# [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread



## Praz

[email protected] 0.98125v---BIOS 0079---HCI---800%/GSAT 2 Hours


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## Secret Dragoon

I'll do this in a bit but I wanted to ask a question

> SOC 1.3v

I have been running SOC 1.25v to get a stable 3.9Ghz w/ 3200Mhz @ 14-14-14-34-1T Timings. What is the safe upper bound on SOC? Gigabyte "claims" that it's safe to set SOC up to 1.35v with air/liquid but every other source claims that you're crazy to go above 1.2v.

My issue is that I am *really close* to getting 4GHz w/ 3600 16-16-16-36-1T but I don't know where I am going wrong. Previously I ran this a single time, but it was very unstable.

This is with the Gaming K7.


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## Silent Scone

Quote:


> Originally Posted by *Secret Dragoon*
> 
> I'll do this in a bit but I wanted to ask a question
> 
> > SOC 1.3v
> 
> I have been running SOC 1.25v to get a stable 3.9Ghz w/ 3200Mhz @ 14-14-14-34-1T Timings. What is the safe upper bound on SOC? Gigabyte "claims" that it's safe to set SOC up to 1.35v with air/liquid but every other source claims that you're crazy to go above 1.2v.
> 
> My issue is that I am *really close* to getting 4GHz w/ 3600 16-16-16-36-1T but I don't know where I am going wrong. Previously I ran this a single time, but it was very unstable.
> 
> This is with the Gaming K7.


I've amended the post, as was going on older information. It's been brought to my attention that anything above 1.2v can be potentially lethal. So your sources are right. It's recommended you do not exceed this voltage.


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## orlfman

If the crosshair is autoing 1.15v for the soc with 2933 and 3200 ratios shouldn't it be safe? i don't see a reason to modify it unless 1.15v's isn't enough. why run lower than the auto soc voltage?

also isn't the greater than 1.2v for the soc crosshair exclusive? since originally asus had a bug that caused soc voltages higher than 1.0v to fry the embed controller on the crosshair. they patched it in 0902. elmor did say in testing up to 1.25v's is fine. anything higher can bring back the motherboard bricking bug of frying the embed controller on the crosshair. he advised 1.2v limit to leave some headroom as 1.25v is the max. so gigabyte might be correct at least for their boards since they might not have the possibility of frying their embedded controllers. i can't recall if amd has released any info publicly about max soc voltages for ryzen.


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## gupsterg

I believe an "Auto rule" in UEFI is bumping SOC on RAM strap change. Not that UEFI "looks up a table" within CPU/SMU and say "hey set x for me".

I had 2x R7 1700, all same hardware :-

i) if UEFI on default and I changed RAM strap to 2400MHz SOC = ~1.050V for both CPU.

ii) if UEFI on default, thus 2133MHz, SOC measured on ProbeIt point for 1st = ~0.838V 2nd = ~0.893V


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## orlfman

Quote:


> Originally Posted by *gupsterg*
> 
> I believe an "Auto rule" in UEFI is bumping SOC on RAM strap change. Not that UEFI "looks up a table" within CPU/SMU and say "hey set x for me".
> 
> I had 2x R7 1700, all same hardware :-
> 
> i) if UEFI on default and I changed RAM strap to 2400MHz SOC = ~1.050V for both CPU.
> 
> ii) if UEFI on default, thus 2133MHz, SOC measured on ProbeIt point for 1st = ~0.838V 2nd = ~0.893V


yeah i've noticed this as well with my 1800x. 2133mhz = ~0.8 - 0.9v's. 2400 = 1.0v. 2933 & 3200 1.15v. 2666mhz i've seen 1.13 - 1.15v. i'm assuming those auto's are perfectly safe for both motherboard and cpu. i doubt asus wants bugs again that will cause more frying of parts after the embed controller fiasco.


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## gupsterg

No idea.

I measure default SOC. Set SOC manually as required, so on remeasure they match stock. Then I up RAM strap and increase SOC as required.

1st R7 1700 2933MHz 14-14-14-14-34-1T VBOOT/VDIMM 1.35V, SOC: ~0.900V needed, could not attain 3200MHz, even with ~1.050V SOC and VCORE increase with offset of +181mV.

2nd R7 1700 3200MHz 14-14-14-34-1T VBOOT/VDIMM 1.35V, SOC: ~0.975V needed.

This was UEFI 1002 or 0902, all same HW except CPU. 1st CPU disposed of, 2nd still not reaching any higher yet. Both could use BCLK of 134MHz with lower RAM strap, with pretty much 0 tweaks to 3.8GHz / BCLK 100MHz profile. Each again attained same 2933MHz/3200MHz.


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## Silent Scone

Quote:


> Originally Posted by *orlfman*
> 
> If the crosshair is autoing 1.15v for the soc with 2933 and 3200 ratios shouldn't it be safe? i don't see a reason to modify it unless 1.15v's isn't enough. why run lower than the auto soc voltage?
> 
> also isn't the greater than 1.2v for the soc crosshair exclusive? since originally asus had a bug that caused soc voltages higher than 1.0v to fry the embed controller on the crosshair. they patched it in 0902. elmor did say in testing up to 1.25v's is fine. anything higher can bring back the motherboard bricking bug of frying the embed controller on the crosshair. he advised 1.2v limit to leave some headroom as 1.25v is the max. so gigabyte might be correct at least for their boards since they might not have the possibility of frying their embedded controllers. i can't recall if amd has released any info publicly about max soc voltages for ryzen.


I don't believe it is exclusive, more a safe limit for the platform if sympathetic and also due to known failures using excessive voltage. What other vendors are saying is up to them, but I'm leaving the recommendation in this thread that 1.2v should not be exceeded, 1.25v maximum.


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## gupsterg

[email protected] 0.975v---BIOS 0082---HCI---400%

W10C, CPU Batch: UA 1709PGT Country: Malaysia.





Spoiler: Above quick run, same settings TPU MemTest64 ~16.5hrs.







Prior to above W7, HCI MemTest ~6hrs/1000%, 7x 2048MB on 0079 but ProcODT as 53.3Ω so is same as 0082.



Spoiler: Warning: Spoiler!


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## Secret Dragoon

I will have to end up trying the Linux Application. Windows doesn't seem to "like" the memtest program too much. Killed my display driver.







.


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## Silent Scone

Quote:


> Originally Posted by *Secret Dragoon*
> 
> I will have to end up trying the Linux Application. Windows doesn't seem to "like" the memtest program too much. Killed my display driver.
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> .


Keep in mind that can be caused by memory instability, but make sure applications such as Afterburner are not open.

Also please can results be submitted in the format noted in the op, thank you


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## hotstocks

I'm running G.skill 3600 C16 2x8 stabily at 3200 14-14-14-34 or 3430 at 16-16-16-36 both require 1.39v and seem to offer the same performance, 3200 is probably better as no bclk shenanigans.


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## Praz

[email protected] 1.00v---BIOS 0079---HCI---475%/GSAT 2.5 Hours

4 x 8GB G.Skill B-Die


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## Silent Scone

Silent [email protected] 0.98v---BIOS 1001---HCI---400%


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## gupsterg

Quote:


> Originally Posted by *Silent Scone*
> 
> Also please can results be submitted in the format noted in the op, thank you


Updated post 10.


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## Silent Scone

Quote:


> Originally Posted by *gupsterg*
> 
> Updated post 10.


Thanks


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## Silent Scone

Quote:


> Originally Posted by *Praz*
> 
> [email protected] 1.00v---BIOS 0079---HCI---475%/GSAT 2.5 Hours
> 
> 4 x 8GB G.Skill B-Die


Aiming for this tomorrow, 3200 has been pretty much P&P so far with the b die modules.


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## orlfman

Quote:


> Originally Posted by *Silent Scone*
> 
> I don't believe it is exclusive, more a safe limit for the platform if sympathetic and also due to known failures using excessive voltage. What other vendors are saying is up to them, but I'm leaving the recommendation in this thread that 1.2v should not be exceeded, 1.25v maximum.


do you have evidence of higher than 1.25v's frying other motherboard embedded controllers though? that's thing because so far its been 100% crosshair only. not even asus prime suffered frying of the emended controller. elmor admitted they didn't see this issue on them. as elmor only stated the 1.2 / 1.25v limit because of it frying the crosshairs embedded controller, not because of it being safe for the "platform" or the processor. i doubt gigabyte is not only stating, but autoing 1.35v's for 3200mhz ratio if it frys their controllers.

don't misunderstand me, i'm skeptical of voltages above the 1.2v, not because of asus and frying the crosshairs controller, but because of how steep of a raise that is from the default 0.8-0.9v's on the soc. the only thing i wish if amd themselves came out stating safe soc voltages for their processors for we can at least know from amd themselves and not this misinformation coming from the manufacturers. like gigabytes 1.35v and asus 1.2v. at least crosshair is concerned, its because you can fry the embedded controller asus uses on it.


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## Spawne32

Quote:


> Originally Posted by *orlfman*
> 
> do you have evidence of higher than 1.25v's frying other motherboard embedded controllers though? that's thing because so far its been 100% crosshair only. not even asus prime suffered frying of the emended controller. elmor admitted they didn't see this issue on them. as elmor only stated the 1.2 / 1.25v limit because of it frying the crosshairs embedded controller, not because of it being safe for the "platform" or the processor. i doubt gigabyte is not only stating, but autoing 1.35v's for 3200mhz ratio if it frys their controllers.
> 
> don't misunderstand me, i'm skeptical of voltages above the 1.2v, not because of asus and frying the crosshairs controller, but because of how steep of a raise that is from the default 0.8-0.9v's on the soc. the only thing i wish if amd themselves came out stating safe soc voltages for their processors for we can at least know from amd themselves and not this misinformation coming from the manufacturers. like gigabytes 1.35v and asus 1.2v. at least crosshair is concerned, its because you can fry the embedded controller asus uses on it.


Are you talking about the DRAM voltage or the Northbridge as it's still called on the MSI boards. Most of the high speed memory seems to be all 1.35v, stock for the NB seems to be floating around 1v.


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## Silent Scone

Quote:


> Originally Posted by *orlfman*
> 
> do you have evidence of higher than 1.25v's frying other motherboard embedded controllers though? that's thing because so far its been 100% crosshair only. not even asus prime suffered frying of the emended controller. elmor admitted they didn't see this issue on them. as elmor only stated the 1.2 / 1.25v limit because of it frying the crosshairs embedded controller, not because of it being safe for the "platform" or the processor. i doubt gigabyte is not only stating, but autoing 1.35v's for 3200mhz ratio if it frys their controllers.
> 
> don't misunderstand me, i'm skeptical of voltages above the 1.2v, not because of asus and frying the crosshairs controller, but because of how steep of a raise that is from the default 0.8-0.9v's on the soc. the only thing i wish if amd themselves came out stating safe soc voltages for their processors for we can at least know from amd themselves and not this misinformation coming from the manufacturers. like gigabytes 1.35v and asus 1.2v. at least crosshair is concerned, its because you can fry the embedded controller asus uses on it.


I've only been using the platform myself for a few days. Different vendors may possibly have experienced different failures, but I've not used Gigabyte on this platform.

Besides which, after spending not much time at all with the CH6, it's pretty evident at least to me that there is no reason to be anywhere near that high.


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## gupsterg

Only my view and opinion based on what I've read and what I've experienced.

2x R7 1700, batch UA 1706PGT (1st CPU) and UA 1709PGT (2nd CPU). 3x RAM kits, CMK8GX4M2A2400C14 , BLS2C4G4D240FSE , F4-3200C14D-16GTZ. Same mobo and rest of HW.

The Corsair kit I could get upto 2666MHz, on 1st CPU I would need SOC 0.900V in UEFI. I would get errors in HCI MemTest, intermittently/variable time periods. Slacking timings, increasing VCORE/SOC/VBOOT&VDIMM did not resolve errors. G.Skill kit 2933MHz not an issue. 3200MHz even with SOC 1.050V in UEFI no go, VCORE upped no go. I have not tried to OC the Crucial kit yet.

2nd CPU I did not try any other RAM yet than G.Skill set. Again increase of SOC using my method of assessing default needed only +100mV.

So I would concur with Silent Scone that we may not need SOC as high as peeps going. IF SOC increase is stabilizing RAM for another perhaps it is masking a non optimal other setting or just the immaturity of platform. As RAM has an effect on Data Fabric clock this is another thing to consider. Perhaps some CPUs do not like this. Perhaps May update will "tweak" this aspect to enable higher RAM use.

The Stilt's share on SOC, link, another post to ref and this one.

So the take away for me is SOC doesn't need to be as high as we may think we need. RAM training is an issue, immaturity of platform and as he states extremely complex training. From having read past posts of The Stilt he has various Ryzen boards and a fair number. He also has Intel, as I've seen his posts where he has said "I will test x and compare".

Then SOC may also be affecting other voltages we are unaware of, link [email protected] Then his post in context of say cold boot vs warm boot.

For me I get occasional cold boot issues on 3200MHz, standby/reboot not an issue. I have thrown Y-Cruncher / x264 / IBT AVX / RB / [email protected] at system many hours and "back to back". One such run was 36hrs+ with these programs. So my failure to cold boot is either a setting I'm over looking or platform immaturity.

Today I plan to retest ProODT, this has been highlighted by Elmor, Praz and [email protected] to aid RAM training.

As I use a PState 0 OC with Offset voltage to CPU on a failed memory training boot there is a "quirk". AMD CBS resets, Extreme Tweaker does not. Then as CPU is in "Default Mode" PB/XFR is active even when UEFI loaded. My R7 1700 uses ~1.35V in these higher states, throw in the +162mV offset I use = ~1.5V.

Screenshot of UEFI and getting ~1.5V is in this post, it is not just UEFI reporting 1.5V I have checked with DMM on ProbeIt point. Solution for this at present, for me is this.


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## Praz

Quote:


> Originally Posted by *Silent Scone*
> 
> Aiming for this tomorrow, 3200 has been pretty much P&P so far with the b die modules.


Hello

Plug n' play is a good thing considering the limited settings AMD has decided to expose.

Quote:


> Originally Posted by *gupsterg*
> 
> So I would concur with Silent Scone that we may not need SOC as high as peeps going. IF SOC increase is stabilizing RAM for another perhaps it is masking a non optimal other setting or just the immaturity of platform.


Hello

Currently needing 1.2V SOC voltage and above is representative of a very bad CPU overclocking sample or as you note more likely a workaround for something amiss at the board level. Recommending or auto setting upward of 1.35V is both ludicrous and irresponsible.


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## gupsterg

@Praz

+rep, thanks for shares







.


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## Silent Scone

Silent [email protected] 1.03v---BIOS 0079---HCI---500%


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## lordzed83

I find time Ill post full screenshot of running linuks one.


Hci free is pain in the ass to start up so moved to beter in my opinion TPU Memtest.


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## Silent Scone

The pro version can be setup easily if you are finding it a chore. That's an interesting pair of screenshots.


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## spyshagg

I had degradation to the point of failure on a kit of CMK16GX4M2B3000C15 2x8GB ddr4 3000 while running XMP profile with an older BIOS on Asus Prime b350 +

The XMP worked right of the bat. But this past this past week the computer started BSODING more and more often and now every 10 minutes.

- I proceeded to install the latest BIOS which auto-detected the RAM as 3000mhz without need of XMP. The BSODS persisted.

- I proceeded to downclock the ram to 2133mhz without success.

- I proceeded to remove one of the sticks for a quick diagnosis and the bsods have stopped. Its a workstation so I cannot test it further, but it appears one of the sticks has indeed gradually deteriorated.


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## lordzed83

Quote:


> Originally Posted by *Silent Scone*
> 
> The pro version can be setup easily if you are finding it a chore. That's an interesting pair of screenshots.




Thats my daily setup iw been using for few weeks. 3605hmz same volts stable ect BUT with 135.xmhz i cant use pstate oc so no downlocking and since its 3200cl16 kit 3605 works stable as u see at cl18 and ran few benchmarks.... 3605 cl18 is TINY BIT slower than 3472 cl16.
Since my cpu is poor 4ghz impossible anything above 3940 does not pass IBT Max x 3. At lest IMC is good in my chip







.

Anyhow one more this is 3605 run over time i was at work 9 hours on windows 8.1 that i swaped 5820k over without format or anything. Stable system is stable







I had to tweek w10 for 12 hours tog et same benchmark scores as on 8.1 lol


Also ill add this:


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## Silent Scone

Silent [email protected] 1.1v---BIOS 0079---HCI---600%


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## madweazl

madweazl -- [email protected] -- 3498Mhz - C16-16-16-36-1t -- 1.425 -- SOC 1.156 -- BIOS 0082 -- HCI -- 400% +


Spoiler: Warning: Spoiler!



https://flic.kr/p/TV6GEx



RAM slightly higher but CPU clocked slightly lower (cant remember why I did this now but I doubt there is any stability differences between the two runs)


Spoiler: Warning: Spoiler!



https://flic.kr/p/SXVgWC


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## bl1tzk1213g

Any tips on getting 3200mhz on taichi board? Cpu voltage 1.35, Dram voltage 1.35, SOC voltage 1.15v (up to 1.2), 2933 is my best with 14-14-14-34 timings. Can't post on 3200 even with loose timings. CPU is 1700 by the way. What's the highest bclk I can use without compromising my NVME ssd?


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## hsn

hsn [email protected] 1v---BIOS 003---HCI---500%
GSKILL F4-3200C14-8GTZSW


Spoiler: Warning: Spoiler!


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## Silent Scone

^ Nice results, thanks for sharing









Silent Scone[email protected] 1.15v---BIOS 079---HCI---400%


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## MrPerforations

Quote:


> Originally Posted by *bl1tzk1213g*
> 
> Any tips on getting 3200mhz on taichi board? Cpu voltage 1.35, Dram voltage 1.35, SOC voltage 1.15v (up to 1.2), 2933 is my best with 14-14-14-34 timings. Can't post on 3200 even with loose timings. CPU is 1700 by the way. What's the highest bclk I can use without compromising my NVME ssd?


I cant answer about the nvme drive, but as I noted yesterday, pci-e 3.0 slots down clock themselves when not working on 3d.
mine sits at pci-e 1.1 when not working and then pci-e 3.0 when working in full screen.
I have a feeling the pci-e speed changing with bus clocking might be down to human error?
I would say test, but as you say it might ruin your ssd contents.


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## gupsterg

@Silent Scone

+rep for share, nice result







. BTW everytime I view the OP table, my OCD kicks in, that my 1700 is shown as 7000, any chance of change? cheers







.


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## Praz

Hello

There are some good results being posted in this thread. Good job everyone.


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## nesham

The same probel I had few days ago. I byed another kit but that another cant work @3000 but max is 2600 at same voltage as first kit. I wil see what max frequency will be with RMA replacment kit.


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## madweazl

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> There are some good results being posted in this thread. Good job everyone.


But AMD memory support is turble!


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## Praz

Hello

[email protected] 0.98125v---BIOS 0003---HCI---500%/GSAT 2 Hours


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## Silent Scone

Quote:


> Originally Posted by *gupsterg*
> 
> @Silent Scone
> 
> +rep for share, nice result
> 
> 
> 
> 
> 
> 
> 
> . BTW everytime I view the OP table, my OCD kicks in, that my 1700 is shown as 7000, any chance of change? cheers
> 
> 
> 
> 
> 
> 
> 
> .


My bad, will amend
Quote:


> Originally Posted by *madweazl*
> 
> But AMD memory support is turble!


Support, and what the platform is capable of (with the right modules) are two different things


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## Spawne32

I am still befuddled about getting my vengeance LPX 3000 to boot at anything beyond 2667 in the MSI B350M with the latest bios, seems no one on the MSI forums with the same board is able to get anything better either.


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## gupsterg

[email protected] 0.975v---BIOS 0081---HCI---3500% -3800%

ProcODT: 53.3Ω

CPU Batch: UA 1709PGT Country: Malaysia



AIDA64 14-14-14-14-34-1T vs 14-13-13-13-34-1T



Asus MemTweakIt compare 14-14-14-14-34-1T vs 14-13-13-13-34-1T



CBR15 was no improvement in bench results, as expected from minute RAM tweak. Going to use 14-13-13-34-1T as "daily driver"







.


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## Silent Scone

Quote:


> Originally Posted by *Spawne32*
> 
> I am still befuddled about getting my vengeance LPX 3000 to boot at anything beyond 2667 in the MSI B350M with the latest bios, seems no one on the MSI forums with the same board is able to get anything better either.


Not sure on the MSI side, might have to contact them for an update.
Quote:


> Originally Posted by *gupsterg*
> 
> [email protected] 0.975v---BIOS 0081---HCI---3500% -3800%
> 
> ProcODT: 53.3Ω
> 
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 
> 
> AIDA64 14-14-14-14-34-1T vs 14-13-13-13-34-1T
> 
> 
> 
> Asus MemTweakIt compare 14-14-14-14-34-1T vs 14-13-13-13-34-1T
> 
> 
> 
> 
> 
> CBR15 was no improvement in bench results, as expected from minute RAM tweak. Going to use 14-13-13-34-1T as "daily driver"
> 
> 
> 
> 
> 
> 
> 
> .


Nice Gup, thanks again rep+


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## gupsterg

No thank you for taking the time to do thread/be OP







. Added this thread to my thread/sig







.


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## Silent Scone

I've added memory kits to the table, given the current state of the platform I think it's beneficial. If possible please specify what kit the result was achieved with.


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## madweazl

Quote:


> Originally Posted by *Silent Scone*
> 
> I've added memory kits to the table, given the current state of the platform I think it's beneficial. If possible please specify what kit the result was achieved with.


F4-3200C14D-16GTZR

Edit: and my RGB still works!


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## Silent Scone

Thanks, always a bonus


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## gupsterg

F4-3200C14D-16GTZ, non RGB







.


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## fragamemnon

Do you accept different chipsets?









I am running 4x4GB G.Skill something-something sticks rated for 2133 @ 2666MHz on a B350 chipset and so far they work like a champ. I might try 2933 later.


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## Silent Scone

Quote:


> Originally Posted by *fragamemnon*
> 
> Do you accept different chipsets?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I am running 4x4GB G.Skill something-something sticks rated for 2133 @ 2666MHz on a B350 chipset and so far they work like a champ. I might try 2933 later.


Yes, 350 is fine. Just post up the results


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## fragamemnon

Currently at about 300% of MemTest. I will edit this post once done.

First run on those sticks, just plug and play (there will be more to come







):


Spoiler: R7 1700 @ 3750MHz, AsRock AB350 Pro4, 4x4GB Crucial CT4G4DFS8213 @ 2666-16-17-17


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## gtbtk

Quote:


> Originally Posted by *Spawne32*
> 
> I am still befuddled about getting my vengeance LPX 3000 to boot at anything beyond 2667 in the MSI B350M with the latest bios, seems no one on the MSI forums with the same board is able to get anything better either.


this may help


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## madweazl

When you're stuck at work and make the wife send you an update...

Should be up over 1000% by the time I get home


Spoiler: Warning: Spoiler!



https://flic.kr/p/UhNt7M


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## Praz

Quote:


> Originally Posted by *Silent Scone*
> 
> I've added memory kits to the table, given the current state of the platform I think it's beneficial. If possible please specify what kit the result was achieved with.


Hello

The 2 x 8GB and 4 x 8GB entries are F4-3600C15D-16GTZ kits. 2 x 16GB are F4-3600C17D-32GTZKW. It might be a good idea to emphasis the need of running as many instances of HCI as there are CPU threads so the processor is fully loaded during testing.


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## Silent Scone

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> The 2 x 8GB and 4 x 8GB entries are F4-3600C15D-16GTZ kits. 2 x 16GB are F4-3600C17D-32GTZKW. It might be a good idea to emphasis the need of running as many instances of HCI as there are CPU threads so the processor is fully loaded during testing.


Ok, cool.

Yes, I've noticed some above are aiming for one instance per core, which obviously is not as strenuous. Please can submissions have one instance per THREAD not CORE, thanks


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## madweazl

Quote:


> Originally Posted by *Silent Scone*
> 
> Ok, cool.
> 
> Yes, I've noticed some above are aiming for one instance per core, which obviously is not as strenuous. Please can submissions have one instance per THREAD not CORE, thanks


Ahh, OK. I didn't realize this stressed the CPU differently (doesn't make any sense to me but I'm game).


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## Silent Scone

If it made no difference, there would be no need to do an instance per core, either









One per thread is pretty brutal, which is the idea. You want to load up the bus as much as possible


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## madweazl

Quote:


> Originally Posted by *Silent Scone*
> 
> If it made no difference, there would be no need to do an instance per core, either
> 
> 
> 
> 
> 
> 
> 
> 
> 
> One per thread is pretty brutal, which is the idea. You want to load up the bus as much as possible


I looked at is as physical vs logical cores. Gives me something else to monkey around with when I get home though


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## madweazl

Update to my previous results:

16-15-15-36 -- 800%

https://flic.kr/p/UipUwK


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## Silent Scone

Thanks, nice one!


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## gtbtk

@Silent Scone Could I please make a suggestion for your thread before it gets too large and unweildly. Great thread by the way. I think that it would be a useful thing to be able to reference and it will show up the current state of the art combinations of memory kit, timing configuration and settings to use to maximize performance for 16GB, 32GB and 64GB systems.

Could you please collect Aida64 Memory latency result that everyone is attaining with the particular memory over clock so It can be recorded and differences between the various configurations compared.

A second thing that would be useful is a standard benchmark result such as a link to the 3dmark web page of the Firestrike result that was obtained with that overclock. The combined score is fairly indicative of how the PC will work in a gaming scenario. As Ram support and configs have gotten better from launch, Ryzen machines were getting combined scores of about 6000. Recent results are getting to the a bit over 8000. I assume that is with Chews 120mhz Refclk method but without something like this database you are compiling, it is only that. An assumption. Meanwhile, 7700K/6900K machines have been scoring in the 9000-1000 range.

I am suggesting firestrike because it can be run from the demo version as opposed to the Timespy CPU result that has become quite popular around here as that requires everyone to have a paid copy of the software which may not always be possible.


----------



## kaseki

Quote:


> Originally Posted by *Praz*
> 
> Quote:
> 
> 
> 
> Originally Posted by *Silent Scone*
> 
> I've added memory kits to the table, given the current state of the platform I think it's beneficial. If possible please specify what kit the result was achieved with.
> 
> 
> 
> Hello
> 
> The 2 x 8GB and 4 x 8GB entries are F4-3600C15D-16GTZ kits. 2 x 16GB are F4-3600C17D-32GTZKW. It might be a good idea to emphasis the need of running as many instances of HCI as there are CPU threads so the processor is fully loaded during testing.
Click to expand...

Yikes, and I thought I finally understood G. Skill terminology. Shouldn't a 4 x 8GB TridentZ kit use a Q instead of a D and be denoted F4-ffffCttQ-32GTZcc, where ffff is the transfer rate, tt is the first timing value, and cc is the color code (assuming such a kit exists)? If two 2 x 8GB D-kits are used, then it would be best to add a "2X" somewhere to clarify that they weren't factory matched.


----------



## Praz

Quote:


> Originally Posted by *kaseki*
> 
> Yikes, and I thought I finally understood G. Skill terminology. Shouldn't a 4 x 8GB TridentZ kit use a Q instead of a D and be denoted F4-ffffCttQ-32GTZcc, where ffff is the transfer rate, tt is the first timing value, and cc is the color code (assuming such a kit exists)? If two 2 x 8GB D-kits are used, then it would be best to add a "2X" somewhere to clarify that they weren't factory matched.


Hello

Seems to clear enough to me. Looking up the part number shows it to be a 2 module kit. I don't think it takes a lot of thought to deduce that 4 modules would require the combining of 2 kits.


----------



## Silent Scone

Quote:


> Originally Posted by *gtbtk*
> 
> @Silent Scone
> Could I please make a suggestion for your thread before it gets too large and unweildly. Great thread by the way. I think that it would be a useful thing to be able to reference and it will show up the current state of the art combinations of memory kit, timing configuration and settings to use to maximize performance for 16GB, 32GB and 64GB systems.
> 
> Could you please collect Aida64 Memory latency result that everyone is attaining with the particular memory over clock so It can be recorded and differences between the various configurations compared.
> 
> A second thing that would be useful is a standard benchmark result such as a link to the 3dmark web page of the Firestrike result that was obtained with that overclock. The combined score is fairly indicative of how the PC will work in a gaming scenario. As Ram support and configs have gotten better from launch, Ryzen machines were getting combined scores of about 6000. Recent results are getting to the a bit over 8000. I assume that is with Chews 120mhz Refclk method but without something like this database you are compiling, it is only that. An assumption. Meanwhile, 7700K/6900K machines have been scoring in the 9000-1000 range.
> 
> I am suggesting firestrike because it can be run from the demo version as opposed to the Timespy CPU result that has become quite popular around here as that requires everyone to have a paid copy of the software which may not always be possible.


Thanks, but wouldn't want it to get unwieldy. If people can obtain the settings they're using and wanting to compare, it only takes a few minutes.


----------



## gtbtk

Quote:


> Originally Posted by *Silent Scone*
> 
> Quote:
> 
> 
> 
> Originally Posted by *gtbtk*
> 
> @Silent Scone
> Could I please make a suggestion for your thread before it gets too large and unweildly. Great thread by the way. I think that it would be a useful thing to be able to reference and it will show up the current state of the art combinations of memory kit, timing configuration and settings to use to maximize performance for 16GB, 32GB and 64GB systems.
> 
> Could you please collect Aida64 Memory latency result that everyone is attaining with the particular memory over clock so It can be recorded and differences between the various configurations compared.
> 
> A second thing that would be useful is a standard benchmark result such as a link to the 3dmark web page of the Firestrike result that was obtained with that overclock. The combined score is fairly indicative of how the PC will work in a gaming scenario. As Ram support and configs have gotten better from launch, Ryzen machines were getting combined scores of about 6000. Recent results are getting to the a bit over 8000. I assume that is with Chews 120mhz Refclk method but without something like this database you are compiling, it is only that. An assumption. Meanwhile, 7700K/6900K machines have been scoring in the 9000-1000 range.
> 
> I am suggesting firestrike because it can be run from the demo version as opposed to the Timespy CPU result that has become quite popular around here as that requires everyone to have a paid copy of the software which may not always be possible.
> 
> 
> 
> Thanks, but wouldn't want it to get unwieldy. If people can obtain the settings they're using and wanting to compare, it only takes a few minutes.
Click to expand...

when I say unwieldy, i am talking about a list of 50-60-70 people and trying to go back and collect additional data after they have already submitted the results. As the list only has about 10 it is not too bad. Gups latency with his 14-13-13-13 timings was 62.5ns which is the best I have seen to date. If 62ns can be matches with a fps score

I am just asking for you to expand your requested format from:

Silent [email protected] 1.2v---BIOS 0902---HCI---400%

to

Silent [email protected] 1.2v---BIOS 0902---HCI---400%*---62.5ns---http://3dmark/firestrike/resultsurl/* and add the extra column to the spreadsheet


----------



## Praz

Hello

The results of all these additional proposed benchmarks are dependent on more than just the set primary timings and memory speed. Unless one digs deep into the BIOS to lock in settings, which some boards will not even have access to, the results don't really have a meaningful value in regards to memory performance. This would as well be an unnecessary burden to place on the user for submitting to this thread. For the more curious this type of testing could be done by the individual which would also provide more realistic results for the system in question assuming the proper settings were used for the various memory configurations.


----------



## madweazl

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> The results of all these additional proposed benchmarks are dependent on more than just the set primary timings and memory speed. Unless one digs deep into the BIOS to lock in settings, which some boards will not even have access to, the results don't really have a meaningful value in regards to memory performance. This would as well be an unnecessary burden to place on the user for submitting to this thread. For the more curious this type of testing could be done by the individual which would also provide more realistic results for the system in question assuming the proper settings were used for the various memory configurations.


Agreed; when you start running FS etc you can make huge gains with core and memory clock speeds that may not be possible depending on the individuals GPU. Too many variables to be useful in regard to RAM in my opinion. The AIDA results seem reasonable since it's a memory bench.


----------



## Silent Scone

Yep, although FS CPU Physics is quite a memory sensitive test, there are too many variables to account for and has the potential to lead users up the garden path.


----------



## gtbtk

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> The results of all these additional proposed benchmarks are dependent on more than just the set primary timings and memory speed. Unless one digs deep into the BIOS to lock in settings, which some boards will not even have access to, the results don't really have a meaningful value in regards to memory performance. This would as well be an unnecessary burden to place on the user for submitting to this thread. For the more curious this type of testing could be done by the individual which would also provide more realistic results for the system in question assuming the proper settings were used for the various memory configurations.


Firestrike is an excellent tool for our purposes and was the reason that I have been so vocal that it is not the windows scheduler or CCX thread switching as the primary cause of the performance issues (yes there is a small amount of latency added when threads switch but that is symptomatic of the low memory frequency and high memory latency. You don't use it in this situation looking at absolute numbers. The total score really doesn't mean much for out purposes, You use the balance of the individual component scores to identify trends.

FS Graphics scores for a given GPU all fall within a reasonably small range for that particular model of card eg a GTX 1070 will run roughly about 19000 stock and about 21000 when overclocked, give or take. That remains true on both Intel and Ryzen systems. That test Loads the GPU without stressing the CPU very much

FS Physics scores likewise tracks the CPU frequency/IPC pretty consistently for both Intel and Ryzen. At the same clocks, an R7 and a 6900K will both roughly sore about the same physics score. That has been true since release of the Ryzen CPUs. This test stresses the CPU and puts minimal load on the GPU. If it was thread switching causing the major part of the problem, you would see it impacting the physics score as well but both brands of CPU tend to track each other quite well. The 6900K only pulls ahead if it is overclocked above about 4.1Ghz.

The FS combined score demonstrates where the performance is being impacted. That is in the part of the system between the cores and the GPU itself that has to run double duty supporting both GPU and CPU related memory traffic and traffic between the CPU and the GPU over PCIe. 6900K will do a 9000-10000 Combined score and the R7 and R5 Ryzens have, until the recent memory OC breakthroughs, was stuck at the 6000-6500 level. Since 3200 c14 single rank speeds became a reality, The best scores are now at around 8500 which is almost matching the Intel equivalent chip. Dual Rank memory with the extra interleaving also seems to help the performance as well.

If a score of 10000 pops up, we then have the chance of analyzing what is happening on that system that no-one else is doing


----------



## Silent Scone

Quote:


> Originally Posted by *gtbtk*
> 
> Firestrike is an excellent tool for our purposes and was the reason that I have been so vocal that it is not the windows scheduler or CCX thread switching as the primary cause of the performance issues (yes there is a small amount of latency added when threads switch but that is symptomatic of the low memory frequency and high memory latency. You don't use it in this situation looking at absolute numbers. The total score really doesn't mean much for out purposes, You use the balance of the individual component scores to identify trends.
> 
> FS Graphics scores for a given GPU all fall within a reasonably small range for that particular model of card eg a GTX 1070 will run roughly about 19000 stock and about 21000 when overclocked, give or take. That remains true on both Intel and Ryzen systems. That test Loads the GPU without stressing the CPU very much
> 
> FS Physics scores likewise tracks the CPU frequency/IPC pretty consistently for both Intel and Ryzen. At the same clocks, an R7 and a 6900K will both roughly sore about the same physics score. That has been true since release of the Ryzen CPUs. This test stresses the CPU and puts minimal load on the GPU. If it was thread switching causing the major part of the problem, you would see it impacting the physics score as well but both brands of CPU tend to track each other quite well. The 6900K only pulls ahead if it is overclocked above about 4.1Ghz.
> 
> The FS combined score demonstrates where the performance is being impacted. That is in the part of the system between the cores and the GPU itself that has to run double duty supporting both GPU and CPU related memory traffic and traffic between the CPU and the GPU over PCIe. 6900K will do a 9000-10000 Combined score and the R7 and R5 Ryzens have, until the recent memory OC breakthroughs, was stuck at the 6000-6500 level. Since 3200 c14 single rank speeds became a reality, The best scores are now at around 8500 which is almost matching the Intel equivalent chip. Dual Rank memory with the extra interleaving also seems to help the performance as well.
> 
> If a score of 10000 pops up, we then have the chance of analyzing what is happening on that system that no-one else is doing


Being forthright, you need to let that go. Furthermore, this is a stability thread. If you want to start a thread comparing 3DMark scores you can do so yourself, however, there is already one in the graphics section.


----------



## gupsterg

@gtbtk

See this post 6 runs of 2133MHz vs 3200MHz. "We" can only control primary timings, the rest are dictated by strap.



Due to nature of this thread, happy to discuss there my results







.


----------



## Praz

Quote:


> Originally Posted by *gtbtk*
> 
> Firestrike is an excellent tool for our purposes and was the reason that I have been so vocal that it is not the windows scheduler or CCX thread switching as the primary cause of the performance issues (yes there is a small amount of latency added when threads switch but that is symptomatic of the low memory frequency and high memory latency. You don't use it in this situation looking at absolute numbers. The total score really doesn't mean much for out purposes, You use the balance of the individual component scores to identify trends.
> 
> FS Graphics scores for a given GPU all fall within a reasonably small range for that particular model of card eg a GTX 1070 will run roughly about 19000 stock and about 21000 when overclocked, give or take. That remains true on both Intel and Ryzen systems. That test Loads the GPU without stressing the CPU very much
> 
> FS Physics scores likewise tracks the CPU frequency/IPC pretty consistently for both Intel and Ryzen. At the same clocks, an R7 and a 6900K will both roughly sore about the same physics score. That has been true since release of the Ryzen CPUs. This test stresses the CPU and puts minimal load on the GPU. If it was thread switching causing the major part of the problem, you would see it impacting the physics score as well but both brands of CPU tend to track each other quite well. The 6900K only pulls ahead if it is overclocked above about 4.1Ghz.
> 
> The FS combined score demonstrates where the performance is being impacted. That is in the part of the system between the cores and the GPU itself that has to run double duty supporting both GPU and CPU related memory traffic and traffic between the CPU and the GPU over PCIe. 6900K will do a 9000-10000 Combined score and the R7 and R5 Ryzens have, until the recent memory OC breakthroughs, was stuck at the 6000-6500 level. Since 3200 c14 single rank speeds became a reality, The best scores are now at around 8500 which is almost matching the Intel equivalent chip. Dual Rank memory with the extra interleaving also seems to help the performance as well.
> 
> If a score of 10000 pops up, we then have the chance of analyzing what is happening on that system that no-one else is doing


Hello

That was quite a wall of text considering as stated previously it is irrelevant to this thread.


----------



## gtbtk

Quote:


> Originally Posted by *Silent Scone*
> 
> Quote:
> 
> 
> 
> Originally Posted by *gtbtk*
> 
> Firestrike is an excellent tool for our purposes and was the reason that I have been so vocal that it is not the windows scheduler or CCX thread switching as the primary cause of the performance issues (yes there is a small amount of latency added when threads switch but that is symptomatic of the low memory frequency and high memory latency. You don't use it in this situation looking at absolute numbers. The total score really doesn't mean much for out purposes, You use the balance of the individual component scores to identify trends.
> 
> FS Graphics scores for a given GPU all fall within a reasonably small range for that particular model of card eg a GTX 1070 will run roughly about 19000 stock and about 21000 when overclocked, give or take. That remains true on both Intel and Ryzen systems. That test Loads the GPU without stressing the CPU very much
> 
> FS Physics scores likewise tracks the CPU frequency/IPC pretty consistently for both Intel and Ryzen. At the same clocks, an R7 and a 6900K will both roughly sore about the same physics score. That has been true since release of the Ryzen CPUs. This test stresses the CPU and puts minimal load on the GPU. If it was thread switching causing the major part of the problem, you would see it impacting the physics score as well but both brands of CPU tend to track each other quite well. The 6900K only pulls ahead if it is overclocked above about 4.1Ghz.
> 
> The FS combined score demonstrates where the performance is being impacted. That is in the part of the system between the cores and the GPU itself that has to run double duty supporting both GPU and CPU related memory traffic and traffic between the CPU and the GPU over PCIe. 6900K will do a 9000-10000 Combined score and the R7 and R5 Ryzens have, until the recent memory OC breakthroughs, was stuck at the 6000-6500 level. Since 3200 c14 single rank speeds became a reality, The best scores are now at around 8500 which is almost matching the Intel equivalent chip. Dual Rank memory with the extra interleaving also seems to help the performance as well.
> 
> If a score of 10000 pops up, we then have the chance of analyzing what is happening on that system that no-one else is doing
> 
> 
> 
> Being forthright, you need to let that go. Furthermore, this is a stability thread. If you want to start a thread comparing 3DMark scores you can do so yourself, however, there is already one in the graphics section.
Click to expand...

This thread, and overclocking in general is not only about stability, it is about stability with the best performance. If you only want stability then you should be running your ram at 2133 with default timings and you don't need this thread in the first place. All I and suggesting is for you guys to list the latency results you get from the Stirling efforts that you are making. You are generally testing for it anyway.

If you also add a firestrike score to the work that you are already doing, YOU guys get to see an additional data point, together with super Pi numbers that will show YOU what are the best methods to use to get the best stability and performance out of this new system. You may even find things that you don't expect like dual rank performance vs single rank performance. Does the extra interleaving give better benefits than single rank frequency and tight timings? I don't know for certain, but there is some evidence that suggest that there might be something to it if the top scores that have been posted at 2400 and 2666Mhz were not a fluke.


----------



## colorfuel

[email protected] 1.0v---BIOS F3---HCI---500%

edit: F4-3200C14D-16GFX

Just testing the standard XMP profile settings for this 16GB G.Skill Flare X kit on stock CPU clocks.

On my Gigabyte K7, it sometimes takes a few reboots to train the setting, but it has proven stable until now.

I have to manually set the SOC voltage to 1.0, on auto, this board gives the SOC 1.25v, which, apparently, is too much.


----------



## Silent Scone

Quote:


> Originally Posted by *colorfuel*
> 
> [email protected] 1.0v---BIOS F3---HCI---500%
> 
> Just testing the standard XMP profile settings for this 16GB G.Skill Flare X kit on stock CPU clocks.
> 
> On my Gigabyte K7, it sometimes takes a few reboots to train the setting, but it has proven stable until now.
> 
> I have to manually set the SOC voltage to 1.0, on auto, this board gives the SOC 1.25v, which, apparently, is too much.


If stable at 1v for that frequency, then 1.25v is excessive, yes.

Great result


----------



## Nighthog

[email protected] 0.9v---BIOS F6---HCI---1000%

CPU VCORE: 1.500V
Gigabyte GA-AB350-Gaming 3

CL 14.15.13.(13).24.62.312 2T
CMK16GX4M2A2666C16R ver 3.21 Micron 2Rx8


----------



## haszek

Not sure if this would be enough, 4x8gb 3200 but on samsung e-die, tried 16-18-18 but failed : / cl18 is working so might try now to lower voltages and check again

[email protected] 1.15v---BIOS 1107---HCI---220%


----------



## Silent Scone

Quote:


> Originally Posted by *haszek*
> 
> Not sure if this would be enough, 4x8gb 3200 but on samsung e-die, tried 16-18-18 but failed : / cl18 is working so might try now to lower voltages and check again
> 
> [email protected] 1.15v---BIOS 1107---HCI---220%


Thanks, it's enough - as minimal coverage for 32GB is 200%. At least enough for entry. With densities above 16GB I would recommend using Google Stress App


----------



## haszek

Quote:


> Originally Posted by *haszek*
> 
> Not sure if this would be enough, 4x8gb 3200 but on samsung e-die, tried 16-18-18 but failed : / cl18 is working so might try now to lower voltages and check again
> 
> [email protected] 1.15v---BIOS 1107---HCI---220%


Test went through at 1.4v but every windows restart was resetting pstates due to failed boot. Only 1.45v DDR boot and 1.44v DDR voltage helped to make it stable.


----------



## Praz

Hello

Regarding additional testing methodology for this thread I think this screenshot says it all. From stable settings SOC voltage was slightly lowered and termination resistance bumped up one step to increase signal reflection. MemTest64 successfully completed one hour using all available memory. HCI produced an error after approximately 14 minute.


----------



## gtbtk

you may find this an interesting read

https://www.micron.com/resource-details/297e5bfa-6f92-4471-9b84-22b1ee76482d


----------



## Silent Scone

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> Regarding additional testing methodology for this thread I think this screenshot says it all. From stable settings SOC voltage was slightly lowered and termination resistance bumped up one step to increase signal reflection. MemTest64 successfully completed one hour using all available memory. HCI produced an error after approximately 14 minute.


This is good to know. Was considering adding this test to the roster, but I'm really not convinced it is needed. Both tests in the thread when used are more than enough if on the right path


----------



## drdrache

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> Regarding additional testing methodology for this thread I think this screenshot says it all. From stable settings SOC voltage was slightly lowered and termination resistance bumped up one step to increase signal reflection. MemTest64 successfully completed one hour using all available memory. HCI produced an error after approximately 14 minute.


This is difficult to understand, maybe you can explain it.

you purposely set bad settings, to prove that one software will fail and one will not? that's a single instance failure - 100% unreliable.


----------



## Silent Scone

Quote:


> Originally Posted by *drdrache*
> 
> This is difficult to understand, maybe you can explain it.
> 
> you purposely set bad settings, to prove that one software will fail and one will not? that's a single instance failure - 100% unreliable.


Really?

An error in that little coverage with HCI versus an entire hour of looping. Quite a disparity there...15% with that much memory is no more than 5 minutes.

100% unreliable indeed. If the metric for 100% is a whole hour







lol. Memory errors are memory errors, regardless of how many instances fail.


----------



## drdrache

Quote:


> Originally Posted by *Silent Scone*
> 
> Really?
> 
> An error in that little coverage with HCI versus an entire hour of looping. Quite a disparity there...15% with that much memory is no more than 5 minutes.
> 
> 100% unreliable indeed. If the metric for 100% is a whole hour
> 
> 
> 
> 
> 
> 
> 
> lol. Memory errors are memory errors, regardless of how many instances fail.


100% unreliable because you tested a SINGLE situation; not time. did you test the same settings with GSTA? my point is, it's incorrect in any testing to
throw out a tool because it failed ONCE.

HCI is great because it's been tested and refined over a long time; but your testing does it no favors, you might as well said "because I said so, it sucks"
because that's how reliable a single test is. bad methods are bad methods, regardless of the desired outcome.


----------



## Praz

Quote:


> Originally Posted by *drdrache*
> 
> 100% unreliable because you tested a SINGLE situation; not time. did you test the same settings with GSTA? my point is, it's incorrect in any testing to
> throw out a tool because it failed ONCE.
> 
> HCI is great because it's been tested and refined over a long time; but your testing does it no favors, you might as well said "because I said so, it sucks"
> because that's how reliable a single test is. bad methods are bad methods, regardless of the desired outcome.


Hello

You think I set up everything that was in that screenshot on the off chance the utility would fail? After seeing the same results numerous times I decided to do a direct comparison in the screenshot I posted. And yes GSAT failed also. To try to call out purposely setting a memory configuration that would fail makes no sense to me. Those known non-stable settings resulting in the successful passing of the utility puts it in an even worse light. But everyone is free to use whatever testing method they choose. If passing a given stability testing utility when similar utilities fail eases one's mind when claiming stability by all means it should be used by that individual. As the two options given in this thread for submission have been in your own words " tested and refined over a long time" there is no need to include a third of questionable reliability.


----------



## spyshagg

My Asus B350 Prime is no longer stable with dual channel memory (two sticks). But each stick works well individually.

Damaged Board or Damaged cpu controller?


----------



## Silent Scone

That's the thing with testing memory, a "single" situation is detecting errors. You could maybe understand the argument if Praz ran HCI for ample coverage over many hours and found a single error. However, it only needed to be run for 15 minutes

A good testing methodology includes various tests, yes, but if test X is finding errors in a few minutes where test Y isn't in an hour of looping then it's stringency is bound to come into question.


----------



## madweazl

@Silent Scone, we were chatting in the C6H specific thread and I had mentioned that I'd never had a memory overclock pass a specific setting in IBT (10 runs @maximum setting) and subsequently fail in HCI. Well, I was able to make that happen this afternoon. While IBT was running, I noticed what what was probably a WHEA error (I didn't have HWiNFO running at the time but started it right after trying to catch another) around the 3rd run in IBT and figured it would be a great time to actually test that statement further (first time this has happened and I've run a bunch of them). Sure enough, HCI failed and it was fairly early. These settings were destined to fail as they're lower than what I achieved stability on at 16-15-15-36 but the opportunity was there.

https://flic.kr/p/T9EMWm


----------



## Silent Scone

So the only change you made was tRAS?


----------



## madweazl

Quote:


> Originally Posted by *Silent Scone*
> 
> So the only change you made was tRAS?


No, there were a couple other settings that were lower as I was attempting something else and was lazy with the needed voltages. It just supported your thoughts that IBT probably wasn't a good measure of stability in relation to the comments in MSI's video.

On a positive note, I was able to improve my settings a little further.

16-15-15-34 1000% (all else the same as initial results but PLL at 1.94v)

Edit: settings are actually slightly different:

madweazl -- [email protected] -- 3502Mhz-C16-15-15-34-1T -- 1.425v -- SOC 1.15v -- 0082 -- HCI 1000 %

https://flic.kr/p/Ta29Fs


----------



## glnn_23

glnn_23 - 1700 @3.8 -- 3605MHz-C16-15-15-42-1T - 1.42v - SOC 1.1125v - Bios 1002 - HCI - 900%

Voltages as set in Bios.

Memory used. F4-4266C19D-16GTZA


----------



## Silent Scone

Quote:


> Originally Posted by *glnn_23*
> 
> glnn_23 - 1700 @3.8 -- 3605MHz-C16-15-15-42-1T - 1.42v - SOC 1.1125v - Bios 1002 - HCI - 900%
> 
> Voltages as set in Bios.
> 
> Memory used. F4-4266C19D-16GTZA


Nice work. Those sticks coming in handy on other platforms I see








Quote:


> Originally Posted by *madweazl*
> 
> No, there were a couple other settings that were lower as I was attempting something else and was lazy with the needed voltages. It just supported your thoughts that IBT probably wasn't a good measure of stability in relation to the comments in MSI's video.
> 
> On a positive note, I was able to improve my settings a little further.
> 
> 16-15-15-34 1000% (all else the same as initial results but PLL at 1.94v)
> 
> Edit: settings are actually slightly different:
> 
> madweazl -- [email protected] -- 3502Mhz-C16-15-15-34-1T -- 1.425v -- SOC 1.15v -- 0082 -- HCI 1000 %
> 
> https://flic.kr/p/Ta29Fs


On the Intel side with DDR4 the two tests in the op are hard to beat for testing memory. It's not bound to be much different here







. Stress App even more so than HCI at isolating the memory sub system, if you can take the time to install the OS.


----------



## gargiulo5000

AMD said "Improvement for the Hynix ram in may"
Well there you go may.
Where are the improvements?


----------



## Silent Scone

Quote:


> Originally Posted by *gargiulo5000*
> 
> AMD said "Improvement for the Hynix ram in may"
> Well there you go may.
> Where are the improvements?


It's only the 3rd. If you want to post gripes I'd suggest doing it on AMDs own message boards.


----------



## g3kiganger3

Quote:


> Originally Posted by *hotstocks*
> 
> I'm running G.skill 3600 C16 2x8 stabily at 3200 14-14-14-34 or 3430 at 16-16-16-36 both require 1.39v and seem to offer the same performance, 3200 is probably better as no bclk shenanigans.


I have these exact sticks and can only get them to go to 3374 via bclk 140x 2666 profile.

Could you tell me how you got this?


----------



## Praz

Hello

[email protected] 1.10v---BIOS 1107---HCI---800%/GSAT 2 Hours---F4-3600C15D-16GTZ (2 Kits)


----------



## Silent Scone

Thanks, Praz.

I've since added the requirement of specifying the memory kit for results format. Anything else is welcome to be posted but not compulsory


----------



## colorfuel

@Silent Scone:

I've added the kit to my post:

[email protected] 1.0v---BIOS F3---HCI---500%-F4-3200C14D-16GFX


----------



## Silent Scone

Thanks!


----------



## Praz

Quote:


> Originally Posted by *Silent Scone*
> 
> Thanks, Praz.
> 
> I've since added the requirement of specifying the memory kit for results format. Anything else is welcome to be posted but not compulsory


Hello

Done.


----------



## haszek

That would be my updated 4x8GB:

[email protected] 1.10v---BIOS 1107---HCI---310%

Kit CMU32GX4M4C3466C16


----------



## hsn

hsn [email protected] 1.1v---BIOS 1107---HCI---500%
GSKILL F4-3200C14-8GTZSW


----------



## Silent Scone

Nice work


----------



## Bloke

Bloke - [email protected] - 3200MHz 16-15-15-36 T1 1.35V - SoC 1.1V - bios 0609 - HCI 1200% - G.Skill F4-3200C14D-16GFX


----------



## gupsterg

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> [email protected] 1.10v---BIOS 1107---HCI---800%/GSAT 2 Hours---F4-3600C17D-32GTZ
> 
> 
> 
> Spoiler: Warning: Spoiler!


+rep, thx







.

ProcODT value? cheers







.


----------



## Praz

Quote:


> Originally Posted by *gupsterg*
> 
> +rep, thx
> 
> 
> 
> 
> 
> 
> 
> .
> 
> ProcODT value? cheers
> 
> 
> 
> 
> 
> 
> 
> .


Hello

ProcODT is set to 43.6Ω.


----------



## rossctr

rossctr - R5 1600 @ 3.8 - 3400MHz 14-14-14-34-1T @ 1.35v - SoC @ 1.0v - C6H BIOS 1107 - HCI 400% - F4-3600C17-8GTZR



Not tried for anything higher yet


----------



## Bloke

Updated post #106


----------



## Silent Scone

Thanks, some nice results being posted. Hopefully, the next big update will bring about some improvements.


----------



## mus1mus

Old run. Micron action.

32GB 4*8GB
F4-2400C15-8GRK
VDIMM - 1.35

R7-1700X @ 3.9
VSOC - 1.04V
VCore 1.3

Gigabyte AX370-K7
BIOS F3D Beta



Also


Spoiler: Wasn't able to capture a run with these


----------



## Silent Scone

All recent results added









Quote:


> Originally Posted by *fragamemnon*
> 
> Currently at about 300% of MemTest. I will edit this post once done.
> 
> First run on those sticks, just plug and play (there will be more to come
> 
> 
> 
> 
> 
> 
> 
> ):
> 
> 
> Spoiler: R7 1700 @ 3750MHz, AsRock AB350 Pro4, 4x4GB Crucial CT4G4DFS8213 @ 2666-16-17-17


Can you let me know the SOC voltage, please.


----------



## bluej511

Anyone in here use memtest64 by techpowerup to test for RAM stability? Curious to how it does to other memory testing.


----------



## Silent Scone

Quote:


> Originally Posted by *bluej511*
> 
> Anyone in here use memtest64 by techpowerup to test for RAM stability? Curious to how it does to other memory testing.


It's good to use multiple tools, hence more than one option in the OP. Whether you use those and more is entirely up to you, it certainly doesn't hurt. I've found it to be fairly inconsistent personally.

Praz also posted this earlier in the thread:

http://www.overclock.net/t/1628751/official-amd-ryzen-ddr4-24-7-memory-stability-thread/80_40#post_26062075


----------



## bluej511

Quote:


> Originally Posted by *Silent Scone*
> 
> It's good to use multiple tools, hence more than one option in the OP. Whether you use those and more is entirely up to you, it certainly doesn't hurt. I've found it to be fairly inconsistent personally.
> 
> Praz also posted this earlier in the thread:
> 
> http://www.overclock.net/t/1628751/official-amd-ryzen-ddr4-24-7-memory-stability-thread/80_40#post_26062075


Ran memtest as well 8x1750mb, gave me about 14gb test usage, had 1gb left over. 100-105% coverage gave me 0 errors as well both seem to work pretty well. Then again its not like my ram speed and timings are aggressive.







+rep for the help.

My settings FYI.
Corsair CMK16GX4M2B3200C16 Ver 5.39 2x8gb
DRAM voltage: 1.35
DRAM boot voltage: 1.35
SoC: 1.0v
Timings: 16-16-16-36
Strap 3200mhz
Crosshair VI 1107
[email protected]

Here she is at 400%, zero errors same as memtest64. Memtest64 used quite a bite more ram pretty much pinging it to 99.9%.


----------



## gupsterg

Personally I'd roll with HCI MemTest or GSAT.

I've used TPU MemTest64 once only. As another member in another thread said what passed HCI MemTest 1hr+ failed TPU MemTest64 within minutes. For me what had passed HCI MemTest also passed TPU MemTest64.

Even if your not using aggressive timings or OC'ing your RAM I reckon doing a HCI MemTest is still a good test to do for various reasons.


----------



## Praz

Quote:


> Originally Posted by *bluej511*
> 
> Here she is at 400%, zero errors same as memtest64. Memtest64 used quite a bite more ram pretty much pinging it to 99.9%.


Hello

The amount of ram usage with HCI is set by the user. I'm not seeing how Memtest64 using more ram in comparison is really relevant.


----------



## bluej511

Quote:


> Originally Posted by *gupsterg*
> 
> Personally I'd roll with HCI MemTest or GSAT.
> 
> I've used TPU MemTest64 once only. As another member in another thread said what passed HCI MemTest 1hr+ failed TPU MemTest64 within minutes. For me what had passed HCI MemTest also passed TPU MemTest64.
> 
> Even if your not using aggressive timings or OC'ing your RAM I reckon doing a HCI MemTest is still a good test to do for various reasons.


Yea i edited my post and got a nice 400% coverage run in.
Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> The amount of ram usage with HCI is set by the user. I'm not seeing how Memtest64 using more ram in comparison is really relevant.


One does it automatically and one doesnt, worth noting isn't it?


----------



## gupsterg

Quote:


> Originally Posted by *bluej511*
> 
> One does it automatically and one doesnt, worth noting isn't it?


Sorta of.

MemTest64 has MAX / Presets in drop down box. HCI MemTest on FOC version "we" have a bit more fiddling to do, but Pro version does open x windows, etc.

It's just that HCI MemTest is "established" test method







, I don't doubt MemTest64 is not good but it may not yet be as good as other tests







. I could be completely wrong as well







. I reckon I gonna do a GSAT run as well soon







.


----------



## gargiulo5000

Any news for the may big updates for ram compatibility and clocking?


----------



## Silent Scone

Quote:


> Originally Posted by *gargiulo5000*
> 
> Any news for the may big updates for ram compatibility and clocking?


Next update is due in roughly a fortnight, I believe. You're best off checking that information on the AMD forum or ask in the CH6 thread. Link in my signature.


----------



## os2wiz

Quote:


> Originally Posted by *bl1tzk1213g*
> 
> Any tips on getting 3200mhz on taichi board? Cpu voltage 1.35, Dram voltage 1.35, SOC voltage 1.15v (up to 1.2), 2933 is my best with 14-14-14-34 timings. Can't post on 3200 even with loose timings. CPU is 1700 by the way. What's the highest bclk I can use without compromising my NVME ssd?


It is a terrible idea to push SOC voltage past 1.10 volts. For the most part it is a fruitless strategy that in the end can damage your cpu.


----------



## bluej511

Quote:


> Originally Posted by *os2wiz*
> 
> It is a terrible idea to push SOC voltage past 1.10 volts. For the most part it is a fruitless strategy that in the end can damage your cpu.


I don't understand where you come up with these useless posts.

There has been PLENTY of people who have needed 1.1-1.25 soc voltage to stabilize a system, and no, in the end it can't damage your cpu. SoC voltage is board related not cpu related, hence why it helps stabilizing memory and/or oc.

https://en.wikipedia.org/wiki/System_on_a_chip


----------



## TahoeDust

I'm working on helping my buddy overclock the ram on his 1600x Asus Prime X370 Pro system. He has A g.Skill F4-3200C16D-16GVKB kit. Can anyone recommend a good starting point? He is gunning for 3200MHz.


----------



## bluej511

Quote:


> Originally Posted by *TahoeDust*
> 
> I'm working on helping my buddy overclock the ram on his 1600x Asus Prime X370 Pro system. He has A g.Skill F4-3200C16D-16GVKB kit. Can anyone recommend a good starting point? He is gunning for 3200MHz.


Start with RAM first before doing an OC, good place to start is DOCP standard to see if it even works. There seems to be an issue with memory at 3200mhz on some peoples CPU, a work around is to use bclk at 101 or above and it would theoretically give you slightly over 3200mhz and may fix the memory hole bug, should be 3232 with bclk at 101.


----------



## TahoeDust

Quote:


> Originally Posted by *bluej511*
> 
> Start with RAM first before doing an OC, good place to start is DOCP standard to see if it even works. There seems to be an issue with memory at 3200mhz on some peoples CPU, a work around is to use bclk at 101 or above and it would theoretically give you slightly over 3200mhz and may fix the memory hole bug, should be 3232 with bclk at 101.


Just realized that is actually Samsung D-Die ram...Not sure what we'll be able to get out of it.


----------



## Silent Scone

Quote:


> Originally Posted by *os2wiz*
> 
> It is a terrible idea to push SOC voltage past 1.10 volts. For the most part it is a fruitless strategy that in the end can damage your cpu.


That's a little reserved. Some more can be needed for the top tier frequencies.


----------



## meRlinXAT

Hallo,

will buy the MSI B350 Gaming Pro Carbon with
- G.Skill RipJaws V schwarz DIMM Kit 16GB, DDR4-3200, CL14-14-14-34 (F4-3200C14D-16GVK)
or
- G.Skill Flare X schwarz DIMM Kit 16GB, DDR4-3200, CL14-14-14-34 (F4-3200C14D-16GFX)

or ... did you think maybe G.Skill RipJaws V schwarz DIMM Kit 16GB, DDR4-3600, CL16-16-16-36 (F4-3600C16D-16GVK) are worth it and possible to reach on this board?

thanks

greetz


----------



## Silent Scone

Quote:


> Originally Posted by *meRlinXAT*
> 
> Hallo,
> 
> will buy the MSI B350 Gaming Pro Carbon with
> - G.Skill RipJaws V schwarz DIMM Kit 16GB, DDR4-3200, CL14-14-14-34 (F4-3200C14D-16GVK)
> or
> - G.Skill Flare X schwarz DIMM Kit 16GB, DDR4-3200, CL14-14-14-34 (F4-3200C14D-16GFX)
> 
> or ... did you think maybe G.Skill RipJaws V schwarz DIMM Kit 16GB, DDR4-3600, CL16-16-16-36 (F4-3600C16D-16GVK) are worth it and possible to reach on this board?
> 
> thanks
> 
> greetz


Stick with the Flare X kit.


----------



## yendor

Quote:


> Originally Posted by *meRlinXAT*
> 
> Hallo,
> 
> will buy the MSI B350 Gaming Pro Carbon with
> - G.Skill RipJaws V schwarz DIMM Kit 16GB, DDR4-3200, CL14-14-14-34 (F4-3200C14D-16GVK)
> or
> - G.Skill Flare X schwarz DIMM Kit 16GB, DDR4-3200, CL14-14-14-34 (F4-3200C14D-16GFX)
> 
> or ... did you think maybe G.Skill RipJaws V schwarz DIMM Kit 16GB, DDR4-3600, CL16-16-16-36 (F4-3600C16D-16GVK) are worth it and possible to reach on this board?
> 
> thanks
> 
> greetz


probably same ic's for 3600 ripjaws and flare x 3200 kits...

3600 not currently possible on non refclock board.

flare x xmp profile has better chance to work at 3200

Same speed possible on all 3 kits at the end of the day.

cl14 gskill at 3200 - most likely bdie regardless of "brand" flare x certainly

cl16 gskill at 3600 - bdie


----------



## chrisjames61

Quote:


> Originally Posted by *bluej511*
> 
> I don't understand where you come up with these useless posts.


I guess the same place he came up with this- "Technology is NOT a liberator . Whom technology serves is a class question. Technology wielded by the capitalist class benefits only the exploiters. Technology wielded by the working class will benefit all of humanity."

Strange.


----------



## bluej511

So gave it another go, ran 14-16-16-16-36 and had errors within 2mins in HCI at 1.35v, changed it to 1.45 and 400% coverage (a bit more so they're all over 400% haha) and 0 errors. You gurus think i may be able to drop to 14-15-15-15-34 or should be fine the way it is now? Granted this was a 16-18-18-18-36 rated stick so its an improvement already for sure.


----------



## Silent Scone

Maybe. You'll have to run it and find out. Not sure why you bumped the DRAM voltage so much, though


----------



## bluej511

Quote:


> Originally Posted by *Silent Scone*
> 
> Maybe. You'll have to run it and find out. Not sure why you bumped the DRAM voltage so much, though


Well i figured 1.35v failed almost within 2mins, got to like 20% coverage maybe if that and going from 16 to 14 cl right away wasn't sure it would make it. I figured if i want to do 14-15-15-15-34 eventually it might have to go that high.


----------



## yendor

Quote:


> Originally Posted by *bluej511*
> 
> Well i figured 1.35v failed almost within 2mins, got to like 20% coverage maybe if that and going from 16 to 14 cl right away wasn't sure it would make it. I figured if i want to do 14-15-15-15-34 eventually it might have to go that high.


Anecdotally, people have run for extended periods as high as 1.5 on ddr4 without apparent issue since it's been available for intel platforms.
Personally higher voltage on a kit has let me get tighter timings to run and even cold boot where lower voltages fail training.


----------



## bluej511

Quote:


> Originally Posted by *yendor*
> 
> Anecdotally, people have run for extended periods as high as 1.5 on ddr4 without apparent issue since it's been available for intel platforms.
> Personally higher voltage on a kit has let me get tighter timings to run and even cold boot where lower voltages fail training.


Heat isn't even an issue for me, i have a core x5 cube case my intake fan is right above both ram sticks so its getting ambient air all the time.


----------



## Jpmboy

jpmboy --- [email protected] --- 3466 14-15-15-39-1T w/ 1.40VDIMM --- SOC 1.10V -- ODT Auto --- GSkill 4266c19 2x8GB kit 1 hour GSAT
moved my better 3600c15 kit back to z270 where it belongs was too long on this side of the tracks











(hopefully you accept BASH GSAT.. I can assure you it finds errors.







)


----------



## Silent Scone

Quote:


> Originally Posted by *Jpmboy*
> 
> jpmboy --- [email protected] --- 3466 14-15-15-39-1T w/ 1.40VDIMM --- SOC 1.10V -- ODT Auto --- GSkill 4266c19 2x8GB kit 1 hour GSAT
> moved my better 3600c15 kit back to z270 where it belongs was too long on this side of the tracks
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> (hopefully you accept BASH GSAT.. I can assure you it finds errors.
> 
> 
> 
> 
> 
> 
> 
> )


Welcome to the red side


----------



## mus1mus

RED Slide.


----------



## bluej511

[email protected] on Crosshair 6 BIOS [email protected] 1.45v dram-1.0v SoC-Prodoct auto- Corsair CMK16GX4M2B3200C162x8gb-HCI 700% coverage.


----------



## Jpmboy

Quote:


> Originally Posted by *Silent Scone*
> 
> Welcome to the red side


I think AMD's ram guys were on strike when this architecture was designed.


----------



## yendor

Quote:


> Originally Posted by *Jpmboy*
> 
> I think AMD's ram guys were on strike when this architecture was designed.


imc has not been an amd strong point... ever, that I can recall...


----------



## Clukos

New BIOS, AGESA 1.0.0.6, lower timings and sub-timings 3466 14-14-14-34, looks stable so far:










All the settings I've used:

3466CL14_settings.txt 19k .txt file


----------



## Silent Scone

Given the lack of uptake of using GSAT here, now accepting W10 entries. Please be sure to check the test is assigning the correct amount of memory, or assign the amount manually with the argument -M

[email protected] 1.10v---BIOS 9945---W10GSAT 2 Hours---G.SKILL F4-3200C14Q-32GTZ

Probeit:

VCORE: 1.355
SOC: 1.1
DRAM 1.365
PLL 1.791


----------



## Praz

Quote:


> Originally Posted by *Silent Scone*
> 
> Given the lack of uptake of using GSAT here, now accepting W10 entries. Please be sure to check the test is assigning the correct amount of memory, or assign the amount manually with the argument -M
> 
> [email protected] 1.10v---BIOS 9945---W10GSAT 2 Hours---G.SKILL F4-3200C14Q-32GTZ
> 
> Probeit:
> 
> VCORE: 1.355
> SOC: 1.1
> DRAM 1.365
> PLL 1.791
> 
> 
> Spoiler: Warning: Spoiler!


Hello

As a group the mindset of AMD users are on a different level that Intel users. To provide motivation may require even more changes for this thread compared to the extremely successful Intel memory stability thread.


----------



## Silent Scone

I think you're right to an extent there. A lot of users seem to be content with simply seeing what boots and what they can run conditionally


----------



## yendor

Quote:


> Originally Posted by *Silent Scone*
> 
> I think you're right to an extent there. A lot of them seem to be content with simply seeing what boots and what they can run conditionally


You scared them off by suggesting they install linux. hallo usb drivers....

Just stumbled over the thread. Been testing memory all along. Looks like I have some reading to do


----------



## finalheaven

Using 4 dimms/sticks (4x8GB - 32GB) Samsung B-Die
2 sets of G.Skill F4-3200C14D-16GTZ

Bios *9943 AGESA 1.0.0.6*
1700 @ *3.8Ghz* (P-State Overclock)
Default refclk/blck
CPU Offset @ *+0.075v*
SOC @ *1.05v*
DDR @ *1.40v* [may be able to decrease]

*3466 @ 15-15-15-15-35-2T (4x8GB)*
Geardown set to Disabled (to use odd CL# and 2T)

These are the only settings that I have changed other than skew offset to disabled.



Will be testing the above settings again with lower DDR voltages.


----------



## Silent Scone

Quote:


> Originally Posted by *yendor*
> 
> You scared them off by suggesting they install linux. hallo usb drivers....
> 
> Just stumbled over the thread. Been testing memory all along. Looks like I have some reading to do


I will add the bash install to the OP. Now that higher density is possible, running stress app test for an hour first saves time.


----------



## finalheaven

*Update*: Was able to pass HCI Memtest with DDR @ *1.38v*.

Using 4 dimms/sticks (4x8GB - 32GB) Samsung B-Die
2 sets of G.Skill F4-3200C14D-16GTZ

Bios using *AGESA 1.0.0.6*
1700 @ *3.8Ghz* (P-State Overclock)
Default *100.6* REFCLK/BCLK
CPU Offset @ *+0.075v*
SOC @ *1.05v*
DDR @ *1.38v*

*3466 @ 15-15-15-15-35-2T (4x8GB)*
Geardown set to Disabled (to use odd CL# and 2T)

I'm probably done with testing for a while. Satisfied with being able to get to 3466 fully stable with 32GB of ram with above settings.


----------



## Silent Scone

Quote:


> Originally Posted by *finalheaven*
> 
> *Update*: Was able to pass HCI Memtest with DDR @ *1.38v*.
> 
> Using 4 dimms/sticks (4x8GB - 32GB) Samsung B-Die
> 2 sets of G.Skill F4-3200C14D-16GTZ
> 
> Bios using *AGESA 1.0.0.6*
> 1700 @ *3.8Ghz* (P-State Overclock)
> Default *100.6* REFCLK/BCLK
> CPU Offset @ *+0.075v*
> SOC @ *1.05v*
> DDR @ *1.38v*
> 
> *3466 @ 15-15-15-15-35-2T (4x8GB)*
> Geardown set to Disabled (to use odd CL# and 2T)
> 
> I'm probably done with testing for a while. Satisfied with being able to get to 3466 fully stable with 32GB of ram with above settings.


Yes that's a good config for this platform, have you tried 1T?


----------



## finalheaven

Quote:


> Originally Posted by *Silent Scone*
> 
> Yes that's a good config for this platform, have you tried 1T?


1T (@ 14-14-14-34) is a no go. Can't boot up cold (after shutdown) from it. So I didn't even bother.


----------



## Silent Scone

Quote:


> Originally Posted by *finalheaven*
> 
> 1T (@ 14-14-14-34) is a no go. Can't boot up cold (after shutdown) from it. So I didn't even bother.


Fair enough, you could dial that out with some work most likely. Speeds above 3200 with 4 DIMMs at 1T might well be difficult for some CPU, will find out as time goes on.


----------



## finalheaven

Quote:


> Originally Posted by *Silent Scone*
> 
> Fair enough, you could dial that out with some work most likely. Speeds above 3200 with 4 DIMMs at 1T might well be difficult for some CPU, will find out as time goes on.


Indeed. Trust me I tried all configs. 15-15-15-35 was the only stable setting after memtest. I can boot with 14-14-14-34-1T @ 3466 and run apps. Just was not stable.


----------



## gupsterg

Updated post 10 & 43 with CPU batch/country.

[email protected] 1.05v---BIOS 9943---HCI---4000%--F4-3200C14D-16GTZ

ProcODT: [Auto] (UEFI 9943 on that value will use AMD "training" to set value) CPU Batch: UA 1713PGT Country: Malaysia





@Silent Scone

You may recall our discussions on my rig not reaching higher than say 2933MHz or 3200MHz depending on which CPU I used. And I highlighted I tried BCLK/Lower straps/ProcODT, etc, etc. I stated "And are "we" saying training failure has nothing to do with firmware?" in this post.

So CPU sample 3 was stuck at ~2933MHz strap prior to UEFI 9943,I could with some BCLK tweaking coax 3126MHz. With UEFI 9943 using strap 3066MHz 14-13-13-13-34-1T was possible with VBOOT/VDIMM: 1.35V SOC: 0.975V. 3200MHz strap did not work (will try The Stilt's/Elmor's posted info in C6H) and ProcODT/Fail_CNT, etc stock.

So to me it is clear that previously it was not my hardware or settings/methods used but firmware restricting what I could gain







.


----------



## Silent Scone

Nice work









Replied to your duplicate post in the CH6 thread


----------



## Clukos

Tightening down timings with the new BIOS and it seems to be successful:










Primary and sub-timings:










Raising tRFC to a more reasonable value has been very successful for my config, I used the values given by the Jedec standard for 2133 which is slightly higher than what AMD gives at stock.


----------



## gupsterg

Quote:


> Originally Posted by *Silent Scone*
> 
> Nice work
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Replied to your duplicate post in the CH6 thread


Thanks







and thanks for the reply there to discuss







.

Now testing 3466MHz with what I regard the runt of 3x R7 1700s







. UEFI 9943/AGESA 1.0.0.6 seems to be what we should have had launch







. Still some issues I have seen but the best all round firmware so far it seems to me







. Glad I didn't splurge on another C6H/RAM or CPU. I feel confident that it's not MOBO/RAM holding me back, more to do with firmware and next settings plus somewhat CPU sample.

I hope we see more activity in this thread







, so big thanks to all participating/sharing







.


----------



## gupsterg

As a compare to my other CPU in post 43. This CPU did not do 3200MHz strap on this UEFI, adjusting CLDO_VDDP to 956mV made the memory hole disappear.

[email protected] 1.00v---BIOS 9943---HCI---1000%--F4-3200C14D-16GTZ

ProcODT: [Auto] (53.3Ω assumed in UEFI 9943) CPU Batch: UA 1713PGT Country: Malaysia




So on this CPU/UEFI scaling has been:-

2933MHz (SOC: 0.975V) 14-13-13-13-34-1T
3066MHz (SOC: 0.975V) 14-13-13-13-34-1T
3200MHz (SOC: 1.000V + CLDO_VDDP to 956mV) 14-13-13-13-34-1T
3333MHz (SOC: 1.050V) 16-15-15-15-36-1T
3466MHz (SOC: 1.075V) 16-15-15-15-36-1T

(Note: I only do SOC in 25mV increments, so could be tweaked finer)

ProcODT: [Auto], VBOOT/VDIMM 1.35V, CPU offset for 3.8GHz +206mV, PLL/SB etc defaults, all cases. Gonna aim to do 3600MHz if I can before swapping to another CPU, it gonna need a CLDO_VDDP adjustment IMO as that is insta Q-Code: F9 like 3200MHz was before on same UEFI.


----------



## Praz

Hello

[email protected] 1.15v---BIOS 9943---HCI---1450%---F4-3600C15D-16GTZ


----------



## Silent Scone

Nice ^


----------



## Jpmboy

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> [email protected] 1.15v---BIOS 9943---HCI---1450%---F4-3600C15D-16GTZ


Praz- did you have to putz with cldo_vddp?


----------



## Praz

Quote:


> Originally Posted by *Jpmboy*
> 
> Praz- did you have to putz with cldo_vddp?


Hello

CLDO_VDDP is set to auto. All changed settings are in the screenshot.


----------



## Jpmboy

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> CLDO_VDDP is set to auto. All changed settings are in the screenshot.


thanks. this 4266c19 will boot the same but unstable. My 3600c15 kit is in another rig ATM (z270 - where it belongs







)


----------



## finalheaven

Do any of you guys have this issue:

I can pass HCI at 3466 with 32gb, but it will not pass Y-Cruncher (the HNT: Hybrid NTT) test. Increasing CPU volt, SOC volt, and DDR volt does not make it stable.

However, if I use only 16gb of ram, it'll pass Y-Cruncher easily. Can't explain it.


----------



## Silent Scone

Quote:


> Originally Posted by *finalheaven*
> 
> Do any of you guys have this issue:
> 
> I can pass HCI at 3466 with 32gb, but it will not pass Y-Cruncher (the HNT: Hybrid NTT) test. Increasing CPU volt, SOC volt, and DDR volt does not make it stable.
> 
> However, if I use only 16gb of ram, it'll pass Y-Cruncher easily. Can't explain it.


Check the 32gb configuration with 2 hours of GSAT


----------



## gupsterg

Quote:


> Originally Posted by *finalheaven*
> 
> Do any of you guys have this issue:
> 
> I can pass HCI at 3466 with 32gb, but it will not pass Y-Cruncher (the HNT: Hybrid NTT) test. Increasing CPU volt, SOC volt, and DDR volt does not make it stable.
> 
> However, if I use only 16gb of ram, it'll pass Y-Cruncher easily. Can't explain it.


Yep have this issue.

3200MHz which was a memory hole on this CPU has passed Y-Cruncher/IBT AVX on same settings as HCI Memtest.

3333MHz has passed ~4hrs Y-Cruncher as HCI Memtest settings, IBT AVX has failed loop 2 of 5 within a run







. Gonna tweak setup for 3333MHz strap, then that experience may help to sort 3466MHz which passed HCI Memtest but not Y-Cruncher/IBT AVX.


----------



## finalheaven

Quote:


> Originally Posted by *Silent Scone*
> 
> Check the 32gb configuration with 2 hours of GSAT


Will try GSAT when I get the chance. But passed 300-400% on HCI with 32gb so figured it should be stable. Not sure why it's failing Y-Cruncher with 32gb and pass on 16b.
Quote:


> Originally Posted by *gupsterg*
> 
> Yep have this issue.
> 
> 3200MHz which was a memory hole on this CPU has passed Y-Cruncher/IBT AVX on same settings as HCI Memtest.
> 
> 3333MHz has passed ~4hrs Y-Cruncher as HCI Memtest settings, IBT AVX has failed loop 2 of 5 within a run
> 
> 
> 
> 
> 
> 
> 
> . Gonna tweak setup for 3333MHz strap, then that experience may help to sort 3466MHz which passed HCI Memtest but not Y-Cruncher/IBT AVX.


My CPU has a memory hole at 3333. CPU cannot boot up cold (from shutdown) at 3466 CL14, but boots up cold at 3466 CL15. Cannot boot up cold at 3600 either. However, 3600 does boot up via restart after changing bios.

Do you know whether CLDO_VDDP or ProcODT may assist in passing stress tests? Thought those values were only to make it boot up.


----------



## Jpmboy

Quote:


> Originally Posted by *finalheaven*
> 
> Do any of you guys have this issue:
> 
> I can pass HCI at 3466 with 32gb, but it will not pass Y-Cruncher (the HNT: Hybrid NTT) test. Increasing CPU volt, SOC volt, and DDR volt does not make it stable.
> 
> However, if I use only 16gb of ram, it'll pass Y-Cruncher easily. Can't explain it.


Check the cpu/die and dimm temps during y-cruncher compared to HCI memtest. y-cruncher (hwbot versions) heats things up more than HCi (maybe not IBT tho) So you may be getting thermally-induced errors.\

and I still can't get 3600 c-anything to perform better that this:


----------



## gupsterg

For me adjusting CPU VCORE/SOC for IBT AVX stability on custom 13312MB vs HCI Memtest/Y-Cruncher run is working on 3333MHz 16-15-15-15-1T 1.35V. HCI Memtest/Y-Cruncher was +206mV VCORE for 3.8GHz and SOC 1.05V for 3333MHz 16-15-15-15-1T 1.35V.

As I got tired of changing combos of:-

i) ProcODT

ii) CLDO_VDDP

iii) Looser tRFC (all 3 values)

And combos of above 3. I initially went +250mV VCORE and 1.2V SOC to pass IBT AVX 10 loops. Now I'm down to +250mV / 1.1V and testing +225mV VCORE.


----------



## Silent Scone

I doubt we'll be seeing sub timings as tight as what can be achieved on BWE. Personally haven't taken the time to try yet.


----------



## gupsterg

BWE above my pay grade, so no experience







. I couldn't even stomach spending on a i7 vs i5 with Intel TBH.

So to wrap up my stability issue with 3333MHz 16-15-15-15-34-1T on IBT AVX vs HCI Memtest/Y-Cruncher settings I needed VCORE +237mV / SOC 1.075V vs +206mv / 1.05V. Anyone wanting the long version/processes I went through follow trail from this post over there.

Next sorting 3466MHz for IBT AVX, did pass HCI Memtest / Y-Crunch on Sunday, but failed IBT AVX that day.


----------



## Jpmboy

Quote:


> Originally Posted by *Silent Scone*
> 
> I doubt we'll be seeing sub timings as tight as what can be achieved on BWE. Personally haven't taken the time to try yet.


BWE, HWE and certainly not near SKL or KBL. (stay strong buddy)
Quote:


> Originally Posted by *gupsterg*
> 
> BWE above my pay grade, so no experience
> 
> 
> 
> 
> 
> 
> 
> . I couldn't even stomach spending on a i7 vs i5 with Intel TBH.
> 
> So to wrap up my stability issue with 3333MHz 16-15-15-15-34-1T on IBT AVX vs HCI Memtest/Y-Cruncher settings I needed VCORE +237mV / SOC 1.075V vs +206mv / 1.05V. Anyone wanting the long version/processes I went through follow trail from this post over there.
> 
> Next sorting 3466MHz for IBT AVX, did pass HCI Memtest / Y-Crunch on Sunday, but failed IBT AVX that day.


I'm not a blue or red fanboi, Thing is tho, a 5+GHz 7700K is tough for any CPU to top in anything but the most thread-intensive tasks (if you don;t mind delidding the damn thing. Both brands have their serious issues)


----------



## finalheaven

Ok so I solved my weird problem. I passed 300% with HCI on 32GB (4x8) 3466 15-15-15-35-2T using:

CPU @ +0.075v offset
SOC @ 1.05v
DDR @ 1.38v

However, I could not even pass two iterations of Y-Cruncher. So I took out 2 of the sticks and tested with 16GB. This passed Y-Cruncher with ease.

Then using 32GB again, I attempted to raise my CPU and SOC volts like crazy to try and reach stability. However, in the end, all I needed was a lot more DDR volt. I passed 10 iterations of Y-Cruncher with:

CPU @ +0.075v offset
SOC @ 1.075v
DDR @ 1.43v

I didn't think that Y-Cruncher (the HNT : Hybrid NTT especially) would need more ram voltage than HCI memtest. Nor that 4 sticks would require that much more voltage than 2 sticks.


----------



## mus1mus

HCI is not soo hard for the Cores as the suggestion is really aimed towards the Memory.

HNT really loves VCore anyways.


----------



## Silent Scone

Quote:


> Originally Posted by *finalheaven*
> 
> Ok so I solved my weird problem. I passed 300% with HCI on 32GB (4x8) 3466 15-15-15-35-2T using:
> 
> CPU @ +0.075v offset
> SOC @ 1.05v
> DDR @ 1.38v
> 
> However, I could not even pass two iterations of Y-Cruncher. So I took out 2 of the sticks and tested with 16GB. This passed Y-Cruncher with ease.
> 
> Then using 32GB again, I attempted to raise my CPU and SOC volts like crazy to try and reach stability. However, in the end, all I needed was a lot more DDR volt. I passed 10 iterations of Y-Cruncher with:
> 
> CPU @ +0.075v offset
> SOC @ 1.075v
> DDR @ 1.43v
> 
> I didn't think that Y-Cruncher (the HNT : Hybrid NTT especially) would need more ram voltage than HCI memtest. Nor that 4 sticks would require that much more voltage than 2 sticks.


Simply running GSAT would have caused you to come to the same conclusion


----------



## finalheaven

Quote:


> Originally Posted by *mus1mus*
> 
> HCI is not soo hard for the Cores as the suggestion is really aimed towards the Memory.
> 
> HNT really loves VCore anyways.


Problem wasn't my vcore at all though. HNT stressed my memory more than HCI.
Quote:


> Originally Posted by *Silent Scone*
> 
> Simply running GSAT would have caused you to come to the same conclusion


Yea it appears HCI isn't too great. Wish there was a native GSAT app for windows though. I figure it can't be too difficult for someone to make it? I didn't want to even do the work around to install bash on windows.


----------



## Spectre-

Running HOF 4000 @ 3500mhz 18-18-18-38- 1T 2000% on memtest86 and 12 hours of prime Blend stable

DRAM vol- 1.4
Soc- 1.1
VDDP- 0.72

Cant run anything above 3600 due to weak IMC


----------



## Spectre-

EDIT DOUBLE POST


----------



## gupsterg

@Jpmboy

Not fan boi of either here TBH as well. Agree 5GHz+ 7700K is hard to beat but damn AMD really come out with something good. Really impressed on boot times now, just due to AGESA improvements. I recall X99 having gripes on ROG forum in this regard even with maturity. Then TBH I'm ~3mths in on ownership and platform has improved well.

I did ~13 reboots yesterday fiddling with 3333MHz for IBT AVX stability pass setup and had no Q-Code: F9. Shutdown PC last night and started today and all sweet. What I regard as the better CPU, even on AGESA 1.0.0.4 I was having rare intermittent Q-Code: F9 on 3200MHz. So I reckon that will be sweet now and hope gain some more RAM MHz on AGESA 1.0.0.6.

@finalheaven

Installing bash is not a biggie. I'm moving to GSAT today for 3466MHz, then see what IBT AVX does. Great to read you solved your issue, thanks for share







.


----------



## mus1mus

Quote:


> Originally Posted by *finalheaven*
> 
> Problem wasn't my vcore at all though. HNT stressed my memory more than HCI.


While I agree that HNT stress is hard for the RAM, I have not experienced it fail on an HCI stable set-up. Something else is doing that.

If your VCore was previously tuned for a lower memory speed, jumping to 3466 will require more. Based from exp.


----------



## Silent Scone

Quote:


> Originally Posted by *finalheaven*
> 
> Problem wasn't my vcore at all though. HNT stressed my memory more than HCI.
> Yea it appears HCI isn't too great. Wish there was a native GSAT app for windows though. I figure it can't be too difficult for someone to make it? I didn't want to even do the work around to install bash on windows.


Both tests have their uses, but I don't think anything hits the memory subsystem as hard as GSAT does. [email protected] pretty much said it all in the Skylake overclocking overview on discovery. Google use this to stress test the memory stability of their servers, nothing else really needs to be said about it's credentials


----------



## gupsterg

[email protected] 1.075v---BIOS 9943---Stressapptest---1hr--F4-3200C14D-16GTZ

CPU R7 1700 Batch: 1713PGT (Malaysia)

ProcODT: [53.3Ω]



3.8_3333MHz_Final_setting.txt 19k .txt file


Updated post 156 and post 160 with RAM kit type in entry text string.

@finalheaven

Once you try GSAT there is no going back







.

Luv'd the pausing/resuming of threads to create power spikes. This alone makes it better than HCI Memtest IMO. Loads all thread, etc with nice easy command and no need to organise multiple windows. I usually use [email protected] for varying load testing of an OC besides other apps.

So well worth the time installing IMO.


----------



## finalheaven

Quote:


> Originally Posted by *mus1mus*
> 
> While I agree that HNT stress is hard for the RAM, I have not experienced it fail on an HCI stable set-up. Something else is doing that.
> 
> If your VCore was previously tuned for a lower memory speed, jumping to 3466 will require more. Based from exp.


Yea, I've been reading that to be the case as well, but mine passes on the same Vcore. However, my prior Vcore was already tuned for 3200 so it wasn't a huge jump to 3466.


----------



## finalheaven

@gupsterg

Let me know how 3466 turns out. I had to increase my SOC to 1.1v just now because it would not cold boot.


----------



## Silent Scone

Quote:


> Originally Posted by *gupsterg*
> 
> [email protected] 1.075v---BIOS 9943---Stressapptest---1hr--F4-3200C14D-16GTZ
> 
> ProcODT: [53.3Ω]
> 
> 
> 
> 3.8_3333MHz_Final_setting.txt 19k .txt file
> 
> 
> Updated post 156 and post 160 with RAM kit type in entry text string.
> 
> @finalheaven
> 
> Once you try GSAT there is no going back
> 
> 
> 
> 
> 
> 
> 
> .
> 
> Luv'd the pausing/resuming of threads to create power spikes. This alone makes it better than HCI Memtest IMO. Loads all thread, etc with nice easy command and no need to organise multiple windows. I usually use [email protected] for varying load testing of an OC besides other apps.
> 
> So well worth the time installing IMO.


As said previously, both have their uses. HCI can find errors at the cache/memory interaction. It's possible to run GSAT with very unstable CPU settings, and still pass. Which is also a testament to how well it isolates memory.


----------



## gupsterg

+rep for share of experience







.

All I can say is on Sunday HCI Memtest passed ~2hrs with tighter timings and lower SOC on 3466MHz strap than GSAT, same settings did not last 5min in GSAT. CPU OC same in both cases, 3.8GHz/+206mV.


----------



## Silent Scone

Yeah, that can happen. GSAT shatters dreams everywhere lol. Normally start out with that before moving on to HCI.


----------



## LuciferX

Ryzen and Motherboard on Stock/Auto, Ram with XMP enabled on BIOS (2933 instead of 3000 mhz , and timings are not the same, maybe don't like C15 ?)



Spoiler: Pics










R7 1700 @ Stock 3GHZ (3.2 Full Load) - 2933 MHZ 16-17-17-35-(69-1T) 1.35v - [email protected] (0.950v) Bios [email protected] x370 Professional Gaming-HCI 450/500% Corsair CMK16GX4M2B3000C15





Should I try GSAT for test stability on stock speeds or HCI is enough?


----------



## Silent Scone

Quote:


> Originally Posted by *LuciferX*
> 
> Ryzen and Motherboard on Stock/Auto, Ram with XMP enabled on BIOS (2933 instead of 3000 mhz , and timings are not the same, maybe don't like C15 ?)
> 
> 
> 
> Spoiler: Pics
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> R7 1700 @ Stock 3GHZ (3.2 Full Load) - 2933 MHZ 16-17-17-35-(69-1T) 1.35v - [email protected] (0.950v) Bios [email protected] x370 Professional Gaming-HCI 450/500% Corsair CMK16GX4M2B3000C15
> 
> 
> 
> 
> 
> Should I try GSAT for test stability on stock speeds or HCI is enough?


Anything above 2666 is overclocking on Ryzen. As mentioned in the post above, GSAT can be an eye opener as to what's stable.


----------



## LuciferX

Quote:


> Originally Posted by *Silent Scone*
> 
> Anything above 2666 is overclocking on Ryzen. As mentioned in the post above, GSAT can be an eye opener as to what's stable.


Thanks! I will try it


----------



## finalheaven

Hypothetically speaking, if one passes say 1-2 hours of GSAT at a certain DDR voltage, will there be any test that stresses it more?

Or in other words, with all things being equal, if another stress test crashes (whether that's prime, y-cruncher, or IBT), can it be related to memory/ram still? Or would it all be related to either CPU or SOC voltage?


----------



## LuciferX

I tried GSAT this time:

R7 1700 @ Stock 3GHZ (3.2 Full Load) - 2933 MHZ 16-17-17-35-(69-1T) 1.35v - [email protected] (0.950v) Bios [email protected] x370 Professional Gaming- GSAT 1 Hour - Corsair CMK16GX4M2B3000C15



Spoiler: Test









Everything seems stable


----------



## finalheaven

Quote:


> Originally Posted by *LuciferX*
> 
> I tried GSAT this time:
> 
> R7 1700 @ Stock 3GHZ (3.2 Full Load) - 2933 MHZ 16-17-17-35-(69-1T) 1.35v - [email protected] (0.950v) Bios [email protected] x370 Professional Gaming- GSAT 1 Hour - Corsair CMK16GX4M2B3000C15
> 
> 
> 
> Spoiler: Test
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Everything seems stable


Nice, but are you not planning to overclock? When you're overclocking you'll usually need more volts. This is why my question above asks with everything else being equal. For instance, I am using 3.8ghz to test my ram and then going up on Vcore as necessary. It's why I'll have my Vcore and SOC above default.


----------



## LuciferX

Quote:


> Originally Posted by *finalheaven*
> 
> Nice, but are you not planning to overclock? When you're overclocking you'll usually need more volts. This is why my question above asks with everything else being equal. For instance, I am using 3.8ghz to test my ram and then going up on Vcore as necessary. It's why I'll have my Vcore and SOC above default.


Probably, but not yet, I'm still checking stability in my new system with RAM close to XMP Specs first (3000mhz @ 1.35v)


----------



## Jpmboy

Quote:


> Originally Posted by *finalheaven*
> 
> Hypothetically speaking, if one passes say 1-2 hours of GSAT at a certain DDR voltage, will there be any test that stresses it more?
> 
> Or in other words, with all things being equal, if another stress test crashes (whether that's prime, y-cruncher, or IBT), can it be related to memory/ram still? Or would it all be related to either CPU or SOC voltage?


prime, IBT and HWBOT y-cruncher really do not stress the ram to the same degree as gsat or HCi. failing in those high current AVX loads is not likely ram, tho it could be the IMC. IMO, prime, ibt and y-cruncher are from the Jurassic mind-set regarding system stability. They are okay for a brief high current load scenario unlike ANYTHING your gaming rig will experience.. a combination of GSAT/HCi, realbench/x264 or x265, and a few loops of IBT (if you feel compelled) is all that is needed. Hours of IBT, prime or Y-c will only prematurely age your cpu and will cause you to run a lower overclock than you otherwise could with no stability issues.
Want to real-world test your rig's ability to compute? run Boinc overnight on all threads and 100% cpu load. It's about as relevant ot a gaming rig as y-cruncher benchmark


----------



## gupsterg

Y-Cruncher was updated for Ryzen, link. Prime95 has also been, link. I agree IBT-AVX is Jurassic. Dunno about "mind-set"







.

I agree these stability tests may not be right context for users which just game, etc on rig. But for some they are relevant. I have done far more IBT AVX then I recall on Ryzen, so far all AOK. Timur Born is very close to 4.0GHz on CPU and snagged 3300MHz prior to UEFI 9943/AGESA 1.0.0.6 and runs IBT AVX like as it's his religion. He has also pushed the envelope on temps testing prior to doing IBT AVX with ~4.0GHz/3300MHz. As he was querying Elmor on how temps are being reported, etc in the C6H OC thread. So far short term no one is reporting degradation, long term no idea.

My view finalheaven is, HCI / GSAT do not push the rig as much as IBT AVX, Y-Cruncher, x264, RB (in order of what my CPU sample find hardest to easiest). So as HCI / GSAT don't load CPU as much, it's basically RAM aspect being tested. IBT AVX / Y-Cruncher do load up the RAM and CPU, so then you see a differing "interaction" being tested IMO. Then there are peeps like chew* and others testing RAM stability using P95 custom setup. So I believe when CPU is heavily loaded and RAM then you will need to tweak elements based on that vs a pass on HCI / GSAT.

FYI for Ryzen owners, tRFC read back bug, previous and current UEFI/AGESA, link.


----------



## finalheaven

Quote:


> Originally Posted by *Jpmboy*
> 
> prime, IBT and HWBOT y-cruncher really do not stress the ram to the same degree as gsat or HCi. failing in those high current AVX loads is not likely ram, tho it could be the IMC. IMO, prime, ibt and y-cruncher are from the Jurassic mind-set regarding system stability. They are okay for a brief high current load scenario unlike ANYTHING your gaming rig will experience.. a combination of GSAT/HCi, realbench/x264 or x265, and a few loops of IBT (if you feel compelled) is all that is needed. Hours of IBT, prime or Y-c will only prematurely age your cpu and will cause you to run a lower overclock than you otherwise could with no stability issues.
> Want to real-world test your rig's ability to compute? run Boinc overnight on all threads and 100% cpu load. It's about as relevant ot a gaming rig as y-cruncher benchmark


Well alright. I'll pass GSAT and an hour of realbench, and use that as my everyday setting then.

@gupsterg

I am able to pass GSAT for 2 hours with 3466 16-16-16-36-2T @ 1.38v. If I use 1T, it requires 1.42-1.43v, so I'll just go with 2T.

Also using 2T, the CPU does not nearly need as much Vcore. It appears stable near my 75mV. I'll be sticking to 75mV or a little higher assuming it has no issues/errors with Realbench.


----------



## finalheaven

@Jpmboy

Is running at 3466 16-16-16-36-2T better than running at 3200 14-14-14-34-1T?

I know latency wise, the 3200 is better, but with the infinity fabric, I assume I should be running 3466?


----------



## Silent Scone

Shouldn't be any confusion over what is what.

The tests in the OP are designed to stress memory, the other aforementioned ones are not









Anyone using Y-Cruncher specifically to test RAM is on the wrong path


----------



## finalheaven

Quote:


> Originally Posted by *Silent Scone*
> 
> Shouldn't be any confusion over what is what.
> 
> The tests in the OP are designed to stress memory, the other aforementioned ones are not
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Anyone using Y-Cruncher specifically to test RAM is on the wrong path


The question wasn't about using Y-Cruncher to test RAM. It was about ruling out RAM completely (as source of failure) if it passed GSAT, but Y-Cruncher was still failing.


----------



## gupsterg

Yeah I'm rolling with 2T for IBT AVX pass. 1T IMO it's failing as I've reached max voltages I'm prepared to give. So yeah I start seeing less of a voltage requirement. Other tests like HCI/GSAT/Y-Cruncher 1T lower volts than IBT AVX all good.

I have not had time to check what is better performing. I won't for a while. Trying for 3600MHz before I swap CPU.


----------



## finalheaven

I just passed 30 mins of GSAT (will do more later) with 32GB (4x8) running 3600mhz 16-16-16-36-2T

SOC @ 1.2v
DDR @ 1.38v

Did not test CPU stability yet but running my 1700 @ +0.0875 offset. 3.8Ghz.

Wonder if running on SOC @ 1.2v will be an issue...

@gupsterg

What is your SOC with 3600 and are you comfortable with 1.2v?


----------



## gupsterg

Just for testing SOC 1.2V, DDR 1.4V as IBT needed min 1.375V for 3466MHz. Having issues in GSAT at present







.


----------



## Silent Scone

Quote:


> Originally Posted by *finalheaven*
> 
> The question wasn't about using Y-Cruncher to test RAM. It was about ruling out RAM completely (as source of failure) if it passed GSAT, but Y-Cruncher was still failing.


Same difference, if you're having to ask


----------



## gupsterg

@finalheaven

Got GSAT running on 3600MHz, knocked out CPU OC. SOC: 1.15V, DDR 1.4V, slowed tRFC down further than XMP 560. Gonna let it run probably 15min then do a retune.


----------



## finalheaven

Quote:


> Originally Posted by *gupsterg*
> 
> @finalheaven
> 
> Got GSAT running on 3600MHz, knocked out CPU OC. SOC: 1.15V, DDR 1.4V, slowed tRFC down further than XMP 560. Gonna let it run probably 15min then do a retune.


Are you able to cold boot with only 1.15v? Boot from shutdown that is.


----------



## gupsterg

Not really tested for that aspect last night. I was having no issue on reboots for tweaking settings, etc. I had to scrap 3600MHz for time being as I kept getting errors in GSAT, mainly 1 HW error logged at end of 15min run







.

So today I've taken the 3.8/3466MHz 16-16-16-16-36-2T IBT AVX pass profile. Then set tRFC as 631 / 469 / 289 , next lowered CPU to 3.7GHz so when I adjusted BCLK I wasn't going over 3.8GHz. Set CPU LLC from [Auto] to LVL2.

[email protected] 1.125v---BIOS 9943---Stressapptest---1hr--F4-3200C14D-16GTZ

CPU R7 1700 Batch: 1713PGT (Malaysia)



ProcODT: [53.3Ω]
GearDown: [Disabled]
Power Down Enable: [Disabled]

Super I/O Clock Skew: [Disabled]

BankGroupSwap: [Disabled]
CLDO_VDDP: 960mV

3508MHz_GSAT_setting.txt 19k .txt file


Gonna do another BCLK bump ...


----------



## finalheaven

Quote:


> Originally Posted by *gupsterg*
> 
> Not really tested for that aspect last night. I was having no issue on reboots for tweaking settings, etc. I had to scrap 3600MHz for time being as I kept getting errors in GSAT, mainly 1 HW error logged at end of 15min run
> 
> 
> 
> 
> 
> 
> 
> .
> 
> So today I've taken the 3.8/3466MHz 16-16-16-16-36-2T IBT AVX pass profile. Then set tRFC as 631 / 469 / 289 , next lowered CPU to 3.7GHz so when I adjusted BCLK I wasn't going over 3.8GHz. Set CPU LLC from [Auto] to LVL2.
> 
> [email protected] 1.125v---BIOS 9943---Stressapptest---1hr--F4-3200C14D-16GTZ
> 
> 
> 
> ProcODT: [53.3Ω]
> GearDown: [Disabled]
> Power Down Enable: [Disabled]
> 
> Super I/O Clock Skew: [Disabled]
> 
> BankGroupSwap: [Disabled]
> CLDO_VDDP: 960mV
> 
> 3508MHz_GSAT_setting.txt 19k .txt file
> 
> 
> Gonna do another BCLK bump ...


Why the disabling of Super I/O Clock Skew? Your SOC isn't that high yet.


----------



## gupsterg

Agreed. Aware Elmor's recommendation was past SOC 1.2V to disable it.

How I see it is some "things" are not a set in stone "recommendation", if you get what I mean. So some times I try X vs Y setup just to see what happens. Super I/O Clock Skew I checked if changing from [Auto] to another value allowed greater stability past 3508MHz it didn't. So I can only assume it may be an idea to play with it when near SOC: 1.2V just to see if it has an affect on stability.

[email protected] 1.00v---BIOS 9943---Stressapptest---1hr--F4-3200C14D-16GTZ



CPU R7 1700 Batch: 1709PGT (Malaysia) in a compare to other CPU in post 156 lower SOC used. The VBOOT/VDIMM will be trimmed to 1.35V at present setting profile in a way to aim for higher RAM. IIRC the other CPU did not do C14 on 3333MHz. maybe the small bump in VDIMM is helping but I don't think so at present.


----------



## ibeat117

[email protected] 1.13v (Auto)---BIOS 9945---Stressapptest---1 Hour--F4-3866C18-16GTZ


----------



## Jpmboy

Quote:


> Originally Posted by *finalheaven*
> 
> @Jpmboy
> 
> Is running at 3466 16-16-16-36-2T better than running at 3200 14-14-14-34-1T?
> 
> I know latency wise, the 3200 is better, but with the infinity fabric, I assume I should be running 3466?


3466 seems to be a sweetspot. if you can reach 3466 c14-15-15-44-1T this has been the most productive ram freq and timings I've been able to work out. overall better than 3600c16 in SiSoft and AIDA (and several benchmarks) in my configuration.
Quote:


> Originally Posted by *gupsterg*
> 
> Y-Cruncher was updated for Ryzen, link. Prime95 has also been, link. I agree IBT-AVX is Jurassic. Dunno about "mind-set"
> 
> 
> 
> 
> 
> 
> 
> .
> 
> I agree these stability tests may not be right context for users which just game, etc on rig. But for some they are relevant. I have done far more IBT AVX then I recall on Ryzen, so far all AOK. Timur Born is very close to 4.0GHz on CPU and snagged 3300MHz prior to UEFI 9943/AGESA 1.0.0.6 and runs IBT AVX like as it's his religion. He has also pushed the envelope on temps testing prior to doing IBT AVX with ~4.0GHz/3300MHz. As he was querying Elmor on how temps are being reported, etc in the C6H OC thread. So far short term no one is reporting degradation, long term no idea.
> 
> My view finalheaven is, H*CI / GSAT do not push the rig as much as IBT AVX, Y-Cruncher, x264, RB* (in order of what my CPU sample find hardest to easiest). So as HCI / GSAT don't load CPU as much, it's basically RAM aspect being tested. IBT AVX / Y-Cruncher do load up the RAM and CPU, so then you see a differing "interaction" being tested IMO. Then there are peeps like chew* and others testing RAM stability using P95 custom setup. So I believe when CPU is heavily loaded and RAM then you will need to tweak elements based on that vs a pass on HCI / GSAT.
> 
> FYI for Ryzen owners, tRFC read back bug, previous and current UEFI/AGESA, link.


yeah - sure I know cruncher was updated to account for Ryzen's "peculiarities". regarding IBT, prime etc. they basically hammer the fpu with repetitive task or proc calls and really do not stress the overall architecture in modern cpus. What trips up these processors is not repeating the same function call over and over (tho it can tell you about you cooling solution). What trips theseup in a real-world use scenario is rapidly changing proc calls accessing many parts of the architecture - ideally simultaneously.

If you are actually hunting primes.. use p95, if you are 24/7 Boinc on all threads, LinPac can help that setup. But if you use your rig like 99.99% of users, Realbench, HCi/GSAT, x264 and x265 stability and performance is a much better regime, and will not cause you yo run a lower OC simply because the cooling can't handle the ridiculous heat caused by hammering the cpu in a manner it will never experience.

As you have seen... stable in GSAT/HCi but failing IBT or Prime may not be from the root cause you think. And certainly, IBT/P95 only reveal ram instability when it is really poor, otherwise it will take days for either to ferret out instability GSAT can find in an hour or two.

lol - mind set... "old tools for new problems".


----------



## gupsterg

@finalheaven

AIDA64 bench I just use as a quick indicator. I other bench test which showed some improvement was HWBot X265 4K. I did ~10.8FPS on 3.975GHz 2933MHz 14-13-13-13-34-1T, 2x I got 10.9xFPS yesterday. 10.97FPS HWbot sub, 10.94FPS ROG Showdown sub (Stage 2) with 3466MHz 16-16-16-16-36-2T.


----------



## Jpmboy

Quote:


> Originally Posted by *gupsterg*
> 
> @finalheaven
> 
> AIDA64 bench I just use as a quick indicator. I other bench test which showed some improvement was HWBot X265 4K. I did ~10.8FPS on 3.975GHz 2933MHz 14-13-13-13-34-1T, 2x I got 10.9xFPS yesterday. 10.97FPS HWbot sub, 10.94FPS ROG Showdown sub (Stage 2) with 3466MHz 16-16-16-16-36-2T.


when using x265 as a stability assessment, check the correction factor with 4x overkill... >0.95 is good. as close to one as possible.


----------



## finalheaven

@Jpmboy @gupsterg

Problem is my only two options are 3200 14-14-14-34-1T *or* 3466 16-16-16-36-2T.

I do not want to run 1.2v SOC so 3600 is out of the running. And between those two, I know 3200 has faster latencies while 3466 will have faster infinity fabric speed. What would you guys choose?


----------



## mafio

Quote:


> Originally Posted by *finalheaven*
> 
> @Jpmboy @gupsterg
> 
> Problem is my only two options are 3200 14-14-14-34-1T *or* 3466 16-16-16-36-2T.
> 
> I do not want to run 1.2v SOC so 3600 is out of the running. And between those two, I know 3200 has faster latencies while 3466 will have faster infinity fabric speed. What would you guys choose?


3200 MHz with lower voltages.


----------



## finalheaven

Quote:


> Originally Posted by *mafio*
> 
> 3200 MHz with lower voltages.


3466 only needs 1.1v SOC so it isn't that high. I'm willing to do 1.1v 24/7 so long as its an improvement over 3200 14-14-14-34-1T. Just not sure if it is.


----------



## Jpmboy

Quote:


> Originally Posted by *finalheaven*
> 
> 3466 only needs 1.1v SOC so it isn't that high. I'm willing to do 1.1v 24/7 so long as its an improvement over 3200 14-14-14-34-1T. Just not sure if it is.


no need to go above 1.1V SOC. Try adding VDIMM for 3466. DDR4 can run 1.4-1.45V as a daily setting with no worries. And afaik, that is not over the top for the ryzen IMC. My 1`600x has been at 1.1 SOC with 1.425V VDIMM for a while now whether on bclk 100 or 130 for 3466 (I do like bclk 130 for 3466, tightens up timings we can't adjust yet).


----------



## gupsterg

@Jpmboy

+rep for experience share







. I don't use HWBot x265 for stability test. I use another custom x265 in OP of my thread. HWBot x265 4K max is CPU 3.975GHz, GPUPI on CPU only for same voltage I can use 4.075GHz. Both those cases are bench stable only







.

@finalheaven

As stated by The Stilt in his Anandtech thread, most cases the performance gain is from Data Fabric clock increase when RAM MHz increased. I'd be comfy with 1.1V SOC as The Stilt has recommended that as max sane value. This is also well below Asus recommendation of 1.2V, IIRC some mobo vendors are stating as high as 1.35V. I know of one member, @madweazl that fired 1.4V at SOC and was OK. This was inadvertently whilst OC'ing on







IIRC







. One member IIRC went to 1.5V and it did have a detrimental effect very quickly. Both cases in C6H OC thread.

I also did 3DM FS with 4.0GHz 3200MHz 14-13-13-13-34-1T vs 3466MHz 16-16-16-16-36-2T and the latter came out on top, link. Yes results compare could be assessed as within run to run variance. Once I finish testing my 2nd CPU I plan to do more bench compares







.

The 2nd CPU for 3333MHz 14-14-14-14-34-1T is pretty optimal for MHz/timings/voltages IMO, much better than my 3rd CPU. It needed only SOC 1V vs 1.075V for all test passes, plus the CPU at 3.8GHz did not need a bump in VCORE compared with other.

GSAT is showing 3466MHz needs 1.1V like the other batch CPU







, nearly half way through testing. Then gonna do a Y-Crunch/IBT AVX run to see if VCORE/SOC need a bump like last CPU for 3466MHz.

Work CLDO_VDDP IMO, you should get 3333MHz working. Both my CPUs were differing for "memory hole" but both have worked for higher RAM with tweaks to that.


----------



## madweazl

I think it was all the way up to 1.6 actually; cant remember off the top of my head. Ran with that set for quite a while too (12 hours or so?).


----------



## gupsterg

[email protected] 1.1v---BIOS 9943---Stressapptest---1hr--F4-3200C14D-16GTZ



CPU R7 1700 Batch: 1709PGT (Malaysia)

ProcODT: 53.3 Ohms

GearDown: [Disabled]
Power Down Enable: [Disabled]
BankGroupSwap: [Disabled]

CLDO_VDDP: [937mV]


----------



## finalheaven

Quote:


> Originally Posted by *gupsterg*
> 
> @finalheaven
> 
> As stated by The Stilt in his Anandtech thread, most cases the performance gain is from Data Fabric clock increase when RAM MHz increased. I'd be comfy with 1.1V SOC as The Stilt has recommended that as max sane value. This is also well below Asus recommendation of 1.2V, IIRC some mobo vendors are stating as high as 1.35V. I know of one member, @madweazl that fired 1.4V at SOC and was OK. This was inadvertently whilst OC'ing on
> 
> 
> 
> 
> 
> 
> 
> IIRC
> 
> 
> 
> 
> 
> 
> 
> . One member IIRC went to 1.5V and it did have a detrimental effect very quickly. Both cases in C6H OC thread.
> 
> I also did 3DM FS with 4.0GHz 3200MHz 14-13-13-13-34-1T vs 3466MHz 16-16-16-16-36-2T and the latter came out on top, link. Yes results compare could be assessed as within run to run variance. Once I finish testing my 2nd CPU I plan to do more bench compares
> 
> 
> 
> 
> 
> 
> 
> .
> 
> The 2nd CPU for 3333MHz 14-14-14-14-34-1T is pretty optimal for MHz/timings/voltages IMO, much better than my 3rd CPU. It needed only SOC 1V vs 1.075V for all test passes, plus the CPU at 3.8GHz did not need a bump in VCORE compared with other.
> 
> GSAT is showing 3466MHz needs 1.1V like the other batch CPU
> 
> 
> 
> 
> 
> 
> 
> , nearly half way through testing. Then gonna do a Y-Crunch/IBT AVX run to see if VCORE/SOC need a bump like last CPU for 3466MHz.
> 
> Work CLDO_VDDP IMO, you should get 3333MHz working. Both my CPUs were differing for "memory hole" but both have worked for higher RAM with tweaks to that.


Hmm, I'll definitely stay at 3466 if its better. Actually one thing I never tested was whether or not I can lower SOC from 1.1v. 3466 1T needed 1.1v, but after I disabled gear down, I never tested to see if I can lower SOC.

I am now testing 3466 16-16-16-36-2T and SOC @ 1.075v. I can boot up from complete power loss (from PSU off) and not lose settings. If this test fails though, I'll move back to 1.1v.
Quote:


> Originally Posted by *Jpmboy*
> 
> no need to go above 1.1V SOC. Try adding VDIMM for 3466. DDR4 can run 1.4-1.45V as a daily setting with no worries. And afaik, that is not over the top for the ryzen IMC. My 1`600x has been at 1.1 SOC with 1.425V VDIMM for a while now whether on bclk 100 or 130 for 3466 (I do like bclk 130 for 3466, tightens up timings we can't adjust yet).


The reason I don't use 3466 14-14-14-34 is because I can't cold boot no matter what I change the ProcODT to. I am pretty sure I can get it to be stable, but my requirement is that it must be able to cold boot. Cold boot as in boot from shutdown. And since I can't cold boot up with it I moved on. Not sure if later bios will fix that or will enable 3600mhz with SOC 1.1v-1.15v. I know I should be happy with 3466 16-16-16-36-2T but its so hard not to want more.


----------



## gupsterg

I do believe SOC increase have in the past masked UEFI/Firmware deficiencies. I have now gained pretty good RAM speed on 2x R7 1700 with lower SOC than plenty of posts of members I have read.

Next I also believe a incorrect CLDO_VDDP value can affect cold boot. I have seen it with both CPUs. For example I initially used 931mV for 3466MHz. All good for some initial small testing runs, all good for warm reboots. Cold was a failure, changed to 937mV and all good. It sorta makes sense when seeing how CLDO_VDDP shifts memory holes and not eradicates them. For example on this CPU with default 950mV all straps upto 3200MHz could be had with just a strap jump. Once I tuned CLDO_VDDP for 3333MHz to work 3200MHz could not be used. On same value then 3466MHz did also work but tweaked for cold boot. Some of the process was shared here.

I'm bowled over with UEFI 9943/AGESA 1.0.06 results. As we know this is beta and AGESA has some bugs perhaps the future releases will make 3466MHz+ sweetier for voltages, etc.

I'm considering staying at 3333MHz 14-14-14-14-34-1T with this CPU as 1V SOC is so sweet IMO, plus the timings. I may just raise CPU to 3.9GHz as I'd prefer odd clock CPU with this RAM strap







.


----------



## finalheaven

Quote:


> Originally Posted by *gupsterg*
> 
> I do believe SOC increase have in the past masked UEFI/Firmware deficiencies. I have now gained pretty good RAM speed on 2x R7 1700 with lower SOC than plenty of posts of members I have read.
> 
> Next I also believe a incorrect CLDO_VDDP value can affect cold boot. I have seen it with both CPUs. For example I initially used 931mV for 3466MHz. All good for some initial small testing runs, all good for warm reboots. Cold was a failure, changed to 937mV and all good. It sorta makes sense when seeing how CLDO_VDDP shifts memory holes and not eradicates them. For example on this CPU with default 950mV all straps upto 3200MHz could be had with just a strap jump. Once I tuned CLDO_VDDP for 3333MHz to work 3200MHz could not be used. On same value then 3466MHz did also work but tweaked for cold boot. Some of the process was shared here.
> 
> I'm bowled over with UEFI 9943/AGESA 1.0.06 results. As we know this is beta and AGESA has some bugs perhaps the future releases will make 3466MHz+ sweetier for voltages, etc.
> 
> I'm considering staying at 3333MHz 14-14-14-14-34-1T with this CPU as 1V SOC is so sweet IMO, plus the timings. I may just raise CPU to 3.9GHz as I'd prefer odd clock CPU with this RAM strap
> 
> 
> 
> 
> 
> 
> 
> .


That was seem like a nice sweet spot. I'll stay at 3466 16-16-16-36-2T w/ 1.1v SOC.

I know that 1.0.0.6 brought huge changes and improvements, but do you think more improvements like this will come again? Other than minor changes, have we reached near full potential of Ryzen? I would really like 3600mhz memory, but the SOC required for that is too much.


----------



## Silent Scone

Those configs with 32GB are fine. No point pushing things much further.


----------



## bl1tzk1213g

Any tips on stabilizing 3600mhz memory? How do I go loosening timings? I get bluescreen on windows with those timings. Raising the SocV to 1.2 does not help either. Or is it current limitation of the platform or my ram?

I have g.skill 3200mhz 8gb samsung b-die sticks.

Dram 1.4V
SocV 1.12
Timings 16-16-16-36
Command rate 1T/2T


----------



## LuciferX

Passed GSAT with R7 @ 3.6 GHZ



R7 1700 @ 3.6 Ghz - 2933 MHZ 16-17-17-35-(69-1T) 1.38v - [email protected] Bios [email protected] x370 Professional Gaming- GSAT 1 Hour - Corsair CMK16GX4M2B3000C15


----------



## Jpmboy

Quote:


> Originally Posted by *finalheaven*
> 
> Hmm, I'll definitely stay at 3466 if its better. Actually one thing I never tested was whether or not I can lower SOC from 1.1v. 3466 1T needed 1.1v, but after I disabled gear down, I never tested to see if I can lower SOC.
> 
> I am now testing 3466 16-16-16-36-2T and SOC @ 1.075v. I can boot up from complete power loss (from PSU off) and not lose settings. If this test fails though, I'll move back to 1.1v.
> The reason I don't use 3466 14-14-14-34 is because I can't cold boot no matter what I change the ProcODT to. I am pretty sure I can get it to be stable, but my requirement is that it must be able to cold boot. Cold boot as in boot from shutdown. And since I can't cold boot up with it I moved on. Not sure if later bios will fix that or will enable 3600mhz with SOC 1.1v-1.15v. I know I should be happy with 3466 16-16-16-36-2T but its so hard not to want more.


gotta be able to clean cold boot... especially on this platform.








if you have 32GB at 3466c16 that is a win. With the 16GB kit I'm using, 3466 14-14-14- has been an issue to stabilize and ALWAYS clean boot. Changing to 14-15-15 44-1t settled everything down, is gast satble and gave very good performance numbers (best I post a bios screenshot, the timings are not all 15s)... nedd to fire up the c6h.


----------



## haszek

4x8GB (e-die)

[email protected] 1.175v---BIOS 9945---HCI---200%

Kit CMU32GX4M4C3466C16
Proc ODT 53.3
CPU offset with Pstates +0.200V (1.38V)
CLDO VDDP 975

Trfc set at 278/171/118

A bit of a struggle for me recently as afterburner was causing black screens during HCI testing (not sure why now, maybe because of the latest windows updates, not sure).
One of my memory sticks Corsair LED RED also had SPD corrupted (fixed with elmor's tool). But anyway this is what I can achieve with my 4x8GB (e-die) with the latest beta bioses. Everything above gives me errors quite quickly even 18-20-20-, 2T doesn't seem to change things for me as well (or cpu V, ddr v, soc v). I might try with different CLDO_VDDP


----------



## gupsterg

@finalheaven

I think today I'm going to try to tighten up 3333MHz strap. Probably aim to use elements of lower MHz strap subtimings to tweak it. Yes I do believe we may see further enhancement of firmware. I do not believe this is it







. Going through the Intel stability test thread this is not a bad showing at all IMO.

3466MHz 16-16-16-36-2T w/ 1.1v SOC passed 1hr GSAT on my 2nd CPU. Y-Cruncher as well for 1hr. IBT AVX it did not







. So just like my other CPU it will need a bump in VCORE and/or SOC for that to pass, which I'm not inclined to do on this. My 2nd CPU unlike my 3rd did not need bumps in VCORE & SOC to pass IBT AVX on 3333MHz. The exact same setup that passed GSAT worked for Y-Cruncer and IBT AVX.

@haszek

The tRFC values did you set manually? cheers







.


----------



## Jpmboy

Stepping the primary timings helped a lot with the 4266c19 kit I have on the c6h. Bios screen shots:

170530120717.zip 835k .zip file

no changes to ODT, geardown, cldo etc.

The kit is decent, not great.. known good on z270 for 4133c17 and 3866c15, but with a bit more help than the 3600c15 2x8GB kit running on that platform atm.


----------



## haszek

Quote:


> Originally Posted by *gupsterg*
> 
> @haszek
> 
> The tRFC values did you set manually? cheers
> 
> 
> 
> 
> 
> 
> 
> .


Yes I checked how motherboard sets them on auto @2133 and used those. Read that e-dies shouldn't have problems with low trfc values, it was however for intel, but worked for me on ryzen as well.


----------



## gupsterg

Nice







, +rep for share







. Yeah been meddling with taking lower strap timings and using with 3333MHz today







.

Have you noted improvement in benches with tightened tRFC? cheers







.


----------



## haszek

Quote:


> Originally Posted by *gupsterg*
> 
> Nice
> 
> 
> 
> 
> 
> 
> 
> , +rep for share
> 
> 
> 
> 
> 
> 
> 
> . Yeah been meddling with taking lower strap timings and using with 3333MHz today
> 
> 
> 
> 
> 
> 
> 
> .
> 
> Have you noted improvement in benches with tightened tRFC? cheers
> 
> 
> 
> 
> 
> 
> 
> .


Minimal but yes, latency with tight settings can go in my case to around 74.5ns -75ns, but with auto (416/256/176) it was usually closer to 75.5-76ns


----------



## gupsterg

Cheers







.

I used 2400MHz strap sub timings with 14-14-14-14-34-560-416-256-1T on my F4-3200C14D-16GTZ whilst on 3333MHz. AIDA64 and GSAT "speed" made it within "spitting speed" of 3466MHz 16-16-16-16-36-560-416-256-2T. Alas it failed GSAT test with significant HW errors







. Using 2666MHz subtimings I still had the "speed" bump compared with 3466MHz, failed with 1 HW error on 1hr test







. Now testing 2800MHz strap sub timings with 3333MHz.


----------



## finalheaven

https://www.hardocp.com/article/2017/05/26/definitive_amd_ryzen_7_realworld_gaming_guide

I wonder how much difference it would have made if they used at least 3200mhz memory. For 7700k, they used 3600mhz memory.


----------



## gupsterg

Post 211 contained this CPU's initial 3333MHz GSAT pass. Then post 222 of 3466MHz. 3466MHz IMO was leaving me no headroom on voltages, etc if need to pass all stability tests I may run and if "tweaked" profile further. So it was tweaking time for 3333MHz







.

3.8_3333_C14_Tweakd_setting.txt 19k .txt file


Only settings missing out of the txt besides PState 0 OC FID:-

BankGroupSwap: [Disabled]
CLDO_VDDP: [937mV]

Nice increase in AIDA64/GSAT memory speeds







. Passed 1hr GSAT, gonna leave it on a overnighter before doing fresh W7/W10C on SSDs. Surprised I haven't needed to do "fresh" images so far in all the testing of "iffy" OCs resulting in stopcodes, etc







.





*** edit ***

reuploaded AIDA64/GSAT compare image as had a error in 3333MHz with 2800MHz GSAT speed result









@haszek

Post 236 I have made an error







. Tests 3333MHz with 2400MHz and 2666MHz strap timings were both 1 HW error. I must have mistook the "thread 15" text as errors


----------



## meRlinXAT

Quote:


> Originally Posted by *finalheaven*
> 
> https://www.hardocp.com/article/2017/05/26/definitive_amd_ryzen_7_realworld_gaming_guide
> 
> I wonder how much difference it would have made if they used at least 3200mhz memory. For 7700k, they used 3600mhz memory.


yes, the comparing was not directly fair.
but on the other side - the conclusion from this test is clear


----------



## Secret Dragoon

Quote:


> Originally Posted by *gupsterg*
> 
> Post 211 contained this CPU's initial 3333MHz GSAT pass. Then post 222 of 3466MHz. 3466MHz IMO was leaving me no headroom on voltages, etc if need to pass all stability tests I may run and if "tweaked" profile further. So it was tweaking time for 3333MHz
> 
> 
> 
> 
> 
> 
> 
> .
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 3.8_3333_C14_Tweakd_setting.txt 19k .txt file
> 
> 
> Only settings missing out of the txt besides PState 0 OC FID:-
> 
> BankGroupSwap: [Disabled]
> CLDO_VDDP: [937mV]
> 
> Nice increase in AIDA64/GSAT memory speeds
> 
> 
> 
> 
> 
> 
> 
> . Passed 1hr GSAT, gonna leave it on a overnighter before doing fresh W7/W10C on SSDs. Surprised I haven't needed to do "fresh" images so far in all the testing of "iffy" OCs resulting in stopcodes, etc
> 
> 
> 
> 
> 
> 
> 
> .
> 
> 
> 
> 
> 
> *** edit ***
> 
> reuploaded AIDA64/GSAT compare image as had a error in 3333MHz with 2800MHz GSAT speed result
> 
> 
> 
> 
> 
> 
> 
> 
> 
> @haszek
> 
> Post 236 I have made an error
> 
> 
> 
> 
> 
> 
> 
> . Tests 3333MHz with 2400MHz and 2666MHz strap timings were both 1 HW error. I must have mistook the "thread 15" text as errors




I am way too scared to test stability on this setup. Basically, it looks like it's "stable" for what I plan on using it for.


----------



## Praz

Hello

[email protected] 1.175v---BIOS 9943---GSAT---2 Hours---F4-3600C15D-16GTZ (2 Kits)


----------



## finalheaven

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> [email protected] 1.175v---BIOS 9943---GSAT---2 Hours---F4-3600C15D-16GTZ (2 Kits)


Is 3600 possible with 4 sticks if you go to 1T and C16?


----------



## Praz

Quote:


> Originally Posted by *finalheaven*
> 
> Is 3600 possible with 4 sticks if you go to 2T and C16?


Hello

3600 is doable with the timings I posted above. However the required memory and SOC voltages are higher then I am willing to use. At least as it applies to my CPU Ryzen has a long way to go to be on equal footing with Intel in regards to memory clocking.


----------



## gupsterg

@Praz

Thanks for share, +rep







.

@Secret Dragoon

Nice







, even getting to OS and doing some AIDA64 benches at 3600MHz feels sweet TBH







. I believe once FW (AMD side) improves some more we could see some improvement on stability at higher speeds, some may even gains some. Perhaps try HCI/GSAT and you'll know if you have some RAM errors or not.

I'd say I'm super happy with AGESA 1.0.0.6







. Besides being able to gain some better RAM MHz I just really have enjoyed the access to RAM timings







. My 3333MHz C14 tweak'd setup passed 8hrs GSAT last night







.


----------



## Robenger

I wish there was a guide for this. I've been trying for a week to get my 3200mhz kit to run at those settings and I've only been able to achieve 2933ish with crazy loose timings.


----------



## mafio

[email protected] 1.00v---BIOS F4d---GSAT---1 Hours---CT16G4DFD8213.C16FBR



ICs are micron C9BGN, double side 16 GB sticks rated at 2133 MHz CAS 15.


----------



## MuddyPaws




----------



## nilco

Im on the beta bios and I cant get my ram settings to stick? Didnt have a problem last bios, but now its reporting as 1066ghz instead of 16xx for 3200?? 16-16-16-16-36 refuses to stick and goes with 15-15-15-36 instead.


----------



## Silent Scone

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> [email protected] 1.175v---BIOS 9943---GSAT---2 Hours---F4-3600C15D-16GTZ (2 Kits)


Nice result, I found some time on Sunday to have a crack at similar, but wasn't quite there yet. Single errors throwing up late on in the test


----------



## ibeat117

Quote:


> Originally Posted by *Robenger*
> 
> I wish there was a guide for this. I've been trying for a week to get my 3200mhz kit to run at those settings and I've only been able to achieve 2933ish with crazy loose timings.


Raise SoC Voltage to 1.1V and DRAM Voltage to 1.35V


----------



## bluej511

Quote:


> Originally Posted by *ibeat117*
> 
> Raise SoC Voltage to 1.1V and DRAM Voltage to 1.35V


I wouldnt worry about soc voltage so much, i do it with 1.0v and its fine, he is however running jtec standard voltage, his voltage is at 1.2, no wonder he cant reach 3200. Im shocked it does 2933 at 1.2, hopefully hwinfo is reading correctly in his case.


----------



## Praz

Quote:


> Originally Posted by *Silent Scone*
> 
> Nice result, I found some time on Sunday to have a crack at similar, but wasn't quite there yet. Single errors throwing up late on in the test


Hello

I was experiencing the same with the memory voltage at 1.37V. There is quite a disparity of needed memory settings between Intel and AMD.


----------



## Jpmboy

nothing very notable, but was able to tighten up FAW, RDD and RTP a bit... and get things buttoned up on bclk 100 for 3466 (a bit more work than 3466 with bclk 130). 3466 on 130 remains quicker by several measures simply because I can't change all timings with 3466/100, including lower CAS which is very frustrating.

jpmboy ---- [email protected] --- 3466 14-15-15-39-1T @ 1.425V --- SOC 1.1. : G Skill F4-4266C19-8GTZA x2.


----------



## gupsterg

MB/s seems horrendous in that screenie







, is that a R5 thing?

Last setting below is current beta stage of tightening 3333MHz further.


----------



## Jpmboy

Quote:


> Originally Posted by *gupsterg*
> 
> MB/s seems horrendous in that screenie
> 
> 
> 
> 
> 
> 
> 
> , is that a R5 thing?
> 
> Last setting below is current beta stage of tightening 3333MHz further.


i think you are reading too much in to the reported M/s in gsat, depends on pauses and power spikes... and YES a 6 core should have a lower bandwidth than an 8 core... and this has been bugging me with AID64 since R7's have no better bandwidth that R5's do in that test. Si Soft seems to reflect this 33% increase in cores properly.

seen maybe one 1800X with meaningful better bandwidth:

gsat bandwidth is within 1000 using the same run command. I wouldn't draw too much from GSAT throughput.

edit: here's a more clear example:


same everything except ram divider.


----------



## gupsterg

Ahhh OK. AIDA64 sometimes is all over the place for me







. I had started to use the GSAT MB/s as when compare a 60s run to another 60s run (setup same of rig) I saw like ~4MB/s delta and thought maybe this is a solid speed test method to use to assess tweaks. Now seems not







. Below is my rig, same settings, left 60s run and right 8hrs.


----------



## Jpmboy

Quote:


> Originally Posted by *gupsterg*
> 
> Ahhh OK. AIDA64 sometimes is all over the place for me
> 
> 
> 
> 
> 
> 
> 
> . I had started to use the GSAT MB/s as when compare a 60s run to another (setup same of rig) I saw like ~4MB/s delta and thought maybe this is a solid speed test method to use to assess tweaks. Now seems not
> 
> 
> 
> 
> 
> 
> 
> . Below is my rig, same settings, left 60s run and right 8hrs.


it may be if you use the exact same command to launch it, and do not do anything with the machine while it's running... which i usually do with AID64 memtest, but 2h of gsat and I'll use it while gsat is running. Not a good way to compare any metric.
Aid64 scales linearly with core/thread count in intel platforms.. seems not to with ryzen for some reason. Weird.


----------



## gupsterg

I'm noob at using GSAT







, but always use same command but say time length for quick tests, etc.

Usually my final OC stability runs I don't use PC. Also for AID64 bench tests. Only today I was doing some tweaking. CPU L3 Cache read was something like 250 GB/s and then write went up to like 10000 GB/s I thought what!?! The platform should have imploded







.

At loss what to really use to assess tweaks at times. Most SW just isn't up to date enough for Ryzen IMO.

Just tried MAXXMem pretty much the app bomb'd on launch.


----------



## Jpmboy

New entry... plz replace the 3466 bclk 130 entry from a few weeks ago:

jpmboy --- [email protected] --- 3466 C 14-14-14-36 (RRD 5, Faw 20, RTP 8) 1.425V, SOC 1.1V, PLL 1.82V. -- 1h BashGSAT.


----------



## hsn

hsn [email protected] 1.15v---BIOS 9945---HCI---400% Team Dark pro 3200 cl14


----------



## AlphaC

I guess this is the thread for it but out of curiosity is the only way for me to get sub 75ms memory latency in AIDA64 to overclock memory past DDR4 3200MHz CL16 or tighten timings?

I see some CH VI Hero screenshots with 67 or 68ns memory latency while stock Ryzen 7 1800X with 2933MHz RAM seems to obtain 80ns.

I've also seen Ryzen 7 1700X @4GHz on a Gigabyte X370 K7 and 3433Mz RAM obtaining 68ns memory latency.

I've also seen Ryzen 7 1700 with DDR4 3200 MHz RAM obtaining 75ns memory latency (pretty much what I obtained).

There was a Ryzen 7 1700 on X370 Taichi with superloose DDR4-3200 20-21-21-41 that had 89ns memory latency.

----

System spec:
Ryzen 7 1700X (stock clocks til Gigabyte implements proper p-states)
EVGA DDR4-3200MHz 16-18-18-38 with tRC 56, 1.35V <-- single sided Hynix
Gigabyte X70 Gaming 5 , AGESA 1.0.06 / F6F BETA BIOS
SOC Voltage manually set to 1.1V

I haven't touched tRFC yet but when I used auto tRC the motherboard set it to 75 tRC and tRFC was 312

Manually dropping tRC to 56 as per XMP profile resulted in tRFC going up to 560

The values in the BIOs at the right side next to "AUTO"


Spoiler: Warning: Spoiler!



tWR: 16
tCWL: 11
tRRD_S: 4
tRRD_L: 6
tWTR_S: 3
tWTR_L: 8
tRFC: 312
tRFC2: 192
tRFC4: 132
tRTP: 8
tFAW: 23
Command Rate (tCMD) : left on auto but auto sets it to 1T
ProcODT: left on auto, no value on right side
tRCPAGE
tRDWR
tRDRDSC
tRDRDSD
tRDRDDD
tRDRD_SCL: 3
twRRD
tWRWRSC
tWRWRSD
tWRWRDD
tWRWR_SCL : 3
tCKE
RttNom
RttWr
RttPark

I'm using the table from https://community.amd.com/community/gaming/blog/2017/05/25/community-update-4-lets-talk-dram to try to decipher some of it



edit: AIDA64 XMP profile settings:


Spoiler: Warning: Spoiler!


----------



## Silent Scone

Table updated


----------



## LuciferX

Quote:


> Originally Posted by *Silent Scone*
> 
> Table updated


Sorry to bother you, but the motherboard I used for the tests was an Asrock Fatal1ty X370 Professional Gaming, not an Asus CH6:

R7 1700 @ Stock 3GHZ (3.2 Full Load) - 2933 MHZ 16-17-17-35-(69-1T) 1.35v - [email protected] (0.950v) Bios [email protected] x370 Professional Gaming-HCI 450/500% Corsair CMK16GX4M2B3000C15

R7 1700 @ Stock 3GHZ (3.2 Full Load) - 2933 MHZ 16-17-17-35-(69-1T) 1.35v - [email protected] (0.950v) Bios [email protected] x370 Professional Gaming- GSAT 1 Hour - Corsair CMK16GX4M2B3000C15

R7 1700 @ 3.6 Ghz - 2933 MHZ 16-17-17-35-(69-1T) 1.38v - [email protected] Bios [email protected] x370 Professional Gaming- GSAT 1 Hour - Corsair CMK16GX4M2B3000C15

Anyway, Thanks for the update!


----------



## gupsterg

@AlphaC

There is no conclusive setting which I have found which will lower the RAM ns shown in AIDA64 consecutively as you drop the timings. The biggest drop of ns for me on like clocks/timings was when AGESA 1.0.0.4 was introduced. The ~6ns they highlighted meant I was getting ~<70ns, see link heading Let's talk BIOS updates.

Combo of RAM MHz + timings and particular UEFI "optimizations" is basically the "recipe" to gain lower ns and seems some aspects are beyond our control. Even with RAM timings tweaks by using AGESA 1.0.0.6 UEFI. This post by The Stilt has some info.

I have numerous AIDA64 RAM benches, usually take 3 runs for a setup, clearly at times AIDA64 has still erroneous results, even on most current beta (v5.90.4247). I have done a few test runs of Intel Memory Latency Checker, linked in this post by 1TM1, to me currently seems less run to run variance. I also find the GSAT MB/s result also had less run to run variance for like settings, etc.


----------



## Silent Scone

Quote:


> Originally Posted by *LuciferX*
> 
> Sorry to bother you, but the motherboard I used for the tests was an Asrock Fatal1ty X370 Professional Gaming, not an Asus CH6:
> 
> R7 1700 @ Stock 3GHZ (3.2 Full Load) - 2933 MHZ 16-17-17-35-(69-1T) 1.35v - [email protected] (0.950v) Bios [email protected] x370 Professional Gaming-HCI 450/500% Corsair CMK16GX4M2B3000C15
> 
> R7 1700 @ Stock 3GHZ (3.2 Full Load) - 2933 MHZ 16-17-17-35-(69-1T) 1.35v - [email protected] (0.950v) Bios [email protected] x370 Professional Gaming- GSAT 1 Hour - Corsair CMK16GX4M2B3000C15
> 
> R7 1700 @ 3.6 Ghz - 2933 MHZ 16-17-17-35-(69-1T) 1.38v - [email protected] Bios [email protected] x370 Professional Gaming- GSAT 1 Hour - Corsair CMK16GX4M2B3000C15
> 
> Anyway, Thanks for the update!


I did make sure to change that, which is strange. Will do now.


----------



## Nighthog

Quote:


> Originally Posted by *Nighthog*
> 
> 
> 
> [email protected] 0.9v---BIOS F6---HCI---1000%
> 
> CPU VCORE: 1.500V
> Gigabyte GA-AB350-Gaming 3
> 
> CL 14.15.13.(13).24.62.312 2T
> CMK16GX4M2A2666C16R ver 3.21 Micron 2Rx8


With new Agesa code and bios, F7a (1.0.0.6 agesa) I could get some more memory speed from my memory.

[email protected] 1.15v---BIOS F7a---HCI---1200%---CMK16GX4M2A2666C16R



CL 16.17.17.(17).40.62.(340.192.132) 1T @ 1.400V


----------



## gupsterg

Quote:


> Originally Posted by *Silent Scone*
> 
> As said previously, both have their uses. HCI can find errors at the cache/memory interaction. It's possible to run GSAT with very unstable CPU settings, and still pass. Which is also a testament to how well it isolates memory.


I agree after the experience I had recently.

I didn't have an unstable CPU setup as such but I passed 2.5hrs and 2hrs GSAT and failed HCI Memtest. I then went about getting passes in IBT AVX, Y-Cruncher and HCI Memtest still resolutely kept showing an single error. Which for a nut like me is unacceptable, now all sorted







. Info in this post.


----------



## mus1mus

Ryzen 7 1800X @ 4100 1.325V BIOS
TridentZ 3200C14 @ 3466 14-14-14-32-1T 1.45V
Gigabyte K7 BIOS F4d Beta AGESA 1.0.0.6
VSOC 0.996V
VDDP 0.996V
Gear Down
BankGroupSwap Disabled
CLDO_VDDP Voltage 0.975


----------



## III-Method-III

Forgive my ignorance please. Just found this thread and despite reading it all, 80% of it is over my head.

I intend to biy a 1700x or 1800x system fairly soon. For my purposes i will require 32gb ram minimim, 64 would be nice. I do both premierw pro video editing and after effects work.

Reading about 4 or 5 weeks ago it seemed double sided ram didnt clock well on ryzen.

Provided i buy good (recommended) ram for oc and learn what i am doing, what oc can i reasonably expect on 32gb and 64gb on a ryzen system clocking at 3.9 or 4ghz?

What ram would you suggest? I need to mentally prepare for the cost

Meth


----------



## Keith Myers

If you look at post #1 in this thread, you will find your answers in page 2 of the table which covers 32Gb of memory. Page 3 for 64GB is unpopulated so there are no systems reported yet with that amount of memory.


----------



## Spanners

[email protected](Stock)---3466Mhz-C14-14-14-38-1T---1.4v---SOC 1.11v---BIOS F6F---Stressapptest---1 Hour--F4-3200C14-8GFX


----------



## mus1mus

Nice and Purrty @Spanners









3600?


----------



## Spanners

Thanks, I will have a try @3600 eventually, I couldn't get into windows (it would post just BSOD immediately) with auto timings @3466 so I ran that GSAT with 38-52-325 Tras-Trc-Trfc. Everything else auto/xmp. Trying 36-50-300 now.


----------



## mus1mus

Try my values.


----------



## Silent Scone

Nice CPU @mus1mus


----------



## mus1mus

Thanks bud. Got lucky.


----------



## Jpmboy

Quote:


> Originally Posted by *Silent Scone*
> 
> Table updated


nice.. added links to the tables.


----------



## neoHannibal

I am new to the forum and firstly just wanted to say Hi to everyone.

Secondly, to the point of my post. I am thinking about putting together a Ryzen build. It will probably be Ryzen 5 1600 and Asus Prime X370-Pro, but I am sort of on a tight budget and don't want to spend the money on a Samsung B-Die memory (in my country of Poland it costs $200+ for 16 GB). I found this website which from what I understand lists G.Skill RAM modules which are compatibile with Ryzen processors. I found there if I understand it correctly that G.Skill F4-3000C15D-16GVGB (under $150) are made on Hynix M-Die chips. On the top of that page it also says that Hynix M-Die module schould go 3200 MHz. Those G.Skill F4-3000C15D-16GVGB are sold as 3000 MHz so thats all I am hoping for. I just want to make sure that they are compatibile with Ryzen and whether they will work on 3000 MHz? Does anyone here have any experience with the G.Skill F4-3000C15D-16GVGB modules or even any Hynix M-Die memories working with Ryzen CPU? I would be perfectly happy if they go 3000 MHz.

Thanks for any tips.


----------



## AlphaC

neoHannibal , welcome to OCN.









If you update your X370 Prime Pro to the latest BIOS with AGESA 1.0.0.6 you should have better luck with Hynix based DIMMs. No guarantees though all single rank (single sided) DIMMs should hit 2666MHz at the least when only two DIMMs are used. That is the official spec per AMD: 2 single rank DIMMs running dual channel can hit 2666MHz.

For the 3000MHz divider you would get 2933MHz.

see https://www.hardwareluxx.de/community/f219/asus-prime-x370-pro-am4-1156996.html also , as far as I can tell that is the most extensive X370 Prime Pro thread on the Internet right now.

I have a kit of Hynix based DDR4 3200MHz CL16 running at DDR4 3200MHz CL16-18-18-38 so it's definitely possible to have Hynix at 3200MHz. The only difference would be the board used and whether your CPU's IMC (integrated memory controller) is as strong (this is random).

Some Corsair 3200MHz CL16 Hynix kits seem to run at 3200MHz 16-18-18-36 which is slightly different but more or less the same kind of timings except tRAS.


----------



## hsn

[email protected] 1.15v---BIOS 9945---HCI---400%- Gskill f4-3200C14-8GTZSW


----------



## Nighthog

Quote:


> Originally Posted by *Nighthog*
> 
> With new Agesa code and bios, F7a (1.0.0.6 agesa) I could get some more memory speed from my memory.
> 
> [email protected] 1.15v---BIOS F7a---HCI---1200%---CMK16GX4M2A2666C16R
> 
> 
> 
> CL 16.17.17.(17).40.62.(340.192.132) 1T @ 1.400V


Some slight improvement further along.

Now:
3200Mhz CL 14.17.17.(17).40.54.(16).(333.192.132) 1T @ 1.450V


----------



## neoHannibal

I almost ordered G.Skill F4-3000C15D-16GVGB with ASUS PRIME X370-PRO but found that they are no on the QVL list for that motherboard, should I order them anyway?


----------



## yendor

Quote:


> Originally Posted by *neoHannibal*
> 
> I almost ordered G.Skill F4-3000C15D-16GVGB with ASUS PRIME X370-PRO but found that they are no on the QVL list for that motherboard, should I order them anyway?


motherboard qvl's tend to lag. try gskill's side.
it is almost certainly not samsung bdie which is pretty much the best for the platform, any platform actually and gives one the best chance of achieving higher ram speed with ryzen in particular.


----------



## neoHannibal

I know but Samsung B-Die based memory is ober $200 for 2 x 8 GB in my country (Poland). Those G.Skill F4-3000C15D-16GVGB are less than $150 and they are listen in a thread on reddit as Hynix M-Die which is supposed to go 3200 MHz. I am hoping for at least the stock 3000 MHz. Mayby I am better off buying Corsair CMK16GX4M2B3000C15 which are on both thread on reddit and the Asus PRIME X370-Pro QVL list and are also supposedly on Hynix M-Die. What should I do?


----------



## Bloke

A new run:

Bloke - [email protected] - 3200MHz 14-14-14-34 T2 1.35V - SoC 1.1V - bios 0803 - HCI 900% - G.Skill F4-3200C14D-16GFX


----------



## yendor

Quote:


> Originally Posted by *neoHannibal*
> 
> I know but Samsung B-Die based memory is ober $200 for 2 x 8 GB in my country (Poland). Those G.Skill F4-3000C15D-16GVGB are less than $150 and they are listen in a thread on reddit as Hynix M-Die which is supposed to go 3200 MHz. I am hoping for at least the stock 3000 MHz.


There have been positive results on various boards. new agesa making older information less relevant so your hopes are valid.


----------



## MAMOLII

ok yep new agesa made the trick... i can be stable to 2800mhz with 32gb hynix dual rank i could not past 2600 before....
1) tried every ProcODT from the 30-120 range nothing better...nothing auto is fine
2)tried every CLDO_VDDP from 900-1000mv cold booted of course.. nothing auto is fine
3) if i put 2800 cant boot!! if i use 2666 strap+105 bus= 2800 works fine...crazy right?
4)tried soc volts ram volts timmings relaxed.,... nope nope nope
5)turn am4 memory training off and it boot faster and more stable!!!

ok my point is that from 2400-2600 i can be stable now at 2800 mhz with 2666 stap+bus 105... it also works at 2821 with 106 bus..haven't tested above...
all this thanks to new agesa...

but why every tweak that i make didnt made any difference?


----------



## Robenger

Quote:


> Originally Posted by *MAMOLII*
> 
> ok yep new agesa made the trick... i can be stable to 2800mhz with 32gb hynix dual rank i could not past 2600 before....
> 1) tried every ProcODT from the 30-120 range nothing better...nothing auto is fine
> 2)tried every CLDO_VDDP from 900-1000mv cold booted of course.. nothing auto is fine
> 3) if i put 2800 cant boot!! if i use 2666 strap+105 bus= 2800 works fine...crazy right?
> 4)tried soc volts ram volts timmings relaxed.,... nope nope nope
> 5)turn am4 memory training off and it boot faster and more stable!!!
> 
> ok my point is that from 2400-2600 i can be stable now at 2800 mhz with 2666 stap+bus 105... it also works at 2821 with 106 bus..haven't tested above...
> all this thanks to new agesa...
> 
> but why every tweak that i make didnt made any difference?


Whats the AM4 memory training? Because I'm having the exact same issue with my 3200 kit from Corsair.


----------



## MAMOLII

its AM4 Advance Boot Training my fault.. i have an asrosk m/b and this setting is under memory speed i set this to disable


----------



## Robenger

Quote:


> Originally Posted by *MAMOLII*
> 
> its AM4 Advance Boot Training my fault.. i have an asrosk m/b and this setting is under memory speed i set this to disable


Do you know what that feature does?


----------



## MuddyPaws

Quote:


> Originally Posted by *Robenger*
> 
> Do you know what that feature does?


plus 1 I would like to know too


----------



## GamingWiidesire

MSI B350 Tomahawk:

GamingWiidesire--1700[email protected]*1.31V*---SOC 0.96V---BIOS 140---HCI---500%---F4-3200C14D-16GTZ

https://www.pic-upload.de/view-33131442/MSIB350Tomahawk32C143200MHzCL14-13-13-301.31VDRAM0.96VSOC575BenchmarkValidation.png.html

[email protected]*1.20V*---SOC 0.95V---BIOS 140---HCI---2222%---F4-3200C14D-16GTZ

https://www.pic-upload.de/view-33122033/MSIB350Tomahawk32C143200MHzCL16-15-14-321.20VDRAM0.95VSOC2222BenchmarkValidation.png.html

[email protected]*1.23V*---SOC 1.06V---BIOS 141---HCI---1000%---F4-3200C15D-16GTZ

https://www.pic-upload.de/view-33043858/MSIB350Tomahawk3200MHzCL16-15-15-331.23V1000BenchmarkValidation.png.html

[email protected]*1.25V*---SOC 1.0V---BIOS 133---HCI---400%---F4-3600C17D-16GTZ

https://www.pic-upload.de/view-33057923/F4-3600C17D-16GTZ-125V.jpg.html


----------



## papalol1

Anyone with CMK16GX4M2B3200C16 at 3200 on ASUS B350 PRIME PLUS? If so, how. I run max 2933.


----------



## finalheaven

@Silent Scone

Update my chart please:

Using 4 dimms/sticks (4x8GB - 32GB) Samsung B-Die
2 sets of G.Skill F4-3200C14D-16GTZ
Bios 1401
1700 @ 3.8Ghz (P-State Overclock)
Overclocking to Manual

Memory: *3466 @ 14-14-14-14-34-1T (4x8GB)*
CPU Offset @ +0.1v
SOC @ 1.1125v
DDR @ 1.4v
DDR Boot @ 1.4v

GSAT 1 hour

Edit: I'm testing SOC @ 1.1v and it appears to be working. Only passed 30 minutes of GSTA though as I edit this.


----------



## Zorngodofall

Need some advice. I am unable to get my Corsair vengeance LPX up to rated speeds. Running the corsair vengeance LPX 2666 on an ASrock fatal1ty gaming k4 board. Bios P.260. I have tried everything to get this memory past 2400~ it will not post at 2666 no matter what. I tried 1.4, 1.45V 18-18-18-36 timings, gear mode disabled and etc and no luck.

Ram is on QVL as DDR4 2666 8GB Corsair CMK16GX4M2A2666C16 ver:5.29

No idea what the ver 5.29 is. That was not there when I bought my ram.


----------



## phnxblz

Just wanted to add what's working for me as I have been scouring through forums the past couple of weeks just to make sure there was some stability with the Ryzen builds . Freshly bought today, Ryzen 1700X with a gigabyte GA-AX370 Gaming K7, using my Cooler Master 212 EVO from the previous build. Ram is Corsair Vengeance LPX 16GB 3000 CMK16GX4M2B3000C15. Haven't done any burn in tests so I'm not sure how completely stable my overclocks is beside CPU bench and Cinebench.

TLR.

1700x - GA-AX370 Gaming K7 - F4e Bios

Mild Overclock - 3.8ghz 1.35 multiplier - Not really looking to go extreme, just wanting a budget 4K video editing rig that just works.

CMK16GX4M2B3000C15 - XMP Profile 1 loaded. Manual adjusted to 3200. PC powered off and on a couple of times after saving settings on UEFI though no video signal was sent to the monitors, then booted windows without issue straight after.

Windows booted, ran a couple of tests on Cinebench and since then did some editing jobs on Adobe Premiere all day. No crashes.

Hoping someone gets a 32GB DDR4 kit pass 3000 stable enough so I can switch out / add on to soon.


----------



## AlphaC

phnxblz, the powering on and off 3-5 times is normal. It's the memory training process.
Quote:


> Originally Posted by *Zorngodofall*
> 
> Need some advice. I am unable to get my Corsair vengeance LPX up to rated speeds. Running the corsair vengeance LPX 2666 on an ASrock fatal1ty gaming k4 board. Bios P.260. I have tried everything to get this memory past 2400~ it will not post at 2666 no matter what. I tried 1.4, 1.45V 18-18-18-36 timings, gear mode disabled and etc and no luck.
> 
> Ram is on QVL as DDR4 2666 8GB Corsair CMK16GX4M2A2666C16 ver:5.29
> 
> No idea what the ver 5.29 is. That was not there when I bought my ram.


Version determines whether it has Hynix or Samsung ICs


----------



## Scotty99

So my ram seems to be stable at 3066 with xmp timings, 3200 on the other hand...

I can set it to 3200 in the bios, board does a 3 loop reset and i can get into windows. Seems fine once im in windows but once i do a restart or turn my PC off, next time i start my PC it does the same 3x boot loop and resets memory to 2133 lol.

Guess ill have to be ok with 3066 atm, just weird that 3200 does this to so many systems, even after the agesa update.


----------



## finalheaven

@Silent Scone

Further update. After setting ProcODT to 53.3, it appears that I can run 3466:14-14-14-34-1T at lower SOC voltages than I thought. It has now passed 1 hour of GSAT with SOC @ 1.05v. I might try to go even lower, but I expect I'm reaching the limit.

Using 4 dimms/sticks (4x8GB - 32GB) Samsung B-Die
2 sets of G.Skill F4-3200C14D-16GTZ
Bios 1401
1700 @ 3.8Ghz (P-State Overclock)
Overclocking to Manual

Memory: *3466 @ 14-14-14-14-34-1T (4x8GB)*
SOC @ 1.05v
DDR @ 1.4v
DDR Boot @ 1.4v
ProcODT @ 53.3

GSAT 1 hour


----------



## AlphaC

On hardwareluxx's thread for X370 Prime Pro they list the following ProcODT:
Samsung B (SR) 2x8GB 53.3 Ohm
Samsung B (DR) 2x16GB 80/96 Ohm
Samsung B (DR) 4x16GB 43.6 Ohm
Hynix A (DR) 2x8GB 53.3 Ohm
Hynix A (DR) 4x8GB 40 Ohm

I'm not quite sure where the numbers are from


----------



## Silent Scone

Quote:


> Originally Posted by *finalheaven*
> 
> @Silent Scone
> 
> Further update. After setting ProcODT to 53.3, it appears that I can run 3466:14-14-14-34-1T at lower SOC voltages than I thought. It has now passed 1 hour of GSAT with SOC @ 1.05v. I might try to go even lower, but I expect I'm reaching the limit.
> 
> Using 4 dimms/sticks (4x8GB - 32GB) Samsung B-Die
> 2 sets of G.Skill F4-3200C14D-16GTZ
> Bios 1401
> 1700 @ 3.8Ghz (P-State Overclock)
> Overclocking to Manual
> 
> Memory: *3466 @ 14-14-14-14-34-1T (4x8GB)*
> SOC @ 1.05v
> DDR @ 1.4v
> DDR Boot @ 1.4v
> ProcODT @ 53.3
> 
> GSAT 1 hour


Ok, thanks for the update, very nice result


----------



## mus1mus

Quote:


> Originally Posted by *phnxblz*
> 
> Just wanted to add what's working for me as I have been scouring through forums the past couple of weeks just to make sure there was some stability with the Ryzen builds . Freshly bought today, Ryzen 1700X with a gigabyte GA-AX370 Gaming K7, using my Cooler Master 212 EVO from the previous build. Ram is Corsair Vengeance LPX 16GB 3000 CMK16GX4M2B3000C15. Haven't done any burn in tests so I'm not sure how completely stable my overclocks is beside CPU bench and Cinebench.
> 
> TLR.
> 
> 1700x - GA-AX370 Gaming K7 - F4e Bios
> 
> Mild Overclock - 3.8ghz 1.35 multiplier - Not really looking to go extreme, just wanting a budget 4K video editing rig that just works.
> 
> CMK16GX4M2B3000C15 - XMP Profile 1 loaded. Manual adjusted to 3200. PC powered off and on a couple of times after saving settings on UEFI though no video signal was sent to the monitors, then booted windows without issue straight after.
> 
> Windows booted, ran a couple of tests on Cinebench and since then did some editing jobs on Adobe Premiere all day. No crashes.
> 
> Hoping someone gets a 32GB DDR4 kit pass 3000 stable enough so I can switch out / add on to soon.


Giga has no issues running 4*8GB sticks past 3000. It's spending the time to know what works best for your set-up that is critical.

Check the main page. You'd find 4*8GB sticks running 3200 on relaxed timings being cheapo RipjawZ.


----------



## gupsterg

Quote:


> Originally Posted by *AlphaC*
> 
> On hardwareluxx's thread for X370 Prime Pro they list the following ProcODT:
> Samsung B (SR) 2x8GB 53.3 Ohm
> Samsung B (DR) 2x16GB 80/96 Ohm
> Samsung B (DR) 4x16GB 43.6 Ohm
> Hynix A (DR) 2x8GB 53.3 Ohm
> Hynix A (DR) 4x8GB 40 Ohm
> 
> I'm not quite sure where the numbers are from


IMO all from Elmor except Samsung B (DR) 2x16GB 96 Ohm, which was from







The Stilt







. Plenty of non C6H owners view the C6H thread







.


----------



## phnxblz

Quote:


> Originally Posted by *mus1mus*
> 
> Giga has no issues running 4*8GB sticks past 3000. It's spending the time to know what works best for your set-up that is critical.
> 
> Check the main page. You'd find 4*8GB sticks running 3200 on relaxed timings being cheapo RipjawZ.


Thank you for the reminder. I noticed that the page was updated since I last saw it. Thanks to all the contributors for this list.

It's a good option for short-term reaching 32GB and over 3000. Though long term, I would like to be able to stuff the build with 64GB of ram when I do more lengthy 4K editing. I would like to upgrade the ram to 32GB now with a 2*16GB, and another 32GB via 2*16 after upgrading the expensive camera gear and lenses.








the costs of getting up there to create high quality media content.


----------



## yendor

Quote:


> Originally Posted by *AlphaC*
> 
> On hardwareluxx's thread for X370 Prime Pro they list the following ProcODT:
> Samsung B (SR) 2x8GB 53.3 Ohm
> Samsung B (DR) 2x16GB 80/96 Ohm
> Samsung B (DR) 4x16GB 43.6 Ohm
> Hynix A (DR) 2x8GB 53.3 Ohm
> Hynix A (DR) 4x8GB 40 Ohm
> 
> I'm not quite sure where the numbers are from


Some of the recommendations for procodt are more board specific. Not many hammering away at enough different kits with multiple boards who could say .. could think of two though .... >. >


----------



## papalol1

ASUS B350 PRIME PLUS

Anyone managed to get CMK16GX4M2B3200C16 Corsair LPX 3200 2x8 CL16 at 3066+ stable? I don't manage to do it.


----------



## Silent Scone

Quote:


> Originally Posted by *papalol1*
> 
> ASUS B350 PRIME PLUS
> 
> Anyone managed to get CMK16GX4M2B3200C16 Corsair LPX 3200 2x8 CL16 at 3066+ stable? I don't manage to do it.


Hi, why at that ratio?

There is someone using that kit in the results table at 3200.


----------



## finalheaven

Is there a way for us to update the first page chart? Or can that only be done by you?

SOC at 1.025v failed for 32GB (4x8) 3466:14-14-14-14-34-1T.

Did not test anything between 1.025v-1.05v though. Will most likely keep 1.05v as my 24/7. Pretty damn surprised 3466-14-14-14-14-34-1T is stable using 4 dimms and 1.05v SOC.


----------



## otto jarvis

Otto [email protected] 1.1250v---BIOS 2.4---GSAT---1 Hour
CMK16GX4M2B3000C15 Version 5.39


----------



## Secret Dragoon

ProcODT is board specific, I use 60Ω for my 2x8GB B-Die kit.


----------



## Scotty99

http://i.imgur.com/b6uEuA7.png

First time ever seeing this on a PC. RMA time?

3066/1.35v/1.1 SoC/16-18-18-38 timings.CPU was at 1.344v, 3.8ghz.


----------



## yendor

Quote:


> Originally Posted by *Scotty99*
> 
> http://i.imgur.com/b6uEuA7.png
> 
> First time ever seeing this on a PC. RMA time?
> 
> 3066/1.35v/1.1 SoC/16-18-18-38 timings.CPU was at 1.344v, 3.8ghz.


means is unstable, not necessarily that ram is bad. The settings that produced this could run and appear fine for a long time without revealing themselves til one day something's not working right and you can't pin it down...


----------



## Scotty99

Quote:


> Originally Posted by *yendor*
> 
> means is unstable, not necessarily that ram is bad. The settings that produced this could run and appear fine for a long time without revealing themselves til one day something's not working right and you can't pin it down...


Yup, im gonna try and weasel my way out of a bdie kit from gskill either way with that screenshot lol.


----------



## gupsterg

Quote:


> Originally Posted by *Secret Dragoon*
> 
> ProcODT is board specific, I use 60Ω for my 2x8GB B-Die kit.


I have been on 60Ω for my 2x8GB B-Die kit on C6H for several days now







. Reason can be found in OP of this thread section > RAM Info / Data Fabric (DFICLK) / Memory Stability testing >







The Stilt's







DDR4 Timings







.


----------



## papalol1

Quote:


> Originally Posted by *Silent Scone*
> 
> Hi, why at that ratio?
> 
> There is someone using that kit in the results table at 3200.


What? I don't understand.


----------



## Silent Scone

Quote:


> Originally Posted by *papalol1*
> 
> What? I don't understand.


Would you not rather run the kit at 3200? As mentioned previously, there is one other user who's submitted a result using that kit running stable at 3200, however, not on that board. You'd need to start by listing your components and current settings


----------



## Silent Scone

Quote:


> Originally Posted by *finalheaven*
> 
> Is there a way for us to update the first page chart? Or can that only be done by you?
> 
> SOC at 1.025v failed for 32GB (4x8) 3466:14-14-14-14-34-1T.
> 
> Did not test anything between 1.025v-1.05v though. Will most likely keep 1.05v as my 24/7. Pretty damn surprised 3466-14-14-14-14-34-1T is stable using 4 dimms and 1.05v SOC.


Only by me. Trick is to not get too excited, and post when you are done tweaking


----------



## SlushPuppy007

Has anyone hit DDR4 @ 4000MHz+ with Ryzen yet?


----------



## Medusa666

Any ideas or advice on getting a pair of Samsung b-die 3600MHz rated G.Skill memory sticks above 3200MHz?

http://gskill.com/en/product/f4-3600c16d-16gvk

Right now I'm running them 3200MHz, 14-14-14-14-36 with 1,35v RAM voltage and 1,125v on SOC.


----------



## yendor

Quote:


> Originally Posted by *Medusa666*
> 
> Any ideas or advice on getting a pair of Samsung b-die 3600MHz rated G.Skill memory sticks above 3200MHz?
> 
> http://gskill.com/en/product/f4-3600c16d-16gvk
> 
> Right now I'm running them 3200MHz, 14-14-14-14-36 with 1,35v RAM voltage and 1,125v on SOC.


Board, bios? sig rig! your x99 looks sweet. Sold?


----------



## Medusa666

Quote:


> Originally Posted by *yendor*
> 
> Board, bios? sig rig! your x99 looks sweet. Sold?


Oh, yeah I forgot the important stuff lol









Board is MSI B350 Tomahawk with a R7 1700, latest beta bios of version 1.64.

The sig rig was amazing, X99 but I sold it now to prepare for Threadripper or X299!


----------



## Silent Scone

Quote:


> Originally Posted by *SlushPuppy007*
> 
> Has anyone hit DDR4 @ 4000MHz+ with Ryzen yet?


I think you've got more chance of winning the lottery.


----------



## Secret Dragoon

Quote:


> Originally Posted by *gupsterg*
> 
> I have been on 60Ω for my 2x8GB B-Die kit on C6H for several days now
> 
> 
> 
> 
> 
> 
> 
> . Reason can be found in OP of this thread section > RAM Info / Data Fabric (DFICLK) / Memory Stability testing >
> 
> 
> 
> 
> 
> 
> 
> The Stilt's
> 
> 
> 
> 
> 
> 
> 
> DDR4 Timings
> 
> 
> 
> 
> 
> 
> 
> .


Geeze if I had seen this sooner I wouldn't have asked so many stupid questions. Why is this in an ASUS specific thread?


----------



## gupsterg

I would hazard a guess at that due to the mobo used by







The Stilt







for the test setup he posted it there







. He has several boards, he is in several threads plus he has several RAM kits, etc. I have no idea why he used what he did vs other HW either







.


----------



## Secret Dragoon

Sorry for the long, long delay. I think I said I'd do this two months ago:



Secret [email protected] 1.15v---BIOS F4d---W10GSAT---1 Hour---F4-3600C16D-16GTZR

@Silent Scone



Spoiler: Warning: Spoiler!



Also to the person who said no board besides the C6H can do 3433+.Don't tell me I can't do something.


----------



## gupsterg

Nice result







.


----------



## Silent Scone

Quote:


> Originally Posted by *Secret Dragoon*
> 
> Sorry for the long, long delay. I think I said I'd do this two months ago:
> 
> 
> 
> Secret [email protected] 1.15v---BIOS F4d---W10GSAT---1 Hour---F4-3600C16D-16GTZR
> 
> @Silent Scone
> 
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> Also to the person who said no board besides the C6H can do 3433+.Don't tell me I can't do something.


Nice work, have you tried working on 1T?


----------



## Secret Dragoon

Quote:


> Originally Posted by *Silent Scone*
> 
> Nice work, have you tried working on 1T?


With the nature of the test, and the lack of an additional computer It's a very boring hour while the test is running.
It would probably work. I usually use 1T / much tighter timings when I am doing benchmarks.


----------



## Silent Scone

Quote:


> Originally Posted by *Secret Dragoon*
> 
> With the nature of the test, and the lack of an additional computer It's a very boring hour while the test is running.
> It would probably work. I usually use 1T / much tighter timings when I am doing benchmarks.


lol, yes it can be a chore when you have things to use the machine for. Best to let it run when you're AFK.


----------



## jclafi

Ryzen R7 1700 memory test ! Great performance gains from DDR4 2133 to 3200 !

https://www.youtube.com/watch?v=1zRFm0YVQ8M&feature=em-subs_digest


----------



## SlushPuppy007

Ordered a kit of G.Skill 2 x 8GB DDR4 4266MHz RAM to go with an ASRock X370 Taichi + 1700X on a custom liquid cooling loop.

RAM: https://www.gskill.com/en/product/f4-4266c19d-16gtzr

Aiming for at least 4GHz on both the RAM and the CPU.

Will post all the crap here.


----------



## baii

Bought trident z 16gb yellow black 3200 16 18 18 shellshocker 107usd and these's don't even run 2933 on b350 pro4. It boot but the board back them to single channel mode. These a hynix m die.

On the other hand, I got a pair of jidec 2400 oem hynix a die and I am able to get 2933 16 16 16.

So m die sucks?


----------



## Silent Scone

Quote:


> Originally Posted by *SlushPuppy007*
> 
> Ordered a kit of G.Skill 2 x 8GB DDR4 4266MHz RAM to go with an ASRock X370 Taichi + 1700X on a custom liquid cooling loop.
> 
> RAM: https://www.gskill.com/en/product/f4-4266c19d-16gtzr
> 
> Aiming for at least 4GHz on both the RAM and the CPU.
> 
> Will post all the crap here.


Both are optimistic, memory more so. 3600Mhz is the maximum obtainable frequency one can expect on DRAM. However, that kit should get you 3466 - 3500 with good timings once dialled in correctly on the right board.


----------



## jclafi

Wrong attitude !

Dont set targets, don't set goals, just buy a decent hardware and try to get the most of it.

A R7 1700X @ 3.9Ghz on all cores and DDR4 3200 with decent timmings will be a killer machine. Update the motherboard BIOS to get the most of the memory. Under USB boot.

Enjoy !


----------



## Silent Scone

Quote:


> Originally Posted by *jclafi*
> 
> Wrong attitude !
> 
> Dont set targets, don't set goals, just buy a decent hardware and try to get the most of it.
> 
> A R7 1700X @ 3.9Ghz on all cores and DDR4 3200 with decent timmings will be a killer machine. Update the motherboard BIOS to get the most of the memory. Under USB boot.
> 
> Enjoy !


lol, good attitude towards life. Sadly all the aspiration in the world won't get you 4000MHz on the memory side on X370


----------



## Secret Dragoon

My advice is to research and just have fun. I bought a 3600 kit knowing full well it was limited to 3200 and when AGESA 1006 came out my investment came true. The problem now is that we don't know if the IMC can handle much more than 3600 (Which is okay).

Last night I was struggling to post 3733. I managed to train, but POST kept on hanging on different error codes. Not fun =(


----------



## papalol1

Quote:


> Originally Posted by *Silent Scone*
> 
> Would you not rather run the kit at 3200? As mentioned previously, there is one other user who's submitted a result using that kit running stable at 3200, however, not on that board. You'd need to start by listing your components and current settings


I already put my components.
Ryzen [email protected]
ASUS B350 PLUS PRIME
CMK16GX4M2B3200C16 Corsair LPX 3200 2x8 CL16

I tried both 3066 and 3200 so wanted to go step by step but none of those work.Stuck at 2933.

Settings, i tried some on default with D.O.C.P only and it didn't boot and i tried some with 1.4-1.45 voltage on DRAM but it doesn't boot. It says NO KEYBOARD DETECTED and doesn't boot.

I managed to boot 3066 one time but it freeze after each 3 secs


----------



## Robenger

Quote:


> Originally Posted by *papalol1*
> 
> I already put my components.
> Ryzen [email protected]
> ASUS B350 PLUS PRIME
> CMK16GX4M2B3200C16 Corsair LPX 3200 2x8 CL16
> 
> I tried both 3066 and 3200 so wanted to go step by step but none of those work.Stuck at 2933.
> 
> Settings, i tried some on default with D.O.C.P only and it didn't boot and i tried some with 1.4-1.45 voltage on DRAM but it doesn't boot. It says NO KEYBOARD DETECTED and doesn't boot.
> 
> I managed to boot 3066 one time but it freeze after each 3 secs


Same kit, same issue, but different mobo.


----------



## papalol1

Quote:


> Originally Posted by *Robenger*
> 
> Same kit, same issue, but different mobo.


We are ****ed bro haha







do you have the NO KEYBOARD issue when trying to go up?


----------



## Robenger

Quote:


> Originally Posted by *papalol1*
> 
> We are ****ed bro haha
> 
> 
> 
> 
> 
> 
> 
> do you have the NO KEYBOARD issue when trying to go up?


No, I haven't had that issue, but 2933 is the absolute max.


----------



## wolfpack122

[email protected] 1.16v---BIOS 9943---Stressapptest---1 Hour--F4-3200C14D-16GTZ





Spoiler: AIDA64 Cache & Memory Benchmark at 3.9 GHz:


----------



## IRobot23

Maybe I missed,but does anyone use?
https://www.mindfactory.de/product_info.php/8GB-TeamGroup-Dark-Pro-rot-DDR4-3000-DIMM-CL15-Dual-Kit_1026759.html
http://pdfs.icecat.biz/pdf/49994795-3318.pdf?access=j9GyMDwIDpAApzH6OHehgnQVNQzRG86Kyn9x4QQNYxaE80JbjqTGPnta1uIgA6Hb


----------



## Silent Scone

Quote:


> Originally Posted by *papalol1*
> 
> I already put my components.
> Ryzen [email protected]
> ASUS B350 PLUS PRIME
> CMK16GX4M2B3200C16 Corsair LPX 3200 2x8 CL16
> 
> I tried both 3066 and 3200 so wanted to go step by step but none of those work.Stuck at 2933.
> 
> Settings, i tried some on default with D.O.C.P only and it didn't boot and i tried some with 1.4-1.45 voltage on DRAM but it doesn't boot. It says NO KEYBOARD DETECTED and doesn't boot.
> 
> I managed to boot 3066 one time but it freeze after each 3 secs


Not used that board. Have you tried adjusting ODT values? This can still very much make or break POST settings. Start with a value of 80 Ohms and work from there.

Quote:


> Originally Posted by *IRobot23*
> 
> Maybe I missed,but does anyone use?
> https://www.mindfactory.de/product_info.php/8GB-TeamGroup-Dark-Pro-rot-DDR4-3000-DIMM-CL15-Dual-Kit_1026759.html
> http://pdfs.icecat.biz/pdf/49994795-3318.pdf?access=j9GyMDwIDpAApzH6OHehgnQVNQzRG86Kyn9x4QQNYxaE80JbjqTGPnta1uIgA6Hb


Not sure, maybe ask in the Ryzen Owners or the CH6 thread

Quote:


> Originally Posted by *wolfpack122*
> 
> [email protected] 1.16v---BIOS 9943---Stressapptest---1 Hour--F4-3200C14D-16GTZ
> 
> 
> 
> 
> 
> Spoiler: AIDA64 Cache & Memory Benchmark at 3.9 GHz:


Nice, thanks for sharing


----------



## papalol1

Quote:


> Originally Posted by *Silent Scone*
> 
> Not used that board. Have you tried adjusting ODT values? This can still very much make or break POST settings. Start with a value of 80 Ohms and work from there.
> Not sure, maybe ask in the Ryzen Owners or the CH6 thread
> Nice, thanks for sharing


I saw on Youtube something from AMD guy saying not going more than 40~60ohms on that setting? I didn't try that one.


----------



## gupsterg

Quote:


> Originally Posted by *wolfpack122*
> 
> [email protected] 1.16v---BIOS 9943---Stressapptest---1 Hour--F4-3200C14D-16GTZ
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Spoiler: AIDA64 Cache & Memory Benchmark at 3.9 GHz:


+rep, thank you for share







.


----------



## Silent Scone

Quote:


> Originally Posted by *papalol1*
> 
> I saw on Youtube something from AMD guy saying not going more than 40~60ohms on that setting? I didn't try that one.


That can be ignored. Gross misinformation unfortunately for AMD. There's no reason not to use higher values


----------



## Nighthog

More improvement for me on Micron dual-ranks.

1200%


[email protected] 1.15v---BIOS F7a---HCI---1200%---CMK16GX4M2A2666C16R

13.17.(13).17.30.44.(12)...(320)... 1T

I've been testing 3333Mhz but not gotten it error free yet.

EDIT: 1200%


----------



## nexxusty

Having a hell of a time getting anything decent out of my 3600mhz C16 B-Die's.

It has to be this motherboard..... I can BARELY run 3200mhz 16-16-16-36-2T @ 1.35v.

AGESA 1.0.0.6 BIOS installed. Board is X370 Killer SLi.

Any tips would be appreciated but man... I think I've tried everything.

SoC voltage from 1.1v to 1.2v did nothing. Didnt go higher for obvious reasons. At a loss lol. ASRock letting me down bigtime here.


----------



## gupsterg

The B dies are good but be aware they are certified on Intel platform. Even then depending on a Intel CPU / motherboard sample used it may not be easily attained. Silent Scone was also running the Intel version of this thread so his viewpoint will be better than most can give.

Users that gain 3600MHz on Ryzen you will note end up giving higher VDIMM than 1.35V. So you may need to look into upping that.

Also it seems on Ryzen upto 3466MHz is more of a realistic expectation depending on CPU/RAM/mobo sample used. Plus firmware is playing a big part, besides user settings. Perhaps Asrock FW not there yet fully for all their boards. So a case of waiting.

AGESA 1.0.0.6 RC4 has been released on C6H. This has a section called CAD Bus configuration, these settings may aid attaining higher RAM MHz. Even that UEFI is not ideal yet, as stated by someone who has better knowledge/experience. So still a waiting game for next AGESA.


----------



## yendor

Quote:


> Originally Posted by *nexxusty*
> 
> Having a hell of a time getting anything decent out of my 3600mhz C16 B-Die's.
> 
> It has to be this motherboard..... I can BARELY run 3200mhz 16-16-16-36-2T @ 1.35v.
> 
> AGESA 1.0.0.6 BIOS installed. Board is X370 Killer SLi.
> 
> Any tips would be appreciated but man... I think I've tried everything.
> 
> SoC voltage from 1.1v to 1.2v did nothing. Didnt go higher for obvious reasons. At a loss lol. ASRock letting me down bigtime here.


AMD's recommendation for max vdimm is no more than 1.5. More knowledgeable users have suggested 1.45+ sees diminshing returns for bdie though I've gotten positive results at 1.5 not possible at 1.45.

So. amd thinks 1.5 vdimm is safe for cpu side. bdie handles more . somewhere between 1.35 and 1.5 may yield better results. Give it a whirl.


----------



## gavinh87

I stupidly left the timing off the screenshot but you can see in task manager I'm running 3466.
Timings are 14-14-14-34-1T, rest are auto.
1.33v 3.8ghz 1700
1.4v dram
1.1 SoC
Rest is pretty much auto.


----------



## SlushPuppy007

Quote:


> Originally Posted by *Silent Scone*
> 
> Both are optimistic, memory more so. 3600Mhz is the maximum obtainable frequency one can expect on DRAM. However, that kit should get you 3466 - 3500 with good timings once dialled in correctly on the right board.


Maximum obtainable DRAM freq right now, yes. AGESA still young. Board is the all round favourite ASRock Taichi. AMD got a solid memory controller on Ryzen, firmware will fix this.


----------



## Praz

Quote:


> Originally Posted by *SlushPuppy007*
> 
> Maximum obtainable DRAM freq right now, yes. AGESA still young. Board is the all round favourite ASRock Taichi. AMD got a solid memory controller on Ryzen, firmware will fix this.


Hello

That AGESA 1.0.0.6 results in a substantial decrease in memory performance in order to provide an increase in memory frequency speaks volumes of the capability of the IMC. When posting baseless opinions or wishlists it should not be done under the illusion of fact.


----------



## yendor

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> That AGESA 1.0.0.6 results in a substantial decrease in memory performance in order to provide an increase in memory frequency speaks volumes of the capability of the IMC. When posting baseless opinions or wishlists it should not be done under the illusion of fact.


eh. stuck on 1.0.0.4 based bios here. would not know yet though I've come to dislike 'improves memory compatibility" in the bios notes... slower.. up, down, sideways. every time. I keep wondering if the next bios will finally make 3200 faster than 2933... I'd have to dig or flash back but iirc even with launch bios the lower frequency performed better.


----------



## Zioa

[email protected] 14 14 28 42 T1-- 1.45V ----SOC 1.15V----Bios 1401---HCI---400%--F4-3200C14D-16GTZR

http://s1195.photobucket.com/user/Zio111/media/ram3466.jpg.html

http://s1195.photobucket.com/user/Zio111/media/aida 3466 new.jpg.html


----------



## SlushPuppy007

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> That AGESA 1.0.0.6 results in a substantial decrease in memory performance in order to provide an increase in memory frequency speaks volumes of the capability of the IMC. When posting baseless opinions or wishlists it should not be done under the illusion of fact.


Dont know what you on about mate or where you got that bad information, but increasing memory freq increases memory performance when sticking with respectable timings.

AMD wont stop releasing AGESA updates anytime soon. Seeing people are already getting a 1700 to 3.9GHz with RAM @ 3600MHz, that means a lot, 4000MHz should be possible down the road (maybe not now, but we'll get there).

Will keep you posted on my progress.


----------



## Salva52

There are a small drop performances in benchs gaming and realbench from 1004a to 1006 with same ram frequency and timings.


----------



## bluej511

Quote:


> Originally Posted by *SlushPuppy007*
> 
> Dont know what you on about mate or where you got that bad information, but increasing memory freq increases memory performance when sticking with respectable timings.
> 
> AMD wont stop releasing AGESA updates anytime soon. Seeing people are already getting a 1700 to 3.9GHz with RAM @ 3600MHz, that means a lot, 4000MHz should be possible down the road (maybe not now, but we'll get there).
> 
> Will keep you posted on my progress.


He's right and he knows what hes on about because he tested it. There is a noticeable difference in SOME games and benchmarks between 1.0.4 and 1.0.6. Why? Because AMD had to slacken some timings to get more memory kits and higher speeds to work. In doing some its affected performance. Its not misinformation.

This is where timing comes more into affect then actual speed. I can do 14-16-16-34 compare to 16-18-18-36 (75t and 312t on both) but those settings immediately fail on 1.0.0.6, so id rather take my tight timings then a newer BIOS thats a total fail for my RAM.


----------



## Skrzypiec

Hello








Anybody testing RAM overclocking with B350 Tomahawk? Does it even make sense compared to the mobos listed?
I consider Tomahawk since it sounds perfect to run a DAW, but I wonder if there's some extra headroom if I need it.
Thanks


----------



## Silent Scone

Quote:


> Originally Posted by *SlushPuppy007*
> 
> AMD wont stop releasing AGESA updates anytime soon. Seeing people are already getting a 1700 to 3.9GHz with RAM @ 3600MHz, that means a lot, 4000MHz should be possible down the road (maybe not now, but we'll get there).


Yes, they will. On Skylake-X.


----------



## SlushPuppy007

Quote:


> Originally Posted by *Silent Scone*
> 
> Yes, they will. On Skylake-X.


Skylake X got issues of its own.

I'm totally calm about the whole ryzen memory story, if the current ryzen generation will not do 4000MHz+ on memory, the ryzen refresh will.

But before settling on anything less, I'm definitely gonna give it my all.


----------



## yendor

Quote:


> Originally Posted by *SlushPuppy007*
> 
> Skylake X got issues of its own.
> 
> I'm totally calm about the whole ryzen memory story, if the current ryzen generation will not do 4000MHz+ on memory, the ryzen refresh will.
> 
> But before settling on anything less, I'm definitely gonna give it my all.


grin, you are not the only person trying, we're just not talking about it. I expect much fail and will take whatever I can scoop off the table.
Yeah the performance has gone down. But just as the changes have made wider compatibility possible future changes may increase performance again. It's not written in stone that amd will stick with agesa that hurts performance once it achieves an actually useful goal in higher ram speed. It is , despite the penalty. worthwhile for them and their customer base, for now.


----------



## Hequaqua

Hequaqua--R5 [email protected] 1.050v---BIOS 1.3---HCI---400%---CMK16GX2B3200C16(Corsair)



I think I did this correctly. I'm waiting on a bios update, hopefully, that will get me to the 3200mhz.









EDIT:

Hequaqua--R5 [email protected] 1.050v---BIOS 1.3---Stressapptest---1 Hour---CMK16GX2B3200C16(Corsair)


----------



## wolfpack122

I did some tests after reading Praz's post.
Below are the best memory speed and timings I can get on 1201 and 9943 without exceeding 1.2V on the SoC and 1.5V on the DRAM.
I didn't bother testing the stability on 1201 as it didn't yield better results.
Changing the command rate to 2T enabled me to tighten a lot of the sub-timings on 9943.



Spoiler: BIOS 1201 - 3600 14-14-14-14-34-1T BankGroupSwap disabled:





Highest score from 3 runs:






Spoiler: BIOS 9943 - 3600 16-16-16-16-22-2T BankGroupSwap disabled:





Lowest score from 3 runs:


----------



## Praz

Quote:


> Originally Posted by *wolfpack122*
> 
> I did some tests after reading Praz's post.
> Below are the best memory speed and timings I can get on 1201 and 9943 without exceeding 1.2V on the SoC and 1.5V on the DRAM.
> I didn't bother testing the stability on 1201 as it didn't yield better results.
> Changing the command rate to 2T enabled me to tighten a lot of the sub-timings on 9943.
> 
> 
> 
> Spoiler: BIOS 1201 - 3600 14-14-14-14-34-1T BankGroupSwap disabled:
> 
> 
> 
> 
> 
> Highest score from 3 runs:
> 
> 
> 
> 
> 
> 
> Spoiler: BIOS 9943 - 3600 16-16-16-16-22-2T BankGroupSwap disabled:
> 
> 
> 
> 
> 
> Lowest score from 3 runs:


Hello

You need to compare to 1401. That's where memory frequency capability increases and memory performance goes downhill.


----------



## wolfpack122

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> You need to compare to 1401. That's where memory frequency capability increases and memory performance goes downhill.


Yes, I couldn't get any decent timings on 1401 which is why I went back to 9943.
I'll flash 1401 again later and retest.


----------



## 5ekundes

Hello just a question.

Memtest86 is displaying incorrect ram info. What should I do?


----------



## wolfpack122

Quote:


> Originally Posted by *5ekundes*
> 
> Hello just a question.
> 
> Memtest86 is displaying incorrect ram info. What should I do?


You can use MemTest by HCI or install 'Bash on Ubuntu on Windows 10' and run Google's 'stressapptest'.
Instructions for both are on the first post of this thread.


----------



## gupsterg

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> You need to compare to 1401. That's where memory frequency capability increases and memory performance goes downhill.


So is AGESA 1.0.0.6 RC4 then final release for that AGESA version or we likely to see another iteration prior to next version of AGESA (ie 1.0.0.7+)?

I'm currently sticking to UEFI 9943 with AGESA 1.0.0.6.


----------



## wolfpack122

Is it possible to get worse performance from tightening any of the memory's timings too much, even while passing stress tests?


----------



## nelsonconta1

hello, im building a Ryzen 1400 + asus prime b350m-k . Can you guys give me a recomendation on what Ram sticks brand and mhz i should buy to reach higher clocks. thanks )


----------



## gupsterg

You would want Samsung B die RAM IC on RAM kit, ideally single rank so 2x 8GB kit, ref this thread







.


----------



## Jpmboy

Quote:


> Originally Posted by *wolfpack122*
> 
> Is it possible to get worse performance from tightening any of the memory's timings too much, even while passing stress tests?


Absolutely. Some timings are dependent upon other operations completing, or some can close a window/bank before the necessary operations complete... these timing mismatches (probably best explained by someone like Raja) do not necessarily lead to error/stability issues, but will reduce efficiency.


----------



## SaccoSVD

Quote:


> Originally Posted by *Jpmboy*
> 
> Absolutely. Some timings are dependent upon other operations completing, or some can close a window/bank before the necessary operations complete... these timing mismatches (probably best explained by someone like Raja) do not necessarily lead to error/stability issues, but will reduce efficiency.


Is there any way to automate finding working sub timings as much as possible? or is it entirely die dependant?

I assume a company like Hynix have automated clock and timing machines to find them.


----------



## Silent Scone

Depends on the strength of the IMC, DRAM modules and motherboard in question. Ryzen does not have a particularly strong IMC, at least not compared to Broadwell-E >


----------



## Scotty99

Its still not bad tho, ive gotten a really cheap pair of 3200 hynix stable at 2933 cas 15. Obviously Bdie seem to work better, but from a price/performance standpoint Bdie isnt winning.


----------



## gupsterg

Quote:


> Originally Posted by *Silent Scone*
> 
> Depends on the strength of the IMC, DRAM modules and motherboard in question. Ryzen does not have a particularly strong IMC, at least not compared to Broadwell-E >


I doubt we can say at the moment it doesn't have a great IMC. The platform is too new and firmware not as developed IMO.

Prior to AEGA 1.0.0.6 all my CPUs were stuck at below 3200MHz. Only after that UEFI I've had ~3500MHz stable and 3600MHz post/OS stable.

1.0.0.6 RC4 has some new options which should once explored and user experience shared on how they gain x by setting x we may see some more gains.

Yes RC4 maybe a tad slower than intial release, but gonna test that today. In case situations I explored on 1.0.0.6 I'd say no performance loss and gains on MHz attained.

Then I recall at one point near launch discussions that Ryzen was being more efficient with RAM than Intel, I'll try dig up that info.


----------



## Silent Scone

Quote:


> Originally Posted by *Scotty99*
> 
> Its still not bad tho, ive gotten a really cheap pair of 3200 hynix stable at 2933 cas 15. Obviously Bdie seem to work better, but from a price/performance standpoint Bdie isnt winning.


It's now becoming less about a compatibility standpoint as things progress. The ability to run good subtimings with bdie is somewhat lost on this platform
Quote:


> Originally Posted by *gupsterg*
> 
> I doubt we can say at the moment it doesn't have a great IMC. The platform is too new and firmware not as developed IMO.
> 
> Prior to AEGA 1.0.0.6 all my CPUs were stuck at below 3200MHz. Only after that UEFI I've had ~3500MHz stable and 3600MHz post/OS stable.
> 
> 1.0.0.6 RC4 has some new options which should once explored and user experience shared on how they gain x by setting x we may see some more gains.
> 
> Yes RC4 maybe a slower tgan intial release, but gonna test that today. In case situation I explored on 1.0.0.6 I'd say no performance loss and gains on MHz attained.
> 
> Then I recall at one point near launch discussions that Ryzen was being more efficient with RAM than Intel, I'll try dig up that info.


Not a lot will change from here on in. If we only take frequency into account - as we've seen with recent updates - this doesn't necessarily mean performance is improved. That's not to say things are bad in this particular area, only that if the competition is the benchmark, then there's an obvious disparity


----------



## gupsterg

Quote:


> Originally Posted by *Silent Scone*
> 
> The ability to run good subtimings with bdie is somewhat lost on this platform


I disagree, respectfully







.


----------



## Silent Scone

Quote:


> Originally Posted by *gupsterg*
> 
> I disagree, respectfully
> 
> 
> 
> 
> 
> 
> 
> .


Heh, well can you run subtimings at or very close to the minimal spacing required by the chipset at 3200-3400 speeds?


----------



## gupsterg

Originally the word was "good"







.

Now "at or very close to the minimal spacing"







.

For the definition of "good" I disagreed, respectfully







.

I would concur that when we get to "at or close to the minimal spacing" Ryzen is currently exhibiting issue







.

Then we are back at "efficiency". If one platform is inefficient then it may allow lower/lowest timings. A more efficient platform may not.

Then just like I commented on







The Stilt's







recent RAM scaling graph and a past post. Each user may find if they can't attain x then y will be optimal.

Placing emphasis on timings can at times be futile depending on case situation. We only need to look at how we go about sometimes trying to see the scaling.

For example in my thread is a table of 2400MHz vs 2800MHz vs 3200MHz vs 3333MHz using same timings, but as you would be aware timings is just a delay figure and true latency either a tool needs to show or be calculated, which is differing in my testing as tCLK has changed. Now 3DM FS and CB15 showed no benefit, but AIDA64 and 3DM SD did.

So on basis of just discussing what x platform does vs y, on what timings it can do we can carry on and on







. But the discussion falls flat when we may look at how it affects performance in use and even to that matter efficiency between x vs y.

I think that's a well rounded post for AMD and Intel platform







.


----------



## Silent Scone

I neglected to add that X370 is also two channels down, too. I did say it's not necessarily bad, just not as good







The takeaway point was that pushing what some of these modules are really capable of isn't possible on the platform, that's all. It's simply not capable of running them that way unconditionally.

And yes, Firestrike or 3DMark Physics/Bullet has always been sensitive to memory latency


----------



## gupsterg

I agree X370 is down two channels







, but then it really isn't supposed to be competing directly at X99. Yeah AMD marketed it against that platform but more in price/performance aspect than features







.

Now besides say quad channel being more of a challenge and I'll give that the Intel platform is dealing with that. In that context X370 should have been better for RAM timings, etc, but then jumping onto dual channel platform on price side is easier than quad from last time I checked.

I agree on your takeaway in a way







, but we can't exclude the real world performance loss may not be something to discuss at such length







, so then the timings also become inconsequential, to a degree







.


----------



## Silent Scone

In all honesty, gup, yes it's all relative. Being able to run very good sub timings alone is somewhat barrel scraping - there are no sizable chunks of performance in the real world when it comes to memory overclocking generally. But if said platform can, then you might as well


----------



## gupsterg

True







, there I agree emphatically







.

I enjoy reading your posts and have thanked you before do so now







. I have great adulation for them







.

Thank you for being OP of thread







.


----------



## Silent Scone

Quote:


> Originally Posted by *gupsterg*
> 
> True
> 
> 
> 
> 
> 
> 
> 
> , there I agree emphatically
> 
> 
> 
> 
> 
> 
> 
> .
> 
> I enjoy reading your posts and have thanked you before do so now
> 
> 
> 
> 
> 
> 
> 
> . I have great adulation for them
> 
> 
> 
> 
> 
> 
> 
> .
> 
> Thank you for being OP of thread
> 
> 
> 
> 
> 
> 
> 
> .


Thanks, wasn't trying to take anything away from what's been achieved on the platform so far. Things have progressed a lot since launch and Zen has a long way to travel









Will you be looking at 'Thread Ripper'?


----------



## gupsterg

No problem







. TR Above my paygrade







. My marriage is tittering on the edge with my PC escapades







, only so much SWMBO will allow within the decree of home rules







.


----------



## Silent Scone

Ah,

Benches before wenches.


----------



## gupsterg

LOL, I wish it could be







. Mines more like a harpy







. After you place that ring on the finger it's downhill, but I guess I should be used it now after 21yrs







. Even the offspring







at me regarding my hobby







. Not complaining TBH







, without them life would be dull







.

Since 2015 I've had the use of 2x i5 4690K, 1x Z97/DDR3, 4x Hawaii, 3x Eizo FG2421, 11x Fiji, 2x U2515H, 3x Asus MG279Q and now 3x R7, 1x X370/DDR4. I sorta roll the pot on as I move along. I buy on promo/cashback deals and so far not loss £ on resale after use.

I was real lucky with the F4-3200C14D-16GTZ, nailed them at ~£77 inc VAT/P&P just prior to Ryzen Launch. I sold my DDR3 at £99.


----------



## Silent Scone

Yeah, that's a very good kit for that sort of money.


----------



## gupsterg

Indeed







.

The R7 I will keep will also be phenomenal "bang for £". I sold the Wraith Spire LED for £50, netted ~£45 IIRC as sold on FVF promo/cheapest shipping used.



Back on topic







.

So tighten up of subtimings on 3333MHz:-

[email protected] 1.05v---BIOS 1401---HCI---9hr--F4-3200C14D-16GTZ

CPU R7 1700 Batch: 1709PGT (Malaysia)



So all settings used are as below txt:-

Tweak_1_3.8_3333_C14ST_setting.txt 19k .txt file


Then:-

i) BankGroupSwap: [Disabled]
ii) BankGroupSwapAlt: [Disabled]
iii) Super IO Skew: [Disabled]
iv) CLDO_VDDP tweak

The HCI was started with ambient temp of ~28°C, first night in a while where room ambient has gone lower, as this morning it was ~22°C. Currently rig still running HCI to determine if ambients have an effect, I envisage by midday ambient may have gone back up to ~28°C.


----------



## MynRich

Quote:


> Originally Posted by *gupsterg*
> 
> Indeed
> 
> 
> 
> 
> 
> 
> 
> .
> 
> The R7 I will keep will also be phenomenal "bang for £". I sold the Wraith Spire LED for £50, netted ~£45 IIRC as sold on FVF promo/cheapest shipping used.
> 
> 
> 
> Back on topic
> 
> 
> 
> 
> 
> 
> 
> .
> 
> So tighten up of subtimings on 3333MHz:-
> 
> [email protected] 1.05v---BIOS 1401---HCI---9hr--F4-3200C14D-16GTZ
> 
> CPU R7 1700 Batch: 1709PGT (Malaysia)
> 
> 
> 
> So all settings used are as below txt:-
> 
> Tweak_1_3.8_3333_C14ST_setting.txt 19k .txt file
> 
> 
> Then:-
> 
> i) BankGroupSwap: [Disabled]
> ii) BankGroupSwapAlt: [Disabled]
> iii) Super IO Skew: [Disabled]
> iv) CLDO_VDDP tweak
> 
> The HCI was started with ambient temp of ~28°C, first night in a while where room ambient has gone lower, as this morning it was ~22°C. Currently rig still running HCI to determine if ambients have an effect, I envisage by midday ambient may have gone back up to ~28°C.


For 2x8GB B-die kits, does 9943 seem to work better than 1401? I tested 9945 (recommended from Elmor for 2x16 Hynix and 4x8GB B-Die) when I used Hynix DDR4 but now that I have B-Die and haven't gone back to check 9943 but if others have seen better results I'll switch?


----------



## gupsterg

9943 has IMC FW better tweaked for 1DPC IIRC. 1401 I'm using to try out the new CAD Bus option due to a little snag I have with RAM profile going nuts with ~≥30°C room ambient. Not helped it yet







.


----------



## Secret Dragoon

When is the list going to be updated?


----------



## poisson21

Hello, F4-3200c14q-64GTZR here stable for 1 hour in GSAT .

[email protected] 1.15v---BIOS 1401---GSAT---1hr--F4-3200C14Q-64GTZ



and with these setting

setting.txt 19k .txt file


for the setting that does not appear , clddvp (i think ^^) 960 mV

Edit : No 64Gb kit listed in the first post, Am i the first one ???


----------



## Silent Scone

Nice work, thanks for share









Quote:


> Originally Posted by *Secret Dragoon*
> 
> When is the list going to be updated?


Probably over the weekend


----------



## Zioa

Quote:


> Originally Posted by *Zioa*
> 
> [email protected] 14 14 28 42 T1-- 1.45V ----SOC 1.15V----Bios 1401---HCI---400%--F4-3200C14D-16GTZR
> 
> http://s1195.photobucket.com/user/Zio111/media/ram3466.jpg.html
> 
> http://s1195.photobucket.com/user/Zio111/media/aida 3466 new.jpg.html


1000%
http://s1195.photobucket.com/user/Zio111/media/1000ram.jpg.html


----------



## polkfan

Hey guys i'm running on this memory (G.SKILL Ripjaws V Series F4-3200C16D-16GVGB) I have the settings at 2933 AMP 1 with DDR 4 voltage at 1.4V and SOC to 1.1V passed over 1000% coverage not sure how to add it to the list or not here is proof on the second URL

https://www.newegg.com/Product/Product.aspx?Item=N82E16820232181

https://postimg.org/image/ul4b2nvn1/


----------



## ajlueke

[email protected] 1.1v---BIOS 2.4---HCI---650%--CMD32GX4M4C3200C14


----------



## ajlueke

4 DIMMS are stable at 3333 MHz!.

[email protected] 1.1v---BIOS 2.4---HCI---550%--CMD32GX4M4C3200C14


----------



## Spanners

Mucking around with the F6 non-beta (X370 Gaming 5). Noticed my tWR (26), tRDRD SCL (6) and tWRWR SCL (6) are pretty loose in comparison to other peoples timings I've seen. Still it's the best I've managed so far. Will update again when I've tried to tighten those up. No need to update the OP (hence me not following the format).

Edit: Also I'll try with GDM and BGS disabled.

Edit2: Well tWR 12, tRDRD SCL 2 and tWRWR SCL 2 was stable also.



Edit3! Mean latency from 5 runs.



Getting thrashed in latency and copy vs Zioa.


----------



## Silent Scone

Thanks, and nice results. Good to see Asrock boards doing well with 4 DIMM now, too


----------



## os2wiz

Quote:


> Originally Posted by *Silent Scone*
> 
> Thanks, and nice results. Good to see Asrock boards doing well with 4 DIMM now, too


I am stable at 3067mhz with two dim 32 GB kit G.Skill F4-3200C14D-32GTZSK on MSI Titanium . Stable on Y-Crunch, and Prime'95 small FFT at 3.85GHZ cpu speed.at 3067 mhz. Sorry I can't located my Prime small FFT file, I will submit it later. On my previous memory kit of FlareX 3200mhz ddr4 I was stable at 33333mhz . Of course those were single rank dimms versus my current dual rank kit.

ReportAIDA64June17.txt 175k .txt file


Ycruncher3.8GHZcpuand3067mhzmemory.PNG 267k .PNG file


----------



## ajlueke

[email protected] 1.1v---BIOS 2.4---HCI---450%--CMD32GX4M4C3200C14

I had to mess with ProcODT a bit and the VTT voltage to get this to pass HIC memtest. I think I'm reaching the limit of what this kit will do. 3600 will post, but I get immediate memory errors.


----------



## Spanners

[email protected](Stock)---3466Mhz-C14-14-14-28-1T---1.41v---SOC 1.11v---BIOS F6---Stressapptest---1 Hour--F4-3200C14-8GFX



This is pretty close to the best I can do @3466, there are some sub-timings I've left at auto which I could get tighter like tRTP and tFAW but this is pretty close to optimised for me.

To the OP I'm running a X370 Gaming 5 not a 3 btw and thanks for maintaining this thread


----------



## rv8000

Quote:


> Originally Posted by *Spanners*
> 
> Mucking around with the F6 non-beta (X370 Gaming 5). Noticed my tWR (26), tRDRD SCL (6) and tWRWR SCL (6) are pretty loose in comparison to other peoples timings I've seen. Still it's the best I've managed so far. Will update again when I've tried to tighten those up. No need to update the OP (hence me not following the format).
> 
> Edit: Also I'll try with GDM and BGS disabled.
> 
> Edit2: Well tWR 12, tRDRD SCL 2 and tWRWR SCL 2 was stable also.
> 
> 
> 
> Edit3! Mean latency from 5 runs.
> 
> 
> 
> Getting thrashed in latency and copy vs Zioa.


Nice results. I've finally stabilized 3333 at some tight timings, but have had zero luck with 3466 so far. Are you changing any other voltages outside of vdimm and vsoc? Do you leave procODT at AUTO?

I've also noticed that disabling BGS has a negative performance impact in AIDA, GDM may hurt read speeds but provide slight boosts for write/copy.


----------



## Spanners

No, just the SOC and DIMM voltage I haven't touched ProcODT yet. Might have to start as 3600 can boot @1.45v but it's pretty unstable at least at the timings I'm running for 3466.

tRFC affected stability the most of any sub-timing from what I could tell but I've only spent a relatively short amount of time experimenting. 260 would throw errors very quickly, 270 would run for 15mins+ but eventually BSOD and 280 was stable. Haven't try to get any more granular than that.

I didn't notice much performance change at all with with GDM and BGS disabled vs enabled but I've only benched AIDA which might not be the most consistent thing to gauge performance with.


----------



## Silent Scone

Quote:


> Originally Posted by *Spanners*
> 
> [email protected](Stock)---3466Mhz-C14-14-14-28-1T---1.41v---SOC 1.11v---BIOS F6---Stressapptest---1 Hour--F4-3200C14-8GFX
> 
> 
> 
> This is pretty close to the best I can do @3466, there are some sub-timings I've left at auto which I could get tighter like tRTP and tFAW but this is pretty close to optimised for me.
> 
> To the OP I'm running a X370 Gaming 5 not a 3 btw and thanks for maintaining this thread


How much memory?


----------



## Silent Scone

Table now updated









Quote:


> Originally Posted by *wolfpack122*
> 
> [email protected] 1.16v---BIOS 9943---Stressapptest---1 Hour--F4-3200C14D-16GTZ
> 
> 
> 
> 
> 
> Spoiler: AIDA64 Cache & Memory Benchmark at 3.9 GHz:


FYI the tRAS value is very low here. Have you tested performance with a higher value? The sum of tRAS should ideally be no less than CAS, tRCD and tRTP


----------



## wolfpack122

Quote:


> Originally Posted by *Silent Scone*
> 
> Table now updated
> 
> 
> 
> 
> 
> 
> 
> 
> FYI the tRAS value is very low here. Have you tested performance with a higher value? The sum of tRAS should ideally be no less than CAS, tRCD and tRTP


Thank you for pointing this out. I didn't know that until I read some of the posts on the C6H thread. But I have been experiencing some strange crashes while gaming.
I'll adjust my timings, retest and resubmit my results.
If you notice any other timings that don't make sense please let me know.


----------



## Spanners

Quote:


> Originally Posted by *Silent Scone*
> 
> How much memory?


Sorry, 16GB (8x2)


----------



## gupsterg

Quote:


> Originally Posted by *Silent Scone*
> 
> Table now updated
> 
> 
> 
> 
> 
> 
> 
> 
> FYI the tRAS value is very low here. Have you tested performance with a higher value? The sum of tRAS should ideally be no less than CAS, tRCD and *tRTP*


Is that a typo?

I thought it was tRAS = tCL + tRCD + tRP


----------



## Silent Scone

No, although that is a common mistake.

EDIT:

See here, quote from [email protected] from an older DDR3 thread, although the rules are static and still apply here
Quote:


> The minimum tRAS is the sum of tRCD, CAS and tRTP. That is, the time it takes to latch a row, read from a column address, and pass the data to the output buffers for burst. After tRTP elapses, a PRECHARGE command can be issued to close the row and charge/recharge the data cells accordingly.


----------



## nexxusty

I love Ryzen so much....

The Crosshair Vi Hero is the best board IMO. I've tried 3 boards and this one makes them all look like crap.

Running an R7 1700 @ 4ghz - 1.395v (55.5c loaded, 69c Small FFT loaded - Custom 480mm Loop, D5 Vario, Raystorm) however the memory support .... this is where I am very impressed.

2x8gb Samsung B-Die (3600mhz Ripjaws V) Running stable @ 3466mhz 15-15-15-15-36-1T @ 1.5v.

RAM is kept at 27c usually and 35c while stress testing at 1.5v. Not even a single worry using 1.5v 24/7 with those numbers.
Very happy with this system.

I've had a little GTX 1050Ti in here to play around with and man.... Paired wih a 4ghz Ryzen and fast RAM it is GREAT at 1080p. Most games can do High settings and some can do Ultra just fine! The GTX 1080 goes back in this week though. This little guy is going into another system I am selling.

Is there a chart I can get in on? 3466mhz 15-15-15-15-36-1T is pretty good I doubt A LOT of people are running speeds like that on Ryzen.


----------



## gupsterg

Quote:


> Originally Posted by *Silent Scone*
> 
> No, although that is a common mistake.
> 
> EDIT:
> 
> See here, quote from [email protected] from an older DDR3 thread, although the rules are static and still apply here
> Quote:
> 
> 
> 
> The minimum tRAS is the sum of tRCD, CAS and tRTP. That is, the time it takes to latch a row, read from a column address, and pass the data to the output buffers for burst. After tRTP elapses, a PRECHARGE command can be issued to close the row and charge/recharge the data cells accordingly.
Click to expand...

+rep







.

I'm currently on The Stilt's 3333MHz Fast setup posted here, I need 1.375V instead of 1.35V







. Now his setup does not follow the rule







.

tRAS is 30, tCL is 14, tRCD is 14 and tRTP is 8, so tRAS should be 36!? I have no performance issue or found a stability issue in current testing. So should we or should we not be sticking to rule I can not make sense







.

Now in a previous post by The Stilt, tCKE was stated as not significant, link and Raja's info here. When does "power saving" on DDR4 kick in?

Cheers







.


----------



## Silent Scone

Quote:


> Originally Posted by *gupsterg*
> 
> +rep
> 
> 
> 
> 
> 
> 
> 
> .
> 
> I'm currently on The Stilt's 3333MHz Fast setup posted here, I need 1.375V instead of 1.35V
> 
> 
> 
> 
> 
> 
> 
> 
> . Now his setup does not follow the rule
> 
> 
> 
> 
> 
> 
> 
> .
> 
> tRAS is 30, tCL is 14, tRCD is 14 and tRTP is 8, so tRAS should be 36!? I have no performance issue or found a stability issue in current testing. So should we or should we not be sticking to rule I can not make sense
> 
> 
> 
> 
> 
> 
> 
> .
> .


The tRAS window debate has been covered at length in the Intel memory thread. What exactly is happening when the value is substituted isn't all that transparent and will depend on the platform and how it handles arbitrary timings set by the user. The rule is what it is, so any performance or stability benefit is 'cosmetic' and the result of other timing adjustments.


----------



## gupsterg

Thank you for info







. I'll roll with The Stilt's 3333MHz Fast for now as they are sweet in all cases I've used. Saved a heck load of time by not discovering my own. Down side is I learnt less about timings







.


----------



## IRobot23

https://www.gskill.com/en/product/f4-3466c16d-8gvk
this samsung b die?


----------



## finalheaven

Well I'm not sure what's better. Running 3466 at 14-14-14-14-34 but rest of the timings loose, or running the Stilt's 3333 (fast) timings. Currently testing Stilt's 3333 (fast) with GSAT.


----------



## mus1mus

Quote:


> Originally Posted by *nexxusty*
> 
> I love Ryzen so much....
> 
> The Crosshair Vi Hero is the best board IMO. I've tried 3 boards and this one makes them all look like crap.
> 
> Running an R7 1700 @ 4ghz - 1.395v (55.5c loaded, 69c Small FFT loaded - Custom 480mm Loop, D5 Vario, Raystorm) however the memory support .... this is where I am very impressed.
> 
> 2x8gb Samsung B-Die (3600mhz Ripjaws V) Running stable @ 3466mhz 15-15-15-15-36-1T @ 1.5v.
> 
> RAM is kept at 27c usually and 35c while stress testing at 1.5v. Not even a single worry using 1.5v 24/7 with those numbers.
> Very happy with this system.
> 
> I've had a little GTX 1050Ti in here to play around with and man.... Paired wih a 4ghz Ryzen and fast RAM it is GREAT at 1080p. Most games can do High settings and some can do Ultra just fine! The GTX 1080 goes back in this week though. This little guy is going into another system I am selling.
> 
> Is there a chart I can get in on? 3466mhz 15-15-15-15-36-1T is pretty good I doubt A LOT of people are running speeds like that on Ryzen.


First, 3466 C15 @ 1.5V is terrible. 3466 C14 should be doable with 1.4V. Look up everyone's results.

2nd, other boards have their upsides and I wouldn't personally say the CH6 is the best board there is.









3rd, not alot of people run 3466 C15. They are doing it with C14.


----------



## ajlueke

[email protected] 1.1v---BIOS 2.4---HCI---1300%--CMD32GX4M4C3200C14

Hello again!

Same timings as before, I just ran the HCI memtest over 1000%. 3466 CL14 2T is probably the best I can do with 4 DIMMs. I'm going to try and see if any tweaks will get 1T stable, but I think 3600 MHz is a long shot.


----------



## Jpmboy

Quote:


> Originally Posted by *Silent Scone*
> 
> Table now updated
> 
> 
> 
> 
> 
> 
> 
> 
> FYI the tRAS value is very low here. Have you tested performance with a higher value? The sum of tRAS should ideally be no less than CAS, tRCD and tRTP


yeah - so many folks ignore this. posted the same in the c6h thread to no avail. http://www.overclock.net/t/1624603/rog-crosshair-vi-overclocking-thread/20820_20#post_26182143


----------



## gupsterg

Will be hammering that at anyone when the need arise







.


----------



## Obvcop

I have been running my Ballistix Sport 2x4gb kit at 2933 for a week now with no problems, I believe this is micron ram but I'm not 100 sure. Managed an overnight of memtest and memtest86 on the first night. I had to lock it down to 1t and geardown disabled in the bios as auto switched them to on and 2T.
The timings I have right now are pretty close to the 2400 XMP timings with a few locked in manually. I also managed to get it down to C12 at 2666 but wanted to go for speed for obvious reasons. I don't really know what I am doing at this point though, can anybody look at my timings and tell me if there is any values I should change or recommendations for tightening it further


----------



## Secret Dragoon

You've got me in at 3200 instead of 3600 =P

http://www.overclock.net/t/1628751/official-amd-ryzen-ddr4-24-7-memory-stability-thread/320#post_26164342

(That's probably why I couldn't find my score before.)

I have a ~5MB/s faster AIDA score I need to test stability out on.


----------



## zeroibis

Quote:


> Originally Posted by *IRobot23*
> 
> https://www.gskill.com/en/product/f4-3466c16d-8gvk
> this samsung b die?


F4-3466C16D-16GVK Of which the single 8gb stick you posted is a part of has not yet had anyone verify what it has see: https://www.reddit.com/r/Amd/duplicates/649ay8/ram_collection_thread_please_post_your_ram/


----------



## IRobot23

Quote:


> Originally Posted by *zeroibis*
> 
> F4-3466C16D-16GVK Of which the single 8gb stick you posted is a part of has not yet had anyone verify what it has see: https://www.reddit.com/r/Amd/duplicates/649ay8/ram_collection_thread_please_post_your_ram/


its 2*4GB


----------



## zeroibis

Quote:


> Originally Posted by *IRobot23*
> 
> its 2*4GB


Ah, well I do not think anyone has reports of what is in 4GB sticks. But if someone gets them please run the program in the redit thread and update everyone so we can find out.








Quote:


> Originally Posted by *Obvcop*
> 
> I have been running my Ballistix Sport 2x4gb kit at 2933 for a week now with no problems, I believe this is micron ram but I'm not 100 sure.


Just run the program in this thread to find out: https://www.reddit.com/r/Amd/duplicates/649ay8/ram_collection_thread_please_post_your_ram/

Also post results up so the list of memory can be updated for all to see.


----------



## Silent Scone

Quote:


> Originally Posted by *Secret Dragoon*
> 
> You've got me in at 3200 instead of 3600 =P
> 
> http://www.overclock.net/t/1628751/official-amd-ryzen-ddr4-24-7-memory-stability-thread/320#post_26164342
> 
> (That's probably why I couldn't find my score before.)
> 
> I have a ~5MB/s faster AIDA score I need to test stability out on.


Amended


----------



## yendor

http://www.overclock.net/t/1627555/ryzen-memory-ic-collection-thread/0_20

probably overlaps with reddit thread.


----------



## wolfpack122

[email protected] 1.175v---BIOS 9943---Stressapptest---1 Hour--F4-3200C14D-16GTZ

I adjusted some of the timings and ran the test at 3.9GHz. Performance is just a tad bit lower, but nothing worth mentioning.


----------



## SaccoSVD

Quote:


> Originally Posted by *wolfpack122*
> 
> [email protected]3600Mhz-C16-16-16-36-2T---1.46v---SOC 1.175v---BIOS 9943---Stressapptest---1 Hour--F4-3200C14D-16GTZ
> 
> I adjusted some of the timings and ran the test at 3.9GHz. Performance is just a tad bit lower, but nothing worth mentioning.


can you show an AIDA memory benchmark? I'm curious.


----------



## wolfpack122

Quote:


> Originally Posted by *SaccoSVD*
> 
> can you show an AIDA memory benchmark? I'm curious.


----------



## SaccoSVD

wow that's fast!

Where do you see the difference? besides benchmarks?

Here is in my machine. Can the RAM speed difference make such a massive boost? Do you OC your card?


----------



## wolfpack122

Quote:


> Originally Posted by *SaccoSVD*
> 
> wow that's fast!
> 
> Where do you see the difference? besides benchmarks?


I mostly play games at 2160p on it so I am not sure if I am seeing any benefits. Maybe I'll test some games at 2160p and see if there is any advantage of pushing the RAM to its limits.

Edit: My GPU is running at 1445MHz on the core and 3903MHz on the memory. I set the fan to 100% so that the core frequency stays at 1445MHz.
Edit 2: I also don't use p-state overclocking and my power profile is set to 'High performance'.


----------



## os2wiz

Quote:


> Originally Posted by *SaccoSVD*
> 
> wow that's fast!
> 
> Where do you see the difference? besides benchmarks?
> 
> Here is in my machine. Can the RAM speed difference make such a massive boost? Do you OC your card?
> 
> Here are AIDA64 benchmarks on my machine Ryzen 1800X 323GB (dual rank 2 dimms) running at 3067mhz memory speed:
> 
> ReportAIDA64628CPU3.85GHZmemory3067mhz.docx 73k .docx file


----------



## SaccoSVD

Quote:


> Originally Posted by *wolfpack122*


How are you getting way more fps than me, I have the same hardware. I cannot believe 600mhz more in the RAM will affect the superposition score in such a massive way.

Are you on a SLI system? Or watercooler OC'd GPU?

I see your GPU utilization was 96% and in my benchmark was 79%....any idea why that happened?


----------



## wolfpack122

Quote:


> Originally Posted by *SaccoSVD*
> 
> How are you getting way more fps than me, I have the same hardware. I cannot believe 600mhz more in the RAM will affect the superposition score in such a massive way.


That benchmark is latency sensitive when the CPU is bottleneck. I get an even better score at 3466CL14, but I couldn't achieve stability at that speed and timings.

Run the benchmark at '1080p Extreme' and you should get a score close to this:


----------



## SaccoSVD

Right...this is what I get.


----------



## wolfpack122

Quote:


> Originally Posted by *SaccoSVD*
> 
> Right...this is what I get.
> 
> 
> Spoiler: Warning: Spoiler!


What are your GPU's core and memory clock during the test?
Setting your fan to a 100% for the duration of the benchmark will keep the core clock from throttling too much due to the increase in temperature.


----------



## SaccoSVD

Quote:


> What are your GPU's core and memory clock during the test?


Stock 980ti SC clocks, without precision X running.
Quote:


> Setting your fan to a 100% for the duration of the benchmark will keep the core clock from throttling too much due to the increase in temperature.


That helped, but what really made a difference was to put the GPU in "Prefer maximum performance" in the NVIDIA control panel.


----------



## Silent Scone

As much as I love GPU benchmarking, can we take this somewhere else please gents


----------



## SaccoSVD

Quote:


> Originally Posted by *Silent Scone*
> 
> As much as I love GPU benchmarking, can we take this somewhere else please gents


I would say so....that's why I was questioning such score related to RAM here. I wanted at least to equalize cause something seemed odd. Case is closed now.


----------



## Silent Scone

Quote:


> Originally Posted by *SaccoSVD*
> 
> I would say so....that's why I was questioning such score related to RAM here. I wanted at least to equalize cause something seemed odd. Case is closed now.


I've not found Superposition to be overly sensitive to memory latency


----------



## SaccoSVD

Quote:


> Originally Posted by *Silent Scone*
> 
> I've not found Superposition to be overly sensitive to memory latency


That's what I thought.


----------



## hotstocks

Can someone please answer which is faster setting for 4 sticks of G.skill single sided b-die 4X8=32 on Asus C6H mobo.
Should Bank Group Swap be Enabled or Disabled?
Thank you


----------



## gupsterg

Quote:


> Originally Posted by *gupsterg*
> 
> @hotstocks
> 
> ProcODT suggestions are in thread. Then finalheaven has shared a few times he runs 4x 8GB 3466MHz on 3200MHz kit, his settings are in here and the RAM thread. Next BankGroupSwap setting was again mentioned by me only yesterday and I don't know how many times before it has been stated.
> 
> Case situation for BankGroupSwap and BankGroupSwapAlt to be Disabled is 1 dimm per channel and single rank kit. Hopefully next user on a search of thread will see this.


Link to post.


----------



## MynRich

[email protected] 1.15v---BIOS 1403---HCI---1000%---TXOBD416G4133HC18FDC01


----------



## harrysun

I'm using this DDR4 kit G.Skill Trident Z DIMM Kit 2x16GB (F4-3200C14D-32GTZ)

(Created with Thaiphoon Burner Freeware Version Download)

AMD Ryzen R7 1800X, Stepping 1 Revision ZP-B1
ASUS ROG CROSSHAIR VI HERO
Motherboard Slots: DIMM_A2, DIMM_B2

BIOS Version: 1403 x64
Build Date: 06/22/2017
EC1 Version: MBEC-AM4-0311
EC2 Version: RGE2-AM4-0106


*AIDA64 6h ok*, *BOINC 6h ok*, *Google stressapptest (GSAT) 6h ok*, *IntelBurnTest v2.54 IBT AVX 10 run Level Maximum*, *HCI Design MemTest Deluxe 135% ok*



Overview about settings [email protected]/s CL14-13-13-26-42 1T 1.35000V BETA BIOS 1403 [email protected]:

Advanced \ AMD CBS \ UMC Common Options \ DDR4 Common Options \ CAD Configuration
CAD Bus Driver Strenght User Controls = Manual
ClkDrvbStren = 40.0 Ohm
AddrCmdDrvStren = 20.0 Ohm
CsOdtDrvStren = 40.0 Ohm
CkeDrvStren = 40.0 Ohm

Advanced \ AMD CBS \ NBIO Common Options
_CLDO_VDDP Control = Auto (Default)_

Advanced \ AMD CBS \ UMC Common Options \ DRAM Memory Mapping
BankGroupSwap = Enabled
_BankGroupSwapAlt = Auto (Default)_

Extreme Tweaker
_CPU Core Voltage = Auto (Default)_
CPU SOC Voltage = Offset mode
VDDSOC Offset Mode Sign = - (minus)
- VDDSOC Voltage Offset = 0.10000
_DRAM Voltage = 1.35000 (Default)_

Extreme Tweaker \ DRAM Timing Control
DRAM ... = 14-13-13-13-26-42-6-8-36-Auto(4)-Auto(12)-10-Auto(0)-2-2-400-350-256-Auto(14)-8-Auto(6)-Auto(3)-Auto(1)-Auto(7)-Auto(7)-Auto(1)-Auto(5)-Auto(5)-Auto(8)
ProcODT_SM = 60 ohm
Cmd2T = 1T
Gear Down Mode = Enabled
_Power Down Enabled = Auto (Default)_
RttNom = RZQ/3
RttWr = RZQ/3
RttPark = RZQ/1

Extreme Tweaker \ External Digi+ Power Control
DRAM VBoot Voltage = 1.37500



Complete BETA BIOS 1403 setting file:


Spoiler: CPU3600_DRAM3200CL14-13_setting.txt



[2017/06/28 06:46:27]
Ai Overclock Tuner [D.O.C.P. Standard]
D.O.C.P. [D.O.C.P DDR4-3200 14-14-14-34-1.35V]
BCLK Frequency [100.0000]
BCLK_Divider [Auto]
Custom CPU Core Ratio [Auto]
> CPU Core Ratio [Auto]
Performance Bias [Auto]
Memory Frequency [DDR4-3200MHz]
Core Performance Boost [Auto]
SMT Mode [Auto]
EPU Power Saving Mode [Disabled]
TPU [Keep Current Settings]
CPU Core Voltage [Auto]
CPU SOC Voltage [Offset mode]
VDDSOC Offset Mode Sign [-]
- VDDSOC Voltage Offset [0.10000]
DRAM Voltage [1.35000]
1.8V PLL Voltage [Auto]
1.05V SB Voltage [Auto]
Target TDP [Auto]
TRC_EOM [Auto]
TRTP_EOM [Auto]
TRRS_S_EOM [Auto]
TRRS_L_EOM [Auto]
TWTR_EOM [Auto]
TWTR_L_EOM [Auto]
TWCL_EOM [Auto]
TWR_EOM [Auto]
TFAW_EOM [Auto]
TRCT_EOM [Auto]
TREFI_EOM [Auto]
TRDRD_DD_EOM [Auto]
TRDRD_SD_EOM [Auto]
TRDRD_SC_EOM [Auto]
TRDRD_SCDLR_EOM [Auto]
TRDRD_SCL_EOM [Auto]
TWRWR_DD_EOM [Auto]
TWRWR_SD_EOM [Auto]
TWRWR_SC_EOM [Auto]
TWRWR_SCDLR_EOM [Auto]
TWRWR_SCL_EOM [Auto]
TWRRD_EOM [Auto]
TRDWR_EOM [Auto]
TWRRD_SCDLR_EOM [Auto]
DRAM CAS# Latency [14]
DRAM RAS# to CAS# Read Delay [13]
DRAM RAS# to CAS# Write Delay [13]
DRAM RAS# PRE Time [13]
DRAM RAS# ACT Time [26]
Trc_SM [42]
TrrdS_SM [6]
TrrdL_SM [8]
Tfaw_SM [36]
TwtrS_SM [Auto]
TwtrL_SM [Auto]
Twr_SM [10]
Trcpage_SM [Auto]
TrdrdScl_SM [2]
TwrwrScl_SM [2]
Trfc_SM [400]
Trfc2_SM [350]
Trfc4_SM [256]
Tcwl_SM [Auto]
Trtp_SM [8]
Trdwr_SM [Auto]
Twrrd_SM [Auto]
TwrwrSc_SM [Auto]
TwrwrSd_SM [Auto]
TwrwrDd_SM [Auto]
TrdrdSc_SM [Auto]
TrdrdSd_SM [Auto]
TrdrdDd_SM [Auto]
Tcke_SM [Auto]
ProcODT_SM [60 ohm]
Cmd2T [1T]
Gear Down Mode [Enabled]
Power Down Enable [Auto]
RttNom [RZQ/3]
RttWr [RZQ/3]
RttPark [RZQ/1]
VTTDDR Voltage [Auto]
VPP_MEM Voltage [Auto]
DRAM CTRL REF Voltage on CHA [Auto]
DRAM CTRL REF Voltage on CHB [Auto]
VDDP Voltage [Auto]
VDDP Standby Voltage [Auto]
1.8V Standby Voltage [Auto]
CPU 3.3v AUX [Auto]
2.5V SB Voltage [Auto]
DRAM R1 Tune [Auto]
DRAM R2 Tune [Auto]
DRAM R3 Tune [Auto]
DRAM R4 Tune [Auto]
PCIE Tune R1 [Auto]
PCIE Tune R2 [Auto]
PCIE Tune R3 [Auto]
PLL Tune R1 [Auto]
PLL reference voltage [Auto]
T Offset [Auto]
Sense MI Skew [Auto]
Sense MI Offset [Auto]
Promontory presence [Auto]
Clock Amplitude [Auto]
CPU Load-line Calibration [Auto]
CPU Current Capability [Auto]
CPU VRM Switching Frequency [Auto]
VRM Spread Spectrum [Auto]
CPU Power Duty Control [T.Probe]
CPU Power Phase Control [Auto]
CPU Power Thermal Control [120]
VDDSOC Load-line Calibration [Auto]
VDDSOC Current Capability [Auto]
VDDSOC Switching Frequency [Auto]
VDDSOC Phase Control [Auto]
DRAM Current Capability [100%]
DRAM Power Phase Control [Extreme]
DRAM Switching Frequency [Auto]
DRAM VBoot Voltage [1.37500]
Security Device Support [Enable]
TPM Device Selection [Discrete TPM]
Erase fTPM NV for factory reset [Enabled]
PSS Support [Enabled]
NX Mode [Enabled]
SVM Mode [Disabled]
SATA Port Enable [Enabled]
PT XHCI GEN1 [Auto]
PT XHCI GEN2 [Auto]
PT USB Equalization4 [Auto]
PT USB Redriver [Auto]
PT PCIE PORT 0 [Auto]
PT PCIE PORT 1 [Auto]
PT PCIE PORT 2 [Auto]
PT PCIE PORT 3 [Auto]
PT PCIE PORT 4 [Auto]
PT PCIE PORT 5 [Auto]
PT PCIE PORT 6 [Auto]
PT PCIE PORT 7 [Auto]
Onboard PCIE LAN PXE ROM [Enabled]
AMD CRB EHCI Debug port switch [Disabled]
Onboard LED [Enabled]
Hyper kit Mode [Disabled]
SATA Port Enable [Enabled]
SATA Mode [AHCI]
SMART Self Test [Enabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
ErP Ready [Disabled]
Restore On AC Power Loss [Power Off]
Power On By PCI-E/PCI [Disabled]
Power On By RTC [Disabled]
Super I/O Clock Skew [Auto]
HD Audio Controller [Enabled]
PCIEX4_3 Bandwidth [Auto]
PCIEX16_1 Mode [Auto]
PCIEX8_2 Mode [Auto]
PCIEX4_3 Mode [Auto]
M.2 Link Mode [Auto]
SB Link Mode [Auto]
Asmedia USB 3.1 Controller [Enabled]
RGB LED lighting [Enabled]
In sleep, hibernate and soft off states [On]
Intel LAN Controller [Enabled]
Intel LAN OPROM [Disabled]
USB Type C Power Switch for USB3.1_E1 [Auto]
USB Type C Power Switch for USB3.1_EC2 [Auto]
Network Stack [Disabled]
Debug Port Table [Disabled]
Debug Port Table 2 [Disabled]
Device [WDC WD6002FFWX-68TZ4N0]
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
USB Mass Storage Driver Support [Enabled]
disk2go disk2go PURE S2 6.50 [Auto]
SanDisk Extreme Pro 0 [Auto]
USB3.1_E1 [Auto]
USB3_1 [Enabled]
USB3_2 [Enabled]
USB3_3 [Enabled]
USB3_4 [Enabled]
USB3_5 [Auto]
USB3_6 [Auto]
USB3_7 [Auto]
USB3_8 [Auto]
USB3_9 [Auto]
USB3_10 [Auto]
USB2_11 [Auto]
USB2_12 [Auto]
USB2_13 [Auto]
USB2_14 [Auto]
USB_15 [Auto]
USB_16 [Auto]
CPU Temperature [Monitor]
MotherBoard Temperature [Monitor]
VRM Temperature [Monitor]
PCH Temperature [Monitor]
T_Sensor1 Temperature [Monitor]
CPU Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
Chassis Fan 3 Speed [Monitor]
W_PUMP+ Speed [Monitor]
CPU Optional Fan Speed [Monitor]
AIO_PUMP Speed [Monitor]
W_FLOW Speed [Monitor]
W_IN Temperature [Monitor]
W_OUT Temperature [Monitor]
CPU Core Voltage [Monitor]
3.3V Voltage [Monitor]
5V Voltage [Monitor]
12V Voltage [Monitor]
CPU Q-Fan Control [Auto]
CPU Fan Smoothing Up/Down Time [0 sec]
CPU Fan Speed Lower Limit [200 RPM]
CPU Fan Profile [Standard]
W_PUMP+ Control [Disabled]
Chassis Fan 1 Q-Fan Control [Auto]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Smoothing Up/Down Time [0 sec]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 1 Profile [Standard]
Chassis Fan 2 Q-Fan Control [Auto]
Chassis Fan 2 Q-Fan Source [CPU]
Chassis Fan 2 Smoothing Up/Down Time [0 sec]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 2 Profile [Standard]
Chassis Fan 3 Q-Fan Control [Auto]
Chassis Fan 3 Q-Fan Source [CPU]
Chassis Fan 3 Smoothing Up/Down Time [0 sec]
Chassis Fan 3 Speed Low Limit [200 RPM]
Chassis Fan 3 Profile [Standard]
OnChip SATA Channel [Auto]
OnChip SATA Type [AHCI]
USB3_1 [Enabled]
USB3_2 [Enabled]
USB3_3 [Enabled]
USB3_4 [Enabled]
IR Config [RX & TX0 Only]
SdForce18 Enable [Disabled]
SD Mode configuration [AMDA]
Uart 0 Enable [Enabled]
Uart 1 Enable [Enabled]
I2C 0 Enable [Enabled]
I2C 1 Enable [Enabled]
I2C 2 Enable [Disabled]
I2C 3 Enable [Disabled]
GPIO Devices Support [Auto]
ESATA Port On Port 0 [Auto]
ESATA Port On Port 1 [Auto]
ESATA Port On Port 2 [Auto]
ESATA Port On Port 3 [Auto]
ESATA Port On Port 4 [Auto]
ESATA Port On Port 5 [Auto]
ESATA Port On Port 6 [Auto]
ESATA Port On Port 7 [Auto]
SATA Power On Port 0 [Auto]
SATA Power On Port 1 [Auto]
SATA Power On Port 2 [Auto]
SATA Power On Port 3 [Auto]
SATA Power On Port 4 [Auto]
SATA Power On Port 5 [Auto]
SATA Power On Port 6 [Auto]
SATA Power On Port 7 [Auto]
SATA Port 0 MODE [Auto]
SATA Port 1 MODE [Auto]
SATA Port 2 MODE [Auto]
SATA Port 3 MODE [Auto]
SATA Port 4 MODE [Auto]
SATA Port 5 MODE [Auto]
SATA Port 6 MODE [Auto]
SATA Port 7 MODE [Auto]
SATA Hot-Removable Support [Auto]
SATA 6 AHCI Support [Auto]
Int. Clk Differential Spread [Auto]
SATA MAXGEN2 CAP OPTION [Auto]
SATA CLK Mode Option [Auto]
Aggressive Link PM Capability [Auto]
Port Multiplier Capability [Auto]
SATA Ports Auto Clock Control [Auto]
SATA Partial State Capability [Auto]
SATA FIS Based Switching [Auto]
SATA Command Completion Coalescing Support [Auto]
SATA Slumber State Capability [Auto]
SATA MSI Capability Support [Auto]
SATA Target Support 8 Devices [Auto]
Generic Mode [Auto]
SATA AHCI Enclosure [Auto]
SATA SGPIO 0 [Disabled]
SATA SGPIO 1 [Disabled]
SATA PHY PLL [Auto]
AC/DC Change Message Delivery [Disabled]
TimerTick Tracking [Auto]
Clock Interrupt Tag [Enabled]
EHCI Traffic Handling [Disabled]
Fusion Message C Multi-Core [Disabled]
Fusion Message C State [Disabled]
SPI Read Mode [Auto]
SPI 100MHz Support [Auto]
SPI Normal Speed [Auto]
SPI Fast Read Speed [Auto]
SPI Burst Write [Auto]
I2C 0 D3 Support [Auto]
I2C 1 D3 Support [Auto]
I2C 2 D3 Support [Auto]
I2C 3 D3 Support [Auto]
UART 0 D3 Support [Auto]
UART 1 D3 Support [Auto]
SATA D3 Support [Auto]
EHCI D3 Support [Auto]
XHCI D3 Support [Auto]
SD D3 Support [Auto]
S0I3 [Auto]
Chipset Power Saving Features [Enabled]
SB Clock Spread Spectrum [Auto]
SB Clock Spread Spectrum Option [-0.375%]
HPET In SB [Auto]
MsiDis in HPET [Auto]
_OSC For PCI0 [Auto]
USB Phy Power Down [Auto]
PCIB_CLK_Stop Override [0]
USB MSI Option [Auto]
LPC MSI Option [Auto]
PCIBridge MSI Option [Auto]
AB MSI Option [Auto]
SB C1E Support [Auto]
SB Hardware Reduced Support [Auto]
GPP Serial Debug Bus Enable [Auto]
IOMMU [Auto]
Remote Display Feature [Auto]
Gnb Hd Audio [Auto]
PSPP Policy [Auto]
Memory Clock [Auto]
Bank Interleaving [Enabled]
Channel Interleaving [Enabled]
Memory Clear [Disabled]
Fast Boot [Enabled]
Next Boot after AC Power Loss [Normal Boot]
Boot Logo Display [Disabled]
POST Report [3 sec]
Boot up NumLock State [Disabled]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Enabled]
Interrupt 19 Capture [Disabled]
Setup Mode [Advanced Mode]
Launch CSM [Enabled]
Boot Device Control [UEFI and Legacy OPROM]
Boot from Network Devices [Legacy only]
Boot from Storage Devices [Legacy only]
Boot from PCI-E Expansion Devices [Legacy only]
OS Type [Other OS]
Setup Animator [Disabled]
Load from Profile [1]
Profile Name [[email protected]!]
Save to Profile [2]
CPU Core Voltage [Auto]
VDDSOC Voltage [Auto]
1.8V PLL Voltage [Auto]
BCLK Frequency [Auto]
CPU Ratio [Auto]
Bus Interface [PCIEX16/X8_1]



Credits goes to:


Spoiler: These information helped me to get G.Skill Trident Z DIMM Kit 2x16GB 2R (F4-3200C14D-32GTZ) @3200MT/s CL14 on BIOS 1403



Quote:


> Originally Posted by *Ramad*
> 
> *No spoilers in this post.*
> 
> Managed to boot @3200MT/s by changing *RttPark* to *RZQ/1* and *RttWr* to *RZQ/3*. I can now boot at the rated speed using *ProcODT_SM = 60* ohm and *68 ohm*, which was impossible before these changes, that I could only boot at the rated speed using ProcODT_SM = 80 ohm, which was not stable at all. RZQ value is 240 ohm (according to Samsung DDR4 document that I did post a link to with screenshots from the document it self in one of my earlier posts).
> 
> *Of course I´m using the lowest ProcODT resistance my RAM can boot at, which is 60 ohm.*
> 
> If you have trouble booting or getting your RAM stable at the rated speed, then change these settings and give it a try (RttPark and RttWr).
> 
> 
> 
> Running at 3200MT/s using ProcODT_SM = 60 ohm requires a small bump in VDDSOC from 0.97500 Volt @ 3066MT/s to 1.000 Volt @3200MT/s, which is not a big deal. Testing stability now at stock timings.
> 
> 
> 
> *CAD Bus Drive Strength* values are as shown below
> 
> 
> 
> Note: This is what worked for my RAM (2X8GB @3200 MT/s Patriot Viper Elite).


Quote:


> Originally Posted by *Jackalito*
> 
> Sorry for not replying to each of you individually but I'm pushed for time, just wanted to let you know that you're up to something here. I've got *G.Skill TridentZ F4-3200C14-32GTZ (2x16GB Sammy B-die)* and previous to some of these suggestions I couldn't run my RAM at 3200MHz with any stability. For example, AIDA64 stress system memory would throw hardware error within seconds regardless of voltage and timings.
> 
> So, *UEFI 1403* and currently testing my RAM at *3200MHz* with these settings:
> *ProcODT at 68* (at 60 it would boot into Windows, but AIDA64 threw errors within 1 minute)
> Timings are loose at *16 16 16 39 75 2T*. They're all in Auto right now.
> Then, *RttPark to RZQ/1* and *RttWr to RZQ/3*.
> *CLDO_VDDP voltage is 910* right now, but I still think it could be fine tuned further.
> I haven't touched *CAD Bus configuration* yet.
> 
> I never imagined my system could boot and train my RAM at 60 or 68 ProcODT values. Until this moment it was only possible at 80 and especially 96. Or at least I think so, because up until now I had never tried *RttPark to RZQ/1* and *RttWr to RZQ/3* values.
> 
> I will keep testing and report back my findings!
> *Thanks so much to Cata79, Ramad, BoMbY and, of course, The Stilt!!!*


Quote:


> Originally Posted by *The Stilt*
> 
> Few more timing sets.
> 
> HQ B-die - 3200MHz "Safe" 1.350V
> 
> 
> 
> UHQ B-die - 3200MHz "Fast" 1.350V
> 
> 
> 
> HQ B-die - 3333MHz "Safe" 1.350V
> 
> 
> 
> UHQ B-die - 3333MHz "Fast" 1.350V
> 
> 
> 
> HQ = e.g. 3000C14, 3200C15, 3600C16, 3600C17 rated B-die kits
> UHQ = e.g. 3200C14, 3600C15 rated B-die kits
> 
> These timings are stable on my 3600C15 kit with < 1.350V voltage (1.340V bios setting).
> In 3200MHz "Fast" example, tCL 13 would be otherwise doable (this kit is rated 13.333 CLK tCL-tRCD-tRP timings at 3200MHz) however AGESA issue affecting tCWL prevents using it at the moment.
> 
> For the best real world performance disable both BankGroupSwap and BankGroupSwapAlternative options, when using 1 DPC SR modules.






My previous/old stable setup was [email protected] [email protected]/s CL14-14-14-34-63-2T V1.3750 BETA BIOS 9943.


----------



## hotstocks

Can everyone with > 3200 mhz memory/tight timings post their Performance Test Memory scores please?
It's a free download and nice program, but would like to see how my scores compare to others while tweaking memory. Ryzen seems to get a bad score compared to Intel, and I am sure it is due to the low latency score, yet it gives me 55 for latency, so obviously it is not 55 ns, just some random scoring.

http://www.passmark.com/products/pt.htm


----------



## SaccoSVD

After much fiddling here are the best timings (that I could find) for a stable 2933 Kit (Vengeance LED 64Gb) part number CMU64GX4M4C3000C15

RAM Voltage 1.35v

Most notable value: "Tfaw" It was originally at 28 and I could set it to 12 without any problem. (any remark about this one besides what AMD says?)



Spoiler: Warning: Spoiler!


----------



## wolfpack122

Here is Jpmboy's post about tRAS and tFAW:
http://www.overclock.net/t/1624603/rog-crosshair-vi-overclocking-thread/20820_20#post_26182143


----------



## SaccoSVD

Quote:


> Originally Posted by *wolfpack122*
> 
> Here is Jpmboy's post about tRAS and tFAW:
> http://www.overclock.net/t/1624603/rog-crosshair-vi-overclocking-thread/20820_20#post_26182143


Thank you.


----------



## Keith Myers

Yes, it appears to benchmark Ryzen poorly across the board compared to any Intel sub-system memory. My scores don't seem to reflect my real-world performance seat-of-the-pants benchmark.
Ryzen 1700X @ 3.875 Ghz G.Skill F4-3600C16D-16GTZ @3333 Mhz @CL14-14-14-34-54-1T @1.375V. BOINC stable.

Code:



Code:


Memory Mark
        #1 - 16GB DDR4 SDRAM PC4-24024 G Skill Intl     3083
        #2 - 8GB DDR3 SDRAM PC3-12800 Corsair   1194
        #3 - 8GB DDR3 SDRAM PC3-12800 Kingston  2343
        #4 - 16GB DDR3 SDRAM PC3-12800  1356
        #5 - 8GB DDR3 SDRAM PC3-12800 G Skill Intl      1859
        #6 - 8GB DDR3 SDRAM PC3-10600 Hynix Semiconductor (Hyundai Elec 1290
        This Computer   2382

Database Operations
        #1 - 16GB DDR4 SDRAM PC4-24024 G Skill Intl     118.0
        #2 - 8GB DDR3 SDRAM PC3-12800 Corsair   37.2
        #3 - 8GB DDR3 SDRAM PC3-12800 Kingston  91.8
        #4 - 16GB DDR3 SDRAM PC3-12800  51.5
        #5 - 8GB DDR3 SDRAM PC3-12800 G Skill Intl      72.4
        #6 - 8GB DDR3 SDRAM PC3-10600 Hynix Semiconductor (Hyundai Elec 21.3
        This Computer   95.4

Memory Read Cached
        #1 - 16GB DDR4 SDRAM PC4-24024 G Skill Intl     30298
        #2 - 8GB DDR3 SDRAM PC3-12800 Corsair   13954
        #3 - 8GB DDR3 SDRAM PC3-12800 Kingston  25225
        #4 - 16GB DDR3 SDRAM PC3-12800  14406
        #5 - 8GB DDR3 SDRAM PC3-12800 G Skill Intl      26391
        #6 - 8GB DDR3 SDRAM PC3-10600 Hynix Semiconductor (Hyundai Elec 14706
        This Computer   28580

Memory Read Uncached
        #1 - 16GB DDR4 SDRAM PC4-24024 G Skill Intl     17866
        #2 - 8GB DDR3 SDRAM PC3-12800 Corsair   6137
        #3 - 8GB DDR3 SDRAM PC3-12800 Kingston  15365
        #4 - 16GB DDR3 SDRAM PC3-12800  6488
        #5 - 8GB DDR3 SDRAM PC3-12800 G Skill Intl      11116
        #6 - 8GB DDR3 SDRAM PC3-10600 Hynix Semiconductor (Hyundai Elec 10629
        This Computer   19432

Memory Write
        #1 - 16GB DDR4 SDRAM PC4-24024 G Skill Intl     13913
        #2 - 8GB DDR3 SDRAM PC3-12800 Corsair   4749
        #3 - 8GB DDR3 SDRAM PC3-12800 Kingston  8865
        #4 - 16GB DDR3 SDRAM PC3-12800  5170
        #5 - 8GB DDR3 SDRAM PC3-12800 G Skill Intl      5439
        #6 - 8GB DDR3 SDRAM PC3-10600 Hynix Semiconductor (Hyundai Elec 8480
        This Computer   10586

Available RAM
        #1 - 16GB DDR4 SDRAM PC4-24024 G Skill Intl     12701
        #2 - 8GB DDR3 SDRAM PC3-12800 Corsair   5975
        #3 - 8GB DDR3 SDRAM PC3-12800 Kingston  5995
        #4 - 16GB DDR3 SDRAM PC3-12800  13766
        #5 - 8GB DDR3 SDRAM PC3-12800 G Skill Intl      6415
        #6 - 8GB DDR3 SDRAM PC3-10600 Hynix Semiconductor (Hyundai Elec 2982
        This Computer   14515

Memory Latency
        #1 - 16GB DDR4 SDRAM PC4-24024 G Skill Intl     23.2
        #2 - 8GB DDR3 SDRAM PC3-12800 Corsair   66.0
        #3 - 8GB DDR3 SDRAM PC3-12800 Kingston  24.9
        #4 - 16GB DDR3 SDRAM PC3-12800  65.4
        #5 - 8GB DDR3 SDRAM PC3-12800 G Skill Intl      26.3
        #6 - 8GB DDR3 SDRAM PC3-10600 Hynix Semiconductor (Hyundai Elec 28.3
        This Computer   54.2

Memory Threaded
        #1 - 16GB DDR4 SDRAM PC4-24024 G Skill Intl     28227
        #2 - 8GB DDR3 SDRAM PC3-12800 Corsair   17212
        #3 - 8GB DDR3 SDRAM PC3-12800 Kingston  20554
        #4 - 16GB DDR3 SDRAM PC3-12800  18990
        #5 - 8GB DDR3 SDRAM PC3-12800 G Skill Intl      11778
        #6 - 8GB DDR3 SDRAM PC3-10600 Hynix Semiconductor (Hyundai Elec 18570
        This Computer   45536


----------



## ytv

So, I'm a bit lost at this point the motherboard I picked up was MSI X370 SLI PLUS and the memory is : CMK16GX4M2B3200C16 (2x8GB)

The memory in BIOS is configured as : Corsair CMK16GX4M2B3200C16 VERSION 5.39 [16-18-18-36 @ 1.36v] in bios.

Now my concern is I'm not sure if my memory is actually bad or it's just the overclock of the memory that is causing the problem. This is the more information for the error : http://hcidesign.com/memtest/decayError.html/ver:5.0a%20flag:6 I did by the way run memtest86 on the memory with no errors.

And I picked my memory through reading this by AMD : https://community.amd.com/community/gaming/blog/2017/03/14/tips-for-building-a-better-amd-ryzen-system

What do you guys think? I can set bios defaults - run memory as default and try again to see if I get another error. If I do get an error on default - then I should return the memory right? Should I return my memory as it might be faulty? Or should I try to change my timings or do some other adjustments in the bios? Can anyone recommend me some decent timings that I should try? I'm not too familiar with overclocking in ram.

Thanks to anyone that can help.


----------



## bluej511

Quote:


> Originally Posted by *ytv*
> 
> 
> 
> So, I'm a bit lost at this point the motherboard I picked up was MSI X370 SLI PLUS and the memory is : CMK16GX4M2B3200C16 (2x8GB)
> 
> The memory in BIOS is configured as : Corsair CMK16GX4M2B3200C16 VERSION 5.39 [16-18-18-36 @ 1.36v] in bios.
> 
> Now my concern is I'm not sure if my memory is actually bad or it's just the overclock of the memory that is causing the problem. This is the more information for the error : http://hcidesign.com/memtest/decayError.html/ver:5.0a%20flag:6 I did by the way run memtest86 on the memory with no errors.
> 
> And I picked my memory through reading this by AMD : https://community.amd.com/community/gaming/blog/2017/03/14/tips-for-building-a-better-amd-ryzen-system
> 
> What do you guys think? I can set bios defaults - run memory as default and try again to see if I get another error. If I do get an error on default - then I should return the memory right? Should I return my memory as it might be faulty? Or should I try to change my timings or do some other adjustments in the bios? Can anyone recommend me some decent timings that I should try? I'm not too familiar with overclocking in ram.
> 
> Thanks to anyone that can help.


I have the same RAM and with my timings at 14-16-34 i get coverage to 700% without errors on my c6h. However, on newer BIOSes i get errors almost instantly, so i know its not the ram. Im running 1.45v dram voltage though for those timings. Heres what my timings are like. I have my soc at 1.05 worked at 1.0v just fine as well.


----------



## ytv

Quote:


> Originally Posted by *bluej511*
> 
> I have the same RAM and with my timings at 14-16-34 i get coverage to 700% without errors on my c6h. However, on newer BIOSes i get errors almost instantly, so i know its not the ram. Im running 1.45v dram voltage though for those timings. Heres what my timings are like. I have my soc at 1.05 worked at 1.0v just fine as well.


Cool, thanks for the settings. At the moment I will try the following :

I will be running the system on the last preset that the motherboard offers - 3200mhz 18-20-20-38 timings @ 1.36v in bios. I'll mess around with it the whole day and restart if no 3 beeps upon restart I will try to run the HCI mem test for windows with timings @ 18-20-20-38.

If I get an error again I guess I will try to default the BIOS and run at default speed which I think is 2133mhz. Run it over night and if I still get an error I guess I'll be returning the ram as it probably faulty, and hopefully that will fix my issues.

Thanks for the help though man - I've been researching my board and I haven't found any information regarding it. BIOS is updated all the way as well. Hopefully this isn't a hardware issue.

Edit :

Well, I ran the test again @ 3200mhz with 18-20-20-38 timings 1.36v in bios. Here are the results :


Time to run bios defaults and try to run this again over night to see if I have any errors. If I do I guess I'll be returning the memory. Unless someone else thinks differently.

2nd Edit :

At bios default memory running 2133mhz (I forgot the timings) I left the test running over night and no errors, so at this point I'm pretty sure this is a memory configuration. I went back to 3200mhz with 18-20-20-38 timings,but now doing 1.4v on dram. Will try again to see if it is more stable.


----------



## SaccoSVD

Quote:


> Originally Posted by *SaccoSVD*
> 
> After much fiddling here are the best timings (that I could find) for a stable 2933 Kit (Vengeance LED 64Gb) part number CMU64GX4M4C3000C15
> 
> RAM Voltage 1.35v
> 
> Most notable value: "Tfaw" It was originally at 28 and I could set it to 12 without any problem. (any remark about this one besides what AMD says?)
> 
> 
> 
> Spoiler: Warning: Spoiler!


Quote to myself.

Standing corrected. I decided to go back to DOCP.

The gains with lower timings were microscopic, and added slight instability. So better to stick to stock settings if you have that RAM. (until someone finds better settings, or AMD magically let's me OC it more)

Conversely, I can run my CPU at 4.05Ghz from 4Ghz which gives me a much more tangible gain.


----------



## thenebulousmind

CPU: Ryzen 1600 @ stock speeds
RAM: Corsair Vengeance LPX 16GB (2x 8GB) - CMK16GX4M2B3200C16
Motherboard: Gigabyte Gaming 5 X370 - F6 BIOS (latest as of this post)
Achiveved Memory Speed & Timing: 3200mhz 16-18-18-36
HCI Test: 600%+

Just figured I'd post this here for anybody interested since this thread helped me test my OC. I was only looking to get advertised capable speeds of my ram. My BIOS reset when I attempted to use XMP profile, but I didn't try to adjust the voltage when doing so, instead I left it to auto. Second try I just manually put in the speed and clock cycles (3200mhz 16-18-18-36)of the RAM with 1.35v. First memtest had a memory error, likely due to me using the system while the test ran and messing up the first few instances of the memtest, but this test pictured is from a fresh boot with only what you see running on top of Avast and a few other background processes.


----------



## wolfpack122

[email protected] 1.175v---BIOS 1403-SP42M---Stressapptest---1 Hour--F4-3200C14D-16GTZ



Spoiler: Pictures here








I flashed BIOS 1403-SP42M and loosened my timings once more which resulted in better performance.

I also increased the resistance for the 'CAD Bus Drive Strength' as I was getting hardware errors during the stress test with the default values:

Clock Drive Strength = 30.0Ohm
Address / Command Drive Strength = 30.0Ohm
CS / ODT Drive Strength = 30.0Ohm
CKE Drive Strength = 30.0Ohm

BankGroupSwap is set to 'Disabled'.
BankGroupSwapAlt is set to 'Enabled'.

I noticed that tPHYRDL is 26 on 9943 while it's 24 on 1403-SP42M (not sure about the regular 1403). I am guessing this is the reason for the increased performance.

Edit: Thanks to Silent Scone and Jpmboy for pointing out how to properly set some of the timings.


----------



## 1TM1

Okay, this one's bout Hynix GTZB as 4x8GB: [email protected] 1.13v---BIOS 9945---HCI---200%

Now a bit more detail: C6H board, RAM is two kits of TridentZ F4-3200C16D-16GTZB single-rank single-sided, XMP-certified timings (per Thaiphoon) 16-18-18-38-56, FAW39,RRDS6,RRDL8 with Hynix M-die chips.

Tested twice (each HCI to >200%) with a cold boot (power off pull the plug) in between. Although four measurements are required to be statistically valid I did only two. However, if you _really_ need reliability you are better off running four tests with complete shutdowns in between.
  
This may or may not not work on other Hynix-M chips. ProcODT is 53 Ohms for 4x8; may be higher for 2x8. In prior BIOS memory liked 40 and 43 Ohms; with 9943-9945 it changed to 53 or 60.

At 1.435 and 1.425V DRAM wasn't stable. Lowering to 1.395 did the trick. At 3333-18-18-38, 3200-14-16-16-38-68 or 3200-16-16-16-37-64 it runs benches but makes HCI errors.

The effect of changing TRDRDSCL and TWRWRSCL from 6(auto) to 4 was: a black screen; changing from 6(auto) to 5 is: reduce one nanosecond.

Also usually when there's a power cycle during a lukewarm boot (shutdown but LEDs on C6H still on) HCI memtest will have errors.

Update: re-tested to 500% with tighter timings - still stable
[email protected] 1.00v---BIOS 9945---HCI---500%


----------



## gupsterg

@wolfpack122

Nice result







, +rep for share







.


----------



## azpc

Samsung C-die 4x8GB
[email protected] 1.15V---BIOS 9945---Stressapptest---1 Hour--M378A1K43CB2-CRC


----------



## Silent Scone

Quote:


> Originally Posted by *azpc*
> 
> Samsung C-die 4x8GB
> [email protected] 1.15V---BIOS 9945---Stressapptest---1 Hour--M378A1K43CB2-CRC


Although it reflects the modules, I would consider using a lower frequency if not able to lower the primaries there.

Apologies for inactivity this past week or so, very busy at the moment. Would much rather be active here


----------



## chroniclard

Anyone got a clue on what I should be tweaking to try and get this stable. Boots to windows fine and seems to work in general use but memtest errors fairly quickly.

1700X
Asus X370 prime pro
2 sticks only of Corsair Vengeance LPX - CMK32GX4M4B3466C16R
Believe its samsung b die


----------



## azpc

Quote:


> Originally Posted by *Silent Scone*
> 
> Although it reflects the modules, I would consider using a lower frequency if not able to lower the primaries there.


This modules worked at 16-17-17-39-1T with 1500X https://www.youtube.com/watch?v=TYOluJ0ncCA but in pair with 1700 i have no problems at Cl 20 only.


----------



## SaccoSVD

nice tango


----------



## Keith Myers

Quote:


> Originally Posted by *chroniclard*
> 
> Anyone got a clue on what I should be tweaking to try and get this stable. Boots to windows fine and seems to work in general use but memtest errors fairly quickly.
> 
> 1700X
> Asus X370 prime pro
> 2 sticks only of Corsair Vengeance LPX - CMK32GX4M4B3466C16R
> Believe its samsung b die


If the sticks really are Samsung B-die, those settings in RTC should be fine to run at 3200 Mhz. Can only guess that one or more sticks are bad. The only other suggestion I have is to put ProcODT at 60 ohms. That seems to be the best value for B-dies, two sticks, single rank at 3200 Mhz for me. I have the G.Skill F4-3600C16D-16GTZ and have no issues running at 3200 Mhz at 14-14-14-32-52-1T. If the Corsair LPX sticks really are B-die, they should be working for you.


----------



## Robenger

Quote:


> Originally Posted by *chroniclard*
> 
> Anyone got a clue on what I should be tweaking to try and get this stable. Boots to windows fine and seems to work in general use but memtest errors fairly quickly.
> 
> 1700X
> Asus X370 prime pro
> 2 sticks only of Corsair Vengeance LPX - CMK32GX4M4B3466C16R
> Believe its samsung b die


I'm almost positive those are Hynix chips. I have the same a similar set in white.


----------



## chroniclard

Looks to be Samsung B-Die, solid at 2933.


----------



## Robenger

Quote:


> Originally Posted by *chroniclard*
> 
> Looks to be Samsung B-Die, solid at 2933.


I stand corrected, as my CMK16GX4M2B3200C16W kit is Hynix, well at least I'm pretty sure. I assumed all the LPX stuff was Hynix as I have the exact same issue. Stuck at 2933.


----------



## Silent Scone

Quote:


> Originally Posted by *azpc*
> 
> This modules worked at 16-17-17-39-1T with 1500X https://www.youtube.com/watch?v=TYOluJ0ncCA but in pair with 1700 i have no problems at Cl 20 only.


What have you tried in terms of tuning?


----------



## seansplayin

Hi, Glad I found this thread.
I have A Ryzen 1800X with a custom water loop and the Asus Crosshair VI Hero and the Corsair Vengeance LPX CMK16GX4M2B3200C16 version 5.39 (hynix) Memory.
I have been on many bios's and have never been stable at 3200mt/s. I've tried bios, 704,1001,9943,1201 and currently on 1401. 704 was the closest to actually being stable at 3200 but would require some retries/resets, into the bios then out of the bios without saving changes to actually cold boot but other than that 3200 actually worked ok when in windows.
currently I'm on 1401 and it actually seems like ive gone backwards on stability from bios 9943. here are my observations:
I need to increase soc voltage to at least 1.12v-1.15v but further increases up to 1.25v don't seem to make any difference at all.
on bios 704 soc at 1.15V-1.2v with memory voltage at 1.5v and Vboot at 1.6v I was successful most of the time cold booting as long as the computer wasn't off for more than 8 hours and even sometimes It still cold booted even when it was off for 18 hours. this was the closest I've been to truly stable.
Bios 1001 was much worse and I ended up mostly running at 2666MT/s speed. nothing seemed to make much difference even loosening the default 3200 timings of 16-18-18-18-36-1T substantially, applying extreme memory settings like memory voltage 1.6v, vboot at 1.6v, vttddr at 0.85v and choose 2T, made no difference.
Bios 9943, not bad was stuck at 2933MT/s but system was very very stable when using the default 3200 memory timings of 16-18-18-18-36-1T. applying extreme settings memory at 1.6v, vboot at 1.6v, vttddr at 0.85v and increasing ProtODT to 80ohms which is the highest I can go the 3200 speed and not get beep errors on post but still made no difference and couldn't run at 3200MT/s.
now I'm on bios 1401 and I truly think we have a regression on memory speed. after clearing the cmos if I choose D.O.C.P 5, select 3200 memory speed, increase memory voltage to 1.4 and SOC voltage to 1.15v I will get a successful post but it does not mean reboots and definitely not cold boots will be successful. because I know all of the bios settings by heart at this point I simple cleared cmos, entered all my settings then I found somewhere under advanced that when enabled allows S4+S5 to be powered down when preparing the system for ERP. which enabled my computer to successfully sleep and I no longer have to do cold boots, it's a work around but so far it wakes successfully with the USB keyboard or Mouse and it's right at the windows desktop. Hibernation of course requires a boot up so I've disabled it. something kind of interesting is with my memory set at 2933 I can run the CPU core at 4100mhz however moving the memory speed up to 3200 makes the CPU unstable and I can either add more vcore voltage or just lower the speed by 25mhz. the interesting thing I actually score higher by 6 points at 4075mhz on cinebench R15 than I was scoring at 4100mhz with 2933 memory and it's not a memory intensive benchmark, right now in Cinebench I'm only 30 points behind my highest score even though my cpu is running 100mhz slower. My Y-Cruncher scores are up too but that's not really a surprise where it's extremely memory intensive so faster memory should produce a higher score. Just know you make have to add more vcore when running higher memory speed. I've saved my bios profile to a usb flash drive so If I have further problems posting I will just simply clear cmos and apply my settings from the usb flash drive.

incase anyone wants to know here are my other settings not related to memory:
Increased memory current to 120%, increased cpu current to 140%, increased SOC current to 120%.
CPU LLC at level 4 with Vcore voltage set to offset + 0.14
100mhz bclk, multi at 40.75 (4075mhz cpu)

cpu at 4075mhz, memory at 3200mt/s


cpu at 4100mhz, memory at 2933mt/s


Y-cruncher cpu at 4075mhz. memory at 3200mt/s


----------



## bluej511

Quote:


> Originally Posted by *Robenger*
> 
> I stand corrected, as my CMK16GX4M2B3200C16W kit is Hynix, well at least I'm pretty sure. I assumed all the LPX stuff was Hynix as I have the exact same issue. Stuck at 2933.


The lpx stuff is all over the place, one member has the same kit i do lpx 3200 cl16 and his memory is samsung edie dual rank, mine is hynix mdie single rank.

The lpx stuff is all over the place. And i can get 3200mhz on mine with timings of 14-16-34 just fine on the ch6.


----------



## SaccoSVD

I see things like this posted on other forums:



Spoiler: Warning: Spoiler!







And here's my most recent benchmark from my system:



Spoiler: Warning: Spoiler!







My RAM is running at 2933. Yes my latency is higher (82ns) than at 3326mhz (74.5) also the Memory throughput except for the copy value.

But look at the L1/2/3 cache numbers, he has almost half the throughput on those than mine (here in all my tests they're those numbers, within the margin of error). That got to harm performance a lot, no?

I see the only difference is his OC is only 3.9Ghz (mine is at 4Ghz) and he has an Asrock board.

EDIT: Oh I see, he is on a Ryzen 5. So less number of cores, less cache amount I guess,


----------



## azpc

Quote:


> Originally Posted by *Silent Scone*
> 
> What have you tried in terms of tuning?


I have changed this settings in various combinations:
VDRAM up to 1.37
Cmd 1T-2T
Gear Down Enabled, Disabled
ProcODT 34.3-96
DRAM Current Capability up to 130%
DRAM Swithing Freq. 400-500
VDDSOC LLC Level 1-4
VDDSOC Current Capability up to 130%

Some stabilyty i have with 18-18-18-40-2T and Trdrd = 5, but the system slow down.


----------



## Silent Scone

Quote:


> Originally Posted by *azpc*
> 
> I have changed this settings in various combinations:
> VDRAM up to 1.37
> Cmd 1T-2T
> Gear Down Enabled, Disabled
> ProcODT 34.3-96
> DRAM Current Capability up to 130%
> DRAM Swithing Freq. 400-500
> VDDSOC LLC Level 1-4
> VDDSOC Current Capability up to 130%
> 
> Some stabilyty i have with 18-18-18-40-2T and Trdrd = 5, but the system slow down.


Consider stabilising 3200, tightening primary and using up to 1.45v for VDIMM

Again apologies for inactivity will update the table over the weekend


----------



## Sufferage

[email protected] 1.1v---BIOS 9943---HCI---800%---F4-3600C16D-16GTZ

Complete timings used can be found in screenshot below.


Spoiler: Proof









P-State overclock through BIOS with set voltage of 1.34375, yields some pretty fine physics scores in 3DMark Skydiver and 3DMark11.


----------



## Ajjlmauen

How do these timings look? If anything looks very off please let me know :-D


----------



## Nighthog

I think tRAS is a bit high, could try lower? maybe all the way down to 30? (though take it in steps to see how far you can go)


----------



## hsn

hsn [email protected] 1.15v---BIOS 0805---Stressapptest 1hour-TeamDarkPro 16gb UD4-3200 CL14


----------



## Jpmboy

will have to live with the following speed and timings as this rig moves on to a day job. Just can't find the magic sauce to get tWTRL and tWR down to more reasonable values. even 12/24 fouls out in GSAT.








P-States OC, offset +0.0625V, 39.5x100. SOC 1.1V, vdimm 1.375V in bios.


----------



## 1TM1

[email protected] 1.175v---BIOS 9945---HCI---200%---F4-3200C16D-16GTZB
32GB RAM is 4x8 Hynix M (two kits of TridentZ F4-3200C16D-16GTZB) with 1800X in C6H. Using 2933 strap with 112.6 BCLK and 35.5 core multiplier. Stable to 200%+ HCI memtest which is >2 hours. SOC increase to 1.175V made memory stable (and surprisingly made latency lower). Other settings are: trdrdscl=twrwrscl=5, procodt=53, Vddr=Vddrboot=1.43V, vttddr=0.719V, memory timings and all else auto.

 
 

an update: re-tested this to 400% - still stable
[email protected] 1.175v---BIOS 9945---HCI---400%---F4-3200C16D-16GTZB


----------



## Silent Scone

Quote:


> Originally Posted by *Jpmboy*
> 
> will have to live with the following speed and timings as this rig moves on to a day job. Just can't find the magic sauce to get tWTRL and tWR down to more reasonable values. even 12/24 fouls out in GSAT.
> 
> 
> 
> 
> 
> 
> 
> 
> P-States OC, offset +0.0625V, 39.5x100. SOC 1.1V, vdimm 1.375V in bios.


On some of these cpu, I don't think there is any magic sauce. We've been spoilt


----------



## nexxusty

I notice a LOT of fluctuations in Aida64.

I dont currently consider it a useful program.

This or I am the king of Ryzen because this is stable and NO ONE has less than 60ns latency stable that I know of.... Not one person. This is done right after a "Normal" test in which I get my normal 64.0ns Memory latency. Which I consider to be the true number as its the number that comes up most often on the test.

Also look at my l1, l2 & l3 numbers. Ive seen 4.1ghz R7's with lower scores. Makes no sense.....

Well... It does make sense though. Aida64 IMO is not ready for Ryzen primetime.

wPrime is the best way IMO to test as latency directly translates to bandwidth/throughput anyway.

Any thoughts boys? When I say boys I mean.... Jpm, Scone, Praz, Elmor, Raja, The Stint... THE Boys.... Hehe.

***edit***

Oh and BTW, thanks for helping me learn Ryzen RAM OC and all the little nuances with the CH6 in about an hour or two. You boys are always on it so fast, by the time I get my new hardware its all been figured out for me.

B-Die 1 DPC Single Sided is where its at. Obviously. I do 3466mhz 14-14-14-14-28-1T. Using the majority of The Stints secondary timings allowed me to become stable.

Nothing is faster currently on Ryzen (as we know 3600mhz is dreadfully slow ATM with the way UEFI is handling that clock speed) than 3466mhz C14/1T.


----------



## SaccoSVD

Quote:


> Originally Posted by *nexxusty*
> 
> 
> 
> I notice a LOT of fluctuations in Aida64.
> 
> I dont currently consider it a useful program.
> 
> This or I am the king of Ryzen because this is stable and NO ONE has less than 60ns latency stable that I know of.... Not one person. This is done right after a "Normal" test in which I get my normal 64.0ns Memory latency. Which I consider to be the true number as its the number that comes up most often on the test.
> 
> Also look at my l1, l2 & l3 numbers. Ive seen 4.1ghz R7's with lower scores. Makes no sense.


Me too, but the latency results tend to be really consistent.


----------



## nexxusty

Quote:


> Originally Posted by *SaccoSVD*
> 
> Me too, but the latency results tend to be really consistent.


Seriously?

The situation for me is the EXACT opposite. My bandwidth remains within 300mb/s each time but my latency for everything else, Cache included is all over the place.

I can get 59.6ns and 66.7ns Memory Latency on the same boot.

Im now slightly even more confused lol...

I also (correct me if I am wrong here) have not seen a 4ghz (stable) Ryzen R7 with RAM clocked high. I only see 3466mhz C14 and 3.9ghz... Never 4.0ghz. Ive seen 4.0ghz/3200mhzC14 but that's weak.

Lol if I wanted 3200mhz I wouldn't even be a member here. Heh.


----------



## zeroibis

Quote:


> Originally Posted by *nexxusty*
> 
> Seriously?
> 
> The situation for me is the EXACT opposite. My bandwidth remains within 300mb/s each time but my latency for everything else, Cache included is all over the place.
> 
> I can get 59.6ns and 66.7ns Memory Latency on the same boot.
> 
> Im now slightly even more confused lol...
> 
> I also (correct me if I am wrong here) have not seen a 4ghz (stable) Ryzen R7 with RAM clocked high. I only see 3466mhz C14 and 3.9ghz... Never 4.0ghz. Ive seen 4.0ghz/3200mhzC14 but that's weak.
> 
> Lol if I wanted 3200mhz I wouldn't even be a member here. Heh.


Meanwhile, I am hoping just to be able to get at least 3200mhz lol, but in my case I need at least 32gb and everyone is playing with 16gb.


----------



## crakej

sorry - repeat post!


----------



## Jpmboy

Quote:


> Originally Posted by *wolfpack122*
> 
> Is it possible to get worse performance from tightening any of the memory's timings too much, even while passing stress tests?


oh. for sure. happens all the time for benchmarks.
Quote:


> Originally Posted by *Silent Scone*
> 
> On some of these cpu, I don't think there is any magic sauce. We've been spoilt


Tight...


----------



## colorfuel

I'm having a bit of a difficulty accepting these high speeds on this AIDA64 test.

The latency seems normal, but the read/write/copy speeds seem to good to be true.

btw, I've only run Memtest (16x850)up to a little over 100% on these settings until now, I'll do that 400% later tonight.


----------



## Ajjlmauen

Quote:


> Originally Posted by *colorfuel*
> 
> I'm having a bit of a difficulty accepting these high speeds on this AIDA64 test.
> 
> The latency seems normal, but the read/write/copy speeds seem to good to be true.
> 
> btw, I've only run Memtest (16x850)up to a little over 100% on these settings until now, I'll do that 400% later tonight.


That is really weird...


----------



## Clukos

This looks promising


















LLC3 vcore 1.375 during load
LLC2 vcsoc 1.1625 in BIOS 1.14-1.15 after vdroop
1.42vdimm + vboot in BIOS


----------



## Ajjlmauen

Quote:


> Originally Posted by *Clukos*
> 
> This looks promising
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> LLC3 vcore 1.375 during load
> LLC2 vcsoc 1.1625 in BIOS 1.14-1.15 after vdroop
> 1.42vdimm + vboot in BIOS


Dont mind if copy this and try it on my sticks


----------



## datspike

Spoiler: Old result HOF 3600c17 2*8Gb @ loose 3200c14



Hell yeah, finally did it!

Asus B350-F Strix
1600X - ZenStates [email protected]
[email protected] 1.1v---BIOS 0805---Stressapptest---1h---HOF4CXLBS3600K17LD162K


I'm using KFA2 / GALAX HOF 3600c17 2*8Gb kit and it was nightmare to get it working at 3200 CL14.
Started 2 days ago with no experience with ram overclocking, started with







Stilt's







safe 3200 timings. Tried tweaking tRAS, tRC, tRFC and other values as seen in that thread - ended up with the same instability or even worse.
The problem was that my kit needs tWR = 2*tRTP for some reason, also those values are as high as stock CL17 ones from my 3200 stock profile.
Also I was having some luck yesterday with Stilt's 3333 safe profile after some tweaking, but the memory is unstable today for some reason, will try to stabilize it right now.


----------



## mablo

Quote:


> Originally Posted by *datspike*
> 
> 
> 
> 
> 
> 
> 
> 
> Stilt's
> 
> 
> 
> 
> 
> 
> 
> safe 3200 timings


Mind PMing me a link to that thread or post? I cannot seem to get my Corsair sticks working on the same board as you. Cheers.


----------



## datspike

Hehe, I was searching for them just like you. Here they are:
1) 3200 safe/fast + 3333 safe/fast
2) His 3466 config (i've lost the post url, so only pic)
Ryzen Essential Info thread by gupsterg. I believe there is a link to 3466 timings somewhere on that page, also a lot of useful info and links


----------



## mablo

Riddle me this all you nerds.

The setting: R5 1600, Asus B350-F Strix, Corsair LPX CMK16GX4M2B3000C15 v5.20 (Hynix chips i believe).

I cannot get windows to play nice. All the worlds BSODs i get. Crashes and freezes. Tried getting the memories to work via DOCP. 1.36v mem voltage, SOC 1.1, proc ODT from 40 to 68.3. Nothing worked.

However, and here is the head-scratcher, I have on two occasions (i think both had procODT auto, and some small difference I cannot remember atm) gotten 400% passes in hci memtest, and 25+ loops in Memtest64,. But windows crashes when using it normally. First of the occasions after i finished 2 hours of tests i thought i'd give gaming a go and it crashed before i even got to opening steam. Mouse cursor started suddenly to lag and then BSOD and rest.

I'm at my wit's end here and either i have a defective board or memories, or the two are the most incompatible components.
Sure I have also to learn a lot about memory OC but still.

Help me out here. Cheers.


----------



## soupernoodle

I've got a kit of F4-3600C17D-16GVK, it doesn't boot passed 3200 so assume i need to mess around with these sub timings, is there a template to start from with these sort of things? Because i have absolutely no idea what the average value of any of these timings are, or how much to adjust them and which way,

Also, does anyone have an idea of what i could potentially get this kit to run at, or if it's likely it could run at the rated speeds.


----------



## yendor

Quote:


> Originally Posted by *mablo*
> 
> Riddle me this all you nerds.
> 
> The setting: R5 1600, Asus B350-F Strix, Corsair LPX CMK16GX4M2B3000C15 v5.20 (Hynix chips i believe).
> 
> I cannot get windows to play nice. All the worlds BSODs i get. Crashes and freezes. Tried getting the memories to work via DOCP. 1.36v mem voltage, SOC 1.1, proc ODT from 40 to 68.3. Nothing worked.
> 
> However, and here is the head-scratcher, I have on two occasions (i think both had procODT auto, and some small difference I cannot remember atm) gotten 400% passes in hci memtest, and 25+ loops in Memtest64,. But windows crashes when using it normally. First of the occasions after i finished 2 hours of tests i thought i'd give gaming a go and it crashed before i even got to opening steam. Mouse cursor started suddenly to lag and then BSOD and rest.
> 
> I'm at my wit's end here and either i have a defective board or memories, or the two are the most incompatible components.
> Sure I have also to learn a lot about memory OC but still.
> 
> Help me out here. Cheers.


Hynix, MFR. The timings you asked about earlier were for samsung bdie kits. The relevant question would be what what method you'ev used to get to higher speed. Most of us worked our way up with the less compatible kits by setting docp or whatever teh boards version of xmp was and climbing one setting up at a time . usually just by starting with a lower frequency and rebooting til that didn't work then loosening timings.

Quote:


> Originally Posted by *soupernoodle*
> 
> I've got a kit of F4-3600C17D-16GVK, it doesn't boot passed 3200 so assume i need to mess around with these sub timings, is there a template to start from with these sort of things? Because i have absolutely no idea what the average value of any of these timings are, or how much to adjust them and which way,
> 
> Also, does anyone have an idea of what i could potentially get this kit to run at, or if it's likely it could run at the rated speeds.


And you do have a a bdie kit. Template? Well there's the stilt's timings referenced earlier or you could use the timings from the amd gaming post. Most of which look a lot like stilt's timings for asus crosshair. 3200 version worked for prime and b350 asus boards. And may not work at all for another vendors. ymmv.

3600 possible if you have the full range of 1.0.0.6 available.. But as the article I linked above indicates performance is not necessarily synonymous with ram frequency. Not at 3200 +.


----------



## mablo

Yeah I realized the timings were for Samsung dies when i read them. I lived under the impression he was posting General timings to try. I might still give them a try some day.

As to settings I used DOCP for all my tests, since it sets SOC voltage to 1.1 by itself. Otherwise voltage is set by offset on the board.

Don't know. Just unlucky memories i guess and some Hynix chips are still iffy. Going on vacation soon but most likely when i get back i will try and sell them and get a pair of Samsung based sticks even if i shell out more bucks. Or hopefully some new bios comes out and fixes all the issues.


----------



## majestynl

Quote:


> Originally Posted by *soupernoodle*
> 
> I've got a kit of F4-3600C17D-16GVK, it doesn't boot passed 3200 so assume i need to mess around with these sub timings, is there a template to start from with these sort of things? Because i have absolutely no idea what the average value of any of these timings are, or how much to adjust them and which way,
> 
> Also, does anyone have an idea of what i could potentially get this kit to run at, or if it's likely it could run at the rated speeds.


Before you do any tweaks on sub-timings, just set your main fabric timings right (can see on the RAM website or package),
and try to let them run on 3200Mhz.

Settings you can try after above:

- ProDT try different values
- Ram voltage
- VDDR half of ram
- Vsoc
- Running 2T instead of 1T

There is no way you can run them on higher clocks with tweaking sub-timings vs fabric timings.Most of the time is the opposite!
After you can run on wished speeds, you can start to tighten the sub-timings!


----------



## soupernoodle

Quote:


> Originally Posted by *majestynl*
> 
> Before you do any tweaks on sub-timings, just set your main fabric timings right (can see on the RAM website or package),
> and try to let them run on 3200Mhz.
> 
> Settings you can try after above:
> 
> - ProDT try different values
> - Ram voltage
> - VDDR half of ram
> - Vsoc
> - Running 2T instead of 1T
> 
> There is no way you can run them on higher clocks with tweaking sub-timings vs fabric timings.Most of the time is the opposite!
> After you can run on wished speeds, you can start to tighten the sub-timings!


Currently i'm running them at [email protected], but i can't push it passed 3200 at all with the rated timings nor with looser timings, 1.35-1.4v 1.1soc


----------



## majestynl

Quote:


> Originally Posted by *soupernoodle*
> 
> Currently i'm running them at [email protected], but i can't push it passed 3200 at all with the rated timings nor with looser timings, 1.35-1.4v 1.1soc


Give a try with the options a gave you above. I'm running 3466 with 1.15soc(auto for me), 53.3ohm, vboot same as Ram voltage.

And at last you can try set to 2T (commandrate)


----------



## andydabeast

Here is a question. Maybe splitting hairs here. For Gskill 2x8gb which would you choose?

-3200mhz @ 16-18-18-38 $127
-3000mhz @ 15-15-15-35 $140


----------



## miklkit

I just started buying parts for my Ryzen build and have some questions about which ram to buy.

First, is there any real difference between TridentZ and Ripjaws? I am only considering G Skill ram.

Second, this is the ram I am looking at off the QVL list. https://www.newegg.com/Product/Product.aspx?item=N82E16820231953

It is 4 sticks because that is how I roll. There are 4 slots and leaving 2 of them empty is ugly so there will be 4 sticks used. Yes this will limit my OC and I'm ok with that.

So the question is if I should get that and run it much lower than its rated speed or would I be better off with, say, 3200 ram? With 4 sticks I doubt if it will even get that far.

The motherboard is a Biostar GT7.


----------



## majestynl

Quote:


> Originally Posted by *andydabeast*
> 
> Here is a question. Maybe splitting hairs here. For Gskill 2x8gb which would you choose?
> 
> -3200mhz @ 16-18-18-38 $127
> -3000mhz @ 15-15-15-35 $140


if $13 doesn't make you poor







, definitely go for lowest CAS!


----------



## majestynl

Quote:


> Originally Posted by *miklkit*
> 
> I just started buying parts for my Ryzen build and have some questions about which ram to buy.
> 
> First, is there any real difference between TridentZ and Ripjaws? I am only considering G Skill ram.
> 
> Second, this is the ram I am looking at off the QVL list. https://www.newegg.com/Product/Product.aspx?item=N82E16820231953
> 
> It is 4 sticks because that is how I roll. There are 4 slots and leaving 2 of them empty is ugly so there will be 4 sticks used. Yes this will limit my OC and I'm ok with that.
> 
> So the question is if I should get that and run it much lower than its rated speed or would I be better off with, say, 3200 ram? With 4 sticks I doubt if it will even get that far.
> 
> The motherboard is a Biostar GT7.


I would go for the TridentZ! I never had any issues with them! On Intel or AMD.
Samsung B-die still works te best.
You can also Check this list setup by a ASUS rep: Link


----------



## miklkit

So Ripjaws are Hynix? TridentZ it is.

Hmm. Nobody is running 4x4. Instead they are running 4x8 or 4x16. It probably makes no difference.

Since almost nobody is going over 3200, that is probably what I should buy.


----------



## yendor

Quote:


> Originally Posted by *miklkit*
> 
> So Ripjaws are Hynix? TridentZ it is.
> 
> Hmm. Nobody is running 4x4. Instead they are running 4x8 or 4x16. It probably makes no difference.
> 
> Since almost nobody is going over 3200, that is probably what I should buy.


A) Don't know if anyone is running 4x 8 or 16. But we have several other owners who have the BIostar Gt7 and merely mentioning the name has the magic ability to summon them .. taps foot...
B) RIpjaws is not necessarily hynix. A list of the ic's in various kits exists on reddit but the author also has it posted here. several kits are bdie. some are dual ranked.

http://www.overclock.net/t/1627555/ryzen-memory-ic-collection-thread/0_20

C) The overclock leader board has owners who've validated.. click on validation links for your board.. (There is probably a way to search cpu-z validations. too tired at the moment to look)
https://docs.google.com/spreadsheets/d/1Dbt_7FiD8hTo2uuOIKBE3ATCDRqVRpAHFsKnieEncv0/edit#gid=87938175

D) Gupsterg's daily driver list includes kits used and the speed they're run at as well as cpu batch info, daily oc etc. hm, could use some more info from owners. (big slacker here... )

https://docs.google.com/spreadsheets/d/1DqctoWXeutgIqkxScE53g6CXDVy6Xp8oyHDucYrVnC0/edit#gid=992367044


----------



## miklkit

Nice. Tighter timings and $18 less. https://www.newegg.com/Product/Product.aspx?Item=N82E16820231940


----------



## andydabeast

Quote:


> Originally Posted by *majestynl*
> 
> if $13 doesn't make you poor
> 
> 
> 
> 
> 
> 
> 
> , definitely go for lowest CAS!


Thanks! 18 down to 15 seemed drastic enough to warrant $13 but to get to cas 14 it would cost another $30 or go down to 2400mhz. I think 3000mhz CL15 is a good value sweet spot.


----------



## majestynl

Cool! Success with your build!


----------



## Infuriare

[email protected] 1.1v---BIOS 1403---Stressapptest---1 Hour---CMK32GX4M4B3600C18



This kit was a PITA to get 100% stable when compared to other kits posted here.
It seems that giving them more voltage, enabling GDM and loosening tWR was needed to get them to pass Stressapptest.


----------



## datspike

Some strange things are happening today.
I was curious to try using another pair of memory slots so changed from the slots 2&4 to 1&3.
Got a lot of errors in the quick memtest86 run - reseated the memory back to the slots 2&4, but changed the sticks places.
Now I can get a bit tighter timings and the lowest ProcODT setting I can boot is 53,3Ohm now, while it was 80Ohm yesterday.
Strange, but I'll take it.


----------



## djleakyg

I made a post in the R7 thread and just found this thread. I think my post belongs here.

Hey guys,

I came across this thread and I am really stoked to be a Ryzen 7 owner. I am likely going to MicroCenter today or tomorrow to pickup an R7 1700X, MSI X370 Gaming Pro Carbon, and some EVGA DDR4 RAM ( basically rebranded G.Skills RipJaws). I know that the BIOS(s) ( yes I know it has UEFI) have been tweaked quite a bit but I am still a little nervous with using higher clocked RAM. I have historically always bought middle of the road RAM. When DDR2 was still fresh and new, I opted for 800 instead of 1067, when DDR3 was king, I first opted for 1333 MHz ( got a screaming deal on 16GB at the time) and then later 1600/1866 MHz in favor of lower CAS latencies.

This time around, I want to really buy high end RAM. At time of writing this post, VRAM is at the highest price it has been since late 2012 early 2013. I am opting for a 16GB ( two 8GB DIMMS). Will I be OK getting DDR4 3000? I live really close so I can return it but I really don't want to if I don't have to.

http://www.microcenter.com/product/459741/16GB_2_x_8GB_DDR4-3000_(PC4-24000)_CL15_Desktop_Memory_Kit

Thanks in advance.


----------



## polkfan

Mine for example are Samsung B-day but dual ranked I got mine at 3066mhz at 16-16-16-36 at 1.4V, edit now 1.35V


----------



## Robenger

Quote:


> Originally Posted by *djleakyg*
> 
> I made a post in the R7 thread and just found this thread. I think my post belongs here.
> 
> Hey guys,
> 
> I came across this thread and I am really stoked to be a Ryzen 7 owner. I am likely going to MicroCenter today or tomorrow to pickup an R7 1700X, MSI X370 Gaming Pro Carbon, and some EVGA DDR4 RAM ( basically rebranded G.Skills RipJaws). I know that the BIOS(s) ( yes I know it has UEFI) have been tweaked quite a bit but I am still a little nervous with using higher clocked RAM. I have historically always bought middle of the road RAM. When DDR2 was still fresh and new, I opted for 800 instead of 1067, when DDR3 was king, I first opted for 1333 MHz ( got a screaming deal on 16GB at the time) and then later 1600/1866 MHz in favor of lower CAS latencies.
> 
> This time around, I want to really buy high end RAM. At time of writing this post, VRAM is at the highest price it has been since late 2012 early 2013. I am opting for a 16GB ( two 8GB DIMMS). Will I be OK getting DDR4 3000? I live really close so I can return it but I really don't want to if I don't have to.
> 
> http://www.microcenter.com/product/459741/16GB_2_x_8GB_DDR4-3000_(PC4-24000)_CL15_Desktop_Memory_Kit
> 
> Thanks in advance.


https://rymem.vraith.com/specific/24


----------



## datspike

Was able to really tighten my 3200c14 timings even more and get more stability after swapping the sticks between each other slots. Very strange.
Also it seems like HCI memtest is more stressful that GSAT for me. My last configuration, which was stable after 2h GSAT run was giving me errors at 100-150% HCI memtest.
My memory kit is GALAX HOF 3600C17 2*8Gb.

Asus B350-F Strix
1600X - Pstates [email protected]~1.206v SVI2 sensor under load, LLC - Regular, voltage set in bios is 1.225v

[email protected] 1.125v---BIOS 0805 modded---HCI---1250%---HOF4CXLBS3600K17LD162K


Spoiler: 1366*768 screens :(


----------



## Praz

Quote:


> Originally Posted by *datspike*
> 
> Was able to really tighten my 3200c14 timings even more and get more stability after swapping the sticks between each other slots. Very strange.
> Also it seems like HCI memtest is more stressful that GSAT for me. My last configuration, which was stable after 2h GSAT run was giving me errors at 100-150% HCI memtest.
> My memory kit is GALAX HOF 3600C17 2*8Gb.
> 
> Asus B350-F Strix
> 1600X - Pstates [email protected]~1.206v SVI2 sensor under load, LLC - Regular, voltage set in bios is 1.225v
> 
> [email protected] 1.125v---BIOS 0805 modded---HCI---1250%---HOF4CXLBS3600K17LD162K
> 
> 
> Spoiler: 1366*768 screens :(


Hello

Swapping modules between slots is part of memory binning. HCI will pick up memory/IMC interface issues where GSAT pretty much isolates memory testing only.


----------



## Silent Scone

Thanks for all the recent entries. The platform has started to come into its own, finally.


----------



## gupsterg

Quote:


> Originally Posted by *andydabeast*
> 
> Here is a question. Maybe splitting hairs here. For Gskill 2x8gb which would you choose?
> 
> -3200mhz @ 16-18-18-38 $127
> -3000mhz @ 15-15-15-35 $140
> Quote:
> 
> 
> 
> Originally Posted by *majestynl*
> 
> if $13 doesn't make you poor
> 
> 
> 
> 
> 
> 
> 
> , definitely go for lowest CAS!
> 
> 
> 
> 
> 
> 
> 
> 
> Quote:
> 
> 
> 
> Originally Posted by *andydabeast*
> 
> Thanks! 18 down to 15 seemed drastic enough to warrant $13 but to get to cas 14 it would cost another $30 or go down to 2400mhz. I think 3000mhz CL15 is a good value sweet spot.
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

So far the "platform" luvs Samsung B die. So my opinion wait if you have to, save the $ and get Samsung B die kit. This thread has nice info. Results you can see in OP of this for Samsung B die.
Quote:


> Originally Posted by *Infuriare*
> 
> [email protected] 1.1v---BIOS 1403---Stressapptest---1 Hour---CMK32GX4M4B3600C18
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 
> 
> 
> 
> This kit was a PITA to get 100% stable when compared to other kits posted here.
> It seems that giving them more voltage, enabling GDM and loosening tWR was needed to get them to pass Stressapptest.


+rep, nice result share







.
Quote:


> Originally Posted by *yendor*
> 
> D) Gupsterg's daily driver list includes kits used and the speed they're run at as well as cpu batch info, daily oc etc. hm, could use some more info from owners. (big slacker here... )
> 
> https://docs.google.com/spreadsheets/d/1DqctoWXeutgIqkxScE53g6CXDVy6Xp8oyHDucYrVnC0/edit#gid=992367044


Was a great idea. Members lost interest in giving data







. I did try chasing people at times, but as it kept taking up so much time, it was better to use time for something more productive







.


----------



## crakej

Quote:


> Originally Posted by *gupsterg*
> 
> Was a great idea. Members lost interest in giving data
> 
> 
> 
> 
> 
> 
> 
> . I did try chasing people at times, but as it kept taking up so much time, it was better to use time for something more productive
> 
> 
> 
> 
> 
> 
> 
> .


Happy to add my stats - it's a really useful doc!

Just requested access


----------



## gupsterg

Will create a google form, ETA ~Monday







.

[email protected]75v---SOC 1.05v---BIOS 9920---HCI---2300%--F4-3200C14D-16GTZ

CPU Batch: UA 1710SUS
ProcODT: 60Ω



Only got this CPU Thursday. As stock SOC was ~900mV and other R7 1700 had needed between 1.05V to 1.075V for 3333MHz Fast I opted for 1.05V as guesstimate. 3333MHz Fast 1.375V 1.05V showed no issues in other stress tests, so I envisaged 3466MHz would be fine for RAM stress testing. Now putting rig through x264, etc.

Below is AIDA64 for 3333MHz Fast and 3466MHz, both The Stilt's setup.




For me this is first time at tight 3466MHz







. Luv'ing the C6H







.

Thank you Elmor, [email protected], The Stilt and others







.


----------



## djleakyg

This might be a stupid question but is there a way you can verify which die your RAM came from? I know there is a list to compare against of known good SN's but I picked up some EVGA RAM while my G.Skills 3200 Kit is on its way. I am just curious if this EVGA stuff is b die or not.


----------



## finalheaven

Quote:


> Originally Posted by *djleakyg*
> 
> This might be a stupid question but is there a way you can verify which die your RAM came from? I know there is a list to compare against of known good SN's but I picked up some EVGA RAM while my G.Skills 3200 Kit is on its way. I am just curious if this EVGA stuff is b die or not.


There are databases like Thaiphoon Burner which might be able to tell you. Otherwise the best way is to open the heatsinks and read the SN on the chips.


----------



## yendor

Quote:


> Originally Posted by *djleakyg*
> 
> This might be a stupid question but is there a way you can verify which die your RAM came from? I know there is a list to compare against of known good SN's but I picked up some EVGA RAM while my G.Skills 3200 Kit is on its way. I am just curious if this EVGA stuff is b die or not.


http://www.softnology.biz/

free version of thaiphoon burner will show you the die version, chip size, process . ranks. various spd data inc timings. handy.


----------



## kushorange

Anyone have any more advice or ideas for tightening the memory?

Using a k7 mobo, Flare-X memory 3200mhz. Ryzen 1700 at 3.85ghz


----------



## datspike

@kushorange
When I was trying to tighten my 3200 timings I've did something like this, checking for stability to 50-100% with hcimemtest at every step:
1) lower tRAS and tRC by 2 at a time
2) tRRDS to 4 and then if stable try lowering tFAW by 2 at a time
3) then try tRTP to 6
4) then tRFC by 5 at a time
As a result my Euler3d memory score increased by 500 at least at the same frequency.

It maybe not the best and scientific way to do it, but worked for me









Too bad that my memory kit cant do stable 3200+ Mhz, or maybe it's the B350-F does not want to overclock my memory.
I'm getting random errors even with loosened Stllt's 3333 safe timings.


----------



## Spanners

Quote:


> Originally Posted by *kushorange*
> 
> Anyone have any more advice or ideas for tightening the memory?
> 
> Using a k7 mobo, Flare-X memory 3200mhz. Ryzen 1700 at 3.85ghz


You could try both the "SCL" timings at 2. Everything else looks pretty good to my quick glace.


----------



## crakej

So who's got their ram faster than 3200 on this board?


----------



## zeroibis

Quote:


> Originally Posted by *crakej*
> 
> So who's got their ram faster than 3200 on this board?


What board?


----------



## crakej

Quote:


> Originally Posted by *zeroibis*
> 
> What board?


Sorry.....wrong thread! ASUS Prime X370


----------



## Silent Scone

Quote:


> Originally Posted by *crakej*
> 
> Sorry.....wrong thread! ASUS Prime X370


Is it the wrong thread?


----------



## crakej

Quote:


> Originally Posted by *Silent Scone*
> 
> Is it the wrong thread?


Well no, but yes, I did mean to post elsewhere but would be interested if anyone with same board has got their ram over 3200 reliably.


----------



## Keith Myers

I tried for a couple of days to get Stilt's 3333 and 3466 memory timings to work. I had no issues getting into Windows. But I would fail on GSAT memory testing or Prime95 testing. Since I run full-stop all cores all the time on distributed computing projects, I need stability. Have just fallen back to my stable CL14 optimized Stilt 3200 setting. ASUS Prime X370 Pro mother board and G. Skill F4-3600C16D-16GTZ memory kit.


----------



## SRT turbo

Anyone have any luck with Gskill's F4-3200C14D-32GVK kit? I have a Gigabyte AX370 gaming K7 and 1700x and can't seem to do anything over 2133mhz.


----------



## Silent Scone

Quote:


> Originally Posted by *SRT turbo*
> 
> Anyone have any luck with Gskill's F4-3200C14D-32GVK kit? I have a Gigabyte AX370 gaming K7 and 1700x and can't seem to do anything over 2133mhz.


No experience with that board, but the memory kit should be fine when dialed in correctly. Not being able to do any more than 2133 is fairly unusual. Can you list your current settings and what you've tried thus far.


----------



## crakej

Quote:


> Originally Posted by *Keith Myers*
> 
> I tried for a couple of days to get Stilt's 3333 and 3466 memory timings to work. I had no issues getting into Windows. But I would fail on GSAT memory testing or Prime95 testing. Since I run full-stop all cores all the time on distributed computing projects, I need stability. Have just fallen back to my stable CL14 optimized Stilt 3200 setting. ASUS Prime X370 Pro mother board and G. Skill F4-3600C16D-16GTZ memory kit.


How far did you push your SoC and ram voltages?


----------



## Keith Myers

Quote:


> Originally Posted by *crakej*
> 
> How far did you push your SoC and ram voltages?


I added 0.00625V + offset to the stock 1.05V SoC and LLC1 to overcome the Vdroop that was taking the Vsoc down to 1.03V. Now Vsoc SVI2 is rock solid exactly at 1.10V. I have the ram at 1.38V in the BIOS. Wish our motherboard exported the DIMM voltage.


----------



## datspike

Quote:


> Originally Posted by *Keith Myers*
> 
> I added 0.00625V + offset to the stock 1.05V SoC and LLC1 to overcome the Vdroop that was taking the Vsoc down to 1.03V. Now Vsoc SVI2 is rock solid exactly at 1.10V. I have the ram at 1.38V in the BIOS. Wish our motherboard exported the DIMM voltage.


Wow.
Seems like you have opened my eyes on the problem which my B350-F strix has.
I just set the LLC to extreme and vSOC to 1.125 - now it's stable at 1.1V exactly. 3333 Fast Stilt's preset is already passed 100% in HCI memtest, which I cannot do before.
Huge thanks.

Update.
400% stable yaay!
I've struggled a lot to get the memory stable and even tried to up the soc voltage to 1.175 but never considered that there is such a large vdroop on my boards soc vrm.
Will try 3466 and 3600 now.

Edit - I was dumb and forgot to change the frequency. Also the vrm's are not that bad as i've said.


----------



## crakej

Quote:


> Originally Posted by *Keith Myers*
> 
> I tried for a couple of days to get Stilt's 3333 and 3466 memory timings to work. I had no issues getting into Windows. But I would fail on GSAT memory testing or Prime95 testing. Since I run full-stop all cores all the time on distributed computing projects, I need stability. Have just fallen back to my stable CL14 optimized Stilt 3200 setting. ASUS Prime X370 Pro mother board and G. Skill F4-3600C16D-16GTZ memory kit.


what were your timings to boot at 3466?


----------



## Keith Myers

I used The Stilt's published timings for my ram kit from Ryzen Timing Checker, which was the 'relaxed' version. 14-14-14-14-28-54-1T-333-tRFC-Geardown Disabled verbatim. It booted into Windows 10 fine and was stable for normal computer activities like reading email, browsing, finance and such all day. However, put the computer to work in its normal duties which is crunching and it would black screen in 1-6 hours. Not usable for my conditions. I don't game but I do have 2 GTX 1070s and one GTX 1060 running flat out and overclocked crunching for SETI, Einstein and MilkyWay projects.

I have the cruncher rock stable for weeks now running 24/7 at 3200 CL14 with The Stilts 3200 timings.

[Edit] Forgot to mention ... ProcODT at 60 ohms. That makes a big difference. 53.3 was not bootable.


----------



## majestynl

Quote:


> Originally Posted by *Keith Myers*
> 
> I tried for a couple of days to get Stilt's 3333 and 3466 memory timings to work. I had no issues getting into Windows. But I would fail on GSAT memory testing or Prime95 testing. Since I run full-stop all cores all the time on distributed computing projects, I need stability. Have just fallen back to my stable CL14 optimized Stilt 3200 setting. ASUS Prime X370 Pro mother board and G. Skill F4-3600C16D-16GTZ memory kit.


First of all I tested 1000 different values, timings and leterly every single timing value.

1 important thing is, if you want stability and you have the time. You need to tighten the timings 1 by 1 and see the effect.

2 don't just increase your dimm or soc voltage if you aren't stable with memtest or any stability test that uses memory/cpu.

After long test period I found my vcore caused instability with tight timings.
And to high dimmm voltage also.

So change 1 value at the time and just make a lot of testing. I would start with vcore. Just add some extra few notches just to test if that's the issue. Then don't go to high with vdimm. Accurate vdimm is also important. Higher vdimm can lead to instability.


----------



## Keith Myers

Quote:


> Originally Posted by *majestynl*
> 
> First of all I tested 1000 different values, timings and leterly every single timing value.
> 
> 1 important thing is, if you want stability and you have the time. You need to tighten the timings 1 by 1 and see the effect.
> 
> 2 don't just increase your dimm or soc voltage if you aren't stable with memtest or any stability test that uses memory/cpu.
> 
> After long test period I found my vcore caused instability with tight timings.
> And to high dimmm voltage also.
> 
> So change 1 value at the time and just make a lot of testing. I would start with vcore. Just add some extra few notches just to test if that's the issue. Then don't go to high with vdimm. Accurate vdimm is also important. Higher vdimm can lead to instability.


Yes, I was changing one value at a time and observing the effect on instability. I used GSAT and P95 for quick and dirty likely candidates and then started my crunching. That is my final stabilty test. Does it keep crunching without black screening for days/weeks. I have spent the last 3 months trying to get the fastest production out of my cruncher.

The Ryzen system is stable and is #33 in the Top 100 Hosts at SETI. I have been preoccupied for the past week trying to get a new linux cruncher running and have back-burnered the Ryzen system for now. I still would like to push the memory faster if possible. I have observed diminishing returns on system production for each bump in memory speed.


----------



## Infuriare

Quote:


> Originally Posted by *datspike*
> 
> Some strange things are happening today.
> I was curious to try using another pair of memory slots so changed from the slots 2&4 to 1&3.
> Got a lot of errors in the quick memtest86 run - reseated the memory back to the slots 2&4, but changed the sticks places.
> Now I can get a bit tighter timings and the lowest ProcODT setting I can boot is 53,3Ohm now, while it was 80Ohm yesterday.
> Strange, but I'll take it.


So after seeing this I decided to swap my 2x8GB dimms that I have in my C6H between the channels and immediately got stability at much tighter timings. I just got around to running GSAT for an hour and it confirmed that they are indeed stable when they previously weren't. Remember to swap your dimms people!

[email protected] 1.1v---BIOS 9920---Stressapptest---1 Hour---CMK32GX4M4B3600C18


----------



## djleakyg

Memory Thread Guru's

I am going to replace my Hynix based EVGA ( Really G Skills) RAM. These are my 5 options. What would you go with & why?

https://www.newegg.com/Product/Productcompare.aspx?CompareItemList=-1%7C20-232-221%5E20-232-221%2C20-232-184%5E20-232-184%2C20-232-205%5E20-232-205%2C20-232-209%5E20-232-209%2C20-232-217%5E20-232-217

https://www.newegg.com/Product/Product.aspx?Item=N82E16820232221
https://www.newegg.com/Product/Product.aspx?Item=N82E16820232184
https://www.newegg.com/Product/Product.aspx?Item=N82E16820232209
https://www.newegg.com/Product/Product.aspx?Item=N82E16820232217
https://www.newegg.com/Product/Product.aspx?Item=N82E16820232205

Money isn't a huge object here, just want to know which of these are the best option to go with.


----------



## yendor

Quote:


> Originally Posted by *djleakyg*
> 
> Memory Thread Guru's
> 
> I am going to replace my Hynix based EVGA ( Really G Skills) RAM. These are my 5 options. What would you go with & why?
> 
> https://www.newegg.com/Product/Productcompare.aspx?CompareItemList=-1%7C20-232-221%5E20-232-221%2C20-232-184%5E20-232-184%2C20-232-205%5E20-232-205%2C20-232-209%5E20-232-209%2C20-232-217%5E20-232-217
> 
> https://www.newegg.com/Product/Product.aspx?Item=N82E16820232221
> https://www.newegg.com/Product/Product.aspx?Item=N82E16820232184
> https://www.newegg.com/Product/Product.aspx?Item=N82E16820232209
> https://www.newegg.com/Product/Product.aspx?Item=N82E16820232217
> https://www.newegg.com/Product/Product.aspx?Item=N82E16820232205
> 
> Money isn't a huge object here, just want to know which of these are the best option to go with.


I'd go with this before those. c15 3600 tridentz or c16 3600 the 3600 binned tridentz made qvl's and ran at 3200 day 1 on more than one board. single rank Bdie is still considerably more compatible overall

https://www.newegg.com/Product/Product.aspx?Item=N82E16820232306

From your list I"d go with the c14 3200 tridentz kit. Same reasoning re b-die. oddly seems happier with tridentz vs ripjaws.


----------



## PriestOfSin

Quick question for you ram experts that doesn't deserve it's own thread.

I am almost ready to order my parts for my Ryzen build, but am at a crossroads:

Right now, there's a combo deal where I can grab a 1700+X370 Taichi+16GB G.Skill F4-3200C16D-16GTZR (Hynix A-Die), where my total will be $850.

However, I can pick up a 1700+X370 Taichi+16GB G.Skill F4-3200C14D-16GVK (Samsung B-Die), and my total will be $900.

Is it worth $50 to basically have a "sure thing" 3200MHz for my RAM? I couldn't care less about RGB LEDs.


----------



## Keith Myers

Quote:


> Originally Posted by *PriestOfSin*
> 
> Quick question for you ram experts that doesn't deserve it's own thread.
> 
> I am almost ready to order my parts for my Ryzen build, but am at a crossroads:
> 
> Right now, there's a combo deal where I can grab a 1700+X370 Taichi+16GB G.Skill F4-3200C16D-16GTZR (Hynix A-Die), where my total will be $850.
> 
> However, I can pick up a 1700+X370 Taichi+16GB G.Skill F4-3200C14D-16GVK (Samsung B-Die), and my total will be $900.
> 
> Is it worth $50 to basically have a "sure thing" 3200MHz for my RAM? I couldn't care less about RGB LEDs.


For me extra $50 is a no-brainer for a 'sure-thing'. As posted, the G.Skill F4-3600-C16D-GTZ was a 'day-one' 3200 clock for me. That was after two previous tries with Corsair Vengeance (Hynix M-die) and G. Skill (Samsung E-die) dual-rank kits that I fought for a month.


----------



## AlphaC

Marketing advisory:
Don't believe the Radeon branded memory R748G2133U2S

https://www.overclockers.ru/lab/85777_2/obzor-i-test-chetyreh-modulej-operativnoj-pamyati-ddr4-2133-amd-radeon-r7-r748g2133u2s-obemom-8-gbajt-na-platformah-intel-kaby-lake-i-amd-ryzen-agesa-1-0-0-6a.html

It's hynix...
Quote:


> Originally Posted by *translated section*
> "On the AMD platform, it takes the frequency of 2933 MHz, but, firstly, with the overestimated timings of 20-20-20, and secondly, the tests themselves are passed like normal, but the test stand is launched "once".
> 
> ...
> 
> But the fact that the modules under the AMD brand on the Intel platform are accelerating _(overclocking)_ better than on AMD's own platform - this is bad.


----------



## nexxusty

Quote:


> Originally Posted by *PriestOfSin*
> 
> Quick question for you ram experts that doesn't deserve it's own thread.
> 
> I am almost ready to order my parts for my Ryzen build, but am at a crossroads:
> 
> Right now, there's a combo deal where I can grab a 1700+X370 Taichi+16GB G.Skill F4-3200C16D-16GTZR (Hynix A-Die), where my total will be $850.
> 
> However, I can pick up a 1700+X370 Taichi+16GB G.Skill F4-3200C14D-16GVK (Samsung B-Die), and my total will be $900.
> 
> Is it worth $50 to basically have a "sure thing" 3200MHz for my RAM? I couldn't care less about RGB LEDs.


With Single Ranked B-Die (2x8gb sticks) you will be able to not only do 3200mhz, but likely you will able to run it at at LEAST C14, C13 possibly too.

It is absolutely worth the extra $50 IMO.

100%.

I have the 3600mhz C16 Ripjaws V 2x8gb kit which I verified to be B-Die before purchase and it has done me VERY well. 3466mhz C14-14-14-14-30-1T @ 1.425v all day. I am using The Stilts timings embedded into UEFI 9920, with a tad more voltage as AFAIK he uses Trident-Z which is binned "better" than the Ripjaws I wield.

The difference (for me) is 0.025v on DRAM. 1.1v on SOC.

Hynix is just a headache right now with Ryzen. I wouldn't ever recommend anything but Samsung B-Die personally. It's not THAT much more and the compatibility is just there.

*edit*

Just did a quick benchmark for you with Aida64 Extreme, haven't done one yet since I stabilized
4.0ghz/3466mhz.


Spoiler: Warning: Spoiler!







I am extremely happy with the results. You can really only get results like this with B-Die.


----------



## Ziglez

At the default 1.35 it would not pass, but at 1.36 had no issues. No overclock on cpu as i'm waiting for my bracket to use my kraken, this stock cooler hits 85 on y-cruncher without any OC.


----------



## PriestOfSin

Quote:


> Originally Posted by *Keith Myers*
> 
> For me extra $50 is a no-brainer for a 'sure-thing'. As posted, the G.Skill F4-3600-C16D-GTZ was a 'day-one' 3200 clock for me. That was after two previous tries with Corsair Vengeance (Hynix M-die) and G. Skill (Samsung E-die) dual-rank kits that I fought for a month.


Quote:


> Originally Posted by *nexxusty*
> 
> With Single Ranked B-Die (2x8gb sticks) you will be able to not only do 3200mhz, but likely you will able to run it at at LEAST C14, C13 possibly too.
> 
> It is absolutely worth the extra $50 IMO.
> 
> 100%.
> 
> I have the 3600mhz C16 Ripjaws V 2x8gb kit which I verified to be B-Die before purchase and it has done me VERY well. 3466mhz C14-14-14-14-30-1T @ 1.425v all day. I am using The Stilts timings embedded into UEFI 9920, with a tad more voltage as AFAIK he uses Trident-Z which is binned "better" than the Ripjaws I wield.
> 
> The difference (for me) is 0.025v on DRAM. 1.1v on SOC.
> 
> Hynix is just a headache right now with Ryzen. I wouldn't ever recommend anything but Samsung B-Die personally. It's not THAT much more and the compatibility is just there.
> 
> *edit*
> 
> Just did a quick benchmark for you with Aida64 Extreme, haven't done one yet since I stabilized
> 4.0ghz/3466mhz.
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 
> 
> 
> 
> I am extremely happy with the results. You can really only get results like this with B-Die.


Gotcha, I will spend the extra $50 and get B-Die memory. Normally I'd just deal with the slower stuff, but figured it was best to ask since I know Ryzen loves fast RAM.










I'll be going with a 16GB kit 3200MHz @ 14 for now (F4-3200C14D-16GVK). I'll likely ask for advice again in a few months since I want to upgrade to 32GB after the first of the year, but I know I need to keep it to two sticks.


----------



## miklkit

I'm tinkering with ram now and have a question about how to read SOC. In the cpu section it is 1.2 volts while in the motherboard section it is 1.166 volts. Which is correct?

This is in HWINFO64 with a Biostar GT7 motherboard.


----------



## Keith Myers

Quote:


> Originally Posted by *miklkit*
> 
> I'm tinkering with ram now and have a question about how to read SOC. In the cpu section it is 1.2 volts while in the motherboard section it is 1.166 volts. Which is correct?
> 
> This is in HWINFO64 with a Biostar GT7 motherboard.


In HWINFO64, you want to use the values labelled with the SVI2 TFN suffix. Those are derived directly from the telemetry provided by the Ryzen CPU. They are the most accurate. I wouldn't use the ones coming from the motherboard sensor chip.


----------



## miklkit

This Hynix ram is stable @ 2933 and I should be happy, but I tried 3200 and got a noticeable bump in performance but it isn't stable.

The SoC is at 1.2v and the dram is at 1.4v. Is there anything else that can get bumped for a bit more stability?


----------



## bluej511

Quote:


> Originally Posted by *miklkit*
> 
> This Hynix ram is stable @ 2933 and I should be happy, but I tried 3200 and got a noticeable bump in performance but it isn't stable.
> 
> The SoC is at 1.2v and the dram is at 1.4v. Is there anything else that can get bumped for a bit more stability?


Got my lpx at 3200 with tight timings but im using 1.45v for dram and 1.15 for soc, 1.0v works just fine too.


----------



## miklkit

I definitely had to bump up the SOC voltage to get it where it is now. More ram voltage is next.


----------



## bluej511

Quote:


> Originally Posted by *miklkit*
> 
> I definitely had to bump up the SOC voltage to get it where it is now. More ram voltage is next.


You may also need more vcore, believe it or not for me going from 2933 to 3200mhz i had to bump up vcore, not so much for ram stability but overall stability. Had to go from 1.2v under load with no LLC to 1.225v under load with LLC2 at 3200mhz.


----------



## miklkit

So I bumped up ram and cpu voltage and then set it to 3200.























This thing runs like my FX now and first tests say it is stable!


----------



## bluej511

Quote:


> Originally Posted by *miklkit*
> 
> So I bumped up ram and cpu voltage and then set it to 3200.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This thing runs like my FX now and first tests say it is stable!


Yea Hynix seems to need more voltage then sammy, ive run it at 1.45 for a while without any issues, same with vcore. My temps are still low so not an issue but i suspect tctl may be reporting incorrectly. It says im running at 36°C even though my water temp is 39°C so I'm guessing the asus cpu sensor with its +5°C temp difference may be close to actual temps then tctl. I may try to set my pll manually to 1.8 and see if that fixes things.


----------



## Ziglez

Quote:


> Originally Posted by *Ziglez*
> 
> At the default 1.35 it would not pass, but at 1.36 had no issues. No overclock on cpu as i'm waiting for my bracket to use my kraken, this stock cooler hits 85 on y-cruncher without any OC.


It seems like even though it passed multiple stress tests, it wasn't stable after all, ended up crashing in PUBG a few times while streaming. Tried bumping the soc to 1.2, but still nothing. Anyone have any suggestions?,


----------



## miklkit

Quote:


> Originally Posted by *miklkit*
> 
> So I bumped up ram and cpu voltage and then set it to 3200.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This thing runs like my FX now and first tests say it is stable!


Well I wuz wrong.







It kept crashing while gaming so I put it back to 2933 and the crashing stopped. Left the voltages alone though.


----------



## Clukos

Quote:


> Originally Posted by *Ziglez*
> 
> It seems like even though it passed multiple stress tests, it wasn't stable after all, ended up crashing in PUBG a few times while streaming. Tried bumping the soc to 1.2, but still nothing. Anyone have any suggestions?,


The Stilt said to lower VDDP to 0.850mv if you experience instability in games.

http://www.overclock.net/t/1624603/rog-crosshair-vi-overclocking-thread/24480#post_26247193


----------



## Ziglez

Quote:


> Originally Posted by *Clukos*
> 
> The Stilt said to lower VDDP to 0.850mv if you experience instability in games.
> 
> http://www.overclock.net/t/1624603/rog-crosshair-vi-overclocking-thread/24480#post_26247193


Well computer just crashed without any overclock, ram at default. So maybe i just got a dud chip or motherboard or Ram, i have no idea. Don't have any spare parts to test. Sadly Ryzen doesn't give much info on what's going on, it just complete black screens.

Edit: So i read the manual today while i was bored, and according to the manual i should use 1b and 2b instead of 1a and 2a DIMM slots, I don't know if that could be causing my issues, ill see how it goes now i guess.


----------



## zeroibis

Just wanted to update this thread that I have found the F4-3200C14D-32GVR to be stable on XMP settings. Here is the HCI MemTest:



More system info here: https://valid.x86.fr/anprpa


----------



## miklkit

I'm running 16gb of Hynix ram at 2940mhz and have noticed some odd behavior.

I have seen virtual memory use as high as 60%, page file use as high as 40%, but physical memory use of no more than 30%. Yes, in games I have occasionally noticed small stutters.

It seems to me that it would want to use the faster physical ram before the SSD based ram. What are the ways to make it so?


----------



## TuttleNuntler

Any ideas what the best way of getting 64gb of ram to work decently is? Is it correct to infer from the OP that asus CH6 and trident Z work together well, or are there so many CH6 simply because the bios is good?

I was considering buying F4-3000C14Q-64GTZ and a CH6.


----------



## OronDF343

[email protected] 1.0v---BIOS F6---Stressapptest---2 Hours---CMK32GX4M2B3200C16R

Board: AX370-Gaming 5
Stressapptest 2 hours on Mageia 6 (with Kernel 4.13.0-rc3)
CPU OC is not very high due to thermal restrictions (voltage is only max. 1.2v with current settings)
Memory voltage is actually set to auto (XMP on) but it reports 1.38v
This memory is 2x16GB Hynix DR so 2933 is max for now. I spent the past day tweaking the subtimings down.

EDIT: https://valid.x86.fr/jvc1i3


----------



## Silent Scone

Quote:


> Originally Posted by *OronDF343*
> 
> [email protected] 1.0v---BIOS F6---Stressapptest---2 Hours---CMK32GX4M2B3200C16R
> 
> Board: AX370-Gaming 5
> Stressapptest 2 hours on Mageia 6 (with Kernel 4.13.0-rc3)
> CPU OC is not very high due to thermal restrictions (voltage is only max. 1.2v with current settings)
> Memory voltage is actually set to auto (XMP on) but it reports 1.38v
> This memory is 2x16GB Hynix DR so 2933 is max for now. I spent the past day tweaking the subtimings down.
> 
> EDIT: https://valid.x86.fr/jvc1i3


Nice. That's a really clean result with good timings


----------



## zGunBLADEz

[email protected] a 1.375v --3333Mhz-C14-14-14-28-1T---ram 1.42v/ProcODT 60oHm---SOC 1.15v---BIOS Beta 62---Google Stressapp--


----------



## zGunBLADEz

Btw guys you need to add juice trying those ram speeds and timmings 1.37v ram is not going to cut it, this is 1.4v-1.45 range


----------



## Praz

Quote:


> Originally Posted by *zGunBLADEz*
> 
> Btw guys you need to add juice trying those ram speeds and timmings 1.37v ram is not going to cut it, this is 1.4v-1.45 range


Hello

What speeds are those?


----------



## zGunBLADEz

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> What speeds are those?


I have gskill 3600 kit for 16/16/16 @ 1.35

To have 3333 and 14/14/14 and custom timings i need to juice her up all way up to 1.42v

As we speak im testing 3466 but at 1.45v as soon i try to drop it to 1.37v for example i get a crash or if i lower it i get errors on google app


----------



## bluej511

Quote:


> Originally Posted by *zGunBLADEz*
> 
> I have gskill 3600 kit for 16/16/16 @ 1.35
> 
> To have 3333 and 14/14/14 and custom timings i need to juice her up all way uo to 1.42v
> 
> As we speak im testing 3466 but at 1.45v as soon i try to droo it to 1.37v i get a crash or if i lower it i get errors on google app


Been running 1.45v for months, heat isnt an issue as i have intake fans right above my ram (cube case so mobo sits horizontal), and to be honest an extra 100mv is nothing for ram.


----------



## zGunBLADEz

Quote:


> Originally Posted by *bluej511*
> 
> Been running 1.45v for months, heat isnt an issue as i have intake fans right above my ram (cube case so mobo sits horizontal), and to be honest an extra 100mv is nothing for ram.


True that,but they are trying to push with no voltage increase thats not how it works of course you are going to have a bunch of failures which is part of the reason.

My kit is 1.35v @ 3600 that dont mean i will get [email protected] at the same voltage

Im touching the ram while im doing the stress its not even warm lol

Stick 1



Stick 2



Put a fan of top to make sure temps are behaving with active cooling.



They surely are


----------



## Praz

Quote:


> Originally Posted by *zGunBLADEz*
> 
> I have gskill 3600 kit for 16/16/16 @ 1.35
> 
> To have 3333 and 14/14/14 and custom timings i need to juice her up all way up to 1.42v
> 
> As we speak im testing 3466 but at 1.45v as soon i try to drop it to 1.37v for example i get a crash or if i lower it i get errors on google app


Hello

The needed voltage is dependent on the memory and IMC. For stability I need 1.40V at 3600MHz/14-14-14 1T. Loose timings at 3600MHz such as 16-16-16 1T 1.35V memory voltage is sufficient.


----------



## zGunBLADEz

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> The needed voltage is dependent on the memory and IMC. For stability I need 1.40V at 3600MHz/14-14-14 1T. Loose timings at 3600MHz such as 16-16-16 1T 1.35V memory voltage is sufficient.


Yup, but for the kind of tight timings/speed they are trying to emulate like stilts/elmers/gupsberg 1.37v or stock volts are not enough.

I copied gupsterg timings all of them not only primary, into my mobo and boot it up at 3333
She didnt boot at first the procodt is MANDATORY on my mobo to boot up. If i dont play with procodt no way jose shes going no where at 3466 she likes 53.3ohm other than that no dance at 3333 she likes 60ohm


----------



## bluej511

Quote:


> Originally Posted by *zGunBLADEz*
> 
> True that,but they are trying to push with no voltage increase thats not how it works of course you are going to have a bunch of failures which is part of the reason.
> 
> My kit is 1.35v @ 3600 that dont mean i will get [email protected] at the same voltage
> 
> Im touching the ram while im doing the stress its not even warm lol
> 
> Stick 1
> 
> 
> 
> Stick 2
> 
> 
> 
> Put a fan of top to make sure temps are behaving with active cooling.
> 
> 
> 
> They surely are


Yup exactly, i went from 16-18-36 to 14-16-34 on my HYNIX ram at 3200mhz and have had zero issues, the newer BIOSes are way more finicky with subtimings unlocked so its a bit harder to make stable at all. I wish my ram had temp sensors on em would be nice to know the running temp.


----------



## zGunBLADEz

I just got a error at 1.45v my ryzen/mobo surely loves voltage lol lucky me have the cooling for it.. now testing at 1.47v


----------



## Silent Scone

Quote:


> Originally Posted by *bluej511*
> 
> the newer BIOSes are way more finicky with subtimings unlocked so its a bit harder to make stable at all. I wish my ram had temp sensors on em would be nice to know the running temp.


Most likely due to Ryzen's inability to run memory at these speeds with reasonably low subs


----------



## zGunBLADEz

To be certified on xmp highest would be 1.5v
I remember pushing those kind of volts on samsung miracle ram no problems they didnt have heatsink either. This ram is better binned and better process than those

[email protected] @ 1.375v -3466Mhz- C14-14-14-28-1T---ram 1.47v/ProcODT 53.3oHm---SOC 1.15v---BIOS Beta 62---Google Stressapp--



Quote:


> Originally Posted by *bluej511*
> 
> Yup exactly, i went from 16-18-36 to 14-16-34 on my HYNIX ram at 3200mhz and have had zero issues, the newer BIOSes are way more finicky with subtimings unlocked so its a bit harder to make stable at all. I wish my ram had temp sensors on em would be nice to know the running temp.


look at the temp on idle after the test is done.. barely nothing. comparing while stress testing it


@Silent Scone
I suggest a ProcODT request as i found this is essential for ram overclocking


----------



## gupsterg

That is a nice result IMO.

I used to use ProcODT: 53.3Ω, 60Ω has worked well as well for me. I've used 3 differing CPUs and same mobo/RAM with 60Ω (C6H/F4-3200C14D-16GTZ). Elmor recommended 53.3Ω as working well for him and The Stilt 60Ω.

I may try to tweak the setup in post 524 to get primaries lower. TBH though all benches so far have been AOK at that setup. Some beat 3333MHz Fast, others are the same and just run to run variance is tighter at 3466MHz.

What I did find as usual is what passes GSAT/HCI Memtest may need extra SOC/VDIMM for other stability tests. For example I can't run Y-Cruncher with SOC: 1.05V for 3.9 / 3466, I need 1.075V. I have currently also increased VDIMM a smidge from 1.375V to 1.385V

Below is The Stilt's presets for 3200/3333MHz Safe/Fast, 3466MHz and 3600MHz for Samsung B Die 1DPC SR kits.



There is a new RTC linked in OP of my thread that shows BankGroupSwapAlt, need to redo those screenies with that version.


----------



## zGunBLADEz

Quote:


> Originally Posted by *gupsterg*
> 
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> That is a nice result IMO.
> 
> I used to use ProcODT: 53.3Ω, 60Ω has worked well as well for me. I've used 3 differing CPUs and same mobo/RAM with 60Ω (C6H/F4-3200C14D-16GTZ). Elmor recommended 53.3Ω as working well for him and The Stilt 60Ω.
> 
> I may try to tweak the setup in post 524 to get primaries lower. TBH though all benches so far have been AOK at that setup. Some beat 3333MHz Fast, others are the same and just run to run variance is tighter at 3466MHz.
> 
> What I did find as usual is what passes GSAT/HCI Memtest may need extra SOC/VDIMM for other stability tests. For example I can't run Y-Cruncher with SOC: 1.05V for 3.9 / 3466, I need 1.075V. I have currently also increased VDIMM a smidge from 1.375V to 1.385V
> 
> Below is The Stilt's presets for 3200/3333MHz Safe/Fast, 3466MHz and 3600MHz for Samsung B Die 1DPC SR kits.
> 
> 
> 
> There is a new RTC linked in OP of my thread that shows BankGroupSwapAlt, need to redo those screenies with that version.


what i did was copy your 3333 timings all of them and did a google stress and it pass when i adjusted the ram voltage didnt have to touch cpu/soc voltage for nothing, i tried that first but it didnt work out..

I say may as well try that on 3466 same timings and i got it to pass as well for it required more voltage on ram tho but im ok with it, still within safe and ram is not running hot..

What i cant do yet is boot the darn thing at 3600 no matter what voltage/ohms and what not lol. Which i find odd and probably related to bios code/perse maybe cpu/mobo more than ram issues specially after all the tweaking i got into it and manage to accomplish on it..

i dont think that crap cant get any lower lol



what i need to do now is lowering that latency under 65 or lower while keeping those w/r/c


----------



## finalheaven

Quote:


> Originally Posted by *gupsterg*
> 
> That is a nice result IMO.
> 
> I used to use ProcODT: 53.3Ω, 60Ω has worked well as well for me. I've used 3 differing CPUs and same mobo/RAM with 60Ω (C6H/F4-3200C14D-16GTZ). Elmor recommended 53.3Ω as working well for him and The Stilt 60Ω.
> 
> I may try to tweak the setup in post 524 to get primaries lower. TBH though all benches so far have been AOK at that setup. Some beat 3333MHz Fast, others are the same and just run to run variance is tighter at 3466MHz.
> 
> What I did find as usual is what passes GSAT/HCI Memtest may need extra SOC/VDIMM for other stability tests. For example I can't run Y-Cruncher with SOC: 1.05V for 3.9 / 3466, I need 1.075V. I have currently also increased VDIMM a smidge from 1.375V to 1.385V
> 
> Below is The Stilt's presets for 3200/3333MHz Safe/Fast, 3466MHz and 3600MHz for Samsung B Die 1DPC SR kits.
> 
> 
> 
> There is a new RTC linked in OP of my thread that shows BankGroupSwapAlt, need to redo those screenies with that version.


Can you post all of Stilt's settings (picture) in your thread as well?


----------



## superstition222

Quote:


> Originally Posted by *gupsterg*
> 
> Below is The Stilt's presets for 3200/3333MHz Safe/Fast, 3466MHz and 3600MHz for Samsung B Die 1DPC SR kits.
> 
> 
> 
> There is a new RTC linked in OP of my thread that shows BankGroupSwapAlt, need to redo those screenies with that version.


I tried two browsers and the picture is too blurry for me to read, even when I click it open and download it.

Also, you may want to update your opening post because it says this:
Quote:


> HCI consider 1000% to be the 'golden standard' however for larger densities this can be time consuming. A minimal coverage of two laps (200%) is required to be added to the table for HCI for density over 16GB. 16GB or less requires a minimum of 4 laps (400%)


Golden standard seems to suggest that HCL is enough, in contrast with this:
Quote:


> What I did find as usual is what passes GSAT/HCI Memtest may need extra SOC/VDIMM for other stability tests.


That statement makes HCL seem rather pointless. Why not just run the other stability tests and skip HCL?


----------



## finalheaven

Quote:


> Originally Posted by *superstition222*
> 
> I tried two browsers and the picture is too blurry for me to read, even when I click it open and download it.


Its because the picture is a mini version of it. You have to right click and open as new tab. Or just use this: http://cdn.overclock.net/f/f7/f749b56e_The_Stilt_Presets.jpeg


----------



## superstition222

Quote:


> Originally Posted by *finalheaven*
> 
> You have to right click and open as new tab.


Thanks for the tip and the link. Maybe this site can make it more obvious how to get a high-res version.


----------



## Medusa666

I'm becoming really frustrated with the stability of my new setup.

It is a Ryzen 7 1800X, 32GB Flare X 2400MHz 15-15-15-39 memory, and an Asrock X370 ITX motherboard.

I have passed 400% in HCI memtest with 31/32GB in use, but I can't pass more than 20-60 min of OCCT, Prime 95, or Realbench without a instability error of some kind, memory related whenever there is a clear reason.

I'm also getting some very rare but totally random BSODs, IRQ not less or equal mostly.

Everything is running at stock, and XMP is enabled for the memory, I turned off C6 support and CoolNQuiet and it seems to improve things somewhat.

Any ideas are welcome.

Thanks!


----------



## gupsterg

@zGunBLADEz

You are using SOC of 1.15V, I am not.

I have used 2 CPUs at ~3500MHz C16 2T without needed that amount of SOC. 3466MHz again for those 2 is lower, 3466MHz on the 1800X as posted in post 524 is using SOC: 1.05V. Later I found Y-Cruncher for ~4hrs pass needs SOC: 1.075V. I have also done ~2hrs of RB Stress mode 16GB, ~2hrs custom x264 AVX and ~15.5hrs of [email protected] on CPU/GPU.

I tune SOC and other voltages. I really aim for no excess.

@superstition222

Th quote you have there for HCI Memtest 1000% as 'golden standard' is not my words







. I am not OP of this thread







. If you check many of my results are above 1000%, I do not even adhere to 400% as pass, the latter for me is 'quick test'.

Why do HCI?

When this thread started I would have said that as well. Quite rightly OP (Silent Scone) pointed out the benefits in this thread. I to learned from personal experience it is a worthwhile exercise.

I will present 2 examples.

i) I setup 3333MHz on my rig, at the time it was differing timings to what The Stilt Fast preset is. They were the tightest timings The Stilt had used on F4-3600C15D-16GTZ at 3466MHz 1.35V. I slackened tRAS, tRC, tFAW and tRFC a bit to gain stability on my F4-3200C14D-16GTZ and was using 1.375V. Now other tests like IBT AVX, Y-Cruncher, x264, RB were passing but HCI Memtest when ran for ~4-6hrs was showing 1-2 errors, until I slackened the timings highlighted previously.

ii) I'm in the UK, a month or so back we experienced a heatwave. Room ambient temp were at ~30-32°C again other tests were fine but HCI Memtest caught errors. So room ambient temp had affected stability. I found out that I needed to use 3200MHz tight instead of 3333MHz tight when room ambient was ~30°C+.

I go all out on stability testing with various apps, various lengths and do reruns. This way I have gained some solid profiles for the HW. I have also gained experience what will work at what sort room temps for HW I have. It has also been great to use these apps as gained experience what sorta voltage I need for say x program and how much by I will need to increase it by when run a differing stress test.

Some CPU samples have shown that once past 3200MHz they need a bump in VCORE as well as say SOC, etc, but some CPUs upto 3333MHz are fine. The current 1800X I use even for 3466MHz isn't needing a bump in VCORE.

Below is sample of my stability testing for the current CPU / profile.







Above the Y-Cruncher was run for 40min and then 4hrs as rerun, again as I said before I don't do just 1x run of anything. x264 will be rerun, but for longer than 20 loops, RB was run for ~15min prior to the 2hr run. AIDA64 I use rarely but as lately some members use it I gave it a whirl, will be doing other tests with it. That [email protected] was ran for 15.5hrs and not the 10.5 shown there, again 0 bad states on CPU/GPU and will be rerun.

If you note the time/date the rig had no downtime between those tests, it is still running now







. I also did some gaming between the stress tests. 4hrs Y-Cruncher is a walk in the park for my HW, I have done ~9hrs at times and say 30hrs+ back to back use.

The hours of usage this C6H and G.Skill RAM has seen is nuts since I got it back in Mar 17.
Quote:


> Originally Posted by *finalheaven*
> 
> Can you post all of Stilt's settings (picture) in your thread as well?


Will do mate







.


----------



## zGunBLADEz

@gupsterg

That was my first try wth the kit, im learning her still... so i know its stable at those settings, now i need to go down lol you know how it works









I know for sure the ram voltage is still at 1.47v thats for sure i already confirmed this lol


----------



## superstition222

Quote:


> Originally Posted by *gupsterg*
> 
> Th quote you have there for HCI Memtest 1000% as 'golden standard' is not my words
> 
> 
> 
> 
> 
> 
> 
> . I am not OP of this thread
> 
> 
> 
> 
> 
> 
> 
> .


Ok. I thought you were because of your comment about updating the OP.
Quote:


> Originally Posted by *gupsterg*
> 
> i) I setup 3333MHz on my rig, at the time it was differing timings to what The Stilt Fast preset is. They were the tightest timings The Stilt had used on F4-3600C15D-16GTZ at 3466MHz 1.35V. I slackened tRAS, tRC, tFAW and tRFC a bit to gain stability on my F4-3200C14D-16GTZ and was using 1.375V. Now other tests like IBT AVX, Y-Cruncher, x264, RB were passing but HCI Memtest when ran for ~4-6hrs was showing 1-2 errors, until I slackened the timings highlighted previously.
> 
> ii) I'm in the UK, a month or so back we experienced a heatwave. Room ambient temp were at ~30-32°C again other tests were fine but HCI Memtest caught errors. So room ambient temp had affected stability. I found out that I needed to use 3200MHz tight instead of 3333MHz tight when room ambient was ~30°C+.
> 
> I go all out on stability testing with various apps, various lengths and do reruns. This way I have gained some solid profiles for the HW. I have also gained experience what will work at what sort room temps for HW I have. It has also been great to use these apps as gained experience what sorta voltage I need for say x program and how much by I will need to increase it by when run a differing stress test.


I don't see what HCL offers in terms of overall efficiency, though, if it doesn't uncover the errors more strenuous tests do. It's just extra work.
Quote:


> Originally Posted by *gupsterg*
> What I did find as usual is what passes GSAT/HCI Memtest may need extra SOC/VDIMM for other stability tests.


Does this mean the other tests are finding stability issues elsewhere, not with the memory stuff?
Quote:


> Originally Posted by *gupsterg*
> Some CPU samples have shown that once past 3200MHz they need a bump in VCORE as well as say SOC, etc, but some CPUs upto 3333MHz are fine. The current 1800X I use even for 3466MHz isn't needing a bump in VCORE.


Yeah, I knew that increasing RAM speed tends to require more vcore because it makes the CPU do more work. I'm just now sure if you're saying other stress-testing apps are more strenuous in terms of uncovering memory setting instability.

Yeah, HCL doesn't stress the vcore as much as something like Prime.


----------



## gupsterg

@zGunBLADEz

No worries chap







, I'm learning too







.

@superstition222

HCI Memtest uncovered RAM errors in example (i) and (ii), please reread. As these errors where so small in count ie <10 over a 4-6 hour period the 'other tests' were not failing. For me I don't want data loss, but yeah I still wanna OC, so I aim to find best stability or back off on OC, etc.

What I'm saying is 'we' use the right tool for job.

This is how I work now when meddling with RAM.

i) I setup a profile, example say 3466MHz with The Stilt preset.

ii) I do GSAT / HCI Memtest, I know then that RAM is technically AOK. Now I know when the CPU gets loaded more ie IBT AVX, P95, Y-Cruncher, etc I will need bumps in voltages, not because RAM has an issue but as those tests are more CPU intensive and can be made to use high level of RAM we're doing a differing kind of testing.

iii) Next I will do some 'idling/low usage' case tests, as one time on a R7 1700 I have I found I did ~30hrs of back to back testing of 3.8/3200. Suddenly at idle the rig went Q-Code: 8, on C6H this is universal Q-Code stating rig destabilised. I then bumped SOC from 0.950V to 0.975V and all was well. If we monitor voltages say with a DMM we'll note some voltages shoot higher when rig under load than idle (load line effect at play), so when the rig was not at load and it was perhaps 'yoyoing' between CPU frequency (as I do a PState OC) it destabilised due to lack of voltage at low loads. Just like overshoot of voltages is something to look for undershoot also can knock an OC profile out of whack.

I also do like doing RB stress mode and [email protected], reason being as GPU is under load as well as CPU, so again a differing kind of testing than RAM tests or CPU/RAM tests highlighted before in this post. Then gaming I like to do as well. Besides looking to see if FPS is good I'm looking for smooth gameplay.

I just did earlier today ~1hr gaming, then as I wasn't gonna use the PC I did reun of Memtest.



For me currently this profile is sound. Gonna do some more gaming, then an overnight rerun of [email protected] and some P95 tomorrow







.


----------



## miklkit

Quote:


> Originally Posted by *Medusa666*
> 
> I'm becoming really frustrated with the stability of my new setup.
> 
> It is a Ryzen 7 1800X, 32GB Flare X 2400MHz 15-15-15-39 memory, and an Asrock X370 ITX motherboard.
> 
> I have passed 400% in HCI memtest with 31/32GB in use, but I can't pass more than 20-60 min of OCCT, Prime 95, or Realbench without a instability error of some kind, memory related whenever there is a clear reason.
> 
> I'm also getting some very rare but totally random BSODs, IRQ not less or equal mostly.
> 
> Everything is running at stock, and XMP is enabled for the memory, I turned off C6 support and CoolNQuiet and it seems to improve things somewhat.
> 
> Any ideas are welcome.
> 
> Thanks!


There is a chance that your problems are not memory related but are actually OS related. I was running into problems and someone suggested Latency Monitor. I found loads of problems and some of them would toss out the same IRQ message.

Try it and see what happens. http://www.resplendence.com/latencymon


----------



## zGunBLADEz

Ok guys sorry to brake it to you but 1hr of Google stressapp is not going to cut it, the same 3466 i just pass on there it went kaput not even 100% on hci. I went back to 3333 to rule out this.

Btw, i forgot to mention. the tutorial dont mention to run this WITHOUT a page file. Which with this disable you are 100% sure you are not testing the hdd/page file instead XD

Edit

Drop it down to 3333 gupsterg timings and so far 150% coverage

So im dropping googleapp for stress testing in my rig i dont trust him no more..

As i see 200% hci @ 38.25x is around 30min so 400% would be around the same as google app but more reliable


----------



## Praz

Quote:


> Originally Posted by *zGunBLADEz*
> 
> Ok guys sorry to brake it to you but 1hr of Google stressapp is not going to cut it, the same 3466 i just pass on there it went kaput not even 100% on hci. I went back to 3333 to rule out this.
> 
> Btw, i forgot to mention. the tutorial dont mention to run this WITHOUT a page file. Which with this disable you are 100% sure you are not testing the hdd/page file instead XD
> 
> Edit
> 
> Drop it down to 3333 gupsterg timings and so far 150% coverage
> 
> So im dropping googleapp for stress testing in my rig i dont trust him no more..
> 
> As i see 200% hci @ 38.25x is around 30min so 400% would be around the same as google app but more reliable


Hello

GSAT isolates and test memory only. HCI is sensitive to both memory and IMC interface instability. As I believe @gupsterg wrote earlier it's all about using the proper tools for the job at hand. Understanding the difference between these tools also help tuning a system.


----------



## zGunBLADEz

I tried cpu at stock as well. Its not him. Hci has never failed me before.


----------



## superstition222

Quote:


> Originally Posted by *gupsterg*
> 
> What I'm saying is 'we' use the right tool for job.


Of course.

The other point, though, is to find the most efficient path.

If it's possible to remove certain programs from the testing regimen and lose nothing (and gain time) then we should do that. Also, of course, finding quicker ways to demonstrate stability is worth pursuing.

The Stilt said that roughly one hour of in-place custom large FFT Prime would be enough to show stability for AMD FX. My testing indicated that it's also important to run out-of-place FFTs in basically the same size range. I had to increase the CPU-NB voltage to stabilize a clock/voltage combo that was stable for The Stilt's in-place test and which failed out-of-place. He said Vishera is cache-limited. Basically, the L2 is the determiner for overclock settings. However, the board I was using is weak, when compared with top-end boards, and seems to need more CPU-NB. The other possibility is that ASUS is overvolting the CPU-NB, underreporting the voltage being delivered. This would explain, particularly if it is a typical choice made by board makers for high-end boards, why my mileage varied. There is also the issue of higher-end boards having two phases for RAM while my board only had one.

I'd rather do one an hour of The Stilt's in-place FFTs and an hour of out-of-place than 24 hours of Prime or multiple days of Prime, which is what some overclockers have said is necessary.

As for HCL, I have found errors after many hours of it so I think it should be possible to have a more efficient stress tester than HCL. I also remember running old CD-booted Memtest on a Power Mac 6100 many eons ago which showed no memory errors and which was extremely unstable. The newest version, though, may be more stressful since it claims much improved performance. One thing I wonder about is running some cores with Prime in-place threads and some with HCL, to increase the load.

HCL, at least prior to the latest version, puts less stress on the CPU than Prime so perhaps it is possible to increase the CPU load in a memory testing program beyond the level it's at now. What would be ideal is a stress-testing program that tests all aspects of stability - within the same program. This could involve various load shifts, pauses for cooldowns, and so on. The program would automatically go through all of the different phases and shut down if temperatures go to high.

I wanted clarification because it sounded to me like you may have been saying other programs are better at testing for memory stability than HCL.


----------



## gupsterg

@zGunBLADEz

I wouldn't rule out using GSAT.

On one CPU I was testing, running GSAT highlighted issues, where as HCI Memtest didn't. I then went 'Hallelujah', why shall I bother with HCI? I don't need to open multiple instances, arrange windows to see test running. Then as highlighted before I was once tightening timings on a setup. GSAT I could pass ~9hrs plus other tests but HCI Memtest kept showing low count of errors.

I can not discount using either anymore.

Only my opinion, 3466MHz is tough to get stable with fast timings. For example on my R7 1700 recently I nailed several hours of testing and then on reruns things fell apart







. The R7 1800X is taking it well so far, last nights [email protected] below.



Again 0 CPU/GPU bad states.

@superstition222

Yes I am for efficient route of testing, but I really can't say I have found one yet. Perhaps this 'platform' is still not as developed, but has come a long way, in a reasonable period IMO.

I agree another's experience may not fit our own experience. Besides HW/FW differences, just the variance between sample HW makes experiences differ. We should just use the 'help' as a generalization to aid us. 'We' technically need to do the 'work/assessments' with our own HW samples to get the best 'we' can with our own abilities.

I just don't regard one stability program 'pass' will then mean 'we' are stable for all circumstances, again just from what I experienced with my own HW. I run my longer tests overnight when I won't be using the PC. How I see it is the time invested means I'll just be able to trust the OC profile/HW, etc. I have done this in the past and then my rigs just work for lengthy periods without need a 'retune'. My Q6600 still at times does days of [email protected] when I have spare GPUs, owned since launch. My i5 4690K rocked 4.9GHz CPU and 4.4GHz Cache 24/7 for 1yr+, I sold it to be on Ryzen.


----------



## zGunBLADEz

Im getting on hci copy errors. What errors you are getting?

Today im going to try hcl 400%
Starting with [email protected]

Just did a hci run 0 problems @ 3333 @ 1.42V SOC 1.05 no page file


Prime in place ffts dont use all ram i dont see why use this

another hci run drop ram voltage [email protected] 3333 1.37v SOC 1.05 no page file


i think the issues im encountering are more bios related than ram...

I cannot boot stock 3600 but i can boot 3466 the whole ordeal timings wise custom no problems..
===========================================
and i got it to pass HCI have to loose the timmings to 15s!!!!! oh well cant complaint








i guess hci is more sensitive to timmings than gsat

[email protected] 1.375v/ SOC 1.15v/ Vram 1.42v i will try later lower soc and vram at least now i know is stable


----------



## hsn

hsn [email protected] 1.1v---asus x370 prime pro BIOS 0805---Stressapptest 2hour-Gskill 32gb f4 3200C14-8GTZSW


----------



## Silent Scone

Quote:


> Originally Posted by *zGunBLADEz*
> 
> [email protected] a 1.375v --3333Mhz-C14-14-14-28-1T---ram 1.42v/ProcODT 60oHm---SOC 1.15v---BIOS Beta 62---Google Stressapp--


What memory kit?

Recent entries updated


----------



## zGunBLADEz

Quote:


> Originally Posted by *Silent Scone*
> 
> What memory kit?
> 
> Recent entries updated


Tridentz 3600/cl16

Also manage to pass hci @3466 see few post above higher timmings but lower latency which is good for games.

This is my 1800x @ 4ghz with 3466


Have 2 threads giving me mem errors (bottom ones) raised the ram volt one notch while the others keep chugging ram away








Restarted the 2 threads on the fly without restarting reallocate the remaining ram and walla no problems after that.

Been playing with hci for too long XD


----------



## MynRich

So in bios 1501, CAD Bus options all set to 30Ohms lets 3600 preset 16-16-16-36 into Windows (but isn't MemTest stable) but not 3466 preset 14-14-14-34. Any preliminary advice on which CAD bus option to raise / lower? My RAM is single rank 1dpc B-Die. Team Group T-Force Xtreem 4133mhz 18-18-18-18-38 1.4v rating.
Currently trying GDME with both straps.


----------



## MynRich

Quote:


> Originally Posted by *MynRich*
> 
> So in bios 1501, CAD Bus options all set to 30Ohms lets 3600 preset 16-16-16-36 into Windows (but isn't MemTest stable) but not 3466 preset 14-14-14-34. Any preliminary advice on which CAD bus option to raise / lower? My RAM is single rank 1dpc B-Die. Team Group T-Force Xtreem 4133mhz 18-18-18-18-38 1.4v rating.
> Currently trying GDME with both straps.


Helped with 3600 strap when also raising DRAM voltage to 1.415v
Oddly, trying to help SOC voltage by switching from manual 1.15v to auto wouldn't post...
Would raising the dram boot voltage to match dram voltage help? I thought I saw an AMD rep say that having boot voltage slightly below dram voltage helps... (boot voltage 1.4v while dram 1.415


----------



## zGunBLADEz

Did another set of timings drops thanks to @Clukos


----------



## Dr. Vodka

Hi! Just upgraded from a 4.5GHz 2500k after six years, now using a C6H on BIOS 1403, R7 1700 + TRUE Spirit 140 power, gskill F4-3466C16D-16GTZ (3466 16-18-18-38-2T 1.35v, B-die). I got this kit because there wasn't any 3200C14 B-die stuff available and I wanted to avoid other memory types as to have smooth sailing on Ryzen. CPU is fine, it can do 3.9GHz 1.33v so far, but I need to stress test that a little more. On the memory side, for the time being I'm setting primary timings and the rest on auto, see what this kit can reliably do, then proceed to tightening the subtimings and command rate. Thaiphoon burner reports of both DIMMs here and here. I'm using slots A2 and B2, if I read the manual correctly those are the first to use in this case.

This kit is rated for (16/1733)*1000 = 9.23ns operation, that is my baseline. 3466C16 is too loose IMO, so I'd like to tighten that up seeing that 3200 is more than plenty to maximize Ryzen's performance. For these tests I'm leaving the CPU at default settings and using 1.1v vSOC, 1.375 vDIMM which are around 1.09v and 1.41v according to hwinfo. The following memtest runs are done with pagefile disabled, leaving around 400MB free for Windows:

3333 15-15-15-35-2T is stable, this is (15/1666)*1000= 9ns



3200 14-14-14-34-2T is (14/1600)*1000 = 8.75ns, I guess this is pushing it:



Oh come on! Error at near 700% and the rest of the memory went on to beyond 2200%, lol.

I tested The Stilt's B-die timings (3200 @ safe 3333 14-14-14-30 + subtimings, 1T no geardown, 1.1vSOC 1.4vDIMM) and I got similar behavior, testing overnight one instance would fail at an early % (how early depends on how aggressive the timings were, how much vSOC/vDIMM, etc) and the rest would go well into 500-1000% where I would just stop the test and go back to the drawing board.

Any ideas as to what is going on here? Is there anything that you'd change to completely stabilize auto 3200 on this kit then move on to subtimings or did I get a dud kit? More voltage beyond 1.4v? ProcODT? (60 ohms seems to do fine) That single instance failing... a weak memory chip in one of the sticks? Do I give up on C14 for this kit and try 3200 15-14-14-34?

Edit: well, stopped being a chicken and set 1.4v at the BIOS, loaded up 3333 safe timings and relaxed tWR from 12 to 24 (Read somewhere here or at the C6H thread that it was too tight for some kits) and...



no more early (0-200%) single instance error. Oh well, just needed some more voltage I guess, I'll now go for 1T+Geardown and if that's stable then pure 1T and consider it tweaked for further stress testing. I did say I was new to the platform and was getting a feeling for it









Edit2: 3200 C14 1T threw an error at some point... didn't bother trying geardown mode here. What if I decided to stay at 3466 C16 and tightened everything else?

Well, it seems it likes it better this way:





I couldn't stabilize pure 1T so I enabled geardown. Similar benchmark scores to 3200C14 and tight subtimings, with more bandwidth and higher CCX/IF connection speed to boot. I'll take it. I'll see now what happens with BGSA enabled, if that doesn't impact stability it stays on.

Lowered VDDP to 0.9v, too.


----------



## miklkit

Ok so I'm tinkering with ram timings now and am wondering about Trc. It has defaulted to 69 and it seems others are going much lower. What does it do and does it help? I am a noob at ram timings.









So far what I have is stable in IBT AVX and Y-Cruncher but I want to get it better before going for the long test required to get on your chart.


----------



## maxrealliti

G.Skill Trident Z 32GB DDR4 32GTZSW K4 3200 C16
Hi clue as to turn right on a steady job. With the acceleration does not start from the first tee it always drops to 2133 and normal. The motherboard ASUS cross 6 Bios 1501 processors of 1800x


----------



## Silent Scone

Quote:


> Originally Posted by *miklkit*
> 
> Ok so I'm tinkering with ram timings now and am wondering about Trc. It has defaulted to 69 and it seems others are going much lower. What does it do and does it help? I am a noob at ram timings.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> So far what I have is stable in IBT AVX and Y-Cruncher but I want to get it better before going for the long test required to get on your chart.


TRC needs to be no less than the sum of tRAS and tRP. Too low a value can result in training failure, so best to soak test the system as well as test stability with the methods listed in the op


----------



## miklkit

Thanks for that info. So it needs to stay above 52 in this system. What would lowering it from 69 do? I'm guessing it helps, but is it worth the bother?


----------



## miklkit

So I think it's about as good as I can get it.

It is a Ryzen 1700

Biostar GT7 with 623 bios

G. Skill Ripjaws DDR4 PC25600 4096 X 4 F4-3200C16Q-16GVKB

1.312 vcore

1.112 SOC


----------



## Silent Scone

Quote:


> Originally Posted by *miklkit*
> 
> Thanks for that info. So it needs to stay above 52 in this system. What would lowering it from 69 do? I'm guessing it helps, but is it worth the bother?


It has a similar effect on performance as lowering tRAS, that being not greatly. If you're struggling with stability, I'd leave this value in auto. Although I see you've managed 400% coverage above.


----------



## miklkit

It has no stability issues that I can tell at this speed, but at 3200 it is hopeless probably because of the 4 sticks.


----------



## Sev501

Hi all

[email protected] 1.15v---BIOS F4 (GB Gaming K7)---Stressapptest---1 Hour---F43200C16-8GTZSK



EDIT: Haven't touched any of the advanced ram options, just manually dialed in the timings. The sub timings and other advanced ones are still from bios auto.


----------



## 010101

Hi guys any whit a hynix 32gb dual rank kit working in a taichi? i cant reach 2933 stable.... just 2800mhz is stable... 2933 boots but unstable in win, Pass all memory tests but randomdly blue screens. In 2800mhz work rock solid.
,
i have this kit

https://gskill.com/en/product/f4-3200c16d-32gtzsw

typon:

aida:

rtc 2933 xmp


I try soc 1.15 dram 1.39 geardown enable disable t1 t2 any ideas? Or someone with a similar kit

I have a taichi bios 3.0 and a r7 1700x stock.


----------



## Dr. Vodka

Hm.

This passed 1100% HCI, and failed while decompressing /installing something (installer returned CRC error). Reverted memory to safe 2133 and it unpacked just fine, downloaded file checks OK.



Goddamnit. Need to stress test more.


----------



## zGunBLADEz

[email protected] a 1.384v --3466Mhz LL-C14-15-15-28-1T---ram 1.44v---SOC 1.15v---BIOS Beta 63---Google Stressapp--


----------



## Silent Scone

Quote:


> Originally Posted by *Dr. Vodka*
> 
> Hm.
> 
> This passed 1100% HCI, and failed while decompressing /installing something (installer returned CRC error). Reverted memory to safe 2133 and it unpacked just fine, downloaded file checks OK.
> 
> 
> 
> Goddamnit. Need to stress test more.


Be sure to check disk integrity also before pressing on with testing the memory again.

Quote:


> Originally Posted by *zGunBLADEz*
> 
> [email protected] a 1.384v --3466Mhz LL-C14-15-15-28-1T---ram 1.44v---SOC 1.15v---BIOS Beta 63---Google Stressapp--


Nice result, thanks for share







- please specify the memory kit


----------



## Robenger

Quote:


> Originally Posted by *zGunBLADEz*
> 
> [email protected] a 1.384v --3466Mhz LL-C14-15-15-28-1T---ram 1.44v---SOC 1.15v---BIOS Beta 63---Google Stressapp--


How are you running memory that fast on a B350 mobo?


----------



## RossiOCUK

I want to get 32GB running, is 3200MHz CL12 feasible? (4x8GB 4000MHz Samsung B-Die)

Would it be easier to obtain (if at all) with 2x16GB DR or 4x8GB SR?


----------



## Silent Scone

Quote:


> Originally Posted by *RossiOCUK*
> 
> I want to get 32GB running, is 3200MHz CL12 feasible? (4x8GB 4000MHz Samsung B-Die)
> 
> Would it be easier to obtain (if at all) with 2x16GB DR or 4x8GB SR?


Hi, CAS12 regardless of the high bin will likely need 1.5v or in excess of. This goes for both - however, you will have an easier time with the 8GB modules.


----------



## RossiOCUK

Quote:


> Originally Posted by *Silent Scone*
> 
> Hi, CAS12 regardless of the high bin will likely need 1.5v or in excess of. This goes for both - however, you will have an easier time with the 8GB modules.


Happy to go over 1.5v, might give it a whack









Figured as much with the 8GB DIMMS, which is why they're already on order.


----------



## gupsterg

The Stilt used greater than or equal to 1.45V for C12 tight, he also had Geardown on, on F4-3600C15D-16GTZ. OP of my thread Is RAM MHz king? has info.


----------



## zGunBLADEz

Quote:


> Originally Posted by *Robenger*
> 
> How are you running memory that fast on a B350 mobo?


you think thats fast?

look at the whole ram table thing










@gupsterg
thats what im working on right now with those ram timings. drop it down to 39.50x did 2 hrs on Y-Cruncher decide is time for a prime blend

40x seems impossible to have stable for this 1800X/MoBo combo with those rams tweaks, maybe 3200 can do it.. But the faster the ram the more stability in question.
But you know we have people calling this setups stable without proper testings..

yeah they are very bencheable at everything even @ 41x but its not something i call 100% stable, i can get away with it casual gaming and regular computer use they are RB/x264/gsat/hci stable etc. Something that i call stable 100% no.. Specially knowing and what apps to use and specially where to hit it lol.

See according to my testings

here
http://www.overclock.net/t/1624139/official-ryzen-7-1800x-1700x-1700-owners-club-4ghz-club/16190#post_26279104
Quote:


> So sum it up, i didnt notice no difference in this particular game on 3200 16CL vs 14CL
> 
> 4.1GHz
> 
> 2133 to 3200 19%+
> 2133 to 3466LL 14/15/15/15/28 51%+
> 3200 to 3466LL 27%+
> 
> 3.8GHz
> 
> 2133 to 3466LL 14/15/15/15/28 41%+
> 
> 3.8GHz vs 4.1GHz with 3466 LL its only a 8%+


If i have to loose a multiplier i will i get more gains out of ram tweaks than mhz


----------



## Worldwin

How did you guys "Terminal?" I installed bash but i can't find out how/where to open "Terminal."


----------



## zGunBLADEz

Quote:


> Originally Posted by *Worldwin*
> 
> How did you guys "Terminal?" I installed bash but i can't find out how/where to open "Terminal."


C:\Windows\System32\bash.exe


----------



## Worldwin

Quote:


> Originally Posted by *zGunBLADEz*
> 
> C:\Windows\System32\bash.exe


So when i type in "stressapptest -W -s 3600" I get the following:
Log: Commandline - stressapptest -W -s 3600
Stats: SAT revision 1.0.6_autoconf, 64 bit binary
Log: buildd @ kapok on Wed Jan 21 17:09:35 UTC 2015 from open source release
Log: 1 nodes, 16 cpus.
Log: Defaulting to 16 copy threads
Log: Total 16332 MB. Free 13233 MB. Hugepages 0 MB. Targeting 15323 MB (93%)
Log: Prefer plain malloc memory allocation.
Process Error: memalign returned 0
Process Error: failed to allocate memory
Process Error: Sat::Initialize() failed

Status: FAIL - test encountered procedural errors

Process Error: Fatal issue encountered. See above logs for details.

I have no idea whats going wrong. Seems like I'm missing something.


----------



## zGunBLADEz

try

stressapptest -W -s 3600 -M 14000
or
stressapptest -W -s 3600 -M 13000

if you have 16gb

it depends how much memory your os have already allocated

go by this line when it error like that
Log: Total 16332 MB. *Free 13233*

so you would need to

stressapptest -W -s 3600 -M 13000


----------



## Worldwin

Quote:


> Originally Posted by *zGunBLADEz*
> 
> try
> 
> stressapptest -W -s 3600 -M 14000
> or
> stressapptest -W -s 3600 -M 13000
> 
> if you have 16gb
> 
> it depends how much memory your os have already allocated
> 
> go by this line when it error like that
> Log: Total 16332 MB. *Free 13233*
> 
> so you would need to
> 
> stressapptest -W -s 3600 -M 13000


Alright thanks. 13000 works. Wish the instruction was more clear for people like me who never used linux distro.


----------



## Silent Scone

Quote:


> Originally Posted by *Worldwin*
> 
> Alright thanks. 13000 works. Wish the instruction was more clear for people like me who never used linux distro.


By allocating 13000 you're not testing enough of the memory. The instructions are clear enough, it's simply that the RAM GSAT is trying to allocate isn't available.

This is why it's recommended to actually install Mint rather than use BASH.


----------



## zGunBLADEz

Quote:


> Originally Posted by *Silent Scone*
> 
> By allocating 13000 you're not testing enough of the memory. The instructions are clear enough, it's simply that the RAM GSAT is trying to allocate isn't available.
> 
> This is why it's recommended to actually install Mint rather than use BASH.


you are not saying that plus you also have to understand every system is different.

Its like me saying every test run here so far with page file on is not valid ...








When stress testing a system first thing you need to do is turn off the page file and do tests in a clean boot. That dont guaranteed you you are going to have a benching/os free resources.
XD


----------



## Silent Scone

Quote:


> Originally Posted by *zGunBLADEz*
> 
> you are not saying that plus you also have to understand every system is different.
> 
> Its like me saying every test run here so far with page file on is not valid ...
> 
> 
> 
> 
> 
> 
> 
> 
> 
> XD


I'm saying it now, I can say it twice if you'd like? Given the difficulties users faced with X370, expecting them to install Mint was a stretch, so I introduced the option of using BASH.

You'd need to elaborate on why you think it's the same as running the test with page file enabled. Depends if you've been allocating memory correctly when testing.


----------



## Silent Scone

Your edit is still not relevant. If you're testing memory, you want to be allocating more than 80% as is instructed in the OP. If you don't feel that's right, feel free to start your own memory thread where the actual testing of memory doesn't take place


----------



## zGunBLADEz

you need to allocate as much as possible i do agreed the problem is you dont know if windows is throwing some into the page file <===

If you turn off page file you have more control over this..

this is my hci run with no page file on windows 7
https://d1rktuf34l9h2g.cloudfront.net/2/26/263805b9_3466tightestyetsofar.jpeg

Look how much memory i have free


----------



## Silent Scone

Quote:


> Originally Posted by *zGunBLADEz*
> 
> you need to allocate as much as possible i do agreed the problem is you dont know if windows is throwing some into the page file <===
> 
> If you turn off page file you have more control over this..


It's not difficult, assuming you're not using the machine (which you should not be) whilst the test is running, allocate 90% of what is available, which gives the OS room to breathe. There's no need to disable page file if done correctly.

The problem is allocating 13000 is not a thorough test. As is indicative by the fact GSAT is automatically trying to allocate more. Simple really.


----------



## zGunBLADEz

Quote:


> Originally Posted by *Silent Scone*
> 
> It's not difficult, assuming you're not using the machine (which you should not be) whilst the test is running, allocate 90% of what is available, which gives the OS room to breathe. There's no need to disable page file if done correctly.
> 
> The problem is allocating 13000 is not a thorough test. As is indicative by the fact GSAT is automatically trying to allocate more. Simple really.


Thats the problem your command is not going to work for everybody as you see right now.

is either you get rid of the page file, do an outside test no os running.. Or you have to deal with the memory allocation


----------



## Silent Scone

Quote:


> Originally Posted by *zGunBLADEz*
> 
> Thats the problem your command is not going to work for everybody as you see right now.
> 
> is either you get rid of the page file, do an outside test no os running.. Or you have to deal with the memory allocation


Or you stop over thinking it, install Mint as suggested and allocate a more suitable amount to the test.

As already said, it's not difficult, but allocating less memory to the test is not the answer. Nothing else need some to be said on the matter. If you want to do things half baked, that's obviously your decision.


----------



## zGunBLADEz

Quote:


> Originally Posted by *Silent Scone*
> 
> Or you stop over thinking it, install Mint as suggested and allocate a more suitable amount to the test.
> 
> As already said, it's not difficult, but allocating less memory to the test is not the answer. Nothing else need some to be said on the matter. If you want to do things half baked, that's obviously your decision.


but thats not the case tho i purposely *turned the page file off to make sure im not testing the page file* that defeats the purpose of testing the ram to begin with right?

Both hci and sat tests i have done and share here are page file free/off pc have barely no ram for herself left...

The problems is if you dont tell the gsat what memory to allocate is going to error out you can empty the ram, but you cant take the os ram usage out you can lower it, but theres so much you can do.

The problem is gsat eventually is going to error out everytime if he dont get the automatic 93% of the TOTAL ram amount.,. Like the user above.. He would need to close everything i mean EVERYTHING and try if that doesnt work he would need to allocate manually the ram

Plus if we see

HCI recommended by post as suggested
Quote:


> 16 instances with 850MB per instance.


that equals to *13,600mb* ram

I have instances of hci running 880 each in my settings with no page file

this is gsat on my pc


Spoiler: Warning: Spoiler!



Quote:


> [email protected]:~# stressapptest -W -s 3600
> Log: Commandline - stressapptest -W -s 3600
> Stats: SAT revision 1.0.6_autoconf, 64 bit binary
> Log: buildd @ kapok on Wed Jan 21 17:09:35 UTC 2015 from open source release
> Log: 1 nodes, 16 cpus.
> Log: Defaulting to 16 copy threads
> Log: Total 16336 MB. Free 13202 MB. Hugepages 0 MB. Targeting 15327 MB (93%)
> Log: Prefer plain malloc memory allocation.
> Process Error: memalign returned 0
> Process Error: failed to allocate memory
> Process Error: Sat::Initialize() failed
> 
> Status: FAIL - test encountered procedural errors
> 
> Process Error: Fatal issue encountered. See above logs for details.
> [email protected]:~#






Dont matter what hes trying to allocate that 93% ram same as the other user

My windows 10 is bare minimum as it is XD

i can try

stressapptest -W -s 3600 -M 14000

or the same settings as hci

stressapptest -W -s 3600 -M 13600

i try 14000 first theres no way i will have 7% ram usage on a clean boot

closed chrome memory hogger and still ..


Spoiler: Warning: Spoiler!



Quote:


> [email protected]:~# stressapptest -W -s 3600
> Log: Commandline - stressapptest -W -s 3600
> Stats: SAT revision 1.0.6_autoconf, 64 bit binary
> Log: buildd @ kapok on Wed Jan 21 17:09:35 UTC 2015 from open source release
> Log: 1 nodes, 16 cpus.
> Log: Defaulting to 16 copy threads
> Log: Total 16336 MB. Free 14743 MB. Hugepages 0 MB. Targeting 15327 MB (93%)
> Log: Prefer plain malloc memory allocation.
> Process Error: memalign returned 0
> Process Error: failed to allocate memory
> Process Error: Sat::Initialize() failed
> 
> Status: FAIL - test encountered procedural errors
> 
> Process Error: Fatal issue encountered. See above logs for details.






usually -m 14000 do the trick XD


----------



## ste1986

Hi all

I'm a regular at OCUK but love this thread and thought I'd join and ask for some advice.

I have the following stable at 4000% HCI. Never had a cold boot issue or unexplained lock ups -

Gigabyte x370 gaming 5
Ryzen 1700
G skills 2x8gb 3600c17 b die kit

Runs 3.9 at 3333c14-14-14-14-38-54 with tRFC at 333, 1T, GD disabled. ProcODT 60.

I am trying to get 3466 working. Exact same settings as above with RAM voltage at 1.45 and SOC 1.175. When I get into windows ok I have got to 1000% HCI.

However I get F9 memory training errors on cold boot. Sometimes one or two but sometimes three which results Ina reset to default.

Are there any things I should try to sort this out? It feels so close... the F9 codes on cold boot only are so annoying. Am I being too optimistic on timings? Or will some careful sub timings or CLDO VDDP tweaks get me there?

Thanks for any help!

PS once it works I will drop SOC but wanted to rule it out as a potential culprit!


----------



## Silent Scone

Quote:


> Originally Posted by *zGunBLADEz*
> 
> but thats not the case tho i purposely *turned the page file off to make sure im not testing the page file* that defeats the purpose of testing the ram to begin with right?
> 
> Both hci and sat tests i have done and share here are page file free/off pc have barely no ram for herself left...
> 
> The problems is if you dont tell the gsat what memory to allocate is going to error out you can empty the ram, but you cant take the os ram usage out you can lower it, but theres so much you can do.
> 
> The problem is gsat eventually is going to error out everytime if he dont get the automatic 93% of the TOTAL ram amount.,. Like the user above.. He would need to close everything i mean EVERYTHING and try if that doesnt work he would need to allocate manually the ram
> 
> Plus if we see
> 
> HCI recommended by post as suggested
> that equals to *13,600mb* ram
> 
> I have instances of hci running 880 each in my settings with no page file
> 
> this is gsat on my pc
> 
> Dont matter what hes trying to allocate that 93% ram same as the other user
> 
> My windows 10 is bare minimum as it is XD
> 
> i can try
> 
> stressapptest -W -s 3600 -M 14000
> 
> or the same settings as hci
> 
> stressapptest -W -s 3600 -M 13600
> 
> i try 14000 first theres no way i will have 7% ram usage on a clean boot
> 
> closed chrome memory hogger and still ..
> 
> usually -m 14000 do the trick XD


I'm not sure how many times I can say the same thing. This is why've it's recommended to run in Mint. You seem to be struggling with this concept.


----------



## zGunBLADEz

It applies the same to hci tho so what would be then linux only test?


----------



## Silent Scone

Quote:


> Originally Posted by *zGunBLADEz*
> 
> It applies the same to hci tho so what would be then linux only test?


Are you trying to say the same concept applies to HCI for Windows? Yes it does, which is one reason why GSAT is better. One more time - when run from Mint.


----------



## zGunBLADEz

Then guys dont bother no more is useless if is not run from linux Chau XD


----------



## Dr. Vodka

Turns out my TridentZ 3466 16-18-18-38 kit is probably based on a TridentZ 3200 15-15-15-35 kit. (It seems like a natural progression for these speeds and timings at 1.35v). Clearly worse quality than 3200C14 1.35v kits. Why not try 3200 14-14-14-28 1T (Stilt safe timings) and see how much voltage it actually needs?

This is 6 hours of SAT



C6H BIOS 1403
vDIMM 1.44v set in BIOS, vDIMM at boot 1.44v too
vSOC 1.1v
ProcODT 60 ohms
vDPP 0.9v
CAD lines stock
CLDO_VDPP stock

1.425v did 6 hours of SAT overnight with two errors. 1.44v passed the test without problems. Under load the memory temperature sensor doesn't read more than 35-36°C at ~20°C ambient temperature. Measuring vDIMM at the probe it points reads 1.46v at 1.44v BIOS.

I've been looking around and it seems B-die can run these kind of voltages for 24/7 use without problem, there's lots of airflow around to keep the memory cool, too. Would you keep this configuration for 24/7 or do I drop down to 1.4v and stay there? Buildzoid says 1.5v daily is fine... Samsung's B-die datasheet states 1.5v is the absolute maximum you'd like to feed these chips (disregarding extreme overclocking, of course). I suppose it's alright.

I could try 3466 15-15-15-35 1T at the same 1.44v with looser subtimings, see if its stable.


----------



## gupsterg

Does seem high VDIMM requirement, compared to others results.

I have F4-3200C14D-16GTZ, VBOOT/VDIMM in UEFI for 3200MHz is 1.35V, 3333MHz 1.375V, 3466MHz 1.385V.

The voltage stated depending on:-

i) CPU/UEFI used.
ii) Testing method.
iii) How well I fine tuned profile.

May need an increase +0.05V to +0.15V for 3333MHz and onwards, but 3200MHz seems to always be fine at 1.35V.


----------



## bluej511

Quote:


> Originally Posted by *gupsterg*
> 
> Does seem high VDIMM requirement, compared to others results.
> 
> I have F4-3200C14D-16GTZ, VBOOT/VDIMM in UEFI for 3200MHz is 1.35V, 3333MHz 1.375V, 3466MHz 1.385V.
> 
> The voltage stated depending on:-
> 
> i) CPU/UEFI used.
> ii) Testing method.
> iii) How well I fine tuned profile.
> 
> May need an increase +0.05V to +0.15V for 3333MHz and onwards, but 3200MHz seems to always be fine at 1.35V.


Ive been running 1.45 for a couple months now and haven't had any issues. Id say 1.45 is plenty safe provided you have good case cooling.


----------



## gupsterg

Not saying it's unsafe







.

My post was in the context of Samsung B Die voltage I have used and most other results don't need 1.45V for 3200MHz on B Die







. Which you are not using







.


----------



## Dr. Vodka

Quote:


> Originally Posted by *gupsterg*
> 
> Does seem high VDIMM requirement, compared to others results.
> 
> I have F4-3200C14D-16GTZ, VBOOT/VDIMM in UEFI for 3200MHz is 1.35V, 3333MHz 1.375V, 3466MHz 1.385V.
> 
> The voltage stated depending on:-
> 
> i) CPU/UEFI used.
> ii) Testing method.
> iii) How well I fine tuned profile.
> 
> May need an increase +0.05V to +0.15V for 3333MHz and onwards, but 3200MHz seems to always be fine at 1.35V.


Yeah, but yours is higher grade memory. Mine doesn't do 3200C14 at 1.35v with auto subtimings, it errors almost instantly.

If yours were to be factory overclocked like mine it'd be probably turned into a 3466C15 or 3600C16 kit.

Damn good memory you've got there.

Maybe I should just aceept I got crap B-die and be happy I can do 3200-3466 at semi decent timings and 1.4v


----------



## bluej511

Quote:


> Originally Posted by *gupsterg*
> 
> Not saying it's unsafe
> 
> 
> 
> 
> 
> 
> 
> .
> 
> My post was in the context of Samsung B Die voltage I have used and most other results don't need 1.45V for 3200MHz on B Die
> 
> 
> 
> 
> 
> 
> 
> . Which you are not using
> 
> 
> 
> 
> 
> 
> 
> .


Yea exactly, for CL14 Hynix needs a good kick in the behind with 1.45v, been stable with no WHEAs, im still on 1107 though.


----------



## gupsterg

Quote:


> Originally Posted by *Dr. Vodka*
> 
> Yeah, but yours is higher grade memory. Mine doesn't do 3200C14 at 1.35v with auto subtimings, it errors almost instantly.
> 
> If yours were to be factory overclocked like mine it'd be probably turned into a 3466C15 or 3600C16 kit.
> 
> Damn good memory you've got there.
> 
> Maybe I should just aceept I got crap B-die and be happy I can do 3200-3466 at semi decent timings and 1.4v


I guess I did AOK with the kit, some others have better results even than me on same kit







, so the grass can always be greener elsewhere







.

Yes 3466 C15 1T tight setup these will do at voltage mentioned. Using GearDown might aid you with higher clocks, for example a member Clukos (differing kit IIRC) has 3466MHz with real tight setup but with GD on and that benches better than 3466MHz C15 1T without GD.
Quote:


> Originally Posted by *bluej511*
> 
> Yea exactly, for CL14 Hynix needs a good kick in the behind with 1.45v, been stable with no WHEAs, im still on 1107 though.


NP







.


----------



## chroniclard

Chroniclard -- [email protected] 1.0v---BIOS 9920---HCI---600%---TDPGD416G3200HC14ADC01 (Team Group Dark Pro "8 Pack Edition" 16GB (2x8GB) DDR4)


----------



## ste1986

Quote:


> Originally Posted by *gupsterg*
> 
> I guess I did AOK with the kit, some others have better results even than me on same kit
> 
> 
> 
> 
> 
> 
> 
> , so the grass can always be greener elsewhere
> 
> 
> 
> 
> 
> 
> 
> .
> 
> Yes 3466 C15 1T tight setup these will do at voltage mentioned. Using GearDown might aid you with higher clocks, for example a member Clukos (differing kit IIRC) has 3466MHz with real tight setup but with GD on and that benches better than 3466MHz C15 1T without GD.
> NP
> 
> 
> 
> 
> 
> 
> 
> .


I think the 3600c17 kit is also the poorer g Skill bin.

3200/14 and 3600/16 are probably the same? Not sure about 3600/15 which may be the top bin?

Any idea RE training failure per post 641? Tearing my hair out


----------



## Silent Scone

Quote:


> Originally Posted by *bluej511*
> 
> Ive been running 1.45 for a couple months now and haven't had any issues. Id say 1.45 is plenty safe provided you have good case cooling.


Some of these imposed limits were put in place when DDR4 launched, as a considerable time has since then it can be seen that the IC themselves are fairly resilient to high voltage. IMO anymore than 1.5v for 24/7 is poor tuning, though.


----------



## TheScarecow

So when you look at DDR4 kits like the following

3600MHz
Tested Latency 16-16-16-36
https://www.gskill.com/en/product/f4-3600c16q-32gtzr

vs
4266MHz
Tested Latency 19-19-19-39
https://www.gskill.com/en/product/f4-4266c19d-16gtzr

can you down clock the 4266mhz kit to 3600mhz and get tighter timings then the 3600 kit?

and would we see much of a performance increase being able to run ryzen at greater then 3600mhz ram?

and also can you use 2 kits of dual channel kits in a quad channel mobo with no issues?


----------



## Silent Scone

Quote:


> Originally Posted by *TheScarecow*
> 
> So when you look at DDR4 kits like the following
> 
> 3600MHz
> Tested Latency 16-16-16-36
> https://www.gskill.com/en/product/f4-3600c16q-32gtzr
> 
> vs
> 4266MHz
> Tested Latency 19-19-19-39
> https://www.gskill.com/en/product/f4-4266c19d-16gtzr
> 
> can you down clock the 4266mhz kit to 3600mhz and get tighter timings then the 3600 kit?
> 
> and would we see much of a performance increase being able to run ryzen at greater then 3600mhz ram?
> 
> and also can you use 2 kits of dual channel kits in a quad channel mobo with no issues?


Are you using these with Thread Ripper?

1) Yes, you potentially can, but there needs to be realistic expectations going in. For instance even 3600 may be out of reach for some users depending on the board and CPU on the platform in question. 3200 seems to be the sweet spot with Zen. It's always best to look for kits that have been validated for the platform you're using.

2) My consensus on mixing memory kits is that if you're having to ask, then it's not something you should consider. More so with the high frequency you're looking to achieve. Expect to make concessions to timings and frequency, or depending on your ability to tune the platform that it may not work even close to the frequency you're hoping for.

3) To my knowledge, although there are some mild improvements to memory performance over X370, greater than 3600 is not possible on the platform, or at least is outside the scope of what one can expect to achieve at a fully operational level.


----------



## TheScarecow

Quote:


> Originally Posted by *Silent Scone*
> 
> Are you using these with Thread Ripper?
> 
> 1) Yes, you potentially can, but there needs to be realistic expectations going in. For instance even 3600 may be out of reach for some users depending on the board and CPU on the platform in question. 3200 seems to be the sweet spot with Zen. It's always best to look for kits that have been validated for the platform you're using.
> 
> 2) My consensus on mixing memory kits is that if you're having to ask, then it's not something you should consider. More so with the high frequency you're looking to achieve. Expect to make concessions to timings and frequency, or depending on your ability to tune the platform that it may not work even close to the frequency you're hoping for.
> 
> 3) To my knowledge, although there are some mild improvements to memory performance over X370, greater than 3600 is not possible on the platform, or at least is outside the scope of what one can expect to achieve at a fully operational level.


I am planning on using them for Threadripper on a Zenith board

1) I am well aware of nothing being promised but as the asus site lists DDR4 3600(O.C.)/3200(O.C.)/2800(O.C.)/2666/2400/2133 MHz I am of the wishful thinking that just like how the crossfire lists DDR4 3200(O.C.)/2666/2400/2133 MHz and people are sometimes getting past that and hitting 3600mhz that maybe Threadripper will do the same past 3600mhz

2) its a question I cant get a clear answer to so i dont see the harm in asking

3) Threadripper hasnt even been out for a week now so bit early to say what the limit really is, besides all the reveiws seem to point to at least 3200mhz being plug and play

I'd still like to know if a 4000mhz kit will be fine to run at lower Mhz with tighter timings, is higher binned ram "better over all" then a 3200 or a 3600 kit?


----------



## Silent Scone

Purchasing a higher bin will likely give you better results when tuning manually, yes.


----------



## MynRich

Quote:


> Originally Posted by *TheScarecow*
> 
> I am planning on using them for Threadripper on a Zenith board
> 
> 1) I am well aware of nothing being promised but as the asus site lists DDR4 3600(O.C.)/3200(O.C.)/2800(O.C.)/2666/2400/2133 MHz I am of the wishful thinking that just like how the crossfire lists DDR4 3200(O.C.)/2666/2400/2133 MHz and people are sometimes getting past that and hitting 3600mhz that maybe Threadripper will do the same past 3600mhz
> 
> 2) its a question I cant get a clear answer to so i dont see the harm in asking
> 
> 3) Threadripper hasnt even been out for a week now so bit early to say what the limit really is, besides all the reveiws seem to point to at least 3200mhz being plug and play
> 
> I'd still like to know if a 4000mhz kit will be fine to run at lower Mhz with tighter timings, is higher binned ram "better over all" then a 3200 or a 3600 kit?


Having bought a single rank B-Die kit rated at 4133MHz c18 (good luck finding them, there were only 50 sold according to Team Group and newegg no longer lists them) to try to hit anything 3600+ (purchased before AGESA 1006 was out)

My advice to you; SAVE MONEY WHERE YOU CAN. Unless you're made of it, paying the premium for only the chance to hit that type of theoretical performance hasn't payed off. The Threadripper are the best of the best Zen cores thrown into a single operating CPU. Meaning that the BEST result you could find on the internet of Ryzen rig performance metrics and OC stability is probably best case scenario for Threadripper, too. The best memory seems to be 3200 c14. 3200Mhz DDR4 seems to be a sweet spot for Zen cores that can even hit 3200MHz (not a guarantee you'll even hit that).

But your odds aren't too good.

1x Ryzen 7 Zen "Core" has 2x 4core/8thread Zen Dies that can do dual channel,

Threadripper Facts
has 2x active "cores" and 2x deactivated "cores" (I'm thinking as PCIe lane pass through or something)

What we can infer about Threadripper from what we know already:
2x Active "Cores" means 4x Active Zen Dies, each 4core/8thread.

ASSUMING:
1) All 16core/32thread hit your desired core OC (4GHz?)
2) the Integrated Memory Controller (that might be 2 different IMC's from 2 different Zen "Cores") can separately hit 3600Mhz at all.
3) the IMC can hit 3600MHz with relatively tight timings
4) the Threadripper CPU can do all this under stress tests that should each be at least 2hrs (depending on test) while staying 100% stable


----------



## gupsterg

Quote:


> Originally Posted by *ste1986*
> 
> I think the 3600c17 kit is also the poorer g Skill bin.
> 
> 3200/14 and 3600/16 are probably the same? Not sure about 3600/15 which may be the top bin?
> 
> Any idea RE training failure per post 641? Tearing my hair out


No idea 1st hand knowledge on binning. I have only used DDR4 when went to Ryzen. I owned 3 kits so far. Corsair 2400MHz C14 (Hynix), Crucial 2400MHz C16 (Micron) and the G.Skill 3200MHz C14 (Samsung B Die). The 3200MHz C14 does really seem to be the kit that my HW likes and others shares also match this experience. If the price was right I wouldn't mind getting 3600MHz C15, as I do believe that is best bin of G.Skill Samsung B die.

Your issue of Q-Code: F9 maybe firmware.

My R7 1700 for ages did that on 3200MHz, rare intermittent Q-Code: F9. My workaround at the time was using "Sleep/Resume", as the post process differs from post from shutdown, it then never did the Q-Code: F9.

Later as AGESA 1.0.0.6 UEFIs came out I was able to gain max ~3500MHz C16 2T or 3333MHz C14 1T with tightened subtimings. I still had the rare intermittent Q-Code: F9. I spent a lot of time tuning settings and stress testing. I came to the conclusion I had to wait for a better UEFI. A UEFI with extra training process at post was released that has solved the issue.

My 1800X also has rare intermittent Q-Code: F9, that does 3466MHz C15 1T with tight subtimings. Again the UEFI with extra training process solved the issue.

So we may pass stress tests, we may have right settings, but still have issues just down to how the UEFI/AGESA is. Elmor has highlighted next round of UEFIs will have AGESA 1.0.0.7, perhaps it will improve 'things'. Besides AGESA having CPU Microcode updates and SMU firmware updates it can include IMC firmware updates. So enjoy what you have attained and reattempt further tweaks when UEFI progresses







.


----------



## Miiksu

Wrong thread. Sorry.


----------



## GloriousEggroll

Hi everyone, new here. This thread helped a lot so I figured I'd drop my results here:

Setup:

Core OC: 4Ghz
CPU: Ryzen 1700X
CPU Voltage: 1.42
CPU LLC: Mode 2
SoC: 1.15
Motherboard: MSI B350 Tomahawk
Bios: 1.72 Beta
Cooler: H100i GTX (H100i v2)

Memory OC:
Ram: G.Skill F4-3200C16D-16GVRB
Timing: 16-18-18-18-38-2T ProcODT: 60 Ohms (would not post below 60)
DRAM Voltage: 1.42
SoC: 1.15
SoC/NB LLC: Mode 2

Test: GSAT 1hr (stressapptest on linux)
Test: Aida64 1hr
Test: mprime 30min (Prime95 for linux)
Max Temp: 61 C
Idle Temp: 38 C

Ran out of time for testing prime last night, will do an extended test today. More screens to come as well

Screens:


----------



## Spanners

Quote:


> Originally Posted by *GloriousEggroll*
> 
> Hi everyone, new here. This thread helped a lot so I figured I'd drop my results here:
> 
> Setup:
> 
> Core OC: 4Ghz
> CPU: Ryzen 1700X
> CPU Voltage: 1.42
> CPU LLC: Mode 2
> SoC: 1.15
> Motherboard: MSI B350 Tomahawk
> Bios: 1.72 Beta
> Cooler: H100i GTX (H100i v2)


What sort of VRM temps are you getting with that configuration?


----------



## braindamage

I haven't seen many Hynix kits on here, so I'll share what I'm currently testing on an Asrock x370 Pro Gaming:

VDIMM: 1.465v
VTT_DDR: 0.750v
SOC: 1.225v LLC 3




I can run at 3066 using these timings with just 0.95v SOC and pass 12 hour prime95 blend + mining for several weeks straight, but need 1.225v SOC for 3200 to not randomly crash in Windows


----------



## chroniclard

Hmm annoying, got 3333 running, up to 1000% HCI then got a few errors. I have 1.0 SOC at the moment, would increasing that help at all?


----------



## bfedorov11

I have a 1700 and Asus Prime B350M-A. Are some boards unable to use certain timings? I cannot run my ram below cl16. It will say it is actually running cl15 in the bios, but once I get to windows it reads cl16. Ram is b die, gskill 2x8 3600 cl15. I am running the latest bios.


----------



## Scotty99

Ya i cant set CL 15 either, asrock killler.


----------



## miklkit

I read somewhere around here that Ryzen doesn't do odd numbers. Even numbers only.


----------



## Dr. Vodka

You can't set odd CL or 2T command rate if you're using geardown mode.

Geardown off, you can do whatever you want.

Geardown is enabled by default if you go higher than 2666MHz on the memory.


----------



## Scotty99

Quote:


> Originally Posted by *Dr. Vodka*
> 
> You can't set odd CL or 2T command rate if you're using geardown mode.
> 
> Geardown off, you can do whatever you want.
> 
> Geardown is enabled by default if you go higher than 2666MHz on the memory.


Hmm ill have to try this later, i swear my board defaults it to off tho.


----------



## Clukos

Had to relax timings a bit to get it stable at 4.0 GHz, 2 hours GSAT + 400% HCI










Soc: 1.125v LLC2
Dram: 1.4v + 1.4vboot


----------



## superstition222

Quote:


> Originally Posted by *bluej511*
> 
> Ive been running 1.45 for a couple months now and haven't had any issues. Id say 1.45 is plenty safe provided you have good case cooling.


Electromigration is continuous as far as I know. What may have worked for years may only work for months if overvolted.


----------



## superstition222

Quote:


> Originally Posted by *Dr. Vodka*
> 
> Hm.
> 
> This passed 1100% HCI, and failed while decompressing /installing something (installer returned CRC error). Reverted memory to safe 2133 and it unpacked just fine, downloaded file checks OK.
> 
> 
> 
> Goddamnit. Need to stress test more.


Sounds like the "northbridge" rather than the RAM but I don't have experience with Zen overclocking. If you were doing this on an FX I would raise CPU NB voltage (or back off on the FSB clock).

Is that what SOC is now, roughly?


----------



## Dr. Vodka

Quote:


> Originally Posted by *superstition222*
> 
> Sounds like the "northbridge" rather than the RAM but I don't have experience with Zen overclocking. If you were doing this on an FX I would raise CPU NB voltage (or back off on the FSB clock).
> 
> Is that what SOC is now, roughly?


Turns out I needed a touch more memory voltage because of my kit using lower quality B-die chips than what you'd find on the 3200C14 kits everyone is using. It's a few posts later.

I've finally settled on this (The Stilt's 3466 timings)



which is great for a 2x8GB 3466 16-18-18-38 2T 1.35v B-die kit.

vSOC 1.1v
vDIMM 1.435v (1.45v at the measuring point for memory in the C6H)
procODT 60ohms
CAD lines 30 ohms each
This is on BIOS 9920, and I could also stabilize this on official 1403. 1501 on the other hand.. it's crap.

I'll leave 9920 behind once they release the AGESA 1007 BIOS up next.


----------



## hsn

hsn [email protected] 1.1v---Gigabyte B350n wifi BIOS F3---HCI Memetes 2000% Gskill 16gb f4 3200C14-8GTZSW


----------



## superstition222

Quote:


> Originally Posted by *hsn*
> 
> hsn [email protected] 1.1v---Gigabyte B350n wifi BIOS F3---HCI Memetes 2000% Gskill 16gb f4 3200C14-8GTZSW


Why test only 11200?


----------



## Synoxia

Guys simple question, do you think 1.42 volt would last atleast 7 years or it's a bit high? 3466 ram 14-15-15-15-36 Aorus k7 mobo, ryzen 1600x stock settings, didn't do a stresstest because i want to learn better first


----------



## hsn

Quote:


> Originally Posted by *superstition222*
> 
> Why test only 11200?


i still launch chrome,there are 4 website when i open hci memtest in the same time until finish


----------



## Silent Scone

Table updated


----------



## blair

Hi Guys,

First real post ITT, rig in use is the Sig-Rig

to save you looking the key elements hardware are
Voltages are listed as 'Load-Idle'

ASUS C6H - v1501
G.Skill F4-3600C16D-16GVK 1.35 16-16-16-36-52-tfaw44-1T- -- 8GBx4 Samsung B-Die
Ryzen 7 1700

CPU Batch: UA 1724PGT Malaysia
CPU: 3.95Ghz
Voltage (via offset): SV12 TFN 1.275-1.300v LLC3
SOC: 1.05-1.056v LLC2 (EFI set to 1.05)
DRAMvBOOT: 1.41v
DRAM Speed: 3333Mhz 1.373-1.395v
Timings: 16-16-16-16-36 2T

Stress Testing so far > Aida 15 mins, RealBench 15 mins, and light gaming, I did get an error on one of the AIDA run at 6 mins, but a second run went to 15 so this isn't very stable yet..









I only really game so I usually aim for gaming stability over much else... I've never hunted that HCI 3000% or simlar on any previous overclock. If i can use it and it never crashes i'm fairly happy









I've never really spent any time properly overclocking RAM before, at least not to the point of learning what all the timings actually mean..
My workload is gaming.. Prior to the mentioned above I was able to run gaming stable 3600 2x8GB @ 3.8G core without must hassle, however AIDA for die within 5-15mins so i ended up going with 3466 where stress testing for 8+ hours in AIDA64/ 4hrs Realbench was error free. I never experienced a Crash at these speeds even when playing with CPU up to 3.95Ghz. Today I installed my second 16GB Kit (originally 1 of the two was DOA).

My goal is 3466Mhz stable with 32gb, I will attempt to get 3600Mhz however I'm not going to work really hard to get it.. If others here want me to test settings for their own knowledge i'm happy to help out where i can, i say this as i don't see a large amount of info out there on this DDR4 kit as well as not as many 4x8G users compared to 2x8G.

Anyway, here is a snap of my HWINFO64, and RTC/Taiphoon if anyone is interested...


SRC: https://puu.sh/xjM2a/1681e29be6.png



SRC: https://puu.sh/xjNuz/c054940ee1.png

Edit: Re-took Taiphoon /RTC screenshot


----------



## blair

UPDATE: Fiddled with timings a bit more.. managed to get 3466 close to 1 hour AIDA64 stress, I will stress overnight and see how it goes..



SRC: https://puu.sh/xjWrT/88579f51ce.png


----------



## yashyulian

test lowend mainboard with ryzen 3


[email protected] 1.1v---BIOS 1.60---HCI---552%---Galax HOF 4000


----------



## schubaltz

schubaltz -- [email protected] ---- 3400mhz 14-14-14-32-50 1T-- 1.4v----SOC 1.15v----Asrock Taichi X370 BIOS 3.00

HCI 2000%---TEAM T-Force Xtreem 3733mhz CL18-20-20-39 1.35v


----------



## SlushPuppy007

Quote:


> Originally Posted by *schubaltz*
> 
> schubaltz -- [email protected] ---- 3400mhz 14-14-14-32-50 1T-- 1.4v----SOC 1.15v----Asrock Taichi X370 BIOS 3.00
> 
> HCI 2000%---TEAM T-Force Xtreem 3733mhz CL18-20-20-39 1.35v


Whats your AIDA64 Memory Score with those settings?


----------



## schubaltz

Quote:


> Whats your AIDA64 Memory Score with those settings?


----------



## Evil Penguin

Has anyone gotten dual-ranked B-Die memory up to 3200MHz?

I'm only having luck getting it up to 2800MHz with my sig rig.


----------



## Praz

Quote:


> Originally Posted by *Evil Penguin*
> 
> Has anyone gotten dual-ranked B-Die memory up to 3200MHz?
> I'm only having luck getting it up to 2800MHz with my sig rig.


Hello

3200MHz 14-13-13 1T in the post linked below.

http://www.overclock.net/t/1628751/official-amd-ryzen-ddr4-24-7-memory-stability-thread/30#post_26052883


----------



## blair

I've gotten my 32gb 4x8G Samsung B-Die what I consider stable now on the 3466 Mem Strap.. Trick for me was VDDP Voltages i think and increasing TFAW i will re-test with lower TFAW and a few other sub timings suggested by Ramad around the post linked below later..

See my post chain linked HERE from the C6H OC'ing thread

Screenshot of Memtest from apporx 3 hours ago from now.. (still running as far as i know...)


SRC= https://puu.sh/xmifK/1cc392d952.png

From 7 Hrs ago or so..

SRC= https://puu.sh/xmcJM/09c2bbb030.png

EDIT: Just got home after a long a** 12.5hr shift, after 21 hours I have 1000% + 0 errors... Time to tweak for performance... or just leave it as is.. haha










SRC= https://puu.sh/xmKhC/1a64ad9367.png

EFI Settings from previous posts used in the above testing



Spoiler: Warning: Spoiler! - Bumped VDDP 1 notch over the 1 error after 100%, no other changes...



[2017/08/29 10:56:07]
Ai Overclock Tuner [Default]
Custom CPU Core Ratio [Auto]
> CPU Core Ratio [39.50]
Performance Bias [Auto]
Memory Frequency [DDR4-3466MHz]
Core Performance Boost [Auto]
SMT Mode [Auto]
EPU Power Saving Mode [Disabled]
TPU [Keep Current Settings]
CPU Core Voltage [Manual mode]
- CPU Core Voltage Override [1.33125]
CPU SOC Voltage [Manual mode]
- VDDSOC Voltage Override [1.13750]
DRAM Voltage [1.42000]
1.8V PLL Voltage [1.81000]
1.05V SB Voltage [1.05000]
Target TDP [Auto]
TRC_EOM [Auto]
TRTP_EOM [Auto]
TRRS_S_EOM [Auto]
TRRS_L_EOM [Auto]
TWTR_EOM [Auto]
TWTR_L_EOM [Auto]
TWCL_EOM [Auto]
TWR_EOM [Auto]
TFAW_EOM [Auto]
TRCT_EOM [Auto]
TREFI_EOM [Auto]
TRDRD_DD_EOM [Auto]
TRDRD_SD_EOM [Auto]
TRDRD_SC_EOM [Auto]
TRDRD_SCDLR_EOM [Auto]
TRDRD_SCL_EOM [Auto]
TWRWR_DD_EOM [Auto]
TWRWR_SD_EOM [Auto]
TWRWR_SC_EOM [Auto]
TWRWR_SCDLR_EOM [Auto]
TWRWR_SCL_EOM [Auto]
TWRRD_EOM [Auto]
TRDWR_EOM [Auto]
TWRRD_SCDLR_EOM [Auto]
Mem Over Clock Fail Count [2]
DRAM CAS# Latency [16]
DRAM RAS# to CAS# Read Delay [16]
DRAM RAS# to CAS# Write Delay [16]
DRAM RAS# PRE Time [16]
DRAM RAS# ACT Time [36]
Trc_SM [56]
TrrdS_SM [7]
TrrdL_SM [10]
Tfaw_SM [50]
TwtrS_SM [Auto]
TwtrL_SM [Auto]
Twr_SM [Auto]
Trcpage_SM [Auto]
TrdrdScl_SM [Auto]
TwrwrScl_SM [Auto]
Trfc_SM [Auto]
Trfc2_SM [Auto]
Trfc4_SM [Auto]
Tcwl_SM [Auto]
Trtp_SM [Auto]
Trdwr_SM [Auto]
Twrrd_SM [Auto]
TwrwrSc_SM [Auto]
TwrwrSd_SM [Auto]
TwrwrDd_SM [Auto]
TrdrdSc_SM [Auto]
TrdrdSd_SM [Auto]
TrdrdDd_SM [Auto]
Tcke_SM [Auto]
ProcODT_SM [53.3 ohm]
Cmd2T [2T]
Gear Down Mode [Disabled]
Power Down Enable [Disabled]
RttNom [Auto]
RttWr [Auto]
RttPark [Auto]
MemAddrCmdSetup_SM [Auto]
MemCsOdtSetup_SM [Auto]
MemCkeSetup_SM [Auto]
MemCadBusClkDrvStren_SM [Auto]
MemCadBusAddrCmdDrvStren_SM [Auto]
MemCadBusCsOdtDrvStren_SM [Auto]
MemCadBusCkeDrvStren_SM [Auto]
VTTDDR Voltage [0.69960]
VPP_MEM Voltage [Auto]
DRAM CTRL REF Voltage on CHA [Auto]
DRAM CTRL REF Voltage on CHB [Auto]
VDDP Voltage [1.08000]
VDDP Standby Voltage [Auto]
1.8V Standby Voltage [Auto]
CPU 3.3v AUX [Auto]
2.5V SB Voltage [Auto]
DRAM R1 Tune [Auto]
DRAM R2 Tune [Auto]
DRAM R3 Tune [Auto]
DRAM R4 Tune [Auto]
PCIE Tune R1 [Auto]
PCIE Tune R2 [Auto]
PCIE Tune R3 [Auto]
PLL Tune R1 [Auto]
PLL reference voltage [Auto]
T Offset [Auto]
Sense MI Skew [Auto]
Sense MI Offset [Auto]
Promontory presence [Auto]
Clock Amplitude [Auto]
CPU Load-line Calibration [Auto]
CPU Current Capability [130%]
CPU VRM Switching Frequency [Auto]
VRM Spread Spectrum [Disabled]
Active Frequency Mode [Disabled]
CPU Power Duty Control [T.Probe]
CPU Power Phase Control [Auto]
CPU Power Thermal Control [120]
VDDSOC Load-line Calibration [Auto]
VDDSOC Current Capability [Auto]
VDDSOC Switching Frequency [Auto]
VDDSOC Phase Control [Auto]
DRAM Current Capability [120%]
DRAM Power Phase Control [Extreme]
DRAM Switching Frequency [Auto]
DRAM VBoot Voltage [1.42000]
Security Device Support [Enable]
TPM Device Selection [Discrete TPM]
Erase fTPM NV for factory reset [Enabled]
PSS Support [Enabled]
NX Mode [Enabled]
SVM Mode [Enabled]
SATA Port Enable [Enabled]
PT XHCI GEN1 [Auto]
PT XHCI GEN2 [Auto]
PT USB Equalization4 [Auto]
PT USB Redriver [Auto]
PT PCIE PORT 0 [Auto]
PT PCIE PORT 1 [Auto]
PT PCIE PORT 2 [Auto]
PT PCIE PORT 3 [Auto]
PT PCIE PORT 4 [Auto]
PT PCIE PORT 5 [Auto]
PT PCIE PORT 6 [Auto]
PT PCIE PORT 7 [Auto]
Onboard PCIE LAN PXE ROM [Enabled]
AMD CRB EHCI Debug port switch [Disabled]
Onboard LED [Enabled]
Hyper kit Mode [Disabled]
SATA Port Enable [Enabled]
SATA Mode [AHCI]
SMART Self Test [Enabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
ErP Ready [Disabled]
Restore On AC Power Loss [Power Off]
Power On By PCI-E/PCI [Disabled]
Power On By RTC [Disabled]
Super I/O Clock Skew [Auto]
HD Audio Controller [Enabled]
PCIEX4_3 Bandwidth [Auto]
PCIEX16_1 Mode [Auto]
PCIEX8_2 Mode [Auto]
PCIEX4_3 Mode [Auto]
M.2 Link Mode [Auto]
SB Link Mode [Auto]
Asmedia USB 3.1 Controller [Enabled]
RGB LED lighting [Enabled]
In sleep, hibernate and soft off states [On]
Intel LAN Controller [Enabled]
Intel LAN OPROM [Disabled]
USB Type C Power Switch for USB3.1_E1 [Auto]
USB Type C Power Switch for USB3.1_EC2 [Auto]
Network Stack [Disabled]
Debug Port Table [Disabled]
Debug Port Table 2 [Disabled]
Device [Samsung SSD 850 EVO 500GB]
Legacy USB Support [Disabled]
XHCI Hand-off [Enabled]
USB Mass Storage Driver Support [Enabled]
SanDisk Cruzer Switch 1.26 [Auto]
USB3.1_E1 [Auto]
USB3_1 [Enabled]
USB3_2 [Enabled]
USB3_3 [Enabled]
USB3_4 [Enabled]
USB3_5 [Auto]
USB3_6 [Auto]
USB3_7 [Auto]
USB3_8 [Auto]
USB3_9 [Auto]
USB3_10 [Auto]
USB2_11 [Auto]
USB2_12 [Auto]
USB2_13 [Auto]
USB2_14 [Auto]
USB_15 [Auto]
USB_16 [Auto]
CPU Temperature [Monitor]
MotherBoard Temperature [Monitor]
VRM Temperature [Monitor]
PCH Temperature [Monitor]
T_Sensor1 Temperature [Monitor]
CPU Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
Chassis Fan 3 Speed [Monitor]
W_PUMP+ Speed [Monitor]
CPU Optional Fan Speed [Monitor]
AIO_PUMP Speed [Monitor]
W_FLOW Speed [Monitor]
W_IN Temperature [Monitor]
W_OUT Temperature [Monitor]
CPU Core Voltage [Monitor]
3.3V Voltage [Monitor]
5V Voltage [Monitor]
12V Voltage [Monitor]
CPU Q-Fan Control [Auto]
CPU Fan Smoothing Up/Down Time [2.6 sec]
CPU Fan Speed Lower Limit [200 RPM]
CPU Fan Profile [Standard]
W_PUMP+ Control [Disabled]
Chassis Fan 1 Q-Fan Control [Auto]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Smoothing Up/Down Time [0 sec]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 1 Profile [Manual]
Chassis Fan 1 Upper Temperature [70]
Chassis Fan 1 Max. Duty Cycle (%) [100]
Chassis Fan 1 Middle Temperature [45]
Chassis Fan 1 Middle. Duty Cycle (%) [60]
Chassis Fan 1 Lower Temperature [40]
Chassis Fan 1 Min. Duty Cycle (%) [21]
Chassis Fan 2 Q-Fan Control [Auto]
Chassis Fan 2 Q-Fan Source [CPU]
Chassis Fan 2 Smoothing Up/Down Time [0 sec]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 2 Profile [Manual]
Chassis Fan 2 Upper Temperature [70]
Chassis Fan 2 Max. Duty Cycle (%) [100]
Chassis Fan 2 Middle Temperature [45]
Chassis Fan 2 Middle. Duty Cycle (%) [60]
Chassis Fan 2 Lower Temperature [40]
Chassis Fan 2 Min. Duty Cycle (%) [23]
Chassis Fan 3 Q-Fan Control [Auto]
Chassis Fan 3 Q-Fan Source [CPU]
Chassis Fan 3 Smoothing Up/Down Time [0 sec]
Chassis Fan 3 Speed Low Limit [200 RPM]
Chassis Fan 3 Profile [Standard]
OnChip SATA Channel [Auto]
OnChip SATA Type [AHCI]
USB3_1 [Enabled]
USB3_2 [Enabled]
USB3_3 [Enabled]
USB3_4 [Enabled]
IR Config [RX & TX0 Only]
SdForce18 Enable [Disabled]
SD Mode configuration [AMDA]
Uart 0 Enable [Enabled]
Uart 1 Enable [Enabled]
I2C 0 Enable [Enabled]
I2C 1 Enable [Enabled]
I2C 2 Enable [Disabled]
I2C 3 Enable [Disabled]
GPIO Devices Support [Auto]
ESATA Port On Port 0 [Auto]
ESATA Port On Port 1 [Auto]
ESATA Port On Port 2 [Auto]
ESATA Port On Port 3 [Auto]
ESATA Port On Port 4 [Auto]
ESATA Port On Port 5 [Auto]
ESATA Port On Port 6 [Auto]
ESATA Port On Port 7 [Auto]
SATA Power On Port 0 [Auto]
SATA Power On Port 1 [Auto]
SATA Power On Port 2 [Auto]
SATA Power On Port 3 [Auto]
SATA Power On Port 4 [Auto]
SATA Power On Port 5 [Auto]
SATA Power On Port 6 [Auto]
SATA Power On Port 7 [Auto]
SATA Port 0 MODE [Auto]
SATA Port 1 MODE [Auto]
SATA Port 2 MODE [Auto]
SATA Port 3 MODE [Auto]
SATA Port 4 MODE [Auto]
SATA Port 5 MODE [Auto]
SATA Port 6 MODE [Auto]
SATA Port 7 MODE [Auto]
SATA Hot-Removable Support [Auto]
SATA 6 AHCI Support [Auto]
Int. Clk Differential Spread [Auto]
SATA MAXGEN2 CAP OPTION [Auto]
SATA CLK Mode Option [Auto]
Aggressive Link PM Capability [Auto]
Port Multiplier Capability [Auto]
SATA Ports Auto Clock Control [Auto]
SATA Partial State Capability [Auto]
SATA FIS Based Switching [Auto]
SATA Command Completion Coalescing Support [Auto]
SATA Slumber State Capability [Auto]
SATA MSI Capability Support [Auto]
SATA Target Support 8 Devices [Auto]
Generic Mode [Auto]
SATA AHCI Enclosure [Auto]
SATA SGPIO 0 [Disabled]
SATA SGPIO 1 [Disabled]
SATA PHY PLL [Auto]
AC/DC Change Message Delivery [Disabled]
TimerTick Tracking [Auto]
Clock Interrupt Tag [Enabled]
EHCI Traffic Handling [Disabled]
Fusion Message C Multi-Core [Disabled]
Fusion Message C State [Disabled]
SPI Read Mode [Auto]
SPI 100MHz Support [Auto]
SPI Normal Speed [Auto]
SPI Fast Read Speed [Auto]
SPI Burst Write [Auto]
I2C 0 D3 Support [Auto]
I2C 1 D3 Support [Auto]
I2C 2 D3 Support [Auto]
I2C 3 D3 Support [Auto]
UART 0 D3 Support [Auto]
UART 1 D3 Support [Auto]
SATA D3 Support [Auto]
EHCI D3 Support [Auto]
XHCI D3 Support [Auto]
SD D3 Support [Auto]
S0I3 [Auto]
Chipset Power Saving Features [Enabled]
SB Clock Spread Spectrum [Auto]
SB Clock Spread Spectrum Option [-0.375%]
HPET In SB [Auto]
MsiDis in HPET [Auto]
_OSC For PCI0 [Auto]
USB Phy Power Down [Auto]
PCIB_CLK_Stop Override [0]
USB MSI Option [Auto]
LPC MSI Option [Auto]
PCIBridge MSI Option [Auto]
AB MSI Option [Auto]
SB C1E Support [Auto]
SB Hardware Reduced Support [Auto]
GPP Serial Debug Bus Enable [Auto]
IOMMU [Auto]
Remote Display Feature [Auto]
Gnb Hd Audio [Auto]
PSPP Policy [Auto]
Memory Clock [Auto]
Bank Interleaving [Enabled]
Channel Interleaving [Enabled]
Memory Clear [Disabled]
Fast Boot [Enabled]
Next Boot after AC Power Loss [Normal Boot]
Boot Logo Display [Disabled]
POST Report [5 sec]
Boot up NumLock State [Enabled]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Enabled]
Interrupt 19 Capture [Disabled]
Setup Mode [Advanced Mode]
Launch CSM [Disabled]
OS Type [Other OS]
Setup Animator [Disabled]
Load from Profile [4]
Profile Name [3.95 3466 VDDP]
Save to Profile [3]
CPU Core Voltage [Auto]
VDDSOC Voltage [Auto]
1.8V PLL Voltage [Auto]
BCLK Frequency [Auto]
CPU Ratio [Auto]
Bus Interface [PCIEX16/X8_1]


----------



## Clukos

3 hours GSAT stable










vdimm 1.4
vsoc 1.1

Combined with a 1700 3.9 GHz overclock at 0.15 offset LLC3


----------



## methebest

Had a go at overclocking yesterday, couldn't boot at 3200Mhz but 2933 is still a big improvement. left hci running overnight.

[email protected] 1.15v---BIOS A.60---HCI---2400%---F4-2133C15-4GNT


----------



## ste1986

[email protected] 1.125v---BIOS F6---HCI---1600%---F4-3600C17D-16GTZR

Note I couldn't get near this at 1.45v and 1.175v SOC so there for sure is a point at which voltage is too high and limiting progress.

Gigabyte Gaming 5 board on F6 BIOS.

This is F9 free and solid, also stable slightly looser at 3466 (800% HCI) but won't cold boot consistently so didn't bother testing further


----------



## ste1986

PS if anyone could take a look at the seconds/thirds on that and let me know if anything else could give any worthwhile improvement let me know and I will adjust and retest









I have not pushed tRC or tRFC further but could do and see if it will take it.

Also tempted to see whether it'll so 14-13-13-13-26 but suspect that's being greedy









My ultimate is to land 3466c14 but F9 boot codes are killing it. Hopefully Gigabyte sort their new BIOS out so it stops frying CPUs and I can test it...


----------



## Shawn Shutt jr

anyone have any luck with CMD32GX4M2B3000C15 corsair dominator platinum ddr4 16x32GB 3000mhz im sitting at 16-16-16-39-1T @1.3v on a ryzen 1700 3.9GHZ with ROG crosshair VI.


----------



## ADRO3

Let me write here also to try to find some info.

Does anyone know if ASROCK is thinking/planning of implementing DRAM boot voltage option.

I find this to be a huge issue for Dram boot stability. I can boot from bios @ 3466 cl14 with The Stilts timings and same memory kit, stresstest it, game and everything works super great, but from a cold boot i get F9 then bootloops and back to bios. I did try it with amd memory training and no luck. After i reapply my OC profile it boots just fine from bios.

If i am not mistaken only C6H is having this option. I guess this is only bios related and not hardware?

Do any of you have some advice? Is the only reason i cannot get it to cold boot dram boot voltage because it sure seems so?

i tried with dram voltage up to 1.4 and soc up to 1.2 and it doesent make any difference for a cold boot. It is fully stable at 1.37v on dram and 1.1 on SOC once it is booted from bios.

as i am aware ram always tries to start @1.2v if there is no option of DRAM boot voltage.

Please ASROCK ... PLEASE!


----------



## ste1986

Exactly the same problem here on gaming 5. Real shame.


----------



## Alexium

I've bought a pair of weird RAM sticks (I guess you can call it noname). Hynix chips, rated at DDR4-3200 1.35 V 16-18-18-39 (not a typo). Got it running at 3066 @ 1.36 V (somehow my MSI X370 likes to set 1.36 instead of 1.35), 18-20-20-40, CR 2T, GearDown off.
Any attempts at 3200 MHz failed so far no matter how relaxed the timings.

Should I increase the SOC voltage? It's Auto now, something like 0.92. Should I go for 1.0 or 1.1?

Of note: Ryzen Timing Checker is not working for me. It shows this:


Spoiler: RTC







I think these are the default SPD timings for 2133 MHz.

Update: I was too quick to call it a success (talk about 24/7 stability). The system would sometimes power down on reboot and revert back to SPD 2133 MHz. So I've tried the following: reverted everything back to default/Auto, activated XMP (which I previously did not do), set the clock to 3066, Geardown ON (because I think XMP has CR at 1T), VRAM to 1.38, SOC to 1.075 (results in 1.1). Seems to stick so far, no shutdown on reboot yet. Gonna pursue 3200 tomorrow, will be grateful for any tips.

P. S. This is on MSI X370 Gaming Plus, latest BIOS - one after AGESA 1.0.0.6. Ryzen 7 1700 (non-X).


----------



## ADRO3

[email protected] 1.15v---BIOS 3.1---HCI---400%---F4-3600C15D-16GTZ

Boots OK frrom cold no F9 errors and is working fully stable on my x370 taichi. I am also pretty happy with benchmark scores


----------



## SlushPuppy007

Quote:


> Originally Posted by *ADRO3*
> 
> [email protected] 1.15v---BIOS 3.1---HCI---400%---F4-3600C15D-16GTZ
> 
> Boots OK frrom cold no F9 errors and is working fully stable on my x370 taichi. I am also pretty happy with benchmark scores


Looks good, can you please share your timings with Ryzen Timing Checker?


----------



## Jpmboy

any threadripper ram postings yet???


----------



## SlushPuppy007

Hi,

I'm running:

1800X
ASRock X370 Taichi (1.0.0.6b)
G.Skill F4-4266C19D-16GTZR

Running the RAM at 3200 and 3466 MHz with low timings (1.45 volts) is not a problem with Gear Down Mode = Enabled.

Can reboot / cold boot without problems.

AIDA shows decent results comparable to others in this thread.

As soon as I Disable GDM and set 1T Command Rate, the machine fails to boot.

So far, increasing VDDR SOC (IMC) voltage up to 1.2v did not help.

How can I stabilize the overclock, do I need to set additional voltage somewhere?


----------



## chonas

Have GALAX HOF 3600mhz sticks. Currently at 2666 12x4 32 stresstested stable. What should my timing progressions be for the next steps?


----------



## usoldier

I got this Kit F4-3200C14D-16GTZR cant seem to get it stable at 3200 HCI mem test keeps giving error can anyone please help


----------



## Keith Myers

Quote:


> Originally Posted by *Jpmboy*
> 
> any threadripper ram postings yet???


I've been lurking on this thread.
asus-rog-zenith-extreme-x399-threadripper-overclocking-support


----------



## crakej

Quote:


> Originally Posted by *SlushPuppy007*
> 
> Hi,
> 
> I'm running:
> 
> 1800X
> ASRock X370 Taichi (1.0.0.6b)
> G.Skill F4-4266C19D-16GTZR
> 
> Running the RAM at 3200 and 3466 MHz with low timings (1.45 volts) is not a problem with Gear Down Mode = Enabled.
> 
> Can reboot / cold boot without problems.
> 
> AIDA shows decent results comparable to others in this thread.
> 
> As soon as I Disable GDM and set 1T Command Rate, the machine fails to boot.
> 
> So far, increasing VDDR SOC (IMC) voltage up to 1.2v did not help.
> 
> How can I stabilize the overclock, do I need to set additional voltage somewhere?


What other settings are you using? - I have same memory on X370 Pro. I only use 0.939 on SoC. Do you have BankGroupSwapAlt enabled? I've read that we should use this and not BankGroupSwap....I may do more experimenting with geardown on....I can't even boot at 3466


----------



## Jpmboy

Quote:


> Originally Posted by *Keith Myers*
> 
> I've been lurking on this thread.
> asus-rog-zenith-extreme-x399-threadripper-overclocking-support


thanks - I check gupsterg's thread once in a while.


----------



## SlushPuppy007

Quote:


> Originally Posted by *crakej*
> 
> What other settings are you using? - I have same memory on X370 Pro. I only use 0.939 on SoC. Do you have BankGroupSwapAlt enabled? I've read that we should use this and not BankGroupSwap....I may do more experimenting with geardown on....I can't even boot at 3466


Glad to hear someone else is also having a tough time with this kit









I'll share more information tonight when I get home.

In short, I managed to boot 3200, 3466 and 3600 with GDM = On. Stability is poor on 3466 and at 3600 the stability tests fails instantly.

Currently I found some settings for 3200MHz that enable me to complete about 2 hours of stability testing before getting errors.

Once I get stable on 3200 I'll move up to 3466.

Being able to boot at 3600 gave me hope.

BUT, disabling GDM is a complete no go on my system, then I cant boot anything past 2933.


----------



## happyluckbox

Hi all, so I've got 128GB of g.skill tridentz rgb stable at 3066mhz 14-14-14-30 2T on my threadripper 1950 (oc at 3.9ghz)

I'm really trying to get it to 3200mhz stable, but it looks like it wont accept 3200mhz unless I loosen timings to 16.

Do you guys think its worth even attempting to stabilize 3200mhz if I'm loosing 2 timing steps?


----------



## SaccoSVD

128Gb at 3066mhz 14-14-14-30 2T looks pretty darn good to me. Considering also you're on a quad channel config.







your AIDA measured throughput must go through the roof right?

I have been pondering about all this, and I think I'm gonna enjoy my current ryzen system and jump to a Threadripper 2 (most likely will come after Ryzen 2)


----------



## happyluckbox

Quote:


> Originally Posted by *SaccoSVD*
> 
> 128Gb at 3066mhz 14-14-14-30 2T looks pretty darn good to me. Considering also you're on a quad channel config.
> 
> 
> 
> 
> 
> 
> 
> your AIDA measured throughput must go through the roof right?
> 
> I have been pondering about all this, and I think I'm gonna enjoy my current ryzen system and jump to a Threadripper 2 (most likely will come after Ryzen 2)


I have aida 64 extreme (trial version)
I've played around with it a bit... how do I find measured throughput?


----------



## SaccoSVD

On the tools menu:


----------



## happyluckbox

Thanks,

So I guess since I have the trial version, I dont get outputs for some of the benchmark results?



Everybody else in here actually purchased aida64 extreme?


----------



## SaccoSVD

Doesn't matter, they'll be around the same.

DAAAANG! that's some big ass throughput. Generally you see around 45000 on Ryzen. Your latency is also really good. Generally in Ryzen is 87ns or 78ns and in some very good cases around yours.

No need to tweak your RAM in my opinion, yours is smoking fast already. I think most due to having Quad channel.

And because you have double the cores your cache throughput is also through the roof!


----------



## SaccoSVD

What did you buy that machine for?


----------



## SlushPuppy007

Before OP kills me, I know my screenshot does not contain all the right info.

I will be posting that soon, just want to give an update on my current progress.

My components:

1800X
X370 Taichi (1.0.0.6b)
G.Skill f4-4266c19d-16gtzr

I'm running stable at 3200MHz with the following timings and voltages!

VDDR_SOC = 1.2v
VDDR_SOC LLC = Level 5

RAM Voltage = 1.4v
ProcODT = 60 Ohm



Its not perfect, but it works. My board hates when I disable GDM and set 1T (most probably because of some timings still to tight).

Also, I have no option to set BankGroupSwap or BankGroupSwapAlt currently, hopefully in the next bios release.

So I increased the speed to 3466MHz with the same timings as above, and it failed to boot, setting the ProcODT to 53.3 Ohm did the trick and I could boot.

Currently I'm still trying to get it stable, but I believe my timings are too tight for 3466, will be loosening it up based on settings from "The Stilt".

Doing extensive testing over this weekend, will post progress.


----------



## Alexium

Quote:


> Originally Posted by *SlushPuppy007*
> 
> I'm running stable at 3200MHz with the following timings and voltages!


I see a lot of timings that are wrong, too tight indeed.
tRAS = tCL + tRCD + 2 so should be 14+14+2 = 30
tRC = tRAS + tRP = 44
tFAW = tRRDS * 6 = 24
tWTRL / tWR = tCL + 4 = 18
tRFC should typically be between 6xRC and 8xRC, yours is slightly larger but probably not too large to cause instability
tCWL = tCL = 14
tRDWR = 1/2 * tWTRL
tWRRD = 1/2 * RDWR (you have 0!)


----------



## Silent Scone

Quote:


> Originally Posted by *happyluckbox*
> 
> Thanks,
> 
> So I guess since I have the trial version, I dont get outputs for some of the benchmark results?
> 
> 
> 
> Everybody else in here actually purchased aida64 extreme?


Yes. Also, that's quite impressive for that density. Time to see if it's stable?


----------



## crakej

Quote:


> Originally Posted by *Alexium*
> 
> I see a lot of timings that are wrong, too tight indeed.
> tRAS = tCL + tRCD + 2 so should be 14+14+2 = 30
> tRC = tRAS + tRP = 44
> tFAW = tRRDS * 6 = 24
> tWTRL / tWR = tCL + 4 = 18
> tRFC should typically be between 6xRC and 8xRC, yours is slightly larger but probably not too large to cause instability
> tCWL = tCL = 14
> tRDWR = 1/2 * tWTRL
> tWRRD = 1/2 * RDWR (you have 0!)


Thank you.... Been looking for these! Only knew how to work out tRFC1/2/4.

Curious about your source for this info?


----------



## Alexium

Quote:


> Originally Posted by *crakej*
> 
> Curious about your source for this info?


Bottom of this post: https://forums.overclockers.ru/viewtopic.php?p=14935169#p14935169


----------



## crakej

Quote:


> Originally Posted by *Alexium*
> 
> Bottom of this post: https://forums.overclockers.ru/viewtopic.php?p=14935169#p14935169


Thank you! Really useful post.....and I haven't even translated it yet! With your help I now have this:

DDR4 Settings Calculations.

tRAS = tCL + tRCD + 2 so should be 14+14+2 = 30
tRC = tRAS + tRP = 44
tFAW = tRRDS * 6 = 24
tWTRL / tWR = tCL + 4 = 18

tRFC should typically be between 6xRC and 8xRC, yours is slightly larger but probably not too large to cause instability, but all ram comes with default tRFC timing like 350ns.....so...
350/2000*Required speed - i.e. 3200 = 560
tRFC2= tRFC/1.345 = 416
tRFC4=tRFC2/1.625 = 256

tCWL = tCL = 14
tRDWR = 1/2 * tWTRL
tWRRD = 1/2 * RDWR

tWRTL and tWR are device dependant - some rams tWR=2 * tWRTL, some tWR=tWRTL-2 - you can work these out from the JDEC and XMP info. tWR=2*tWRTL is not an IMC problem but a feature of different devices.

I will post this info in other forums right now. Thank you so much for sharing


----------



## Alexium

Quote:


> Originally Posted by *crakej*
> 
> I will post this info in other forums right now. Thank you so much for sharing


No problem!
But it's not the ultimate answer to all questions. Some timings are supposed to be taken from XMP, but XMP often has some broken values, and you need experience (or someone experienced) to notice and correct it. I've had at least two or three subtimings set too low. Correcting them did not help me reach the advertised speed of 3200, but it did stabilize operation at 3066.


----------



## eXile6

Hey guys,

I am going to be ordering my new Ryzen system soon and have a few questions in regards to what to buy.

Now Memory seems very critical to Ryzen's performance (especially in games) and since the main use of this PC will be gaming and productivity (video streaming/recording), I would like the best kit for the job.

CPU: R7 1700X
Mobo: Asus CH6 or Gigabyte K7
RAM: ???
Choice 1: [Trident Z RGB] F4-3200C14D-16GTZR
Choice 2: [Trident Z RGB] F4-3200C14D-32GTZR

Ideally I would like 32GB ram, Adobe Premier loves it and the more the better. However seeing how some people are struggling even getting 16GB kits to run at 3200, is it worth getting the 32?

Any input will be highly appreciated (even your opinion on the mobo/cpu choice is welcome).


----------



## Evil Penguin

Quote:


> Originally Posted by *eXile6*
> 
> Hey guys,
> 
> I am going to be ordering my new Ryzen system soon and have a few questions in regards to what to buy.
> 
> Now Memory seems very critical to Ryzen's performance (especially in games) and since the main use of this PC will be gaming and productivity (video streaming/recording), I would like the best kit for the job.
> 
> CPU: R7 1700X
> Mobo: Asus CH6 or Gigabyte K7
> RAM: ???
> Choice 1: [Trident Z RGB] F4-3200C14D-16GTZR
> Choice 2: [Trident Z RGB] F4-3200C14D-32GTZR
> 
> Ideally I would like 32GB ram, Adobe Premier loves it and the more the better. However seeing how some people are struggling even getting 16GB kits to run at 3200, is it worth getting the 32?
> 
> Any input will be highly appreciated (even your opinion on the mobo/cpu choice is welcome).


It's probably worth going with 32GB and be good with that for a while.

I think eventually with more BIOS updates 16GB modules will work reliably at 3200MHz.


----------



## Alexium

Quote:


> Originally Posted by *eXile6*
> 
> Hey guys,
> 
> seeing how some people are struggling even getting 16GB kits to run at 3200, is it worth getting the 32?


3200C14 means Samsung chips. 16 GB kits that struggle with 3200 are Hynix or Micron. So your 16 GB option is no problem. Now, 16 GB modules (of the 32 GB kit) are double-sided, which is harder for the Ryzen's IMC, but I have heard that people manage to run Samsung 32 GB kits at decent clocks, too. How certain / reliable / difficult that is, I don't know.


----------



## Alexium

Quote:


> Originally Posted by *Evil Penguin*
> 
> I think eventually with more BIOS updates 16GB modules will work reliably at 3200MHz.


Not if the problem is in the IMC hardware.


----------



## Evil Penguin

Quote:


> Originally Posted by *Alexium*
> 
> Not if the problem is in the IMC hardware.


Yes, "if". It's not clear to me whether or not that's the case yet. I don't think AMD is done improving memory compatibility.


----------



## happyluckbox

If im able to run 128gb of gskill memory at 3060mhz 14-14-14-30 rock solid stable I think the memory controller can handle more than you think


----------



## Alexium

Quote:


> Originally Posted by *happyluckbox*
> 
> If im able to run 128gb of gskill memory at 3060mhz 14-14-14-30 rock solid stable I think the memory controller can handle more than you think


Curious (and I apologize for off-topic): are you actually using that much RAM? If yes, may I ask what for?
It's not that I can't think of any uses, but everything I could think of is rather exotic.


----------



## happyluckbox

Quote:


> Originally Posted by *Alexium*
> 
> Curious (and I apologize for off-topic): are you actually using that much RAM? If yes, may I ask what for?
> It's not that I can't think of any uses, but everything I could think of is rather exotic.


I use it for piosolver, its a program that simulates game theoretically optimal poker.
I explained it in a prior post but i think it went over most peoples heads haha.


----------



## Alexium

Quote:


> Originally Posted by *happyluckbox*
> 
> I explained it in a prior post but i think it went over most peoples heads haha.


I honestly did not see it, it's not on the last two pages. Thanks for indulging my curiosity


----------



## happyluckbox

Here it is, was in the threadripper thread
Quote:


> Originally Posted by *happyluckbox*
> 
> I use it for Piosolver-
> It solves the game of poker from preflop, flop, turn, and river for multiple bet and raise sizes. Basically it allows you to input ranges for the preflop raiser and the caller, and using these ranges it will extrapolate the best play (for both players) for every scenario using game theoretically optimal play (GTO). The longer the solver runs for, the closer to a nash equilibrium strategy it gets for both players. (where either player can do nothing further to exploit their respective villian, and if he were to deviate from pio's strategy he can then be exploited and lose ev)
> 
> You can imagine the computations can be rather long/intensive, given how massive the game tree can actually get.
> 
> Just to give you an idea, theres 1326 possible combinations of hands you can be dealt preflop, and there are 22100 different flops in poker (of which 1755 are strategicaly relevant). This doesnt even begin to look at multiple bet/raise sizes for different hands, or different runouts for turns and rivers for each of those actions. The amount of ram it takes to solve from some situations from preflop can be mind boggling, which is why I went for a 128gb ddr threadripper build
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I play poker as a profession so exploring gto strategy begins to get useful for me at the stakes I play at. I have days where i win or lose an entire threadripper setup or more, so I think investing 5-6k in TR build was a wise choice long
> term
> 
> 
> 
> 
> 
> 
> 
> 
> 
> (I also intend to play games occasionally, and its always nice to have some justification to sate my computer hobby
> 
> 
> 
> 
> 
> 
> 
> )


----------



## Synoxia

Question: do you think in the future it will be possible to "ovc" the IMC? (I am noob) Because i am sick of not being able to run my gskill 16 gb 3600 cl17 kit... i am now stuck with 3466 cl14 1t command rate 1.43 volt (for some reason, i can boot only CL14 with the new f6 bios, so i just raised the voltages lol)


----------



## Nautilus

So what's the best kit available for ryzen these days? Still the flare x 3200s?


----------



## superstition222

Quote:


> Originally Posted by *Nautilus*
> 
> So what's the best kit available for ryzen these days? Still the flare x 3200s?


Patriot has certified some of its RAM to run at 3400. It also certified 32 GB at 3200.

http://www.anandtech.com/show/11624/patriot-publishes-list-of-amd-ryzen-compatible-dimms-up-to-ddr43400-up-to-64-gb

There may be faster RAM available.


----------



## sbakic

Hello guys,

i just bought ryzen build my specs:
R7 1700x
KRAKEN x62
Crosshair Vi Hero (WI-FI)
Gskill trindentZ 32GB CL15 3000MHZ
GTX 1070 OC ASUS
PSU EVGA 750P2

This is my first oc system and i have some troubles. Currently it is oc as this:
R7 1700x 3.8Ghz
Vcore offset + 0.025
CPU LLC level 1
BLCK 100mhz
ram 2800 mhz C15 2T 1.35V
C states Enabled
everything other is auto
Soc is 1.05 with this ram

I tried to bump cpu clock to 39x it couldn't pass cinebenchR15 on 1.4215V manual so i let it to be 38x, but 38.50x wasn't stable 100% at 1.4125V too

System passed:
cinebenchR15,
PSMark
RealBech (benchmark and stresstest 15min (with 16GB ram not 32GB))
3dMark
AIDA64 stresstest 1h
7zip

Cant pass prime95 large fft and OCCT 1h (15min max)

VID is 1.325, vcore is with this offset max 1.375 -1.385V

From these test I should say that i didn't win the lottery for cpu and don't know what to do next, what should I do?


----------



## SaccoSVD

Quote:


> Originally Posted by *sbakic*
> 
> Hello guys,
> 
> i just bought ryzen build my specs:
> R7 1700x
> KRAKEN x62
> Crosshair Vi Hero (WI-FI)
> Gskill trindentZ 32GB CL15 3000MHZ
> GTX 1070 OC ASUS
> PSU EVGA 750P2
> 
> This is my first oc system and i have some troubles. Currently it is oc as this:
> R7 1700x 3.8Ghz
> Vcore offset + 0.025
> CPU LLC level 1
> BLCK 100mhz
> ram 2800 mhz C15 2T 1.35V
> C states Enabled
> everything other is auto
> Soc is 1.05 with this ram
> 
> I tried to bump cpu clock to 39x it couldn't pass cinebenchR15 on 1.4215V manual so i let it to be 38x, but 38.50x wasn't stable 100% at 1.4125V too
> 
> System passed:
> cinebenchR15,
> PSMark
> RealBech (benchmark and stresstest 15min (with 16GB ram not 32GB))
> 3dMark
> AIDA64 stresstest 1h
> 7zip
> 
> Cant pass prime95 large fft and OCCT 1h (15min max)
> 
> VID is 1.325, vcore is with this offset max 1.375 -1.385V
> 
> From these test I should say that i didn't win the lottery for cpu and don't know what to do next, what should I do?


Try LLC3 and CPU/SOC Phase set to extreme. That alone should help a lot. Here Phase set to extreme allowed me to go from 1.42v down to 1.375v at LLC3 for a 4Ghz OC.

SOC to 1.1v is also good, and safe. (1.25v is on the danger side)

BTW: Forget CPUz vcore reading. Use HWInfo "CPU Core Voltage (SVI2 TFN)"


----------



## Jpmboy

Quote:


> Originally Posted by *happyluckbox*
> 
> Thanks,
> 
> So I guess since I have the trial version, I dont get outputs for some of the benchmark results?
> 
> 
> 
> Everybody else in here actually purchased aida64 extreme?


if you want the full package - yes, you have to buy it.
Quote:


> Originally Posted by *Alexium*
> 
> Bottom of this post: https://forums.overclockers.ru/viewtopic.php?p=14935169#p14935169


tRAS = CAS+tRDC+*tRTP*. that link is wrong. Check the JEDEC standard.


----------



## Alexium

Quote:


> Originally Posted by *Jpmboy*
> 
> tRAS = CAS+tRDC+*tRTP*. that link is wrong. Check the JEDEC standard.


It wasn't wrong, it listed different suggestions for Samsung and Hynix. Anyway, that set of formulas is being reworked and is no longer available.


----------



## sbakic

I think that volte for cpu drops to much i set to manual 1.4125V and LLC1 and it drops to 1.331V while hard stress test comes and it crush pc. What to do then?


----------



## janice1234

[email protected] 0.98v---BIOS 3.10---HCI---1000%---F4-3200C14D-16GFX


----------



## Jpmboy

Quote:


> Originally Posted by *Alexium*
> 
> It wasn't wrong, it listed different suggestions for Samsung and Hynix. Anyway, that set of formulas is being reworked and is no longer available.


yeah, the thing is the ras window needs to be open for all three operations to complete. What happens is when ras is set too low (and even XMPs are low) the board corrects the timing error during post - but does not relay this event. And it is redone at each post so the substituted value changes. -2 off the sum is usually fine, or when the system tolerates (and is stable to) mush lower values of RAS, there may actually be an offset to the user end of the bios. The timing correction can deal with a fair amount, but we know you can set RAS so low that things can go waaay off the reservation.


----------



## Alexium

Quote:


> Originally Posted by *Jpmboy*
> 
> yeah, the thing is the ras window needs to be open for all three operations to complete


Interesting, thanks a lot for the explanation. Do you happen to know the formulas for setting other timings properly? Secondary / tertiary timings? I know my XMP has some seriously broken values. I fixed them ,more or less (with the help of knowledgeable people), but still not sure if it's all correct now.
I have not been able to POST my 2x8 GB 3200 Hynix kit at 3200, and I would love to...


----------



## ssateneth

Can anyone recommend some settings to make 4x16GiB stable with 3333MHz speed? Doesn't get far into POST, often stuck on 54, 55, sometimes stuck on other 'random' codes. I've tried SoC voltages from 0.9 to 1.3 in 0.025v increments with no change in behavior. Rarely causes motherboard to beeeeeeeeeeeep (MSI x399). 3466 is almost guaranteed motherboard beep. I see some ohms setting mentioned here and there. Any suggestions to what to set it to (rather, what the default is, recommended direction to go, and 'maximum safe' value)? Equipment used in sig. Core speeds currently toying with 4.2GHz.

edit: 3200 isn't entirely stable either. In the limited tests I've done with HCI Memtest, it doesn't throw out any errors (using default core clocks just in case), but eventually threw a BSOD with a kernel_security_check_failure stop code. Memory controller dun like this setup Q_Q

Latency is higher since I've set UMA
Here are speeds with ram at 3200 (unstable)


and here with ram at 3066 (havent had a problem thus far)


----------



## Jpmboy

Quote:


> Originally Posted by *Alexium*
> 
> Interesting, thanks a lot for the explanation. Do you happen to know the formulas for setting other timings properly? Secondary / tertiary timings? I know my XMP has some seriously broken values. I fixed them ,more or less (with the help of knowledgeable people), but still not sure if it's all correct now.
> I have not been able to POST my 2x8 GB 3200 Hynix kit at 3200, and I would love to...


there's just a few others that are simple like RAS. eg, FAW can be set as low as 4x RRD. things like tREFI can be increased significantly (lowering can cause a refresh before all dram ops are completed, reducing efficiency)... 2x Auto is safe. The issue is charge decay. Sometimes you can use "suspend to ram" to test tREFI at very high settings.
There is "arithmetic" in the jedec standard.









JESD79-41.pdf 3864k .pdf file


----------



## mongoled

Has anyone devised a method in which we can determine if poor memory overclocking is attributed to the CPU memory controller or to the actual RAM chips ?

Ive got a F4-3600C15D-16GTZ kt and seems pretty crappy, im using the stilt's 3200 safe memory timings and am struggling to get them stable in prime95 custom 14000mb.

Ive tried with different cpu, soc, ram voltages, etc but still not getting them stable.

They need 1.4v just for prime95 to make it into at least 10-15 minutes of the test.

From what ive understood my motherboard has not got VTT adjustments though still trying to confirm if DRAM CH_A/CH_B VREF is the same thing ....


----------



## mus1mus

Did you consider running high RAM clocks with low CPU clock to determine if CPU instability is at play?


----------



## mongoled

Quote:


> Originally Posted by *mus1mus*
> 
> Did you consider running high RAM clocks with low CPU clock to determine if CPU instability is at play?


Im putting your suggestion into play but with a little variation.

Ive knocked the CPU to 3Ghz, but RAM ive left with the stilt's safe timings.

Will report back how it gets on .........


----------



## Performer81

Quote:


> Originally Posted by *Alexium*
> 
> I have not been able to POST my 2x8 GB 3200 Hynix kit at 3200, and I would love to...


Try these Timings. XMP Profile in Bios and then set these timings manually. Vdimm and Soc auto.:

http://abload.de/image.php?img=timingszyrrp.jpg

Works perfect on my GT7. On Gigabyte Gaming 5 even cas 16 worked.


----------



## Alexium

Quote:


> Originally Posted by *Performer81*
> 
> Works perfect on my GT7. On Gigabyte Gaming 5 even cas 16 worked.


Thanks!
Could you please also run a program called "Ryzen timing checker", and post a screenshot? It will show all the secondary and tertiary timings. Might be important.


----------



## Performer81

Quote:


> Originally Posted by *Alexium*
> 
> Thanks!
> Could you please also run a program called "Ryzen timing checker", and post a screenshot? It will show all the secondary and tertiary timings. Might be important.


Hope it helps:

http://abload.de/image.php?img=rtc9isq8.jpg

SOc is at 1,094 and vdimm at ~ 1,34-1,35 according to hwinfo. Its the vengeance 3200LPX 16GB Hynix Kit


----------



## Alexium

Quote:


> Originally Posted by *Performer81*
> 
> Hope it helps:


Thanks a lot! Some of your sub-timings are set higher than mine, so mine might be too tight. Going to give the elusive 3200 objective another try!


----------



## Worldwin

[email protected] --SOC 1.13 ---BIOS:F6--HCl--1600%---F4-3200c-8GTZ


----------



## 1TM1

There's something about memory training...
Several weeks ago I got 3333-16 on 32GB Hynix M-die 4x8, all stable to 800%+ tested more than once. 1.05V SOC and 1.45V DRAM. Setting survived the warm reboot (power cable not pulled) so I was all excited and ready to post here then I tested a cold reboot (pulled the power cable) and memory would not POST at 3333-16 or 3333-18 anymore. It worked at older 3200-16 stable settings but no more 3333.
I waited a few weeks, then loaded older 3333 setting (all timings on auto making it 3333-18) with 1.1V SOC and 1.435V DRAM. That worked. Memory got re-trained. After that training 3333-16 with 1.05V and 1.45V works again.

Two points:
1) verify memory stability by a cold (pull the plug) boot. Just Memtest86 or HCImemtest alone is not enough. Must do a cold boot POST. I think 400%, cold POST, 400% should be enough. 100 cold 400 cold 400 better.
2) while I waited Aida64 expired so I reverted to Intel Latency Checker, Windows System Tool and 7-Zip command mode to compare RAM speed without expiring.

I use commands below as a batch file to produce quick and consistent numbers about effects of settings on memory speed and overall computer performance (set advanced shortcut properties for this batch file to run as administrator)

@echo off
mlc_avx512.exe --idle_latency
mlc_avx512.exe --peak_bandwidth
winsat mem
cd C:\Program Files\7-Zip\
7z b
pause

All I do is press a keyboard shortcut (also set in shortcut properties) and it runs. output looks like this:
 timings right now are 
(1800X at 4000, C6H with 9945, F4-3200C16D-16GTZB)

update: Ah yes, @Raja talked about this memory training six months ago. http://www.overclock.net/t/1624603/rog-crosshair-vi-overclocking-thread/2540#post_25932285


----------



## mongoled

Quote:


> Originally Posted by *mus1mus*
> 
> Did you consider running high RAM clocks with low CPU clock to determine if CPU instability is at play?


For the Stilt's 3200mhz safe timings to have some stability (+3hrs) prime95 custom 14000mb the CPU frequency has to be no higher than 3.0ghz across all cores.

Any higher than 3.0Ghz then prime will fail.

Its not possible for me to post reliably with memory frequency higher than 3333mhz, we have no vram boot voltage on the MSI X370 titanium motherboards ......

So this looks to be a piss poor memory controller on the CPU? Even by increasing the SOC voltage, no stability is gained.

The only way to gain some 'stability' is to push more than 1.45v through the RAM but even then it wont run for a few hours.

And we also dont have ddr vtt adjustments


----------



## YaGit(TM)

For those having cold boot issues (even though stable on stress testing)

try setting your DRAM boot voltage(if available) to same or a bit lower on your actual volt.

I set mine @ 1.39v DRAM boot voltage
but my oc'd ram is actually running @ 1.438v

not sure will apply to others but i have not experience cold boot issues since...


----------



## 010101

How safe is it to raise DRAM voltage?


----------



## SaccoSVD

1.4V is considered safe. 1.45V and 1.5V too but don't mark my words.

I think generally you don't need more than 1.4V but I'm not a RAM expert.


----------



## SlushPuppy007

Quote:


> Originally Posted by *010101*
> 
> How safe is it to raise DRAM voltage?


What is the model of the RAM?


----------



## 010101

https://gskill.com/en/product/f4-3200c16d-32gtzsw

Hynix m-die dual rank.... i have a x370 taichi and is only stable to 2800mhz....
2933 unstable... and 3200 dont boot just one time boot and never more














@2933


@2800


----------



## SlushPuppy007

For that kit I'd say 1.4v is safe for 24/7 operation.

currently I'm running my B-Die Kit @ 1.45v (BIOS) for stability testing, actual reported voltage is 1.48 v in windows.

https://www.gskill.com/en/product/f4-4266c19d-16gtzr

This is probably too high for comfort...


----------



## 010101

Quote:


> Originally Posted by *SlushPuppy007*
> 
> For that kit I'd say 1.4v is safe for 24/7 operation.
> 
> currently I'm running my B-Die Kit @ 1.45v (BIOS) for stability testing, actual reported voltage is 1.48 v in windows.
> 
> https://www.gskill.com/en/product/f4-4266c19d-16gtzr
> 
> This is probably too high for comfort...


I try 1.4 but, is not it worth to sell this kit? and buy a samsung b die kit?


----------



## SlushPuppy007

Quote:


> Originally Posted by *010101*
> 
> I try 1.4 but, is not it worth to sell this kit? and buy a samsung b die kit?


Wait for the next AGESA 1.0.0.7 update, and test for improvement.

If you are still not happy with the performance, then you can sell?


----------



## 010101

Yes, that makes sense. Thank you!


----------



## crakej

Quote:


> Originally Posted by *SlushPuppy007*
> 
> For that kit I'd say 1.4v is safe for 24/7 operation.
> 
> currently I'm running my B-Die Kit @ 1.45v (BIOS) for stability testing, actual reported voltage is 1.48 v in windows.
> 
> https://www.gskill.com/en/product/f4-4266c19d-16gtzr
> 
> This is probably too high for comfort...


b-die can run safely up to 1.5v - but you shouldn't need that much...


----------



## 010101

Well why the last bios my kit of hynix m die dual rank f4-3200c16d-32gtzsw Is seem to be stable whyt 1.40 vdram at 2933.... on taichi... i need more test and test low timinings


----------



## happyluckbox

This might sound like a dumb question, but where is the IMC located for ryzen threadripper setups? Is it on the cpu itself or the x399 motherboard?


----------



## CriticalOne

I am using the Corsair Vengeance LPX 3200 2x8GB kit and I want to adjust my memory subtimings from the ones above. What do you all suggest I do?


----------



## WarpenN1

I'm certain that It is in the die itself or therefore 2 dual channel memory controllers giving a quad channel memory support


----------



## ssateneth

Quote:


> Originally Posted by *happyluckbox*
> 
> This might sound like a dumb question, but where is the IMC located for ryzen threadripper setups? Is it on the cpu itself or the x399 motherboard?


On the CPU. 2 channels per die. Threadripper has 2 active dies so 2 + 2 = 4 channels. Disabling a full die through BIOS may reduce usable RAM slots / channels, I have yet to check that myself.


----------



## Jaju123

Got myself a kit of F4-3600C15D-16GTZ, ryzen 1700, and MSI x370 gaming carbon pro. Having issues booting anything above 3200mhz or below 3200 cl14. Does anyone have any tips I can try off the bat? Haven't had much time to tweak. The AMP profile of 3600 just boot loops over and over until it resets, same for anything higher than 3200. All I've done is set dram voltage to 1.38 and soc voltage to 1.2. Before that I couldn't even boot 3200. Any help appreciated.


----------



## happyluckbox

Use cldo_vddp to get above 3200


----------



## seansplayin

this is what I'm using and I have the same memory assuming you have version 5.39

http://www.overclock.net/t/1624603/rog-crosshair-vi-overclocking-thread/27150#post_26350843


----------



## ssateneth

I can run multiple hour GSAT on my 1950x with 4x16GB sam b-die 3200MHz 14-14-14-34 1T 1.35v with no error, but still occasionally get BSOD with stop errors like KERNEL_SECURITY_CHECK_FAILURE, UNEXPECTED_KERNEL_MODE_TRAP, and IRQL_NOT_LESS_OR_EQUAL just idling. 3066 rarely gets BSOD overnight too. 2933 is stable. Anything I can do to make the higher speeds stable? MSI x399 board.


----------



## mus1mus

Quote:


> Originally Posted by *ssateneth*
> 
> I can run multiple hour GSAT on my 1950x with 4x16GB sam b-die 3200MHz 14-14-14-34 1T 1.35v with no error, but still occasionally get BSOD with stop errors like KERNEL_SECURITY_CHECK_FAILURE, UNEXPECTED_KERNEL_MODE_TRAP, and IRQL_NOT_LESS_OR_EQUAL just idling. 3066 rarely gets BSOD overnight too. 2933 is stable. Anything I can do to make the higher speeds stable? MSI x399 board.


Try adding SOC Voltage.
Tune CLDO_VDDP
Add a bit of VDDP - best to match it or slightly lower than VSOC.


----------



## WarpenN1

I have question, why does my RAMs become unstable and start to throw errors in memtest when I raise my DRAM voltage from/over 1.35v to 1.4-1.55v







it's kind of hard to overclock my ram over their rated speed because I'm tied to 1.35v as about max stable voltage

C6H and tridentz 2*16GB 3200cl14 here :/

Can anyone shed some light to this problem? If for example I'm at stable memory settings (at least 500% coverage in memtest) with 1.35 voltage. And only thing that I change is increase my DRAM voltage to something like 1.4 or 1.5. (It gets increasingly unstable as up I go with voltage)







1.55v Is instantaneous errors is memtest with same settings as I was stable with 1.35v :/


----------



## happyluckbox

So I'd really like to somehow get 3200 mhz stable on my threadripper 1950x system. Currently, I'm running 128gbs of gskill tridentz currently at 3060mhz 14-14-14-34 2T.
I know its already really good for 128gbs of ram, but I feel like getting to 3200mhz would be a real accomplishment. I've been able to post using cldo_vddp at 950mv, but it's really unstable. (instantly drops worker threads in p95) Any ideas on what is the best voltage I can increase to target the IMC (im guessing this is the weakpoint?) Also, as I understand it, the IMC is built into threadripper and not the motherboard correct? Or is this feat simply not possible, and if that's the case, will future agesa updates help, or is the IMC hardware simply being stressed to the maximum?


----------



## Keith Myers

Probably something to do with the increased voltage increasing the amplitude of the standing waves on all the data transmission lines which decreases the integrity of the timing pulses. You would have to change the ProcODT or other memory resistance to compensate.


----------



## Keith Myers

If Threadripper BIOS' follow the trajectory of Ryzen motherboards with their AGESA updates, memory compatibility and memory speeds should improve with evolution. Consensus opinion that every chip's IMC is a little better/worse than other samples so can affect the speeds the IMC will allow with stability. Just read through all the memory threads for nuggets of information on how others are able to achieve higher speeds with the large memory installations.


----------



## WarpenN1

Quote:


> Originally Posted by *Keith Myers*
> 
> Probably something to do with the increased voltage increasing the amplitude of the standing waves on all the data transmission lines which decreases the integrity of the timing pulses. You would have to change the ProcODT or other memory resistance to compensate.


Okay thanks! Should I try to increase or decrease resistances as going up in voltage?


----------



## Keith Myers

Quote:


> Originally Posted by *WarpenN1*
> 
> Okay thanks! Should I try to increase or decrease resistances as going up in voltage?


I believe you should up both/either/or ProcODT and CAD Bus lines in the memory section. Try 60 ohms in ProcODT and 30 ohms in the CAD Bus driving strength resistances. I don't think you need to go that high in memory voltage just for 3200 Mhz in the first place. Somewhere around 1.38-1.40V should be sufficient even with 32 Megs. Also Ryzen Timing Checker is your friend. I would start with the Stilt's Timing charts first.
Stilt's Timing Charts


----------



## WarpenN1

Quote:


> Originally Posted by *Keith Myers*
> 
> I believe you should up both/either/or ProcODT and CAD Bus lines in the memory section. Try 60 ohms in ProcODT and 30 ohms in the CAD Bus driving strength resistances. I don't think you need to go that high in memory voltage just for 3200 Mhz in the first place. Somewhere around 1.38-1.40V should be sufficient even with 32 Megs. Also Ryzen Timing Checker is your friend. I would start with the Stilt's Timing charts first.
> Stilt's Timing Charts


I'm trying to just straight out get 3333mhz stable now, I noticed that in many games like far cry 3 has awful big difference if I don't set affinity to use cores from one CCX (tested with RAM at 2800mhz) FPS difference is almost like 20-30FPS and that is in under 100FPS! so it's huge. Giving affinity to 4 cores (without SMT cores) gives in top of that about 5-15FPS... And total GPU usage increased from 40-70% to 70-100% with setting affinity to 4 real cores from one CCX! I wanna get max possible infinity fabric speeds with faster RAM so infinity fabric bottleneck would get smaller. GTA V is not really affected by infinity fabric because my GPU usage is almost all the time 99% but with some drops here and there probably caused by infinity fabric so probably cores can't communicate fast enough.

Here are my settings for 3333mhz


Spoiler: Warning: Spoiler!







procodt = 68.6ohm

Ram voltage = 1.4v

vddp = 0.9v

VDDSoC = 1.02v, LLC 3 (spiking to 1.05v)

vpp_mem Voltage = 2.56v

VTTDR voltage = 0.75v

RESTISTANCES

Clock Drive Strength = 40.0Ohm
Address / Command Drive Strength = 40.0Ohm
CS / ODT Drive Strength = 40.0Ohm
CKE Drive Strength = 60.0Ohm

I can run about 40-1hr prime95 BLEND test with these settings and I know if I change CKE drive strength to 40ohms from 60ohm blend test fails immediately

I think that CDS and address strength change from 32ohm to 40ohm and DRAM voltage change from 1.41 to 1.40 did not change a whole lot ( or I'm testing that change now, I bet that failure comes at about 1hr mark)

And I'm using prime95 blend first and verify that with memtest. In my use case, prime95 fails faster if RAM's are unstable.

EDIT: changing two first mem bus resitances from 32ohm to 40ohm and lowering dram from 1.41v to 1.4v allowed me to pass 1hr mark of blend, at least I'm going for the right direction. I think









Do CLDO_VDDP voltage do more than just resolve memory holes? Can right CLDO voltage lower the need of vcore?

EDIT: error was detected in about 1.55h mark now, testing with memtest little bit before changing resitance(s) and trying again just to get feel of it how stable memtest is. Lol this time around memtest caught error in like 5% of coverage have to figure out what's really is really bottlenecking RAM :/


----------



## Keith Myers

Well I am not a gamer so anything related to that is over my head. I see a couple of things that draw my attention. First is VTTDDR is disobeying the rule. It should be 1/2 Vddr. So with your Vddr set at 1.4V, VTTDDR should be at 0.7V NOT 0.75V.

The other one is that stability in higher memory clocks has been observed with setting Vddp to equal Vsoc or slightly less. That should be at ~ 1.0V with your Vsoc at 1.02V. You have it too low at 0.9V Gupsterg is the expert here.


----------



## happyluckbox

Do you guys think I would see any significant improvement returning my current Samsung b-die 128gb tridentz (rated at 3200mhz 15-15-15-35, but currently running at 3060mhz 14-14-14-30) for a 128gb kit that actually is rated to run at 14cas?

I'm thinking it's not really worth paying restocking fee of 10% just to try to get 128gb 14cas tridentZ when my kit already can run at 14cas. but maybe it would help me stabilize 3200mhz?


----------



## WarpenN1

Quote:


> Originally Posted by *Keith Myers*
> 
> Well I am not a gamer so anything related to that is over my head. I see a couple of things that draw my attention. First is VTTDDR is disobeying the rule. It should be 1/2 Vddr. So with your Vddr set at 1.4V, VTTDDR should be at 0.7V NOT 0.75V.
> 
> The other one is that stability in higher memory clocks has been observed with setting Vddp to equal Vsoc or slightly less. That should be at ~ 1.0V with your Vsoc at 1.02V. You have it too low at 0.9V Gupsterg is the expert here.


Hmmm then this is super weird but when I set my vttddr from 0.75v to 0.706v memtest fails immediately. I have DRAM voltage at 1.41 so 0.7062v (can't set it more precisely) should be about half :/

And with loosened timings 16-16-16-34-50 got me 200% coverage in memtest before fail compared 14-14-14-28-42 when it failed in couple of minutes.


----------



## ssateneth

Quote:


> Originally Posted by *mus1mus*
> 
> Try adding SOC Voltage.
> Tune CLDO_VDDP
> Add a bit of VDDP - best to match it or slightly lower than VSOC.


SoC I can play around with
CLDO_VDDP as well.

Not sure what VDDP is, MSI board may not have it.

But it seems ProcODT has a -big- influence. In an attempt to get 3200 andhgiher running, turns out 80 ohms and higher leads to 3 long beeps, automatic reboot, repeat 5 times, then it posts with RAM at default settings (Volts and CPU specific settings are still intact).

68.3 ohms though, 3200 posts right away, as does 3333. 3466 has -never- booted before, but now magically boots. It is a little problematic but I have it posting at 60 and 53 ohms (53 had problems POSTing but running GSAT now without issue, going on over an hour so far). I thought higher meant more supportive for overclocking but maybe for me its the reverse, kinda? I haven't tried any of the really low settings yet, but i've been following the rule that amd posted that higher settings may be more supportive.

So I guess dual rank single DIMM quad channel at 3333+ can be a thing, just have to fiddle with those specific stability settings. stressapptest on windows 10 bash shell hasn't thrown any errors yet (in fact it's never thrown an error yet on any setting since I get BSOD's instead, even if I run a full 4 hours of GSAT -W)

I'd love to get the full 3600 my kit is rated for, but testing each setting is very cumbersome as MSI x399 has very slow failure recovery (it could also be a threadripper thing too)


----------



## Keith Myers

Single rank, B-die is supposed to run best at 53 or 60. 4 sticks often need bumping to 68. Double rank is another story entirely. I think you can count on one hand and have fingers left over of the number of people that have 3600 Mhz running stable. 3200 should be a given and 3466 is quite doable as based on the commentary and posts in all the memory threads. The BIOS' across all platforms, Ryzen or Threadripper and all manufacturers seem to put 3600 in fantasy land. Until AGESA 1.0.7 drops and some wishful thinking I believe, 3600 will remain a pipedream for most.


----------



## Keith Myers

Quote:


> Originally Posted by *happyluckbox*
> 
> Do you guys think I would see any significant improvement returning my current Samsung b-die 128gb tridentz (rated at 3200mhz 15-15-15-35, but currently running at 3060mhz 14-14-14-30) for a 128gb kit that actually is rated to run at 14cas?
> 
> I'm thinking it's not really worth paying restocking fee of 10% just to try to get 128gb 14cas tridentZ when my kit already can run at 14cas. but maybe it would help me stabilize 3200mhz?


No, just the opposite in fact. The lesser amount of sticks installed, the greater likelihood of getting higher memory or stock rated clocks running. The less amount of work the IMC has to do, the better the results.


----------



## happyluckbox

Quote:


> Originally Posted by *Keith Myers*
> 
> No, just the opposite in fact. The lesser amount of sticks installed, the greater likelihood of getting higher memory or stock rated clocks running. The less amount of work the IMC has to do, the better the results.


I dont think you understood my question. I am already running a 128gb kit that was originally rated for 15cas 3200mhz. It ended up being samsung b die and I was able to tune it to be 14cas 3060mhz.

I am now wondering if I had originally purchased a 128gb kit that was rated for 14cas 3200mhz, if I would be able to achieve 14cas 3200mhz.


----------



## Keith Myers

Quote:


> Originally Posted by *happyluckbox*
> 
> I dont think you understood my question. I am already running a 128gb kit that was originally rated for 15cas 3200mhz. It ended up being samsung b die and I was able to tune it to be 14cas 3060mhz.
> 
> I am now wondering if I had originally purchased a 128gb kit that was rated for 14cas 3200mhz, if I would be able to achieve 14cas 3200mhz.


Yes, I did. I'm surprised that RAM rated at 15 CAS ended up being B-die. The rule of thumb as always been CAS 14 guaranteed to be B-die or any RAM rated at 3333 or greater is B-die. The B-die ram rated at 3200 or greater usually can be tightened up to CAS14. I think that is holding true even at the higher densities.


----------



## happyluckbox

Quote:


> Originally Posted by *Keith Myers*
> 
> Yes, I did. I'm surprised that RAM rated at 15 CAS ended up being B-die. The rule of thumb as always been CAS 14 guaranteed to be B-die or any RAM rated at 3333 or greater is B-die. The B-die ram rated at 3200 or greater usually can be tightened up to CAS14. I think that is holding true even at the higher densities.


So should I purchase the cas14 128gb kit, or just stick with my cas15 128gb kit? I really want to try and stabilize 3200mhz, and I wonder if the higher quality ram 14cas kit will allow me to reach it. I mean I have samsung b die already (lucked out i guess) So maybe its not worth the attempt. Also.... im out of my warranty/return period...


----------



## Keith Myers

Quote:


> Originally Posted by *happyluckbox*
> 
> So should I purchase the cas14 128gb kit, or just stick with my cas15 128gb kit? I really want to try and stabilize 3200mhz, and I wonder if the higher quality ram 14cas kit will allow me to reach it. I mean I have samsung b die already (lucked out i guess) So maybe its not worth the attempt. Also.... im out of my warranty/return period...


If you are out of your return period I would just stick with what you have. The CAS14 B-Die _SHOULD_ have been binned higher than the CAS15 sticks, so you might have reached higher clocks, but nothing is ever guaranteed. Unless you are able to sell your CAS15 stuff for a good price to offset the cost of the new CAS 14 128GB kit, I would just stick with what you have in my view.


----------



## WarpenN1

Quote:


> Originally Posted by *Keith Myers*
> 
> Well I am not a gamer so anything related to that is over my head. I see a couple of things that draw my attention. First is VTTDDR is disobeying the rule. It should be 1/2 Vddr. So with your Vddr set at 1.4V, VTTDDR should be at 0.7V NOT 0.75V.
> 
> The other one is that stability in higher memory clocks has been observed with setting Vddp to equal Vsoc or slightly less. That should be at ~ 1.0V with your Vsoc at 1.02V. You have it too low at 0.9V Gupsterg is the expert here.


Quote:


> Originally Posted by *WarpenN1*
> 
> Hmmm then this is super weird but when I set my vttddr from 0.75v to 0.706v memtest fails immediately. I have DRAM voltage at 1.41 so 0.7062v (can't set it more precisely) should be about half :/
> 
> And with loosened timings 16-16-16-34-50 got me 200% coverage in memtest before fail compared 14-14-14-28-42 when it failed in couple of minutes.


Bump from 0.9v vddp voltage to 1.0v helped quite a lot! Got 600% coverage without error compared to 200% with 3333mhz 16-16-16-34-50^^ Now i'm verifying it with prime95 if it catches any instability that memtest did not.

Gonna try getting 14-14-14-28-42 timings stable next week









But I don't understand why changing vttddr from 0.752v to 0.7062 (DRAM voltage 1.41v) makes RAMs very unstable


----------



## mongoled

Quote:


> Originally Posted by *Keith Myers*
> 
> Well I am not a gamer so anything related to that is over my head. I see a couple of things that draw my attention. First is VTTDDR is disobeying the rule. It should be 1/2 Vddr. So with your Vddr set at 1.4V, VTTDDR should be at 0.7V NOT 0.75V.
> 
> The other one is that stability in higher memory clocks has been observed with setting Vddp to equal Vsoc or slightly less snip........ .


Cheers for this bit of info, I hadn't come across this up till now! I require 1.45v for 3066mhz to be stable prime95 custom 14000mb stable +6 hrs.

Will test this when I get a chance


----------



## Keith Myers

Quote:


> Originally Posted by *WarpenN1*
> 
> Bump from 0.9v vddp voltage to 1.0v helped quite a lot! Got 600% coverage without error compared to 200% with 3333mhz 16-16-16-34-50^^ Now i'm verifying it with prime95 if it catches any instability that memtest did not.
> 
> Gonna try getting 14-14-14-28-42 timings stable next week
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But I don't understand why changing vttddr from 0.752v to 0.7062 (DRAM voltage 1.41v) makes RAMs very unstable


I don't know. Maybe that is just what your RAM needs. It IS operating well out of "design" spec so voltages and settings may not scale linearly from the JEDEC standard.


----------



## Nemesis158

Just did a sort of budged upgrade with room to grow, replaced my 3930k/RIVE with:
Ryzen 7 1700x
Asus Prime X370 Pro (bios is updated to latest release w/ agesa 1.0.0.6a)
1x16GB G.skill Ripjaws V 3200MHz

I ordered the ram because it was on sale at $130, and it was not until i received it that i realized I had ordered a single dimm 16GB instead of 2x8GB dimms. I didn't send it back though because i planned to get another 16GB for 32GB total at a later point.

this 16GB dimm is Dual rank Hynix M-die
3200MHz XMP Timings are 16-18-18-38. full timing list 16-18-18-18-36-56-6-8-39

Originally tried default XMP DOCP, no POST and board did not self-reset
Then tried Auto with 2933 and 2800MHz. no post or auto reset on 2933 but did auto reset on 2800mhz. I have not seen it auto-reset since

then i went back after reading a little and lowered the main timings on 3066 and put my SOC up to 1.1625. Posted and loaded windows fine and i have been using this as a base ever since:
16-17-17-17-37-55-6-8-35 soc1.1625v

Computer has been more stable with high ram usage than low ram usage, ive yet to run an actual stress test because i doubt any would pass.
Playing GTAV yeilds about 50% ram usage and no issues while in game, but regular web browsing or leaving the PC idle will randomly BSOD. common errors "Kernel Check Security Failure" and "Unexpected Kernel Mode trap"

tried raising tFAW from 35 closer to the XMP spec of 39 causes non-post (non-post at 37). lowering tFAW tRRDL and tRRDS seemed to help improve stability, currently at tFAW=34, tRRDS=5, tRRDL=7.
tried raising SoC voltage further. no apparent stability change between 1.1625-1.175v. SoC voltage 1.1825v+ causes non-post.

Trouble is i haven't really found a proper guide detailing what to try and where to go with the other subtimings. I would like to get to 3200mhz. given that I have gotten this far I think it is possible, but I dont know where to start with all these timings.

here are the timing readings from thaiphoon:








and here are my current timings as reported from Aida64:








and the xmp timings according to aida64









thanks for any and all help that can be provided


----------



## SlushPuppy007

Hi folks,

Running the following hardware:

1800X
ASRock X370 Taichi
G.Skill f4-4266c19d-16gtzr

I finally managed to get the following stable (48 Hours HCI):

No CPU Overclock (yet)

VDDCR_SOC = 1.10625v
VDDCR_SOC_LLC = Level 3
DRAM Voltage = 1.325v
VTT_DDR = 0.670v
VDDP = 0.980v
ProcODT = 60 ohm
CLDO_VDDP Voltage = 935mV

Gear Down Mode = on
Bank Group Swap = off
Bank Group Swap Alt = off



I'm happy with the above settings just to start gaming on my new build, but I would like to go for better.

The main problem I'm currently facing is as soon as Gear Down Mode is disabled and 1T enabled, my PC fails to boot for three tries, and then resets the RAM to default 2133MHz.

The closest I came to a successful boot is when I under-volt the IMC considerably, then the PC boots up to the BIOS screen, and then freezes right there.

I've tried numerous voltage combinations on the IMC and DRAM, but could not get it to boot to windows yet.

The Taichi does not have DRAM Boot Voltage like the CH6, do you recon this is why I'm unable to boot with GDM = off + 1T @ 3200MHz?

2933MHz with GDM =off + 1T boots just fine though.


----------



## Darkomax

Sharing my oc, Ryzen 5 1600, Gigabyte Gaming 3, KFA2(Galax) 3600C17 16GB



Anything higher or tighter would give me memtest errors.
Impressed by the performance gain from subtimings, i've seen 15% gain in some games.


----------



## happyluckbox

Hey guys, any tips on getting 4ghz stable on my setup? I tried upping my frequency from 3.9 to 3.925 then 3.95, then 3.975, and I didnt need to increase vcore at all! BUT going to 4.0 requires a massive leap in vcore from 1.368 to 1.41++ and even then its not quite stable. I'm starting to think its not vcore and some other voltage instead. Any ideas?


----------



## gupsterg

Quote:


> Originally Posted by *Keith Myers*
> 
> The other one is that stability in higher memory clocks has been observed with setting Vddp to equal Vsoc or slightly less. That should be at ~ 1.0V with your Vsoc at 1.02V. You have it too low at 0.9V Gupsterg is the expert here.


No expert







. Still learning lots and do not have the depth of knowledge or experience to have that moniker







. More of a viral poster of info, from a) testing b) picked up from others shares







.

I had issues stabilising a 3466MHz RAM profile on C6H with UEFI 1403 onwards. I then had to reassess settings. I then opted to lower VDDP. I and another prior to me deciding to do this, had seen that UEFI upto 99xx were ~900mV on VDDP and later ones ~975mV. It had not posed an issue for me on UEFI between 99xx and 1403, but the ones after it was.

When I got Ryzen at launch and noted VDDP probe point on C6H I asked The Stilt what it was, link. Here is a later dated post by The Stilt concerning it again, link.

CLDO_VDDP I found helped with moving memory holes. On one CPU sample that I did more testing then others I had. I noted lowering it moved the hole down the frequency range and upping it the other way. Another C6H owner also experienced this. If all CPUs behave this way I have no idea. I also noted if I used say excessively low CLDO_VDDP, so all RAM MHz between 2133MHz and 3466MHz would post, I'd have stability issues in OS. So excessively low was no good, so what must be used is what is right for target RAM MHz.

ProcODT was a tricky one to get right IMO. For example I started using 60Ω mainly with my F4-3200C14D-16GTZ. One day when testing a custom setup of P95 I had dropped threads. Changing to 53.3Ω resolved issues. Again we may find a profile passes Memtest/GSAT and other tests but another may highlight a shortcoming in settings.

Another tricky one was CAD Bus. I had opt'd for 30Ω on higher than 3333MHz:-

ClkDrvStren
AddrCmdDrvStren
CsOdtDrvStren
CkeDrvStren

I found SuperPi was sensitive to changes to this, I'd have runs which failed.

On the whole I have never ever done as much RAM tweaking as I am for Ryzen. Has been nice to get into to pick up tweaks, test methods, but can be time consuming and tedious







.

SOC on all CPUs I have had I also tune. I start with default and then start increasing as needed for target RAM MHz, usually I'm going for 3200MHz, 3333MHz or 3466MHz.

I have only used 1 Ryzen board, the C6H and one RAM kit more than the 3 I had at one time, F4-3200C14D-16GTZ. With this combo I have used 3x R7 1700 and 1x R7 1800X. I shall be testing a 2nd R7 1800X soon







.


----------



## Keith Myers

Gupsterg, thanks for chiming in. You are more an "expert" than I. And done 10X the amount of RAM testing. Furthermore, your links back to the Stilt comments finally shed light on just "what the heck" is Vddp anyway. My searches for it had turned up nothing but noise in other science branches. Lots of good info in your post.


----------



## gupsterg

No worries







.

The link for that post on VDDP has been in FAQ of my Ryzen Essential thread from beginning







.

It is hard to give a one post that covers all aspects, also becomes long







.

For example I found TR less forgiving on what ProcODT will be stable to post, it seems to not post as on wide range as it did on Ryzen. I'm currently using same dimms. Exhausting some DC testing before moving to QC. In a way makes it easier to know what is right.

By my above post I do not mean to detract any value from running Memtest/GSAT. I know early on in this thread I thought differently. Praz, Silent Scone and Jpmboy, had posted of the benefits of those tests and it has held true for me.

Again I can not say which of those is best to run, I have deemed both are worthy to use. Then as stated various other tests may show some more tweaking is needed. So the higher MHz/tighter RAM I went for the more varied testing I opted for.

In the C6H thread there are also posts were I noted RAM profile I deemed stable broke with increased ambient temps. So another factor to consider. Also there is posts in there where Memtest caught errors that other tests did not.


----------



## ssateneth

Well, I found a Ryzen sub tmiings video on youtube, and along with the Proc_ODT setting, I broke >100000MB/sec on read, write, and copy on AIDA64 memory benchmark. Preliminary testing shows its very stable. It's amazing the impact of secondary timings are on write (and copy) speeds are. Recommend tuning them yourself for significant write and copy boost. Read doesn't seem as impacted.

Video here https://www.youtube.com/watch?v=urVJR_qh-2c

Newest AIDA64 beta can't read my settings correctly.
MSI X399
1950X @ 4225MHz, 1.425v, SoC @ 0.95v
4x16GiB Samsung B-die @ 3333MHz, 1.5v. No CLDO_VDDP adjustment made. 53.3 ohm ProcODT
I know some of the timings are probably too low (violates some rules), but wanted to flesh out timings fields before I turned in for the night. have to say resetting CMOS for bad timings is a pain with this board, but at least it remembers OC profiles and applies them with keyboard shortcut on first POST after reset.

Wanted to add this was in NUMA mode. UMA brings reads to ~83K, writes to ~95K, and copy to ~92K, latency 82.4ns


----------



## Jackl2

Hi all,

Which memory kit would be best for the following specs:

AM4 platform (R7 1700)
Asus CH Hero 6
3200+ DDR4, 32GB in total (2x16GB), timing of 14 or 15


----------



## Jaju123

My timings so far. Stable at 1.35V with 1.1 SOC voltage on a MSI X370 carbon gaming pro. Might be able to get a bit tighter even if I give it a try. Using a G-Skill 3600 mhz CL15 2x8gb samsung B-die kit.


----------



## Jackl2

Quote:


> Originally Posted by *Jackl2*
> 
> Hi all,
> 
> Which memory kit would be best for the following specs:
> 
> AM4 platform (R7 1700)
> Asus CH Hero 6
> 3200+ DDR4, 32GB in total (2x16GB), timing of 14 or 15


Did some googling and all, here is the final list, would anyone recommend one over the other (and why)?

F4-3200C14D-32GTZ

F4-3200C15D-32GVK

F4-3400C16D-32GTZ

F4-3466C16D-32GTZ


----------



## happyluckbox

Go with the first one- pretty much guarantees samsung b


----------



## Jackl2

Quote:


> Originally Posted by *happyluckbox*
> 
> Go with the first one- pretty much guarantees samsung b


I believe they all do, I was asking for the best outcome in terms of frequency vs timings


----------



## happyluckbox

Either first or last then, - id just recommend going with the first tbh.

youll likely get it to 3333 mhz or maybe even 3466


----------



## chonas

Which of the following settings on GALAX HOF 3600 mhz RAM should I change to increase the speed of my RAM? It is stable at 3466 with:
tCL 16
tRCDRD 16
tRCDWR 16
tRP 16
tRAS 34
tRC 75
tRRD_S 6
tRRD_L 8
tFAW 27
tWTR_S 5
tWTR_L 10
tWR 18
tMAW.MAC 1
TrdrdScL 4
TwrwrScL 4
tRFC 900
tRFC2 600
tRFC4 300
tCWL 14
tRTP 10
Trdwr 10
Twrrd 3
TwrwrSc 3
TwrwrSd 8
TwrwrDd 8
TrdrdSc 1
TrdrdSd 6
TrdrdDd 6
tCKE 8
ProcODT Auto


----------



## miklkit

Quote:


> Originally Posted by *Jackl2*
> 
> Did some googling and all, here is the final list, would anyone recommend one over the other (and why)?
> 
> F4-3200C14D-32GTZ
> 
> F4-3200C15D-32GVK
> 
> F4-3400C16D-32GTZ
> 
> F4-3466C16D-32GTZ


I"m pretty sure the GVK one is Samsung E-die. I got F4-3200C16Q-16GVKB thinking it was B-die but it turned out to be E-die. Still got it to 3020 so far, but 3200 is not stable.


----------



## Jackl2

Quote:


> Originally Posted by *miklkit*
> 
> I"m pretty sure the GVK one is Samsung E-die. I got F4-3200C16Q-16GVKB thinking it was B-die but it turned out to be E-die. Still got it to 3020 so far, but 3200 is not stable.


According to this site: https://www.reddit.com/r/Amd/comments/649ay8/ram_collection_thread_please_post_your_ram/

all of those I listed are b-die...

Maybe the 16Q is an E-die? Where do you check?


----------



## Jackl2

Q is quad channel, D is dual channel


----------



## miklkit

I got the parts numbers off the package it came in and then there is Thaiphoon Burner.


----------



## Jackl2

hmmm the Agesa 1.0.0.6 it has me tempted to go with F4-3466C16D-32GTZ and just lower the timing from 16 to 14... that would be a big improvement over the F4-3200C14D-32GTZ IMO. What do you guys think. Its only about $20 difference.


----------



## Rockzilla182

I am running Corsair Vengeance LPX 2x8GB 3000MHz CL15 with Ryzen 5 1600 on the Gigabyte AB350-Gaming 3. I have XMP profile enabled and it is working, but what are good timings for this RAM if i wanted to plug it in manually?

XMP profile timings are 16-17-17-35-52, command rate 1T


----------



## Seahawkshunt

Quote:


> Originally Posted by *Rockzilla182*
> 
> I am running Corsair Vengeance LPX 2x8GB 3000MHz CL15 with Ryzen 5 1600 on the Gigabyte AB350-Gaming 3. I have XMP profile enabled and it is working, but what are good timings for this RAM if i wanted to plug it in manually?
> XMP profile timings are 16-17-17-35-52, command rate 1T


I own the same RAM kit I think. Mine is Corsair Vengeance LPX CMK16GX4M2B3000C15 (2x8) SK Hynix on a Asus x370-A motherboard. Here is the SPD information from Aida64 if you do not have it.


Spoiler: Warning: Spoiler!







I have had varying ranges of success with these timings and I am sure your mileage will vary also with a different BIOS/CPU and motherboard. I have to load XMP first then set speed and timings manually after that to have any success. For my PC the one XMP profile available with slightly lower timings resulted in the best results for me (Aida64). Good luck.


----------



## Nemesis158

Quote:


> Originally Posted by *Jackl2*
> 
> Q is quad channel, D is dual channel


S= single DIMM kit. D= dual DIMM kit. Q= quad DIMM kit.


----------



## gupsterg

Quote:


> Originally Posted by *Jackl2*
> 
> hmmm the Agesa 1.0.0.6 it has me tempted to go with F4-3466C16D-32GTZ and just lower the timing from 16 to 14... that would be a big improvement over the F4-3200C14D-32GTZ IMO. What do you guys think. Its only about $20 difference.


F4-3466C16D-32GTZ likely to be Hynix, as it has timings 16-18-18-38.

Your better off with F4-3200C14D-32GTZ, which will be Samsung B die.

Loose rule is where primary timings match is Samsung (ie 14-14-14).


----------



## Jackl2

Quote:


> Originally Posted by *gupsterg*
> 
> F4-3466C16D-32GTZ likely to be Hynix, as it has timings 16-18-18-38.
> 
> Your better off with F4-3200C14D-32GTZ, which will be Samsung B die.
> 
> Loose rule is where primary timings match is Samsung (ie 14-14-14).


According to this site: https://www.reddit.com/r/Amd/comments/62vp2g/clearing_up_any_samsung_bdie_confusion_eg_on/

The F4-3466C16D-16GTZ is Samsung B-Die, same as the 3200 CL 14. I really would doubt GSkill would use anything but B-Die on their 3200+ TridentZ kits.

The big question now is to go 4x8GB or 2x16GB, but am leaning towards 2x16GB and F4-3466C16D-32GTZ w/ Agesa 1.0.0.6 should get there without any or minor tweaking.


----------



## gupsterg

I said "likely" not "absolutely"







.

I can only give "pointers" not give "absolute" facts in this context







.

As always when "we" move from "official" to OC YMMV







.

As said before in PM, you need to assess and make a choice







.

As stated in this thread many a time getting say a Memtest/GSAT pass may not mean you get 0 issues in heavy usage/stability testing. See how many DR 3466MHz results there are here and other Ryzen threads and form a opinion on what you are likely to achieve







.

As said in PM after 3200MHz timings matter more than frequency







.

Look forward to results shares on your setup







.


----------



## Wndrbrh

Running 3200Mhz stable on a GB AX370 Gaming K7

[email protected] 1.1v---BIOS F6---HCI---400%---F4-3200C14D-16GFX


----------



## Jackl2

Quote:


> Originally Posted by *gupsterg*
> 
> I said "likely" not "absolutely"
> 
> 
> 
> 
> 
> 
> 
> .
> 
> I can only give "pointers" not give "absolute" facts in this context
> 
> 
> 
> 
> 
> 
> 
> .
> 
> As always when "we" move from "official" to OC YMMV
> 
> 
> 
> 
> 
> 
> 
> 
> .
> 
> As said before in PM, you need to assess and make a choice
> 
> 
> 
> 
> 
> 
> 
> .
> 
> As stated in this thread many a time getting say a Memtest/GSAT pass may not mean you get 0 issues in heavy usage/stability testing. See how many DR 3466MHz results there are here and other Ryzen threads and form a opinion on what you are likely to achieve
> 
> 
> 
> 
> 
> 
> 
> .
> 
> As said in PM after 3200MHz timings matter more than frequency
> 
> 
> 
> 
> 
> 
> 
> .
> 
> Look forward to results shares on your setup
> 
> 
> 
> 
> 
> 
> 
> .


Thanks, BTW I really appreciate all the help and answers.

Problem with all of this is that there is so much contradictory stuff out there on the Internet, makes everything just harder









We need 1 or two memory experts to just lay out the facts and have everyone follow them.

Most important point you mentioned is that after 3200+ timing matters more.


----------



## Nautilus

Guys, I'm near the Marietta/Atlanta Micro Center and need urgent Threadripper memory advice. There are limited stock of ram here, could you take a look and pick 3200Mhz 4x8GB ram for me? I don't want to end up with incompatible ram and having to run it 2133 or 2400Mhz only.

Could you look it up for me? --> http://www.microcenter.com

I haven't decided on the mobo yet. Best memory compatibility could be a defining factor.


----------



## Trender07

Guys you think this is stable?


----------



## happyluckbox

What pr
Quote:


> Originally Posted by *Trender07*
> 
> Guys you think this is stable?


What mem stress test prog is that?


----------



## boredgunner

Quote:


> Originally Posted by *happyluckbox*
> 
> What pr
> What mem stress test prog is that?


HCI MemTest.


----------



## jearly410

delete


----------



## jearly410

Quote:


> Originally Posted by *Trender07*
> 
> Guys you think this is stable?


My rule of thumb is any error means instability


----------



## Ouji

Asus PRIME-X370 Pro

[email protected] 1.2v---BIOS 0902---HCI---1100%--BLS8G4D240FSC


----------



## Rockzilla182

Gigabyte AB350-Gaming 3 Mobo

[email protected] 1.1v---BIOS F7---Stressapptest---1 Hour--CMK16GX4M2B3000C15


----------



## wodey

G.SKILL Ripjaws V Series 8GB 288-Pin DDR4 SDRAM DDR4 2400 (PC4 19200) Intel X299 / Z270 / Z170 / X99 Platform Desktop Memory Model F4-2400C17S-8GVR
DDR4 2400 (PC4 19200)
Timing 17-17-17-39
CAS Latency 17
Voltage 1.2V
This was the cheapest at the time for 8gb single stick
https://www.newegg.com/Product/Product.aspx?Item=N82E16820232601

All I did was manually set the cas latency and then the other timings were filled in. Ram training? I believe these were Spectek chips when I ran the program to identify memory. I don't see much information about these.

It's at 1.3v and memtest was fine.



Tried to do 3200 with 1.35v with the automatic timings but windows crashed.

Should I just go back to 2400 and the lower timings?


----------



## Shiftstealth

Has anyone heard of B-Die not hitting 3200Mhz stable?

I bought Flare X for my 1700X, and X370 GT7. SOC is at 1.15,RAM is at 1.45 but i can't get 3200 Stable. When i set 3200 16-18-18-18-40 it boots, but all 8 cores go to 550Mhz. 3200 14-14-14-14-34 refuses to boot.


----------



## PriestOfSin

Quote:


> Originally Posted by *Shiftstealth*
> 
> Has anyone heard of B-Die not hitting 3200Mhz stable?
> 
> I bought Flare X for my 1700X, and X370 GT7. SOC is at 1.15,RAM is at 1.45 but i can't get 3200 Stable. When i set 3200 16-18-18-18-40 it boots, but all 8 cores go to 550Mhz. 3200 14-14-14-14-34 refuses to boot.


That's bizarre. You're certain it's B-Die? my G.Skill 3200 @ 14 was so simple I just set the XMP in the bios. Mine is " F4-3200C14D-16GTZKW ", which did you buy?

Perhaps it's a problem with the bios?


----------



## Shiftstealth

Quote:


> Originally Posted by *PriestOfSin*
> 
> That's bizarre. You're certain it's B-Die? my G.Skill 3200 @ 14 was so simple I just set the XMP in the bios. Mine is " F4-3200C14D-16GTZKW ", which did you buy?
> 
> Perhaps it's a problem with the bios?


Fairly certain. I bought this kit:
https://www.newegg.com/Product/Product.aspx?Item=N82E16820232530&cm_re=flare_x-_-20-232-530-_-Product

I wish mine was that simple


----------



## PriestOfSin

Quote:


> Originally Posted by *Shiftstealth*
> 
> Fairly certain. I bought this kit:
> https://www.newegg.com/Product/Product.aspx?Item=N82E16820232530&cm_re=flare_x-_-20-232-530-_-Product
> 
> I wish mine was that simple


Well crap. Yep, that's B-Die for sure. Are you sure you're on the latest bios for your board? There was a bios update for it on 9-19, looks like.


----------



## chew*

Not enough room on screen for info and 32 threads so whatever......nor do I care enough to actually open 32 instances.



And since this has been debated to no end.........imagine that I tuned prime before I ran memtest which is easily noted by system date


----------



## happyluckbox

Quote:


> Originally Posted by *Shiftstealth*
> 
> Fairly certain. I bought this kit:
> https://www.newegg.com/Product/Product.aspx?Item=N82E16820232530&cm_re=flare_x-_-20-232-530-_-Product
> 
> I wish mine was that simple


Run thaiphoon burner on it. see if its really b -die. You shouldnt be having problems


----------



## Shiftstealth

Quote:


> Originally Posted by *happyluckbox*
> 
> Run thaiphoon burner on it. see if its really b -die. You shouldnt be having problems


Do you have a good mirror? I tried to download it, but it detects a virus.


----------



## happyluckbox

Quote:


> Originally Posted by *Shiftstealth*
> 
> Do you have a good mirror? I tried to download it, but it detects a virus.


I think it gave me that notification too when I first dled it. Pretty sure it was a fake positive, I don't have the link anymore though.


----------



## Shiftstealth

Quote:


> Originally Posted by *happyluckbox*
> 
> I think it gave me that notification too when I first dled it. Pretty sure it was a fake positive, I don't have the link anymore though.




It looks like samsung to me. Looks like its B-Die


----------



## Performer81

Did you try the 3200MHZ manually or with XMP Profile? Try XMP and everything else at AUTO.
Maybe its really the Board and it does not seem to be very memory friendly. Had the Gigabyte Gaming 5 and the Biostar X370GT7 and to reach 3200MHZ was much easier on the Gigabyte which also had no problems with memory training reboots. Hell i even reached 3333 on the Gigabyte with cheap Hynix which was amazing, I regret that i sold it.


----------



## Shiftstealth

Quote:


> Originally Posted by *Performer81*
> 
> Did you try the 3200MHZ manually or with XMP Profile? Try XMP and everything else at AUTO.
> Maybe its really the Board and it does not seem to be very memory friendly. Had the Gigabyte Gaming 5 and the Biostar X370GT7 and to reach 3200MHZ was much easier on the Gigabyte which also had no problems with memory training reboots. Hell i even reached 3333 on the Gigabyte with cheap Hynix which was amazing, I regret that i sold it.


Apparently my X370 GT7 has a SOC switching frequency setting which may have fixed everything. I upped it to 450Khz from auto, and now it is testing stability at 3200MhzCL14. I'm not sure what the deal is with this setting i've tried a quick google search which yields nothing.


----------



## PriestOfSin

Quote:


> Originally Posted by *Shiftstealth*
> 
> Apparently my X370 GT7 has a SOC switching frequency setting which may have fixed everything. I upped it to 450Khz from auto, and now it is testing stability at 3200MhzCL14. I'm not sure what the deal is with this setting i've tried a quick google search which yields nothing.


I wonder if other boards have that issue? Glad you got it worked out though!


----------



## miklkit

Huh! I bailed on the 919 bios because of the 0.5ghz bug in it plus some sensors quit working.

I have no idea what that SOC switching frequency does so never touched it. Gotta touch it now.


----------



## chew*

Quote:


> Originally Posted by *Shiftstealth*
> 
> Apparently my X370 GT7 has a SOC switching frequency setting which may have fixed everything. I upped it to 450Khz from auto, and now it is testing stability at 3200MhzCL14. I'm not sure what the deal is with this setting i've tried a quick google search which yields nothing.


Default vcore on gt7 is 300k

Default soc on gt7 is 400k

Just some fyi.


----------



## Performer81

Soc switching frequency to 450 does nothing for me.


----------



## miklkit

It doesn't seem to do anything on the 623 bios, but have not tried the 919 bios yet.

One thing is that I'm doing some video encoding and it seems slightly smoother now.


----------



## miklkit

In bios 919 it is a little better now. At least the sensors are working again.


----------



## Shiftstealth

Quote:


> Originally Posted by *miklkit*
> 
> Huh! I bailed on the 919 bios because of the 0.5ghz bug in it plus some sensors quit working.
> 
> I have no idea what that SOC switching frequency does so never touched it. Gotta touch it now.


What is the .5Ghz bug? I've booted to that a few times, and thought it was instability.


----------



## miklkit

Dunno. When I updated to the 919 bios I got it for the first time. By playing with voltages I managed to upgrade it to the 1.5ghz bug. That was where I bailed on 919 and went back to 623 which is on bios1.

I'm back on 919 now after bumping the switching frequency and bumping up the cpu volts. It might even be stable enough for everyday use. Maybe.


----------



## Shiftstealth

Quote:


> Originally Posted by *miklkit*
> 
> Dunno. When I updated to the 919 bios I got it for the first time. By playing with voltages I managed to upgrade it to the 1.5ghz bug. That was where I bailed on 919 and went back to 623 which is on bios1.
> 
> I'm back on 919 now after bumping the switching frequency and bumping up the cpu volts. It might even be stable enough for everyday use. Maybe.


I found on google that if you get the .5ghz bug to fully shut down, and restart and it should go away. I'm not at home to test it though.


----------



## 336613f

Ryzen 3 1200 @ 3.7ghz with max voltage currently at 1.308 allowing it to drop when needed.

Corsair Vengeance LPX 2400 ram 16-16-16-39 1.2 voltage is the stock but I am at:
2800 16-17-16-38 1T with voltage still 1.2

https://valid.x86.fr/exedhf Cpu-Z just to show validation on previous statements.

Currently running 3 instances of MemTest at 2gb ram each as there was 2gb of the 8gb in use for system(new to this testing so apologize if I'm doing this wrong)
currently at 30% on all three runs with 0 errors.

Motherboard is the Asus Prime Plus B350 with a recently flashed version of 0902. Despite a lot of conflicting reviews I have always prefered Asus for motherboards and most of the negative reviews seemed to be before bios updates happened or just general lack of knowledge.

Previous knowledge involves lots of custom builds, lots of trial and error, had a 8350 before able to run at 5ghz using just an h60 and stable(verified on site). 24/7 use was 4.5ghz on the H60 and still managed to undervolt below stock stable.

Any other questions I am happy to answer to the best of my ability.

(it would seem that although timings can be a bit tighter the corsair vengeance lpx 2400 ram is very overclock friendly)


----------



## miklkit

Quote:


> Originally Posted by *Shiftstealth*
> 
> I found on google that if you get the .5ghz bug to fully shut down, and restart and it should go away. I'm not at home to test it though.


Once it went away it never came back. It is currently at 1.4v cpu and 1.137 SOC and is still not stable. It is looking like the memory is wobbly but I don't know what else to change besides just bumping up the SOC.

EDIT: More SOC is stabilizing it. While the overall voltages are higher the cpu only went up 1C while the vrm went down 3C.


----------



## Trender07

Any of you had L1 cache error on HWInfo ?


----------



## miklkit

That means that your system is very unstable.


----------



## SaccoSVD

Does anyone uses a 64Gb 3200Mhz corsair dominator kit?

CMD64GX4M4C3200C16

Can I get the exact timings/subtimings for that kit please?


----------



## poah

Can't seem to overclock the CPU using bios, goes straight into a black screen but it will O/C with Ryzen master which I have set to 3.7 @ 1.25V for video editing but standard for everything else. Board is an MSI Tomahawk

[email protected] 1.1v---BIOS 1.8---HCI---362%---CMK16GX4M2A2400C14


----------



## sbrigo

Hi guys,
can you help me to use my memory at 3,200 Mhz?

MOBO Asus Prime x370
latest BIOS
DDR4 FlareX
F4-3200C14-8GFX

installed in slot #2 and #4

I'm loosing hopes


----------



## crakej

Quote:


> Originally Posted by *sbrigo*
> 
> Hi guys,
> can you help me to use my memory at 3,200 Mhz?
> 
> MOBO Asus Prime x370
> latest BIOS
> DDR4 FlareX
> F4-3200C14-8GFX
> 
> installed in slot #2 and #4
> 
> I'm loosing hopes


You'll prob get more help here http://www.overclock.net/t/1626011/my-experience-with-the-asus-prime-x370-pro/5050


----------



## Worldwin

One thing i notice while using GSAT is that my AMD display driver keeps crashing, even when just using XMP. I am guessing i am running out of memory as i have it set to 14500 leaving pretty much no room for background tasks.


----------



## Silent Scone

Quote:


> Originally Posted by *Worldwin*
> 
> One thing i notice while using GSAT is that my AMD display driver keeps crashing, even when just using XMP. I am guessing i am running out of memory as i have it set to 14500 leaving pretty much no room for background tasks.


You want to be assigning 85-90% of what is available, then ideally not use the machine till the test has completed.


----------



## patthehat

Hey, I am reporting in with a 2933CL14 @ 1.4 V stable G.Skill Aegis 3000CL16 2x8GB kit (F4-3000C16-8GISB) on a MSI X370 Gaming Plus with a Ryzen 5 1600 (3.8 GHz @ 1.34 V). I am wondering whether I picked the right balance of timings and speed, and if not, how I should try increasing it. I tried TheStilt's 3200CL16 Hynix AFR and MFR settings already but sadly couldn't get it to POST. Can I somehow see which dies I got?

Below are my current fully stable setings.



Thanks in advance for any input!


----------



## thigobr

[email protected] 0.950v---BIOS 0902---HCI---1000%---F4-3200C14-8GTZ



@patthehat Thaiphoon Burner can sometimes extract information about the ICs used on the module:

http://www.softnology.biz/files.html


----------



## Worldwin

Quote:


> Originally Posted by *Silent Scone*
> 
> You want to be assigning 85-90% of what is available, then ideally not use the machine till the test has completed.


Yea when i set it to 14500 only 300mb avail vs 14300 where ~500mb avail.

Anyhow my ST drawcall for DX11 went from 1.68m @ XMP to 1.76m tightening timings @ 3200. Since im not done im hoping to hit 1.8m.


----------



## ssateneth

So a little thing I found with my particular setup.

Tcwl and Trdwr subtimings are influenced by the other. If I set my Trdwr timing to 6, I cannot set Tcwl any lower than the default timing of 14. On the other side of the fence, if I set Tcwl to 10 (Can't set to 9, it self-corrects to 10 for me), the lowest I can set Trdwr to is 9.

The latter increases copy speeds marginally compared to the former.

RAM used is in my sig. Samsung B-die. I don't think the geardown mode is correctly managed on my MSI board; If I set GDM to disabled, I should be able to set command rate to 1, but it auto-configures to 2 on it's own. Probably losing some performance there, otherwise I could likely get CAS to 13. Feel free to steal timings. I have not yet found the lowest Trfc can go, and Tras and Trc violates some rules still so I won't go lower than that. Anyways, heres the timings I managed on 3200. I'll work on 3333 next but it's hard to get stable; The RAM itself is rock solid, but random BSOD's when not putting a load on the PC plague this build.

edit: tRFC got misconfigured, correcting it now. also temporarily on stock CPU speeds to see if I can fish out some BSOD's


----------



## chew*

Twcl should be equal to or 1 less than CL. Ryzen appears not to like odd twcl.

Of course you can break this rule but stability means nothing if performance is lost.

Tfaw rule is trrds multiplied by 4+0-8.
Your at 12 when minimum should be 16.

Many seem to focus solely on stability and speed but seldom focus on how it impacts performance.

Aida means very little realworld wise tbh.

My system does not BSOD FYI. I can't imagine why


----------



## sandysuk

Quote:


> Originally Posted by *ssateneth*
> 
> I don't think the geardown mode is correctly managed on my MSI board; If I set GDM to disabled, I should be able to set command rate to 1, but it auto-configures to 2 on it's own.


Quirky BIOS, set CMD to Auto, reboot, then set it to 1 and it will take. same with the tcwl, set another figure reboot the set what you want and it will take.

Great bandwidth numbers on 3200, I'm not close with 3333, 3333 is fine for me perhaps as I am not so aggressive my Aida numbers are R:94 w:98 c:93 l:62, I have to run 3466 to get close to you, both are stable HCI memtest into the 1000s, prime for a day, 3466 struggles with cold boot. ~ 30% success rate can't seem to tune it out.

I notice you are on 1.62, what does it bring SSD Raid there yet, I'm still on official 1.5?


----------



## ssateneth

Quote:


> Originally Posted by *sandysuk*
> 
> Quirky BIOS, set CMD to Auto, reboot, then set it to 1 and it will take. same with the tcwl, set another figure reboot the set what you want and it will take.
> 
> Great bandwidth numbers on 3200, I'm not close with 3333, 3333 is fine for me perhaps as I am not so aggressive my Aida numbers are R:94 w:98 c:93 l:62, I have to run 3466 to get close to you, both are stable HCI memtest into the 1000s, prime for a day, 3466 struggles with cold boot. ~ 30% success rate can't seem to tune it out.
> 
> I notice you are on 1.62, what does it bring SSD Raid there yet, I'm still on official 1.5?


Thanks for pointing out how to set a stuck setting. I got GDM disabled, 1T command rate, and CAS latency down to 13. AIDA memory latency is down to 61.1ns, but i'll likely switch back to UA (some of the stuff I do benefits more from UMA than NUMA). I'll run HCI maybe overnight.

I haven't touched RAID in a long time (last array was a 6 drive RAID10 on mechanical drives). Reasons being I don't want to risk data loss on a RAID0 due to 1 drive failing. Don't want to spend a lot on extra drives either, and lastly prevents just pulling out the drive and plopping it in a different system and having access to the data (usually need the same motherboard type to use RAID created by BIOS). I've been trying newer revisions anyways to try to aid in memory stuff obviously. 1.63 is available but recommend not using it since it has a bug where any ram speed other than 2133 causes about 30 seconds of POST beeping until it continues the POST process and successfully booting. Makes it very hard to tweak settings in a timely manner.

Just wanted to reiterate 2933 is rock solid. Still working the bugs out of 3200. 3333 is really hard (even at stock timings and CPU), 3466 I can only sometimes get to POST.


----------



## chew*

You happen to have multiple vgas installed in that system?

If so stick only 1 in then start from scratch dealing with your bsods if they even exist after.

If only 1 vga you have other issues.


----------



## ssateneth

Quote:


> Originally Posted by *chew**
> 
> You happen to have multiple vgas installed in that system?
> 
> If so stick only 1 in then start from scratch dealing with your bsods if they even exist after.
> 
> If only 1 vga you have other issues.


Only 1 VGA.

BTW, some more behaviors I noted. When doing a memory intensive activity and you dont have enough SoC voltage, no BSOD. Instead it instantly restarts. I'm ok with 0.9v SOC on 3200. 3333 requires more than 0.9. Quick and dirty 1v fixes that issue.

Also might be some signaling thing going on for 3333 and higher. If I have Auto volts, I am almost guaranteed to BSOD on OS load (Wont even get to desktop). If I set to 1.45v, its much more reliable. If I set to 1.4375, it has similar behavior to Auto volts (this is stock CPU speed. Temperatures are fine, just dumping different voltages to see what happens).

Some people mention VDDP but this board does not have a slider for VDDP. There is something like CLDO_VDDP but that is something else. That setting does not seem to have any significant effect (Tried a 1v to 0.8v at steps of 0.01 with no discernible change)


----------



## chew*

Well hmmm.

I can tell you with 2 fury x as i have not pinned down if its those or amd in general is causing me drama.

Mostly randomly accessing vga followed by a mouse freeze/unfreeze 10-20 secs later.

I screwed with swapping chipset drivers. It got worse with them uninstalled so maybe a clue on my end.

Lets see random bsod idle prelaunch.

Net drivers were causing drama. Lack of installing them.

There is some nb performance setting in agesa having it enabled caused major drama. Random bsod idle.

Other than that the idle bsod has not plagued me.

Maybe one of those tips helps.

I am not home but i will screen the drama NB performance setting when i get home


----------



## revolver90

I have a ryzen 3 1200(overclocked to 3.9ghz on 1.3v...can't go any higher) on an Asrock b350m pro4 and g.skill aegis 3000mhz 8gb.
I have managed to run the memory on 2933mhz with the following timings on 1.4v.


Is there any optimization i can do to the timings to improve even more the performance of my build?


----------



## chew*

Lets see. If you want to follow Ryzen rules Tras 30 or ddr4 rules 32.

Ddr 4 rules makes your trc 46 to 48 if you follow that. Avoid odds if possible.

Twcl should be = tcl or -1 but....avoid odds.( optimal example is tcl 15 twcl 14 )

I have found borrowing 2400 strap subs to boost performance so...

TrrdS 4

TrrdL 6

Tfaw = trrds*4 +0-8 so the loosest would be 24.

Also 2400 strap subs.

TwtrS 3

TwtrL 8

You can pull trfc in if your sticks can do it. Baseline 132/192/312 <-- pull last one in for performance leave other 2 alone.

More 2400 strap subs

Twrwr SD 6
twrwr DD 6

Trdrd sd 4
Trdrd dd 4

Last but not least you can play with cke which in my testing 6-9 are optimal ranges. Highly suggest testing this as it can impact performance.

And just so people do not think I pull magical numbers out of my azz.

http://www.overclock.net/t/1627407/asrock-x370-taichi-overclocking-thread/1920#post_26379605

Sometimes what you would assume automatically is faster... Is not.

2400 strab subs and trfc play a huge role in gains.

Far more than say 14-13-13-28-42 vs 14-14-14-28-50/52.


----------



## sandysuk

Quote:


> Originally Posted by *ssateneth*
> 
> BTW, some more behaviors I noted. When doing a memory intensive activity and you dont have enough SoC voltage, no BSOD. Instead it instantly restarts. I'm ok with 0.9v SOC on 3200. 3333 requires more than 0.9. Quick and dirty 1v fixes that issue.
> 
> Also might be some signaling thing going on for 3333 and higher. If I have Auto volts, I am almost guaranteed to BSOD on OS load (Wont even get to desktop). If I set to 1.45v, its much more reliable. If I set to 1.4375, it has similar behavior to Auto volts (this is stock CPU speed. Temperatures are fine, just dumping different voltages to see what happens).


My board Autos SOC voltage at 1.1875, to stabilizes 3466 I had to set 1.1875 (which gives 1.2)

My RAM settings are the following for 3333 with 4x8 Gskill, 3466 is much the same but with CL14-15-15-30 with RC and RFC increased, when I decide to have a stab at trying to get it too run cold boot again I'll get the numbers.

Using 1.45v also, found RAM slots near the IO back plate get quite hot so have a fan over them, not sure if they had any instability due to that but more cooling can't hurt.


----------



## chew*

Same. The heatpiped sink warms up that last dimm.

Pass 4x16g DR ( 2000 % coverage ) in memtest @3200 with DR @ 1.36 vdimm in bios 1.050 SOC .88vddp

Vcore was jacked up to produce heat since memtest does not get it warm enough at normal vcore imo.. I do not trust results on AMD without getting cpu warm......

Took over 24 hours to run this but I don't mind the system is being tuned for 24/7 abuse as a VM.
So much for memtest is the easier way.....I prefer prime my 2c


----------



## mongoled

Here are my results, rig in my sig below,

in short,

1600X @4.0---3200MHz-C14-14-14-30-1T---1.450v---SOC 1.000v---HCI---1000%---F4-3600C15D-16GTZ



These are also prime95 stable custom 14000mb +12 hours

There is scope for improvement, just from what ive been reading my combination of hardware is not the best out there!

I couldnt hold these settings using prime95 with tRAS at 28, also I cant drop tFAW to tRRDS x 4 + 0 -8, instantly drops threads in prime95

Am I asking for too much with the CPU at 4.0 Ghz, as most of the results people are posting are with CPU speeds below 3.9 Ghz ?

Also tFRC is at 560, im retrying at 312 as I had initially thought that the inconsistant stability I was seeing was becuase of tFRC but it turned out it was because of tRAS at 28.

And..... this CPU will be going for RMA as it has the segmentation fault.

If anybody can spot a big no no with my memory timings could they please kindly point this out !


----------



## revolver90

Thank toy for the response,i actually got better performance with your settings


----------



## MynRich

1700 4GHz 1.3875v LLC2, 3333MT/s DDR4 14-14-14-14-30-44-307-1T 1.37v SOC 1.05v LLC2 ProcODT-60Ohms


----------



## sisay

Hi,
my 3000c14-32gtz b-die dual rank (14-14-14-34)
on the 68ohm procodt i have 3200 mhz, every other value causes no connection in pc.
I set1.4V memory voltage, 1.2 Soc, every time in memtest86 I have random errors. I made a change of timing, every time the computer does not turn on, it only works on cl14. Can you stabilize the memory?
I have yet set
ClkDrvbStren = 40.0 Ohm
AddrCmdDrvStren = 20.0 Ohm
CsOdtDrvStren = 40.0 Ohm
CkeDrvStren = 40.0 Ohm
RttNom = RZQ / 3
RttWr = RZQ / 3
RttPark = RZQ / 1

sry for my English


----------



## poah

is there any real point in increasing the voltage for a few extra MHz or one CL point? I'm running 2993 @ 1.35v 15 17 17 36 currently


----------



## happyluckbox

Quote:


> Originally Posted by *poah*
> 
> is there any real point in increasing the voltage for a few extra MHz or one CL point? I'm running 2993 @ 1.35v 15 17 17 36 currently


Depends how much more voltage. You can't ask an arbitary question like that and expect a proper answer


----------



## poah

Quote:


> Originally Posted by *happyluckbox*
> 
> Depends how much more voltage. You can't ask an arbitary question like that and expect a proper answer


sorry it was too tough for you to see what I was meaning









Increasing MHz from 2993 to 3200 won't make any real difference to render times or fps in games. Like wise going down one point in your RAM timings will have the same lack of real world difference so why pump the voltage up to get 3200mhz etc when all it is doing is heating up your motherboard. There is a point of diminishing returns when tuning ram just like CPU overclocking. I could get 4.0ghz but the voltage increase was huge to what 3.9 was.


----------



## chew*

Quote:


> Originally Posted by *poah*
> 
> sorry it was too tough for you to see what I was meaning
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Increasing MHz from 2993 to 3200 won't make any real difference to render times or fps in games. Like wise going down one point in your RAM timings will have the same lack of real world difference so why pump the voltage up to get 3200mhz etc when all it is doing is heating up your motherboard. There is a point of diminishing returns when tuning ram just like CPU overclocking. I could get 4.0ghz but the voltage increase was huge to what 3.9 was.


In an effort to answer your question in a real world scenario.

I'm tuning this system for an app called agisoft photo scan pro. Its basically rendering and the system will run non stop 24/7

Now being realistic lets just toss all results above 3200 away and just compare the results at 3200 by me versus everyone else.

For 3200 I only need 1.36v and it took quite some time tuning wise to get the system stable with the least volts.

Regardless take a look at some of the lesser scores and compare the time it took.

even if comparing to the 1 sec difference results that 1 secs = 30 secs in an hour multiplied by 24 hours that is 12 mins saved. multiply that by a week that is over an hour saved multiply that by 52 that is 52 hours saved in a year which means the machine made up for 2 days of work.

now compare that to the results 7 seconds and slower and do the same math.

Simply put time is money/productivity for some.


----------



## miklkit

On the other end of the scale there is a total memory noob like me. I do notice the difference from faster ram in games and benches so did what I could to make these 4 stick faster and they are currently at 3020mhz.

HWINFO64 lets you monitor ram temps and I never saw them going over 40C and they were usually around 36C so I disabled monitoring the ram to save space. This is at 1.43 volts too. If you are worried about the ram overheating the motherboard, then you need to get a better motherboard.


----------



## chew*

Here is the setting that causes a lot of drama on TR.

I found that by default auto is not performance........least on my board.

I am always looking for ways to sqezze more performance from my system so when I see a performance setting I try it. At least on the Asrock I would avoid this setting for now....


----------



## mijotter

Greetings. I'm building a Ryzen PC. Going with the 1800x on the Crosshair Hero VI MoBo.

I've been reading that the RAM has to be Samsung B-die in order to run well with the high clocks/frequencies.

I need 32 gb of RAM so finding the right sticks that are 2x16 has been difficult.

Would these be just as effective?

https://www.newegg.com/Product/Product.aspx?Item=N82E16820232091&ignorebbr=1&nm_mc=AFC-C8Junction&cm_mmc=AFC-C8Junction-PCPartPicker,%20LLC-_-na-_-na-_-na&cm_sp=&AID=10446076&PID=3938566&SID=

OR should I get these for the much higher price?

https://www.newegg.com/Product/Product.aspx?Item=N82E16820232206&cm_re=f4_3200c14d_32gtz-_-20-232-206-_-Product&nm_mc=AFC-C8Junction&cm_mmc=AFC-C8Junction-VigLink-_-na-_-na-_-na&cm_sp=&AID=10446076&PID=6146846&SID=j8m0glxlq5000kb500053

Thanks.


----------



## ssateneth

Quote:


> Originally Posted by *chew**
> 
> Same. The heatpiped sink warms up that last dimm.
> 
> Pass 4x16g DR ( 2000 % coverage ) in memtest @3200 with DR @ 1.36 vdimm in bios 1.050 SOC .88vddp
> 
> Vcore was jacked up to produce heat since memtest does not get it warm enough at normal vcore imo.. I do not trust results on AMD without getting cpu warm......
> 
> Took over 24 hours to run this but I don't mind the system is being tuned for 24/7 abuse as a VM.
> So much for memtest is the easier way.....I prefer prime my 2c


Over the last couple days, I've been running HCI to weed out RAM things. Started at my 'fast' settings. Picked up some regular errors, ok, I expected that (1 here, 2 there, but they are steady). Go to AUTO on primary timings, errors are much less frequent now, but now they appear in sets of 8. At this point, I brought down CPU clock speed, and brought RAM secondary, and finally tertiary timings all to AUTO, brought RAM voltage down to 1.35 aaaaaaand... nada. I think my IMC is crap. I sitll pick up infrequent sets of 8 errors and last few times the PC has rebooted (MEMORY_MANAGEMENT, SYSTEM_SERVICE_EXCEPTION, PAGE_FAULT_IN_NONPAGED_AREA, DRIVER_IRQL_NOT_LESS_OR_EQUAL). This reminds me of my intel board when I was pushing the cache speed too much.

Is your VDDP the CLDO_VDDP setting or an actual setting called VDDP? If the latter, my board doesn't have that. Also what procodt and CAD ohm settings are you using?


----------



## chew*

Quote:


> Originally Posted by *ssateneth*
> 
> Over the last couple days, I've been running HCI to weed out RAM things. Started at my 'fast' settings. Picked up some regular errors, ok, I expected that (1 here, 2 there, but they are steady). Go to AUTO on primary timings, errors are much less frequent now, but now they appear in sets of 8. At this point, I brought down CPU clock speed, and brought RAM secondary, and finally tertiary timings all to AUTO, brought RAM voltage down to 1.35 aaaaaaand... nada. I think my IMC is crap. I sitll pick up infrequent sets of 8 errors and last few times the PC has rebooted (MEMORY_MANAGEMENT, SYSTEM_SERVICE_EXCEPTION, PAGE_FAULT_IN_NONPAGED_AREA, DRIVER_IRQL_NOT_LESS_OR_EQUAL). This reminds me of my intel board when I was pushing the cache speed too much.
> 
> Is your VDDP the CLDO_VDDP setting or an actual setting called VDDP? If the latter, my board doesn't have that. Also what procodt and CAD ohm settings are you using?


vddcr_soc_s5 formerly known as vddp not to be confused with cldo_vddp ( probably why they changed the name )

I have not needed to screw with ODT or cad bus with this particular cpu. it just works and pushing for 3333 is most likely going to be a stretch with DR and will require way way more tinkering than the person that is eventually going to use this machine is going to care to do.

As it is it is getting another 64 gb added and that is going to be drama by itself for which I have created profiles ranging from 2666-3066 for.


----------



## Esenel

[email protected] 1.1v---BIOS 9920---HCI---400%---F4-3200C14-16GTZ


----------



## ssateneth

Quote:


> Originally Posted by *chew**
> 
> vddcr_soc_s5 formerly known as vddp not to be confused with cldo_vddp ( probably why they changed the name )
> 
> I have not needed to screw with ODT or cad bus with this particular cpu. it just works and pushing for 3333 is most likely going to be a stretch with DR and will require way way more tinkering than the person that is eventually going to use this machine is going to care to do.
> 
> As it is it is getting another 64 gb added and that is going to be drama by itself for which I have created profiles ranging from 2666-3066 for.


Yeah the MSI board does not have that voltage setting. Would it be your opinion that lacking that setting is likely the cause for lack of stability above 2933MHz (4x16GiB DR sam b-die), regardless of RAM timings/settings? Only has Core, SOC, "CPU 1P8" which seems to be PLL (default 1.8v), DDR4 (main, vpp, and vref), and PROM core and phy (which I assume is the promontory PCH core and phy)


----------



## chew*

Probably cpu with 4x16. Board/bios optimizations can help but only so much..

Probably going to need to dig in and fine tune it. Took me about 2 weeks.


----------



## chroniclard

Couple of questions.









Currently have 3333 running with the stilts fast 3200 settings 14-13-13-13-28 at 1T

Cant seem to get any better at 1T, though this isn't bad at all.

1. Is running at 2T "easier"?
2. Is there any performance loss at 2T?
3. Think 3466 @ 2T would be any better, given the timings would probably be looser?

cheers


----------



## Laur3nTyu

I'm having a hard time convincing myself to run the RAM higher than its rated voltage 1.35V.

ATM i'm running 3200CL14 (My ram is 3600 g.skill CL 16) @ 1.4v.

Is the ram gonna die on me or is it safe to run it at 1.4v? I haven't found any info about it that convinced me and I decided to ask you guys..

What are your thoughts?


----------



## ssateneth

Quote:


> Originally Posted by *Laur3nTyu*
> 
> I'm having a hard time convincing myself to run the RAM higher than its rated voltage 1.35V.
> 
> ATM i'm running 3200CL14 (My ram is 3600 g.skill CL 16) @ 1.4v.
> 
> Is the ram gonna die on me or is it safe to run it at 1.4v? I haven't found any info about it that convinced me and I decided to ask you guys..
> 
> What are your thoughts?


XMP profiles are allowed to program voltage in as high as 1.5v, which is only 25% higher than the default 1.2v. It's safe.


----------



## ssateneth

Quote:


> Originally Posted by *chew**
> 
> Probably cpu with 4x16. Board/bios optimizations can help but only so much..
> 
> Probably going to need to dig in and fine tune it. Took me about 2 weeks.


Meh. I find it hard to believe it's the CPU. Was purchased from silicon lottery, top tier bin. In any case, it comes down to begging MSI to add the voltage, or to spend money and get a different board or different (and less) ram


----------



## chew*

Quote:


> Originally Posted by *ssateneth*
> 
> Meh. I find it hard to believe it's the CPU. Was purchased from silicon lottery, top tier bin. In any case, it comes down to begging MSI to add the voltage, or to spend money and get a different board or different (and less) ram


Um silicon lottery explicitly states they do not bin imc. Just core clock with memory @ defaults.


----------



## nexxusty

Quote:


> Originally Posted by *Laur3nTyu*
> 
> I'm having a hard time convincing myself to run the RAM higher than its rated voltage 1.35V.
> 
> ATM i'm running 3200CL14 (My ram is 3600 g.skill CL 16) @ 1.4v.
> 
> Is the ram gonna die on me or is it safe to run it at 1.4v? I haven't found any info about it that convinced me and I decided to ask you guys..
> 
> What are your thoughts?


I understand you are scared running higher than 1.35v will damage your RAM. This is an unwarranted fear however.

As the gentleman right after your post said.... XMP profiles can use up 1.5v VDIMM. Keep your RAM below 45c and you can use up to 1.5v no problem. Honestly, even 1.65v with active cooling is fine for Samsung B-Die IC's. Again, keeping your RAM under 45c is crucial.

Something called "Wandering Bits" happens above that temperature. I always give myself 5c from that figure, so I don't let my RAM go above 40c. I actively cool my kit so it doesn't ever go over 36c. This has been a boon to me as Ripjaws IC's are not as good as Trident Z IC's. At least mine aren't.... Every timing/voltage set you see for Samsung B-Die is done with Trident Z usually.

While I can always do these timings stably, however I always require 1.43v VDIMM where as most of these timing/voltage set's are done with 1.4v. My SoC is in the same 1.1v range. No issues there.

I too have a set of G.Skill 3600mhz CL16, these are THE best kits to get with Ryzen. Period.

Trident Z or Ripjaws V, it doesn't matter. The Ripjaws just require a liiiitle more voltage to stabilize it seems. Honestly, I would just save the cash and go with a set of Ripjaws V 10 out of 10 times in this situation. Unless, maybe you bench with Intel as well. I bet the Trident Z will scale a bit better on Intel in terms of voltage to frequency.

Out of curiosity, which set do you have? Same as I, or the Trident Z variation?


----------



## Laur3nTyu

Quote:


> Originally Posted by *nexxusty*
> 
> I understand you are scared running higher than 1.35v will damage your RAM. This is an unwarranted fear however.
> 
> As the gentleman right after your post said.... XMP profiles can use up 1.5v VDIMM. Keep your RAM below 45c and you can use up to 1.5v no problem. Honestly, even 1.65v with active cooling is fine for Samsung B-Die IC's. Again, keeping your RAM under 45c is crucial.
> 
> Something called "Wandering Bits" happens above that temperature. I always give myself 5c from that figure, so I don't let my RAM go above 40c. I actively cool my kit so it doesn't ever go over 36c. This has been a boon to me as Ripjaws IC's are not as good as Trident Z IC's. At least mine aren't.... Every timing/voltage set you see for Samsung B-Die is done with Trident Z usually.
> 
> While I can always do these timings stably, however I always require 1.43v VDIMM where as most of these timing/voltage set's are done with 1.4v. My SoC is in the same 1.1v range. No issues there.
> 
> I too have a set of G.Skill 3600mhz CL16, these are THE best kits to get with Ryzen. Period.
> 
> Trident Z or Ripjaws V, it doesn't matter. The Ripjaws just require a liiiitle more voltage to stabilize it seems. Honestly, I would just save the cash and go with a set of Ripjaws V 10 out of 10 times in this situation. Unless, maybe you bench with Intel as well. I bet the Trident Z will scale a bit better on Intel in terms of voltage to frequency.
> 
> Out of curiosity, which set do you have? Same as I, or the Trident Z variation?


I am using the G.skill Trident Z grey/red color (F4-3600C16D-16GTZ) .

Currently using it under ryzen 1600x / c6h combo @ 3466 @ 1.4v with the Stilts's preset. I checked for stability and it's stable (400% HCI). I'm happy I managed to get it higher than 3200 thought I cannot see a real difference but it's more like a psihical comfort


----------



## Darkstalker420

Sorry if this is off topic somewhat. But this thread is named exactly what i don't have (Memory Stability)! and you people seem to know your stuff so i'm wondering if you could give us a few pointers. I have the rig in my sig running a not very stable 3200Mhz DRAM @ 39,19,19,19 C18 1T 1.35v using the D.O.C.P profile. My sticks are "B"Die Corsair CMK16GX4M2B3600C18 Vengeance LPX 16 GB (2 x 8 GB). They are in the MoBo's QVL rated for 3200Mhz operation via the D.O.C.P setting The thing is if i run them as they are set i get BSOD's watching YouTube vids!! But can game for hours and the rig is just "flaky" imho.

My last rig was a PhII X6 so this way out of my league for messing in the BIOS.







IBT will fail at V HIGH preset on the second pass and AIDA64 will run for about 9:00 then errors out. I found raising the SoC V's to 1.160v's stopped the YouTube BSOD's. I have gone upto 1.200v's for the SoC and this didn't help also upto 1.46v's for DRAM and this didn't help much either. I can't seem to tighten the timings at all (36.16,16,16 will just crash stress test programs faster!).

3333Mhz will get into windows but crash when stressing in seconds. 3466Mhz will BSOD on loading Windows 10. This is with the high SoC and DRAM v's posted above. I have worked my way up of course not just "hit the high v's". I'm not clocking the CPU i would just like to get 3466 C16/14 or even a 100% stable 3200Mhz with "tight" timings and i will be happy but as mentioned the Strix's BIOS is like a foreign language. I have tried a few guides but find the settings are not called what the are in MY BIOS as lots of the guides use the C6H and they obviously are different. So i'm leary of just whacking the numbers in and hoping that its the right setting.

Any assistance would be very much appreciated as i'm out of my depth really but want MOAR MHZ!!














Even a link to a good guide showing me what to "tweak" that isn't just C6H this C6H that would be great tbh. But anything would be good. I should say all is on AUTO/DEFAULT bar the SoC and the DRAM which D.O.C.P sets to 1.35v. Thanks people.









Thanx.


----------



## Silent Scone

Quote:


> Originally Posted by *chew**
> 
> Twcl should be equal to or 1 less than CL. Ryzen appears not to like odd twcl.
> 
> Of course you can break this rule but stability means nothing if performance is lost.
> 
> Tfaw rule is trrds multiplied by 4+0-8.
> Your at 12 when minimum should be 16.
> 
> Many seem to focus solely on stability and speed but seldom focus on how it impacts performance.
> 
> Aida means very little realworld wise tbh.
> 
> My system does not BSOD FYI. I can't imagine why


Can't imagine, or don't honestly know why?


----------



## chew*

it was a comment at a guy with an aida only shot but complaining about bsods......


----------



## happyluckbox

My tcwl doesn't work unless I set it to 10 with a cas latency of 14. I thought it was supposed to be equal to CL or CL-1? If I try to change tcwl to 14, 13, 12, or 11, I cannot post. Only 10 works.


----------



## Nighthog

Quote:


> Originally Posted by *happyluckbox*
> 
> My tcwl doesn't work unless I set it to 10 with a cas latency of 14. I thought it was supposed to be equal to CL or CL-1? If I try to change tcwl to 14, 13, 12, or 11, I cannot post. Only 10 works.


I had similar issues before with my ryzen 7 and b350 board( 10 or 12 only worked error free). A new bios update seemed to have fixed it.

Though I much reckon it may have something to do with timings and voltages and such. It ties much in with what other stuff are set as. As mentioned it performs better with being equal meaning it requires more from stability standpoint. so you might need to tweak other settings to match your memory to be able to have stability.

And don't put tCWL to odd numbers 11. 13 etc. doesn't work outright for me at all.


----------



## xethi

Quote:


> Originally Posted by *Nighthog*
> 
> I had similar issues before with my ryzen 7 and b350 board( 10 or 12 only worked error free). A new bios update seemed to have fixed it.
> 
> Though I much reckon it may have something to do with timings and voltages and such. It ties much in with what other stuff are set as. As mentioned it performs better with being equal meaning it requires more from stability standpoint. so you might need to tweak other settings to match your memory to be able to have stability.
> 
> And don't put tCWL to odd numbers 11. 13 etc. doesn't work outright for me at all.


i didnt know tcwl = cas is the better setting to have for performance if stable. what else is true about those sub timings.

i mostly started from stilt profile mixed with chews and mixed and match but dont know how each can affect speed hard to find info

i for now am at 1.39vram 3466 14 14 14 30 46 trrds 4 trrdl6 tfaw 24 twr 12 trfc 267 tcwl 14 trtp 8 trdwr6

lower tras or tfaw doesnt pass yet with my current setup. not sure which other timings i can try to play with other then trfc that i know for sure that lower mean better performance if stable but 267 seem low allready.


----------



## Nighthog

Quote:


> Originally Posted by *xethi*
> 
> i didnt know tcwl = cas is the better setting to have for performance if stable. what else is true about those sub timings.
> 
> i mostly started from stilt profile mixed with chews and mixed and match but dont know how each can affect speed hard to find info
> 
> i for now am at 1.39vram 3466 14 14 14 30 46 trrds 4 trrdl6 tfaw 24 twr 12 trfc 267 tcwl 14 trtp 8 trdwr6
> 
> lower tras or tfaw doesnt pass yet with my current setup. not sure which other timings i can try to play with other then trfc that i know for sure that lower mean better performance if stable but 267 seem low allready.


You are basically finalized in your settings already. Not much to do but try each setting one at the time and see if it can be put lower and not return errors. It's a tedious work to find those last squeezes available, You might need to set one and test for hours before it returns a error and then go back and try something else.









I've been putting half the day today to find what is causing me a error in HCImemtest in the 300-500% range with some tight timings for 3066Mhz, can't find the one that is causing it.








I use the same timings as 2933 so it's just a gain if I can nail the problem out. In the meanwhile I found out some stuff that can be tighter without issue.


----------



## mongoled

Do I have the worse sticks of Gskill B-die on the Internets ??

I need 1.45v (showing as 1.475v in bios) to run 3200-14-14-14-1T-30-50-312 - F4-3600C15D-16GTZ (Prime95 custom 14000mb stable +12 hrs)



tRFC is 560 in image above but since ive improved it to 312.

Settings in sig

Ive asked several times in this thread for someone to double check over my settings but im just being ignored, so i am asking one last time.

Thanks

** EDIT **

What controls/influences the tREF values ???

** EDIT2 **

Keep seeing people mention F4-3600C16D are the best sticks and mine are 15D but are worse instead of better ...................


----------



## Worldwin

Quote:


> Originally Posted by *mongoled*
> 
> Do I have the worse sticks of Gskill B-die on the Internets ??
> 
> I need 1.45v (showing as 1.475v in bios) to run 3200-14-14-14-1T-30-50-312 - F4-3600C15D-16GTZ (Prime95 custom 14000mb stable +12 hrs)
> 
> 
> 
> tRFC is 512 in image above but since ive improved it to 312.
> 
> Settings in sig
> 
> Ive asked several times in this thread for someone to double check over my settings but im just being ignored, so i am asking one last time.
> 
> Thanks
> 
> ** EDIT **
> 
> What controls/influences the tREF values ???


Increase your SOC. You have it at 1.0V. Considering you are using the better RAM (3600 C15) you should not be facing these problems. Try upping SOC to 1.1V. This should let you lower your DRAM V.


----------



## mongoled

Quote:


> Originally Posted by *Worldwin*
> 
> Increase your SOC. You have it at 1.0V. Considering you are using the better RAM (3600 C15) you should not be facing these problems. Try upping SOC to 1.1V. This should let you lower your DRAM V.


Thanks for posting, ive tried with up to 1.2v on the soc, same result.

If I drop even to 1.440 volts in BIOS prime95 will start dropping threads a few hours in ......


----------



## ElectroGeek007

^Forgot to put this in the first screenshot

[email protected] 1.1v---BIOS 1701---W10GSAT---1 Hour---F4-3600C15D-16GTZ

Got some new RAM! CPU back at stock for now while I continue to mess around with timings. This kit should be able to do CL14 3466 I would think but I haven't been able to get that stable yet. Suggestions welcome.


----------



## mongoled

Quote:


> Originally Posted by *ElectroGeek007*
> 
> [email protected] 1.1v---BIOS 1701---W10GSAT---1 Hour---F4-3600C15D-16GTZ
> :


Hi, can you hold these settings at a higher CPU clock speed ?

Thanks


----------



## Kanashimu

What tricks have you guys used to stabilize CPU + Memory OCs together?

I had my 1600X at 4.05 Ghz, which ran Realbench for 8 hours with no issues. vCore 1.45 under load

I had my Trident Z run at 3200 12-14-14-14-30-44-267 for 8 hours on Realbench with no issues. vDDR 1.53 and vSoC 1.2

However, if I try to join the two OCs together, it will always fail within an hour. If I play a game, I'll get regular crashes.

Gigabyte K7, F6 bios.


----------



## ElectroGeek007

Quote:


> Originally Posted by *mongoled*
> 
> Quote:
> 
> 
> 
> Originally Posted by *ElectroGeek007*
> 
> [email protected] 1.1v---BIOS 1701---W10GSAT---1 Hour---F4-3600C15D-16GTZ
> :
> 
> 
> 
> Hi, can you hold these settings at a higher CPU clock speed ?
> 
> Thanks
Click to expand...

Yes it just passed at my standard OC (pstate OC @ 4GHz, +0.025 vcore offset)


----------



## mongoled

Quote:


> Originally Posted by *ElectroGeek007*
> 
> Yes it just passed at my standard OC (pstate OC @ 4GHz, +0.025 vcore offset)


Thanks, nice clock










What stress test is that ?

Are you also stable with prime95 loading all your memory at those settings ?

PS
Im just trying to verify if my RAM is crap!


----------



## miklkit

Quote:


> Originally Posted by *Kanashimu*
> 
> What tricks have you guys used to stabilize CPU + Memory OCs together?
> 
> I had my 1600X at 4.05 Ghz, which ran Realbench for 8 hours with no issues. vCore 1.45 under load
> 
> I had my Trident Z run at 3200 12-14-14-14-30-44-267 for 8 hours on Realbench with no issues. vDDR 1.53 and vSoC 1.2
> 
> However, if I try to join the two OCs together, it will always fail within an hour. If I play a game, I'll get regular crashes.
> 
> Gigabyte K7, F6 bios.


Dunno how others do it, but I locked the cpu into a low stable clock speed and then worked on the ram. Got it as good as it could be and then slowly brought the cpu up to its sweet spot. Higher ram clocks mean more cpu voltage is needed so the cpu might need to get backed off a touch.


----------



## jakemfbacon

Hey guys... I am going to start going through this whole thread, hopefully, in-order to start OC my ram but I had some quick questions first.
First, is it better to OC the ram before you start OCing the CPU?
I have the Asus Crosshair VI motherboard and everytime I boot up I get Q code 24. I know this is not an error, but has anyone been successful with getting it to stop showing this. It didn't always.
The manual says to put the ram in slots A2 and B2 (two grey slots). What is the reasoning for this? I had it in those but just tried A1 and B1 (black slots) and seems like it is running a bit smoother. Could be my imagination though.
Thanks!


----------



## MynRich

Quote:


> Originally Posted by *jakemfbacon*
> 
> Hey guys... I am going to start going through this whole thread, hopefully, in-order to start OC my ram but I had some quick questions first.
> First, is it better to OC the ram before you start OCing the CPU?
> I have the Asus Crosshair VI motherboard and everytime I boot up I get Q code 24. I know this is not an error, but has anyone been successful with getting it to stop showing this. It didn't always.
> The manual says to put the ram in slots A2 and B2 (two grey slots). What is the reasoning for this? I had it in those but just tried A1 and B1 (black slots) and seems like it is running a bit smoother. Could be my imagination though.
> Thanks!


I've always used A2 and B2, but I've seen people on this forum say the same. Realistically, not sure it matters at all as long as they're alternating. Whichever is best/most stable would be my recommendation.
As for the 24, idk if there's a setting in BIOS to set the Q-Code LED to only show boot codes, but I've never even looked to turn it off..


----------



## MynRich

Quote:


> Originally Posted by *zobaa*
> 
> Hello guys. I have just upgraded from phenom II X6 1055t to ryzen 7 1700. After 3 months hard working search i had bought CMK16GX4M2B3200C16R which is exactly compatible at msi list. As u could guess it works 2133 mhz
> 
> 
> 
> 
> 
> 
> 
> 
> 
> With standard xmp profile 1 and profile 2 same 2133
> 
> Could u pls kindly inform me the easiest way to have 3200 or 2933 ? Can i have 3700 on cpu elsewhere or stock.
> 
> Pls point guide or video link if u can
> 
> Thanks
> 
> If someone have same ryzen 7 1700, b350 tomahawk and CMK16GX4M2B3200C16R pls send me the bios pictures...


I used to use the 32GB (2x16GB) kit of that RAM, but this was well before AGESA 1006 released, allowing many to achieve the higher speeds. AFAIK, you're looking at a 2T command rate with higher speeds that aren't sammy-B's? I have since switched to those Samsung B-die just to be safe.


----------



## Nighthog

Some results for 2933Mhz that is quite stable and easy to tweak I found out.


I didn't think I could go so low on so many sub-timings this time around.

3066Mhz I'll have to try again later but there is this recurring random error that peeks it's head now and then. HCi memtest will be usually fine to 300-500% until I get that single error.

F9d bios seems to be a little better in some respects but worse in others. (haven't managed to boot 3200Mhz yet as F7 managed (3333 as well but not without errors))


----------



## xethi

mem5003466.JPG 417k .JPG file


if anyone can help .i was trying to lower my trc which worked from 46 to 44.see memtest

in bios i have dramv at 1.39v but it shows in hwinfo64 1.408 and sometimes 1.416 so i tried to lower bios setting to 1.385 noting else after this memtest above and got huge crash 1f od ect boot looped a few times then i had to reput settings 1by1 as profle saved even if known stable wasnt booting.

is that normal 0.05v difference to do all that ****storm?


----------



## Kanashimu

Quote:


> Originally Posted by *miklkit*
> 
> Dunno how others do it, but I locked the cpu into a low stable clock speed and then worked on the ram. Got it as good as it could be and then slowly brought the cpu up to its sweet spot. Higher ram clocks mean more cpu voltage is needed so the cpu might need to get backed off a touch.


Thanks for the tip! I dropped my CPU down from 4050 down to 3950 to achieve stability with both the CPU and mem OCs. While it sucks to lose 100 Mhz, my overall performance is substantially better with 3200 12-14-14-14-30-44-267.


----------



## Xzow

Had Ryzen 1700x for a few months already, C6H mobo. Still wasn't able to boot at 3200mhz with my CMD16GX4M2B3200C16 corsair ram.

I have it on 3066mhz right now, with CPU voltage & frequency on default. It seems to be stable for days now, but I'm afraid of pushing it higher at this point.. I got a terribly binned 1700x I think.


----------



## edurm

Hello dear guys

I live in brazil and need help, would this 2x16GB b-die chip work on a MSI mortar B350B ? (3200Mhz would be fine)

can t find another opptions here









Thks n advance

G Skill Trident - F4-3333C16D-32GTZSK

32gb-ddr4-memoria-D_NQ_NP_985370-MLB26007510575_092017-F.jpg 233k .jpg file


memoria-32gb-ddr4-3333mhz-g-skill-trident-z-chip-b-die-D_NQ_.jpg 178k .jpg file


----------



## Shiftstealth

Just airing this out there for anyone with a Biostar X370 GT7

A few weeks ago i stated that i upped the SOC switching frequency to 450Khz.

Well i am now RMA'ing my CPU because it can't do 2400Mhz on B-Die anymore, and couldn't do 2133Mhz on Hynx memory at stock. It required 1.1V SOC to be stable. I'd like to state i never pushed more than 1.15 through my SOC and it degraded. It was at the point where it started randomly disconnecting my SSD's.

So i wouldn't advise anyone use that setting.


----------



## miklkit

Eh? I have been using that setting and have not noticed any difference yet. That does not mean that I will not be changing it...........


----------



## MynRich

Quote:


> Originally Posted by *Shiftstealth*
> 
> Just airing this out there for anyone with a Biostar X370 GT7
> 
> A few weeks ago i stated that i upped the SOC switching frequency to 450Khz.
> 
> Well i am now RMA'ing my CPU because it can't do 2400Mhz on B-Die anymore, and couldn't do 2133Mhz on Hynx memory at stock. It required 1.1V SOC to be stable. I'd like to state i never pushed more than 1.15 through my SOC and it degraded. It was at the point where it started randomly disconnecting my SSD's.
> 
> So i wouldn't advise anyone use that setting.


Quote:


> Originally Posted by *miklkit*
> 
> Eh? I have been using that setting and have not noticed any difference yet. That does not mean that I will not be changing it...........


Quote:


> Originally Posted by *miklkit*
> 
> Eh? I have been using that setting and have not noticed any difference yet. That does not mean that I will not be changing it...........


Same, I've used all the switching frequency settings for awhile now... though I haven't gone above 400kHz switching freq on any of those.


----------



## bl1tzk1213g

Any tips for hitting 3334mhz or 3600mhz on taichi x370??


----------



## chew*

Quote:


> Originally Posted by *bl1tzk1213g*
> 
> Any tips for hitting 3334mhz or 3600mhz on taichi x370??


3400 is not that hard. beyond that needs a lucky chip.

lot of helpful folks in the taichi x370 thread.


----------



## happyluckbox

Anybody got 128gb of ram running at 3060mhz or higher?
Feels lonely by myself ?


----------



## andreamit

Trying to decide what 2x8GB DDR4 would be best for Ryzen 1600 + Asus ROG Strix B350-F Gaming. Would you say that getting samsung b-die kits like for example G.Skill Trident Z RGB F4-3200C14D-16GTZR or RipJaws V Series F4-3200C14D-16GVK would be the best choice to avoid any compatibility issue? I heard this mobo is a bit picky when it comes to RAM and I'd rather spend something more and getting my RAM to run at 3200mhz without too much hassle. Thank you!


----------



## miklkit

Quote:


> Originally Posted by *MynRich*
> 
> Same, I've used all the switching frequency settings for awhile now... though I haven't gone above 400kHz switching freq on any of those.


I dropped back to 400mhz and noticed a snappier more accurate mouse. Didn't notice any change when I first switched to 450mhz so the change must have been gradual.


----------



## ssateneth

Quote:


> Originally Posted by *chew**
> 
> Um silicon lottery explicitly states they do not bin imc. Just core clock with memory @ defaults.


Welp, at this point, I think I can blame the motherboard. I picked up an Asrock taichi board when it was on sale at newegg. Thus far, all my BSOD problems went away. Setting 3333 with no other changes (other than 1.35v dram) = instantly POST and no problems. Asrock board also has POST beep and allow delaying of POST screen, 2 of my little nitpicks with the MSI board. Also seems to have a LOT more options exposed.

So yeah, the Asrock board definitely an improvement over the MSI one. I gave MSI lots of chances since X79 (2 chances on X99 and one on X399) and they all fell short. So I'm back on track to getting some fine speeds out of this system.

Unrelated to RAM, it seems the asrock board also respects disabling some of the thermal/power settings. I'm able to push the chip with MUCH more current (thus heat) and it simply refuses to freeze/turn off. Testing 4250MHz on all cores!


----------



## maskymus

[email protected] 1.1v---ProcODT 53.3---Asus CH6 BIOS 1701---HCI 1000%---F4-3200C14Q-32GTZ (4x8Gb)


Spoiler: results







tried 3466 with cas14 and cas15 - no stability in memtest with 1T (at any voltage), passed 1 hour GSAT with cas15.
3333 14-14-14-34-1T failed around 300%.

question: should I push more frequency with 2T or try to get something stable at 3333 CR-1T?


----------



## sandysuk

[
Quote:


> Originally Posted by *ssateneth*
> 
> Welp, at this point, I think I can blame the motherboard. I picked up an Asrock taichi board when it was on sale at newegg. Thus far, all my BSOD problems went away. Setting 3333 with no other changes (other than 1.35v dram) = instantly POST and no problems. Asrock board also has POST beep and allow delaying of POST screen, 2 of my little nitpicks with the MSI board. Also seems to have a LOT more options exposed.
> 
> So yeah, the Asrock board definitely an improvement over the MSI one. I gave MSI lots of chances since X79 (2 chances on X99 and one on X399) and they all fell short. So I'm back on track to getting some fine speeds out of this system.
> 
> Unrelated to RAM, it seems the asrock board also respects disabling some of the thermal/power settings. I'm able to push the chip with MUCH more current (thus heat) and it simply refuses to freeze/turn off. Testing 4250MHz on all cores!


Don't say that I have bought a dud going for MSI









To be fair it seems OK for me but I do wonder if I would have got better results from another board.

I'll be interested to know, how much further you managed to push things, everything is coming out of mine soon to do some case drilling so it could be an opportune time to switch. Though my luck with hardware suggests I should leave a working system alone


----------



## ssateneth

Quote:


> Originally Posted by *sandysuk*
> 
> [
> Don't say that I have bought a dud going for MSI
> 
> 
> 
> 
> 
> 
> 
> 
> 
> To be fair it seems OK for me but I do wonder if I would have got better results from another board.
> 
> I'll be interested to know, how much further you managed to push things, everything is coming out of mine soon to do some case drilling so it could be an opportune time to switch. Though my luck with hardware suggests I should leave a working system alone


MSI board I would get BSOD's from 3066 upwards. 3333 uncommonly did not POST but could get into OS and use it (until BSOD). 3466 would get stuck on POST sequence, sometimes be able to get into UEFI, but no further.

This Asrock board, well... It's very promising. I had a few MEMORY_MANAGEMENT errors early on. Some preliminary settings changed, I can reliably get into OS @ 3600 Ram speed. Haven't had a POST fail yet with tweaks. I'll likely be settling on 3466 or 3333.


----------



## sandysuk

Definitely had some cold boot issues at 3466 so settled on 3333, but it's been rock solid, never had a blue screen at those speeds, only when trying CL12 on the RAM.

That you are still having memory issue might suggest you have a problem with the RAM or it settings still despite better progress.


----------



## Jaju123

I was stable for 6 hours on memtest86, however was getting Large FFT fatal errors in prime 95. I thought it was related to my CPU OC but I dialed back the RAM from 3333 to 3200 and the large FFT errors are gone. Just wanted to let you guys know that instability might be exposed in these different ways too.


----------



## ssateneth

Just reiterating my new asrock board is great to work with so far. Only thing I havent seen on it is Spread Spectrum, and the ability to disable Bluetooth. Some of the other options are buried inside 4 folders, like the VDDP_CLDO (though dont think I'll need it so far).

Been running HCI to try to squish random detected memory errors here and there. Changed lots of voltages and loosened timings to no effect until I got to ProcODT. Seems the default is 68.6 ohms since it had identical error behavior. Once I set it down to 60 Ohms, I stopped seeing errors in the first 5% of coverage. Currently on 30% of 28 x 2GB instances @ 3466, which is far better than anything I've gotten prior.

BTW, has anyone had issues with slow screen repainting with their threadripper systems? Not during RAM testing, but just regular use. I use HWInfo64 to monitor sensors and unless I expand the sensors window so there is no scrolling needing, it spends a vast majority of the time repainting the list of sensors. HWInfo64 seems to be the worst of the munch, but anything else that has a lot of individual text fields and buttons has a noticeably slow draw time.


----------



## chew*

Load up Ryzen master. In memory settings you can see the default odt. Iirc @ 3200 = 60ohms on taichi.

Glad the taichi is working out for you I just personally refrain from suggesting brands especially if I am working with that vendor.


----------



## rdr09

Quote:


> Originally Posted by *andreamit*
> 
> Trying to decide what 2x8GB DDR4 would be best for Ryzen 1600 + Asus ROG Strix B350-F Gaming. Would you say that getting samsung b-die kits like for example G.Skill Trident Z RGB F4-3200C14D-16GTZR or RipJaws V Series F4-3200C14D-16GVK would be the best choice to avoid any compatibility issue? I heard this mobo is a bit picky when it comes to RAM and I'd rather spend something more and getting my RAM to run at 3200mhz without too much hassle. Thank you!


We have same cpu and mobo. I paired them with the GSkill FlareX 16 3200 CL14 and it is running at those spec easy. Also tried 3333 but only tested in a couple of games. This is with Bios 0902.


----------



## happyluckbox

Amd and others say tcwl should be set to cas or cas-1

My cas is 14, but im only able to set tcwl to 10 or 12.

tcwl 13 or 14 result in no post.

Which should I run and why can't I set tcwl to 14?


----------



## Xzow

What die is this ram? It just says "?"


----------



## Mega Man

That would be the question (mark)


----------



## ssateneth

To anyone that purchased HCI memtest pro, it seems they released some new versions recently. I have 5.0. Does anyone know if you have to repurchase the pro version to get the update?


----------



## crakej

Quote:


> Originally Posted by *chew**
> 
> Load up Ryzen master. In memory settings you can see the default odt. Iirc @ 3200 = 60ohms on taichi.
> 
> Glad the taichi is working out for you I just personally refrain from suggesting brands especially if I am working with that vendor.


I can't see ODT in R Master Chew.....where is it?

I've been thinking of jumping ship on my motherboard and move to the TaiChi or CH6 I should have bought in the first place...


----------



## chew*

Crakej. Sorry man I think they excluded x370 boards from showing that.

X399/TR version of RM shows ODT defaults.


----------



## chew*

Quote:


> Originally Posted by *happyluckbox*
> 
> Amd and others say tcwl should be set to cas or cas-1
> 
> My cas is 14, but im only able to set tcwl to 10 or 12.
> 
> tcwl 13 or 14 result in no post.
> 
> Which should I run and why can't I set tcwl to 14?


I would say timing bug in bios.

if I had no choice I would run 12, I would ping gigabyte however and have them sort that that is clearly something that needs fixing.


----------



## gupsterg

Quote:


> Originally Posted by *Xzow*
> 
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 
> 
> 
> 
> 
> What die is this ram? It just says "?"


Contact @Voodoo Jungle he is author of SW and should be able to resolve issue.


----------



## Voodoo Jungle

*gupsterg*, he seems to be using an old TB version. It's E-die.


----------



## coreykill99

So in what ways can instability be measured? over my last few days off I played around with ram some more. reverted everything in bios to defaults and started playing with 3466. idk why cause I cant get 3333 stable for anything. but got it to stick. at about defaults of 15-15-15-35 I can push the cas to 14 across the board but cant push the 35-34 otherwise I get memory errors instantly. so not sure what needs played with there. but aida benchmark says even at those timings its still faster than my 3200xmp profile. ran HCI for about 600% no issues. now all this happened in the last few days so we have ram playing, new windows updates, and a BF1 update. and I cant put my finger on it but i keep getting micro stutters in BF1. and seeing odd latency issues in windows. not quite lag just waiting where I never waited before. encoded about 8 hours of video yesterday. and while it was running decided Id catch up on some youtube. went to open firefox and that took a moment. "whatever" moved to a video gave me the browser outline said not responding. for just a moment. then played just fine. not sure. that's just one example. seen other strange things here or there but nothing enough to call out on. nothing is running "wrong" just...off? idk. thinking about next days off reinstalling windows fresh with this update and seeing how that goes. wondering if there finished release wasn't quite so finished.


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## jearly410

Quote:


> Originally Posted by *coreykill99*
> 
> So in what ways can instability be measured? over my last few days off I played around with ram some more. reverted everything in bios to defaults and started playing with 3466. idk why cause I cant get 3333 stable for anything. but got it to stick. at about defaults of 15-15-15-35 I can push the cas to 14 across the board but cant push the 35-34 otherwise I get memory errors instantly. so not sure what needs played with there. but aida benchmark says even at those timings its still faster than my 3200xmp profile. ran HCI for about 600% no issues. now all this happened in the last few days so we have ram playing, new windows updates, and a BF1 update. and I cant put my finger on it but i keep getting micro stutters in BF1. and seeing odd latency issues in windows. not quite lag just waiting where I never waited before. encoded about 8 hours of video yesterday. and while it was running decided Id catch up on some youtube. went to open firefox and that took a moment. "whatever" moved to a video gave me the browser outline said not responding. for just a moment. then played just fine. not sure. that's just one example. seen other strange things here or there but nothing enough to call out on. nothing is running "wrong" just...off? idk. thinking about next days off reinstalling windows fresh with this update and seeing how that goes. wondering if there finished release wasn't quite so finished.


That sounds normal for unstable memory. Drop down to 3200 same timings and see if the problems persist.


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## Jaju123

Quote:


> Originally Posted by *coreykill99*
> 
> So in what ways can instability be measured? over my last few days off I played around with ram some more. reverted everything in bios to defaults and started playing with 3466. idk why cause I cant get 3333 stable for anything. but got it to stick. at about defaults of 15-15-15-35 I can push the cas to 14 across the board but cant push the 35-34 otherwise I get memory errors instantly. so not sure what needs played with there. but aida benchmark says even at those timings its still faster than my 3200xmp profile. ran HCI for about 600% no issues. now all this happened in the last few days so we have ram playing, new windows updates, and a BF1 update. and I cant put my finger on it but i keep getting micro stutters in BF1. and seeing odd latency issues in windows. not quite lag just waiting where I never waited before. encoded about 8 hours of video yesterday. and while it was running decided Id catch up on some youtube. went to open firefox and that took a moment. "whatever" moved to a video gave me the browser outline said not responding. for just a moment. then played just fine. not sure. that's just one example. seen other strange things here or there but nothing enough to call out on. nothing is running "wrong" just...off? idk. thinking about next days off reinstalling windows fresh with this update and seeing how that goes. wondering if there finished release wasn't quite so finished.


I had the same, then I ran prime95 with large FFT and it gave me errors when memtest would not. Now I had to relax my timings and speed a bit and the stutters in BF1 etc. are gone!


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## 1usmus

*Ryzen DRAM Calculator 0.9.6 v6 fix*



https://drive.google.com/file/d/0Byx_5So-FNsdSjNqVmp3YkVZc3c/view?usp=sharing


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## ssateneth

Quote:


> Originally Posted by *1usmus*
> 
> *Ryzen DRAM Calculator 0.9.6 v6 fix*
> 
> 
> 
> https://drive.google.com/file/d/0Byx_5So-FNsdSjNqVmp3YkVZc3c/view?usp=sharing


Dont think its working right. It tells me to set tCL to 8131 lol. lots of other timings it tells me to put hundreds or thousands.

When I put in the nanoseconds, it puts in a comma instead of a period. and when i push left or right arrow button to change cursor, it makes the cursor go in the opposite direction.

Maybe you should release english version or something with english syntax?










Also I see a google spreadsheets of yours that recommends setting VDDP_CLDO to 425mv, is that safe? Everything i read so far says 0.8 to 0.9 and lower can help move memory hole. 425mv isnt going to burn my CPU will it? Currently using HCI to fine-tune 3333MHz on my TR system. 3466 seems in reach (random single errors here and there) as does 3600 to a lesser degree, just need to find the right setting to tweak. I get sets of 8 errors detected with GDM off and CR of 1, but GDM on and CR auto-set to 1 makes them go away, though its slightly slower in synthetic benches


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## SaccoSVD

How should I work with that app in order to try higher clocks? I have Thaiphoon pro also and introduced my XMP timings for 2933

Do I still need to guess the primary timings, calculate and try the resulting secondary timings?

Ah...no...I should put my timings and change the clock so I get all the timings after calculating...right?

What is the difference between UHQ and HQ XMP? Which one should I use?

BTW: The rank and Dimm values aren't remembered after Save Set is used. The app opens with the default values for those.


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## maskymus

[email protected] 1.05v---ProcODT 53.3---Asus CH6 BIOS 1701---HCI 1000% / Prime95 4.5H---F4-3200C14Q-32GTZ (4x8Gb)
Results:



Spoiler: Prime95



Code:



Code:


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----------



## ssateneth

Woo, Early 3333 found stable on my TR 1950X! Just have to hone in on timings. Also have to grab 1.6 memtest as soon as I can to increase the speed of testing. Primary timings are not tuned yet, just set tertiary timings since they have huge impact on read/write/copy speeds.


----------



## 1usmus

Quote:


> Originally Posted by *ssateneth*
> 
> Dont think its working right. It tells me to set tCL to 8131 lol. lots of other timings it tells me to put hundreds or thousands.
> 
> When I put in the nanoseconds, it puts in a comma instead of a period. and when i push left or right arrow button to change cursor, it makes the cursor go in the opposite direction.
> 
> Maybe you should release english version or something with english syntax?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Also I see a google spreadsheets of yours that recommends setting VDDP_CLDO to 425mv, is that safe? Everything i read so far says 0.8 to 0.9 and lower can help move memory hole. 425mv isnt going to burn my CPU will it? Currently using HCI to fine-tune 3333MHz on my TR system. 3466 seems in reach (random single errors here and there) as does 3600 to a lesser degree, just need to find the right setting to tweak. I get sets of 8 errors detected with GDM off and CR of 1, but GDM on and CR auto-set to 1 makes them go away, though its slightly slower in synthetic benches


yes problem in the syntax, soon correct

"CLDO" has a waveform and is a trigger in the system, with this value it is better to train the memory and the system needs less voltage on the "Soc"

https://drive.google.com/file/d/0Byx_5So-FNsdQmNMdkg4ejIxbms/view?usp=sharing

with English parser, try


----------



## ssateneth

Quote:


> Originally Posted by *1usmus*
> 
> yes problem in the syntax, soon correct
> 
> "CLDO" has a waveform and is a trigger in the system, with this value it is better to train the memory and the system needs less voltage on the "Soc"
> 
> https://drive.google.com/file/d/0Byx_5So-FNsdQmNMdkg4ejIxbms/view?usp=sharing
> 
> with English parser, try


I ran the eng version, and the symptoms are the same. Comma instead of period, cursor moving opposite directions, and suggested timings in hundreds or thousands


----------



## 1usmus

del


----------



## ssateneth

Quote:


> Originally Posted by *1usmus*
> 
> https://drive.google.com/file/d/0Byx_5So-FNsdWGpIdzJXYllqNFE/view?usp=sharing
> 
> and now?


Still the exact same symptoms. I double checked that I'm not opening the old versions and im actually using the new version.


----------



## 1usmus

I apologize for errors, I hope now everything works correctly

*Ryzen DRAM Calculator 0.9.6 v7*

https://drive.google.com/file/d/0Byx_5So-FNsdVkRKRl9CN1lQVXc/view?usp=sharing

*adaptation to any language


----------



## ssateneth

Quote:


> Originally Posted by *1usmus*
> 
> I apologize for errors, I hope now everything works correctly
> 
> *Ryzen DRAM Calculator 0.9.6 v7*
> 
> https://drive.google.com/file/d/0Byx_5So-FNsdVkRKRl9CN1lQVXc/view?usp=sharing
> 
> *adaptation to any language


Timings are now properly calculated. The number format and cursor direction is still not working as expected for english user, but at this point its a cosmetic issue.

BTW, maybe a late question. Is this timing calculator designed around regular Ryzen CPUs and not Threadripper CPUs? I tried setting the RTT to the recommended settings but I get a 3 beep no-post (DIS, RZQ3, RZQ1, using 4 b-die dual rank DIMMs on threadripper)


----------



## 1usmus

Quote:


> Originally Posted by *ssateneth*
> 
> Timings are now properly calculated. The number format and cursor direction is still not working as expected for english user, but at this point its a cosmetic issue.
> 
> BTW, maybe a late question. Is this timing calculator designed around regular Ryzen CPUs and not Threadripper CPUs? I tried setting the RTT to the recommended settings but I get a 3 beep no-post (DIS, RZQ3, RZQ1, using 4 b-die dual rank DIMMs on threadripper)


I'm using character conversion inside a program... this is a universal solution to the problem for all languages








in the future I will try to fix all cosmetics

RTT this is a memory setting and it will not depend on the type of processor, if this is the "dual rank" - disable / rzq3 / rzq1. If the single is ranked - disable / dynamic odt off / rzq 5. From the number of modules will only change procODT. For 4 dual rank modules - procODT 43 or 48, for 8 dual rank ~40 and lower. For 4 singl rank 48-53, for 8 modules procODT 40-48.

in any case it needs to be tested ...


----------



## Xzow

Quote:


> Originally Posted by *Voodoo Jungle*
> 
> *gupsterg*, he seems to be using an old TB version. It's E-die.


Thanks for replying to that. Yeah, it was a test I did a while ago, I guess I should have tried again.
Do you know why TB gets flagged as a trojan now?


----------



## Muezick

Has any one tested Corsairs new White RGB Ram?


----------



## Voodoo Jungle

Quote:


> Originally Posted by *Xzow*
> 
> Do you know why TB gets flagged as a trojan now?


I would ask this question to Microsoft, because the only anti-virus software that don't like my TB is Windows Defender.


----------



## hsn

hsn [email protected] 1.1v---Gigabyte B350n wifi BIOS F6a---GSAT 1hour---Corsair Vengeance Led 32gb ddr4 3200 (hynix dual rank)


----------



## Xzow

Quote:


> Originally Posted by *Voodoo Jungle*
> 
> I would ask this question to Microsoft, because the only anti-virus software that don't like my TB is Windows Defender.


It also tags keygens/cracks as trojans all the time, and you can never know for sure..


----------



## Mega Man

One is illegal, the other not


----------



## Xzow

Quote:


> Originally Posted by *Mega Man*
> 
> One is illegal, the other not


Not all cracks are illegal, and in some countries you're allowed to use them if you bought the software. Remember when things required you to have a cd inside?


----------



## papalol1

ASUS B350 PRIME PLUS
cmk16gx4m2b3200c16

https://gyazo.com/8ac0a1e2f0523f856f10ca41d1e59ee8

Any way to make them work at 3200?


----------



## Xzow

memtest1.jpg 762k .jpg file


[email protected] 1.15v---C6H BIOS 1701---HCI---1980%---Corsair CMD16GX4M2B3200C16


----------



## Jaju123

Has anyone else found that they are actually _less_ stable with _higher_ ram voltage? I ran prime95 and memtest with 1.5V on my G skill 16GB 3600 CL15 kit at just 3200mhz CL14 and instantly got tonnes of errors where before it would take like 10 minutes for errors to appear with 1.45V. I then backed down the voltage to 1.36V and managed to run completely stable for hours. Now, I have lowered voltages massively to only 1.3V on the RAM and 1.06 on the SOC and my computer is ten times as stable than it was at 1.45V and higher. Maybe with very highly binned B-die RAM kits extra voltage is counter productive?


----------



## MynRich

I've found better stability with DRAM voltage set lower too. I have yet to stabilize 1.4v or higher on my F4-3600C15D-16GTZ DDR4 kit. staying under 1.4v allowed memtest pro to pass.


----------



## Jaju123

Quote:


> Originally Posted by *MynRich*
> 
> I've found better stability with DRAM voltage set lower too. I have yet to stabilize 1.4v or higher on my F4-3600C15D-16GTZ DDR4 kit. staying under 1.4v allowed memtest pro to pass.


That's very interesting because it's the same kit as me. What speeds and timings have you been able to achieve? I'm currently running the 3333mhz "fast" timings by The Stilt and it's totally stable at 1.35v and 1.0625 soc voltage.


----------



## iakovl

need the wisdom of the forum members
CMK16GX4M2B3200C16 i get memtest errors a crashes on 3200, can run 2133 without problem so far
GB AB350N itx board with latest 1.0.0.6b bios (before couldn't see 3200 settings)

what can i do get normal memory speed without crashing the system


----------



## makatech

Quote:


> Originally Posted by *Jaju123*
> 
> That's very interesting because it's the same kit as me. What speeds and timings have you been able to achieve? I'm currently running the 3333mhz "fast" timings by The Stilt and it's totally stable at 1.35v and 1.0625 soc voltage.


DRAM 1.35 on 3333MHz, very impressive, I recently heard about another guy running 3333MHz on 1.355. Didn't understand this was possible but it may be cpu or memory dependent? What are your other settings? procODT, LLC etc, running it all on auto?

Surprise nr 2 is the low SoC settings possible, I was chocked being able to run SoC 1.0 for my 32000 setup. ;-) 1.0625 soc for 3333MHz is pretty low too.

I don't think that is possible on my Asus Prime X370 board but I will try. ;-) So far I have not been able to run 3333MHz stable with good manual settings, extremely frustrating. :-( Booting in Windows and running benchmarks is fine but it's not stable with hci memtest or prime95 yet. Perhaps CLDO_VDDP is the secret, not tried yet.

My current timings for _3200MHz_, seem to be stable in hci memtest and prime95 blend test but no night test yet.

DRAM Voltage 1.38, procODT 53.3, SoC 1.0, extreme phase control on cpu and soc.

Settings for Cmd2t, GearDownMode etc visible on the picture.

Memory Corsair CMK16GX4M2B3733C17R

Cpu 1600X (running stock)

My current manual timings:



I'm now on Reous 0902 bios but timings and settings exactly the same with exception from disabling BGS


----------



## Frikencio

Quote:


> Originally Posted by *iakovl*
> 
> need the wisdom of the forum members
> CMK16GX4M2B3200C16 i get memtest errors a crashes on 3200, can run 2133 without problem so far
> GB AB350N itx board with latest 1.0.0.6b bios (before couldn't see 3200 settings)
> 
> what can i do get normal memory speed without crashing the system


Enabe GearDown Mode with a tCKE of 8


----------



## iakovl

under 3200 profile? or lower it?


----------



## Frikencio

Quote:


> Originally Posted by *iakovl*
> 
> under 3200 profile? or lower it?


Same settings but with GearDown mode enabled and tCKE value at 8.

GearDown mode and tCKE timing are located in advanced ram settings.


----------



## Jaju123

Quote:


> Originally Posted by *makatech*
> 
> DRAM 1.35 on 3333MHz, very impressive, I recently heard about another guy running 3333MHz on 1.355. Didn't understand this was possible but it may be cpu or memory dependent? What are your other settings? procODT, LLC etc, running it all on auto?
> 
> Surprise nr 2 is the low SoC settings possible, I was chocked being able to run SoC 1.0 for my 32000 setup. ;-) 1.0625 soc for 3333MHz is pretty low too.
> 
> I don't think that is possible on my Asus Prime X370 board but I will try. ;-) So far I have not been able to run 3333MHz stable with good manual settings, extremely frustrating. :-( Booting in Windows and running benchmarks is fine but it's not stable with hci memtest or prime95 yet. Perhaps CLDO_VDDP is the secret, not tried yet.
> 
> My current timings for _3200MHz_, seem to be stable in hci memtest and prime95 blend test but no night test yet.
> 
> DRAM Voltage 1.38, procODT 53.3, SoC 1.0, extreme phase control on cpu and soc.
> 
> Settings for Cmd2t, GearDownMode etc visible on the picture.
> 
> Memory Corsair CMK16GX4M2B3733C17R
> 
> Cpu 1600X (running stock)
> 
> My current manual timings:
> 
> 
> 
> I'm now on Reous 0902 bios but timings and settings exactly the same with exception from disabling BGS


Well, my kit is supposed to do 3600 15-15-15-15-35 at 1.35v so 3333 cl14 seems more lax than that even.


----------



## makatech

Quote:


> Originally Posted by *Jaju123*
> 
> Well, my kit is supposed to do 3600 15-15-15-15-35 at 1.35v so 3333 cl14 seems more lax than that even.


?

I believe most kits are rated at 1.35V but 1.35V is rarely possible for the higher memory speeds using good manual timings on a Ryzen system (for a stable setup).

Very common that higher DRAM voltage is needed for Samsung b-die sticks on the highest speeds.


----------



## Jaju123

Quote:


> Originally Posted by *makatech*
> 
> ?
> 
> I believe most kits are rated at 1.35V but 1.35V is rarely possible for the higher memory speeds using good manual timings on a Ryzen system (for a stable setup).
> 
> Very common that higher DRAM voltage is needed for Samsung b-die sticks on the highest speeds.


Yeah I heard that too, but my kit is literally the opposite. More stable below 1.4v than above it. You have to take each case individually sometimes I guess.


----------



## Valter84

Hello,

I am here to report my results with Asus Prime X370 Pro and HyperX Predator hx432c16pb3k2/16.
This ram have XMP profile 3200 16-18-18-18-36-1T.
All the values that were were set manually were try and error, clear cmos sometimes, try and error.
I am new to computer builds and OC so if someone can help me to get better timings, I will be thankfull.










Thank you and sorry about my poor English.


----------



## mongoled

Quote:


> Originally Posted by *Jaju123*
> 
> Yeah I heard that too, but my kit is literally the opposite. More stable below 1.4v than above it. You have to take each case individually sometimes I guess.


Bud, i decided to try dropping the RAM voltage quite substantially as you suggested (im my PM to you I had only dropped it to 1.4v without better results)

Its not helping at all in my setup, I tried with 1.3675v and I get a black screen after a few minutes using custom 14000mb


----------



## Jaju123

3466 at 1.36V CL14.... booted right up lol.


----------



## crakej

Quote:


> Originally Posted by *Jaju123*
> 
> 3466 at 1.36V CL14.... booted right up lol.


What RAM do you have?


----------



## Jaju123

Quote:


> Originally Posted by *crakej*
> 
> What RAM do you have?


The G Skill Trident Z F4-3600C15D-16GTZ kit. I think it's a good choice because it's already binned for low latency at high frequencies at only 1.35V. It's one of the best kits out there right now that isn't immensely expensive.


----------



## B4rr3L Rid3R

My poor Micron trying to catch up













That's not the max stable clock, but I need my system really stable for Blender work and those are my initial tests for a while.

https://valid.x86.fr/k3nu27

Crucial BLT8G4D30AETA.K16F

2x 8GB 30000Mhz CL15 1.35V


----------



## miklkit

This is pure speculation on my part, but is there a relationship between ram voltage and SOC voltage?

It seems there are people who run high ram volts and low SOC volts, and those who run low ram volts and high SOC volts. I am running high ram volts and low SOC volts.


----------



## Mega Man

Quote:


> Originally Posted by *Jaju123*
> 
> Has anyone else found that they are actually _less_ stable with _higher_ ram voltage? I ran prime95 and memtest with 1.5V on my G skill 16GB 3600 CL15 kit at just 3200mhz CL14 and instantly got tonnes of errors where before it would take like 10 minutes for errors to appear with 1.45V. I then backed down the voltage to 1.36V and managed to run completely stable for hours. Now, I have lowered voltages massively to only 1.3V on the RAM and 1.06 on the SOC and my computer is ten times as stable than it was at 1.45V and higher. Maybe with very highly binned B-die RAM kits extra voltage is counter productive?


it is common for too much voltage to cause instability actually


----------



## Jaju123

Quote:


> Originally Posted by *Mega Man*
> 
> it is common for too much voltage to cause instability actually


Weird that people never talk about lowering the voltage being an option then. In relation to my earlier post, too, 3466 cl14 boots up fine but is not stable at all. Could do cl16 but then there's no benefit over 3333mhz cl14 with fast subtimings. Does anyone have any ideas?


----------



## Mega Man

i dont have any that will help you past there.

simply put excessive voltages can and many times do cause instabilities have for years. i first learned on amd 7970s ....

unfortunately the louder voice in this community are people who are not knowledgeable and really do think more is better.... and others who are more experienced get sick of either repeating information or the argument afterward sad but true fact ....


----------



## geoxile

Need some help. I got my RAM back from a RMA (one stick died) and I tried testing them individually using the google stressapptest and both sticks passed at 3200mhz. But now testing them together in dual channel configuration they're failing with thousands of hardware incidents in an hour test. It's G.Skill Trident Z 3200C14, which should be Samsung B-die. I have pretty loose timings on them and just set it to 3200mhz. I tried SOC voltage up to 1.15V and DRAM voltage to 1.4V but so far no luck. I had some Ballistix Sports 2400mhz that I used while the Trident Zs were away and they passed naturally, given it's only 2400mhz. Any ideas?

Edit: It also failed at 2933MHz in dual channel.


----------



## marcola20

Hy everyone, can someone help me, i tried to go to 2933 but nothing works....if needs some images...my memory is a Corsair LPX Vengeance Modelo CMK16GX4M2B3000C15 - Version 5,39

what can i do to go to 2933mhz, in in 2800mhz now.


----------



## makatech

Quote:


> Originally Posted by *marcola20*
> 
> Hy everyone, can someone help me, i tried to go to 2933 but nothing works....if needs some images...my memory is a Corsair LPX Vengeance Modelo CMK16GX4M2B3000C15 - Version 5,39
> 
> what can i do to go to 2933mhz, in in 2800mhz now.


Before changing to Samsung b-die sticks I remember running procODT = 53.3, SoC = 1.1, DRAM volt = 1.38 for 3066MHz, timings 14,17,17, 17,35 (or try something with 14,16,16,16...I hardly remember), rest I had on Auto I think. For 3200 I believe I had to raise DRAM to 1.4

Asus Prime X370...

_*but...* sporadically I got double beeps at coldboots with an automatic additional boot sequence for all speeds above 2800MHz. After the extra automatic post sequence it booted Windows fine though and keeping all my settings. This may not be an error but may be a bit annoying listening to sporadic double beeps at coldboots. I advice you to ignore it if it happens. The reason to this behavior may the Asus Prime X370 lacking an option for setting boot volt for RAM._

*Maybe much better:* This post from @The Stilt may help a lot for configuring your Hynix memories. He is using the Crosshair board but it is for sure worth trying his settings.
http://www.overclock.net/t/1624603/rog-crosshair-vi-overclocking-thread/24130#post_26242714

Good luck


----------



## crakej

my RAM has to be at 1.4v to run 3200 - it is specced to run 4266 at this voltage though. Giving more volts for 3333 did not bring any improvement for me.


----------



## rdr09

[email protected] 1.10v---BIOS 0902---HCI---400%


----------



## maskymus

[email protected] CH6 BIOS 1701---HCI 900% / Prime95 8H (blend test)---F4-3200C14Q-32GTZ (4x8Gb)
using 1usmus ryzen rec settings except for CLDO_VDDP = Auto,VTT DDR = 0.693, RTT Park = Auto, SOC 1.05



Spoiler: prime95



results-prime-3200-custom.txt 38k .txt file


----------



## coreykill99

Quote:


> Originally Posted by *maskymus*
> 
> [email protected] CH6 BIOS 1701---HCI 900% / Prime95 8H (blend test)---F4-3200C14Q-32GTZ (4x8Gb)
> using 1usmus ryzen rec settings except for CLDO_VDDP = Auto,VTT DDR = 0.693, RTT Park = Auto, SOC 1.05
> 
> 
> 
> Spoiler: prime95
> 
> 
> 
> results-prime-3200-custom.txt 38k .txt file


is that a new version of RTC? pretty sure mine does not have a reading for bank group swap alt.


----------



## maskymus

It's RTC 1.01 - has support for BankGroupSwapAlternative


----------



## mus1mus

Quote:


> Originally Posted by *rdr09*
> 
> [email protected] 1.10v---BIOS 0902---HCI---400%


Nice!

How's the CPU doing?


----------



## rdr09

Quote:


> Originally Posted by *mus1mus*
> 
> Nice!
> 
> How's the CPU doing?


CPU is running great at a mild oc using the Asus's TPU II setting. Definitely an upgrade from the Phenom. At 3.7 its matching even my i7 Sandy 4.5 in single core performance. The faster DDR4 does help a lot.


----------



## ssateneth

Little bit of progress on my system using the asrock x399 taichi board, 1950x, and 4x16GB b-die modules. Turns out that I'm in the crowd where my ram (or IMC) does -not- like higher ram voltage as it throws intermittent errors in HCI memtest. I started with 1.4 and went up 0.025v every time I got an error (3333MHz RAM, tuned tertiary timings, stock secondary, am working on primary timings right now. CAS14 dialed in, working on Trcd). RAM was fine with stock Trcd (23!) but obviously thats a terrible timing. I went as high as 1.55 (prepared to go to 1.65) but errors quickly got worse the higher the voltage went. So started back at 1.4 and went down by 0.01v steps. Seems like 1.37v is the 'magic number' for this particular setup. Intermittent errors are gone.

Made to 400% HCI on 3333 14-14-stock-stock, currently 300% HCI on 14-13-stock-stock. I've been stuck on Trcd for over a week, feels good to finally make some progress. Hopefully this week i'll be fully tuned and reduce voltages further once timings are fully tuned. I'll probably try a shot at 3466 too (and see if reducing ram voltage further makes good success on that since it got the same intermittent issues), or 3333 1T with GDM off.


----------



## 1usmus

*Ryzen DRAM Calculator 0.9.9 v2
*

global update

https://drive.google.com/file/d/0Byx_5So-FNsdc0ZlaFRULThCcmM/view?usp=sharing

* reworked all calculators, presets


----------



## geoxile

Anyone run into a case where stressapptest fails in Windows but passes in Linux mint? I'm running mint from usb and it passed a 45min test while it'll fail in a few minutes in Windows FCU. OS aside the only other big difference is Windows has AMD drivers installed



Pic of my 2hr pass in mint. Using settings and timings for 8GBx2 Trident Z 3200C14 provided by the calculator above ^

Problem is I can't get it to pass in Windows...

Edit: Just noticed something severely wrong with the test in Linux, it's not clocking to 3200!


----------



## Valter84

Hello guys.

Placing my findings with my ryzen 1700 @ 3.9ghz, asus prime x370 pro and HyperX Predator hx432c16pb3k2/16.
Soc voltage @ 0.95v (llc3) and Ram voltage @ 1.36


I am a litle dummy regarding ram OC, are this good results?
Should I tweek more timings?

Thank you.


----------



## AndreiD

Quote:


> Originally Posted by *geoxile*
> 
> Anyone run into a case where stressapptest fails in Windows but passes in Linux mint? I'm running mint from usb and it passed a 45min test while it'll fail in a few minutes in Windows FCU. OS aside the only other big difference is Windows has AMD drivers installed


I have a similar issue, tried GSAT with Windows FCU and I kept getting hardware errors:

I'm not sure why, since I can get through 2 passes of memtest86 and over 1000% HCI coverage, but somehow I fail GSAT regardless of memory speed, DIMM slots used (even used 1 DIMM at a time). Going to chalk that up as an issue with using GSAT with Windows FCU, the errors seem to be CPU related (?) since I always fail on 2 threads? Maybe to do with SMT?


----------



## Frikencio

For HCI Memtest *Pro* users, if you want to try my Launcher is here for download:

https://mega.nz/#!7pJS0ZLI!f2jYlBRYXSULSqdaryAwmMUA7VG2vkVjoLHUiBncLg4

You need to place the executable into the HCI Memtest *Pro* folder.

After launching the Memtest instances you can exit the launcher.
You can reopen the launcher at any time and click Update.


----------



## happyluckbox

For 128gb of ram you need hci memtest pro right?


----------



## Esenel

Quote:


> Originally Posted by *happyluckbox*
> 
> For 128gb of ram you need hci memtest pro right?


No you do not.
But with your CPU you have to manually open 32 instances of it (without the pro edition) :-D
And there are always 2 or 3 screens where to click ok.

So I would invest the 5$ ;-)


----------



## coreykill99

Quote:


> Originally Posted by *Frikencio*
> 
> For HCI Memtest *Pro* users, if you want to try my Launcher is here for download:
> 
> https://mega.nz/#!7pJS0ZLI!f2jYlBRYXSULSqdaryAwmMUA7VG2vkVjoLHUiBncLg4
> 
> You need to place the executable into the HCI Memtest *Pro* folder.
> 
> After launching the Memtest instances you can exit the launcher.
> You can reopen the launcher at any time and click Update.


what is this exactly? I have memtest pro. you say launcher does this just open a bunch of instances?


----------



## AndreiD

Quote:


> Originally Posted by *coreykill99*
> 
> what is this exactly? I have memtest pro. you say launcher does this just open a bunch of instances?


Gave it a try and that seems to be exactly what it does, makes things easier than just using a batch file.
It's pretty nifty.


----------



## happyluckbox

Why does each individually allowed max memory allowed on hci memtest Always seem to fluctuate?

Sometimes It maxes out with 2667mb on each instance. Then after Restarting comp again, it suddenly allows 3104mb on each hci instance.

Currently running 32 threads at 3104mb per instance, but this only loads 102/128gb of my ram. Can I run more than 32 threads to approach 95% of ram load?


----------



## geoxile

Quote:


> Originally Posted by *AndreiD*
> 
> I have a similar issue, tried GSAT with Windows FCU and I kept getting hardware errors:
> 
> I'm not sure why, since I can get through 2 passes of memtest86 and over 1000% HCI coverage, but somehow I fail GSAT regardless of memory speed, DIMM slots used (even used 1 DIMM at a time). Going to chalk that up as an issue with using GSAT with Windows FCU, the errors seem to be CPU related (?) since I always fail on 2 threads? Maybe to do with SMT?


I passed a few different hour runs on Linux, it's Windows that's the problem it seems. Also passed 800% HCI run on 16x850MB after reinstalling Windows and that passed but Windows FCU GSAT still fails.


----------



## ssateneth

Quote:


> Originally Posted by *happyluckbox*
> 
> Why does each individually allowed max memory allowed on hci memtest Always seem to fluctuate?
> 
> Sometimes It maxes out with 2667mb on each instance. Then after Restarting comp again, it suddenly allows 3104mb on each hci instance.
> 
> Currently running 32 threads at 3104mb per instance, but this only loads 102/128gb of my ram. Can I run more than 32 threads to approach 95% of ram load?


the max is a windows thing. cant really do anything about it.

you can run as many threads as needed to cover ram usage. doesnt need to be synced to thread count on CPU.


----------



## ssateneth

Quote:


> Originally Posted by *coreykill99*
> 
> what is this exactly? I have memtest pro. you say launcher does this just open a bunch of instances?


It simply opens a bunch of instances with X ram usage. It probably checks status if you hit the update button, but i havent used it much. I've been using "Dang Wang Version 2.5 2014/09/22" instead (and no, there is no virus in it. It's a false positive because of the way it manipulates the memtest processes position). And I purchased memtest pro in case any outcries of piracy. I just plop my 6.0 hci memtest in the %temp% directory and make it read only so dang wang doesnt overwrite it.


----------



## ZeNch

Quote:


> Originally Posted by *Valter84*
> 
> Hello guys.
> 
> Placing my findings with my ryzen 1700 @ 3.9ghz, asus prime x370 pro and HyperX Predator hx432c16pb3k2/16.
> Soc voltage @ 0.95v (llc3) and Ram voltage @ 1.36
> 
> 
> I am a litle dummy regarding ram OC, are this good results?
> Should I tweek more timings?
> 
> Thank you.


Your results of ram... close all programs>try again your test... your read/write/copy results need to be more than 40000 ._.

if your results are the same of your image, try to set more vSoc or more Dram Voltage... your results are VERY VERY low


----------



## ssateneth

Quote:


> Originally Posted by *ZeNch*
> 
> Your results of ram... close all programs>try again your test... your read/write/copy results need to be more than 40000 ._.
> 
> if your results are the same of your image, try to set more vSoc or more Dram Voltage... your results are VERY VERY low


His scores are low but not for the reason you think.

Your ram is operating in single channel mode. They are inserted in the wrong slots. Consult your motherboard manual for correct placement. Typically the placement for 2 DIMMs on ryzen is the 2nd and 4th slot furthest from the CPU socket.

Once you get the dual channel issue sorted, you can gain some across-the-board performance lowering your tRFC, since its operating at a stock timing of 560 (350 nanoseconds). Try numbers 210-280, lower is better but too low can cause instability, errors, or no-post (takes time to find a good number. Too low will not damage anything).

Other timings you can work on can GREATLY increase write and copy speeds. Look at tRDWR, tWRRD (manually set it if you have to), tWRWRSD, tRDRDSD. Make sure tWRWRSC and tRDRDSC remain 1.


----------



## ZeNch

Quote:


> Originally Posted by *ssateneth*
> 
> His scores are low but not for the reason you think.
> 
> Your ram is operating in single channel mode. They are inserted in the wrong slots. Consult your motherboard manual for correct placement. Typically the placement for 2 DIMMs on ryzen is the 2nd and 4th slot furthest from the CPU socket.


Good point...
mb per sec. /2 is for single channel (64bits vs 128bits)

@Valter84


----------



## AndreiD

Quote:


> Originally Posted by *geoxile*
> 
> I passed a few different hour runs on Linux, it's Windows that's the problem it seems. Also passed 800% HCI run on 16x850MB after reinstalling Windows and that passed but Windows FCU GSAT still fails.


Does seem to be an issue with FCU since they changed how you install bash. Guess it's just best to run Mint from an USB stick and run GSAT in that rather than Windows.


----------



## fas7play

hello overclock.net,
playing around with my new system.









[email protected] 1.1v---Asrock AB350M Pro4 BIOS 3.00---HCI---400%---F4-3200C14D-16GTZSW



to determine which timings have a positive effect, i collected some data. (no cpu oc during test ...)
=> BGS ON/OFF with no impact.
=> GDM for a bit more stability


template:
stilts settings + setting of a korean dude and some values out of 1usmus tool.

So far I have been able to gather very little informations:
tFAW: [16]
=> AMD: [Configured to a minumum 4x tRRD_S, but values >8x tRRD_S are often used for stability.]
(i may go with more relaxed timings [20+], no heavy impact on performance.)

tWR: [10]
=> [AMD: Higher values are often beneficial for stability, and values < 8 can quickly corrupt data stored in RAM.]

tWTRS [3] + tWTRL [7]
=> on AIDA64 i saw a boost for WRITE + COPY... any thoughts?

tWRWRSCL [2] + tRDRDSCL [2]
=> performance booster! / i tried to build around this values..

tCWL [14] + tRTP [8] + tRDWR [6] + tWRRD [3]
=> no influence on the speed / stability problems with smaller values

tWRWRSD [5] + tWRWRDD [5] + tRDRDSD [3] + tRDRDDD [3] + tCKE [1]
=> no impact, no informations about this values...

tRC [42]
=> AMD: [Lower values can notably improve performance, but should not be set lower than tRP+tRAS for stability reasons.]

tRFC [267]
=> 255 is possible but has a great influence on stability.

if you could give me more information on the individual values, thanks?

greetings from austria


----------



## 1usmus

Quote:


> Originally Posted by *fas7play*
> 
> hello overclock.net,
> playing around with my new system.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [email protected] 1.1v---Asrock AB350M Pro4 BIOS 3.00---HCI---400%---F4-3200C14D-16GTZSW
> 
> 
> 
> to determine which timings have a positive effect, i collected some data. (no cpu oc during test ...)
> => BGS ON/OFF with no impact.
> => GDM for a bit more stability
> 
> 
> template:
> stilts settings + setting of a korean dude and some values out of 1usmus tool.
> 
> So far I have been able to gather very little informations:
> tFAW: [16]
> => AMD: [Configured to a minumum 4x tRRD_S, but values >8x tRRD_S are often used for stability.]
> (i may go with more relaxed timings [20+], no heavy impact on performance.)
> 
> tWR: [10]
> => [AMD: Higher values are often beneficial for stability, and values < 8 can quickly corrupt data stored in RAM.]
> 
> tWTRS [3] + tWTRL [7]
> => on AIDA64 i saw a boost for WRITE + COPY... any thoughts?
> 
> tWRWRSCL [2] + tRDRDSCL [2]
> => performance booster! / i tried to build around this values..
> 
> tCWL [14] + tRTP [8] + tRDWR [6] + tWRRD [3]
> => no influence on the speed / stability problems with smaller values
> 
> tWRWRSD [5] + tWRWRDD [5] + tRDRDSD [3] + tRDRDDD [3] + tCKE [1]
> => no impact, no informations about this values...
> 
> tRC [42]
> => AMD: [Lower values can notably improve performance, but should not be set lower than tRP+tRAS for stability reasons.]
> 
> tRFC [267]
> => 255 is possible but has a great influence on stability.
> 
> if you could give me more information on the individual values, thanks?
> 
> greetings from austria


Understated values tRRDS/tRRDL -> tFAW performance will not increase.
The restriction is purely electrical - the activation takes a lot of energy, and therefore with frequent line activations, the electrical load on the circuit is very high. To reduce it, this delay was introduced.

tWRWR / tRDRD
Minimum delay between two commands for reading or writing in different/same rankings.

tCKE
waiting for the attenuation of digital noise, 1 - automatic mode


----------



## Valter84

Quote:


> Originally Posted by *ZeNch*
> 
> Your results of ram... close all programs>try again your test... your read/write/copy results need to be more than 40000 ._.
> 
> if your results are the same of your image, try to set more vSoc or more Dram Voltage... your results are VERY VERY low


Thank you very much, I have found that I had only one of the ram dims properly inserted in my mobo :S!

New benchmark result:


Should I change some timings?

My rig-> ryzen 1700 @ 3.9ghz, asus prime x370 pro and HyperX Predator hx432c16pb3k2/16.
Soc voltage @ 0.95v (llc3) and Ram voltage @ 1.36


----------



## happyluckbox

So my 128gb of gskill ram is stable at 3060mhz in everything outside of HCI memtest. During HCI, I get 1-2 memory errors every hour or so. So nothing crazy, but clearly HCI is discovering some instabilities. This is with 32 threads running on my threadripper 1950x.

Any tips on how I can stabilize 3060mhz, short of downclocking to 2933mhz?

Already tried differing levels of vsoc, including under and overvolting.

Also tried undervolting PLL.

Can changes in vddp (cpu soc sb voltage) help? If so, undervolting or overvolting?


----------



## Paarthurnax

Ppl, can u help me ? idk much about memory overclock ( Actually is my first time trying ) and i'm a bit confuse about latency!

how can i know what is a good latency or a bad latency ?

I already made a overlock and didnt know if my latency is good or a completely ****


----------



## Milestonegio

[email protected] 1v---BIOS 1001---HCI---1550%---416G3000HC16CDC01

I use 1600 + B350 Strix + 2x8GB Team Group T-Force DARK 3000MHz C16-18-18-38 (Dual Rank Samsung S-Die).

I spent a lot of time trying to stabilize RAM at 3066 C16-18-18-36 combine Safe/Fast settings from Ryzen Timing Calculator and I get it to work at 1.475V on DRAM and 1.175V on SOC.
Btw, ASUS mobo does very good job by default (About 90% of values are correct).

Right before stressing I just decided to try 2933MHz and started from 14-18-18-36 just for fun&#8230; and it was stable. Then I tried 14-16-16-34 and I was shocked - It seemed to be stable. I started lowering voltages and end up at 1V for SOC and 1.35V DRAM. After that I opened web version of RTC to understand how to squeeze secondary timings because App gives me timings for 2933 16-17&#8230; whatever. I successfully applied few of them and realize that I can just lower freq in RTC until I get 14-16-16-34 primaries. Then I squeeze secondaries even more using presets for 2666MHz. There you have it


----------



## 1usmus

Quote:


> Originally Posted by *Milestonegio*
> 
> [email protected] 1v---BIOS 1001---HCI---1550%---416G3000HC16CDC01
> 
> I use 1600 + B350 Strix + 2x8GB Team Group T-Force DARK 3000MHz C16-18-18-38 (Dual Rank Samsung S-Die).
> 
> I spent a lot of time trying to stabilize RAM at 3066 C16-18-18-36 combine Safe/Fast settings from Ryzen Timing Calculator (Btw, ASUS mobo does very good job by default. About 90% values are the same). I get it to work at 1.475V on DRAM and 1.175V on SOC.
> Right before heavy stressing I just decided to try 2933MHz and started from 14-18-18-36 just for fun&#8230; and it was stable. Then I tried 14-16-16-34 and I was shocked - It seemed to be stable. I started lowering voltages and end up at 1V for SOC and 1.35V DRAM. After that I opened web version of RTC to understand how to squeeze secondary timings because App gives me timings for 2933 16-17&#8230; whatever. I successfully applied few of them and realize that I can just lower freq in RTC until I get 14-16-16-34 primaries. Then I squeeze secondaries even more using presets for 2666MHz. There you have it


pls upload launcher RunMemTestPro 3.0


----------



## Milestonegio

Pressed "Reply" but i'm not sure if i did it correctlty. Btw, you have no idea what I went through to get this after i've seen screen at G.Skill website...

HCIDangWang.zip 588k .zip file


----------



## happyluckbox

Hey all, TR 1950x.

I'm able to get 128gb running at 3060mhz 14cas.

It's very stable, but it does get 1 or 2 errors every hour or so running HCI memtest. This issue doesn't occur if I downclock to 2933mhz. I'm certain its the IMC and not the ram.

Increasing vsoc to 1.2v seems to reduce the amount of errors, as does increasing vddp from .91 to .95.
PLL voltage changes and secondary ram timings don't seem to make a difference.

Are there any other changes I can make to help eliminate these ram errors? The errors cause crashes when I use research software that fully loads my ram to 120gb. Outside of HCI memtest and my research software however, its 100% stable in p95, aida, games, etc. So I know its barely unstable. I'm sure there is some setting or voltage that will fix this. Currently playing with CAD bus OHM resistances.


----------



## chroniclard

Hmm, I had one error after 8 hours(over 4000%) of memtest, would you bother trying to iron that out or not?


----------



## Milestonegio

Quote:


> Originally Posted by *chroniclard*
> 
> Hmm, I had one error after 8 hours(over 4000%) of memtest, would you bother trying to iron that out or not?


How could you get over 4000% in 8 hours? Check my screen on this page, i've only 1500% in 8+ hours.


----------



## chroniclard

Quote:


> Originally Posted by *Milestonegio*
> 
> How could you get over 4000% in 8 hours? Check my screen on this page, i've only 1500% in 8+ hours.


Set it going last night, 16 instances, this morning had over 4000%?

CPU? Mines 1700x @ 3925,or you have older memtest?

Ah, also you are doing 12 threads of 1150, I am doing 16 threads of 850.


----------



## AndreiD

Quote:


> Originally Posted by *geoxile*
> 
> Anyone run into a case where stressapptest fails in Windows but passes in Linux mint? I'm running mint from usb and it passed a 45min test while it'll fail in a few minutes in Windows FCU. OS aside the only other big difference is Windows has AMD drivers installed
> 
> 
> 
> Pic of my 2hr pass in mint. Using settings and timings for 8GBx2 Trident Z 3200C14 provided by the calculator above ^
> 
> Problem is I can't get it to pass in Windows...
> 
> Edit: Just noticed something severely wrong with the test in Linux, it's not clocking to 3200!


Just did the GSAT in Windows 1703 (pre-FCU) and I'm completely stable at settings that would fail if I did GSAT via bash in FCU:

So I'm almost certain it's an FCU issue at this point. If you're on FCU i think you should go the HCI Memtest route instead until Microsoft properly fix all of the FCU issues.

Hope this helps


----------



## chroniclard

Ok, gonna call this stable. (Is 1 hour GSAT long enough?)

Chroniclard [email protected] 1.1v---BIOS 0052---GSAT 1 hour Corsair LPX CMK32GX4M4B3466C16


----------



## Valter84

My results for 1hour GSAT.

[email protected] 1.05v---BIOS 1001---GSAT 1 hour - HyperX Predator hx432c16pb3k2/16


----------



## iNeri

Hi guys.

Somebody knows if this kit are samsung b-die???

https://www.amazon.com/Patriot-PVE416G373C7KRD-Viper-Elite-memory/dp/B01KBKHP5Q/ref=sr_1_1?ie=UTF8&qid=1509808677&sr=8-1&keywords=patriot+3733&dpID=41xOnG8GNIL&preST=_SY300_QL70_&dpSrc=srch

This are CL [email protected] mhz


----------



## Jeager

I'm sorry guys but GSAT seems ****, I run it for almost 3 jours without any errors but wasnt able to benchmark on x264 nor pass prime95 in blend. Even with timing lowered I had errors after in HCI


----------



## chroniclard

hmm, so I did GSAT 1 hour and 600% memtest, all passed fine. Last night I left memtest running and came down this morning, 4000%+ with a load of errors.

Could the ram be overheating or is it just not stable.....?


----------



## Jeager

For me it's not stable.
If you quickly want to check your ram, run some x264 bench or realbench, if it's stable you can memtest to confirm your oc is 100% stable.

I think I was stable too with good timing but in the end i wasnt able to bench normal x264


----------



## x58haze

I was wondering if someone can guidance me a little, do you think that, I should configured my rams as fast preset? if so, should I, configure all manually, with all options displayed in the (Ryzen Dram Calculator)

Like all cad options settings manually, all rtt, the proc0t, the VTT, PPL, VPP, CLD0, VDDP, SOC, Dram and so on?

I have an asrock b350 chipset fatality k4 gaming, with a Ryzen cpu 5 1600, plus 2 kit of ram patriot 2x4 (total of 8 gigs)

Thaiphon burner photos:


XMP PARAMETERS:


Ryzen-Dram Calculator:


I'm using latest bios 3.20, hope someone can guidance me thanks


----------



## sakae48

@x58haze if your RAM could run on fast timing, sure why not?








try at safe timings first then try the fast one. fast timing could require higher voltage

so, i've been OC'd my RAM to 3600 using fast timing at 1.5v (that thing won't boot at all under 1.48v so i decided to use 1.5v instead for more stability). then, i decided to go 3866 but no luck. being dumb i decided to go 3600 extreme at 1.52v. ofc it doesnt work at all. i need to open the glass panel and do clear cmos









and now, i can't run at 3600 at 1.5v anymore. it throws error just in 0.5% pass in HCI, youtube crashed several times, BSOD, blah blah blah.
going back 3466 fast, still errored. now i'm back to 3333 fast. didn't do HCI just because i don't want to see another error. did i hurt my kits that bad?


----------



## x58haze

Quote:


> Originally Posted by *sakae48*
> 
> @x58haze if your RAM could run on fast timing, sure why not?
> 
> 
> 
> 
> 
> 
> 
> 
> try at safe timings first then try the fast one. fast timing could require higher voltage
> 
> so, i've been OC'd my RAM to 3600 using fast timing at 1.5v (that thing won't boot at all under 1.48v so i decided to use 1.5v instead for more stability). then, i decided to go 3866 but no luck. being dumb i decided to go 3600 extreme at 1.52v. ofc it doesnt work at all. i need to open the glass panel and do clear cmos
> 
> 
> 
> 
> 
> 
> 
> 
> 
> and now, i can't run at 3600 at 1.5v anymore. it throws error just in 0.5% pass in HCI, youtube crashed several times, BSOD, blah blah blah.
> going back 3466 fast, still errored. now i'm back to 3333 fast. didn't do HCI just because i don't want to see another error. did i hurt my kits that bad?


Woah thats sound terrible







, and why would you go up above 3.6 which that is basically the best at the moment, to get the most from latest GTX 1080 only? in games such hitman that actually benefit from 3200mhz, like +25 fps extra. so is not point to push more than 3.6 atm , only if you really want to be in the top-overclockers or bench-markers, if that so, then you can push and push

but yeah 3.2 is very good to be honest even the gtx 1060 between 2.135 hz to 3200 the boost in some games are like 10%, while on gtx 1070, is like 30%, and 1080gtx is just 40% and just in certain games not all games, like a margin of 3-5 games

But yeah there is not reason to go over 3.5 at least you are overclocking for Top benchs or etc ,thats all i know

And hope your ram are ok, all can i say, try to reseat your CPU, and Memory cards

But before that, have you try to clean your Rams?

If no try to grab an eraser and clean the contact, like putting some pressure don't worry, them in both sides, then just blow that, second just grab a little be of alcohol and careful clean the contact with a cloth, then, just put the ram again properly, then reset your CPU take off from the socket, wait for 20 sec, and put it back, and please ensure that you have your power-cord unplugged and ensure that your Lithium battery is removed too

then just put the cpu back, put the lithium battery back, plug everything and grab that software memory test, open 8 new windows of that and calculated ram regardless to your 8 gigs, or 16 or 32 etc ,etc
My english is not that good sorry.


----------



## sakae48

Quote:


> Originally Posted by *x58haze*
> 
> Woah thats sound terrible
> 
> 
> 
> 
> 
> 
> 
> , and why would you go up above 3.6 which that is basically the best at the moment, to get the most from latest GTX 1080 only? in games such hitman that actually benefit from 3200mhz, like +25 fps extra. so is not point to push more than 3.6 atm , only if you really want to be in the top-overclockers or bench-markers, if that so, then you can push and push
> 
> but yeah 3.2 is very good to be honest even the gtx 1060 between 2.135 hz to 3200 the boost in some games are like 10%, while on gtx 1070, is like 30%, and 1080gtx is just 40% and just in certain games not all games, like a margin of 3-5 games
> 
> But yeah there is not reason to go over 3.5 at least you are overclocking for Top benchs or etc ,thats all i know
> 
> And hope your ram are ok, all can i say, try to reseat your CPU, and Memory cards
> 
> But before that, have you try to clean your Rams?
> 
> If no try to grab an eraser and clean the contact, like putting some pressure don't worry, them in both sides, then just blow that, second just grab a little be of alcohol and careful clean the contact with a cloth, then, just put the ram again properly, then reset your CPU take off from the socket, wait for 20 sec, and put it back, and please ensure that you have your power-cord unplugged and ensure that your Lithium battery is removed too
> 
> then just put the cpu back, put the lithium battery back, plug everything and grab that software memory test, open 8 new windows of that and calculated ram regardless to your 8 gigs, or 16 or 32 etc ,etc
> My english is not that good sorry.


well.. i cant help myself to not to reach higher numbers








that reason somehow backfired on me









now running 3333 and holy cow there's lots of errors! i'll clean them later. hope it fix tho..


----------



## Valter84

Quote:


> Originally Posted by *Jeager*
> 
> For me it's not stable.
> If you quickly when to check if you ram is stable, run some x264 bench or realbench, if it's stable you can memtest to confirm your oc is 100% stable.
> 
> I think I was stable too with good timing but in the end i wasnt able to bench normal x264


Same for me, GSAT runs ok, but memtest fails.
NOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO!


----------



## Chris1182

Hi Guys,

my results :

Chris1182 -- 1800x @ 4.0 --- 3333Mhz - C14 - 14 - 14 - 14 -- 28 - 1T --- 1.35v --- SOC 1.05v --- BIOS 1501 --- HCI 1000% - G.Skill F4-3600C15D - 16GTZ



Chris1182 -- 1800x @ 4.0 --- 3466Mhz - C15 - 15 - 15 - 15 -- 35 - 1T --- 1.35v --- SOC 1.05v --- BIOS 1501 --- HCI 1000% - G.Skill F4-3600C15D - 16GTZ



I am still looking for 3466Mhz - C14 - 14 - 14 - 14 - 28 , but unfortunately I get an error at 200 - 380%

In my system I have found, the more voltage I give, the faster come the errors

Sorry for my bad english









regards Chris


----------



## Jeager

Quote:


> Originally Posted by *Chris1182*
> 
> Hi Guys,
> 
> my results :
> 
> Chris1182 -- 1800x @ 4.0 --- 3333Mhz - C14 - 14 - 14 - 14 -- 28 - 1T --- 1.35v --- SOC 1.05v --- BIOS 1501 --- HCI 1000% - G.Skill F4-3600C15D - 16GTZ
> 
> 
> 
> Chris1182 -- 1800x @ 4.0 --- 3466Mhz - C15 - 15 - 15 - 15 -- 35 - 1T --- 1.35v --- SOC 1.05v --- BIOS 1501 --- HCI 1000% - G.Skill F4-3600C15D - 16GTZ


What are the benchmark dif between stable 3333 & 3466 ?


----------



## Chris1182

Quote:


> Originally Posted by *Jeager*
> 
> What are the benchmark dif between stable 3333 & 3466 ?


1800x @ 4.0 - 3333Mhz - C14 - 14 - 14 - 14 - 28 - 1T



1800x @ 4.0 - 3466Mhz - C15 - 15 - 15 - 15 - 35 - 1T



1800x @ 4.0 - 3466Mhz - C14 - 14 - 14 - 14 - 28 - 1T



*NEW Result :*









Chris1182 -- 1800x @ 4.0 --- 3466Mhz - C14 - 14 - 14 - 14 -- 28 - 1T --- 1.365v --- SOC 1.05v --- BIOS 1501 --- HCI 1000% - G.Skill F4-3600C15D - 16GTZ


----------



## Jeager

Quote:


> Originally Posted by *Chris1182*
> 
> 1800x @ 4.0 - 3333Mhz - C14 - 14 - 14 - 14 - 28 - 1T
> 
> 1800x @ 4.0 - 3466Mhz - C15 - 15 - 15 - 15 - 35 - 1T
> 
> 1800x @ 4.0 - 3466Mhz - C14 - 14 - 14 - 14 - 28 - 1T
> 
> *NEW Result :*
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Chris1182 -- 1800x @ 4.0 --- 3466Mhz - C14 - 14 - 14 - 14 -- 28 - 1T --- 1.365v --- SOC 1.05v --- BIOS 1501 --- HCI 1000% - G.Skill F4-3600C15D - 16GTZ


Nice, look like 3333 is better than 3466 at 15 except on the winrar bench


----------



## Particle

Not having much luck here. I purchased some DDR4-3333 hoping for 2933 or 3200, but the system falls back to 2133 when set to anything over 2666. I'm using a 1700X with a Crosshair VI Hero, but it's not on the latest firmware. I'll try the firmware ASUS released on 2017-10-03 and report back.


----------



## Atomfix

G.Skill Trident Z 3000MHz CL16 16GB 1.35V Kit

Overclocked to 3200MHz CL 16-16-15-36 1T 1.38V (Fluctuates to 1.4V in HWinfo64)

Ryzen 1700 3.6GHz 1.21V Forgot to add stability screenshots. It did pass 1 hour of Prime 95 on custom settings to eat all my RAM up









https://valid.x86.fr/usr4ug


----------



## nexxusty

Quote:


> Originally Posted by *Particle*
> 
> Not having much luck here. I purchased some DDR4-3333 hoping for 2933 or 3200, but the system falls back to 2133 when set to anything over 2666. I'm using a 1700X with a Crosshair VI Hero, but it's not on the latest firmware. I'll try the firmware ASUS released on 2017-10-03 and report back.


Thats not at all how memory works with Ryzen.

I suggest you do some more reading man, I could have told you that you were wasting money my friend.

Anyway... with Ryzen you buy Samsung B-Die IC's if you want any hopes of attaining any speed other than 2133, 2400, 2666. e.g slow ass speeds.

Immediately return that RAM and buy some G.Skill Trident Z or Ripjaws V. 3600mhz CAS 16.


----------



## Particle

Quote:


> Originally Posted by *nexxusty*
> 
> Thats not at all how memory works with Ryzen.
> 
> I suggest you do some more reading man, I could have told you that you were wasting money my friend.
> 
> Anyway... with Ryzen you buy Samsung B-Die IC's if you want any hopes of attaining any speed other than 2133, 2400, 2666. e.g slow ass speeds.
> 
> Immediately return that RAM and buy some G.Skill Trident Z or Ripjaws V. 3600mhz CAS 16.


You're kind of presumptive. The memory I have is Ripjaws V Samsung B die. It works fine at 3066 with the latest BIOS. Memory support was rough with the early firmware releases. Reading told me this. That's why I bought what I did and why I updated the BIOS.


----------



## Gadfly

My first post here, LMK if I didn't do something right:

Gadfly -- 1800x @ 4.1 --- 3466Mhz - C14 - 14 - 14 - 14 -- 28 - 1T --- 1.47v --- SOC 1.15v --- BIOS 0052 --- HCI 2299% - G.Skill F4-3600C15D - 16GTZ


----------



## ZeNch

Quote:


> Originally Posted by *Gadfly*
> 
> My first post here, LMK if I didn't do something right:
> 
> Gadfly -- 1800x @ 4.1 --- 3466Mhz - C14 - 14 - 14 - 14 -- 28 - 1T --- 1.47v --- SOC 1.15v --- BIOS 0052 --- HCI 2299% - G.Skill F4-3600C15D - 16GTZ


wow, really good!! cinebench 15 score?


----------



## Gadfly

Quote:


> Originally Posted by *ZeNch*
> 
> wow, really good!! cinebench 15 score?


----------



## nexxusty

Quote:


> Originally Posted by *Particle*
> 
> You're kind of presumptive. The memory I have is Ripjaws V Samsung B die. It works fine at 3066 with the latest BIOS. Memory support was rough with the early firmware releases. Reading told me this. That's why I bought what I did and why I updated the BIOS.


I'm kind of presumptuous because nobody has issues like that with B-Die on a CH6 with properly functioning hardware....

Maybe hardware issues?

I would start looking at the this, you should easily be able to use the profiles within the UEFI to obtain 3200mhz or 3466mhz. Haven't used a kit of B-Die yet that couldn't. Easy, easy profiles for B-Die to do.

The IC's are capable of much, much more than 3466mhz CAS 14.... This COULD be a weak IMC.... howwver again... I've never had an IMC that couldnt do at least 3200mhz CAS 13 with B-Die.

You have 2x8gb correct?


----------



## Silent Scone

Quote:


> Originally Posted by *nexxusty*
> 
> I'm kind of presumptuous because nobody has issues like that with B-Die on a CH6 with properly functioning hardware....
> 
> Maybe hardware issues?
> 
> I would start looking at the this, you should easily be able to use the profiles within the UEFI to obtain 3200mhz or 3466mhz. Haven't used a kit of B-Die yet that couldn't. Easy, easy profiles for B-Die to do.
> 
> The IC's are capable of much, much more than 3466mhz CAS 14.... This COULD be a weak IMC.... howwver again... I've never had an IMC that couldnt do at least 3200mhz CAS 13 with B-Die.
> 
> You have 2x8gb correct?


Your presumptions are very presumptuous indeed. All CPU are different in this regard and can be hit and miss depending on the given memory rules. Not every CPU will work without adjustment, you'd have been better off suggesting he tried looking under CBS and adjusting ProcODT values, as these can still be the difference between POST and no POST on some CPU with a given memory kit.


----------



## Particle

*DIMM Size & Memory Channels Used*
Your guess is correct in that I'm using 2 x 8 GiB. I can't run in the primary slots though due to clearance issues with the CPU heatsink. As such, the DIMMs are in DIMM_A2 and DIMM_B2 instead of DIMM_A1 and DIMM_B1. Has anyone tested the difference between those slots on a Crosshair VI? I've seen boards where the farther slots were better, boards where the nearer slots were better, and boards where it didn't seem to matter. I don't know which is the case with the Crosshair VI Hero.

*Using Default Settings*
So far I'm just using all default settings for the memory. I wanted to see how far it could go without fine tuning anything since I'm shipping this system off to a friend. If there aren't many settings to change though, I'd like to try for 3200 or 3333. My friend is primarily a gamer and is on very old Intel hardware now (i5 2500K). He switched from AMD to Intel and was really turned off by the FX series. He also wasn't impressed by Ryzen at launch because of its 5-10% deficit to Skylake in gaming workloads in the initial launch reviews. As such, I want that 5-10% boost from high memory frequencies since it will mostly close the gap in his workloads. It's more about painting a good mental image for him than it is tangile performance since 5-10% is hardly perceptible. A person needs to feel good or proud about their system in order to be satisfied. I don't want him to feel like he's upgrading to a second-rate platform (even though even at DDR4-2400 it's clock for clock already faster than his Sandy Bridge).

*BIOS / Firmware Results With Default Settings*
When I first posted here, the board was running firmware 1107 which is dated May 4, 2017. I see that ASUS seems to have pulled that release from their website. On that version it wouldn't POST at anything beyond DDR4-2666. I updated the board to firmware 1703 which is dated 2017-10-03 last night. On that version it would POST at anything up to 3066, though I eventually found that 3066 doesn't work on every startup reliably. If it does POST at 3066, the memory seems to work without errors though.

*Fine Tuning Plans*
I've not tried changing ProcODT, but a search on this thread suggests that 60 ohms is a common setting people have found success with in the past. Is that accurate? What is the default value when set to auto? Are there other settings I should read about?


----------



## Gadfly

I tightened my timings up just a touch:

Gadfly -- 1800x @ 4.1 --- 3466Mhz - C14 - 14 - 14 - 14 -- 28 - 1T --- 1.47v --- SOC 1.1375v --- BIOS 0052 --- HCI 4370% - G.Skill F4-3600C15D - 16GTZ




Now to keep working on 3600. I am almost there... I might have to try 16-15-15-32 or something as 3600 CL15 appears to be just a touch beyond stability for my DIMMS.


----------



## Particle

Quote:


> Originally Posted by *Gadfly*
> 
> I tightened my timings up just a touch:
> 
> Gadfly -- 1800x @ 4.1 --- 3466Mhz - C14 - 14 - 14 - 14 -- 28 - 1T --- 1.47v --- SOC 1.1375v --- BIOS 0052 --- HCI 4370% - G.Skill F4-3600C15D - 16GTZ
> 
> Now to keep working on 3600. I am almost there... I might have to try 16-15-15-32 or something as 3600 CL15 appears to be just a touch beyond stability for my DIMMS.


What all have you had to adjust in your pursuit of higher frequencies?


----------



## Particle

I tried adjusting the ODT setting when I got home from work earlier. I tried 53.3, 60, 80, and 96 ohms but none of them would allow me to POST at 3200. The best I seem to be able to get is 3066, and even that fails during training on maybe 1 in 3 boots. Are there any other settings which help? ODT didn't seem to make any perceptible difference for me. DIMM voltage seems to make no difference even at 1.44 volts.


----------



## The Sandman

The [email protected] 1.08125v---BIOS 9920---HCI---1500% 8.5 hrs--- F4-3200C14D-16GFX





Various stress tests


Spoiler: Warning: Spoiler!













Bios text file

39253466tight11417_setting.txt 19k .txt file


----------



## nexxusty

Quote:


> Originally Posted by *Gadfly*
> 
> I tightened my timings up just a touch:
> 
> Gadfly -- 1800x @ 4.1 --- 3466Mhz - C14 - 14 - 14 - 14 -- 28 - 1T --- 1.47v --- SOC 1.1375v --- BIOS 0052 --- HCI 4370% - G.Skill F4-3600C15D - 16GTZ
> 
> 
> 
> 
> Now to keep working on 3600. I am almost there... I might have to try 16-15-15-32 or something as 3600 CL15 appears to be just a touch beyond stability for my DIMMS.


Have you not noticed in comparison to others, your latency and your copy is low?









I'd take a look at that. Almost 70ns for 3466 C14 1T is not right. As well as 48000mb/s copy, should be over 50000mb/s for sure, closer to 51-52000mb/s.


----------



## Gadfly

Quote:


> Originally Posted by *nexxusty*
> 
> Have you not noticed in comparison to others, your latency and your copy is low?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I'd take a look at that. Almost 70ns for 3466 C14 1T is not right. As well as 48000mb/s copy, should be over 50000mb/s for sure, closer to 51-52000mb/s.


Latency is on par for those timings, copy is lower since alt swap is disabled. It will bench lower, but real world performance is higher.

Here is the exact same system, exact same settings, and exact same timings, just with BankGroupSwapAlt enable:


----------



## Particle

The Crosshair VI firmware 1703 contains memory timing presets for various memory configurations it seems. I tried the "safe" 3200 one but it wouldn't POST. I tried about every termination impedance between 53.3 and 96 ohms. I watched that video of the AMD guy going over memory overclocking, but after a few minutes it became clear that he had no idea what he was talking about when he tried to give technical explanations. As an example, he warned that going over 120 ohms for ODT would be dangerous unless you had liquid nitrogen. Total bull****. I design digital computer circuits as a hobby, and that's just simply not what that is. The higher numbers would actually impart less load on the signal drivers making them less dangerous from an electrical perspective. The real story is that you need termination to be balanced. The whole idea is that matching impedance on both sides of a signal line prevents electrical wave front propagation from having severe reflections once it makes it to the end of the conductor. Reflections kill signal quality. Poor signal quality means lower clock frequencies. Unbalanced by being too high is bad. Unbalanced by being too low is bad. Only a match is good, and that is a variable target when dealing with different slots and modules. The modules themselves are static, so that is why they would design the memory controller to be able to vary its own termination.


----------



## Aby67

it is interesting to read this ram thread, but I cant just avoid asking myself.....is the effort worth, if zen 2 is 60 days from now and likely see ryzen 7 chips have threadripper like performance?!...and what memory stunts will come from samsung along all of their line including znand?


----------



## Anty

Wut? Zen2 is not in 60 days....
Zen+ will be in early 2018 which is only die shrink, same arch as current ryzen.
Secon it is unlikely Zen2 will same perf as current threadripper.


----------



## chroniclard

People like to tweak/overclock as much as possible. Is it worth it? There are gains to be had, upto a point.


----------



## sakae48

worth to someone wants to push their system to the limit









there's people who push their system to the optimal point where any higher speed won't give significant gain

and there's people who push their system to the maximum possible where only 1 point gain means an improvement


----------



## reptilee

Hello All!

Can anybody help me hit 3066mhz? I can get just 2933mhz.

My set-up is B350 Tomahawk Arctic with 1600 and G.Skill 16GB (2x8GB), Ripjaws V, DDR4 3200MHz, (F4-3200C16D-16GVKB) 16-16-16-36.

Any tricks & tips? =)

And btw is here somewhere new BIOS for the arctic, because non-Arctic get more updates. Can I put Tomahawk BIOS to my Arctic?

MSI_SnapShot.bmp 2304k .bmp file


----------



## Aby67

Quote:


> Originally Posted by *Anty*
> 
> Wut? Zen2 is not in 60 days....
> Zen+ will be in early 2018 which is only die shrink, same arch as current ryzen.
> Secon it is unlikely Zen2 will same perf as current threadripper.


Zen 2 should be announced at CES this January with early adopters like reviewers having hands on in February.
As for ONLY die shrink, I want to remind You that die shrink for eg Nvidia meant precisely doubling the performance with the same memory type, and quadruplicating with HBM2.
I dont know if AMD will use a Intel like marketing strategy and offer lower performance Ryzen 2 series to milk they clients for a year, but if they do not, then I can assure to You that We looking at double the performance gains while a in worst case scenario at least 60%......60% performance gain will see top overclockers getting scores above 2500 in cinebench...and that is if Samsung will not upgrade their RAM performance...something that I am unwilling to believe.
So if a 2800x will score 3000/3200 or 2500 on cinebench and if it will stay with 8 cores or go up as much as 16 cores is all at the discretion of AMD policy and yealds.
In a Idilliac scenario if they have fantastic yealds during the manufacturing process, then We could very well see 16 core Ryzen 7 cpus, capable from anything from 4500 to 6000 points in cinebench.
https://www.youtube.com/watch?v=RwF5XewHmU8
Anyhow, We will keep eyes on Samsung and see what they are up to for ram Memory.


----------



## sakae48

i thought it was Zen refresh, no? this is the 12nm node, right?


----------



## Jeager

Same product with a die shrink won't mean performance boost, maybe less voltage/heat and more mhz but that's all


----------



## Aby67

Quote:


> Originally Posted by *sakae48*
> 
> i thought it was Zen refresh, no? this is the 12nm node, right?


Good question....was though to be a 12nm process all the way till the moment that apparently AMD declared going directly to 7nm....so as the the whole Zen architecture is mainly focused around power efficiency availability and bandwidth...what will happen that You will see new cpus needing much less power to deliver the same current performance....a 8 core cpu would be much much smaller as well...so they will be for sure making 16 core cpus, only that it is unknown if they will use them for the consumer grade market or if those will go only for EPYC and Threadripper...it would be odd not to see 64 core EPYC chips later in 2018. It owuld indicate bad yealds at 7nm and definitely a very high price increase on all AMD line up.
The fact that they have not released Threadripper 24 and 32 core cpus hints that Ryzen 2 will stay on 8 cores, but if they will release Threadripper in CES with 32 cores, then no doubt there will be 16 core Ryzen 7s capable of clocking way above 4.0Ghz.
the fact that Threadripper prices are bing discounted in these days while at the same time selling like bread, hints that Zen2 will definitely have a massive increase in performance no doubt.
You do need to keep in mind that Global Foundries and AMD are basically Samsung today........You know Samsung?! that company that gives a very hard time to apple and many others somewhere in south east asia?!


----------



## Anty

I don't know where did you get this info. All sources adhere to this:



Zen2 in 2019.
Second AMD is not nVidia. AMD is known to ALWAYS slip the schedule and expectations.
hird absolutely no hint where ryzen should have 16/32 configuration. Only optimistic sources say 6/12 per CCX.


----------



## Aby67

Quote:


> Originally Posted by *Anty*
> 
> I don't know where did you get this info. All sources adhere to this:
> 
> 
> 
> Zen2 in 2019.
> Second AMD is not nVidia. AMD is known to ALWAYS slip the schedule and expectations.
> hird absolutely no hint where ryzen should have 16/32 configuration. Only optimistic sources say 6/12 per CCX.


https://wccftech.com/amd-talks-ryzen-zen-2-ipc-clock-speed/

Please do note how much they emphasize Threadripper gaming and Multithreaded gaming being the thing from 2018.

Another video that might be interesting to see is about multi threaded gaming and the death of the I5

https://www.youtube.com/watch?v=RwF5XewHmU8&t=916s

As for AMD slipping schedules and expectations, ehm that is not the case for this gen CPUs, You not considering that current Zen cpus on 14 nm have almost 100% yealds, they are very simple cpus to make for AMD, opposite to a 18 or 24 core Intel massive chip


----------



## Anty

There is no info about retail zen2 being available next year.
AMD does not create games - how it looks now everybody knows.


----------



## Aby67

Quote:


> Originally Posted by *Anty*
> 
> There is no info about retail zen2 being available next year.
> AMD does not create games - how it looks now everybody knows.


I will grant You that it possibly not sure if Zen 2 will be announced this January and released February or in the summer, but it is 2018.
Yes AMD does not create games but it does provide the tools for content creators to create them on.
I am a content creator, and I can safely say that 2018 BIG thing is photo realism in gaming, which will lead into tons creators moving on into higher cpu count, and from there the next thing will be dynamic and way more advanced AI for NPC...
You are going to gradually see more and more character crowded game play (it if fits the story or game theme) behaving more and more as if human controlled.
There are already gaming platforms that can use more than 8 cores, even if zen never existed, but as it exists and now sells more than Intel, and because all consoles are based on AMD tech...the article with the interview I shared to You clearly explains that at AMD they were not sure if ZEN would ever trigger more cores for gaming, but that as a matter of fact it did, so we are in a situation were 4 cores are dead, and 6 cores are the next ones in a couple of years tops...hell there have been smart phones running on octacores for years now.
I can understand that You are Intel aficionado, and I am not saying that Intel does bad cpus, but the margin of improvement on AMD architecture at much better yealds (thus) much cheaper pricing warrant than even the 8700k will have a gaming supremacy for a few months, sooner or later zen 2 will be out, once drivers get optimized AMD will get the gaming supremacy title...and I have ALWAYS been an Intel client for years, and I am happy that now We have not only a choice but that all the content we make or use will be soooooooooooooo much superior because of 2017 AMD stunt and years of R/D they put into it, I can only be grateful and so should You...if it wasnt for AMD we would be still here now with the same crappy titles and same crappy limits in the content we can provide same as it was 5 years ago or more....and begging Nvidia to bring us more power than a 1080


----------



## Particle

Quote:


> Originally Posted by *reptilee*
> 
> Hello All!
> 
> Can anybody help me hit 3066mhz? I can get just 2933mhz.
> 
> My set-up is B350 Tomahawk Arctic with 1600 and G.Skill 16GB (2x8GB), Ripjaws V, DDR4 3200MHz, (F4-3200C16D-16GVKB) 16-16-16-36.
> 
> Any tricks & tips? =)
> 
> And btw is here somewhere new BIOS for the arctic, because non-Arctic get more updates. Can I put Tomahawk BIOS to my Arctic?
> 
> MSI_SnapShot.bmp 2304k .bmp file


I am in a similar boat with a Crosshair VI Hero and 2x8GB Ripjaws DDR4-3333. The talk seems to be that adjusting ProcODT manually and adding DIMM voltage are the two main ways to improve the success rate for memory training at POST. I didn't have any success with changing either of those. I suspect that if you don't either, you might just be out of luck. There isn't any magic that anyone has been able to offer to help me get past 2933 reliably either.


----------



## Quinteger

Hello, forum folks,
Anyone got any luck trying to overclock memory on ASUS Prime X370-Pro?
I was able to run my CMK16GX4M2B3466C16 E-die dual ranks at 3066 out of the box, but I still haven't found a way to stabilize on 3200, even on factory 3466 timings, tried numerous cad_bus and terminator settings.
CPU is 1600, currently runs at 3.7, 1.3v.


----------



## Atomfix

Is CL18 at 3200MHz better than CL15 3000MHz?

Managed to find some stable timings at 3200MHz until the new AGESA comes up. AIDA benchmark scores are better than CL15 3000MHz. Also heard that higher frequency is benefited to games hence trying to stay at 3200MHz

G.Skill Trident Z 3000MHz 16GB Kit. Hynix M-Die

F4-3000C15-8GTZB


----------



## reptilee

"I am in a similar boat with a Crosshair VI Hero and 2x8GB Ripjaws DDR4-3333. The talk seems to be that adjusting ProcODT manually and adding DIMM voltage are the two main ways to improve the success rate for memory training at POST. I didn't have any success with changing either of those. I suspect that if you don't either, you might just be out of luck. There isn't any magic that anyone has been able to offer to help me get past 2933 reliably either."

I managed reach 3066mhz just changing timings to > 16-18-18-18-36. ProcODT 60.

Now little testing and then chasing THE 3200mhz.


----------



## Jeager

Quote:


> Originally Posted by *Atomfix*
> 
> Is CL18 at 3200MHz better than CL15 3000MHz?
> 
> Managed to find some stable timings at 3200MHz until the new AGESA comes up. AIDA benchmark scores are better than CL15 3000MHz. Also heard that higher frequency is benefited to games hence trying to stay at 3200MHz
> 
> G.Skill Trident Z 3000MHz 16GB Kit. Hynix M-Die
> 
> F4-3000C15-8GTZB


Math tells us that 3000 CL15 is faster so unless you can do 3200 with a better CL I would stick to 3000 (you can try 3000 CL14 too







)


----------



## Xzow

Memtest passes for me at 3066mhz but WoW crashes often... CPU vcore and multiplier are default/auto.


----------



## Anty

Try google stressapptest instead of memtest.


----------



## Worldwin

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> GSAT is best for testing memory isolated stability. Understanding exactly what each tool does and what a failure or pass of each implies seems to be a major stumbling block for some.


The problem comes when results don't make sense.

Say for me: I can do [email protected] at 3.9 and 3466 on ram for 10hrs fine.

Memtest does 1000% and GSAT passes at 2hrs no problem. I still get crashes while I'm playing HOTS and once while I'm watching a youtube video. The confusion comes from when you crash under a drastically less intensive task. It leads to people wondering what really is wrong since its not easy to figure out.


----------



## Aby67

Quote:


> Originally Posted by *Xzow*
> 
> Memtest passes for me at 3066mhz but WoW crashes often... CPU vcore and multiplier are default/auto.


I will never understand why some people get 3200mhz timed at 14CL out of the box and others wont, others get 3600mhx at 16 cl work straight out of the box as well..
Would any one know if most Motherboard BIOS are still not mature or some motherboards are just really not good?!


----------



## ZeNch

Quote:


> Originally Posted by *Aby67*
> 
> I will never understand why some people get 3200mhz timed at 14CL out of the box and others wont, others get 3600mhx at 16 cl work straight out of the box as well..
> Would any one know if most Motherboard BIOS are still not mature or some motherboards are just really not good?!


IMC (internal memory controller) is in CPU no motherboard, ryzen is "beta" haha.

equally each chip of ram is different.


----------



## Aby67

Quote:


> Originally Posted by *ZeNch*
> 
> IMC (internal memory controller) is in CPU no motherboard, ryzen is "beta" haha.
> 
> equally each chip of ram is different.


Ryzen cannot be in beta because You cannot change a CPU controller once it is inside Your socket buddy....The Debugging happens in the software side with the BIOS....but then it is not that Motherboard manufacturers release their official Bios as Beta neither


----------



## ZeNch

Quote:


> Originally Posted by *Aby67*
> 
> Ryzen cannot be in beta because You cannot change a CPU controller once it is inside Your socket buddy....The Debugging happens in the software side with the BIOS....but then it is not that Motherboard manufacturers release their official Bios as Beta neither


true ryzen in beta no, am4 yes (bios is part of platform). am4 need omprovements to see his performance.

i have ram with M die (hinyx) [email protected] and im happy. but other peopple with same ram and mother cant go to XMP (DOCP) profile.

i like am4 but i change this platform for "AM4+" when this exist haha.


----------



## Jeager

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> GSAT is best for testing memory isolated stability. Understanding exactly what each tool does and what a failure or pass of each implies seems to be a major stumbling block for some.


It's far from being the best and it's closer to sorry. Never had issues when I was trying to find "uber timings" but I lost 2/3 days of tests because I wasn't able to run a x264 bench for more than 5m. Tried memtest/prime and voila


----------



## Praz

Quote:


> Originally Posted by *Jeager*
> 
> It's far from being the best and it's closer sorry. Never had issues when I was trying to find "uber timings" but I lost 2/3 days of tests because I wasn't able to run a x264 bench for more than 5m. Tried memtest/prime and voila


Hello

Seems the second part of my post applies to you. Any tool is only a means to accomplish an end. The user has to have the ability and knowledge to utilize the tool properly. And where are your entries in the chart of this thread? As HCI/GSAT does not find errors in your opinion you should be among the top entries but somehow I am not seeing your results.


----------



## miklkit

That list is meaningless. I passed the requirements to get on it months ago and never made it. Guess I'm not in the correct clique.


----------



## ssateneth

Memtest86 (not memtest86+) test #7 seems to be the quickest that I've used so far to illicit errors out of the system for ryzen threadripper (may apply to regular ryzen and intel platforms). I've used HCI (takes 2-6 hours to pop an error out) and GSAT (1 hour recommended but doesn't seem to pop them reliably). Memtest86 test #7 seems to pop them reliably in about 15 minutes. I'm using UEFI version of memtest86 pro 7.4. The free version lets you do specific tests too. The only difference I use pro vs free is a config file that jumps right to the specific test and X amount of passes automatically instead of manually changing it every time i start memtest


----------



## Esenel

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> Seems the second part of my post applies to you. Any tool is only a means to accomplish an end. The user has to have the ability and knowledge to utilize the tool properly. And where are your entries in the chart of this thread? As HCI/GSAT does not find errors in your opinion you should be among the top entries but somehow I am not seeing your results.


Quote:


> Originally Posted by *miklkit*
> 
> That list is meaningless. I passed the requirements to get on it months ago and never made it. Guess I'm not in the correct clique.


There are no updates. Just have a look at the used bios versions :-(

My 3466 CL15 entry lies 2 month in the thread :-D


----------



## Darkomax

3200CL13 at 1.39v, the best I could achieve since 3333CL14/3466CL15 is unstable (I could probably stabilize but at the cost of loosen timings and performance). Tried quickly C12 but it needs a steep voltage increase so I didn't bother.


----------



## gupsterg

@Chris1182

+rep thanks for shares, especially the 3466MHz C14 1T







. May have to dust off the C6H and place a CPU in it again







.

@Gadfly

+rep thanks for shares







, always interesting to read your tweaks







.

@Particle

Yeah I hate the Robert Hallock video.

a) LLC was touched on without giving correct info.
b) ProcODT was incorrect info.

Thankfully we had members like







The Stilt, [email protected], Elmor and Praz







, giving the correct info in the C6H thread prior to that awful "video"







.

Reads to me if your CPU has a memory hole for 3200MHz, you may find tinkering with CLDO_VDDP helps you.


----------



## Trender07

Any way guys for running to 3600 MHz? I got this ones samsung b-dies KFA2 (galax in usa i think) HOF 3600, but with its profile it won't boot at 3600 mhz. I am running at 3466 MHz now. For 3600 mhz I already tried setting 2T and geardown on, bankgroupswap enabled and 1.40V but still it won't boot at 3600


----------



## darkwizard

just ordered a F4-3200C14D-16GFX 16gb kit, soon I'll be playing with them and hopefully I can run at 3466 C14 on my CH6.


----------



## sandysuk

Never did post my stability results for my system.



[email protected] 4.1
3333Mhz -C14-13-13-26-1T----1.43v---- SOC 1.1875v---MSI X399 BIOS 1.5----HCI----2200% ----F4-3600C16Q-32GTZR


----------



## x58haze

Hey guys i was wondering if someone else here knows what chipset is my RAM? because i tried to contact Patriot support, and they don't even know :/ and that's so awful, how supposed that even a manufacturers doesn't know what are they chipset in memory ? lol :/

I have this kit of ram:

Viper Patriot Kit 2x4 (8gigs) PE000418-PV48G320C6K,

I asked to the support if my ram are SamSung-B die or hynix? or what chipset is? all i get was:


Also i put an screenshot of my Asrock b350 Fatality k4 Gamming QVL for memory and i ask them, does my ram are samsung or samsun b-die , what does mean Samsung11D1? and they didn't know..


So to be honest I don't know what is the real chip behind my rams, also Thaiphoon burner seems not to detect the chipset.. :/
My advise please don't buy things from PATRIOT!


----------



## ZeNch

Quote:


> Originally Posted by *x58haze*
> 
> Hey guys i was wondering if someone else here knows what chipset is my RAM? because i tried to contact Patriot support, and they don't even know :/ and that's so awful, how supposed that even a manufacturers doesn't know what are they chipset in memory ? lol :/
> 
> I have this kit of ram:
> 
> Viper Patriot Kit 2x4 (8gigs) PE000418-PV48G320C6K,
> 
> I asked to the support if my ram are SamSung-B die or hynix? or what chipset is? all i get was:
> 
> 
> Also i put an screenshot of my Asrock b350 Fatality k4 Gamming QVL for memory and i ask them, does my ram are samsung or samsun b-die , what does mean Samsung11D1? and they didn't know..
> 
> 
> So to be honest I don't know what is the real chip behind my rams, also Thaiphoon burner seems not to detect the chipset.. :/
> My advise please don't buy things from PATRIOT!


3000mhz cl16 its probably (not sure) hinyx but i dont know if A-die or M-die.

its my opinion i dont know.


----------



## Frikencio

Guys, 4x SR DIMMS @ 3200 are faster than 2x SR DIMMS @ 3200?

And if so, "how much"? 2800 4x SR DIMMS could be "faster" than 2x SR DIMMS @ 3200?


----------



## Trender07

Quote:


> Originally Posted by *x58haze*
> 
> Hey guys i was wondering if someone else here knows what chipset is my RAM? because i tried to contact Patriot support, and they don't even know :/ and that's so awful, how supposed that even a manufacturers doesn't know what are they chipset in memory ? lol :/
> 
> I have this kit of ram:
> 
> Viper Patriot Kit 2x4 (8gigs) PE000418-PV48G320C6K,
> 
> I asked to the support if my ram are SamSung-B die or hynix? or what chipset is? all i get was:
> 
> 
> Also i put an screenshot of my Asrock b350 Fatality k4 Gamming QVL for memory and i ask them, does my ram are samsung or samsun b-die , what does mean Samsung11D1? and they didn't know..
> 
> 
> So to be honest I don't know what is the real chip behind my rams, also Thaiphoon burner seems not to detect the chipset.. :/
> My advise please don't buy things from PATRIOT!


You can use Thaiphoon to check it


----------



## ZeNch

Quote:


> Originally Posted by *Trender07*
> 
> You can use Thaiphoon to check it


read the end of the post, Thaiphoon not detect this chip.


----------



## Anty

Quote:


> Originally Posted by *Frikencio*
> 
> Guys, 4x SR DIMMS @ 3200 are faster than 2x SR DIMMS @ 3200?
> 
> And if so, "how much"? 2800 4x SR DIMMS could be "faster" than 2x SR DIMMS @ 3200?


Assuming *same timings* difference is minimal between x4 and x2.
So 4x2800 won't be faster than 2x3200 in this case.


----------



## Frikencio

Quote:


> Originally Posted by *Anty*
> 
> Assuming *same timings* difference is minimal between x4 and x2.
> So 4x2800 won't be faster than 2x3200 in this case.


But Dual Rank are faster?


----------



## Anty

Minimally faster for same speed and timings. But SR OC better.


----------



## Frikencio

Quote:


> Originally Posted by *Anty*
> 
> Minimally faster for same speed and timings. But SR OC better.


And technically, 4x SR equals to 2x DR ?


----------



## Anty

Not sure what you are asking - speed increase or OC?
Regarding speed it could be comparable (but I don't have numbers)
OC is still better with x4 SR than x2 DR (at least for b-die).


----------



## Frikencio

Quote:


> Originally Posted by *Anty*
> 
> Not sure what you are asking - speed increase or OC?
> Regarding speed it could be comparable (but I don't have numbers)
> OC is still better with x4 SR than x2 DR (at least for b-die).


I have the B-Die Samsung CL14-3200. 2 sticks of 8 Gb SR.

I want to use another 2 sticks to get to 32Gb.

Will I need to, would it achieve same speed?


----------



## Anty

Yes. I have 4x8GB b-dies and it can run [email protected] 1T. Actually even [email protected] 2T but it is slower so [email protected] is better deal.


----------



## feathers632

Hello people,

Looking at the Ryzen mem stability window... No one past 3600mhz?

I got 4000mhz ram from Teamgroup 8-pack.

Boots at 3600mhz mem but not stable. Is stable at 3400. CPU is at 3.92ghz.

CAS 18-19-19-39 Timings 1.30-1.40v VDIMM

https://www.overclockers.co.uk/team-group-xtreem-8pack-edition-16gb-2x8gb-ddr4-pc4-32000c18-4000mhz-dual-channel-kit-black-my-098-tg.html

Giga Aorus gaming 5 (not the K version).

Mostly auto mem timings based on the XMP profile.

Since the ram timing above are for 4000mhz and I'm only running it at 3400... Would like to lower timings or get it stable at 3600mhz. How do we go about reducing timings?










Ryzen 1700 @ 3.92ghz.
Giga Aorus Gaming 5.
16gb 4000 DDR4


----------



## Anty

Try [email protected]4-14-14-28 (get timings from trident z [email protected] ram).
As for now 3600 doesn't seem a good option if you can't run it very tight like 15-14-14-30.


----------



## Darkomax

Well ****, I thought my 3200CL13 was stable after passing 2500% memtest and 1h GSAT, but it randomly crashes in daily usage (BSOD that are obviously linked to memory). Reverted to CL14 and no problems.


----------



## feathers632

Quote:


> Originally Posted by *Anty*
> 
> Try [email protected] (get timings from trident z [email protected] ram).
> As for now 3600 doesn't seem a good option if you can't run it very tight like 15-14-14-30.


Thanks.. tried those timings but it defaulted to 2133mhz. I dialed in slightly higher timings the bios suggested and it's booted to windies now. Will test it.

Still an improvement over the 4000mhz timings I'd been using.


----------



## Aby67

Quote:


> Originally Posted by *Anty*
> 
> Try [email protected] (get timings from trident z [email protected] ram).
> As for now 3600 doesn't seem a good option if you can't run it very tight like 15-14-14-30.


Is there anyone that can run 3600mhz at 14-14-14-30 as You suggest achieving.... and would it be best to undervolt the CPU a tad first to get Ram stable first, as it is known that Threadripper and Ryzen7 have in built overshoot and ripple protection, which either will droop heavily or under clock the CPU big time or just give black screen

thanks


----------



## Anty

I wrote 15-14-14-30 not 14-14-14-30








I can boot and bench with those timings but it is not stable (no big surprise). [email protected] 2T stable though.
And no - it requires more voltage for me to sustain core and mem OC (same for 3466).
I never experienced underclocking or blackscreens (C6H with power limit 130%)


----------



## darkwizard

Hey guys, I'm receiving today the Flare X F4-3200C14D-16GFX which are on sale for $174+, should I keep these puppies or go for the Trident ones to run 3466mhz? thanks guys.


----------



## x58haze

Quote:


> Originally Posted by *ZeNch*
> 
> 3000mhz cl16 its probably (not sure) hinyx but i dont know if A-die or M-die.
> 
> its my opinion i dont know.


This memories are 3200 mhz with XMP 2.0 16-18-18-36 as i describe in the asrock picture, but yeah I don't know what to do :/ people cannot help me at all because they are not so sure about the chip on this rams

I have heard yeah your memory are probably Samsun-b die, other say probably Hinyx heheh i'm so lost







i wont be buying anything from Patriot....


----------



## ZeNch

Quote:


> Originally Posted by *x58haze*
> 
> This memories are 3200 mhz with XMP 2.0 16-18-18-36 as i describe in the asrock picture, but yeah I don't know what to do :/ people cannot help me at all because they are not so sure about the chip on this rams
> 
> I have heard yeah your memory are probably Samsun-b die, other say probably Hinyx heheh i'm so lost
> 
> 
> 
> 
> 
> 
> 
> i wont be buying anything from Patriot....


if you see the Samsung B-die rams have timmings like a 14CL in 3200mhz and hinyx like to 16-18-18 or similar (in 3200mhz) it not is sure is commonly


----------



## Worldwin

Anyone know how to stop the memory from failing at cold boot. My comp has to cycle 2-3 times before post or entering windows. This problem only occurs for this set of timings. My other set of timings which are way tighter don't suffer from this. The really tight timings are not stable but the one that cycles multiple times. I am thinking its cause the tRFC is too high? at 333 vs 312.


----------



## The Sandman

Quote:


> Originally Posted by *darkwizard*
> 
> Hey guys, I'm receiving today the Flare X F4-3200C14D-16GFX which are on sale for $174+, should I keep these puppies or go for the Trident ones to run 3466mhz? thanks guys.


I just posted this in the C6H thread http://www.overclock.net/t/1624603/rog-crosshair-vi-overclocking-thread/29840#post_26455151
No issues running Flare-X @ 3466MHz here.


----------



## feathers632

I've heard rumours of 4ghz DDR4 with piezen on the latest Agesa but I guess that's a load of pish?


----------



## Trender07

Guys any idea why my memory speeds goes up by itself? AM4 Advanced memory I already tried disabling and enabling looks like it isn't doing that idk what even do.

Anyways this is the timings I have set on my mobo:

And this is what I ACTUALLY get omg?:









and I don't know why :s just look at dat high trfc!


----------



## darkwizard

Quote:


> Originally Posted by *The Sandman*
> 
> I just posted this in the C6H thread http://www.overclock.net/t/1624603/rog-crosshair-vi-overclocking-thread/29840#post_26455151
> No issues running Flare-X @ 3466MHz here.


Awesome man, thanks! I got it and it is running at 3200mhz with no issues so far.


----------



## Jeager

Quote:


> Originally Posted by *Trender07*
> 
> Any way guys for running to 3600 MHz? I got this ones samsung b-dies KFA2 (galax in usa i think) HOF 3600, but with its profile it won't boot at 3600 mhz. I am running at 3466 MHz now. For 3600 mhz I already tried setting 2T and geardown on, bankgroupswap enabled and 1.40V but still it won't boot at 3600


I have them, they run stable at 3333 and I can sometime boot at 3466 but isnt stable and 3600 never booted up







(didn't try more than 1.4v)

What's your timing voltage for 3466 ?


----------



## starise

I'm new to Ryzen and i'm testing right now my memory.

I can't POST with *GearDownMode* disabled also using default settings.
Anyway, getting that option enabled, I managed to push them to 3333 CAS 14.
It looks strange to me. Is this behavior normal?

Here's my memory:


----------



## Anty

Buildzoid does not sleep









https://www.reddit.com/r/Amd/comments/7e28on/preparing_my_ryzen_7_1700_for_benching_the_hwbot/


----------



## stryk9

Anybody able to assist me with the issue of my RAM settings reverting after a reboot? It will maintain my CPU OC but revert the RAM timings. Strange because the OC is stable (besides the issue).


----------



## ZeNch

F1 error?
have you cold boot? (some restarts to power on)


----------



## 1usmus

Quote:


> Originally Posted by *Anty*
> 
> Buildzoid does not sleep
> 
> 
> 
> 
> 
> 
> 
> 
> 
> https://www.reddit.com/r/Amd/comments/7e28on/preparing_my_ryzen_7_1700_for_benching_the_hwbot/


a liquid nitrogen?

the activity of the string is still 40, a useless achievement


----------



## The Sandman

Quote:


> Originally Posted by *1usmus*
> 
> the activity of the string is still 40, a useless achievement


If I may ask, you mentioned "the activity of the String" are you referring to tRC? Guessing not low enough?


----------



## Aby67

Quote:


> Originally Posted by *stryk9*
> 
> Anybody able to assist me with the issue of my RAM settings reverting after a reboot? It will maintain my CPU OC but revert the RAM timings. Strange because the OC is stable (besides the issue).


https://www.youtube.com/watch?v=zoXbHRR7j98

follow these guidelines see if they help


----------



## hsn

Unfortunaly my mobo doesn't suport oc blck.
still need test to another mainboard


----------



## darje666

Hi im having trouble reaching anything higher than 2667mhz on my 2x8GB my current timings are 16 18 18 36 1T at 1.344V.
Its Corsair CMK16GX4M2B3200C16R
http://www.corsair.com/en-gb/vengeance-lpx-16gb-2x8gb-ddr4-dram-3200mhz-c16-memory-kit-red-cmk16gx4m2b3200c16r

Im running it alongside Ryzen 1700 @ 3.8Ghz 1.28Vcore soc voltage 1,056
MBO is MSI B350 Tomahawk. Bios 1.90.

So anyone have any suggestion on the timings etc.?

Thanks


----------



## Swaylogeezy

[email protected] 1.1v---BIOS 3.20---HCI---1680%---F4-3200C14D-16GVK

I know the timings stink, but I just wanted to try









Asrock TAICHI


----------



## reptilee

Quote:


> Originally Posted by *darje666*
> 
> Hi im having trouble reaching anything higher than 2667mhz on my 2x8GB my current timings are 16 18 18 36 1T at 1.344V.
> Its Corsair CMK16GX4M2B3200C16R
> http://www.corsair.com/en-gb/vengeance-lpx-16gb-2x8gb-ddr4-dram-3200mhz-c16-memory-kit-red-cmk16gx4m2b3200c16r
> 
> Im running it alongside Ryzen 1700 @ 3.8Ghz 1.28Vcore soc voltage 1,056
> MBO is MSI B350 Tomahawk. Bios 1.90.
> 
> So anyone have any suggestion on the timings etc.?
> 
> Thanks


-Set manually timings 16-18-18-36 (disable xmp profile)

- Dram voltage 1.4

- Soc 1.1

-Gearmode > disabled

-Trc 75

-ProcODT 60

- If command rate 1 wont work, try 2.

-Set first 2800mhz, then 2933mhz ( if it boots) and so on.

-Disable memory try it!

-If it run steady you can put trc to auto and you can try out better timings.


----------



## darje666

Thanks but im afraid it doesnt boot with those settings.


----------



## darje666

Quote:


> Originally Posted by *reptilee*
> 
> -Set manually timings 16-18-18-36 (disable xmp profile)
> 
> - Dram voltage 1.4
> 
> - Soc 1.1
> 
> -Gearmode > disabled
> 
> -Trc 75
> 
> -ProcODT 60
> 
> - If command rate 1 wont work, try 2.
> 
> -Set first 2800mhz, then 2933mhz ( if it boots) and so on.
> 
> -Disable memory try it!
> 
> -If it run steady you can put trc to auto and you can try out better timings.


Thanks but im afraid it doesnt boot with those settings.


----------



## Aby67

Hello

I would kindly like to know if those of you who have purchased 32Gb Gskill ram 3600 cl 17 can get to run this at faster timings on threadripper.....

I would also like to know if anyone has managed to get the 64 GB kit 3600 to get those timings to be worth buying than the 32Gb kits.

thanks


----------



## Aby67

Quote:


> Originally Posted by *darje666*
> 
> Hi im having trouble reaching anything higher than 2667mhz on my 2x8GB my current timings are 16 18 18 36 1T at 1.344V.
> Its Corsair CMK16GX4M2B3200C16R
> http://www.corsair.com/en-gb/vengeance-lpx-16gb-2x8gb-ddr4-dram-3200mhz-c16-memory-kit-red-cmk16gx4m2b3200c16r
> 
> Im running it alongside Ryzen 1700 @ 3.8Ghz 1.28Vcore soc voltage 1,056
> MBO is MSI B350 Tomahawk. Bios 1.90.
> 
> So anyone have any suggestion on the timings etc.?
> 
> Thanks


I like MSI brand a lot, but unfortunately I suspect that MSI AMD motherboards particularly on the entry level are a bunch of crap....the problem You have to getting those speeds at the speeds You payed for is the motherboard, even if You had a CPU with a very bad memory controller.
MSI motherboards for Ryzen 7 are the epiphany of instability in all its components.
Please do not take any offense, and I can understand you went for the 1700, but if You do chose this kind of CPU because other overclockers get it to run faster than the top tier ones, it must be hosted on top tier motherboards starting from the Gygabite 370 minimum and preferably on the ASUS overkill ones especially as You might want to upgrade the CPU with the newer and way much faster over 4.5 Ghz versions that will come on 12nm and even faster on ZEN 2 7 nm.

We can all be very pleased at AMD pricing, but please do take in Mind that AMD steal buy pricing is over with, and that ZEN CPus cost less than Intel ONLY because of the different architecture that gives close to 100 % yealds in the manufacturing process.

These kind of CPU You have and ZEn in general, is way superior to Intel extreme broadwell or even xeons that came around couple of years ago...while You are purchasing them as mainstream pricing, if Zen was released two years ago, the pricing would have been that of HEDT on all the 7 line.

These CPu are NOT Intel I5 crap, so do not aim at buying Intel I 5 crap like priced motherboards..the ASUS CH6 is so overkill in the vrms it has, that it is in quality way superior in what You get on server 4 CPU motherboards designed specifically for intel platinum xeons that cost over 10k dollars a piece.

Ryzen 7 CPUs are not toys because they are cheap...they run much much faster than CPUs that people have payed for over 2000 dollars just some time ago....putting a 1700 ryzen on 350 board is kinda like wanting to be feeeloading......I hope You understand the concept and dot take it as I am belittling you.....if You buy a ferrari , put good tires on it buddy thats what I am trying to suggest You because You have indeed a hell of a CPU that was a great buy.


----------



## reptilee

My Tomahawk Arctic is running @ 3066mhz with G.Skill 16GB (2x8GB), Ripjaws V, DDR4 3200MHz, CL16 (F4-3200C16D-16GVKB) :

- Dram voltage 1.4

- Soc 1.1

-Gearmode > disabled

-Trc 75

-ProcODT 60

-Disable memory try it!

Worth to try at least..


----------



## darje666

Quote:


> Originally Posted by *reptilee*
> 
> -Set manually timings 16-18-18-36 (disable xmp profile)
> 
> - Dram voltage 1.4
> 
> - Soc 1.1
> 
> -Gearmode > disabled
> 
> -Trc 75
> 
> -ProcODT 60
> 
> - If command rate 1 wont work, try 2.
> 
> -Set first 2800mhz, then 2933mhz ( if it boots) and so on.
> 
> -Disable memory try it!
> 
> -If it run steady you can put trc to auto and you can try out better timings.


holy crap it worked when i used your settings and 2T instead of 1T. and now im getting 3200mhz stable!!!


----------



## reptilee

Quote:


> Originally Posted by *darje666*
> 
> holy crap it worked when i used your settings and 2T instead of 1T. and now im getting 3200mhz stable!!!


Gratz! =)


----------



## Xzow

Quote:


> Originally Posted by *Swaylogeezy*
> 
> [email protected] 1.1v---BIOS 3.20---HCI---1680%---F4-3200C14D-16GVK
> 
> I know the timings stink, but I just wanted to try
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Asrock TAICHI


That awkward feeling when one persons stinky timings at 3466 is my dream at 3200


----------



## Swaylogeezy

Hello,

cold boot issue

I tightened my timings passed hci 1200% and stressed tested my 4.0ghz 1800x overclock. I have boot training disabled, but I have not touched the CLD_VDDP. Any ideas on where to start?



I did oc my memory when my cpu was only at 3.7, could that be the issue?


----------



## Arengeta

I've a question. HCI passes 400% without any errors, however occasionally I get a black screen during the test. Is this normal or is the overclock unstable?


----------



## Aby67

Quote:


> Originally Posted by *Arengeta*
> 
> I've a question. HCI passes 400% without any errors, however occasionally I get a black screen during the test. Is this normal or is the overclock unstable?


probably your hdmi cable from the gpu to the monitor is way too long....lt me guess, you have a cable 3 ft longer?


----------



## Arengeta

Quote:


> Originally Posted by *Aby67*
> 
> probably your hdmi cable from the gpu to the monitor is way too long....lt me guess, you have a cable 3 ft longer?


Using a 2m DVI-D cable.


----------



## Aby67

Quote:


> Originally Posted by *Arengeta*
> 
> Using a 2m DVI-D cable.


i have a 1.5 meter hdmi cable, and occasionally i get a black screen for an instant just like you, it is as if the gpu hiccups for power....i wish to share tham while im still not on amd im running ecc memory on high base lock xeons....i dont think dvi is like hdmi or DP, but if u dont need that length look for a 50 cm one, it can only do good...which reminds me of making myself a black friday hdmi cable buy.....

i dont know what system u on, but, if u on a high end cpu, power supply matters big time too and all the su cables even more....if they are not top class stuff if u overclocking it will affect performance and stability


----------



## ssateneth

Quote:


> Originally Posted by *Arengeta*
> 
> I've a question. HCI passes 400% without any errors, however occasionally I get a black screen during the test. Is this normal or is the overclock unstable?


I had the same symptom. Workaround is to disable your video card in device manager. It still outputs to monitor fine, but you will be limited to 1 monitor and no 3d acceleration. It's something to do with display driver not getting information quick enough due to HCI hogging bandwidth so it craps out.


----------



## Shovel Knight

Shovel Knight --- [email protected] --- 3066Mhz - C16-17-17-27-1T --- 1.5v --- SOC 1.1v --- BIOS 3203 --- HCI 400% --- Part Number: 8GX-D4-3200-MR

Ram type: EVGA SuperSC 16GB 2 x 8GB DDR4-3200 PC4-25600 CL16 Dual Channel Desktop Memory Kit

http://www.microcenter.com/product/459742/SuperSC_16GB_2_x_8GB_DDR4-3200_PC4-25600_CL16_Dual_Channel_Desktop_Memory_Kit

Mobo: ASUS ROG B350-F Gaming

Hello all. I came across this thread the other day after I updated my MOBO bios. My new bios was supposedly supposed to help with stability of 3200Mhz DDR4. Needless to say, stabilizing Hynix M-Die RAM is extremely difficult on Ryzen, and the most I can get stable with this RAM in MemTest is periodic errors which read "difference=8", at 3200Mhz. I have tried tweaking all of the settings, to no avail. Thankfully it is stable at 3066Mhz now. I was running it at 2933Mhz before this new update. This, along with other forums has been extremely helpful in determining which RAM kit I should upgrade to, and I thank you all.

Obviously RAM manufacturers do not hold their RAM to the same high standards as us, otherwise this EVGA ram would have worked on memtest with no errors and minimal tweaking right out of the box; RAM dies store recommended values for the mobo, but it is my opinion that RAM manufacturers neglect consumers when they do not give guidance for ALL of the settings, such as TWTR_S and TWTR_L, which in my experience are drastically responsible for the stability of your RAM.

I am currently halfway through running HCI 400% with my CPU OC'd to 3.95Ghz, and will post the results shortly. Thanks!


----------



## Aby67

Quote:


> Originally Posted by *Shovel Knight*
> 
> Shovel Knight --- [email protected] --- 3066Mhz - C16-17-17-27-1T --- 1.5v --- SOC 1.1v --- BIOS 3203 --- HCI 400%
> 
> Ram type: EVGA SuperSC 16GB 2 x 8GB DDR4-3200 PC4-25600 CL16 Dual Channel Desktop Memory Kit
> 
> http://www.microcenter.com/product/459742/SuperSC_16GB_2_x_8GB_DDR4-3200_PC4-25600_CL16_Dual_Channel_Desktop_Memory_Kit
> 
> Mobo: ASUS ROG B350-F Gaming
> 
> Hello all. I came across this thread the other day after I updated my MOBO bios. My new bios was supposedly supposed to help with stability of 3200Mhz DDR4. Needless to say, stabilizing Hynix M-Die RAM is extremely difficult on Ryzen, and the most I can get stable with this RAM in MemTest is periodic errors which read "difference=8", at 3200Mhz. I have tried tweaking all of the settings, to no avail. Thankfully it is stable at 3066Mhz now. I was running it at 2933Mhz before this new update. This, along with other forums has been extremely helpful in determining which RAM kit I should upgrade to, and I thank you all.
> 
> Obviously RAM manufacturers do not hold their RAM to the same high standards as us, otherwise this EVGA ram would have worked on memtest with no errors and minimal tweaking right out of the box; RAM dies store recommended values for the mobo, but it is my opinion that RAM manufacturers neglect consumers when they do not give guidance for ALL of the settings, such as TWTR_S and TWTR_L, which in my experience are drastically responsible for the stability of your RAM.
> 
> I am currently halfway through running HCI 400% with my CPU OC'd to 3.95Ghz, and will post the results shortly. Thanks!


https://www.youtube.com/watch?v=zoXbHRR7j98&t=1774s
If you havent check this , it should cover all you might want to know.....*(disregard if you know this notorious overclocker)
cheers


----------



## Shovel Knight

What happened to my post?


----------



## Shovel Knight

Here it is again







My computer is glitching out because of the HCI test.

Shovel Knight --- [email protected] --- 3066Mhz - C16-17-17-27-1T --- 1.5v --- SOC 1.1v --- BIOS 3203 --- HCI 400%

Ram type: EVGA SuperSC 16GB 2 x 8GB DDR4-3200 PC4-25600 CL16 Dual Channel Desktop Memory Kit

http://www.microcenter.com/product/459742/SuperSC_16GB_2_x_8GB_DDR4-3200_PC4-25600_CL16_Dual_Channel_Desktop_Memory_Kit

Mobo: ASUS ROG B350-F Gaming

Hello all. I came across this thread the other day after I updated my MOBO bios. My new bios was supposedly supposed to help with stability of 3200Mhz DDR4. Needless to say, stabilizing Hynix M-Die RAM is extremely difficult on Ryzen, and the most I can get stable with this RAM in MemTest is periodic errors which read "difference=8", at 3200Mhz. I have tried tweaking all of the settings, to no avail. Thankfully it is stable at 3066Mhz now. I was running it at 2933Mhz before this new update. This, along with other forums has been extremely helpful in determining which RAM kit I should upgrade to, and I thank you all.

Obviously RAM manufacturers do not hold their RAM to the same high standards as us, otherwise this EVGA ram would have worked on memtest with no errors and minimal tweaking right out of the box; RAM dies store recommended values for the mobo, but it is my opinion that RAM manufacturers neglect consumers when they do not give guidance for ALL of the settings, such as TWTR_S and TWTR_L, which in my experience are drastically responsible for the stability of your RAM.

I am currently halfway through running HCI 400% with my CPU OC'd to 3.95Ghz, and will post the results shortly. Thanks!


----------



## Shovel Knight

Quote:


> Originally Posted by *Aby67*
> 
> https://www.youtube.com/watch?v=zoXbHRR7j98&t=1774s
> If you havent check this , it should cover all you might want to know.....*(disregard if you know this notorious overclocker)
> cheers


Yeah I watched his video. Putting my TWTR timings near each other makes my memory less stable. I learned from him that my previously high VDDP voltage of .98 was why my USB connections were acting up. Good thing I found out too! Now it is set at .92


----------



## The Sandman

Quote:


> Originally Posted by *Arengeta*
> 
> I've a question. HCI passes 400% without any errors, however occasionally I get a black screen during the test. Is this normal or is the overclock unstable?


I run HCI for a minimum of 1000% to test memory stability.
I never see black screens during tests. I'd guess instability.


----------



## Shovel Knight

Earlier I had a black box pop up on my screen during this HCI test. It was another program running in the background crashing or something.


----------



## Shovel Knight

Shovel Knight --- [email protected] --- 3066Mhz - C16-17-17-27-1T --- 1.5v --- SOC 1.15v --- BIOS 3203 --- HCI 400%

I had to slightly increase my SOC for my CPU overclock but it has worked out pretty well!

Cheers


----------



## superstition222

Quote:


> Originally Posted by *The Sandman*
> 
> I run HCI for a minimum of 1000% to test memory stability.
> I never see black screens during tests. I'd guess instability.


The developer of MemTest HCL said 400% should catch everything.

It would be nice to have scientific evidence. 1000% is obviously just a number out of a hat because it sounds nice. It's the same number the guy in that video put out.



Someone at Techpowerup said he doesn't consider a system fully tested unless Memtest is run for 4 days.









Someone also recently posted advice, in a comment to that guy's video, that he should use Techpowerup's new RAM tester. It lets one test RAM with a single instance in Windows. However, I have found, with HCL multiple instances, that the quickest way to uncover errors is to give a small allocation to two instances. I think this creates hot spots. I give one instance 512 MB and one 768 MB, or as little as 384 MB. Running a program that tests all the RAM in a single instance may not uncover errors as quickly.


----------



## Iceman1985

I have had a bad experience with three earlier Ryzen builds where i had unexplainable stuttering, games were unplayable and i blamed the hardware for that every time. (Sent them back and re-ordered)

So i've been playing around with my 4th rig with the exact same components except for ram. This time i have Crosshair VI Hero (9920), 1800X paired with 2x8gb Flare X 3200c14. Now i don't have any stuttering at all, all works as intended i guess.

This is the only one of Stilt's settings that is HCI-stable: "3333Mhz safe".

I also have 4x8gb of G.Skill's TridentZ RGB ram: (F4-3200C14Q-32GTZR) which is B-die.

I would like to run my RGB-ram instead to get 32gb in total. I've seen people hit 4x8gb dimms with high speed and low latencies and i wanna give it a shot again.

I have a spare 1800X in an unopened box next to me because i think there might be something "off" about this one too.. the voltages read in bios is much higher than i've seen on my last builds:
SOC in bios: 1.25V - (set 1.05)
V-core in bios: 1.55V - (set offset +0.075ish for 4ghz)
Dram voltage in HWinfo: 1.504 - (set 1.4V Stilt's profile)
See this for more info: 

So if any kind sould would like to help me out with my 4 dimms i would appreciate it. I've PM'ed a few of you in here with mixed results, never gotten my system stable with 4x8gb.

Any suggestions i can try is more than welcome, for example "This setting is a MUST" and "try this". And yes, i have read every single page in this thread from start to end but with three earlier builds have made my brain fry i think. Seriously.

/Iceman


----------



## ZeNch

Quote:


> Originally Posted by *Iceman1985*
> 
> I have had a bad experience with three earlier Ryzen builds where i had unexplainable stuttering, games were unplayable and i blamed the hardware for that every time. (Sent them back and re-ordered)
> 
> So i've been playing around with my 4th rig with the exact same components except for ram. This time i have Crosshair VI Hero (9920), 1800X paired with 2x8gb Flare X 3200c14. Now i don't have any stuttering at all, all works as intended i guess.
> 
> This is the only one of Stilt's settings that is HCI-stable: "3333Mhz safe".
> 
> I also have 4x8gb of G.Skill's TridentZ RGB ram: (F4-3200C14Q-32GTZR) which is B-die.
> 
> I would like to run my RGB-ram instead to get 32gb in total. I've seen people hit 4x8gb dimms with high speed and low latencies and i wanna give it a shot again.
> 
> I have a spare 1800X in an unopened box next to me because i think there might be something "off" about this one too.. the voltages read in bios is much higher than i've seen on my last builds:
> SOC in bios: 1.25V - (set 1.05)
> V-core in bios: 1.55V - (set offset +0.075ish for 4ghz)
> Dram voltage in HWinfo: 1.504 - (set 1.4V Stilt's profile)
> See this for more info:
> 
> So if any kind sould would like to help me out with my 4 dimms i would appreciate it. I've PM'ed a few of you in here with mixed results, never gotten my system stable with 4x8gb.
> 
> Any suggestions i can try is more than welcome, for example "This setting is a MUST" and "try this". And yes, i have read every single page in this thread from start to end but with three earlier builds have made my brain fry i think. Seriously.
> 
> /Iceman


http://www.overclock.net/t/1640919/ryzen-dram-calculator-overclocking-dram

see this tool to set your ram settings


----------



## Iceman1985

Quote:


> Originally Posted by *ZeNch*
> 
> http://www.overclock.net/t/1640919/ryzen-dram-calculator-overclocking-dram
> 
> see this tool to set your ram settings


I have tried that tool with my Flare X memory, did not get it stable at any given speed. And i changed every setting that was provided in the tool.


----------



## Anty

Try different SOC and DRAM voltages (like SOC 1.15, DRAM 1.45).
I also have 4x8 and those from tool won't work stable.
procODT and CAD bus helped me too - especially for 3600.


----------



## Iceman1985

Quote:


> Originally Posted by *Anty*
> 
> Try different SOC and DRAM voltages (like SOC 1.15, DRAM 1.45).
> I also have 4x8 and those from tool won't work stable.
> procODT and CAD bus helped me too - especially for 3600.


What ProcODT and CAD bus do you use?

I just tried, can't seem to get 4x8gb to boot even without losing memory training. Tried ProcODT, Geardown, Voltages, forcing 24,24,24,24 on the Cad bus but nothing.. as soon as i change from 3200Mhz to 3333Mhz it won't train/boot.


----------



## Dr. Vodka

Quote:


> Originally Posted by *Iceman1985*
> 
> forcing 24,24,24,24 on the Cad bus but nothing.


ProcODT for single rank 8GB B-die sticks is 53.3-60 ohms. For the CAD bus you want higher resistances for higher speeds, try 30-30-30-30 (This is one of the Stilt's recommendations)

In my case, 40-40-40-40 helped stability and eliminated cold boot issues 9/10 times on 2x8GB 3466MHz 15-15-15-35 1T no geardown (Stilt's built in B-die 3466 profile on the C6H). For that odd cold boot fail, increasing the boot retry count helps, the next time it boots without issues.

If you can't boot 3333 then you probably have to play with CLDO_VDDP to move the memory hole. If 3466 boots, then that's your issue.


----------



## Iceman1985

Quote:


> Originally Posted by *Dr. Vodka*
> 
> ProcODT for single rank 8GB B-die sticks is 53.3-60 ohms. For the CAD bus you want higher resistances for higher speeds, try 30-30-30-30 (This is one of the Stilt's recommendations)
> 
> In my case, 40-40-40-40 helped stability and eliminated cold boot issues 9/10 times on 2x8GB 3466MHz 15-15-15-35 1T no geardown (Stilt's built in B-die 3466 profile on the C6H). For that odd cold boot fail, increasing the boot retry count helps, the next time it boots without issues.
> 
> If you can't boot 3333 then you probably have to play with CLDO_VDDP to move the memory hole. If 3466 boots, then that's your issue.


Is memory hole dependant on number of sticks or ram-size? Because i have not experienced this memory hole with 2x8gb.. how do we know if we are encountering a memory hole? And does the memory-hole move with 4x8gb? That would explain alot if it did...


----------



## blair

Quote:


> Originally Posted by *Iceman1985*
> 
> What ProcODT and CAD bus do you use?
> 
> I just tried, can't seem to get 4x8gb to boot even without losing memory training. Tried ProcODT, Geardown, Voltages, forcing 24,24,24,24 on the Cad bus but nothing.. as soon as i change from 3200Mhz to 3333Mhz it won't train/boot.


I'm running 4x8gb B-Die @ 3466 at the moment.. obtained 400% memtest. My first attempt which crashed at an unknown % is documented HERE.

The followup changes are documented HERE which persisted to 400% memtest where i called it a day and continued gaming.

It is worth noting my Memory controller does appear to be pretty good... so your results may vary.

It's worth noting When the above settings don't work to well i would drop down to 3333 and it would never have any major issues.. I think from memory i didn't need to toy with CLDO_VDDP to get 3333 working though..

many have reccomended 30-30-40-60 for the CAD bus for higher speeds.. try it out? 24-24-24-24 from what i've seen is not going to work for 4x8gb B-Die.

I hope this helps.. Good Luck


----------



## RealSteelH6

F4-3200C14D-16GTZR works at the advertised settings (3200MHz CL14-14-14-34) on a MSI B350M PRO-VD Plus with a Ryzen 5 1600.
And the F4-3200C16D-16GTZR works at 2933MHz CL16-18-18-38 on that board (Both have been tested with MemTest86.
The Crucial kit BLS2C16G4D240FSB doesn't work at all (no post) in dual channel mode (only a single ram stick works).


----------



## LicSqualo

Hi, I'm new here.









[email protected] 1.07v---BIOS 0052---HCI---1500%---F4-3600C16-16GTZ


----------



## blair

Quote:


> Originally Posted by *LicSqualo*
> 
> Hi, I'm new here.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [email protected] 1.07v---BIOS 0052---HCI---1500%---F4-3600C16-16GTZ


Hey, what is the chance you know the Week code of your 1700??

Mine is 1724 Malaysia

P.S. Very nice OC, makes me want to get some much better cooling to try and push my Core much quicker... especially considering i know i have a decent IMC.


----------



## LicSqualo

Hi, of course I've take a shot before install-it









See my Sig for a detailed picture. 1709 PGT Malaysia.


----------



## tiamat556

is it better to have 4x8 single rank samsung 3200 bdie dimms(F4-3200C14Q-32GTZ ), or 2x16gb dual rank 3200 (F4-3200C14D-32GTZR ) samsung bdie dimms ? when I mean better, I mean which one am I more to achieve the rated speed ? I have the X370 gaming 5 by Gigabyte and on the QVL is does list the F4-3200C14Q2-128GTZ, which I believe is basically the same ram ?


----------



## blair

Quote:


> Originally Posted by *LicSqualo*
> 
> Hi, of course I've take a shot before install-it
> 
> 
> 
> 
> 
> 
> 
> 
> 
> See my Sig for a detailed picture. 1709 PGT Malaysia.


Cheers, a very early one I see


----------



## blair

Quote:


> Originally Posted by *tiamat556*
> 
> is it better to have 4x8 single rank samsung 3200 bdie dimms(F4-3200C14Q-32GTZ ), or 2x16gb dual rank 3200 (F4-3200C14D-32GTZR ) samsung bdie dimms ?


Depends if you need 64gb down the track, or you are happy to leave 32gb as your maximum.

Dual Rank will not clock as high as Single Rank
Dual Rank is harder for the IMC to work with.
Single Rank can outpace Dual Rank simply due to higher clock speed.
Dual Rank supports interleaving of RANKs and Channels, as such clock for clock Dual Rank will outperform Single Rank
I.E. While R1 is performing an operation R2 can be sent an operation, rinse and repeat, Dual Channel is parallel as in writes to both Channels at the same time.

TL/DR - If you want high clock speed, and capacity isn't a major issue get single rank
If you want high capacity and are willing to sacrifice clock speed, get Dual Rank


----------



## blair

Edit: Double Post - Delete me.


----------



## tiamat556

Quote:


> Originally Posted by *blair*
> 
> Depends if you need 64gb down the track, or you are happy to leave 32gb as your maximum.
> 
> Dual Rank will not clock as high as Single Rank
> Dual Rank is harder for the IMC to work with.
> Single Rank can outpace Dual Rank simply due to higher clock speed.
> Dual Rank supports interleaving of RANKs and Channels, as such clock for clock Dual Rank will outperform Single Rank
> I.E. While R1 is performing an operation R2 can be sent an operation, rinse and repeat, Dual Channel is parallel as in writes to both Channels at the same time.
> 
> TL/DR - If you want high clock speed, and capacity isn't a major issue get single rank
> If you want high capacity and are willing to sacrifice clock speed, get Dual Rank


are you saying 4x8 single rank is still more likely to work than 2x16 dual rank ? I was under impression, while single rank is more compatible than dual rank, 2 sticks is more compatible than 4.


----------



## Jossrik

Quote:


> Originally Posted by *tiamat556*
> 
> are you saying 4x8 single rank is still more likely to work than 2x16 dual rank ? I was under impression, while single rank is more compatible than dual rank, 2 sticks is more compatible than 4.


I have the F4-3200C14D-32GVK. Dual Sided, Dual Rank, and it's been a struggle achieving 3200. I'm on the MSI XPower Gaming Titanium board, which overall I'm pretty happy with, but waiting for the next AGESA update. 3066 runs beautifully though at fairly tight timings. As was said, dual rank is technically faster, but because you can achieve higher speeds with single rank it's easily overcome with single rank simply clocked higher.


----------



## tiamat556

Quote:


> Originally Posted by *Jossrik*
> 
> I have the F4-3200C14D-32GVK. Dual Sided, Dual Rank, and it's been a struggle achieving 3200. I'm on the MSI XPower Gaming Titanium board, which overall I'm pretty happy with, but waiting for the next AGESA update. 3066 runs beautifully though at fairly tight timings. As was said, dual rank is technically faster, but because you can achieve higher speeds with single rank it's easily overcome with single rank simply clocked higher.


have you had better luck with 4x8 3200 bdie dimms ?


----------



## ssateneth

Quote:


> Originally Posted by *LicSqualo*
> 
> Hi, I'm new here.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [email protected] 1.07v---BIOS 0052---HCI---1500%---F4-3600C16-16GTZ


Hi, where did you get DangWang version 20170819 and an english patch for it? I only have Dang Wang Version 2.5 2014/09/22


----------



## Jossrik

Quote:


> Originally Posted by *tiamat556*
> 
> have you had better luck with 4x8 3200 bdie dimms ?


I haven't had the chance to try the 4x8gb BDie yet. BUT, I've read through this forum and the forum for my board (which, granted, doesn't make me an expert), but the people who seem to know their stuff have said many times that dual rank is harder on the memory controller on the chip than single rank, and that's the part that determines how high you can clock your memory stably.


----------



## tiamat556

Quote:


> Originally Posted by *Jossrik*
> 
> I haven't had the chance to try the 4x8gb BDie yet. BUT, I've read through this forum and the forum for my board (which, granted, doesn't make me an expert), but the people who seem to know their stuff have said many times that dual rank is harder on the memory controller on the chip than single rank, and that's the part that determines how high you can clock your memory stably.


i've read that too, but it always seems to be when comparing dual rank vs single rank with 2 dimms. I read an early ryzen memory testing article and basically both 2 die dual rank, and 4 die single rank ended up both capped at 2666mhz


----------



## LicSqualo

Quote:


> Originally Posted by *ssateneth*
> 
> Hi, where did you get DangWang version 20170819 and an english patch for it? I only have Dang Wang Version 2.5 2014/09/22


I don't remember exactly the post, but here in this thread http://www.overclock.net/t/1640919/ryzen-dram-calculator-overclocking-dram.


----------



## Jossrik

Quote:


> Originally Posted by *tiamat556*
> 
> i've read that too, but it always seems to be when comparing dual rank vs single rank with 2 dimms. I read an early ryzen memory testing article and basically both 2 die dual rank, and 4 die single rank ended up both capped at 2666mhz


That's what I originally thought, but I got into a fight with a G.Skill rep once and since have advised different. With Intel (Boo!, anyway) the differences between RAM speeds in real world applications was minimal, and it didn't matter unless you were trying to mix RAM. There's where the biggest difference is. You may have bought a kit when it first came out that was single sided and the same product number kit could be dual sided and you'd think you were getting the same exact RAM, but you wouldn't, and you'd have all kinds of stability issues and not really know why. One of the reasons everyone recommends getting a bigger kit and selling the old RAM. The G.Skill rep even said that older motherboards that haven't had a bios update might not accept dual sided at all, it's newer tech. He said if you had an older motherboard your best bet was eBay. (not kidding). The speed difference between single side and double side is minimal. But dual sided is faster. We're talking benchies only faster. Ryzen is changing all the rules, getting better day by day and by better, I mean easier to tweak, and with the next AGESA update, we may see dual sided overtake single sided RAM because of the more efficient coding. Who knows though. For now, if you have the option, get the 4x8Gb B-Die. As far as capped at 2666, I think that's what it's rated at as achievable by your motherboard QVL. You can go higher, but it's less and less of a guarantee the faster you go.


----------



## blair

Quote:


> Originally Posted by *tiamat556*
> 
> i've read that too, but it always seems to be when comparing dual rank vs single rank with 2 dimms. I read an early ryzen memory testing article and basically both 2 die dual rank, and 4 die single rank ended up both capped at 2666mhz


How recent was this, i'd almost bet it was pre AGESA 1006,

So think of it like this..
Dual Rank is Interleaved for writing to the memory, which is why it's faster, if you are not aware interleaving is where the IMC will perform an operation to Rank 1, while that operation is completing it will perform an operation on Rank 2 while waiting for Rank 1's operation to finish, it then rinses and repeats.

As the IMC with 2 dual rank sticks is now 'almost' writing to 4 sticks, you end up with greater bandwidth, however, you also have a much harder time working all that out, as such you often need to run at a lower clock speed to compensate for the additional work.

Dual rank 'IS' faster than single rank, but.. not by a huge margin, not like what we saw when jumping from Single Channel to Dual Channel memory. Dual channel was a straight up 2x increase, while Dual rank is far less.

So all of this is fine and dandy.. but.. you need to consider the second variable.. the CPU architecture and how that affects your system performance, in this case we are using Ryzen, which as we likely all know utilises AMD's Infinity Fabric, this fabric is the data path that connects each CCX (4 core module) to each other and runs at the clock speed that your memory runs at. Increasing the Infinity fabric speed increases your CPU's ability to complete processing operations. As such, Faster RAM = Faster CPU.

As I've learnt recently Memory clock speed relates to a CPU clock speed that is 'optimal' I.E. Ryzen at 3.9Ghz will see greater benefit from 2800mhz to 3200, than it does form 3200 to 3600. If you boosted the core clock higher, say, 4.2Ghz (unattainable for most) that same 3200 to 3600mhz jump would likely yeild the same linear gain that 2800 to 3200mhz made at 3.8. Basically, RAM speed increases performance, but.. it has limits, those limits are on the CPU.

When Ryzen+ comes out, we might see the architecture reach 4.3-4.4Ghz, which is when DDR4 at 3600Mhz will become something else the main competitor will really need to worry about... (depending how achievable it is....)
When Ryzen 2 comes out, I wouldn't be surprised if the DRAM speed and infinity fabric speed are semi-disconnected from each other and dividers are introduced, meaning we can start to OC the Core and Infinity fabric as well to yield some super performance.

Anyway.. all that said.. RE my earlier post.

If you need to use 64GB RAM get Dual Rank, (lower speed, higher RAM, i.e. Virtual Machines's, Video editing, etc)
If you need 32gb RAM or less, get Single Rank (I.E. Gaming)

something else, i remember seeing something about Dual Rank natively running at 1866, and Single Rank 2400 simply due to the load difference between the two. 1866 to 2400, in terms of performance, i'd take 2400 single rank any day









Really really ask yours how much RAM you actually need... as it will govern what you are capable of achieving.

If you go single rank, and can afford it, drop the extra coin on a 3600 kit or two, you'll thank me later







The faster the kit you buy the higher quality the IC's are, meaning you have a greater chance to achieving your goals.. depending of course.. on your Silicon Lottery chance on the IMC to begin with...









Enjoy and good luck!


----------



## mtrai

Quote:


> Originally Posted by *blair*
> 
> How recent was this, i'd almost bet it was pre AGESA 1006,
> 
> So think of it like this..
> *Dual Rank is Interleaved for writing to the memory, which is why it's faster*, if you are not aware interleaving is where the IMC will perform an operation to Rank 1, while that operation is completing it will perform an operation on Rank 2 while waiting for Rank 1's operation to finish, it then rinses and repeats.
> 
> *As the IMC with 2 dual rank sticks is now 'almost' writing to 4 sticks, you end up with greater bandwidth, however, you also have a much harder time working all that out, as such you often need to run at a lower clock speed to compensate for the additional work.*
> 
> Dual rank 'IS' faster than single rank, but.. not by a huge margin, not like what we saw when jumping from Single Channel to Dual Channel memory. Dual channel was a straight up 2x increase, while Dual rank is far less.
> 
> ster the kit you buy the higher quality the IC's are, meaning you have a greater chance to achieving your goals.. depending of course.. on your Silicon Lottery chance on the IMC to begin with...
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Enjoy and good luck!


Thanks for putting this into simple English that is easy to understand. RIght now I have it set to channel Interleaved but I guess I need to really test all the possible combinations.

Egads all this ddr4 deep discussions are starting to make my head swim. With that said I appreciate all this deep diving as it has given me a better understanding of ram.

All of this has let me obtain 3200 on my E-die dual rank 2 x 8 gb g.skill on my 1700X clocked at 4050. I still cannot pass HCL in windows without errors but it seems pass every other test out there I can find. I must admit that 3200 was never totally stable on my Skylake system either. I could get it 3333 on it but would get lots of BSOD and now GSOD with insider builds. Not so much at all at 3200.

My default speed though is 2133 which does not agree with the last few post for dual rank. I bought this ram a couple of years ago for my i5 6600K build.

G.SKILL Ripjaws V Series 16GB (2 x 8GB) 288-Pin DDR4 SDRAM DDR4 3200 (PC4 25600) Intel Z170 Platform / Intel X99 Platform Desktop Memory Model F4-3200C16D-16GVKB


----------



## Arengeta

Finally got 3466mhz stable with Samsung OEM B-die chips (Samsung M378A1K43BB1-CPB) with no nvidia drivers crashing (did get a black screen for 1 sec during the HCI memtest, but that's about it, before I was getting over 10 black screens before even getting to 50-60%).

Voltages in bios/windows
Vcore - 1.35V/1.36V
SOC - 1.05V/1.068V
DRAM - 1.4V/1.41V
CAD_BUS = 30
ProcODT/RTT_NOM/RTT_PARK/RTT_WR = auto


----------



## Worldwin

Quote:


> Originally Posted by *Arengeta*
> 
> Finally got 3466mhz stable with Samsung OEM B-die chips (Samsung M378A1K43BB1-CPB) with no nvidia drivers crashing (did get a black screen for 1 sec during the HCI memtest, but that's about it, before I was getting over 10 black screens before even getting to 50-60%).
> 
> Voltages in bios/windows
> Vcore - 1.35V/1.36V
> SOC - 1.05V/1.068V
> DRAM - 1.4V/1.41V
> CAD_BUS = 30
> ProcODT/RTT_NOM/RTT_PARK/RTT_WR = auto


Up your ram per HCL to 850 from 750 and have it run for at least 400% since you have 16gb. Also recommend you set CR to 2t since its probably limiting you.


----------



## Arengeta

Quote:


> Originally Posted by *Worldwin*
> 
> Up your ram per HCL to 850 from 750 and have it run for at least 400% since you have 16gb. Also recommend you set CR to 2t since its probably limiting you.


Errors were not a problem, they never occured even up to 1000%, the nvidia driver crash (black screen occuring for 1 second from time to time during the test) was the main issue for me. During this 200% test it only happened once compared to 10+ times before.
As for 850MB, I am somehow unable to run 16 instances with 850MB, not enough ram for that.


----------



## zerowalker

Why is HCI Memtest preferred over something that's run on boot like Memtest86?

EDIT:

I actually can have similar problems with blackscreens even if anything else seems stable,
completely different system though, but if you solve it i might be interested.


----------



## Silent Scone

Quote:


> Originally Posted by *zerowalker*
> 
> Why is HCI Memtest preferred over something that's run on boot like Memtest86?
> 
> EDIT:
> 
> I actually can have similar problems with blackscreens even if anything else seems stable,
> completely different system though, but if you solve it i might be interested.


Short answer. Memtest86 is not relevant on current platforms. It doens't catch instability at any reasonable level. In fact, with it setup correctly with concurrent instances, HCI is a brutal test of stability in comparison. It's also good at catching instability at cache interaction on certain platforms. Google Stress App Test, however, is better at isolating memory.

EDIT: I'm aware the thread hasn't been updated for sometime, I will look at updating the stability tables over the weekend


----------



## Silent Scone

Quote:


> Originally Posted by *superstition222*
> 
> The developer of MemTest HCL said 400% should catch everything.
> 
> It would be nice to have scientific evidence. 1000% is obviously just a number out of a hat because it sounds nice. It's the same number the guy in that video put out.
> 
> 
> 
> Someone at Techpowerup said he doesn't consider a system fully tested unless Memtest is run for 4 days.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Someone also recently posted advice, in a comment to that guy's video, that he should use Techpowerup's new RAM tester. It lets one test RAM with a single instance in Windows. However, I have found, with HCL multiple instances, that the quickest way to uncover errors is to give a small allocation to two instances. I think this creates hot spots. I give one instance 512 MB and one 768 MB, or as little as 384 MB. Running a program that tests all the RAM in a single instance may not uncover errors as quickly.


The amount of coverage time is down to the user, however, I would recommend as suggested running for at least 400% coverage. That is no guarantee that errors won't occur after that. One just needs to keep an open mind that loading up the memory bus in the way HCI does is by no means akin to most workloads. If you can pass for 400% coverage or more, then the memory is likely stable enough, if not unconditionally.


----------



## chroniclard

I can pass GSAT for an hour, Memtest86 pass, then HCI will error after 600%.

Weather or not that proves anything I dont know.









Just passed Memtest 86 so will leave HCI going overnight see what happens.


----------



## Silent Scone

Quote:


> Originally Posted by *chroniclard*
> 
> I can pass GSAT for an hour, Memtest86 pass, then HCI will error after 600%.
> 
> Weather or not that proves anything I dont know.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Just passed Memtest 86 so will leave HCI going overnight see what happens.


Normally run GSAT for 2 hours. It depends on the platform, but memory errors are memory errors


----------



## Esenel

Quote:


> Originally Posted by *Silent Scone*
> 
> EDIT: I'm aware the thread hasn't been updated for sometime, I will look at updating the stability tables over the weekend


Then I will also throw in the 3466 CL14 

[email protected] 1.150v---BIOS 9920---HCI---400%---F4-3200C14D-16GTZ


----------



## zerowalker

Quote:


> Originally Posted by *Silent Scone*
> 
> Short answer. Memtest86 is not relevant on current platforms. It doens't catch instability at any reasonable level. In fact, with it setup correctly with concurrent instances, HCI is a brutal test of stability in comparison. It's also good at catching instability at cache interaction on certain platforms. Google Stress App Test, however, is better at isolating memory.
> 
> EDIT: I'm aware the thread hasn't been updated for sometime, I will look at updating the stability tables over the weekend


Ah nice, thanks.

Is there any test that's good at getting unstable voltage drops (cause of Speedstep, C1E etc, when cpu goes idle and goes back to load for example, as i noticed that can be Extremely hard to get as stress testing doesn't test that as it's always on full load).


----------



## heyider

I have these CMK32GX4M2A2400C16 and an asus b350 prime plus, and a ryzen 1800x, what would be a good overclocking setup for my memories?


----------



## Silent Scone

Quote:


> Originally Posted by *zerowalker*
> 
> Ah nice, thanks.
> 
> Is there any test that's good at getting unstable voltage drops (cause of Speedstep, C1E etc, when cpu goes idle and goes back to load for example, as i noticed that can be Extremely hard to get as stress testing doesn't test that as it's always on full load).


Try Realbench.


----------



## Arengeta

Had to reduce the frequency to 3.8Ghz, the VRM would overheat during load.
Finally had the time to pass 400% HCI with 850MB per instance.


----------



## lordnikon

I just ordered a Ryzen 5 1500X, along with the following:

ASRock AB350M Pro4 MicroATX Mobo:
https://www.newegg.com/Product/Product.aspx?Item=N82E16813157762

CORSAIR Vengeance LPX 2x4GB DDR4 2666 (CMK8GX4M2A2666C16):
https://www.newegg.com/Product/Product.aspx?item=N82E16820233826

The mobo's manual on Page 24 talks about Single Ranked and Dual Ranked memory, and implies that if I wanted to max out the mobo with 64GB of RAM, I would have to use 4x SR dimms of DDR4 2400, or 4x DR dimms of DDR4 2133, and that the max 2666/2667 configuration would be 2x 16GB dimms for a total of 32GB.

If these set of restrictions are true, then HOW does one determine which dimms are "Single Rank" or "Dual Rank" from an online retailer like Newegg or Amazon?

I have never encountered this SR/DR topic before. Any info would be supremely helpful.


----------



## Arengeta

Quote:


> Originally Posted by *lordnikon*
> 
> I just ordered a Ryzen 5 1500X, along with the following:
> 
> ASRock AB350M Pro4 MicroATX Mobo:
> https://www.newegg.com/Product/Product.aspx?Item=N82E16813157762
> 
> CORSAIR Vengeance LPX 2x4GB DDR4 2666 (CMK8GX4M2A2666C16):
> https://www.newegg.com/Product/Product.aspx?item=N82E16820233826
> 
> The mobo's manual on Page 24 talks about Single Ranked and Dual Ranked memory, and implies that if I wanted to max out the mobo with 64GB of RAM, I would have to use 4x SR dimms of DDR4 2400, or 4x DR dimms of DDR4 2133, and that the max 2666/2667 configuration would be 2x 16GB dimms for a total of 32GB.
> 
> If these set of restrictions are true, then HOW does one determine which dimms are "Single Rank" or "Dual Rank" from an online retailer like Newegg or Amazon?
> 
> I have never encountered this SR/DR topic before. Any info would be supremely helpful.


All 16GB ram sticks are dual rank. Most 8GB's are single rank but there is no way to figure out the ranks of one kit just by the specification.


----------



## Jossrik

Quote:


> Originally Posted by *lordnikon*
> 
> I just ordered a Ryzen 5 1500X, along with the following:
> 
> ASRock AB350M Pro4 MicroATX Mobo:
> https://www.newegg.com/Product/Product.aspx?Item=N82E16813157762
> 
> CORSAIR Vengeance LPX 2x4GB DDR4 2666 (CMK8GX4M2A2666C16):
> https://www.newegg.com/Product/Product.aspx?item=N82E16820233826
> 
> The mobo's manual on Page 24 talks about Single Ranked and Dual Ranked memory, and implies that if I wanted to max out the mobo with 64GB of RAM, I would have to use 4x SR dimms of DDR4 2400, or 4x DR dimms of DDR4 2133, and that the max 2666/2667 configuration would be 2x 16GB dimms for a total of 32GB.
> 
> If these set of restrictions are true, then HOW does one determine which dimms are "Single Rank" or "Dual Rank" from an online retailer like Newegg or Amazon?
> 
> I have never encountered this SR/DR topic before. Any info would be supremely helpful.


To muddy the water further, I was told by a G.Skill rep that they can go from single rank to dual rank and keep the same product name/SKU. As tech gets faster they change the process and don't have to say, basically all you can tell from a web site is capacity, latency, and voltage tested.


----------



## bl1tzk1213g

I can't seem to boot even 2133 with these settings for 3466 supposedly. I have booted and tested 3466 before with tighter timings and I was able to boot 3200>3333>3466 but not with these newer and looser timings. I get "D2" mobo error and sends me to boot loop.

I have 3200cl14 trident-z 32gb (8gbx4) for quad channel but only using two sticks. I can run 3200cl14 at 3.9ghz just fine. any tips getting it boot and stable at 3466?


----------



## Arengeta

Quote:


> Originally Posted by *bl1tzk1213g*
> 
> I can't seem to boot even 2133 with these settings for 3466 supposedly. I have booted and tested 3466 before with tighter timings and I was able to boot 3200>3333>3466 but not with these newer and looser timings. I get "D2" mobo error and sends me to boot loop.
> 
> I have 3200cl14 trident-z 32gb (8gbx4) for quad channel but only using two sticks. I can run 3200cl14 at 3.9ghz just fine. any tips getting it boot and stable at 3466?


Because you are using stock delays instead of your XMP settings.


----------



## BadRobot

I upgrade to a Ryzen 1800X, MSI x370 gaming pro, and 2 sticks from a set of Corsair Dominator Platinum 128GX4M8B2800C14. So far, it's managed the 2800 C14-16-16-36 profile and can do 2933Mhz at the same CL. Anything above that results in the motherboard reverting to stock. I can't even get 3000 CL16. Thaiphoon Burner doesn't say what die is used but I suspect Hynix because the CMD32GX4M8B2800C14 is Hynix as well with the same XMP profile and timings.

Is this one a loss or is it worth trying more? The listed revision/version is 4.31 which should be samsung b-die.


----------



## Arengeta

Quote:


> Originally Posted by *BadRobot*
> 
> I upgrade to a Ryzen 1800X, MSI x370 gaming pro, and 2 sticks from a set of Corsair Dominator Platinum 128GX4M8B2800C14. So far, it's managed the 2800 C14-16-16-36 profile and can do 2933Mhz at the same CL. Anything above that results in the motherboard reverting to stock. I can't even get 3000 CL16. Thaiphoon Burner doesn't say what die is used but I suspect Hynix because the CMD32GX4M8B2800C14 is Hynix as well with the same XMP profile and timings.
> 
> Is this one a loss or is it worth trying more? The listed revision/version is 4.31 which should be samsung b-die.


Can't say for sure for 2800C14 ram, I know that 3000C15 and above on Dominator were Samsung B-die.
The kit you're running could be hynix or could be samsung, but they're dual rank and for hynix 2933mhz for dual rank seems to be a rather good result. Samsung an average but could also be the limit for overclocking.


----------



## BadRobot

Quote:


> Originally Posted by *Arengeta*
> 
> Can't say for sure for 2800C14 ram, I know that 3000C15 and above on Dominator were Samsung B-die.
> The kit you're running could be hynix or could be samsung, but they're dual rank and for hynix 2933mhz for dual rank seems to be a rather good result. Samsung an average but could also be the limit for overclocking.


Hell, it doesn't even post with 3000 18-18-18-40 and that's pretty loose. Any of the MemoryTryIt settings saved in the MSI board above 2933C14 don't post or reset to stock. Ver4.31 is very likely Samsung from all the posts I've found. Oh well. It's not worth the money to get a 4000C19 2x8GB set to drop to a comfortable 3466+ or so.


----------



## Arengeta

Quote:


> Originally Posted by *BadRobot*
> 
> Hell, it doesn't even post with 3000 18-18-18-40 and that's pretty loose. Any of the MemoryTryIt settings saved in the MSI board above 2933C14 don't post or reset to stock. Ver4.31 is very likely Samsung from all the posts I've found. Oh well. It's not worth the money to get a 4000C19 2x8GB set to drop to a comfortable 3466+ or so.


DR 2933mhz is equivalent to 3200mhz SR, so I'd say you got a decent result. You could try tightening the secondary timings aswell and playing around with main ones, but the difference most likely won't be noticable.
What SOC are you setting? What vDRAM? Your 4Ghz overclock might be limiting ram overclocks.


----------



## bl1tzk1213g

Quote:


> Originally Posted by *Arengeta*
> 
> Because you are using stock delays instead of your XMP settings.


Can you elaborate more? I did load xmp at 3200, booted to windows, then Back to bios. Sort of figured it out. Timing of 15-15-15 causes not to boot with d2 error, as well as having BGSWAP disabled and BGSWAP ALT enabled. Im anle to boot 3466 with 14-14-14 timings and both bgswap and bgswap alt on auto.

Crashes memtest after a few minutes, temp never reaches near 50 degrees.
Cpu at 1.39v
ddr at 1.44
soc at 1.14
Vddp .890
Cldo_vddp 650
Rtt > rzq7/disabled/rzq5
30/30/30 ohms


----------



## Arengeta

Quote:


> Originally Posted by *bl1tzk1213g*
> 
> Can you elaborate more? I did load xmp at 3200, booted to windows, then Back to bios. Sort of figured it out. Timing of 15-15-15 causes not to boot with d2 error, as well as having BGSWAP disabled and BGSWAP ALT enabled. Im anle to boot 3466 with 14-14-14 timings and both bgswap and bgswap alt on auto.
> 
> Crashes memtest after a few minutes, temp never reaches near 50 degrees.
> Cpu at 1.39v
> ddr at 1.44
> soc at 1.14
> Vddp .890
> Cldo_vddp 650
> Rtt > rzq7/disabled/rzq5
> 30/30/30 ohms


http://www.overclock.net/t/1640919/ryzen-dram-calculator-overclocking-dram/0_100#
Step 3 and 4 in the instruction. You have used basic delays for B-die single rank modules instead of the XMP parameters.
SOC is quite high, I'm able to run my 3466mhz ram on as low SOC as 1.025V, might try to lower that a bit. The RAM voltage is also quite high. Higher voltages on DDR/SOC does not necessarily mean you will be more stable, infact if I set my vDRAM to 1.42V instead of 1.39V I'll start getting errors below 100% on HCI memtest while on 1.39V I'm stable.


----------



## mtrai

Quote:


> Originally Posted by *Arengeta*
> 
> DR 2933mhz is equivalent to 3200mhz SR, so I'd say you got a decent result. You could try tightening the secondary timings aswell and playing around with main ones, but the difference most likely won't be noticable.
> What SOC are you setting? What vDRAM? Your 4Ghz overclock might be limiting ram overclocks.


Wait a minute...I am now curious...as I did not know this...DR 2933 is the equivalent to 3200 SR...can you point me to where I can read about the DR vs SR ram?

Assuming this is correct and no reason not to believe you this would explain why my 1700X build scores the way it does in benchmarks since I have Dual Rank 2 x 8 D-die sticks at 3200 16 15 15 15 21 54 309 1t+


----------



## bl1tzk1213g

Quote:


> Originally Posted by *Arengeta*
> 
> http://www.overclock.net/t/1640919/ryzen-dram-calculator-overclocking-dram/0_100#
> Step 3 and 4 in the instruction. You have used basic delays for B-die single rank modules instead of the XMP parameters.
> SOC is quite high, I'm able to run my 3466mhz ram on as low SOC as 1.025V, might try to lower that a bit. The RAM voltage is also quite high. Higher voltages on DDR/SOC does not necessarily mean you will be more stable, infact if I set my vDRAM to 1.42V instead of 1.39V I'll start getting errors below 100% on HCI memtest while on 1.39V I'm stable.


Here's the XMP timings, not that far off. Still crashes within minutes.


----------



## Arengeta

Quote:


> Originally Posted by *bl1tzk1213g*
> 
> Here's the XMP timings, not that far off. Still crashes within minutes.


Have you tried CLDO VDDP 0.425?
Try lowering SOC and voltages and see if it makes any changes. Also I would recommend trying to use RTT's on auto and ProcODT (my motherboard picks better settings than auto and I have yet to figure out which ones). 3466 with low timings requires plenty of different tweaks and lots of time testing.
Сan also try different CAD_BUS, 20 or 24.


----------



## BadRobot

Quote:


> Originally Posted by *Arengeta*
> 
> DR 2933mhz is equivalent to 3200mhz SR, so I'd say you got a decent result. You could try tightening the secondary timings aswell and playing around with main ones, but the difference most likely won't be noticable.
> What SOC are you setting? What vDRAM? Your 4Ghz overclock might be limiting ram overclocks.


CPU 1.4V
NB/Soc 1.2125V (but bios says 1.248
DRAM 1.4V

These timings are the closest to what I have with auto. That's with D/E/C die ram.


On a related note, the prime95 blend test has always crashed at about 30-35 minutes in, probably due to a mode change. MemTest can go to 6000% with no errors and all the benchmarks, including Intel burn test, complete very well. Dropped to 3.95Ghz for the cpu so maybe something with the LLC compensating too much on the ram or CPU?


----------



## Arengeta

Quote:


> Originally Posted by *BadRobot*
> 
> NB/Soc 1.2125V (but bios says 1.248
> 
> On a related note, the prime95 blend test has always crashed at about 30-35 minutes in, probably due to a mode change. MemTest can go to 6000% with no errors and all the benchmarks, including Intel burn test, complete very well. Dropped to 3.95Ghz for the cpu so maybe something with the LLC compensating too much on the ram or CPU?


SOC is way too high, I'd say at the edge of frying motherboard or CPU. I found anything above 1.1V unnecessary unless you're trying for extreme RAM overclocks (above 3600mhz).
You're also stressing your VRM really bad with such high voltages, it can't withstand them and that explains your crashes in prime95. (check your VRM temps, i'd say they're prolly well over 100C).


----------



## BadRobot

Quote:


> Originally Posted by *Arengeta*
> 
> SOC is way too high, I'd say at the edge of frying motherboard or CPU. I found anything above 1.1V unnecessary unless you're trying for extreme RAM overclocks (above 3600mhz).
> You're also stressing your VRM really bad with such high voltages, it can't withstand them and that explains your crashes in prime95. (check your VRM temps, i'd say they're prolly well over 100C).


I'll set them lower when I wake up tomorrow. Ah~ sandy bridge was much easier to overclock. I'll check HWInfo and HWMonitor for vrm temps if they're listed.


----------



## BadRobot

Quote:


> Originally Posted by *Arengeta*
> 
> SOC is way too high, I'd say at the edge of frying motherboard or CPU. I found anything above 1.1V unnecessary unless you're trying for extreme RAM overclocks (above 3600mhz).
> You're also stressing your VRM really bad with such high voltages, it can't withstand them and that explains your crashes in prime95. (check your VRM temps, i'd say they're prolly well over 100C).


Yep. Thanks for the pointer, man. 1h20m of prime95 blend test with CPU maxing out at Tctl at 102.8, Tdie at 82.8 and stabilizing at 95.0/75.0. The highest temps from the board is TMPIN4 at 89 and AUXTIN at 70 Celsius.

Time to work on those subtimings!


----------



## DVH2015

Quote:


> Originally Posted by *Praz*
> 
> Hello
> 
> [email protected] 1.10v---BIOS 1107---HCI---800%/GSAT 2 Hours---F4-3600C17D-32GTZ


Praz, one question. In the images it says F4-3600C15 but you wrote...C17D.. which is also on the first page. Do I miss something?


----------



## Praz

Quote:


> Originally Posted by *DVH2015*
> 
> Praz, one question. In the images it says F4-3600C15 but you wrote...C17D.. which is also on the first page. Do I miss something?


Hello

I have corrected the post. The memory used was 2 kits of F4-3600C15D-16GTZ.


----------



## happyluckbox

Anybody have any tips on stabilizing 128gb of ram @3060mhz at 14-14-14-30-2T?
It's actually totally stable for everything outside of hci memtest, and it hci only throws 1 error every few hours or so.

Dropping to 2933mhz eliminates the issue entirely.


----------



## ZeNch

Hello, i have a problem:

i change my case and my cpu cooler and when i power on my pc again i have cold boots, i set high timmings other ProcODT 2T and nothing, i select 2133 and boot perfect, i try with 3200 again but with more voltage and go unstable but boot.

before [email protected] stable
now [email protected] to boot (unstable)

i change my rams to other socket and go better (boot at 1.375 without cold boots).

any idea?

i dont change other piece and dont update bios or other thing.

My rams dont like the new home (case) xD


----------



## ZeNch

update:


Errors 8 but i see 6 ._.
all error are the same in the same test.
my settings are AUTO in all settings (cpu and ram in auto without oc)

few weeks ago i try to play BF4 and i have force close i think memory problem, i change my settings to old OC (tested befor and work perfect) and its fail again.

i think: its my cpu.
i put my ram in auto and i cant pass 3 hours with prime (before with this setting i pass ALL test, 12 hours of prime) i need more vCore and pass 10 hours but not more. i try test my old settings of OC and the same, fail.

i use this for months and now its fail.

My settings of cpu (before work perfect)
[email protected]
[email protected]
*
i post it here for the error in memtest, its rare i never see the same errors repeat in various cores.*

CPU problem?

i dont use high LLC and not use high vCore and my temps are ever low than 72 in stress.


----------



## Shovel Knight

Quote:


> Originally Posted by *happyluckbox*
> 
> Anybody have any tips on stabilizing 128gb of ram @3060mhz at 14-14-14-30-2T?
> It's actually totally stable for everything outside of hci memtest, and it hci only throws 1 error every few hours or so.
> 
> Dropping to 2933mhz eliminates the issue entirely.


I would consider not ******* around with it past 2933 anymore. I have had issues with my USB connections malfunctioning. Others have attributed this to high VDDP voltage, but a previously stable HCI test at 2933 still rendered USB issues for me, even with my VDDP voltage at .90, which irritated the **** out of me.

I am not running overclocked anymore as there is no game in my arsenal demanding it currently. All of my games are maxed out at 1080p, with my 1700X and XFX RX 480. I can even run some 4K games, such as Dark Souls 3, better than my XBox One X, due to my better processor. I definitely don't want to fry my processor until AMD releases better guidance for overclocking Ryzen.

That being said, I would recommend trying to raise TRFC timings. There may be micro adjustments necessary in TrrDS and TrrDL settings necessary for many RAM kits to function optimally at any given speed setting, and as it stands there is no software to optimize your RAM for you.

I have emailed HCI about coming up with a way to adjust RAM based on statistical difference errors. They said it was an interesting idea. When trying to push my RAM to 3200 Mhz, I can get it stable like yours, but with error every 15 seconds saying "Difference of 8", and adjusting some timings made the errors more or less frequent, while other timings changed the difference values. Without understanding HCI's source code, I can only assume that HCI calculates difference errors as RAM reporting memory cells which are 8 matrice units away from where they are supposed to be reading, and I would love a comprehensive guide on how to walk my ram towards a difference of zero, or a frequency of 0.

There are literally trillions of possible ways to configure RAM, and this is why I hate overclocking RAM and think that marketing overclocked RAM is somewhat of a scam, as it has potential to degrade your CPU, there is practically zero guidance on overclocking your RAM, and even purchasing exact overclocked RAM kits on my MoBo's vendor list doesn't result in perfect timings, even with assumed pre-tested XMP profiles. There is no official standard for what is a "stable" overclock and until there is, I am not going to upgrade my RAM kit any further. It is extremely demanding to ask vendors to test each and every RAM kit for each and every motherboard, but in my opinion, if you want to sell me an overclocked RAM kit, and claim that the Perfect Tender Rule and Mutual Consideration Rules in contract law have been satisfied, vendor lists need a much higher standard. This thread is a step toward that, and you guys rock.

Thanks!


----------



## freestaler

Hi all,

I trying to get 3600 stable. At the moment it is only "Bench" stable (2x 8 GB SR 3600-14-14-14-22-36-1T). No chance to get more as 30% in HCL at 3600. I did try the timmings and settings from RamCalc, but not chance to boot. This at Stable,Fast and Exterme Preset. Try changes at the Cold_VDDP between 840 - 940 (around +12 steps). It didnt help. No way. Wtih my "own" Timmings i can boot and bench but no chance to get stable. Aso try to lower my timmings much and play with the must settings, like ProcODm, VDDP, ColdVDDP, CAD Bus, Votage, GDM and some stoff .

Maybe someone has for me a Tip, or had the same problem and know a way to get stability on this kind of ram (not the usually 3200-14 Trident) or with my board.

HW;

Asrock x370 Taichi
1700 @ 3.8 @ 1.35 Vcore (100mhz less to not test cpu ;-) , LLC2 and PState)
VSoc 1.125
VDDP 930
Trident F4 4133 c19d (19-21-21-41) GTZA https://www.gskill.com/en/product/f4-4133c19d-16gtza (only avaible B Die on the orderday of the rest of my system) @ 1.48



or



just for info, 3466 is possbile (this run with less critiical Timings, but this timings doenst works on 3600)


----------



## Shovel Knight

A Google Deep Mind Alpha RAM overclocking Mobo Chip would be sick. Especially if it was held to an HCI standard or used HCI.


----------



## bl1tzk1213g

Does ram temp affect stability? At around what temp does instability start according to your guys' observation?


----------



## sakae48

yes. my sticks would run at 3866 at under 30C but would not even boot above that. and my IMC wouldn't run at 3866 if CPU temp above 35C


----------



## Esenel

Quote:


> Originally Posted by *bl1tzk1213g*
> 
> Does ram temp affect stability? At around what temp does instability start according to your guys' observation?


Yes it does. Beginning at ~49°C.

http://www.overclock.net/t/1640919/ryzen-dram-calculator-overclocking-dram/420_30#post_26471942

http://www.overclock.net/t/1640919/ryzen-dram-calculator-overclocking-dram/420_30#post_26472770


----------



## krys

Hi all,
Just finished my first ryzen build and new to this world








Before doing a stability test for the memory, I have read the instruction and have 2 questions from the quote below
1. what " suggested means » mean?
2. How do you test your « general system »? For the CPU I read that cinebanch or realbanch are good tool, but how do you test your general system?

Thx

Should you go without saying that general system and CPU stability should be gauged via the suggested means before attempting an outright memory stability test.


----------



## Arengeta

Quote:


> Originally Posted by *krys*
> 
> Hi all,
> 1. what " suggested means » mean?
> 2. How do you test your « general system »? For the CPU I read that cinebanch or realbanch are good tool, but how do you test your general system?


2. LinX 0.7.0 AMD version for CPU and HCI memtest for RAM stability.


----------



## generaleramon

Someone with a Biostar X370GTN stable @3600Mhz?
I have a 2x8GB TridentZ 3200CL14 set.
I'm testing the lasted bios with AGESA 1.0.7.2a.
[email protected] is fine, [email protected] needs +200mv on the SOC Voltage to be near stable...100% stable with 1 slot used @3600Mhz and stock SOC.
Trying now with the 3333Mhz strap+105Blck=3500MHz... Not bad for a ITX board and a R7-1700


----------



## Milestonegio

[email protected] 1v---BIOS 3401---HCI---400%---416G3000HC16CDC01
(1600 + B350 Strix + 2x8GB T-Force 3000MHz C16-18-18-38 Dual Rank Samsung S-Die, procODT=60, CADs: 20-20-30-30).


Upd: voltage finally start doing it's job. 2933Mhz-C12-15-15-34-1T seems stable but only at 1.475V.


----------



## JD809

I'm using a biostar x370gtn with a ryzen 1600x cpu, I've got a Corsair CMK16GX4M2E4000C19R Vengeance LPX 16 GB (2x8 GB). But I'm struggling to hit 3600mhz speed barely stable on 3466mhz, so I'm looking for advice on how I can hit that target as a lot of the guides for overclocking the ram on ryzen don't use biostar boards.


----------



## mth21

Help i cant get my LPX 3000 CL15 stable,

My mobo is ASUS Strix B350F
last stable is on BISO 0902 , ryzen 1600 @3,85 ram 2933 Mhz

since then, all bios update ruining my overclock stability, since i can not downgrade the bios (risky), i just keep updating , till now (3401) i can not get my ram stable even at 2666 settings
i have tried :
2933 16-17-17-17-35 soc 1,1v dram 1,35 procodt Auto, HCI error
2933 17-18-18-18-38 soc 1,1v dram 1,38 procodt 60, HCI error
2666 17-18-18-18-38 soc 1,1v dram 1,38 procodt 60, HCI error

no idea what cause my issues, ram stick is no probelm, HCI pass at stock 2133

sometimes i use memtest86 dos , 4 passes passed , when HCI error at 200%

I have latest windows update , should i trus HCI or memtest86? I have my cpu at stock setting when overclocking my ram,

Now all are at default setting just to be safe,

please help, thank you


----------



## ZeNch

Quote:


> Originally Posted by *mth21*
> 
> Help i cant get my LPX 3000 CL15 stable,
> 
> My mobo is ASUS Strix B350F
> last stable is on BISO 0902 , ryzen 1600 @3,85 ram 2933 Mhz
> 
> since then, all bios update ruining my overclock stability, since i can not downgrade the bios (risky), i just keep updating , till now (3401) i can not get my ram stable even at 2666 settings
> i have tried :
> 2933 16-17-17-17-35 soc 1,1v dram 1,35 procodt Auto, HCI error
> 2933 17-18-18-18-38 soc 1,1v dram 1,38 procodt 60, HCI error
> 2666 17-18-18-18-38 soc 1,1v dram 1,38 procodt 60, HCI error
> 
> no idea what cause my issues, ram stick is no probelm, HCI pass at stock 2133
> 
> sometimes i use memtest86 dos , 4 passes passed , when HCI error at 200%
> 
> I have latest windows update , should i trus HCI or memtest86? I have my cpu at stock setting when overclocking my ram,
> 
> Now all are at default setting just to be safe,
> 
> please help, thank you


try with it: http://www.overclock.net/t/1640919/ryzen-dram-calculator-overclocking-dram


----------



## Trender07

I can boot up to 3466 MHz easy but I can't get stable more than 3200 MHz.(Yes I tried with Ryzen calculator timings, and my mems are samsung bdie 3600)


----------



## Milestonegio

[email protected]-SOC 1v---BIOS 3401---HCI---1500%---416G3000HC16CDC01
(1600 + B350 Strix + 2x8GB T-Force 3000MHz C16-18-18-38 Dual Rank Samsung S-Die, procODT=60, CADs: 20-20-30-30).


It's just stupid but it's stable as you can see.

Some observations on S-Die:
It can't run Clock/RD near 200 (Something around 196 is stable but at 200+ no post at all), RAS<34 and RC<49 at any voltage up to 1.6V.

Please explain why I get such high latency an AIDA64. On BIOS 1001 it was around 79 at C14-16-16-34 which is also too high from my point of view. Sadly, i can't get stable 3200/3333/3466 since i haven't VDDP_CLDO control.


----------



## mth21

i have tried this tool. fast and safe timing, not even post


----------



## JD809

Quote:
same
Quote:


> Originally Posted by *mth21*
> 
> i have tried this tool. fast and safe timing, not even post


Same on a biostar x370gtn.


----------



## mth21

Quote:


> Originally Posted by *ZeNch*
> 
> try with it: http://www.overclock.net/t/1640919/ryzen-dram-calculator-overclocking-dram


Quote:


> Originally Posted by *JD809*
> 
> same
> Same on a biostar x370gtn.


What make me confuse is, my memory have a lot off error in gsat and hci, even at stock bios setting
This all happen since 3203
I have not try memtest86, will try tonight

I have
Ryzen 5 1600
CMK16GX4M2B3000C15 8 GBx2 (dual channel 2 rank, micron b-die), XMP 15-17-17-35 1.35v
STRIX B350-F (currently runnign on 3401 , problem still exist)

Anyone have the same hardware , pleae help


----------



## ZeNch

The calculator not is perfect is a help to known your ram. in my RIG if i set TRFC with calculator settings... dont post (M-Die)


----------



## mth21

Quote:


> Originally Posted by *mth21*
> 
> What make me confuse is, my memory have a lot off error in gsat and hci, even at stock bios setting
> This all happen since 3203
> I have not try memtest86, will try lastnight
> 
> I have
> Ryzen 5 1600
> CMK16GX4M2B3000C15 8 GBx2 (dual channel 2 rank, micron b-die), XMP 15-17-17-35 1.35v
> STRIX B350-F (currently runnign on 3401 , problem still exist)
> 
> Anyone have the same hardware , pleae help


Hello,

I have run memtest86 tonihgt (default bios setting)
8 passes passed without any error


So i assume the memory stick is good right ?

So i guess the problem is either with my BIOS or Windows system ,
let me know what you think

Thanks


----------



## ZeNch

i like to test 12 or 16 passes of memtest (i see errors in pass number 10 for example).

Try to set your vSoc at 1.0875v.

i dont use gsat, and hci need to run 12 instances (in Ryzen 1600)with: your free ram/12

(12runs of 1000mb sound fine).

in the task mannager you need to set each instance with one cpu core.


----------



## mth21

Quote:


> Originally Posted by *ZeNch*
> 
> i like to test 12 or 16 passes of memtest (i see errors in pass number 10 for example).
> 
> Try to set your vSoc at 1.0875v.
> 
> i dont use gsat, and hci need to run 12 instances (in Ryzen 1600)with: your free ram/12
> 
> (12runs of 1000mb sound fine).
> 
> in the task mannager you need to set each instance with one cpu core.


is it possible if the windows/BIOS update causing my memory error?

actually i never have windows crash or even BSOD , i found the error when doing re-test after updating BIOS to 3401


----------



## ZeNch

Quote:


> Originally Posted by *mth21*
> 
> is it possible if the windows/BIOS update causing my memory error?
> 
> actually i never have windows crash or even BSOD , i found the error when doing re-test after updating BIOS to 3401


i dont know if its possible but the same situation here.


----------



## mth21

Quote:


> Originally Posted by *ZeNch*
> 
> i dont know if its possible but the same situation here.


if you have the same problem, so i guess the bios must be causing the problem?


----------



## Needhelp666

commandrate 1t is unstable for some reason..


----------



## mth21

Quote:


> Originally Posted by *ZeNch*
> 
> i like to test 12 or 16 passes of memtest (i see errors in pass number 10 for example).
> 
> Try to set your vSoc at 1.0875v.
> 
> i dont use gsat, and hci need to run 12 instances (in Ryzen 1600)with: your free ram/12
> 
> (12runs of 1000mb sound fine).
> 
> in the task mannager you need to set each instance with one cpu core.




I just did 12 passes ,
Does this look good?

but still can not pass 1 hour gsat

haha

[EDIT]

i just passed 1 hour gsat with auto timing and set the dram volt to 1.36 (kind of frustating with the manual timing







)

what you think, does the result good?




[EDIT 2]
Somehow when i combine CPU OC and RAM OC , the gsat fail again , no idea if that two related
was able to pass when CPU stock and RAM OC


----------



## bigfootnz

[email protected] 1.075v---BIOS 1701---HCI---1000%



I've little problem, or I think that I've problem, with my memory. I've done all stability tests, HCI 1000%, Prime95 both blend and smallFFT without problems. But on AIDA64 memory benchmark for L3 Cache Copy speed I've occasional drops in speed as you can see on second image.



But if I increase SOC voltage to 1.1375V this problem is happening only occasional, but still is happening sometimes. Now my question is this problem or this is normal to have this speed drops. I do not have any other problems, everything is working like a charm. So should I bring SOC voltage to 1.075v or keep it at 1.1375V or even try it with bigger voltage? Or maybe try to play with ProcODT whihc is auto at the moment. As I've found somewhere info that L3 Cache speed drops are linked to insufficient SOC voltage, but again all stability test have been passed without errors and in normal PC usage I do not have any problems.


----------



## kazablanka

I think that numbers in aida shouldn't bother you. Aida isnt the most accurate program to check bandwidth but it is ok for taking a look for how your system performs. Try to run aida by booting in safe mode


----------



## bigfootnz

OK, I'll try in safe mode to see is there any difference.


----------



## bl1tzk1213g

What else affects stability? Does CLDO_VDDP affect stability or just memory holes to boot? I've tried all kinds of CLDO VDDP 425, 700, 866, 850, 950 etc. Still could not get past 50% HCI memtest.

I'll post my timings and voltages on the bottom. I used Ryzen calculator for my memory. So many things to try and I want to know which setting/voltage I should change first. Too much voltage dram/soc gives me even more errors.

3466 mhz
VDDP .890
20/20/20/20 ohms


----------



## Albert1007

Hi guys,
Is it safe to run DDR4 at ~1.45V for 24/7 usage?


----------



## sideeffect

Hello everybody. Thanks for all the informative posts I have read some of the thread and gained good ideas and settings advice.

Thought I would share my stable settings using slightly more unusual modules. *ADATA Z1 DDR4 2400MHz 2x16GB* 16-16-16-39-55 dual rank modules.

They boot at 3066Mhz but are not stable even with super relaxed timings. 3200Mhz they won't even boot. 2933Mhz they are stable and I was able to tighten the timings a great deal they don't like lower TRCD/TRP timings but surprisingly they don't mind low CAS latency.

Voltages
CPU - 1.30625v set in Zenstates with LLC Auto
SOC - 1.0v set in BIOS with SOC LLC Auto
RAM - 1.37v


----------



## Arengeta

Quote:


> Originally Posted by *bl1tzk1213g*
> 
> What else affects stability? Does CLDO_VDDP affect stability or just memory holes to boot? I've tried all kinds of CLDO VDDP 425, 700, 866, 850, 950 etc. Still could not get past 50% HCI memtest.
> 
> I'll post my timings and voltages on the bottom. I used Ryzen calculator for my memory. So many things to try and I want to know which setting/voltage I should change first. Too much voltage dram/soc gives me even more errors.
> 
> 3466 mhz
> VDDP .890
> 20/20/20/20 ohms


CAD BUS, ProcODT, too high DRAM voltage, too high SOC voltage could also cause errors in HCI. Too low tWRWR SCL, tRDRD SCL, tRCDRD.
Try geardownmode enabled.

Is this enough to be in the list? Samsung OEM B-die.


----------



## DR4G00N

Quote:


> Originally Posted by *Albert1007*
> 
> Hi guys,
> Is it safe to run DDR4 at ~1.45V for 24/7 usage?


Depends on what IC's the sticks have, for Samsung that's no problem, some of the higher freq kits run at 1.5V for their XMP profiles.
I'd assume that it would be fine on all other IC's as well.


----------



## floatboth

Hi everyone. I have finally acquired some B-die, namely KFA2 Hall of Fame DDR4-4000 CL19.

(Thaiphoon Burner actually did not recognize the exact model and said "K4A8G085W?", but 4000C19 rated single rank 8gb memory that can actually boot when tRCD/tRP are 1 lower than tCL must be B-die







)

Very aggressive settings like 3466 CL14 can boot but are extremely unstable. Now trying 3333 CL15 based on the Safe preset from the calculator, but a bit tightened. It was going great&#8230; but then an error happened at 540%:




So far it seems that these sticks prefer lower voltage (1.37 currently, more stable than >1.4) and also higher tRAS than the Fast profile&#8230;

This is significantly faster than the cheap Hynix sticks I had, but I'm not super impressed with the legendary B-die that supposedly likes high voltages and runs extreme settings no problem. Did I lose the silicon lottery on the sticks?


----------



## Arengeta

Quote:


> Originally Posted by *floatboth*
> 
> Hi everyone. I have finally acquired some B-die, namely KFA2 Hall of Fame DDR4-4000 CL19.
> 
> (Thaiphoon Burner actually did not recognize the exact model and said "K4A8G085W?", but 4000C19 rated single rank 8gb memory that can actually boot when tRCD/tRP are 1 lower than tCL must be B-die
> 
> 
> 
> 
> 
> 
> 
> )
> 
> Very aggressive settings like 3466 CL14 can boot but are extremely unstable. Now trying 3333 CL15 based on the Safe preset from the calculator, but a bit tightened. It was going great&#8230; but then an error happened at 540%:
> 
> 
> 
> 
> So far it seems that these sticks prefer lower voltage (1.37 currently, more stable than >1.4) and also higher tRAS than the Fast profile&#8230;
> 
> This is significantly faster than the cheap Hynix sticks I had, but I'm not super impressed with the legendary B-die that supposedly likes high voltages and runs extreme settings no problem. Did I lose the silicon lottery on the sticks?


Try fast settings with procodt 53, wrwrscl 4, rdrdscl 4


----------



## datspike

Quote:


> Originally Posted by *floatboth*
> 
> Did I lose the silicon lottery on the sticks?


More likely that IMC quality on your CPU is not the best, I'm feeling like that's the limiting factor for memory OC on Ryzen right now


----------



## shilent

I upgraded my Crosshair VI BIOS from 1403 to 3008 yesterday.

I'm now getting GSAT error in less than 10 minutes. Doesn't seem to matter what speed I run my memory at. I put my CPU back to stock and even tried leaving memory settings on auto which ran it at 2133 and that made zero difference.

I'm running GSkill 3466 CL16 B-die, and I use the Stilts 3200 fast settings.

Everything else seems fine and stable, HCI memtest, Intelburntest, gaming, etc.

Anyone seen this? I wasted many hours trying to get GSAT error free. I'm going to ignore GSAT until I see instability elsewhere.


----------



## Bartouille

memtestlauncher.zip 32k .zip file


memtestlaunchersrc.zip 9k .zip file


Made a program to automatically start the free version of memtest. Feel free to use it.


----------



## bigfootnz

Just update on my Mem OC. With my Corsair CMK16GX4M2B3200C16 OC to 3.2GHz [email protected] HCI has passed test @1000% but GSAT has failed almost immediately. After memory tweaking I've found stable memory OC with 3hours GSAT 3.2GHz [email protected] Now I don't have any more those drops in L3 cache memory test.

In my case HCI is not relevant for memory test at all.


----------



## harrysun

Quote:


> Originally Posted by *bigfootnz*
> 
> In my case HCI is not relevant for memory test at all.


It's all about likelihoods which application fails (someday). I've done all these test until Prime95 failed:

AIDA64 6-8h *passed*: CPU & RAM
BOINC 6-8h (pending): CPU
Google stressapptest (GSAT) 6h *passed*: CPU & RAM
IntelBurnTest v2.54 IBT AVX 30 run Level Maximum *passed*: CPU & RAM
OCCT Perestroïka 4h *passed*: CPU
HCI Memtest Deluxe (at least 200% for 32GB) *passed 500+%*: RAM
y-cruncher 24h (pending): CPU
Prime95 6-8h *failed 5+h*: CPU (& RAM)


----------



## floatboth

Quote:


> Originally Posted by *Arengeta*
> 
> Try fast settings with procodt 53, wrwrscl 4, rdrdscl 4


Nah that shows errors very quickly







Safe with the SC_L timings at 4 though, is overnight stable!



But the performance drop (from t*SC_L 3) is very significant&#8230;


----------



## Nighthog

My new motherboard seems much worse for memory overclocking than my first board. I was seeing results to be able to use 3066 with tighter timings on F10 bios for my previous board but the new one can't even manage too tight timings with 2933Mhz yet. Though I'm running without water this time around but was expecting to just click in my old settings and be done. Didn't work out closely at all. Extensive testing has been needed to find the culprit timings that aren't cooperating.


----------



## ph1ber

So pretty happy this morning. Woke up to seeing that MemTest64 had run it's 8 hours with no errors. Finally I got something stable to work from







I got the timings from another user i C6H thread and they worked out really well for me. Posting bios settings as well. Hope this helps someone








Asus Crosshair 6 Hero Bios 3101.




Spoiler: BIOS Settings



[2017/12/26 10:57:42]
Ai Overclock Tuner [D.O.C.P. Standard]
D.O.C.P. [D.O.C.P DDR4-3603 15-15-15-35-1.35V]
BCLK Frequency [100.2000]
BCLK_Divider [Auto]
Custom CPU Core Ratio [Auto]
> CPU Core Ratio [38.00]
Performance Bias [Auto]
Memory Frequency [DDR4-3339MHz]
Core Performance Boost [Disabled]
SMT Mode [Auto]
EPU Power Saving Mode [Disabled]
TPU [Keep Current Settings]
CPU Core Voltage [Manual mode]
- CPU Core Voltage Override [1.32500]
CPU SOC Voltage [Manual mode]
- VDDSOC Voltage Override [1.05000]
DRAM Voltage [1.37500]
1.8V PLL Voltage [Auto]
1.05V SB Voltage [Auto]
Target TDP [Auto]
TRC_EOM [Auto]
TRTP_EOM [Auto]
TRRS_S_EOM [Auto]
TRRS_L_EOM [Auto]
TWTR_EOM [Auto]
TWTR_L_EOM [Auto]
TWCL_EOM [Auto]
TWR_EOM [Auto]
TFAW_EOM [Auto]
TRCT_EOM [Auto]
TREFI_EOM [Auto]
TRDRD_DD_EOM [Auto]
TRDRD_SD_EOM [Auto]
TRDRD_SC_EOM [Auto]
TRDRD_SCDLR_EOM [Auto]
TRDRD_SCL_EOM [Auto]
TWRWR_DD_EOM [Auto]
TWRWR_SD_EOM [Auto]
TWRWR_SC_EOM [Auto]
TWRWR_SCDLR_EOM [Auto]
TWRWR_SCL_EOM [Auto]
TWRRD_EOM [Auto]
TRDWR_EOM [Auto]
TWRRD_SCDLR_EOM [Auto]
Mem Over Clock Fail Count [Auto]
DRAM CAS# Latency [14]
DRAM RAS# to CAS# Read Delay [14]
DRAM RAS# to CAS# Write Delay [14]
DRAM RAS# PRE Time [14]
DRAM RAS# ACT Time [22]
Trc [36]
TrrdS [5]
TrrdL [8]
Tfaw [30]
TwtrS [3]
TwtrL [12]
Twr [10]
Trcpage [Auto]
TrdrdScl [2]
TwrwrScl [2]
Trfc [266]
Trfc2 [Auto]
Trfc4 [Auto]
Tcwl [14]
Trtp [8]
Trdwr [7]
Twrrd [3]
TwrwrSc [1]
TwrwrSd [7]
TwrwrDd [7]
TrdrdSc [1]
TrdrdSd [5]
TrdrdDd [5]
Tcke [1]
ProcODT [53.3 ohm]
Cmd2T [1T]
Gear Down Mode [Enabled]
Power Down Enable [Auto]
RttNom [RZQ/7]
RttWr [Dynamic ODT Off]
RttPark [RZQ/5]
MemAddrCmdSetup_SM [Auto]
MemCsOdtSetup_SM [Auto]
MemCkeSetup_SM [Auto]
MemCadBusClkDrvStren_SM [30.0 Ohm]
MemCadBusAddrCmdDrvStren_SM [30.0 Ohm]
MemCadBusCsOdtDrvStren_SM [30.0 Ohm]
MemCadBusCkeDrvStren_SM [30.0 Ohm]
VTTDDR Voltage [0.69300]
VPP_MEM Voltage [Auto]
DRAM CTRL REF Voltage on CHA [Auto]
DRAM CTRL REF Voltage on CHB [Auto]
VDDP Voltage [Auto]
VDDP Standby Voltage [Auto]
1.8V Standby Voltage [Auto]
CPU 3.3v AUX [Auto]
2.5V SB Voltage [Auto]
DRAM R1 Tune [Auto]
DRAM R2 Tune [Auto]
DRAM R3 Tune [Auto]
DRAM R4 Tune [Auto]
PCIE Tune R1 [Auto]
PCIE Tune R2 [Auto]
PCIE Tune R3 [Auto]
PLL Tune R1 [Auto]
PLL reference voltage [Auto]
T Offset [Auto]
Sense MI Skew [Auto]
Sense MI Offset [Auto]
Promontory presence [Auto]
Clock Amplitude [Auto]
CLDO VDDP voltage [Auto]
CPU Load-line Calibration [Level 2]
CPU Current Capability [110%]
CPU VRM Switching Frequency [Manual]
CPU Voltage Frequency [300]
CPU Power Duty Control [T.Probe]
CPU Power Phase Control [Auto]
CPU Power Thermal Control [120]
VDDSOC Load-line Calibration [Level 2]
VDDSOC Current Capability [Auto]
VDDSOC Switching Frequency [Manual]
Fixed VDDSOC Switching Frequency(KHz) [300]
VDDSOC Phase Control [Auto]
DRAM Current Capability [110%]
DRAM Power Phase Control [Extreme]
DRAM Switching Frequency [Manual]
Fixed DRAM Switching Frequency(KHz) [300]
DRAM VBoot Voltage [1.37500]
Security Device Support [Enable]
TPM Device Selection [Discrete TPM]
Erase fTPM NV for factory reset [Enabled]
PSS Support [Auto]
NX Mode [Enabled]
SVM Mode [Enabled]
PT XHCI GEN1 [Auto]
PT XHCI GEN2 [Auto]
PT USB Equalization4 [Auto]
PT USB Redriver [Auto]
PT PCIE PORT 0 [Auto]
PT PCIE PORT 1 [Auto]
PT PCIE PORT 2 [Auto]
PT PCIE PORT 3 [Auto]
PT PCIE PORT 4 [Auto]
PT PCIE PORT 5 [Auto]
PT PCIE PORT 6 [Auto]
PT PCIE PORT 7 [Auto]
PT SATA PORT 0 Enable [Auto]
PT SATA PORT 1 Enable [Auto]
PT SATA PORT 2 Enable [Auto]
PT SATA PORT 3 Enable [Auto]
PT SATA PORT 4 Enable [Auto]
PT SATA PORT 5 Enable [Auto]
PT SATA PORT 6 Enable [Auto]
PT SATA PORT 7 Enable [Auto]
Onboard PCIE LAN PXE ROM [Enabled]
AMD CRB EHCI Debug port switch [Disabled]
Onboard LED [Enabled]
Hyper kit Mode [Disabled]
SATA Port Enable [Enabled]
SATA Mode [AHCI]
SMART Self Test [Enabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
ErP Ready [Disabled]
Restore On AC Power Loss [Power Off]
Power On By PCI-E/PCI [Disabled]
Power On By RTC [Disabled]
Super I/O Clock Skew [Auto]
HD Audio Controller [Enabled]
PCIEX4_3 Bandwidth [Auto]
PCIEX16_1 Mode [Auto]
PCIEX8_2 Mode [Auto]
PCIEX4_3 Mode [Auto]
M.2 Link Mode [Auto]
SB Link Mode [Auto]
Asmedia USB 3.1 Controller [Enabled]
When system is in working state [On]
In sleep, hibernate and soft off states [On]
Intel LAN Controller [Enabled]
Intel LAN OPROM [Disabled]
USB Type C Power Switch for USB3.1_E1 [Auto]
USB Type C Power Switch for USB3.1_EC2 [Auto]
Network Stack [Disabled]
Debug Port Table [Disabled]
Debug Port Table 2 [Disabled]
Device [INTEL SSDSC2CW120A3]
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
USB Mass Storage Driver Support [Enabled]
Generic Ultra HS-SD/MMC [Auto]
USB3.1_E1 [Auto]
USB3_1 [Enabled]
USB3_2 [Enabled]
USB3_3 [Enabled]
USB3_4 [Enabled]
USB3_5 [Auto]
USB3_6 [Auto]
USB3_7 [Auto]
USB3_8 [Auto]
USB3_9 [Auto]
USB3_10 [Auto]
USB2_11 [Auto]
USB2_12 [Auto]
USB2_13 [Auto]
USB2_14 [Auto]
USB_15 [Auto]
USB_16 [Auto]
CPU Temperature [Monitor]
MotherBoard Temperature [Monitor]
VRM Temperature [Monitor]
PCH Temperature [Monitor]
T_Sensor1 Temperature [Monitor]
CPU Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
Chassis Fan 3 Speed [Monitor]
W_PUMP+ Speed [Monitor]
CPU Optional Fan Speed [Monitor]
AIO_PUMP Speed [Monitor]
W_FLOW Speed [Monitor]
W_IN Temperature [Monitor]
W_OUT Temperature [Monitor]
CPU Core Voltage [Monitor]
3.3V Voltage [Monitor]
5V Voltage [Monitor]
12V Voltage [Monitor]
CPU Q-Fan Control [Auto]
CPU Fan Smoothing Up/Down Time [0 sec]
CPU Fan Speed Lower Limit [200 RPM]
CPU Fan Profile [Standard]
W_PUMP+ Control [Disabled]
Chassis Fan 1 Q-Fan Control [Auto]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Smoothing Up/Down Time [0 sec]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 1 Profile [Standard]
Chassis Fan 2 Q-Fan Control [Auto]
Chassis Fan 2 Q-Fan Source [CPU]
Chassis Fan 2 Smoothing Up/Down Time [0 sec]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 2 Profile [Standard]
Chassis Fan 3 Q-Fan Control [Auto]
Chassis Fan 3 Q-Fan Source [CPU]
Chassis Fan 3 Smoothing Up/Down Time [0 sec]
Chassis Fan 3 Speed Low Limit [200 RPM]
Chassis Fan 3 Profile [Standard]
OnChip SATA Channel [Auto]
OnChip SATA Type [AHCI]
USB3_1 [Enabled]
USB3_2 [Enabled]
USB3_3 [Enabled]
USB3_4 [Enabled]
IR Config [RX & TX0 Only]
SdForce18 Enable [Disabled]
SD Mode configuration [AMDA]
Uart 0 Enable [Enabled]
Uart 1 Enable [Enabled]
I2C 0 Enable [Enabled]
I2C 1 Enable [Enabled]
I2C 2 Enable [Disabled]
I2C 3 Enable [Disabled]
GPIO Devices Support [Auto]
ESATA Port On Port 0 [Auto]
ESATA Port On Port 1 [Auto]
ESATA Port On Port 2 [Auto]
ESATA Port On Port 3 [Auto]
ESATA Port On Port 4 [Auto]
ESATA Port On Port 5 [Auto]
ESATA Port On Port 6 [Auto]
ESATA Port On Port 7 [Auto]
SATA Power On Port 0 [Auto]
SATA Power On Port 1 [Auto]
SATA Power On Port 2 [Auto]
SATA Power On Port 3 [Auto]
SATA Power On Port 4 [Auto]
SATA Power On Port 5 [Auto]
SATA Power On Port 6 [Auto]
SATA Power On Port 7 [Auto]
SATA Port 0 MODE [Auto]
SATA Port 1 MODE [Auto]
SATA Port 2 MODE [Auto]
SATA Port 3 MODE [Auto]
SATA Port 4 MODE [Auto]
SATA Port 5 MODE [Auto]
SATA Port 6 MODE [Auto]
SATA Port 7 MODE [Auto]
SATA Hot-Removable Support [Auto]
SATA 6 AHCI Support [Auto]
Int. Clk Differential Spread [Auto]
SATA MAXGEN2 CAP OPTION [Auto]
SATA CLK Mode Option [Auto]
Aggressive Link PM Capability [Auto]
Port Multiplier Capability [Auto]
SATA Ports Auto Clock Control [Auto]
SATA Partial State Capability [Auto]
SATA FIS Based Switching [Auto]
SATA Command Completion Coalescing Support [Auto]
SATA Slumber State Capability [Auto]
SATA MSI Capability Support [Auto]
SATA Target Support 8 Devices [Auto]
Generic Mode [Auto]
SATA AHCI Enclosure [Auto]
SATA SGPIO 0 [Auto]
SATA SGPIO 1 [Disabled]
SATA PHY PLL [Auto]
AC/DC Change Message Delivery [Disabled]
TimerTick Tracking [Auto]
Clock Interrupt Tag [Auto]
EHCI Traffic Handling [Disabled]
Fusion Message C Multi-Core [Disabled]
Fusion Message C State [Disabled]
SPI Read Mode [Auto]
SPI 100MHz Support [Auto]
SPI Normal Speed [Auto]
SPI Fast Read Speed [Auto]
SPI Burst Write [Auto]
I2C 0 D3 Support [Auto]
I2C 1 D3 Support [Auto]
I2C 2 D3 Support [Auto]
I2C 3 D3 Support [Auto]
I2C 4 D3 Support [Auto]
I2C 5 D3 Support [Auto]
UART 0 D3 Support [Auto]
UART 1 D3 Support [Auto]
UART 2 D3 Support [Auto]
UART 3 D3 Support [Auto]
SATA D3 Support [Auto]
EHCI D3 Support [Auto]
XHCI D3 Support [Auto]
SD D3 Support [Auto]
S0I3 [Auto]
Chipset Power Saving Features [Enabled]
SB Clock Spread Spectrum [Auto]
SB Clock Spread Spectrum Option [-0.375%]
HPET In SB [Auto]
MsiDis in HPET [Auto]
_OSC For PCI0 [Auto]
USB Phy Power Down [Auto]
PCIB_CLK_Stop Override [0]
USB MSI Option [Auto]
LPC MSI Option [Auto]
PCIBridge MSI Option [Auto]
AB MSI Option [Auto]
SB C1E Support [Auto]
SB Hardware Reduced Support [Auto]
GPP Serial Debug Bus Enable [Auto]
PSPP Policy [Auto]
Memory Clock [Auto]
Bank Interleaving [Enabled]
Channel Interleaving [Enabled]
Memory Clear [Disabled]
Fast Boot [Enabled]
Next Boot after AC Power Loss [Normal Boot]
Boot Logo Display [Auto]
POST Delay Time [3 sec]
Boot up NumLock State [Enabled]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Enabled]
Interrupt 19 Capture [Disabled]
Setup Mode [Advanced Mode]
Launch CSM [Enabled]
Boot Device Control [UEFI and Legacy OPROM]
Boot from Network Devices [Legacy only]
Boot from Storage Devices [Legacy only]
Boot from PCI-E Expansion Devices [Legacy only]
OS Type [Other OS]
Setup Animator [Disabled]
Load from Profile [2]
Profile Name [3.8Ghz3333Stbl]
Save to Profile [1]
CPU Core Voltage [Auto]
VDDSOC Voltage [Auto]
1.8V PLL Voltage [Auto]
BCLK Frequency [Auto]
CPU Ratio [Auto]
Bus Interface [PCIEX16/X8_1]


----------



## Arengeta

Quote:


> Originally Posted by *floatboth*
> 
> Nah that shows errors very quickly
> 
> 
> 
> 
> 
> 
> 
> Safe with the SC_L timings at 4 though, is overnight stable!
> 
> 
> 
> But the performance drop (from t*SC_L 3) is very significant&#8230;


You need as low latency as possible, ram speeds do not matter much.


----------



## kmac20

That's pretty inaccurate if you've looked at any series of benchmarks which show that raising ram speed is far more important to lowering timings slightly.


----------



## kazablanka

I think 3200mhz with low sub-timings is better than 3333mhz with fast timings from calculator for me.


----------



## Trender07

I can even boot with 3466 MHz but its unstable asf, only stable is 3200 mhz :s and yeah ive used the ryzen calculatoir


----------



## datspike

Quote:


> Originally Posted by *Trender07*
> 
> I can even boot with 3466 MHz but its unstable asf, only stable is 3200 mhz :s and yeah ive used the ryzen calculatoir


Try this.
I have the same memory modules, tCWL = 14 with main timings = 15 is the way to get those sticks to 3466.
Stable for me at 1.4v VDRAM / 0.6996v VTT


Spoiler: Warning: Spoiler!


----------



## abso

Quote:


> Originally Posted by *ph1ber*
> 
> So pretty happy this morning. Woke up to seeing that MemTest64 had run it's 8 hours with no errors. Finally I got something stable to work from
> 
> 
> 
> 
> 
> 
> 
> I got the timings from another user i C6H thread and they worked out really well for me. Posting bios settings as well. Hope this helps someone
> 
> 
> 
> 
> 
> 
> 
> 
> Asus Crosshair 6 Hero Bios 3101.


Is Memtest64 a better tool to test ram than HCI Memtest?


----------



## ssateneth

Quote:


> Originally Posted by *abso*
> 
> Is Memtest64 a better tool to test ram than HCI Memtest?


Everyone has their own favorite. Some like HCI, some like Memtest64, some like GSAT, and I like the UEFI bootable version of Memtest86 with test #7 on loop.


----------



## 12Cores

I got my GSKILL(F4-3200C16D-16GVK) timings down to [email protected], they will not OC beyond 3200mhz and are not stable at CL14. I am not seeing any tangible improvements at 4k with these lower timings but it appears to stable will let it ride for now.


----------



## Trender07

Quote:


> Originally Posted by *datspike*
> 
> Try this.
> I have the same memory modules, tCWL = 14 with main timings = 15 is the way to get those sticks to 3466.
> Stable for me at 1.4v VDRAM / 0.6996v VTT
> 
> 
> Spoiler: Warning: Spoiler!


For some reason when I set tcl to 15 It changes to 16 so It actually reads 16-15-15-15-32 etc everything Ive set its just like yours
and what ProcODT are you using? Im using 48 Ohms but it still isnt Stable It crashes


----------



## datspike

Quote:


> Originally Posted by *Trender07*
> 
> For some reason when I set tcl to 15 It changes to 16 so It actually reads 16-15-15-15-32 etc everything Ive set its just like yours
> and what ProcODT are you using? Im using 48 Ohms but it still isnt Stable It crashes


Disable Geardown Mode and set 1 rank mode, I'm also using 53Ohm ProcODT


----------



## Trender07

Quote:


> Originally Posted by *datspike*
> 
> Disable Geardown Mode and set 1 rank mode, I'm also using 53Ohm ProcODT


Okay just disabled geardown and set 53 ohms, btw how do you set the 1 rank mode? This is my rtc


It still isnt stable (btw my motherboard also have a 3rd trfc, I set that one on auto as rtc only shows 2)


----------



## datspike

Quote:


> Originally Posted by *Trender07*
> 
> Okay just disabled geardown and set 53 ohms, btw how do you set the 1 rank mode?


Well, than your IMC is just worse than mine in terms of silicone quality








I cant give you more advises..


----------



## Nighthog

Quote:


> Originally Posted by *Trender07*
> 
> Okay just disabled geardown and set 53 ohms, btw how do you set the 1 rank mode? This is my rtc
> 
> 
> It still isnt stable (btw my motherboard also have a 3rd trfc, I set that one on auto as rtc only shows 2)


I can suggest try tCKE higher than 1 and also try tRTP to 10. Depending on memory kits/motherboard etc all don't like those too low/tight.
tWR can also be problematic for some.
My motherboard refuses to boot with tCKE @ 1, I can get 2 to work but need excessive voltage. ~1.350V I can use it @ 4 for my particular kit/mobo combo. [email protected] needs almost 1.500V.(1.470-1.490) to be stable with some other suitable low timings.

You have to try ALL the relevant Ohms. 40. 53. 60. 68. 80... It's a combo of motherboard/RAM/CPU which one is the one to use. I've noted BIOS version can alter which one you need as well. Some Bios options can alter what you may need to run for your particular kit as well.


----------



## Trender07

Quote:


> Originally Posted by *datspike*
> 
> Well, than your IMC is just worse than mine in terms of silicone quality
> 
> 
> 
> 
> 
> 
> 
> 
> I cant give you more advises..


It still helped, thanks for your input anyways
Quote:


> Originally Posted by *Nighthog*
> 
> I can suggest try tCKE higher than 1 and also try tRTP to 10. Depending on memory kits/motherboard etc all don't like those too low/tight.
> tWR can also be problematic for some.
> My motherboard refuses to boot with tCKE @ 1, I can get 2 to work but need excessive voltage. ~1.350V I can use it @ 4 for my particular kit/mobo combo. [email protected] needs almost 1.500V.(1.470-1.490) to be stable with some other suitable low timings.
> 
> You have to try ALL the relevant Ohms. 40. 53. 60. 68. 80... It's a combo of motherboard/RAM/CPU which one is the one to use. I've noted BIOS version can alter which one you need as well. Some Bios options can alter what you may need to run for your particular kit as well.


Yeah agreed on the Ohms, its kinda random, and I think it changes with speed, in like I know for sure @3200 the best is 43 Ohms, but at higher speed (in like 3333 MHz-3466Mhz) looks like it likes more 48 Ohms
Okay then Ill try tCKE @ 3 and 1.40V and tRTP 10

EDIT:
Not even at [email protected] and 1.5V mine just can't 3466 x) hci fails under a minute, I think Ill stick with 3333


----------



## ph1ber

Quote:


> Originally Posted by *abso*
> 
> Is Memtest64 a better tool to test ram than HCI Memtest?


Well it's been the one that has consistently given me errors the fastest so I have stuck to it but I'm a beginner at this pretty much. I'm sure there are people here with vastly more experience that can tell you more


----------



## Arengeta

Quote:


> Originally Posted by *Trender07*
> 
> It still helped, thanks for your input anyways
> Yeah agreed on the Ohms, its kinda random, and I think it changes with speed, in like I know for sure @3200 the best is 43 Ohms, but at higher speed (in like 3333 MHz-3466Mhz) looks like it likes more 48 Ohms
> Okay then Ill try tCKE @ 3 and 1.40V and tRTP 10
> 
> EDIT:
> Not even at [email protected] and 1.5V mine just can't 3466 x) hci fails under a minute, I think Ill stick with 3333


Try RDRDSCL/WRWRSCL timings at 4 instead of 2. Helped stability a lot above.

About the speeds: with higher ram speed you get lower latency even if you're running auto timings, that's why in every benchmark higher speed ram wins. But as you have seen probably aswell low timing 3200mhz (CL14) gets same performance as 3466mhz with regular timings.

Memory Read/Write/Copy do not matter at all, ask anyone who's using intel and they have significantly lower speeds and much lower latency.


----------



## abso

Is there any risk for the hardware experimenting with those ram values ( ohm etc.)?


----------



## Silent Scone

Quote:


> Originally Posted by *abso*
> 
> Is there any risk for the hardware experimenting with those ram values ( ohm etc.)?


None.


----------



## ph1ber

Turns out 2x8 hours stresstesting in MemTest64 and prime95 pales in comparison to 10 minutes of Overwatch. Constant crashes with 3466 memory which has been stable for everything else. Dialed it down to my previous 3333MHz cl14 and all has been good ever since..


----------



## The Sandman

Quote:


> Originally Posted by *ph1ber*
> 
> Turns out 2x8 hours stresstesting in MemTest64 and prime95 pales in comparison to 10 minutes of Overwatch. Constant crashes with 3466 memory which has been stable for everything else. Dialed it down to my previous 3333MHz cl14 and all has been good ever since..


Running 3466MHz may very well require a slight Vcore/SOC adjustment if you're not aware.
I run my Flare-X (B-Die SS) at 3466MHz 14-13-13-26-44-1T @1.42v Dram Voltage. Your sig states you're running Dram voltage at 1.374v, seems low to me if this is what you're attempting 3466MHz with.

Is your current OC w/3333MHz capable of passing at least 10 passes of IBT AVX set to either Very High or preferably "Custom" and 13320MBs?
HCI MemTest, OCCT AVX, Y-Cruncher, Realbench should all be no issue if you're close to stable.
Hopefully these are what you were referring to when you mentioned "everything else".


----------



## ph1ber

Quote:


> Originally Posted by *The Sandman*
> 
> Running 3466MHz may very well require a slight Vcore/SOC adjustment if you're not aware.
> I run my Flare-X (B-Die SS) at 3466MHz 14-13-13-26-44-1T @1.42v Dram Voltage. Your sig states you're running Dram voltage at 1.374v, seems low to me if this is what you're attempting 3466MHz with.
> 
> Is your current OC w/3333MHz capable of passing at least 10 passes of IBT AVX set to either Very High or preferably "Custom" and 13320MBs?
> HCI MemTest, OCCT AVX, Y-Cruncher, Realbench should all be no issue if you're close to stable.
> Hopefully these are what you were referring to when you mentioned "everything else".


What's in my signature is what I'm running right now. In the link in my sig to bios settings is what I was running with 3466MHz. I was running way looser timings than you are and with really good ram and it seemed to handle stress tests just fine just not that game. I'm not prepared to spend days on end stress testing every single setting..again. If 3333Mhz turn out to cause issues I'll look into it further I guess. I've run a lot of tests on these settings as well as the ones for 3466 but feel like taking a break from it now and just use my computer


----------



## harrysun

Quote:


> Originally Posted by *ph1ber*
> 
> Turns out 2x8 hours stresstesting in MemTest64 and prime95 pales in comparison to 10 minutes of Overwatch. Constant crashes with 3466 memory which has been stable for everything else. Dialed it down to my previous 3333MHz cl14 and all has been good ever since..


Futuremark and Unigine where for me good indicators for freezes because also the GPU is put in consideration.


----------



## xethi

Quote:


> Originally Posted by *ph1ber*
> 
> What's in my signature is what I'm running right now. In the link in my sig to bios settings is what I was running with 3466MHz. I was running way looser timings than you are and with really good ram and it seemed to handle stress tests just fine just not that game. I'm not prepared to spend days on end stress testing every single setting..again. If 3333Mhz turn out to cause issues I'll look into it further I guess. I've run a lot of tests on these settings as well as the ones for 3466 but feel like taking a break from it now and just use my computer


have same issue now and have been running 3466 for a few months now but whem ambient temperature droped overwatch started to crash with these settings. i tried to pinpoint the problem as it was mainly vga driver crashing but it turned out to be ram at 3466 as i tried all settings 1by1 stock cpu high ram speed crash and high cpu core and ram at 3200 very low timings crash stoped even tho i have multiple hci and stress test all a minimum of 500% and multiple times.

i have read that imc can be picky with lower temp but only crashed in overwatch even when i tried to warm it up.

see link for latest hci test and still crashed, was at 3900core at 1.37v. soc 1.1v .dram 1.39in ,bios overshooting to 1.408 1.416v.

2512171733memtest800.JPG 546k .JPG file
.

and also iam getting a huge difference in vcore requirement 3200 ram cpu 3800 need 1.2v core but with 3466 need 1.28v. now at 3200ram 3.95cpu core at 1.35vcore in bios settings. with 3466 ram no vcore below 1.4v can boot 3925.


----------



## abso

Your whole System is crashing while playing Overwatch or just the game?


----------



## xethi

Quote:


> Originally Posted by *abso*
> 
> Your whole System is crashing while playing Overwatch or just the game?


the thing is i had many different types of crashes most where client crash like if you alt f4 out of a game. some where nvdlllect bsod some where irql not less of equal but those were the least. it was everytime a different kind of crash it took me a lot of time to pintpoint the source.

tried first vga in the differnet pcie slot did ddu many times tried different drivers also reinstalled window 10 as had some tweaks like superfect changed in registry too and read that overwatch prefers it ect ect ect . the list goes on







and only in overwatch btw all those.


----------



## ph1ber

Quote:


> Originally Posted by *abso*
> 
> Your whole System is crashing while playing Overwatch or just the game?


For me it was always game client only.


----------



## Leito360

I've been able to install Ubuntu on Windows 10, but how do I install the stressapp? what commands should I input? I'm very lost here!!


----------



## kaseki

Quote:


> Originally Posted by *Leito360*
> 
> I've been able to install Ubuntu on Windows 10, but how do I install the stressapp? what commands should I input? I'm very lost here!!


OK, first go to https://github.com/stressapptest/stressapptest

Second, read the bit about installation and use

Code:



Code:


sudo apt-get install stressapptest

for Ubuntu using the terminal application.

Third, figure out where it got installed among your directories/folders and move your Linux terminal's directory location to that directory (this is similar to using microsoft's command window). I don't have access to my Ryzen PC at the moment, and don't remember where it was. Of course, you could make a link from the actual executable to the desktop for ease of use. That is beyond the scope of this comment.

Fourth, read the bit about usage, and choose your parameters. I used 3600 seconds for typical runs, 16 threads, an amount of memory near the total available, but leaving a few hundred MB for the OS, and the -W switch also. (My exact command line seems to be lost in my pile of notes created during my tuning exercise that ended in September due to other priorities.)

Fifth, type the command string and enter. Be sure to use the ./ if you are in the directory with the executable or have a proper path. You should see a starting message and then a string of results repeated as time progresses. You may want to extend the vertical extent of the window to gain perspective.

Note that I run Mint (derived from Ubuntu) without the complication of Windows, so the exact behavior in your case is not something I would have observed.

kas


----------



## kaseki

The "origin" for promoting GSAT use in the C6H thread seems to be: https://rog.asus.com/forum/showthread.php?73665-Our-preferred-memory-stress-test as linked by @gupsterg. The command string there is the one I believe I used.


----------



## Dopamin3

Got my 2 x 16GB kit stable on Asrock X370 Taichi.

[email protected] 1.1v---BIOS 3.20a---HCI---436%---F4-3200C14D-32GTZR

Pictures: https://photos.app.goo.gl/P7z24gbHNANXkubt2


----------



## Keith Myers

I use

Code:



Code:


stressapptest -W -M 14480 -s 3600

That tests 14480MB across 16 cores for 1 hour.


----------



## sealancer

Hi guys,

I recently RMA'ed my RAM (f4-3000c15d-16gtzb) and got a new kit. One of the stick failed in the earlier kit hence had to return it. The old kit ran fine with agesa update, was able to hit 2933 by loosening the timings to 18.

The new kit only runs at 2666 but not more than that. I tried to loosen the timings but the system ends up boot looping







. It terminates with 3E and starts all over again. Any Idea whats going on?

My system spec

Ryzen 1700
x370 taichi
RAM : 16GB (f4-3000c15d-16gtzb, hynix M die).
XMP setting:
2666 ==> 16-16-16-16-35. (1.368v ram, 1.1 soc)
3002/2933. ==> 18-18-18-38 (1.38v ram, 1.1 soc)




PS: I know RAM is not on QVL but GSkill said they tested the RAM and it works . They wont even exchange for compatible ram or give a refund







. Given the sky high RAM prices, I have postponed buying a QVL kit.


----------



## Atomfix

Quote:


> Originally Posted by *sealancer*
> 
> Hi guys,
> 
> I recently RMA'ed my RAM (f4-3000c15d-16gtzb) and got a new kit. One of the stick failed in the earlier kit hence had to return it. The old kit ran fine with agesa update, was able to hit 2933 by loosening the timings to 18.
> 
> The new kit only runs at 2666 but not more than that. I tried to loosen the timings but the system ends up boot looping
> 
> 
> 
> 
> 
> 
> 
> . It terminates with 3E and starts all over again. Any Idea whats going on?
> 
> My system spec
> 
> Ryzen 1700
> x370 taichi
> RAM : 16GB (f4-3000c15d-16gtzb, hynix M die).
> XMP setting:
> 2666 ==> 16-16-16-16-35. (1.368v ram, 1.1 soc)
> 3002/2933. ==> 18-18-18-38 (1.38v ram, 1.1 soc)
> 
> PS: I know RAM is not on QVL but GSkill said they tested the RAM and it works . They wont even exchange for compatible ram or give a refund
> 
> 
> 
> 
> 
> 
> 
> . Given the sky high RAM prices, I have postponed buying a QVL kit.


I have the exact same kit as yourself. Only yesterday I've found someone else on here who runs the same kit as myself also and copied his settings for 3200MHz OC 14-15-15-15-30 @1.42V 1T. My SOC Voltage is also 1.15V Mine also is Hynix M-Die

Give these settings a blast and see how you get on. Can't promise they will work as I'm using a different motherboard to yourself so it may vary. I have a Gigabyte Gaming K5 AX370. The person I copied it from had a Gaming 3.... I think.

https://valid.x86.fr/sskcnd CPUZ Validation


----------



## mth21

Does this below test is enough to ensure my cpu and memory stability ?
1. Google Stress app : 1 Hour
2. HCI Memtest : 500%
3. Memtest86 10/12 passes, i forgot
4. Prime 95, Small FFT : 5 hours
5. Prime 95, Blend test 14500 MB Memory (my memory is 16GB) : 12 hours

Thank you


----------



## harrysun

@mth21, every body here defines "enought" different. Here is my test suite for 32GB of RAM:

AIDA64 6-8h: CPU & RAM
BOINC 6-8h: CPU
Google stressapptest (GSAT) 6h: CPU & RAM
IntelBurnTest v2.54 IBT AVX 30 run Level Maximum: CPU & RAM
OCCT Perestroïka 4h: CPU
HCI Memtest Deluxe (at least 200% for 32GB; better 1000% needs 14-16h): RAM
TechPowerup MemTest64 8-12h: RAM
y-cruncher 24h: CPU
Prime95 (Howto use for stress testing) 10-24h:
RAM/IMC test (Voltage/Resistance):

CPU/L1/L2/L3 test:


ASUS RealBench 8h: general stability
Futuremark 3DMark benchmark: general stability
Unigine Superposition benchmark: general stability
You can also find more details about my test progress and procedure/test document following the link in the signature.


----------



## sealancer

Quote:


> Originally Posted by *Atomfix*
> 
> I have the exact same kit as yourself. Only yesterday I've found someone else on here who runs the same kit as myself also and copied his settings for 3200MHz OC 14-15-15-15-30 @1.42V 1T. My SOC Voltage is also 1.15V Mine also is Hynix M-Die
> 
> Give these settings a blast and see how you get on. Can't promise they will work as I'm using a different motherboard to yourself so it may vary. I have a Gigabyte Gaming K5 AX370. The person I copied it from had a Gaming 3.... I think.
> 
> https://valid.x86.fr/sskcnd CPUZ Validation


Thx , let me try it out.

Dont see any issue upping the SOC voltage to 1.15v but increasing the DRAM voltage to 1.42v looks a bit hard. Given the official RAM speed of 3000 it should not require more than 1.37-1.39v.
More over the RAM does not have a thermal sensor as such would not have any idea if if it is running under acceptable temperature or not







.


----------



## Atomfix

Quote:


> Originally Posted by *sealancer*
> 
> Thx , let me try it out.
> 
> Dont see any issue upping the SOC voltage to 1.15v but increasing the DRAM voltage to 1.42v looks a bit hard. Given the official RAM speed of 3000 it should not require more than 1.37-1.39v.
> More over the RAM does not have a thermal sensor as such would not have any idea if if it is running under acceptable temperature or not
> 
> 
> 
> 
> 
> 
> 
> .


Updated timings here. Last ones I posted were unstable. The new timings give a big performance increase in Aida64







Bare in mind, I'm still testing out the new timings so you may have to loosen one or two things yourself if it's unstable.

And don't worry about the RAM voltage so much. You've bought a high-end G.Skill Trident Z kit that comes with a lifetime warranty. Make use of it







I'd like to keep mine below 1.45V personally, I've felt the RAM sticks whilst stressing under Prime95 and still feel stone cold to the touch. Mostly due to the fan mounted to the top of the case blowing down on them.

I've also got BankGroup Swap enabled. Not sure why it says Disabled on the screenshot. And about the voltages on why they've soo high, It's Hynix M-Die, so not as gracious as Samsung B-Die. Plus it could all be down to how strong your IMC Controller is.


----------



## binder87

Quote:


> Originally Posted by *Atomfix*
> 
> Updated timings here. Last ones I posted were unstable. The new timings give a big performance increase in Aida64
> 
> 
> 
> 
> 
> 
> 
> Bare in mind, I'm still testing out the new timings so you may have to loosen one or two things yourself if it's unstable.
> 
> And don't worry about the RAM voltage so much. You've bought a high-end G.Skill Trident Z kit that comes with a lifetime warranty. Make use of it
> 
> 
> 
> 
> 
> 
> 
> I'd like to keep mine below 1.45V personally, I've felt the RAM sticks whilst stressing under Prime95 and still feel stone cold to the touch. Mostly due to the fan mounted to the top of the case blowing down on them.
> 
> I've also got BankGroup Swap enabled. Not sure why it says Disabled on the screenshot. And about the voltages on why they've soo high, It's Hynix M-Die, so not as gracious as Samsung B-Die. Plus it could all be down to how strong your IMC Controller is.


Glad to see you're listening









How's stability now with the looser tras?

And Also you're right, there's really no issues with running a high end ddr4 kit @ up to 1.45 24/7....
Hell, I have a crucial kit with no heatsink at all which I run @1.35 24/7 when its rated @1.2 ...
I mounted the original wraith spire cooler fan to blow on them, but not directly , its around 10-15 cm away.
I can also confirm that I ran them at 1.4 before, and touched them right after stressing them, and they really weren't hot at all. Slightly slightly warm....this was before mounting the fan, and they have no heatsink!
1,45v is really not an issue.


----------



## binder87

BTW, for those who strictly game and don't do any productivity work on their chips, if you disable SMT (which currently at least, benefits most games) you can push the ram slightly more...that was at least the case with my testing, and obviously it makes sense also. So I don't know if it was discussed here on this thread, but for whoever only game on his ryzen and wants to push his memory slightly more, disabling SMT helps. Keep in mind though, that Of course, as you disable threads , don't expect to get a higher cpu benchmarks scores...


----------



## gupsterg

Quote:


> Originally Posted by *Iceman1985*
> 
> Is memory hole dependant on number of sticks or ram-size? Because i have not experienced this memory hole with 2x8gb.. how do we know if we are encountering a memory hole? And does the memory-hole move with 4x8gb? That would explain alot if it did...


The Stilt has stated as CPU/DRAM specific, link.

Using same board/RAM but differing CPU I have seen differing "memory hole", unfortunately not got any other DDR4 to try, not likely with the crazed pricing as well







.
Quote:


> Originally Posted by *Bartouille*
> 
> memtestlauncher.zip 32k .zip file
> 
> 
> memtestlaunchersrc.zip 9k .zip file
> 
> 
> Made a program to automatically start the free version of memtest. Feel free to use it.


Sweet







, there is one in OP of ASUS ZE thread and IIRC Ryzen Essential, if you don't mind I will add link to this post in both those threads OP?
Quote:


> Originally Posted by *kaseki*
> 
> The "origin" for promoting GSAT use in the C6H thread seems to be: https://rog.asus.com/forum/showthread.php?73665-Our-preferred-memory-stress-test as linked by @gupsterg. The command string there is the one I believe I used.


GSAT is part of test suite for profile testing, as is HCI Memtest and other apps. One time did think GSAT was better than HCI, but then was proved wrong by my own kit (besides advise from members







). So my opinion is if we're after best stability ran as many tests as possible. In my opinion no one program is capable of all testing.


----------



## Bartouille

Quote:


> Originally Posted by *gupsterg*
> 
> Sweet
> 
> 
> 
> 
> 
> 
> 
> , there is one in OP of ASUS ZE thread and IIRC Ryzen Essential, if you don't mind I will add link to this post in both those threads OP?


Yea that would be cool.







I got so annoyed to have to start all those instances and place them by hand!


----------



## darknezx

I thought I can contribute to this thread after getting help from this forum.

[email protected] 1.125v----BIOS 3401 (Asus Strix X370-F Gaming)---HCI(700% - sorry I forgot to do a screenshot) and 11 passes of memtest86---F4-3200C16-8GTZB


----------



## xethi

Quote:


> Originally Posted by *ph1ber*
> 
> For me it was always game client only.


i was able to fix my crashes by increasing ram voltage a bit and relaxed some timings . did you find root of your problem?anything below 1.395 in bios on ram at 3466 client crash reapeared and was able to repeat it to confirm even with the relaxed timing version.


----------



## djayarr808

[email protected] 1.2v---BIOS 1701---HCI---200%---CMK32GX4M4B3200C16W

Sorry if I'm doing something obviously and obliviously wrong.

I dropped the ball and ordered non B-Die Corsair LPX 32GB 3200mHz RAM. Mostly did this to test stability at what I, and most others, consider average or below average settings. I'm happy with the speed and timings, but just wanted to be part of the party









Also, I just let Pro do its thing and then came back later and realized it was running an interesting 10 instances and varying amounts of memories (400+% on one of them; I assume that means its a smaller amount?).

Core Voltage is manually set to 1.30V on my C6H, LLC at AUTO (random problems at other levels), SOC at 1.2V, and DRAM at 1.33V. As you can see, my voltage sits rather low, and is the same when doing Cinebench, AIDA, and Prime95. Is this Vdroop? No amount of tinkering with LLC saw real change in voltages. Nothing ever reached my manually set VCore (VID gets up to it, but CPU-Z and the other two Vcore readings in HW-Info don't get close). Had it at 3.9 @ 1.4 and it sat at low 1.3s for the most part. Should I be worried about it if it's stable for hours of stress testing?

Anyway, this is a RAM thread, so here are my test screens:


----------



## bl1tzk1213g

What timings can loosen to help stability without losing much performance?


----------



## Silent Scone

Quote:


> Originally Posted by *bl1tzk1213g*
> 
> What timings can loosen to help stability without losing much performance?


Setting tRCD one clock higher than tRP can often help if close to stable. You won't lose much performance, as with most things memory, the gains are never huge.


----------



## BLUuuE

Quote:


> Originally Posted by *Milestonegio*
> 
> [email protected]-SOC 1v---BIOS 3401---HCI---1500%---416G3000HC16CDC01
> (1600 + B350 Strix + 2x8GB T-Force 3000MHz C16-18-18-38 Dual Rank Samsung S-Die, procODT=60, CADs: 20-20-30-30).
> 
> 
> It's just stupid but it's stable as you can see.
> 
> Some observations on S-Die:
> It can't run Clock/RD near 200 (Something around 196 is stable but at 200+ no post at all), RAS<34 and RC<49 at any voltage up to 1.6V.
> 
> Please explain why I get such high latency an AIDA64. On BIOS 1001 it was around 79 at C14-16-16-34 which is also too high from my point of view. Sadly, i can't get stable 3200/3333/3466 since i haven't VDDP_CLDO control.


Hey, do you have the link to your MemTest launcher? I can't seem to find v3.0 anywhere, only 2.5


----------



## binder87

I see all sorts of posts about too high of a dram voltage that causes instability.
I apologize, but it sounds weird...and I honestly don't think its true.
If its only based on anecdotal experience by people , I really think it shouldn't be followed as an advice. Memory errors are caused by a complex combination of things at times, and too high of a voltage really doesn't sounds like one...
Higher voltage as a rule of thumb causes stabilization of speeds, otherwise ln2 wasn't necessary. Only reason I could think of is overheating of the chip due to higher voltage, but that is so unlikely in the voltage range people are using for the ram, so I exclude it. So anyone has a scientific explanation as to why too much dram voltage can cause instability? I'm really skeptical with this.


----------



## Silent Scone

Quote:


> Originally Posted by *binder87*
> 
> I see all sorts of posts about too high of a dram voltage that causes instability.
> I apologize, but it sounds weird...and I honestly don't think its true.
> If its only based on anecdotal experience by people , I really think it shouldn't be followed as an advice. Memory errors are caused by a complex combination of things at times, and too high of a voltage really doesn't sounds like one...
> Higher voltage as a rule of thumb causes stabilization of speeds, otherwise ln2 wasn't necessary. Only reason I could think of is overheating of the chip due to higher voltage, but that is so unlikely in the voltage range people are using for the ram, so I exclude it. So anyone has a scientific explanation as to why too much dram voltage can cause instability? I'm really skeptical with this.


There is a lot of pseudosciences posted, that much is true. However, this isn't really one of them. This is entirely possible and comes down a multitude of reasons and 'alignment' issues at the electrical level. [email protected] posted a breakdown that may help with understanding these a few years ago. The same rules still ring true now. https://rog.asus.com/forum/showthread.php?44467-Overclocking-Tips-Beginner-and-Advanced-Guide-to-Overclocking&country=&status=

The implications of which will obviously differ between the platform in question, and the DRAM IC being used. DRAM overclocking is a complex beast, to say the least.


----------



## Parser26

Quote:


> Originally Posted by *reptilee*
> 
> My Tomahawk Arctic is running @ 3066mhz with G.Skill 16GB (2x8GB), Ripjaws V, DDR4 3200MHz, CL16 (F4-3200C16D-16GVKB) :
> 
> - Dram voltage 1.4
> 
> - Soc 1.1
> 
> -Gearmode > disabled
> 
> -Trc 75
> 
> -ProcODT 60
> 
> -Disable memory try it!
> 
> Worth to try at least..


I have the same ram, tried those settings, couldnt boot









mobo: msi b350m mortar


----------



## mtrai

Quote:


> Originally Posted by *Atomfix*
> 
> I have the exact same kit as yourself. Only yesterday I've found someone else on here who runs the same kit as myself also and copied his settings for 3200MHz OC 14-15-15-15-30 @1.42V 1T. My SOC Voltage is also 1.15V Mine also is Hynix M-Die
> 
> Give these settings a blast and see how you get on. Can't promise they will work as I'm using a different motherboard to yourself so it may vary. I have a Gigabyte Gaming K5 AX370. The person I copied it from had a Gaming 3.... I think.
> 
> ]


Are you referring to me? I think I posted about my Dec 17 G.skill 2 x 8 klt at those timings with 1300=% HCI coverage. I was playing around again with some of the settings today but no luck in improving it. However I need to point out I have a few other settings through out the bios that I change.

I just updated this morning to the new beta bios and can squeeze a TAD bit more out of my ram at these settings. I everyone would like I can post all my settings, as a few of the ram are not main timing nor did I really post other bios settings that affect ram. The bios settings I posted are for the previous beta bios not the one released yesterday. THough I did apply the same settings to 3501 is that the right number? I will update my settings a bit later with the current bios build number.

NOTE I HAVE NOT STRESS TESTED THESE WITH THE NEW BETA BIOS ELMOR JUST released just the previous bios. All seems fine so far.




current_setting.txt 20k .txt file


----------



## mth21

Hi Guys,

Occasionally i can not pass GSAT test for 1 hour for unknow reason

but

Always pass HCI 2000% all day test

Im running on Strix B350F Bios 3401, Vengeance LPX 3000 Mhz (Currently 2933MHz 16-19-19-38 1.35v) , Ryzen 5 1600 3.8 Ghz 1,25v

My suspect is bios causing this issue, i was able to run stable with 16-17-17-35 in Bios 0902

Anyone have similar setup, please share your experience

Thank :thumb:you


----------



## sideeffect

Quote:


> Originally Posted by *mth21*
> 
> Im running on Strix B350F Bios 3401, Vengeance LPX 3000 Mhz (Currently 2933MHz 16-19-19-38 1.35v) , Ryzen 5 1600 3.8 Ghz 1,25v
> 
> My suspect is bios causing this issue, i was able to run stable with 16-17-17-35 in Bios 0902


I'm Running the Asus B350 TUF with BIOS 3401 but I updated to it immediately on purchase and haven't tested other BIOS versions.

I'm curious why did you need to raise the TRCD and TRP by 2 steps did the motherboard not post or errors? Also is it just TRCD that needed raising did you try TRP lower? I am wondering because I have to keep my TRCD high for stability and it is quite peculiar as the other timings all go very low. I am currently running 14-18-14-34 @2933 stable but something like 16-16-16-38 is unstable.

I haven't tested GSAT yet but I'll give it a go over the weekend.


----------



## harrysun

Note: As always, my current stable setup can be found in the signature!


Spoiler: Does memory speeds matter?




YT: Does Ryzen Really Need Fast Memory? Guide for Gamers
YT: Ryzen 7 EVEN FASTER - Low Latency RAM testing
Hitman Memory Benchmarking (Timings used for 3200LL & 3466LL)
AMD: Memory OC Showdown: Frequency vs. Memory Timings
AMD Ryzen 7 AGESA 1006 performance and DDR4 memory check - review - An introduction at a double data-rate
AMD Ryzen Memory Analysis: 20 Apps & 17 Games, up to 4K Review




Configuration for F4-3200C14D-32GTZ @3333MT/s CL14-14-14-28-44 1.5T BIOS 1701.

My previous configuration with F4-3200C14D-32GTZ @3200MT/s CL14-13-13-26-42 1T 1.35000V BIOS 1701 can be found here.

I'm using G.Skill Trident Z DIMM Kit 2x16GB (F4-3200C14D-32GTZ):

(Created with Thaiphoon Burner Freeware Version Download)

AMD Ryzen R7 1800X, Stepping 1 Revision ZP-B1
CPU batch: UA 1734SUS (CPU exchanged since my last announcement for F4-3200C14D-32GTZ @3200MT/s CL14-13-13-26-42 1T 1.35000V)
ASUS ROG CROSSHAIR VI HERO
Motherboard Slots: DIMM_A2, DIMM_B2

BIOS Version: 1701 x64 AGESA 1.0.0.6b
Build Date: 09/22/2017
EC1 Version: MBEC-AM4-0311
EC2 Version: RGE2-AM4-0106



Spoiler: Toolchain used for testing CPU & RAM stability



Test protocol used to find stable settings can be downloaded here (Google Docs).


Spoiler: For all of you who want to see how find the right settings starts



Searching for the right settings is a quick and funny task, NOT. Here is my paper work before continue with Google Docs document: 



AIDA64 6-8h: CPU & RAM
BOINC 6-8h: CPU
Google stressapptest (GSAT) 6h: CPU & RAM
IntelBurnTest v2.54 IBT AVX 30 run Level Maximum: CPU & RAM
OCCT Perestroïka 4h: CPU
HCI Memtest Deluxe (at least 200% for 32GB; better 1000% needs 14-16h): RAM
TechPowerup MemTest64 8-12h: RAM
y-cruncher 24h: CPU
Prime95 (Howto use for stress testing) 10-24h:
RAM/IMC test (Voltage/Resistance):

CPU/L1/L2/L3 test:


ASUS RealBench 8h: general stability
Futuremark 3DMark benchmark: general stability
Unigine Superposition benchmark: general stability

*I have to be careful with the RAM/DIMM temperature:*
Quote:


> Originally Posted by *Esenel*
> 
> Quote:
> 
> 
> 
> Originally Posted by *1usmus*
> 
> *I shot a jitter phenomenon on video. When the 52 degree memory module reaches the platform, errors appear. This video can be a huge scandal.
> 
> https://youtu.be/nrVbyg4Vstg*
> 
> 
> 
> For me it looks exactly the same.
> It is a reproducible phenomenon for me at 3466 Mhz CL14. At first I thought it was just my RAM not being capable of the OC, until I realized the errors just begin when the RAM is at 52.X°C.
> Then I forced my fans to 100% during HCI Memtest and I passed the 400% without any error at ~47°C.
Click to expand...

 
*) T_Sensor1 = Ambient temperature in the case
    



*How stable is this setup:*


Spoiler: In a 30h run of Prime95 Blend 2048k-4096k one worker failed after 26h



 
*) T_Sensor1 = Ambient temperature in the case



Overview about settings F4-3200C14D-32GTZ @3333MT/s CL14-14-14-28-44 1.5T 1.41500V BIOS 1701 x64 AGESA 1.0.0.6b:

Advanced \ AMD CBS \ NBIO Common Options
CLDO_VDDP Control = 810


Advanced \ AMD CBS \ UMC Common Options \ DRAM Memory Mapping
BankGroupSwap = Auto (results automaticaly in Enabled)
BankGroupSwapAlt = Auto (results automaticaly in Disabled)

Extreme Tweaker
CPU SOC Voltage = Offset Mode
VDDSOC Offset Mode Sign = - (minus)
VDDSOC Voltage Override = 0.10625

DRAM Voltage = 1.41500

Extreme Tweaker \ DRAM Timing Control
DRAM ... = 14-14-14-14-28-44-5-8-30-4-12-10-Auto(0)-2-2-312-Auto(192)-Auto(132)-14-8-7-3-1-7-7-1-5-5-1
Cmd2T = 1T
Gear Down Mode = Enabled
_Power Down Enabled = Auto (Auto = Enabled; Default)_ (I can not measure any change in latency with Power Down Enabled = Disabled)
_Resistance:_
ProcODT_SM = 60.0 ohm
RttNom = RZQ/5
RttWr = RZQ/3
RttPark = RZQ/1
MemCadBus ClkDrvStren_SM = 30.0 Ohm
MemCadBus AddrCmdDrvStren_SM = 30.0 Ohm
MemCadBus CsOdtDrvStren_SM = 60.0 Ohm
MemCadBus CkeDrvStren_SM = 60.0 Ohm

Extreme Tweaker \ Tweaker's Paradise
VTTDDR Voltage = 0.70620
VDDP Voltage = _Auto_
VDDP Standby Voltage = _Auto_

Extreme Tweaker \ External Digi+ Power Control
DRAM VBoot Voltage = 1.41500

    

*Setup:*

Setting file:

harrysun41_3600_3333CL14_setting.txt 20k .txt file
 (apply/check the blue changes from above)
Configuration for BIOS 1701 as CMO file to apply:

harrysun41_3600_3333CL14_UEFI1701_CMO.zip 1k .zip file

UEFI/BIOS in screenshots:

harrysun41_UEFI1701_3600_3333CL14.zip 531k .zip file

Credits goes to @1usmus for Ryzen DRAM Calculator:


Spoiler: Ryzen DRAM Calculator 0.9.9 v11 by 1usmus



  





Spoiler: Ryzen DRAM Calculator 0.9.9 v9 by 1usmus



  





Spoiler: Source of inspiration for 3333MT/s with F4-3200C14D-32GTZ




@The Stilt for the HQ B-die - 3333MHz "Safe" 1.350V settings: post #26178558
Post by @kaseki
Post by @Ramad/@kaseki (but @Ramad is using a different kit *Patriot Viper Elite 2x8GB DR*)
Post by @roybotnik
Post by @SaiKamalDoss
Post by @AlphaZero
Post by @R71800XSS
Post by @1usmus (but @1usmus is using a different kit F4-*3000*C14D-32GTZ)
Quote:


> Originally Posted by *1usmus*
> 
> *I want to write a report on the latest tests 3333 dual rank* I hope this helps many
> 
> 
> 
> 1. Memory is very sensitive to interference on the cad_bus. The decrease in the speed of response and switching of the phases of power help me.
> 
> 
> Spoiler: current power settings
> 
> 
> 
> CPU Load-line Calibration [Level 4]
> CPU Current Capability [130%]
> CPU VRM Switching Frequency [Manual]
> CPU Voltage Frequency [300]
> CPU Power Duty Control [T.Probe]
> CPU Power Phase Control [Power Phase Response]
> Manual Adjustment [Regular]
> CPU Power Thermal Control [120]
> VDDSOC Load-line Calibration [Level 4]
> VDDSOC Current Capability [120%]
> VDDSOC Switching Frequency [Manual]
> Fixed VDDSOC Switching Frequency(KHz) [300]
> VDDSOC Phase Control [Optimized]
> DRAM Current Capability [120%]
> DRAM Power Phase Control [Extreme]
> DRAM Switching Frequency [Manual]
> Fixed DRAM Switching Frequency(KHz) [300]
> 
> 
> 
> 2. The most stable state of the system with an increase in frequency above 3200 is reached by CAD_BUS 30 30 40 60. At low values, there are a lot of mistakes and blue screens.
> CAD_BUS timings I did not touch, because the system did not start or gave a blue screen. *Ramad* rule (AddrCmdSetup = AddrCmdDrvStren ) not working on 3333 and 3466.I'm thinking of synchronizing these values is not worth it. I asked *Elmor* for information - he does not have it. I managed to run 3466 on these settings (20 40 20 + 30 30 40 24), even without a coldboot, but a lot of errors 8 in HCI 5.1.
> 
> 3. Rule VTTDDR (vdram * 0.5) not working for frequencies above 3200. Current value VTTDDR 0.69960 and vdram 1.410 (it must be 0,705, but it has errors)
> 
> 4. VDRAM. 3333 run even at 1.38, but only 2gb working without error, on 1.410 12-16gb works without error.
> 
> 5. Im trying to use *Ramad* CLDO_VDDP 425, works fine on 3200 and 3333, it turned out to reduce the voltage on SOC from 1.025 to 0.98. On 3466 not started. Voltage to other components could not be reduced, errors appear.
> 
> 6. VPP 2.5 - 2.52 greatly affects the stability of the system, has a wavy form, the above to lift the voltage is useless. PLL 1.77-1.83 also greatly affects the stability of the system. Step 0.01
> 
> 7. VDDP. Dual rank is very sensitive to this parameter, only 0,900 volts work perfectly, at 855 there are sometimes errors
> 
> 8. Rtt disable / rzq3 / rzq1 and rzq1 / rzq3 / rzq1 work better than rzq3 / rzq3 / rzq1.
> + procODT 68.8 = best couple
> 
> 
> 
> 
> 
> 
> 
> 
> The worst performance was on procODT 80.
> 
> 9. tRAS tRC 28 42 there are errors with the code 2000000, removed them with tRAS tRC 30 44
> 
> 10. DRAM TUNE at a frequency above 3200 can not be touched, either the blue screen or the system is unstable
> 
> *probably did not forget anything*
> 
> 
> Spoiler: all settings
> 
> 
> 
> [2017/10/10 19:30:21]
> Ai Overclock Tuner [Manual]
> BCLK Frequency [100.0000]
> BCLK_Divider [Auto]
> Custom CPU Core Ratio [Auto]
> > CPU Core Ratio [38.00]
> Performance Bias [None]
> Memory Frequency [DDR4-3333MHz]
> Core Performance Boost [Disabled]
> SMT Mode [Enabled]
> EPU Power Saving Mode [Disabled]
> TPU [Keep Current Settings]
> CPU Core Voltage [Manual mode]
> - CPU Core Voltage Override [1.31875]
> CPU SOC Voltage [Manual mode]
> - VDDSOC Voltage Override [0.98750]
> DRAM Voltage [1.41000]
> 1.8V PLL Voltage [Auto]
> 1.05V SB Voltage [Auto]
> Target TDP [Auto]
> TRC_EOM [Auto]
> TRTP_EOM [Auto]
> TRRS_S_EOM [Auto]
> TRRS_L_EOM [Auto]
> TWTR_EOM [Auto]
> TWTR_L_EOM [Auto]
> TWCL_EOM [Auto]
> TWR_EOM [Auto]
> TFAW_EOM [Auto]
> TRCT_EOM [Auto]
> TREFI_EOM [Auto]
> TRDRD_DD_EOM [Auto]
> TRDRD_SD_EOM [Auto]
> TRDRD_SC_EOM [Auto]
> TRDRD_SCDLR_EOM [Auto]
> TRDRD_SCL_EOM [Auto]
> TWRWR_DD_EOM [Auto]
> TWRWR_SD_EOM [Auto]
> TWRWR_SC_EOM [Auto]
> TWRWR_SCDLR_EOM [Auto]
> TWRWR_SCL_EOM [Auto]
> TWRRD_EOM [Auto]
> TRDWR_EOM [Auto]
> TWRRD_SCDLR_EOM [Auto]
> Mem Over Clock Fail Count [2]
> DRAM CAS# Latency [14]
> DRAM RAS# to CAS# Read Delay [14]
> DRAM RAS# to CAS# Write Delay [14]
> DRAM RAS# PRE Time [14]
> DRAM RAS# ACT Time [30]
> Trc_SM [44]
> TrrdS_SM [6]
> TrrdL_SM [9]
> Tfaw_SM [34]
> TwtrS_SM [4]
> TwtrL_SM [12]
> Twr_SM [12]
> Trcpage_SM [Auto]
> TrdrdScl_SM [2]
> TwrwrScl_SM [2]
> Trfc_SM [277]
> Trfc2_SM [Auto]
> Trfc4_SM [Auto]
> Tcwl_SM [14]
> Trtp_SM [8]
> Trdwr_SM [7]
> Twrrd_SM [3]
> TwrwrSc_SM [Auto]
> TwrwrSd_SM [Auto]
> TwrwrDd_SM [Auto]
> TrdrdSc_SM [Auto]
> TrdrdSd_SM [Auto]
> TrdrdDd_SM [Auto]
> Tcke_SM [1]
> ProcODT_SM [68.6 ohm]
> Cmd2T [1T]
> Gear Down Mode [Auto]
> Power Down Enable [Disabled]
> RttNom [RZQ/1]
> RttWr [RZQ/3]
> RttPark [RZQ/1]
> MemAddrCmdSetup_SM [Auto]
> MemCsOdtSetup_SM [Auto]
> MemCkeSetup_SM [Auto]
> MemCadBusClkDrvStren_SM [30.0 Ohm]
> MemCadBusAddrCmdDrvStren_SM [30.0 Ohm]
> MemCadBusCsOdtDrvStren_SM [40.0 Ohm]
> MemCadBusCkeDrvStren_SM [60.0 Ohm]
> VTTDDR Voltage [0.69960]
> VPP_MEM Voltage [2.51500]
> DRAM CTRL REF Voltage on CHA [Auto]
> DRAM CTRL REF Voltage on CHB [Auto]
> VDDP Voltage [0.90000]
> VDDP Standby Voltage [0.90000]
> 1.8V Standby Voltage [Auto]
> CPU 3.3v AUX [Auto]
> 2.5V SB Voltage [Auto]
> DRAM R1 Tune [Auto]
> DRAM R2 Tune [Auto]
> DRAM R3 Tune [Auto]
> DRAM R4 Tune [Auto]
> PCIE Tune R1 [Auto]
> PCIE Tune R2 [Auto]
> PCIE Tune R3 [Auto]
> PLL Tune R1 [Auto]
> PLL reference voltage [Auto]
> T Offset [Auto]
> Sense MI Skew [Auto]
> Sense MI Offset [Auto]
> Promontory presence [Auto]
> Clock Amplitude [Auto]
> CPU Load-line Calibration [Level 4]
> CPU Current Capability [130%]
> CPU VRM Switching Frequency [Manual]
> CPU Voltage Frequency [300]
> CPU Power Duty Control [T.Probe]
> CPU Power Phase Control [Power Phase Response]
> Manual Adjustment [Regular]
> CPU Power Thermal Control [120]
> VDDSOC Load-line Calibration [Level 4]
> VDDSOC Current Capability [120%]
> VDDSOC Switching Frequency [Manual]
> Fixed VDDSOC Switching Frequency(KHz) [300]
> VDDSOC Phase Control [Optimized]
> DRAM Current Capability [120%]
> DRAM Power Phase Control [Extreme]
> DRAM Switching Frequency [Manual]
> Fixed DRAM Switching Frequency(KHz) [300]
> DRAM VBoot Voltage [1.41000]
> Security Device Support [Enable]
> TPM Device Selection [Discrete TPM]
> Erase fTPM NV for factory reset [Enabled]
> PSS Support [Enabled]
> NX Mode [Disabled]
> SVM Mode [Disabled]
> SATA Port Enable [Enabled]
> PT XHCI GEN1 [Auto]
> PT XHCI GEN2 [Auto]
> PT USB Equalization4 [Auto]
> PT USB Redriver [Auto]
> PT PCIE PORT 0 [Auto]
> PT PCIE PORT 1 [Auto]
> PT PCIE PORT 2 [Auto]
> PT PCIE PORT 3 [Auto]
> PT PCIE PORT 4 [Auto]
> PT PCIE PORT 5 [Auto]
> PT PCIE PORT 6 [Auto]
> PT PCIE PORT 7 [Auto]
> Onboard PCIE LAN PXE ROM [Enabled]
> AMD CRB EHCI Debug port switch [Disabled]
> Onboard LED [Disabled]
> Hyper kit Mode [Disabled]
> SATA Port Enable [Enabled]
> SATA Mode [AHCI]
> SMART Self Test [Enabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> ErP Ready [Disabled]
> Restore On AC Power Loss [Power Off]
> Power On By PCI-E/PCI [Disabled]
> Power On By RTC [Disabled]
> Super I/O Clock Skew [Auto]
> HD Audio Controller [Enabled]
> PCIEX4_3 Bandwidth [Auto]
> PCIEX16_1 Mode [Auto]
> PCIEX8_2 Mode [Auto]
> PCIEX4_3 Mode [Auto]
> M.2 Link Mode [GEN 3]
> SB Link Mode [Auto]
> Asmedia USB 3.1 Controller [Enabled]
> RGB LED lighting [Disabled]
> Intel LAN Controller [Disabled]
> USB Type C Power Switch for USB3.1_E1 [Auto]
> USB Type C Power Switch for USB3.1_EC2 [Auto]
> Network Stack [Disabled]
> Debug Port Table [Disabled]
> Debug Port Table 2 [Disabled]
> Device [WDC WD30EFRX-68EUZN0]
> Legacy USB Support [Enabled]
> XHCI Hand-off [Enabled]
> USB Mass Storage Driver Support [Enabled]
> Generic USB Flash Disk 0.00 [Auto]
> Generic-SD/MMC/MS/MSPRO 1.00 [Auto]
> USB3.1_E1 [Auto]
> USB3_1 [Enabled]
> USB3_2 [Enabled]
> USB3_3 [Enabled]
> USB3_4 [Enabled]
> USB3_5 [Auto]
> USB3_6 [Auto]
> USB3_7 [Auto]
> USB3_8 [Auto]
> USB3_9 [Auto]
> USB3_10 [Auto]
> USB2_11 [Auto]
> USB2_12 [Auto]
> USB2_13 [Auto]
> USB2_14 [Auto]
> USB_15 [Auto]
> USB_16 [Auto]
> CPU Temperature [Monitor]
> MotherBoard Temperature [Monitor]
> VRM Temperature [Monitor]
> PCH Temperature [Monitor]
> T_Sensor1 Temperature [Monitor]
> CPU Fan Speed [Monitor]
> Chassis Fan 1 Speed [Monitor]
> Chassis Fan 2 Speed [Monitor]
> Chassis Fan 3 Speed [Monitor]
> W_PUMP+ Speed [Monitor]
> CPU Optional Fan Speed [Monitor]
> AIO_PUMP Speed [Monitor]
> W_FLOW Speed [Monitor]
> W_IN Temperature [Monitor]
> W_OUT Temperature [Monitor]
> CPU Core Voltage [Monitor]
> 3.3V Voltage [Monitor]
> 5V Voltage [Monitor]
> 12V Voltage [Monitor]
> CPU Q-Fan Control [Disabled]
> W_PUMP+ Control [Auto]
> Chassis Fan 1 Q-Fan Control [Auto]
> Chassis Fan 1 Q-Fan Source [CPU]
> Chassis Fan 1 Smoothing Up/Down Time [0 sec]
> Chassis Fan 1 Speed Low Limit [200 RPM]
> Chassis Fan 1 Profile [Standard]
> Chassis Fan 2 Q-Fan Control [Auto]
> Chassis Fan 2 Q-Fan Source [CPU]
> Chassis Fan 2 Smoothing Up/Down Time [0 sec]
> Chassis Fan 2 Speed Low Limit [200 RPM]
> Chassis Fan 2 Profile [Standard]
> Chassis Fan 3 Q-Fan Control [Auto]
> Chassis Fan 3 Q-Fan Source [CPU]
> Chassis Fan 3 Smoothing Up/Down Time [0 sec]
> Chassis Fan 3 Speed Low Limit [200 RPM]
> Chassis Fan 3 Profile [Standard]
> OnChip SATA Channel [Auto]
> OnChip SATA Type [AHCI]
> USB3_1 [Enabled]
> USB3_2 [Enabled]
> USB3_3 [Enabled]
> USB3_4 [Enabled]
> IR Config [RX & TX0 Only]
> SdForce18 Enable [Disabled]
> SD Mode configuration [AMDA]
> Uart 0 Enable [Enabled]
> Uart 1 Enable [Enabled]
> I2C 0 Enable [Enabled]
> I2C 1 Enable [Enabled]
> I2C 2 Enable [Disabled]
> I2C 3 Enable [Disabled]
> GPIO Devices Support [Auto]
> ESATA Port On Port 0 [Auto]
> ESATA Port On Port 1 [Auto]
> ESATA Port On Port 2 [Auto]
> ESATA Port On Port 3 [Auto]
> ESATA Port On Port 4 [Auto]
> ESATA Port On Port 5 [Auto]
> ESATA Port On Port 6 [Auto]
> ESATA Port On Port 7 [Auto]
> SATA Power On Port 0 [Auto]
> SATA Power On Port 1 [Auto]
> SATA Power On Port 2 [Auto]
> SATA Power On Port 3 [Auto]
> SATA Power On Port 4 [Auto]
> SATA Power On Port 5 [Auto]
> SATA Power On Port 6 [Auto]
> SATA Power On Port 7 [Auto]
> SATA Port 0 MODE [Auto]
> SATA Port 1 MODE [Auto]
> SATA Port 2 MODE [Auto]
> SATA Port 3 MODE [Auto]
> SATA Port 4 MODE [Auto]
> SATA Port 5 MODE [Auto]
> SATA Port 6 MODE [Auto]
> SATA Port 7 MODE [Auto]
> SATA Hot-Removable Support [Auto]
> SATA 6 AHCI Support [Auto]
> Int. Clk Differential Spread [Auto]
> SATA MAXGEN2 CAP OPTION [Auto]
> SATA CLK Mode Option [Auto]
> Aggressive Link PM Capability [Auto]
> Port Multiplier Capability [Auto]
> SATA Ports Auto Clock Control [Auto]
> SATA Partial State Capability [Auto]
> SATA FIS Based Switching [Auto]
> SATA Command Completion Coalescing Support [Auto]
> SATA Slumber State Capability [Auto]
> SATA MSI Capability Support [Auto]
> SATA Target Support 8 Devices [Auto]
> Generic Mode [Auto]
> SATA AHCI Enclosure [Auto]
> SATA SGPIO 0 [Disabled]
> SATA SGPIO 1 [Disabled]
> SATA PHY PLL [Auto]
> AC/DC Change Message Delivery [Disabled]
> TimerTick Tracking [Auto]
> Clock Interrupt Tag [Enabled]
> EHCI Traffic Handling [Disabled]
> Fusion Message C Multi-Core [Disabled]
> Fusion Message C State [Disabled]
> SPI Read Mode [Auto]
> SPI 100MHz Support [Auto]
> SPI Normal Speed [Auto]
> SPI Fast Read Speed [Auto]
> SPI Burst Write [Auto]
> I2C 0 D3 Support [Auto]
> I2C 1 D3 Support [Auto]
> I2C 2 D3 Support [Auto]
> I2C 3 D3 Support [Auto]
> UART 0 D3 Support [Auto]
> UART 1 D3 Support [Auto]
> SATA D3 Support [Auto]
> EHCI D3 Support [Auto]
> XHCI D3 Support [Auto]
> SD D3 Support [Auto]
> S0I3 [Auto]
> Chipset Power Saving Features [Enabled]
> SB Clock Spread Spectrum [Auto]
> SB Clock Spread Spectrum Option [-0.375%]
> HPET In SB [Auto]
> MsiDis in HPET [Auto]
> _OSC For PCI0 [Auto]
> USB Phy Power Down [Auto]
> PCIB_CLK_Stop Override [0]
> USB MSI Option [Auto]
> LPC MSI Option [Auto]
> PCIBridge MSI Option [Auto]
> AB MSI Option [Auto]
> SB C1E Support [Auto]
> SB Hardware Reduced Support [Auto]
> GPP Serial Debug Bus Enable [Auto]
> IOMMU [Auto]
> Remote Display Feature [Auto]
> Gnb Hd Audio [Auto]
> PSPP Policy [Auto]
> Memory Clock [Auto]
> Bank Interleaving [Enabled]
> Channel Interleaving [Enabled]
> Memory Clear [Disabled]
> Fast Boot [Enabled]
> Next Boot after AC Power Loss [Normal Boot]
> Boot Logo Display [Disabled]
> POST Report [1 sec]
> Boot up NumLock State [Enabled]
> Wait For 'F1' If Error [Enabled]
> Option ROM Messages [Enabled]
> Interrupt 19 Capture [Disabled]
> Setup Mode [Advanced Mode]
> Launch CSM [Enabled]
> Boot Device Control [UEFI and Legacy OPROM]
> Boot from Network Devices [Legacy only]
> Boot from Storage Devices [Legacy only]
> Boot from PCI-E Expansion Devices [Legacy only]
> OS Type [Other OS]
> Setup Animator [Disabled]
> Load from Profile [1]
> Profile Name []
> Save to Profile [1]
> CPU Core Voltage [Auto]
> VDDSOC Voltage [Auto]
> 1.8V PLL Voltage [Auto]
> BCLK Frequency [Auto]
> CPU Ratio [Auto]
> Bus Interface [PCIEX16/X8_1]


Quote:


> Originally Posted by *Ramad*
> 
> CAD Bus Timings are at Auto. Drivers impedance are 20 - 20 - 40 - 60
> 
> I think it's my fault for not giving more detail on what I meant by systematic, here are the details.
> 
> I would do it like this:
> 
> *Manipulating CLDO*
> 
> *Constants:*
> 
> *Getting the processor out of the equation:*
> I would set the processor to it's default frequency that's 3.6GHz, give a voltage at 1.25V, disable CPB and SOC voltage to 1.05V. (The CPU now is a constant and have no impact on the outcome).
> 
> *Getting the RAM out of the equation:*
> I have my RAM frequency at 3200MT/s with my stable timings (that I have been running for over a month and know is stable), voltage at 1.37, VTTDDR at 1.38/2, CAD impedance at 20 - 20 - 40 - 60(40). (The RAM now have no impact on the outcome).
> 
> *Getting PROCODT of the equation:*
> I would set it to the value that I have been using with my stable RAM settings. (PROCODT now have no impact on the outcome).
> 
> *1 Variable:* *Always 1 variable, never more than 1 variable.*
> 
> *My 1 Variable is CLDO_VDDP:* This is my variable, the value that I would change and see the outcome and its effect on system stability.
> 
> *Example:* trigger 900mV
> 
> Trigger CLDO_VDDP voltage at 900mV
> 
> Boot to OS, start a a test for 30 min., if no error, then I would drop the RAM and VTTDDR to the voltage my RAM is rated at, that's 1.35V and VTTDDR 1.36V/2 (the board overvolts the RAM rail by 0.016V), then boot to OS and run a test again.
> 
> If CLDO_VDDP at 900mV allows me to drop the RAM voltage to the rated voltage, then it's a good value.
> 
> *Collecting DATA:* This is where I look at the details and see which value had the least hiccups.
> 
> *Possible Outcome:* More than 1 good CLDO_VDDP value
> 
> The right CLDO_VDDP value is the value that lets me drop the RAM, CPU and SOC voltages without sacrificing stability.
> 
> Manipulating PROCODT is the same way, but CLDO_VDDP must be a constant, means you choose a right value and *stick* with it.
> 
> This is what I meant when I wrote systematic.


Quote:


> Originally Posted by *1usmus*
> 
> I would reconfigure the power system with an emphasis on overclocking the processor + the current limitation on SOC/DRAM will allow for greater stability for system
> 
> 
> 
> 
> 
> 
> 
> 
> 
> CPU Load-line Calibration [Level 3]
> *CPU Current Capability [130%]*
> CPU VRM Switching Frequency [Auto]
> VRM Spread Spectrum [Disabled]
> Active Frequency Mode [Disabled]
> CPU Power Duty Control [Extreme]
> *CPU Power Phase Control [Power Phase Response]
> Manual Adjustment [Ultra Fast]*
> *VDDSOC Load-line Calibration [Level 3]*
> *VDDSOC Current Capability [120%]*
> VDDSOC Switching Frequency [Auto]
> *VDDSOC Phase Control [Optimized]*
> *DRAM Current Capability [100%]*
> DRAM Power Phase Control [Extreme]
> DRAM Switching Frequency [Manual]
> *Fixed DRAM Switching Frequency(KHz) [300]*
> 
> by the way i come back again on 3101, he is pleasant to me more. At 1701 there are problems and a long start



About CLOD_VDDP:
Quote:


> Originally Posted by *The Stilt*
> 
> Few suggestions regarding the controls allowed by the new (AGESA 1.0.0.6) bioses:
> 
> - In case you run into a MEMCLK hole, adjust the CLDO_VDDP voltage. The VDDP adjustment window is rather narrow, usually < 100mV. Also the window is neither static or linear. Because of that the setting which is optimal for frequency *x* might not be optimal for frequency *y*. Also since the window is not linear, but more of a wave form e.g. VDDP at 975mV might work perfectly fine whereas 980mV won't be able to train the memory. The MEMCLK hole is both CPU and DRAM specific, but so far I haven't seen any evidence it being motherboard specimen specific. This means that swapping either the CPU or the memory (to another CPU or modules) might either introduce or the get rid of the MEMCLK hole. Personally I have 100% success rate in clearing the MEMCLK hole with CLDO_VDDP adjustment (1x R7 1700, 1x R7 1800X and 2x R7 1700X). All of the MEMCLK holes on these CPUs have been cleared using 937 - 1000mV setting. Do note that when you change the CLDO_VDDP voltage, saving the bios settings *will not* put the new CLDO_VDDP voltage into effect, since the CLDOs can only be programmed during a cold reset or a cold boot. Because of that I suggest that you save the new CLDO_VDDP value and press the reset button before the system has booted up again. Also CLDO_VDDP must be at least 100mV lower than the DRAM voltage at all times. Regardless it is not recommended to exceed 1050mV.
> 
> - For Samsung B-die dual rank modules I suggest that 96Ohm ProcODT is used.


Quote:


> Originally Posted by *1usmus*
> 
> I decided to write a small article explaining why some systems work fine at 3200+ and others do not at all
> 
> *Influence of СLDO_VDDP on MEMCLK "holes"*
> 
> CLDO_VDDP is a voltage regulator for the module (physical interface) of encoding and decoding of the transmitted and received data stream. The purpose of coding is to simplify the process of restoring the data stream of the receiver. It determines the signals, signal ratios and time parameters necessary for transferring control information, reading and writing data to DRAM devices. In plain language, CLDO_VDDP is the voltage that regulates the memory access at a certain frequency. "Hole" in turn - the frequency gap on which the memory controller can operate with our RAM.
> 
> Consider this simple picture:
> 
> 
> 
> It shows 3 identical systems (motherboard + RAM + processor). All 3 systems were overclocked and received the following results:
> 
> 1) The system was perfectly dispersed to a frequency of 3333 MHz
> 2) The system was accelerated to 2933
> 3) The system did not start at all
> 
> If all systems are the same, why such results? Let's understand. The bottom line is that each memory controller (IMC) has its own technical characteristics ("voltage" and time) and at the same voltage / frequency it will behave differently, namely it will have different access to memory. Red marked our MEMCLK holes, these are the very hole-mediators through which our memory controller communicates with RAM, and if there is no hole in the frequency range chosen by us - the system does not start or start, but the memory runs with errors. At you I think there was a question as these holes to move and expand - all is very simple, voltage CLDO_VDDP allows to spend the given manipulations. The only difficulty is that these holes can not be mathematically calculated. A vivid example of CLDO_VDDP 866 which is magical for many. The hole of this voltage is in the region of 3300-3500 MHz, but again not for all systems. As shown by our internal tests, not all of it works, I repeat all the IMC are different and require a different voltage CLDO_VDDP to achieve the same frequency.
> 
> In view of the fact that the shape of the voltage CLDO_VDDP is wave, the minimum voltage change can drastically change the stability of the system. The voltage step is 1 mv. Borders from 700 to 975.
> 
> I also want to publish a list of CLDO_VDDP, which can help stabilize your memory
> 
> 
> 
> Spoiler: CLDO_VDDP list (volts)
> 
> 
> 
> 0.562
> 0.568
> 0.573
> 0.579
> 0.585
> 0.590
> 0.596
> 0.601
> 0.607
> 0.613
> 0.618
> 0.624
> 0.630
> 0.635
> 0.641
> 0.646
> 0.652
> 0.658
> 0.663
> 0.669
> 0.675
> 0.680
> 0.686
> 0.691
> 0.697
> 0.703
> 0.708
> 0.714
> 0.720
> 0.725
> 0.731
> 0.736
> 0.742
> 0.748
> 0.753
> 0.759
> 0.765
> 0.770
> 0.776
> 0.781
> 0.787
> 0.793
> 0.798
> 0.804
> 0.810
> 0.815
> 0.821
> 0.826
> 0.832
> 0.838
> 0.843
> 0.849
> 0.855
> 0.860
> 0.866
> 0.871
> 0.877
> 0.883
> 0.888
> 0.894
> 0.900
> 0.905
> 0.911
> 0.916
> 0.922
> 0.928
> 0.933
> 0.939
> 0.945
> 0.950
> 0.956
> 0.961
> 0.967
> 0.973
> 
> 
> 
> *upd 1 : small addition-explanation*
> 
> The curve represente your dram voltage signal, changing cldo_vddp move back and forth this signal compared to your available frequency setting.
> The purpose to changing it is to make the curve crossed your setting line on the appropriate frequency setting.
> Whereas the zone where there is no curve present is a memory hole .
> Depending of your IMC or RAM the curve can vary in lenght or thickness.
> 
> 
> 
> only the form is more oblate, in dozens of times



About DRAM Voltage and VTTDDR Voltage:
Quote:


> Originally Posted by *1usmus*
> 
> I want to share with you the results of my testing
> 
> 
> 
> 
> 
> 
> 
> 
> 
> *In most cases, the memory works incorrectly because of incorrect voltage DRAM and VTT_DDR*
> On this picture in green I selected the best options
> 
> do not argue, they are not universal, to calculate their personal voltages, use my calculator, the tab VDRAM / VTT DDR Calculator


Quote:


> Originally Posted by *1usmus*


Quote:


> Originally Posted by *Ramad*
> 
> *RAM and VTTDDR voltages*
> 
> I had time last week to take a look at a few things with BIOS version 1403. Among other things, I tried to figure out the reason for that random error we all know, which can hit my system with no warning, it could while running OCCT or IBT right after few hours of HCI memtest. Starting with a look at the RAM voltage I chose in the BIOS and the reported/read RAM voltage by the BIOS and HWINFO I was certain that the motherboard is applying higher RAM voltage than the value I choose.
> 
> I did experiment with VTTDDR in earlier BIOS versions (9945/9943 and older) which did not provide CAD settings, that could help stabilize the system, however, with CAD and Rtt on 1401/1403, better stability is possible, but that random error still show up now and then.
> 
> This week I tried configuring RAM voltages based on BIOS and HWINFO readings. In all of the tests is the following settings used:
> 
> *
> *
> 
> CPU voltage: 1.238V + 0.1375V
> SOC: 1.02500V
> 1.8V PLL: 1.86V
> CLDO_VDDP: 868mv
> VPP: 0.960V
> CAD: 20 -20 -40 - 60
> Rtt: Disabled - RZQ/3 - RZQ/1
> RAM voltage: As read by the BIOS/HWINFO
> VTTDDR: 0.5 x RAM voltage (BIOS value and read value)
> RAM tested: 12 GiB
> 
> - Starting with default VTTDDR voltage = 0.6732V @1.35V set in the BIOS and read as 1.373V by BIOS and software: *FAIL with 2 errors within 6 min.*
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> - Lowering RAM voltage to 1.335V will result the BIOS/software to read it at 1.352V, VTTDDR voltage kept at 0.6732V: *PASS for more than 1½ hour and 300%.*
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 
> 
> 
> 
> - Raising the RAM voltage to 1.35V will result the BIOS/software to read the voltage at 1.373V, VTTDDR voltage is raised to 0.6798V: *FAIL with 1 error within 1 min.
> *
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 
> 
> 
> 
> - RAM voltage kept at 1.35V, read as 1.373V by BIOS/software, VTTDDR voltage is raised to 0.6864V: *PASS with more than 1½ hour and 300%.*
> 
> 
> Spoiler: Warning: Spoiler!
> 
> 
> 
> 
> 
> 
> 
> *What does it mean?:*
> 
> I can only talk about my hardware and my experience with the BIOS. What it means for me is, VTTDDR needs to be tweeked based on BIOS/software read RAM voltages and not the value I test in the BIOS, means if I test 1.35V and the BIOS/software report it 1.373V, then VTTDDR should be 0.5 x 1.373V = 0.6864V and so on.
> 
> What it does mean for you is based on your experience with your hardware, and if you are suffering of that random error, then this may be a solution for you too. But if your RAM does not care about the balance between RAM and VTTDDR voltages and you are content with your results, then this is not for you.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Edit: Corrections + new results.


----------



## VPII

I need some advice. I've got the following:

AMD Ryzen 7 1700 running stock for what I'm going to explain
Asus Crosshair VI Hero bios 3501
2 x 8GB G.Skill TridentZ RGB F4-3200C14D-16GTZR

Initially when I installed the ram it was no problem running the ram at speed and timings when using the preset in the bios. Unfortunately I'll get these random BLUE SCREENS and when I searched I found that the problem may be one of two things. Windows system files being corrupt or memory errors. I did a full system file check and everything appeared to be in order. I then ran Windows Memory Diagnostic tool which runs a memory check upon startup and it quickly told me that there are problems with the hardware. I took it a bit further and ran memtest86 which after running for 7 hours found 86 errors. This was all done with the cpu running stock and memeory voltage at 1.4vdimm compared to the 1.35v it states on the package.

This morning I decided to up the vdimm a little more to 1.475 and ran the windows memory diagnostics tool again and it passed. I will not gradually drop the vdimm and see whether it still passes, but would this mean I need to have the memory replaced?


----------



## rdr09

Quote:


> Originally Posted by *VPII*
> 
> I need some advice. I've got the following:
> 
> AMD Ryzen 7 1700 running stock for what I'm going to explain
> Asus Crosshair VI Hero bios 3501
> 2 x 8GB G.Skill TridentZ RGB F4-3200C14D-16GTZR
> 
> Initially when I installed the ram it was no problem running the ram at speed and timings when using the preset in the bios. Unfortunately I'll get these random BLUE SCREENS and when I searched I found that the problem may be one of two things. Windows system files being corrupt or memory errors. I did a full system file check and everything appeared to be in order. I then ran Windows Memory Diagnostic tool which runs a memory check upon startup and it quickly told me that there are problems with the hardware. I took it a bit further and ran memtest86 which after running for 7 hours found 86 errors. This was all done with the cpu running stock and memeory voltage at 1.4vdimm compared to the 1.35v it states on the package.
> 
> This morning I decided to up the vdimm a little more to 1.475 and ran the windows memory diagnostics tool again and it passed. I will not gradually drop the vdimm and see whether it still passes, but would this mean I need to have the memory replaced?


I would recommend returning the ram and if you can - get a G. Skill FlareX 3200. If it does not run at spec, then return it.


----------



## freestaler

I did found my "rockstable" setting. With this settings all works just fine, Prime95, Aida+, HCL. Maybe i didnt get a good 1700, too much vcore and i can boot with 3600 and CL14 Timmings but no way to get them stable. if i look at other Adia64 result, id looks for me as i got the better Latency and bandwith with less strong value (i use 16,16,16). So i just happy. maybe somebody else can use this setting. With the RyzenRamCalc Value it didnt boot,

[email protected]@1.4375---3466Mhz-C16-16-16-21-37-1T---1.415v---SOC 1.0875v---Asrock x370 Taichi BIOS 3.2a---HCI---3000---GSKILL-F4-4133C19-8GTZA-- GDM OFF -- BGS disabled -- BGSALT disabled - CAD & ProcOCT @ Auto


----------



## PuPpEt

Guys, i would like to know why if i set 14-13-13-13 like the Ryzen DRAM Calculator fast preset say (main+advanced) i'm getting instantly a CORE error (or whatever error) with OCCT (or IBS AVX):


If i put 14-14-14-14 everything is fine (every other settings remain the same), OCCT starts (or every other program) and it seems even stable after some tests (still need to do intensive ones).

Why with 13 tRCD and 13 tRP doesn't work? I've even tried 13 tRCD and 14 tRP and it fails too.


----------



## freestaler

Quote:


> Originally Posted by *PuPpEt*
> 
> Guys, i would like to know why if i set 14-13-13-13 like the Ryzen DRAM Calculator fast preset say (main+advanced) i'm getting instantly a CORE error (or whatever error) with OCCT (or IBS AVX):
> 
> 
> If i put 14-14-14-14 everything is fine (every other settings remain the same), OCCT starts (or every other program) and it seems even stable after some tests (still need to do intensive ones).
> 
> Why with 13 tRCD and 13 tRP doesn't work? I've even tried 13 tRCD and 14 tRP and it fails too.


My sys wont boot with "odd" CL timmings under value of 16. So try with 14-15-15-15.. when this doesnt boot you know then, you got them same "bug". try to upper your frequence then, try to go with this timmings at 3333.


----------



## Shaav

[email protected] 1.20v---F10---HCI---800%---BLT16G4D30AETA.K16









https://abload.de/img/unbenanntqiuhl.png


----------



## btoledob

[email protected] 1.078v---BIOS X37AGB30---Stressapptest---1 Hour--cmk8gx4m2b3000c15

Motherboard is Biostar Racing X370GT7


----------



## shubjero

Quote:


> Originally Posted by *spyshagg*
> 
> I had degradation to the point of failure on a kit of CMK16GX4M2B3000C15 2x8GB ddr4 3000 while running XMP profile with an older BIOS on Asus Prime b350 +
> 
> The XMP worked right of the bat. But this past this past week the computer started BSODING more and more often and now every 10 minutes.
> 
> - I proceeded to install the latest BIOS which auto-detected the RAM as 3000mhz without need of XMP. The BSODS persisted.
> 
> - I proceeded to downclock the ram to 2133mhz without success.
> 
> - I proceeded to remove one of the sticks for a quick diagnosis and the bsods have stopped. Its a workstation so I cannot test it further, but it appears one of the sticks has indeed gradually deteriorated.


I have the same ram but in the gigabyte k7 and this ram had never been stable for me. Windows memory tests fail when both dimms are used but when tested individually (standard 4 pass), no errors are detected. I have a replacement set coming today from Amazon. If these still don't work I'm going to try different memory.


----------



## ZeNch

Quote:


> Originally Posted by *shubjero*
> 
> I have the same ram but in the gigabyte k7 and this ram had never been stable for me. Windows memory tests fail when both dimms are used but when tested individually (standard 4 pass), no errors are detected. I have a replacement set coming today from Amazon. If these still don't work I'm going to try different memory.


In my tests the more common fail is in test 8 (when i test new settings for ram)
1st i run 16 passes of test8 (2 hours aprox)
2nd run 12 or 16 passes of all test (14 or 16 hours i dont remember)

the first test is to see fast if my setting are wrong, the 2nd is a complete test of stability.

i repeat, commonly i have errors with test8 only.


----------



## miklkit

@btoledob

What ram are you using? I am running this ram which is Samsung E-die. https://www.newegg.com/Product/Product.aspx?Item=N82E16820231940

With the same bios it runs at 3200 but is not stable. It runs great at 2933 and with a little tweaking I got it to 3030 14-16 with 1.4 volts and SOC of 1.119v. Performance is comparable to 3200 with loose timings.


----------



## Warlord1981

Hello guyz. I own G.Skill F4-3000C15D-16GTZR (2x8 Hynix-A Single Rank) with [email protected]

Has anyone managed to run these RAMs stable at 3200 or 3066 and with which settings? Or it is impossible and I should stick with 2933?

Thank you in advance!


----------



## veirge

Edit. Nvm. Is there a way to delete this post.


----------



## piglett

Hi guys!
Long time lurker around here, now seeking help.

System specs:
Ryzen 1700
AsRock Killer SLI motherboard
G.Skill Trident z 3600 c15 16gb kit (F4-3600C15D-16GTZ)
Reeven Okeanos cooler.

I can't get my memory over 2933Mhz, not even at 3000Mhz. Currently running bios 4.5, AGESA 1.0.0.0, previous bios 3.40 AGESA 1.0.0.6b.
The processor runs at 3.6Ghz at 1.1V fully stable( yeah, i'm an undervolter).;SOC at 0.9V, memory timings 14-14-14-31-45 1T at 1.35V.
I've tried raising the SOC voltage at a max of 1.2V, timings loosened at 16-16-16-42 1T, increased ram voltage up to 1.42V. Didn't even bother to try frequencies over 3200Mhz.

Could someone please test getting over 2933Mhz while undervolting at 3.6Ghz 1.1V? How can this be a limiting factor?

Thank you!

EDIT: forgot to mention that the systems boots with the ram over 2933MHz, but crashes, restarts, blue-screens, fails tests.


----------



## SlushPuppy007

Quote:


> Originally Posted by *piglett*
> 
> Hi guys!
> Long time lurker around here, now seeking help.
> 
> System specs:
> Ryzen 1700
> AsRock Killer SLI motherboard
> G.Skill Trident z 3600 c15 16gb kit (F4-3600C15D-16GTZ)
> Reeven Okeanos cooler.
> 
> I can't get my memory over 2933Mhz, not even at 3000Mhz. Currently running bios 4.5, AGESA 1.0.0.0, previous bios 3.40 AGESA 1.0.0.6b.
> The processor runs at 3.6Ghz at 1.1V fully stable( yeah, i'm an undervolter).;SOC at 0.9V, memory timings 14-14-14-31-45 1T at 1.35V.
> I've tried raising the SOC voltage at a max of 1.2V, timings loosened at 16-16-16-42 1T, increased ram voltage up to 1.42V. Didn't even bother to try frequencies over 3200Mhz.
> 
> Could someone please test getting over 2933Mhz while undervolting at 3.6Ghz 1.1V? How can this be a limiting factor?
> 
> Thank you!
> 
> EDIT: forgot to mention that the systems boots with the ram over 2933MHz, but crashes, restarts, blue-screens, fails tests.


supp?

I had to push 1.45 volts through my 1800X to get to 3.9GHz on the x370 taichi (BIOS P3.20), so 3.6 @ 1.1 is already pretty impressive for a 1700...

Oh and.. its on a 2 x triple 360mm custom loop..

That RAM kit ur running is as sweet as you'll get for Ryzen 1.0. Low latency high speed | B-die

I have the trident z rgb 4266 CL19, and managed to get the following, can possibly do better, but got tired after weeks of trail and error.

been running this config for about 3 months, stress tested latest prime95 over 2 days, memtest 2 days, no random reboots | crashes, stable AF.


----------



## lizhenghong728

That is good


----------



## PuPpEt

Hope anyone can help me... i'm trying to get stable G.Skill F4-3466C16-8GTZR @ 3333Mhz.
CPU is at 3.9Ghz @ 1.33v (but i can go lower)
CPU LLC 3, SOC LLC 2
Motherboard: AsRock x370 Taichi bios 3.20a

I've used the DRAM Calculator "Fast Preset".



But i'm getting error from 1 to 10 minutes of HCI Memtest...

I've tried changing with almost every combination possible:
- DRAM Voltage from 1.35v to 1.39v in BIOS (showing in HWiNFO64 from 1.36v to 1.41v);
- SOC Voltage from 1.025v to 1.05v (showing in HWiNFO64 from 1.030v to 1.051v);
- The three combination of procODT as the calculator suggest;
- The four combination of CAD_BUS as the calculator suggest;
- VDDP Voltage 850 and 900;
- CLD0_VDDP: 700, 425 and 866 (but i'm not 100% sure if on Taichi the COLD RESET i do to trigger the value is correct... i can't find a way to check);
- VTTDDR is automatic, 0.680 or 0.690.

I can pass a IBS AVX of 10 passes on Very High with all those settings and prolly Prime95, but i fail always HCI Memtest...

I don't understand and don't know what to do anymore...


----------



## abso

Try Geardownmode Enabled


----------



## PuPpEt

Quote:


> Originally Posted by *abso*
> 
> Try Geardownmode Enabled


It's the same, i get errors in HCI


----------



## freestaler

Quote:


> Originally Posted by *PuPpEt*
> 
> It's the same, i get errors in HCI


Try my settings. your Gskill memory should be close the same as my one when i look at the value for the calculator.. i think the calculator works for Asus "ram" programming.. not really for asrock. we had to find your timmings self.

http://www.overclock.net/t/1628751/official-amd-ryzen-ddr4-24-7-memory-stability-thread/1320#post_26550017

Short;

14/3200*2 = 0,00875s
14/3333*2 = 0.00840s
16/3466*2 = 0,00923s
16/3600*2= 0,00888s

If you look at nanoseconds, you could see that your ram should works around 9,23 Nanoseconds,, with your settings now you are "to fast".. gskill would sell this Kit as "3200Cl14" and not as 3466 Cl16.. so you need more VCore as default, maybe at lot more defently when you would go so hard close to 8 ns. ;-)


----------



## Dimswitch

User: Dimswitch
CPU: 1700X @ Stock
Mobo: ASRock X370 TaiChi
Speed: 3333-14-14-14-28-1T @ 1.38V
SOC: 1.0375V
BIOS: P3.20
Model: F4-3200C14D-16GVR
Test: HCI 1600%




Memory Interleave @ Channel, 256, Hash enabled
procodt/CAD_bus/termination @ Auto (hurray for b-die)
Warm boots and cold boots equally fast and go on the first training.

I'm pretty happy with the current performance+stability so I'll leave it here for now.

Thanks @gupsterg, @1usmus, @The Stilt for the tools and info that got me started.

*edited with lower subtimings and longer testing


----------



## PuPpEt

User: PuPpEt
CPU: 1700 @ 3.9Ghz - 1.31875v (BIOS) 1.312 (HWiNFO64)
Motherboard: ASRock X370 Taichi
Speed: 3200-14-14-14-28-1T @ 1.355v (BIOS) 1.376v (HWiNFO64)
SOC: 1.025v (BIOS) 1.032v (HWiNFO64)
BIOS: P3.20A
Model: F4-3466C16-8GTZR
Test: IBS AVX 10 Passes "Very High" - Prime95 "Blend" 1 Hour - HCI 400%

Other settings: CPU LLC 3 - SOC LLC 2 - procODT 53 RTT 5 / Off / 5 - CAD BUS 20 / 20 / 20 / 20 - CLD0 VDDP 700


----------



## Synoxia

Hello, im back at memory tweakings after updating my bios. What do you think i should realistically aim for with a 16gb 3600 cl17 Tridentz B-DIE kit? Is it worth going google test thing over HCI? I regret so much not buying 3200c14...


----------



## Dr. Vodka

PuPpEt said:


> But i'm getting error from 1 to 10 minutes of HCI Memtest...
> 
> I've tried changing with almost every combination possible:
> - DRAM Voltage from 1.35v to 1.39v in BIOS (showing in HWiNFO64 from 1.36v to 1.41v);
> - SOC Voltage from 1.025v to 1.05v (showing in HWiNFO64 from 1.030v to 1.051v);
> - The three combination of procODT as the calculator suggest;
> - The four combination of CAD_BUS as the calculator suggest;
> - VDDP Voltage 850 and 900;
> - CLD0_VDDP: 700, 425 and 866 (but i'm not 100% sure if on Taichi the COLD RESET i do to trigger the value is correct... i can't find a way to check);
> - VTTDDR is automatic, 0.680 or 0.690.
> 
> I can pass a IBS AVX of 10 passes on Very High with all those settings and prolly Prime95, but i fail always HCI Memtest...
> 
> I don't understand and don't know what to do anymore...


I have the same gskill kit rated for 3466C16 16-18-18-38 2T 1.35v. This specific B-die bin isn't as high quality as for example, what's used in 3200C14 or 3600C16 kits. We need more voltage to get stability.

I'm running The Stilt's 3466MHz 15-15-15-35 1T no geardown profile, slightly relaxed to 15-16-16-36. This is on a C6H + BIOS 3502:



Spoiler
















1.425v vDIMM
1.10v vSOC
60ohms ProcODT (this is the specific value for 2 single ranked B-die sticks, or 53.3ohms)
40-40-40-40 CAD bus settings (One of Stilt's recommendations was to try higher CAD bus settings at higher than 3200MHz speeds, 40-40-40-40 did the trick for me)

This could be a baseline for you to try stuff from.



As for your case,

1.39v isn't enough for 3333 14-14-14 and tight subtimings especially for this B-die bin. 14-14-14 is too agressive, I'd say. Most performance benefits come from proper secondary and tertiary subtimings in this platform. 15-15-15 should be MUCH easier to stabilize. (No geardown mode for odd CAS latency, if not it'll default to 14 or 16)

Don't be afraid to go above 1.4v, B-die is resilient, its absolute maximum voltage according to the datasheet is 1.5v and some vendors are selling stupid fast DDR4-45xx kits at 1.45v out of the box. Just get some airflow over the sticks, you'll see the built in sensors not go much if at all above 40°C under torture testing which is excellent.

If you can't get it stable, forget about what the calculator says and try the timings in this post. You'll also probably need more vSOC, try 1.075-1.1v.


----------



## Darkomax

Synoxia said:


> Hello, im back at memory tweakings after updating my bios. What do you think i should realistically aim for with a 16gb 3600 cl17 Tridentz B-DIE kit? Is it worth going google test thing over HCI? I regret so much not buying 3200c14...


Mine can do 3200CL14 at 1.35v and 3333CL14 at 1.42v (not TridentZ but Galax with same specs), not working so far with 3466 whatever timings (IMC or MB limit, I'm on a B350 Gaming 3).
Advanced timings here.


----------



## Synoxia

Darkomax said:


> Mine can do 3200CL14 at 1.35v and 3333CL14 at 1.42v (not TridentZ but Galax with same specs), not working so far with 3466 whatever timings (IMC or MB limit, I'm on a B350 Gaming 3).
> Advanced timings here.


Yo, look at this, does it look good? 1.43 ram voltage, anything else i can tweak? 3466 c14 seems nope for my kit (3600 c17 tridentz) but seems like it likes 3333


----------



## Darkomax

Seems good. I can't do 3466 either but it's a motherboard or IMC limit (or a memory hole but I have no idea how to fix it, well I know how but I'm not willing to spend the time to find out). 3333CL14 is pretty fast already. I heard new memory multipliers are coming in new BIOSes, so I may try 3400MHz when it comes.


----------



## n1njamn

Hey guys, maybe one of you more knowledgeable than myself can help me get my 3200 cl 15 corsair vengeance stable with my ryzen 1600x. I use the ryzen master software to overclock the cpu to 4.05ghz and to get the ram up to its rated 3200. This would be all well and good but the it's not stable. Most of the time(not all) when I restart the computer it has to boot several times before finally starting. Is it possible for me to add voltage or something in the bios? Or maybe even tighten the timings? I am using a AsRock killer sli x370 motherboard. Thanks for any and all help guys!!!


----------



## seanpatrick

n1njamn said:


> Hey guys, maybe one of you more knowledgeable than myself can help me get my 3200 cl 15 corsair vengeance stable with my ryzen 1600x. I use the ryzen master software to overclock the cpu to 4.05ghz and to get the ram up to its rated 3200. This would be all well and good but the it's not stable. Most of the time(not all) when I restart the computer it has to boot several times before finally starting. Is it possible for me to add voltage or something in the bios? Or maybe even tighten the timings? I am using a AsRock killer sli x370 motherboard. Thanks for any and all help guys!!!


I spent hours and hours with any and all combinations of settings trying to get 3200 stable with Corsair LPX 3200 & the Asrock x370 Killer SLI. Best I could do was 3066 stable on the second-last bios. I ended up selling it for an MSI Arctic Mortar B350 MATX (an aesthetic choice) and much to my surprise it booted up first time @ 3200 and is stable after testing.


----------



## n1njamn

damn, Thanks a lot for the reply though. Maybe i'll just deal with inconsistent boot ups , that or just leave my system on sleep all the time.


----------



## Synoxia

Does 1 hour GSAT imply that you are rock solid?


----------



## hsn

hsn--1300x @3.9ghz---3733Mhz-C18-18-18-38-1T---1.4v---SOC 1.15v---BIOS f20----Stressapptest---1 Hour--Galax 3600 c17


----------



## Darkomax

hsn said:


> hsn--1300x @3.9ghz---3733Mhz-C18-18-18-38-1T---1.4v---SOC 1.15v---BIOS f20----Stressapptest---1 Hour--Galax 3600 c17


Amazing. What motherboard?
I would try 3600C16 or 3466C14/C15, it'd probably be faster than 3733C18 in real use cases.


----------



## hsn

Darkomax said:


> Amazing. What motherboard?
> I would try 3600C16 or 3466C14/C15, it'd probably be faster than 3733C18 in real use cases.


i user gigabyte b350 itx
actually i can boot on 3800 but still need time to test


----------



## kivikas14

[email protected] 1.01875v---BIOS 3502---HCI---900%


----------



## Contagion

What's some good low profile B die sets? I have a petg tube going right over the DIMM slots.

Right now I'm using some old LPX sticks, not RGB. They fit fine.


----------



## Shaav

I heard these come with B-Die chips:
https://www.innodisk.com/en/products/dram-module/embedded/Embedded_VLP_DDR4_LONG_DIMM


----------



## The Sandman

Contagion said:


> What's some good low profile B die sets? I have a petg tube going right over the DIMM slots.
> 
> Right now I'm using some old LPX sticks, not RGB. They fit fine.


If it's of any help my GSkill Flare-X mounted in position with their HS's in place measure 1 1/2" (38.1mm) above the top of the empty memory slot (facing you) next to the one I measured.
I will also add that I found a .050" (1.27mm) difference in assembled height (on the mobo) and I used the taller of the two for my measurement. 

If nothing else you could use the Flare-X spec sheet along with this info and have a number to go from.
The 1.5" mentioned above would be an absolute minimum clearance. Probably no way to remove or install memory. With OD of petg at this distance be sure to add clearance as needed if wanted.


----------



## Kayant

User: Kayant
CPU: 1600 @ 3.9Ghz
Mobo: ASRock Fatal1ty AB350 Gaming-ITX/ac
Speed: 3200-16-17-17-38-1T @ 1.4V
SOC: 1.087V
BIOS: P3.40
Model: Gskill f4-3000c15d-16gvrb
Test: Stressapptest 10008 seconds + RamTest 6 Hours/8211%


----------



## Mech0z

If Dual rank is still preferred for Ryzen (I will be getting Ryzen+), do you guys think I can trust that this is Dual rank when they list it in specifications https://www.alzashop.com/corsair-16gb-kit-ddr4-3000mhz-cl15-vengeance-lpx-black-d4121236.htm I just havent seen other shops list directly what rank they are

Configuration
Dual Rank

PS: I would love Flare-X but I am using a Noctua D15 + Fractal Define C which gives me a max memory height of 37mm


----------



## miklkit

Move that front fan to the back tower and then remove the rear case exhaust fan and cut a big gaping hole in the back of the case. It is especially important to remove the rear I/O panel for vrm air flow.


----------



## tfran1990

im new to the forum and have some questions.

My ram kit is F4-3400C16D-32GTZ
Trident Z 16Gx2 
the XMP profile says 3400Mhz @ 16-16-16-36 1.35V
my mobo is the AUSU CH6

i would like to take advantage of the infinity fabric gain from having fast ram.

using the most current BIOS, currently im able to get stable at 2933 14-16-16-32 1.38v SOC 1.00 this is with my ryzen 1700x at stock speeds and voltage


i think im misunderstanding how the xmp profile works.selecting the 3400 as XMP should work with a little voltage bump, right?
even if i go into the BIOS set the dropdown to 3400 and set the timings manul to 16-16-16-36 i still can get a boot. even with a voltage bump.

i have looked at alot of the charts for ram timings, i seee some kits that have almost the same model number. should i be able to get almost the same settings as a ram kit with a simular model number?

is there anyone with this kit that is able to get in the 3Ghz range, is so how was it done?

is ryzen master a good tool to use?

is 2933 a good starting point with this kit?

is it harder to achave a fast ram overclock with big kits?(16Gx2 VS. 4Gx2)

based on a post from the ryzen memory ic collection 
"In general (on Ryzen) you can expect up to 3466 MHz (without BCLK-OC) with Samsung B-Die (on AGESA 1.0.0.6+ Bios Versions), up to 2933 MHz (without BCLK-OC) with Samsung D/E/S-Die (AGESA 1.0.0.5+). Hynix A/M-Die are mostly working @ 3200 MHz with AGESA 1.0.0.5+. Do note that Dual Rank RAM is faster than Single Rank. E.g. 2933 MHz Dual Rank is faster than 3200 MHz Single Rank. Single/Dual Rank is not to be confused with Single/Dual Channel (Dual Channel is always better)."

it looks as if i have a solid kit of ram, its smasung B die dual rank. i must be doing something wrong...


----------



## ZeNch

tfran1990 said:


> im new to the forum and have some questions.
> 
> My ram kit is F4-3400C16D-32GTZ
> Trident Z 16Gx2
> the XMP profile says 3400Mhz @ 16-16-16-36 1.35V
> my mobo is the AUSU CH6
> 
> i would like to take advantage of the infinity fabric gain from having fast ram.
> 
> using the most current BIOS, currently im able to get stable at 2933 14-16-16-32 1.38v SOC 1.00 this is with my ryzen 1700x at stock speeds and voltage
> 
> 
> i think im misunderstanding how the xmp profile works.selecting the 3400 as XMP should work with a little voltage bump, right?
> even if i go into the BIOS set the dropdown to 3400 and set the timings manul to 16-16-16-36 i still can get a boot. even with a voltage bump.
> 
> i have looked at alot of the charts for ram timings, i seee some kits that have almost the same model number. should i be able to get almost the same settings as a ram kit with a simular model number?
> 
> is there anyone with this kit that is able to get in the 3Ghz range, is so how was it done?
> 
> is ryzen master a good tool to use?
> 
> is 2933 a good starting point with this kit?
> 
> is it harder to achave a fast ram overclock with big kits?(16Gx2 VS. 4Gx2)
> 
> based on a post from the ryzen memory ic collection
> "In general (on Ryzen) you can expect up to 3466 MHz (without BCLK-OC) with Samsung B-Die (on AGESA 1.0.0.6+ Bios Versions), up to 2933 MHz (without BCLK-OC) with Samsung D/E/S-Die (AGESA 1.0.0.5+). Hynix A/M-Die are mostly working @ 3200 MHz with AGESA 1.0.0.5+. Do note that Dual Rank RAM is faster than Single Rank. E.g. 2933 MHz Dual Rank is faster than 3200 MHz Single Rank. Single/Dual Rank is not to be confused with Single/Dual Channel (Dual Channel is always better)."
> 
> it looks as if i have a solid kit of ram, its smasung B die dual rank. i must be doing something wrong...



Do you try with Ryzen calculator settings? 

http://www.overclock.net/forum/13-amd-general/1640919-ryzen-dram-calculator-1-0-0-beta-overclocking-dram-am4.html

Try with latest update of BIOS


----------



## tfran1990

no i did not but thank you for pointing me in the right direction. i will go check it out.


----------



## 010101

Any why a hynix m die dual rank kit ? i have this kit 

https://gskill.com/en/product/f4-3200c16d-32gtzsw

But no lock hiting more of 2933mhz i hava a taichi.


----------



## os2wiz

Dual rank, single rank these debates constantly are argued with each bios change. But no one is addressing the really Big issue. With the latest 1.11 agesa code release from AMD while memory compatibility has increased Memory Performance has markedly decreasedfrom 8 to 10% from agesa code 1.07. This is Not an acceptable trade off. My Cinebench 15 Open GLscores have dropped from 128-131 fps to 117 fps. All memory optimizations in bios were performed with step by step tweaking of each timing. This is SIMPLY NOT ACCEPTABLE.AMD is throwing away performance to get more people to higher memory speeds. It is completely assinine in my opinion.


----------



## sideeffect

os2wiz said:


> Memory Performance has markedly decreased from 8 to 10% from agesa code 1.07.


I just tested Cinebench OpenGL and it seems very inconsistent to me. I didn't get the same score twice the fluctuation in scores between highest and lowest was around 10%. 

Why would you base your systems memory performance on that benchmark which seems inconsistent and more GPU related than system Memory related? For me there was no real difference in benchmark scores between AGESA 1071 and AGESA 1000a.


----------



## os2wiz

sideeffect said:


> I just tested Cinebench OpenGL and it seems very inconsistent to me. I didn't get the same score twice the fluctuation in scores between highest and lowest was around 10%.
> 
> Why would you base your systems memory performance on that benchmark which seems inconsistent and more GPU related than system Memory related? For me there was no real difference in benchmark scores between AGESA 1071 and AGESA 1000a.



The variation from one run versus anothr with same bios and hardware is about 3 to 4% not 10%. I was consistently at 126fps up to 131 fps with the same hardware I have now the only difference is bios since 1.007 agesa up to 1.100 agesa curently. Now I can only get 114 fps to 117 fps. So your hypothesis does NOT stand up to the light of day.


----------



## sideeffect

os2wiz said:


> The variation from one run versus anothr with same bios and hardware is about 3 to 4% not 10%. I was consistently at 126fps up to 131 fps with the same hardware I have now the only difference is bios since 1.007 agesa up to 1.100 agesa curently. Now I can only get 114 fps to 117 fps. So your hypothesis does NOT stand up to the light of day.


I did a quick video test as I have to go to work. 

highest 108.20
Lowest 98.25
Difference 10%

Small overhead due to recording. Memory is running at 3000Mhz.


----------



## os2wiz

sideeffect said:


> I did a quick video test as I have to go to work.
> 
> highest 108.20
> Lowest 98.25
> Difference 10%
> 
> Small overhead due to recording. Memory is running at 3000Mhz.
> 
> https://www.youtube.com/watch?v=04acn_0nBgI&feature=youtu.be


I run my memory at rated speed of 3200mhz, but have tightened timings of 14-13-13-13-32. It passes 3 runs of scrunch stability stress test. Your.scores for fps are very low even forvddr4 3000 on cinebench15 what cup are you using? I am at 3.925 GHZ on a Ryzen 1800X. I have had my Ryzen setup since March of 2017. My scores started going down with me bioses since about 8 days ago.


----------



## harrysun

os2wiz said:


> My scores started going down with me bioses since about 8 days ago.


Sounds like the operating system hasn't been changed in any other way since March 2017? The results are within the range of measurement accuracy. With synthetic tests we are not well advised to conclude a deterioration.


----------



## Kayant

Has anyone comes across this behaviour before?

I recently discovered running Linx for sometime(Usually I go with 25m) then running GSAT right after I end up getting errors but not with a straight of GSAT without running anything prior. 

I know any error related to memory is bad but at least in terms of visible stability things are pretty stable with all the settings i have tested using that procedure. Stock 2133Mhz also has errors when using that procedure.

Any clue has to why this might happen? I am going to try a long run of GSAT to see if errors come up then.


----------



## os2wiz

harrysun said:


> Sounds like the operating system hasn't been changed in any other way since March 2017? The results are within the range of measurement accuracy. With synthetic tests we are not well advised to conclude a deterioration.



You are incorrect. Others have reported the same issue.Even the guy who first doubted me when he posted his scores, it is evident that he is also suffering unusually poor performance with the agesa coded bioses after 1.007. A 10 % decline in open GL scores on cinebench is NOT within normal parameters. I have been through this with the other newbie. I will not repeat the data again. Read please!


----------



## harrysun

os2wiz said:


> You are incorrect. Others have reported the same issue.Even the guy who first doubted me when he posted his scores, it is evident that he is also suffering unusually poor performance with the agesa coded bioses after 1.007. A 10 % decline in open GL scores on cinebench is NOT within normal parameters. I have been through this with the other newbie. I will not repeat the data again. Read please!


So why do you not downgrade if an older version is better? We do update the BIOS because of an issue or because in hoppe of an improvement. If not, go back to your lovely version and be happy. Or why did you upgrade?


----------



## sideeffect

os2wiz said:


> I run my memory at rated speed of 3200mhz, but have tightened timings of 14-13-13-13-32. It passes 3 runs of scrunch stability stress test. Your.scores for fps are very low even forvddr4 3000 on cinebench15 what cup are you using? I am at 3.925 GHZ on a Ryzen 1800X. I have had my Ryzen setup since March of 2017. My scores started going down with me bioses since about 8 days ago.


I had the same score with AGESA 1071. The scores are similar to identical system the GPU does not boost with this benchmark. 

If the BIOS is really 8-10% slower why is this slowness not showing up in game or system benchmarks other than this one? 

This benchmark seems pretty bad to me it is not consistent with scores, uses only 6 threads with only 1 core heavily utilised and even that not fully, the GPU is barely utilised (30%) and it downclocks.


----------



## 010101

harrysun said:


> So why do you not downgrade if an older version is better? We do update the BIOS because of an issue or because in hoppe of an improvement. If not, go back to your lovely version and be happy. Or why did you upgrade?


You cant donwgrade an agesa version....


----------



## Anty

Of course you can...


----------



## Dr. Vodka

010101 said:


> You cant donwgrade an agesa version....


The C6H can downgrade to any previous version thanks to its flashback functionality. Other boards could give you issues trying to do that.


----------



## 010101

OK my bad... 

Enviado desde mi Redmi Note 4 mediante Tapatalk


----------



## sideeffect

Until it can be demonstrated the new AGESA is negatively effecting performance I am unconvinced. The burden to prove that is also on the person making the claim with multiple proper comparison benchmarks that can be verified by other users not just an isolated instance which could just as easily be caused by a Windows update, Driver update, Power plan, OpenGL etc.


----------



## datspike

[email protected] 1.125v---BIOS 6001---HCI---400%---F4-3600C15D-16GTZ
Also tested with TestMem5 (20 cycles) - passed.
https://valid.x86.fr/596vai


Spoiler























upd.
Unstable in games, will update with 3533C14 configuration


----------



## MrPhilo

Does running a higher overclocked effect the RAM stability?

For example 4.05Ghz, Safe Timing 3333Mhz

If I downclock to 4.0Ghz, would I be able to go for Fast Timing for 3333Mhz?


----------



## coreykill99

so playing around the last few days I started pushing the timings down on my kit. this is about where I ended up im sure it can go much further. most notable to me though is running aide mem bench. the other day I got a latency of 70.6 I have it in the screencap. but today its fallen well back to 73.6 I have old screencaps of latency @ 66.1 on looser timings any ideas on why for that one? also having a hell of a time getting anything other than the 3200 strap to run with any sort of stability. closest I have seen to 3333 stable is ~1200% in ramtest. I played with it for 3 days straight trying to get something. anything at all stable @ 3333 it just didnt want to for me. kinda losing patience with it. Any Tips?
Running Gskill F4-3200C14D-16GTZKO @ 1.37V SOC @ 1.025V


----------



## The Sandman

MrPhilo said:


> Does running a higher overclocked effect the RAM stability?
> 
> For example 4.05Ghz, Safe Timing 3333Mhz
> 
> If I downclock to 4.0Ghz, would I be able to go for Fast Timing for 3333Mhz?


Taking it for granted it will not run fast timing currently
It may work out that way but my guess would be if you can't run it at 4.05MHz than dropping to only 4.0GHz will probably not be enough of a drop.
Without knowing your current settings and what fails etc it's to hard to guess.
I tightened my Flare-X at 3466MHz to 14-13-13-26-44-1T but required added Dram, SOC and Vcore to fully stabilize at 3925MHz.



coreykill99 said:


> so playing around the last few days I started pushing the timings down on my kit. this is about where I ended up im sure it can go much further. most notable to me though is running aide mem bench. the other day I got a latency of 70.6 I have it in the screencap. but today its fallen well back to 73.6 I have old screencaps of latency @ 66.1 on looser timings any ideas on why for that one? also having a hell of a time getting anything other than the 3200 strap to run with any sort of stability. closest I have seen to 3333 stable is ~1200% in ramtest. I played with it for 3 days straight trying to get something. anything at all stable @ 3333 it just didnt want to for me. kinda losing patience with it. Any Tips?
> Running Gskill F4-3200C14D-16GTZKO @ 1.37V SOC @ 1.025V


Disable GearDownMode and retest (stability too).
I also Disable PowerDownMode

Memory Hole perhaps? 
Have you tried 3466 strap?
Sorry but this NEW IMPROVED site upgrade doesn't allow me to attach a PNG or even a bios text file anymore to show timings I use (slightly different than yours)


----------



## Darkstalker420

Hey OC.net. Running an R7 1700 ASUS Strix B350 F - Gaming (BIOS 3803) along with some Corsairs CMK16GX4M2B3600C18 Vengeance LPX 16GB (B - Die). From the off i could run 3200Mhz using D.O.C.P. profile (though it got me some "nasty" timings like 620 Trfc!! as it was for 3600Mhz operation). This was fine UNTIL..... I flashed from 1001 BIOS to the newer 3xxx BIOS. Since then my rig has suffered from ramdom BSOD's (memory_management) and firefox tabs keep crashing. Just stupid things tbh. Fallout 4 CTD's are another one.

Before the BIOS update i could pass 10 loops of IBT AVX on HIGH (2048mb) but now it will error out on the second pass EVERYTIME! I then started to tune the timings using The Stilts "safe" 3200 preset and the following:

ProcODT 53.
DRAM 1.36v (been upto 1.40v and didn't help tbh).
SoC is on AUTO (1.1V)
VCore on AUTO (says 1.340v in BIOS though does go up/down as needed).
LLC all on AUTO for everything.
Geardown OFF.
1T.

RTT NOM RZQ/7 (34).
RTT WR OFF.
RTT PARK RZQ/5 (48).

CAD_BUS are all 20 20 20 20.
CLDO_VDDP 700
Interleave set to Channel.

Using the settings above i can now get Memtest86 (USB Boot) to work for over an hour with no errors. Before the settings above it would start to get errors around the 27 min area (about 7 errors then i would stop it). Have to be honest i upgraded from an AM2 PhII X6 rig so most of what i'm seeing to "tweak" in the BIOS might as well be a foreign language LMAO!! I'm happy at 3200Mhz but want to get stability tbh as i can't depend on this rig 100% as it will still do "funny stuff" as it feels like.

Sadly getting stress test stable does seem out of my reach as i don't really have the knowledge to "tweak" out the instability as the usual slackening of timings/raising V's hasn't helped me with this. Tried Memtest64 also but that errors out anything from 40 second onward (sometimes lasts a few mins others not). So just wondered if anyone could offer some advice regarding gaining "real" stability. Any advice would be very helpful as going from AM2 to AM4 has left me feeling a little "shellshocked" LMAO!! If you need to know anything else please do ask.

**EDIT** 

During a 10 loop (MAX) MemTest64 (through up an error on loop 10!) i monitored the voltages with HWINFO and spotted the following during the stresstest:

CPU Core (average)= 1.088v (max)= 1.375v.
SoC (average)= 1.085v (max)= 1.094v.


Thanx.


----------



## tfran1990

EDIT nvm i see what i did wrong.

ok so i got my ram to 3200. my question is how important is the cpu z single and multi thread score?

im at 3200 16-16-16-36 and my "score" is lower then if i had my ram clocked to 2933 with 14-16-16-32.

tight timings are always going to show better score. From what i read the Ryzen has better performance with higher frequency, correct? 

would 3200 at 14-16-16-32 be even better if i can get it there?


----------



## christoph

the new agesa update is less stable in memory than the previous..


but my question is, how do I know what procODT is my motherboard setting at AUTO, or how can I read it in windows to know what setting set by the motherboard?


----------



## ZeNch

christoph said:


> the new agesa update is less stable in memory than the previous..
> 
> 
> but my question is, how do I know what procODT is my motherboard setting at AUTO, or how can I read it in windows to know what setting set by the motherboard?


You can't.
Need to test with common ProcODT settings 48/53/60 certain Rams need 80 but I don't know what model.

Try with dram calculator for Ryzen.
http://www.overclock.net/forum/13-amd-general/1640919-ryzen-dram-calculator-1-0-0-beta-2-overclocking-dram-am4.html


----------



## christoph

yeah I'm testing at 60 right now


----------



## Kayant

Kayant said:


> Has anyone comes across this behaviour before?
> 
> I recently discovered running Linx for sometime(Usually I go with 25m) then running GSAT right after I end up getting errors but not with a straight of GSAT without running anything prior.
> 
> I know any error related to memory is bad but at least in terms of visible stability things are pretty stable with all the settings i have tested using that procedure. Stock 2133Mhz also has errors when using that procedure.
> 
> Any clue has to why this might happen? I am going to try a long run of GSAT to see if errors come up then.


Little update after doing multiple test I feel GSAT through Windows 10(Ubuntu) is unreliable after multiple runs results seem to be inconsistent from time to time. Ultimately having done test with other programs including HCI/Techpowerup memtest/Ram test/offline memtest86/the same GSAT(But a a native Linux mint install) 3 hour run reporting it as stable. Windows GSAT has been the only outliner so far.


----------



## 1usmus

*Ryzen DRAM Calculator 1.0.0 Beta 3 (overclocking DRAM on AM4)​*









http://www.overclock.net/forum/13-a...lator-1-0-0-beta-3-overclocking-dram-am4.html​


----------



## MrPhilo

Sorry for being off topic

Does anyone have G SKill TridentZ RGB 4266 CL19 spd dump file for me to restore please? It's file format has to be .spd, not .thp (Thaiphoon burner)

My 2 stick have error and I need the .spd to restore it!

Thanks


----------



## Spectre73

christoph said:


> the new agesa update is less stable in memory than the previous..
> 
> 
> but my question is, how do I know what procODT is my motherboard setting at AUTO, or how can I read it in windows to know what setting set by the motherboard?


Ryzen Master shows it in the new version!


----------



## Leftezog

What is the best bios for stable high frequency/low latency memory overclocking? I'm at 3502 and I have a bit trouble trying to get my ram stable above 3200c14. My kit is tridentz rgb 3600c16.


----------



## christoph

Spectre73 said:


> Ryzen Master shows it in the new version!


thanks, I'll give it a go


----------



## The Sandman

Leftezog said:


> What is the best bios for stable high frequency/low latency memory overclocking? I'm at 3502 and I have a bit trouble trying to get my ram stable above 3200c14. My kit is tridentz rgb 3600c16.


1701/9920 or 6001 IMHO.
I've had my Flare-X (B-Die) at 3466 14-13-13-26-44-1T up till 6001.
On 9920 ran 1600% HCI stable without issue.

Not saying I won't go back (I haven't given up yet) but this new Agesa is a PITA.
If you have B-Die and don't feel like playing for hours go with 1701/9920/3502.
Any other go with with 6001.
I don't see any performance gains with memory with 6001 (compared to my previous B-Die settings), in fact I still have not matched them.
I've been trying all weekend to even semi stabilize 14-13-13 GearDownMode Enabled as before with zero luck so far.

I did come across this from a while back if its of any help http://www.overclock.net/forum/26326957-post26508.html


----------



## Leftezog

The Sandman said:


> 1701/9920 or 6001 IMHO.
> I've had my Flare-X (B-Die) at 3466 14-13-13-26-44-1T up till 6001.
> On 9920 ran 1600% HCI stable without issue.
> 
> Not saying I won't go back (I haven't given up yet) but this new Agesa is a PITA.
> If you have B-Die and don't feel like playing for hours go with 1701/9920/3502.
> Any other go with with 6001.
> I don't see any performance gains with memory with 6001 (compared to my previous B-Die settings), in fact I still have not matched them.
> I've been trying all weekend to even semi stabilize 14-13-13 GearDownMode Enabled as before with zero luck so far.
> 
> I did come across this from a while back if its of any help http://www.overclock.net/forum/26326957-post26508.html


I have a big concern that my memory isn't good enough for 3466c14 cause at typhoon burner the primary timings ns is 8.869ns each and not 8.750ns as I see in other b-die kits. I have trident z rgb 3600c16 b-die kit but I believe that rgb kits are worse in performance versus the non rgb kits. I use my computer for mainly for gaming but you know I also want to achive the best overclock possible from cpu/ram/gpu just for fun  So for gaming you suggest earlier bios from 3502 like 1701/9920?


----------



## The Sandman

Leftezog said:


> I have a big concern that my memory isn't good enough for 3466c14 cause at typhoon burner the primary timings ns is 8.869ns each and not 8.750ns as I see in other b-die kits. I have trident z rgb 3600c16 b-die kit but I believe that rgb kits are worse in performance versus the non rgb kits. I use my computer for mainly for gaming but you know I also want to achive the best overclock possible from cpu/ram/gpu just for fun  So for gaming you suggest earlier bios from 3502 like 1701/9920?


If it were me I'd consider giving 6001 a quick try. It didn't help my set up at all (F4-3200C14D-16GFX) and am currently back on 3502.
IIRC I have read some are able to run 3600MHz on 6001. This was not possible before as far as I know.

RGBs have nothing to do with performance. Both RGB and non RGB kits use the same chips. You simply have c16 and not c14.

Had any luck running D.O.C.P.?
I don't recall seeing what you've already tried.

If 3600MHz isn't happening on 6001 I'd probably just stay on 3502.
For me memory wise 1701/9920 and 3502 are close to the same. 3008 high lat.
They all have pros and cons but earlier versions usually use slightly less voltage.


----------



## tfran1990

EDIT wrong place


----------



## Leftezog

The Sandman said:


> If it were me I'd consider giving 6001 a quick try. It didn't help my set up at all (F4-3200C14D-16GFX) and am currently back on 3502.
> IIRC I have read some are able to run 3600MHz on 6001. This was not possible before as far as I know.
> 
> RGBs have nothing to do with performance. Both RGB and non RGB kits use the same chips. You simply have c16 and not c14.
> 
> Had any luck running D.O.C.P.?
> I don't recall seeing what you've already tried.
> 
> If 3600MHz isn't happening on 6001 I'd probably just stay on 3502.
> For me memory wise 1701/9920 and 3502 are close to the same. 3008 high lat.
> They all have pros and cons but earlier versions usually use slightly less voltage.


I have ch6 wifi and 6001 bios isn't out yet. ? So I'm stucked at 3502. I am testing now 3333 c14 and it seems stable in games and everything I do but even though it passed ramtest tester at 2700+% it gave me and error in hci memtest at around 300%. I read that some have errors with Trident z memory when they reach about 50°c but I can't check this variable because my Trident rgb kit don't have thermal sensors. Now that search feature in site works I can search better and find solutions for testing. It was imposible to read all the comments before and search something so I will continue testing and report back. ?


----------



## datspike

When I was trying to run AIDA benchmark on 3733C14 config I needed 1.2 vSOC to get it to pass the benchmark, and this is considered to be the max safe voltage on the memory controller.
The thing is after seeing Raven APU's overclocked to 1600-1700Mhz on gpu core with something like 1.3-1.4 vSOC I'm generally confused about how people even have their cpu imc not degraded yet.
Interesting if the Raven imc is just more resistant to higher voltage then ryzen 1xxx imc or 1.2 is not the limit? What are your thoughts guys?


----------



## Nighthog

datspike said:


> When I was trying to run AIDA benchmark on 3733C14 config I needed 1.2 vSOC to get it to pass the benchmark, and this is considered to be the max safe voltage on the memory controller.
> The thing is after seeing Raven APU's overclocked to 1600-1700Mhz on gpu core with something like 1.3-1.4 vSOC I'm generally confused about how people even have their cpu imc not degraded yet.
> Interesting if the Raven imc is just more resistant to higher voltage then ryzen 1xxx imc or 1.2 is not the limit? What are your thoughts guys?


As far as I was concerned the issue was with Asus ROG boards not being able to handle more than 1.2vSoC in the beginnings. It fried or corrupted something else on the board if I recall correctly. There hasn't been "reports" of dead things as far I'm concerned for other board makers. Though I haven't seen people really push further than 1.2vSoC since the issues came about for Asus. It became like it was a issue for all boards/chips although as far as I know untested. 
But I've not really seen any need to go that high on vSoC for anyone really. 1.15V seems about the most people need.


----------



## datspike

Nighthog said:


> 1.15V seems about the most people need.


I was asking because I can boot 3733C14 on 1.2V SOC and that voltage seems to be the only thing which makes the configuration stable on such high clocks.
Guess I'll try hitting those on Ryzen 2xxx


----------



## Leftezog

Guys I had a stable ram profile in bios, checking it with ram testers and be stable at everything, heavy gaming, simple tasks browsing, everything. I have my ram at 3333Mhz C14 with CAD_BUS values at auto, after I mess a bit with CAD_BUS values so to have them stable in one value and not let the mobo set them. After some testing setting values to 20,20,2020 - 30,30,30,30 - 20,20,30,30 and 30,30,40,60 the ram was giving errors in ram testers. After I done testing I loaded back my stable profile in bios which typically the only difference it had was CAD_BUS values at auto. And guess what. Runned memtest from curiocity again and it gave me again errors. How is this even possible? I'm very confused because this isn't the only time that it happened to me. My bios settings are the above:



Spoiler



[2018/03/05 23:40:16]
Ai Overclock Tuner [Manual]
BCLK Frequency [100.0000]
BCLK_Divider [Auto]
Custom CPU Core Ratio [Auto]
> CPU Core Ratio [39.00]
Performance Bias [None]
Memory Frequency [DDR4-3333MHz]
Core Performance Boost [Disabled]
SMT Mode [Enabled]
EPU Power Saving Mode [Disabled]
TPU [Keep Current Settings]
CPU Core Voltage [Manual mode]
- CPU Core Voltage Override [1.40000]
CPU SOC Voltage [Manual mode]
- VDDSOC Voltage Override [1.07500]
DRAM Voltage [1.39500]
1.8V PLL Voltage [1.80000]
1.05V SB Voltage [1.05000]
Target TDP [Auto]
TRC_EOM [Auto]
TRTP_EOM [Auto]
TRRS_S_EOM [Auto]
TRRS_L_EOM [Auto]
TWTR_EOM [Auto]
TWTR_L_EOM [Auto]
TWCL_EOM [Auto]
TWR_EOM [Auto]
TFAW_EOM [Auto]
TRCT_EOM [Auto]
TREFI_EOM [Auto]
TRDRD_DD_EOM [Auto]
TRDRD_SD_EOM [Auto]
TRDRD_SC_EOM [Auto]
TRDRD_SCDLR_EOM [Auto]
TRDRD_SCL_EOM [Auto]
TWRWR_DD_EOM [Auto]
TWRWR_SD_EOM [Auto]
TWRWR_SC_EOM [Auto]
TWRWR_SCDLR_EOM [Auto]
TWRWR_SCL_EOM [Auto]
TWRRD_EOM [Auto]
TRDWR_EOM [Auto]
TWRRD_SCDLR_EOM [Auto]
Mem Over Clock Fail Count [2]
DRAM CAS# Latency [14]
DRAM RAS# to CAS# Read Delay [14]
DRAM RAS# to CAS# Write Delay [14]
DRAM RAS# PRE Time [14]
DRAM RAS# ACT Time [28]
Trc [42]
TrrdS [4]
TrrdL [6]
Tfaw [16]
TwtrS [4]
TwtrL [12]
Twr [10]
Trcpage [Auto]
TrdrdScl [2]
TwrwrScl [2]
Trfc [312]
Trfc2 [192]
Trfc4 [132]
Tcwl [14]
Trtp [6]
Trdwr [6]
Twrrd [3]
TwrwrSc [1]
TwrwrSd [7]
TwrwrDd [7]
TrdrdSc [1]
TrdrdSd [5]
TrdrdDd [5]
Tcke [1]
ProcODT [68.6 ohm]
Cmd2T [2T]
Gear Down Mode [Disabled]
Power Down Enable [Disabled]
RttNom [RZQ/7]
RttWr [RZQ/3]
RttPark [RZQ/1]
MemAddrCmdSetup_SM [Auto]
MemCsOdtSetup_SM [Auto]
MemCkeSetup_SM [Auto]
MemCadBusClkDrvStren_SM [20.0 Ohm]
MemCadBusAddrCmdDrvStren_SM [20.0 Ohm]
MemCadBusCsOdtDrvStren_SM [20.0 Ohm]
MemCadBusCkeDrvStren_SM [20.0 Ohm]
VTTDDR Voltage [Auto]
VPP_MEM Voltage [Auto]
DRAM CTRL REF Voltage on CHA [Auto]
DRAM CTRL REF Voltage on CHB [Auto]
VDDP Voltage [0.90000]
VDDP Standby Voltage [0.90000]
1.8V Standby Voltage [Auto]
CPU 3.3v AUX [Auto]
2.5V SB Voltage [Auto]
DRAM R1 Tune [Auto]
DRAM R2 Tune [Auto]
DRAM R3 Tune [Auto]
DRAM R4 Tune [Auto]
PCIE Tune R1 [Auto]
PCIE Tune R2 [Auto]
PCIE Tune R3 [Auto]
PLL Tune R1 [Auto]
PLL reference voltage [Auto]
T Offset [Auto]
Sense MI Skew [Auto]
Sense MI Offset [Auto]
Promontory presence [Auto]
Clock Amplitude [Auto]
CLDO VDDP voltage [Auto]
CPU Load-line Calibration [Level 3]
CPU Current Capability [130%]
CPU VRM Switching Frequency [Manual]
CPU Voltage Frequency [300]
CPU Power Duty Control [T.Probe]
CPU Power Phase Control [Power Phase Response]
Manual Adjustment [Ultra Fast]
CPU Power Thermal Control [120]
VDDSOC Load-line Calibration [Level 3]
VDDSOC Current Capability [120%]
VDDSOC Switching Frequency [Manual]
Fixed VDDSOC Switching Frequency(KHz) [300]
VDDSOC Phase Control [Power Phase Response]
Manual Adjustment [Ultra Fast]
DRAM Current Capability [130%]
DRAM Power Phase Control [Extreme]
DRAM Switching Frequency [Manual]
Fixed DRAM Switching Frequency(KHz) [300]
DRAM VBoot Voltage [1.40000]
Security Device Support [Enable]
TPM Device Selection [Discrete TPM]
Erase fTPM NV for factory reset [Enabled]
PSS Support [Auto]
NX Mode [Enabled]
SVM Mode [Enabled]
PT XHCI GEN1 [Auto]
PT XHCI GEN2 [Auto]
PT USB Equalization4 [Auto]
PT USB Redriver [Auto]
PT PCIE PORT 0 [Auto]
PT PCIE PORT 1 [Auto]
PT PCIE PORT 2 [Auto]
PT PCIE PORT 3 [Auto]
PT PCIE PORT 4 [Auto]
PT PCIE PORT 5 [Auto]
PT PCIE PORT 6 [Auto]
PT PCIE PORT 7 [Auto]
PT SATA PORT 0 Enable [Auto]
PT SATA PORT 1 Enable [Auto]
PT SATA PORT 2 Enable [Auto]
PT SATA PORT 3 Enable [Auto]
PT SATA PORT 4 Enable [Auto]
PT SATA PORT 5 Enable [Auto]
PT SATA PORT 6 Enable [Auto]
PT SATA PORT 7 Enable [Auto]
Onboard PCIE LAN PXE ROM [Enabled]
AMD CRB EHCI Debug port switch [Disabled]
Onboard LED [Enabled]
Hyper kit Mode [Disabled]
SATA Port Enable [Enabled]
SATA Mode [AHCI]
SMART Self Test [Enabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
ErP Ready [Disabled]
Restore On AC Power Loss [Power Off]
Power On By PCI-E/PCI [Disabled]
Power On By RTC [Disabled]
Super I/O Clock Skew [Auto]
HD Audio Controller [Enabled]
PCIEX4_3 Bandwidth [Auto]
PCIEX16_1 Mode [Auto]
PCIEX8_2 Mode [Auto]
PCIEX4_3 Mode [Auto]
M.2 Link Mode [Auto]
SB Link Mode [Auto]
Asmedia USB 3.1 Controller [Enabled]
When system is in working state [On]
In sleep, hibernate and soft off states [Off]
Intel LAN Controller [Enabled]
Intel LAN OPROM [Disabled]
Wi-Fi Controller [Enabled]
USB Type C Power Switch for USB3.1_E1 [Auto]
USB Type C Power Switch for USB3.1_EC2 [Auto]
Network Stack [Disabled]
Debug Port Table [Disabled]
Debug Port Table 2 [Disabled]
Device [OCZ-VERTEX3]
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
USB Mass Storage Driver Support [Enabled]
USB3.1_E1 [Auto]
USB3_1 [Enabled]
USB3_2 [Enabled]
USB3_3 [Enabled]
USB3_4 [Enabled]
USB3_5 [Auto]
USB3_6 [Auto]
USB3_7 [Auto]
USB3_8 [Auto]
USB3_9 [Auto]
USB3_10 [Auto]
USB2_11 [Auto]
USB2_12 [Auto]
USB2_13 [Auto]
USB2_14 [Auto]
USB_15 [Auto]
USB_16 [Auto]
CPU Temperature [Monitor]
MotherBoard Temperature [Monitor]
VRM Temperature [Monitor]
PCH Temperature [Monitor]
T_Sensor1 Temperature [Monitor]
CPU Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
Chassis Fan 3 Speed [Monitor]
W_PUMP+ Speed [Monitor]
CPU Optional Fan Speed [Monitor]
AIO_PUMP Speed [Monitor]
W_FLOW Speed [Monitor]
W_IN Temperature [Monitor]
W_OUT Temperature [Monitor]
CPU Core Voltage [Monitor]
3.3V Voltage [Monitor]
5V Voltage [Monitor]
12V Voltage [Monitor]
CPU Q-Fan Control [PWM Mode]
CPU Fan Smoothing Up/Down Time [0 sec]
CPU Fan Speed Lower Limit [200 RPM]
CPU Fan Profile [Silent]
W_PUMP+ Control [Disabled]
Chassis Fan 1 Q-Fan Control [Auto]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Smoothing Up/Down Time [0 sec]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 1 Profile [Standard]
Chassis Fan 2 Q-Fan Control [Auto]
Chassis Fan 2 Q-Fan Source [CPU]
Chassis Fan 2 Smoothing Up/Down Time [0 sec]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 2 Profile [Standard]
Chassis Fan 3 Q-Fan Control [Auto]
Chassis Fan 3 Q-Fan Source [CPU]
Chassis Fan 3 Smoothing Up/Down Time [0 sec]
Chassis Fan 3 Speed Low Limit [200 RPM]
Chassis Fan 3 Profile [Standard]
OnChip SATA Channel [Auto]
OnChip SATA Type [AHCI]
USB3_1 [Enabled]
USB3_2 [Enabled]
USB3_3 [Enabled]
USB3_4 [Enabled]
IR Config [RX & TX0 Only]
SdForce18 Enable [Disabled]
SD Mode configuration [AMDA]
Uart 0 Enable [Enabled]
Uart 1 Enable [Enabled]
I2C 0 Enable [Enabled]
I2C 1 Enable [Enabled]
I2C 2 Enable [Disabled]
I2C 3 Enable [Disabled]
GPIO Devices Support [Auto]
ESATA Port On Port 0 [Auto]
ESATA Port On Port 1 [Auto]
ESATA Port On Port 2 [Auto]
ESATA Port On Port 3 [Auto]
ESATA Port On Port 4 [Auto]
ESATA Port On Port 5 [Auto]
ESATA Port On Port 6 [Auto]
ESATA Port On Port 7 [Auto]
SATA Power On Port 0 [Auto]
SATA Power On Port 1 [Auto]
SATA Power On Port 2 [Auto]
SATA Power On Port 3 [Auto]
SATA Power On Port 4 [Auto]
SATA Power On Port 5 [Auto]
SATA Power On Port 6 [Auto]
SATA Power On Port 7 [Auto]
SATA Port 0 MODE [Auto]
SATA Port 1 MODE [Auto]
SATA Port 2 MODE [Auto]
SATA Port 3 MODE [Auto]
SATA Port 4 MODE [Auto]
SATA Port 5 MODE [Auto]
SATA Port 6 MODE [Auto]
SATA Port 7 MODE [Auto]
SATA Hot-Removable Support [Auto]
SATA 6 AHCI Support [Auto]
Int. Clk Differential Spread [Auto]
SATA MAXGEN2 CAP OPTION [Auto]
SATA CLK Mode Option [Auto]
Aggressive Link PM Capability [Auto]
Port Multiplier Capability [Auto]
SATA Ports Auto Clock Control [Auto]
SATA Partial State Capability [Auto]
SATA FIS Based Switching [Auto]
SATA Command Completion Coalescing Support [Auto]
SATA Slumber State Capability [Auto]
SATA MSI Capability Support [Auto]
SATA Target Support 8 Devices [Auto]
Generic Mode [Auto]
SATA AHCI Enclosure [Auto]
SATA SGPIO 0 [Auto]
SATA SGPIO 1 [Disabled]
SATA PHY PLL [Auto]
AC/DC Change Message Delivery [Disabled]
TimerTick Tracking [Auto]
Clock Interrupt Tag [Auto]
EHCI Traffic Handling [Disabled]
Fusion Message C Multi-Core [Disabled]
Fusion Message C State [Disabled]
SPI Read Mode [Auto]
SPI 100MHz Support [Auto]
SPI Normal Speed [Auto]
SPI Fast Read Speed [Auto]
SPI Burst Write [Auto]
I2C 0 D3 Support [Auto]
I2C 1 D3 Support [Auto]
I2C 2 D3 Support [Auto]
I2C 3 D3 Support [Auto]
I2C 4 D3 Support [Auto]
I2C 5 D3 Support [Auto]
UART 0 D3 Support [Auto]
UART 1 D3 Support [Auto]
UART 2 D3 Support [Auto]
UART 3 D3 Support [Auto]
SATA D3 Support [Auto]
EHCI D3 Support [Auto]
XHCI D3 Support [Auto]
SD D3 Support [Auto]
S0I3 [Auto]
Chipset Power Saving Features [Enabled]
SB Clock Spread Spectrum [Auto]
SB Clock Spread Spectrum Option [-0.375%]
HPET In SB [Auto]
MsiDis in HPET [Auto]
_OSC For PCI0 [Auto]
USB Phy Power Down [Auto]
PCIB_CLK_Stop Override [0]
USB MSI Option [Auto]
LPC MSI Option [Auto]
PCIBridge MSI Option [Auto]
AB MSI Option [Auto]
SB C1E Support [Auto]
SB Hardware Reduced Support [Auto]
GPP Serial Debug Bus Enable [Auto]
PSPP Policy [Auto]
Memory Clock [Auto]
Bank Interleaving [Enabled]
Channel Interleaving [Enabled]
Memory Clear [Disabled]
Fast Boot [Enabled]
Next Boot after AC Power Loss [Normal Boot]
Boot Logo Display [Auto]
POST Delay Time [3 sec]
Boot up NumLock State [Enabled]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Enabled]
Interrupt 19 Capture [Disabled]
Setup Mode [Advanced Mode]
Launch CSM [Enabled]
Boot Device Control [UEFI and Legacy OPROM]
Boot from Network Devices [Legacy only]
Boot from Storage Devices [Legacy only]
Boot from PCI-E Expansion Devices [Legacy only]
OS Type [Other OS]
Setup Animator [Disabled]
Load from Profile [4]
Profile Name [3333_fast_test]
Save to Profile [3]
CPU Core Voltage [Auto]
VDDSOC Voltage [Auto]
1.8V PLL Voltage [Auto]
BCLK Frequency [Auto]
CPU Ratio [Auto]
Bus Interface [PCIEX16/X8_1]


----------



## The Sandman

Leftezog said:


> Guys I had a stable ram profile in bios, checking it with ram testers and be stable at everything, heavy gaming, simple tasks browsing, everything. I have my ram at 3333Mhz C14 with CAD_BUS values at auto, after I mess a bit with CAD_BUS values so to have them stable in one value and not let the mobo set them. After some testing setting values to 20,20,2020 - 30,30,30,30 - 20,20,30,30 and 30,30,40,60 the ram was giving errors in ram testers. After I done testing I loaded back my stable profile in bios which typically the only difference it had was CAD_BUS values at auto. And guess what. Runned memtest from curiocity again and it gave me again errors. How is this even possible? I'm very confused because this isn't the only time that it happened to me. My bios settings are the above:
> 
> 
> 
> Spoiler
> 
> 
> 
> [2018/03/05 23:40:16]
> Ai Overclock Tuner [Manual]
> BCLK Frequency [100.0000]
> BCLK_Divider [Auto]
> Custom CPU Core Ratio [Auto]
> > CPU Core Ratio [39.00]
> Performance Bias [None]
> Memory Frequency [DDR4-3333MHz]
> Core Performance Boost [Disabled]
> SMT Mode [Enabled]
> EPU Power Saving Mode [Disabled]
> TPU [Keep Current Settings]
> CPU Core Voltage [Manual mode]
> - CPU Core Voltage Override [1.40000]
> CPU SOC Voltage [Manual mode]
> - VDDSOC Voltage Override [1.07500]
> DRAM Voltage [1.39500]
> 1.8V PLL Voltage [1.80000]
> 1.05V SB Voltage [1.05000]
> Target TDP [Auto]
> TRC_EOM [Auto]
> TRTP_EOM [Auto]
> TRRS_S_EOM [Auto]
> TRRS_L_EOM [Auto]
> TWTR_EOM [Auto]
> TWTR_L_EOM [Auto]
> TWCL_EOM [Auto]
> TWR_EOM [Auto]
> TFAW_EOM [Auto]
> TRCT_EOM [Auto]
> TREFI_EOM [Auto]
> TRDRD_DD_EOM [Auto]
> TRDRD_SD_EOM [Auto]
> TRDRD_SC_EOM [Auto]
> TRDRD_SCDLR_EOM [Auto]
> TRDRD_SCL_EOM [Auto]
> TWRWR_DD_EOM [Auto]
> TWRWR_SD_EOM [Auto]
> TWRWR_SC_EOM [Auto]
> TWRWR_SCDLR_EOM [Auto]
> TWRWR_SCL_EOM [Auto]
> TWRRD_EOM [Auto]
> TRDWR_EOM [Auto]
> TWRRD_SCDLR_EOM [Auto]
> Mem Over Clock Fail Count [2]
> DRAM CAS# Latency [14]
> DRAM RAS# to CAS# Read Delay [14]
> DRAM RAS# to CAS# Write Delay [14]
> DRAM RAS# PRE Time [14]
> DRAM RAS# ACT Time [28]
> Trc [42]
> TrrdS [4]
> TrrdL [6]
> Tfaw [16]
> TwtrS [4]
> TwtrL [12]
> Twr [10]
> Trcpage [Auto]
> TrdrdScl [2]
> TwrwrScl [2]
> Trfc [312]
> Trfc2 [192]
> Trfc4 [132]
> Tcwl [14]
> Trtp [6]
> Trdwr [6]
> Twrrd [3]
> TwrwrSc [1]
> TwrwrSd [7]
> TwrwrDd [7]
> TrdrdSc [1]
> TrdrdSd [5]
> TrdrdDd [5]
> Tcke [1]
> ProcODT [68.6 ohm]
> Cmd2T [2T]
> Gear Down Mode [Disabled]
> Power Down Enable [Disabled]
> RttNom [RZQ/7]
> RttWr [RZQ/3]
> RttPark [RZQ/1]
> MemAddrCmdSetup_SM [Auto]
> MemCsOdtSetup_SM [Auto]
> MemCkeSetup_SM [Auto]
> MemCadBusClkDrvStren_SM [20.0 Ohm]
> MemCadBusAddrCmdDrvStren_SM [20.0 Ohm]
> MemCadBusCsOdtDrvStren_SM [20.0 Ohm]
> MemCadBusCkeDrvStren_SM [20.0 Ohm]
> VTTDDR Voltage [Auto]
> VPP_MEM Voltage [Auto]
> DRAM CTRL REF Voltage on CHA [Auto]
> DRAM CTRL REF Voltage on CHB [Auto]
> VDDP Voltage [0.90000]
> VDDP Standby Voltage [0.90000]
> 1.8V Standby Voltage [Auto]
> CPU 3.3v AUX [Auto]
> 2.5V SB Voltage [Auto]
> DRAM R1 Tune [Auto]
> DRAM R2 Tune [Auto]
> DRAM R3 Tune [Auto]
> DRAM R4 Tune [Auto]
> PCIE Tune R1 [Auto]
> PCIE Tune R2 [Auto]
> PCIE Tune R3 [Auto]
> PLL Tune R1 [Auto]
> PLL reference voltage [Auto]
> T Offset [Auto]
> Sense MI Skew [Auto]
> Sense MI Offset [Auto]
> Promontory presence [Auto]
> Clock Amplitude [Auto]
> CLDO VDDP voltage [Auto]
> CPU Load-line Calibration [Level 3]
> CPU Current Capability [130%]
> CPU VRM Switching Frequency [Manual]
> CPU Voltage Frequency [300]
> CPU Power Duty Control [T.Probe]
> CPU Power Phase Control [Power Phase Response]
> Manual Adjustment [Ultra Fast]
> CPU Power Thermal Control [120]
> VDDSOC Load-line Calibration [Level 3]
> VDDSOC Current Capability [120%]
> VDDSOC Switching Frequency [Manual]
> Fixed VDDSOC Switching Frequency(KHz) [300]
> VDDSOC Phase Control [Power Phase Response]
> Manual Adjustment [Ultra Fast]
> DRAM Current Capability [130%]
> DRAM Power Phase Control [Extreme]
> DRAM Switching Frequency [Manual]
> Fixed DRAM Switching Frequency(KHz) [300]
> DRAM VBoot Voltage [1.40000]
> Security Device Support [Enable]
> TPM Device Selection [Discrete TPM]
> Erase fTPM NV for factory reset [Enabled]
> PSS Support [Auto]
> NX Mode [Enabled]
> SVM Mode [Enabled]
> PT XHCI GEN1 [Auto]
> PT XHCI GEN2 [Auto]
> PT USB Equalization4 [Auto]
> PT USB Redriver [Auto]
> PT PCIE PORT 0 [Auto]
> PT PCIE PORT 1 [Auto]
> PT PCIE PORT 2 [Auto]
> PT PCIE PORT 3 [Auto]
> PT PCIE PORT 4 [Auto]
> PT PCIE PORT 5 [Auto]
> PT PCIE PORT 6 [Auto]
> PT PCIE PORT 7 [Auto]
> PT SATA PORT 0 Enable [Auto]
> PT SATA PORT 1 Enable [Auto]
> PT SATA PORT 2 Enable [Auto]
> PT SATA PORT 3 Enable [Auto]
> PT SATA PORT 4 Enable [Auto]
> PT SATA PORT 5 Enable [Auto]
> PT SATA PORT 6 Enable [Auto]
> PT SATA PORT 7 Enable [Auto]
> Onboard PCIE LAN PXE ROM [Enabled]
> AMD CRB EHCI Debug port switch [Disabled]
> Onboard LED [Enabled]
> Hyper kit Mode [Disabled]
> SATA Port Enable [Enabled]
> SATA Mode [AHCI]
> SMART Self Test [Enabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> ErP Ready [Disabled]
> Restore On AC Power Loss [Power Off]
> Power On By PCI-E/PCI [Disabled]
> Power On By RTC [Disabled]
> Super I/O Clock Skew [Auto]
> HD Audio Controller [Enabled]
> PCIEX4_3 Bandwidth [Auto]
> PCIEX16_1 Mode [Auto]
> PCIEX8_2 Mode [Auto]
> PCIEX4_3 Mode [Auto]
> M.2 Link Mode [Auto]
> SB Link Mode [Auto]
> Asmedia USB 3.1 Controller [Enabled]
> When system is in working state [On]
> In sleep, hibernate and soft off states [Off]
> Intel LAN Controller [Enabled]
> Intel LAN OPROM [Disabled]
> Wi-Fi Controller [Enabled]
> USB Type C Power Switch for USB3.1_E1 [Auto]
> USB Type C Power Switch for USB3.1_EC2 [Auto]
> Network Stack [Disabled]
> Debug Port Table [Disabled]
> Debug Port Table 2 [Disabled]
> Device [OCZ-VERTEX3]
> Legacy USB Support [Enabled]
> XHCI Hand-off [Enabled]
> USB Mass Storage Driver Support [Enabled]
> USB3.1_E1 [Auto]
> USB3_1 [Enabled]
> USB3_2 [Enabled]
> USB3_3 [Enabled]
> USB3_4 [Enabled]
> USB3_5 [Auto]
> USB3_6 [Auto]
> USB3_7 [Auto]
> USB3_8 [Auto]
> USB3_9 [Auto]
> USB3_10 [Auto]
> USB2_11 [Auto]
> USB2_12 [Auto]
> USB2_13 [Auto]
> USB2_14 [Auto]
> USB_15 [Auto]
> USB_16 [Auto]
> CPU Temperature [Monitor]
> MotherBoard Temperature [Monitor]
> VRM Temperature [Monitor]
> PCH Temperature [Monitor]
> T_Sensor1 Temperature [Monitor]
> CPU Fan Speed [Monitor]
> Chassis Fan 1 Speed [Monitor]
> Chassis Fan 2 Speed [Monitor]
> Chassis Fan 3 Speed [Monitor]
> W_PUMP+ Speed [Monitor]
> CPU Optional Fan Speed [Monitor]
> AIO_PUMP Speed [Monitor]
> W_FLOW Speed [Monitor]
> W_IN Temperature [Monitor]
> W_OUT Temperature [Monitor]
> CPU Core Voltage [Monitor]
> 3.3V Voltage [Monitor]
> 5V Voltage [Monitor]
> 12V Voltage [Monitor]
> CPU Q-Fan Control [PWM Mode]
> CPU Fan Smoothing Up/Down Time [0 sec]
> CPU Fan Speed Lower Limit [200 RPM]
> CPU Fan Profile [Silent]
> W_PUMP+ Control [Disabled]
> Chassis Fan 1 Q-Fan Control [Auto]
> Chassis Fan 1 Q-Fan Source [CPU]
> Chassis Fan 1 Smoothing Up/Down Time [0 sec]
> Chassis Fan 1 Speed Low Limit [200 RPM]
> Chassis Fan 1 Profile [Standard]
> Chassis Fan 2 Q-Fan Control [Auto]
> Chassis Fan 2 Q-Fan Source [CPU]
> Chassis Fan 2 Smoothing Up/Down Time [0 sec]
> Chassis Fan 2 Speed Low Limit [200 RPM]
> Chassis Fan 2 Profile [Standard]
> Chassis Fan 3 Q-Fan Control [Auto]
> Chassis Fan 3 Q-Fan Source [CPU]
> Chassis Fan 3 Smoothing Up/Down Time [0 sec]
> Chassis Fan 3 Speed Low Limit [200 RPM]
> Chassis Fan 3 Profile [Standard]
> OnChip SATA Channel [Auto]
> OnChip SATA Type [AHCI]
> USB3_1 [Enabled]
> USB3_2 [Enabled]
> USB3_3 [Enabled]
> USB3_4 [Enabled]
> IR Config [RX & TX0 Only]
> SdForce18 Enable [Disabled]
> SD Mode configuration [AMDA]
> Uart 0 Enable [Enabled]
> Uart 1 Enable [Enabled]
> I2C 0 Enable [Enabled]
> I2C 1 Enable [Enabled]
> I2C 2 Enable [Disabled]
> I2C 3 Enable [Disabled]
> GPIO Devices Support [Auto]
> ESATA Port On Port 0 [Auto]
> ESATA Port On Port 1 [Auto]
> ESATA Port On Port 2 [Auto]
> ESATA Port On Port 3 [Auto]
> ESATA Port On Port 4 [Auto]
> ESATA Port On Port 5 [Auto]
> ESATA Port On Port 6 [Auto]
> ESATA Port On Port 7 [Auto]
> SATA Power On Port 0 [Auto]
> SATA Power On Port 1 [Auto]
> SATA Power On Port 2 [Auto]
> SATA Power On Port 3 [Auto]
> SATA Power On Port 4 [Auto]
> SATA Power On Port 5 [Auto]
> SATA Power On Port 6 [Auto]
> SATA Power On Port 7 [Auto]
> SATA Port 0 MODE [Auto]
> SATA Port 1 MODE [Auto]
> SATA Port 2 MODE [Auto]
> SATA Port 3 MODE [Auto]
> SATA Port 4 MODE [Auto]
> SATA Port 5 MODE [Auto]
> SATA Port 6 MODE [Auto]
> SATA Port 7 MODE [Auto]
> SATA Hot-Removable Support [Auto]
> SATA 6 AHCI Support [Auto]
> Int. Clk Differential Spread [Auto]
> SATA MAXGEN2 CAP OPTION [Auto]
> SATA CLK Mode Option [Auto]
> Aggressive Link PM Capability [Auto]
> Port Multiplier Capability [Auto]
> SATA Ports Auto Clock Control [Auto]
> SATA Partial State Capability [Auto]
> SATA FIS Based Switching [Auto]
> SATA Command Completion Coalescing Support [Auto]
> SATA Slumber State Capability [Auto]
> SATA MSI Capability Support [Auto]
> SATA Target Support 8 Devices [Auto]
> Generic Mode [Auto]
> SATA AHCI Enclosure [Auto]
> SATA SGPIO 0 [Auto]
> SATA SGPIO 1 [Disabled]
> SATA PHY PLL [Auto]
> AC/DC Change Message Delivery [Disabled]
> TimerTick Tracking [Auto]
> Clock Interrupt Tag [Auto]
> EHCI Traffic Handling [Disabled]
> Fusion Message C Multi-Core [Disabled]
> Fusion Message C State [Disabled]
> SPI Read Mode [Auto]
> SPI 100MHz Support [Auto]
> SPI Normal Speed [Auto]
> SPI Fast Read Speed [Auto]
> SPI Burst Write [Auto]
> I2C 0 D3 Support [Auto]
> I2C 1 D3 Support [Auto]
> I2C 2 D3 Support [Auto]
> I2C 3 D3 Support [Auto]
> I2C 4 D3 Support [Auto]
> I2C 5 D3 Support [Auto]
> UART 0 D3 Support [Auto]
> UART 1 D3 Support [Auto]
> UART 2 D3 Support [Auto]
> UART 3 D3 Support [Auto]
> SATA D3 Support [Auto]
> EHCI D3 Support [Auto]
> XHCI D3 Support [Auto]
> SD D3 Support [Auto]
> S0I3 [Auto]
> Chipset Power Saving Features [Enabled]
> SB Clock Spread Spectrum [Auto]
> SB Clock Spread Spectrum Option [-0.375%]
> HPET In SB [Auto]
> MsiDis in HPET [Auto]
> _OSC For PCI0 [Auto]
> USB Phy Power Down [Auto]
> PCIB_CLK_Stop Override [0]
> USB MSI Option [Auto]
> LPC MSI Option [Auto]
> PCIBridge MSI Option [Auto]
> AB MSI Option [Auto]
> SB C1E Support [Auto]
> SB Hardware Reduced Support [Auto]
> GPP Serial Debug Bus Enable [Auto]
> PSPP Policy [Auto]
> Memory Clock [Auto]
> Bank Interleaving [Enabled]
> Channel Interleaving [Enabled]
> Memory Clear [Disabled]
> Fast Boot [Enabled]
> Next Boot after AC Power Loss [Normal Boot]
> Boot Logo Display [Auto]
> POST Delay Time [3 sec]
> Boot up NumLock State [Enabled]
> Wait For 'F1' If Error [Enabled]
> Option ROM Messages [Enabled]
> Interrupt 19 Capture [Disabled]
> Setup Mode [Advanced Mode]
> Launch CSM [Enabled]
> Boot Device Control [UEFI and Legacy OPROM]
> Boot from Network Devices [Legacy only]
> Boot from Storage Devices [Legacy only]
> Boot from PCI-E Expansion Devices [Legacy only]
> OS Type [Other OS]
> Setup Animator [Disabled]
> Load from Profile [4]
> Profile Name [3333_fast_test]
> Save to Profile [3]
> CPU Core Voltage [Auto]
> VDDSOC Voltage [Auto]
> 1.8V PLL Voltage [Auto]
> BCLK Frequency [Auto]
> CPU Ratio [Auto]
> Bus Interface [PCIEX16/X8_1]


Have you tried to lower ProcODT? 
68.6 seems high for Sammy B-Die.
My Flare-X run at 53.3.

If it were me I'd clear CMOS (not f5 default settings) and re-enter OC settings and re-test.

If it's any help here is my Bios text file (3502) that passes 1500% on HCI Memtest running 3466MHz 14-13-13-26-44-1T.
Notice VDDP, ProcODT, Rtt and MemCadBus settings. You can always use the Ryzen memory calculator to get a starting point for these on your chips.


----------



## Leftezog

The Sandman said:


> Have you tried to lower ProcODT?
> 68.6 seems high for Sammy B-Die.
> My Flare-X run at 53.3.
> 
> If it were me I'd clear CMOS (not f5 default settings) and re-enter OC settings and re-test.
> 
> If it's any help here is my Bios text file (3502) that passes 1500% on HCI Memtest running 3466MHz 14-13-13-26-44-1T.
> Notice VDDP, ProcODT, Rtt and MemCadBus settings. You can always use the Ryzen memory calculator to get a starting point for these on your chips.


I will try it when I get home. Thanks. Also all of you having offset voltages in cpu do you overclock it through asus turbo vcore, with dual intelligent processor 5 or what?


----------



## Superbegita

The Sandman said:


> 1701/9920 or 6001 IMHO.
> I've had my Flare-X (B-Die) at 3466 14-13-13-26-44-1T up till 6001.
> On 9920 ran 1600% HCI stable without issue.
> 
> Not saying I won't go back (I haven't given up yet) but this new Agesa is a PITA.
> If you have B-Die and don't feel like playing for hours go with 1701/9920/3502.
> Any other go with with 6001.
> I don't see any performance gains with memory with 6001 (compared to my previous B-Die settings), in fact I still have not matched them.
> I've been trying all weekend to even semi stabilize 14-13-13 GearDownMode Enabled as before with zero luck so far.
> 
> I did come across this from a while back if its of any help http://www.overclock.net/forum/26326957-post26508.html


Hi guys ! Great to be here ^^ Humm for me i have succeed (thanks to the software of course) to reach 3533Mhz on my actual kit (G.Skill Trident Z RGB 2x8go 4266Mhz CAS19 so of course memory chips Samsung in B-Die) ..BUT ! With very low timings i am a bit surprise i have to said 0.0

See by yourselves https://image.noelshack.com/fichiers/2018/10/2/1520348938-capture-d-ecran-100.png

For my buuild it's composed by:

-Ryzen R7 1800X oc to 4.13Ghz stable (with 1.5750 VCore of course..no miracles can hapen to reach with point)

- Motherboard: Gigabyte AX370 Gaming K7 (flagship of Gigabyte in Ryzne for make iut simple)

- Ram: G.Skill Trident Z RGB 4266Mhz CAS19 in 2x8go.

An others of course ^^

Ah yeah ! I have quickly notice that for me and my memory chips... I MUST activate absolutely Gear Down Modse .. And it llok like the ProcODT 60 ohms is the best for me


----------



## The Sandman

Leftezog said:


> I will try it when I get home. Thanks. Also all of you having offset voltages in cpu do you overclock it through asus turbo vcore, with dual intelligent processor 5 or what?


I use a P-State 0 VID OC along with Offset.
It's located under Advanced/AMD CBS/Custom Pstates/throttling.

Have a look here for the "How To" https://hardforum.com/threads/ryzen-pstate-overclocking-method-calculation-and-calculator.1928648/
The third post sums it all up nicely.

I never recommend using any Asus SW.


----------



## Superbegita

Guysb ! I think..i really found the priceless ULTRAZ golden one Ryzen..Judging by yourselves 

https://image.noelshack.com/fichiers/2018/10/3/1520450642-sans-titre.png

It's one of friend from mine.. I won't leblieve it until it show me..THAT !

Apparently...in can run to 4000Mhz but with only one stick to the desk (at least).. I am REALLY surprise..Even me i don't get too hight 0.0


----------



## Dr. Vodka

Ok... Gonna need some stress testing on that, and some benchmarks. If stable, that's THE golden sample! If not, it probably has a decent shot at 3600MHz stable.


----------



## abso

I am running my Ram with this settings for a while now and everything is stable. https://imgur.com/a/UYUzr

Anyone here sees any more potential to finetune any further or should I call it a day? The RAM is Corsair LPX 3000 with Samsung E-Die.


----------



## Leftezog

Hi to everyone! Anyone can suggest a specific order for ram overclocking for 3333 mhz or 3466 for Samsung b die on asus ch6? I have 3600 c16 2x8gb kit and the best I managed so far is 3200c14 stilt's safe timings. I can boot with ease with either 3333c14 ,3466c14 or 3600c16 but I cant find stable settings that passes hci memtest. Anyone have a suggestion about an order? Like first we put some loose primary timings to the ram and the rest on auto, dram voltage at 1.4 or 1.44 according to speed and timings or if I must first adjust vddp or something else on tweaker's paradise and after mess with proc odt cad and rtt values? Anyone can help ?


----------



## Darkstalker420

Wondered if anyone could offer advice. Rig is ASUS Strix B350 F Gaming (3803 BIOS). The problem is i can't pass OCCT Linpack as the rig errors out at around 18 mins every time REGARDLESS of settings (within reason of course). I have ran various voltages as far as i feel comfortable with by themselves and together. Tried LLC levels and such and just can't crack the Linpack OCCT though it will do an hour of the other included OCCT CPU Test without issue (that clued me into the bad VDroop this board has) as before raising the OFFSET it wouldn't pass that either.

Through raising the OFFSET of the CPU to (+) 0.05625 i managed to get the hour pass on OCCT. Though that didn't help at all with the Linpack version. I'm truly stuck i just want 3200C14 tbh and would be happy to pass stress tests at that. The sad thing is the rig is fine day to day now and will game/browse/stream etc. But WILL not pass any kind if "real" stress test 100%. I'm pulling my hair out tbh LMAO!! I have no idea about the more technical memory settings and if i just input everything the calculator says it STILL crashes at 18 mins or so. If i set it all to AUTO.... Still crashes at around 18 mins so whatever i try it crashes at 18 mins every time (bar ONE time it made it to 36 mins).

From watching the OCCT monitoring plugin it seems to crash as the test is "winding down" on each pass as i watch the temp drop on the CPU and hear the fans slow down. This was the case around the 36 min mark as well. I still suspect perhaps voltage but bumping up the OFFSET again didn't help out and running LLC on EXTREME hasn't helped it last longer. Have to say i have been messing about with this for weeks now and i'm truly sick of it tbh. Each adjustment in settings requires at least 18 mins to check if stable (i stopped using IBT AVX because it would pass/fail tests randomly as in might pass 10 on V HIGH. Then fail a quick 10 STANDARD!!).

Just using OCCT for now. Any help WHAT SO EVER will be very welcome. Pic has settings/timings etc.

Sticks are 2 8GB B Die: Corsair CMK16GX4M2B3600C18

Thanx.


----------



## Darkstalker420

Set ALL memory related options back to AUTO and VCore and SoC on AUTO (with EXTREME phase enabled LLC on AUTO for both) and loaded D.O.C.P. settings (now remember i purchased these sticks because they were in the QVL list for 3200Mhz operation via D.O.C.P). Lets see how we do..... Same around 18 min as usual. This is what i'm up against even settings that were "supposed" to be click and play ain't even working. I can load up "The Stilts" safe 3200Mhz timings and it will still crash at around 18 mins. Load up the slowest AUTO D.O.C.P. timings you can think of and...... Still crash at around 18 mins.
Use AUTO VCore/SoC crash about 18 mins... Add "Reasonable" OFFSET VCore/SoC.... Crash about 18 mins. Nothing i have "fiddled" with makes any difference. I don't know enough about setting some of the other stuff like CLDO_VDDP and other such things but i get the idea they are the "finishing touch" on memory settings but with this rig i can't even seem to get basic memory timings to "make a difference" regarding stability.

I'm truly stuck people. I see some with B Die at 3466 or more with C14 timings and here i am with QVL 3200Mhz sticks that won't do what they were rated to do EVEN by the MoBo manufacturer. All i want is 3200C14 100% stress test stable and i will be done until i clock the 1700 some time in the future. Yet it just escapes me how to get it stable. HELP!!!!!! *shouting fades to sobbing* LMAO!!

Here is a pic of the last attempt notice the much slower timings this time in RTC.

Thanx.


----------



## KoeRt

abso said:


> I am running my Ram with this settings for a while now and everything is stable. https://imgur.com/a/UYUzr
> 
> Anyone here sees any more potential to finetune any further or should I call it a day? The RAM is Corsair LPX 3000 with Samsung E-Die.


Which board do you have and which BIOS do you run with it?


----------



## abso

KoeRt said:


> Which board do you have and which BIOS do you run with it?


STRIX X370-F with latest BIOS


----------



## Superbegita

Darkstalker420 said:


> Set ALL memory related options back to AUTO and VCore and SoC on AUTO (with EXTREME phase enabled LLC on AUTO for both) and loaded D.O.C.P. settings (now remember i purchased these sticks because they were in the QVL list for 3200Mhz operation via D.O.C.P). Lets see how we do..... Same around 18 min as usual. This is what i'm up against even settings that were "supposed" to be click and play ain't even working. I can load up "The Stilts" safe 3200Mhz timings and it will still crash at around 18 mins. Load up the slowest AUTO D.O.C.P. timings you can think of and...... Still crash at around 18 mins.
> Use AUTO VCore/SoC crash about 18 mins... Add "Reasonable" OFFSET VCore/SoC.... Crash about 18 mins. Nothing i have "fiddled" with makes any difference. I don't know enough about setting some of the other stuff like CLDO_VDDP and other such things but i get the idea they are the "finishing touch" on memory settings but with this rig i can't even seem to get basic memory timings to "make a difference" regarding stability.
> 
> I'm truly stuck people. I see some with B Die at 3466 or more with C14 timings and here i am with QVL 3200Mhz sticks that won't do what they were rated to do EVEN by the MoBo manufacturer. All i want is 3200C14 100% stress test stable and i will be done until i clock the 1700 some time in the future. Yet it just escapes me how to get it stable. HELP!!!!!! *shouting fades to sobbing* LMAO!!
> 
> Here is a pic of the last attempt notice the much slower timings this time in RTC.
> 
> Thanx.


Hummm..questions....huu.. What exactly is the motherboard you use? X370/B350 ? And if....what model exactly. I know that well..some people get some torubles on the ASRock more exactly the Killer SLI version (it'ds not of course the top tier Taichi ones..but still).


But you're right indeed some people can have 3466/3533Mhz with very low timings with Samsung B ie (i am one of thoses).
I used as motherboard the Gigabyte AX370 (Aorus one) Gaming K7 (their flagship for AM4). I run my ram at 3533Mhz at 14-14-14-14-28-46 and of copurse ALL sub timings heavilmy modified.

Ah yes i was to forgot ! I usef the last BIOS i can for now (the ones just before the one for being able to run a Pinnacle Ridge) More exactly the F22b version. From what i have experiment with various boards on AM4..and Ryzen chips..

The more the Ryzen is naturally good..The more you have big chances that the memory controller will be very good.

But i need to push the voltage to at least 1.47 no less..if not i get instant BOSD.


----------



## GaudyGhost

..


----------



## mongoled

Hi!

Has anybody seen/mentioned if any sort of relationship exists between vdimm and soc voltage ??

Basically I am seeing the following characteristics.

vdimm: 1.35v
soc: 1.0v
no issues when booting/rebooting/shutdown etc etc

Now....

Simply raising the vdimm voltage to 1.4v triggers memory training beeps on either booting/rebooting/shutdown etc etc

Then if I do the following, raise soc voltage by 0.050v so the settings are as below

vdimm: 1.40v
soc: 1.050v

Then again I have no issues when booting/rebooting/shutdown etc etc

So was wondering if anybody else has seen mentioned or experienced something similar


----------



## zGunBLADEz

Got a CH6 and a B350-I Strix after that bcuz i decided to shrink my build, this little board is something else im starting to like it lol
Got me a new set of ram to go with the itx board was hoping for the best i mean cant complaint 
GSKILL F4-3600C17D-32GTZR


It corrupted my os when i tried to use stock values at first but thats how my Mortar Artic M-Atx started in the beginning now she can do 3600 just fine she have a new owner anyway lol. Good little matx that mortar artic board for the price i just hoped for better vrm cooling than the one it got. This itx vrm cooling is better tho it needs to be active cooled while stress testing with programs like P95 etc regular usage not needed. It dont have a vrm diode either which is a shame.

16hrs+ hci coverage 1300%+


----------



## Nighthog

I've been testing this new Gigabyte BIOS and I'm back to 3200Mhz with this memory kit I've been using.

Stock CPU though, water waiting for components.

EDIT:
Found that Cadbus was unstable with 20Ohm so had loosened some timings to try find stability but only found it when I increased Cadbus to 24Ohm. 
Could get lower timings and lower voltage to be stable with 24Ohm values after a retry. Could probably be tweaked a little more I guess but it's about where I will let it be.


----------



## -antero-

Hi to all!

What would be the best settings for G.Skill F4-3200C15-8GTZ (2*8GB kit) on AsRock AB350M Pro4? Played little bit, but managed to screw up even 3200 safe timings
Is it better to go with cl14 or cl16 (probably cl16 would be safer bet)? I know that Ryzen doesn't support cl15 as my kit is stated to run, automatically sets it to cl16.
Bios is the latest one from AsRock homepage (4.70)


----------



## Anty

Ryzen supports CL15 but with 1T only. Most likely you have 2T or gear down enabled.


----------



## -antero-

Anty said:


> Ryzen supports CL15 but with 1T only. Most likely you have 2T or gear down enabled.


Gear down always disabled and cpuz shows [email protected]


----------



## Superbegita

-antero- said:


> Gear down always disabled and cpuz shows [email protected]


Humm same here..Even if i let 2T for Command Rate CPU-Z always show me 1T

For your problem..i have to say that the more motherboard you have is good..The more you'll to expect much highter ram frequency.

I know someone with a ...well an ASRock but an X370 an SLI Killer well since he goes from Biostar to this one he can't even reach 3000Mhz in fact.. - -

But for me indeed it seems that GearDownMode is in Enabled mode.


----------



## -antero-

Short of got something stable yesterday. HCI memtest for overnight resulted with 2 errors, fortunately no restart. Pc was fully useable in the morning and memtest was still running, ended it at ~1700% coverage. After that did little bit Aida64 system stability ~45min, 4-5 runs of Cinebench15 and at the end did also Heaven Benchmark 4.0. So far everything is running, now I'm going to do some gaming tests and after that HCI again.


----------



## seansplayin

*Ryzen with 3733 memory*

Hi, so I finally ditched my Corsair LPX 3200 mem kit and Tonight installed TridentZ 4266 16 GB kit (white). I loaded the 3600mem preset under the memory timings page, set dram voltage to 1.5v, SOC to 1.15v, set to 1T and bam, trained, posted and booted into windows. It's definitely not stable but here's what the benchmarks gave me. Kind of crazy cause I've not seen anyone talking higher than 3600 memory speed for Ryzen, wonder If I should loosen some timings and try to stable it out at 3733.

http://s943.photobucket.com/user/se...4100_3733_3600biospreset_zps8m8djf33.jpg.html
http://s943.photobucket.com/user/se...4100_3733-1616161638561T_zpsxe1ayke7.jpg.html
http://s943.photobucket.com/user/se...4100_3733-1616161638561T_zpsnhtyxq3q.jpg.html


----------



## 336613f

Whoa 172 single core score on cinebench I think is the best I have seen so far with regular Am4 Ryzen cpus to date. That has to be the Ram speeding the infinity fabric up a bunch!


----------



## zGunBLADEz

this is my itx strix i love this board


----------



## Superbegita

zGunBLADEz said:


> this is my itx strix i love this board


Hummm i am impressed sure ! How did you managed to obtain this on Cinébench 15? Myself i am at 1828/1840 not more.. But i am at 4.1ghz.

I have some dubts you're full stable judging the 41.25....Myself i have been obliged to downclock to 4.1ghz.

Most amazing is that my ram is above yours and i still don't get it...But my timings are low..

AMD Cool and Quiet disbale i guess too? (so as me).


----------



## Anty

@seansplayin

Could you post dump from RTC 1.03?


----------



## seansplayin

Memory TridentZ 4266, (F4-4266C19D-16GTZKW)
ASUS C6H running bios 3008
After weeks of failed stability testing I've finally figured out what settings we're causing my memory errors. setting procODT to 48, RTTNOM to RZQ/7, RTT to off, RTTPARK to RZQ/7, CAD_BUS ClkDrv to 30, CAD_BUS AddrCmdDrv to 40, CAD_BUSCkeDrv to 60. 
until I changed these settings it honestly didn't matter how much voltage I threw at the dram/soc or how much I loosened the timings I would still get 2 mem errors usually within the first hour of a 10 hour memtest. 

now that I solved that problem it's time to start tightening the primary and secondary timings.


----------



## seansplayin

*4125 core, 3600 memory*



zGunBLADEz said:


> this is my itx strix i love this board


this is mine at 4125 C6H FTW


----------



## krissbay

I actualy have a strange difficulty with my RAM and CPU OC.
If i OC the RAM alone my memory speed(read, write and copy) ist around 50000 MB/s but when i OC my CPU in the same time 
these Speeds drop to around 40000 MB/s. For both CPU and GPU i set 1.4 V.
did anybody experienced something similar and know whats causing this?


----------



## seansplayin

krissbay said:


> I actualy have a strange difficulty with my RAM and CPU OC.
> If i OC the RAM alone my memory speed(read, write and copy) ist around 50000 MB/s but when i OC my CPU in the same time
> these Speeds drop to around 40000 MB/s. For both CPU and GPU i set 1.4 V.
> did anybody experienced something similar and know whats causing this?


yeah I could see how selecting a faster memory speed could actually lower performance if you're using auto memory timings and your motherboard is populating some loose timings. use Ryzen timing checker to compare memory timings between your two memory speed profiles and post results.


----------



## Pietro

Ryzen [email protected] 1.2-1.225V or 3.9GHz 1.4V, soc 1.1V, Samsung B-die 3600MHz Cl17 works with my ryzen at 3200MHz 14-14-14-14-28-42.


----------



## NYM

[email protected] 0.94v---BIOS P3.40---HCI---400%---BLS8G4D26BFSC.16FB

Just wanting to share my results, my [email protected] 1.187vcore(bios setting) and a single 8 gb ballistix [email protected] 2666 cl16 1.2v. Prime95 small fft stable for at least 2 hours, average temperature of 65 degrees(25 degrees ambient), using a Wraith MAX rev.B cooler.

Previously at bios P3.10, my memory was always having error at hci memory test at about 1%-50% coverage, ever since updating to P3.40, it solved magically.


----------



## ProjectV8

Hello.

These are my lovely Micron B-die.
2400 15-15-15-35 1.2V @ 3260 16-18-18-34 1T 1.35V (Easily)

Micron chips also present in the HyperX HX424C15FB/8 (8GB Modules) easily reach 3400Mhz. I had the opportunity to test them on a MSI-B350-PC Mate that I set up for a friend.


----------



## seansplayin

*4225 core-3466 memory*

after a failed memory upgrade in friends computer yesterday we got bored and decided to see how fast we could push my system. I did get to 4225 though.


----------



## RX7-2nr

I've got my trident z F4-3000C16D-16GTZR running at 3000. 1800x and C6H. These are hynix a die single rank dimms. Didn't take anything more than enabling docp 5. C6H blows the the soc voltage out all the way to 1.19 when you use any docp setting so I lowered it to 1.06. I haven't done any other tweaking but I want to tune the voltages down, maybe try to push it to 3200, or tighten the timings. At 3000 with no tweaking it's HCI 400% stable.


----------



## matthew87

I posted this in the Crosshair 6 Thread but hoping someone here can provide some input:

I've found my overlcocked RAM, Samsung B die @ 3466mhz, is entirely stable so long as the PC is 'warm'. When cold booting after the computer has been off for a few hours GSAT and HCI Memtest will quickly pickup lots of errors errors. Give the PC 5-10 minutes to 'warm up', reboot, and presto the memory can pass 2 hours of GSAT and 8+ hours - 1200% - of HCI Memtest with no errors at all. Subsequent reboots after 'warm up' also will not generate any errors, even with complete power off. 

No changes are being made to voltages, LLC, or any settings in BIOS between 'cold' and 'warm' stability tests. The memory errors only ever appear for the first 5-15 minutes of PC use. 

I've configured DRAM timings, DRAM voltage and SoC voltages in BIOS. 

Can anyone suggest what could be the cause and solution for this obscure issue?


----------



## datspike

matthew87 said:


> Give the PC 5-10 minutes to 'warm up', reboot, and presto the memory can pass 2 hours of GSAT and 8+ hours - 1200% - of HCI Memtest with no errors at all. Subsequent reboots after 'warm up' also will not generate any errors, even with complete power off.


That's a behavior I have not seen yet on Ryzen. Can you post your RTC screenshot and memory voltages?

Btw, figured out that I need the vttddr on the high side (1.46\0.7788) is the key to get 3600C14 to be stable.
Will post an entry with all the settings and HCI 1000+ run later


Spoiler














Does anyone know why AIDA have started to show such high latencies on later AGESA bioses? SIV64 still shows a more reasonable 60.9 to 61.1ns latency (to be fair SIV64 always was 1-2ns lower than AIDA), while AIDA reports a crazy 66-67ns+ result.
I remember getting 64.5ns with AIDA with 3466C15 tightened config on my other kit and 1.0.0.6a based bios.


----------



## Anty

datspike said:


> That's a behavior I have not seen yet on Ryzen.
> 
> Does anyone know why AIDA have started to show such high latencies on later AGESA bioses?


1) I've experienced it with old BIOSes when room temp was low - many failed trainings until PC warmed up.

2) DRAM power saving turned off?


----------



## gagac1971

hello to all here...i have ryzen 1800x asus CH6 board whit bios 6004 overclocked at 4.0 ghz whit 1.352V and i want to ask you if i can purchase some nice g skill memorys at 3600 mhz?can somebody help me whit this choice?will be possible to run 3600 mhz memory speed at rated speed?


----------



## datspike

Anty said:


> 2) DRAM power saving turned off?


It was enabled indeed, as well as GDM. Thanks for the tip, somehow missed those settings on that run.


----------



## ProjectV8

gagac1971 said:


> hello to all here...i have ryzen 1800x asus CH6 board whit bios 6004 overclocked at 4.0 ghz whit 1.352V and i want to ask you if i can purchase some nice g skill memorys at 3600 mhz?can somebody help me whit this choice?will be possible to run 3600 mhz memory speed at rated speed?


Maybe this can help you. 
=> https://rymem.vraith.com/basic/top10
=>https://rymem.vraith.com/basic/view_by_mobo


----------



## The Sandman

gagac1971 said:


> hello to all here...i have ryzen 1800x asus CH6 board whit bios 6004 overclocked at 4.0 ghz whit 1.352V and i want to ask you if i can purchase some nice g skill memorys at 3600 mhz?can somebody help me whit this choice?will be possible to run 3600 mhz memory speed at rated speed?


Only a few are just now able to run 3600MHz on 1xxx series chips and I can't say how stable they are.
Better to aim for a tight 3466MHz. From I've seen most that have 3600MHz memory are running in this area.
3600MHz is much more doable with 2xxx version.

My 1800x/C6H will run GSkill Flare-X 3200C14 at 3466MHz 14-13-13-26-44-1T 8 hr 1600% HCI stable to give you an idea.


----------



## zGunBLADEz

seansplayin said:


> this is mine at 4125 C6H FTW


that board sucks sorry lol

btw thats a 32GB KIT 2x16GB rated for 3600 running @ 3466/LL on top of that.
On a ITX B350 mobo so go figures


----------



## ScorpMCP

Can you keep that while disabling geardown mode? I got the same kit and been running at 3446 stable with tight timings, trying to get it to work at 1t without geardown mode now since the new bioses are out, thats why im asking.
Im not sure but I think RTC will show either 1t or 2t with geardown mode on, but its like a third kinda state. Maybe someone who knows could enlighten me.
On another note with the new bios i could boot up into windows instantly on 3666mhz with those same 3446 timings, not that it was stable or anything but feels like a big step up from last bios so maybe theres some potential there. Cheers.


----------



## Danesh_italiano

I've got 16GB (2x 8GB) GSkill Ripjaws V 3600Mhz CL16 running at 3200Mhz CL14 STABLE with 1.35v on my Asus Prime B350M-E. This motherboards changes automatically the SOC voltage to 1.10v when running at 3200Mhz + 1.35v. Updated bios from AGESA 1001a to 1002a and the latency jumped from 82ns to 68ns. Same configuration on ALL settings.
Other day, for no reason (no windows updates or new drivers/bios), my PC started crashing/BSOD when i was trying to play any game. I had to change the SOC voltage from 1.10v to 1.125v. Now it is stable again. To make sure everything are rock solid, usually i run Memtest for 12 hours, prime95 for 10 hours and aida64 stress test for 8 hours.

Also, my 2200G it is overclocked to 3.825Mhz with 1.381v. Unfortunally i am not able to overclock the GPU. I am getting random freezes even if a set the clock to 1100Mhz. I need to leave it as Auto.


----------



## The Sandman

ScorpMCP said:


> Can you keep that while disabling geardown mode? I got the same kit and been running at 3446 stable with tight timings, trying to get it to work at 1t without geardown mode now since the new bioses are out, thats why im asking.
> Im not sure but I think RTC will show either 1t or 2t with geardown mode on, but its like a third kinda state. Maybe someone who knows could enlighten me.
> On another note with the new bios i could boot up into windows instantly on 3666mhz with those same 3446 timings, not that it was stable or anything but feels like a big step up from last bios so maybe theres some potential there. Cheers.


If this was meant for me...
With my 1800x I could not run Geardown Disabled with this clock, even up to UEFI 0001.
Also been trying with my 2700x and so far no luck with disabling it and maintaining stability.
At least on the 2700x it appears to have more headroom. Just haven't had enough time to get there yet. 

Might start here on Geardown Mode http://www.overclock.net/forum/26711945-post33563.html 
I know there is more but couldn't locate it about 1T and 2T (the NEW site strikes again lol)


----------



## PapitaHD

*New ram kit, difficulties with the timings*

Hi everyone!
Recently I did a slight upgrade and replaced my TridentZ 3733cl17 kit with even better samsung b-dies as I got the 3600cl15 one. I've been testing it for almost 2 weeks now and basically the thing is that the only timings it likes is the Stilt's 3466 preset from the C6H's bios (I have C6H+1700x). With the previous kit I could use the fast/extreme presets from 1usmus's calculator and it was perfectly stable but no luck with the new ram kit. Fortunately it's hci memtest stable with the Stilt's cl15 preset at 3533 and almost stable at 3600 (managed to go 800+% without an error) but I think it has some room for tightening at 3466-3533.
I attached the timings which work now, I really tried every power option, I think I have the best settings with the voltages and everything but I don't understand how the timings work. As soon as I change anything on the attached preset (at 3466-3533) it's not stable anymore.
Could anyone give me some suggestions how could I tighten the timings?


----------



## Naol

Naol--R5 [email protected] 1.1v---BIOS f20---HCI---1200%---KHX2400C15/8G

My first Ram overclock, I'm happy with it, but I'll try tightening the timings, and change CR to 1T. 
Everything other than Vsoc, Ram Voltage and multiplier, Power Down, Gear Down is on auto. 3200mhz is a no go, it won't boot at all, sometimes 2nd bios will kick in. I also tried Ryzen Dram Calculator, but it wouldn't boot with suggested timings, although Auto settings don't diverge too much from the calculator.
Also did GSAT 1 hour passed with no errors, but I didn't took a printscreen and I did LinX with no errors too, but it froze the system after 18th run though.


----------



## kidwolf909

Anyone here have any experience with the Team Group T-Force Night Hawk RGB DDR4-3600 or DDR4-4000 kits? I just picked up a 2700X and would like to pair it with some RGB RAM, but not entirely sure whether I want to go with the usual TridentZ RGB or the Team Group.

Definitely looking for B-die, of course. I'm assuming both the Team 3600 and 4000 kits are B-die given their speeds and timings (CL18-20-20-44)

Thanks in advance!


----------



## CJMitsuki

kidwolf909 said:


> Anyone here have any experience with the Team Group T-Force Night Hawk RGB DDR4-3600 or DDR4-4000 kits? I just picked up a 2700X and would like to pair it with some RGB RAM, but not entirely sure whether I want to go with the usual TridentZ RGB or the Team Group.
> 
> Definitely looking for B-die, of course. I'm assuming both the Team 3600 and 4000 kits are B-die given their speeds and timings (CL18-20-20-44)
> 
> Thanks in advance!



Im going with TridentZ 3600c15 or their 4000mhz kit to try to get it to 3600c14. I couldnt find much info on Team Group kits aside from the 4000mhz kit below. Honestly the G.Skill has sexier timings @3600 but its hard to compare since there was no 3600mhz kits in Thaiphoon Burners database for team group. TridentZ kits has proven itself to me so Im rolling with what is proven to me but Im not getting the RGB model. Probably get something very close to the TridentZ kit below.


----------



## kidwolf909

CJMitsuki said:


> Im going with TridentZ 3600c15 or their 4000mhz kit to try to get it to 3600c14. I couldnt find much info on Team Group kits aside from the 4000mhz kit below. Honestly the G.Skill has sexier timings @3600 but its hard to compare since there was no 3600mhz kits in Thaiphoon Burners database for team group. TridentZ kits has proven itself to me so Im rolling with what is proven to me but Im not getting the RGB model. Probably get something very close to the TridentZ kit below.


Thank you for the feedback, CJMitsuki! I wish I could find the dang REP+ button that we used to have here...

Anyway - yea, I've seen enough positive feedback on the G.Skill to know it's a safe option. I'm just intrigued by the possibility of going DDR4-4000CL18 from Team for the same price as DDR4-3200CL14 from G.Skill. Although, I'd be willing to be that both kits could kit one another's speed/timings since they're highly-binned B-die.


----------



## CJMitsuki

kidwolf909 said:


> Thank you for the feedback, CJMitsuki! I wish I could find the dang REP+ button that we used to have here...
> 
> Anyway - yea, I've seen enough positive feedback on the G.Skill to know it's a safe option. I'm just intrigued by the possibility of going DDR4-4000CL18 from Team for the same price as DDR4-3200CL14 from G.Skill. Although, I'd be willing to be that both kits could kit one another's speed/timings since they're highly-binned B-die.


Thank You. I know I will more than likely not be able to hit 4000mhz at first but can still be clocked at lower speeds with lower timings...such as, 3600c14 which sounds sexy but if not able to push 4000 then Im sure it will happen with Bios revisions in the coming months. Honestly 3600c14 will be a beast if you are able to get the secondaries and tertiaries tightened which Im fairly confident about if running a 4000mhz tridentz B Die kit downclocked to 3600. Crank voltage to 1.45v and go to town on x470 chipset. Im not as confident about the x370. ive heard many good things about the CH7 involving memory potential. I was dead set on getting the 2700x and a CH7 but I backed out of the preorder after seeing benchmarks on the CPU and Im going to keep my 1700x for a bit longer but I just ordered a CH7 and the kit I mentioned in my earlier post but in 4133mhz since there wasnt much difference in price. The memory potential doesnt seem to be getting much from the new IMC but more from the mobo itself. I dont really care for hardcore CPU overclocking anyway, I want some smoking memory which I feel like will benefit the infinity fabric in ridiculous ways once we are able to push past the 4000mhz mark consistently with good stability. Another reason I held off on the new CPU is the rumors of many more higher core count CPUs in the works. 2800x 10 core?!


----------



## masterkaj

For anyone trying to pass a custom prime95 blend test to check ram/imc stability. I just figured out why I was intermittently having trouble passing with any setting on my 2700x while my 1700x passed with the same settings. 

It seems I can pass on version 29.2 but always get rounding errors on 29.4 build 7. I’m not sure what changed in the newer version but I am passing memtest at 1000%, ram test at 9000%, both prime95 blend and smallfft for over 10 hours on 29.2, realbench for 8 hours, IBT 10 passes on maximum, and 8 hours on AIDA. 

I’m assuming 29.2 is good at finding stability because I never had one crash on my 1700x and the newer version may just have some bug on our processors. I can still get rounding errors on 29.2 if I tighten my timings too much so I know it still catches imc/ram instability. 

I thought I was going crazy chasing stability and it just turned out to be a software issue. I can now focus on optimizing my timing/boosting frequency above my DDR3333 profile instead of trying to get my default 3200 xmp to pass.


----------



## BadRobot

This ram is amazing! I got dual rank 2x16GB from a set of 128GB Corsair Dominator Platinum ram (CMD128GX4M8B2800C14). The version on the sticker is 4.31 which should be Samsung B-die. Well, thanks to AGESA 1.1.0.1 update for my board, I pushed my previous overclock of 2933Mhz CL14 to 3200Mhz CL14. They perform beautifully! Unfortunately, my Ryzen 1800X can't do 4Ghz anymore since I bluescreen after a while in games. Turned it to 3.9Ghz and it's doing great.

Screenshot direct link: https://i.imgur.com/RhEV8AS.png + https://i.imgur.com/pJfu9bt.jpg


----------



## Jaju123

Just FYI, motherboard makes a huge difference.
Went from a MSI gaming carbon pro x370 to a Asus Crosshair VII hero and i can suddenly run 3600mhz cl15 no problem, or 3466 very low latency. 

Before I couldn't even run 3600 without instant horrific memory errors in memtest or failures in prime95. Same for 3466. Now both are solid as a rock at the same timings or better.

On a 3600mhz cl15 b die kit btw.

Sent from my CLT-L09 using Tapatalk


----------



## Nighthog

Decided to make a surprise decision to buy some new memory out of the blue. 

I want to test out some new memory kits just released from Kingston. 

*HX434C19FB2K2/16*

2X DDR4 3466Mhz 2x8GB CL19 @ 1.2V

Probably a bad decision but that 1.2 Volts sparked my interest. Gonna see how they fare, if they will work at all and see what kind of chips they might have.


----------



## ProjectV8

Nighthog said:


> Decided to make a surprise decision to buy some new memory out of the blue.
> I want to test out some new memory kits just released from Kingston.
> *HX434C19FB2K2/16*
> 2X DDR4 3466Mhz 2x8GB CL19 @ 1.2V
> Probably a bad decision but that 1.2 Volts sparked my interest. Gonna see how they fare, if they will work at all and see what kind of chips they might have.


*HX434C19FB2K2/16* = Micron Single Side and I believe to be B-die.

I do not think it's a bad decision to choose these memory modules.
Micron chips have a high overclocking power.
I have two Hyper X modules Micron B-die 2400 CL15 1.2v that have already managed to reach 3400Mhz with 1.42v.
I currently use the 3200 Cl16 1.35V.


----------



## Nighthog

ProjectV8 said:


> *HX434C19FB2K2/16* = Micron Single Side and I believe to be B-die.
> 
> I do not think it's a bad decision to choose these memory modules.
> Micron chips have a high overclocking power.
> I have two Hyper X modules Micron B-die 2400 CL15 1.2v that have already managed to reach 3400Mhz with 1.42v.
> I currently use the 3200 Cl16 1.35V.


Micron B-die on these as well? My current Corsair says Micron B-die, though dual-rank. Need 1.46-1.47Volts to reach 3200Mhz on them though.
Will have to see when they arrive.


----------



## BadRobot

Jaju123 said:


> Just FYI, motherboard makes a huge difference.
> Went from a MSI gaming carbon pro x370 to a Asus Crosshair VII hero and i can suddenly run 3600mhz cl15 no problem, or 3466 very low latency.
> 
> Before I couldn't even run 3600 without instant horrific memory errors in memtest or failures in prime95. Same for 3466. Now both are solid as a rock at the same timings or better.
> 
> On a 3600mhz cl15 b die kit btw.
> 
> Sent from my CLT-L09 using Tapatalk


Yeah but ram can only go so far right? I have an MSI x370 Gaming Pro and the ram is rated for 2800CL14 on it's XMP profile. Just getting it to anywhere close to 3600 seems almost impossible.


----------



## Jaju123

BadRobot said:


> Yeah but ram can only go so far right? I have an MSI x370 Gaming Pro and the ram is rated for 2800CL14 on it's XMP profile. Just getting it to anywhere close to 3600 seems almost impossible.


My ram is 3600 cl15 rated. However, I spoke too soon. It actually wasn't stable.

Sent from my CLT-L09 using Tapatalk


----------



## matthew87

How frequently has VTTDDR voltage needed to be tweaked for stability?

For the past 3-4 days i've been trying to put the finishing tweaks on my 3466mhz memory O/C to get it completely stable. A HCI Memtest run of 400% would usually yield around 5-10 errors in total, felt like i was close and just needed to tweak a few settings but for the life of me could not nail down which settings needed to be refined. I tried lowering and increasing SoC and DRAM voltages, substantially loosening timings, ProcODT, CAD ohms, nothing had any positive impact and either was indifferent or made things worse. Even tried changing from older C6H bios and AGESA versions, nothing. 

Then I manually set VTTDDR and presto, 1520% HCI run at 3466mhz without a single error. Backed up again with another 400% pass and 1 hour of GSAT. It's stable. 

I don't recall reading to much that VTTDDR could have such a dramatic impact.


----------



## Anty

Did you set it exactly to 50% or bump it up (or down) a notch?
I also had more luck with VTT set manually just above default 50% (I took average of lowest and highest VDRAM shown by HWINFO and voila ).


----------



## PC loyalist

First Ryzen 2 post?

PC loyalist--R5 [email protected] 1.056v---BIOS 4009---HCI---600%---G.skill F4-3733C17Q-4GTZ

only using 2 Dimms, so 8GB in total

Tried to get to XMP speed 3733 but would error out at speed >3533. Any idea if it is my Asus strix B350-i motherboard or I have reached the limit of my memory controller?


----------



## matthew87

Anty said:


> Did you set it exactly to 50% or bump it up (or down) a notch?
> I also had more luck with VTT set manually just above default 50% (I took average of lowest and highest VDRAM shown by HWINFO and voila ).


Bumped it down just under 50%

Absolutely frustrated trying to get this memory over clock stable. The same settings that a few days ago were solid enough to pass 1 hour of GSAT and 1500% of HCI Memtest and multiple reboots now fail almost immediately. Within 5 minutes i'll get errors in either app.

I"ve changing ProcODT between 40-60ohm, upping DRAM and SoC voltage, SoC LLC Auto and levels 2 and 3, reducing SoC and DRAM voltage, upping DRAM Boot voltage, increasing and decreasing VTTDDR... Nothing works, the once stable settings are now completely broken. I also tried reloading the overclock saved profile and performing a cold boot. It feels like there's some auto memory training settings that have now changed but for the life of me i can pin what. 

Anyone got any suggestions on how a once stable memory OC can back flip so dramatically and any ideas to try and fix this?


----------



## cameronmc88

I'm using the google memory test via Linux bash from first page and it suggests 90% of available memory.. So I'm using like 89% and in Hwinfo it shows 7% page file used does this mean 89% of available is too much?


----------



## Nighthog

Nighthog said:


> Decided to make a surprise decision to buy some new memory out of the blue.
> 
> I want to test out some new memory kits just released from Kingston.
> 
> *HX434C19FB2K2/16*
> 
> 2X DDR4 3466Mhz 2x8GB CL19 @ 1.2V
> 
> Probably a bad decision but that 1.2 Volts sparked my interest. Gonna see how they fare, if they will work at all and see what kind of chips they might have.


I got these delivered and they booted right away... Tested 1 kit first.

Load XMP1 and presto! 

They are Micron E-die 16nm. Single-rank.

EDIT: No problems either with both kits installed @ 3466Mhz for 32Gb with AUTO XMP1.


----------



## harkinsteven

These are my memory timings but I can't get it the PC to boot into windows with 1t command rate. Has anyone got any suggestions on what I can do to boost stability? Thanks.


----------



## LicSqualo

harkinsteven said:


> These are my memory timings but I can't get it the PC to boot into windows with 1t command rate. Has anyone got any suggestions on what I can do to boost stability? Thanks.


Try with Geardown Mode Enabled and you will able to have the 1T comand rate.


----------



## harkinsteven

LicSqualo said:


> Try with Geardown Mode Enabled and you will able to have the 1T comand rate.


Thanks. I'll give it a go.

Edit. Booted no problem now. Thanks.


----------



## Shaav

> Nothing works, the once stable settings are now completely broken.


Yeah, same here. I solved the problem by adjusting the rTT values. Before I had to set them to RZQ/7, RZQ/3, RZQ/1 now I have to set them to RZQ/5, - , -


----------



## Nighthog

I have my memory now at 3600Mhz.

Though I've been trying to just get more speed not tighten timings thus far.
Seems I just needed to adjust my *DrvStr* values and *ProcODT* with a small increase in voltage to reach the higher speeds. *40.0Ohm* seems to do the trick for all values with testing thus far.
These kits are much easier to play with than my old kit.

I noticed my CPU IMC needed extra voltage @ 3600Mhz to not freeze the computer when I started my memory testing for errors. (stock + *0.042V offset* = 1.128~1.140 CPU VCORE SOC)

3533Mhz needed only 1.21Volts
3600Mhz @ 1.24Volts ----> *1.300V*

_... or scrap that 1...2 errors @ 70% coverage. small tweak still needed. Best result thus far though_

1.300V did the trick it seems. Tested various other things before I just gave up an added more voltage in the end.

EDIT: Testing 18.21.21.21.42.78... tWRWRSCL/tRDRDSCL 4/4 @ 3600Mhz 1.300V. (seems a odd error now and then per 50% that needs elimination with tweaking)
Lower than 4 in xxxxSCL gives huge issues and lower than 21 in primary timings doesn't boot.

EDIT2: 1.320V did the trick for above 18.21.21.21.42.78... 4/4, MemTest @ 100% Coverage for a first.


----------



## Anty

But what is the sense of pushing freq so high while having so bad timings?


----------



## Trender

ASRocks agesa 2000 series BIOS are pure trash (at least x370 killer sli) I had to downgrade bios to agesa 10006b. I though it'd get solved with a 2000 series CPU but dear god was I wrong.
I went from 3333 MHz with bios pre 2000 series on my 1700 to barely get stable 3200 mhz... I hope some bios come fast but Its been like that since first bios of january or so 
(now i got my new 2700x testing 3000-3200 mhz...)


----------



## ScorpMCP

The Sandman said:


> If this was meant for me...
> With my 1800x I could not run Geardown Disabled with this clock, even up to UEFI 0001.
> Also been trying with my 2700x and so far no luck with disabling it and maintaining stability.
> At least on the 2700x it appears to have more headroom. Just haven't had enough time to get there yet.
> 
> Might start here on Geardown Mode http://www.overclock.net/forum/26711945-post33563.html
> I know there is more but couldn't locate it about 1T and 2T (the NEW site strikes again lol)


Hey thanks for the link man, i found this snippet about geardown mode on https://community.amd.com/community/gaming/blog/2017/05/25/community-update-4-lets-talk-dram as i suspected it overrides the command rate set while enabled.

After countless reboots and tinkering i got it [email protected] 3533-14-15-14-34 1T. Not as tight as I would like it, still some tweaking to do, maybe its the 4 sticks holding me back.

ScorpMCP--R7 [email protected] 1.16v---BIOS 4009---HCI---200%---2x G.skill F4-3200C14D-16GFX


----------



## Anty

SOC 1.6V ????


----------



## CJMitsuki

ScorpMCP said:


> Hey thanks for the link man, i found this snippet about geardown mode on https://community.amd.com/community/gaming/blog/2017/05/25/community-update-4-lets-talk-dram as i suspected it overrides the command rate set while enabled.
> 
> After countless reboots and tinkering i got it [email protected] 3533-14-15-14-34 1T. Not as tight as I would like it, still some tweaking to do, maybe its the 4 sticks holding me back.
> 
> ScorpMCP--R7 [email protected] 1.6v---BIOS 4009---HCI---200%---2x G.skill F4-3200C14D-16GFX





Anty said:


> SOC 1.6V ????



Im hoping 1.6v SoC is a typo but if not Id suggest you change that immediately...If you are even able to use your computer anymore that is...


----------



## Anty

If he won't reply tomorrow it means it was not a typo :skull:


----------



## CJMitsuki

Anty said:


> If he won't reply tomorrow it means it was not a typo :skull:



Oh, with that voltage he is 100% ******* something up if not a typo. He probably had amazing stability for the few moments before his mobo turned into a toaster oven


----------



## ScorpMCP

CJMitsuki said:


> Im hoping 1.6v SoC is a typo but if not Id suggest you change that immediately...If you are even able to use your computer anymore that is...


lol i just woke up and realized the typo. Yes it was supposed to say 1.16


----------



## Nighthog

Anty said:


> But what is the sense of pushing freq so high while having so bad timings?


Testing everything takes time. Speed was first then timings.
Though I still am running better timings @ 3600Mhz than [email protected] these were rated for with a little extra voltage right now.


----------



## Trender

Guys any help? I can't even get 3200 stable with ryzen 2000 BIOSs (asrock x370 killer sli). They're just awful since 1st one released in january, but I had my 1700 so I downgraded back to september bios iirc.

So I got this week my 2700X and well ofc I had to upgrade to these BIOS and theyre awful, I came from 3333 MHz stable with my pre-2000 bios to now 9 second unstable 3200...
Thy're so bad if I reset mobo then put the memory settings I get up to 12 mins stables(stress) but then after 1st reboot it never pass 9 seconds, I tried stilts setting and ryzen calculator settings + all tweaks I could try and 0 nothing all crash. I will never buy another asrock mobo unless they fix this. 
And im not the only one that can't get this asrock x370 killer sli motherboard stable with the new ryzen 2000 bios: https://elchapuzasinformatico.com/2018/04/amd-ryzen-7-2700x-review/ (read red Note
(my 1700 was just as bad if not worse with these bios, but I could downgrade and use old bios...)


----------



## Trender

I just can't get it stable with Ryzen 2000 BIOS.
Look I haven't dont anything but just a reboot and can't get over 1 min stable just right after I got 12 mins and rebooted. And most of the times can't get over 9 second.
I think im going open a new thread about this I cant use my 2700X with this mobo


----------



## ScorpMCP

Trender said:


> Guys any help? I can't even get 3200 stable with ryzen 2000 BIOSs (asrock x370 killer sli). They're just awful since 1st one released in january, but I had my 1700 so I downgraded back to september bios iirc.
> 
> So I got this week my 2700X and well ofc I had to upgrade to these BIOS and theyre awful, I came from 3333 MHz stable with my pre-2000 bios to now 9 second unstable 3200...
> Thy're so bad if I reset mobo then put the memory settings I get up to 12 mins stables(stress) but then after 1st reboot it never pass 9 seconds, I tried stilts setting and ryzen calculator settings + all tweaks I could try and 0 nothing all crash. I will never buy another asrock mobo unless they fix this.
> And im not the only one that can't get this asrock x370 killer sli motherboard stable with the new ryzen 2000 bios: https://elchapuzasinformatico.com/2018/04/amd-ryzen-7-2700x-review/ (read red Note
> (my 1700 was just as bad if not worse with these bios, but I could downgrade and use old bios...)


What is your voltages on dram,soc and VTTDDR? Try bumping ProcODT to 48, RTTNOM to RZQ7, see if that helps, if not try loosening timings a little, like; TRAS: 34, TRRDL 9, tRDRDSCL/tWRWSCL 3/3,twrwrsd/d 7/7 and play around a bit and check if it improves.


----------



## ScorpMCP

Updated 3533mhz 32gb, tightened timings down and tested it more thoroughly,
runs smooth and snappy 

ScorpMCP--R7 [email protected] 1.16v---BIOS 4012---HCI---400%---2x G.skill F4-3200C14D-16GFX


----------



## Trender

ScorpMCP said:


> What is your voltages on dram,soc and VTTDDR? Try bumping ProcODT to 48, RTTNOM to RZQ7, see if that helps, if not try loosening timings a little, like; TRAS: 34, TRRDL 9, tRDRDSCL/tWRWSCL 3/3,twrwrsd/d 7/7 and play around a bit and check if it improves.


Tried them but it just didnt made a difference, it got unstable so fast at 9 secs.
Voltages: Tried them all from 1.30 to 1.40V, vsoc tried also everything from 1.05 to 1.15, vttddr is half vdram.
About the ProcODT and stuff I tried it and looks like higher OHms just makes it worse, looks like my RAM( samsung [email protected] 2x8gb single rank) just wants 43.6 OHms, lower doesnt boots and higher makes it worse


----------



## ScorpMCP

Trender said:


> Tried them but it just didnt made a difference, it got unstable so fast at 9 secs.
> Voltages: Tried them all from 1.30 to 1.40V, vsoc tried also everything from 1.05 to 1.15, vttddr is half vdram.
> About the ProcODT and stuff I tried it and looks like higher OHms just makes it worse, looks like my RAM( samsung [email protected] 2x8gb single rank) just wants 43.6 OHms, lower doesnt boots and higher makes it worse


yea about the termination block, I suggested 48 just to match rttpark , maybe try changing the CAD_Bus drive strength block from the 24-24-24-24 to something like 40-40-40-40 or 40-20-40-40, not neccessarily for the higher ohms, just to make them speak at close to the same volume, might make the signal "sound" clearer, if you catch my drift. I think rttnom you should enable atleast, if you keep testing to help get rid of excess noise.


----------



## Trender

ScorpMCP said:


> yea about the termination block, I suggested 48 just to match rttpark , maybe try changing the CAD_Bus drive strength block from the 24-24-24-24 to something like 40-40-40-40 or 40-20-40-40, not neccessarily for the higher ohms, just to make them speak at close to the same volume, might make the signal "sound" clearer, if you catch my drift. I think rttnom you should enable atleast, if you keep testing to help get rid of excess noise.


Nope fam  it just ran stress until 18 mins this time (my record with these bios is 27 mins...) and then error so I rebooted and as always it failed stress at 9 secs (most of the time lul) then other times I managed to 10 secs and 17 secs such shame. 
I think these BIOS are bugged because I don't know why it stress test some mins like 12-20 mins and then after I reboot pc withouth chaning absolutely anything and values are the same checking ryzen timing check and bios yet it fail stress test at 9 secs and is unstable :/
---------------------------------------------------------------------
Another test:
Runs "good":
http://www.overclock.net/forum/attachment.php?attachmentid=177057&thumb=1
Then I just restart:
http://www.overclock.net/forum/attachment.php?attachmentid=177065&thumb=1
and boila, unstable.
And its like that until I reset bios and re-type everything again....


----------



## untouchable247

Hey guys, what's the BEST possible 16GB ram kit out there for a 2700x on a Crosshair VII Hero?

F4-3200C14D-16GTZRX? F4-3200C14D-16GFX? Are they the same?

F4-3600C15D-16GTZ? F4-4133C17D-16GTZR?

Or is the silicon lottery the determining factor in the end and all of those kits perform similarly with the same cpu and board?


----------



## ZeNch

untouchable247 said:


> Hey guys, what's the BEST possible 16GB ram kit out there for a 2700x on a Crosshair VII Hero?
> 
> F4-3200C14D-16GTZRX? F4-3200C14D-16GFX? Are they the same?
> 
> F4-3600C15D-16GTZ? F4-4133C17D-16GTZR?
> 
> Or is the silicon lottery the determining factor in the end and all of those kits perform similarly with the same cpu and board?


F4-3200C14D-16GTZRX? F4-3200C14D-16GFX? Are they the same? *I think no, in your place i go to Flare version*
F4-3600C15D-16GTZ? F4-4133C17D-16GTZR? *3600mhz (stable) is the max speed i think, but 4133 kit give you better timmings sure*

Chips?
TridentZ 3200> i dont know (b-die probably)
Flare> B-die
TridentZ 3600> Samsung (i dont know if B-die or other)
Trident 4133> i dont know

Today with the tools i try to buy 4133 kit and set it to 3200/3600mhz and super low timming.
what board have you? x470 boards are better to memory overclock.


----------



## gupsterg

untouchable247 said:


> Hey guys, what's the BEST possible 16GB ram kit out there for a 2700x on a Crosshair VII Hero?
> 
> F4-3200C14D-16GTZRX? F4-3200C14D-16GFX? Are they the same?
> 
> F4-3600C15D-16GTZ? F4-4133C17D-16GTZR?
> 
> Or is the silicon lottery the determining factor in the end and all of those kits perform similarly with the same cpu and board?


Trident Z and Flare X you have stated, besides heatspreader are the same.

Trident Z non X will function as good if not better than the kit with X (ie for AMD). AFAIK F4-3600C15 is best bin and next would be F4-3200C14.

All stated RAM kits should be Samsung B die, single rank/sided, ie what Ryzen favours the most. You will be more CPU/IMC limited than board IMO. I've used 5 differing Ryzen CPUs on same board/RAM and MHz they attain, timings, SOC voltages, etc are somewhat varied.

The F4-3200C14D-16GTZ I have had ~3500MHz out of. IMO the best profile I've experienced with my HW, taking various aspects into context, is 3400MHz C15 using settings of SOC 1.031V VDIMM 1.365V. The screenie below is HCI v6.0, this has differing % over time than other versions (ie lower % for greater time).



Spoiler


----------



## untouchable247

ZeNch said:


> F4-3200C14D-16GTZRX? F4-3200C14D-16GFX? Are they the same? *I think no, in your place i go to Flare version*
> F4-3600C15D-16GTZ? F4-4133C17D-16GTZR? *3600mhz (stable) is the max speed i think, but 4133 kit give you better timmings sure*
> 
> Chips?
> TridentZ 3200> i dont know (b-die probably)
> Flare> B-die
> TridentZ 3600> Samsung (i dont know if B-die or other)
> Trident 4133> i dont know
> 
> Today with the tools i try to buy 4133 kit and set it to 3200/3600mhz and super low timming.
> what board have you? x470 boards are better to memory overclock.


The ram is for a ASUS Crosshair VII Hero (no wifi) board and a Ryzen 2700x.

I couldn't find any reports of the 4133 Mhz kit being tested with a x470 board. ASUS claim the board supports DDR4-3600 (OC). 4133 underclocked to 3600Mhz with low timings sounds good but is realistic?


----------



## untouchable247

gupsterg said:


> Trident Z and Flare X you have stated, besides heatspreader are the same.
> 
> Trident Z non X will function as good if not better than the kit with X (ie for AMD). AFAIK F4-3600C15 is best bin and next would be F4-3200C14.


Thanks for your answer, really helpful.

So the "Ryzen ready", "full AMD support" is nothing but marketing, same chips, same bins, different labeling and higher price?!


----------



## gupsterg

untouchable247 said:


> Thanks for your answer, really helpful.
> 
> So the "Ryzen ready", "full AMD support" is nothing but marketing, same chips, same bins, different labeling and higher price?!


No problem and indeed.

I also have F4-3200C14Q-32GVK, again not AMD ready, not even on QVL for ASUS ZE, bought open box as it was an unmissable deal. I have had 3466MHz C15 out of them in that board.

I inserted them in my ASUS C6H. I did not even undo the 4.0GHz 3400MHz C15 profile before swapping RAM. Rig posted 1st time and went to OS. I ran HCI Memtest v6.0 and quickly had 1 error, I increased SOC only, 1.031V to 1.037V. So far ~2hrs passed with 0 errors.



Spoiler












*Note:* Ryzen Timings Checker has some misread values up top from UEFI actual setup.



You want easiest ride with Ryzen concerning RAM, just make sure RAM IC is Samsung B die.


----------



## matthew87

Anyone able to offer some advice on cold boot issues with my mem overclock?

GSkill F4-3200C14 Trident Z memory, overclocked to 3466mhz C15, stable and can pass GSAT and 400-1500% HCI Memtest. 

The overclock becomes unstable each and every time A/C is disconnected and the PC goes through cold boot. So BIOS settings that were good enough to see the PC pass 8+ hours of stress testing and benchmarking immediately fail and turns to rubbish if the PC has to go through cold boot and POST. Almost immediately i'll start getting memory copy errors in HCI Memtest after a cold boot. 

This is on a C6H running 6101 BIOS. 

Rebooting or booting from warm state is fine. Memory OC only becomes unstable when cold booting is added to the mix. 

When checking HWInfo and Ryzen Timing Checker there's absolutely no difference in voltages, timings or any settings between stable and unstable stress testing runs. Only the fact that the PC went through a cold boot. Tearing my hair out trying to figure out WHY this is happening. I've manually set SoC, VDIMM, VDDP, VTTDRAM, VDIMM Boot, and complete memory timings including CAD Bus, GearDown and ProcODT.

1500% HCI Memtest pass to failing within 30 seconds after a cold boot.


----------



## Shaav

Hey guys,

Don't you think it's too timeconsuming to browse the whole thread in order to find the information how other people overclocked their RAM? I think it would be a good idea to have an excel sheet where all the overclocking results are being collected (including *all necessairy information like IC-type, voltages, resistances etc.*). This will hopefully help some people to overclock their modules even further.

I would appreciate it if you would enter your results in the following excel sheet.
https://docs.google.com/spreadsheets/d/1HKPVfDcFO-aieAOXHFQZp15rwWadbPTVDNgO8vtyDCM/edit#gid=0

If you want to know the IC-type of you RAM module you have to install Typhoon burner: http://www.softnology.biz/files/thphn130.zip
All other information are shown in the BIOS or can be displayed with Ryzen Timing Checker: https://www.techpowerup.com/download/ryzen-timing-checker/

If I forgot a collum where a neccesairy voltage, resistance etc. should be listet, let me know.


----------



## gupsterg

matthew87 said:


> Anyone able to offer some advice on cold boot issues with my mem overclock?
> 
> GSkill F4-3200C14 Trident Z memory, overclocked to 3466mhz C15, stable and can pass GSAT and 400-1500% HCI Memtest.
> 
> The overclock becomes unstable each and every time A/C is disconnected and the PC goes through cold boot. So BIOS settings that were good enough to see the PC pass 8+ hours of stress testing and benchmarking immediately fail and turns to rubbish if the PC has to go through cold boot and POST. Almost immediately i'll start getting memory copy errors in HCI Memtest after a cold boot.
> 
> This is on a C6H running 6101 BIOS.
> 
> Rebooting or booting from warm state is fine. Memory OC only becomes unstable when cold booting is added to the mix.
> 
> When checking HWInfo and Ryzen Timing Checker there's absolutely no difference in voltages, timings or any settings between stable and unstable stress testing runs. Only the fact that the PC went through a cold boot. Tearing my hair out trying to figure out WHY this is happening. I've manually set SoC, VDIMM, VDDP, VTTDRAM, VDIMM Boot, and complete memory timings including CAD Bus, GearDown and ProcODT.
> 
> 1500% HCI Memtest pass to failing within 30 seconds after a cold boot.


See if bumping SOC, VDIMM/VBOOT help.

I have same mobo, RAM and using same UEFI. Dunno if CPU differ; mine is R7 1800X (Batch UA 1737SUS).

I had A/C removed from rig all night. Flipped PSU power on this morning. Booted F4-3200C14Q-32GVK at 3400MHz C15 without issues. This is the same as when I use F4-3200C14D-16GTZ for that setup and even 3466MHz is fine.


----------



## Trender

matthew87 said:


> Anyone able to offer some advice on cold boot issues with my mem overclock?
> 
> GSkill F4-3200C14 Trident Z memory, overclocked to 3466mhz C15, stable and can pass GSAT and 400-1500% HCI Memtest.
> 
> The overclock becomes unstable each and every time A/C is disconnected and the PC goes through cold boot. So BIOS settings that were good enough to see the PC pass 8+ hours of stress testing and benchmarking immediately fail and turns to rubbish if the PC has to go through cold boot and POST. Almost immediately i'll start getting memory copy errors in HCI Memtest after a cold boot.
> 
> This is on a C6H running 6101 BIOS.
> 
> Rebooting or booting from warm state is fine. Memory OC only becomes unstable when cold booting is added to the mix.
> 
> When checking HWInfo and Ryzen Timing Checker there's absolutely no difference in voltages, timings or any settings between stable and unstable stress testing runs. Only the fact that the PC went through a cold boot. Tearing my hair out trying to figure out WHY this is happening. I've manually set SoC, VDIMM, VDDP, VTTDRAM, VDIMM Boot, and complete memory timings including CAD Bus, GearDown and ProcODT.
> 
> 1500% HCI Memtest pass to failing within 30 seconds after a cold boot.


I have same exact problem: http://www.overclock.net/forum/10-a...memory-stability-thread-150.html#post27330665
But mine is just after a simple restart :/. And its like that until I reset mobo...


----------



## matthew87

gupsterg said:


> See if bumping SOC, VDIMM/VBOOT help.
> 
> I have same mobo, RAM and using same UEFI. Dunno if CPU differ; mine is R7 1800X (Batch UA 1737SUS).
> 
> I had A/C removed from rig all night. Flipped PSU power on this morning. Booted F4-3200C14Q-32GVK at 3400MHz C15 without issues. This is the same as when I use F4-3200C14D-16GTZ for that setup and even 3466MHz is fine.


Thanks Gupsterg. 

I've well and truly gone through SOC voltage, all the way from 1.05 - 1.2v in an attempt to resolve this. 

Same for DRAM voltage, 1.38v - 1.45v for 3466mhz. 

What i haven't played around too much with was VBOOT voltage. I've just bumped that up to 1.43v (up from 1.4v) and after a cold boot it's at least been able to pass 40% HCI Memtest without error. That already seems more positive than all my previous results where i'd get an error within 60 seconds, more often than not before the test had even reached 1% and certainly within 10%. 

Is it normal for Ryzen and the C6H to still do a second 'POST' when cold booting with overclocked memory? I thought it was, as this is the behaviour my motherboard has always exhibited. When cold booting it will power up, fans spin etc for a two or so seconds, then power rests and then after 5-10 seconds it will successfully POST and show monitor output. 

I thought the cold boot bug was specific to when the PC tried to post, kept failing and then it would reset to factory default speeds and 2133mhz DRAM. At VBOOT of 1.4v I didn't have that issue, it would still POST at 3466mhz speeds after the fist automated reboot. I can't see what if anything upping VBOOT to 1.43v has changed, as it's still booting from cold the same as before, but so far it's stable.


----------



## Dr. Vodka

matthew87 said:


> Thanks Gupsterg.
> 
> I've well and truly gone through SOC voltage, all the way from 1.05 - 1.2v in an attempt to resolve this.
> 
> Same for DRAM voltage, 1.38v - 1.45v for 3466mhz.
> 
> What i haven't played around too much with was VBOOT voltage. I've just bumped that up to 1.43v (up from 1.4v) and after a cold boot it's at least been able to pass 40% HCI Memtest without error. That already seems more positive than all my previous results where i'd get an error within 60 seconds, more often than not before the test had even reached 1% and certainly within 10%.
> 
> Is it normal for Ryzen and the C6H to still do a second 'POST' when cold booting with overclocked memory? I thought it was, as this is the behaviour my motherboard has always exhibited. When cold booting it will power up, fans spin etc for a two or so seconds, then power rests and then after 5-10 seconds it will successfully POST and show monitor output.
> 
> I thought the cold boot bug was specific to when the PC tried to post, kept failing and then it would reset to factory default speeds and 2133mhz DRAM. At VBOOT of 1.4v I didn't have that issue, it would still POST at 3466mhz speeds after the fist automated reboot. I can't see what if anything upping VBOOT to 1.43v has changed, as it's still booting from cold the same as before, but so far it's stable.


What produces double booting after the cold boot fix got implemented months ago in 9920/3008/etc is setting VBOOT to anything other than auto. If your board boots at 3466MHz with VBOOT at auto, then don't bother with it and save yourself that extra stop/start on your hard drive's motor.

Try setting your CAD bus to 30-30-30-30 (Stilt's recommendation back in the day for stabilizing >3200MHz memory) or 40-40-40-40.

40-40-40-40 got rid of almost every cold boot failure back in 1xxx BIOSes for my 1700 and my 3466MHz memory, so that's a tried and true setting, at least for me.

Use Stilt's 3200MHz or 3466MHz profile with proper subtimings (they're built in), it's usually more stable overall and of course much more performant than loading the XMP profile and leaving auto subtimings...

Geardown mode can be your friend in these cases, when enabled you'll be forced to use an even CAS latency and 1T command rate, so it'll be either 14 or 16 for you. It's effectively a "1.5T" mode, reducing load on both the IMC and the memory.


----------



## matthew87

Dr. Vodka said:


> What produces double booting after the cold boot fix got implemented months ago in 9920/3008/etc is setting VBOOT to anything other than auto. If your board boots at 3466MHz with VBOOT at auto, then don't bother with it and save yourself that extra stop/start on your hard drive's motor.


Thanks, hadn't seen that mentioned. I've put it back to auto and indeed no more double booting. 



> Try setting your CAD bus to 30-30-30-30 (Stilt's recommendation back in the day for stabilizing >3200MHz memory) or 40-40-40-40.


I've tried the Stilt's and Ryzen DRAM Calculator's custom (based of thaiphoon burner), safe and fast settings. 

That includes:
SoC - 1.05-1.15v
DRAM 1.35-1.45v
ProcODT between 43-60ohm 
CAD Bus: 20-20-20-20 | 30-30-30-30 | 30-30-40-60 | 20-20-30-30
VTTP, VTT DDR, and CLDO_VDDP voltages as recommended by Ryzen DRAM Calculator, auto and manual adjustments
Geardown Auto, enabled and disabled

Nothing has been able to resolve the issue of random memory errors after cold boots.


----------



## gupsterg

matthew87 said:


> Thanks Gupsterg.
> 
> I've well and truly gone through SOC voltage, all the way from 1.05 - 1.2v in an attempt to resolve this.
> 
> Same for DRAM voltage, 1.38v - 1.45v for 3466mhz.
> 
> What i haven't played around too much with was VBOOT voltage. I've just bumped that up to 1.43v (up from 1.4v) and after a cold boot it's at least been able to pass 40% HCI Memtest without error. That already seems more positive than all my previous results where i'd get an error within 60 seconds, more often than not before the test had even reached 1% and certainly within 10%.
> 
> Is it normal for Ryzen and the C6H to still do a second 'POST' when cold booting with overclocked memory? I thought it was, as this is the behaviour my motherboard has always exhibited. When cold booting it will power up, fans spin etc for a two or so seconds, then power rests and then after 5-10 seconds it will successfully POST and show monitor output.
> 
> I thought the cold boot bug was specific to when the PC tried to post, kept failing and then it would reset to factory default speeds and 2133mhz DRAM. At VBOOT of 1.4v I didn't have that issue, it would still POST at 3466mhz speeds after the fist automated reboot. I can't see what if anything upping VBOOT to 1.43v has changed, as it's still booting from cold the same as before, but so far it's stable.


Seems like you have explored SOC/VDIMM to resolve issue  . VBOOT/VDIMM should be set in sync.

The second post is normal when A/C has been removed from board. Even on early UEFIs greater than >2666MHz caused it (besides what Dr Vodka has stated). It is basically mobo posting to setup Embedded Controllers as needed. My P5K (ancient Intel) board does this even if A/C is removed or not. My M7R (another Intel board) does same as C6H if A/C is removed, the ZE does the same, will let you know how C7H is but expect it to be the same. You'll also find on ROG forum even the latest Intel boards do as C6H does.

Cold boot bug often cropping up in C6H thread can be where A/C was removed from board and not. Basically memory training fails on post. I had both cases. I shall PM you a UEFI, try that.


----------



## matthew87

Plot thickens. 

Last night, no issues whatsoever with errors in HCI Memtest or GSAT. Shutdown, restarts, cold boots, no memory errors.

Cold booted this morning, within 5 seconds there were half a dozen errors in Memtest. Restarted computer, again errors. Shut the PC down, left it for 5 minutes, turned it back on and so far it's passed 200% HCI Memtest without error. 

In short:

Stable last night through shutdown, restart and even cold boots. Passed 3 rounds of 200% Memtest and 2 runs of GSAT. 
Errors galore this morning after a cold boot. To the point within 5 seconds HCI Memtest recorded half a dozen errors. 
Restarting a couple times did nothing to resolve memory errors
A complete shutdown however results in no more memory errors. I did not disconnect A/C

Any ideas? 

I assume it must be a memory training issue, that intermittently some obscure memory or voltage settings aren't being set at POST.

Worth perhaps also mentioning that it's almost Winter here, so last night was a little chilly at around 10 degrees c.


----------



## mth21

STRIX B-350F BIOS 4011+ RYZEN 5 1600 + Corsair Vengeance LPX 16GB (2x8GB) DDR4 DRAM 3000MHz C15 (15-17-17-35)

Anyone here got the same kit? i cant got my kit to 2933/3000MHz without losen the timing to 16-19-19-36


is there any way to tighten the timing?

thanks


----------



## i_max2k2

Hi all,

I'm getting this ram F4-3200C14D-32GVK, 2x16gb dual rank samsung b die on 3200Mhz 14-14-14-34 timings. I would be putting this on Asus Crosshair VII X470, I was wondering if anyone has this or any ram on this page
https://www.newegg.com/Product/Prod...d=1&N=100007611 600327642 600561668 600546709

What has been your luck with this memory, any tips to get them to stock and then overclock them more?

Thanks


----------



## thanos999

finally been looking for a thread on how to overclock the ramm for a ryzen chip
i need help never done memory timing befor and also this is my first amd build ever

here are the specs chip is ryzen 5 2600 watercooled using a corsair h100 aio the board is an asus prime x470 pro memory is corsair vengeance lpx 16gig 2666mhz ddr4 cmk16gx4m2a2666c16w gpu is evga gtx 760 which is going to be replaced soon with either a gtx 1070 or 1070 ti

i just need help overclocking the ramm what settings do i change what settings do i leave alone?

here is a cpuz validation off my overclocock 
core voltage was at 1.525 when i did the run


----------



## hsn

i have corsair dominator platinum special edition 2x16gb ddr4 3200 cl14-16-16 (samsung bdie dual rank)

just test with stessapptest 1 hour running on 3466 cl14-15-15-30


----------



## NightAntilli

gupsterg said:


> Trident Z and Flare X you have stated, besides heatspreader are the same.
> 
> Trident Z non X will function as good if not better than the kit with X (ie for AMD). AFAIK F4-3600C15 is best bin and next would be F4-3200C14.
> 
> All stated RAM kits should be Samsung B die, single rank/sided, ie what Ryzen favours the most. You will be more CPU/IMC limited than board IMO. I've used 5 differing Ryzen CPUs on same board/RAM and MHz they attain, timings, SOC voltages, etc are somewhat varied.
> 
> The F4-3200C14D-16GTZ I have had ~3500MHz out of. IMO the best profile I've experienced with my HW, taking various aspects into context, is 3400MHz C15 using settings of SOC 1.031V VDIMM 1.365V. The screenie below is HCI v6.0, this has differing % over time than other versions (ie lower % for greater time).
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 177401
> 
> 
> View attachment 177409


How big are the chances to get certain memory kits stable that are not listen on the QVL of a motherboard? Of the two best kits you mentioned (F4-3600C15 and F4-3200C14) the former is not mentioned at all on the Asrock X470 Taichi QVL for Pinnacle Ridge, and the latter is supported at only 2933 MHz. Is it reasonable to expect either of them to be able to run at their rated speeds and timings at all?


----------



## gupsterg

@matthew87

If room temp is 10C you may find Ryzen Gen 1 suffers with that. See the C6H OC guide, page 5.

@NightAntilli

IMO they should gain >3200MHz easily.

F4-3200C14Q-32GVK is not on ASUS ZE QVL, below is HCI v6.0 ~8hrs run @ 3466MHz C15 1T.



Spoiler














That same kit is not on ASUS C6H QVL. I had a profile determined using F4-3200C14D-16GTZ, I swapped to F4-3200C14Q-32GVK, a 1 step bump in SOC got me HCI pass, 1 step bump in ProcODT got me P95 stable. So not on QVL and doubled RAM amount  and only 1 step each up. I would have done more testing for that situation, but wanted to move to PR+C7H.



Spoiler






















All I'm seeing is Samsung B die =  , then if you've gone 8GB dimms (which should be single rank/sided) =  .

The G.Skill kits seem the business. I wouldn't pay up for "AMD Ryzen" specific.


----------



## NightAntilli

@Gupster Ok thank you. Would 4x 8GB for 32GB total reach >3200 MHz also with reasonable timings, or is it limited to two modules? Just trying to get a sense of the memory limits before I buy it. No sense in spending a bunch of money to ultimately have it running at slow speeds.


----------



## zGunBLADEz

was about time lol

32GB Kit (G.Skill F4-3600C17-16GTZR)

3466/LL almost 15hrs run for %1300+ coverage on a B350-I Strix mobo

SOC 1.00v


----------



## gupsterg

@NightAntilli

F4-3200C14Q-32GVK is 4x 8GB  . The Q denotes Quad Channel kit, the 32 denotes total GB of kit. In the screenies you'll se F4-3200C14-8GVK, basically the dimm P/N designated by G.Skill. My F4-3200C14D-16GTZ will show as F4-3200C14-8GTZ.

IMO (emphasis on opinion), Ryzen AGESA is developed enough to allow someone >3200MHz. How much more does depend on:-


CPU IMC (some seem to be more forgiving, in that take it in their stride)
Time they input to test and tweak. 3200MHz C14 has been real easy for me on C6H, C7H and ZE. Even 3333MHz is no biggie, at >3400MHz is where it seems you need to apply more time/effort.

As stated before I determined a 3400MHz C15 profile on 2 dimms (F4-3200C14D-16GTZ), swapped to 4 dimms (F4-3200C14Q-32GVK) needed a bump in SOC and ProcODT to gain stability.
@zGunBLADEz

Sweet  .


----------



## NightAntilli

Ok thanks. Guess I can go for 32GB. I'm hoping I'll be able to do at least 3200 MHz with CL14 with it.


----------



## incontempt

I'm posting this because it's 1st time to be stable with memtest, it's Kingston hyperx kit KHX3000C15D4-8GX afr, maybe someone with the same kit can give a better suggestion for the values, 1.4 volts for ram,1.1 soc ,vddp 880. It's on official non modded bios - prime b350 plus 4011


----------



## gupsterg

NightAntilli said:


> Ok thanks. Guess I can go for 32GB. I'm hoping I'll be able to do at least 3200 MHz with CL14 with it.


NP  , besides posting I read a lot of forums. My workday allows that (usually ). IMO you'd have a real potato of a setup if it can't run 3200MHz C14 on Samsung B Die, in config of 4x 8GB (single rank/sided).


----------



## Samuris

Hi guys i have ddr4 8x2go g.skill trident Z F4-4266C19-8GTZA on a asus x470-F gaming, any one have somes good timings for this memory ? thanks
i tryed with ryzen dram calculator, impossible to reach 3600mhz and be perfectly stable, can boot and launch game but i bug somes minutes after, i have actually a 2200g instead of 2700x cause i have no graphic card and i'm waiting for gtx 1180, so this apu is very cheap, i see somes video with 2200g with 3600mhz memory but it like impossible for me, so i'm actually at 3400mhz 14/14/14/14/50


----------



## zGunBLADEz

2nd run 3466LL same settings 1800% hci over 19hrs non stop.

Tried to drop tfaw and tras with no luck it error outso those are a no no i only have left to play with trcdwr/trcdrd 15 to 14
and maybe trfc from 282 to 260 how it goes from there.. 

I know for a fact my kit dont like geardown disable but looking a perf wise idk theres something fishy i have tried to disable all that and have cas 2t instead of 1t+geardown enable and i can see gain in perf.
@gupsterg what you think about that.


----------



## mth21

Corsair Vengeance LPX 16GB (2x8GB) DDR4 DRAM 3000MHz C15 (15-17-17-35)

running on 2933 MHz 16-19-19-38
@1.36V SOC 1.1V

How can i tighten my timing?

Thank you


----------



## matthew87

@gupsterg

Thanks for all your assistance, greatly appreciated.

I don't think my issue however is related to temperature or even POST/Cold boot. 

Synchronizing memory and memory boot voltages has resolved any cold boot/training issues I've had. I am confident that the PC and CPU memory controller aren't having issues training or booting my overclocked memory. Countless cold and warm boots has resulted in no additional reboots to train the memory. Further testing also suggests that the issue isn't temperature related, warm, cold, half way between, some times i can pass hours of stress testing from a cold boot/shutdown and other times it will fail immediately even when warm if the PC has been shutdown or cold booted. Even if the shutdown was for a couple of seconds and immedaitely following stress testing, the CPU wouldn't even have time to have cooled down between Windows shutting down and me pressing the power button to turn the PC back on. 

There's absolutely no rhyme or reason i can see to explain how my memory O/C can go from rock solid passing 12+ hours of stress testing to immediately unstable errors within seconds between shutdown or cold boot. If i get lucky and its a 'stable' boot, i can stress test 24/7 without issues. 

Someone suggested i try re-seating my memory and see if that helps. No idea how it could, but they swear they had similar issues as i and that resolved it.


----------



## gupsterg

@Samuris

Below in spoiler is officially support RAM MHz.



Spoiler














Below quote source link for 2nd gen Ryzen RAM MHz.



> On the tested samples, the distribution of the maximum achievable memory frequency was following:
> 
> 
> 3400MHz - 12.5% of the samples
> 3466MHz - 25.0% of the samples
> 3533MHz - 62.5% of the samples
> 
> There are clear differences in how the memory controller behaves on the different CPU specimens. The majority of the CPUs will do 3466MHz or higher at 1.050V SoC voltage, however the difference lies in how the different specimens react to the voltage. Some of the specimens seem scale with the increased SoC voltage, while the others simply refuse to scale at all or in some cases even illustrate negative scaling. All of the tested samples illustrated negative scaling (i.e. more errors or failures to train) when higher than 1.150V SoC was used. In all cases the maximum memory frequency was achieved at =< 1.100V SoC voltage.


It maybe your CPU IMC has reached it's ceiling, 3400MHz C14 is not shabby at all IMO. I would assume the Strix has memory presets within DRAM Timing Control page? be interested to know.

@zGunBLADEz

Sweet run again  . Dunno if you have seen, but I have had it sometimes on R7+C6H and TR+ZE. I'll be running HCI, all is sound, zero errors all instances. Then when I start stopping the instances I may see some error near the end  . So now I make a habit of doing a short run where I stop test after >100% and then do another >400%.

Your text about GDM has not made sense to me, sorry. If you are saying 2T benches better than 1T+GDM: On that would seem strange to me. Perhaps this is a case of there are some errors occurring at high speed RAM + 1T+GDM: On, which are not being detected by test SW we would use. As these may not be happening at 2T you see improved performance. I again this is my opinion. I have in the main used 1T GDM: Off, after 3466MHz is where usually I need to drop 1T GDM: Off and use 2T. Then as usually SOC/VDIMM gets higher side for daily use (IMO), I just stop testing at that point.

For me so far highest RAM frequency I have used on daily basis is 3466MHz C15 1T GDM: Off. Max HCI stable has been 3520MHz C16 2T. Max bench stable has been 3600MHz C16 (don't recall T but will check screenies).

My new test bed of R7 2700X+C7H has been pleasing on aspects of SOC voltage/RAM MHz scaling. For example my best Ryzen gen 1 sample needed 1.025V set in UEFI for 3400MHz, my first and so far only Pinnacle Ridge CPU is needing 0.925V in UEFI. I'm using F4-3200C14D-16GTZ on C7H, the kit I used the most on C6H.

@mth21

Use Thaiphoon Burner to get RAM IC information, it will aid you.



Spoiler











@matthew87

NP  .

Just so it's clear to me setting VBOOt/VDIMM in sync has resolved issue? And are you using UEFI 9930 or another?

Cheers


----------



## matthew87

@gupsterg

I'm still using 6101, have 9930 loaded on usb ready to use flash back however. Thought I'd give 6101 another final crack before I cut my losses and try older bios releases. I've read a few comments form other forum members suggesting the new AGESA 1.0.02(a) is not as stable as the older BIOS releases for overclocking on 1st gen Ryzen platforms. 

Yes, setting dram boot and dram voltage both to 1.42 appears to resolve any cold boot 'bug' issues. No more second reboot and training is occurring after a cold start. But this still hasn't resolved the intermittent instability.

I just got home form work, cold booted PC, had half a dozen HCI memtest errors within 30 seconds of the program starting. So i shut the PC down, started it back up and without entering BIOS or changing a single setting it's now just passed 120% HCI Memtest. 

Doing my head in.... 

Also tried removing and reinserting RAM just in case some physical connection was an issue, no difference.

BIOS settings:

VCORE = Auto
DRAM = 1.42v
DRAM Boot = 1.42v
SoC = 1.0935
Memory timings: 15-15-15-35-54-333-1T - Geardown = Disabled
LLC and all Power/Tweaker options = Auto
ProcODT and CAD Bus timings = Auto

Also tried 16-16-16-36-54-560 timings
SoC up to 1.15v
DRAM up to 1.44v
ProcODT and CAD Bus timings as recommended by Stilt and Ryzen DRAM Calculator. Including custom from Thaiphoon and the recommended, alt 1 and alt 2 in Ryzen DRAM calc.
CLDO_VDDT 
VDDP
VTTD

If i dont have any luck tonight i'll revert back to 9930 and also try 3502 BIOS


----------



## gupsterg

VBOOT is setting part of AMD code at post, which runs before ODM (ASUS). VDIMM is for after that process. The Stilt and many others have posted to keep it sync'd. Problem is due to frequency of posting in the thread and it just gets lost with in it. Just glad you got part of your problem resolved.

The board posts in differing ways for a few situations:-

i) POST from shutdown with no A/C to board.
ii) POST from shutdown with A/C to board.
iii) POST from a reset/restart.
iv) POST from sleep.

If a profile is exhibiting an issue of stability within OS from any of those, in my experience the current profile is not stable. The Stilt early on mentioned that Ryzen has the most complicated training process he has seen.

Any profile I consider using 24/7 has to pass repeat testing and with various posts. I also saw last year a profile determined in cooler ambient temps broke for RAM on increased ambient.

It just maybe 3466MHz is too much for your IMC. Based on what I experienced I believe 3466MHz is the highest gen 1 can deliver for all aspects. Max officialy gen 1 was 2666MHz, 3466MHz is 30% OC.


----------



## matthew87

gupsterg said:


> VBOOT is setting part of AMD code at post, which runs before ODM (ASUS). VDIMM is for after that process. The Stilt and many others have posted to keep it sync'd. Problem is due to frequency of posting in the thread and it just gets lost with in it. Just glad you got part of your problem resolved.
> 
> The board posts in differing ways for a few situations:-
> 
> i) POST from shutdown with no A/C to board.
> ii) POST from shutdown with A/C to board.
> iii) POST from a reset/restart.
> iv) POST from sleep.
> 
> If a profile is exhibiting an issue of stability within OS from any of those, in my experience the current profile is not stable. The Stilt early on mentioned that Ryzen has the most complicated training process he has seen.
> 
> Any profile I consider using 24/7 has to pass repeat testing and with various posts. I also saw last year a profile determined in cooler ambient temps broke for RAM on increased ambient.
> 
> It just maybe 3466MHz is too much for your IMC. Based on what I experienced I believe 3466MHz is the highest gen 1 can deliver for all aspects. Max officialy gen 1 was 2666MHz, 3466MHz is 30% OC.


You might very well be right, i have considered also dropping back down to 3400mhz or 3333mhz with tighter timings and gear down disabled. Both will still achieve a notable bandwidth and latency improvement. 

But as i've seen this PC pass 1500% HCI Memtest, 2 hours of Google Stress Test App and 4 hours of Prime95 with 13GB assigned large FFT with no errors in a single stress testing session it seems it the RAM and CPU mem controller can do 3466mhz. Perhaps i'm being naive but i wouldn't have thought if either the mem controller or RAM wasn't capable of running at 3466mhz that after all that stress testing i'd have seen an error.


----------



## gupsterg

For me Pinnacle Ridge AGESA with use on gen 1 been sweet, bare in mind at this time I only had 1 CPU to try. It nailed 4.0GHz/3400MHz C15 1T GDM: Off very easily IMO. I was keen to try tightening timings but also had PR+C7H beckoning to be used. I determined an OC based on 2 sticks of 8GB and to my surprise it even nailed it with 4 with 2 tweaks. Perhaps a good CPU, dunno.

Now on PR+C7H 3400MHz C15 was again very easy to attain. So IMO my new sweet spot to try on either gen 1 or 2 is that. Then move to tightening timings.

In both cases of HW SOC/VDIMM was nice and low, so really sound for 24/7 usage IMO.

I get what your saying about how you've tested 3466MHz and issue of erratic stability in OS based on differing POST. OS and POST stability are 2 different things IMO. Especially now as AGESA has moved forward so much. There must so much that goes on at POST regarding training that we don't know or have access to control.

You are better off resolving issue for now by dropping MHz, getting on using the PC and enjoying it. Perhaps a later UEFI will gain you what you desire  . UEFI's besides CPU microcode updates can contain IMC FW updates  .


----------



## zGunBLADEz

gupsterg said:


> @zGunBLADEz
> 
> Sweet run again  . Dunno if you have seen, but I have had it sometimes on R7+C6H and TR+ZE. I'll be running HCI, all is sound, zero errors all instances. Then when I start stopping the instances I may see some error near the end  . So now I make a habit of doing a short run where I stop test after >100% and then do another >400%.
> 
> Your text about GDM has not made sense to me, sorry. If you are saying 2T benches better than 1T+GDM: On that would seem strange to me. Perhaps this is a case of there are some errors occurring at high speed RAM + 1T+GDM: On, which are not being detected by test SW we would use. As these may not be happening at 2T you see improved performance. I again this is my opinion. I have in the main used 1T GDM: Off, after 3466MHz is where usually I need to drop 1T GDM: Off and use 2T. Then as usually SOC/VDIMM gets higher side for daily use (IMO), I just stop testing at that point.
> 
> For me so far highest RAM frequency I have used on daily basis is 3466MHz C15 1T GDM: Off. Max HCI stable has been 3520MHz C16 2T. Max bench stable has been 3600MHz C16 (don't recall T but will check screenies).
> 
> My new test bed of R7 2700X+C7H has been pleasing on aspects of SOC voltage/RAM MHz scaling. For example my best Ryzen gen 1 sample needed 1.025V set in UEFI for 3400MHz, my first and so far only Pinnacle Ridge CPU is needing 0.925V in UEFI. I'm using F4-3200C14D-16GTZ on C7H, the kit I used the most on C6H.


Thanks it wasnt easy tho 32GB 16gb x stick dual ranked too., well i was fighting with this kit for awhile and he was gsat stable on all those settings even 3600.
But as soon i fired up HCI thats when the problems begins. I always turn my page file on any type of stress test to begin with i dont want no intervention on my tests.

if hci give me problems i expect p95 (crashing or mostly whea errors will follow thru) occt failing no mercy. So i cant rely on gsat no more. HCI is the test to go for me. If hci is golden in my tests i have the ram out of the equation on the other tests. P95 will crash or give you whea errors.

I thought in the beginning 3466 was impossible even 1mus said this with LL (3333 was the cap for me stable), i tried my 2 cpus 1800x and the 2700x bpth mobos both failed HCI till i encountered this settings i been using right now my kit seems to like. funny thing is i can leave everything on auto and just adjust the primary timings and i guaranteed you IT WILL FAIL hci but with this custom timings no problems

So what is causing this errors IDK but now i think 3533 and 3600 are possible with some play. The problems is which setting is the culprit or what settings lol


----------



## zGunBLADEz

this is what i have so far like the picture says 

"at this point i think i am aiming for crumbs"


----------



## zGunBLADEz

Working on 14/13/13/14/32/44/1T trfc 260 and tfaw 20 shes eating hci like a good baby


----------



## Nighthog

Just a update on progress on my part. 3600Mhz CL14  

Needs 1.500V. 
With all the same but CL16 I only need 1.340V in comparison.


----------



## gupsterg

@zGunBLADEz

I take my hat off to you! :thumb: . Damn nice results for sure :thumb: .

I had an ~2 day fight on 3466MHz The Stilt preset using a R7 2700X and F4-3200C14D-16GTZ. In a way worth it, as allowed me to gain experience and tune setup before moving on.

I found upto 3400MHz I needed to adjust only SOC/VDIMM. There were 2 settings that created large gains in stability for me on 3466MHz.

3466MHz using HCI passed ~40min, failed Y-Cruncher in <30min. Setting VTTDDR to 0.687V made Y-Cruncher last for ~2.75hrs before fail. Then I used P95, as needed something that made profile fail quick to tune it. Even then it took a lot of attempts to discover ProcODT needed to be set to 48 Ohms. This surprised me, as the RAM I used, has been used with 5 differing Ryzen gen 1 and 1x TR, never did I use that ProcODT value. So as advised by several experienced members in C6H thread at launch, ProcODT definitely needs tuning based on combined HW in use. I also found with CPU stock I needed SOC: 0.956V but when combined with ACB OC of 4.075GHz SOC needed bump to 0.968V.

Anyhow here is some screenies.

ASUS ROG C7H UEFI 0601
R7 2700X UA 1805SUS (PState 0 4.075GHz VID: 1.287 SOC: 0.968V) 
F4-3200C14D-16GTZ (3466MHz C15 1T VDIMM: 1.37V VTT: 0.687V)



Spoiler


----------



## tryout1

zGunBLADEz said:


> Thanks it wasnt easy tho 32GB 16gb x stick dual ranked too., well i was fighting with this kit for awhile and he was gsat stable on all those settings even 3600.
> But as soon i fired up HCI thats when the problems begins. I always turn my page file on any type of stress test to begin with i dont want no intervention on my tests.
> 
> if hci give me problems i expect p95 (crashing or mostly whea errors will follow thru) occt failing no mercy. So i cant rely on gsat no more. HCI is the test to go for me. If hci is golden in my tests i have the ram out of the equation on the other tests. P95 will crash or give you whea errors.
> 
> I thought in the beginning 3466 was impossible even 1mus said this with LL (3333 was the cap for me stable), i tried my 2 cpus 1800x and the 2700x bpth mobos both failed HCI till i encountered this settings i been using right now my kit seems to like. funny thing is i can leave everything on auto and just adjust the primary timings and i guaranteed you IT WILL FAIL hci but with this custom timings no problems
> 
> So what is causing this errors IDK but now i think 3533 and 3600 are possible with some play. The problems is which setting is the culprit or what settings lol


Sry to just burst in and yell stuff around and btw hi @all, but did you check your DIMM Temperature while stressing with GSAT and HCI? Have a new Ryzen system too since last week with F4-3200C14D-32GTZR as a 2x16GB Kit and tried to oc them too slightly from 3200 to 3333 with optimized timings, funny was that with the same test as you did just only 1hr of GSAT everything was fine and stable but e.g. playing WoW or Destiny 2 gave me random crashes and read errors and i checked again GSAT alone 1hr no problem then i added Heaven in the background and as soon my Stick reached about 50-51 °C errors appeared everywhere, right now i was sitting at about 1.39v for the VDIMMS and about 1.05 SOC but can't test further now my power supply magic smoked yesterday while playing but that's different story.

And great job so far, keep it up :thumb:


----------



## matthew87

gupsterg said:


> For me Pinnacle Ridge AGESA with use on gen 1 been sweet, bare in mind at this time I only had 1 CPU to try. It nailed 4.0GHz/3400MHz C15 1T GDM: Off very easily IMO. I was keen to try tightening timings but also had PR+C7H beckoning to be used. I determined an OC based on 2 sticks of 8GB and to my surprise it even nailed it with 4 with 2 tweaks. Perhaps a good CPU, dunno.
> 
> Now on PR+C7H 3400MHz C15 was again very easy to attain. So IMO my new sweet spot to try on either gen 1 or 2 is that. Then move to tightening timings.
> 
> In both cases of HW SOC/VDIMM was nice and low, so really sound for 24/7 usage IMO.
> 
> I get what your saying about how you've tested 3466MHz and issue of erratic stability in OS based on differing POST. OS and POST stability are 2 different things IMO. Especially now as AGESA has moved forward so much. There must so much that goes on at POST regarding training that we don't know or have access to control.
> 
> You are better off resolving issue for now by dropping MHz, getting on using the PC and enjoying it. Perhaps a later UEFI will gain you what you desire  . UEFI's besides CPU microcode updates can contain IMC FW updates  .


Agreed.

It's just so damn annoying seeing the PC intermittently being capable of 3466mhz C15 with GDM: Off. Cold boot and POST perfect, HCI, Prime95 and GSAT stable, AIDA 64 results show great bandwidth and latency improvements. Next reboot the memory has become completely unstable with errors galore. I'd be able to accept this if i could at least conclude why it's unstable, is it board, BIOS, CPU IMC or RAM? But i can't even figure out where the failure point is. Giving me half hope/success is just doing my head in, i'd much prefer straight out failure then this current situation of my OC being stable until next shutdown or cold boot. 

Then i see others having a far easier time. I tried 3400mhz memory and that generated a single error after 400% of HCI Memtest. Seemed to be a little happier and maybe a few voltage and timing tweaks will get me there. But even then, i still couldn't get it stable with the same timing and voltage settings that were good enough to pass 1500% HCI and GSAT at 3466mhz. I just can't get this working regardless. It's like anything about default 3200mhz memory speeds wont work. 

It's become a personal challenge for me to get this working.

But you're right, at some point i've got to cut my losses and just try lower speeds/looser timings. I can't complain too bad given i've been running 3200mhz C14 stable since 9920 or earlier BIOS releases. I know a substantial number of C6H and Ryzen owners in the initial 3-6 months of the platforms release would have been happy just having 3200mhz yet alone being able to get semi stable at 3466 and even 3600mhz.


----------



## gupsterg

I was an owner of C6H which had issues running 3200MHz in initial months  . I was stuck at 2933MHz with one CPU, even using BCLK I didn't gain 3200MHz and the F4-3200C14D-16GTZ was on the QVL as being certified for 3200MHz  . Another CPU would run 3200MHz, had real erratic cold/warm post issues. Did my head in also , I used sleep/resume to not have this occur. I used the rig for few months like that. The CPU could do ~3520MHz on RAM, but I had post issues even at 3200MHz  . Then it was UEFI 9930 that sorted that, that. Up till then I'd had 3x R7 1700, I saw a deal on a R7 1800X and got that.

It was similar in OC headroom on CORE/RAM as others, but didn't have memory holes. As it had segfault issue, I had it swapped under that. What got sent back to me, turned out to be the only gen 1 CPU that touched 4.0GHz with high stability. Again had no memory holes and has been nice for RAM OC/POST stability. Still debating if I dispose of it.

Most picky I have had is Threadripper. 3200MHz was non issue, it took a few months worth of UEFI rolling forward to gain 3333MHz, 3466MHz was done also but just seemed higher side of SOC/VDIMM (IMO). Recent UEFI seems to have allowed me to trim down SOC/VDIMM for 3466MHz. Working on it currently by throwing all tweaks I can to gain as low a SOC/VDIMM for RAM setup I can.

Pinnacle Ridge has been sweet for sure. I'm hoping I can snag 3533MHz, that would be my best attained so far if gained.


----------



## Pablogamer

Someone here with experience with Ryzen 2 and the Prime X370 Pro and memory ram above 3200MHz?


----------



## hsn

Finally i can get stable on my ram.
ram 1.44v
soc 1.1475v


----------



## tekjunkie28

hsn said:


> Finally i can get stable on my ram.
> ram 1.44v
> soc 1.1475v


Is that SOC voltage safe?

Sent from my SM-N950U using Tapatalk


----------



## hsn

tekjunkie28 said:


> Is that SOC voltage safe?
> 
> Sent from my SM-N950U using Tapatalk


i think safe,because on my mobo when setting ram on high speed it's automatically read 1.25v soc.


----------



## bouchnick

I have a really weird issue trying to overclock my ram. I have 3200cl14 Samsung b-die Team Dark pro ram (Single rank 2x8gb) both in the 2/4 slots of my Asus Prime x470-Pro motherboard. Paired with a 2700x.

I can easily get the extreme timings at 3200mhz cl14 stable with a 10 hours memory test, but as soon as I raise the frequency to a mere 3246mhz I'll get an error within 30 minutes to an hour. Even with timings looser than the safe presets. My DRAM is at 1.4v and SOC at 1.075 (the most stable settings I got so far).

Any idea what the hell is going on?


----------



## Dopamin3

tekjunkie28 said:


> Is that SOC voltage safe?
> 
> Sent from my SM-N950U using Tapatalk


Yea 1.2v is safe for 24/7, any higher is bad.


----------



## OmBen

hello, im new to overclocking.

i need your suggestion to get stability on overclocking 

My Ram : f4-3866c18d-gtzr
ryzen 2700x
ASUS ROG Strix -F x470

Soc : 1.13125
V : 1.45

Its my first time overclocking and im confused what i need to change, i think im close


----------



## abso

Is there a way of finding out if my G.Skill RipJaws V F4-3200C15D-16GVR is using Samsung B-Dies without taking it out of the Box? I also could not find any info if this is single or dualrank ram.


----------



## OmBen

Somehow managed to get 3533Mhz C14 with HCI 400%

V : 1.495
Soc : 1.15

Is it still considered safe for 24/7 ?


----------



## datspike

OmBen said:


> Somehow managed to get 3533Mhz C14 with HCI 400%
> V : 1.495


I'm running 3600C13\3533C14\3533C13 for 6 months at 1.5v, no problems at all. XMP's max is 1.5v, anything over is not known if safe. I believe that there's a bit more safety room over 1.5 volts


----------



## zGunBLADEz

gupsterg said:


> @zGunBLADEz
> 
> I take my hat off to you! :thumb: . Damn nice results for sure :thumb: .
> 
> I had an ~2 day fight on 3466MHz The Stilt preset using a R7 2700X and F4-3200C14D-16GTZ. In a way worth it, as allowed me to gain experience and tune setup before moving on.
> 
> I found upto 3400MHz I needed to adjust only SOC/VDIMM. There were 2 settings that created large gains in stability for me on 3466MHz.
> 
> 3466MHz using HCI passed ~40min, failed Y-Cruncher in <30min. Setting VTTDDR to 0.687V made Y-Cruncher last for ~2.75hrs before fail. Then I used P95, as needed something that made profile fail quick to tune it. Even then it took a lot of attempts to discover ProcODT needed to be set to 48 Ohms. This surprised me, as the RAM I used, has been used with 5 differing Ryzen gen 1 and 1x TR, never did I use that ProcODT value. So as advised by several experienced members in C6H thread at launch, ProcODT definitely needs tuning based on combined HW in use. I also found with CPU stock I needed SOC: 0.956V but when combined with ACB OC of 4.075GHz SOC needed bump to 0.968V.
> 
> Anyhow here is some screenies.
> 
> ASUS ROG C7H UEFI 0601
> R7 2700X UA 1805SUS (PState 0 4.075GHz VID: 1.287 SOC: 0.968V)
> F4-3200C14D-16GTZ (3466MHz C15 1T VDIMM: 1.37V VTT: 0.687V)
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 186121
> 
> 
> View attachment 186129
> 
> 
> View attachment 186137
> 
> 
> View attachment 186145
> 
> 
> View attachment 186153


Idk man, i feel you.. i think every reboot the system with ryzen have a mind on his own. To me it needs HCI stable, As if it dont pass HCI im not comfortable with it. GSAT proves stable but the system with fail stronger tests including whea errors. Same on intel. HCI stable no whea errors aka borderline "semi" stable i will call it.



tryout1 said:


> Sry to just burst in and yell stuff around and btw hi @all, but did you check your DIMM Temperature while stressing with GSAT and HCI? Have a new Ryzen system too since last week with F4-3200C14D-32GTZR as a 2x16GB Kit and tried to oc them too slightly from 3200 to 3333 with optimized timings, funny was that with the same test as you did just only 1hr of GSAT everything was fine and stable but e.g. playing WoW or Destiny 2 gave me random crashes and read errors and i checked again GSAT alone 1hr no problem then i added Heaven in the background and as soon my Stick reached about 50-51 °C errors appeared everywhere, right now i was sitting at about 1.39v for the VDIMMS and about 1.05 SOC but can't test further now my power supply magic smoked yesterday while playing but that's different story.
> 
> And great job so far, keep it up :thumb:


thanks.
ram temps around 40s-45s my soc is ((1.00 LLC5 which is even)) i notice i get no stability problems on this once i find one that dont freeze the pc.

But at this point i think im leaving it a 3466 and the timings i have and calling it a day. I dont see no point trying to squeeze that bit extra IN R/W/C


----------



## BLUuuE

OmBen said:


> Somehow managed to get 3533Mhz C14 with HCI 400%
> 
> V : 1.495
> Soc : 1.15
> 
> Is it still considered safe for 24/7 ?


You should be opening 16 instances of HCI memtest, so that it can pass over your RAM faster.


----------



## Adrovek

I've contacted Gigabyte support, but they saying they haven't detected any issues while testing exactly same setup and sent me the pictures of them running it at 3200Mhz etc. 

If I set XMP Profile 1, I get B2 error and my PC doesn't boot at all, can't get to bios or anything. So I have reset CMOS to be able to boot again. I've tried various stuff, but best result for me is if I select XMP profile 1, but then I reduce multiplier a bit, that way max. I was able to get is 3066Mhz that i'm running it at atm. Could anyone help me get this ram to at least 3200Mhz?

CPU-Z + Typhoon screenshots:
- https://imgur.com/a/5WY4etv

RAM: 
- Corsair CMK32GX4M2B3200C16 v4.31

Thanks!


----------



## OmBen

datspike said:


> I'm running 3600C13\3533C14\3533C13 for 6 months at 1.5v, no problems at all. XMP's max is 1.5v, anything over is not known if safe. I believe that there's a bit more safety room over 1.5 volts


oh okay thanks man ! 



BLUuuE said:


> You should be opening 16 instances of HCI memtest, so that it can pass over your RAM faster.


Im using HCI memtest pro, and automatically open 5 instances when i press start, automatically using 96% ram usage. do i still need to open 16 ?


----------



## kawzir

Hi guys, I'm new to ram overclocking as I just started to explore it after I build my ryzen PC weeks ago. 

One question: assuming my 3200CL14 16gb bdie ram kit is cappable of running 3466CL14, is more VDIMM applied always improves the stability of ram overclocking? I mean within the safe range, like <1.5V. If it's true, is it good to start OC by setting the VDIMM to 1.5v and test its limit? As it can take away VDIMM as a variable to take care of.


----------



## BLUuuE

OmBen said:


> Im using HCI memtest pro, and automatically open 5 instances when i press start, automatically using 96% ram usage. do i still need to open 16 ?


You don't have to, but you'd be wasting your time if you didn't. Your 2700X has 16 threads. May as well use them all.


----------



## Shaav

> more VDIMM applied always improves the stability of ram overclocking? I mean within the safe range, like <1.5V.


No!

My sweetspot is at around ~1,45V


----------



## qwerty0304

*CMK16GX4M2B3200C16*

anyone knows the stable timings for CMK16GX4M2B3200C16. this is samsung die. ryzen 5 2600 asrock ab350m pro4
xmp settings doens't boot/bsod.

Thanks


----------



## Adrovek

qwerty0304 said:


> anyone knows the stable timings for CMK16GX4M2B3200C16. this is samsung die. ryzen 5 2600 asrock ab350m pro4
> xmp settings doens't boot/bsod.
> 
> Thanks


I've posted few posts above with nearly the same issue, so far no solutions :S

EDIT: Actually I've been experiementing with voltages and stuff, I managed to get it working and perhaps you can tooo. Not going to waste time with boring ***** so straight to the point... I've set "XMP profile 1" in bios and then changed DRAM voltage to 1.40, anything bellow that didn't work for me.


----------



## Hequaqua

Hi all.....

I'm a bit of a noob when it comes to OC'ing ram. I read through this thread a while back...and the search function isn't the greatest since the move.

I ran the HCI/Google Stress test at 3400mhz....passed both. Thought I would try 3466....the Google test says Thread 7 found 1 error, and Thread 10 found 1 error.

Here is a screen shot of one of the errors....I can't make head or tails out of it....thought I would post here and perhaps get some guidance from more experienced OC'ers.

View attachment 195065


I'm running the 2600x(stock clocks), fixed core voltage at 1.325v and the SoC is 1.150v. I'm using the GSkill Flare X Series F4-3200C14D-16GFX. I set the timings manually using the Ryzen DRAM Calculator. I believe I'm on the "Safe" settings profile that it generated. I'm on the Asus Strix X470 Gaming board.

Any info would be appreciated.

EDIT: I believe I have the DRAM at 1.45v

EDIT II: I was on the "Fast" profile, testing "Safe" now.


----------



## zGunBLADEz

if you find errors in gsat dont even try hci


----------



## Hequaqua

zGunBLADEz said:


> if you find errors in gsat dont even try hci


OK.

Passed with safe timings on the gsat test. :thumb:

I thought I was on safe settings for 3466...must have been 3400. I live in a state of confusion...so hard telling...lol

Going to try hci now.


----------



## Mr Splash

Hequaqua said:


> Hi all.....
> 
> I'm a bit of a noob when it comes to OC'ing ram. I read through this thread a while back...and the search function isn't the greatest since the move.
> 
> I ran the HCI/Google Stress test at 3400mhz....passed both. Thought I would try 3466....the Google test says Thread 7 found 1 error, and Thread 10 found 1 error.
> 
> Here is a screen shot of one of the errors....I can't make head or tails out of it....thought I would post here and perhaps get some guidance from more experienced OC'ers.
> 
> View attachment 195065
> 
> 
> I'm running the 2600x(stock clocks), fixed core voltage at 1.325v and the SoC is 1.150v. I'm using the GSkill Flare X Series F4-3200C14D-16GFX. I set the timings manually using the Ryzen DRAM Calculator. I believe I'm on the "Safe" settings profile that it generated. I'm on the Asus Strix X470 Gaming board.
> 
> Any info would be appreciated.
> 
> EDIT: I believe I have the DRAM at 1.45v
> 
> EDIT II: I was on the "Fast" profile, testing "Safe" now.


Forget I thought you were running at 3200 I'm going blind, lol. I deleted my comments.


----------



## Hequaqua

Mr Splash said:


> Forget I thought you were running at 3200 I'm going blind, lol. I deleted my comments.


I don't think I ever got to see them....so no harm, no foul...lol

I can pass at 3466 with the safe settings from Ryzen calculator, but not the fast....I did mess with some voltages and thought I had it, but nope....

At the moment, I'm at 3400mhz with a core voltage of 1.337v, ram is @1.45v, and the SoC is 1.1v. I can pass 3400 with the extreme timings....so not too bad I guess. I don't get as much throughput and the latency is a bit higher than 3466, but still I'm fairly happy. 

View attachment 195409


I will try to get a couple of runs in so they can be posted on the results page tomorrow...that's if they pass.  I'll try not to make any changes in the bios.


----------



## minal

What stable frequencies and timings have currently been achieved with dual sided/rank modules on X470 and Zen+? Specifically, I'm working with F4-3200C14D-32GTZ + 2700X + C7HWIFI.

It would be nice to know roughly what to expect and use it as a starting point.


----------



## MyShadow

minal said:


> What stable frequencies and timings have currently been achieved with dual sided/rank modules on X470 and Zen+? Specifically, I'm working with F4-3200C14D-32GTZ + 2700X + C7HWIFI.
> 
> It would be nice to know roughly what to expect and use it as a starting point.


Also very interested in this - seems that not many people go down this path


----------



## spyshagg

minal said:


> What stable frequencies and timings have currently been achieved with dual sided/rank modules on X470 and Zen+? Specifically, I'm working with F4-3200C14D-32GTZ + 2700X + C7HWIFI.
> 
> It would be nice to know roughly what to expect and use it as a starting point.





MyShadow said:


> Also very interested in this - seems that not many people go down this path













I have 2x 16GB Corsair DR 2400mhz memory running @ 3066mhz with the timings above EXCEPT @ CAS 16-18-18, TRAS 36, tCWL x16, tRTP x12

Using 1.395v. Can go up to 3133mhz. Does not scale with voltage. 1.395v is the top.

Asus CH7 + 2700x


----------



## Hequaqua

Hequaqua--X470 R5 [email protected] 1.100v---BIOS 4011---HCI---400%---GSKill F4-3200C14-8GFX[2]

View attachment 195929


Hequaqua--X470 R5 [email protected] 1.100v---BIOS 4011---Stressapptest---1 Hour---GSKill F4-3200C14-8GFX[2]

View attachment 195937


----------



## minal

spyshagg said:


> I have 2x 16GB Corsair DR 2400mhz memory running @ 3066mhz with the timings above EXCEPT @ CAS 16-18-18, TRAS 36, tCWL x16, tRTP x12
> 
> Using 1.395v. Can go up to 3133mhz. Does not scale with voltage. 1.395v is the top.
> 
> Asus CH7 + 2700x


Thanks. Those who have that RAM will appreciate it. Btw, how do you decide which timings to tweak if the calculator's settings don't work?

The F4-3200C14D-32GTZ works at 3200MT/s with DOCP. Has anyone tried for more?


----------



## matthew87

@gupsterg

Finally had some success, 3333mhz with tight timings: 











14-14-14-14-44-5-8-20-320 @ 1.375v VDRAM with GDM On. 

Yet to try trimming SoC and DRAM voltages but this is absolutely rock solid. 2000% HCI Memtest, 2 hours GSAT, 4 hours Prime95 13.5GB blend and a few hours of Battlefield 1 and Divinity OS 2 without a single error, crash or bug. Passed a number of cold and warm boots too without a single POST issue or stress test failure. It's finally stable! 

I found i couldn't tighten tRC any further, below 44 i'd get errors. The above results are preliminary too, no doubt i can still tighten up some of the sub timing. But none the less, even with what i have now it's improved read and write speeds by 10%, copy an impressive 16% and latency reduction of 8% over default 3200mhz DOCP profile.


----------



## tekjunkie28

So I have a question. Is my TRIDENT Z rgb 3200mhz 16c hynix a die or my gigabyte x470 gaming 5 wifi the weak link? I cant get 3200mhz stable unless I up the dram voltage to 1.390v. Also is it still wise to keep termination voltage half of the dram voltage?

Sent from my SM-N950U using Tapatalk


----------



## spyshagg

minal said:


> Thanks. Those who have that RAM will appreciate it. Btw, how do you decide which timings to tweak if the calculator's settings don't work?
> 
> The F4-3200C14D-32GTZ works at 3200MT/s with DOCP. Has anyone tried for more?


dont change all settings at once. Start by changing a few, and when it doesn't post, its easier to find which setting caused it. Same thing for testing stability once it posts and enters windows.


----------



## The Sandman

minal said:


> how do you decide which timings to tweak if the calculator's settings don't work?
> 
> The F4-3200C14D-32GTZ works at 3200MT/s with DOCP. Has anyone tried for more?


 @tekjunkie28 second sentence may help you. My Samy B-Die take 1.42 for 3466mhz and 1.4v for 3200MHz, don't be shy  

It's not always just timings. ProcODT, RTT (could be just one of these), and Cad_Bus all, or maybe just one may need tuning/altering from calculator. Takes time but check each one. You may be surprised.

Not enough VTTDDR had me chasing my tail for hours. Dram voltage at 1.42000 with VTTDDR at .71 was failing but increase to .71940 made a huge difference in stability.
Also set VDDP and VDDP Standby voltage (same for both)


----------



## seansplayin

so 12 hours of testing with memtest64 led me to believe the memory was stable, unfortunately instantly upon starting HCI memtest I began getting errors


----------



## tekjunkie28

seansplayin said:


> so just completed 12 hours of Memtest64 with zero errors @3533 using the timings from dram calculator's 3466 "fast" preset. 14,14,14,28,44,1t.


Nice, what's your voltages look like?

Sent from my SM-N950U using Tapatalk


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## seansplayin

I'm not 100% stable right now, I run 16 instances of [email protected] 850MB/Instance. I get 1 error around the 750% point but the remaining 15 instances will carry on error free until I stop them at around 2800%.
Dram Voltage is @ 1.51v and SOC is at 1.13V
I raised the tRCDWR up to 15 which took me from 3 threads dropping out to only 1 thread dropping out.

Trying to upload pictures but keeps saying "upload failed"


----------



## tekjunkie28

seansplayin said:


> I'm not 100% stable right now, I run 16 instances of [email protected] 850MB/Instance. I get 1 error around the 750% point but the remaining 15 instances will carry on error free until I stop them at around 2800%.
> Dram Voltage is @ 1.51v and SOC is at 1.13V
> I raised the tRCDWR up to 15 which took me from 3 threads dropping out to only 1 thread dropping out.
> 
> Trying to upload pictures but keeps saying "upload failed"


Ouch. That's some high voltage for my tastes.

I did get my GSkill flare X and its stable at 3400 with 14 14 14 14 34 @ 3.8 volts but I have not tested it thoroughly. I get it up and ran ashes benchmark and went to bed. I'll test it later tonight or tomorrow.

Sent from my SM-N950U using Tapatalk


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## m3ta1head

Managed to get sub 60ns latency.


----------



## kawzir

I don't know what to expect from my ram OC anymore. Few days ago I finally settled on 3466 fast presets from the calculator, able to pass 600% HCI test with no error. Today, got one crash when playiny PUBG so I run HCI test again, it can't even pass 30% without catching errors. However, after that I still game on the unstable settings, no crash so far for 6 hours. I don't know where Im heading to.


----------



## tekjunkie28

kawzir said:


> I don't know what to expect from my ram OC anymore. Few days ago I finally settled on 3466 fast presets from the calculator, able to pass 600% HCI test with no error. Today, got one crash when playiny PUBG so I run HCI test again, it can't even pass 30% without catching errors. However, after that I still game on the unstable settings, no crash so far for 6 hours. I don't know where Im heading to.


I had similar issues with hynix chips. B die hasn't given me that issue yet but it's only been 2 days and not much tinkering yet either. 

Sent from my SM-N950U using Tapatalk


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## 1TM1

matthew87 said:


> this is absolutely rock solid. 2000% HCI Memtest,


It may or may not be. Many ran it to XXX% memtest only to find instability on next reboot.
As I wrote earlier, 200%, cold pull the plug reboot, 200%, cold reboot, 200% is a better test.


----------



## Aenra

Someone help me please 'cause i'm going nuts..

Got the deluxe version of HCI's memtest, i do it from DOS, which is better, more memory than i could ever test within Windows.
Now the deluxe version, it shows you the available memory before it starts testing.

Each and every time i changed settings and rerun it, available memory showed as 15.70Gigs. For days now. Again, barring memory timings changes, nothing else has been touched, at all, be it in BIOS or in windows.
Last 'try' also got errors, so i went to BIOS, changed a setting, rerun memtest.. and available memory showed as 14.95Gigs :S
Am like O.K., hole. I go right back to the previous settings, just to check, and re-re-run memtest.. and it shows 14.95 now too! With the very same settings it showed me 15.70 the last time, lol
So i optimise defaults, save, reboot, run memtest again, all default right? Just to check. 

14.95... 

Help me, lol
(it's not the integrated Vega, because its UMA settings haven't been changed. As stated above, absolutely nothing else's being changed)


----------



## tekjunkie28

Integrated Vega for my work PCs take 1GB no matter what....


Aenra said:


> Someone help me please 'cause i'm going nuts..
> 
> Got the deluxe version of HCI's memtest, i do it from DOS, which is better, more memory than i could ever test within Windows.
> Now the deluxe version, it shows you the available memory before it starts testing.
> 
> Each and every time i changed settings and rerun it, available memory showed as 15.70Gigs. For days now. Again, barring memory timings changes, nothing else has been touched, at all, be it in BIOS or in windows.
> Last 'try' also got errors, so i went to BIOS, changed a setting, rerun memtest.. and available memory showed as 14.95Gigs :S
> Am like O.K., hole. I go right back to the previous settings, just to check, and re-re-run memtest.. and it shows 14.95 now too! With the very same settings it showed me 15.70 the last time, lol
> So i optimise defaults, save, reboot, run memtest again, all default right? Just to check.
> 
> 14.95...
> 
> Help me, lol
> (it's not the integrated Vega, because its UMA settings haven't been changed. As stated above, absolutely nothing else's being changed)


Sent from my SM-N950U using Tapatalk


----------



## Aenra

tekjunkie28 said:


> Integrated Vega for my work PCs take 1GB no matter what....


Thanks for the swift reply tek;

Assuming this stands regardless of motherboard brand or model, then the only explanation is that.. what? Memtest was showing me the wrong available memory for days now?
Not sure which scenario is worse 

* this board is a Gigabyte AB350N Gaming WiFi (mini ITX)


----------



## matthew87

1TM1 said:


> It may or may not be. Many ran it to XXX% memtest only to find instability on next reboot.
> As I wrote earlier, 200%, cold pull the plug reboot, 200%, cold reboot, 200% is a better test.


This is what I have done and why i specifically i mentioned cold and warm reboots. 

Week in, multiple cold and warm boots, zero stability issues.


----------



## Aenra

matthew87 said:


> Week in, multiple cold and warm boots, zero stability issues.


I can see how this comes to play, given Ryzen peculiarities; but don't you run Blend afterwards anyway?
My modus is 400% memtest, then a custom blend (custom so i can add all the non-used memory). If it passes that too, then and only then am i gonna bother with cold testing. Which i do agree, is a must for Ryzens.

If you disagree, care to elaborate? Always open to advice.


----------



## tekjunkie28

Aenra said:


> Thanks for the swift reply tek;
> 
> Assuming this stands regardless of motherboard brand or model, then the only explanation is that.. what? Memtest was showing me the wrong available memory for days now?
> Not sure which scenario is worse [emoji14]
> 
> * this board is a Gigabyte AB350N Gaming WiFi (mini ITX)


Ah crappy tapatalk didn't show me a reply quickly like usual. So I built 4 PC's for work with all the same hardware. They are asrock a320m hdv mobo with a ryzen 2400G. I selected 512 1gb and 2gb but windows always reports 6.9gb available. Probably just not mature bios? I'll test more Tuesday if I get a chance and get back. 

Sent from my SM-N950U using Tapatalk


----------



## matthew87

Aenra said:


> I can see how this comes to play, given Ryzen peculiarities; but don't you run Blend afterwards anyway?
> My modus is 400% memtest, then a custom blend (custom so i can add all the non-used memory). If it passes that too, then and only then am i gonna bother with cold testing. Which i do agree, is a must for Ryzens.
> 
> If you disagree, care to elaborate? Always open to advice.


I agree, and that was pretty much the process I followed due to intermittent stability issues. Where the PC could successfully pass all manner of stress tests and benchmarks until it was cold or even warm rebooted. 

My process:

HCI Memtest - 400%
Prime95 Blend medium to large FFT with 90% free memory assigned (Run for at least 1 hour)
GSAT

Reboot warm and repeat above

Reboot after disconnecting A/C for 15 minutes or so, as best to emulate a true cold boot both in terms of power and temperatures and repeat stress tests. 

If after all this no instability occurred i'd then cold boot again and run overnight a 1500-200% HCI Memtest. 

What i learned about my Ryzen 1700X is that it loves SoC voltage, for 3333mhz with tight timings i've needed to set 1.0675v in BIOS to maintain stability. Under full load and with vdroop this equates to a SoC voltage of 1.05v according to the 1700X's sensors. I also had to use Gear Down Mode, for some unexplained reason I could only achieve intermittent stability between reboots with it off. Once on, i could tighten the timings some more which while not completely offsetting the performance hit of enabling GDM certainly reduced it.

I'm now roughly a week or so since and my 3333mhz mem overclock has been flawless in benchmarks, stress tests and real world usage. No WHEA errors, instability, POST issues or application crashes or freezes.

One day i might to back and look at 3466mhz, but this mem overclock has still yielded quite substantial improvements to Read, Write, Copy and access latency. Reading reviews of a few Samsung B die C16 3466mhz memory kits running on Intel 7 and 8th gen processors at stock XMP timings my 3333mhz overclock is exceeding them in bandwidth across the board. Which really reinforced to me the importance of memory timings and to not get too caught up in 'mhz' as really there's far more to memory performance than what speed they operate.


----------



## Aenra

tekjunkie28 said:


> Ah crappy tapatalk didn't show me a reply quickly like usual


Absolutely no worries whatsoever 
You ever get the time (or remember to) have a closer look, by all means post.
* Edit: Not sure if it's an immature BIOS, 'cause between you and me we've covered all the major brands, lol.. sounds like an AGESA thing am afraid.



matthew87 said:


> temperatures


I err, wasn't going to mention this, but you know what i do, lol?
Unplug it, take it to the bedroom, turn the AC on, all the way down to 18C, full scale on air, close the door on my way out. I know how it sounds, but with my TR, this saved me a looot of time, trust me on that. I'd leave it off for an hour and it'd still pass, next day, hang again. So i thought eff it, i'll go extreme. And it worked!


----------



## matthew87

My post wasn't 100% exhaustive as to how far i went with testing/eliminating cold boot stability issues. I'm not sure how much information is too much, i could write a short story on my experience trying to get stable memory overclocks on Ryzen and eliminate intermittent stability. 

But i agree, cold boot stability has bitten me in the backside a few times and it is important to test thoroughly. Nothing worse then stress testing and thinking you've got a stable setup and finding out you're wrong. 

Thankfully it's now winter here, so it's been getting down to around 8c overnight. I've left the PC disconnected from A/C for a good 4-24 hours while testing for cold boot stability. Believe me when i say I've tested this O/C for stability exhaustively. If you read through my posts trying to get 3466mhz stable i was pulling my hair out trying to get to the bottom of both cold and warm boot instability. It was a the point i could pass 1500+ HCI Memtest, 2-4 hours of Prime95 blend and multiple GSAT runs at 3466mhz C14 timings with GDM off. That's pretty stable by most people's measure, certainly enough that even if you're a little off it's at best going to be a few tweaks to timings or voltages here or there. 

Next reboot be it warm or cold this same previously rock solid O/C could be so unstable startup programmes would crash when Windows Desktop was loading and stress testing apps would immediately find memory errors. Changes to timings and voltages achieved nothing, stability either went backwards or remained poor but regardless could not be improved for a once 'stable' O/C. 

Nothing more frustrating than performing 24-36 hours of solid benchmarking and stress testing thinking you've got it stable, no errors, performance brilliant, everything looking awesome and then find it turns to absolute rubbish.


----------



## canni76

[email protected] 1.1v---BIOS F4g---HCI---400% .Safe preset from RyzenDramCalculator.

Link to picture from my desktop https://imgur.com/7VinLnA .


----------



## Aenra

matthew87 said:


> If you read through my posts


Going to, this mini Ryzen (2400G) is making it too hard for me, even the TR was easy in comparison.. am starting to think it's the mobo at fault, i do lack crucial 'switches', but hey.. i wanted a mini-ITX build ^^

[getting a bit better now, though still failing after the "A/C treatment"]


----------



## m3ta1head

Is this considered 100% stable? Got errors on 2 threads at 1486%, the rest went 2500%+. Just wanting to establish a rock solid baseline at 3200 before trying to stabilize higher frequencies.

edit: 2600X, Strix B350-F, G.Skill F4-3200C14D @ 14-14-13-22-36-1T, 1.39vDIMM, 1.1vSOC


----------



## tekjunkie28

m3ta1head said:


> Is this considered 100% stable? Got errors on 2 threads at 1486%, the rest went 2500%+. Just wanting to establish a rock solid baseline at 3200 before trying to stabilize higher frequencies.
> 
> edit: 2600X, Strix B350-F, G.Skill F4-3200C14D @ 14-14-13-22-36-1T, 1.39vDIMM, 1.1vSOC


Here's what I have found in 20 years of building PCs. NOTHING overclocked is stable... even stock is potentially unstable and your at the mercy of the PSU and then component quality and then software. Luckily windows is almost perfect for bug checking so if you have any errors there it will BSOD. I never did stress test my Pentium 4, q9550. I did stress test my haswell and it was such a waste to throw 700mhz at that chip. The tradeoff was worthless bc I would hit a voltage limit before i hit temp limit. The 2700x itself is just about perfect stock and the best thing is to OC memory.


I have heard that SOC beyond 1.1v could give issues even it It is safe.

Sent from my SM-N950U using Tapatalk


----------



## SavantStrike

tekjunkie28 said:


> Here's what I have found in 20 years of building PCs. NOTHING overclocked is stable... even stock is potentially unstable and your at the mercy of the PSU and then component quality and then software. Luckily windows is almost perfect for bug checking so if you have any errors there it will BSOD. I never did stress test my Pentium 4, q9550. I did stress test my haswell and it was such a waste to throw 700mhz at that chip. The tradeoff was worthless bc I would hit a voltage limit before i hit temp limit. The 2700x itself is just about perfect stock and the best thing is to OC memory.
> 
> 
> I have heard that SOC beyond 1.1v could give issues even it It is safe.
> 
> Sent from my SM-N950U using Tapatalk


I have machines that were over clocked and stability tested until they were stable and ran fine for years, some with years of uninterrupted power on time (if not running windows).

You can have an over clocked machine that's stable and doesn't throw memory errors, it just takes a little extra planning.


----------



## tekjunkie28

SavantStrike said:


> I have machines that were over clocked and stability tested until they were stable and ran fine for years, some with years of uninterrupted power on time (if not running windows).
> 
> You can have an over clocked machine that's stable and doesn't throw memory errors, it just takes a little extra planning.


Oh its possible but I never had any issues with this until Haswell year and forward. 

Sent from my SM-N950U using Tapatalk


----------



## matthew87

m3ta1head said:


> Is this considered 100% stable? Got errors on 2 threads at 1486%, the rest went 2500%+. Just wanting to establish a rock solid baseline at 3200 before trying to stabilize higher frequencies.


Any errors in HCI Memtest = unstable. 

It should be able to do infinite runs without a single error. 

I'd try increasing tRC to 38 and stress testing again. 

Based on my experience OCing 1st gen Ryzen i found if tRC was set to low i would get similar intermittent stability. It could pass hours and hours of HCI without error and then the odd random 1 or 2 would appear. Bumped it up a few notches and no more issues.


----------



## m3ta1head

matthew87 said:


> Any errors in HCI Memtest = unstable.
> 
> It should be able to do infinite runs without a single error.
> 
> I'd try increasing tRC to 38 and stress testing again.
> 
> Based on my experience OCing 1st gen Ryzen i found if tRC was set to low i would get similar intermittent stability. It could pass hours and hours of HCI without error and then the odd random 1 or 2 would appear. Bumped it up a few notches and no more issues.


Thanks! I wasn't sure as it passed numerous other stress tests, 12hr+ runs of memtest and prime95 with flying colors. Only HCI produced errors (but it seems to be the most demanding memory test overall). I will try bumping tRC and report back.


----------



## VeritronX

So what was the conclusion on the program Ram Test?

I bought that and have been using it, has been doing a good job so far.. I leave it on overnight or while at work and it usually gets to over 32000% coverage by the time I stop it 8-10hrs later. I've been really happy with the stability of my 1700 with ram set to these settings from the calculator: http://i.imgur.com/n5NGxqb.png

I've found that I don't have any cold or warm boot stability problems with this on my AX370 K7 Gigabyte board when I have all the memory options set manually, it never seems to need to multi-reboot for memory training either even when it's been off and unplugged for half the day beforehand.


----------



## mtrai

Hey just wanted to point out some info...if you are using HWinfo to monitor while testing memory and have AMD gpus in crossfire it causes a slow memory leak in HWinfo which causes me to always get errors in memory testing unless I disable crossfire first or not run any monitoring software. Not all causes the monitoring memory leak. IE HWmonitor does not leak, however Aida does leak is monitoring.


----------



## CJMitsuki

mtrai said:


> Hey just wanted to point out some info...if you are using HWinfo to monitor while testing memory and have AMD gpus in crossfire it causes a slow memory leak in HWinfo which causes me to always get errors in memory testing unless I disable crossfire first or not run any monitoring software. Not all causes the monitoring memory leak. IE HWmonitor does not leak, however Aida does leak is monitoring.



Have you updated HWiNFO to the latest version which came out in the last day or so?


----------



## mtrai

CJMitsuki said:


> Have you updated HWiNFO to the latest version which came out in the last day or so?


Yeah there is still the slow memory leak where the programs I stated continue to eat memory.


----------



## CJMitsuki

mtrai said:


> CJMitsuki said:
> 
> 
> 
> Have you updated HWiNFO to the latest version which came out in the last day or so?
> 
> 
> 
> Yeah there is still the slow memory leak where the programs I stated continue to eat memory.
Click to expand...

 @Mumak has anyone else had this problem?


----------



## Yviena

Does anyone have any tips for stabilizing 3466 extreme preset? I already found the best procODT and cadbus settings with 1.11250v SoC voltage, and it's somewhat stable as all threads chug along well into 1000% except one that always fails around the 370% mark.

Relaxing the tras and TRC/TRFC timings actually makes the ram fail much earlier at around the 100% mark.


----------



## datspike

@Yviena there is a lot of things you can do to stabilize your config. 
I.e. try checking voltage scaling, messing with trrds/l, tfaw, twtrs/l, twr, tscl and trfc. 
RRDS and RRDL + FAW seem to be happy at 4\4\16 for example on my kit. Fun thing that 4\4\16 is actually more stable than something like 6\8\24. 
Increasing tWR by 2 and\or tSCL's by 1 can help stabilize things at the expense of memory bandwidth.
tRFC generally scales with voltage in my experience.

I actually stopped tweaking any other secondary\tetrietary timings than trrds/l, tfaw, twtrs/l, twr, tscl and trfc as they dont seem to improve performance or affect stability in any way.


----------



## Mumak

CJMitsuki said:


> @Mumak has anyone else had this problem?


The only memory leak we're aware of is in AMD drivers when using Crossfire. This is in their drivers or libraries.
Is this perhaps your config?


----------



## neojack

VeritronX said:


> So what was the conclusion on the program Ram Test?


i am using the paid version ,a nd it's really good. it's the first program I use because it is the fastest to find errors

But i also use other programs overnight to confirm everything is stable :
- first : ram test overnight
- Google stress app (installed on a separate old spinning hard drive I got around, with ubuntu)
- HCI memtest
- prime 95
- good old memtest 86+ wich is good to find physical defects, but not so good to find unstability. so i use it last.


----------



## Vipeax

Anyone here running 16GB modules on a high frequency? I have a 2700X in a X470-i (mini-itx) with 2 memory slots, so I have it running on a F4-3200C14D-32GTZR kit at:










It feels like 16GB modules/more than 16GB of RAM in total has a large impact on the IMC, which seems to make going beyond 3200, at least on respectable timings, a tough one. Can anyone either confirm or deny this? The above went through 1200% of HCI MemTest and I'm happy with what I have (1.35V on the RAM/1.0V on the SOC, low voltages keep the heat to a minimum in a small case), but I'd still like to know if this is the case or not.


----------



## Anty

You can try different RTT and CAD bus settings.


----------



## minal

Vipeax said:


> Anyone here running 16GB modules on a high frequency? I have a 2700X in a X470-i (mini-itx) with 2 memory slots, so I have it running on a F4-3200C14D-32GTZR kit at:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> It feels like 16GB modules/more than 16GB of RAM in total has a large impact on the IMC, which seems to make going beyond 3200, at least on respectable timings, a tough one. Can anyone either confirm or deny this? The above went through 1200% of HCI MemTest and I'm happy with what I have (1.35V on the RAM/1.0V on the SOC, low voltages keep the heat to a minimum in a small case), but I'd still like to know if this is the case or not.


 I'm using F4-3200C14D-32GTZ and I just copied the settings for 3200 from this ROG forum post: https://rog.asus.com/forum/showthre...ules-for-Crosshair-VII-2700X/page2#post719511

It passed stress tests, but I didn't try to optimize more for now.


----------



## nuthead53

Just went from getting 3400fast stable and error free with fairly loose timings attached to trying The Stilts 3333 (https://i.imgur.com/LQZeSWE.jpg)

Got some errors in HCI at about 70% so obviously not stable, not really sure what to go after to improve the stability. I assume voltage is ok and it's just a matter of getting the right balance on timings.

Using some bdie Corsair 3600 on a 2700x


----------



## Yviena

nuthead53 said:


> Just went from getting 3400fast stable and error free with fairly loose timings attached to trying The Stilts 3333 (https://i.imgur.com/LQZeSWE.jpg)
> 
> Got some errors in HCI at about 70% so obviously not stable, not really sure what to go after to improve the stability. I assume voltage is ok and it's just a matter of getting the right balance on timings.
> 
> Using some bdie Corsair 3600 on a 2700x


Try using the ryzen dram calculator, I got my 1700 to be stable at the 3466 extreme preset with 1.46v ram voltage, the recommended settings where spot on.

I just needed to change CAD bus to alt1 and upping the SoC voltage from the recommended 1.11250 to 1.125v.

Seems i can't currently upload images of hci passing 1500% as for some reason uploading to overclock.net fails..


----------



## nuthead53

Thanks, I did. That's where I got the 3400fast from.

The primary timings aren't very tight though, even on extreme so I was experimenting with the stilts.


----------



## raucous

I have a 2700X system and recently overclocked the memory to 3466 using the Stilts memory preset. I ran MemTest86 overnight and it finished on exactly 3 hours and it was error free. I had to hard reset the PC at the end of the test as I think my fancy gaming keyboard failed to respond in the MemTest menu just as my keyboard would fail to respond and bring up the BIOS screen on my old computer.

Other than the memory overclock I have left everything else on auto. 

Do these voltages look within safe levels?

CPU Core Voltage 1.363 - Auto (varies a lot, often lower)
CPU SOC Voltage 1.136V - Auto
DRAM Voltage 1.400V
1.8 PLL Voltage 1.831 1.831V - Auto
1.05V SB Voltage 1.091V (to 1.094V) - Auto

Thanks


----------



## CJMitsuki

raucous said:


> I have a 2700X system and recently overclocked the memory to 3466 using the Stilts memory preset. I ran MemTest86 overnight and it finished on exactly 3 hours and it was error free. I had to hard reset the PC at the end of the test as I think my fancy gaming keyboard failed to respond in the MemTest menu just as my keyboard would fail to bring up the BIOS screen on my old computer.
> 
> Other than the memory overclock I have left everything else on auto.
> 
> Do these voltages look within safe levels?
> 
> CPU Core Voltage 1.363 - Auto (varies a lot, often lower)
> CPU SOC Voltage 1.136V - Auto
> DRAM Voltage 1.400V
> 1.8 PLL Voltage 1.831 1.831V - Auto
> 1.05V SB Voltage 1.091V (to 1.094V) - Auto
> 
> Thanks


The voltages look fine. They are within spec. I would run memtest overnight though. 3 hours is good for initial stability but at least 8-12 hours will give you confirmation.


----------



## raucous

CJMitsuki said:


> The voltages look fine. They are within spec. I would run memtest overnight though. 3 hours is good for initial stability but at least 8-12 hours will give you confirmation.


Thanks - I will run Memtest for 8-12 hours tonight.

Is it fine for me to leave these voltages all on auto? I.e. they will not exceed safe levels when the system is under full load?


----------



## Whatisthisfor

Achieved 3533MHZ CL14 HCI 300% stable with Ryzen 2700X, a 32 DDR4 Kit (F4-4133C17Q-32GTZR) on a Gigabyte X470 AORUS GAMING 7 WIFI, 1,44V Vcore, 1,025V SOC + BLK 102. Timings are loose and could probably be tightened here and there.


----------



## tekjunkie28

I would also like confirmation on SOC and DRAM voltages. What is 24/7 safe and also how much does SOC voltage contribute to overall temps as this will potentially affect performance of the cpu itself.


raucous said:


> Thanks - I will run Memtest for 8-12 hours tonight.
> 
> Is it fine for me to leave these voltages all on auto? I.e. they will not exceed safe levels when the system is under full load?


Sent from my SM-N950U using Tapatalk


----------



## Anty

tekjunkie28 said:


> I would also like confirmation on SOC and DRAM voltages. What is 24/7 safe


soc 1.2
dram 1.5



tekjunkie28 said:


> how much does SOC voltage contribute to overall temps


there is some increase but nothing to die for


----------



## encrypted11

Vipeax said:


> Anyone here running 16GB modules on a high frequency? I have a 2700X in a X470-i (mini-itx) with 2 memory slots, so I have it running on a F4-3200C14D-32GTZR kit at:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> It feels like 16GB modules/more than 16GB of RAM in total has a large impact on the IMC, which seems to make going beyond 3200, at least on respectable timings, a tough one. Can anyone either confirm or deny this? The above went through 1200% of HCI MemTest and I'm happy with what I have (1.35V on the RAM/1.0V on the SOC, low voltages keep the heat to a minimum in a small case), but I'd still like to know if this is the case or not.


Stressapptest testing, seems like hardly anyone is using this. No use of GearDownMode / MRC Fastboot like features.
VddSoC 1.0125V, also stressapptest 2H stable at 3200MHz 0.99V. ProcODT 60Ohms.

It hits a brick wall on the 3466 strap regardless of SoC voltage or 30-30-30-30 / 40-40-40-40 cad bus, it'll post and boot into mint 18.3, results in a kernel panic in under 10 seconds. At Cad Bus auto it'll fail posting.

The kit I'm using are capable of C16 4000MHz 1T or C18 4400MHz 2T stressapptest stable on Intel, so its the board or CPU I guess.


Spoiler


----------



## tryout1

well it looks like i'm onto something, fought the last 4 days with tweaking several values up and down to get 3333 stable with my Dual Ranks *Gskill F4-3200C14D-32GTZR* but it seems like that temps where my culprit all along cause i hit about 48 °C upwards everytime, now i just was so pissed that i said f**k it i go back to 3200 Fast but before i put a fan over the DRAMs to get some circulation going (seems like the H500P Mesh is to less with 2 front 200mm + 2 120mm on top + 1 140 mm on back, well as you can see i just started HWinfo64 before i stopped my first indication of "stable" settings but at least it ran quite a bit and think i will test other apps too. So i would really say temps are key?! If yes is there a way beside loosen timings/clocks to raise the "issue limit" from ~48 °C upwards to let's say 60-70 °C?

So well yeah *DRAM Voltage* is set to *1.37v* in Bios, *SOC 1.0375v* LLC3, Vcore Offset -0,075v LLC3 (PE2), CLO_VDDP 700mV

Here my .log if anyone is interested i deleted it some days ago and started to write down things in there.



Code:


[2018-06-01T20:05:15.9090056+02:00] License activated successfully.
[2018-06-01T20:05:31.1671953+02:00] Started testing 24381 MB with 16 thread(s).
[2018-06-01T20:22:59.2656820+02:00] ERROR DETECTED!
[2018-06-01T20:23:02.5292594+02:00] Stopped testing after 0:00:17:31 with 534 % coverage and 1 error(s).
[2018-06-01T20:29:57.1715293+02:00] RAM Test is up-to-date.
[2018-06-01T20:30:06.9025298+02:00] Started testing 27102 MB with 16 thread(s).
[2018-06-01T20:47:15.7697176+02:00] ERROR DETECTED!
[2018-06-01T20:47:27.5368687+02:00] Stopped testing after 0:00:17:20 with 478 % coverage and 1 error(s).
[2018-06-01T20:57:02.6721590+02:00] RAM Test is up-to-date.
[2018-06-01T20:57:04.7806613+02:00] Started testing 27114 MB with 16 thread(s).
[2018-06-01T21:32:32.2997958+02:00] Stopped testing after 0:00:35:27 with 980 % coverage and 0 error(s).
[2018-06-01T21:44:09.2263741+02:00] RAM Test is up-to-date.
[2018-06-01T21:44:10.3886294+02:00] Started testing 27193 MB with 16 thread(s).
[2018-06-01T21:50:49.3115983+02:00] ERROR DETECTED!
[2018-06-01T21:51:06.5787128+02:00] ERROR DETECTED!
[2018-06-01T21:51:43.6864636+02:00] Stopped testing after 0:00:07:33 with 210 % coverage and 2 error(s).
[2018-06-01T22:00:18.2573700+02:00] RAM Test is up-to-date.
[2018-06-01T22:00:19.6754425+02:00] Started testing 27214 MB with 16 thread(s).
[2018-06-01T22:10:53.9095677+02:00] ERROR DETECTED!
[2018-06-01T22:21:40.0818733+02:00] Stopped testing after 0:00:21:20 with 581 % coverage and 1 error(s).
[2018-06-01T22:27:02.8876377+02:00] RAM Test is up-to-date.
[2018-06-01T22:27:04.5790612+02:00] Started testing 27271 MB with 16 thread(s).
[2018-06-01T22:38:35.6033115+02:00] ERROR DETECTED!
[2018-06-01T22:41:42.0711077+02:00] ERROR DETECTED!
[2018-06-01T22:47:41.0251654+02:00] Stopped testing after 0:00:20:36 with 571 % coverage and 2 error(s).
[2018-06-01T22:49:49.3494973+02:00] RAM Test is up-to-date.
[2018-06-01T22:49:54.7136801+02:00] Started testing 27095 MB with 16 thread(s).
[2018-06-01T22:56:57.2851511+02:00] ERROR DETECTED!
[2018-06-01T22:57:57.5422327+02:00] Stopped testing after 0:00:08:02 with 220 % coverage and 1 error(s).
[2018-06-01T22:59:35.7679333+02:00] RAM Test is up-to-date.
[2018-06-01T22:59:39.1546855+02:00] Started testing 27097 MB with 16 thread(s).
[2018-06-01T23:06:11.9863478+02:00] ERROR DETECTED!
[2018-06-01T23:10:42.9390808+02:00] ERROR DETECTED!
[2018-06-01T23:14:39.6876633+02:00] ERROR DETECTED!
[2018-06-01T23:14:50.2865702+02:00] ERROR DETECTED!
[2018-06-01T23:15:06.6315085+02:00] Stopped testing after 0:00:15:27 with 426 % coverage and 4 error(s).
[2018-06-01T23:16:53.4686448+02:00] RAM Test is up-to-date.
[2018-06-01T23:16:55.8209177+02:00] Started testing 27106 MB with 16 thread(s).
[2018-06-01T23:58:54.1127173+02:00] Stopped testing after 0:00:41:58 with 1163 % coverage and 0 error(s).
[2018-06-04T17:46:26.5611237+02:00] RAM Test is up-to-date.
[2018-06-04T17:46:28.2018465+02:00] Started testing 27589 MB with 16 thread(s).
[2018-06-04T18:06:14.7608733+02:00] ERROR DETECTED!
[2018-06-04T18:06:17.6462649+02:00] Stopped testing after 0:00:19:49 with 538 % coverage and 1 error(s).
[2018-06-04T18:10:50.7172504+02:00] RAM Test is up-to-date.
[2018-06-04T18:10:51.2016521+02:00] Started testing 27450 MB with 16 thread(s).
[2018-06-04T18:30:14.1462598+02:00] ERROR DETECTED!
[2018-06-04T18:30:17.5088051+02:00] Stopped testing after 0:00:19:26 with 530 % coverage and 1 error(s).
[2018-06-04T18:34:22.2660310+02:00] RAM Test is up-to-date.
[2018-06-04T18:34:23.0163699+02:00] Started testing 27438 MB with 16 thread(s).
[2018-06-04T18:54:02.5122653+02:00] ERROR DETECTED!
[2018-06-04T18:54:05.6668153+02:00] Stopped testing after 0:00:19:42 with 538 % coverage and 1 error(s).
[2018-06-04T18:57:12.4362655+02:00] RAM Test is up-to-date.
[2018-06-04T18:57:12.9831972+02:00] Started testing 27410 MB with 16 thread(s).
[2018-06-04T19:15:01.9518171+02:00] ERROR DETECTED!
[2018-06-04T19:15:05.6368703+02:00] Stopped testing after 0:00:17:52 with 489 % coverage and 1 error(s).
[2018-06-04T19:22:21.6114476+02:00] Started testing 27459 MB with 16 thread(s).
[2018-06-04T19:22:22.0020868+02:00] RAM Test is up-to-date.
[2018-06-04T19:41:43.7393447+02:00] ERROR DETECTED!
[2018-06-04T19:41:46.7426282+02:00] Stopped testing after 0:00:19:25 with 529 % coverage and 1 error(s).
[2018-06-04T19:45:03.8265061+02:00] RAM Test is up-to-date.
[2018-06-04T19:45:04.3107578+02:00] Started testing 27463 MB with 16 thread(s).
[2018-06-04T19:48:43.9589290+02:00] ERROR DETECTED!
[2018-06-04T19:48:47.3706086+02:00] Stopped testing after 0:00:03:43 with 98 % coverage and 1 error(s).
[2018-06-04T19:54:50.8726976+02:00] RAM Test is up-to-date.
[2018-06-04T19:54:53.4665527+02:00] Started testing 27407 MB with 16 thread(s).
[2018-06-04T20:28:11.6446023+02:00] Stopped testing after 0:00:33:18 with 911 % coverage and 0 error(s).
[2018-06-04T20:31:01.2193895+02:00] Started testing 27407 MB with 16 thread(s).
[2018-06-04T20:31:06.7508143+02:00] RAM Test is up-to-date.
[2018-06-04T20:48:45.4448901+02:00] ERROR DETECTED!
[2018-06-04T20:48:48.8574850+02:00] Stopped testing after 0:00:17:47 with 485 % coverage and 1 error(s).
[2018-06-04T20:51:22.3479732+02:00] RAM Test is up-to-date.
[2018-06-04T20:51:23.4819065+02:00] Started testing 27401 MB with 16 thread(s).
[2018-06-04T21:10:24.9532865+02:00] ERROR DETECTED!
[2018-06-04T21:10:28.7056353+02:00] Stopped testing after 0:00:19:05 with 521 % coverage and 1 error(s).
[2018-06-04T21:23:01.9343846+02:00] RAM Test is up-to-date.
[2018-06-04T21:23:02.2312576+02:00] Started testing 27568 MB with 16 thread(s).
[2018-06-04T22:24:16.3533030+02:00] Stopped testing after 0:01:01:14 with 1546 % coverage and 0 error(s).	SOC 1.05v RAM 1.41v DDR3200-Fast
[2018-06-05T19:26:58.0586069+02:00] RAM Test is up-to-date.
[2018-06-05T19:26:58.3242285+02:00] Started testing 27568 MB with 16 thread(s).
[2018-06-05T19:42:38.4259917+02:00] ERROR DETECTED!
[2018-06-05T19:42:41.6926011+02:00] Stopped testing after 0:00:15:43 with 424 % coverage and 1 error(s).
[2018-06-05T19:54:53.1831668+02:00] RAM Test is up-to-date.
[2018-06-05T19:54:53.9867324+02:00] Started testing 26464 MB with 16 thread(s).
[2018-06-05T20:07:04.5464253+02:00] ERROR DETECTED!
[2018-06-05T20:07:07.6898455+02:00] Stopped testing after 0:00:12:13 with 342 % coverage and 1 error(s).
[2018-06-05T20:16:21.2502630+02:00] RAM Test is up-to-date.
[2018-06-05T20:16:32.7014561+02:00] Started testing 26792 MB with 16 thread(s).
[2018-06-05T20:37:12.3889637+02:00] ERROR DETECTED!
[2018-06-05T20:37:15.2909813+02:00] Stopped testing after 0:00:20:42 with 582 % coverage and 1 error(s).
[2018-06-05T20:39:40.0412576+02:00] RAM Test is up-to-date.
[2018-06-05T20:39:41.1379908+02:00] Started testing 27486 MB with 16 thread(s).
[2018-06-05T20:43:31.3327733+02:00] ERROR DETECTED!
[2018-06-05T20:43:35.5281822+02:00] Stopped testing after 0:00:03:54 with 104 % coverage and 1 error(s).
[2018-06-05T20:46:09.2764684+02:00] RAM Test is up-to-date.
[2018-06-05T20:46:09.3858442+02:00] Started testing 27473 MB with 16 thread(s).
[2018-06-05T20:54:37.6523299+02:00] ERROR DETECTED!
[2018-06-05T20:54:41.2469410+02:00] Stopped testing after 0:00:08:31 with 231 % coverage and 1 error(s).
[2018-06-05T20:58:21.7562001+02:00] RAM Test is up-to-date.
[2018-06-05T20:58:23.6259307+02:00] Started testing 27487 MB with 16 thread(s).
[2018-06-05T21:04:39.9039601+02:00] ERROR DETECTED!
[2018-06-05T21:04:43.7771064+02:00] Stopped testing after 0:00:06:20 with 171 % coverage and 1 error(s).
[2018-06-05T21:07:28.1535751+02:00] RAM Test is up-to-date.
[2018-06-05T21:07:28.3879711+02:00] Started testing 27489 MB with 16 thread(s).
[2018-06-05T21:36:58.0539267+02:00] ERROR DETECTED!
[2018-06-05T21:37:01.6234894+02:00] Stopped testing after 0:00:29:33 with 805 % coverage and 1 error(s).	SOC 1.075v RAM 1.4v CLLO_VDDP 700mV "Safe Timings"
[2018-06-05T21:45:52.3254744+02:00] RAM Test is up-to-date.
[2018-06-05T21:45:52.7473762+02:00] Started testing 27659 MB with 16 thread(s).
[2018-06-05T22:11:48.5364327+02:00] ERROR DETECTED!
[2018-06-05T22:11:52.0520651+02:00] Stopped testing after 0:00:25:59 with 691 % coverage and 1 error(s).	SOC 1.081v RAM 1.4v CLLO_VDDP 700mV "Safe Timings"
[2018-06-05T22:14:33.8320126+02:00] RAM Test is up-to-date.
[2018-06-05T22:14:34.3007838+02:00] Started testing 27457 MB with 16 thread(s).
[2018-06-05T22:36:32.2183286+02:00] ERROR DETECTED!
[2018-06-05T22:36:35.7059494+02:00] Stopped testing after 0:00:22:01 with 601 % coverage and 1 error(s).	SOC 1.087v RAM 1.4v CLLO_VDDP 700mV "Safe Timings"
[2018-06-05T22:39:25.4501907+02:00] RAM Test is up-to-date.
[2018-06-05T22:39:25.7277224+02:00] Started testing 26517 MB with 16 thread(s).
[2018-06-05T22:50:05.0613420+02:00] ERROR DETECTED!
[2018-06-05T22:50:08.7469946+02:00] Stopped testing after 0:00:10:43 with 298 % coverage and 1 error(s).	SOC 1.0v RAM 1.4v CLLO_VDDP 700mV "Safe Timings"
[2018-06-05T22:54:45.4249309+02:00] RAM Test is up-to-date.
[2018-06-05T22:54:45.8311941+02:00] Started testing 27626 MB with 16 thread(s).
[2018-06-05T23:04:44.5832493+02:00] ERROR DETECTED!
[2018-06-05T23:04:47.8268285+02:00] Stopped testing after 0:00:10:01 with 268 % coverage and 1 error(s).	SOC 1.1v RAM 1.4v CLLO_VDDP 700mV "Safe Timings"
[2018-06-06T17:24:43.3703032+02:00] RAM Test is up-to-date.
[2018-06-06T17:24:44.9016448+02:00] Started testing 27447 MB with 16 thread(s).
[2018-06-06T17:37:42.1331925+02:00] ERROR DETECTED!
[2018-06-06T17:37:44.8403499+02:00] Stopped testing after 0:00:12:59 with 355 % coverage and 1 error(s).	SOC 1.075v RAM 1.4v Ohm 20-20-20-20 CLLO_VDDP 700mV "Safe Timings"
[2018-06-06T17:40:39.9816714+02:00] RAM Test is up-to-date.
[2018-06-06T17:40:40.3410864+02:00] Started testing 27533 MB with 16 thread(s).
[2018-06-06T17:50:45.1670318+02:00] ERROR DETECTED!
[2018-06-06T17:50:48.5467382+02:00] Stopped testing after 0:00:10:08 with 275 % coverage and 1 error(s).	SOC 1.075v RAM 1.4v Ohm 30-30-30-30 System ultralaggy after stresstest start "Safe Timings"
[2018-06-06T17:58:31.0700691+02:00] RAM Test is up-to-date.
[2018-06-06T17:58:31.7732261+02:00] Started testing 27463 MB with 16 thread(s).
[2018-06-06T18:59:07.7739702+02:00] Stopped testing after 0:01:00:35 with 1667 % coverage and 0 error(s).	SOC 1.0375v RAM 1.35v Ohm 24-24-24-24 CLLO_VDDP 700mV "Safe Timings" + FAN
[2018-06-06T19:50:10.5341765+02:00] RAM Test is up-to-date.
[2018-06-06T19:50:14.7777719+02:00] Started testing 25929 MB with 16 thread(s).
[2018-06-06T20:46:31.1620799+02:00] ERROR DETECTED!
[2018-06-06T20:46:34.6797303+02:00] Stopped testing after 0:00:56:19 with 1508 % coverage and 1 error(s).	SOC 1.0375v RAM 1.35v Ohm 24-24-24-24 CLLO_VDDP 700mV "Fast Timings" + FAN
[2018-06-06T20:49:08.7809662+02:00] Started testing 26481 MB with 16 thread(s).
[2018-06-06T20:49:28.8552513+02:00] RAM Test is up-to-date.
[2018-06-06T21:57:03.4655159+02:00] Stopped testing after 0:01:07:54 with 1805 % coverage and 0 error(s).	SOC 1.0375v RAM 1.37v Ohm 24-24-24-24 CLLO_VDDP 700mV "Fast Timings" + FAN


----------



## neojack

raucous said:


> I had to hard reset the PC at the end of the test as I think my fancy gaming keyboard failed to respond in the MemTest menu just as my keyboard would fail to respond and bring up the BIOS screen on my old computer.


i have the same problems with keyboard in memtest 86
activate port 64 emulation in the bios, it helps !

PS : it take time for memtest 86 to react to key inputs


----------



## neojack

Vipeax said:


> Anyone here running 16GB modules on a high frequency? I have a 2700X in a X470-i (mini-itx) with 2 memory slots, so I have it running on a F4-3200C14D-32GTZR kit at:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> It feels like 16GB modules/more than 16GB of RAM in total has a large impact on the IMC, which seems to make going beyond 3200, at least on respectable timings, a tough one. Can anyone either confirm or deny this? The above went through 1200% of HCI MemTest and I'm happy with what I have (1.35V on the RAM/1.0V on the SOC, low voltages keep the heat to a minimum in a small case), but I'd still like to know if this is the case or not.



dual rank increases the perfs of the ram, so 3200C14 is more like a 3400-3500C14 , so yeah it's taxing on the IMC 

that say, i was able to attain 3333C14 with this exact CPU, ram kit, and Motherboard.
After some hardware problems caused by myself, I had to get another CPU, motherboard, and Ram.
on the new kit 2 sticks , I was unstable at 3200

so it's part of silicon lottery 

you may find good leads in this thread focused on dual rank 16Gb samsung b-die sticks :
http://www.overclock.net/forum/11-a...duel-rank-2-x-f4-3200c14d-32gtz-kit-64gb.html


----------



## Whatisthisfor

nuthead53 said:


> Just went from getting 3400fast stable and error free with fairly loose timings attached to trying The Stilts 3333 (https://i.imgur.com/LQZeSWE.jpg)
> 
> Got some errors in HCI at about 70% so obviously not stable, not really sure what to go after to improve the stability. I assume voltage is ok and it's just a matter of getting the right balance on timings.
> 
> Using some bdie Corsair 3600 on a 2700x


Try same timings as me first for 3400 1,40V SOC 1,025V and then for 3533 1,44V SOC 1,025V:
http://www.overclock.net/forum/10-a...memory-stability-thread-162.html#post27482724


----------



## Whatisthisfor

neojack said:


> dual rank increases the perfs of the ram, so 3200C14 is more like a 3400-3500C14 , so yeah it's taxing on the IMC
> 
> that say, i was able to attain 3333C14 with this exact CPU, ram kit, and Motherboard.
> After some hardware problems caused by myself, I had to get another CPU, motherboard, and Ram.
> on the new kit 2 sticks , I was unstable at 3200
> 
> so it's part of silicon lottery
> 
> you may find good leads in this thread focused on dual rank 16Gb samsung b-die sticks :
> http://www.overclock.net/forum/11-a...duel-rank-2-x-f4-3200c14d-32gtz-kit-64gb.html


I would say, 3200 CL14 dual rank is like 3600 CL14 single rank performance


----------



## CJMitsuki

Whatisthisfor said:


> I would say, 3200 CL14 dual rank is like 3600 CL14 single rank performance



Ill take that challenge but with 3466mhz single rank. What is dual rank getting in Cinebench? I would say gaming benches but I only have a 1060 6gb so my gaming benches arent going to be good due to that. Here is some of mine. Also, ill drop down to whatever cpu speed you need me to to make it match to whatever you run so the benches can be more even. Im curious to see how well dual rank runs comparatively speaking. Ill get a kit if worth it when ram prices drop.





Spoiler


----------



## chroniclard

CJMitsuki said:


> Ill take that challenge but with 3466mhz single rank. What is dual rank getting in Cinebench? I would say gaming benches but I only have a 1060 6gb so my gaming benches arent going to be good due to that. Here is some of mine. Also, ill drop down to whatever cpu speed you need me to to make it match to whatever you run so the benches can be more even. Im curious to see how well dual rank runs comparatively speaking. Ill get a kit if worth it when ram prices drop.



Hmm, are you using the performance bias? 

Heres mine, "only" 4225 mhz and 3333 RAM but quite a big difference.


----------



## CJMitsuki

chroniclard said:


> CJMitsuki said:
> 
> 
> 
> Ill take that challenge but with 3466mhz single rank. What is dual rank getting in Cinebench? I would say gaming benches but I only have a 1060 6gb so my gaming benches arent going to be good due to that. Here is some of mine. Also, ill drop down to whatever cpu speed you need me to to make it match to whatever you run so the benches can be more even. Im curious to see how well dual rank runs comparatively speaking. Ill get a kit if worth it when ram prices drop.
> 
> 
> 
> 
> Hmm, are you using the performance bias?
> 
> Heres mine, "only" 4225 mhz and 3333 RAM but quite a big difference.
Click to expand...

I’m running CB11.5 but I think it’s the more balanced one and the CB15 bias is the one that favors Cinebench more. Aida bias isn’t that great for Cinebench at all. That is still a really good Cinebench score though. I’ll drop to 4225 here in a bit and test. Might be pretty close. Cinebench does love bandwidth though and you got a lot more than me so you may have it once I drop to 4225. I have been trying to get 1T to work with my same subtimings and it doesn’t seem to be going for it just yet so I’m testing ram at the moment. I think I’m way too tight for 1T. I’ll probably have to relax tRFC and a tiny bit on tRAS and bump voltage. Hopefully.

Edit-just noticed you are single rank too lol. Nvm the part about the bandwidth then. Still really nice CB score.


----------



## CJMitsuki

CJMitsuki said:


> I’m running CB11.5 but I think it’s the more balanced one and the CB15 bias is the one that favors Cinebench more. Aida bias isn’t that great for Cinebench at all. That is still a really good Cinebench score though. I’ll drop to 4225 here in a bit and test. Might be pretty close. Cinebench does love bandwidth though and you got a lot more than me so you may have it once I drop to 4225. I have been trying to get 1T to work with my same subtimings and it doesn’t seem to be going for it just yet so I’m testing ram at the moment. I think I’m way too tight for 1T. I’ll probably have to relax tRFC and a tiny bit on tRAS and bump voltage. Hopefully.
> 
> Edit-just noticed you are single rank too lol. Nvm the part about the bandwidth then. Still really nice CB score.


this is all i could manage on 4.225ghz until I have time to get to 1t on this strap.


----------



## chroniclard

Damn, got 1250% on Ramtest with these settings then got an error.

Anyone suggest what I might tweak? Bit more voltage or soc?


----------



## CJMitsuki

chroniclard said:


> Damn, got 1250% on Ramtest with these settings then got an error.
> 
> Anyone suggest what I might tweak? Bit more voltage or soc?


There’s many things you can try. You can even bump a few timings up a hair like tWR to 12 or tWTRS to 4 or those 2 tWRWR in the tertiaries from 5s to 6s. You can try to bump PLL up a bit or VPP or the 2.5v SB up a bit. There’s proc ODT and cad bus that can give stability. Sometimes more voltage and SoC worsens the situation. I’ve seen many times where too much of either causes errors. So you could even try to take DRAMv down a step and see what it does.


----------



## chroniclard

Ok, thanks once again. Will play some more.


----------



## chroniclard

CJMitsuki said:


> There’s many things you can try. You can even bump a few timings up a hair like tWR to 12 or tWTRS to 4 or those 2 tWRWR in the tertiaries from 5s to 6s. You can try to bump PLL up a bit or VPP or the 2.5v SB up a bit. There’s proc ODT and cad bus that can give stability. Sometimes more voltage and SoC worsens the situation. I’ve seen many times where too much of either causes errors. So you could even try to take DRAMv down a step and see what it does.


Well, I reduced my DRAM V from 1.4 to 1.385 and just hit 2000% so I am happy with that.


----------



## Whatisthisfor

Achieved 3600 CL16-15-15 HCI 300 (32GB) BLC 102 on 2700x & Gigabyte X470 7 Wifi. Vcore 1,45V and SOC 1,025V. LLCs on Auto. Geardown disabled wont boot unfortunately (endless loop), so CL15 wasnt possible, maybe with upcoming BIOS? CL14 did fail after 150%.


----------



## dalaeck

Vipeax said:


> Anyone here running 16GB modules on a high frequency? I have a 2700X in a X470-i (mini-itx) with 2 memory slots, so I have it running on a F4-3200C14D-32GTZR kit at:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> It feels like 16GB modules/more than 16GB of RAM in total has a large impact on the IMC, which seems to make going beyond 3200, at least on respectable timings, a tough one. Can anyone either confirm or deny this? The above went through 1200% of HCI MemTest and I'm happy with what I have (1.35V on the RAM/1.0V on the SOC, low voltages keep the heat to a minimum in a small case), but I'd still like to know if this is the case or not.



I also happen to be trying to get my F4-3200C14D-32GTZ to work on my ASUS X470-I at 14-CL timings. 

My system is slightly different - 2700 not 2700X and furthermore I'm overclocked but under-volted (for thermals, all she can take) at 3475 Mhz and 1.1 V V-core. 



My ram runs solidly 3200 Mhz with CL16-22-22-22 timings - no errors from any stress tests or any memory checking programs. 

Using your exact same settings system is very stable to stress testing, real-bench 15 min, AIDA 64 multiple hours, phoronix-test-suite stress-run. 



But, and here's where I need help from the gurus: it fails memtestx86, consistently, tests 7,8 or 9. Always a few errors. Single digits numbers of errors. 

This is driving me nuts. I want the damn CL-14, because I want it and it's so damn close. 

I've tried a lot of things now, and I really need additional advice/direction from someone more knowledgeable (good guesses welcomed too). 



It will pass a 1 hour stressaptest something like 50% of the time. But that only uses 94% of the ram, whereas memtest uses all of it, and I'm an unlucky sob so there could be some random chicanery going on. 

When stressaptest fails it's always: Report Error: miscompare : DIMM Unknown : 1 Hardware error

And this could be something completely unrelated to the memory itself from my own digging: https://www.reddit.com/r/Amd/comments/8k2jzf/ryzen_2700x_gets_hardware_errors_when_using/


Things I have tried: 



 D.O.C.P and adjusting up and down the soc and ram voltages - more errors in memtestx86 than following settings
 Ryzen DRAM Calculator safe, fast and extreme presets - safe seems to have fewer errors, but it's all single digits error count so margin of error in that statement is large
 Vipeax's precise settings above
 harrysun's settings from this forum http://www.overclock.net/forum/11-a...duel-rank-2-x-f4-3200c14d-32gtz-kit-64gb.html

Vipeax's settings are as good as any for a starting point - what else should I try?


----------



## encrypted11

Are your stressapptest copy rates above 30000MB/s? If the memory settings are optimal you should be getting probably 25000MB/s+ at least.


----------



## dalaeck

*Seems ok?*

Hi encrypted11, log snippet using Viperax settings:

Stats: Found 0 hardware incidents
Stats: Completed: 982466.00M in 36.36s 27019.16MB/s, with 0 hardware incidents, 0 errors
Stats: Memory Copy: 982466.00M at 27536.90MB/s


At 94% usage -> 27539/0.94 = 29293 MB/s for the full kit

Seems ok?


----------



## encrypted11

No real anomaly right there 

On a watered down version of The Stilt's 3200 fast profile, I'm getting similar numbers. About 97.5% usage, stressapptest -M 14500 -W -s 7200


----------



## encrypted11

Gear down mode disabled on all of my runs


----------



## minal

dalaeck said:


> Hi encrypted11, log snippet using Viperax settings:
> 
> Stats: Found 0 hardware incidents
> Stats: Completed: 982466.00M in 36.36s 27019.16MB/s, with 0 hardware incidents, 0 errors
> Stats: Memory Copy: 982466.00M at 27536.90MB/s
> 
> 
> At 94% usage -> 27539/0.94 = 29293 MB/s for the full kit
> 
> Seems ok?





encrypted11 said:


> No real anomaly right there
> 
> On a watered down version of The Stilt's 3200 fast profile, I'm getting similar numbers. About 97.5% usage, stressapptest -M 14500 -W -s 7200


I'm also a linux user with F4-3200C14D-32GTZ. I'm using the memory settings found here: https://rog.asus.com/forum/showthre...ules-for-Crosshair-VII-2700X/page2#post719511

stressapptest shows me ~42GB/s, Intel Memory Latency Checker, which @gupsterg recommended for memory testing similar to AIDA64, reports ~46GB/s and latency ~71ns (varies between 65-72ns).


----------



## dalaeck

minal said:


> I'm also a linux user with F4-3200C14D-32GTZ. I'm using the memory settings found here: https://rog.asus.com/forum/showthre...ules-for-Crosshair-VII-2700X/page2#post719511
> stressapptest shows me ~42GB/s, Intel Memory Latency Checker, which @*gupsterg* recommended for memory testing similar to AIDA64, reports ~46GB/s and latency ~71ns (varies between 65-72ns).


Thanks minal - if you (or any other ROG forum user) could do me a favour and re-post the zip file settings I'll test them out right away. Otherwise I'll have to wait until my ROG forum account acquires more permissions (sometime next work week it seems). 

42 GB/s is amazing, I'm confused how sub-timings can impact things that dramatically!


----------



## minal

dalaeck said:


> Thanks minal - if you (or any other ROG forum user) could do me a favour and re-post the zip file settings I'll test them out right away. Otherwise I'll have to wait until my ROG forum account acquires more permissions (sometime next work week it seems).
> 
> 42 GB/s is amazing, I'm confused how sub-timings can impact things that dramatically!


 Here you go. I didn't realize an account was required to access the file.


----------



## dalaeck

*Victory!*



minal said:


> Here you go. I didn't realize an account was required to access the file.


Many thanks!!!! 
I was literally gritting my teeth watching memtest86 count down with no errors! I have no idea which setting did the trick, but that did the trick. I'm done with torture testing my tiny little beast of a machine. Now I can have some fun. 
Intel memory latency checked: ~74 ns 47000 MB/s !


Intel(R) Memory Latency Checker - v3.5
Measuring idle latencies (in ns)...
Memory node
Socket 0 
0 78.4 

Measuring Peak Injection Memory Bandwidths for the system
Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)
Using all the threads from each core if Hyper-threading is enabled
Using traffic with the following read-write ratios
ALL Reads : 47590.0 
3:1 Reads-Writes : 43847.1 
2:1 Reads-Writes : 42208.2 
1:1 Reads-Writes : 40455.2


----------



## minal

dalaeck said:


> Many thanks!!!!
> I was literally gritting my teeth watching memtest86 count down with no errors! I have no idea which setting did the trick, but that did the trick. I'm done with torture testing my tiny little beast of a machine. Now I can have some fun.
> Intel memory latency checked: ~74 ns 47000 MB/s !
> 
> 
> Intel(R) Memory Latency Checker - v3.5
> Measuring idle latencies (in ns)...
> Memory node
> Socket 0
> 0 78.4
> 
> Measuring Peak Injection Memory Bandwidths for the system
> Bandwidths are in MB/sec (1 MB/sec = 1,000,000 Bytes/sec)
> Using all the threads from each core if Hyper-threading is enabled
> Using traffic with the following read-write ratios
> ALL Reads : 47590.0
> 3:1 Reads-Writes : 43847.1
> 2:1 Reads-Writes : 42208.2
> 1:1 Reads-Writes : 40455.2


Congrats. I found it "just worked" and passed extensive stress tests for me too, and I didn't feel like spending time tuning further yet. I applied all the memory related settings including Vdimm and Vsoc. 

Your latency seems a bit higher at 74-78ns. I get 65-72ns. But still an improvement over the original ~90ns. 

Others here get better than 50GB/s and ~60ns, but that's single ranked memory. Not sure what's the record for dual ranked modules.


----------



## dalaeck

Thanks again, yeah if the first part of "getting it to run without errors at CL14" was easier I would be tempted to dive deeper into the sub-timings and eek out more gains, but I've literally been at this for a week. 
Plenty, plenty happy to see the memtests pass. 
I just watched a video on DDR-5066 at computex. I don't even want to think about trying to get such a thing working given how many hours I just sunk into my barely-overclocked 2nd gen "better memory support" ryzen 2.


----------



## encrypted11

minal said:


> I'm also a linux user with F4-3200C14D-32GTZ. I'm using the memory settings found here: https://rog.asus.com/forum/showthre...ules-for-Crosshair-VII-2700X/page2#post719511
> 
> stressapptest shows me ~42GB/s, Intel Memory Latency Checker, which @gupsterg recommended for memory testing similar to AIDA64, reports ~46GB/s and latency ~71ns (varies between 65-72ns).


I was wondering how long was the stressapptest run? The best I've seen was ~37500MB/s on a 30 second run. 
But ~32500MB/s sustained on my 3333 1T RTC profile over 2 hours.


----------



## minal

dalaeck said:


> Thanks again, yeah if the first part of "getting it to run without errors at CL14" was easier I would be tempted to dive deeper into the sub-timings and eek out more gains, but I've literally been at this for a week.
> Plenty, plenty happy to see the memtests pass.
> I just watched a video on DDR-5066 at computex. I don't even want to think about trying to get such a thing working given how many hours I just sunk into my barely-overclocked 2nd gen "better memory support" ryzen 2.


 Thanks go to i_max from ROG forums. I've been surprised at how difficult it is to get decent specs stable. "Better memory support" with Ryzen 2 means "higher probability" of getting it to run at eg 3200MT/s as opposed to virtually no chance. haha 

I get the impression that memory and hardware issues are so tricky that manufacturers guarantee the base JEDEC 2133 ratings and leave anything more to your luck and skill. Even the QVL seems based on trial and error.



encrypted11 said:


> I was wondering how long was the stressapptest run? The best I've seen was ~37500MB/s on a 30 second run.
> But ~32500MB/s sustained on my 3333 1T RTC profile over 2 hours.


I just ran it for 60 seconds and 600 seconds and got the same ~41.6GB/s result. I don't remember the result from longer runs, but it seems to be pretty consistent.


----------



## encrypted11

Thanks for sharing.  I thought 42000MB/s was a good number on this platform though anything 30000MB/s + seem fairly close to the platform's peak copy rate on stressapptest. Guess it might be better.


----------



## dlfpa

[email protected] 1.1v---BIOS F10---Stressapptest---1 Hour--CMK16GX4M2B3200C16










any suggestions? should i tihgten timing a bit more? if so which timings should i test?
i added cpuz over linux ss btw for more information. hope its ok.


----------



## dlfpa

i was trying to tighten my timings a bit, tried cl 16-15-14-13 step by step, used google stressapptest 1hour like instructed here https://rog.asus.com/forum/showthread.php?73665-Our-preferred-memory-stress-test

passed everytime. 

cpuz always showed what i set in bios, until cl13... if i set 14-16-16-32 i see that but even if i set 13-16-16-32 i still see 14-16-16-32.

i don't know if its only in windows or my bios still keeps cl14, i tested with cl13 too it passed the stress test but i'm not sure if it was actually cl13 or still 14. 

heres my bios settings and cpuz in windows: https://imgur.com/a/igbZmyT

why would that happen? is there a calculation or something? like "you can't go below C14 if timingX is above Y clocks" and sets it back to c14? 

or is my ram runs at c13 but only shows up as c14? 
that's kinda weird... tried c12 just to see what it'll show up as but didnt boot, might try at lower mhz just to see but wanted to ask first...


----------



## CJMitsuki

dlfpa said:


> i was trying to tighten my timings a bit, tried cl 16-15-14-13 step by step, used google stressapptest 1hour like instructed here https://rog.asus.com/forum/showthread.php?73665-Our-preferred-memory-stress-test
> 
> passed everytime.
> 
> cpuz always showed what i set in bios, until cl13... if i set 14-16-16-32 i see that but even if i set 13-16-16-32 i still see 14-16-16-32.
> 
> i don't know if its only in windows or my bios still keeps cl14, i tested with cl13 too it passed the stress test but i'm not sure if it was actually cl13 or still 14.
> 
> heres my bios settings and cpuz in windows: https://imgur.com/a/igbZmyT
> 
> why would that happen? is there a calculation or something? like "you can't go below C14 if timingX is above Y clocks" and sets it back to c14?
> 
> or is my ram runs at c13 but only shows up as c14?
> that's kinda weird... tried c12 just to see what it'll show up as but didnt boot, might try at lower mhz just to see but wanted to ask first...



If I were to guess Id say you have Gear Down Mode enabled. You cant run an odd numbered Cas with it enabled, It will revert you to the next even number. Looking at your timings, I would stop worrying about getting Cas as low as possble and get the other Primary timings and the subtimings tightened up instead of using Auto to set them. There is a massive amount of performance hiding in the subtimings if you manually tighten them. Dropping your Cas as low as you can go isnt going to benefit you if your subtimings are trash.


----------



## dlfpa

CJMitsuki said:


> If I were to guess Id say you have Gear Down Mode enabled. You cant run an odd numbered Cas with it enabled, It will revert you to the next even number. Looking at your timings, I would stop worrying about getting Cas as low as possble and get the other Primary timings and the subtimings tightened up instead of using Auto to set them. There is a massive amount of performance hiding in the subtimings if you manually tighten them. Dropping your Cas as low as you can go isnt going to benefit you if your subtimings are trash.


 i can use cas 15 though... and i really don't know much about sub timings... can you help me a bit because it's so confusing for me. i'm not experienced with ram overclock... 

based on stable 14-16-16-32 main timings what should be my next step in subtimings?


edit:
ah i searched a bit and see it's activates after 2666mhz which explains i could use c15 at 2133.
now tried c15 3066 and it showed up as c16 okay. it's that mode for sure. thanks for the info. still i would gladly accept help for subtimings


----------



## CJMitsuki

dlfpa said:


> i can use cas 15 though... and i really don't know much about sub timings... can you help me a bit because it's so confusing for me. i'm not experienced with ram overclock...
> 
> based on stable 14-16-16-32 main timings what should be my next step in subtimings?
> 
> 
> edit:
> ah i searched a bit and see it's activates after 2666mhz which explains i could use c15 at 2133.
> now tried c15 3066 and it showed up as c16 okay. it's that mode for sure. thanks for the info. still i would gladly accept help for subtimings





I really couldnt tell you as I dont know what model ram you have firstly and secondly each kit is different. Have you checked out the DRAM calculator thread and looked into that tool? Also you have to read these forum threads and you will gather information on memory OC there is plenty of information out there. Ask question and study a bit, YouTube videos are ok to watch as well.

DRAM Calculator thread
http://www.overclock.net/forum/13-amd-general/1640919-ryzen-dram-calculator-1-1-0-beta-2-overclocking-dram-am4.html



Now the calculator isnt meant to give you the perfect timings but it is meant to get you close. A lot of people can just plug the numbers in and it work the first time and others have to work a bit to get them working. That will depend a lot on the frequency you plan to run. It is a really nice tool, especially for someone that isnt familiar with memory timings. Id suggest using it and do lots of research in the forum threads to help you understand it a bit better. Youd be surprised at what you will learn and how much better your performance will be once you adjust those subtimings. Just keep a saved profile with a safe setup so you can always revert to it in case you cant boot with certain timings. Also, only change one thing at a time and test it so youll know if it worked or not. If you change 5 different things and you cant boot then how do you know which out of the 5 are not working? Memory timings are also time consuming so expect to spend a lot of time on them getting them correct, that is the cost of the added performance unless you get lucky and just plug those calculator numbers in and everything works and is stable.


----------



## KeY0Ke

Hello all

I have just built a system with the configuration and issue encountered as of below:

CPU: AMD Ryzen 2700X

Motherboard: Asrock X470 Taichi Ultimate

RAM: Gskill Trident Z RGB DDR4 3200Mhz 4 x 8GB (B Die) F4-3200C14Q-32GTZRX

PSU: Seasonic 750W Prime Titanium

Operating System & Version: Windows 10


When the PC cold boot, before showing the log in screen/after showing log in screen, Windows will BSOD. This issue occurs every single cold boot, however, after cold boot, everything is working fine and no problem. I have only set XMP profile at the Bios level without any tweaking. BSOD code is IRQL NOT LESS OR EQUAL

I have tried to run memtest84 (1 loop) and memtest64 (18 loops) and did not detect any memory errors. I have also updated to latest beta bios but issue still persist

Appreciate the help and advices provided in advance! really hope to get this to work as i have already paid extra to get the b die rams thinking it will minimise the issues encountered

I have tried the ryzen dram timing calculator, it comes out with CL20/22 configuration which i am really not really keen to try

This is the screenshot from the ryzen timing checker


Spoiler


----------



## chroniclard

I there anything here I could look to tweak to reduce latency?


----------



## dlfpa

CJMitsuki said:


> I really couldnt tell you as I dont know what model ram you have firstly and secondly each kit is different. Have you checked out the DRAM calculator thread and looked into that tool? Also you have to read these forum threads and you will gather information on memory OC there is plenty of information out there. Ask question and study a bit, YouTube videos are ok to watch as well.
> 
> DRAM Calculator thread
> http://www.overclock.net/forum/13-amd-general/1640919-ryzen-dram-calculator-1-1-0-beta-2-overclocking-dram-am4.html
> 
> 
> 
> Now the calculator isnt meant to give you the perfect timings but it is meant to get you close. A lot of people can just plug the numbers in and it work the first time and others have to work a bit to get them working. That will depend a lot on the frequency you plan to run. It is a really nice tool, especially for someone that isnt familiar with memory timings. Id suggest using it and do lots of research in the forum threads to help you understand it a bit better. Youd be surprised at what you will learn and how much better your performance will be once you adjust those subtimings. Just keep a saved profile with a safe setup so you can always revert to it in case you cant boot with certain timings. Also, only change one thing at a time and test it so youll know if it worked or not. If you change 5 different things and you cant boot then how do you know which out of the 5 are not working? Memory timings are also time consuming so expect to spend a lot of time on them getting them correct, that is the cost of the added performance unless you get lucky and just plug those calculator numbers in and everything works and is stable.



my rams are close to their limits i guess, i just tried to lower tRC from 54 to 52 and bsod on boot... 

might try others one by one when i have more free time but yeah... 



which timings affects the performance more though? which ones i should prioritize?
for example, is trying higher CL to reduce tRC really worth? does timings affect each others limits on how low the can be? 



btw i'm using the xmp profile and lowering frequency and main timings. sub timings are not set by cpu, all auto by xmp(as far as i know) if xmp contains timings for subtimings as well...


that tool calculated tRC 52 for safe 46 for fast and 38 for extreme btw. even 52 doesn't work. and my main timings are the same as fast. 14-16-16-16-32 so if that calculation was fine for mine i should've boot with tRC46, i can't even boot with 52. 

https://i.imgur.com/ImWwyNW.png 



i'll try the rest but i really don't know which ones i should focus first.


----------



## dlfpa

i'm getting lower cinebench score with tighter timings, is that normal? why could that be happening?


my timings were 14-16-16-16-32, all subtimings were auto
now i tightened timings to 14-15-15-30 also tightened most of the subtimings too. current settings: https://i.imgur.com/S7igV5x.png



cinebench score was 1583 now with tighter timings it's 1574...


rest are the same. cpu clock, voltages etc...


----------



## tekjunkie28

First off I'd like to say that the ryzen Dram calculator needs help it something else is wrong. The settings it gives me dont work at all. So u tried the Stilts timings and his work flawlessly on 3200 and now testing up to 3466Mhz at 15-15-15... timings and so far it has passed 6 hours as of this morning. Why is the ryzen dram calculator not working for me worth my Samsung B die flare X 14 14 14 14 34/36? memory?


Also why can I not get geardown mode to disable unless I'm in 2T command mode?? Is that normal?

What is power down mode and does it have anything to do with speed? 

My specs are 2700x at stock and a gigabyte gaming 5 x470. 

Sent from my SM-N950U using Tapatalk


----------



## tekjunkie28

encrypted11 said:


> Thanks for sharing.  I thought 42000MB/s was a good number on this platform though anything 30000MB/s + seem fairly close to the platform's peak copy rate on stressapptest. Guess it might be better.


On a 2700X on aida inwas getting 38,000MBps at 2400Mhz mem on read. Now I'm getting 53000 on 3466Mhz but 2T and 15CL timings gear down mode disabled.

Sent from my SM-N950U using Tapatalk


----------



## KeY0Ke

Removed duplicate post


----------



## KeY0Ke

tekjunkie28 said:


> First off I'd like to say that the ryzen Dram calculator needs help it something else is wrong. The settings it gives me dont work at all. So u tried the Stilts timings and his work flawlessly on 3200 and now testing up to 3466Mhz at 15-15-15... timings and so far it has passed 6 hours as of this morning. Why is the ryzen dram calculator not working for me worth my Samsung B die flare X 14 14 14 14 34/36? memory?
> 
> 
> Also why can I not get geardown mode to disable unless I'm in 2T command mode?? Is that normal?
> 
> What is power down mode and does it have anything to do with speed?
> 
> My specs are 2700x at stock and a gigabyte gaming 5 x470.
> 
> Sent from my SM-N950U using Tapatalk


I have also tried silits timing and also ryzen calculator timings. With geardown disabled, i cant get it to cold boot successfully. Am4 advance training will keep posting for 3 times (pc on and off after few seconds) due to memory training fail i believe. 

My ram is gskill trident z rgb 4 x 8gb b die. Default is 2T though but i change it to 1T at stock voltage 1.35v 14-14-14-28 stilts safe timing

Passed gsat for 1 hour though. Dont have time to test that long. So i am using it as of now. Speed is about 40753mbps though. I cant expect much as i am using 4 dimms compared to most using 2 dimms here which is more stressful for the imc. So guess i will just live with it. I rather have stable post instead of peak performance


----------



## CJMitsuki

Everyone seems to think that memory OC should just be plug and play with no real dedication of effort. The DRAM calculator will NEVER BE PLUG AND PLAY FOR EVERYONE. Hell it wont even be plug and play for most. Same with the Stilts presets, what works for you may not work for the next person even with the exact same model ram. You have to take in the quality of silicon in the chips, the type of motherboard and the quality of the manufacturing process, the Quality of the silicon in the CPU and how good the IMC is, heat, voltages, other bios settings, etc. I could go all day on factors that could mean that your particular set wont work when another person that has the same set does. The DRAM calculator is to get you in the vicinity of the timings you need, it is up to you to research and learn memory timings. Just go to Google and type in something like "Understanding Memory Timings" or something to that effect, go to the forums and just read and ask questions and see what opinions are and other users experiences with that particular setup or system. Dont just go to a couple of threads and read 2 posts, go to many different forums and read a wide variety of information. Then when you feel like you have a small amount of knowledge, enough to get you started at least, then experiment yourself. That being said you should, in your research, found the consequences of inputting bad timings and how to revert those consequences and more importantly the risks and consequences of going outside of the safe voltages for ddr4 and the Ryzen IMC. You need to get yourself educated on what you are going rather than plugging something in and it not working then asking why it isnt working. Its ok to ask for help and most have no problem giving help but some make no attempt to learn and want it done for them all them time. This will be especially true with memory OC bc there is so much investment into the research as the information is vast and takes quite awhile to grasp just a small amount of the basics. Memory timings behavior is really very mysterious for the most part as well so the best thing you can do is research and figure some things out for yourself. Get yourself a notebook and write things down so you can look back and see what changing this timing resulted in and so on and so forth. Also, when you do ask for help, include cpu-z memory screen shots with the model number in your post. Its really important to know if you have hynix AFR or Samsung E-Die, or Samsung B-Die as they all behave totally different from one another. 

If you dont spend a bit of time to learn how to overclock memory then you should not fool with it because you wont always have the plug and play result that most think you will. I get frustrated at memory behavior quite often but those frustrations push me to learn more so there will be less frustration in the future. Again, Im not saying to refrain from asking for help but dont get in the habit of it being your first action rather than trying to learn for yourself. If you come asking for help and people see that you have a basic understanding of memory then they know you have took the initiative to help yourself a bit and makes them want to help you rather than someone saying a piece of software is to blame for incorrect memory timings when it cant know the condition of the silicon, the mobo, and other such influences on memory. It is merely a tool to help those that already have a basic understanding as there will never be "cookie cutter" timings that work with every B-Die kit or any other kit for that matter.


----------



## KeY0Ke

CJMitsuki said:


> Everyone seems to think that memory OC should just be plug and play with no real dedication of effort. The DRAM calculator will NEVER BE PLUG AND PLAY FOR EVERYONE. Hell it wont even be plug and play for most. Same with the Stilts presets, what works for you may not work for the next person even with the exact same model ram. You have to take in the quality of silicon in the chips, the type of motherboard and the quality of the manufacturing process, the Quality of the silicon in the CPU and how good the IMC is, heat, voltages, other bios settings, etc. I could go all day on factors that could mean that your particular set wont work when another person that has the same set does. The DRAM calculator is to get you in the vicinity of the timings you need, it is up to you to research and learn memory timings. Just go to Google and type in something like "Understanding Memory Timings" or something to that effect, go to the forums and just read and ask questions and see what opinions are and other users experiences with that particular setup or system. Dont just go to a couple of threads and read 2 posts, go to many different forums and read a wide variety of information. Then when you feel like you have a small amount of knowledge, enough to get you started at least, then experiment yourself. That being said you should, in your research, found the consequences of inputting bad timings and how to revert those consequences and more importantly the risks and consequences of going outside of the safe voltages for ddr4 and the Ryzen IMC. You need to get yourself educated on what you are going rather than plugging something in and it not working then asking why it isnt working. Its ok to ask for help and most have no problem giving help but some make no attempt to learn and want it done for them all them time. This will be especially true with memory OC bc there is so much investment into the research as the information is vast and takes quite awhile to grasp just a small amount of the basics. Memory timings behavior is really very mysterious for the most part as well so the best thing you can do is research and figure some things out for yourself. Get yourself a notebook and write things down so you can look back and see what changing this timing resulted in and so on and so forth. Also, when you do ask for help, include cpu-z memory screen shots with the model number in your post. Its really important to know if you have hynix AFR or Samsung E-Die, or Samsung B-Die as they all behave totally different from one another.
> 
> If you dont spend a bit of time to learn how to overclock memory then you should not fool with it because you wont always have the plug and play result that most think you will. I get frustrated at memory behavior quite often but those frustrations push me to learn more so there will be less frustration in the future. Again, Im not saying to refrain from asking for help but dont get in the habit of it being your first action rather than trying to learn for yourself. If you come asking for help and people see that you have a basic understanding of memory then they know you have took the initiative to help yourself a bit and makes them want to help you rather than someone saying a piece of software is to blame for incorrect memory timings when it cant know the condition of the silicon, the mobo, and other such influences on memory. It is merely a tool to help those that already have a basic understanding as there will never be "cookie cutter" timings that work with every B-Die kit or any other kit for that matter.


What you have said is correct. But i think most of us here are too spoilt by how easy to get rams running on intel chipset. Just go in to bios and set xmp profile. For ryzen, even if you enable xmp profile, it might not be stable too like my case when i am using 4 dimms

Ryzen timing calculator is just a guideline, and we have to tune accordingly to the performance of our individual components

Ryzen requires ram tuning as they are more stringent on it. Yes silicon lottery plays a part too and people using 2 or 4 dimms or even single or dual rank memories will have different capabilities on the timings and frequencies they are able to achieve as 4 dimms and dual ranks memory will be more stressful for imc. 

To keep it simple, if want plug and play, go with intel and enable xmp, if you like to tune then ryzen is a good platform to play with

Ryzen has too much considerations to take care, gsat and memtest stable does not mean is cold boot stable


----------



## minal

CJMitsuki said:


> Everyone seems to think that memory OC should just be plug and play with no real dedication of effort.


 The problem is that anything but the lowest speeds is considered "OC". Plug and play is exactly what I expect for setting up a system with good, rated, performance. 

The rest of what you describe makes sense for getting the maximum performance out of a component, setting OC records, etc. But that also leaves little margin for error, which easily results in broken systems in the future. It's a different kind of user who wants that.

The title of this thread is "Ryzen DDR4 24/7 Memory Stability" and it's unfortunate that non-OCers have to come here to get their "OC" 3200MT/s RAM to work properly if at all. 

Alternatively there are always cases like someone I know who for a business computer bought "OC" RGB RAM and didn't even bother (or know about) setting DOCP. Yay for JEDEC 2133.. lol


----------



## minal

KeY0Ke said:


> To keep it simple, if want plug and play, go with intel and enable xmp, if you like to tune then ryzen is a good platform to play with


I don't buy that. Ryzen isn't just for tweakers, although it's great that it's so open for enthusiasts to dig into the details. But Ryzen also makes sense for a lot of "regular" users who don't have the time or desire to tune things just to run their system.


----------



## encrypted11

As someone that is tuning RAM on Intel CoffeeLake and AMD Pinnacle Ridge, I think some of the memory compatibility behavior (or lack of) are grossly misunderstood to be expected behavior right here. Subtiming tuning are almost already a "must have" at speeds like 3200MHz on this platform in terms of readiness for stressapptest. That's a stark contrast compared to pretty much plug and play 3600MHz 4 DIMMs hardware reps like [email protected] are willing to cite (which is already an underestimate). Subtiming tuning comes later when you're up for improving memory performance on coffeelake than an outright compatibility adjustment on my experiences with PR.

While I'm glad in stability terms the IMC on Ryzen passes google stressapptest at reasonable settings likely between 3200-3333MHz, it is still by far out run by the Intel IMC that does's 4000MHz, 2 or 4 dimms on a motherboard with a good memory trace layout and reasonable number of PCB layers. Considering the hardware IP hasn't changed between SR and PR aside for better firmware, I believe we're close to saturation of the SR/PR IMC capability on RAMs that scale very well (b die for example).


----------



## KeY0Ke

minal said:


> I don't buy that. Ryzen isn't just for tweakers, although it's great that it's so open for enthusiasts to dig into the details. But Ryzen also makes sense for a lot of "regular" users who don't have the time or desire to tune things just to run their system.


Lol i might think other wise. Part of the reason is the issue i encountered with my 4 dimms on my board. Luckily i get to the end result i got. I even considered to only run 16gb memory on my set up, but i am running VMs, i need the 32gb and even if i buy dual rank 16gb ram with 2 dimms, i doubt is going to simplify the issue either.


----------



## CJMitsuki

minal said:


> The problem is that anything but the lowest speeds is considered "OC". Plug and play is exactly what I expect for setting up a system with good, rated, performance.
> 
> The rest of what you describe makes sense for getting the maximum performance out of a component, setting OC records, etc. But that also leaves little margin for error, which easily results in broken systems in the future. It's a different kind of user who wants that.
> 
> The title of this thread is "Ryzen DDR4 24/7 Memory Stability" and it's unfortunate that non-OCers have to come here to get their "OC" 3200MT/s RAM to work properly if at all.
> 
> Alternatively there are always cases like someone I know who for a business computer bought "OC" RGB RAM and didn't even bother (or know about) setting DOCP. Yay for JEDEC 2133.. lol



Well, to be fair a good 16-32gb kit is going to perform decently and if you dont know what benchmarks are and dont care then how will even know that there is a great deal of performance "hiding" within the timings and bios settings. Moth of those types wont buy a high end board to even have those settings and if they do I doubt they even touch the bios. In other words, "What you dont know, wont hurt you." The fact of the matter is that we have people that are here on an overclocking forum and I assume it is to help others or to learn from others about these things. Im just trying to point them in a direction that includes them helping themselves just as much as they are helped. Thats what leads to fruitful knowledge and hopefully any knowledge gained will be shared with another. I can be shown how to do something and learn what is shown to me but it doesnt help me in different scenarios when varibles are changed. If I research and learn some on my own I can mitigate that downside a bit. The rest comes from actual trial and error through experience which is the best way to learn for me. Either that or go into rage mode from trying for hours and hours and going backwards in performance which does happen sometimes. Ive spent many hours that led to no performance gained but did help me learn what not to do :lachen:


----------



## CJMitsuki

minal said:


> I don't buy that. Ryzen isn't just for tweakers, although it's great that it's so open for enthusiasts to dig into the details. But Ryzen also makes sense for a lot of "regular" users who don't have the time or desire to tune things just to run their system.



If they dont want to tweaK memory or cpu then they dont have to. Just boot it up and dont touch the bios and if it doesnt boot due to memory problems then its a simple RMA. Otherwise it will run fine but at 2133mhz, beyond that you will have possibly have to "tweak" things a bit. You arent going to be gimped because you didnt OC and get every possible bit out of the system. It just wont run as well as someone who took the time to do that but it will still run quite well. If it bothers someone that they wont get the same level of performance then they should educate themselves to gain that performance increase.


----------



## minal

KeY0Ke said:


> Lol i might think other wise. Part of the reason is the issue i encountered with my 4 dimms on my board. Luckily i get to the end result i got. I even considered to only run 16gb memory on my set up, but i am running VMs, i need the 32gb and even if i buy dual rank 16gb ram with 2 dimms, i doubt is going to simplify the issue either.


I think I was unclear and/or you misunderstood: In principle Ryzen marketing and relevance aren't exclusive to enthusiasts, although effectively it seems that way once trying to setup a system at least on the RAM front.



CJMitsuki said:


> Well, to be fair a good 16-32gb kit is going to perform decently and if you dont know what benchmarks are and dont care then how will even know that there is a great deal of performance "hiding" within the timings and bios settings.


A good kit... rated at 2133? 3200?

I would agree if the difference in performance weren't so huge, and if reviews were just going by 2133... But a factor of two difference in memory throughput isn't something to ignore. Most people won't want to leave that kind of performance on the table, but would be willing to say take 80-90% of it by buying a well-rated kit (eg. 3200), and sacrifice the remainder of what could be had in the interest of stability and time. We're not talking about getting every last bit of performance. 

To me it sounds like requiring anyone who buys more than a 4 cylinder vehicle to be a mechanic/tuner. Sure you could get more out of it, but most want to get their stock V6/V8/V12 and just drive off without a hassle.


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## CJMitsuki

minal said:


> To me it sounds like requiring anyone who buys more than a 4 cylinder vehicle to be a mechanic/tuner. Sure you could get more out of it, but most want to get their stock V6/V8/V12 and just drive off without a hassle.



No, its more like anyone wanting to buy a 4 cylinder should know its a 4 cylinder but also has the ability to do much more than stock if they learn how to get it to do so properly. Sounds like you are comparing buying a Dell POS to buying a 5000$ custom computer with your analogy inistead of comparing ram advertising being misleading or obtuse. I do agree however that they should be a bit more forthcoming when they advertise ram though. Stating this is 3200mhz ram is a bit misleading. They should say, this ram has been rated to be able to be overclocked to 3200mhz but is not guaranteed as well as let them know that stock is 2133mhz. Most corporations are misleading though so no real shocker there.


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## tekjunkie28

Well I'm just gonna say that the dram calculator isn't correct in a few sets of timing. I dont remember what they are called but the set of subtimings 1-7-7. Dram calc says 1-6-6 and 1-5-5 for extreme I think on Samsung B due. Those timings dont run at all at 6's, not even Stilts timings put them at 6's. Stilts timing put them st 7 even in fast so that's what I did and they are flawless. I'm just saying the Dram calculator needs some adjustments. 

Sent from my SM-N950U using Tapatalk


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## CJMitsuki

tekjunkie28 said:


> Well I'm just gonna say that the dram calculator isn't correct in a few sets of timing. I dont remember what they are called but the set of subtimings 1-7-7. Dram calc says 1-6-6 and 1-5-5 for extreme I think on Samsung B due. Those timings dont run at all at 6's, not even Stilts timings put them at 6's. Stilts timing put them st 7 even in fast so that's what I did and they are flawless. I'm just saying the Dram calculator needs some adjustments.
> 
> Sent from my SM-N950U using Tapatalk


I’ve gotten that set of tertiary timings to hit 661551 and much lower plenty of times. Some timings rely heavily on other subtimings and if a certain timing is a certain amount then you can’t run below a certain amount on another related subtiming. Like tCWL for instance, you can’t take it higher than the Cas latency but you can go lower but if you have an odd Cas then the rule fir tCWL is Cas-1 bc for some reason tCWL doesn’t like odd numbers as well as anything above Cas. I’m sure there are many hard rules that are much more obscure. Again, the DRAM calculator doesn’t give you the answers, it is a guide to show you the right area and it’s up to you to find the exact timings. It can’t account for your CPU silicon quality and such. Some people don’t even start with an IMC strong enough to run BDie above 3000, is that the calculators fault since it says Cas should be 14 but they have to run it on 15? There are many variables that the calculator simply cannot account for. If you can’t run those tertiaries below 661441 then it’s something on your end causing a variance. Just two nights ago I had 3466 tighter than extreme settings running 331221. Not saying it was good to be that low bc there is a point where lowering subtimings is detrimental to performance but it can run below 661441 for sure. Doubt you will see much gain for being below that though.


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## minal

CJMitsuki said:


> Sounds like you are comparing buying a Dell POS to buying a 5000$ custom computer with your analogy


This memory experience makes a compelling argument for buying pre-built systems.



CJMitsuki said:


> No, its more like anyone wanting to buy a 4 cylinder should know its a 4 cylinder but also has the ability to do much more than stock if they learn how to get it to do so properly.


Ok, sticking with the 4 cylinder analogy, you could get a VW Golf (2133)... or a factory tuned GTI (2933) or R (3200). But currently with memory, you have reviews boasting about R performance, or even R plus custom modifications, but then expecting everyone to buy a Golf and be responsible for the modifications themselves.

Your arguments make perfect sense for the target audience of this site: OCers. But not for the majority of people who want to run stable high-performance systems.

Consider professionals (computational researchers, CAD engineers, etc) who want added performance from their system and memory (eg, GTI or R), but also stability and time savings (factory warranty, turnkey solution). 

Additionally, when people ask for recommendations before purchasing a system, everyone tells them Ryzen does much better with faster memory and they should get as fast as they can afford. After purchase... muahaha they are responsible to tune it themselves or run it at 2133!


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## Causticspit

Hi, I have a Threadripper 1950X unlocked on a ROG Strix X399-E Gaming Motherboard. I have 3Ghz speed RAM 16GB of it. If I overclock the CPU to 4Ghz all is good. I stress tested it with Prime 95 for a couple of hours and it stayed stable and pretty cool at 56C.

If I look at my RAM speed it's only at 2100Mhz. If I increase it using the Multiplier It crashes. I have tried other RAM and it's the same story. What's the secret to overclocking RAM? CPU seems easy to overclock, but RAM seems like Black Magic!


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## CJMitsuki

minal said:


> CJMitsuki said:
> 
> 
> 
> Sounds like you are comparing buying a Dell POS to buying a 5000$ custom computer with your analogy
> 
> 
> 
> This memory experience makes a compelling argument for buying pre-built systems.
> 
> 
> 
> CJMitsuki said:
> 
> 
> 
> No, its more like anyone wanting to buy a 4 cylinder should know its a 4 cylinder but also has the ability to do much more than stock if they learn how to get it to do so properly.
> 
> Click to expand...
> 
> Ok, sticking with the 4 cylinder analogy, you could get a VW Golf (2133)... or a factory tuned GTI (2933) or R (3200).
Click to expand...

Ok, I gotcha. So what is the model number of your ram and post your Ryzen Timing screenshot and which mobo are you using? I’ll see if I can help out once I’m off work and home where I can be of use as I’m at lunch on the job and can’t really help much but I can get info in the meantime.



Causticspit said:


> Hi, I have a Threadripper 1950X unlocked on a ROG Strix X399-E Gaming Motherboard. I have 3Ghz speed RAM 16GB of it. If I overclock the CPU to 4Ghz all is good. I stress tested it with Prime 95 for a couple of hours and it stayed stable and pretty cool at 56C.
> 
> If I look at my RAM speed it's only at 2100Mhz. If I increase it using the Multiplier It crashes. I have tried other RAM and it's the same story. What's the secret to overclocking RAM? CPU seems easy to overclock, but RAM seems like Black Magic!


No offense but the only thing you have told me is that you have 3000mhz ram. You’ll have to come more specific than that. Like model number of your ram for starters. You could be running Hynix AFR dies for all I know. Secondly which multiplier are you referring to? The bclk multiplier? Mclk multiplier if your board supports asynchronous mode? Either way trying to overclock ram that way will not produce much in the way of positive results. I can tell you probably have little if any knowledge about ram and possibly about the bios. I’ll see what I can do later once I’m home though. If you don’t know much about it you may have to enable XMP and pray it works if your ram even has an XMP profile. Just let me get the ram model number and Ryzen Timing screenshot in the meantime.


----------



## minal

CJMitsuki said:


> Ok, I gotcha. So what is the model number of your ram and post your Ryzen Timing screenshot and which mobo are you using? I’ll see if I can help out once I’m off work and home where I can be of use as I’m at lunch on the job and can’t really help much but I can get info in the meantime.


 That's generous of you. These remarks are general about the state of Ryzen + memory. My system is actually stable at 3200MT/s.

Some folks here including myself are using memory settings/Vsoc/etc (attached) by i_max from ROG forums. If you'd like to take a look and comment, that would of course be welcomed. Hardware is 2700X, C7HWIFI, 2x16GB F4-3200C14D-32GTZ and several people here and on the C7H thread have the same or similar setup.


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## tekjunkie28

CJMitsuki said:


> I’ve gotten that set of tertiary timings to hit 661551 and much lower plenty of times. Some timings rely heavily on other subtimings and if a certain timing is a certain amount then you can’t run below a certain amount on another related subtiming. Like tCWL for instance, you can’t take it higher than the Cas latency but you can go lower but if you have an odd Cas then the rule fir tCWL is Cas-1 bc for some reason tCWL doesn’t like odd numbers as well as anything above Cas. I’m sure there are many hard rules that are much more obscure. Again, the DRAM calculator doesn’t give you the answers, it is a guide to show you the right area and it’s up to you to find the exact timings. It can’t account for your CPU silicon quality and such. Some people don’t even start with an IMC strong enough to run BDie above 3000, is that the calculators fault since it says Cas should be 14 but they have to run it on 15? There are many variables that the calculator simply cannot account for. If you can’t run those tertiaries below 661441 then it’s something on your end causing a variance. Just two nights ago I had 3466 tighter than extreme settings running 331221. Not saying it was good to be that low bc there is a point where lowering subtimings is detrimental to performance but it can run below 661441 for sure. Doubt you will see much gain for being below that though.


That's interesting. I think my IMC is pretty decent. So far I'm stable with stilts timings for 3466 and 1000%+ of HCI memtest. 

What does everyone use to test memory? 

Sent from my SM-N950U using Tapatalk


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## KeY0Ke

Just an udpate, i have already found the root cause of the BSOD.
Somehow, fast boot is causing the BSOD. hence, disabling fastboot solves the problem for my BSOD.

I am also tuning my RAM the last few days. 

Managed to achieve GSAT stable for 1 hour at 1.35v 3200MHz CL14-14-14-14-28 (Stilts timing) but with geardown enabled. With geardown disabled, i cant cold boot successfully.

Below is my screenshots:


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## encrypted11

Impressive at 40753MB/s within the Linux shell in Windows.

The best in my own run in mint 18.3.


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## Hequaqua

encrypted11 said:


> Impressive at 40753MB/s within the Linux shell in Windows.
> 
> The best in my own run in mint 18.3.


Where do you see that you had 40753Mb/s? 

New to reading the speeds, was curious. :thumb:


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## encrypted11

The summary page, stats, @KeY0Ke 's 4 dimm overclock.


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## Kildar

I got 3200 from my ram at stock settings from day one with my previous 1700.

I lucked out and bought G.Skill Samsung B-Die F4-3200 @ 14-14-14-34 for my initial build.

Since upgrading to a 2700x I have been able to tighten my timings considerably.

The trick is to buy good ram and Samsung B-die kits seem to be the best.


----------



## Hequaqua

encrypted11 said:


> The summary page, stats, @KeY0Ke 's 4 dimm overclock.


Ah...OK....I was confused...your run is the one in the pic, correct?

Which was 32543MB/s.


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## encrypted11

Thats right


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## Jedson3614

Hey guys, I am working on a build and overclocking guide for AMD 7 ASUS here on OCN, similar o my Coffe lake one but I had some questions. I've run into a wall where I believe my IMC isn't good enough to run 3600 MHZ. I've tried all the usual SoC to 1.2, and even tried 1.4V on memory voltage. Seem's my chip works great though using XFR2 and 3466. That is SoC on auto and no additional voltage on memory. Have any of you seen any success in reaching 3600Mhz? The press kit AMD sent out does not include 3600MHz RAM and in fact, has a 3400 kit. I'm using the latest bios but was just curious how luck any of you guys were. It would appear not too many reviews or even overclockers are hitting 3600Mhz but some are. I wonder what the percentage is? The voltage curve on Ryzen+ seems to be an interesting thing to look into for my article.


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## Anty

"and tried *even* 1.4V on memory voltage"


Even should be 1.5 
Depending on CPU and BIOS you may need 1.4 to run 3200. My chip won't do 3466 below 1.42 nowadays and was around 1.45 in the past (1700 though, not 2700).

Yes I did 3600 but it was 1.48 on DRAM.


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## tekjunkie28

Jedson3614 said:


> Hey guys, I am working on a build and overclocking guide for AMD 7 ASUS here on OCN, similar o my Coffe lake one but I had some questions. I've run into a wall where I believe my IMC isn't good enough to run 3600 MHZ. I've tried all the usual SoC to 1.2, and even tried 1.4V on memory voltage. Seem's my chip works great though using XFR2 and 3466. That is SoC on auto and no additional voltage on memory. Have any of you seen any success in reaching 3600Mhz? The press kit AMD sent out does not include 3600MHz RAM and in fact, has a 3400 kit. I'm using the latest bios but was just curious how luck any of you guys were. It would appear not too many reviews or even overclockers are hitting 3600Mhz but some are. I wonder what the percentage is? The voltage curve on Ryzen+ seems to be an interesting thing to look into for my article.


Is this a 24/7 OC guide? Of so I wouldn't ever venture too far over 1.1V SOC, maybe 1.5V but the thing with Ryzen is there are sweet spots. You may even get better stability at lower voltages. I do sometimes.

As for 3600 I'll check when I get time this weekend but so far I have 3466Mhz almost stable (1 error in 10-12 hours stress test) at 14-14-14-26-44. If I can boot at 3600mhz then I can almost certainly hit 3600 stable. If I cant I'm thinking it's my mobo bc I find that I'm able to push higher and higher with lower voltages tweaking some subtimings. My IMC must be made of iron.

Sent from my SM-N950U using Tapatalk


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## Jedson3614

Anty said:


> "and tried *even* 1.4V on memory voltage"
> 
> 
> Even should be 1.5
> Depending on CPU and BIOS you may need 1.4 to run 3200. My chip won't do 3466 below 1.42 nowadays and was around 1.45 in the past (1700 though, not 2700).
> 
> Yes I did 3600 but it was 1.48 on DRAM.


Ahhhh yeas I have 2700X, and I figured it is possible, I am just trying to gather information on the probability that you'll reach 3600 Mhz. I got 3466 easy on my CPU.


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## Jedson3614

tekjunkie28 said:


> Is this a 24/7 OC guide? Of so I wouldn't ever venture too far over 1.1V SOC, maybe 1.5V but the thing with Ryzen is there are sweet spots. You may even get better stability at lower voltages. I do sometimes.
> 
> As for 3600 I'll check when I get time this weekend but so far I have 3466Mhz almost stable (1 error in 10-12 hours stress test) at 14-14-14-26-44. If I can boot at 3600mhz then I can almost certainly hit 3600 stable. If I cant I'm thinking it's my mobo bc I find that I'm able to push higher and higher with lower voltages tweaking some subtimings. My IMC must be made of iron.
> 
> Sent from my SM-N950U using Tapatalk


More or less yes 24/7 but I will still offer suggestions to boost performance and offer details to anyone willing to risk pushing things just a little further to achieve desired speeds. On air and even water 1.2 isn't that extreme. I probably wouldn't go too much outside of that but I do agree you shouldn't touch SoC unless you have to, auto seems to work just fine for most users.


----------



## encrypted11

Jedson3614 said:


> Hey guys, I am working on a build and overclocking guide for AMD 7 ASUS here on OCN, similar o my Coffe lake one but I had some questions. I've run into a wall where I believe my IMC isn't good enough to run 3600 MHZ. I've tried all the usual SoC to 1.2, and even tried 1.4V on memory voltage. Seem's my chip works great though using XFR2 and 3466. That is SoC on auto and no additional voltage on memory. Have any of you seen any success in reaching 3600Mhz? The press kit AMD sent out does not include 3600MHz RAM and in fact, has a 3400 kit. I'm using the latest bios but was just curious how luck any of you guys were. It would appear not too many reviews or even overclockers are hitting 3600Mhz but some are. I wonder what the percentage is? The voltage curve on Ryzen+ seems to be an interesting thing to look into for my article.


Leave no rocks unturned. But quite frankly I don't think you'd need 1.4+ VDIMM on b dies to peak out on Ryzen.

To put this into perspective, my 1.4V 4266 rated TridentZ B dies do tight 4000MHz C16-1T on CoffeeLake 1.4V with full memory training, MRC Fastboot disabled. I tried busting VDIMM to the high 1.4V range with practically no v/f scaling recorded on this platform. I ended up with a 3333 1T daily profile (google stressapptest) at 1.36V VDIMM which is already an unoptimised voltage point and a random figure I picked; could've gone lower.

Check your kit's scaling on your Coffeelake test rig with the rams from the ryzen press kit to ensure you're not hitting a scaling problem.

Otherwise I'd say at a certain point, the IMC seemed to just hits a hard wall in handling DRAM frequency (albeit at a fairly low SoC voltage). Look at settings like AMD CBS\UMC Common Options\Cad Bus an ProcODT apart from tuned subtimings if you had to.


----------



## CJMitsuki

Jedson3614 said:


> Hey guys, I am working on a build and overclocking guide for AMD 7 ASUS here on OCN, similar o my Coffe lake one but I had some questions. I've run into a wall where I believe my IMC isn't good enough to run 3600 MHZ. I've tried all the usual SoC to 1.2, and even tried 1.4V on memory voltage. Seem's my chip works great though using XFR2 and 3466. That is SoC on auto and no additional voltage on memory. Have any of you seen any success in reaching 3600Mhz? The press kit AMD sent out does not include 3600MHz RAM and in fact, has a 3400 kit. I'm using the latest bios but was just curious how luck any of you guys were. It would appear not too many reviews or even overclockers are hitting 3600Mhz but some are. I wonder what the percentage is? The voltage curve on Ryzen+ seems to be an interesting thing to look into for my article.


Plenty in the CH7 thread hit 3600 including me but it doesn’t matter because you’ll never be able to tighten the timings enough to out perform 3466 or 3533mhz. It’s not even close performance wise. I even had pretty decent timings on 3600 but it just isn’t near enough. You basically have to be able to do 14-14-14-22-36 with GD disabled and 1T and at the current state of things that won’t happen until there is more bios updates furthering memory compatibility. Your performance will come from 3466-3533mhz at this point in time on Ryzen+.


----------



## encrypted11

[email protected] 1.0v---BIOS 0601---Stressapptest---2 Hours--F4-4266C19D-16GTZKW

[email protected] 0.9975v---BIOS 0601---Stressapptest---2 Hours--F4-4266C19D-16GTZKW

Lost my RTC screenies for the 3200 run. They're the identical subs though. Credits: Stilt safe/fast profiles


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## tekjunkie28

So what would you guys call stable? And does AIDA64 make for a good stress test or not? It seems that I can test for 6 to 10 hours and get one 1 error after that. It's just so confusing.

Sent from my SM-N950U using Tapatalk


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## mtrai

tekjunkie28 said:


> So what would you guys call stable? And does AIDA64 make for a good stress test or not? It seems that I can test for 6 to 10 hours and get one 1 error after that. It's just so confusing.
> 
> Sent from my SM-N950U using Tapatalk


TBH it is stable when you feel it is stable for what you want. Others will have different ideas on what is stable...only you can know what works for you. For me what you got 6-10 hours testing with 1 error would stable enough for me. Keep in mind...any overclock is never 100% stable.


----------



## crakej

I've got 3600CL14 for my daily use and can say that what @CJMitsuki says above true. The only real benefit I have is a slightly higher mem transfer rate. You can see my timings below, which I have tried to tighten further - but I get no more performance than I have now with these settings. I am going to go back to slightly lower speeds to see if I can get better performance - might be able to get CL13 at 3466, but not sure will make much difference...

I have same ram as you @encrypted11 - you can see I've had to raise voltages quite a bit to get stability, and the way it's scaling it's going to need more and more as speeds increases. I'd like to know why Ryzen needs all this extra volts while intel does not....not as much anyway. I sometimes think we're just forcing it to work by ramming lots of volts when there might be settings that help us to reduce the amount of voltage Ryzen seems to need.

I've found I need geardown enabled for >3200 - anyone else found this?


----------



## encrypted11

crakej said:


> I have same ram as you @encrypted11 - you can see I've had to raise voltages quite a bit to get stability, and the way it's scaling it's going to need more and more as speeds increases. I'd like to know why Ryzen needs all this extra volts while intel does not....not as much anyway. I sometimes think we're just forcing it to work by ramming lots of volts when there might be settings that help us to reduce the amount of voltage Ryzen seems to need.


My sentiments exact, or it is just us people attempting to workaround the memory instability by brute force?
Either way, I'd like to know the actual reason behind that.


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## crakej

encrypted11 said:


> My sentiments exact, or it is just us people attempting to workaround the memory instability by brute force?
> Either way, I'd like to know the actual reason behind that.


It's interesting - while ryzen uses DDR4, it seems to use it in a very different way to an intel cpu. I do hope they bring us more updates that make DDR4 more efficient - more compatible!

Have you gone over 3333 with Ryzen? Did you have to use geardown?


----------



## encrypted11

crakej said:


> It's interesting - while ryzen uses DDR4, it seems to use it in a very different way to an intel cpu. I do hope they bring us more updates that make DDR4 more efficient - more compatible!
> 
> Have you gone over 3333 with Ryzen? Did you have to use geardown?


Yes I have, but I've attempted to stay away from Geardown Mode similar to MRC Fastboot on Intel whenever possible.

If I remembered correctly, 3466 1T + GDM wasn't remotely close with a kernel panic shortly after boot. Even if it doesn't occur on idle, gsat was able to induce a panic within a matter of seconds. So it probably might happen on 2T with GDM at some point with some timings relaxed but I fell the attempt wasn't worthwhile if I had to turn up more flags to make memory training easier with poorer timings. Who knows, 3466 with GDM disabled might be a different story on the coming PinnaclePI 1004.


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## tekjunkie28

mtrai said:


> TBH it is stable when you feel it is stable for what you want. Others will have different ideas on what is stable...only you can know what works for you. For me what you got 6-10 hours testing with 1 error would stable enough for me. Keep in mind...any overclock is never 100% stable.


That's my thoughts exactly but wanted to know opinions. Thank you. I will do some more work and see what I can do. 

Sent from my SM-N950U using Tapatalk


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## crakej

encrypted11 said:


> Yes I have, but I've attempted to stay away from Geardown Mode similar to MRC Fastboot on Intel whenever possible.
> 
> If I remembered correctly, 3466 1T + GDM wasn't remotely close with a kernel panic shortly after boot. Even if it doesn't occur on idle, gsat was able to induce a panic within a matter of seconds. So it probably might happen on 2T with GDM at some point with some timings relaxed but I fell the attempt wasn't worthwhile if I had to turn up more flags to make memory training easier with poorer timings. Who knows, 3466 with GDM disabled might be a different story on the coming PinnaclePI 1004.


It's been ok with GDM=on - really didn't want to use it at first - though might go back see if I can get 3466 to boot with it off. What I've found a 3600 is that I have a choice - I can do T1, GDM=on or I can do T2 GDM=off. I couldn't even boot 3333 without GDM - maybe more voltage will get it to work....


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## mtrai

tekjunkie28 said:


> That's my thoughts exactly but wanted to know opinions. Thank you. I will do some more work and see what I can do.
> 
> Sent from my SM-N950U using Tapatalk


You will find others here who do not think for example memory is stable until it passes 50,000 %


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## KeY0Ke

crakej said:


> I've found I need geardown enabled for >3200 - anyone else found this?


i need geardown mode with CL14-14-14-14-28 3200Mhz. with geardown mode disabled even on stock timings CL14-14-14-14-34, i got errors in gsat and also issue with cold boot. partly because i am using 4 dimms instead of 2 and i am using 1T instead of 2T. i can get gdm disabled with 2T though.

i have tested that with gdm 1T = no gdm 2T on aida64 tests.


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## KeY0Ke

@Silent Scone
Motherboard is Asrock X470 Taichi Ultimate. Unsure why Aida64 shows unknown motherboard

KeY0Ke -- [email protected] 1.093V---BIOS 1.10---Stressapptest---1 Hour--F4-3200C14Q-32GTZRX


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## tekjunkie28

I have gotten stable 3333mhz stilts fast timings. Now I'm just dialing in the voltages and going to save the profile before trying for 3400 or 3466Mhz.

I have found that anything other 1.4volts on the ram leads to more errors. This is on a Giagabyte x470 gaming 5. Is it a mobo issue or a ryzen issue? 

Sent from my SM-N950U using Tapatalk


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## CJMitsuki

tekjunkie28 said:


> I have gotten stable 3333mhz stilts fast timings. Now I'm just dialing in the voltages and going to save the profile before trying for 3400 or 3466Mhz.
> 
> I have found that anything other 1.4volts on the ram leads to more errors. This is on a Giagabyte x470 gaming 5. Is it a mobo issue or a ryzen issue?
> 
> Sent from my SM-N950U using Tapatalk


It’s not really an issue honestly. Only the amount of voltage that is needed to run a certain strap should be applied. That goes for any voltage that pertains to memory. Overvolting any of them can cause errors and unwanted behavior in other settings. While you can possibly stabilize these adverse effects with other settings it can cause more problems ultimately leading to max overclocking potential being lowered due to more voltage than necessary being applied and using stability settings to compensate and running out of safe voltage on higher frequencies. Too many people solve stability issues by simply hammering it with more DRAM or SoC voltage and don’t look for other sources of the instabilities first. Which can be attributed to the lower frequencies they will attain later on. I have no doubt that these methods also cause many of the “cold boot issues” you see many complaining about and blame it all on the board or memory when 99% of it is their settings and can be fixed with some patience and testing. I can run 3600mhz with 1.4v and 1.05 SoC voltage because those 2 main voltages is the last place I look for stability when overclocking. You have Cad_Bus, Proc ODT, PLL, VPP_MEM, CLDO VDDP, among several other secondary voltages and settings you can turn to for stability before using your main voltages. Once you hit 1.5v or 1.2v SoC you will run out of that safe range to go any higher once bios updates permit us to go.


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## encrypted11

3600 with 5000% HCI or 2H GSAT or the Karhu Ram Test equivalent or at least with Silent Scone's lower limit met?

This is a 24/7 memory stability thread than a benchmark thread and Techpowerup Memtest64 (from what I'm noticing in post history) isn't an accepted test.


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## encrypted11

Also, some of Raja's previous comments in comparing memory testers.


Spoiler


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## CJMitsuki

encrypted11 said:


> 3600 with 5000% HCI or 2H GSAT or the Karhu Ram Test equivalent or at least with Silent Scone's lower limit met?
> 
> This is a 24/7 memory stability thread than a benchmark thread and Techpowerup Memtest64 (from what I'm noticing in post history) isn't an accepted test.


Honestly I trust HCI more than RamTest even though RamTest is nice and all. I don’t 100% trust any memory program that runs inside the OS though. Before I’m confident my memory is clean I run MemTest 6.0 Deluxe (Included with HCI Deluxe version) to 1000% outside of OS. About 10 hours with 16gb ram. It test 15.93gb of my 16gb so I feel more confident about that than anything. But for inside the OS either of those 2 are fine but I prefer HCI memtest if I had to choose just one although I do run both. What is the preferred file sharing site? I can see if I’m able to share the bootable MemTest Deluxe with everyone that doesn’t have it so they can burn it to a disc and use it if they wish.


----------



## encrypted11

CJMitsuki said:


> Honestly I trust HCI more than RamTest even though RamTest is nice and all. I don’t 100% trust any memory program that runs inside the OS though. Before I’m confident my memory is clean I run MemTest 6.0 Deluxe (Included with HCI Deluxe version) to 1000% outside of OS. About 10 hours with 16gb ram. It test 15.93gb of my 16gb so I feel more confident about that than anything. But for inside the OS either of those 2 are fine but I prefer HCI memtest if I had to choose just one although I do run both. What is the preferred file sharing site? I can see if I’m able to share the bootable MemTest Deluxe with everyone that doesn’t have it so they can burn it to a disc and use it if they wish.



An in-OS memory tester is required for a measurement of OS level stability.

And there's about no reason not to back up disk data prior to a memory overclock, restoring them after the overclock was deemed stable. A relevant post from [email protected]

https://rog.asus.com/forum/showthre...ternative-for-memory-testing/page2#post603650



[email protected] said:


> Exactly. Memtest86 is not good for gauging OS level stability (that's what "as good", which was the original question, means to me). That's what we've found, so when a user is asking about stable memory, or stability in general, we steer them towards the tests that have proven to get us closer to having a stable system. At least two of us that have more than a basic grasp of memory systems have found Memtest86 insufficient for the task, and personally would only use it if we need to confirm a memory module has severely degraded (in truth you don't even need to use it for that, as you can work that stuff out without it).
> 
> 
> And if we are getting into confusion of apples and oranges (semantics), let's not forget what your post here was alluding to: https://rog.asus.com/forum/showthrea...l=1#post603496
> 
> It too was comparing the implied memory, and hence OS level stability, between these tests. Nothing more, nothing less. Based on the contents of that post, I'd say the apples and oranges confusion that you implied later, has nothing to do with it - the answer you were seeking was a comparison in stress-test ability for stability. For that, one needs to understand the nature of IO, noise margins, references, overshoot, and a manner of other subjects before understanding why concurrent loads and random data patterns can trip up a system. Would advise reading up on these subjects or taking up further education if you have a real interest in the topics; otherwise, it will always remain a mystery.
> 
> Alternatively, compare these tests for yourself. You don't need a deep understanding of things to do that. Nobody needs Praz's or my permission to download something and try it. That's how one learns. Too much talking on forums and not enough doing is what creates most of these "debates", anyway.
> 
> Many of us that do this a LOT have found the two tests we recommend to be very effective. It isn't blind advice. Plus, one doesn't need to rely on Memtest86 to work out if DRAM is degrading, so I don't see the need for us to push it as an absolute priority in any way and least of all from an outright stability perspective.
> 
> No stress test programmer would ever claim a given test to be an absolute because the nature of instability manifests in many different ways. The rest comes down to experienced users testing things and finding consistently better results. When we find tests that work well, we go through them in a methodical manner to tune our systems (I test my memory overclocks with GSAT first, then HCI, then on to other parts of the system). Unfortunately, Memtest86 hasn't proven useful to us for anything we cannot do with other tests really (and better in relevant ways), so we don't push it as a "good alternative". Nor will we until it does.


There are also similar quotes from Praz on the subject matter.


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## CJMitsuki

encrypted11 said:


> An in-OS memory tester is required for a measurement of OS level stability.
> 
> And there's about no reason not to back up disk data prior to a memory overclock, restoring them after the overclock was deemed stable. A relevant post from [email protected]
> 
> https://rog.asus.com/forum/showthre...ternative-for-memory-testing/page2#post603650
> 
> 
> 
> There are also similar quotes from Praz on the subject matter.


I agree with him on his view of MemTest86, its good use is to find out more accurately what the errors are doing. For instance, say you have memory that you cant get stable for whatever reason you can run MemTest86 and see if the same bits are causing errors. If they are then that could be associated with hardware failure leading you to check dimm slots for debris or other problems. I actually had a problem like that and the exact same bits were causing errors in every single error on MemTest86 and after some research it was suggested that hardware problems can cause that so I started checking the motherboard visually and the dimm slots then finally the dimm contacts and noticed a couple seemed tarnished so I carefully took alcohol and wiped all contacts down then left a fair amount of alcohol on the contacts and inserted and removed them multiple times into the slots to try and clean them as best as I could. Upon rebooting and testing further my memory problems were gone so MemTest is not completely irrelevant in memory testing as most memory testers dont show you information on the errors as detailed as MemTest86 does. As far as stressing memory, sure it isnt my first choice but it doesnt hurt to run something to test the entire memory while you are out working or school or whatever the reason. There is a better alternative than MemTest86 though. I always just pop in the bootable disc and let it run while im at work and when I get home see the results. Plus I like the benchmark that MemTest Deluxe includes to show you if your overclock has made your system any faster than the last time you ran it with different settings. When it comes to testing memory the more, the merrier. I run every one of them I trust, inside the OS and out, no reason not to.

"An in-OS memory tester is required for a measurement of OS level stability."

Agreed, they all shoulkd be ran. The onlt reason I dont trust them 100% is that its impossible for them to test all of the ram so that leaves around 10-15% of possibility even though 99 times out of 100 there will not be an error hiding in that small percentage. Its still a good idea while you are away to boot up outside of OS and run something for that added peace of mind, at least for me it is.


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## mtrai

Gonna call this memory speed and timings stable. 3576 with tight timings. This is the kit G.SKILL TridentZ RGB Series 16GB (2 x 8GB) 288-Pin DDR4 4133MHz (PC4 33000) Desktop Memory Model F4-4133C19D-16GTZR 13 hours and some minutes or 2091 loops. Good enough for me.


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## tekjunkie28

How's the best way to determine if your IMC is any goo?. I still got 1 error after 2200% on HCI at stilts fast timing 1.37V (that's the manualsetting, bios reports it at 1.8v for some stupid reason.) 

Also according to thaiphoon burner my ram is 350ns for the tRFC timing as opposed to the dram timing calculator v1 and v2 profiles which both list 260ns. Is this odd?

Sent from my SM-N950U using Tapatalk


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## allikat

This is a threadnought, and searching for AMD is not gonna help.... but does the "Designed for AMD" on a memory set make any difference? If it looks like B-die, times like B-die, will it make any difference if it's on a stick that comes in a package with the AMD logo? Or is B-die from (for example) GSkill gonna be the same as any other B-die from Gskill? Outside the usual manufacturer binning and so on...


----------



## nexxusty

allikat said:


> This is a threadnought, and searching for AMD is not gonna help.... but does the "Designed for AMD" on a memory set make any difference? If it looks like B-die, times like B-die, will it make any difference if it's on a stick that comes in a package with the AMD logo? Or is B-die from (for example) GSkill gonna be the same as any other B-die from Gskill? Outside the usual manufacturer binning and so on...


Not really no. The difference lies in the tiers of kits.

Example being..... Trident Z will almost always have better binned B-Die than Ripjaws V. Found this out the hard way when I figured B-Die was B-Die and bought a set of Ripjaws V.

Not the case. The Ripjaws I had did do the timings of other peoples B-Die, however only at higher voltages. With active cooling it was never an issue.

YMMV on that, however you can *usually* pull off timings anyone else has with any set of B-Die as long as your IMC is up to the task and you don't mind doing 1.4v+.


----------



## CJMitsuki

nexxusty said:


> allikat said:
> 
> 
> 
> This is a threadnought, and searching for AMD is not gonna help.... but does the "Designed for AMD" on a memory set make any difference? If it looks like B-die, times like B-die, will it make any difference if it's on a stick that comes in a package with the AMD logo? Or is B-die from (for example) GSkill gonna be the same as any other B-die from Gskill? Outside the usual manufacturer binning and so on...
> 
> 
> 
> Not really no. The difference lies in the tiers of kits.
> 
> Example being..... Trident Z will almost always have better binned B-Die than Ripjaws V. Found this out the hard way when I figured B-Die was B-Die and bought a set of Ripjaws V.
> 
> Not the case. The Ripjaws I had did do the timings of other peoples B-Die, however only at higher voltages. With active cooling it was never an issue.
> 
> YMMV on that, however you can *usually* pull off timings anyone else has with any set of B-Die as long as your IMC is up to the task and you don't mind doing 1.4v+.
Click to expand...

You need to look at the rates timings to gather the binning quality. For instance the best binned BDie kits are 3200c14 and 3600c15 and those two will pretty much always cost more than the rest due to the low Cas latency associated relative to the speeds. 3600c16 has several different binned dies. I think there is a Hynix and 2 different types of Bdies one being inferior to the other. I’m not positive but I think the model number ends with an A and a B such as F4-3600c16d-16GVKA and GVKB. I’ll have to check this and confirm on the model number types but I do know that bin is one to research thoroughly before buying. Personally I wouldn’t take anything less than 3200c14 or the 3600c15 kits as they overclock nicely. Single rank 1DPC of course but I have no use for more than 16gb and it gives the best overclocking frequencies. You struggle a bit more with dual rank and 32gb 2dpc setups a bit more and they click a bit lower due to the added stress to the IMC.


----------



## allikat

CJMitsuki said:


> You need to look at the rates timings to gather the binning quality. For instance the best binned BDie kits are 3200c14 and 3600c15 and those two will pretty much always cost more than the rest due to the low Cas latency associated relative to the speeds. 3600c16 has several different binned dies. I think there is a Hynix and 2 different types of Bdies one being inferior to the other. I’m not positive but I think the model number ends with an A and a B such as F4-3600c16d-16GVKA and GVKB. I’ll have to check this and confirm on the model number types but I do know that bin is one to research thoroughly before buying. Personally I wouldn’t take anything less than 3200c14 or the 3600c15 kits as they overclock nicely. Single rank 1DPC of course but I have no use for more than 16gb and it gives the best overclocking frequencies. You struggle a bit more with dual rank and 32gb 2dpc setups a bit more and they click a bit lower due to the added stress to the IMC.


I'm looking at https://www.gskill.com/en/product/f4-3600c16d-16gtzr , https://www.gskill.com/en/product/f4-3200c14d-16gtzrx and https://www.gskill.com/en/product/f4-3200c14d-16gtzr . All 16GB kits that show up in various B-die searches and match all the "how to find b-die" articles.


----------



## CJMitsuki

allikat said:


> CJMitsuki said:
> 
> 
> 
> You need to look at the rates timings to gather the binning quality. For instance the best binned BDie kits are 3200c14 and 3600c15 and those two will pretty much always cost more than the rest due to the low Cas latency associated relative to the speeds. 3600c16 has several different binned dies. I think there is a Hynix and 2 different types of Bdies one being inferior to the other. I’m not positive but I think the model number ends with an A and a B such as F4-3600c16d-16GVKA and GVKB. I’ll have to check this and confirm on the model number types but I do know that bin is one to research thoroughly before buying. Personally I wouldn’t take anything less than 3200c14 or the 3600c15 kits as they overclock nicely. Single rank 1DPC of course but I have no use for more than 16gb and it gives the best overclocking frequencies. You struggle a bit more with dual rank and 32gb 2dpc setups a bit more and they click a bit lower due to the added stress to the IMC.
> 
> 
> 
> I'm looking at https://www.gskill.com/en/product/f4-3600c16d-16gtzr , https://www.gskill.com/en/product/f4-3200c14d-16gtzrx and https://www.gskill.com/en/product/f4-3200c14d-16gtzr . All 16GB kits that show up in various B-die searches and match all the "how to find b-die" articles.
Click to expand...

Both of the 3200c14 kits look good but don’t download the rgb controller for them and try to refrain from using rgb software on any rgb ram as it goes through the SPD and has been known to corrupt the chip. I have the 16gtzr kit and have had it for a year and a half and I have it overclocked to 3533 Cas 14 with super tightened timings and it’s runs at 58ns latency on my 2700x. I couldn’t have asked for a better kit.


----------



## S4ch4Z

That took a lot of trial and error work, but there, finally stable at 3466 14-14-14-28-42 (1.42V, 1.05V SOC)



















Thanks to everyone involved here, your guidance is much appreciated


----------



## H-man

https://i.imgur.com/ummvjIz.png 
[email protected] 1.025v---ASUS Prime B350-Plus --BIOS 0806---Stressapptest---1 Hour--2x M391A2K43BB1-CPB
2933 14-16-16-16-32-52 1T 1.35V DDR, 1.025V SOC
32GB of ECC M391A2K43BB1-CPB on an ASUS Prime B350-plus.
No tweaking, just used ryzen DRAM Calculator 1.2.0 beta2. My board doesn't seem to want to go too much higher and I'm not sure how to do so, the ryzen timing calc's timings don't work too well past this speed. Not bad for a $230 kit on a sub $200 CPU+board combo though. I'm aware that ECC can mask marginal timings so I checked the event log for WHEA and there are no events detected there.


----------



## larrydavid

H-man said:


> https://i.imgur.com/ummvjIz.png
> [email protected] 1.025v---ASUS Prime B350-Plus --BIOS 0806---Stressapptest---1 Hour--2x M391A2K43BB1-CPB
> 2933 14-16-16-16-32-52 1T 1.35V DDR, 1.025V SOC
> 32GB of ECC M391A2K43BB1-CPB on an ASUS Prime B350-plus.
> No tweaking, just used ryzen DRAM Calculator 1.2.0 beta2. My board doesn't seem to want to go too much higher and I'm not sure how to do so, the ryzen timing calc's timings don't work too well past this speed. Not bad for a $230 kit on a sub $200 CPU+board combo though. I'm aware that ECC can mask marginal timings so I checked the event log for WHEA and there are no events detected there.


How'd you find the ram so cheap?


----------



## H-man

larrydavid said:


> How'd you find the ram so cheap?


I was looking in the right place at the right time (AKA I waited months). I also have a 2x8GB modules that I paid $110 for thanks to fry's doing a closeout (currently moping in my parts box because it's A die micron and not ECC). Had to use the 2x8GB while I was waiting.


----------



## datspike

Hmm. Cant stabilize 3600 no matter what. I've successfully got the karhu ramtest to 7k%, reboot, errors at 7-200%. After another reboot it can became stable again. 
Seems like memory training instability. 
Have anyone of you guys encountered that? 
I have fast boot disabled.


----------



## tekjunkie28

datspike said:


> Hmm. Cant stabilize 3600 no matter what. I've successfully got the karhu ramtest to 7k%, reboot, errors at 7-200%. After another reboot it can became stable again.
> Seems like memory training instability.
> Have anyone of you guys encountered that?
> I have fast boot disabled.


Yes. I'm not sure what the problem actually is but I think I may have to do with leaving subtiming on auto. I was unstable like that for everything except for the stilts 3333mhz safe and modified fast timings. I'm not stable at 3400mhz or 3466mhz. Idk if it's my ram or my cpu which is unstable.

Sent from my SM-N950U using Tapatalk


----------



## CJMitsuki

datspike said:


> Hmm. Cant stabilize 3600 no matter what. I've successfully got the karhu ramtest to 7k%, reboot, errors at 7-200%. After another reboot it can became stable again.
> Seems like memory training instability.
> Have anyone of you guys encountered that?
> I have fast boot disabled.



3600 strap is just very iffy with Ryzen right now. I gave up on 3600 and found a much better avenue by dropping to 3400 and taking voltage to 1.57v then dropping to 12-12-12-26 and it runs circles around 3600c14 with gear down disabled at 1T. Running 2010+ points in Cinebench consistently at 4.3ghz and around 2055 at 4.4ghz. The response of my system at those timings are like night and day compared to anything at c14, buttery smooth. I am going to try 3200c10 soon and see how that responds. Also when i dropped to c12 my latency at 4.3ghz was 57ns :sonic:


----------



## Trender

Guys any help?

With the Calculator (ryzen 2700x and ofc chose zen+) I did input all the settings and got 2 mins in Karhu RAM Test. 
One setting it said 53 OHms but it always worked better for me 43.6 so I changed it and ofc tried all the ohms. 
So with calculator settigns that are for 53 but using 43 OHms instead I get 6 mins on RAM Test.
But it still isn't stable @3600, can I get any help? The calculator says 53 OHms but I get much more stable with 43 OHms, what else should I change?
My RAMS 16 gb Samsung b die @ 3600


----------



## CJMitsuki

Trender said:


> Guys any help?
> 
> With the Calculator (ryzen 2700x and ofc chose zen+) I did input all the settings and got 2 mins in Karhu RAM Test.
> One setting it said 53 OHms but it always worked better for me 43.6 so I changed it and ofc tried all the ohms.
> So with calculator settigns that are for 53 but using 43 OHms instead I get 6 mins on RAM Test.
> But it still isn't stable @3600, can I get any help? The calculator says 53 OHms but I get much more stable with 43 OHms, what else should I change?
> My RAMS 16 gb Samsung b die @ 3600


3600 is very difficult to stabilize and you won’t get much, if any, benefit over 3533 so if I were you I would drop back to 3533 and optimize timings for best performance. Even 3466 at tightened timings will outperform 3600 with loose timings and won’t cause you frustrations as 3600 will right now.


----------



## drkCrix

Question regarding DDR voltage vs SoC voltage. Does it matter when trying to stabilize the system if you prioritize a lower SoC voltage vs a higher DDR voltage?

Right now I am stable at 14-14-14-30-52 1t @ 3333 with 1.1v SoC and 1.37v DDR.

Previous I had it running at the same speed but with 1.05v SoC and 1.4v DDR.

Does it really make a difference or should I call it stable and a) leave it or b) try for 3466

Cheers,

Chris


----------



## tempos14

Hey there,


i got some problems to get my Ryzen setup stable (cold boot bug as well). I tried a lot of different settings, but nothing worked fine. 



Specs:


Ryzen 2700
G.Skill Trident Z 3600er CL16
ASUS x470-i Strix
Corsair SF450
DanCase A4





    


Here are the different settings i tried:





Do you have any ideas to get the system stable? If you need further information, fell free to ask .



Greets from germany,
tempos14


----------



## CJMitsuki

tempos14 said:


> Hey there,
> 
> 
> i got some problems to get my Ryzen setup stable (cold boot bug as well). I tried a lot of different settings, but nothing worked fine.
> 
> 
> 
> Specs:
> 
> 
> Ryzen 2700
> G.Skill Trident Z 3600er CL16
> ASUS x470-i Strix
> Corsair SF450
> DanCase A4
> 
> 
> 
> 
> 
> 
> 
> 
> Here are the different settings i tried:
> 
> 
> 
> 
> 
> Do you have any ideas to get the system stable? If you need further information, fell free to ask /forum/images/smilies/smile.gif.
> 
> 
> 
> Greets from germany,
> tempos14


Honestly I would drop down away from 3600mhz. Even on B Die it is difficult to get stable and requires very specific settings that differ per set. It is a very frustrating strap. You need to start 3200 and get it stable then work your way up. More than likely between 3400 and 3533 is where you will find the best performance for your kit. I would try 3200 at 14-14-14-30-44 as a baseline start. Just work your way up from there, trying to stay at Cas 14 and see how high you can push your frequency. Don’t even worry about 3600. As for cold boot issues, Cad Bus and Proc ODT setting work best but many other things can help. Also, every once in awhile try lowering SoC. I’ve found that I get more errors above 1.1v SoC and right now mine is 1.068 and will be wrrors above that on 3600. But if you can get 3533c14 working or even 3400-3466c14 then you’ll find they offer great performance as well.


----------



## tempos14

Yesterday I tried 3200 CL16 1T, VCore & SoC Auto (~1,057 VCore, 1,138 SoC), LLC3, GDM & PDM on, ProcODT 60 Ohm, VDDCR CPU Power Duty Control Extreme.

Failed (reboot) after three hours of Aida64. 

On the next step i will lowering the SoC Voltage to 1,05/1,075/1,1V, change ProcODT to 68,6 Ohm. Wish me luck .


----------



## tempos14

No chance to get 3200 CL16 stable, I tried a lot of different settings:

VDimm from 1,3 to 1,4V
SoC Voltage from 1,05 to 1,1V
ProcODT from 48 to 68,6 Ohm

The longest run on Aida64 was about 5 hours. 

If nothing works, goodbye Ryzen .


----------



## poporange630

I've been trying to fiddle with 2700X and B-die RAM for a few weeks now. Can't get anything Stable above 3266MHZ.
I do get good timing though... please see image attached: https://imgur.com/a/3qRzaL0


I've so far tried to loose the timing, DRAM voltage to 1.46V, SOC to 1.1V and use Ryzen DRAM calculator, etc, just can't get it 100% stable without AIDA64 or MEMTEST64 error.

Any idea would be much appriciated!


----------



## mtrai

@CJMitsuki I had a thought last night..well a dream lol about ram overclocking. I have not had time to test this but MAYBE, just MAYBE has anyone looked to the CPU Core voltage needed to run the ram at 3600 and higher. The reason this thought came to me is due to the fact as we push our ram speed higher we are also pushing the cpu internal Infinty Fabric speeds fast. Ram clock speed equals Infinity Fabric speed. This in addition to all the other voltages we need to look at?

Thoughts?


----------



## tempos14

poporange630 said:


> I've been trying to fiddle with 2700X and B-die RAM for a few weeks now. Can't get anything Stable above 3266MHZ.
> I do get good timing though... please see image attached: https://imgur.com/a/3qRzaL0
> 
> 
> I've so far tried to loose the timing, DRAM voltage to 1.46V, SOC to 1.1V and use Ryzen DRAM calculator, etc, just can't get it 100% stable without AIDA64 or MEMTEST64 error.
> 
> Any idea would be much appriciated!


Same here. No chance to get 3600/3200/2866 MHz stable. I did a cmos reset and tried do get 3200 CL16 stable. Just set some settings in the bios manually, the rest on auto:

3200 MHZ, CL 16, 1T
VCore Offset - 0,375 V
Soc 1,0875 V
ProcODT 60 Ohm
Vdimm 1,375 V


EDIT: SoC 1,0875 V (WIN 1,075V) BSOD after 10 min, SoC 1,1 V (WIN 1,0875) still running (30min). Stay tuned


----------



## CJMitsuki

mtrai said:


> @CJMitsuki I had a thought last night..well a dream lol about ram overclocking. I have not had time to test this but MAYBE, just MAYBE has anyone looked to the CPU Core voltage needed to run the ram at 3600 and higher. The reason this thought came to me is due to the fact as we push our ram speed higher we are also pushing the cpu internal Infinty Fabric speeds fast. Ram clock speed equals Infinity Fabric speed. This in addition to all the other voltages we need to look at?
> 
> Thoughts?


I have tested that and the voltage itself doesn’t have much to do with the ram stability but if the cpu is hungry for more voltage and hasn’t received enough for that frequency to be able to have peak performance then that can cause instability in the ram it seems as the cpu itself isn’t stable 100% therefore affecting the IMC as well. Now, other voltages relating to cpu definitely have some effect. What I found is that Cad_Bus, Rtt Park, and Proc ODT are the biggest factors for stability at high frequency. I suppose the added resistance helps calm the erratic behavior. I’m pretty much stable at 3600 now but if my Dimms get near 40c then I need to loosen tRAS and tRFC a bit to compensate. I’m running 30-30-40-40ohm, disabled, disabled, 60ohm Rtt Park, and still sitting with 53.3 ohm Proc ODT as it didn’t offer much for me with my timings. I’m able to run 14-14-14-28-42 and when my dimms are high 30c range(37c+) then it’s 30-44. tRFC is 380 and 425 respectively. There may be a stray error here or there as I don’t care to test it for hours but the performance is ridiculous. Cpu response is crazy and I can tell it’s much stronger than 3533 setup I had. I can almost reach the HWBoT x265 time above mine but I need to optimize some more things in the OS and reinstall tonight. Also need a much better gpu even though my 1060 is running great for a 1060. It runs 2100mhz core and 9.7ghz memory. Just can’t compete with 1080s or rx580s and up. If I could unlock the voltage then I’m sure I could put some good numbers up but Nvidia has it locked up tight. I think I’m going to go with AMD gpus for that reason. Nvidias practices leave a sour taste for me. Not a fan of their business model.


----------



## mtrai

CJMitsuki said:


> I have tested that and the voltage itself doesn’t have much to do with the ram stability but if the cpu is hungry for more voltage and hasn’t received enough for that frequency to be able to have peak performance then that can cause instability in the ram it seems as the cpu itself isn’t stable 100% therefore affecting the IMC as well. Now, other voltages relating to cpu definitely have some effect. What I found is that Cad_Bus, Rtt Park, and Proc ODT are the biggest factors for stability at high frequency. I suppose the added resistance helps calm the erratic behavior. I’m pretty much stable at 3600 now but if my Dimms get near 40c then I need to loosen tRAS and tRFC a bit to compensate. I’m running 30-30-40-40ohm, disabled, disabled, 60ohm Rtt Park, and still sitting with 53.3 ohm Proc ODT as it didn’t offer much for me with my timings. I’m able to run 14-14-14-28-42 and when my dimms are high 30c range(37c+) then it’s 30-44. tRFC is 380 and 425 respectively. There may be a stray error here or there as I don’t care to test it for hours but the performance is ridiculous. Cpu response is crazy and I can tell it’s much stronger than 3533 setup I had. I can almost reach the HWBoT x265 time above mine but I need to optimize some more things in the OS and reinstall tonight. Also need a much better gpu even though my 1060 is running great for a 1060. It runs 2100mhz core and 9.7ghz memory. Just can’t compete with 1080s or rx580s and up. If I could unlock the voltage then I’m sure I could put some good numbers up but Nvidia has it locked up tight. I think I’m going to go with AMD gpus for that reason. Nvidias practices leave a sour taste for me. Not a fan of their business model.


Wow that are some crazy dram temps. Mine hardly ever get above 36 degrees cel. Now I need to figure out why I am not hitting higher performance in some of those benchmarks. And also trying to figure out why I am able to sustain 1700 to 1715 core on my new vega 64 in timespy but not in firestrike.


----------



## CJMitsuki

mtrai said:


> CJMitsuki said:
> 
> 
> 
> I have tested that and the voltage itself doesn’t have much to do with the ram stability but if the cpu is hungry for more voltage and hasn’t received enough for that frequency to be able to have peak performance then that can cause instability in the ram it seems as the cpu itself isn’t stable 100% therefore affecting the IMC as well. Now, other voltages relating to cpu definitely have some effect. What I found is that Cad_Bus, Rtt Park, and Proc ODT are the biggest factors for stability at high frequency. I suppose the added resistance helps calm the erratic behavior. I’m pretty much stable at 3600 now but if my Dimms get near 40c then I need to loosen tRAS and tRFC a bit to compensate. I’m running 30-30-40-40ohm, disabled, disabled, 60ohm Rtt Park, and still sitting with 53.3 ohm Proc ODT as it didn’t offer much for me with my timings. I’m able to run 14-14-14-28-42 and when my dimms are high 30c range(37c+) then it’s 30-44. tRFC is 380 and 425 respectively. There may be a stray error here or there as I don’t care to test it for hours but the performance is ridiculous. Cpu response is crazy and I can tell it’s much stronger than 3533 setup I had. I can almost reach the HWBoT x265 time above mine but I need to optimize some more things in the OS and reinstall tonight. Also need a much better gpu even though my 1060 is running great for a 1060. It runs 2100mhz core and 9.7ghz memory. Just can’t compete with 1080s or rx580s and up. If I could unlock the voltage then I’m sure I could put some good numbers up but Nvidia has it locked up tight. I think I’m going to go with AMD gpus for that reason. Nvidias practices leave a sour taste for me. Not a fan of their business model.
> 
> 
> 
> Wow that are some crazy dram temps. Mine hardly ever get above 36 degrees cel. Now I need to figure out why I am not hitting higher performance in some of those benchmarks. And also trying to figure out why I am able to sustain 1700 to 1715 core on my new vega 64 in timespy but not in firestrike.
Click to expand...

Only time my dimms get higher than 35 is when my AC is off and house warms to 75f+ bc I forget to turn it back on. If I have AC cranked up then they run about 25c maybe 28c. Cpu will drop to around 15c since water temps are nice and cool. 
Fire strike uses DX11 and Timespy uses DX12 so maybe that could be a factor? I’m not too keen on GPU overclocking behavior. I may attempt voltage mod on my 1060 soon. I have a 970 as a backup just in case and I can unlock it.


----------



## mtrai

CJMitsuki said:


> Only time my dimms get higher than 35 is when my AC is off and house warms to 75f+ bc I forget to turn it back on. If I have AC cranked up then they run about 25c maybe 28c. Cpu will drop to around 15c since water temps are nice and cool.
> Fire strike uses DX11 and Timespy uses DX12 so maybe that could be a factor? I’m not too keen on GPU overclocking behavior. I may attempt voltage mod on my 1060 soon. I have a 970 as a backup just in case and I can unlock it.


My 2 x RX 580 I overclocked via the bios with all my own working settings and modified mem straps...Vega 64 is just a new beast to work with. That makes more sense on those dram temps. That is what I chalked it up to...DX11 vs DX12. My comparsions was actually WoW BFA beta. I noticed when I used DX12 it would need more gpu core then on the DX11 settings.

THe only issue I have at 3600 is sometimes 1 f9 and then post correctly or total ram training failure. Like we used to get way back with getting 3200 to run correctly.


----------



## jinsk8r

Hi, im new to this. Currently i don't OC the memory but these errors are there, what do I do? My memory is Galax (KFA2) HOF 3600 8gbx2 samsung b-die setting at 2133 C17 (default no XMP).
Thank you!


----------



## CJMitsuki

jinsk8r said:


> Hi, im new to this. Currently i don't OC the memory but these errors are there, what do I do? My memory is Galax (KFA2) HOF 3600 8gbx2 samsung b-die setting at 2133 C17 (default no XMP).
> Thank you!


Those aren’t memory errors. Some conflict is causing those threads to crash in that program it seems. Go check the event logs and see what’s causing the conflict


----------



## jinsk8r

CJMitsuki said:


> Those aren’t memory errors. Some conflict is causing those threads to crash in that program it seems. Go check the event logs and see what’s causing the conflict


There is no event at the time these errors occured. This is the first time I use this software, I think I just stick to MemTest and manually launch 16 instances everytime I want to check my memory


----------



## CJMitsuki

jinsk8r said:


> CJMitsuki said:
> 
> 
> 
> Those aren’t memory errors. Some conflict is causing those threads to crash in that program it seems. Go check the event logs and see what’s causing the conflict
> 
> 
> 
> There is no event at the time these errors occured. This is the first time I use this software, I think I just stick to MemTest and manually launch 16 instances everytime I want to check my memory /forum/images/smilies/frown.gif
Click to expand...

You can always make a batch file that launches 16 instances with a click and inputs the value as well as starts them all for you.


----------



## jinsk8r

CJMitsuki said:


> You can always make a batch file that launches 16 instances with a click and inputs the value as well as starts them all for you.


I don't know any of these command lines. Can you share the file with me so I can modify it to run in my system? Thank you! :thumb:


----------



## CJMitsuki

jinsk8r said:


> CJMitsuki said:
> 
> 
> 
> You can always make a batch file that launches 16 instances with a click and inputs the value as well as starts them all for you.
> 
> 
> 
> I don't know any of these command lines. Can you share the file with me so I can modify it to run in my system? Thank you! /forum/images/smilies/thumb.gif
Click to expand...

Yes, I’m going to make a thread with a tutorial on how to create a batch file for MemTest this evening.


----------



## jinsk8r

I'm a newbie please help.
Finally I managed to make my kit run at 3600c16 but it's totally unstable.

MB: Asrock X370 Taichi
Bios: 3.20 (I tried 4.60 but it's too bad I needed to roll back to 3.20)
CPU: Ryzen 1700
Ram: Galax HOF 3600 8GBx2 Kit in A2 B2 slots
Cooler: Corsair H100i V2 fan Perf

Ram Overclocking:
I used BIOS 3.20 back then and overclocked my kit to [email protected] and it worked well (never tested with software because I didn't know).
Then later I updated BIOS to 4.60 but they changed many things (Removed C-State option etc) and I couldnt overclock my ram (harder than before, and sometimes it just didnt let me overclock both CPU and ram)
Now I rolled back to 3.20 and managed to OC my kit to [email protected], loaded Windows but there are BSOD sometimes so I raised the dram voltage, but I still think it will not last the stress test.

My voltage:
CPU LLC lv3
VSOC LLC lv2
Dram: 1.46 (Windows load 1.496)
Vsoc: 1.106
Vtt DDR: 0.7
VDDP: 0.85

My timings I set as this preset (the setting in red DQS str I can't find it in my BIOS):









SO HERE ARE MY QUESTIONs:
- What do I do now to make my kit stable (maybe to reduce voltage as well)?
- When I test using Mem Test or Ram Test, what do I do if errors occur? (Changing which timings, reducing voltage..etc?)

Thank you!



Optional question:

CPU Overclocking:
CPU 3.8GHZ with fixed Vcore of 1.2125V (1.206 when load in Windows), CPU LLC Level 2, SOC LLC Level 2. "C6" disabled also "c-state" are disabled. Temp is 40c idle and 72c Prime95 Small (Ambient 28c). I feel this temp is a little too hight, isn't it?


----------



## tempos14

Check the CLDO_vDDP voltage and set it to 950. This was the only chance to get my system stable to 3200CL14. Still testing. See my initial post one or two pages before.

Actual settings of my rig:

Ryzen 2700
G.Skill TridentZ 3600/CL16
ASUS X470-i

VCore offset -0.375 V (Win 1.057 V) 
LLC3
VSoc 1.0375 V (Win 1.0313 V)
LLC3
ProcODT 53,3 ohm
CLDO_vDDP 950 mV
VRam 1.375 V (maybe 1,35 V is possible)


----------



## CJMitsuki

jinsk8r said:


> I'm a newbie please help.
> Finally I managed to make my kit run at 3600c16 but it's totally unstable.
> 
> MB: Asrock X370 Taichi
> Bios: 3.20 (I tried 4.60 but it's too bad I needed to roll back to 3.20)
> CPU: Ryzen 1700
> Ram: Galax HOF 3600 8GBx2 Kit in A2 B2 slots
> Cooler: Corsair H100i V2 fan Perf
> 
> Ram Overclocking:
> I used BIOS 3.20 back then and overclocked my kit to [email protected] and it worked well (never tested with software because I didn't know).
> Then later I updated BIOS to 4.60 but they changed many things (Removed C-State option etc) and I couldnt overclock my ram (harder than before, and sometimes it just didnt let me overclock both CPU and ram)
> Now I rolled back to 3.20 and managed to OC my kit to [email protected], loaded Windows but there are BSOD sometimes so I raised the dram voltage, but I still think it will not last the stress test.
> 
> My voltage:
> CPU LLC lv3
> VSOC LLC lv2
> Dram: 1.46 (Windows load 1.496)
> Vsoc: 1.106
> Vtt DDR: 0.7
> VDDP: 0.85
> 
> My timings I set as this preset (the setting in red DQS str I can't find it in my BIOS):
> 
> 
> 
> 
> 
> 
> 
> 
> 
> SO HERE ARE MY QUESTIONs:
> - What do I do now to make my kit stable (maybe to reduce voltage as well)?
> - When I test using Mem Test or Ram Test, what do I do if errors occur? (Changing which timings, reducing voltage..etc?)
> 
> Thank you!
> 
> 
> 
> Optional question:
> 
> CPU Overclocking:
> CPU 3.8GHZ with fixed Vcore of 1.2125V (1.206 when load in Windows), CPU LLC Level 2, SOC LLC Level 2. "C6" disabled also "c-state" are disabled. Temp is 40c idle and 72c Prime95 Small (Ambient 28c). I feel this temp is a little too hight, isn't it?


My advice is the same as before. Drop the 3600mhz setup and go for something easier to attain that has more performance. 3600c16 is around the same performance as 3333c14. 3400c14 or 3466c14 will run circles around 3600c16. If you are ever in doubt about a setup just go by this rough equation to determine if one setup has more potential than another. (MHz/Cas Latency=X) The higher the number found for X the better the potential performance of the setup. 3600c16 is not any better than 3333c14. Its probably worse. Higher speed on ram does not equate to more performance. Cas Latency is a determining factor. I can probably hit 3800 if I run at Cas18 but why? It would surely be horrible for performance. You are stressing your IMC for nothing. That time and energy would be better off spent on 3400 at Cas14 which shouldn’t be hard to attain. Even 3333mhz would be better with timings set correctly.


----------



## jinsk8r

CJMitsuki said:


> My advice is the same as before. Drop the 3600mhz setup and go for something easier to attain that has more performance. 3600c16 is around the same performance as 3333c14. 3400c14 or 3466c14 will run circles around 3600c16. If you are ever in doubt about a setup just go by this rough equation to determine if one setup has more potential than another. (MHz/Cas Latency=X) The higher the number found for X the better the potential performance of the setup. 3600c16 is not any better than 3333c14. Its probably worse. Higher speed on ram does not equate to more performance. Cas Latency is a determining factor. I can probably hit 3800 if I run at Cas18 but why? It would surely be horrible for performance. You are stressing your IMC for nothing. That time and energy would be better off spent on 3400 at Cas14 which shouldn’t be hard to attain. Even 3333mhz would be better with timings set correctly.


Overcoming those frustrations of cold boots, finally I got my kit running well in Windows.
I set these settings: Fast 3466C14









However when I use Mem Test it pops error after a few minutes and my PC blacks out (literally the screen turned black) and resets. Same issue when stress with Prime95 Blend.

What is my problem here and how to fix it? Thank you!

My Spec:


> MB: Asrock X370 Taichi
> Bios: 3.20 (I tried 4.60 but it's too bad I needed to roll back to 3.20)
> CPU: Ryzen 1700
> Ram: Galax HOF 3600 8GBx2 Kit in A2 B2 slots
> Cooler: Corsair H100i V2 fan Perf


My voltage:


> CPU LLC lv2
> VSOC LLC lv2
> Dram: 1.415 (Windows load 1.44)
> Vsoc: 1.05
> Vtt DDR: 0.7
> VDDP: 0.85


----------



## ssateneth

Go into device manager, go to your video card, right click, disable. Driver is crashing because it can't talk to the video card as fast as it wants to (memory test taking up all the bandwidth). I had this issue too when testing overnight. Disabling video card device for testing fixed it.


----------



## CJMitsuki

jinsk8r said:


> CJMitsuki said:
> 
> 
> 
> My advice is the same as before. Drop the 3600mhz setup and go for something easier to attain that has more performance. 3600c16 is around the same performance as 3333c14. 3400c14 or 3466c14 will run circles around 3600c16. If you are ever in doubt about a setup just go by this rough equation to determine if one setup has more potential than another. (MHz/Cas Latency=X) The higher the number found for X the better the potential performance of the setup. 3600c16 is not any better than 3333c14. Its probably worse. Higher speed on ram does not equate to more performance. Cas Latency is a determining factor. I can probably hit 3800 if I run at Cas18 but why? It would surely be horrible for performance. You are stressing your IMC for nothing. That time and energy would be better off spent on 3400 at Cas14 which shouldn’t be hard to attain. Even 3333mhz would be better with timings set correctly.
> 
> 
> 
> Overcoming those frustrations of cold boots, finally I got my kit running well in Windows.
> I set these settings: Fast 3466C14
> 
> 
> 
> 
> 
> 
> 
> 
> 
> However when I use Mem Test it pops error after a few minutes and my PC blacks out (literally the screen turned black) and resets. Same issue when stress with Prime95 Blend.
> 
> What is my problem here and how to fix it? Thank you!
> 
> My Spec:
> 
> 
> 
> MB: Asrock X370 Taichi
> Bios: 3.20 (I tried 4.60 but it's too bad I needed to roll back to 3.20)
> CPU: Ryzen 1700
> Ram: Galax HOF 3600 8GBx2 Kit in A2 B2 slots
> Cooler: Corsair H100i V2 fan Perf
> 
> Click to expand...
> 
> My voltage:
> 
> 
> 
> CPU LLC lv2
> VSOC LLC lv2
> Dram: 1.415 (Windows load 1.44)
> Vsoc: 1.05
> Vtt DDR: 0.7
> VDDP: 0.85
> 
> Click to expand...
Click to expand...

When you run MemTest how much are you allocating to each thread? I assume you have 16gb of memory and are running 16 instances of MemTest?


----------



## jinsk8r

CJMitsuki said:


> When you run MemTest how much are you allocating to each thread? I assume you have 16gb of memory and are running 16 instances of MemTest?


Yes 16 instances, 850mb each.


----------



## bitxan

what is the normal operating temperature for ddr4 3200 cl 14 when stability tests are performed with memtest hci? if I leave it running for 10 hours I can see with 56 ° laser thermometer


----------



## CJMitsuki

bitxan said:


> what is the normal operating temperature for ddr4 3200 cl 14 when stability tests are performed with memtest hci? if I leave it running for 10 hours I can see with 56 ° laser thermometer


Probably around 30c, you need to get better airflow to those sticks. Zip tie a fan to them. If you don’t youre going to damage them.


----------



## bitxan

to be damaged at 30 °, is it a joke? ddr4 supports up to 85 °, what I wanted to know is what temperature are getting at 3200cl14 speed since from 2933 to 3200 it goes up 4 °


----------



## Hequaqua

bitxan said:


> to be damaged at 30 °, is it a joke? ddr4 supports up to 85 °, what I wanted to know is what temperature are getting at 3200cl14 speed since from 2933 to 3200 it goes up 4 °


This is what I [email protected]:









Under HCI/GoogleStressApp maybe a bit higher. I think the highest I've seen is around 38-40°C.

Hope this helps....but yea, DDR4 can operate at pretty high temps.


----------



## bitxan

Hequaqua said:


> This is what I [email protected]:
> 
> View attachment 206372
> 
> 
> Under HCI/GoogleStressApp maybe a bit higher. I think the highest I've seen is around 38-40°C.
> 
> Hope this helps....but yea, DDR4 can operate at pretty high temps.





thanks for the answer, with ibt I go up to 40º maximum after 6 hours but with HCI memtest reaches 53º.
Greetings.


----------



## jinsk8r

Update: I still get cold boots on these settings but I tried to bump SOC voltage to 1.1v and ProcODT to 60ohm now I can test on Prime95 Blend, but it pops the Rounding error after a while.

I set these settings: Fast 3466C14









What is my problem here and how to fix it (stable test and cold boots)? Thank you!

My Spec:


> MB: Asrock X370 Taichi
> Bios: 3.20 (I tried 4.60 but it's too bad I needed to roll back to 3.20)
> CPU: Ryzen 1700
> Ram: Galax HOF 3600 8GBx2 Kit in A2 B2 slots
> Cooler: Corsair H100i V2 fan Perf


My voltage:


> CPU LLC lv2
> VSOC LLC lv2
> Dram: 1.415 (Windows load 1.44)
> Vsoc: 1.05
> Vtt DDR: 0.7
> VDDP: 0.85


----------



## tempos14

jinsk8r said:


> Update: I still get cold boots on these settings but I tried to bump SOC voltage to 1.1v and ProcODT to 60ohm now I can test on Prime95 Blend, but it pops the Rounding error after a while.
> 
> I set these settings: Fast 3466C14
> 
> 
> 
> 
> 
> 
> 
> 
> 
> What is my problem here and how to fix it (stable test and cold boots)? Thank you!
> 
> My Spec:
> 
> 
> My voltage:


Try ProcODT 53,3 ohm and CLDO_vDDP 950 mV. Have a look at tCDRD and tTCWR, you mixed CL14 & CL15.


----------



## Hequaqua

For those that have the HCI Pro Version, you can copy and paste this code below into Notepad, save is as filename.ps1. Put it in the pro folder. When you want to launch it, right-click it and open it with PowerShell. It should launch how ever many threads and memory you edit it to. It's the first 3 lines that determine that. I have mine at 12 threads w/1024mb of RAM.

The free version doesn't support Command Lines AFAIK.











Spoiler



## To Fill ##
$MemtestThreads = 12
$MemtestMemoryperThread = 1024
$RunMemtestWithLowPriority = $true

## Script Logic - do not modify until you are not know what you are doing! #
$StartArgument = "/t" + $MemtestMemoryperThread
$StartCount = $null
while($StartCount -lt $MemtestThreads) {
start memtestpro $StartArgument
$StartCount++
}

Start-Sleep 5
if ($RunMemtestWithLowPriority -eq $true){
foreach ($Process in (Get-Process | where {$_.Processname -like "*memtest*"})) {$Process.PriorityClass = "BelowNormal"}
}

$CSharpSource = @" 
using System; 
using System.Runtime.InteropServices;

namespace TW.Tools.InlinePS
{
public static class WindowManagement
{
[DllImport("user32.dll", EntryPoint = "SetWindowPos")]
public static extern IntPtr SetWindowPos(IntPtr hWnd, int hWndInsertAfter, int x, int Y, int cx, int cy, int wFlags);

public const int SWP_NOSIZE = 0x01, SWP_NOMOVE = 0x02, SWP_SHOWWINDOW = 0x40, SWP_HIDEWINDOW = 0x80;

public static void SetPosition(IntPtr handle, int x, int y, int width, int height)
{
if (handle != null)
{ 
SetWindowPos(handle, 0, x, y, 0, 0, SWP_NOSIZE | SWP_HIDEWINDOW);

if (width > -1 && height > -1)
SetWindowPos(handle, 0, 0, 0, width, height, SWP_NOMOVE);

SetWindowPos(handle, 0, 0, 0, 0, 0, SWP_NOSIZE | SWP_NOMOVE | SWP_SHOWWINDOW);
}
}
}
}
"@ 

Add-Type -TypeDefinition $CSharpSource -Language CSharp -ErrorAction SilentlyContinue

$Width = 267
$Height = 325
$monitor = Get-Wmiobject Win32_Videocontroller
$MaxVertical = $Monitor.CurrentVerticalResolution
$MaxHorizontal = $Monitor.CurrentHorizontalResolution
$XCount = 0
$YCount = 0

$AllProcesses = Get-Process -name memTest* | Sort-Object -Property StartTime


foreach ($Process in $AllProcesses){
if (($YCount * $Height) -ge ($MaxVertical - $Height)){
$YCount = 0
$XCount++
}

if ($YCount -eq "0"){
$PosY = ($YCount * $Height)
}
else{
$PosY = ($YCount * $Height - $YCount * 3)
}

$PosX = $MaxHorizontal - (($XCount+1) * $Width - (5 * ($XCount+1)))

[TW.Tools.InlinePS.WindowManagement]::SetPosition($Process.MainWindowHandle, $PosX, $PosY, $Width, $Height)
$Ycount++

}


----------



## bMind

Since I'm few days old owner of brand new Ryzen 2700X, Crosshair VII Hero and F4-3200C14D-32GTZR I decided to check in myself here as well  Since I'm at stock speeds (box cooler still) the only thing I could play a bit is the memory. I know that it's decent kit out of the box, with really nice timings and all..but there is always some room for improvement  Im currently using D.O.C.P profile that loaded referenced speeds for my kit - [email protected], screen from timing checker below.


----------



## minal

bMind said:


> Since I'm few days old owner of brand new Ryzen 2700X, Crosshair VII Hero and F4-3200C14D-32GTZR I decided to check in myself here as well  Since I'm at stock speeds (box cooler still) the only thing I could play a bit is the memory. I know that it's decent kit out of the box, with really nice timings and all..but there is always some room for improvement  Im currently using D.O.C.P profile that loaded referenced speeds for my kit - [email protected], screen from timing checker below.



The settings from here were stable and improved benchmarked performance. But D.O.C.P. profile is good enough that I didn't notice a difference when upgrading to a new BIOS and I didn't bother entering the settings again yet..


----------



## bMind

minal said:


> The settings from here were stable and improved benchmarked performance. But D.O.C.P. profile is good enough that I didn't notice a difference when upgrading to a new BIOS and I didn't bother entering the settings again yet..


I see  Still..thanks for the link


----------



## jinsk8r

Well after hours of testing I couldn't even make my kit (Galax HOF 3600) stable at 3333C14 so 3200 it is, error free, way less than I expected (3600)


----------



## Keith Myers

*An appeal to any SIV users for Save files from the developer*

The developer of SIV is needing Save_Local files from anyone running SIV 5.32 Beta-12 or later and owners of the Strix B450-F (0503, maybe earlier)
and Strix X470-I (0701) motherboards. The C6H and C7H boards are already covered. ASUS has been implementing WMI interrogations of ACPI resources in their latest BIOS. This is to standardize polling of motherboard sensor data across all platforms and to eliminate the conflicts that arise when multiple programs access the sensors at the same time, vis-a-vis the recent issues with HWinfo and AIDA64.

So anyone that might be running SIV could you please update to version 5.32 Beta-12 or later and let the system run for an hour before clicking the Save_Local file function. That creates two debug files that the developer uses to find the bugs in SIV and the ASUS BIOS of which many have been found already. You can send the Save files from within the Save_Local function after the polling finishes and creates the files. Only takes a minute.

Thanks in advance for any responses.

Cheers, Keith


----------



## Trender

NICE with the latest asus bios (released today) now I can run my RAMs 3600 for 1h 36 mins on Karhu ram test, what do you guys think, its stable?


jinsk8r said:


> Well after hours of testing I couldn't even make my kit (Galax HOF 3600) stable at 3333C14 so 3200 it is, error free, way less than I expected (3600)


Its because of ASRock crap bios. I have same RAMs lol and had an Asrock X370 Killer. With first ryzen 2000 BIOS I couldn't even run my RAMs at 3200 barely and later BIOS I got them at 3333 mhz (after waiting for BIOS with those early crap BIOS at 3200 barely!) so I bought this ASUS X470 strix F and can even run them at 3600 with profile only lol (I always had to tweak with ryzen calculator for asrock...)


----------



## Lisanderus

jinsk8r said:


> Hi, im new to this. Currently i don't OC the memory but these errors are there, what do I do? My memory is Galax (KFA2) HOF 3600 8gbx2 samsung b-die setting at 2133 C17 (default no XMP).
> Thank you!


Dont use 4.6 bios. Latest normal 4.4.


----------



## Wuest3nFuchs

*Samsung E-Die Dual Rank/Sided*

*Samsung E-Die Dual Rank/Sided success *with* Crucial Ballistix Elite BLE8G4D30AEEA.K16FE* 2*8GB *first introduced in 2016*


One thing that really got me :thinking:


So i got a really hard time fixing them to run stable over 2133mhz.
The last 3weeks to run @ rated 3000mhz and after that beyond were i was able to achieve 3200mhz.


XMP/DOCP didn't worked out well on my Prime X470, let's see what this ram does on the CH7.



WTH does micron use Samsung Dies? OR is typhoon burner wrong ,no!


Here's a test https://www.funkykit.com/reviews/me...-elite-16gb-ddr4-3000-cl16-memory-kit-review/


----------



## Trender

Any help with my weird samsung b rams? Everyone uses 53 Ohms but mines are just better with 43 Ohms :/
Still can't get them really stable at 3600 but I really want it


----------



## visata

I'm running F4-3200C14D-16GFX at 3200Mhz on CH6. I want to upgrade my PC with another 16GB (F4-3200C14D-16GFX). Will these 4x8GB run at 3200Mhz?

Thanks


----------



## tekjunkie28

Trender said:


> Any help with my weird samsung b rams? Everyone uses 53 Ohms but mines are just better with 43 Ohms :/
> Still can't get them really stable at 3600 but I really want it


Try T2 or more rttpark?

Sent from my SM-N950U using Tapatalk


----------



## browny2911

Ive had trouble for the last year running anything beyond 2933mhz on my r5 1600.

Here are my pc specs:

Ryzen r5 1600 Stock clock speed while testing ram
Asus strix b350-f motherboard running latest 4011 bios
Corsair vengeance lpx 3200mhz model no. CMK16GX4M2B3200C16 (not sure if e-die or Hynix based)
gtx 1060 6gb
Samsung 250gb ssd
WD HDD 500gb
windows 10 latest update
It runs stables 2933mhz at 14-14-14-36-54 at 1.36v Soc at 1.112v ProcOT 60ohms GDM enabled

Any idea how i could run it higher?


----------



## 1usmus

*Ryzen DRAM Calculator 1.3.0 released* 

https://www.overclock.net/forum/13-...r-1-1-0-beta-2-overclocking-dram-am4-116.html


----------



## gupsterg

Trender said:


> Any help with my weird samsung b rams? Everyone uses 53 Ohms but mines are just better with 43 Ohms :/
> Still can't get them really stable at 3600 but I really want it


Do not regard what ProcODT you need weird compared to another. This setting is dependent on your combined HW and targeted settings.

For example I have owned F4-3200C14D-16GTZ since having C6H from launch date. I used about 5 differing Ryzen gen 1 CPUs with that motherboard and RAM. I usually needed ProcODT of 53 or 60. Once I got a 2700X and C7H, the same RAM uses 48 for 3466MHz. If I move that CPU and RAM to C6H I need 53.


----------



## 1usmus

Trender said:


> Any help with my weird samsung b rams? Everyone uses 53 Ohms but mines are just better with 43 Ohms :/
> Still can't get them really stable at 3600 but I really want it



In this there is nothing wrong, here is an example for you 
43ohm for 3466


Spoiler














53ohm for 3666, but the system boots on 48ohm too


Spoiler














and this is not due to the new motherboard, but AGESA
In any case, this indicates the enormous OC potential of the system 



in which slots do you have memory installed? A1B1?


----------



## Trender

gupsterg said:


> Do not regard what ProcODT you need weird compared to another. This setting is dependent on your combined HW and targeted settings.
> 
> For example I have owned F4-3200C14D-16GTZ since having C6H from launch date. I used about 5 differing Ryzen gen 1 CPUs with that motherboard and RAM. I usually needed ProcODT of 53 or 60. Once I got a 2700X and C7H, the same RAM uses 48 for 3466MHz. If I move that CPU and RAM to C6H I need 53.





1usmus said:


> In this there is nothing wrong, here is an example for you
> 43ohm for 3466
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 53ohm for 3666, but the system boots on 48ohm too
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> and this is not due to the new motherboard, but AGESA
> In any case, this indicates the enormous OC potential of the system
> 
> 
> 
> in which slots do you have memory installed? A1B1?


loool guys I actually set higher rttpark and it actually got more stable! lmao so much time trying with subtimings and it was the rttpark it finally made it more stable.
For me my RAMs I can boot them @3600 from 43 ohms to 53 ohms at least, but its been always last longer in test with 43 Ohms ( I discovered it like a year ago+ when I couldn't get 3200 mhz on first month of ryzen 1, then changed the procodt to 43 ohms and there it was 3200 stables ! .( my rams are on a2 b2)
Alright so Ill try with the new calc 1.3 with tight timings, I got this one rn: https://www.overclock.net/forum/attachment.php?attachmentid=208368&thumb=1, isn't the new calc too optimistic lol?
Also about the new magic rttpark, do I need higher or lower RTTpark with different procodts(like maybe I can use 53 now) or something or I just need to try all the combinations of procodt and rttpark now?


----------



## thidiniz

Hello guys, my system is very stable, I have nothing to complain about, except for the Cold Boot, but I'm getting used to it.

Is there anything I can do to try to get better timings ou higher MHz? Again, I'm happy how things are, but if I can get a better performance, why not.

2700x XFR on (vCore Normal with -0.1250v)
x470 Gaming 7 Wifi (Bios F4J)
Patriot 2x8GB 3733 17-19-19-39 (PV416G373C7K) @ 14-16-16-16-36

Image: All timings with a red rectangle are set manually, everything else are on AUTO.


----------



## ssateneth

thidiniz said:


> Hello guys, my system is very stable, I have nothing to complain about, except for the Cold Boot, but I'm getting used to it.
> 
> Is there anything I can do to try to get better timings ou higher MHz? Again, I'm happy how things are, but if I can get a better performance, why not.
> 
> 2700x XFR on (vCore Normal with -0.1250v)
> x470 Gaming 7 Wifi (Bios F4J)
> Patriot 2x8GB 3733 17-19-19-39 (PV416G373C7K) @ 14-16-16-16-36
> 
> Image: All timings with a red rectangle are set manually, everything else are on AUTO.


tCWL can be lowered (may require higher tRDWR. increase tRDWR an amount equal to how much you lowered tCWL)

these timings im about to suggest typically don't need a long stability test. they either work or they don't (no POST)
after that, tRDWR and tWRRD lower individually as low as you can get it (I know you just increased tRDWR in the previous step. now we are lowering it with tuned tCWL)
tWRWRSC and tRDRDSC can be set to 1. might be called tWRWRSCL and tRDRDSCL
if you only have 1 DIMM per channel (so 2 DIMMs), tWRWRDD and tRDRDDD won't have any effect. I still set as low as I can because it makes me feel better. This is typically 1, sometimes 2 depending on manufacturer.
that just leaves tWRWRSD and tRDRDSD. these have to be tuned 1 at a time, same as for tuning tRDWR and tWRRD

what do these timings do? these are delays inserted between switching between read modes and write modes, and delays inserted between 2 reads or 2 writes on different physical layers (the DD, SD, and SC suffixes). end result is significantly better sequential reads/writes, higher copy, latency remains more or less the same.


----------



## tekjunkie28

thidiniz said:


> Hello guys, my system is very stable, I have nothing to complain about, except for the Cold Boot, but I'm getting used to it.
> 
> Is there anything I can do to try to get better timings ou higher MHz? Again, I'm happy how things are, but if I can get a better performance, why not.
> 
> 2700x XFR on (vCore Normal with -0.1250v)
> x470 Gaming 7 Wifi (Bios F4J)
> Patriot 2x8GB 3733 17-19-19-39 (PV416G373C7K) @ 14-16-16-16-36
> 
> Image: All timings with a red rectangle are set manually, everything else are on AUTO.


Where did y get f4J bios at??

Sent from my SM-N950U using Tapatalk


----------



## thidiniz

ssateneth said:


> tCWL can be lowered (may require higher tRDWR. increase tRDWR an amount equal to how much you lowered tCWL)
> 
> these timings im about to suggest typically don't need a long stability test. they either work or they don't (no POST)
> after that, tRDWR and tWRRD lower individually as low as you can get it (I know you just increased tRDWR in the previous step. now we are lowering it with tuned tCWL)
> tWRWRSC and tRDRDSC can be set to 1. might be called tWRWRSCL and tRDRDSCL
> if you only have 1 DIMM per channel (so 2 DIMMs), tWRWRDD and tRDRDDD won't have any effect. I still set as low as I can because it makes me feel better. This is typically 1, sometimes 2 depending on manufacturer.
> that just leaves tWRWRSD and tRDRDSD. these have to be tuned 1 at a time, same as for tuning tRDWR and tWRRD
> 
> what do these timings do? these are delays inserted between switching between read modes and write modes, and delays inserted between 2 reads or 2 writes on different physical layers (the DD, SD, and SC suffixes). end result is significantly better sequential reads/writes, higher copy, latency remains more or less the same.


Awesome, I'll try these settings, thank you very much



tekjunkie28 said:


> Where did y get f4J bios at??
> 
> Sent from my SM-N950U using Tapatalk


http://forum.gigabyte.us/thread/1542/am4-beta-bios-thread?page=133

Last post on this page


----------



## 1usmus

I have prepared for you an approximate tablet, in which there is a dependence of the change of procODT + RTT on the frequency. The PTT PARK parameter is marked with a blue color, which in most cases will have the best ratio of the useful signal to noise. Gray color indicates what I did not test. In the future, I will try to provide you with a more accurate version.

Remember, each memory module is a silicic lottery + printed circuit board has a different wiring (impedance).


----------



## Trender

FINALLY got my mems stable at 3533, lol took 2 years and 2 motherboards(the asrock one was trash, couldnt get more than 3333 mhz)
60 RTTPark did the trick, the always default was 48
So geardown, 43 OHms, 60 RTTpark + 1.45V DRAM


----------



## gupsterg

Usually for 3466MHz 1.37V seems AOK for me. Recently tweaked it to 1.365V. This CPU usually for SOC 0.968 - 0.981V snags 3466MHz depending upon which Samsung B Die sticks I use (GVK, GTZ, GTZSW, all 3200MHz C14 8GB sticks). The RTT tweaks are not for HCI stability/passing, but testing for another aspect.









Usually for 3533MHz 1.37-1.375V snags me some stability testing passes, reruns on same setup can fail, so still working on it .


----------



## maje90

Hi everybody!

I hope to find some help from you experts...
My ryzen pc is like 7 month old.
I did some rough oc back then and, indeed, up to today sometime I did have blue-screens or freeze in my games, so I wanted to check the situation.

My config is:
Asus CH6
1800X (under Noctua NH-D15)
F4-3600C15D-16GTZ
(and sapphire RX 580 8GB)

If i leave it all to "auto" in the bios, the RAM goes to 2200MHz, but i think its too low (i paid for a good one!), overclock then.
I'm not expert, I tried some set like 100 MHz base clock, 135MHz - 3600MHz RAM preset (in the bios), and other ... but it would always fail memtest in the first minutes!

I just tried to achieve something near this:
CPU 3800MHz 1.4V (SOC 1.15V)
RAM 3600MHz 1.4V 14-14-14-auto

Then suddenly a "lucky" combinations!... see attached screenshot.

And now my questions and doubts:
Why are the memtest percentages so different? (I started and stopped them all together)
There is some setting like frequency/voltage/youtell that is clearly wrong/unsafe/stupid?
There is something I could easily improve?

Thank you already!

Riccardo


----------



## Trender

maje90 said:


> Hi everybody!
> 
> I hope to find some help from you experts...
> My ryzen pc is like 7 month old.
> I did some rough oc back then and, indeed, up to today sometime I did have blue-screens or freeze in my games, so I wanted to check the situation.
> 
> My config is:
> Asus CH6
> 1800X (under Noctua NH-D15)
> F4-3600C15D-16GTZ
> (and sapphire RX 580 8GB)
> 
> If i leave it all to "auto" in the bios, the RAM goes to 2200MHz, but i think its too low (i paid for a good one!), overclock then.
> I'm not expert, I tried some set like 100 MHz base clock, 135MHz - 3600MHz RAM preset (in the bios), and other ... but it would always fail memtest in the first minutes!
> 
> I just tried to achieve something near this:
> CPU 3800MHz 1.4V (SOC 1.15V)
> RAM 3600MHz 1.4V 14-14-14-auto
> 
> Then suddenly a "lucky" combinations!... see attached screenshot.
> 
> And now my questions and doubts:
> Why are the memtest percentages so different? (I started and stopped them all together)
> There is some setting like frequency/voltage/youtell that is clearly wrong/unsafe/stupid?
> There is something I could easily improve?
> 
> Thank you already!
> 
> Riccardo


Voltages are safe, but that 100 mhz what do you mean? the clock engine? or you mean u OC'ng ur 1800x 100 mhz more? I think for 3.8 Ghz is better if you dont overclock your 1800X....
Also you don't have 14-14-14 from looking at CPU-Z, looks like it have the preset loaded.
Also 110% is quite low for memtest, you have to leave it wayyyyy more time


----------



## CJMitsuki

Trender said:


> Voltages are safe, but that 100 mhz what do you mean? the clock engine? or you mean u OC'ng ur 1800x 100 mhz more? I think for 3.8 Ghz is better if you dont overclock your 1800X....
> Also you don't have 14-14-14 from looking at CPU-Z, looks like it have the preset loaded.
> Also 110% is quite low for memtest, you have to leave it wayyyyy more time


Meh, 110% will find the majority of possible errors. If you aren’t running the machine with critical data then it won’t be a big deal. When he was talking about 100mhz he meant he overclocked the refclk from 100mhz to 135mhz. His CPUZ shows you the story. He may not be running c14 but if he had stumbled on 3600c14 stability that quick he would have been quite lucky. But attender does make a point, even though your memory OC is nice I would try for 3400-3533 at CL14 bc they perform better than what you currently have. To answer the question about why the percentages are all different, that’s bc each instance of MemTest you are running pertains to a different thread of your CPU and faster cores/threads will have higher percentage than the slower cores. Generally it’s cores 2,4,and 6 I see as being the faster ones but it ultimately depends on the silicon.


----------



## maje90

Ok, i lowered bus base clock to 105MHz, and also ram frequency.
But i managed to improve timings somehow... lowered tCl to 14 , and tRas and tRc by .. a lot!
One of the 16 Memtest instances found an error at 310% (bottom right)
(still I have very different percentages, I haven't found someone else with a behavior like this... )

Ram voltage is 1.375.

As i found an error past 200% i'm somehow thinking "well, it's good enough" ... but i'm a noob.
I feel like I'm somehow near a satisfying OC...

Any tips?
Should I push a bit more voltages? (I fear to damage the hardware so I'd like to stay under 1.4V ... does it make sense?)

OT
Does cpu frequency matter in memtest?
For "stability" in general there are other tests to try?


----------



## 1usmus

gupsterg said:


> Usually for 3466MHz 1.37V seems AOK for me. Recently tweaked it to 1.365V. This CPU usually for SOC 0.968 - 0.981V snags 3466MHz depending upon which Samsung B Die sticks I use (GVK, GTZ, GTZSW, all 3200MHz C14 8GB sticks). The RTT tweaks are not for HCI stability/passing, but testing for another aspect.
> 
> View attachment 209280
> 
> 
> Usually for 3533MHz 1.37-1.375V snags me some stability testing passes, reruns on same setup can fail, so still working on it .
> 
> View attachment 209282


Did you measure the real voltage of the RAM with a multimeter? (it's hard for me to believe that 1.375 volts for this frequency is enough)
Why do not you use CL14 and more tight timings?


----------



## 1usmus

*I ask guests and users of the forum to write down their results in the tables, this will help me improve the product, and you will also find something useful for yourself.*
Thanks!

ZEN >> https://docs.google.com/spreadsheet...CX-49Auk-aRAcTs-8cVNL1caHo/edit#gid=725475388
ZEN+ >> https://docs.google.com/spreadsheets/d/1Vm2i2-YIQKrZGpLO60l3JKX3nlMIr8ChhBTxvXQb13Y/edit#gid=0

_________________________

*TM5 0.12 config mod by me*

*added tests with complex random patterns

download TM5 0.12 >> http://testmem.tz.ru/tm5.rar
download config for TM5 0.12 >> https://drive.google.com/open?id=1bZz_mbcEgdizSx3NR2gJIXkqU0wfh4Ep


----------



## gupsterg

gupsterg said:


> Usually for 3466MHz 1.37V seems AOK for me. Recently tweaked it to 1.365V. This CPU usually for SOC 0.968 - 0.981V snags 3466MHz depending upon which Samsung B Die sticks I use (GVK, GTZ, GTZSW, all 3200MHz C14 8GB sticks). The RTT tweaks are not for HCI stability/passing, but testing for another aspect.
> 
> View attachment 209280
> 
> 
> Usually for 3533MHz 1.37-1.375V snags me some stability testing passes, reruns on same setup can fail, so still working on it .
> 
> View attachment 209282





1usmus said:


> Did you measure the real voltage of the RAM with a multimeter? (it's hard for me to believe that 1.375 volts for this frequency is enough)
> Why do not you use CL14 and more tight timings?


I hope this is OK, if you'd like an improved video let me know. Background noise has not been removed/edited. The section in video where:-

i) thermometer for room temp is shown.
ii) multimeter screen shown.

has been slowed to 1/2 speed.






If I use above 1.375V in UEFI I actually get worse training/errors on stability testing. Even if change other settings.

1.365V in UEFI results in 1.367V on DMM. My C7H for VDIMM upto 1.365V set in UEFI exhibits +0.02V, for 1.37V and above set in UEFI I see +0.05V on DMM.

As my C7H is early board, it shows ~1.1V on ProbeIt point/software monitoring for 1.05V chipset voltage, ie ~+50mV greater than actual.

I have some test results for 3533MHz using The Stilt 3466MHz timings on even less than 1.365V VDIMM.

I have yet to crack post to post training variation for 3533MHz  . As stated in your Ryzen DRAM Calculator thread I can pass a stability test for ages, then on next post it will not pass.

Even the SOC shown in video of ~1.04V on DMM (UEFI set to 1.056V) is excessive for my CPU sample. Below is over night run of 3533MHz at PState 0 4.1 1.325V, SOC 1.0125V, VDIMM: 1.365, VTT: 0.687, ProcODT: 53, RTT off off 80, room at start 27C, room at screen shot capture 26C, 1 error 1000% of 1500% (HCI log / UEFI settings).









View attachment HCI 4.1 1.325 1.0125 1.365 0.687 53 RTT off off 80 room 27C 26C 1 error 1000% of 1500%.txt


View attachment 0804_4.1_3533S_V2_setting.txt


----------



## Pepitorl

I bought a new PC a few days ago and I'm trying to make it stable.

Ryzen 7 2700x
Asus CH6
F4-3600C15D-16GTZ

For now I am in:
frequency: 3466
vsoc: 1.1
vram: 1.41
Timing: 14-14-14-26

If under the vram or vsoc, it becomes unstable, I have also tried to have the same latencies but using 3533 and 1.45 vram but it is not stable.

If I used an x470 motherboard, could I increase the frequency more easily?


----------



## gupsterg

Pepitorl said:


> I bought a new PC a few days ago and I'm trying to make it stable.
> 
> Ryzen 7 2700x
> Asus CH6
> F4-3600C15D-16GTZ
> 
> For now I am in:
> frequency: 3466
> vsoc: 1.1
> vram: 1.41
> Timing: 14-14-14-26
> 
> If under the vram or vsoc, it becomes unstable, I have also tried to have the same latencies but using 3533 and 1.45 vram but it is not stable.
> 
> If I used an x470 motherboard, could I increase the frequency more easily?


The C7H does not gain more RAM MHz than C6H in my experience, I own both and tried same CPU/RAM in each.

The C6H uses ASUS T-Topology, so each RAM slot is favoured as any other, old article on it. The C7H uses daisy chain topology, so 2 slots out of the 4 are more favourable to RAM than other 2.


----------



## 1usmus

gupsterg said:


> I hope this is OK, if you'd like an improved video let me know. Background noise has not been removed/edited. The section in video where:-
> 
> i) thermometer for room temp is shown.
> ii) multimeter screen shown.
> 
> has been slowed to 1/2 speed.
> 
> https://youtu.be/b57fVAXNt2U
> 
> If I use above 1.375V in UEFI I actually get worse training/errors on stability testing. Even if change other settings.
> 
> 1.365V in UEFI results in 1.367V on DMM. My C7H for VDIMM upto 1.365V set in UEFI exhibits +0.02V, for 1.37V and above set in UEFI I see +0.05V on DMM.
> 
> As my C7H is early board, it shows ~1.1V on ProbeIt point/software monitoring for 1.05V chipset voltage, ie ~+50mV greater than actual.
> 
> I have some test results for 3533MHz using The Stilt 3466MHz timings on even less than 1.365V VDIMM.
> 
> I have yet to crack post to post training variation for 3533MHz  . As stated in your Ryzen DRAM Calculator thread I can pass a stability test for ages, then on next post it will not pass.
> 
> Even the SOC shown in video of ~1.04V on DMM (UEFI set to 1.056V) is excessive for my CPU sample. Below is over night run of 3533MHz at PState 0 4.1 1.325V, SOC 1.0125V, VDIMM: 1.365, VTT: 0.687, ProcODT: 53, RTT off off 80, room at start 27C, room at screen shot capture 26C, 1 error 1000% of 1500% (HCI log / UEFI settings).
> 
> View attachment 209796
> 
> 
> View attachment 209798
> 
> 
> View attachment 209800


thanks for the detailed answer  I'm just probably used to seeing huge voltages for memory, I'm glad that the situation has changed now.
I see you are also using more resistance for RTT_PARK. The difference in stability you feel?
There is also a nuance with voltage for SOC, on a lower voltage system can perfectly cope with stress tests, but the cache and latency are deteriorating...you checked it? (I met this on my systems)
Do you have additional cooling for DRAM? What is the maximum temperature?

I want to share with you the information, the latest AGESA has changes with tertiary timings, tWRRD and tRDWR, they have a huge impact on stability. And their ratio can be not 7 to 3, for example, but and 10 to 12. And this allows to work very stable old micron b-die at a frequency of 3400, which is fantastic.


Spoiler
















Perhaps after this information you will find something interesting


----------



## maje90

maje90 said:


> Ok, i lowered bus base clock to 105MHz, and also ram frequency.
> But i managed to improve timings somehow... lowered tCl to 14 , and tRas and tRc by .. a lot!
> One of the 16 Memtest instances found an error at 310% (bottom right)
> (still I have very different percentages, I haven't found someone else with a behavior like this... )
> 
> Ram voltage is 1.375.
> 
> As i found an error past 200% i'm somehow thinking "well, it's good enough" ... but i'm a noob.
> I feel like I'm somehow near a satisfying OC...
> 
> Any tips?
> Should I push a bit more voltages? (I fear to damage the hardware so I'd like to stay under 1.4V ... does it make sense?)
> 
> OT
> Does cpu frequency matter in memtest?
> For "stability" in general there are other tests to try?


up?


----------



## nick name

Hi guys I have a G.SKILL TridentZ 3600CL15 kit. I am beginning to think it's my CPU's IMC that is holding the kit back, but I was hoping I could get some advice on tweaking in the event it isn't. I will post a screenshot below of what I can get prime95 stable at. I can get prime95 temporarily stable on some tighter timings and/or faster speeds, but of course that isn't actually stable. And the tighter timings staying stable is really what I am hoping to achieve. Please feel free to make any suggestions. Also, please note I do not change any of the Termination Block or CAD_BUS Block settings because I have no idea how those impact anything so guidance there would be extremely helpful.


----------



## ajc9988

nick name said:


> Hi guys I have a G.SKILL TridentZ 3600CL15 kit. I am beginning to think it's my CPU's IMC that is holding the kit back, but I was hoping I could get some advice on tweaking in the event it isn't. I will post a screenshot below of what I can get prime95 stable at. I can get prime95 temporarily stable on some tighter timings and/or faster speeds, but of course that isn't actually stable. And the tighter timings staying stable is really what I am hoping to achieve. Please feel free to make any suggestions. Also, please note I do not change any of the Termination Block or CAD_BUS Block settings because I have no idea how those impact anything so guidance there would be extremely helpful.


If that is stable and you are trying to tighten things down, first I would try to do tWR at 12, lower tRDRD SCL and tWRWR SCL to 3 and 3 (if you can get these down to 2s, great, but start with 3s as it should be easier to obtain), try tCKE at 1 instead of 9, and see if stable. If not, you can also try to change tRTP to 10, tighten tRDWR to 7 (no guarantee here), and try tWRRD at 4 instead of 3, potentially. Then, if you can get tFAW between 15 and 30 (whatever is tighter and stable), that would be great. 

You may need to play with some other settings and the SOC or DRAM voltages to get this stable. Then there is attempting to do the tRFC timings which give me hell at times. But those are some potential timings to play with to try to tighten up the speed.

If concerned with snappiness, if you want, use TM5 and watch the amount of time to complete a full cycle. That should tell you if it is helping with aspects that will benefit you on the snappiness of the system response. 

Take note before you start of current stable settings. Also, it is wise to do a backup in case you frag your windows install. It doesn't always happen, but when it does, you'll be happy you can just restore your system to a stable image.


----------



## CJMitsuki

nick name said:


> Hi guys I have a G.SKILL TridentZ 3600CL15 kit. I am beginning to think it's my CPU's IMC that is holding the kit back, but I was hoping I could get some advice on tweaking in the event it isn't. I will post a screenshot below of what I can get prime95 stable at. I can get prime95 temporarily stable on some tighter timings and/or faster speeds, but of course that isn't actually stable. And the tighter timings staying stable is really what I am hoping to achieve. Please feel free to make any suggestions. Also, please note I do not change any of the Termination Block or CAD_BUS Block settings because I have no idea how those impact anything so guidance there would be extremely helpful.


Nothing is holding your kit back. To even get 3600 at Tcl 14 semi stable is decent. Now here’s what you have to do. Drop to 3533mhz and tighten...now you’ll be faster than 3600 with those timings. Cad_bus looks ok at 24ohm as does the other resistances. Try 3533 at 14-14-14-14-30-44-4-6-24-4-8-12-0-2-2-260-auto-auto-14-8-8-3-1-7-7-1-5-5-1...These are kind of tight but not to the maximum. I guarantee you if you get those timings or a hair tighter then you’ll forget 3600mhz. Also you’ll want to refresh your windows install using the “sfc /scannow” and “DISM” commands as that can rid you of system file corruption very easily. Also I’ve found that reflashing bios after testing and failing mem tests can be enough to rid you of an irritating error that seems impossible to get rid of. You can also set 30-30-40-40 or 30-30-40-60ohm and possibly scrape up some more stability. But there is nothing wrong with your cpu or memory, you are just at the limit of most good kits for Ryzen at the moment. Roll 3533 and wait for the next bios and try again.


----------



## nick name

CJMitsuki said:


> Nothing is holding your kit back. To even get 3600 at Tcl 14 semi stable is decent. Now here’s what you have to do. Drop to 3533mhz and tighten...now you’ll be faster than 3600 with those timings. Cad_bus looks ok at 24ohm as does the other resistances. Try 3533 at 14-14-14-14-30-44-4-6-24-4-8-12-0-2-2-260-auto-auto-14-8-8-3-1-7-7-1-5-5-1...These are kind of tight but not to the maximum. I guarantee you if you get those timings or a hair tighter then you’ll forget 3600mhz. Also you’ll want to refresh your windows install using the “sfc /scannow” and “DISM” commands as that can rid you of system file corruption very easily. Also I’ve found that reflashing bios after testing and failing mem tests can be enough to rid you of an irritating error that seems impossible to get rid of. You can also set 30-30-40-40 or 30-30-40-60ohm and possibly scrape up some more stability. But there is nothing wrong with your cpu or memory, you are just at the limit of most good kits for Ryzen at the moment. Roll 3533 and wait for the next bios and try again.


Well the posted timings are actually prime95 stable, but I will try 3533 at those timings you suggested and test those with aida64 against what I get currently. And I do use sfc and DISM whenever I feel I need it and I also reset the BIOS occasionally too. So it makes me happy to hear I am doing some things right.


----------



## nick name

ajc9988 said:


> If that is stable and you are trying to tighten things down, first I would try to do tWR at 12, lower tRDRD SCL and tWRWR SCL to 3 and 3 (if you can get these down to 2s, great, but start with 3s as it should be easier to obtain), try tCKE at 1 instead of 9, and see if stable. If not, you can also try to change tRTP to 10, tighten tRDWR to 7 (no guarantee here), and try tWRRD at 4 instead of 3, potentially. Then, if you can get tFAW between 15 and 30 (whatever is tighter and stable), that would be great.
> 
> You may need to play with some other settings and the SOC or DRAM voltages to get this stable. Then there is attempting to do the tRFC timings which give me hell at times. But those are some potential timings to play with to try to tighten up the speed.
> 
> If concerned with snappiness, if you want, use TM5 and watch the amount of time to complete a full cycle. That should tell you if it is helping with aspects that will benefit you on the snappiness of the system response.
> 
> Take note before you start of current stable settings. Also, it is wise to do a backup in case you frag your windows install. It doesn't always happen, but when it does, you'll be happy you can just restore your system to a stable image.



I will try those. I haven't been doing anything beyond changing everything all at once so having a strategy will help with the hair pulling. Thank you for that.


----------



## nick name

Are there any other voltages I can manipulate beyond the standard DRAM and SOC that can aid stability?


----------



## ajc9988

nick name said:


> I will try those. I haven't been doing anything beyond changing everything all at once so having a strategy will help with the hair pulling. Thank you for that.


Cool. And you may need to set the CLDO voltage rather than auto to either 700, 866, or 913, which are main recs in the calculator. You may also need to play with the RTT resistances or the CAD_BUS to stabilize it (not just the block resistances, but the timings, which you should try 0 or 1 on each one looking for stable with those if need be, but hold off on that until you've tried other things to try to get it stable). 

Another way is to play with the calculator and run through v1 and v2 with different timings to watch and see how those recommendations change depending on the speed for the ram in the calculator, the version, and whether Safe, Fast, or Extreme is being used. After you get a feel for which are changed together, you might start getting a feel for potential timings that could be changed to help stabilize a clock, even if you don't know the why yet. Also, sometimes too much voltage can cause errors to kick, or at least it did for me. If you are starting from stable at the ram speed, then it usually is increasing voltages to find stable, but if you never had stable at that speed, it can be difficult to hunt and peck for timings or voltages. That, at least, is what I've seen. And remember, what you set isn't always what the board is sending, so if the calculator says a certain voltage, you may need to set slightly lower in voltage so what is delivered is the amount recommended. The voltage can also vary by your hardware. You can play with what LLCs are available to you as well. 

Hope this helps. And happy hunting!


----------



## ajc9988

nick name said:


> Are there any other voltages I can manipulate beyond the standard DRAM and SOC that can aid stability?


Look at the second page in the calculator under the advanced tab, or look at the power supply system tab in the calculator to get an idea. That should give other settings that can help performance or stability. Start with the main ones. Then CLDO. Then interleaving settings. Then timings. Then I will try the debug voltages mentioned if the other ones did not help. Also, when playing with the DRAM voltage, you can play with the VTT voltages to look for stable (so SOC and DRAM, then VTT, then CLDO, then timings further, etc.).


----------



## nick name

ajc9988 said:


> Look at the second page in the calculator under the advanced tab, or look at the power supply system tab in the calculator to get an idea. That should give other settings that can help performance or stability. Start with the main ones. Then CLDO. Then interleaving settings. Then timings. Then I will try the debug voltages mentioned if the other ones did not help. Also, when playing with the DRAM voltage, you can play with the VTT voltages to look for stable (so SOC and DRAM, then VTT, then CLDO, then timings further, etc.).


I couldn't find an answer anywhere on whether CLDO_VDDP voltage was just for memory training to fill holes or if it helped stability. And honestly I kinda forgot the Advanced page was there in the Calculator.


----------



## ajc9988

nick name said:


> I couldn't find an answer anywhere on whether CLDO_VDDP voltage was just for memory training to fill holes or if it helped stability. And honestly I kinda forgot the Advanced page was there in the Calculator.


1usmus has a page linked about it in the Ryzen DRAM Calculator page (in the bottom of the first post). It is used to help with memclk holes, so allowing for higher speeds to be stable easier if not in the hole for the voltage set. He is a wealth of information on the topic. I'd say just review the other tabs in the calculator and his links to other strings in the forum for a bit off of that first page to get familiarity with your bearings, then start the playing. Also, don't forget to review his ram flow chart included with the new 1.31 DRAM calculator, as that will also give you an idea on what to play with and when. I gave you a bit more on timings you can try, but as he pointed out, finding the right tFAW is a good place to start. The other subtimings work together as a body, so changing one can throw off the balance, but if the balance is already off.... But, you still need to be in a range with those and not just trying to tighten or loosen some of them separate from some others. I tried to give an idea of the ones you have a bit more wiggle room with, but you may want to reset them to something you knew worked with the other timings previously before grabbing a different one to try, or figuring out similar combinations.

Another way to look at them is to study the changes recommended between an older version (like 1.2 beta x) and the current version to start seeing how those timings changed between the versions on recommendations. 

Personally, I see the calculator as a guideline. If they work for you, great. If not, there is a pattern to hunt for stability. It may take hours or days of testing to find stable and certify it on your system. It can be a process. But, once you do it, you have accomplished tight timings on 3600, a feat few have done (I used to have that). Also, share the stable timings with 1usmus in the spreadsheets he has for timings. This gives more data points, which allows for him to refine his calculator, which helps the community as a whole.


----------



## gupsterg

1usmus said:


> thanks for the detailed answer  I'm just probably used to seeing huge voltages for memory, I'm glad that the situation has changed now.
> I see you are also using more resistance for RTT_PARK. The difference in stability you feel?
> There is also a nuance with voltage for SOC, on a lower voltage system can perfectly cope with stress tests, but the cache and latency are deteriorating...you checked it? (I met this on my systems)
> Do you have additional cooling for DRAM? What is the maximum temperature?
> 
> I want to share with you the information, the latest AGESA has changes with tertiary timings, tWRRD and tRDWR, they have a huge impact on stability. And their ratio can be not 7 to 3, for example, but and 10 to 12. And this allows to work very stable old micron b-die at a frequency of 3400, which is fantastic.
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Perhaps after this information you will find something interesting


It is only this Ryzen gen 2 CPU that seems to allow usage of lower VDIMM. All the Ryzen gen 1 CPUs and single 1950X I have need more, even when same RAM kit used.

See new video in spoiler below. Video has HCI pass of ~1500% on below settings, CPU-Z tabs/bench, AIDA64 bench.

Ryzen 2700X Batch 1805SUS
ASUS C7H WiFi UEFI 0702 (was trying to see if an older UEFI allows 3533MHz, but no go)
F4-3200C14-8GVK @ 3466MHz The Stilt (2 dimms from a quad channel kit)

PState 0 4.1GHz VID: 1.325V, SOC: 1.006V, VDIMM: 1.355V, VTT: 0.687V, ProcODT/CAD Bus/RTT all auto. As LLC is [Auto] (ie AMD Stock) I can experience greater VDROOP on VCORE/SOC depending on load.



Spoiler











Changing RTT settings is strange and "hit'n'miss", probably as I only have single rank/sided dimms. For example if I use F-3200C14D-16GTZ as in previous video, I can use higher RTT values if particular dimms are in A2/B2, if I swap the same dimms around in the slots I can not change RTT nom, wr and or park, even I single setting/step. The F4-3200C14-8GVK IIRC also don't allow any changes to RTT, I will check later.

I see no deterioration in AIDA64 benchmark when using lower SOC. No additional cooling for RAM. My setup is good airflow. The front intake/CPU TY-143 can spin upto 2.5K RPM. Usually ~40C (+/- ~2C) when under load and some what depends on room ambient.



Spoiler














I will try the tWRRD and tRDWR tweak at some point, thank you for share of tip .


----------



## CJMitsuki

gupsterg said:


> It is only this Ryzen gen 2 CPU that seems to allow usage of lower VDIMM. All the Ryzen gen 1 CPUs and single 1950X I have need more, even when same RAM kit used.
> 
> See new video in spoiler below. Video has HCI pass of ~1500% on below settings, CPU-Z tabs/bench, AIDA64 bench.
> 
> Ryzen 2700X Batch 1805SUS
> ASUS C7H WiFi UEFI 0702 (was trying to see if an older UEFI allows 3533MHz, but no go)
> F4-3200C14-8GVK @ 3466MHz The Stilt (2 dimms from a quad channel kit)
> 
> PState 0 4.1GHz VID: 1.325V, SOC: 1.006V, VDIMM: 1.355V, VTT: 0.687V, ProcODT/CAD Bus/RTT all auto. As LLC is [Auto] (ie AMD Stock) I can experience greater VDROOP on VCORE/SOC depending on load.
> 
> 
> 
> Spoiler
> 
> 
> 
> https://youtu.be/YlZww1perIE
> 
> 
> 
> Changing RTT settings is strange and "hit'n'miss", probably as I only have single rank/sided dimms. For example if I use F-3200C14D-16GTZ as in previous video, I can use higher RTT values if particular dimms are in A2/B2, if I swap the same dimms around in the slots I can not change RTT nom, wr and or park, even I single setting/step. The F4-3200C14-8GVK IIRC also don't allow any changes to RTT, I will check later.
> 
> I see no deterioration in AIDA64 benchmark when using lower SOC. No additional cooling for RAM. My setup is good airflow. The front intake/CPU TY-143 can spin upto 2.5K RPM. Usually ~40C (+/- ~2C) when under load and some what depends on room ambient.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 210676
> 
> 
> 
> 
> I will try the tWRRD and tRDWR tweak at some point, thank you for share of tip .


The kit being single sided doesn’t have any bearing on the RttPark values as mine are F4-3200c14-8gtzr and I can use up to 60ohm throughout most straps but I can only use 80ohm for 3600 and higher. It will not boot at lower frequencies at 80ohm. Maybe it’s just your kit or the timings you are running, possibly the vDIMM voltage? You run your DRAM quite low compared to what I run which is why I say that. I don’t see higher voltages affect the temps on my sticks much at all. Also I rarely have to change SoC at all. At 3533 with tight timings and 3600 I have to use 1.1v but everything below that I use 1.0875v. But even running 1.55v or 1.6v on my DRAM doesn’t make it get hot. I see maybe 31-32c max on my sticks after a long benching run. I think it’s just the Silicon Lottery or the board itself having that effect. Also I used to manually adjust everything in the Tweakers Paradise tab but I only set a couple of things now. CLDO_VDDP and Disable Sense Mi Skew and the one that is generally half of the VDIMM voltage I forget the name. Also things that give more stability such as disabling OpCache have other effects on certain instruction sets. I’ve seen it greatly affect certain benchmarks. Also Streaming Stores can have a huge change in memory bandwidth from what I’ve seen. If it is disabled I saw memory bandwidth drop by 50%. I want access to the options Asus disabled on 0804 that I could access through the search function. I want to see how they affect memory and processor performance. I don’t want to downgrade to be able to access them again but I may have no other choice.


----------



## gupsterg

Within Tweakers Paradise I usually only disable Sense MI Skew and set VTTDDR, ie the one which is supposed to be set 1/2 of VDIMM.

I try to keep tweaks to lowest number of settings I can for a profile.

I go for lower voltage on any aspect of profile for various reasons, usually not due to temperature though. More so I think lower voltages would have improved "data eye" aspects, ie less noise, etc.

CLDO_VDDP I only tweak if a CPU has a memory hole, which this 2700X does not have, only tested upto 3600MHz for post issues.

Why I say "Changing RTT settings is strange and "hit'n'miss", probably as I only have single rank/sided dimms." is as a lot of stuff I have referenced seems to highlight single rank/sided RAM does not need RTT tweaks. Will double check. Again as said before I can only use higher RTT nom, wr and park on the GTZ when I place particular dimms in A2/B2 of C7H, if I swap same dimms around between A2/B2 I can't. The 2 GVK I have used out of a quad set do not tolerate any tweaks of RTT from quick testing I did.

As a new ZE UEFI came out and I have GTZSW on them, again RTT tweaks seem to affect stability rather than aid me.

Again I'm not disputing RTT tweaks work for others and me, nor am I suggesting people don't try tweaking them, just only sharing what I'm experiencing with whatever I am tinkering with  .

On the TR/ZE rig as I have low airflow, due to rads, etc. I can see higher dimm temps.



Spoiler


----------



## ajc9988

gupsterg said:


> Within Tweakers Paradise I usually only disable Sense MI Skew and set VTTDDR, ie the one which is supposed to be set 1/2 of VDIMM.
> 
> I try to keep tweaks to lowest number of settings I can for a profile.
> 
> I go for lower voltage on any aspect of profile for various reasons, usually not due to temperature though. More so I think lower voltages would have improved "data eye" aspects, ie less noise, etc.
> 
> CLDO_VDDP I only tweak if a CPU has a memory hole, which this 2700X does not have, only tested upto 3600MHz for post issues.
> 
> Why I say "Changing RTT settings is strange and "hit'n'miss", probably as I only have single rank/sided dimms." is as a lot of stuff I have referenced seems to highlight single rank/sided RAM does not need RTT tweaks. Will double check. Again as said before I can only use higher RTT nom, wr and park on the GTZ when I place particular dimms in A2/B2 of C7H, if I swap same dimms around between A2/B2 I can't. The 2 GVK I have used out of a quad set do not tolerate any tweaks of RTT from quick testing I did.
> 
> As a new ZE UEFI came out and I have GTZSW on them, again RTT tweaks seem to affect stability rather than aid me.
> 
> Again I'm not disputing RTT tweaks work for others and me, nor am I suggesting people don't try tweaking them, just only sharing what I'm experiencing with whatever I am tinkering with  .
> 
> On the TR/ZE rig as I have low airflow, due to rads, etc. I can see higher dimm temps.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 210726
> 
> 
> View attachment 210728


Not disputing your experience, but I did find mine to be slightly different on the Asrock Taichi X399. After the new BIOS, I see voltages read in HWInfo as being slightly higher than they used to be with the older BIOSes. So, I am running my ram within the same voltage envelope that I used to according to HWInfo, but am setting about 20mV less. As for the voltages on the SOC, I am now using the same voltage I was before, but because it is on LLC1 instead of 2 now, it is slightly higher. So it is a mixed bag and on actual voltage set, it is lower, but voltage read the same. 

Meanwhile, I was getting a little closer to getting 3733 stable at one point, but it just shot up the required voltage on DIMMs by about 60-80mV (20-40 over the top amount of voltage I was using before, which was 1.44V, which I got to run at 1.4V, but with a slight decline in CB score, but not enough to care; voltage that was close was around 1.47-1.48, but more voltage wasn't stabilizing, so need to see what to set - WIP). 

But I did want to thank you for sharing your experience and what you saw with your equipment. Every brick is needed to create a wall, every data point is needed to see the whole of platform behavior. So, thank you!


----------



## gupsterg

Likewise I have read some of your posts and valued shares of experience  , so thanks.

Pretty much on the C6H/ZE the average column for VDIMM is reflective of what I set in UEFI for it. Usual setup for HWINFO is polling interval of 750ms, this makes the average monitoring data better to ref. So the 3466MHz ZE screenie 1.373V = 1.375V set in UEFI. Due to how the granularity is for read back of voltages from Super IO chip, some voltages do read back incorrectly. Dunno if it is my particular ZE board, but channels AB VDIMM can be reported back lower than CD, depending on settings.

Most of my time is spent determining 24/7 usage profiles, so I use LLC [Auto] which tends to be AMD stock on ASUS boards. I can encounter large VCORE/SOC VDROOP.

On the C7H if I use a version of HWINFO without ASUS WMI, VDIMM is vastly lower than I have set.

Latest ZE UEFI has more RAM MHz without need for BCLK change. Last night tested 3400MHz @ VDIMM: 1.355V SOC: 1.05V.



Spoiler




View attachment 1402_3400S_LV_setting.txt


----------



## Cyanold

Hi all,

Just complete my build, i am trying to overclock the ram. I enabled the docp in the bios and set speed at 3600mhz, no other changes, i can managed to get in the system but games will crash also get errors in MemTest86 for first few minutes.

I tried to turn the speed down to 3466, it passed 2 passes. Could anyone suggest me any ways i can get the ram speed up to 3600mhz or i should just settle at 3466 mhz. The performance gain from 3466 to 3600 seems pretty marginal a
The build is:
Ryzen 2700X
Asus Crosshair VI Hero 6201
Gskill Ripjaws V F14 3600C16D 16GVK B die


----------



## nick name

Cyanold said:


> Hi all,
> 
> Just complete my build, i am trying to overclock the ram. I enabled the docp in the bios and set speed at 3600mhz, no other changes, i can managed to get in the system but games will crash also get errors in MemTest86 for first few minutes.
> 
> I tried to turn the speed down to 3466, it passed 2 passes. Could anyone suggest me any ways i can get the ram speed up to 3600mhz or i should just settle at 3466 mhz. The performance gain from 3466 to 3600 seems pretty marginal a
> The build is:
> Ryzen 2700X
> Asus Crosshair VI Hero 6201
> Gskill Ripjaws V F14 3600C16D 16GVK B die


When I enable DOCP on my RAM I still have to add more voltage above the 1.35v it sets. I would also encourage you to bump the SOC up a little too. 1.1v can be the sweet spot for many, but you may just need a slight +offset. 

If you don't feel like fiddling with it right now then I would suggest going straight to something like 1.45v on DRAM and 1.1v on the SOC. Then when you have time start lowering voltages to see where it stays stable. My 3600MHz is running both of those numbers but my timings are tighter than the DOCP settings.


----------



## CJMitsuki

Cyanold said:


> Hi all,
> 
> Just complete my build, i am trying to overclock the ram. I enabled the docp in the bios and set speed at 3600mhz, no other changes, i can managed to get in the system but games will crash also get errors in MemTest86 for first few minutes.
> 
> I tried to turn the speed down to 3466, it passed 2 passes. Could anyone suggest me any ways i can get the ram speed up to 3600mhz or i should just settle at 3466 mhz. The performance gain from 3466 to 3600 seems pretty marginal a
> The build is:
> Ryzen 2700X
> Asus Crosshair VI Hero 6201
> Gskill Ripjaws V F14 3600C16D 16GVK B die


My suggestion is to forget 3600, it isn’t worth the headache. 3533 will get you a better result at the moment since you’ll be able to tighten it up much further. I just got 3533mhz stable at c13 and it wasn’t nearly the headache that 3600c14 was and it’s better performance than 3666 and 3733 @c14. 3600 will just cause you misery for little to no gain in performance over 3533 with good timings.


----------



## nick name

CJMitsuki said:


> My suggestion is to forget 3600, it isn’t worth the headache. 3533 will get you a better result at the moment since you’ll be able to tighten it up much further. I just got 3533mhz stable at c13 and it wasn’t nearly the headache that 3600c14 was and it’s better performance than 3666 and 3733 @c14. 3600 will just cause you misery for little to no gain in performance over 3533 with good timings.


Have you posted your 3533CL13 timings yet? I'd like to give them a try.


----------



## CJMitsuki

nick name said:


> Have you posted your 3533CL13 timings yet? I'd like to give them a try.


They are on the Crosshair 7 Hero thread. I had to flash an earlier bios as I couldn’t get it completely stable on the most current one from Asus. I have the DRAM voltage at 1.49v and it is also stable with 104 bclk at 4.5ghz initially. I’ll do more in depth testing later this evening as I had to head to work but as it sits it is stable in my eyes. Initially it had about 2-3 errors per 100% and it took me about 5 hours to find the right settings which was higher DRAM voltage and a much lower SoC with a couple of other tweaks to resistances. Wasn’t too horrible but in the end the main culprit was only one tick away and the least suspect.


----------



## nick name

Can anyone tell me about tcke? What it impacts? Bandwidth or latency? And are the only values 1 or 9?


----------



## nick name

So I have been playing with this for a few hours and it is starting to look very promising. I just purchased HCI MemTestPro, but have only tested with prime95 and MemTest64 so far and those haven't returned any errors.


----------



## Cyanold

nick name said:


> When I enable DOCP on my RAM I still have to add more voltage above the 1.35v it sets. I would also encourage you to bump the SOC up a little too. 1.1v can be the sweet spot for many, but you may just need a slight +offset.
> 
> If you don't feel like fiddling with it right now then I would suggest going straight to something like 1.45v on DRAM and 1.1v on the SOC. Then when you have time start lowering voltages to see where it stays stable. My 3600MHz is running both of those numbers but my timings are tighter than the DOCP settings.


Thanks for all the information. I increased Dram Voltage to 1.45V and leave SOC at Auto (BIOS is showing 1.19).Run two tests on Memtest 86, no errors. 

I rerun memory bench mark on Aida64 just for comparison the gain and noticed that the latency has gone up by 1.5ns at 63.4ns. Should this gone another way after I increased the frequency?

Another question about Dram Voltage, probably been answered many times before, but is 1.45V suitable for long run?


----------



## Cyanold

nick name said:


> So I have been playing with this for a few hours and it is starting to look very promising. I just purchased HCI MemTestPro, but have only tested with prime95 and MemTest64 so far and those haven't returned any errors.


Your memory is very capable, what model is this?


----------



## nick name

Cyanold said:


> Thanks for all the information. I increased Dram Voltage to 1.45V and leave SOC at Auto (BIOS is showing 1.19).Run two tests on Memtest 86, no errors.
> 
> I rerun memory bench mark on Aida64 just for comparison the gain and noticed that the latency has gone up by 1.5ns at 63.4ns. Should this gone another way after I increased the frequency?
> 
> Another question about Dram Voltage, probably been answered many times before, but is 1.45V suitable for long run?



At those looser timings the latency will increase. If you can bring them down then the latency should follow. 

And I am using a G.SKILL TridentZ 3600CL15 2x8GB kit.


----------



## Cyanold

nick name said:


> At those looser timings the latency will increase. If you can bring them down then the latency should follow.
> 
> And I am using a G.SKILL TridentZ 3600CL15 2x8GB kit.


I didnt touch timing so was the same 16-16-16-36, push the frequency from 3433 to 3600, i was getting higher latency in AIDA64 by 1.5.

I also tried to adjust timing based on RAM Calculator as per below shot, but getting errors in Memtest 86 test 8, tried loose CL to 15 doesnt help. Reduce the frequency to 3533 Mhz with 14-15-15-30 timing, it's stable. Also tried to tight tRCDWR to 14, getting errors. Lots of time and efforts need to put in in order to get timing right.

Still looking for ways to get my RAM up to 3600.

Thanks in advance


----------



## CJMitsuki

Cyanold said:


> I didnt touch timing so was the same 16-16-16-36, push the frequency from 3433 to 3600, i was getting higher latency in AIDA64 by 1.5.
> 
> I also tried to adjust timing based on RAM Calculator as per below shot, but getting errors in Memtest 86 test 8, tried loose CL to 15 doesnt help. Reduce the frequency to 3533 Mhz with 14-15-15-30 timing, it's stable. Also tried to tight tRCDWR to 14, getting errors. Lots of time and efforts need to put in in order to get timing right.
> 
> Still looking for ways to get my RAM up to 3600.
> 
> Thanks in advance





Sometimes instead of going up in frequency you should just go down in cas latency. could be easier and much better. 

This is HCImemtest stable for me for 10 hours


Spoiler













HCImemtest64


Spoiler


----------



## ajc9988

gupsterg said:


> Likewise I have read some of your posts and valued shares of experience  , so thanks.
> 
> Pretty much on the C6H/ZE the average column for VDIMM is reflective of what I set in UEFI for it. Usual setup for HWINFO is polling interval of 750ms, this makes the average monitoring data better to ref. So the 3466MHz ZE screenie 1.373V = 1.375V set in UEFI. Due to how the granularity is for read back of voltages from Super IO chip, some voltages do read back incorrectly. Dunno if it is my particular ZE board, but channels AB VDIMM can be reported back lower than CD, depending on settings.
> 
> Most of my time is spent determining 24/7 usage profiles, so I use LLC [Auto] which tends to be AMD stock on ASUS boards. I can encounter large VCORE/SOC VDROOP.
> 
> On the C7H if I use a version of HWINFO without ASUS WMI, VDIMM is vastly lower than I have set.
> 
> Latest ZE UEFI has more RAM MHz without need for BCLK change. Last night tested 3400MHz @ VDIMM: 1.355V SOC: 1.05V.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 210810
> 
> View attachment 210812
> 
> View attachment 210814
> 
> View attachment 210816


Yeah, I can understand that. And until AGESA 1.1.0.0 (BIOS 3.0 or higher) on the X399 Taichi, I saw more droop on auto. Now, it sets it to LLC 1 and I see an equal to slightly higher voltage on what HWinfo is reading. And with the ram, it is coming up 30mV higher, but is fine as long as you pay attention to what you are using. I do look for 24/7 settings also, but just for my rig. 

Meanwhile, I hear the same thing from people on the Asrock Taichi side, that you can get higher speeds without BCLK. It is true for the majority, but it has knocked me down from 3600MHz with 100BCLK. 

Here was my attempt last night at 3600 again. Almost stable, but I couldn't get it there primarily due to cache issues (and SOC voltage could not stabilize, I tried multiple LLCs, etc.). 

I had to loosen tRDRD SCL and tWRWR SCL to 3s, as HCI got errors on 2s, and the L3 read was down at 200 and something on one run of AIDA64. After an all night HCI run, wound up with 6 errors in 1000% with the 3s, so still not stable. But, when I ran CB15 with nothing else open, I was back to 3545, which is in the range of what I used to get (I think around the 3560 to 3600 scores were with 4.1GHz, not 4.05GHz, which is my normal clocks for the system). But, I'm hoping to get it back to where I was at before. SOC was set to 1.05 LLC2 (found it more stable than LLC1 and lower voltage), DRAM set to 1.41V in BIOS (1.44V in HWInfo). It seems like going to 3s on that resolved the issue with the L3 odd behavior and only hit performance on TM5 by 2 or 4 seconds per cycle, which isn't too bad. 

The readings from what was set used to be tight, so more than likely just issues needing ironed out with the new BIOSes preparing for the TR2. If you guys have an idea on something I may be missing, let me know.


----------



## nick name

I know everyone uses HCI MemTest (I just paid for pro also), but is anyone using the Stilt recommended Karhu RAM Test? I saw him recommended it in a post last December where he said it performed faster due to X86 programming so I bought it too. I am using it now and I just wanted to see if anyone uses it and has any best practices to share.


----------



## CJMitsuki

nick name said:


> I know everyone uses HCI MemTest (I just paid for pro also), but is anyone using the Stilt recommended Karhu RAM Test? I saw him recommended it in a post last December where he said it performed faster due to X86 programming so I bought it too. I am using it now and I just wanted to see if anyone uses it and has any best practices to share.


When RamTest first released I bought it and used it but after a few bios updates it seemed to become more and more inconsistent in its testing so I stopped using it. Not sure if it has received an update at all but if not then I don’t plan to use it again until it does. HCI was and still is the most consistent for me. Not to mention the extra test for running without the OS. If it gets an update I’ll try it again and see if the inconsistencies are gone.


----------



## gupsterg

@ajc9988

I wouldn't read too much into AIDA64 bench swing on cache, etc TBH. Seen it swing so many times on Ryzen gen 1/2 and Threadripper for really no apparent reason. Again I've read some highlight they use it as a guide to stability, etc. I really can't say that I find that bench feasible in that context. IIRC when the bench is run it is given higher priority as process but it still can be affected by a background process.

3466MHz is the best I've had out of my TR, 3533MHz attempts did not bare fruit for me, so is nice to see 3600MHz semi stable  .

@nick name

I have a lot of faith in The Stilt, so if he approves it I would use it  . This is only my opinion. IIRC the app was developed on a Finnish forum and he may well have helped in beta testing, etc.

Another thing is, some don't check for post to post variation of training, which can lead to mixed results. I have seen first hand instances of where 1st run of x program passes and even a 2nd, but on 3rd or so it fails. Hence we could say an app is not giving reliable test results, where as the test methodology was at fault.

I use GSAT/HCI, you'll see earlier in this thread where I felt GSAT was better. Lack of experience made me come to this conclusion. As Silent Scone pointed out each has it's place. I use both now TBH. I use GSAT in Linux Mint as well as BASH on windows.


----------



## ajc9988

nick name said:


> I know everyone uses HCI MemTest (I just paid for pro also), but is anyone using the Stilt recommended Karhu RAM Test? I saw him recommended it in a post last December where he said it performed faster due to X86 programming so I bought it too. I am using it now and I just wanted to see if anyone uses it and has any best practices to share.


Each program tests in a different way. I personally do something similar to Gupsterg, which I will mention below.



CJMitsuki said:


> When RamTest first released I bought it and used it but after a few bios updates it seemed to become more and more inconsistent in its testing so I stopped using it. Not sure if it has received an update at all but if not then I don’t plan to use it again until it does. HCI was and still is the most consistent for me. Not to mention the extra test for running without the OS. If it gets an update I’ll try it again and see if the inconsistencies are gone.


Thank you for this insight, as I was on the fence about adding this to my regimen for stability testing. I will hold off on that then at the moment. 



gupsterg said:


> @ajc9988
> 
> I wouldn't read too much into AIDA64 bench swing on cache, etc TBH. Seen it swing so many times on Ryzen gen 1/2 and Threadripper for really no apparent reason. Again I've read some highlight they use it as a guide to stability, etc. I really can't say that I find that bench feasible in that context. IIRC when the bench is run it is given higher priority as process but it still can be affected by a background process.
> 
> 3466MHz is the best I've had out of my TR, 3533MHz attempts did not bare fruit for me, so is nice to see 3600MHz semi stable  .
> 
> @nick name
> 
> I have a lot of faith in The Stilt, so if he approves it I would use it  . This is only my opinion. IIRC the app was developed on a Finnish forum and he may well have helped in beta testing, etc.
> 
> Another thing is, some don't check for post to post variation of training, which can lead to mixed results. I have seen first hand instances of where 1st run of x program passes and even a 2nd, but on 3rd or so it fails. Hence we could say an app is not giving reliable test results, where as the test methodology was at fault.
> 
> I use GSAT/HCI, you'll see earlier in this thread where I felt GSAT was better. Lack of experience made me come to this conclusion. As Silent Scone pointed out each has it's place. I use both now TBH. I use GSAT in Linux Mint as well as BASH on windows.


With AIDA64, a drop in L3 Copy to 400 range I pay no mind to. I've seen that on fully stable and for the reasons you stated. Reason I brought up L3 read at 200 is I've never seen that, and as it turned out, HCI found errors which may be related to what caused that. Also, the L2 copy can vary by a couple hundred, from the high 1400s to the 1700s. So that one I also wouldn't worry about at all. Meanwhile, check out what I used to have on version 2.0 of the BIOS for the Taichi X399. I was one of the few to have 3600 rock stable on the old BIOSes. I'm happy more people are able to get their ram stable now at higher frequencies, but I am saddened that my performance comes as the cost (although the BIOS that is beta meant for AGESA 1.0.0.6 is a mess, and that other one has not been updated in light of more recent security vulnerabilities, which primarily effect Intel, but almost all chips have some issue with). 

https://d1ebmxcfh8bf9c.cloudfront.net/u112474/image_id_2015376.jpeg

On testing, you and I have a very similar method. I start with TM5. After it passes that (before the changes to the cfg file by 1usmus, I did 210 cycles but never saw an error past cycle 48 if it was going to fail that test), I then move onto HCI with a cold boot. Then, sometimes, I move to that on thumbdrive or onto two different runs, cold boots in between, with GSAT, much in the way you described, but also varying the testing parameters for different stressing of the SOC with it. This is why I set aside a long period of 2 weeks for validations. I really need to be sure that even though overclocked to high levels, there are not errors being spit out. I used to have memtest86+ from passmark in the mix, ran in parallel 4 passes to check for the bitflips with rowhammer. But, yes, we do very similar testing it seems as well.


----------



## gupsterg

Indeed that's very sweet result, especially accounting for further complexity of Threadripper. I have ref'd it before and linked it to others when discussions occurred  .

UEFI/AGESA do not only contain CPU Microcode updates, but can have IMC, SMU, etc firmware changes. So a particular UEFI could well be favourable to x setup and or HW combo. It is possible to place x module with y UEFI, I never looked into this but The Stilt did do some UEFIs along that way for C6H early on. Perhaps 1usmus knows how to, amount of time he has probably spent on Ryzen is bewildering IMO, besides dedication to his app, etc is monumental.


----------



## nick name

CJMitsuki said:


> When RamTest first released I bought it and used it but after a few bios updates it seemed to become more and more inconsistent in its testing so I stopped using it. Not sure if it has received an update at all but if not then I don’t plan to use it again until it does. HCI was and still is the most consistent for me. Not to mention the extra test for running without the OS. If it gets an update I’ll try it again and see if the inconsistencies are gone.


The version I just downloaded is 1.1.0.0 

Is that the same version you tested?


----------



## nick name

So I finally ran an all night test and I am pleased it came back error free. It was, however, with RAM Test and not with HCI which we have been discussing above. 

I am running BCLK 100.6 and 3600MHz so it clocks slightly above. My CPU itself seems weird with how it requests voltages with PE Level 3 versus Level 2. Watching the same frequencies with the same programs I notice that Level 2 will run at higher voltages than Level 3 and what I find is that I have to add an offset that I am uncomfortable with especially during single core performance runs. On top of that I get crashes when I venture too high in the BCLK pushing because I can't sort the voltages. And it was frustrating sorting through all that and not being able to find an offset that worked well and I was comfortable with so I gave up. 

But moving on the the RAM: here is the screenshot.


----------



## ajc9988

gupsterg said:


> Indeed that's very sweet result, especially accounting for further complexity of Threadripper. I have ref'd it before and linked it to others when discussions occurred  .
> 
> UEFI/AGESA do not only contain CPU Microcode updates, but can have IMC, SMU, etc firmware changes. So a particular UEFI could well be favourable to x setup and or HW combo. It is possible to place x module with y UEFI, I never looked into this but The Stilt did do some UEFIs along that way for C6H early on. Perhaps 1usmus knows how to, amount of time he has probably spent on Ryzen is bewildering IMO, besides dedication to his app, etc is monumental.


Yeah, I noticed that a bit when I was first building the platform and UEFI revisions were coming like rapid fire for a little while. But, I take on memory overclocking like a puzzle box. You have to work it until you get everything aligned, try different approaches to solve it, etc. So, I still am searching for the new settings that can allow 3600 to be stable with the newer UEFI, but always have the fallback of downflashing if needed. I only recently started reporting in more depth. Hell, before the AGESA 1.1.0.0, with my hardware, I could not quickly find a tight 3466 setting, but 3600 dialed in very easily without much effort on my part. Now, the roles are reversed. 

I might try my loose 3600 timings I seem to have gotten stable (16-17-17-34) on UEFI version 3.00, but that just seems underwhelming compared to the chase for tight timings that can beat my current 3466 timings. But, overall, this new UEFI has made me dig deeper into the settings to get better at searching for stable ram overclocks, so I don't mind the learning experience and gaining a deeper understanding of my hardware (overclocking is my hobby). But, so far I have gotten close on 14-15-14-14 and 14-17-17-17 (or 14-17-16-16, can't remember at the moment) timings with 3600. This means I am close and just need to chisel away. Last night was the first time I tried ProcODT of 48 and 60 that my machine didn't crap itself into bootloops, so I played with that a bit looking to find anything that could get me slightly closer (it didn't for 14-15-14-14, but might on the other timing set that I got close on). The game continues!

And I do agree, the amount of time 1usmus has spent on this is incredible! He also announced a red dram calculator today (version 1.40) that he plans on having out by the end of the month that includes Threadripper support. So very exciting things ahead.


----------



## nick name

ajc9988 said:


> Yeah, I noticed that a bit when I was first building the platform and UEFI revisions were coming like rapid fire for a little while. But, I take on memory overclocking like a puzzle box. You have to work it until you get everything aligned, try different approaches to solve it, etc. So, I still am searching for the new settings that can allow 3600 to be stable with the newer UEFI, but always have the fallback of downflashing if needed. I only recently started reporting in more depth. Hell, before the AGESA 1.1.0.0, with my hardware, I could not quickly find a tight 3466 setting, but 3600 dialed in very easily without much effort on my part. Now, the roles are reversed.
> 
> I might try my loose 3600 timings I seem to have gotten stable (16-17-17-34) on UEFI version 3.00, but that just seems underwhelming compared to the chase for tight timings that can beat my current 3466 timings. But, overall, this new UEFI has made me dig deeper into the settings to get better at searching for stable ram overclocks, so I don't mind the learning experience and gaining a deeper understanding of my hardware (overclocking is my hobby). But, so far I have gotten close on 14-15-14-14 and 14-17-17-17 (or 14-17-16-16, can't remember at the moment) timings with 3600. This means I am close and just need to chisel away. Last night was the first time I tried ProcODT of 48 and 60 that my machine didn't crap itself into bootloops, so I played with that a bit looking to find anything that could get me slightly closer (it didn't for 14-15-14-14, but might on the other timing set that I got close on). The game continues!
> 
> And I do agree, the amount of time 1usmus has spent on this is incredible! He also announced a red dram calculator today (version 1.40) that he plans on having out by the end of the month that includes Threadripper support. So very exciting things ahead.



Have you tried the timings that are stable for my 3600MHz clock yet? That might be a useful reference. I posted them a post or two before yours. I am using SOC 1.11250V with Auto LLC and DRAM 1.46V with a VTTDDR .750.


----------



## ajc9988

nick name said:


> Have you tried the timings that are stable for my 3600MHz clock yet? That might be a useful reference. I posted them a post or two before yours. I am using SOC 1.11250V with Auto LLC and DRAM 1.46V with a VTTDDR .750.


I have not, but planned on checking it out in the next day or so. For the SOC and DRAM voltage, I'll go with what the ram tells me, because I have not had to use that high a voltage except for when I was shooting for getting 3733 stable (which I plan on also trying if I get 3600 working again).


----------



## nick name

ajc9988 said:


> I have not, but planned on checking it out in the next day or so. For the SOC and DRAM voltage, I'll go with what the ram tells me, because I have not had to use that high a voltage except for when I was shooting for getting 3733 stable (which I plan on also trying if I get 3600 working again).


Yeah with the SOC I set it that high because it reports in HWiNFO as 1.086V~1.1V with Auto LLC. I've found it more reliable then trying to find a suitable LLC setting @ 1.1V. And I might be able to come down on the DRAM voltage, but I haven't tried yet.


----------



## ssateneth

is there anything particularly negative from doing an exhaustive search of rtt* resistance settings? trying every single combination on my 1950x and asrock taichi due to the new bios, hoping i can get faster ram setting working. The board has NEVER posted 3600 ram before, and the first thing i do is load 3600 XMP after loading P3.20 latest BIOS and it loaded windows to desktop (though not for long). so obviously there was stability improvements.

i was running 3333 ram 24/7. while 3600 seems like a stretch now, 3466 works sort of, 0.12 memtest throws occasional errors. sorry if this has been answered before, but what sliders should I be looking at? i've already loosened timings a ton, 18-20-20-39 2T, everything else XMP auto. I'm not afraid to set vdimm to 1.5. soc was fine at 1v with 3333. i have not messed with vddp_cldo or vddcr_soc_s5 but heard those sliders have a recommended range or direction to push them towards. what are their defaults? procodt only seems to work at 53.3 or 60, occasional POST beep error on 68.6. no POST on higher or lower

so any recommendations? i'd pay to get 3600 working 24/7


----------



## 1usmus

*3733CL14*

*Began testing the fast preset 3733CL14 (announcement)*



Spoiler


----------



## 1usmus

gupsterg said:


> Indeed that's very sweet result, especially accounting for further complexity of Threadripper. I have ref'd it before and linked it to others when discussions occurred  .
> 
> UEFI/AGESA do not only contain CPU Microcode updates, but can have IMC, SMU, etc firmware changes. So a particular UEFI could well be favourable to x setup and or HW combo. It is possible to place x module with y UEFI, I never looked into this but The Stilt did do some UEFIs along that way for C6H early on. Perhaps 1usmus knows how to, amount of time he has probably spent on Ryzen is bewildering IMO, besides dedication to his app, etc is monumental.


Stilt did not change anything, the bios with different PMU was provided by ASUS.
Update part of the bios at the moment there is no possibility, now in each biography contains at once 3 mini biographies for the processors ZEN. Free space is very small, checksum control is very difficult to comply with.

I want to say that the new AGESA 1.0.0.4 has great potential. Significantly changed the impedance of the line, optimized tertiary timings in the automatic mode and much more. Also, the management of the PBO scalar has been removed, possibly temporarily.


----------



## gupsterg

@nick name

Nice :thumb: .

@ssateneth

Playing with any single or multiple combinations of:-

i) ProcODT
ii) RTT
iii) CAD Bus timings/resistances

I have experienced zero adverse effects on HW. "Setup" will just not post if your way out. If "Setup" isn't far out then you'll have post but may encounter instability in testing. Once right post/stability in testing will not be an issue, unless of course voltages, etc are at fault.

Recently on the ZE with latest UEFI as that has more RAM MHz setting without need for BCLK change I opted of 3400MHz. This allowed me to use VDIMM 1.35V. I'm using The Stilt 3466MHz timings preset.









Above is without any tweaks OS and or "Performance Bias" and CPU stock. I have been reruning tests in WinOS/Linux nearly 2 days now and no issues.









Usually my CPU needs SOC: 1.025V for 3200MHz The Stilt preset with couple of timings lowered by myself, I can use VDIMM: 1.35V. The 3400MHz above again is "play'n'play" on my HW, SOC: 1.05V VDIMM: 1.35V, ProcODT [Auto] (53), RTT Off Off 48, all CAD timings/resistances [Auto] (ie 0 0 0 24 24 24 24). I have had 3466MHz on several past UEFIs, but wanted to try 3400MHz. Plan on seeing if I can maintain VDIMM: 1.35V and lower any timings.

@1usmus

Pretty sure the C6H/ZE modified UEFIs were The Stilt's doing, he has the ability to sign UEFIs.


----------



## 1usmus

@gupsterg

You are very naive, you should not believe me or Stilt (his words are not all true and mine, too)
You are an experienced tester, you can find your own way and have your own opinion 

This thread needs independent people who were not bribed by a motherboard or someone else's opinion


----------



## mtrai

Calm down y'all..we all have our own opinions on Ryzen Overclock. No one is 100% accurate nor is anyone 100% wrong. Further people do have to admit the presets built into the BIOS are for several different boards so are just starting points...same the Calculator tool...just a starting point. I Have not actually used the presets...or calculator in a long time...but i have noticed as it has evolved the 3600 Sammy B-die settings have to be almost an exact match of my original 3600 settings that took me months to get to...where as the bios memory presets have not changes as far as I know from day 1.

Take how anyone looks at overclocking and you have to work it into how YOU overclock. Also you have to account not just for your memory, but your CPU, and motherboard. Yes even the same motherboards can behave differently. And there you have to consider someone PSU, GPU and even Hard Drives can also affect how you can overclock.

So please let not clash. I have gotten valuable information from both @1usmus and @gupsterg And I hope I have contributed a little bit as well.

The reason I have been so quiet is I got my ram stable at 3600 quite a while back and my PBO2 XFR 2 boosts are outstanding...so I not really bothered with more.... all core boosts to 4300 and single up to 4 cores will do 4425. There really is not much left for me to do until a new bios comes out.

And I have been spending a lot of time with my new Vega 64 Powercolor Red Devil and setting it up. It is yet a different beast then my 2 RX 580s. Overclocking and undervolting it is just weird.
@gupsterg what modified bios are you talking about that stilt did? I am interested in seeing them.


----------



## gupsterg

No clashing here :thumb: . As stated a few posts back I have respect for 1usmus  . I think due to English not being 1usmus first language his post could be taken differently then what he may really mean. He has his opinion, which he is entitled to and I have mine, which I can respect and I believe he does mine as well.

The C6H ones are linked in the Ryzen Essential OP, but due to forum change the links may not work. If you require them PM and will send you  .


----------



## mtrai

gupsterg said:


> No clashing here :thumb: . As stated a few posts back I have respect for 1usmus  . I think due to English not being 1usmus first language his post could be taken differently then what he may really mean. He has his opinion, which he is entitled to and I have mine, which I can respect and I believe he does mine as well.
> 
> The C6H ones are linked in the Ryzen Essential OP, but due to forum change the links may not work. If you require them PM and will send you  .


Please do...I want to take a look at them. As I, and a few others like 1usmus are the only ones who will mod the bios but I did not know of any modified stilts bios. Incidentally, you were a great help to me a number of years ago when I made the jump from my AMD FX 8120 to Skylake I5 6600k. Currently I am seriously fighting a war with my vega 64 as sometimes it just wants to exceed the max core clock to boost up to 1850 and or course crashes since it is not getting enough voltage or just can't do 1850 haha but think its can...but I can't push it that high since I am air.


----------



## 1usmus

I do not swear, I love @gupsterg

I really consider him an excellent tester and that he can find more options for stability of the system, the main thing is not to listen to anyone and experiment


----------



## ajc9988

nick name said:


> Yeah with the SOC I set it that high because it reports in HWiNFO as 1.086V~1.1V with Auto LLC. I've found it more reliable then trying to find a suitable LLC setting @ 1.1V. And I might be able to come down on the DRAM voltage, but I haven't tried yet.


Tried them. Failed. But, it led me to playing with 14-15-13-13 tight which I couldn't fully get stable on 3466, but that gave me a 3545 CB15 score and 103.5GBps AIDA64 read. Another WIP.



1usmus said:


> Stilt did not change anything, the bios with different PMU was provided by ASUS.
> Update part of the bios at the moment there is no possibility, now in each biography contains at once 3 mini biographies for the processors ZEN. Free space is very small, checksum control is very difficult to comply with.
> 
> I want to say that the new AGESA 1.0.0.4 has great potential. Significantly changed the impedance of the line, optimized tertiary timings in the automatic mode and much more. Also, the management of the PBO scalar has been removed, possibly temporarily.


I was wondering if you have tooled around with any Asrock BIOSes? I saw you mention somewhere that they are constantly putting out internal ones and that they are a mess. I'm not a coder, needless to say a firmware coder, but noticed they are the one company out of the big four that don't have one (not to deride biostar, but high end boards haven't really been put out by them in a long time).



1usmus said:


> @gupsterg
> 
> You are very naive, you should not believe me or Stilt (his words are not all true and mine, too)
> You are an experienced tester, you can find your own way and have your own opinion
> 
> This thread needs independent people who were not bribed by a motherboard or someone else's opinion


This is how I feel. Take the advice and information, give it a try, but play around and see what you come out with. That gives more data points and may give a different way to arrive at the same or similar conclusion (here, talking about stable clocks on ram). Old saying of more than one way to skin a cat sort of thing.



gupsterg said:


> No clashing here :thumb: . As stated a few posts back I have respect for 1usmus  . I think due to English not being 1usmus first language his post could be taken differently then what he may really mean. He has his opinion, which he is entitled to and I have mine, which I can respect and I believe he does mine as well.
> 
> The C6H ones are linked in the Ryzen Essential OP, but due to forum change the links may not work. If you require them PM and will send you  .





1usmus said:


> I do not swear, I love @gupsterg
> 
> I really consider him an excellent tester and that he can find more options for stability of the system, the main thing is not to listen to anyone and experiment


I do cuss and I remember you asking me not to in one of our first encounters. Since then, I'd like to think that interactions have gotten better between us. But, for anyone reading this, even if I cuss or am passionate or use strong language, I'd like to apologize upfront, it is my personality. Once you get past that, I'm actually fairly reasonable and even pleasant. I do want to apologize if anyone got the wrong end of the stick, so to speak, and I have rubbed anyone the wrong way (I'm sure I have to someone, somewhere, at some time). 

With that said, I do find the conversations had here to be stimulating and productive and thank you all for the great discourse.


----------



## MrPhilo

With 3533CL14 Tight Timing I can get past 2500% Memtest with 10 x 850 with no errors at Level 2 (Perf. Enhancer) which is stuck at 4.15Ghz at 1.43V when using memtest (Temp on CPU average is 60 as reported by HWInfo, highest was 71c)

I since have overclocked to 4.25Ghz (1.4v) and using the same timing it fails around 400%. (Temp on CPU average is 58 as reported by HWInfo, highest was 66c)

I decided to clock my CPU to 4.15Ghz (1.3v) and I have so far gone past 1800% in Memtest

It's weird but I guess the extra stress and power on the CPU (even though it's using less volts) is also impacting the CPU IMC?


----------



## tekjunkie28

MrPhilo said:


> With 3533CL14 Tight Timing I can get past 2500% Memtest with 10 x 850 with no errors at Level 2 (Perf. Enhancer) which is stuck at 4.15Ghz at 1.43V when using memtest (Temp on CPU average is 60 as reported by HWInfo, highest was 71c)
> 
> I since have overclocked to 4.25Ghz (1.4v) and using the same timing it fails around 400%. (Temp on CPU average is 58 as reported by HWInfo, highest was 66c)
> 
> I decided to clock my CPU to 4.15Ghz (1.3v) and I have so far gone past 1800% in Memtest
> 
> It's weird but I guess the extra stress and power on the CPU (even though it's using less volts) is also impacting the CPU IMC?


Yup and it's like this for every processor I've had with an IMC. I almost miss having my northbrige chipsets.

Sent from my SM-N950U using Tapatalk


----------



## ajc9988

MrPhilo said:


> With 3533CL14 Tight Timing I can get past 2500% Memtest with 10 x 850 with no errors at Level 2 (Perf. Enhancer) which is stuck at 4.15Ghz at 1.43V when using memtest (Temp on CPU average is 60 as reported by HWInfo, highest was 71c)
> 
> I since have overclocked to 4.25Ghz (1.4v) and using the same timing it fails around 400%. (Temp on CPU average is 58 as reported by HWInfo, highest was 66c)
> 
> I decided to clock my CPU to 4.15Ghz (1.3v) and I have so far gone past 1800% in Memtest
> 
> It's weird but I guess the extra stress and power on the CPU (even though it's using less volts) is also impacting the CPU IMC?


Here is some info from 1usmus.https://www.overclock.net/forum/26902089-post1334.html

Speaking of which, @1usmus, do you have a list of errors that correlate with more likely timings? I don't even know if that is possible, but wanted to ask because all information, even if not true in all situations, can help on my hunting and pecking. Thank you.


----------



## CJMitsuki

MrPhilo said:


> With 3533CL14 Tight Timing I can get past 2500% Memtest with 10 x 850 with no errors at Level 2 (Perf. Enhancer) which is stuck at 4.15Ghz at 1.43V when using memtest (Temp on CPU average is 60 as reported by HWInfo, highest was 71c)
> 
> I since have overclocked to 4.25Ghz (1.4v) and using the same timing it fails around 400%. (Temp on CPU average is 58 as reported by HWInfo, highest was 66c)
> 
> I decided to clock my CPU to 4.15Ghz (1.3v) and I have so far gone past 1800% in Memtest
> 
> It's weird but I guess the extra stress and power on the CPU (even though it's using less volts) is also impacting the CPU IMC?


It could mean that 4.25ghz needs more than 1.4v and your cpu is unstable which will lead to memory errors. The IMC is part of the cpu so the cpu must remain stable for the memory to be stable. I would say that it isn’t a bad thing at all since it lets you know that your cpu isn’t stable at that particular voltage/frequency. I’d bet that if you added a bit more vCore it would stabilize.


----------



## Blackbox30

Ryzen 5 2600, MSI B350 Tomahawk, 16gb G Skill Ripjaws V 3200. Corsair h100i v2, corsair CXm750, Asus Dual GTX 1060 6gb. Running OC @ 4.2 ghz. vcore is 1.369v. Dram is 3200 with 1.232v. And soC is 1.056v. Avg temp is 44.2c. Mobo is 43.8c. Mem clock says 1,598.06 Mhz ???. Everything seems stable. Ran cpuz bench and stress test. Any suggestions?


----------



## nick name

Blackbox30 said:


> Ryzen 5 2600, MSI B350 Tomahawk, 16gb G Skill Ripjaws V 3200. Corsair h100i v2, corsair CXm750, Asus Dual GTX 1060 6gb. Running OC @ 4.2 ghz. vcore is 1.369v. Dram is 3200 with 1.232v. And soC is 1.056v. Avg temp is 44.2c. Mobo is 43.8c. Mem clock says 1,598.06 Mhz ???. Everything seems stable. Ran cpuz bench and stress test. Any suggestions?


DDR is double data rate so take the mem clock and multiply by 2 and you get your 3200MHz.


----------



## setesetesete

hey guys,

Im trying to improve my memory oc, despite being two different modules they run at 3000mhz 1.35v and give no errors in memtest (12 hrs). One is a hynix m-die single rank and the other a micron a-die double rank both 2400mhz xmp. running GDM off, PDM off, Bankgroupswap off and 1T.

https://imgur.com/s1EkRYu

https://imgur.com/Fhqmu4f

https://imgur.com/ztiTkK8

another question is memory intervealing. using numa vs uma mode. i cant find any information on that. i already tried numa (channel) and i think it give less stutter in games like pubg, but could be placebo.

thanks


----------



## clackersx

[email protected] (PE LVL2) 1822SUS---3466MHz-C14-14-14-28-1T---1.41v---SOC 1.0v---Asus C7H ---BIOS 0804---HCI---9374%/56 Hours

AIDA---54878R---53664W---51300C---61.7ns

https://valid.x86.fr/aq7kt4

2700X
Asus Crosshair VII Hero Wifi
GSKILL F4-3200C14-8GFX


----------



## seansplayin

oops


----------



## seansplayin

1usmus said:


> *Began testing the fast preset 3733CL14 (announcement)*
> 
> 
> 
> Spoiler


dude that's awesome, if you can get 3733 stable and use those timing, OMG that'd be huge. I'm running pretty close to those timings but I'm only at 3533. thank you for all your hard work, we all benefit

Since I took the screen shot below I moved the Procodt up to 53 and lowered the tRFC to 333. In Ubuntu right now or I'd take an update one



Spoiler


----------



## 1usmus

ajc9988 said:


> Here is some info from 1usmus.https://www.overclock.net/forum/26902089-post1334.html
> 
> Speaking of which, @1usmus, do you have a list of errors that correlate with more likely timings? I don't even know if that is possible, but wanted to ask because all information, even if not true in all situations, can help on my hunting and pecking. Thank you.


I stopped using HCI because of weak tests and therefore I can not provide the decryption for errors. I can only provide a list of timings, which in my opinion can stabilize the system.



seansplayin said:


> dude that's awesome, if you can get 3733 stable and use those timing, OMG that'd be huge. I'm running pretty close to those timings but I'm only at 3533. thank you for all your hard work, we all benefit
> 
> Since I took the screen shot below I moved the Procodt up to 53 and lowered the tRFC to 333. In Ubuntu right now or I'd take an update one
> 
> 
> 
> Spoiler


You have a good result
You do not need to chase the frequency, I think 3533cl13 not worse than 3666cl14


----------



## nick name

1usmus said:


> I stopped using HCI because of weak tests and therefore I can not provide the decryption for errors. I can only provide a list of timings, which in my opinion can stabilize the system.
> 
> 
> 
> You have a good result
> You do not need to chase the frequency, I think 3533cl13 not worse than 3666cl14


What are you using to test memory now?

And my latency @3636MHzCL14 is the same as 3533CL13, but with more bandwidth. And I couldn't get 3533MHzCL13 stable. Am I qualifying my speeds wrong by using AIDA64?


----------



## ajc9988

nick name said:


> What are you using to test memory now?
> 
> And my latency @3636MHzCL14 is the same as 3533CL13, but with more bandwidth. And I couldn't get 3533MHzCL13 stable. Am I qualifying my speeds wrong by using AIDA64?


That is a fine way to qualify it. That is peak. Sisoft Sandra is more avg if you want to use that method.


----------



## CJMitsuki

ajc9988 said:


> That is a fine way to qualify it. That is peak. Sisoft Sandra is more avg if you want to use that method.


Actually you dont want to ever use Aida64 to qualify your speed at all. It’s information is misleading more often than not. You can have amazing numbers in Aida64 even without optimal subtimings. your subtimings play a massive role in performance and even with good numbers in Aida64 that particular setup can run slow. I use Aida64 for what it is, only numbers to show you possible performance of a given setup. Those numbers do not correlate to actual performance. The best way I’ve found to judge ram performance is running rendering benchmarks and gaming benchmarks and recently been looking at TestMem 5 cycle times as long as the same amount of memory is used for each test then in theory a faster cycle time should mean faster ram for the particular instruction sets TM5 uses at least. Cpu frequency didn’t seem to have any efffect at all on cycle times so it seems to be a solid way to assess performance for now. In no way, shape, or form is Aida64 to be regarded as a qualifier of actual ram performance. It’s a good base to use to see if your setup has potential, nothing more.


----------



## ajc9988

CJMitsuki said:


> Actually you dont want to ever use Aida64 to qualify your speed at all. It’s information is misleading more often than not. You can have amazing numbers in Aida64 even without optimal subtimings. your subtimings play a massive role in performance and even with good numbers in Aida64 that particular setup can run slow. I use Aida64 for what it is, only numbers to show you possible performance of a given setup. Those numbers do not correlate to actual performance. The best way I’ve found to judge ram performance is running rendering benchmarks and gaming benchmarks and recently been looking at TestMem 5 cycle times as long as the same amount of memory is used for each test then in theory a faster cycle time should mean faster ram for the particular instruction sets TM5 uses at least. Cpu frequency didn’t seem to have any efffect at all on cycle times so it seems to be a solid way to assess performance for now. In no way, shape, or form is Aida64 to be regarded as a qualifier of actual ram performance. It’s a good base to use to see if your setup has potential, nothing more.


You do understand the word "peak" right, and that I said it can be used for peak. Now, you bring up a good point, that peak means very little in the way of overall performance, as sustained has a much larger impact as it is what the ram performs at regularly. 

Here is my sisoft Sandra memory bandwidth score: http://ranker.sisoftware.net/show_r...e4ddeed7e0d9e8cebc81b197f297aa9abccff2c2&l=en
Overall memory score: http://ranker.sisoftware.net/show_run.php?q=c2ffc8ffd9b8d9e4d2e6dee9cfbd80b096f396ab9bbdcef3c3&l=en
Data cache and memory latencies: http://ranker.sisoftware.net/show_r...e6d2e7d6e4d3e1c7b588b89efb9ea393b5c6fbcb&l=en

TM5 also has its limits on that front. This is why I use multiple benchmarks when qualifying my machine, because each has its own place. Peak is worth knowing, sustained is worth knowing, effect on processing is worth knowing, etc. Now, I believe it is superpi that is really ram sensitive (so can be used for tuning). I use CB15 for a little bit of tuning and to check for performance regressions (it runs really fast on a 1950X, which makes that easier, but ram won't drastically increase your score, timings can tweak it, and after you get used to using it, it should give fairly repeatable results so long as something doesn't kick on working in the background, you allow the temps to return to normal before the next run, etc.). 

Then my friend mentioned a couple games can be memory sensitive, such as killing floor 2 and frostbite games, generally. I haven't used games personally, but may be worth a gander as another measure. 

So, it really depends what is meant by qualify. If you mean checking peak, sure, it can work. But I don't believe in using only one program to qualify ram. MaxxMem2 was good during DDR3, but is practically broken for DDR4, it seems. If I missed anything, please let me know.

Edit: Also, someone mentioned blender previously for checking that. You'd want to use the same image and have it be short completion time to where you can run it between tweaks to see. If doing it as a larger qualifier in between say a slow, fast, or extreme settings that are qualified as stable from other tests, like HCI, GSAT, TM5, RamTest, or whatever your poison may be, then maybe running a longer one like gooseberry or the pavillion or class room. Just as a thought.


----------



## MrPhilo

clackersx said:


> [email protected] (PE LVL2) 1822SUS---3466MHz-C14-14-14-28-1T---1.41v---SOC 1.0v---Asus C7H ---BIOS 0804---HCI---9374%/56 Hours
> 
> AIDA---54878R---53664W---51300C---61.7ns
> 
> https://valid.x86.fr/aq7kt4
> 
> 2700X
> Asus Crosshair VII Hero Wifi
> GSKILL F4-3200C14-8GFX


What's your digi settings


----------



## CJMitsuki

ajc9988 said:


> You do understand the word "peak" right, and that I said it can be used for peak. Now, you bring up a good point, that peak means very little in the way of overall performance, as sustained has a much larger impact as it is what the ram performs at regularly.
> 
> Here is my sisoft Sandra memory bandwidth score: http://ranker.sisoftware.net/show_r...e4ddeed7e0d9e8cebc81b197f297aa9abccff2c2&l=en
> Overall memory score: http://ranker.sisoftware.net/show_run.php?q=c2ffc8ffd9b8d9e4d2e6dee9cfbd80b096f396ab9bbdcef3c3&l=en
> Data cache and memory latencies: http://ranker.sisoftware.net/show_r...e6d2e7d6e4d3e1c7b588b89efb9ea393b5c6fbcb&l=en
> 
> TM5 also has its limits on that front. This is why I use multiple benchmarks when qualifying my machine, because each has its own place. Peak is worth knowing, sustained is worth knowing, effect on processing is worth knowing, etc. Now, I believe it is superpi that is really ram sensitive (so can be used for tuning). I use CB15 for a little bit of tuning and to check for performance regressions (it runs really fast on a 1950X, which makes that easier, but ram won't drastically increase your score, timings can tweak it, and after you get used to using it, it should give fairly repeatable results so long as something doesn't kick on working in the background, you allow the temps to return to normal before the next run, etc.).
> 
> Then my friend mentioned a couple games can be memory sensitive, such as killing floor 2 and frostbite games, generally. I haven't used games personally, but may be worth a gander as another measure.
> 
> So, it really depends what is meant by qualify. If you mean checking peak, sure, it can work. But I don't believe in using only one program to qualify ram. MaxxMem2 was good during DDR3, but is practically broken for DDR4, it seems. If I missed anything, please let me know.
> 
> Edit: Also, someone mentioned blender previously for checking that. You'd want to use the same image and have it be short completion time to where you can run it between tweaks to see. If doing it as a larger qualifier in between say a slow, fast, or extreme settings that are qualified as stable from other tests, like HCI, GSAT, TM5, RamTest, or whatever your poison may be, then maybe running a longer one like gooseberry or the pavillion or class room. Just as a thought.


I’ll just keep this my only answer to you due to the condescending tone I see in most of the posts on here or HWBOT when others are in disagreement with you. 
Aida64 is never to be trusted in any light and even what it tells you as peak is to be taken with a grain of salt. I can input timings that barely boot and throw massive errors but Aida64 will show great bandwidth numbers and I’ve even seen the program show good latency from an error ridden setup. Not sure how that’s possible with the amount of errors but that’s why I don’t really trust Aida64. As far as games are concerned, if you use your rig for gaming then that’s what you want to use to qualify your memory performance. If you use it as a rendering workstation then use those benchmarks. If you overclock for fun then you’ll use everything and have multiple setups. SuperPi is really good to test memory performance but optimizing for SuperPi doesn’t necessarily mean you will have the best setup for gaming. Compare apples to apples because there is no one benchmark that can tell you that. If you use Aida64 then use it after you have determined stability and performance with everything else and if the numbers look good in Aida then cool, if not, don’t even worry about it. It’s just not a trustworthy program when determining real performance and very questionable when determining peak performance. 
Don’t take this as an attack on your opinion. Forums are for discussion, no need to get bothered if someone disagrees with you :thumb:


----------



## ajc9988

CJMitsuki said:


> I’ll just keep this my only answer to you due to the condescending tone I see in most of the posts on here or HWBOT when others are in disagreement with you.
> Aida64 is never to be trusted in any light and even what it tells you as peak is to be taken with a grain of salt. I can input timings that barely boot and throw massive errors but Aida64 will show great bandwidth numbers and I’ve even seen the program show good latency from an error ridden setup. Not sure how that’s possible with the amount of errors but that’s why I don’t really trust Aida64. As far as games are concerned, if you use your rig for gaming then that’s what you want to use to qualify your memory performance. If you use it as a rendering workstation then use those benchmarks. If you overclock for fun then you’ll use everything and have multiple setups. SuperPi is really good to test memory performance but optimizing for SuperPi doesn’t necessarily mean you will have the best setup for gaming. Compare apples to apples because there is no one benchmark that can tell you that. If you use Aida64 then use it after you have determined stability and performance with everything else and if the numbers look good in Aida then cool, if not, don’t even worry about it. It’s just not a trustworthy program when determining real performance and very questionable when determining peak performance.
> Don’t take this as an attack on your opinion. Forums are for discussion, no need to get bothered if someone disagrees with you :thumb:


I actually agree with everything you just said there. And I've seen the same thing with error prone memory timings returning high results in AIDA. I don't see that as the problem and do agree that it should never be taken as stable just because it passes AIDA64 mem benchmark. That would be silly. In fact, there is a chance that the errors thrown cause the erroneous peak bandwidth number itself. 

And I agree, it isn't the be all, end all on performance at all. And getting a peak score in it may be a detriment to your workload, as you said. But, if all you are looking for is the highest peak, so long as you have done stability testing, then I do not see it as a problem. 

As to the condescension in my tone, that is naturally the way I speak. In part, it is due to my education and formal training in writing where assertive statements are part of the job. And that does reflect in my personality. Believe it or not, give pushback. If you show me that I am either wrong (with facts) or present new information, you will be surprised at me incorporating new information. 

Now, your description does give context to my prior statements on how to check the ram's function, and adds to it due to that context. You previously gave one way of checking, which is testmem5 cycle to completion times. That, too, in light of your statement, also gives the context in which that performance metric should be taken, as even that may not be optimal depending on workload. But, overall, we agree the best qualification is done testing the workloads on which the machine will primarily be tasked.

Edit: Also, it didn't ask best practices, it asked generally, and qualification always, necessarily, depends on goals.

Edit 2: Also, even though you see me as condescending, neither of us got to saying to qualify on the type of workloads done on the machine until we had the back and forth, building on each other. You said one thing, I said another, then examples were given, but the best advice of qualifying on the type of workload done came AFTER all of that information. So, even though you see me as aggressive and combative in tone and condescending in demeanor, we still got to the best advice through our interaction. That is what it is all about, working with each other to get to the answer.


----------



## Leftezog

Is it wrong to run HCI memtest in safe mode?


----------



## clackersx

MrPhilo said:


> What's your digi settings


Everything auto/default except current limits maxed out and 1.41V ram boot.


----------



## MGeaR356

Question ppl, I have a gigabyte gaming 7 X470 with 2600x my ram is a corsair b die 3600 c18

My ram voltage settings for stability for 3400MHZ 14-14-14-22 is at 1.51v. Is it too high? Anything lower will have prime 95 blend test error within 20mins


----------



## x58haze

Day 323 still without know what chipset are my pair of ram 

Dunno if Samsung B die or D/Die or Hynyx or idk.

Patriot 2x4 GB PV48G320C6K (11D1) 3200 mhz (under QVL of my motherboard b350 fatality k4 gamming)

Even patriot support says that they cannot guarantee what type of chipset are cause they work with many manufacturer <-- very unprofessional...

What make me sad is that i cannot use properly 1usmus ram calculator cause i dont know what is my chipset also asked via twitter to Viper patriot and via gmail, and they didn't know like hey sorry we dont know and blah blah u.u

and yes tried thaiphon burner and still without reading.. what chipset


----------



## ssateneth

x58haze said:


> Day 323 still without know what chipset are my pair of ram
> 
> Dunno if Samsung B die or D/Die or Hynyx or idk.
> 
> Patriot 2x4 GB PV48G320C6K (11D1) 3200 mhz (under QVL of my motherboard b350 fatality k4 gamming)
> 
> Even patriot support says that they cannot guarantee what type of chipset are cause they work with many manufacturer <-- very unprofessional...
> 
> What make me sad is that i cannot use properly 1usmus ram calculator cause i dont know what is my chipset also asked via twitter to Viper patriot and via gmail, and they didn't know like hey sorry we dont know and blah blah u.u
> 
> and yes tried thaiphon burner and still without reading.. what chipset



take off the heatspreader and physically look at the chips, or take an in-focus picture of one of the chips and post it here. you wouldve known in hours then.


----------



## tekjunkie28

x58haze said:


> Day 323 still without know what chipset are my pair of ram
> 
> Dunno if Samsung B die or D/Die or Hynyx or idk.
> 
> Patriot 2x4 GB PV48G320C6K (11D1) 3200 mhz (under QVL of my motherboard b350 fatality k4 gamming)
> 
> Even patriot support says that they cannot guarantee what type of chipset are cause they work with many manufacturer <-- very unprofessional...
> 
> What make me sad is that i cannot use properly 1usmus ram calculator cause i dont know what is my chipset also asked via twitter to Viper patriot and via gmail, and they didn't know like hey sorry we dont know and blah blah u.u
> 
> and yes tried thaiphon burner and still without reading.. what chipset


That looks like Hynix all the way. Huge difference. I never seen b die run at those timings xmp.

Sent from my SM-N950U using Tapatalk


----------



## hsn

1usmus said:


> I stopped using HCI because of weak tests and therefore I can not provide the decryption for errors. I can only provide a list of timings, which in my opinion can stabilize the system


Thank you for yout utility
my mobo just flash to new agesa 1.0.0.4

i have agood result

dram 1.42v
soc 1.1


----------



## tekjunkie28

What does AGESA 1.0.0.4 actually change or improve? 

Sent from my SM-N950U using Tapatalk


----------



## x58haze

ssateneth said:


> take off the heatspreader and physically look at the chips, or take an in-focus picture of one of the chips and post it here. you wouldve known in hours then.


But man i'm not that tech to remove the heatspreader, i don't have the tools to put the heatspreader back, don't have the special glu and so on 
Theres is not way to check the chipset on my rams without removing heatspreader? like with focus with camera as you describe?


----------



## x58haze

tekjunkie28 said:


> That looks like Hynix all the way. Huge difference. I never seen b die run at those timings xmp.
> 
> Sent from my SM-N950U using Tapatalk


but what type of Hynix MFR, AFR, CFR? 

i hit Hynix MFR set safe preset


----------



## x58haze

See also the D-Die ranks shows timings of 16/18/18 guessing is very boring and cause problems in my pc, like the steam windows reminds open when close sometimes tyring to use the D-die on calculate safe... 

And yeah i have an asrock b350 fatality k4 gaming, SOC voltages are not in the bios, but on ryzen master tool.
But the problem here is that i wanted to know what type of chipset do i have, to properly use 1usmus calculator

Also in that Advance tab of 1usmus, ther are dram options that doesnt seems to appear in my bios, probably have different names .....
Things such VTTDR voltages min,max DRAM r1 r4 tune super/io clock chew
anyway aff Sorry for 3 comments in a row.


----------



## nick name

Leftezog said:


> Is it wrong to run HCI memtest in safe mode?


I wouldn't think so. In fact it should allow you to test more memory than during a normal boot into Windows. Some people test outside of the OS for exactly that reason.


----------



## Darkstalker420

@x58haze

Can't you use thiphon burner (sp? not sure but the SPD reading tool) to read the memory settings then add them in "custom" in 1usmus's calculator?

Thanx.


----------



## x58haze

Darkstalker420 said:


> @x58haze
> 
> Can't you use thiphon burner (sp? not sure but the SPD reading tool) to read the memory settings then add them in "custom" in 1usmus's calculator?
> 
> Thanx.


I dont know what you mean but this what i got when reading SPD
and then going into tools xmp enhancer. 

Also whats the point of add custon things to 1usmus, which i just simple know what are my chipset ram :'( i'm not buying anymore from Viper. also sad cause i cannot buy anything right now here in Venezuela yesterday salary was 5.000.000 now is 180.000.000 3000% of upgrade now inflation will be more add 9000% cause current inflation is 1.000.000% now with those salary increase 3000% people will tear blood even more, another sad thing is that i buy example a motherboard in usa 200$ when receiving here goverment will say hey no no, pay me 200$ 
and we dont get paid in dollars x.x


----------



## Leftezog

nick name said:


> I wouldn't think so. In fact it should allow you to test more memory than during a normal boot into Windows. Some people test outside of the OS for exactly that reason.


Thanks for your answer man. I will continue running HCI in safe mode for the obvious reason you told. More memory free to test.


----------



## Valka814

How much difference can be from a bootable dram voltage to a stabel one?


----------



## Trender

Hey guys, 1 of my RAM stick just broken, theyre 2 weeks lul. (3600 gskill tridentz rgb). I've used 1.45V and it came 1.35v on their profile but I've read that 1.45V was safe.
So did I broke the RAM stick with so many voltage or maybe it was just bad luck and faulty?


Valka814 said:


> How much difference can be from a bootable dram voltage to a stabel one?


I'd say 0.05V


----------



## miklkit

@x58haze This is Thaiphoon Burner. Thaiphoon Burner - Official Support Website


This is my Samsung E-die:


----------



## MGeaR356

I am on 1.5v.. Not too sure if it's too high for my b die rams


----------



## x58haze

miklkit said:


> @x58haze This is Thaiphoon Burner. Thaiphoon Burner - Official Support Website
> 
> 
> This is my Samsung E-die:


Yeah my friend i used thaiphon burner too  but chipset not recognize i use the free version, are you using a paid version?

Sadly this pair of rams not everyone has , probably i made a mistake in 2017 buying? 2x4 8gigas of ram 2 dimm single rank, for 60$? to cheap?


----------



## miklkit

I have the free version. I can't blame you for going cheap but with Ryzen the better the ram is, the better the cpu runs.


----------



## x58haze

miklkit said:


> I have the free version. I can't blame you for going cheap but with Ryzen the better the ram is, the better the cpu runs.


Also i have a motherboard mid range b350 chipset fatality k4 gaming, which doesn't came with Calibration voltages for optimal overclock... and yep :c
Also i found that amd ryzen seems to have poor IPC when playing single core games u.u 

But the thing with intel is that their motherboard socket if you dont be careful you can bent cpu sockets and while amd their cpu have the pins and not direct from the motherboard.


----------



## tekjunkie28

x58haze said:


> Also i have a motherboard mid range b350 chipset fatality k4 gaming, which doesn't came with Calibration voltages for optimal overclock... and yep :c
> Also i found that amd ryzen seems to have poor IPC when playing single core games u.u
> 
> But the thing with intel is that their motherboard socket if you dont be careful you can bent cpu sockets and while amd their cpu have the pins and not direct from the motherboard.


Yea the IPC isnt as high as Intels. This is well known but at the same time most games I have ran across dont need ultra high FPS. The one game that's is severely single threaded is WoW.

Sent from my SM-N950U using Tapatalk


----------



## miklkit

Saying the IPC isn't as high as some doesn't mean it is slow.


----------



## mongoled

Guys, would like some advice!

Ive been through two MSI X370 Titaniums and 3 Ryzen CPUs (2x1600x and 2600x)

But still I cannot get my memory stable at anything higher than 3200mhz (my sig says 3333mhz, but its not 100% prime95 stable).

I have put hours and €€€ into this and have gotten nowhere over a period of 11 months.

I have not changed the memory which is G.SKILL F4-3600C15D-16GTZ.

Now here is when it gets weird, when I attempt to push past 3200mhz, lets say 3333mhz, increasing the voltage from 1.35v results in less stability!

Ive tried momentarily up to 1.5v and prime95 fails almost instantly, but if I run 1.35v it will through a few iterations etc etc.

So my predicament is as follows, im pretty sure its the MSI motherboard, but the reality is I should try another set of RAM first, so im looking at these G.SKILL F4-3200C14D-16GFX.

Would like to hear peoples opinions if they believe its the memory or the motherboard.

And yes, ive used 1usmus very helpful application, along with the Stilt's timing etc etc, but anything over 3200mhz is a no go when testing with prime95 (custom FFT 192, 14000mb )


----------



## LillysTittchen

Hey,
can someone explain me, why MemTest Pro achieves 8000% coverage without errors and after reboot it throws instantly errors? My Bios settings:

Memory Frequency: 3533 MHz
DRAM Voltage: 1.48 V
DRAM VPP: 2.52 V
Vcore: Auto
CLD0_VDDP: Auto
DRAM VREF ChA: Auto
DRAM VREF ChB: Auto

That are all adjustable voltages.

Timings: CL18-19-19-39
SubTimings: All Auto
GearDownMode: Disabled
PowerDown enabled: Disabled
BankGroupSwap: Enabled
ProcODT: 53,3
RttNom: 34,3
RttPark: 48
AddrCmdDrvStr, CsOdtDrvStr, CKEDrvStr, CLKDrvStr: 24, 24, 24, 24

There are more settings that may effect ram stability, i.e. CPU NB/SoC Switching Frequency, CPU NB/SoC LLC, Precision Boost, Opcache Control...

It's really weird. Just a simple reboot and the system isn't stable anymore??!! How can this be. There must be a voltage or setting, that changes by restarting the system, I don't have another explanation. Thats why I started to set most of the bios options istead of leaving it on Auto.

Btw: No Core oc done, just ram oc.


----------



## jclafi

Ryzen w/ Poor IPC ?

No, not a chance....



x58haze said:


> Also i have a motherboard mid range b350 chipset fatality k4 gaming, which doesn't came with Calibration voltages for optimal overclock... and yep :c
> Also i found that amd ryzen seems to have poor IPC when playing single core games u.u
> 
> But the thing with intel is that their motherboard socket if you dont be careful you can bent cpu sockets and while amd their cpu have the pins and not direct from the motherboard.


----------



## Bartouille

LillysTittchen said:


> Hey,
> can someone explain me, why MemTest Pro achieves 8000% coverage without errors and after reboot it throws instantly errors? My Bios settings:
> 
> Memory Frequency: 3533 MHz
> DRAM Voltage: 1.48 V
> DRAM VPP: 2.52 V
> Vcore: Auto
> CLD0_VDDP: Auto
> DRAM VREF ChA: Auto
> DRAM VREF ChB: Auto
> 
> That are all adjustable voltages.
> 
> Timings: CL18-19-19-39
> SubTimings: All Auto
> GearDownMode: Disabled
> PowerDown enabled: Disabled
> BankGroupSwap: Enabled
> ProcODT: 53,3
> RttNom: 34,3
> RttPark: 48
> AddrCmdDrvStr, CsOdtDrvStr, CKEDrvStr, CLKDrvStr: 24, 24, 24, 24
> 
> There are more settings that may effect ram stability, i.e. CPU NB/SoC Switching Frequency, CPU NB/SoC LLC, Precision Boost, Opcache Control...
> 
> It's really weird. Just a simple reboot and the system isn't stable anymore??!! How can this be. There must be a voltage or setting, that changes by restarting the system, I don't have another explanation. Thats why I started to set most of the bios options istead of leaving it on Auto.
> 
> Btw: No Core oc done, just ram oc.


Memory training is super inconsistent on this platform. At lower speeds it's not too noticeable because there is more margin for error but when you start pushing high speeds (3466MHz+) you can really tell. On my system I noticed that memory training is more consistent if you only boot after switching psu off (i.e. drain psu power). Give it a try.


----------



## nick name

mongoled said:


> Guys, would like some advice!
> 
> Ive been through two MSI X370 Titaniums and 3 Ryzen CPUs (2x1600x and 2600x)
> 
> But still I cannot get my memory stable at anything higher than 3200mhz (my sig says 3333mhz, but its not 100% prime95 stable).
> 
> I have put hours and €€€ into this and have gotten nowhere over a period of 11 months.
> 
> I have not changed the memory which is G.SKILL F4-3600C15D-16GTZ.
> 
> Now here is when it gets weird, when I attempt to push past 3200mhz, lets say 3333mhz, increasing the voltage from 1.35v results in less stability!
> 
> Ive tried momentarily up to 1.5v and prime95 fails almost instantly, but if I run 1.35v it will through a few iterations etc etc.
> 
> So my predicament is as follows, im pretty sure its the MSI motherboard, but the reality is I should try another set of RAM first, so im looking at these G.SKILL F4-3200C14D-16GFX.
> 
> Would like to hear peoples opinions if they believe its the memory or the motherboard.
> 
> And yes, ive used 1usmus very helpful application, along with the Stilt's timing etc etc, but anything over 3200mhz is a no go when testing with prime95 (custom FFT 192, 14000mb )


I am using G.SKILL 3600C15 RAM and can run 3600 without issue. I have to use more than 1.35V even at DOCP timings however. Are you also adjusting your SOC? If you haven't set it to 1.1V then I would recommend that. AMD has said to set any RAM overclock to SOC 1.1V. Going higher probably won't help. And how does your RAM perform at 1.45V?


----------



## x58haze

The sad part is that i never would be able to know what are my ram chipset :/ until someone here in Overclock has the same pair of rams x.x


----------



## mongoled

nick name said:


> I am using G.SKILL 3600C15 RAM and can run 3600 without issue. I have to use more than 1.35V even at DOCP timings however. Are you also adjusting your SOC? If you haven't set it to 1.1V then I would recommend that. AMD has said to set any RAM overclock to SOC 1.1V. Going higher probably won't help. And how does your RAM perform at 1.45V?


Hi! Yeah ive tried everything ive read over the last 11 months!

Ive tried SOC voltage from 0.900v up to 1.2v, no difference!

Its as if I hit the same brickwall irrespectve of three different CPUs and two motherboards.

Either the RAM is dud or the MSI is a dud.

But I have no way of finding out unless I either buy another motherboard or another set of RAM.........

I cant complete post at 3600mhz irrespective of memory timings/voltage


----------



## mongoled

LillysTittchen said:


> Hey,
> can someone explain me, why MemTest Pro achieves 8000% coverage without errors and after reboot it throws instantly errors? My Bios settings:
> 
> Memory Frequency: 3533 MHz
> DRAM Voltage: 1.48 V
> DRAM VPP: 2.52 V
> Vcore: Auto
> CLD0_VDDP: Auto
> DRAM VREF ChA: Auto
> DRAM VREF ChB: Auto
> 
> That are all adjustable voltages.
> 
> Timings: CL18-19-19-39
> SubTimings: All Auto
> GearDownMode: Disabled
> PowerDown enabled: Disabled
> BankGroupSwap: Enabled
> ProcODT: 53,3
> RttNom: 34,3
> RttPark: 48
> AddrCmdDrvStr, CsOdtDrvStr, CKEDrvStr, CLKDrvStr: 24, 24, 24, 24
> 
> There are more settings that may effect ram stability, i.e. CPU NB/SoC Switching Frequency, CPU NB/SoC LLC, Precision Boost, Opcache Control...
> 
> It's really weird. Just a simple reboot and the system isn't stable anymore??!! How can this be. There must be a voltage or setting, that changes by restarting the system, I don't have another explanation. Thats why I started to set most of the bios options istead of leaving it on Auto.
> 
> Btw: No Core oc done, just ram oc.


Sounds like my MSI X370, prime95 stable with settings in sig,

then next reboot fails after a few iterations.

Wish I had never gone with MSI........


----------



## nick name

mongoled said:


> Hi! Yeah ive tried everything ive read over the last 11 months!
> 
> Ive tried SOC voltage from 0.900v up to 1.2v, no difference!
> 
> Its as if I hit the same brickwall irrespectve of three different CPUs and two motherboards.
> 
> Either the RAM is dud or the MSI is a dud.
> 
> But I have no way of finding out unless I either buy another motherboard or another set of RAM.........
> 
> I cant complete post at 3600mhz irrespective of memory timings/voltage


I'd bet it's the motherboard and not the RAM.


----------



## mongoled

nick name said:


> I'd bet it's the motherboard and not the RAM.


Thats what im leaning towards, such a shame built my rig around it!

It wouldnt just be the cost of the motherboard that I would have to right off but the monoblock also.

:/


----------



## tekjunkie28

mongoled said:


> Guys, would like some advice!
> 
> Ive been through two MSI X370 Titaniums and 3 Ryzen CPUs (2x1600x and 2600x)
> 
> But still I cannot get my memory stable at anything higher than 3200mhz (my sig says 3333mhz, but its not 100% prime95 stable).
> 
> I have put hours and €€€ into this and have gotten nowhere over a period of 11 months.
> 
> I have not changed the memory which is G.SKILL F4-3600C15D-16GTZ.
> 
> Now here is when it gets weird, when I attempt to push past 3200mhz, lets say 3333mhz, increasing the voltage from 1.35v results in less stability!
> 
> Ive tried momentarily up to 1.5v and prime95 fails almost instantly, but if I run 1.35v it will through a few iterations etc etc.
> 
> So my predicament is as follows, im pretty sure its the MSI motherboard, but the reality is I should try another set of RAM first, so im looking at these G.SKILL F4-3200C14D-16GFX.
> 
> Would like to hear peoples opinions if they believe its the memory or the motherboard.
> 
> And yes, ive used 1usmus very helpful application, along with the Stilt's timing etc etc, but anything over 3200mhz is a no go when testing with prime95 (custom FFT 192, 14000mb )


It's the motherboard more than likely. I would go with a asus C7H. It automatically changes some timings and it highly capable board for high memory speeds. 

What are your timings at 3200? CL14 with tight timings at 3200 is still hard to beat.

Sent from my SM-N950U using Tapatalk


----------



## nick name

mongoled said:


> Thats what im leaning towards, such a shame built my rig around it!
> 
> It wouldnt just be the cost of the motherboard that I would have to right off but the monoblock also.
> 
> :/


Ouch. Yeah I guess you could try to sell them together and wait for that special buyer, but at this point I'm not sure they are out there. Hopefully, a BIOS update will come around that gets you where you want to be. I sold off my first Asus Prime X470 because of the capabilities of the Crosshair VII and have been pleased with that decision. I also lucked out and found a $60 off sale Newegg was having right when I was ready to buy a Crosshair.


----------



## mongoled

nick name said:


> Ouch. Yeah I guess you could try to sell them together and wait for that special buyer, but at this point I'm not sure they are out there. Hopefully, a BIOS update will come around that gets you where you want to be. I sold off my first Asus Prime X470 because of the capabilities of the Crosshair VII and have been pleased with that decision. I also lucked out and found a $60 off sale Newegg was having right when I was ready to buy a Crosshair.


Well ive been trying to nab a Asus Crosshair VI from fleebay while penny pinching, but I keep missing out!

Hopefully will be able to grab one cheap and cheerful to at least run some tests.

Fingers crossed!


----------



## mongoled

tekjunkie28 said:


> It's the motherboard more than likely. I would go with a asus C7H. It automatically changes some timings and it highly capable board for high memory speeds.
> 
> What are your timings at 3200? CL14 with tight timings at 3200 is still hard to beat.
> 
> Sent from my SM-N950U using Tapatalk


Yeah already using 1usmus fast profile for 3200mhz, but it does not have the throughput of higher frequency memory.

Its not that I cant get by with 3200mhz tight timings, its just that im a tweaker and ive always maxed out my rigs, but 3200mhz is way behind what other peeps are pushing and I bought this RAM at a premium so I could do just that!


----------



## tekjunkie28

mongoled said:


> Yeah already using 1usmus fast profile for 3200mhz, but it does not have the throughput of higher frequency memory.
> 
> Its not that I cant get by with 3200mhz tight timings, its just that im a tweaker and ive always maxed out my rigs, but 3200mhz is way behind what other peeps are pushing and I bought this RAM at a premium so I could do just that!


What kind of throughput are you wanting? I can assure you that its not as high as you would expect. You're just chasing numbers at some point. 

Sent from my SM-N950U using Tapatalk


----------



## nick name

mongoled said:


> Well ive been trying to nab a Asus Crosshair VI from fleebay while penny pinching, but I keep missing out!
> 
> Hopefully will be able to grab one cheap and cheerful to at least run some tests.
> 
> Fingers crossed!


Do you think you'd be satisfied with a Crosshair VI knowing the VII is out there? Also, here are my numbers currently.


----------



## 1usmus

mongoled said:


> Guys, would like some advice!
> 
> Ive been through two MSI X370 Titaniums and 3 Ryzen CPUs (2x1600x and 2600x)
> 
> But still I cannot get my memory stable at anything higher than 3200mhz (my sig says 3333mhz, but its not 100% prime95 stable).
> 
> I have put hours and €€€ into this and have gotten nowhere over a period of 11 months.
> 
> I have not changed the memory which is G.SKILL F4-3600C15D-16GTZ.
> 
> Now here is when it gets weird, when I attempt to push past 3200mhz, lets say 3333mhz, increasing the voltage from 1.35v results in less stability!
> 
> Ive tried momentarily up to 1.5v and prime95 fails almost instantly, but if I run 1.35v it will through a few iterations etc etc.
> 
> So my predicament is as follows, im pretty sure its the MSI motherboard, but the reality is I should try another set of RAM first, so im looking at these G.SKILL F4-3200C14D-16GFX.
> 
> Would like to hear peoples opinions if they believe its the memory or the motherboard.
> 
> And yes, ive used 1usmus very helpful application, along with the Stilt's timing etc etc, but anything over 3200mhz is a no go when testing with prime95 (custom FFT 192, 14000mb )


new agesa do not helped 1.0.0.4 ?

_________________________

4-5 motherboards out of 100 fail completely within a year, 10 out of 100 motherboards have a slight defect in conductors (buses). Perhaps you have this particular case. 
There is also an unofficial statistics in which 15% of processors are not able to work stably with a memory frequency over 3200 MHz

Prior to the announcement of Zen 2 4 months left, I advise you to wait.


----------



## mongoled

tekjunkie28 said:


> What kind of throughput are you wanting? I can assure you that its not as high as you would expect. You're just chasing numbers at some point.
> 
> Sent from my SM-N950U using Tapatalk


Well yeah, thats what tweakers do, chase numbers 



See screenshots of 'nick name' below your last post

I push arnd 50000mb @3200, compared to 57000 @3600

Will post pics tomorrow when I have access to the PC 



nick name said:


> Do you think you'd be satisfied with a Crosshair VI knowing the VII is out there? Also, here are my numbers currently.


I will be satisfied when I can run my memory close to what I expected having forked out a premium price for it + motherboard monblock.

So that would be at least greater than 3466mhz



1usmus said:


> new agesa do not helped 1.0.0.4 ?
> 
> _________________________
> 
> 4-5 motherboards out of 100 fail completely within a year, 10 out of 100 motherboards have a slight defect in conductors (buses). Perhaps you have this particular case.
> There is also an unofficial statistics in which 15% of processors are not able to work stably with a memory frequency over 3200 MHz
> 
> Prior to the announcement of Zen 2 4 months left, I advise you to wait.


Im am using the modified BIOS you and others have kindly made available to us and the new agesa have generally not helped.

Re statistics, I would have to be pretty unlucky for it to be the cause of my woes! It is possible ofcourse!

Yes, its not so long to wait for Zen2


----------



## seansplayin

miklkit said:


> Saying the IPC isn't as high as some doesn't mean it is slow.


It's true if you compare the top end of AMD 2700x and Intel 8700k/8086k, Intel has a small single thread performance lead but IMHO it's irrelevant. the 1% and .1% lows are what kills the gaming experience. without a FPS counter no one can tell the difference between 115fps and 125fps, however you'll definitely notice the difference between 1% lows of 40fps and 60fps. fast memory on Ryzen provides huge gains in .1% and 1% lows. 
having 33% more cores 6>8 cores means closing background apps before gaming is not needed and streaming while gaming or watching youtube makes pretty much no difference.

if you really want higher single thread performance on Ryzen you can disable SMT and you'll be able to overclock 200mhz higher at least for my 1800x but your multi-thread performance will drop to 72% when comparing Cinebench scores. DX11 games will get a small performance bump from disabling SMT, DX12 games usually do a little better with SMT enabled. this is my 1800x @ 4300mhz with ok memory speed and timings with SMT disabled.


----------



## miklkit

I have zero need for the very highest single thread performance. Multi thread performance is what I want and need. And now you are saying that a 4790K is a bad cpu?


----------



## enerdjysk

bought a fresh SAMSUNG M378A1K43CB2-CRC, 2600X OEM, MSI B450 TOMAHAWK, first after a 18 18 18 38, 3000 overclock google stressapptest show me some errors, so i use the default RAM settings and test again, so i've got some error again. 
i didnt overclock cpu, disable XFR and PBO, set CPU voltage to AUTO and multiplier to 36
any chances its a bad RAM or problem could be in CPU/mobo?


----------



## Darkstalker420

@mongoled

Try raising your SoC LLC to the highest it will go (for me it's EXTREME). I couldn't get repeatable stress tests until i did that. Also (if your MoBo supports it raise CPU Switch Frequency 
i set mine to 350). Those were the best for me to get 3200Mhz stable and might help you out.

Thanx.


----------



## Aeonyx7

Has anyone here achieved solid speeds with 64GB (4x16)? I'm thinking of adding a second 32GB Dominator Platinum 3200 kit to my build. Can't get over 3066MHz stable with Aorus X470 Gaming 5 (should have bought the 7, I know), and wondering if I'd see way losses in mem clocks by going 4 DIMMs.


----------



## DemonAk

I have 4x16gb samsung oem c-die, stable at 3333mhz, dram voltage: 1.37 (hwinfo: 1.384-1.392). Can't get stable 3400,3466 and 3533


----------



## 1usmus

LillysTittchen said:


> Hey,
> can someone explain me, why MemTest Pro achieves 8000% coverage without errors and after reboot it throws instantly errors? My Bios settings:
> 
> Memory Frequency: 3533 MHz
> DRAM Voltage: 1.48 V
> DRAM VPP: 2.52 V
> Vcore: Auto
> CLD0_VDDP: Auto
> DRAM VREF ChA: Auto
> DRAM VREF ChB: Auto
> 
> That are all adjustable voltages.
> 
> Timings: CL18-19-19-39
> SubTimings: All Auto
> GearDownMode: Disabled
> PowerDown enabled: Disabled
> BankGroupSwap: Enabled
> ProcODT: 53,3
> RttNom: 34,3
> RttPark: 48
> AddrCmdDrvStr, CsOdtDrvStr, CKEDrvStr, CLKDrvStr: 24, 24, 24, 24
> 
> There are more settings that may effect ram stability, i.e. CPU NB/SoC Switching Frequency, CPU NB/SoC LLC, Precision Boost, Opcache Control...
> 
> It's really weird. Just a simple reboot and the system isn't stable anymore??!! How can this be. There must be a voltage or setting, that changes by restarting the system, I don't have another explanation. Thats why I started to set most of the bios options istead of leaving it on Auto.
> 
> Btw: No Core oc done, just ram oc.


HCI is a very weak test, you may have errors in the first case. I published a new BIOS for your motherboard, try it. The link in my signature.



enerdjysk said:


> bought a fresh SAMSUNG M378A1K43CB2-CRC, 2600X OEM, MSI B450 TOMAHAWK, first after a 18 18 18 38, 3000 overclock google stressapptest show me some errors, so i use the default RAM settings and test again, so i've got some error again.
> i didnt overclock cpu, disable XFR and PBO, set CPU voltage to AUTO and multiplier to 36
> any chances its a bad RAM or problem could be in CPU/mobo?


use the ryzen dram calculator, 3000 is not the limit


----------



## Hequaqua

@1usmus

First, thanks for all the work that you've done and are continuing to do! :thumb:

Second, what do you suggest as the "best" way to determine ram stability?

Normally, these are the things that I do:

TM5(your cfg file)5 Cycles
TM5(your cfg file)15 Cycles
GSTAT(at least a hour w/13312mb of ram)
HCI(at least 400% coverage)

That seems to work for me really well. I'm stable at 3400CL14 with the fast timings from the calculator. I don't care for HCI either. 

My RTC:



Spoiler


----------



## 1usmus

Hequaqua said:


> @1usmus
> 
> First, thanks for all the work that you've done and are continuing to do! :thumb:
> 
> Second, what do you suggest as the "best" way to determine ram stability?
> 
> Normally, these are the things that I do:
> 
> TM5(your cfg file)5 Cycles
> TM5(your cfg file)15 Cycles
> GSTAT(at least a hour w/13312mb of ram)
> HCI(at least 400% coverage)
> 
> That seems to work for me really well. I'm stable at 3400CL14 with the fast timings from the calculator. I don't care for HCI either.
> 
> My RTC:
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 216777


I believe that TM5 + 15 cycles is the best test. It is the only complex test that now exists for memory testing. Karhu and HCI have, for example, only one cycle. Actually, there are a lot of differences.

The only nuance during any long-term testing is the temperature. Above 52 degrees will be errors. Because I did only 5 cycles in my configuration.


----------



## Hequaqua

1usmus said:


> I believe that TM5 + 15 cycles is the best test. It is the only complex test that now exists for memory testing. Karhu and HCI have, for example, only one cycle. Actually, there are a lot of differences.
> 
> The only nuance during any long-term testing is the temperature. Above 52 degrees will be errors. Because I did only 5 cycles in my configuration.


Thanks.....for the info.

I have a additional fan feeding cool air on the ram. Temps are 35°C Max. :thumb:


----------



## DemonAk

Hequaqua said:


> Second, what do you suggest as the "best" way to determine ram stability?
> 
> Normally, these are the things that I do:
> 
> TM5(your cfg file)5 Cycles
> TM5(your cfg file)15 Cycles
> GSTAT(at least a hour w/13312mb of ram)
> HCI(at least 400% coverage)


try the last control test https://www.memtest86.com/download.htm, only he found errors on the 7th test in my memory, then added voltage on ram and was able to pass it


----------



## crakej

mongoled said:


> Guys, would like some advice!
> 
> Ive been through two MSI X370 Titaniums and 3 Ryzen CPUs (2x1600x and 2600x)
> 
> But still I cannot get my memory stable at anything higher than 3200mhz (my sig says 3333mhz, but its not 100% prime95 stable).
> 
> I have put hours and €€€ into this and have gotten nowhere over a period of 11 months.
> 
> I have not changed the memory which is G.SKILL F4-3600C15D-16GTZ.
> 
> Now here is when it gets weird, when I attempt to push past 3200mhz, lets say 3333mhz, increasing the voltage from 1.35v results in less stability!
> 
> Ive tried momentarily up to 1.5v and prime95 fails almost instantly, but if I run 1.35v it will through a few iterations etc etc.
> 
> So my predicament is as follows, im pretty sure its the MSI motherboard, but the reality is I should try another set of RAM first, so im looking at these G.SKILL F4-3200C14D-16GFX.
> 
> Would like to hear peoples opinions if they believe its the memory or the motherboard.
> 
> And yes, ive used 1usmus very helpful application, along with the Stilt's timing etc etc, but anything over 3200mhz is a no go when testing with prime95 (custom FFT 192, 14000mb )


Try Geardown=*Enabled*


----------



## rdr09

mongoled said:


> Guys, would like some advice!
> 
> And yes, ive used 1usmus very helpful application, along with the Stilt's timing etc etc, but anything over 3200mhz is a no go when testing with prime95 (custom FFT 192, 14000mb )


Stilt's timing as in post # 20666 . . .

https://www.overclock.net/forum/11-...i-overclocking-thread-2067.html#post_26178558

Someone asked if you messed with SOC? Set it to 1.1v. Apply some LLC to it. Also, try a different test such as TestMem and HCI.


----------



## Hequaqua

DemonAk said:


> try the last control test https://www.memtest86.com/download.htm, only he found errors on the 7th test in my memory, then added voltage on ram and was able to pass it


What do you mean the last control test?

I downloaded it....made a USB drive...booted into it and started running. I didn't finish the whole thing though....figured I had a couple of questions first.

Here is what it showed after the first pass:









First question is the display for the CPU/Temp....is that what it is running the cpu at and the current temp? I have my CPU set to 4.2ghz, and the RAM is at 3400.

Second, do I just need to run it the 4 passes(all tests)?


----------



## DemonAk

Hequaqua said:


> What do you mean the last control test?
> 
> I downloaded it....made a USB drive...booted into it and started running. I didn't finish the whole thing though....figured I had a couple of questions first.
> 
> Here is what it showed after the first pass:
> 
> View attachment 217038
> 
> 
> First question is the display for the CPU/Temp....is that what it is running the cpu at and the current temp? I have my CPU set to 4.2ghz, and the RAM is at 3400.
> 
> Second, do I just need to run it the 4 passes(all tests)?


I had in mind the last test that will show whether the memory is stable. most likely temperatures are incorrect because I had 105 degrees. Not necessarily pass all 4 passes, 2 think enough. Your memory is stable


----------



## Hequaqua

DemonAk said:


> I had in mind the last test that will show whether the memory is stable. most likely temperatures are incorrect because I had 105 degrees. Not necessarily pass all 4 passes, 2 think enough. Your memory is stable


I didn't think it was correct.....but then again, first time I've used it. I'm stable in everything else, but that test is another that can go into my toolbox. Thanks! :thumb:

EDIT/Update: I ran the full test, 4 cycles....no errors! :thumb:



Spoiler


----------



## LillysTittchen

I found out that enabling *GearDownMode* stabilizes my Hynix AFR ram on higher frequencies > 3400 MHz with tighter timings. For example 3533 with 1T 16-17-17-35 and GDM disabled will throw BSODs, no matter what procOdt or voltage I have set. Same with 3600 but here the system won't even boot, so that I have to clear CMOS. When I enable GDM my system is almost stable. I would even say it's semi stable.

Can someone confirm that?


----------



## nick name

LillysTittchen said:


> I found out that enabling *GearDownMode* stabilizes my Hynix AFR ram on higher frequencies > 3400 MHz with tighter timings. For example 3533 with 1T 16-17-17-35 and GDM disabled will throw BSODs, no matter what procOdt or voltage I have set. Same with 3600 but here the system won't even boot, so that I have to clear CMOS. When I enable GDM my system is almost stable. I would even say it's semi stable.
> 
> Can someone confirm that?


I can say I can confirm it, I can say it will allow for the use of odd numbered timings. That may be what is adding to your stability.


----------



## LillysTittchen

I guess GDM enabled doesn't have much impact on overall performance right?


----------



## CJMitsuki

LillysTittchen said:


> Hey,
> can someone explain me, why MemTest Pro achieves 8000% coverage without errors and after reboot it throws instantly errors? My Bios settings:
> 
> Memory Frequency: 3533 MHz
> DRAM Voltage: 1.48 V
> DRAM VPP: 2.52 V
> Vcore: Auto
> CLD0_VDDP: Auto
> DRAM VREF ChA: Auto
> DRAM VREF ChB: Auto
> 
> That are all adjustable voltages.
> 
> Timings: CL18-19-19-39
> SubTimings: All Auto
> GearDownMode: Disabled
> PowerDown enabled: Disabled
> BankGroupSwap: Enabled
> ProcODT: 53,3
> RttNom: 34,3
> RttPark: 48
> AddrCmdDrvStr, CsOdtDrvStr, CKEDrvStr, CLKDrvStr: 24, 24, 24, 24
> 
> There are more settings that may effect ram stability, i.e. CPU NB/SoC Switching Frequency, CPU NB/SoC LLC, Precision Boost, Opcache Control...
> 
> It's really weird. Just a simple reboot and the system isn't stable anymore??!! How can this be. There must be a voltage or setting, that changes by restarting the system, I don't have another explanation. Thats why I started to set most of the bios options istead of leaving it on Auto.
> 
> Btw: No Core oc done, just ram oc.


I think it has more to do with the “Auto” settings in the bios. With every reboot you are letting the bios change the “Auto” settings to what the bios algorithm decides is best for it. Well, it’s likely that one or more of these settings could be changed to something that will cause memory instability. I changed nearly all voltages and memory settings to something other than Auto as I was getting inconsistent reboots as well. Once I spent a great deal of time tweaking these settings instead of letting the bios do it I got no more inconsistent boots. It makes sense that especially at the edge of stability where one tiny difference can mean stable or unstable setup, there will be more inconsistencies with more Auto settings for the bios to decide on.



1usmus said:


> HCI is a very weak test, you may have errors in the first case. I published a new BIOS for your motherboard, try it. The link in my signature.
> 
> 
> 
> use the ryzen dram calculator, 3000 is not the limit


While I agree with you on HVI being a weak test TM5 has some inconsistencies and odd behavior sometimes as well. I’ve seen, with a very fast setup that sometimes TM5 will hang up at test 14(very last test) for an extended amount of time before letting the test move to the next cycle. The timer is also very odd on how it counts. I also wish it would record in the window how long each cycle took and what time on the timer the cycle ended. Maybe even have a choice for a more detailed log with how long each test in the cycle took and average cycle times etc.


----------



## CJMitsuki

Hequaqua said:


> I didn't think it was correct.....but then again, first time I've used it. I'm stable in everything else, but that test is another that can go into my toolbox. Thanks! :thumb:
> 
> EDIT/Update: I ran the full test, 4 cycles....no errors! :thumb:
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 217116
> 
> 
> View attachment 217118


Memtest86 isn’t that great for memory testing anymore. It was good back when that’s all that we had to use but it’s probably the worst one for determining stability. If you want to test outside of the OS then I’d suggest using HCI MemTest Deluxe. If you get the paid version it comes with an bootable ISO that you can use Rufus to copy to usb and use their test out of the OS. Everyone has their say about HCI but I still say that particular test is the best for finding errors. TM5 is good but I’ve ran several rounds of 10 cycles with TM5 and passed them but after running HCI Deluxe while at work when I come home it has found 1 or 2 errors that are very rare. Passing 1000% on that test assures me the ram is clean without any doubt in my mind. For 16gb 1000% is about 10 hours and it tests 15.93gb of the 16gb in the system so that is the benefit of not having the OS interfering with the memory test. Some argue and say “Bit you have to run inside the OS to make sure it is stable”. If your memory is stable with all variables out of the equation then it is stable, no way to argue that. If you boot into your OS and there are errors then the errors didn’t magically appear. There are problems coming from the OS itself that is not due to the memory since that is confirmed to be clean if not inside of the OS. Corrupt files are what I have found to be the biggest contributor of false positives for memory errors. Using SFC and DISM commands will clean Win 10 and 8, the System Update Readiness Tool and SFC commands for Windows 7. Vista is also the same as Win 10 but am not positive. Why didn’t I mention 8.1? Because if you use that OS you have bigger problems than corrupt files to worry about :lachen:


----------



## Hequaqua

CJMitsuki said:


> Memtest86 isn’t that great for memory testing anymore. It was good back when that’s all that we had to use but it’s probably the worst one for determining stability. If you want to test outside of the OS then I’d suggest using HCI MemTest Deluxe. If you get the paid version it comes with an bootable ISO that you can use Rufus to copy to usb and use their test out of the OS. Everyone has their say about HCI but I still say that particular test is the best for finding errors. TM5 is good but I’ve ran several rounds of 10 cycles with TM5 and passed them but after running HCI Deluxe while at work when I come home it has found 1 or 2 errors that are very rare. Passing 1000% on that test assures me the ram is clean without any doubt in my mind. For 16gb 1000% is about 10 hours and it tests 15.93gb of the 16gb in the system so that is the benefit of not having the OS interfering with the memory test. Some argue and say “Bit you have to run inside the OS to make sure it is stable”. If your memory is stable with all variables out of the equation then it is stable, no way to argue that. If you boot into your OS and there are errors then the errors didn’t magically appear. There are problems coming from the OS itself that is not due to the memory since that is confirmed to be clean if not inside of the OS. Corrupt files are what I have found to be the biggest contributor of false positives for memory errors. Using SFC and DISM commands will clean Win 10 and 8, the System Update Readiness Tool and SFC commands for Windows 7. Vista is also the same as Win 10 but am not positive. Why didn’t I mention 8.1? Because if you use that OS you have bigger problems than corrupt files to worry about :lachen:


I do have the paid version of HCI. I have used it inside/outside of the OS.

I have my own, for lack of a better word-thresholds, of what I consider stable. Some may agree, some may not....they aren't me though....lol. 

I ran that test because it was suggested. AFAIK, it was updated in Feb. 2018, what those updates cover as far as testing, I don't know...I didn't read the release notes. I use about 4-5 different tests for memory. Then a few that I throw in that are CPU heavy, but do rely on ram as well(prime95/IBT/ect).

Like I posted earlier....all of them are just tools that can go into my toolbox.


----------



## CJMitsuki

Hequaqua said:


> I do have the paid version of HCI. I have used it inside/outside of the OS.
> 
> I have my own, for lack of a better word-thresholds, of what I consider stable. Some may agree, some may not....they aren't me though....lol.
> 
> I ran that test because it was suggested. AFAIK, it was updated in Feb. 2018, what those updates cover as far as testing, I don't know...I didn't read the release notes. I use about 4-5 different tests for memory. Then a few that I throw in that are CPU heavy, but do rely on ram as well(prime95/IBT/ect).
> 
> Like I posted earlier....all of them are just tools that can go into my toolbox.


Stability doesn’t have one solid threshold, it’s a subjective term when used for memory overclocking. Just like a gamer doesn’t need server like stability neither will a computer used as a server want to be “game stable”. It applies to what you use the machine for and your personal tastes for such levels of stability. As for memtest86, sure it can be a tool in your toolbox but look at it as the old, rusty, bent screwdriver that can work but may not be the best tool for the job


----------



## Hequaqua

CJMitsuki said:


> Stability doesn’t have one solid threshold, it’s a subjective term when used for memory overclocking. Just like a gamer doesn’t need server like stability neither will a computer used as a server want to be “game stable”. It applies to what you use the machine for and your personal tastes for such levels of stability. As for memtest86, sure it can be a tool in your toolbox but look at it as the old, rusty, bent screwdriver that can work but may not be the best tool for the job


I hear ya.....that's why I don't put all my eggs in one basket....in fact, that was the first time I ever used....but good info to know.....info is king when finding what's right for our rig. :thumb:


----------



## LillysTittchen

CJMitsuki said:


> I think it has more to do with the “Auto” settings in the bios. With every reboot you are letting the bios change the “Auto” settings to what the bios algorithm decides is best for it. Well, it’s likely that one or more of these settings could be changed to something that will cause memory instability. I changed nearly all voltages and memory settings to something other than Auto as I was getting inconsistent reboots as well. Once I spent a great deal of time tweaking these settings instead of letting the bios do it I got no more inconsistent boots. It makes sense that especially at the edge of stability where one tiny difference can mean stable or unstable setup, there will be more inconsistencies with more Auto settings for the bios to decide on.
> 
> 
> 
> While I agree with you on HVI being a weak test TM5 has some inconsistencies and odd behavior sometimes as well. I’ve seen, with a very fast setup that sometimes TM5 will hang up at test 14(very last test) for an extended amount of time before letting the test move to the next cycle. The timer is also very odd on how it counts. I also wish it would record in the window how long each cycle took and what time on the timer the cycle ended. Maybe even have a choice for a more detailed log with how long each test in the cycle took and average cycle times etc.


Hi CJMitsuki
you answered my question already in the Ryzen DRAM Calculator thread but I find ur answer here better 
I share your theory about Auto setup will fluctuate, thats why I asked you and "nick name" for further steps in the Ryzen DRAM Calculator thread where I also posted my Bios settings regarding OC. Maybe you will find time and answer there. Its on page 287, no one answered yet so I would appreciate if you could have a look.

I also did some investigations on Bios modding but its frustrating. The tutorials about it are really rare and trivial. Do you have experience about this topic?


----------



## CJMitsuki

LillysTittchen said:


> Hi CJMitsuki
> you answered my question already in the Ryzen DRAM Calculator thread but I find ur answer here better
> I share your theory about Auto setup will fluctuate, thats why I asked you and "nick name" for further steps in the Ryzen DRAM Calculator thread where I also posted my Bios settings regarding OC. Maybe you will find time and answer there. Its on page 287, no one answered yet so I would appreciate if you could have a look.
> 
> I also did some investigations on Bios modding but its frustrating. The tutorials about it are really rare and trivial. Do you have experience about this topic?


Unfortunately no, I don’t but @1usmus has a bios modding thread you may want to check out. I wouldn’t go modding and flashing a rom unless I was absolutely sure I had done it correctly. If you have dual bios or a way to externally flash the bios then you would be safe. If there are no protections for such a mistake on your mobo then I would tread carefully. I will check your other question here in a bit once I’m on break again at work and see if I can give you an answer.


----------



## Shaav

Hey guys,

if you could submit your (stable) RAM overclocking results in this spreadsheet, that would be great:

*https://docs.google.com/spreadsheets/d/1HKPVfDcFO-aieAOXHFQZp15rwWadbPTVDNgO8vtyDCM*

I think this would help all of us.


----------



## B4rr3L Rid3R

DemonAk said:


> I have 4x16gb samsung oem c-die, stable at 3333mhz, dram voltage: 1.37 (hwinfo: 1.384-1.392). Can't get stable 3400,3466 and 3533


Linx doesnt get memory errors, go with prime custom, y-cruncher or even AIDA64 that uses the whole memory. It's a great CPU overclock test btw


----------



## AmaKatsu

I think HCI lack of thermal test for ram



For HCI memtest Pro 5.1 and 6.1 ran both 6hrs with no problem (VSoC 1.087)



But error on Aida64 in 1hr,



VSoC 1.10 able to run 5mins

VSoC 1.087 able to run 1hr

VSoC 1.067 able to run 8hrs+

And I'm stuck at 3333 CL16 1.37v because of thermal issue >_<"

For 3400 1.39v need fan cooler to pass stable test.


----------



## CJMitsuki

AmaKatsu said:


> I think HCI lack of thermal test for ram
> 
> 
> 
> For HCI memtest Pro 5.1 and 6.1 ran both 6hrs with no problem (VSoC 1.087)
> 
> 
> 
> But error on Aida64 in 1hr,
> 
> 
> 
> VSoC 1.10 able to run 5mins
> 
> VSoC 1.087 able to run 1hr
> 
> VSoC 1.067 able to run 8hrs+
> 
> And I'm stuck at 3333 CL16 1.37v because of thermal issue >_<"
> 
> For 3400 1.39v need fan cooler to pass stable test.


Just zip tie a small case fan to the memory heatsinks blowing directly onto the ram. Its worked for plenty of people.


----------



## bluerodent

If I have the latest AGESA installed on my ASRock Fatal1ty AB350 Gaming-ITX/ac motherboard, what chances do I stand at being able to run a G.SKILL TridentZ 3600CL16 kit (F4-3600C16D-16GTZ) at stock XMP 2.0 settings with a 1st generation Ryzen 7 1700 processor? For what it is worth, my processor is a RMA replacement Ryzen 7 1700 from early December 2017 which corrects the very rare Linux segfault bug. It may very well be a better binned part since I can do 3.9 GHz at 1.35V, whereas the original could only do 3.8 GHz at the same voltage. Keep in mind, however, that it is not a total show stopper if I cannot run this kit at 3600 MHz because I am buying it more to futureproof with a high bandwidth kit to feed a possible 12- or 16-core Ryzen 7 3000 series processor next year. I am just curious how far I can push this memory kit from the beginning. If this is also of any help, my current BIOS which is the latest one available from ASRock for my model has AGESA PinnaclePI-AM4_1.0.0.4. MSI claims here ( https://www.msi.com/Motherboard/support/B350M-BAZOOKA.html#down-bios) that this 1.0.0.4 AGESA "improve memory compatibility." Hmm...


----------



## rdr09

bluerodent said:


> If I have the latest AGESA installed on my ASRock Fatal1ty AB350 Gaming-ITX/ac motherboard, what chances do I stand at being able to run a G.SKILL TridentZ 3600CL16 kit (F4-3600C16D-16GTZ) at stock XMP 2.0 settings with a 1st generation Ryzen 7 1700 processor? For what it is worth, my processor is a RMA replacement Ryzen 7 1700 from early December 2017 which corrects the very rare Linux segfault bug. It may very well be a better binned part since I can do 3.9 GHz at 1.35V, whereas the original could only do 3.8 GHz at the same voltage. Keep in mind, however, that it is not a total show stopper if I cannot run this kit at 3600 MHz because I am buying it more to futureproof with a high bandwidth kit to feed a possible 12- or 16-core Ryzen 7 3000 series processor next year. I am just curious how far I can push this memory kit from the beginning. If this is also of any help, my current BIOS which is the latest one available from ASRock for my model has AGESA PinnaclePI-AM4_1.0.0.4. MSI claims here ( https://www.msi.com/Motherboard/support/B350M-BAZOOKA.html#down-bios) that this 1.0.0.4 AGESA "improve memory compatibility." Hmm...




I've been reading how lower speed like 3400 with tight timings can beat 3600 Cl16. If it does not work using XMP, then you lower it down to 3400 or 3466 MHz. Use the DRAM calculator by 1usmus. 

https://www.overclock.net/forum/13-...lator-1-1-0-beta-2-overclocking-dram-am4.html

Check out Jpm's post #7313 (Intel thread lol)

https://www.overclock.net/forum/5-i...el-ddr4-24-7-memory-stability-thread-732.html

When I updated to the latest BIOS version on an Asus B350 switching from 1st gen Ryzen to 2nd, i had to raise my voltage fr 1.35 to 1.37v to keep 3200MHz (factory spec) stable. Now, i just lowered the speed down to 3166 Cl 14 and back down to 1.35v. A little slower but my RAM temp stays below 40C running Realbench. Much lower when gaming.


----------



## rush2049

name	frequency	timings	GDM	read	write	copy	latency	CPU all core turbo	rank	DIMMs	Die type	VSOC (BIOS)	VDIMM (BIOS)	
ProcODT	RttNom	RttWr	RttPark	CLKDrvSTr	AddrCmdDrvStr	CsOdtDrvStr	CKEDrvStr	AddrCmdSetup	CsOdtSetup	CkeSetup 
DRAM part number	part number	Mainboard	BIOS

rush2049	3600 MHz	14-14-14-28-42-2T	off	54658 MB/s	trial aida	trial aida	66.9 ns	R7 1800X	4,00 Ghz 4x8GB	Samsung B-die	1,187 V	1,440 V	
53.3	RZQ/7	Dynamic ODT Off	RZQ/5	30 Ω	30 Ω	30 Ω	30 Ω	0	0	0	
Prime95 (non AVX) Custom 8K-13K; 26000MB; 3min - 30 min passed+	F4-3600C15-8GTZ ASUS ROG Crosshair VI Hero	6201




Sorry for formatting, but I filled in that google sheet above. I only have trial aida so I can't find my write/copy.

edit-------------------------------------
This is slightly better, but I avg the above test scores.
https://www.overclock.net/forum/attachment.php?attachmentid=220346


----------



## rush2049

On the left you have my current stable settings.

In the two photos at the bottom are my unstable, but best cpu_z bench passing settings. Only adjusting the memory at the moment.

https://www.overclock.net/forum/attachment.php?attachmentid=220604


----------



## Synoxia

mobo: CH7 bios 702
CPU: ryzen 1600x
RAM: https://www.gskill.com/en/product/f4-3600c17q-16gtz

SOC 1.10625
CPU voltage 1.42
Dram voltage 1.41


----------



## cicero s

RAM: Corsair Vengeance LPX3000 (version *5.20*), CMK16GX4M2B3000C15, H5AN4G8NAFR-TFC, Hynix AFR.
CPU: 2700X
MB: GB X470 Gaming 7


currently on 3000MHz, 14-16-16-34-50 1T. Is there any better result for the specific ram? I can't reach 3200 and getting skeptical more and more due to the nature of this ram kit; they seem to have a number of versions, and each reports a different result.


thanks in advance.


----------



## christoph

AmaKatsu said:


> I think HCI lack of thermal test for ram
> 
> 
> 
> For HCI memtest Pro 5.1 and 6.1 ran both 6hrs with no problem (VSoC 1.087)
> 
> 
> 
> But error on Aida64 in 1hr,
> 
> 
> 
> VSoC 1.10 able to run 5mins
> 
> VSoC 1.087 able to run 1hr
> 
> VSoC 1.067 able to run 8hrs+
> 
> And I'm stuck at 3333 CL16 1.37v because of thermal issue >_<"
> 
> For 3400 1.39v need fan cooler to pass stable test.




you found more stability with LESS voltage?


----------



## mtrai

christoph said:


> you found more stability with LESS voltage?



Yes that is indeed sometimes the case on Ryzen that less voltage is more stable and this can change from one bios to another and of course from board to board. When I say board to board I do not just mean manufacturer but each board is unique even within the same line...as are each CPU. All in all it makes for an interesting puzzle.

That I why I say to only use someone else settings as a stating point, no matter how stable they prove it is You ram, cpu and motherboard all are unique to you.


----------



## HeroofTime

Hello everyone,

I've had my system for almost a year (around 10 months), and finally got around to overclocking my RAM the past two days. I would greatly appreciate your help. This is far from my first time overclocking, so I have a fairly good understanding of most of the settings that tie into overclocking RAM. My system specs that are relevant to this post are listed at the bottom. I've done so much testing the past two days, so I'm unsure where to start with my rant. I do know that I shouldn't expect results as high as others have due to having dual-rank modules. Also, I only used the 3333MHz timing and resistance configuration that was spit out by 1usmus's calculator (photo attached, using both primary and alternate RFC values when I needed more stability).

I started by trying to get 3333MHz stable. Nothing I tried mattered to get this speed stable. I used a BIOS setting of 1.45V and 1.4V on DRAM (1.5V and 1.45V in HWMonitor) and a BIOS setting of 1.2V on SOC (approximately 1.23V to 1.24V in HWMonitor). I tried using lower SOC voltage values of 1.05V, 1.1V, 1.1125V, 1.125V, 1.13125V, 1.15V, and 1.175V with little to no difference in stability at and beyond 1.1V. I tried using different ProcODT values of 60Ω, 68.6Ω, and 80Ω. 80Ω was the most stable when it came to booting into the OS. 60Ω wouldn't POST, and 68.6Ω was hit and miss. I used the recommended NOM, WR, and PARK values from the calculator and didn't mess with those after that (34Ω, 80Ω, and 240Ω). At this point, I left my DRAM voltage at 1.45V, my SOC voltage at 1.2V, and my ProcODT resistance at 80Ω. CLK, ADDR, CSODT, and CKE settings took me a very long time to find which values were the most stable. I tried 20Ω across the board, and I could rarely boot into the OS without Windows crashing almost instantly as it was trying to boot. 24Ω across the board was almost the same. 30Ω across the board was almost the same too. 30Ω, 30Ω, 40Ω, and 60Ω appeared to have made things slightly more stable because I could boot into the OS a little more frequently with these settings. I kept testing each setting to see which one would boot most frequently into Windows. I wanted to rule out any feeling of placebo, so I really beat the dead horse on this one.

At this point, I know that 3333MHz will not work with the timings spit out by the calculator no matter how hard I try. I at least know which resistance settings are the most stable for my setup though. So, I tried 3200MHz with the same timings. I could easily boot into the OS now, but Prime95 keeps failing no matter what voltage settings I try for both DRAM and SOC. I tried using the alternate RFC timings from the calculator to no avail. So, I tried 3133MHz with the same troubleshooting steps. The only difference now was that Prime95 would last longer but still fail sooner or later.

Going forward, I realized I needed to take down my voltages to more realistic, daily levels and not max them out because I wouldn't be running my system at these voltages anyways. I took my DRAM voltage down to 1.395V in BIOS (almost exactly 1.45V in HWMonitor) and my SOC voltage down to 1.1375V in BIOS (almost exactly 1.175V in HWMonitor). So, I tried 3066MHz with the same timings but more relaxed voltages in Prime95. With Prime95 using 27GB of RAM and Windows reporting slightly less than 29GB of RAM being used overall, it lasted for exactly 3 hours and 30 minutes. I normally run this test for much longer and will do so at another point in time. I'm happy with this result, but I'm pretty sure I can do some more tweaking to help my RAM's performance. What do you think?

For example, in my UserBenchmark result below, my latency is poor compared to some of the other results that are showing almost half of my latency. How do I go about improving that stat? I also wonder if the calculator spit out safe resistance values and correct timings. Could someone simply confirm this? Lastly, how do my dual-rank modules stack up against others' setups (poor, average, good)?

I really appreciate your guys' time. Up next for me is overclocking my CPU, but I'm not going to touch that until I know what settings my RAM likes. I'm going to put all my RAM settings back to stock when I overclock my CPU, and then I'll put everything together and see how it goes from there onward. I hope I'm not forgetting anything else.

http://www.userbenchmark.com/UserRun/11263552

AMD 1800X w/ Phanteks PH-TC14PE
F4-3200C16D-32GTZSK (16GB x 2, Samsung B-die)
ASUS Crosshair 6 Hero (BIOS v6301)

PS: I did forget to state that to get any higher speeds I need to bump DRAM voltage up. That seems to be the main limiting factor in getting more speed. I've read many times that 1.45V is more than likely the highest yet safest voltage to run B-die memory at. Some people run theirs at 1.5V IIRC but who knows.


----------



## kazablanka

DRAM Voltage: 1.45v
VSOC: 1.1v / llc3 - 120% - optimized
CLDO_VDDP: 866
The other memory settings are in the ss


----------



## 1usmus

HeroofTime said:


> Hello everyone,
> 
> I've had my system for almost a year (around 10 months), and finally got around to overclocking my RAM the past two days. I would greatly appreciate your help. This is far from my first time overclocking, so I have a fairly good understanding of most of the settings that tie into overclocking RAM. My system specs that are relevant to this post are listed at the bottom. I've done so much testing the past two days, so I'm unsure where to start with my rant. I do know that I shouldn't expect results as high as others have due to having dual-rank modules. Also, I only used the 3333MHz timing and resistance configuration that was spit out by 1usmus's calculator (photo attached, using both primary and alternate RFC values when I needed more stability).
> 
> I started by trying to get 3333MHz stable. Nothing I tried mattered to get this speed stable. I used a BIOS setting of 1.45V and 1.4V on DRAM (1.5V and 1.45V in HWMonitor) and a BIOS setting of 1.2V on SOC (approximately 1.23V to 1.24V in HWMonitor). I tried using lower SOC voltage values of 1.05V, 1.1V, 1.1125V, 1.125V, 1.13125V, 1.15V, and 1.175V with little to no difference in stability at and beyond 1.1V. I tried using different ProcODT values of 60Ω, 68.6Ω, and 80Ω. 80Ω was the most stable when it came to booting into the OS. 60Ω wouldn't POST, and 68.6Ω was hit and miss. I used the recommended NOM, WR, and PARK values from the calculator and didn't mess with those after that (34Ω, 80Ω, and 240Ω). At this point, I left my DRAM voltage at 1.45V, my SOC voltage at 1.2V, and my ProcODT resistance at 80Ω. CLK, ADDR, CSODT, and CKE settings took me a very long time to find which values were the most stable. I tried 20Ω across the board, and I could rarely boot into the OS without Windows crashing almost instantly as it was trying to boot. 24Ω across the board was almost the same. 30Ω across the board was almost the same too. 30Ω, 30Ω, 40Ω, and 60Ω appeared to have made things slightly more stable because I could boot into the OS a little more frequently with these settings. I kept testing each setting to see which one would boot most frequently into Windows. I wanted to rule out any feeling of placebo, so I really beat the dead horse on this one.
> 
> At this point, I know that 3333MHz will not work with the timings spit out by the calculator no matter how hard I try. I at least know which resistance settings are the most stable for my setup though. So, I tried 3200MHz with the same timings. I could easily boot into the OS now, but Prime95 keeps failing no matter what voltage settings I try for both DRAM and SOC. I tried using the alternate RFC timings from the calculator to no avail. So, I tried 3133MHz with the same troubleshooting steps. The only difference now was that Prime95 would last longer but still fail sooner or later.
> 
> Going forward, I realized I needed to take down my voltages to more realistic, daily levels and not max them out because I wouldn't be running my system at these voltages anyways. I took my DRAM voltage down to 1.395V in BIOS (almost exactly 1.45V in HWMonitor) and my SOC voltage down to 1.1375V in BIOS (almost exactly 1.175V in HWMonitor). So, I tried 3066MHz with the same timings but more relaxed voltages in Prime95. With Prime95 using 27GB of RAM and Windows reporting slightly less than 29GB of RAM being used overall, it lasted for exactly 3 hours and 30 minutes. I normally run this test for much longer and will do so at another point in time. I'm happy with this result, but I'm pretty sure I can do some more tweaking to help my RAM's performance. What do you think?
> 
> For example, in my UserBenchmark result below, my latency is poor compared to some of the other results that are showing almost half of my latency. How do I go about improving that stat? I also wonder if the calculator spit out safe resistance values and correct timings. Could someone simply confirm this? Lastly, how do my dual-rank modules stack up against others' setups (poor, average, good)?
> 
> I really appreciate your guys' time. Up next for me is overclocking my CPU, but I'm not going to touch that until I know what settings my RAM likes. I'm going to put all my RAM settings back to stock when I overclock my CPU, and then I'll put everything together and see how it goes from there onward. I hope I'm not forgetting anything else.
> 
> http://www.userbenchmark.com/UserRun/11263552
> 
> AMD 1800X w/ Phanteks PH-TC14PE
> F4-3200C16D-32GTZSK (16GB x 2, Samsung B-die)
> ASUS Crosshair 6 Hero (BIOS v6301)
> 
> PS: I did forget to state that to get any higher speeds I need to bump DRAM voltage up. That seems to be the main limiting factor in getting more speed. I've read many times that 1.45V is more than likely the highest yet safest voltage to run B-die memory at. Some people run theirs at 1.5V IIRC but who knows.


6XXX series of bios is just awful, I advise you to return to 3502 or 3008 (best for DR)


----------



## Wuest3nFuchs

Wuest3nFuchs said:


> *Samsung E-Die Dual Rank/Sided success *with* Crucial Ballistix Elite BLE8G4D30AEEA.K16FE* 2*8GB *first introduced in 2016*
> 
> 
> One thing that really got me :thinking:
> 
> 
> So i got a really hard time fixing them to run stable over 2133mhz.
> The last 3weeks to run @ rated 3000mhz and after that beyond were i was able to achieve 3200mhz.
> 
> 
> XMP/DOCP didn't worked out well on my Prime X470, let's see what this ram does on the CH7.
> 
> 
> 
> WTH does micron use Samsung Dies? OR is typhoon burner wrong ,no!
> 
> 
> Here's a test https://www.funkykit.com/reviews/me...-elite-16gb-ddr4-3000-cl16-memory-kit-review/



Karhu Ram Test Result:
9000% stable @ 3000mhz


https://imgur.com/a/f0TE04i


----------



## kimoliatisa

AGESA Version	PinnaclePI-AM4 1.0.0.2
Cpu volt(auto) level 3 oc
G Skill FlareX [email protected] 1.45v soc volt 1.2 (best mem for Ryzen):thumb:

CAS Latency (CL)	14T
RAS To CAS Delay (tRCD)	13T
RAS Precharge (tRP)	13T
RAS Active Time (tRAS)	22T

funny think at 3533 the system is unstable but 3600 working like a boss 24/7


----------



## mtrai

kimoliatisa said:


> AGESA Version	PinnaclePI-AM4 1.0.0.2
> Cpu volt(auto) level 3 oc
> G Skill FlareX [email protected] 1.45v soc volt 1.2 (best mem for Ryzen):thumb:
> 
> CAS Latency (CL)	14T
> RAS To CAS Delay (tRCD)	13T
> RAS Precharge (tRP)	13T
> RAS Active Time (tRAS)	22T
> 
> funny think at 3533 the system is unstable but 3600 working like a boss 24/7


Can you post your ryzen timing checker screen shot and all other bios details when you have time?


----------



## kazablanka

Ι had problems with procODT @48ohms ,some times the memory training was failing ,so i moved to 53ohms, i had to change some other values too to be stable with this procODT

DRAM Voltage:1.46v
VSOC voltage: 1.1v
SOC LLC3 / 120% / 300 / optimized


----------



## HeroofTime

@1usmus Do you think I could squeeze more performance out of an older BIOS like those? One thing that doesn't make sense to me is that I finally got 3066MHz stable with much tighter timings (attached), but 3133MHz wasn't stable whatsoever with those loose timings and same voltages shown in the picture in my previous post on the previous page. How does that make any sense?

With the new timings, it boosted my UserBenchmark score to tie with 1st place! I still don't understand how to lower the latency on the RAM though. Also, is it better to round up or round down the three tRFC values that the calculator spits out? Lastly, do the tRFC values tie into any other RAM setting or depend on any other RAM setting? If not, is it safe to assume you can tweak them as you'd wish without any using specific numbers?

Thank you for your time 1usmus. Your calculator is a life saver by the way! 

http://www.userbenchmark.com/UserRun/11322146

PS: I completely missed that the calculator stated to disable PowerDown, but I still have it enabled with no stability issues. It passed Prime95 for hours on end. I'm still going to do more testing though, and will disable it if I run into any stability issues.


----------



## Bapt33

hi,

ive got ryzen 2600 + flare X 3200 CL14, on x370 asus prime, which suck for memory stability on ryzen 2nd generation. So i only can get 3133mhz but i have to set command rate on 2T with powerdown off.
1T with powerdown on give me stability issues, but its because my mobo suck too, so try switch command rate to 2T for more stability, you will not see performance impact


----------



## LillysTittchen

Sorry for the little bit off topic post but I got a strange behaviour after replacing my Radeon R290 (ASUS R9 290 DirectCU II OC 4GB) with a Radeon RX 580 (ASUS ROG Strix Radeon RX 580 OC). When I enable the BIOS option _Windows 10 WHQL Support_ (Default: *Disabled*) and leave BIOS, every further try to access BIOS will end up with a black screen. I can properly boot to Windows but the screen will be black until Windows is loaded.

There are 4 things I noticed:
1. When I enable _Windows 10 WHQL Support_, 2 new Options are visible: Secure Boot and GOP Configuration. When I open GOP Configuration there is no option, just a grey Text with "Unknown driver", "Unknown device"
2. When I enable _Windows 10 WHQL Support_ and leave BIOS, I get a summarization of the changes I applied and an hidden option called _CSM Support_ gets *disabled* (CSM = legacy support AFAIK) too.
3. With my old card I had no problems while _Windows 10 WHQL Support_ was enabled
4. I have no visible option for FastBoot, but I checked my bios file with AMIBCP and there is an option _MSI FastBoot_ and _FastBoot _both *disabled*.

The RX 580 has GOP support, see screenshot, so whats exactly going on here :/ Can someone help?
Thanks in advance!


----------



## 1usmus

Bapt33 said:


> hi,
> 
> ive got ryzen 2600 + flare X 3200 CL14, on x370 asus prime, which suck for memory stability on ryzen 2nd generation. So i only can get 3133mhz but i have to set command rate on 2T with powerdown off.
> 1T with powerdown on give me stability issues, but its because my mobo suck too, so try switch command rate to 2T for more stability, you will not see performance impact



the motherboard limits your result, maybe something will change with the new bios, but 3200 for it is often the maximum result I've seen


----------



## 1usmus

*DRAM Calculator for Ryzen™ 1.4.0​*









*Download :*

*TechpowerUP* -> https://www.techpowerup.com/download/ryzen-dram-calculator/
*Guru3d* -> https://www.guru3d.com/files-details/download-ryzen-dram-calculator.html​*Changelog:*

* Initial support Threadripper gen 1 and gen 2
* Improved SOC voltage prediction for different processors and their generations
* Additional window that will tell what minimum DRAM voltage is needed by the system 
* Additional windows that show a nanosecond delay for the current calculated profile. It will be especially useful for users who are reflashing SPD
* Improved prediction procODT + RTT + CAD_BUS for some memory (the block has endured many changes)
* Improved overclocking for Hynix CJR . Up to 3800 MHz inclusive. Big thanks @Reous for the help
* A switch has been added to define system tasks, BGS / BGSalt recommendations depend on it. Turning off BGS allows you to increase gaming performance by up to 5%
* The "Custom" profile will be based solely on the data that is placed in XMP. Its new name is "Debug". Mode designed from scratch, available for almost all chips (but still need some time for a more subtle configuration).I think this mode is needed for professionals who want to see all the changes relative to automatic overclocking or XMP profile. This will allow them to see some nuances that can not provide the profiles of "V1" and "V2".Also, this mode will be useful to owners of systems based on Intel processors. 
* Some changes in procODT + RTT for systems in which 4 RAM SR modules
* Added support for Micron D-die
* Changes in the code that will help speed up the development of the calculator (future versions)
* Added some popup tips for key settings
* New picture in folder *Configuring Ryzen Systems v5*
* Other corrections/bug fixes


*Changes that are planned in* *Red DRAM Calculator 1.4.1*

* Improved overclocking for Hynix CJR (I hope the company G. Skill will not ignore my proposal), Micron E-die and Micron H-die
* Improved support for Threadripper

Best regards, Iurii Bublii (@1usmus)!


----------



## ilmazzo

thumbs up 1usmus thanks

In the meantime

I'm sitting here

X470 asrock 1.5 bios
2x8gb trident z rgb samsung chip 3200 cl14

trying for a SAFE (rs as you wish) 3466 CL16....I took inspiration from a screenshot of a 3600 setup here so I assume even safer staying at 3466




the part is most misteryous to me is the one regarding the bus configuration, the auto settings are way out than what was for the other setup which where hynix if I recal well.....comments? thanks bye


----------



## rdr09

ilmazzo said:


> thumbs up 1usmus thanks
> 
> In the meantime
> 
> I'm sitting here
> 
> X470 asrock 1.5 bios
> 2x8gb trident z rgb samsung chip 3200 cl14
> 
> trying for a SAFE (rs as you wish) 3466 CL16....I took inspiration from a screenshot of a 3600 setup here so I assume even safer staying at 3466
> 
> 
> 
> 
> the part is most misteryous to me is the one regarding the bus configuration, the auto settings are way out than what was for the other setup which where hynix if I recal well.....comments? thanks bye


Memory Read and Write are very good but the latency is a tad higher than comparable 3200 Cl 14. Guess does not matter much at those speeds.


----------



## ilmazzo

rdr09 said:


> Memory Read and Write are very good but the latency is a tad higher than comparable 3200 Cl 14. Guess does not matter much at those speeds.


I don't know if I'm stable or not atm, I had no time for testing yesterday I will try it in this weekend (just got an aida bench and a R15 run)

The main doubts I have (except for the higher latency) are on the bus part ....

I find difficult to find all the setting in my asrock bios to input what the calculator lists and I see values all over the place regarding others users even with my same exact ram kit.....

p.s: would be greatly appreciated if someone posts a 3466 SAFE setting as a bottomline to where start from....


----------



## kazablanka

Ryzen 2600x + asus prime x470 pro
PBO X10
Vcore 0ffset -0.0625v
DRAM 1.44v
Vsoc 1.0v


----------



## ilmazzo

kazablanka said:


> Ryzen 2600x + asus prime x470 pro
> PBO X10
> Vcore 0ffset -0.0625v
> DRAM 1.44v
> Vsoc 1.0v


jeeeeeez




1,44 dim voltage? Are temps sustainable? during testing which temp you got?


----------



## kazablanka

ilmazzo said:


> jeeeeeez
> 
> 
> 
> 
> 1,44 dim voltage? Are temps sustainable? during testing which temp you got?


39 celsius degrees ,my top case fans push air to vrms and memory


----------



## ilmazzo

2600x default with xfr2 active llc4
Vsoc 1.1 llc 4
Trident z b die [email protected] cl14 1,4v


----------



## kazablanka

ilmazzo said:


> 2600x default with xfr2 active llc4
> Vsoc 1.1 llc 4
> Trident z b die [email protected] cl14 1,4v


What is the resason of llc4 and no auto ?


----------



## ilmazzo

nothing evaluated actually, just "feelings" 

I did not monitored voltages across the benches so i don't know if I have a vdrop that requires an higher or lower llc, think I'm going to start now cause I want to dig down the PBO setting and try to squeeze some more juice from the boost according to the thermal margin I have available....


----------



## Yviena

Is there a big difference between SCL 2 and 3? I don't notice any difference in aida64 but I'm only semi-stable at SCL 2 while totally stable with 3.


----------



## DivineLight

This is my current daily-driving setup. What can I improve in it?

I tried running 3600 CL14 but I couldn't get it stable for at least six hours. CL16 doesn't seem to be worth aiming for unless its 3733+. Are there any people here running those speeds on a daily setup (No insane voltage or benches, stability tested)?

*Used hardware* Ryzen 2700X (4.2 @ Stock Voltage), 4266 GSkill RGB Kit (2 x 8), ASUS Crosshair VII Hero


----------



## CJMitsuki

DivineLight said:


> This is my current daily-driving setup. What can I improve in it?
> 
> I tried running 3600 CL14 but I couldn't get it stable for at least six hours. CL16 doesn't seem to be worth aiming for unless its 3733+. Are there any people here running those speeds on a daily setup (No insane voltage or benches, stability tested)?
> 
> *Used hardware* Ryzen 2700X (4.2 @ Stock Voltage), 4266 GSkill RGB Kit (2 x 8), ASUS Crosshair VII Hero


 Ill tell you something thats will save you a lot of trouble. Ive tested Ryzen and its relation to memory for nearly 2 years and many things changed but something that never changed was the ability of a frequency 1-2 steps lower outperforming the higher frequency with tighter, optimized timings. 3600c14 can be outperformed by 3400-3533c14 depending on the timings, assuming you have a decent CPU/IMC. Performance from bandwidth plateaus around that frequency range and lowering latency and improving the efficiency through timings takes over for performance scaling. My best performing setup is at 3500c14 at the timings below. Also, tighter doesnt always equate to better. There are thresholds that you dont want to cross with timings. Even with no errors there will be adverse effects by pushing too far. You just have to put in the hours of testing and failing many tests before you find the right value for every timing and resistance setting. Now when memory compatibility gets better through updates like with new Agesa updates then ill bump the speed up and test for errors again. Going above Cas 14 will likely not be worth it until 4000mhz is possible and that will all depend on subtimings as well.


----------



## kazablanka

DivineLight said:


> This is my current daily-driving setup. What can I improve in it?
> 
> I tried running 3600 CL14 but I couldn't get it stable for at least six hours. CL16 doesn't seem to be worth aiming for unless its 3733+. Are there any people here running those speeds on a daily setup (No insane voltage or benches, stability tested)?
> 
> *Used hardware* Ryzen 2700X (4.2 @ Stock Voltage), 4266 GSkill RGB Kit (2 x 8), ASUS Crosshair VII Hero


I do but you have to know that cpu needs more voltage from 3533mhz to 3600mhz, in best case +0,02v to vcore to be stable and the difference from 3533mhz is not that much in real world performance


----------



## kazablanka

ilmazzo said:


> nothing evaluated actually, just "feelings"
> 
> I did not monitored voltages across the benches so i don't know if I have a vdrop that requires an higher or lower llc, think I'm going to start now cause I want to dig down the PBO setting and try to squeeze some more juice from the boost according to the thermal margin I have available....


Can you run a cinebench r15 with pbo and see in what speed your cpu run the benchmark? with pbo x10 and -0.1v my cpu keeps 4150mhz at cinebench constant.


----------



## ilmazzo

kazablanka said:


> Can you run a cinebench r15 with pbo and see in what speed your cpu run the benchmark? with pbo x10 and -0.1v my cpu keeps 4150mhz at cinebench constant.


I tried to understand how these settings (is CBS according to the asrock naming of ryzen functions) works but I failed miserably!

I could not see any "pbo multiplier" , just the pstates management for both frequency and votages (but I still got no idea of what voltages is pulling my cpu under heavy loads since I did not understand my bios for this pbo stuff) but is not the road I want to follow.... If I recall well (but I was in summer time so ambient temp was maybe lot hotter than now so not directly comparable to now due to the dynamic temperature boost of ryzen) it seemed between 4ghz on all cores, maybe 4050.......


----------



## kazablanka

ilmazzo said:


> I tried to understand how these settings (is CBS according to the asrock naming of ryzen functions) works but I failed miserably!
> 
> I could not see any "pbo multiplier" , just the pstates management for both frequency and votages (but I still got no idea of what voltages is pulling my cpu under heavy loads since I did not understand my bios for this pbo stuff) but is not the road I want to follow.... If I recall well (but I was in summer time so ambient temp was maybe lot hotter than now so not directly comparable to now due to the dynamic temperature boost of ryzen) it seemed between 4ghz on all cores, maybe 4050.......


You can try to set offset vcore -0.0875v and see if your all core boost clock go higher


----------



## kazablanka

HCI testing

VDRAM 1,44v
VSOC 1,0v


----------



## Synoxia

CJMitsuki said:


> Ill tell you something thats will save you a lot of trouble. Ive tested Ryzen and its relation to memory for nearly 2 years and many things changed but something that never changed was the ability of a frequency 1-2 steps lower outperforming the higher frequency with tighter, optimized timings. 3600c14 can be outperformed by 3400-3533c14 depending on the timings, assuming you have a decent CPU/IMC. Performance from bandwidth plateaus around that frequency range and lowering latency and improving the efficiency through timings takes over for performance scaling. My best performing setup is at 3500c14 at the timings below. Also, tighter doesnt always equate to better. There are thresholds that you dont want to cross with timings. Even with no errors there will be adverse effects by pushing too far. You just have to put in the hours of testing and failing many tests before you find the right value for every timing and resistance setting. Now when memory compatibility gets better through updates like with new Agesa updates then ill bump the speed up and test for errors again. Going above Cas 14 will likely not be worth it until 4000mhz is possible and that will all depend on subtimings as well.
> 
> 
> 
> View attachment 224346



Hey can you share your settings of CH7 where you reach 4.4ghz? Mine is super unstable under -0.06 undervolt and single core voltages worry me...


----------



## DivineLight

I already found out higher timings can be sometimes benefitial. My CPU runs stock, so its about 1.4 - 1.425 V.

My CPU does 4100 - 4150 in Cinebench with XFR, but it varies. In other programs it can only be 4050 MHz or even less. Thats why I'm using a 42 multiplicator, it just works, doesn't apply 1.5 V+ and I can focus on getting the RAM stable. It already hits the 1900 territory in Cinebench with these settings.

How do you use such low SOC voltages? Mine would probably not even boot at 1 V. I lowered it a bit and now it runs better. I already need 1.1 V for 3533. CLDO is at 875, which gave me the three hour run once, CPU_PLL is now 50 mV higher as someone told me it could help.

My PSU is also the best you can get, a Seasonic Prime 650 W Titanium Ultra, a fresh replacement from the time when I had to RMA everything just to find out my CPU was defective... I doubt it could be any hardware-side limitation, only my IMC.


----------



## kazablanka

DivineLight said:


> I already found out higher timings can be sometimes benefitial. My CPU runs stock, so its about 1.4 - 1.425 V.
> 
> My CPU does 4100 - 4150 in Cinebench with XFR, but it varies. In other programs it can only be 4050 MHz or even less. Thats why I'm using a 42 multiplicator, it just works, doesn't apply 1.5 V+ and I can focus on getting the RAM stable. It already hits the 1900 territory in Cinebench with these settings.
> 
> How do you use such low SOC voltages? Mine would probably not even boot at 1 V. I lowered it a bit and now it runs better. I already need 1.1 V for 3533. CLDO is at 875, which gave me the three hour run once, CPU_PLL is now 50 mV higher as someone told me it could help.
> 
> My PSU is also the best you can get, a Seasonic Prime 650 W Titanium Ultra, a fresh replacement from the time when I had to RMA everything just to find out my CPU was defective... I doubt it could be any hardware-side limitation, only my IMC.


You can try my settings and see how it goes ,your ram kit is an ultra high quality such as mine. Uhq chips need less soc voltage to be stable. 
Many times errors in memtest may produced by cpu instability. Set all my memory settings.
Set your v core voltage +0.02v from what you have now,dram voltage 1.44v vsoc 1.0v with llc3/120%/300hz/optimized and test it.Every other memory setting such as cldo leave it to auto. Also set memory interleaving by channel.


----------



## larrydavid

Anyone having luck with full stability with a second-gen threadripper(2950X/2990WX) and dual rank b-die overclocking? I've seen a lot of success on first-gen Threadripper, but myself and others have had a lot of difficulty with second-gen threadripper.


----------



## ZeNch

larrydavid said:


> Anyone having luck with full stability with a second-gen threadripper(2950X/2990WX) and dual rank b-die overclocking? I've seen a lot of success on first-gen Threadripper, but myself and others have had a lot of difficulty with second-gen threadripper.



https://www.overclock.net/forum/13-...lator-1-1-0-beta-2-overclocking-dram-am4.html


----------



## larrydavid

ZeNch said:


> https://www.overclock.net/forum/13-...lator-1-1-0-beta-2-overclocking-dram-am4.html


I'm well aware of the Ryzen Dram Calculator. It doesn't do anything useful for me and others for second-gen threadrippers and dual rank memory. The setting changes I make in the bios regarding RTT values and others do nothing; the changes made in the bios don't reflect in the Ryzen Timing Checker. No setting changes affect stability at all. I believe the current AGESA has issues on Threadrippers.


----------



## ZeNch

larrydavid said:


> ZeNch said:
> 
> 
> 
> https://www.overclock.net/forum/13-...lator-1-1-0-beta-2-overclocking-dram-am4.html
> 
> 
> 
> I'm well aware of the Ryzen Dram Calculator. It doesn't do anything useful for me and others for second-gen threadrippers and dual rank memory. The setting changes I make in the bios regarding RTT values and others do nothing; the changes made in the bios don't reflect in the Ryzen Timing Checker. No setting changes affect stability at all. I believe the current AGESA has issues on Threadrippers.
Click to expand...

Version 1.4 add support for TR (i think in beta)


----------



## larrydavid

ZeNch said:


> Version 1.4 add support for TR (i think in beta)


I'm using 1.4. It's the only tool there is for this, so it's really difficult to tell if RTT is bugged, or the BIOS/Agesa is bugged.


----------



## CJMitsuki

Synoxia said:


> Hey can you share your settings of CH7 where you reach 4.4ghz? Mine is super unstable under -0.06 undervolt and single core voltages worry me...



Ill possibly show you my settings but if you are worried about single core voltages you wont like mine. Ill post my IBT AVX and hwinfo at 4.4 on 1-4 cores and just pay attention to the core voltage under WMI as that is the one that is the actual core voltage after VDroop and what the core is receiving. Also note the temps, especially the Temperature 1 sensor as that is the ambient temp inside the case so if you arent able to cool things very well you will likely burn your cpu up. If you still want my settings for this particular setup then ill still give them to you but im not responsible for what you do with them. Also, I can run with slightly less voltage but Ill fully validate that later. at this voltage I can run 4.4 all core and be fine. Although performance doesnt go up by a ton compared to this setup.


----------



## lowdog

Seems that any DR at over 2933 is a PITA with both TR1 and TR2.....I have tested both (2950X, 1900X, 1920X, MSI X399 MEG, Asrock X399 Fat Pro)! Sometimes it appears stable with 3200MHz but sooner or later for no apparent reason it will throw an error when under a ram stress test with same setting that had previously appeared stable. I am doubtful anyone has REAL stability with DR at over 2933MHz on any Threadripper setup. 


Tested numerous ProcODt values, timings, voltages for dram and SOC, resistances etc blah blah and there was NO secret sauce....something happens when rebooting or restarting or shutting down the system then restarting it that make what had seemed stable under tests become an error thrower when tested again. IMHP of course.


----------



## Synoxia

CJMitsuki said:


> Ill possibly show you my settings but if you are worried about single core voltages you wont like mine. Ill post my IBT AVX and hwinfo at 4.4 on 1-4 cores and just pay attention to the core voltage under WMI as that is the one that is the actual core voltage after VDroop and what the core is receiving. Also note the temps, especially the Temperature 1 sensor as that is the ambient temp inside the case so if you arent able to cool things very well you will likely burn your cpu up. If you still want my settings for this particular setup then ill still give them to you but im not responsible for what you do with them. Also, I can run with slightly less voltage but Ill fully validate that later. at this voltage I can run 4.4 all core and be fine. Although performance doesnt go up by a ton compared to this setup.
> 
> 
> View attachment 224654


Meh that voltage looks bad on all cores... aren't you worried? Why aren't you PBO overclocking? Btw nice Ram OC


----------



## CJMitsuki

Synoxia said:


> Meh that voltage looks bad on all cores... aren't you worried? Why aren't you PBO overclocking? Btw nice Ram OC


 That is PBO OC, its only 1.46v on 1-4 cores and 1.44v on all core. If it were PState OC then youd lose the ability to downvolt. When I apply a hard load such as IBT AVX and it goes to All Core OC on XFR/PBO then the voltages drop a bit as the LLC cant fully control that at 250+ watts. Im not worried about the voltage because voltage isnt what kills an electrical component (unless you add so much that it arcs across the gaps in the integrated circuits) Its the resulting heat caused by said voltage. The only thing voltage alone does is cause Electromigration. If you can control the heat so the hot and cold cycles arent killing the cpu die with that excessive heat or the expansion and contraction due to temp spikes then you get nothing more than normal cpu degradation over time. I have been running 4.4+ ghz on even higher voltages not long after the 2700x launched and since then the cpu has never seen 80c and it rarely even sees 70c aside from really heavy benches and/or tests so to answer your question, Not worried at all. When im benching all night I have the 1-4 core voltages around 1.58v for 6+ hours at a time. Literally no cpu degradation or IMC degradation. Of course I keep a low SoC voltage and DRAM voltages arent gonna do anything. I could run 1.6v daily and theyd be fine with the case temps that low. No need to though as the problem with the ram isnt that, its the Ryzen compatibility atm which will get better with time. Cant complain with the ram performance though. It runs quite beautifully.


Edit: heres with voltage offset lowered by 2 steps to .375v
Took one screen shot during the test and one once it was over. First pic shows the all core and voltage used during the all core boost. Its much lower than when just hanging out with no load before idling.


----------



## christoph

CJMitsuki said:


> That is PBO OC, its only 1.46v on 1-4 cores and 1.44v on all core. If it were PState OC then youd lose the ability to downvolt. When I apply a hard load such as IBT AVX and it goes to All Core OC on XFR/PBO then the voltages drop a bit as the LLC cant fully control that at 250+ watts. Im not worried about the voltage because voltage isnt what kills an electrical component (unless you add so much that it arcs across the gaps in the integrated circuits) Its the resulting heat caused by said voltage. The only thing voltage alone does is cause Electromigration. If you can control the heat so the hot and cold cycles arent killing the cpu die with that excessive heat or the expansion and contraction due to temp spikes then you get nothing more than normal cpu degradation over time. I have been running 4.4+ ghz on even higher voltages not long after the 2700x launched and since then the cpu has never seen 80c and it rarely even sees 70c aside from really heavy benches and/or tests so to answer your question, Not worried at all. When im benching all night I have the 1-4 core voltages around 1.58v for 6+ hours at a time. Literally no cpu degradation or IMC degradation. Of course I keep a low SoC voltage and DRAM voltages arent gonna do anything. I could run 1.6v daily and theyd be fine with the case temps that low. No need to though as the problem with the ram isnt that, its the Ryzen compatibility atm which will get better with time. Cant complain with the ram performance though. It runs quite beautifully.


what?

I oc using Pstate to 4.0 Ghz and it does downclock and downvolt to 1.55 GHz at 0.87 volts


----------



## CJMitsuki

christoph said:


> what?
> 
> I oc using Pstate to 4.0 Ghz and it does downclock and downvolt to 1.55 GHz at 0.87 volts



Hmm, maybe that was just on a setup I was running or couldve been a bug on the CH7 at the time. Meh, Ill try it out tonight and see if it downvolts although ive flashed bios to a newer version since. I dont run PState OC now bc the performance isnt near as good as XFR. Just slightly better latency and you also dont get a single core boost.


Edit: I was wrong on the Pstate not downvolting. It is for me now. mustve been a bios issue at the time.


----------



## DivineLight

Are you sure about 1 V SOC? Because it will not even boot then. 1.025 V is the lowest that boots, 1.05 seem to become stable. I'll let it test over this night. Currently I run a mix of my 3533 and Ryzen Timing Calculators settings.

Is this singlecore turbo really that worth? Its just one core and I noticed it doesn't always work, like in Cinebench. I'm aiming at 4.25 GHz if it will run somehow, maybe just 4.2 because they run with the stock voltage. The temperatures seem to be pretty high with 80°. My VRAM will reach 45 - 47° under load. I'm not sure if that is much because other people told me they use additional fans for stability and reach 70°. But I need a 24/7 setup that will work stable all the time. There are nine fans in this case, the airflow is fantastic, with 50° VRM temperatures under full load.


----------



## CJMitsuki

DivineLight said:


> Are you sure about 1 V SOC? Because it will not even boot then. 1.025 V is the lowest that boots, 1.05 seem to become stable. I'll let it test over this night. Currently I run a mix of my 3533 and Ryzen Timing Calculators settings.
> 
> Is this singlecore turbo really that worth? Its just one core and I noticed it doesn't always work, like in Cinebench. I'm aiming at 4.25 GHz if it will run somehow, maybe just 4.2 because they run with the stock voltage. The temperatures seem to be pretty high with 80°. My VRAM will reach 45 - 47° under load. I'm not sure if that is much because other people told me they use additional fans for stability and reach 70°. But I need a 24/7 setup that will work stable all the time. There are nine fans in this case, the airflow is fantastic, with 50° VRM temperatures under full load.



Dont run it at high temps. I run chilled air through my case and my VRMs run around 40c max and 22-24c normal operating temp. You have to have something more than normal air flowing through your case. I currently have 8 fans in my case and its in a Silverstone RL06 which is a very small case but has amazing airflow and my home A/C is routed through my case with an adapter and through the side blowing onto the gpu for now. gpu idles at 14c at the lowest and cpu is around 18c give or take 1-2c. Dont try to add a positive offset without some way to drop temps a bit more. I also run liquid metal on the cpu and kryonaut on my gpu. Just run Performance enhancer on auto and xfr setup with pbo enabled and that should give you a stable setup then just tune your offset to match the temps you want. About Soc voltage, that is going to vary according to ram. Every set is going to have a specific Soc voltage that it likes. Its up to you to test and find that voltage. Its determined by the silicon and you cant just go on someone elses voltage and expext it to work. Just test a voltage and then bump it up when it fails and test again and keep trying that until you find the right SoC voltage. Mine happens to be 1.05v at low frequency (below 3200mhz) and 1.1v for everything else.


----------



## kazablanka

DivineLight said:


> Are you sure about 1 V SOC? Because it will not even boot then. 1.025 V is the lowest that boots, 1.05 seem to become stable. I'll let iχt test over this night. Currently I run a mix of my 3533 and Ryzen Timing Calculators settings.
> 
> Is this singlecore turbo really that worth? Its just one core and I noticed it doesn't always work, like in Cinebench. I'm aiming at 4.25 GHz if it will run somehow, maybe just 4.2 because they run with the stock voltage. The temperatures seem to be pretty high with 80°. My VRAM will reach 45 - 47° under load. I'm not sure if that is much because other people told me they use additional fans for stability and reach 70°. But I need a 24/7 setup that will work stable all the time. There are nine fans in this case, the airflow is fantastic, with 50° VRM temperatures under full load.


Υes iam sure ,everythig works full stable with 1v on soc. Maybe depends on imc. Have you tried all the settings i wrote you?

I have do also a test with 3600mhz on ram with just enabling xmp, i left it all night running hci and its full stable.
I think your air flow is not very good. My ram at 3600mhz with fast timing and 1.44v after running hcimemtest for hours was about 40c .


----------



## alawadhi3000

larrydavid said:


> Anyone having luck with full stability with a second-gen threadripper(2950X/2990WX) and dual rank b-die overclocking? I've seen a lot of success on first-gen Threadripper, but myself and others have had a lot of difficulty with second-gen threadripper.


Best I could do is 3133MHz CL14 @ 1.39V RAM / 1.0875V SoC.

Anything above 3133MHz even with a loose timings throws an error while testing for stability.


----------



## lowdog

alawadhi3000 said:


> Best I could do is 3133MHz CL14 @ 1.39V RAM / 1.0875V SoC.
> 
> Anything above 3133MHz even with a loose timings throws an error while testing for stability.



we are talking quad channell DR (Dual Rank dimms) so 4 x 16GB modules. Your sig says 32GB so if quad channell that would be 4 x 8GB SR (Singl Rank dimms) because I would assume you would not be running 2 x 16GB DR dimms in dual channell on Threadripper as it makes no sence.


----------



## rdr09

kazablanka said:


> Υes iam sure ,everythig works full stable with 1v on soc. Maybe depends on imc. Have you tried all the settings i wrote you?
> 
> I have do also a test with 3600mhz on ram with just enabling xmp, i left it all night running hci and its full stable.
> I think your air flow is not very good. My ram at 3600mhz with fast timing and 1.44v after running hcimemtest for hours was about 40c .


I noticed my G.Skill FlareX @ 3200 Cl14 throws out errors above 40c. Even with good airflow. Must be the design of the fins. I have to underclock it down to 3125 MHz to keep it around 40 in gaming.


----------



## alawadhi3000

lowdog said:


> we are talking quad channell DR (Dual Rank dimms) so 4 x 16GB modules. Your sig says 32GB so if quad channell that would be 4 x 8GB SR (Singl Rank dimms) because I would assume you would not be running 2 x 16GB DR dimms in dual channell on Threadripper as it makes no sence.


You are the only one talking about Quad Channel Dual Rank memory, he didn't mention that and in one of his older posts he said that he has a 2x16GB kit just like me.

Yeah I'm running a DR 2x16GB on a Threadripper (And on x99 before that), and it makes sense for my typical use.


----------



## lowdog

alawadhi3000 said:


> You are the only one talking about Quad Channel Dual Rank memory, he didn't mention that and in one of his older posts he said that he has a 2x16GB kit just like me.
> 
> Yeah I'm running a DR 2x16GB on a Threadripper (And on x99 before that), and it makes sense for my typical use.




Well excuse me.


----------



## CJMitsuki

rdr09 said:


> I noticed my G.Skill FlareX @ 3200 Cl14 throws out errors above 40c. Even with good airflow. Must be the design of the fins. I have to underclock it down to 3125 MHz to keep it around 40 in gaming.


Could be how the case and your fans push that air. Some cases have dead spots where turbulence from the air of several fans collide causing areas in the case not to have air passing over them near as much. I made myself a memory cooler from an old gtx 660 cooler. fans blow straight onto the dimm plus I have a RL06 which has the whole front pretty much wide open and its a smaller case. I placed the fans so the airflow isnt directly hitting air from another fan and made sure the a.irflow was flowing across the dimms especially. Theres 8 Noctuas in my case now and two small fans for the memory cooler in that tiny case so it moves a massive amount of air with positive pressure. My dimms stay nice and cool but one is always 2c hotter as its the one that is behind the other and doesnt get the full blast of the fresh air entering the case but thats np. You probably dont run your fans as aggressively as i do. At 65c on the cpu my fans are at 2600rpm+ and only at 85% of full speed. Noctua AF-14 ippc-3000 are a beast of a fan and are literally water resistant not to mention one of the most powerful fans you can get. 8 of those can nearly lift my case off of my desk like a helicopter. Dont ever let one hit your fingers either when you reach inside your case. I promise youll only let it happen once. They are also whisper quiet at lower speeds.


----------



## nexxusty

Finally got a "Game Stable" result @ 3200mhz out of a 2400mhz Hynix MFR kit.

CL14-15-15-15-28 @ 1.44v. Tons of airflow. Really good for a budget kit, I just wanted Destiny 2 to run a bit better. Hehe.

Since I took it from 2400mhz all the way up to 3200mhz, the difference with my 1060 6GB at 1080p is ridiculous.... I'm seeing around 15-20% increase here. Love Ryzen for this. Hehe.


----------



## gupsterg

rdr09 said:


> I noticed my G.Skill FlareX @ 3200 Cl14 throws out errors above 40c. Even with good airflow. Must be the design of the fins. I have to underclock it down to 3125 MHz to keep it around 40 in gaming.


Perhaps it's not the RAM. I see a lot about RAM temps being thrown around, I for one can't see it in my tests.

My TR+ZE rig lacks airflow, even though I have modded case to have mesh at front and removed plastic behind mesh in top panel.



Spoiler














I have a rad at front (360mm) and same at top of case, front fans as intake and top as exhaust. Then I only have the rear case fan as exhaust, PSU fan is really not helping exhausting in case as it's fitted fan down.

RTC info in below screenies is not read back correct on later AGESA UEFI.

DIMM Config: 1DPC-SR
ProcODT: 60
CAD Bus Timings: 0/0, 0/0, 0/0
RTT: Off, Off, 48
CAD Bus Resistances: 24, 24, 24, 24

(SOC: 1.05V VDIMM: 1.35V)



Spoiler
















Spoiler














I also have a set of F4-3200C14Q-32GVK, I've used them with C6H, C7H and ZE. Even though you would think the Trident Z in above screenies would be better due to solid lumps of heatsink on them, the RipJaw V set actually tightens up more.



nexxusty said:


> Finally got a "Game Stable" result @ 3200mhz out of a 2400mhz Hynix MFR kit.
> 
> CL14-15-15-15-28 @ 1.44v. Tons of airflow. Really good for a budget kit, I just wanted Destiny 2 to run a bit better. Hehe.
> 
> Since I took it from 2400mhz all the way up to 3200mhz, the difference with my 1060 6GB at 1080p is ridiculous.... I'm seeing around 15-20% increase here. Love Ryzen for this. Hehe.


Sweeet!  .


----------



## DivineLight

You use dual-channel memory on a quadchannel platform? You are sacrificing performance then. When I still had the quadchannel X99 platform I never felt the need of expensive RAM since my Micron-B-Dies at 2400 MHZ CL17 would still outperform 4000 MHz RAM in quadchannel mode and 4000 didn't exist yet when I bought it. TR can reach over 100 GB/s of memory bandwith.


----------



## gupsterg

DivineLight said:


> You use dual-channel memory on a quadchannel platform? You are sacrificing performance then. When I still had the quadchannel X99 platform I never felt the need of expensive RAM since my Micron-B-Dies at 2400 MHZ CL17 would still outperform 4000 MHz RAM in quadchannel mode and 4000 didn't exist yet when I bought it. TR can reach over 100 GB/s of memory bandwith.


"sacrificing"!? :thinking:









Above is without using any OS tweaks and UEFI Performance Bias tweaks.

I think you have mis-read or understood something in my previous post :thinking: . I'd re-read it and see the screen shots again in previous post.

1DPC-SR = 1 dimm per channel, single rank

In the HWINFO screenies you'll see 4 dimm temperatures, so 4 dimms = quad channel in use.


----------



## rdr09

CJMitsuki said:


> Could be how the case and your fans push that air. Some cases have dead spots where turbulence from the air of several fans collide causing areas in the case not to have air passing over them near as much. I made myself a memory cooler from an old gtx 660 cooler. fans blow straight onto the dimm plus I have a RL06 which has the whole front pretty much wide open and its a smaller case. I placed the fans so the airflow isnt directly hitting air from another fan and made sure the a.irflow was flowing across the dimms especially. Theres 8 Noctuas in my case now and two small fans for the memory cooler in that tiny case so it moves a massive amount of air with positive pressure. My dimms stay nice and cool but one is always 2c hotter as its the one that is behind the other and doesnt get the full blast of the fresh air entering the case but thats np. You probably dont run your fans as aggressively as i do. At 65c on the cpu my fans are at 2600rpm+ and only at 85% of full speed. Noctua AF-14 ippc-3000 are a beast of a fan and are literally water resistant not to mention one of the most powerful fans you can get. 8 of those can nearly lift my case off of my desk like a helicopter. Dont ever let one hit your fingers either when you reach inside your case. I promise youll only let it happen once. They are also whisper quiet at lower speeds.


I'll set the two top fans to exhaust and see if that makes a difference. The rear is the only exhaust. Thanks.


----------



## CJMitsuki

rdr09 said:


> CJMitsuki said:
> 
> 
> 
> Could be how the case and your fans push that air. Some cases have dead spots where turbulence from the air of several fans collide causing areas in the case not to have air passing over them near as much. I made myself a memory cooler from an old gtx 660 cooler. fans blow straight onto the dimm plus I have a RL06 which has the whole front pretty much wide open and its a smaller case. I placed the fans so the airflow isnt directly hitting air from another fan and made sure the a.irflow was flowing across the dimms especially. Theres 8 Noctuas in my case now and two small fans for the memory cooler in that tiny case so it moves a massive amount of air with positive pressure. My dimms stay nice and cool but one is always 2c hotter as its the one that is behind the other and doesnt get the full blast of the fresh air entering the case but thats np. You probably dont run your fans as aggressively as i do. At 65c on the cpu my fans are at 2600rpm+ and only at 85% of full speed. Noctua AF-14 ippc-3000 are a beast of a fan and are literally water resistant not to mention one of the most powerful fans you can get. 8 of those can nearly lift my case off of my desk like a helicopter. Dont ever let one hit your fingers either when you reach inside your case. I promise youll only let it happen once. They are also whisper quiet at lower speeds.
> 
> 
> 
> I'll set the two top fans to exhaust and see if that makes a difference. The rear is the only exhaust. Thanks.
Click to expand...

You can check gamers nexus as they review tons of cases and have airflow data on nearly all of them showing them at stock fan configuration as well as other fan configurations giving ideas as to which way is best for a particular case. It also ranks those cases giving an idea about which are best for airflow and kept the components at the best T Delta. That’s how I chose my case specifically. Case was right at 100$ and had nearly the best airflow of any case, even 200$ cases. I could’ve went with the same model with a metal and plastic side panel for 85 but I got the tempered glass one instead. Only gripe is the lack of a reset button but I just used my soldering iron to remove a momentary release button from another PCB and wire it to a reset button connector so I could use it on the mobo then drilled and mounted it so it could be accessed from outside the case. Airflow in this case is amazing as I have currently 4 of the 140mm fans on the front with my 280mm rad in a push pull as the main intake and two 140mm exhausting through the top and another exhausting outlet the back and a final 140mm that I custom mounted to blow more cool air into the gpu directly. Then the 2 tiny fans blowing directly onto the dimms. PSU is separated as the case has a basement shroud so there’s no heat transfer from it. I was going to remove it for more room but Gamers Nexus showed that it affected airflow performance considerably so I scrapped that idea. All fans stay at least 1500rpm and are very quiet. The memory cooler fan are the ones that I can hear the most as they do t have the high quality bearings that the Noctuas have or the anti vibration notches and pads.


----------



## CJMitsuki

gupsterg said:


> DivineLight said:
> 
> 
> 
> You use dual-channel memory on a quadchannel platform? You are sacrificing performance then. When I still had the quadchannel X99 platform I never felt the need of expensive RAM since my Micron-B-Dies at 2400 MHZ CL17 would still outperform 4000 MHz RAM in quadchannel mode and 4000 didn't exist yet when I bought it. TR can reach over 100 GB/s of memory bandwith.
> 
> 
> 
> "sacrificing"!? /forum/images/smilies/thinking.gif
> 
> View attachment 225238
> 
> 
> Above is without using any OS tweaks and UEFI Performance Bias tweaks.
> 
> I think you have mis-read or understood something in my previous post /forum/images/smilies/thinking.gif . I'd re-read it and see the screen shots again in previous post.
> 
> 1DPC-SR = 1 dimm per channel, single rank
> 
> In the HWINFO screenies you'll see 4 dimm temperatures, so 4 dimms = quad channel in use.
Click to expand...

That’s a really good result for that amount of memory especially on the Threadripper. Usually you don’t see much more than 3200. This reaffirms my notion that the G.Skill 3200c14 single rank dimms are the most versatile and best performing memory for AMD at present. I’m glad I got mine before the massive price hike before first gen launch. Only wish I had gotten 2 sets.


----------



## kazablanka

rdr09 said:


> I noticed my G.Skill FlareX @ 3200 Cl14 throws out errors above 40c. Even with good airflow. Must be the design of the fins. I have to underclock it down to 3125 MHz to keep it around 40 in gaming.


My top fans push air to my ram sticks, here is my setup and hci testing temps


----------



## gupsterg

CJMitsuki said:


> That’s a really good result for that amount of memory especially on the Threadripper. Usually you don’t see much more than 3200. This reaffirms my notion that the G.Skill 3200c14 single rank dimms are the most versatile and best performing memory for AMD at present. I’m glad I got mine before the massive price hike before first gen launch. Only wish I had gotten 2 sets.


+1 :thumb: , you would weep knowing what I paid for F4-3200C14D-16GTZ back in Q1 2017 (I know I do knowing what the kits cost after that  ).

It's like catnip to Ryzen IMC  .

Below is RipJaws 3200MHz C14 @ 3466MHz VDIMM 1.35V on R7 2700X+C7H.



Spoiler


----------



## Yvese

So while testing with memtest is it normal to have half of the instances be roughly 100% behind the other half? ie with my 2600x I have 12 instances and after 1 hour half of them will be at say 200% and the other will be around 100%. I'm assuming it's because half are using the real cores while the other are coming from threads. Then when I look at screenshots of others running memtest everyone's instances are near equal so I'm a bit worried and confused.

EDIT: Could it be because I'm putting too much ram in memtest? I have 16gb but on desktop with nothing running I have around 13-13.5gb left so for each instance I put 1050 which totals 12.6gb. Thing is when I look at my available memory after starting the test it shows I still have 1gb left even if I had 13gb before running the test. Could it be using pagefile?


----------



## Aretak

Is it possible for a chip to just not be able to do anything better than 3200MHz, or am I just sucking at finding the sweet spot? I've spent hours trying to get something above that running on my 2700X, and whilst I can get to the point that games and day to day applications seem stable enough, it will never, ever past memtest (failing out relatively quickly too). On the other hand, I can run 3200MHz with timings tighter than the fast preset in the calculator without issue and fully stable. It just seems like my chip absolutely refuses to do any clock speed above that. I've tried 3333, 3400 and 3466 all without success and tweaked and retweaked every voltage and timing that the calculator and flowchart have listings for. Using a 3866MHz C18 G.Skill B-die kit and a Crosshair VI for reference.


----------



## DivineLight

Did you increase the voltage? 3600 crashed within seconds or minutes for me, now I can run it a few hours at 1.48 V. 3533 will run fine at 1.43 V. It seems to be less an issue with the SOC voltage for me, so its probably right Zen+ needs less SOC. When I noticed it to crash very quick it was usually too low voltage.


----------



## Aretak

DivineLight said:


> Did you increase the voltage? 3600 crashed within seconds or minutes for me, now I can run it a few hours at 1.48 V. 3533 will run fine at 1.43 V. It seems to be less an issue with the SOC voltage for me, so its probably right Zen+ needs less SOC. When I noticed it to crash very quick it was usually too low voltage.


Yeah, I've gone up to 1.45V on the memory and it changed nothing. I'm not comfortable going higher than that for "only" 3466. I've even tried the safe timings from the calculator at higher voltages and even those weren't stable. I've had the memory kit running at its rated 3866 in an Intel system via XMP without issues, so I know it's "good" so to speak. It's just irritating me at this point, even if the gains would be minor from a very tight 3200.


----------



## DivineLight

I think even 1.45 V is too low, I tried that too, but it would go unstable after a few seconds or minutes. My record so far is five hours. 3200 to 3466 is a slight difference, after that the difference is probably nonexistant if you run 3466 at very tight settings. So 3600 remains as a dream.

I bought these kits for future proofing, so I will not have problems with future CPUs. 4266 is one of the fastest kits you can currently buy and I wish Zen 2 supported it and scaled as well as it if Zen does with lower speeds. The results seem fantastic, even at 3533 CL14 you get Min-FPS like with Intel-CPUs.


----------



## gupsterg

Yvese said:


> So while testing with memtest is it normal to have half of the instances be roughly 100% behind the other half? ie with my 2600x I have 12 instances and after 1 hour half of them will be at say 200% and the other will be around 100%. I'm assuming it's because half are using the real cores while the other are coming from threads. Then when I look at screenshots of others running memtest everyone's instances are near equal so I'm a bit worried and confused.
> 
> EDIT: Could it be because I'm putting too much ram in memtest? I have 16gb but on desktop with nothing running I have around 13-13.5gb left so for each instance I put 1050 which totals 12.6gb. Thing is when I look at my available memory after starting the test it shows I still have 1gb left even if I had 13gb before running the test. Could it be using pagefile?


I can't say I have had such a big gap. Does not matter if I have used Ryzen gen1/2 with C6H or C7H and even on TR+ZE. It's more like below ~50% from highest% instance and lowest % instance, I have done runs of over 7hrs at times.

Run something like HWINFO, fire up the HCI test and you should be able to see instantly in HWINFO if the settings used for HCI loaded up the pagefile.


----------



## 1usmus

Aretak said:


> Is it possible for a chip to just not be able to do anything better than 3200MHz, or am I just sucking at finding the sweet spot? I've spent hours trying to get something above that running on my 2700X, and whilst I can get to the point that games and day to day applications seem stable enough, it will never, ever past memtest (failing out relatively quickly too). On the other hand, I can run 3200MHz with timings tighter than the fast preset in the calculator without issue and fully stable. It just seems like my chip absolutely refuses to do any clock speed above that. I've tried 3333, 3400 and 3466 all without success and tweaked and retweaked every voltage and timing that the calculator and flowchart have listings for. Using a 3866MHz C18 G.Skill B-die kit and a Crosshair VI for reference.


try 3502 bios, the problem is not in memory and not in the processor

Single errors are module overheating (over 52 degrees) or incorrect secondary timings, such as tFAW, for example. Mass errors are *procODT*, *RTT* and voltages.

When you find successful procODT, RTT, and voltages, you need to configure secondary and tertiary timings (tRRDS , tFAW , tRTP, tRDWR , tWRRD).


----------



## Yvese

gupsterg said:


> I can't say I have had such a big gap. Does not matter if I have used Ryzen gen1/2 with C6H or C7H and even on TR+ZE. It's more like below ~50% from highest% instance and lowest % instance, I have done runs of over 7hrs at times.
> 
> Run something like HWINFO, fire up the HCI test and you should be able to see instantly in HWINFO if the settings used for HCI loaded up the pagefile.


HWINFO shows 0-1% pagefile usage so I think I can rule that out. I ran memtest for 5 hours and attached a screenshot below. Also attached my current timings and Aida bench. As you can see, half of the instances are much slower but show 0 errors. Really not sure what's going on. I ran userbench and it says my ram is at 97th percentile so my ram doesn't seem to be 'slower'.


----------



## nexxusty

Ugh, finally getting a nice kit of B-Die again. I haven't went with Patriot for a long time.... but this is the ONLY B-Die in Canada you can get from Amazon.

This is the kit: https://www.amazon.ca/gp/product/B07CX6WK5G/ref=oh_aui_detailpage_o00_s00?ie=UTF8&psc=1

I'm told this benches VERY well, among the best for a Single Sided kit. That, B-Die, and 3600mhz will make my 2700x very happy. I currently have Hynix MFR @ 3200mhz 14-15-15-15-28-1T with this IMC, I cannot wait to see what this kit can do.

That and I'm getting some decent Internet here, 25/5. Now don't laugh, I'm rural and my modem is wireless. This new modem they are installing is going to be amazing. 4K streaming will finally work in my place. 

Going to be a great week! Cheers boys!



1usmus said:


> try 3502 bios, the problem is not in memory and not in the processor
> 
> Single errors are module overheating (over 52 degrees) or incorrect secondary timings, such as tFAW, for example. Mass errors are *procODT*, *RTT* and voltages.
> 
> When you find successful procODT, RTT, and voltages, you need to configure secondary and tertiary timings (tRRDS , tFAW , tRTP, tRDWR , tWRRD).


I would like to personally thank you for the time you put into the Ryzen RAM Calculator application. Thank you.

I was able to take my lowly Hynix MFR 8GB kit to 3200mhz 14-15-15-15-28-1T with this tool. Very much appreciated.


----------



## Moparman

The Team Dark pro 3200c14 Bdie ia also a very good kit for Ryzen.


----------



## Yviena

1usmus said:


> Aretak said:
> 
> 
> 
> Is it possible for a chip to just not be able to do anything better than 3200MHz, or am I just sucking at finding the sweet spot? I've spent hours trying to get something above that running on my 2700X, and whilst I can get to the point that games and day to day applications seem stable enough, it will never, ever past memtest (failing out relatively quickly too). On the other hand, I can run 3200MHz with timings tighter than the fast preset in the calculator without issue and fully stable. It just seems like my chip absolutely refuses to do any clock speed above that. I've tried 3333, 3400 and 3466 all without success and tweaked and retweaked every voltage and timing that the calculator and flowchart have listings for. Using a 3866MHz C18 G.Skill B-die kit and a Crosshair VI for reference.
> 
> 
> 
> try 3502 bios, the problem is not in memory and not in the processor
> 
> Single errors are module overheating (over 52 degrees) or incorrect secondary timings, such as tFAW, for example. Mass errors are *procODT*, *RTT* and voltages.
> 
> When you find successful procODT, RTT, and voltages, you need to configure secondary and tertiary timings (tRRDS , tFAW , tRTP, tRDWR , tWRRD).
Click to expand...

Do you maybe know why ram that is stable and has passed hci 2000%, and memtest5 16 cycles becomes unstable after a shutdown/reboot with the exact same timings and temperatures?

EDIT: memclear disabled fixed stability between reboots.


----------



## Sarkoth

Managed to get 2 kits of 2x16 GB Corsair Vengeance LPX 3200 CL16 running at 3466 and 3533 respectively on their own, the former being Hynix M, the latter kit being Samsung B, both dual rank. Together they only run at 3200 16 18 18 36 with 1.39V but they are rock solid.

Crosshair VII
R5 2600 @ 4.0 manual all-core with ~1.36V on auto and 23°C idle and ~60℃ under AIDA stress test or Prime95. Going to try higher after some prolonged heavy load testing
SOC 1.1635
PLL 1.7

Didnt manage for the life of me to tighten timings of the full 64GB RAM rack though. Not even sub timings budged an inch. Averages ~50000 on bench. Guess it's fine for a temporary system until Zen2 drops though.


----------



## DivineLight

Anyone here ever tried to overclock *Micron B-Dies*? I managed to get my old 3000 CL18 overclock working again, but I'm not really happy with it. Its a 4x4 config and won't even boot 3200. The RAM is a 2400 CL17 kit from 2016 that I previously used for my Quadchannel X99 rig, but now was reused in my Ryzen 1700 HTPC.


----------



## larrydavid

For you Asrock Threadripper owners, there's a new AGESA update in a beta BIOS.

3.33D "Update ThreadRipperPI-SP3r2 1.1.0.2(BETA)"

https://www.asrock.com/support/index.asp?cat=bBIOS

I'm hoping this will solve some dual rank memory overclocking issues.


----------



## DivineLight

I managed to find the setting that reduced my latency. And its still working! Which timings would you adjust? trcdrd to 14 will cause errors after a few hours.


----------



## kazablanka

new cpu same stability


----------



## nick name

kazablanka said:


> new cpu same stability


Try this. It's stable for me. I have to run 1.5V on DRAM though.


----------



## kazablanka

nick name said:


> Try this. It's stable for me. I have to run 1.5V on DRAM though.


Thanks i'll give them a try ,but i dont want to run so high volrages for 24/7. I try to stay as low as i can on voltages.


----------



## glnn_23

A little stability testing with stressapptest

vdimm 1.425v
vddsoc 1.1v


----------



## Duvar

Any ideas what i should try next? This is what i am running atm.
1. Pic with 24/7 settings, second with higher cpu oc.
Maybe i should change the fan above the ram to intake for better temps.
I am using 3600CL17 Gskill RGB RAM with Samsung B Dies.


----------



## ilmazzo

Which voltage for the ram? Wonderful aida sir



Duvar said:


> Any ideas what i should try next? This is what i am running atm.
> 1. Pic with 24/7 settings, second with higher cpu oc.
> Maybe i should change the fan above the ram to intake for better temps.
> I am using 3600CL17 Gskill RGB RAM with Samsung B Dies.


----------



## Duvar

1.482V under load as seen in HardwareInfo64 for 3600MHz.
I lowered clocks a bit for even lower voltages and this is the result 3535MHz with lil better timings and 1.465V.
What do you think, what profile is better, 3600 or 3535?


----------



## nick name

Duvar said:


> 1.482V under load as seen in HardwareInfo64 for 3600MHz.
> I lowered clocks a bit for even lower voltages and this is the result 3535MHz with lil better timings and 1.465V.
> What do you think, what profile is better, 3600 or 3535?


Shouldn't Tcl and Tcwl be the same? And at lower speeds like 3535 you might be able to do 14-14-14-14. At least that has been my experience. Once I get to 3600 I have to use 14-15-14-14.


----------



## ilmazzo

So the 1493 cinebench screen and aida is the one at 3600?

I would prefer the sub 60ns result setting, since mine is used especially for gaming I would tend on low latency settings instead of high bandwidth

I would like to see the lowest timings possible at which frequency levels and decide which more effective route follow

2666 cl12

Or 3466 cl14

I want to stay at 1,4v max at dimms





Duvar said:


> 1.482V under load as seen in HardwareInfo64 for 3600MHz.
> I lowered clocks a bit for even lower voltages and this is the result 3535MHz with lil better timings and 1.465V.
> What do you think, what profile is better, 3600 or 3535?


----------



## Duvar

Both CB Scores are with 3600, but cpu clock is lower in one of the pics.

Now this is what i am trying for now with 1.465V RAM Voltage:


----------



## ilmazzo

Ok thanks for clarifying 

I’m near that setup but with 1,4v and 3400 

I will try 3466 and see if it is stable

Then i will try the lowest timings possible on ddr4 and decide where to go

Anyway my 2600x could not manage 4,[email protected],4v all cores so I don’t know if overclocking it the old way will bring much to the table instead of leaving on pbo and xfr




Duvar said:


> Both CB Scores are with 3600, but cpu clock is lower in one of the pics.
> 
> Now this is what i am trying for now with 1.465V RAM Voltage:


----------



## Duvar

I was told, that Samsung B Dies are laughing about 1.5V, the guy told be 1.5V is no problem at all for Samsung B Dies 24/7.
But if they get over 55°C, they get instable, he said, so lower voltages are ofc better, but how much will you sacrifice?^^
I think our RAM is nearly perfect tuned, i have now 3 Profiles, 3466/3533/3600, dont think, that any of these profiles are a lot better than the other one.
I am looking forward for Zen 2, my 2600 will go to my second PC, i hope we can push RAM even further with Zen 2.
Anyway, thx for your input.


----------



## 1usmus

Duvar said:


> 1.482V under load as seen in HardwareInfo64 for 3600MHz.
> I lowered clocks a bit for even lower voltages and this is the result 3535MHz with lil better timings and 1.465V.
> What do you think, what profile is better, 3600 or 3535?


HWinfo is not an exact "device" for measurements, you should focus only on those values that you entered in the BIOS


----------



## mtrai

Duvar said:


> I was told, that Samsung B Dies are laughing about 1.5V, the guy told be 1.5V is no problem at all for Samsung B Dies 24/7.
> But if they get over 55°C, they get instable, he said, so lower voltages are ofc better, but how much will you sacrifice?^^
> I think our RAM is nearly perfect tuned, i have now 3 Profiles, 3466/3533/3600, dont think, that any of these profiles are a lot better than the other one.
> I am looking forward for Zen 2, my 2600 will go to my second PC, i hope we can push RAM even further with Zen 2.
> Anyway, thx for your input.


I keep worndering how people getting over such high ram temps? I have been running these B-die G.SKILL TridentZ RGB Series 16GB (2 x 8GB) 288-Pin DDR4 4133MHz (PC4 33000) Desktop Memory Model F4-4133C19D-16GTZR https://www.amazon.com/gp/product/B01NCV4CY8/ref=oh_aui_detailpage_o06_s00?ie=UTF8&psc=1 

at 1.48 volts almost from day one with no temp issues. It rarely ever even hits 35 celsius at 3600+ at CL 14 and very tight timings. Ambient though is 26 -27 celsius.


----------



## nick name

mtrai said:


> I keep worndering how people getting over such high ram temps? I have been running these B-die G.SKILL TridentZ RGB Series 16GB (2 x 8GB) 288-Pin DDR4 4133MHz (PC4 33000) Desktop Memory Model F4-4133C19D-16GTZR https://www.amazon.com/gp/product/B01NCV4CY8/ref=oh_aui_detailpage_o06_s00?ie=UTF8&psc=1
> 
> at 1.48 volts almost from day one with no temp issues. It rarely ever even hits 35 celsius at 3600+ at CL 14 and very tight timings. Ambient though is 26 -27 celsius.


Mine only get into the 40s when I am testing them. Gaming can reach 38, but that was during the summer when my room temp was pretty warm.


----------



## ilmazzo

26c ambient and 35 at 1,48? Well you have to cool them with something then, i get even 42 at 1,4 3400 cl14 and I have a decent airflow

Ps: during testing too


mtrai said:


> Duvar said:
> 
> 
> 
> I was told, that Samsung B Dies are laughing about 1.5V, the guy told be 1.5V is no problem at all for Samsung B Dies 24/7.
> But if they get over 55°C, they get instable, he said, so lower voltages are ofc better, but how much will you sacrifice?^^
> I think our RAM is nearly perfect tuned, i have now 3 Profiles, 3466/3533/3600, dont think, that any of these profiles are a lot better than the other one.
> I am looking forward for Zen 2, my 2600 will go to my second PC, i hope we can push RAM even further with Zen 2.
> Anyway, thx for your input.
> 
> 
> 
> I keep worndering how people getting over such high ram temps? I have been running these B-die G.SKILL TridentZ RGB Series 16GB (2 x 8GB) 288-Pin DDR4 4133MHz (PC4 33000) Desktop Memory Model F4-4133C19D-16GTZR https://www.amazon.com/gp/product/B01NCV4CY8/ref=oh_aui_detailpage_o06_s00?ie=UTF8&psc=1
> 
> at 1.48 volts almost from day one with no temp issues. It rarely ever even hits 35 celsius at 3600+ at CL 14 and very tight timings. Ambient though is 26 -27 celsius.
Click to expand...


----------



## nexxusty

Alright, one more time around with Ryzen + and Memory clocking. 2700x, TWO 16gb 3600mhz B-Die kits..... Lets do this. One was free too. I LOVE Amazon. Hehe.

Best one stays.

MY Halloween is going to be the best! Have fun you guys!


----------



## Duvar

I get those temps only if stress testing, not gaming.


----------



## Yvese

Doesn't increasing memory voltage also indirectly pump it to your CPU since Ryzen integrates a lot of things on the chip itself that the motherboard normally handled on Intel platforms? That's why 1.45-1.5v has been the 'max' that's been recommended. Correct me if I'm wrong please.


----------



## glnn_23

24/7 settings for core and mem 3700c14

PE Level 2
Core Ratio Auto
Vcore Offset -0.10625
SOC 1.1
Vdimm 1.425
LLC 2


----------



## nexxusty

glnn_23 said:


> 24/7 settings for core and mem 3700c14
> 
> PE Level 2
> Core Ratio Auto
> Vcore Offset -0.10625
> SOC 1.1
> Vdimm 1.425
> LLC 2


Wow is that ever a nice chip, mine couldn't even boot at that speed. Let alone be stable.


----------



## glnn_23

nexxusty said:


> Wow is that ever a nice chip, mine couldn't even boot at that speed. Let alone be stable.


4392Mhz is the single core speed. 
All core was something around 4240Mhz CB15 and Prime95 all core 4215Mhz.


----------



## gupsterg

Yvese said:


> Doesn't increasing memory voltage also indirectly pump it to your CPU since Ryzen integrates a lot of things on the chip itself that the motherboard normally handled on Intel platforms? That's why 1.45-1.5v has been the 'max' that's been recommended. Correct me if I'm wrong please.


The OC guides I've read by Elmor on Intel/Ryzen always have:-

"Depends on your DRAM sticks, the limit is considered from CPU IMC side."

Dunno about temperature effect from this, but some CPU IMC's may not like increased VDIMM IMO. JEDEC allows XMP certification of upto 1.5V on DDR4. The other consideration of increased voltages is perhaps things like noise, etc. I do tend to go as low as I can for a setup, may that be VCORE/SOC/VDIMM.



glnn_23 said:


> 24/7 settings for core and mem 3700c14
> 
> PE Level 2
> Core Ratio Auto
> Vcore Offset -0.10625
> SOC 1.1
> Vdimm 1.425
> LLC 2


WOW :specool: .


----------



## DivineLight

3700 CL14 24/7 stable, that would be impressive. Don't forget to endurance test yours. This setting is gamestable, but it doesn't like the tfaw setting at 3600. I'm wondering how you can even boot at 1.425 V. I need 1.45 V to archieve 3600. Up to 3866 is bootable but of course very unstable and only CR2. If I get 3600 working with decent timings I'm already happy. Most people suffer when trying to reach 3200-3400.


----------



## tiagogl

zGunBLADEz said:


> was about time lol
> 
> 32GB Kit (G.Skill F4-3600C17-16GTZR)
> 
> 3466/LL almost 15hrs run for %1300+ coverage on a B350-I Strix mobo
> 
> SOC 1.00v


Hello, can you provide all timmings and other config to achieve this result? I have same memory but I'm not getting stability in 3200 mhz


----------



## Yviena

Does anyone know if there are any ram cooler that can be squeezed in while using a NH-D15 ?


----------



## nick name

glnn_23 said:


> 24/7 settings for core and mem 3700c14
> 
> PE Level 2
> Core Ratio Auto
> Vcore Offset -0.10625
> SOC 1.1
> Vdimm 1.425
> LLC 2


ASUS recently told me the X470 Prime Pro is better for CPU overclocking than the Crosshair VII. It appears that the component sharing ROG Strix is also better and better at RAM overclocking also. If the Crosshair VII didn't have its extra Performance Enhancer Levels I may be inclined to get a Strix board. 

How stable is that memory speed? And which RAM kit do you have again?


----------



## glnn_23

TridentZ 4266 non rgb.

RAM overclocking may just be a little easier due to only 2 ram slots.

Not sure what you mean by 'how stable is that memory speed'

Same settings here as when I ran gsat now running hci memtest.
.


----------



## nick name

glnn_23 said:


> TridentZ 4266 non rgb.
> 
> RAM overclocking may just be a little easier due to only 2 ram slots.
> 
> Not sure what you mean by 'how stable is that memory speed'
> 
> Same settings here as when I ran gsat now running hci memtest.
> .


Ummm how stable is that memory speed? Seems like it explains itself. I'm not sure how else to phrase it. I guess I could ask: what are you using to test your memory stability? Is it one of those things that makes sense in my head but doesn't make sense said out loud? Damn it, now you have you me questioning my own thoughts. 

Ok. My question is: what are you using to test your memory stability?


----------



## glnn_23

nick name said:


> Ummm how stable is that memory speed? Seems like it explains itself. I'm not sure how else to phrase it. I guess I could ask: what are you using to test your memory stability? Is it one of those things that makes sense in my head but doesn't make sense said out loud? Damn it, now you have you me questioning my own thoughts.
> 
> Ok. My question is: what are you using to test your memory stability?


So far just stressapptest and hci memtest. Might run Ram Test as well.

These are the 3 tests I have used in the past on different platforms to test memory and posted both here and more so in the Intel DDR4 24/7 memory stability thread.


----------



## nick name

glnn_23 said:


> So far just stressapptest and hci memtest. Might run Ram Test as well.
> 
> These are the 3 tests I have used in the past on different platforms to test memory and posted both here and more so in the Intel DDR4 24/7 memory stability thread.


Well I am very impressed. 

And looking at what RAM prices are now for that kit I almost wish I would have waited 6 months. I paid nearly the same for my 3600CL15 as Newegg has the 4266 kit now.


----------



## Yviena

I find that gsat sucks for memory stability, it only heats up my ram to 32c, so of course it's going to pass, while I would consider 2500% hci and 30 cycles tm5 stable.


----------



## tiagogl

*Need help to make memory stable*

Hello,

I have the following Gskill Trident Z Bdie F4-3600C17-32GTZR. I'm trying to make my memory stable to run 3200 CL14 with 1.430 volts. Please there is any advice? Here is my timings on the attachment 
My config:
Ryzen 2700x
Asus Strix X370-F


----------



## rdr09

tiagogl said:


> Hello,
> 
> I have the following Gskill Trident Z Bdie F4-3600C17-32GTZR. I'm trying to make my memory stable to run 3200 CL14 with 1.430 volts. Please there is any advice? Here is my timings on the attachment
> My config:
> Ryzen 2700x
> Asus Strix X370-F


Have you tried using the DRAM Calculator?

https://www.overclock.net/showthread.php?p=27721744#post27721744

Also, are you using A2, B2 DIMM Slots?


----------



## tiagogl

rdr09 said:


> tiagogl said:
> 
> 
> 
> Hello,
> 
> I have the following Gskill Trident Z Bdie F4-3600C17-32GTZR. I'm trying to make my memory stable to run 3200 CL14 with 1.430 volts. Please there is any advice? Here is my timings on the attachment
> My config:
> Ryzen 2700x
> Asus Strix X370-F
> 
> 
> 
> Have you tried using the DRAM Calculator?
> 
> https://www.overclock.net/showthread.php?p=27721744#post27721744
> 
> Also, are you using A2, B2 DIMM Slots?
Click to expand...

Yes. These timings I get from calculator and I'm using a2 and b2.


----------



## redtopracer

OK so finally upgraded to some HQ b die and got me a 2x8gb 3200 15 gskill kit. Does pretty decent, not great. Trying to dial out the last little bit from it.


Setup is a 1600x on a gigabyte x370 gaming k7 bios f23 by ket. So far I have been able to run the stilts fast timings gdm on for 3200 and 3333. Also managed to get the 3466 timing from the stilt stable at 3400. Settled on safe timings for the calculator at 3400. Noticed some things about this setup that made me have some questions. 

The sticks like procodt 48 for stability reasons but boot like crap on it. 53 and 60 both boot every time on it but throw errors every few pass's.They also require 1.44v dram and 1.0625v soc to run stable and boot somewhat successfully, more or less voltage does not alleviate boot or errors issues. current best settings still f9 on mem training once or twice but rarely fail. Which is better than before where it might take a CMOS clear to get it running. Voltages are set as follows. 

4.1ghz pstate0

Vcore 1.38v llc high

Soc 1.0623v uncore llc high

Vddp .860v

Dram 1.44v

Dram termination .731v

Everything else is left to stock. 


Testing so far puts current setting's stable on karhus ramtest to 3000%. Heat related errors occur afterwards but with an additional fan pointed on the sticks its tested out to 5000% before I had to stop. 
RTT has been tested with NOM set rzq/7 and disabled. WR has been left disabled and I've tried park set to everything from 3-6. So far the only thing that's seemed to help is a small dram and soc voltage bump. Higher voltages up to 1.55v and 1.175v have not alleviated any booting issues. 


3466 tested stable on the stilts timings set to procodt 48. But failed to boot at all with separate attempts to retest. RTT and voltage settings listed above did not help in any further attempts to boot. Testing on procodt 53&60 booted fine but threw errors fast the higher the procodt got. 


I'm at my wits end with these sticks. The IMC on this chip was able to previously drive 3333 16,16,17,30 2t on hynix mfr IC's but any attempts to tighten at 3400 or run higher MHz result in errors. Is this the limit for these sticks or am I missing something?I've ran stock clocks with higher vcore to see if it was the CPU oc and it was not.


----------



## ilmazzo

I read somewhere that amd released 1.0.0.6 agesa and some asus mobos have already a bios for it, I think I'll give it a chance whenever asrock will release a bios with it

The question is.... in case of worst results than my actual one, is there any issue to downgrade bioses on asrocks motherboard or in general? cheers


----------



## jclafi

My X470 still on agesa 1.0.0.4C.. But run my LPX @ rated speed's w/ tunned timmings easy. 

But need's 1.42v to be stable and nothing less.


----------



## maje90

*700% yay!*

Hi all.
I've tried to use Ryzen calculator... I've actually just put the numbers >_<

It worked! Up to 700% HCI!

I don't really understand what I'm doing, so I have some questions.
1- in the BIOS I've manually set 1.4V for CPU and 1.385V for RAM, but it's displayed as 1.417V for both... Are those real voltages or what? Is this ok for common daily usage?
2- I let the pc do the memtests for like... 6 hours? ... but the task manager was saying more than a day of "activity time"... why is that?
3- Now, as the previous OC set-up i did, my pc boot up twice at every cold boot. What does it mean?
(like: press button, it turn on, some fans start spinning for 1-2 secs, turn off, it turn on again and boot normally...)
4- The 16 istances of memtest done very different percentages, 6 of them did reach 700%, the other 10 1100%. Is that normal?

My PC:
MOBO: Asus Crosshair VI Hero - CPU: Ryzen 1800X - Cooler: Noctua NH-D15 - RAM: F4-3600C15D-16GTZ - PSU: Seasonic Focus+ SSR-650FX
(GPU: Sapphire RX 580 8GB NITRO+ - Drives: Samsung SSD 850 EVO sata + 3x WD HDD sata - Case: Sharkoon DG7000-G)


----------



## Snurt

Hi


First post here.


This is a G.Skill FlareX kit running 3200mhz with 1.39v VDIMM.











But what is up with that tRCDRD? If i enter anything lower than 15 i get ram error in any of the test programs.
Also, what is the consensus on the Karhu RAM Test?


----------



## herericc

maje90 said:


> Hi all.
> I've tried to use Ryzen calculator... I've actually just put the numbers >_<
> 
> It worked! Up to 700% HCI!
> 
> I don't really understand what I'm doing, so I have some questions.
> 1- in the BIOS I've manually set 1.4V for CPU and 1.385V for RAM, but it's displayed as 1.417V for both... Are those real voltages or what? Is this ok for common daily usage?
> 2- I let the pc do the memtests for like... 6 hours? ... but the task manager was saying more than a day of "activity time"... why is that?
> 3- Now, as the previous OC set-up i did, my pc boot up twice at every cold boot. What does it mean?
> (like: press button, it turn on, some fans start spinning for 1-2 secs, turn off, it turn on again and boot normally...)
> 4- The 16 istances of memtest done very different percentages, 6 of them did reach 700%, the other 10 1100%. Is that normal?
> 
> My PC:
> MOBO: Asus Crosshair VI Hero - CPU: Ryzen 1800X - Cooler: Noctua NH-D15 - RAM: F4-3600C15D-16GTZ - PSU: Seasonic Focus+ SSR-650FX
> (GPU: Sapphire RX 580 8GB NITRO+ - Drives: Samsung SSD 850 EVO sata + 3x WD HDD sata - Case: Sharkoon DG7000-G)


Hey dude, the Crosshair VI hero has a GARBAGE voltage sensor that doesn't belong on a "top of the line" motherboard so all it's voltage readings are ridiculously inaccurate. Many people have tested using multimeters/oscilliscopes and have proven that the actual voltage being supplied to the cpu/ram is basically what you set it to in the BIOS.
RE: point 3, make sure you set your "DRAM Startup Voltage" i can't remember which sub-menu it's hidden in but it's in there somewhere. Run a dram startup voltage of 1.4V and you should see the double boot issue less.


----------



## Singularity48

Hello everyone, this is my first post on this site. I recently built an AM4 rig and have been messing with memory since the way Ryzen interacts with RAM is interesting.

Relevant specs: Crosshair VII Hero (0804, AGESA 1.0.0.2), 2700x (PE2, PBO x10, -100mV offset), G.SKILL TridentZ RGB 2x16GB (F4-3200C14D-32GTZR)

I initially built the rig with a kit of single rank 2x8 Ripjaws V bdie, and messed with that a bit but never got much better than like DRAM Calc 3200 fast. I tried 3333 and 3466 with safe/fast presets but they weren't very stable, threw errors like crazy at 3466c14 and eventually did at 3333c14 around 400%.

So there was a sale on the 2x16 TridentZ RGB B-die right before black friday, and I picked it up. It ran XMP just fine and I had it like that a few days, and started experimenting. I went at it with two options to start, (dual rank, gaming) DRAM calc 3466 extreme preset, and 3200 extreme preset. Based on the advice from the AMD dude who gave basically a seminar on memory OC for ryzen (Robert?), I set DRAM to 1.5v, SOC to 1.1v (only values different from DRAM Calc presets). 3466 wouldn't train. I didn't attempt to make it work, I just reset and went to the 3200 settings instead to see if that would work immediately. It didn't, so I went with the first step of the handy overclock troubleshooting image that comes with DRAM Calculator, I bumped procODT up to 60ohm from 53.3.

Not only did it post, it runs perfectly as far as I can tell. 900% memtest stable across 10 simultaneous tests splitting ~29GB of memory, I only stopped the test at that because I was done with my morning coffee after running it overnight and needed to use my computer lol. Haven't had a single crash or even a hint of something going wrong memory-wise after several days of my usual use.

My question is, did I hit the lottery? And if it was that easy to stabilize at these timings, I'm wondering where to go from here as far as pushing this kit.

I'll run a 16 instance memtest when I go to bed and post better proof (if this is even special for bdie, I honestly don't know) with all the relevant info in one screenshot, but for now here's these.


----------



## 1usmus

tiagogl said:


> Hello,
> 
> I have the following Gskill Trident Z Bdie F4-3600C17-32GTZR. I'm trying to make my memory stable to run 3200 CL14 with 1.430 volts. Please there is any advice? Here is my timings on the attachment
> My config:
> Ryzen 2700x
> Asus Strix X370-F


Why so much voltage for RAM? 1.36 should be enough

please explain what is happening



redtopracer said:


> OK so finally upgraded to some HQ b die and got me a 2x8gb 3200 15 gskill kit. Does pretty decent, not great. Trying to dial out the last little bit from it.
> 
> 
> Setup is a 1600x on a gigabyte x370 gaming k7 bios f23 by ket. So far I have been able to run the stilts fast timings gdm on for 3200 and 3333. Also managed to get the 3466 timing from the stilt stable at 3400. Settled on safe timings for the calculator at 3400. Noticed some things about this setup that made me have some questions.
> 
> The sticks like procodt 48 for stability reasons but boot like crap on it. 53 and 60 both boot every time on it but throw errors every few pass's.They also require 1.44v dram and 1.0625v soc to run stable and boot somewhat successfully, more or less voltage does not alleviate boot or errors issues. current best settings still f9 on mem training once or twice but rarely fail. Which is better than before where it might take a CMOS clear to get it running. Voltages are set as follows.
> 
> 4.1ghz pstate0
> 
> Vcore 1.38v llc high
> 
> Soc 1.0623v uncore llc high
> 
> Vddp .860v
> 
> Dram 1.44v
> 
> Dram termination .731v
> 
> Everything else is left to stock.
> 
> 
> Testing so far puts current setting's stable on karhus ramtest to 3000%. Heat related errors occur afterwards but with an additional fan pointed on the sticks its tested out to 5000% before I had to stop.
> RTT has been tested with NOM set rzq/7 and disabled. WR has
> 
> been left disabled and I've tried park set to everything from 3-6. So far the only thing that's seemed to help is a small dram and soc voltage bump. Higher voltages up to 1.55v and 1.175v have not alleviated any booting issues.
> 
> 
> 3466 tested stable on the stilts timings set to procodt 48. But failed to boot at all with separate attempts to retest. RTT and voltage settings listed above did not help in any further attempts to boot. Testing on procodt 53&60 booted fine but threw errors fast the higher the procodt got.
> 
> 
> I'm at my wits end with these sticks. The IMC on this chip was able to previously drive 3333 16,16,17,30 2t on hynix mfr IC's but any attempts to tighten at 3400 or run higher MHz result in errors. Is this the limit for these sticks or am I missing something?I've ran stock clocks with higher vcore to see if it was the CPU oc and it was not.


rather, it is the limit for your memory controller, only half of the first generation controllers can operate with a frequency of 3466+ RAM

At the end of this week, the F24 should appear, maybe it will improve the situation + I will update the presets for all the Samsung b-die



ilmazzo said:


> I read somewhere that amd released 1.0.0.6 agesa and some asus mobos have already a bios for it, I think I'll give it a chance whenever asrock will release a bios with it
> 
> The question is.... in case of worst results than my actual one, is there any issue to downgrade bioses on asrocks motherboard or in general? cheers


when it comes out we will know all the advantages and disadvantages 



maje90 said:


> Hi all.
> I've tried to use Ryzen calculator... I've actually just put the numbers >_<
> 
> It worked! Up to 700% HCI!
> 
> I don't really understand what I'm doing, so I have some questions.
> 1- in the BIOS I've manually set 1.4V for CPU and 1.385V for RAM, but it's displayed as 1.417V for both... Are those real voltages or what? Is this ok for common daily usage?
> 2- I let the pc do the memtests for like... 6 hours? ... but the task manager was saying more than a day of "activity time"... why is that?
> 3- Now, as the previous OC set-up i did, my pc boot up twice at every cold boot. What does it mean?
> (like: press button, it turn on, some fans start spinning for 1-2 secs, turn off, it turn on again and boot normally...)
> 4- The 16 istances of memtest done very different percentages, 6 of them did reach 700%, the other 10 1100%. Is that normal?
> 
> My PC:
> MOBO: Asus Crosshair VI Hero - CPU: Ryzen 1800X - Cooler: Noctua NH-D15 - RAM: F4-3600C15D-16GTZ - PSU: Seasonic Focus+ SSR-650FX
> (GPU: Sapphire RX 580 8GB NITRO+ - Drives: Samsung SSD 850 EVO sata + 3x WD HDD sata - Case: Sharkoon DG7000-G)


1) yes, this is normal + sensors can be deceiving, but rest assured, everything is good and accurate
3) this phenomenon is called memory training, I think that this is normal. If you want to get rid of it you will have to find other settings for procODT and RTT
4) it is not necessary that in each window there will be the same number of percent. You have prioritized background services in your operating system.


----------



## 1usmus

Singularity48 said:


> Hello everyone, this is my first post on this site. I recently built an AM4 rig and have been messing with memory since the way Ryzen interacts with RAM is interesting.
> 
> Relevant specs: Crosshair VII Hero (0804, AGESA 1.0.0.2), 2700x (PE2, PBO x10, -100mV offset), G.SKILL TridentZ RGB 2x16GB (F4-3200C14D-32GTZR)
> 
> I initially built the rig with a kit of single rank 2x8 Ripjaws V bdie, and messed with that a bit but never got much better than like DRAM Calc 3200 fast. I tried 3333 and 3466 with safe/fast presets but they weren't very stable, threw errors like crazy at 3466c14 and eventually did at 3333c14 around 400%.
> 
> So there was a sale on the 2x16 TridentZ RGB B-die right before black friday, and I picked it up. It ran XMP just fine and I had it like that a few days, and started experimenting. I went at it with two options to start, (dual rank, gaming) DRAM calc 3466 extreme preset, and 3200 extreme preset. Based on the advice from the AMD dude who gave basically a seminar on memory OC for ryzen (Robert?), I set DRAM to 1.5v, SOC to 1.1v (only values different from DRAM Calc presets). 3466 wouldn't train. I didn't attempt to make it work, I just reset and went to the 3200 settings instead to see if that would work immediately. It didn't, so I went with the first step of the handy overclock troubleshooting image that comes with DRAM Calculator, I bumped procODT up to 60ohm from 53.3.
> 
> Not only did it post, it runs perfectly as far as I can tell. 900% memtest stable across 10 simultaneous tests splitting ~29GB of memory, I only stopped the test at that because I was done with my morning coffee after running it overnight and needed to use my computer lol. Haven't had a single crash or even a hint of something going wrong memory-wise after several days of my usual use.
> 
> My question is, did I hit the lottery? And if it was that easy to stabilize at these timings, I'm wondering where to go from here as far as pushing this kit.
> 
> I'll run a 16 instance memtest when I go to bed and post better proof (if this is even special for bdie, I honestly don't know) with all the relevant info in one screenshot, but for now here's these.


for dual rank, the optimal frequency is 3200-3333, try using the calculator again
1.5 for DRAM is a lot, I do not advise using it without additional cooling of the modules

+

for your motherboard there was a new bios


----------



## ilmazzo

1usmus said:


> when it comes out we will know all the advantages and disadvantages



yup, sure  thanks for the moment!


----------



## Singularity48

Oh snap the man himself. Thank you for the DRAM Calculator, it's so damn handy!



1usmus said:


> for dual rank, the optimal frequency is 3200-3333, try using the calculator again
> 1.5 for DRAM is a lot, I do not advise using it without additional cooling of the modules


So the highest I should aim for is like 3200-3333 @ ~c12-c14 TT? And get DRAM/SoC voltage as low as possible while maintaining stability?
Also, my DIMM temps in HWinfo64 at 3200 12-13-13-22-36 1.5v have never gone higher than 50c in any stress test, is that still too high?



1usmus said:


> for your motherboard there was a new bios


Yeah I was waiting for 1.0.0.6 to release, but now I'm waiting to see dual rank performance compared to 1.0.0.2.


----------



## stinger2k

Singularity48 said:


> Oh snap the man himself. Thank you for the DRAM Calculator, it's so damn handy!
> 
> 
> So the highest I should aim for is like 3200-3333 @ ~c12-c14 TT? And get DRAM/SoC voltage as low as possible while maintaining stability?
> Also, my DIMM temps in HWinfo64 at 3200 12-13-13-22-36 1.5v have never gone higher than 50c in any stress test, is that still too high?
> 
> 
> Yeah I was waiting for 1.0.0.6 to release, but now I'm waiting to see dual rank performance compared to 1.0.0.2.




Try to set RTTNom 7, RTTWr 3, RTTPark disabled and Procodt 43,6 or 48 Ohm, and booting up 3333 with your Ram (at 1,375V). I do have the same kit 2x and i´m semi stable (Memtest stable, Karhu Ram Test sometimes stable, sometimes errors.


----------



## stinger2k

tiagogl said:


> Hello,
> 
> I have the following Gskill Trident Z Bdie F4-3600C17-32GTZR. I'm trying to make my memory stable to run 3200 CL14 with 1.430 volts. Please there is any advice? Here is my timings on the attachment
> My config:
> Ryzen 2700x
> Asus Strix X370-F


RTT 7/3/disabled Procodt 43,6 or 48 Ohm, 1,375V Vdimm should do the thing (CAD Bus 30/40/24/20 at my setup [email protected] cl14 now rockstable..)


----------



## By-Tor

Just coming back to AMD after a 3 years hiatus to the other team.. 

I have my RAM (see sig) running @ 3466, 14-14-14-34 on 1.38v. It seems to be running great without issues, but is 1.38v a bit high for my kit?

I have this kit: G.Skill F4-3200C14D-16GVR


----------



## Jspinks020

Despite that lower kit is like a few more bucks. You should still be fine at cl16 3200...should absolutely be stable..was widely tested on both and it's been rock Probably just a handful of incompatibility. Id have to buy a new kit anyways...I can't get the **** to go to 3333-3400mhz even anymore.


----------



## stinger2k

By-Tor said:


> Just coming back to AMD after a 3 years hiatus to the other team..
> 
> I have my RAM (see sig) running @ 3466, 14-14-14-34 on 1.38v. It seems to be running great without issues, but is 1.38v a bit high for my kit?
> 
> I have this kit: G.Skill F4-3200C14D-16GVR



Almost 1,45V for 24/7 shouldn´t be a problem...


----------



## By-Tor

stinger2k said:


> Almost 1,45V for 24/7 shouldn´t be a problem...


Thank you


----------



## Synoxia

Seems like my ram don't like frequency that much. Currently 3413 c14-13. Would this still be faster than 3000/3200 c12 or worth trying extremely tight timings?
EDIT: First test gave me out +5 points, the second had the same score on cinebench....
P.S i have been running 1.5v 24/7 for months... ram never exceeded 40c really, JDEC specs max frequency 85 to 120, why 1.5v wouldn't be safe?


----------



## alefim

Hi Guys,

With the BIOS update of my mobo MSI X470 M7 AC, with Agesa 1.0.0.6, the Ryzen Timing Checker failed to show some information.

I have a GSKILL 3600CL16 and i am using the 1.45v 3600CL14 and SOC 1.0375 LLC 3. Is the voltage okay?

Does anyone have higher frequencies with stability and safe voltage?


----------



## Synoxia

Bumping the frequency up to even just 3276 c12-13 starts to give me bsods the ISTANT i start GSAT for testing. Tried bumping ProcODT to 48 but didn't help at all, voltage is a no go because it's already at 1.5v and that's my psychological barrier atm for 24/7 use. 
Soc is at 1.11, 1.8v pll, 1.05v sb voltage locked. 
I run a -0.5v offset and high performance power plan because Balanced cause microstutters in games with a 2700x.
What else i can do to improve https://www.gskill.com/en/product/f4-3600c17d-16gtz this kit? 








Looking at this chart seems like i lost nothing but gained as my ram didn't hit 3466c14 and 3200 cl12 should perform similiar... i'd to like to reach 3333 frequency on c12 but maybe that's impossible i guess? 
For now i managed to squeeze the full 12-12-12 on 3200 clock... i also noticed DPC latency got lower by like 30-40 microseconds from 3413 c14-13 to 3200c12 (Don't care of 700 spikes, those are caused from hwinfo running in background ACPI.sys)

Ryzen 2700x, Asus CH7 MotherBoard 1103 bios (agesa 1.0.0.6)


----------



## 12vyy

*BDie not running 3200CL14*

Rig:
CPU: Ryzen 2700x at stock settings
MB: Crosshair VII WIFI
RAM: F4-3200C14D-16GTZRX (BDie Single Rank checked via TB and yes they are in the right slots A2 and B2)

The DOCP profile is unstable getting BSODs and ramtest throws errors like crazy so I tried to use the DRAM Calc and while the subtimings did work as soon as i touched the main timings (even CL18) it was getting unstable again. I tested DRAM Voltage from 1.35 - 1.45 and SOC Voltage from 1-1.15 but havent touched the Advanced tab besides the DRAM boot Voltage because im new to RAM OCing and just want to get my advertised speed since I paid that premium price for the BDies.

For the Termination Block i found that procODT 53 or 60 worksd best.

If I need to provide more indepth infos please tell me and I will do. Help would really be appreciated since I struggle 3 days straight.


----------



## Synoxia

12vyy said:


> Rig:
> CPU: Ryzen 2700x at stock settings
> MB: Crosshair VII WIFI
> RAM: F4-3200C14D-16GTZRX (BDie Single Rank checked via TB and yes they are in the right slots A2 and B2)
> 
> The DOCP profile is unstable getting BSODs and ramtest throws errors like crazy so I tried to use the DRAM Calc and while the subtimings did work as soon as i touched the main timings (even CL18) it was getting unstable again. I tested DRAM Voltage from 1.35 - 1.45 and SOC Voltage from 1-1.15 but havent touched the Advanced tab besides the DRAM boot Voltage because im new to RAM OCing and just want to get my advertised speed since I paid that premium price for the BDies.
> 
> For the Termination Block i found that procODT 53 or 60 worksd best.
> 
> If I need to provide more indepth infos please tell me and I will do. Help would really be appreciated since I struggle 3 days straight.


What are you trying to do? The ram calc safe and fast preset should be faster than your DOCP... I suggest you trying The Stilt 3200 fast preset in your crosshair bios. Plug and play best timings, that ram kit could get you 3200 c12 like me or even better... you and me have same cpu and mobo, so unless your cpu can't keep up with your ram kit (which is BETTER than my kit) or you do user error i think you could basically load my timings, speed an voltage no problems... and yes procodt 53 seems the best on ch7


----------



## 1usmus

stinger2k said:


> RTT 7/3/disabled Procodt 43,6 or 48 Ohm, 1,375V Vdimm should do the thing (CAD Bus 30/40/24/20 at my setup [email protected] cl14 now rockstable..)


I find it difficult to call this program a test, very often it is blind to errors. 
Take it a rule to check the system a couple of programs. For example Karhu + Linx, TM5 + Prime



Synoxia said:


> Seems like my ram don't like frequency that much. Currently 3413 c14-13. Would this still be faster than 3000/3200 c12 or worth trying extremely tight timings?
> EDIT: First test gave me out +5 points, the second had the same score on cinebench....
> P.S i have been running 1.5v 24/7 for months... ram never exceeded 40c really, JDEC specs max frequency 85 to 120, why 1.5v wouldn't be safe?


A memory with a more advanced technical process is more sensitive to voltage. For example, Hynix CJR (18nm) or Micron H-die (16nm) have a chance to die at a voltage above 1.47. Memory on Samsung b-die (20 nm)is resistant to 1.5 volts
Stabilizing 3200CL12 is much more complicated than 3733Cl14, this is from my experience 



alefim said:


> Hi Guys,
> 
> With the BIOS update of my mobo MSI X470 M7 AC, with Agesa 1.0.0.6, the Ryzen Timing Checker failed to show some information.
> 
> I have a GSKILL 3600CL16 and i am using the 1.45v 3600CL14 and SOC 1.0375 LLC 3. Is the voltage okay?
> 
> Does anyone have higher frequencies with stability and safe voltage?


i have 3733CL14 on 1.51

p.s. M7 too 



Spoiler


----------



## 1usmus

*Hynix CJR single rank presets collection (beta 1) *

3200-3867

https://www.overclock.net/forum/27754172-post3629.html


----------



## dgoc18

Hi guys,

I just got new AMD build spec below.

AMD Ryzen 3 2200G.

X470 GAMING PRO CARBON.

G-Skill Sniper X 3600 F4-3600C19-8GSXKB CAS 19, I snagged it for $ 128 shipped from Egg.

EVGA SuperNova 850 GOLD PSU.

I select “Memory try it” to 3466 16-18-18-36-82 in the bios 2 sec bam!

Not bad after all but I am still learning tweak memory timings, 3600 was able to boot to Windows no problem but run some test apps that cause BSOD's lot of time.

I know cas 19 is fugly but I can't afford cas 14 and too expensive, That is all to it.

Pic below.


----------



## Synoxia

1usmus said:


> I find it difficult to call this program a test, very often it is blind to errors.
> Take it a rule to check the system a couple of programs. For example Karhu + Linx, TM5 + Prime
> 
> 
> 
> A memory with a more advanced technical process is more sensitive to voltage. For example, Hynix CJR (18nm) or Micron H-die (16nm) have a chance to die at a voltage above 1.47. Memory on Samsung b-die (20 nm)is resistant to 1.5 volts
> Stabilizing 3200CL12 is much more complicated than 3733Cl14, this is from my experience
> 
> 
> 
> i have 3733CL14 on 1.51
> 
> p.s. M7 too
> 
> 
> 
> Spoiler


Hey @1smus. 
Do you know why on the earth i can't use CAS 13 on asus CH7 even if your calc tells me to? example: 3200 c12-13-13-13? OK, stable gsat. 3200 c14-13-13-13? OK, stable gsat. 3200 c13-13-13-13 doesn't even post, not OK.

I'm trying to get the best achievable single core performance for games on my 2700x, i am already 100% stable on 3200 c12 (screen for subtimings) do you think it's still better han 3481 c14-13 if 1st cas isn't c13 (second screen)? Should i tighten the subtimings or try for higher frequency? 3733 c14 should be as fast as 3200c12 (7,5 NS) but idk i'm kinda confused at this point

https://www.gskill.com/en/product/f4-3600c17d-16gtz

These are my ram, i run them at 1.49 24/7. I've seen you running them 1.51... what's the deal with rams? DDR3 could run 1.60-1.70 without problems 24/7, i never seen ddr4 above 40c, do you think pushing 1.55-1.60 is ok for 24/7?


----------



## kazablanka

@1usmus ,updating to 1006 agesa on prime x470 pro ,i found that my 3600Μhz ram overclock was not stable ,with 1002 agesa it was rock stable.

I set rtt and cad bus values to auto and it became stable, unfortunately rtc can't read the values correct any more. Do you think amd has change this values for default ?


----------



## Synoxia

Afaik 3686 won't even post. I don't even mind trying 3753. Ill try to get this stable and maybe further reduce timings


----------



## alefim

1usmus said:


> i have 3733CL14 on 1.51
> 
> p.s. M7 too
> 
> 
> 
> Spoiler



Can you pass on the other information? SOC LLC, CLDO VDDP, PLL Voltage ...

1.51v not much? What memory model do you use? Thx


----------



## nick name

kazablanka said:


> @1usmus ,updating to 1006 agesa on prime x470 pro ,i found that my 3600Μhz ram overclock was not stable ,with 1002 agesa it was rock stable.
> 
> I set rtt and cad bus values to auto and it became stable, unfortunately rtc can't read the values correct any more. Do you think amd has change this values for default ?


The Stilt released a version that works with the latest AGESA, but he said that's the last one he'll do.


----------



## Reous

@*kazablanka* You have to update RTC to version 1.05 if you need Agesa 1006 

Edit: Just saw nike name was faster


----------



## kazablanka

@Reous @nick name ,thanks guys ,i thouthg 1.04 was the last one that would released. I'll try 1.05.


----------



## kazablanka

with new agesa i can tight a little more some timings


----------



## 1usmus

kazablanka said:


> with new agesa i can tight a little more some timings


very good :thumb:
but you have a chance to improve performance if you use tRFC 160ns , 180ns or 192ns


----------



## Synoxia

I tried to match @1usmus but obviously impossible mostly because i lack knowledge but maybe also bin? i dont know but this is what i settled for now...

https://www.gskill.com/en/product/f4-3600c17d-16gtz my ram


----------



## 1usmus

Synoxia said:


> I tried to match @1usmus but obviously impossible mostly because i lack knowledge but maybe also bin? i dont know but this is what i settled for now...
> 
> https://www.gskill.com/en/product/f4-3600c17d-16gtz my ram



try not to do too low tWTRL and tRRDL
SCL 2 not relevant, it does not improve performance and does not improve throughput. At this frequency, 3 is the optimal value 
too "compressed" timings can give the opposite result


----------



## Synoxia

1usmus said:


> try not to do too low tWTRL and tRRDL
> SCL 2 not relevant, it does not improve performance and does not improve throughput. At this frequency, 3 is the optimal value
> too "compressed" timings can give the opposite result


So you suggest raising SCLs, TWTRL, TRRDL to get higher frequency? I also thought of trying 14-13-13-13 but i dont think they would be stable.

@CJMitsuki it's running SCLs 2 with similiar speed/cas tho

Can you also explain what do the tweaks in the advanced page do? Anything relevant for gaming purposes besides bankgroupswap?


----------



## Atomfix

Can I get this any better? Passed over an over on Prime95 with memory usage 90% saturated. I can get it to boot using Stilts timings at 3200MHz but it was unstable in stress tests.

G.Skill Trident Z 3000MHz 8GB x2 kit. Hynix M-Die.
Ryzen 1700 @ Stock clock.
Gigabyte X370 Gaming K5

Soc Voltage @ 1.1V


----------



## Synoxia

@1usmus i'm now testing this with GSAT, 3600c14-15-15-15 doesn't post... your calculator says that i have a 93% chip quality and that it could go 3674c14.
Do you think i can do any better?

P.S I noticed that lowering trcdrwr and trcdrd by 1 point makes mouse input feel snappier... placebo? Can someone also confirm this?


----------



## Maxikas

Hi

I need some advice about memory kit for new Threadripper 1920X build. My mainboard is Asrock X399 Taichi.

*1)* G.SKILL 32GB 3200MHz Flare X Black CL14 (4x8GB) F4-3200C14Q-32GFX

*2)* *2 x* G.SKILL 16GB 3200MHz Flare X Black Ryzen CL14 (2x8GB) F4-3200C14D-16GFX
Is there any reasonable reason to go with 2 x 2 x 8GB, except that in the future, it would be faster to resale them as separate kits ?
Also i could split this and buy one kit now and second in next month. 

*3)* HyperX 32GB 3600MHz Predator RGB CL17 (4x8GB) HX436C17PB3AK4/32 
Asrock QVL claims that these are Samsung B-Die and will run at 3466 MHz. Anybody got these modules and can confirm it or not ? 
Little bit risky but this is the cheapest mem kit - i can get it for ~ 428 $
What do You think ?

I'm almost decided for 1) option. Not the cheapest but should be stable plug & play 3200 @ CL14.


----------



## Jspinks020

The Smoke adds Performance lol...but a fresh rad and better pics now..old camera was a blurry thing. Definitely botched mixed metal Loop. Need to put something in it man.


----------



## Keith Myers

Maxikas said:


> Hi
> 
> I need some advice about memory kit for new Threadripper 1920X build. My mainboard is Asrock X399 Taichi.
> 
> *1)* G.SKILL 32GB 3200MHz Flare X Black CL14 (4x8GB) F4-3200C14Q-32GFX
> 
> *2)* *2 x* G.SKILL 16GB 3200MHz Flare X Black Ryzen CL14 (2x8GB) F4-3200C14D-16GFX
> Is there any reasonable reason to go with 2 x 2 x 8GB, except that in the future, it would be faster to resale them as separate kits ?
> Also i could split this and buy one kit now and second in next month.
> 
> *3)* HyperX 32GB 3600MHz Predator RGB CL17 (4x8GB) HX436C17PB3AK4/32
> Asrock QVL claims that these are Samsung B-Die and will run at 3466 MHz. Anybody got these modules and can confirm it or not ?
> Little bit risky but this is the cheapest mem kit - i can get it for ~ 428 $
> What do You think ?
> 
> I'm almost decided for 1) option. Not the cheapest but should be stable plug & play 3200 @ CL14.


I went with G. Skill Trident Z F4-3200C14Q-32GTZKW for my 2920X on an Asrock X399 Fat Pro Gaming motherboard. Currently running them on the Calculator 3400 Fast timings. 100% stable on full BOINC load over a week non-stop now. Tried to push on to 3466 but did not spend enough time trying find stability and just fell back to 3400 which I am very happy with. My Ryzen 2700X hosts only run 3466 Fast either so not any noticeable slowdown for 66Mhz less clock.:thumb:


----------



## Jspinks020

Go to a Microcenter and try to find that Evga kit. It's a stable one. Probably right just some Gskill kit. Get the Ripjaws kit or something, I seen that.


----------



## AlphaC

Jspinks020 said:


> Go to a Microcenter and try to find that Evga kit. It's a stable one. Probably right just some Gskill kit. Get the Ripjaws kit or something, I seen that.


If you mean the 3200MHz CL16 EVGA kit, I would avoid it. I have it and it is Hynix MFR.


----------



## Maxikas

Ordered G.SKILL FlareX 4x8GB F4-3200C14Q-32GFX. With a bit of luck, i'll receive them today.


----------



## MrPhilo

CPU 4.25Ghz at 1.425V (LLC5)
SoC 1.15v (LLC5)
RAM at 3600CL14 at 1.5v (Vdrops to 1.482v as per Hwinfo)

So far so good


----------



## alefim

SOC 1.0375v LLC3
MEM 1.46v
CLDO_VDDP 0.915v


----------



## GameBoy

Is it possible that a GPU change can make your RAM or CPU overclock unstable? Just swapped out my 7970 to a Vega 56 and now I started blue screening in games and in OCCT. No crashes at stock setting


----------



## MrWhiteRX7

GameBoy said:


> Is it possible that a GPU change can make your RAM or CPU overclock unstable? Just swapped out my 7970 to a Vega 56 and now I started blue screening in games and in OCCT. No crashes at stock setting


You reinstalled your chipset driver after uninstalling/ installing gpu driver?


----------



## kazablanka

1usmus said:


> very good :thumb:
> but you have a chance to improve performance if you use tRFC 160ns , 180ns or 192ns


i tried trfc 160ns but aida score was worst , i tested trfc 252 (140ns) and it is stable. How does trfc affect on performance and which is the lower possible trfc at 3600mhz?


----------



## GameBoy

MrWhiteRX7 said:


> You reinstalled your chipset driver after uninstalling/ installing gpu driver?


Already tried that, doesn't make a difference. Lowering down to 3333Mhz at the same timings seem to have made it better, not experiencing any more crashes. But how can I just lose the ability to be at 3466mhz with a GPU change?

Don't think it's the PSU because I can get it to crash in CPU/mem stress tests when the GPU is idle


----------



## Jspinks020

GameBoy said:


> Already tried that, doesn't make a difference. Lowering down to 3333Mhz at the same timings seem to have made it better, not experiencing any more crashes. But how can I just lose the ability to be at 3466mhz with a GPU change?


It's just unstable...try more voltage or something...running into the same thing, it might require more than you think...it usually was that way always from what I remember. Kit's are affordable again..go ahead and try to dog it out. Ripjaws kit was only 113$ and stuff, Probably pick up like the LPX for something similar.

There's not a huge difference but I guess if you want to. already at really nice Reads at least.


----------



## man from atlantis

Hi what should i aim for overclocking the memory? Higher throughput or lower latency? I have a flare x kit and can run @ the settings below 24/7. 

Daily G.Skill Flare X @3466MHz 14-13-13-13-22T 1.41V vDIMM, 1.0V vSoC


----------



## man from atlantis

MrPhilo said:


> CPU 4.25Ghz at 1.425V (LLC5)
> SoC 1.15v (LLC5)
> RAM at 3600CL14 at 1.5v (Vdrops to 1.482v as per Hwinfo)
> 
> So far so good


Using your timings i finally can run @3600MHz with no problem. Mem test havent given any errors for 15mins. I reduced the tRCDRD to 14 just to ease my ocd.

vDIMM @1.44v, vSoC @1.125v










[email protected], 3200MHz CL14 XMP, [email protected]/9000, Shadow of the Tomb Raider *145FPS*
https://abload.de/img/4300x3200xmpx2075x90011dsx.png

[email protected], 3466MHz CL14 tight timings, [email protected]/9000, Shadow of the Tomb Raider *172FPS*
https://abload.de/img/4300x3466x2075x9000u8cf1.png

[email protected], 3600MHz CL14 looser timings, [email protected]/9000, Shadow of the Tomb Raider *175FPS*
https://abload.de/img/4300x3600x2075x9000fbi05.png


----------



## Jackalito

Hey guys, I could use your help to get my RAM (G.Skill F4-3200C14-32GTZ - Sammy B-Die) stable again at 3200MHz. It was stable with my previous combo ASUS CH6 + 1700X, but I can't use the same settings to make it stable at 3200 with the new one, ASUS CH7 + 2700X:
So far I've only managed to get my memory stable at 3066MHz using the Ryzen DRAM Calculator as basis.

Here are the settings:












Ai Overclock Tuner: Default
Performance Enhancer: Auto
CPU Core Ratio: Auto
Performance Bias: None
Memory Frequency: 3066MHz
Core Performance Boost: Disabled
SMT Mode: Auto
TPU: Keep current settings

ProcODT: 60 ohm
Cmdt2T: 2T
Gear Down Mode: Disabled
Power Down Mode: Disabled

RttNom: RZQ/7
RttWr: RZQ/3
RttPark: RZQ/1

MemAddrCmdSetup: Auto
MemCsOdtSetup: Auto
MemCkeSetup: Auto

MemCadBusClkDrvStren: Auto
MemCadBusAddrCmdDrvStren: Auto
MemCadBusCsOdtDrvStren: Auto
MemCadBusCkeDrvStren: Auto

VTTDDR Voltage: 0.67500
VPP_MEM Voltage: 2.50000
VDDP Voltage: 0.85500
CLDO VDDP voltage: 700

CPU Core Voltage: Auto
CPU SOC Voltage: 0.98750
DRAM Voltage: 1.350
1.8V PLL Voltage: 1.80000
1.05V SB Voltage: Auto
NO LLC


Fast Boot: Disabled
CSM: Disabled



I'm not overclocking my CPU yet, as I'm waiting to replace the out-of-the-box cooler with a Noctua NH-D15 SE-AM4.


I would appreciate it if anyone, with the same or a similar Dual Rank memory kit, could give me some hints at what to tweak next.


Thanks in advance! :thumb:


----------



## Jspinks020

AlphaC said:


> If you mean the 3200MHz CL16 EVGA kit, I would avoid it. I have it and it is Hynix MFR.


Yeah....Should of got a different kit...That one likes the XMP Profile about it.


----------



## Spectre73

Jackalito said:


> Hey guys, I could use your help to get my RAM (G.Skill F4-3200C14-32GTZ - Sammy B-Die) stable again at 3200MHz. It was stable with my previous combo ASUS CH6 + 1700X, but I can't use the same settings to make it stable at 3200 with the new one, ASUS CH7 + 2700X:
> So far I've only managed to get my memory stable at 3066MHz using the Ryzen DRAM Calculator as basis.
> 
> Here are the settings:


I immediately gained a ton of stability by reducing ProcODT to 53.3.

I am using a 1600x with 2x G.Skill B-Die F4-3200C14-16GTZSW (32 GB). RAM voltage is at 1.375v (it was unstable at 1.35).

It ist still not 100% stable. But only RamTest (Karhu) throws a very occasional error. I am in search for the last setting that would give me 100% stability.


----------



## rdr09

man from atlantis said:


> Using your timings i finally can run @3600MHz with no problem. Mem test havent given any errors for 15mins. I reduced the tRCDRD to 14 just to ease my ocd.
> 
> vDIMM @1.44v, vSoC @1.125v
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [email protected], 3200MHz CL14 XMP, [email protected]/9000, Shadow of the Tomb Raider *145FPS*
> https://abload.de/img/4300x3200xmpx2075x90011dsx.png
> 
> [email protected], 3466MHz CL14 tight timings, [email protected]/9000, Shadow of the Tomb Raider *172FPS*
> https://abload.de/img/4300x3466x2075x9000u8cf1.png
> 
> [email protected], 3600MHz CL14 looser timings, [email protected]/9000, Shadow of the Tomb Raider *175FPS*
> https://abload.de/img/4300x3600x2075x9000fbi05.png


Great job.

I'm tempted to use Mr. Philo's settings on my FlareX, too. Hardly any difference between 3466 and 3600 but huge from 3200. What will you end up using?


----------



## Jspinks020

Some CL18 timings 18-20-20-39-81-615 and the 1tcr. Everything still about the same, just started the slacking slightly, see if it will hold up 3466 next 24hrs. I got some BSOD while I was asleep last time...sometimes immediate BSOD's...it needs slacked. 

You all are Probably right we all should be over 3200 easily in the modern age, that was like 4 or 5 years ago stuff.


----------



## man from atlantis

rdr09 said:


> Great job.
> 
> I'm tempted to use Mr. Philo's settings on my FlareX, too. Hardly any difference between 3466 and 3600 but huge from 3200. What will you end up using?


Im gonna keep on using 3466tight timings, as you said theres hardly any difference and the soc voltage is tad high for my liking. I was having 140w idle power consumption (2 screen and a router) with 3466 and 150w w 3600mhz. 3466 is rock rock solid. Im gonna try undervolting from now on as i broke the 2000 barrier on cinebench15 @4.35ghz/3600mhz lol.


----------



## MrPhilo

rdr09 said:


> Great job.
> 
> I'm tempted to use Mr. Philo's settings on my FlareX, too. Hardly any difference between 3466 and 3600 but huge from 3200. What will you end up using?





man from atlantis said:


> Im gonna keep on using 3466tight timings, as you said theres hardly any difference and the soc voltage is tad high for my liking. I was having 140w idle power consumption (2 screen and a router) with 3466 and 150w w 3600mhz. 3466 is rock rock solid. Im gonna try undervolting from now on as i broke the 2000 barrier on cinebench15 @4.35ghz/3600mhz lol.


I went back down to 3533 which is a pretty good sweet spot, 3466 with tight timing is just as good.

I'm at 3533 CL14 at 1.45v with just a bit tighter timing than my 3600, also i'm down to 1.1v for SoC now.


----------



## Jackalito

Spectre73 said:


> I immediately gained a ton of stability by reducing ProcODT to 53.3.
> 
> I am using a 1600x with 2x G.Skill B-Die F4-3200C14-16GTZSW (32 GB). RAM voltage is at 1.375v (it was unstable at 1.35).
> 
> It ist still not 100% stable. But only RamTest (Karhu) throws a very occasional error. I am in search for the last setting that would give me 100% stability.



Thanks, Spectre! I've been gathering some insights from the threads where I asked for help. Will be testing your settings as well and report back as soon as I can :thumb:


----------



## Jspinks020

It's no go...gonna stay with 3200 awhile...unless I buy another kit. And it's dropped and Tight CL15 timings it's very stable...I'm afraid that's where many are gonna be some kit's. That's still okay though and runs good. the x370 side their still catching hell to even run 3200 or some junk...


----------



## kazablanka

dram voltage: 1.46v
vsoc: 1.1v

cpu stock (pbo enabled / -0.1v offset)


----------



## Myllox

man from atlantis said:


> Using your timings i finally can run @3600MHz with no problem. Mem test havent given any errors for 15mins. I reduced the tRCDRD to 14 just to ease my ocd.
> 
> vDIMM @1.44v, vSoC @1.125v
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [email protected], 3200MHz CL14 XMP, [email protected]/9000, Shadow of the Tomb Raider *145FPS*
> https://abload.de/img/4300x3200xmpx2075x90011dsx.png
> 
> [email protected], 3466MHz CL14 tight timings, [email protected]/9000, Shadow of the Tomb Raider *172FPS*
> https://abload.de/img/4300x3466x2075x9000u8cf1.png
> 
> [email protected], 3600MHz CL14 looser timings, [email protected]/9000, Shadow of the Tomb Raider *175FPS*
> https://abload.de/img/4300x3600x2075x9000fbi05.png


You running those settings stable? like 4hrs Karhu?


----------



## man from atlantis

Myllox said:


> man from atlantis said:
> 
> 
> 
> Using your timings i finally can run @3600MHz with no problem. Mem test havent given any errors for 15mins. I reduced the tRCDRD to 14 just to ease my ocd.
> 
> vDIMM @1.44v, vSoC @1.125v
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [email protected], 3200MHz CL14 XMP, [email protected]/9000, Shadow of the Tomb Raider *145FPS*
> https://abload.de/img/4300x3200xmpx2075x90011dsx.png
> 
> [email protected], 3466MHz CL14 tight timings, [email protected]/9000, Shadow of the Tomb Raider *172FPS*
> https://abload.de/img/4300x3466x2075x9000u8cf1.png
> 
> [email protected], 3600MHz CL14 looser timings, [email protected]/9000, Shadow of the Tomb Raider *175FPS*
> https://abload.de/img/4300x3600x2075x9000fbi05.png
> 
> 
> 
> You running those settings stable? like 4hrs Karhu?
Click to expand...

I don't have any cold boot or bsod issues, which is fine by me


----------



## Myllox

man from atlantis said:


> I don't have any cold boot or bsod issues, which is fine by me


Awesome! congrats 

Its where im at i guess, several runs of Karhu with single errors at 5000-10000% .. no issues otherwise


----------



## man from atlantis

HCI 16 instances over 200% coverage
3500MHz CL14 tight timings vDIMM @1.44v, [email protected], dirty voltages, i think i can pass the test with lower voltages.


----------



## Synoxia

Is GSAT still reliable? I've just noticed that my DRAM gets up to 46c while gaming, while under GSAT only up to 38c...


----------



## Jspinks020

Sorry it's not Nicer at only 3200 and 15-15-15-36 cr1 and you can drop TRFC a few notches. About the Best I can do. That kit resets won't boot some timings too low either....but not bad...I think it reads slightly more than my 7700k. What I said awesome chip and mastered good cruising top clock and nothing crazy. And what they said Don't really Need a Crazy VRM for that.


----------



## mc conor

Hey guys,

I'm doing a 2700x build and am looking for the fastest 16gb kit in the uk.

https://www.overclockers.co.uk/team...4500mhz-dual-channel-kit-black-my-09a-tg.html


Thinking that this should get down to a low latency on 3466 as it seems to be quite well binned.

Has anyone had experience with this kit or any recommendations for the best possible 16gb set in the uk?


Thanks.


----------



## Myllox

mc conor said:


> Hey guys,
> 
> I'm doing a 2700x build and am looking for the fastest 16gb kit in the uk.
> 
> https://www.overclockers.co.uk/team...4500mhz-dual-channel-kit-black-my-09a-tg.html
> 
> 
> Thinking that this should get down to a low latency on 3466 as it seems to be quite well binned.
> 
> Has anyone had experience with this kit or any recommendations for the best possible 16gb set in the uk?
> 
> 
> Thanks.


premium b-die .. excellent choice  .. im guessing you would be able to hit 3600 cl14 quite easy if you get a good 2700x chip (good quality IMC)


----------



## FJSAMA

man from atlantis said:


> HCI 16 instances over 200% coverage
> 3500MHz CL14 tight timings vDIMM @1.44v, [email protected], dirty voltages, i think i can pass the test with lower voltages.


Whats your 3466 timings and voltages?
Dunno if i miss any post or page but im curious, thanks


----------



## rdr09

mc conor said:


> Hey guys,
> 
> I'm doing a 2700x build and am looking for the fastest 16gb kit in the uk.
> 
> https://www.overclockers.co.uk/team...4500mhz-dual-channel-kit-black-my-09a-tg.html
> 
> 
> 
> Thinking that this should get down to a low latency on 3466 as it seems to be quite well binned.
> 
> Has anyone had experience with this kit or any recommendations for the best possible 16gb set in the uk?
> 
> 
> Thanks.




Too expensive. Try to look for G.Skill FlareX 3200 Cl4 or this

https://www.overclockers.co.uk/team-group-dark-pro-8pack-edition-16gb-2x8gb-ddr4-pc4-25600c14-3200mhz-dual-channel-kit-black-my-08l-tg.html#write_comment


----------



## porschedrifter

Guys I'm having a horrible time trying to get my gskill ripjaws v to boot at 3600.
Xmp for that is 19-20-20-40 at 1.35. SOC is 1.1 and running stock clocks on my 1700x to rule things out. Xmp won't boot at all. I've tried cldo voltage as well as procodt.

Crosshair vi, 1700x, 3600mhz 16gb

Prepared by Thaiphoon Burner Super Blaster
-------------------------------------------------------------
MEMORY MODULE
-------------------------------------------------------------
Manufacturer : G.Skill
Series : Ripjaws V Red
Part Number : F4-3600C19-16GVRB
Serial Number : 00000000h
JEDEC DIMM Label : 16GB 2Rx8 PC4-2133-UB1-10
Architecture : DDR4 SDRAM UDIMM
Speed Grade : DDR4-2133
Capacity : 16 GB (16 components)
Organization : 2048M x64 (2 ranks)
Register Manufacturer : N/A
Register Model : N/A
Manufacturing Date : Undefined
Manufacturing Location : Taipei, Taiwan
Revision / Raw Card : 0000h / B1 (8 layers)
-------------------------------------------------------------
DRAM COMPONENTS
-------------------------------------------------------------
Manufacturer : Hynix
Part Number : H5AN8G8NCJR-TFC
Package : Standard Monolithic 78-ball FBGA
Die Density / Count : 8 Gb C-die (18 nm) / 1 die
Composition : 1024Mb x8 (64Mb x8 x 16 banks)
Clock Frequency : 1067 MHz (0.938 ns)
Minimum Timing Delays : 15-15-15-36-50
Read Latencies Supported : 16T, 15T, 14T, 13T, 12T, 11T, 10T
Supply Voltage : 1.20 V
XMP Certified : 1802 MHz / 19-20-20-40-60 / 1.35 V
XMP Extreme : Not programmed
SPD Revision : 1.0 / January 2014
XMP Revision : 2.0 / December 2013
-------------------------------------------------------------
SOURCE SPD DUMP
-------------------------------------------------------------
000 23 10 0C 02 85 21 00 08 00 40 00 03 09 03 00 00
010 00 00 08 0C F8 03 00 00 6E 6E 6E 11 08 76 F0 0A
020 20 08 00 05 00 A8 1E 2B 2E 00 00 00 00 00 00 00
030 00 00 00 00 00 00 00 00 00 00 00 00 15 2B 16 36
040 0B 2B 0C 36 00 00 36 15 2B 0C 2C 16 2B 0C 00 00
050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
070 00 00 00 00 00 83 B5 CE 00 00 00 00 00 C2 AF 7E
080 11 11 21 01 00 00 00 00 00 00 00 00 00 00 00 00
090 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 74 DF
100 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
110 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
120 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
130 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
140 04 CD 00 00 00 00 00 00 00 46 34 2D 33 36 30 30
150 43 31 39 2D 31 36 47 56 52 42 00 00 00 00 80 AD
160 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
170 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
180 0C 4A 05 20 00 00 00 00 00 A3 00 00 05 00 10 00
190 00 54 58 58 10 B1 0A F0 0A 20 08 00 05 00 C0 11
1A0 27 00 00 00 00 00 00 00 00 E6 A0 CD 9B 9B D2 BA
1B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00


----------



## Jspinks020

It's Samsung B-die kit and I want it...Probably Overclocks. what the hell went wrong and is wrong with Hynix?...Avoid it like the plague...it's absolutely unstable....


----------



## thomasck

[email protected] 1.15v---BIOS 5.1---HCI---200%+---CMU16GX4M2C3200C16 

RAM is a corsair vengeance led 3200 v5.39. Thaipoon reports Hynix AFR but somehow looks like is MFR.


----------



## Handrox

G.Skill Trident Z DDR4 3600 PC4-28800 16GB 2x8GB CL16


----------



## Jspinks020

Yeah was also thinking the Trident Z....But like I said not bad with the evga kit.


----------



## Ex0cet

I've been using this timings since the first day I bought my 2700x + C7H. Everything was rock solid stable so I was very lazy and didn't waste any more efforts trying to improve on this.

I bet I could shave a few millivolts here and there and even tighten a few more timings with more patience in hand... Anyhow I'm quite happy with the performance.


----------



## kazablanka

Handrox said:


> G.Skill Trident Z DDR4 3600 PC4-28800 16GB 2x8GB CL16


Nice timings ,try hci memtest at least 1000% coverage if you want to test for real stability ,memtest64 is too weak and 63 loops is a really short testing. I used to test with memtest64 in the past but not anymore.


----------



## Handrox

Jspinks020 said:


> Yeah was also thinking the Trident Z....But like I said not bad with the evga kit.


These modules are being a pleasant surprise, just for benchmark, to use 3600MHz @ CL12


kazablanka said:


> Nice timings ,try hci memtest at least 1000% coverage if you want to test for real stability ,memtest64 is too weak and 63 loops is a really short testing. I used to test with memtest64 in the past but not anymore.


I already use time, games, editing, everything without the slightest problem. I passed the memtest just to join the thread.


----------



## MrWhiteRX7

Played around with my 3466 settings tonight and found that lowering my soc actually allowed me to bring down the Tfaw from 36 to 16. Still learning new tricks with these things! 

Next it's time to shoot for 3600... just bumping ddrvoltage to 1.45 it gets me in and able to bench at exact same timings/ sub timings for my current 3466 settings but I'm getting an error here and there when memtesting. Hopefully it won't take too much hassle to get it stable!


----------



## Handrox

MrWhiteRX7 said:


> Played around with my 3466 settings tonight and found that lowering my soc actually allowed me to bring down the Tfaw from 36 to 16. Still learning new tricks with these things!
> 
> Next it's time to shoot for 3600... just bumping ddrvoltage to 1.45 it gets me in and able to bench at exact same timings/ sub timings for my current 3466 settings but I'm getting an error here and there when memtesting. Hopefully it won't take too much hassle to get it stable!


Here I got 3600MHz CL14 using 1.46v and 3666MHz CL14 with 1.49v


----------



## MrWhiteRX7

Handrox said:


> Here I got 3600MHz CL14 using 1.46v and 3666MHz CL14 with 1.49v


That's what I'll be doing. I only did a quick test at 1.45 and it benches great but gives an error here and there so not completely stable in memtest. Gonna go up to 1.46 and also play with soc just a tad. I think 3600 will be pretty easy from here. 3666 we'll see lol


----------



## MrPhilo

man from atlantis said:


> Using your timings i finally can run @3600MHz with no problem. Mem test havent given any errors for 15mins. I reduced the tRCDRD to 14 just to ease my ocd.
> 
> vDIMM @1.44v, vSoC @1.125v
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [email protected], 3200MHz CL14 XMP, [email protected]/9000, Shadow of the Tomb Raider *145FPS*
> https://abload.de/img/4300x3200xmpx2075x90011dsx.png
> 
> [email protected], 3466MHz CL14 tight timings, [email protected]/9000, Shadow of the Tomb Raider *172FPS*
> https://abload.de/img/4300x3466x2075x9000u8cf1.png
> 
> [email protected], 3600MHz CL14 looser timings, [email protected]/9000, Shadow of the Tomb Raider *175FPS*
> https://abload.de/img/4300x3600x2075x9000fbi05.png


No problem, I have decrease my SoC to 1.125 as well, working great so far. RAM is still at 1.49v though.

Just noticed the 30fps increase from 3200cl14 default timing to 3600cl14. That is quite a lot tbh.


----------



## Darkomax

Yes subtimings make a ridiculous difference in some games, I observed a big gain in The Witcher 3 as well (better test in Novigrad). Like 15% more FPS just from going from XMP to fast setting.


----------



## nick name

Man, I am jealous of the folks that are getting 3600 @ 14-14-14-14 to run stable and with decent sub-timings.


----------



## 6950X

The absolute best memory for Ryzen right now is;

G.Skill TridentZ DDR4 3600 CAS15. This memory kit is only $229 it is premium Samsung B-Die. Intel guys were hitting 4266Mhz-4400mhz on this ram Kit first try.

The right 2700X will run it at 3600 CAS 14. 

A lot of people were reporting XMP 3600 CAS15 is working on some X470 boards So, that would be my go to kit. And, whenever Ryzen 3000 comes, and X570, you can push even further! 

Here’s the kit I’m referring to, if your building a 2700X pick no less then that.

https://m.newegg.com/products/N82E16820232306


----------



## MrPhilo

kazablanka said:


> dram voltage: 1.46v
> vsoc: 1.1v
> 
> cpu stock (pbo enabled / -0.1v offset)


Nice score, especially with geardown turned off.

Sometime I wish I went to the x470 Prime Pro instead of the Crosshair VII. I know you use to have VII before and you changed to x470 Pro, is the ram more stable on there than the VII for you?


----------



## thomasck

thomasck said:


> [email protected] 1.15v---BIOS 5.1---HCI---200%+---CMU16GX4M2C3200C16
> 
> 
> 
> RAM is a corsair vengeance led 3200 v5.39. Thaipoon reports Hynix AFR but somehow looks like is MFR.


Got over 1500% no errors with the configuration above with bumped voltages, 1.45V and soc 1.165V. 

3333 1.5V gives me errors after 400%. 

ATM testing 3200 with tighter timings, once I can't get 3333 stable. I've read around these hynix mfr would work in between 1.5-1.7V, but I consider too high. 

Sent from my HTC U11 using Tapatalk

Edit,

Just a little update, running with the config above at 1.45V. That might be helpful to someone.. The sticks are Corsair Vengeance 3200 Led V5.39 - Hynix MFR. Mobo is a Taichi x370.



Spoiler


----------



## Vrbaa

Is it right to keep RAM at lowest possible timings? By that I mean I have tested every timing (primary and also all other timings) to lowest possible value doing it one by one, stress testing using AIDA and Prime95... Is it safe?


----------



## The Sandman

Vrbaa said:


> Is it right to keep RAM at lowest possible timings? By that I mean I have tested every timing (primary and also all other timings) to lowest possible value doing it one by one, stress testing using AIDA and Prime95... Is it safe?



For stressing memory I'd recommend to use HCI Memtest and/or Karhu Ramtest.
AIDA is to weak and while Prime95 can stress ram in a custom run it may take longer than the two mentioned previously.


Use AIDA for the Cache & Memory Benchmark to see how your changes have helped or .... plus it gives you something to compare against others with the same kit to see how you've done.


----------



## w0mbat

I got a question for you guys that I just can't seem to figure out. We all know that GDM acts kinda like a "1.5T" settings and helps to stabilize settings that aren't fully stable at 1T. Turning GDM off is supposed to reduce latency and increase performance.

But what I have found is that turning GDM off _increases_ the latency on my system. For example, my Samsung B-die kit running at 3200 CL14 GDM=on achieves about 64.8ns latency in Aida64. With GDM=off I get >66ns.

The GDM off setting is 100% stable. >10.000% in Karhu, >10.000% in HCI, Prime95 stable an zero crashes while gaming.

How come that turning GDM=off _increases_ the latency in the Aida64 test? Am I the only one here or is this normal behavior?


----------



## Vrbaa

The Sandman said:


> For stressing memory I'd recommend to use HCI Memtest and/or Karhu Ramtest.
> AIDA is to weak and while Prime95 can stress ram in a custom run it may take longer than the two mentioned previously.
> 
> 
> Use AIDA for the Cache & Memory Benchmark to see how your changes have helped or .... plus it gives you something to compare against others with the same kit to see how you've done.


I'm using geekbench and Aida64 benchmark. I see better results but is it safe to keep all timinga at lowest possible settings? I see people are using some formulas which said one timing should be equal to sum of other two timings etc. But for me all the timings are lowest possible and if I'm going to tighten up one of them it won't be stable anymore. It took a long time to get this all stable but now it is. 
Yes, I also tested with HCI memtest for 12h and much more stress testing tools.


----------



## nick name

Vrbaa said:


> I'm using geekbench and Aida64 benchmark. I see better results but is it safe to keep all timinga at lowest possible settings? I see people are using some formulas which said one timing should be equal to sum of other two timings etc. But for me all the timings are lowest possible and if I'm going to tighten up one of them it won't be stable anymore. It took a long time to get this all stable but now it is.
> Yes, I also tested with HCI memtest for 12h and much more stress testing tools.


In gaming there can be too tight.


----------



## Ex0cet

I tightened timings a little bit more and lowered CPUv and SOCv (both with an -0.0750 offset now), PE: LVL 2, RAM is 1.4v.


----------



## Ex0cet

Ex0cet said:


> I tightened timings a little bit more and lowered CPUv and SOCv (both with an -0.0750 offset now), PE: LVL 2, RAM is 1.4v.


Same as before, but even even tighter. 

I'm done for today.


----------



## thomasck

Update, best settings I've got so far.. Bought HCI the other day, I've being using it on daily basis basically, turned out to be the best stability test in my cenario.

hynix mfr 3200 cl16



Spoiler


----------



## fragamemnon

Has anyone posted with 3600MHz or higher RAM on a first-gen Ryzen?

These are my current best settings on a R7 1700 @ 3.9GHz.


----------



## Reous

fragamemnon said:


> Has anyone posted with 3600MHz or higher RAM on a first-gen Ryzen?


There are several results with DDR4-3600 in the first post.


----------



## fragamemnon

Reous said:


> There are several results with DDR4-3600 in the first post.



Correct, silly of me. I was about to complain that the link redirects to the URL posts don't work. But now I figured I can search within the thread for these users' posts.
Sorry!


----------



## aepseidhe

Hello, maybe someone will have some input on below issue with b-die kits.
I had spare 2x8 GB F4-3200C15-8GVK ( part of quad memory kit - it's b-die, I guess now, the poor ones) so I decided to use it in cheap build:
- ryzen 2200g
- asrock b450m pro 4 later replaced with asus b450m tuf pro-gaming (asrock is quite garbrage mobo even it was cheap had a lot of weird issues)

Issue:
I cannot set CAS to 15 - it works only as CAS 16 when used as +3000mhz (other parameters as from XMP)

on Asrock I was able to achieve:
3200 16/15/15/15/35/50 @ 1.3v (SOC 1.1)

on asus I'm able to get
3200 16/15/15/15/35/50 @ 1.28v (SOC 1.05) (played some cs-go +12h memtest)
3533 16/15/15/15/35/50 @ 1.39v (SOC 1.1) (did not test it much but I was able play some CS-GO for few hours)

Currently
340016/15/15/15/35/50 @ 1.35v (SOC 1.1)

but it's always that CAS 16 instead of 15 (leave alone CAS 14).

Is this an issue with CPU (got it used - don't know the history of it - ?maybe controller was used hard way?) or memory (badly binned)?


Please advise.

Thank you!


----------



## LicSqualo

fragamemnon said:


> Has anyone posted with 3600MHz or higher RAM on a first-gen Ryzen?
> 
> These are my current best settings on a R7 1700 @ 3.9GHz.


With this last Agesa 1.0.0.6, bios 6401 on Asus C6H, my 1700 actually run at 4090 MHz with a base clock of 101 MHz. The ram run at 3568 MHz (3533 preset) with c14 timings (perhaps really tights).

Actually I'm lowering the VSoc.


----------



## nick name

aepseidhe said:


> Hello, maybe someone will have some input on below issue with b-die kits.
> I had spare 2x8 GB F4-3200C15-8GVK ( part of quad memory kit - it's b-die, I guess now, the poor ones) so I decided to use it in cheap build:
> - ryzen 2200g
> - asrock b450m pro 4 later replaced with asus b450m tuf pro-gaming (asrock is quite garbrage mobo even it was cheap had a lot of weird issues)
> 
> Issue:
> I cannot set CAS to 15 - it works only as CAS 16 when used as +3000mhz (other parameters as from XMP)
> 
> on Asrock I was able to achieve:
> 3200 16/15/15/15/35/50 @ 1.3v (SOC 1.1)
> 
> on asus I'm able to get
> 3200 16/15/15/15/35/50 @ 1.28v (SOC 1.05) (played some cs-go +12h memtest)
> 3533 16/15/15/15/35/50 @ 1.39v (SOC 1.1) (did not test it much but I was able play some CS-GO for few hours)
> 
> Currently
> 340016/15/15/15/35/50 @ 1.35v (SOC 1.1)
> 
> but it's always that CAS 16 instead of 15 (leave alone CAS 14).
> 
> Is this an issue with CPU (got it used - don't know the history of it - ?maybe controller was used hard way?) or memory (badly binned)?
> 
> 
> Please advise.
> 
> Thank you!


You will have to disable Geardown mode if you want to run odd CL timings. If the system can't train that right away it will change it to the next even CL timing.


----------



## aepseidhe

nick name said:


> You will have to disable Geardown mode if you want to run odd CL timings. If the system can't train that right away it will change it to the next even CL timing.


It's weird b-die [email protected] cannot work [email protected] I have disabled Geardown mode and then computer did not start at all.

What I did:
a) load xmp - no other changes - [email protected] started (soc in HWmonitor @ 1.2)
b) set procODT at 60ohm - no change in results
c) I have increased voltage to 1.4 - no changes
d) geardown mode disabled - no boot

Later I played with frequencies and voltages without modifying other parameters, that's why I found it worked at 3533 /3400 / 3466 with almost no changes with SOC at 1.1

UPDATE: my Ryzen (or in general?) does not work at CL15 so when I loaded xmp it started to fail ...

I just took all settings (maybe except procd with 60ohm) from safe preset for b-die and I have now:

- iGPU @ 1550 mhz- GFXv 1.1875v, SOC 1.1v
- RAM @ [email protected] 1.35v - safe preset - special thanks for -antero- (user) who mentioned in here the b-die do not work at CL15 at all

Cheers and thank for to help!

Summary: for other G.SKILL ripjaws [email protected] ... just run it like it was [email protected]


----------



## MrPhilo

My new setup, decided to go for lower voltage instead of going for 3600CL14 with pretty high voltage.

4.25Ghz at 1.375v
3533CL14 at 1.415v (yes, pretty low but surprising)
SoC at 1.025v


----------



## tiagogl

Hello guys I really need your help.

I performed a lot of memory tests like AIDA , HCI more then 400% and also Linx and my memory looks stable . I have F4-3600C17-32GTZR running 3200 CL14 , 1.365V, SOC 1.05. No CPU overclock , just using PBO of my Strix X370. My battlefield 5 is failing without any error message . I'm having on event viewer just message about APPCRASH KERNELBASE.DLL. Any tip to identify if my memory is not really stable on the games? 

I tried new CAD_BUS like 24 , 24 , 20 ,20 and not helped.


----------



## Flexarius

Hi,

i have problems with my settings

2700X
Asus CHVII @1201v Bios
G.Skill F4-3600C15D-16GTZ

Is there some experience which is the best setting for 3466 MHz, 3533 MHz, 3600 MHz. The most pre-settings safe/fast from DRAM Calculator 1.4 are unstable or RAM-Test errors 100-500%. 

Is here someone with this RAM-Kit?


----------



## aepseidhe

Flexarius said:


> Hi,
> 
> i have problems with my settings
> 
> 2700X
> Asus CHVII @1201v Bios
> G.Skill F4-3600C15D-16GTZ
> 
> Is there some experience which is the best setting for 3466 MHz, 3533 MHz, 3600 MHz. The most pre-settings safe/fast from DRAM Calculator 1.4 are unstable or RAM-Test errors 100-500%.
> 
> Is here someone with this RAM-Kit?



Hi that's, quite weird cause I do have:
- 2200g (zen 1 @ 14nm)
- G.Skill F4-3200C15Q-32GVK (but using only half of it -> 2x F4-3200C15-8GVK)
- Asus B450m PRO Tuf Gaming

and with using settings from "Ryzen DRAM Calculator" for safe preset I was able to achieve [email protected] - only differences:
- SOC voltage at 1.1v due to using Vega 8 overclocked to 1550 mhz
- DRAM voltage at 1.395v
- procODT at 60 ohm

The rest set exactly the same as in DRAM calculator for safe preset - Tested - memtest DOS + HCI (450%).

Zen+ should give better results for DDR overclocking than Zen1. The bioses are in corresponding versions - (yours 1201v bios looks like the one which I'm using based on description of changes).


----------



## nick name

Flexarius said:


> Hi,
> 
> i have problems with my settings
> 
> 2700X
> Asus CHVII @1201v Bios
> G.Skill F4-3600C15D-16GTZ
> 
> Is there some experience which is the best setting for 3466 MHz, 3533 MHz, 3600 MHz. The most pre-settings safe/fast from DRAM Calculator 1.4 are unstable or RAM-Test errors 100-500%.
> 
> Is here someone with this RAM-Kit?


You want to make sure you are paying attention to the labels in the Calculator and in BIOS. If you're trying to use the timings that are 14-14-15-14 from the Calculator they actually go into BIOS as 14-15-14-14. If that 15 is in the incorrect field it will bork it. The field that is swapped in the calculator and ASUS BIOS is *tRCDRD*. Once I figured out I wasn't paying attention to the fields it changed the game.


----------



## 1usmus

*DRAM Calculator for Ryzen™ 1.4.1
*

https://www.overclock.net/forum/27810904-post3824.html

love everyone


----------



## thomasck

1usmus said:


> *DRAM Calculator for Ryzen[emoji769] 1.4.1
> 
> *
> 
> 
> 
> https://www.overclock.net/forum/27810904-post3824.html
> 
> 
> 
> love everyone


Thanks 1usmus! Your tool is very helpful! 

Sent from my HTC U11 using Tapatalk


----------



## MrPhilo

1usmus said:


> *DRAM Calculator for Ryzen™ 1.4.1
> *
> 
> https://www.overclock.net/forum/27810904-post3824.html
> 
> love everyone


Hi pal

Do you have that post where you go on to talk about what type of timing could cause small errors or loosening certain timing can reduce voltage etc

I had it as favourite but some reason its gone now


----------



## Bruizer

tiagogl said:


> Hello guys I really need your help.
> 
> I performed a lot of memory tests like AIDA , HCI more then 400% and also Linx and my memory looks stable . I have F4-3600C17-32GTZR running 3200 CL14 , 1.365V, SOC 1.05. No CPU overclock , just using PBO of my Strix X370. My battlefield 5 is failing without any error message . I'm having on event viewer just message about APPCRASH KERNELBASE.DLL. Any tip to identify if my memory is not really stable on the games?
> 
> I tried new CAD_BUS like 24 , 24 , 20 ,20 and not helped.


You aren't the only one with Battlefield V failing without any error message (happens after a round or two almost religiously). Beginning to think it's a BFV issue, not a my ram issue.


----------



## thomasck

Bruizer said:


> You aren't the only one with Battlefield V failing without any error message (happens after a round or two almost religiously). Beginning to think it's a BFV issue, not a my ram issue.


Yeah sure is a bf5 issue. Been running ram completely stable for some days after matching write voltage and suddenly bf5 just does not launch. Bf1 works normal and other games as well. 

Sent from my HTC U11 using Tapatalk


----------



## Wuest3nFuchs

1usmus said:


> *DRAM Calculator for Ryzen[emoji769] 1.4.1
> *
> 
> https://www.overclock.net/forum/27810904-post3824.html
> 
> love everyone [/quote @1usmus
> 
> excellent!
> Thanks man!
> 
> Gesendet von meinem SM-G950F mit Tapatalk


----------



## ilmazzo

Anyone upgraded to 2.0 bios with 1.0.0.6 agesa on the X470 Taichi? I think I'll move to it this weekend, let's see what changed keeping my actual settings ([email protected],25 fixed speed with fixed voltage of 1,44V and 3400 CL14 1,4Vdimm)

I'll try to check if I'm stable at 3466 too but for 3600 I would have to raise voltage to 1,45V on dimms and I'm not confident to go with that voltage on the long run, even if they are samsung b-die....


----------



## Martin778

G.Skill offers B-Die kits that run 1.45V on XMP settings 
They had 1.50V ones but they got discontinued and the highest are 1.45V. Wonder why...


----------



## ilmazzo

Martin778 said:


> G.Skill offers B-Die kits that run 1.45V on XMP settings
> They had 1.50V ones but they got discontinued and the highest are 1.45V. Wonder why...


You are tempting me bro'


----------



## binder87

Hi. 
So I'm about to get a pair of trident z 3200 cl16, samsung E die. I know this one really likes higher voltages. What's the absolute max safe 24/7 voltage on a samsung e die? There's a 120mm fan blowing nearby .


----------



## cicero s

Bruizer said:


> You aren't the only one with Battlefield V failing without any error message (happens after a round or two almost religiously). Beginning to think it's a BFV issue, not a my ram issue.



Same situation here. 3466CL14 had to be adjusted in order to prevent the soft crash (game silently exits without any warning). I had to increase DRAM voltage and trfc value. BFV really hates overclocked RAMs.


----------



## rul3s

Hi guys!
I have a Ryzen 5 2600 and KFA2 DDR4 4000 CL19 and now I'm setting it properly.
With help of Ryzen DRAM Calculator I've setted it up like this, with CPU stock:

- Timmings 14-14-14-30 (Ryzen Dram Calculator for Bdie, Safe presset)
- Vsoc Offset +0,025 (1.25v)
- Vram 1.4v

I've runned Realbench, 3DMark correctly. Also, Google Apps Stress Test without issues, but, when started to playing PUBG, I couldn't finish a match without crashing the game. After that, I've tried HCI and after 15 minutes of working, it found one error.
So, in my case, PUBG and HCI found a memory issue althought Google Stress App (from windows) didn't found anything.
Now I've setted +0,05 on Vsoc (1.15-1.165v) and retesting again.


----------



## BLUuuE

*Initial testing*

Recently got myself a 2600, B450 Tomahawk and 2x8GB Hynix AFR sticks.



Spoiler















1.420v DRAM and 1.025v SOC.

I'm slowly transferring to The Stilt's Hynix AFR extreme timings. Hopefully all goes well.


----------



## ilmazzo

Yesterday night I was giving a try to this setting posted by our loved user 1usmus

https://www.overclock.net/forum/27804162-post3803.html

The second and more demanding one, so I managed to set my setup in this way:

vsoc auto voltage with llc3 (1,1v)
1,45v vdram
cpu def + pbo on

here are some quick results just to have an idea to what to expect from it:





cinebench r15 netted a 1415 which is quite meh but this is not the focus of this rig, I will crank up the cpu as the last step


----------



## rul3s

rul3s said:


> Hi guys!
> I have a Ryzen 5 2600 and KFA2 DDR4 4000 CL19 and now I'm setting it properly.
> With help of Ryzen DRAM Calculator I've setted it up like this, with CPU stock:
> 
> - Timmings 14-14-14-30 (Ryzen Dram Calculator for Bdie, Safe presset)
> - Vsoc Offset +0,025 (1.25v)
> - Vram 1.4v
> 
> I've runned Realbench, 3DMark correctly. Also, Google Apps Stress Test without issues, but, when started to playing PUBG, I couldn't finish a match without crashing the game. After that, I've tried HCI and after 15 minutes of working, it found one error.
> So, in my case, PUBG and HCI found a memory issue althought Google Stress App (from windows) didn't found anything.
> Now I've setted +0,05 on Vsoc (1.15-1.165v) and retesting again.


I can't achieve 3200 14-14-14-30-44 on Sasmung B-Die, Motherboard Gigabyte x470 Ultra gaming, Ryzen 5 2600. I've tried all Vsco from 1.10 (minimum) to 1.20... any idea or suggestion? Maybe motherboard fault?
After 1h of HCI it throws 1 error almost every instance of it (12).


----------



## alefim

rul3s said:


> I can't achieve 3200 14-14-14-30-44 on Sasmung B-Die, Motherboard Gigabyte x470 Ultra gaming, Ryzen 5 2600. I've tried all Vsco from 1.10 (minimum) to 1.20... any idea or suggestion? Maybe motherboard fault?
> After 1h of HCI it throws 1 error almost every instance of it (12).


Ryzen 2600 4,2Ghz 1.375v LLC Auto
MEM GSKill 3600 CL16 @ CL14 1.46v
Soc 1.075v LLC Auto
CLDO_VDDP 0.915v

MOBO MSI X470 M7 AC

https://www.overclock.net/forum/13-...lator-ryzena-1-4-1-overclocking-dram-am4.html

https://www.overclock.net/forum/26472770-post445.html

https://www.overclock.net/forum/26902089-post1334.html


----------



## Darkomax

I achieved 3400MHz with a Strix X370-I and 2x8GB 3200 from Galax (it passed 50 passes before). Trying 3466 now.


----------



## The Sandman

rul3s said:


> Hi guys!
> I have a Ryzen 5 2600 and KFA2 DDR4 4000 CL19 and now I'm setting it properly.
> With help of Ryzen DRAM Calculator I've setted it up like this, with CPU stock:
> 
> - Timmings 14-14-14-30 (Ryzen Dram Calculator for Bdie, Safe presset)
> - Vsoc Offset +0,025 (1.25v)
> - Vram 1.4v
> 
> I've runned Realbench, 3DMark correctly. Also, Google Apps Stress Test without issues, but, when started to playing PUBG, I couldn't finish a match without crashing the game. After that, I've tried HCI and after 15 minutes of working, it found one error.
> So, in my case, PUBG and HCI found a memory issue althought Google Stress App (from windows) didn't found anything.
> Now I've setted +0,05 on Vsoc (1.15-1.165v) and retesting again.





rul3s said:


> I can't achieve 3200 14-14-14-30-44 on Sasmung B-Die, Motherboard Gigabyte x470 Ultra gaming, Ryzen 5 2600. I've tried all Vsco from 1.10 (minimum) to 1.20... any idea or suggestion? Maybe motherboard fault?
> After 1h of HCI it throws 1 error almost every instance of it (12).


SOC set at 1.25v? Why so high?

Maximum recommended is 1.2v.
Even 1.15v - 1.165v seems high for 3200MHz imho.

Samsung B-Die S/S S/R at 3200MHz will usually run with SOC set to .950v to 1.050v.
Over volting causes instability same as under volting.

My Flare-X run 3466MHz with 1.07v SOC as an example. (HWinfo read SoC SV12 value)


----------



## rul3s

The Sandman said:


> rul3s said:
> 
> 
> 
> Hi guys!
> I have a Ryzen 5 2600 and KFA2 DDR4 4000 CL19 and now I'm setting it properly.
> With help of Ryzen DRAM Calculator I've setted it up like this, with CPU stock:
> 
> - Timmings 14-14-14-30 (Ryzen Dram Calculator for Bdie, Safe presset)
> - Vsoc Offset +0,025 (1.25v)
> - Vram 1.4v
> 
> I've runned Realbench, 3DMark correctly. Also, Google Apps Stress Test without issues, but, when started to playing PUBG, I couldn't finish a match without crashing the game. After that, I've tried HCI and after 15 minutes of working, it found one error.
> So, in my case, PUBG and HCI found a memory issue althought Google Stress App (from windows) didn't found anything.
> Now I've setted +0,05 on Vsoc (1.15-1.165v) and retesting again.
> 
> 
> 
> 
> 
> 
> rul3s said:
> 
> 
> 
> I can't achieve 3200 14-14-14-30-44 on Sasmung B-Die, Motherboard Gigabyte x470 Ultra gaming, Ryzen 5 2600. I've tried all Vsco from 1.10 (minimum) to 1.20... any idea or suggestion? Maybe motherboard fault?
> After 1h of HCI it throws 1 error almost every instance of it (12).
> 
> Click to expand...
> 
> SOC set at 1.25v? Why so high?
> 
> Maximum recommended is 1.2v.
> Even 1.15v - 1.165v seems high for 3200MHz imho.
> 
> Samsung B-Die S/S S/R at 3200MHz will usually run with SOC set to .950v to 1.050v.
> Over volting causes instability same as under volting.
> 
> My Flare-X run 3466MHz with 1.07v SOC as an example. (HWinfo read SoC SV12 value)
Click to expand...

I didn't say anything about 1.25 on VSOC, I've tried from 1.10 to 1.20.
Less i cant because gigabyte x470 ultra gaming sets the minimum on 1.10 when going to 3200 memòries... 😩


----------



## BLUuuE

After a few more days of testing on my OEM Hynix AFR sticks, the best I could get is 3333 C15.



Spoiler















1.025v SOC and 1.420v DRAM.

I can boot 3533 C17 with 1.480v DRAM, but it's unstable. Anything over 3333MHz is a hit or miss. 
One time, I thought I had 3400 C16 stable, then the next boot it would instantly error.


----------



## NightAntilli

I'm now in the process of upgrading my system to Ryzen... I currently have an FX-8320 and the plan is to get an X470 Taichi with an R7 1700 (too good to pass up for under $200). 

Now... I want to get 32 GB for my system, and the plan is to get a 3200MHz CL14 Trident Z kit (most likely this one). I'm not interested in ever upgrading this system to 64GB. So that leaves me with two choices: 

1) Getting 4 kits of single rank memory (4x8GB)
2) Getting 2 kits of dual rank memory (2x16GB)

The question is... Which one is more likely to give me the best overall performance with the R7 1700? Or in other words, which will provide me the best clocks and timings for all purpose usage?


----------



## nick name

NightAntilli said:


> I'm now in the process of upgrading my system to Ryzen... I currently have an FX-8320 and the plan is to get an X470 Taichi with an R7 1700 (too good to pass up for under $200).
> 
> Now... I want to get 32 GB for my system, and the plan is to get a 3200MHz CL14 Trident Z kit (most likely this one). I'm not interested in ever upgrading this system to 64GB. So that leaves me with two choices:
> 
> 1) Getting 4 kits of single rank memory (4x8GB)
> 2) Getting 2 kits of dual rank memory (2x16GB)
> 
> The question is... Which one is more likely to give me the best overall performance with the R7 1700? Or in other words, which will provide me the best clocks and timings for all purpose usage?


I'd assume getting the dual rank kit takes motherboard RAM topology out of the equation. Dual rank sticks get a little hotter, but can be more efficient. I'd go with the 2x16GB.


----------



## LTC

I have had no luck getting my 16GB kit of G-Skill F4-3600C17-8GVK running at 3200Mhz 14-14-14-14-30. These are "safe" values from the DRAM calculator, but no matter how much voltage I give (1.35-1.45) they are not stable in memTestPro. SOC voltage is stuck at 1.15V for some reason on the X470 Aorus Ultra Gaming motherboard, so I have no way of lowering that. I'm getting kinda frustrated as it seems easy to hit 3200Mhz with those timings for some people. Any tricks to make this work? I'm using a 2700X if that makes a difference.


----------



## miklkit

I have a 1700 and went with 4 sticks because I like how they fill all the slots. But 4 sticks will not clock as high as 2 sticks because they put more load on the cpu. So the choice is looks or performance. I ended up at 3030mhz vs 3200mhz.



I hope you buy an aftermarket cooler and OC that 1700 because there is a very noticeable increase in performance. My 1700 turbos to 3.74ghz stock and running it at 3.924ghz beats that performance easily. Its single thread performance is similar to a 4790k and its multi thread performance is quite strong. 



I came from an FX8370 @ 5 ghz and with no other changes gained 20fps in games. You are going to be very pleasantly surprised.


----------



## kignt

LTC said:


> I have had no luck getting my 16GB kit of G-Skill F4-3600C17-8GVK running at 3200Mhz 14-14-14-14-30. These are "safe" values from the DRAM calculator, but no matter how much voltage I give (1.35-1.45) they are not stable in memTestPro. SOC voltage is stuck at 1.15V for some reason on the X470 Aorus Ultra Gaming motherboard, so I have no way of lowering that. I'm getting kinda frustrated as it seems easy to hit 3200Mhz with those timings for some people. Any tricks to make this work? I'm using a 2700X if that makes a difference.


What's the Thaiphoon Burner's spd info of the kit?


----------



## LTC

kignt said:


> What's the Thaiphoon Burner's spd info of the kit?


What info do you need precisely?


----------



## kignt

LTC said:


> What info do you need precisely?


Wondering if it's samsung b-die, example (not b-die)


----------



## Vrbaa

Anyone got Hynix MFR running above 3000MHz?


----------



## nick name

Vrbaa said:


> Anyone got Hynix MFR running above 3000MHz?


I don't have the kit anymore, but I had a 3200 Hynix kit that ran up to 3400 with its stock timings. On a ASUS Prime X470 board.


----------



## LTC

kignt said:


> Wondering if it's samsung b-die, example (not b-die)


It does say b-die.


----------



## kazablanka

so after alot of testing and pretty much time of pc usage these are my lower fully stable timings @3600mhz with 1.46v dram


----------



## Vrbaa

nick name said:


> I don't have the kit anymore, but I had a 3200 Hynix kit that ran up to 3400 with its stock timings. On a ASUS Prime X470 board.


Hynix MFR?


----------



## nick name

Vrbaa said:


> Hynix MFR?


Yeah, it was a TridnetZ 3200CL16 kit with 16-18-18 timings.


----------



## Vrbaa

MFR?


----------



## nick name

Vrbaa said:


> MFR?


Yes and more specifically it was a TridentZ kit.


----------



## Vrbaa

nick name said:


> Yes and more specifically it was a TridentZ kit.


Fu.. I can't get 2933MHz using my GSkill Ripjaws IV 3200MHz kit. One of the sticks can go as high as 3200, but other one not higher than 2866MHz. This is my second kit, first one was even worse.. But both kits are working stable on declared speed using Intel platform.


----------



## nick name

Vrbaa said:


> Fu.. I can't get 2933MHz using my GSkill Ripjaws IV 3200MHz kit. One of the sticks can go as high as 3200, but other one not higher than 2866MHz. This is my second kit, first one was even worse.. But both kits are working stable on declared speed using Intel platform.


Are you using the RAM slots that manual instructs to use?


----------



## Vrbaa

nick name said:


> Are you using the RAM slots that manual instructs to use?


Yes. I have Ryzen 2600 and MSI X370 Gaming Pro Carbon and latest bios.


----------



## 1usmus

NightAntilli said:


> I'm now in the process of upgrading my system to Ryzen... I currently have an FX-8320 and the plan is to get an X470 Taichi with an R7 1700 (too good to pass up for under $200).
> 
> Now... I want to get 32 GB for my system, and the plan is to get a 3200MHz CL14 Trident Z kit (most likely this one). I'm not interested in ever upgrading this system to 64GB. So that leaves me with two choices:
> 
> 1) Getting 4 kits of single rank memory (4x8GB)
> 2) Getting 2 kits of dual rank memory (2x16GB)
> 
> The question is... Which one is more likely to give me the best overall performance with the R7 1700? Or in other words, which will provide me the best clocks and timings for all purpose usage?


ASUS CH6 , Asrock Taichi X470 and X370 best motherbords for 4X dimm configurations (no matter the number of ranks)



kazablanka said:


> so after alot of testing and pretty much time of pc usage these are my lower fully stable timings @3600mhz with 1.46v dram


excellent result!
and I see low voltage for SOC, this is a very good solution for improving stability

I'll tell you one secret, the memory controller is able to adjust timings on its own and what the RTC demonstrates is not true, this program reads the “shell” but not real values


----------



## 1usmus

LTC said:


> I have had no luck getting my 16GB kit of G-Skill F4-3600C17-8GVK running at 3200Mhz 14-14-14-14-30. These are "safe" values from the DRAM calculator, but no matter how much voltage I give (1.35-1.45) they are not stable in memTestPro. SOC voltage is stuck at 1.15V for some reason on the X470 Aorus Ultra Gaming motherboard, so I have no way of lowering that. I'm getting kinda frustrated as it seems easy to hit 3200Mhz with those timings for some people. Any tricks to make this work? I'm using a 2700X if that makes a difference.


1) attentiveness (it is a single organism, if you violate the proportions of timings you will not be able to get a stable system)
2) do not use high voltage for SOC, for your frequency of 0.97-0.98 volts should be enough


----------



## kazablanka

1usmus said:


> excellent result!
> and I see low voltage for SOC, this is a very good solution for improving stability
> 
> I'll tell you one secret, the memory controller is able to adjust timings on its own and what the RTC demonstrates is not true, this program reads the “shell” but not real values


Thanks for sharing your knowledge with me  
I am testing and some other settings now with 1.45v dram ,so this means that imc can change the timings that i have set? I think that this may be the reason for no performance improvement after lowering some timings.
I use tm5 to measure the performance every time i lower timings, by the time the test takes to be completed. Is this a good way to measure performance gains ? 3600mhz with auto timings (just docp) takes twice the time to complete the test from 3600Μhz with this timings


----------



## nick name

kazablanka said:


> Thanks for sharing your knowledge with me
> I am testing and some other settings now with 1.45v dram ,so this means that imc can change the timings that i have set? I think that this may be the reason for no performance improvement after lowering some timings.
> I use tm5 to measure the performance every time i lower timings, by the time the test takes to be completed. Is this a good way to measure performance gains ? 3600mhz with auto timings (just docp) takes twice the time to complete the test from 3600Μhz with this timings


I wouldn't use the amount of time it takes. CPU speed might change, but even if you have the CPU speed locked there isn't any way to make certain the test is testing the same amount of RAM each time.


----------



## rul3s

[email protected] 1.10v---BIOS 2.50---HCI---1000%---HOF4CXL1BST4000M19SF162K


----------



## Bruizer

1usmus said:


> 1) attentiveness (it is a single organism, if you violate the proportions of timings you will not be able to get a stable system)
> 2) do not use high voltage for SOC, for your frequency of 0.97-0.98 volts should be enough


 @1usmus I've been tinkering with my G.Skill Flare X 3200 c14 and have managed to get it to 3400 at 1.385v stable with ryzen calc fast timings (trfc 272) with my 2700x set to a -0.1v offset (PBO enabled w/ PE2). But I require 1.075 soc. Any lower and I start getting weird behavior.

Any thoughts on getting the soc lower or is it maybe just the chip lottery?

Edit: Also, I believe I saw something where you said if twr is below 12 you get data loss? Should I bump mine up from 10 to 12?


----------



## kazablanka

nick name said:


> I wouldn't use the amount of time it takes. CPU speed might change, but even if you have the CPU speed locked there isn't any way to make certain the test is testing the same amount of RAM each time.


From my testing cpu speed doesn't affect the time score. I take the same time with pbo and with manual overclock @ 4225mhz. I have change the cfg to always test the same amount of ram


----------



## nick name

kazablanka said:


> From my testing cpu speed doesn't affect the time score. I take the same time with pbo and with manual overclock @ 4225mhz. I have change the cfg to always test the same amount of ram


Can you tell me how to do that? Mine always grabs more RAM as it becomes available after each pass.


----------



## kazablanka

nick name said:


> Can you tell me how to do that? Mine always grabs more RAM as it becomes available after each pass.


You have to play with Reserved Memory for Windows from the MT.cfg to make tm5 grab the same ram amount


----------



## nick name

kazablanka said:


> You have to play with Reserved Memory for Windows from the MT.cfg to make tm5 grab the same ram amount


Bahhh, I want to find a way where you can assign the number of threads to use and RAM for each thread.


----------



## kazablanka

may 1usmus can help you with this


----------



## Vrbaa

Hello,

which values in Bios contribute to the stability of ram memory at higher frequencies? Which voltage options and other parameters in Bios should I change for ram stability?


----------



## nick name

Vrbaa said:


> Hello,
> 
> which values in Bios contribute to the stability of ram memory at higher frequencies? Which voltage options and other parameters in Bios should I change for ram stability?


Have you started exploring the 1usmus DRAM Calculator yet? That's gonna give you a better idea for about what you're asking about.


----------



## Vrbaa

nick name said:


> Have you started exploring the 1usmus DRAM Calculator yet? That's gonna give you a better idea for about what you're asking about.


Of course I'm and it doesn't help unfortunately


----------



## Bruizer

*Currently Stable*

G.Skill Flare X currently stable at 3400 fast presets at 1.385volts. Past mdsched.exe, Testmem5, Memtest64 (9 hours), and haven't had any crashes gaming (Battlefield V), etc.

Not sure whether I'll tighten timings next, go for 3466, or settle. I don't want to go over 1.4v just because. Idle ram temps at 25c, max load at 37c.

The 2700x is PBO with PE2 and voltage offset of -0.1.


----------



## mtrai

TIL and thought I would share here and in the memory thread. AIDA should somehow make this bit more know somehow. But if you right click the start benchmark a hidden menu pops up. Credit to https://www.reddit.com/r/overclocki...y_psa_in_aida64_right_click_the_bench_button/

However I then tried right clicking in the results area and got an additional menu that allows you to change the bench mark order and weather it displays in MB/s or GB/s and there are 3 additional tests. I am not sure what all this really means for testing just yet...but there are changes from one test to another especially in latency.


----------



## Darkomax

Nice didn't know that.


----------



## CJMitsuki

nick name said:


> kazablanka said:
> 
> 
> 
> Thanks for sharing your knowledge with me /forum/images/smilies/biggrin.gif
> I am testing and some other settings now with 1.45v dram ,so this means that imc can change the timings that i have set? I think that this may be the reason for no performance improvement after lowering some timings.
> I use tm5 to measure the performance every time i lower timings, by the time the test takes to be completed. Is this a good way to measure performance gains ? 3600mhz with auto timings (just docp) takes twice the time to complete the test from 3600Μhz with this timings
> 
> 
> 
> I wouldn't use the amount of time it takes. CPU speed might change, but even if you have the CPU speed locked there isn't any way to make certain the test is testing the same amount of RAM each time.
Click to expand...

Cpu speed wont change the speed of the test at the same amount of ram used. There is a way to get it to use the same amount of ram most of the time. If you adjust the amount allocated for the OS in the config you can keep it from pulling more ram most of the time. I do however wish you could lock the amount tested as well as having a start button in the test rather than it starting automatically once opened.


----------



## CJMitsuki

Vrbaa said:


> nick name said:
> 
> 
> 
> Have you started exploring the 1usmus DRAM Calculator yet? That's gonna give you a better idea for about what you're asking about.
> 
> 
> 
> Of course I'm and it doesn't help unfortunately
Click to expand...

VttDDR, VppMem, CLDO VDDP, VDDP those can all be adjusted for added stability but not necessarily more stability from more voltage. Your problems could stem from a bad IMC silicon or just that the dies in the kit you have dont play well with Ryzen. If it isnt HQ Samsung BDie or Hynix CJR its likely to be “hit or miss” on a good OC. Also, LLC settings can play a role in stability so lowering the switching frequency can help as well as enabling Spread Spectrum but oddly enough at very high frequencies higher cpu frequencies or rather higher baseclocks can help stabilize the setup. Possibly from the added OC on the IMC? Not positive.


----------



## tiagogl

*Looks stable but still crashing on Battlefield 5*

Hello guys . I need little help here. Sometimes I can play hours of game and sometimes crash with 10 minutes. I tested my memory and looks fine, any advice?

This is the error:

Crashing a lot here. Sometimes I can play hours without problem and others crash with few minutes!
Nome do aplicativo com falha: bfv.exe, versão: 1.0.69.20852, carimbo de data/hora: 0x5c487dbc
Nome do módulo com falha: d3d12.dll, versão: 10.0.17763.168, carimbo de data/hora: 0xb19854df
Código de exceção: 0xc0000005
Deslocamento da falha: 0x0000000000079f0c
ID do processo com falha: 0x9f0
Hora de início do aplicativo com falha: 0x01d4c1621b57d493
Caminho do aplicativo com falha: C:\Program Files (x86)\Origin Games\Battlefield V\bfv.exe
Caminho do módulo com falha: C:\Windows\SYSTEM32\d3d12.dll
ID do Relatório: e215a678-5df2-4958-b00a-5dd5704e83d2
Nome completo do pacote com falha:
ID do aplicativo relativo ao pacote com falha:

Happens with DX11 too, Just play in DX12 because frametime is better!


----------



## BLUuuE

*HMA81GU6AFR8N-UH Final OC*

My daily overclock with tight subtimings.



Spoiler















2 x HMA81GU6AFR8N-UH
B450 Tomahawk
1.0125v SOC, Mode 3 LLC
1.420v DRAM

Can anyone set tRTP to 14? I can set any value below 14, but for some reason setting 14 in BIOS results in 13 in Windows and BIOS. No bootloops or anything. Boots perfectly fine.


----------



## nick name

BLUuuE said:


> My daily overclock with tight subtimings.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 2 x HMA81GU6AFR8N-UH
> B450 Tomahawk
> 1.0125v SOC, Mode 3 LLC
> 1.420v DRAM
> 
> Can anyone set tRTP to 14? I can set any value below 14, but for some reason setting 14 in BIOS results in 13 in Windows and BIOS. No bootloops or anything. Boots perfectly fine.


Which memtest is that? 

And I've seen my tRTP setting change itself and I always use a value below 14. It's currently set at 5.


----------



## BLUuuE

nick name said:


> Which memtest is that?
> 
> And I've seen my tRTP setting change itself and I always use a value below 14. It's currently set at 5.


https://github.com/integralfx/MemTestHelper

It's just a launcher for HCI Memtest.

My AFR sticks won't do any lower than the auto values.

3200 has it at 12, 3333 at 13, so I'd assume I'd need it at 14 for 3466, but that's not going to happen.









- MSI Support


----------



## owikh84

DDR4-3533 CL14-15-15-30-1T @ 1.44V | vSOC @ 1.175v

2700X @ 4.2GHz
ROG Crosshair VII Hero-WiFi 
Trident Z RGB DDR4-4266 CL19 2x8GB


----------



## tiagogl

tiagogl said:


> Hello guys . I need little help here. Sometimes I can play hours of game and sometimes crash with 10 minutes. I tested my memory and looks fine, any advice?
> 
> This is the error:
> 
> Crashing a lot here. Sometimes I can play hours without problem and others crash with few minutes!
> Nome do aplicativo com falha: bfv.exe, versão: 1.0.69.20852, carimbo de data/hora: 0x5c487dbc
> Nome do módulo com falha: d3d12.dll, versão: 10.0.17763.168, carimbo de data/hora: 0xb19854df
> Código de exceção: 0xc0000005
> Deslocamento da falha: 0x0000000000079f0c
> ID do processo com falha: 0x9f0
> Hora de início do aplicativo com falha: 0x01d4c1621b57d493
> Caminho do aplicativo com falha: C:\Program Files (x86)\Origin Games\Battlefield V\bfv.exe
> Caminho do módulo com falha: C:\Windows\SYSTEM32\d3d12.dll
> ID do Relatório: e215a678-5df2-4958-b00a-5dd5704e83d2
> Nome completo do pacote com falha:
> ID do aplicativo relativo ao pacote com falha:
> 
> Happens with DX11 too, Just play in DX12 because frametime is better!


After reset my PC sometimes it's stable other times I run the same test and I got errors . I don't know what do anymore, it's crashing with other games too. I'm not changing the values and after this huge test the memory should be stable! I'm using 1.375 in the memory volts.


1usmus said:


> can you help me?


----------



## nick name

BLUuuE said:


> https://github.com/integralfx/MemTestHelper
> 
> It's just a launcher for HCI Memtest.
> 
> My AFR sticks won't do any lower than the auto values.
> 
> 3200 has it at 12, 3333 at 13, so I'd assume I'd need it at 14 for 3466, but that's not going to happen.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> - MSI Support


Sweet. I paid for Pro because it was supposed to allow for spawning multiple test windows, but never found any support for actually activating that functionality. That kinda irked me.


----------



## Hequaqua

nick name said:


> Sweet. I paid for Pro because it was supposed to allow for spawning multiple test windows, but never found any support for actually activating that functionality. That kinda irked me.


I use this powershell with the pro version. Works well for me.

View attachment Test.zip


You will need to change the settings for the number of threads and memory amount.

I just put it in the same folder as the test. Right click it then tell it to run with Power Shell. It should look like this:



Spoiler


----------



## BLUuuE

nick name said:


> Sweet. I paid for Pro because it was supposed to allow for spawning multiple test windows, but never found any support for actually activating that functionality. That kinda irked me.


You're welcome. Let me know if you want anything added/fixed.


----------



## nick name

BLUuuE said:


> You're welcome. Let me know if you want anything added/fixed.


Oh snap! It's yours? Bravo, sir.


----------



## Cadman597

*Same memory kit*



tiagogl said:


> After reset my PC sometimes it's stable other times I run the same test and I got errors . I don't know what do anymore, it's crashing with other games too. I'm not changing the values and after this huge test the memory should be stable! I'm using 1.375 in the memory volts.


I have the same kit and CPU but on a Crosshair VII. Try my timings maybe?


----------



## The Sandman

tiagogl said:


> After reset my PC sometimes it's stable other times I run the same test and I got errors . I don't know what do anymore, it's crashing with other games too. I'm not changing the values and after this huge test the memory should be stable! I'm using 1.375 in the memory volts.



HCI advises to run test using one instance per thread (16 for us) and for 16GBs you'd run 850MB per instance to equal 90% total memory usage.
With 32GBs you'd double that amount of memory per instance. It sucks you tested that long without proper setup, I feel ya. If I'm missing something here please fill me in.

What else have you tested OC with (not just memory) and for how long?
Is it possible it's not entirely memory always failing? This why I ask about "other" tests/methods you have used to ensure CPU/system stability.

Trust me when I say passing any test at any given OC "one time" is not near enough testing. Ryzen can be a real PITA and will require both hot and cold restarts to ensure stability.
When it comes to testing I'm glad I don't have the need for 32GBs of ram yet, my 16 keeps me busy enough. 

Good luck!


----------



## tiagogl

Cadman597 said:


> I have the same kit and CPU but on a Crosshair VII. Try my timings maybe?



What voltage?


----------



## BLUuuE

So I decided to see how much I could lower SOC voltage while still keeping my RAM stable.
Turns out I could drop it by 0.100v, from 1.025v to 0.925v.



Spoiler















Haven't tested if SOC voltage affects CPU temperatures much, if at all. I'll do it some time later and edit this post with some info.

edit: P95 blend test with 12000MB seems to be freezing 1 minute in... 
Tried increasing SOC and CPU voltage to no avail.
Guess I'll go back to 3400 C16


----------



## Cadman597

*Memory Voltage*



tiagogl said:


> What voltage?


1.37 Volts


----------



## crazycrave

I am testing 3466Mhz on my 1600 not overclocked but the timings had to be loser for FS http://www.3dmark.com/fs/18373775
to make a pass .


----------



## nick name

Out of curiosity -- what are other people's CPU idle temps and RAM temps? I'm not concerned so much with how high or low your CPU idle/RAM temps are, but more the difference between CPU idle and RAM temps. My CPU idle and RAM temps are usually the same.


----------



## dgoc18

MSI X70 GAMING PRO CARBON.

AMD Ryzen 2600 @ 4.0 ghz

G.Skill Sniper X F4-3600C19-8GSXKB (2x8GB single rank) A2, B2 slots.

My setting for bios below.

CPU voltage 1.4
SOC voltage auto 
RAM voltage 1.4
All other settings are auto.

Trick part is that I selected 3333 CL16 then switch to 3533 CL16 that works for me. 

3533 is missing in "Memory Try It !" is magic gem.

This method what I did in bios is really simple.

1. I selected 3333 16-18-18-18-36 under Memory Try It ! in bios then.

2. I selected 3533 under “Dram Frequency” then save bios and exit.

Running 3533 16-18-18-18-36 stable.

Benchmark, Gaming, others works fine.

Do you happen have same ram kit but similar and MSI motherboard ? You can try this method to see if it’s works for you.

See the pic below.


----------



## nick name

dgoc18 said:


> MSI X70 GAMING PRO CARBON.
> 
> AMD Ryzen 2600 @ 4.0 ghz
> 
> G.Skill Sniper X F4-3600C19-8GSXKB (2x8GB single rank) A2, B2 slots.
> 
> My setting for bios below.
> 
> CPU voltage 1.4
> SOC voltage auto
> RAM voltage 1.4
> All other settings are auto.
> 
> Trick part is that I selected 3333 CL16 then switch to 3533 CL16 that works for me.
> 
> 3533 is missing in "Memory Try It !" is magic gem.
> 
> This method what I did in bios is really simple.
> 
> 1. I selected 3333 16-18-18-18-36 under Memory Try It ! in bios then.
> 
> 2. I selected 3533 under “Dram Frequency” then save bios and exit.
> 
> Running 3533 16-18-18-18-36 stable.
> 
> Benchmark, Gaming, others works fine.
> 
> Do you happen have same ram kit but similar and MSI motherboard ? You can try this method to see if it’s works for you.
> 
> See the pic below.



I'd look to lower SOC to anything below 1.1V as I don't see any stability gained that high and more frequently the opposite. I used to recommend 1.1V as a catchall, but have found that because of either my own previous misunderstanding or AGESA updates it isn't nearly necessary. At this point I've found 1.0V to be perfectly sufficient and absolutely stable. 

I'd also start work on lowering your tRFC. The motherboard frequently sets it too high for stability and hopefully that is your case and you can successfully lower it.


----------



## dgoc18

@nick name

I just lower soc to 1.1 and I set 462 for trfc as you suggested.

I used RTC to look at trfc number for safe present.

Update the result score below.

Thanks for tip.:thumb:


----------



## nick name

dgoc18 said:


> @nick name
> 
> I just lower soc to 1.1 and I set 462 for trfc as you suggested.
> 
> I used RTC to look at trfc number for safe present.
> 
> Update the result score below.
> 
> Thanks for tip.:thumb:


No, problem. I'd try SOC at 1.0V and run a quick test. It will be obvious real quick if that's severely unstable. And if it is only close to stable then it's a good sign you can use less SOC which means less voltage through the CPU and that's always a plus.


----------



## Nick Moiré

as you see from my configs,

For 8GBx2 :: ProcODT, RttNom, RttWr and RttPark, they're the same value for bus 3200-3600

For 8GBx4 :: RttNom, RttWr and RttPark, need a proper value to boot up otherwise it will cause 3 bios beep or ClearCMOS.

So, my question... 

1.Why 4 sticks of RAM need Rtt values ?

2.How's Rtt relate to each other(Nom/Wr/Park) ?

THANKS.


----------



## BLUuuE

*Hynix CJR OC*

Got myself some Hynix CJR (2 x F4-3600C19-8GVRB)

1.45v DRAM, 1.025v SOC



Spoiler















I can boot 3733MHz and run AIDA64 memory benchmark, but not much else. Limited by my IMC.



Spoiler















Pretty impressive.


----------



## nick name

Did anyone else know that with Samsung b-die you can drop tRCDWR to as low as 8 and maintain stability? I just learned that from a Buildzoid video.


----------



## Saiger0

nick name said:


> Did anyone else know that with Samsung b-die you can drop tRCDWR to as low as 8 and maintain stability? I just learned that from a Buildzoid video.


loweered mine to 8 and it seems stable for me. I only testes wih tm5 though.


----------



## hesee

Saiger0 said:


> loweered mine to 8 and it seems stable for me. I only testes wih tm5 though.


I have been running it with 8 (3200mhz, dual rank) about 1.5 years so far. Works just fine.


----------



## nick name

I asked about it in another thread and 1usmus says that 8 is too low and will be overridden by the memory controller. So what I've done is set it to 12 and that actually seems to behave as expected ie performance gains and stability lost. Also, I'm assuming that 8 was indeed too low as using 14 produced the same results in testing.


----------



## hesee

nick name said:


> I asked about it in another thread and 1usmus says that 8 is too low and will be overridden by the memory controller. So what I've done is set it to 12 and that actually seems to behave as expected ie performance gains and stability lost. Also, I'm assuming that 8 was indeed too low as using 14 produced the same results in testing.


Hmm. I haven't measured it with 2700x, but using value 8 with 1700 and summitridge agesa 1.0.0.6 it produced better results in synthetics than 14.


----------



## 0razor1

*2600 question*

Guys,

I can run my 2600 w/ 3600 CL17 Kingston B-dies at 3.30 GHz no issue, barring showing CL18 in CPU-z (mobo page) despite being CL17 per XMP and manual override.

Voltages:
CPU: 1.40 (this will see some changes since I'm just at 4.1 GHz and I have an incoming 360 rad AIO)
IMC: 1.20 (what's the upper limit?)
Board: MSI x370 titanium (Feb BIOS updated 1.0.0.6 I believe.)

Do advise on how to proceed. The 3600 ran at CL17 with my 6600k with a mild SA boost.


----------



## herericc

0razor1 said:


> Guys,
> 
> I can run my 2600 w/ 3600 CL17 Kingston B-dies at 3.30 GHz no issue, barring showing CL18 in CPU-z (mobo page) despite being CL17 per XMP and manual override.
> 
> Voltages:
> CPU: 1.40 (this will see some changes since I'm just at 4.1 GHz and I have an incoming 360 rad AIO)
> IMC: 1.20 (what's the upper limit?)
> Board: MSI x370 titanium (Feb BIOS updated 1.0.0.6 I believe.)
> 
> Do advise on how to proceed. The 3600 ran at CL17 with my 6600k with a mild SA boost.


From what I understand you're WAY overdoing it on your VSOC... Most people recommend using like 0.9 to 1V TOTAL on the SOC not 1.2V... Try turning it down it might improve your stability. Ryzen+ needs way less voltage on the SOC than Ryzen1.


----------



## tekjunkie28

herericc said:


> From what I understand you're WAY overdoing it on your VSOC... Most people recommend using like 0.9 to 1V TOTAL on the SOC not 1.2V... Try turning it down it might improve your stability. Ryzen+ needs way less voltage on the SOC than Ryzen1.


This isn't probably anything to write home about but I can run 3533 at 14-14-14 with better than XMP timings with a SOC of 0.61 or 0.63. I forget but for my particular processor this is the sweet spot as anything over doesnt do anything and under makes it just slightly unstable. I run 3400 14 14 14 28 with the rest of the timing following the fast or better timings on the calculator. I have been rock solid for months now. 

Sent from my SM-N950U using Tapatalk


----------



## binder87

Hey all. 
So im on the verge of giving up and thought i might give a 16gb kit that i have one last chance before im selling it. I purchased a 2x8gb g.skill trident z f43200c16d16gtzb for a great price. According to what i read its a samsung e-die, dual ranked (even though RTC reads it as single rank. Strange). For the life of me , i can't get it to work at 3200 with T1...only 2. It also has boot holes where itll refuse to post at lower speeds but itll post at 3200 (not stable though). I tried different tweaks according to the ryzen memory calculator...also voltage up to 1.48v. Nothing. I really don't wanna sell this kit, but so far I'm getting better results with my 2666 micron b die kit 😕. Any insight? Ryzen 5 1600, msi b350 gaming plus (yeah, its ****). Not the latest bios, but maybe from 2 months ago


----------



## rdr09

binder87 said:


> Hey all.
> So im on the verge of giving up and thought i might give a 16gb kit that i have one last chance before im selling it. I purchased a 2x8gb g.skill trident z f43200c16d16gtzb for a great price. According to what i read its a samsung e-die, dual ranked (even though RTC reads it as single rank. Strange). For the life of me , i can't get it to work at 3200 with T1...only 2. It also has boot holes where itll refuse to post at lower speeds but itll post at 3200 (not stable though). I tried different tweaks according to the ryzen memory calculator...also voltage up to 1.48v. Nothing. I really don't wanna sell this kit, but so far I'm getting better results with my 2666 micron b die kit 😕. Any insight? Ryzen 5 1600, msi b350 gaming plus (yeah, its ****). Not the latest bios, but maybe from 2 months ago


binder, do yourself a favor and sell that. Get yourself the G.Skill FlareX 3200 Cl14. Once those arrive, sell that 2666.


----------



## binder87

rdr09 said:


> binder87 said:
> 
> 
> 
> Hey all.
> So im on the verge of giving up and thought i might give a 16gb kit that i have one last chance before im selling it. I purchased a 2x8gb g.skill trident z f43200c16d16gtzb for a great price. According to what i read its a samsung e-die, dual ranked (even though RTC reads it as single rank. Strange). For the life of me , i can't get it to work at 3200 with T1...only 2. It also has boot holes where itll refuse to post at lower speeds but itll post at 3200 (not stable though). I tried different tweaks according to the ryzen memory calculator...also voltage up to 1.48v. Nothing. I really don't wanna sell this kit, but so far I'm getting better results with my 2666 micron b die kit 😕. Any insight? Ryzen 5 1600, msi b350 gaming plus (yeah, its ****). Not the latest bios, but maybe from 2 months ago
> 
> 
> 
> binder, do yourself a favor and sell that. Get yourself the G.Skill FlareX 3200 Cl14. Once those arrive, sell that 2666.
Click to expand...

Damn it . Exactly the answer i was afraid off 🤣. I guess there's no other way...god damn it ryzen. If only the samsung b dies weren't expensive af 😕


----------



## rdr09

binder87 said:


> Damn it . Exactly the answer i was afraid off 🤣. I guess there's no other way...god damn it ryzen. If only the samsung b dies weren't expensive af 😕


Sorry mate. I have two sets of 3200 speeds - FlareX and Ripjaws. The Flare is 50$ more but has no drama. Runs at 3200 DOCP in both my B350 and X470 boards. The Ripjaws will but needs the calculator.


----------



## The Sandman

0razor1 said:


> Guys,
> 
> I can run my 2600 w/ 3600 CL17 Kingston B-dies at 3.30 GHz no issue, barring showing CL18 in CPU-z (mobo page) despite being CL17 per XMP and manual override.
> 
> Voltages:
> CPU: 1.40 (this will see some changes since I'm just at 4.1 GHz and I have an incoming 360 rad AIO)
> IMC: 1.20 (what's the upper limit?)
> Board: MSI x370 titanium (Feb BIOS updated 1.0.0.6 I believe.)
> 
> Do advise on how to proceed. The 3600 ran at CL17 with my 6600k with a mild SA boost.



As herericc mentioned first lower Soc (I'd start with 1.0v, maybe less) 1.2v is the recommended max.

Be sure to verify GearDownMode is *Enabled* in Bios to allow use of odd number Cas value. @binder87 this is my everyday with Flare-X.


----------



## binder87

rdr09 said:


> binder87 said:
> 
> 
> 
> Damn it . Exactly the answer i was afraid off 🤣. I guess there's no other way...god damn it ryzen. If only the samsung b dies weren't expensive af 😕
> 
> 
> 
> Sorry mate. I have two sets of 3200 speeds - FlareX and Ripjaws. The Flare is 50$ more but has no drama. Runs at 3200 DOCP in both my B350 and X470 boards. The Ripjaws will but needs the calculator.
Click to expand...

I wish the calculator was my solution. Unfortunately nothing from the suggested tweaks there helps. As soon as i set it to 3200 and 1T, ill get blue screen pretty fast while in windows. Its ok at 2T with obscure timings but its crap. My 2666 micron b die with tight subtimings will beat it performance wise, so its very frustrating. I would settle for 3000ish, but it doesn't even post at 2933-3000ish.


----------



## nick name

The Sandman said:


> As herericc mentioned first lower Soc (I'd start with 1.0v, maybe less) 1.2v is the recommended max.
> 
> Be sure to verify GearDownMode is *Enabled* in Bios to allow use of odd number Cas value. @binder87 this is my everyday with Flare-X.



To clarify: setting GDM to Enabled will allow you to POST if you use an odd numbered CL because the system will simply change it to even if there is any instability with the odd numbered value you input. If you want to try to force an odd numbered CL then you need GDM disabled, but it may not POST.


----------



## binder87

The odd/even cl is not an issue....its just not stable even with even numbered cl . I lost hope.


----------



## 1usmus

I started to format tests in the guide article on DRAM overclocking, it has 27 tests (4 games and synthetics) for each of the *19 presets*. Testing took 5 full working days. The most ambitious that exists on the Internet. This week's article will be on *TechpowerUP* :devil:


----------



## r0l4n

[email protected] 1.135v---BIOS 6401---HCI---1000%--F4-3600C16-8GVK

Asus C6H with The Stilt Safe 3333 profile at 3400.


----------



## nick name

Has anyone tried values similar?


----------



## ilmazzo

1usmus said:


> I started to format tests in the guide article on DRAM overclocking, it has 27 tests (4 games and synthetics) for each of the *19 presets*. Testing took 5 full working days. The most ambitious that exists on the Internet. This week's article will be on *TechpowerUP* :devil:


impressive


----------



## Saiger0

I´m trying to get 3466c14 stable, is it still recommended to NOT use GDM enabled togethr with un-even primary timings?


----------



## nick name

Saiger0 said:


> I´m trying to get 3466c14 stable, is it still recommended to NOT use GDM enabled togethr with un-even primary timings?


Well GDM with odd CAS will usually result in the odd value being increased to an even value.


----------



## tryout1

1usmus said:


> I started to format tests in the guide article on DRAM overclocking, it has 27 tests (4 games and synthetics) for each of the *19 presets*. Testing took 5 full working days. The most ambitious that exists on the Internet. This week's article will be on *TechpowerUP* :devil:


That's quite the feat oh and thx for providing us with great information and tools so far to get our dram running smoothly :thumb:

@rest I tried running tRCDWR at 8 too but there wasn't even one bit of a difference for me than with tRCDWR 14 just for information.


----------



## christoph

Saiger0 said:


> I´m trying to get 3466c14 stable, is it still recommended to NOT use GDM enabled togethr with un-even primary timings?



what Ram voltage? 

I tried the same timings for my ram but was not stable, BUT I think it can gain stability using 1.48v or maybe a little more Ram voltage


----------



## AmaKatsu

Yesterday I read from somewhere that increase tFAW may lower VRAM voltage 

So, I try on my 4 dimm

8GBx4 Hynix CJR
3466 16-22-22-22-42 60 tFAW 34
bandwidth 53k / 53k / 51k / 70.7ns
with 1.40v (lower to 1.38-1.39 cause unstable)

for new setting I just change only tFAW to 40 and use VRAM 1.38v, that's work

bandwidth drop 400-600MB/s each, that acceptable to me 

both setting tested with memtest5 10cycle and GSAT 2hrs.











Sent from my iPhone using Tapatalk


----------



## Saiger0

christoph said:


> what Ram voltage?
> 
> I tried the same timings for my ram but was not stable, BUT I think it can gain stability using 1.48v or maybe a little more Ram voltage


I also have to increase my dream voltage to 1.46 to get it somewhat stable. Problem for me are single late errors which can't be fixed with voltage.


----------



## christoph

Saiger0 said:


> I also have to increase my dream voltage to 1.46 to get it somewhat stable. Problem for me are single late errors which can't be fixed with voltage.



Yeah i think i'm going to test those timings again with 1.47v at bios, later this weekend...


----------



## 1usmus

*AMD Ryzen Memory Tweaking & Overclocking Guide* by me

https://www.techpowerup.com/reviews/AMD/Ryzen_Memory_Tweaking_Overclocking_Guide/


----------



## oile

1usmus said:


> *AMD Ryzen Memory Tweaking & Overclocking Guide* by me
> 
> 
> 
> https://www.techpowerup.com/reviews/AMD/Ryzen_Memory_Tweaking_Overclocking_Guide/


An ASTONISHING work.


----------



## BLUuuE

*Hynix CJR - 3600 CL15*

Got a 2700X with pretty good silicon (4GHz 1.15v, 4.2GHz 1.35v) and it also looks like the IMC is good as well.



Spoiler
























1.45v DRAM, 1.025v SOC.

Can't seem to get the timings down at all, tho I think I'm limited by my mobo (B450 Tomahawk).


----------



## FJSAMA

1usmus said:


> *AMD Ryzen Memory Tweaking & Overclocking Guide* by me
> 
> https://www.techpowerup.com/reviews/AMD/Ryzen_Memory_Tweaking_Overclocking_Guide/
> "I am preparing +1 page on configuring procODT and RTT, in the coming days it will already be"


Ill wait on this page since a cant go higher than 3266 without changing procODT to 60 to be able to boot but it is crazy unstable (bsods and lots of errors no matter if i loosen recomended timings)
Its that or a memhole... 🙄 
Anyway its a shame with a 2nd gen ryzen and 3200c14 bdie...


----------



## nick name

BLUuuE said:


> Got a 2700X with pretty good silicon (4GHz 1.15v, 4.2GHz 1.35v) and it also looks like the IMC is good as well.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 1.45v DRAM, 1.025v SOC.
> 
> Can't seem to get the timings down at all, tho I think I'm limited by my mobo (B450 Tomahawk).


Which RAM kit is that?


----------



## BLUuuE

nick name said:


> Which RAM kit is that?


2 x F4-3600C19-8GVRB


----------



## BLUuuE

*Hynix CJR - 3600 CL16*

Seems like I need some active cooling on my sticks. 1.45v DRAM would fail in under 5 minutes, yet 1.40v will pass RAM Test and GSAT for 1 hr.



Spoiler























1.400v DRAM, 1.025v SOC.


----------



## christoph

BLUuuE said:


> Seems like I need some active cooling on my sticks. 1.45v DRAM would fail in under 5 minutes, yet 1.40v will pass RAM Test and GSAT for 1 hr.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 1.400v DRAM, 1.025v SOC.




what are those timings? 16 - 8 - 18?


----------



## BLUuuE

christoph said:


> what are those timings? 16 - 8 - 18?


Most ICs can run tRCDWR at 8. It doesn't affect stability but I don't know if it helps with performance or not.


----------



## christoph

BLUuuE said:


> Most ICs can run tRCDWR at 8. It doesn't affect stability but I don't know if it helps with performance or not.



really? well I didn't know that


----------



## Saiger0

BLUuuE said:


> Most ICs can run tRCDWR at 8. It doesn't affect stability but I don't know if it helps with performance or not.


According to 1usmus the memory controller will overwrite this value automatically because its too low.

"I have already once explained that such an abnormally low timing is, I repeat, each field has a protection system against "stupid values", but in some versions of the BIOS it is missing. 
BUT the memory controller will independently correct this value to the appropriate one."


----------



## NightAntilli

I've been trying to get my system completely stable. No luck yet... Currently I get occasional errors when testing with HCI memtest. I tuned to the best of my abilities at this point. Any advice is welcome. I'll be happy enough if it runs at 3200CL14 without issues.

Motherboard: Asrock X470 Taichi (bios version 2.00)
CPU: Ryzen 7 1700 @ stock (for now)
Memory: G.Skill 3200CL14 2x16GB, dual rank (F4-3200C14-16GTZ)


----------



## lDevilDriverl

Hi! 
Can anyone help me to get more stable memory settings? I'm already don't know what to do...
Thanks in advance!

AMD Ryzen Memory Tweaking & Overclocking Guide - completed


Also can run aida with 4000 ram speed =)

Ryzen 5 2600X // Alphacool lt360 // ASUS ROG STRIX B450-I GAMING // Hyperx Predator HX441C19PB3K2/16 3600cl14 1.39 // ASRock Radeon™ VII


----------



## Reous

lDevilDriverl said:


> Hi!
> Can anyone help me to get more stable memory settings? I'm already don't know what to do...
> Thanks in advance!
> 
> AMD Ryzen Memory Tweaking & Overclocking Guide - completed
> 
> 
> Also can run aida with 4000 ram speed =)
> 
> Ryzen 5 2600X // Alphacool lt360 // ASUS ROG STRIX B450-I GAMING // Hyperx Predator HX441C19PB3K2/16 3600cl14 1.39 // ASRock Radeon™ VII




@lDevilDriverl Lovely IMC! Already have seen your post on oc.ru some weeks ago. Is 3600C14 the highest stable setting so far?


----------



## lDevilDriverl

@Reous 3600C14 are most easiest setting for my config 24/7 and I like that 3600C14 need only 1.39v. Right now I have not much time for my experiments and also I'm waiting for new m.2 ssd for win10. Want to install win7 on my old ssd and will continue my attempts to get stable 3933\4000. Not sure but it looks that win10 was damaged by all failed attempts=)


----------



## Reous

Tbh i don't think 3933/4000 is possible but i'm curious ...  It depends on what stability tests do you use. I also was able to run TM5 at 3933C16 CJR but other tests crashed immediately.


----------



## BLUuuE

*Hynix CJR - 3933 CL16 (not fully stable)*

I got a B450I to see how far I could push Hynix CJR. Surprisingly, it booted 3933 16-22-22-42 1.45v and I was able to complete an AIDA64 memory benchmark. Upon starting memtest, it BSOD'd.



Spoiler


----------



## The Pook

BLUuuE said:


> I got a B450I to see how far I could push Hynix CJR. Surprisingly, it booted 3933 16-22-22-42 1.45v and I was able to complete an AIDA64 memory benchmark. Upon starting memtest, it BSOD'd.
> 
> 
> 
> Spoiler



dat latency tho


----------



## Keith Myers

Question. Can RAM sticks degrade over time from high voltage? I have been stable on the ASUS C7H 1.4V CL14 3466 Single B-die memory pre-set for the past year. Temps have always been good at less than 35° C. in the well ventilated case. But for the past couple of weeks I have been generating seg faults on both cpu and gpu tasks in an unusual amount. Much more than normal. I reseated the RAM and the gpus and that didn't change the problem of errors. Still was generating an error about every 4 hours. I have 2 other duplicate systems that have not been having any unusual seg fault errors.

So I tried two things, reduced my cpu clock from 4.025 Ghz to 4.0 Ghz and also dropped the RAM down to 3200Mhz CL14 at 1.35V which is XMP stock rating. Seems to have stopped the errors. So I will probably bump the cpu clock back to 4.025Ghz and observe. What I do next is the question regarding the RAM. I am wondering if over time that the 1.4V for the memory is now not sufficient. Is my supposition valid? The RAM sticks have degraded over time and are no longer stable at the previous voltage of 1.4V? Should I add more voltage for the 3466 clock when I attempt again? Or drop back to 3400 or 3333 and accept that the sticks will not work anymore at 3466 Mhz?


----------



## lDevilDriverl

@Reous tm5 1usmus, LinX


----------



## BLUuuE

The Pook said:


> dat latency tho


Well that's what you'd expect from auto timings...


----------



## Reous

*@**lDevilDriverl *I prefer Karhu and Aida64


----------



## lDevilDriverl

@Reous Don't think there is much difference. Any advises about timings, ProcODT ect.?)))


----------



## Reous

*@**lDevilDriverl *I would suggest first to find a stable 3666 or 3733 setting. B-die on this board prefer a ProcODT from 48Ohm. Timings depends on your kit.

This was a try from yesterday:


https://www.overclock.net/forum/members/618378-ldevildriverl.html


----------



## lDevilDriverl

@Reous Would you be so kind as to run some tm5 or linx?=) I'll try your settings today and let you know results. Which dram v you were using?


----------



## lDevilDriverl

@Reous I tested your settings and tm5 got errors. After making a few changes tm5 1usmus was passed(have no time to finish 15 cycles, but I think it's ok). Right now it
s my(thanks to you:thumb best 'stable' results =) additional info on my last screen. dram is on 1.43v.


----------



## lDevilDriverl

@Reous some lags were found during The Division 2 bech, also 3600 shows 'better'(+2fps) results


----------



## NightAntilli

NightAntilli said:


> I've been trying to get my system completely stable. No luck yet... Currently I get occasional errors when testing with HCI memtest. I tuned to the best of my abilities at this point. Any advice is welcome. I'll be happy enough if it runs at 3200CL14 without issues.
> 
> Motherboard: Asrock X470 Taichi (bios version 2.00)
> CPU: Ryzen 7 1700 @ stock (for now)
> Memory: G.Skill 3200CL14 2x16GB, dual rank (F4-3200C14-16GTZ)
> 
> https://www.overclock.net/forum/attachment.php?attachmentid=261506&stc=1&thumb=1&d=1553564195


RAM is a funny thing... The timings above, for some reason, are more unstable than the ones below, yet the ones below are generally tighter, except the tRAS and tRC... Seems like I'm getting close, but still not fully stable... Also adding Taiphoon and Ryzen calc screenshot.


----------



## BLUuuE

Any tips? Pulling my hair out trying to stabilise 3733MHz.



Spoiler























1.4v DRAM, 1.1v SOC

R7 2700X @ 4.1GHz 1.25v
2 x F4-3600C19-8GVRB (Hynix CJR)
Strix B450-I


----------



## nick name

BLUuuE said:


> Any tips? Pulling my hair out trying to stabilise 3733MHz.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 1.4v DRAM, 1.1v SOC
> 
> R7 2700X @ 4.1GHz 1.25v
> 2 x F4-3600C19-8GVRB (Hynix CJR)
> Strix B450-I


On b-die I gave up finding something stable because of the voltage it took to get even close to stable at timings I wasn't entirely thrilled with anyway.


----------



## sideeffect

With ASUS modded 4602 BIOS for the first time I have been able to disable BankGroupSwapAlt and enable BankGroupSwap. In older BIOS it would never set.

Scores were slightly higher in AIDA. Game benchmarks seem the same. Am I right in that this is the optimal configuration for Dual Rank modules or is this pointless to change?

RTC does misread the DIMM Config it is DR.


----------



## Reous

lDevilDriverl said:


> @*Reous* Would you be so kind as to run some tm5 or linx?=) I'll try your settings today and let you know results. Which dram v you were using?





lDevilDriverl said:


> @*Reous* some lags were found during The Division 2 bech, also 3600 shows 'better'(+2fps) results



I have already changed the RAM but i will test it if i have some time. Maybe on sunday.

Less performence is a sign of instability. Have you tried it with more voltage?


----------



## Nighthog

sideeffect said:


> With ASUS modded 4602 BIOS for the first time I have been able to disable BankGroupSwapAlt and enable BankGroupSwap. In older BIOS it would never set.
> 
> Scores were slightly higher in AIDA. Game benchmarks seem the same. Am I right in that this is the optimal configuration for Dual Rank modules or is this pointless to change?
> 
> RTC does misread the DIMM Config it is DR.



I can confirm BankGroupSwapAlt "enabled" is bad for performance on my Biostar board with Agesa 0.0.7.2
Set and use regular BankGroupSwap "enabled" and BankGroupSwapAlt "disabled" 

I use 4x8Gb SR modules.


----------



## lDevilDriverl

Reous said:


> Less performence is a sign of instability. Have you tried it with more voltage?


yes, got overheating and few errors=) I will test this settings later.


----------



## 1usmus

sideeffect said:


> With ASUS modded 4602 BIOS for the first time I have been able to disable BankGroupSwapAlt and enable BankGroupSwap. In older BIOS it would never set.
> 
> Scores were slightly higher in AIDA. Game benchmarks seem the same. Am I right in that this is the optimal configuration for Dual Rank modules or is this pointless to change?
> 
> RTC does misread the DIMM Config it is DR.


I tested 2 * 8 , 2 * 16 , 4 * 8 and unfortunately I did not see the difference in any application (this was when I was preparing the DRAM-guide)
@lDevilDriverl

I think one of the reasons for the jerks - low voltage for soc


----------



## Hale59

This was a quick test to see how much higher i could go on my flares. Not tested for stability.


----------



## BLUuuE

Hi @Reous,

I read your post over at HardwareLuxx forums and I'm trying your long method to find the optimal CAD Bus values. I was wondering how you determined which settings were best. Did you choose the settings that failed at the highest coverage %? Or did you use the settings which resulted in the least errors after testing for a fixed coverage % (say 1000%)? Or did you use another method?

I've tried 50+ combinations and none of them were able to pass 2000% in RAM Test. Best one only made it to 1132%. I tried my best settings again but they failed at 42%, which means it was a fluke. I'm not too sure how to go about this any more if I can't consistently determine which settings are better than others.

If you have any tips that would be greatly appreciated.

Specs:
2700X @ 4.1GHz 1.25v
2 x F4-3600C19-8GVRB (Hynix CJR)
B450-I BIOS 1201
RTC
1.40v DRAM, 1.075v SOC


----------



## Reous

BLUuuE said:


> Did you choose the settings that failed at the highest coverage %?


I have used this method. In best case it doesn't show up any error. If nothing helps your other settings could be wrong. For example:

Too low Vcore? Have you tried lower cpu clock or higher voltage?
Wrong Rtt settings? Have you tried other like off/off/5, off/off/7 or 7/off/5?
Too low timings? If Rtt does not help i would try 16-21-21-21. Maybe also with Auto subtimings.
PowerDownMode is disabled?
What Vdimm voltage do you use?


----------



## rdr09

Hale59 said:


> This was a quick test to see how must higher i could go on my flares. Not tested for stability.



You should be able to get about the same latency or lower with the Flares at 3466 Cl14. I keep mine at 3266 DOCP and gets about 65 in latency. For benching i use 3466 or 3566 speeds.


----------



## BLUuuE

Reous said:


> I have used this method. In best case it doesn't show up any error. If nothing helps your other settings could be wrong. For example:
> 
> Too low Vcore? Have you tried lower cpu clock or higher voltage?
> Wrong Rtt settings? Have you tried other like off/off/5, off/off/7 or 7/off/5?
> Too low timings? If Rtt does not help i would try 16-21-21-21. Maybe also with Auto subtimings.
> PowerDownMode is disabled?
> What Vdimm voltage do you use?


I've dropped my 2700X to 4GHz 1.25v but I don't think it helped.

As suggested, I've tried different Rtt settings.


Spoiler















I tried 48-Disabled-34.3 again and it failed before 100%...

This is what I was getting at in my previous post. I've had the same settings go over 1000% but when I try them again they fail before 100%.

I set all my subtimings back to auto and also tried 16-21-21 but that was a no go as well.

Powerdown mode is disabled.

I've tried 1.45v DRAM voltage but that didn't seem to help either.

I've read that CLDO_VDDP can help with these issues. I'll try playing with it and seeing if it helps or not.

edit:
I think I know what might be causing these issues. I think the RAM is training itself out of stable settings due to all the changes I make. I did a cold reboot and put in settings that would consistently pass 20% in HCI MemTest and they passed 20% again. Before cold rebooting they would BSOD or fail almost instantly.


----------



## lDevilDriverl

@1usmus, thx! i'll try to add more. How do you thinks, SOC 1.15v will be safe for my mobo? As I remember, you told that 1.15 is very high voltage and 1.2 can kill cpu memory controller pretty fast...


----------



## lDevilDriverl

@Hale59, better show as your RTC =) 
and https://www.overclock.net/forum/27577522-post2594.html will be grate to see =)


----------



## Reous

*@BLUuuE*
Are you sure your soc is enough for 3733? Have you tried more?
Also i only do my tests with 20-20-20-20 CAD settings. So if you have time you could repeat your tests


----------



## ilmazzo

Hey guys, what about intel memory latency checker? Anyone using it?


----------



## minal

ilmazzo said:


> Hey guys, what about intel memory latency checker? Anyone using it?


Yes, and it's nice that it's cross-platform. MLC measures ~70ns latency (68-72ns) and 43GB/s for my 2700X with 2x16GB 3200MHz (DOCP) running linux.


----------



## ilmazzo

minal said:


> Yes, and it's nice that it's cross-platform. MLC measures ~70ns latency (68-72ns) and 43GB/s for my 2700X with 2x16GB 3200MHz (DOCP) running linux.


thanks

well, is a little different from aida and seems that has more in-depth functions (it has a parameters list to play with), I will add it to the test suite when I will take the time to re-work my ram oc profile from scratch


----------



## minal

ilmazzo said:


> thanks
> 
> well, is a little different from aida and seems that has more in-depth functions (it has a parameters list to play with), I will add it to the test suite when I will take the time to re-work my ram oc profile from scratch


Yes, MLC and AIDA gives somewhat different measurement results for latency and bandwidth. There's a post with a comparison on the Asus C7H forum.


----------



## nick name

Reous said:


> *@**lDevilDriverl *I would suggest first to find a stable 3666 or 3733 setting. B-die on this board prefer a ProcODT from 48Ohm. Timings depends on your kit.
> 
> This was a try from yesterday:
> 
> 
> https://www.overclock.net/forum/members/618378-ldevildriverl.html


Man, I am not even close to getting this stable.


----------



## lDevilDriverl

@nick name https://www.overclock.net/forum/27913792-post2293.html so it looks stable for me. I'll try 3800 with this https://www.overclock.net/forum/27911592-post2280.html settings later. Don't have much time=\


----------



## ilmazzo

I'm doing again a new setup for my 3200 bdie

This one is 3466 safe from calculator with gaming profile selected

latency is between high 65 and low 66 which is quite high, I'll manage to validate fast preset asap but for the moment I'm ok in hunt showdown, my favorite game atm which is quite sensitive to ram

[email protected],45v (just to exclude any ram voltage need, then I'll lower) soc 1,03125 and cpu default with xfr enabled but don't remember pbo if on or off


----------



## ilmazzo

Validated 3466 fast (from calculator) after more than 8 hours of TM5 ...... I launched it yesterday night and forgot about it lol

this evening I'll put some proof and some benchmarks (60/61ns latency, now we are talking....)


----------



## rdr09

ilmazzo said:


> Validated 3466 fast (from calculator) after more than 8 hours of TM5 ...... I launched it yesterday night and forgot about it lol
> 
> this evening I'll put some proof and some benchmarks (60/61ns latency, now we are talking....)


Nice. Please post the part no. as well. Although memory stability depends on the motherboard and the imc, imo, memory type matters the most. Thank you.


----------



## lDevilDriverl

@ilmazzo you can set tWR to 12. Also you should run tm5 1usmus with administrator permissions and add swap file(4-8Gb). Without administrator permissions tm5 can't run all tests, some of them will be skipped. You can try 2 or 3 for SCL's and use RTC 1.05. Maybe RTC 1.05 can show that missing ProcODT and others... 30 minutes for 5 cycles is very bad result, looks like something wrong with setups. It can be because of tWR set to 24 instead of 12. tWR shouldn't be such high... My PC spent 50 minutes to run 15 cycles of TM5 1usmus. Also try 288 value or lower for tRFC. Good B-die can work correctly with tRFC(ns) 160 or lower. Try to set tRFC to get tRFC(ns) 160. 
You can check my 3600 setups which I'm using 24\7. Try to get such timing for 3466 and if you pass tm5 1usmus with administrator permissions without errors go for 3600 
Good luck!


----------



## ilmazzo

lDevilDriverl said:


> @ilmazzo you can set tWR to 12. Also you should run tm5 1usmus with administrator permissions and add swap file(4-8Gb). Without administrator permissions tm5 can't run all tests, some of them will be skipped. You can try 2 or 3 for SCL's and use RTC 1.05. Maybe RTC 1.05 can show that missing ProcODT and others... 30 minutes for 5 cycles is very bad result, looks like something wrong with setups. It can be because of tWR set to 24 instead of 12. tWR shouldn't be such high... My PC spent 50 minutes to run 15 cycles of TM5 1usmus. Also try 288 value or lower for tRFC. Good B-die can work correctly with tRFC(ns) 160 or lower. Try to set tRFC to get tRFC(ns) 160.
> You can check my 3600 setups which I'm using 24\7. Try to get such timing for 3466 and if you pass tm5 1usmus with administrator permissions without errors go for 3600
> Good luck!


yup, I did not launched with administrator privileges good find.... I will retry asap

that screen was for the SAFE profile, I will put the one with FAST after validation launched in a proper way ......


----------



## nick name

I've found that having other monitoring apps running will cause RTC to display incorrect values or not display some at all.


----------



## ilmazzo

I usually run bench and tools after having closed everything in background so I did not jumped in this issue so far

I use monitoring when playing or bench after validation



nick name said:


> I've found that having other monitoring apps running will cause RTC to display incorrect values or not display some at all.


----------



## nick name

ilmazzo said:


> I usually run bench and tools after having closed everything in background so I did not jumped in this issue so far
> 
> I use monitoring when playing or bench after validation


What I'm saying is to be aware of in which order you open things. Open RTC before opening other monitoring programs to avoid RTC providing incorrect readings.


----------



## ilmazzo

got it, thanks


----------



## ilmazzo

Well well well

Seems I'm not stable..... I launched with administration privileges TM5 with 1usmus profile and I got 7 errors

The weird think is that hunt showdown had no issue at all, while the other times if I failed the tm5 test it would bring the game to crash in a short time....ok, so let's go back to the flow chart and try to stabilize this profile.....


----------



## lDevilDriverl

Hi, any advise how to make 3800cl14 more stable? Errors appears at the end of cycle tm5 1usmus.(((


----------



## Komora Csaba

Hy.What is yours hynix afr max overclock?(g skill trident z 3200cl16 gtzr)


----------



## Iceman1985

Hey guys, i need some help here. Been trying my new setup and the 3466 fast from calculator is stable. Now i'm trying 3600 fast but it fails after 1000% Karhu.
I have an Asus B450i Strix, 2700X and 2x8gb FlareX.

I cant use more than 1V SOC then it fails much much faster than 1000%. I am using PBO 3 with offset from -0.1 to -0.05, doesnt seem to make any difference.

Would it be better for me to try for 3466 even tighter than fast or going for 3600 fast?


----------



## Reous

Higher RAM Voltage maybe? If this make it worse try following:


ProcODT: 48 Ohm if possible

RttNom: Disabled
All CAD: 20 Ohm


----------



## nick name

Iceman1985 said:


> Hey guys, i need some help here. Been trying my new setup and the 3466 fast from calculator is stable. Now i'm trying 3600 fast but it fails after 1000% Karhu.
> I have an Asus B450i Strix, 2700X and 2x8gb FlareX.
> 
> I cant use more than 1V SOC then it fails much much faster than 1000%. I am using PBO 3 with offset from -0.1 to -0.05, doesnt seem to make any difference.
> 
> Would it be better for me to try for 3466 even tighter than fast or going for 3600 fast?


I've found that the closer I push my RAM to the edge the more sensitive it becomes to temps. Can you try testing while actively cooling your RAM? Or just removing a panel from your case? And what voltage are you running for DRAM?


----------



## Iceman1985

I ran 1,44V and 1,45V. I can try to cool them and try more. I tried cad bus settings around 20 too but i cant even boot with 20 20 20 20 on the last bios. Is there any noticable gains to be made primarily for gaming going for 3600?


----------



## lDevilDriverl

@Iceman1985 
1. Set cpu to 1.35v or lower with auto ratio, llc's to 4.
2. SOC 1.024-1.075 or 1.1 and check temps/errors 
3. try Dram V from 1.39 to 1.45 by +0.01
4. SCLs to 4 or 6 \ try set CADs, RttWR, RttPARK, RttNOM, tRTP, tRDWR to auto


----------



## sotheray

Hi guys, I need some advice.
I'm trying to stabilized CJR kits @3800c16 on my Asus B350i platform.
I have tested and configured some settings necessary for stability, including procODT, RTT, DRAM & SOC Voltage, CAD_BUS, tRDWR & tWRRD, tFAW, tRTP, tRCD and tRP.
Here's some notes. The first part is tuning 3733c16, the second is 3800.

The question is, a 5-cycles TM5 test, or even 50-cycles test, is easy to pass, but there always happens a single error in an 100-cycles TM5 test. This really annoys me, as this kind of single error will sometimes cause blue screen(happened on my x370taichi). 
I'm trying to tune tRFC to fix this problem, will this be effective?


----------



## keenan

Hi guys, hoping someone here has some experience with Micron 8Gbit E-die memory?

I recently bought 2 x 8gb Ballistix Sport LT 3000Mhz (BLS8G4D30AESBK) and they seem to be a good bit of fun to play around with, but I need advice/help/info regarding some timings.

The be precise, the timings I would like to get lower, but just a small change results in a no post are the following..

• TRCDRD (17)
• TRC (56)
• TRFC (500)

Any help would be appreciated.

Attached is my progress so far..


----------



## 1usmus

sotheray said:


> Hi guys, I need some advice.
> I'm trying to stabilized CJR kits @3800c16 on my Asus B350i platform.
> I have tested and configured some settings necessary for stability, including procODT, RTT, DRAM & SOC Voltage, CAD_BUS, tRDWR & tWRRD, tFAW, tRTP, tRCD and tRP.
> Here's some notes. The first part is tuning 3733c16, the second is 3800.
> 
> The question is, a 5-cycles TM5 test, or even 50-cycles test, is easy to pass, but there always happens a single error in an 100-cycles TM5 test. This really annoys me, as this kind of single error will sometimes cause blue screen(happened on my x370taichi).
> I'm trying to tune tRFC to fix this problem, will this be effective?


Hi) I like your notes.
I want to please you, you have already received a phenomenal result. 

1) Try to use tRFC as low as possible, since your remaining timings have tuning. For example 480 or 498.

2) Did you monitor the temperature of the processor / RAM for 100 cycles? LLC enabled for SOC?

3) B350 have insufficiently good screens for CAD (this is one of the key differences from older brothers), that is, the only chance to stabilize the system is the jewelry setting of the CAD



keenan said:


> Hi guys, hoping someone here has some experience with Micron 8Gbit E-die memory?
> 
> I recently bought 2 x 8gb Ballistix Sport LT 3000Mhz (BLS8G4D30AESBK) and they seem to be a good bit of fun to play around with, but I need advice/help/info regarding some timings.
> 
> The be precise, the timings I would like to get lower, but just a small change results in a no post are the following..
> 
> • TRCDRD (17)
> • TRC (56)
> • TRFC (500)
> 
> Any help would be appreciated.
> 
> Attached is my progress so far..


why do you have such low tRRDS, tRCDWR , tRTP , tFAW and too high tWR, tRDWR?
honestly I'm surprised they have stability



Iceman1985 said:


> Hey guys, i need some help here. Been trying my new setup and the 3466 fast from calculator is stable. Now i'm trying 3600 fast but it fails after 1000% Karhu.
> I have an Asus B450i Strix, 2700X and 2x8gb FlareX.
> 
> I cant use more than 1V SOC then it fails much much faster than 1000%. I am using PBO 3 with offset from -0.1 to -0.05, doesnt seem to make any difference.
> 
> Would it be better for me to try for 3466 even tighter than fast or going for 3600 fast?


in your case the SOC will have a “hole” to a certain voltage, try 1.1 volts


----------



## keenan

1usmus said:


> why do you have such low tRRDS, tRCDWR , tRTP , tFAW and too high tWR, tRDWR?
> honestly I'm surprised they have stability


Hi 1usmus, thanks you for the reply.

I used your DRAM Calculator to give a starting point, but in your calculator for Micron E/H the max frequency is 3466Mhz. I stayed with that because anything higher would give errors in memtest.

So, because I couldn't go higher. I just started tightening the timings. Primary timing hold the best latency improvement as far as I know, so I started with tCL, tRCDWR, tRCDRD, tRP, tRAS and tRC.

tRCDWR surprised me the most by going all the way down to 10. Believe me, I checked for errors at 16, 14 and 12 as well.

tRAS was also surprising because it is so much lower even XMP.

As far as the secondary timings, I just started tightening timings to see if they offer any further performance compared to the timings provided by DRAM Calculator.

One question I have, maybe I just missed something. In my bios I have 2 parts for CAD Sub settings.

In the DRAM Calculator it doesn't provide any values for the first part below..

First part is: CAD Sub Timing Configuration. (these are all still on auto)

AddrCmdSetup
CsOdtSetup
CkeSetup

Second part is: CAD Sub Strength Configuration.

ClkDrvStren [20 ohm]
AddrCmdDrvStren [20 ohm]
CsOdtDrvStren [20 ohm]
CkeDrvStren [20 ohm]

What values would work best there?


----------



## nick name

keenan said:


> Hi guys, hoping someone here has some experience with Micron 8Gbit E-die memory?
> 
> I recently bought 2 x 8gb Ballistix Sport LT 3000Mhz (BLS8G4D30AESBK) and they seem to be a good bit of fun to play around with, but I need advice/help/info regarding some timings.
> 
> The be precise, the timings I would like to get lower, but just a small change results in a no post are the following..
> 
> • TRCDRD (17)
> • TRC (56)
> • TRFC (500)
> 
> Any help would be appreciated.
> 
> Attached is my progress so far..


I wanna say I read something from AMD saying tFAW below 12 will bring instability, but I know I read this:
Configured to a minumum 4x tRRD_S, but values >8x tRRD_S are often used for stability.

I got that from:
https://community.amd.com/community/gaming/blog/2017/05/25/community-update-4-lets-talk-dram


----------



## binder87

Hi. Anyone has an idea whats the max safe 24/7 voltage to run a samsung e-die? I see some conflicting reports. Currently at 1.51v, and it scales really well with voltage so far (also when benching at up to 1.6v). I have a 120mm fan blowing on the ram. Tnx .


----------



## lDevilDriverl

3800 passed=)
1.49v


----------



## Reous

*@lDevilDriverl* Nice! CL14 is not possible? CL16 1.49V sounds a bit high compared with your 3733CL14 result.


----------



## lDevilDriverl

@Reous 3800cl14 is pissing me off =) maybe later. set 3800cl16/1.49v with a margin just to pass test. will try lower voltage but later) wright now I wanna go stable 3866cl16/3933cl16-18


----------



## sotheray

1usmus said:


> Hi) I like your notes.
> I want to please you, you have already received a phenomenal result.
> 
> 1) Try to use tRFC as low as possible, since your remaining timings have tuning. For example 480 or 498.
> 
> 2) Did you monitor the temperature of the processor / RAM for 100 cycles? LLC enabled for SOC?
> 
> 3) B350 have insufficiently good screens for CAD (this is one of the key differences from older brothers), that is, the only chance to stabilize the system is the jewelry setting of the CAD



Hi 1usmus thx for your encouragement
1) I have tested a lot of tRFC values, the results are showed below. It seems any value lower than 478 will cause blue screen, so I do not put them in the excel. Unfortunately, still cannot find a fully stable value  the most stable one is 494, no error in 6-hour test but 2 hours later when i saw the screen, it showed a single error

2) I think the temperature is not what limited, because i'm using a bare platform. Also I use a 12cm fan on the memory kit. CPU is stock. SOC LLC Lv3 (b350i have Range of lv1-lv5)

3)So do you think now i should adjust my CAD settings instead of just tune the tRFC? Currently i'm using 24 20 20 20, and I've just tested 4 different settings(see my 1st post, 2nd note).

and btw, an interesting phenomenon: using soc vrm switching frequency 400kHz, 50-cycle no error. change to 500kHz, cannot pass 1-cycle.


----------



## lDevilDriverl

@sotheray stable tRFC values = tRFC (ns) 160 or 240 like safe for b-die. You can use dram calc/Thaiphoon for those


----------



## MacMus

Hi guys,

I have an issue with my Memory kit i purchased for X399 threadripper 1950X on Asus Zenith Extreme Alpha.

My kit is 2x F4-3600C16D-16GTZR.

To begin with booting up with auto detected settings with timings 3600 CL16-16-16-36 1.35V is not possible.

So i used a Ryzen Memory Calculator to find a stable 3200 I did put all my timers, but still getting on test memory5 every few runs some errors.

I'm not sure which timers to tweak to make it more stable ?

https://ibb.co/XW5dZZB

my CPU is now 1.4 V @ 4Ghz. SoC is set to auto and RAM is set 1.36. If i set ram on auto my system does not boot.


----------



## christoph

MacMus said:


> Hi guys,
> 
> I have an issue with my Memory kit i purchased for X399 threadripper 1950X on Asus Zenith Extreme Alpha.
> 
> My kit is 2x F4-3600C16D-16GTZR.
> 
> To begin with booting up with auto detected settings with timings 3600 CL16-16-16-36 1.35V is not possible.
> 
> So i used a Ryzen Memory Calculator to find a stable 3200 I did put all my timers, but still getting on test memory5 every few runs some errors.
> 
> I'm not sure which timers to tweak to make it more stable ?
> 
> https://ibb.co/XW5dZZB
> 
> my CPU is now 1.4 V @ 4Ghz. SoC is set to auto and RAM is set 1.36. If i set ram on auto my system does not boot.




try Power Down Mode Disable and Gear Down Mode in Auto


----------



## MacMus

christoph said:


> try Power Down Mode Disable and Gear Down Mode in Auto


what those settings do ?


----------



## NightAntilli

MacMus said:


> Hi guys,
> 
> I have an issue with my Memory kit i purchased for X399 threadripper 1950X on Asus Zenith Extreme Alpha.
> 
> My kit is 2x F4-3600C16D-16GTZR.
> 
> To begin with booting up with auto detected settings with timings 3600 CL16-16-16-36 1.35V is not possible.
> 
> So i used a Ryzen Memory Calculator to find a stable 3200 I did put all my timers, but still getting on test memory5 every few runs some errors.
> 
> I'm not sure which timers to tweak to make it more stable ?
> 
> https://ibb.co/XW5dZZB
> 
> my CPU is now 1.4 V @ 4Ghz. SoC is set to auto and RAM is set 1.36. If i set ram on auto my system does not boot.


What I did was the following;

1) Set the standard DDR4 frequency (2133 MHz)
2) Load XMP, but maintain 2133 MHz
3) Test the memory at XMP timings and 2133 MHz. It should be stable. Otherwise, you might have faulty memory.
4) If stable at #3, write down all the timings and subtimings (or take picture).
5*) Set the RAM at its rated frequency and rated timings, and manually fill in all the other timings & subtimings you wrote down.
6) Test memory again. If it's stable, you're done. If not, continue to the next step.
7) When #6 fails (it most likely will), compare all timings and subtimings from your current setup to the one from the Ryzen DRAM Calculator (Fast setting).
8) Loosen all timings that are tighter than the calculator fast setting to the value of the calculator. Leave the rest as is.
9) Test again. If it's stable, you're done. If it's not, continue...
10**) Same as step 7 and 8, but for the safe setting instead.
11) Test again. If stable, you're done, if it's not, continue...
12) Try all the changes listed here in order, and retest after each change, until it's stable. 

*In my case XMP was slower than its rated timing. XMP was 15 15 15 36 50 vs 14 14 14 34 48 rated. So I changed those, and wrote down the other timings. 
**I did not reach this step. The RAM was mostly stable compared to the fast setting, causing only very occasional errors. I jumped to step 12 instead, and that made it fully stable.


----------



## sotheray

lDevilDriverl said:


> @sotheray stable tRFC values = tRFC (ns) 160 or 240 like safe for b-die. You can use dram calc/Thaiphoon for those


I'm using CJR, not b-die so unable to copy it. Already tried dram calc values(498 & 496). Thiaphoon... under winPE now so cannot open it, the SSD will arrive 2 days later and i'll have a try at that time.


----------



## MacMus

NightAntilli said:


> What I did was the following;
> 
> 1) Set the standard DDR4 frequency (2133 MHz)
> 2) Load XMP, but maintain 2133 MHz
> 3) Test the memory at XMP timings and 2133 MHz. It should be stable. Otherwise, you might have faulty memory.
> 4) If stable at #3, write down all the timings and subtimings (or take picture).
> 5*) Set the RAM at its rated frequency and rated timings, and manually fill in all the other timings & subtimings you wrote down.
> 6) Test memory again. If it's stable, you're done. If not, continue to the next step.
> 7) When #6 fails (it most likely will), compare all timings and subtimings from your current setup to the one from the Ryzen DRAM Calculator (Fast setting).
> 8) Loosen all timings that are tighter than the calculator fast setting to the value of the calculator. Leave the rest as is.
> 9) Test again. If it's stable, you're done. If it's not, continue...
> 10**) Same as step 7 and 8, but for the safe setting instead.
> 11) Test again. If stable, you're done, if it's not, continue...
> 12) Try all the changes listed here in order, and retest after each change, until it's stable.
> 
> *In my case XMP was slower than its rated timing. XMP was 15 15 15 36 50 vs 14 14 14 34 48 rated. So I changed those, and wrote down the other timings.
> **I did not reach this step. The RAM was mostly stable compared to the fast setting, causing only very occasional errors. I jumped to step 12 instead, and that made it fully stable.


Thanks a lot for this step by step guide. I really appreciate it.

So what you saying is better to play around with timings and keep the rated frenqency ? In nether of your steps i have seen advice to lower frequency. 

Which timing i should be lossing first ? Cause i already know it will now boot at XMP profile i have.


----------



## NightAntilli

MacMus said:


> Thanks a lot for this step by step guide. I really appreciate it.
> 
> So what you saying is better to play around with timings and keep the rated frenqency ? In nether of your steps i have seen advice to lower frequency.
> 
> Which timing i should be lossing first ? Cause i already know it will now boot at XMP profile i have.


If after all these steps you're not getting anywhere, then you can consider lowering your frequency. Also note that the higher your CPU overclock, the more difficult it is to run your memory at higher speeds.

For loosening the timings, use the Ryzen DRAM calculator tool, and see whichever timing you have is faster than the one from the calculator, and loosen those first.


----------



## 1usmus

keenan said:


> Hi 1usmus, thanks you for the reply.
> 
> I used your DRAM Calculator to give a starting point, but in your calculator for Micron E/H the max frequency is 3466Mhz. I stayed with that because anything higher would give errors in memtest.
> 
> So, because I couldn't go higher. I just started tightening the timings. Primary timing hold the best latency improvement as far as I know, so I started with tCL, tRCDWR, tRCDRD, tRP, tRAS and tRC.
> 
> tRCDWR surprised me the most by going all the way down to 10. Believe me, I checked for errors at 16, 14 and 12 as well.
> 
> tRAS was also surprising because it is so much lower even XMP.
> 
> As far as the secondary timings, I just started tightening timings to see if they offer any further performance compared to the timings provided by DRAM Calculator.
> 
> One question I have, maybe I just missed something. In my bios I have 2 parts for CAD Sub settings.
> 
> In the DRAM Calculator it doesn't provide any values for the first part below..
> 
> First part is: CAD Sub Timing Configuration. (these are all still on auto)
> 
> AddrCmdSetup
> CsOdtSetup
> CkeSetup
> 
> Second part is: CAD Sub Strength Configuration.
> 
> ClkDrvStren [20 ohm]
> AddrCmdDrvStren [20 ohm]
> CsOdtDrvStren [20 ohm]
> CkeDrvStren [20 ohm]
> 
> What values would work best there?


Most low secondary timings will not give any advantage. All timings are a single organism, there is harmony in the calculator. 

CAD recommendations will be provided in the next tab of the calculator, but this is the bit mask of the transceiver transceiver, because 0 0 0 will always have the best result. Changes in these parameters may be necessary only in cases of excessive resonance or reflections on signal lines. 


Spoiler














You can find information on how to set them up, but this is absurd.


----------



## 1usmus

sotheray said:


> Hi 1usmus thx for your encouragement
> 1) I have tested a lot of tRFC values, the results are showed below. It seems any value lower than 478 will cause blue screen, so I do not put them in the excel. Unfortunately, still cannot find a fully stable value  the most stable one is 494, no error in 6-hour test but 2 hours later when i saw the screen, it showed a single error
> 
> 2) I think the temperature is not what limited, because i'm using a bare platform. Also I use a 12cm fan on the memory kit. CPU is stock. SOC LLC Lv3 (b350i have Range of lv1-lv5)
> 
> 3)So do you think now i should adjust my CAD settings instead of just tune the tRFC? Currently i'm using 24 20 20 20, and I've just tested 4 different settings(see my 1st post, 2nd note).
> 
> and btw, an interesting phenomenon: using soc vrm switching frequency 400kHz, 50-cycle no error. change to 500kHz, cannot pass 1-cycle.


1) Linx 0.7.0 8gb 15 cycles , please demonstrate this result (494 tRFC)

3) There are 2 types of errors, false and real, in your case, an error can be caused not by CAD_BUS. After changing the tRFC, you should check out 20 20 20 20 and 24 24 24 24

400khz present in the calculator as a recommendation, it's great that you found something like this, now you can be sure that the memory controller is "powered" efficiently



MacMus said:


> Hi guys,
> 
> I have an issue with my Memory kit i purchased for X399 threadripper 1950X on Asus Zenith Extreme Alpha.
> 
> My kit is 2x F4-3600C16D-16GTZR.
> 
> To begin with booting up with auto detected settings with timings 3600 CL16-16-16-36 1.35V is not possible.
> 
> So i used a Ryzen Memory Calculator to find a stable 3200 I did put all my timers, but still getting on test memory5 every few runs some errors.
> 
> I'm not sure which timers to tweak to make it more stable ?
> 
> https://ibb.co/XW5dZZB
> 
> my CPU is now 1.4 V @ 4Ghz. SoC is set to auto and RAM is set 1.36. If i set ram on auto my system does not boot.


special for u 
https://www.overclock.net/forum/27835628-post600.html


----------



## binder87

binder87 said:


> Hi. Anyone has an idea whats the max safe 24/7 voltage to run a samsung e-die? I see some conflicting reports. Currently at 1.51v, and it scales really well with voltage so far (also when benching at up to 1.6v). I have a 120mm fan blowing on the ram. Tnx .


Any insight 😛?


----------



## MacMus

1usmus said:


> special for u
> https://www.overclock.net/forum/27835628-post600.html


thank you!

What about N/A values from screenshots how shall those be set?


----------



## keenan

1usmus said:


> Most low secondary timings will not give any advantage. All timings are a single organism, there is harmony in the calculator.


I definitely trust your calculator..

Some more fun with Micron E-dies 

3600 cl14 @ 1.45v (tRCDRD is a stubborn sucker}


----------



## keenan

binder87 said:


> Any insight 😛?


I would guess the same as B-die. Have you seen this video?


----------



## binder87

keenan said:


> binder87 said:
> 
> 
> 
> Any insight 😛?
> 
> 
> 
> I would guess the same as B-die. Have you seen this video?
Click to expand...

Thanks for the vid! I'm a huge fan of buildzoid. 
Very interesting to watch , but unfortunately doesn't address the "what's the max safe long term samsung E-die voltage". I wonder if 1.6-1.65v can be safe long term.


----------



## 1usmus

keenan said:


> I definitely trust your calculator..
> 
> Some more fun with Micron E-dies
> 
> 3600 cl14 @ 1.45v (tRCDRD is a stubborn sucker}


not bad 
tRFC below can not install? 
can you share configurator(launcher) memtest?




MacMus said:


> thank you!
> 
> What about N/A values from screenshots how shall those be set?


my post has a description for each N/A item


----------



## sotheray

1usmus said:


> 1) Linx 0.7.0 8gb 15 cycles , please demonstrate this result (494 tRFC)
> 
> 3) There are 2 types of errors, false and real, in your case, an error can be caused not by CAD_BUS. After changing the tRFC, you should check out 20 20 20 20 and 24 24 24 24
> 
> 400khz present in the calculator as a recommendation, it's great that you found something like this, now you can be sure that the memory controller is "powered" efficiently


Linx result here:
(tRFC 494, CAD_BUS 24 20 20 20)

btw, I found that tRFC 488 & CAD_BUS 20 20 20 20 can pass TM5 100 cycles (520min) with also 1 error, but failed at linx 5th cycle.


----------



## lDevilDriverl

3866 looks stable. I will continue testing


----------



## 1usmus

*TM5 0.12 v3 config*

https://drive.google.com/open?id=17u_88vsjraTDw5_wI6gJY05peEicbBsQ

after the first start of the program, delete the file *cfg.link* otherwise, v3 config will not work



Spoiler















* fixed test crash , when a certain cycle there was a shortage of memory
* 2 new test added
* test number 14 was temporarily removed, because there were few situations in which an error was found there
* special config for HEDT with 4 channel mode


----------



## keenan

1usmus said:


> not bad
> tRFC below can not install?
> can you share configurator(launcher) memtest?


Hi 1usmus,

With 3600Mhz the lowest I can set tRFC is 550, any lower and the system won't post. Is there anything I can do about that or is that just the limit of Micron?

I have managed to tighten tRP, tRC and tRFC from the last run and I think I am happy to stay here... for now 

Just a pity about tRCDRD, tRC and tRFC!

Do you want a screenshot of MemTestHelper.exe settings tab or you want a link to the actual .exe?

I will attach a screenshot.

Here's the link.. https://github.com/integralfx/MemTestHelper/releases/tag/1.9.4


----------



## Reous

*@lDevilDriverl*

Just go for DDR4-4000


----------



## lDevilDriverl

@Reous Do you believe in magic?! =))))))


----------



## binder87

binder87 said:


> keenan said:
> 
> 
> 
> 
> 
> binder87 said:
> 
> 
> 
> Any insight 😛?
> 
> 
> 
> I would guess the same as B-die. Have you seen this video?
> 
> 
> 
> 
> 
> 
> 
> Click to expand...
> 
> Thanks for the vid! I'm a huge fan of buildzoid.
> Very interesting to watch , but unfortunately doesn't address the "what's the max safe long term samsung E-die voltage". I wonder if 1.6-1.65v can be safe long term.
Click to expand...

So i just passed 1 hour of techpowerup memtest 64 with no errors at these (pic) mem speed/timings (ill test for a longer period tonight) . Yeah, i know, gdm is enabled, but its the only way to get this mem module (sammy e-die) to run at these settings with my r5 1600 (if i disable gdm, cant even get remotely close to this, tried all the suggested fixes, only enabling dgm worked). So this is at 1.6v vdimm. Funny enough, the max temp on the dimms during the test was 31c XD . So obviously temp is not an issue. I just wonder if 1.6v will be ok 24/7on my e die...heard some people are doing this with no issues, but im still a bit reluctant. I can do same settings, but cl 14 on 1.5V, but cl12 is so sexy.....
Idk what to do :0 .
I do play competative cs:go at 1080p, so every frame gained is actually important to me.


----------



## Nighthog

keenan said:


> Hi 1usmus,
> 
> With 3600Mhz the lowest I can set tRFC is 550, any lower and the system won't post. Is there anything I can do about that or is that just the limit of Micron?
> 
> I have managed to tighten tRP, tRC and tRFC from the last run and I think I am happy to stay here... for now
> 
> Just a pity about tRCDRD, tRC and tRFC!


I can concur on the limit of tRFC (ns) needs to be around lowest 305-315ns (500+ tRFC range) for Micron E-die.
Been using such a kit for over a year now. Depends on voltage on how low it can go, But 310ns is about the limit they will go.

Sub timings on Micron are not a issue. Just push everything the lowest values BIOS allows. They can handle it with 1.200V stock. Only at high speeds 3600+ do you eventually need to adjust a few of them higher for stability.

I was pushing 3733Mhz on my gigabyte board but changed my motherboard for a Biostar as I had reached the limits the board could do but it wasn't any better, actually worse.
Considering doing a new switch. The Biostar can't boot above 3200Mhz. But it could do lower timings for that speed than the Gigabyte I used.


----------



## lDevilDriverl

@Reous like this but stable?) Any advise?


----------



## Reous

*@lDevilDriverl
*
Yeah something like this  Is this not TM5 stable? More Soc maybe or maybe you are at a point where you have to play with the CAD settings.
Would love to have a good IMC like yours.


----------



## lDevilDriverl

@Reous something goes wrong.... tm5 not stable(((
https://valid.x86.fr/fylry5
but I'm writing this with that timings
CPU locked on x42 during R15 run. can't boot with x44 =(


----------



## Reous

*@lDevilDriverl
*
Looks really good  I think you have to play with your voltages, Rtt and CAD to get this stable. Keep us updated!


----------



## Aretak

Just returned to Ryzen after a stint playing with X79, and man, the 2700X that I had before must have had the worst IMC in the world. It's the only part I sold, so I'm now running the same Crosshair VI, using the same BIOS version with the same memory kit, but with a brand new 2600X. I could never, ever get anything above 3200MHz CL14 stable on the 2700X. It just wouldn't happen, no matter how many hours I spent tweaking timings and voltages and miscellaneous settings. I was somewhat dreading getting back into memory tweaking after my experience with the 2700X. However, I downloaded the calculator, shot for 3466MHz CL14 Fast straight away and it seems to be perfectly stable. Only had time to do up to 400% in HCI Memtest, but I'm not kidding when I say that I never even made 40% at anything above 3200MHz with that 2700X, despite hours of effort. It always threw errors within a minute or two no matter what I tried. This took five minutes and all I did was use the timings from the main page, without getting into all the VDDP voltages and things, which are still on auto. RAM is at 1.41V and SoC at 1.025V - the latter being the only thing I had to change, as the calculator's primary recommendation of 0.9V SoC resulted in a near-instant black screen and reboot when I started the test.

I know 3466MHz CL14 isn't anything to shout about compared to what some of you are doing these days, but I'm just delighted to finally get literally anything over 3200MHz working after banging my head against it for so long with the last chip.


----------



## MacMus

christoph said:


> try Power Down Mode Disable and Gear Down Mode in Auto


that helped to push to 3266, but when i change it to 3333 it makes ridiculous numbers of errors ;-(


----------



## MacMus

binder87 said:


> I do play competative cs:go at 1080p, so every frame gained is actually important to me.


lol! how much fps u have already ?


----------



## MacMus

how do i calculcate this rfc rfc1 rfc2 values ?

time checker only gives first value ;-(


----------



## lDevilDriverl

MacMus said:


> how do i calculcate this rfc rfc1 rfc2 values ?
> 
> time checker only gives first value ;-(


You need only one trfc. Trfc1 and trfc2 can be auto. Try to use ryzen dram calculator 1.4.1


----------



## lDevilDriverl

Reous said:


> *@lDevilDriverl
> *
> Looks really good /forum/images/smilies/smile.gif I think you have to play with your voltages, Rtt and CAD to get this stable. Keep us updated!


Can't change tras trc with 4000. system just won't boot=/


----------



## christoph

MacMus said:


> that helped to push to 3266, but when i change it to 3333 it makes ridiculous numbers of errors ;-(




try these timings with 3200 Mhz first, start with SOC at 1.1v and go up to 1.13, RttNOM 60 and; RttPARK 48 if not then 60

and you can rise the RAM voltage up to 1.4- 1.42v if you go up to 3466Mhz you going to need 1.44v maybe, start with 1.4 at 3333MHz then you'll see what you need, keep an eye on the RAM temperature


----------



## keenan

christoph said:


> MacMus said:
> 
> 
> 
> that helped to push to 3266, but when i change it to 3333 it makes ridiculous numbers of errors ;-(
> 
> 
> 
> 
> 
> try these timings with 3200 Mhz first, start with SOC at 1.1v and go up to 1.13, RttNOM 60 and; RttPARK 48 if not then 60
> 
> and you can rise the RAM voltage up to 1.4- 1.42v if you go up to 3466Mhz you going to need 1.44v maybe, start with 1.4 at 3333MHz then you'll see what you need, keep an eye on the RAM temperature
Click to expand...

What can you use to check memory temps?


----------



## binder87

MacMus said:


> binder87 said:
> 
> 
> 
> I do play competative cs:go at 1080p, so every frame gained is actually important to me.
> 
> 
> 
> lol! how much fps u have already ?
Click to expand...

Depends on the map/conditions. Usually I'm pushing above 200. Since i have a ryzen, which kinda sucks for csgo, I'm trying to maximize everything i can.


----------



## nick name

keenan said:


> What can you use to check memory temps?


If your RAM has the sensors then it will display in HWiNFO.


----------



## binder87

keenan said:


> christoph said:
> 
> 
> 
> 
> 
> MacMus said:
> 
> 
> 
> that helped to push to 3266, but when i change it to 3333 it makes ridiculous numbers of errors ;-(
> 
> 
> 
> 
> 
> try these timings with 3200 Mhz first, start with SOC at 1.1v and go up to 1.13, RttNOM 60 and; RttPARK 48 if not then 60
> 
> and you can rise the RAM voltage up to 1.4- 1.42v if you go up to 3466Mhz you going to need 1.44v maybe, start with 1.4 at 3333MHz then you'll see what you need, keep an eye on the RAM temperature
> 
> Click to expand...
> 
> What can you use to check memory temps?
Click to expand...

Hwinfo64 and only if your mem module has a temp sensor. As a general rule though, ram doesn't really gets hot.


----------



## keenan

nick name said:


> If your RAM has the sensors then it will display in HWiNFO.


Thank you



binder87 said:


> Hwinfo64 and only if your mem module has a temp sensor. As a general rule though, ram doesn't really gets hot.


Thanks, I'm already running mine at 1.45v so I thought if they were still alright then I would try 1.6v to see how they scale..


----------



## christoph

keenan said:


> Thank you
> 
> 
> 
> Thanks, I'm already running mine at 1.45v so I thought if they were still alright then I would try 1.6v to see how they scale..


don't go over 1.5v, it might kill something


----------



## jcpq

I try to get 3600Mhz -Gskill FlareX 3200CL14, with 15-15-15-30.
I did not want to use very high voltages, currently 1.42v in ram


----------



## binder87

christoph said:


> keenan said:
> 
> 
> 
> Thank you
> 
> 
> 
> Thanks, I'm already running mine at 1.45v so I thought if they were still alright then I would try 1.6v to see how they scale..
> 
> 
> 
> don't go over 1.5v, it might kill something
Click to expand...

Thats far from the truth...no need to false scare.
Most overclockers push up to 2.0V into their modules for quick bench runs with only air cooling. Above 1.5 and up to 2.0V is highly unlikely to kill a ddr4 module if its used shortly with ok temps...
Many people run samsung E-dies above 1.5V daily and its fine. Its just that up to 1.5v is what was tested and guaranteed as max safe. it doesn't mean that going above it will kill anything. It depends on how much you go above, type of module, temp, etc. Degradation if anything is more likely to hit before death. 
As a side note, never heard of a ddr4 module getting instakilled from 1.6v shoved into it for a short time.


----------



## christoph

binder87 said:


> Thats far from the truth...no need to false scare.
> Most overclockers push up to 2.0V into their modules for quick bench runs with only air cooling. Above 1.5 and up to 2.0V is highly unlikely to kill a ddr4 module if its used shortly with ok temps...
> Many people run samsung E-dies above 1.5V daily and its fine. Its just that up to 1.5v is what was tested and guaranteed as max safe. it doesn't mean that going above it will kill anything. It depends on how much you go above, type of module, temp, etc. Degradation if anything is more likely to hit before death.
> As a side note, never heard of a ddr4 module getting instakilled from 1.6v shoved into it for a short time.




who said it would be an instakill? but don't let me stop you, go ahead, is your hardware and you can do whatever you want with it


----------



## MacMus

christoph said:


> try these timings with 3200 Mhz first, start with SOC at 1.1v and go up to 1.13, RttNOM 60 and; RttPARK 48 if not then 60
> 
> and you can rise the RAM voltage up to 1.4- 1.42v if you go up to 3466Mhz you going to need 1.44v maybe, start with 1.4 at 3333MHz then you'll see what you need, keep an eye on the RAM temperature


how do i calculate other rfc values ?


----------



## nick name

MacMus said:


> how do i calculate other rfc values ?


Whenever I see a formula for tRFC it is tRC and some multiplier. I see some folks say one multiplier and others use another, but I'm not certain if the multiplier is a must as many folks will input any value until they find instability. I have read that anything below 232 for tRFC is gonna cause instability. I, myself, never go below 242.


----------



## MacMus

christoph said:


> try these timings with 3200 Mhz first, start with SOC at 1.1v and go up to 1.13, RttNOM 60 and; RttPARK 48 if not then 60
> 
> and you can rise the RAM voltage up to 1.4- 1.42v if you go up to 3466Mhz you going to need 1.44v maybe, start with 1.4 at 3333MHz then you'll see what you need, keep an eye on the RAM temperature


i'm able to pull 3333 with SoC 1.1v and 1.4v RttNOM 60 and ,RttPARK 60 and your setting from screenshot.

Rising to 1.13 and imcreasing the RAM voltage to 1.42V did not help ;-(

Futher ideas?


----------



## christoph

MacMus said:


> how do i calculate other rfc values ?


is suppose to be like this one, use 206 for the tRFC 2 and 127 for the tRFC 4


----------



## nick name

christoph said:


> is suppose to be like this one, use 206 for the tRFC 2 and 127 for the tRFC 4


You are supposed to leave those on Auto.


----------



## jcpq

My stable OC Memory
Ryzen 5 [email protected]
Gskill FlareX [email protected]
Asus Rog Strix B450-I
Memory OC is @3600Mhz-C14-14-15-14-28-1T
Dram Voltage is @ 1.44v and SOC is at 1.1125V


----------



## MacMus

i made it stable @ 3400 but i have strange issue.. system when completely shuts down fails to properly come up during POST.
It tries 2-3 times (power off then power on .. etc) eventually It reports it failed to boot due to memory .. I have to go to bios just save the settings and system POST without issues for second time.

After it comes up it spits memory error... so i have to set it back to 3333 and then to 3400 with timing changes.. it's like some settings or voltages during post are different or something.


----------



## christoph

nick name said:


> You are supposed to leave those on Auto.



NO


----------



## christoph

MacMus said:


> i made it stable @ 3400 but i have strange issue.. system when completely shuts down fails to properly come up during POST.
> It tries 2-3 times (power off then power on .. etc) eventually It reports it failed to boot due to memory .. I have to go to bios just save the settings and system POST without issues for second time.
> 
> After it comes up it spits memory error... so i have to set it back to 3333 and then to 3400 with timing changes.. it's like some settings or voltages during post are different or something.



what system do you have? Bios, Mobo, etc


----------



## christoph

MacMus said:


> i'm able to pull 3333 with SoC 1.1v and 1.4v RttNOM 60 and ,RttPARK 60 and your setting from screenshot.
> 
> Rising to 1.13 and imcreasing the RAM voltage to 1.42V did not help ;-(
> 
> Futher ideas?



Oh I forgot, use Power down disable, and Gear down Mode in auto or enabled


----------



## BLUuuE

christoph said:


> NO





The Stilt said:


> tRFC2 or tRFC4 are not used unless the refresh mode is 2x or 4x (which normally never happens). Therefore they can be completely ignored (including the programming rule, i.e. tRFC > tRFC2 > tRFC4).


Yes.


----------



## rdr09

jcpq said:


> My stable OC Memory
> Ryzen 5 [email protected]
> Gskill FlareX [email protected]
> Asus Rog Strix B450-I
> Memory OC is @3600Mhz-C14-14-15-14-28-1T
> Dram Voltage is @ 1.44v and SOC is at 1.1125V


Something odd with your results. A FlareX at 3466 Cl14 gets around 61 in Aida Mem Latency, which is ideal especially if you have a high-end gpu. No need any higher unless some worlkoad requires higher speed.


----------



## christoph

BLUuuE said:


> Yes.


then NO


----------



## 1usmus

christoph said:


> BLUuuE said:
> 
> 
> 
> Yes.
> 
> 
> 
> then NO
Click to expand...

tRFC2 and tRFC4 do not work on Ryzen systems, at the moment they are disabled (decoration) or removed from bios. In the new calculator, I also deleted them


----------



## christoph

1usmus said:


> tRFC2 and tRFC4 do not work on Ryzen systems, at the moment they are disabled (decoration) or removed from bios. In the new calculator, I also deleted them


then NO


----------



## nick name

christoph said:


> then NO


You really gotta admire the dedication.


----------



## keenan

nick name said:


> christoph said:
> 
> 
> 
> then NO
> 
> 
> 
> You really gotta admire the dedication.
Click to expand...



A quick question to anyone that has done some extensive testing, which configuration would be better for real world usage? All are at 1.45v..

3200Mhz 12-15-12-12-21
3466Mhz 14-17-14-10-21
3600Mhz 14-20-14-14-28

??


----------



## christoph

nick name said:


> You really gotta admire the dedication.



is not dedication, we know since the beginning that Ryzen does not use tRFC2 and 4, then what difference does it make to input a value or leave at auto?

the guy said "you should" which is NOT, you CAN leave in Auto as Ryzen does not use those values, but is NOT that you should leave it untouched;

rising RAM voltage beyond 1.5v is something you SHOULDN'T do, you CAN if you don't care about longevity of the hardware


----------



## binder87

keenan said:


> nick name said:
> 
> 
> 
> 
> 
> christoph said:
> 
> 
> 
> then NO
> 
> 
> 
> You really gotta admire the dedication.
> 
> Click to expand...
> 
> /forum/images/smilies/biggrin.gif
> 
> A quick question to anyone that has done some extensive testing, which configuration would be better for real world usage? All are at 1.45v..
> 
> 3200Mhz 12-15-12-12-21
> 3466Mhz 14-17-14-10-21
> 3600Mhz 14-20-14-14-28
> 
> ??
Click to expand...

Run aida 64 memory and cache benchmark for each, and see...
If you do other memory intensive task which is timed, check there as well. Its quiet easy.


----------



## jcpq

rdr09 said:


> Something odd with your results. A FlareX at 3466 Cl14 gets around 61 in Aida Mem Latency, which is ideal especially if you have a high-end gpu. No need any higher unless some worlkoad requires higher speed.


Solved!

I changed performance enhancer from level 2 to auto.


----------



## rdr09

jcpq said:


> Solved!
> 
> I changed performance enhancer from level 2 to auto.


Nice. Can you disable Power and Gear down modes?


----------



## nick name

christoph said:


> is not dedication, we know since the beginning that Ryzen does not use tRFC2 and 4, then what difference does it make to input a value or leave at auto?
> 
> the guy said "you should" which is NOT, you CAN leave in Auto as Ryzen does not use those values, but is NOT that you should leave it untouched;
> 
> rising RAM voltage beyond 1.5v is something you SHOULDN'T do, you CAN if you don't care about longevity of the hardware


Then why the f--k did you bother asking what their values should be?


----------



## nick name

jcpq said:


> Solved!
> 
> I changed performance enhancer from level 2 to auto.


Do you have anything running in the background? 

And latency responds directly to CPU speed so if running Auto gets your more consistent speed then lower latency makes sense.


----------



## jcpq

rdr09 said:


> Nice. Can you disable Power and Gear down modes?


GDM-Enabled
Power GDM - Disabled


----------



## jcpq

nick name said:


> Do you have anything running in the background?
> 
> And latency responds directly to CPU speed so if running Auto gets your more consistent speed then lower latency makes sense.


There was nothing to run in the background.


----------



## rdr09

jcpq said:


> GDM-Enabled
> Power GDM - Disabled


Can you disable GDM and maintain stability?


----------



## MacMus

nick name said:


> Do you have anything running in the background?
> 
> And latency responds directly to CPU speed so if running Auto gets your more consistent speed then lower latency makes sense.


What is performance enchancer?


----------



## MacMus

christoph said:


> what system do you have? Bios, Mobo, etc


I have TR1950X, Asus Zenith Extreme with latest bios, F4-36000C16D-16GTZR 2x16.


----------



## nick name

MacMus said:


> What is performance enchancer?


Performance Enhancer on ASUS boards runs PBO with pre-set settings. PE 1 runs PBO with its minimal settings and PE 2 runs PBO with its maximum settings. Boards with PE 3 and PE 4 run an overclocked PBO.


----------



## christoph

nevermind


----------



## christoph

nick name said:


> Then why the f--k did you bother asking what their values should be?




and when the **** did I ask? ******* idiot


----------



## nick name

christoph said:


> and when the **** did I ask? ******* idiot


You're right. You didn't ask. That's my mistake.


----------



## 1usmus

keenan said:


> A quick question to anyone that has done some extensive testing, which configuration would be better for real world usage? All are at 1.45v..
> 
> 3200Mhz 12-15-12-12-21
> 3466Mhz 14-17-14-10-21
> 3600Mhz 14-20-14-14-28
> 
> ??


This week I will publish a benchmark for RAM, it will give you the answer


----------



## keenan

1usmus said:


> keenan said:
> 
> 
> 
> /forum/images/smilies/biggrin.gif
> 
> A quick question to anyone that has done some extensive testing, which configuration would be better for real world usage? All are at 1.45v..
> 
> 3200Mhz 12-15-12-12-21
> 3466Mhz 14-17-14-10-21
> 3600Mhz 14-20-14-14-28
> 
> ??
> 
> 
> 
> This week I will publish a benchmark for RAM, it will give you the answer /forum/images/smilies/smile.gif
Click to expand...

Thank you Yuri, I will be eagerly waiting for your results 😉

On another note, I have now tried these Micron E-dies at 3600Mhz Cl14 all the way up to 1.6v and I can not get tRCDRD, tRC or tRFC any lower.

I guess this is the main difference between expensive Samsung B-dies and cheap Micron E-dies.


----------



## MacMus

christoph said:


> Oh I forgot, use Power down disable, and Gear down Mode in auto or enabled


that pushed it to 3400. i am afraid to set it up for 3466..

What those two option do ?


----------



## keenan

MacMus said:


> christoph said:
> 
> 
> 
> Oh I forgot, use Power down disable, and Gear down Mode in auto or enabled
> 
> 
> 
> that pushed it to 3400. i am afraid to set it up for 3466..
> 
> What those two option do ?
Click to expand...

PowerDownMode is a power saving feature
GearDownMode is effectively a hybrid command rate of 1.5T.


----------



## nick name

keenan said:


> PowerDownMode is a power saving feature
> GearDownMode is effectively a hybrid command rate of 1.5T.


Someone please correct me if I'm wrong: tCKE doesn't matter unless you have GDM Enabled so if you have it Enabled and still can't find stability with it on and tCKE at 1 then try a value of 6 and if that isn't stable try 9.


----------



## christoph

MacMus said:


> that pushed it to 3400. i am afraid to set it up for 3466..
> 
> What those two option do ?



then probably you gonna need like 1.46v on the RAM, is ok as long you don't go over 1.5v for 24/7


----------



## christoph

nick name said:


> Someone please correct me if I'm wrong: tCKE doesn't matter unless you have GDM Enabled so if you have it Enabled and still can't find stability with it on and tCKE at 1 then try a value of 6 and if that isn't stable try 9.



as the guy above said, Gear down mode is just a 1.5T command rate, if you still have no stability then maybe is the RAM voltage

or maybe is the SOC voltage, some guys got stability only at 1.15v and even beyond that, like 1.17v

but here only you can test and find what's stable


----------



## MacMus

What is safe SoC and Ram voltage ? can i just set it up for 1.45 and forget ?

Thanks a lot so far guys... i though XMP and mobo presets are ok but they are just worthless.. XMP 3200 barly boots the sytem and now i'm setting with manual tweakings on 3400 60ns :O


----------



## christoph

MacMus said:


> What is safe SoC and Ram voltage ? can i just set it up for 1.45 and forget ?
> 
> Thanks a lot so far guys... i though XMP and mobo presets are ok but they are just worthless.. XMP 3200 barly boots the sytem and now i'm setting with manual tweakings on 3400 60ns :O



SOC is up to 1.2v but 1.2v is a lot as nobody use it that high, if you need to keep it that high then probably is something else causing instability, lots of guys need as much as 1.17v and one guy here in OCN needed 1.2v ; and the SOC voltage adds a lot of heat to the CPU so keep an eye there


RAM is up to 1.5v, some guys here need 1.5v to keep the ram stable at high frequency, the RAM does not get so hot actually but lots of people said that keeping the ram below 50 adds stability, you can always set more than 1.5v but it might kill something, specially the RAM, as a long term stability wise solution


----------



## MacMus

christoph said:


> SOC is up to 1.2v but 1.2v is a lot as nobody use it that high, if you need to keep it that high then probably is something else causing instability, lots of guys need as much as 1.17v and one guy here in OCN needed 1.2v ; and the SOC voltage adds a lot of heat to the CPU so keep an eye there
> 
> 
> RAM is up to 1.5v, some guys here need 1.5v to keep the ram stable at high frequency, the RAM does not get so hot actually but lots of people said that keeping the ram below 50 adds stability, you can always set more than 1.5v but it might kill something, specially the RAM, as a long term stability wise solution



is SoC related to ram ?

what about tFAW, tRTP, tRC ?


----------



## christoph

MacMus said:


> is SoC related to ram ?
> 
> what about tFAW, tRTP, tRC ?



yes, SoC controls a few things and one of them in the RAM, at higher RAM frequency you going to need more voltage, but mostly between 1.05 and 1.15 is good enough to stabilize the RAM

and the timings are definitely tied to the RAM frequency you trying to achieve and for that we use the RAM calculator that 1usmus has given us which is the way to go even if is just the starting point when it comes to RAM


----------



## jcpq

Some more tweaks.
Gskill [email protected]


----------



## rdr09

jcpq said:


> Some more tweaks.
> Gskill [email protected]


Nice. Same results. It was my 3533 settings. Just raised it up to 3600.


----------



## Rapidian

What are your voltages (DRAM Voltage) that you are running your Flare-X memory at when running at 3533 MT/s or 3600 MT/s? Curious how mine compares with a Asus Strix B450-I mobo and what temps do you get under memory load?

To achieve 3466, i had to run my DRAM Voltage at 1.425 to be stable, but the SOC Voltage was running lower at 0.95. I'm trying to get stable for 3500 and 3600.


----------



## mtrai

Y'all do realize that the ram latency being under 60 is already impressive. With Zen+ you are not gonna get much better then 57 to 58..unless you are able to push the ram higher then 3800.

Me at my current ram at 3733 58.6 though I have had it at 3800 almost stable. Remember you have to make 100% sure all the correct bios settings are set correctly for latency...as default or auto are not the best settings. The second pic was ran on Nov 17 2018 with an earlier bios. Notice I am still seeing the same latencies though the earlier one had some tighter ram timings.


----------



## jcpq

Rapidian said:


> What are your voltages (DRAM Voltage) that you are running your Flare-X memory at when running at 3533 MT/s or 3600 MT/s? Curious how mine compares with a Asus Strix B450-I mobo and what temps do you get under memory load?
> 
> To achieve 3466, i had to run my DRAM Voltage at 1.425 to be stable, but the SOC Voltage was running lower at 0.95. I'm trying to get stable for 3500 and 3600.


Dram=1.4v
Soc=1.1v
Board=Asus rog strix b450-i


----------



## rdr09

Rapidian said:


> What are your voltages (DRAM Voltage) that you are running your Flare-X memory at when running at 3533 MT/s or 3600 MT/s? Curious how mine compares with a Asus Strix B450-I mobo and what temps do you get under memory load?
> 
> To achieve 3466, i had to run my DRAM Voltage at 1.425 to be stable, but the SOC Voltage was running lower at 0.95. I'm trying to get stable for 3500 and 3600.


I use 3266 docp for daily use. Anything above that are just for benching but i do use games for stability. Settings for 3466 (Fast) and 3600 are exact same except voltage and, of course, speed. If i own a high-end gpu like a 2080, then i'll use 3466.


----------



## ilmazzo

According to TM5 v3 1usmus profile I should be stable at 3466 safe BUT hunt showdown from time to time soft crashes and I'm back to desktop.....

So I think I have to tweak again but would like to test better to avoid losing my hunters while testing, or maybe I should download the test game and try it there.....I should update the calculator anyway and maybe re-export the xml file from typhoon burner since I'm just using the read xmp function but don't know if it catches all the details the calculator needs to be kit ram specific....


----------



## sotheray

@1usmus
Finally run 3800CL16 stable with pbo x10, all limits set to 65535, core offset -0.075V. Passed RunMemtestPro4.0 1000% (based on memtest), Linx0.7.0 8gb 15cycles, TM5 config v3 10cycles (not shown in the pic).
Kingston HyperX Predator RGB 3200C16 kit (CJR).
DRAM Voltage 1.44V, SOC Voltage 1.09375V (in bios setting). Timings are shown in the pic.

I successfully ran this memory stable at CPU default a weeks ago. However, after using pbo to boost the cpu, it became unstable, and took me several days to adjust some settings (including voltages, CAD, even some interleaving settings). Now my opinion is that core voltage & soc voltage are the keys. Other core offset voltage such as -0.1V, -0.05V or even 0V will turn the memory unstable. As well as soc voltage (tested from 1.075V to 1.125V).

update: ***... i restarted the system and re-tested the stability. It seems that sometime the system is stable after restart, but sometime it is not.  what should i do? @1usmus


----------



## nick name

ilmazzo said:


> According to TM5 v3 1usmus profile I should be stable at 3466 safe BUT hunt showdown from time to time soft crashes and I'm back to desktop.....
> 
> So I think I have to tweak again but would like to test better to avoid losing my hunters while testing, or maybe I should download the test game and try it there.....I should update the calculator anyway and maybe re-export the xml file from typhoon burner since I'm just using the read xmp function but don't know if it catches all the details the calculator needs to be kit ram specific....


Have you tried curing it with just a bit more voltage?


----------



## lDevilDriverl

@mtrai GJ! Can you should RTC?


----------



## ilmazzo

nick name said:


> Have you tried curing it with just a bit more voltage?


voltage for drams is already at max for my feelings (1,45v), I can try more soc voltage (1,031 atm) and don't know what else.....2600x is at stock with just pbo on to exclude mutual impact....


----------



## nick name

ilmazzo said:


> voltage for drams is already at max for my feelings (1,45v), I can try more soc voltage (1,031 atm) and don't know what else.....2600x is at stock with just pbo on to exclude mutual impact....


Ahhh, then maybe backing off tFAW and/or tRFC just a touch then.


----------



## ilmazzo

nick name said:


> Ahhh, then maybe backing off tFAW and/or tRFC just a touch then.


i've just updated the calc to 1.4.1 and got slighly different settings to test, we will see


----------



## lDevilDriverl

@mtrai I can't go less than 57.2. What RAM you were using?


----------



## lDevilDriverl

del


----------



## Atomfix

Does anyone know how I can get my latency any lower? I find that 85ns is a little high for my liking.

Ryzen 1700 @ Stock with boost enabled.
G.Skill Trident Z F4-3000C15-8GTZB Hynix M Die @ 1.35V Power Down Mode is Enabled.
SOC @ 1.1V


----------



## ProjectV8

RTC 1.05 is not getting a proper memory reading on this new Gigabyte F30 BIOS.
High latency is according to what is configured on your system.
Rising the cpu clock will lower the latency a bit

I would try:
16-16-16-35

tRRDS 6
tRRDL 8


----------



## rdr09

lDevilDriverl said:


> del


Very nice. You think Ryzen 3000 will allow us to easily reach that low? That's the lowest i've seen from 2000 series.
@Atomix, you can try oc'ing to 3466 Cl 16 Fast and you might be able to get it down to 70. My Ripjaws 3200 Cl16 are same way.


----------



## Atomfix

ProjectV8 said:


> RTC 1.05 is not getting a proper memory reading on this new Gigabyte F30 BIOS.
> High latency is according to what is configured on your system.
> Rising the cpu clock will lower the latency a bit
> 
> I would try:
> 16-16-16-35
> 
> tRRDS 6
> tRRDL 8





rdr09 said:


> Very nice. You think Ryzen 3000 will allow us to easily reach that low? That's the lowest i've seen from 2000 series.
> 
> @Atomix, you can try oc'ing to 3466 Cl 16 Fast and you might be able to get it down to 70. My Ripjaws 3200 Cl16 are same way.


I've managed to get it to boot @3200MHz 16-16-16-35 with TRRDS at 6 and L at 8. But had to increase RAM voltage to 1.37V It's passed 19 loops using TechpowerUP MemTest. A slight increase in Write and Copy. Latency is now at 79

CPU still at stock with Boost on.


----------



## mtrai

lDevilDriverl said:


> @mtrai GJ! Can you should RTC?


Here is RTC at 3830 since I am using 100.8 BCLK It is not entirely stable but getting there. I had a lot going on since Hurricane Michael and my mother-in-law passing away about a week ago and caring for her to work with any of this. I am also using high binned g.skill tident g rgb 4133 CL 19 ram 2 x 8 GB


----------



## lDevilDriverl

@mtrai I'm defiantly need to buy hi-end gskills ram=)
Thinking about something from thous F4-4266C19D-16GTZKW, F4-4400C19D-16GTZKK!
Are you able to turn off GDM?
What dram voltage you are using for 3800cl14 and how hot your ram goes(CPU\RAM benchs, games)?


----------



## AmaKatsu

With AGESA 0.0.7.2, the budget mobo like Asrock AB350M Pro4 seem to breakthrough 3400MHz wall

new bios can run 3600


----------



## mtrai

lDevilDriverl said:


> @mtrai I'm defiantly need to buy hi-end gskills ram=)
> Thinking about something from thous F4-4266C19D-16GTZKW, F4-4400C19D-16GTZKK!
> Are you able to turn off GDM?
> What dram voltage you are using for 3800cl14 and how hot your ram goes(CPU\RAM benchs, games)?


I got the 4133 trident kit CL 19. I run 1.6 volts on the ram. I run GDM on auto and so it uses 1.5 for stability. As far as temps go...I never gets above 36 Celsius


----------



## lDevilDriverl

mtrai said:


> I got the 4133 trident kit CL 19. I run 1.6 volts on the ram. I run GDM on auto and so it uses 1.5 for stability. As far as temps go...I never gets above 36 Celsius


It's too much. My 3800 14 14 15 14 28 42 use 1.46(maybe because of my tRCDRD is 15). try to use 1.4 and add +0.01 each time if the system is not stable.


----------



## ilmazzo

trying 3400 fast

no matter what, 3466 is a no go in games

so I'll try to stabilize this 3400 14 fast and forget about it, first benches are good, got a whopping 7200+ in cpu test of tymespy...have to try cine r15 and r20 and at the end try optimizations suggested in the rc tab


----------



## MacMus

MacMus said:


> i made it stable @ 3400 but i have strange issue.. system when completely shuts down fails to properly come up during POST.
> It tries 2-3 times (power off then power on .. etc) eventually It reports it failed to boot due to memory .. I have to go to bios just save the settings and system POST without issues for second time.
> 
> After it comes up it spits memory error... so i have to set it back to 3333 and then to 3400 with timing changes.. it's like some settings or voltages during post are different or something.



I still see this issue coming back ;-( After i shutdown PC and let it sit for few minutes and turn it on it's booting several times and eventually fails.. i have to go to bios load settings and only then it comes up with 3400 speeds.

What's the problem ?


----------



## christoph

MacMus said:


> I still see this issue coming back ;-( After i shutdown PC and let it sit for few minutes and turn it on it's booting several times and eventually fails.. i have to go to bios load settings and only then it comes up with 3400 speeds.
> 
> What's the problem ?



what MOBO on what BIOS?


----------



## ilmazzo

ilmazzo said:


> trying 3400 fast
> 
> no matter what, 3466 is a no go in games
> 
> so I'll try to stabilize this 3400 14 fast and forget about it, first benches are good, got a whopping 7200+ in cpu test of tymespy...have to try cine r15 and r20 and at the end try optimizations suggested in the rc tab


With the system just started up full of crap (steam, gog, rainmeter, blablablabla) I got a 61ns in aida and a 59,5ns in MLC so I'm on the right path, I played 4-5 hours of XCOM2 with no issue at all while on the previous 3466 safe I had two pc crashes within one hour, I will try TM5 for validation and try Hunt Showdown which is my oc nightmare scenario

Then some optimizations and finally put back the cpu to 4,25 all cores fixed frequency, retest everything together, validate it and then i'll forget about bios and so on.

New 21:9 144hz IPS screen from LG will replace my actual Asus 21:9 and if I'm lucky a used V64 to go away with it will be my 2019 upgrades. Well, my wife will deserve a present too since she'll deliver the second baby uh uh uh


----------



## MacMus

christoph said:


> what MOBO on what BIOS?


Asus Zenith Extreme Alpha.. I changed now to ErP S4+S5 and how it always boots up twice, but i have not seen it fail competently to boot up.

An ideas?


----------



## ilmazzo

Think I'm done with this setup

[email protected],25 1,45V LLC1 , SOC 1,1V
16GB Trident Z bdie [email protected] 14-14-14-28 1T 1,45V

some tests


----------



## christoph

MacMus said:


> Asus Zenith Extreme Alpha.. I changed now to ErP S4+S5 and how it always boots up twice, but i have not seen it fail competently to boot up.
> 
> An ideas?



actually that issue had it many may guys, but it is related to the BIOS, have you check in Asus forum to see what other people did to fix the issue?


----------



## Alex K

Hi! Anybody used this kit for Ryzen build?
https://www.gskill.com/en/product/f4-3200c15d-32gtzr


----------



## lDevilDriverl




----------



## rdr09

ilmazzo said:


> Think I'm done with this setup
> 
> [email protected],25 1,45V LLC1 , SOC 1,1V
> 16GB Trident Z bdie [email protected] 14-14-14-28 1T 1,45V
> 
> some tests


Wow. Good job!


----------



## ilmazzo

rdr09 said:


> Wow. Good job!


thansk dude

but I need some tweaks, hunt showdown crashed one time (soft crash, back to desktop without errors) so I need to figure out this bad scenario...


----------



## Saiger0

ilmazzo said:


> thansk dude
> 
> but I need some tweaks, hunt showdown crashed one time (soft crash, back to desktop without errors) so I need to figure out this bad scenario...


In my experience hunt showdown crashes without error msg are beacuse of unstable ram. 
Besides that I wouldnt be comfortable with anything over 1.4v let alone 1,45v with the highest llc setting..



lDevilDriverl said:


>


this is insane! Can you do a aida64 memory test?


----------



## lDevilDriverl

Saiger0 said:


> lDevilDriverl said:
> 
> 
> 
> /forum/images/smilies/biggrin.gif
> 
> 
> 
> this is insane! Can you do a aida64 memory test?
Click to expand...

My 4000cl14 was better


----------



## Saiger0

lDevilDriverl said:


> My 4000cl14 was better


damn you won the silicone lottery bigtime


----------



## ilmazzo

Saiger0 said:


> In my experience hunt showdown crashes without error msg are beacuse of unstable ram.
> Besides that I wouldnt be comfortable with anything over 1.4v let alone 1,45v with the highest llc setting..


you mean on the cpu? well, temps are in check by a good margin so I won't bother too much, in one or two years will be replaced so.....

yep. hunt s very memory sensitive, i'm stable at TM5 with 1usmus profile and all bench and games except this one....


----------



## mtrai

lDevilDriverl said:


> My 4000cl14 was better


Hmm looking good.


----------



## lDevilDriverl

@mtrai I don't know why but Latency is better on 2700x... 2600x got ~+2-3ns =\ tRC looks too low. is it stable?


----------



## mtrai

lDevilDriverl said:


> @mtrai I don't know why but Latency is better on 2700x... 2600x got ~+2-3ns =\ tRC looks too low. is it stable?


I used to have the TRC lower but it was not stable. However both 40 and 42 for the TRC works for me.


----------



## MacMus

christoph said:


> actually that issue had it many may guys, but it is related to the BIOS, have you check in Asus forum to see what other people did to fix the issue?


i don't get it.. was it on alpha or previous asus zenith extreme ?


----------



## christoph

MacMus said:


> i don't get it.. was it on alpha or previous asus zenith extreme ?


No, it was a bug in the Bios for many different MOBOS and brands, it was a bug between the bios and Ryzen that many brands have fix by now, search in the Asus forum for what you can find about it and how to bypass it


and actually I think there was a video in youtube that explain the issue and how they bypass the whole thing


----------



## MacMus

christoph said:


> No, it was a bug in the Bios for many different MOBOS and brands, it was a bug between the bios and Ryzen that many brands have fix by now, search in the Asus forum for what you can find about it and how to bypass it
> 
> 
> and actually I think there was a video in youtube that explain the issue and how they bypass the whole thing


iam not sure what do u mean by thing ? is this is that power related issue, bios related, Soc, RAM or what ? ;-(

I appreciate some more clues ;-)


----------



## christoph

MacMus said:


> iam not sure what do u mean by thing ? is this is that power related issue, bios related, Soc, RAM or what ? ;-(
> 
> I appreciate some more clues ;-)



it says right there "BIOS"

have you checked in the Asus Forum?


----------



## crakej

I had to RMA my G.Skill 4266 CL19s, and got a full refund (even tho I asked for replacement).

So, i have 250GBP to spend on ram. Shall I get the same again, or does anyone have any recommendations? Was thinking about Predator Platinum 4400s but their XMP profiles use T2. They are b-dies though. I do want ram that I can use for next few years and use their full speed when I update my CPU. Love tinkering so not worried about working out timings etc.


----------



## nick name

crakej said:


> I had to RMA my G.Skill 4266 CL19s, and got a full refund (even tho I asked for replacement).
> 
> So, i have 250GBP to spend on ram. Shall I get the same again, or does anyone have any recommendations? Was thinking about Predator Platinum 4400s but their XMP profiles use T2. They are b-dies though. I do want ram that I can use for next few years and use their full speed when I update my CPU. Love tinkering so not worried about working out timings etc.


I've been curious about the 4000CL17 TridentZ kits.


----------



## crakej

nick name said:


> I've been curious about the 4000CL17 TridentZ kits.


Interesting - hadn't seen those... might be better than the 4266CL19s


----------



## nick name

crakej said:


> Interesting - hadn't seen those... might be better than the 4266CL19s


Those kits cost the same now was what I paid for my 3600C15 kit a while ago.


----------



## crakej

lDevilDriverl said:


>


You're getting all these good timings with your Predators? Just RMAed my 4266CL19s - wondering if I should try these instead! Are they b-dies?

Was looking at these as well, but their XMP profiles are using T2 - Patriot Viper Steel Series 16GB KIT DDR4 4400Mhz CL19 - wondering if I can OC them with T1

Hmmm... maybe it's best to just stick with the 4266s as I know them well....


----------



## lDevilDriverl

@crakej Better buy some G.skill kit like mtrai have. His kit is better.


----------



## crakej

lDevilDriverl said:


> @crakej Better buy some G.skill kit like mtrai have. His kit is better.


Which kit does @mtrai have currently?

I was very impressed by your results though - not seen anyone boot 4000 before


----------



## lDevilDriverl

@crakej I hope 4000 won't be a problem for zen2 =)
https://www.newegg.com/Product/Product.aspx?Item=N82E16820232472
https://www.newegg.com/Product/Product.aspx?Item=N82E16820232621
https://www.newegg.com/Product/Product.aspx?Item=N82E16820232824


----------



## ProjectV8

Hello guys.
What do you think?
Would it be possible to stabilize these modules at 3333Mhz?

I have tried a few times 3333Mhz using the DRAM Calculator but in windows there is always some problem.
The voltage I use at it for 3200Mhz is 1.35v and the default is 1.20.
Remembering that it is also not easy to stabilize the 3266Mhz. There is always some crash in games.


----------



## rdr09

ProjectV8 said:


> Hello guys.
> What do you think?
> Would it be possible to stabilize these modules at 3333Mhz?
> 
> I have tried a few times 3333Mhz using the DRAM Calculator but in windows there is always some problem.
> The voltage I use at it for 3200Mhz is 1.35v and the default is 1.20.
> Remembering that it is also not easy to stabilize the 3266Mhz. There is always some crash in games.


It may not just be the RAM's fault, but the CPU as well. My Ripjaws 3200 CL16 has no problem running 3200 DOCP or even oc to 3466 CL16 with the R7 2700, but with my R5 1600 it only can do 2933 MHz DOCP. Have to use calculator to set 3200 MHz and is hard to make it stable. I gave up.

Try adjusting your SOC voltage.


----------



## ProjectV8

@rdr09
It's very strange that, because before buying this current memory kit, I used these totally stable Kingston Value RAM 2400 CL17 KVR24N17S8 / 8 @ 3333Mhz.
https://www.amazon.com/Kingston-Tec...=Kvr24n17s8/4&qid=1556824946&s=gateway&sr=8-2


I'll take a look at the soc voltage, because I rarely do that. I always leave in AUTO.

It is also my plans to move to the new Ryzen.
Thank you for your support


----------



## Struzzin

@rdr09 
Is your Ripjaws 3200 a M-Die set ?
I have a 1700X and this kit has been horrible. 
I already decided I should get Ryzen 3000 / X570 and new memory. 
Kinda tired of messing with it.


----------



## rdr09

Struzzin20 said:


> @rdr09
> Is your Ripjaws 3200 a M-Die set ?
> I have a 1700X and this kit has been horrible.
> I already decided I should get Ryzen 3000 / X570 and new memory.
> Kinda tired of messing with it.


Yes, it is. It does run 3200 DOCP with the 2700, but now i can't oc the cpu. With the Flares, i can oc it to 4.1GHz. Weird.


EDIT: I put the Ripjaw 3200 CL 16 back to the R5 1600 system and I got it to run at the following settings, game stable:


1. DOCP (Options:AUTO/DOCP Standard/DOCP)

2. 3133 CL16

3. DRAM Voltage 1.37v

4. SOC Voltage 1.17v (Offset +0.083)


Gonna run HCI soon.





ProjectV8 said:


> @rdr09
> It's very strange that, because before buying this current memory kit, I used these totally stable Kingston Value RAM 2400 CL17 KVR24N17S8 / 8 @ 3333Mhz.
> https://www.amazon.com/Kingston-Tec...=Kvr24n17s8/4&qid=1556824946&s=gateway&sr=8-2
> 
> 
> I'll take a look at the soc voltage, because I rarely do that. I always leave in AUTO.
> 
> It is also my plans to move to the new Ryzen.
> Thank you for your support


Just don't go over 1.2V SOC. My 1600 is week 18. I read week 25 and lower might be affected by Segfault. Just speculating that segfault has to do with RAM issue.


----------



## ProjectV8

@rdr09

Very good info. Really had many RMAs involving cpus with segfault problem.
I need to get my cpu off the socket to see which year and week. I bought it in July 2017, but did not write down the batch numbers etc.

I'll try another day 3333mhz by changing the soc and see what happens


----------



## Struzzin

rdr09 said:


> Yes, it is. It does run 3200 DOCP with the 2700, but now i can't oc the cpu. With the Flares, i can oc it to 4.1GHz. Weird.
> 
> Just don't go over 1.2V SOC. My 1600 is week 18. I read week 25 and lower might be affected by Segfault. Just speculating that segfault has to do with RAM issue.


That is strange. 
Is the only way to know the date to look on the top of the CPU ? 
IF you have one from week 25 and lower can you RMA it ?


----------



## rdr09

Struzzin20 said:


> That is strange.
> Is the only way to know the date to look on the top of the CPU ?
> IF you have one from week 25 and lower can you RMA it ?


Yes, that's is the only way. AMD, after you inform them, will send you something to test the cpu. If the test shows a fault, then they'll let you RMA. At least that was what i experienced. However, since i'm currently overseas, they were not able to send me the test. I told them i'll take care of it when i get back to the states.

I've heard of some cases where they just replaced the cpu and the new ones are able to oc better. Not sure about the ram issue. First gen gets higher latency than 2nd gen anyways.


----------



## 1usmus

I’m finally ready to announce the release date of the new version *DRAM Calculator for Ryzen™ 1.5.0* - *7th may* 








*May 7* is the birthday of the new product, the benchmark of the memory subsystem. His name - *MEMbench*. This test package is absolutely free and has no limitations. More information I will publish on news portals on the day of publication


----------



## ProjectV8

@1usmus
you are awesome dude.
Thank you for all the effort and this beautiful work.


----------



## mtrai

crakej said:


> Which kit does @mtrai have currently?
> 
> I was very impressed by your results though - not seen anyone boot 4000 before


 G Skill TridentZ RGB F4-4133C19-8GTZR	8 GB DDR4-4133 DDR4 SDRAM (19-19-19-39 @ 2070 MHz) x2 16GB set.

As far as 4000 I have seen a couple of questionable screenshots of Ryzen running ram right at 4000...I seem to remember the screenshot that comes to mind showing 4005 though was highly unstable...but was s;posedly able to get a Aida mem bench ran and screenshotted.


----------



## 1TM1

After over two years of tinkering with 3200-16 which got as fast as 3302-16 cold-restart-stable on C6H and an easy 3200-16 on Taichi but only 3000-14 on X370-Pro, I am moving to samsung chips. Recent deal on https://www.overclock.net/#/topics/1725394


----------



## 1usmus

*DRAM Calculator for Ryzen v1.5.0 + MEMbench 0.6*
























​
https://www.techpowerup.com/255229/...om/255229/announcing-dram-c…egrated-benchmark
https://www.guru3d.com/news-story/download-dram-calculator-for-ryzen-updated-to-v1-4.html
https://www.hardwareluxx.de/index.p...0-fuer-ryzen-prozessoren-veroeffentlicht.html

special thanks to @slafniyfor helping to create a new product 

in the coming weeks there will be another update with large-scale modifications 

UPD 1:

*Version for those who do not have the start of the program (the request for system information is disabled)*
https://drive.google.com/open?id=1fmPIkMZ4GrJO8onEkUZGMHKgkD7D3osz


----------



## ProjectV8

@1usmus

Thank you.
I'll test now


----------



## minal

Thanks @1usmus Any chance of a linux version?


----------



## Keith Myers

minal said:


> Thanks @1usmus Any chance of a linux version?


This would be most welcome. This new version will not run under WINE like the old 1.4.0 version.


----------



## geoxile

Oh well does Micron E-die compare to Samsung B-die? I have a 2x8 kit of B-die but looking to upgrade to a lower profile set of 2x16 and B-die is still pretty expensive


----------



## Unknownm

trfc2 / trfc4 , what values would these be in Dram calculator ?


----------



## Hequaqua

Unknownm said:


> trfc2 / trfc4 , what values would these be in Dram calculator ?


I'm not 100% sure, but iirc, Ryzen doesn't use those. It might be back in the thread, again, iirc 1usmus stated that. 

Hope this helps.


----------



## Unknownm

Hequaqua said:


> I'm not 100% sure, but iirc, Ryzen doesn't use those. It might be back in the thread, again, iirc 1usmus stated that.
> 
> Hope this helps.


Thank you I will start looking 

REP+


----------



## Nighthog

geoxile said:


> Oh well does Micron E-die compare to Samsung B-die? I have a 2x8 kit of B-die but looking to upgrade to a lower profile set of 2x16 and B-die is still pretty expensive


While Micron E-die is easy to work with stock/XMP and they clock quite decently on speed provided you have the right motherboard with good IMC on the CPU for the higher speeds your good to go with current pricing.

But they aren't performance champions and can't provide the best timings such as Samsung B-die have provided on their best chips and/or on midrange quality ones.

I bought a Micron E-die kit when they first came around in the beginning of 2018 and none had seen them yet. I recall being the first to really test them out. I was kinda exited and giddy when I could run 3600Mhz then 3733Mhz with newest AGESA. But in the end I could not be but a bit disappointed as I consistently saw Samsung B-die produce better results for everyone else thanks to large degree with the better timings they could pull off.

Now I see the priced of RAM has crashed.. these Micron E-die kits can be had for half the price I paid back in 2018. And I have seen they are maybe better binned/refined today as 1usmus has a 2666Mhz kit supposed Micron E-die get better results than my 3466Mhz kits have done.(lower timings possible than I could get)

So they are good "PLUG AND PLAY" kits, they just work. no hassles for you but not the best performers provided the timings they provide which will require tweaking to pull some extra performance out off. But in the end B-die is a better bet I reckon required you might need more work to get them to speed( I have seen countless stories of people not getting what they wanted from their kits, thanks to a larger user base)


----------



## MacMus

Coming here with an issue....


I have Asus Zenith Alpha board and strange RAM behaviour .. When i am testing with usmus memory test everything is fine and I can be using my PC for hours no error.

However one every few boots i get random 1 sec freezes after some time .. and random app/games crashes.. In that moment when i run memory test i have hundreds of errors ;-(

This mostly happens after reset, not after clean power up.

What could be an issue, voltage, some timings going out of sync after some time or what ? Where do you suggest to look ?

MM


----------



## ProjectV8

@MacMus

https://www.overclock.net/forum/27694284-post3363.html


By 1usmus

"Nuances to help you set up your system.

* Do not use too high voltages for SOC and DRAM. The calculator will tell you in which framework you should look for a stable result. Always start debugging the system with these voltages.

* Always use extra cooling for RAM. The less heat, the more stable your system.

* A change to procODT or RTT is required when the system does not start, has a huge number of errors, or a BSOD occurs.

* Single and rare errors can be cured by manually sorting such timings: tFAW (from 16 to 36), by increasing tRRDS by 1 or 2, by changing tRTP (from 8 to 12).

* Single and rare errors can be cured by changing tRDWR (from 6 to 9) and tWRRD (from 1 to 4). Note that timings must be configured in pairs. Example: tRDWR 6 tWRRD 2, tRDWR 6 tWRRD 3, tRDWR 6 tWRRD 4, tRDWR 7 tWRRD 1, and so on.

* Single and rare errors can be cured with the help of the tRFC change, the calculator offers you another alternative tRFC. You can also round the recommended number. tRFC 2/4 is not necessary to configure.

* Improve system stability can Geardown enabled.

* Improve the stability of the system can VDDP, the recommended framework from 855mv to 950mv. Step 15mv.

* Spread spectrum disabled can improve the stability of the system.

* The source of errors can also be Windows, not necessarily a problem in overclocking.

* Regularly update the BIOS. It is recommended to update it with afuefix64, instructions can be found here >> https://www.overclock.net/forum/11-a...correctly.html or ask on the forum (there are special cases and in order to avoid problems it is better to ask).

* Increasing tRCDRD and tRP by 1 can improve stability and reduce memory voltage requirements . "


----------



## 1usmus

*DRAM Calculator for Ryzen™ 1.5.1 + MEMbench 0.7*










Spoiler



*DRAM Calculator*

* Updated Micron E / H die presets (3533 max)
* Debug profile is available only for SAFE presets (in case if do not start the system when using V1 or V2).
* Minor adjustments to calculate Debug profiles.
* Small changes in presets for Samsung b-die.
* Reduced activation time for tooltips for the Main tab.
* Added hint for "Topology".
* Fix crash program due to incorrect saving of user settings.
* For OEM, the frequency limit has been increased to 3533.
* Cosmetic edits in the About tab.
* Added links to German and Ukrainian communities.

*MEMbench*

* Fixed a global error when the application refused to start due to an incorrect request for system information (System info).
* Fixed a bug when starting the RTC degraded the speed of MEMbench.
* Fixed a bug where empty Ram size or Task Scope fields caused system crashes.
* Improved accuracy of results + increase the speed of the benchmark.
* Added an alternative mode Stop at (task mode) - Total. Now he is recomended for benchmark. Of course, you can activate the old Single mode, but the results will be worse.
* Removed the output of information about the speed of the test. This parameter was used to debug MEMbech and is not valuable to users.
* Added pop-up hints for MEMbench.
* A slight change in the color scheme MEMbench. Color graphs vary depending on the mode used. Thanks to this, in the future it will be easier for you to recognize the mode in which the test was done.
* Added system time in System info. Validation time is a prerequisite.
* Added "Max RAM" button. Calculation of the maximum-free ammount of RAM. Ideal for Memtest mode.
* Fixed a bug where the application allowed Memtest to run when there was a shortage of RAM.
* Added button-link to MEMbench results page.



https://www.techpowerup.com/download/ryzen-dram-calculator/
https://www.guru3d.com/files-details/download-ryzen-dram-calculator.html
https://www.computerbase.de/downloads/systemtools/dram-calculator-ryzen/


----------



## Unknownm

Have a couple questions please let me know if BIOS setting matches the dram calculator 

(BIOS) CLDO_VDDP = CLDO_VDDP (DRAM Calculator) [This I know is right]
(BIOS) CLDO VDDP = Debug VDDP (DRAM Calculator)
(BIOS) CPU 1.80V = PLL (DRAM Calculator)
(BIOS) VPP_MEM = VPP (DRAM Calculator)


DRAM Calculator shows CAD_BUS Timings & Drive/Block. I believe my BIOS has 2 different spots for these values:

Advanced\AMD CBS\DDR4 C.O\CAD BUS Configuration

"AddrCMDSetup"
"CsOdtSetup"
"CkeSetup"

"ClkDrvStren"
"AddrCmdDrvStrn"
"CsOdtDrvStren"
"CkeDrvStren"

Ai Tweaker\Dram Timings

"MemAddrCmdSetup"
"MemCsOdtSetup"
"MemCkeSetuo"

"MemCadBusClkDrvStrn"
"MemCadBusAddrCmdDrvStren"
"MemCadBusCsOdtDrvStren"
"MemCadBusCkeDrvStren"

can POST 3600Mhz SAFE but fails prime95 4Hours in with complete restart (no bsod just restart)

If I apply higher voltage , prime95 fails faster
SOC (1.05v to 1.15v)
CLDO_VDDP & CLDO VDDP (950 / 950)

When I turn on the PC the BIOS hangs on DRAM Yellow light. I restart and everything POSTs as well

Edit: having cad bus @ 30-30-40-60 gave me 4h prime instead of 2h


----------



## MacMus

ProjectV8 said:


> @MacMus
> 
> https://www.overclock.net/forum/27694284-post3363.html
> 
> 
> By 1usmus
> 
> "Nuances to help you set up your system.
> 
> * Do not use too high voltages for SOC and DRAM. The calculator will tell you in which framework you should look for a stable result. Always start debugging the system with these voltages.
> 
> Spread spectrum disabled can improve the stability of the system.
> 
> *


This is what i notice ram goes out of wack less often by lower voltage on SOC and DRAM.. with high voltage it goes to **** sometimes on random occasions.
It looks like heat is not a problem, but something else...

I dont' understand this spread spectrum .. is that for CPU or RAM or whut ? Where i can find spread spectrum for RAM?


----------



## SanguineDrone

Hey all, can someone recommend me a 2x16gb ram kit?
I'm building a new workstation mITX based on the 2700x and Asus ROG Strix B450-I.
I'm also trying to stay under $200 for RAM.
Thanks !!


----------



## VPII

SanguineDrone said:


> Hey all, can someone recommend me a 2x16gb ram kit?
> I'm building a new workstation mITX based on the 2700x and Asus ROG Strix B450-I.
> I'm also trying to stay under $200 for RAM.
> Thanks !!



Not sure about pricing in the USA or Europe so please excuse my comment if not in your area. I'd go with the Gskill FlareX stated as AMD Ryzen compatible as it is using the Samsung B-die chips.


----------



## CM_Elite_110

Micron B-die hoping tomorrow is the day that it passes 2000% in HCI memtest @ 3533 MHz. It looked like i was there earlier today, but no, fail at 544% 
Have tried a lot at 3600MHz but something isn't stable when i reach those speeds and i have to set the SOC voltage a bit to high ( 1.18 V) for my liking. The extra voltage actually is pretty significant under full load, i guess there are a lot of transistors that uses this voltage on the chip. However these are my timings and latency at the moment. 
Latest bios for my GA-AB350N-Gaming WIFI is used and i only uped the memory voltage to get it to post, after finding a stable frequency i started tuning the timings a bit. We will see if i "want" to work the down even more after i get this stable...


----------



## SanguineDrone

VPII said:


> Not sure about pricing in the USA or Europe so please excuse my comment if not in your area. I'd go with the Gskill FlareX stated as AMD Ryzen compatible as it is using the Samsung B-die chips.


I've looked at for 2x16gb kits, they only go up to 2933 and CL14 
Not sure if it's worth the huge price premium.


----------



## minal

SanguineDrone said:


> Hey all, can someone recommend me a 2x16gb ram kit?
> I'm building a new workstation mITX based on the 2700x and Asus ROG Strix B450-I.
> I'm also trying to stay under $200 for RAM.
> Thanks !!


It won't be under that budget, but for 2x16GB 3200 CL14, there's the F4-3200C14D-32GTZ : https://www.gskill.com/en/product/f4-3200c14d-32gtz


----------



## CM_Elite_110

SanguineDrone said:


> I've looked at for 2x16gb kits, they only go up to 2933 and CL14
> Not sure if it's worth the huge price premium.


A quick search on Newegg (without CL specified) i find this kit that "1usmus" has recommended lately, and it also has good reviews with Ryzen as well.

https://www.newegg.com/global/se-en/Product/Product.aspx?Item=N82E16820232709 

These are the parameters i used.

https://www.newegg.com/global/se-en...49&IsNodeId=1&bop=And&Order=PRICE&PageSize=36


----------



## Nighthog

Unknownm said:


> can POST 3600Mhz SAFE but fails prime95 4Hours in with complete restart (no bsod just restart)
> 
> If I apply higher voltage , prime95 fails faster
> SOC (1.05v to 1.15v)
> CLDO_VDDP & CLDO VDDP (950 / 950)
> 
> When I turn on the PC the BIOS hangs on DRAM Yellow light. I restart and everything POSTs as well
> 
> Edit: having cad bus @ 30-30-40-60 gave me 4h prime instead of 2h


SoC gets more unstable/diffrent the longer you have it under usage/load. I've noted that it usually requires more voltage at longer runs, if voltage is low on a cold boot it can work for some time but after it's warmed up it will start to require increased voltages to stabilize as it may suddenly start to throw errors/bluescreens after several hours. Let it cool down and if will settle down after a while but it is easier to just increase the voltage instead to push the edge away from occurring. 
procODT and Cad Bus settings have a effect on how stable or fast it can occur. Higher values I've noted usually cause it faster unless they are just a bad/unstable combination. They all play together. 

I can for sure say HEAT! is a big factor on this. Open your chassis put a fan on your RAM or backside of motherboard and you can probably run much longer. 
Something is drifting with it's tolerances and causes issues at longer loads when it heats up. As a point you might even need different CAD BUS settings for a warm system compared to a cold one. (they might error on cold boot but they will work when the system gets hot enough)

Found most of this testing out 3733-->3800Mhz memory speeds. At the edge of insanity.


----------



## Synoxia

Hello. I have been out for a while from OC scene, I'm using a x470 Asus ROG HERO VII and I'm still on 1104 BIOS. Are there any memory improvements with 2103? Any new 2700x overclocking methods? (I used to BCLK)


----------



## nick name

Synoxia said:


> Hello. I have been out for a while from OC scene, I'm using a x470 Asus ROG HERO VII and I'm still on 1104 BIOS. Are there any memory improvements with 2103? Any new 2700x overclocking methods? (I used to BCLK)


You should head over the CH7 forum. There are some differences with 2203. CPU requires less power. PE 3 and PE 4 can be controlled in BIOS by adjusting EDC now (previously only done through Ryzen Master). EDC no longer capped at 168. TDC and PPT seem to be uncapped as well (TDC used to be 114 but haven't found any benefit from the change). I haven't seen any increased memory performance, but others report they have.


----------



## nick name

Nighthog said:


> SoC gets more unstable/diffrent the longer you have it under usage/load. I've noted that it usually requires more voltage at longer runs, if voltage is low on a cold boot it can work for some time but after it's warmed up it will start to require increased voltages to stabilize as it may suddenly start to throw errors/bluescreens after several hours. Let it cool down and if will settle down after a while but it is easier to just increase the voltage instead to push the edge away from occurring.
> procODT and Cad Bus settings have a effect on how stable or fast it can occur. Higher values I've noted usually cause it faster unless they are just a bad/unstable combination. They all play together.
> 
> I can for sure say HEAT! is a big factor on this. Open your chassis put a fan on your RAM or backside of motherboard and you can probably run much longer.
> Something is drifting with it's tolerances and causes issues at longer loads when it heats up. As a point you might even need different CAD BUS settings for a warm system compared to a cold one. (they might error on cold boot but they will work when the system gets hot enough)
> 
> Found most of this testing out 3733-->3800Mhz memory speeds. At the edge of insanity.


That makes sense with SoC as everything needs more power the hotter it gets.

And I have a fan sitting on my GPU in front of my RAM. I'm able to due so because of my AIO so if someone is in the same boat then I'd recommend giving it a try.


----------



## 1TM1

1TM1 said:


> moving to samsung chips. Recent deal on https://www.overclock.net/#/topics/1725394


 received mine, manufactured April 2019, price drop $134 https://m.newegg.com/product/N82E16820232217


----------



## nick name

I never knew you could set tWRWRSC/tWRWRSD and tRDRDSD/tRDRDDD to the same value. Everything I've seen always has them varied by 2. 7/7 5/5 or 6/6 4/4 or 5/5 3/3. But then I looked at the preset on the CH7 for 3466MHz and it's set up as 4/4 4/4.


----------



## sotheray

lDevilDriverl said:


>


 @lDevilDriverl
Hello, may I ask if you use ice or other subzero condition to achieve this 3733cl12 or 4000cl14? These timings are amazing, and put huge pressure on soc @Ambient.


----------



## Unknownm

despite what dram calculator says no way any rec,alt,alt2-3 work. Either NO POST yellow dram light or restart from prime95 after 2-4h with yellow light

I started challenging the common settings, in groups

Clkdrvstr, addcmddrvstr, csodtdrvstr, ckedevstr, 
rttmom-rttpark (rttwr disable) and bus timings
Higher voltages
Lower voltages

skip ahead 7 days of testing, cad bus block drvstr ohms are too low. 3600mhz 60-60-60-60 ohms, 3533mhz 40-40-40-40 ohms. 

Even if 3600mhz fails its shown much more stability. I'm already 50mins into prime95 while 20,24,30 ohm would fail first 10mins

Sent from my SM-G960W using Tapatalk


----------



## ilmazzo

In 1.5.1 which topology should be chisen for a taichi x470? X470 or dual?


----------



## Dezterity

I'm sure this has been asked before, but I can't find it in search and it's a really long thread to look all the pages. 

In the first post there were 16 threads of memtest with 850mb each = 13600mb total memory. If I have a R5 2600 and 16gb ram, should I use 12 threads with 850mb each or the amount necessary to get 13600mb used in total (1133mb)?


----------



## The Sandman

Dezterity said:


> I'm sure this has been asked before, but I can't find it in search and it's a really long thread to look all the pages.
> 
> In the first post there were 16 threads of memtest with 850mb each = 13600mb total memory. If I have a R5 2600 and 16gb ram, should I use 12 threads with 850mb each or the amount necessary to get 13600mb used in total (1133mb)?


Same amount of total memory just divide by 12 instead of 16 (850mbs per is what I use on my 2700x). 
Thread count to match number of instances of MemTest, each instance to run with equal amount.


Welcome to OCN!


----------



## Darkomax

Running at 1.4V, tightened what I could. Tried 3533 and it spits some errors, sometimes after 6000% in RAM test. Disabling Geardown mode is a no-no on this CPU, and it doesn't like tRCDRD at 14.


----------



## ilmazzo

I got the geardown mode on just will bypass some tightened values making it pointless, or am I wrong?


----------



## Darkomax

It overwrites the command rate, even if I don't exactly know how it works. I don't really have a choice, if I disable, I get a crazy amount of errors. My R5 1600 was fine with it disabled.


----------



## crakej

Enabling GearDown can work wonders for OCing ram. Some ram need it enabled, some doesn't

It really doesn't impact performance - one of my fastest profiles runs with geardown on.


----------



## ilmazzo

crakej said:


> Enabling GearDown can work wonders for OCing ram. Some ram need it enabled, some doesn't
> 
> It really doesn't impact performance - one of my fastest profiles runs with geardown on.


Ok, I will give it a try ..... I only care about latency, see if it will in the end be a salvation for the 3400 fast profile I'm trying to stabilize for hunt showdown


----------



## crakej

ilmazzo said:


> Ok, I will give it a try ..... I only care about latency, see if it will in the end be a salvation for the 3400 fast profile I'm trying to stabilize for hunt showdown


I always recommend to people having trouble reaching or passing 3200MTs to enable GearDown. It might not work for everyone, but I think for most it allows higher clocked ram. Worked wonders when I had G.Skill memory.


----------



## NightAntilli

I have it disabled since my modules were more stable at 1T.


----------



## crakej

NightAntilli said:


> I have it disabled since my modules were more stable at 1T.


I've just got new Patriot Steel 4400s - they don't need GearDown enabled so far - I'm running them at 3600CL14 currently. I'm hopeful that when I have problem getting them faster, I'll still have geardown in reserve to push them a bit further. I have booted these at 3866 T1 GearDown off but it wasn't useable. My old G.Skill 4233s had to have it on to get 3200MTs or higher...

Now I have 3600 working well I'm going to try pushing them further


----------



## Reous

crakej said:


> I've just got new Patriot Steel 4400s - they don't need GearDown enabled so far - I'm running them at 3600CL14 currently.



Sounds great. What voltage do they need and can you show a RTC screen?


----------



## nick name

Darkomax said:


> It overwrites the command rate, even if I don't exactly know how it works. I don't really have a choice, if I disable, I get a crazy amount of errors. My R5 1600 was fine with it disabled.


You could try tCKE at lower values next since you're using GDM. Try going to 6 and if that works well then try 1.


----------



## Darkomax

Zen 2 is promising, some boards are rated for 4400MHz! 
https://www.asrock.com/mb/AMD/X570 Taichi/#Specification
https://www.gigabyte.com/fr/Motherboard/X570-AORUS-MASTER-rev-10#kf


----------



## lDevilDriverl

Last overclocking before 3800x


----------



## nick name

lDevilDriverl said:


> Last overclocking before 3800x


Ummmmmm wut.

How many tries to get through one Aida bench?

Also, don't forget that you can right-click on Start Benchmark and then select Start Memory Tests Only.


----------



## ilmazzo

lDevilDriverl said:


> Last overclocking before 3800x


these throughputs are ridiculously low, think you made something wrong there


----------



## mirzet1976

His RAM is not in Dual Channel


----------



## lDevilDriverl

ilmazzo said:


> lDevilDriverl said:
> 
> 
> 
> Last overclocking before 3800x
> 
> 
> 
> these throughputs are ridiculously low, think you made something wrong there
Click to expand...

You should be more attentive! It's single channel...


----------



## crakej

Reous said:


> Sounds great. What voltage do they need and can you show a RTC screen?


Here we go....sozz for delay!

Ram is at 1.425 SoC at 0.987v. I get about 54GBs transfer and 63ns latency.


----------



## ilmazzo

copy is a bit low and latency non that nice for being 3600, got 61.7 at 3400 cl14 fast timings from 1usmus calcuator, which seems stable so far to me but need moar testing, I'll add some screen when I have time

in my opinion there is not much need to push frequency much more than 3466, just stick with timer timings as much as you can to squeeze these ryzen chips....my .02$ or .0178€


----------



## LicSqualo

Latency is always different from a 1st gen Ryzen (1700x) vs a 2nd gen Ryzen (2600x).
But copy seems low also for me.
This is my speed at 3500 MHz c13 with a 101 base clock set (Trident RGB 3600c16)


----------



## nick name

crakej said:


> Here we go....sozz for delay!
> 
> Ram is at 1.425 SoC at 0.987v. I get about 54GBs transfer and 63ns latency.


Bro, that is awesome for 1.425V.


----------



## nick name

lDevilDriverl said:


> You should be more attentive! It's single channel...


So did you have any trouble getting that speed to complete Aida benchmarks?


----------



## crakej

Yes, copy is a bit low, but I'm sure it's fixable - I've had times when i've done tests and the copy speed has been really good, just gotta get those timings right.

My fastest profile so far is 3533 14,13,13,13,24 T1 CPU @ 4.2GHz. With CPU at this speed, this is the max I can get from my memory - after 3533 the CPU needs too much power to maintain 4.2GHz so I dropped to 4.1GHz. I have a LOT more testing to do with these patriots, but for now, check this out that I'm working on: 3866MTs T1, GearDown off, CL16,17,16,16,32. 1.49v ram, 1.15v SoC. These voltages are high as this is only early testing and settings are not optimal. I need to test with GearDown on and also T2. I've also got tCKE at 1 currently - I could reduce this, and the cpu voltage. T2 will probably also allow lower ram voltages, but that's a long way off! This profile boots reliably and runs benchmarks, In fact, I'm using it now to type this!


----------



## ilmazzo

LicSqualo said:


> Latency is always different from a 1st gen Ryzen (1700x) vs a 2nd gen Ryzen (2600x).
> But copy seems low also for me.
> This is my speed at 3500 MHz c13 with a 101 base clock set (Trident RGB 3600c16)


yup sorry, did not see the first gen ryzen

anyway, CL13.....was not a rule that odd cl values were rounded to the upper value on ryzens by the mc?


----------



## ilmazzo

crakej said:


> Yes, copy is a bit low, but I'm sure it's fixable - I've had times when i've done tests and the copy speed has been really good, just gotta get those timings right.
> 
> My fastest profile so far is 3533 14,13,13,13,24 T1 CPU @ 4.2GHz. With CPU at this speed, this is the max I can get from my memory - after 3533 the CPU needs too much power to maintain 4.2GHz so I dropped to 4.1GHz. I have a LOT more testing to do with these patriots, but for now, check this out that I'm working on: 3866MTs T1, GearDown off, CL16,17,16,16,32. 1.49v ram, 1.15v SoC. These voltages are high as this is only early testing and settings are not optimal. I need to test with GearDown on and also T2. I've also got tCKE at 1 currently - I could reduce this, and the cpu voltage. T2 will probably also allow lower ram voltages, but that's a long way off! This profile boots reliably and runs benchmarks, In fact, I'm using it now to type this!


well, good work!


----------



## nick name

crakej said:


> Yes, copy is a bit low, but I'm sure it's fixable - I've had times when i've done tests and the copy speed has been really good, just gotta get those timings right.
> 
> My fastest profile so far is 3533 14,13,13,13,24 T1 CPU @ 4.2GHz. With CPU at this speed, this is the max I can get from my memory - after 3533 the CPU needs too much power to maintain 4.2GHz so I dropped to 4.1GHz. I have a LOT more testing to do with these patriots, but for now, check this out that I'm working on: 3866MTs T1, GearDown off, CL16,17,16,16,32. 1.49v ram, 1.15v SoC. These voltages are high as this is only early testing and settings are not optimal. I need to test with GearDown on and also T2. I've also got tCKE at 1 currently - I could reduce this, and the cpu voltage. T2 will probably also allow lower ram voltages, but that's a long way off! This profile boots reliably and runs benchmarks, In fact, I'm using it now to type this!



Damn. Color me impressed. And I keep hearing more and more that Ryzen 2 will run 4000MHz RAM unofficially so I might have to find me a new kit of RAM soon.


----------



## LicSqualo

ilmazzo said:


> yup sorry, did not see the first gen ryzen
> 
> anyway, CL13.....was not a rule that odd cl values were rounded to the upper value on ryzens by the mc?


Personally I'm too ignorant to follow rules in this matter  And my system refuse to follow the dram calculator values
Effectively I put these subtimings copying a 3200 set from a user in C6H thread. But trying I found that was stable also for 3466 MHz and after (now) for 3500 MHz.
ROCK STABLE!!! (yes, a lucky shot, i know).

Regarding the rule you mention, I set 13 in bios, but the system has changed only the first value to 14 as you can see. 
1usmus have see this and have stated that the system has changed in automatic for the right value.
This was/is a fact for my case.


----------



## crakej

LicSqualo said:


> Personally I'm too ignorant to follow rules in this matter  And my system refuse to follow the dram calculator values
> Effectively I put these subtimings copying a 3200 set from a user in C6H thread. But trying I found that was stable also for 3466 MHz and after (now) for 3500 MHz.
> ROCK STABLE!!! (yes, a lucky shot, i know).
> 
> Regarding the rule you mention, I set 13 in bios, but the system has changed only the first value to 14 as you can see.
> 1usmus have see this and have stated that the system has changed in automatic for the right value.
> This was/is a fact for my case.


You can only use odd numbers for CL when GearDown=off usually...


----------



## LicSqualo

crakej said:


> You can only use odd numbers for CL when GearDown=off usually...


I tried with GDM Off, but no boot. And if boot, a lot of error. And if low errors no significant progress, despite the time spent to archive a good and stable result.
So GDM on is a must for my system .


----------



## ilmazzo

LicSqualo said:


> I tried with GDM Off, but no boot. And if boot, a lot of error. And if low errors no significant progress, despite the time spent to archive a good and stable result.
> So GDM on is a must fo my system


bella zio

as that film stated "whatever it works!"


----------



## crakej

LicSqualo said:


> I tried with GDM Off, but no boot. And if boot, a lot of error. And if low errors no significant progress, despite the time spent to archive a good and stable result.
> So GDM on is a must for my system .


Some kits just need it - and it doesn't affect performance in any meaningful way.


----------



## LicSqualo

e si! 

... and also "not all donuts go out with hole"  ahahahaha


----------



## LicSqualo

I've a "near stable" preset of 3568 MHz (3533 + 101 bck) in 1usmus c14 profile. This give me a solid 56k write, 55k read, 52k copy. 66,x latency.

But I prefer to live that spent my time to try and check stability. 
Here now is summer, so temperature could go higher 25°C. My actual profile is most conservative and not aggresive like in winter


----------



## lDevilDriverl

@LicSqualo As I know with GDM on all those 13-13-13-22-36 you set in bios will be ignored )))))) I already test such setups on 3600-3800 with 14 15 14 14 28 42 - 14 13 13 13 22 36 and there is no difference in aida (only result variations from run to run). So all those 13 is beautiful numbers. You can see that in Dram Calc bench too


----------



## LicSqualo

lDevilDriverl said:


> @LicSqualo As I know with GDM on all those 13-13-13-22-36 you set in bios will be ignored )))))) I already test such setups on 3600-3800 with 14 15 14 14 28 42 - 14 13 13 13 22 36 and there is no difference in aida (only result variations from run to run). So all those 13 is beautiful numbers. You can see that in Dram Calc bench too


Hi, I'm not sure I know what you mean.
I certainly can't put numbers at random otherwise the system won't start.
I just pointed out that I put 13 on tCL and the system changed it to 14. 
And I can't even think (it would be very illogical) that the system does not take into account the parameters that have been entered.
I'm wrong?


----------



## lDevilDriverl

@LicSqualo That's because tCWL 14. Turn off GDM, set tCWL 13 and you should be able to get tCL 13.


----------



## Shenhua

Hi guys. I know this might look the wrong place for my question but it isn't.

Before the questions, here are some things about my setup.
Last year in summer i bought some "holding place" parts for ryzen 3000, and now i decided I'll stick with the setup. Thing is, i need a new mobo because the one i have ( gigabyte ab350m gaming 3), it's not meant to deal with a 2600 and a 3600cl16 trident z kit. It's holding back the PB of the 2600 and I'm afraid to go past the current 3200cl14-14-14-32 im using, which considering the board, I think it's awesome, and i also paid only 40 bucks for it.

I don't care much about OCing the CPU, but i wanna squeeze the RAM a lot, since i have a 144hz monitor and 1080 oced, and playing with downgraded settings were needed to reach the framerate.

I'm looking to buy a b350/b450/x370/x470 USED that can handle a 2700x stock (if i upgrade in the future........for example b450m mortar VRM level, or better), and great for RAM OC.

So far, regarding RAM overclocking, first gen, despite the ****ty VRM gigabyte it's one of the best at RAM overclocking. I've heard asrock is the next best thing. Idk anything about MSI, and I don't wanna hear about Asus (had a x370 prime and it's crap, and the second gen it's even ****tier and overpriced.....i would settle for a crosshair x470, but nobody's gonna sell that board, and i dont want the crosshair x370).

Second gen, gigabyte sucks, Asus just like first gen, MSI is ok, asrock is ok.

SO....! Where I'm wrong and what are your recommendations?


----------



## lDevilDriverl

@nick name no trouble with one stick, but second one can't handle this frequency


----------



## nick name

lDevilDriverl said:


> @nick name no trouble with one stick, but second one can't handle this frequency


That's awesome. ASUS is supposed have figured something out in regards to RAM on their new boards and with the other rumors that many boards can run 4000MHz RAM is making me excited to see these boards get into people's rigs.


----------



## Darkomax

Working on 3533, I'll leave it running for some time because the problem with is that setup is that I have random errors. Could have been just a voltage issue as I haven't pushed more than 1.45V (1.44V gives tons of errors), now testing with 1.46V.

Edit : ran 37 runs without issue, I guess 1.45V was just borderline.


----------



## MacMus

it it possible that high voltage causes errors ?

I have TR1950X with 3400 Quad channel 14-15-14 which is stable according to usmus profile and extended run from AIDA.

I did put 1.4V on 1.39 sometimes my PC does not boot at all, on 1.42 and above produce tons of error in usmus tool...


----------



## pmc25

I wonder if that new DDR4 5000 CL17 2x8GB kit will work at the advertised speed on Ryzen 3 on a decent X570 board ...


----------



## crakej

MacMus said:


> it it possible that high voltage causes errors ?
> 
> I have TR1950X with 3400 Quad channel 14-15-14 which is stable according to usmus profile and extended run from AIDA.
> 
> I did put 1.4V on 1.39 sometimes my PC does not boot at all, on 1.42 and above produce tons of error in usmus tool...


Short answer - yes!

I have often had to bring down my voltage to bring stability - in fact, at some speeds I only get stability with the exact required voltage - one step up or down can kill stability.


----------



## nick name

pmc25 said:


> I wonder if that new DDR4 5000 CL17 2x8GB kit will work at the advertised speed on Ryzen 3 on a decent X570 board ...


Are you talking about the kit from the G.SKILL booth? Was that a retail 5000CL17 kit or is it a kit that was overclocked to 5000MHz 17-17-17-17?


----------



## pmc25

nick name said:


> Are you talking about the kit from the G.SKILL booth? Was that a retail 5000CL17 kit or is it a kit that was overclocked to 5000MHz 17-17-17-17?


It was presented as a new SKU. Whether they will actually launch we don't know. RAM sellers constantly announce new SKUs that never make it to market.


----------



## nick name

pmc25 said:


> It was presented as a new SKU. Whether they will actually launch we don't know. RAM sellers constantly announce new SKUs that never make it to market.


Well that is exciting. 

What I found disappointing was the display with Ryzen boards only running 3600 14-14-14-14. There are some folks that can run that now and a good many more that run 3600 14-15-14-14.


----------



## pmc25

nick name said:


> Well that is exciting.
> 
> What I found disappointing was the display with Ryzen boards only running 3600 14-14-14-14. There are some folks that can run that now and a good many more that run 3600 14-15-14-14.


The Ryzen displays were all on Ryzen 2, on X570. None of the RAM guys had Ryzen 3.

Also, as we know, both Threadripper and later production Zen, and all Zen+ typically went significantly tighter and higher than spec on many RAM kits. Zen 2 it should be better still ... but we have no idea what the ceiling is, or where diminishing returns cut in.

Sweetspot for Zen was 3466 as tight as possible. Sweetspot for Zen+ was 3600 *if* you could get it tight enough.


Sweetspot has to be well above 4000 for Zen 2, I'm thinking.


----------



## nick name

pmc25 said:


> The Ryzen displays were all on Ryzen 2, on X570. None of the RAM guys had Ryzen 3.
> 
> Also, as we know, both Threadripper and later production Zen, and all Zen+ typically went significantly tighter and higher than spec on many RAM kits. Zen 2 it should be better still ... but we have no idea what the ceiling is, or where diminishing returns cut in.
> 
> Sweetspot for Zen was 3466 as tight as possible. Sweetspot for Zen+ was 3600 *if* you could get it tight enough.
> 
> 
> Sweetspot has to be well above 4000 for Zen 2, I'm thinking.


It didn't occur to me that those rigs had Zen+ in them. That actually does make things look more promising if the boards were what allowed for that 14-14-14-14. And I'm assuming all those exhibition rigs were stable and not just bootable. Or am I wrong in assuming that?

And there does seem to be a bit of chatter about 4000MHz running on boards unofficially.


----------



## Shenhua

Shenhua said:


> Hi guys. I know this might look the wrong place for my question but it isn't.
> 
> Before the questions, here are some things about my setup.
> Last year in summer i bought some "holding place" parts for ryzen 3000, and now i decided I'll stick with the setup. Thing is, i need a new mobo because the one i have ( gigabyte ab350m gaming 3), it's not meant to deal with a 2600 and a 3600cl16 trident z kit. It's holding back the PB of the 2600 and I'm afraid to go past the current 3200cl14-14-14-32 im using, which considering the board, I think it's awesome, and i also paid only 40 bucks for it.
> 
> I don't care much about OCing the CPU, but i wanna squeeze the RAM a lot, since i have a 144hz monitor and 1080 oced, and playing with downgraded settings were needed to reach the framerate.
> 
> I'm looking to buy a b350/b450/x370/x470 USED that can handle a 2700x stock (if i upgrade in the future........for example b450m mortar VRM level, or better), and great for RAM OC.
> 
> So far, regarding RAM overclocking, first gen, despite the ****ty VRM gigabyte it's one of the best at RAM overclocking. I've heard asrock is the next best thing. Idk anything about MSI, and I don't wanna hear about Asus (had a x370 prime and it's crap, and the second gen it's even ****tier and overpriced.....i would settle for a crosshair x470, but nobody's gonna sell that board, and i dont want the crosshair x370).
> 
> Second gen, gigabyte sucks, Asus just like first gen, MSI is ok, asrock is ok.
> 
> SO....! Where I'm wrong and what are your recommendations?


Any1?

Enviado desde mi Redmi Note 3 mediante Tapatalk


----------



## pmc25

Does anybody have any idea whether these new G.Skill kits (fast and super tight timings) are Samsung or Micron?

They can't be Samsung B-die as production has ended and they wouldn't have done an 11th hour newer stepping.

That leaves Micron E-die & Samsung A-die.

Micron E-die which has been looking pretty good (potentially better than Samsung B-die), but nowhere near this good. Maybe a new stepping or higher bins though?

Samsung A-die is a totally unknown quantity at this point, as no announced products have been announced to be based on it.

G.Skill have been completely mum.


----------



## Dmac73

I wonder how much the memory overclocking improvements are tied into the IMC improvements vs motherboard improvements , i.e. - x470 --> x570. Obviously IMC will make a bigger difference. But i wonder how much a high end x470 board will hold back memory speeds vs x570.

Dmac


----------



## MacMus

Dmac73 said:


> I wonder how much the memory overclocking improvements are tied into the IMC improvements vs motherboard improvements , i.e. - x470 --> x570. Obviously IMC will make a bigger difference. But i wonder how much a high end x470 board will hold back memory speeds vs x570.
> 
> Dmac


to talking about imc on CPU ? 


Does anyone know how will new TR Zen2 look like ? Is it again "glued" with infinity fabric or there is some chiplet magic involved?


----------



## crakej

MacMus said:


> to talking about imc on CPU ?
> 
> 
> Does anyone know how will new TR Zen2 look like ? Is it again "glued" with infinity fabric or there is some chiplet magic involved?


I heard they've taken Threadripper 3 off their roadmap so we don't even know if there will be a Zen 2 part, especially with a 16 core AM4 coming out.

Do a google search - there's lots of information about it (thanks pmc25)


----------



## rdr09

Shenhua said:


> Any1?
> 
> Enviado desde mi Redmi Note 3 mediante Tapatalk


Read good things about MSI Carbon. It can handle an 8 core for sure. Prolly be able to handle 8 core R3 as well.

I have a X470 prime pro and have zero issues with RAM. I've bdie and non bdie. Both oc to 3466. MHz fine. Of course, bdie gives better numbers.


----------



## pmc25

crakej said:


> They've taken TR3 off their roadmap so we don't even know if there will be a Zen 2 part, especially with a 16 core AM4 coming out.


TR4. And please stop trolling. Yes we do know. The clickbait articles were just that. Zen 2 TR4 is coming. Su confirmed it at a press session after the presentation - question was asked by one of the sites publishing those articles, which she took a backhanded swipe at.

Unless they have so few wafers they can't get EPYC or TR4 out (in which case they should not be launching Navi - EPYC & TR4 are way higher margin), then it'll launch around the same time as 2017 and 2018.

What world do people live in where they think AMD are going to cede HEDT back to Intel again, with Intel launching their Volcano-X++++ at the end of Q3 this year (same launch time frame as TR4).


----------



## MacMus

looks like some folks are really up to the troll task!

New TR with chiplet design will be a monster ... can't wait to swap my decaying 4.2 Ghz 1950x ;-)


----------



## crakej

pmc25 said:


> TR4. And please stop trolling. Yes we do know. The clickbait articles were just that. Zen 2 TR4 is coming. Su confirmed it at a press session after the presentation - question was asked by one of the sites publishing those articles, which she took a backhanded swipe at.
> 
> Unless they have so few wafers they can't get EPYC or TR4 out (in which case they should not be launching Navi - EPYC & TR4 are way higher margin), then it'll launch around the same time as 2017 and 2018.
> 
> What world do people live in where they think AMD are going to cede HEDT back to Intel again, with Intel launching their Volcano-X++++ at the end of Q3 this year (same launch time frame as TR4).


With all due respect, I answered with what I know and in good intention. I have never been accused of being a 'troll', but thank you for the up to date information. My answer did not rule out anything - but you seem to have felt it necessary to make many assumptions about what I think. Whatever.

I look forward to Threadripper 3 then - it will be a beast! I heard that they were getting good results wafer-wise

And chill out please! What's the matter with you??

Edit: original post updated.


----------



## Shenhua

rdr09 said:


> Read good things about MSI Carbon. It can handle an 8 core for sure. Prolly be able to handle 8 core R3 as well.
> 
> 
> 
> I have a X470 prime pro and have zero issues with RAM. I've bdie and non bdie. Both oc to 3466. MHz fine. Of course, bdie gives better numbers.


What i said ofc doesn't exclude that some will have great experience, but to be fair, the x370 was only problems even to run 3200 cl14 with a b-die kit, on like 5-7 versions of bios. And I've heard and red a lot of bad experiences coming from others users on both x370 and x470. I also have a strix card, and while the card itself it's great, everything it's propietary, they still use warranty stickers in Europe and Asus software It's garbage and so are some of the features of the card. So at least until i hear good feedback, asus for me It's completely non existent.

Tnx for sharing your experience, and tnx for answering (looks like the others don't have much interest to say anything).

Enviado desde mi Redmi Note 3 mediante Tapatalk


----------



## MacMus

crakej said:


> Do a google search - there's lots of information about it (thanks pmc25)


Uh.. where ? i have not seen any infromational post about new TR architecture design .. only stiupid articles taking about killing off TR, which is nonsense.


----------



## ilmazzo

I got a crash in hunt showdown in the lobby when choosing a hunter so I went back to improve stability of my 3400 fast setting

Ended up increasing again voltage to 1,44 for ram, 1,1 for soc and enabled geardown mode as someone suggested me

well, yesterday I was able to do a run in quickplay with no issues at all (but even with the previos settings I had a match on test server fine but then it crashed in the live game as said before grrrrr), usual benches were fine 3170ish in cine r20 with cpu at default the only negative was that my latency was slightly hit bad, it increased to 62,7ns instead of 61,7 , oh well.....


----------



## crakej

MacMus said:


> Uh.. where ? i have not seen any infromational post about new TR architecture design .. only stiupid articles taking about killing off TR, which is nonsense.


All we really know is that it will be chiplet design.

It's not hard to find discussions about it - but the details you seek (rumoured details) are appearing in discussions with titles like 'Threadripper 3 killed from roadmap' Just read a little further!

Here's a good Redit conversation to start: https://www.reddit.com/r/Amd/comments/bkqcka/amd_drops_thirdgen_threadripper_from_latest/


----------



## MacMus

crakej said:


> Short answer - yes!
> 
> I have often had to bring down my voltage to bring stability - in fact, at some speeds I only get stability with the exact required voltage - one step up or down can kill stability.


Thanks!

i notice couple of things:

1. My Mobo does not boot on ERP mode and on my RAM settings unless i change s3+s5 and always "force" dual" boot for the motherboard. So it does boot.. then is shuts off during RAM POST and boot again for second time. successfully. What does that mean?

2. I get random 00 codes on mobo boot and it only helps when i pull battery and put it back in. I start to wonder if that could be RAM related and connected somehow to issue nr.1 as the post starts with ram ?

3. I use TestMeM 0.12 to test stability. right now i don't see any error, but once or twice i notice it started to run beyond usual time and never finished. does it point to issues with ram?

How can i address 1 and 2. I have Asus Zenith Extreme Alpha. Someone pointed me to look on asus forums but this is a nightmare people are only complaining and nothing is constructive. If asus support leaving this forum i wonder if i made a good decision with this mobo ;-(


----------



## MacMus

christoph said:


> it says right there "BIOS"
> 
> have you checked in the Asus Forum?


I still could not find solution for this ;-(


----------



## christoph

MacMus said:


> I still could not find solution for this ;-(



what was your settings again?

cpu voltage, SoC, Ram everything


----------



## crakej

MacMus said:


> Thanks!
> 
> i notice couple of things:
> 
> 1. My Mobo does not boot on ERP mode and on my RAM settings unless i change s3+s5 and always "force" dual" boot for the motherboard. So it does boot.. then is shuts off during RAM POST and boot again for second time. successfully. What does that mean?
> 
> 2. I get random 00 codes on mobo boot and it only helps when i pull battery and put it back in. I start to wonder if that could be RAM related and connected somehow to issue nr.1 as the post starts with ram ?
> 
> 3. I use TestMeM 0.12 to test stability. right now i don't see any error, but once or twice i notice it started to run beyond usual time and never finished. does it point to issues with ram?
> 
> How can i address 1 and 2. I have Asus Zenith Extreme Alpha. Someone pointed me to look on asus forums but this is a nightmare people are only complaining and nothing is constructive. If asus support leaving this forum i wonder if i made a good decision with this mobo ;-(


1. This is memory training trying to get the best settings for your memory before booting OS

2. On CH7 Code 00 is not used. Does this happen while your using the machine? What exactly happens - does it power off? If power is still on, press and hold in the power button until power does go off. This should force safe mode when you power on (doesn't always work). We do need your ram settings inc voltages + what memory do you have exactly?

3. dunno without 2!


----------



## hazium233

I was trying to read this thread for inspiration, but ran into something that reminded me about something I ran into the other day with stability testing.

The OP lists GSAT test parameters as "90% of available memory" (probably only ~12.8GB for Win10 for 16GB total), and the HCI Memtest example had 850MBx16 instances for 13.6.

There is an exchange early in the thread about GSAT under WSL where someone had an error because it couldn't allocate the default 93% of total ram, and the discussion turned into how much you needed to test with that program to be useful.

I have Ubuntu for Windows, which I was using to test via GSAT. How well has this worked for others here? Is a liveUSB going to be better (have Mint on a laptop actually so I already have an image)?

In general, how much memory are you guys able to test in Windows without hammering swap?

In part I'd like to try and improve my efficiency for stability testing, and if GSAT in Windows isn't going to be able to test enough ram to make it worthwhile, then I will consider dropping it.

I had a pass of GSAT (-M 13300) pass an hour, then throw an error in TM5 during a 6 cycle test. Curious if this was because not enough memory was allocated to make GSAT sensitive enough, or the tests are just different.


----------



## Keith Myers

> Curious if this was because not enough memory was allocated to make GSAT sensitive enough, or the tests are just different.


I think the tests are just different. I only have GSAT available to me as a Linux user. I run with stressapptest -W -M 12990 -s 3600 for my quick and dirty. But even with just -s 900 I can quickly determine whether the memory clocks and timings are even a valid candidate for 24/7/365 BOINC loads. I have pretty much standardized on 3466 CL14 Fast timings for my crunchers and called it quits. Good enough and fast enough for crunching.


----------



## hazium233

Thank you. I wonder if it might in general require more voltage for the same timings than GSAT (or looser timings), or if the temps are different. In hwinfo, max CPU temp was actually a fraction of a degree lower in TM5, but I can't measure ram temp.

For fun, I ended up making a persistent Live USB with the Mint - Mate image I had laying around to see how much available memory there would be with it running. It turned out that free -m gave me 15100, and GSAT could automatically allocate target memory. I might end up that way going forward so I don't have to boot the computer to Windows for first testing. Might try something with LXDE or Xfce though, which should free up a couple more MB as well, like Lu or Xubuntu.

I had Memtest86 on a usb, but it hasn't been useful unless I try settings that are way off, and it doesn't seem to even get those until pass 2 or so.


----------



## hazium233

So my ram are two 8gb Crucial Ballistix Sport AT rated at 2666 16-18-18-38 1.2v. They are D-Die, D9TZV.

I have been tinkering with 3200 CL16. RTC below, with SOC set to -0.075 (from 1.1v auto) and vDIMM 1.34... 16-16/19-18-36



Spoiler















Actually this is more or less the E-Die preset from the calculator, but anyway from Mint live usb, passed GSAT 2 hours



Spoiler















Booted into Windows, grabbed the RTC screenshot, and then promptly failed HCI memtest near instantly. Heh, back to the drawing board.

This is a Ryzen 1600 on a Strix B350-F (bios 4207 Pinnacle 1.0.0.6). So only my processor, motherboard, and ram working against me.

Kind of surprised this would pass GSAT so easily (it also did an hour last night), then fail so miserably.

So this may be more SOC / IMC related rather than the ram? Meaning, even though went 1.34 instead of 1.35 (for the hell of it), GSAT didn't produce an error and that isolates RAM more than cache? Time to crank SOC?

I don't really understand when it is time to tweak ProcODT or CAD BUS either on these. I haven't tried CAD BUS at all since Auto gives me straight 24's, which was recommended by the calculator. ProcODT recommended is only 48 for D-Die.

I'll just attach the 3200 D-Die V1 below, but mostly it seems tighter than the E-Die. I did experiments with the Debug setting and my imported XMP latencies (you see them in the bottom left, that is not RXMP), and it was going slowly.

I also don't know if tRFC is a factor, since the chip is rated for 350ns, and the calc is way below that (409 for D-Die preset, 572 on debug). I might loosen that and give it a shot.

edit: I didn't really notice the attach before here, so I had already uploaded to imgur for the other ones. I guess I can't spoiler attachments.


----------



## christoph

hazium233 said:


> So my ram are two 8gb Crucial Ballistix Sport AT rated at 2666 16-18-18-38 1.2v. They are D-Die, D9TZV.
> 
> I have been tinkering with 3200 CL16. RTC below, with SOC set to -0.075 (from 1.1v auto) and vDIMM 1.34... 16-16/19-18-36
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Actually this is more or less the E-Die preset from the calculator, but anyway from Mint live usb, passed GSAT 2 hours
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Booted into Windows, grabbed the RTC screenshot, and then promptly failed HCI memtest near instantly. Heh, back to the drawing board.
> 
> This is a Ryzen 1600 on a Strix B350-F (bios 4207 Pinnacle 1.0.0.6). So only my processor, motherboard, and ram working against me.
> 
> Kind of surprised this would pass GSAT so easily (it also did an hour last night), then fail so miserably.
> 
> So this may be more SOC / IMC related rather than the ram? Meaning, even though went 1.34 instead of 1.35 (for the hell of it), GSAT didn't produce an error and that isolates RAM more than cache? Time to crank SOC?
> 
> I don't really understand when it is time to tweak ProcODT or CAD BUS either on these. I haven't tried CAD BUS at all since Auto gives me straight 24's, which was recommended by the calculator. ProcODT recommended is only 48 for D-Die.
> 
> I'll just attach the 3200 D-Die V1 below, but mostly it seems tighter than the E-Die. I did experiments with the Debug setting and my imported XMP latencies (you see them in the bottom left, that is not RXMP), and it was going slowly.
> 
> I also don't know if tRFC is a factor, since the chip is rated for 350ns, and the calc is way below that (409 for D-Die preset, 572 on debug). I might loosen that and give it a shot.
> 
> edit: I didn't really notice the attach before here, so I had already uploaded to imgur for the other ones. I guess I can't spoiler attachments.



begin with SoC at 1.05v up to 1.12v and set tFAW at least 26


----------



## hazium233

^ Thanks for the input.

I have another question, this is about setting CLDO_VDDP. I thought I read conflicting info on this, but maybe I misread. Is the only way to apply a change to power down the system?


----------



## christoph

hazium233 said:


> ^ Thanks for the input.
> 
> I have another question, this is about setting CLDO_VDDP. I thought I read conflicting info on this, but maybe I misread. Is the only way to apply a change to power down the system?



if you mean if you need to power down the computer for it to apply a the change in the bios? then yes


----------



## SHNS0

This was an absolute nightmare. R5 1600, Asrock Steel Legend B450M, HyperX 3333mhz CL16 (now at 3000 but with much tighter overall timings)


----------



## ilmazzo

whoah italians are migrating (even) here seems lol

think 36k% can be a good measure of stability, but who knows.....


----------



## SHNS0

ilmazzo said:


> whoah italians are migrating (even) here seems lol
> 
> think 36k% can be a good measure of stability, but who knows.....


From what I've seen, almost everythng that goes over 15-20k has a very, very good chance of being perfectly stable.
Some people recommended me in the beginning like 3-6k, but I've had errors popping up afterwards.

In some cases I've had memory/SOC tweaking pass ramtest but fail after a long while Prime95 blend.... But in this case it did 24h of that too


----------



## ilmazzo

On my rig I recently ended up stabilizing it enabling geardown mode on my 3400 14 fast subtimings setup, vsoc 1.1 (default, so certainly stable from my pov) and waaaaaaay high 1,44v on dram (think I'll get it down to 1,42 and check stability since i?m getting near 50c while gaming which is a bit too high and summer is coming) 

hunt showdown is a strange beast on ram ocing at least on my rig

ciao


----------



## hazium233

Long story short, I think I was partly on the wrong path with ProcODT at 60ohms. I had done some testing at 53.3 and 48 before and didn't see any difference at those settings, but that was looser. Also I reevaluated some of the timings where there are "formulas," and also compared what I had to what Reous was using for D9TZV on a much better 3600MT/s OC.

Basically from previous:

VDIMM to 1.35 (decided not to screw around with goofy 1.34 any longer)
ProcODT to 48
tRAS to 38 (to better fit tCL + tRCD + tRTP +/- 2)
tWTRS to 5
tWTRL to 10
tCKE to 1

[email protected]/s-C16-16/19-18-38-1T---1.35v---SOC 1.025v---BIOS 4207---HCI-400---BLS8G4D26BFSTK.8FD



Spoiler















I essentially tested this with 30 min GSAT and TM5 6 cycles... except that those were with CLDO_VDDP at 700 the previous night. My progress is low because I just mess with it little by little each night. In this memtest session, I actually went back to CLDO_VDDP Auto (which is annoyingly opaque since my board will not say current setting).

Before that I did try tweaking tFAW to 28, bumping SOC to -0.0625 and tRTP up to 12 while still on 60 ohm ProcODT, but that ended up with a single error in test 2, cycle six for TM5.

Just glad to get a run to 400 done on halfway decent timings. This is a fair bit better than my previous "maybe stable" 3200 with tRCDRD at 20 and tRCDWR at 18. Will probably try to test it longer this weekend, and maybe play with CLDO_VDDP again.


----------



## SHNS0

ilmazzo said:


> On my rig I recently ended up stabilizing it enabling geardown mode on my 3400 14 fast subtimings setup, vsoc 1.1 (default, so certainly stable from my pov) and waaaaaaay high 1,44v on dram (think I'll get it down to 1,42 and check stability since i?m getting near 50c while gaming which is a bit too high and summer is coming)
> 
> hunt showdown is a strange beast on ram ocing at least on my rig
> 
> ciao


In my limited experience I've seen that lower SOC voltage actually helps with stability.
I'm not an expert, I just started going more seriously into RAM a few weeks ago - but from what I've seen the more you push the IMC, the more precise you have to be with the voltage - too little and it will complain, too much and it will complain.

And from what I've seen, it's the same with VDDP and RAM voltage.
My Steel Legend B450M was pushing auto SOC 1.1v and VDDP at I think either 1.05 or also 1.1v... And lowering those helped with getting more stable. I now have both at 0.95v
This might also change after CPU overclocking, though for me it didn't. I didn't push things very far, for the system I was giving more value to lower voltage and higher stability over that extra few % of performance.


----------



## Shenhua

Any1 knows if b450 mortar/tomahawk/pro carbon are T- Topology or daisy chain?


Enviado desde mi Redmi Note 3 mediante Tapatalk


----------



## ilmazzo

SHNS0 said:


> In my limited experience I've seen that lower SOC voltage actually helps with stability.
> I'm not an expert, I just started going more seriously into RAM a few weeks ago - but from what I've seen the more you push the IMC, the more precise you have to be with the voltage - too little and it will complain, too much and it will complain.
> 
> And from what I've seen, it's the same with VDDP and RAM voltage.
> My Steel Legend B450M was pushing auto SOC 1.1v and VDDP at I think either 1.05 or also 1.1v... And lowering those helped with getting more stable. I now have both at 0.95v
> This might also change after CPU overclocking, though for me it didn't. I didn't push things very far, for the system I was giving more value to lower voltage and higher stability over that extra few % of performance.


Makes sense

well, I was trying to get stable hunt showdown mainly, once that is achieved I'll try to optimize voltages on both soc and ram chips..... I say that hunt is weird because although I got no errors on TM5 stability tests, I get crash sometimes instantly or sometimes after half an hour of gaming.....that's why I have not yet launched stability tests marathons on my rig.... I will do it when I'll optimize the voltages..... 1,05 on soc and 1,42 on ram....not much but something that'll help temperatures for sure ... cheers


----------



## MacMus

crakej said:


> 2. On CH7 Code 00 is not used. Does this happen while your using the machine? What exactly happens - does it power off? If power is still on, press and hold in the power button until power does go off. This should force safe mode when you power on (doesn't always work). We do need your ram settings inc voltages + what memory do you have exactly?
> !


No it only happens sometimes on the first boot, but not always. PC stays ON, LCD shows 00, all fans are blowing at max speed. Nothing helps in this stage including replacing RAM, CPU except removing battery.

my RAM settings:



Code:


[2019/06/09 10:35:21]
Ai Overclock Tuner [Manual]
BCLK Frequency [Auto]
Custom CPU Core Ratio [Manual]
> FID [160]
> DID [8]
Overclocking Enhancement [Disabled]
Performance Bias [Auto]
Memory Frequency [DDR4-3400MHz]
Core Performance Boost [Disabled]
SMT Mode [Auto]
Spread Spectrum [Auto]
EPU Power Saving Mode [Disabled]
TPU [Keep Current Settings]
TRC_EOM [Auto]
TRTP_EOM [Auto]
TRRS_S_EOM [Auto]
TRRS_L_EOM [Auto]
TWTR_EOM [Auto]
TWTR_L_EOM [Auto]
TWCL_EOM [Auto]
TWR_EOM [Auto]
TFAW_EOM [Auto]
TRCT_EOM [Auto]
TREFI_EOM [Auto]
TRDRD_DD_EOM [Auto]
TRDRD_SD_EOM [Auto]
TRDRD_SC_EOM [Auto]
TRDRD_SCDLR_EOM [Auto]
TRDRD_SCL_EOM [Auto]
TWRWR_DD_EOM [Auto]
TWRWR_SD_EOM [Auto]
TWRWR_SC_EOM [Auto]
TWRWR_SCDLR_EOM [Auto]
TWRWR_SCL_EOM [Auto]
TWRRD_EOM [Auto]
TRDWR_EOM [Auto]
TWRRD_SCDLR_EOM [Auto]
Mem Over Clock Fail Count [Auto]
DRAM CAS# Latency [14]
DRAM RAS# to CAS# Read Delay [15]
DRAM RAS# to CAS# Write Delay [14]
DRAM RAS# PRE Time [14]
DRAM RAS# ACT Time [30]
Trc [44]
TrrdS [6]
TrrdL [6]
Tfaw [34]
TwtrS [4]
TwtrL [12]
Twr [12]
Trcpage [Auto]
TrdrdScl [3]
TwrwrScl [3]
Trfc [326]
Trfc2 [Auto]
Trfc4 [Auto]
Tcwl [14]
Trtp [8]
Trdwr [7]
Twrrd [4]
TwrwrSc [1]
TwrwrSd [7]
TwrwrDd [7]
TrdrdSc [1]
TrdrdSd [5]
TrdrdDd [5]
Tcke [1]
ProcODT [53.3 ohm]
Cmd2T [1T]
Gear Down Mode [Enabled]
Power Down Enable [Enabled]
RttNom [60 Ohm]
RttWr [Dynamic ODT Off]
RttPark [48 Ohm]
MemAddrCmdSetup [Auto]
MemCsOdtSetup [Auto]
MemCkeSetup [Auto]
MemCadBusClkDrvStren [24.0 Ohm]
MemCadBusAddrCmdDrvStren [24.0 Ohm]
MemCadBusCsOdtDrvStren [24.0 Ohm]
MemCadBusCkeDrvStren [24.0 Ohm]
CPU Load-line Calibration [Level 5]
CPU Current Capability [Auto]
CPU VRM Switching Frequency [Auto]
VRM Spread Spectrum [Auto]
CPU Power Duty Control [T.Probe]
CPU Power Phase Control [Auto]
CPU Power Thermal Control [120]
VDDSOC Load-line Calibration [Auto]
VDDSOC Current Capability [Auto]
VDDSOC Switching Frequency [Auto]
VDDSOC Phase Control [Auto]
VDDSOC Power Thermal Control [120]
DRAM Current Capability(CHA, CHB) [100%]
DRAM Current Capability(CHC, CHD) [100%]
DRAM Power Phase Control(CHA, CHB) [Extreme]
DRAM Power Phase Control(CHC, CHD) [Extreme]
DRAM Switching Frequency(CHA, CHB) [Auto]
DRAM Switching Frequency(CHC, CHD) [Auto]
DRAM VBoot Voltage AB [Auto]
DRAM VBoot Voltage CD [Auto]
VTTDDR AB Voltage [Auto]
VTTDDR CD Voltage [Auto]
DRAM CTRL REF Voltage on CHA [Auto]
DRAM CTRL REF Voltage on CHB [Auto]
DRAM CTRL REF Voltage on CHC [Auto]
DRAM CTRL REF Voltage on CHD [Auto]
VPP DRAM AB [Auto]
VPP DRAM CD [Auto]
1.8V Standby Voltage [Auto]
CPU 3.3v AUX [Auto]
2.5V SB Voltage [Auto]
DRAM R1 Tune [Auto]
DRAM R2 Tune [Auto]
DRAM R3 Tune [Auto]
DRAM R4 Tune [Auto]
Sense MI Skew [Disabled]
Sense MI Offset [Auto]
Clock Amplitude [Auto]
PLL Tune R1 [Auto]
PLL Tune R2 [Auto]
PCIE Tune R1 [Auto]
PCIE Tune R2 [Auto]
PCIE Tune R3 [Auto]
Ln2 Tune [Auto]
PLL Reference Voltage [Auto]
PLL Reference Voltage 2 [Auto]
Short Reset [Auto]
CLDO VDDP voltage [Auto]
CPU Core Voltage [Manual mode]
- CPU Core Voltage Override [1.31250]
CPU SOC Voltage [Manual mode]
- VDDSOC Voltage Override [1.02500]
DRAM AB Voltage [1.40000]
DRAM CD Voltage [1.40000]
1.8V PLL Voltage [Auto]
1.05V SB Voltage [Auto]
TPM Device Selection [Discrete TPM]
Erase fTPM NV for factory reset [Enabled]
SATA Port Enable [Enabled]
SATA Mode [AHCI]
SMART Self Test [Enabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
HD Audio Controller [Enabled]
CPU PCIE Link Mode [GEN 3]
SB PCIE Link Mode [GEN 3]
PCIEX16_1 Bandwidth [X16 Mode]
PCIEX16_2 Bandwidth [X8 Mode]
PCIEX16_3 Bandwidth [X16 Mode]
PCIEX16_4 Bandwidth [X4 Mode]
Asmedia USB 3.1 Controller [Enabled]
ASMedia Storage Controller [Enabled]
ASPM Support [Disabled]
When system is in working state [All On]
When system is in sleep, hibernate or soft off states [Aura Off]
10G LAN Card [Enabled]
10G LAN PXE Option ROM [Disabled]
Intel LAN Controller [Enabled]
Intel LAN OPROM [Disabled]
Wi-Fi Controller [Enabled]
Bluetooth Controller [Enabled]
USB power delivery in Soft Off state (S5) [Disabled]
ErP Ready [Enable(S4+S5)]
Restore On AC Power Loss [Power Off]
Power On By PCI-E/PCI [Disabled]
Power On By RTC [Disabled]
NX Mode [Enabled]
SVM Mode [Enabled]
Above 4G Decoding [Enabled]
SR-IOV Support [Enabled]
Network Stack [Disabled]
Device [Samsung SSD 850 EVO 500GB]
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
KingstonDataTraveler 3.0PMAP [Auto]
U31G2_EC1 [Enabled]
U31G2_E2 [Enabled]
U31G2_E3 [Enabled]
U31G2_E4 [Enabled]
U31G2_1 [Enabled]
U31G1_1 [Enabled]
U31G1_2 [Enabled]
U31G1_3 [Enabled]
U31G1_4 [Enabled]
U31G1_5 [Enabled]
U31G1_6 [Enabled]
U31G1_7 [Enabled]
U31G1_8 [Enabled]
U31G1_9 [Enabled]
U31G1_10 [Enabled]
U31G1_11 [Enabled]
U31G1_12 [Enabled]
USB13 [Enabled]
USB14 [Enabled]
USB15 [Enabled]
USB16 [Enabled]
CPU Temperature [Monitor]
MotherBoard Temperature [Monitor]
VRM Temperature [Monitor]
PCH Temperature [Monitor]
PSU Temperature [Monitor]
T_Sensor1 Temperature [Monitor]
T_Sensor2 Temperature [Monitor]
DIMM.2 sensor1 Temperature [Monitor]
DIMM.2 sensor2 Temperature [Monitor]
EXT_Sensor1  Temperature [Monitor]
EXT_Sensor2  Temperature [Monitor]
EXT_Sensor3  Temperature [Monitor]
CPU Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
HAMP Fan Speed [Monitor]
W_PUMP+ Speed [Monitor]
CPU Optional Fan Speed [Monitor]
Extension Fan 1 Speed [Monitor]
Extension Fan 2 Speed [Monitor]
Extension Fan 3 Speed [Monitor]
Extension Fan 4 Speed [Monitor]
Extension Fan 5 Speed [Monitor]
Extension Fan 6 Speed [Monitor]
HS Fan Speed [Monitor]
FLOW_RATE [Monitor]
Water In T Sensor Temperature [Monitor]
Water Out T Sensor Temperature [Monitor]
WB_FLOW_RATE [Monitor]
WB In T Sensor Temperature [Monitor]
WB Out T Sensor Temperature [Monitor]
PSU Fan Speed [Monitor]
PSU Power [Monitor]
PSU Vin Voltage [Monitor]
CPU Core Voltage [Monitor]
3.3V Voltage [Monitor]
5V Voltage [Monitor]
12V Voltage [Monitor]
CPU Q-Fan Control [PWM Mode]
CPU Fan Smoothing Up/Down Time [0 sec]
CPU Fan Speed Lower Limit [600 RPM]
CPU Fan Profile [Manual]
CPU Upper Temperature [50]
CPU Fan Max. Duty Cycle (%) [100]
CPU Middle Temperature [45]
CPU Fan Middle. Duty Cycle (%) [100]
CPU Lower Temperature [10]
CPU Fan Min. Duty Cycle (%) [100]
Chassis Fan 1 Q-Fan Control [Auto]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Smoothing Up/Down Time [0 sec]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 1 Profile [Standard]
Chassis Fan 2 Q-Fan Control [Auto]
Chassis Fan 2 Q-Fan Source [CPU]
Chassis Fan 2 Smoothing Up/Down Time [0 sec]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 2 Profile [Standard]
HAMP Fan Q-Fan Control [Auto]
HAMP Fan Source [CPU]
HAMP Fan Smoothing Up/Down Time [0 sec]
HAMP Fan Speed Low Limit [200 RPM]
HAMP Fan Profile [Standard]
Extension Fan 1 Q-Fan Control [Auto]
Extension Fan 1 Q-Fan Source [CPU]
Extension Fan 1 Speed Low Limit [200 RPM]
Extension Fan 1 Profile [Standard]
Extension Fan 2 Q-Fan Control [Auto]
Extension Fan 2 Q-Fan Source [CPU]
Extension Fan 2 Speed Low Limit [200 RPM]
Extension Fan 2 Profile [Standard]
Extension Fan 3 Q-Fan Control [Auto]
Extension Fan 3 Q-Fan Source [Multiple Sources]
Temperature Source 1 [EXT_Sensor1]
Temperature Source 2 [EXT_Sensor3]
Temperature Source 3 [N/A]
Extension Fan 3 Speed Low Limit [600 RPM]
Extension Fan 3 Profile [Manual]
Extension Fan 3 Upper Temperature [40]
Extension Fan 3 Max. Duty Cycle (%) [100]
Extension Fan 3 Middle Temperature [34]
Extension Fan 3 Middle. Duty Cycle (%) [65]
Extension Fan 3 Lower Temperature [34]
Extension Fan 3 Min. Duty Cycle (%) [65]
Extension Fan 4 Q-Fan Control [Auto]
Extension Fan 4 Q-Fan Source [CPU]
Extension Fan 4 Speed Low Limit [200 RPM]
Extension Fan 4 Profile [Standard]
Extension Fan 5 Q-Fan Control [Auto]
Extension Fan 5 Q-Fan Source [Multiple Sources]
Temperature Source 1 [EXT_Sensor1]
Temperature Source 2 [EXT_Sensor3]
Temperature Source 3 [N/A]
Extension Fan 5 Speed Low Limit [600 RPM]
Extension Fan 5 Profile [Manual]
Extension Fan 5 Upper Temperature [36]
Extension Fan 5 Max. Duty Cycle (%) [100]
Extension Fan 5 Middle Temperature [32]
Extension Fan 5 Middle. Duty Cycle (%) [70]
Extension Fan 5 Lower Temperature [32]
Extension Fan 5 Min. Duty Cycle (%) [70]
Extension Fan 6 Q-Fan Control [Auto]
Extension Fan 6 Q-Fan Source [Multiple Sources]
Temperature Source 1 [EXT_Sensor1]
Temperature Source 2 [EXT_Sensor3]
Temperature Source 3 [N/A]
Extension Fan 6 Speed Low Limit [600 RPM]
Extension Fan 6 Profile [Manual]
Extension Fan 6 Upper Temperature [36]
Extension Fan 6 Max. Duty Cycle (%) [100]
Extension Fan 6 Middle Temperature [32]
Extension Fan 6 Middle. Duty Cycle (%) [70]
Extension Fan 6 Lower Temperature [32]
Extension Fan 6 Min. Duty Cycle (%) [70]
W_PUMP+ Control [Disabled]
Heatsink Fan Q-Fan Control [PWM Mode]
Heatsink Fan Smoothing Up/Down Time [0 sec]
Heatsink Fan Speed Low Limit [Ignore]
Heatsink Fan Profile [Manual]
Heatsink Fan Upper Temperature [75]
Heatsink Fan Max. Duty Cycle (%) [60]
Heatsink Fan Middle Temperature [80]
Heatsink Fan Middle. Duty Cycle (%) [30]
Heatsink Fan Lower Temperature [60]
Heatsink Fan Min. Duty Cycle (%) [0]
Power Supply Unit  Fan Q-Fan Control [PWM Mode]
Power Supply Unit Fan Speed Low Limit [200 RPM]
Power Supply Unit  Fan Profile [Standard]
Fast Boot [Enabled]
Next Boot after AC Power Loss [Normal Boot]
Boot Logo Display [Auto]
POST Delay Time [3 sec]
Boot up NumLock State [Enabled]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Enabled]
Interrupt 19 Capture [Disabled]
Setup Mode [Advanced Mode]
Launch CSM [Enabled]
Boot Device Control [UEFI and Legacy OPROM]
Boot from Network Devices [Legacy only]
Boot from Storage Devices [Legacy only]
Boot from PCI-E Expansion Devices [Legacy only]
OS Type [Other OS]
Setup Animator [Disabled]
Profile Name [3466]
Save to Profile [1]
DIMM Slot Number [DIMM_A1]
Download & Install ARMOURY CRATE app [Enabled]
Bus Interface [PCIEX16_3]
RedirectForReturnDis [Auto]
L2 TLB Associativity [Auto]
Platform First Error Handling [Disabled]
Enable IBS [Auto]
Global C-state Control [Auto]
Power Supply Idle Control [Auto]
Opcache Control [Auto]
OC Mode [Normal Operation]
Relaxed EDC throttling [Auto]
SEV-ES ASID Space Limit [1]
Streaming Stores Control [Auto]
ACPI _CST C1 Declaration [Auto]
L1 Stream HW Prefetcher [Auto]
L2 Stream HW Prefetcher [Auto]
SMU and PSP Production Mode [Auto]
DRAM scrub time [Auto]
Redirect scrubber control [Auto]
Disable DF sync flood propagation [Auto]
Freeze DF module queues on error [Auto]
GMI encryption control [Auto]
xGMI encryption control [Auto]
CC6 memory region encryption [Auto]
Location of private memory regions [Auto]
System probe filter [Auto]
Memory interleaving [Channel]
Memory interleaving size [2 KB]
Channel interleaving hash [Enabled]
Memory Clear [Disabled]
ACPI SLIT Distance Control [Auto]
Overclock [Enabled]
Memory Clock Speed [Auto]
Tcl [Auto]
Trcdrd [Auto]
Trcdwr [Auto]
Trp [Auto]
Tras [Auto]
Trc Ctrl [Auto]
TrrdS [Auto]
TrrdL [Auto]
Tfaw Ctrl [Auto]
TwtrS [Auto]
TwtrL [Auto]
Twr Ctrl [Auto]
Trcpage Ctrl [Auto]
TrdrdScL Ctrl [Auto]
TwrwrScL Ctrl [Auto]
Trfc Ctrl [Auto]
Trfc2 Ctrl [Auto]
Trfc4 Ctrl [Auto]
Fail_CNT [5]
ProcODT [Auto]
Tcwl [Auto]
Trtp [Auto]
Trdwr [Auto]
Twrrd [Auto]
TwrwrSc [Auto]
TwrwrSd [Auto]
TwrwrDd [Auto]
TrdrdSc [Auto]
TrdrdSd [Auto]
TrdrdDd [Auto]
Tcke [Auto]
Power Down Enable [Auto]
Cmd2T [Auto]
Gear Down Mode [Auto]
CAD Bus Timing User Controls [Auto]
CAD Bus Drive Strength User Controls [Auto]
Data Bus Configuration User Controls [Auto]
DFE Read Training [Enable]
FFE Write Training [Auto]
PMU Pattern Bits Control [Auto]
Data Poisoning [Auto]
DRAM ECC Symbol Size [Auto]
DRAM ECC Enable [Auto]
TSME [Auto]
Data Scramble [Auto]
Chipselect Interleaving [Auto]
BankGroupSwap [Auto]
BankGroupSwapAlt [Auto]
Address Hash Bank [Auto]
Address Hash CS [Auto]
MBIST Enable [Disabled]
IOMMU [Auto]
Determinism Slider [Auto]
cTDP Control [Auto]
Fan Control [Auto]
PSI [Auto]
ACS Enable [Auto]
Enable AER Cap [Auto]
PCIe ARI Support [Auto]
CLDO_VDDP Control [Auto]
HD Audio Enable [Auto]
SOC OVERCLOCK VID [0]
Block PCIe Loopback [Auto]
CRS Delay [6]
CRS Limit [6]
Ignore sideband [Disabled]
Disable L1 w/a [Disabled]
Disable BridgeDis [Disabled]
Toggle RRC Enable [Disabled]
IRQ sets BridgeDis [Disabled]
PCIE RESET Control [Disabled]
AMD XGBE Controller 0 [Auto]
AMD XGBE Controller 1 [Auto]
AMD XGBE Controller 2 [Auto]
AMD XGBE Controller 3 [Auto]
AMD XGBE Controller 4 [Auto]
AMD XGBE Controller 5 [Auto]
AMD XGBE Controller 6 [Auto]
AMD XGBE Controller 7 [Auto]
NTB Enable [Auto]


----------



## nick name

I was hoping the memory threshold tied to Infinity Fabric would have been closer to 4000+ , but I guess this isn't terrible.


----------



## crakej

MacMus said:


> No it only happens sometimes on the first boot, but not always. PC stays ON, LCD shows 00, all fans are blowing at max speed. Nothing helps in this stage including replacing RAM, CPU except removing battery.
> 
> my RAM settings:
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> Code:
> 
> 
> [2019/06/09 10:35:21]
> Ai Overclock Tuner [Manual]
> BCLK Frequency [Auto]
> Custom CPU Core Ratio [Manual]
> > FID [160]
> > DID [8]
> Overclocking Enhancement [Disabled]
> Performance Bias [Auto]
> Memory Frequency [DDR4-3400MHz]
> Core Performance Boost [Disabled]
> SMT Mode [Auto]
> Spread Spectrum [Auto]
> EPU Power Saving Mode [Disabled]
> TPU [Keep Current Settings]
> TRC_EOM [Auto]
> TRTP_EOM [Auto]
> TRRS_S_EOM [Auto]
> TRRS_L_EOM [Auto]
> TWTR_EOM [Auto]
> TWTR_L_EOM [Auto]
> TWCL_EOM [Auto]
> TWR_EOM [Auto]
> TFAW_EOM [Auto]
> TRCT_EOM [Auto]
> TREFI_EOM [Auto]
> TRDRD_DD_EOM [Auto]
> TRDRD_SD_EOM [Auto]
> TRDRD_SC_EOM [Auto]
> TRDRD_SCDLR_EOM [Auto]
> TRDRD_SCL_EOM [Auto]
> TWRWR_DD_EOM [Auto]
> TWRWR_SD_EOM [Auto]
> TWRWR_SC_EOM [Auto]
> TWRWR_SCDLR_EOM [Auto]
> TWRWR_SCL_EOM [Auto]
> TWRRD_EOM [Auto]
> TRDWR_EOM [Auto]
> TWRRD_SCDLR_EOM [Auto]
> Mem Over Clock Fail Count [Auto]
> DRAM CAS# Latency [14]
> DRAM RAS# to CAS# Read Delay [15]
> DRAM RAS# to CAS# Write Delay [14]
> DRAM RAS# PRE Time [14]
> DRAM RAS# ACT Time [30]
> Trc [44]
> TrrdS [6]
> TrrdL [6]
> Tfaw [34]
> TwtrS [4]
> TwtrL [12]
> Twr [12]
> Trcpage [Auto]
> TrdrdScl [3]
> TwrwrScl [3]
> Trfc [326]
> Trfc2 [Auto]
> Trfc4 [Auto]
> Tcwl [14]
> Trtp [8]
> Trdwr [7]
> Twrrd [4]
> TwrwrSc [1]
> TwrwrSd [7]
> TwrwrDd [7]
> TrdrdSc [1]
> TrdrdSd [5]
> TrdrdDd [5]
> Tcke [1]
> ProcODT [53.3 ohm]
> Cmd2T [1T]
> Gear Down Mode [Enabled]
> Power Down Enable [Enabled]
> RttNom [60 Ohm]
> RttWr [Dynamic ODT Off]
> RttPark [48 Ohm]
> MemAddrCmdSetup [Auto]
> MemCsOdtSetup [Auto]
> MemCkeSetup [Auto]
> MemCadBusClkDrvStren [24.0 Ohm]
> MemCadBusAddrCmdDrvStren [24.0 Ohm]
> MemCadBusCsOdtDrvStren [24.0 Ohm]
> MemCadBusCkeDrvStren [24.0 Ohm]
> CPU Load-line Calibration [Level 5]
> CPU Current Capability [Auto]
> CPU VRM Switching Frequency [Auto]
> VRM Spread Spectrum [Auto]
> CPU Power Duty Control [T.Probe]
> CPU Power Phase Control [Auto]
> CPU Power Thermal Control [120]
> VDDSOC Load-line Calibration [Auto]
> VDDSOC Current Capability [Auto]
> VDDSOC Switching Frequency [Auto]
> VDDSOC Phase Control [Auto]
> VDDSOC Power Thermal Control [120]
> DRAM Current Capability(CHA, CHB) [100%]
> DRAM Current Capability(CHC, CHD) [100%]
> DRAM Power Phase Control(CHA, CHB) [Extreme]
> DRAM Power Phase Control(CHC, CHD) [Extreme]
> DRAM Switching Frequency(CHA, CHB) [Auto]
> DRAM Switching Frequency(CHC, CHD) [Auto]
> DRAM VBoot Voltage AB [Auto]
> DRAM VBoot Voltage CD [Auto]
> VTTDDR AB Voltage [Auto]
> VTTDDR CD Voltage [Auto]
> DRAM CTRL REF Voltage on CHA [Auto]
> DRAM CTRL REF Voltage on CHB [Auto]
> DRAM CTRL REF Voltage on CHC [Auto]
> DRAM CTRL REF Voltage on CHD [Auto]
> VPP DRAM AB [Auto]
> VPP DRAM CD [Auto]
> 1.8V Standby Voltage [Auto]
> CPU 3.3v AUX [Auto]
> 2.5V SB Voltage [Auto]
> DRAM R1 Tune [Auto]
> DRAM R2 Tune [Auto]
> DRAM R3 Tune [Auto]
> DRAM R4 Tune [Auto]
> Sense MI Skew [Disabled]
> Sense MI Offset [Auto]
> Clock Amplitude [Auto]
> PLL Tune R1 [Auto]
> PLL Tune R2 [Auto]
> PCIE Tune R1 [Auto]
> PCIE Tune R2 [Auto]
> PCIE Tune R3 [Auto]
> Ln2 Tune [Auto]
> PLL Reference Voltage [Auto]
> PLL Reference Voltage 2 [Auto]
> Short Reset [Auto]
> CLDO VDDP voltage [Auto]
> CPU Core Voltage [Manual mode]
> - CPU Core Voltage Override [1.31250]
> CPU SOC Voltage [Manual mode]
> - VDDSOC Voltage Override [1.02500]
> DRAM AB Voltage [1.40000]
> DRAM CD Voltage [1.40000]
> 1.8V PLL Voltage [Auto]
> 1.05V SB Voltage [Auto]
> TPM Device Selection [Discrete TPM]
> Erase fTPM NV for factory reset [Enabled]
> SATA Port Enable [Enabled]
> SATA Mode [AHCI]
> SMART Self Test [Enabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> HD Audio Controller [Enabled]
> CPU PCIE Link Mode [GEN 3]
> SB PCIE Link Mode [GEN 3]
> PCIEX16_1 Bandwidth [X16 Mode]
> PCIEX16_2 Bandwidth [X8 Mode]
> PCIEX16_3 Bandwidth [X16 Mode]
> PCIEX16_4 Bandwidth [X4 Mode]
> Asmedia USB 3.1 Controller [Enabled]
> ASMedia Storage Controller [Enabled]
> ASPM Support [Disabled]
> When system is in working state [All On]
> When system is in sleep, hibernate or soft off states [Aura Off]
> 10G LAN Card [Enabled]
> 10G LAN PXE Option ROM [Disabled]
> Intel LAN Controller [Enabled]
> Intel LAN OPROM [Disabled]
> Wi-Fi Controller [Enabled]
> Bluetooth Controller [Enabled]
> USB power delivery in Soft Off state (S5) [Disabled]
> ErP Ready [Enable(S4+S5)]
> Restore On AC Power Loss [Power Off]
> Power On By PCI-E/PCI [Disabled]
> Power On By RTC [Disabled]
> NX Mode [Enabled]
> SVM Mode [Enabled]
> Above 4G Decoding [Enabled]
> SR-IOV Support [Enabled]
> Network Stack [Disabled]
> Device [Samsung SSD 850 EVO 500GB]
> Legacy USB Support [Enabled]
> XHCI Hand-off [Enabled]
> KingstonDataTraveler 3.0PMAP [Auto]
> U31G2_EC1 [Enabled]
> U31G2_E2 [Enabled]
> U31G2_E3 [Enabled]
> U31G2_E4 [Enabled]
> U31G2_1 [Enabled]
> U31G1_1 [Enabled]
> U31G1_2 [Enabled]
> U31G1_3 [Enabled]
> U31G1_4 [Enabled]
> U31G1_5 [Enabled]
> U31G1_6 [Enabled]
> U31G1_7 [Enabled]
> U31G1_8 [Enabled]
> U31G1_9 [Enabled]
> U31G1_10 [Enabled]
> U31G1_11 [Enabled]
> U31G1_12 [Enabled]
> USB13 [Enabled]
> USB14 [Enabled]
> USB15 [Enabled]
> USB16 [Enabled]
> CPU Temperature [Monitor]
> MotherBoard Temperature [Monitor]
> VRM Temperature [Monitor]
> PCH Temperature [Monitor]
> PSU Temperature [Monitor]
> T_Sensor1 Temperature [Monitor]
> T_Sensor2 Temperature [Monitor]
> DIMM.2 sensor1 Temperature [Monitor]
> DIMM.2 sensor2 Temperature [Monitor]
> EXT_Sensor1  Temperature [Monitor]
> EXT_Sensor2  Temperature [Monitor]
> EXT_Sensor3  Temperature [Monitor]
> CPU Fan Speed [Monitor]
> Chassis Fan 1 Speed [Monitor]
> Chassis Fan 2 Speed [Monitor]
> HAMP Fan Speed [Monitor]
> W_PUMP+ Speed [Monitor]
> CPU Optional Fan Speed [Monitor]
> Extension Fan 1 Speed [Monitor]
> Extension Fan 2 Speed [Monitor]
> Extension Fan 3 Speed [Monitor]
> Extension Fan 4 Speed [Monitor]
> Extension Fan 5 Speed [Monitor]
> Extension Fan 6 Speed [Monitor]
> HS Fan Speed [Monitor]
> FLOW_RATE [Monitor]
> Water In T Sensor Temperature [Monitor]
> Water Out T Sensor Temperature [Monitor]
> WB_FLOW_RATE [Monitor]
> WB In T Sensor Temperature [Monitor]
> WB Out T Sensor Temperature [Monitor]
> PSU Fan Speed [Monitor]
> PSU Power [Monitor]
> PSU Vin Voltage [Monitor]
> CPU Core Voltage [Monitor]
> 3.3V Voltage [Monitor]
> 5V Voltage [Monitor]
> 12V Voltage [Monitor]
> CPU Q-Fan Control [PWM Mode]
> CPU Fan Smoothing Up/Down Time [0 sec]
> CPU Fan Speed Lower Limit [600 RPM]
> CPU Fan Profile [Manual]
> CPU Upper Temperature [50]
> CPU Fan Max. Duty Cycle (%) [100]
> CPU Middle Temperature [45]
> CPU Fan Middle. Duty Cycle (%) [100]
> CPU Lower Temperature [10]
> CPU Fan Min. Duty Cycle (%) [100]
> Chassis Fan 1 Q-Fan Control [Auto]
> Chassis Fan 1 Q-Fan Source [CPU]
> Chassis Fan 1 Smoothing Up/Down Time [0 sec]
> Chassis Fan 1 Speed Low Limit [200 RPM]
> Chassis Fan 1 Profile [Standard]
> Chassis Fan 2 Q-Fan Control [Auto]
> Chassis Fan 2 Q-Fan Source [CPU]
> Chassis Fan 2 Smoothing Up/Down Time [0 sec]
> Chassis Fan 2 Speed Low Limit [200 RPM]
> Chassis Fan 2 Profile [Standard]
> HAMP Fan Q-Fan Control [Auto]
> HAMP Fan Source [CPU]
> HAMP Fan Smoothing Up/Down Time [0 sec]
> HAMP Fan Speed Low Limit [200 RPM]
> HAMP Fan Profile [Standard]
> Extension Fan 1 Q-Fan Control [Auto]
> Extension Fan 1 Q-Fan Source [CPU]
> Extension Fan 1 Speed Low Limit [200 RPM]
> Extension Fan 1 Profile [Standard]
> Extension Fan 2 Q-Fan Control [Auto]
> Extension Fan 2 Q-Fan Source [CPU]
> Extension Fan 2 Speed Low Limit [200 RPM]
> Extension Fan 2 Profile [Standard]
> Extension Fan 3 Q-Fan Control [Auto]
> Extension Fan 3 Q-Fan Source [Multiple Sources]
> Temperature Source 1 [EXT_Sensor1]
> Temperature Source 2 [EXT_Sensor3]
> Temperature Source 3 [N/A]
> Extension Fan 3 Speed Low Limit [600 RPM]
> Extension Fan 3 Profile [Manual]
> Extension Fan 3 Upper Temperature [40]
> Extension Fan 3 Max. Duty Cycle (%) [100]
> Extension Fan 3 Middle Temperature [34]
> Extension Fan 3 Middle. Duty Cycle (%) [65]
> Extension Fan 3 Lower Temperature [34]
> Extension Fan 3 Min. Duty Cycle (%) [65]
> Extension Fan 4 Q-Fan Control [Auto]
> Extension Fan 4 Q-Fan Source [CPU]
> Extension Fan 4 Speed Low Limit [200 RPM]
> Extension Fan 4 Profile [Standard]
> Extension Fan 5 Q-Fan Control [Auto]
> Extension Fan 5 Q-Fan Source [Multiple Sources]
> Temperature Source 1 [EXT_Sensor1]
> Temperature Source 2 [EXT_Sensor3]
> Temperature Source 3 [N/A]
> Extension Fan 5 Speed Low Limit [600 RPM]
> Extension Fan 5 Profile [Manual]
> Extension Fan 5 Upper Temperature [36]
> Extension Fan 5 Max. Duty Cycle (%) [100]
> Extension Fan 5 Middle Temperature [32]
> Extension Fan 5 Middle. Duty Cycle (%) [70]
> Extension Fan 5 Lower Temperature [32]
> Extension Fan 5 Min. Duty Cycle (%) [70]
> Extension Fan 6 Q-Fan Control [Auto]
> Extension Fan 6 Q-Fan Source [Multiple Sources]
> Temperature Source 1 [EXT_Sensor1]
> Temperature Source 2 [EXT_Sensor3]
> Temperature Source 3 [N/A]
> Extension Fan 6 Speed Low Limit [600 RPM]
> Extension Fan 6 Profile [Manual]
> Extension Fan 6 Upper Temperature [36]
> Extension Fan 6 Max. Duty Cycle (%) [100]
> Extension Fan 6 Middle Temperature [32]
> Extension Fan 6 Middle. Duty Cycle (%) [70]
> Extension Fan 6 Lower Temperature [32]
> Extension Fan 6 Min. Duty Cycle (%) [70]
> W_PUMP+ Control [Disabled]
> Heatsink Fan Q-Fan Control [PWM Mode]
> Heatsink Fan Smoothing Up/Down Time [0 sec]
> Heatsink Fan Speed Low Limit [Ignore]
> Heatsink Fan Profile [Manual]
> Heatsink Fan Upper Temperature [75]
> Heatsink Fan Max. Duty Cycle (%) [60]
> Heatsink Fan Middle Temperature [80]
> Heatsink Fan Middle. Duty Cycle (%) [30]
> Heatsink Fan Lower Temperature [60]
> Heatsink Fan Min. Duty Cycle (%) [0]
> Power Supply Unit  Fan Q-Fan Control [PWM Mode]
> Power Supply Unit Fan Speed Low Limit [200 RPM]
> Power Supply Unit  Fan Profile [Standard]
> Fast Boot [Enabled]
> Next Boot after AC Power Loss [Normal Boot]
> Boot Logo Display [Auto]
> POST Delay Time [3 sec]
> Boot up NumLock State [Enabled]
> Wait For 'F1' If Error [Enabled]
> Option ROM Messages [Enabled]
> Interrupt 19 Capture [Disabled]
> Setup Mode [Advanced Mode]
> Launch CSM [Enabled]
> Boot Device Control [UEFI and Legacy OPROM]
> Boot from Network Devices [Legacy only]
> Boot from Storage Devices [Legacy only]
> Boot from PCI-E Expansion Devices [Legacy only]
> OS Type [Other OS]
> Setup Animator [Disabled]
> Profile Name [3466]
> Save to Profile [1]
> DIMM Slot Number [DIMM_A1]
> Download & Install ARMOURY CRATE app [Enabled]
> Bus Interface [PCIEX16_3]
> RedirectForReturnDis [Auto]
> L2 TLB Associativity [Auto]
> Platform First Error Handling [Disabled]
> Enable IBS [Auto]
> Global C-state Control [Auto]
> Power Supply Idle Control [Auto]
> Opcache Control [Auto]
> OC Mode [Normal Operation]
> Relaxed EDC throttling [Auto]
> SEV-ES ASID Space Limit [1]
> Streaming Stores Control [Auto]
> ACPI _CST C1 Declaration [Auto]
> L1 Stream HW Prefetcher [Auto]
> L2 Stream HW Prefetcher [Auto]
> SMU and PSP Production Mode [Auto]
> DRAM scrub time [Auto]
> Redirect scrubber control [Auto]
> Disable DF sync flood propagation [Auto]
> Freeze DF module queues on error [Auto]
> GMI encryption control [Auto]
> xGMI encryption control [Auto]
> CC6 memory region encryption [Auto]
> Location of private memory regions [Auto]
> System probe filter [Auto]
> Memory interleaving [Channel]
> Memory interleaving size [2 KB]
> Channel interleaving hash [Enabled]
> Memory Clear [Disabled]
> ACPI SLIT Distance Control [Auto]
> Overclock [Enabled]
> Memory Clock Speed [Auto]
> Tcl [Auto]
> Trcdrd [Auto]
> Trcdwr [Auto]
> Trp [Auto]
> Tras [Auto]
> Trc Ctrl [Auto]
> TrrdS [Auto]
> TrrdL [Auto]
> Tfaw Ctrl [Auto]
> TwtrS [Auto]
> TwtrL [Auto]
> Twr Ctrl [Auto]
> Trcpage Ctrl [Auto]
> TrdrdScL Ctrl [Auto]
> TwrwrScL Ctrl [Auto]
> Trfc Ctrl [Auto]
> Trfc2 Ctrl [Auto]
> Trfc4 Ctrl [Auto]
> Fail_CNT [5]
> ProcODT [Auto]
> Tcwl [Auto]
> Trtp [Auto]
> Trdwr [Auto]
> Twrrd [Auto]
> TwrwrSc [Auto]
> TwrwrSd [Auto]
> TwrwrDd [Auto]
> TrdrdSc [Auto]
> TrdrdSd [Auto]
> TrdrdDd [Auto]
> Tcke [Auto]
> Power Down Enable [Auto]
> Cmd2T [Auto]
> Gear Down Mode [Auto]
> CAD Bus Timing User Controls [Auto]
> CAD Bus Drive Strength User Controls [Auto]
> Data Bus Configuration User Controls [Auto]
> DFE Read Training [Enable]
> FFE Write Training [Auto]
> PMU Pattern Bits Control [Auto]
> Data Poisoning [Auto]
> DRAM ECC Symbol Size [Auto]
> DRAM ECC Enable [Auto]
> TSME [Auto]
> Data Scramble [Auto]
> Chipselect Interleaving [Auto]
> BankGroupSwap [Auto]
> BankGroupSwapAlt [Auto]
> Address Hash Bank [Auto]
> Address Hash CS [Auto]
> MBIST Enable [Disabled]
> IOMMU [Auto]
> Determinism Slider [Auto]
> cTDP Control [Auto]
> Fan Control [Auto]
> PSI [Auto]
> ACS Enable [Auto]
> Enable AER Cap [Auto]
> PCIe ARI Support [Auto]
> CLDO_VDDP Control [Auto]
> HD Audio Enable [Auto]
> SOC OVERCLOCK VID [0]
> Block PCIe Loopback [Auto]
> CRS Delay [6]
> CRS Limit [6]
> Ignore sideband [Disabled]
> Disable L1 w/a [Disabled]
> Disable BridgeDis [Disabled]
> Toggle RRC Enable [Disabled]
> IRQ sets BridgeDis [Disabled]
> PCIE RESET Control [Disabled]
> AMD XGBE Controller 0 [Auto]
> AMD XGBE Controller 1 [Auto]
> AMD XGBE Controller 2 [Auto]
> AMD XGBE Controller 3 [Auto]
> AMD XGBE Controller 4 [Auto]
> AMD XGBE Controller 5 [Auto]
> AMD XGBE Controller 6 [Auto]
> AMD XGBE Controller 7 [Auto]
> NTB Enable [Auto]


I can't see anything untoward in your settings... Sadly the only board I've had code 00 on was completely dead, so I can only wonder if perhaps you have some damage on your board or a bad solder joint somewhere. Did you inspect both sides of your board when you got it to make sure all was well? Sometimes there are obvious problems with solder.

Does anyone else have any ideas why this might happen intermittently?


----------



## crakej

nick name said:


> I was hoping the memory threshold tied to Infinity Fabric would have been closer to 4000+ , but I guess this isn't terrible.


This is un-tuned performance - this is what you'll get with XMP

I already run my 1xxx CPU at up to 3733c16 and 62ns latency (god I love this cpu!) so I'm guessing those who win the lottery will get better performance..... and those who tune their settings!

VERY excited!


----------



## ilmazzo

I'm on the 62ish too, we will see where we will end up with this zen 2 after 1usmus cure!


----------



## Synoxia

GSAT stress test pass 8900 seconds, but then random firefox crashes? LOL? Can anyone explain this?


----------



## Redwoodz

MacMus said:


> No it only happens sometimes on the first boot, but not always. PC stays ON, LCD shows 00, all fans are blowing at max speed. Nothing helps in this stage including replacing RAM, CPU except removing battery.
> 
> my RAM settings:
> 
> 
> [/code]





crakej said:


> I can't see anything untoward in your settings... Sadly the only board I've had code 00 on was completely dead, so I can only wonder if perhaps you have some damage on your board or a bad solder joint somewhere. Did you inspect both sides of your board when you got it to make sure all was well? Sometimes there are obvious problems with solder.
> 
> Does anyone else have any ideas why this might happen intermittently?


 After the latest Ageasa and Windows update I get overclocking shut-downs w/no bluescreen that leaves the mobo running and showing code 00 on my X470 Taichi. I just restart and everything is fine. Your overclock is not very stable, and your boot settings are not stable I would think


----------



## hazium233

Synoxia said:


> GSAT stress test pass 8900 seconds, but then random firefox crashes? LOL? Can anyone explain this?


I have had Firefox not play nice with Nvidia and Realtek drivers, mostly on 1809 and depending on FF version. But could also be you aren't quite stable. What other memory stress tests did you run?


----------



## MacMus

Redwoodz said:


> After the latest Ageasa and Windows update I get overclocking shut-downs w/no bluescreen that leaves the mobo running and showing code 00 on my X470 Taichi. I just restart and everything is fine. Your overclock is not very stable, and your boot settings are not stable I would think


I am not running OC only underclock .. i can run RAM test all day long..


----------



## nick name

MacMus said:


> I am not running OC only underclock .. i can run RAM test all day long..


Prove it. Run a test all day long.


----------



## MacMus

nick name said:


> Prove it. Run a test all day long.


sure i did run Aida memory test whole day. Can u recommend some setting or SW i should run with ?


----------



## nick name

MacMus said:


> sure i did run Aida memory test whole day. Can u recommend some setting or SW i should run with ?


Sorry, I was just joking around.


----------



## UltraMega

Ram question here:

I'm thinking about getting a Ryzen 2600 with a GIGABYTE B450M DS3H mobo.

https://www.newegg.com/p/N82E16813145083


One of the fastest ram kits on the QVL is this: F4-3200C14D-16GFX 

https://www.newegg.com/g-skill-16gb...=flare X&cm_re=flare_X-_-20-232-530-_-Product

Ram QVL: http://download.gigabyte.us/FileList/Memory/mb_memory_b450m-ds3h_summit.pdf


Just wondering if there is any cheaper 3200mhz ram I can get, as this will be a budget build. This ram is a pretty good deal already but there are so many variants, it more than I know how to sort through. Looking to get the cheapest decent/reliable 3200mhz ram that will work with XMP setting on this board. 

Any suggestion is appreciated!

Edit: would this ram work? https://www.newegg.com/g-skill-16gb...=flare X&cm_re=flare_X-_-20-232-767-_-Product


----------



## hazium233

UltraMega said:


> Ram question here:
> 
> I'm thinking about getting a Ryzen 2600 with a GIGABYTE B450M DS3H mobo.
> 
> https://www.newegg.com/p/N82E16813145083
> 
> 
> One of the fastest ram kits on the QVL is this: F4-3200C14D-16GFX
> 
> https://www.newegg.com/g-skill-16gb...=flare X&cm_re=flare_X-_-20-232-530-_-Product
> 
> Ram QVL: http://download.gigabyte.us/FileList/Memory/mb_memory_b450m-ds3h_summit.pdf
> 
> 
> Just wondering if there is any cheaper 3200mhz ram I can get, as this will be a budget build. This ram is a pretty good deal already but there are so many variants, it more than I know how to sort through. Looking to get the cheapest decent/reliable 3200mhz ram that will work with XMP setting on this board.
> 
> Any suggestion is appreciated!
> 
> Edit: would this ram work? https://www.newegg.com/g-skill-16gb...=flare X&cm_re=flare_X-_-20-232-767-_-Product


At least GSkill lists your board in their QVL.

Might be nice to know what IC is really in it. Scrolling through the reviews, one guy says Hynix, another Spectek (which is Micron), and another Micron B-die.


----------



## Hequaqua

I believe the Flare X 3200CL14 is Samsung. I have that set in my son's rig.

Here is a link to search for Samsung B-Die:

https://benzhaomin.github.io/bdiefinder/

It seems to be the best...or was. I know I have had good luck with both my sets. The Flare X and the one listed in my sig(current timings are in there as well).

Here is TM5 20 cycles:



Spoiler


----------



## Xinoxide

I've got this kit with my Ryzen 2700 at 4200MHz: https://www.gskill.com/en/product/f4-3600c16d-16gtzr

Its the Trident Z RGB 3600MHz kit. Currently running 3200MHz.

single Rank - Bdie 8.9u

I just upped my vSOC to 1.08 after a rando 0xD1 bsod while Idle. 

All my BSODS so far have been IMC related and the kit works upwards of 4000MHz on a friends system.

Timings I can take care of, I am more curious about what I can do with other settings to get better IMC stability, Not questioning the RAM itself.

I've been running them at 3200MHz 14-15-15-28 1.35v for the surefire stability while playing things.


----------



## Keith Myers

The Flare-X CL14 kit is definitely B-Die. Should be able to run it at 3466Mhz at the rated timings with no issues. If it fails a RAM test at those clocks, then change to 14-15-14-34 for timings. Get the Ryzen DDR4 RAM Calculator for better sub-timings and settings for that memory.


----------



## Wuest3nFuchs

hi all together !

Got the Gskill 16gb kit F4-3200C14-8GFX having K4A8G085WB-BCPB chips on it ! 



Are these K4A8G085WB-BCPB good ones based on the part number?
One thing i noticed after placing a external tempsensor...they already have one build in ! THATS SO NICE !


*3 hrs GSAT stable* [with 2 cold boots and one warm restart after an hour of BFV on 64p Server]


*Karhu ~4000%* stable


Was 7000% the goal for karhu ,or 4000% ?


----------



## nick name

Wuest3nFuchs said:


> hi all together !
> 
> Got the Gskill 16gb kit F4-3200C14-8GFX having K4A8G085WB-BCPB chips on it !
> 
> 
> 
> Are these K4A8G085WB-BCPB good ones based on the part number?
> One thing i noticed after placing a external tempsensor...they already have one build in ! THATS SO NICE !
> 
> 
> *3 hrs GSAT stable* [with 2 cold boots and one warm restart after an hour of BFV on 64p Server]
> 
> 
> *Karhu ~4000%* stable
> 
> 
> Was 7000% the goal for karhu ,or 4000% ?


From Karhu's FAQ.

Q: How much coverage is enough?
A: Error detection rates by test coverage*:

Coverage ≤ 100 %: 64,57 %
Coverage ≤ 200 %: 75,79 %
Coverage ≤ 400 %: 82,68 %
Coverage ≤ 800 %: 91,34 %
Coverage ≤ 1600 %: 96,06 %
Coverage ≤ 3200 %: 98,03 %
Coverage ≤ 6400 %: 99,41 %


----------



## Wuest3nFuchs

nick name said:


> From Karhu's FAQ.
> 
> 
> 
> Q: How much coverage is enough?
> 
> A: Error detection rates by test coverage*:
> 
> 
> 
> Coverage ≤ 100 %: 64,57 %
> 
> Coverage ≤ 200 %: 75,79 %
> 
> Coverage ≤ 400 %: 82,68 %
> 
> Coverage ≤ 800 %: 91,34 %
> 
> Coverage ≤ 1600 %: 96,06 %
> 
> Coverage ≤ 3200 %: 98,03 %
> 
> Coverage ≤ 6400 %: 99,41 %


thank you nick name 

Gesendet von meinem SM-G950F mit Tapatalk


----------



## nick name

Wuest3nFuchs said:


> thank you nick name
> 
> Gesendet von meinem SM-G950F mit Tapatalk


No problem. I have it bookmarked because I forget.


----------



## Martin778

Guys, I bought a 3200 CL14 Bdie FlareX kit for the upcoming Zen2 but I also want to try 32GB 3200C16 E-Die from Micron. Anyone knows which kit has these? There is a website with B-Die finder but so far nothing for E-Die.


----------



## BLUuuE

Martin778 said:


> Guys, I bought a 3200 CL14 Bdie FlareX kit for the upcoming Zen2 but I also want to try 32GB 3200C16 E-Die from Micron. Anyone knows which kit has these? There is a website with B-Die finder but so far nothing for E-Die.


Recent 3000 15-16-16, 3200 16-18-18 and 3600 16-18-18 Ballistix kits should use Micron Rev. E.


----------



## Martin778

Yep, 'should'  I'm not the kind of guy to order 5 kits, bin 1 and return 4. I don't understand the price difference which is insane as the availability of these kits in EU is abysmal, take a look:
2x16 Ballistix LT 3200 C16:
a) White https://tweakers.net/pricewatch/1300874/crucial-ballistix-sport-lt-bls2k16g4d32aesc.html
b) Red https://tweakers.net/pricewatch/1300950/crucial-ballistix-sport-lt-bls2k16g4d32aese.html
c) Grey https://tweakers.net/pricewatch/1300940/crucial-ballistix-sport-lt-bls2k16g4d32aesb.html

And then we have the Ballistix AT which I have no clue what they are, Crucial's site doesn't make it any clearer 
https://tweakers.net/pricewatch/1300850/crucial-ballistix-sport-at-bls2k16g4d32aest.html

Finally Ballistix Elite for an absolutely crazy price: 
https://tweakers.net/pricewatch/1295738/crucial-ballistix-elite-ble2k16g4d32aeea.html

That said, if I want there is one single B-Die TZ RGB 3200C14 kit I can grab but it costs 350 euro....


----------



## BLUuuE

Martin778 said:


> Yep, 'should'  I'm not the kind of guy to order 5 kits, bin 1 and return 4. I don't understand the price difference which is insane as the availability of these kits in EU is abysmal, take a look:
> 2x16 Ballistix LT 3200 C16:
> a) White https://tweakers.net/pricewatch/1300874/crucial-ballistix-sport-lt-bls2k16g4d32aesc.html
> b) Red https://tweakers.net/pricewatch/1300950/crucial-ballistix-sport-lt-bls2k16g4d32aese.html
> c) Grey https://tweakers.net/pricewatch/1300940/crucial-ballistix-sport-lt-bls2k16g4d32aesb.html
> 
> And then we have the Ballistix AT which I have no clue what they are, Crucial's site doesn't make it any clearer
> https://tweakers.net/pricewatch/1300850/crucial-ballistix-sport-at-bls2k16g4d32aest.html
> 
> Finally Ballistix Elite for an absolutely crazy price:
> https://tweakers.net/pricewatch/1295738/crucial-ballistix-elite-ble2k16g4d32aeea.html
> 
> That said, if I want there is one single B-Die TZ RGB 3200C14 kit I can grab but it costs 350 euro....


https://redd.it/bq4m52
https://redd.it/bpybh1
https://redd.it/bqnq0m
https://redd.it/be9fou

You can also check the code after the period (.) in the model number if can get the kit in store. 
For example, BLS16G4D30AESC.*M8FE* means it's Micron 8Gbit Rev. E.


----------



## hazium233

Martin778 said:


> Yep, 'should'  I'm not the kind of guy to order 5 kits, bin 1 and return 4. I don't understand the price difference which is insane as the availability of these kits in EU is abysmal, take a look:
> 2x16 Ballistix LT 3200 C16:
> a) White https://tweakers.net/pricewatch/1300874/crucial-ballistix-sport-lt-bls2k16g4d32aesc.html
> b) Red https://tweakers.net/pricewatch/1300950/crucial-ballistix-sport-lt-bls2k16g4d32aese.html
> c) Grey https://tweakers.net/pricewatch/1300940/crucial-ballistix-sport-lt-bls2k16g4d32aesb.html
> 
> And then we have the Ballistix AT which I have no clue what they are, Crucial's site doesn't make it any clearer
> https://tweakers.net/pricewatch/1300850/crucial-ballistix-sport-at-bls2k16g4d32aest.html
> 
> Finally Ballistix Elite for an absolutely crazy price:
> https://tweakers.net/pricewatch/1295738/crucial-ballistix-elite-ble2k16g4d32aeea.html
> 
> That said, if I want there is one single B-Die TZ RGB 3200C14 kit I can grab but it costs 350 euro....


AT is basically an LT with a different heat spreader, made for the TUF Alliance deal.


----------



## Martin778

Considering no E-die 32GB kits are available from the shops I trust, or are very expensive for what they are, I grabbed the last 32GB 3200C14 kit my trusted shop had for 280eu.


----------



## doggymad

I picked up the TZ 32GB (2x16) 3200C14 RAM in UK from Newegg, even with the 2 day world delivery plus taxes, etc... it only came in at £250 which was far cheaper than anywhere else I could find. I’m pairing it with the 3900X on Monday. I ordered yesterday, they sent tracking straight away and it’ll arrive tomorrow. Usually NewEgg works out more expensive but in this case was £50 cheaper! Def B-die too!


----------



## Martin778

Ok, got the 2x16 3200C14 kit. On the Aorus B450 PRO F.40 the XMP is a no go, no boot. Lowering the frequency to 3000MHz does the trick, above that it seems to hit a wall. 3000MHz passed 125% memtest.
Still, 3000 CL14-14-14-34 on 32 gigs and cheapo board doesn't seem that bad.

So far the only thing I see is different between the normal Intel XMP based kit and the FlareX is that the FlareX has preset SOC voltage(?).


----------



## rares495

[email protected](for this test)---3200Mhz-C16-18-18-36-1T---1.4v---SOC 1.1v---BIOS 1.70---HCI---6.5 Hours/1000%--AX4U300038G16-SBG

2x8GB of ADATA Gammix D10(Hynix MFR) rated for XMP 3000 16-18-18-18-36-55 1.35V. Information about these DIMMs is scarce. I suspect it's because this memory sucks and nobody buys it.

tRFC should have been 480 but MSI boards are dumb and never apply that setting the first time. Should be stable with 480 and maybe some other timings can go a bit lower. Perhaps I'll work on it some more and post an update. Any advice would really be appreciated.

UPDATE: They seem to be stable at 3333 1.44V 16-18-18-36 58. Need to do a long HCI run but no errors after 3 minutes, while every other config wouldn't last 20 seconds, so I'm hopeful.


----------



## hazium233

^ Your RAS is pretty low. 16+18+10=44, or 16+18+8=42

--

Does anybody run HCI Memtest with more instances than threads? Someone elsewhere had mentioned that their transfer rate shows higher when they do this, and so I tried it briefly, and transfer rate appeared like it might have been faster with 24 threads than 12 on my 1600. Curious if this may just be an artifact with the helper calculation, or if it might actually run faster for a real test. Don't know how this would affect the actual results.


----------



## DragonQ

Anyone in this thread with an X370 or X470 ASRock motherboard and a Ryzen 3000 series CPU? Looks like they all have AGESA ComboPI 1.0.0.1 right now and various people including myself are struggling to run RAM any higher than 3200 MT/s with any settings.


----------



## BLUuuE

hazium233 said:


> ^ Your RAS is pretty low. 16+18+10=44, or 16+18+8=42
> 
> --
> 
> Does anybody run HCI Memtest with more instances than threads? Someone elsewhere had mentioned that their transfer rate shows higher when they do this, and so I tried it briefly, and transfer rate appeared like it might have been faster with 24 threads than 12 on my 1600. Curious if this may just be an artifact with the helper calculation, or if it might actually run faster for a real test. Don't know how this would affect the actual results.


Divide the speed by the number of threads to get the average speed of each instance/thread.

Running more threads than your CPU has isn't actually faster.










Settings: Stop at 10%



Code:


40.75 / 6 = 6.79

81.69 / 12 = 6.8075


----------



## hazium233

BLUuuE said:


> Divide the speed by the number of threads to get the average speed of each instance/thread.
> 
> Running more threads than your CPU has isn't actually faster.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Settings: Stop at 10%
> 
> 
> 
> Code:
> 
> 
> 40.75 / 6 = 6.79
> 
> 81.69 / 12 = 6.8075


I didn't think to divide it. I was wondering how it was arriving at that speed.


----------



## blair

C6H 7106 Bios,
3700X
vCore Voltage offset at -0.05-0.075 (i think 0.062 atm.. unsure can't recall)

4x 8gb B-Die Cl16 3600 1.44v

tested to 600% with attached Timings, all manually configured except for Trfc2/4


----------



## BLUuuE

hazium233 said:


> I didn't think to divide it. I was wondering how it was arriving at that speed.





Code:


tested_ram = total_coverage / 100 * ram
speed = tested_ram / elapsed_time

e.g.
tested_ram = 61.8 / 100 * 6000 = 3708
speed = 3708 / 91 = 40.747... = 40.75

https://github.com/integralfx/MemTestHelper/blob/master/MemTestHelper2/MainWindow.xaml.cs#L112


----------



## Unknownm

The computer shop in my area is opening a new location with door crashers deals and one of these deals is my ram for $69.99, meaning I will have 4x8GB (instead of 2x8GB) which is great! Just worried about ram stability.

Does anyone know what settings have to be edited when adding 4x ram sticks of same speed/model? 
DRAM Calculator only shows lower "procODT" "RTT_PARK" when switching from 2 to 4 DIMM Modules. However maybe out of experience someone knows better?

Thanks


----------



## hazium233

BLUuuE said:


> Code:
> 
> 
> tested_ram = total_coverage / 100 * ram
> speed = tested_ram / elapsed_time
> 
> e.g.
> tested_ram = 61.8 / 100 * 6000 = 3708
> speed = 3708 / 91 = 40.747... = 40.75
> 
> https://github.com/integralfx/MemTestHelper/blob/master/MemTestHelper2/MainWindow.xaml.cs#L112


Yeah. I hadn't timed the runs before, it was showing ~50% faster speed at 24 threads instead of 12 and I wondered if this wasn't something with data set size or stalls, but with timing it to a percent that was indeed slower.

Maybe related, but I never understood the utility of the total coverage number summing all of the coverages, unless just used for stopping the test. I would have thought that say for 8GB divided into four instances of 2000MB, when all four instances are at 100%, total coverage would likewise really be 100%. HCI's page was vague about confidence at whatever coverage, and how that actually worked across multiple instances.


----------



## BLUuuE

hazium233 said:


> Yeah. I hadn't timed the runs before, it was showing ~50% faster speed at 24 threads instead of 12 and I wondered if this wasn't something with data set size or stalls, but with timing it to a percent that was indeed slower.
> 
> Maybe related, but I never understood the utility of the total coverage number summing all of the coverages, unless just used for stopping the test. I would have thought that say for 8GB divided into four instances of 2000MB, when all four instances are at 100%, total coverage would likewise really be 100%. HCI's page was vague about confidence at whatever coverage, and how that actually worked across multiple instances.


If you reach 100% total coverage, that means you've tested 8000MB.

When you have 4 instances at 100%, the average coverage would be 100%.

I think I originally had it as average coverage, but some instances can go a bit faster than others so it made it a bit confusing for the estimated time to X%. 
I could maybe add a switch to let the user toggle between total coverage/speed and average coverage/speed, but it's not really necessary imo.


----------



## hazium233

BLUuuE said:


> If you reach 100% total coverage, that means you've tested 8000MB.
> 
> When you have 4 instances at 100%, the average coverage would be 100%.
> 
> I think I originally had it as average coverage, but some instances can go a bit faster than others so it made it a bit confusing for the estimated time to X%.
> I could maybe add a switch to let the user toggle between total coverage/speed and average coverage/speed, but it's not really necessary imo.


No, toggle isn't necessary. If I made a request it would just be for an extra digit in the coverage field. But that isn't a big deal, it is helpful as is. Thank you.

It isn't a big deal, but I don't understand HCI's numbers then. I would have thought that in above example, 100% total coverage would mean I have tested whatever amount is in each instance, eg 2000MB as each instance would only be showing ~25% or so.


----------



## glnn_23

Running 3900x in CH7. 
2 x 8Gb TridentZ 4266 @ 3733c14-15-14 28 1T 
1hr gsat in Win10 and have run Ramtest 5000% 
Vdimm 1.4v, Soc 1.1v in bios.


----------



## rares495

rares495 said:


> [email protected](for this test)---3200Mhz-C16-18-18-36-1T---1.4v---SOC 1.1v---BIOS 1.70---HCI---6.5 Hours/1000%--AX4U300038G16-SBG
> 
> 2x8GB of ADATA Gammix D10(Hynix MFR) rated for XMP 3000 16-18-18-18-36-55 1.35V. Information about these DIMMs is scarce. I suspect it's because this memory sucks and nobody buys it.
> 
> tRFC should have been 480 but MSI boards are dumb and never apply that setting the first time. Should be stable with 480 and maybe some other timings can go a bit lower. Perhaps I'll work on it some more and post an update. Any advice would really be appreciated.
> 
> UPDATE: They seem to be stable at 3333 1.44V 16-18-18-36 58. Need to do a long HCI run but no errors after 3 minutes, while every other config wouldn't last 20 seconds, so I'm hopeful.





hazium233 said:


> ^ Your RAS is pretty low. 16+18+10=44, or 16+18+8=42
> 
> --
> 
> Does anybody run HCI Memtest with more instances than threads? Someone elsewhere had mentioned that their transfer rate shows higher when they do this, and so I tried it briefly, and transfer rate appeared like it might have been faster with 24 threads than 12 on my 1600. Curious if this may just be an artifact with the helper calculation, or if it might actually run faster for a real test. Don't know how this would affect the actual results.


Turns out they weren't stable even at 3200. Passed 1000% HCI but crashed during a GTA V session. Kinda losing the little bit of faith I had in these sticks.


----------



## ssateneth

If only AMD let us change tREFI... Could easily shave off another 5% of latency and increase bandwidth 5%
Also, give us RTL's and IOL's


----------



## hazium233

rares495 said:


> Turns out they weren't stable even at 3200. Passed 1000% HCI but crashed during a GTA V session. Kinda losing the little bit of faith I had in these sticks.


I didn't notice before, but do you need so much SOC voltage for 3200 (or 3333 for that matter)? Over 1.1v probably isn't necessary on Zen+ unless at very high speed (even then, many scale negatively). For 3200, I would think that closer to 1v would possibly work, assuming ProcODT and RTT is correct, or the timings aren't overly aggressive.

Does it boot with lower ProcODT? For example my ram will boot 3200 at anything from 43 to 60 ohms (didn't test higher), Auto sets 60 and it is very hard to get any set of timings stable at reasonable SOC, but at 48 it is a lot easier.

If you are tightening all the tertiary and secondaries, you might end up needing to loosen RCDRD, RP, or both.

RAS>=RCDRD+CAS+RTP+/-2 may make your life easier. The bare minimum RAS>=RCDRD+CAS+4

Adjusting RAS leads to an adjustment to RC since RC=RAS+RP

Calculator has RTP=12. I don't know what MFR really likes, but tighter RTP doesn't have a drastic effect on performance, and lowering it may need more vDIMM, or lower CAD drive strength resistance. Effect would be from RAS or RC changes.

Maybe try something like this at 3200

CAS 16
RCDWR 18
RCDRD 19
RP 19
RAS 43
RC 62

RTP 8

RFC 496

With SOC lowered to more like 1.025v or less, testing alternative/lower ProcODT.

Alternatively, you may have to loosen RDRDSCL or WRWRSCL from 4 to 6, I don't know how low MFR likes these.


----------



## christoph

hazium233 said:


> I didn't notice before, but do you need so much SOC voltage for 3200 (or 3333 for that matter)? Over 1.1v probably isn't necessary on Zen+ unless at very high speed (even then, many scale negatively). For 3200, I would think that closer to 1v would possibly work, assuming ProcODT and RTT is correct, or the timings aren't overly aggressive.
> 
> Does it boot with lower ProcODT? For example my ram will boot 3200 at anything from 43 to 60 ohms (didn't test higher), Auto sets 60 and it is very hard to get any set of timings stable at reasonable SOC, but at 48 it is a lot easier.
> 
> If you are tightening all the tertiary and secondaries, you might end up needing to loosen RCDRD, RP, or both.
> 
> RAS>=RCDRD+CAS+RTP+/-2 may make your life easier. The bare minimum RAS>=RCDRD+CAS+4
> 
> Adjusting RAS leads to an adjustment to RC since RC=RAS+RP
> 
> Calculator has RTP=12. I don't know what MFR really likes, but tighter RTP doesn't have a drastic effect on performance, and lowering it may need more vDIMM, or lower CAD drive strength resistance. Effect would be from RAS or RC changes.
> 
> Maybe try something like this at 3200
> 
> CAS 16
> RCDWR 18
> RCDRD 19
> RP 19
> RAS 43
> RC 62
> 
> RTP 8
> 
> RFC 496
> 
> With SOC lowered to more like 1.025v or less, testing alternative/lower ProcODT.
> 
> Alternatively, you may have to loosen RDRDSCL or WRWRSCL from 4 to 6, I don't know how low MFR likes these.



you going to need like 1.12 or 1.14v for the SoC for that ram speed, at least 1.1v for 3200 MHz


----------



## hazium233

christoph said:


> you going to need like 1.12 or 1.14v for the SoC for that ram speed, at least 1.1v for 3200 MHz


An R5 2600 needs 1.1v SOC for 3200MT/s? That seems high compared with shared results, how did you determine this?


----------



## Unknownm

1.075v SoC with 1.44v DRAM @ 3466 mhz on my setup. 

Sent from my SM-G960W using Tapatalk


----------



## kamil234

1.1v SOC 1.45v RAM

3600CL14 - Ryzen 3900x on Gigabyte AORUS Elite


----------



## christoph

hazium233 said:


> An R5 2600 needs 1.1v SOC for 3200MT/s? That seems high compared with shared results, how did you determine this?



cuz it depends on the CPU and not the actual voltage, you have to test for yourself, but mostly what I have seem around it needs 1.1v for 3200 MHz

and it depends too if you're OCing that cpu


----------



## Dr. Vodka

Micron E-die is awesome.

This is 4x16GB (dual rank) sticks doing 3400MHz 14-18-14-32 1T on 1st gen Ryzen. Will do more stress testing, but it's looking nice so far.


edit: updated the picture as I was using an old version of Thaiphoon Burner that didn't properly recognize the ICs. I was also using 1.42v vDIMM so I updated that too.











One TM5 run in that screenshot, and an overnight run of bootable HCI memtest


Before this I had 2x8GB TridentZ 3466MHz B-die sticks, I also had a very hard time stabilizing anything above 3400MHz. Probably the board being T-topology or my 1700's IMC/fabric not wanting to go any higher. Anything above 3400MHz with these 4 sticks results in crashing or not POSTing. Anyway, I'm thrilled with the results.



It's insane for the cost, apart from Ryzen's cranky IMC seemingly loving these ICs as much as B-die.


----------



## Kitilan

Dr. Vodka said:


> Micron E-die is awesome.
> 
> This is 4x16GB (dual rank) sticks doing 3400MHz 14-18-14-32 1T on 1st gen Ryzen. Will do more stress testing, but it's looking nice so far.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> One TM5 run in that screenshot, and an overnight run of bootable HCI memtest
> 
> 
> Before this I had 2x8GB TridentZ 3466MHz B-die sticks, I also had a very hard time stabilizing anything above 3400MHz. Probably the board being T-topology or my 1700's IMC/fabric not wanting to go any higher. Anything above 3400MHz with these 4 sticks results in crashing or not POSTing. Anyway, I'm thrilled with the results.
> 
> 
> 
> It's insane for the cost, apart from Ryzen's cranky IMC seemingly loving these ICs as much as B-die


what is the memory voltage?

Отправлено с моего SM-G930F через Tapatalk


----------



## Dr. Vodka

Kitilan said:


> what is the memory voltage?
> 
> Отправлено с моего SM-G930F через Tapatalk



It's in the picture, forgot to put it in the post.


1.42v vDIMM, +130% current
1.1v vSOC, no LLC


----------



## Kitilan

oh, yeah, didn't notice. thx









Отправлено с моего SM-G930F через Tapatalk


----------



## Martin778

How is this? 2x16GB @ 3733MHz 16-16-16-36 2T 1.45Vdimm 1.15V SOC.
Haven't touched secondary timings yet, this is simply bumped up 3200C14 XMP profile and tweaked primary timings.


----------



## christoph

Martin778 said:


> How is this? 2x16GB @ 3733MHz 16-16-16-36 2T 1.45Vdimm 1.15V SOC.
> Haven't touched secondary timings yet, this is simply bumped up 3200C14 XMP profile and tweaked primary timings.



seems logic, no problems


----------



## rdr09

Martin778 said:


> How is this? 2x16GB @ 3733MHz 16-16-16-36 2T 1.45Vdimm 1.15V SOC.
> Haven't touched secondary timings yet, this is simply bumped up 3200C14 XMP profile and tweaked primary timings.


That looks great. Very nice temps. If you game the temp should be similar. Are you going to figure out the boost to 4.2 or higher?


----------



## gerardfraser

Since I been testing 3600X ,memory works great.Here is one test CL16 4200Mhz while testing a CPU overclock for stability.


----------



## Martin778

rdr09 said:


> Martin778 said:
> 
> 
> 
> How is this? 2x16GB @ 3733MHz 16-16-16-36 2T 1.45Vdimm 1.15V SOC.
> Haven't touched secondary timings yet, this is simply bumped up 3200C14 XMP profile and tweaked primary timings.
> 
> 
> 
> That looks great. Very nice temps. If you game the temp should be similar. Are you going to figure out the boost to 4.2 or higher?
Click to expand...

Sorry for typing on mobile!
I'm waiting for new BIOSes as Ryzen Balanced seems harsh on the CPU in terms of downlocking. I haven't touched any CPU options yet, with fan swapped (Noctua 12x25) ML360R AiO my all core boost is ~4125-4200 in gams and 4050-4100 in synthetic stress tests.


----------



## CubanB

I have a choice between the Corsair LPX 3200mhz C16 (Hynix) that I currently have (new in box) or I can return them and get my money back within the return window.

And then get some Micron E die.. 3200mhz C16 Crucial Ballstix.. the only catch is that I wouldn't receive them for 2-3 weeks due to shipping time due to buying internationally. I don't mind waiting though, it's more about how much the benefit would be.

Do you guys think this would be worth it? B Die is out of the question, I want to run 64GB and it's just too expensive. But the Ballastix is pretty much the same price as the Corsair (when bought locally with ebay vouchers)..

I've never OC'd ram with Ryzen before. But if I use the RAM calculator and tried to find the sweet spot for 3700X or 3900X.. would I see extra benefit from the Micron E die? Could I expect to run either of these RAM kits for a few years with decent 24/7 stability? I appreciate any replies as I need to make this choice within the next day or two (due to the 2-3 week wait).


----------



## Martin778

My 2x16GB 3733 C16 setup also passed with SOC Voltage lowered to 1.11V. The IMC on Zen2 is crazy.


----------



## lordzed83

This not bad read shame no tight timings test but 
https://lab501.ro/procesoare-chipseturi/amd-ryzen-3000-part-iv-ddr4-latenta-vs-frecventa


----------



## pantsaregood

Martin778 said:


> My 2x16GB 3733 C16 setup also passed with SOC Voltage lowered to 1.11V. The IMC on Zen2 is crazy.


Is that just an XMP profile? tRFC looks really loose. Maybe you can push the timings down with some voltage. I'd like to see how Zen 2 latency behaves with FCLK at 1866 MHz.


----------



## Martin778

With 3900X, otherwise the same settings:









It's just an updooted 3200C14 XMP profile.


----------



## Vins

MSI B450M Pro-M2 with Corsair VS550 PSU (HEC board not the faulty older ones!!). Latest BIOS with Ryzen 3000 cpus support

Ryzen 1600x @3.9 Ghz (vcore 1.3250)

2x8GB HyperX Predator 3000 KHX3000C15D4/8GX (H5AN8G8NCJR-UHC)
XMP 15-17-17-36 3000 Mhz

@3400 16-19-19-44 superstable with 1000% HCI, several hours of prime95 and RealBench stress tests.

vdram 1.40, soc 1.075
Termination Block settings (ProcODT 53.3, 34, ODT Off, Park 48)
CadBus (24,30,24,24)

The HyperXs can boot @3533 but i still havent found stable settings. Will update if i succeed


----------



## ilmazzo

Martin778 said:


> With 3900X, otherwise the same settings:
> 
> It's just an updooted 3200C14 XMP profile.


I would like to see where zen 2 can go down on latency tough...... I would like 60ns or lower instead of pleanty of bandwidth but that's just me and my gaming focus


----------



## Martin778

I really doubt it does much if anything as they stuffed the CPU with enormous amounts of cache anyways.


----------



## hazium233

^ "Gamecache"


----------



## Streetdragon

Still testing for now.
I get prooblems with CAS14 and T1. So 2T it is now:
14 15 14 21 38 2T 4*8Gigs 1,43V
With a bit tuned subtimings. Gear down mode off

What do you think?


----------



## dev1ance

Rather than running 2T, you could run 1T+GearDownMode which acts more like 1.5T. A good compromise.


----------



## Streetdragon

nope not stable


----------



## nick name

The Stilt recently mentioned that increased CLDO_VDDP voltage could help with the new CPUs. It seems that it's no longer just for working out memory holes with lowering it.


----------



## DragonQ

nick name said:


> The Stilt recently mentioned that increased CLDO_VDDP voltage could help with the new CPUs. It seems that it's no longer just for working out memory holes with lowering it.


Interesting thing I noticed is that increasing VDDP in my X470 Taichi BIOS actually increases CLDO_VDDG according to Ryzen Master. THe only way I could get my memory stable at XMP (3000 MT/s) was to set that to 0.95 V. CLDO_VDDP still reads as 0.9 V.

On my wife's B450 Gaming Carbon Pro AC, XMP is stable at stock. However, that board's stock voltages for XMP are exactly the same as what I set manually on my board: 0.95 V for CLDO_VDDG and 0.9 V for CLDO_VDDP.


----------



## gamervivek

Streetdragon said:


> nope not stable


2T gives you better results than 1T+GDM stable settings?


----------



## Streetdragon

gamervivek said:


> 2T gives you better results than 1T+GDM stable settings?


slightly better, but could be in margin of error


----------



## Dr. Vodka

Tuned my 4x16GB DR Micron rev. E sticks a bit more












This is as far as they'll go on my 1700.


----------



## Kukielka

My results on my 3900X.
2xF4-3200C14-8GTZR

Even with having 4 sticks installed this result looks pretty nice so far.
I'll post more later, I'll try out the new Bios first tho. Let's see if I can push it to 3733CL14 
(And lets hope the new Bios fixes the problems I have with ocing the 3900x itself. )


----------



## 1usmus

* July 29, I will introduce to the world new DRAM Calculator for Ryzen 1.6.0 *

You will receive full support for Zen 2, X570, updated presets, new features, training tips for x399, and of course the new version of MEMbench (Custom and Random latency tests).
Stay in touch


----------



## Wuest3nFuchs

1usmus said:


> * July 29, I will introduce to the world new DRAM Calculator for Ryzen 1.6.0 *
> 
> 
> 
> You will receive full support for Zen 2, X570, updated presets, new features, training tips for x399, and of course the new version of MEMbench (Custom and Random latency tests).
> 
> Stay in touch


THX!!!!
need to look into it, but im still on a 2700x maybe ryzen 4000 for me next .

Gesendet von meinem SM-G950F mit Tapatalk


----------



## kazablanka

https://browser.geekbench.com/v4/cpu/14047048


----------



## os2wiz

I have 32GB dual rank memory kit running at 3600mhz CL16-16-17-17-3-59 with gear down enabled. I am unsure of what is best for performance with dual rank memory as far as bank group swap and BGS alt. I have a Ryzen 3900X on an MSI X570 MEG ACE motherboard. I also have questions on iother advanced memory settings. I have found Ryzen Dram Calculator to be of zero assistance in fidning optimum settings. Their so-called "safe settings" have most often led to system hangs and me having to hit the clear cmos button. Any guidance from someone who has dual-rank dimms installed would be appreciated. Note I am not asking for theoretical postulations, but practical recommendations based on my case scenario and first hand experience. Thank you.


----------



## Martin778

Same question as above but now running 16-16-16-36-48 2T


----------



## Alpi

R5 3600, Cr6Hero, 2x8 TridentZ 3200c15 @ 3600c16. Vdimm : 1,37 - Vsoc : 1,0125
Y-cruncher succeed with 14Gb mem load @ my ss.


----------



## alefim

3666 CL 14


----------



## ilmazzo

alefim said:


> 3666 CL 14


suicide run?

vdram voltage?


----------



## Dphotog

Currently running 3900x

I hit my goal of 3733mhz cl14 1866 IF at the cost if high voltage 1.51v

My tests showed that could also run 3666mhz cl 14 1833 IF 1.47volt.

Mind you my only true test was benching was through shadow of the tomb raider
I've read 1.5v seems to be the max by some people and wanted to head your thoughts if 1.51volt is going to really end my rams life. Below is what I'm using.

https://pcpartpicker.com/product/2F...-x-16-gb-ddr4-3200-memory-f4-3200c14d-32gtrsm


----------



## Martin778

That's too much voltage IMO, I needed 1.41V to run 3733 on MSI Godlike, also 2x16GB B-Die's.


----------



## Aretak

1usmus said:


> * July 29, I will introduce to the world new DRAM Calculator for Ryzen 1.6.0 *
> 
> You will receive full support for Zen 2, X570, updated presets, new features, training tips for x399, and of course the new version of MEMbench (Custom and Random latency tests).
> Stay in touch


Thanks for your hard work. Seems it's available to download now from TechPowerUp. Used it to get some numbers for 3600MHz on my new 3700X and it seems to be working a treat (though I've only tried the Safe preset so far). Running four sticks of B-die on a Crosshair VI Hero and it passes some basic stress testing with Memtest at least. Have to see how it holds up under extended pressure later, then tighten some more if so.










Considering I could never, ever get anything above 3466MHz stable enough to pass even a minute of Memtest with this board and the couple of Zen+ chips I had, it's already an improvement.


----------



## nick name

Dphotog said:


> Currently running 3900x
> 
> I hit my goal of 3733mhz cl14 1866 IF at the cost if high voltage 1.51v
> 
> My tests showed that could also run 3666mhz cl 14 1833 IF 1.47volt.
> 
> Mind you my only true test was benching was through shadow of the tomb raider
> I've read 1.5v seems to be the max by some people and wanted to head your thoughts if 1.51volt is going to really end my rams life. Below is what I'm using.
> 
> https://pcpartpicker.com/product/2F...-x-16-gb-ddr4-3200-memory-f4-3200c14d-32gtrsm


It's not too much voltage if it's what is needed to run the speed and timings. Samsung b-dies can tolerate a lot of voltage and 1.5V daily isn't a problem. There are many knowledgeable folks that run their b-die kits above that daily.


----------



## DeathAngel

*Latency bad?!*

I need some help guys. I have a B450M Mortar with a 3700x on the latest 1.80 BIOS with AGESA 3ab, 2 x 16 GB HyperX Micron E-die 3200c18 1.2V RAM.

Trying to get 3600C16 running, for IF clock. I have used the new calculator and can input all the values except tRCDRD (21 instead of 17), tRC (62 instad of 56), tRTP (12 instead of 13, goes to 14 when I input 13, odd even thing for the BIOS?). Some things like the tWRRD value were lower (2 instead of 4) in the "auto" configuration, same with tRDRDDD (4 auto vs 5 calc) and tWRWRDD (6 auto vs 7 calc). Is that important?

But my main problem is that all of that tweaking doesn't do a lot for my latencies, AIDA64 still show 80.5 ns, where that one AMD slide had 69ns and a lot of people here with a similar setup get 70 to 75ns. What am I missing? This is my first Ryzen rig btw, read a lot but still noob-ish I guess. Is the tRCDRD and tRC value that important? Setting them lower will not allow a boot, need to clear CMOS the BIOS. Even on relaxed settings like 3000MHz I cannot set tRCDRD to lower than 18. I haven't spent a lot of money on the kit so I'm not expecting miracles. But that latency just seems wrong, somehow. Any input is much appreciated. 


*€dit: German forum helped me, it was the PowerDownMode enabled that cost me the latency (80ns when enabled, 72ns when disabled). Will go back to some tweaking then. *


----------



## Duvar

I wished i could go a lil bit down with the voltage, but not possible with this timings


----------



## CapKrunch

I copied 3600 fast preset and loose few timing. It have been running good so far and will do long stress test tonight.


----------



## Streetdragon

my settings foor now:

btw is there a guide for idiotts for how too use the ram calculator? Tried it and it shows me everytime "not supported" etc
Edit: nevermind^^ got it to wor, but i cant use the timings, wont boot at all for me.
Will doo it oldschool: try and repeat


----------



## DragonQ

Is it possible that RAM could be unstable if SOC voltage is too high? I notice my board defaults to 1.1 V but the new DRAM Calculator suggests 1.025 V.


----------



## alefim

ilmazzo said:


> suicide run?
> 
> vdram voltage?


VDRAM 1.47v
VSOC 1.05v LLC Auto
CLDO_VDDP: 0.915v


----------



## ilmazzo

alefim said:


> VDRAM 1.47v
> VSOC 1.05v LLC Auto
> CLDO_VDDP: 0.915v


whoa

thanks!

Well, I don't think my 2600X will let me get near that, taken apart the fact that even at 1,45v my dimms get overheating...I have to update to 1903, update chipsted drivers and last bios on my taichi x470 then , for the last time (maybe) I will do again a new oc profile for ram and see where I can get to.....


----------



## rul3s

Hello guys
I think we should update "RAM Test" from GSAT to MemTest5 + 1usmus config.

I was experiencing issues with [email protected] (32002CL14 was 1000% OK), HCI showed errors on 50-60%, GSAT was running ok with all ram and 3600seconds. I was going crazy thinking about IMC or Mobo and finally TM5 showed RAM errors within 30 first seconds.

All this exactly the same with a 2600, 2600x and a 3700x.


----------



## DragonQ

rul3s said:


> Hello guys
> I think we should update "RAM Test" from GSAT to MemTest5 + 1usmus config.
> 
> I was experiencing issues with [email protected] (32002CL14 was 1000% OK), HCI showed errors on 50-60%, GSAT was running ok with all ram and 3600seconds. I was going crazy thinking about IMC or Mobo and finally TM5 showed RAM errors within 30 first seconds.
> 
> All this exactly the same with a 2600, 2600x and a 3700x.


I use OCCT AVX2 CPU test. Shows errors within 1 minute if my RAM is unstable. If it passes 5+ minutes then I run MemTestPro over 16 threads. Short test is 10% coverage per thread to get a "generally stable" result, then run overnight to guarantee it if I'm sticking with it.


----------



## nick name

DragonQ said:


> I use OCCT AVX2 CPU test. Shows errors within 1 minute if my RAM is unstable. If it passes 5+ minutes then I run MemTestPro over 16 threads. Short test is 10% coverage per thread to get a "generally stable" result, then run overnight to guarantee it if I'm sticking with it.


Yeah, you always wanna mix and match your tests.


----------



## rul3s

3700x + Asus x470 Strix F + KFA2 DDR4 4000CL19


[email protected] 1.10v---BIOS 5007(1.0.0.2)---1000%--HOF4CXLBS4000M19SF162K

From ryzen dram calculator [email protected] presset


----------



## nick name

Is anyone running RAM at 3733MHz 14-16-14-14 with tuned subs . . . or close to it? If so -- what DRAM voltage are you running?


----------



## Aretak

Best I've managed so far, running a 4x8GB B-die setup. Tightening up some subtimings based on the Fast profile from the calculator dropped me all the way from 73ns to 67. Haven't stress tested it overnight or anything yet, but it's passed everything I've thrown at it so far and no random CTDs or anything in general use. Can get into Windows at 3733, but nowhere near stable. 3800 is a complete no-go and fails with either C5 (memory initialisation) or 07 (memory training) at any sort of voltage I'm comfortable running.


----------



## Streetdragon

3733 1:1 Cl 14 15 14 14 1T 1.5V


----------



## kazablanka

3800c15-17-10-15-30-45 @1,45v


----------



## DragonQ

I was quite excited when I loaded in my Thaiphoon output into Ryzen DRAM Calculator and it suggested a new set of timings that I could try. Unfortunately, even when I input nearly every single thing it suggests (timings, voltages, procODT, PMU training), it will not post at 3333 MT/s. I must have like bottom 1% RAM stock or something.


----------



## thegr8anand

What else can be tightened? The tCL is actually 13 in bios but i think GDM rounds it to 14. For some reason can't lower tRCDRD can't lower than 15.


----------



## Streetdragon

wow what is your voltage? Try lower some su timings like trfc


----------



## kazablanka

thegr8anand said:


> What else can be tightened? The tCL is actually 13 in bios but i think GDM rounds it to 14. For some reason can't lower tRCDRD can't lower than 15.


You could set trfc at 261-262 ,but your latency isn't as good as your timings. Try to untight some of them and check if your latency get better


----------



## thegr8anand

kazablanka said:


> You could set trfc at 261-262 ,but your latency isn't as good as your timings. Try to untight some of them and check if your latency get better



I tried but impossible to go below 65, do they go around 60 with 3733? I only see 3800mhz rams with lower latencies around 60-62. 





Streetdragon said:


> wow what is your voltage? Try lower some su timings like trfc


 

Tightened it even more and i think this the best possible now below 1.5v.


----------



## kazablanka

thegr8anand said:


> I tried but impossible to go below 65, do they go around 60 with 3733? I only see 3800mhz rams with lower latencies around 60-62.
> 
> 
> 
> 
> 
> 
> 
> Tightened it even more and i think this the best possible now below 1.5v.


Are you on manual overclock @4275mhz? If you are then your latency is just fine


----------



## savagebunny

Probably one of the few Biostar X370 GT7 users still at this point. Struggling on AGESA 1.0.0.1, but luckily good 3200 works for the time being. Will need a new board for faster. Also, can't even post past 1733 FCLK. Even when its still 1:1, beyond 3200 latency, boot speed, bios screen is slow, windows is sluggish anything beyond 3200Mhz. Early adopter life.


----------



## DragonQ

I had a small breakthrough and managed to get into Windows for the first time with RAM at 3333 MT/s. I did this by lowering procODT to 34.3 Ohms. I also tried 32 Ohms and 40 Ohms, all with VDIMM = 1.45 V, but it always BSODs within 2 minutes of OCCT.

What are the safe values of procODT to use with Ryzen 3000 and what are good values to try? So far lower values seem much more stable than the 53/60 suggested by Ryzen DRAM Calculator (can't even get into Windows with those values).


----------



## rul3s

Going one step ahead, [email protected] Custom config










1500% HCI estable + TestMem5 (1smus config) 6 cicles.


----------



## EddieZ

BLUuuE said:


> Got myself some Hynix CJR (2 x F4-3600C19-8GVRB)
> 
> 1.45v DRAM, 1.025v SOC
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I can boot 3733MHz and run AIDA64 memory benchmark, but not much else. Limited by my IMC.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Pretty impressive.



Thanks, have the same memory, used your config and it works. Somewhat more VDDCR (1.0875), cannot set it manually so is on Auto.
Haven't tested thouroughly, but Windows appears to run smooth. Let's see with some load 

Running on AMD Ryzen 2600X/ASUS TUF Gaming X470


----------



## nick name

thegr8anand said:


> What else can be tightened? The tCL is actually 13 in bios but i think GDM rounds it to 14. For some reason can't lower tRCDRD can't lower than 15.


I can't help, but is anyone else just tickled that his cores are asleep against a calming night sky?


----------



## Wickedtme

nick name said:


> I can't help, but is anyone else just tickled that his cores are asleep against a calming night sky?


LOL


----------



## Wickedtme

Best ive gotten so far, not sure were to go from here, are my voltages ok?
Oh, and its flare x 3200 cl14


----------



## Newbie2009

I have Corsair ddr4 3200mhz that xmp is at 1.35v. Would I be safe running 1.45v safe 24/7?


----------



## eeroo94

Newbie2009 said:


> I have Corsair ddr4 3200mhz that xmp is at 1.35v. Would I be safe running 1.45v safe 24/7?


Yes, 1,45v is perfectly safe.


----------



## ilmazzo

eeroo94 said:


> Yes, 1,45v is perfectly safe.


.... if temps are in check (below 50c)


----------



## reqq

used 1usmus fast calculation.. two of them are red in my bios. DRAM CH_A and CH_B vref voltage at 0.725. You think this is safe for daily system?


----------



## upgraditus

reqq said:


> used 1usmus fast calculation.. two of them are red in my bios. DRAM CH_A and CH_B vref voltage at 0.725. You think this is safe for daily system?


DRAM voltage itself red? since they just reflect half of that value.


----------



## reqq

upgraditus said:


> DRAM voltage itself red? since they just reflect half of that value.


my dram voltage set to 1.47.. and yes thats red.. but i read thats perfectably fine for ddr4 and b-die. Dont know about these other values though.


----------



## upgraditus

reqq said:


> my dram voltage set to 1.47.. and yes thats red.. but i read thats perfectably fine for ddr4 and b-die. Dont know about these other values though.


If DRAM voltage is 1.47 then vref would be 0.7*3*5v

Like I said it's just 1/2 DRAM voltage, if you're fine running 1.47v then should be fine with the others too.


----------



## Wickedtme

After many problems with stability and errors, i decided to try the asrock built in xmp settings for different rams, picked the 4200mhz gskill, then lowered it to 3800, infinity at 1900, and it was stable, then i did the same settings in ryzen ram calculator to see the timings at 4200mhz, and used those with lower voltage at 3800mhz, this is the result, and its stable, im just a little worried about seeing the ram temps in HWiFO reach 48c, ordered a fan hub so i can free up a fan header to put a ram cooler in for peace of mind. Had a corsair airflow dram cooler collecting dust, so it will come in handy.









Thoughts?


----------



## kazablanka

ilmazzo said:


> .... if temps are in check (below 50c)


Why temps have to be below 50c ,ddr4 is designed to operate at much higher temperature


----------



## Streetdragon

Like i always say: Cool hardware is happy hardware!


----------



## kazablanka

Streetdragon said:


> Like i always say: Cool hardware is happy hardware!


Ok but this doesn't that you can't operate ram above 50c...


----------



## Jackalito

kazablanka said:


> Ok but this doesn't that you can't operate ram above 50c...



It's not about RAM flat out not working; it's about the cooler the sticks are, the higher clocks with tighter timings you can get stable.


----------



## Streetdragon

Jackalito said:


> It's not about RAM flat out not working; it's about the cooler the sticks are, the higher clocks with tighter timings you can get stable.


Yep
sure you can run them 90°+
but one clock+timing can bestable at 40° but start to produce errors at 42°. So thats the main point


----------



## kazablanka

Streetdragon said:


> Yep
> sure you can run them 90°+
> but one clock+timing can bestable at 40° but start to produce errors at 42°. So thats the main point


Then your ram overclock is not full stable or your ram kit requires more voltage when the chips get hotter 

I have no error operating above 50c


----------



## Streetdragon

Reread my post, read ther members posts in this forum and think about it^^


----------



## hazium233

Has anybody attempted to read memory timings in the Chipset section of AIDA64?

I was poking around in there, and while most of the timings seem to be reported as I would expect, I don't know where it is getting the values for others. Specifically the tRRD values (RAS to RAS) seemed weird. Tried a few profiles from stock/default to overclocked with different RRDS/L and RDRDSCLs.

I assume AIDA just can't read the info correctly from my board/cpu.

I can't remember if I checked this on older versions. Usually just use RTC.


----------



## kazablanka

Streetdragon said:


> Reread my post, read ther members posts in this forum and think about it^^


Ι gave you an example of my system that the specific configuration runs stable at 53c the timings are pretty tight I think ,many people here posts things that have no idea about ,this is not a proof. Stable is something that runs stable in any condition everything else is just unstable for me. So if you think that bdies need to operate under 42c its an opinion not the rule.


----------



## christoph

kazablanka said:


> Ι gave you an example of my system that the specific configuration runs stable at 53c the timings are pretty tight I think ,many people here posts things that have no idea about ,this is not a proof. Stable is something that runs stable in any condition everything else is just unstable for me. So if you think that bdies need to operate under 42c its an opinion not the rule.


is not what we think, is common knowledge by now that over 42-45 the ram tends to produce errors when below those temps will not, but as you may know ( i think you might know as you are tying to impose "your knowledge" ) the knowledge that precede this is that it depends on the silicon lottery if or not will be stable beyond certain values.

PERIOD.


----------



## Grin

Max temperature for b-dies is 85C but Gskill do not recommend to run them over 70C 1.5v No proof I did discuss it with rep by phone


----------



## thagabe

@Grin 

Cool! When OC my memory and stress it can get up to 54C @1.4V so I'm well within the safe zone!


----------



## VPII

Look I've never been someone to do stress testing on my hardware, but I figured that everything seems to run so well with my new build I'll leave Karhu Ram Test to run overnight just to see if my DDR4 3200 CL14 is stable at DDR4 3733 CL16 bur 2T command rate. I wasn't happy about the 2T command rate, but I was informed by a close friend that I'll gain more from fine tuning TWCL than I'll gain from T1 command rate. The last (well the second sorry, the last show latency at 4.26Ghz) screenshot is with the CPU at 4.39Ghz, not for everyday use just benching but look at the impact on the latency.


----------



## kazablanka

christoph said:


> is not what we think, is common knowledge by now that over 42-45 the ram tends to produce errors when below those temps will not, but as you may know ( i think you might know as you are tying to impose "your knowledge" ) the knowledge that precede this is that it depends on the silicon lottery if or not will be stable beyond certain values.
> 
> PERIOD.


Ok you can keep your "common knowledge" and your ram below 45c... have a nice day


----------



## christoph

kazablanka said:


> Ok you can keep your "common knowledge" and your ram below 45c... have a nice day



don't be stupid kid, the world record OC don't run things at 90 degrees, do they?


----------



## Redwoodz

kazablanka said:


> Ok you can keep your "common knowledge" and your ram below 45c... have a nice day





christoph said:


> don't be stupid kid, the world record OC don't run things at 90 degrees, do they?


 I wouldn't worry about any RAM temps under 60c. The thing is, the cooler your chips are the less voltage it takes to be stable at a given speed as a rule.


----------



## kazablanka

christoph said:


> don't be stupid kid, the world record OC don't run things at 90 degrees, do they?


Maybe I am stupid but I am not a kid ,so you can run your ram on dry ice to be sure. Have a nice day in Alaska.


----------



## kazablanka

Redwoodz said:


> I wouldn't worry about any RAM temps under 60c. The thing is, the cooler your chips are the less voltage it takes to be stable at a given speed as a rule.


That's excactly what iam trying to say but as I can see in this forum is a rule to not operate a bdie kit above 42c.


----------



## Streetdragon

kazablanka said:


> That's excactly what iam trying to say but as I can see in this forum is a rule to not operate a bdie kit above 42c.


Ok..... hope you understand it now. I dont think so......

Run it at 90° if you want. What ever,
BUT under 40-42° the rram is more stable and can run tigher timings/ higrer speed becasue colder = more voltage efficent = more stable.
CPU work this way, GPU work this way and ram work this way.....


----------



## kazablanka

Streetdragon said:


> Ok..... hope you understand it now. I dont think so......
> 
> Run it at 90° if you want. What ever,
> BUT under 40-42° the rram is more stable and can run tigher timings/ higrer speed becasue colder = more voltage efficent = more stable.
> CPU work this way, GPU work this way and ram work this way.....


So if I keep my ram temperature under 42c what timings can I lower and be stable. I am waiting for your proposals.

If you use your system for rendering how can you keep ram under 42c?

temperature is not ram' s problem but mobo's by adding noise in the signal in many cases. Well filtered mobo's have no problem with temps.
You can upload a ss with your ram configuration running tm5 and keep it below 42c and another with the same settings by not trying to cool the ram


----------



## nick name

My daily 3600 tight timings are stable when I use a fan to cool my RAM, but throw errors when I don't. I would say the errors start coming around mid-40*C. 

And RAM is absolutely capable of running at higher temps when left at stock or close to it, but when you push RAM to the edge temp becomes a factor. And since many folks are trying to run their RAM at the very edge the temp that starts to become problematic can be pretty low. So yeah it's anecdotal evidence that points to 42*C, but it's not a rule. Obviously not if someone can run their RAM at higher temps. But if someone is running their RAM at higher temps then they may find some more performance if they lowered their temps.


----------



## Grin

Streetdragon said:


> Ok..... hope you understand it now. I dont think so......
> 
> Run it at 90° if you want. What ever,
> BUT under 40-42° the rram is more stable and can run tigher timings/ higrer speed becasue colder = more voltage efficent = more stable.
> CPU work this way, GPU work this way and ram work this way.....


You need a water cooling to keep your ram below 42C Normally my 4x16 3200/14 are working in the range 45-55C stable 24/7


----------



## nick name

Grin said:


> You need a water cooling to keep your ram below 42C Normally my 4x16 3200/14 are working in the range 45-55C stable 24/7


Well I wouldn't say you have to go that far. With my 2x8GB kit a fan in front of my RAM keeps it normally below 40*C.


----------



## Grin

Errors coming because of undervoltage. Just increase the dram voltage. Dram chips is not a magic things and as chips in ssd and nvme can work normally till 70-75C


----------



## Streetdragon

Grin said:


> You need a water cooling to keep your ram below 42C Normally my 4x16 3200/14 are working in the range 45-55C stable 24/7


nope^^ have 4 of 4 dimms in use. between the dimms is thermal paste and on the outer ram moduls are heatsinks.
Ontop is a 120mm fan that cools them down.


Which timings trigger the temp instability. dont know. im not a pro. i just lower timings and test


----------



## savagebunny

Biostar just pushed 1.0.0.3AB for my GT7. Fun stuff. I was stuck at 3200 on 1.0.0.1, and 1600 FCLK.


----------



## savagebunny

Just upped tRFC to 300, and DRAM Voltage. Wasn't stable for ramtest but enough for AIDA


----------



## VPII

savagebunny said:


> Just upped tRFC to 300, and DRAM Voltage. Wasn't stable for ramtest but enough for AIDA


Make your command rate 2T, you won't loose much just drop twcl a tad. You might have stability then.

Sent from my SM-G960F using Tapatalk


----------



## gamervivek

Contrary to the AMD DRAM post with 1st gen Ryzen, I'm finding increased stability at lower ProcODT values for 3800Mhz ram.

Is lower than 40Ohms safe? Currently at 34.3, down from 36.9 which had couple of errors in 6th test of memtest86.


----------



## VPII

At last, one try 3800 mem and 1900 IF and it was a go, not just that but it is also stable.... SO happy.


----------



## nick name

VPII said:


> At last, one try 3800 mem and 1900 IF and it was a go, not just that but it is also stable.... SO happy.


You tease. Tell the good folks how you done gone done it.


----------



## VPII

nick name said:


> You tease. Tell the good folks how you done gone done it.[/quote @nick name, in all honesty I did not even touch voltages other than vcore and vdimm. Vdimm is at 1.45v which is fine. There is no setting for IF speed in the Msi Meg X570 Ace, it sets it automatically at 1:1 with memory speed if doable. I confirmed it in Ryzen Master. For timings I basically set CL16 16 16 with 32 Tras and Trfc 275 and trc 42 or 48. Can't remember now. Twlc I set at 10 to compensate for T2 command rate as it basicallt makes up for T2 command rate. This board is actually so easy to use.
> 
> Sent from my SM-G960F using Tapatalk


----------



## thegr8anand

Nice. Will try tonight with 2T as it might get me 3800 as well.


----------



## RossiOCUK

Aretak said:


> Best I've managed so far, running a 4x8GB B-die setup. Tightening up some subtimings based on the Fast profile from the calculator dropped me all the way from 73ns to 67. Haven't stress tested it overnight or anything yet, but it's passed everything I've thrown at it so far and no random CTDs or anything in general use. Can get into Windows at 3733, but nowhere near stable. 3800 is a complete no-go and fails with either C5 (memory initialisation) or 07 (memory training) at any sort of voltage I'm comfortable running.


I have 4x8GB on the CHVI also. Can you please provide a txt dump of your settings for me?


----------



## DragonQ

thegr8anand said:


> Nice. Will try tonight with 2T as it might get me 3800 as well.


I wonder if it's even worth going for 3800 2T compared to 3733 1T? All the tests I've seen so far show that timings are more important than clock speed beyond ~3200 MT/s, for gaming anyway.


----------



## VPII

DragonQ said:


> I wonder if it's even worth going for 3800 2T compared to 3733 1T? All the tests I've seen so far show that timings are more important than clock speed beyond ~3200 MT/s, for gaming anyway.[/quote @DragonQ check my results at 3800 2T a few posts up.
> 
> Sent from my SM-G960F using Tapatalk


----------



## thegr8anand

VPII said:


> DragonQ said:
> 
> 
> 
> I wonder if it's even worth going for 3800 2T compared to 3733 1T? All the tests I've seen so far show that timings are more important than clock speed beyond ~3200 MT/s, for gaming anyway.[/quote @*DragonQ* check my results at 3800 2T a few posts up.
> 
> Sent from my SM-G960F using Tapatalk
> 
> 
> 
> 
> Aida does show better MB/s and latency than my 3733 but that increase is expected of 3800. DragonQ is right, 2T should be worse than 1T, 1T with GD still should be better than 2T. Have you tried testing if it made an improvement in games than your 3733 timings?
> 
> 
> 
> my 3733 with 1T/GD enabled.
Click to expand...


----------



## VPII

thegr8anand said:


> VPII said:
> 
> 
> 
> Aida does show better MB/s and latency than my 3733 but that increase is expected of 3800. DragonQ is right, 2T should be worse than 1T, 1T with GD still should be better than 2T. Have you tried testing if it made an improvement in games than your 3733 timings?
> 
> 
> 
> my 3733 with 1T/GD enabled.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Well cannot get 1T even for 3733 as it just sets it at 2T even if I set it to 1T. My results look good in Aida because I dropped twcl which gives more than 1T.
> 
> Sent from my SM-G960F using Tapatalk
Click to expand...


----------



## DragonQ

thegr8anand said:


> VPII said:
> 
> 
> 
> Aida does show better MB/s and latency than my 3733 but that increase is expected of 3800. DragonQ is right, 2T should be worse than 1T, 1T with GD still should be better than 2T. Have you tried testing if it made an improvement in games than your 3733 timings?
> 
> my 3733 with 1T/GD enabled.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Indeed, AIDA memory benchmark is one thing but certain setting changes might increase your AIDA scores whilst reducing performance in some real-world scenarios.
Click to expand...


----------



## VPII

thegr8anand said:


> VPII said:
> 
> 
> 
> Aida does show better MB/s and latency than my 3733 but that increase is expected of 3800. DragonQ is right, 2T should be worse than 1T, 1T with GD still should be better than 2T. Have you tried testing if it made an improvement in games than your 3733 timings?
> 
> 
> 
> my 3733 with 1T/GD enabled.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Especially for you.... 1T / 1N.... And tah dah.... it is exactly the same as with 2T.... I have now Geardown option in my mobo except that it is select able when choosing 1T or 2T it is a third option.
Click to expand...


----------



## thegr8anand

That is pretty great. If it works with 1T why use 2T?


----------



## VPII

thegr8anand said:


> That is pretty great. If it works with 1T why use 2T?


Because with my board I have no control over geardown and if enabled which I cannot see then I am sorry performance will be the same as 2T with geardown disabled. Okay, seen that Ryzen Timing Checker does not work I checked with AMD Ryzen Master and it is disabled so all good. Currently running Karhu Memtest and if okay for 5 to 7 hours then this will be my new settings.


----------



## VPII

1T no go.... failed Karhu memtest at 2500% or there about so I'm back on 2T. Seriously it seems most people have this epiphany about 1T that they don't really see how to bypass it with other timings which works at 2T.


----------



## thegr8anand

I think you need to benchmark some games and compare before and after to see if 2T is actually benefiting you.


----------



## VPII

thegr8anand said:


> I think you need to benchmark some games and compare before and after to see if 2T is actually benefiting you.


1T fail, 2T go...so I think it is clear

Sent from my SM-G960F using Tapatalk


----------



## oreonutz

I just re read the Rules and Realized I was supposed to use HCI MemTest and the Google Stress Test for this, not just Karhu Mem Test, so I now Realize this won't count, but I worked so long to get these results. So I am posting them anyway! LOL! I will run the other 2 tests while working today and post those later.

3900x - All Core OC 4225Mhz - Ram: 3800Mhz - IF: 1900Mhz - CL: 16 - tRRCD: 17 - tWRCD: 16 - tRP: 17 - tRAS: 34 - tRC: 56 - tRFC: 364 - CR1



Spoiler


----------



## dgoc18

2T is okay, 2T is for high memory clocks. There is nothing crazy about 1T at all. I have to accept 2T that works for me.

Mine ram 3800 IF 1900 2T 15-15-15-15-36-50-260 better than nothing, 1T won't post, I have to reset clear cmos every time.

Great information about Dram for main and sub timings. Link at below.

https://community.amd.com/community/gaming/blog/2017/05/25/community-update-4-lets-talk-dram

https://community.amd.com/community...emory-oc-showdown-frequency-vs-memory-timings

You can pin tab or bookmark to read later on.

2 cents.


----------



## MNKyDeth

[email protected](GearDownMode-enabled)---1.44v---SOC 1.1v---BIOS 7C35v13---Stressapptest---1 Hour--CMW32GX4M2C3466C16
FCLK = 1900
3800x | MSI MEG ACE | Corsair [email protected] 32GB - dram calc memory settings (fast)


Attached a notepad of the last bit of output from the stresstestapp

Log: Seconds remaining: 30
Log: Seconds remaining: 20
Log: Seconds remaining: 10
Stats: Found 0 hardware incidents
Stats: Completed: 132600192.00M in 3600.51s 36828.12MB/s, with 0 hardware incidents, 0 errors
Stats: Memory Copy: 132600192.00M at 36835.97MB/s
Stats: File Copy: 0.00M at 0.00MB/s
Stats: Net Copy: 0.00M at 0.00MB/s
Stats: Data Check: 0.00M at 0.00MB/s
Stats: Invert Data: 0.00M at 0.00MB/s
Stats: Disk: 0.00M at 0.00MB/s

Status: PASS - please verify no corrected errors

[email protected]:~$


----------



## Takla

savagebunny said:


> Probably one of the few Biostar X370 GT7 users still at this point. Struggling on AGESA 1.0.0.1, but luckily good 3200 works for the time being. Will need a new board for faster. Also, can't even post past 1733 FCLK. Even when its still 1:1, beyond 3200 latency, boot speed, bios screen is slow, windows is sluggish anything beyond 3200Mhz. Early adopter life.


3900x on a biostar mainboard. thats a yikes from me


----------



## thegr8anand

Closing background apps increased the score little bit. Pretty happy with it as 3800mhz not possible for me. 99.06% read and 97.45% write of max theoretical bandwidth of 59728 Mb/s.


----------



## DragonQ

1T works for me at 3733-16-18-16-36 @ 1.4 V but only with GDM enabled. Disabling it leads to errors in OCT. Maybe I could get away with disabling it by raising VDIMM to 1.45 V but unless it actually allows me to set CAS to 15, it seems pointless.

All of my other timings are based on what I had stable at 3200 @ 1.35 V, so now I'm at 1.4 V I can probably improve a few of them. Otherwise I'm happy with where I am right now: AIDA64 latency is 67.7ns and gaming performance is solid.


----------



## DragonQ

Well I guess I spoke too soon. Although my rig is stable for ~650% MemTestPro and over an hour of OCCT, I get lock-ups and reboots after ~30 minutes of gaming. Is there a particular setting that would be likely to cause this kind of instability?

I've tried loosening:
tRAS (32 -> 36)
tRC (54 -> 56)
tRRDS (5 -> 6)
tRRDL (5 -> 6)
tRTP (12 -> 14)
tWRWR SD (7 -> 8)
tRDRD SD (5 -> 6)

Some of my timings are pretty loose to begin with (e.g. tWR = 21). I've also tried going to VDIMM = 1.42 V to no avail. I could try 1.45 V I guess but I wasn't sure if heat was causing the instability. I guess that's unlikely given stress tests all seem to pass for hours. What about procODT would that help with anything aside from booting? Would cLDO_VDDP > 0.9 V help at all?


----------



## kenny0048

DragonQ said:


> 1T works for me at 3733-16-18-16-36 @ 1.4 V but only with GDM enabled. Disabling it leads to errors in OCT. Maybe I could get away with disabling it by raising VDIMM to 1.45 V but unless it actually allows me to set CAS to 15, it seems pointless.
> 
> All of my other timings are based on what I had stable at 3200 @ 1.35 V, so now I'm at 1.4 V I can probably improve a few of them. Otherwise I'm happy with where I am right now: AIDA64 latency is 67.7ns and gaming performance is solid.


In Micron E-die, CAD_BUS 120/30/30/120 is another world. (DDR4-3800 +, 1T, Disable GDM, tCKE = 1, etc ...)
I don't know about Samsung B-die, but it might be worth trying.

If you want to use the system with 1.40v, make sure that OCCT can pass at 1.38v.
The margin in this case is 0.02v.
If the error still occurs, CLDO_VDDP must be raised to move the memory hole.
or CAD_BUS tuning is required.

### CAD_BUS tuning ###
To check for waveform Level, loop only Test8 (Random test) of Memtest86.
The trend can be confirmed by lowering the voltage and intentionally generating an error.

An error (+) indicates that CAD_BUS is too low. (Impedance is low, signal level is too high)
An error (-) indicates that CAD_BUS is too high. (Impedance is high, signal level is too low)

Exsample test8 result
Error (+) 66667666: 66668666
Error (-) 77776777: 77775777

* This is unavoidable when tuning a parallel bus.
* The ratio of +/- errors in a random test must be 1: 1.
* CAD_BUS setting is not appropriate if random test results are biased.
* If there is an offset, it will be an incorrect value when reading voltage of capacitor.


----------



## DragonQ

I am not sure what you mean by CAD_BUS, haven't seen that option yet. I've loosened more timings, upped VDIMM to 1.45 V, upped VDDP to 0.95 V, and upped CLDO_VDDP to 0.95 V. Still crashes while gaming despite passing stress tests.

I've tried lowering procODT to 40 Ohms but beyond that I'm not sure what else I can do other than lower the speed.


----------



## nick name

DragonQ said:


> I am not sure what you mean by CAD_BUS, haven't seen that option yet. I've loosened more timings, upped VDIMM to 1.45 V, upped VDDP to 0.95 V, and upped CLDO_VDDP to 0.95 V. Still crashes while gaming despite passing stress tests.
> 
> I've tried lowering procODT to 40 Ohms but beyond that I'm not sure what else I can do other than lower the speed.


Just needs some more VDIMM.


----------



## DragonQ

nick name said:


> Just needs some more VDIMM.


I'm not comfortable running over 1.45 V on daily basis. Even dropping to 3666 MT/s doesn't help game stability (although it passes stress tests) and I know anything between 3200 and 3600 MT/s barely boots, so I guess I'm buggered.


----------



## savagebunny

Takla said:


> 3900x on a biostar mainboard. thats a yikes from me


It isn't bad. If you look at my more recent posts of my 3600 results, I'm doing better than some with better boards. Also I'm on 1.0.0.3AB and everything works.


----------



## Nighthog

savagebunny said:


> Biostar just pushed 1.0.0.3AB for my GT7. Fun stuff. I was stuck at 3200 on 1.0.0.1, and 1600 FCLK.


I have the X470GT8 did you have the same experience of being stuck @ 3200mhz max for your board with all previous BIOS and did you have another earlier cpu in that board prior?

I'm curious if the new BIOS has finally fixed the MEM OC disability these Biostar boards had. (3200 MAX)

Feeling like throwing it up from it's box again and to test the newest 1.0.0.3AB BIOS with my Ryzen 1700. (had tried all earlier up to comboPI 1.0.0.1 version)


----------



## savagebunny

Nighthog said:


> I have the X470GT8 did you have the same experience of being stuck @ 3200mhz max for your board with all previous BIOS and did you have another earlier cpu in that board prior?
> 
> I'm curious if the new BIOS has finally fixed the MEM OC disability these Biostar boards had. (3200 MAX)
> 
> Feeling like throwing it up from it's box again and to test the newest 1.0.0.3AB BIOS with my Ryzen 1700. (had tried all earlier up to comboPI 1.0.0.1 version)


Yes, we both were on ComboAM4 1.0.0.1 which locked us at 3200. With 1.0.0.3AB it's all fixed now. I'm doing 3733 runs easily with my 3900x. If you have Samsung B-Die set VDIMM Voltage to +0.252 in the BIOS, it's a good starting point at 3600Mhz.


----------



## oreonutz

DragonQ said:


> I'm not comfortable running over 1.45 V on daily basis. Even dropping to 3666 MT/s doesn't help game stability (although it passes stress tests) and I know anything between 3200 and 3600 MT/s barely boots, so I guess I'm buggered.


Instead of Raising VDimm try Raising your ProcODT. You can do so without adding more heat, and it will help increase stability. Don't go higher than 60-Ohms, I found the Sweet spot to be in between 48-Ohms and 53-Ohms. When you Raise ProcODT you can usually lower Voltage too.

Also, if you have a memory hole, you can often fix it by LOWERING (instead of Raising) CLDO VDDP. Stock is .900, moving .01 at a time (so from .900 to .890 and from .890 to .880 and so on) is the recommended Method. However I found my best stability with .850v, this may be too low for you, but was what I needed to plug a Memory Hole. I would first raise your ProcODT starting at 40-Ohms and go up a level from there until reaching 53-Ohms, and then if you are still having issues lower CLDO VDDP .01 at a time until you find stability. If you still can't find stability it is likely that one of your timings is just not set correctly. Timings work off of a Formula, and are all related to another, largely based off the ns of your Primary Timings at a given speed, so if you have kept the same timings from a lower speed, you may want to recalculate them. 

I can post formula's to help, but it generally only confuses the hell out of people unless they are good at math. The recommended method would just be to use Thaiphoon Burner (Which you would also need for the manual method anyway) to capture your DIMM's Specs in Nano Seconds and then use 1usmus' Ryzen Calculator to calculate your timings. However, its important when using his calculator to not use the Built in Profile, but instead set that to Manual, then import your Memory Profile exported from Thaiphoon Burner, then calculate a safe and then fast profile for the speed you are attempting to obtain. Use the safe timings first and see if you achieve stability at your desired frequency, and then try the Fast Profile, just remember that some of the timings relate to each other so its best to plug all the fast timings in and see if you achieve stability, because if you try only some from fast with some from safe, you could lose stability because the calculation between related timings could be off.

I hope this helps.

EDIT: It is also COMPLETELY Possible that your game stability is unrelated to your Ram Overclock, and could be related to other factors, such as a game bug, Core OC instability, Driver incompatibility, or a thousand other things. I highly recommend paying the $5 for Karhu's RAM Test, simply because it does an even BETTER job at finding Memory Instability then HCI Mem Test, and can do it in a Quarter of the time. This is because it uses Your Multiple Cores/Threads much more efficiently, so can scan through your Ram much faster. If you can get to 1000% in Karhu's RAM Test without one error, then the chances that the Memory OC is your issue is incredibly low. If you are rocking 16GB of Ram then getting to 1000% in Karhu's Test takes about 15 Minutes or so, as compared to the Hour or so that same amount takes in HCI's Mem Test.


----------



## 1usmus

*DRAM Calculator for Ryzen™ 1.6.1*









*Changelog:*

* NEW. Graph of random access to caches and DRAM. Please note , that the testing process may take several minutes.
* NEW. FreezKiller - software that will make your frame rate as smooth as possible without sacrificing performance. New iteration of cleaning Standby caches without jerking. Just click the "Start" button, minimize the application and launch your game.
* NEW. Samsung b-die , Hynix CJR and Micron E-die presets. Particular attention was paid to memory, which is based on Micron E-die chips.
* Updated Memtest mode, the application will automatically configure all the parameters individually for your system in 1 click (just select MEMbench mode -> Memtest).
* Improved support for 4 DIMM's.
* Overclocking potential DRAM received an update (tab "Advanced").
* Correction MEMbench algorithms. In some cases, you will get better results.
* Included libraries for improved compatibility with some versions of Windows.
* Bug fixes.

*Download:*
Techpowerup link
Guru3d link
Сomputerbase.de link
Techspot link


----------



## Jackalito

1usmus said:


> *DRAM Calculator for Ryzen™ 1.6.1*
> 
> 
> 
> 
> 
> 
> 
> 
> 
> *Changelog:*
> 
> * NEW. Graph of random access to caches and DRAM. Please note , that the testing process may take several minutes.
> * NEW. FreezKiller - software that will make your frame rate as smooth as possible without sacrificing performance. New iteration of cleaning Standby caches without jerking. Just click the "Start" button, minimize the application and launch your game.
> * NEW. Samsung b-die , Hynix CJR and Micron E-die presets. Particular attention was paid to memory, which is based on Micron E-die chips.
> * Updated Memtest mode, the application will automatically configure all the parameters individually for your system in 1 click (just select MEMbench mode -> Memtest).
> * Improved support for 4 DIMM's.
> * Overclocking potential DRAM received an update (tab "Advanced").
> * Correction MEMbench algorithms. In some cases, you will get better results.
> * Included libraries for improved compatibility with some versions of Windows.
> * Bug fixes.
> 
> *Download:*
> Techpowerup link
> Guru3d link
> Сomputerbase.de link
> Techspot link



Thanks, 1usmus! +Rep! :thumb:


----------



## oreonutz

1usmus said:


> *DRAM Calculator for Ryzen™ 1.6.1*
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> *Changelog:*
> 
> * NEW. Graph of random access to caches and DRAM. Please note , that the testing process may take several minutes.
> * NEW. FreezKiller - software that will make your frame rate as smooth as possible without sacrificing performance. New iteration of cleaning Standby caches without jerking. Just click the "Start" button, minimize the application and launch your game.
> * NEW. Samsung b-die , Hynix CJR and Micron E-die presets. Particular attention was paid to memory, which is based on Micron E-die chips.
> * Updated Memtest mode, the application will automatically configure all the parameters individually for your system in 1 click (just select MEMbench mode -> Memtest).
> * Improved support for 4 DIMM's.
> * Overclocking potential DRAM received an update (tab "Advanced").
> * Correction MEMbench algorithms. In some cases, you will get better results.
> * Included libraries for improved compatibility with some versions of Windows.
> * Bug fixes.
> 
> *Download:*
> Techpowerup link
> Guru3d link
> Сomputerbase.de link
> Techspot link


First and Foremost, Thank You for making such an Awesome tool for the community!

Second, and this could just be my dumb ass doing something wrong, but the TechPowerUp Link seems to be hosting the previous version. I downloaded and ran it looking for the new Latency Graph and couldn't figure out how to make the button appear like on your screen shot, when I noticed I was running the previous version. Went back to the TechPowerUp link and saw it was still the older version.

The Guru3d Link is the new version though!


----------



## mongoled

OK, so I got pulled back in



Prime95 29.8 build 5, Blend +8hrs
YCruncher v0.7.7.9501 +11hrs
RealBench +8hrs
TM5 - 25 Cycles
Memtest (1usmus) - 5000%

PBO 10x, Boost 75mhz

Only thing left is to play some games!

Providing there are no unforeseen issues this is stable enough for me

 


** EDIT **
I had deemed the rig to be stable, the only thing I hadnt done was test the graphics subsystem (yes I know Realbench does this, but had not played any 3d games etc) but im getting hard locks when least expected.

Example, I wanted to play doom, first attempt the PC locked up (but sound could be heard) when loading the saved game (PCIe intensive).

I crashed the PC (ctrl-del not doing anything) and then started the game again, it did not lock up and I played for around an hour.

I went to exit the game and it hard locked.

The same thing happened when I loaded 3dmark, on the loading stage of the benchmark, again a hard lock.

Tried again and the benchmark ran with no issues.

So I am getting random lock ups when anything intensive is done on the PCIe bus, i.e. high data throughput or when the PCIe bus


** EDIT2 **
OK, something to do with the memory subsystem.

Running 3800/1900 with [email protected] default settings im getting way less whea errors/warnings and so far no hard locks.

Will need to return to my subtimings to see which is effecting PCIe stability and will report back.


** EDIT3 **
Just needed to increase vdimm by 0.01v, seems like with loads that stress the PCIe subsystem and when using tight tfaw (16) and high mem/if frequencies, instability is introduced when vdimm voltage is not enough.

I am seeing less whea errors/warnings and games are no longer hardlocking/rebooting etc


----------



## Aretak

RossiOCUK said:


> I have 4x8GB on the CHVI also. Can you please provide a txt dump of your settings for me?


Too late to be of use I'm sure, but for reference these are the settings that I use for 4x8GB/3600/CL14.

Been trying to get something higher using only two sticks, but I think I got a bad chip that doesn't like an FCLK above 1800MHz. It straight up refuses to boot at 1900MHz and is unstable in-between.


----------



## Dphotog

I think I've given up on the 3800 dream and settling down with 3733 cl13-16-16-16 1.52v latency is 64.1 prior to Ryzen Master OC 63.1 with OC. 

Before y'all get high and mighty about the Voltage I've been told and read that it's not the end of the world with B-die to go over 1.5v. I've ran multiple stabliltiy tests through memtest and Aida64 I've not done prime95 because I feel like it will crash anything.

Ram: Trident Royal 2x 16gb dual rank 1T with gear down mode enabled. Won't post without gear down mode on.

I've had nothing but issues with 3800 and I'm pretty sure it's the cpu telling me no with the fclk just not taking to it even with voltages cranked or downed there's always a 1 in 5 chance it doesn't post and cycles and resetting my bios. Even with super relaxed timings. Thus my cracking down on 3733 and tightening as much on the main timings I could I haven't gotten to subtiming tightening yet since I used my 3800 subtimings over for the 3733 build.


----------



## ver_21

Dphotog said:


> I think I've given up on the 3800 dream and settling down with 3733 cl13-16-16-16 1.52v latency is 64.1 prior to Ryzen Master OC 63.1 with OC.
> 
> Before y'all get high and mighty about the Voltage I've been told and read that it's not the end of the world with B-die to go over 1.5v. I've ran multiple stabliltiy tests through memtest and Aida64 I've not done prime95 because I feel like it will crash anything.
> 
> Ram: Trident Royal 2x 16gb dual rank 1T with gear down mode enabled. Won't post without gear down mode on.
> 
> I've had nothing but issues with 3800 and I'm pretty sure it's the cpu telling me no with the fclk just not taking to it even with voltages cranked or downed there's always a 1 in 5 chance it doesn't post and cycles and resetting my bios. Even with super relaxed timings. Thus my cracking down on 3733 and tightening as much on the main timings I could I haven't gotten to subtiming tightening yet since I used my 3800 subtimings over for the 3733 build.



Haven't been able to follow all of your post, but I run the following:


DRAM: 3800CL16-17-16-32-48 1T

FCLK: 1900
SOC: 1.15
VDDP: 1.10
VDDG: 1.075
DRAM: 1.45V


I was getting stuck with random "8d" boot errors until I tweaked the SOC, VDDP, and VDDG to the maximums suggested by DRAM Calc.




These are sticks of Kingston Hyperx 4000 (BDie) on an X570 Ace, BIOS version 145 (beta).


----------



## hazium233

Can someone comment on TM5 Test 0 errors? Test is "RefreshStable," which I found a description of from the author. 



> in the sense, it checks the safety of data in memory while its _other_ sections are checked. It is impossible to check all the memory at one time (limitation of the x86 mode), therefore, the window mode is used. Tests are chased in the window, and the rest of the memory is idle. So, test No. 0 just checks that during the testing of other memory blocks, the rest were not damaged. The test is called "RefreshStable", actually


I have been trying to test different patterns of timings at 3200MT/s and 1.35V with my Micron Rev D sticks. Most recently when I was testing a config with secondary/tertiaries calculated at or near specification seeing what affect I could have on primaries. For instance, I tested a config last night with 14-16/18-16-36 and it generated a Test 0 error on cycle 3 and then 4 (at which point I aborted). 

I had previously run 14-18/18-18-36 to >400% per thread in HCI, then a 14-16/18-16-36-66 config generated an error in HCI at 524%. The TM5 test was with tRC reverted to "spec."

I also had one Test 0 error on a 16-16/18-18-38 config, but with tightened tRRDS and FAW, and also more aggressive RDWR.

I would have thought that from the description, this might be something you would see with aggressive tRFC or something, but I had that at 350ns.

I guess I can just try throwing a little voltage at it later. Might try modifying tRTP/tWR for fun, or increasing tRRDS a little over calculated spec. But wondered if anybody had run into this with that test.


----------



## Mr.N00bLaR

Guidelines for memory voltage for the 3000 series cpus?


----------



## Hale59

Mr.N00bLaR said:


> Guidelines for memory voltage for the 3000 series cpus?


https://www.tomshardware.com/reviews/amd-ryzen-3000-best-memory-timings,6310.html


----------



## Mr.N00bLaR

Hale59 said:


> https://www.tomshardware.com/reviews/amd-ryzen-3000-best-memory-timings,6310.html


Hmm, maybe I missed the info on memory voltage? Interesting read on the effective performance though, maybe I should set DOCP and forget it. (3200cl14)


----------



## Synoxia

What does freezkiller do?


----------



## cicero s

Synoxia said:


> What does freezkiller do?



I guess the feature works like ISLC.


https://www.wagnardsoft.com/forums/viewforum.php?f=18


----------



## Synoxia

cicero s said:


> I guess the feature works like ISLC.
> 
> 
> https://www.wagnardsoft.com/forums/viewforum.php?f=18


Guess is not enough XD


----------



## 1usmus

Synoxia said:


> What does freezkiller do?


The new generation of intelligent standby cleaning, does not cause jerks during cleaning.


----------



## Synoxia

1usmus said:


> The new generation of intelligent standby cleaning, does not cause jerks during cleaning.


I see. Thank you then for your work. Maybe you want to consider some clever options like autostart at login or system timer like ISLC so i dont have to use timertool


----------



## 1usmus

*DRAM Calculator for Ryzen 1.6.2*


*Changelog:*

* NEW. Memory status. Information about the available memory.
* NEW. CAD_BUS received very flexible settings. Thanks to these flexible settings, it is possible to disable GDM (1T mode) without losing stability for Zen 2. DR also got the opportunity to disable GDM at low frequencies (up to 3200 MHz inclusive). Compatibility with previous generations is required to be tested.
* Updated function to determine the maximum available memory for testing (Memtest mode). At the moment, the test should not go into drives or a swap file.
* tRDWR has been changed in most profiles, this is a bonus to the chance to get a stable system.
* Most presets received small changes, in particular Micron e-die .
* Improved support for 4 modules.
* Bug fixes.

*Download:*

Techpowerup link
Guru3d link
Сomputerbase.de link

I sent an archive for all resources, it will take some time.


----------



## GlitchSpider

[email protected] 1.050v---BIOS 2501---HCI---1200%---CMK16GX4M2B3200C16


----------



## thor2002ro

i got a ryzen 2700(non-x) with AMD Wraith Max cooler on Gigabyte X470 AORUS GAMING 7 WIFI v1.1 bios F5 and a G.Skill Ripjaws V Red 32GB 3600MHz CL19 1.35v Dual Channel Kit(C die)

i run the ram at 3333mhz 16/19/20/20/40 @ 1.4v 1T gear down enabled and procODT 60
no cpu oc yet, soc voltage 1.2

I stress tested the ram about 24h with memtest64(windows app) no issues
about 10h stressapptest no issues
prime95 tested about 1h and errored out with large FFTs any ideas?


----------



## rosty

Hello , if someone has a similar setup ( 3900x - on k7 x370 * 3733 mhz memory 16 gb ( 2x8 -> viper steel ) I' m looking for some numbers if these are expected results or if this below what should i been getting . Memory is stable @ 1.5 V , with the common memtesting 400%- > i did add a small 40 mm fan over the 2 modules as they felt warm without and i do not have any temp monitoring for the modules . .


----------



## Streetdragon

thats some good stuff you have there


----------



## Brightmist

R5 3600, X370 Taichi
G.Skill 3600C16 (2x8GB) B-die kit @3600C14
SoC 1.1V, VDDG 0.95V, DRAM Voltage 1.45V (actual is probably 1.48V, that's what's showing up on HWinfo64 since X370 Taichi historically overvolted RAM)
Stock CPU settings (PBO felt like RNG)
100% Manual, Fast profile from Ryzen DRAM Calculator with BGSalt enabled, BGS disabled.
AIDA 64 latency ~69 ns.

System was booting up with 3800C16 [email protected] too but RAM latency was moving up and down 95 ns so not sure if it was stable that way. I'll just keep this untill new AGESA with a properly working PBO.


----------



## Synoxia

Both Ram tests are unrealistic for me. Not sure if i am doing something wrong, but while GSAT is quickly able to find if a ram is "just unstable" at given settings-voltage, it won't heat up ram past 42c.
HCI will heat the ram, but in an unrealistic way. Correct me if am wrong, but can you name an application that will stress the ram as much HCI does while barely using the cpu? Hwinfo show 100% load but that's not true because there's no way my 3700x can stay at 50c under full 100% load and mantain 4.2ghz speed at stock settings with a D15... any proper 100% cpu load app will throw cpu into the 65-70s... While running HCI my front fans are not spinning fast enough because they use CPU sensor and CPU is not heating at all.
Where is the problem then? After a daily use i can see ram temp is going into the 45c (higher than GSAT) and we know that after that some error can appear... so even if i am 10000 sec stable with GSAT i am still unsure of stability but HCI produces an unrealistic scenario aswell.

TLDR: HCI is like prime 95, unrealistic heat scenario that your cpu will never see, ever. But gsat is not stressing ram enough aswell


----------



## SuperPowerUp

Ryzen 2600
Asrock Fatal1ty B450 Gaming K4
G.Skill Ripjaws V F4-3200C16-8GVKB (2x8 GB) 3200mhz Samsung B-die
Win 10 Pro 64

Can someone give me some insight on why I can't run my memory stable at 3200mhz in HCI Memtest? It boots into Windows fine but I can't get it stable no matter what. I've tried upping the Dram voltage to 1.41v and VDDCR SOC to 1.15v without success. However I can pass HCI at 2933mhz stock XMP. 

I tried setting the memory with Ryzen Dram Calculator but it failed to boot. Even with 2933mhz safe settings.


----------



## makkara

@Synoxia
Maybe run GPU bench at same time with GSAT to make more heat for ram. I tested stability with HCI + Heaven bench and the RAM got to 52C, but was still stable. Also 10 cycles of TestMem5 + Heaven with 1usmus v3 test config.


----------



## Synoxia

makkara said:


> @Synoxia
> Maybe run GPU bench at same time with GSAT to make more heat for ram. I tested stability with HCI + Heaven bench and the RAM got to 52C, but was still stable. Also 10 cycles of TestMem5 + Heaven with 1usmus v3 test config.


HCI heats the ram a lot , i dont think heaven actually made a difference.

Temps after 12000 sec of GSAT... lol where using HCI litterally gave me 40c+ after 5 minutes


----------



## neurotix

rosty said:


> Hello , if someone has a similar setup ( 3900x - on k7 x370 * 3733 mhz memory 16 gb ( 2x8 -> viper steel ) I' m looking for some numbers if these are expected results or if this below what should i been getting . Memory is stable @ 1.5 V , with the common memtesting 400%- > i did add a small 40 mm fan over the 2 modules as they felt warm without and i do not have any temp monitoring for the modules . .


Yeah, these results look about right.

Your results are very close to mine, just with slightly lower bandwidth.

See the image at the bottom of my post here:

https://www.overclock.net/forum/11-...ocking-discussion-thread-85.html#post28124966


----------



## ChronoDog

oreonutz said:


> I can post formula's to help, but it generally only confuses the hell out of people unless they are good at math.


Could you, please?

I'd like to set decent 24/7 timings for 3733MHz, but it seems like the Ryzen DRAM Calculator is hell-bent on me running my RAM at CL14 even on "Safe", which is simply unrealistic without lethal (>1.5V) voltages. Using the values it gives with a V1 profile instead of Manual latencies seems to work, but I can't help but feel it could do way better, if only I knew the formulae.


----------



## centvalny

C8I with ram @ 4400 1.35V and 4866 1.5V


----------



## rastaviper

SuperPowerUp said:


> Ryzen 2600
> 
> Asrock Fatal1ty B450 Gaming K4
> 
> G.Skill Ripjaws V F4-3200C16-8GVKB (2x8 GB) 3200mhz Samsung B-die
> 
> Win 10 Pro 64
> 
> 
> 
> Can someone give me some insight on why I can't run my memory stable at 3200mhz in HCI Memtest? It boots into Windows fine but I can't get it stable no matter what. I've tried upping the Dram voltage to 1.41v and VDDCR SOC to 1.15v without success. However I can pass HCI at 2933mhz stock XMP.
> 
> 
> 
> I tried setting the memory with Ryzen Dram Calculator but it failed to boot. Even with 2933mhz safe settings.


Who told u that they are bdies?

They are not according to this:
https://benzhaomin.github.io/bdiefinder/

Sent from my ONEPLUS A6003 using Tapatalk


----------



## BLUuuE

rastaviper said:


> Who told u that they are bdies?
> 
> They are not according to this:
> https://benzhaomin.github.io/bdiefinder/
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Just because they're not on the B-die finder, doesn't mean they can't be B-die.

The B-die finder guarantees you get B-die but there are kits that can come with B-die, albeit not very good.


----------



## christoph

BLUuuE said:


> Just because they're not on the B-die finder, doesn't mean they can't be B-die.
> 
> The B-die finder guarantees you get B-die but there are kits that can come with B-die, albeit not very good.



yeah, exactly..


I bought my kit being rated 17-18-18 at 3600 Mhz, and I was shock when I opened the app and see that they are B-die so they are working at 14-15-14 3466 Mhz no problems at all


----------



## rastaviper

BLUuuE said:


> Just because they're not on the B-die finder, doesn't mean they can't be B-die.
> 
> 
> 
> The B-die finder guarantees you get B-die but there are kits that can come with B-die, albeit not very good.


Well either the motherboard doesn't like your RAM or your RAM is not very easy to be overclocked.
But I am curious. If you couldn't find these ram modules in any list of bfinder, how you are so sure that they have bdie? Did you have any inside info?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## misoonigiri

SuperPowerUp said:


> Ryzen 2600
> Asrock Fatal1ty B450 Gaming K4
> G.Skill Ripjaws V F4-3200C16-8GVKB (2x8 GB) 3200mhz Samsung B-die
> Win 10 Pro 64


By g.skill naming convention,
F4-3200C16-8GVKB would be single stick 8GB - but search on g.skill site found no results with this model#
F4-3200C16D-16GVKB would be 2 sticks of total 16GB (2x8GB) - could be Hynix MFR or Samsung D-die according to
https://www.reddit.com/r/Amd/comments/62vp2g/clearing_up_any_samsung_bdie_confusion_eg_on/
https://www.overclock.net/forum/18051-memory/1678905-f4-3200c16d-16gvkb-running-ryzen-help.html

Edit:
Ahh, from thaiphoon screenshot in 2nd link, I see thaiphoon gives model# of single dimm as F4-3200C16-8GVKB
If you got the model# & samsung b-die result from thaiphoon, then it may be so too as long as you did not misread WD-BCPB d-die as b-die (WB-BCPB)


----------



## Synoxia

Looking for B-DIE is so simple. Did you EVER find some hynix, micron chip binned at 3200c14, 3600c15? These are 100% samsung bdie.


----------



## Synoxia

I can't get this stable, idk why... it's just 45mhz over 3800 which i've been running 15-16-17-15-30-45-294TRFC at 1.445 1000% HCI stable, i losened timings and bumped voltage to 1.46, it gave 2 errors at 420% of HCI memtest... anyone has a clue?


----------



## christoph

rastaviper said:


> Well either the motherboard doesn't like your RAM or your RAM is not very easy to be overclocked.
> But I am curious. If you couldn't find these ram modules in any list of bfinder, how you are so sure that they have bdie? Did you have any inside info?
> 
> Sent from my ONEPLUS A6003 using Tapatalk



what do you mean my motherboard does not like my ram?

and you use Thaiphoon to see the info written to the ram modules, and there's where it tells you what brand and type of chip


----------



## rastaviper

Synoxia said:


> Looking for B-DIE is so simple. Did you EVER find some hynix, micron chip binned at 3200c14, 3600c15? These are 100% samsung bdie.


But the RAM above claiming to be bdie is C16.
So according to your post is doubtful to be a bdie,.right?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Synoxia

rastaviper said:


> But the RAM above claiming to be bdie is C16.
> So according to your post is doubtful to be a bdie,.right?
> 
> Sent from my ONEPLUS A6003 using Tapatalk


I dont know, i don't even dare to check, but anything that isn't highly binned is not B-DIE. B-die is very best of samsung ram which is the best ram manifacturer, which is why you want b-die ram. 
My B-DIE is 3600 c17-18, not as good bin as 3200c14 but it served me well on all 3 generations of ryzen, it can run 3200 c12 stable, 3533 c14 gdm off stable, 3800c15 gdm off stable.
G-SKILL usually uses only b-die but a 3200c16 kit sounds very suspect to me... just buy an higher bin and call it a deal.


----------



## hazium233

*tRCDRD is a Harsh Mistress*

I have been stubbornly trying to work on tRCDRD a little on my Micron Rev D set. They are out of a Ballistix Sport AT 2666 16-18-18-38-61 1.2v set. With a 1600 on a X370-F (4012 Pinnacle 1.0.0.2). Previously I had them on a B350-F, there should be a couple previous posts in here.

Anyway, I had gone back to XMP ish timings on the new board. Previously with tRCDRD 18 I had some runs that did >400%/thread in HCI but then failed longer runs. I since bought Ram Test and have been using that in an attempt to speed things up.

Decided to try some more volts and basically I have had the test go like this (percent until error):

1.345 - 129% (ha)
1.35 - 2340%
1.35 - 3302% -> modified some sub timings, VTTDDR +1 notch
1.36 - 6117%
1.36 - 2381% -> modified RAS and RDWR, WRRD.
1.365 - 9825% - RTC attached 

I might try another bump. Although the bios lets me increment 0.005V, I am not entirely sure what it is doing in reality. Also, this last test I had ProcODT a little lower than I used for most other tests at 3200. I am not sure I can find a consistent difference between 43.6 and 48 ohm at this speed, but that was a mistake for this test and a little bit confounding. I also had dropped tRTP and tWR lower than they had been set in some other tests.

I'm considering pulling a stick and testing them one at a time to see if there is just one dud, or if both are duds. Or maybe redo the last batch with VTTDDR modified.

I have CLDO_VDDP set to 950mV. I have Digi VRM settings to basically all auto (don't think that could be it but I don't know).


----------



## neurotix

If anyone is looking for great B-Die, guaranteed, real cheap, try my kit. Its 3200 C14 guaranteed Samsung Bdie and I run it at 3800 c16 100% stable in an hour of terminal stresstestapp on Debian 10 (Linux is my main OS). It does 3600 c14 too but I do get greatly improved bandwidth and lower latency in AIDA64 at 3800 c16 (> 64ns with a lot of Windows tweaks). It runs at well under 1.5v, I forget what I eventually settled on but its like 1.460 or something (have to check)

It also passed 2400% (100% coverage all threads or w/e) in the latest Ryzen Dram Calc Memtest using all available physical memory.

(No screenshots sorry, on my phone atm)

https://www.amazon.com/G-SKILL-Flar...3131&s=gateway&sprefix=g.skill+flare+x&sr=8-1

I paid $119- price has gone up since.  I paid $120 and got better than a kit worth 5 times that that probably has higher cas at 3800 in its XMP profile. This kit is awesome.


----------



## Keith Myers

neurotix said:


> If anyone is looking for great B-Die, guaranteed, real cheap, try my kit. Its 3200 C14 guaranteed Samsung Bdie and I run it at 3800 c16 100% stable in an hour of terminal stresstestapp on Debian 10 (Linux is my main OS). It does 3600 c14 too but I do get greatly improved bandwidth and lower latency in AIDA64 at 3800 c16 (> 64ns with a lot of Windows tweaks). It runs at well under 1.5v, I forget what I eventually settled on but its like 1.460 or something (have to check)
> 
> It also passed 2400% (100% coverage all threads or w/e) in the latest Ryzen Dram Calc Memtest using all available physical memory.
> 
> (No screenshots sorry, on my phone atm)
> 
> https://www.amazon.com/G-SKILL-Flar...3131&s=gateway&sprefix=g.skill+flare+x&sr=8-1
> 
> I paid $119- price has gone up since.  I paid $120 and got better than a kit worth 5 times that that probably has higher cas at 3800 in its XMP profile. This kit is awesome.


I agree, I picked up this kit back in June for $125. I have always bought Trident-Z kits previously, but since they are getting hard to find with CL14, this was a no brainer. Very happy with the kit.


----------



## neurotix

Keith Myers said:


> I agree, I picked up this kit back in June for $125. I have always bought Trident-Z kits previously, but since they are getting hard to find with CL14, this was a no brainer. Very happy with the kit.


Awesome rigs good gawd. Is the gov. paying for those? Jeez.

That amount of flops for [email protected] is something I can only dream of. It'd be well over 100mil PPD. Very nice. Fellow *nix user too. Thanks for your vote of confidence!

Ryzen DRAM Calc since it's update says my bin is 94% (under "memory quality") and is telling me they're capable of 4266 CAS16 or something like that but I'm sure that's pretty exaggerated.


----------



## Keith Myers

neurotix said:


> Awesome rigs good gawd. Is the gov. paying for those? Jeez.
> 
> That amount of flops for [email protected] is something I can only dream of. It'd be well over 100mil PPD. Very nice. Fellow *nix user too. Thanks for your vote of confidence!
> 
> Ryzen DRAM Calc since it's update says my bin is 94% (under "memory quality") and is telling me they're capable of 4266 CAS16 or something like that but I'm sure that's pretty exaggerated.


I am pushing the standard TridentZ 3200CL14 16gb kit to 3600CL14 on my Ryzen 3900X rig. I probably could go to 3733CL14 or even 3800CL15.


----------



## Keith Myers

neurotix said:


> Awesome rigs good gawd. Is the gov. paying for those? Jeez.
> 
> That amount of flops for [email protected] is something I can only dream of. It'd be well over 100mil PPD. Very nice. Fellow *nix user too. Thanks for your vote of confidence!
> 
> Ryzen DRAM Calc since it's update says my bin is 94% (under "memory quality") and is telling me they're capable of 4266 CAS16 or something like that but I'm sure that's pretty exaggerated.


From everything I've read in the C7H OCN forums, there is no point in going past 1900Mhz FCLK for a 1:1 memory clock. You may/might post better benchmark numbers but for a crunching rig running 24/7, the ability to maintain and hold low latency is the key to getting better application speeds. Particularly with science or compute apps.


----------



## rastaviper

Keith Myers said:


> I agree, I picked up this kit back in June for $125. I have always bought Trident-Z kits previously, but since they are getting hard to find with CL14, this was a no brainer. Very happy with the kit.


Currently running my 3200C15D-16GTZ at *3732* 16-15-15, 1.37v 
Stable enough for CB R20 and for many hours of gaming with Ghost Recon Wildlands at Ultra settings.
Super Pi 1m at* 9.125 *with cpu 3600x at 4500mhz


----------



## neurotix

Keith Myers said:


> From everything I've read in the C7H OCN forums, there is no point in going past 1900Mhz FCLK for a 1:1 memory clock. You may/might post better benchmark numbers but for a crunching rig running 24/7, the ability to maintain and hold low latency is the key to getting better application speeds. Particularly with science or compute apps.





rastaviper said:


> Currently running my 3200C15D-16GTZ at *3732* 16-15-15, 1.37v
> Stable enough for CB R20 and for many hours of gaming with Ghost Recon Wildlands at Ultra settings.
> Super Pi 1m at* 9.125 *with cpu 3600x at 4500mhz


I've got the C8H but it depends on your chip and it's IMC. C7H should do well afaik.

You are absolutely correct; there is no point in trying to go above 1900MHz IFclk. I've seen many forum posts in the C8H OC thread showing clockers with pretty extreme memory running above 4000Mhz, 1900 fclk. You get a 10ns latency penalty when not running at 1:1, but at even 4266MHz with very low timings it's basically totally made up for, given you have a kit that will do it. (I doubt ours will and haven't tried.) The one person I saw was 4266Mhz @ something crazy like 12-12-14-13-26-32 1T or roundabout. If you read back in the CH8 thread you'll see it eventually. The bandwidth was well above 60GB/sec on all, including write, and the latency was 61ns range.  (In the latest AIDA64 under W10) No clue if they were using extreme cooling or not but I think it was just just custom water. No idea about voltage or a ram fan kit. Nor stability.

None of these guys/people even try to go above 1900, it's basically impossible, I don't know about under LN2 though. You probably won't POST if you try no matter what you do. I'm not going to dig up some of the reddit links I've posted there but in one of my posts I linked a chart a reddit user did on Google Sheets showing a bunch of RAM speeds and timings all the way to 4333MHz (I believe) on 3900x, vs i9 9900k, and he demonstrably showed percentage scaling of the 3900x with high speed RAM across about 10 current games scales fantastically, improving FPS significantly, and giving the 3900x higher performance in gaming than a 9900k highly clocked with very fast RAM. He also showed the sweet spot for this to be 1900 Fclk, 3800MHz memory with any higher memory speeds performing a little worse. (He also did not try to maintain 1:1 ratio above 3800MHz because again, raising it higher is impossible so far.) If you can find this it's very well done but I don't have the link on hand, sorry.

This is my rig at my current speed in AIDA:









Think I may have posted it in this thread already but whatever, there ya go. No reading back.


It is well worth aiming for 1900 Fclk and 3800 RAM if you're after latency. Big improvement. Decent improvement over 3600 C14 but not as good as going from 3200 C14 to that. The latest bios for my board supposedly lowers that latency by 1ns according to some users. I haven't gone to it because people haven't answered when I asked them if the 1001 bios has per CCD/CCX ratio and VID overclocking or not compared to the Shamino bios I use from ROG forums. The_Stilt's modified bios for this board is supposed to be very good too. I'd suggest trying 16-16-17-16-32-50 1T if you want to attempt it, and the rest of my timings are from the latest Ryzen DRAM Calc with imported stats of my kit from Taiphoon Burner. The subtimings had to be loosened considerably but the latency was still lower with greater bandwidth (according to AIDA anyway- you might be able to prove that wrong if you're a Linux guru and know about programs for that stuff that I don't. Maybe a BOINC or [email protected] memory stat and stability test- [email protected] had one of these for GPUs at one point a long time ago). 

Fclk 1900 gives you lower latency across all tiers of processor cache as well. And slightly higher bandwidth. It's very small but consistent, so I don't think it's a margin of error deal.

I was trying various combinations of timings at 3800 C14 but my board would not post above 1800 Fclk, it wasn't until I backed off and especially raised subtimings. BankGroupSwapAlt enabled seems to help too but I have BGS totally off.

Hope this is helpful...


----------



## Keith Myers

I don't game so increased FPS is meaningless to me. I care about application speed and transaction speed. Those are the material things that matter in my use case. Anything that speeds up floating point calculations is my target goal. That normally means increased cpu clock speeds. But the next best improvement is a speedup in transactions that need memory access.


----------



## Keith Myers

For testing stability, GSAT for memory and Prime95 for cpu clocks and memory. For benching performance gains, Intel Memory Latency Checker is best for seeing memory throughput and latencies. For application benches, then Geekbench gives a good overall picture for all application types but the final arbiter are my BOINC science applications.


----------



## hazium233

*tRCDRD is a Harsh Mistress 2*

Micron D sticks, needed a little more volts. (Crucial BLS8G4D26BFSTK - MT40A1G8WE-075E: D - 2666MT/s 16-18-18-38 1.2V)

Played with a couple other settings at 1.365V that did not improve anything. Should have just went to 1.37 the other day. 16-18/18-18-36 3200MT/s.

Hit 10346% coverage in Ram Test and I manually shut it off. It needs more testing, although if I am going to bother it will need to outperform the old 16-19/16-18-42 profile, or come close (I might go back to leaving tRFC alone though).

Might try to get a decent set at CL 14. A while back I had tested 14-18-18-36 3200MT/s 1.35V to 400% in HCI, maybe I will try to make it "rock stable."

Playing around with all the sub timings at 1.35V was an interesting adventure though.


----------



## hazium233

Keith Myers said:


> For testing stability, GSAT for memory and Prime95 for cpu clocks and memory. For benching performance gains, Intel Memory Latency Checker is best for seeing memory throughput and latencies. For application benches, then Geekbench gives a good overall picture for all application types but the final arbiter are my BOINC science applications.


How long do you tend to test with GSAT?

The most strange case I had was where I passed 2hr of GSAT, and then proceeded to fail HCI at like 1.7% or so coverage. Changed a couple settings and sailed through. Ultimately this might have been ProcODT mostly, and dimm voltage 1.34 partially to blame.

From the admittedly short time I have spent this half year I am wondering about some of these tests. Not so much the specifics of every test, but more generally the idea of how much testing is "finding" errors and how much is "creating" errors.

For instance, above timings would chug happily along at 1.35V in memtest86 for longer than that Ram Test (indeed, ran tRCDRD at 18 with similar timings a few days ago for 4 cycles of 16 tests, and had run it in other profiles through that test before).

I don't have the capability to measure dimm temperatures, but the system is in a Meshify C with two intake fans and a rear exhaust, and I have the stock Wraith Spire, so dimms should get ok airflow. Have read some comments on this, I assume memtest86 is keeping things fairly cool, have read GSAT is cooler than HCI. In that case I suppose HCI (or maybe Ram Test as well) should need more dimm voltage than GSAT, and indeed have read comments to that effect.


----------



## rastaviper

neurotix said:


> I've got the C8H but it depends on your chip and it's IMC. C7H should do well afaik.
> 
> 
> 
> You are absolutely correct; there is no point in trying to go above 1900MHz IFclk. I've seen many forum posts in the C8H OC thread showing clockers with pretty extreme memory running above 4000Mhz, 1900 fclk. You get a 10ns latency penalty when not running at 1:1, but at even 4266MHz with very low timings it's basically totally made up for, given you have a kit that will do it. (I doubt ours will and haven't tried.) The one person I saw was 4266Mhz @ something crazy like 12-12-14-13-26-32 1T or roundabout. If you read back in the CH8 thread you'll see it eventually. The bandwidth was well above 60GB/sec on all, including write, and the latency was 61ns range.  (In the latest AIDA64 under W10) No clue if they were using extreme cooling or not but I think it was just just custom water. No idea about voltage or a ram fan kit. Nor stability.
> 
> 
> 
> None of these guys/people even try to go above 1900, it's basically impossible, I don't know about under LN2 though. You probably won't POST if you try no matter what you do. I'm not going to dig up some of the reddit links I've posted there but in one of my posts I linked a chart a reddit user did on Google Sheets showing a bunch of RAM speeds and timings all the way to 4333MHz (I believe) on 3900x, vs i9 9900k, and he demonstrably showed percentage scaling of the 3900x with high speed RAM across about 10 current games scales fantastically, improving FPS significantly, and giving the 3900x higher performance in gaming than a 9900k highly clocked with very fast RAM. He also showed the sweet spot for this to be 1900 Fclk, 3800MHz memory with any higher memory speeds performing a little worse. (He also did not try to maintain 1:1 ratio above 3800MHz because again, raising it higher is impossible so far.) If you can find this it's very well done but I don't have the link on hand, sorry.
> 
> 
> 
> This is my rig at my current speed in AIDA:
> 
> 
> 
> View attachment 296728
> 
> 
> 
> 
> Think I may have posted it in this thread already but whatever, there ya go. No reading back.
> 
> 
> 
> 
> 
> It is well worth aiming for 1900 Fclk and 3800 RAM if you're after latency. Big improvement. Decent improvement over 3600 C14 but not as good as going from 3200 C14 to that. The latest bios for my board supposedly lowers that latency by 1ns according to some users. I haven't gone to it because people haven't answered when I asked them if the 1001 bios has per CCD/CCX ratio and VID overclocking or not compared to the Shamino bios I use from ROG forums. The_Stilt's modified bios for this board is supposed to be very good too. I'd suggest trying 16-16-17-16-32-50 1T if you want to attempt it, and the rest of my timings are from the latest Ryzen DRAM Calc with imported stats of my kit from Taiphoon Burner. The subtimings had to be loosened considerably but the latency was still lower with greater bandwidth (according to AIDA anyway- you might be able to prove that wrong if you're a Linux guru and know about programs for that stuff that I don't. Maybe a BOINC or [email protected] memory stat and stability test- [email protected] had one of these for GPUs at one point a long time ago).
> 
> 
> 
> Fclk 1900 gives you lower latency across all tiers of processor cache as well. And slightly higher bandwidth. It's very small but consistent, so I don't think it's a margin of error deal.
> 
> 
> 
> I was trying various combinations of timings at 3800 C14 but my board would not post above 1800 Fclk, it wasn't until I backed off and especially raised subtimings. BankGroupSwapAlt enabled seems to help too but I have BGS totally off.
> 
> 
> 
> Hope this is helpful...


Half of your numbers are like double than mine!!
How did u do that??
I guess also the CPU is affecting such results.











Sent from my ONEPLUS A6003 using Tapatalk


----------



## Keith Myers

Well since I don't run Windows, I have limited applications that I can test with. For GSAT, I basically use it to quickly zero in on prospective settings. I normally run a 15 minute test and if it fails, go back and try something different. If 15 minute passes, then test for 30 minutes. If that passes, I move on to an hour of Prime95 small FFT with 12000MB of RAM used. That most closely resembles my actual BOINC load. It that passes, I deploy the settings on BOINC. Normally if the settings I use on Prime95 work, I never have any issues with BOINC. If I start getting sigsegv errors, I know that memory is unstable and need to revisit my prior testing with longer test runs.
I agree that GSAT does not heat up the RAM that much as it does when the cpu is crunching also. I don't have any way of monitoring memory temps via software. All I can do is shoot the memory with a IR temp gun. I have very good ventilation in all my cases so I don't think that the memory ever gets unreasonable in temps leading to memory corruption. My systems are very stable. They only get rebooted when I get around to looking at them and notice a month's worth of updates pending.


----------



## neurotix

rastaviper said:


> Half of your numbers are like double than mine!!
> How did u do that??
> I guess also the CPU is affecting such results.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sent from my ONEPLUS A6003 using Tapatalk



Yep, you are correct sir.

If I don't have this wrong, anything that's not a 3900x has half the memory write speed and slower cache. This is because 8 core Ryzen 3000 and under only have 1 cpu die instead of 2 linked together by Infinity Fabric. The 2 together have more cache, and get higher throughput because of the way IF works.

I think I might have heard that its anything less than a 3800x that has halved memory write speed but I'm uncertain.

EDIT: And AMD really should be more transparent about this themselves so consumers don't compromise on the CPU to get faster RAM or a higher tiered board if they aren't made of money. 

Don't worry about it though, guy: if you're just playing games, you probably won't see a difference. Try to get your CPU to run or boost to 4500+ (or whatever the max for that chip is) and don't worry about RAM as much. Chances are at the same speeds with the same graphics card that both our systems would perform very close or identically in gaming.


----------



## hazium233

Keith Myers said:


> Well since I don't run Windows, I have limited applications that I can test with. For GSAT, I basically use it to quickly zero in on prospective settings. I normally run a 15 minute test and if it fails, go back and try something different. If 15 minute passes, then test for 30 minutes. If that passes, I move on to an hour of Prime95 small FFT with 12000MB of RAM used. That most closely resembles my actual BOINC load. It that passes, I deploy the settings on BOINC. Normally if the settings I use on Prime95 work, I never have any issues with BOINC. If I start getting sigsegv errors, I know that memory is unstable and need to revisit my prior testing with longer test runs.
> I agree that GSAT does not heat up the RAM that much as it does when the cpu is crunching also. I don't have any way of monitoring memory temps via software. All I can do is shoot the memory with a IR temp gun. I have very good ventilation in all my cases so I don't think that the memory ever gets unreasonable in temps leading to memory corruption. My systems are very stable. They only get rebooted when I get around to looking at them and notice a month's worth of updates pending.


Right. That seems pretty logical.

My system is just used for entertainment, I don't really know what a good approximation for games truly is. Some of them are buggy and crash with factory default settings from time to time and don't make great stability tests.

I kind of wish Realbench had better customization for memory used. I downloaded Y-cruncher, but I think in the end I think I will stick with Prime for that sort of stress.


----------



## sideeffect

Upgraded my RAM to 2x16GB Ballistix E die (3000 15-16-16) got them for £126 on Amazon which is a good price in the UK.

My 3700x wont boot at 1900 FCLK requires around 1.125v SOC for 1866 stable so I have decided to run it at 1833 FCLK where it's stable at 1.05v SOC. Vdimm voltage is 1.405v. BIOS is 5214 modified with spread spectrum disabled.


----------



## rastaviper

sideeffect said:


> Upgraded my RAM to 2x16GB Ballistix E die (3000 15-16-16) got them for £126 on Amazon which is a good price in the UK.
> 
> 
> 
> My 3700x wont boot at 1900 FCLK requires around 1.125v SOC for 1866 stable so I have decided to run it at 1833 FCLK where it's stable at 1.05v SOC. Vdimm voltage is 1.395v. BIOS is 5214 modified with spread spectrum disabled.


Why the L1 is so much better than my 3732 16-15-14?
Is the 3700x influencing so much more the result in comparison to the 3600x?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## sideeffect

@rastaviper

My friends 3600 on an MSI B450 has cache scores similar to yours also. 

Edit - The L1 and L2 scores are 25% higher on 3700x and 3600x has 25% less cores so maybe something to do with the benchmark utilising those extra L1 and L2 caches in parallel.


----------



## hazium233

More Micron Rev D adventures.

Upped dimm voltage by 0.005 to 1.375V, due to maybe the voodoo of matching real VTTDDR step to 1/2 dimm voltage, and tested with slightly tweaked tRC and tFAW down to 24. Passed an hour GSAT in PuppyLinux and then >10500% in Ram Test. Improved CB R20 by a tiny amount, AIDA RNG went up maybe.

Have been using a new lower ProcODT of 43ohm. I have not tried to see if SOC will come down with it.

I either need to go for a daily 3200 C14 or try higher frequencies.

Anyway it was interesting to see that I could move tRCDRD down a little with dimm voltage.


----------



## kingzize

Im running this 24/7 stable config:

2x8GB F4-3600C15-8GTZ


----------



## rastaviper

Anyone with Bdies F4-3200C15D-16GTZ that manages to keep them stable at 3800?


----------



## Swissola

kingzize said:


> Im running this 24/7 stable config:
> 
> 2x8GB F4-3600C15-8GTZ


 @kingzize What are your voltages like? VDDG and VDDP in particular?


----------



## kingzize

Swissola said:


> What are your voltages like? VDDG and VDDP in particular?


DIMM: 1.44v
SOC: 1.1v
VDDP: 0.98v
VDDG: 0.96v


----------



## Serchio

kingzize said:


> Im running this 24/7 stable config:
> 
> 
> 
> 2x8GB F4-3600C15-8GTZ




Thanks mate!

2x8GB F4-3200C14-8GTZ


----------



## dufus

*best asus x470-i bios for ddr4 overclock 2700x*

Dear all,

Is there consensus on which bios is the best for ddr4 speeds on the asus strix x470-i combined with 2700X and g.skill F4-3200C14-8GFX (flareX 2x8gb)? I used to run bios version 1201 and got [email protected] from dram calc, but curiousity got the better of me and after several bios upgrades I never got it stable again. Now I am on bios version 2703 and the best I got is 3200 safe. BIOS downgrade is a pain in the ***, so have any of you had luck with any of the more recent bioses?

Also, is there a consensus on the best procODT and cam_bus settings for this combination?

Best regards,


----------



## CelticGamer

I just recently swapped out my 2700X for a 3800X, and I'm trying to figure out why the latency on my RAM has raised 5ns, using the same exact settings as I used on the 2700X.

I'm wondering if there is some setting on these MSI boards that I have neglected to change.


----------



## Keith Myers

CelticGamer said:


> I just recently swapped out my 2700X for a 3800X, and I'm trying to figure out why the latency on my RAM has raised 5ns, using the same exact settings as I used on the 2700X.
> 
> I'm wondering if there is some setting on these MSI boards that I have neglected to change.


You have a different memory access architecture now. You have to go through the I/O die to memory on the 3800X when the 2700X directly accessed memory through the IMC of the cpu die on that part.


----------



## sideeffect

CelticGamer said:


> I just recently swapped out my 2700X for a 3800X, and I'm trying to figure out why the latency on my RAM has raised 5ns, using the same exact settings as I used on the 2700X.
> 
> I'm wondering if there is some setting on these MSI boards that I have neglected to change.


It's normal that memory performance particularly latency is worse on Zen 2 than Zen+. In Zen 2 AMD moved the memory controller out of the main CPU chiplet and into a secondary IO chiplet this has increased latency but AMD have mitigated the impact by adding more L3 cache (Gamecache). 3800x also has half the memory write bandwidth of the 2700x.


----------



## CelticGamer

I appreciate the explaination. I guess I will just have to spend some time shaving off as much latency as possible.


----------



## kingzize

Serchio said:


> Thanks mate!


You're welcome


----------



## rastaviper

Hey guys,
Any recommendations for pushing my 3200 Gskill C15 bdies at 3800?

I can use them stable at 3733 at 16-15-14 1T, 1.37v, but no matter what I try, they don't even post at 3800 16-16-16. Pc freezes and need to reset bios every time to continue.

Increased vdpp, vdgg, ram voltage didn't help

Sent from my ONEPLUS A6003 using Tapatalk


----------



## savagebunny

Finally pushed for stable 3733 the other night. If I want > 60k copy, must run CL 14, but 24/7 I keep it at 16. Just wanted to break a personal best over 60k copy. 3800Mhz is next for sub 63ns, problem on my board, or chip is memory training at 3733, sometimes doesn't survive reboot, all related to AGESA. 

VDIMM: 1.50v in Windows
VDDG: 975mv
VDDP: 900mv
SOC: 1.1v



rastaviper said:


> Hey guys,
> Any recommendations for pushing my 3200 Gskill C15 bdies at 3800?
> 
> I can use them stable at 3733 at 16-15-14 1T, 1.37v, but no matter what I try, they don't even post at 3800 16-16-16. Pc freezes and need to reset bios every time to continue.
> 
> Increased vdpp, vdgg, ram voltage didn't help
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Start from default if you wanna target 3733. Voltage is way to low. Set to 1.5v, Disable XMP, 16-16-16-32, 3733Mhz, If not set to 3600 then work from there.


----------



## rastaviper

savagebunny said:


> Finally pushed for stable 3733 the other night. If I want > 60k copy, must run CL 14, but 24/7 I keep it at 16. Just wanted to break a personal best over 60k copy. 3800Mhz is next for sub 63ns, problem on my board, or chip is memory training at 3733, sometimes doesn't survive reboot, all related to AGESA.
> 
> VDIMM: 1.50v in Windows
> VDDG: 975mv
> VDDP: 900mv
> SOC: 1.1v
> 
> 
> 
> Start from default if you wanna target 3733. Voltage is way to low. Set to 1.5v, Disable XMP, 16-16-16-32, 3733Mhz, If not set to 3600 then work from there.


Probably you have misread my post.
I am stable at 3733 already.
I want to push for 3800 though and I am asking for advice for this part.
For 3733 I don't need so high Voltage as u. 
1.37v is working fine for me for 16-15-14


----------



## mongoled

Just wanted to add this as I see this rarely mentioned.

I see some people hitting latency lower than 63ns, very rarely could I achieve this so I chalked that down to an anomaly.

However I now know the reason (in hindsight should have been evident).

Latency is tied also to CPU frequency (this also effects throughput)!

When my CPU chooses to run the latency test on C01 I get results lower than 63 ns on my setup.

Just something to keep in mind when looking at latency results .........


----------



## mongoled

rastaviper said:


> Probably you have misread my post.
> I am stable at 3733 already.
> I want to push for 3800 though and I am asking for advice for this part.
> For 3733 I don't need so high Voltage as u.
> 1.37v is working fine for me for 16-15-14


I use the settings below, my set though is F4-3600C15D-16GTZ.

As your RAM sticks are a result of binning there is a good chance you can run similar settings

1.44 volts
tCL: 15
tRCDWR: 10
tRCDRD: 17
tRP: 15
tRAS: 28
tRC: 42
tRRDS: 4
tRRDL: 6
tFAW	16
tWTRS: 4
tWTRL: 8
tWR: 12
tRDRD SCL: 4
tWRWR SCL: 4
tRFC	: 266
tCWL: 14
tRTP: 12
tRDWR: 10
tWRRD: 1
tWRWR SC: 1
tWRWR SD: 7
tWRWR DD: 7
tRDRD SC: 1
tRDRD SD: 5
tRDRD DD: 5
tCKE: 1


----------



## rastaviper

mongoled said:


> I use the settings below, my set though is F4-3600C15D-16GTZ.
> 
> As your RAM sticks are a result of binning there is a good chance you can run similar settings
> 
> 1.44 volts
> tCL: 15
> tRCDWR: 10
> tRCDRD: 17
> tRP: 15
> tRAS: 28
> tRC: 42
> tRRDS: 4
> tRRDL: 6
> tFAW	16
> tWTRS: 4
> tWTRL: 8
> tWR: 12
> tRDRD SCL: 4
> tWRWR SCL: 4
> tRFC	: 266
> tCWL: 14
> tRTP: 12
> tRDWR: 10
> tWRRD: 1
> tWRWR SC: 1
> tWRWR SD: 7
> tWRWR DD: 7
> tRDRD SC: 1
> tRDRD SD: 5
> tRDRD DD: 5
> tCKE: 1


So with this setup u managed to stabilize your Ram at 3800?

To be honest, I never tried to setup my Ram voltage over 1.4v
What about your vddp and vddg? you don't have any special settings for them?


----------



## mongoled

rastaviper said:


> So with this setup u managed to stabilize your Ram at 3800?
> 
> To be honest, I never tried to setup my Ram voltage over 1.4v
> What about your vddp and vddg? you don't have any special settings for them?


Yes,

Nope at defaults, though some people had to reduce voltage for those (vddp and vddg) to get stability ....

See screen shot below (currently running DRAM test +1016 mins...)


----------



## rastaviper

What about XMP profile?
Does it help if it's On or OFF?
Currently I have it On while keeping active the 3733 settings.

Also @mongoled check your PM :specool:


----------



## mongoled

rastaviper said:


> What about XMP profile?
> Does it help if it's On or OFF?
> Currently I have it On while keeping active the 3733 settings.
> 
> Also @mongoled check your PM :specool:


Dont use XMP,

manually type your settings


----------



## neurotix




----------



## rastaviper

mongoled said:


> Dont use XMP,
> 
> 
> 
> manually type your settings


I do put manually all my settings even if XMP is On.
Normally this shouldn't happen?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## mongoled

rastaviper said:


> I do put manually all my settings even if XMP is On.
> Normally this shouldn't happen?
> 
> Sent from my ONEPLUS A6003 using Tapatalk


If you used XMP in the past its better you reset your BIOS to defaults than enter the settings manually.

XMP can sometimes apply settings we cannot see and cannot change.


----------



## MFarkha

Hello all - looking for some help here.

I have a 3900x w/ the x570 Aorus Pro. I just finished overclocking my RAM using the DRAM calculator and when I went from SAFE --> FAST timings I hear the USB disconnect and immediately reconnect sound constantly whenever I run a RandomX benchmark (crypto mining) - the sounds start initially, doesn't take time for them to manifest. Initially, my impression that this was a stability issue but I can't seem to re-create this barrage of disconnect/reconnect sounds with p95, IBT, realbench, CSGO, GW2.

With the FAST settings I've ran: p95 blend --> 4 hours; realbench --> 4 hours; MEMbench --> individual threads to 400%; IBT --> Maximum 10 runs. None of these reproduce the disconnect/reconnect barrage of sounds.This only started once I went from SAFE --> Fast as the benchmark ran without this USB disconnect/reconnect sound issue with SAFE settings. What's weird is that all of my USB devices work flawless while it appears to be disconnecting and reconnecting so I suspect that this is happening on the microsecond level.

Is there a specific time or voltage that impacts the USB controller the most? I'm presently at 1.46 Volts (samsung b-die) with 1.12 SOC, VDDG 1.075 and VDDP at 1.1. Thank you!

Edit: I downloaded a USB viewer tool and I have an external HD that keeps reconnecting and disconnecting. A clue I suppose.


----------



## MFarkha

Found the issue. For some reason, plugging my external HD into a USB 2.0 slot made it stop cycling.


----------



## sideeffect

MFarkha said:


> Found the issue. For some reason, plugging my external HD into a USB 2.0 slot made it stop cycling.


It's often the SOC voltage being too low that can cause USB issues but I have also had USB problems from too many devices being on a Hub like on my monitor if I connect 4 devices I have issues with disconnects but 3 devices is fine. I also had issues with my USB headset for a long time with my B350 board that went away with the 1903 update/newer chipset drivers.

I really like USB viewer tool though I used to use it a lot when I was having problems with the headset.


----------



## GeneralHARM

any tips for getting rid of errors with this setup, i can post, boot, pass easy MEMbench, but i always get errors in Kahru well before 1000% coverage.


----------



## oreonutz

ChronoDog said:


> Could you, please?
> 
> I'd like to set decent 24/7 timings for 3733MHz, but it seems like the Ryzen DRAM Calculator is hell-bent on me running my RAM at CL14 even on "Safe", which is simply unrealistic without lethal (>1.5V) voltages. Using the values it gives with a V1 profile instead of Manual latencies seems to work, but I can't help but feel it could do way better, if only I knew the formulae.


Sorry, been offline for a bit, have had a lot going on. This won't get you all the way there this is still going to include significant work on your part, but this will get you started. How you use it is to use Thaiphoon Burner to grab the Nanoseconds of your timings at your Rated CL and Speed. Then the goal is to keep either at Or below that Nano Seconds to Complete when Raising your Speed by using the "How to Solve For CL when Desired Clock Speed & Nano Seconds Is Known" Calculation to calculate for each timing at that speed. You also have to realize that a lot of timings relate to each other, so looking up past articles made on Tech Powerup by 1usmus will help with that theory. But this is just a very very 1000 Foot High View to hopefully get you started. Also realize that 1usmus makes a VERY powerful tool, but for best results you need to make sure you are using Thaiphoon Burner to get your Specific Kits Profile in Nano Seconds, and then Use that Profile in Ryzen Memory Calculator. A lot of people think they are using their Profile from Thaiphoon Burner, but the second you Choose Profile 1 or 2 In Ryzen Timing Calc it switches to a using a Profile that 1usmus baked in, and not yours. You need to switch it To Manual, then import your Profile, and make sure to not switch it off manual, then you will get results for your specific kit, even when going as high as 3733Mhz. Even so, here is a little theory to get you started. Keep in mind, I am no Memory Guru like 1usmus, just an Enthusiast who got curious and went out and did some light research.



Spoiler



Ram Nano Second Timings Calc Equation

(1 ÷ {Half of Ram Clock Speed}) x [Cas Latency Timing] = Time in Nano Seconds to complete Calculation.

ex.

If my RAM is 3200Mhz, and my CL is 14 Then The Equation looks like=

(1 ÷ 1.6) x 14 = nano seconds = 8.75 nano Seconds

as opposed to the same Ram Kit running at 3200Mhz at CL16

(1 ÷ 1.6) x 16 = 10 Nano Seconds
_Lower Nano Seconds Result is Better_

More Examples:
3466 @ CL15 = 8.655510675129833

3466 @ CL16 = 9.232544720138488

4000 @ CL17 = 8.5

3800 @ CL16 = 8.421052631578947

3733 @ CL15 = 8.036431824270024

3600 @ CL14 = 7.777777777777778

3800 @ CL15 = 7.894736842105263
_________________________________________________

How to Solve For CL when Desired Clock Speed & Nano Seconds Is Known 
_ex. is 3466Mhz with 8.75 nano seconds) = {CAS LATENCY}_

(1 ÷ 1.733 {Half of Clock Speed in Ghz}) x n{Unknown CAS Latency} = 8.75 {Known Nano Seconds}

0.577n = 8.75n {Now Divide each side by 0.577 to isolate n}

n = 8.75 ÷ 0.577

n = 15.16

_*In This Example The Desired CAS Latency to Plug in at this speed would be 15*_
__________________________________________________________

THEORETICAL MAX BANDWIDTH CALCULATION

MAX BANDWIDTH OF BUS (64Bit Per Channel) x Effective Memory Clock (Rated Speed) ÷ 8 = Theoretical Max

So My Ram is 3200Mhz on a Dual Channel Board. This looks like;

(128Bits x 3200Mhz) ÷ 8 = 51,200MBps 

Current Aida Read Result is: 49,606 / That is 96% Of the Max Theoretical Read Speed

If Triple Channel Memory at 1066Mhz Then

(192Bits x 1066Mhz) ÷ 8 = 25,584MBps 

Current Aida Read Result is 23,859 / That is 93% of the Max Theoretical Read Speed

Ex on Current Memory On Ryzen 3000 setup.

(128bits x 3800Mhz) ÷ 8 = 60,800MBps 

Result 1 for Aida Read Result = 59,268 / Thats 97% of Max Theoretical Read
Result 1 for Aida Write Result = 56,146 / Thats 92.3% of Max Theoretical Write

Result 2 For Aida Read Result = 60,189 / Thats 98.99% of Max Theoretical Read
Result 2 For Aida Write Result = 56,477 / Thats 92.3% of Max Theoretical Write


----------



## neurotix

+rep to oreonutz (lol)

This is basically correct.

The right way to use Ryzen Dram Calculator is:

1) You need Thaiphoon Burner as stated. (Many AV report it as a false positive because it has code that contains low-level functions, likely in ASM, that query the SMBus, etc. to retrieve the data programmed into the SPD chips on the DIMMs. The program is safe.) Near the top menu bar is a button that is something like 'Read SPD' or 'Read XMP'. Click it.

2) Thaiphoon generates a report that pops up in a window. *MAKE SURE YOU SCROLL DOWN TO THE BOTTOM AND CHECK THE CHECKBOX, 'SHOW TIMINGS IN NS'!!!* Last time I used the program, for the life of me, I could not find this option again. If you miss this step, DRAM Calc will *bleep* at you and refuse to load your profile.

3) After doing that, Thaiphoon has an option in a dropdown menu or a button, 'Export Profile'. *You need to pick 'export full html profile' out of the various options.* Navigate to the folder you have Ryzen DRAM Calculator in, and save the html report there.

4) Open Ryzen Calc, and at the bottom, above 'Import XMP', click reset. Then click 'Import XMP' and select the html file. If you did this correctly, you will see the exact model number, specs etc. of your specific memory in the top-right of the application now. If you follow my instructions exactly, you will notice that it has some (expensive) high frequency Gskill DRAM by default- the program seems to have 1usmus' kits profile built into it by default, so it generates timings that most people's memory here simply cannot do.

5) You'll notice after resetting XMP and importing YOUR XMP profile (e.g. erasing or otherwise telling the program to not use the inbuilt profile) everything will be blank. You should see your kits' timing in ns (nanoseconds) in the left column. Go through all the dropdown boxes and change them appropriately. For Ryzen 3000 series processors choose 'Ryzen 2' or 'Ryzen 2nd gen' (2000 series was a die shrink, sort of (not really lol), and optimization of Ryzen 1000... thus Ryzen 3000 is actually 2nd Gen), for memory rank pick 1 or single if you have 16GB (8gb x2) G.skill, pick Bdie if you know you have it, and for motherboard/chipset pick whatever you have. If you have an older mobo it will be X470 or X370 if you bought a decent board for either Ryzen release or Ryzen refresh, if you just bought a setup like I did and didn't buy a cheap junk offbrand board it will be X570.

6) Now you can select the frequency you're targeting. I'd suggest 3800MHz for R9 3900x (And 3950X), and 3733MHz for everything else (as I've heard it can be difficult to get the lower binned IMCs to do higher than 1866MHz Fclk, but I've seen one user with a C8I and R5 3600 getting pretty insane speeds in excess of 4000MHz on DRAM). Click generate fast. Be sure 'profile' on the left side 'Profile' is still set to manual- DO NOT change it to V1 or V2. Take pictures of the settings on your smartphone for both the first tab with timings, and the Advanced tab

7) Enter *literally every setting and voltage* that the Calculator spits out. Enter the settings from the "Rec." columns. If you don't, don't complain when you can't POST. I advise backing up your bios settings if you can (on my board its Asus User Profile); you WILL be doing cmos resets a lot. I save a few profiles in the settings, and also copy them to a usb stick.

8) Use your head to find some of the Advanced settings. Be thorough and take your time, and you'll find them all. Settings like Interleave Size, DRAM R1-R4 tune, ProcODT, BankGroupSwap_Alt(this one is quite important- may be called BGS_Alt- if you enable it, set BGS to disabled- both cannot be active at once), etc. *You really must set everything. No excuses and no complaints!* I helped one guy in a PM for over a week and he literally refused to answer when I repeatedly asked if he had found every setting, and even made and uploaded 2 15 minute videos to Youtube showing where to find every relevant setting, that he didn't watch, in the end he insisted he had 'solved his instability problem' at 3733 cas 14 by adding a fan blowing on the DIMMs because *he was too lazy and couldn't be bothered to do it all!* He claimed his memory "was overheating" (lol- it doesn't... 45C-50C is totally fine, if it were above 70C maybe I'd be concerned...) and refused to consider loosening timings to get to 3800MHz which carries a minimum of performance hit and still lowers latency and increases bandwidth...dont be like him. Learn your board and BIOS! (On mine, all of the Advanced tab settings can be found in 'AMD CBS' in the Advanced tab of our BIOS- Just go from the top and go through literally every menu and submenu and you'll find most of them. A few more are in the RAM timing options themselves (termination impedance) and others are in Tweakers Paradise.) I'm thrilled to have bought $119 3200 cas 14 memory and gotten a +600MHz OC and sub-64ns latency.

9) Good luck! Hope this helps. If you do all this and still have issues- I have a few tricks that might work if your RGB 3600 c16 DIMMS won't stabilize above 3600MHz  This is why I buy cheaper, non-blinkenlights memory


----------



## rastaviper

neurotix said:


> +rep to oreonutz (lol)
> 
> 
> 
> This is basically correct.
> 
> 
> 
> The right way to use Ryzen Dram Calculator is:
> 
> 
> 
> 1) You need Thaiphoon Burner as stated. (Many AV report it as a false positive because it has code that contains low-level functions, likely in ASM, that query the SMBus, etc. to retrieve the data programmed into the SPD chips on the DIMMs. The program is safe.) Near the top menu bar is a button that is something like 'Read SPD' or 'Read XMP'. Click it.
> 
> 
> 
> 2) Thaiphoon generates a report that pops up in a window. *MAKE SURE YOU SCROLL DOWN TO THE BOTTOM AND CHECK THE CHECKBOX, 'SHOW TIMINGS IN NS'!!!* Last time I used the program, for the life of me, I could not find this option again. If you miss this step, DRAM Calc will *bleep* at you and refuse to load your profile.
> 
> 
> 
> 3) After doing that, Thaiphoon has an option in a dropdown menu or a button, 'Export Profile'. *You need to pick 'export full html profile' out of the various options.* Navigate to the folder you have Ryzen DRAM Calculator in, and save the html report there.
> 
> 
> 
> 4) Open Ryzen Calc, and at the bottom, above 'Import XMP', click reset. Then click 'Import XMP' and select the html file. If you did this correctly, you will see the exact model number, specs etc. of your specific memory in the top-right of the application now. If you follow my instructions exactly, you will notice that it has some (expensive) high frequency Gskill DRAM by default- the program seems to have 1usmus' kits profile built into it by default, so it generates timings that most people's memory here simply cannot do.
> 
> 
> 
> 5) You'll notice after resetting XMP and importing YOUR XMP profile (e.g. erasing or otherwise telling the program to not use the inbuilt profile) everything will be blank. You should see your kits' timing in ns (nanoseconds) in the left column. Go through all the dropdown boxes and change them appropriately. For Ryzen 3000 series processors choose 'Ryzen 2' or 'Ryzen 2nd gen' (2000 series was a die shrink, sort of (not really lol), and optimization of Ryzen 1000... thus Ryzen 3000 is actually 2nd Gen), for memory rank pick 1 or single if you have 16GB (8gb x2) G.skill, pick Bdie if you know you have it, and for motherboard/chipset pick whatever you have. If you have an older mobo it will be X470 or X370 if you bought a decent board for either Ryzen release or Ryzen refresh, if you just bought a setup like I did and didn't buy a cheap junk offbrand board it will be X570.
> 
> 
> 
> 6) Now you can select the frequency you're targeting. I'd suggest 3800MHz for R9 3900x (And 3950X), and 3733MHz for everything else (as I've heard it can be difficult to get the lower binned IMCs to do higher than 1866MHz Fclk, but I've seen one user with a C8I and R5 3600 getting pretty insane speeds in excess of 4000MHz on DRAM). Click generate fast. Be sure 'profile' on the left side 'Profile' is still set to manual- DO NOT change it to V1 or V2. Take pictures of the settings on your smartphone for both the first tab with timings, and the Advanced tab
> 
> 
> 
> 7) Enter *literally every setting and voltage* that the Calculator spits out. Enter the settings from the "Rec." columns. If you don't, don't complain when you can't POST. I advise backing up your bios settings if you can (on my board its Asus User Profile); you WILL be doing cmos resets a lot. I save a few profiles in the settings, and also copy them to a usb stick.
> 
> 
> 
> 8) Use your head to find some of the Advanced settings. Be thorough and take your time, and you'll find them all. Settings like Interleave Size, DRAM R1-R4 tune, ProcODT, BankGroupSwap_Alt(this one is quite important- may be called BGS_Alt- if you enable it, set BGS to disabled- both cannot be active at once), etc. *You really must set everything. No excuses and no complaints!* I helped one guy in a PM for over a week and he literally refused to answer when I repeatedly asked if he had found every setting, and even made and uploaded 2 15 minute videos to Youtube showing where to find every relevant setting, that he didn't watch, in the end he insisted he had 'solved his instability problem' at 3733 cas 14 by adding a fan blowing on the DIMMs because *he was too lazy and couldn't be bothered to do it all!* He claimed his memory "was overheating" (lol- it doesn't... 45C-50C is totally fine, if it were above 70C maybe I'd be concerned...) and refused to consider loosening timings to get to 3800MHz which carries a minimum of performance hit and still lowers latency and increases bandwidth...dont be like him. Learn your board and BIOS! (On mine, all of the Advanced tab settings can be found in 'AMD CBS' in the Advanced tab of our BIOS- Just go from the top and go through literally every menu and submenu and you'll find most of them. A few more are in the RAM timing options themselves (termination impedance) and others are in Tweakers Paradise.) I'm thrilled to have bought $119 3200 cas 14 memory and gotten a +600MHz OC and sub-64ns latency.
> 
> 
> 
> 9) Good luck! Hope this helps. If you do all this and still have issues- I have a few tricks that might work if your RGB 3600 c16 DIMMS won't stabilize above 3600MHz  This is why I buy cheaper, non-blinkenlights memory


Wow respect for the analytical explanation.
Never cared to put every exact setting from the Calc, as already I can get the 3733 setup at 16-15-14, but maybe I will try to put all settings for maybe some better AIDA results.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## eBombzor

My E-Die kit (3000 - CL15) couldn't do 3733 CL16 with GDM disabled at any voltage but once I turned GDM on without changing anything else, I am able to pass Kahru 400% (still testing atm) at 1.35v. 

Pretty insane? Didn't know GDM made this much of a difference in stability. Anyone else run e-die's at super low voltages?

Also set my SOC voltage to offset -0.05 (total 1.05v) at 1866mhz. What's the lowest voltage anyone's used for SOC at 1800+mhz?


----------



## neurotix

rastaviper said:


> Wow respect for the analytical explanation.
> Never cared to put every exact setting from the Calc, as already I can get the 3733 setup at 16-15-14, but maybe I will try to put all settings for maybe some better AIDA results.
> 
> Sent from my ONEPLUS A6003 using Tapatalk


You will definitely get better AIDA results if you take the time, especially if you set all the subtimings manually as per DRAM Calc and whatever it gives you.

The advanced settings (like BGS_Alt, Memory Interleave Size, etc) and voltages will help too. The reason is because these affect the memory controller, bus, Infinity Fabric (on-chip bus), and so on. This will not only give you more stability, but possibly more speed. If anything you may not notice a change in bandwidth, but you might see lower latency in ns, which is more important anyway.



eBombzor said:


> My E-Die kit (3000 - CL15) couldn't do 3733 CL16 with GDM disabled at any voltage but once I turned GDM on without changing anything else, I am able to pass Kahru 400% (still testing atm) at 1.35v.
> 
> Pretty insane? Didn't know GDM made this much of a difference in stability. Anyone else run e-die's at super low voltages?
> 
> Also set my SOC voltage to offset -0.05 (total 1.05v) at 1866mhz. What's the lowest voltage anyone's used for SOC at 1800+mhz?


Hi.

I can't really advise on the E-Die thing, but I can give some general suggestions.

Yes, turning Gear Down Mode on is supposedly well known for getting troublesome sticks in line, though at a small bandwidth hit (you gain stability for sure). In my testing, I lost about 1GB/sec across the board, and saw higher latency (not much), but you gain stability (I am stable at my settings @ 1T though.) GDM helps specifically at IFclk < 1800MHz. This is one of the tips I was going to mention in my post above- enable this if you are having trouble booting with RAM higher than 3600MHz/1800 fclk.

- Turn ECC off unless you plan on running heavy scientific apps (folding, BOINC, mining, any other apps like that), a production webserver that requires 100% uptime, large video projects that pay the bills, etc. I've been overclocking for 20 years and building rigs for 10 and never seen a consumer desktop platform, let alone one focused on gaming and content creation, that even supports ECC. When overclocking/overvolting/undervolting/etc you can probably only ever have 99.8% stability in the best cases anyway- sooner or later you WILL find something that will make you crash- the better the job you do, the less it becomes "if?" and more it becomes "when?". My previous setup was binned and tested by SiliconLottery (4790k 4.8), and they claimed it did 4.8GHz at 1.31v, but only tested in RealBench for an hour- I got it to crash pretty quick with something at those settings. In reality, it needed 1.34v but it was never 100% and would crash randomly in some untested workload/test eventually, but maybe twice a year. Anyway, disable ECC- you don't need it and turning it off will allow you to overclock higher. (If you require 100% stability- leave it on- then run [email protected] for a week straight nonstop on the CPU. If you have ANY memory issues during this period, folding will error, dump the unit, and say BAD_WORK_UNIT in its console. I'd urge anyone here to give this a shot, if you are unstable, even an hour of this will be more effective at finding memory errors than the test built in to the Calculator.)

- Do you have BankGroupSwap_Alt on? This can make a big difference too.

- Raising ProcODT (and other impedances linked to it) can help. Try between 41Ohm-53Ohm.


----------



## rastaviper

neurotix said:


> You will definitely get better AIDA results if you take the time, especially if you set all the subtimings manually as per DRAM Calc and whatever it gives you.
> 
> 
> 
> The advanced settings (like BGS_Alt, Memory Interleave Size, etc) and voltages will help too. The reason is because these affect the memory controller, bus, Infinity Fabric (on-chip bus), and so on. This will not only give you more stability, but possibly more speed. If anything you may not notice a change in bandwidth, but you might see lower latency in ns, which is more important anyway.
> 
> 
> 
> 
> - Do you have BankGroupSwap_Alt on? This can make a big difference too.
> 
> 
> 
> - Raising ProcODT (and other impedances linked to it) can help. Try between 41Ohm-53Ohm.


I am not sure if I have prepared 100% the Calc,.but the recommended settings were 16-16-16, when I can easily go down to 16-15-14. Can it be that the Calc gives more strict results?

Also any idea where to find the BGS settings at a x570 Gigabyte mobo?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## GeneralHARM

neurotix said:


> +rep to oreonutz (lol)
> 
> 
> 9) Good luck! Hope this helps. If you do all this and still have issues- I have a few tricks that might work if your RGB 3600 c16 DIMMS won't stabilize above 3600MHz  This is why I buy cheaper, non-blinkenlights memory


Any tricks for getting rid of errors? as i posted on the last page I can post/boot windows and pass easy membench but pop an error in Kahru mem test pretty quickly.


----------



## sideeffect

eBombzor said:


> My E-Die kit (3000 - CL15) couldn't do 3733 CL16 with GDM disabled at any voltage but once I turned GDM on without changing anything else, I am able to pass Kahru 400% (still testing atm) at 1.35v.
> 
> Pretty insane? Didn't know GDM made this much of a difference in stability. Anyone else run e-die's at super low voltages?
> 
> Also set my SOC voltage to offset -0.05 (total 1.05v) at 1866mhz. What's the lowest voltage anyone's used for SOC at 1800+mhz?


Did you test clkDrvStren at 60 or 120? For me 60 stabilises GDM disabled at 3733 but I do run higher voltage than you about 1.4v. That SOC voltage is really good for 1866 I would think that is way above average. Does it post at 1900? My 3700x won't post at 1900 and requires about 1.125v for 1866. My friends 3600 does 1900 at around 1.05v...


----------



## rastaviper

hmm
Put all details according to the Mem Calculator but my pc can't boot properly and gives me the 3 beeps.

How can I know where is the problem?









Sent from my ONEPLUS A6003 using Tapatalk


----------



## mongoled

Set tRDWR to 10


----------



## VPII

This is the lowest I've seen on latency, basically a brand new win10 installation, well Thursday is when it was installed, no updates yet.


----------



## rastaviper

mongoled said:


> Set tRDWR to 10


Ok will check that, although I doubt that this is the problem.

Also, how important is the SOC?
I am putting it at 1.1 at the menu that gives all different options, but there is somewhere another SOC option where you have to set it manually and also there is a comment that this option works only in combination with the activation of SOC/CORE option.
What should I do with that?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## eBombzor

sideeffect said:


> Did you test clkDrvStren at 60 or 120? For me 60 stabilises GDM disabled at 3733 but I do run higher voltage than you about 1.4v. That SOC voltage is really good for 1866 I would think that is way above average. Does it post at 1900? My 3700x won't post at 1900 and requires about 1.125v for 1866. My friends 3600 does 1900 at around 1.05v...


I have it set to 120 right now. I would try 60 but I am ok with leaving GDM on at this point because it seems to bring a ton of stability.

I couldn't post at 1900 1.1v sadly, I might be able to post at 1.125v but I am just sick of having to unplug my case and manually reset the jumper everytime it doesn't post lmao. Goddammit asus. Maybe someday but as of now I am p happy with what I got.


----------



## hesee

neurotix said:


> 8) Use your head to find some of the Advanced settings. Be thorough and take your time, and you'll find them all. Settings like Interleave Size, DRAM R1-R4 tune, ProcODT, BankGroupSwap_Alt(this one is quite important- may be called BGS_Alt- if you enable it, set BGS to disabled- both cannot be active at once), etc. *You really must set everything. No excuses and no complaints!* I helped one guy in a PM for over a week and he literally refused to answer when I repeatedly asked if he had found every setting, and even made and uploaded 2 15 minute videos to Youtube showing where to find every relevant setting, that he didn't watch, in the end he insisted he had 'solved his instability problem' at 3733 cas 14 by adding a fan blowing on the DIMMs because *he was too lazy and couldn't be bothered to do it all!* He claimed his memory "was overheating" (lol- it doesn't... 45C-50C is totally fine, if it were above 70C maybe I'd be concerned...) and refused to consider loosening timings to get to 3800MHz which carries a minimum of performance hit and still lowers latency and increases bandwidth...dont be like him. Learn your board and BIOS! (On mine, all of the Advanced tab settings can be found in 'AMD CBS' in the Advanced tab of our BIOS- Just go from the top and go through literally every menu and submenu and you'll find most of them. A few more are in the RAM timing options themselves (termination impedance) and others are in Tweakers Paradise.) I'm thrilled to have bought $119 3200 cas 14 memory and gotten a +600MHz OC and sub-64ns latency.


Good stuff, but i disagree on memory heating. It does matter. When i switched from air cooling to customloop memory temperatures went up 7c. Game crashes, bluescreens etc with same memory settings. Reservoir blocked some airflow to the ram and dual rank runs hotter anyway. So i started testing. Memory went up to 55c and it allways created errors before Karhu test reached 1000%. Between 50-54c it allways created errors before hitting 10000%. Under 50c Karhu can run forever. So stability was fixed by attaching small noctua fan to reservoir and it's airflow to ram is solved all unstability issues. Timings, voltages and cpu overclock were untouched.


----------



## neurotix

rastaviper said:


> I am not sure if I have prepared 100% the Calc,.but the recommended settings were 16-16-16, when I can easily go down to 16-15-14. Can it be that the Calc gives more strict results?
> 
> Also any idea where to find the BGS settings at a x570 Gigabyte mobo?
> 
> Sent from my ONEPLUS A6003 using Tapatalk



The opposite. Higher timing = less strict. So, if you can do those primary timings (which isn't the best idea) you are running tighter, more difficult to stabilize timings than recommended.




GeneralHARM said:


> Any tricks for getting rid of errors? as i posted on the last page I can post/boot windows and pass easy membench but pop an error in Kahru mem test pretty quickly.



Tried turning on Gear Down Mode, turning off ECC, and so forth? Have you raised DRAM voltage to 1.5v, and VTT_DDR to 0.750v to match? How about loosening timings? (If you're doing CAS16 timings try: 16-16-17-16-34-52) You can also raise CAS to 18.

If all of those fail, then you probably need to lower the frequency you are aiming for by 1-2 dividers (e.g. 3733 to 3666/1833MHz Fclk)



rastaviper said:


> hmm
> Put all details according to the Mem Calculator but my pc can't boot properly and gives me the 3 beeps.
> 
> How can I know where is the problem?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sent from my ONEPLUS A6003 using Tapatalk


No clue but see above.



VPII said:


> This is the lowest I've seen on latency, basically a brand new win10 installation, well Thursday is when it was installed, no updates yet.


Wth? What kit do you have? Is it just 1903 without updates? The best I've done with identical frequency and similar timings is 63.6ns




hesee said:


> Good stuff, but i disagree on memory heating. It does matter. When i switched from air cooling to customloop memory temperatures went up 7c. Game crashes, bluescreens etc with same memory settings. Reservoir blocked some airflow to the ram and dual rank runs hotter anyway. So i started testing. Memory went up to 55c and it allways created errors before Karhu test reached 1000%. Between 50-54c it allways created errors before hitting 10000%. Under 50c Karhu can run forever. So stability was fixed by attaching small noctua fan to reservoir and it's airflow to ram is solved all unstability issues. Timings, voltages and cpu overclock were untouched.



Are you sure you set everything correctly in bios? Did you set all voltages, timings, impedence, and all options in AMD CBS or under the Advanced section of DRAM calc?

The other person had the same issue and added a fan but would not say whether or not they had set literally every or nearly every option (my Crosshair VIII doesn't have a few of the settings under Advanced everywhere, and also cannot set Vref Cha A/B to anything higher than 0.600v, and has no Boot DRAM voltage setting- but I set everything else I can)

If you did and adding the fan was the only solution, I'd admit I could be wrong in some cases, but if you didn't it could be a stability problem that is reduced or solved by adding cooling. You may not actually be fully stable.

I have a very large case, a 3000rpm/100+CFM front fan, great airflow etc. I added a G.skill memory cooler but more to help with CPU and socket temperatures than RAM cooling. Regardless, my memory was in the 55C range as well before doing so, as I use a H100i and have two 350w+ cards exhausting heat upward. My memory ran at that temperature and the speeds in my sig rig with no issues. Passed 3200%

Quoting someone elsewhere:

"The actual 'damage' voltage is actually closer to 2V, JEDEC requires DDR4 tolerate spikes of 1.9V without harm. The system doesn't need to function however, just not fail entirely. 1.5V is a good daily limit of course, as most people want their RAM to last for more than single upgrade cycle.

Temperature related errors occur far more frequently when running your tRFC/tREFI on the edge of stability. Shorter refresh cycles keep the cells properly charged, at a small cost to bandwidth. In fact, there is a separate tREFI value for when your sticks exceed the max temp, which sets the tREFI time extremely low so errors don't occur. Not all boards have that accessible though, and it honestly should never be needed."

DDR4 is rated by JEDEC for up to 1.5v 24/7 and 81C temperature.

Check your tRFC. But tbh I don't really care to argue/explain this more- if adding a fan solves your problem and lets you run your system stable and you're happy with that, then I'll admit it works, if YOU are satisfied and happy that's all that really matters.


EDIT: O ya, someone asked somewhere (I think) about where to find the settings I'm mentioning on a Gigabyte AORUS board. I have no idea! Just go through every menu you can find in your bios, including all submenus, and hopefully you will find them all. Given that all the board partners UEFI firmware is basically based on the same thing one way or another, they should all be there on a higher end model, and I would suggest the 'Advanced' tab of your BIOS or look for AMD CBS (no idea what CBS stands for, so if you see something that may be it, try that)


----------



## Uzito2K

I need some advice on tightening timings for my Crucial Ballistix Sport LT 32GB 3200 CL16 (BLS2K16G4D32AESB) kit.
I've got 3700x on ASUS Prime X570-Pro motherboard. I've tried the DRAM calculator settings and the PC would not boot.
I've tried to set up just the primary timings and it worked fine, though I do not see any improvement in latency - 75ns with default timings, same 75ns with manual tweaks.

Here's comparison between what calculator had suggested and what I was able to boot with:


----------



## hesee

neurotix said:


> Are you sure you set everything correctly in bios? Did you set all voltages, timings, impedence, and all options in AMD CBS or under the Advanced section of DRAM calc?
> 
> The other person had the same issue and added a fan but would not say whether or not they had set literally every or nearly every option (my Crosshair VIII doesn't have a few of the settings under Advanced everywhere, and also cannot set Vref Cha A/B to anything higher than 0.600v, and has no Boot DRAM voltage setting- but I set everything else I can)
> 
> If you did and adding the fan was the only solution, I'd admit I could be wrong in some cases, but if you didn't it could be a stability problem that is reduced or solved by adding cooling. You may not actually be fully stable.


The fan was solution on 2700X running my own custom timings, when temperatures were restored to same levels as they were during air cooling settings were stable again. No touching of settings was required. B-Dies are bit temperature sensitive when settings are pushed to the limits.

As for ram calculator. It gives sane starting settings, so following it strictly is good starting position. When switching to 3900X it tried ram calculator, including settings in advanced tab. No go, 3600mhz was really unstable using safe settings and unbootable using fast settings. So i went to oldschool and did it by the hand. No settings presented in advanced tab were needed, main culprit was wrong termination settings for my motherboard (well my asrock x370 professional gaming did require it's own config with 2700X as well).

Other things i spotted from calculator vs own experiences:

- Faw 4X has allways required big boost in voltage and 6X is the sweetspot, loosening from that gives no real voltage benefit.
- TCWL/Trtp/Trdwr/twrrd line given by calculator was unstable, it would have worked with twrrd 5, but i choose to use my own default. (i tried both)

Voltage is higher than suggested, but it runs on tigher settings, with execption of TRFC. That ram setup is actually unbootable on termination settings (rec & alts) that ram calculator suggests.


----------



## rastaviper

rastaviper said:


> Ok will check that, although I doubt that this is the problem.
> 
> Also, how important is the SOC?
> I am putting it at 1.1 at the menu that gives all different options, but there is somewhere another SOC option where you have to set it manually and also there is a comment that this option works only in combination with the activation of SOC/CORE option.
> What should I do with that?
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Any comments about the double SOC entry?
Are they about the same thing (so I should put exactly the same figures) or do they affect different parameters?
And what is this *SOC/Uncore* option and where do I find the *BGS* settings?


----------



## rdr09

Uzito2K said:


> I need some advice on tightening timings for my Crucial Ballistix Sport LT 32GB 3200 CL16 (BLS2K16G4D32AESB) kit.
> I've got 3700x on ASUS Prime X570-Pro motherboard. I've tried the DRAM calculator settings and the PC would not boot.
> I've tried to set up just the primary timings and it worked fine, though I do not see any improvement in latency - 75ns with default timings, same 75ns with manual tweaks.
> 
> Here's comparison between what calculator had suggested and what I was able to boot with:


Only time i use the calc is when i need to run my G.Skill Ripjaws V 3200 MHz CL16 above 3333MHz. For 3333 and below, i use DOCP with an added bit of voltage - 1.36v.

At DOCP 3333 CL16, M-Die, 1.36v, latency is around 71ns. So, i set the RAM to DOCP 3200 CL16, raise the speed to 3333, and add voltage. That's it.


----------



## Nguyen Vo

Hello everyone, I'm using a 3900x at stock settings on a x570 MSI Meg ACE board running 32 gb (16 gb x 2) 3800 mhz cl16 from a stock of 3200mhz cl14. I'm having trouble with stability when using the Stressapptest. It runs for about 20 minutes and then my computer crashes with a black screen. I entered in everything described in DRAM calculator v1.62 using fast preset. Can anyone guide me in loosening my timings or adjusting the voltages. Another note, the only setting I wasn't able to find was the VTT-DRAM voltage, but everything is entered as shown.


----------



## mongoled

Nguyen Vo said:


> Hello everyone, I'm using a 3900x at stock settings on a x570 MSI Meg ACE board running 32 gb (16 gb x 2) 3800 mhz cl16 from a stock of 3200mhz cl14. I'm having trouble with stability when using the Stressapptest. It runs for about 20 minutes and then my computer crashes with a black screen. I entered in everything described in DRAM calculator v1.62 using fast preset. Can anyone guide me in loosening my timings or adjusting the voltages. Another note, the only setting I wasn't able to find was the VTT-DRAM voltage, but everything is entered as shown.


Raise trtp to 12 (if its still unstable try 14)


----------



## The Sandman

neurotix said:


> +rep to oreonutz (lol)
> 
> This is basically correct.
> 
> The right way to use Ryzen Dram Calculator is:
> 
> 1) You need Thaiphoon Burner as stated. (Many AV report it as a false positive because it has code that contains low-level functions, likely in ASM, that query the SMBus, etc. to retrieve the data programmed into the SPD chips on the DIMMs. The program is safe.) Near the top menu bar is a button that is something like 'Read SPD' or 'Read XMP'. Click it.
> 
> 2) Thaiphoon generates a report that pops up in a window. *MAKE SURE YOU SCROLL DOWN TO THE BOTTOM AND CHECK THE CHECKBOX, 'SHOW TIMINGS IN NS'!!!* Last time I used the program, for the life of me, I could not find this option again. If you miss this step, DRAM Calc will *bleep* at you and refuse to load your profile.



Thank you and to @oreonutz for sharing this info +Rep. I never had any luck importing profile until this lol.
Also wanted to add, if you click "Read", select dimm than click "Report" this is where you scroll down to locate "Show delays in nanoseconds"
Great work guys!


----------



## Nguyen Vo

mongoled said:


> Raise trtp to 12 (if its still unstable try 14)


Thanks for the advice, I tried Trptp 14 but, still getting instability with the stressapptest.


----------



## mongoled

Nguyen Vo said:


> Thanks for the advice, I tried Trptp 14 but, still getting instability with the stressapptest.


What are the DRAM voltage, vSOC voltage and VDDP/VDDG voltages set at ?


----------



## Nguyen Vo

mongoled said:


> What are the DRAM voltage, vSOC voltage and VDDP/VDDG voltages set at ?


SoC voltage is 1.1 v, DRAM voltage is at 1.44 v (was tested on 1.42, and 1.43), VDDP is 0.9 v, and VDDG is 0.95. I just tried using the Safe preset settings, but I'm still experience black screen reboot crashes.


----------



## rastaviper

rastaviper said:


> Any comments about the double SOC entry?
> Are they about the same thing (so I should put exactly the same figures) or do they affect different parameters?
> And what is this *SOC/Uncore* option and where do I find the *BGS* settings?


So after updating all these entries (except the BGS that I can't find anywhere) the things get better and better!
With Ram at 1,39v, 16-15-15, 3733 I can now go down to Latency 63ns as u can see here: https://www.overclock.net/forum/13-...membench-0-8-dram-bench-197.html#post28160880


----------



## mongoled

Nguyen Vo said:


> SoC voltage is 1.1 v, DRAM voltage is at 1.44 v (was tested on 1.42, and 1.43), VDDP is 0.9 v, and VDDG is 0.95. I just tried using the Safe preset settings, but I'm still experience black screen reboot crashes.


Those look OK,

Have you tested the CPU 'independant' from the RAM by running prime95 small FFTs?

Just to rule out an issue that isnt related to RAM?


----------



## Streetdragon

Nguyen Vo said:


> SoC voltage is 1.1 v, DRAM voltage is at 1.44 v (was tested on 1.42, and 1.43), VDDP is 0.9 v, and VDDG is 0.95. I just tried using the Safe preset settings, but I'm still experience black screen reboot crashes.


not enough vddg. enter 1090mV and retest.

Some need less vddg to go stable some need more.
I need soc 1.125, 1100mv vddg vddp auto


----------



## Nguyen Vo

Streetdragon said:


> not enough vddg. enter 1090mV and retest.
> 
> Some need less vddg to go stable some need more.
> I need soc 1.125, 1100mv vddg vddp auto


After increasing my SoC voltage to 1.125 volts, I was able to get a stable 3800 mhz 16-16-16-16-32 with 1900 mhz fclk! Thank you so much for your suggestions. How safe is 1.125 volts on the SoC though?


----------



## Streetdragon

dont know^^ 1.1V is auto on gigabyte
1.125 should not be so bad. maybe uses 1-2Watt more power under full load


----------



## mongoled

Nguyen Vo said:


> After increasing my SoC voltage to 1.125 volts, I was able to get a stable 3800 mhz 16-16-16-16-32 with 1900 mhz fclk! Thank you so much for your suggestions. How safe is 1.125 volts on the SoC though?


Nice one!

Should be OK as the poster above alluded to


----------



## rastaviper

mongoled said:


> I use the settings below, my set though is F4-3600C15D-16GTZ.
> 
> 
> 
> As your RAM sticks are a result of binning there is a good chance you can run similar settings
> 
> 
> 
> 1.44 volts
> 
> tCL: 15
> 
> tRCDWR: 10
> 
> tRCDRD: 17
> 
> tRP: 15
> 
> tRAS: 28
> 
> tRC: 42
> 
> tRRDS: 4
> 
> tRRDL: 6
> 
> tFAW16
> 
> tWTRS: 4
> 
> tWTRL: 8
> 
> tWR: 12
> 
> tRDRD SCL: 4
> 
> tWRWR SCL: 4
> 
> tRFC: 266
> 
> tCWL: 14
> 
> tRTP: 12
> 
> tRDWR: 10
> 
> tWRRD: 1
> 
> tWRWR SC: 1
> 
> tWRWR SD: 7
> 
> tWRWR DD: 7
> 
> tRDRD SC: 1
> 
> tRDRD SD: 5
> 
> tRDRD DD: 5
> 
> tCKE: 1


Hmm maybe will try this setup.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## mongoled

rastaviper said:


> Hmm maybe will try this setup.
> 
> Sent from my ONEPLUS A6003 using Tapatalk


I dont think you will be OK with the trfc (im talking about 100% stability), 

change to something higher than 288


----------



## lDevilDriverl

mongoled said:


> rastaviper said:
> 
> 
> 
> Hmm maybe will try this setup.
> 
> Sent from my ONEPLUS A6003 using Tapatalk
> 
> 
> 
> I dont think you will be OK with the trfc (im talking about 100% stability),
> 
> change to something higher than
> 288
Click to expand...


4x8 vs 260 trfc is ok (2 different kits of b-die)

I'll try to go with rcdwr 10-11.


----------



## MindBlank

Is it possible that a lower SoC voltage can actually help stabilize a memory OC? 

I was running some tests with 1.1625v SoC and consistently got errors around the 65-80% mark in Memtest. I dropped SoC to 1.1v and stopped testing at 190% error free...

EDIT: Temps are the same between the 2 voltages, so it's not that.


----------



## rastaviper

I think this should be near the limit for me.
Best AIDA score with my 3600x at 4441mhz, Ram at 3733 16-15-15 
(And something weird: all numbers went up when my CPU went from 4300 to 4450mhz except the Read which reduced by 300 points)


----------



## lDevilDriverl

rastaviper said:


> I think this should be near the limit for me.
> Best AIDA score with my 3600x at 4441mhz, Ram at 3733 16-15-15


Could you please show all your timings? tm5 1usmum v3 passed? 


rastaviper said:


> (And something weird: all numbers went up when my CPU went from 4300 to 4450mhz except the Read which reduced by 300 points)


I have noticed this on my 2600x, 3600x looks the same) my wright speed is 30399 and looks like this is max for 3600x(only with bclk overclocking could be bigger)


----------



## rastaviper

lDevilDriverl said:


> Could you please show all your timings? tm5 1usmum v3 passed?
> 
> I have noticed this on my 2600x, 3600x looks the same) my wright speed is 30399 and looks like this is max for 3600x(only with bclk overclocking could be bigger)


Yeap test passed


----------



## Hequaqua

lDevilDriverl said:


> Could you please show all your timings? tm5 1usmum v3 passed?
> 
> I have noticed this on my 2600x, 3600x looks the same) my wright speed is 30399 and looks like this is max for 3600x(only with bclk overclocking could be bigger)


Write speed is limited because of only having one CCD on the die.


----------



## lDevilDriverl

rastaviper said:


> Yeap test passed


Try to go with ProcODT 60>36.9 or 34.3, RS 52>42, tFAW 20>16, trrds 5>4, trrdl 8>6, twr 14>12, twtrl 14>12


----------



## lDevilDriverl

Hequaqua said:


> Write speed is limited because of only having one CCD on the die.


I know that, I mean that 30399 looks like max for 1 ccd


----------



## rastaviper

lDevilDriverl said:


> Try to go with ProcODT 60>36.9 or 34.3, RS 52>42, tFAW 20>16, trrds 5>4, trrdl 8>6, twr 14>12, twtrl 14>12


Do u think these will give some better AIDA results?

Also I tried to increase manually the BCLK from 100 to 102 and my windows got stuck and started repairing themselves.


----------



## mongoled

rastaviper said:


> Do u think these will give some better AIDA results?
> 
> Also I tried to increase manually the BCLK from 100 to 102 and my windows got stuck and started repairing themselves.


Mate be careful!

BCLK clock, do you understand what you are doing there ??

As from what you have written it does not look this way.

If you value your data then dont overclock using the BCLK !

If you want to test, then make sure you dont have any drives that have valuable data connected to your PC before you start testing.

Please read about BCLK and what it does.

Dont just raise values without knowing what they do, unless you dont care about your data or hardware .........


----------



## rastaviper

mongoled said:


> Mate be careful!
> 
> 
> 
> BCLK clock, do you understand what you are doing there ??
> 
> 
> 
> As from what you have written it does not look this way.
> 
> 
> 
> If you value your data then dont overclock using the BCLK !
> 
> 
> 
> If you want to test, then make sure you dont have any drives that have valuable data connected to your PC before you start testing.
> 
> 
> 
> Please read about BCLK and what it does.
> 
> 
> 
> Dont just raise values without knowing what they do, unless you dont care about your data or hardware .........


I was reading that till 104 things should be quite safe.
Do u have something else in mind.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## lDevilDriverl

rastaviper said:


> Do u think these will give some better AIDA results?
> 
> Also I tried to increase manually the BCLK from 100 to 102 and my windows got stuck and started repairing themselves.


for bclk overclocking you should use 3733 + fclk 1867 (if your cpu works fine with 3800/1900)


----------



## mongoled

rastaviper said:


> I was reading that till 104 things should be quite safe.
> Do u have something else in mind.
> 
> Sent from my ONEPLUS A6003 using Tapatalk


'Safe', what is 'safe'

If you dont care about your data then BCLK is safe

If you dont care about your hardware then BCLK is safe.

Do you care about any of the two examples ??

If you care about your data, then you should do what i suggested, dont have any valuable data connected to your system when you test BCLK.

If you care about your hardware then again, you should only have attached hardware that you dont mind loosing.

Please re some indepth articles on what BCLK is, not just '104 is safe'.

There is not one given number to what is safe, overclocking is not black and white, different devices have different tolerances.

Just a quick bit of guidance, the BCLK will overclock all the devices that are attached to your motherboard via PCIe.

Devices such as your SSD, NVME drives, if they cant handle the increase in frequency then your data will be corrupted. Silent data corruption is the worst kind, because by the time you realise its toooooo late ..........

Other devices such as graphics cards, sound cards, usb devices, may just crash, but also may be effected in that they will fail later down the line, or cause you instabilities that you cant understand.

Sorry, im old school, meaning, that i read read and read some more before I do things.

This day and age, it seems most people want you to hold their hands, while at the same time 'they are the experts' without having read no where near enough on the subject at hand.

Like being at school, those who understood the value in reading and studying and those who just wanted to have the answer or cheat there way through education...........


----------



## lDevilDriverl

mongoled said:


> 'Safe', what is 'safe'
> 
> If you dont care about your data then BCLK is safe
> 
> If you dont care about your hardware then BCLK is safe.
> 
> Do you care about any of the two examples ??
> 
> If you care about your data, then you should do what i suggested, dont have any valuable data connected to your system when you test BCLK.
> 
> If you care about your hardware then again, you should only have attached hardware that you dont mind loosing.
> 
> Please re some indepth articles on what BCLK is, not just '104 is safe'.
> 
> There is not one given number to what is safe, overclocking is not black and white, different devices have different tolerances.
> 
> Just a quick bit of guidance, the BCLK will overclock all the devices that are attached to your motherboard via PCIe.
> 
> Devices such as your SSD, NVME drives, if they cant handle the increase in frequency then your data will be corrupted. Silent data corruption is the worst kind, because by the time you realise its toooooo late ..........
> 
> Other devices such as graphics cards, sound cards, usb devices, may just crash, but also may be effected in that they will fail later down the line, or cause you instabilities that you cant understand.
> 
> Sorry, im old school, meaning, that i read read and read some more before I do things.
> 
> This day and age, it seems most people want you to hold their hands, while at the same time 'they are the experts' without having read no where near enough on the subject at hand.
> 
> Like being at school, those who understood the value in reading and studying and those who just wanted to have the answer or cheat there way through education...........


to harsh


----------



## Synoxia

Is it possible that some ram slots on a motherboard just suck? What has previously been 3000% hci stable can't run on other memory slots. not even 3800 with auto timings...


----------



## mongoled

lDevilDriverl said:


> to harsh


Yes, you can say I over stepped the line.

Unfortunately these are the realities i see in my every day life .......


----------



## rastaviper

mongoled said:


> Yes, you can say I over stepped the line.
> 
> 
> 
> Unfortunately these are the realities i see in my every day life .......


It's ok,.I got the point.
Nothing happened BTW. No ocing and no problems so far after next reboot 

Sent from my ONEPLUS A6003 using Tapatalk


----------



## mongoled

rastaviper said:


> It's ok,.I got the point.
> Nothing happened BTW. No ocing and no problems so far after next reboot
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Do an sfc /scannow from an elevated cmd prompt.

If it finds corrupt files and cant repair them then you would need to run a DSIM command.

CPU 1P8 voltage is supposed to help with BCLK, it didnt help my board, cannot even run 101.

Looks stable, but will crash when the PCIe sub system is thorougly tested by running disk benchmarks such as crystaldiskmark.


----------



## Nguyen Vo

My wifi crashes with the error: Intel(R) Wi-Fi 6 AX200 160MHz #2 : Has encountered an internal error and has failed. This happens when playing intense games.

It only happens when I overclock my ram. Any ideas why this might be happening?

Running a 3900x stock with 16gb x 2 at 3800mhz cl16 on a x570 MEG Ace


----------



## DragonQ

My FCLK is happy at 1866 MHz but my RAM is only happy to go up to 1800 MHz (3600 MT/s) at 1.4 V. Would running micron-E die at 1.45 V be safe for daily use on an X470 Taichi Ultimate? Loosening timings and adjusting VDDP/CLDO_VDDP/VLDO_VDDG doesn't seem to help so I think more voltage would be the only way, but I don't want to risk reducing the lifespan of the sticks.


----------



## lDevilDriverl

rastaviper said:


> lDevilDriverl said:
> 
> 
> 
> Try to go with ProcODT 60>36.9 or 34.3, RS 52>42, tFAW 20>16, trrds 5>4, trrdl 8>6, twr 14>12, twtrl 14>12
> 
> 
> 
> Do u think these will give some better AIDA results?
> 
> Also I tried to increase manually the BCLK from 100 to 102 and my windows got stuck
> and started repairing themselves.
Click to expand...

It should.


----------



## Cidious

OK here we go. I seem to have rare single errors.

One night testing with HCI at around 800% of 32GB RAM no errors. TM5 v0.12 no errors for the full run (about 35 minutes) Karhu 1 error at 6000%. Should I ignore it or dig deeper?

AMD Ryzen 7 3800X
MSI B450M Mortar MAX
Crucial Ballistix Sport LT 3200 @ 3800 CL16 fine-tuned DRAM Calculator Fast Preset

DRAM 1.420v
VSOC 1.050v
VDDG 0.950v
VDDP 0.900v

I have a feeling it might be tRFC but not sure. Any ideas?


----------



## MadSupra354

I've been importing HTML's from Thaiphoon burner into the DRAM calculator and it's giving me timings that will cause a hang at the BIOS screen and require a CMOS reset. I've tried increasing the ProcODT impedance from 40Ω to 43.6Ω, maybe it needs to go higher? First screenshot is (roughly) my current timings/overclock. I'm trying to see if I can achieve at least 3200MHz. I'm not sure what could be causing the hang, this happened on the F42b and F42d BIOS for my AX370 Gaming-K5.


----------



## eBombzor

Cidious said:


> OK here we go. I seem to have rare single errors.
> 
> One night testing with HCI at around 800% of 32GB RAM no errors. TM5 v0.12 no errors for the full run (about 35 minutes) Karhu 1 error at 6000%. Should I ignore it or dig deeper?
> 
> AMD Ryzen 7 3800X
> MSI B450M Mortar MAX
> Crucial Ballistix Sport LT 3200 @ 3800 CL16 fine-tuned DRAM Calculator Fast Preset
> 
> DRAM 1.420v
> VSOC 1.050v
> VDDG 0.950v
> VDDP 0.900v
> 
> I have a feeling it might be tRFC but not sure. Any ideas?


I wouldn't ignore RAM errors ever. That definitely does seem like a tRFC error. Have you tried running games? When I tried lowering my tRFC I ran HCI and Kahru for a few hours without any errors but once I loaded up BF4 I crashed within seconds. Memtests are slow at catching tRFCs for some reason. Also Rev Es are the worst at tRFCs so I would put it at 580 and see if that fixes it.

The tRTP is very low as well. Have you tested each timing individually?

Sidenote: do you have CPU cache enabled on Kahru? It can speed up the test assuming your CPU doesn't have an OC.

Here are my Rev E results for comparison. https://imgur.com/zOznGj1



MadSupra354 said:


> I've been importing HTML's from Thaiphoon burner into the DRAM calculator and it's giving me timings that will cause a hang at the BIOS screen and require a CMOS reset. I've tried increasing the ProcODT impedance from 40Ω to 43.6Ω, maybe it needs to go higher? First screenshot is (roughly) my current timings/overclock. I'm trying to see if I can achieve at least 3200MHz. I'm not sure what could be causing the hang, this happened on the F42b and F42d BIOS for my AX370 Gaming-K5.


Loosen the CL to 16. 3200 CL14 is kinda expecting too much for MFR.


----------



## Synoxia

Stable 4 dimm overclock but sometimes i get F9 codes on boot, then 15 and need clear cmos. How to fix? Vboot voltage doesn't help



MindBlank said:


> Is it possible that a lower SoC voltage can actually help stabilize a memory OC?
> 
> I was running some tests with 1.1625v SoC and consistently got errors around the 65-80% mark in Memtest. I dropped SoC to 1.1v and stopped testing at 190% error free...
> 
> EDIT: Temps are the same between the 2 voltages, so it's not that.


Are you MindBlankTech youtuber? Btw in my experience yes, many times lowering soc voltage was better. Sweetspot for ryzen 1-2 is 1.0 to 1.15 while ryzen 3 0.95 to 1.10. Also lowering vdsoc gets you better auto boost.


----------



## Cidious

eBombzor said:


> I wouldn't ignore RAM errors ever. That definitely does seem like a tRFC error. Have you tried running games? When I tried lowering my tRFC I ran HCI and Kahru for a few hours without any errors but once I loaded up BF4 I crashed within seconds. Memtests are slow at catching tRFCs for some reason. Also Rev Es are the worst at tRFCs so I would put it at 580 and see if that fixes it.
> 
> The tRTP is very low as well. Have you tested each timing individually?
> 
> Sidenote: do you have CPU cache enabled on Kahru? It can speed up the test assuming your CPU doesn't have an OC.
> 
> Here are my Rev E results for comparison. https://imgur.com/zOznGj1
> 
> 
> 
> Loosen the CL to 16. 3200 CL14 is kinda expecting too much for MFR.


Thanks for the helping hand by now I had figured it out myself already. tRFC seemed to be fine. Either raising tRTP 10->12 or tRDWR 8->9 fixed it. Can't be bothered at this point to find out which of those it was.

Also new Agesa bios pulled another 1ns from my latency. over a course of 3 days my latency dropped from 70.5ish ish to 66.2ish. Same kit, practically same settings. but changed CPU and Motherboard. 3600 -> 3800X and Mortar non-MAX -> Mortar MAX. Pretty awesome. 

Here is the result:


----------



## kazablanka

f4-3600c16d gtzr ,not bad for this kit


----------



## rastaviper

kazablanka said:


> f4-3600c16d gtzr ,not bad for this kit


Latency at Aida test?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## kazablanka

rastaviper said:


> Latency at Aida test?
> 
> Sent from my ONEPLUS A6003 using Tapatalk


63.6ns on stock 3700x


----------



## rastaviper

kazablanka said:


> 63.6ns on stock 3700x


What do u mean by stock?
You are clocked at 4400.

Also it's strange that with such low subtimings that you can't go lower than 63 ns.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## kazablanka

rastaviper said:


> kazablanka said:
> 
> 
> 
> 63.6ns on stock 3700x
> 
> 
> 
> What do u mean by stock?
> You are clocked at 4400.
> 
> Also it's strange that with such low subtimings that you can't go lower than 63 ns.
> 
> Sent from my ONEPLUS A6003 using Tapatalk
Click to expand...

Ιts not clocked at 4.4ghz ,aida reads the boost at one core. The cpu is stock. 


My latency at manual 4.4ghz overclock is about 61.8ns


----------



## MadSupra354

Silent Scone said:


> A minimal coverage of two laps (200%) is required to be added to the table for HCI for density over 16GB. 16GB or less requires a minimum of 4 laps (400%)


Can I ask, is this 400% in total? Is there anything wrong with using the bootable memtest86 for stability testing? Not looking to be added to the table, just interested.


----------



## eBombzor

MadSupra354 said:


> Can I ask, is this 400% in total? Is there anything wrong with using the bootable memtest86 for stability testing? Not looking to be added to the table, just interested.


Yeah in total to account for sustained load/heat. In my experience memtest86 either doesn't catch errors or is extremely slow at catching them compared to HCI, Kahru, TM5, or GSAT.


----------



## hardwarelimits

Hello mates! Thinking to buy this kit https://31cad9c3-8fbb-4c77-8527-01d...d/20c502_cfb6f743e26d4df19a3ec077cf417d46.pdf 

You think I can lower them to 3800 cl 16 ( cl 14 if lucky) if my cpu allow it? That's the cheapest B-die I found. Thanks


----------



## Forsaken1

hardwarelimits said:


> Hello mates! Thinking to buy this kit https://31cad9c3-8fbb-4c77-8527-01d...d/20c502_cfb6f743e26d4df19a3ec077cf417d46.pdf
> 
> You think I can lower them to 3800 cl 16 ( cl 14 if lucky) if my cpu allow it? That's the cheapest B-die I found. Thanks


Solid choice to play with.3800 cl14 no sweat pumping volts.


----------



## rastaviper

hardwarelimits said:


> Hello mates! Thinking to buy this kit https://31cad9c3-8fbb-4c77-8527-01d...d/20c502_cfb6f743e26d4df19a3ec077cf417d46.pdf
> 
> You think I can lower them to 3800 cl 16 ( cl 14 if lucky) if my cpu allow it? That's the cheapest B-die I found. Thanks


4400 ram modules?
And what is so cheap about them?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## hardwarelimits

Forsaken1 said:


> Solid choice to play with.3800 cl14 no sweat pumping volts.


Great to know thanks.


----------



## hardwarelimits

rastaviper said:


> 4400 ram modules?
> And what is so cheap about them?
> 
> Sent from my ONEPLUS A6003 using Tapatalk


I wish I knew, but I did check on this B-die finder and they have same latency as some others G.skill kits at 8.6. They have others at 8.2ns but you have to give an arm and leg for it


----------



## rastaviper

hardwarelimits said:


> I wish I knew, but I did check on this B-die finder and they have same latency as some others G.skill kits at 8.6. They have others at 8.2ns but you have to give an arm and leg for it


So u don't know how much they cost?
Who is paying for them?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## MadSupra354

eBombzor said:


> Loosen the CL to 16. 3200 CL14 is kinda expecting too much for MFR.


Tried 16-18-18-19-38 and still needed to clear CMOS, I don't know if it's the BIOS as IIRC I was able to boot with looser timings @ 3200MHz on 1.0.0.3 ABB, or if it's the motherboard, or if MFR chips are really just a time sink trying to overclock. :confuseds


----------



## hardwarelimits

rastaviper said:


> So u don't know how much they cost?
> Who is paying for them?
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Lol.I meant they are cheaper compared to any of the 16GB 4400mhz B-die kits I searched for.


----------



## glnn_23

Playing with my TridentZ 4266c19 on an Asus x570 Impact and 3600 to see what speed I can get.

RAM test 5000% at 4533c19

In Bios

Vdimm 1.43v. (Hardware monitor 1.45v)
SOC 1.1v
VDDG. 1.0v

Cpu stock with included cooler.


----------



## rastaviper

hardwarelimits said:


> Lol.I meant they are cheaper compared to any of the 16GB 4400mhz B-die kits I searched for.





glnn_23 said:


> Playing with my TridentZ 4266c19 on an Asus x570 Impact and 3600 to see what speed I can get.
> 
> RAM test 5000% at 4533c19
> 
> In Bios
> 
> Vdimm 1.43v. (Hardware monitor 1.45v)
> SOC 1.1v
> VDDG. 1.0v
> 
> Cpu stock with included cooler.


Excuse me,

But what is the reason to pay more for 4000+ ram modules and then get worse timings and memory test score than some good 3200 modules??


----------



## Streetdragon

fun?


----------



## glnn_23

rastaviper said:


> Excuse me,
> 
> But what is the reason to pay more for 4000+ ram modules and then get worse timings and memory test score than some good 3200 modules??


Just trying for max speed here. Got an error after an hour running RT 4600mhz at same settings

These 4266 sticks are a few years old and have worked well on many platforms not just AM4. 

The 3600 may also be holding back the memory performance a little compared to a 3900x I owned. It doesn't seem to like 3800/1900 at all. 

Here's 4 of the same sticks running Aida 64 with the 12 core.
https://www.overclock.net/forum/attachment.php?attachmentid=284142&d=1564315967


----------



## kazablanka

a little bit ,better subs for my 2x8 kit config (tridentz f4-3600c16 gtr) ,and my 4x8 config ( tridentz f4-3600c16gtzr + f4-4000c18gtzkw)


----------



## rastaviper

glnn_23 said:


> Just trying for max speed here. Got an error after an hour running RT 4600mhz at same settings
> 
> 
> 
> These 4266 sticks are a few years old and have worked well on many platforms not just AM4.
> 
> 
> 
> The 3600 may also be holding back the memory performance a little compared to a 3900x I owned. It doesn't seem to like 3800/1900 at all.
> 
> 
> 
> Here's 4 of the same sticks running Aida 64 with the 12 core.
> 
> https://www.overclock.net/forum/attachment.php?attachmentid=284142&d=1564315967


Well it's known for some time now, that for the 3600 the sweet spot of memory is at 3733

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Unkzilla

Can post some screenshots later but I haven't seen many similar results out there for Hynix MFR 

On my MSI B450i board, I have 2x16 gb sticks dual rank running stable at - 3733mhz - 16-19-19-19-37-58 - 1.49v dram, 1.125v soc 

AIDA64 is around 53500 read, 54000 write, 68.5ns latency . Not bad for a cheap and nasty kit of dual rank memory. Noticed that decreasing TRFC has a big impact on latency however 580 is as low as I can go - 570 and stress tests seem to fail. Guess I must be at the limit for such crud memory 

When I upgraded recently to 1.0.0.4 bios, the above would constantly BSOD above 3600mhz. Rolled back to 1.0.0.3 and its stable again . Anyone have similar issues updating to a new bios?


----------



## MadSupra354

Unkzilla said:


> Can post some screenshots later but I haven't seen many similar results out there for Hynix MFR


What's the default XMP frequency for your kit?


----------



## Unkzilla

MadSupra354 said:


> What's the default XMP frequency for your kit?


Ah it's Gskill ripjaws V 3200- C16-18-18-18-36 at default from memory


----------



## Unkzilla

Hynix MFR/M-die @ 3733/C16 with 3800x/msi b450i motherboard , if anyone is interested in subtimings etc let me know


----------



## userxy79

Unkzilla said:


> Hynix MFR/M-die @ 3733/C16 with 3800x/msi b450i motherboard , if anyone is interested in subtimings etc let me know


This is good to know, thx for sharing that.

Would you pls share all Timings/Voltages and can you verify that it's Rockstable? Thank you.

On my CH6 with R7 1700 I struggled hard getting 2x 16Gb @2933MHz with stock Timings Rockstable. Needed Auto Voltage on SOC (was 1. 14v) and 1,42v for RAM. 

Gesendet von meinem BAH2-L09 mit Tapatalk


----------



## jcpq

I found this balance point.


----------



## Unkzilla

userxy79 said:


> This is good to know, thx for sharing that.
> 
> Would you pls share all Timings/Voltages and can you verify that it's Rockstable? Thank you.
> 
> On my CH6 with R7 1700 I struggled hard getting 2x 16Gb @2933MHz with stock Timings Rockstable. Needed Auto Voltage on SOC (was 1. 14v) and 1,42v for RAM.
> 
> Gesendet von meinem BAH2-L09 mit Tapatalk


Hi, timings are attached. Soc is 1.125v and ram is 1.49v

For stability testing its passed 8hrs of realbench, 2hrs aida64 memory test and haven't had any game crashes for weeks . Normally borderlands 3 for me will CTD within a hour if I have any stability issues and it's been absolutely fine- good enough for me 

r


----------



## Feimitsu

Ryzen 1600, Asrock B450 ITX, Corsair Vengeance LPX 3000 (CMK16GX4M2B3000C15, H5AN8G8NAFR-TFC)

I am stable at the following settings (SOC VID 0.95v, VDIMM 1.25v, [email protected] [email protected] gives errors in HCIMemtest).

Can somebody explain how it is possible that i'm stable at such low voltages? Any recommendations to improve my performance?

Thank you!


----------



## Feimitsu

Well, decided to push things a bit further:

Ryzen [email protected]@1.1V, SOC 1.1V, VDIMM 1.35V

What would be the IF clock after which there's no more scaling for Ryzen 1st Gen? I might drop clocks and work on timings.


----------



## MadSupra354

So I bought Karhu and never got an email for the download/licence. I sent the guy an email immediately and also haven't gotten a response, and this was 3 days ago. Any advice?


----------



## gerardfraser

MadSupra354 said:


> So I bought Karhu and never got an email for the download/licence. I sent the guy an email immediately and also haven't gotten a response, and this was 3 days ago. Any advice?


Wait a bit, he/she could be in the hospital ,family member sick ,on vacation or just not checking email for a week or two. I do not think he/she is trying to rip you off ,also I do not use the program but the person is probably on this site or someone knows the person.
Yep best advice give it a week or two,it does suck but there are plenty of free tools to use while waiting.


----------



## hesee

gerardfraser said:


> Wait a bit, he/she could be in the hospital ,family member sick ,on vacation or just not checking email for a week or two. I do not think he/she is trying to rip you off ,also I do not use the program but the person is probably on this site or someone knows the person.
> Yep best advice give it a week or two,it does suck but there are plenty of free tools to use while waiting.


Yep, i agree. I met the guy once, didn't feel like conjob material. He might still be in graduation/job limbo, but if there's no answer within week, then it's better to send another email. And double check spam folder.


----------



## MadSupra354

hesee said:


> I met the guy once, didn't feel like conjob material.


 I understand he's not robbing me, especially for €8. I just wondered if anyone knew if he was active on here for example, or if there were other ways to contact him, or if there was any information I might've not known.


----------



## korzychxp

Hi. I searched the entire internet and despite the fact that the we have yet 3rd series of Ryzens and we still do not know which timing are affecting memory latency. Ill test it in AIDA. At now i have 68ns with 3733Mhz CL16 memory.


On Ryzen 2700X i had on similar timings and 3600Mhz 63ns.


Check my timings here:










What i can do to lower it? My friends have 66ns on their Ryzen 3 CPUs. 2 ns is way to much loss of performance


My rams are crucial ballistic sport lt 3000mhz cl15 which have good overclocking potential (micron e-die)


----------



## gerardfraser

korzychxp said:


> Hi. I searched the entire internet and despite the fact that the we have yet 3rd series of Ryzens and we still do not know which timing are affecting memory latency. Ill test it in AIDA. At now i have 68ns with 3733Mhz CL16 memory.
> 
> 
> On Ryzen 2700X i had on similar timings and 3600Mhz 63ns.
> 
> 
> Check my timings here:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> What i can do to lower it? My friends have 66ns on their Ryzen 3 CPUs. 2 ns is way to much loss of performance
> 
> 
> My rams are crucial ballistic sport lt 3000mhz cl15 which have good overclocking potential (micron e-die)


What are you losing performance in with a difference of 2ns.


----------



## korzychxp

In gaming. On Far Cry Primal i have 2-3 fps less on benchmark.


----------



## gerardfraser

korzychxp said:


> In gaming. On Far Cry Primal i have 2-3 fps less on benchmark.


OK in gaming ,do you game at 1920x1080 or lower or above.

Ram does not really have any affect on gaming at higher resolution and 2-3 FPS is margin of error stuff.

Your Ram setting are fine except ClkDrvStren is set to 120 try 24.


----------



## korzychxp

I'm playing on 1080p.

ClkDrvStren 120 is recommended setting from DRAM Calculator but yeah i think it is too high.

And we still don't have answer really which timings are affecting ram latency most.


----------



## gerardfraser

korzychxp said:


> I'm playing on 1080p.
> 
> ClkDrvStren 120 is recommended setting from DRAM Calculator but yeah i think it is too high.
> 
> And we still don't have answer really which timings are affecting ram latency most.


*Well if your not into all the reading below. Here is how to get your 2ns drop you want.
Change interrupt power setting to processor 1 instead of default on the current windows power plan you are using.
You can use Windows power plan settings explorer utility*
https://forums.guru3d.com/threads/windows-power-plan-settings-explorer-utility.416058/

Well the answer is not that easy but you may have just hit your limit but I doubt it. My Ram at CL16 3800Mhz or CL14 3800Mhz is around 62ns and it really does not make a difference in gaming.

I also tested Farcry Primal 1920x1080 @CL 16 3400Mhz and CL16 3800Mhz and got the same average.I tested on an AMD machine ,I would need to test on Intel machine with old graphics card to see it there is a difference for me. I could suggest setting all day to you but maybe do some reading ,this may or may not help ,worth a try.

Demystifying Memory Overclocking on Ryzen
https://www.reddit.com/r/ryzen/comments/ahtubu/xpost_from_roverclocking_demystifying_memory/

AMD Ryzen Memory Tweaking & Overclocking Guide
https://www.techpowerup.com/review/amd-ryzen-memory-tweaking-overclocking-guide/

Ryzen 3600X Tested Tight Ram Timings 2133Mhz-4200Mhz 2560x1440 Ultra settings. Results may interest you as in 94ns getting same FPS as 65ns



Spoiler


----------



## korzychxp

On Far Cry Primal minimal fps is actually most changing with RAM freq/timings.

With power plans i don't want to mess, only timings.


----------



## oRuin

I was wondering if someone could help me as I have been trying to get my system stable for 2 days.
AMD Ryzen 3700x
Gigabyte x570 Elite Motherboard
Patriot Viper Steel 16GB (2x8GB) DDR4 PC4-35200C19 4400MHz Dual Channel Kit (PVS416G440C9K)

I'm running my IF at 1800 that is stable. My memory is running at 3600 with the timings shown below. Timings are from an exported Thaiphoon full html report, imported into Ryzen Memory Calculator.
My issue is I cannot get 1T at all. It's absolutely stable at 2T but with 1T prime95 Large FFTs crashes almost instantly.

I'm at my wits end!

Thank you


----------



## Keith Myers

Turn Gear Down enabled. Almost no penalty over 1T and is as stable as 2T. Gear Down is quasi "1.5T"


----------



## oRuin

Keith Myers said:


> Turn Gear Down enabled. Almost no penalty over 1T and is as stable as 2T. Gear Down is quasi "1.5T"



Tried Gear Down on, same memtest errors.
Gave 3600mhz along with all the xmp profile timings 19-19-19-39 etc a shot with 1T. Failed @ 1.35, 1.4, 1.45, 1.5v

Two days of doing everything I possibly can to get 1T at 3600 and they just cannot do it.


----------



## oRuin

AMD Ryzen 3700x
Gigabyte x570 Elite Motherboard
Patriot Viper Steel 16GB (2x8GB) DDR4 PC4-35200C19 4400MHz Dual Channel Kit (PVS416G440C9K)

Default XMP of 19-19-19-39 @ all different volts. Fails memtest and Prime95 Large FFTs everytime with 1T enabled. Gear Down doesn't help either. Shame.


----------



## athkatla

X570 Elite supports up to 4000,
so you can't use default XMP.

Secondly this kit is not in the QVL list.


Sent from my BLA-L29 using Tapatalk


----------



## oRuin

athkatla said:


> X570 Elite supports up to 4000,
> so you can't use default XMP.
> 
> Secondly this kit is not in the QVL list.
> 
> 
> Sent from my BLA-L29 using Tapatalk


Sorry forgot to say this is running at 3400 MHz and 3600mhz. Yes I understand this isn't on the QVL.


----------



## rastaviper

athkatla said:


> X570 Elite supports up to 4000,
> so you can't use default XMP.
> 
> Secondly this kit is not in the QVL list.
> 
> 
> Sent from my BLA-L29 using Tapatalk


There are still people mentioning the QVL??
Really?
Do you know how many ram modules are out of the qvl list and they have outstanding performance?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## athkatla

No I don't know, can you please enlighten me? How many there are? 

I suppose you also are aware of how many modules are not in QVL but don't have outstanding performance. 

And finally maybe you could guide the OP with your wisdom to achieve this great performance with his kit.

Am waiting anxiously for the results as I am interested in buying this kit. 

Sent from my BLA-L29 using Tapatalk


----------



## lDevilDriverl

Hi,
Was playing with my second config (BLS8G4D30AESEK x2 edie + 2600x and Asus B450-i) got 3800cl16 on 1.45v


Spoiler


----------



## MadSupra354

Trying to get more than 2933MHz out of my Hynix MFR. 1usmus' calculator will give me timings for 3200 that will fail memory training, so I tried putting in 3200MHz at CL16 with everything else on auto with 1.35v and it POSTed. I'm not sure what to do next though, it seems importing the XMP gives the calculator optimistic timings.


----------



## rastaviper

athkatla said:


> No I don't know, can you please enlighten me? How many there are?
> 
> I suppose you also are aware of how many modules are not in QVL but don't have outstanding performance.
> 
> And finally maybe you could guide the OP with your wisdom to achieve this great performance with his kit.
> 
> Am waiting anxiously for the results as I am interested in buying this kit.
> 
> Sent from my BLA-L29 using Tapatalk


It's not something new. Search if you want to find more info.

At the end of the day, the QVL is just an indication.
For example, my trident 3200 rams weren't included at this list and still they can perform amazingly at 3733 16-15-15.

So buy the RAM that you consider as good and don't select them just from the QVL list.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## athkatla

Nice, can you share you overclocking secrets with oRuin?

Sent from my BLA-L29 using Tapatalk


----------



## glnn_23

Running a 3950x in an Asus Impact.
2 x 8Gb TridentZ 4266c19

Did a fair bit of testing ended up at 4578c18. IF 1885Mhz

Bios voltage settings
Vdimm 1.43v
Soc 1.05v
VDDG .985v


----------



## neurotix

oRuin said:


> I was wondering if someone could help me as I have been trying to get my system stable for 2 days.
> AMD Ryzen 3700x
> Gigabyte x570 Elite Motherboard
> Patriot Viper Steel 16GB (2x8GB) DDR4 PC4-35200C19 4400MHz Dual Channel Kit (PVS416G440C9K)
> 
> I'm running my IF at 1800 that is stable. My memory is running at 3600 with the timings shown below. Timings are from an exported Thaiphoon full html report, imported into Ryzen Memory Calculator.
> My issue is I cannot get 1T at all. It's absolutely stable at 2T but with 1T prime95 Large FFTs crashes almost instantly.
> 
> I'm at my wits end!
> 
> Thank you





oRuin said:


> AMD Ryzen 3700x
> Gigabyte x570 Elite Motherboard
> Patriot Viper Steel 16GB (2x8GB) DDR4 PC4-35200C19 4400MHz Dual Channel Kit (PVS416G440C9K)
> 
> Default XMP of 19-19-19-39 @ all different volts. Fails memtest and Prime95 Large FFTs everytime with 1T enabled. Gear Down doesn't help either. Shame.





Hello,

Have you set *literally every advanced setting* as shown by Ryzen DRAM Calc? Most of these are generally needed to stabilize IFclk, voltage is less important.

In the Advanced settings/AMD CBS menu of your board, please set VPP_MEM voltage, VTT_DDR voltage (half of RAM clock), and every setting (or nearly every setting) I highlighted in red in this image:











You need to set CAD_Bus settings, BankGroupSwap_Alt, Proc_ODT and all voltages correctly too

If you're already doing this, no worries, don't mean to patronize, but a lot of people here are lazy with Ryzen memory overclocking and dont set literally every setting (or are too stupid to go into every single menu in AMD CBS under advanced, where they all are... ) then wonder why they can't get their memory past 3600MHz. I've mostly given up helping because certain people refuse to listen

I assume at the least you are entering every timing: in that case, some of the primary + subtimings its telling you to set are pretty aggressive and will fail to POST on my setup- or they will and I'll boot into Windows and it will be fine, but I'll reboot and my board won't post (15, 22, 8d, and eventually F9 (Loading Recovery Module) POST codes) and I will have to reset it and load a profile again

I can tell you 100% that especially on more recent BIOS versions, I've had serious issues running my RAM at any frequency @ CAS14, regardless of voltage. They will do 3800 c16 and I've even done 4066/1866 fclk cas 16, but aren't stable anymore at XMP at 3200MHz 14-14-14-14-39-55! (On AGESA 1.0.0.3, BIOS 0803 on my system when I first got this setup they were fine and even did those timings at 3600MHz)

So I would suggest setting every advanced setting I listed; even missing FFE and DFE Training in my case can cause my system to fail to boot at high fclk.

I would also suggest

CAS: 16
tRCDWR: 16
tRCDRD: 17 (this one often needs to be one clock higher)
tRP: 16
tRAS: 32 (30 is too low and will be crash prone)
tRC: 50, or 55 (48 is too low and will be crash prone)
tCWL: 16
tRFC: 304 or 312 (288 is riding the edge of whats possible)
tFAW: 16, 20 or 24. Preferably 20 but if it errors try 24. 12 is ludicriously low.
bring up tRRDS to 6 and tRRDL to 8


These are much looser timings but I can run these from 3600 all the way to 4066 if I wish, I keep it synchronous at 3800/1900

If you want tighter primaries, try 14-15-16-15-32-47 (or 48). tRC = tRP + tRAS 

Always test by booting in 2T first, as Ryzen 3000 seems to have problems with the IMC and Infinity Fabric training initial overclocks at 1T or even 1T GDM ON. Also, start low and raise memory frequency gradually- 3200/1600, then 3600/1800, then 3733/1866 or 3800/1900. Theres a bug in the bios on my board currently where if you try and go right from 2400 or whatever to 3800 without first running the fclk at 1600MHz then 1800MHz, it will essentially never boot, regardless of settings, voltage, etc.

With either timing set I gave, if you still have issues then loosen your ProcODT termination impedance- raise it to 36.9 and run all the ones below it at 24. You can also try raising each of these values one notch higher, but it's not recommended.

I'd start with changing all this, trying my timings, and booting at 3200/1600 THEN 3600/1800 after making the changes, at 2T first, then try 1T GDM, (if it fails here raise timings e.g. use the first set I gave), then 1T. Good luck.

I remember in the 90s when Patriot, Kingston and Corsair were the shizz for DRAM... but since I've been building (2009), I only use G.SKILL

Been a happy camper. If they can't do XMP and can't even run 3600/1800 (i.e. if all my advice fails you), then RMA or return (as its defective or not compatible) and get my kit. G.SKILL Flare X 3200MHz 14-14-14-34 (20nm Samsung B-Die, 8.7ns cas stock). You won't be disappointed. Out of the two others here with Ryzen and the kit I have, all of us can OC to very high margins and low timings, and this kit is guaranteed Samsung B-Die, whereas the TridentZ Neo RGB 3600 c16 that youtube tech personalities are pushing can be either SKHynix or Samsung. It was like $119. https://www.amazon.com/G-SKILL-Flar...qid=1575510912&sprefix=g.skill+flare+x&sr=8-1

Im thrilled with what this kit does, I've been OCing RAM since DDR-266 (cas 2!) and never had a kit overclock this well. It literally runs 13 memory dividers higher than what it's rated for (3200 c14 -> 4066 c16)

Anyway I hope this helps you as well as others. Let me know how it goes. If anyone else needs help, feel free to ask- I'll keep an eye on this thread for a while and take a break from Forza... btw, anyone playing The Outer Worlds? Is it good? I haven't liked any Western PC RPGs since the last Dragon Age game (which everyone else hates but I enjoyed.) This rig has always primarily been equipped for 60Hz, immersive single player RPGs... Outer Worlds looks interesting and I'd love to play a high end RPG on my new Ultrawide...


----------



## rastaviper

neurotix said:


> Hello,
> 
> 
> 
> Have you set *literally every advanced setting* as shown by Ryzen DRAM Calc? Most of these are generally needed to stabilize IFclk, voltage is less important.
> 
> 
> 
> In the Advanced settings/AMD CBS menu of your board, please set VPP_MEM voltage, VTT_DDR voltage (half of RAM clock), and every setting (or nearly every setting) I highlighted in red in this image:
> 
> 
> 
> 
> 
> View attachment 310154
> 
> 
> 
> 
> 
> 
> You need to set CAD_Bus settings, BankGroupSwap_Alt, Proc_ODT and all voltages correctly too
> 
> 
> 
> If you're already doing this, no worries, don't mean to patronize, but a lot of people here are lazy with Ryzen memory overclocking and dont set literally every setting (or are too stupid to go into every single menu in AMD CBS under advanced, where they all are... ) then wonder why they can't get their memory past 3600MHz. I've mostly given up helping because certain people refuse to listen
> 
> 
> 
> I assume at the least you are entering every timing: in that case, some of the primary + subtimings its telling you to set are pretty aggressive and will fail to POST on my setup- or they will and I'll boot into Windows and it will be fine, but I'll reboot and my board won't post (15, 22, 8d, and eventually F9 (Loading Recovery Module) POST codes) and I will have to reset it and load a profile again
> 
> 
> 
> I can tell you 100% that especially on more recent BIOS versions, I've had serious issues running my RAM at any frequency @ CAS14, regardless of voltage. They will do 3800 c16 and I've even done 4066/1866 fclk cas 16, but aren't stable anymore at XMP at 3200MHz 14-14-14-14-39-55! (On AGESA 1.0.0.3, BIOS 0803 on my system when I first got this setup they were fine and even did those timings at 3600MHz)
> 
> 
> 
> So I would suggest setting every advanced setting I listed; even missing FFE and DFE Training in my case can cause my system to fail to boot at high fclk.
> 
> 
> 
> I would also suggest
> 
> 
> 
> CAS: 16
> 
> tRCDWR: 16
> 
> tRCDRD: 17 (this one often needs to be one clock higher)
> 
> tRP: 16
> 
> tRAS: 32 (30 is too low and will be crash prone)
> 
> tRC: 50, or 55 (48 is too low and will be crash prone)
> 
> tCWL: 16
> 
> tRFC: 304 or 312 (288 is riding the edge of whats possible)
> 
> tFAW: 16, 20 or 24. Preferably 20 but if it errors try 24. 12 is ludicriously low.
> 
> bring up tRRDS to 6 and tRRDL to 8
> 
> 
> 
> 
> 
> These are much looser timings but I can run these from 3600 all the way to 4066 if I wish, I keep it synchronous at 3800/1900
> 
> 
> 
> If you want tighter primaries, try 14-15-16-15-32-47 (or 48). tRC = tRP + tRAS
> 
> 
> 
> Always test by booting in 2T first, as Ryzen 3000 seems to have problems with the IMC and Infinity Fabric training initial overclocks at 1T or even 1T GDM ON. Also, start low and raise memory frequency gradually- 3200/1600, then 3600/1800, then 3733/1866 or 3800/1900. Theres a bug in the bios on my board currently where if you try and go right from 2400 or whatever to 3800 without first running the fclk at 1600MHz then 1800MHz, it will essentially never boot, regardless of settings, voltage, etc.
> 
> 
> 
> With either timing set I gave, if you still have issues then loosen your ProcODT termination impedance- raise it to 36.9 and run all the ones below it at 24. You can also try raising each of these values one notch higher, but it's not recommended.
> 
> 
> 
> I'd start with changing all this, trying my timings, and booting at 3200/1600 THEN 3600/1800 after making the changes, at 2T first, then try 1T GDM, (if it fails here raise timings e.g. use the first set I gave), then 1T. Good luck.
> 
> 
> 
> I remember in the 90s when Patriot, Kingston and Corsair were the shizz for DRAM... but since I've been building (2009), I only use G.SKILL
> 
> 
> 
> Been a happy camper. If they can't do XMP and can't even run 3600/1800 (i.e. if all my advice fails you), then RMA or return (as its defective or not compatible) and get my kit. G.SKILL Flare X 3200MHz 14-14-14-34 (20nm Samsung B-Die, 8.7ns cas stock). You won't be disappointed. Out of the two others here with Ryzen and the kit I have, all of us can OC to very high margins and low timings, and this kit is guaranteed Samsung B-Die, whereas the TridentZ Neo RGB 3600 c16 that youtube tech personalities are pushing can be either SKHynix or Samsung. It was like $119. https://www.amazon.com/G-SKILL-Flar...qid=1575510912&sprefix=g.skill+flare+x&sr=8-1
> 
> 
> 
> Im thrilled with what this kit does, I've been OCing RAM since DDR-266 (cas 2!) and never had a kit overclock this well. It literally runs 13 memory dividers higher than what it's rated for (3200 c14 -> 4066 c16)
> 
> 
> 
> Anyway I hope this helps you as well as others. Let me know how it goes. If anyone else needs help, feel free to ask- I'll keep an eye on this thread for a while and take a break from Forza... btw, anyone playing The Outer Worlds? Is it good? I haven't liked any Western PC RPGs since the last Dragon Age game (which everyone else hates but I enjoyed.) This rig has always primarily been equipped for 60Hz, immersive single player RPGs... Outer Worlds looks interesting and I'd love to play a high end RPG on my new Ultrawide...


Very nice post, but just wanted to mention that from my personal experience with my Bdies Trident 3200 [email protected] 16-15-15 1T, there was no difference at all for me when adding the advanced settings.
Also in some cases, my system couldn't boot when I was selecting them according to the calculator.
So I just left them alone and started tuning only the standard settings.
And these are the results:









Sent from my ONEPLUS A6003 using Tapatalk


----------



## newls1

guess maybe I got lucky? my 4x16gb sticks of gskill neo 3600 (Hynix DJR modules) really do quite well in this asus c8h motherboard. using this calc program im at 3733/1866 @ 1.4v CL16 for 64gb ram. More then enough performance for me and NO ISSUES what so ever yet.


----------



## neurotix

rastaviper;

If you turn BankGroupSwap_Alt on, and possibly other settings needed to make it boot with it on, your Memory Copy bandwidth would be closer to 58GB/Sec, possibly even 60GB/Sec

Memory Copies are by far the most often used Memory operation; *especially* in gaming. You are missing out on free fps.

I'd be remiss, and letting down all my friends on this site from years gone, if I didn't advise you all to go into a menu for 10 minutes, learn where these options are, and learn your bios and how to set these parameters


----------



## rastaviper

neurotix said:


> rastaviper;
> 
> 
> 
> If you turn BankGroupSwap_Alt on, and possibly other settings needed to make it boot with it on, your Memory Copy bandwidth would be closer to 58GB/Sec, possibly even 60GB/Sec
> 
> 
> 
> Memory Copies are by far the most often used Memory operation; *especially* in gaming. You are missing out on free fps.
> 
> 
> 
> I'd be remiss, and letting down all my friends on this site from years gone, if I didn't advise you all to go into a menu for 10 minutes, learn where these options are, and learn your bios and how to set these parameters


Any idea where is this option at a Gigabyte x570 bios?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## neurotix

rastaviper said:


> Any idea where is this option at a Gigabyte x570 bios?
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Find the AMD CBS menu. It will be somewhere in there, if present. (It is probably under the Advanced section.)

If you have no AMD CBS menu with a ton of settings in it anywhere, I can't help you, sorry.


----------



## rastaviper

neurotix said:


> Find the AMD CBS menu. It will be somewhere in there, if present. (It is probably under the Advanced section.)
> 
> 
> 
> If you have no AMD CBS menu with a ton of settings in it anywhere, I can't help you, sorry.


I do have the CBS menu, but there is no such setting there.
I have already checked that

Sent from my ONEPLUS A6003 using Tapatalk


----------



## neurotix

Don't know what to tell you!


----------



## Synoxia

I advise you guys that test with HCI memtest, if you want a even more extensive test try loading up a gpu/cpu/ram intensive game like ac odyssey along with hci, i've found out i am not stable anymore but now i am rock solid even after that D:


----------



## Anusha

I ran into an issue recently. Wondering if you can give me some advice.

I have a R7 2700 on a MSI B450 Gaming Pro Carbon AC. I originally had a Corsair CMK16GX4M2Z3200C16 kit with Hynix chips. I bought a new kit to upgrade to 32GB but the new kit has Samsung B-Die chips. I didn't expect that, even though I knew there have been such variants. 

Hynix: https://imgur.com/4bHEDnC
Samsung: https://imgur.com/qre5Aad

Without much tweaking, the sticks wouldn't POST at 3200MHz. They would do fine at 2933MHz.

What do you think I should do? 

I am planning to get a Ryzen 3000 or 4000 chip at some point in the future, but not sure when. It could be in a couple of months, or when Ryzen 4000/5000 comes out.

If I want to achieve 3200MHz CL16, where would you start?

Do you think I'm better offer buying another kit of the B-Die and selling the old Hynix kit (or even keeping it as a backup)?

Cheers


----------



## neurotix

Anusha said:


> snip
> 
> If I want to achieve 3200MHz CL16, where would you start?
> 
> Do you think I'm better offer buying another kit of the B-Die and selling the old Hynix kit (or even keeping it as a backup)?
> 
> Cheers




If I'm reading this right, it sounds like you are mismatching kits?

So you are trying to run 32GB, with 2 Samsung and 2 Hynix kits.

This is no good, yes, sell the Hynix kit.


----------



## Anusha

neurotix said:


> If I'm reading this right, it sounds like you are mismatching kits?
> 
> So you are trying to run 32GB, with 2 Samsung and 2 Hynix kits.


Yes, unintentionally. It's a shame there is no way to determine which chips the kit is using without opening it.



neurotix said:


> This is no good, yes, sell the Hynix kit


Is this as a general guideline, or also applies to newer Ryzen CPUs which have better memory controllers? 

Do you think it's worth playing around with manual timings to find a common ground between the two? Or is it almost impossible to achieve this with 3200MHz or higher speeds?


----------



## athkatla

What I would do is use Ryzen master to write down all timings for each kit then use both kits and manually enter in BIOS the highest values (slower timings) from each kit.

Primary timings should be the same, the differences should be on the secondary and tertiary ones.


----------



## rastaviper

Anusha said:


> Yes, unintentionally. It's a shame there is no way to determine which chips the kit is using without opening it.
> 
> 
> 
> 
> 
> Is this as a general guideline, or also applies to newer Ryzen CPUs which have better memory controllers?
> 
> 
> 
> Do you think it's worth playing around with manual timings to find a common ground between the two? Or is it almost impossible to achieve this with 3200MHz or higher speeds?


For as long as I remember, there were always incompatibilities if mixing different brands and modules.
Always stick to the same batch of modules, especially when overclocking.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## neurotix

delete


----------



## minal

neurotix said:


> View attachment 311548
> 
> 
> 
> GSAT/stressapptest stability, 1H, 3800MHz/1900MHz 16-16-16-16-32-50 1T, 1.42v
> 
> Unfortunately, the motherboard support is incomplete, so dmidecode on a bare metal install of Linux seems to be missing information, and I have no way to show/prove the rest of the timings, just that its stable at 3800MT/s


 +1 for linux results!


Yes dmidecode info is incomplete (and inaccurate for VDIMM), unfortunately.


----------



## Gadfly

Anyone got a 3800C14 Samsung B die dual rank profile?


----------



## Rayleighzero

Just a very quick question boys.. would u mind sharing your 4x8GB SR B-die Results / timings i got my flares X varely below the xmp at 14-14-14-34-54 - 3200.. also on which AGESA.. X470 Prime Pro / 2700x on my build


----------



## rastaviper

Wow,
First time going under 63ns for Aida latency!!
*62.8* at 3733 15-14-14 1.45v!
3600x @4400


----------



## Nizzen

rastaviper said:


> Wow,
> First time going under 63ns for Aida latency!!
> *62.8* at 3733 15-14-14 1.45v!
> 3600x @4400


Try Aida64 stresstest for 30min, to see if it's stable 

Nice job if it's stable!


----------



## rastaviper

Nizzen said:


> Try Aida64 stresstest for 30min, to see if it's stable
> 
> 
> 
> Nice job if it's stable!


Hmm doesn't have any problems with other benches, but it forces closes my game after 30 minutes of playing..

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Anusha

rastaviper said:


> For as long as I remember, there were always incompatibilities if mixing different brands and modules.
> Always stick to the same batch of modules, especially when overclocking.
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Got another B-Die set - so a total of 8GBx4, and I still can't do 3200. Just wouldn't post. Quite disappointed in my 2700. It's a bad clocker AND had a bad IMC.

Settled at 2933 CL14 which isn't too bad. Will try again once I get a 3xx0 or 4xx0 chip someday.


----------



## bogdi1988

Anusha said:


> Got another B-Die set - so a total of 8GBx4, and I still can't do 3200. Just wouldn't post. Quite disappointed in my 2700. It's a bad clocker AND had a bad IMC.
> 
> Settled at 2933 CL14 which isn't too bad. Will try again once I get a 3xx0 or 4xx0 chip someday.


With my 2990wx, 2933 was the most I could run with 8 sticks of ram - which would be the comparison of Ryzen running 4 sticks. Anything over 2933 was fairly unstable.


----------



## The Sandman

nvm my bad


----------



## Hequaqua

I've been trying to get my mixed kit of Flare X and Trident Z stable....just can't quite get there....so....putting up the Flare X for sale if anyone is interested:

https://www.overclock.net/forum/146...-x-f4-3200cl14d-16gfx-2-8gb.html#post28241294


----------



## hazium233

I recently switched out my 1600 for a 2700X. Still have the old Crucial Ballistix Sport AT 2666 16-18-18-38 1.2V sticks, which are Micron Rev D. I have the cores on default currently. Board is X370-F with 4012 (Pinnacle 1.0.0.2a).

14-18/16-16-36-56 3200MT/s at 1.375V with 0.950V on SOC, and VRM config at default with AI Tweaker set to manual. The timings were the same as I had used on the 1600 including the same dimm voltage.

Anyway above passed 10,500% on Ram Test, but then it generated an error on subsequent testing. I ended up using 1.4V last night and tested to >20,000% (attached with first and subsequent AIDA run).

Still not entirely sure if the SOC voltage or ProcODT might be right for this config. On the 1600, I used 1.025V and 43.3 for this set (although 48 also seemed to work). My board wants to use 1.05V SOC with "optimized defaults" even at 2666MT/s standard speed for my dimms, which seems a little absurd. For some reason this board seems to want to play with the ram timings at optimized defaults, going 16-16-16 at 1.35V and 2666MT/s if those are on auto, without selecting DOCP. I think that is a little weird, but I guess that is another topic.

I am also not sure the role Performance Bias might have played with that. On the 1600 I tested with it off, but I had left it on Auto for the 2700X.

What should cache scores look like for this processor in AIDA? Core clocks will increase the bandwidth, right? I was trying to compare to other results online but a lot of those seem to have PBO, custom core ratios, or base clock changes. Anything else change it?


----------



## Darkomax

Just got myself a 3500X from aliexpress, let's the fun begin! 1900MHz FCLK didn't work (not too surprising) but 1866 does! not bad for a low tier chip. Starting tweaking from 3766 CL16.
Edit : settled with 3733 15-17-15-35 (sadly RCDRD won't be stable below 17) at 1.45V/1.1V SoC


----------



## PL_Razer

*Possible RAM combatibility/stability issue*

Got redirected here by someone for possible issues with my ram heres cpu-z info


----------



## Booty Die

Just found out testing video games or running a GPU stress test during ram testing is essential if you're planning on playing games with your overclocked ram.
My ram timings were 100% solid in any ram test (memtest86, tm5, memtest64, etc overnight ) but when running furmark or a game on my GPU (GTX 1070 going to 60-70°C) they would start producing errors.

I'm guessing this is due to heat from my GPU, and Samsung b-die is apparently really sensitive to this.
I haven't seen any ram overclock guides mentioning this. Also, common advice seems to be to just run a ramtest 24/7 but this doesn't create the thermals inside your case you might see in real situations.

tl;dr Run a GPU/CPU stress test or play a video game as a RAM stability test. (eg. Furmark)

Any thoughts on this? I have 3 noctua fans (2 in 1 out) and a dark rock pro 4 so case cooling shouldn't be a problem. 
Had to solve this by putting my ram from 1,45v to 1,35V with looser primary timings (at a higher frequency to compensate).


----------



## rastaviper

Booty Die said:


> Just found out testing video games or running a GPU stress test during ram testing is essential if you're planning on playing games with your overclocked ram.
> 
> My ram timings were 100% solid in any ram test (memtest86, tm5, memtest64, etc overnight ) but when running furmark or a game on my GPU (GTX 1070 going to 60-70°C) they would start producing errors.
> 
> 
> 
> I'm guessing this is due to heat from my GPU, and Samsung b-die is apparently really sensitive to this.
> 
> I haven't seen any ram overclock guides mentioning this. Also, common advice seems to be to just run a ramtest 24/7 but this doesn't create the thermals inside your case you might see in real situations.
> 
> 
> 
> tl;dr Run a GPU/CPU stress test or play a video game as a RAM stability test. (eg. Furmark)
> 
> 
> 
> Any thoughts on this? I have 3 noctua fans (2 in 1 out) and a dark rock pro 4 so case cooling shouldn't be a problem.
> 
> Had to solve this by putting my ram from 1,45v to 1,35V with looser primary timings (at a higher frequency to compensate).


How exactly do you know that your RAM is producing errors during video games?
Why it can't be that your CPU or something else is causing that error?

I am asking, as I am trying to identify what is causing the freezing of my PC, while I am playing CONTROL at ultra settings. It can be after 30 or 60 minutes that the whole system freezes and I can only restart the PC. No blue screens, no error messages. My CPU temp is max at 60 degrees, and the CPU cores are at Auto.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Booty Die

First I noticed crashes in-game (some DirectX error or something) when playing cod modern warfare. 
This was odd because I didn't have any errors in any memory test.
Tried verifying the integrity of my game files and windows installation, they were all 100% normal. 

Then I ran a memtest while running a GPU stress test simultaneously because I was suspecting thermals and the errors quickly started showing. (I used Furmark and HCI Memtest (16 instances for 3700x)). 
You could also try a CPU stress test + GPU stress test and memtest simultaneously I guess. 

I've heard of people putting fans on their ram for better cooling, but haven't tested it myself.


Edit: I'm curious if there is any such thing as "temperature" sensitive timings, my sub timings are very tight and it would be great if I could just loosen one instead of lowering my voltage and primary timings.


----------



## Booty Die

rastaviper said:


> How exactly do you know that your RAM is producing errors during video games?
> Why it can't be that your CPU or something else is causing that error?
> 
> I am asking, as I am trying to identify what is causing the freezing of my PC, while I am playing CONTROL at ultra settings. It can be after 30 or 60 minutes that the whole system freezes and I can only restart the PC. No blue screens, no error messages. My CPU temp is max at 60 degrees, and the CPU cores are at Auto.
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Hey, I might have solved this game/thermal related crashes/errors by loosening my TRFC by 10%. 
I've read somewhere that it's thermally sensitive and it seems to have solved the errors. 
Lowering the DRAM voltage only slowed down the heating of my RAM but didn't solve the underlying problem. 

Haven't seen any changes in Cinebench R20, 3Dmark or other benchmarks.
Going to run some more stress tests but so far it's looking good. U could try it out.


----------



## rastaviper

Booty Die said:


> Hey, I might have solved this game/thermal related crashes/errors by loosening my TRFC by 10%.
> 
> I've read somewhere that it's thermally sensitive and it seems to have solved the errors.
> 
> Lowering the DRAM voltage only slowed down the heating of my RAM but didn't solve the underlying problem.
> 
> 
> 
> Haven't seen any changes in Cinebench R20, 3Dmark or other benchmarks.
> 
> Going to run some more stress tests but so far it's looking good. U could try it out.


Still u haven't replied to my question.
How do u know what is causing the problem.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## marcelo19941

My new setup is arriving! 3950x with crosshair viii impact and a memory kit that can do 4266 cl16 with super tight timings on my previous intel setup.
Im new to amd is there any tips for OC? Is it very different from intel?


----------



## Booty Die

rastaviper said:


> Still u haven't replied to my question.
> How do u know what is causing the problem.
> 
> Sent from my ONEPLUS A6003 using Tapatalk


I know because I stopped having instant game crashes (black screen, full stop) when I set my TRFC to a looser setting and voltage lower from my previously "24/7 ram test stable" settings. 
Tried every other "fix" I found online for the crashes, reinstalling drivers/game, etc, but only changing my ram stopped them. 

I also ran a memory test while playing a game and errors showed up after a couple of minutes, and they also showed up during GPU stress testing with furmark. 
In any other instance, the RAM was stable. This makes me think it's most likely thermally related errors from GPU/CPU heat, which doesn't show up in normal ramtests as far as I know.


----------



## Durvelle27

Hey guys i have a Ryzen 3600 rig with Some Micron RAM rated at 3200MHz CL16 but it will not boot. If i set ram to 3133MHz it boots just fine and pasts some test. But I've tried loosening timings and raising volts but still will not boot at 3200MHz

Any advice


----------



## rastaviper

Booty Die said:


> I know because I stopped having instant game crashes (black screen, full stop) when I set my TRFC to a looser setting and voltage lower from my previously "24/7 ram test stable" settings.
> 
> Tried every other "fix" I found online for the crashes, reinstalling drivers/game, etc, but only changing my ram stopped them.
> 
> 
> 
> I also ran a memory test while playing a game and errors showed up after a couple of minutes, and they also showed up during GPU stress testing with furmark.
> 
> In any other instance, the RAM was stable. This makes me think it's most likely thermally related errors from GPU/CPU heat, which doesn't show up in normal ramtests as far as I know.


Hmm weird.
No matter if I play any heavy games, my RAM temp never goes higher than 30-35 degrees. Can it be that the hw monitor doesn't work correctly?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Booty Die

rastaviper said:


> Hmm weird.
> No matter if I play any heavy games, my RAM temp never goes higher than 30-35 degrees. Can it be that the hw monitor doesn't work correctly?
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Don't have temp sensors on my RAM so I can't compare. 
Maybe try setting your RAM to stock and seeing if they fix the crashes? If they don't it's most likely something else. 
I've read somewhere B die ram is most stable at 20°C but 30-35°C certainly doesn't sound high.


----------



## The Sandman

Durvelle27 said:


> Hey guys i have a Ryzen 3600 rig with Some Micron RAM rated at 3200MHz CL16 but it will not boot. If i set ram to 3133MHz it boots just fine and pasts some test. But I've tried loosening timings and raising volts but still will not boot at 3200MHz
> 
> Any advice


Memory hole perhaps? CLDO VDDP may help if you haven't gone there yet.
https://www.overclock.net/forum/26107733-post16116.html
https://www.overclock.net/forum/26246618-post24462.html


----------



## Durvelle27

The Sandman said:


> Durvelle27 said:
> 
> 
> 
> Hey guys i have a Ryzen 3600 rig with Some Micron RAM rated at 3200MHz CL16 but it will not boot. If i set ram to 3133MHz it boots just fine and pasts some test. But I've tried loosening timings and raising volts but still will not boot at 3200MHz
> 
> Any advice
> 
> 
> 
> Memory hole perhaps? CLDO VDDP may help if you haven't gone there yet.
> https://www.overclock.net/forum/26107733-post16116.html
> https://www.overclock.net/forum/26246618-post24462.html
Click to expand...

Never updated that post

Since than I've hit 3733MHz on the RAM

Trying to see how stabile i can get with tighter timings


----------



## dajez

I have a 4000Mhz CL19 set, I'm running it atm at 3600Mhz CL14 to have IF at 1800Mhz so 1:1. What would be best, 3600 or try to get 4000 to lower timings but don't have IF at 1:1?


----------



## neurotix

Booty Die said:


> Hey, I might have solved this game/thermal related crashes/errors by loosening my TRFC by 10%.
> I've read somewhere that it's thermally sensitive and it seems to have solved the errors.
> Lowering the DRAM voltage only slowed down the heating of my RAM but didn't solve the underlying problem.
> 
> Haven't seen any changes in Cinebench R20, 3Dmark or other benchmarks.
> Going to run some more stress tests but so far it's looking good. U could try it out.





Booty Die said:


> I know because I stopped having instant game crashes (black screen, full stop) when I set my TRFC to a looser setting and voltage lower from my previously "24/7 ram test stable" settings.
> Tried every other "fix" I found online for the crashes, reinstalling drivers/game, etc, but only changing my ram stopped them.
> 
> I also ran a memory test while playing a game and errors showed up after a couple of minutes, and they also showed up during GPU stress testing with furmark.
> In any other instance, the RAM was stable. This makes me think it's most likely thermally related errors from GPU/CPU heat, which doesn't show up in normal ramtests as far as I know.





Booty Die said:


> Don't have temp sensors on my RAM so I can't compare.
> Maybe try setting your RAM to stock and seeing if they fix the crashes? If they don't it's most likely something else.
> I've read somewhere B die ram is most stable at 20°C but 30-35°C certainly doesn't sound high.



Hey, if you don't mind, can you tell me what game this was? It didn't happen to be something from the Forza series, did it?

Currently having constant CTD with no error message with Horizon 4, really want to finish it


----------



## Booty Die

neurotix said:


> Hey, if you don't mind, can you tell me what game this was? It didn't happen to be something from the Forza series, did it?
> 
> Currently having constant CTD with no error message with Horizon 4, really want to finish it


It was in COD Modern warfare and also in GTA V. 
Don't have Horizon 4 but I'm sure unstable ram can crash any game.


----------



## rastaviper

Booty Die said:


> Don't have temp sensors on my RAM so I can't compare.
> 
> Maybe try setting your RAM to stock and seeing if they fix the crashes? If they don't it's most likely something else.
> 
> I've read somewhere B die ram is most stable at 20°C but 30-35°C certainly doesn't sound high.


Don't know what changed -except the weather that is becoming colder- but the crashes had stopped.
I can play CONTROL for 2 hours without any problems.
So probably it was the CPU getting affected by the temperature. 

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Joseph Mills

[cross posted]


As I was reading through different RAM overclocking guides, I stumbled upon a spreadsheet with different overclocking results. With only 107 entries on the Zen 2 list, I thought that not many people knew about it, so here it is. The data definitely proves to be useful.
Be careful to follow the formatting on the sheet!



DDR4 Ryzen overclocking log:

https://docs.google.com/spreadsheet...MWVPcYjf6nOlr9CtkkfN78tSo/edit#gid=1814864213


The document was linked from this article:
https://github.com/integralfx/MemTe...DR4 OC Guide.md#finding-the-maximum-frequency


----------



## mrab54

*Troubles running @ 3600 F4-3600C16D-32GVKC*

I have a new build:

3900x
Gigabyte x570 aorus pro wifi
F4-3600C16D-32GVKC 2x16GB Dual rank 16-19-19-36 DDR4-3600

Right off the bat, I booted to BIOS and enabled XMP. Save, reboot. Nada.

Then began the fun. I've been out of the loop as I'm upgrading from a 2700k Intel rig. 

I get up to speed, run Taiphoon to get XMP values, import that to DRAM Calculator, run Ryzen 2 gen, Hynix CJR (even though it's D-die), V1 profile, 2 rank, 3600 MT/s, 2 modules, x570, Calculate Safe.

I set all values according to DRAM, no boot. I tried setting my XMP values and then filling in the gap with DRAM values, no boot. Played with Alternate procODT of 60 and 48, no boot. Tried bumping DRAM voltage to 1.36, no boot. 

I lowered the RAM speed to 3200 and I boot and appear stable - I've run P95 for about 30 mins, and the stressapptest tool for the same.

I'm at a loss here. I think I should just try returning the sticks and stop wasting my time. Am I missing something here? I've never had such troubles getting something to run at advertised speeds.

Thanks!


----------



## elmntfrlif

Have you tried upping your SOC voltage? The calculator recommends 1.1v. I run my SOC at 1.08v to get 3800 stable on my 3950x


----------



## mrab54

Yes I'm at 1.1 soc.


----------



## mrab54

My motherboard doesn't have many of the settings on the Advanced tab -> Memory Interleaving and no PMU Training settings. I manually set L1/L2 Prefetcher enabled, spread spectrum enabled, bumped the vddp and vddg a little bit, DRAM at 1.4, 1.45 seemed to make no difference. I think my trfc values were off, trfc2 and 4 were higher, so now set them according to calculator at 630/468/288. I've tried playing with procODT settings, 53/60/48 and +/- a value to that - doesn't seem to do much but get better results at 53 or 60.

When I try to boot at 3600, some of the time I do get the box to beep and see the mobo LED's go from CPU->MEM->VGA->beep but then it just restarts. 3400 I can boot into Windows but get memory errors. 3200 I boot and seem stable.

So, is it just the RAM or is it motherboard?


----------



## zugok

I have the exact same ram (ripjaws) on my new build, 2 sets for a total of 64gb.

Maybe running memtest86 at your motherboards UEFI Defaults might be useful to make sure the hardware is ok? The memtest86 test passed at default UEFI settings for me, so maybe that means the MB and ram are ok?

My build, is a 2700x & Asrock Taichi x570, and cannot boot @3600 only 3200 reliably so far. However it won't pass the Memtest86 running at the DRAM calculator recommended 3200 settings.

I have been raising the DRAM to 1.4v and CPU_VDDCR_SOC Voltage to 1.025. that gets better more stable results, but still not passing the full memtest86 suite like it does at default UEFI.

Still testing+tons of reading, I tried putting all the timings to same value that seemed to make things worse.


----------



## VPII

I need to ask a question. I have two exactly the same sets of 2 x 8GB G-Skill Flare X DDR4 3200 CL14. Now both sets on their own can do 3733 with 1866 IF and it is 100% stable. I've basically with my previous 3900X and 3950X run the first set 3800 with 1900 IF which unfortunately do not work anymore with my new 3950X. At present I am only able to get the memory to run 3600 with 1800 IF with CL14 timings. I tried 3666 but I got windows 10 errors and 3733 does not even want to start. I upped the vdimm from 1.4 to 1.45 just to make sure it was working, so if someone can just explain to me whether it is possible to get the same speed with 4 sticks of ram as what you get with 2 sticks of ram.


----------



## gupsterg

VPII said:


> I need to ask a question. I have two exactly the same sets of 2 x 8GB G-Skill Flare X DDR4 3200 CL14. Now both sets on their own can do 3733 with 1866 IF and it is 100% stable. I've basically with my previous 3900X and 3950X run the first set 3800 with 1900 IF which unfortunately do not work anymore with my new 3950X. At present I am only able to get the memory to run 3600 with 1800 IF with CL14 timings. I tried 3666 but I got windows 10 errors and 3733 does not even want to start. I upped the vdimm from 1.4 to 1.45 just to make sure it was working, so if someone can just explain to me whether it is possible to get the same speed with 4 sticks of ram as what you get with 2 sticks of ram.


I've had 1x R5 3600, 1x R7 3700X and 3x R9 3900X all do 3733MHz C16 GDME 1:1:1 (FCLK:UCLK:MEMCLK) on C7HWIFI with F4-3200C14Q-32GVK. A R9 3900X out of three can do 3800MHz and the R5 3600 can also.

Originally I cracked 3800MHz on 4x8GB on the R5 3600. I found checking which dimms performed best in which slots enabled be to have access to more settable range of ProcODT at POST and also improved stability with even less stable earlier tests I had done.

So to understand what I did I'll explain about the board in use I had. The C7H is daisy chain topology, so tracing is not equidistant. From CPU socket the slots go B1 B2 A1 A2. B2 & A2 must be populated first if using 2 dimms, as they are the end slot of each memory channel and termination on signally should occur there.

Even though it was a quad channel kit I found 2 of the dimms performed better than 2 of the others when in same slots (ie B2 & A2). The pair which needed a little extra juice and tweaks to work at 3800MHz in the further slots from CPU I moved to closer slots (ie B1 & B2) when going 4x8GB. I placed the better pair in further away slots (ie A1 & A2).

The setup of dimms seemed to work well with all the other CPUs I tested later and if I deviated it from it, it adversely affected stability.


----------



## VPII

gupsterg said:


> I've had 1x R5 3600, 1x R7 3700X and 3x R9 3900X all do 3733MHz C16 GDME 1:1:1 (FCLK:UCLK:MEMCLK) on C7HWIFI with F4-3200C14Q-32GVK. A R9 3900X out of three can do 3800MHz and the R5 3600 can also.
> 
> Originally I cracked 3800MHz on 4x8GB on the R5 3600. I found checking which dimms performed best in which slots enabled be to have access to more settable range of ProcODT at POST and also improved stability with even less stable earlier tests I had done.
> 
> So to understand what I did I'll explain about the board in use I had. The C7H is daisy chain topology, so tracing is not equidistant. From CPU socket the slots go B1 B2 A1 A2. B2 & A2 must be populated first if using 2 dimms, as they are the end slot of each memory channel and termination on signally should occur there.
> 
> Even though it was a quad channel kit I found 2 of the dimms performed better than 2 of the others when in same slots (ie B2 & A2). The pair which needed a little extra juice and tweaks to work at 3800MHz in the further slots from CPU I moved to closer slots (ie B1 & B2) when going 4x8GB. I placed the better pair in further away slots (ie A1 & A2).
> 
> The setup of dimms seemed to work well with all the other CPUs I tested later and if I deviated it from it, it adversely affected stability.


Thank you @gupsterg I'll surely try this out. I'll test the dimms separately with as low a vdimm as possible running the 3733 with 1866 IF which the cpu can do, then the two dimms that can go that high at the lowest vdimm would then be the better dimms and should be moved to the outside. You can correct me if I am wrong with the way I want to check this. Thanks again.


----------



## 1usmus

*DRAM Calculator for Ryzen 1.7.0*










*Download:*
Techpowerup link
Guru3d link
Сomputerbase.de link


----------



## TwilightRavens

Anyone running a Ryzen 5 1600 (AF) or 2600(X) and have any thing to say about this set of RAM: https://www.newegg.com/product/N82E16820232860?m_ver=1 (its b-die and I have it on the way already.

I mainly curious if anyone is able to achieve the XMP profile without much issue on Zen+, or even better yet think it’ll do 3733MHz roughly (on Zen 2)? I ask because i’m thinking about snagging a Zen+ cpu and just wait out for Zen 3 since Zen 2 is already halfway into its life cycle.


----------



## lDevilDriverl

My new personal record with 2600x + Micron Rev.: E 3933cl16 =)


----------



## LicSqualo

lDevilDriverl said:


> My new personal record with 2600x + Micron Rev.: E 3933cl16 =)


INCREDIBLE! AWESOME NUMBERS!


----------



## neurotix

Here's mine with the new benchmark test

My Inter-CCX latency....can that be trusted? Guessing it's lower because I'm running synchronous 1:1 with the IMC. No idea if this is a good score for 3900X inter-CCX latency. Also throwing up my CPU-Z with clocks + the CPU-Z bench.

















*~Omai single thread ya きもち* 

There's some variance in my bus clock but CCX 0 of CCD 0 is at 4550MHz..


----------



## polkfan

https://www.reddit.com/r/Amd/comments/eyoff9/please_stop_mindlessly_advising_people_to_buy/

Shaking my head lol


----------



## neurotix

polkfan said:


> https://www.reddit.com/r/Amd/comments/eyoff9/please_stop_mindlessly_advising_people_to_buy/
> 
> Shaking my head lol


The whole problem here is morons insisting they somehow need 32GB or 64GB and buying Dual Rank B-Die DIMMs which is damn near every kit he is mentioning- and all they do is game.

A pure gaming rig is totally fine with 16GB in a single rank kit and a large page file if necessary

$120 for my kit and it is the highest bin of single rank B-Die, 3200 c14 and does 3800 c16 GDM Off, 4133 c16 and 4266 c18, so if Ryzen 4 can run memory above 4000mhz in ratio I'm set.

Then you have people who also do nothing but game and still insist on 32GB of single rank B-Die and whine about not being able to do 3800mhz or 3733mhz yet refuse to remove 2 sticks when told that then they will probably hit those speeds.

More than half the people joining the forums lately cant even figure out how to use Thaiphoon properly and create a profile and import it correctly. I see this asked almost daily. If you cant even figure this out on your own, why are you even trying?

That whole post was nothing but user error. POST code : D00F15 (doofus).


----------



## polkfan

neurotix said:


> The whole problem here is morons insisting they somehow need 32GB or 64GB and buying Dual Rank B-Die DIMMs which is damn near every kit he is mentioning- and all they do is game.
> 
> A pure gaming rig is totally fine with 16GB in a single rank kit and a large page file if necessary
> 
> $120 for my kit and it is the highest bin of single rank B-Die, 3200 c14 and does 3800 c16 GDM Off, 4133 c16 and 4266 c18, so if Ryzen 4 can run memory above 4000mhz in ratio I'm set.
> 
> Then you have people who also do nothing but game and still insist on 32GB of single rank B-Die and whine about not being able to do 3800mhz or 3733mhz yet refuse to remove 2 sticks when told that then they will probably hit those speeds.
> 
> More than half the people joining the forums lately cant even figure out how to use Thaiphoon properly and create a profile and import it correctly. I see this asked almost daily. If you cant even figure this out on your own, why are you even trying?
> 
> That whole post was nothing but user error. POST code : D00F15 (doofus).


EXACTLY 

I bought my kit years ago and its been very nice with every gen of Ryzen being able to push it higher and higher. 

I made the point that yes E-die is pretty good we all know that but insisting on people to not worry about what they get is BAD advise, one can buy a cheapo 3600mhz 19 cas kit that won't even work on Zen 2 as i read it happening, and have fun trying to get it to anything higher if your infinity fabric lets you(Zen 3 might even have a faster infinity fabric who knows?). Lol be at like 22 cas timings at that point


----------



## neurotix

polkfan said:


> EXACTLY
> 
> I bought my kit years ago and its been very nice with every gen of Ryzen being able to push it higher and higher.
> 
> I made the point that yes E-die is pretty good we all know that but insisting on people to not worry about what they get is BAD advise, one can buy a cheapo 3600mhz 19 cas kit that won't even work on Zen 2 as i read it happening, and have fun trying to get it to anything higher if your infinity fabric lets you(Zen 3 might even have a faster infinity fabric who knows?). Lol be at like 22 cas timings at that point



I've been advising people here who have trouble OCing memory to simply buy my kit and just 2 sticks. It has no rgb but its guaranteed B-Die and the best bin of it.

Too many people are watching Youtube personalities using/shilling TridentZ Neo from G.skill and while you can get it in B-Die (if you buy 8GB DIMMs that are binned lower), most are buying 2x16GB or 4x16GB kits or 4x8GB 3600 c16 kits and it seems like the majority come with Hynix D-Die.

Someone even paid like $400 for TridentZ Neo 3800mhz and was salty when they got Hynix D-Die. I'm seriously starting to question if those kits can even come with B-Die

I've even seen users here say they want the RGB so wont get another kit (buy some light strips/fans!) or won't use an Aftermarket cooler and will use the stupid Wraith cooler instead "so the RGB on their ram doesn't get covered up".

Our forums have been destroyed...


----------



## Notbn

neurotix said:


> I've been advising people here who have trouble OCing memory to simply buy my kit and just 2 sticks. It has no rgb but its guaranteed B-Die and the best bin of it.
> 
> Too many people are watching Youtube personalities using/shilling TridentZ Neo from G.skill and while you can get it in B-Die (if you buy 8GB DIMMs that are binned lower), most are buying 2x16GB or 4x16GB kits or 4x8GB 3600 c16 kits and it seems like the majority come with Hynix D-Die.
> 
> Someone even paid like $400 for TridentZ Neo 3800mhz and was salty when they got Hynix D-Die. I'm seriously starting to question if those kits can even come with B-Die
> 
> I've even seen users here say they want the RGB so wont get another kit (buy some light strips/fans!) or won't use an Aftermarket cooler and will use the stupid Wraith cooler instead "so the RGB on their ram doesn't get covered up".
> 
> Our forums have been destroyed...



Flare X is the shiz


----------



## polkfan

Notbn said:


> Flare X is the shiz


I wouldn't mind having several kits of memory just to test it out and see what it can do even more so E-die. Bullzoid does a decent job at this but its typically not practical seems like E-die doesn't mind frequency to around 4400mhz but it hates low timings and consistently requires crazy high TRFC.


----------



## neurotix

polkfan said:


> I wouldn't mind having several kits of memory just to test it out and see what it can do even more so E-die. Bullzoid does a decent job at this but its typically not practical seems like E-die doesn't mind frequency to around 4400mhz but it hates low timings and consistently requires crazy high TRFC.


Yes, repped, exactly. Especially the 500+ tRFC in most cases above 3466mhz.

Check this thread out:

https://www.overclock.net/forum/18051-memory/1735436-hynix-17nm-djrs.html


And yes this Flare X is amazing, highly recommended for the price

https://www.amazon.com/G-SKILL-Flar...14&qid=1581037320&sprefix=flare+x+3200&sr=8-2

Buy some if you're on Ryzen 3000- it overclocks fantastic. You might get 3800 c14 1T Gdm Off if you go above 1.5v (and keep it cool)

https://www.amazon.com/G-Skill-Turb...&qid=1581037413&sprefix=g.skill+turbil&sr=8-2

Hope this helps... I got Flare X because of how good Flare Pi DDR3 was


----------



## Cische

*G.Skill F4-3600C15-8GTZ*

Hi guys, I'm Italian and I'm new to this community. I'm glad to share with you what I managed to do with my current configuration. Thaiphoon says the memories should be Samsung D-Die. :headscrat
Dram voltage 1.42, SOC voltage 1.15v


----------



## gupsterg

polkfan said:


> I wouldn't mind having several kits of memory just to test it out and see what it can do even more so E-die. Bullzoid does a decent job at this but its typically not practical seems like E-die doesn't mind frequency to around 4400mhz but it hates low timings and consistently requires crazy high TRFC.


I've had:-

F4-3200C14D-16GTZ
F4-3600C15D-16GTZ
F4-3200C14Q-32GVK
F4-3200C14Q-32GTZSW
F4-4000C18Q-32GTZ
Patriot Viper Steel 4000MHz C19 2x8GB kit

Out of those 3200MHz C14 G.Skill been best buy for me. I should have BLS2K16G4D32AESB in my hands today.



neurotix said:


> Buy some if you're on Ryzen 3000- it overclocks fantastic. You might get 3800 c14 1T Gdm Off if you go above 1.5v (and keep it cool)
> 
> https://www.amazon.com/G-Skill-Turb...&qid=1581037413&sprefix=g.skill+turbil&sr=8-2


I decided to buy FTB-3500C5-D, reason for opting for that version over FTB-3500C5-DR was mainly the issue of twisting I saw in video linked below. Plus I like the frame better ascetically and I believe it's ~15mm closer to RAM.



Spoiler











In a closed case, with somewhat restricted airflow (have 360mm rad at front/top), I'm bettering temps than open bench with a 120mm fan pointed at RAM at distance. Issue I have is whine from these fans, I can hear their distinct whine over 6x F12 and 1x BQSW3. After a bit more testing I think I may change the molex connector to 3pin mobo header one and set a fan profile to improve noise profile.

Left screenie is with BQSW3 [email protected] (red arrow in photo), right is FTB-3500C5-D.



Spoiler






















As stated in the video of the other version, purchase of the fan cooler to dimm slots is not that great  ....


----------



## gupsterg

R9 3900X (Batch Code: BF 1944SUT)
C7HWIFI UEFI 3004 AGESA Combo-AM4 1.0.0.4B
Crucial Ballistix Sport LT 2x16GB kit (BLS2K16G4D32AESB)

RX Vega 64
Intel 660P 1TB NVMe on M.2_1 of mobo
ASUS Hyper M.2 x16 Card with 2x Adata SX8200 Pro 1TB NVMe (PCI-E slot in bifurcation of 4x/4x)
2x SATA HDD 2TB

Bykski A-Ryzen-ThV2-X (AS5 TIM)
2x Magicool 360 G2 Slim rads (3x Arctic Cooling F12 PWM per rad, top as exhaust, front as intake)
EK XRES 140 Revo D5 PWM

Be Quiet Dark Base 900 with mesh mod to front, upper panel mesh airflow improved. 1x Be Quiet Silent Wings 3 140mm PWM 1000rpm used as rear exhaust.

No additional cooling to RAM, 3333MHz had done RAM Test of 200%, completed a bench of AIDA64 and when went to open Ryzen Master system froze. Upped VDIMM to 1.355V on rerun did not have same issue. Run upto 3600MHz was nice and easy, ~1hr into Kahru RAM Test saw 5 errors. 3666MHz even with some changes to slights changes to ProcODT/RTT/timings/voltages hasn't gained me further stability, all tests on that MEMCLK have so far had extremely high error count in <50% run of RAM Test. At times experienced BSOD.

All test data in this ZIP, organise by time to see process better of testing so far.

So far my opinion is it's decent RAM in context of price.

I saw on the Reddit thread people saying Micron E is easier on IMC, IMO hyperbole.

Samsung B die is more flexible, is more friendly IMO, same sorta testing I can be up at 3733MHz/3800MHz with ease. If you already have B die or it is costing not vastly more than Micron E it is the better buy still with Ryzen 3000 if you value ease of OC, etc, etc.

Will carry on with more testing  .



Spoiler


----------



## basriwizz

Hi, does anyone knows how much difference there is between G.Skill's 3000C14 and 3200C14 kits (4x16GB) ?
Is it worth the price difference betwem them? (like 100$ between them)


----------



## TwilightRavens

basriwizz said:


> Hi, does anyone knows how much difference there is between G.Skill's 3000C14 and 3200C14 kits (4x16GB) ?
> 
> Is it worth the price difference betwem them? (like 100$ between them)




The 3200MHz kit is for sure b-die if the timings are 14-14-14-34, the 3000MHz kit could be b-die or it could be a Hynix MFR, CJR or even DJR kit from what I understand, I don’t think it would be rev. e because I think at 3000MHz that’s usually C15, though It could be a decent d-die bin. That’s why the 3200MHz kit costs more though and that they know most people will buy the 3200/C14 bin of b-die, even though most of the time you can get a 3600/C16 or even 4000/C18-19 kit for less most of the time if you were for sure set on b-die and searched around a bit.



Cische said:


> Hi guys, I'm Italian and I'm new to this community. I'm glad to share with you what I managed to do with my current configuration. Thaiphoon says the memories should be Samsung D-Die. :headscrat
> 
> Dram voltage 1.42, SOC voltage 1.15v




From what I understand from watching buildzoid is d-die is pretty much Samsungs version of rev. e almost exactly, so basically apply any rev e logic to it and you should be good as far as I know anyway.

Also dang, that’s a really good set of d-die with those timings holy cow.


----------



## polkfan

Cische said:


> Hi guys, I'm Italian and I'm new to this community. I'm glad to share with you what I managed to do with my current configuration. Thaiphoon says the memories should be Samsung D-Die. :headscrat
> Dram voltage 1.42, SOC voltage 1.15v


That's Samsung B-die my kit was also programmed incorrectly don't bother contacting G-skill they will say D-die but you don't get those timings with anything else but B-die


----------



## TwilightRavens

polkfan said:


> That's Samsung B-die my kit was also programmed incorrectly don't bother contacting G-skill they will say D-die but you don't get those timings with anything else but B-die




Yeah I was gonna say it has to be b-die because I have only seen a select few d-die kits that even hit 3600MHz C16, let alone ones that do better than 16-19-19-19-38. Even at 3200MHz you’re hard pressed to get 14-17-17-17-36 without stupid voltages (1.5v+).


----------



## gupsterg

I am now balled over with the price/performance of *Micron E die*  ...

First this screenie, left to right:-


3x AIDA64 for usual timings I use on Samsung B die
3x AIDA64 for current timings I'm using on Micron E die.
Initial testing for the Micron E die profile as used for 3x AIDA64.
3737% RAM Test for 3x AIDA64 3800C16, but VDIMM 1.365V.

Next 12.5K PASS in Kahru RAM Test for 3800C16 1.365V.



Spoiler











Here's an updated ZIP for 3800MHz testing so far, organise files by time, Setup means profile set in UEFI, WP means a Warm Post test run, SPx means count of testing on Same Post, when a filename is repeated exactly I'm just capturing data of the same test run but later in it.



basriwizz said:


> Hi, does anyone knows how much difference there is between G.Skill's 3000C14 and 3200C14 kits (4x16GB) ?
> Is it worth the price difference betwem them? (like 100$ between them)


Consider Micorn E die if you have 3000 series Ryzen for sure.


----------



## DeadSec

yo guys,
I came up to a stable system by loading 3600 MHz [email protected]@CR1 (Tref 288). But the 3800 MHz is a hard part. I getting reboots under CPU-load using these settings down below.
Any recommendations to get rid of this issue?


----------



## gupsterg

An updated ZIP for Micron E die 3800MHz mixed testing of ~31hrs continuous uptime, organise files by time.

Filenames at beginning have:-


Setup means test on POST when profile setup in UEFI.
FCP means a full fold POST, ie power supply switched off from wall prior to POST.
FP means a full POST from shutdown.
WP means a warm POST test run.
SPx means count of testing on same Post.
When a filename is repeated exactly, just capturing data of the same test run but later.


----------



## rastaviper

gupsterg said:


> I've had:-
> 
> 
> 
> F4-3200C14D-16GTZ
> 
> F4-3600C15D-16GTZ
> 
> F4-3200C14Q-32GVK
> 
> F4-3200C14Q-32GTZSW
> 
> F4-4000C18Q-32GTZ
> 
> Patriot Viper Steel 4000MHz C19 2x8GB kit
> 
> 
> 
> Out of those 3200MHz C14 G.Skill been best buy for me. I should have BLS2K16G4D32AESB in my hands today.
> 
> 
> 
> 
> 
> 
> 
> I decided to buy FTB-3500C5-D, reason for opting for that version over FTB-3500C5-DR was mainly the issue of twisting I saw in video linked below. Plus I like the frame better ascetically and I believe it's ~15mm closer to RAM.
> 
> 
> 
> 
> 
> Spoiler
> 
> 
> 
> https://youtu.be/fLGbRrVpngo
> 
> 
> 
> 
> 
> In a closed case, with somewhat restricted airflow (have 360mm rad at front/top), I'm bettering temps than open bench with a 120mm fan pointed at RAM at distance. Issue I have is whine from these fans, I can hear their distinct whine over 6x F12 and 1x BQSW3. After a bit more testing I think I may change the molex connector to 3pin mobo header one and set a fan profile to improve noise profile.
> 
> 
> 
> Left screenie is with BQSW3 [email protected] (red arrow in photo), right is FTB-3500C5-D.
> 
> 
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 325284
> 
> 
> 
> 
> View attachment 325286
> 
> 
> 
> 
> 
> 
> As stated in the video of the other version, purchase of the fan cooler to dimm slots is not that great  ....


I have the 3200C15-16GTZ and they are pretty good.
Managed to hit 62.5ns in Aida at 3733 15-14-14

Sent from my ONEPLUS A6003 using Tapatalk


----------



## gupsterg

An updated ZIP, organise files by time. On Micron E die 3800MHz Phase 1 mixed testing of ~48hrs continuous uptime, Phase 2 I have lowered VDIMM to set value of 1.36V, from past experience with board a read with DMM on Probeit point for this would be ~1.364V.

Filenames at beginning have:-


Setup means test on POST when profile setup in UEFI.
FCP means a full fold POST, ie power supply switched off from wall prior to POST.
FP means a full POST from shutdown.
WP means a warm POST test run.
SPx means count of testing on same Post.
When a filename is repeated exactly, just capturing data of the same test run but later.



rastaviper said:


> I have the 3200C15-16GTZ and they are pretty good.
> Managed to hit 62.5ns in Aida at 3733 15-14-14


Nice :thumb: .


----------



## runeoe

*F4-3200C16D-32GTZRX*

Hi guys, new to Ryzen and DDR4. Am currently testing 4x16GB of F4-3200C16D-32GTZRX. There doesn't seem to be a lot of information around 4x16GB overclocking. My goal is to get maximum performance within 24/7 safe voltages. (not comfortable going above 1.4v MEM)


Setup:

3600X + Asus x570 Tuf
Two kits of 2X16 F4-3200C16D-32GTZRX, (not one kit of 4x16gb)
According to typhoonburner, Dual rank, Samsung B-die???



Tests:

3200 @ 15-16-16-17-54 @1.35v, .975 SOC (6pass memtest64, 48hrs no errors, only tested stock voltage so far)
3600 @ 17-21-21-21-60 @1.40v, 1.10 SOC (memtest errors immediately @1.35v + .975 SOC, running first pass memtest64 now, no errors yet...)


Memtest64 takes around 8hours per pass... So I would appreciate some feedback before pushing further...



I've seen latency calculations like 3200/15 = latency, but doesn't seem to take into account sub-timings. How much further would my timings @3600 have to drop to be worthwhile over [email protected]? or should I just try to get 3200 to C14 and call it a day?


There are so many sub-timings, which are the most impactful/worth exploring? (other than the standard CL-X-X-RP-RAS-RC)
any other rules of thumb like RC >= RAS+RP that I should keep in mind?


----------



## TwilightRavens

runeoe said:


> Hi guys, new to Ryzen and DDR4. Am currently testing 4x16GB of F4-3200C16D-32GTZRX. There doesn't seem to be a lot of information around 4x16GB overclocking. My goal is to get maximum performance within 24/7 safe voltages. (not comfortable going above 1.4v MEM)
> 
> 
> Setup:
> 
> 3600X + Asus x570 Tuf
> Two kits of 2X16 F4-3200C16D-32GTZRX, (not one kit of 4x16gb)
> According to typhoonburner, Dual rank, Samsung B-die???
> 
> 
> 
> Tests:
> 
> 3200 @ 15-16-16-17-54 @1.35v, .975 SOC (6pass memtest64, 48hrs no errors, only tested stock voltage so far)
> 3600 @ 17-21-21-21-60 @1.40v, 1.10 SOC (memtest errors immediately @1.35v + .975 SOC, running first pass memtest64 now, no errors yet...)
> 
> 
> Memtest64 takes around 8hours per pass... So I would appreciate some feedback before pushing further...
> 
> 
> 
> I've seen latency calculations like 3200/15 = latency, but doesn't seem to take into account sub-timings. How much further would my timings @3600 have to drop to be worthwhile over [email protected]? or should I just try to get 3200 to C14 and call it a day?
> 
> 
> There are so many sub-timings, which are the most impactful/worth exploring? (other than the standard CL-X-X-RP-RAS-RC)
> any other rules of thumb like RC >= RAS+RP that I should keep in mind?




I learned a few things from watching buildzoid, b-die likes to stay under 50C range, so sometimes by raising voltage it might make it go over its stable temp threshold, check out this one:


----------



## rastaviper

TwilightRavens said:


> I learned a few things from watching buildzoid, b-die likes to stay under 50C range, so sometimes by raising voltage it might make it go over its stable temp threshold, check out this one: https://youtu.be/ZJDXsoYKZaY


I have never seen any RAM temps lot than 35 degrees, even at 1.45v
Someone should have really bad airflow to hit 50+ temps.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## TwilightRavens

rastaviper said:


> I have never seen any RAM temps lot than 35 degrees, even at 1.45v
> Someone should have really bad airflow to hit 50+ temps.
> 
> Sent from my ONEPLUS A6003 using Tapatalk




Yeah i was thinking the same thing, only time i’ve really seen it is when pushing 1.6v+.


----------



## deepor

rastaviper said:


> I have never seen any RAM temps lot than 35 degrees, even at 1.45v
> Someone should have really bad airflow to hit 50+ temps.
> 
> Sent from my ONEPLUS A6003 using Tapatalk





TwilightRavens said:


> Yeah i was thinking the same thing, only time i’ve really seen it is when pushing 1.6v+.



I have close to 50°C at 1.4V here. When I use 1.45V, it goes above 50°C. The airflow is pretty good, there's a tower air-cooler moving air in the area and the front case fans are close.

It's two sticks of 16GB 2400MHz CL17 ECC server memory. This means each memory stick has 18 memory chips on it. It has no heatspreaders. It uses Samsung B-die, and it can do 3200MHz at 1.45V and 3133MHz at 1.4V. I use it at 3133MHz with 14-17-15-31 timings and 1.4V. When I run a memory stress test or I run prime95, the warmer stick hits 48°C and the other one 46°C.


----------



## Kaltenbrunner

If I got r5 3600x or r7 3700x, would my current 2x8GB 3000MHz CL16 be fine, or is that considering slow for ryzen ?


----------



## Oversemper

*UPDATE:* final 3733cl16 1.35v is here

Crucial BLS2K16G4D32AESE, overclock from 3200 to 3733 without voltage increase. Stable everywhere, including torture tests, karhu and memtest86 over night.
All current settings in the scan below in the "curr" column, expect for RFC which is 560, not 653 (see dram memtest screenshots).
ram IC details: https://files.fm/f/k2vz9x44
Benching:

*XMP3200 at 1080p*:
CS GO# FPS Benchmark v1.01
Average framerate: 417,53

GTA 5
Frames Per Second (Higher is better) Min, Max, Avg
Pass 0, 12.209938, 165.456070, 144.305801
Pass 1, 103.996590, 249.993759, 166.070847
Pass 2, 109.861130, 227.676331, 157.566254
Pass 3, 130.093155, 194.924164, 181.341003
Pass 4, 6.560844, 272.680176, 160.962555

Time in milliseconds(ms). (Lower is better). Min, Max, Avg
Pass 0, 6.043900, 81.900497, 6.929729
Pass 1, 4.000100, 9.615700, 6.021526
Pass 2, 4.392200, 9.102401, 6.346537
Pass 3, 5.130200, 7.686800, 5.514472
Pass 4, 3.667300, 152.419403, 6.212625

*3733 at 1.35v, 18-20-18-40 CR1 RFC 560 at 1080p*:
CS GO# FPS Benchmark v1.01
Average framerate: 446.41

GTA 5
Frames Per Second (Higher is better) Min, Max, Avg
Pass 0, 31.911770, 177.383591, 154.278091
Pass 1, 131.409500, 193.764664, 173.012558
Pass 2, 119.314659, 215.280624, 165.292282
Pass 3, 77.609016, 239.068604, 182.820938
Pass 4, 7.819532, 293.746155, 167.480591

Time in milliseconds(ms). (Lower is better). Min, Max, Avg
Pass 0, 5.637500, 31.336401, 6.481802
Pass 1, 5.160900, 7.609800, 5.779927
Pass 2, 4.645100, 8.381200, 6.049889
Pass 3, 4.182900, 12.885100, 5.469833
Pass 4, 3.404300, 127.884895, 5.970841


----------



## gupsterg

[email protected] with Micron E die 2x16GB 3200C16 bin

~9hrs Kahru RAM Test
~10hrs HCI v6.0
~4hrs Y-Cruncher

~23.5hrs continuous uptime testing for that profile.

Now got SOC down to 1.025V, RAM Test ~12K% & HCI v6.0 ~200% in this ZIP.

Now on some P95.



Spoiler














3x AIDA64 for profile.



Spoiler


----------



## Oversemper

@gupsterg

Awesome!

My mobo/3800x doesn't post with any infinity fabric over 1866Mhz whatever soc voltage I set. But, anyways, I'm having only 1-1.5 ns higher latency than yours, which is not that much FPS-wise. However, your throughput (~60000Mb/s) is very fast, I wander if it's 3900x is just faster than 3800x even without overclocking ram...


----------



## gupsterg

Oversemper said:


> @gupsterg
> 
> Awesome!
> 
> My mobo/3800x doesn't post with any infinity fabric over 1866Mhz whatever soc voltage I set. But, anyways, I'm having only 1-1.5 ns higher latency than yours, which is not that much FPS-wise. However, your throughput (~60000Mb/s) is very fast, I wander if it's 3900x is just faster than 3800x even without overclocking ram...


Thanks, you've had nice gains as well :thumb: .

2 CCD CPUs (3900X/3950X) bench better in AIDA64 than 1 CCD. 1st screenie is my R5 3600 and 2nd is R9 3900X, both using same RAM MHz, etc.



Spoiler














2 of the R9 3900X I had didn't do FCLK 1900MHz, nor a R7 3700X. Only 1 of the R9 3900X and R5 3600 did FCLK 1900MHz for me.


----------



## OliverYY

I measure default SOC. Set SOC manually as required, so on remeasure they match stock. Then I up RAM strap and increase SOC as required.

1st R7 1700 2933MHz 14-14-14-14-34-1T VBOOT/VDIMM 1.35V, SOC: ~0.900V needed, could not attain 3200MHz, even with ~1.050V SOC and VCORE increase with offset of +181mV.

2nd R7 1700 3200MHz 14-14-14-34-1T VBOOT/VDIMM 1.35V, SOC: ~0.975V needed.

This was UEFI 1002 or 0902, all same HW except CPU. 1st CPU disposed of, 2nd still not reaching any higher yet. Both could use BCLK of 134MHz with lower RAM strap, with pretty much 0 tweaks to 3.8GHz / BCLK 100MHz profile. Each again attained same 2933MHz/3200MHz.


----------



## edhutner

I would like to share some experience about 1900fclk using dual rank b-dies.
The key to get stable fclk 1900mhz was VDDP voltage.
On my motherboard when vddp is auto it's actual value is depending on ddr speed. For 3200mhz vddp is 0.9V, for 3600/3733/3800 it is 1.1V.
However I cannot get stable ddr 3800mhz with vddp 1.1V. By experimenting and stress testing I found for me that lowering it to 0.93V is enough to get stable ddr 3800mhz (fclk 1900mhz) with tight timings.


----------



## neurotix

delete


----------



## gupsterg

Impressed with this £100 2x16GB Micron E kit. [email protected] with stock SOC/CLDO_VDDP/CLDO_VDDG, ~58hrs uptime mixed testing in ZIP.


----------



## Serchio

G.Skill F4-3200C14-8GTZ were nice but G.Skill F4-3600C15-8GTZ are much better. Haven't pushed them hard yet but I am going to try to go below [email protected]


----------



## rastaviper

Serchio said:


> G.Skill F4-3200C14-8GTZ were nice but G.Skill F4-3600C15-8GTZ are much better. Haven't pushed them hard yet but I am going to try to go below [email protected]


I have G.skill F4Cl15 3200 GTZ and they can do 62.5ns just fine at 3733 with 15-14-14.


Sent from my ONEPLUS A6003 using Tapatalk


----------



## Oversemper

As a continuation to this:
https://www.overclock.net/forum/10-...memory-stability-thread-308.html#post28332312

I pretty much easily made it (2x16Gb xmp3200 16-18-18 micron E-die) run stable 3733 16-19(tRCDRD19/tRCDWR16)-16-36 at stock 1.35v.
If I set tCL to 14, then I cannot post even at 1.45v. If I set tRCDRD to 18 (tRCDWR is set to 16) then memtest86 starts giving errors within 20 seconds of the test. If disable GDM with tCR at 1T also errors within first minute of the test.

With the below settings I've run memtest86 overnight, 4 hours of prime95 and 5 runs of IBM at 90% memory consumption. Gaming PUBG, GTA5, Sniper Elite 4, wolfenstein the new colossus.
For the screen below did a one hour of karhu ram test, during which hour I was browsing and watching youtube. Attached also the mobo profile for asus strix x570-f gaming bios 1405 with all these settings. A note regarding the mobo profile: for 3800x I've enabled PBO and set voltage to -0.075 offset to get lower CPU temperatures. The -0.075 offset for me decreases singe-thread cinebench score from ~530 to ~510, pretty much nothing, but it also increases the multi-thread score from ~5050 to ~5130; CPU temperature in stress testing is 2-3 degrees lower with the -0.075 offset.

Also, maybe somebody have an idea how to OC further to cl14?

*UPDATE:* Did a screenshot with 10000+ coverage (and showing power profile). Also a very important thing for me: I was having random sudden reboots when idling or when playing CPU not stressful games like sniper elite 4, I saw this thread (https://community.amd.com/thread/241981) where Mr. murky said to switch to *ryzen high performance plan*. I did that and the reboots are gone! The reboots were only at no or low cpu usage. I could stress test 24+ hours straight but then get a reboot when idling at desktop. I guess it has something to do with power consumption reduction which is more "intense" at ryzen balanced profile.

*UPDATE 2:* added MemTest86 report.


----------



## Serchio

rastaviper said:


> I have G.skill F4Cl15 3200 GTZ and they can do 62.5ns just fine at 3733 with 15-14-14.
> 
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Could you attach a screenshot from ryzen master so that I can compare my subtimings?


----------



## marcelo19941

These Trident Z Neo 3600 CL16 32Gb kits are great!


----------



## Oversemper

@marcelo19941

Yeah, top memory for top price. Which voltage are they on at 3800Mhz 14-15-14-28? And these are 16x2 or 8x4?


----------



## Serchio

marcelo19941 said:


> These Trident Z Neo 3600 CL16 32Gb kits are great!


Great kit! I had Trident Z Neo 3600 CL16 but 16 GB but I have sent them back. I had many issues with them - I couldn't even run them at [email protected]@1.48V.


----------



## marcelo19941

Oversemper said:


> @marcelo19941
> 
> Yeah, top memory for top price. Which voltage are they on at 3800Mhz 14-15-14-28? And these are 16x2 or 8x4?


They are 16x2 running at a set voltage of 1,48V on bios but readings on HWinfo says 1,504V


----------



## gupsterg

Some timings I've used so far on the Micron E 2x16GB, link.

I managed to get SOC down to 1.025V as well, in this ZIP is most recent testing, 3x AIDA64 link.

Previously on 4x8GB (single sided/rank) when using 3800MHz, I had seen I could set tRTP 5, but it would still be 6 (left screenie). On 2x16GB (dual sided/rank) you can set below 10, but it does not take (right screenie).



Spoiler


----------



## 2600ryzen

gupsterg said:


> Some timings I've used so far on the Micron E 2x16GB, link.
> 
> I managed to get SOC down to 1.025V as well, in this ZIP is most recent testing, 3x AIDA64 link.
> 
> Previously on 4x8GB (single sided/rank) when using 3800MHz, I had seen I could set tRTP 5, but it would still be 6 (left screenie). On 2x16GB (dual sided/rank) you can set below 10, but it does not take (right screenie).
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 328500



If trtp changed itself from 5 to 6 you must've had geardown mode enabled.


----------



## gupsterg

2600ryzen said:


> If trtp changed itself from 5 to 6 you must've had geardown mode enabled.


Not anything to do with gear down mode, I have only seen that affect you gain odd CAS.

Frequency and density of RAM in use seem to determine how low you can set tRTP and gain it as set. If I drop MHz even with gear down mode on it will apply.

Here's tRTP 8 with 2x16GB 3600MHz with GDME.



Spoiler


----------



## 2600ryzen

On my kit GDM affects cas, tcwl, and trtp.


----------



## gupsterg

2600ryzen said:


> On my kit GDM affects cas, tcwl, and trtp.


Hmm, strange. Not doubting your experience, but just stating not see it with HW I've used.

I've used several Samsung B die single sided/rank 8GB dimm kits on C6H, C7H, ZE & ZEA with say Zen/Zen+/Zen2, only dual sided/rank kit I've used is this Micron E TBH and only on Zen2+C7H.

*** edit ***

Gonna +rep your post as it has provoked further investigation :thumb: . 

I read a Micron DDR4 white paper and found at end of page 93/top page 94:-



> When operating in 2N gear-down mode, the following MR settings apply:
> 
> • CAS latency (MR0[6:4,2]): Even number of clocks
> • Write recovery and read to precharge (MR0[11:9]): Even number of clocks
> • Additive latency (MR1[4:3]): CL - 2
> • CAS WRITE latency (MR2 A[5:3]): Even number of clocks
> • CS to command/address latency mode (MR4[8:6]): Even number of clocks
> • CA parity latency mode (MR5[2:0]): Even number of clocks


So with GDME below must be even:-

• tCL
• tWR
• tCWL
• tRTP

So seems as if the 8 I used for tRTP at 3600MHz with GDME was allowed as it was even, will retest with 3800MHz.

*** edit2 ***

Yep tRTP 8 is applying at 3800MHz, @2600ryzen thank you for posting :thumb: .


----------



## pegadroid

please help.
i plan to build new pc with ryzen 9 3900x and asus strik x570 e
and i have ram Corsair CMR32GX4M4C3466c16 ver4.31 B-die and this ram not on qvl list.
can i run xmp without problem? i am new with amd.


----------



## Roboionator

pegadroid said:


> please help.
> i plan to build new pc with ryzen 9 3900x and asus strik x570 e
> and i have ram Corsair CMR32GX4M4C3466c16 ver4.31 B-die and this ram not on qvl list.
> can i run xmp without problem? i am new with amd.


i think will work


----------



## gupsterg

Ok tRTP 8 with some further tweaks to tRAS & tRC passed ~14k% Kahru RAM Test.



Spoiler













pegadroid said:


> please help.
> i plan to build new pc with ryzen 9 3900x and asus strik x570 e
> and i have ram Corsair CMR32GX4M4C3466c16 ver4.31 B-die and this ram not on qvl list.
> can i run xmp without problem? i am new with amd.
> 
> 
> 
> Roboionator said:
> 
> 
> 
> i think will work
Click to expand...

Will be fine.

*** edit ***

A Samsung DDR4 PDF (page 82/83) also has same information as Micron.



> For the operation of geardown mode in 1/4 rate, the following MR settings should be applied.
> CAS Latency (MR0 A[6:4,2]) : Even number of clocks
> Write Recovery and Read to Precharge (MR0 A[11:9]) : Even number of clocks
> Additive Latency (MR1 A[4:3]) : 0, CL -2
> CAS Write Latency (MR2 A[5:3]) : Even number of clocks
> CS to Command/Address Latency Mode (MR4 A[8:6]) : Even number of clocks
> CA Parity Latency Mode (MR5 A[2:0]) : Even number of clocks


*** edit 2 ***
Gear down mode is part of JEDEC DDR4 Rev B specification, so it's not a manufacturer specific implementation.


----------



## athosdewitt

hi, OC result stable 24/7 at just 1.27v , the CPU runs at stock settings since already get bottleneck by GTX 970. I've paid for 2x16GB 75 euros. / 82$ 
the kit it's good enough or nah? it is a better ideea to sell it and get 2x8GB b-die for same amount of money or the gains would be insignificant ? so many questions.. sorry about that

forgot to mention the AIDA and Ub test were made at different days.


----------



## Dannyz

Hey guys, I think I need some help tuning my memory with my Ryzen 9 3900X. No matter what I do I just can’t get these sticks to work with any config beyond stock. I believe the IMC on my 3900X is total garbage. It’s a little bit disappointing to see since I bought one the best binned kits supposedly. The G Skill Trident Z 3600MHzCL15 kit 16GB (2x8GB) F4-3600C15D-16GTZ. I’ve tried increasing different voltages as well, (DRAM, VDDG, VDDP, SOC) but it only helps prolong any instability. With the safe preset from Dram calculator(see attached images) the memory will end up erroring out at around 2000% coverage and Prime95 will reset the system within 30 minutes. I’ve seen so many posts of people getting technically worse quality kits with lower voltages stable at higher frequencies, higher IF, and tighter timing.

Here are the full system specs
CPU: Ryzen 9 3900X
CPU Cooler: NH-D15
Motherboard: X570 Aorus Master (Agesa 1003ABBA)
Memory: G skill Trident Z 16GB (2x8GB) F4-3600C15D-16GTZ
GPU: RTX 2080 XC Gaming
SSD: Samsung 970 Evo Plus
Case: Corsair Air 740
PSU: EVGA 750G2

Any help/advice is appreciated .


----------



## TwilightRavens

Dannyz said:


> Hey guys, I think I need some help tuning my memory with my Ryzen 9 3900X. No matter what I do I just can’t get these sticks to work with any config beyond stock. I believe the IMC on my 3900X is total garbage. It’s a little bit disappointing to see since I bought one the best binned kits supposedly. The G Skill Trident Z 3600MHzCL15 kit 16GB (2x8GB) F4-3600C15D-16GTZ. I’ve tried increasing different voltages as well, (DRAM, VDDG, VDDP, SOC) but it only helps prolong any instability. With the safe preset from Dram calculator(see attached images) the memory will end up erroring out at around 2000% coverage and Prime95 will reset the system within 30 minutes. I’ve seen so many posts of people getting technically worse quality kits with lower voltages stable at higher frequencies, higher IF, and tighter timing.
> 
> Here are the full system specs
> CPU: Ryzen 9 3900X
> CPU Cooler: NH-D15
> Motherboard: X570 Aorus Master (Agesa 1003ABBA)
> Memory: G skill Trident Z 16GB (2x8GB) F4-3600C15D-16GTZ
> GPU: RTX 2080 XC Gaming
> SSD: Samsung 970 Evo Plus
> Case: Corsair Air 740
> PSU: EVGA 750G2
> 
> Any help/advice is appreciated .




Try running it at 3600MHz 16-16-16-16 36 andsee if that does anything.


----------



## KedarWolf

Buildzoid DDR4 5000MHz and other RAM speeds breakdown.

https://www.youtube.com/watch?time_continue=1154&v=MLja1q-M4SU&feature=emb_logo



Spoiler






















'


----------



## gupsterg

KedarWolf said:


> Buildzoid DDR4 5000MHz and other RAM speeds breakdown.
> 
> https://www.youtube.com/watch?time_continue=1154&v=MLja1q-M4SU&feature=emb_logo
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> '


Dunno if it's the CPU speed, but seems 3800C16 is too slow in those results.

CPU stock, no performance bias/os tweaks.



Spoiler














Kahru RAM Test ~12K% PASS
HCI v6.0 ~300% PASS
Y Cruncher ~1hrs PASS
P95 non AVX 4K 8192K 26GB ~2hrs PASS
RB Stress mode 32GB ~2hrs PASS

Total ~17hrs testing in this ZIP.

I have further enhanced tRFC from 570 to 551, so far ~18hrs testing done and not yet benched it.


----------



## rares495

Ryzen 7 3700X, MSI X470 Gaming Pro, 2x8GB Corsair Vengeance LPX 3000 15-17-17-35-52(Hynix AFR) running at 3400 14-17-19-32-44 2T 1.45V - HCI 1700% (~10hrs)

All credit goes to this reddit post: https://www.reddit.com/r/overclocking/comments/adrbdf/r5_2600_hynix_afr_overclock/

I used the exact timings and settings, just have the ProcODT & RttPark set to 60 because they weren't stable at 48.


----------



## TwilightRavens

KedarWolf said:


> Buildzoid DDR4 5000MHz and other RAM speeds breakdown.
> 
> 
> 
> https://www.youtube.com/watch?time_continue=1154&v=MLja1q-M4SU&feature=emb_logo
> 
> 
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> '




That’s Rev E I assume? Or D die?


----------



## KedarWolf

TwilightRavens said:


> That’s Rev E I assume? Or D die?


The Corsair 5000 is Spectek Z11B.


----------



## KedarWolf

Buildzoid says 2x16GB Dual Rank the way to go for 32GB, even a bit better than 2x8GB. All X570 are Daisy Chain, two DIMMs better for overclocking.






I can get this kit cheap for $410 CAD including shipping, or like $17.47 USD with the current exchange. 

Trident Z Neo
DDR4-3600MHz CL16-16-16-36 1.35V
32GB (2x16GB)

https://www.gskill.com/product/165/326/1562839473/F4-3600C16D-32GTZN-Overview


----------



## dansi

After having my own zen build, i come to disagree with buildzoid findings, at least in terms of what applies for him, don't for me. So everyone needs to keep their options open.


----------



## KedarWolf

dansi said:


> After having my own zen build, i come to disagree with buildzoid findings, at least in terms of what applies for him, don't for me. So everyone needs to keep their options open.


All X570 boards are Daisy Chain, not T-Topology. so two DIMM's overclocks better than four, so if you want 32GB, 2x16 the way to go, not 4x8GB. I think 32GB is more future proof.

Buildzoid also explains in the video because on Rysen 3000 series, Dual Rank RAM can do two instructions sets at the same time or something like that, they're better than Single Rank RAM, the 8GB DIMMs, you'd have to watch the video.

The only thing I'm not 100% sure on is using two Dual Rank DIMM's worse than 2 Single Rank DIMMs for raw overclocking potential. Like could you do 3800MHz 1800 easier in Single Rank.

I know on Z390 Dual Rank overclocks much worse than Single Rank.


----------



## dcdead

2x16 GB Flare X 3200C14 Dual Rank @ 3800CL14. Karhu 20000% passed

Of course, Read and Copy values are limited by the 1-CCD CPU


----------



## Himo5

Mentioning Buildzoid I've got two 2x8Gb kits of the Patriot Viper Steel 4400 MHz CL19 set he was going wild about recently (£109 each!!) so I can try a 32Gb installation with them. 

I want to test them between X370 and X570 boards (Asus X370-F and X570-E) to see how much performance I have to make up to add video processing to a server build on the X370-F when Renoir comes to the desktop.

I tried 32Gb on the X370-F (BIOS v.5220) with an R5-1600 and can run the DOCP (19-19-19-19-39) at 3600 MHz, but have not initially been able to make anything of the 16-16-16-16-32 Safe overclock that DRAM Calculator 1.7.0 offered.

I've got an R5-3400G and an R7-3700X to try them on as well, so this may take a while.


----------



## hardwarelimits

KedarWolf said:


> All X570 boards are Daisy Chain, not T-Topology. so two DIMM's overclocks better than four, so if you want 32GB, 2x16 the way to go, not 4x8GB. I think 32GB is more future proof.
> 
> Buildzoid also explains in the video because on Rysen 3000 series, Dual Rank RAM can do two instructions sets at the same time or something like that, they're better than Single Rank RAM, the 8GB DIMMs, you'd have to watch the video.
> 
> The only thing I'm not 100% sure on is using two Dual Rank DIMM's worse than 2 Single Rank DIMMs for raw overclocking potential. Like could you do 3800MHz 1800 easier in Single Rank.
> 
> I know on Z390 Dual Rank overclocks much worse than Single Rank.


 Not all x570 boards are Daisy Chain. There's a few T-Topology. 

Check https://docs.google.com/spreadsheet...FnsZYZiW1pfiDZnKCjaXyzd1o/edit#gid=2112472504


----------



## KedarWolf

hardwarelimits said:


> Not all x570 boards are Daisy Chain. There's a few T-Topology.
> 
> Check https://docs.google.com/spreadsheet...FnsZYZiW1pfiDZnKCjaXyzd1o/edit#gid=2112472504


I read there were a few boards T-Topology prerelease but on release, they were Daisy Chain.


----------



## TwilightRavens

KedarWolf said:


> I read there were a few boards T-Topology prerelease but on release, they were Daisy Chain.




My X570 Taichi is T-Topology, so not all.


----------



## KedarWolf

TwilightRavens said:


> My X570 Taichi is T-Topology, so not all.



https://www.reddit.com/r/Amd/comments/ddcl3g/is_the_asrock_x570_taichi_ttopology_or_daisy_chain/

"It's not T-topology. Me and Gavin from Anandtech confirmed: ASRock preproduction samples (the ones given to us reviewers) are T-topology. Retail ones are daisy chain."


----------



## TwilightRavens

KedarWolf said:


> https://www.reddit.com/r/Amd/comments/ddcl3g/is_the_asrock_x570_taichi_ttopology_or_daisy_chain/
> 
> 
> 
> "It's not T-topology. Me and Gavin from Anandtech confirmed: ASRock preproduction samples (the ones given to us reviewers) are T-topology. Retail ones are daisy chain."




I must have ended up with a pre-production board then because I’ve had no issues benching my 4 x 8 rev e kit to 4400MHz without stupid loose timings with IF unlinked, or I’m just lucky.


----------



## rares495

How do you guys test FCLK stability? Aida? IBT? HCI?

I wonder how high my CPU can go but I'm not sure what to test with.


EDIT: Quick test with 1900MHz FCLK & 1700 UCLK/MEMCLK and the latency is identical in Aida64. Shouldn't there be a latency penalty? if the ratio isn't 1:1? Or does that happen only when MEMCLK > FCLK?


----------



## EmL

rares495 said:


> How do you guys test FCLK stability? Aida? IBT? HCI?


I first noticed an issue with FCLK at 1900 MHz watching a movie with MadVR/LAVFilters there was some audio stuttering. As described in this thread: https://www.reddit.com/r/MSI_Gaming/comments/el6e8m/psa_audio_poppingcrackling_potential_fix_for/

I had no issue whatsoever with TM5 extreme config, OCCT, P95, HCI memtest or anything else.

This is my 24/7 OC with a R5 3600. 

Corsair Vengeance LPX 3000CL15 - CMK16GX4M2B3000C15 running at 3600CL16 @1.390 V.
I can get them to 3800CL18 @1.40 V but I haven't had the time to try and stabilize FCLK at 1900 MHz.


----------



## rares495

EmL said:


> I first noticed an issue with FCLK at 1900 MHz watching a movie with MadVR/LAVFilters there was some audio stuttering. As described in this thread: https://www.reddit.com/r/MSI_Gaming/comments/el6e8m/psa_audio_poppingcrackling_potential_fix_for/
> 
> I had no issue whatsoever with TM5 extreme config, OCCT, P95, HCI memtest or anything else.
> 
> This is my 24/7 OC with a R5 3600.
> 
> Corsair Vengeance LPX 3000CL15 - CMK16GX4M2B3000C15 running at 3600CL16 @1.390 V.
> I can get them to 3800CL18 @1.40 V but I haven't had the time to try and stabilize FCLK at 1900 MHz.


I have the exact same SKU but they are Hynix AFR instead of Micron D-die. Thanks for the settings. 

EDIT: I was unable to push my DIMMs further, even with your settings. A B-die kit & a new motherboard will be coming soon.


----------



## neurotix

mrab54 said:


> I have a new build:
> 
> 3900x
> Gigabyte x570 aorus pro wifi
> F4-3600C16D-32GVKC 2x16GB Dual rank 16-19-19-36 DDR4-3600
> 
> Right off the bat, I booted to BIOS and enabled XMP. Save, reboot. Nada.
> 
> Then began the fun. I've been out of the loop as I'm upgrading from a 2700k Intel rig.
> 
> I get up to speed, run Taiphoon to get XMP values, import that to DRAM Calculator, run Ryzen 2 gen, Hynix CJR (even though it's D-die), V1 profile, 2 rank, 3600 MT/s, 2 modules, x570, Calculate Safe.
> 
> I set all values according to DRAM, no boot. I tried setting my XMP values and then filling in the gap with DRAM values, no boot. Played with Alternate procODT of 60 and 48, no boot. Tried bumping DRAM voltage to 1.36, no boot.
> 
> I lowered the RAM speed to 3200 and I boot and appear stable - I've run P95 for about 30 mins, and the stressapptest tool for the same.
> 
> I'm at a loss here. I think I should just try returning the sticks and stop wasting my time. Am I missing something here? I've never had such troubles getting something to run at advertised speeds.
> 
> Thanks!


Late on this.

Use the manual profile in DRAM Calc. It will spit out different timings. V1 are 1usmus benching timings for 4x8GB SR sticks. If 16-16-16-16-32-50 doesnt work (with BGS_Alt, CAD_BUS, all AMD CBS options set etc )then try 16-17-16-16 or even 16-18-16-16-36-55 as tRCDRD often needs to be higher than the rest (18 here)



zugok said:


> I have the exact same ram (ripjaws) on my new build, 2 sets for a total of 64gb.
> 
> Maybe running memtest86 at your motherboards UEFI Defaults might be useful to make sure the hardware is ok? The memtest86 test passed at default UEFI settings for me, so maybe that means the MB and ram are ok?
> 
> My build, is a 2700x & Asrock Taichi x570, and cannot boot @3600 only 3200 reliably so far. However it won't pass the Memtest86 running at the DRAM calculator recommended 3200 settings.
> 
> I have been raising the DRAM to 1.4v and CPU_VDDCR_SOC Voltage to 1.025. that gets better more stable results, but still not passing the full memtest86 suite like it does at default UEFI.
> 
> Still testing+tons of reading, I tried putting all the timings to same value that seemed to make things worse.


Your VDD_SOC is low enough that the integrated memory controller cannot function. Set it to The_Stilts recommended 1.1v and both VDDG voltages to 1.060v (-0.40 below SoC) and VDDP to 1.099 and try again. 1.06v is the lowest SoC should go and keep VDDG_CCD and VDDG_IO at -0.40v below SoC. You shouldnt mess with debug voltages if you dont understand them https://github.com/integralfx/MemTestHelper/blob/master/DDR4 OC Guide.md Everything I just recommended is from Stilts research but it works well, credit goes to him, Im just a messenger.



VPII said:


> I need to ask a question. I have two exactly the same sets of 2 x 8GB G-Skill Flare X DDR4 3200 CL14. Now both sets on their own can do 3733 with 1866 IF and it is 100% stable. I've basically with my previous 3900X and 3950X run the first set 3800 with 1900 IF which unfortunately do not work anymore with my new 3950X. At present I am only able to get the memory to run 3600 with 1800 IF with CL14 timings. I tried 3666 but I got windows 10 errors and 3733 does not even want to start. I upped the vdimm from 1.4 to 1.45 just to make sure it was working, so if someone can just explain to me whether it is possible to get the same speed with 4 sticks of ram as what you get with 2 sticks of ram.


You didnt specify timings but try 16-18-16-16-36-55 1T gdm on with 1.45v (use the manual 3800 preset for your memory grade for secondary timing: tFAW 24, 304 tRFC, etc) Those are probably looser/higher timings than you are trying to run. If using Hynix or Micron DR then try 36 or 40 tFAW and 498 tRFC as D-Die, E-Die etc like very high tRFC (but its possible to get them running 3800/1900 cas16 with more capacity and higher latency-+2ns versus B-Die and the same bandwidth, 60GB/sec Read) Advice for others who might see this and have Hynix. Flare X should be ok at 16-18-16-16-32-50 if necessary

EDIT: Also be sure to check you are raising tRCDRD to 18 not tRCDWR (some boards like mine swap them in the actual timings menu in bios) If tRCDRD = 17 doesnt boot try 18 as Gear Down Mode doesnt allow odd memory timings, only even, so 17 just becomes 16 if GDM = ON



rares495 said:


> How do you guys test FCLK stability? Aida? IBT? HCI?
> 
> I wonder how high my CPU can go but I'm not sure what to test with.
> 
> 
> EDIT: Quick test with 1900MHz FCLK & 1700 UCLK/MEMCLK and the latency is identical in Aida64. Shouldn't there be a latency penalty? if the ratio isn't 1:1? Or does that happen only when MEMCLK > FCLK?


If FCLK != MEMCLK / 2;
asynchronous_mode = 1
else
return 0;

(!= means 'is not equal to' in C, C++ etc.) basically if the divider for FCLK is not equal to exactly half of the memory clock divider, then yes the UCLK will run at half speed on Auto so 933mhz @ 1866 with a 15ns latency penalty.

You avoid this by manually setting fclk higher, running high frequency and tight timing (my kit can do 4133/1866mhz at cas 16 and it gets 65GB/sec memory copy but latency is 70ns instead of ~64ns- for bandwidth hungry applications like rendering, video etc it may be more beneficial)

UCLK is an internal bus of the chip. In this case it can run at half frequency of the MEMCLK (a new feature on Ryzen 3000) as it has been decoupled from FCLK. This allows the much higher RAM OC we are seeing. So running at half doesnt affect the MEMCLK which still runs at 3800 or whatever.. In my example the MEMCLK is 4133, manual FCLK 1866, UCLK = 933. 6ns higher latency yeah but the bandwidth is amazing. Not good for gaming, but, does great in memory intensive apps that arent as time sensitive.

Anyway I use Google GSAT/stressapptest on the command line on my secure, hardened Linux. The same way Google tests every cloud servers memory integrity/stability.

Perfect stability is chasing the wind- the impossible- we ARE running things out of spec and proven stable parameters. A BSOD every 6 mo. while gaming is inconsequential. It happened on chips I had that were super stable and binned by SiliconLottery, a setup I am way more confident in stability wise than what I have now.

SL used 1h of ROG Realbench to bin chips for a very long time; it works well and can make you crash fast for memory, too. In 10 years experience, if I was even slightly unstable, realbench would hardlock my machine when it was 24h Prime 27.9 stable, IBT 3 hrs, x264 5 passes, etc and Rwalbench would lock it up in under 5 minutes if I was pushing my setup hard 

Hope this is helpful


----------



## nick name

neurotix said:


> Late on this.
> 
> Use the manual profile in DRAM Calc. It will spit out different timings. V1 are 1usmus benching timings for 4x8GB SR sticks. If 16-16-16-16-32-50 doesnt work (with BGS_Alt, CAD_BUS, all AMD CBS options set etc )then try 16-17-16-16 or even 16-18-16-16-36-55 as tRCDRD often needs to be higher than the rest (18 here)
> 
> 
> 
> Your VDD_SOC is low enough that the integrated memory controller cannot function. Set it to The_Stilts recommended 1.1v and both VDDG voltages to 1.060v (-0.40 below SoC) and VDDP to 1.099 and try again. 1.06v is the lowest SoC should go and keep VDDG_CCD and VDDG_IO at -0.40v below SoC. You shouldnt mess with debug voltages if you dont understand them https://github.com/integralfx/MemTestHelper/blob/master/DDR4 OC Guide.md Everything I just recommended is from Stilts research but it works well, credit goes to him, Im just a messenger.
> 
> 
> 
> You didnt specify timings but try 16-18-16-16-36-55 1T gdm on with 1.45v (use the manual 3800 preset for your memory grade for secondary timing: tFAW 24, 304 tRFC, etc) Those are probably looser/higher timings than you are trying to run. If using Hynix or Micron DR then try 36 or 40 tFAW and 498 tRFC as D-Die, E-Die etc like very high tRFC (but its possible to get them running 3800/1900 cas16 with more capacity and higher latency-+2ns versus B-Die and the same bandwidth, 60GB/sec Read) Advice for others who might see this and have Hynix. Flare X should be ok at 16-18-16-16-32-50 if necessary
> 
> EDIT: Also be sure to check you are raising tRCDRD to 18 not tRCDWR (some boards like mine swap them in the actual timings menu in bios) If tRCDRD = 17 doesnt boot try 18 as Gear Down Mode doesnt allow odd memory timings, only even, so 17 just becomes 16 if GDM = ON
> 
> 
> 
> If FCLK != MEMCLK / 2;
> asynchronous_mode = 1
> else
> return 0;
> 
> (!= means 'is not equal to' in C, C++ etc.) basically if the divider for FCLK is not equal to exactly half of the memory clock divider, then yes the UCLK will run at half speed on Auto so 933mhz @ 1866 with a 15ns latency penalty.
> 
> You avoid this by manually setting fclk higher, running high frequency and tight timing (my kit can do 4133/1866mhz at cas 16 and it gets 65GB/sec memory copy but latency is 70ns instead of ~64ns- for bandwidth hungry applications like rendering, video etc it may be more beneficial)
> 
> UCLK is an internal bus of the chip. In this case it can run at half frequency of the MEMCLK (a new feature on Ryzen 3000) as it has been decoupled from FCLK. This allows the much higher RAM OC we are seeing. So running at half doesnt affect the MEMCLK which still runs at 3800 or whatever.. In my example the MEMCLK is 4133, manual FCLK 1866, UCLK = 933. 6ns higher latency yeah but the bandwidth is amazing. Not good for gaming, but, does great in memory intensive apps that arent as time sensitive.
> 
> Anyway I use Google GSAT/stressapptest on the command line on my secure, hardened Linux. The same way Google tests every cloud servers memory integrity/stability.
> 
> Perfect stability is chasing the wind- the impossible- we ARE running things out of spec and proven stable parameters. A BSOD every 6 mo. while gaming is inconsequential. It happened on chips I had that were super stable and binned by SiliconLottery, a setup I am way more confident in stability wise than what I have now.
> 
> SL used 1h of ROG Realbench to bin chips for a very long time; it works well and can make you crash fast for memory, too. In 10 years experience, if I was even slightly unstable, realbench would hardlock my machine when it was 24h Prime 27.9 stable, IBT 3 hrs, x264 5 passes, etc and Rwalbench would lock it up in under 5 minutes if I was pushing my setup hard
> 
> Hope this is helpful



Does Realbench stop on error?


----------



## neurotix

nick name said:


> Does Realbench stop on error?


Dunno as I run Linux as a main os and use stressapptest.

It was some years ago with a 4790k and FX 8350 that I used Realbench often, I think now it might (I used it on this setup but GSAT > everything else except maybe memtest86.

Generally though back on Win7 itd throw a Stop Error (BSOD) of 0x101 or 0x124 if unstable, or just hard lock so you have to hold the power button down for 5 secs to shut the system off (frozen mouse cursor or black screen)

Prime 27.9 (no AVX) is a good test too but 7nm runs very hot.

Also Ive never been a gung ho proponent of longtime testing to ensure stability. With my 4790k I just ran 5 loops of Intel x264 command line 16 thread encoding test (check the old Haswell, Skylake etc overclocking guide for x264) and if it didnt crash I would play games on it, watch youtube at 4K or now 8K, etc. for a day and if it didnt crash generally Id never have a crash in normal usage. I dont use my machine for video encoding, rendering or a webserver where its so mission critical that if it crashes once every 3 months its the end of the world. Ill deal with 99.6% stability vs 100.0%, big deal.

Ryzen DRAM Calc stress test for all free memory to 105% each thread is a good test too but it seems it passes a lot of systems and Ive seen like 50 users complain of random crashes they cant figure out while using that.

Prime95 non avx for an hour (7nm runs very hot...) is a good test of overall stability but with these high core count parts from each vendor, heat density on the package and the physics limits of the IHS make fast and effective heat removal a serious problem, which is what users like @newls1 have to deal with(what do you stress test with? how long?) He has a high end water loop but cooling a 7nm 16 core part is restricted by the ability to remove heat from the die effectively. So something like Prime95 non avx is more of a test of cooling now.

Hope this is helpful


----------



## newls1

neurotix said:


> Dunno as I run Linux as a main os and use stressapptest.
> 
> It was some years ago with a 4790k and FX 8350 that I used Realbench often, I think now it might (I used it on this setup but GSAT > everything else except maybe memtest86.
> 
> Generally though back on Win7 itd throw a Stop Error (BSOD) of 0x101 or 0x124 if unstable, or just hard lock so you have to hold the power button down for 5 secs to shut the system off (frozen mouse cursor or black screen)
> 
> Prime 27.9 (no AVX) is a good test too but 7nm runs very hot.
> 
> Also Ive never been a gung ho proponent of longtime testing to ensure stability. With my 4790k I just ran 5 loops of Intel x264 command line 16 thread encoding test (check the old Haswell, Skylake etc overclocking guide for x264) and if it didnt crash I would play games on it, watch youtube at 4K or now 8K, etc. for a day and if it didnt crash generally Id never have a crash in normal usage. I dont use my machine for video encoding, rendering or a webserver where its so mission critical that if it crashes once every 3 months its the end of the world. Ill deal with 99.6% stability vs 100.0%, big deal.
> 
> Ryzen DRAM Calc stress test for all free memory to 105% each thread is a good test too but it seems it passes a lot of systems and Ive seen like 50 users complain of random crashes they cant figure out while using that.
> 
> Prime95 non avx for an hour (7nm runs very hot...) is a good test of overall stability but with these high core count parts from each vendor, heat density on the package and the physics limits of the IHS make fast and effective heat removal a serious problem, which is what users like @newls1 have to deal with(what do you stress test with? how long?) He has a high end water loop but cooling a 7nm 16 core part is restricted by the ability to remove heat from the die effectively. So something like Prime95 non avx is more of a test of cooling now.
> 
> Hope this is helpful


he is correct.... owning this cpu for the past 5 months has taught me to stop caring about passing stability tests, cause to be 100% with y'all, i cant pass a single one with my 4.6ghz OC @ 1.31v BUT.................... I can play all my high demanding games like METRO EXODUS, FC5, ETC...... with my 2080Ti OC'ed to the roof as well, FOR DAYS with no issues and very cool temps. So the PC is doing exactly what I want it to do, with dumb cool temps and pc has never crashed 1 time on me, so I have kept this OC for 4 months now and couldnt be any happier. Stabilty tests may be important for some, but if my pc can do every single thing i want it to do with no issues and low voltage, ive taught myself to no give 2 *****s about passing a stability test. some/most might argue with me about this, but since this is my pc, and im a grown ass man, i can do what I want


----------



## neurotix

newls1 said:


> he is correct.... owning this cpu for the past 5 months has taught me to stop caring about passing stability tests, cause to be 100% with y'all, i cant pass a single one with my 4.6ghz OC @ 1.31v BUT.................... I can play all my high demanding games like METRO EXODUS, FC5, ETC...... with my 2080Ti OC'ed to the roof as well, FOR DAYS with no issues and very cool temps. So the PC is doing exactly what I want it to do, with dumb cool temps and pc has never crashed 1 time on me, so I have kept this OC for 4 months now and couldnt be any happier. Stabilty tests may be important for some, but if my pc can do every single thing i want it to do with no issues and low voltage, ive taught myself to no give 2 *****s about passing a stability test. some/most might argue with me about this, but since this is my pc, and im a grown ass man, i can do what I want


Ive benched mine at 4.55ghz/4.525/4.275/4.250 w/1.3875v @ 3800 c14.. 

Just running normal games at those clocks the cpu sits pegged at 40-45 spikes to 52c in almost every game and never crashes. Really I need something like Fire Strike Ultra looped to get my GPUs both above 100% power limit. They both heat up a lot and run above 2ghz so heat output could be close to 700w from the cards alone. If this is the situation and my rad gets hot af (heat rises/gpu coolers blow up), I might see temps on the gpus around 75/68c and temps on cpu around 60c but clocks will stabilize on the cards and it doesnt crash. Big deal. Its far too late in the game to water cool Pascal, they are custom cards (In regular games running well under 50c), last I checked EK still had the 1080ti ftw3 full Nickel block for $159 and I need two... yeah uh no

If it does what you need it to, exactly, a lot of our PCs are overbuilt by far for basic use, and despite numerous AGESA and board vendor issues, while its running its very fast. Especially great on Linux.

EDIT: Also thanks for the reply bud, been gettin ignored on some other threads :/ https://www.ekwb.com/shop/ek-fc1080-gtx-ti-ftw3-nickel


----------



## newls1

neurotix said:


> Ive benched mine at 4.55ghz/4.525/4.275/4.250 w/1.3875v @ 3800 c14..
> 
> Just running normal games at those clocks the cpu sits pegged at 40-45 spikes to 52c in almost every game and never crashes. Really I need something like Fire Strike Ultra looped to get my GPUs both above 100% power limit. They both heat up a lot and run above 2ghz so heat output could be close to 700w from the cards alone. If this is the situation and my rad gets hot af (heat rises/gpu coolers blow up), I might see temps on the gpus around 75/68c and temps on cpu around 60c but clocks will stabilize on the cards and it doesnt crash. Big deal. Its far too late in the game to water cool Pascal, they are custom cards (In regular games running well under 50c), last I checked EK still had the 1080ti ftw3 full Nickel block for $159 and I need two... yeah uh no
> 
> If it does what you need it to, exactly, a lot of our PCs are overbuilt by far for basic use, and despite numerous AGESA and board vendor issues, while its running its very fast. Especially great on Linux.
> 
> EDIT: Also thanks for the reply bud, been gettin ignored on some other threads :/ https://www.ekwb.com/shop/ek-fc1080-gtx-ti-ftw3-nickel


I ignored you in a thread? if i did, i just didnt see it and ive spent all of 45seconds on here in the past 1 month as ive been working way to much OT lately and just have ZERO time for anything else. This media driven BS craze with this virus isnt helping the 911 scene at all.... as soon as someone sneezes, coughs, or has allergies, they immediatly think they have the coronas...


----------



## hazium233

Himo5 said:


> Mentioning Buildzoid I've got two 2x8Gb kits of the Patriot Viper Steel 4400 MHz CL19 set he was going wild about recently (£109 each!!) so I can try a 32Gb installation with them.
> 
> I want to test them between X370 and X570 boards (Asus X370-F and X570-E) to see how much performance I have to make up to add video processing to a server build on the X370-F when Renoir comes to the desktop.
> 
> I tried 32Gb on the X370-F (BIOS v.5220) with an R5-1600 and can run the DOCP (19-19-19-19-39) at 3600 MHz, but have not initially been able to make anything of the 16-16-16-16-32 Safe overclock that DRAM Calculator 1.7.0 offered.
> 
> I've got an R5-3400G and an R7-3700X to try them on as well, so this may take a while.


Did you happen to test that ram on the X370-F with any of the Pinnacle bioses, like 4207? I would be interested on thoughts regarding 5220 vs them.

Also, were you always using 4 dimms, or did you ever try 2x8? Curious if this one might actually clock better with all four dimms filled.

I have this board, but had been hesitant to go to Combo. Hence the questions. 

On 4012 it isn't looking great for 2x8 over 3466, which is lining up with something another user has said about it.


----------



## nick name

hazium233 said:


> Did you happen to test that ram on the X370-F with any of the Pinnacle bioses, like 4207? I would be interested on thoughts regarding 5220 vs them.
> 
> Also, were you always using 4 dimms, or did you ever try 2x8? Curious if this one might actually clock better with all four dimms filled.
> 
> I have this board, but had been hesitant to go to Combo. Hence the questions.
> 
> On 4012 it isn't looking great for 2x8 over 3466, which is lining up with something another user has said about it.


While I don't have your board I do have an ASUS board with a 2700X. That combo ran my 3600CL15 b-die kit at 3600MHz 14-15-14-14 on all BIOS versions old and new. The new BIOS versions didn't get me any more stability at speeds beyond 3600MHz, but it did seem to get higher speeds more "bootable". 

So if you're running 3466MHz then perhaps you'll see some benefit in a newer BIOS. 

Does your mobo have BIOS flashback?


----------



## TwilightRavens

3900X + AsRock X570 Taichi + 2 x 16GB dual rank Samsung b die working flawlessly at 3600MHz (16-16-16-36).

Edit- This kit to be exact: G.SKILL Trident Z Neo (For AMD Ryzen) Series 32GB (2 x 16GB) 288-Pin RGB DDR4 SDRAM DDR4 3600 (PC4 28800) Desktop Memory Model F4-3600C16D-32GTZN https://www.newegg.com/product/N82E16820232860?ignorebbr=1&m_ver=1


----------



## neurotix

newls1 said:


> I ignored you in a thread? if i did, i just didnt see it and ive spent all of 45seconds on here in the past 1 month as ive been working way to much OT lately and just have ZERO time for anything else. This media driven BS craze with this virus isnt helping the 911 scene at all.... as soon as someone sneezes, coughs, or has allergies, they immediatly think they have the coronas...


No no no, I didnt mean you, and yes this virus stuff is ridiculous, its not the return of the black plague...



TwilightRavens said:


> 3900X + AsRock X570 Taichi + 2 x 16GB dual rank Samsung b die working flawlessly at 3600MHz (16-16-16-36).
> 
> Edit- This kit to be exact: G.SKILL Trident Z Neo (For AMD Ryzen) Series 32GB (2 x 16GB) 288-Pin RGB DDR4 SDRAM DDR4 3600 (PC4 28800) Desktop Memory Model F4-3600C16D-32GTZN https://www.newegg.com/product/N82E16820232860?ignorebbr=1&m_ver=1


Nice, I see you bit the bullet and upgraded (you had Haswell or Ivy before right?)


----------



## hazium233

nick name said:


> While I don't have your board I do have an ASUS board with a 2700X. That combo ran my 3600CL15 b-die kit at 3600MHz 14-15-14-14 on all BIOS versions old and new. The new BIOS versions didn't get me any more stability at speeds beyond 3600MHz, but it did seem to get higher speeds more "bootable".
> 
> So if you're running 3466MHz then perhaps you'll see some benefit in a newer BIOS.
> 
> Does your mobo have BIOS flashback?


No, that was practically Crosshair exclusive. If I had it (or a programmer), I might just flash around  To revert down AGESA, have to use afudos or I think Stilt modified flashrom might work.

4012 has PBO, but 4207 doesn't, which is the only reason I didn't flash it already. I think all the Combo versions have it available again, but I may just end up doing 4207 modded with PBO unlocked.


----------



## TwilightRavens

neurotix said:


> No no no, I didnt mean you, and yes this virus stuff is ridiculous, its not the return of the black plague...
> 
> 
> 
> Nice, I see you bit the bullet and upgraded (you had Haswell or Ivy before right?)


Close, a dying Z97 board with a Broadwell i7.


----------



## KedarWolf

This chip is pretty much golden. Cinebench loop stable at 4.375GHZ, 1.29V I think it was, whatever it defaults to at 1.29v, but I had to raise the power limits to get it stable, it draws more wattage and will hit 80C looping Cinebench, and memory at 3800 MHz, 16-16-16-32 1T with Ryzen calculator fast sub timings. had to raise tRFC to 315 though.


----------



## neurotix

KedarWolf said:


> This chip is pretty much golden. Cinebench loop stable at 4.375GHZ, 1.29V I think it was, whatever it defaults to at 1.29v, but I had to raise the power limits to get it stable, it draws more wattage and will hit 80C looping Cinebench, and memory at 3800 MHz, 16-16-16-32 1T with Ryzen calculator fast sub timings. had to raise tRFC to 315 though.



Nice, can you run with GearDownMode = Disabled ?

Great subtimings and nice primaries, you should post your benchmark results, Id like to see the Inner CCX Latency. AIDA64 would be great too :thumb:

EDIT: Also check the 3950x thread, newls1 has one and with manual CCX OC and 1.35v his first CCX (CCD0, CCX0) runs at 4675mhz last I heard, and is gaming stable. Running a 3950x all core 4.3ghz is a waste. The best binned chiplets period that clock the highest get used for the first CCD


----------



## KedarWolf

neurotix said:


> Nice, can you run with GearDownMode = Disabled ?
> 
> Great subtimings and nice primaries, you should post your benchmark results, Id like to see the Inner CCX Latency. AIDA64 would be great too :thumb:
> 
> EDIT: Also check the 3950x thread, newls1 has one and with manual CCX OC and 1.35v his first CCX (CCD0, CCX0) runs at 4675mhz last I heard, and is gaming stable. Running a 3950x all core 4.3ghz is a waste. The best binned chiplets period that clock the highest get used for the first CCD


Gear Down Mode disabled instant crash in Windows when running AIDA64.


----------



## KedarWolf

neurotix said:


> Nice, can you run with GearDownMode = Disabled ?
> 
> Great subtimings and nice primaries, you should post your benchmark results, Id like to see the Inner CCX Latency. AIDA64 would be great too :thumb:
> 
> EDIT: Also check the 3950x thread, newls1 has one and with manual CCX OC and 1.35v his first CCX (CCD0, CCX0) runs at 4675mhz last I heard, and is gaming stable. Running a 3950x all core 4.3ghz is a waste. The best binned chiplets period that clock the highest get used for the first CCD


I tried Ryzen Master, overclocked the fastest cores, the rest at my known stable settings, when I ran Cinebench, only the fastest cores stay at clock speeds, the rest went to 3600MHz and terrible Cinebench scores.


----------



## cassinni

Hi,

a few days ago i bought additional 16 GB RAM for my PC to take it to 32GB (4x8GB). Exactly the same RAM as I had already in my PC.
16GB (2x 8192MB) G.Skill Aegis DDR4-3000 DIMM CL16-18-18-38 Dual Kit (EAN 4719692013446 SKU F4-3000C16D-16GISB).

My PC: AMD Ryzen 5 2600 / EVGA GeForce GTX 1080 SC / MSI B450 Gaming Pro Carbon AC / 32GB G.Skill Aegis DDR4-3000 / Noctua NH-D15 / SilverStone SST-RL06WS-GP / Seasonic Focus Plus Platinum 650W / SAMSUNG NVMe SSD 970 Evo / Samsung LC32JG52QQUXEN

I was told and noticed before I made the purchace that my 16GB Ram were running since 2018 with a Dram Frequency of only 1066 MHz. (2132 MHz?)
I expected it to auto run at 3000 as it says on the ram... i was wrong.
So I get the new Ram and try to enable xmp in my MSI Bios (latest update flashed). 
I finish up with the Bios setup (pic 1). Now picture 2 is after I boot into Windows 10 Cpu-Z.
Ever since I did this Bios ram overclock to 3000 MHz I get bluescreens. "System thread exception not handled", "IRQL not less or equal" or "system service exception". I get into Windows 10 (64bits) without issues tho...

What values should I chose to get 3000 MHz or as close as possible while having a stable system?
Where do I enter these values exactly?


Please help me, its so boring without a PC while being indoors all day.


----------



## neurotix

KedarWolf said:


> I tried Ryzen Master, overclocked the fastest cores, the rest at my known stable settings, when I ran Cinebench, only the fastest cores stay at clock speeds, the rest went to 3600MHz and terrible Cinebench scores.


Bruh you need to do a manual CCX ratio overclock. Stagger it. Try 46/45/43/42 per CCD ratios with 1.375v. You have a monster water loop right? If not and youre on a tower air cooler then try 45/44.5/42.75/42.5 with the same volts.

Hopefully whatever (non ASUS) board you run has manual CCX overclocking. The chip wont downclock at all and will run much hotter- but the performance will be much higher (Ive done 8800/563 ST in cpu-z bench for example with my first CCD at 4550mhz)



cassinni said:


> Hi,
> 
> a few days ago i bought additional 16 GB RAM for my PC to take it to 32GB (4x8GB). Exactly the same RAM as I had already in my PC.
> 16GB (2x 8192MB) G.Skill Aegis DDR4-3000 DIMM CL16-18-18-38 Dual Kit (EAN 4719692013446 SKU F4-3000C16D-16GISB).
> 
> My PC: AMD Ryzen 5 2600 / EVGA GeForce GTX 1080 SC / MSI B450 Gaming Pro Carbon AC / 32GB G.Skill Aegis DDR4-3000 / Noctua NH-D15 / SilverStone SST-RL06WS-GP / Seasonic Focus Plus Platinum 650W / SAMSUNG NVMe SSD 970 Evo / Samsung LC32JG52QQUXEN
> 
> I was told and noticed before I made the purchace that my 16GB Ram were running since 2018 with a Dram Frequency of only 1066 MHz. (2132 MHz?)
> I expected it to auto run at 3000 as it says on the ram... i was wrong.
> So I get the new Ram and try to enable xmp in my MSI Bios (latest update flashed).
> I finish up with the Bios setup (pic 1). Now picture 2 is after I boot into Windows 10 Cpu-Z.
> Ever since I did this Bios ram overclock to 3000 MHz I get bluescreens. "System thread exception not handled", "IRQL not less or equal" or "system service exception". I get into Windows 10 (64bits) without issues tho...
> 
> What values should I chose to get 3000 MHz or as close as possible while having a stable system?
> Where do I enter these values exactly?
> 
> 
> Please help me, its so boring without a PC while being indoors all day.


Did you change voltage to 1.4+ (1.45 max) or change primary timings or both?


----------



## TwilightRavens

Overclocked my dual rank b die Neo kit from 3600MHz to 3733MHz on the XMP timings and i'm quite pleased with the results.


----------



## cassinni

neurotix said:


> Did you change voltage to 1.4+ (1.45 max) or change primary timings or both?


No, i did not touch it. I don't know how to do that.


----------



## KedarWolf

Here are my daily driver BIOS settings screenshots for 24/7 use. Looping Cinebench on a single 360 RAD tops out at 70C. 

I can do 4.45/4.4/4.35/4.3 at 1.325v LLC 2 but temps get a bit over 80C looping Cinibench and that troubles me. 

The IMC on my 3950x is quite good, I'm very happy with what I got, and it is 100% single Ryzen DRAM Calculator stress test with no errors. I also can loop five minutes in Cinebench. :h34r-smi

See in the Spoiler.



Spoiler


----------



## rastaviper

TwilightRavens said:


> Overclocked my dual rank b die Neo kit from 3600MHz to 3733MHz on the XMP timings and i'm quite pleased with the results.


Who am I to spoil your fun, but what exactly is that pleases you when your latency is around 70 and people are looking ways to get it at near 60s?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## TwilightRavens

rastaviper said:


> Who am I to spoil your fun, but what exactly is that pleases you when your latency is around 70 and people are looking ways to get it at near 60s?
> 
> Sent from my ONEPLUS A6003 using Tapatalk



For me, if it ain’t broke, don’t fix it. For now (until my Noctua’s get delivered for my h100i v2) it’s staying as is, however once I get that installed I probably will try and push 3800MHz or try for some CL14 or CL15 timings with 3733MHz, then all bets will be off as I won’t be limited by CPU temps. I’m also not trying to set any records or anything, something modest is enough for me to be satisfied.

I may end up breaking down and getting something beefier than my h100i that I pulled off my old Z97 like a 360mm or even a 420mm, only time will tell. I think i’ve done pretty well for now as when I first had it up and running it was at 82.9ns latency, then I set the fclk 1:1 and that dropped it to 72.6ns, then i bumped RAM speed up to 3733MHz and fclk to 1867MHz. 1867 seems to be the limit my chip will do reliably so timings reduction may be in the near future.

However my setup was not a fan of geardown mode set to disabled and i’ve heard that right there will net you a few ns less latency. You are right though, what’s the point in a $300 set of dual rank b-die to settle on something so modest, for now reliability is my reason, I need this 110% stable for my workloads and I can’t jeopardize something being unstable until I have time to sit down and fine tune it.


----------



## Veii

KedarWolf said:


> Here are my daily driver BIOS settings screenshots for 24/7 use. Looping Cinebench on a single 360 RAD tops out at 70C.
> 
> I can do 4.45/4.4/4.35/4.3 at 1.325v LLC 2 but temps get a bit over 80C looping Cinibench and that troubles me.
> 
> The IMC on my 3950x is quite good, I'm very happy with what I got, and it is 100% single Ryzen DRAM Calculator stress test with no errors. I also can loop five minutes in Cinebench. :h34r-smi
> 
> See in the Spoiler.
> 
> 
> 
> Spoiler


The tCWL you use as 14, has no effect - because you are running GDM Enabled
the tRDWR of 11 should be able to be lowered up to 8 with current timings or 9 as failsafe one
are these dual rank kits ?

tRFC could be 288-214-132 with current timings, but you need to lower remain timings else you'll overshoot
The next safe one was 336-250-154
Of course, doublecheck everything with a SiSoftware Sandra Multi-Core Efficiency test, as well as the same result in Yuri's calculator

I wonder why you didn't increase PHY's memory training algorithm, the delay of it by setting a/A or 10 as value
8 as value should work tho, although 10/A is slower and so more accurate

What you can do, is push CAD_BUS to 30-20-20-24 or even up 40-20-20-24 which should allow you do drop ProcODT -1 and get better signal integrity out of it
Actually while i'm looking at it, this looks like 2x16 kits right ?, then go up to 48-20-20-24 as CAD_BUS / your max limit should be 96ohm there

Your SCL of 5 looks high still, SCL 4 should work after you lower tRDWR a bit, and then can use tWRRD as 4 or 2 
(but only if you lower tRDWR + SCL4)

Voltage vise:
Your VDDG voltage should be 50mV over VDDP, while vSOC should be >50mV VDDG
Aka try if VDDP 900 would work out for you, or even 913 
Else you might need to push VDDG IOD bit higher 
Lowering VDDP should be easier tho and possible if you can lower procODT 

Nothing else to optimise so far, just increase memory training time on PHY :thumb:
* well and at best please share a SiSoftware Sandra Multi-Core efficiency Test, to have comparable results before and after


----------



## KedarWolf

All credit goes to @GeneO who wrote this script. Rep him, not me, there is no way I could write this kind of thing myself, just good enough at math logic to edit it for our needs.

I just modified it to work with a 3950x CPU. Will make 3900X versions and other AMD CPU's when I can.

What is it is an AutoHotKey HCI MemTestPro script that automatically opens 32 instances of MemTest Pro, but allocates each of the 32 instances of it running to a separate logical CPU, or one instance allocated to each one of the 32 separate threads.

It uses a total of about 25.5M of memory., a 32GB version with a bit of room left for the O/S etc.

If you check on Windows task manager and click one instance and 'Go to details', then 'Set Affinity' you see each one is running on its own separate thread, that absolute best way to run HCI MemTest Pro!

It also spaces each instance evenly so you can see the error messages (or lack there-of) and progress.

The compiled AHK exe is included in the zip file. Also included the raw AHK file, if you want to play with it and make your own version for your CPU core count and memory amount. It's pretty much just math logic how to edit the script for other core counts and amounts of memory.

You need to install AutoHotKey to run the raw AHK file or compile it to an exe, but the exe is standalone, just put it in the folder with the latest version of MemTest Pro. If you have the latest version of MemTest, it works using the MTPclassic.exe. 

If you have an older version of MemTest Pro rename MTPclassic.exe to MemTestPro.exe in the AHK script or whatever your MemTest Pro exe is named. if you bought MemTest Pro less than a year ago you can email them for a free upgrade.


----------



## neurotix

Veii said:


> The tCWL you use as 14, has no effect - because you are running GDM Enabled
> the tRDWR of 11 should be able to be lowered up to 8 with current timings or 9 as failsafe one
> are these dual rank kits ?
> 
> tRFC could be 288-214-132 with current timings, but you need to lower remain timings else you'll overshoot
> The next safe one was 336-250-154
> Of course, doublecheck everything with a SiSoftware Sandra Multi-Core Efficiency test, as well as the same result in Yuri's calculator
> 
> I wonder why you didn't increase PHY's memory training algorithm, the delay of it by setting a/A or 10 as value
> 8 as value should work tho, although 10/A is slower and so more accurate
> 
> What you can do, is push CAD_BUS to 30-20-20-24 or even up 40-20-20-24 which should allow you do drop ProcODT -1 and get better signal integrity out of it
> Actually while i'm looking at it, this looks like 2x16 kits right ?, then go up to 48-20-20-24 as CAD_BUS / your max limit should be 96ohm there
> 
> Your SCL of 5 looks high still, SCL 4 should work after you lower tRDWR a bit, and then can use tWRRD as 4 or 2
> (but only if you lower tRDWR + SCL4)
> 
> Voltage vise:
> Your VDDG voltage should be 50mV over VDDP, while vSOC should be >50mV VDDG
> Aka try if VDDP 900 would work out for you, or even 913
> Else you might need to push VDDG IOD bit higher
> Lowering VDDP should be easier tho and possible if you can lower procODT
> 
> Nothing else to optimise so far, just increase memory training time on PHY :thumb:
> * well and at best please share a SiSoftware Sandra Multi-Core efficiency Test, to have comparable results before and after


Great advice, as usual. No disagreement from me.


----------



## KedarWolf

KedarWolf said:


> All credit goes to @GeneO who wrote this script. Rep him, not me, there is no way I could write this kind of thing myself, just good enough at math logic to edit it for our needs.
> 
> I just modified it to work with a 3950x CPU. Will make 3900X versions and other AMD CPU's when I can.
> 
> What is it is an AutoHotKey HCI MemTestPro script that automatically opens 32 instances of MemTest Pro, but allocates each of the 32 instances of it running to a separate logical CPU, or one instance allocated to each one of the 32 separate threads.
> 
> 
> 
> Spoiler
> 
> 
> 
> It uses a total of about 25.5M of memory., a 32GB version with a bit of room left for the O/S etc.
> 
> If you check on Windows task manager and click one instance and 'Go to details', then 'Set Affinity' you see each one is running on its own separate thread, that absolute best way to run HCI MemTest Pro!
> 
> It also spaces each instance evenly so you can see the error messages (or lack there-of) and progress.
> 
> The compiled AHK exe is included in the zip file. Also included the raw AHK file, if you want to play with it and make your own version for your CPU core count and memory amount. It's pretty much just math logic how to edit the script for other core counts and amounts of memory.
> 
> You need to install AutoHotKey to run the raw AHK file or compile it to an exe, but the exe is standalone, just put it in the folder with the latest version of MemTest Pro. If you have the latest version of MemTest, it works using the MTPclassic.exe.
> 
> If you have an older version of MemTest Pro rename MTPclassic.exe to MemTestPro.exe in the AHK script or whatever your MemTest Pro exe is named. if you bought MemTest Pro less than a year ago you can email them for a free upgrade.





KedarWolf said:


> Here are my daily driver BIOS settings screenshots for 24/7 use. Looping Cinebench on a single 360 RAD tops out at 70C.
> 
> I can do 4.45/4.4/4.35/4.3 at 1.325v LLC 2 but temps get a bit over 80C looping Cinibench and that troubles me.
> 
> The IMC on my 3950x is quite good, I'm very happy with what I got, and it is 100% single Ryzen DRAM Calculator stress test with no errors. I also can loop five minutes in Cinebench. :h34r-smi
> 
> See in the Spoiler.
> 
> 
> 
> Spoiler


Changed a couple of voltages and timings to get HCI MemTest Pro stable. Linpack Xtreme stable as well.

Final 24/7 BIOS screenshots below in Spoiler! :band:



Spoiler


----------



## nick name

Does anyone in here run a 2x16GB kit at 4400MHz stable?


----------



## KedarWolf

nick name said:


> Does anyone in here run a 2x16GB kit at 4400MHz stable?


Even if you can run 4400MHz your latency will take a huge hit. Best to go 3800MHz max for latency for everyday use and gaming, unless you are benchmarking, then you can try higher RAM speeds. :drunken:


----------



## gerardfraser

KedarWolf said:


> Even if you can run 4400MHz your latency will take a huge hit. Best to go 3800MHz max for latency for everyday use and gaming, unless you are benchmarking, then you can try higher RAM speeds. :drunken:


I would just like to say 3800MHz max for latency for everyday use and gaming is not the limit because I use higher and I am sure other's do also. You are correct when saying you take a latency hit when your MCLK/FCLK/UCLK are not synced 1:1:1.
From my testing you can get equal results from fine tuning your memory timings over faster or slower ram ,I have only tested up to 4200Mhz . I have not tested 4400Mhz mainly because I just did not want to test 4400Mhz. Just my opinion. 

Also from my testing 2933Mhz Ram with tuned timings are just as fast as any Ram on Ryzen. Spammed a couple videos if you want to see.I do not play at 1920x1080 but people just do not believe crap when using higher than 1920x1080 ,best thing it easily testable by most people if you can run 3800Mhz,just got to tune Ram timings.

AMD Ryzen Fabric Clock 1467Mhz (DDR4 2933Mhz) vs Fabric Clock 1933Mhz (DDR4 3866Mhz) Battlefield 5 and Grand Theft Auto V @1920x1080


Spoiler











AMD Ryzen Fabric Clock 1467Mhz (DDR4 2933Mhz) vs Fabric Clock 1933Mhz (DDR4 3866Mhz) Red Dead Redemption 2 and Sleeping Dogs


Spoiler


----------



## nick name

KedarWolf said:


> Even if you can run 4400MHz your latency will take a huge hit. Best to go 3800MHz max for latency for everyday use and gaming, unless you are benchmarking, then you can try higher RAM speeds. :drunken:


I understand that. And I'd still like to know if anyone here has a stable 4400MHz b-die setup.


----------



## hardwarelimits

gerardfraser said:


> I would just like to say 3800MHz max for latency for everyday use and gaming is not the limit because I use higher and I am sure other's do also. You are correct when saying you take a latency hit when your MCLK/FCLK/UCLK are not synced 1:1:1.
> From my testing you can get equal results from fine tuning your memory timings over faster or slower ram ,I have only tested up to 4200Mhz . I have not tested 4400Mhz mainly because I just did not want to test 4400Mhz. Just my opinion.
> 
> Also from my testing 2933Mhz Ram with tuned timings are just as fast as any Ram on Ryzen. Spammed a couple videos if you want to see.I do not play at 1920x1080 but people just do not believe crap when using higher than 1920x1080 ,best thing it easily testable by most people if you can run 3800Mhz,just got to tune Ram timings.
> 
> AMD Ryzen Fabric Clock 1467Mhz (DDR4 2933Mhz) vs Fabric Clock 1933Mhz (DDR4 3866Mhz) Battlefield 5 and Grand Theft Auto V @1920x1080
> 
> 
> Spoiler
> 
> 
> 
> https://www.youtube.com/watch?v=cav4_-g6nfI&t=0s
> 
> 
> 
> AMD Ryzen Fabric Clock 1467Mhz (DDR4 2933Mhz) vs Fabric Clock 1933Mhz (DDR4 3866Mhz) Red Dead Redemption 2 and Sleeping Dogs
> 
> 
> Spoiler
> 
> 
> 
> https://www.youtube.com/watch?v=aKx071DcKrs&t=0s


 Interesting. Do you use daily 4200 with 1933 flck ? Ill give a try on mines to see
Edit: Tried a bunch of settings, with all AUTO can't seem to post even playing with Cad bus and ProcODT .
Care to share your timings so we can use as guide?


----------



## Lobstar

This is my daily driver setup. Watercooling my Patriot 4400 kits. I haven't pushed for anything, just found something stable with all 4 sticks and just got my fclk figured out.


----------



## KedarWolf

Veii said:


> The tCWL you use as 14, has no effect - because you are running GDM Enabled
> the tRDWR of 11 should be able to be lowered up to 8 with current timings or 9 as failsafe one
> are these dual rank kits ?
> 
> 
> 
> Spoiler
> 
> 
> 
> tRFC could be 288-214-132 with current timings, but you need to lower remain timings else you'll overshoot
> The next safe one was 336-250-154
> Of course, doublecheck everything with a SiSoftware Sandra Multi-Core Efficiency test, as well as the same result in Yuri's calculator
> 
> I wonder why you didn't increase PHY's memory training algorithm, the delay of it by setting a/A or 10 as value
> 8 as value should work tho, although 10/A is slower and so more accurate
> 
> What you can do, is push CAD_BUS to 30-20-20-24 or even up 40-20-20-24 which should allow you do drop ProcODT -1 and get better signal integrity out of it
> Actually while i'm looking at it, this looks like 2x16 kits right ?, then go up to 48-20-20-24 as CAD_BUS / your max limit should be 96ohm there
> 
> Your SCL of 5 looks high still, SCL 4 should work after you lower tRDWR a bit, and then can use tWRRD as 4 or 2
> (but only if you lower tRDWR + SCL4)
> 
> Voltage vise:
> Your VDDG voltage should be 50mV over VDDP, while vSOC should be >50mV VDDG
> Aka try if VDDP 900 would work out for you, or even 913
> Else you might need to push VDDG IOD bit higher
> Lowering VDDP should be easier tho and possible if you can lower procODT
> 
> 
> Nothing else to optimise so far, just increase memory training time on PHY :thumb:
> * well and at best please share a SiSoftware Sandra Multi-Core efficiency Test, to have comparable results before and after


The only setting I'm not sure of is the below. Is that correct for PHY's memory training algorithm?

Edit: And do I need to set CAD BUS Timing Configuration?










*Never mind, figured it out with Ryzen RAM Calculator.

I'm proud of this score, but more tweaks in timings.
*


----------



## KedarWolf

KedarWolf said:


> The only setting I'm not sure of is the below. Is that correct for PHY's memory training algorithm?
> 
> Edit: And do I need to set CAD BUS Timing Configuration?





Spoiler



Old settings better than optimized ones in the multicore test but in AIDA64 cache and memory test, latency goes down by quite a bit.

The top picture is my old settings.





















Had to raise the SOC voltage, was unstable, would reboot looping Cinebench. Lower than 1.1v reboots looping Cinebench.

Got decent VDDG and VDDP though.

Tweaked some timings, passing RamTest, need to test HCI overnight. Getting decent multi-thread scores now. 










*Anything else to tweak? Bios screens again in Spoiler.*

If I disable Gear Down Mode, won't boot. 



Spoiler


----------



## TwilightRavens

KedarWolf said:


> Spoiler
> 
> 
> 
> Old settings better than optimized ones in the multicore test but in AIDA64 cache and memory test, latency goes down by quite a bit.
> 
> The top picture is my old settings.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Had to raise the SOC voltage, was unstable, would reboot looping Cinebench. Lower than 1.1v reboots looping Cinebench.
> 
> Got decent VDDG and VDDP though.
> 
> Tweaked some timings, passing RamTest, need to test HCI overnight. Getting decent multi-thread scores now.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> *Anything else to tweak? Bios screens again in Spoiler.*
> 
> If I disable Gear Down Mode, won't boot.
> 
> 
> 
> Spoiler



I’ve heard from some people that’s its really hard to get a dual rank kit running with geardown mode disabled without clocking down to something like 2933-3200, I had zero luck on it with my dual rank b-die running 3733MHz geardown mode on.


----------



## pegadroid

i build amd ryzen for three day.
Ryzen 9 3900x
Asus Strix x570 e
Corsair cmr32gx4m4c3466c16 4.31 (samsung b-die) 4 x8gb
--------------------------------------------------------------------
i can't run my ram with xmp profile (auto or manual set)
and now i try to run 3200 mhz with 16-18-18-18-36 1T 1.350v run HCI covered min 400% an max 900% and no have error
any sugestion for better performance?


----------



## TwilightRavens

pegadroid said:


> i build amd ryzen for three day.
> Ryzen 9 3900x
> Asus Strix x570 e
> Corsair cmr32gx4m4c3466c16 4.31 (samsung b-die) 4 x8gb
> --------------------------------------------------------------------
> i can't run my ram with xmp profile (auto or manual set)
> and now i try to run 3200 mhz with 16-18-18-18-36 1T 1.350v run HCI covered min 400% an max 900% and no have error
> any sugestion for better performance?



A lot of X570 boards have a daisy chain memory configuration, which basically means it’ll only really clock well with two sticks and not 4, if you need 32GB it might be better to look at a 2 x 16GB rather than 4 x 8GB. This kit, while pricey is b-die: https://www.newegg.com/product/N82E16820232860?m_ver=1


----------



## rastaviper

TwilightRavens said:


> I’ve heard from some people that’s its really hard to get a dual rank kit running with geardown mode disabled without clocking down to something like 2933-3200, I had zero luck on it with my dual rank b-die running 3733MHz geardown mode on.


All my RAM ocing is with GDM disabled at 3733 without any issues.
Any proper bdie should run fine as long as the correct turning is in place.

Are u using the Ryzen Ram Calculator properly?
Or else u won't find the best setup for your RAM.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## KedarWolf

I just ASS-UMED my timings couldn't go any lower at 3800MHz, but so far this is testing RamTest stable. :thumb:


I think the IMC on this chip is golden, and the MSI Prestige X570 Creation has incredible memory overclocking capabilities. :band:

I'm using 2x16GB Trident Z Neo CL16 (16-16-16-36) 3600MHz RAM running at 3800MHz 15-15-15-30 1T as seen below.


----------



## Himo5

Lobstar said:


> This is my daily driver setup. Watercooling my Patriot 4400 kits. I haven't pushed for anything, just found something stable with all 4 sticks and just got my fclk figured out.



Having got two sets of 2x8Gb Patriot Viper Steel DDR4 4400MHz/CL19 I've been trying to find out how best to set them up in a Ryzen 3000 installation, seeing as none of the DOCP settings I might attempt in BIOS would be likely to work, especially for 32Gb of RAM made up from two 16Gb kits.
A week ago I found an entry in the Statistics link from the Membench page of the DRAM Calculator showing how someone had got at least 16Gb of this Patriot kit to 3800MHz at CL16.So I fed these settings into BIOS, leaving everything else set to Auto and it trained in POST enough to pass Memtest86 and boots safely into W10 producing the following profile in the ASUS X370-F BIOS (Version 5220):


----------



## TwilightRavens

rastaviper said:


> All my RAM ocing is with GDM disabled at 3733 without any issues.
> Any proper bdie should run fine as long as the correct turning is in place.
> 
> Are u using the Ryzen Ram Calculator properly?
> Or else u won't find the best setup for your RAM.
> 
> Sent from my ONEPLUS A6003 using Tapatalk



Not using the DRAM calculator because i’m not going to go past 1.35v, I don’t intend to, nor do I want to, I know how to use it and have used it in the past with my wife’s 2600X and 3200 b die kit. I’m just seeing what this kit is capable of with 1.35v with minimal effort. I’m not trying to get that last 0.001% of performance out of it because for my personal use case don’t need to.

Edit: I did fire it up for lulz just to see what it would tell me as far as frequency/timings would go for dr b die at 1.35v and its saying pretty much 3733MHz 16-17-17-38, but i’ve managed manually without much effort 16-16-16-30 so far, but this also v1.62 so it is an older version.

Edit 2: Okay well i’ll try and see what I can do with a limit of 1.45v because why not, that’s relatively safe for 24/7 long term usage right? Longevity is important because I don’t really get that much money for pc upgrades so i try to make a system last 3-5 years and the last thing i wanna risk is RAM going bad before then.


----------



## rares495

@Himo5 The 4400 C19 viper steel kits should do 3800 C14 or C15. Check this:


----------



## Himo5

I tried Buildzoid's timings, 14-16-13-27-40-300, and they posted at 3666MHz but I couldn't get them through Memtest86 above 3533MHz.


----------



## rares495

Himo5 said:


> I tried Buildzoid's timings, 14-16-13-27-40-300, and they posted at 3666MHz but I couldn't get them through Memtest86 above 3533MHz.


You did set the DRAM Voltage to 1.5, right?


----------



## rares495

TwilightRavens said:


> Not using the DRAM calculator because i’m not going to go past 1.35v, I don’t intend to, nor do I want to, I know how to use it and have used it in the past with my wife’s 2600X and 3200 b die kit. I’m just seeing what this kit is capable of with 1.35v with minimal effort. I’m not trying to get that last 0.001% of performance out of it because for my personal use case don’t need to.
> 
> Edit: I did fire it up for lulz just to see what it would tell me as far as frequency/timings would go for dr b die at 1.35v and its saying pretty much 3733MHz 16-17-17-38, but i’ve managed manually without much effort 16-16-16-30 so far, but this also v1.62 so it is an older version.
> 
> Edit 2: Okay well i’ll try and see what I can do with a limit of 1.45v because why not, that’s relatively safe for 24/7 long term usage right? Longevity is important because I don’t really get that much money for pc upgrades so i try to make a system last 3-5 years and the last thing i wanna risk is RAM going bad before then.


Fake news! DDR4 overclocking at 1.35V is not a thing. Anything under 1.6V is 100% safe, though, assuming that your case airflow isn't total garbage. For long term use, you wouldn't want to go over 1.5V, plus there's also frequency-voltage scaling to consider. B-die likes 1.5V, but is also very temperature sensitive, so airflow is important.


----------



## TwilightRavens

rares495 said:


> Fake news! DDR4 overclocking at 1.35V is not a thing. Anything under 1.6V is 100% safe, though, assuming that your case airflow isn't total garbage. For long term use, you wouldn't want to go over 1.5V, plus there's also frequency-voltage scaling to consider. B-die likes 1.5V, but is also very temperature sensitive, so airflow is important.



Yeah I have pretty decent airflow in my case (the front fan controller is nice, thinking about putting the temp sensor onthe RAM itself and have a fan automated by temp on it.) I’m actually shocked i’ve managed to get what I have out of it at 1.35v but i’ll give 1.45v a shot and see what it does. 

Also would it be worth trying to stabilize fclk 1900MHz for DDR4 3800MHz or should I stick with 1867/3733 and just slam the timings as low as possible?


----------



## Himo5

rares495 said:


> You did set the DRAM Voltage to 1.5, right?



Yes, but I couldn't get these to POST at 3733Mhz, which was where Buildzoid stopped. I was very glad to find a setting at 3800MHz which worked.


----------



## rares495

Himo5 said:


> Yes, but I couldn't get these to POST at 3733Mhz, which was where Buildzoid stopped. I was very glad to find a setting at 3800MHz which worked.


Ah...first gen Ryzen. You should be very happy with anything over 3200mhz tbh.


----------



## rares495

TwilightRavens said:


> Yeah I have pretty decent airflow in my case (the front fan controller is nice, thinking about putting the temp sensor onthe RAM itself and have a fan automated by temp on it.) I’m actually shocked i’ve managed to get what I have out of it at 1.35v but i’ll give 1.45v a shot and see what it does.
> 
> Also would it be worth trying to stabilize fclk 1900MHz for DDR4 3800MHz or should I stick with 1867/3733 and just slam the timings as low as possible?


Don't spend much time on FCLK. Most chips cannot do 1900. 3733/1867 is pretty good as well.


----------



## TwilightRavens

rares495 said:


> Don't spend much time on FCLK.


Yeah that's what i've heard, I'm shocked mine is stable at 1867 with just 1.1v on SoC


----------



## Lobstar

Himo5 said:


> ::Your words::


I'm not sure if this helps you out at all but this is what I've got going. I'm sure I can tighten this up but it's been really happy and so far only one error in memtest with lots of coverage.

Edit: I just noticed I have some messed up settings like clkdrvstr and ODT. Should be 24 and 60 respectively.


----------



## rastaviper

TwilightRavens said:


> Yeah that's what i've heard, I'm shocked mine is stable at 1867 with just 1.1v on SoC


What do u mean by "just"?
The majority is using around 1.1v at SOC, if not less..nothing special about that.

Also, if your RAM can be stable at 1900 1:1, then I would suggest that you check your Aida results with different combinations of speed [emoji362] timings, in order to figure out which setup delivers the best performance.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## 2600ryzen

rares495 said:


> Fake news! DDR4 overclocking at 1.35V is not a thing. Anything under 1.6V is 100% safe, though, assuming that your case airflow isn't total garbage. For long term use, you wouldn't want to go over 1.5V, plus there's also frequency-voltage scaling to consider. B-die likes 1.5V, but is also very temperature sensitive, so airflow is important.





Maybe for Micron and Samsung 1.6v is ok but I've heard of Hynix degrading between 1.45v-1.5v a few times.


----------



## Veii

^ memory IC voltage depends not only on manufacture but also on die size
Example:
Micron Rev E 16nm, you wouldn't want to over 1.45v
Micron Rev D/E 18nm, you wouldn't want to go over 1.46v, but 1.5v can work for 24/7 
Samsung B-Die 20nm, 1.5v is fine for 24/7 it likes to move around 1.46-1.48v / low grade b-dies hate anything over 1.48v
Hynix MFR 25nm, your max would be 1.62v for 24/7 usage, while only over 1.48v they start to scale up
Hynix AFR/CFR up to manufacturing date, it's 1.48v but again dependend on manufacturing node

This counts for every IC
Micron and Samsung ones scale a bit different
Samsung ones can run up to 1.9v while with normal cooling it's 1.72v - IF you use maxmem and limit size (architectural issue)
Micron ones don't have this kind of issue, but they have another issue with negative voltage scaling 
Some rev E kits are 16nm, some are 18nm, some are 12nm 

For 12nm, i personally wouldn't go over 1.42v/1.43v as daily settings
* while again Samsung C-dies under lower node scale differently 
there is no "works for all" voltage, it might be ~1.46v for Samsung IC, ~1.42v for Micron IC, ~1.50v for Hynix IC (because they are on a big nm node)
+/- 30-60mV depend on the current available node size


----------



## 2600ryzen

Veii said:


> ^ memory IC voltage depends not only on manufacture but also on die size
> Example:
> Micron Rev E 16nm, you wouldn't want to over 1.45v
> Micron Rev D/E 18nm, you wouldn't want to go over 1.46v, but 1.5v can work for 24/7
> Samsung B-Die 20nm, 1.5v is fine for 24/7 it likes to move around 1.46-1.48v / low grade b-dies hate anything over 1.48v
> Hynix MFR 25nm, your max would be 1.62v for 24/7 usage, while only over 1.48v they start to scale up
> Hynix AFR/CFR up to manufacturing date, it's 1.48v but again dependend on manufacturing node
> 
> This counts for every IC
> Micron and Samsung ones scale a bit different
> Samsung ones can run up to 1.9v while with normal cooling it's 1.72v - IF you use maxmem and limit size (architectural issue)
> Micron ones don't have this kind of issue, but they have another issue with negative voltage scaling
> Some rev E kits are 16nm, some are 18nm, some are 12nm
> 
> For 12nm, i personally wouldn't go over 1.42v/1.43v as daily settings
> * while again Samsung C-dies under lower node scale differently
> there is no "works for all" voltage, it might be ~1.46v for Samsung IC, ~1.42v for Micron IC, ~1.50v for Hynix IC (because they are on a big nm node)
> +/- 30-60mV depend on the current available node size





I have spectek 25nm 'a die' do you think up to 1.6v would be safe 24/7 on that? Makes sense that max safe voltage would reduce on the smaller process nodes.


----------



## Veii

2600ryzen said:


> I have spectek 25nm 'a die' do you think up to 1.6v would be safe 24/7 on that? Makes sense that max safe voltage would reduce on the smaller process nodes.


Spectek and hynix are not much far of each other 
1.58v should be fine , you should see tCL scaling after 1.52v
If yes, go up to 1.55 but cool them actively
Spectek are still a mystery today, but either tCL & tRP should scale, or only tCL
Try~

Keep in mind you need more resistance when you use higher voltages
more CAD_BUS resistance and more procODT
48-24-24-24 for example can be an entry point on >1.5v
maybe even 48-24-30-24
After 1.580v every 10mV will make a big difference between stable and not stable
Focus on resistance optimization before doing 20-30mV voltage jumps after 1.55 
~ keep us up to date with results :thumb:

* Oh also on A1 pcb, don't overdo it
Consider that traces are shorter and you might need more resistance instead of more voltage
A2 is more voltage, less resistance
A0 don't mind it, go all in , it's a bad pcb to begin with


----------



## 2600ryzen

Cheers. On my kit I've only gone to max 1.52v so far for [email protected], I need about 1.48v to go [email protected] with Procodt of 68ohms. Only noticed that voltage scales with tcl/tcwl/and maybe trtp on my kit.


----------



## KedarWolf

KedarWolf said:


> Don't know what else to tweak. With all you peeps help, I really got the memory dialed in. :h34r-smi
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> BIOS screenshots below in Spoiler. Gear Down Enabled with these settings faster in AIDA64 than my Gear Down Disabled settings I had. :drunken:
> 
> 
> 
> Spoiler


I took a nap, ran HCI MemTest Pro with the allocated threads Memtest Pro script I posted a few days ago. :h34r-smi

I'm gonna let it run overnight though, get to maybe 800%. 

RAM temps are good for 1.5v but I have a 3000 RPM RAM fan sitting above the DIMMs. :thumb:

3950x, 2x16GB Trident Z Neo 16-16-16-36 3600MHz at the below, Gear Down Mode enabled. :bruce:










This is faster in AIDA64 than my stable Gear Down Mode disabled settings. :band:


----------



## TwilightRavens

rastaviper said:


> What do u mean by "just"?
> The majority is using around 1.1v at SOC, if not less..nothing special about that.


Ah for some reason I thought some other people required 1.15v on SoC for that roughly, I may try 1900 fclk once I get my 1080 ti oc dialed in.


----------



## 2600ryzen

KedarWolf said:


>



Timings look good, maybe the scl timings could go lower they have a big effect on bandwidth. Are you using 2t when you disable GDM? that gives me worse scores for everything except latency on my kit. 1t should be faster than GDM though.


----------



## KedarWolf

2600ryzen said:


> Timings look good, maybe the scl timings could go lower they have a big effect on bandwidth. Are you using 2t when you disable GDM? that gives me worse scores for everything except latency on my kit. 1t should be faster than GDM though.


I can only do 15-15-15-30 2T with GDM disabled and my AIDA64 scores are a lot worse.


----------



## KedarWolf

2600ryzen said:


> Timings look good, maybe the scl timings could go lower they have a big effect on bandwidth. Are you using 2t when you disable GDM? that gives me worse scores for everything except latency on my kit. 1t should be faster than GDM though.


I lower SCLs to 2, now getting well over 58000 in write and 64800 in copy and 62.2ns latency. 

Karthu RamTest stable as well at those timings, tonight, going to let HCI run overnight.


----------



## gooshpitz

Pretty happy with the results. I just can't make it work at 3600MHz.


----------



## rares495

gooshpitz said:


> Pretty happy with the results. I just can't make it work at 3600MHz.


It's B-die man. Set the DRAM voltage to 1.5V and SOC to 1.1V, then try again.

3466 is already pretty good for Zen+ though. You might not be able to go higher due to the weak IMC.


----------



## gooshpitz

Too much extra voltage, even then i think i would also need to loosen timings. This is fine. Any1 know why is voltage spiking to 1,41? HWinfo reading error?


----------



## rares495

gooshpitz said:


> Too much extra voltage, even then i think i would also need to loosen timings. This is fine. Any1 know why is voltage spiking to 1,41? HWinfo reading error?


Well then don't complain if you're not willing to do what is necessary.


----------



## rares495

KedarWolf said:


> I lower SCLs to 2, now getting well over 58000 in write and 64800 in copy and 62.2ns latency.
> 
> Karthu RamTest stable as well at those timings, tonight, going to let HCI run overnight.


We make a great team, you and I. Keep pushing, baby! (that's what she said)


----------



## nick name

gooshpitz said:


> Too much extra voltage, even then i think i would also need to loosen timings. This is fine. Any1 know why is voltage spiking to 1,41? HWinfo reading error?


Set voltage to 1.47V on DRAM. Also, I didn't need more than 1.0V on SOC with my 2700X on my CH7. 

These were my daily stable timings. These two settings were left on Auto: tRDWR and tWRRD. Actually, I almost always leave those two on Auto.


----------



## gooshpitz

What's your latency?


----------



## nick name

gooshpitz said:


> What's your latency?


It was in the 58s.


----------



## KedarWolf

rares495 said:


> We make a great team, you and I. Keep pushing, baby! (that's what she said)


You might be able to get your tRDWR as low as 8, 10 is a low as I can go but some get 9 or 8.


----------



## nick name

KedarWolf said:


> You might be able to get your tRDWR as low as 8, 10 is a low as I can go but some get 9 or 8.


I haven't seen you post any test results. Do you test for stability?


----------



## Veii

rares495 said:


> We make a great team, you and I. Keep pushing, baby! (that's what she said)
> 
> 
> KedarWolf said:
> 
> 
> 
> You might be able to get your tRDWR as low as 8, 10 is a low as I can go but some get 9 or 8.
Click to expand...

tRDWR 8 / tWRRD 4 should work with his SCL 2
Might even be able to do 7/4 , or 7/2
Optimal tRFC would be 252 for this settings
But you can potentially lower tRC down to 40 (else 41 if it has issues) 
40 combined with tRFC 240-178-110 , that should work well with your tRTP 6
EDIT: tRC 41, goes together with tRFC 246-183-112 

Too low tRFC doesn't give anything
Too low timings also make no difference, even when they are stable (if they aren't in perfect sync)
Don't forget to start crosstesting with SiSoftware Sandra , Multi Core efficiency test (detailed result)
Results under the hood are not what they seen as virtual timings
After all timings are virtual placeholders of real world delays - they can be as low as your kits like them
But having them not in sync, will show performance penalties - simply because boards do autocorrect timings and add delay, even when your virtual timings say otherwise 
Great results tho rares495 :thumb:
* just focus on latency readouts, which are not Aida64 ones


----------



## Veii

gooshpitz said:


> Pretty happy with the results. I just can't make it work at 3600MHz.
> 
> 
> 
> rares495 said:
> 
> 
> 
> It's B-die man. Set the DRAM voltage to 1.5V and SOC to 1.1V, then try again.
> 
> 3466 is already pretty good for Zen+ though. You might not be able to go higher due to the weak IMC.
> 
> 
> gooshpitz said:
> 
> 
> 
> Too much extra voltage, even then i think i would also need to loosen timings. This is fine. Any1 know why is voltage spiking to 1,41? HWinfo reading error?
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

Downgrade Bios to 1003ABBA (Version 2801) for anything Zen related, 1004B doesn't behave well
1.0.0.4C/1.0.0.5 only would be fine for it 
In the bios, enable Cinebench Gentle Performance Bias 
Put SOC voltage to 1.05 with LLC drop, soo you gain between 1.025 min and 1.048v max
(12nm IMC loves 1.05v for 3600MT/s, but less is better)

on 1003ABBA , change CAD_BUS to 24-20-20-24, keep your RTT values, remove AddCMDSetup CAD_BUS Delay = put it to 0,0,0
Use tRFC 294-218-134 for now till you have every other setting stable
Later you can try 252-187-115 with 1.46v

For the future then, check in thaiphoon burner what kind of PCB layout you have at which B-die nm node
Bottom left PCB Revision and Version

After all that is stable, lower procODT to 48ohm and keep same vDIMM voltage with vSOC around the 1.03 mark
2700X has XFR and a FIT module
it will boost up to 1.48v, don't worry too much
In the future if you want to use PBO with set limits (not open to infinity)
use an offset to keep it under 1.48v, as it will boost to 1.5/1.52 up to applied clock 
PBO on 2700X can boost up to 4.3 AC and 4.5 Single Core, if you let it
Example:


Spoiler












^ you will need to focus on taming that then, but that's a future thing after RAM is set


3600 MT/s would be identical timings except
tRFC to 294-218-134 stable & 252-187-115 lowest
14-14-15-14-28 SLC 3 @ 3600 should run with A1 PCBs , if you didn't lose IC lotttery
Might need bit higher timings on A0 PCB or 1.48v on A2 PCB and RTT_PARK disabled (for A0 layout)
^ depends rly on PCB layout and bit on IC quality , soo please doublecheck 
* don't attempt 3600 without fixing written parts above and having stable 48ohm procODT
EDIT:
** Don't use too excessive vSOC (focus on your Signal Integrity)
Like tRFC depends on MT/S, vSOC depends on MemFreq.
3734 MT/s should be easy on zen+ (3800 as absolute limit),
Zen 1's "easy" limit was 3467 MT/s, (3600 as absolute limit)


----------



## KedarWolf

nick name said:


> I haven't seen you post any test results. Do you test for stability?


I meant to run Karhu ramTest 1.1.0.0 a few hours when I napped today, but I opened it forgot to start it. I'm running it now for an hour while on Twitch, but going to run HCI MemTest Pro with the allocated threads script I shared overnight with these settings.

HCI is my go-to test. 

So far when I do run Karthu, no errors. I just prefer to be gaming and stuff during the day, not running stress tests, but I can run Karthu with Twitch open if I leave a bit of memory free.


----------



## nick name

KedarWolf said:


> I meant to run Karhu ramTest 1.1.0.0 a few hours when I napped today, but I opened it forgot to start it. I'm running it now for an hour while on Twitch, but going to run HCI MemTest overnight with these settings.
> 
> HCI is my go-to test.
> 
> So far when I do run Karthu, no errors. I just prefer to be gaming and stuff during the day, not running stress tests, but I can run Karthu with Twitch open if I leave a bit of memory free.


Run Karhu overnight with CPU Cache set to Enabled under the Advanced tab. You don't want to run it that way while using anything else though as the cache testing slows everything down.


----------



## nick name

@Veii Can you give me some guidance. I can't seem to run anything lower than tRFC 310 and maintain an error free Karhu test. And I can run tRTP at 8 with tRFC of 310 for 9 hours error free.


----------



## rares495

Went even lower and left Karhu over night. Cache option not enabled, though. I might run HCI as well.
@Veii This is on 1.0.04B btw.


----------



## Veii

rares495 said:


> Went even lower and left Karhu over night. Cache option not enabled, though. I might run HCI as well.
> 
> @Veii This is on 1.0.04B btw.


Yes tRDWR is far to high, you add excessive latency - but i mean tRFC is too high too, so it's fine
Seems like you aren't overshooting 126.316ns (240 tRFC)
Your new lowest rec tRFC is 234-174-107 now - if it doesn't post, it's because of tRDWR/tWRRD combination, being too high
Let me drop this tiny Calculator here too, to assist you 
https://docs.google.com/spreadsheets/d/1A7G97QOL0dNMwJZa9SYEq2RElJ5T6Hcx9WdReTsnIWw/
Full Calculator is yet WIP, but this should be useful enough already :guitar:
Continue the great work :thumb:

EDIT:
Might i ask, what CAD_BUS & procODT settings you use ?


----------



## rares495

Veii said:


> Yes tRDWR is far to high, you add excessive latency - but i mean tRFC is too high too, so it's fine
> Seems like you aren't overshooting 126.316ns (240 tRFC)
> Your new lowest rec tRFC is 234-174-107 now - if it doesn't post, it's because of tRDWR/tWRRD combination, being too high
> Let me drop this tiny Calculator here too, to assist you
> https://docs.google.com/spreadsheets/d/1A7G97QOL0dNMwJZa9SYEq2RElJ5T6Hcx9WdReTsnIWw/
> Full Calculator is yet WIP, but this should be useful enough already :guitar:
> Continue the great work :thumb:
> 
> EDIT:
> Might i ask, what CAD_BUS & procODT settings you use ?


CAD & ODT are all on auto, believe it or not. Not sure how to monitor them as RTC doesn't work on Zen 2.

Ran your Sandra just now but no clue what it means.

Thanks for the calculator!


----------



## Veii

rares495 said:


> CAD & ODT are all on auto, believe it or not. Not sure how to monitor them as RTC doesn't work on Zen 2.
> 
> Ran your Sandra just now but no clue what it means.
> 
> Thanks for the calculator!


Nearly 90 GB/s is very solid 
@polkfan here some settings  ~ scroll two quotes up
What is import is exactly that. Latency Between CCX (biggest one if you scroll down the list), InterCore Bandwith, InnerCore Latency
Let me crosslink another thread, soo i don't have to type too much
https://www.overclock.net/forum/11-...chi-overclocking-thread-736.html#post28381858
You look for exactly this graph you showed, and you should focus on the delays in the export on the list
We can see, you lose a bit of Inter-Core Latency compared to Polkfan his results, but that's just the older AGESA and older SMU

Oh also at the bottom, filter to local results only
Red is your latest result
Might want to attach that full latency log for comparison
But the graph does show it very well

EDIT:
You monitor them sadly only with Ryzen Master, but opening it once does bug out CPPC
(needs to be deactivated, and re-activated in the bios after RM wipe)
Or you don't monitor them and try know your voltages 
(you can read a bit the last 2 pages on our Taichi Thread, especially the "starting preset of voltages")
Your goal would be, lowering procODT to 28ohm down - and VDDG potentially under the 1v range (950mV at best)
while keeping VDDP at 900mV at best 
(they do scale all three together, here another chunk to read about it)
Get voltages down, clean/increase good signal integrity and later try to push FCLK beyond 1900
* should have the tRFC calculator, the timings don't rly change only tRFC might do - timings are virtual values scaling from MCLK down
like visible here:


Spoiler




















Tiny Sneakpeak ~ just again needs couple more weeks of work


----------



## rares495

@Veii tRFC 234 is not stable at all and can't post with lower than 10 tRDWR. Sadly I do not have the time to play around anymore right now but will continue to push tonight.

Current settings:

VDDP 0.900V
VDDGs 0.950V
procODT & all that stuff = Auto (didn't even have to scroll so far down in the bios for these results - might have to do it to go lower)


----------



## KedarWolf

nick name said:


> Run Karhu overnight with CPU Cache set to Enabled under the Advanced tab. You don't want to run it that way while using anything else though as the cache testing slows everything down.


I prefer HCI MemTest Pro with the threads allocated script to run it I've shared.

I find it'll find errors Karhu can miss.

Here's an hour of Karhu. Gonna run HCI 7 hours overnight plus several hours while at work tomorrow.


----------



## Veii

rares495 said:


> @Veii tRFC 234 is not stable at all and can't post with lower than 10 tRDWR. Sadly I do not have the time to play around anymore right now but will continue to push tonight.
> 
> Current settings:
> 
> VDDP 0.900V
> VDDGs 0.950V
> procODT & all that stuff = Auto (didn't even have to scroll so far down in the bios for these results - might have to do it to go lower)


34.4Ω and 28Ω is your procODT range 
(lower = better, but works together with CAD_BUS, vCore & vSOC,
less voltage, less resistance needed=cleaner signal integrity=higher potential FCLK)
lowest vSOC = 1.0v (minimum 50mV higher than VDDG, optimally 75mV higher)
CAD_BUS depends on AGESA
on one hand 24-24-24-24 does work
on the other hand 30-20-20-24 does work better
Even 40-20-20-24 should work well for you on higher voltages
(higher voltage, higher resistance, higher drivestrengh)


Veii said:


> Translated from @cm87 very helpful RAM OC PDF Guide posted on Hardwareluxx
> About the CAD-Values:
> • CLKDrvStr - Helpful gainst Post Problems with low ProcODT (recommendation less Ω)
> • AddrCmdDrvStr - Does influence stability quite a bit (recommendation 30 or higher - find it out single handed)
> • CsOdtDrvStr - It's quite similar to how RTT_NOM works (try out what runs better - to be known, higher values increase the chance of POST issues)
> • CKEDrvStr - against waking up from sleep issues (more is better, but does increase thermals by quite a bit)
Click to expand...

Yes tRFC lowest mentioned is for perfect sync, something likely still overshoots 
tRDWR goes together with tWRRD in steps 
Here it was re-replained and rephrased, hopefully understandable this time :ninja:
EDIT: i think i found the issue
Try tWR 13, or 9
~ tho you overshoot somewhere with delay to not having it post :ninja:


----------



## rares495

Veii said:


> 34.4Ω and 28Ω is your procODT range
> (lower = better, but works together with CAD_BUS, vCore & vSOC / less voltage, less resistance needed=cleaner signal integrity)
> lowest vSOC = 1.0v (minimum 50mV higher than VDDG, optimally 75mV higher)
> CAD_BUS depends on AGESA
> on one hand 24-24-24-24 does work
> on the other hand 30-20-20-24 does work better
> Even 40-20-20-24 should work well for you on higher voltages
> Yes tRFC lowest mentioned is for perfect sync, something likely still overshoots
> tRDWR goes together with tWRRD in steps
> Here it was re-replained and rephrased, hopefully understandable this time :ninja:


Thanks. I'll give it a try tonight.


----------



## KedarWolf

Veii said:


> 34.4Ω and 28Ω is your procODT range
> (lower = better, but works together with CAD_BUS, vCore & vSOC / less voltage, less resistance needed=cleaner signal integrity)
> lowest vSOC = 1.0v (minimum 50mV higher than VDDG, optimally 75mV higher)
> CAD_BUS depends on AGESA
> on one hand 24-24-24-24 does work
> on the other hand 30-20-20-24 does work better
> Even 40-20-20-24 should work well for you on higher voltages
> Yes tRFC lowest mentioned is for perfect sync, something likely still overshoots
> tRDWR goes together with tWRRD in steps
> Here it was re-replained and rephrased, hopefully understandable this time :ninja:


I read at higher voltages too low proODT can hurt signal integrity. Why I keep it proODT at 43.6 and 40-20-20-24 CAD_BUS as someone suggested.

I have tried lower proODT though and never really had issues, as low as 34.4.

Run my RAM at 1.5v. VDDGs at .950, VDDP at .900v.

Should I try to run it at 34.4 again and how do I test if I have issues?

I'm so far stable at 43.6 etc. Gonna run HCI for a dozen hours or more overnight and while I'm at work. :h34r-smi


----------



## Veii

KedarWolf said:


> I read at higher voltages too low proODT can hurt signal integrity. Why I keep it proODT at 43.6 and 40-20-20-24 CAD_BUS as someone suggested.
> 
> I have tried lower proODT though and never really had issues, as low as 34.4.
> 
> Run my RAM at 1.5v. VDDGs at .950, VDDP at .900v.
> 
> Should I try to run it at 34.4 again and how do I test if I have issues?
> 
> I'm so far stable at 43.6 etc. Gonna run HCI for a dozen hours or more overnight and while I'm at work. :h34r-smi
> 
> 
> 
> Spoiler


The way memory OC on ryzen as general works is:
The higher procODT is, the worse signal integrity gets and playroom is less
(after 60-68/69 ohm , you can't push FCLK at all, on every ryzen)
But high procODT is required if you push high vSOC through it, or have high density kits 
(which includes higher procODT to start with, SR 28-40ohm, DR 48-60ohm)
procODT range changes with AGESA and 1003ABBA rec lowest was 34.4 or sometimes 32, current rec is 28ohm with 24-20-20-24 but you can push the first value higher
24<->48-20-20-24 for SR, 60<->120-20-20-24 for DR or higher amount of kits with big capacity
^ source 1usmus, as always 

My findings are, that you need to up CAD_BUS resistance if you go high with vDIMM too
Else yes you are right, high vSOC if needed, can have negative effects on the sillicon if procODT is too low
although, who would push 1.3v SOC with 20ohm proc 
Sometimes board default to 1.2v , which defaults to 60ohm proc , and of course 1.1v VDDP&VDDG 
defaulting to low vSOC is only possible with VDDP & VDDG are lower, because of the range 
you can't lower vSOC under VDDG voltage, same as you can't lower VDDG under VDDP voltage


----------



## Tobiman

Currently running G-SKILL DDR4-3000 CL14. It's B-die but it seems to be of a lower quality. I'm getting errors shortly after starting the memtest. Have no idea where to start looking. I was going to try the SAFE preset since it doesn't change much but I haven't gotten around to doing that yet. 

I'm using 1USmus's FAST profile for dual rank with timings pictured below. I noticed the timings somehow changed, magically, on their own, when I ran the AIDA memory benchmark again. Doesn't seem to have cost me any performance but wierd. Dram voltage is at the recommended 1.35. Do I need to turn it up to get passed these errors? Thanks!


----------



## rares495

Tobiman said:


> Currently running G-SKILL DDR4-3000 CL14. It's B-die but it seems to be of a lower quality. I'm getting errors shortly after starting the memtest. Have no idea where to start looking. I was going to try the SAFE preset since it doesn't change much but I haven't gotten around to doing that yet.
> 
> I'm using 1USmus's FAST profile for dual rank with timings pictured below. I noticed the timings somehow changed, magically, on their own, when I ran the AIDA memory benchmark again. Doesn't seem to have cost me any performance but wierd. Dram voltage is at the recommended 1.35. Do I need to turn it up to get passed these errors? Thanks!


tRC should be equal to tRAS + tRP => 16-16-16(tRP)-36(tRAS)-52(tRC)

tFAW should be 4x tRRDS/tRRDL => 4/4 & 16


----------



## Tobiman

rares495 said:


> tRC should be equal to tRAS + tRP => 16-16-16(tRP)-36(tRAS)-52(tRC)
> 
> tFAW should be 4x tRRDS/tRRDL => 4/4 & 16


I fixed it. Still getting errors in membench though.


----------



## rares495

Tobiman said:


> I fixed it. Still getting errors in membench though.


You literally didn't apply a single setting I posted lol.


----------



## Tobiman

rares495 said:


> You literally didn't apply a single setting I posted lol.


I'll do so now.


----------



## 2600ryzen

Tobiman said:


> I'll do so now.



Up the voltage to 1.45v first, then you can tune it down once you're stable.


----------



## KedarWolf

rares495 said:


> tRC should be equal to tRAS + tRP => 16-16-16(tRP)-36(tRAS)-52(tRC)
> 
> tFAW should be 4x tRRDS/tRRDL => 4/4 & 16


Is there a website that has ALL the timing rules for the Ryzen 3*** series?

I know I had a website for Intel.


----------



## KedarWolf

nick name said:


> I haven't seen you post any test results. Do you test for stability?


Goin to let it run at least another 10 hours or so while I'm at work. 

Been going 5.5 hours as is.


----------



## nick name

@Veii Can you give me some guidance. I can't seem to run anything lower than tRFC 310 and maintain an error free Karhu test. And I can run tRTP at 8 with tRFC of 310 for 9 hours error free.


----------



## Veii

Tobiman said:


> I fixed it. Still getting errors in membench though.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> rares495 said:
> 
> 
> 
> You literally didn't apply a single setting I posted lol.
Click to expand...

tRRDS to tFAW doesn't have to be *4
It can be *4 for tightest, *5 for common, *6 for failsafe, 6*6 36 tFAW, nothing wrong
but what IS WRONG, are his tRDWR & tWRRD settings
Before when he/she had SLC 4, 16-16-16-25 , 8/4 did work, although 8/1 would work
4*4 16 tRCDRD , 8*2 16 tRCDWR, covering it perfectly
BUT - now he has SLC 5 inside
tRDWR isn't bothered by that, can still use tRDWR 8 or 9
But if he uses 8 and his kits require this delay bump - tWRRD should be 3=3*5 15 , 4*5=20 which overshoots tRCDRD 

Not always will tRRDS *4 work, especially since this looks like dual rank kits
Although to your defense rares, @Tobiman didn't attach any Thaiphoon burner report showing IC size in nm, rank density and showing PCB layout if (A0,A1,A2 or B0,B1,B2)
Soo we are working here blind 



KedarWolf said:


> Is there a website that has ALL the timing rules for the Ryzen 3*** series?


Ryzen has the same settings since gen 1, same rules only ranges differ and CAD_BUS,RTT,procODT differs between bios and ICs
This was my guide of explaining, although i did post it one page back on here 
https://www.overclock.net/forum/11-...chi-overclocking-thread-705.html#post28246564
and this is the page you might be looking for, but it doesn't cover the rules
https://reddit.com/r/overclocking/comments/ahs5a2/demystifying_memory_overclocking_on_ryzen_oc/
After all, there are nearly no public rules - simply as they are many ways of calculation
Only first 3 timings change freely without rulesets: tCL, tRCD, tRP
They differ between ICs and depend on more than just "delay"

Don't forget, 3rd gen does autocorrect timings,
A passed set of timings ≠ a good set of timings
Boards do autoinject delay since gen 1 , tiny bit but you'll notice it on SiSandra results


----------



## rares495

@Veii I could have just quoted you, of course. Perhaps I'll do that next time.

Can you explain the SLC thing?


----------



## Veii

nick name said:


> @Veii Can you give me some guidance. I can't seem to run anything lower than tRFC 310 and maintain an error free Karhu test. And I can run tRTP at 8 with tRFC of 310 for 9 hours error free.


14-14-16-14-30-54
tRFC 378-281-173 or 324-241-148
SCL 3
tRDWR 8
tWRRD 4
tRTP is 9 or 6 (for 324 tRFC)
1.46vDimm ~ till we get a thaiphoon burner report from you

used tRDRD / tWRWR SD & DD values of 4,4-6,6 don't always deliver better performance
same as tRDDS, tRDDL 4,4 are not always better than 4,6
You can use 4,5 if you want
As you used GDM , every odd value will be even , you are running 14-14-16 in reality

The best you could do is either get GDM away, or lower tRC-2 at the end to tRC 52,
which would make 312-232-143 (164.22ns) with tRTP of 6,8,12 as option to select
that turns tWR as 12 or 8

Here some more rules:


----------



## Veii

rares495 said:


> @Veii I could have just quoted you, of course. Perhaps I'll do that next time.
> 
> Can you explain the SLC thing?


SCL as alone SCL, not 100%
it has more connections to it - but ultimately it depends on PCB layout (trace layout) and current sensing unit (voltage+free voltage after tRP precacharge)
And it can be used for tWRRD calculation - if you need on odd values like tRCD 17 to calculate tRDWR
(that would be 9 which has remain unused delay, or 8 which needs then a bit of latency added from tWRRD, to compensate - but would give a faster bandwidth boost)
I often used it for CL14 flat - while taking tRDWR 6,3 instead of 7,1 / 3 because SLC was 2, but it would've worked borderline on SCL 3 too as 3*4 12 instead of 14 ~ key is to not overshoot

SCL is not only PCB related but also frequency related
this is a tiny illustration of some of the ranges, although it's a flawed one without any delay used








SCL is strange on it's own - same as both SD DD values are not fully clear how to calculate
I need to get the exact cycle times correct of how memory behaves
That way get "world clock" delay, and so let me adjust perfect tRFC and automate every timing at the end (then i'll release the full manual calculator)
But all that is still wip for couple more weeks  , later when i get this result finally - i will automate everything and work with "timing efficiency" not only "high bandwidth and calculated timing latency" 
* we know, 3467CL12 is faster than 3600C14 

EDIT:
The only advice i can give is 
In order to lower SCL, you need everything lower - including low tRFC
too high tRFC and low SCL won't be stable


----------



## nick name

Veii said:


> 14-14-16-14-30-54
> tRFC 378-281-173 or 324-241-148
> SCL 3
> tRDWR 8
> tWRRD 4
> tRTP is 9 or 6 (for 324 tRFC)
> 1.46vDimm ~ till we get a thaiphoon burner report from you
> 
> used tRDRD / tWRWR SD & DD values of 4,4-6,6 don't always deliver better performance
> same as tRDDS, tRDDL 4,4 are not always better than 4,6
> You can use 4,5 if you want
> As you used GDM , every odd value will be even , you are running 14-14-16 in reality
> 
> The best you could do is either get GDM away, or lower tRC-2 at the end to tRC 52,
> which would make 312-232-143 (164.22ns) with tRTP of 6,8,12 as option to select
> that turns tWR as 12 or 8
> 
> Here some more rules:


Sorry, I'm running a G.Skill 3600C15 b-die kit.


----------



## Veii

nick name said:


> Sorry, I'm running a G.Skill 3600C15 b-die kit.


Thaiphoon burner readout please 
Even from the same model number, you can have two different PCB revisions
and different b-die nm sizes


----------



## rares495

Veii said:


> Thaiphoon burner readout please
> Even from the same model number, you can have two different PCB revisions
> and different b-die nm sizes


Seems that my PCBs are A1.


----------



## nick name

Veii said:


> Thaiphoon burner readout please
> Even from the same model number, you can have two different PCB revisions
> and different b-die nm sizes


Sorry I thought the 3600C15 TridentZ were all A1.


----------



## nick name

rares495 said:


> Seems that my PCBs are A1.


Hmmmm yours say A1 10 layers. Mine are 8 layers.


----------



## Veii

Yep it's different 
i have A1 Viper 4000 kits
nearly everyone who gets them has A0 Vipers 
It's random, but it's important  @nick name , be more brave with voltage, near 1.48  @rares495 rather go down with voltage and work with CAD_BUS a bit 
Both can peak 1.5, but over that degradation starts to get closely dangerous - you need to up all resistance values if you go over 1.5v


----------



## nick name

Veii said:


> Yep it's different
> i have A1 Viper 4000 kits
> nearly everyone who gets them has A0 Vipers
> It's random, but it's important
> @nick name , be more brave with voltage, near 1.48
> @rares495 rather go down with voltage and work with CAD_BUS a bit
> Both can peak 1.5, but over that degradation starts to get closely dangerous - you need to up all resistance values if you go over 1.5v


I'm running 1.5V and what I've done is gone up to 36.9Ohms for ODT as I had been trying to go lower to find stability. That seems promising with the short test runs I've done.


----------



## Tobiman

@Veii. Here are my current stable timings and clocks. I started getting even more errors after using the timings I was advised to on this thread, by other people. Reverted back to SAFE 1usmus timings and it's been fine so far, even passing the easy membench test without any errors like before. I haven't run the full memtest which used to pop-up errors earlier.


----------



## rastaviper

Here is my *3200 GTZ bdie.*
It's perfectly stable at* 3733 16-15-15* for daily use and heavy gaming, but it can't do 3800 16-15-15 or 3733 14-14-14.
The best I have seen for use in benchmarks is 3733 15-14-14 with voltage up to 1.46v

Anyone has any suggestions?


----------



## nick name

nick name said:


> I'm running 1.5V and what I've done is gone up to 36.9Ohms for ODT as I had been trying to go lower to find stability. That seems promising with the short test runs I've done.


That didn't prove to be stable overnight.


----------



## rares495

nick name said:


> That didn't prove to be stable overnight.


Try to use my timings. Check previous posts in this thread for the image.


----------



## nick name

rares495 said:


> Went even lower and left Karhu over night. Cache option not enabled, though. I might run HCI as well.
> 
> @Veii This is on 1.0.04B btw.





rares495 said:


> Try to use my timings. Check previous posts in this thread for the image.


Unfortunately, those timings are tighter than what failed so I don't have any hope it would work. My problem (I'm assuming) is tRFC as I can't seem to get anything overnight stable below 310. I do test the CPU Cache though so perhaps that's why your overnight test was stable?


----------



## KedarWolf

nick name said:


> That didn't prove to be stable overnight.


34.3, not stable overnight, but when I

At 1.5v I tried 34.3, not stable overnight, but when I went back to 43.6, so far stable HCI MemTest at 300%.

So what I read might be right, too low procODT at higher RAM voltages seems to hurt signal integrity.


----------



## rares495

nick name said:


> Unfortunately, those timings are tighter than what failed so I don't have any hope it would work. My problem (I'm assuming) is tRFC as I can't seem to get anything overnight stable below 310. I do test the CPU Cache though so perhaps that's why your overnight test was stable?


Use those timings with gear down mode enabled, procODT 36.9, CAD_bus all 24, tRFC 312, DRAM voltage of 1.52V(yes, it's safe 24/7), SOC voltage of 1.1V, VDDP 0.900V, VDDGs 0.950V


----------



## nick name

rares495 said:


> Use those timings with gear down mode enabled, procODT 36.9, CAD_bus all 24, tRFC 312, DRAM voltage of 1.52V(yes, it's safe 24/7), SOC voltage of 1.1V, VDDP 0.900V, VDDGs 0.950V


I already know I can pass with tRFC at 312. My goal is getting tRFC to below 300.


----------



## rares495

nick name said:


> I already know I can pass with tRFC at 312. My goal is getting tRFC to below 300.


That should not be your goal. You can set:

-tRFC 312 for tRC 39

-tRFC 336 for tRC 42

And these will be more than adequate. You probably won't get as good results as me due to the different PCBs but you shouldn't be that far off.


----------



## nick name

rares495 said:


> That should not be your goal. You can set:
> 
> -tRFC 312 for tRC 39
> 
> -tRFC 336 for tRC 42
> 
> And these will be more than adequate. You probably won't get as good results as me due to the different PCBs but you shouldn't be that far off.


And why shouldn't it be my goal?


----------



## KedarWolf

I said this in another thread, but if you've been messing around in your BIOS, but are now getting errors in Karhu or HCI MemTest that you never got before using your previously stable settings do this.

Save stable BIOS settings to a USB, shut down your PC, turn PSU power switch off for 30 seconds. Then turn it back on, press BIOS reset button, start PC, load saved stable BIOS settings, should fix the problem.


----------



## rares495

nick name said:


> And why shouldn't it be my goal?


 @Veii can answer that.


----------



## KedarWolf

rares495 said:


> That should not be your goal. You can set:
> 
> -tRFC 312 for tRC 39
> 
> -tRFC 336 for tRC 42
> 
> And these will be more than adequate. You probably won't get as good results as me due to the different PCBs but you shouldn't be that far off.


239 tRFC seems to be working for me.


----------



## rares495

KedarWolf said:


> 239 tRFC seems to be working for me.


Cool but for tRC 42 the lowest you need is 252.


----------



## Veii

KedarWolf said:


> 34.3, not stable overnight, but when I
> At 1.5v I tried 34.3, not stable overnight, but when I went back to 43.6, so far stable HCI MemTest at 300%.
> 
> So what I read might be right, too low procODT at higher RAM voltages seems to hurt signal integrity.
> 
> 
> rares495 said:
> 
> 
> 
> Use those timings with gear down mode enabled, procODT 36.9, CAD_bus all 24, tRFC 312, DRAM voltage of 1.52V(yes, it's safe 24/7), SOC voltage of 1.1V, VDDP 0.900V, VDDGs 0.950V
Click to expand...

No GDM timings are usually faster, but "usually faster" is speculation - you all should test Infinity Fabric Bandwith and Latency with SiSandra
"Stable" is great to know, but it doesn't help any results spending that much time to test it stable for nothing

Signal integrity does better up when you have lower resistance, not higher
Lower procODT helps to have higher potential FCLK
Desync is still an issue with current AGESA , but not for long 
One of the limits is already lifted
Example of polkfans results:
Bad procODT and wrong CAD_BUS 


Spoiler






























Detailed results
BAD (auto proc, auto CAD)
https://docs.google.com/document/d/12fnvc1X_mID_J_QIT1-WyeVXR9ei9Fe2G7jeMEp28gE/edit
Good (finetuned proc & CAD - same timings)
https://docs.google.com/document/d/1P2pg9vZQLs5GwR4ibgbLrPb_09Hf3bTEMdvNu4qbw3U/edit
Old AGESA results:
https://docs.google.com/document/d/1cRwUAeLvAMLzmhxnlfM6uNbpQ2Xee8y3FuiSJBeqvPc/edit
Better illustrative picture wip

As you can see, 20ns difference between furthest core inside CCX towards furthest core into another CCX
Now down to 66ns instead of usually near 90ish, or non finetuned voltages 77ns


KedarWolf said:


> 239 tRFC seems to be working for me.
> 
> 
> Spoiler


Low tRFC doesn't do anything except desync after time, it does help a bit by triggering a pre-charge stacking method
Which there is no guide for 
1usmus used this on his timings - which compared to my method, he spend dozzens of hours testing many ram kits to figure out well performing timings with SiSandra
His presets are working often better than user manual lowered ones, because it triggers exactly this cycle stacking method which allows (even against the rulesets) to use lower timings than should possibly work

But again, lower timings don't help much when real world performance suffers by having them not in clean sync
Normal user wouldn't notice it, because boards do add up hidden latency to balance delays
Simply as not only for example 3733= 3733,333333334MT/s which ultimately results in up to 8 decimal values just to calculate internal delay
Example:








^ soo because of this inconsistency starting back to not only Spread Spectrum by the CPUs but also inconsistent fixed frequency multiplier by the IMC
This simply means, every board always adds latency - since early as gen 1 ryzen AM4 boards
While 3rd gen does autocorrect by itself ontop of that
They can pass and they will pass stresstests, but real life performance can suffer by as much as 3-4GB/s bandwidth with differences of 10ns inter-core bandwith
^ Which means, test it - always test your timings, visual is one thing, stresstesting is also one thing
But it's like lying to yourself 

A sidenote about tRFC
The calculator shared works with math in ns, same as the DRAM calculator
But tRFC2/4 is often rounded down and still flawed by +/- 1 value between his and my versions of calculator
^ and to be honest, both of our versions are wrong by +1/-1

tRFC does scale in Steps
+/- 16 for 1 cycle
8 = 1/2 cycle
4 = 1/4 cycle
2 = 1/8th cycle

You can try to go between -4 & -16 as steps, from the result
But you have to calculate the rest via DRAM calculator 
I haven't found yet his exact method after what range you cause the cycle stacking method, 
or force precharge before the cell is empty
But accurate tRFC does play an important role in this


----------



## KedarWolf

rares495 said:


> Cool but for tRC 42 the lowest you need is 252.


How do you calculate that?


----------



## rares495

KedarWolf said:


> How do you calculate that?


With God Veii's calculator.


----------



## rares495

Veii said:


> No GDM timings are usually faster, but "usually faster" is speculation - you all should test Infinity Fabric Bandwith and Latency with SiSandra
> "Stable" is great to know, but it doesn't help any results spending that much time to test it stable for nothing
> 
> Signal integrity does better up when you have lower resistance, not higher
> Lower procODT helps to have higher potential FCLK
> Desync is still an issue with current AGESA , but not for long
> One of the limits is already lifted
> Example of polkfans results:
> Bad procODT and wrong CAD_BUS
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Detailed results
> BAD (auto proc, auto CAD)
> https://docs.google.com/document/d/12fnvc1X_mID_J_QIT1-WyeVXR9ei9Fe2G7jeMEp28gE/edit
> Good (finetuned proc & CAD - same timings)
> https://docs.google.com/document/d/1P2pg9vZQLs5GwR4ibgbLrPb_09Hf3bTEMdvNu4qbw3U/edit
> Old AGESA results:
> https://docs.google.com/document/d/1cRwUAeLvAMLzmhxnlfM6uNbpQ2Xee8y3FuiSJBeqvPc/edit
> Better illustrative picture wip
> 
> As you can see, 20ns difference between furthest core inside CCX towards furthest core into another CCX
> Now down to 66ns instead of usually near 90ish, or non finetuned voltages 77ns
> 
> Low tRFC doesn't do anything except desync after time, it does help a bit by triggering a pre-charge stacking method
> Which there is no guide for
> 1usmus used this on his timings - which compared to my method, he spend dozzens of hours testing many ram kits to figure out well performing timings with SiSandra
> His presets are working often better than user manual lowered ones, because it triggers exactly this cycle stacking method which allows (even against the rulesets) to use lower timings than should possibly work
> 
> But again, lower timings don't help much when real world performance suffers by having them not in clean sync
> Normal user wouldn't notice it, because boards do add up hidden latency to balance delays
> Simply as not only for example 3733= 3733,333333334MT/s which ultimately results in up to 8 decimal values just to calculate internal delay
> Example:
> 
> 
> 
> 
> 
> 
> 
> 
> ^ soo because of this inconsistency starting back to not only Spread Spectrum by the CPUs but also inconsistent fixed frequency multiplier by the IMC
> This simply means, every board always adds latency - since early as gen 1 ryzen AM4 boards
> While 3rd gen does autocorrect by itself ontop of that
> They can pass and they will pass stresstests, but real life performance can suffer by as much as 3-4GB/s bandwidth with differences of 10ns inter-core bandwith
> ^ Which means, test it - always test your timings, visual is one thing, stresstesting is also one thing
> But it's like lying to yourself
> 
> A sidenote about tRFC
> The calculator shared works with math in ns, same as the DRAM calculator
> But tRFC2/4 is often rounded down and still flawed by +/- 1 value between his and my versions of calculator
> ^ and to be honest, both of our versions are wrong by +1/-1
> 
> tRFC does scale in Steps
> +/- 16 for 1 cycle
> 8 = 1/2 cycle
> 4 = 1/4 cycle
> 2 = 1/8th cycle
> 
> You can try to go between -4 & -16 as steps, from the result
> But you have to calculate the rest via DRAM calculator
> I haven't found yet his exact method after what range you cause the cycle stacking method,
> or force precharge before the cell is empty
> But accurate tRFC does play an important role in this



Found out that my Auto procODT is 36.9ohm and my CAD_bus is all 24. I guess I can try to lower the ODT and push for 1933 or more.


----------



## Veii

rares495 said:


> Found out that my Auto procODT is 36.9ohm and my CAD_bus is all 24. I guess I can try to lower the ODT and push for 1933 or more.


procODT and CAD_BUS go hand in hand
This range is for 1004B


Veii said:


> Starting Preset:
> 
> ProcODT 28–36.9Ω SR / 36.9–53.3Ω DR
> CAD_BUS 24-20-20-24 / CadBusClkDrvStrengh (first value) can be pushed to 30-60Ω - DR 60-120Ω
> CLD0_VDDP 900mV
> CLD0_VDDG 950mV
> VDDG CCD 950mV
> VDDG IOD 950mV


I think i've posted this once tho
24-24-24-24 works well for 1003ABBA , same as minimum procODT of 34
But 24-20-20-24 works better for 1004B and higher with minimum proc of 28ohm, sometimes 30ohm if you can select it

Of course CadBusClkDrvStrengh scales with used IC, and so procODT scales up with higher CAD_BUS values
But best signal integrity you get by lowering everything
keep in mind vSOC is 50-75mV higher than VDDG, and VDDG is 50-75mV higher than VDDP
You start with 900mV CLDO_VDDP, soo minimum VDDG is 950 - which results in minimum vSOC of 1.0v or 1.025v 
The minimum ruleset remains even auto predicted from the board - but you can go also higher
There is no need to increase VDDG just because you have high vSOC - but high vSOC will have negative results of "wasted voltage"

Keep in mind, CAD_BUS and proc voltage change up to AGESA and vary with kits
VDDG CCD and IOD can stay identical, where CCD can be pushed for multi CCD or IOD can be pushed if you use 3rd gen on a bad PCB board (for better ram OC)


----------



## rastaviper

rastaviper said:


> Here is my *3200 GTZ bdie.*
> 
> It's perfectly stable at* 3733 16-15-15* for daily use and heavy gaming, but it can't do 3800 16-15-15 or 3733 14-14-14.
> 
> The best I have seen for use in benchmarks is 3733 15-14-14 with voltage up to 1.46v
> 
> 
> 
> Anyone has any suggestions?


Any special reason that everyone just ignored my message?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Dollar

Sisoftware sandra multi-core test has always given me really weird results or maybe I just don't understand how to read them. In terms of bandwidth I get the best score with..... optimized defaults 2133 super loose 2t auto timings.3700x - x370 c6h - 4x8GB 

For example:

2133 optimized defaults = 97.337 GB/s - 60.7ns 
3600 dram calc safe v1 = 95.407 GB/s - 48.1ns


?????

@Veii what am I doing wrong here?


----------



## rares495

rastaviper said:


> Any special reason that everyone just ignored my message?
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Can your CPU do 1900MHz FCLK?


----------



## rares495

Veii said:


> procODT and CAD_BUS go hand in hand
> This range is for 1004B
> 
> I think i've posted this once tho
> 24-24-24-24 works well for 1003ABBA , same as minimum procODT of 34
> But 24-20-20-24 works better for 1004B and higher with minimum proc of 28ohm, sometimes 30ohm if you can select it
> 
> Of course CadBusClkDrvStrengh scales with used IC, and so procODT scales up with higher CAD_BUS values
> But best signal integrity you get by lowering everything
> keep in mind vSOC is 50-75mV higher than VDDG, and VDDG is 50-75mV higher than VDDP
> You start with 900mV CLDO_VDDP, soo minimum VDDG is 950 - which results in minimum vSOC of 1.0v or 1.025v
> The minimum ruleset remains even auto predicted from the board - but you can go also higher
> There is no need to increase VDDG just because you have high vSOC - but high vSOC will have negative results of "wasted voltage"
> 
> Keep in mind, CAD_BUS and proc voltage change up to AGESA and vary with kits
> VDDG CCD and IOD can stay identical, where CCD can be pushed for multi CCD or IOD can be pushed if you use 3rd gen on a bad PCB board (for better ram OC)


Tried various configurations without any luck. I'm 99% certain that this CPU cannot do 1933MHz.


----------



## Veii

rastaviper said:


> Here is my *3200 GTZ bdie.*
> It's perfectly stable at* 3733 16-15-15* for daily use and heavy gaming, but it can't do 3800 16-15-15 or 3733 14-14-14.
> The best I have seen for use in benchmarks is 3733 15-14-14 with voltage up to 1.46v
> 
> 
> 
> 
> 
> 
> 
> 
> Anyone has any suggestions?
> 
> 
> rastaviper said:
> 
> 
> 
> Any special reason that everyone just ignored my message?
Click to expand...

People are busy no bad intention 
tRAS would be optimally 31 here, going up and down has negative effects (-1 works but not rec to use it yet)
tFAW is a bit lower than it should be (you likely just can use it because of your A1 layout, although not rec)
Best explanation to give is this post:
https://www.overclock.net/forum/180...tras-34-seems-tras-34-win-9.html#post28383868

lowering SCL should be your main focus at start
tRFC is low, but SCL is a bit too high for it - that's a step for another test after you fix some parts
there is no need for tWRRD delay when you already overshoot tRCDRD 15 with your current set tRDWR 8 (8*2=16) can be just 1
your tRTP doesn't work with tRFC at all, nor does tWR work with tRFC at all
if this timings are stable, it's purely only because the board adds latency and also ryzen 3rd gen autocorrects a bit

Try this:








CL15 is soo awkward to work with
If you have post issues or random errors try 
tRFC 338 and tWR 16
if you still face errors
tRAS 31, tRC 46, tRFC 345-257-158, tWR 12, tRTP 8


----------



## KedarWolf

rares495 said:


> With God Veii's calculator.


I'm not sure how to actually calculate my custom settings in the DRAM Calculator For Ryzen.

Is that what you use? It's not allowing me to input my custom timings.

That being said, if the below is stable, what can I set tRFC at? I get a tiny bit higher latency in AIDA64 with 252 instead of 239 but a bit lower in Sandra.


----------



## Veii

KedarWolf said:


> I'm not sure how to actually calculate my custom settings in the DRAM Calculator For Ryzen.
> 
> Is that what you use? It's not allowing me to input my custom timings.
> 
> That being said, if the below is stable, what can I set tRFC at? I get a tiny bit higher latency in AIDA64 with 252 instead of 239 but a bit lower in Sandra.


I've posted it here i think twice already, maybe it got lost 
This is what he uses
https://docs.google.com/spreadsheets/d/1A7G97QOL0dNMwJZa9SYEq2RElJ5T6Hcx9WdReTsnIWw
If too many people use it, just duplicate it offline for yourself

for *6 values copy the whole ns in DRAM calculator,
3733=3734 in reality
On Sisandra, look not only at InterCore bandwith and Intercore latency combined
But scroll down to the furthest 1ccx core->2nd ccx core latencys 
It should let you export this chart too for personal comparison

Try to get that "maximum delay" down , to have game FPS increases
Else InterCore-Bandwith and combined Inter-Core latency does focus on IPC improvement
SiSandra report at the bottom should also have "effective thread performance" as a value


----------



## KedarWolf

Found this, some basic guidelines like tRFC values.

https://www.techpowerup.com/review/amd-ryzen-memory-tweaking-overclocking-guide/8.html


----------



## KedarWolf

rares495 said:


> We make a great team, you and I. Keep pushing, baby! (that's what she said)


Try lowering tRP as well.


----------



## rares495

KedarWolf said:


> Try lowering tRP as well.


I might. Need to figure out the whole tRDWR thing first.


----------



## Veii

rares495 said:


> I might. Need to figure out the whole tRDWR thing first.


Need a guide or two ? 
I've spread it already quite often - it's not hard, or can't you understand it ?


----------



## Veii

KedarWolf said:


> Try lowering tRP as well.


Try lowering tWTRS to 2, tWTRL 8
If it passes, you can later try some magic on tRAS - but it will surely fail if the rest is a bit unstable
Congrats to 240 tRFC with tRTP 6 :thumbsups :clock:

EDIT: 
"Magic on tRAS" (this is experimental and will fail if any unused latency exists)
you can get tRAS to 27 if you use 
tRCD+tWR+tBL (4 or 2)

You can lower tWR by using
tRRDS+tWTRS

Effectively making tWR 8, having to use tRTP 8 for now
soo it would be
15+8+4=27 instead of 29 as minimum tRAS
This pushes 2 "wasted into delay" steps on tRC (but are needed to keep tRFC 240 stable)
(+2 tRC is used for stability for example)
having extra waiting-for-action delay between tRAS and tRC is fine, but tRAS needs to be perfect without delay

You'd need to have success with tWTRS of 2, 
in order to have even more range in tWR
That would make tRAS as 23-24 which should in theory let you drop tRCD WR -1, because the rest is soo tight
That then should allow you finally tRC to drop further and allowing tRFC of 222 or even 208 to work
240 is about the hardcap-limit so far without changing anything
More range would be given by dropping to tCL13 but odd values area b*ch to calculate 
* keep in mind tWR NEEDS to be an EVEN value 
** "Magic on tRAS" will also 100% fail if you have any desync between your tRFC and (tRTP,tWR,tRC)

EDIT 2:
I forgot one thing, you are rocking dual rank
Get that BankGroupSwap ALT away and enable BankGroupSwap from the CBS
Both are in the AMD CBS menu, should be near DF or UMC 
* keep in mind, CBS is b*chy too,
once you enter the memory timing settings by accident, every mem timing will convert into HEX
if that happen, you pretty much can CMOS reset and trow away that profile if it was saved
as it will continue to overwrite the main menu and only accept HEX values - but it will give you a warning before accessing this sub-category 

EDIT 3:
I've attached the guide towards that "magic trick" 
But it's 158 pages long, happy reading :wubsmiley


----------



## KedarWolf

Veii said:


> Try lowering tWTRS to 2, tWTRL 8
> If it passes, you can later try some magic on tRAS - but it will surely fail if the rest is a bit unstable
> Congrats to 240 tRFC with tRTP 6 :thumbsups :clock:
> 
> EDIT:
> "Magic on tRAS" (this is experimental and will fail if any unused latency exists)
> you can get tRAS to 27 if you use
> tRCD+tWR+tBL (4 or 2)
> 
> You can lower tWR by using
> tRRDS+tWTRS
> 
> Effectively making tWR 8, having to use tRTP 8 for now
> soo it would be
> 15+8+4=27 instead of 29 as minimum tRAS
> This pushes 2 "wasted into delay" steps on tRC (but are needed to keep tRFC 240 stable)
> (+2 tRC is used for stability for example)
> having extra waiting-for-action delay between tRAS and tRC is fine, but tRAS needs to be perfect without delay
> 
> You'd need to have success with tWTRS of 2,
> in order to have even more range in tWR
> That would make tRAS as 23-24 which should in theory let you drop tRCD WR -1, because the rest is soo tight
> That then should allow you finally tRC to drop further and allowing tRFC of 222 or even 208 to work
> 240 is about the hardcap-limit so far without changing anything
> More range would be given by dropping to tCL13 but odd values area b*ch to calculate
> * keep in mind tWR NEEDS to be an EVEN value
> ** "Magic on tRAS" will also 100% fail if you have any desync between your tRFC and (tRTP,tWR,tRC)
> 
> EDIT 2:
> I forgot one thing, you are rocking dual rank
> Get that BankGroupSwap ALT away and enable BankGroupSwap from the CBS
> Both are in the AMD CBS menu, should be near DF or UMC
> * keep in mind, CBS is b*chy too,
> once you enter the memory timing settings by accident, every mem timing will convert into HEX
> if that happen, you pretty much can CMOS reset and trow away that profile if it was saved
> as it will continue to overwrite the main menu and only accept HEX values - but it will give you a warning before accessing this sub-category
> 
> EDIT 3:
> I've attached the guide towards that "magic trick"
> But it's 158 pages long, happy reading :wubsmiley


Had to go back to this. The other wasn't passing HCI MemTest Pro.


----------



## KedarWolf

Veii said:


> Try lowering tWTRS to 2, tWTRL 8
> 
> 
> Spoiler
> 
> 
> 
> If it passes, you can later try some magic on tRAS - but it will surely fail if the rest is a bit unstable
> Congrats to 240 tRFC with tRTP 6 :thumbsups :clock:
> 
> EDIT:
> "Magic on tRAS" (this is experimental and will fail if any unused latency exists)
> you can get tRAS to 27 if you use
> tRCD+tWR+tBL (4 or 2)
> 
> You can lower tWR by using
> tRRDS+tWTRS
> 
> Effectively making tWR 8, having to use tRTP 8 for now
> soo it would be
> 15+8+4=27 instead of 29 as minimum tRAS
> This pushes 2 "wasted into delay" steps on tRC (but are needed to keep tRFC 240 stable)
> (+2 tRC is used for stability for example)
> having extra waiting-for-action delay between tRAS and tRC is fine, but tRAS needs to be perfect without delay
> 
> You'd need to have success with tWTRS of 2,
> in order to have even more range in tWR
> That would make tRAS as 23-24 which should in theory let you drop tRCD WR -1, because the rest is soo tight
> That then should allow you finally tRC to drop further and allowing tRFC of 222 or even 208 to work
> 240 is about the hardcap-limit so far without changing anything
> More range would be given by dropping to tCL13 but odd values area b*ch to calculate
> * keep in mind tWR NEEDS to be an EVEN value
> ** "Magic on tRAS" will also 100% fail if you have any desync between your tRFC and (tRTP,tWR,tRC)
> 
> My MSI X570 Creation doesn't have a CBS menu.
> 
> EDIT 2:
> I forgot one thing, you are rocking dual rank
> Get that BankGroupSwap ALT away and enable BankGroupSwap from the CBS
> Both are in the AMD CBS menu, should be near DF or UMC
> * keep in mind, CBS is b*chy too,
> once you enter the memory timing settings by accident, every mem timing will convert into HEX
> if that happen, you pretty much can CMOS reset and trow away that profile if it was saved
> as it will continue to overwrite the main menu and only accept HEX values - but it will give you a warning before accessing this sub-category
> 
> EDIT 3:
> I've attached the guide towards that "magic trick"
> But it's 158 pages long, happy reading :wubsmiley


Had to go back to this. The other wasn't passing HCI MemTest Pro. 










And I don't have a CBS Menu on my MSI X570 Creation, I do have the below though.


----------



## Veii

aand you entered that evil bugged CBS subsection
Hopefully you didn't safe and boot after you entered this menu 
else you're f**iretrucked 

rip tRFC 240  
well at least you can slowly work your tRDWR down as 10 is still too much
don't forget, GDM enabled pushes all odd values to even values
tRP 13 = 14 in reality and tRAS 29 = 30 in reality


----------



## KedarWolf

Veii said:


> aand you entered that evil bugged CBS subsection
> Hopefully you didn't safe and boot after you entered this menu
> else you're f**iretrucked
> 
> rip tRFC 240
> well at least you can slowly work your tRDWR down as 10 is still too much
> don't forget, GDM enabled pushes all odd values to even values
> tRP 13 = 14 in reality and tRAS 29 = 30 in reality


Fails to post lower than 10.


----------



## kyo2020

My config with 3800 mhz cl 16 , in Asus x370 crosshair hero vi.


----------



## rares495

Veii said:


> Need a guide or two ?
> I've spread it already quite often - it's not hard, or can't you understand it ?


Nobody can understand your logic when it comes to DRAM. Except maybe 1usmus... Explaining further could go a long way.

And maybe write in a different way. Something like this:

"Set X to Y because it needs to be equal to W+Z"

instead of

"try X+Y because you need to keep in mind W+Z and S when looking at V but V is also affected by G+H when dealing with low F and also changing E and D"

Also, we could use your full calculator even if it's in beta. Mind sharing it?


----------



## rares495

Veii said:


> Try lowering tWTRS to 2, tWTRL 8
> If it passes, you can later try some magic on tRAS - but it will surely fail if the rest is a bit unstable
> Congrats to 240 tRFC with tRTP 6 :thumbsups :clock:
> 
> EDIT:
> "Magic on tRAS" (this is experimental and will fail if any unused latency exists)
> you can get tRAS to 27 if you use
> tRCD+tWR+tBL (4 or 2)
> 
> You can lower tWR by using
> tRRDS+tWTRS
> 
> Effectively making tWR 8, having to use tRTP 8 for now
> soo it would be
> 15+8+4=27 instead of 29 as minimum tRAS
> This pushes 2 "wasted into delay" steps on tRC (but are needed to keep tRFC 240 stable)
> (+2 tRC is used for stability for example)
> having extra waiting-for-action delay between tRAS and tRC is fine, but tRAS needs to be perfect without delay
> 
> You'd need to have success with tWTRS of 2,
> in order to have even more range in tWR
> That would make tRAS as 23-24 which should in theory let you drop tRCD WR -1, because the rest is soo tight
> That then should allow you finally tRC to drop further and allowing tRFC of 222 or even 208 to work
> 240 is about the hardcap-limit so far without changing anything
> More range would be given by dropping to tCL13 but odd values area b*ch to calculate
> * keep in mind tWR NEEDS to be an EVEN value
> ** "Magic on tRAS" will also 100% fail if you have any desync between your tRFC and (tRTP,tWR,tRC)
> 
> EDIT 2:
> I forgot one thing, you are rocking dual rank
> Get that BankGroupSwap ALT away and enable BankGroupSwap from the CBS
> Both are in the AMD CBS menu, should be near DF or UMC
> * keep in mind, CBS is b*chy too,
> once you enter the memory timing settings by accident, every mem timing will convert into HEX
> if that happen, you pretty much can CMOS reset and trow away that profile if it was saved
> as it will continue to overwrite the main menu and only accept HEX values - but it will give you a warning before accessing this sub-category
> 
> EDIT 3:
> I've attached the guide towards that "magic trick"
> But it's 158 pages long, happy reading :wubsmiley


This plan looked great on paper except cannot post with tWTRS of 2 but it did post with 3. I cannot physically go lower than 10 on tWR.


----------



## rastaviper

rares495 said:


> Can your CPU do 1900MHz FCLK?


I have a 3600x, which can run most benchmarks at 4.4Ghz and some at 4.5Ghz.
I can't even boot at 1900.


Veii said:


> People are busy no bad intention
> tRAS would be optimally 31 here, going up and down has negative effects (-1 works but not rec to use it yet)
> tFAW is a bit lower than it should be (you likely just can use it because of your A1 layout, although not rec)
> Best explanation to give is this post:
> https://www.overclock.net/forum/180...tras-34-seems-tras-34-win-9.html#post28383868
> 
> lowering SCL should be your main focus at start
> tRFC is low, but SCL is a bit too high for it - that's a step for another test after you fix some parts
> there is no need for tWRRD delay when you already overshoot tRCDRD 15 with your current set tRDWR 8 (8*2=16) can be just 1
> your tRTP doesn't work with tRFC at all, nor does tWR work with tRFC at all
> if this timings are stable, it's purely only because the board adds latency and also ryzen 3rd gen autocorrects a bit
> 
> Try this:
> 
> 
> 
> 
> 
> 
> 
> 
> CL15 is soo awkward to work with
> If you have post issues or random errors try
> tRFC 338 and tWR 16
> if you still face errors
> tRAS 31, tRC 46, tRFC 345-257-158, tWR 12, tRTP 8


Thanks for your info, but what is the target?
The settings that you are proposing are for making the 3800 a reality?
Because I was also wondering how to lower more the timings at 14-14-14, as I can already run many benches at 15-14-14.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## rares495

rastaviper said:


> I have a 3600x, which can run most benchmarks at 4.4Ghz and some at 4.5Ghz.
> I can't even boot at 1900.Thanks for your info, but what is the target?
> The settings that you are proposing are for making the 3800 a reality?
> Because I was also wondering if it's worth to lower more the timings at 14-14-14.
> 
> Sent from my ONEPLUS A6003 using Tapatalk


If it can't do 1900 FCLK then there's no point in trying for 3800. Your target should be 3600/3733 with as low timings as possible.


----------



## KedarWolf

rares495 said:


> @Veii tRFC 234 is not stable at all and can't post with lower than 10 tRDWR. Sadly I do not have the time to play around anymore right now but will continue to push tonight.
> 
> Current settings:
> 
> VDDP 0.900V
> VDDGs 0.950V
> procODT & all that stuff = Auto (didn't even have to scroll so far down in the bios for these results - might have to do it to go lower)


Have you been stress testing your settings? 

I can run your settings with Gear Down Disabled on my Dual Rank (I know yours are Single Rank) but I'm not stress-tested stable with your settings.

You run Karhu or HCI MemTest or anything to check, see if you get errors?


----------



## rares495

KedarWolf said:


> Have you been stress testing your settings?
> 
> I can run your settings with Gear Down Disabled on my Dual Rank (I know yours are Single Rank) but I'm not stress-tested stable with your settings.
> 
> You run Karhu or HCI MemTest or anything to check, see if you get errors?


I believe this passed 7 hours of Karhu but no cache. Haven't tested with HCI yet. Will leave it running over night.


----------



## rastaviper

rares495 said:


> If it can't do 1900 FCLK then there's no point in trying for 3800. Your target should be 3600/3733 with as low timings as possible.


Well that's why I am asking.
Is it possible for this CPU and with such a bdie to hit 3800?
And with what sort of settings, as I have tried the recommended by the Dram calculator and the system doesnt even boot.


----------



## rares495

rares495 said:


> I believe this passed 7 hours of Karhu but no cache. Haven't tested with HCI yet. Will leave it running over night.


Nope. BSOD after 12min of Karhu w/ cache.


----------



## rares495

rares495 said:


> Nope. BSOD after 12min of Karhu w/ cache.


 @KedarWolf Went back up a bit and this seems more stable. 30min of Karhu w/ cache already.

I might even go back up to 29-42 since that is supposedly better for the sync because I can set the optimal tRFC for that as well.


----------



## rastaviper

So this is my latest result with 3733 15-14-13, 3600x at 4.4Ghz, CPU core 1.46v where I can run any of the benchmarks that I have tried without reboots or errors.
Unfortunately the heat doesn't help too, as in CB20 I get a reboot at 4.450mhz, when the temp hits 90 degrees. I have tried with less cpu voltage but then a reboot is happening.
Mugen Rev B is not enough for my system. :madsmiley


----------



## rares495

rastaviper said:


> So this is my latest result with 3733 15-14-13, 3600x at 4.4Ghz, CPU core 1.46v where I can run any of the benchmarks that I have tried without reboots or errors.
> Unfortunately the heat doesn't help too, as in CB20 I get a reboot at 4.450mhz, when the temp hits 90 degrees. I have tried with less cpu voltage but then a reboot is happening.
> Mugen Rev B is not enough for my system. :madsmiley


1.46V AND 90 degrees? Wow...that CPU will die in a like a week.


----------



## rastaviper

rares495 said:


> 1.46V AND 90 degrees? Wow...that CPU will die in a like a week.


I thought we have a serious discussion here and I wouldn't expect to hear the funny posts that someone can find at Reddit.

Well this CPU is up and running for months because in general it runs under 1.3v, but for benchmarking purposes (where the voltage is higher) it can reach temporarily 90 degrees.
So we will be here next week and no worries the CPU will be fine. Do u have anything useful to add to my previous post?


----------



## rares495

rastaviper said:


> I thought we have a serious discussion here and I wouldn't expect to hear the funny posts that someone can find at Reddit.
> 
> Well this CPU is up and running for months because in general it runs under 1.3v, but for benchmarking purposes (where the voltage is higher) it can reach temporarily 90 degrees.
> So we will be here next week and no worries the CPU will be fine. Do u have anything useful to add to my previous post?


Not really. I'm done giving tech advice to stubborn people. It's just a waste of my limited time.

You do you, bro.


----------



## rastaviper

rares495 said:


> Not really. I'm done giving tech advice to stubborn people. It's just a waste of my limited time.
> 
> 
> 
> You do you, bro.


Lol, really?
Now you play the busy card?
But you had time to make your ironic comment.. Probably you found it funny too.
And what? You didn't expect a reply? 
So now you know for the next time. 

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Saiger0

rastaviper said:


> Lol, really?
> Now you play the busy card?
> But you had time to make your ironic comment.. Probably you found it funny too.
> And what? You didn't expect a reply?
> So now you know for the next time.
> 
> Sent from my ONEPLUS A6003 using Tapatalk



This is a 24/7 stabilty thread where people give advice on daily settings. He was concered about you frying your cpu and had a very valid point. No one expects you to post benchmarking profiles. There are other threads specifically for that topic. Please.


----------



## nick name

rares495 said:


> Nope. BSOD after 12min of Karhu w/ cache.


Yeah, we all need to start testing CPU Cache with Karhu. Seeing folks test without it adds confusion as to what is achievable and what is not.


----------



## nick name

Saiger0 said:


> This is a 24/7 stabilty thread where people give advice on daily settings. He was concered about you frying your cpu and had a very valid point. No one expects you to post benchmarking profiles. There are other threads specifically for that topic. Please.


Very valid point.


----------



## Veii

rares495 said:


> Nobody can understand your logic when it comes to DRAM. Except maybe 1usmus... Explaining further could go a long way.
> 
> And maybe write in a different way. Something like this:
> 
> "Set X to Y because it needs to be equal to W+Z"
> 
> instead of
> 
> "try X+Y because you need to keep in mind W+Z and S when looking at V but V is also affected by G+H when dealing with low F and also changing E and D"


Hahaha, thank you for this kind words 
I can't deny, it happens and i'm sorry for that~
When i write, it always ends up long, because what i write is one to one what i think 
And very often mid writing, i remember "oh i should mention X scenario has to be met, else the advice is useless" 
I can see why it's confusing

Memory calculation has soo many connections together and little caveats you need to have considered
before even trying the "public rule"

Let's try this again 
How to calculate tRDWR & tWRRD - Single Ranked way:

Imagine we have 3 sets of timings:
1.) 14-14-14-14-28-32 SLC 3 (Typical SR B-dies)
2.) 16-16-17-16-32-48 SLC 4 (Micron kits, high speed DR b-dies)
3.) 14-17-19-18-42-60 SCL 2 (Hynix MFR, CFR, anything Hynix)

*1.)*


Spoiler



What commonly works is
tRDWR 8
tWRRD 1
has wasted delay, not influenced by SCL & is rockstable
tRDWR 7
tWRRD 1
works still because *2**7 is 14 = perfect result, no wasted latency
perfect result = no need to use tWRRD to add latency
tRDWR 6
tWRRD 3
you can lower tRDWR for -1 of tRCD WR, but because 6*2 is 12 and not =14 or >14, you have to add latency
tWRRD is this latency, you use SCL here for calculation helper, and use either *2 or *4 for math
important is that this result is *smaller or equal to tRCD RD* (write to read transition = tWRRD)
*「*Soo what works now:
4*2 = 8, nope not enough
4*3 = 12, that can work
4*4 = 16, this overshoots and is too much
2*5 = 10, this can maaybe work, let's see
2*6 = 12, this can work - but it won't, more to it later
2*7 = 14, this would work in a perfect world, but it won't - more to it later*」*

Double-check calculate with SCL:
because what to pick is not always clear, clear is only that tWRRD should not overshoot used tRCD RD timing
we have here SCL 3, soo optimally 3 times value of tWRRD
3*2=6, not enough
3*3=9, maybe, would post but likely not enough delay
3*4=12, this looks alright
3*5=15, too much

Soo we end up as options:
3*4=12
2*7=14 
Aka 
tRDWR 6 
tWRRD 4
or 
tRDWR 6
tWRRD 7

But we have a problem
Rule of tRDWR and tWRRD says, only *one of both* can be a *big value*
Only one of them can be used as main delay, and the other has to be used or not used as added delay
Because we have *tRCD WR* as *biggest delay* in the chain, we need to focus on only one
We could run:
tRDWR 4
tWRRD 6
in theory it could work, in practical terms it won't
because every read command, discharges the cell fully and needs time to recharge
Soo priority is first tRDWR, then tWRRD - resulting in more stability if you increase tRCD WR and not tRCD RD first 


*2.)*


Spoiler



What works here:
tRDWR 9
tWRRD 1
has wasted delay because *2**9=18, but works fine because result is not smaller than 17
tRDWR 8
tWRRD 4
we have to use added latency here, because *2**8=16, but we need 17
that can be calculated either SCL * tWRRD value or the manual way like example *1#*
4*4=16 , that's a perfect match - important is just that it doesn't overshoot tRCD RD

We could also use
tRDWR 8
tWRRD 3
because 4*3 is 12 which near 16, it could pass
But 4*4 = tWRRD 4 ** 4* (default multiplier 4 which also is here SCL 4) = 16
this is a better option to use in having less wasted latency somewhere in the chain

If we would have here SCL of 3 we could only use
tWRRD 4 = (4*3) = 12, that is not over 16, would be fine
trying 3*3 would result in 9, and this is then not enough latency
* soo always keep your SCL in mind, even when default math for tWRRD is **4* or _sometimes *2_ on timings over >20


*3.)*


Spoiler



This is again one example of ODD timings, but this time with very low SLC under very high voltage
we look for tRCD WR 19 and tRCD RD 17 / the rest of the timings don't matter
tRDWR 10
tWRRD 1
Our usual safe play, 10*2=20 higher delay on read to write, 
because IC are slow and we have huge delay in tRCD WR
tRDWR 9
tWRRD 8
you could expect to use 8, because we spoke about " high delay *2 instead *4 "
a better option is:
tRDWR 9
tWRRD 4
This would be *4**4=16, a tiny bit under 17
- which has just enough delay to cover this tRDWR= (tRCD WR/2)-1, way of cutting latency and increasing bandwidth


Ruleset in short:
tRDWR needs a *2 multiplier and *can overshoot*, *or be equal* to tRCD WR
tWRRD (if used) needs to focus either on **4* multiplier or work SCL to add latency. It should be as close to tRCD RD as possible

Keep in mind, this ruleset works for all 3 examples perfectly
But i see it doesn't work with Dual Rank dimms - which need for some reason higher tRDWR delay wasted somewhere
Maybe i'm overseeing one timing which wastes this latency, or "higher tRFC than for SR" is the culprit here
Soo use it only for single rank
tWRRD should have the same rules, just minimum tWRRD doesn't seem to work out :thinking:

Hopefully it is this time finally understandable
I can't explain it more simple than that :teaching:


rares495 said:


> Also, we could use your full calculator even if it's in beta. Mind sharing it?


Sorry i can't so far, it needs weeks of work till it can be usable to people who don't know the material at all
I haven't fully figured out how DRAM exactly works in all it's steps, to be able to calculate delay (in ns) better
And so knowing maximum global tRFC
But i need this , soo efficiency to frequency is predicted far more accurately :thumb:

There is still a lot to do and a lot i want to implement than just this tiny cutout you see here
i also shared only the tRFC calculator part of it - because i thought it was finally needed, to help people get their timings accurately
and me getting a bit of rest - as there is far to much projects to finish, than doing timings for people
That's the reason of this tutorial here
To teach people, not to work for them without them learning anything


----------



## Veii

rastaviper said:


> I have a 3600x, which can run most benchmarks at 4.4Ghz and some at 4.5Ghz.
> I can't even boot at 1900.Thanks for your info, but what is the target?
> The settings that you are proposing are for making the 3800 a reality?
> Because I was also wondering how to lower more the timings at 14-14-14, as I can already run many benches at 15-14-14.


The reason for them is , so you start slowly getting away that tRCD WR 16 which bothers too much
With it there you would need to focus on timings like 14-14-16-15 or 14-15-16-14 to have a well working calculation
15 same like 7, are very annoying numbers to work with, getting CL15 away would go a big way in future tightening progress
I purposely used higher tRFC soo you don't have to think about 4-5 potential desync locations
It might be slower, but you can focus on working away SCL , lowering tRCD WR and lowering tCL

Your ultimate goal is getting clean (no delay) tRAS transition, and then being able to use low tRC
Getting this first 3 timings correctly and tight (tCL, tRCD, tRP) is key for having anything after it function fine
having 7.5 value as multiplier, even calculated by ns purely - is a mess, soo i had to use high timings

This is your goal 
I'm not focusing on benchmark settings, here no one cares for them
You can care for them after you get your ram stable - 24/7 is important
And a lot of bad timings will be 24/7 stable, because the board and now the cpu do autocorrect and add non readable delay to timings
Soo again, purpose of this is to get your rams in clean sync - later you can consider tighten them step by step
But having strange first 3 timings don't help anything, you'll only go into a rabbit hole of testing without fixing it first :ninja:

Oh, no all where for b-dies
The rules are universal , only what changes per IC is first 3 timings, and tRFC
SCL is more PCB focused than IC focused
@rares495 & @KedarWolf
Always use tRFC 2 and 4 the one i write out - or if not clear via tRFC Calculator for *6, copy ns value with decimal and use in DRAM Calculator
I know i know "it's not used unless memory hits 85c" 
But that's not the whole story
It isn't used directly - but it changes more than one part and it changes tREFI range
It changes timings, bank swapping and functions we have no access too
Always change it, that's my advice (i've seen differences on the HynixMFR timings)
- although it changes tiny bits +/- 1, soo you maaybe could ignore it if you want
@kyo2020 tRFC 2 and 4 is never higher than tRFC
ultimately you calculate it via ns only - but you can use either my tRFC calculator or 1usmus DRAM calculator - Additional Calculator menu
^ IF , you start to use tRFC 2 and 4 - if not, keep it identical to main tRFC


----------



## KedarWolf

Veii said:


> Hahaha, thank you for this kind words
> I can't deny, it happens and i'm sorry for that~
> When i write, it always ends up long, because what i write is one to one what i think
> And very often mid writing, i remember "oh i should mention X scenario has to be met, else the advice is useless"
> I can see why it's confusing
> 
> 
> 
> Spoiler
> 
> 
> 
> Memory calculation has soo many connections together and little caveats you need to have considered
> before even trying the "public rule"
> 
> Let's try this again
> How to calculate tRDWR & tWRRD - Single Ranked way:
> 
> Imagine we have 3 sets of timings:
> 1.) 14-14-14-14-28-32 SLC 3 (Typical SR B-dies)
> 2.) 16-16-17-16-32-48 SLC 4 (Micron kits, high speed DR b-dies)
> 3.) 14-17-19-18-42-60 SCL 2 (Hynix MFR, CFR, anything Hynix)
> 
> *1.)*
> 
> 
> Spoiler
> 
> 
> 
> What commonly works is
> tRDWR 8
> tWRRD 1
> has wasted delay, not influenced by SCL & is rockstable
> tRDWR 7
> tWRRD 1
> works still because *2**7 is 14 = perfect result, no wasted latency
> perfect result = no need to use tWRRD to add latency
> tRDWR 6
> tWRRD 3
> you can lower tRDWR for -1 of tRCD WR, but because 6*2 is 12 and not =14 or >14, you have to add latency
> tWRRD is this latency, you use SCL here for calculation helper, and use either *2 or *4 for math
> important is that this result is *smaller or equal to tRCD RD* (write to read transition = tWRRD)
> *「*Soo what works now:
> 4*2 = 8, nope not enough
> 4*3 = 12, that can work
> 4*4 = 16, this overshoots and is too much
> 2*5 = 10, this can maaybe work, let's see
> 2*6 = 12, this can work - but it won't, more to it later
> 2*7 = 14, this would work in a perfect world, but it won't - more to it later*」*
> 
> Double-check calculate with SCL:
> because what to pick is not always clear, clear is only that tWRRD should not overshoot used tRCD RD timing
> we have here SCL 3, soo optimally 3 times value of tWRRD
> 3*2=6, not enough
> 3*3=9, maybe, would post but likely not enough delay
> 3*4=12, this looks alright
> 3*5=15, too much
> 
> Soo we end up as options:
> 3*4=12
> 2*7=14
> Aka
> tRDWR 6
> tWRRD 4
> or
> tRDWR 6
> tWRRD 7
> 
> But we have a problem
> Rule of tRDWR and tWRRD says, only *one of both* can be a *big value*
> Only one of them can be used as main delay, and the other has to be used or not used as added delay
> Because we have *tRCD WR* as *biggest delay* in the chain, we need to focus on only one
> We could run:
> tRDWR 4
> tWRRD 6
> in theory it could work, in practical terms it won't
> because every read command, discharges the cell fully and needs time to recharge
> Soo priority is first tRDWR, then tWRRD - resulting in more stability if you increase tRCD WR and not tRCD RD first
> 
> 
> *2.)*
> 
> 
> Spoiler
> 
> 
> 
> What works here:
> tRDWR 9
> tWRRD 1
> has wasted delay because *2**9=18, but works fine because result is not smaller than 17
> tRDWR 8
> tWRRD 4
> we have to use added latency here, because *2**8=16, but we need 17
> that can be calculated either SCL * tWRRD value or the manual way like example *1#*
> 4*4=16 , that's a perfect match - important is just that it doesn't overshoot tRCD RD
> 
> We could also use
> tRDWR 8
> tWRRD 3
> because 4*3 is 12 which near 16, it could pass
> But 4*4 = tWRRD 4 ** 4* (default multiplier 4 which also is here SCL 4) = 16
> this is a better option to use in having less wasted latency somewhere in the chain
> 
> If we would have here SCL of 3 we could only use
> tWRRD 4 = (4*3) = 12, that is not over 16, would be fine
> trying 3*3 would result in 9, and this is then not enough latency
> * soo always keep your SCL in mind, even when default math for tWRRD is **4* or _sometimes *2_ on timings over >20
> 
> 
> *3.)*
> 
> 
> Spoiler
> 
> 
> 
> This is again one example of ODD timings, but this time with very low SLC under very high voltage
> we look for tRCD WR 19 and tRCD RD 17 / the rest of the timings don't matter
> tRDWR 10
> tWRRD 1
> Our usual safe play, 10*2=20 higher delay on read to write,
> because IC are slow and we have huge delay in tRCD WR
> tRDWR 9
> tWRRD 8
> you could expect to use 8, because we spoke about " high delay *2 instead *4 "
> a better option is:
> tRDWR 9
> tWRRD 4
> This would be *4**4=16, a tiny bit under 17
> - which has just enough delay to cover this tRDWR= (tRCD WR/2)-1, way of cutting latency and increasing bandwidth
> 
> 
> Ruleset in short:
> tRDWR needs a *2 multiplier and *can overshoot*, *or be equal* to tRCD WR
> tWRRD (if used) needs to focus either on **4* multiplier or work SCL to add latency. It should be as close to tRCD RD as possible
> 
> Keep in mind, this ruleset works for all 3 examples perfectly
> But i see it doesn't work with Dual Rank dimms - which need for some reason higher tRDWR delay wasted somewhere
> Maybe i'm overseeing one timing which wastes this latency, or "higher tRFC than for SR" is the culprit here
> Soo use it only for single rank
> tWRRD should have the same rules, just minimum tWRRD doesn't seem to work out :thinking:
> 
> Hopefully it is this time finally understandable
> I can't explain it more simple than that :teaching:
> 
> Sorry i can't so far, it needs weeks of work till it can be usable to people who don't know the material at all
> I haven't fully figured out how DRAM exactly works in all it's steps, to be able to calculate delay (in ns) better
> And so knowing maximum global tRFC
> But i need this , soo efficiency to frequency is predicted far more accurately :thumb:
> 
> There is still a lot to do and a lot i want to implement than just this tiny cutout you see here
> i also shared only the tRFC calculator part of it - because i thought it was finally needed, to help people get their timings accurately
> and me getting a bit of rest - as there is far to much projects to finish, than doing timings for people
> That's the reason of this tutorial here
> To teach people, not to work for them without them learning anything


It's a bit confusing. I have Dual Rank RAM. Lowest tRDWR I can go is 10. 
I fixed the tRFC according to your Calculator.
This is so far HCI stable with Gear Down Mode disabled.
I get some lower Read, Write And Copy then my Gear Down Enabled settings but my latency goes from 62.3 to 62.1

@Veii Would I be better off going SCL 3 and tWRRD 4 and leave TRDWR at 10?
So far I have SCLs at 2.


----------



## Veii

Try to push ClkDrvStren to 60ohm / 60-20-20-24
This should help a big chunk, but will increase thermals on 3 parts
Mosfets, CPU sillicon, Memory
Should be fine, changes would be around 3-5c max

Keep your low SCL
What i didn't mention was, that SCL2 can be used as *4 too , doesn't have to be *2
The fixed rule of tRDWR *2 and tWRRD *4 always stays, just sometimes *3 works or *5 works ~ which depend on SCL
If you use values like SCL 3,5,7 then it's good to focus on it, else *4 works always as baseline

You can try going down to 9 if 10/1 is your maximum
9 with something , we have to see
your tRCD RD is 8, with SCL 2 logical result is tWRRD 4, but if 4 doesn't post, tWRRD 2 can work too
appreciate your low SLC, too high delay will overshoot low tRFC 

it might be better to push tRRDL to 5 instead of 4
But let's keep that aside for now, as optional option - might lead to a better score, but doesn't have to be used
Nothing to say else, tRDWR needs to be lower, that's the first priority


----------



## KedarWolf

Veii said:


> Try to push ClkDrvStren to 60ohm / 60-20-20-24
> This should help a big chunk, but will increase thermals on 3 parts
> Mosfets, CPU sillicon, Memory
> Should be fine, changes would be around 3-5c max
> 
> 
> 
> Spoiler
> 
> 
> 
> Keep your low SLC
> What i didn't mention was, that SCL2 can be used as *4 too , doesn't have to be *2
> The fixed rule of tRDWR *2 and tWRRD *4 always stays, just sometimes *3 works or *5 works ~ which depend on SCL
> If you use values like SCL 3,5,7 then it's good to focus on it, else *4 works always as baseline
> 
> You can try going down to 9 if 10/1 is your maximum
> 9 with something , we have to see
> your tRCD RD is 8, with SCL 2 logical result is tWRRD 4, but if 4 doesn't post, tWRRD 2 can work too
> appreciate your low SLC, too high delay will overshoot low tRFC
> 
> it might be better to push tRRDL to 5 instead of 4
> But let's keep that aside for now, as optional option - might lead to a better score, but doesn't have to be used
> Nothing to say else, tRDWR needs to be lower, that's the first priority


Will tRDWR x5 SCLs work if I keep SCLs on 2? Or should I change it to 12?

I ask because no post on tRDWR under 10. 

Got tWRRD to 4 and ClkDrvStren to 60ohm / 60-20-20-24.


----------



## Veii

KedarWolf said:


> Will tRDWR x5 SCLs work if I keep SCLs on 2? Or should I change it to 12?
> 
> I ask because no post on tRDWR under 10.
> 
> Got tWRRD to 4 and ClkDrvStren to 60ohm / 60-20-20-24.


tRDWR has to stay *2 
tWRRD has many "it depends on X" parts and plays with SCL, tRDWR doesn't
you should have a high range, but it doesn't let you for some reason
One thing that pushes high tRDWR is frequency, another is SCL, another seems to be dual rank
Because this doesn't happen on 4 dimms 

Why do you run 2T ? only way to keep GDM disabled ?
one thing i don't understand is SD DD range yet
Wonder if 5 5 7 7 behaved bad or hindered you to lower timings further before 

There's not much to say right now, you have the option to lower tRC -2 , and so use lower tRFC
But you want to keep it a multiple of your tRTP if possible for better stability 
You can try to get back tWR to 12 , if the tRFC does divide fine by 12 and fine by 6
We're going that way backwards , but somehow you need to get that tRDWR down 

Maaybe you need tRCD RD 15 to get with tRP 12 in order for anything else to function
But this high tRDWR bothers


----------



## kyo2020

Veii said:


> The reason for them is , so you start slowly getting away that tRCD WR 16 which bothers too much
> With it there you would need to focus on timings like 14-14-16-15 or 14-15-16-14 to have a well working calculation
> 15 same like 7, are very annoying numbers to work with, getting CL15 away would go a big way in future tightening progress
> I purposely used higher tRFC soo you don't have to think about 4-5 potential desync locations
> It might be slower, but you can focus on working away SCL , lowering tRCD WR and lowering tCL
> 
> Your ultimate goal is getting clean (no delay) tRAS transition, and then being able to use low tRC
> Getting this first 3 timings correctly and tight (tCL, tRCD, tRP) is key for having anything after it function fine
> having 7.5 value as multiplier, even calculated by ns purely - is a mess, soo i had to use high timings
> 
> This is your goal
> I'm not focusing on benchmark settings, here no one cares for them
> You can care for them after you get your ram stable - 24/7 is important
> And a lot of bad timings will be 24/7 stable, because the board and now the cpu do autocorrect and add non readable delay to timings
> Soo again, purpose of this is to get your rams in clean sync - later you can consider tighten them step by step
> But having strange first 3 timings don't help anything, you'll only go into a rabbit hole of testing without fixing it first :ninja:
> 
> Oh, no all where for b-dies
> The rules are universal , only what changes per IC is first 3 timings, and tRFC
> SCL is more PCB focused than IC focused
> 
> @*rares495* & @*KedarWolf*
> Always use tRFC 2 and 4 the one i write out - or if not clear via tRFC Calculator for *6, copy ns value with decimal and use in DRAM Calculator
> I know i know "it's not used unless memory hits 85c"
> But that's not the whole story
> It isn't used directly - but it changes more than one part and it changes tREFI range
> It changes timings, bank swapping and functions we have no access too
> Always change it, that's my advice (i've seen differences on the HynixMFR timings)
> - although it changes tiny bits +/- 1, soo you maaybe could ignore it if you want
> 
> @*kyo2020* tRFC 2 and 4 is never higher than tRFC
> ultimately you calculate it via ns only - but you can use either my tRFC calculator or 1usmus DRAM calculator - Additional Calculator menu
> ^ IF , you start to use tRFC 2 and 4 - if not, keep it identical to main tRFC



I'm going to try leaving them all at 394. Question why others achieve higher bandwidth with the memories at 3800 mhz ?, I tried to lower the main latencies to 16 using higher voltage but the change is minimal it is not worth it. But others with equal latencies have more memory bandwidth.


----------



## Veii

kyo2020 said:


> I'm going to try leaving them all at 394. Question why others achieve higher bandwidth with the memories at 3800 mhz ?, I tried to lower the main latencies to 16 using higher voltage but the change is minimal it is not worth it. But others with equal latencies have more memory bandwidth.


Using <Spoiler> as example


Spoiler














Memory Bandwidth depends on memory efficiency
efficiency depends on how fast memory can do X operation, which depends all just on delays
You get higher efficiency the less "wasted" delays exist between your timings
You need this delays between each command, soo voltage can recharge cells and used memory ICs can do their job with the timeframe you give it to
The less "wasted" delay exists between each operation, the better your efficiency is = better bandwidth

Your timings for example are very very open
And your voltages are far to high
when you use CLDO_VDDG of 1.025v (hopefully VDDP of 900mV)
then the minimum vSOC it allows you is 1.075-1.1v (50-75mV higher as fixed ruleset)
There is no need to run 1.15v , it will help nothing only lower signal integrity and increase useless heat
(50mV less on SOC for a 3950X are about 50-60W savings)
High vSOC also requires you to use higher procODT resistance - which at the end all together limit your maximum OC capabilities
Soo lower that first
You aren't going for >4000 on 4 dimms to request any vSOC over 1.1v

Next,
You aren't using Dual rank kits and use 4 dimms
Enable Bank Group Swap, and disable BGS Alt 
Intelligent bioses should have that automatically disabled, but you never know
Your 24-20-24-24 is fine for now, rec is to push 30-20-24-24 but then it might even allow you 30-20-20-24 when signal integrity is cleaner

Who told you tWRWR SD DD & tRDRD SD DD using these values? 
tFAW should be 36 or 24
I see you cut tRC -2 and tCWL = tCL-2 as maximum , but why ?
Why did you keep that high SCL ?

Rec tRFC for this timings is 384-285-176
even if we consider +1 cycle more = +16 tRFC, it's still wrong tRFC on your side, as it shows +10
+8 tRFC is half cycle 
+4 is 1/4
+2 is 1/8
If this tRFC doesn't post, it's because SCL are just far to high - lowering it to 4 would help a lot
if you lower it to 4, then you need to change tWRRD to 4


----------



## KedarWolf

Veii said:


> tRDWR has to stay *2
> tWRRD has many "it depends on X" parts and plays with SCL, tRDWR doesn't
> you should have a high range, but it doesn't let you for some reason
> One thing that pushes high tRDWR is frequency, another is SCL, another seems to be dual rank
> Because this doesn't happen on 4 dimms
> 
> Why do you run 2T ? only way to keep GDM disabled ?
> one thing i don't understand is SD DD range yet
> Wonder if 5 5 7 7 behaved bad or hindered you to lower timings further before
> 
> There's not much to say right now, you have the option to lower tRC -2 , and so use lower tRFC
> But you want to keep it a multiple of your tRTP if possible for better stability
> You can try to get back tWR to 12 , if the tRFC does divide fine by 12 and fine by 6
> We're going that way backwards , but somehow you need to get that tRDWR down
> 
> Maybe you need tRCD RD 15 to get with tRP 12 in order for anything else to function
> But this high tRDWR bothers


Yes, BSODs with Gear Down Mode disabled.

I get better AIDA Read, Right and Copy with Gear Down Mode enabled with better timings and 1T, but my latency goes up .1NS 62.1 to 62.2.

I think I'm better off Gear Down Mode enabled, here's disabled and enabled below, in order.


----------



## kyo2020

Veii said:


> Using <Spoiler> as example
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Memory Bandwidth depends on memory efficiency
> efficiency depends on how fast memory can do X operation, which depends all just on delays
> You get higher efficiency the less "wasted" delays exist between your timings
> You need this delays between each command, soo voltage can recharge cells and used memory ICs can do their job with the timeframe you give it to
> The less "wasted" delay exists between each operation, the better your efficiency is = better bandwidth
> 
> Your timings for example are very very open
> And your voltages are far to high
> when you use CLDO_VDDG of 1.025v (hopefully VDDP of 900mV)
> then the minimum vSOC it allows you is 1.075-1.1v (50-75mV higher as fixed ruleset)
> There is no need to run 1.15v , it will help nothing only lower signal integrity and increase useless heat
> (50mV less on SOC for a 3950X are about 50-60W savings)
> High vSOC also requires you to use higher procODT resistance - which at the end all together limit your maximum OC capabilities
> Soo lower that first
> You aren't going for >4000 on 4 dimms to request any vSOC over 1.1v
> 
> Next,
> You aren't using Dual rank kits and use 4 dimms
> Enable Bank Group Swap, and disable BGS Alt
> Intelligent bioses should have that automatically disabled, but you never know
> Your 24-20-24-24 is fine for now, rec is to push 30-20-24-24 but then it might even allow you 30-20-20-24 when signal integrity is cleaner
> 
> Who told you tWRWR SD DD & tRDRD SD DD using these values?
> tFAW should be 36 or 24
> I see you cut tRC -2 and tCWL = tCL-2 as maximum , but why ?
> Why did you keep that high SCL ?
> 
> Rec tRFC for this timings is 384-285-176
> even if we consider +1 cycle more = +16 tRFC, it's still wrong tRFC on your side, as it shows +10
> +8 tRFC is half cycle
> +4 is 1/4
> +2 is 1/8
> If this tRFC doesn't post, it's because SCL are just far to high - lowering it to 4 would help a lot
> if you lower it to 4, then you need to change tWRRD to 4


I understand, the time I got automatically using the XMP is what appears automatically at 3200 mhz, the main latencies are added by me, the cad, procodt is automatic. It is largely automatic but it works. There was no information about the 3800 mhz on my motherboard and I got it to work with these times months ago it works like this without errors. If under the tRFC you do not find memory errors but it may happen that the computer restarts itself randomly. Could you make me the list of latencies at 3800 mhz for better memory bandwidth results, I would be very useful there is not much information for the 3800 mhz on my motherboard with these memories.


----------



## Veii

KedarWolf said:


> Yes, BSODs with Gear Down Mode disabled.
> 
> I get better AIDA Read, Right and Copy with Gear Down Mode enabled with better timings and 1T, but my latency goes up .1NS 62.1 to 62.2.
> 
> I think I'm better off Gear Down Mode enabled, here's disabled and enabled below, in order.
> 
> 
> Spoiler


Keep in mind, GearDownMode, pushes all ODD values to EVEN values - it rounds it up
You are running 14-8-16-14-30-40 tCWL 14 with GDM enabled
Also Aida64 is good to know Read and Write bandwith and how Cache bandwith does
But SiSandra results are accurate, Aida64 latency results don't mean much 
The difference should be quite big without GDM 

If you run SiSandra, be sure everything is turned off that you can turn off (just as comparison)
Having background tasks, will wake up sleeping cores and so lower effective boost = also lower result
Lower it a bit, because SiSandra Multi-Core efficiency depends on efficiency not cpu freq , but it will make a difference in effective performance


----------



## KedarWolf

Veii said:


> Try to push ClkDrvStren to 60ohm / 60-20-20-24
> This should help a big chunk, but will increase thermals on 3 parts
> Mosfets, CPU sillicon, Memory
> Should be fine, changes would be around 3-5c max
> 
> 
> 
> Spoiler
> 
> 
> 
> Keep your low SCL
> What i didn't mention was, that SCL2 can be used as *4 too , doesn't have to be *2
> The fixed rule of tRDWR *2 and tWRRD *4 always stays, just sometimes *3 works or *5 works ~ which depend on SCL
> If you use values like SCL 3,5,7 then it's good to focus on it, else *4 works always as baseline
> 
> You can try going down to 9 if 10/1 is your maximum
> 9 with something , we have to see
> your tRCD RD is 8, with SCL 2 logical result is tWRRD 4, but if 4 doesn't post, tWRRD 2 can work too
> appreciate your low SLC, too high delay will overshoot low tRFC
> 
> it might be better to push tRRDL to 5 instead of 4
> But let's keep that aside for now, as optional option - might lead to a better score, but doesn't have to be used
> Nothing to say else, tRDWR needs to be lower, that's the first priority


My temps are really good BTW.

My CPU at my current settings with an Optimus Foundation block and one 360 rad stay under 65C while running Cinebench. Even when stress testing my RAM is under 37C. Not sure what my MOSFETs are under in HWInfo but my VRMs and chipset stay nice and low. My chipset fan NEVER turns on, set to start spinning at 60C. 

Oh, found it. This is with Cinibench running, nice and low.


----------



## Veii

KedarWolf said:


> My temps are really good BTW.
> 
> My CPU at my current settings with an Optimus Foundation block and one 360 rad stay under 65C while running Cinebench. Even when stress testing my RAM is under 37C. Not sure what my MOSFETs are under in HWInfo but my VRMs and chipset stay nice and low. My chipset fan NEVER turns on, set to start spinning at 60C.
> 
> Oh, found it. This is with Cinebench running, nice and low.


Hehe 
It can run cooler 
If you take a look a the center bottom row
VR VOUT 1.275v
That's how much vcore is requested running through your Mosfets (vCore section)
And bottom one is vSOC , delivered is 1.105v - requested is 1.116

we can see your LLC does overshoot a bit on the SOC line, same for the vCore line
Interesting is CHIP SOC arrives 1.008v, soo somewhere you lost a bit
Accurate temps would be 41c for the VRM section - but Cine R20 rly doesn't put stress on it
Y-Cruncher would be used for 3rd gen or LinpackXtreme 1.1.2


----------



## KedarWolf

Veii said:


> Hehe
> It can run cooler
> If you take a look a the center bottom row
> VR VOUT 1.275v
> That's how much vcore is requested running through your Mosfets (vCore section)
> And bottom one is vSOC , delivered is 1.105v - requested is 1.116
> 
> we can see your LLC does overshoot a bit on the SOC line, same for the vCore line
> Interesting is CHIP SOC arrives 1.008v, soo somewhere you lost a bit
> Accurate temps would be 41c for the VRM section - but Cine R20 rly doesn't put stress on it
> Y-Cruncher would be used for 3rd gen or LinpackXtreme 1.1.2


I have it on LLC3.

Here is Linpack XTreme 1.1.2 running.

Edit: What's the Chip SOC supposed to be at and any point in fixing it?


----------



## rares495

Veii said:


> Hahaha, thank you for this kind words
> I can't deny, it happens and i'm sorry for that~
> When i write, it always ends up long, because what i write is one to one what i think
> And very often mid writing, i remember "oh i should mention X scenario has to be met, else the advice is useless"
> I can see why it's confusing
> 
> Memory calculation has soo many connections together and little caveats you need to have considered
> before even trying the "public rule"
> 
> Let's try this again
> How to calculate tRDWR & tWRRD - Single Ranked way:
> 
> Imagine we have 3 sets of timings:
> 1.) 14-14-14-14-28-32 SLC 3 (Typical SR B-dies)
> 2.) 16-16-17-16-32-48 SLC 4 (Micron kits, high speed DR b-dies)
> 3.) 14-17-19-18-42-60 SCL 2 (Hynix MFR, CFR, anything Hynix)
> 
> *1.)*
> 
> 
> Spoiler
> 
> 
> 
> What commonly works is
> tRDWR 8
> tWRRD 1
> has wasted delay, not influenced by SCL & is rockstable
> tRDWR 7
> tWRRD 1
> works still because *2**7 is 14 = perfect result, no wasted latency
> perfect result = no need to use tWRRD to add latency
> tRDWR 6
> tWRRD 3
> you can lower tRDWR for -1 of tRCD WR, but because 6*2 is 12 and not =14 or >14, you have to add latency
> tWRRD is this latency, you use SCL here for calculation helper, and use either *2 or *4 for math
> important is that this result is *smaller or equal to tRCD RD* (write to read transition = tWRRD)
> *「*Soo what works now:
> 4*2 = 8, nope not enough
> 4*3 = 12, that can work
> 4*4 = 16, this overshoots and is too much
> 2*5 = 10, this can maaybe work, let's see
> 2*6 = 12, this can work - but it won't, more to it later
> 2*7 = 14, this would work in a perfect world, but it won't - more to it later*」*
> 
> Double-check calculate with SCL:
> because what to pick is not always clear, clear is only that tWRRD should not overshoot used tRCD RD timing
> we have here SCL 3, soo optimally 3 times value of tWRRD
> 3*2=6, not enough
> 3*3=9, maybe, would post but likely not enough delay
> 3*4=12, this looks alright
> 3*5=15, too much
> 
> Soo we end up as options:
> 3*4=12
> 2*7=14
> Aka
> tRDWR 6
> tWRRD 4
> or
> tRDWR 6
> tWRRD 7
> 
> But we have a problem
> Rule of tRDWR and tWRRD says, only *one of both* can be a *big value*
> Only one of them can be used as main delay, and the other has to be used or not used as added delay
> Because we have *tRCD WR* as *biggest delay* in the chain, we need to focus on only one
> We could run:
> tRDWR 4
> tWRRD 6
> in theory it could work, in practical terms it won't
> because every read command, discharges the cell fully and needs time to recharge
> Soo priority is first tRDWR, then tWRRD - resulting in more stability if you increase tRCD WR and not tRCD RD first
> 
> 
> *2.)*
> 
> 
> Spoiler
> 
> 
> 
> What works here:
> tRDWR 9
> tWRRD 1
> has wasted delay because *2**9=18, but works fine because result is not smaller than 17
> tRDWR 8
> tWRRD 4
> we have to use added latency here, because *2**8=16, but we need 17
> that can be calculated either SCL * tWRRD value or the manual way like example *1#*
> 4*4=16 , that's a perfect match - important is just that it doesn't overshoot tRCD RD
> 
> We could also use
> tRDWR 8
> tWRRD 3
> because 4*3 is 12 which near 16, it could pass
> But 4*4 = tWRRD 4 ** 4* (default multiplier 4 which also is here SCL 4) = 16
> this is a better option to use in having less wasted latency somewhere in the chain
> 
> If we would have here SCL of 3 we could only use
> tWRRD 4 = (4*3) = 12, that is not over 16, would be fine
> trying 3*3 would result in 9, and this is then not enough latency
> * soo always keep your SCL in mind, even when default math for tWRRD is **4* or _sometimes *2_ on timings over >20
> 
> 
> *3.)*
> 
> 
> Spoiler
> 
> 
> 
> This is again one example of ODD timings, but this time with very low SLC under very high voltage
> we look for tRCD WR 19 and tRCD RD 17 / the rest of the timings don't matter
> tRDWR 10
> tWRRD 1
> Our usual safe play, 10*2=20 higher delay on read to write,
> because IC are slow and we have huge delay in tRCD WR
> tRDWR 9
> tWRRD 8
> you could expect to use 8, because we spoke about " high delay *2 instead *4 "
> a better option is:
> tRDWR 9
> tWRRD 4
> This would be *4**4=16, a tiny bit under 17
> - which has just enough delay to cover this tRDWR= (tRCD WR/2)-1, way of cutting latency and increasing bandwidth
> 
> 
> Ruleset in short:
> tRDWR needs a *2 multiplier and *can overshoot*, *or be equal* to tRCD WR
> tWRRD (if used) needs to focus either on **4* multiplier or work SCL to add latency. It should be as close to tRCD RD as possible
> 
> Keep in mind, this ruleset works for all 3 examples perfectly
> But i see it doesn't work with Dual Rank dimms - which need for some reason higher tRDWR delay wasted somewhere
> Maybe i'm overseeing one timing which wastes this latency, or "higher tRFC than for SR" is the culprit here
> Soo use it only for single rank
> tWRRD should have the same rules, just minimum tWRRD doesn't seem to work out :thinking:
> 
> Hopefully it is this time finally understandable
> I can't explain it more simple than that :teaching:
> 
> Sorry i can't so far, it needs weeks of work till it can be usable to people who don't know the material at all
> I haven't fully figured out how DRAM exactly works in all it's steps, to be able to calculate delay (in ns) better
> And so knowing maximum global tRFC
> But i need this , soo efficiency to frequency is predicted far more accurately :thumb:
> 
> There is still a lot to do and a lot i want to implement than just this tiny cutout you see here
> i also shared only the tRFC calculator part of it - because i thought it was finally needed, to help people get their timings accurately
> and me getting a bit of rest - as there is far to much projects to finish, than doing timings for people
> That's the reason of this tutorial here
> To teach people, not to work for them without them learning anything


I couldn't get tRDWR lower than 10 in any way so I just went back to 14-14-12-28-40, everything else on Auto and adjusted from there. The board automagically set tRDWR to 8 and tWRRD to 2 which goes against your rule. Tried 7-1 but no post. Tried SCL 4 + 6-3 and no post.

procODT still 36.9ohm and CAD_bus all 24 set by the board on Auto.


----------



## rares495

Aaaaand it seems that I cannot set a RCDRD lower than 15 or there will be errors. At least now I know a bit more about my kit. Next is getting tWR and tRTP back down to acceptable values.


----------



## KedarWolf

rares495 said:


> Aaaaand it seems that I cannot set a RCDRD lower than 15 or there will be errors. At least now I know a bit more about my kit. Next is getting tWR and tRTP back down to acceptable values.


In the Spoiler is BIOS settings of what is passing HCI and Karhu, cache enabled. Don't be afraid to try 2T if 1T is unstable. Higher RAM frequencies it happens. :drum:

Note all the voltages on manual. :thumb:

Note: I have tWRRD at 1 as I found I get a rather large reduction in SisSoftware Sandra Processor Multi-Core Efficiency bandwidth and a bit higher latency. Same with AIDA64 Extreme cache and memory test. :h34r-smi

Still can't get tRDWR lower, even tried most things on Auto, nada. 

*Edit: Tested it again, tWRRD at 4 is better.* :glasses












Spoiler


----------



## rares495

KedarWolf said:


> In the Spoiler is BIOS settings of what is passing HCI and Karhu, cache enabled. Don't be afraid to try 2T if 1T is unstable. Higher RAM frequencies it happens. :drum:
> 
> Note all the voltages on manual. :thumb:
> 
> Note: I have tWRRD at 1 as I found I get a rather large reduction in SisSoftware Sandra Processor Multi-Core Efficiency bandwidth and a bit higher latency. Same with AIDA64 Extreme cache and memory test. :h34r-smi
> 
> Still can't get tRDWR lower, even tried most things on Auto, nada.
> 
> *Edit: Tested it again, tWRRD at 4 is better.* :glasses
> 
> 
> 
> Spoiler


No thanks. 2T is boring. I'll see if I can post with tWTRS 2 then follow the tRAS magic guide.


----------



## rares495

@Veii Managed to boot with tRDWR 8 and tWRRD 1. Passed 5min of Karhu with cache.

tWTRS 2 attempt was not successful, unfortunately. Might have posted with tWTRS 3 but I doubt it was gonna be stable.

I cannot go lower than tWR 10 no matter what I do. I think it's a BIOS limitation.


----------



## Saiger0

rares495 said:


> @Veii Managed to boot with tRDWR 8 and tWRRD 1. Passed 5min of Karhu with cache.
> 
> tWTRS 2 attempt was not successful, unfortunately. Might have posted with tWTRS 3 but I doubt it was gonna be stable.
> 
> I cannot go lower than tWR 10 no matter what I do. *I think it's a BIOS limitation*.


On my MSI x470 Gaming Pro Carbon the 1004b bios is buggy aswell. I can´t even run my 100% stable settings on this bios without it having the cold boot issue. Alot of users reprting that they can´t even use xmp.. :/ 
I´ll stick with stilts mod bios since it has been the most stable for me.


----------



## rares495

Saiger0 said:


> On my MSI x470 Gaming Pro Carbon the 1004b bios is buggy aswell. I can´t even run my 100% stable settings on this bios without it having the cold boot issue. Alot of users reprting that they can´t even use xmp.. :/
> I´ll stick with stilts mod bios since it has been the most stable for me.


Sorry to hear that. My BIOS is fine, I just can't set tWR as low as I'd like.

@Veii Checked my friend's Strix X570-E BIOS and he can't set tWR lower than 10 either. 32GB 3600C16 Trident Z Neo kit.


----------



## nick name

KedarWolf said:


> In the Spoiler is BIOS settings of what is passing HCI and Karhu, cache enabled. Don't be afraid to try 2T if 1T is unstable. Higher RAM frequencies it happens. :drum:
> 
> Note all the voltages on manual. :thumb:
> 
> Note: I have tWRRD at 1 as I found I get a rather large reduction in SisSoftware Sandra Processor Multi-Core Efficiency bandwidth and a bit higher latency. Same with AIDA64 Extreme cache and memory test. :h34r-smi
> 
> Still can't get tRDWR lower, even tried most things on Auto, nada.
> 
> *Edit: Tested it again, tWRRD at 4 is better.* :glasses
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Spoiler


You gotta screenshot the completed tests too.


----------



## rastaviper

Veii said:


> The reason for them is , so you start slowly getting away that tRCD WR 16 which bothers too much
> 
> With it there you would need to focus on timings like 14-14-16-15 or 14-15-16-14 to have a well working calculation
> 
> 15 same like 7, are very annoying numbers to work with, getting CL15 away would go a big way in future tightening progress
> 
> I purposely used higher tRFC soo you don't have to think about 4-5 potential desync locations
> 
> It might be slower, but you can focus on working away SCL , lowering tRCD WR and lowering tCL
> 
> 
> 
> Your ultimate goal is getting clean (no delay) tRAS transition, and then being able to use low tRC
> 
> Getting this first 3 timings correctly and tight (tCL, tRCD, tRP) is key for having anything after it function fine
> 
> having 7.5 value as multiplier, even calculated by ns purely - is a mess, soo i had to use high timings
> 
> 
> 
> This is your goal
> 
> I'm not focusing on benchmark settings, here no one cares for them
> 
> You can care for them after you get your ram stable - 24/7 is important
> 
> And a lot of bad timings will be 24/7 stable, because the board and now the cpu do autocorrect and add non readable delay to timings
> 
> Soo again, purpose of this is to get your rams in clean sync - later you can consider tighten them step by step
> 
> But having strange first 3 timings don't help anything, you'll only go into a rabbit hole of testing without fixing it first :ninja:
> 
> 
> 
> Oh, no all where for b-dies
> 
> The rules are universal , only what changes per IC is first 3 timings, and tRFC
> 
> SCL is more PCB focused than IC focused
> 
> 
> @rares495 & @KedarWolf
> 
> Always use tRFC 2 and 4 the one i write out - or if not clear via tRFC Calculator for *6, copy ns value with decimal and use in DRAM Calculator
> 
> I know i know "it's not used unless memory hits 85c"
> 
> But that's not the whole story
> 
> It isn't used directly - but it changes more than one part and it changes tREFI range
> 
> It changes timings, bank swapping and functions we have no access too
> 
> Always change it, that's my advice (i've seen differences on the HynixMFR timings)
> 
> - although it changes tiny bits +/- 1, soo you maaybe could ignore it if you want
> 
> 
> @kyo2020 tRFC 2 and 4 is never higher than tRFC
> 
> ultimately you calculate it via ns only - but you can use either my tRFC calculator or 1usmus DRAM calculator - Additional Calculator menu
> 
> ^ IF , you start to use tRFC 2 and 4 - if not, keep it identical to main tRFC


Thank you again for your valuable points.


Sent from my ONEPLUS A6003 using Tapatalk


----------



## Veii

rares495 said:


> I couldn't get tRDWR lower than 10 in any way so I just went back to 14-14-12-28-40, everything else on Auto and adjusted from there. The board automagically set tRDWR to 8 and tWRRD to 2 which goes against your rule. Tried 7-1 but no post. Tried SCL 4 + 6-3 and no post.
> 
> procODT still 36.9ohm and CAD_bus all 24 set by the board on Auto.


You can use tWRRD *4 or *2 , i haven't found *2 makes sense because both will be high and there is a rule that only one is allowed to be high
In case of <8 timings, it makes sense tWRRD 4 should work
Board else used Half tRCD +1 - which is common, nothing unexpected
DRAM Calculator goes the same way , but with tWRRD 1
Valid option 



rares495 said:


> @Veii Managed to boot with tRDWR 8 and tWRRD 1. Passed 5min of Karhu with cache.


Keep on working :thumb:
Bad set of this two will only result in no post - it behaves identical on intel
there might be better guides for this part, but the guide from me is made by me - need more learning in exceptions why DR needs it soo high
AMD to Intel
tRDWR -> tRRDR	
tWRRD -> tRRDD



rares495 said:


> I cannot go lower than tWR 10 no matter what I do. I think it's a BIOS limitation.


Yea has to be bios limitation
I suspect this SD DD values - i rly don't like them
Can you try the same experimenting with all 1 
SC SD DD = 1 1 1, 1 1 1
That works to combat instability 
1,5,5 1,7,7 always lead to better results for me



Saiger0 said:


> On my MSI x470 Gaming Pro Carbon the 1004b bios is buggy aswell. I can´t even run my 100% stable settings on this bios without it having the cold boot issue. Alot of users reprting that they can´t even use xmp.. :/
> I´ll stick with stilts mod bios since it has been the most stable for me.


I remember 1004B broke memory training for B-Dies
But it should be fine if you override them via the CBS PHY section 
To increase memory training delay to 10
People where upset, the board takes too much time to train - and the fixes break more than they help



rares495 said:


> @Veii Checked my friend's Strix X570-E BIOS and he can't set tWR lower than 10 either. 32GB 3600C16 Trident Z Neo kit.


For your friend, he has bios mods by Reous 
You can request there that he fixes it - same for tWTRS to go down to 2 tWRTL 6
And doublecheck if your SD DD values are unlocked down to 1 
Instead of down to 2 only


----------



## rares495

Veii said:


> You can use tWRRD *4 or *2 , i haven't found *2 makes sense because both will be high and there is a rule that only one is allowed to be high
> In case of <8 timings, it makes sense tWRRD 4 should work
> Board else used Half tRCD +1 - which is common, nothing unexpected
> DRAM Calculator goes the same way , but with tWRRD 1
> Valid option
> 
> Keep on working :thumb:
> Bad set of this two will only result in no post - it behaves identical on intel
> there might be better guides for this part, but the guide from me is made by me - need more learning in exceptions why DR needs it soo high
> AMD to Intel
> tRDWR -> tRRDR
> tWRRD -> tRRDD
> 
> Yea has to be bios limitation
> I suspect this SD DD values - i rly don't like them
> Can you try the same experimenting with all 1
> SC SD DD = 1 1 1, 1 1 1
> That works to combat instability
> 1,5,5 1,7,7 always lead to better results for me
> 
> I remember 1004B broke memory training for B-Dies
> But it should be fine if you override them via the CBS PHY section
> To increase memory training delay to 10
> People where upset, the board takes too much time to train - and the fixes break more than they help
> 
> For your friend, he has bios mods by Reous
> You can request there that he fixes it - same for tWTRS to go down to 2 tWRTL 6
> And doublecheck if your SD DD values are unlocked down to 1
> Instead of down to 2 only


It worked, but this has no impact on tWR. Still can't go lower than 10. At least my right side in Zen Timings looks amazing now lol.


----------



## nick name

rares495 said:


> It worked, but this has no impact on tWR. Still can't go lower than 10. At least my right side in Zen Timings looks amazing now lol.


Aaaaaaand no way is that stable.


----------



## rares495

nick name said:


> Aaaaaaand no way is that stable.


Yeah, probably not, but this is an amazing kit so you never know. 

Will leave karhu/hci over night to test that.


----------



## Veii

nick name said:


> Aaaaaaand no way is that stable.


Check my signature 
The hynixMFR timings where a great example of this method
It's a bit slower, but far more stable for awkward timings like you guys rock


----------



## nick name

Veii said:


> Check my signature
> The hynixMFR timings where a great example of this method
> It's a bit slower, but far more stable for awkward timings like you guys rock


I was looking at the GDM and the tRFC.


----------



## Veii

nick name said:


> I was looking at the GDM and the tRFC.


tRFC looks acceptable, but GDM off let's see 
it can run up to his kits


----------



## Joseph Mills

I was finally able to get my 4x16gb Dual-rank 3200C15 TridentZ B-die running at 3533Mhz CL16. I've only run the memtest on it for 15min (if anything is wrong, it usually catches it within the first 10 minutes).
All that aside, when I reboot, it shuts off once, and then boots normally (ram training I assume). 



Does this mean that the timings are off somewhere?


Is it bad for the system to reboot, turn off, back on again, and boot?


Thanks in advance!


----------



## Veii

Joseph Mills said:


> I was finally able to get my 4x16gb Dual-rank 3200C15 TridentZ B-die running at 3533Mhz CL16. I've only run the memtest on it for 15min (if anything is wrong, it usually catches it within the first 10 minutes).
> All that aside, when I reboot, it shuts off once, and then boots normally (ram training I assume).
> 
> 
> 
> Does this mean that the timings are off somewhere?
> 
> Is it bad for the system to reboot, turn off, back on again, and boot?
> 
> Thanks in advance!


Can we get a bit more information 
Which bios do you run ?
What settings where your last tried ones
(RTT value, cad_bus, voltages, procODT ?)

Memory training has issues on 1004B , but you can fix it by going into the AMD CBS menu and finding there the submenu PHY Memory Controller
People here will give you the exact location if you can't find it 
But it can be bad memory training or just wrong CAD_BUS values, which do influence memory training


----------



## Joseph Mills

Veii said:


> Can we get a bit more information
> Which bios do you run ?
> What settings where your last tried ones
> (RTT value, cad_bus, voltages, procODT ?)
> 
> Memory training has issues on 1004B , but you can fix it by going into the AMD CBS menu and finding there the submenu PHY Memory Controller
> People here will give you the exact location if you can't find it
> But it can be bad memory training or just wrong CAD_BUS values, which do influence memory training



You're right! Those details would be helpful.
I'm running a:
3800X on an Gigabyte Aorus Elite x570 - bios F12f
Mem Voltage set at 1.44v, but HWiNFO shows 1.46v



My Current values are:
ProcODT: 60

CAD_Bus: All Auto


ClkDrv: 30
AddrCmd: 20
CsOdt:20
CkeDrv:24


RttNom: 7
RttWr: 3
RttPark: 1


----------



## Veii

Joseph Mills said:


> You're right! Those details would be helpful.
> I'm running a:
> 3800X on an Gigabyte Aorus Elite x570 - bios F12f
> Mem Voltage set at 1.44v, but HWiNFO shows 1.46v
> 
> 
> 
> My Current values are:
> ProcODT: 60
> 
> CAD_Bus: All Auto
> 
> 
> ClkDrv: 30
> AddrCmd: 20
> CsOdt:20
> CkeDrv:24
> 
> 
> RttNom: 7
> RttWr: 3
> RttPark: 1


Alright, i see the issue 
First ClkDrvStrgh should be for dual rank between 48-120
You can start with 48-20-20-24 

ProcODT range after 1004B should be between 34-53 for dual rank 
And 28-32 for single rank units - procODT doesn't need to change with more dimms
the first value in CAD_BUS does the rest and the VDDD IOD line does main work for very high density kits
Drop procODT to 34.4Ohm , push at least 1.42v through the dimms
(a thaiphoon burner report would help on what PCB these dimms are and at what ns size the ICs are)
That's about it

Your procODT of 60 limits everything and requires at least 24-24-24-24 
in your case it does require at least 30-30-30-30 
Soo lower procODT please , so we can use X - 20 - 20 - 24 

vSOC optimally you can lower -25mV , instead of 1.1 down to 1.075
VDDP is correct, VDDG is correct


----------



## Hequaqua

rares495 said:


> It worked, but this has no impact on tWR. Still can't go lower than 10. At least my right side in Zen Timings looks amazing now lol.


What are you using to get those timing readings? If I may ask....


----------



## Joseph Mills

Veii said:


> Alright, i see the issue
> First ClkDrvStrgh should be for dual rank between 48-120
> You can start with 48-20-20-24
> 
> ProcODT range after 1004B should be between 34-53 for dual rank
> And 28-32 for single rank units - procODT doesn't need to change with more dimms
> the first value in CAD_BUS does the rest and the VDDD IOD line does main work for very high density kits
> Drop procODT to 34.4Ohm , push at least 1.42v through the dimms
> (a thaiphoon burner report would help on what PCB these dimms are and at what ns size the ICs are)
> That's about it
> 
> Your procODT of 60 limits everything and requires at least 24-24-24-24
> in your case it does require at least 30-30-30-30
> Soo lower procODT please , so we can use X - 20 - 20 - 24
> 
> vSOC optimally you can lower -25mV , instead of 1.1 down to 1.075
> VDDP is correct, VDDG is correct



Thanks!
This is where my settings are now (See attached)

Also, it rebooted nicely without the re-training on/off thing.
Lastly, I've included my Thaiphoon Burner reading.


----------



## Veii

Hequaqua said:


> What are you using to get those timing readings? If I may ask....


ZenTimings Reader , from the german community
Re-uploaded, but if you don't trust me i can look for the google drive link 

Also @rares495, @Joseph Mills is the perfect example that my tCRD /2 -1 method does work flawlessly 
I just don't seem to understand why you guys have it that high , at least why on dual rank it's that high :thinking:


----------



## Joseph Mills

Veii said:


> ZenTimings Reader , from the german community
> Re-uploaded, but if you don't trust me i can look for the google drive link
> 
> Also @*rares495* , @*Joseph Mills* is the perfect example that my tCRD /2 -1 method does work flawlessly
> I just don't seem to understand why you guys have it that high , at least why on dual rank it's that high :thinking:


 @Veii - Thanks for that Google sheet tRFC Calculator! I used your numbers. 

You are correct - I was able to run 277 on my current timings. I used your sheet to get my current tRFC numbers in hopes to get up to 3600Mhz (because I heard that tRFC scales with voltage, and wanted to keep voltage low). Do you have any suggestions to dial tRFC in on dual rank?


----------



## Veii

Joseph Mills said:


> @Veii - Thanks for that Google sheet tRFC Calculator! I used your numbers.
> 
> You are correct - I was able to run 277 on my current timings. I used your sheet to get my current tRFC numbers in hopes to get up to 3600Mhz (because I heard that tRFC scales with voltage, and wanted to keep voltage low). Do you have any suggestions to dial tRFC in on dual rank?


tRFC stays identical 
It stays identical because your timings are virtual values to simplify things
this values all generate themself by the MT/s speed and work as ns delays with 8 decimals

tRFC works in cycles
full cycles 16 as value
1/2 cycle 8 
1/4 = 4
1/8 = 2 as value

There is far more to this than what you see on the calculator and Yuri (1usmus) has faster values, because he abuses the cycle stacking method or so called forced refresh trigger method before the cells discharge
That way using far lower values than math would show it's possible
BUT - you need to test this, there is yet not clear math to skip all the testing

On the calculator you get them as accurate as possible , it should be "nearly" flawless so far
Doesn't matter where you input this ns value, as long as it's accurate to at least 3 decimals, the result should be fine

Nearly - because tRFC2 and tRFC4 use clean values as dividers and not math to have it perfect absolute perfect
it should be off by 0.000Xns value / but as boards autocorrect, this should be more accurate than using whole value ns values 

In order to lower tRFC , you need to work on your first 4 timings 
Key values are tRAS and then tRC after it
Important was first to lower SCL and then tRDWR as low as possible
tRP is very variable with voltage and time between tCL and tRCD 
Soo every IC manufacture will have different delays how long they need to discharge and charge back 
Every read command is a full cell discharge - soo the first 3 values vary with voltage and with IC manufacture 

The rest follows an universal pattern 
Of course bank density matters , but connection between them is universal
You never change only 1 timing - they minimum go in pairs if not in triplets
This explains it very simple:


Spoiler


----------



## Joseph Mills

Veii said:


> tRFC stays identical
> It stays identical because your timings are virtual values to simplify things
> this values all generate themself by the MT/s speed and work as ns delays with 8 decimals
> 
> tRFC works in cycles
> full cycles 16 as value
> 1/2 cycle 8
> 1/4 = 4
> 1/8 = 2 as value
> 
> There is far more to this than what you see on the calculator and Yuri (1usmus) has faster values, because he abuses the cycle stacking method or so called forced refresh trigger method before the cells discharge
> That way using far lower values than math would show it's possible
> BUT - you need to test this, there is yet not clear math to skip all the testing
> 
> On the calculator you get them as accurate as possible , it should be "nearly" flawless so far
> Doesn't matter where you input this ns value, as long as it's accurate to at least 3 decimals, the result should be fine
> 
> Nearly - because tRFC2 and tRFC4 use clean values as dividers and not math to have it perfect absolute perfect
> it should be off by 0.000Xns value / but as boards autocorrect, this should be more accurate than using whole value ns values
> 
> In order to lower tRFC , you need to work on your first 4 timings
> Key values are tRAS and then tRC after it
> Important was first to lower SCL and then tRDWR as low as possible
> tRP is very variable with voltage and time between tCL and tRCD
> Soo every IC manufacture will have different delays how long they need to discharge and charge back
> Every read command is a full cell discharge - soo the first 3 values vary with voltage and with IC manufacture
> 
> The rest follows an universal pattern
> Of course bank density matters , but connection between them is universal
> You never change only 1 timing - they minimum go in pairs if not in triplets
> This explains it very simple:
> 
> 
> Spoiler



Thanks! I'm trying to wrap my head around this.
I appreciate your help. You helped me get a stable 3533mhz CL16 tRFC 280 on my system!


----------



## Veii

Joseph Mills said:


> Thanks! I'm trying to wrap my head around this.
> I appreciate your help. You helped me get a stable 3533mhz CL16 tRFC 280 on my system!


This , is an old post about couple of personal rulesets (keep in mind the age part)
And the usual "testing steps" you go through when you increase frequency


----------



## rares495

nick name said:


> Aaaaaaand no way is that stable.


Well well welll. 4 hours of Karhu with cache.

@Veii Thanks again. 

As for Joseph's tRDWR, I think your method might only work for way looser timings. I don't know. What I use is already pretty far in the realm of stupid low.


----------



## Hequaqua

Veii said:


> ZenTimings Reader , from the german community
> Re-uploaded, but if you don't trust me i can look for the google drive link
> 
> Also @rares495, @Joseph Mills is the perfect example that my tCRD /2 -1 method does work flawlessly
> I just don't seem to understand why you guys have it that high , at least why on dual rank it's that high :thinking:


Oh I trust you....Thanks. I got it.

Here are my timings....my set of ram is 3466CL16 B Die. I'm not sure where I came up with these timings, but they have been rock solid on several bios and AGESA updates. I think they were a combo from the Calc and testing and changing things. I know they don't match the calc eithier safe/preset. My cpu has a pretty weak IF.....


----------



## Veii

rares495 said:


> Well well welll. 4 hours of Karhu with cache.
> 
> @Veii Thanks again.
> 
> As for Joseph's tRDWR, I think your method might only work for way looser timings. I don't know. What I use is already pretty far in the realm of stupid low.


I'm very happy it works
Yes these 4,4 6,6 did look awkward 
Unsure so far if it's worth it to increase or balance timings in the exchange of lower tRDWR 
because that does add a quite significant bump in higher bandwidth (the tRDWR part) and helps later to lower overall tRFC ~ but 1,1,1 1,1,1 does lower overall bandwidth :thinking:

It's good to know this worked out for you
Thank you too for all the testing, it helps in learning how other dimms behave with awkward timings :specool:


----------



## KedarWolf

Veii said:


> I'm very happy it works
> 
> 
> Spoiler
> 
> 
> 
> Yes these 4,4 6,6 did look awkward
> Unsure so far if it's worth it to increase or balance timings in the exchange of lower tRDWR
> because that does add a quite significant bump in higher bandwidth (the tRDWR part) and helps later to lower overall tRFC ~ but 1,1,1 1,1,1 does lower overall bandwidth :thinking:
> 
> It's good to know this worked out for you
> Thank you too for all the testing, it helps in learning how other dimms behave with awkward timings :specool:


The trick to tRDWR at 8 is tCWL at 14.

I'm running Karhu on the below. 1T still a no go.


----------



## rares495

Veii said:


> but 1,1,1 1,1,1 does lower overall bandwidth :thinking:


Maybe half a GB/s at most. And not always. That's what I'm seeing in my tests.


----------



## KedarWolf

Veii said:


> I'm very happy it works
> Yes these 4,4 6,6 did look awkward
> 
> 
> Spoiler
> 
> 
> 
> Unsure so far if it's worth it to increase or balance timings in the exchange of lower tRDWR
> because that does add a quite significant bump in higher bandwidth (the tRDWR part) and helps later to lower overall tRFC ~ but 1,1,1 1,1,1 does lower overall bandwidth :thinking:
> 
> It's good to know this worked out for you
> Thank you too for all the testing, it helps in learning how other dimms behave with awkward timings :specool:


Here's my Thaiphoon Burner.

I find it interesting it's a B1 Revision.


----------



## Veii

Hequaqua said:


> Oh I trust you....Thanks. I got it.
> 
> Here are my timings....my set of ram is 3466CL16 B Die. I'm not sure where I came up with these timings, but they have been rock solid on several bios and AGESA updates. I think they were a combo from the Calc and testing and changing things. I know they don't match the calc eithier safe/preset. My cpu has a pretty weak IF.....
> 
> View attachment 335806


Might want to tell the voltages and procODT you currently run - at which CAD_BUS values are you
1004B or 1003ABBA AGESA ?
Because you use GDM, keep in mind - every odd value will turn into even
Effectively you run 16-16-18-14-30-46 right now (which is an issue as tRFC should be then 32 as minimum)
Optimal tRFC would be 368-273-168 but you can run 322-239-147 too 
Lowest is 276, but first you have to fix your main 4 timings - as GDM enabled does mess everything up
Even if you don't see it - the behavior remains 
Oh also when you use GDM, tCL=tCWL

Let's try this first 








Key for now is to lower tRDWR and get that odd tRCD WR 17 away
Also to doublecheck your voltages

I actually found the original Github 
Sorry, seems like my version was a bit outdated
https://github.com/irusanov/ZenTimings/releases <- ZenTimings Official Source


----------



## Hequaqua

Veii said:


> Might want to tell the voltages and procODT you currently run - at which CAD_BUS values are you
> 1004B or 1003ABBA AGESA ?
> Because you use GDM, keep in mind - every odd value will turn into even
> Effectively you run 16-16-18-14-30-46 right now (which is an issue as tRFC should be then 32 as minimum)
> Optimal tRFC would be 368-273-168 but you can run 322-239-147 too
> Lowest is 276, but first you have to fix your main 4 timings - as GDM enabled does mess everything up
> Even if you don't see it - the behavior remains
> Oh also when you use GDM, tCL=tCWL
> 
> Let's try this first
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Key for now is to lower tRDWR and get that odd tRCD WR 17 away
> Also to doublecheck your voltages
> 
> I actually found the original Github
> Sorry, seems like my version was a bit outdated
> https://github.com/irusanov/ZenTimings/releases <- ZenTimings Official Source


OK.....think I have those corrected:









I running a static 4.2ghz on my 3700X. The SoC voltage is set at 1.075v in the bios. I see 1.056-1.063 via HWiNFO in Windows. Ram voltage is 1.380v. I believe that ProcODT/CAD_Bus are set to auto...which iirc(forgot to look), ProcODT is 60, and CAD_Bus are 24-24-24-24. I'm on version 1.0.0.4B

I ran Sisoft and compared it to the other timings. Seemed to be about the same, keep in mind that this version of SiSoft is the latest, and the old run was under the previous version. 

Thanks for the help so far....:thumb:


----------



## heptilion

Hi I have managed to get my ram stable at these settings. I feel like the voltages i need for this on the upper limit so would like some feedback on what i can do to lower it.

I tried running with recommended settings(with 1.496 voltages and the rest as suggested per calc) but can get karhu stable on 10,000% but fail on memtest at 120% everytime. So I am not sure what i can do to fix this. Should I try upping my dram voltage more? 

Any suggestions please


----------



## Veii

Hequaqua said:


> OK.....think I have those corrected:
> 
> View attachment 335888
> 
> 
> I running a static 4.2ghz on my 3700X. The SoC voltage is set at 1.075v in the bios. I see 1.056-1.063 via HWiNFO in Windows. Ram voltage is 1.380v. I believe that ProcODT/CAD_Bus are set to auto...which iirc(forgot to look), ProcODT is 60, and CAD_Bus are 24-24-24-24. I'm on version 1.0.0.4B
> 
> I ran Sisoft and compared it to the other timings. Seemed to be about the same, keep in mind that this version of SiSoft is the latest, and the old run was under the previous version.
> 
> Thanks for the help so far....:thumb:


procODT 60 is a big issue 
for Single rank kits you need to move around 28-32ohm 
on 1004B Agesa, optimal CAD_BUS starts with 24-20-20-24 
Single rank kits like between 24-40ohm for the first value, some up to 48ohm 
Dual Rank kits like 60-120ohm on the first value
less is better because more, generates heat
But it's recommendable to start at least with 24-20-20-24 
Then later once you start pushing very tight timings, up this to 30-20-20-24 or even 40-20-20-24 (SR)

check your VDDG and VDDP voltage
VDDP should stay at 900mV 
VDDG is always 50mv higher than VDDP , as bare minimum
vSOC is 50-75mV higher than VDDG as bare minimum 

if you have a dual CCD cpu and want to push per CCX overclock
You put VDDG CCD to higher value but not higher than vSOC 
and IOD to something between VDDP and VDDG 
Example starting preset:
CLDO_VDDP 900mV
CLDO_VDDG 950mV
VSOC 1000-1025mV 
* VDDG CCD 1000mV
* VDDG IOD 925mV
procODT 28ohm
CAD_BUS 24-20-20-24

vSOC can scale up without conflicts with others, but over 1.05v it's wasted heat
VDDG CCD and IOD nearly always can stay identical at 950mV 
* but dual CCD user can play around a bit
Just don't go 1.1v VSOC or higher , it's useless very useless / might be needed for XOC or 4800MT/s memory OC 
But it's useless 
The only reason to use 1.1v SOC is with strong loadline dropping it to 1.087v and with 1025mV VDDG (again 4500-4800MT/s range)

EDIT: @Hequaqua try if these settings are stable
Then try again with turned of GDM - up VDIMM to at least 1.42v
Optimally near 1.46v range
if you pass both GDM off and on
Try to lower SCL to 3 with tWRRD 2 and stresstest again


----------



## Veii

heptilion said:


> Hi I have managed to get my ram stable at these settings. I feel like the voltages i need for this on the upper limit so would like some feedback on what i can do to lower it.
> 
> I tried running with recommended settings(with 1.496 voltages and the rest as suggested per calc) but can get karhu stable on 10,000% but fail on memtest at 120% everytime. So I am not sure what i can do to fix this. Should I try upping my dram voltage more?
> 
> Any suggestions please


You overvolt so far nearly everything
Do you rock high per CCX OC , to need boost in VDDG ?
1900FLCK is reachable just with 950mV VDDG 
But you have to lower procODT too, else resistance is too high

What's been the reason for VDDP raise ?
it feels comfortable at 900mV 
If you want to use high voltages for benching 4.6-4.7 under cascade cooling
then you use VDDP 1.1 with VDDG (CCD) 1150, IOD 1125mV and vSOC 1.2v 
But that's not the case
VDDP can stay at 900mV without problems, even when you push 1025mV VDDG with 1.1v VSOC
(suggested is the starting preset above all on 950mV VDDG / keep your 40-20-20-24 CAD_BUS tho)

Start that way and try tRFC 350-260-160, tWRRD 3
Later you can try tRFC 300-223-137, tWR 12, tRTP 6
vDIMM is a bit high - do you have A0 or A1 PCBs (bottom left on thaiphoon burner report)


----------



## heptilion

Veii said:


> You overvolt so far nearly everything
> Do you rock high per CCX OC , to need boost in VDDG ?
> 1900FLCK is reachable just with 950mV VDDG
> But you have to lower procODT too, else resistance is too high
> 
> What's been the reason for VDDP raise ?
> it feels comfortable at 900mV
> If you want to use high voltages for benching 4.6-4.7 under cascade cooling
> then you use VDDP 1.1 with VDDG (CCD) 1150, IOD 1125mV and vSOC 1.2v
> But that's not the case
> VDDP can stay at 900mV without problems, even when you push 1025mV VDDG with 1.1v VSOC
> (suggested is the starting preset above all on 950mV VDDG / keep your 40-20-20-24 CAD_BUS tho)
> 
> Start that way and try tRFC 350-260-160, tWRRD 3
> Later you can try tRFC 300-223-137, tWR 12, tRTP 6
> vDIMM is a bit high - do you have A0 or A1 PCBs (bottom left on thaiphoon burner report)


I am running a 3800x on asus crosshair 8 hero mobo. Those settings i have written is how I managed to get my ram to be initially stable and have been running for a couple of months. But as you said everything is too high.

Now I am trying with lower vddp 900, vdg 1.025 and soc 1.1(hw info and bios read 1.087) with dram at 1.485(hw infor 1.496) but keep getting error on memtest at around 120%(single task) but passing karhu 10k. I have A1(10 layers) PCB as per thaiphoon report.


----------



## rares495

heptilion said:


> I am running a 3800x on asus crosshair 8 hero mobo. Those settings i have written is how I managed to get my ram to be initially stable and have been running for a couple of months. But as you said everything is too high.
> 
> Now I am trying with lower vddp 900, vdg 1.025 and soc 1.1(hw info and bios read 1.087) with dram at 1.485(hw infor 1.496) but keep getting error on memtest at around 120%(single task) but passing karhu 10k. I have A1 PCB as per thaiphoon report.


Remember to use Karhu RT with cache enabled, otherwise you can pass 100k and it would mean nothing. This way you're also testing the stability of your FCLK.


----------



## heptilion

rares495 said:


> Remember to use Karhu RT with cache enabled, otherwise you can pass 100k and it would mean nothing. This way you're also testing the stability of your FCLK.


It was on default for cache. I will change it to enabled. Keep RNG on default?

Thanks


----------



## rares495

heptilion said:


> It was on default for cache. I will change it to enabled. Keep RNG on default?
> 
> Thanks


Yes. No problem.


----------



## Hequaqua

Veii said:


> procODT 60 is a big issue
> for Single rank kits you need to move around 28-32ohm
> on 1004B Agesa, optimal CAD_BUS starts with 24-20-20-24
> Single rank kits like between 24-40ohm for the first value, some up to 48ohm
> Dual Rank kits like 60-120ohm on the first value
> less is better because more, generates heat
> But it's recommendable to start at least with 24-20-20-24
> Then later once you start pushing very tight timings, up this to 30-20-20-24 or even 40-20-20-24 (SR)
> 
> check your VDDG and VDDP voltage
> VDDP should stay at 900mV
> VDDG is always 50mv higher than VDDP , as bare minimum
> vSOC is 50-75mV higher than VDDG as bare minimum
> 
> if you have a dual CCD cpu and want to push per CCX overclock
> You put VDDG CCD to higher value but not higher than vSOC
> and IOD to something between VDDP and VDDG
> Example starting preset:
> CLDO_VDDP 900mV
> CLDO_VDDG 950mV
> VSOC 1000-1025mV
> * VDDG CCD 1000mV
> * VDDG IOD 925mV
> procODT 28ohm
> CAD_BUS 24-20-20-24
> 
> vSOC can scale up without conflicts with others, but over 1.05v it's wasted heat
> VDDG CCD and IOD nearly always can stay identical at 950mV
> * but dual CCD user can play around a bit
> Just don't go 1.1v VSOC or higher , it's useless very useless / might be needed for XOC or 4800MT/s memory OC
> But it's useless
> The only reason to use 1.1v SOC is with strong loadline dropping it to 1.087v and with 1025mV VDDG (again 4500-4800MT/s range)
> 
> EDIT:
> @Hequaqua try if these settings are stable
> Then try again with turned of GDM - up VDIMM to at least 1.42v
> Optimally near 1.46v range
> if you pass both GDM off and on
> Try to lower SCL to 3 with tWRRD 2 and stresstest again


Well........the first try was a disaster. Took me 30-40min just to get back into the bio. Even after clearing it via I/O switch, the jumper. I finally got it to post though. 

I'll try again in the morning, it's getting late here. Oh....btw way 30 is the lowest ProcODT I can set. Also, terminations settings RTT_Nom/RTT_RW/RTT_Park were all still on Auto I believe. I'm guessing those should have been Disabled/Disabled/RZZQ/5(48)?


----------



## heptilion

Ok It seems to be stable with 1.025vddg 0.900vddp and 1.112(hwinfo 1.1)vsoc. I had to up the dram voltage to 1.5v(hwinfo 1.512). Memtest ran for 750%(single thread). 

Testing .900vddp .95vddg and 1.1(hw info 1.087) with 1.5v(1.512hwinfo) and seems to be running stable atm. covered 800%(single thread) so far.

@Veii Does this mean I need high voltage for my ram to be stable with A1(10 layer) PCB?


----------



## KedarWolf

Veii said:


> You overvolt so far nearly everything
> Do you rock high per CCX OC , to need boost in VDDG ?
> 1900FLCK is reachable just with 950mV VDDG
> But you have to lower procODT too, else resistance is too high
> 
> 
> 
> Spoiler
> 
> 
> 
> What's been the reason for VDDP raise ?
> it feels comfortable at 900mV
> If you want to use high voltages for benching 4.6-4.7 under cascade cooling
> then you use VDDP 1.1 with VDDG (CCD) 1150, IOD 1125mV and vSOC 1.2v
> But that's not the case
> VDDP can stay at 900mV without problems, even when you push 1025mV VDDG with 1.1v VSOC
> (suggested is the starting preset above all on 950mV VDDG / keep your 40-20-20-24 CAD_BUS tho)
> 
> Start that way and try tRFC 350-260-160, tWRRD 3
> Later you can try tRFC 300-223-137, tWR 12, tRTP 6
> vDIMM is a bit high - do you have A0 or A1 PCBs (bottom left on thaiphoon burner report)



@Veii Can you tell me anything about my Trident Z Neo 2x16GB 16-16-16-36 3600 RAM?

Here's my Thaiphoon Burner.

I find it interesting it's a B1 Revision.


----------



## Satanello

Hello, I'm trying to optimize ram timings but i need some help.
My system spec: Msi MEG X570 ACE bios 1.80; Ryzen 3900X cooled with CM ML240R RGB; 2x16Gb Gskill SniperX 3600 C19 (Dual rank Hynix CJR ICs)
Here you can see a Taiphoon Burner screenshot: 


What I've done: I tried 1usmus settings from calculator but I'm not able to use all the suggested settings and I'm using a Vdimm 1.38V (bios setting, but hwinfo say 1,4V).

To reduce tRCDWR from 20 to 19 i should add 0,2V to Vdimm (1,4V bios setting, hwinfo read 1,42V).

procODT: 60
RTT_NOM: OFF
RTT_WR:80
RTT_PARK: 240

CAD_BUS
ClkDrv: 24
AddrCmdDrv: 20
CsOdtDrv: 20
CkeDrv: 24

Voltage settings:
Vcore: auto
VSoc: auto
VDDP: 0,9V
VDDG CCD: 1,0V
VDDG IOD: 1,0V

Thanks in advance 

EDIT: Veii I used your calculator and I'm testing the modified tRFC values (560-416-256)


----------



## nick name

rares495 said:


> Well well welll. 4 hours of Karhu with cache.
> 
> @Veii Thanks again.
> 
> As for Joseph's tRDWR, I think your method might only work for way looser timings. I don't know. What I use is already pretty far in the realm of stupid low.


Oooooh how exciting. How long did you let it run?

What are you voltages and resistances?


----------



## rares495

nick name said:


> Oooooh how exciting. How long did you let it run?
> 
> What are you voltages and resistances?


Got a single error at 4h 20min. Coverage was over 22k, which is something you'd never reach with HCI because I never let HCI run more than 8-12h and the coverage then is nowhere near 22000%, more like 1500-1700%. I consider this 24/7 stable until I get a random BSOD in Windows/Games.

DRAM voltage is 1.5V in BIOS and 1.52V in HWinfo. VDDP 0.900V, VDDG IOD/CCD 0.950V, SOC voltage 1.104V in HWInfo. procODT 36,9ohm, CAD_bus 60-24-24-24.


----------



## nick name

rares495 said:


> Got a single error at 4h 20min. Coverage was over 22k, which is something you'd never reach with HCI because I never let HCI run more than 8-12h and the coverage then is nowhere near 22000%, more like 1500-1700%. I consider this 24/7 stable until I get a random BSOD in Windows/Games.
> 
> DRAM voltage is 1.5V in BIOS and 1.52V in HWinfo. VDDP 0.900V, VDDG IOD/CCD 0.950V, SOC voltage 1.104V in HWInfo. procODT 36,9ohm, CAD_bus 60-24-24-24.


For whatever reason I get much more DRAM voltage droop (at least as HWiNFO reports) than I did with my 2700X. It was pretty much non-existent with the 2700X. 1.5V droops to 1.48V and it wasn't something I noticed during my initial testing. Makes me wonder if it may have been the culprit for some of my overnight test errors.


----------



## rares495

nick name said:


> For whatever reason I get much more DRAM voltage droop (at least as HWiNFO reports) than I did with my 2700X. It was pretty much non-existent with the 2700X. 1.5V droops to 1.48V and it wasn't something I noticed during my initial testing. Makes me wonder if it may have been the culprit for some of my overnight test errors.


I never checked this but it could be the cause of my error as well.


----------



## pegadroid

TwilightRavens said:


> A lot of X570 boards have a daisy chain memory configuration, which basically means it’ll only really clock well with two sticks and not 4, if you need 32GB it might be better to look at a 2 x 16GB rather than 4 x 8GB. This kit, while pricey is b-die: https://www.newegg.com/product/N82E16820232860?m_ver=1


all G.SKILL - F4-3600C16D-32GTZN using samsung b-die?


----------



## KedarWolf

pegadroid said:


> all G.SKILL - F4-3600C16D-32GTZN using samsung b-die?


That's the kit I have.


----------



## pegadroid

KedarWolf said:


> That's the kit I have.


F4-3600C16D-32GTZN or F4-3600C16Q-32GTZN?

when i buy this F4-3600C16D-32GTZN I will definitely get samsung B-die right?
https://www.tokopedia.com/linecomp/memory-g-skill-f4-3600c16d-32gtzn-trident-z-neo-32gb-2x16gb-ddr4


----------



## KedarWolf

pegadroid said:


> F4-3600C16D-32GTZN or F4-3600C16Q-32GTZN?
> 
> when i buy this F4-3600C16D-32GTZN I will definitely get samsung B-die right?
> https://www.tokopedia.com/linecomp/memory-g-skill-f4-3600c16d-32gtzn-trident-z-neo-32gb-2x16gb-ddr4


F4-3600C16D-32GTZN

2x16GB, not the 4x8GB F4-3600C16Q-32GTZN

Edit: The F4-3600C16D-32GTZN will be b-die.

The below is Hynix I think, the 16-19-19-39 3600.

G.SKILL Trident Z Neo (For AMD Ryzen) Series 16GB (2 x 16GB) 288-Pin RGB DDR4 SDRAM DDR4 3600 (PC4 28800) Desktop Memory Model F4-3600C16D-32GTZNC

DDR4 3600 (PC4 28800)
Timing 16-19-19-39
CAS Latency 16
Voltage 1.35V
Compatible with AMD Ryzen 3000 Series CPUs & AMD X570 Motherboards


----------



## pegadroid

KedarWolf said:


> F4-3600C16D-32GTZN
> 
> 2x16GB, not the 4x8GB F4-3600C16Q-32GTZN
> 
> Edit: The F4-3600C16D-32GTZN will be b-die.
> 
> The below is Hynix I think, the 16-19-19-39 3600.
> 
> G.SKILL Trident Z Neo (For AMD Ryzen) Series 16GB (2 x 16GB) 288-Pin RGB DDR4 SDRAM DDR4 3600 (PC4 28800) Desktop Memory Model F4-3600C16D-32GTZNC
> 
> DDR4 3600 (PC4 28800)
> Timing 16-19-19-39
> CAS Latency 16
> Voltage 1.35V
> Compatible with AMD Ryzen 3000 Series CPUs & AMD X570 Motherboards


Ok, thank you
tomorrow I will buy F4-3600C16D-32GTZN 16-16-16-36, 1.35V
------------------------
btw, mine all core 4.3ghz too. but 3900x :specool:at 1,200 llc lvl 4 asus strix x570 e


----------



## KedarWolf

rares495 said:


> I never checked this but it could be the cause of my error as well.


Do you peeps have HCI MemTest Pro 7.0, the newest version? and a 3950x?

If you don't and you bought it in the last year, they'll email you a free upgrade.

If you do, put this MemTest helper file in the folder with the MTPclassic.exe file and run it. Or you can just try renaming your MemTest.exe to MTPclassic.exe, sometimes that works.

It runs MemTest Pro 32 times for a 3950x, once for each thread and spaces them evenly on the screen. And it allocates each running Memtest instance to its own thread, so like the first one is using only the first thread, second using only second thread, etc. Uses about 25.5GB of RAM all running.

You can check this by opening task manager, right-click on one MemTest.exe, go to Details, Set Affinity, see the thread it's on.

It's the absolute best way to run MemTest.

I can compile an .exe for say a 3900x or whatever CPU you have as well.

All credit goes to @GeneO who wrote this script. Rep him, not me, there is no way I could write this kind of thing myself, just good enough at math logic to edit it for our needs.


----------



## yrelbirb

hi people, i've a weird issue. im currently running 2700x 4.1 ghz @1.29v with a gigabyte b450 gaming x board.

i have my micron b-die kits at 1.36v 3200 mhz cl14-20-20-36-56 timings, along with some other tightened subtimings. it passed %2200 hci memtest (i didnt take a pic but i will run the test again overnight). but before i set up on these timings and stability, i need to fix a potential problem

when i disable global c states and cool and quiet; my latency goes up, it hovers between 70.5-71.5 ns. today, i left c-states and cool and quiet auto, and voila, my latency is back to 68-69 ns range.

what's the catch here

my problem with c-states is it makes my overclock unstable on intel burn test. so should i consider my overclock bad? i tried even 1.36v for vcore but still IBT stopped at 3rd 4th run, saying my system is unstable. i think 1.36v should be enough for 4.1 ghz, no? even at 1.29v, without c-states, i managed to pass countless hours of various stress tests so i figured c-states messed up my overclock. but in the same time, enabling c-states for some reason, makes my ram latency go lower.

so what's the catch and what might be the problem here? i really wonder 

--

https://www.reddit.com/r/overclocki...zen_and_global_cstates_affecting_ram_latency/

this ryzen friend apparently have the exact same issue i have. you can read his post too, if i was unclear (im not native english speaker so sorry for any misunderstandings)


----------



## Veii

pegadroid said:


> btw, mine all core 4.3ghz too. but 3900x :specool: at 1,200 llc lvl 4 asus strix x570 e


1.2v VSOC or vCore 


yrelbirb said:


> hi people, i've a weird issue. im currently running 2700x 4.1 ghz @1.29v with a gigabyte b450 gaming x board.
> 
> i have my micron b-die kits at 1.36v 3200 mhz cl14-20-20-36-56 timings, along with some other tightened subtimings. it passed %2200 hci memtest (i didnt take a pic but i will run the test again overnight). but before i set up on these timings and stability, i need to fix a potential problem
> 
> when i disable global c states and cool and quiet; my latency goes up, it hovers between 70.5-71.5 ns. today, i left c-states and cool and quiet auto, and voila, my latency is back to 68-69 ns range.
> 
> what's the catch here
> 
> my problem with c-states is it makes my overclock unstable on intel burn test. so should i consider my overclock bad? i tried even 1.36v for vcore but still IBT stopped at 3rd 4th run, saying my system is unstable. i think 1.36v should be enough for 4.1 ghz, no? even at 1.29v, without c-states, i managed to pass countless hours of various stress tests so i figured c-states messed up my overclock. but in the same time, enabling c-states for some reason, makes my ram latency go lower.
> 
> so what's the catch and what might be the problem here? i really wonder


If your system becomes unstable under AVX loadsand voltage drops, it's LLC
keep in mind, on your gigabyte boards - you always have an offset of 0.1v between put in and reality
it's a hardware issue that affects all 3xx and 4xx boards including X399 Designare
Only the X470 K7 and Gaming 5 where not affected
Soo don't trust the voltage readout 

Is there any reason why you run fixed allcore instead of PBO ?
at what vSOC is this , and what procODT ?

Grab LinpackXtreme 1.1.1 (check the version number) and grab OCCT Beta 
for finetuning LLC
after you found your lowest voltage to be not only SSE but also AVX2 stable, put +2 steps onto it, if you ever want to run anything over 3400MT/s 
vSOC can stay under 1.05v , depends on your current memory OC

Also about 2nd gen, don't go over AGESA 1003ABBA so far
Else just wait for the new agesa~

EDIT:
2nd part of the question
Cool 'n Quiet can disable not only downclocking but also boosting behaviour, same as C-States would 
But the loss in latency likely is just instability


----------



## yrelbirb

Veii said:


> 1.2v VSOC or vCore
> 
> If your system becomes unstable under AVX loadsand voltage drops, it's LLC
> keep in mind, on your gigabyte boards - you always have an offset of 0.1v between put in and reality
> it's a hardware issue that affects all 3xx and 4xx boards including X399 Designare
> Only the X470 K7 and Gaming 5 where not affected
> Soo don't trust the voltage readout
> 
> Is there any reason why you run fixed allcore instead of PBO ?
> at what vSOC is this , and what procODT ?
> 
> Grab LinpackXtreme 1.1.1 (check the version number) and grab OCCT Beta
> for finetuning LLC
> after you found your lowest voltage to be not only SSE but also AVX2 stable, put +2 steps onto it, if you ever want to run anything over 3400MT/s
> vSOC can stay under 1.05v , depends on your current memory OC
> 
> Also about 2nd gen, don't go over AGESA 1003ABBA so far
> Else just wait for the new agesa~
> 
> EDIT:
> 2nd part of the question
> Cool 'n Quiet can disable not only downclocking but also boosting behaviour, same as C-States would
> But the loss in latency likely is just instability


PROOCDT is 53.3 and vsoc is 1.025 

sadly i have no ways of setting the LLC

i also tried 1.32v 4 ghz all core overclock and disabled c-states, result is same again; latency is 71 ns

cpu itself uses 1.32v 4 ghz in stock boost so it cannot be about stability, or if its, i dont know how it is related really.1.32v should've been plenty enough for 4 ghz, no?

for your question, i dont like constant 1.45v+ on my cpu. i read amd_Robert's posts as well but im not convinved. his "idle" definition does not suit my "idle" definition. his idle seems to be "close everything, dont use anything". my idle definition is, using chrome, using discord and such. and when im doing these things, like for 3 hours, then i go check hwinfo and i read average 1.43v on my cpu. sorry but im not cool with that. i dont want to use coreboost, pbo or xfr and such

---

1.32v 4 ghz (it cant be unstable, its stock vcore and stock boost speed) and C-state disabled;

https://prnt.sc/rr4pcs

1.32v 4 ghz completely same settings, just C-state enabled;

https://prnt.sc/rr4rl7


----------



## Veii

yrelbirb said:


> PROOCDT is 53.3 and vsoc is 1.025
> 
> sadly i have no ways of setting the LLC
> 
> i also tried 1.32v 4 ghz all core overclock and disabled c-states, result is same again; latency is 71 ns
> 
> cpu itself uses 1.32v 4 ghz in stock boost so it cannot be about stability, or if its, i dont know how it is related really.1.32v should've been plenty enough for 4 ghz, no?
> 
> for your question, i dont like constant 1.45v+ on my cpu. i read amd_Robert's posts as well but im not convinved. his "idle" definition does not suit my "idle" definition. his idle seems to be "close everything, dont use anything". my idle definition is, using chrome, using discord and such. and when im doing these things, like for 3 hours, then i go check hwinfo and i read average 1.43v on my cpu. sorry but im not cool with that. i dont want to use coreboost, pbo or xfr and such
> 
> ---
> 
> 1.32v 4 ghz (it cant be unstable, its stock vcore and stock boost speed) and C-state disabled;
> 
> https://prnt.sc/rr4pcs
> 
> 1.32v 4 ghz completely same settings, just C-state enabled;
> 
> https://prnt.sc/rr4rl7


Check if you can pass LinX 1.1.1 and OCCT Beta medium dataset 30min & small dataset AVX2 30min
If you can't pass neither of these tests, your OC is usntable
Just again you have an 0.1v offset between real voltage and read out voltage 
The 2700X has a FIT module inside, the cpu knows it's sillicon healthy
Sure it doesn't change it's frequency every 5ms like 3rd gen
But it's intelligent enough to not overvolt uselessly 

A word on maximum voltage
12nm can boost up to 1.48v without issues - 3rd gen can do too, but it has a big exception
staying near the 1.42v mark is a common usecase for a boosting CPU
You should need about 1.28v for 4Ghz, and near 1.32v for 4.1 - but 4.1 is not as easy to hit as PBO 4.3 with 4.1 allcore under AVX
There is a big difference

Idle, hmm discord depends on if with HW rendering or not, is not an easy to run program
Chrome even more harsh
The issue for boosting wake up calls shouldn't be both of these tools however
Which average voltage do you read 
in order to be sure about your actual applied voltage you need a multimeter or just take my word
Again offset hardware issue on these boards 

There is something you can keep in mind to be a less worried
- Voltage can be even 1.6v , if there is no load, the voltage doesn't harm - full load voltage is important 
- 2nd gen boosting ranges are around 1.48v which is a common thing, for their behavior 
- and your board has issues with the voltage readout, hwinfo only knows what it is told to know 

You might want to check if it supports it, VRM readout - as VR IN sensors 
Or just sell the board and get something else to stay calm minded
There is not much to help against actual hardware flaws
Well at the end, you can just measure it yourself - but i wouldn't worry all too much
PBO with an offset and fixed PPT,TDC,EDC rating was what i found to work the best on 2nd gen and run far cooler


----------



## yrelbirb

Veii said:


> Check if you can pass LinX 1.1.1 and OCCT Beta medium dataset 30min & small dataset AVX2 30min
> If you can't pass neither of these tests, your OC is usntable
> Just again you have an 0.1v offset between real voltage and read out voltage
> The 2700X has a FIT module inside, the cpu knows it's sillicon healthy
> Sure it doesn't change it's frequency every 5ms like 3rd gen
> But it's intelligent enough to not overvolt uselessly
> 
> A word on maximum voltage
> 12nm can boost up to 1.48v without issues - 3rd gen can do too, but it has a big exception
> staying near the 1.42v mark is a common usecase for a boosting CPU
> You should need about 1.28v for 4Ghz, and near 1.32v for 4.1 - but 4.1 is not as easy to hit as PBO 4.3 with 4.1 allcore under AVX
> There is a big difference
> 
> Idle, hmm discord depends on if with HW rendering or not, is not an easy to run program
> Chrome even more harsh
> The issue for boosting wake up calls shouldn't be both of these tools however
> Which average voltage do you read
> in order to be sure about your actual applied voltage you need a multimeter or just take my word
> Again offset hardware issue on these boards
> 
> There is something you can keep in mind to be a less worried
> - Voltage can be even 1.6v , if there is no load, the voltage doesn't harm - full load voltage is important
> - 2nd gen boosting ranges are around 1.48v which is a common thing, for their behavior
> - and your board has issues with the voltage readout, hwinfo only knows what it is told to know
> 
> You might want to check if it supports it, VRM readout - as VR IN sensors
> Or just sell the board and get something else to stay calm minded
> There is not much to help against actual hardware flaws
> Well at the end, you can just measure it yourself - but i wouldn't worry all too much
> PBO with an offset and fixed PPT,TDC,EDC rating was what i found to work the best on 2nd gen and run far cooler


hmm i will try linx 1.1.1.1

so my question is, if it passes linx 1.1.1.1 without c-states but fails with c-states does it mean my oc is unstable? how so?

https://prnt.sc/rr5ce3

how many times linpack?

nevermind i began small avx2 occt beta with C-states disabled

then i will try with C-states enabled

btw, i still didn'T get why latency is 2-3 ms less with c-states on

if its about unstability, then why did 1.32v 4 ghz still gave latency difference with c-states enabled?

surely this cpu shouldnt fail 1.32v 4 ghz with any avx load (unless the board is really crappy and if thats the case i will return it)


----------



## KedarWolf

Veii said:


> 1.2v VSOC or vCore
> 
> If your system becomes unstable under AVX loadsand voltage drops, it's LLC
> keep in mind, on your gigabyte boards - you always have an offset of 0.1v between put in and reality
> it's a hardware issue that affects all 3xx and 4xx boards including X399 Designare
> Only the X470 K7 and Gaming 5 where not affected
> Soo don't trust the voltage readout
> 
> 
> 
> Spoiler
> 
> 
> 
> Is there any reason why you run fixed allcore instead of PBO ?
> at what vSOC is this , and what procODT ?
> 
> Grab LinpackXtreme 1.1.1 (check the version number) and grab OCCT Beta
> for finetuning LLC
> after you found your lowest voltage to be not only SSE but also AVX2 stable, put +2 steps onto it, if you ever want to run anything over 3400MT/s
> vSOC can stay under 1.05v , depends on your current memory OC
> 
> 
> Also about 2nd gen, don't go over AGESA 1003ABBA so far
> Else just wait for the new agesa~
> 
> EDIT:
> 2nd part of the question
> Cool 'n Quiet can disable not only downclocking but also boosting behaviour, same as C-States would
> But the loss in latency likely is just instability


On my 3950x my latency goes up from 62 to 62.5 with C-States and Cool 'N Quiet disabled as well. 

Edit: About PBO Boost.

This what I found with BIOS CCX overclocking and PBO Boost using buildzoid settings.

With on Offset on both CPU and CDO voltages, with C-States and Cool 'N Quiet enabled, my idle voltages while watching Twitch on Chrome are very low. 

When running the x265 benchmark at 4K with warmer ambient temps, all my cores hover around 74C, I get a score of just over 30FPS.

With PBO Boost using the buildzoid suggested settings, C_States and Cool 'N Quiet disabled, while running x265 at 4K I get around 84C temps every core and just over 28FPS.

I think I'm going to stick to CCX with Offsets.


----------



## Veii

yrelbirb said:


> hmm i will try linx 1.1.1.1
> 
> so my question is, if it passes linx 1.1.1.1 without c-states but fails with c-states does it mean my oc is unstable? how so?
> 
> https://prnt.sc/rr5ce3
> 
> how many times linpack?
> 
> nevermind i began small avx2 occt beta with C-states disabled
> 
> then i will try with C-states enabled
> 
> btw, i still didn'T get why latency is 2-3 ms less with c-states on
> 
> if its about unstability, then why did 1.32v 4 ghz still gave latency difference with c-states enabled?
> 
> surely this cpu shouldnt fail 1.32v 4 ghz with any avx load (unless the board is really crappy and if thats the case i will return it)


The 2700X can run 1.28v 4.3 with ease but boosts to 4.5 near 1.45v under pbo, OC03 preset


Spoiler














linx, 20 rounds, allcore, no sleep, no hwmonitor
you shouldn't disable any of these
it has to downboost in order to behave fine on AVX and AVX2 offset
You also get latency differences when the cpu downclocks because AIDA's test is single core only 
and ultimately connection to Infinity Fabric are more important 
^ which means, use SiSandra for testing not aida64


----------



## Veii

KedarWolf said:


> On my 3950x my latency goes up from 62 to 62.5 with C-States and Cool 'N Quiet disabled as well.
> 
> Edit: About PBO Boost.
> 
> This what I found with BIOS CCX overclocking and PBO Boost using buildzoid settings.
> 
> With on Offset on both CPU and CDO voltages, with C-States and Cool 'N Quiet enabled, my idle voltages while watching Twitch on Chrome are very low.
> 
> When running the x265 benchmark at 4K with warmer ambient temps, all my cores hover around 74C, I get a score of just over 30FPS.
> 
> With PBO Boost using the buildzoid suggested settings, C_States and Cool 'N Quiet disabled, while running x265 at 4K I get around 84C temps every core and just over 28FPS.
> 
> I think I'm going to stick to CCX with Offsets.


Yea no, pbo on 3rd gen makes no sense to use explained here:
https://www.overclock.net/forum/13-...membench-0-8-dram-bench-689.html#post28388302
At least not right now 
per CCX with a low voltage runs well enough - but you need to know your safe allcore voltage 
the offset causes clock stretching still - after some updates it should be better


----------



## KedarWolf

Veii said:


> Yea no, pbo on 3rd gen makes no sense to use explained here:
> https://www.overclock.net/forum/13-...membench-0-8-dram-bench-689.html#post28388302
> At least not right now
> per CCX with a low voltage runs well enough - but you need to know your safe allcore voltage
> the offset causes clock stretching still - after some updates it should be better


I get about 1.256v VR VOUT when stress testing my CPU, much lower on idle of course.


----------



## yrelbirb

Veii said:


> The 2700X can run 1.28v 4.3 with ease but boosts to 4.5 near 1.45v under pbo, OC03 preset
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> linx, 20 rounds, allcore, no sleep, no hwmonitor
> you shouldn't disable any of these
> it has to downboost in order to behave fine on AVX and AVX2 offset
> You also get latency differences when the cpu downclocks because AIDA's test is single core only
> and ultimately connection to Infinity Fabric are more important
> ^ which means, use SiSandra for testing not aida64


i think you dont get me... i say latency is lesser when i actually enable C-states. its worse when c-states are disabled. not the other way around 

here's occt beta with your settings;

https://prnt.sc/rr5zya

this is with C-states disabled (aka 71 ns latency)

i enable c-states and it becomes 68 ns. i will test with c-states on as well (it will probably crash or give errors)

in theory, c-states disabled actually should give lesser latency, no? i have no quarrel with c-states. i can enable or disable it. enabling it is actually beneficial for me, lower power usage and apparently, lower latency. but it seems to disrupt my all core overclock for some reason (will see if that error IBT gives is exclusive to it or will it behave the same with linx as well)

i will try sisandra as well. but im sure it will have the same latency penalty with c-states disabled. something's very wrong with this mobo

here's sisandra latency with c-states enabled
https://prnt.sc/rr685o

i will return back to you after linextreme test


----------



## Veii

@yrelbirb , to me it makes sense 
Latency is just access time - but AIDA64 latency doesn't tell the whole story 
i ment SiSandra Multi-Core efficiency test
the graph under detailed result and at best the whole log, so you see the maximum inter-core latency and inter-CCX latency
Oh at the filter option at the bottom, disable online results or filter by local results only


----------



## yrelbirb

Veii said:


> @yrelbirb , to me it makes sense
> Latency is just access time - but AIDA64 latency doesn't tell the whole story
> i ment SiSandra Multi-Core efficiency test
> the graph under detailed result and at best the whole log, so you see the maximum inter-core latency and inter-CCX latency
> Oh at the filter option at the bottom, disable online results or filter by local results only


hello

i ran linpack extreme 1.1.1 for 20 runs at 10 gb no errors found. but as long as test is finished, result screen has gone 

https://prnt.sc/rr759t

i guess its fine now? i upped the vcore to +0.104 offset before running the test as well. i also enabled c-states for the test, same for cool and quiet too. but cpu never clocks down due to the ratio i guess. i dont know how to make it downclock. or do i need to? vcore seems to fall to values like 0.50v or something like that but cpu clock always same. is it okay?

how can i reach to the past result? is it gone? i can swear it was no error and almost all the runs ended about at 150 sec (took a total of 50 min)

so i should use the system with c-states enabled? can low vcore but fixed clock speed be problematic?

another question what power plan should i use with my current overclock_? or does it even matter_?

https://prnt.sc/rr77y8

and this is my currrent latency. a latench that i cannot not even dream of with c-states disabled, for some weird reason

--

here's my efficency results, no idea how to comment on them though

an extra question: in general, i thought overclockers always disbled c-states and such. so if it passed linpack 1.1.1 20 times, can i be at least assume that it wont ruin my cpu/or ruin stability in general for at least gaming purposes? its really weird seeing 0.540vcore accompanied with 4.1 ghz so i wondered if something's wrong

core power usage and cpu speeds;

https://prnt.sc/rr7faq

https://prnt.sc/rr7ffg

cpuz shows 0.50 and such voltages from time to time as well (when pc at idle)

so its ok i guess? i both retain better latency and more guaranteed stability and lower power consumption at idler states. no?_ i still didnt get why aida64 latency gets higher with c states disabled though

--

btw, these are my latest timings (you know i decided to settle on 3200 mt/s and im content on that. any comments on timings again? i think you asked me once to get SClL values to 2. for some reason they did stabilize

https://prnt.sc/rr7s2q

these timings past %2200 in hci memtest but i will continue to test more. is there any room for tightening yet?


----------



## yrelbirb

good news, i managed to get rid of stupid offset

i found pstate overclocking in bios

i can now set an "exact" voltage

;

https://prnt.sc/rr8quv

my psate0 adjustment;

https://prnt.sc/rr8r1k

clocks only go max 4.1 ghz just like i wanted and downclocks when it needs to;

https://prnt.sc/rr8r3u

--

only nitpick is; vcore sees very low values (thanks to c states i guess), but SVI2 TFN seems to be set at the p0 voltage (its probably bios bug again)


----------



## pegadroid

KedarWolf said:


> F4-3600C16D-32GTZN
> 
> 2x16GB, not the 4x8GB F4-3600C16Q-32GTZN
> 
> Edit: The F4-3600C16D-32GTZN will be b-die.
> 
> The below is Hynix I think, the 16-19-19-39 3600.
> 
> G.SKILL Trident Z Neo (For AMD Ryzen) Series 16GB (2 x 16GB) 288-Pin RGB DDR4 SDRAM DDR4 3600 (PC4 28800) Desktop Memory Model F4-3600C16D-32GTZNC
> 
> DDR4 3600 (PC4 28800)
> Timing 16-19-19-39
> CAS Latency 16
> Voltage 1.35V
> Compatible with AMD Ryzen 3000 Series CPUs & AMD X570 Motherboards


Finally i have G Skill F4-3600C16D-32GTZN and yes this kit is Samsung B-die :specool:, and run XMP very smooth, thanks you man
is it safe when using 1.48v for dram voltage? using timing cl14?
what's the limit, temp or voltage dram?



Veii said:


> 1.2v VSOC or vCore


vcore 1.2 V llc lvl 4, = 1.192 V


----------



## Veii

yrelbirb said:


> good news, i managed to get rid of stupid offset
> 
> i found pstate overclocking in bios
> 
> i can now set an "exact" voltage
> 
> ;
> 
> https://prnt.sc/rr8quv
> 
> my psate0 adjustment;
> 
> https://prnt.sc/rr8r1k
> 
> clocks only go max 4.1 ghz just like i wanted and downclocks when it needs to;
> https://prnt.sc/rr8r3u
> --
> only nitpick is; vcore sees very low values (thanks to c states i guess), but SVI2 TFN seems to be set at the p0 voltage (its probably bios bug again)


Yes that's what i've been doing on the 1700X 
Pstate OC
disable anything under 3-6 and disable EDC Throttling if you have the cooling ability 
EDC throttling does hang up the system on a small error mid windows - no EDC throttling keeps it alive till it fully shuts-down on instability
disabled runs more smooth and scores are higher, as it isn't throttling too early
yes, focus on tDie temp and SVI 2 voltage 

With that enable cool and quiet in the main OC menu under CPU Features
set it to P2 if it allows you and disable everything from P3 to P7
That way it will downclock to 700mhz if needed, and you aren't bugging it out
It's a design issue when you have an allcore, that it doesn't throttle frequency nor voltage - i think it's intentional to annoy us ^^'

Under AMD CBS, if you have OC presets 00-04, use these


Spoiler














Else fix CLDO_VDDP voltage under NBIO or DF to 700mV, enable memory interleaving (512), hash interleaving, both L1 L2 prefetcher settings under CPU Common settings and set cTDP to 300W just to lift some limits 
Memory Clear also to disable

Under CBS->NBIO you can set SOC VID
For your usecase it's better to fix it there (first put it on the main OC menu on auto)
This one is written in HEX, soo i've attached couple of screenshots with voltage examples


Spoiler






















Attached is Performance Bias from the Crosshair Hero's - as you likely don't have these options in the bios
Use CB Gentle for 24/7 - it should lower communication latency to Infinity Fabric and also lower Memory latency a bit
This here is your goal:


Spoiler












I'm sorry for the bad picture
It was one of the few things i had left from the client - picture wasn't made by me


L1 bandwidth over 1000GB/S
L2 at least 900 on Read & Copy
L3 at least >400-410 on all 3
L3 access time, you won't be able to match without PBO (that's 4.3 PBO)
Memory latency you should be able to match and beat, where just 3400MT/s v2 b-dies

About SiSandra, results like this are what i'd like people to share back and forth as comparison








Memory interleaving size and every type of timing will change this graph
Also the PB tuning will change it
For 3rd gen the whole text report down bellow is interesting
For 1st/2nd gen users only the overall view with bandwidth + inter-core latency
EDIT:
Performance Bias and Performance Enhancer doesn't work on 3rd gen yet
i can suggest every 3rd gen user to support infraredbg, the maintainer of the zenstate tool by giving him SMU adress exports
Till we find out the correct adress 3rd gen uses to communicate with it's PSP firmware
Thread visible here, and page to download the SMU debug tool here


----------



## yrelbirb

welp i give up

this mobo really sucks

pstate overclocking, ok. voltage always 1.3, right? and it is really the case

here are my tests;

pstate0 1.3v 4.075 ghz, its all ok

go into desktop, set power plan to %40, so cpu goes to 2.2 ghz. svi2 tfn still reads 1.3v. ok. assume its a bug.

well, apparently its not.

go prime95, small fft, voila, power usage is 65-70 watt.

its supposed to drop into 0.7V for 2.2 ghz. apparently it doesn't.

then i go and manually set 2.2 ghz and 0.7v and? smallfft tests uses 35-40 watt.

this proves my theory that once Pstate0 is used, board wont downvolt


----------



## heptilion

So I have managed to get my memory to be stable on these timings. Any suggestions on lower timings please?


----------



## Veii

yrelbirb said:


> Hi, veii, thanks for detailed descriptions again
> 
> you may remember me from other ram post, thanks to you my soc was set to 1.025 by hex value under AMD CBS section
> 
> my vddp is also fixed at 700 mv as per your instructions from past discussion (again, thrash B-Die subject)


I actually did forget, i'm sorry
Didn't look at names as since then couple of posts have passed
That makes now sense, thank you for reminding me 


yrelbirb said:


> with pstate overclocking and c states enabled; my vcore drops to 0.5 values, okay its fine its supposed to be. but svi2 tfn never drops, alwsays stays about 1.3v. i assume its bugged again, right? no need to worry about that i guess?


I think at the last your powerplan is bugged, because you don't drop under Pstate 1 which is around the 2ghz mark
First two ryzens had 3 Pstates only, soo you don't need the rest of them
Can you check if on your ryzen balanced powerplan, you have minimum load as 1-5% (something in between works)
Normaly SVI2 is accurate, but somehow it doesn't read out your remain powerstates
At worst, zenstate will help - but first doublecheck your current powerplan settings

If it won't work, we'll skip PState OC and just go the PBO path with limited ranges and negative vCore offset



yrelbirb said:


> here are my settings. did I make a mistake, or am I okay? some of the things you mention was not present (like memory interleaving size). and also you said choose pstate 2 or something, i think you meant "ppc adjustment". what does it do and why was it pstate0 and why did I set it to pstate2 ?


Yep the name varies between bios brands, we still have no universal naming scheme most of the time
What you wanted to set is the lowest PState Cool'n'Quiet has to drop (which is effectively a part of C-States) 

i didnt get you though, how can i get down to 60 ns with micron b die kits?  i would think its impossible? i would like to settle on 68 range honestly, default XMP was at 77 ns with 3000 mhz cl16...[/QUOTE]
XMP is after all ***********Memory-Profile, don't take it as limits
I shouldn't have mentioned to beat the memory latency, but you should be able to ~ as these where just bad b-dies limited to 3400
Right right, it's been some time ~ Aida64 is not cheap 
But SiSoftware Sandra is free, you can use that to finetune memory
So far L2 and L3 cache look alright on your side ~ important was to keep them as identical as possible between Read & Copy
You'd notice instability or bottlenecking especially on the L3 result having +/- 50gb/s 
On the example result shown, i had around 20gb/s difference and on L2 still around the same - it still had playroom but the ram kit was bad

Yep just use SiSandra to test and finetune timings from now on (of course also checking if they are stable)
After you have your baseline reading, every boot launch CB_Gentle.exe from the previous post attached
That should fix a bit the latency "issues" with 2nd gen & improve L3 cache access time, without pushing memory latency 
* test your memory with CB_Gentle performance bias enabled, as instability can occur with it enabled


----------



## Veii

heptilion said:


> So I have managed to get my memory to be stable on these timings. Any suggestions on lower timings please?


tRAS and tRC have a lot of playroom still 
Try if you can manage tRAS 30, tRC 48, tRFC 288-214-132


----------



## yrelbirb

Veii said:


> I actually did forget, i'm sorry
> Didn't look at names as since then couple of posts have passed
> That makes now sense, thank you for reminding me
> 
> I think at the last your powerplan is bugged, because you don't drop under Pstate 1 which is around the 2ghz mark
> First two ryzens had 3 Pstates only, soo you don't need the rest of them
> Can you check if on your ryzen balanced powerplan, you have minimum load as 1-5% (something in between works)
> Normaly SVI2 is accurate, but somehow it doesn't read out your remain powerstates
> At worst, zenstate will help - but first doublecheck your current powerplan settings
> 
> If it won't work, we'll skip PState OC and just go the PBO path with limited ranges and negative vCore offset
> 
> 
> Yep the name varies between bios brands, we still have no universal naming scheme most of the time
> What you wanted to set is the lowest PState Cool'n'Quiet has to drop (which is effectively a part of C-States)
> 
> i didnt get you though, how can i get down to 60 ns with micron b die kits?  i would think its impossible? i would like to settle on 68 range honestly, default XMP was at 77 ns with 3000 mhz cl16...


thx, i will continue to work on ram but i give up on CPU. i will just let everything auto. if it degrades or get broken on completely stock settings i think i will not buy amd ever again, nothing i can do

as i said in the post above, cpu downclocks but doesnt actually downvolts so no savings or whatsoever (35w at 2.2 ghz and 0.7v, and 70ww at 2.2 ghz and 1.3v)

mobo is bad too but i guess i have to rely on "just works" stock

--

one of the games i play the most is Heroes of Storm. this is why i didnt like this cpu or its behaviour. this game uses only 1-2 cores at best

so this cpuı constantly tries to boost one clock to 4.2-4.25 ghz

result is, here's a 20 min heroes of storm game

https://prnt.sc/rryn57

this means this cpu worked at an average of 1.4v for 20 min... and i play this game for hours. 


for now im picking %99 max power plan in desktop to obstruct constant 1.4v

sorry but i cannot use my programs to my cpu's whim. i like to run some background tasks all the time, that should be the purpose of cpu

vbut everyone in the same time says max constant safe voltage is 1.35... and here my cpu, at stock, uses 1.4v+ constantly on desktop and single threaded games

--

returned to my all core overclock


----------



## Veii

Hmm how can i manage to explain it to you @yrelbirb 
You seem to overlook important parts 
Let's start that way:

How long does a CPU live:
- Under 82-85c 24/7 load around 6-8 years, where point of degradation would be poweroff and not constant load
- Under normal usecases let's say a year with 365d without all the weekends (104 days), around 12h usage a day equal to 3132h poweron time
you could expect here with a lifetime of about 10 years ~ usually over 12 but factoring in poweroff which is more harmful than a constant running system we end up near the 10ish mark

When does a silicon degrade:
- long term too high heat (90c for >240h, or around 10+ days) *
* this depends on used voltage
- far to high over-current spikes (we speak here about short term spikes near 1.6-1.72v)
- a combination of both, too high constant non variable voltage under constant load with high heat

How to prevent degradation:
- shuffling voltage, the less time X voltage is running ~ the more "spikes" it can absorb 
- sacrificing frequency when you have to use high voltage, lower frequency = less harm under high voltage 
- combating high voltage with high resistance

How would you know what is safe and what not:
- Safe voltage depends on above conditions (X frequency under Y time with Z thermal conditions)
- Safe voltage range depends on architectural node size 
Examples:
*14nm* [email protected] AC can run 1.32v 24/7, 14nm [email protected] AC can run constant 1.42v, 1950X @4.3ghz can run 1.365v (lower voltage because it pushes near 380-400W which pushes too much current under too many cores)
*12nm* [email protected] 1.4v has no issues, we miss examples from intel but if a 8c 5ghz exists it would need to run near 1.35 or 4.5ghz @ 1.4v
*10nm* [email protected] GHz should use about 1.110v if "intel tdp" is to believe but should have limits up to 1.38v at this frequency or 1.325 peaking 4Ghz / or to fantasize [email protected] constant load
*7nm* 3rd gen ryzen - 4.0Ghz AC requies about 1v with upper limits of 1.375, 4.2Ghz requires 1.2v with upper limits 1.3625v, 4.5Ghz requires 1.32v with upper limits 1.28-1.325v, 4.6Ghz requires sillicon lottery >1.32v with maximum limits of ~1.3v

As you can hopefully see, "safe voltage range" depends on several factors
X frequency at N node size, and then depending on Y time how long it would hold this voltage and if it would constantly use full load

To give more examples:
1.72v on DDR4 B-dies runs fine if you limit a 8gb dimm to 2gb size @ 2100mhz (4200MT/s) 24/7 (20nm) ~ 45c
1.62v on HynixMFR (24nm) full size @1666Mhz (3333MT/s) is fine 24/7 too ~ 45c
1.5v on 20nm B-dies full size up to 2400Mhz (4800MT/s) can run 24/7 ~ 65-70c, would destabilize after
1.46v dual rank micron Rev. E 18nm have no issues under full capacity, or 1.58-1.6v~ at small capacity limit

All depends on nm size to frequency at specific temp and workload stress
could give more examples why 1.48v peak or 1.35-1,36v allcore would be considered safe under 12nm while 7nm does use nearly the same maximum range but effective allcore voltage is manufacturing size lower ~ it all clearly makes sense, if you understand how it works
~ but this post would be far bigger than it already is

You have to keep in mind, every device be it Memory ICs or sillicon depend on far more factors than just voltage at X manufacturing node
3rd gen goes around the degradation part with far to high current because it does push this 1.48v max only for 5ms-10ms at an update time far higher than remain generations before
If 2nd gen would use the same method which now 4th gen will use too, it could run 1.6v boost with ease - but as it can't we are limited to common sense delay, but even here XFR does exist same as for 1st gen ~ although slower


Keep that last part in mind
Update time and so frequency + voltage cycling are strongly beneficial for silicons stability and combat degradation
By going constant load with fixed frequency you do limit CPUs lifespan down to 6 years instead potentially 10~
But we are on OCN, soo people don't care too much about half the lifespan of their CPUs - as they are rated anyways for 10-12years
Just keep that in mind,
The OC example of the 2700X under near 4.3ghz AC (1.32v / 1.268v AVX2) or 4.55ghz Boost (1.458v) moved in the safe voltage range
While it struggled to get anything over 4.2v allcore to run
Hopefully you should understand also why it did that

The 1950X i had before to play with pushes 1.5v VID but uses only 1.2v for itself
That allows it to run 4.1Ghz AC under 1.2v~ or 1.25v with room for memory OC 

You can push high voltage to everything, and keep it "idle" at high clock
As long as there is no load to it it wouldn't degrade nor use a lot of power 


Spoiler












better pictures oppon request, with a bit of delay - as i have to ask for usage permissions


It idles at around 32W+10W SOC, even tho technically it does push high voltage through it
The silicon has been running 2+ years since launch back then 2017 and does use all cores @ 85% load to encode x264


----------



## KedarWolf

Anyone even uses stressapptest any more?


----------



## yrelbirb

thiswas a great read, thanks you a lot. then i can use stock/auto freely i guess

maybe i can utilize a bit of negative offset still?

"So far L2 and L3 cache look alright on your side ~ important was to keep them as identical as possible between Read & Copy
You'd notice instability or bottlenecking especially on the L3 result having +/- 50gb/s
On the example result shown, i had around 20gb/s difference and on L2 still around the same - it still had playroom but the ram kit was bad"

how do i go on to tweak this? which timings or settings affect this difference on l3?

oh also, what does cb_gentle do in a basic sense? 

and for si sandra, which values i aim to check for? and whats a proper way to make a report ouf ot it = (i think i tried but failed  )


----------



## Veii

yrelbirb said:


> thiswas a great read, thanks you a lot. then i can use stock/auto freely i guess
> maybe i can utilize a bit of negative offset still?


You can !
We have no clock stretching on 2nd gen
2700X is no powersaving cpu at all, it can pull 240W from the line and be in the safe limits
X series loves voltage because it's a leaky CPU , soo don't overthink it too much
Only take care when you use PBO - that negative offset is needed 
Because PBO does push on stock higher voltages and shifts the boosting table around 
(Boosting table = X voltage for Y frequency, "the range")

It's a bit unfortunate that gigabyte messed up their boards back then a lot
It's something you just have to keep in mind - if you use fixed voltage (don't) then it pushes 0.1v more than what you type
Auto knows it's ranges and the 2700X has a FIT module inside, it clearly knows its ranges on stock - soo don't worry 

If you want to limit heat, best practice is PBO with negative offset and always lower vSOC 
And if you want to limit frequency, best practice is PBO with fixed values under TDC,EDC,PPT 
Which translate to "i can only take this much power, and if X workload pushes me too hot after this value, i will throttle down"
^ that way you can perfectly control how much voltage it can take, and if it should throttle on AVX2 intensive workloads to maintain stability


----------



## yrelbirb

so either way, i assume you suggest enabling xfr/pbo as well? i've tried putting a -0.72 offset (would be cool to maintain)

so, for stability; i should run linpack 1.1.1 20 times and 30 min occt beta, am i right?

do i play with edc relaxed setting and cTDP or leeave them auto for this kind of usage?

oh and from my top post (i added later but i couldnt anticipate you would reply this quickly  )

"how do i go on to tweak this? which timings or settings affect this difference on l3?

oh also, what does cb_gentle do in a basic sense?

and for si sandra, which values i aim to check for? and whats a proper way to make a report ouf ot it = (i think i tried but failed )
"


----------



## yrelbirb

good news... offset doesnt break the voltage like it did with pstate overclocking

https://prnt.sc/rs30ny

https://prnt.sc/rs31ma

i should deduct -0.72 (my offset) from svi2 tfn value i guess, because it equals out to vcore as well

time to test stability of this -0.72 then

pbo seems to give me the same overclock as well (about 4.1 ghz) so its cool


----------



## heptilion

Veii said:


> tRAS and tRC have a lot of playroom still
> Try if you can manage tRAS 30, tRC 48, tRFC 288-214-132


 @Veii I managed to pass 1000% single on memtest on timings you suggested. Any other tweaks i could try?


----------



## heptilion

KedarWolf said:


> Do you peeps have HCI MemTest Pro 7.0, the newest version? and a 3950x?
> 
> If you don't and you bought it in the last year, they'll email you a free upgrade.
> 
> If you do, put this MemTest helper file in the folder with the MTPclassic.exe file and run it. Or you can just try renaming your MemTest.exe to MTPclassic.exe, sometimes that works.
> 
> It runs MemTest Pro 32 times for a 3950x, once for each thread and spaces them evenly on the screen. And it allocates each running Memtest instance to its own thread, so like the first one is using only the first thread, second using only second thread, etc. Uses about 25.5GB of RAM all running.
> 
> You can check this by opening task manager, right-click on one MemTest.exe, go to Details, Set Affinity, see the thread it's on.
> 
> It's the absolute best way to run MemTest.
> 
> I can compile an .exe for say a 3900x or whatever CPU you have as well.
> 
> All credit goes to @GeneO who wrote this script. Rep him, not me, there is no way I could write this kind of thing myself, just good enough at math logic to edit it for our needs.


 @KedarWolf could you compile an .exe for a 3800x with 16GB memory please?? Probably need to make it use around 12500mb of memory for testing.

Thanks.


----------



## Veii

yrelbirb said:


> "So far L2 and L3 cache look alright on your side ~ important was to keep them as identical as possible between Read & Copy
> You'd notice instability or bottlenecking especially on the L3 result having +/- 50gb/s
> On the example result shown, i had around 20gb/s difference and on L2 still around the same - it still had playroom but the ram kit was bad"
> 
> 
> 
> how do i go on to tweak this? which timings or settings affect this difference on l3?
> oh also, what does cb_gentle do in a basic sense?
Click to expand...

I can't explain it in basic sense, it's low level infinity fabric tweaking 
Here it was taken out of the bios for XOC people to easier use it
Elmor and infraredbg (zenstates) , i think The Stilt too - can you give you a long explanation what it does 
~ when they find the time , or you can go into the asus zenstate thread and ask directly there for a long explenation
I can only say, CB_Gentle has no negative effects - where early Performance Bias CinebenchR15/Aida64 had negative effects on memory latency, with exchange of far lower L3 latency and so higher IPC


yrelbirb said:


> and for si sandra, which values i aim to check for? and whats a proper way to make a report ouf ot it = (i think i tried but failed  )


Check this thread here https://www.overclock.net/forum/13-...membench-0-8-dram-bench-693.html#post28392870
The Detailed Tab (Multi-Core Efficiency) with filtered local results 


yrelbirb said:


> so either way, i assume you suggest enabling xfr/pbo as well? i've tried putting a -0.72 offset (would be cool to maintain)
> do i play with edc relaxed setting and cTDP or leave them auto for this kind of usage?"


cTDP can stay on it's maximum 300W it doesn't bother, it's just there to lift some OCP
XFR is always on, it's the boosting mechanism
If you enable PBO you have to use a negative offset / need to take a look at what PBO settings i've used back then under what offset
But yes, exactly that


> so, for stability; i should run linpack 1.1.1 20 times and 30 min occt beta, am i right?


That's the fastest way, but on OCCT two times one with medium dataset auto instruction set, and one small instruction set AVX2
Medium dataset should detect issues with the IMC, while small instruction set is similar to P95 just here under AVX to focus on maximum voltage drop and so adjust LLC



> oh and from my top post (i added later but i couldnt anticipate you would reply this quickly  )
> "how do i go on to tweak this? which timings or settings affect this difference on l3?


Aida64 results you can see as efficiency result between Read and Copy
Perfect efficiency aka maxed out platform performance would be about equal values between both
Usually with bottlenecking ram (72ns or higher under first two gens) you dropped L3 cache down to 360GB/s instead 440
Let's say it was clearly noticable
But frequency does push L2 and L3 maximum bandwidth where lower latency on it's own can be seen as higher IPC
Although, SiSandra is better for this kind of end-finetuning



yrelbirb said:


> good news... offset doesnt break the voltage like it did with pstate overclocking
> https://prnt.sc/rs30ny
> https://prnt.sc/rs31ma
> 
> 
> 
> i should deduct -0.72 (my offset) from svi2 tfn value i guess, because it equals out to vcore as well
Click to expand...

SVI2 is the last sensor which is said to be the most accurate one
On your side tho i wouldn't trust any sensor voltage readouts, only a multimeter 
I think memory voltage was the only one that was fine

An offset shouldn't cause issues on your side, as the CPU knows what it can handle 
Just don't go into positive offset, because what you read out is not true 
Go with the offset by thermals and performance, not by values on your board


----------



## yrelbirb

Veii said:


> I can't explain it in basic sense, it's low level infinity fabric tweaking
> Here it was taken out of the bios for XOC people to easier use it
> Elmor and infraredbg (zenstates) , i think The Stilt too - can you give you a long explanation what it does
> ~ when they find the time , or you can go into the asus zenstate thread and ask directly there for a long explenation
> I can only say, CB_Gentle has no negative effects - where early Performance Bias CinebenchR15/Aida64 had negative effects on memory latency, with exchange of far lower L3 latency and so higher IPC
> 
> Check this thread here https://www.overclock.net/forum/13-...membench-0-8-dram-bench-693.html#post28392870
> The Detailed Tab (Multi-Core Efficiency) with filtered local results
> 
> cTDP can stay on it's maximum 300W it doesn't bother, it's just there to lift some OCP
> XFR is always on, it's the boosting mechanism
> If you enable PBO you have to use a negative offset / need to take a look at what PBO settings i've used back then under what offset
> But yes, exactly that
> 
> That's the fastest way, but on OCCT two times one with medium dataset auto instruction set, and one small instruction set AVX2
> Medium dataset should detect issues with the IMC, while small instruction set is similar to P95 just here under AVX to focus on maximum voltage drop and so adjust LLC
> 
> 
> Aida64 results you can see as efficiency result between Read and Copy
> Perfect efficiency aka maxed out platform performance would be about equal values between both
> Usually with bottlenecking ram (72ns or higher under first two gens) you dropped L3 cache down to 360GB/s instead 440
> Let's say it was clearly noticable
> But frequency does push L2 and L3 maximum bandwidth where lower latency on it's own can be seen as higher IPC
> Although, SiSandra is better for this kind of end-finetuning
> 
> 
> SVI2 is the last sensor which is said to be the most accurate one
> On your side tho i wouldn't trust any sensor voltage readouts, only a multimeter
> I think memory voltage was the only one that was fine
> 
> An offset shouldn't cause issues on your side, as the CPU knows what it can handle
> Just don't go into positive offset, because what you read out is not true
> Go with the offset by thermals and performance, not by values on your board


hmm u mentioned something about board always puts 0.1

does this aplly to offset as well? 0.1 seems a bit much, is it a gigabyte specific issue?

here's my sisandra results with cb_gentle

https://ranker.sisoftware.co.uk/show_run.php?q=c2ffc9ef8eefd2e3d6e2d5eddbfd8fb282a4c1a499a98ffcc1f1

and aida rezults

https://prnt.sc/rs60fs

hmm so i can opt out of xfr enchament (pbo). i can and probably should still set a negative offset for core boost, right? so i get lower thermals and better stability for potential reasons?

for static vcore, you mean to say if i set 1.32v for example, gigabyte mobo actually doeds 1.42v? holy light if thats the case...

edit,

i dont know what happened but despite having set an offset, now for some reason vcore and svi2 tfn matches up.. maybe cb._gentle did something to fix it?

https://prnt.sc/rs694b

https://prnt.sc/rs69o0

any clues? ***


----------



## Veii

yrelbirb said:


> hmm u mentioned something about board always puts 0.1
> 
> does this aplly to offset as well? 0.1 seems a bit much, is it a gigabyte specific issue?
> here's my sisandra results with cb_gentle
> https://ranker.sisoftware.co.uk/show_run.php?q=c2ffc9ef8eefd2e3d6e2d5eddbfd8fb282a4c1a499a98ffcc1f1
> 
> and aida rezults
> https://prnt.sc/rs60fs
> 
> hmm so i can opt out of xfr enchament (pbo). i can and probably should still set a negative offset for core boost, right? so i get lower thermals and better stability for potential reasons?
> 
> for static vcore, you mean to say if i set 1.32v for example, gigabyte mobo actually doeds 1.42v? holy light if thats the case...
> 
> edit,
> i dont know what happened but despite having set an offset, now for some reason vcore and svi2 tfn matches up.. maybe cb._gentle did something to fix it?
> https://prnt.sc/rs694b
> https://prnt.sc/rs69o0
> any clues? ***


It's a gigabyte specific mistake, a hardware issue - nothing a bios can rly fix, but they should be aware

Yep, noticed it before on X399 Designare too - you put 1.1v SOC in, it pushed 1.2 
But unless you don't use fixed voltages, it should be fine
It should also be fine by using hex values from AMD CBS - as SMU Firmware should tell the cpu use this exact HEX and request this voltage
then it should be fine 
But yes, don't trust readouts 
Only the X470 Gaming 5 and K7 had no issues, the whole rest did 
X570 doesn't have this issue anymore and maybe there are new revisions of some boards / i haven't checked

Just yes, don't trust your voltage readouts 
that SVI, VCore change - normally LLC does something, "normally" even more sure, when the bios auto controls it without giving the user the input on it

Work now with sisandra, when you finetune stuff
Keep in mind, lower procODT=potentially higher memory OC on first two gens
Higher vSOC = higher required procODT - same goes for higher density kits

CPU perf benefits hmm, cinebench R20 is still a valid option
and SuperPi 1.5 SX is a good benchmark for both Memory and CPU performance - although it runs slower on Win10
well, benchmark just for you 
And enable that PBO - XFR is always on, but it's "enhancements" are still beneficial
* just keep in mind, to use a far stronger offset with PBO - because PBO does normally push it to 1.5-1.54v (which is quite borderline on 12nm ~ but hey , at least on that generation it worked well)


----------



## Veii

heptilion said:


> @Veii I managed to pass 1000% single on memtest on timings you suggested. Any other tweaks i could try?


Excuse my lack of memory on usernames
But you couldn't push 3800MT/s yet, did you ?
tRTP could be 6 with tWR 12 to round this set of timings up, but it looks solid
What you can do afterwards is also put tRDWR to 7, and tWRRD 4 - but if that fails to post try 3 (it will either work or fail to post)
tRC be lowered later a tiny bit after tRDWR 7 works soo you get tRFC down another big chunk - but that's it

For better results on this frequency you need to start going awkward timings, like going down with tRP
Soo it allows you to lower tRC even more (tRAS+tRP), which allows you to lower tRFC another big step 
afterwards you should finally be able to use SCL of 2 on this set, but if it still doesn't want to work, you'll need to lower tRCD RD one step more


----------



## yrelbirb

Veii said:


> Excuse my lack of memory on usernames
> But you couldn't push 3800MT/s yet, did you ?
> tRTP could be 6 with tWR 12 to round this set of timings up, but it looks solid
> What you can do afterwards is also put tRDWR to 7, and tWRRD 4 - but if that fails to post try 3 (it will either work or fail to post)
> tRC be lowered later a tiny bit after tRDWR 7 works soo you get tRFC down another big chunk - but that's it
> 
> For better results on this frequency you need to start going awkward timings, like going down with tRP
> Soo it allows you to lower tRC even more (tRAS+tRP), which allows you to lower tRFC another big step
> afterwards you should finally be able to use SCL of 2 on this set, but if it still doesn't want to work, you'll need to lower tRCD RD one step more



my ram is weird on this regard

trp 14 tras 36 and trc 56 its ok. %1000 memtest

i try trc at 50 doesnt boot, 52 doesnt boot 54 boot but errors quickly

wonder what trips up my kit? should i use trp @20 bcoz of high trc? or should i st ick to trp 14 and trc56 in general?

you mentioned something about latencies and smooth transition so i opted out of tras 21 and been using 36 for a time now

i also checked this guide ;

https://github.com/integralfx/MemTestHelper/blob/master/DDR4 OC Guide.md

"Tightening Timings" section, i used every extreme labeled settings he provided, and all of them combined passed %2200 memtest (bored after waking up)


am i lucky on that regard?  

i used rzq/7 + dynamic off + rzq /5 (from dram calculator)
all cad bus are 24-24-24-24
and prooct - 53.3


----------



## Veii

yrelbirb said:


> my ram is weird on this regard
> 
> trp 14 tras 36 and trc 56 its ok. %1000 memtest
> 
> i try trc at 50 doesnt boot, 52 doesnt boot 54 boot but errors quickly
> 
> wonder what trips up my kit? should i use trp @20 bcoz of high trc? or should i st ick to trp 14 and trc56 in general?
> 
> you mentioned something about latencies and smooth transition so i opted out of tras 21 and been using 36 for a time now
> 
> i also checked this guide ;
> https://github.com/integralfx/MemTestHelper/blob/master/DDR4 OC Guide.md
> 
> "Tightening Timings" section, i used every extreme labeled settings he provided, and all of them combined passed %2200 memtest (bored after waking up)
> 
> am i lucky on that regard?
> 
> i used rzq/7 + dynamic off + rzq /5 (from dram calculator)
> all cad bus are 24-24-24-24
> and prooct - 53.3


Might be lucky with a good PCB 
When you change tRC did you "only" change tRC ?
Without changing tRFC with it you will break the "perfect" sync and the kit will error out 
If you go that tight without wasted latency between timings 

Hmm it's quite some pages behind on this thread
No Timing goes alone, you change 1 = you need to change likely it's 2nd connection
you change tRCD = you need to work on tRDWR & tWRRD 
You change tRP = you need to change tRAS
you change tRAS = you need to change tRC
Changing tRC needs adjustment on tRFC
adjustment on tRFC needs a doublecheck with tWR and tRTP

You never change 1 timing 
Let me drop my tRFC calculator here again in case it got lost
https://docs.google.com/spreadsheets/d/1A7G97QOL0dNMwJZa9SYEq2RElJ5T6Hcx9WdReTsnIWw/

The only timings which scale with voltage are:
tCL, tRP and a bit tRFC - but only because you have remain current that can be used to precharge cells on far too high current
only voltage will not change tRFC 
Heat will influence tRFC range simply because heat does translate to how long cells need to discharge and recharge again 

soo heat only influences delay a bit - and voltage creates heat 
What scales between IC brands is:
tCL, tRCD, tRP, SCL, tRFC
some chips just need longer to recharge soo you need bigger transition timings between each action

Offtopic Sidethought:
i wonder if we push tRP and lower tRCD far lower than tCL 
Like 14-12-12-16-26-32
instead of
14-12-16-12-30-42 :thinking:
In theory that could work as what only causes errors is cells not recharging in time which is tRP's work
On higher frequency they should discharge fast enough to cover this 12 timings.
Only recharge delay was an issue and needed always 1.6v or higher to cover it :thinking:
Might anyone want to test this ?
If it works how i think it should, we would have far lower tRAS & tRC :wubsmiley


----------



## yrelbirb

Veii said:


> Might be lucky with a good PCB
> When you change tRC did you "only" change tRC ?
> Without changing tRFC with it you will break the "perfect" sync and the kit will error out
> If you go that tight without wasted latency between timings
> 
> Hmm it's quite some pages behind on this thread
> No Timing goes alone, you change 1 = you need to change likely it's 2nd connection
> you change tRCD = you need to work on tRDWR & tWRRD
> You change tRP = you need to change tRAS
> you change tRAS = you need to change tRC
> Changing tRC needs adjustment on tRFC
> adjustment on tRFC needs a doublecheck with tWR and tRTP
> 
> You never change 1 timing
> Let me drop my tRFC calculator here again in case it got lost
> https://docs.google.com/spreadsheets/d/1A7G97QOL0dNMwJZa9SYEq2RElJ5T6Hcx9WdReTsnIWw/
> 
> The only timings which scale with voltage are:
> tCL, tRP and a bit tRFC - but only because you have remain current that can be used to precharge cells on far too high current
> only voltage will not change tRFC
> Heat will influence tRFC range simply because heat does translate to how long cells need to discharge and recharge again
> 
> soo heat only influences delay a bit - and voltage creates heat
> What scales between IC brands is:
> tCL, tRCD, tRP, SCL, tRFC
> some chips just need longer to recharge soo you need bigger transition timings between each action
> 
> Offtopic Sidethought:
> i wonder if we push tRP and lower tRCD far lower than tCL
> Like 14-12-12-16-26-32
> instead of
> 14-12-16-12-30-42 :thinking:
> In theory that could work as what only causes errors is cells not recharging in time which is tRP's work
> On higher frequency they should discharge fast enough to cover this 12 timings.
> Only recharge delay was an issue and needed always 1.6v or higher to cover it :thinking:
> Might anyone want to test this ?
> If it works how i think it should, we would have far lower tRAS & tRC :wubsmiley


how do we change tRP in relation to tRAS actually?
and connectioın between, "you change tRCD = you need to work on tRDWR & tWRRD " how they do happen?
i tried alot of things but these rams do not boot below 19 tRCD for 3200 mhz (they boot at 19 but you said with geardown they become actually 20. but ryzen timing checker still shows as 19 so not sure still)

btw i forgot to add, i use SCL as 2-2 and it seems stable;
https://prnt.sc/rsbxty

*** happened to my readings xd it does this sometimes. a reset fixes it.  wonder why?

ooh hwinfo is the culprit

https://prnt.sc/rsceg6


----------



## Veii

yrelbirb said:


> how do we change tRP in relation to tRAS actually?
> and connectioın between, "you change tRCD = you need to work on tRDWR & tWRRD " how they do happen?
> i tried alot of things but these rams do not boot below 19 tRCD for 3200 mhz (they boot at 19 but you said with geardown they become actually 20. but ryzen timing checker still shows as 19 so not sure still)
> 
> btw i forgot to add, i use SCL as 2-2 and it seems stable;
> https://prnt.sc/rsbxty
> 
> *** happened to my readings xd it does this sometimes. a reset fixes it.  wonder why?


tRFC 1 hahaha
If a whole memory cycle would only take 0.625ns - dreaams 
but it did got tREFI right :thinking: 
Yep, it's a RTC bug but the tool still works far better than ZenTimings - because it shows tSTAG and tMRD(tMDRPDA) 
^ which is what does change tRFC2 and 4 
tSTAG is used on tCKE, where tSTAG also is used to calculate tRFC1 
Even tho tRFC2/4 is not directly used before 85c - it still does modify far more than the normal eye sees 

tRDWR & tWRRD guide rewritten 
https://www.overclock.net/forum/10-...memory-stability-thread-328.html#post28385690

There are many many guides out there and the easiest to understand is this page:
https://www.reddit.com/r/overclocking/comments/ahs5a2/demystifying_memory_overclocking_on_ryzen_oc/

And this was my take on the whole scene:
https://www.overclock.net/forum/11-...chi-overclocking-thread-705.html#post28246564
EDIT:
How to calculate tRAS is tRCD+tCL
tRC is tRAS + tRP, +/- 2 if you want to tighten things


----------



## yrelbirb

Veii said:


> tRFC 1 hahaha
> If a whole memory cycle would only take 0.625ns - dreaams
> but it did got tREFI right :thinking:
> Yep, it's a RTC bug but the tool still works far better than ZenTimings - because it shows tSTAG and tMRD(tMDRPDA)
> ^ which is what does change tRFC2 and 4
> tSTAG is used on tCKE, where tSTAG also is used to calculate tRFC1
> Even tho tRFC2/4 is not directly used before 85c - it still does modify far more than the normal eye sees
> 
> tRDWR & tWRRD guide rewritten
> https://www.overclock.net/forum/10-...memory-stability-thread-328.html#post28385690
> 
> There are many many guides out there and the easiest to understand is this page:
> https://www.reddit.com/r/overclocking/comments/ahs5a2/demystifying_memory_overclocking_on_ryzen_oc/
> 
> And this was my take on the whole scene:
> https://www.overclock.net/forum/11-...chi-overclocking-thread-705.html#post28246564
> EDIT:
> How to calculate tRAS is tRCD+tCL
> tRC is tRAS + tRP, +/- 2 if you want to tighten things



it turned out to be a hwinfo bug though

i think when both of them tried to read timings from dram other one got worked up

actually i think it might be dangerous, right? i shouldnt have two programs trying to access dram timings. or is it a superstation? 

i will be caarefully reading those guides as well and return back to you with my findings and tunings


----------



## Veii

yrelbirb said:


> it turned out to be a hwinfo bug though
> 
> i think when both of them tried to read timings from dram other one got worked up
> 
> actually i think it might be dangerous, right? i shouldnt have two programs trying to access dram timings. or is it a superstation?
> 
> i will be caarefully reading those guides as well and return back to you with my findings and tunings


Ah yes, i forgot 
This is still a thing 
RTC does low level access SMU, HWInfo current one does the same 
HWInfo and Ryzen master will cause issues and can let the cpu lock down till cold-re'boot

I had that once while using SMU tool to dump SMU adresses while having HWInfo open 
bad times, whole system hanged up ~ it was under remote control 
Seems like this is now needed for HWinfo to work accurately on 3rd gen
You can downgrade to HWInfo 6.14 tho for 2nd or 1st gen - had to do the same for the Threadripper


----------



## Keith Myers

KedarWolf said:


> Anyone even uses stressapptest any more?


Yes, when it is the only memory tester other than Memtest in the BIOS for Linux.


----------



## Satanello

Hello all, I tested for hours this week but I definitely need your help to find the right settings for my memory kit.
I tried all the 1usmus settings from Calulator but something is non going as expected........
Atm I'm at ddr4 3800 but I'd like to reduce latency to reach the best for gaming, here attached my best settings.
I tried TRFC up to 600 TRFC (not TRFC2 and 4 to reduce the quantity of variables) and tRC 62 but I see better bandwith and worse latency...... 
Could anyone give me some advice on how to try to change timings?
please be patient my english is bad 

EDIT: Vdimm is fixed at 1,4V bios / 1,42 Hwinfo; if i add +0,2V I can probably reduce tRCDWR from 22 to 21 (at 3600 the behavior was this but I never tried to go up with the voltage at 3800)
VSOC: 1,075
Cad, proc ODT VDDP, VDDG, all Auto because I used a memory try it profile to start (using 1usmus settings my system failed boot).


----------



## yrelbirb

hmm so i tried 

trp 14
tras 34
trc 48
and trfc 480

3 times reboot and back to desktop with defalt timings

tried trc 50 and trfc 500, same

cant seem to tighten tRC with this kit

booted to trc 54 and trfc 540... testing with 1usmus now

no luck lol 

https://prnt.sc/rt4n0n

hmm same for tRFC

i tried from trfc calc these values;

392 3 times loop and default to windows
448 same as above


----------



## Veii

yrelbirb said:


> hmm so i tried
> 
> trp 14
> tras 34
> trc 48
> and trfc 480
> 
> 3 times reboot and back to desktop with defalt timings
> 
> tried trc 50 and trfc 500, same
> 
> cant seem to tighten tRC with this kit
> 
> booted to trc 54 and trfc 540... testing with 1usmus now
> 
> no luck lol
> 
> https://prnt.sc/rt4n0n
> 
> hmm same for tRFC
> 
> i tried from trfc calc these values;
> 
> 392 3 times loop and default to windows
> 448 same as above


Error 2 is a timeout issue, somewhere something ends too quickly or you lack voltage and cells are not recharged in time
a sync issue with other words which's first culprit is voltage somewhere or resistance somewhere
Same goes for error on test 12
EDIT:
Please provide a zentimings/rtc readout on the timings that error'd out
EDIT2:
Error on test 6, often together with 12 is a voltage issue on VSOC or CLDO_VDDP
4 times error 6 at the start is IMC not getting enough voltage
If you check the cfg it will say what test does what 
Simple test with 1mb size are always starting tests
Error 5 then 6 is a timings missmatch between dimms (data mirror move)
afterwards error 6 is purely related to the IMC , be if procODT, CLDO_VDDP or vSOC
~ it translates to "i couldn't even start transfering data, i crashed" 
4-6x error 6 result in full bluescreen


----------



## Satanello

@Veii. I know that your trfc calculator only works well for Single rank rams (I tried it) but would you have any suggestions on what I could try for my Hynix CJR dual ranks? I haven't found many references to these rams on this thread (I found a German forum but I don't even know a word of German ....).
Isn't there anybody trying to "work" on dual rank CJR/DJR ram? Can I do some tests to help you fine-tune your dram calculator?


----------



## yrelbirb

Veii said:


> Error 2 is a timeout issue, somewhere something ends too quickly or you lack voltage and cells are not recharged in time
> a sync issue with other words which's first culprit is voltage somewhere or resistance somewhere
> Same goes for error on test 12
> EDIT:
> Please provide a zentimings/rtc readout on the timings that error'd out
> EDIT2:
> Error on test 6, often together with 12 is a voltage issue on VSOC or CLDO_VDDP
> 4 times error 6 at the start is IMC not getting enough voltage
> If you check the cfg it will say what test does what
> Simple test with 1mb size are always starting tests
> Error 5 then 6 is a timings missmatch between dimms (data mirror move)
> afterwards error 6 is purely related to the IMC , be if procODT, CLDO_VDDP or vSOC
> ~ it translates to "i couldn't even start transfering data, i crashed"
> 4-6x error 6 result in full bluescreen


hmm my voltage was 1.4v at that time. should i go little bit higher?

with just trc 56 and trfc 560 and at 1.36v, im stable no errors 1usmus and very long hci memtests

btw i would like to ask one more question here,

i tried to follow your guide ;

https://www.overclock.net/forum/10-...memory-stability-thread-328.html#post28385690

so lets say

my tRCDRD is 20 (cant lower it for now)
tRCDWR very dynamic can even lower to 8 but lets assume i put at 16 

so my tRDWR should be 8, right?

how about tWRRD though? do I leave at 1? does geardown mode affect tWRRD (make it auto to 2?) 

you say it should be close to RCDRD but with a max multiplier of *4 i should make it "5" which would be weird bcoz its also said that one needs to be substaintailly bigger than other (preferreably RDWR)

so i got confused a bit here. how should i exactly tweak my tRCDWR, tRDWR and tWRRDs actually ? should i change my SCL values (2-2) too ? or are thay okay?

(extra note: i tweaked my tRTP to 10, so it divides tRFC now. it also divides by tRCD (10/20) , okay i guess? what about tWR in this state?=")


----------



## Veii

Satanello said:


> @Veii. I know that your trfc calculator only works well for Single rank rams (I tried it) but would you have any suggestions on what I could try for my Hynix CJR dual ranks? I haven't found many references to these rams on this thread (I found a German forum but I don't even know a word of German ....).
> Isn't there anybody trying to "work" on dual rank CJR/DJR ram? Can I do some tests to help you fine-tune your dram calculator?


tRFC doesn't depend on memory density
it depends on current used timings and frequency / timings delay depend on memory IC
Stuff like *7 or *6 work for good A1 PCBs or A2 with low timings, B1/B2 for dual rank
Example are these timings from KendarWolf








240tRFC is a *6 thing, *5 is just stupid, needs LN2  soo i didn't include it

Hardwareluxx maybe or Computerbase, if you can link it
it would help to know how these kits scale, at least where their problem lies
But nop - you can use *8 or *10 with it or do the math yourself, tRC in ns times 9 div by 2000


----------



## Satanello

Veii said:


> tRFC doesn't depend on memory density
> 
> it depends on current used timings and frequency / timings delay depend on memory IC
> 
> Stuff like *7 or *6 work for good A1 PCBs or A2 with low timings, B1/B2 for dual rank
> 
> Example are these timings from KendarWolf
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 240tRFC is a *6 thing, *5 is just stupid, needs LN2  soo i didn't include it
> 
> 
> 
> Hardwareluxx maybe or Computerbase, if you can link it
> 
> it would help to know how these kits scale, at least where their problem lies
> 
> But nop - you can use *8 or *10 with it or do the math yourself, tRC in ns times 9 div by 2000


Thank you I'll try.
Here the thread on Hardwareluxx forum: https://www.hardwareluxx.de/communi...c-die-h5an8g8ncjr-2020-update.1206340/page-13

I am reading the thread thanks to the translator integrated in chrome 

Inviato dal mio LYA-L29 utilizzando Tapatalk


----------



## KedarWolf

heptilion said:


> @KedarWolf could you compile an .exe for a 3800x with 16GB memory please?? Probably need to make it use around 12500mb of memory for testing.
> 
> Thanks.


Oh, I never saw this until now, will do.


----------



## KedarWolf

heptilion said:


> @KedarWolf could you compile an .exe for a 3800x with 16GB memory please?? Probably need to make it use around 12500mb of memory for testing.
> 
> Thanks.


16 thread 16GB of RAM version for a 3800x with MemTest Pro.

It uses about 90% of your RAM after the operating system and background apps which is ideal.

Put it in the same folder as your MemTest Pro 7.0 and run it.

If you have an older version of MemTest Pro rename the MemTestPro.exe to MTPclassic.exe but there was one older version of Memtest Pro the script wouldn't work on.

If it doesn't work, upgrade to the latest version for $5 or if you bought it in the last year, email their support, they'll email you a free upgrade.


----------



## KedarWolf

Got under 62ns latency.

Now to test SisSoft.


----------



## rares495

KedarWolf said:


> Got under 62ns latency.
> 
> Now to test SisSoft.


Ok, great. Now I have to test RCDWR 8 again. Thanks... -.-


----------



## kyo2020

Well , in Asus x370 crosshair hero vi with r5 3600 only 65.9 ns....


----------



## rares495

kyo2020 said:


> Well , in Asus x370 crosshair hero vi with r5 3600 only 65.9 ns....


Change to tRRDL 4, tWTRS 4, tRDRDSD 5, tWRWRSD 7, tRCDRD 15, tRDWR 8, tWRRD Auto. That should be a bit better.

Add tRFC 308, tRFC2 229, tRFC4 141.


----------



## KedarWolf

KedarWolf said:


> Got under 62ns latency.
> 
> Now to test SisSoft.


----------



## yrelbirb

@Veii hi, i made some adjustments to tRDWr; how does it look :! did i do okay?

https://prnt.sc/rv1xfp

::::::::::

sidenot, i wrote you from pm too maybe i could ask here you too; when i use your Cb_GENTLe.exe, my fps in games gets very lower, any reason for this; ? i didnt get why you recommended me exactly so i wondered. 

it got inter lore latency to 55 ns and bandwitdh to 65gb/s though. but still, i didnt get what im trading exactly in terms of performance,;






a steep 10-15 fps drop can be observed for this game;

---

i still cant understand why its stable with low tRP... but doesnt even boot with tRC @52... 

should i up the tRP to match the tRP+tRAS=tRC calc, or just leave it as is ?


----------



## werks

Hi guys, recently switched to amd after years of intel.

I would appreciate any feedback, good or bad, if i can improve my timings.
tRC + tRCDRD is the lowest atm, any lower and it will not boot. 

Cheers


----------



## rares495

werks said:


> Hi guys, recently switched to amd after years of intel.
> 
> I would appreciate any feedback, good or bad, if i can improve my timings.
> tRC + tRCDRD is the lowest atm, any lower and it will not boot.
> 
> Cheers


Try tRCDRD 16 with tRCDWR 14/16, tRDWR 9/10 and tWRRD 1/2/3/4.

tRP 12 + tRAS 30 + tRC 42 and tRFC 420-312-192.

Proc_ODT 36,9


----------



## Veii

yrelbirb said:


> @Veii hi, i made some adjustments to tRDWr; how does it look :! did i do okay?
> 
> https://prnt.sc/rv1xfp
> 
> ::::::::::
> 
> sidenot, i wrote you from pm too maybe i could ask here you too; when i use your Cb_GENTLe.exe, my fps in games gets very lower, any reason for this; ? i didnt get why you recommended me exactly so i wondered.
> 
> it got inter lore latency to 55 ns and bandwitdh to 65gb/s though. but still, i didnt get what im trading exactly in terms of performance,;
> 
> https://www.youtube.com/watch?v=AfeHM_1uHWo
> 
> a steep 10-15 fps drop can be observed for this game;
> 
> ---
> 
> i still cant understand why its stable with low tRP... but doesnt even boot with tRC @52...
> 
> should i up the tRP to match the tRP+tRAS=tRC calc, or just leave it as is ?


I've read it, but this is awkward
It would be good to compare SiSandra Graphs visually between both modes 
I had a very awkward still not resolved issue with a buggy bios/SMU version back then
enabling performance enchancer would kill about 180-200cb in R15 
But can confirm on a 2700X that it does work well - when it works
Check this gallery:
https://imgur.com/gallery/d2KWrBM
This was far back then, but i've seen this happening also on ASRock B450M Pro4 
It was strongly noticable on L3 latency increase but cinebench revealed it 

Can you try if you can replicate the drop in performance in Cine R15 too ?
Else yes something must behave very strange to lose that much FPS out of nowhere
A visual SiSandra benchmark would show what it changed 
The only way i resolved it was mod another bios, because SMU transplants are annoying

If you can replicate that R15 point drop, maybe it's time to switch the bios
It shouldn't be thaat bad, at max you'd feel 1-2fps difference on games that don't utilize the cpu much
While there should be an increase, not a drop 

Timings:
Don't go tRRDL 4 unless you rock tight timings , 14-16-20 is not tight 
It will have negative effects only , but this is theory
Real difference will only be shown by SiSandra or DRAM Memtest-Benchmark
Try 4-5, or go back to 4.6 again 
About tRAS & tRC - sure you have wasted delay, but you need to test yourself if you can remove wasted delay while keeping memory error free
Non B-Dies can need this type of delay on tRC
tRAS should be at best always a clean transition
Which you have: tCL+tWR+2 or 4 & tCL + tCRD WR 

Need to crosstest a lot of combinations what leads to better perf on SiSandra
Focus on inter-core latency too , not only bandwidth 
Then later you can lower tWR to 14, and push tRAS to 34
If it errors, take away two also from tRC and fix tRFC afterwards
It shouldn't error on excessive delay but over +4 it can error

As you have GDM enabled, try to play only with even values 
tWRRD 4 likely performs better on this set than tWRRD 3 
Nothing else to judge - all is try and error, tRTP of 6 would be beneficial, but only at the end after everything else
tCKE 1 would be better than 8, 6 might work but this is IC dependent

After all this above, your next goal is tRCD RD 18


----------



## werks

rares495 said:


> Try tRCDRD 16 with tRCDWR 14/16, tRDWR 9/10 and tWRRD 1/2/3/4.
> 
> tRP 12 + tRAS 30 + tRC 42 and tRFC 420-312-192.
> 
> Proc_ODT 36,9


Thanks mate, couldnt get it to boot with those changes


----------



## yrelbirb

Veii said:


> I've read it, but this is awkward
> It would be good to compare SiSandra Graphs visually between both modes
> I had a very awkward still not resolved issue with a buggy bios/SMU version back then
> enabling performance enchancer would kill about 180-200cb in R15
> But can confirm on a 2700X that it does work well - when it works
> Check this gallery:
> https://imgur.com/gallery/d2KWrBM
> This was far back then, but i've seen this happening also on ASRock B450M Pro4
> It was strongly noticable on L3 latency increase but cinebench revealed it
> 
> Can you try if you can replicate the drop in performance in Cine R15 too ?
> Else yes something must behave very strange to lose that much FPS out of nowhere
> A visual SiSandra benchmark would show what it changed
> The only way i resolved it was mod another bios, because SMU transplants are annoying
> 
> If you can replicate that R15 point drop, maybe it's time to switch the bios
> It shouldn't be thaat bad, at max you'd feel 1-2fps difference on games that don't utilize the cpu much
> While there should be an increase, not a drop
> 
> Timings:
> Don't go tRRDL 4 unless you rock tight timings , 14-16-20 is not tight
> It will have negative effects only , but this is theory
> Real difference will only be shown by SiSandra or DRAM Memtest-Benchmark
> Try 4-5, or go back to 4.6 again
> About tRAS & tRC - sure you have wasted delay, but you need to test yourself if you can remove wasted delay while keeping memory error free
> Non B-Dies can need this type of delay on tRC
> tRAS should be at best always a clean transition
> Which you have: tCL+tWR+2 or 4 & tCL + tCRD WR
> 
> Need to crosstest a lot of combinations what leads to better perf on SiSandra
> Focus on inter-core latency too , not only bandwidth
> Then later you can lower tWR to 14, and push tRAS to 34
> If it errors, take away two also from tRC and fix tRFC afterwards
> It shouldn't error on excessive delay but over +4 it can error
> 
> As you have GDM enabled, try to play only with even values
> tWRRD 4 likely performs better on this set than tWRRD 3
> Nothing else to judge - all is try and error, tRTP of 6 would be beneficial, but only at the end after everything else
> tCKE 1 would be better than 8, 6 might work but this is IC dependent
> 
> After all this above, your next goal is tRCD RD 18



Hello veiii; i tried other timings; They work ok for now (booted, will do an hci memtest for long and return to you=)))

TRCDrd 18 doesn't even boot; needed cmos reset 

;;;;;;;;;

for cb_Gentle thing;

cb gentle cb15 score = 1745
non cb gentle cb15 score = 1711


some other benhmarks including si sandra;

https://imgur.com/a/mWzWLWT


;
drop on ac odessay is brutal  ;;

a noticeable drop on cpuz benchmark as well. not that much for cinebench15 but im sure its not a marginal error; i tested a couple of times always 30-50 point trailing behind with cb_gentle applied


----------



## Veii

@yrelbirb have you considered downgrading ?
Staying with 2nd gen only till 1003ABBA ?
1003ABBA is fine for 1st and 2nd gen , 1004B is rarely fine for first gen and often even buggy for 1004B
Memory training is messed up on 1004B - with their fix to "decrease start-up delay" 
Strongly would suggest not to use it , unless needed - and if needed then with fixed PHY memory training (increased training delay to 10/A as hex value) ~ under AMD CBS (likely DF or NBIO)

Your shown SiSandra screenshot is a bit messy
Dual CCX units will always show two graphs between one test - be sure it only shows one test
Also enable local score view only from the sorting options down bellow
It's there for comparisons ~ it's not in your interest to compare stock online results or even intel results
If you want to exactly compare with PE and non PE - be sure to say which is what
For you, RED is the current run color - soo be sure if you compare both to say what run was which color 
Example of readable illustration:


Spoiler











This was illustration between SCL 2 and 3
(While i hit 64GB/s afterwards)


Keep it that way, at the bottom it allows you to switch displaying mode too

I wonder if it rly isn't messed up on this bios
This is how it has to look if PE works fine
Sorry for the bad picture, i got it that way delivered
Focus on L3 cache delay


Spoiler



60.8ns memory, 8.8ns L3 on 4.3 PBO








61.6ns memory, 9.2ns L3 on 4.1250 PBO









Default was around 10.2-10.3ns L3 without PE


----------



## Veii

werks said:


> Hi guys, recently switched to amd after years of intel.
> 
> I would appreciate any feedback, good or bad, if i can improve my timings.
> tRC + tRCDRD is the lowest atm, any lower and it will not boot.
> 
> Cheers


Your tRAS is messed up
and how where you guided to run tWRWR SD/DD 4, while the rest is 1-1-1 ?
1.5v for 19nm Rev E , is brave ~ to say the least
1.5v JEDEC specification doesn't mean every IC under every nm node 
1.48v would be your room of movement, if not stability would likely be better near 1.44-1.46v

Really wonder where you got these timings from
because doesn't matter how low of a virtual value you put tRAS on, it will still hang in a "wait for command" loop with added delay by the board 
In other words, it's a placeholder without any function except potential instability and unclear added delay - where you have another unclear delay till tRC
To illustrate, current wasted delay is around:
tRAS 27+12=39 or maximum tRAS 33+12=45 about +10 wasted on tRC 
(IF tRAS would be correct)
You can put it +1, +2, +4 for stability, rarely even +8 - but +10 is just waste of delay after the board already does autocorrect your far too low tRAS

fix your tRAS, first most important thing
you can either run with direct no delay which would be:
tRAS 33, tRC 45, tRFC 450-334-206 
or as alternative
tRC 49, tRFC 490-364-224

But if it fails, it's your far to low tRP 
Because currently you have soo many wait-for-action delay, the chain has enough time to precharge cells and can be fine with this low delay
Likely tho in reality this would be too low and fail , because the value is a lie with unpredicted wasted delay 
Hopefully understandable~

Oh, Also while you are at fixing stuff
Put back that CWL 15 , tWRRD 3 - reboot and try if tRCD RD 17 or 16 would boot 
^ only after you fix your timings first, because right now it's a mess


----------



## yrelbirb

Veii said:


> @yrelbirb have you considered downgrading ?
> Staying with 2nd gen only till 1003ABBA ?
> 1003ABBA is fine for 1st and 2nd gen , 1004B is rarely fine for first gen and often even buggy for 1004B
> Memory training is messed up on 1004B - with their fix to "decrease start-up delay"
> Strongly would suggest not to use it , unless needed - and if needed then with fixed PHY memory training (increased training delay to 10/A as hex value) ~ under AMD CBS (likely DF or NBIO)
> 
> Your shown SiSandra screenshot is a bit messy
> Dual CCX units will always show two graphs between one test - be sure it only shows one test
> Also enable local score view only from the sorting options down bellow
> It's there for comparisons ~ it's not in your interest to compare stock online results or even intel results
> If you want to exactly compare with PE and non PE - be sure to say which is what
> For you, RED is the current run color - soo be sure if you compare both to say what run was which color
> Example of readable illustration:
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This was illustration between SCL 2 and 3
> (While i hit 64GB/s afterwards)
> 
> 
> Keep it that way, at the bottom it allows you to switch displaying mode too
> 
> I wonder if it rly isn't messed up on this bios
> This is how it has to look if PE works fine
> Sorry for the bad picture, i got it that way delivered
> Focus on L3 cache delay
> 
> 
> Spoiler
> 
> 
> 
> 60.8ns memory, 8.8ns L3 on 4.3 PBO
> 
> 
> 
> 
> 
> 
> 
> 
> 61.6ns memory, 9.2ns L3 on 4.1250 PBO
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Default was around 10.2-10.3ns L3 without PE


hmm what if i brick my mobo_? 

https://www.gigabyte.com/Motherboard/B450-Gaming-X-rev-10/support#support-dl-bios

this is my mobo, are u sure it is related to bios version,? my friend bricked his mobo once trying to return to an older bios so im a bit afraid on that. if its absoletely safe, which version do i go back? (im at f50 currently). since the mobo is low end and cant even show proper voltages, i afraid it might brick itself when downgrading (not so much confidence for the mobo here xd)

also; i have no train value under amd cbs , checked it up

and comparison si sandra;

https://prnt.sc/rvehwo

timings and %400 hci (bored )

https://prnt.sc/rveigy

lowered tras to 34 no problems

;;;

ok im really scared from bios thing now. my friend had a gigabyte b450m s2h. he once updated his bios and bricked his mobo (many more people did actually). then the vendors came out and said to not update bios bcoz it was known to brick it.

i guess overall : gigabyte is a failure. shouldn't have cheaped on mobo... big regret. :thumbsdow


----------



## Veii

yrelbirb said:


> hmm what if i brick my mobo_?
> 
> https://www.gigabyte.com/Motherboard/B450-Gaming-X-rev-10/support#support-dl-bios
> 
> this is my mobo, are u sure it is related to bios version,? my friend bricked his mobo once trying to return to an older bios so im a bit afraid on that. if its absoletely safe, which version do i go back? (im at f50 currently). since the mobo is low end and cant even show proper voltages, i afraid it might brick itself when downgrading (not so much confidence for the mobo here xd)
> 
> also; i have no train value under amd cbs , checked it up
> 
> and comparison si sandra;
> 
> https://prnt.sc/rvehwo
> 
> timings and %400 hci (bored )
> 
> https://prnt.sc/rveigy
> 
> lowered tras to 34 no problems
> 
> ;;;
> 
> ok im really scared from bios thing now. my friend had a gigabyte b450m s2h. he once updated his bios and bricked his mobo (many more people did actually). then the vendors came out and said to not update bios bcoz it was known to brick it.


I was thinking about this method, using internal bios updater always leads to funny bios bugs and suprises
Hmm there is no F42 requested for the B450 Gaming X
https://www.overclock.net/forum/11-...04-agesa-fw-stack-patched-bioses-3rd-gen.html
Maaybe if The Stilt is bored and you ask nicely - he could redo F41 to be working with ABBA
You have F42G, and likely this is also his answer - but i can remember their "destiny fix = PCIe 4.0 disable _fix_" lead to only issues
If you are lucky , The Stilt could do this request

Else you can also use 1usmus's tutorial with AFUEFI (afugan is for ASUS only)
https://www.overclock.net/forum/11-...yzen-bios-mods-how-update-bios-correctly.html
and that way clean downgrade 
You have couple of options to clean downgrade
But using the internal updater will make issues


----------



## yrelbirb

this might be too much form meh i guess ; i will likely bork something haha  better go on to try a little bit more tighten timings and be done with it i guess , have to leave low latency intercore in the table for now :w

, im sorry that i responded like this; nothing personnal, i just dont havve the confidence in me and in my board and i think i wouldnt want to bother those people too 

damn tRCD wont go to 18 

i think it comes down to luck , no? everyone in my local forum was surprised when i say them 3200 cl14 booted and stable (max i did %2200 though)

, it shocked me as well. luck i guess. and unluck when it come to trcd. but i guess trcd bottlenecks the ram heavy as well. i feel like lowering tRP from 20 to 14 have no effect on latency at all (be it sandro or, aida)

i would also extra question;

you say if i enable geardown, my 19 tRCD goes up to 20 (but shows 19)

but when i set tCL13 from bios, it is also seen as tcl 14 in windows (so geardown in effect)

are we sure that geardown affects tRCD in my case?


----------



## Veii

yrelbirb said:


> this might be too much form meh i guess ; i will likely bork something haha  better go on to try a little bit more tighten timings and be done with it i guess , have to leave low latency intercore in the table for now :w
> 
> , im sorry that i responded like this; nothing personnal, i just dont havve the confidence in me and in my board and i think i wouldnt want to bother those people too
> 
> i would also extra question;
> you say if i enable geardown, my 19 tRCD goes up to 20 (but shows 19)
> but when i set tCL13 from bios, it is also seen as tcl 14 in windows (so geardown in effect)
> are we sure that geardown affects tRCD in my case?


Very sure, you don't see hidden delay but GDM does round up odd timings
And GDM uses tCKE where tRFC2 and tRFC4 accuracy start to play a big role 
Also tCWL=tCL with GDM enabled
Far better to have it off - it's annoying enabled

But 3200MT/s is not high at all for 2nd gen, 3600-3733 should be your focus
If you read the #4 on the FW Collection thread, it shows a demonstration example how it will look and what it does
This is a clean SPI flash, which means everything including any kind of serial number will be wiped - soo a backup is important for warranty purposes and for transferring serial number + mac adress
In short, keeping warranty up ~ because it's a hardware clean flash, no traces left

Unless you can run tCL 12 on 3200 or 3400, there is no reason to stay with 3200CL14
It makes more sense to up it to 3400-3600 MT/s at least


----------



## yrelbirb

Veii said:


> Very sure, you don't see hidden delay but GDM does round up odd timings
> And GDM uses tCKE where tRFC2 and tRFC4 accuracy start to play a big role
> Also tCWL=tCL with GDM enabled
> Far better to have it off - it's annoying enabled
> 
> But 3200MT/s is not high at all for 2nd gen, 3600-3733 should be your focus
> If you read the #4 on the FW Collection thread, it shows a demonstration example how it will look and what it does
> This is a clean SPI flash, which means everything including any kind of serial number will be wiped - soo a backup is important for warranty purposes and for transferring serial number + mac adress
> In short, keeping warranty up ~ because it's a hardware clean flash, no traces left
> 
> Unless you can run tCL 12 on 3200 or 3400, there is no reason to stay with 3200CL14
> It makes more sense to up it to 3400-3600 MT/s at least


well you have a point but even though i tried 1.45v at same timings, i get instant errors for 3400 mhz , i tried following that 1usmus guide in techspot, loose timings etc, played around rzq values and some proocdt values (tried every alternative set in dram calc), ram cant get okay with 3400 mhz or maybe my imc is not good quality enough so no idea

tried some tCL12 but it also shows same behaviour with trcd , it doesnt boot at all. i tried 1.45 v in hopes of maybe it scales with voltage but no luck


----------



## rastaviper

@Veii have u considered creating a shared excel file where u will include all these different combinations for Tras, Tcke etc
I think it will save u a massive amount of time from writing all the timings every time by hand.
U could easily assign different timings depending on the layout (A0, A1 etc) for different freq (3200, 3400 etc)

Personally I tried to keep up with your recommendations but I got lost with all the long posts.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Veii

rastaviper said:


> @Veii have u considered creating a shared excel file where u will include all these different combinations for Tras, Tcke etc
> I think it will save u a massive amount of time from writing all the timings every time by hand.
> U could easily assign different timings depending on the layout (A0, A1 etc) for different freq (3200, 3400 etc)
> 
> Personally I tried to keep up with your recommendations but I got lost with all the long posts.


https://www.overclock.net/forum/13-...membench-0-8-dram-bench-699.html#post28395252
^ 
For presets , you have pretested ones by 1usmus 
He has the kits infront of him, and can do the test
I can only teach what i learned by myself ~ my current ryzen is dead 
But this sheet is not ready
The only collection of information i can give is this post:
https://www.overclock.net/forum/11-...chi-overclocking-thread-705.html#post28246564

Else you can find enough resources here:
https://github.com/integralfx/MemTestHelper/blob/master/DDR4 OC Guide.md
and 
https://reddit.com/r/overclocking/comments/ahs5a2/demystifying_memory_overclocking_on_ryzen_oc/
^ for explaining timings
The manual mode way you can use 1usmus advices on techpowerup 
and this is the reddit OPs personal method for lowering latency
https://docs.google.com/document/d/1yIZ_jWPHQX0VJOPUpK_p0meg7i7omyL42GwhQo6peNg/edit?usp=sharing

My methods are different and more math focused - but flawed
Flawed because i still don't know the exact timings movement steps between each timing, to fully switch to ns only
so far it's an ETA method for calculation with tRFC being quite fine, but also not perfect because it misses exact tSTAG calculation (that depends on layers and PCB revision)

Long posts are there to teach people and simplify things
Above linked resources are explained and recommended methods
At the end you have to learn it yourself, not depend on gifted timings
1usmus gifts timings on his calculator if you want gifts
But it's still recommended to learn it by yourself, not count on others


----------



## yrelbirb

Veii said:


> https://www.overclock.net/forum/13-...membench-0-8-dram-bench-699.html#post28395252
> ^
> For presets , you have pretested ones by 1usmus
> He has the kits infront of him, and can do the test
> I can only teach what i learned by myself ~ my current ryzen is dead
> But this sheet is not ready
> The only collection of information i can give is this post:
> https://www.overclock.net/forum/11-...chi-overclocking-thread-705.html#post28246564
> 
> Else you can find enough resources here:
> https://github.com/integralfx/MemTestHelper/blob/master/DDR4 OC Guide.md
> and
> https://reddit.com/r/overclocking/comments/ahs5a2/demystifying_memory_overclocking_on_ryzen_oc/
> ^ for explaining timings
> The manual mode way you can use 1usmus advices on techpowerup
> and this is the reddit OPs personal method for lowering latency
> https://docs.google.com/document/d/1yIZ_jWPHQX0VJOPUpK_p0meg7i7omyL42GwhQo6peNg/edit?usp=sharing
> 
> My methods are different and more math focused - but flawed
> Flawed because i still don't know the exact timings movement steps between each timing, to fully switch to ns only
> so far it's an ETA method for calculation with tRFC being quite fine, but also not perfect because it misses exact tSTAG calculation (that depends on layers and PCB revision)
> 
> Long posts are there to teach people and simplify things
> Above linked resources are explained and recommended methods
> At the end you have to learn it yourself, not depend on gifted timings
> 1usmus gifts timings on his calculator if you want gifts
> But it's still recommended to learn it by yourself, not count on others



do you mind if i ask how your ryzen died?


----------



## Veii

yrelbirb said:


> do you mind if i ask how your ryzen died?


IMC died, by overcurrent spike of my old PSU
House surge installation was triggered by my roommate, the anti shock surge one 
(idk the name of it)
Soo by the forced loss of power and later turned on one, my powersupply did sacrifice itself, but it took the memory controller with it
It was mid TM5 test, soo full 1.15v was into it 
I was testing if i can get 3600 stable, but this needed 1.175v SOC on 1st gen

This tiny 50mV more or how much more leaked, killed the memory controller of it
Actually it did work for 2 days, first taichi stopped recognizing it but i could still get my place on SiSandra with the modded tomahawk
Later on the next day after another coldboot , it fully said bye 
Soo degredation for 24-48hours by this overcurrent spike while full load was applied 
Served me well this tiny cpu 
Was lapped, and the first batch which retailed for 350ish bucks 
Soo also a horrible overclocker and still good toy


----------



## Redwoodz

nick name said:


> For whatever reason I get much more DRAM voltage droop (at least as HWiNFO reports) than I did with my 2700X. It was pretty much non-existent with the 2700X. 1.5V droops to 1.48V and it wasn't something I noticed during my initial testing. Makes me wonder if it may have been the culprit for some of my overnight test errors.





rares495 said:


> I never checked this but it could be the cause of my error as well.


 Your VDDPv will affect this I believe.



yrelbirb said:


> do you mind if i ask how your ryzen died?


 Hey bud don't worry about 1.5v. YOU WILL NEVER DEGRADE your cpu with boost frequencies & voltage. Heat induced by high power draw is where you will degrade your chip.If it is boosting it is not under load. That's how it works. 

Secondly your monitoring software does not work fast enough to show you all of the minute adjustment in power every millisecond. A thousand times per second.

Thirdly remember after you get everything in bios set Windows can change your power plan behavior. Make sure you have Windows power plan set to performance or whatever you wish.

I simply set a manual over clock and enable Cool & Quiet. Works great.


----------



## 2600ryzen

Veii said:


> Very sure, you don't see hidden delay but GDM does round up odd timings
> And GDM uses tCKE where tRFC2 and tRFC4 accuracy start to play a big role
> Also tCWL=tCL with GDM enabled
> Far better to have it off - it's annoying enabled
> 
> But 3200MT/s is not high at all for 2nd gen, 3600-3733 should be your focus
> If you read the #4 on the FW Collection thread, it shows a demonstration example how it will look and what it does
> This is a clean SPI flash, which means everything including any kind of serial number will be wiped - soo a backup is important for warranty purposes and for transferring serial number + mac adress
> In short, keeping warranty up ~ because it's a hardware clean flash, no traces left
> 
> Unless you can run tCL 12 on 3200 or 3400, there is no reason to stay with 3200CL14
> It makes more sense to up it to 3400-3600 MT/s at least



GDM means your IMC is still running at 1t though doesn't it? I get better bandwidth and I think lower intercore latency with GDM enabled and it feels faster(dragging a windows around the desktop is much smoother and easier to read the window contents with GDM). With 2t I get worse bandwidth but better RAM latency.


----------



## 2600ryzen

Anything I could do to reduce TRCDRD/TRP, and also wondering if I set TRFC correctly - I used 9 x TRC because 8 x TRC wouldn't post. Also how do I set TRFC2/4? Are they a multiple of TRC too?
This is 25nm Spectek A-die, it's mean to be [email protected] but my motherboard can't post above 2933mhz.


----------



## hazium233

2600ryzen said:


> GDM means your IMC is still running at 1t though doesn't it? I get better bandwidth and I think lower intercore latency with GDM enabled and it feels faster(dragging a windows around the desktop is much smoother and easier to read the window contents with GDM). With 2t I get worse bandwidth but better RAM latency.


Sort of, it overrides the command rate setting. The command / address is running at 1/4 data rate or "twice as slow" as the clock, and commands only go in on even clocks as a result. Been referred to as "1.5t" sometimes.

There is a little article about it here. *There is a bit on the reddit wiki too.



2600ryzen said:


> Anything I could do to reduce TRCDRD/TRP, and also wondering if I set TRFC correctly - I used 9 x TRC because 8 x TRC wouldn't post. Also how do I set TRFC2/4? Are they a multiple of TRC too?
> This is 25nm Spectek A-die, it's mean to be [email protected] but my motherboard can't post above 2933mhz.


I don't know enough about Rev A (either the 4Gb or 8Gb). For the other 8Gb Micron revisions (B, D, E..) tRCDRD usually seems to have pretty limited voltage scaling. So you can try extra vdimm, but it may not work in a practical range of voltage.

Another voltage that might be worth attempting is VPP Mem (default 2.5) in steps up to 2.525 or 2.53.


----------



## 2600ryzen

Is it better for TRP to be lower than TRCDRD or the other way around? Depending on TRDWR I can run TRCDRD/TRP at either 16/17 or 17/16.


----------



## hazium233

2600ryzen said:


> Is it better for TRP to be lower than TRCDRD or the other way around? Depending on TRDWR I can run TRCDRD/TRP at either 16/17 or 17/16.


Assuming they are both stable, I am not so sure the difference would matter in practice. I would wonder if this is a real dependency, or has to do with minimum row cycle.

Lower tRCDRD would have a little bit better latency to first word for page empty. Otherwise, it should be the same.


----------



## KevyMatts

Hi guys 

@Veii was helping me out.

I'm still gettings errors running TM5 but not Karhu. 

Any suggestions 

thanks


----------



## Veii

2600ryzen said:


> GDM means your IMC is still running at 1t though doesn't it? I get better bandwidth and I think lower intercore latency with GDM enabled and it feels faster(dragging a windows around the desktop is much smoother and easier to read the window contents with GDM). With 2t I get worse bandwidth but better RAM latency.


Yes, normally 2T is slower. But you are dependent on 2 steps of values either tCL 14 or tCL16 which is about 0.12-0.15v difference between them
Having GDM disabled is helpful a lot,
You can run odd timings and finetune it better - where even with 2T it will perform better with lower timings
Than higher timings GDM enabled
But no GDM is far more stress to these chips - soo first is to test at what voltage the lower CL can even boot and what is minimum voltage for post - be it just a bluescreen
Later after your know your min/max limits, you can try to stabilize with higher timings GDM off and then see if 2T is needed or 1T could run 
Hard to say, but GDM off 2T without work is far worse then GDM on tCKE 1 with low tRFC


2600ryzen said:


> Is it better for TRP to be lower than TRCDRD or the other way around? Depending on TRDWR I can run TRCDRD/TRP at either 16/17 or 17/16.
> 
> 
> hazium233 said:
> 
> 
> 
> Assuming they are both stable, I am not so sure the difference would matter in practice. I would wonder if this is a real dependency, or has to do with minimum row cycle.
> Lower tRCDRD would have a little bit better latency to first word for page empty. Otherwise, it should be the same.
Click to expand...

Wondered that too, pre'charge delay is technically a fixed introduced delay for slower cells to recharge
while lower tRCD WR means just snappier lower delays before start of write cycle - but is dependent on tRP (kinda) if it has enough voltage already and can supply these one in time

Normally if you reverse them - tRP would need to be +1 of a delay, if not even +2
I've thought about it, because it can help lower tRAS that way (same as tCL can help) 
And tRAS has a big effect on timing efficiency aka higher bandwidth - although tWR, tRTP and tRC do great work too

Someone has to try and study it a bit more
Someone who already understands how to fix this 5 points:
tRDWR, tRAS, tRC, tRFC, tWR - after changing first 3 timings 
It should have a positive effect, but i think it's not predictable as value
Because tCL, tRCD, tRP are unique independent values based on IC, PCB and Voltage
Haven't gotten up with a prediction how to get these without trial and error - as they are unique per kit


Redwoodz said:


> Your VDDPv will affect this I believe.


it shouldn't
VDDP doesn't influence maximum FCLK, nor will it make any difference before 4200-4500MT/s
but it does influence signal integrity and likely procODT has a connection with it
VDDG and VDDG IOD (Mainboard) would influence it, same as vSOC will (if not set correctly after VDDG)


----------



## yrelbirb

btw here with your latest suggestions; 

i have a sneaky suspicion that it never runs at the rated tras... it might be why tRC doesnt work below 56 as well

you see, i can go down to 21 and still past %1000 on hci memtest

board is probably substuting some random number for tras maybe even for other timings... how can i be sure that i uses the tras "i set"=?

https://prnt.sc/rwrouv

should twr be = trp*2?

trcdwr = 14
trdwr = 7 (soo trdwr*2 trcdwr 14 i guess=?)
and twdrd auto , it set to 1

scl's are still weirdly at 2 and stable, no issues :O


----------



## 2600ryzen

yrelbirb said:


> btw here with your latest suggestions;
> 
> i have a sneaky suspicion that it never runs at the rated tras... it might be why tRC doesnt work below 56 as well
> 
> you see, i can go down to 21 and still past %1000 on hci memtest
> 
> board is probably substuting some random number for tras maybe even for other timings... how can i be sure that i uses the tras "i set"=?
> 
> https://prnt.sc/rwrouv
> 
> should twr be = trp*2?
> 
> 
> 
> trcdwr = 14
> trdwr = 7 (soo trdwr*2 trcdwr 14 i guess=?)
> and twdrd auto , it set to 1
> 
> scl's are still weirdly at 2 and stable, no issues :O





I find for a few timings if I lower them too far they don't give errors just perform worse at benchmarks. I can run trdrdscl and twrwrscl at 2 without errors but 4 gives me better benches(I use 1 pass of the first 6 tests of memtest86 to bench it because it can't be interrupted by background processes). Same with trrds/l.


----------



## 2600ryzen

My [email protected] kit errors horribly on test 8 in memtest86 if I go 3066mhz or above(I think because I'm on zen+ and my board doesn't officially support above 2933mhz speed), I rediscovered my stable settings playing with drvstrength and memsetup. Changing Memcsodtsetup to 1 from 0 reduced the errors by over half and changing Memcadbusckedrvstren to 20 got rid of them entirely. Anything else I did seemed to make it worse.
Managed to get [email protected] 1000%(10 cycles) stable in testmem5 with 1.48v. Still wont cold boot though.


----------



## Veii

yrelbirb said:


> btw here with your latest suggestions;
> 
> i have a sneaky suspicion that it never runs at the rated tras... it might be why tRC doesnt work below 56 as well
> 
> you see, i can go down to 21 and still past %1000 on hci memtest
> 
> board is probably substuting some random number for tras maybe even for other timings... how can i be sure that i uses the tras "i set"=?
> 
> https://prnt.sc/rwrouv
> 
> should twr be = trp*2?
> 
> trcdwr = 14
> trdwr = 7 (soo trdwr*2 trcdwr 14 i guess=?)
> and twdrd auto , it set to 1
> 
> scl's are still weirdly at 2 and stable, no issues :O


It's reverse
tRDWR for tRCD RD , tWRRD for tRCD WR

tWR is unique 
Optimally it's a clean divider of tRFC, and tRTP is optimally half of tWR
tWR can be equal to tCL , or used the formular 8ns*MT/s div 2000 = optimal tWR 
also tWR has to stay an even value
3033MT/s = 3034MT/s in reality


----------



## rares495

Veii said:


> It's reverse
> tRDWR for tRCD RD , tWRRD for tRCD WR
> 
> tWR is unique
> Optimally it's a clean divider of tRFC, and tRTP is optimally half of tWR
> tWR can be equal to tCL , or used the formular 8ns*MT/s div 2000 = optimal tWR
> also tWR has to stay an even value
> 3033MT/s = 3034MT/s in reality


So if 3800MT/s optimal tWR would be 16, right? Also cuz of my tRFC 240/16=15 clean.

Then tRTP = 8, but does 10-6 instead of 12-8 or 16-8 add latency?


----------



## yrelbirb

ahahaha so i got it reverse; but ram still works ok? is it supposed to crash ?


----------



## PolRoger

Veii said:


> Very sure, you don't see hidden delay but GDM does round up odd timings
> And GDM uses tCKE where tRFC2 and tRFC4 accuracy start to play a big role
> Also tCWL=tCL with GDM enabled
> Far better to have it off - it's annoying enabled


tCWL=tCL with GDM enabled? Is this true??

I was originally running some settings @3600C16 with GDM disabled and now I'm running at 3733C16 with GDM enabled. 

I've noticed that if I change tCWL from 12 to 13 with GDM enabled it will round up to 14. So if one were to set even number tCWL settings below tCL 16 with GDM... tCWL will still actually be running at 16?


----------



## 2600ryzen

PolRoger said:


> tCWL=tCL with GDM enabled? Is this true??
> 
> I was originally running some settings @3600C16 with GDM disabled and now I'm running at 3733C16 with GDM enabled.
> 
> I've noticed that if I change tCWL from 12 to 13 with GDM enabled it will round up to 14. So if one were to set even number tCWL settings below tCL 16 with GDM... tCWL will still actually be running at 16?



On my kit I can run Tcwl 2 below Tcl so 12/14. If I try Tcwl 1 below Tcl it gets rounded up to 14. Can't recall benchmarking it to test if it's actually faster though I do get slightly higher write bandwidth vs read bandwidth.


----------



## Veii

rares495 said:


> So if 3800MT/s optimal tWR would be 16, right? Also cuz of my tRFC 240/16=15 clean.
> 
> Then tRTP = 8, but does 10-6 instead of 12-8 or 16-8 add latency?


tWR 10 is still an unclear topic
It has to have bad performance, and you can't lower on this bios tRTP under 6, same as tWR under 10 doesn't work (for whatever reason)
But low tWR can be helped with low tRAS
12-6 is still a golden middle point , while the advice of tWR being 8ns of x MT/s is valid
1usmus seem to have better results with tWR12 - very unsure if tWR 10 does help at all 
It works and does it's job, but if lower tRAS has positive effects needs to be tested per person
This set, behaved far worse


Spoiler














Than this set:


Spoiler














Only difference was tWR, and higher tRRDL 
Lowest is not always the best - and 4-4 instead of 4-5 on tRRDS can have negative results
1usmus is pretty clear, benchmark timings - low doesn't mean good ^^'

Both tWR's where not a perfect divider of tRFC here, and optimally tRTP of half tWR does work better
But the difference between this two sets was about 5gb/s bandwidth - while both where perfectly stable


PolRoger said:


> tCWL=tCL with GDM enabled? Is this true??
> 
> I was originally running some settings @3600C16 with GDM disabled and now I'm running at 3733C16 with GDM enabled.
> 
> I've noticed that if I change tCWL from 12 to 13 with GDM enabled it will round up to 14. So if one were to set even number tCWL settings below tCL 16 with GDM... tCWL will still actually be running at 16?


Very sure
Rounding it does anyways , but GDM uses tCWL=tCL and uses tCKE
Where we go into the mystery topic of tSTAG and tMRD which all influence tCKE behavior
Soo if you use GDM, be sure that tRFC2 and 4 are correct - as this influences tSTAG results and tSTAG is used to calculate tRFC
Just a back and forth bahaviour - get tRFC correct then tCKE will work as intentionally
Sometimes tCKE 6 can have positive effects, sometimes even 8 - else 1 always leads to better results unless exceptions happen


----------



## Joseph Mills

Who wants to take a stab at this?


I'm trying to get down to 3466Mhz CL14, from a stable 3466Mhz CL16. I keep hitting errors in TM5 on test 4 and 6 within the first 10 minutes. Can't seem to find out where the errors are coming from.

My rig: 3800X, Aorus Elite x570, 4x16 TridentZ 3200C15 dual rank


Current settings:


----------



## Joseph Mills

Joseph Mills said:


> Who wants to take a stab at this?
> 
> 
> I'm trying to get down to 3466Mhz CL14, from a stable 3466Mhz CL16. I keep hitting errors in TM5 on test 4 and 6 within the first 10 minutes. Can't seem to find out where the errors are coming from.
> 
> My rig: 3800X, Aorus Elite x570, 4x16 TridentZ 3200C15 dual rank
> 
> 
> Current settings:



The issue ended up being not enough DRAM voltage. I bumped it up to 1.43v (1.452v in HWinfo), and no errors came up.


----------



## werks

Veii said:


> Your tRAS is messed up
> and how where you guided to run tWRWR SD/DD 4, while the rest is 1-1-1 ?
> 1.5v for 19nm Rev E , is brave ~ to say the least
> 1.5v JEDEC specification doesn't mean every IC under every nm node
> 1.48v would be your room of movement, if not stability would likely be better near 1.44-1.46v
> 
> Really wonder where you got these timings from
> because doesn't matter how low of a virtual value you put tRAS on, it will still hang in a "wait for command" loop with added delay by the board
> In other words, it's a placeholder without any function except potential instability and unclear added delay - where you have another unclear delay till tRC
> To illustrate, current wasted delay is around:
> tRAS 27+12=39 or maximum tRAS 33+12=45 about +10 wasted on tRC
> (IF tRAS would be correct)
> You can put it +1, +2, +4 for stability, rarely even +8 - but +10 is just waste of delay after the board already does autocorrect your far too low tRAS
> 
> fix your tRAS, first most important thing
> you can either run with direct no delay which would be:
> tRAS 33, tRC 45, tRFC 450-334-206
> or as alternative
> tRC 49, tRFC 490-364-224
> 
> But if it fails, it's your far to low tRP
> Because currently you have soo many wait-for-action delay, the chain has enough time to precharge cells and can be fine with this low delay
> Likely tho in reality this would be too low and fail , because the value is a lie with unpredicted wasted delay
> Hopefully understandable~
> 
> Oh, Also while you are at fixing stuff
> Put back that CWL 15 , tWRRD 3 - reboot and try if tRCD RD 17 or 16 would boot
> ^ only after you fix your timings first, because right now it's a mess


Thank you for the feedback. how about now? lowered to 1.44v
tried tRCDRD 17, too many errors within 10 secs


----------



## PolRoger

GDM uses tCWL=tCL… ??



Veii said:


> Very sure
> Rounding it does anyways , but GDM uses tCWL=tCL and uses tCKE
> Where we go into the mystery topic of tSTAG and tMRD which all influence tCKE behavior
> Soo if you use GDM, be sure that tRFC2 and 4 are correct - as this influences tSTAG results and tSTAG is used to calculate tRFC
> Just a back and forth bahaviour - get tRFC correct then tCKE will work as intentionally
> Sometimes tCKE 6 can have positive effects, sometimes even 8 - else 1 always leads to better results unless exceptions happen


I guess it make no sense then to run/enter a lower tCWL than CAS with GDM on...

I decided to run three different AIDA memory benchmarks to compare... Although I'm not seeing too much difference between them? Maybe with GDM disabled it is showing slightly better COPY results?

3733C16 tCWL 16 GDM on
3733C16 tCWL 12 GDM on
3733C16 tCWL 12 GDM disabled

TRFC for all three runs @288-192-128


----------



## Veii

PolRoger said:


> GDM uses tCWL=tCL… ??
> 
> 
> 
> I guess it make no sense then to run/enter a lower tCWL than CAS with GDM on...
> 
> I decided to run three different AIDA memory benchmarks to compare... Although I'm not seeing too much difference between them? Maybe with GDM disabled it is showing slightly better COPY results?
> 
> 3733C16 tCWL 16 GDM on
> 3733C16 tCWL 12 GDM on
> 3733C16 tCWL 12 GDM disabled
> 
> TRFC for all three runs @288-192-128


GDM on allows for less stress onto memory, but GDM off allows you to finetune timings better
On a direct comparison GDM on would be slower - but sometimes GDM on allows CL14 to run
Else GDM disabled allows CL15-15 to run or overall odd values to be used for more finetuning

If the kit can run GDM off, stay on it - it's better
But some kits need GDM on 
GDM off 2T is also a bit better than GDM on - not one to one compared, but because with GDM you have more control to lower timings
There is no correct answer, use what the kits allow 
If GDM 2T is the only option, pick that rather than GDM on - unless you can drop tCL -2 with GDM on


----------



## Dollar

@Veii can you comment on the BGS setting? The dram calc suggests enabling this with 4x8GB single rank sticks. If I enable BGS I always see a small drop in performance. Is this expected? If I leave BGS on auto then it stays disabled. (c6h motherboard)


----------



## rares495

Veii said:


> tWR 10 is still an unclear topic
> It has to have bad performance, and you can't lower on this bios tRTP under 6, same as tWR under 10 doesn't work (for whatever reason)
> But low tWR can be helped with low tRAS
> 12-6 is still a golden middle point , while the advice of tWR being 8ns of x MT/s is valid
> 1usmus seem to have better results with tWR12 - very unsure if tWR 10 does help at all
> It works and does it's job, but if lower tRAS has positive effects needs to be tested per person
> This set, behaved far worse
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Than this set:
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Only difference was tWR, and higher tRRDL
> Lowest is not always the best - and 4-4 instead of 4-5 on tRRDS can have negative results
> 1usmus is pretty clear, benchmark timings - low doesn't mean good ^^'
> 
> Both tWR's where not a perfect divider of tRFC here, and optimally tRTP of half tWR does work better
> But the difference between this two sets was about 5gb/s bandwidth - while both where perfectly stable


This is where I'm currently at. Retested today and passed 10k karhu w/ cache in ~1h 35min. Did a Sandra test and the results were worse than my previous stable 13-27. 

And of course I've been trying to get tRDWR lower than 8 and tRCDRD lower than 15 and no success as usual. GDM on does nothing. 2T does nothing. Even played with cad_bus timing values and my kit seems to not care about those and any resistance value whatsoever. Will post with anything or not post with anything. There's no setting that will make the system post when others won't and vice versa.

Next I will test with tWR 12, tRTP 6 and 12-8, 16-8.


----------



## yrelbirb

is tRTP 6 and tWR 12 is a good spot for 3200 MT/s?
@Veii

should i use SiSandra memory bandwidth and latency tests for timing tweaking?

i cant afford aida64 rn 

or should i just focus on intercore lat and intercore band_


----------



## Veii

rares495 said:


> Next I will test with tWR 12, tRTP 6 and 12-8, 16-8.


You can try to push tWTRS and L both to 4, 


yrelbirb said:


> is tRTP 6 and tWR 12 is a good spot for 3200 MT/s?
> 
> should i use SiSandra memory bandwidth and latency tests for timing tweaking?
> 
> i cant afford aida64 rn
> 
> or should i just focus on intercore lat and intercore band_


You should use Sisandra for tweaking, Aida64 doesn't show this difference
Aida64 does show L2 and L3 bandwidth increase but that goes hand in hand with cpu OC
Main focus is Sisandra 
3200MT/s can run tRDWR up to 6 down - depends on memory kit 
You can focus get getting that down
And this tRTP 13 you showed before, was with GDM enabled, soo it was a 14 anyways 
if you can maintain tWR 12, you can focus on lowering tRAS and so also tRP 

But i see this WTR_S/L of 5-13 
Was this auto predicted ?
3-10 (useless), 4-12,5-14 are the steps 
if you stay with 5, use 14 as tWTR_L
tFAW here is *6 tRRDS, it's not 35 but should be 36
You can try to lower this down to 5* tRRDS instead 6*

Then later when everything is lower focus on getting that tRCD 22 away, maybe down to 20
While you are with GDM on

At the very end try for your kit tRRD_S/L 8-8 with same tFAW 36



Dollar said:


> @Veii can you comment on the BGS setting? The dram calc suggests enabling this with 4x8GB single rank sticks. If I enable BGS I always see a small drop in performance. Is this expected? If I leave BGS on auto then it stays disabled. (c6h motherboard)


BGS Alt is for 2 dimms
BGS is for 4 dimms on a dual channel board 
when using BGS, disable ALT else it will mess stuff up
also disable powerdown mode 

Where do you see this drop in perf
Can you replicate it ?
At best can you replicate a SiSandra Multi-Core efficiency (detailed) report between both results (local only)
And doublecheck with the memory benchmark on the DRAM Calculator
It could be seen as lower in bandwidth but still faster in reality as BGS does work well 
Very noticable if you disable BGS Alt on 2 dimm systems, perf will drop a lot


----------



## yrelbirb

yep its auto predict, nevermind it anyway

so i can maintan tWR 12 , tRTP 6 but my tRC is 56

doesn it cause desync? should i up my tRC to 60 ?

also; for tRCDRD 20 and tRCDWR 14

tRDWR should be 7 or so right? and tWDDR 1 or what?

since i cant tighten tRCDRD


----------



## Veii

yrelbirb said:


> yep its auto predict, nevermind it anyway
> 
> so i can maintan tWR 12 , tRTP 6 but my tRC is 56
> 
> doesn it cause desync? should i up my tRC to 60 ?
> 
> also; for tRCDRD 20 and tRCDWR 14
> 
> tRDWR should be 7 or so right? and tWDDR 1 or what?
> 
> since i cant tighten tRCDRD


Usually with low frequency you can go -2 under tRCD , or half tCL 
Normally math says tRCD RD 20 = tRDWR 10,1 or 10 + something added latency, oor 11-1 for stability
I don't know if you could drop to 7 actually , it can work keep tWRRD at 2 or 3
Math says tWRRD 5 , but i am very sure 7-5 wouldn't run, 8-5 could maybe run
Simply because both are too high which is against the ruleset and not how that works, you can try tho 

about tRC & tRFC :thinking: 
600 should work, but you can try to keep the same values
you don't increase any latency but lower timings, higher max tRFC shouldn't bother too much
too low will make issues 

Sync, desync - the formular on tRFC calculator is to have no board/cpu added delay sync
After tSTAG is calculated with it - you can see it as "limit" so far it's just "very helpful recommendation" 
You can focus to keep tWR a clean divider of tRFC - that optional rule is useful for stability


----------



## yrelbirb

Veii said:


> Usually with low frequency you can go -2 under tRCD , or half tCL
> Normally math says tRCD RD 20 = tRDWR 10,1 or 10 + something added latency, oor 11-1 for stability
> I don't know if you could drop to 7 actually , it can work keep tWRRD at 2 or 3
> Math says tWRRD 5 , but i am very sure 7-5 wouldn't run, 8-5 could maybe run
> Simply because both are too high which is against the ruleset and not how that works, you can try tho
> 
> about tRC & tRFC :thinking:
> 600 should work, but you can try to keep the same values
> you don't increase any latency but lower timings, higher max tRFC shouldn't bother too much
> too low will make issues
> 
> Sync, desync - the formular on tRFC calculator is to have no board/cpu added delay sync
> After tSTAG is calculated with it - you can see it as "limit" so far it's just "very helpful recommendation"
> You can focus to keep tWR a clean divider of tRFC - that optional rule is useful for stability


https://prnt.sc/rxag5r

am i lucky? 

i adjusted twr to 14, so it divides 560 (trfc)

trtp at 8 so it divies trc (56) 

trrwd 7 and twrrd 5 seems to work... weirdly

sisandra

https://prnt.sc/rxah9h


----------



## yrelbirb

btw i compiled some results with non tweaked and tweaked results in cpu bound benchmarks;

default mobo subtimings;
https://i.hizliresim.com/qT8T6Z.png
my tweaks;
https://i.hizliresim.com/pSHFTH.png

differences in games;

shadow of lara ; 

https://i.hizliresim.com/M18UZY.jpg

https://i.hizliresim.com/cxGBSR.jpg


ac odesa;

https://i.hizliresim.com/p3xAp8.jpg

https://i.hizliresim.com/COpJmQ.jpg

---

to me ,; these improvements makes the whole hassle worth... its almost can be counted as 0.1 ghz overclock ; just from sub timings

; of course they might be tweaked even further but gotta research more


----------



## Veii

yrelbirb said:


> https://prnt.sc/rxag5r
> 
> am i lucky?
> 
> i adjusted twr to 14, so it divides 560 (trfc)
> 
> trtp at 8 so it divies trc (56)
> 
> trrwd 7 and twrrd 5 seems to work... weirdly
> 
> sisandra
> 
> https://prnt.sc/rxah9h


Math would say it has to work, but it's odd 
Well now math wouldn't work, you add excessive delay 
7-3 would be for tRCD WR 14 
Although change TM5 config to 20 rounds in order to check instability 
3 is good and fine for fast tests - but the timings look already correct 
tRC is optimal value -2 , it would be hard to get it lower than that 

Just fix tWRRD a bit , unless you want to try 
14-16-18-14-32-46 / tRDWR 7 / tWRRD 4 / tRFC 552 / tWR 12 / tRTP 6 or 8


----------



## Veii

yrelbirb said:


> btw i compiled some results with non tweaked and tweaked results in cpu bound benchmarks;
> 
> default mobo subtimings;
> https://i.hizliresim.com/qT8T6Z.png
> my tweaks;
> https://i.hizliresim.com/pSHFTH.png
> 
> differences in games;
> 
> shadow of lara ;
> 
> https://i.hizliresim.com/M18UZY.jpg
> 
> https://i.hizliresim.com/cxGBSR.jpg
> 
> 
> ac odesa;
> 
> https://i.hizliresim.com/p3xAp8.jpg
> 
> https://i.hizliresim.com/COpJmQ.jpg
> 
> ---
> 
> to me ,; these improvements makes the whole hassle worth... its almost can be counted as 0.1 ghz overclock ; just from sub timings
> 
> ; of course they might be tweaked even further but gotta research more


6 avg fps is solid 
you get the biggest benefit from SCL and tRDWR 
then low tRCD helps 
Overall you have headroom, maaybe the new even lower timings could work 
that should give another 3fps at least


----------



## rares495

Veii said:


> You can try to push tWTRS and L both to 4,


No post with tWTRL 4,5,6 or 7.

What do you think about the score in Asus Mem TweakIt?

I get 92821 with tRP 13, tRAS 27 and 93269 with tRP 12, tRAS 28.


----------



## Veii

rares495 said:


> No post with tWTRL 4,5,6 or 7.
> 
> What do you think about the score in Asus Mem TweakIt?
> 
> I get 92821 with tRP 13, tRAS 27 and 93269 with tRP 12, tRAS 28.


Never used it :thinking:


----------



## rares495

Veii said:


> Never used it :thinking:


After setting tRCDWR to 11 I got a nice increase to 94793. The tool seems to focus on the main timings. Could you check your own score? (get the tool from Crosshair VIII thread in the utilities section)
@1usmus is this score relevant at all?


----------



## yrelbirb

Veii said:


> Math would say it has to work, but it's odd
> Well now math wouldn't work, you add excessive delay
> 7-3 would be for tRCD WR 14
> Although change TM5 config to 20 rounds in order to check instability
> 3 is good and fine for fast tests - but the timings look already correct
> tRC is optimal value -2 , it would be hard to get it lower than that
> 
> Just fix tWRRD a bit , unless you want to try
> 14-16-18-14-32-46 / tRDWR 7 / tWRRD 4 / tRFC 552 / tWR 12 / tRTP 6 or 8


hey; 46 tRC needs cmos reset ; same for 48 50 or 52 for that matter

52 boots but errors alot quickly in 1usmus memtest

how do i make it 20 rounds btw?

;;

same for tRCD (when others are normal values), needs cmoes reset for 18

maybe usmus right, maybe my mobo is faking tras? maybe its not 32 at all when set to that number, who knows


----------



## rastaviper

Veii said:


> You can try to push tWTRS and L both to 4,
> 
> 
> 
> You should use Sisandra for tweaking, Aida64 doesn't show this difference
> 
> Aida64 does show L2 and L3 bandwidth increase but that goes hand in hand with cpu OC
> 
> Main focus is Sisandra


You are mentioning to use Sandra for measuring and perfOrmance gains but I don't see anyone posting results from there!

So which test exactly should we use for memory optimising when we try different RAM timings?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Notbn

Can anyone give me some advice? I'm pretty new to memory tuning. At the current settings I get an error with Karhu about 40mins in. Ideally I'd like to run 3800CL16 stable. Current voltage is 1.45V on a MSI X570 Unify. Any advice to help stabilize? Kit is 16GB 4400CL19 Patriot Viper Steel



Thanks.


----------



## rares495

Notbn said:


> Can anyone give me some advice? I'm pretty new to memory tuning. At the current settings I get an error with Karhu about 40mins in. Ideally I'd like to run 3800CL16 stable. Current voltage is 1.45V on a MSI X570 Unify. Any advice to help stabilize? Kit is 16GB 4400CL19 Patriot Viper Steel
> 
> 
> 
> Thanks.


These exact timings will work. They were used by Buildzoid on the same kit (Viper Steel 4400C19). Try to pass 10000% Karhu with cache(advanced tab) and then we can talk about tightening them some more.

Remember to disable gear down mode, power down mode and bank group swap. Set Proc_ODT to 28.2 and CAD_Bus to 40-20-24-24. Voltage 1.5V and SOC Voltage 1.05V


----------



## KevyMatts

When i have GDM disabled I seem to be unstable with errors.

But when it's enabled it doesn't have errors. 

Also I'm running 4 sticks of 8gb so should have BGS enabled? And power down disabled?


----------



## Tobiman

After a few weeks on safe preset, i've bumped up the timings to 1usmus fast preset and the result is a bit better. Old aida64 score is below new score.


----------



## yrelbirb

same here; doesnt even boot without gdm actually


----------



## KevyMatts

yrelbirb said:


> same here; doesnt even boot without gdm actually



It's so frustrating


----------



## Dollar

Veii said:


> BGS Alt is for 2 dimms
> BGS is for 4 dimms on a dual channel board
> when using BGS, disable ALT else it will mess stuff up
> also disable powerdown mode
> 
> Where do you see this drop in perf
> Can you replicate it ?
> At best can you replicate a SiSandra Multi-Core efficiency (detailed) report between both results (local only)
> And doublecheck with the memory benchmark on the DRAM Calculator
> It could be seen as lower in bandwidth but still faster in reality as BGS does work well
> Very noticable if you disable BGS Alt on 2 dimm systems, perf will drop a lot



The small drop in performance can be seen in aida and DRAM calc benchmark. This post is going to be a mess....

3700x with no PBO using the stock cooler with a custom silent fan curve. Room temp stayed 25c during all tests.
Crosshair VI with the latest bios 7704 AM4 combo PI 1.0.0.4 patch B
4x8GB @3600 using 1usmus safe preset to avoid timing mistakes my the board or myself. Middle bin 4133 Patriot b-die a0 pcb. The BGS setting in Dram calculator correctly shows if it's enabled or disabled.


*AIDA BGS ON with BGS alt OFF - Average of five runs*
READ - 52,905 | COPY - 52,495 | LATENCY - 67.44


*AIDA BGS OFF with BGS alt ON - Average of five runs*
READ - 53,194 | COPY - 53,048 | LATENCY - 67.32


*Dram Calculator Benchmark 1.7.0 by 1usmus with BGS ON and BGS alt OFF average of four runs*
124.33 Seconds
67.52ns Custom Latency
68.77ns Random Latency
41.4Gb/s Read Speed


*Dram Calculator Benchmark 1.7.0 by 1usmus with BGS OFF and BGS alt ON average of four runs*
120.77 Seconds
67.35ns Custom Latency
68.7ns Random Latency
44.1Gb/s Read Speed



*Sandra multi-core efficiency test with BGS ON and BGS alt OFF. I ran it three times and posted the highest scoring run below*



Spoiler



SiSoftware Sandra

Benchmark Results
Inter-Core Bandwidth : 94.2GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Inter-Core Latency : 47.9ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Inter-Core Bandwidth : 5.89GB/s
No. Threads : 16
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 125.610W
Inter-Core Bandwidth : 767.99MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 3.81ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 295.52kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Inter-Core Bandwidth : 22.05MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 0.11ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 
U0-U2 Data Latency : 27.4ns
U0-U4 Data Latency : 28.0ns
U0-U6 Data Latency : 27.9ns
U0-U8 Data Latency : 71.2ns
U0-U10 Data Latency : 70.4ns
U0-U12 Data Latency : 71.3ns
U0-U14 Data Latency : 69.2ns
U0-U1 Data Latency : 11.6ns
U0-U3 Data Latency : 27.4ns
U0-U5 Data Latency : 28.0ns
U0-U7 Data Latency : 28.0ns
U0-U9 Data Latency : 70.7ns
U0-U11 Data Latency : 71.1ns
U0-U13 Data Latency : 71.0ns
U0-U15 Data Latency : 69.2ns
U2-U4 Data Latency : 27.2ns
U2-U6 Data Latency : 27.5ns
U2-U8 Data Latency : 69.0ns
U2-U10 Data Latency : 69.3ns
U2-U12 Data Latency : 68.0ns
U2-U14 Data Latency : 68.1ns
U2-U1 Data Latency : 26.9ns
U2-U3 Data Latency : 11.2ns
U2-U5 Data Latency : 27.3ns
U2-U7 Data Latency : 27.7ns
U2-U9 Data Latency : 68.8ns
U2-U11 Data Latency : 69.3ns
U2-U13 Data Latency : 69.5ns
U2-U15 Data Latency : 67.6ns
U4-U6 Data Latency : 27.3ns
U4-U8 Data Latency : 68.2ns
U4-U10 Data Latency : 68.6ns
U4-U12 Data Latency : 69.3ns
U4-U14 Data Latency : 69.1ns
U4-U1 Data Latency : 27.5ns
U4-U3 Data Latency : 27.2ns
U4-U5 Data Latency : 11.3ns
U4-U7 Data Latency : 27.3ns
U4-U9 Data Latency : 67.9ns
U4-U11 Data Latency : 69.3ns
U4-U13 Data Latency : 67.8ns
U4-U15 Data Latency : 69.2ns
U6-U8 Data Latency : 67.1ns
U6-U10 Data Latency : 69.8ns
U6-U12 Data Latency : 69.0ns
U6-U14 Data Latency : 67.7ns
U6-U1 Data Latency : 27.3ns
U6-U3 Data Latency : 27.6ns
U6-U5 Data Latency : 27.4ns
U6-U7 Data Latency : 11.2ns
U6-U9 Data Latency : 68.7ns
U6-U11 Data Latency : 68.1ns
U6-U13 Data Latency : 67.7ns
U6-U15 Data Latency : 65.9ns
U8-U10 Data Latency : 27.8ns
U8-U12 Data Latency : 27.7ns
U8-U14 Data Latency : 27.5ns
U8-U1 Data Latency : 69.6ns
U8-U3 Data Latency : 66.7ns
U8-U5 Data Latency : 66.2ns
U8-U7 Data Latency : 66.3ns
U8-U9 Data Latency : 10.9ns
U8-U11 Data Latency : 27.8ns
U8-U13 Data Latency : 27.7ns
U8-U15 Data Latency : 27.3ns
U10-U12 Data Latency : 27.9ns
U10-U14 Data Latency : 27.7ns
U10-U1 Data Latency : 64.9ns
U10-U3 Data Latency : 65.9ns
U10-U5 Data Latency : 66.1ns
U10-U7 Data Latency : 67.8ns
U10-U9 Data Latency : 27.8ns
U10-U11 Data Latency : 11.0ns
U10-U13 Data Latency : 27.6ns
U10-U15 Data Latency : 27.7ns
U12-U14 Data Latency : 27.8ns
U12-U1 Data Latency : 66.0ns
U12-U3 Data Latency : 67.9ns
U12-U5 Data Latency : 67.1ns
U12-U7 Data Latency : 64.2ns
U12-U9 Data Latency : 27.7ns
U12-U11 Data Latency : 27.6ns
U12-U13 Data Latency : 10.9ns
U12-U15 Data Latency : 27.7ns
U14-U1 Data Latency : 65.8ns
U14-U3 Data Latency : 64.8ns
U14-U5 Data Latency : 63.7ns
U14-U7 Data Latency : 65.4ns
U14-U9 Data Latency : 27.3ns
U14-U11 Data Latency : 27.7ns
U14-U13 Data Latency : 27.8ns
U14-U15 Data Latency : 10.9ns
U1-U3 Data Latency : 27.8ns
U1-U5 Data Latency : 27.7ns
U1-U7 Data Latency : 27.7ns
U1-U9 Data Latency : 69.0ns
U1-U11 Data Latency : 66.2ns
U1-U13 Data Latency : 67.5ns
U1-U15 Data Latency : 65.4ns
U3-U5 Data Latency : 27.8ns
U3-U7 Data Latency : 27.6ns
U3-U9 Data Latency : 66.1ns
U3-U11 Data Latency : 65.4ns
U3-U13 Data Latency : 65.1ns
U3-U15 Data Latency : 67.0ns
U5-U7 Data Latency : 27.4ns
U5-U9 Data Latency : 67.5ns
U5-U11 Data Latency : 68.3ns
U5-U13 Data Latency : 65.5ns
U5-U15 Data Latency : 68.9ns
U7-U9 Data Latency : 68.1ns
U7-U11 Data Latency : 69.5ns
U7-U13 Data Latency : 67.4ns
U7-U15 Data Latency : 64.3ns
U9-U11 Data Latency : 27.5ns
U9-U13 Data Latency : 27.7ns
U9-U15 Data Latency : 27.3ns
U11-U13 Data Latency : 27.6ns
U11-U15 Data Latency : 27.7ns
U13-U15 Data Latency : 27.8ns
1x 64bytes Blocks Bandwidth : 11.67GB/s
4x 64bytes Blocks Bandwidth : 19.9GB/s
4x 256bytes Blocks Bandwidth : 72.77GB/s
4x 1kB Blocks Bandwidth : 216.2GB/s
4x 4kB Blocks Bandwidth : 333.51GB/s
16x 4kB Blocks Bandwidth : 300.36GB/s
4x 64kB Blocks Bandwidth : 335.9GB/s
16x 64kB Blocks Bandwidth : 294.58GB/s
8x 256kB Blocks Bandwidth : 267.83GB/s
4x 1MB Blocks Bandwidth : 259GB/s
8x 1MB Blocks Bandwidth : 14.37GB/s
8x 4MB Blocks Bandwidth : 13.53GB/s

Benchmark Status
Result ID : AMD Ryzen 7 3700X 8-Core Processor (8C 16T 4.38GHz, 1.8GHz IMC, 8x 512kB L2, 2x 16MB L3)
Microcode : MU8F710013
Computer : ASUS CROSSHAIR VI HERO
Platform Compliance : x64
Buffering Used : No
No. Threads : 16
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 7 3700X 8-Core Processor
Speed : 4.38GHz (100%)
Min/Max/Turbo Speed : 2.2GHz - 3.6GHz - 4.38GHz
Maximum Power : 61.821W - 125.610W
Cores per Processor : 8 Unit(s)
Cores per Compute Unit : 2 Unit(s)
Front Side Bus Speed : 100MHz
Revision/Stepping : 71 / 0
Microcode : MU8F710013
L1D (1st Level) Data Cache : 8x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 8x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 8x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 16MB, 16-Way, Exclusive, 64bytes Line Size, 8 Thread(s)

Memory Controller
Speed : 1.8GHz (100%)
Min/Max/Turbo Speed : 900MHz - 1.8GHz

Performance Enhancing Tips
Warning 242 : Dynamic OverClocking/Turbo engaged. Performance will not be consistent!
Tip 2 : Double-click tip or press Enter while a tip is selected for more information about the tip.




*Sandra multi-core efficiency test with BGS OFF and BGS alt ON. I ran it three times and posted the highest scoring run below*



Spoiler



SiSoftware Sandra

Benchmark Results
Inter-Core Bandwidth : 94.77GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Inter-Core Latency : 47.5ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Inter-Core Bandwidth : 5.92GB/s
No. Threads : 16
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 124.180W
Inter-Core Bandwidth : 781.45MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 3.83ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 298.92kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Inter-Core Bandwidth : 22.44MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 0.11ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 
U0-U2 Data Latency : 28.2ns
U0-U4 Data Latency : 28.2ns
U0-U6 Data Latency : 28.0ns
U0-U8 Data Latency : 67.7ns
U0-U10 Data Latency : 67.0ns
U0-U12 Data Latency : 68.5ns
U0-U14 Data Latency : 68.3ns
U0-U1 Data Latency : 11.4ns
U0-U3 Data Latency : 28.0ns
U0-U5 Data Latency : 28.3ns
U0-U7 Data Latency : 28.1ns
U0-U9 Data Latency : 69.3ns
U0-U11 Data Latency : 70.4ns
U0-U13 Data Latency : 69.8ns
U0-U15 Data Latency : 67.4ns
U2-U4 Data Latency : 27.5ns
U2-U6 Data Latency : 27.6ns
U2-U8 Data Latency : 66.4ns
U2-U10 Data Latency : 68.5ns
U2-U12 Data Latency : 67.9ns
U2-U14 Data Latency : 63.2ns
U2-U1 Data Latency : 27.5ns
U2-U3 Data Latency : 10.6ns
U2-U5 Data Latency : 27.4ns
U2-U7 Data Latency : 27.6ns
U2-U9 Data Latency : 65.3ns
U2-U11 Data Latency : 68.2ns
U2-U13 Data Latency : 67.9ns
U2-U15 Data Latency : 65.6ns
U4-U6 Data Latency : 27.3ns
U4-U8 Data Latency : 66.0ns
U4-U10 Data Latency : 67.7ns
U4-U12 Data Latency : 67.4ns
U4-U14 Data Latency : 63.4ns
U4-U1 Data Latency : 27.6ns
U4-U3 Data Latency : 27.4ns
U4-U5 Data Latency : 11.1ns
U4-U7 Data Latency : 27.3ns
U4-U9 Data Latency : 62.5ns
U4-U11 Data Latency : 68.3ns
U4-U13 Data Latency : 67.3ns
U4-U15 Data Latency : 65.7ns
U6-U8 Data Latency : 59.9ns
U6-U10 Data Latency : 69.2ns
U6-U12 Data Latency : 68.7ns
U6-U14 Data Latency : 64.9ns
U6-U1 Data Latency : 27.4ns
U6-U3 Data Latency : 27.6ns
U6-U5 Data Latency : 27.4ns
U6-U7 Data Latency : 11.0ns
U6-U9 Data Latency : 67.8ns
U6-U11 Data Latency : 68.7ns
U6-U13 Data Latency : 67.2ns
U6-U15 Data Latency : 66.2ns
U8-U10 Data Latency : 27.7ns
U8-U12 Data Latency : 27.7ns
U8-U14 Data Latency : 27.2ns
U8-U1 Data Latency : 67.0ns
U8-U3 Data Latency : 67.2ns
U8-U5 Data Latency : 64.7ns
U8-U7 Data Latency : 66.0ns
U8-U9 Data Latency : 10.7ns
U8-U11 Data Latency : 27.7ns
U8-U13 Data Latency : 27.7ns
U8-U15 Data Latency : 27.4ns
U10-U12 Data Latency : 27.6ns
U10-U14 Data Latency : 28.0ns
U10-U1 Data Latency : 68.7ns
U10-U3 Data Latency : 68.5ns
U10-U5 Data Latency : 68.3ns
U10-U7 Data Latency : 68.0ns
U10-U9 Data Latency : 27.9ns
U10-U11 Data Latency : 11.3ns
U10-U13 Data Latency : 27.6ns
U10-U15 Data Latency : 27.7ns
U12-U14 Data Latency : 27.8ns
U12-U1 Data Latency : 64.6ns
U12-U3 Data Latency : 68.7ns
U12-U5 Data Latency : 68.4ns
U12-U7 Data Latency : 68.3ns
U12-U9 Data Latency : 27.6ns
U12-U11 Data Latency : 27.7ns
U12-U13 Data Latency : 11.1ns
U12-U15 Data Latency : 27.7ns
U14-U1 Data Latency : 67.7ns
U14-U3 Data Latency : 68.2ns
U14-U5 Data Latency : 65.6ns
U14-U7 Data Latency : 67.1ns
U14-U9 Data Latency : 27.4ns
U14-U11 Data Latency : 27.7ns
U14-U13 Data Latency : 27.8ns
U14-U15 Data Latency : 10.8ns
U1-U3 Data Latency : 27.0ns
U1-U5 Data Latency : 27.7ns
U1-U7 Data Latency : 27.6ns
U1-U9 Data Latency : 68.3ns
U1-U11 Data Latency : 67.6ns
U1-U13 Data Latency : 68.0ns
U1-U15 Data Latency : 66.4ns
U3-U5 Data Latency : 27.5ns
U3-U7 Data Latency : 27.7ns
U3-U9 Data Latency : 67.9ns
U3-U11 Data Latency : 68.1ns
U3-U13 Data Latency : 68.0ns
U3-U15 Data Latency : 67.0ns
U5-U7 Data Latency : 27.3ns
U5-U9 Data Latency : 60.5ns
U5-U11 Data Latency : 68.1ns
U5-U13 Data Latency : 67.3ns
U5-U15 Data Latency : 64.7ns
U7-U9 Data Latency : 60.9ns
U7-U11 Data Latency : 69.5ns
U7-U13 Data Latency : 69.2ns
U7-U15 Data Latency : 69.9ns
U9-U11 Data Latency : 27.3ns
U9-U13 Data Latency : 27.8ns
U9-U15 Data Latency : 27.5ns
U11-U13 Data Latency : 27.6ns
U11-U15 Data Latency : 27.8ns
U13-U15 Data Latency : 28.0ns
1x 64bytes Blocks Bandwidth : 11.65GB/s
4x 64bytes Blocks Bandwidth : 20.12GB/s
4x 256bytes Blocks Bandwidth : 72.41GB/s
4x 1kB Blocks Bandwidth : 215GB/s
4x 4kB Blocks Bandwidth : 331.57GB/s
16x 4kB Blocks Bandwidth : 297GB/s
4x 64kB Blocks Bandwidth : 336.8GB/s
16x 64kB Blocks Bandwidth : 294GB/s
8x 256kB Blocks Bandwidth : 268GB/s
4x 1MB Blocks Bandwidth : 262.56GB/s
8x 1MB Blocks Bandwidth : 15.07GB/s
8x 4MB Blocks Bandwidth : 13.9GB/s

Benchmark Status
Result ID : AMD Ryzen 7 3700X 8-Core Processor (8C 16T 4.33GHz, 1.8GHz IMC, 8x 512kB L2, 2x 16MB L3)
Microcode : MU8F710013
Computer : ASUS CROSSHAIR VI HERO
Platform Compliance : x64
Buffering Used : No
No. Threads : 16
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 7 3700X 8-Core Processor
Speed : 4.33GHz (99%)
Min/Max/Turbo Speed : 2.2GHz - 3.6GHz - 4.35GHz
Maximum Power : 61.821W - 124.179W
Cores per Processor : 8 Unit(s)
Cores per Compute Unit : 2 Unit(s)
Front Side Bus Speed : 100MHz
Revision/Stepping : 71 / 0
Microcode : MU8F710013
L1D (1st Level) Data Cache : 8x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 8x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 8x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 16MB, 16-Way, Exclusive, 64bytes Line Size, 8 Thread(s)

Memory Controller
Speed : 1.8GHz (100%)
Min/Max/Turbo Speed : 900MHz - 1.8GHz

Performance Enhancing Tips
Warning 242 : Dynamic OverClocking/Turbo engaged. Performance will not be consistent!
Tip 2 : Double-click tip or press Enter while a tip is selected for more information about the tip.




Timings used so you don't need to go check what the 3600 safe preset timings are. Power down mode was disabled.


----------



## Veii

rares495 said:


> After setting tRCDWR to 11 I got a nice increase to 94793. The tool seems to focus on the main timings. Could you check your own score? (get the tool from Crosshair VIII thread in the utilities section)


I wish i could but my ryzen is dead since some time, i'm on an old i7-3612QM frankenstein notebook 

Else would've worken on timings myself the whole time


yrelbirb said:


> hey; 46 tRC needs cmos reset ; same for 48 50 or 52 for that matter
> 52 boots but errors alot quickly in 1usmus memtest
> how do i make it 20 rounds btw?
> ;;
> same for tRCD (when others are normal values), needs cmoes reset for 18
> maybe usmus right, maybe my mobo is faking tras? maybe its not 32 at all when set to that number, who knows


Just to doublecheck, when you changed tRCD - you always kept an eye on tRDWR & WRRD ?
If yes, then it's purely voltage related and you can't run it ~ if you have post issues
Error issues are most of the times just missmatching timings or missmatching voltages (cpu,imc)
tRAS 28 has no issues to run, as this is normal for CL14 , tRAS 24 should have no issues to run
But under 20 it's questionable - although you will see the result difference immediately, if anything is autocorrecting
Boards do autocorrect anyways, because timings are very odd 8 digit decimal values 
Ryzen 3rd gen does autocorrect tho to keep up stability, 2nd gen only the board


Spoiler






> [Main Section]
> Config Name=Default
> Config Author=1usmus_v3
> Cores=0
> Tests=16
> Time (%)=100
> Cycles=20
> Language=0
> Test Sequence=6,12,2,10,5,1,4,3,0,13,9,14,7,8,1,11,15


Cycles change from 3 to 20
inside TM5/Bin/MT.cfg





rastaviper said:


> You are mentioning to use Sandra for measuring and perfOrmance gains but I don't see anyone posting results from there!
> 
> So which test exactly should we use for memory optimising when we try different RAM timings?


Because people barely listen 
I've mentioned it too often ^^'
Multi-Core efficiency testing (detailed result) ~ that's been a thing since gen 1
Results scale a bit with cpu clock too, on a fixed clock it's easier to work with, or on a 3600 which always hits max boost
But as long as you don't change voltages, the results should be accurate
You can focus on 4 aspects of the result
- first filter to local mode and disable 5 results at once, maybe even change current running color if you wish
- Focus on inter-core bandwidth and latency
- the report is always huge, your focus can also be "Performance per Threads"
- also inside that long report you see furthest core to furthest core latency testing, this is important for actual game perf / your goal is near 68ns as max, down to 65-66ns as max



Tobiman said:


> After a few weeks on safe preset, i've bumped up the timings to 1usmus fast preset and the result is a bit better. Old aida64 score is below new score.


Can you show the older timings
Performance might look better (unsure if latency between cores & CCX is really better ~ written in the report down bellow)
But you seem to either be throttled or some timing is mismatching
That huge spike at the start is missing - mostly was noticed as infinity fabric throttling
Did you change any CAD_BUS values or RTT values in the meantime too ?
After all something made you slower, while the remain set of timings are better

EDIT:
I noticed the green result was stock - auto predicted values
But i've seen this behavior on the old X370 Taichi bioses compared to the new ones
You might be able to fix that, but it's artificial throttle 
see here:
https://www.overclock.net/forum/11-...chi-overclocking-thread-736.html#post28381784
That topic goes on for 4-5 pages
Let's see if we can fix that a bit, but you might be artificially throttled at this point


Dollar said:


> The small drop in performance can be seen in aida and DRAM calc benchmark. This post is going to be a mess....
> Timings used so you don't need to go check what the 3600 safe preset timings are. Power down mode was disabled.


BGS Alt did indeed perform far better - it's noticable
U4-U14 latency was better by a big chunk, same as performance per thread = ipc - was better 
i wonder why, on 4 dimms :thinking:
What PCB layout did you use ?
Are these Samsung or Micron B-dies ?


----------



## Dollar

Veii said:


> BGS Alt did indeed perform far better - it's noticable
> U4-U14 latency was better by a big chunk, same as performance per thread = ipc - was better
> i wonder why, on 4 dimms :thinking:
> What PCB layout did you use ?
> Are these Samsung or Micron B-dies ?


Four sticks of these


----------



## rastaviper

Veii said:


> Because people barely listen
> I've mentioned it too often ^^'
> Multi-Core efficiency testing (detailed result) ~ that's been a thing since gen 1
> Results scale a bit with cpu clock too, on a fixed clock it's easier to work with, or on a 3600 which always hits max boost
> But as long as you don't change voltages, the results should be accurate
> You can focus on 4 aspects of the result
> - first filter to local mode and disable 5 results at once, maybe even change current running color if you wish
> - Focus on inter-core bandwidth and latency
> - the report is always huge, your focus can also be "Performance per Threads"
> - also inside that long report you see furthest core to furthest core latency testing, this is important for actual game perf / your goal is near 68ns as max, down to 65-66ns as max


Well something doesn't work well with SANDRA either.
With previous testing at Multi-Core efficiency and 4.4Ghz, my best score was *85.15GB/s and 46.5ns*
https://ranker.sisoftware.co.uk/sho...d2e3d6e2dbefd8fe8cb181a7c2a79aaa8cffc2f2&l=en

Now with further Ram tuning my Inter-Core Bandwidth for the same clocks (4.4ghz) is worse at 81.121Gb/s and my latency dropped at 46ns.
It seems that the Ram tuning works, but why my bandwidth to be worse?


----------



## rares495

It seems that the bandwidth test is useless.


----------



## Veii

rastaviper said:


> Well something doesn't work well with SANDRA either.
> With previous testing at Multi-Core efficiency and 4.4Ghz, my best score was *85.15GB/s and 46.5ns*
> https://ranker.sisoftware.co.uk/sho...d2e3d6e2dbefd8fe8cb181a7c2a79aaa8cffc2f2&l=en
> 
> Now with further Ram tuning my Inter-Core Bandwidth for the same clocks (4.4ghz) is worse at 81.121Gb/s and my latency dropped at 46ns.
> It seems that the Ram tuning works, but why my bandwidth to be worse?


Lower timings are not always better 
please show the detailed result , the graph 
The same test exists on the DRAM calculator as "memory curve"
Bandwidth is influenced by the cpu clock a bit - but 4gb/s difference can be solely just cpu OC instability


----------



## rastaviper

Veii said:


> Lower timings are not always better
> 
> please show the detailed result , the graph
> 
> The same test exists on the DRAM calculator as "memory curve"
> 
> Bandwidth is influenced by the cpu clock a bit - but 4gb/s difference can be solely just cpu OC instability


But lowering the latency score means that the RAM performance is better right?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Veii

rastaviper said:


> But lowering the latency score means that the RAM performance is better right?


Not always


----------



## Tobiman

Veii said:


> Can you show the older timings
> Performance might look better (unsure if latency between cores & CCX is really better ~ written in the report down bellow)
> But you seem to either be throttled or some timing is mismatching
> That huge spike at the start is missing - mostly was noticed as infinity fabric throttling
> Did you change any CAD_BUS values or RTT values in the meantime too ?
> After all something made you slower, while the remain set of timings are better
> 
> EDIT:
> I noticed the green result was stock - auto predicted values
> But i've seen this behavior on the old X370 Taichi bioses compared to the new ones
> You might be able to fix that, but it's artificial throttle
> see here:
> https://www.overclock.net/forum/11-...chi-overclocking-thread-736.html#post28381784
> That topic goes on for 4-5 pages
> Let's see if we can fix that a bit, but you might be artificially throttled at this point


The CAD_BUS and RTT values for SAFE and FAST preset are the exact same so I didn't change anything there. The safe and fast presets are linked below respectively. I made a modification to the voltage of the fast preset since the default values presented by the program didn't add up. I set dram voltage to 1.45.


----------



## nick name

Is anyone running a G.Skill RipJaws V 3600C16 kit? The Hynix DJR chips?


----------



## hazium233

yrelbirb said:


> same here; doesnt even boot without gdm actually





KevyMatts said:


> When i have GDM disabled I seem to be unstable with errors.
> 
> But when it's enabled it doesn't have errors.


Ability to run GDM depends partly on the IMC and partly on the dimms. Unless you are trying to run all odd timings at 1T, then you may as well leave it on. Most samples will clock higher with it anyway.



yrelbirb said:


> hey; 46 tRC needs cmos reset ; same for 48 50 or 52 for that matter
> 
> 52 boots but errors alot quickly in 1usmus memtest
> 
> how do i make it 20 rounds btw?
> 
> ;;
> 
> same for tRCD (when others are normal values), needs cmoes reset for 18
> 
> maybe usmus right, maybe my mobo is faking tras? maybe its not 32 at all when set to that number, who knows


Was this Micron 8Gb Rev B?

I don't think you are going to be able to get tRC much less than 56t at 3200MT/s, similarly I would guess tRCDRD of ~19t at this clock would be good based on expectations. tRFC ~300ns give or take.

Voltage is a bit of a YMMV thing (and at higher ones you might need to play with VTTDDR and VREF), but hitting a wall by 1.42V or so would be in line with some others' results on this IC.


----------



## yrelbirb

yes it is 

300ns would be good. i never tinkered with tRFC actually (bcoz i heard somewhere that it can corrupt system in a sneakily way) , i think a realy realy long test needed to count on tRFC overclock, no?


----------



## 2600ryzen

My micron A die can handle 300ns easily compared to stock 350ns, 9 x Trc for me.


----------



## yrelbirb

yes i began some testings at 3200 mhz

300 ns didnt work sadly

trying 504 trfc now

equals to 315 ns if i calculated correctly??

it looks ok for now. will test for memtest %1000 at least

oh and tRC at 56

so tRc is cleaN divider of my trfc (trc*9 504)

also a clean divider for trtp (8)

looks fine for now. will also see if any improvements were happened on games

--

do SCL needs adjustsments with other timings correalted? they are always 2-2 for me... and stable for some reason (stock 2133 training puts SCL's into 2-2 as well)


----------



## dug96

Hello everyone, I'm looking for a bit of advice on tightening my timings on my kit. Here are my system specs as background: Ryzen 3600 , Asus X470-f ( t-topology), 3733 CL17 Corsair B-die (single rank).

So far I've been utilizing the DRAM calc and have arrived on these timings so far @ 1.39v DRAM, 1.075v SOC, proOCDT 28 ohms, 30-20-20-24 . I am pretty sure the math on some of my timings does not add up correctly and I am wondering if that is preventing me from moving to CL14 or 15 as either one will result in no boot, needing a CMOS clear (with DRAM @ 1.47). Would it be incorrect timings or am I hitting the limits of T-topology layout?


----------



## Veii

dug96 said:


> Hello everyone, I'm looking for a bit of advice on tightening my timings on my kit. Here are my system specs as background: Ryzen 3600 , Asus X470-f ( t-topology), 3733 CL17 Corsair B-die (single rank).
> 
> So far I've been utilizing the DRAM calc and have arrived on these timings so far @ 1.39v DRAM, 1.075v SOC, proOCDT 28 ohms, 30-20-20-24 . I am pretty sure the math on some of my timings does not add up correctly and I am wondering if that is preventing me from moving to CL14 or 15 as either one will result in no boot, needing a CMOS clear (with DRAM @ 1.47). Would it be incorrect timings or am I hitting the limits of T-topology layout?


Seen this issue today for the 3rd time already
minimum tRAS for you is not 28 - it's far to low
30 or 32 is your value
tRC doesn't have to be a clean perfect math, but tRAS has to be, else it waits the whole time for commands to pass

Put tRAS to 30 and at best & increase tWR to 14
only memory voltage is preventing you to boot CL15 , but you can try later adding tWRRD 3 if it changes stability
But it will lower timing efficiency 
Else next step is lowering SCL to 3

EDIT:
Will this post under 1.48vDIMM


----------



## dug96

Veii said:


> Seen this issue today for the 3rd time already
> minimum tRAS for you is not 28 - it's far to low
> 30 or 32 is your value
> tRC doesn't have to be a clean perfect math, but tRAS has to be, else it waits the whole time for commands to pass
> 
> Put tRAS to 30 and at best & increase tWR to 14
> only memory voltage is preventing you to boot CL15 , but you can try later adding tWRRD 3 if it changes stability
> But it will lower timing efficiency
> Else next step is lowering SCL to 3
> 
> EDIT:
> Will this post under 1.48vDIMM


Ah I remember you mentioning the same thing a few pages back about tRAS, I apologize for the frustration. I forgot to change that back after my initial attempts for 14-14-14-28. I am going to try your suggestions out and report back shortly.


----------



## Veii

dug96 said:


> Ah I remember you mentioning the same thing a few pages back about tRAS, I apologize for the frustration. I forgot to change that back after my initial attempts for 14-14-14-28. I am going to try your suggestions out and report back shortly.


It wasn't you 
It makes me wonder who teaches that
low tRAS only results in a wait-for-command-completion-before-action scenario 
It does nothing than just slow down things and at worst error out memory tests for mysterious reasons 
Appearing that often, makes me think it's some guide somewhere 
tRAS can only be lower than tCL+tRTC if you abuse memory heterogeneity ~ which i doubt many read 
And that tCL+tWR+tBL method for it, would nearly always cause trouble if the rest is not as tight as possible


----------



## dug96

Every guide I've read so far always suggests the same rule for tRAS or +2, so I would guess it mostly just user error. I have now put your suggested timings in but it required 1.45v to boot into windows. Is that normal to need such a boost in tRFC while still staying on CL16? I am still having trouble getting to even CL15


----------



## Veii

dug96 said:


> Every guide I've read so far always suggests the same rule for tRAS or +2, so I would guess it mostly just user error. I have now put your suggested timings in but it required 1.45v to boot into windows. Is that normal to need such a boost in tRFC while still staying on CL16? I am still having trouble getting to even CL15


You are at 3800MT/s 
CL15 is no joke on this speed 
Some need 1.56v on 3600MT/s to hit CL14
1.5v on very good kits can run 3800CL14 
not unexpected to need 1.48v for very low tRFC and low timings 
1.46v is about the sweetspot for bad and good b-dies, 1.48v only for good binns of b-dies
the bad ones don't like over 1.46v

tRFC is lower than usual because tRC is already -2
-4 is about the max i've seen, but i didn't see a testing rabbit to explore what it negatively affects by going that low in tRC
surely messes up something 
-2 on dual rank is hard, but on single rank kits it's easy to do and let's you use very low tRFC
but tRAS has to stay as a clean transition or on slow ICs with (like you mentioned) added artificial delay
Although, just increasing tRP instead tRAS does work too - at the end both will influence tRC
* depends really if recharge after write was too slow or just globally everything was too harsh soo tRP bump would help


----------



## dug96

Thanks for the advice Veii, I think I was looking for someone smarter than me to tell me to give up for that last bit of latency. I figured T-topology is a disadvantage to begin with..

Are there any other changes I should try out at this point?


----------



## Veii

dug96 said:


> Thanks for the advice Veii, I think I was looking for someone smarter than me to tell me to give up for that last bit of latency. I figured T-topology is a disadvantage to begin with..
> 
> Are there any other changes I should try out at this point?


You go step by step 
Doing too many changes, puts you in a rabbit hole situation
Where you just don't know where you've messed up
Increasing frequency , increasing resistance, changing procODT 
all can lead to a startover with timings creation 

Soo you lower stuff step by step and see where it fails 
after all every kit is unique - only the "baseline" is calculable 
Tightening it more is from kit to kit unique , and even from the same model number unique 

SLC you have to drop to at least 3, tRDWR might be workable with 
and then maybe something 16-14-14-16 can run in the future with lower tRAS and tRC
You need to go methodological on it

First is lowering SLC and testing how low you can get tRFC before the kits start to choke by too high latency from the main 3 timings (tCL,tRCD,tRP)
Later you lower tRCD and at the same time always finetune tRDWR & tWRRD 
Then you check how low tRP can go with your voltage and at best and last try if you can lower tCL
tCL goes at last


----------



## rares495

Veii said:


> You are at 3800MT/s
> CL15 is no joke on this speed
> Some need 1.56v on 3600MT/s to hit CL14
> 1.5v on very good kits can run 3800CL14
> not unexpected to need 1.48v for very low tRFC and low timings
> 1.46v is about the sweetspot for bad and good b-dies, 1.48v only for good binns of b-dies
> the bad ones don't like over 1.46v


How about 1.52V?


----------



## Veii

rares495 said:


> How about 1.52V?


Can't say at what point Samsung B-dies require maxmem , but it should be near that value 
afterwards it needs to drop to 2gb per IC - in order to use voltages like 1.6 or 1.72v 
an architectural flaw on b-dies

Don't entirely know 20nm degradation point, except 1.5v is known as the widespread JEDEC max spec for 24/7 operation on this nm nodesize
haven't had a dead memory kit so far to say what's absolute max 
But it's known that near 1.56-1.58v it will require maxmem 4096mb in order to even post to windows


----------



## rares495

Veii said:


> Can't say at what point Samsung B-dies require maxmem , but it should be near that value
> afterwards it needs to drop to 2gb per IC - in order to use voltages like 1.6 or 1.72v
> an architectural flaw on b-dies
> 
> Don't entirely know 20nm degradation point, except 1.5v is known as the widespread JEDEC max spec for 24/7 operation on this nm nodesize
> haven't had a dead memory kit so far to say what's absolute max
> But it's known that near 1.56-1.58v it will require maxmem 4096mb in order to even post to windows


Will increased temperature speed up the degradation?


----------



## Veii

rares495 said:


> Will increased temperature speed up the degradation?


It's not behaving like silicon, normally no 
They either have a state of 0 or 1 - where it's stored first as garbage
only the sense amplifier which works by voltage and delay, can encode if it's stored as 0 or 1
Too high voltage only causes instability until full death

I spoke about degradation, it's a bit different than silicon degradation
Might have been not very clear
Capacitors can die by too much heat and too much voltage
I haven't seen a dead DDR1 dimm that died by time - but usually time is the indicator of a dead capacitor or IC

No sorry, i don't know exactly what causes them to die
But maximum voltage changes up to nm size
and stability changes for example under LN2 electrodes behave differently and voltage behaves differently 
I don't think it's comparable to normal usage voltage limits 

Where rocking 1.62v on HynixMFR without issues before , while it dropped to 1.55 later for stability 
They are to this date in perfect condition but where 25nm
Although Hynix doesn't have a maxmem flaw like b-dies do
Can't exactly answer this question i'm sorry
Didn't have dead memory to track the exact cause , so far the safe limits where holding up 
Edit: please ask Buildzoid how b-dies can die, he loves to use 1.7-1,72v for them


----------



## rares495

Veii said:


> It's not behaving like silicon, normally no
> They either have a state of 0 or 1 - where it's stored first as garbage
> only the sense amplifier which works by voltage and delay, can encode if it's stored as 0 or 1
> Too high voltage only causes instability until full death
> 
> I spoke about degradation, it's a bit different than silicon degradation
> Might have been not very clear
> Capacitors can die by too much heat and too much voltage
> I haven't seen a dead DDR1 dimm that died by time - but usually time is the indicator of a dead capacitor or IC
> 
> No sorry, i don't know exactly what causes them to die
> But maximum voltage changes up to nm size
> and stability changes for example under LN2 electrodes behave differently and voltage behaves differently
> I don't think it's comparable to normal usage voltage limits
> 
> Where rocking 1.62v on HynixMFR without issues before , while it dropped to 1.55 later for stability
> They are to this date in perfect condition but where 25nm
> Although Hynix doesn't have a maxmem flaw like b-dies do
> Can't exactly answer this question i'm sorry
> Didn't have dead memory to track the exact cause , so far the safe limits where holding up
> Edit: please ask Buildzoid how b-dies can die, he loves to use 1.7-1,72v for them


Ok. Thanks.

I have a question about tRAS and tRC. I think my kit can do 23 tRAS and ~30-32 tRC. Is there any point in lowering these if I cannot lower tRFC as well? 1usmus said there's not much point to low tRFC but I wonder about sync if I don't lower it as well.


----------



## Veii

rares495 said:


> Ok. Thanks.
> 
> I have a question about tRAS and tRC. I think my kit can do 23 tRAS and ~30-32 tRC. Is there any point in lowering these if I cannot lower tRFC as well? 1usmus said there's not much point to low tRFC but I wonder about sync if I don't lower it as well.


1usmus was correct, that boards and now 3rd gen especially does autocorrect
i know buildzoid uses CL12-11 timings which equal to 24 tRAS and 35 tRC
They work for him, but 3rd gen does autocorrect on bad timings that's true

Unless you know some rules, you can't know 
It sounds stupid, but unless you know that something is wrong, you might never get to know as the cpu does autocorrect 
As long as you see any difference in latency on any kind of benchmark, it does work 
Or bandwidth increase 
Because lower timings, higher timing efficiency = better bandwidth
I'm no help here, because i can't work on memory right now - only can teach what i learned by myself some time ago

As long as there is even a subtle difference, it's worth it
But keep the rules up, i mean you'll notice instability early or later anyways 
And as long as timings can post memory training , they can work 
Wrong timings won't even get to post ~ bad ones might be unstable but that means you are close


----------



## LicSqualo

My actual settings from two years. No problems so far. I've copied the timings from another users and tried without errors until now. 
Can i do better? 

With the last windows update (18363) I can't use Winring0.dll so no RTC, no ZenTimings or 1usmus dram calculator show my actual timings... Anyone have a solution?


----------



## rares495

LicSqualo said:


> My actual settings from two years. No problems so far. I've copied the timings from another users and tried without errors until now.
> Can i do better?
> 
> With the last windows update (18363) I can't use Winring0.dll so no RTC, no ZenTimings or 1usmus dram calculator show my actual timings... Anyone have a solution?


Ryzen Master or Asus Mem TweakIt.


----------



## LicSqualo

rares495 said:


> Ryzen Master or Asus Mem TweakIt.


Ryzen master show only few timings on my Ryzen 1700 and Asus mem tweakIt was not made for Ryzen or AMD products.
Thank you, but this not solve, CAD timings are not showed.


----------



## yrelbirb

trfc crashed at 504 in heroes of storm despite passing 1usmus test so i backed it up;

in the meantime i played with trcdwr and trdwr abit and got down to 68.2 ns

ac odyssey fps went to 121 from 119

just wanted to say; for wsome reason heroes of storm is a good game to test ram stability. this game instantly detects memory errors and hard crashes 

@Veii what u tihnk about those timings, especialyl the tRCDWR at 12 and tRDWR at 6. they seem to help in terms of latency? also; once in a time you wanted me to put 1-5-5-7-7-1 timings to 1-1-1-1--11 what was that about ; would it still apply for those timings?


----------



## nick name

LicSqualo said:


> Ryzen master show only few timings on my Ryzen 1700 and Asus mem tweakIt was not made for Ryzen or AMD products.
> Thank you, but this not solve, CAD timings are not showed.


Does Ryzen Timing Checker work with your board?


----------



## rares495

Veii said:


> 1usmus was correct, that boards and now 3rd gen especially does autocorrect
> i know buildzoid uses CL12-11 timings which equal to 24 tRAS and 35 tRC
> They work for him, but 3rd gen does autocorrect on bad timings that's true
> 
> Unless you know some rules, you can't know
> It sounds stupid, but unless you know that something is wrong, you might never get to know as the cpu does autocorrect
> As long as you see any difference in latency on any kind of benchmark, it does work
> Or bandwidth increase
> Because lower timings, higher timing efficiency = better bandwidth
> I'm no help here, because i can't work on memory right now - only can teach what i learned by myself some time ago
> 
> As long as there is even a subtle difference, it's worth it
> But keep the rules up, i mean you'll notice instability early or later anyways
> And as long as timings can post memory training , they can work
> Wrong timings won't even get to post ~ bad ones might be unstable but that means you are close


Nothing was stable, unfortunately. It seems that going lower is a huge waste of time.


----------



## Veii

yrelbirb said:


> trfc crashed at 504 in heroes of storm despite passing 1usmus test so i backed it up;
> in the meantime i played with trcdwr and trdwr abit and got down to 68.2 ns
> ac odyssey fps went to 121 from 119
> @Veii what u tihnk about those timings, especialyl the tRCDWR at 12 and tRDWR at 6. they seem to help in terms of latency? also; once in a time you wanted me to put 1-5-5-7-7-1 timings to 1-1-1-1--11 what was that about ; would it still apply for those timings?


tWR should be 14 here unless you want to lower tRFC
tRDWR has nothing to do with tRCD WR 
It's good to know that it runs, but right now more of a miracle
put tWRRD to 3 and start lowering the wasted latency between tRAS and tRC
1-1-1 1-1-1 was an alternative when you use awkward timings, it does lower performance but is more stable


----------



## LicSqualo

nick name said:


> Does Ryzen Timing Checker work with your board?


RTC has work until february, after the last windows update (1909 or 19H2) not more 
Same for ZenTimings and the Dram Calculator of 1usmus.
I've tried all the possible but nothing. 
The problem (seems to me) is the winring0.dll file, that is not loaded with the last update.


----------



## nick name

LicSqualo said:


> RTC has work until february, after the last windows update (1909 or 19H2) not more
> Same for ZenTimings and the Dram Calculator of 1usmus.
> I've tried all the possible but nothing.
> The problem (seems to me) is the winring0.dll file, that is not loaded with the last update.


What anti-virus are you running? Windows Security kept silently blocking RTC for me and I had to white list it.


----------



## LicSqualo

nick name said:


> What anti-virus are you running? Windows Security kept silently blocking RTC for me and I had to white list it.


Done time ago (and I re-check now), without success.


----------



## nick name

LicSqualo said:


> Done time ago (and I re-check now), without success.


It's something I had to deal with several times. Are you saying it isn't shown in the Windows Security protection history?


----------



## LicSqualo

nick name said:


> It's something I had to deal with several times. Are you saying it isn't shown in the Windows Security protection history?


Yes, isn't listed but I've added both RTC.exe and the folder in the whitelist. Beside I've checked also in the folder protection list and excluded also here.

The error is: "InitialiseOls failed."


----------



## PolRoger

Veii said:


> You go step by step
> 
> First is lowering SLC and testing how low you can get tRFC before the kits start to choke by too high latency from the main 3 timings (tCL,tRCD,tRP)
> Later you lower tRCD and at the same time always finetune tRDWR & tWRRD
> Then you check how low tRP can go with your voltage and at best and last try if you can lower tCL
> tCL goes at last


Hi Veii,

Thanks for giving us all the feedback that do here in this thread. 

I've been trying to improve my memory tweaking and was wondering if you could provide some rules (guidance) for tWR, tRTP, and fine tuning tRDWR and tWRRD?

Here is what I'm currently running now @3733C14 with ~1.44v DRAM:


----------



## nick name

LicSqualo said:


> Yes, isn't listed but I've added both RTC.exe and the folder in the whitelist. Beside I've checked also in the folder protection list and excluded also here.
> 
> The error is: "InitialiseOls failed."


Ahhh, I had that if my memory serves. I wanna say I did something that made it work, but it's been so long I can't remember. 

I posted it about it in the past and can't find it now. I did, though, find some possible fixes:

https://www.overclock.net/forum/13-...ent-fud-about-ryzen-timing-checker-rtc-9.html


----------



## LicSqualo

Thanks for your concern. I appreciate it. That's how I felt:
1) Download the program again
2) verify the antivirus from a possible block of it (double/triple check)
3) Install HardwareMonitor
4) verify that windows does not give error messages in the system and application logs
5) cross-check with programs using the same winring0.dll
Unfortunately, no one has given me a positive result, I just have to install windows again, a solution that I do not like because it does not make me understand where the error is.
The first program with which I realized that something was not working is Dram Calculator by 1usmus. When I press the button to show the times it answers me that it is possible only with the 1st generation of Ryzen (and my 1700 is just the first generation).
So I tried RTC that I hadn't used for a long time (January seems to me) and I had error there too. Then I noticed that lately ryzen 3xxx owners were using Zentimings and I tried this too. Nothing, all programs give me error. On google I did an extensive search to understand if there were solutions to this situation and I found that the same problem happened to those who use Throttlestop, but that the windows updates (memory protection, the incriminated function) have made today impossible to use it unless you change the dll.
I still have to try reinstalling Windows, which I don't do often as I have a lot of programs installed and it would be a deadly bore to do it again.


----------



## 2600ryzen

Is it more important for Twr to sync with Trfc or for Trc to sync with Trfc? Pretty sure it's best if they all sync up but that's really difficult. Right now I'm doing (9 x Trc) + 6 = Trfc so I can get Trfc to also sync with Twr.
In this case Trc = 50 Twr = 12 and Trfc = 456.


----------



## BLUuuE

LicSqualo said:


> Yes, isn't listed but I've added both RTC.exe and the folder in the whitelist. Beside I've checked also in the folder protection list and excluded also here.
> 
> The error is: "InitialiseOls failed."


Install OpenHardwareMonitor

edit: Just realised you've already tried this. NVM.


----------



## nick name

LicSqualo said:


> Thanks for your concern. I appreciate it. That's how I felt:
> 1) Download the program again
> 2) verify the antivirus from a possible block of it (double/triple check)
> 3) Install HardwareMonitor
> 4) verify that windows does not give error messages in the system and application logs
> 5) cross-check with programs using the same winring0.dll
> Unfortunately, no one has given me a positive result, I just have to install windows again, a solution that I do not like because it does not make me understand where the error is.
> The first program with which I realized that something was not working is Dram Calculator by 1usmus. When I press the button to show the times it answers me that it is possible only with the 1st generation of Ryzen (and my 1700 is just the first generation).
> So I tried RTC that I hadn't used for a long time (January seems to me) and I had error there too. Then I noticed that lately ryzen 3xxx owners were using Zentimings and I tried this too. Nothing, all programs give me error. On google I did an extensive search to understand if there were solutions to this situation and I found that the same problem happened to those who use Throttlestop, but that the windows updates (memory protection, the incriminated function) have made today impossible to use it unless you change the dll.
> I still have to try reinstalling Windows, which I don't do often as I have a lot of programs installed and it would be a deadly bore to do it again.



When you try to install it do you have any monitoring programs open like HWiNFO?


----------



## LicSqualo

nick name said:


> When you try to install it do you have any monitoring programs open like HWiNFO?


Yes, I've SIV (http://rh-software.com/) always (from win7) running (also before this problem) to monitor my system and control all my fans connected (via Corsair hardware). Please can you specify what program "When you try to install it"?


----------



## rares495

2600ryzen said:


> Is it more important for Twr to sync with Trfc or for Trc to sync with Trfc? Pretty sure it's best if they all sync up but that's really difficult. Right now I'm doing (9 x Trc) + 6 = Trfc so I can get Trfc to also sync with Twr.
> In this case Trc = 50 Twr = 12 and Trfc = 456.


Can you post your current timings? Also, what kind of memory is it? Thaiphoon Burner screenshot pls.


----------



## Veii

PolRoger said:


> Hi Veii,
> Thanks for giving us all the feedback that do here in this thread.
> 
> I've been trying to improve my memory tweaking and was wondering if you could provide some rules (guidance) for tWR, tRTP, and fine tuning tRDWR and tWRRD?
> 
> Here is what I'm currently running now @3733C14 with ~1.44v DRAM:


tWR is optimally near the 8ns which is 8*MT/s divided by 2000 
(8*3734)/2000= 14.936ns, 15 would be the optimal - BUT
according to 1usmus's research is lower tWR still beneficial
I'm doubting that formular a bit as write recovery depends on more than just running frequeuncy
It depends on tCL and tRTP , but i have no perfect formular for it - 1usmus knows more

Lowest tWR=
tRRDS+tWTRS
Highest tWR=
tCL + tRTP
Alternative Option:
tRAS-tRCD (Biggest)

Recommended is value between lowest tWR
And Alt. - one in between, should be mostly lowest tWR +2, or Alt tWR -2
tWR has to be an even value, but as there is more to it than 8ns of x Frequency, use the math formular above only to orient yourself where you want to be
For 3200MT/s for example 8*3200/2000=12.8 and tWR 12 runs wonderfully there

Divided by 2000 is for turning virtual values into nanosecounds 
tCL 16 = 8.57ns
((8,57*3734)/2000)= 16,00019 
To be more accurate, tCL 16 = 8.56989823245849ns
Soo you can see why boards do autocorrect 
Starting with 3734MT/s being more like 3733,333336 - which is a fundamental error in getting perfect timings
The DDR frequency is already rounded down which causes math errors, and tRFC accuracy does suffer from that

tRDWR & tWRRD has no perfect rule, only one that is trial and error
https://www.overclock.net/forum/10-...memory-stability-thread-328.html#post28385690
It's flawed and depends on dual or single ranked, but it's functional and usable
We noticed tCWL = tCL , for this ruleset
If it's lower, it will prevent low tRDWR to post 

EDIT:
You run SerJ's config on TM5
Results on that one don't matter
What you want is the 1usmus_v3 config 20 rounds, which is 1:30h for 16GB or 3h for 32GB
I've attached my TM on it, if you don't want to search, but yes - you load the wrong config for the test


2600ryzen said:


> Is it more important for Twr to sync with Trfc or for Trc to sync with Trfc? Pretty sure it's best if they all sync up but that's really difficult. Right now I'm doing (9 x Trc) + 6 = Trfc so I can get Trfc to also sync with Twr.
> In this case Trc = 50 Twr = 12 and Trfc = 456.


tWR should be in sync with tRFC if possible , if not possible at least tRTP has to be 
Preferable to keep tWR in sync and see if how tRTP behaves, if 6 is possible else just half of current tWR

I am pretty sure with tSTAG inside the tRFC calculation , it will show what of both has to be a perfect half
But i have the suspension, it doesn't matter here that much
Because in order for it to matter a lot, timings have to be turned into ns and the math being done
there is too much variability on whole virtual values to predict perfect results 
At worst the board does autocorrect anyways, but try to keep it a divider if you can 
It's no "has to be" rule - it's a strong recommendation for tWR to be a divider of tRFC

The less wasted latency you have across the remain timings, the less it would matter if it's a tiny tiny bit offsync ~ as it's corrected anyways


----------



## nick name

LicSqualo said:


> Yes, I've SIV (http://rh-software.com/) always (from win7) running (also before this problem) to monitor my system and control all my fans connected (via Corsair hardware). Please can you specify what program "When you try to install it"?


Have you tried closing all monitoring software before installing?


----------



## 2600ryzen

Yes I'm finding having Trtp and Twr a perfect multiple of Trfc makes my Dram Calculator benchmark perform more consistently, and also feels better in general desktop use probably from the reduced wasted latency. Also using Twr = 2 x Trtp to get the perfect multiple with Trfc.


----------



## Veii

2600ryzen said:


> Yes I'm finding having Trtp and Twr a perfect multiple of Trfc makes my Dram Calculator benchmark perform more consistently, and also feels better in general desktop use probably from the reduced wasted latency. Also using Twr = 2 x Trtp to get the perfect multiple with Trfc.


Feel is always such an irregular thing
SiSandra is a valid benchmark to notice timing differences ^^'


----------



## rares495

Veii said:


> Feel is always such an irregular thing
> SiSandra is a valid benchmark to notice timing differences ^^'


I keep trying for some reason. I should already be pretty happy with my timings but I can't stop. 

You said that TM5 can tell us what is wrong. Is that really true? What can you tell from this image?


----------



## Veii

rares495 said:


> I keep trying for some reason. I should already be pretty happy with my timings but I can't stop.
> 
> You said that TM5 can tell us what is wrong. Is that really true? What can you tell from this image?


it's been a bit of time, got rusty 
But yes you can 
Error test 10 is under a simple test size 8mb, it's a burst test / mostly voltage related, more delay related on cell precharge 
Test 11 error is a normal delay for 16mb block size, this is rather timings related

I can imagine it's copy, error, read error, copy error - what happened here
tRP is either to low, tWR too low or you lowered vDIMM voltage
anyhow, somewhere you choke on a burst write and read test  
But it's not a chargeback error, else test 9 would error with a blocksize of 4mb 
(that is rather a SOC voltage or too low vDIMM error)

Error 6 and 12 belong to the memory controller 
which come together, first error 6 size 1mb that is initialization error , either 4-5 times error 6=BSOD or 6,12
Error on test 12 is blocksize 32mb error
Very often just resistance choke, either by too low vSOC or too high procODT/cad_BUS

rly depends on the amount of errors followed one after another 
This current one is more a burst test error, which is either delay or voltage related
mostly precharge delay, because of error 11 which is more a writeback error after test 10
EDIT:
As it either is delay or tRP/voltage related - try to push tWRRD to 3 instead of two
Or put tRP higher


----------



## yrelbirb

a random question about dram calculator

https://prnt.sc/rzzhb1

as you can see the values the tool gave me especially tRCD weird, since geardown mode on makes it 20(or so i heard)

i think 1usmus should fix this? or he didnt bother bcoz its the same anyway (it will round to 20)

but again, it made me wonder

also; according the tool values tRFC wasn't a clean divider of tRC. do u have any idea why, a bug or a problem?


----------



## rares495

Veii said:


> it's been a bit of time, got rusty
> But yes you can
> Error test 10 is under a simple test size 8mb, it's a burst test / mostly voltage related, more delay related on cell precharge
> Test 11 error is a normal delay for 16mb block size, this is rather timings related
> 
> I can imagine it's copy, error, read error, copy error - what happened here
> tRP is either to low, tWR too low or you lowered vDIMM voltage
> anyhow, somewhere you choke on a burst write and read test
> But it's not a chargeback error, else test 9 would error with a blocksize of 4mb
> (that is rather a SOC voltage or too low vDIMM error)
> 
> Error 6 and 12 belong to the memory controller
> which come together, first error 6 size 1mb that is initialization error , either 4-5 times error 6=BSOD or 6,12
> Error on test 12 is blocksize 32mb error
> Very often just resistance choke, either by too low vSOC or too high procODT/cad_BUS
> 
> rly depends on the amount of errors followed one after another
> This current one is more a burst test error, which is either delay or voltage related
> mostly precharge delay, because of error 11 which is more a writeback error after test 10
> EDIT:
> As it either is delay or tRP/voltage related - try to push tWRRD to 3 instead of two
> Or put tRP higher


Voltage still 1.52V. Tried 1.5V and won't even boot properly.

Errors were pretty close together. 1-2 tests apart.

Should I increase tWR and tRTP a bit? Maybe 16-8? tWR 16 should be pretty optimal for me as per the calculation. (3800*8/2000=15.2)


----------



## Veii

yrelbirb said:


> a random question about dram calculator
> 
> https://prnt.sc/rzzhb1
> 
> as you can see the values the tool gave me especially tRCD weird, since geardown mode on makes it 20(or so i heard)
> 
> i think 1usmus should fix this? or he didnt bother bcoz its the same anyway (it will round to 20)
> 
> but again, it made me wonder
> 
> also; according the tool values tRFC wasn't a clean divider of tRC. do u have any idea why, a bug or a problem?


Alt value is a clean one - current value for whatever reason it's higher and not lower, has tSTAG included 
normally it should be lower - soo there is a bug that ALT isn't 522 but is *8=464
Here alt would work, but rec one has tSTAG included
if 464 runs, pick that - else 522 (my advice) but 525 can be perfectly calculated just that thaiphoon burner report gave it such high values

It can be true that 522 won't run, or that the dimm is badly programmed 
Prediction is not perfect on the dram calculator - such thing is not easy
Anyways, yes that's the reason  just bad prediction on ALT or rec one uses tSTAG 
~ for whatever reason it predicts it that high

I am not sure why it's not factored in for GDM
but you can see on tRC, that tRCD 20 is factored in not 19 - maybe just a bug


----------



## Veii

rares495 said:


> Voltage still 1.52V. Tried 1.5V and won't even boot properly.
> 
> Errors were pretty close together. 1-2 tests apart.
> 
> Should I increase tWR and tRTP a bit? Maybe 16-8? tWR 16 should be pretty optimal for me as per the calculation. (3800*8/2000=15.2)


Your optimal tWR is between 10,12,14, at least tRAS-tRCD is 14 or 16
Yes 16 can run well but try to change for now tWRRD to 3
If that doesn't work it's tWR to 16 try - if it doesn't post, you have to keep it 14 or lower 
if you use 14, better use tRTP 8 not 6
Else tWR 12

Anyways, it's a precharge delay issue, on a small burst test
If 1.53v doesn't resolve that, you rly have to change timings a bit
EDIT: Having low tRP needs higher voltage soo current remains a bit


----------



## rares495

Veii said:


> Your optimal tWR is between 10,12,14, at least tRAS-tRCD is 14 or 16
> Yes 16 can run well but try to change for now tWRRD to 3
> If that doesn't work it's tWR to 16 try - if it doesn't post, you have to keep it 14 or lower
> if you use 14, better use tRTP 8 not 6
> Else tWR 12
> 
> Anyways, it's a precharge delay issue, on a small burst test
> If 1.53v doesn't resolve that, you rly have to change timings a bit


This image makes me laugh quite a bit.

Yeah, I'll try tWRRD 3 then the rest.


----------



## rares495

Veii said:


> Your optimal tWR is between 10,12,14, at least tRAS-tRCD is 14 or 16
> Yes 16 can run well but try to change for now tWRRD to 3
> If that doesn't work it's tWR to 16 try - if it doesn't post, you have to keep it 14 or lower
> if you use 14, better use tRTP 8 not 6
> Else tWR 12
> 
> Anyways, it's a precharge delay issue, on a small burst test
> If 1.53v doesn't resolve that, you rly have to change timings a bit


Now a single error in test 2 and then 3 errors in 1 second on test 2 in cycle 3 + single error in test 10 on cycle 3.

EDIT: 3 errors in 1 second test 10 cycle 4.


----------



## nick name

rares495 said:


> Now a single error in test 2 and then 3 errors in 1 second on test 2 in cycle 3 + single error in test 10 on cycle 3.
> 
> EDIT: 3 errors in 1 second test 10 cycle 4.


Increase tRCDRD by 1.


----------



## rares495

nick name said:


> Increase tRCDRD by 1.


But I want it at 14 or lower.


----------



## nick name

rares495 said:


> But I want it at 14 or lower.


It's kinda just a Ryzen thing.


----------



## rares495

Veii said:


> Your optimal tWR is between 10,12,14, at least tRAS-tRCD is 14 or 16
> Yes 16 can run well but try to change for now tWRRD to 3
> If that doesn't work it's tWR to 16 try - if it doesn't post, you have to keep it 14 or lower
> if you use 14, better use tRTP 8 not 6
> Else tWR 12
> 
> Anyways, it's a precharge delay issue, on a small burst test
> If 1.53v doesn't resolve that, you rly have to change timings a bit
> EDIT: Having low tRP needs higher voltage soo current remains a bit


Nothing worked, as usual. Getting rid of errors in tests 10,11 got me errors in tests 2, 13 and vice versa.


----------



## nick name

I got tRFC below 310 overnight-stable finally. I had to increase some primary and secondaries, but that's ok. Something else I learned is that using a fixed CPU multiplier results in a lower latency in Aida. Even if it's a lower multiplier than what max boost on the CPU is. Also, slightly more bandwidth in SiSoftware Sandra.

Edit:
Decided to run another test today. TM5 anta777 profile. I got one error. Grrrrrrr.

Edit 2:
I added some more voltage (1.52V) to account for the droop down to 1.472V and it passed that test without errors.


----------



## PolRoger

nick name said:


> I got tRFC below 310 overnight-stable finally. I had to increase some primary and secondaries, but that's ok. Something else I learned is that using a fixed CPU multiplier results in a lower latency in Aida. Even if it's a lower multiplier than what max boost on the CPU is. Also, slightly more bandwidth in SiSoftware Sandra.


Those timings are looking pretty tight  ... Are you still running @C14 with ~1.5v DRAM? 

I've been trying to zero in on some decent daily (medium/fast) timings @3800C16 4 DIMMMs... I might give some of those settings a try using two sticks (2x8GB) perhaps to use for benching purposes?


----------



## Muqeshem

nick name said:


> I got tRFC below 310 overnight-stable finally. I had to increase some primary and secondaries, but that's ok. Something else I learned is that using a fixed CPU multiplier results in a lower latency in Aida. Even if it's a lower multiplier than what max boost on the CPU is. Also, slightly more bandwidth in SiSoftware Sandra.


can you please share the voltages and power settings please ?


----------



## nick name

PolRoger said:


> Those timings are looking pretty tight  ... Are you still running @C14 with ~1.5v DRAM?
> 
> I've been trying to zero in on some decent daily (medium/fast) timings @3800C16 4 DIMMMs... I might give some of those settings a try using two sticks (2x8GB) perhaps to use for benching purposes?





Muqeshem said:


> can you please share the voltages and power settings please ?



The timings are in the screen grabs. They are 14-16-14-14.

I am running 1.5V on DRAM and 1.106 on SOC to account for the droop. VDDG is 1050 and VDDP is 1000. My DRAM seems to droop down to around 1.472V ~ 1.482V according to HWiNFO. 


I ran another TM5 test and it revealed 1 error. I added that to my post above.


----------



## Veii

@nick name Good job :thumb:
Two things
get tRFC2 and tRFC4 correct because you use GDM
soo tCKE will work too 
if you already did , then try to scale up tCKE to 6 slowly 
and even if at 6 it doesn't do anything
try tRRDL on 5 
Unsure about tWTRL on 8, 3-10 would it be or 4-12

continue the experiment  
VDDP might be uselessly that high , could try cutting 25mV on it too ~ might be even 50mV away
As 950mV cLDO_VDDP, 1025mV cLODO_VDDG and same 1.1v vSOC

if VDDP is too low, your procODT is a bit too high
work with CAD_BUS against it to fix it - the first value


----------



## glnn_23

Picked up a 3900x yesterday and running in an Asus C8H.
Little easier running 2 x 8Gb than with 4 so far. Trying to run IF 1900..


----------



## nick name

glnn_23 said:


> Picked up a 3900x yesterday and running in an Asus C8H.
> Little easier running 2 x 8Gb than with 4 so far. Trying to run IF 1900..


Well aren't you a quick learner. Have you been keeping up with the thread before getting that 3900X?


----------



## thomasck

Can't make 1900 1:1 here, maybe is the CPU (most likely), maybe is the board, taichi x370. 

I can squeeze a bit more here, reducing tCL to 14, but what gives me better latency is getting tRFC to 261, but with the expense of more voltage, I'm fine at 1.46V ATM. tCL to 14 seems to don't change anything in terms of read/write/latency.
I still have some micro-pauses while gaming, here and there, and sure is something about my timings, it's not critical, but in some matches is pretty noticeable, then it goes away.

I know the thread holds a preference for HCI test, but I don't trust it any more like I did before. My to go test now is memtest/karhu, no "cause it's faster", but cause memtest/karhu actually did find an error which HCI and others did not find, for almost a year a had a unstable rig cause of that, and I could never figure out what was the problem. Once I ran memtest/karhu it found one error, bumbed the ram voltage (which was already at 1.45V) a bit and voilá, no more crashes in game. I was almost RMAing the GPU thinking it was the culprit. 

The kit is HyperX Pretador 4000 CL19, Sam bdie.


----------



## glnn_23

nick name said:


> Well aren't you a quick learner. Have you been keeping up with the thread before getting that 3900X?


While I do look at this thread every now and then I've had a 3600, 3900x and 3950x in the past. Used these with a C7H and Impact. The 3 Asus boards are very similar. 

All credit to 1usmus and the Ryzen DRAM Calculator.


----------



## nick name

glnn_23 said:


> While I do look at this thread every now and then I've had a 3600, 3900x and 3950x in the past. Used these with a C7H and Impact. The 3 Asus boards are very similar.
> 
> All credit to 1usmus and the Ryzen DRAM Calculator.


Ahhhh. That makes sense.


----------



## 2600ryzen

Got my 3600 today now my [email protected] Micron A-die works fine at stock settings and even did 1 pass of memtest86 at cl18 3600mhz. Think I'm going to stick to cl16 3400mhz for now, nearly stabilized my timings I only have tRDWR left to tighten, couldn't get the primaries any tighter.


----------



## Domdabom04

I can't seem to lower my tWR timing. I initially settled on 16, the "safe" preset according to the GitHub guide. Turns out that it was unstable, and the lowest I can get it stable is 22. My ICs are Hynix DJR. Here are my other settings:

DDR4-3733
16-19-8-20-36
tRC: 56
tRFC: 500
tWTR_S: 4
tWTR_L: 10
tRTP: 11
tRRD_S: 4
tRRD_L: 6
tFAW: 16
tCWL: 16
tCKE:1

The tertiaries are at 4-1-1-1-2-1-1-1, and tRDWR and tWRRD are 10 and 1 respectively. From everything I've seen, tWR should be able to go much lower than this. Help would be appreciated, thanks


----------



## 2600ryzen

Domdabom04 said:


> I can't seem to lower my tWR timing. I initially settled on 16, the "safe" preset according to the GitHub guide. Turns out that it was unstable, and the lowest I can get it stable is 22. My ICs are Hynix DJR. Here are my other settings:
> 
> DDR4-3733
> 16-19-8-20-36
> tRC: 56
> tRFC: 500
> tWTR_S: 4
> tWTR_L: 10
> tRTP: 11
> tRRD_S: 4
> tRRD_L: 6
> tFAW: 16
> tCWL: 16
> tCKE:1
> 
> The tertiaries are at 4-1-1-1-2-1-1-1, and tRDWR and tWRRD are 10 and 1 respectively. From everything I've seen, tWR should be able to go much lower than this. Help would be appreciated, thanks





TRTP needs to be at least half of TWR on my kit or it wont post. Try TRPT of 10 with TWR of 20, or 8/16.


----------



## PolRoger

4 DIMM (4x8GB) 3800C16 Samsung B-die results/settings...

With 4 DIMMs populated at 3800 MT/s, I haven't had much luck running with Gear Down Mode disabled or at Cas 14/15. I settled on Cas 16 with Gear Down Mode enabled. Contributing factors to stability are the quality of the B-die IC in the individual memory sticks; The UCLK/FCLK quality of the individual Ryzen 2 CPU (strong IMC?) and the specific motherboard/BIOS combo that the setup is running/testing out in.

#1: 3950X/ASUS CH8H (WiFi) ~1.41v DRAM, ~1.1v SOC:

#2: 3900X/ASRock Taichi ~1.415v DRAM, ~1.1v SOC:

#3: 3900X/ASUS CH7H (WiFi) ~1.44v DRAM, ~1.1v SOC:


With setup #1: I was able to pass stability with TRRD_S&L @4/6 along with SCL 3.

With setup #2: I was able to pass stability but had to back down a bit to TRRD_ S&L @5/6 along with SCL 4.

With setup #3: I was able to pass stability but also had to back off some to TRRD_S&L @5/5 along with SCL 4. The memory sticks also needed a bump up in DRAM (~1.44v) to boot @3800 MT/s with this combo.


----------



## Cosminnn

I got 4 errors. Primaries and secondaries set up and tertiary on auto. RAM voltage on 1,52 V.

Is there anything to change?


----------



## nick name

Cosminnn said:


> I got 4 errors. Primaries and secondaries set up and tertiary on auto. RAM voltage on 1,52 V.
> 
> Is there anything to change?


I'm surprised you got so few with tRCDRD below tCL.


----------



## fingon82

I got 0 with TCL 14 and tRCDRD 13 1,35v
So far, stabile for a 3-4 days

Did anyone runs 24/7 TRAS amd TRCD lower than TCL+TRP, and TRAS+TRP?


----------



## Cosminnn

nick name said:


> I'm surprised you got so few with tRCDRD below tCL.


I lowered to 14 and recalculated tras and trc ... but still 2 errors.


----------



## fingon82

Probably bcs of low TRFC


----------



## rares495

Cosminnn said:


> I lowered to 14 and recalculated tras and trc ... but still 2 errors.


Try tRCDRD 15, tRAS 30, tRC 43. Voltage 1.5V

Keep in mind that the PCBs are A2 and won't go as tight as A0/A1. You might have hit the limit already.

Alternatively, you can just use Buildzoid's Viper Steel timings and go down from there. Check the attached screenshot for that.


----------



## LicSqualo

fingon82 said:


> I got 0 with TCL 14 and tRCDRD 13 1,35v
> So far, stabile for a 3-4 days
> 
> Did anyone runs 24/7 TRAS amd TRCD lower than TCL+TRP, and TRAS+TRP?


Yes, me. For about two years now.


----------



## fingon82

Thanks, LicSqualo.

Damn, my english is rusty+typos everywhere, i just noticed in your quote...


----------



## Cosminnn

fingon82 said:


> Probably bcs of low TRFC





rares495 said:


> Try tRCDRD 15, tRAS 30, tRC 43. Voltage 1.5V
> 
> Keep in mind that the PCBs are A2 and won't go as tight as A0/A1. You might have hit the limit already.
> 
> Alternatively, you can just use Buildzoid's Viper Steel timings and go down from there. Check the attached screenshot for that.


Increased TRFC to 280 .. looks like it did the job.


----------



## rares495

Cosminnn said:


> Increased TRFC to 280 .. looks like it did the job.


Nope. 3 cycles is nothing. You have to pass 20 cycles. Use the TM5 that I have attached.


----------



## LicSqualo

rares495 said:


> Nope. 3 cycles is nothing. You have to pass 20 cycles. Use the TM5 that I have attached.


I tried your attachment: only 3 cycles and only 5 tests. Perhaps is the wrong version.


----------



## nick name

Cosminnn said:


> Increased TRFC to 280 .. looks like it did the job.


Whoa. I don't think I've seen a Ryzen CPU run faster than 3600MHz with tRCDRD the same as tCL without errors. That's pretty sweet.

Edit:

This is what my kit does.


----------



## fingon82

LicSqualo said:


> I tried your attachment: only 3 cycles and only 5 tests. Perhaps is the wrong version.


Its good, but you must load config from bin dir and run exe as admin


----------



## LicSqualo

fingon82 said:


> Its good, but you must load config from bin dir and run exe as admin


Thanks! Much appreciated. I've reload the 1usmus version and changed to test 20 times.


----------



## thomasck

Where do you guys get those profiles to run with TM5? Thanks.


----------



## Hequaqua

thomasck said:


> Where do you guys get those profiles to run with TM5? Thanks.


You can them from his profile. They are listed at the bottom. 

https://www.overclock.net/forum/27937684-post4314.html


----------



## thomasck

Hequaqua said:


> You can them from his profile. They are listed at the bottom.
> 
> 
> 
> https://www.overclock.net/forum/27937684-post4314.html


Thanks!

Sent from Tapatalk


----------



## CaptnNemo

I guess I'll ask here. I just purchased the MSI Meg Ace X570 with the 3950x. I have Gskill 2x16gb 3000mhz CL14 which I OC at 3800mhz. So far so good. My timings are 16-17-17-36
at 1.42v.

I have not ran intensive testing on them yet but I played about 5 heavy demanding games for a while and no crashes or anything. Do you experts think I am safe with this and if so, is there any more juice I could squeeze out of these pair of sticks ? or should I just leave it as is ?

I'm quite new in OC memory so I don't know every settings and what they do exactly.

Thank you


----------



## rastaviper

CaptnNemo said:


> I guess I'll ask here. I just purchased the MSI Meg Ace X570 with the 3950x. I have Gskill 2x16gb 3000mhz CL14 which I OC at 3800mhz. So far so good. My timings are 16-17-17-36
> 
> at 1.42v.
> 
> 
> 
> I have not ran intensive testing on them yet but I played about 5 heavy demanding games for a while and no crashes or anything. Do you experts think I am safe with this and if so, is there any more juice I could squeeze out of these pair of sticks ? or should I just leave it as is ?
> 
> 
> 
> I'm quite new in OC memory so I don't know every settings and what they do exactly.
> 
> 
> 
> Thank you


Well from 3000 up to 3800 is not a small thing, but the timings are quite high.
It's always better if you could make them more tight.

Sent from my ONEPLUS A6003 using Tapatalk


----------



## CaptnNemo

rastaviper said:


> Well from 3000 up to 3800 is not a small thing, but the timings are quite high.
> It's always better if you could make them more tight.
> 
> Sent from my ONEPLUS A6003 using Tapatalk


Right!! thnx, I'll try to fiddle with them a bit. Do the software for Ryzen DDR4 thing calculator actually gives you what your memory is capable of theoretically or its just the user that inputs whatever timings and it gives out the rest of the settings accordingly ?

Thank you


----------



## rastaviper

CaptnNemo said:


> Right!! thnx, I'll try to fiddle with them a bit. Do the software for Ryzen DDR4 thing calculator actually gives you what your memory is capable of theoretically or its just the user that inputs whatever timings and it gives out the rest of the settings accordingly ?
> 
> Thank you


Personally I have managed to get much lower timings with my bdies than what the Dram Calc was suggesting.
But still, it's a very useful tool to use when u start tweaking your ram. Then it's just try and error to reach the lowest timings.


----------



## CaptnNemo

rastaviper said:


> Personally I have managed to get much lower timings with my bdies than what the Dram Calc was suggesting.
> But still, it's a very useful tool to use when u start tweaking your ram. Then it's just try and error to reach the lowest timings.


I see, alright I will start with that and than see how I can lower the timings while having sustainable stability. I have Bdies too on my ram so there's that at least.

Thanks again for your suggestion.


----------



## jcpq

Ryzen 3600X
G.Skill Flare X [email protected]
Asus x570-i


----------



## duox7142

Hey everyone! 

Recently been getting into the fun world of AMD memory overclocking, and I'm reaching out because I'm starting to hit a wall.

My specs are:
Ryzen 9 3950X
4x 8gb 3200c14 Samsung b-die
ASRock x570 Taichi

The RAM is currently running 3600c14 no problem, FCLK 1:1 at 1800mhz.

My RAM, with the right settings, can be stable at 3800mhz with loose timings. However, when running Karhu or TM5 for over an hour or two, the computer will black screen and reboot, with no prior error message. I tried everything at stock, but only with FCLK at 1900mhz in RandomX, which is good for testing FCLK. fails after an hour. I've been told that it is due to AMD infinity fabric not stable at that range. I also heard cDLO_VDDG increase can help stabilize it. When I go into the BIOS to set VDDP and VDDG to fixed values, the system refuses to post, even though I initially set them to match what they are at on auto. It makes no sense why manual setting fails where it matches auto. They're less than SOC, so there's that. For record, SOC autos to 1.2v and VDDG /VDDP at 1.1v. im wondering if 1.11 or 1.12v on VDDG can get FCLK stable.

So my questions are, 1) why does my BIOS refuse to post when VDDP and VDDG are manually set at any level? 2) is it possible VDDG can increase FCLK stability? 3) what else could aid in FCLK stability? Temperature, connecting the additional optional 4pin EPS connector, motherboard, etc? Thanks!


----------



## rares495

duox7142 said:


> Hey everyone!
> 
> Recently been getting into the fun world of AMD memory overclocking, and I'm reaching out because I'm starting to hit a wall.
> 
> My specs are:
> Ryzen 9 3950X
> 4x 8gb 3200c14 Samsung b-die
> ASRock x570 Taichi
> 
> The RAM is currently running 3600c14 no problem, FCLK 1:1 at 1800mhz.
> 
> My RAM, with the right settings, can be stable at 3800mhz with loose timings. However, when running Karhu or TM5 for over an hour or two, the computer will black screen and reboot, with no prior error message. I tried everything at stock, but only with FCLK at 1900mhz in RandomX, which is good for testing FCLK. fails after an hour. I've been told that it is due to AMD infinity fabric not stable at that range. I also heard cDLO_VDDG increase can help stabilize it. When I go into the BIOS to set VDDP and VDDG to fixed values, the system refuses to post, even though I initially set them to match what they are at on auto. It makes no sense why manual setting fails where it matches auto. They're less than SOC, so there's that. For record, SOC autos to 1.2v and VDDG /VDDP at 1.1v. im wondering if 1.11 or 1.12v on VDDG can get FCLK stable.
> 
> So my questions are, 1) why does my BIOS refuse to post when VDDP and VDDG are manually set at any level? 2) is it possible VDDG can increase FCLK stability? 3) what else could aid in FCLK stability? Temperature, connecting the additional optional 4pin EPS connector, motherboard, etc? Thanks!


1) Because your BIOS is dumb. VDDP should be lower than VDDG though.

2) Yes

3) Temperature - no; additional 4pin - no

VDDG should be at least 50mV lower than the SOC voltage (which goes up to 1.1V "safely") => max VDDG = 1.050V


----------



## PolRoger

duox7142 said:


> Hey everyone!
> 
> Recently been getting into the fun world of AMD memory overclocking, and I'm reaching out because I'm starting to hit a wall.
> 
> My specs are:
> Ryzen 9 3950X
> 4x 8gb 3200c14 Samsung b-die
> ASRock x570 Taichi
> 
> The RAM is currently running 3600c14 no problem, FCLK 1:1 at 1800mhz. My RAM, with the right settings, can be stable at 3800mhz with loose timings.


I have a 3950X that can't/won't post at 3800 MT/s 1:1... I don't think that particular sample will do 1900MHz FCLK? Max seems to be ~1866MHz. I also have the X570 Taichi and I'm not having trouble manually setting VDDP/VDDG voltages?

Did you purchase a quad kit (4x8GB) or two (2x8GB) kits? It may be easier to test/dial-in your 3800 MT/s settings at first with just two sticks DIMMs populated and test again later with four sticks??

Some more 4x8GB settings here:
https://www.overclock.net/forum/10-...memory-stability-thread-354.html#post28417226


----------



## yrelbirb

rares495 said:


> 1) Because your BIOS is dumb. VDDP should be lower than VDDG though.
> 
> 2) Yes
> 
> 3) Temperature - no; additional 4pin - no
> 
> VDDG should be at least 50mV lower than the SOC voltage (which goes up to 1.1V "safely") => max VDDG = 1.050V


do vddg and vddp voltages matter for zen+? i have a dumb gigabyte motherboard (b450 gaming x), which cant even properly show vcore voltages when an offset is put. i wonder if its dumb and spits out dangerous levels of voltages to the voltages that it does not show...


----------



## hazium233

yrelbirb said:


> do vddg and vddp voltages matter for zen+? i have a dumb gigabyte motherboard (b450 gaming x), which cant even properly show vcore voltages when an offset is put. i wonder if its dumb and spits out dangerous levels of voltages to the voltages that it does not show...


Zen1 and Zen+ don't have CLDO_VDDG at all. CLDO_VDDP exists, on Zen+ with two single rank dimms, you often do not need to go down the rabbit hole of testing the steps. Useful range is 700- 975mV or so, you can find charts of the steps to try, but even then it is plausible that best can be in between. You can attempt to tune it to resolve a memory hole, but you probably won't find a real hole with the later default values.


----------



## FrivolousJay

Veii said:


> tWR should be in sync with tRFC if possible , if not possible at least tRTP has to be
> Preferable to keep tWR in sync and see if how tRTP behaves, if 6 is possible else just half of current tWR



How do I sync tWR with tRFC?


----------



## 2600ryzen

FrivolousJay said:


> How do I sync tWR with tRFC?



tRFC / tWR = a whole number. I just adjust tRFC slightly up from 295ns until it's a whole number.


----------



## FrivolousJay

2600ryzen said:


> tRFC / tWR = a whole number. I just adjust tRFC slightly up from 295ns until it's a whole number.



Thank you and thanks to everyone else that provided knowledge in this thread. 



Using this thread as a guide I was able to get my RAM to run stable at these timings. I can get onto the desktop and start TM5 with GDM On/1T at 1.51v but it starts showing errors right away then crashes. I don't think I want to go any higher than 1.51v. GDM Off/2T and GDM On/1T didn't show any difference in latency in Aida64, however, GDM off/2T provided better results in CBR20 (average of 3 runs). Is there anything else you guys see that I can try tightening some more? Current voltages are 1.5v DRAM, 1.1 SoC, .950 VDDP, .1050 VDDG.


----------



## Cosminnn

duox7142 said:


> Hey everyone!
> 
> Recently been getting into the fun world of AMD memory overclocking, and I'm reaching out because I'm starting to hit a wall.
> 
> My specs are:
> Ryzen 9 3950X
> 4x 8gb 3200c14 Samsung b-die
> ASRock x570 Taichi
> 
> The RAM is currently running 3600c14 no problem, FCLK 1:1 at 1800mhz.
> 
> My RAM, with the right settings, can be stable at 3800mhz with loose timings. However, when running Karhu or TM5 for over an hour or two, the computer will black screen and reboot, with no prior error message. I tried everything at stock, but only with FCLK at 1900mhz in RandomX, which is good for testing FCLK. fails after an hour. I've been told that it is due to AMD infinity fabric not stable at that range. I also heard cDLO_VDDG increase can help stabilize it. When I go into the BIOS to set VDDP and VDDG to fixed values, the system refuses to post, even though I initially set them to match what they are at on auto. It makes no sense why manual setting fails where it matches auto. They're less than SOC, so there's that. For record, SOC autos to 1.2v and VDDG /VDDP at 1.1v. im wondering if 1.11 or 1.12v on VDDG can get FCLK stable.
> 
> So my questions are, 1) why does my BIOS refuse to post when VDDP and VDDG are manually set at any level? 2) is it possible VDDG can increase FCLK stability? 3) what else could aid in FCLK stability? Temperature, connecting the additional optional 4pin EPS connector, motherboard, etc? Thanks!


"the computer will black screen and reboot, with no prior error message"
Looks like a CPU instability .. do you overclock your CPU?


----------



## 2600ryzen

FrivolousJay said:


> Thank you and thanks to everyone else that provided knowledge in this thread.
> 
> 
> 
> Using this thread as a guide I was able to get my RAM to run stable at these timings. I can get onto the desktop and start TM5 with GDM On/1T at 1.51v but it starts showing errors right away then crashes. I don't think I want to go any higher than 1.51v. GDM Off/2T and GDM On/1T didn't show any difference in latency in Aida64, however, GDM off/2T provided better results in CBR20 (average of 3 runs). Is there anything else you guys see that I can try tightening some more? Current voltages are 1.5v DRAM, 1.1 SoC, .950 VDDP, .1050 VDDG.



I found GDM needed 0.01v/0.02v more DRAM voltage than 2t for some reason, if GDM is throwing errors in testmem5 then that's what's probably caused it to benchmark worse too.
You might be able to get tRDWR and tWRRD down to 7-4 or 6-4 instead of 8-1.


----------



## Cosminnn

After I set tWR in sync with tRFC and tRTP, still have one error on a 10 cycle run.


----------



## rares495

Cosminnn said:


> After I set tWR in sync with tRFC and tRTP, still have one error on a 10 cycle run.


That kit will never be stable with those timings. (unless you push 1.7V or something)

Error 11 seems to be related to timings.


----------



## Cosminnn

rares495 said:


> That kit will never be stable with those timings. (unless you push 1.7V or something)
> 
> Error 11 seems to be related to timings.


I guess also the test is quite demanding ... I passed almost 18 hours of Karhu, memtest with 16 instances 500%, only here I bump into troubles.
I do overclocking just for fun and hobby, no demanding games or editing.

I guess I am fine with those timings and level of stability or ... almost 99% stability to use as daily driver.

I might watch buildzoid video on 4400 patriots again and try to achieve cl12 on 3800 ... pushing 2v into the RAM and get a stable reading for a nice pic to show on formus ... not for daily use. 

Thank you all for feed-back.


----------



## duox7142

Cosminnn said:


> "the computer will black screen and reboot, with no prior error message"
> Looks like a CPU instability .. do you overclock your CPU?


Infinity fabric is CPU overclocking essentially. But normally I'm only running PBO with 300/230/230. Maybe PBO needs more voltage when paired with RAM OC? VDDG would give the Infinity Fabric more stability, but my computer balks when I try to increase it.


----------



## fingon82

Cosminnn said:


> After I set tWR in sync with tRFC and tRTP, still have one error on a 10 cycle run.


Try trcdrd 15,and maybe a bit higher trfc


----------



## nick name

Cosminnn said:


> I guess also the test is quite demanding ... I passed almost 18 hours of Karhu, memtest with 16 instances 500%, only here I bump into troubles.
> I do overclocking just for fun and hobby, no demanding games or editing.
> 
> I guess I am fine with those timings and level of stability or ... almost 99% stability to use as daily driver.
> 
> I might watch buildzoid video on 4400 patriots again and try to achieve cl12 on 3800 ... pushing 2v into the RAM and get a stable reading for a nice pic to show on formus ... not for daily use.
> 
> Thank you all for feed-back.


When you test with Karhu -- don't forget to Enable CPU cache testing in the Advanced tab.


----------



## nick name

Cosminnn said:


> After I set tWR in sync with tRFC and tRTP, still have one error on a 10 cycle run.


I'm still amazed that you can run your tRCDRD the same as tCL and only get one error so it makes trying to trying to help you a bit of a guessing game. 

What is your SOC and DRAM voltage? I have to run 1.52V on DRAM to get 1.5V after droop and 1.106V on SOC to get 1.1V after droop and that cured my 1 error problem. Perhaps you're similar?


----------



## Cosminnn

nick name said:


> Cosminnn said:
> 
> 
> 
> After I set tWR in sync with tRFC and tRTP, still have one error on a 10 cycle run.
> 
> 
> 
> I'm still amazed that you can run your tRCDRD the same as tCL and only get one error so it makes trying to trying to help you a bit of a guessing game.
> 
> What is your SOC and DRAM voltage? I have to run 1.52V on DRAM to get 1.5V after droop and 1.106V on SOC to get 1.1V after droop and that cured my 1 error problem. Perhaps you're similar?
Click to expand...

I made an escape from the lockdown in the big city and went to the country side on my in-laws house, so I am away from my desktop. 
From what I remember, 1,52 or 1,53V on dram and auto on the rest. Same as other colleague mentioned here, on X570 Taichi, I can not set manually the voltages, I mean I can but it won't boot. Only works with auto. 
I did not found a software tool to read the mentioned voltages on windows and bios won't show them.


----------



## nick name

Cosminnn said:


> I made an escape from the lockdown in the big city and went to the country side on my in-laws house, so I am away from my desktop.
> From what I remember, 1,52 or 1,53V on dram and auto on the rest. Same as other colleague mentioned here, on X570 Taichi, I can not set manually the voltages, I mean I can but it won't boot. Only works with auto.
> I did not found a software tool to read the mentioned voltages on windows and bios won't show them.


HWiNFO will show you voltages. Though for your board I can't say how accurate it will be.


----------



## rares495

Cosminnn said:


> I might watch buildzoid video on 4400 patriots again and try to achieve cl12 on 3800 ... pushing 2v into the RAM and get a stable reading for a nice pic to show on formus ... not for daily use.


5 o'clock news: Romanian overclocker killed in house fire after attempting XOC on air cooling.


----------



## CaptnNemo

Well, don't think I'll be squeezing much more out of my Gskill CL14 3000mhz kit lolll. Voltage is at 1.45

Don't want to risk higher just in case


----------



## rares495

CaptnNemo said:


> Well, don't think I'll be squeezing much more out of my Gskill CL14 3000mhz kit lolll. Voltage is at 1.45
> 
> Don't want to risk higher just in case


Something's definitely wrong there. 68ns is way too much latency for 3800 C16. That's a B-die kit, right?


----------



## FrivolousJay

2600ryzen said:


> I found GDM needed 0.01v/0.02v more DRAM voltage than 2t for some reason, if GDM is throwing errors in testmem5 then that's what's probably caused it to benchmark worse too.
> You might be able to get tRDWR and tWRRD down to 7-4 or 6-4 instead of 8-1.



Upping the DRAM voltage by 0.01 helped boost CB performance on GDM on/1T over GDM off/2T. Thanks! I tried running GDM off/1T at 1.52v but TM5 still threw up errors as soon as the test started. Guess I'll have to settle for GDM on. tRDWR and tWRRD 7/4 is running stable so far. Are there other timings that I have to re-adjust to align it with the 7/4?


----------



## CaptnNemo

rares495 said:


> Something's definitely wrong there. 68ns is way too much latency for 3800 C16. That's a B-die kit, right?


Yes it is. How should I set it then ?

Thnx


----------



## CaptnNemo

Thats Gskill official screenshot of their Optimized 3800 kit.


https://www.gskill.com/community/15...Memory-Kit-for-AMD-Ryzen-3000-&-X570-Platform


I thought I managed good considering loll I don't know all the settings and what they do exactly towards eachother.


----------



## PolRoger

CaptnNemo said:


> Thats Gskill official screenshot of their Optimized 3800 kit.
> 
> 
> https://www.gskill.com/community/15...Memory-Kit-for-AMD-Ryzen-3000-&-X570-Platform
> 
> 
> I thought I managed good considering loll I don't know all the settings and what they do exactly towards eachother.



You are running this dual rank kit right?... "I have Gskill 2x16gb 3000mhz CL14" 

Your GSkill link shows for single rank B-die... With 2x8GB and 4x8GB sticks.

Have you tried "1usmus" settings for dual rank kits?

#1 2R 3800 Safe:
#2 2R 3800 Fast:


----------



## neurotix

CaptnNemo said:


> Thats Gskill official screenshot of their Optimized 3800 kit.
> 
> 
> https://www.gskill.com/community/15...Memory-Kit-for-AMD-Ryzen-3000-&-X570-Platform
> 
> 
> I thought I managed good considering loll I don't know all the settings and what they do exactly towards eachother.





PolRoger said:


> You are running this dual rank kit right?... "I have Gskill 2x16gb 3000mhz CL14"
> 
> Your GSkill link shows for single rank B-die... With 2x8GB and 4x8GB sticks.
> 
> Have you tried "1usmus" settings for dual rank kits?
> 
> #1 2R 3800 Safe:
> #2 2R 3800 Fast:



Did you guys notice in G.skills screenshot, that they were using AGESA 1.0.0.3??? Not even 1.0.0.3ab or the current 1.0.0.4 but an ancient firmware from right before launch..

On that AGESA version I do 60gb/sec copy, 59gb/sec write, 62GB/sec copy @ 63.5ns which is 3ns better than G.skill's. so much for engineers, just get Flare X


----------



## jcpq

neurotix said:


> Did you guys notice in G.skills screenshot, that they were using AGESA 1.0.0.3??? Not even 1.0.0.3ab or the current 1.0.0.4 but an ancient firmware from right before launch..
> 
> On that AGESA version I do 60gb/sec copy, 59gb/sec write, 62GB/sec copy @ 63.5ns which is 3ns better than G.skill's. so much for engineers, just get Flare X


Hello Neurotix

I also have Flare X

You could share your settings / timings for (G.SKILL Flare X B-Die 3200 C14 @ 3800MHz C14-16-15-15-30-48 1T 1.475v GDM off)

Thanks


----------



## Cosminnn

nick name said:


> HWiNFO will show you voltages. Though for your board I can't say how accurate it will be.


Now that I got more time to reflect, my voltage limitation applies to VDDP and VDDG, I can set Soc/Uncore OC Voltage, but I still have it on auto.

HWiNFO shows me DRAM voltage, if I remember correctly a little lower than what is set up in BIOS and other DRAM related voltage ... not sure what it is exactly, at around 1.045v ... Premium VD something.

Is there any other RAM related voltage values reflected in HWinfo?

I'll provide more info when I return to "big city lock-down".


----------



## 2600ryzen

Ryzen master shows the correct SOC/VDDG/VDDP voltages, if you set the SOC/VDD voltages under the AMB CBS/Overclocking menu in bios. I have to have my motherboard SOC voltage control on auto for that to work though.


----------



## Karagra

This is my current setup.


----------



## pikmin

Hey. Can someone point me in the right direction to find where I can download Anta777 version of TM5? I finally built a new PC in over 5 years and got some Gskills F4-3600c15D_16GTZ running with a X3700. I overclocked them to 14-15-14-28 using the DRAM calculator. It seems pretty stable at the moment. I passed TM5 using 1usmus V3 config and passed DRAM calculator MemBench on easy. 

I am thinking that I should run Anta777 TM5 config too to be on the safe side and to have piece of mind. I don't mind running another test on top of Anta777 if someone can recommend one.


Thanks,


----------



## Hequaqua

pikmin said:


> Hey. Can someone point me in the right direction to find where I can download Anta777 version of TM5? I finally built a new PC in over 5 years and got some Gskills F4-3600c15D_16GTZ running with a X3700. I overclocked them to 14-15-14-28 using the DRAM calculator. It seems pretty stable at the moment. I passed TM5 using 1usmus V3 config and passed DRAM calculator MemBench on easy.
> 
> I am thinking that I should run Anta777 TM5 config too to be on the safe side and to have piece of mind. I don't mind running another test on top of Anta777 if someone can recommend one.
> 
> 
> Thanks,


Here is the config file for Anta777:

View attachment [email protected]


----------



## Veii

@pikmin define passed
6 rounds or 20 rounds
some errors like bad tRFC appears only after 19 rounds - about 1:30h exactly before TM5 20 rounds end

Another good testing tool is passing y-cruncher the first 3 tests couple of times 
As they will fail when the memory controller fails
^ which are then more voltage related by still go hand in hand with memory OC


----------



## kyo2020




----------



## Dollar

If anyone is interested I found an amazing review by Reous which tests the performance benefit of tightening each timing. Why bother running some timings at the bleeding edge of stability when it doesn't really increase performance much?


https://www.hardwareluxx.de/communi...fluss-auf-spiele-und-anwendungen-amd.1269156/


----------



## hazium233

Veii said:


> @pikmin define passed
> 6 rounds or 20 rounds
> some errors like bad tRFC appears only after 19 rounds - about 1:30h exactly before TM5 20 rounds end
> 
> Another good testing tool is passing y-cruncher the first 3 tests couple of times
> As they will fail when the memory controller fails
> ^ which are then more voltage related by still go hand in hand with memory OC


What are decent settings for using y-cruncher stress test? I have only briefly played with it, one thing I thought was annoying was that "time per test" seemed to apply only to iterations or something, but the tests themselves were running more iterations than I expected.


----------



## rares495

Dollar said:


> If anyone is interested I found an amazing review by Reous which tests the performance benefit of tightening each timing. Why bother running some timings at the bleeding edge of stability when it doesn't really increase performance much?
> 
> 
> https://www.hardwareluxx.de/communi...fluss-auf-spiele-und-anwendungen-amd.1269156/


You have to go low but also sync all timings for the best performance. Sync seems to be more important than going low for stability but for performance going as low as possible is absolutely necessary.


----------



## 2600ryzen

Dollar said:


> If anyone is interested I found an amazing review by Reous which tests the performance benefit of tightening each timing. Why bother running some timings at the bleeding edge of stability when it doesn't really increase performance much?
> 
> 
> https://www.hardwareluxx.de/communi...fluss-auf-spiele-und-anwendungen-amd.1269156/



Seems to match what I've found overclocking RAM.


----------



## KedarWolf

Yes, but we do it because we CAN.

We are on OVERCLOCK.net.


----------



## fingon82

What voltage, 1.45v? ^^^

Do 15-20 circles


----------



## KedarWolf

fingon82 said:


> What voltage, 1.45v? ^^^
> 
> Do 15-20 circles


I have the Anta Extreme preset as well, does 20 loops, but I'm waiting until I go to bed tonight, takes like almost 3 hours to run or something. 

Edit: 1.5v on b-die, I'll post my BIOS settings, got it really dialled down for an extreme RAM overclock.

See Spoiler for BIOS settings. 



Spoiler


----------



## gerardfraser

New AIDA64 dropped so I thought I would do stress test CPU/FPU/Cache/Memory.Yeah I was bored,test was for DDR4 3600Mhz @ 1.23v.
Ran this in April for week for stability and worked great

DDR4-3600Mhz @ 1.23v with max temperature of 27°C
MB-max temperature of 26°C
MB Chip-max temperature of 31°C
MB VRM-max temperature of 48°C
CPU Clock- 4325Mhz-4425Mhz @ 1.368v with max temperature of 71°C


----------



## Veii

hazium233 said:


> What are decent settings for using y-cruncher stress test? I have only briefly played with it, one thing I thought was annoying was that "time per test" seemed to apply only to iterations or something, but the tests themselves were running more iterations than I expected.


Just test everything 
All of the tests use different instruction sets and so applied current voltage will differ
You want to run stresstest mode and select all tests 
Time to pass, are results times ~ usually it takes 2-3min each test for about 8 tests
Passing two times the whole set of tests is usually enough, but likely we can optimize that in the future better

First 3 tests will always fail if there is an issue with fabric clock 
Some ryzen chips fail that on stock, but usually non should fail this


----------



## fingon82

@KedarWolf

Did you try to lower TRP further?

I'm really impressed with that TRFC. How low can you take it on 1.45v if you tested that?


----------



## rares495

fingon82 said:


> @*KedarWolf*
> 
> Did you try to lower TRP further?
> 
> I'm really impressed with that TRFC. How low can you take it on 1.45v if you tested that?



He can't go lower than 11 because he would need too low tRAS and tRC. His kit cannot do that. His tRP limit is probably 12 stable.


----------



## Veii

fingon82 said:


> @KedarWolf
> Did you try to lower TRP further?
> I'm really impressed with that TRFC. How low can you take it on 1.45v if you tested that?
> 
> 
> rares495 said:
> 
> 
> 
> He can't go lower than 11 because he would need too low tRAS and tRC. His kit cannot do that. His tRP limit is probably 12 stable.
Click to expand...

Yes, this tRFC was not possible he got errors - not even with factoring in tSTAG to lower it, it was far to low and needs tRFC 40 at least
or minimum 42, 44 was far too high for it ~ 240 works on lower timings but not on this set

tRFC 240 would be 126.3157895ns with tRC 40
It would make more sense to use something like this set:








Where 140ns update time is less harsh to the chips, than going <130ns update cycle
EDIT:
You can optionally use that for 32gb Dimms, or also go even further down to tRAS 26 
- but tBL 4 won't work with this set, it's based on tBL 2
You will need to go tWR 10 for that in order to get tRAS formular right
And in order to go tWR 10, it needs to be tRAS-tRCD which works only with tRCD RD 6 + tCL 12
tRCD RD 8, WR 14 results in 12 average 
26 tRAS - 12 tRCD = 12 tWR not 10 tWR
and tRRD_S+tWTR_S = 8 tWR not 10 
It's complicated  
If you push tWTR_S/L as 6-6 , this formula might work to run tRAS 26 
Else we need bios-mods allowing to use tWR 8 :ninja:


----------



## hazium233

Veii said:


> Just test everything
> All of the tests use different instruction sets and so applied current voltage will differ
> You want to run stresstest mode and select all tests
> Time to pass, are results times ~ usually it takes 2-3min each test for about 8 tests
> Passing two times the whole set of tests is usually enough, but likely we can optimize that in the future better
> 
> First 3 tests will always fail if there is an issue with fabric clock
> Some ryzen chips fail that on stock, but usually non should fail this


Another dumb question then. Does this ever stop by itself? Or is there a hotkey? It seemed like it was just going to run iterations forever when I tried it a bit.


----------



## Veii

hazium233 said:


> Another dumb question then. Does this ever stop by itself? Or is there a hotkey? It seemed like it was just going to run iterations forever when I tried it a bit.


It behaves very similar to LinpackXtreme
It will loop forever 
A stresstest after all 
The benchmark, will end after all tests are done - but it's considerable to loop it twice at least


----------



## Keith Myers

hazium233 said:


> Another dumb question then. Does this ever stop by itself? Or is there a hotkey? It seemed like it was just going to run iterations forever when I tried it a bit.


In the configuration setup there is a toggle for "stop on error" But if no errors found, it will loop continuously until you stop it.


----------



## 2600ryzen

Is there anything I can do to help make 2t stable? When I try disabling GDM and running 2t it usually wont post or if it does it will just freeze up in bios or trying to boot to windows. I don't think there's an inter CCX latency penalty on Zen2 from running 2t due to the different memory controller configuration now on the SOC, can't test though because I can't get it to run properly.


----------



## Notbn

Does anyone have a link or a quide on the general rules on how to sync all the necessary timings? I understand the main timings, as well as tRC = (tRP+tRAS) but what about everything else? Is there a rule of thumb I should be following?


I'm trying to get 3800CL16 @1.45V perfectly stable on my system. Its a 4400CL19 Patriot Viper Steel Kit, but I keep getting an error on Karhu about an hour in.

I'm not interested in dropping main timings any lower, I know buildzoid can get CL12 on his kit but I don't exactly want to pump like 1.5+ volts into the kit. Here's where I'm at:


----------



## Hale59

Notbn said:


> ...I know buildzoid can get CL12 on his kit but I don't exactly want to pump like 1.5+ volts into the kit.


CL12 on INTEL.


----------



## Notbn

Hale59 said:


> CL12 on INTEL.



Haha yeah I had it wrong, it was CL14. Impressive, but not what I want.


----------



## nick name

Notbn said:


> Does anyone have a link or a quide on the general rules on how to sync all the necessary timings? I understand the main timings, as well as tRC = (tRP+tRAS) but what about everything else? Is there a rule of thumb I should be following?
> 
> 
> I'm trying to get 3800CL16 @1.45V perfectly stable on my system. Its a 4400CL19 Patriot Viper Steel Kit, but I keep getting an error on Karhu about an hour in.
> 
> I'm not interested in dropping main timings any lower, I know buildzoid can get CL12 on his kit but I don't exactly want to pump like 1.5+ volts into the kit. Here's where I'm at:


These are my CL16 "takin' it easy" timings. Though I don't know what voltage you're gonna find yourself at for them. I also leave tRDWR and tWRRD on Auto as the board sets each channel a little different.

Edit:

Sorry, it didn't attach the first time. I've also tested voltages briefly and 1.45V doesn't run stable, but it also droops down to 1.42V according to HWiNFO. However, 1.47V ran error free for 35 minutes in Karhu.


----------



## 2600ryzen

Notbn said:


> Does anyone have a link or a quide on the general rules on how to sync all the necessary timings? I understand the main timings, as well as tRC = (tRP+tRAS) but what about everything else? Is there a rule of thumb I should be following?
> 
> 
> I'm trying to get 3800CL16 @1.45V perfectly stable on my system. Its a 4400CL19 Patriot Viper Steel Kit, but I keep getting an error on Karhu about an hour in.
> 
> I'm not interested in dropping main timings any lower, I know buildzoid can get CL12 on his kit but I don't exactly want to pump like 1.5+ volts into the kit. Here's where I'm at:



Try Twr = 16 and Trfc = 304. Then Trfc/Trtp/Twr will all be synced up.


----------



## rastaviper

Notbn said:


> Haha yeah I had it wrong, it was CL14. Impressive, but not what I want.


You don't want to get lower timings (get better performance) or can't?

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Notbn

2600ryzen said:


> Try Twr = 16 and Trfc = 304. Then Trfc/Trtp/Twr will all be synced up.



Did this and it passed 4 hours of Karhu. Pretty happy with that.


----------



## Notbn

rastaviper said:


> You don't want to get lower timings (get better performance) or can't?
> 
> Sent from my ONEPLUS A6003 using Tapatalk



Just couldn't be arsed to fiddle around with CL14 and have to run the ram at the ragged edge of stability. I don't sit around and run benchmarks all day, I would rather just be conservative than worry about the extra 3-5 FPS while gaming. 



This is the 24/7 stability thread after all!


----------



## SpecChum

Evening all, I did post this to my own thread on the memory subforum, as I didn't realise this one was here 

I did great some great help there, but I figured since this is Ryzen only thread it may got some more exposure.

Below are my settings, straight from DRAM Calc, but they get me over 73ns, and I'm aiming, ideally, for 72ns, as I think this removes some bottleneck system wide?

I can't do 1T without GDM, it doesn't crash, but I get memtest errors within minutes; 3333 doesn't work at all, pretty much instant BSOD once in Windows.

Ryzen 1700 on a C6H.

Thanks 

NINJA EDIT FOR A QUICK FOLLOWUP: What values does GDM change? Is it all odd values, or just certain ones? I've been googling and seen some say it's all, and some says it's only "tCL, tWR, tCWL and tRTP"

If it's all, most of my primaries there aren't doing anything above the default 14-14-14?

EDIT: I've just noticed those timings are wrong, so I've updated image again. I've noticed RTC 1.05 do that a few times.


----------



## 2600ryzen

Notbn said:


> Did this and it passed 4 hours of Karhu. Pretty happy with that.



You could probably test with lower Trfc if you wanted, reduce it by 16 at a time to find the safe min. Trfc is the most important timing I think.


----------



## SpecChum

Left HCI Memtest running over night, with a little trepidation it must be said lol

Passed, almost 2000%, so I'm happy with that.

Still over 73ns latency on Aida64 tho, but I do notice the results fluctuate somewhat, even when I close down everything I can think of. Yesterday, I did have 1 result bang on 72ns, but I can't seem to repeat it, they're all 73 usually.


----------



## aepseidhe

Just looked at some results here, and just realized that the AIDA's read/write result of my 4x8GB ripjaws (originally [email protected] bdie) are kinda great (with non-oc 3900x on MSI MEG ACE x570)

OC is kinda small [email protected] with 1.37v (set 1.35v) + 1.05 SOC


----------



## Veii

SpecChum said:


> NINJA EDIT FOR A QUICK FOLLOWUP: What values does GDM change? Is it all odd values, or just certain ones? I've been googling and seen some say it's all, and some says it's only "tCL, tWR, tCWL and tRTP"
> 
> If it's all, most of my primaries there aren't doing anything above the default 14-14-14?
> 
> EDIT: I've just noticed those timings are wrong, so I've updated image again. I've noticed RTC 1.05 do that a few times.


First 5 for sure, tRTP should be factored in, same as tWR
tRRD_ & tWTR_ ones are bank dependent values - unsure if the time on these change
tRFC is not affected as tRFC triggers a forced refresh inside the tREFI delay range
This should mention everything that is needed
























Accurate tRFC,tRFC2 & 4 will calculate accurate tREFI - but that modifier is mostly an intel thing
tRFC does force a refresh cycle when the memory is idle - which is what tCKE flag on 1 does
(put memory state back to idle without suspension)
Because of this i always suggest to keep a clean sync at the start, else transitions would "wait-for-action" own added delay
SCL, tRDWR/WRRD, SD & DD stuff are mostly signal "cutters" , same for RRD_ & tWTR_ 
Although tWRT_ i'm still conflicted, as it's write time recovery and not an "keep active for X amount and cut" time like tRRD_
There would be no reason to round up the mentioned ones, but tWTR_could get some roundup 

overall with GDM on, you slow down internal IOs speed
While on 2T you introduce another cycle in the MUX layer, which operates still at twice the speed of the IO unit on the memory
Soo 2T is still better than GDM on, being forced to use GDM means something/somewhere pushes too high of a stress on the IO controller of the dimm
Which can translate to, insufficient impedance - or not enough voltage for it to run at this pushed frequency
Usually it's not needed to keep it enabled 


Spoiler


----------



## SpecChum

Awesome, thanks.

I've not even tried benching 2T as I naively believed the (mainly reddit) posts saying GDM was worse than 1T but better than 2T - that'll teach me.

I'll try 2T later.

Also, as I've mentioned before, 1T GDM off isn't a million miles away, it boots fine, and I can use Windows as normal, but it errors on memtest in under 5 minutes.

Would you suggest playing with the CAD_BUS and SoC voltage a little? I'm currently on 24-24-24-24 and 1.025v, respectively.


----------



## Veii

SpecChum said:


> Awesome, thanks.
> 
> I've not even tried benching 2T as I naively believed the (mainly reddit) posts saying GDM was worse than 1T but better than 2T - that'll teach me.
> 
> I'll try 2T later.
> 
> Also, as I've mentioned before, 1T GDM off isn't a million miles away, it boots fine, and I can use Windows as normal, but it errors on memtest in under 5 minutes.
> 
> Would you suggest playing with the CAD_BUS and SoC voltage a little? I'm currently on 20-20-20-20 and 1.025v, respectively.


They are not wrong, GDM which is known as 1.5T is faster on it's core
but because of the roundup and added latency , it's worse than 2T 
At least it helps using far lower timings and makes calculation easier 
But you lose accuracy, and you need accuracy to tigger a cycle stacking method - which goes beyond JEDEC specs
I can link you to this two links to easier learn how DRAM operates:
https://www.systemverilog.io/ddr4-basics
https://www.synopsys.com/designware-ip/technical-bulletin/ddr4-bank-groups.html
and this is a more technical explanation for later on 

procODT changes always up to bios and changes also up to used vDIMM to what i personally noticed
same as CAD_BUS resistance change up to voltage
Start with 24-20-20-24 and push 24-24-24-24 if you really need to, because you use high vSOC for example
1003ABBA and on the old 1006 bios with a patch = 0072 agesa, 24-20-20-24 worked very well for me
You can get some setting examples from here the Zen sheet
Although it only has the old timings and old result - newer 3467 ones should lead to even better results


----------



## hazium233

Veii said:


> First 5 for sure, tRTP should be factored in, same as tWR
> tRRD_ & tWTR_ ones are bank dependent values - unsure if the time on these change
> tRFC is not affected as tRFC triggers a forced refresh inside the tREFI delay range


Are the banks not sync'd to the same clock edges when GDM is initialized? That seems like it should be the only way that odd timings for bank to bank timings might work, unless I am missing something about GDM. Which is plausible, since this is a hobby not a career for me, heh



> Because of this i always suggest to keep a clean sync at the start, else transitions would "wait-for-action" own added delay
> SCL, tRDWR/WRRD, SD & DD stuff are mostly signal "cutters" , same for RRD_ & tWTR_
> Although tWRT_ i'm still conflicted, as it's write time recovery and not an "keep active for X amount and cut" time like tRRD_
> There would be no reason to round up the mentioned ones, but tWTR_could get some roundup


Had been meaning to ask this somewhere about the RDRD_, WRWR_, RDWR, WRRD timings. I am not sure I saw a satisfying explanation of how these timings are exactly used. And specifically whether something like tRDRDSCL is actually an offset rather than a real timing. Like if those are offset from CCDL. Or does it get changed on the fly? The reason for asking this is the "minimum" tRDRDSCL at 2t seems like it should be too low to work for back to back reads.

Have read the reddit Demystifying Ryzen Ram post a long time ago, specifics were a bit light there.

**

Actually have a few questions about syncing the timings, tried to get an idea about the math but the questions may end up going all the way down to basic why this or that?  Idea is largely manipulation of non-available parameters, correct?


----------



## Veii

hazium233 said:


> Are the banks not sync'd to the same clock edges when GDM is initialized? That seems like it should be the only way that odd timings for bank to bank timings might work, unless I am missing something about GDM. Which is plausible, since this is a hobby not a career for me, heh
> 
> 
> 
> Had been meaning to ask this somewhere about the RDRD_, WRWR_, RDWR, WRRD timings. I am not sure I saw a satisfying explanation of how these timings are exactly used. And specifically whether something like tRDRDSCL is actually an offset rather than a real timing. Like if those are offset from CCDL. Or does it get changed on the fly? The reason for asking this is the "minimum" tRDRDSCL at 2t seems like it should be too low to work for back to back reads.
> 
> Have read the reddit Demystifying Ryzen Ram post a long time ago, specifics were a bit light there
> 
> Actually have a few questions about syncing the timings, tried to get an idea about the math but the questions may end up going all the way down to basic why this or that?  Idea is largely manipulation of non-available parameters, correct?


Can only forward you guys to this guide 
https://www.systemverilog.io/understanding-ddr4-timing-parameters
tRRD_ & tCCD_ are cutting timings
tFAW pushes an row ACTIVATE command , both of these control the cutting of the time soo cells can recharge


> The ACTIVATE command is used to open a row within a bank. In Understanding the Basics we saw that every bank has a set of sense amps, so one row can remain active per bank


tRRD_ would at best connect with tRP 


> Four Activate Window or sometimes also called Fifth Activate Window is a timing restriction. tFAW specifies a window within which only four activate commands can be issued. So, you can issue ACTIVATE commands back-to-back with tRRD_S between them, but once you have completed 4 activates you cannot issue another one until the tFAW window expires.


tRP meaning:


> Precharge time. The banks have to be precharged and idle for tRP before a REFRESH command can be applied


On DDR3 you have a prefetcher of 8 where rows are precharged and accessed at the same time per row , 8 at a time
With a bank group can you access them faster, recharge faster and have them ready faster - soo technically 2 operations at the same time
A read command does wipe the cells charge and needs to be recharged before another read command can be issued
This tiny notes-taking of mine, should explain it to you 


Spoiler















soo while tFAW timing activates the row for master set X amount
tRRD_ read -> precharge -> write back , commands whole commands
It checks @ at this current time the row is in side the same bank group or not
_S one does jump the 2nd bank-group for a row-to-row operation, a back-to-back operation
_L is used if the transfer operation is inside the same bankgroup 

tFAW only allows 4x tRRD_S to pass, before pulling a "Time Break" and switch to wait-for-action mode, till tFAW ACTIVATE window elapsed

This post will be double the size of the DDR4-Basics post, which is already huge
Please read it to understand command behavior 
tasks like tREFI main range to tRFC refresh range , happen in the hidden 
Same as tBL (prefetcher and bank groups) and the tAL command (Additive Latency = board added latency)
tCCD_ stuff works in the hidden together with tRRD_ , mostly taken into consideration while loading the xmp profile 
It's there since a loong time, but never assigned as visible or readable value inside the bios 
It's just there and does it's work in the hidden
tCCD belongs to the READ commands, while tRRD_ is a cut through command , it's not a delay like tFAW
It's job is to do transfer sparks and should not be affected by GDM
as GDM belongs to the mux layer and not to the main commands 
Soo i'm still on a conflicting topic with tWTR_ , and a bit with tRRD_ as this is no fixed delay to be rounded but a cut command

SD DD ones are delays yes
same as tWRRD and tRDWR are actually delays funnily 
Although tWRRD does work as 3 even with GDM enabled, soo it seems to be separated away from it
In this case, tFAW has identical behavior and should be a different activate timing, away from GDM :thinking:
Anyways, my unit is ready for pickung ~ i'll experiment tomorrow more on it
Memory is always a bit special , tCCD_ and tWTR_ i haven't found a direct connection, if they are renamed or not :thinking:
as tCCD is in the READ command section, and tWTR_ should come after a write
tRRD_ like tFAW and tRFC are ACTIVATE = clock counters, they should not be influenced at all by GDM


----------



## hazium233

Veii said:


> Can only forward you guys to this guide
> https://www.systemverilog.io/understanding-ddr4-timing-parameters
> tRRD_ & tCCD_ are cutting timings
> tFAW pushes an row ACTIVATE command , both of these control the cutting of the time soo cells can recharge
> 
> tRRD_ would at best connect with tRP
> 
> tRP meaning:


Yes, I read that site before.

I know RRDS/L and tFAW. Limit activates in proximity to control current since row activation is energy intensive. 

The ones that don't get are Read-Write (tRDWR), Write-Read (tWRRD), and the tRDRDSCL / tWRWRSCL. These are spacing reads and writes in some way, so they must be related to column-column delay, no?

The problem is these don't exist in the timing diagrams like in the JEDEC document like most of the other ones.



> On DDR3 you have a prefetcher of 8 where rows are precharged and accessed at the same time per row , 8 at a time
> With a bank group can you access them faster, recharge faster and have them ready faster - soo technically 2 operations at the same time
> A read command does wipe the cells charge and needs to be recharged before another read command can be issued
> This tiny notes-taking of mine, should explain it to you
> 
> 
> Spoiler


It was my understanding that the read that is destructive is the read of the page from array into the sense amplifier, but once the page is in the sense amplifiers (row buffer) you can read or write as much as needed, within reason. Have not seen the limit, but I would assume it is like maximum row time, assumed it to be 9xtREFI.

I have only ever read that precharge is necessary when closing the page, because the data is in the sense amp / row buffer and needs to go into the capacitors in the array. Or rather I thought it was only one of the complementary bitlines that is drained, the other used for comparison. But regardless, the idea being closing the page is precharge and applying the appropriate charge to the capacitors.



> soo while tFAW timing activates the row for master set X amount
> tRRD_ read -> precharge -> write back , commands whole commands
> It checks @ at this current time the row is in side the same bank group or not
> _S one does jump the 2nd bank-group for a row-to-row operation, a back-to-back operation
> _L is used if the transfer operation is inside the same bankgroup
> 
> tFAW only allows 4x tRRD_S to pass, before pulling a "Time Break" and switch to wait-for-action mode, till tFAW ACTIVATE window elapsed


Yeah, and given relatively normal parameters, same bank activations at tRRDL are ultimately limited by tRC.



> tCCD_ stuff works in the hidden together with tRRD_ , mostly taken into consideration while loading the xmp profile
> It's there since a loong time, but never assigned as visible or readable value inside the bios
> It's just there and does it's work in the hidden
> tCCD belongs to the READ commands, while tRRD_ is a cut through command , it's not a delay like tFAW
> It's job is to do transfer sparks and should not be affected by GDM
> as GDM belongs to the mux layer and not to the main commands
> Soo i'm still on a conflicting topic with tWTR_ , and a bit with tRRD_ as this is no fixed delay to be rounded but a cut command


Are we still talking about tRRD_ (RAS to RAS) here or tRDRD_ (Read Read)? 

I don't really understand the mux layers outside of very generally with the prefetch number, but all of the small amount of info on GDM is that command and address lines reduced to 1/4 rate (that is 1/2 frequency), and at initialization, the clock edge is synced to CK_t/CK_c crossings. Since those are now half the frequency of the clock, they should only ever line up with every other clock from that point on, hence the even timings. 

How often does it go into the gear sync? Is this only at startup?

As an aside, tRTP and tWR share the same address bits in MR0, so if auto-precharge is used by Ryzen, then I have wondered how it sets this if manually set timings do not obey tRTP = 1/2*tWR, as that is the way the logic for the shared address works.



> SD DD ones are delays yes
> same as tWRRD and tRDWR are actually delays funnily
> Although tWRRD does work as 3 even with GDM enabled, soo it seems to be separated away from it
> In this case, tFAW has identical behavior and should be a different activate timing, away from GDM :thinking:
> Anyways, my unit is ready for pickung ~ i'll experiment tomorrow more on it
> Memory is always a bit special , tCCD_ and tWTR_ i haven't found a direct connection, if they are renamed or not :thinking:
> as tCCD is in the READ command section, and tWTR_ should come after a write
> tRRD_ like tFAW and tRFC are ACTIVATE = clock counters, they should not be influenced at all by GDM


I have not seen or run the test, but does tWRRD 3t with GDM on actually bench better than 4t? I have it usually set this way but never bothered to test. 

But that timing still seems weird to me. Why is there a tWRRD if there is the "normal" DDR tWTRS/L? The latter is explained in some places. Simply as a way to make sure the write has gone through the I/O and that the write driver has had time to overdrive the sense amp (latter for tWR too).


----------



## Lobstar

Hey there, I would love some feedback on where you guys think I can improve my RAM OC. I'm really happy with the current setup but I feel like if I knew more I could get more out of it.


----------



## KedarWolf

I'm having an issue on my 3950x. I'm now getting errors in TM5 I never got with the same settings. Only changes to my PC are two video cards now, not one, and a much better power supply that meets Platinum certification standards.

I checked the voltages in HWInfo, they look stable and fine, so I'm going to try taking out the second video card and retest everything.

Do you think video cards in SLI can cause system instability?

I have determined without a RAM fan my RAM is getting too hot, around 50C. This with cool ambient temps and the RAM RGB turned off. I ordered a RAM cooling fan, I know it really helps, I broke a wire on my old one.

And yes, if you're getting close to 50C or higher b-die will throw errors.


----------



## klaren

@Veii I thought that GDM only affects command rate, check "Figure 59 — Comparison Timing Diagram Between Geardown Disable and Enable." from the spec. Basically you can only issue commands every other clock cycle so it will affect every timing between commands.


----------



## SpecChum

Well, tried 2T, and that isn't stable either, seems I can only use 3200+ with GDM on, HOWEVER, I managed to boot 3400 with GDM, yay, and it's stable for about half an hour with timings below, but then I get a test error.

Anything obvious to change that might be causing the error? Values are direct from DRAM calc for 3400 fast with no changes.

1.4v on DRAM, and I've tried various SoC voltages from 1.05 to 1.09, still errors after about half an hour - time consuming this testing lark 

I am fully watercooled, so my only intakes are through a radiator, so my in-case airflow isn't great, and RAM gets to just shy of 49c, so could be that? Doesn't seem that hot tho.

Quick edit: It's interesting that both 1T and 2T are the same, they both boot fine, and windows seems fine, but any memtest errors in under 5 minutes, usually under 2.


----------



## rares495

Lobstar said:


> Hey there, I would love some feedback on where you guys think I can improve my RAM OC. I'm really happy with the current setup but I feel like if I knew more I could get more out of it.


Highly doubt that those settings would pass Karhu with cache or TM5 1usmus v3 20 cycles. They are really out of sync. Plus the procODT 60 ohms is waaaaaay too high for B-die.

Can you post a screenshot of thaiphoon burner please?


----------



## Lobstar

rares495 said:


> Highly doubt that those settings would pass Karhu with cache or TM5 1usmus v3 20 cycles. They are really out of sync. Plus the procODT 60 ohms is waaaaaay too high for B-die.
> 
> Can you post a screenshot of thaiphoon burner please?


I don't doubt you in the least. First, thanks for taking a peek. I don't expect anything but I'd be greatly appreciative of a once over. Further, happy to provide any testing I can get away with. That said, here's the requested info.


----------



## rares495

Lobstar said:


> I don't doubt you in the least. First, thanks for taking a peek. I don't expect anything but I'd be greatly appreciative of a once over. Further, happy to provide any testing I can get away with. That said, here's the requested info.



Yeah, the 4400 Viper Steels should not go that low due to their A2 PCB. I don't know the actual timing limitations but that's at least the theory. @Veii can tell you more about it.


----------



## 2600ryzen

It took 1.5v and had to reduce Trdrd/wrwr_scl to 6 killing bandwidth, but I finally got under 70ns aida64 memory latency. Reasonable for my budget micron rev a kit. 

I get bandwidth over 51gb/s with the scl's at 5 with cl18 and about 47gb/s with my cl16/scl 6 setting, still cl16 feels much faster and has nearly 2ns less latency.


----------



## KedarWolf

KedarWolf said:


> I'm having an issue on my 3950x. I'm now getting errors in TM5 I never got with the same settings. Only changes to my PC are two video cards now, not one, and a much better power supply that meets Platinum certification standards.
> 
> I checked the voltages in HWInfo, they look stable and fine, so I'm going to try taking out the second video card and retest everything.
> 
> Do you think video cards in SLI can cause system instability?
> 
> I have determined without a RAM fan my RAM is getting too hot, around 50C. This with cool ambient temps and the RAM RGB turned off. I ordered a RAM cooling fan, I know it really helps, I broke a wire on my old one.
> 
> And yes, if you're getting close to 50C or higher b-die will throw errors.



I removed one 1080 Ti and now no errors on TM5.

I'm trying moving my two Gen 4 M.2's to the bottom two M.2 shots. If I have one in the top slot it uses CPU PCI-e lanes, not chipset lanes. 

Running TM5 while I'm at work.


----------



## SpecChum

Might have a go at getting 3200MHz working with GDM off today.

If you were faced with the issue of neither 1T or 2T working, they boot fine, but TM5 errors in minutes regardless if I choose 1 or 2T, what would you look at first?

2T even fails when I just do DOCP primaries, and everything else auto.

However, turning on GDM on makes it work perfect, even at tighter timings, albeit some are rounded up, but they're still a lot tighter than the DOCP auto timings.

I'm not 100% if GDM helps the IMC or the RAM, or both?


----------



## hazium233

@SpecChum - have seen some people who tested multiple cpu samples say that some just didn't want to run GDM off at some speeds, so I would assume it is both.

**

Got sidetracked last time, but originally I wanted to ask about some of the math for syncing timings, for something like a finicky or uncommon IC. I am using 2x8GB Micron 8Gb Rev D, original timings are 16-18-18-38 2666MT/s 1.2V*.

Was working at 3466MT/s with them. At 3200MT/s, they seemed like they could only manage 18t tRCDRD after a bit of effort at reasonable voltage, and at 3466MT/s it looks like it is going to be 20t. Can set tCL and tRP to 16t. Best tRFC I bothered to test was 225ns (360t at 3200MT/s). The thing about these is that despite tCL or tRP, I am not sure tRC can really be very aggressive.

So if I try to work out with factors, I can end up with something sort of like this:

16-20/18-16-36-64

tRFC 384 (~221ns... 221.5810733)

tRTP / tWR - 8 / 16

tRFC is tRC*6, tRTP*48, tWR*24

tRDWR / tWRRD - 8 / 3 (or 4...)

8 = tRCDWR / 2 - 1

In post I saw tWRRD * tRDRDSCL <= tRCDRD (but didn't follow exactly how close it should be)

In which case, is 4t (4*4=16) supposed to work? Will 3t plausibly work (also ties into earlier GDM unknown, if rounded up to even... 3 passes testing with high tRFC).

I already know 2 here is too low, that was interestingly the auto value. Using 6t on SCL gets a lot closer to the tRCDRD, but 6t on SCL is a good deal slower on bandwidth.

-

One thing, I know @Veii recommended whole nanosecond values, but I had trouble finding them for this frequency, at least at numbers that actually allowed timings to be multiples of one another. This changes with frequency or rate value used.

Additionally, going back to relationship between tRC and tRFC, I saw using the 1/2*tCL as the multiplier, or 1/2*tCL - 1... have been using more like tRC*6 (which is 1/2*tCL-2 here).

*These are two individual sticks, and I think sadly they might be a bit different electrically. Such that the one seems to require a bit more voltage to run the same thing than the other stick in brief testing.


----------



## grinch66

Hello everyone.
These are my timings for 2x 8GB Crucial Tactical Tracer Micron E-Die. 
VSOC 1.1V, DRAM 1.4V, VDDG 0.950V, VDDP 0.900V


What do you think of that? Did I follow all the rules? Which timings could I still try to change?
Thanks for your help.


----------



## rares495

grinch66 said:


> Hello everyone.
> These are my timings for 2x 8GB Crucial Tactical Tracer Micron E-Die.
> VSOC 1.1V, DRAM 1.4V, VDDG 0.950V, VDDP 0.900V
> 
> 
> What do you think of that? Did I follow all the rules? Which timings could I still try to change?
> Thanks for your help.



tRRDL 5, tRTP 8, tCWL 16, tRDWR 8/9.


----------



## 2600ryzen

grinch66 said:


> Hello everyone.
> These are my timings for 2x 8GB Crucial Tactical Tracer Micron E-Die.
> VSOC 1.1V, DRAM 1.4V, VDDG 0.950V, VDDP 0.900V
> 
> 
> What do you think of that? Did I follow all the rules? Which timings could I still try to change?
> Thanks for your help.



I agree with rares except if Trtp-Twr is stable at 6-12 I say keep it that way and put Trfc to 528 if you can otherwise 540.


----------



## grinch66

rares495 said:


> tRRDL 5, tRTP 8, tCWL 16, tRDWR 8/9.





2600ryzen said:


> I agree with rares except if Trtp-Twr is stable at 6-12 I say keep it that way and put Trfc to 528 if you can otherwise 540.


Thanks for your advice.
Looks stable. 
Any other suggestions?


----------



## SpecChum

hazium233 said:


> @SpecChum - have seen some people who tested multiple cpu samples say that some just didn't want to run GDM off at some speeds, so I would assume it is both.


That could be what it is to be fair, doesn't seem to matter what timings I put or 1T or 2T, TM5 fails after a couple of minutes - although it's not like I've tested every timing possible, they've all started with 14-14-14-14


----------



## Joseph Mills

Quick question about terminology:
Sometimes when I turn my computer on, it will shut itself off, then back on, then boot normally. This usually happens when it's been off over night (doesn't do it every time it's been off for a while). My memory overclock is always stable when it gets back into windows. Is this considered a cold boot issue?


----------



## hazium233

I actually had tRCDWR at 16t and tRAS at 38t from previous tests and didn't think to change it, but tested the tRFC at 384 last night with some AIDA and then just let Karhu run overnight.

These are Micron 8Gb D 2666 1.2V sticks. These sticks were individually packaged, I think they are a bit dissimilar electrically (tried to test this a week or so ago). But I suppose if I was motivated, I need to retest some of the timings with more voltage and this tRFC.

Previously I could get some settings to run at 1.410V, but step up or down killed it in AIDA immediately, and those settings had worse subs except for tFAW.

***

These are on A2 PCB from what I understand, despite what thaiphoon shows *actually I am not sure, really the spacing should be like A1. I had thought maybe getting two more for the hell of it might be interesting, but then saw mention that 4 x A2 is harder to stabilize on T-topo potentially than 2 x dual rank?

Really though, people seem to want too much for these sticks given the cost of other things. Have considered getting either some Rev E, CJR, or more recently just getting B-die in a decent 3600 or the 4000+ bins.


----------



## Cosminnn

nick name said:


> I'm still amazed that you can run your tRCDRD the same as tCL and only get one error so it makes trying to trying to help you a bit of a guessing game.
> 
> What is your SOC and DRAM voltage? I have to run 1.52V on DRAM to get 1.5V after droop and 1.106V on SOC to get 1.1V after droop and that cured my 1 error problem. Perhaps you're similar?


Here are my settings, voltage settings.


----------



## paih85

*#wtshare*

cpu: 3700x (auto no oc)
dram: 1.45v (max limit for myself)
vsoc: 1.025v
vddp: 900mV
vddg: 975mV

i can do 3800c16 fully stable in test and gaming but random microstutter + sound crackling annoyed me.


----------



## 2600ryzen

sound crackling can be from not enough SOC voltage.


----------



## paih85

2600ryzen said:


> sound crackling can be from not enough SOC voltage.


that time already 1.1v. need up more?


----------



## rares495

paih85 said:


> that time already 1.1v. need up more?


No. You can try to increase VDDG a bit but keep a ratio between soc, VDDG, VDDP like:

1.1V soc

1V VDDG

900mV VDDP


----------



## paih85

rares495 said:


> No. You can try to increase VDDG a bit but keep a ratio between soc, VDDG, VDDP like:
> 
> 1.1V soc
> 
> 1V VDDG
> 
> 900mV VDDP


ok noted. will try. thanks


----------



## grinch66

These are my current stable settings.
Any other suggestions for improvement or correction?
Are there really reasonable rules for TRAS and TRC?


----------



## 1usmus

*DRAM Calculator for Ryzen 1.7.1
*










* New presets adapted to latest AGESA 
* DRAM PCB revision - presets became more "flexible"
* New features (overclocking assist) and etc.
* Reading timings for all Ryzen's (even Zen3)

*Guide (DE)* >> https://www.computerbase.de/2020-05/dram-calculator-for-ryzen-1.7.1/
*Guide (EN)* >> https://wccftech.com/dram-calculator-for-ryzen-1-7-1-download/

*Download:*

Techpowerup link
Guru3d link
WCCFTECH link
Сomputerbase.de link
Techspot link


----------



## Hale59

Deleted


----------



## Chobbit

Hi guys, a friend has built a Ryzen 5 3600 / Auros B450 Pro build with 16GB Vengence pro 3200: https://www.corsair.com/uk/en/Catego...tab-tech-specs

Now he only built it two days ago and he's not an overclocker but he's turned on the XMP as you would expect to get the quoted clocks/timings but it's randomly Blue screening (gaming, watching streams & once when his desktop started) but the BSOD message is always 'stop code memory management'. Obviously social distancing means I can't just go around and help.

I suspect it's incorrect voltages with XMP and leaving everything else on Auto, so I've told him to turn the XMP off and we'll try setting the values manually:

Latency16-18-18-36
Voltage1.35V
Speed3200MHz

However what should the vccio and vccsa voltages be for this setup? so we can make sure it's definetly getting the correct power across the board.


Cheers


----------



## rares495

Chobbit said:


> vccio and vccsa voltages


----------



## Chobbit

rares495 said:


>


Oh? so is it only the single DRAM voltage that affects RAM on AMD?


----------



## rares495

Chobbit said:


> Oh? so is it only the single DRAM voltage that affects RAM on AMD?



Those are intel voltages.


On the superior AMD platform we use: Vsoc. VDDG, VDDP


Your friend can try 1.45V VDIMM, 1.05V soc, 0.950V VDDG, 0.900V VDDP


----------



## Chobbit

rares495 said:


> Those are intel voltages.
> 
> 
> On the superior AMD platform we use: Vsoc. VDDG, VDDP
> 
> 
> Your friend can try 1.45V VDIMM, 1.05V soc, 0.950V VDDG, 0.900V VDDP



Thanks, sorry I'm not going to lie I've used intel for mobo/CPUs mostly in the last 10 years (used AMD for GPU's and have a 5700XT currently. So never overclocked on an AMD board and only used to Intel, don't get me wrong AMD have been impressing me more and more though.


----------



## MyUsername

Did a bit of tinkering today, copy bench looks a bit dodgy but I like it. I don't know what else to tweak.


----------



## GoldCartGamer

Posted in DRAM Calc thread, but wasn't sure if this belonged in here instead.

I've run a few tests since building this PC last year and been happy with my performance, but wonder if there are tools or tests I am missing to further squeeze out performance from my 3900x and RAM timings before I drop in a 3950x and start all over lol. Just found out about ZenTimings and TestMem5 tonight in this thread. First time AMD build and first time really pushing my PC setup. Learned a bit from Buildzoid as well. I have run MemTest previously with zero errors. 


3900x
B-Die 16 GB (2 x 8 GB) 3200 CL14 - TDPGD416G3200HC14ADC01
Running 1usmus Ryzen Universal power plan with suggested settings in bios
Latest bios (F12e - AGESA 1.0.0.4 B) with latest chipset drivers from AMD
Bios settings:
VCORE SOC - 1.2v
DRAM - 1.5v
DRAM Termination - .750v
FCLK - 1900
SOC VID - 48
UCLK MODE - UCLK==MEMCLK
VDDP - 1000
VDDG - 1050
PBO enabled 4x scaler
PPT - 300
TDC - 230
EDC - 230


----------



## glnn_23

Here's my latest effort with my C8H , 3900x and 2x8Gb. Trying to lower latency a little.
Vdimm 1.455v in bios.


----------



## rares495

glnn_23 said:


> Here's my latest effort with my C8H , 3900x and 2x8Gb. Trying to lower latency a little.
> Vdimm 1.455v in bios.


Very nice! You beat my 61.5 ns 

It's amazing how much a manual OC affects latency in Aida64.


----------



## CiiD

Where I am at so far, 1.5V in BIOS. Don't have it clipped, but it is stable 20 rounds with v3 and >10000% w/ Karhu. 
Doing this with 4x8 DIMMS has been a challenge, stability testing takes so long. Tried with 240 RFC and got a crash, but that could have been my tRDWR too tight at the time too, when that happened I backed off the 240 rfc and looked to getting 14-14-14-28-40 working.
Any suggestions where to reduce next? 

(Ignore the [email protected], I don't think that's Prime95 Small FFT stable with a healthy voltage, just using it to quickly compare latencies)


----------



## rares495

CiiD said:


> Where I am at so far, 1.5V in BIOS. Don't have it clipped, but it is stable 20 rounds with v3 and >10000% w/ Karhu.
> Doing this with 4x8 DIMMS has been a challenge, stability testing takes so long. Tried with 240 RFC and got a crash, but that could have been my tRDWR too tight at the time too, when that happened I backed off the 240 rfc and looked to getting 14-14-14-28-40 working.
> Any suggestions where to reduce next?
> 
> (Ignore the [email protected], I don't think that's Prime95 Small FFT stable with a healthy voltage, just using it to quickly compare latencies)



That's one of the best kits on the market. Can you post a screenshot of ryzen master so we can see the voltage and resistance values? Thanks


----------



## CiiD

rares495 said:


> That's one of the best kits on the market. Can you post a screenshot of ryzen master so we can see the voltage and resistance values? Thanks


Some other data. A1 layout per Thaiphoon, 10 layer PCB... unfortunate because DRAM calc 1.7.1 doesn't have settings for that, and the defaults for single rank A0/A2 w/ 4 DIMMs certainly didn't work, nor did inputting my XMP into manual.
I'm okay with keeping it at 1.5V daily, so there might still be some room. 

I haven't been able to get off GDM with 4 DIMMS with these primaries, so mostly looking at secondary tertiary timings. Took me a while but tighter tRDWR/tWRRD were the cause of most of my previous fails at reducing other timings.


----------



## rares495

CiiD said:


> Some other data. A1 layout per Thaiphoon, 10 layer PCB... unfortunate because DRAM calc 1.7.1 doesn't have settings for that, and the defaults for single rank A0/A2 w/ 4 DIMMs certainly didn't work, nor did inputting my XMP into manual.
> I'm okay with keeping it at 1.5V daily, so there might still be some room.
> 
> I haven't been able to get off GDM with 4 DIMMS with these primaries, so mostly looking at secondary tertiary timings. Took me a while but tighter tRDWR/tWRRD were the cause of most of my previous fails at reducing other timings.



Thaiphoon is drunk. Those modules should use A2 PCBs.


----------



## Farih

Could anyone point out to me what readings are the Dram voltage and MEM VTT voltage in HWinfo64.
Dram voltage is set to 1.4V in the BIOS but i cant see it anywhere. (Asus X570 Tuf board)

If I disable auto in Ryzen master it says 1.076V MEM VDDIO and 0.54V MEM VTT, I do see voltages around that in HWinfo64 but I wont believe the RAM is running 3800mhz 16-16-16-16-36 that low lol.


----------



## SpecChum

Farih said:


> Could anyone point out to me what readings are the Dram voltage and MEM VTT voltage in HWinfo64.
> Dram voltage is set to 1.4V in the BIOS but i cant see it anywhere. (Asus X570 Tuf board)
> 
> If I disable auto in Ryzen master it says 1.076V MEM VDDIO and 0.54V MEM VTT, I do see voltages around that in HWinfo64 but I wont believe the RAM is running 3800mhz 16-16-16-16-36 that low lol.


Yours doesn't seem to show it for some reason.

On my C6H it's part of the "ASUS WMI" section, between CPU SOC Voltage and VDDP Voltage.


----------



## Farih

SpecChum said:


> Yours doesn't seem to show it for some reason.
> 
> On my C6H it's part of the "ASUS WMI" section, between CPU SOC Voltage and VDDP Voltage.


Maybe the X570 TUF doesn't have sensors for it?
Kinda strange lol


----------



## CiiD

Yea, just pulled it, definitely A2.


----------



## SpecChum

Farih said:


> Maybe the X570 TUF doesn't have sensors for it?
> Kinda strange lol


There is a new version just out, 6.26, you tried that one?


----------



## Farih

SpecChum said:


> There is a new version just out, 6.26, you tried that one?


Just updated it, same as before


----------



## rares495

CiiD said:


> Yea, just pulled it, definitely A2.



Yup.


----------



## SpecChum

Farih said:


> Just updated it, same as before


Odd. I'm really not sure.

I mean, you do have a fairly new board, but still...


----------



## Cosminnn

Farih said:


> Just updated it, same as before


Check if do not have "hidden" values in HWinfo64.


----------



## SpecChum

Cosminnn said:


> Check if do not have "hidden" values in HWinfo64.


I took that as a given, given how experienced they are.

Please don't let me down here, Farih


----------



## Farih

SpecChum said:


> I took that as a given, given how experienced they are.
> 
> Please don't let me down here, Farih


Cant see anything hidden or disabled 

Edit:
These are all voltages shown in HWmonitor, also no Dram voltages


----------



## rares495

Farih said:


> Cant see anything hidden or disabled
> 
> Edit:
> These are all voltages shown in HWmonitor, also no Dram voltages



Don't use that garbage anymore. Get HWInfo64.


----------



## SpecChum

rares495 said:


> Don't use that garbage anymore. Get HWInfo64.


He is, he's just showing the DRAM voltage doesn't appear in either app. Keep up! lol


----------



## rares495

SpecChum said:


> He is, he's just showing the DRAM voltage doesn't appear in either app. Keep up! lol



My bad lol


----------



## Farih

rares495 said:


> My bad lol


No worries!


----------



## 2600ryzen

I have asus tuf b350 that does show dram voltages either.


----------



## Farih

2600ryzen said:


> I have asus tuf b350 that does show dram voltages either.


Does or doesn't? 


When i enable MEM VDDIO and MEM VTT in Ryzen master it says 1.076V and 0.54V (they have never manually been set before)
They kinda seem to resemble these voltages in HWinfo64. (look at colours)

But no way 3800mhz CL16 can run that low.


----------



## 2600ryzen

Yeah I mean doesn't. My RM shows the same voltages as yours but I've set mine to 1.5v in bios.


----------



## chitos123

Can't reach more than 3200mhz :sadsmiley
Please advise to achieve a higher clock

2400G X470(Daisy chain, 4-layer)
CPU 39x 1.25v 
GPU auto auto
SOC 1.125v
RAM 1.505v


Current HCI 10000% pass setting


----------



## SpecChum

chitos123 said:


> Can't reach more than 3200mhz :sadsmiley
> Please advise to achieve a higher clock
> 
> 2400G X470(Daisy chain, 4-layer)
> CPU 39x 1.25v
> 
> GPU auto auto
> SOC 1.125v
> Ram 1.505v


Obvious starter for 10 for me is to try enabling GDM.

And lower your SoC, that's too high. Try 1.1v first, then lower if you can.

Saying that, CL12? What RAM you got?


----------



## polkfan

F4-3600C15-8GTZ

K4A8G085W[B/D]-BCPB (all 4 of these dimms say the same thing)

None of my 4 sticks tell me what nm or process node it was made on its just blank the timings are 3600mhz 15-15-15-35-50

So it's either D die or B-die makes no sense to me at all this kit cost be $160 i wanted B-die but with no RGB

I have 4 sticks of this stuff hoping to keep it until AM5 and DDR5 comes since i might be skipping zen 3 sadly after the news(first ryzen gen if so)

In total all 4 of these cost $320 today total so i'd be pissed if it sucked


----------



## SpecChum

polkfan said:


> F4-3600C15-8GTZ
> 
> K4A8G085W[B/D]-BCPB (all 4 of these dimms say the same thing)
> 
> None of my 4 sticks tell me what nm or process node it was made on its just blank the timings are 3600mhz 15-15-15-35-50
> 
> So it's either D die or B-die makes no sense to me at all this kit cost be $160 i wanted B-die but with no RGB
> 
> I have 4 sticks of this stuff hoping to keep it until AM5 and DDR5 comes since i might be skipping zen 3 sadly after the news(first ryzen gen if so)
> 
> In total all 4 of these cost $320 today total so i'd be pissed if it sucked


Those timings could be B-die, 3200C14 usually is, and 3600C15 is faster (8.75 vs 8.33ns). Could run them through Thaiphoon Burner, and see?

Try GDM mode first, then take it from there, but you'll have to raise your CL for >3200Mhz


----------



## 2600ryzen

Yeah I don't think non b die can do trcd/trp of 15 at 3600mhz.


----------



## hazium233

polkfan said:


> F4-3600C15-8GTZ
> 
> K4A8G085W[B/D]-BCPB (all 4 of these dimms say the same thing)
> 
> None of my 4 sticks tell me what nm or process node it was made on its just blank the timings are 3600mhz 15-15-15-35-50
> 
> So it's either D die or B-die makes no sense to me at all this kit cost be $160 i wanted B-die but with no RGB
> 
> I have 4 sticks of this stuff hoping to keep it until AM5 and DDR5 comes since i might be skipping zen 3 sadly after the news(first ryzen gen if so)
> 
> In total all 4 of these cost $320 today total so i'd be pissed if it sucked


Look on the label of the dimm for a code starting with 042. What are the last three digits? 10B usually indicates B-die.

There do seem to be a few murmurs that some recent lots of this sku have binned Samsung 8Gb D-die.


----------



## polkfan

After going through the 5 stages of grief i'll be buying a Taichi X570 or the MSI MEG X570 UNIFY whatever has the best VRM and bios support and is T-Topology 


Time for research i guess i have PLENTY of time before these prices and stock come back to earth but i have $350 ready to go. Zen 3 is it i guess for DDR4 memory. I won't be changing until we get good quality DDR5 sticks that are on par with current Samsung B-die(Must be bullzoid approved lol)


Came to this conclusion after reading all the patents for Zen 3 i expect bigger IPC gains then what we seen with Zen 2 even more so in latency based operations. 

Anyone wants more info just ask. 

AKA do not listen to the tech youtubers just cause its 7nm doesn't mean it won't be a major update how silly of a assumption for some of them to make the fabrication is nothing more then the crust on the pizza. May i remind you all of maxwell?


----------



## Dollar

polkfan said:


> After going through the 5 stages of grief i'll be buying a Taichi X570 or the MSI MEG X570 UNIFY whatever has the best VRM and bios support and is T-Topology



The X570 Taichi is not T-Topology, buildzoid's pre-production sample was but that changed. Not sure about the unify but it seems like everyone is going to daisy chain.


----------



## polkfan

Dollar said:


> The X570 Taichi is not T-Topology, buildzoid's pre-production sample was but that changed. Not sure about the unify but it seems like everyone is going to daisy chain.


Darn  

I really want to keep my same 4 dimm samsung b-die setup oh well daisy chain can't be that bad right?????? Right


----------



## Notbn

polkfan said:


> Darn
> 
> I really want to keep my same 4 dimm samsung b-die setup oh well daisy chain can't be that bad right?????? Right



Neither are T-top. Also don't get the Taichi. I had one and that chipset fan is the most annoying thing ever, also my chipset would hit 80C while gaming.... Unify is the better buy unless you MUST have intel lan and 6 sata ports.


----------



## rastaviper

polkfan said:


> F4-3600C15-8GTZ
> 
> 
> 
> K4A8G085W[B/D]-BCPB (all 4 of these dimms say the same thing)
> 
> 
> 
> None of my 4 sticks tell me what nm or process node it was made on its just blank the timings are 3600mhz 15-15-15-35-50
> 
> 
> 
> So it's either D die or B-die makes no sense to me at all this kit cost be $160 i wanted B-die but with no RGB
> 
> 
> 
> I have 4 sticks of this stuff hoping to keep it until AM5 and DDR5 comes since i might be skipping zen 3 sadly after the news(first ryzen gen if so)
> 
> 
> 
> In total all 4 of these cost $320 today total so i'd be pissed if it sucked


I have the same in 3200 and they are Bdie that can run up to 3733 15-14-13

Sent from my ONEPLUS A6003 using Tapatalk


----------



## EddieZ

hazium233 said:


> Look on the label of the dimm for a code starting with 042. What are the last three digits? 10B usually indicates B-die.
> 
> There do seem to be a few murmurs that some recent lots of this sku have binned Samsung 8Gb D-die.


Or check here: https://www.hardwareluxx.de/communi...b-die-liste-alle-hersteller-15-05-20.1161530/


----------



## KedarWolf

This 4000RPM RAM fan is amazing, at 1.5V my RAM doesn't go over 40C.

But likely the biggest improvement is I reset my 3950x in the socket when I changed the thermal paste (well, it actually pulled out of the socket trying to get the waterblock off it, lucky I never wrecked anything) and since then my RAM is performing much better. 










*My BIOS settings are in the Spoiler.*



Spoiler


----------



## nexxusty

MyUsername said:


> Did a bit of tinkering today, copy bench looks a bit dodgy but I like it. I don't know what else to tweak.


That is a nice kit you have there if that is TM5 stable.


----------



## Nikhil g18

KedarWolf said:


> This 4000RPM RAM fan is amazing, at 1.5V my RAM doesn't go over 40C.
> 
> But likely the biggest improvement is I reset my 3950x in the socket when I changed the thermal paste (well, it actually pulled out of the socket trying to get the waterblock off it, lucky I never wrecked anything) and since then my RAM is performing much better.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> *My BIOS settings are in the Spoiler.*
> 
> 
> 
> Spoiler


can you make it stable at 1t or gdm on ?


----------



## s1ll1

Hi
First time setting memorystuff, does these pictures settings look bad?
Dram voltage 1.5v, soc 1.1v,vddg ccd/iod 1.05v and cldo vddp 0.95v


----------



## KedarWolf

Nikhil g18 said:


> can you make it stable at 1t or gdm on ?


It's better GDM on. Higher bandwidth, same latency as well.


----------



## KedarWolf

Nikhil g18 said:


> can you make it stable at 1t or gdm on ?












Ran anta777 Extreme cfg as well, I think I have it dialed in pretty good.


----------



## thomasck

s1ll1 said:


> Hi
> 
> First time setting memorystuff, does these pictures settings look bad?


Numbers look fine. What voltages are you using? 
I also have a 4000 CL19 running at 3733 with very similar timings.

Sent from Tapatalk


----------



## s1ll1

thomasck said:


> Numbers look fine. What voltages are you using?
> I also have a 4000 CL19 running at 3733 with very similar timings.
> 
> Sent from Tapatalk


hi. Dram voltage 1.5v, soc 1.1v,vddg ccd/iod 1.05v and cldo vddp 0.95v


----------



## polkfan

Notbn said:


> Neither are T-top. Also don't get the Taichi. I had one and that chipset fan is the most annoying thing ever, also my chipset would hit 80C while gaming.... Unify is the better buy unless you MUST have intel lan and 6 sata ports.


Does it come with AC wifi i do need that? I've read so many comments about that chipset fan noise and i'm extremely picky about that stuff! So any choices around $300 not more would be nice don't want to spend that much more on a dead socket. 

GDM On 3600Mhz safe Dram Calc 1.7.1
AiDA64
52176 MB/S Read
28797 MB/s Write
52508 MB/s
69ns Latency
Test passed took 16.5 hours

3600mhz GDM On fast Dram Calc 1.7.1
Run 10PM

Hi i need help trying to get my 4 sticks of 8GB non RGB samsung B-die(3600mhz 15-15-15-35-50) to either boot without needing gear down mode or using tighter timings. Right now i'm trying to get the most out of 3600mhz).

If anyone can help me that would be great i've tried everything using dram calc 1.7.1, PROC, CAD and with diffrent configserations.
3200mhz all 4 sticks wil boot without GDM on but with 3600 it rquires it to be clear just 2 of these sticks run perfectly at 3800mhz 14-14-14-28-42 timings. I set my memory to 1.5V as i have good airflow and i'm doing that now.


Yes i do see the unify has Intel wifi AC so overall that's the board i plan on getting 

PLUS MSI is the ONLY company with a effing brain when it comes to moving that chipset fan AWAY from the bottom of your 300 watt GPU


----------



## KedarWolf

Nikhil g18 said:


> can you make it stable at 1t or gdm on ?












*Ran anta777 Extreme .cfg as well, I think I have it dialed in pretty good. *


----------



## yrelbirb

can a bad motherboard influence ram overclocking?

my friend has a asrock b450m hdv r4.0

and HYNIX JJR (taiphoon report)

we tried these timings;

3400 mhz 1.39v
tCL 16
tRCDRD 22
tRP16
tRAS 40
tRC 68

still, it crashes at boot

is it possible that motherboard is very bad at OC'ing?


----------



## rdr09

yrelbirb said:


> can a bad motherboard influence ram overclocking?
> 
> my friend has a asrock b450m hdv r4.0
> 
> and HYNIX JJR (taiphoon report)
> 
> we tried these timings;
> 
> 3400 mhz 1.39v
> tCL 16
> tRCDRD 22
> tRP16
> tRAS 40
> tRC 68
> 
> still, it crashes at boot
> 
> is it possible that motherboard is very bad at OC'ing?


Both my Samsung B-die and Hynix CJR C-die need 1.4v for 3400MHz. If you can give more info like results of dram calc and Ryzen timing checker, that might help diagnose the issue.


----------



## KedarWolf

Hey peeps, try to get your ProcODT as low as you can without getting errors in TM5. I tested mine, I can do 40 ohm on my 2x16GB DIMMs but any lower I get TM5 errors. :h34r-smi

The reason you want it low is you get better signal integrity the lower it is, though too low you'll get errors in TM5. 

With both Anta777 Extreme .cfg and 1usmus_v3 I get no errors at 40. 

Also, I do better with ClkDrvStren at 60, your CPU and memory will run a bit hotter but it can help with stability. :drum:

I run 60-20-24-24. :2cents:


----------



## SpecChum

KedarWolf said:


> Hey peeps, try to get your ProcODT as low as you can without getting errors in TM5. I tested mine, I can do 40 ohm on my 2x16GB DIMMs but any lower I get TM5 errors. :h34r-smi
> 
> The reason you want it low is you get better signal integrity the lower it is, though too low you'll get errors in TM5.
> 
> With both Anta777 Extreme .cfg and 1usmus_v3 I get no errors at 40.
> 
> Also, I do better with ClkDrvStren at 60, your CPU and memory will run a bit hotter but it can help with stability. :drum:
> 
> I run 60-20-24-24. :2cents:


This C6H defaults to 36.9ohm and 24-24-24-24 on auto, and it seems fine, so I'm leaving it lol


----------



## KedarWolf

SpecChum said:


> This C6H defaults to 36.9ohm and 24-24-24-24 on auto, and it seems fine, so I'm leaving it lol


I run my Dual Rank RAM at 3800MHz with really tight timings. Took a lot of tweaking to get it 100% stable, and I can do the timings with GDM enabled or disabled, TM5 stable, but I keep it enabled as I get more AIDA64 bandwidth. See below. :band:

Edit: Need to do it 2T GDM disabled though.


----------



## jfrob75

KedarWolf said:


> I run my Dual Rank RAM at 3800MHz with really tight timings. Took a lot of tweaking to get it 100% stable, and I can do the timings with GDM enabled or disabled, TM5 stable, but I keep it enabled as I get more AIDA64 bandwidth. See below. :band:
> 
> Edit: Need to do it 2T GDM disabled though.


 Thought I would take a moment and thank you for developing these timings. I have the same RAM kit as you and finally got around to trying your tighter timings. It took 1.52 volts in the BIOS for VDimm to get it stable with just changing tCL from 16 to 14. Once that was done changed all the other timings. Based on the RAM test in the Ryzen DRAM Calculator it is still stable. 

My voltage settings are:
SOC = 1125mv
VDDG = 1050mv
VDDP = 900mv
MEM VDDIO = 1.52V


CAD Bus Drive Strength:
24,20,24,24


CPU On-Die Termination:
43.6


GearDown = enabled


Cmd2t = 1T


----------



## glnn_23

Ive spent a bit of time now on getting the memory running ok with 2x8Gb and back to 4x8Gb here.

3800c14 and 3800c15 with 4 sticks is not doable for me and perhaps I need 2x16Gb to drop to the lower tCL.


----------



## tcclaviger

Here are my results. T-top or nothing for me!!

This is 4x8 Team Group Dark Pro 3200C14 @ 1.46v, auto vddp, vddg, and 1.09 soc.

Memtest x86 stable, including hammer test, and multiple runs of all blender bench tests completed.

CPU flat refuses to go over 1886 IF 😞


----------



## jcpq

tcclaviger said:


> Here are my results. T-top or nothing for me!!
> 
> This is 4x8 Team Group Dark Pro 3200C14 @ 1.46v, auto vddp, vddg, and 1.09 soc.
> 
> Memtest x86 stable, including hammer test, and multiple runs of all blender bench tests completed.
> 
> CPU flat refuses to go over 1886 IF 😞


Very nice.


----------



## Muqeshem

glnn_23 said:


> Ive spent a bit of time now on getting the memory running ok with 2x8Gb and back to 4x8Gb here.
> 
> 3800c14 and 3800c15 with 4 sticks is not doable for me and perhaps I need 2x16Gb to drop to the lower tCL.


What type of cooling you use for your CPU. It reaches near an undervolted ryzen 9 3590x with a 3.8ghz or 3.7ghz results in cinebench r20 multi cpu test.

This latency is insane indeed. But why your cl is 16 but your latency is below 62 ns ? 
Do the latency decrease with a highly overclocked ryzen cpu ?


----------



## KedarWolf

tcclaviger said:


> Here are my results. T-top or nothing for me!!
> 
> This is 4x8 Team Group Dark Pro 3200C14 @ 1.46v, auto vddp, vddg, and 1.09 soc.
> 
> Memtest x86 stable, including hammer test, and multiple runs of all blender bench tests completed.
> 
> CPU flat refuses to go over 1886 IF 😞


I'm struggling to believe those timings at that speed are TM5 or any RAM stress test stable. 

Edit: memtest86 not really a good test anymore, try TM5 or the RAM tester in the DRAM Calculator.


----------



## polkfan

Guys how can you made it where the board boots with gear down mode OFF with 4 sticks i tried all the ryzen calc settings. 

It can boot to 3400mhz off but can't even run a simple memory test


----------



## tcclaviger

KedarWolf said:


> tcclaviger said:
> 
> 
> 
> Here are my results. T-top or nothing for me!!
> 
> This is 4x8 Team Group Dark Pro 3200C14 @ 1.46v, auto vddp, vddg, and 1.09 soc.
> 
> Memtest x86 stable, including hammer test, and multiple runs of all blender bench tests completed.
> 
> CPU flat refuses to go over 1886 IF 😞
> 
> 
> 
> I'm struggling to believe those timings at that speed are TM5 or any RAM stress test stable. /forum/images/smilies/redface.gif
> 
> Edit: memtest86 not really a good test anymore, try TM5 or the RAM tester in the DRAM Calculator.
Click to expand...

Will give ram tester a whirl momentarily.

EDIT: Running TM5 so far so good, screenies coming...

EDIT2: Complete. C6E is a beast.

It's stable, not sure what's so hard to get?

Windows based testers are less accurate than memtest v8, but I'll take a screenshot to prove my point for you.


----------



## tcclaviger

Muqeshem said:


> glnn_23 said:
> 
> 
> 
> Ive spent a bit of time now on getting the memory running ok with 2x8Gb and back to 4x8Gb here.
> 
> 3800c14 and 3800c15 with 4 sticks is not doable for me and perhaps I need 2x16Gb to drop to the lower tCL.
> 
> 
> 
> What type of cooling you use for your CPU. It reaches near an undervolted ryzen 9 3590x with a 3.8ghz or 3.7ghz results in cinebench r20 multi cpu test.
> 
> This latency is insane indeed. But why your cl is 16 but your latency is below 62 ns ?
> Do the latency decrease with a highly overclocked ryzen cpu ?
Click to expand...

Clock speed, does indeed directly translate to lower aida64 measured latencies. The difference between 3800and 4200 for me is about 9ms, and repeatable. It hits 1 core per CCX, so it's full CPU speed that counts, at least in my CPU configuration that's how it runs the test.


----------



## Dollar

tcclaviger said:


> Will give ram tester a whirl momentarily.
> 
> EDIT: Running TM5 so far so good, screenies coming...
> 
> EDIT2: Complete. C6E is a beast.
> 
> It's stable, not sure what's so hard to get?
> 
> Windows based testers are less accurate than memtest v8, but I'll take a screenshot to prove my point for you.



memtest86 in 2020 eh?


Mind sharing the full list of timings?


----------



## KedarWolf

tcclaviger said:


> Will give ram tester a whirl momentarily.
> 
> EDIT: Running TM5 so far so good, screenies coming...
> 
> EDIT2: Complete. C6E is a beast.
> 
> It's stable, not sure what's so hard to get?
> 
> Windows based testers are less accurate than memtest v8, but I'll take a screenshot to prove my point for you.


Show us a timings screen of this app.

https://github.com/irusanov/ZenTimings/releases

This is me at 3800MHz.


----------



## tcclaviger

Attached as requested, and a screen of a ton of Benches using Bclk + PB to get higher boost speeds/performance. As a compromise for CPU stability, I had to back down 1 strap on mem/if to get the bclk up higher. These will be my daily settings now, offset -0.0325, LLC 1, SOC 1.09 (not 1.1 as shown in RM), DRAM @ 1.47.

NVME drive on top is pcie 3.0 x4, bottom is pcie 2.0 x4 (in bottom x16 slot via adaptor) to use all available pcie lanes efficiently. No performance drop from raised bclk. Much ado about nothing from people in that regard.

Data bus configuration is the C6E auto, 7/off/5 was causing crash on PC idle, no idea why.

TM 5 is less prone to show errors than memtest86 VERSION EIGHT... not sure what people don't get about that.... it's inside windows and cannot test as much ram, regardless, it passed 10 iterations, as 1usmus recommends for 32gb.


----------



## 2600ryzen

Haven't tried memtest86 v8, the version I have is OK it just hides problems with the SOC because the pci-e bus isn't really doing anything when you boot from usb. I can pass the old version of memtest86 at 3733mhz easily with 1.1v SOC but as soon as I run testmem5 in windows it's just non stop errors.


----------



## Dollar

tcclaviger said:


> Attached as requested, and a screen of a ton of Benches using Bclk + PB to get higher boost speeds/performance. As a compromise for CPU stability, I had to back down 1 strap on mem/if to get the bclk up higher. These will be my daily settings now, offset -0.0325, LLC 1, SOC 1.09 (not 1.1 as shown in RM), DRAM @ 1.47.
> 
> NVME drive on top is pcie 3.0 x4, bottom is pcie 2.0 x4 (in bottom x16 slot via adaptor) to use all available pcie lanes efficiently. No performance drop from raised bclk. Much ado about nothing from people in that regard.
> 
> Data bus configuration is the C6E auto, 7/off/5 was causing crash on PC idle, no idea why.
> 
> TM 5 is less prone to show errors than memtest86 VERSION EIGHT... not sure what people don't get about that.... it's inside windows and cannot test as much ram, regardless, it passed 10 iterations, as 1usmus recommends for 32gb.



Thanks for the info.



7/OFF/5 wouldn't work on my C6H + 4x8GB config either. I had to stay with the default 7/3/1. I'll have to go dig up my extra thumb drive and give the new memtest86 a try.


----------



## tcclaviger

Hope the settings help. These are ryzen calced but I had to mess with a couple here and there find stability, which I did at 3600 and 1.4v. From there it was just crank up voltage as clocks raise and B-Die did all the work lol.


----------



## KedarWolf

tcclaviger said:


> Attached as requested, and a screen of a ton of Benches using Bclk + PB to get higher boost speeds/performance. As a compromise for CPU stability, I had to back down 1 strap on mem/if to get the bclk up higher. These will be my daily settings now, offset -0.0325, LLC 1, SOC 1.09 (not 1.1 as shown in RM), DRAM @ 1.47.
> 
> NVME drive on top is pcie 3.0 x4, bottom is pcie 2.0 x4 (in bottom x16 slot via adaptor) to use all available pcie lanes efficiently. No performance drop from raised bclk. Much ado about nothing from people in that regard.
> 
> Data bus configuration is the C6E auto, 7/off/5 was causing crash on PC idle, no idea why.
> 
> TM 5 is less prone to show errors than memtest86 VERSION EIGHT... not sure what people don't get about that.... it's inside windows and cannot test as much ram, regardless, it passed 10 iterations, as 1usmus recommends for 32gb.


I changed ProcODT to 36.3 which ALWAYS gets a few random errors in TM5, I get them at less than 43.6, passed every Passmark MemTest Version 8.4, even the hammer test. 

So, I'm not sure how it is better.


----------



## 2600ryzen

Raising the bclk to 102.8mhz killed my 16Gb m.2 optane drive.


----------



## SpecChum

2600ryzen said:


> Raising the bclk to 102.8mhz killed my 16Gb m.2 optane drive.


:bigeyedsm "killed" as in it's completely dead, or just until you put it back to 100MHz?


----------



## tcclaviger

KedarWolf said:


> tcclaviger said:
> 
> 
> 
> Attached as requested, and a screen of a ton of Benches using Bclk + PB to get higher boost speeds/performance. As a compromise for CPU stability, I had to back down 1 strap on mem/if to get the bclk up higher. These will be my daily settings now, offset -0.0325, LLC 1, SOC 1.09 (not 1.1 as shown in RM), DRAM @ 1.47.
> 
> NVME drive on top is pcie 3.0 x4, bottom is pcie 2.0 x4 (in bottom x16 slot via adaptor) to use all available pcie lanes efficiently. No performance drop from raised bclk. Much ado about nothing from people in that regard.
> 
> Data bus configuration is the C6E auto, 7/off/5 was causing crash on PC idle, no idea why.
> 
> TM 5 is less prone to show errors than memtest86 VERSION EIGHT... not sure what people don't get about that.... it's inside windows and cannot test as much ram, regardless, it passed 10 iterations, as 1usmus recommends for 32gb.
> 
> 
> 
> I changed ProcODT to 36.3 which ALWAYS gets a few random errors in TM5, I get them at less than 43.6, passed every Passmark MemTest Version 8.4, even the hammer test. /forum/images/smilies/redface.gif
> 
> So, I'm not sure how it is better. /forum/images/smilies/rolleyes.gif
Click to expand...

Better because tm5 can't check all of the memory, it's explicitly impossible to check the reserved windows areas.

Keep using your windows based tested if you like, at the end of the day if the system isn't crashing on you, and is performing as expected, so no ecc errors impairing performance, it really doesn't matter what the tests say.

I won't use prime95 or occt either but many swear by them. I've never once had memory associated instability if 4 rounds of memtest86 pass, on any platform.


----------



## 2600ryzen

SpecChum said:


> :bigeyedsm "killed" as in it's completely dead, or just until you put it back to 100MHz?



Dead. RIP optane.


----------



## Bal3Wolf

So what vcore do you guys run on your cpus mine is a [email protected] all core overclock 1.315 vcore drops to 1.28 under load have tossed 6-8hrs of realbench at it 4 hrs of cb20 4-6 hrs of aida and gamed and i run metatrader also its nice and stable i dont really wanna go any higher on vcore about as high as i feel safe. Wonder what others have run 24/7 on the ryzen 3 series chips.




2600ryzen said:


> Raising the bclk to 102.8mhz killed my 16Gb m.2 optane drive.


if i raise my blck higher then 100 my ssds dont show up anymore but are back once i put it back to 100.


----------



## SpecChum

Bal3Wolf said:


> So what vcore do you guys run on your cpus mine is a [email protected] all core overclock 1.315 vcore drops to 1.28 under load have tossed 6-8hrs of realbench at it 4 hrs of cb20 4-6 hrs of aida and gamed and i run metatrader also its nice and stable i dont really wanna go any higher on vcore about as high as i feel safe. Wonder what others have run 24/7 on the ryzen 3 series chips.


I just run stock with PBO, it's more than enough for me.

Did you test your FIT voltage before you set that 1.315v?

Your voltage is above what most consider "safe", which seems to be between 1.1v and 1.2v with a Prime95 small FFT load.

You could potentially degrade the CPU with too high a voltage.

EDIT: Just tested mine, it's 1.161v, so yeah, you're too high.


----------



## Bal3Wolf

1.1 to 1.2 ? i never seen it that low even with pbo on stock lol no i didnt mess with FIT voltages.


----------



## KedarWolf

SpecChum said:


> I just run stock with PBO, it's more than enough for me.
> 
> Did you test your FIT voltage before you set that 1.315v?
> 
> Your voltage is above what most consider "safe", which seems to be between 1.1v and 1.2v with a Prime95 small FFT load.
> 
> You could potentially degrade the CPU with too high a voltage.
> 
> EDIT: Just tested mine, it's 1.161v, so yeah, you're too high.


I run a CCX overclock with an Offset that sets voltages max at 1.3v in BIOS, 1.258 when running Cinebench.

My CPU temps when running Cinebench are actually LOWER than with a PBO overclock by a good amount, so I feel my voltages are fine.

From what I understand if your voltage under load is under say 1.3v max with a fixed or CCX overclock you're fine.


----------



## SpecChum

Bal3Wolf said:


> 1.1 to 1.2 ? i never seen it that low even with pbo on stock lol no i didnt mess with FIT voltages.


Turn PBO on, set 300, 230, 230 and try Prime95 Small FFT with HWiNFO running.

The minimum voltage you see on the SVI2 TFN CPU Core Voltage is your FIT max; that's the most voltage FIT sees fit to put through your processor when it's under max load, like P95.

The way you have it now it'd use your static voltage for every load, even Prime95 where it should be dropping it, and that's potentially dangerous.

I've got a 3900X too, and mine was 1.61v, so I'd be careful. Just don't want you running into stability issues in 6 months due to a slightly degraded CPU.


----------



## Bal3Wolf

KedarWolf said:


> I run a CCX overclock with an Offset that sets voltages max at 1.3v in BIOS, 1.258 when running Cinebench.
> 
> My CPU temps when running Cinebench are actually LOWER than with a PBO overclock by a good amount, so I feel my voltages are fine.
> 
> From what I understand if your voltage under load is under say 1.3v max with a fixed or CCX overclock you're fine.




Yea im always under 1.3 under load and temps wise my cpu never hits 70c tops out around 65-67c with my 420 and 360 rad with my strike waterblock.


----------



## SpecChum

KedarWolf said:


> I run a CCX overclock with an Offset that sets voltages max at 1.3v in BIOS, 1.258 when running Cinebench.
> 
> My CPU temps when running Cinebench are actually LOWER than with a PBO overclock by a good amount, so I feel my voltages are fine.
> 
> From what I understand if your voltage under load is under say 1.3v max with a fixed or CCX overclock you're fine.


https://www.reddit.com/r/overclocking/comments/ejd5c9/1325v_is_not_safe_for_zen_2/

Cinebench isn't a high enough load, you need something like Prime95 on small FFT.

Mine only wants to push 1.16v when I run that.


----------



## Bal3Wolf

iv seen warnings all over to not run prime 95 smallfft on these ryzens that alone can degrade them even with stock setups. To me i don't think its very useful just like your talking about all core voltages being higher your going to have more voltages pushed thru your cpu on 80% of stuff you run because the cpu is not detecting the power draw and down volting it more.


----------



## Tobiman

My 3600 needs about 1.46 volts to maintain 4.150ghz. Is this a bad chip?


----------



## Bal3Wolf

SpecChum said:


> Turn PBO on, set 300, 230, 230 and try Prime95 Small FFT with HWiNFO running.
> 
> The minimum voltage you see on the SVI2 TFN CPU Core Voltage is your FIT max; that's the most voltage FIT sees fit to put through your processor when it's under max load, like P95.
> 
> The way you have it now it'd use your static voltage for every load, even Prime95 where it should be dropping it, and that's potentially dangerous.
> 
> I've got a 3900X too, and mine was 1.61v, so I'd be careful. Just don't want you running into stability issues in 6 months due to a slightly degraded CPU.




Ok i did exacty what you said my SVI TFN is 1.275 goes up to 1.294 that was on a stock balanced power plan also i just noticed switching to amd high perf plan its staying around 1.294-1.301 avg

i like how he explains stuff


----------



## KedarWolf

The MSI Unify AGESA 1.0.0.5 beta bIOS is bugged. With PBO bug, even just PBO enabled, the CPUs never move from a stock 3.5HGz. 

I even tried buildzoid recommended settings, nada, and this with PBA enabled in the Advanced menu AND the CPU settings menu.


----------



## Bal3Wolf

that sucks try 350 350 19 i got some wierd boosts using that it goes way high tho and pulls a ton of power only setting i had almost held 4.4Ghz boost on all cores in cb20 I have no idea what it will do on a msi and 3950x tho.


----------



## SpecChum

Bal3Wolf said:


> Ok i did exacty what you said my SVI TFN is 1.275 goes up to 1.294 that was on a stock balanced power plan also i just noticed switching to amd high perf plan its staying around 1.294-1.301 avg


Cool, I was just being careful, I just don't want anyone getting any surprises down the road  Hope I didn't offend anyone.

Weird how are chips are like 100mv apart, must be a binning thing.

Mine dives straight to 1.191v then after a few minutes drops to 1.175v, then pretty much stays there with a couple of dips to 1.169v or even 1.161v, presumably to hold the temperature steady.


----------



## SpecChum

@Bal3Wolf

Just seen your power usage at 190W, mine seems to max out out at 146W under P95 Small FFT for 3.95GHz, so I do think it's a binning thing.

You also clearly have better cooling, I'm only on a 280mm AIO so I'm gimped by the flowrate from the teeny tiny pump and mediocre radiator

Saying that, I do have the RGB ML140's on there, which stop at under 1200RPM, so I might swap them for the non RGB version ML's I've got also, as they top out at 2000RPM - not that I'd use them at that speed, too loud, but 1500 to 1700 isn't too bad, that should knock a couple of degrees off the water temp, which reaches 42C after a while.

My graphics card lives a life of cool luxury however, that's got a D5 pump and a 360mm radiator all to itself lol


----------



## Bal3Wolf

i did drop my clock down to 4.3ghz to be a little safer for now load is hovers between 1.237 to 1.269 idle and load im fairly happy with that.


----------



## polkfan

What kind of speeds and timings do you guys typically get with 4 dimms? Been awhile seen i saw bullzoid's show.


----------



## jfrob75

Anyone been able to push 4 DIMMs of B-die 3600MHz GSkill 4 x 16GB rank 2 memory beyond it's default? If so what are your settings?
I have 2 kits of GSkill F4-3600C16-16GTZN. 32GB per kit.
Just installed in my 2nd kit and not able to post beyond default of 3600MHz. I have been able to tighten up some of the Primary and secondary timings with a VDimm of 1.43V but no luck with higher freq at default timings and even higher VDimm of 1.47.


----------



## Joseph Mills

@*polkfan* & @*jfrob75* 


I have a 4x16 dual rank 3200C15 b-die setup, and I'm stable at 3533Mhz CL16 1.42V. In order to hit 3600 (which is my max), I have to set the Rtt to either 7-2-1 or 6-3-1. At this point, I encounter random cold-boot issues, but is stable once it gets running. At 3533, I don't run into these issues with my kit. So, if you want to hit a higher clock, try those two Rtt settings. Also, my ProcODT is set at 40 OHM.


EDIT:
Here's a spreadsheet of what people have been able to hit with different numbers of dimms on the different Zen platforms - https://docs.google.com/spreadsheet...MWVPcYjf6nOlr9CtkkfN78tSo/edit#gid=1814864213


----------



## KedarWolf

Can having RGB affect RAM stability even if temps are sub 40C while stress testing? :h34r-smi

I ask because my RAM has tested TestMem5 just fine with RGB off, but I'm having issues with the same settings and even tweaking the settings with RGB on.


----------



## 2600ryzen

Sounds like it is though I don't see how if the temps are low?


----------



## jfrob75

Joseph Mills said:


> @*polkfan* & @*jfrob75*
> 
> 
> I have a 4x16 dual rank 3200C15 b-die setup, and I'm stable at 3533Mhz CL16 1.42V. In order to hit 3600 (which is my max), I have to set the Rtt to either 7-2-1 or 6-3-1. At this point, I encounter random cold-boot issues, but is stable once it gets running. At 3533, I don't run into these issues with my kit. So, if you want to hit a higher clock, try those two Rtt settings. Also, my ProcODT is set at 40 OHM.
> 
> 
> EDIT:
> Here's a spreadsheet of what people have been able to hit with different numbers of dimms on the different Zen platforms - https://docs.google.com/spreadsheet...MWVPcYjf6nOlr9CtkkfN78tSo/edit#gid=1814864213


Thanks for the input. I may give it another try using your suggestions.


----------



## expor

I spent the whole week reading multiple recommended sources (1usmus guide, DDR4 OC guide on github, Ryzen OC guide on reddit), on DDR4 overclocking but the more I read, the more I get confused. One source contradicts the other. One says RCDRW and RCDRD should be kept the same, while others say just lower either as far as you can. Similar for TRAS, TRP and many other parameters. Meanwhile some guides say lowering any parameter too far can cause negative performance impact. So here I am, hoping your expertise can help me figure out which of the achieved timings can maybe be improved further.

After a lot of manual tinkering and tweaking (Managed to get 3600-16-10-19-8) I used the DRAM Calculator to OC my stock Ballistix BLS8G4D32AESBK 3200 (2x8GB) kit to 3600-15-15-19-16-36 at 1.38V (details below). Basically I took all the recommended settings for the 'Fast Preset' for my Micron E-Die and everything seems fine! It passed 10 cycles of TM5 (1usmus v3 config) and 7707% Karhu without any errors. Cinebench R20 score went from ~3710 to ~3750 (going from auto XMP 3200 to OC 3600). AIDA64 reports ~52741gb/s avg with ~67.5ns avg latency (based on 5 runs).

I'm running a 3600X (stock settings) on an MSI B450 TOMAHAWK MAX board.

SiSoft Sandra results: https://ranker.sisoftware.co.uk/show...a598a88efdc0f0

So my questions

Do my achieved results make sense related to reported performance?
General remarks on what I could change to improve latency and / or bandwith?
Should I try to lower tRCDRW as far as possible? I already know tRCDRD doesn't like anything lower than 19 at this frequence. I also noticed when going from tRCDRW 16 to 15, my reported write speed in DRAM Calculator on average has dropped from ~30gbs to ~27.5gbs, although Cinebench R20 scores improved.
Should I try to lower tRP as far as possible? Of course adapting tRAS / tRC accordingly.
After achieving above (stable tested) results yesterday, I lowered tWR to 12 and tRFC to 507. I did a few 'Easy' test in DRAM Calculator and it seemed fine, but this wasn't very extensive of course. This morning on coldboot the PC wouldn't POST. I had to reset CMOS and load my stable tested settings again for it to boot (I didn't try booting with lowered tWR and tRFC immediately which would've been more conclusive). Could this be because of the additionally lowered the tWR / tRFC, or does this have to be in my base (stable tested) settings? I have had three coldboots on the stable tested settings since, and they were all fine. Tips to prevent this if it occurs again?
I tried the Safe and Fast 3800 (CL16) presets as well. The PC would boot but my keyboard and mouse kept dis/re-connecting (they have RGB LED so it was obvious). DRAM Calculator meanwhile continued to run, so it seemed USB specific. Any idea what I could do to get that fixed? I'm perfectly fine with my current 3600 OC, but curious nevertheless. I also saw my latency dropped to ~65ns, rather than the ~67.5ns I'm getting at 3600 which I found odd, since 3800 @ CL16 should be slower than CL15 @ 3600.

PS. Please let me know if this is the wrong place to ask my questions!


----------



## TK421

Anything I can do to tighten this kit more?


----------



## Karagra

Hey everyone sitting on a 3900x, and some Viper 4400mhz cl 19 ram... I was wondering what I could do to tighten these timings... I know 3800mhz 1:1 is best who has really tested 4600mhz on the ram + to see if it compares outside of 1:1?


----------



## Veii

TK421 said:


> Anything I can do to tighten this kit more?


Holy mess  
Yes, fix tWRRD it's far to high
tFAW is too high, tWTRL is too low, tRTP is not in sync (not with tWR and not with tRFC) 
your SD DD ones are strange, pretty sure they where auto predicted - and your SCL can drop -1 
Also you have GDM enabled, soo primaries are autocorrected

Out of curiosity, does mem tweak allow you to change EVERYTHING at the right
Or does it just tempt you and only shows their readouts ?
Please try how this behaves
Need a confirmation, if this works on dual rank or not 








@Karagra This is under 2T or 1T ? 
GDM Off ?
Please use 
https://github.com/irusanov/ZenTimings/releases to showcase used timings 
What was auto predicted and what is set by you 
These are some quite high values, some make sense - some are just far to high without reason


----------



## TK421

Veii said:


> Holy mess
> Yes, fix tWRRD it's far to high
> tFAW is too high, tWTRL is too low, tRTP is not in sync (not with tWR and not with tRFC)
> your SD DD ones are strange, pretty sure they where auto predicted - and your SCL can drop -1
> Also you have GDM enabled, soo primaries are autocorrected
> 
> Out of curiosity, does mem tweak allow you to change EVERYTHING at the right
> Or does it just tempt you and only shows their readouts ?
> Please try how this behaves
> Need a confirmation, if this works on dual rank or not
> 
> 
> 
> 
> 
> 
> 
> 
> 
> @*Karagra* This is under 2T or 1T ?
> GDM Off ?
> Please use
> https://github.com/irusanov/ZenTimings/releases to showcase used timings
> What was auto predicted and what is set by you
> These are some quite high values, some make sense - some are just far to high without reason





Hi,


I will test your suggested memory settings.




I can't do 3800C14 btw.



I'm at *1.39v memory* w/ vrm settings maxed out (phase count, response, current, etc).








I know b-die scales very nicely with voltage but I don't feel like pumping considerably more volts than stock (for now).










Memtweakit doesn't actually change timing settings. I don't think any software can, maybe ryzen master but it's a bit iffy.


----------



## rares495

Karagra said:


> Hey everyone sitting on a 3900x, and some Viper 4400mhz cl 19 ram... I was wondering what I could do to tighten these timings... I know 3800mhz 1:1 is best who has really tested 4600mhz on the ram + to see if it compares outside of 1:1?


Everything above 3800 is much worse. Even if you reach 4600 CL15 or 4800 CL16, the performance won't be great.


----------



## jfrob75

Here are my timings for 4DIMMS on a GB X570 Aorus Extreme.
Has anyone been able to get 4DIMMs to run @3733MHz or 3800MHz on Aorus Extreme?



Spoiler


----------



## Veii

jfrob75 said:


> Here are my timings for 4DIMMS on a GB X570 Aorus Extreme.
> Has anyone been able to get 4DIMMs to run @3733MHz or 3800MHz on Aorus Extreme?


The extreme isn't by any chance T-Topolgy ?
4x A0 might be possible at 3734MT/s if you remain under 48procODT
3800 can work if you can run that at 34.4Ohm with cad_bus 120-20-20-24
But if you have A1 or A2 kits, or even dual rank ~ your chance on a daisy chain one will be very low
3667 is usually the absolute max, while non A0 kits will have a hard time with only 25% of the signal on the 2nd row of dimms
T-topology would be 50/50% with some struggle with A2 kits but higher success than daisy chain with 4 dimms


----------



## Karagra

Veii said:


> Holy mess
> @Karagra This is under 2T or 1T ?
> GDM Off ?
> Please use
> https://github.com/irusanov/ZenTimings/releases to showcase used timings
> What was auto predicted and what is set by you
> These are some quite high values, some make sense - some are just far to high without reason


----------



## jfrob75

Veii said:


> The extreme isn't by any chance T-Topolgy ?
> 4x A0 might be possible at 3734MT/s if you remain under 48procODT
> 3800 can work if you can run that at 34.4Ohm with cad_bus 120-20-20-24
> But if you have A1 or A2 kits, or even dual rank ~ your chance on a daisy chain one will be very low
> 3667 is usually the absolute max, while non A0 kits will have a hard time with only 25% of the signal on the 2nd row of dimms
> T-topology would be 50/50% with some struggle with A2 kits but higher success than daisy chain with 4 dimms


I am fairly certain the Extreme is daisy chain and my DIMMS are Rank 2 B1 so I guess I should be happy with tight timings @ 3600MHz.


----------



## Veii

Karagra said:


>


Hmm some timings make sense, some really don't
Who decided for that high tRC and that low tRAS ~ it's low because tWR is high
tRAS is being auto corrected that low, while tRC has over 46ns wait-for-action delay
Nothing will happen till tRC isn't over
The same goes for tFAW, it awaits 6x tRRDS while it can only accept 4x before termination 
You can add there a bit of delay, to cover precharge speed - but too much would be a waste

tRDRD , tWRWR SD DD - make all sense, they are a bit low but they make sense
SCL looks to be also low at 5 @ this speed 
tRDWR is kinda correct, but tWRRD is not, should be 3 at least 
i think 807 tRFC tries to be a perfect 350ns - but it's also a bit offsync
It should be 805-598-368 at this speed, and not 807-600-369
It sounds to me like it was auto predicted, at least it tried 
https://docs.google.com/spreadsheets/d/1A7G97QOL0dNMwJZa9SYEq2RElJ5T6Hcx9WdReTsnIWw/
here again the tiny tRFC calulator for such things 

tRC 46, 69,92 look to be whole value transitions - 20ns,30ns,40ns Cycle delay @ 4600MT/s
It's good that you don't relay on GDM at all here, makes things easier
But some of the values are soo high predicted - the only explanation for stability are the many many delays wasted everywhere

Higher Primaries with clean transitions should technically behave far better than low primaries and high rest to keep up stability 
Can you please try this set, it's very experimental
I have trust in it, but it might make you issues - because it's CL18











jfrob75 said:


> I am fairly certain the Extreme is daisy chain and my DIMMS are Rank 2 B1 so I guess I should be happy with tight timings @ 3600MHz.


Sounds like 3600 would be the maximum
Maybe 3667MT/s 
Whats your current procODT and CAD_BUS setup ?
Same for the voltages ~ VDDP,VDDG,VSOC,VDIMM


----------



## Karagra

Veii said:


> Hmm some timings make sense, some really don't
> Who decided for that high tRC and that low tRAS ~ it's low because tWR is high
> tRAS is being auto corrected that low, while tRC has over 46ns wait-for-action delay
> Nothing will happen till tRC isn't over
> The same goes for tFAW, it awaits 6x tRRDS while it can only accept 4x before termination
> You can add there a bit of delay, to cover precharge speed - but too much would be a waste
> 
> tRDRD , tWRWR SD DD - make all sense, they are a bit low but they make sense
> SCL looks to be also low at 5 @ this speed
> tRDWR is kinda correct, but tWRRD is not, should be 3 at least
> i think 807 tRFC tries to be a perfect 350ns - but it's also a bit offsync
> It should be 805-598-368 at this speed, and not 807-600-369
> It sounds to me like it was auto predicted, at least it tried
> https://docs.google.com/spreadsheets/d/1A7G97QOL0dNMwJZa9SYEq2RElJ5T6Hcx9WdReTsnIWw/
> here again the tiny tRFC calulator for such things
> 
> tRC 46, 69,92 look to be whole value transitions - 20ns,30ns,40ns Cycle delay @ 4600MT/s
> It's good that you don't relay on GDM at all here, makes things easier
> But some of the values are soo high predicted - the only explanation for stability are the many many delays wasted everywhere
> 
> Higher Primaries with clean transitions should technically behave far better than low primaries and high rest to keep up stability
> Can you please try this set, it's very experimental
> I have trust in it, but it might make you issues - because it's CL18
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sounds like 3600 would be the maximum
> Maybe 3667MT/s
> Whats your current procODT and CAD_BUS setup ?
> Same for the voltages ~ VDDP,VDDG,VSOC,VDIMM


EDIT: Turns out using TM5 its unstable... Would trying 4400mhz be a better option? Ram boots at 4800mhz but crashes within a minute of windows 10 being fully loaded.


----------



## Veii

Karagra said:


> EDIT: Turns out using TM5 its unstable... Would trying 4400mhz be a better option? Ram boots at 4800mhz but crashes within a minute of windows 10 being fully loaded.


Uhm, i can not do anything with this information i'm sorry
I could help you a bit if you share a TM5 screenshot of when it errors out and under what error 
4400 would need different timings, 4600 ones where optimised for 4600 they should break on anything other than 4600

But did you even confirm your set of timings were stable in the first place before submitting the Aida64 screenshot ?
I used it as a base, but how do we know your kit can run that in the first place 
Even when the kit is XMP rated - it still can be that your setup (RTT,Voltage,CAD_BUS,procODT all are wrong) preventing intelXMP to remotely have a chance of working


----------



## jfrob75

[QUOTE
Sounds like 3600 would be the maximum
Maybe 3667MT/s 
Whats your current procODT and CAD_BUS setup ?
Same for the voltages ~ VDDP,VDDG,VSOC,VDIMM[/QUOTE]


These value are shown in the images in my previous post but here they are anyway.
procODT = 43.6
CAD_BUS = 24,20,24,24
VSOC = 1.05
VDDP = .950
VDDG = 1.00
VDIMM = 1.46


The times I have tried to post at higher mem frequency it does not make it past the memory training. I have tried numerous procODT values, CAD_BUS settings, Dat Bus Config values and SOC values. I put all the memory timings settings to AUTO when I do this. I have VDIMM as high as 1.5 volts. No luck making beyond memory training. I can run 2 DIMMS with tight timings at 3800MHz just not 4 DIMMS. So, my guess is it may be some lower level BIOS settings that we have no control over.


P.S. Once my test bench arrives I am going try these 4DIMMS in my CH8 MB.


----------



## Reous

@*Karagra* 
Is 4600 the highest clock you can boot or is more possible? My B-Die only do 4666/4733 but still trying to get them stable. Changed now to Micron E-Die @* *DDR4-5000 . I know it isn't worth it, it is just for fun.


----------



## Cosminnn

Finally managed to get stable. Reading around, I lowered trdwr and twrrd from 8-3 ( auto on bios settings) to 9-4.

Looking to see if I can lower trfc and stay stable. Remind me please ... tRFC should be in sync with? tWR and tRTP ...


----------



## hazium233

Reous said:


> @*Karagra*
> Is 4600 the highest clock you can boot or is more possible? My B-Die only do 4666/4733 but still trying to get them stable. Changed now to Micron E-Die @* *DDR4-5000 . I know it isn't worth it, it is just for fun.


4000MT/s Elite kit?

From what I understand, those had C9BKV in them (decodes to CT40A1G8SA-55M:E) ... which means 0.55ns = 3600MT/s native. 

I think it was chip hell where someone pulled the heatspreaders on a new Ballistix 3600 kit, and it now had C9BKV as well (instead of C9BJZ like Elite 3600 had).

You or emissary42 didn't happen to pull the heatspreaders on the BL2K16G36C16U4R set that was reviewed at hardwareluxx did you? For science? 

Anyway what is interesting to me is that there are some FBGA codes for seemingly absurd native speeds from Micron:

C9BJZ - CT40A1G8SA-62M:E - 0.62ns - 3200MT/s

C9BKV - CT40A1G8SA-55M:E - 0.55ns - 3600MT/s

C9BLL - CT40A1G8SA-050M:E - 0.50ns - 4000MT/s

C9BLM - CT40A1G8SA-045M:E - 0.45ns - 4400MT/s

I don't know if any of those latter are in the wild, but 4400MT/s at 1.200V seems amusing, I have no idea what the spec timings are supposed to be at that speed. The old part sheet I have doesn't cover these.


----------



## SpecChum

Cosminnn said:


> Remind me please ... tRFC should be in sync with? tWR and tRTP ...


Yep, and yours are fine, I know this as they're same as mine, 288, 12 (x24) and 8 (x36)


----------



## Muqeshem

SpecChum said:


> Yep, and yours are fine, I know this as they're same as mine, 288, 12 (x24) and 8 (x36)


Is there a guide to know which values should sync with each others ?
I know that tRP and tRCDRD should equal tRAS and tRP + tRAS should equal tRC.
However, I didn't know that tWR and tRTP should be synced with tRFC with those values times 24 and times 36 respectively. 

Please find my ZenTiminings screenshot for my memory, it is a dual rank running it at 1.4 dram volt and 1.1soc. tRFC value was 304 but i synced them based on your comments.


----------



## SpecChum

Muqeshem said:


> Is there a guide to know which values should sync with each others ?
> I know that tRP and tRCDRD should equal tRAS and tRP + tRAS should equal tRC.
> However, I didn't know that tWR and tRTP should be synced with tRFC with those values times 24 and times 36 respectively.
> 
> Please find my ZenTiminings screenshot for my memory, it is a dual rank running it at 1.4 dram volt and 1.1soc. tRFC value was 304 but i synced them based on your comments.


I really don't think it matters that much, but doesn't hurt to do it, I guess. It's not the 24 and 36 that's important, only that the to lower values divide into tRFC.

Someone like @Veii might be best to ask why.


----------



## Veii

Cosminnn said:


> Finally managed to get stable. Reading around, I lowered trdwr and twrrd from 8-3 ( auto on bios settings) to 9-4.
> 
> Looking to see if I can lower trfc and stay stable. Remind me please ... tRFC should be in sync with? tWR and tRTP ...


Where did you get or found out these tRDRD SD , DD / tWRWR SD,DD values ?
Is there any logic why you used for example 1-5-5-1-6-6 , instead of 1-7-7 ?
difference of 1 between R & W might be too small of a difference
It shouldn't need to let you use such high tRDWR and then even need tWRRD delay afterwards
wasted delay for idk what stability reason
Seems like it was needed but that means (on single rank even more sure) that something else times out and needs that latency 
I atm just suspect your SD,DD values as troublemaker, as the rest doesn't look bad


Muqeshem said:


> Is there a guide to know which values should sync with each others ?
> I know that tRP and tRCDRD should equal tRAS and tRP + tRAS should equal tRC.
> However, I didn't know that tWR and tRTP should be synced with tRFC with those values times 24 and times 36 respectively.
> 
> Please find my ZenTiminings screenshot for my memory, it is a dual rank running it at 1.4 dram volt and 1.1soc. tRFC value was 304 but i synced them based on your comments.


Short guide, baseline edition
*tCL* = voltage scaled
*tRCD* = IC dependent
*tRP* = voltage scaling and PCB dependent , defines capacitor discharge and recharge time - discharge happens automatically even without a triggered discharge
*tRAS* = tRCD+tCL or tWR+tCL+tBL (2 in this case), 2nd option is for awkward scenarios or high speeds - at best it meets both formulas with the same value / no wiggle room
*tRC* = tRP + tRAS / +2 or +4 for stability, -2 as lowest 
*tRRD, tWTR* are unique (delay depends on bank amount) but tRRDL 8 is JEDEC spec 
You want at best, run *tWTRL* = tRRDS*2
*tWR* = tRRDS+tWTRS (lowest), tRAS-tRCD (optimal), tCL+tRTP (highest) , tRTP*2 (alternative) ~ has to be an even number
*SCL's*= PCB, IC, voltage dependent / lower has a big boost
*tCWL* = keep it identical to tCL - makes more issues than it's worth to tweak ~ makes issues with tRDWR delay
*tRTP *= optimally clean divider of tRFC, even better if half of tWR but no must - tRFC divider is important
*tRFC* = baseline is clean multiple of tRC in ns not virtual value
(use https://docs.google.com/spreadsheet...YEq2RElJ5T6Hcx9WdReTsnIWw/edit#gid=1745688811 for help)
*SD, DD* values are a bit unclear but keep 2 as delay between tRDRD and tWRWR ~ or use 1-1-1-1-1-1 as failsafe for unstable kits, bad values will cut perf
*tRDWR & tWRRD* where explained here / dual rank needs +2, math remains identical, 4 dimms might need tWRRD added delay with tRDWR= tRCD RD/2



jfrob75 said:


> These value are shown in the images in my previous post but here they are anyway.
> procODT = 43.6
> CAD_BUS = 24,20,24,24
> VSOC = 1.05
> VDDP = .950
> VDDG = 1.00
> VDIMM = 1.46
> 
> 
> The times I have tried to post at higher mem frequency it does not make it past the memory training. I have tried numerous procODT values, CAD_BUS settings, Dat Bus Config values and SOC values. I put all the memory timings settings to AUTO when I do this. I have VDIMM as high as 1.5 volts. No luck making beyond memory training. I can run 2 DIMMS with tight timings at 3800MHz just not 4 DIMMS. So, my guess is it may be some lower level BIOS settings that we have no control over.
> 
> P.S. Once my test bench arrives I am going try these 4DIMMS in my CH8 MB.


Wasn't the CH8 also daisy chain ?
4 dimms on daisy chain even more 4x A2 will make you a very hard time

Try two sets of voltages:
CCD focused if FCLK and high procODT is the issue~
VDDP = .900
VDDG CCD = 1050
VDDG IOD = .975
VSOC = 1.125

If Board struggles with dimm amount or A2/B2 PCB:
VDDP = .900
VDDG CCD = 950
VDDG IOD = 1000
VSOC = 1.1

Rec optimals are:
VDDP = .900
VDDG IOD = 975
VDDG CCD = 950
VSOC = 1.075

Failsafe
VDDP = .900
VDDG CCD = 975
VDDG IOD = 1050
VSOC = 1.125

You can prioritize CCD or IOD up to needs
higher CCD makes sense for a 3950X or sTR4
But VDDP above 900mV is not really needed unless you pass the 1900 MCLK mark
Later 950 might be better


----------



## SpecChum

Veii said:


> *tRAS* = tCL+tRAS


That can't be right lol

tCL + tRCD maybe?


----------



## Veii

SpecChum said:


> That can't be right lol
> 
> tCL + tRCD maybe?


typo


----------



## Reous

hazium233 said:


> 4000MT/s Elite kit?
> 
> From what I understand, those had C9BKV in them (decodes to CT40A1G8SA-55M:E) ... which means 0.55ns = 3600MT/s native.
> 
> You or emissary42 didn't happen to pull the heatspreaders on the BL2K16G36C16U4R set that was reviewed at hardwareluxx did you? For science?



Yes 4000 Elite Kit. Older TB version says D9VPP and newest version says D9WFL so idk
No we haven't removed the HS because of warranty rules


----------



## Cosminnn

Veii said:


> Where did you get or found out these tRDRD SD , DD / tWRWR SD,DD values ?
> Is there any logic why you used for example 1-5-5-1-6-6 , instead of 1-7-7 ?
> difference of 1 between R & W might be too small of a difference
> It shouldn't need to let you use such high tRDWR and then even need tWRRD delay afterwards
> wasted delay for idk what stability reason
> Seems like it was needed but that means (on single rank even more sure) that something else times out and needs that latency
> I atm just suspect your SD,DD values as troublemaker, as the rest doesn't look bad


There are auto settings from Bios ... not really played with those settings. Is there any suggestion on how to set it manually? 1-7-7-1-7-7 will work or the right combination is 1-5-5-1-7-7?
Thanks for the time taken to investigate.


----------



## Dr. Vodka

I've managed to improve some more on my old overclock with my 4x16GB DR sticks of Rev. E










I'll gladly take 3466MHz over 3400MHz. Amusingly enough, I could never get 3466MHz to be stable with my 2x8GB B-die sticks, most likely the C6H being a T-topology board just hating having only two sticks to work with.

How would you further tweak these timings? It's already doing tRCDRD a bit below 10ns (9.8ns) which is awesome, couldn't be happier about these sticks.

ProcODT below 48 ohms won't POST. tRFC2 (386) and tRFC4 (238) are set as per Veii's sheet.

--------------------------------------------------------

I can't stabilize 3533MHz no matter what. I understand I'm just asking too much out of my 1700 at this point. I have to tweak the PHY settings a lot to get the errors down, whereas 3466MHz is stable on mostly default settings (ProcODT 48, RZQ 7/2/1, 24-20-20-24). These are the settings that get me the least errors:










RTTwr at any setting results in loads of errors. Disabling it gets me down to three errors. 24-20-20-24 got me 4 errors in another run. Probably the same in the end and could've got 3 or 4 errors either way.

It sometimes errors in the second or third run (~20 minutes per run), sometimes well into ~2 hours of testing. It's random. I may have missed some more voltage somewhere. Can't quite pinpoint what is failing, but I'm pretty sure it's the IMC/fabric just giving up under such load. 

--------------------------------------------------------

3600MHz is impossible to work with, as expected. vSOC over 1.15v doesn't help... as expected, tweaking PHY settings from defaults shifts the errors from instant to ~3 minutes into TM5 at loose primaries (18-20-20-20-40) and auto timings on the rest as per this excellent guide. 

Some 3666MHz results just for fun

3733MHz boots to the BIOS, hangs as soon as Windows starts loading, lol, my 1700 just wants to kill itself and be done with at this point. My two B-die sticks wouldn't even POST at 3733MHz


----------



## KedarWolf

KedarWolf said:


> My Blender on my Godlike, the quoted first one was my Unify.
> 
> I expected to get an only marginally better overclock on my Godlike, it's pretty much CPU dependent.
> 
> Still, a decent Blender run.
> 
> 
> 
> Spoiler


An updated version of Blender out, renders the image faster.

This is me with a mild BCLK overclock and Blender Classroom.

At my 24/7 settings I run, stress-tested stable and TM5 stable. 

3:54.28.


----------



## Karagra

Reous said:


> @*Karagra*
> Is 4600 the highest clock you can boot or is more possible? My B-Die only do 4666/4733 but still trying to get them stable. Changed now to Micron E-Die @* *DDR4-5000 . I know it isn't worth it, it is just for fun.


Same boat, I can boot up to 4733, and if i try like 20x i can get it to randomly train 4800 for wont train again for another 20x extremely unstable, I have spent the last few days testing between 4400-4733 trying to figure out what would be the best spot to start setting up sub-timings

EDIT: I cant seem to really get over 4400mhz to run TM5 without throwing an error or 2, I wish Dram Calculator had experimental timings for 4400+ xD. Have you managed to get yourself above 4400mhz without it throwing an error?


----------



## Karagra

Is it weird I can 1:1 my FCLK through every MHZ my board will post at? I can post up to 4733mhz


----------



## hazium233

Reous said:


> Yes 4000 Elite Kit. Older TB version says D9VPP and newest version says D9WFL so idk
> No we haven't removed the HS because of warranty rules


Right, warranty is why I didn't pull HS on my AES to see if they are C9BJZ instead of D9VPP. 

From what I understand, thaiphoon rarely seems to read these C9 part numbers (if at all). So for C9BJZ, they are almost always read D9VPP. Have seen a few commenters in various places who did pull heatsinks to verify. One comment on chiphell suggested that any of the Sport LT's produced in 2019 were C9BJZ, and I think it is plausible the new line is also using it in the same bins.

Not sure if anyone finds this interesting or if it is off topic, but here was the one chiphell post where someone pulled the heatspreader off the new Ballstix 3600 and it had C9BKV chips. Saw a thread on an Australian forum about this too, but it didn't have pictures.

I think it would be funny to see some of these parts do 3600MT/s or higher at 1.200V, although I have no clue what Micron is using for the speed bin timings at these grades. The 8Gbit part document I have just goes to -62E and -62Y for 3200MT/s at JEDEC 22-22-22. My two 3200C16 Sport LT sticks pass GSAT at little tighter than XMP at 1.200V though. I should try to run XMP through AIDA at 1.2 and see what happens, but haven't gotten around to that.


----------



## Reous

Karagra said:


> Have you managed to get yourself above 4400mhz without it throwing an error?



On the Strix X570-I i have managed to get 4533 CL16 stable (Karhu + Aida). So i expect 4666 CL17 with the Impact. Next week i will continue my tests.




Spoiler



*DDR4-3533 Samsung B-Die*











*DDR4-5000 Micron E-Die*















hazium233 said:


> Not sure if anyone finds this interesting or if it is off topic, but here was the one chiphell post where someone pulled the heatspreader off the new Ballstix 3600 and it had C9BKV chips. Saw a thread on an Australian forum about this too, but it didn't have pictures.



Yeah this is interesting. I will check out this on the weekend.


----------



## Silent Scone

4x8GB (F4-4266C17Q-32GTZR)

3733 1:1 C14-15-14-361T 1.45v

3950X 44/44/43/43 1.32v


----------



## KedarWolf

These timings are great considering the voltages. But my b-die doesn't like higher voltages. I tried these settings at 1.45v and higher, get errors within three cycles. As a result, I don't think I'll ever get CL14 stable. 










Sub 3.54 Blender Classroom, but that is with all tasks shutdown, and all unnecessary services stopped in Windows 10. 

The second is without shutting down tasks and services, only start-up programs disabled in the start-up tab in task manager.

These are NOT benchmarking BIOS settings I'm using, but my settings I run on my PC 24/7. :drum:

I'm afraid to push this CPU to past what I feel is safe as it's on 7nm and I fear I will degrade it trying to push high voltages and high clocks. :h34r-smi


----------



## KedarWolf

KedarWolf said:


> These timings are great considering the voltages. But my b-die doesn't like higher voltages. I tried these settings at 1.45v and higher, get errors within three cycles. As a result, I don't think I'll ever get CL14 stable.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sub 3.54 Blender Classroom, but that is with all tasks shutdown, and all unnecessary services stopped in Windows 10.
> 
> The second is without shutting down tasks and services, only start-up programs disabled in the start-up tab in task manager.
> 
> These are NOT benchmarking BIOS settings I'm using, but my settings I run on my PC 24/7. :drum:
> 
> I'm afraid to push this CPU to past what I feel is safe as it's on 7nm and I fear I will degrade it trying to push high voltages and high clocks. :h34r-smi


Old stand-by RAM test.


----------



## Cosminnn

https://www.overclock.net/forum/11-amd-motherboards/1730162-official-asrock-x570-overclocking-support-thread-63.html#post28486048

Not to double post, but do you have any idea about the values for tFAW using Advanced-AMD CBS- UMC-DRAM Timing configuration, rather than OC Tweaker?

<< Found it meanwhile, it is in HEXA, so 16 hexa decimal is 22 decimal, I need 16 decimal ... that would be 10 hexadecimal.>>


----------



## TK421

Veii said:


> Holy mess
> Yes, fix tWRRD it's far to high
> tFAW is too high, tWTRL is too low, tRTP is not in sync (not with tWR and not with tRFC)
> your SD DD ones are strange, pretty sure they where auto predicted - and your SCL can drop -1
> Also you have GDM enabled, soo primaries are autocorrected
> 
> Out of curiosity, does mem tweak allow you to change EVERYTHING at the right
> Or does it just tempt you and only shows their readouts ?
> Please try how this behaves
> Need a confirmation, if this works on dual rank or not
> 
> 
> @*Karagra* This is under 2T or 1T ?
> GDM Off ?
> Please use
> https://github.com/irusanov/ZenTimings/releases to showcase used timings
> What was auto predicted and what is set by you
> These are some quite high values, some make sense - some are just far to high without reason















Can't do 14 or lower primary timings


I revised some stuff, and this is stable with 1.45v memory voltage.


GDM off seems to not be stable.


----------



## Veii

TK421 said:


> Can't do 14 or lower primary timings
> 
> I revised some stuff, and this is stable with 1.45v memory voltage.
> GDM off seems to not be stable.


Start that way








GDM you get away by using high ClkDrvStrengh and possible higher VDDG IOD - up to board 
60-20-24-24 for example
or 80-20-24-24 CAD_BUS


----------



## rares495

Cosminnn said:


> Finally managed to get stable. Reading around, I lowered trdwr and twrrd from 8-3 ( auto on bios settings) to 9-4.
> 
> Looking to see if I can lower trfc and stay stable. Remind me please ... tRFC should be in sync with? tWR and tRTP ...


Amazing! Congrats!


----------



## KedarWolf

Cosminnn said:


> Finally managed to get stable. Reading around, I lowered trdwr and twrrd from 8-3 ( auto on bios settings) to 9-4.
> 
> Looking to see if I can lower trfc and stay stable. Remind me please ... tRFC should be in sync with? tWR and tRTP ...


tRFC Calculator

https://docs.google.com/spreadsheets/d/1A7G97QOL0dNMwJZa9SYEq2RElJ5T6Hcx9WdReTsnIWw/edit#gid=0


----------



## Gadfly

KedarWolf said:


> tRFC Calculator
> 
> https://docs.google.com/spreadsheets/d/1A7G97QOL0dNMwJZa9SYEq2RElJ5T6Hcx9WdReTsnIWw/edit#gid=0


Trfc is not a calculated value. It is an arbitrary number and can be run at any value as long as your memory will tolerate it; anyone that tells your trfc is a multiplier of another timing, or should be perfectly dividable by a value simply doesn't understand what Trfc is or what it does. 

The best practice is to lower it until you start generating errors; then start to slowly raise the value and test memory performance and stability. Going too low can cause a performance loss, but your memory will start to error before you hit that point.


----------



## TK421

Veii said:


> Start that way
> 
> 
> 
> 
> 
> 
> 
> 
> GDM you get away by using high ClkDrvStrengh and possible higher VDDG IOD - up to board
> 60-20-24-24 for example
> or 80-20-24-24 CAD_BUS



Hold on I'm also reading some stuff on the ddr4 oc guide github


https://github.com/integralfx/MemTestHelper/blob/master/DDR4 OC Guide.md


I will revise some more, 1.45v results in too much memory heat (causes issues at 50c).


What does clkdrvstrength do? I left it on auto for my board.


VDDG IOD is at 965 or 970 afaik.
VDDSOC 1.0675v LLC3












TRFC 330 / 246 / 151


----------



## thomasck

Gadfly said:


> Trfc is not a calculated value. It is an arbitrary number and can be run at any value as long as your memory will tolerate it; anyone that tells your trfc is a multiplier of another timing, or should be perfectly dividable by a value simply doesn't understand what Trfc is or what it does.
> 
> 
> 
> The best practice is to lower it until you start generating errors; then start to slowly raise the value and test memory performance and stability. Going too low can cause a performance loss, but your memory will start to error before you hit that point.


Positive, I've seen people saying tRFC got to be a multiplier of tWR, and I'm using like that. tRFC 276 and tWR 12. Coincidentally 276 is near the limit here.

Sent from Tapatalk


----------



## Gadfly

thomasck said:


> Positive, I've seen people saying tRFC got to be a multiplier of tWR, and I'm using like that. tRFC 276 and tWR 12. Coincidentally 276 is near the limit here.
> 
> Sent from Tapatalk


They would be incorrect. tWR has nothing to do with tRFC. it can be literally any number. You want to start at a close number based on your voltage (voltage drives how low you can run tRFC, as it is relys on enough charge in the capacitors to refresh the row.) The faster you refresh the row, the less waiting, the faster your total memory performance. 

There is no multiples of another timing, or syncing with another timing.

Here is what our good friend Bullzoid said about it:

" tRFC scales with voltage on some ICs so at 2V you can run lower TRFC than at 1.5V. There's not any way I'm aware of to calculate it as it's just a physical property of the memory. However if you've tested that at 2133MHz 1.5V the lowest stable TRFC is 200nCK then at 4266 it should be around 400nCK."

Here is a good chart on how you can expect trfc to scale:

https://preview.redd.it/vqizab42rr431.png?width=1150&format=png&auto=webp&6597de7e


----------



## Gadfly

thomasck said:


> Positive, I've seen people saying tRFC got to be a multiplier of tWR, and I'm using like that. tRFC 276 and tWR 12. Coincidentally 276 is near the limit here.
> 
> Sent from Tapatalk


They would be incorrect. tWR has nothing to do with tRFC. it can be literally any number. You want to start at a close number based on your voltage (voltage drives how low you can run tRFC, as it is relys on enough charge in the capacitors to refresh the row.) The faster you refresh the row, the less waiting, the faster your total memory performance. 

There is no multiples of another timing, or syncing with another timing.

Here is what our good friend Bullzoid said about it:

" tRFC scales with voltage on some ICs so at 2V you can run lower TRFC than at 1.5V. There's not any way I'm aware of to calculate it as it's just a physical property of the memory. However if you've tested that at 2133MHz 1.5V the lowest stable TRFC is 200nCK then at 4266 it should be around 400nCK."

Here is a good chart on how you can expect trfc to scale:

https://preview.redd.it/vqizab42rr431.png?width=1150&format=png&auto=webp&6597de7e


----------



## Gadfly

Base profile for the new memory kit. I know there is still a lot of work to be done to tighten up the timings, I just wanted get a good stable base profile. 

Key voltages and settings:

Vcore: 1.31 LLC 3 (droop to 1.28v under load)
VDDG: 0.945
VDDP: 0.900
vSOC: 1.07v
DRAM: 1.47v
Proc_ODT: 30ohm


----------



## TechnoPeasant

Question for you guys, do any of you happen to know what tRFC, tRFC2, and tRFC4 mean on a x570 Asus mobo? I'm following the mem OC guide on github, which has a formula for tRFC timings, but I can't figure out how they apply to these 3 fields in my BIOS. Thanks!


----------



## nowarranty

Testing out some samsung b die, is 3533 cl13 1.5v and 1.04v soc too much for a 24/7 overclock?

I tried 3533 cl14 and got interested in tightening further, I used the ryzen dram calculator tool and set the fast timings for 3533 then changed cas latency. 

Curious if that additional voltage for cl13 is harmless and worth the benefits. Can't remember where I read that up to 1.5v was okay for usage but not sure about 24/7. 

Also, would I gain more out of the system in general by increasing timings and trying to get infinity fabric to 1800 or 1900 if possible instead of a lower frequency and tighter ram timings?


----------



## Gadfly

nowarranty said:


> Testing out some samsung b die, is 3533 cl13 1.5v and 1.04v soc too much for a 24/7 overclock?
> 
> I tried 3533 cl14 and got interested in tightening further, I used the ryzen dram calculator tool and set the fast timings for 3533 then changed cas latency.
> 
> Curious if that additional voltage for cl13 is harmless and worth the benefits. Can't remember where I read that up to 1.5v was okay for usage but not sure about 24/7.
> 
> Also, would I gain more out of the system in general by increasing timings and trying to get infinity fabric to 1800 or 1900 if possible instead of a lower frequency and tighter ram timings?


1.5v is fine for 24/7 B-die. I have a kit that has been running 1.52v 24/7 for 3 years with no ill effects; and I am not talking about a desktop that is idle, it is in my build box, it is crunching memory intensive processes all day every day.


----------



## Veii

@thomasck before you follow any random guide, always use SiSoftware Sandra - Multi-Core efficiency Test
To doublecheck your results, where only your offline ones matter

It will show timing differences and subtle one you might not see
But the only graph that interests us is the Detailed Latency Curve , aka IF Peak Bandwidth curve
Some results, yes including tRFC might behave lower and some might trigger cycle stacking and behave faster 

At the end every OCer has their own set of rules ~ they have to, else it will be booring 
But tRFC might scale with voltage, tho that's not the whole part of the story WHY it does scale with voltage 
It doesn't go alone and only tREF(i) is average and unpredictable 
Well test your results, words don't matter when the results are bad ^^#
~ but seems like this tRFC discussion moved over here with exact the same wording, might as well just link the starting point on another thread 
Buildzoid is not wrong, just that isn't the whole part of the story


----------



## thomasck

@Veii actually I'm still using the timings I got from you over the taichi x370 thread, months ago. You recommended 280, that's what I was using. Then I've seen somewhere here around OC.net it should be a multiple of tWR, so I set to 276 and started to have problems with weird horizontal lines in the screen from time to time, but no stress test would fail. Any way, then set it back to 280, and after to 294, which is what I'm using now. I'm not having problems with the timings, all seems fine, that was just a consideration.


----------



## Veii

thomasck said:


> @Veii actually I'm still using the timings I got from you over the taichi x370 thread, months ago. You recommended 280, that's what I was using. Then I've seen somewhere here around OC.net it should be a multiple of tWR, so I set to 276 and started to have problems with weird horizontal lines in the screen from time to time, but no stress test would fail. Any way, then set it back to 280, and after to 294, which is what I'm using now. I'm not having problems with the timings, all seems fine, that was just a consideration.


Which speed ?
Still grab SiSandra 
It's a good tool to test tiny differences - although average Inter-Core bandwidth will vary
SuperPi 1.5SX is a good test for both cpu+memory performance 

maybe 288 works better for you, but it depends on the frequency


----------



## nowarranty

Gadfly said:


> Base profile for the new memory kit. I know there is still a lot of work to be done to tighten up the timings, I just wanted get a good stable base profile.
> 
> Key voltages and settings:
> 
> Vcore: 1.31 LLC 3 (droop to 1.28v under load)
> VDDG: 0.945
> VDDP: 0.900
> vSOC: 1.07v
> DRAM: 1.47v
> Proc_ODT: 30ohm


I'm working on similar speeds and timings


When I stabilize my ram overclocks with SOC and DRAM voltage should I then start lowering VDDG and VDDP by 10mv until I get errors?

Also, I set LLC of low/medium on SOC voltage but I still see it spiking from 1.03 to 1.04 under load at times. I tried dynamic soc voltage but it still idled at 1.03. Any suggestions about this?


----------



## Veii

nowarranty said:


> When I stabilize my ram overclocks with SOC and DRAM voltage should I then start lowering VDDG and VDDP by 10mv until I get errors?
> 
> Also, I set LLC of low/medium on SOC voltage but I still see it spiking from 1.03 to 1.04 under load at times. I tried dynamic soc voltage but it still idled at 1.03. Any suggestions about this?


cLDO_VDDP -> VDDG 50mV
VDDG -> VSOC 50mV

minimum voltage offset, actually it's 48 but 50 works
That's behavior by AMD spec
If you want to lower it by yourself, you should enable UncoreOC mode inside AMD OVERCLOCKING


----------



## thomasck

Veii said:


> Which speed ?
> Still grab SiSandra
> It's a good tool to test tiny differences - although average Inter-Core bandwidth will vary
> SuperPi 1.5SX is a good test for both cpu+memory performance
> 
> maybe 288 works better for you, but it depends on the frequency


3733! In spoiler are the timings,
procodt 32
nom off
wr off
park 5
30-20-24-24
vddp 0950
both vddg 950
soc 1050
ram 1.47



Spoiler















Yeah, I use SuperPi 1.5SX to quick check performance, 9.003s it's the best I can get atm. Now is fore sure a bit higher as tRFC is 294. 

280 also happened to display some very quick horizontal lines in the screen here and there too, maybe some degradation? Can't believe in that as maximum used was 1.47v in this a2 bdie rated to 4000 cl19, hyperx predator


----------



## nick name

Which SuperPi test do I run?


----------



## Veii

nick name said:


> Which SuperPi test do I run?


32million digits


----------



## nowarranty

Veii said:


> cLDO_VDDP -> VDDG 50mV
> VDDG -> VSOC 50mV
> 
> minimum voltage offset, actually it's 48 but 50 works
> That's behavior by AMD spec
> If you want to lower it by yourself, you should enable UncoreOC mode inside AMD OVERCLOCKING


I'm not sure what you mean with


> cLDO_VDDP -> VDDG 50mV
> VDDG -> VSOC 50mV


I am using the ryzen dram tool to get reference voltages, should I work my way down from the recommended voltage or up from the minimum?
Bios lets me enter the voltages directly but there is no offset for these


----------



## nick name

Veii said:


> 32million digits


How long does that take?


----------



## Veii

nowarranty said:


> I'm not sure what you mean with
> I am using the ryzen dram tool to get reference voltages, should I work my way down from the recommended voltage or up from the minimum?
> Bios lets me enter the voltages directly but there is no offset for these


The less voltage the better, 
less vSOC = lower procODT = higher reachable FCLK

IMC to Frequency Voltage samples
12nm = 2nd gen and 3rd gen ~ same IMC just a K17 rebrand
https://www.overclock.net/forum/13-...membench-0-8-dram-bench-827.html#post28490842

Voltage Patterns so you understand how scaling works
https://www.overclock.net/forum/18051-memory/1746444-oc-ing-t-force-4133-cl18.html#post28424814
^ the center message of this post

In short words
VDDG needs to be at least 50mV higher than cLDO_VDDP else you choke it
VSOC the main line that covers the fabric & the memory controller needs to be at absolute minimum 50mV higher than VDDG
soo
VDDP -> VDDG 50mV bump
VDDG-> VSOC 50mV bump

You need to enable UncoreOC mode inside AMD OVERCLOCKING menu, if you want to use own custom voltages
else they will be autocorrected


----------



## Veii

nick name said:


> How long does that take?


Between 7-9 minutes 
Up to CPU and Memory speed
It's also a pretty accurate benchmark for memory performance, and a heavy one for the fabric


----------



## nick name

Veii said:


> Between 7-9 minutes
> Up to CPU and Memory speed
> It's also a pretty accurate benchmark for memory performance, and a heavy one for the fabric


Is it single or multi-threaded?


----------



## Keith Myers

@nick name
Multi-threaded.


----------



## Yuke

Any idea how i could tackle GDM off?

Its Dual Rank RAM

SOC ~1.115V
VDDP 1V
VDDG 1.05V
DRAM ~1.43V


----------



## nowarranty

Veii said:


> The less voltage the better,
> less vSOC = lower procODT = higher reachable FCLK
> 
> IMC to Frequency Voltage samples
> 12nm = 2nd gen and 3rd gen ~ same IMC just a K17 rebrand
> https://www.overclock.net/forum/13-...membench-0-8-dram-bench-827.html#post28490842
> 
> Voltage Patterns so you understand how scaling works
> https://www.overclock.net/forum/18051-memory/1746444-oc-ing-t-force-4133-cl18.html#post28424814
> ^ the center message of this post
> 
> In short words
> VDDG needs to be at least 50mV higher than cLDO_VDDP else you choke it
> VSOC the main line that covers the fabric & the memory controller needs to be at absolute minimum 50mV higher than VDDG
> soo
> VDDP -> VDDG 50mV bump
> VDDG-> VSOC 50mV bump
> 
> You need to enable UncoreOC mode inside AMD OVERCLOCKING menu, if you want to use own custom voltages
> else they will be autocorrected


Thank you so much for sharing this! :thumb:
I will test more and try to lower voltages, I was able to tweak 1866mhz FCLK but could not boot 1900mhz with any configuration. Loose timings and high voltages did not help.

I am new to ryzen, will running high DRAM voltages like 1.5v be too stressful for the ryzen IMC? Trying to figure out if I should increase CL by 1 and lower the voltages by 0.05v for longevity


----------



## happyluckbox

Does anybody know if there is a way in bios to disable ram sticks? Sometimes my workload requires me to use large amounts of ram (200gb+), but alot of my workload requires less ram (64gb or less), and I'd like to use a higher overclock for those workloads.
Short of physically removing ram, is there anyway to quickly disable ram/ranks?


----------



## rares495

Gadfly said:


> Trfc is not a calculated value. It is an arbitrary number and can be run at any value as long as your memory will tolerate it; anyone that tells your trfc is a multiplier of another timing, or should be perfectly dividable by a value simply doesn't understand what Trfc is or what it does.
> 
> The best practice is to lower it until you start generating errors; then start to slowly raise the value and test memory performance and stability. Going too low can cause a performance loss, but your memory will start to error before you hit that point.


You divide it by other timings to get the best possible sync. That's what the "calculator" "calculates". Going too low can hurt performance and cause instability.


----------



## rares495

Yuke said:


> Any idea how i could tackle GDM off?
> 
> Its Dual Rank RAM
> 
> SOC ~1.115V
> VDDP 1V
> VDDG 1.05V
> DRAM ~1.43V


It's tough to get GDM off stable with dual rank memory. And probably not worth it.


----------



## nowarranty

rares495 said:


> It's tough to get GDM off stable with dual rank memory. And probably not worth it.


Should I be aiming for very high overclocks with GDM off or on? I saw the ryzen dram calculator was mentioning to keep it off but the searches I've done are showing me the opposite? I only have a few days on ryzen so far


----------



## Veii

Yuke said:


> Any idea how i could tackle GDM off?
> 
> Its Dual Rank RAM
> 
> SOC ~1.115V
> VDDP 1V
> VDDG 1.05V
> DRAM ~1.43V


You might need to lower every voltage by around 25-50mV 
Change for now tRDWR to 9, tWRRD to 4 
Then try CAD_BUS 90-20-24-24
or was it 80 :thinking: increase ClkDrvStrengh just 1-2 steps beyond 60ohm 


nowarranty said:


> I am new to ryzen, will running high DRAM voltages like 1.5v be too stressful for the ryzen IMC? Trying to figure out if I should increase CL by 1 and lower the voltages by 0.05v for longevity


High VDIMM might need higher CAD_BUS but 1.5 isn't that much 
About the IMC, it doesn't matter for vDIMM 


happyluckbox said:


> Does anybody know if there is a way in bios to disable ram sticks? Sometimes my workload requires me to use large amounts of ram (200gb+), but alot of my workload requires less ram (64gb or less), and I'd like to use a higher overclock for those workloads.
> Short of physically removing ram, is there anyway to quickly disable ram/ranks?


Sadly no , not even in AMD CBS
But you can use the "maxmem" command inside windows to disable bank groups
people often use maxmem: 4086 , when they want to push 1.9v on 2x8gb B-die dimms 
Sadly even that doesn't have manual scaling and will limit it equally from all the dimms

No i really don't think you can :thinking:
AMD CBS at best would be the place to go looking for, but i haven't seem AMD implementing this feature inside their AGESAs
Maybe you should write https://twitter.com/Thracks Robert by asking if there is any way inside AMD CBS for EPYC & Threadripper systems to disable dimms fully
If not, they will then at least include it in the next big agesa update :thumb:

EDIT:
I was thinking about Clover Injecting DSDT firmware, and there fixing it (as this bootloader has low level access)
But even there - you can change memory speed of the units and even "redo" memory size ~ pretty much overwrite it by the serial number
But i haven't seen it being able to purely "disable" the memory access to it
Will need to look, it's been some time
If anyone wants to export me the whole ACPI / DSDT folder of their ryzen ~ backed up via clover
I can take a look on how DSDT firmware is build these days ~ tho i'm pretty sure you can't at this point
You can kick away PCIe and USB host controllers, but i haven't seen a method to purely disable dimms ~ tho it's possible to only use half a size of each


----------



## Spectre73

*Need Help at the edge of stability*

So I am nearly stable with my 2x16 F4-3200C14-16GTZSW RAM.
I am running it at 3600 with the values according to the Ryzen Master screenshot I took.

Karhu RAM errors only happen once in a lifetime, so sometime it runs above 20000%, but sometimes, rarely, it errors at 12k or whatever. TM 5 and everything else works fine.

I would like to eliminate the last instability. Which value(s) do I need to adjust most likely? RAM temp with torture testing is just under 50°C, no way to change that. And I don't want to add a fan or whatever. I will probably get a better airflow case in the future, my Phanteks Evolve is not great in that regard. Last error over night happend at around 11000% with 48°C. RAM at 1.40v is definitely prone to errors. Above that I only tested for 1,45v. That already gave me near stability, but I do not want to go higher, voltage wise.

Your help would be greatly appreciated!


----------



## Veii

Spectre73 said:


> So I am nearly stable with my 2x16 F4-3200C14-16GTZSW RAM.
> I am running it at 3600 with the values according to the Ryzen Master screenshot I took.
> 
> Karhu RAM errors only happen once in a lifetime, so sometime it runs above 20000%, but sometimes, rarely, it errors at 12k or whatever. TM 5 and everything else works fine.
> 
> I would like to eliminate the last instability. Which value(s) do I need to adjust most likely? RAM temp with torture testing is just under 50°C, no way to change that. And I don't want to add a fan or whatever. I will probably get a better airflow case in the future, my Phanteks Evolve is not great in that regard. Last error over night happend at around 11000% with 48°C. RAM at 1.40v is definitely prone to errors. Above that I only tested for 1,45v. That already gave me near stability, but I do not want to go higher, voltage wise.
> 
> Your help would be greatly appreciated!


Put ClkDrvStrengh to 30 (CAD_BUS) 
and try tRFC 312-232-143 with tRTP 8, tWR 16
If tWR is too low, push 24, i think 16 should be just enough

VCore looks a bit high, likely requires negative offset with PBO 
- but that's something you'd know how to setup as these values look from buildzoid


----------



## Spectre73

Veii said:


> Put ClkDrvStrengh to 30 (CAD_BUS)
> and try tRFC 312-232-143 with tRTP 8, tWR 16
> If tWR is too low, push 24, i think 16 should be just enough
> 
> VCore looks a bit high, likely requires negative offset with PBO
> - but that's something you'd know how to setup as these values look from buildzoid


Thanks for the reply. I will try CAD_BUS value and tRFC. tWR too low was erroring out, so I raised it. Not sure if I want to lower it again, but I will definitely try 24, once I tried the other settings. Your tRTP sugestion looks very low also - I can not imagine that I will gain stability by lowering it, so I will first try CAD_BUS and tRFC.

Just one addition. My "instability" if you can even call it that way, was with AddrCmdDrvStr of 24. I just today lowered it to 20. I am atm running a KARHU test and will probably have to wait some time until I can say for sure if it helps.

It is true that I used buildzoid values for PBO, but I did not pay attention to negative offset. The picture was taken with a KARHU run in progress, what would you suggest for lowering VCore?


----------



## 2600ryzen

If you can run 1.1v SOC and 1v VDDG at 1900mhz in desync mode does that mean I should definitely be able to run 3733mhz in 1:1 mode with only 1.1v SOC? 

I still seem to need [email protected] to run testmem5 without errors or the computer randomly powering off during testmem5. I'm running procodt 28Ohms and auto cad strength(24-24-24-24 I think), I played with the cad strengths and VDDG/P a little without being able to see a difference.


----------



## Veii

Spectre73 said:


> Thanks for the reply. I will try CAD_BUS value and tRFC. tWR too low was erroring out, so I raised it. Not sure if I want to lower it again, but I will definitely try 24, once I tried the other settings. Your tRTP sugestion looks very low also - I can not imagine that I will gain stability by lowering it, so I will first try CAD_BUS and tRFC.
> 
> Just one addition. My "instability" if you can even call it that way, was with AddrCmdDrvStr of 24. I just today lowered it to 20. I am atm running a KARHU test and will probably have to wait some time until I can say for sure if it helps.
> 
> It is true that I used buildzoid values for PBO, but I did not pay attention to negative offset. The picture was taken with a KARHU run in progress, what would you suggest for lowering VCore.


You'd need ClkDrvStrengh for more dimms or dual rank 
if you have "too strong signal degredation" issues 
You should rather lower your main voltages - for example VDDP and VDDG IOD 
As you're on X570 ontop of that on a good board, you don't need much IOD at all 
That should help then pushing ClkDrvStrengh higher 
Which does help to lower procODT 

it should not error out when you use them together
but try to use tRTP and tRFC together
else only CAD_BUS alone 
No timing goes alone on memory, tho the set looks already pretty solid


----------



## Spectre73

Veii said:


> You'd need ClkDrvStrengh for more dimms or dual rank
> if you have "too strong signal degredation" issues
> You should rather lower your main voltages - for example VDDP and VDDG IOD
> As you're on X570 ontop of that on a good board, you don't need much IOD at all
> That should help then pushing ClkDrvStrengh higher
> Which does help to lower procODT
> 
> it should not error out when you use them together
> but try to use tRTP and tRFC together
> else only CAD_BUS alone
> No timing goes alone on memory, tho the set looks already pretty solid


Just for confirmation: I should raise ClkDrvStrength to 30 and simultaneously reduce VDDG IOD? If I do that, I also need to lower VDDP since that needs to be around 50 mV lower than VDDG, right?
I am a little bit confused with your additional remarks, but I will try your old suggestions first and see, if I need to follow through with voltage reduction (VDDG/VDDP).


----------



## Veii

Spectre73 said:


> Just for confirmation: I should raise ClkDrvStrength to 30 and simultaneously reduce VDDG IOD? If I do that, I also need to lower VDDP since that needs to be around 50 mV lower than VDDG, right?
> I am a little bit confused with your additional remarks, but I will try your old suggestions first and see, if I need to follow through with voltage reduction (VDDG/VDDP).


It was only an answer as you mentioned ClkDrvStrengh higher made instability issues for you
IF you have instability issues by it, it's not from it, but rather the rest of the voltages 
Pushing it a bit higher doesn't harm , especially on 4 dimms  

i see RTT_Park 240ohm , soo you should have 4*8 dimms 
4 dimms on daisy chain is annoying, as the remain 2 dimms get only 25% of the signal strengh 
Daisy Chain runs in 75/25 % - T-Topology splits it 50/50 
Do you have any voltage control over the 2nd set of dimms ? Channel B ? 

You can lower VDDG IOD overal , well we'll see later 
So far everything looks alright only average vcore looked too high ~ but that's another topic
Try for now just a bit higher clkdrvstrengh and see if the sample of timings work
First just change the CAD_BUS value and that should resolve the error
But i think you can go higher , and then later try the better timings


----------



## Veii

2600ryzen said:


> If you can run 1.1v SOC and 1v VDDG at 1900mhz in desync mode does that mean I should definitely be able to run 3733mhz in 1:1 mode with only 1.1v SOC?
> 
> I still seem to need [email protected] to run testmem5 without errors or the computer randomly powering off during testmem5. I'm running procodt 28Ohms and auto cad strength(24-24-24-24 I think), I played with the cad strengths and VDDG/P a little without being able to see a difference.


Need far more information 
What's your setup 
Which dimms are you using, how many of them
1v cLDO_VDDP is already high
You don't need more than 900mV to hit 1900FCLK 
Poweroff relates to voltage yes, but it can also be overcurrent protection - it can be a lot of things

It can be voltage choking too~
Please give more information and start with 900mV cLDO_VDDp
actually 913 would be just fine for it ~ same 2nd gen rules apply here too, except that we get no memory "hole" because VDDG voltage is changeable


----------



## Spectre73

Veii said:


> i see RTT_Park 240ohm , soo you should have 4*8 dimms


As I wrote, I am on 2x16 Dimms. RTT values off/3/1 are normal for this setup, AFAIK. It is not only the Auto setting in BIOS but also the recommended setting in DRAM calc. Also, I have not seen anything else on 2x16.

The rest of your answer is understood, thank you!


----------



## 2600ryzen

Veii said:


> Need far more information
> What's your setup
> Which dimms are you using, how many of them
> 1v cLDO_VDDP is already high
> You don't need more than 900mV to hit 1900FCLK
> Poweroff relates to voltage yes, but it can also be overcurrent protection - it can be a lot of things
> 
> It can be voltage choking too~
> Please give more information and start with 900mV cLDO_VDDp
> actually 913 would be just fine for it ~ same 2nd gen rules apply here too, except that we get no memory "hole" because VDDG voltage is changeable



I was only using 1v for VDDG to test my infinity fabric at 1900mhz(it was fine), VDDP was on auto which is 0.9v at 3400mhz RAM.
I think I was using 0.95v VDDG and 0.9v VDDP when at 3733mhz 1:1 mode with SOC at 1.1v. My RAM is micron a die 2x16gb dual rank 3200mhzc16.


----------



## Veii

2600ryzen said:


> I was only using 1v for VDDG to test my infinity fabric at 1900mhz(it was fine), VDDP was on auto which is 0.9v at 3400mhz RAM.
> I think I was using 0.95v VDDG and 0.9v VDDP when at 3733mhz 1:1 mode with SOC at 1.1v. My RAM is micron a die 2x16gb dual rank 3200mhzc16.


i was looking your old posts, but no where you ever mentioned what board you use
Push CAD_BUS 60-20-24-24 for it 
Voltages can work , but up to board you might need to increase or lower IOD


----------



## 2600ryzen

Oh ok I'm using an asus tuf b350 board, I couldn't get stable above 3133mhz when I was on zen+.


----------



## Nguyen Vo

Hi everyone,

Wondering if anyone can help me figure out why I'm getting audio crackling/popping. This happens regardless of web browser, gaming, music player, or anything else. I used DPC latency checker and I get high latency (red bars) during high loads. I experimented with various vSOC, CLDO VDDP, & CLDO VDDG combinations, but I still get the audio crackling/popping. I have ran TM5 with 1usmus's config for 24x cycles stable and stressapptest for 4 hours stable with no errors. 


I'm running a 3900x with 16gb x 2 on a MSI x570 Meg Ace with an 5700 xt. Please see my screenshots for my timings and voltages.

*Current:*
vSOC: 1.05 
CLDO VDDP: 0.90
CLDO VDDG: 0.95
vdram: 1.45 
MemCLK: 1800 mhz
FCLK: 1800 mhz

*Alternative:* I saw on reddit, how lower voltages might increase stability and decrease the audio issues, but I still had them with this set up.
vSOC: 1.00 
CLDO VDDP: 0.80
CLDO VDDG: 0.90
vdram: 1.45 
MemCLK: 1800 mhz
FCLK: 1800 mhz

*Test 1:* -> Still get crackling and high DPC latency randomly 
vSOC: 1.1 
CLDO VDDP: 0.95
CLDO VDDG: 1.00
vdram: 1.45 
MemCLK: 1800 mhz
FCLK: 1800 mhz

*Test 2:* -> Still get crackling and high DPC latency randomly; Ram is stable, but I get more audio crackling and popping than with 1800 mhz MemCLK and FCLK. So I assume my 3900x isn't meant to run 1900.
vSOC: 1.125 
CLDO VDDP: 0.950
CLDO VDDG: 1.025
vdram: 1.45 
MemCLK: 1900 mhz
FCLK: 1900 mhz


----------



## Spectre73

Nguyen Vo said:


> Hi everyone,
> 
> Wondering if anyone can help me figure out why I'm getting audio crackling/popping. This happens regardless of web browser, gaming, music player, or anything else. I used DPC latency checker and I get high latency (red bars) during high loads. I experimented with various vSOC, CLDO VDDP, & CLDO VDDG combinations, but I still get the audio crackling/popping. I have ran TM5 with 1usmus's config for 24x cycles stable and stressapptest for 4 hours stable with no errors.


That is strange. Have not heard of such behaviour at 1800 FCLK. I only have it at 1900 FCLK, so my CPU probably can not do it. Same for you, but also at 1800 FCLK. 
A poster on reddit said, that his crackling went away after he reduced VDDP/VDDG (can not remember which one).
Maybe you can go lower on your and see if it changes something?


----------



## Veii

@Nguyen Vo please grab Y-cruncher , stresstest mode, mark all test show a confirmation screen that you pass all of them twice (2nd cycle)
Then grab prime95 , run largeFFT for actually 2hours , but just share a screenshot with Y-cruncher

If voltage missmatches, it will scream and error instantly 
Each test takes 2min, soo about 32-35min testing all of them
well you might answer faster if you error out

The rest can be windows related and not from the system~
Even more when windows update 2004 is a bugfest
You might be able to do something by disabling specific hardware access and lower system timer-clock
Which speaking of, what powerprofile are you running ?
Keep us up to date


----------



## Nguyen Vo

Spectre73 said:


> That is strange. Have not heard of such behaviour at 1800 FCLK. I only have it at 1900 FCLK, so my CPU probably can not do it. Same for you, but also at 1800 FCLK.
> A poster on reddit said, that his crackling went away after he reduced VDDP/VDDG (can not remember which one).
> Maybe you can go lower on your and see if it changes something?


Yep, I tried that, but still getting the audio issues.


----------



## Nguyen Vo

Veii said:


> @Nguyen Vo please grab Y-cruncher , stresstest mode, mark all test show a confirmation screen that you pass all of them twice (2nd cycle)
> Then grab prime95 , run largeFFT for actually 2hours , but just share a screenshot with Y-cruncher
> 
> If voltage missmatches, it will scream and error instantly
> Each test takes 2min, soo about 32-35min testing all of them
> well you might answer faster if you error out
> 
> The rest can be windows related and not from the system~
> Even more when windows update 2004 is a bugfest
> You might be able to do something by disabling specific hardware access and lower system timer-clock
> Which speaking of, what powerprofile are you running ?
> Keep us up to date


Thank you for the reply, I will try that out right now! I'm still running Windows 1903 with the Ryzen Balanced Profile.


----------



## 2600ryzen

Nguyen Vo said:


> Yep, I tried that, but still getting the audio issues.


 I get them sometime when I run high voltage RAM(1.5v+), maybe try increasing/decreasing procodt?I only need 0.85v VDDG and 0.9v VDDP to be stable at 3600mhz, maybe they could go lower too.


----------



## Gadfly

Nguyen Vo said:


> Hi everyone,
> 
> Wondering if anyone can help me figure out why I'm getting audio crackling/popping. This happens regardless of web browser, gaming, music player, or anything else. I used DPC latency checker and I get high latency (red bars) during high loads. I experimented with various vSOC, CLDO VDDP, & CLDO VDDG combinations, but I still get the audio crackling/popping. I have ran TM5 with 1usmus's config for 24x cycles stable and stressapptest for 4 hours stable with no errors.
> 
> 
> I'm running a 3900x with 16gb x 2 on a MSI x570 Meg Ace with an 5700 xt. Please see my screenshots for my timings and voltages.
> 
> *Current:*
> vSOC: 1.05
> CLDO VDDP: 0.90
> CLDO VDDG: 0.95
> vdram: 1.45
> MemCLK: 1800 mhz
> FCLK: 1800 mhz
> 
> *Alternative:* I saw on reddit, how lower voltages might increase stability and decrease the audio issues, but I still had them with this set up.
> vSOC: 1.00
> CLDO VDDP: 0.80
> CLDO VDDG: 0.90
> vdram: 1.45
> MemCLK: 1800 mhz
> FCLK: 1800 mhz
> 
> *Test 1:* -> Still get crackling and high DPC latency randomly
> vSOC: 1.1
> CLDO VDDP: 0.95
> CLDO VDDG: 1.00
> vdram: 1.45
> MemCLK: 1800 mhz
> FCLK: 1800 mhz
> 
> *Test 2:* -> Still get crackling and high DPC latency randomly; Ram is stable, but I get more audio crackling and popping than with 1800 mhz MemCLK and FCLK. So I assume my 3900x isn't meant to run 1900.
> vSOC: 1.125
> CLDO VDDP: 0.950
> CLDO VDDG: 1.025
> vdram: 1.45
> MemCLK: 1900 mhz
> FCLK: 1900 mhz


 @Nguyen Vo

Try these timings at 1900mhz, same memory kit. Set your VDDP (not CLDO_VDDP) to .900; CLDO_VDDG to .945v, SoC to 1.08v, CLDO_VDDP: .900; Proc_ODT to 53.3ohm.


----------



## Nighthog

Nguyen Vo said:


> Hi everyone,
> 
> Wondering if anyone can help me figure out why I'm getting audio crackling/popping. This happens regardless of web browser, gaming, music player, or anything else. I used DPC latency checker and I get high latency (red bars) during high loads. I experimented with various vSOC, CLDO VDDP, & CLDO VDDG combinations, but I still get the audio crackling/popping. I have ran TM5 with 1usmus's config for 24x cycles stable and stressapptest for 4 hours stable with no errors.
> 
> 
> I'm running a 3900x with 16gb x 2 on a MSI x570 Meg Ace with an 5700 xt. Please see my screenshots for my timings and voltages.
> 
> *Test 2:* -> Still get crackling and high DPC latency randomly; Ram is stable, but I get more audio crackling and popping than with 1800 mhz MemCLK and FCLK. So I assume my 3900x isn't meant to run 1900.
> vSOC: 1.125
> CLDO VDDP: 0.950
> CLDO VDDG: 1.025
> vdram: 1.45
> MemCLK: 1900 mhz
> FCLK: 1900 mhz


Have you tried setting VDDG_CCD & VDDG_IOD separate?

I know my 3800X sample doesn't want my VDDG_CCD @ 1000mv or higher. Causes issues, it's happy when it's below it only. VDDG_IOD I can push quite high if I want but most things don't need too much more but it's usually happy in the 1050-1100mv range whatever you might want to try. But it can work in the 900mv range if not pushing FCLK & Memory speed. 
VDDP I have found my setup likes it a little more on the 1000mv+ when pushing the system on IMC/FCLK etc. But normally it's Ok 900-1000mv in normal setup range.

SoC voltage needs to be enough above your VDDG. atleast 50mv above. Can cause issues if not set properly, Audio noise a point noted that can happen when not set up properly.


----------



## Nguyen Vo

@Veii I ran Prime95 and Y-cruncher as directed and got no issues at my current settings of: 
vSOC: 1.05
CLDO VDDP: 0.90
CLDO VDDG: 0.95
vdram: 1.45
MemCLK: 1800 mhz
FCLK: 1800 mhz

@2600ryzen I played around with ProcODT from 43.6-53.3 and no changes to my audio issue. Which procODT is recommended? I tried looking around, but it is hard to find information on how to determine which ProcODT to stick at.

@Gadfly I'll try those timings! What vdram did you use?
EDIT: So I tried your voltages, but it leads to very frequent audio-crackling and very high & frequent DPC latency. I used your timings with these voltages: 
vSOC: 1.125
CLDO VDDP: 0.95
CLDO VDDG: 1.05
vdram: 1.45
MemCLK: 1900 mhz
FCLK: 1900 mhz

I still get some intermittent audio crackling and high DPC latency under high load. The timings seem to be stable after running a couple cycles of TM5.

@Nighthog Yes, I tried VDDG_CCD & VDDG_IOD separate usually with VDDG_IOD being the lower voltage.


----------



## Gadfly

Nguyen Vo said:


> @Gadfly I'll try those timings! What vdram did you use?
> EDIT: So I tried your voltages, but it leads to very frequent audio-crackling and very high & frequent DPC latency. I used your timings with these voltages:
> vSOC: 1.125
> CLDO VDDP: 0.95
> CLDO VDDG: 1.05
> vdram: 1.45
> MemCLK: 1900 mhz
> FCLK: 1900 mhz
> 
> I still get some intermittent audio crackling and high DPC latency under high load. The timings seem to be stable after running a couple cycles of TM5.


 @Nguyen Vo

Do you need SoC that high? 1.07 ~ 1.08v should be more than enough. Same with VDDG, do you need 1.05v? Will 0.945v work? 

EDIT: I see that you tried the lower voltages with crackling; See below with the lower voltages:

Go into your bios and find the 1.0v SB (Southbridge) setting. On Asus boards it is right under where you set the soc and dram voltage. Set it to 1.02 - 1.05v. (My theory is that this needs to be at least as high as your VDDG IOD voltage.). 

You also want to make sure that the chipset link is manually set to Gen 4 (not auto).


----------



## Nguyen Vo

@Gadfly

Yeah it seems like I need higher SOC voltages for my IOD. I have tried increasing my SB voltage between 1.03-1.07 and it does help a little bit, but I still get high DPC latency and audio crackling. I think I might not have won the silicon lottery. 

I'll try setting the chipset link manually to Gen 4 and see if that helps. 

I wonder if I have fabric degradation. I used to run a slightly unstable 3800 mhz / 1900 fclk when I first got my 3900x. It was unstable-ish at the time, but I didn't realize it. I was running the SOC voltage at like 1.125 v at that time.


----------



## LuckyBahstard

Has anyone found themselves forced to use command rate 2T with GDM off (because of stability on 1T)? I assume yes, and if so, how did you get back to 1T? OR did you give up and go back to GDM on?

I think I'm only stable with CR2T at 3600, if I keep GDM off. I have Viper Steel 4400 2x8.

My frustrating journey or wall-bashing while revisiting my 3600 stability (with GDM off) is in the spoiler.



Spoiler



I've tried EVERYTHING (I think), with GDM off at 3600. I just stabilized 3533 with ClkDrv moved to 60.

Keeping voltages (1.5V dram, 1.125V soc, .950/1.0V vddg, 900mV vddp) w/ 3600 CL14 flat
Keeping voltages but increasing procODT from 28.2 to 30, 32, 34.3, or 60
Keeping voltages but increasing procODT to 60 and cad_bus down to 24/20/24/24 from 60/20/24/24
Voltages back down (1.45V dram, 1.05V soc, .950 vddg, 900mV vddp)
Voltages down and ClkDrv down to 40 or 24 from 60
Loosened CL14 timings (trcd_rc to 15, trdwr/twrrd to 8/2, trfc to 384)
Loosened to CL16 flat timings and loose subtimings

I was stable at 3600 CL16 through 10 cycles. Shortcut that with moving to flat 14s, now stability testing. 

But I see that 3600 CL14 w/ GDM off, CR2, has notably lower L2 and L3 cache latency in AIDA64 than its GDM On test-result-counterpart... ugh.

My machine info in my siggy.


----------



## Nighthog

LuckyBahstard said:


> Has anyone found themselves forced to use command rate 2T with GDM off (because of stability on 1T)? I assume yes, and if so, how did you get back to 1T? OR did you give up and go back to GDM on?
> 
> I think I'm only stable with CR2T at 3600, if I keep GDM off. I have Viper Steel 4400 2x8.
> 
> My frustrating journey or wall-bashing while revisiting my 3600 stability (with GDM off) is in the spoiler.
> 
> 
> 
> Spoiler
> 
> 
> 
> I've tried EVERYTHING (I think), with GDM off at 3600. I just stabilized 3533 with ClkDrv moved to 60.
> 
> Keeping voltages (1.5V dram, 1.125V soc, .950/1.0V vddg, 900mV vddp) w/ 3600 CL14 flat
> Keeping voltages but increasing procODT from 28.2 to 30, 32, 34.3, or 60
> Keeping voltages but increasing procODT to 60 and cad_bus down to 24/20/24/24 from 60/20/24/24
> Voltages back down (1.45V dram, 1.05V soc, .950 vddg, 900mV vddp)
> Voltages down and ClkDrv down to 40 or 24 from 60
> Loosened CL14 timings (trcd_rc to 15, trdwr/twrrd to 8/2, trfc to 384)
> Loosened to CL16 flat timings and loose subtimings
> 
> I was stable at 3600 CL16 through 10 cycles. Shortcut that with moving to flat 14s, now stability testing.
> 
> But I see that 3600 CL14 w/ GDM off, CR2, has notably lower L2 and L3 cache latency in AIDA64 than its GDM On test-result-counterpart... ugh.
> 
> My machine info in my siggy.


GDM:disabled is very much memory kit dependent if they can do it. All kits need slightly different settings for it to work, some are harder than others to be able to use it. 
I've tried Micron Rev.E, Rev.J & Hynix DJR in the same system.
Micron is hard to get it to do it period. Hynix DJR, was a breeze, no efforts at all. I don't know how hard Samsung kits have it but I reckon your kits need specific setting if they can do it at all.
I kinda can say A2 raw card kits need to drive clkDrvStr quite hard to make it work. My kits where all based on same A2 PCB layout.

You might need more voltage? clkDrvStr 60Ohm I've noted requires a little extra voltage when going up in speed if you have it that high, compared to 20-24, to boot/train.


----------



## TwilightRavens

Okay so my wife is currently having issues with bsod regarding RAM on her Gigabyte X470 Aorus Ultra Gaming/Ryzen 5 2600X rig with 2 x 8GB 3200MHz C14 b-die. No matter what I do its not stable at XMP, even giving SoC 1.15v and the RAM 1.5v does nothing for it. I tried setting VDDP and VDDG to 1v, DRAM termination voltage for channel a and b to half the DRAM voltage and even tried using Ryzen DRAM calc safe settings but it does nothing. I tested the kit in my X570 Taichi with my 3900X and it does not experience the same issues. Does anyone have any suggestions? Running one of the newest bios for the board and it seems to get worse the newer I go.


----------



## Darqsunscreen

Nguyen Vo had same issue with audio. try cpu soc voltage. try 1.1v or max 1.125 (my setting) that is with 3700x.


----------



## deepor

@TwilightRavens:

You need to take manual control of the ProcODT, RTT, CAD settings. Those ProcODT, RTT, CAD resistances are what's usually breaking things on Zen+ when you start getting into MHz that are a good bit higher than the officially supported max MHz (which is just 2667MHz for a 2x8GB kit).

Perhaps check out the "Ryzen DRAM calculator" tool to get some suggestions for what ProcODT, RTT, CAD values to try. It shows those recommendations in the bottom right half of the main window.

Here is a Google Docs spreadsheet with people sharing their memory overclock:

https://docs.google.com/spreadsheets/d/1dsu9K1Nt_7apHBdiy0MWVPcYjf6nOlr9CtkkfN78tSo/

That spreadsheet has columns for ProcODT, RTT, CAD. You can try stealing someone's settings from there. Make sure you only look at the "2x8GB" setups, don't look at the 4x8GB or 2x16GB setups, those people need very different ProcODT, RTT settings. Also make sure you look at the "Zen+" tab of the document, not the "Zen2" tab.


----------



## TwilightRavens

deepor said:


> @TwilightRavens:
> 
> You need to take manual control of the ProcODT, RTT, CAD settings. Those ProcODT, RTT, CAD resistances are what's usually breaking things on Zen+ when you start getting into MHz that are a good bit higher than the officially supported max MHz (which is just 2667MHz for a 2x8GB kit).
> 
> Perhaps check out the "Ryzen DRAM calculator" tool to get some suggestions for what ProcODT, RTT, CAD values to try. It shows those recommendations in the bottom right half of the main window.
> 
> Here is a Google Docs spreadsheet with people sharing their memory overclock:
> 
> https://docs.google.com/spreadsheets/d/1dsu9K1Nt_7apHBdiy0MWVPcYjf6nOlr9CtkkfN78tSo/
> 
> That spreadsheet has columns for ProcODT, RTT, CAD. You can try stealing someone's settings from there. Make sure you only look at the "2x8GB" setups, don't look at the 4x8GB or 2x16GB setups, those people need very different ProcODT, RTT settings. Also make sure you look at the "Zen+" tab of the document, not the "Zen2" tab.


Actually I think I figured it out, for some reason the stupid Gigabyte board reverted to the backup BIOS so it was running version F2 (launch bios of Zen+) so no wonder it was having issues. Though if it continues to do it I'll give that a look. I ended up flashing both the backup and main to F50 (latest as of this post) that way in case it decides to do it again it'll just be reverting to a backup with the same version.


----------



## Hequaqua

TwilightRavens said:


> Actually I think I figured it out, for some reason the stupid Gigabyte board reverted to the backup BIOS so it was running version F2 (launch bios of Zen+) so no wonder it was having issues. Though if it continues to do it I'll give that a look. I ended up flashing both the backup and main to F50 (latest as of this post) that way in case it decides to do it again it'll just be reverting to a backup with the same version.


Does that board have two bios switches? One for main/back-up, one for single/dual? 

If so....set it to single, and it shouldn't revert to the back-up bios at all. I know the Gaming 7 I'm on is that way.


----------



## happyluckbox

Does anybody know if using higher core count CPU sku with Ryzen can reduce memory stability? I recently upgraded from a 3970x to a 3990x and am experiencing memory instability with 256gb at 3200mhz. I'm thinking the motherboard just can't handle the extra strain?


----------



## TwilightRavens

Hequaqua said:


> Does that board have two bios switches? One for main/back-up, one for single/dual?
> 
> If so....set it to single, and it shouldn't revert to the back-up bios at all. I know the Gaming 7 I'm on is that way.



I’m assuming it does because when I flashed the latest it asked if I wanted to flash the backup bios too. How to switch it I have no idea as my wife doesn’t like me tinkering with it, however I may have accidentally hit it (if its on the board itself) either when I gave her my old GTX 1080 as an upgrade or when I swapped out her Spire cooler for the Prism off my 3900X. But as to where it’s located idk because I don’t really use that pc myself. I think the board is generally the same layout as the Gaming 7 that you have, I think this one just has a weaker VRM (8+3 phase) compared to yours, so wherever the switch is on your it’s likely to be in the same location.


----------



## TwilightRavens

happyluckbox said:


> Does anybody know if using higher core count CPU sku with Ryzen can reduce memory stability? I recently upgraded from a 3970x to a 3990x and am experiencing memory instability with 256gb at 3200mhz. I'm thinking the motherboard just can't handle the extra strain?



I’m thinking the IMC on your 3990X would be to blame because it may very well be a silicon lotto loser compared to the 3970X. I couldn’t see more cores realistically being the issue for RAM stability. But that’s just my two cents.

I guess it could depend also on how robust the DRAM VRM is on you specific board as the 3990X may be drawing just enough current from the vcore vrm to affect the RAM vrm, but I would highly doubt it as that would take quite a bit more power all things considered, and I just don’t see a 3990X drawing all that much more power over a 3970X since its 64 cores should be a top of the line bin.


----------



## 2600ryzen

happyluckbox said:


> Does anybody know if using higher core count CPU sku with Ryzen can reduce memory stability? I recently upgraded from a 3970x to a 3990x and am experiencing memory instability with 256gb at 3200mhz. I'm thinking the motherboard just can't handle the extra strain?



Have you tried switching some of the RAM dimms around?


----------



## Hequaqua

TwilightRavens said:


> I’m assuming it does because when I flashed the latest it asked if I wanted to flash the backup bios too. How to switch it I have no idea as my wife doesn’t like me tinkering with it, however I may have accidentally hit it (if its on the board itself) either when I gave her my old GTX 1080 as an upgrade or when I swapped out her Spire cooler for the Prism off my 3900X. But as to where it’s located idk because I don’t really use that pc myself. I think the board is generally the same layout as the Gaming 7 that you have, I think this one just has a weaker VRM (8+3 phase) compared to yours, so wherever the switch is on your it’s likely to be in the same location.


It doesn't appear that board uses any type of switches for choosing the bios. There are two leds that show which bios is currently loaded. Those are right beneath the CPU socket to the right of the LED_CPU header. Left would be Main bios(labeled M_Bios), right Back-up(labeled B_Bios).


----------



## nowarranty

Some opinions about this would really help me. I am trying to push for 3733 on an X570 aorus board but it seems my chip is just not having it with 3733. I couldn't boot 3800 even with the max voltages from dram calculator. I was able to pass 4 hours on GSAT at 3733 but I decided to try the windows HCI memtest on dram calculator and I started getting errors. 

I'm noticing I need just about the same voltages to do 3733 as I need for 3666 and the dram calculator suggests significantly less for 3600. Would I be better off aiming for 3600 with lower VDDP, VDDG, and SOC rather than the extra 33mhz IFCK from 3666? Takes me around 950/1050/1050/1100 to do 3666. 

I've been trying c14 3733 and doing c14 3666 now. The kit I have is GSKILL c15 3600 kit of samsung b die and I assume I should be able to overclock it without too much difficulty. Being new to ryzen and zen 2 chips, I'm not sure how running the higher voltages will pan out in the long run, but I would like to be more conservative with the chip.


----------



## TwilightRavens

nowarranty said:


> Some opinions about this would really help me. I am trying to push for 3733 on an X570 aorus board but it seems my chip is just not having it with 3733. I couldn't boot 3800 even with the max voltages from dram calculator. I was able to pass 4 hours on GSAT at 3733 but I decided to try the windows HCI memtest on dram calculator and I started getting errors.
> 
> I'm noticing I need just about the same voltages to do 3733 as I need for 3666 and the dram calculator suggests significantly less for 3600. Would I be better off aiming for 3600 with lower VDDP, VDDG, and SOC rather than the extra 33mhz IFCK from 3666? Takes me around 950/1050/1050/1100 to do 3666.
> 
> I've been trying c14 3733 and doing c14 3666 now. The kit I have is GSKILL c15 3600 kit of samsung b die and I assume I should be able to overclock it without too much difficulty. Being new to ryzen and zen 2 chips, I'm not sure how running the higher voltages will pan out in the long run, but I would like to be more conservative with the chip.



B-die is safe up to 1.4v as is, up to 1.5v if you have at least some airflow blowing in it.


----------



## nowarranty

TwilightRavens said:


> B-die is safe up to 1.4v as is, up to 1.5v if you have at least some airflow blowing in it.


So it seems I managed to accidentally boot 3800mhz.

I was going to just use 3600 but after seeing 3733 boot with 950/1000/1050 and high dram voltage I became encouraged to try 3800, and that worked so I'm wondering if I should just blast the dimms with voltage and set the auxiliary fan on the sticks. The case has okay airflow but I could add another fan directly on top.

Is there a mixture between higher soc voltage/lower dram voltage or does this mean for me to use 3800/1900 i'll need a lot of voltage? For 3733 I need around 1.5v and for 3600 it seems I can get by with 1.47. I am using tight timings on 3733 and 3600 from the dram calculator with my dimm timings xml imported. I could not find stability with the recommended vddg/vddp/soc from dram calculator but with some extra dram voltage it seems to pass gsat/hci without a problem. For setting 1.52 in bios it seems to be at almost 1.55 on sensors, this is where I'm too much of a dense noob to realize if it's really worth 50-100mhz in ram+fclk, but I know ryzen loves a higher fclk and I guess this is what keeps me pushing it.
Using the 3600c15 sticks, seems like 3600c14 and 3733c14 really need a lot of voltage, I am going to try 3800c15 and 3800c16 but I'm afraid this is where I start getting into the penalty zone of lower ns vs higher frequency, I don't know how to balance these trade offs realistically


----------



## TwilightRavens

nowarranty said:


> So it seems I managed to accidentally boot 3800mhz.
> 
> I was going to just use 3600 but after seeing 3733 boot with 950/1000/1050 and high dram voltage I became encouraged to try 3800, and that worked so I'm wondering if I should just blast the dimms with voltage and set the auxiliary fan on the sticks. The case has okay airflow but I could add another fan directly on top.
> 
> Is there a mixture between higher soc voltage/lower dram voltage or does this mean for me to use 3800/1900 i'll need a lot of voltage? For 3733 I need around 1.5v and for 3600 it seems I can get by with 1.47. I am using tight timings on 3733 and 3600 from the dram calculator with my dimm timings xml imported. I could not find stability with the recommended vddg/vddp/soc from dram calculator but with some extra dram voltage it seems to pass gsat/hci without a problem. For setting 1.52 in bios it seems to be at almost 1.55 on sensors, this is where I'm too much of a dense noob to realize if it's really worth 50-100mhz in ram+fclk, but I know ryzen loves a higher fclk and I guess this is what keeps me pushing it.
> Using the 3600c15 sticks, seems like 3600c14 and 3733c14 really need a lot of voltage, I am going to try 3800c15 and 3800c16 but I'm afraid this is where I start getting into the penalty zone of lower ns vs higher frequency, I don't know how to balance these trade offs realistically


My 3900X takes 1.15v SoC, 1.0v VDDG and 0.95v VDDG SoC to boot FCLK 1900MHz stable. My dual rank b-die TridentZ Neo 3600MHz 2 x 16GB kit (16-16-16-16-36) will do 3800MHz (16-16-16-16-32) with heavily tuned secondary timings and 1.452v, but I needed a fan blowing directly on them to be stable otherwise when they pass that 40C threshold they start spitting out errors in HCImemtest. Hopefully this is of some help to you.


----------



## nowarranty

TwilightRavens said:


> My 3900X takes 1.15v SoC, 1.0v VDDG and 0.95v VDDG SoC to boot FCLK 1900MHz stable. My dual rank b-die TridentZ Neo 3600MHz 2 x 16GB kit (16-16-16-16-36) will do 3800MHz (16-16-16-16-32) with heavily tuned secondary timings and 1.452v, but I needed a fan blowing directly on them to be stable otherwise when they pass that 40C threshold they start spitting out errors in HCImemtest. Hopefully this is of some help to you.


should I stop focusing on aida64 memory latency all together?
I was also using this https://notkyon.moe/ram-latency.htm, but when it comes down to 7.22 (3600 c13) vs 7.36 (3800 c14) I'll have to use high voltage in either scenario.

I just did a 500% pass on HCI with 14-15-15-30 1.53 bios (1.548 in aida) but I'm sure every step I take towards 1.6v is not desirable for 24/7. Temps reached 48/49 on the dimms with passive airflow. I'm seeing 72-74ns in aida where as 3600 was 63-65. 

Technically and realistically I benefit from a faster fclk, bandwidth and speed wise, but that's highly dependent on timings alone?

I might be trying to do too much, and while I'm a noob, I just don't want any extra performance going to waste. Plus I've already invested so many hours testing what does and doesn't work, I'm just surprised I couldnt boot 1900fclk with higher SOC voltages.


----------



## TwilightRavens

nowarranty said:


> should I stop focusing on aida64 memory latency all together?
> I was also using this https://notkyon.moe/ram-latency.htm, but when it comes down to 7.22 (3600 c13) vs 7.36 (3800 c14) I'll have to use high voltage in either scenario.
> 
> I just did a 500% pass on HCI with 14-15-15-30 1.53 bios (1.548 in aida) but I'm sure every step I take towards 1.6v is not desirable for 24/7. Temps reached 48/49 on the dimms with passive airflow. I'm seeing 72-74ns in aida where as 3600 was 63-65.
> 
> Technically and realistically I benefit from a faster fclk, bandwidth and speed wise, but that's highly dependent on timings alone?
> 
> I might be trying to do too much, and while I'm a noob, I just don't want any extra performance going to waste. Plus I've already invested so many hours testing what does and doesn't work, I'm just surprised I couldnt boot 1900fclk with higher SOC voltages.



Try adjusting timings like tFAW and tRTP, those will give a significant increase


----------



## tcclaviger

I did a thing! RAM cooling added today, and the 3rd 480 Rad. Time to start climbing over 1.5v and see what these babies can really do!

While I'm here, I took some pics of the ICs since I removed the stock spreaders. I saw speak of certain BIN codes on the chips, but I don't know which of the numbers that is.

Team Tforce Dark Pro cl14 3200 kits.

The water cooled B-Die is like 1c over water temp most of the time and 5c over water when stressing all 4 sticks.

I know the cooler temps won't directly improve performance, but it should give me a little more safe headroom to squeeze timings some more.


Current settings attached, suggestions on where to go from here?


----------



## nowarranty

MFarkha said:


> Hello all - looking for some help here.
> 
> I have a 3900x w/ the x570 Aorus Pro. I just finished overclocking my RAM using the DRAM calculator and when I went from SAFE --> FAST timings I hear the USB disconnect and immediately reconnect sound constantly whenever I run a RandomX benchmark (crypto mining) - the sounds start initially, doesn't take time for them to manifest. Initially, my impression that this was a stability issue but I can't seem to re-create this barrage of disconnect/reconnect sounds with p95, IBT, realbench, CSGO, GW2.
> 
> With the FAST settings I've ran: p95 blend --> 4 hours; realbench --> 4 hours; MEMbench --> individual threads to 400%; IBT --> Maximum 10 runs. None of these reproduce the disconnect/reconnect barrage of sounds.This only started once I went from SAFE --> Fast as the benchmark ran without this USB disconnect/reconnect sound issue with SAFE settings. What's weird is that all of my USB devices work flawless while it appears to be disconnecting and reconnecting so I suspect that this is happening on the microsecond level.
> 
> Is there a specific time or voltage that impacts the USB controller the most? I'm presently at 1.46 Volts (samsung b-die) with 1.12 SOC, VDDG 1.075 and VDDP at 1.1. Thank you!
> 
> Edit: I downloaded a USB viewer tool and I have an external HD that keeps reconnecting and disconnecting. A clue I suppose.


Now having this problem with XMP enabled or with manual settings. I'm not sure what to do, I've tried a higher soc, vddg, and vddp. 
:wth:
I've tried the 60/40 emulation for usb in bios. I can't think or find anything else, any suggestions would help


----------



## happyluckbox

tcclaviger said:


> I did a thing! RAM cooling added today, and the 3rd 480 Rad. Time to start climbing over 1.5v and see what these babies can really do!
> 
> While I'm here, I took some pics of the ICs since I removed the stock spreaders. I saw speak of certain BIN codes on the chips, but I don't know which of the numbers that is.
> 
> Team Tforce Dark Pro cl14 3200 kits.
> 
> The water cooled B-Die is like 1c over water temp most of the time and 5c over water when stressing all 4 sticks.
> 
> I know the cooler temps won't directly improve performance, but it should give me a little more safe headroom to squeeze timings some more.
> 
> 
> Current settings attached, suggestions on where to go from here?


wow that is really nice. mind if i ask what waterblock for the ram?


----------



## Gadfly

Quick result updates:

Memory is using stock RGB heat spreaders, and just airflow from $5 fan blowing on them.


----------



## Gadfly

tcclaviger said:


> I did a thing! RAM cooling added today, and the 3rd 480 Rad. Time to start climbing over 1.5v and see what these babies can really do!
> 
> While I'm here, I took some pics of the ICs since I removed the stock spreaders. I saw speak of certain BIN codes on the chips, but I don't know which of the numbers that is.
> 
> Team Tforce Dark Pro cl14 3200 kits.
> 
> The water cooled B-Die is like 1c over water temp most of the time and 5c over water when stressing all 4 sticks.
> 
> I know the cooler temps won't directly improve performance, but it should give me a little more safe headroom to squeeze timings some more.
> 
> 
> Current settings attached, suggestions on where to go from here?


So... pretty much the same temps as air cooling the dimms?


----------



## Veii

Gadfly said:


> Quick result updates:
> Simple Fan blowing air on the memory keeps the memory below 40'C


Great result :thumb:
There is nothing to be done at this, except maybe pushing FCLK higher
Maybe you can get tRC -1 or -2 & lower tRFC in steps of 4 as a value
Or somehow magically drop tRDWR -1 (doubt)
Pretty much the lowest you can run unless you get CL12 or CL13 without GDM to work at 2T :specool:


----------



## Gadfly

Veii said:


> There is nothing to be done at this, except maybe pushing FCLK higher


That is next. 

Getting Proc_ODT down to 30 ohm and SoC down to 1.08v should help push fclk a little higher, even if it just a small bclk bump.


----------



## nowarranty

has anyone ever experienced this? https://community.amd.com/thread/244682 were they able to fix it through loosening memory overclocks?


----------



## Gadfly

nowarranty said:


> has anyone ever experienced this? https://community.amd.com/thread/244682 were they able to fix it through loosening memory overclocks?


Never seen that issue.


----------



## Veii

nowarranty said:


> has anyone ever experienced this? https://community.amd.com/thread/244682 were they able to fix it through loosening memory overclocks?


Never seen it either, doesn't sound like a memory issue but rather a heat VRM issue
if cores lock down to a specific speed, nearly always it's because FIT module triggers
be it because of unstable current, clock stretching, VRM overheating, overcurrent - who knows
But memory shouldn't be the culprit for FIT safety-trigger


----------



## yann3804

Hi all!

I bought a new PC recently. Specs are: Ryzen 3300x on X570 Tomahawk MSI board (bought this board because of apparently really good VRMs). 32Gb of RAM: 2x16Gb dual rank G.Skill FlareX 3200CL14 (F4-3200C14D-32GFX).

Looking for a long lasting OC. I'm trying to go from 3200CL14 to 3600CL14, but might try 3400CL14 instead if too unstable. 

So, I imported my report from Taiphoon Burner into DRAM Calculator 1.7.3 as seen in the uploaded screenshot. 
I'm trying to run the SAFE preset. 
I inputted every timing into the BIOS, aswell as each recommended voltages (1.05V SOC in override mode, VDDG 1.0V, VDDP 0.95V) and GDM on, BGS off, etc. Literally every recommended timing on the calculator I've put into the BIOS.

However, the SAFE preset will not POST unless VDimm is at least 1.41V. with 1.41V I can enter Windows but MEMBench is full of errors under one minute. 1.44V seems stable - however I want a long lasting OC, so trying to keep it below ~1.41V.

So, I either need to 1. Loosen timings, or 2. Decrease memory frequency from 3600 to ... 3400? 
Thing is, I've hardly found any info on how to properly loosen timings. Sure, I could just do +1 to primary timings, but that seems very amateur. Is there any guide to how to this? Or if someone could tell me exactly what to loosen, that'd be very nice of them.

If anyone wants to help I'd greatly appreciate.

Thanks to anyone reading.


----------



## fingon82

1.41v isnt much for b die,i would leave it there

I woud actually try to tighten latencies,esp secondary ones with a try fom fast preset, if you have the time for testing


----------



## yann3804

fingon82 said:


> 1.41v isnt much for b die,i would leave it there
> 
> I woud actually try to tighten latencies,esp secondary ones with a try fom fast preset, if you have the time for testing


no no... 1.41V only POST (my PC otherwise won't turn on, i had to clear cmos), but stable memtest I need at least 1.44V as far as i tried...


----------



## fingon82

Still tolerable. I would tolerate up to 1.45v. Just tighten some latencies some more and thats it

There are factory kits working at 1.45v,its not much


----------



## PuffyArgos

yann3804 said:


> no no... 1.41V only POST (my PC otherwise won't turn on, i had to clear cmos), but stable memtest I need at least 1.44V as far as i tried...


I have a 16gb Team Group kit (8gb x2) 3600 cl14 b-die that has 1.45v in the XMP. It won't post on anything less either.


----------



## rares495

PuffyArgos said:


> I have a 16gb Team Group kit (8gb x2) 3600 cl14 b-die that has 1.45v in the XMP. It won't post on anything less either.


Yeah, there are a few kits with 1.5V XMP profiles as well.


----------



## Yuke

I gave up trying to get GDM = Off on my Dual Rank B-Die Kit.

So i instead went for balanced 3800Mhz settings...maybe at some point i will try out an "Extreme Profile" with GDM still on...but dunno how hard you can drive a dual rank kit (that seems to be decently binned)


VSOC 1.1V
DRAM-V 1.39V
VDDG 1.05V
VDDP 0.95V

(Basically what the DRAM calculator recommends for a well binned B-Die kit but with lower TRFC)

So far im at Karhu 2000% without errors.


----------



## 2600ryzen

nowarranty said:


> has anyone ever experienced this? https://community.amd.com/thread/244682 were they able to fix it through loosening memory overclocks?



I had that on my 2600 where the cores would get locked to 600mhz for some reason, can't remember what I did to fix it maybe disable some cpu protection but I did fix it.
edit: think it had something to do with overcurrent protection, OCP.


----------



## PuffyArgos

Hey guys, newbie here. I only became interested in RAM OCs a few week ago and have spent the time since reading and tweaking and read and tweaking. I was hoping I could elicit some comments or suggestions on my current timings to get my latency down a bit more.


3950x @4000mhz all-core PBO disabled
16gb (2x8gb) 3600mhz 14-14-14-14-28-42 @1.45v
CAD_Bus 24-20-24-24ohm ProcODT 40ohm
Asus ROG Strix x570-F


I appreciate any thoughts, thanks guys.


----------



## Dollar

Yuke said:


> I gave up trying to get GDM = Off on my Dual Rank B-Die Kit.
> 
> So i instead went for balanced 3800Mhz settings...maybe at some point i will try out an "Extreme Profile" with GDM still on...but dunno how hard you can drive a dual rank kit (that seems to be decently binned)
> 
> 
> VSOC 1.1V
> DRAM-V 1.39V
> VDDG 1.05V
> VDDP 0.95V
> 
> (Basically what the DRAM calculator recommends for a well binned B-Die kit but with lower TRFC)
> 
> So far im at Karhu 2000% without errors.



Why do you have your SCL timings at different values? Did you notice better performance that way?


----------



## Yuke

Dollar said:


> Why do you have your SCL timings at different values? Did you notice better performance that way?


Ugh, no, just slipped i guess. it should be 4 4


----------



## yann3804

Quick question:

Is it better to follow this guide https://github.com/integralfx/MemTestHelper/blob/master/DDR4 OC Guide.md
or simply use the DRAM Calculator?

which gives better performance?


----------



## rares495

yann3804 said:


> Quick question:
> 
> Is it better to follow this guide https://github.com/integralfx/MemTestHelper/blob/master/DDR4 OC Guide.md
> or simply use the DRAM Calculator?
> 
> which gives better performance?


First use the calculator, then follow the guide but once you get past a certain point they'll both become useless to you. The only thing that will help you is your previous experience with your particular memory kit. 

But yeah, they're great tools for beginners.


----------



## jfrob75

Yuke said:


> I gave up trying to get GDM = Off on my Dual Rank B-Die Kit.
> 
> So i instead went for balanced 3800Mhz settings...maybe at some point i will try out an "Extreme Profile" with GDM still on...but dunno how hard you can drive a dual rank kit (that seems to be decently binned)
> 
> 
> VSOC 1.1V
> DRAM-V 1.39V
> VDDG 1.05V
> VDDP 0.95V
> 
> (Basically what the DRAM calculator recommends for a well binned B-Die kit but with lower TRFC)
> 
> So far im at Karhu 2000% without errors.


 I believe I have the same memory kit and I am able to run at the following:


VSOC 1.125V
DRAM 1.52V
VDDG 1.05V
VDDP 1.00V


----------



## 2600ryzen

Anyone have any ideas on running with GDM off 1T/2T? My computer freezes if I try to run higher than 3200mhz with GDM disabled though I know other people with Micron Rev e can run GDM off 1T at 3800mhz. Can this be limited by your motherboard? I only have an asus b350.


edit: I just checked and the guy who had it working had B2 RAW card and I have B0


Reference Raw Card:B0 (8 layers)


----------



## rares495

2600ryzen said:


> Anyone have any ideas on running with GDM off 1T/2T? My computer freezes if I try to run higher than 3200mhz with GDM disabled though I know other people with Micron Rev e can run GDM off 1T at 3800mhz. Can this be limited by your motherboard? I only have an asus b350.
> 
> 
> edit: I just checked and the guy who had it working had B2 RAW card and I have B0
> 
> 
> Reference Raw Card:B0 (8 layers)


B0 should run tighter than B2 so it should be easier for you to achieve GDM off.

But don't trust Thaiphoon. Post a photo showing the side of a module.


----------



## 2600ryzen

rares495 said:


> B0 should run tighter than B2 so it should be easier for you to achieve GDM off.
> 
> But don't trust Thaiphoon. Post a photo showing the side of a module.



Here you go.


----------



## TwilightRavens

yann3804 said:


> no no... 1.41V only POST (my PC otherwise won't turn on, i had to clear cmos), but stable memtest I need at least 1.44V as far as i tried...



I have my b-die at 1.452v daily but it needed active cooling over it to be stable.


----------



## rares495

2600ryzen said:


> Here you go.


B2 confirmed. 

Thaiphoon is confused as usual.


----------



## Yuke

jfrob75 said:


> I believe I have the same memory kit and I am able to run at the following:
> 
> 
> VSOC 1.125V
> DRAM 1.52V
> VDDG 1.05V
> VDDP 1.00V
> 
> 
> View attachment 357232


Thats nice to know! I will reserve the extreme profile for when i have a CPU worth pushing my RAM.


----------



## nick name

Anyone looking for a G.Skill 3600C15 2X8GB kit? Newegg has them at the lowest I think I've ever seen.

https://www.newegg.com/g-skill-16gb-288-pin-ddr4-sdram/p/N82E16820232306


----------



## johnadams2

*Unstable Quad-Channel Memory (Errors) with ASRock X399 Taichi + 1950X + 2x16GB G.Skill Flare-X (F4-3200C14D-16GFX)*

My setup is not stable at the advertised 3200Mhz levels when used in Quad Channel mode. Latest BIOS, everything. HCI MemTest shows 2-3 errors 200% coverage in. 4 sticks for 32GB in total. In BIOS, set eveything to Auto and Stable. Did not overclock.

I had to bring the speed down a notch (3166Mhz) and set voltage at 1.355 in order to not have any errors.

Anyone else had this issue? It's annoying because these errors, even though just a handful, causes random crashes within a week.

Here's parts of the HCI MemTest logs showing the error:

======== Starting new MemTest session ========
MemTest PRO 7.0 (c) 2019, HCI Design (http://hcidesign.com/memtest)
NOTE: greater than 100% coverage is possible. Each 100% indicates a thorough testing of all allocated RAM, however, intermittent errors may take multiple 100% cycles to be detected.

[21728] Thu Jun 25 19:18:02 2020 >> Test started. Allocated 2281 MB of memory for testing.
[1436] Thu Jun 25 19:27:29 2020 >> Status Update: MB; 20.4% Coverage, 0 Errors. 1739 MB/s
...
[21728] Thu Jun 25 20:18:02 2020 >> Status Update: MB; 111.7% Coverage, 0 Errors. 1675 MB/s
[21728] Thu Jun 25 20:24:20 2020 >> Memory error found copying between 0xde20fb60, 0x3bbaf90c, difference =20000000
[1436] Thu Jun 25 20:27:29 2020 >> Status Update: MB; 130.3% Coverage, 0 Errors. 2168 MB/s
[21728] Thu Jun 25 20:28:02 2020 >> Status Update: MB; 129.7% Coverage, 1 Errors. 1785 MB/s
...
[23488] Thu Jun 25 20:37:57 2020 >> Status Update: MB; 146.1% Coverage, 0 Errors. 1887 MB/s
[21728] Thu Jun 25 20:38:02 2020 >> Status Update: MB; 148.8% Coverage, 1 Errors. 1987 MB/s
...
[21728] Thu Jun 25 20:54:41 2020 >> Memory error found copying between 0xde91190c, 0x3c2b17f8, difference =20000000
[21728] Thu Jun 25 20:58:02 2020 >> Status Update: MB; 187.4% Coverage, 2 Errors. 1665 MB/s
...
[3676] Thu Jun 25 21:47:40 2020 >> Status Update: MB; 269.9% Coverage, 0 Errors. 1734 MB/s
[22144] Thu Jun 25 21:47:43 2020 >> Status Update: MB; 269.3% Coverage, 0 Errors. 1686 MB/s
[13676] Thu Jun 25 21:47:48 2020 >> Status Update: MB; 274.4% Coverage, 0 Errors. 1719 MB/s
[22544] Thu Jun 25 21:47:48 2020 >> Status Update: MB; 267.9% Coverage, 0 Errors. 1665 MB/s
[22676] Thu Jun 25 21:47:52 2020 >> Status Update: MB; 269.8% Coverage, 0 Errors. 1585 MB/s
[23488] Thu Jun 25 21:47:57 2020 >> Status Update: MB; 269.1% Coverage, 0 Errors. 1706 MB/s
[21728] Thu Jun 25 21:48:02 2020 >> Status Update: MB; 274.7% Coverage, 2 Errors. 1740 MB/s
[21708] Thu Jun 25 21:52:14 2020 >> Test finished. 0 errors found.

[184] Thu Jun 25 21:52:14 2020 >> Test finished. 0 errors found.

[21728] Thu Jun 25 21:52:14 2020 >> Test finished. 2 errors found.

[22144] Thu Jun 25 21:52:15 2020 >> Test finished. 0 errors found.

[3676] Thu Jun 25 21:52:15 2020 >> Test finished. 0 errors found.

[22544] Thu Jun 25 21:52:15 2020 >> Test finished. 0 errors found.

[22676] Thu Jun 25 21:52:15 2020 >> Test finished. 0 errors found.

[13676] Thu Jun 25 21:52:15 2020 >> Test finished. 0 errors found.

[23488] Thu Jun 25 21:52:15 2020 >> Test finished. 0 errors found.

[1436] Thu Jun 25 21:52:15 2020 >> Test finished. 0 errors found.


----------



## Joseph Mills

Is there a chart that shows what needs to change for the different errors in TM5?
I'm hitting 9, 10, and 14 after an hour and a half testing on TM5.

(calling on @Veii for this one)


----------



## Gadfly

fingon82 said:


> Still tolerable. I would tolerate up to 1.45v. Just tighten some latencies some more and thats it
> 
> There are factory kits working at 1.45v,its not much


For B-Die 1.5v is perfectly acceptable for 24/7 use. I have a g.skilll memory kit rated at 1.5v out of the box. 

You just have to watch the dimm temps, make sure you keep them below 50'C. even a small amount of airflow makes a big difference. With just some air from a cheap fan I dropped dimm temps from 51'C to below 40'C at 1.49v.


----------



## Veii

Joseph Mills said:


> Is there a chart that shows what needs to change for the different errors in TM5?
> I'm hitting 9, 10, and 14 after an hour and a half testing on TM5.
> 
> (calling on @Veii for this one)


No one bothered to make a chart so far 
But just open the MT.cfg 
Most of them make sense after some testing time
9,10 are burst tests, mostly related to vDIMM
14 what they call mirror move , is cloning data between banks
Can be mostly related to tFAW, tRRDS, tWTRS

Logically viewed
It choked on a burst test and then didn't have enough voltage left for a mirror copy 
Try stepping down vDIMM a tiny bit 
Burst test size 4Mb is only voltage related, as memory shouldn't have enough time to take time to (p)recharge, on such small dataset
soo most of the time it's just a voltage crash
8mb can be relate to timings choking it, same as 16mb will relate to issues with delays
32mb is quite big, that mostly relates to an actual timeout or tRFC issue 
Can be tRCD related too

Your current pattern indicates just a burst testing crash
+1 or -1 step on vdimm 
If nothing works play with lower procODT and so also lower vSOC with it


----------



## Veii

PuffyArgos said:


> Hey guys, newbie here. I only became interested in RAM OCs a few week ago and have spent the time since reading and tweaking and read and tweaking. I was hoping I could elicit some comments or suggestions on my current timings to get my latency down a bit more.
> 
> 3950x @4000mhz all-core PBO disabled
> 16gb (2x8gb) 3600mhz 14-14-14-14-28-42 @1.45v
> CAD_Bus 24-20-24-24ohm ProcODT 40ohm
> Asus ROG Strix x570-F
> I appreciate any thoughts, thanks guys.


Hello, 
You actually already made good progress
There are just tiny bugs you couldn't have thought off before

VDDCR SOC runs at 1.363v
What ryzen master shows is actually accurate
That happens because your cLDO_VDDG is already at 1.1v while only the cLDO_VDDP is at 900mV
Soo the board thinks
"Oh he used 200mV stepping, let's continue to use it for stability sake"
That's why you end up at near 1.3v SOC 

Please enable UncoreOC mode inside AMD OVERCLOCKING
Afterwards, drop procODT lower and fix vSOC to 1.1v 
Usually 1.1v should work well with 34-36,9
It might be fine for 30ohm but will be a bit much for 28ohm
* in case your board even allows to run 28 instead of 30ohm procODT

About your timings, really nothing to complain
You might want to push tRTP down to 6, and lower tRDWR to 7 / tWRRD 1
In order to get that 2T away, you will need to increase ClkDrvStrengh a tiny bit
SLC both of them should be able to go down to 3 instead 4
but that work is for a another day

As you run procODT 40ohm, hitting 1900FCLK will be far away
Focus so far on lowering every voltage except vDIMM 
Which speaking of, please give it a bit more 
1.46v shouldn't bother even bad ICs
You run tRCD 14 on 3600MT/s which is not bad at all
But A2 PCB-kits love voltage
Either voltage or high ClkDrvStrengh impedance under CAD_BUS

Your work for now:
- tRTP 6, tRDWR 7, 
- vDIMM >1.46, 
- procODT <36.9ohm, vSOC not higher than 1.125, better 1.1v
- ClkDrvStrengh >24ohm
- focus on going to 1867/1900 FCLK after you lowered every voltage


----------



## PuffyArgos

Veii said:


> Hello,
> You actually already made good progress
> There are just tiny bugs you couldn't have thought off before
> 
> VDDCR SOC runs at 1.363v
> What ryzen master shows is actually accurate
> That happens because your cLDO_VDDG is already at 1.1v while only the cLDO_VDDP is at 900mV
> Soo the board thinks
> "Oh he used 200mV stepping, let's continue to use it for stability sake"
> That's why you end up at near 1.3v SOC
> 
> Please enable UncoreOC mode inside AMD OVERCLOCKING
> Afterwards, drop procODT lower and fix vSOC to 1.1v
> Usually 1.1v should work well with 34-36,9
> It might be fine for 30ohm but will be a bit much for 28ohm
> * in case your board even allows to run 28 instead of 30ohm procODT
> 
> About your timings, really nothing to complain
> You might want to push tRTP down to 6, and lower tRDWR to 7 / tWRRD 1
> In order to get that 2T away, you will need to increase ClkDrvStrengh a tiny bit
> SLC both of them should be able to go down to 3 instead 4
> but that work is for a another day
> 
> As you run procODT 40ohm, hitting 1900FCLK will be far away
> Focus so far on lowering every voltage except vDIMM
> Which speaking of, please give it a bit more
> 1.46v shouldn't bother even bad ICs
> You run tRCD 14 on 3600MT/s which is not bad at all
> But A2 PCB-kits love voltage
> Either voltage or high ClkDrvStrengh impedance under CAD_BUS
> 
> Your work for now:
> - tRTP 6, tRDWR 7,
> - vDIMM >1.46,
> - procODT <36.9ohm, vSOC not higher than 1.125, better 1.1v
> - ClkDrvStrengh >24ohm
> - focus on going to 1867/1900 FCLK after you lowered every voltage


This is perfect, exactly the type of feedback I was hoping for. I really appreciate your thoughts.

I only use Ryzen Master to capture my timings for screen shots. All timings/voltages are managed in BIOS. I didn't notice RM was reporting SOC voltage of 1.36. That's mildly terrifying as I've been running this 24/7 for about 21 days. HWiNFO has been reporting 1.1v this whole time (what I use on a daily basis to track voltages and temps). Any chance it was RM that thought "Oh he used 200mV stepping, let's continue to use it for stability sake" while the board was actually sticking to 1.1v on all other boots?

Looks like I have a few things to work on anyway. I look forward to reporting back with results. Thanks again for the help.


----------



## rares495

nick name said:


> Anyone looking for a G.Skill 3600C15 2X8GB kit? Newegg has them at the lowest I think I've ever seen.
> 
> https://www.newegg.com/g-skill-16gb-288-pin-ddr4-sdram/p/N82E16820232306


MAAAAAN that price is so GOOOOD. Holy balls. High-tier B-die for just $125. Amazing!


----------



## FranZe

nick name said:


> Anyone looking for a G.Skill 3600C15 2X8GB kit? Newegg has them at the lowest I think I've ever seen.
> 
> https://www.newegg.com/g-skill-16gb-288-pin-ddr4-sdram/p/N82E16820232306


They dont deliver to me


----------



## hmeh

*Trying to get 3800C14 stable*

On the left I have what I'm stable with at 1.44V (53.6 latency), on the right I have what I'm trying to get stable, it's my first pass at 3800C14 (and currently has similar latency, which is a little surprising). Until I went up to 1.52V I couldn't get it to work at all. 

I've run TM5 Extreme for a bit over an hour with no errors, but just got an error after 3 passes on Karhu, so it's not there yet.

I have a Gigabyte Aorus Master x570 and my 1.52V reports at 1.536-1.548V in HWInfo. 

For one, I'm gathering that I shouldn't be too worried about running at 1.52V, yeah? 

Next, should I even be bothering with this? Am I actually going to be able to get latency lower enough to make any sort of difference?

Lastly, any tips for either getting to CL14 stable or for what to do next on my CL16 config?

I've been completely unable to get GDM disabled at CL16 so I could try CL15. Actually, at one point I managed to destroy my windows install. Fun.


----------



## tcclaviger

Gadfly said:


> tcclaviger said:
> 
> 
> 
> I did a thing! RAM cooling added today, and the 3rd 480 Rad. Time to start climbing over 1.5v and see what these babies can really do!
> 
> While I'm here, I took some pics of the ICs since I removed the stock spreaders. I saw speak of certain BIN codes on the chips, but I don't know which of the numbers that is.
> 
> Team Tforce Dark Pro cl14 3200 kits.
> 
> The water cooled B-Die is like 1c over water temp most of the time and 5c over water when stressing all 4 sticks.
> 
> I know the cooler temps won't directly improve performance, but it should give me a little more safe headroom to squeeze timings some more.
> 
> 
> Current settings attached, suggestions on where to go from here?
> 
> 
> 
> So... pretty much the same temps as air cooling the dimms?
Click to expand...

Nope, air cooled dims at 1.52 volts running TM5 for example heats them up a good bit, around 45-50c.

People take for granted ram doesn't generate heat.

People are wrong.


----------



## SpecChum

tcclaviger said:


> Nope, air cooled dims at 1.52 volts running TM5 for example heats them up a good bit, around 45-50c.
> 
> People take for granted ram doesn't generate heat.
> 
> People are wrong.


And that's with decent air flow!

My b-die gets to over 56C when running TM5, and that's at 1.4V with the side panel off.


----------



## hmeh

hmeh said:


> Next, should I even be bothering with this? Am I actually going to be able to get latency lower enough to make any sort of difference?


I just tested my current CL16 timings against just increasing VDDR to 1.52 and tCL to 14 and my AIDA64 numbers were not inspiring. They're extremely close to the CL16 timings.

CL16: 60236 57592 64082 63.6
CL14: 60278 57682 64161 63.6

Given that I had to back off several timings to not make CL14 super unstable, I don't think I'll even be able to make those benches hold at CL14, so likely CL16 is best for me? Does that seem right? 

If so, what should I tweak next on my CL16?


----------



## nick name

rares495 said:


> MAAAAAN that price is so GOOOOD. Holy balls. High-tier B-die for just $125. Amazing!


Newegg also has a couple other G.Skill 3200C14 2X8GB kits on sale for USD $105 and the TridentZ kit is USD $109. That is some of the cheapest Samsung b-die I have ever seen.


----------



## rares495

nick name said:


> Newegg also has a couple other G.Skill 3200C14 2X8GB kits on sale for USD $105 and the TridentZ kit is USD $109. That is some of the cheapest Samsung b-die I have ever seen.


Yeah, fast memory is getting really cheap. Well...3200 kits are not the best bins but still. Most of them should do 3800 CL16. Not bad for $100. Although for just $20 more you get the 3600C15 and it's so gooooood.


----------



## nick name

rares495 said:


> Yeah, fast memory is getting really cheap. Well...3200 kits are not the best bins but still. Most of them should do 3800 CL16. Not bad for $100. Although for just $20 more you get the 3600C15 and it's so gooooood.


I got drunk and ordered another 3600C15 kit. I'm gonna compare it to the kit I have and then combine them to see what I can do at 32GB and then decide what to do after that. Maybe sell one kit or if 32GB overclocking goes well -- keep both kits.


----------



## rares495

nick name said:


> I got drunk and ordered another 3600C15 kit. I'm gonna compare it to the kit I have and then combine them to see what I can do at 32GB and then decide what to do after that. Maybe sell one kit or if 32GB overclocking goes well -- keep both kits.


4x8 overclocking is not gonna go so well but I hope you get at least CL 15.


----------



## Keith Myers

rares495 said:


> 4x8 overclocking is not gonna go so well but I hope you get at least CL 15.


I have two TridentZ 3200CL14 16GB kits for a 4X8GB configuration. I have 3600CL14 Fast timings stable on a C7H mobo. Didn't have any luck pushing them further with half an afternoon attempting higher. But good enough for BOINC crunching.


----------



## TwilightRavens

Ended up getting a Ryzen 5 3600 to replace my wife's 2600X since I figured that was what was being picky about the RAM, I was kinda wrong, it just did not like running 3200MHz C14 (XMP profile) and instead I ended up overclocking it to 3600MHz with DRAM calc fast timings with a bit of extra voltage than what it calls for. So far it's running like a champ.


----------



## tcclaviger

TwilightRavens said:


> Ended up getting a Ryzen 5 3600 to replace my wife's 2600X since I figured that was what was being picky about the RAM, I was kinda wrong, it just did not like running 3200MHz C14 (XMP profile) and instead I ended up overclocking it to 3600MHz with DRAM calc fast timings with a bit of extra voltage than what it calls for. So far it's running like a champ.


X470 Asus board? I've seen a bunch of people who have a hole with 3200 divider, but 1 step below and above worked.


----------



## tcclaviger

nick name said:


> rares495 said:
> 
> 
> 
> Yeah, fast memory is getting really cheap. Well...3200 kits are not the best bins but still. Most of them should do 3800 CL16. Not bad for $100. Although for just $20 more you get the 3600C15 and it's so gooooood.
> 
> 
> 
> I got drunk and ordered another 3600C15 kit. I'm gonna compare it to the kit I have and then combine them to see what I can do at 32GB and then decide what to do after that. Maybe sell one kit or if 32GB overclocking goes well -- keep both kits.
Click to expand...

Woohoo. Things to do to kill time 😛

I think I finally got my kit 4x8 3200CL14 stable at 14-14-14-14-32-46-1t at 3800 today, pic below, its definitely possible with 4 dims on a C7H. Working on bringing tRAS and tRC down some.

Came down to "don't be yellow, throw more voltage" lol. 1.535 seems to have done the trick.

Good luck with 32gb, seems to not be holding me back much, hopefully you have the same experience.

I'm very tempted order a couple kits myself and see if 3600-15 will play nicely with my 2700x system, because the Hynix CJR in it now is poopoo.


----------



## hmeh

tcclaviger said:


> I think I finally got my kit 4x8 3200CL14 stable at 14-14-14-14-32-46-1t at 3800 today, pic below, its definitely possible with 4 dims on a C7H. Working on bringing tRAS and tRC down some.
> 
> Came down to "don't be yellow, throw more voltage" lol. 1.535 seems to have done the trick.


Very nice. Could you share your AIDA64 results with that? 

Is 1.535V what you set in or what HWINFO reports?

Also, if you could share your ProcODT/clk/rtt that'd be helpful.

I've been trying to get C14 stable as well, but my initial forays into it didn't show much of any speed improvement, so it didn't seem worth the voltage bump. Did you find it increased your benches much?

If you wouldn't mind taking a look at my posts below and see if you have any suggestions, I'd appreciate it.

https://www.overclock.net/forum/10-...memory-stability-thread-391.html#post28521700
https://www.overclock.net/forum/10-...memory-stability-thread-391.html#post28522086


----------



## rares495

tcclaviger said:


> Woohoo. Things to do to kill time 😛
> 
> I think I finally got my kit 4x8 3200CL14 stable at 14-14-14-14-32-46-1t at 3800 today, pic below, its definitely possible with 4 dims on a C7H. Working on bringing tRAS and tRC down some.
> 
> Came down to "don't be yellow, throw more voltage" lol. 1.535 seems to have done the trick.
> 
> Good luck with 32gb, seems to not be holding me back much, hopefully you have the same experience.
> 
> I'm very tempted order a couple kits myself and see if 3600-15 will play nicely with my 2700x system, because the Hynix CJR in it now is poopoo.


Not bad. Which modules are those?


----------



## tcclaviger

As requested, these modules, 2 sets, sequential serial numbers:

TDPGD416G3200HC14ADC01

1.535 set in bios, 1.53 via DMM.

Currently hitting it with Ycruncher to test fclk and verify stability. EDIT: wewt passing ycruncher and everything else so calling this good now. 

PS: holy hell ycruncher is an intense test... Hit every limit, TDC 105, EDC 145, PPT 185. Haven't seen another test suite that can peg all 3.

Will update with RM screenshot for other data. EDIT: Added, the procdot etc are all on auto 😮, it works better than dram calc values for some reason.

Adjusted back to 32 from 30. Saw no gains with 30 so don't see a reason to push a tighter timing. The only repeatable difference I could find was a regression in Ryzen membench time from 100.6 to 101.3, so 32 it is.


----------



## nick name

tcclaviger said:


> Woohoo. Things to do to kill time 😛
> 
> I think I finally got my kit 4x8 3200CL14 stable at 14-14-14-14-32-46-1t at 3800 today, pic below, its definitely possible with 4 dims on a C7H. Working on bringing tRAS and tRC down some.
> 
> Came down to "don't be yellow, throw more voltage" lol. 1.535 seems to have done the trick.
> 
> Good luck with 32gb, seems to not be holding me back much, hopefully you have the same experience.
> 
> I'm very tempted order a couple kits myself and see if 3600-15 will play nicely with my 2700x system, because the Hynix CJR in it now is poopoo.


Really? Straight 14s? I'm confounded how some folks can do that. I get instant errors. 

I was running my 2700X at 3600MHz 14-15-14-14-30-44 and tight everything else.


----------



## tcclaviger

I I have no idea why this works, because from what I understand I should be forced to back of to 14-15-14 or 14-15-15.


----------



## nick name

tcclaviger said:


> I I have no idea why this works, because from what I understand I should be forced to back of to 14-15-14 or 14-15-15.


Well as long as it works. Let me know if you stumble across something that indicates why it works for you that isn't just silicon quality.


----------



## hmeh

Thanks for posting, @tcclaviger

Are you on 1900 memclk or 1833? RM shows 1833, but AIDA shows 1900. 

That's a great latency reading you ended up with, hope it proves stable.


----------



## TwilightRavens

tcclaviger said:


> X470 Asus board? I've seen a bunch of people who have a hole with 3200 divider, but 1 step below and above worked.


Nah it was the Gigabyte X470 Aorus Ultra Gaming, craptastic board but meh, at least it finally works.



nick name said:


> Really? Straight 14s? I'm confounded how some folks can do that. I get instant errors.
> 
> I was running my 2700X at 3600MHz 14-15-14-14-30-44 and tight everything else.


Yeah I'm the same way because I can only get my kit to 16-16-16-16-32 at 3800MHz, but that may be because dual rank kits might not time the same as opposed to single rank in my case, or maybe because i'm just not comfortable going over 1.45v.


----------



## tcclaviger

hmeh said:


> Thanks for posting, @tcclaviger
> 
> Are you on 1900 memclk or 1833? RM shows 1833, but AIDA shows 1900.
> 
> That's a great latency reading you ended up with, hope it proves stable.


1833 strap with raised bclk to bring it up to 3800/1900.

It changes nothing for my memory performance vs going straight 1900 strap with 100bclk, but it does give my CPU a nice uplift in performance since Asus boards can disable bclk multiplier compensation by the CPU, so you end up with higher boost clocks (4450 all core, 4730ish single core vs 100 bclk giving about 4250/4550).

Has been well behaved this far, time, will tell ofc.


----------



## SpecChum

tcclaviger said:


> 1833 strap with raised bclk to bring it up to 3800/1900.
> 
> It changes nothing for my memory performance vs going straight 1900 strap with 100bclk, but it does give my CPU a nice uplift in performance since Asus boards can disable bclk multiplier compensation by the CPU, so you end up with higher boost clocks (4450 all core, 4730ish single core vs 100 bclk giving about 4250/4550).
> 
> Has been well behaved this far, time, will tell ofc.


There's something weird here, aside from latency, my results are on par with yours but I'm only at 3800C16 @ 1.35v

You're not being bottlenecked somewhere are you?


----------



## Karagra

SpecChum said:


> There's something weird here, aside from latency, my results are on par with yours but I'm only at 3800C16 @ 1.35v
> 
> You're not being bottlenecked somewhere are you?


That is not even the same score xD


----------



## TwilightRavens

So I've got a pair of Hynix MFR's 3200MHz 16-18-18-18-38 iirc laying around, how well would that likely scale with voltages and such, aside from the IMC being a factor is there any scaling to be had with MFR kits, or is it kinda a crapshoot? I have never really overclocked any other DDR4 besides b-die and rev-e so anyone that has experience with MFR kits is welcomed for an opinion.


----------



## SpecChum

Karagra said:


> That is not even the same score xD


Which bit? We seem to be within error of each other baring latency.

I guess I just expected C14 vs C16 to be further apart.


----------



## rares495

SpecChum said:


> Which bit? We seem to be within error of each other baring latency.
> 
> I guess I just expected C14 vs C16 to be further apart.


Latency is the only thing that matters in Aida64.


----------



## pipes

I wouldn't want to be a spoilsport or even be a mentor to anything, everyone does what they want, now I can't find anyone who said that 1.5 time for b-die chips was a safe voltage. Yes it is but in terms of absolute maximums, looking for the datasheets, they give reason but I degrade it is mentioned in the notes just below the Absolute maximum table


----------



## SpecChum

rares495 said:


> Latency is the only thing that matters in Aida64.


I wouldn't say only, but I agree in principal it's the most important, I was just seeing the other results and expected them to be further apart I guess.


----------



## rares495

SpecChum said:


> I wouldn't say only, but I agree in principal it's the most important, I was just seeing the other results and expected them to be further apart I guess.


Yeah, the only thing. Bandwidth varies way too much run to run to even look at. Plus there's a limit set by the 3800 MT/s bottleneck. 60800 MB/s is the theoretical limit so with a 3900X you can start approaching that even with sh t-tier memory. The copy result is not even worth looking at because aida pulls it out of thin air (again, the limit is 60800 MB/s at 3800 MT/s so how does Aida measure 64000 MB/s?)

Latency-wise 63.9ns vs 62.5ns is a huge difference.


----------



## pipes

rares495 said:


> Yeah, the only thing. Bandwidth varies way too much run to run to even look at. Plus there's a limit set by the 3800 MT/s bottleneck. 60800 MB/s is the theoretical limit so with a 3900X you can start approaching that even with sh t-tier memory. The copy result is not even worth looking at because aida pulls it out of thin air (again, the limit is 60800 MB/s at 3800 MT/s so how does Aida measure 64000 MB/s?)
> 
> 
> 
> Latency-wise 63.9ns vs 62.5ns is a huge difference.


My limite with a 3700x is 58000 MB/S with atriot vipera 4000 MHz cl16

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## rares495

pipes said:


> My limite with a 3700x is 58000 MB/S with atriot vipera 4000 MHz cl16
> 
> Inviato dal mio MI 9 utilizzando Tapatalk


60800 MB/s is the theoretical limit but not everyone will get there.

I couldn't reach 59000 with my 3700X either. Same thing with the 3600.


----------



## pipes

rares495 said:


> Yeah, I couldn't reach 59000 with my 3700X either. Same thing with the 3600.


More later Will post my result with aida64

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## pipes

rares495 said:


> 60800 MB/s is the theoretical limit but not everyone will get there.
> 
> 
> 
> I couldn't reach 59000 with my 3700X either. Same thing with the 3600.


It's a good result

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## pipes

rares495 said:


> 60800 MB/s is the theoretical limit but not everyone will get there.
> 
> I couldn't reach 59000 with my 3700X either. Same thing with the 3600.


this is my result


----------



## 2600ryzen

pipes said:


> this is my result



Looks like you're not running in 1:1 mode. Underclock your RAM to 3800mhz and your scores will be much better.


----------



## rares495

pipes said:


> this is my result


Yes, you need to stop at 3733/3800 to run in 1:1 mode. Going over that adds 8-10ns of latency.


----------



## pipes

I hace try with 4000 MHz yo set cl15 but it's nota accepted...very strange

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## pipes

rares495 said:


> Yes, you need to stop at 3733/3800 to run in 1:1 mode. Going over that adds 8-10ns of latency.


My northbridge is different from tour, is 1900 MHz setting from BIOS but aida64 read 998...any idea?

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## rares495

pipes said:


> My northbridge is different from tour, is 1900 MHz setting from BIOS but aida64 read 998...any idea?
> 
> Inviato dal mio MI 9 utilizzando Tapatalk


You need to run MEMCLK 1:1 UCLK. There must be some setting in the DRAM section of the BIOS. I don't know what it's called.


----------



## pipes

Sorry corrector of the phone, fclk is read differently from what is set in the bios


Inviato dal mio MI 9 utilizzando Tapatalk


----------



## Galaxypfm

I need more memory on AM4, what configuration 2x32GB or 4x16GB will be better OC? I want effects like 2x8GB. Memory is Gskill on Bdie bones.


----------



## rares495

Galaxypfm said:


> what configuration 2x32GB or 4x16GB will be better OC? I want effects like 2x8GB


That's not gonna happen.


----------



## Galaxypfm

rares495 said:


> That's not gonna happen.


I will not get the same OC results as for 2x8GB, so which option will give approximate results?


----------



## rares495

Galaxypfm said:


> I will not get the same OC results as for 2x8GB, so which option will give approximate results?


None. More memory = slower memory. Much slower. You might not hit 3600.


----------



## Galaxypfm

rares495 said:


> None. More memory = slower memory. Much slower. You might not hit 3600.


Currently on x370 Zen1 I have 3466 14 14 14 28, I thought I would get similar results. on 2x16GB will be the same problem as on 4x16GB?


----------



## rares495

Galaxypfm said:


> Currently on x370 Zen1 I have 3466 14 14 14 28, I thought I would get similar results. on 2x16GB will be the same problem as on 4x16GB?


2x16 and 2x32 are better than 4x16.


----------



## Galaxypfm

rares495 said:


> 2x16 and 2x32 are better than 4x16.


So it's best not to pack in 4 banks, only 2? Gskill doesn't have 2x32GB, only Crucial remains 
I thought I would buy 2x16GB to 2x8GB and I'll have 48GB.


----------



## rares495

Galaxypfm said:


> So it's best not to pack in 4 banks, only 2? Gskill doesn't have 2x32GB, only Crucial remains
> I thought I would buy 2x16GB to 2x8GB and I'll have 48GB.


That's like having 4x16. Don't do that.


----------



## Galaxypfm

rares495 said:


> That's like having 4x16. Don't do that.


What 2x32GB bdie will you recommend?

On 4 banks max 3600 with what timings and which zen?


----------



## pipes

More performance with 3800/1900 but i think my problem is fclk the no set at 1900 when put the RAM at 4000mhz

Inviato dal mio MI 9 utilizzando Tapatalk


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## rares495

Galaxypfm said:


> What 2x32GB bdie will you recommend?
> 
> On 4 banks max 3600 with what timings and which zen?


I can't find 2x32 B-die kits. Weird.



pipes said:


> More performance with 3800/1900 but i think my problem is fclk the no set at 1900 when put the RAM at 4000mhz
> 
> Inviato dal mio MI 9 utilizzando Tapatalk


Of course it won't be 1900. In 2:1 mode, the FCLK=UCLK but UCLK=MEMCLK/2 => 4000/2=2000 & 2000/2=1000 MHz FCLK


----------



## pipes

And for RAM at 3800/1900 go to 1900 MHz under aida64

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## pipes

I an instabile with this setting on two memtest
I have increase soc DRAM and vddg voltages









Inviato dal mio MI 9 utilizzando Tapatalk


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## Galaxypfm

1. So there is no 2x32GB, it remains 2x16GB interesting what OC we will get at 2x16 + 2x8?

2. 2x16GB will be similar in oc as 2x8GB because it will be on 2 banks?

3. Will there be a difference in OC between F4-3600C16D-32GTZR VS F4-F4-4000C19D-32GTZR, choosing 4000 instead of 3600 will give us the opportunity to better tighten timings?


----------



## rares495

Galaxypfm said:


> 1. So there is no 2x32GB, it remains 2x16GB interesting what OC we will get at 2x16 + 2x8?
> 
> 2. 2x16GB will be similar in oc as 2x8GB because it will be on 2 banks?
> 
> 3. Will there be a difference in OC between F4-3600C16D-32GTZR VS F4-F4-4000C19D-32GTZR, choosing 4000 instead of 3600 will give us the opportunity to better tighten timings?


2x16 should be dual rank. Crucial sells some expensive SR 2x16 kits but they're all Micron Rev. E not B-die. 

3600C16 should be better.


----------



## Galaxypfm

rares495 said:


> 2x16 should be dual rank. Crucial sells some expensive SR 2x16 kits but they're all Micron Rev. E not B-die.
> 
> 3600C16 should be better.


So higher clock speed doesn't mean better OC at the start? since you write that the 3600 I gave will be better, is it about timings 19?


----------



## Keith Myers

Galaxypfm said:


> 1. So there is no 2x32GB, it remains 2x16GB interesting what OC we will get at 2x16 + 2x8?
> 
> 2. 2x16GB will be similar in oc as 2x8GB because it will be on 2 banks?
> 
> 3. Will there be a difference in OC between F4-3600C16D-32GTZR VS F4-F4-4000C19D-32GTZR, choosing 4000 instead of 3600 will give us the opportunity to better tighten timings?


Yes, there is. And from G.Skill too with B-dies. They have their Trident Z RGB DC kits that are 32GB sticks. They are double height to fit all the chips and are specific to certain motherboards for compatibility.
https://www.gskill.com/products/1/165/296/Trident-Z-RGB-DC


----------



## Galaxypfm

Keith Myers said:


> Yes, there is. And from G.Skill too with B-dies. They have their Trident Z RGB DC kits that are 32GB sticks. They are double height to fit all the chips and are specific to certain motherboards for compatibility.
> https://www.gskill.com/products/1/165/296/Trident-Z-RGB-DC


Yes, I know, but this product is probably discontinued.
The manufacturer's website also has information that they work only with selected motherboards "Trident Z RGB DC modules are only compatible on the following ASUS motherboards:
"ROG Z390 MAXIMUS XI APEX, ROG MAXIMUS XI GENE, and ROG STRIX Z390-I GAMING." I have a Gigabyte x370 K7.


----------



## tcclaviger

So after a couple of days playing games etc, I found that my limit is FCLK.

While 3798/1898 was memory and CPU stable, FCLK would kick an error eventually, verified by lowering the fclk strap one notch and running it asynchronously without any problems.

Strangely, no stability testing or benchmarking caught or would trigger it, only gaming and general use.

So, as a daily compromise, raised BCLK back to CPU stability limit, and forced to back off fclk/memory strap 1 notch to 3739/1868. 

At least I know the memory is capable of 3800 with straight 14s now. 

Regarding voltage: there are 1.5v XMP2 gskill kits and ton of 1.45v kits, if 1.5v degrades it, it'll be rather slow, even slower if kept cool, so pick your voltage base on your situation. 

Mini ITX with 2 fans... Probably dont use 1.53....
28 fan 3x480 loop with water cooled ram in air conditioned office...why not?


----------



## Keith Myers

Galaxypfm said:


> Yes, I know, but this product is probably discontinued.
> The manufacturer's website also has information that they work only with selected motherboards "Trident Z RGB DC modules are only compatible on the following ASUS motherboards:
> "ROG Z390 MAXIMUS XI APEX, ROG MAXIMUS XI GENE, and ROG STRIX Z390-I GAMING." I have a Gigabyte x370 K7.


Why I mentioned very limited application because of the motherboard requirements.

So, why not the Corsair Vengeance LPX 32GB sticks using the Samsung 32GB A-dies.

https://www.corsair.com/us/en/Categories/Products/Memory/VENGEANCE-LPX/p/CMK32GX4M1D3000C16#tab-tech-specs

https://www.newegg.com/corsair-32gb-288-pin-ddr4-sdram/p/N82E16820236568


----------



## Galaxypfm

Keith Myers said:


> Why I mentioned very limited application because of the motherboard requirements.
> 
> So, why not the Corsair Vengeance LPX 32GB sticks using the Samsung 32GB A-dies.
> 
> https://www.corsair.com/us/en/Categories/Products/Memory/VENGEANCE-LPX/p/CMK32GX4M1D3000C16#tab-tech-specs
> 
> https://www.newegg.com/corsair-32gb-288-pin-ddr4-sdram/p/N82E16820236568


Sorry, I had to overlook this. The framework you provided are on the new A-die bones which will be the successor to the B-die? do you also think that filling up 4 banks is an OC problem?


----------



## Keith Myers

Galaxypfm said:


> Sorry, I had to overlook this. The framework you provided are on the new A-die bones which will be the successor to the B-die? do you also think that filling up 4 banks is an OC problem?


Absolutely no idea of the overclockability of these new A-dies. Haven't seen them mentioned anywhere in OCN threads.

I think the consensus is that filling all four slots on a Ryzen motherboard is a bad idea, no matter the density. Has to do with signal integrity.

I was simply offering suggestions on how you could get to your desired 64GB capacity on just two sticks. There are solutions contrary to your original assertion there were no 2 X 32GB kits.


----------



## deepor

Galaxypfm said:


> Sorry, I had to overlook this. The framework you provided are on the new A-die bones which will be the successor to the B-die? do you also think that filling up 4 banks is an OC problem?



About using two or four sticks, that's a question about the wiring of your motherboard. The motherboard memory slots wiring can be "daisy chain topology" or "T-topology". Boards are normally built using "daisy chain". The "T-topology" boards do better with four sticks, while "daisy chain" is better with two sticks.

I'll try to explain what this topology stuff is about:

"Daisy chain" means that the wiring from the CPU to the memory slots is like this:



Code:


+-----+
|     |------> memory slot A1
|     |         |
| CPU |         \------> memory slot A2
|     |
|     |------> memory slot B1
+-----+         |
                \------> memory slot B2

And "T-topology" means that the wiring is like this:



Code:


+-----+     /-----> memory slot A1
|     |-----+
|     |     \-----> memory slot A2
| CPU |
|     |     /-----> memory slot B1
|     |-----+
+-----+     \-----> memory slot B2

With daisy chain the wiring goes to the recommended two slots for memory stick 1 and 2, and then from there continues to the slots for stick 3 and 4. When you use a memory kit with four sticks, the first two sticks have a shorter distance to the CPU than sticks 3 and 4. When you use a memory kit with just two sticks, then with daisy chain you enjoy the short the distance for your sticks. If you use a memory kit with four sticks, then you will be limited because of the extra distance for sticks 3 and 4.

With T-topology the wiring for all sticks is the same length. It doesn't matter if you use a memory kit with two or four sticks. But when using just two sticks, then the wiring is longer than on a daisy chain board. The T-topology boards are very rare nowadays from what I heard.


----------



## nick name

I just got my new G.Skill 3600C15 delivered today. Time to see if it's better or worse (or the same) than my current G.Skill 3600C15 kit. And then to see how well both kits work together. Cracking open a beer and getting to work. 

The stickers on the new kit say 2020 June. Nothing like freshly picked b-die. It's so nice when they're in season. They smell delightful.


----------



## nick name

nick name said:


> I just got my new G.Skill 3600C15 delivered today. Time to see if it's better or worse (or the same) than my current G.Skill 3600C15 kit. And then to see how well both kits work together. Cracking open a beer and getting to work.
> 
> The stickers on the new kit say 2020 June. Nothing like freshly picked b-die. It's so nice when they're in season. They smell delightful.


Ok. So far this kit is far superior. Definitely the newer/better PCB. And it seems to take less voltage for the exact same timings -- 1.5V for the old kit and 1.45V for the new kit with the same timings. What I am testing now is -- old kit 14-16-14-14, but new kit hasn't thrown any errors at 14-14-14-14 at the same speed. Old kit threw errors IMMEDIATELY and the new kit is 6 minutes in without error at 14-14-14-14 at 1.45V.

Sorry I'm kinda live blogging this.


----------



## Galaxypfm

Why F4-3600C16D-32GTZR will be better than F4-4000C19D-32GTZR what is the reason? since it is said that higher clock speeds of the manufacturer give better OC.


----------



## TwilightRavens

Galaxypfm said:


> Why F4-3600C16D-32GTZR will be better than F4-4000C19D-32GTZR what is the reason? since it is said that higher clock speeds of the manufacturer give better OC.


They are both b-die but the 3600 C16 is likely a better bin, but really I'd get whichever is cheaper as they'll be within a percent of each other. Higher stock XMP speeds doesn't always mean higher bin, it just means it'll run that speed, for all we know it could only do 3600 C17 for example, or it could do C13 its really a dice roll, but generally if you are looking at C19 b-die go for the 4133, 4266 or even 4400 stuff (all should still be C19) as those are far superior bins to 4000 C19. Anything after 4400 rev e is the best option as its clocks can't be beat even though the timings are less than ideal.


----------



## nick name

So kinda fun thing with the new 3600C15 kit. It can do speed better than my old 3600C15 kit. The old kit could easily do 4400MHz 18-20-18-18 and the new kit does 4400MHz 16-18-16-16 with tight timings. And the old kit would almost never POST at 4600MHz with craptastic timings while the new kit will easily POST 4600MHz 18-20-18-18 and tight timings.


----------



## Galaxypfm

TwilightRavens said:


> They are both b-die but the 3600 C16 is likely a better bin, but really I'd get whichever is cheaper as they'll be within a percent of each other. Higher stock XMP speeds doesn't always mean higher bin, it just means it'll run that speed, for all we know it could only do 3600 C17 for example, or it could do C13 its really a dice roll, but generally if you are looking at C19 b-die go for the 4133, 4266 or even 4400 stuff (all should still be C19) as those are far superior bins to 4000 C19. Anything after 4400 rev e is the best option as its clocks can't be beat even though the timings are less than ideal.


Now I understand a little more. Only 2x16GB modules are not higher than 4000, they are Royal, but they have uneven timing and are unavailable. Which Gskill Neo do you use? Because I see that you had no problem with oc.


----------



## TwilightRavens

Galaxypfm said:


> Now I understand a little more. Only 2x16GB modules are not higher than 4000, they are Royal, but they have uneven timing and are unavailable. Which Gskill Neo do you use? Because I see that you had no problem with oc.


This is the exact kit I have: https://www.newegg.com/g-skill-32gb-288-pin-ddr4-sdram/p/N82E16820232860

Its for sure b-die, there are others that ar 16-19-19, I think those are rev e.


----------



## dansi

No offense, but what the point of pushing up memory frequency if IF cnnot catch up and incurring performance penalty?


----------



## nick name

dansi said:


> No offense, but what the point of pushing up memory frequency if IF cnnot catch up and incurring performance penalty?


I'm not running it daily that fast. Just seeing what the RAM and CPU can do. And while there is a penalty going that fast -- the penalty with the new kit (and its better timings) is only 3.5ns ~ 4ns. Oh, it also takes a lot of voltage.


----------



## mongoled

nick name said:


> So kinda fun thing with the new 3600C15 kit. It can do speed better than my old 3600C15 kit. The old kit could easily do 4400MHz 18-20-18-18 and the new kit does 4400MHz 16-18-16-16 with tight timings. And the old kit would almost never POST at 4600MHz with craptastic timings while the new kit will easily POST 4600MHz 18-20-18-18 and tight timings.


Nice catch


----------



## Rawson

I have B die that came rated at 16-18-18-18-38-56 (or very close), same stock speed as my hynix A die. both kit are 3200mhz. my hynix will OC quite nicely to 14-17-17-17 and heavily modified subtimings no problem. whereas my samsung will reject any timing control really. it will post @3266 whereas my hynix wont go above 3200. i thought this was quite interesting. regardless, i want to overclock this samsung kit to atleast my hynix A kits level. is this possible - or is this simply substandard b die?


----------



## PuffyArgos

Rawson said:


> I have B die that came rated at 16-18-18-18-38-56 (or very close), same stock speed as my hynix A die. both kit are 3200mhz. my hynix will OC quite nicely to 14-17-17-17 and heavily modified subtimings no problem. whereas my samsung will reject any timing control really. it will post @3266 whereas my hynix wont go above 3200. i thought this was quite interesting. regardless, i want to overclock this samsung kit to atleast my hynix A kits level. is this possible - or is this simply substandard b die?


What voltage are you running on the b-die kit? b-die shines on it's near linear relationship between voltage and frequency.


----------



## Galaxypfm

1. I will buy F4-3600C16D-32GTZR, I hope they will do the same as F4-4000C19D-32GTZR because I don't know if it makes sense to pay extra to these 4000?

2. There will be a higher infinity Fabric R4000 limit, is this true and how much?


----------



## DeusM

Hi everybody this is more an announcement as i learned something new today!


If you have 4 sticks of RAM it *ABSOLUTELY* matters which order they are in, i don't know why but here is what i went through.




Two nights ago i was pushing the ram so i can see what it can do, for fun i tried 4000mhz with IF at 2000 and the computer gave me the old black screen and not booting.


So as usual i removed the CMOS batttery and it did not reset for some reason. So i removed it again and Reseated the ram. i thought while i do that i can check what PCB layout i have.


After taking photos of the PCB layout i put the ram back in and didnt take care to put them in exactly the same positions. First boot into bios to load my Stable 3800 cl16 profile and it would not work. i wondered why?? i tried my 3733cl16 stable clock and again IT WOULD NOT BOOT!


After 2 days of testing and frustration i realised that the sticks were in random order. 



Today i tried 6 Different combinations of which ram stick goes where. and it made a HUGE difference to how many errors i would receive in the stress test. 



This may be known to other people but i never thought of this before since my kit is a 32gb kit and came with the 4 sticks in 1 package.




Im guessing this might have too do with the x570 gaming edge WIFI daisy chain.




I posted this in another thread but i thought it would be good for people to see!


----------



## rares495

Rawson said:


> I have B die that came rated at 16-18-18-18-38-56 (or very close), same stock speed as my hynix A die. both kit are 3200mhz. my hynix will OC quite nicely to 14-17-17-17 and heavily modified subtimings no problem. whereas my samsung will reject any timing control really. it will post @3266 whereas my hynix wont go above 3200. i thought this was quite interesting. regardless, i want to overclock this samsung kit to atleast my hynix A kits level. is this possible - or is this simply substandard b die?


Hynix AFR (A-die) is trash and even tuned will probably be worse than this also trash B-die kit that you own. Not that you can tune much. It's AFR...

The B-die kit could be pushed into the good B-die territory with more voltage.


----------



## hazium233

Rawson said:


> I have B die that came rated at 16-18-18-18-38-56 (or very close), same stock speed as my hynix A die. both kit are 3200mhz. my hynix will OC quite nicely to 14-17-17-17 and heavily modified subtimings no problem. whereas my samsung will reject any timing control really. it will post @3266 whereas my hynix wont go above 3200. i thought this was quite interesting. regardless, i want to overclock this samsung kit to atleast my hynix A kits level. is this possible - or is this simply substandard b die?


Just made a post about this in the calc thread, but first step is to double check that it is really even B-die by looking on the label. Is this a GSkill kit?

If it is, you can look at the code starting with 042 on the label, and if it ends in 10C, it is C-die.

Corsair 16-18-18-36 3200 kits that have version number 4.32 are C-die.

C-die does not behave like B-die at all, and so attempting to scale it with voltage will be frustrating.


----------



## 1TM1

DeusM said:


> If you have 4 sticks of RAM it *ABSOLUTELY* matters which order they are in


One possibility is heat. Some sticks get hotter than others. If you set hot ones on the inside between others you get errors. I have a thermal camera and saw one of four sticks (without T sensors) gets hot, so I set it in the outer socket closest to the fan to chill. Some sticks have sensors which can be read with HWinfo. If not, maybe you can use an infrared thermometer to check temperatures one at a time. Better yet just add a fan on case top to blow air on RAM.

see https://www.overclock.net/forum/attachment.php?attachmentid=352550&d=1591483582


----------



## KedarWolf

I'm pretty happy with this.










brb, getting AIDA benchmark.


----------



## Yuke

KedarWolf said:


> I'm pretty happy with this.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> brb, getting AIDA benchmark.


seems nice, what voltage?


----------



## rares495

KedarWolf said:


> I'm pretty happy with this.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> brb, getting AIDA benchmark.


Bruh, you used to be close to me in terms of timings. W-T-F happened to your RAM?


Spoiler


----------



## KedarWolf

rares495 said:


> Bruh, you used to be close to me in terms of timings. W-T-F happened to your RAM?
> 
> 
> Spoiler


I'm using 2x16GB, and my other timings were not quite stable in TM5.

So is 100% stable now, only diff is tRFC and tRAS I need to stay stable.


----------



## rares495

KedarWolf said:


> I'm using 2x16GB, and my other timings were not quite stable in TM5.
> 
> So is 100% stable now, only diff is tRFC and tRAS I need to stay stable.


That tRC is weird. Should be 40-42.

tWRRD should be 1.

tRCDWR that low doesn't help in my experience.


----------



## KedarWolf

Yuke said:


> seems nice, what voltage?


I'm running 1.46v in BIOS RAM, .900 VDDP and .950 and 1.000 VDDG's, .730v on the VREF's, 1.15v on the VOC though, a bit high, but I'm okay with that.


----------



## KedarWolf

rares495 said:


> That tRC is weird. Should be 40-42.
> 
> tWRRD should be 1.
> 
> tRCDWR that low doesn't help in my experience.


Yeah, I'm cheating on timings a bit but to match tRC with tRFC I need 45

tWRRD at 1 will not boot.

I get really good latency with tRCDWR at 10 and it's 2 below tWR which is good.


----------



## rares495

KedarWolf said:


> Yeah, I'm cheating on timings a bit but to match tRC with tRFC I need 45
> 
> tWRRD at 1 will not boot.
> 
> I get really good latency with tRCDWR at 10 and it's 2 below tWR which is good.


But you're out of sync because some of those timings are random. 

tRP of 14 => tRAS = tCL(14) + tRP(14) + tBL(2) = 30 => tRC = tRP(14) + tRAS(30) = 44 but 42 might work. That means tRFC 1/2/4 should be 252 - 187 - 115 which I'm sure your kit can do.


----------



## KedarWolf

rares495 said:


> But you're out of sync because some of those timings are random.
> 
> tRP of 14 => tRAS = tCL(14) + tRP(14) + tBL(2) = 30 => tRC = tRP(14) + tRAS(30) = 44 but 42 might work. That means tRFC 1/2/4 should be 252 - 187 - 115 which I'm sure your kit can do.


No, my kit gets TM5 errors at 252. I need to do 270 to get rid of them. Yes, I know the timings are not quite synced but latency at 61.9ns is really good for 2x16GB I feel.


----------



## Yuke

KedarWolf said:


> I'm running 1.46v in BIOS RAM, .900 VDDP and .950 and 1.000 VDDG's, .730v on the VREF's, 1.15v on the VOC though, a bit high, but I'm okay with that.


Well..lol i guess. I tried out 14 16 16 16 28 44 288 at 1.5V (readout) and im still getting a bluescreen when trying to boot into windows. Guess there goes the dream for my "extreme settings".


----------



## DeusM

1TM1 said:


> DeusM said:
> 
> 
> 
> If you have 4 sticks of RAM it *ABSOLUTELY* matters which order they are in
> 
> 
> 
> One possibility is heat. Some sticks get hotter than others. If you set hot ones on the inside between others you get errors. I have a thermal camera and saw one of four sticks (without T sensors) gets hot, so I set it in the outer socket closest to the fan to chill. Some sticks have sensors which can be read with HWinfo. If not, maybe you can use an infrared thermometer to check temperatures one at a time. Better yet just add a fan on case top to blow air on RAM.
> 
> see https://www.overclock.net/forum/attachment.php?attachmentid=352550&d=1591483582
Click to expand...


Definitely is not heat, that's a 80mm fan that I got rid of for a 120mm. They do not go over 35 degrees. Even after 4 hours of stress testing


----------



## KedarWolf

rares495 said:


> But you're out of sync because some of those timings are random.
> 
> tRP of 14 => tRAS = tCL(14) + tRP(14) + tBL(2) = 30 => tRC = tRP(14) + tRAS(30) = 44 but 42 might work. That means tRFC 1/2/4 should be 252 - 187 - 115 which I'm sure your kit can do.


This just passed 25 cycles.


----------



## KedarWolf

rares495 said:


> That tRC is weird. Should be 40-42.
> 
> tWRRD should be 1.
> 
> tRCDWR that low doesn't help in my experience.


yeah, I'm cheating on timings a bit but to match tRC with tRFC I need 45

tWRRD at 1 will not boot.

I get really good latency with tRCDWR at 10 and it's 2 below tWR which is good. 

tRCDWR at 10 might have been autocorrecting. At 12 I get this.


----------



## rares495

KedarWolf said:


> This just passed 25 cycles.


Nice! Bring tRCDWR up to 14 and then see if you can do 8 tRDWR and 1 tWRRD. That should perform better than the current 9-4. If it doesn't work, try 8-2 or at least 8-4.


----------



## KedarWolf

rares495 said:


> Nice! Bring tRCDWR up to 14 and then see if you can do 8 tRDWR and 1 tWRRD. That should perform better than the current 9-4. If it doesn't work, try 8-2 or at least 8-4.


8-2 works.


----------



## nick name

I never see anyone post about it, but does anyone ever play with high speeds like 4400MHz or 4600MMHz? I'm curious to know what voltages others are using at those speeds.


----------



## glnn_23

nick name said:


> I never see anyone post about it, but does anyone ever play with high speeds like 4400MHz or 4600MMHz? I'm curious to know what voltages others are using at those speeds.


A while back I ran RamTest for an hour 4578c18 @ 1.43v on an Asus Impact.


----------



## nick name

glnn_23 said:


> A while back I ran RamTest for an hour 4578c18 @ 1.43v on an Asus Impact.


How tight were the other timings?


----------



## glnn_23

nick name said:


> How tight were the other timings?


4578c18 18 19 18 36 54 1T. 
GDM Disabled.


----------



## nick name

glnn_23 said:


> 4578c18 18 19 18 36 54 1T.
> GDM Disabled.


Sorry. I meant more the rest of them. But that 1T is impressive. I can't hit speed without 2T.

How did the test go? Errors?


----------



## glnn_23

nick name said:


> Sorry. I meant more the rest of them. But that 1T is impressive. I can't hit speed without 2T.
> 
> How did the test go? Errors?


Post #2989 on page 299
No errors.
Moving forward I would change some of these timings I used back then. For example Trfc 2 & 4 are on auto.


----------



## nick name

glnn_23 said:


> Post #2989 on page 299
> No errors.
> Moving forward I would change some of these timings I used back then. For example Trfc 2 & 4 are on auto.


Sweet. Thank you.


----------



## kratosatlante

nick name said:


> I never see anyone post about it, but does anyone ever play with high speeds like 4400MHz or 4600MMHz? I'm curious to know what voltages others are using at those speeds.


in my case only test in old bios, 2801 , new bios dont work(or me fail in some config) 4000+


----------



## Eder

Hey everyone, I would like to share my latest 4x8gb tuning. I've got two F4-3200CL14D-16GFX kits, my first kit is the 01h revision and my second kit is the 21h revision. It's hard to remove the heathspreaders but they are very likely A1 PCB and both perform the same.

With the latest ComboAM4v2 1.0.0.2 these are my timings. This time I tried to follow the relations between timings from al the enlightment @Veii is giving us.

My very stable config (8h gaming+20 rounds TM5):








CLDO_VDDP=0.900 
VDDG_CCD =0.950
VDDG_IOD=0.975
VSOC = 1.075
VDIM= 1.42
procODT = 43.6 RTT 7/0/5 40/20/24/24

Now trying this config (TM5 passed, no realworld test yet)








CLDO_VDDP=0.900 
VDDG_CCD =0.950
VDDG_IOD=0.975
VSOC = 1.075
VDIM= 1.44
procODT= 43.6 RTT 7/0/5 40/20/24/24

What do you guys think? Lower SCL values would be fantastic but I haven't got any succes so far. I'm using a MSI X570 Unify, case with a lot of airflow and a small fan on the memory so there is room to try tweak some more. Any suggestions?


----------



## Streetdragon

KedarWolf said:


> 8-2 works.


Impressive. Just Impressive!
i cant reach your latenz^^
Thats the limit that i can do


----------



## nick name

Streetdragon said:


> Impressive. Just Impressive!
> i cant reach your latenz^^
> Thats the limit that i can do


Wow. 

Do you have CPU Cache set to Enabled in Karhu?


----------



## rares495

Streetdragon said:


> Impressive. Just Impressive!
> i cant reach your latenz^^
> Thats the limit that i can do



You can pass it with an allcore OC. 


Your memory is really good btw.


----------



## Streetdragon

Enabled yep


----------



## nick name

Streetdragon said:


> Enabled yep


What are your voltages?


----------



## Streetdragon

1.5V in Bios. 1.512 Readout.
Dimms run 13° over Ambient. So i can keep them cool


----------



## nick name

Streetdragon said:


> 1.5V in Bios. 1.512 Readout.
> Dimms run 13° over Ambient. So i can keep them cool


Damn that's a nice kit of RAM.


----------



## pipes

Streetdragon said:


> 1.5V in Bios. 1.512 Readout.
> 
> Dimms run 13° over Ambient. So i can keep them cool


It's voltage limit for b-die if u hace b-die samsung

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## kratosatlante

nick name said:


> I never see anyone post about it, but does anyone ever play with high speeds like 4400MHz or 4600MMHz? I'm curious to know what voltages others are using at those speeds.


reflashing 3103 and trying again, best i get this, cant past 4600 whatever if try or Voltage, 4400 if 1867 seems stable, with IF1900 not at all, 4533 if 1867 may be with a lot of work, IF 1900 not, cl16 and 1.515 voltage


----------



## FranZe

nick name said:


> Wow.
> 
> Do you have CPU Cache set to Enabled in Karhu?


When its set to default is it enabled then?


----------



## Nizzen

pipes said:


> It's voltage limit for b-die if u hace b-die samsung
> 
> Inviato dal mio MI 9 utilizzando Tapatalk


1.5v vdram is not the limit for 24/7 

If you keep b-die under 45-50c, 1.6-1.65v will not throw any errors


----------



## pipes

I would also read the datasheets ...


----------



## rares495

pipes said:


> I would also read the datasheets ...



Datasheets are for stock operation. We are overclocking here.


----------



## nick name

FranZe said:


> When its set to default is it enabled then?


No, I'm pretty sure you have to set it to Enabled.


----------



## pipes

rares495 said:


> Datasheets are for stock operation. We are overclocking here.


What can change with or without oc? This Is not a 24/7 thread?

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## Yuke

Any recommendations for improvement? Dual Rank B-Die kit.

I need to up Voltage from 1.38V to 1.51V for CL14, sadly, so not sure if its worth it.


----------



## Streetdragon

Yuke said:


> Any recommendations for improvement? Dual Rank B-Die kit.
> 
> I need to up Voltage from 1.38V to 1.51V for CL14, sadly, so not sure if its worth it.


Worth? not really no. But fun to push the sticks to its limit(in "ok" volts)

https://www.overclock.net/forum/10-...memory-stability-thread-402.html#post28535988


----------



## Gadfly

tcclaviger said:


> Nope, air cooled dims at 1.52 volts running TM5 for example heats them up a good bit, around 45-50c.
> 
> People take for granted ram doesn't generate heat.
> 
> People are wrong.


I agree, but why so hot with air cooling? Just a small fan blowing on the dimms will but you below 40'C at only 1.52


----------



## tcclaviger

Gadfly said:


> I agree, but why so hot with air cooling? Just a small fan blowing on the dimms will but you below 40'C at only 1.52


I think it's the 4x8 instead of 2x16, less airflow for them around the sides of the sticks. Case has more than enough airflow. They only got warm during TM5, Kahru etc when deliberately stressing it all at once.

Regarding staying within manufacturer specs, this isn't "lookwebuiltapctomanufacturwrspecs.net".


----------



## nick name

tcclaviger said:


> I think it's the 4x8 instead of 2x16, less airflow for them around the sides of the sticks. Case has more than enough airflow. They only got warm during TM5, Kahru etc when deliberately stressing it all at once.
> 
> Regarding staying within manufacturer specs, this isn't "lookwebuiltapctomanufacturwrspecs.net".


Well if we're pointing at that . . . there is a flame. Hot hot hot.


----------



## Yuke

Streetdragon said:


> Worth? not really no. But fun to push the sticks to its limit(in "ok" volts)
> 
> https://www.overclock.net/forum/10-...memory-stability-thread-402.html#post28535988


Its just weird that i can push everything pretty far but my CL main timing...Atm testing 250TRFC and no errors so far...wish my main timings would be that forgiving....but imho going from 1.4V to 1.51V just for that is questionable, especially as my CPU is not worth the push imho...maybe when i upgrade to Zen3 refresh in 1.5Years.


----------



## Yuke

1.44V in BIOS

RFC from 288 to 264 needed 0.06V more. I think thats pretty much my limit without going all out with 1.51V.


----------



## rares495

Yuke said:


> 1.44V in BIOS
> I think thats pretty much my limit without going all out with 1.51V.


So it's not your limit then. Just the limit of what you feel is "safe".


----------



## Yuke

rares495 said:


> So it's not your limit then. Just the limit of what you feel is "safe".


Well, yes, thats what i wrote. Its my first dual rank Kit, so no idea how i should handle it in the long term.


----------



## nick name

Yuke said:


> Well, yes, thats what i wrote. Its my first dual rank Kit, so no idea how i should handle it in the long term.


I've never heard anyone with experience and knowledge say 1.5V is bad for Samsung b-die. However, I have heard plenty of folks say it's perfectly fine. 

So if you want to see what your kit can do and have some fun then I'd encourage you'd to give 1.5V a go. Overclocking RAM can be very fun.


----------



## Yuke

nick name said:


> I've never heard anyone with experience and knowledge say 1.5V is bad for Samsung b-die. However, I have heard plenty of folks say it's perfectly fine.
> 
> So if you want to see what your kit can do and have some fun then I'd encourage you'd to give 1.5V a go. Overclocking RAM can be very fun.


So can i push dual rank like single rank in terms of longetivity?


----------



## nick name

Yuke said:


> So can i push dual rank like single rank in terms of longetivity?


Yes. 

Don't forget -- some b-die XMP/DOCP are set to 1.5V.


----------



## Yuke

nick name said:


> Yes.
> 
> Don't forget -- some b-die XMP/DOCP are set to 1.5V.


Yes, but those are Single Rank Kits afaik.


Tightened up tRAS/tRC combo, 1.45V set in BIOS now. Anything else i could do with secondary/tertiary timings?


----------



## nick name

Yuke said:


> Yes, but those are Single Rank Kits afaik.
> 
> 
> Tightened up tRAS/tRC combo, 1.45V set in BIOS now. Anything else i could do with secondary/tertiary timings?


Well I wouldn't run tRAS and tRC that low. I'd run it at 34 and 50 and then lower tRFC at 250.


----------



## nick name

Yuke said:


> Yes, but those are Single Rank Kits afaik.
> 
> 
> Tightened up tRAS/tRC combo, 1.45V set in BIOS now. Anything else i could do with secondary/tertiary timings?


And why do you think dual rank are different than single rank? All ICs have heat spreaders on them so if heat is the issue -- it shouldn't be. Heat isn't going to destroy the RAM, but it may cause instability at the tightest timings.


----------



## rares495

nick name said:


> Well I wouldn't run tRAS and tRC that low. I'd run it at 34 and 50 and then lower tRFC at 250.


Going as low as possible is really nice. 


You do need to sync everything though.


----------



## Yuke

nick name said:


> Well I wouldn't run tRAS and tRC that low. I'd run it at 34 and 50 and then lower tRFC at 250.


Isnt there a rule where tRFC should be a multiple of tWR and tRTP? Should i change tWR/tRTP?


----------



## nick name

Yuke said:


> Isnt there a rule where tRFC should be a multiple of tWR and tRTP? Should i change tWR/tRTP?


I couldn't say. I've seen folks use multiples of tRC though. 

My current timings don't base tRFC off of tRC and it proved stable last night so I'm really not sure.


----------



## rares495

Yuke said:


> Isnt there a rule where tRFC should be a multiple of tWR and tRTP? Should i change tWR/tRTP?


tCL*32	tRC * 8	tCL/2	tRC * 7	tCL/2-1	tRC * 6

From God Veii's tRFC calculator:

https://docs.google.com/spreadsheet...YEq2RElJ5T6Hcx9WdReTsnIWw/edit#gid=1745688811


----------



## Yuke

rares495 said:


> tCL*32	tRC * 8	tCL/2	tRC * 7	tCL/2-1	tRC * 6
> 
> From God Veii's tRFC calculator:
> 
> https://docs.google.com/spreadsheet...YEq2RElJ5T6Hcx9WdReTsnIWw/edit#gid=1745688811


Hmmm, thanks for the link. Not sure if i get it but it seems i should run CL=14 and tRC=44 for tRFC=264....CL16 and tRC=48 should use tRFC=288?...but i can use tRFC 264 with CL16 and tRC=48 and it also gives me better benchmark results. Am i missing something?


----------



## rares495

Yuke said:


> Hmmm, thanks for the link. Not sure if i get it but it seems i should run CL=14 and tRC=44 for tRFC=264....CL16 and tRC=48 should use tRFC=288?...but i can use tRFC 264 with CL16 and tRC=48 and it also gives me better benchmark results. Am i missing something?


It's a matter of sync. 

If you're not using optimal subtimings, the motherboard will autocorrect.


----------



## Dr. Vodka

Just upgraded to a 3900x from a segfault bugged 1700.











My 1700 couldn't reliably do over 3400-3466MHz, no matter if using 2x8GB quality B-die or these same 4x16GB Rev. E sticks. This 3900x makes short work of them, and works wonderfully in the same C6H. 64GB, quad rank, 1900MHz fabric, 3800MHz memory, lowest procODT, low voltages overall.

I can run 1900MHz fabric on 0.8v VDDG and pass stress tests, but then I get audio crackling/cutouts, so it's not really stable.

tRCDRD 18 @ 3800MHz hangs half way into Windows' loading screen... So, settled on 19 (clean 10ns @ 3800MHz) and 16 for the rest of the primaries, and the rest of the timings have all been manually calculated from @Veii 's knowledge. Extremely helpful posts.


No doubt Rev. E is light on the memory controller.


----------



## heptilion

hey guys i am back with some new issues  

Ive been running with these timings 2x8gb gskill flarex for a couple of months and decided to buy another set of the same ram to make it 4x8gb and im finding it difficult to get them to run at these or any higher timings. ive tried running only the new kits by themselves and it works but 4x8 setup is a no go. any advice? ive tried playing around with different procodt and cad bus timings but doesnt seem to fix it. 

2x8gb voltages are

dram - 1.5
vddg - .95
vddp - .9
vsoc 1.088
proc odt 34
cad bus 40-20-20-24


any advice would be much appreciated @rares495 @KedarWolf @Veii


----------



## rares495

Dr. Vodka said:


> Just upgraded to a 3900x from a segfault bugged 1700.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> My 1700 couldn't reliably do over 3400-3466MHz, no matter if using 2x8GB quality B-die or these same 4x16GB Rev. E sticks. This 3900x makes short work of them, and works wonderfully in the same C6H. 64GB, quad rank, 1900MHz fabric, 3800MHz memory, lowest procODT, low voltages overall.
> 
> I can run 1900MHz fabric on 0.8v VDDG and pass stress tests, but then I get audio crackling/cutouts, so it's not really stable.
> 
> tRCDRD 18 @ 3800MHz hangs half way into Windows' loading screen... So, settled on 19 (clean 10ns @ 3800MHz) and 16 for the rest of the primaries, and the rest of the timings have all been manually calculated from Veii's knowledge. Extremely helpful posts.
> 
> 
> No doubt Rev. E is light on the memory controller.


You just have to increase VDDG to get rid of the audio crackle.


----------



## Dr. Vodka

rares495 said:


> You just have to increase VDDG to get rid of the audio crackle.



I have no crackle at 0.9v, as shown in the picture with all my settings.

I was just amazed to see 1900MHz work at only 0.8v  My 3900x must have a nice I/O die.


On the other hand, my friend's 3950x crackles at 1900MHz and ~1.05v VDDG, 1.1v vSOC... F for him


----------



## 2600ryzen

Dr. Vodka said:


> Just upgraded to a 3900x from a segfault bugged 1700.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> My 1700 couldn't reliably do over 3400-3466MHz, no matter if using 2x8GB quality B-die or these same 4x16GB Rev. E sticks. This 3900x makes short work of them, and works wonderfully in the same C6H. 64GB, quad rank, 1900MHz fabric, 3800MHz memory, lowest procODT, low voltages overall.
> 
> I can run 1900MHz fabric on 0.8v VDDG and pass stress tests, but then I get audio crackling/cutouts, so it's not really stable.
> 
> tRCDRD 18 @ 3800MHz hangs half way into Windows' loading screen... So, settled on 19 (clean 10ns @ 3800MHz) and 16 for the rest of the primaries, and the rest of the timings have all been manually calculated from Veii's knowledge. Extremely helpful posts.
> 
> 
> No doubt Rev. E is light on the memory controller.



I think GDM rounds up odd trcdrd timings, or it seems to on mine so you might be running trcdrd20. On my Rev E 2 x 16gb kit if I lower Tfaw below 28 the Dram calculator benchmark gets slower, have you benchmarked Tfaw 16 vs higher numbers like 20-24?


----------



## rares495

heptilion said:


> hey guys i am back with some new issues
> 
> Ive been running with these timings 2x8gb gskill flarex for a couple of months and decided to buy another set of the same ram to make it 4x8gb and im finding it difficult to get them to run at these or any higher timings. ive tried running only the new kits by themselves and it works but 4x8 setup is a no go. any advice? ive tried playing around with different procodt and cad bus timings but doesnt seem to fix it.
> 
> 2x8gb voltages are
> 
> dram - 1.5
> vddg - .95
> vddp - .9
> vsoc 1.088
> proc odt 34
> cad bus 40-20-20-24
> 
> 
> any advice would be much appreciated @rares495 @KedarWolf @Veii


4x8 = hard to run; you give up overclocking potential for capacity

Try cad_bus 60-20-20-24 and procODT 60-80 ohm.


----------



## rares495

Dr. Vodka said:


> I have no crackle at 0.9v, as shown in the picture with all my settings.
> 
> I was just amazed to see 1900MHz work at only 0.8v  My 3900x must have a nice I/O die.
> 
> 
> On the other hand, my friend's 3950x crackles at 1900MHz and ~1.05v VDDG, 1.1v vSOC... F for him


Yeah, the 12&16 core chips could always do 1900 easily. Even my old 3700X did it on auto VDDG. This 3600 needs 1.15V SOC and 1.1V VDDG to stop the crackle.


----------



## heptilion

rares495 said:


> 4x8 = hard to run; you give up overclocking potential for capacity
> 
> Try cad_bus 60-20-20-24 and procODT 60-80 ohm.


I tried that and no go. I cant even run this at 3200mhz tight ram timings using ryzen calc. Only works with xmp cl14. And the system gets stuck sometimes when I try to get into bios as well. What in the world is going on :/


----------



## 2600ryzen

4 Dimms depends a lot more on getting good contact between the cpu pins and the motherboard. Once I lost dual channel because I was moving my fan around on the cpu heatsink and when I gently pressed the heatsink into the motherboard so the pressure was even across the cpu pins it fixed it and also allowed me to run 1t GDM off at up to 3800mhz..for a few days. Eventually it went back to only being able to run GDM disabled at up to 3200mhz but it helped for a while. 

I can see why threadripper with so many memory channels and RAM slots has a really sophisticated locking mechanism to ensure the cpu pins make good contact.


----------



## mongoled

heptilion said:


> I tried that and no go. I cant even run this at 3200mhz tight ram timings using ryzen calc. Only works with xmp cl14. And the system gets stuck sometimes when I try to get into bios as well. What in the world is going on :/


Dude,

grab some coffee, get google and start researching.

Nothing is "going on".

Its well know if you at least did a bit of research that 4 x 8GB is alot more difficult to run at similar timings/frequency than 2 x 8GB.

Only a quick look in this thread and you will see others have attempted this and have received some assistance from others

 

It should be nothing of a suprise if you read a bit first!

FYI

ProcODT: 40 ohms/6
RTTNOM: 34 ohms/7
RTTWR: 80 ohms/3
RTTPARK: 240 ohms/1

ClkDrv: 24 
AddrCmdDrv: 20
CsOdtDrv: 30
CkeDrv: 24

You also have to play with DRAM voltage, vSOC with the above settings religiously just to get it to post at higher frequencies.

The maximum I could reliably post at was 3666/1833 but forget TM5 stability and I spent a good 48 hours reading, researching, testing, documenting to get this far.

Ofcourse, it also depends on your motherboard, if you had spent 5 minutes checking you would have known this.

I was doing this on my x370, which is a challange in itself.

If you are on x570 you have a better chance of getting somthing similar to your 2 x 8GB clocks.

But please, again, nothing is "going on" ............


----------



## heptilion

mongoled said:


> Dude,
> 
> grab some coffee, get google and start researching.
> 
> But please, again, nothing is "going on" ............


Mate, I posted my issues after doing research and playing around with timings. That's why i went back to see what happens when i try to tighten my timings at 3200 instead of overclocking after "rares" suggestion didnt work. 

I will try your timings and will post back with my findings. Thanks for suggesting those to me. Much appreciated


----------



## mongoled

heptilion said:


> Mate, I posted my issues after doing research and playing around with timings. That's why i went back to see what happens when i try to tighten my timings at 3200 instead of overclocking after "rares" suggestion didnt work.
> 
> I will try your timings and will post back with my findings. Thanks for suggesting those to me. Much appreciated


What motherboard are you on?

That will tell us if it is T-Topology or Daisy Chain topology.

For me, timings were not the issue, I could try 22-22-22-22 etc it didnt make a difference.

Its all in playing with the settings I posted, learning what your motherboard/ram combination react to and taking it from there .

Good luck!


----------



## heptilion

mongoled said:


> What motherboard are you on?
> That will tell us if it is T-Topology or Daisy Chain topology.
> 
> For me, timings were not the issue, I could try 22-22-22-22 etc it didnt make a difference.
> 
> Its all in playing with the settings I posted, learning what your motherboard/ram combination react to and taking it from there .
> 
> Good luck!


It's c8h hero wifi, which I believe is Daisy chained. Also do you follow dram 1.73 or 1.62? Because I just noticed that bgs is enabled and bgs alt disabled in 1.62 for 4 dimms and it's the other way arlund( which is what thought should be normally) in 1.73.


----------



## mongoled

heptilion said:


> It's c8h hero wifi, which I believe is Daisy chained. Also do you follow dram 1.73 or 1.62? Because I just noticed that bgs is enabled and bgs alt disabled in 1.62 for 4 dimms and it's the other way arlund( which is what thought should be normally) in 1.73.


That wont make a difference regards the issue.

Its about finding the right combination.

And it helps immensly if the kits are matched, as in, sold matched.

Buying two identical 2 x 8GB kits is not the same as buying a kit that has been matched/sold as 4 x 8GB.

Be prepared to invest a substantial amount of time to get them to work, you have a good motherboard at least for getting there!

https://docs.google.com/spreadsheet...FnsZYZiW1pfiDZnKCjaXyzd1o/edit#gid=2112472504

I started here


----------



## VPII

mongoled said:


> That wont make a difference regards the issue.
> 
> 
> 
> Its about finding the right combination.
> 
> 
> 
> And it helps immensly if the kits are matched, as in, sold matched.
> 
> 
> 
> Buying two identical 2 x 8GB kits is not the same as buying a kit that has been matched/sold as 4 x 8GB.
> 
> 
> 
> Be prepared to invest a substantial amount of time to get them to work, you have a good motherboard at least for getting there!
> 
> 
> 
> https://docs.google.com/spreadsheet...FnsZYZiW1pfiDZnKCjaXyzd1o/edit#gid=2112472504
> 
> 
> 
> I started here


Well I am fortunate enough to have two sets of 2 x 8Gb G-Skill Flare X DDR4 3200 CL14, and running fine at 3733 CL16 without any issues.

Sent from my SM-G960F using Tapatalk


----------



## heptilion

VPII said:


> Well I am fortunate enough to have two sets of 2 x 8Gb G-Skill Flare X DDR4 3200 CL14, and running fine at 3733 CL16 without any issues.
> 
> Sent from my SM-G960F using Tapatalk


Could you share your settings with us please!

Looks like I can't run even xmp profile anymore on 4x8gb 3200cl14. For some reason system keeps restarting while I'm just browsing.


----------



## Veii

Yuke said:


> Hmmm, thanks for the link. Not sure if i get it but it seems i should run CL=14 and tRC=44 for tRFC=264....CL16 and tRC=48 should use tRFC=288?...but i can use tRFC 264 with CL16 and tRC=48 and it also gives me better benchmark results. Am i missing something?


I would need to look closer, out of this range which one fits well for 3800MT/s








But for example on 3733.3xxx4MT/s ~ the one that works well is 336, lower is always a bit tricky

The values you get suggested are correct, but in order to perform better - the rest of the set needs to be also correct
Pushing tRC up will add wasted latency, and if tRFC delay is wrong or a tiny bit off, it will be postponed to another whole refresh cycle
In tREFI main time, after all 9* this tRFC can happen, and be postponed before it closes
Logically on AMD tREFI is auto calculated 

You can lie and make your live easier by just pushing tRC up, and keeping tRAS correct 
But if tRAS is too low, it will be autocorrected up, if tRC is too low usually no autocorrect will happen and it will spill out errors 
(this means tho, using correct tRFC to begin with for this low tRC) 
If you use a "wrong" tRFC and tRC is too low, what only will happen is 
- tRFC will be postponed to the next cycle
- memory will finish tRC cycle, look for refresh time, see tRFC got postponed and just wait till the next big cycle happens
"next Cycle" tho as tRFC mostly is 6 cycles if calculated low enough, the delay and performance degrade by this "autocorrection" will be noticable 


heptilion said:


> hey guys i am back with some new issues
> 
> Ive been running with these timings 2x8gb gskill flarex for a couple of months and decided to buy another set of the same ram to make it 4x8gb and im finding it difficult to get them to run at these or any higher timings. ive tried running only the new kits by themselves and it works but 4x8 setup is a no go. any advice? ive tried playing around with different procodt and cad bus timings but doesnt seem to fix it.
> 
> 2x8gb voltages are
> 
> dram - 1.5
> vddg - .95
> vddp - .9
> vsoc 1.088
> proc odt 34
> cad bus 40-20-20-24
> 
> 
> any advice would be much appreciated
> 
> 
> mongoled said:
> 
> 
> 
> Dude,
> grab some coffee, get google and start researching.
> 
> FYI
> 
> ProcODT: 40 ohms/6
> RTTNOM: 34 ohms/7
> RTTWR: 80 ohms/3
> RTTPARK: 240 ohms/1
> 
> ClkDrv: 24
> AddrCmdDrv: 20
> CsOdtDrv: 30
> CkeDrv: 24
> 
> You also have to play with DRAM voltage, vSOC with the above settings religiously just to get it to post at higher frequencies.
Click to expand...

Now that we know he is on X570 Daisy Chain, he might be fine with values like 40-20-20-24 
But 60-20-20-24 would make him/her issues, if he/she was on X370 to begin with 
X570 shouldn't have cold boot issues with low CsOdtDrv although as what he tries is GDM disabled 
First work would be to get the RTT and CAD_BUS values correct
@rares495 suggestion was correct , he lucky appears to have an x570 board

What only missed is, increasing VDDG IOD ~ prioritizing it after using doubled stepping , doubled 50mV or doubled 75mV 
To split it around
3734MT/s would optimally be:
cLDO_VDDP 913mV
VDDG CCD 953
VDDG IOD 1003
vSOC 1050 or 1100 with P0 SOC powerstate (constant without fluctuation)


Spoiler



I'm sorry for the bad picture, not my setup ~ it's inside AMD CBS










although as most boards don't allow fine granual voltage control except in the 5mV not 1mV range:

cLDO_VDDP 900mV
VDDG CCD 950
VDDG IOD 1000
vSOC 1050/1100
or
cLDO_VDDP 900mV
VDDG CCD 975
VDDG IOD 1050
vSOC 1125 (flat LLC again) 
would work

I belive 1050vSOC is fine, 
But heptilion has to keep in mind, that such low vSOC requires low procODT else you have voltage crashes or no post at all
39.6Ohm should be plenty for 4x SR B-dies, maybe even down to 36ohm 
30 could work near the 3600MT/s range with about 1.025/1.0325vSOC
1.1 & 1.125v vSOC would require at least >40ohm ProcODT to make no issues

Overall keep IOD higher, and my suggestion is, doublecheck each of your memory PCBs (bottom and the side)
Make pictures like:


Spoiler














in order to figure out which PCB these things are on
This is important, as Daisy Chain splits your signal into 75/25% 
soo the "slave" set of dimms will only get 1/4th & the main set 3/4th out of the impedance and also voltage you have applied
Meaning, you have to overvolt the main dimms and the board a bit (here comes VDDG IOD into play) to even have a remote chance of getting high frequency stable

Optimally you want A0 kits to be on the slave side, as these prefer lower current and can work even on B350 boards well enough


heptilion said:


> Could you share your settings with us please!
> 
> Looks like I can't run even xmp profile anymore on 4x8gb 3200cl14. For some reason system keeps restarting while I'm just browsing.


Try this set:








4 dimms like 1-4-4-1-6-6 SD, DDs more 
If you use tRDWR = tRCD/2 , on 4 dimms you have to add tWRRD delay, else you need to use tRDWR+1 
4 dimms and also dual rank might need higher tRFC - but look at the first picture attached
This is your tRFC range for 14-42 and 16-48, 15-45 would be an option but tRFC results are odd and not even, soo no option so far

If you have post issues, use higher tRFC
If you have all is stable, try to use tWR 12
If that still posts, you can try for the primaries:
14-12-16-14-30-42 
16 = tRCD RD 
Although you might need to use tRC 44 here for 4 dimms, 
we'll see

First figure out which PCB these things are even on, before you can have success with 1usmus DRAM calculator suggestions 
Only then after RTT & CAD_BUS + voltages are correct, consider going GDM disabled and work on your kit

EDIT:
Oops, reuploaded your timings preset 
~ i'm sorry for the double compression on it
Made a tiny mistake on tRAS
tRAS 30 is only fine when you use tCL+tWR+tBL (2) math 
but as tWR starts with 24 and so will be ignored, tCL+tRCD=tRAS = 32, under CL16-16-16


----------



## heptilion

Veii said:


> First figure out which PCB these things are even on, before you can have success with 1usmus DRAM calculator suggestions
> Only then after RTT & CAD_BUS + voltages are correct, consider going GDM disabled and work on your kit


According to thaiphoon reading they are A1 but from looking at PCB layout they seem to be A2? 

Also does it matter in which order i should install the new kit and old kit? a2b2 - old a1b1- new( as seen in the picture) or a2a1 -old b2b1- old


----------



## Veii

heptilion said:


> According to thaiphoon reading they are A1 but from looking at PCB layout they seem to be A2?
> 
> Also does it matter in which order i should install the new kit and old kit? a2b2 - old a1b1- new( as seen in the picture) or a2a1 -old b2b1- old


Yes they are all A2, good luck  
It would matter, if the kits where on a different PCB 
And it matters if you know which kits need more voltage
The one that need more voltage put on the main channel 2,4
the one that need less voltage and technically are a better binning, put on 1,3 

else always put the kit which doesn't need much voltage or likes less (like A0 kits)
on the slave channel 

I think you can start to do some binning and figure out which kit is weaker  
But 4x A2 on Daisy Chain, is bothersome - at least they are not Dual rank B2 

use the same voltage sample put above with 1050vSOC 
And try to see how much voltage you need to get for example something like this stable
It's under GDM enabled, with RTT 0-0-5 @ 30 or 28.2 ohm (1800FCLK) @ 1.44vDimm

Actually i wanted to jump on the Memory Voltage Too Much-Not enough discussion
but i think people would figure it out by themself that too much is too much for B-Dies
It won't really destroy or degrade them , even when temps are low
But this set would error 12 on 1.48vDimm, and Error 6-6-6-12 on 1.52v (A0 PCB) 
Lower did help here

Well yes, doublecheck which of your kits can run this and maybe even the 3467C14-14 harsh one from my signature
Do some binning and if they are anywhere near identical 
(i hope they have the same tRCD RD range)
then just check which one needs lower voltage for the same set of timings and put the best one on 1-3 

240ohm on RTT_PARK is only needed for 4 dimms and so also high procODT
Here it's not, try low procODT and so with it low vSOC to do some binning


----------



## VPII

heptilion said:


> Could you share your settings with us please!
> 
> Looks like I can't run even xmp profile anymore on 4x8gb 3200cl14. For some reason system keeps restarting while I'm just browsing.


In all honesty, I've never really ran the memory at DOCP / stock. Always been overclocked higher. Here is a screen grab of my memory timings with vdimm set to 1.45v in the bios. The 1.45vdimm is 100% safe. From what I gathered, most people say to place a fan over your memory dimms to keep it cool for stability, but the only fan close to my dimms at present is on blowing over the vrm which is not even needed. The system is as follow:

AMD Ryzen 9 3950X
MSI Meg X570 Ace 7C35v198(Beta version)
4 x 8GB G-Skill Flare X at 3733mhz CL16


----------



## heptilion

Veii said:


> Yes they are all A2, good luck
> It would matter, if the kits where on a different PCB
> And it matters if you know which kits need more voltage
> The one that need more voltage put on the main channel 2,4
> the one that need less voltage and technically are a better binning, put on 1,3
> 
> else always put the kit which doesn't need much voltage or likes less (like A0 kits)
> on the slave channel
> 
> I think you can start to do some binning and figure out which kit is weaker
> But 4x A2 on Daisy Chain, is bothersome - at least they are not Dual rank B2


Ok i Just checked which kit is stable and found that my old kit is better than the new one. 

Tested with 3200 A2 Fast timings ( attached below) on dram 1.36 vsoc 1.05 vddp .9 vddg .95 procodt 28.2 and cadbus 40 20 20 24.

With old kit in 2 4 and new on 1 3 i was getting errors on tm5 from the get go but when i swapped them around is stable on 3 cycles so far which suggests the old kit is better.

but when i restart the pc it gets stuck during boot and have to reset to boot again. what would cause such thing?


----------



## Veii

heptilion said:


> Ok i Just checked which kit is stable and found that my old kit is better than the new one.
> 
> Tested with 3200 A2 Fast timings ( attached below) on dram 1.36 vsoc 1.05 vddp .9 vddg .95 procodt 28.2 and cadbus 40 20 20 24.
> 
> With old kit in 2 4 and new on 1 3 i was getting errors on tm5 from the get go but when i swapped them around is stable on 3 cycles so far which suggests the old kit is better.


Yes the better kit on 1-3 would help
but still split VDDG CCD and IOD a bit
CL14-14 is one thing, but what really is better will show after you push beyond 3600
Some of them only shine after 1.42v , some after 1.46 and A2 kits love beyond that near 1.48-1.51v 
You have to test which one can keep flat tRCD of 14 without any need to go up to 15
tRP belongs only to voltage, soo you can lower that later if you want to meet a tRC target
I am not sure how long you can hold SCL 2, but let's see


> but when i restart the pc it gets stuck during boot and have to reset to boot again. what would cause such thing?


This belongs to CAD_BUS CsOdtDrive
3rd CAD_BUS value

see if by increasing VDDG IOD to 1v while still keeping 1.05vSOC till 3600MT/s , you'd see a fix
If not, just use something like 40-20-24-24 
Or at worst even 40-20-30-24


----------



## heptilion

Veii said:


> Yes the better kit on 1-3 would help
> 
> This belongs to CAD_BUS CsOdtDrive
> 3rd CAD_BUS value
> 
> see if by increasing VDDG IOD to 1v while still keeping 1.05vSOC till 3600MT/s , you'd see a fix
> If not, just use something like 40-20-24-24
> Or at worst even 40-20-30-24


Tried increasing csodt drive to 24 30 and even 40 but still the issue is occuring. also upped vddg iod to 1v and still no go.

edit 1 : think i managed to fix it by changing rtt 7-3-1 with cad 40-20-20-24

edit 2 : had to enable gear down mode to run these on 3600MT but TM5 passed 2 rounds. will try 3733 next to see what happens


----------



## mongoled

Has anybody got any info on how high BCLK can effect FCLK/MCLK stability.

Long story short, I know using no BCLK I have 3800/1900 rock stable.

But when using high BCLK, I am stable up to 3788/1866 all ram timings/settings being equal.

And so far the instability I have experienced is in TM5 throwing random errors.

Cant spot a pattern in the error codes, sometimes is error 1, 10, other times its 4 and 5 sometimes 15, 0, and 12. 

Ive tried with fix CPU multipliers and with PBO disabled just so i know these are not effecting the results.

Ive tried playing around with many different combinations but cant get a foot hold on what may assist in helping TM5 play nice....

BCLK at 107.525 with 3533mhz mem gives me a nice rounded 3800/1900


----------



## Veii

heptilion said:


> Tried increasing csodt drive to 24 30 and even 40 but still the issue is occurring. also upped vddg iod to 1v and still no go.
> 
> edit 1 : think i managed to fix it by changing rtt 7-3-1 with cad 40-20-20-24
> edit 2 : had to enable gear down mode to run these on 3600MT but TM5 passed 2 rounds. will try 3733 next to see what happens


3733 might need vSOC of 1075
What procODT are you running atm for these 4 dimms ?
GDM disabled only works, when RTT and CAD_BUS values are fine, then you need a bit more voltage
But it will always work, once you figured out it's pattern on why it doesn't

Keep us up to date 
EDIT:
Use 20 rounds TM5 1usmus_v3 to actually state stability. Some tests like tRFC crash on the 19th cycle, and till the 6th it can be everything including heat.
You can get the original zip from 1usmus's dram calculator first post or his signature & change the MT.cfg to cycle loop 20 times instead of 3
Or you can get it pre-zipped, edited from here


mongoled said:


> Has anybody got any info on how high BCLK can effect FCLK/MCLK stability.
> 
> Long story short, I know using no BCLK I have 3800/1900 rock stable.
> But when using high BCLK, I am stable up to 3788/1866 all ram timings/settings being equal.
> 
> BCLK at 107.525 with 3533mhz mem gives me a nice rounded 3800/1900


I remember 1usmus running 3734MT/s timings with BLCK rounded up at the very start
Except for potential data loss issues on NVME's and added latency by desync
(some frequency control chips ~forgot their actual name~ crystal something) 
some of the chips, actually cause added latency, in order to separate storage and video card desync
Memory also is detected without BLCK bump ~ and so timings it uses are also autocorrected for the wrong frequency
It can work well, but you might need BLCK >110Mhz to hit natural scaling tRFC targets 

For example tRFC full cycle is virtual value 32, or 1/2 cycle is 16
Having "optimal tRFC" +16 or +32 above the main frequency you build your timings on before BCLK OC
Will cause a natural transition, even when autoprediction tries to mess it up, it will at worst time-break once and fix itself 

Usually bad idea, but IF you can use such a high decoupled range ~ then it might be useful to bypass the artificial frequency lockdown on 3xxx X Ryzen


mongoled said:


> And so far the instability I have experienced is in TM5 throwing random errors.
> Cant spot a pattern in the error codes, sometimes is error 1, 10, other times its 4 and 5 sometimes 15, 0, and 12.
> Ive tried with fix CPU multipliers and with PBO disabled just so i know these are not effecting the results.
> Ive tried playing around with many different combinations but cant get a foot hold on what may assist in helping TM5 play nice....


Error 1, 10 ~ simple Test size 8-16mb , 8 is a burst error, too much not enough voltage related (difference +/- 0.01vDimm)
Error 4,5,15,0 ~ Mirror Copy and Simple Error size 0 , a delay issue a "not enough = chokes too early" issue
tRDWR/tWRRD or just plain simply tRFC desynching
Error 12 ~ simple test size 16mb, this one can mean a lot
Depends on the pairs it came with, but as you mentioned 15 & 0 which both are mirror copy errors
If the order is correct, it tries to duplicate the data to the other bank, fails - retries again, fails - tries to delay and crashes by wrong timings (size 16mb)

At the end, the main issue appears to be just wrong prediction and wrong tRFC 
Maybe only just wrong tRFC causing bad tREFI, causing badly sheduled retry correction , just error'ing 
Try what i mentioned before - 3600 and 4000MT/s are quite well synced, but you can explore which "suggested tRFC" works out better

For example patterns that work well are
CL14-tRC42, CL15-tRC45, CL16-tRC48
try to move tRC in steps of 3 and see if you can hit a nicely even identical tRFC across the range 
Actually no make it a bit more accurate
Keep the ruleset in mind that, every 4 frequency bumps of 200MT/s are +1 tCL increase = +3 tRC increase
check the frequency difference = MT/s stepping between your base frequency and your end up freuquency
Calculate the tRC increase difference and see when you hit +16 or +32 suggested tRFC difference 
Good luck :thumb:


----------



## heptilion

Veii said:


> 3733 might need vSOC of 1075
> What procODT are you running atm for these 4 dimms ?
> GDM disabled only works, when RTT and CAD_BUS values are fine, then you need a bit more voltage
> But it will always work, once you figured out it's pattern on why it doesn't


Running with procodt 28.2 and rtt 7-3-1 with cad 40-20-20-24. 
vdimm 1.5(1.512 actual value)
vsoc 1.06875 (1.05 actual value)
vddp .9
vddg ccd 0.95
vddg iod 1

i didnt want to play around with rtt much cus its what fixed my reboot issue. what do you think i should do?

Update 1: Passed tm5 20 cycles on these timings. now to figure out if i can disable gear down mode.

Update 2: @Veii Tried playing around with cad bus settings and even increased vsoc to 1.075 and procohm 34.3 but no go. So my next option is to tighted timings maybe? any suggestions?


----------



## pipes

heptilion said:


> 3733 passed 5th cycle on tm5 as i was typing this.
> 
> 
> 
> Running with procodt 28.2 and vsoc 1.06875 in bios(but actual value is 1.048). i didnt want to play around with rtt much cus its what fixed my reboot issue. what do you think i should do?


Onlus for my 3700x zen timings no work?

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## mongoled

Veii said:


> I remember 1usmus running 3734MT/s timings with BLCK rounded up at the very start
> Except for potential data loss issues on NVME's and added latency by desync
> (some frequency control chips ~forgot their actual name~ crystal something)
> some of the chips, actually cause added latency, in order to separate storage and video card desync
> Memory also is detected without BLCK bump ~ and so timings it uses are also autocorrected for the wrong frequency
> It can work well, but you might need BLCK >110Mhz to hit natural scaling tRFC targets
> 
> For example tRFC full cycle is virtual value 32, or 1/2 cycle is 16
> Having "optimal tRFC" +16 or +32 above the main frequency you build your timings on before BCLK OC
> Will cause a natural transition, even when autoprediction tries to mess it up, it will at worst time-break once and fix itself
> 
> Usually bad idea, but IF you can use such a high decoupled range ~ then it might be useful to bypass the artificial frequency lockdown on 3xxx X Ryzen
> 
> Error 1, 10 ~ simple Test size 8-16mb , 8 is a burst error, too much not enough voltage related (difference +/- 0.01vDimm)
> Error 4,5,15,0 ~ Mirror Copy and Simple Error size 0 , a delay issue a "not enough = chokes too early" issue
> tRDWR/tWRRD or just plain simply tRFC desynching
> Error 12 ~ simple test size 16mb, this one can mean a lot
> Depends on the pairs it came with, but as you mentioned 15 & 0 which both are mirror copy errors
> If the order is correct, it tries to duplicate the data to the other bank, fails - retries again, fails - tries to delay and crashes by wrong timings (size 16mb)
> 
> At the end, the main issue appears to be just wrong prediction and wrong tRFC
> Maybe only just wrong tRFC causing bad tREFI, causing badly sheduled retry correction , just error'ing
> Try what i mentioned before - 3600 and 4000MT/s are quite well synced, but you can explore which "suggested tRFC" works out better
> 
> For example patterns that work well are
> CL14-tRC42, CL15-tRC45, CL16-tRC48
> try to move tRC in steps of 3 and see if you can hit a nicely even identical tRFC across the range
> Actually no make it a bit more accurate
> Keep the ruleset in mind that, every 4 frequency bumps of 200MT/s are +1 tCL increase = +3 tRC increase
> check the frequency difference = MT/s stepping between your base frequency and your end up freuquency
> Calculate the tRC increase difference and see when you hit +16 or +32 suggested tRFC difference
> Good luck :thumb:


Thanks! Its does seem that it is something to do with sync.

Ive read your suggestions several times and am still unable to follow your logic.

I will come back to your suggestion later and re-read and maybe i will understand what you are saying.

For example

"every 4 frequency bumps of 200MT/s"

Are you saying, for every 800MT/s increase adjust tCL +1 and tRC +3 ?

If so, why are you saying every 4 frequency bumps of 200 MT/s, what is the relevance of 4 ?

And you say 

"Try what i mentioned before - 3600 and 4000MT/s are quite well synced"

What do mean that they are "well synced" ?

In comparative to what, to other preset MT/s such as 3200, 3333, 3533 etc and with reference to pre-determned autocorrection tables for tRFC ?

And that the autocorrection of 3600 and 4000 MT/s are more accurate when using BCLK?

I do appreciate the assistance and think I have understood the general relevance of what you have explained. ......


----------



## glnn_23

Running 2x8Gb Team Group 3600c14 @ 3800c14

Vdimm 1.46
Soc 1.075
Vddg ccd 1.0
Vddg iod .95


----------



## Veii

mongoled said:


> Thanks! Its does seem that it is something to do with sync.
> Ive read your suggestions several times and am still unable to follow your logic.
> I will come back to your suggestion later and re-read and maybe i will understand what you are saying.
> 
> For example
> "every 4 frequency bumps of 200MT/s"
> 
> Are you saying, for every 800MT/s increase adjust tCL +1 and tRC +3 ?
> If so, why are you saying every 4 frequency bumps of 200 MT/s, what is the relevance of 4 ?
> 
> And you say
> "Try what i mentioned before - 3600 and 4000MT/s are quite well synced"
> What do mean that they are "well synced" ?
> In comparative to what, to other preset MT/s such as 3200, 3333, 3533 etc and with reference to pre-determned autocorrection tables for tRFC ?
> 
> And that the autocorrection of 3600 and 4000 MT/s are more accurate when using BCLK?
> I do appreciate the assistance and think I have understood the general relevance of what you have explained. ......


4 steps or 4 bumps, i ment as +1 , +1 , +1 , +1 either on the memory multiplier or overall the predefined by the bios speed
4 steps should equal about a 200Mhz jump
For example between 2933,3000,3066?,3133,3200 - that's 5 steps


Spoiler



There is a known ruleset, that when you increase the MT/s from 3200 -> 3400 or from 3800->4000 you can pretty much expect a +1 in tCL requirement +1 in tRCD 
you can compare this more accurately with the tRFC calculator, what it spills out on transfer time and CAS time 
it's also visible when you let's say put a fixed transfer time of 160ns for tRFC 
You can watch how tRFC changes, by how much when you follow the natural pattern

There is another way to doublecheck that too
multiply tCASns * 3 
or on google sheet, 
=C3*3=C4 
in this case C3= tCASns 
that will either spill out "true" or "false"

And to doublecheck that doublechecking:
Use this math:
(tCAS / (1000 / MT/s)) 
* in google sheet math =(C3/(1000/B2) 
** B2 being the correct memory frequency
the value should be 32, which is exactly a full cycle 
^ you can find that example in the 3rd sheet of the same doc - the experimenting zone i here there work on

I've mentioned on the post before that for example
tCL14 = tRC 42 as perfect cycle
tCL 15 = tRC 45
tCL 16 = tRC 48
tCL 17 = tRC 51 
and so on 
it goes as +3 tRC each tCL bump

I requested you to watch how tRFC changes, 
as on the current Pre-Prelease doc for accuracy sake tRFC changes only with tRC change
Which means,
use can use the same math and see when it will align - align that tRFC spilled out is exactly either +16 or +32 of your main timings, before BLCK bump
Taking for example 4000MT/s it's easy to work with, no decimals nothing
same as 3200MT/s


I just did it myself and it actually doesn't align - soo i'll put the answer as a WIP spoiler
The logic is correct, but i see a tRFC difference of 36 instead of 32 
Forget that answer so far, i'll look closer into it where the mistake is
But i think because something is not correct ~ i'll need a bit of time to figure out why it's tRFC jumps are 36 values, while a cycle is 32
Will let you know once i have it resolved - somewhere my math messes up 
* if a cycle ends up as 36 and not 32, i would need to redo the whole calculator  
Yes, give me some time ~ i'll have to look closer where it messes up 

EDIT 2:
tRFC calculator remains correct, but math is not correct to figure out the jump
it scales logarithmic, the results i got out , are the tRC value
About "tRFC cycle is 32" ~ i will need to investigate if this remains correct, because the education material looks to be wrong
What i get out is logarithmic scalable and not fixed tRFC multiplier
I'll investigate more and fix potential issues 
Maybe DDR education material made a mistake by their-self


----------



## Veii

glnn_23 said:


> Running 2x8Gb Team Group 3600c14 @ 3800c14
> 
> Vdimm 1.46
> Soc 1.075
> Vddg ccd 1.0
> Vddg iod .95


Can you benchmark how this set compares ?








If you have post issues, increase VDIMM to 1.48 and/or push tWTR_L back to 12


----------



## mongoled

Veii said:


> 4 steps or 4 bumps, i ment as +1 , +1 , +1 , +1 either on the memory multiplier or overall the predefined by the bios speed
> 4 steps should equal about a 200Mhz jump
> For example between 2933,3000,3066?,3133,3200 - that's 5 steps
> 
> 
> Spoiler
> 
> 
> 
> There is a known ruleset, that when you increase the MT/s from 3200 -> 3400 or from 3800->4000 you can pretty much expect a +1 in tCL requirement +1 in tRCD
> you can compare this more accurately with the tRFC calculator, what it spills out on transfer time and CAS time
> it's also visible when you let's say put a fixed transfer time of 160ns for tRFC
> You can watch how tRFC changes, by how much when you follow the natural pattern
> 
> There is another way to doublecheck that too
> multiply tCASns * 3
> or on google sheet,
> =C3*3=C4
> in this case C3= tCASns
> that will either spill out "true" or "false"
> 
> And to doublecheck that doublechecking:
> Use this math:
> (tCAS / (1000 / MT/s))
> * in google sheet math =(C3/(1000/B2)
> ** B2 being the correct memory frequency
> the value should be 32, which is exactly a full cycle
> ^ you can find that example in the 3rd sheet of the same doc - the experimenting zone i here there work on
> 
> I've mentioned on the post before that for example
> tCL14 = tRC 42 as perfect cycle
> tCL 15 = tRC 45
> tCL 16 = tRC 48
> tCL 17 = tRC 51
> and so on
> it goes as +3 tRC each tCL bump
> 
> I requested you to watch how tRFC changes,
> as on the current Pre-Prelease doc for accuracy sake tRFC changes only with tRC change
> Which means,
> use can use the same math and see when it will align - align that tRFC spilled out is exactly either +16 or +32 of your main timings, before BLCK bump
> Taking for example 4000MT/s it's easy to work with, no decimals nothing
> same as 3200MT/s
> 
> 
> I just did it myself and it actually doesn't align - soo i'll put the answer as a WIP spoiler
> The logic is correct, but i see a tRFC difference of 36 instead of 32
> Forget that answer so far, i'll look closer into it where the mistake is
> But i think because something is not correct ~ i'll need a bit of time to figure out why it's tRFC jumps are 36 values, while a cycle is 32
> Will let you know once i have it resolved - somewhere my math messes up
> * if a cycle ends up as 36 and not 32, i would need to redo the whole calculator
> Yes, give me some time ~ i'll have to look closer where it messes up
> 
> EDIT 2:
> tRFC calculator remains correct, but math is not correct to figure out the jump
> it scales logarithmic, the results i got out , are the tRC value
> About "tRFC cycle is 32" ~ i will need to investigate if this remains correct, because the education material looks to be wrong
> What i get out is logarithmic scalable and not fixed tRFC multiplier
> I'll investigate more and fix potential issues
> Maybe DDR education material made a mistake by their-self


Hi!

So that you dont waste your time, unless you want to check this for your own research.

I am currently running the same settings that have consistently failed TM5 with BCLK of 107.625 (God knows how many hours I spent trying to work out what was going on), the only difference is I have used the main tRFC set to 252 as so the other tRFC are AUTO configured.

Currently I am into the 11th cycle with no errors.

If this TM5 completes without those "random" errors appearing, than at least you know that it may be worth researching further, otherwise the errors I am receiving are not due to badly synchronised tRFC values but something else.

Wont be long before we know the answer


----------



## Veii

heptilion said:


> Running with procodt 28.2 and rtt 7-3-1 with cad 40-20-20-24.
> vdimm 1.5(1.512 actual value)
> vsoc 1.06875 (1.05 actual value)
> vddp .9
> vddg ccd 0.95
> vddg iod 1
> 
> i didnt want to play around with rtt much cus its what fixed my reboot issue. what do you think i should do?
> 
> Update 1: Passed tm5 20 cycles on these timings. now to figure out if i can disable gear down mode.
> 
> Update 2: @Veii Tried playing around with cad bus settings and even increased vsoc to 1.075 and procohm 34.3 but no go. So my next option is to tighted timings maybe? any suggestions?


Are you experiment friendy ?  
Can you try if this would work 









There is barely anything you can tighten anymore except when you get tRCD RD 16 down to 15 
From now on you have to measure subtle differences with SiSoftware Sandra - Multi-Core efficiency test 
Filter to local results/my own - only , and compare the both results under the detailed tab 
Your stable one and this awkward one ~ if it would even post

Also the benchmark inside DRAM calculator - Draw Latency Curve, is important  
Set of timings might need more than 1.5v maybe up to 1.53, but test it with your current voltage atm


----------



## Veii

mongoled said:


> Hi!
> 
> So that you dont waste your time, unless you want to check this for your own research.
> 
> I am currently running the same settings that have consistently failed TM5 with BCLK of 107.625 (God knows how many hours I spent trying to work out what was going on), the only difference is I have used the main tRFC set to 252 as so the other tRFC are AUTO configured.
> 
> Currently I am into the 11th cycle with no errors.
> 
> If this TM5 completes without those "random" errors appearing, than at least you know that it may be worth researching further, otherwise the errors I am receiving are not due to badly synchronised tRFC values but something else.
> 
> Wont be long before we know the answer


The remain tRFC2,4 should be accurate tho ?
I want to research a bit more on that topic when i have more time, but i updated the sheet to V2.3 
Fixed the failsafe value, was a calculation mistake of mine
You can try to bump tRFC value by the same amount your tRC is atm , if you have issues or by half of it
But i will need to investigate why it doesn't scale how it has to, in 32 steps


----------



## mongoled

Veii said:


> The remain tRFC2,4 should be accurate tho ?
> I want to research a bit more on that topic when i have more time, but i updated the sheet to V2.3
> Fixed the failsafe value, was a calculation mistake of mine
> You can try to bump tRFC value by the same amount your tRC is atm , if you have issues or by half of it
> But i will need to investigate why it doesn't scale how it has to, in 32 steps


TM5 passed on first attempt using exact same values except assigning first tRFC value as 252 and leaving tRFC2/4 on AUTO.

See screen shot

Needs further investigation, I am your disposal if you need me to try some different things out



** EDIT **
BCLK is 107.5625 not 107.625 ...


----------



## Veii

mongoled said:


> TM5 passed on first attempt using exact same values except assigning first tRFC value as 252 and leaving tRFC2/4 on AUTO.
> 
> See screen shot
> 
> Needs further investigation, I am your disposal if you need me to try some different things out
> ** EDIT **
> BCLK is 107.5625 not 107.625 ...


Hmm, soo with only tRFC1 across the whole range it doesn't fail but with 252-187-115 it does fail ?
Or did you run 288 before ?
What was your old result, i can't seem to find it directly 
Can you still grab SiSoftware Sandra, and make a tiny multi-core efficiency test ?
Filter to "my local scores" only and and show it as Detailed result with the graph please


----------



## mongoled

Veii said:


> Hmm, soo with only tRFC1 across the whole range it doesn't fail but with 252-187-115 it does fail ?
> Or did you run 288 before ?
> What was your old result, i can't seem to find it directly
> Can you still grab SiSoftware Sandra, and make a tiny multi-core efficiency test ?
> Filter to "my local scores" only and and show it as Detailed result with the graph please


Yes exactly this,

tRFC1 across the whole range == TM5 passes no issues

tRFC 252-187-115 == TM5 fails with different error codes with no apparent pattern 

Do you want me to run the Sandra with [email protected] across all values or with 252-187-115 ??


----------



## Veii

mongoled said:


> Yes exactly this,
> 
> tRFC1 across the whole range == TM5 passes no issues
> 
> tRFC 252-187-115 == TM5 fails with different error codes with no apparent pattern
> 
> Do you want me to run the Sandra with [email protected] across all values or with 252-187-115 ??


First with 252 across the whole range on the stable set
The issue is, tRFC 2 / 4 where accurate but let me try to manually calculate them using 3800MT/s as sample 

Can you just verify on warm boot change, if it really was tRFC2/4 as the issue and not bad training ?
Under AMD CBS inside UMC, or NBIO you should have somewhere MBIST - inside there PHY memory configuration and Data scrabling
Somewhere there should be an option called Testing pattern or Data-Eye mode, put it to data eye mode only 
Inside an SMU menu you should have APBDIS which you should put at 1 to force SOC P-State to stay at 0 without fluctuation
and inside DF should be an option called Memory Clear - Disable this one 

Failing tRFC2/4 would only be affected by GDM and so also tCKE value
Awkward indeed - as it is correctly calculated 
Oh i see tho that you should use either 8/1 or 7/3 under tRDWR & tWRRD 

The only reason i can see why you would get timeout issues with fixed tRFC 2 / 4, would be when the rest of the timings are wrong
But you are the first person that actually shows that tRFC2/4 are used even without GDM :thinking: 
Try if you can get 7/3 tRDWR/tWRRD stable with a written out tRFC1-2-4 
and if not , try if it will also fail on 8/1, 8/2 shouldn't be needed , even less on single rank units

I'll have to go out for the next 3-4h 
Please test around, but across the whole MT/s range, as long as tRC and MT/s is correct - tRFC2/4 should also be
Using tRC as baseline for calculation, shouldn't mess up with frequency differences - as timings after all are just placeholders multiplied by running MT/s (ns)


----------



## rastaviper

I am trying to optimise everything for benchmarks and so far only managed to reduce the TRC at 48 and TFAW at 12.
TWRWRSC/SD don't respond well at 5.

Any proposals?









Sent from my ONEPLUS A6003 using Tapatalk


----------



## mongoled

Veii said:


> First with 252 across the whole range on the stable set
> The issue is, tRFC 2 / 4 where accurate but let me try to manually calculate them using 3800MT/s as sample


OK 



Veii said:


> Can you just verify on warm boot change, if it really was tRFC2/4 as the issue and not bad training ?
> Under AMD CBS inside UMC, or NBIO you should have somewhere MBIST - inside there PHY memory configuration and Data scrabling
> Somewhere there should be an option called Testing pattern or Data-Eye mode, put it to data eye mode only
> Inside an SMU menu you should have APBDIS which you should put at 1 to force SOC P-State to stay at 0 without fluctuation
> and inside DF should be an option called Memory Clear - Disable this one


I am on x370.

Will run TM5 test again, than warm boot, than will run again ...

I cannot find this information in my BIOS.

The only thing I can find relevant to PHY is in the memory training section, the following values
DFE Read Training (Auto|Enabled|Disabled)
FFE Write Training (Auto|Enabled|Disabled)
PMU Pattern Bits (Integer value)
MR6VrefDQ (Integer value)
CPU Vref Training Seed (Integer value)



Veii said:


> Failing tRFC2/4 would only be affected by GDM and so also tCKE value
> Awkward indeed - as it is correctly calculated
> Oh i see tho that you should use either 8/1 or 7/3 under tRDWR & tWRRD
> 
> The only reason i can see why you would get timeout issues with fixed tRFC 2 / 4, would be when the rest of the timings are wrong
> But you are the first person that actually shows that tRFC2/4 are used even without GDM :thinking:
> Try if you can get 7/3 tRDWR/tWRRD stable with a written out tRFC1-2-4
> and if not , try if it will also fail on 8/1, 8/2 shouldn't be needed , even less on single rank units


I leave tRDWR & tWRRD on AUTO because I play with timing alot, so not to have non posting system I leave AUTO and then once system posted I enter the AUTO detected values manually....

Using values 8/1 lead to bluescreen on booting Windows or non successful entering OS
Using values 7/3 lead to non posting system, must rest BIOS

I have tCKE always on 1, would this effect non posting/unstable system when changing tRDWR & tWRRD values ?

Re GDM and tRFC2/4, didnt know this, have always used GDM disabled so never knew of such circumstane 



Veii said:


> I'll have to go out for the next 3-4h
> Please test around, but across the whole MT/s range, as long as tRC and MT/s is correct - tRFC2/4 should also be
> Using tRC as baseline for calculation, shouldn't mess up with frequency differences - as timings after all are just placeholders multiplied by running MT/s (ns)


No problem, do your jobs, I will do additional testing.


----------



## mongoled

rastaviper said:


> I am trying to optimise everything for benchmarks and so far only managed to reduce the TRC at 48 and TFAW at 12.
> TWRWRSC/SD don't respond well at 5.
> 
> Any proposals?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sent from my ONEPLUS A6003 using Tapatalk


I have a consistant "anomly" with AIDA64 bandwidth measurements on my two Windows OS.

Do not know why this happens and do not know if others are effected.

Basically it is like this.

If I go into the BIOS, does not matter if I change a value or not, on the next boot AIDA64 read throughput results loose something between 800-1200 mbytes/s

I simply reboot one more time and and results are where I expect them to be.

I have disabled "fast startup".

Just pointing this out.

Maybe you have reached the limits of your B-die memory, for sure there is a reason they were binned at 3200mhz ...


----------



## 2600ryzen

mongoled said:


> I have a consistant "anomly" with AIDA64 bandwidth measurements on my two Windows OS.
> 
> Do not know why this happens and do not know if others are effected.
> 
> Basically it is like this.
> 
> If I go into the BIOS, does not matter if I change a value or not, on the next boot AIDA64 read throughput results loose something between 800-1200 mbytes/s
> 
> I simply reboot one more time and and results are where I expect them to be.
> 
> I have disabled "fast startup".
> 
> Just pointing this out.
> 
> Maybe you have reached the limits of your B-die memory, for sure there is a reason they were binned at 3200mhz ...



When you leave the bios do you quit without saving so it doesn't restart or you do save settings and restart/retrain? I think this makes a difference on mine with inconsistent latency results.


----------



## mongoled

2600ryzen said:


> When you leave the bios do you quit without saving so it doesn't restart or you do save settings and restart/retrain? I think this makes a difference on mine with inconsistent latency results.


It depends,

sometimes I do CTRL-ALT-DEL

sometimes F10 --> enter.

I didnt check to see if there was any difference ....

Also I do a double reboot if I change settings, as the "anomoly" also gets triggered in the same manner.

Ive just made it a "must do" when doing any benhmark tests or tests that need to deliver consistant results to reboot twice.

Its a pain in the a.....

Was wondering if others had noticed this...


----------



## mongoled

@Veii

must be something to do with memory training issue and high BCLK.

TM5 is failing, where as the first time I posted the PC and tried it with just tRFC set to 252 it passed.

Must have been a chance occurance.

Since each subsequent reboot, TM5 errors with different error codes .......

** EDIT **
So for quick test I simply set tRFC to AUTO

On reboot AUTO values are 666-495-305

These values although so much more loose make TM5 error out after the 2nd pass with error code 2 and then 3

** EDIT2 **
OK, need to return to previous baselines, which means rolling back the BIOS to pre combo 1.0.0.6 just to rule out if its the BIOS that is causing all the funky stuff im seeing .....


----------



## heptilion

Veii said:


> Are you experiment friendy ?
> Can you try if this would work
> 
> 
> 
> 
> 
> 
> 
> 
> 
> There is barely anything you can tighten anymore except when you get tRCD RD 16 down to 15
> From now on you have to measure subtle differences with SiSoftware Sandra - Multi-Core efficiency test
> Filter to local results/my own - only , and compare the both results under the detailed tab
> Your stable one and this awkward one ~ if it would even post
> 
> Also the benchmark inside DRAM calculator - Draw Latency Curve, is important
> Set of timings might need more than 1.5v maybe up to 1.53, but test it with your current voltage atm


Didn't get time to work on these because i was getting some crashes while playing games last night. So decided to run some stability to tests to see whats going on. 
Tm5 20 tests, y cruncher 2 runs and memtest 850% single all passed. I am running prime 95 large fft atm and its passing but im getting a whea error in hwinfo64 for CPU Bus/Interconnect. 

Running with vscoc 1.075(hw info 1.056) proc odt 34.3 cad 40 20 24 24. Vddp .9 vddg ccd .95 iod 1.Not sure how to identify whats what.


----------



## Veii

rastaviper said:


> I am trying to optimise everything for benchmarks and so far only managed to reduce the TRC at 48 and TFAW at 12.
> TWRWRSC/SD don't respond well at 5.
> Any proposals?


Start with:








See what you need to run this (voltage vise and maybe 2T at worst ?)
later push SD DD's down to 5-5-7-7 
tRAS was too low at the start, needed to be at least 29, and tRC was just high without reasoning 
tCWL 14 ≠ tCL was preventing tRDWR to be low, and as it can only be an even value even without GDM, 16 would've been better
tCL 15 + tWR 12 + tBL 2 = 29 , 28 was too low 
EDIT:
Actually still push tCWL to 16 ~ forgot to add it
* rly need a better picture editor than ShareX 


mongoled said:


> I am on x370.
> 
> Will run TM5 test again, than warm boot, than will run again ...
> I cannot find this information in my BIOS.
> 
> The only thing I can find relevant to PHY is in the memory training section, the following values
> DFE Read Training (Auto|Enabled|Disabled)
> FFE Write Training (Auto|Enabled|Disabled)
> PMU Pattern Bits (Integer value)
> MR6VrefDQ (Integer value)
> CPU Vref Training Seed (Integer value)


Set PHY to this, to fix Memory Training issues after 1003ABBA
















*!* = important
*~* = not thaat important, but helpful

X370 same as latest X570 should have the same options inside CBS when/if it's fully open. IF depends on the manufactures current mood on bios release 


mongoled said:


> I leave tRDWR & tWRRD on AUTO because I play with timing alot, so not to have non posting system I leave AUTO and then once system posted I enter the AUTO detected values manually....
> 
> Using values 8/1 lead to bluescreen on booting Windows or non successful entering OS
> Using values 7/3 lead to non posting system, must rest BIOS


You shouldn't leave them alone, predictions still are messy
A tutorial was written back here
Dual rank only need tRCD RD/2 +2, but as 8-1 doesn't even work for you, try +1 on it. 9-1 will work, but i think the issue remains somewhere else


mongoled said:


> I have tCKE always on 1, would this effect non posting/unstable system when changing tRDWR & tWRRD values ?
> Re GDM and tRFC2/4, didnt know this, have always used GDM disabled so never knew of such circumstane


tCKE belongs to GDM, and defines the powestate on idle of the dimms
1 being always active, 6 being rapid suspend (intel users use this often), 9 being instant suspend
We like to keep it at 1  same as powerdown disabled
tCKE shouldn't actively do anything when GDM is disabled, but like tRFC2/4 (which is not directly used on ryzen) , they are still used as baseline to make other auto correction timings. Accuracy is key, soo it's good to enforce it


mongoled said:


> @Veii
> must be something to do with memory training issue and high BCLK.
> TM5 is failing, where as the first time I posted the PC and tried it with just tRFC set to 252 it passed.
> Must have been a chance occurance.
> Since each subsequent reboot, TM5 errors with different error codes .......
> 
> ** EDIT **
> So for quick test I simply set tRFC to AUTO
> On reboot AUTO values are 666-495-305
> These values although so much more loose make TM5 error out after the 2nd pass with error code 2 and then 3
> 
> ** EDIT2 **
> OK, need to return to previous baselines, which means rolling back the BIOS to pre combo 1.0.0.6 just to rule out if its the BIOS that is causing all the funky stuff im seeing .....


Error 3 belongs again to a mirror move error = timeout
2 is a 32mb transfer, but to up delay and occurence they either belong together or not. Memory will actively try to autocorrect but it often might not be able to.
Try to downgrade using Flashrom from here to keep it clean - but follow #4 to make a backup first
AfuEfi from 1usmus's BiosMod Thread works too, but flashrom does a full SPI wipe where nothing is left. It's just cleaner 


heptilion said:


> Didn't get time to work on these because i was getting some crashes while playing games last night. So decided to run some stability to tests to see whats going on.
> Tm5 20 tests, y cruncher 2 runs and memtest 850% single all passed. I am running prime 95 large fft atm and its passing but im getting a whea error in hwinfo64 for CPU Bus/Interconnect.
> 
> Running with vscoc 1.075(hw info 1.056) proc odt 34.3 cad 40 20 24 24. Vddp .9 vddg ccd .95 iod 1.Not sure how to identify whats what.


This is interesting, Maybe run y-cruncher for a longer time and be sure that it actually does all of it's test. 4 Loops are enough but it should show instability before the 2nd loop finishes 
Can you try to post with procODT 32 ? 
The only thing i can think off, is somehow loadline messing up vSOC making it drop under 1.05
Be it because of thermals, the psu, or just plain different workload


----------



## dansi

all you RAM clockers, have you seen the early previews of Renoir APU? Those can run ram past 4000+ with sync IF!


----------



## heptilion

Veii said:


> This is interesting, Maybe run y-cruncher for a longer time and be sure that it actually does all of it's test. 4 Loops are enough but it should show instability before the 2nd loop finishes
> Can you try to post with procODT 32 ?
> The only thing i can think off, is somehow loadline messing up vSOC making it drop under 1.05
> Be it because of thermals, the psu, or just plain different workload


Think ive managed to fix it by increasing vsoc to 1.1(actual value fluctuates between 1.075-1.085) with procodt 34.6.

I will try and see if procodt 32 works as well.

update: aaaaand now im getting audio issues playing youtube in chrome with hw accelaration off. random crackling not frequent but can notice when it pops. upped vddg ccd to 0.975 and iod 1.025 but no change. if i keep vddp .9 vddg but increase ccd .95 and vddg 1.05 ill have to increase vsoc even more( 1.1+ cus of my high vdroop) and then increase procodt to compensate that.


----------



## mongoled

Veii said:


> Try to downgrade using Flashrom from here to keep it clean - but follow #4 to make a backup first
> AfuEfi from 1usmus's BiosMod Thread works too, but flashrom does a full SPI wipe where nothing is left. It's just cleaner


Thanks for your detailed explanations, FYI I have collected most of your explnations of TM5 memory errors and will publish these sometime soon



Ive currently gone back to scratch as I need to determine whats going on

1/ BIOS flash fromm combo 1.0.0.4 to 1.0.0.6 did something funky
2/ Ryzen Master has done something funky to the BIOS
3/ Playing with ODT values when using 4 dimms has effected the CPU somehow
3/ Playing with ODT values when using 4 dimms has effected the motherboard somehow
4/ Playing with high BCLK has effected CPU/motherboard
5/ Playing with EDC bug has effected CPU/motherboard
6/ Some other newly introduced hardware issue i.e. failing PSU

Im just seeing tooooooo many strange things.

i.e. 

Before @3800/1900 I needed 0.955v for VDDP now 0.805v is sufficient

Before @3800/1900 I needed 1.035v for VDDG IOD to stop audio audio issues now less than 1.0v there are no audio issues 

Using vSOC of 1.1v now leads to PC reboots when running TM5, for the record I never used this much voltage for vSOC, maximum I used was 1.080v

Also, have seen my BIOS menu randomly all turn to chinese characters and than randomly freeze, after posting a 2nd time things turn to "normal"

Also, when I first flashed the BIOS to 1.0.0.6, when using offset for vSOC, for reasons unknown to me it pumped according to BIOS over 1.2v to vSOC. I caught this almost straight away. It would not fix itself with a re-post. I had to manually set the vSOC voltage to some value manually, drop mclk/fclk down to say 3200/1600. After this vSOC started behaving.

Its as if something on the agesa BIOS upgrade had some tables crossed.

Maybe that +1.2v on the vSOC damaged the CPU.

Toooooo many variables.

Re FLASHROM, before I go down this avenue.

I first

1/ Uninstaled Ryzen Master
2/ Enter BIOS, reset to default
3/ Reboot, enter BIOS use MSI flash utility to re-flash BIOS
4/ Reboot use MSI BIOS recovery utility to re-flash BIOS

Fucccc,

System rebooted while typing this (was running TM5), thankfully Firefox recovered that txt i had written!

Looks like I will flash with FLASHROM, im beginning to think the CPU got damaged with the +1.2v vSOC ....


----------



## rares495

mongoled said:


> Thanks for your detailed explanations, FYI I have collected most of your explnations of TM5 memory errors and will publish these sometime soon
> 
> 
> 
> Ive currently gone back to scratch as I need to determine whats going on
> 
> 1/ BIOS flash fromm combo 1.0.0.4 to 1.0.0.6 did something funky
> 2/ Ryzen Master has done something funky to the BIOS
> 3/ Playing with ODT values when using 4 dimms has effected the CPU somehow
> 3/ Playing with ODT values when using 4 dimms has effected the motherboard somehow
> 4/ Playing with high BCLK has effected CPU/motherboard
> 5/ Playing with EDC bug has effected CPU/motherboard
> 6/ Some other newly introduced hardware issue i.e. failing PSU
> 
> Im just seeing tooooooo many strange things.
> 
> i.e.
> 
> Before @3800/1900 I needed 0.955v for VDDP now 0.805v is sufficient
> 
> Before @3800/1900 I needed 1.035v for VDDG IOD to stop audio audio issues now less than 1.0v there are no audio issues
> 
> Using vSOC of 1.1v now leads to PC reboots when running TM5, for the record I never used this much voltage for vSOC, maximum I used was 1.080v
> 
> Also, have seen my BIOS menu randomly all turn to chinese characters and than randomly freeze, after posting a 2nd time things turn to "normal"
> 
> Also, when I first flashed the BIOS to 1.0.0.6, when using offset for vSOC, for reasons unknown to me it pumped according to BIOS over 1.2v to vSOC. I caught this almost straight away. It would not fix itself with a re-post. I had to manually set the vSOC voltage to some value manually, drop mclk/fclk down to say 3200/1600. After this vSOC started behaving.
> 
> Its as if something on the agesa BIOS upgrade had some tables crossed.
> 
> Maybe that +1.2v on the vSOC damaged the CPU.
> 
> Toooooo many variables.
> 
> Re FLASHROM, before I go down this avenue.
> 
> I first
> 
> 1/ Uninstaled Ryzen Master
> 2/ Enter BIOS, reset to default
> 3/ Reboot, enter BIOS use MSI flash utility to re-flash BIOS
> 4/ Reboot use MSI BIOS recovery utility to re-flash BIOS
> 
> Fucccc,
> 
> System rebooted while typing this (was running TM5), thankfully Firefox recovered that txt i had written!
> 
> Looks like I will flash with FLASHROM, im beginning to think the CPU got damaged with the +1.2v vSOC ....



Yup, 1.2V+ SOC was a bad idea.


----------



## mongoled

It was not my idea!

The BIOS decided to do that by itself!


----------



## rares495

mongoled said:


> It was not my idea!
> 
> The BIOS decided to do that by itself!



Perhaps that's what happens when you play with too high BCLK


----------



## mongoled

rares495 said:


> Perhaps that's what happens when you play with too high BCLK


Doubt it,

It happened at BIOS defaults.

Directly after I flashed from 1.0.0.4 to 1.0.0.6

...........

I am sure you have seen the "pre-determined" values that are applied to vSOC based on mclk/fclk frequency ?

When I upped to 3800/1900 it did the vSOC "boost of death"


----------



## 2600ryzen

mongoled said:


> Thanks for your detailed explanations, FYI I have collected most of your explnations of TM5 memory errors and will publish these sometime soon
> 
> 
> 
> Ive currently gone back to scratch as I need to determine whats going on
> 
> 1/ BIOS flash fromm combo 1.0.0.4 to 1.0.0.6 did something funky
> 2/ Ryzen Master has done something funky to the BIOS
> 3/ Playing with ODT values when using 4 dimms has effected the CPU somehow
> 3/ Playing with ODT values when using 4 dimms has effected the motherboard somehow
> 4/ Playing with high BCLK has effected CPU/motherboard
> 5/ Playing with EDC bug has effected CPU/motherboard
> 6/ Some other newly introduced hardware issue i.e. failing PSU
> 
> Im just seeing tooooooo many strange things.
> 
> i.e.
> 
> Before @3800/1900 I needed 0.955v for VDDP now 0.805v is sufficient
> 
> Before @3800/1900 I needed 1.035v for VDDG IOD to stop audio audio issues now less than 1.0v there are no audio issues
> 
> Using vSOC of 1.1v now leads to PC reboots when running TM5, for the record I never used this much voltage for vSOC, maximum I used was 1.080v
> 
> Also, have seen my BIOS menu randomly all turn to chinese characters and than randomly freeze, after posting a 2nd time things turn to "normal"
> 
> Also, when I first flashed the BIOS to 1.0.0.6, when using offset for vSOC, for reasons unknown to me it pumped according to BIOS over 1.2v to vSOC. I caught this almost straight away. It would not fix itself with a re-post. I had to manually set the vSOC voltage to some value manually, drop mclk/fclk down to say 3200/1600. After this vSOC started behaving.
> 
> Its as if something on the agesa BIOS upgrade had some tables crossed.
> 
> Maybe that +1.2v on the vSOC damaged the CPU.
> 
> Toooooo many variables.
> 
> Re FLASHROM, before I go down this avenue.
> 
> I first
> 
> 1/ Uninstaled Ryzen Master
> 2/ Enter BIOS, reset to default
> 3/ Reboot, enter BIOS use MSI flash utility to re-flash BIOS
> 4/ Reboot use MSI BIOS recovery utility to re-flash BIOS
> 
> Fucccc,
> 
> System rebooted while typing this (was running TM5), thankfully Firefox recovered that txt i had written!
> 
> Looks like I will flash with FLASHROM, im beginning to think the CPU got damaged with the +1.2v vSOC ....



Go through your AMD overclocking menu and make sure everything's auto, that's where ryzen master settings are stored on my system.


----------



## mongoled

2600ryzen said:


> Go through your AMD overclocking menu and make sure everything's auto, that's where ryzen master settings are stored on my system.


This BIOS does not have an "AMD Overclocking Menu"

I remember in the very first BIOSs for my motherboard there was such a section, but it got removed a while back.

Some of the items that were in this section were lumped in the "Advanced CPU" section, but most of the AMD CBS stuff is missing 

:/

FLASHROM BIOS flash did not change anything,

Looks like I am going to have to purchase some new hardware to work out what is going on ...

Have a new 3600X upstairs for a clients build that is dated 2023, will play with that on the X570 motherboard I bought for the build, I can at least check my 4 x 8GB Viper dimms to see how they act on the X570 ....

Right now I am running VDDP @ 0.780v (3800/1900 know good settings, PBO disabled) to see if the system reboots while running TM5 .... 0.770v fails to post, so I am right at the edge.

Need to narrow down what causes the main instability than may be able to work out what got damaged ...


----------



## Veii

rares495 said:


> Yup, 1.2V+ SOC was a bad idea.
> 
> 
> mongoled said:
> 
> 
> 
> It was not my idea!
> The BIOS decided to do that by itself!
> 
> 
> rares495 said:
> 
> 
> 
> Perhaps that's what happens when you play with too high BCLK
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

Some bioses indeed push >1.3vSOC or 1.2+ cLDO_VDDG early on by default 
It's far to high , and vSOC can not be less than 1.25v if VDDG is that high 

But the CPU shouldn't degrade by 1.2vSOC , only 1.3+ 
Well if it pushes 1.25v VDDG it might exceed 1.3vSOC  

PSP Firmware on the Units updates between AGESAs, and as 1.0.0.5/1.0.0.6 changed quite a few things and lowered voltages
It can be, that the recommended values are now far lower
Although 800mV cLDO_VDDP is low  
This would require double 75mV stepping everywhere
VDDP 800
VDDG 950
VSOC 1100 is double 75mV

I am not sure if the units would like 900mV VDDG and 1v VSOC only 
even if you use 125mV stepping
800-925-1050 , it could be strange 
Although, remain with identical voltage jumps across them - if you decide to use higher "stepping/voltage jumps"

Flashrom will wipe the whole flashchip
soo if you decide to do it , downgrade strongly to 1003A, then upgrade normally to 1003ABBA and only afterwards decide if you want 1004B or 1006/1002v2
Usually 1003ABB is the place where you got a Pcie 4.0 lockdown and a big PSP Firmware update was made
But 1003ABBA should be fine enough als middle step, before you continue beyond 1004


----------



## mongoled

Veii said:


> Some bioses indeed push >1.3vSOC or 1.2+ cLDO_VDDG early on by default
> It's far to high , and vSOC can not be less than 1.25v if VDDG is that high
> 
> But the CPU shouldn't degrade by 1.2vSOC , only 1.3+
> Well if it pushes 1.25v VDDG it might exceed 1.3vSOC
> 
> PSP Firmware on the Units updates between AGESAs, and as 1.0.0.5/1.0.0.6 changed quite a few things and lowered voltages
> It can be, that the recommended values are now far lower
> Although 800mV cLDO_VDDP is low
> This would require double 75mV stepping everywhere
> VDDP 800
> VDDG 950
> VSOC 1100 is double 75mV
> 
> I am not sure if the units would like 900mV VDDG and 1v VSOC only
> even if you use 125mV stepping
> 800-925-1050 , it could be strange
> Although, remain with identical voltage jumps across them - if you decide to use higher "stepping/voltage jumps"
> 
> Flashrom will wipe the whole flashchip
> soo if you decide to do it , downgrade strongly to 1003A, then upgrade normally to 1003ABBA and only afterwards decide if you want 1004B or 1006/1002v2
> Usually 1003ABB is the place where you got a Pcie 4.0 lockdown and a big PSP Firmware update was made
> But 1003ABBA should be fine enough als middle step, before you continue beyond 1004


I did it, with FLASHROM, flashed direct the latest verion that is 1.0.0.6, no difference.

The thing is even previous BIOS is acting different (when flashed with regular method), may have to also try FLASHROM to 1.0.0.4 agesa BIOS to 100% rule out BIOS flash issue.

And the thing, very rarely I can get a 25 cycles TM5 run finished at 3800/1900, but not consistently

And as explained the error codes are different even when I dont change any settings.

No real pattern as I keep explaining.

My PSU is several years old, maybe need to test with different PSU ...

:/

Will follow the flash guidance you have offered as the final steps ...


----------



## Veii

mongoled said:


> I did it, with FLASHROM, flashed direct the latest verion that is 1.0.0.6, no difference.
> The thing is even previous BIOS is acting different (when flashed with regular method), may have to also try FLASHROM to 1.0.0.4 agesa BIOS to 100% rule out BIOS flash issue.
> And the thing, very rarely I can get a 25 cycles TM5 run finished at 3800/1900, but not consistently


I suspect, AMD did low level changes (PSP Firmware) as a result to have now consistent behavior on lower versions

About the Chinese Bios bug, i had that once on the B350 Toma
Memory timings where soo broken, that the main core-bootloader (before the bios) froze
It crashed soo much, that the cpu mentioned PSP FW Reset enforced, please remove the cpu and put it back in to reset PSP Firmware
the bios turned chinese later 

I have something similar on a X399 Bios, where the boot-order menu is fully broken and freezes
Quite funny 

But no, PSP Firmware update is not a bad thing ~ except preventing us to use PCIe 4.0 and having to buy overpriced B550 Boards :ninja:
Go back to 1003ABBA if you want , or 1004B IF AMD Overclocking menu exists there
Your variable results mostly belong to bad memory training and maybe PSU idle instability - but AMD CBS has an option for that one too
Just fix memory training through AMD CBS , and enforce every RTT, CAD_BUS, Voltage value (except vCore) 
Soo we have no variability and skip bios bugs

I don't think i'll have the time to fully open the latest or 1004B bios for you, but if you are experiment friendly 
The WinRaid forum has tutorials on how to work with APTIO bioses 
Overall, when you fix everything under CBS, the bios version rarely matters
We had no PMU (memory training algorythm) updates since mid 2018 
Only more and new extended features with new microcodes to assist with them
I see no reason why an old 1003ABBA with replaced microcode can't be as great of an overclocker, as 1005/1006 version

PSP firmware once updated, remains in the CPU - you might be able to gain write access to it, 
but unless you clearly know what you do , i don't suggest to explore that path further ~ as you can't flash an ARM chip inside the sillicon


----------



## mongoled

Veii said:


> I suspect, AMD did low level changes (PSP Firmware) as a result to have now consistent behavior on lower versions
> 
> About the Chinese Bios bug, i had that once on the B350 Toma
> Memory timings where soo broken, that the main core-bootloader (before the bios) froze
> It crashed soo much, that the cpu mentioned PSP FW Reset enforced, please remove the cpu and put it back in to reset PSP Firmware
> the bios turned chinese later
> 
> I have something similar on a X399 Bios, where the boot-order menu is fully broken and freezes
> Quite funny
> 
> But no, PSP Firmware update is not a bad thing ~ except preventing us to use PCIe 4.0 and having to buy overpriced B550 Boards :ninja:
> Go back to 1003ABBA if you want , or 1004B IF AMD Overclocking menu exists there
> Your variable results mostly belong to bad memory training and maybe PSU idle instability - but AMD CBS has an option for that one too
> Just fix memory training through AMD CBS , and enforce every RTT, CAD_BUS, Voltage value (except vCore)
> Soo we have no variability and skip bios bugs
> 
> I don't think i'll have the time to fully open the latest or 1004B bios for you, but if you are experiment friendly
> The WinRaid forum has tutorials on how to work with APTIO bioses
> Overall, when you fix everything under CBS, the bios version rarely matters
> We had no PMU (memory training algorythm) updates since mid 2018
> Only more and new extended features with new microcodes to assist with them
> I see no reason why an old 1003ABBA with replaced microcode can't be as great of an overclocker, as 1005/1006 version
> 
> PSP firmware once updated, remains in the CPU - you might be able to gain write access to it,
> but unless you clearly know what you do , i don't suggest to explore that path further ~ as you can't flash an ARM chip inside the sillicon


Great info!

The newer BIOS allow me to BCLK



Older BIOS, nope ....

I have setting for PSU idle its currently in "CPU Features" section and I have that set to "normal" rathar than "low" as I remember leaving this on auto was causing the 3600 to lock up in Windows when no load was being placed on it and this occured when I first got the CPU and was running default BCLK and agesa 1.0.0.4 ....


----------



## Veii

mongoled said:


> Great info!
> 
> The newer BIOS allow me to BCLK
> 
> Older BIOS, nope ....


This might come out of nowhere
But do you think, you can make a closeup of the board near the Flash-Chip 
In order to check which and how many "clockgens" you have 
Quote in Post https://www.overclock.net/forum/11-...chi-overclocking-thread-765.html#post28471378 shows how it kinda looks like
Or just search for Renesas 9VRS4883BKLF - to get a picture 
EDIT:








picture by JP-Review Site

The CH6 has two of them one for the storage/PCIe and one for the CPU
The Taichi is based on the same PCB but misses one - soo we can not go fully decoupled mode, except by manually lowering Storage Link speed to 93Mhz instead of 100

Question remains, 
Does your board have two of them ~ if so i can take a look inside the bios to explore if you have a module for access to them and maybe port it back
or does it just have one - where this BLCK is the same "fake" BLCK OC we could do on the Taichi, by lowering the link speed to the GPU/Storage and increasing with one clockgen the main BLCK


----------



## mongoled

Veii said:


> This might come out of nowhere
> But do you think, you can make a closeup of the board near the Flash-Chip
> In order to check which and how many "clockgens" you have
> Quote in Post https://www.overclock.net/forum/11-...chi-overclocking-thread-765.html#post28471378 shows how it kinda looks like
> Or just search for Renesas 9VRS4883BKLF - to get a picture
> EDIT:
> picture by JP-Review Site
> 
> The CH6 has two of them one for the storage/PCIe and one for the CPU
> The Taichi is based on the same PCB but misses one - soo we can not go fully decoupled mode, except by manually lowering Storage Link speed to 93Mhz instead of 100
> 
> Question remains,
> Does your board have two of them ~ if so i can take a look inside the bios to explore if you have a module for access to them and maybe port it back
> or does it just have one - where this BLCK is the same "fake" BLCK OC we could do on the Taichi, by lowering the link speed to the GPU/Storage and increasing with one clockgen the main BLCK


Thanks for the offer, but I highly doubt this motherboard has two clockgen as when it was released the motherboard reviews said that it did not even have one and that for a "flagship" overclocking motherboard was a big let down.

After some BIOS updates, BCLK became available so I am unsure how that was achieved I am guessing its through software (fake BCLK OC )???

I took some pictures of the areas and zoomed on ICs then google but non of those I could photo had anything to do with clockgen and as my motherboard is covered with a full motherboard waterblock there are many ICs I cannot get access to unless I completly strip down the whole system which I dont plan doing at this moment in time.


----------



## hmeh

@Veii, I could really use your help on this one, if you please. I started out just trying to get decent timings at IF1900 and I'm now seeing rare errors on Karhu (error at 3600%). I've previously run 12000% successfully with this config (what is in screenshot + tRFC 282), so I'm not sure why it's erroring now.

I'm about to try raising tRFC quite a bit to 329 from 282 (282 is where I saw the error). What can I change to improve rare karhu errors? I've never seen a crash during normal use (I am not a gamer)

I've got 3950x, x570 AORUS Master.


----------



## Veii

hmeh said:


> @Veii, I could really use your help on this one, if you please. I started out just trying to get decent timings at IF1900 and I'm now seeing rare errors on Karhu (error at 3600%). I've previously run 12000% successfully with this config (what is in screenshot + tRFC 282), so I'm not sure why it's erroring now.
> 
> I'm about to try raising tRFC quite a bit to 329 from 282 (282 is where I saw the error). What can I change to improve rare karhu errors? I've never seen a crash during normal use (I am not a gamer)
> 
> I've got 3950x, x570 AORUS Master.


I'm sorry, i don't have experience with Karhu
Karhu with cache can also error for voltage reasons, where you need to confirm stability with Y-Cruncher all tests 2-3 cycles, and/or Prime95 Large FFT 2-3hours

cLDO_VDDP as 1v looks to be far to high, but the voltage set has a scalling of 50mV, soo it probably is fine
Although i'm not understanding the reason for the overvolt of the IMC

Timings:








I didn't see if you have 4x 8Gb or two times dual rank
Although 48 procODT is high, could be dual rank B2 kits maybe 
tWTR_ stuff is high because of ?

Black numbers are overwrites, 
no color = use what you have
green in this case, is a stepup 

Reason for erroring can be a timeout issue
You use GDM, soo tRFC2/4 are important - tRFC 2 on your side is misscalculated (like always) 
tWRRD should be 3 not 4, as you have no tRCD that exceeds 16 - soo 4*3=12 is the closest that will work well, explanation here
Optimally you should try to increase ClkDrvStrengh (first cad_bus value) near 60-120ohm on Dual Rank, helping you disable GDM and helping you lower procODT
Or you try and check how much vDIMM is needed so you can get CL14 to run


----------



## hmeh

Veii said:


> I'm sorry, i don't have experience with Karhu
> Karhu with cache can also error for voltage reasons, where you need to confirm stability with Y-Cruncher all tests 2-3 cycles, and/or Prime95 Large FFT 2-3hours


Interesting, I can also try disabling cache, I forgot about this fact. Which TM5 profile do you recommend testing for stability?




Veii said:


> cLDO_VDDP as 1v looks to be far to high, but the voltage set has a scalling of 50mV, soo it probably is fine
> Although i'm not understanding the reason for the overvolt of the IMC


Which one is IMC voltage, SOC or VDDG or something else? What would you recommend I try?



Veii said:


> I didn't see if you have 4x 8Gb or two times dual rank
> Although 48 procODT is high, could be dual rank B2 kits maybe
> tWTR_ stuff is high because of ?


Yes, 2x16GB. Not sure on tWTR, I think I started w/ DRAM calc, but it's been a while.



Veii said:


> Reason for erroring can be a timeout issue
> You use GDM, soo tRFC2/4 are important - tRFC 2 on your side is misscalculated (like always)


Wow, I didn't know that, why doesn't anyone say that. I'll try setting those too.



Veii said:


> tWRRD should be 3 not 4, as you have no tRCD that exceeds 16 - soo 4*3=12 is the closest that will work well, explanation here


Thanks



Veii said:


> Optimally you should try to increase ClkDrvStrengh (first cad_bus value) near 60-120ohm on Dual Rank, helping you disable GDM and helping you lower procODT


I can get GDM off to post with 60 ohm, but it errors in karhu quickly. Will increasing that further help?



Veii said:


> Or you try and check how much vDIMM is needed so you can get CL14 to run


1.52V is the lowest I can get it to post on, which seems high to me. I never stability tested it because I didn't see any uptick perfwise in AIDA test, but maybe other things needed to be tuned as well to really see that. I'm not a gamer, so I'm more interested in stability than making the top of the spreadsheet, will I get much benefit from CL14? Enough to justify 1.52V?

Thank you for the detailed reply.


----------



## Veii

dansi said:


> all you RAM clockers, have you seen the early previews of Renoir APU? Those can run ram past 4000+ with sync IF!


X̶T̶ ̶3̶x̶x̶x̶ ̶u̶n̶i̶t̶s̶ ̶c̶a̶n̶ ̶t̶o̶o̶ 
Only X units would also be, if we wheren't artificially locked by AMD
But Renoir will run them desynced and only sync up to workload ~ it will be variable 
OCing that one will be fun
EDIT:
Redacted, as sample of proof could be a faked or other OCers result outweight the possibility
~ making it either a golden sample or unpublished method in "how" 
soo not recommended to buy till confirmed personally otherwise :ninja:


hmeh said:


> Interesting, I can also try disabling cache, I forgot about this fact. Which TM5 profile do you recommend testing for stability?


Use TM5 1usmus_V3 with >20 cycles
Reuploaded here

Disabling cache mode only makes sense, if you try to stabilize 5000-6000MT/s memory, where only checking the timings make sense
But cache mode not only is faster, but tests the stability of the memory controller



hmeh said:


> Which one is IMC voltage, SOC or VDDG or something else? What would you recommend I try?


cLDO_VDDP = memory controller
cLDO_VDDG = Fabric voltage
VDDG CCD = voltage inside the CCD between CCX
VDDG IOD = voltage from the IOD-die toward the board. Covers the PCIe link, covers the link towards the DIMM channels
vSOC = System on Chip voltage = cLDO_VDDP & VDDG voltage together (a fixed scaling pattern between them exist)



hmeh said:


> Yes, 2x16GB. Not sure on tWTR, I think I started w/ DRAM calc, but it's been a while.


Then my predictions are fine for the set
tWTR_ and tRRD_ belong to the delay between banks and groups on a read and write operation 
Higher density or very bad kits, will require higher values
Just tWTR_L is predicted a bit too high by default



hmeh said:


> Wow, I didn't know that, why doesn't anyone say that. I'll try setting those too.


No one talks about this, as people are used to the Truth that 2x and 4x slowed mode is not used on ryzen
According to DDR4 spec, these only are enabled after 85c
Which i think is partially true, as it depends on the dataset and DRAM operation which changes in realtime 
(you have access to only half of the timings as fixed values, the other halfs are realtime variables)

tRFC 2 / 4 is not directly used, but it indeed is used for math
It goes together with tCKE and changes tMRD & tMOD state
Accuracy here is key, as they are used to backwards calculate tRFC , while tREFI maximum refresh interval/cycle is calculated by tRFC
Overall a little chain - soo a messed up calculation here, breaks stability. Doesn't matter what tRFC value you you (it does a bit to hit a good sync) , you still have to calculate correct tRFC2/4 or use tRFC 1 across all 3 
Else you get strange rounding errors

tCKE technically is also only used when GDM is enabled, but it isn't doing nothing unless powerdown is also disabled



hmeh said:


> I can get GDM off to post with 60 ohm, but it errors in karhu quickly. Will increasing that further help?


60-20-20-24 ? 
You can go up to 120 even, but maybe start with GDM off & 2T 
GDM does also push the internal mux chip on half clock operation, which technically makes it as 1.5T 
But this has negatives of rounding timings up. Soo if you do all calculations by hand - it's more accurate to work with 2T and perf still will be better than GDM on
Although that pushes nearly double stress on the memory, but not on the memory controller



hmeh said:


> 1.52V is the lowest I can get it to post on, which seems high to me. I never stability tested it because I didn't see any uptick perfwise in AIDA test, but maybe other things needed to be tuned as well to really see that. I'm not a gamer, so I'm more interested in stability than making the top of the spreadsheet, will I get much benefit from CL14? Enough to justify 1.52V?
> 
> Thank you for the detailed reply.


That's not even that high, but it depends on the PCB yours chips are on - if >1.48v has positive or negative scaling
Degradation won't happen that early (well it can't even without heat degradation, as this is not silicon) 
B-Dies can start to crash on 1.56v, and up to PCB and IC binning some might not like anything over 1.46v
Dual rank will be even more sensitive to higher VDIMM, but that doesn't mean that the voltage is dangerous ~ just has negative scaling effects

You can lower voltage requirements by higher tRFCand higher tRP (row p/recharge) delay. And so the opposite, lower tRP helping you reach lower tRC and lower tRFC, which requires higher vDIMM
Overall, less VDIMM the better
But GDM disabled would be useful for tCL 15 for example


----------



## hmeh

Veii said:


> cLDO_VDDP = memory controller
> cLDO_VDDG = Fabric voltage
> VDDG CCD = voltage inside the CCD between CCX
> VDDG IOD = voltage from the IOD-die toward the board. Covers the PCIe link, covers the link towards the DIMM channels
> vSOC = System on Chip voltage = cLDO_VDDP & VDDG voltage together (a fixed scaling pattern between them exist)


Okay, so try lowering VDDP some and see if that still posts? Will lowering VDDP
affect intermittent errors?

Edit: 900 VDDP (auto) appears stable. Currently running TM5 with your green numbers and so far so good (17 passes, will run more after experimenting with other things). What would you recommend after that? tCL15/14 or lower tRFC?

Any concerns about 1050 VDDG? I don't remember if I worked that down to the lowest it could go w/ FCLK 1900.




Veii said:


> No one talks about this, as people are used to the Truth that 2x and 4x slowed mode is not used on ryzen
> According to DDR4 spec, these only are enabled after 85c
> Which i think is partially true, as it depends on the dataset and DRAM operation which changes in realtime
> (you have access to only half of the timings as fixed values, the other halfs are realtime variables)
> 
> tRFC 2 / 4 is not directly used, but it indeed is used for math


How do I calculate tRFC 2 / 4? Is it a set formula?




Veii said:


> tCKE technically is also only used when GDM is enabled, but it isn't doing nothing unless powerdown is also disabled


I have Powerdown disabled, as recommended by calculator. Is this okay?




Veii said:


> 60-20-20-24 ?


Yes, or maybe 60-20-20-20, I don't remember.

I experimented with turning GDM off. These are the steps I took:

ClkDrvStren 120 + GDM off - no boot into windows
VDDR 1.46 - crash immediately in tm5
VDDR 1.52 - bsod immediately in tm5
ProcODT 53.3, *Setup 63 - tm5 errors: 0,2,6,7,12 (max temp 43.9)

So I can probably lower voltage back down and I don't know if it was ProcODT or *Setup that made the difference. I got the *Setup setting from another post of someone successfully getting GDM off with my same kit, I believe. Is that setting safe? Any other recommendations to get GDM off stable?



Veii said:


> That's not even that high, but it depends on the PCB yours chips are on - if >1.48v has positive or negative scaling
> Degradation won't happen that early (well it can't even without heat degradation, as this is not silicon)
> B-Dies can start to crash on 1.56v, and up to PCB and IC binning some might not like anything over 1.46v
> Dual rank will be even more sensitive to higher VDIMM, but that doesn't mean that the voltage is dangerous ~ just has negative scaling effects
> 
> You can lower voltage requirements by higher tRFCand higher tRP (row p/recharge) delay. And so the opposite, lower tRP helping you reach lower tRC and lower tRFC, which requires higher vDIMM
> Overall, less VDIMM the better
> But GDM disabled would be useful for tCL 15 for example



1.52v seemed to work, but temps got higher more quickly. It's a bit warm in my
house (no AC and summer) so I'm hesitant to introduce more heat. Of course,
Karhu makes quite a bit more heat than my normal day-to-day usage, I believe.

If I want to lower tRFC after raising VDIMM where do I go next?

Edit: I ran with tCL 14 (GDM on) and all the other timings the same. I had 1 error after 25 tm5 cycles in test 7, 2:38 minutes into a 2:55 minute run. What could I tweak to get that stable? That seems close. I wouldn't have seen an error w/ only 21 or so cycles. I wonder if that's temperature related, I forgot to check my max temp before rebooting.



Veii said:


> Karhu with cache can also error for voltage reasons, where you need to confirm stability with Y-Cruncher all tests 2-3 cycles, and/or Prime95 Large FFT 2-3hours


If this fails is my voltage too high or too low? and specifically the VDDP is the concern? I think my bios lets me set it to anything, what would you expect me to be able to set it to? (edit: as above, I set vddp to auto and mobo goes to 900 and that seems fine)


----------



## glnn_23

Veii said:


> Can you benchmark how this set compares ?
> 
> 
> 
> 
> 
> 
> 
> 
> If you have post issues, increase VDIMM to 1.48 and/or push tWTR_L back to 12



Thanks for your help Veii. Unfortunately the mb won't let me set tRCDWR as low 7 and 8 seems to be the limit. 

Also tRDWR set to 7 will not post.


----------



## 2600ryzen

Veii said:


> XT 3xxx units can too
> Only X units would also be, if we wheren't artificially locked by AMD
> But Renoir will run them desynced and only sync up to workload ~ it will be variable
> OCing that one will be fun



XT cpu's can do 2000mhz+ fclk? How are the X cpu's artificially locked?


----------



## Veii

glnn_23 said:


> Thanks for your help Veii. Unfortunately the mb won't let me set tRCDWR as low 7 and 8 seems to be the limit.
> 
> Also tRDWR set to 7 will not post.


Just to confirm, you set everything at once ~ correct ?
tRCDWR as 7 not working is unfortunate - i need to redo the whole set then as the average latency on tRCD between both WRite and ReaD is awkward. I get 10.5 out instead of 11, it can make issues
But alright, then the slower way 
Just please confirm to me that you tried the set as a big one 

Try the same set with tRCD WR 9 
tRP will still be 12 as AVG tRCD latency between 9 and 15 = 12
that should work with tRDWR 7 and tWRRD 4 then 

If you still face post issues and between 1.44-1.52v dimm nothing happens 
(always make a trashcan profile, soo you can restore on cmos clear the whole memory training settings ~ PHY, and voltages)
Try 1.44v, 1.46, 1.48, 1.52vDIMM 
Keep in mind, anything on auto except vCore will be an issue 

Yes, if nothing happens, i will need to redo your whole set with tRCD 16 
But then you will have to closely benchmark for subtle differences with SiSoftware Sandra and DRAM Calculator benchmark + it's latency curve


hmeh said:


> Okay, so try lowering VDDP some and see if that still posts? Will lowering VDDP
> affect intermittent errors?
> 
> Edit: 900 VDDP (auto) appears stable. Currently running TM5 with your green numbers and so far so good (17 passes, will run more after experimenting with other things). What would you recommend after that? tCL15/14 or lower tRFC?


Auto only since recently is 900mV cLDO_VDDP , there is a CPU VDDP ~ don't confuse them 
Lower VDDP and so also lower procODT decreases the stress on the memory controller 
Which results (like it was usually the case on first two gens) in higher maximum FCLK limit 


hmeh said:


> Any concerns about 1050 VDDG? I don't remember if I worked that down to the lowest it could go w/ FCLK 1900.


Up to AGESA the recommended voltages vary , but take a closer look here 
The bottom part of the post , but maybe the whole response would be helpful to you.


hmeh said:


> How do I calculate tRFC 2 / 4? Is it a set formula?


There is a tiny little tool that exists for this kind of work:
https://docs.google.com/spreadsheets/d/1A7G97QOL0dNMwJZa9SYEq2RElJ5T6Hcx9WdReTsnIWw/
The 2nd sheet ~ Pre-Release one has a Manual mode, just put in either your desired tRFC in ns (if you know your target)
Or directly the whole number and fill in the first 3 fields (Frequency, tCL, tRC)
There is a formula if you click on the tRFC fields and try to check the math (should let you i hope)
But it has to always be done from the start in ns, else you get stacking rounding errors
Math:
You turn tRFC to ns first
((tRFCns * MT/s) / 2000) = tRFC
((tRFCns * MT/s) / 2000)/1.346 = tRFC2
((tRFCns * MT/s) / 2000)/2.1875 = tRFC4

If you keep converting and back converting tRFC virtual number, you will get rounding errors 
It is key to either use MCLK or MT/s as main baseline for accuracy.
And accuracy will be kept accurate when you get tRFCns correct
= ((tRFC / MT/s) * 2000)

Well explore the sheet, you should be able to understand it 


hmeh said:


> I have Powerdown disabled, as recommended by calculator. Is this okay?


No issues here
No issues either having it enabled, you just have to work more accurate with tRFC, tCKE and memory might need a bit of time to wake up on powerdown
Can be pretty much always disabled, doesn't matter that much


hmeh said:


> Yes, or maybe 60-20-20-20, I don't remember.
> I experimented with turning GDM off. These are the steps I took:
> 
> ClkDrvStren 120 + GDM off - no boot into windows
> VDDR 1.46 - crash immediately in tm5
> VDDR 1.52 - bsod immediately in tm5
> ProcODT 53.3, *Setup 63 - tm5 errors: 0,2,6,7,12 (max temp 43.9)
> 
> So I can probably lower voltage back down and I don't know if it was ProcODT or *Setup that made the difference. I got the *Setup setting from another post of someone successfully getting GDM off with my same kit, I believe. Is that setting safe? Any other recommendations to get GDM off stable?


Between 40-20-24-24 , 40-20-20-20, 60-20-20-24 is a huge difference 
X570 boards, use X - 20 - 20 - 24 
X370/B450 boards use X - 20 - 24 - 24
120Ohm ClkDrvStrengh might be a bit too much impedance for only two dimms 
Between 40-20 and 60-20 should be plenty 
But 60-20 will require higher Vdimm too and again low procODT 

Increasing ClkDrvStrengh helps to lower procODT, but will logically have the opposite effect if you have proc too high
Then if you have high vSOC , a low procODT will cause force shutdowns or instant crashes
While a low vSOC near the 1.05 - 1.075v range, is not fine with >40 procODt
All depends also on the stress of the memory controller, but keep this in mind

Also be sure to consider that VDDG both of them share a voltage and split it by themself up to need
VDDG needs to be as absolute minimum 50mV higher than cLDO_VDDP, the same goes for VSOC (50mV higher than VDDG)
If you put both VDDGs at the same voltage, it will use the highest voltage as offset
If you have a difference between them which is helpful for 4 dimms or low end boards - it will use the average VDDG voltage as scaling baseline (as again they share voltage but they do it in the hidden)

Custom voltages on ryzen 3rd gen , this specific ones are NOT applied if you don't enable UncoreOC mode inside AMD Overclocking
The Cpu by spec follows a fixed offset in the hidden. It does follow the 50mV (well 48mV) offset set by AMD and will overvolt the higher voltage (like vSOC) if the lower line is higher than vSOC

The same goes for cLDO_VDDP, if that is 1v - it will automatically autocorrect VDDG 



hmeh said:


> 1.52v seemed to work, but temps got higher more quickly. It's a bit warm in my
> house (no AC and summer) so I'm hesitant to introduce more heat. Of course,
> Karhu makes quite a bit more heat than my normal day-to-day usage, I believe.
> 
> If I want to lower tRFC after raising VDIMM where do I go next?
> Edit: I ran with tCL 14 (GDM on) and all the other timings the same. I had 1 error after 25 tm5 cycles in test 7, 2:38 minutes into a 2:55 minute run. What could I tweak to get that stable? That seems close. I wouldn't have seen an error w/ only 21 or so cycles. I wonder if that's temperature related, I forgot to check my max temp before rebooting.


Error 7 is a burst test 2mb - pretty much a voltage missmatch/crash , if you didn't use CAD_BUS Timing dividers (you call setup 63-63-63?)
Either +/- 0.01v on VDIMM/VDDR and it will be fixed. Just a tiny too slow (p)recharge issue of tRP. Try -1 step down, else +1 up



hmeh said:


> If this fails is my voltage too high or too low? and specifically the VDDP is the concern? I think my bios lets me set it to anything, what would you expect me to be able to set it to? (edit: as above, I set vddp to auto and mobo goes to 900 and that seems fine)


On everything that has to do with memory, it strongly depends  
It has no fixed patterns, only little hint points
If Y-Cruncher errors, it will say on which test it is. That up to workload will mean something but it still can mean 4 things at least
We can iron down what it really is, but it will be voltage related at this point
It nearly never is cLDO_VDDP related. Y-cruncher crashes mostly are PBO's fault or Loadlines vSOC fault
VDDP issues are fully no boot issues or instant Bluescreens on memory tests. VDDG issues mostly come as audio crackle
Although audio crackle issues also can be related to procODT. After all everything belongs to one package

Prime95 Large FFT crashes, are memory controller crashes. Nearly always appearing as WHEA errors
that is VDDP or VDDG as the issue. As vSOC errors will be easier noticable and mostly be instant reboots or issues with procODT
The cpu can take between 1.05-1.2v VSOC up to running procODT, but it ill always make issues if voltages either don't follow a fixed voltage stepping or it missmatches with procODT


----------



## Veii

2600ryzen said:


> XT cpu's can do 2000mhz+ fclk? How are the X cpu's artificially locked?


XT CPUs can do up to 2100, i've seen 2200 by chinese OCers 
They have a changed memory controller, it's not just your casual 100Mhz bump that's advertised
1usmus did also subtle hint it - but i guess he prepares something or needs long testing, so only his twitter follower know it
Chiphell users and other chinese OCers got it up to 4400/2200 1:1 mode 
The Renoir APUs and the XT series are very similar. The APUs and the X series are not that similar
I am not sure if XT series already function fully with variable vSOC and variable FCLK like Renoir does

But to be honnest, i've seen 3xxx X users have variable vSOC. 
Even when PBO SOC TDC,EDC is still to this date hidden (while it's in the bios since 1004B patch B & 1005)

If it was just a subtle Boost bump, the pricing wouldn't make sense at all.
They where artificially locked since 1003ABBA, well since the start.
We started to have negative SiSandra results by going 1900 1:1 mode instead of staying on 2133 (1066 FCLK).
It was visible on Threadripper and here, also clearly noticable afterwards on SiSandra as delay between the furthest core in one CCX and the furthest core to the other CCD
Also written as U1-U24 latency 

SiSandra Multi-Core efficiency testing has an important meaning, it's not just this virtual score which scales by efficiency by frequency (IPC) and also CCX frequency
The real interesting thing is the latency curve and the latency between cores inside CCX and CCDs
It's a long topic and i've talked abit about it on the X370 Taichi Thread where our 1004B bios was a Pre-Released 1005/1006 Agesa
Exactly at this 1006 (renamed 1005) AGESA we seems like got a PSP firmware update, because Inter-Core latency dropped by 2-3ns and voltage requirement pretty much changed fully

They still are locked near 1900FCLK, although i don't know why 
Some limits got lifted, but this needs more samples and direct research from someone. 
The last tests where around the time where only a handful of boards got AGESA 1005
It's hard to compare before and after changes, when a PSP Firmware update is a one way - way 
Without having data to compare from before, you can't see changes.
And without tracking it on SiSandra exclusively, you won't notice what's going between CCX's 

On a direct question about Renoir's dynamic FCLK and STAMP shifting (like on notebooks)
with very visible PBO TDC, EDC limiting feature in the bios
https://twitter.com/VeiiTM/status/1278258904837902337
i got no answers, and seen no one bothered to investigate
It's there since mid April (i've re-posted the microcode on 11-04) and clearly it's not a Renoir only PBO feature, that far back 
But so far, no one bothered to investigate or saw it i guess  
It's since a long time in the Bios

We'll see, so far i haven't seen all limits being lifted on X series units ~ if they ever will be


----------



## rares495

Veii said:


> XT CPUs can do up to 2100, i've seen 2200 by chinese OCers
> They have a changed memory controller, it's not just your casual 100Mhz bump that's advertised
> 1usmus did also subtle hint it - but i guess he prepares something or needs long testing, so only his twitter follower know it
> Chiphell users and other chinese OCers got it up to 4400/2200 1:1 mode


Is this true for most XT chips or are these just golden samples?


----------



## Veii

rares495 said:


> Is this true for most XT chips or are these just golden samples?


3900X golden samples get up to 1950 so far, but i don't think it's the sample that defines that. 
They are locked since a long time - 2000 should be no issue, as 1900 is hittable on a 2700X from the technical point of view
I don't know much more on this, can't test or confirm for all. Yuri knows more
Only know it needs 1.2vSOC to be maintained and know Renoir is not much different than XT on it's core

So far a 1200AF awaits to be pushed to 3733/3800 when i get a setup together
Later might try to source down a Renoir APU from china, as i wanted to have one as natural upgrade path
Need that 2nd GPU in the system for the future
XT units are a bit too expensive to consider them and X units are just powersaving binns


----------



## mongoled

Well looks like im looking at buying a new CPU, those XTs now look interesting if the 2000 fclk is true



Amazon.de has a price drop for the 3600XT ....

Its looking like either one of two things has deterioted in my setup, its either the motherboard or the CPU.

Going to have to buy a CPU to work out which one it is ....


----------



## Veii

mongoled said:


> Well looks like im looking at buying a new CPU, those XTs now look interesting if the 2000 fclk is true
> 
> Amazon.de has a price drop for the 3600XT ....
> Its looking like either one of two things has deterioted in my setup, its either the motherboard or the CPU.
> Going to have to buy a CPU to work out which one it is ....


Please don't consider it as guaranteed thing. Everyone keeps being silent about variable vSOC+FCLK , XT and Renoir 
Only explore it if you can return the CPU :ninja:


----------



## mongoled

Veii said:


> Please don't consider it as guaranteed thing. Everyone keeps being silent about variable vSOC+FCLK , XT and Renoir
> Only explore it if you can return the CPU :ninja:


I wont be returning,

I need another CPU to work out if my 3600 is the reason for my instabilities ...

3600XT = 215.55
3600X = 178.98
3600 = 154.51

I wont pay the VAT, so its a choice between these 3 CPUs ..


----------



## Veii

mongoled said:


> I wont be returning,
> 
> I need another CPU to work out if my 3600 is the reason for my instabilities ...
> 
> 3600XT = 215.55
> 3600X = 178.98
> 3600 = 154.51
> 
> I wont pay the VAT, so its a choice between these 3 CPUs ..


That's a pretty big price uplift 
the 3600X alone can't sustain the boost target, without manual work
A 3600 can be tuned to sustain 4.3Ghz allcore on TM5 (with PBO boost) on bad samples and likely 4.4 on good samples
If you can't return it, it might be trown away money just to explore it's limits
What i can see across benchers, it does for sure scale higher on CCX clock but no one tried to push FCLK beyond 1900Mhz
People are playing with the 3300X - while the 3600XT is still marketed as MTS-B0 stepping and the Renoir ones as RN-A1

What if the cpu was fine to begin with ?
Can't you return stuff or don't you want to ?


----------



## hmeh

Veii said:


> Auto only since recently is 900mV cLDO_VDDP , there is a CPU VDDP ~ don't confuse them
> Lower VDDP and so also lower procODT decreases the stress on the memory controller
> Which results (like it was usually the case on first two gens) in higher maximum FCLK limit
> 
> Up to AGESA the recommended voltages vary , but take a closer look here
> The bottom part of the post , but maybe the whole response would be helpful to you.


I had no trouble getting to FCLK 1900 (I could never get to FCLK 1933). I
currently have:
cLDO_VDDP 900 
VDDG 1050 
VSOC 1100

Should I align on either 100 or 50 stepping? Or does it matter since this is stable?



Veii said:


> If you keep converting and back converting tRFC virtual number, you will get rounding errors
> It is key to either use MCLK or MT/s as main baseline for accuracy.


So it's okay for tRFCns to have decimals, yes? As long as I don't convert back
and forth when calculating tRFC2/4, yes?



Veii said:


> Between 40-20-24-24 , 40-20-20-20, 60-20-20-24 is a huge difference
> X570 boards, use X - 20 - 20 - 24
> X370/B450 boards use X - 20 - 24 - 24
> 120Ohm ClkDrvStrengh might be a bit too much impedance for only two dimms
> Between 40-20 and 60-20 should be plenty
> But 60-20 will require higher Vdimm too and again low procODT


Okay, will try 60 - 20 - 20 - 24. I had 120 - 20 - 24 - 24

With this, what should my ProcODT target be with 2 16gb dimms?



Veii said:


> Custom voltages on ryzen 3rd gen , this specific ones are NOT applied if you don't enable UncoreOC mode inside AMD Overclocking
> The Cpu by spec follows a fixed offset in the hidden. It does follow the 50mV (well 48mV) offset set by AMD and will overvolt the higher voltage (like vSOC) if the lower line is higher than vSOC
> 
> The same goes for cLDO_VDDP, if that is 1v - it will automatically autocorrect VDDG


I'm seeing HWINFO respecting my voltages I listed above (they report as 1.092,
1.069, 0.924), so do I need UncoreOC mode?



Veii said:


> Error 7 is a burst test 2mb - pretty much a voltage missmatch/crash , if you didn't use CAD_BUS Timing dividers (you call setup 63-63-63?)
> Either +/- 0.01v on VDIMM/VDDR and it will be fixed. Just a tiny too slow (p)recharge issue of tRP. Try -1 step down, else +1 up


Is setup 63-63-63 good/ I did not have it set for this run, just on auto.
tRP -1/+1 or VDDR +/- 0.01v or both?


----------



## Veii

mongoled said:


> Well looks like im looking at buying a new CPU, those XTs now look interesting if the 2000 fclk is true
> 
> Amazon.de has a price drop for the 3600XT ....
> Its looking like either one of two things has deterioted in my setup, its either the motherboard or the CPU.
> Going to have to buy a CPU to work out which one it is ....


https://forums.overclockers.co.uk/posts/33749937 One person, fail at 1900FLCK
https://forums.overclockers.co.uk/posts/33750638 2nd person, fail at 1867 (probably could be knowledge)

I am not sure what to judge out of this
Either A:
One guy was unlucky or both don't understand procODT and vSOC scalling
B:
Both guys are great overclockers, and one chinese sample was golden 
C:
It was a fake all along, although yet no mention about variable vSOC on the new lineup ~ as i've seen it in person doing it's thing when UncoreOC is not enabled

I might redact my comment before, to not trap people into buyers remorse, till i can get to play with a sample myself to see it's limits
Price jump is too high, a 3700X should be equally priced at this point while still expensive
Maybe it even makes more sense to import a Renoir 4600G from Asia (china, taiwan, korea), for you

On the positive side, 
two confirmations that around 1.28v is enough for 4.6Ghz per CCX OC


----------



## 2600ryzen

mongoled said:


> I wont be returning,
> 
> I need another CPU to work out if my 3600 is the reason for my instabilities ...
> 
> 3600XT = 215.55
> 3600X = 178.98
> 3600 = 154.51
> 
> I wont pay the VAT, so its a choice between these 3 CPUs ..



You could get a 3300x, that has the best Zen2 Ram latency for reasons I don't understand. I don't think it's the single ccx because the 3100 has great latency too.


----------



## Veii

hmeh said:


> I had no trouble getting to FCLK 1900 (I could never get to FCLK 1933). I
> currently have:
> cLDO_VDDP 900
> VDDG 1050
> VSOC 1100
> Should I align on either 100 or 50 stepping? Or does it matter since this is stable?


From cLDO_VDDP to VDDG you can pick if single or double stepping, VDDG does split the voltage anyways by itself 
And as you have two of them , you can pretty much use double stepping
By how much, it doesn't matter as long as it's not lower than 50mV. Can be 50, 75, 100, 125
Official by AMD is 50mV 

Lower remains better 



hmeh said:


> So it's okay for tRFCns to have decimals, yes? As long as I don't convert back
> and forth when calculating tRFC2/4, yes?


As long as you use the base in ns, and don't start to divide tRFC by / value - then you are fine
Decimals are between 8-11 digits, many calculators even struggle to display them ~ and boards do also wrongly predict them
Else yes, a whole value tRFCns was before better - but memory scales logarithmic per frequency, soo any kind of fixed ns value is always wrong

Optimally you hit a value less than 1 decimal or even non - but the tRFC calculator works so far well enough on it's current state
It's trustful with it's values
It's not perfect, as i can't predict how boards calculate tSTAG. But it's accurate when tRC is accurate




hmeh said:


> Okay, will try 60 - 20 - 20 - 24. I had 120 - 20 - 24 - 24
> With this, what should my ProcODT target be with 2 16gb dimms?


1900 FCLK ? will have issues beyond 32 procODT unless the memory controller is great
Might work up till 36.9ohm, 40 would be common requirement for Dual Rank B-dies
48 is according to teaching book, 40 will work tho for 3734MT/s 

Best practice remains to stay near 1.075v vSOC and move along 32ohm for DR or 28Ohm for Single Rank
And just help procODT by using high ClkDrvStrengh CAD_BUS values
1.1 vSOC is already too much for anything under 36.9Ohm (borderline), it's alright for 40ohm



hmeh said:


> I'm seeing HWINFO respecting my voltages I listed above (they report as 1.092,
> 1.069, 0.924), so do I need UncoreOC mode?


The issue is, HWInfo does read what you put in the bios, but it isn't the reality 
It can't check the autocorrection, for that you have to install once at least ryzen Master
But keep in mind this will disable CPPC & CPPC preferred cores functionality ~ soo you need to enable that again in AMD CBS (SMU) or AMD OVERCLOCKING XFR Enchancements 



hmeh said:


> Is setup 63-63-63 good/ I did not have it set for this run, just on auto.
> tRP -1/+1 or VDDR +/- 0.01v or both?


CAD_BUS Timings depend on MT/s mainly and VDDR a bit
They are adding latency and cut at a specific time window. Logically this time window is MT/s sensitive and shifts
You have to figure out what your kit likes the most - but if this is the only thing that helps you stabilize it, something else is not correct
It adds a bit of latency, but Finetune that cutting time and move between 50-63 as a value
For now only try VDDR +/- 0.005/0.001 to get that Burst-Test Error 7 away


----------



## KedarWolf

https://www.aliexpress.com/item/328...earchweb0_0,searchweb201602_,searchweb201603_

ALSEYE RAM Cooler PC Fan DDR Memory Cooler with Dual 60mm Fan PWM 1500-4000RPM Cooler for DDR2/3/4

My RAM fan arrived from Aliexpress. PWM as well. An amazing 45 CFM, likely loud though, but I never hear my fans over my headset. 

And I ordered it April 25th, so a few days less than three months to arrive. 

You actually have to put it together but they even include a tiny screwdriver to do so. 

And it comes with a molex power adapter for the PWM if you want to run it that way, but I'm pretty sure it'll max out the RPM if you do do that.


----------



## Veii

2600ryzen said:


> You could get a 3300x, that has the best Zen2 Ram latency for reasons I don't understand. I don't think it's the single ccx because the 3100 has great latency too.


Hmm L3 cache size is lower on both, but it remains faster than a 3800X because it's only one CCX and doesn't have to share anything 




Halfway known information, but a good OCer and well made video 

Going decoupled mode, shouldn't be much of an issue on it as it shouldn't exceed 70ns
(72ns was my personal research where the bottleneck was since Zen) 
~ but people also haven't explored that path. On TR decoupled mode was beneficial beyond 2200MCLK

But i think, you could have more fun with Renoir unless you can return CPUs
Someday this mystery will be solved by someone 
If i had a unit to play with, likely my goal would be keeping beyond 4800 to run and see if & how much is needed to actually make it beneficial going decoupled mode, and if there is another frequency in the middle for good sync


----------



## hmeh

Veii said:


> CAD_BUS Timings depend on MT/s mainly and VDDR a bit
> They are adding latency and cut at a specific time window. Logically this time window is MT/s sensitive and shifts
> You have to figure out what your kit likes the most - but if this is the only thing that helps you stabilize it, something else is not correct
> It adds a bit of latency, but Finetune that cutting time and move between 50-63 as a value
> For now only try VDDR +/- 0.005/0.001 to get that Burst-Test Error 7 away


Okay, so leave the timings on auto. Unfortunately, my gigabyte motherboard only allows 0.01V +/- on VDDR, or am I missing something?


----------



## 2600ryzen

Veii said:


> Hmm L3 cache size is lower on both, but it remains faster than a 3800X because it's only one CCX and doesn't have to share anything
> https://www.youtube.com/watch?v=84OkOLzRPxY
> Halfway known information, but a good OCer and well made video
> 
> Going decoupled mode, shouldn't be much of an issue on it as it shouldn't exceed 70ns
> (72ns was my personal research where the bottleneck was since Zen)
> ~ but people also haven't explored that path. On TR decoupled mode was beneficial beyond 2200MCLK



I didn't know the 3300x was that good. The 4.4ghz 3300x + tuned memory > 3800x with same tuned memory at almost every game. The faster the memory the faster the 3300x becomes relative to the other Zen 2 cpu's.


----------



## mongoled

Veii said:


> https://forums.overclockers.co.uk/posts/33749937 One person, fail at 1900FLCK
> https://forums.overclockers.co.uk/posts/33750638 2nd person, fail at 1867 (probably could be knowledge)
> 
> I am not sure what to judge out of this
> Either A:
> One guy was unlucky or both don't understand procODT and vSOC scalling
> B:
> Both guys are great overclockers, and one chinese sample was golden
> C:
> It was a fake all along, although yet no mention about variable vSOC on the new lineup ~ as i've seen it in person doing it's thing when UncoreOC is not enabled
> 
> I might redact my comment before, to not trap people into buyers remorse, till i can get to play with a sample myself to see it's limits
> Price jump is too high, a 3700X should be equally priced at this point while still expensive
> Maybe it even makes more sense to import a Renoir 4600G from Asia (china, taiwan, korea), for you
> 
> On the positive side,
> two confirmations that around 1.28v is enough for 4.6Ghz per CCX OC


I better do some research then! The way you spoke of 2000mhz fclk it sounded like it was common, good of you to follow it up with some posts from other forums.

Also, I am on x370, so this may also be a limiting factor....

Renoir 4600G looks like an interesting proposition, but looks like it will be difficult to get hold of one, also would need to see some benchmarks to see how the latency is with those CPUs as being a monolithic die we should expect great improvement ?



Veii said:


> That's a pretty big price uplift
> the 3600X alone can't sustain the boost target, without manual work
> A 3600 can be tuned to sustain 4.3Ghz allcore on TM5 (with PBO boost) on bad samples and likely 4.4 on good samples
> If you can't return it, it might be trown away money just to explore it's limits
> What i can see across benchers, it does for sure scale higher on CCX clock but no one tried to push FCLK beyond 1900Mhz
> People are playing with the 3300X - while the 3600XT is still marketed as MTS-B0 stepping and the Renoir ones as RN-A1
> 
> What if the cpu was fine to begin with ?
> Can't you return stuff or don't you want to ?


Which cpu are you refering to "was fine to begin with?", my current 3600 or the one I decide to get ?

Im not really into acting that way, now if I have purchased something and I know that it is not performing as it should than yes I will return it, but not if it is performing to specification.

A bad overclocker is not a reason to return a CPU, I would either suck it up or sell it on at a loss ...

Thts not saying that I did the more honerable thing when i was younger



If I can find info that there is more than 50% chance that an XT will do 2000mhz fabric than i would go for it, otherwise I would prefer to tune a 3600, hopefully if I go down that route I can finaly get a beastly overclockers, its been years for me to get lucky .....



2600ryzen said:


> You could get a 3300x, that has the best Zen2 Ram latency for reasons I don't understand. I don't think it's the single ccx because the 3100 has great latency too.


Im not going to drop to a quad core


----------



## hmeh

@Veii okay, I've got the below stable it seems, at least via TM5 25 cycles and y-cruncher 4 full iterations. 

I'm still not clear on the VSOC/VDDG/cLDO VDDP and what I should do. You can see what RM is reporting below. What should I try instead?

*Edit: tRCDRD 14 is stable too w/ same settings*

Any suggested tweaks on the timings? Not sure how tCL 14 changes the calculations of the other timings.

Have you ever seen TM5 hang? Sometimes it'll stop after test 15 and never move on to the next cycle. I've seen that happen twice. It keeps counting the timer, but it frees all the memory and just doesn't do anything.

Thanks again for all your help.


----------



## Veii

hmeh said:


> Okay, so leave the timings on auto. Unfortunately, my gigabyte motherboard only allows 0.01V +/- on VDDR, or am I missing something?


I've seen gigabyte boards often add delay to them out of nowhere. Auto should default to 0. You can see if 1-1-1 would make any difference and it would be a subtle bit slower.
1-1-1 shouldn't do anything positive, it only might make a difference, if boards defaulted to something by their own


2600ryzen said:


> I didn't know the 3300x was that good. The 4.4ghz 3300x + tuned memory > 3800x with same tuned memory at almost every game. The faster the memory the faster the 3300x becomes relative to the other Zen 2 cpu's.


It's really a good CPU, i miss a bit decoupled testing on that unit. People usually don't go beyond 4400MT/s. 
Needs testing above >4800, as the best sync was around 1200-1200-1200 1:1:1 default mode on Threadripper.


mongoled said:


> I better do some research then! The way you spoke of 2000mhz fclk it sounded like it was common, good of you to follow it up with some posts from other forums.


It should be possible, and i've seen it possible. But like you mentioned it could've been a golden unit, or afterwards restricted as that sample was an Engineering Unit and it's been some time since then. 1950 at least could be expected on a better sllicon even when they opted not to replace the IMC on that sample (which i doubt)
The issue is, unclearness ~ no one talks about this. Variable vSOC would allow higher vSOC as 2000FCLK required 1.2 vSOC
And the XT units could do that (same as with the new microcode old X units under pre 1005 AGESA bios)
, soo either the IMC got replaced, or the FW of it is different/got patched away again on the XT units
Overall one of the 3 options can be true as far of this date
1.) Both OCers didn't play enough with vSOC beyond 1.1
2.) Chinese OCer and leaker had either a golden Unit 
3.) ^ but the ES sample got last minute changed, maybe it affected PCIe 4.0 link quality
~ i could expect from AMD at least on their 100$ premium bin to lift some limits - even more when they sell it as a "new lineup" 
but hey, maybe it really caused some issues with Signal Quality to be disabled again. Variable vSOC and technically variable FCLK where possible already on X units, even tho it was only with some modding. 
I've seen 2000 on XT units possible, unsure why both OCUK guys couldn't get beyond 1900 stable. At least 1950/1967 could be expected 



mongoled said:


> Also, I am on x370, so this may also be a limiting factor....
> 
> Renoir 4600G looks like an interesting proposition, but looks like it will be difficult to get hold of one, also would need to see some benchmarks to see how the latency is with those CPUs as being a monolithic die we should expect great improvement ?


Hmm does this help
https://twitter.com/1usmus/status/1276440775518310400 
Also includes a reference to XT units
... wow, Robert Hallocks account https://twitter.com/Thracks / https://twitter.com/aschilling/status/1277997703289614342 is gone  
The last thing he "leaked/mentioned" was Renoir's dynamic FCLK and VSOC adjusting and boosting up to situation higher
something is indeed odd ~ usually he doesn't ignore direct questions about the platform, but again everyone keeps being silent about variable VSOC :wubsmiley



mongoled said:


> Which cpu are you refering to "was fine to begin with?", my current 3600 or the one I decide to get ?
> 
> Im not really into acting that way, now if I have purchased something and I know that it is not performing as it should than yes I will return it, but not if it is performing to specification.
> 
> A bad overclocker is not a reason to return a CPU, I would either suck it up or sell it on at a loss ...
> Thts not saying that I did the more honerable thing when i was younger


Yes absolutely !
It's a thing of Moral, i fully understand you ~ but this was absolutely not my intention 

I guess it's different as per country.
Returning an abused CPU (be it after XOC or high VCore with guaranteed degradation) is NOT oke
People do this up till 2 years of their warranty and some abuse the later system *

* Up to country, you usually have a no questions asked replace policy on everything that's not a medical unit.
With other words any kind of electronic, to prevent buyers remorse. 
You have to return it in mint condition, while a bit of dust is acceptable.
Up to shop in my location it's between 14-30 days, 14 being mostly online delivery and Amazon **
** although people do abuse amazon's swap policy after 1+ year of usage, where the consumer doesn't like the CPU

I believe you, it's a very thin line and has to do with moral
At least in Europe it is common practice to return electronics you don't like, before keeping them for the expected 3-5years timeframe
My question about the return for you was focused on your potential issue you try to figure out
If it's the CPU that made issues or the Board.

I've seen OCers just do 10min binning on a batch of 10 CPUs without using dangerous voltages 
- just to test which has a good memory controller or good cores booting the set under low voltage
Yes a purely thing of moral and viewpoint.  
Testing if the CPU actually has a swapped IMC be it alone to only run it through readout software like Aida64 and HWInfo - i wouldn't personally consider as "abusive return with the happiness swap policy" we commonly have on this continuent
Although, even warranty here is extended by at least +1 to +5 years, up to goods you buy ~ purely as a happy consumer has no reason to return their purchase.

Else, i do fully agree with you - never return an abused CPU ! 
You only cause trouble for a potential new buyer.
AMD or the retailer couldn't care less about it when the product is intact 


mongoled said:


> If I can find info that there is more than 50% chance that an XT will do 2000mhz fabric than i would go for it, otherwise I would prefer to tune a 3600, hopefully if I go down that route I can finaly get a beastly overclockers, its been years for me to get lucky .....


Yes, on this high price difference, i might test it to finally clear up this question but not keep it. 
100 bucks above for the identical architecture is not fine. When you pay 100+ for binning, there are other places to do so 

Sadly at this point i can't anymore
Seems like stuff changed, when you read the posts and twitter links above
Likely it could be possible if variable vSOC & MCLK is still able to be turned on.
But on no IMC swap, i can only expect 1967 as absolute max and it has to use variable vSOC
~ else 1. you degrade the unit & 2. signal integrity would suffer making higher than ~1930FCLK without this anyways not possible


hmeh said:


> @Veii okay, I've got the below stable it seems, at least via TM5 25 cycles and y-cruncher 4 full iterations.
> 
> I'm still not clear on the VSOC/VDDG/cLDO VDDP and what I should do. You can see what RM is reporting below. What should I try instead?
> *Edit: tRCDRD 14 is stable too w/ same settings*
> 
> Any suggested tweaks on the timings? Not sure how tCL 14 changes the calculations of the other timings.
> 
> Have you ever seen TM5 hang? Sometimes it'll stop after test 15 and never move on to the next cycle. I've seen that happen twice. It keeps counting the timer, but it frees all the memory and just doesn't do anything.
> 
> Thanks again for all your help.


tCL 14 is helpful on tRAS calculation 
(tCL+tRCD or tCL+tWR+tBL)

Your set only remains stable as it will be waiten for tRP to pass and recharge the cells.
with 14-11-14, avg tRCD is 12.5 - where on this high voltage tRP 12 would be better than 13
If you fall beyond avg tRCD 12, you will have issues with tWRRD - as 4 * 3 tWRRD = 12 
Ruleset says, tWRRD should be less or equal to tRCD (WR), but not bigger 

Did you by purpose put tRRD_L to 4 instead of 5 ?
I don't think i made the mistake and forgot to add it ^^








Likely the set only is stable because of auto-correction

Try to go now for 
tRCD WR 10
tRP 12
tRC 44
tRRD_L 5 (what you forgot to add)
tRTP 7
tRFC 308-229-141 
Good Luck :specool:


----------



## Veii

Veii said:


> Overall one of the 3 options can be true as far of this date
> 1.) Both OCers didn't play enough with vSOC beyond 1.1
> 2.) Chinese OCer and leaker had either a golden Unit
> 3.) ^ but the ES sample got last minute changed, maybe it affected PCIe 4.0 link quality


 @mongoled Suspicion on 3.) increases even more








It's not far of reality, that high Fabric Clock will make issues with PCIe :thinking:
There should be no reason to artificially lock 3xxx CPUs 
unless you want to keep up the "aging like wine" meme and want to have a hidden Ace in your sleeves ~ if the competition returns


----------



## mongoled

Im tired, real tired ...

I enjoy our hobby, I really do, just it can become so draining when the "basic rules" that we have come to accept take on a new dimension and than we need to find "new rules".

The main things I would like to discuss is the acceptance that vDDG and vDDP must follow the basic rule of being less than vSOC as these are derived from vSOC so in theory they cannot be a higher than vSOC.

So....... I have two MSI motherboards in front of me and X370 and an X570.

On both motherboards i set vSOC to "Offset mode --> - (minus) --> 0.0500", CPUNB LCC to 1 (highest) this gives me on both motherboards a vSOC voltage of around 1.050v according to HWINFO.

Now, I leave VDDP and VDDG on auto in both motherboard BIOS and boot to Windows on each system and open Ryzen Master.

On both systems Ryzen Master is showing [email protected] and [email protected] while vSOC (VDDCR) is showing a 1.1v

OK...... so Ryzen Master must be interpreting the voltages incorrectly.

So on the X370 motherboard i go into the BIOS and manually type put VDDP to 1.1v and VDDG to 1.15v, press F10..... system boot normally.....open Ryzen Master and VDDP/VDDG are showing the same values as when they are left on AUTO, i.e. 1.1481v/1.0979v

According to the "rule" that VDDG/VDDP are derived from vSOC and vSOC is @ 1.050v which is less than VDDG/VDDP

Huh ....?#@??!?!?

Now I am going to stop using "Offset" method and put manual value and see if this situation continues.

Why am I doing this, because I cannot get to the bottom of why the "rules" are not consistent. I have other stories to tell about the 3600 now paired with the X570 and the 3600X paired with the X370.

tired, so tired .....


----------



## hmeh

Veii said:


> I've seen gigabyte boards often add delay to them out of nowhere. Auto should default to 0. You can see if 1-1-1 would make any difference and it would be a subtle bit slower.
> 1-1-1 shouldn't do anything positive, it only might make a difference, if boards defaulted to something by their own


Would I see this as latency in AIDA64?




Veii said:


> tCL 14 is helpful on tRAS calculation
> (tCL+tRCD or tCL+tWR+tBL)


What is tBL? Does this mean I might be able to try tRAS 28?



Veii said:


> Did you by purpose put tRRD_L to 4 instead of 5 ?


Oops 




Veii said:


> Likely the set only is stable because of auto-correction
> 
> Try to go now for
> tRCD WR 10
> tRP 12
> tRC 44
> tRRD_L 5 (what you forgot to add)
> tRTP 7
> tRFC 308-229-141


This is very unstable now, 35+ errors in first cycle alone, 2, 4, 5, 6, 10, 12.

tRTP 7 doesn't work, it shows tRTP 8 regardless.

What should I try? Would I be able to get stable at 14-14-14-14-28? I don't know how the other timings play into that. My set up doesn't need to be perfect, just stable and good.

Last night I tried the same timings I showed with much lower tRFC (270 - 201 - 123) and it had 1 error on 11

Also, tRRDL correction with previously stable timings gave me error on 6 in first cycle. (though after reverting to tRCDRD 15, so far so good)


----------



## Veii

@mongoled , i understand 
What you set will be ignored if the lower end of the chain is a mess
And even when you set all 3, you still can have the CPU ignore this too low changes - unless you enable UncoreOC mode

If you set VDDG only but it somewhy for a magical bad bios design reason, thinks cLDO_VDDP needs to be higher 
Your VDDG will be ignored 
if you set VSOC lower than VDDG, your vSOC will be ignored and autocorrected

Ryzen master so far does report the truth, HWInfo doesn't get autocorrection figured out  
That's why we enforce UncoreOC mode - soo "custom voltages" actually are set, neverless if the CPU thinks they are stable or not
AMD's ruleset is a 50mV offset, but 1004 and up has funny bugs. It's a bugfest all along tbh 

@hmeh , hmm soo tRTP is autocorrected with GDM enabled ? interesting :thinking:
That would mean that tRFC could be autocorrected too, i wonder. Well maybe it isn't when you set tRFC 2 and 4 else it would show funny errors and break the set

Soo on your old set you got tRRD_L 5 error 6 fixed ?
Or did you adapt the new set just with tRCD RD 15
New set has lower tRP as i put avg tRCD delay lower, by using tRCD WR 10 instead 11, soo tRP ended up to 12 instead of like 12.5 or 13 
tRP is row (p)recharge - it has to match tRCD else the cells can't be recharged in time and will fail
tRP is strongly dependent on VDIMM, but you aready use a lot - let's see maybe we can get the bottom set somehow to work

14-14-14-28 
You have to run tRC 42 to be perfect as tCL 14
tRCD RD depends on IC binning and a very subtle bit on voltage, but it's mostly IC binning.
Barely anyone gets 14-14-14 on 3800 easy to run. It will need over 1.5v and then also luck that not only the PCB is A1 or A2 but also that the ICs don't have negative scaling over 1.48v and also are a high binning
tRCD RD is pretty much fixed and predefined, it does increase +1 around the same time when tCL does - soo about each +4 jumps on MT/s frequency, or around 200MT/s 
GDM will round stuff up, soo often disabling it and just running 2T with tighter timings leads to better results than GDM as 1.5T with only even values

in order for 14-xx-xx-28/30-42 to work, you need tWR of 10 or 12. or a double for DR = 20/24 
Then a tRFC which divides wonderfully by 6, by 8, 10 or by 24
using whole value tRFC like 280 or 240 allows tWR 10 to work well, that combined with either tRTP 6 or 8
tWR doesn't have to be tRTP *2 , but it's recommended - and it can't be an odd value either neverless of GDM state
It can be tRRD_S + tWTR_S , but we are bios limited by 10 as lowest tWR 

tBL is bank group amount, it depends on the dimm size
2 is for 8gb dimms
EDIT:
Memory latency you see in Aida64, but Inter-Core latency and especially the latency curve- you have to use SiSoftware Sandra - Multi-Core Efficiency Test (detailed mode)
when you compare timings efficiency and "sync" of them
Aida64 won't show autocorrection issues, a latency curve will show it
DRAM Calculator does have a latency curve feature, but it can need a bit of a redesign when you compare two memory benchmarks


----------



## mongoled

Veii said:


> It should be possible, and i've seen it possible. But like you mentioned it could've been a golden unit, or afterwards restricted as that sample was an Engineering Unit and it's been some time since then. 1950 at least could be expected on a better sllicon even when they opted not to replace the IMC on that sample (which i doubt)
> The issue is, unclearness ~ no one talks about this. Variable vSOC would allow higher vSOC as 2000FCLK required 1.2 vSOC
> And the XT units could do that (same as with the new microcode old X units under pre 1005 AGESA bios)
> , soo either the IMC got replaced, or the FW of it is different/got patched away again on the XT units
> Overall one of the 3 options can be true as far of this date
> 1.) Both OCers didn't play enough with vSOC beyond 1.1
> 2.) Chinese OCer and leaker had either a golden Unit
> 3.) ^ but the ES sample got last minute changed, maybe it affected PCIe 4.0 link quality
> ~ i could expect from AMD at least on their 100$ premium bin to lift some limits - even more when they sell it as a "new lineup"
> but hey, maybe it really caused some issues with Signal Quality to be disabled again. Variable vSOC and technically variable FCLK where possible already on X units, even tho it was only with some modding.
> I've seen 2000 on XT units possible, unsure why both OCUK guys couldn't get beyond 1900 stable. At least 1950/1967 could be expected


Well I searched for results for XT infinity fabric overclocks and there is very little information out there.

When you speak of variable vSOC, can you please be clear to what you are asserting ?

Two different SOC voltages, for example vSOC FCLK and vSOC UCLK ??

So regards 1, 2 & 3 we will have to wait for more samples to get into the right hands.....



Veii said:


> Hmm does this help
> https://twitter.com/1usmus/status/1276440775518310400
> Also includes a reference to XT units
> ... wow, Robert Hallocks account https://twitter.com/Thracks / https://twitter.com/aschilling/status/1277997703289614342 is gone
> The last thing he "leaked/mentioned" was Renoir's dynamic FCLK and VSOC adjusting and boosting up to situation higher
> something is indeed odd ~ usually he doesn't ignore direct questions about the platform, but again everyone keeps being silent about variable VSOC :wubsmiley


Thanks for the links, though we are relient on information that has been passed down from other sources, which means we would have to trust those sources to trust the validity of the information .... 

Well I dont think those OcUK guys are hardcore overclocker





Veii said:


> Yes absolutely !
> It's a thing of Moral, i fully understand you ~ but this was absolutely not my intention
> 
> I guess it's different as per country.
> Returning an abused CPU (be it after XOC or high VCore with guaranteed degradation) is NOT oke
> People do this up till 2 years of their warranty and some abuse the later system *
> 
> * Up to country, you usually have a no questions asked replace policy on everything that's not a medical unit.
> With other words any kind of electronic, to prevent buyers remorse.
> You have to return it in mint condition, while a bit of dust is acceptable.
> Up to shop in my location it's between 14-30 days, 14 being mostly online delivery and Amazon **
> ** although people do abuse amazon's swap policy after 1+ year of usage, where the consumer doesn't like the CPU
> 
> I believe you, it's a very thin line and has to do with moral
> At least in Europe it is common practice to return electronics you don't like, before keeping them for the expected 3-5years timeframe
> My question about the return for you was focused on your potential issue you try to figure out
> If it's the CPU that made issues or the Board.
> 
> I've seen OCers just do 10min binning on a batch of 10 CPUs without using dangerous voltages
> - just to test which has a good memory controller or good cores booting the set under low voltage
> Yes a purely thing of moral and viewpoint.
> Testing if the CPU actually has a swapped IMC be it alone to only run it through readout software like Aida64 and HWInfo - i wouldn't personally consider as "abusive return with the happiness swap policy" we commonly have on this continuent
> Although, even warranty here is extended by at least +1 to +5 years, up to goods you buy ~ purely as a happy consumer has no reason to return their purchase.
> 
> Else, i do fully agree with you - never return an abused CPU !
> You only cause trouble for a potential new buyer.
> AMD or the retailer couldn't care less about it when the product is intact


Irrespective of different country laws, I dont agree with buying batches of same hardwares, testing them however safetly this maybe, than returning them. For me this is an abuse of the replacement policy and it does not matter what i feel about this, there is an additional expense to someone somewhere for these actions which we all end up paying somewhere along the line.

If you want to test 10 CPUs, than you should be in a position to sell those you do not want and take the hit, not pass the hit to everyone else....

Of course these are moral issues and it is easy to bend this line when we are looking at our own pockets.



Veii said:


> Yes, on this high price difference, i might test it to finally clear up this question but not keep it.
> 100 bucks above for the identical architecture is not fine. When you pay 100+ for binning, there are other places to do so
> 
> Sadly at this point i can't anymore
> Seems like stuff changed, when you read the posts and twitter links above
> Likely it could be possible if variable vSOC & MCLK is still able to be turned on.
> But on no IMC swap, i can only expect 1967 as absolute max and it has to use variable vSOC
> ~ else 1. you degrade the unit & 2. signal integrity would suffer making higher than ~1930FCLK without this anyways not possible


Well as I mentioned in a previous post I have a system to build for a customer, an x570 motherboard with a 3600X, the 3600X is a very new batch 2023.

I have put my 3600 into the X570 and it has no problems running 3800/1900!

I have put the 3600X into my X370 and when i tried to run 3800/1900 it started to act like my 3600!

So i was running out of things to try and I decided to switch the dimms and now the 3600X as acting like I expect it to act.

Tomorrow I will put my 3600 back into the X370 and than test the 3600X in the X570.

I cannot understand why this would happen, it could just be a chance occurance and the 3600 will start acting funny in the X370 motherboard, wont say anymore until i test some more tomorrow.....



Veii said:


> @mongoled Suspicion on 3.) increases even more
> 
> 
> 
> 
> 
> 
> 
> 
> It's not far of reality, that high Fabric Clock will make issues with PCIe :thinking:
> There should be no reason to artificially lock 3xxx CPUs
> unless you want to keep up the "aging like wine" meme and want to have a hidden Ace in your sleeves ~ if the competition returns


Well we have to wait and see, hopefully my CPU is OK and I wont be the guinee pig


----------



## hmeh

Veii said:


> @hmeh , hmm soo tRTP is autocorrected with GDM enabled ? interesting :thinking:


Seems so, yes.



Veii said:


> Soo on your old set you got tRRD_L 5 error 6 fixed ?
> Or did you adapt the new set just with tRCD RD 15


The attached set with tRCD RD 15 is stable, no error 6.
It also looks like the tRCD RD 14 set attached is stable too, I'm sure some timings are wrong, I don't understand all of the calculations yet. Any tweaks or different directions/improvements would be appreciated. *Edit: ALMOST stable, Error in Test 1 on the 24th cycle, doh*



Veii said:


> New set has lower tRP as i put avg tRCD delay lower, by using tRCD WR 10 instead 11, soo tRP ended up to 12 instead of like 12.5 or 13
> tRP is row (p)recharge - it has to match tRCD else the cells can't be recharged in time and will fail
> tRP is strongly dependent on VDIMM, but you aready use a lot - let's see maybe we can get the bottom set somehow to work


What do you mean by bottom set? The tRP 12 one or the tRP 13 I already had?



Veii said:


> 14-14-14-28
> You have to run tRC 42 to be perfect as tCL 14
> tRCD RD depends on IC binning and a very subtle bit on voltage, but it's mostly IC binning.
> Barely anyone gets 14-14-14 on 3800 easy to run. It will need over 1.5v and then also luck that not only the PCB is A1 or A2 but also that the ICs don't have negative scaling over 1.48v and also are a high binning
> tRCD RD is pretty much fixed and predefined, it does increase +1 around the same time when tCL does - soo about each +4 jumps on MT/s frequency, or around 200MT/s


Got it. Yeah, not sure I want to go above 1.52v. tRCD RD 14 worked (on one
pass, then after tRRD_L 5 was set, I got error 11 once), but it seems
I had my tRP wrong so that doesn't really matter. Is tRCD RD 14/WR 12 better than
tRCD RD 15/WR 11 for any reason?



Veii said:


> GDM will round stuff up, soo often disabling it and just running 2T with tighter timings leads to better results than GDM as 1.5T with only even values


Is SiSoft the best way to see the difference between GDM and 2T? 

Which things
round up? tCL, tRTP (apparently), anything else?



Veii said:


> in order for 14-xx-xx-28/30-42 to work, you need tWR of 10 or 12. or a double for DR = 20/24
> Then a tRFC which divides wonderfully by 6, by 8, 10 or by 24
> using whole value tRFC like 280 or 240 allows tWR 10 to work well, that combined with either tRTP 6 or 8
> tWR doesn't have to be tRTP *2 , but it's recommended - and it can't be an odd value either neverless of GDM state
> It can be tRRD_S + tWTR_S , but we are bios limited by 10 as lowest tWR


Do you have a suggested set to try?



Veii said:


> tBL is bank group amount, it depends on the dimm size
> 2 is for 8gb dimms


Okay, so mine would be 4 since I have 2x16gb, yes?



By the way, I tried hard to get VSOC down below 1.1v and failed. VDDG 1.05 and
VSOC 1.1 seem and ProcODT 43.6 seem to be my minimum or things fail to post/bluescreen/etc.

I attached a Sisoft sandra result, but I don't know how to interpret it and it doesn't seem to make a lot of difference between my CL16 set and my CL14 set.


----------



## Veii

mongoled said:


> Well I searched for results for XT infinity fabric overclocks and there is very little information out there.
> 
> When you speak of variable vSOC, can you please be clear to what you are asserting ?
> Two different SOC voltages, for example vSOC FCLK and vSOC UCLK ??
> So regards 1, 2 & 3 we will have to wait for more samples to get into the right hands.....
> 
> Thanks for the links, though we are relient on information that has been passed down from other sources, which means we would have to trust those sources to trust the validity of the information ....


SOC as one and only voltage, the other one would be a VID SOC which belongs to APUs, and scales up from SOC (+100mV) while is different than the main SOC line
Renoir has variable Fabric Clock, variable Mem clock & a variable SOC voltage up to load, thermals and the remain rest
(STAMP algorithm taken from mobile)

I have seen and had issues with variable SOC, where SOC is predefined on Matisse in 3 powerstates
P0 = Flat, P1 and P2 = low idle
There is no P3 sleep, normally as its the main voltage line to the CPU aside from VCORE
I've seen it dropping down to 400mhz, while we should know by now that the Fabric is one of the hottest and most powerhungry parts of the Zen architecture

SOC has to switch to P2 state when the cpu switches to idle
When SOC goes down, so should also go VDDG ~ which literally means, Fabric clock does go down with it but not MCLK
But this ends up a bit contradicting, as cLDO_VDDP can not be under 700mV and doesn't move a bit
Unsure how that voltage to the memory controller keeps getting supplied, when the main SOC line is lower 

The issue atm are two,
The leakers and the information from the corresponding persons such as Tracks (AMD) and 1usmus are accurate
Many more know about this, but not everything is allowed to be told.
1usmus mentioned according to the link i send you that XT units where able to hit more than 1900FCLK - by the research on his own
The information from me on XT is halfway by the footage i got to see and the other half decided by logic of what i've seen 

SOC TDC, SOC EDC exists since far beyond Renoir launch and before any leak of APUs
PPT, TDC, EDC are key values which control the throttling of anything that has to do with voltage management and variable clock
This goes on since gen 2, while gen 2 lacked access to VDDG voltage, making cLDO_VDDP key in preventing what was known as memory hole
A frequency which has to match it's VDDP signals to the specific MCLK frequency, in order to prevent boot and alignment issues 
Discussed and researched here

Knowing out of personal research that in order to push FCLK, good signal integrity is key
Where low procODT and low or variable voltages are very important
Seeing variable VSOC and fabric clock on Matisse X units far before anything Renoir was mentioned
The logic ends up pretty clear that in order to met the boosting targets, and now looking at the key feature-set of Renoir
Variable frequency and variable voltage up to load is key in meeting higher fabric clocks

Looking a bit on Threadripper and the current EPYC lineup - the fabric on it's own didn't change much
It still suffers from the same thermal and signal integrity issues since 1st gen
Issues by design, but preventable

Usually i get some specific answers fast, or if not several leakers would've figured this out already
But it remains a big silence when it comes to variable SOC and variable FCLK together
Indication for it's existence while disabled? remains not only with UncoreOC mode, but also APBDIS inside AMD CBS 
APBDIS put to 1 allows for an enforced SOC powerstate which is held - neverless of the LLC state or what SMU requests

What remains suspicious is not only the silence around that topic, or the hidden bios features since a long time
But that it doesn't behave that way anymore after the latest PSP Firmware patch on AGESA 1006 (renamed 1005)
While it did work by using 1005/1006 Renoir microcode inside pre 1006 bios (modified 1004BB)

About the Robert Hallock topic,
He decided to suspend his social media accounts and got a higher work position by AMD (promotion)
They funnily add up, but he mentioned it has nothing to do with the Renoir whitepaper and the suspension was by his own decision 
That topic is on hold so far 
But the PCIe link issues fit wonderfully with higher FCLK and variable voltages 
~ will let you know once that mystery clears up 

Neverless of that topic, 
SiSoftware Sandra shows scaling and pretty much also shows the Artifical limitation of Matisse units
Some limits got lifted when it comes to inter-core latency (some call it improvements, although nothing changed) but the Fabric Clock remains locked at 1900-1930ish Mhz and going decoupled mode doesn't scale positive like it does on Threadripper
A big and mysterious topic, why they are locked down and since quite some time. Also why XT units aren't at least unlocked anymore when the MemController seems like isn't replaced on the retail units. 
1950FCLK and 220+ GB/s Inter-Core Bandwidth ~ would be a very welcoming boost
https://ranker.sisoftware.co.uk/sho...a994a583ebd6e3c5bd80b197f297aa9abccff2c2&l=en
The highest and best result remains 210GB/s with 53ns inter-core latency, no one even slightly peaking beyond 1900FCLK 
People get nearly identical results between 1.6Ghz IMC (193-200GB/s) and 1.9GHz IMC (192-210GB/s) 
30-40GB/s as bump for example you by going 50Mhz higher, on an 8 core
Here we have 300Mhz difference on a 16 core for just 10ish GB/s more, likely just a constant OC stability difference between the testers
it doesn't scale, but SiSandra is not to blame

In the older days, i remember that we can boot beyond memory controllers limits +200/+300 above it, just it would crash on any kind of memory controller load
Today we can't even post beyond 1900FCLK, where it is more of a lockdown than a "just not possible" issue
Tho i'm drifting away 
What i want to say is, these people who share the data are trustful, just that data sadly doesn't seem to match up retail units at the current moment
Maybe AMD could lift that limit, soo they can actually sell these overpriced XT units finally ^^''
~ or maybe not, as PCIe 4.0 seems to die out 


mongoled said:


> Well as I mentioned in a previous post I have a system to build for a customer, an x570 motherboard with a 3600X, the 3600X is a very new batch 2023.
> 
> I have put my 3600 into the X570 and it has no problems running 3800/1900!
> I have put the 3600X into my X370 and when i tried to run 3800/1900 it started to act like my 3600!
> So i was running out of things to try and I decided to switch the dimms and now the 3600X as acting like I expect it to act.
> 
> Tomorrow I will put my 3600 back into the X370 and than test the 3600X in the X570.
> 
> I cannot understand why this would happen, it could just be a chance occurance and the 3600 will start acting funny in the X370 motherboard, wont say anymore until i test some more tomorrow.....
> 
> Well we have to wait and see, hopefully my CPU is OK and I wont be the guinee pig


If we speak about the voltage anomaly it likely is fine.
I think, i've misinterpreted your issue at the start in why you'd want to inspect the boards behavior 

Can you try to fix on both X370 & X570 ~ PPT TDC EDC to 90-46-50 with PBO enabled X1 scalar
This should result in cosy voltage behavior under allcore loads while nearly be identical to the 3600X specs 
It can be that X370 has lower "AMD Recommended" limits than X570 does, or doesn't change them up to CPU model
cLDO_VDDP , VDDG, VSOC voltage issues just remain bios bugs (AGESA bugs) with messy predictions


----------



## hmeh

Morning, @Veii 

In addition to my post above, the following set tested stable last night. Could you point out what can be improved and/or steer me in the right direction please? Thanks!


----------



## Streetdragon

tfaw 12
trfc 152
both scl to 2
tcwl 12
trtp 4
trdwr 6


----------



## rares495

Streetdragon said:


> tfaw 12
> trfc 152
> both scl to 2
> tcwl 12
> trtp 4
> trdwr 6


tFAW under 16 is pointless.

tRFC I assume you meant 252 but he should use tRFC 2/4 as well: 252-187-115

tCWL 12 is useless and can mess with other timings

tRTP 4 won't work

tRDWR 6 is a wet dream but with tRCDRD 14 he could maybe try 7, though it will most likely not work


----------



## KrampusKlaus

Hey guys, building an R5 3600 system for a friend. Going to be OCing some Crucial Ballistix 3200 CL16 to 3800 if I can get the FCLK to 1900, and tightening the timings as best as Rev-E will go.

Do y’all have a recommendation for a good budget B550 mobo for memory overclocking? Between ASUS, MSI, ASRock, and Gigabyte, which have the best bios features?


----------



## heptilion

Veii said:


> GDM will round stuff up, soo often disabling it and just running 2T with tighter timings leads to better results than GDM as 1.5T with only even values


Ive been getting 46ns in sandra with these settings with GDM enabled and tcrdrd 16 @1T. When disable GDM, tcrdrd 15 @ 2T im getting 46.4ns. what timings can i tighten to improve here. but my aida latency remains at 64.5ns. what timings should i try with 2T to improve latency or should go back to settings with gdm enabled and 1T.

I tried the settings you suggested but it was giving me instant errors in TM5. increasing dram voltage didnt help.


----------



## Veii

hmeh said:


> Morning, @Veii
> 
> In addition to my post above, the following set tested stable last night. Could you point out what can be improved and/or steer me in the right direction please? Thanks!


tRAS 28
tRC 42
tWR 10
tRTP 8 
tRFC 250-186-114

Please try if this would perform better, compare both with SiSandra, 
You only should select your benchmarked result - which you get by pressing the refresh button at the bottom
I'm not fully sure if tRFC would be fine, it's "in sync" with tWR and should be fine with tRTP 8, 6 wouldn't work 

Be sure to benchmark the above set you currently are running 1-2 times 
Also ty, seems like we need to increase TM5 config to 25 cycles zZZ 
I hope it was just heat, or your PSU but 25 cycles for 32gb should've been around 3:10h ?
1h is enough to hit thermal equilibrium :thinking:

Yes, from now on you have to work SiSandra to see on the latency curve subtle differences and at best export the bottom textlog of it either in a google docs to compare the values (U1-U31, U7-U20 and so on) 
Or upload it as TXT/PDF here 
SuperPi 1.5 32mil digits, might also be fine to tell the subtle differences, but that is then cpu heat dependent 


Streetdragon said:


> tfaw 12
> trfc 252
> both scl to 2
> tcwl 12
> trtp 4
> trdwr 6
> 
> 
> 
> rares495 said:
> 
> 
> 
> tFAW under 16 is pointless.
> tRFC I assume you meant 252 but he should use tRFC 2/4 as well: 252-187-115
> tCWL 12 is useless and can mess with other timings
> tRTP 4 won't work
> tRDWR 6 is a wet dream but with tRCDRD 14 he could maybe try 7, though it will most likely not work
Click to expand...

hmeh has Dual Rank dimms - some quite well binned ones considering tRCD RD 14 runs well
Usually his tRDWR is tRCD RD /2 +2 
He/She already uses a trick to get it lower by adding tWRRD delay - there is no chance to go lower  

tFAW might be oke at 10 if tRRD_S 5 is used, but i am pretty sure, boards are locked and *3 tFAW is strange 
4* tFAW always runs 
tWR he/she should be at 20 usually not 12 or even now down to 10 ~ for dual rank 

Only playground do give the top 5 primaries and maaybe tRFC
Although also that one shouldn't be possible beyond 120ns
Playing with:
tRP, 
tRAS, 
tRCD WR
SCL 
would be the only thing left, or trying to get GDM off 2T ~ with CL13-7-14-11-27-38, to run 


heptilion said:


> Ive been getting 46ns in sandra with these settings with GDM enabled and tcrdrd 16 @1T. When disable GDM, tcrdrd 15 @ 2T im getting 46.4ns. what timings can i tighten to improve here. but my aida latency remains at 64.5ns. what timings should i try with 2T to improve latency or should go back to settings with gdm enabled and 1T.
> 
> I tried the settings you suggested but it was giving me instant errors in TM5. increasing dram voltage didnt help.


46ns which exactly, Inter-Core Latency or Inner-Core ?
SiSandra Multi-Core efficiency test, is what interests you  
Comparing the latency curve between timings and later fine adjusting inner-core delays between cores 

tRCD WR might have been too low, as it should be 13 to begin with 
Just change tRCD WR to 13 and benchmark it with SiSandra, this will be stable and won't break
Then if you can , try this exotic set








I'd love to know if this method of tWR & tRFC calculation works out 
~ as always, benchmark and compare with SiSandra to your stable set under Detailed result and write down the Inter-Core latency of both sets 
EDIT:
Usually tRFC mini shows 294-218-134 which would go well with tRTP 6 and tWR 12
Maybe compare that change too - the latency curve should show subtle differences, only tRTP 6 might be low for you (unbenched)


----------



## hmeh

Veii said:


> tRAS 28
> tRC 42
> tWR 10
> tRTP 8
> tRFC 250-186-114


Thanks, trying that out. It didn't immediately blow up in TM5, so that's good.

Here are the results between tRAS 30 and tRAS 28, two of each: https://docs.google.com/spreadsheets/d/1GDAfAZ_qYXtRrNiyBU9bPWH-1D5crB6vrGmpsv55aQs/edit?usp=sharing



Veii said:


> Be sure to benchmark the above set you currently are running 1-2 times
> Also ty, seems like we need to increase TM5 config to 25 cycles zZZ
> I hope it was just heat, or your PSU but 25 cycles for 32gb should've been around 3:10h ?
> 1h is enough to hit thermal equilibrium :thinking:


Close, 2:55h. And yeah it's somewhat consistent w/ what I saw with Karhu. A single error after a long time. Very strange. I have a good PSU (rmx 850w)




Veii said:


> tWR he/she should be at 20 usually not 12 or even now down to 10 ~ for dual rank


He  And this meaning that it's surprising that 10 runs?



Veii said:


> would be the only thing left, or trying to get GDM off 2T ~ with CL13-7-14-11-27-38, to run


Yeah... I'm guessing that'd take more voltage. I think I'm quite happy if this is stable.


----------



## pipes

only with my platform zen timings 1.0.5 no work


----------



## Veii

hmeh said:


> Thanks, trying that out. It didn't immediately blow up in TM5, so that's good.
> 
> Here are the results between tRAS 30 and tRAS 28, two of each: https://docs.google.com/spreadsheets/d/1GDAfAZ_qYXtRrNiyBU9bPWH-1D5crB6vrGmpsv55aQs/edit?usp=sharing
> 
> Close, 2:55h. And yeah it's somewhat consistent w/ what I saw with Karhu. A single error after a long time. Very strange. I have a good PSU (rmx 850w)
> 
> He  And this meaning that it's surprising that 10 runs?
> 
> Yeah... I'm guessing that'd take more voltage. I think I'm quite happy if this is stable.


It's surprising that you won't need that much write recovery time and that tRCD RD 14 works for you - even more for dual rank units
Which memory kit is this actually ? 
Where is it found inside ? 

Sadly tRAS 28 result according to stats is worse. i blame tRFC :/
Try one more sheet with even lower tRFC down to *6 _ 252-187-115 with tWR 12 and you have to try if tRTP 6 would run stable or 8 is needed
Do you have a picture result too - detailed picture result, but on everything the tRAS 28 one is worse 
Might be something else that makes issues there.


----------



## Veii

pipes said:


> only with my platform zen timings 1.0.5 no work


Ask irusanov aka infraredbg (on OCN) from the ZenState thread 
https://www.overclock.net/forum/13-amd-general/1684897-asus-zenstates-25.html


----------



## hmeh

Veii said:


> It's surprising that you won't need that much write recovery time and that tRCD RD 14 works for you - even more for dual rank units
> Which memory kit is this actually ?
> Where is it found inside ?
> 
> Sadly tRAS 28 result according to stats is worse. i blame tRFC :/
> Try one more sheet with even lower tRFC down to *6 _ 252-187-115 with tWR 12 and you have to try if tRTP 6 would run stable or 8 is needed
> Do you have a picture result too - detailed picture result, but on everything the tRAS 28 one is worse
> Might be something else that makes issues there.


This is my kit: https://www.newegg.com/g-skill-32gb...32gb_cl16 3600 g.skill-_-20-232-860-_-Product

I added an Analysis tab to the sheet that makes it pretty obvious that it's worse: https://docs.google.com/spreadsheet...9bPWH-1D5crB6vrGmpsv55aQs/edit#gid=1542351726

It is better with AIDA latency though, 63.53 vs 63.63 after 4 runs avg. So pretty small difference

Green is first set, Blue is next/slower set

Also, just to be clear, you said lower trfc, but what you're proposing is higher, 252 vs 250, just a little higher. Is that right?


----------



## hmeh

Ok, tested with tRFC 252 and updated the sheet. It's slower all around (though in one of my tests I hit 186GB/s, so it shows up better in the detailed view.

Red: tRAS 28, tRFC 252
Green: tRAS 28, tRFC 250
Yellow: tRAS 30, tRFC 264

tRTP 6 didn't blow up immediately, btw.

Also, the results from sisoft are pretty inconsistent. The first run is usually really bad. The next few start to come down. I switched back to tRAS 30 and I'm not able to get quite as low as I did before, but it's still better than the 28 (I replaced the second run in the sheet)

Also, my tRCDRD 15/WR 13 set with tRFC 315 actually scored better???


----------



## 2600ryzen

I've managed to reduce vSOC to 1.05v by reducing VDDP to 825mv and VDDG to 900mv, I didn't realize VDDP could go that low at 3800mhz. I think 2 x 750mv and 1 x 750mv is the correct stepping between vSOC/VDDG/VDDP on my kit.


----------



## Veii

hmeh said:


> This is my kit: https://www.newegg.com/g-skill-32gb...32gb_cl16 3600 g.skill-_-20-232-860-_-Product


This is some d*rn good set you got  
But i know there are also bad Neo sets out there. 



hmeh said:


> I added an Analysis tab to the sheet that makes it pretty obvious that it's worse: https://docs.google.com/spreadsheet...9bPWH-1D5crB6vrGmpsv55aQs/edit#gid=1542351726
> 
> It is better with AIDA latency though, 63.53 vs 63.63 after 4 runs avg. So pretty small difference
> Green is first set, Blue is next/slower set
> 
> Also, just to be clear, you said lower trfc, but what you're proposing is higher, 252 vs 250, just a little higher. Is that right?


Oh just bad wording - i was referring at first the 262 which had/has a bump on the blue 184.395GB/s result @ the 8x 256kb dataset 
But the 186.127GB/s compared to the 184 set is a significant change.


hmeh said:


> Ok, tested with tRFC 252 and updated the sheet. It's slower all around (though in one of my tests I hit 186GB/s, so it shows up better in the detailed view.
> 
> Red: tRAS 28, tRFC 252
> Green: tRAS 28, tRFC 250
> Yellow: tRAS 30, tRFC 264
> 
> tRTP 6 didn't blow up immediately, btw.


On SiSandra, bandwidth inter-core/inner-core latency, and also efficiency per clock = ipc 
are 3 different separated results 
The GB/s is a combined score of several factors while the latency part is split and doesn't 100% add up to the score
The curve on it's own is separated and accurate, while the logs can have a 0.01-0.02ns difference
Here we see up to 0.5ns difference up to sleeping CCD state ~ but at the end SiSandra is very very accurate 
Only the GB/s result depends also on boosting and so the frequency-to-powerdraw efficiency is factored in it. 
At least it doens't adjust the curve

Inside your bios,
Do you have inside AMD CBS -> DF or NBIO i think as it, next to Memory Channel Interleaving and hash interleaving
Any kind of option to specify the interleaving size of it ?
We still can play with tRRD_L and tWTR_L values a subtle bit in the future 

It seems like the 250 tRFC test had a tiny bump in the 256kb region when i tried to only sync it with tWR
But the 252 one is just plain better because of tRC matching 
Seems like on 250 it got postponed once 
Hmm it's not perfect yet, but ns calculation is bothersome 
Overall i'm happy that my ETA math on tRFC mini shows significant benefits 
And i appreciate a lot your charting accuracy and analysis :wubsmiley


----------



## Veii

hmeh said:


> Also, the results from sisoft are pretty inconsistent. The first run is usually really bad. The next few start to come down. I switched back to tRAS 30 and I'm not able to get quite as low as I did before, but it's still better than the 28 (I replaced the second run in the sheet)
> 
> Also, my tRCDRD 15/WR 13 set with tRFC 315 actually scored better???


Oh can you elaborate on that tRCD RD 15 set with a comparison ?
The one with GDM on ? 
We know ryzen is still locked - but only the score would be higher because it can boost better - up to stress and remain voltage
But the curve ? it will only show positive results and should be consistent ?
We only focus on the latency curve and maybe later adjust and compare inter-core & inner-core latency

EDIT:
I looked closer on the tRCD 15 set
Either it was with GDM enabled, or something else lifted strain
CPU boosted to 4.62Ghz soo the result looks higher - at least on the GB/s side of things
Efficiency and the curve should be better on the tRAS 28 set
At worst you can benchmark with SuperPi 1.5 SX (32M) to verify which set holds up boost stability longer
But then heat comes into play and makes it variable


----------



## Galaxypfm

I bought F4-4000C19D-32GTZR memory for zen1 on x370 I want to set them like F4-3600C16D-16GTZR I had them on 3466 14 15 15 15 35 1.45V, soc 1.15V with CPU OC 3.9 1.375V LLC Turbo, maybe someone uses similar memory? Dram Calculator doesn't help.


----------



## Veii

Galaxypfm said:


> I bought F4-4000C19D-32GTZR memory for zen1 on x370 I want to set them like F4-3600C16D-16GTZR I had them on 3466 14 15 15 15 35 1.45V, soc 1.15V with CPU OC 3.9 1.375V LLC Turbo, maybe someone uses similar memory? Dram Calculator doesn't help.


My signature  
You peaked maximum FCLK on this gen already, soo your high voltage might not bother
But you can pretty much remove 75mV from SOC unless it remains under high vdroop
You don't need more than 1.075v vSOC with droop included 
procODT was 53.3ohm, but maybe if you can run 48 - it could be possible for you to hit 3500MT/s with under 1.1vSOC 
3600 i got nearly stable back then but it required 1.175vSOC ~ while 3.8Ghz on low vSOC peaked 210W to cool 

Be sure to verify stability with LinpackXtreme 1.1.1 (not 1.1.2 or up) 
20 cycles is enough to make it crash it call it stable
Else yes, 700mV cLDO_VDDP, 53ohm procODT, 24-20-20-24 works on 1003ABBA else 24-24-24-24, RTT is 0/0/5 and Interleaving size is 512kb


----------



## KedarWolf

Veii said:


> My signature
> 
> 
> Spoiler
> 
> 
> 
> You peaked maximum FCLK on this gen already, soo your high voltage might not bother
> But you can pretty much remove 75mV from SOC unless it remains under high vdroop
> You don't need more than 1.075v vSOC with droop included
> procODT was 53.3ohm, but maybe if you can run 48 - it could be possible for you to hit 3500MT/s with under 1.1vSOC
> 3600 i got nearly stable back then but it required 1.175vSOC ~ while 3.8Ghz on low vSOC peaked 210W to cool
> 
> 
> Be sure to verify stability with LinpackXtreme 1.1.1 (not 1.1.2 or up)
> 20 cycles is enough to make it crash it call it stable
> Else yes, 700mV cLDO_VDDP, 53ohm procODT, 24-20-20-24 works on 1003ABBA else 24-24-24-24, RTT is 0/0/5 and Interleaving size is 512kb


I thought Linpack Xtreme 1.1.2 and higher are optimized for the new AMD CPUs?

Oh wait, they're using a different GEN CPU I think. For 3000 series 1.1.2 and up though, right?


----------



## hmeh

@Veii there is some wild deviation between runs with Sisoftware. See tRAS 30 (1) vs the others. It was my first run after booting. Since then I cant' get anywhere near there. Also, my tCL 16 set had one really good run and then the rest not as good. I wonder if I should just always throw away the first run? And I wonder what happens that causes that.

I have GDM enabled on all my sets, by the way. I can do 2T GDM off, but would that help anything at this point since I can run tCL 14? I can't run GDM off 1T, it's very unstable.

https://docs.google.com/spreadsheet...U9bPWH-1D5crB6vrGmpsv55aQs/edit#gid=148986667


----------



## Galaxypfm

Veii said:


> My signature
> You peaked maximum FCLK on this gen already, soo your high voltage might not bother
> But you can pretty much remove 75mV from SOC unless it remains under high vdroop
> You don't need more than 1.075v vSOC with droop included
> procODT was 53.3ohm, but maybe if you can run 48 - it could be possible for you to hit 3500MT/s with under 1.1vSOC
> 3600 i got nearly stable back then but it required 1.175vSOC ~ while 3.8Ghz on low vSOC peaked 210W to cool
> 
> Be sure to verify stability with LinpackXtreme 1.1.1 (not 1.1.2 or up)
> 20 cycles is enough to make it crash it call it stable
> Else yes, 700mV cLDO_VDDP, 53ohm procODT, 24-20-20-24 works on 1003ABBA else 24-24-24-24, RTT is 0/0/5 and Interleaving size is 512kb


This is my result on 2x8GB Bdie 3600 16 16 16 36 but on 2x16GB 4000 19 19 19 39 there is a problem because it either does not turn on with the same or similar settings, after a few minutes there is an error in Prime 95 at max power. Anyone have any ready settings for 2x16GB bdie?


----------



## Veii

hmeh said:


> @Veii there is some wild deviation between runs with Sisoftware. See tRAS 30 (1) vs the others. It was my first run after booting. Since then I cant' get anywhere near there. Also, my tCL 16 set had one really good run and then the rest not as good. I wonder if I should just always throw away the first run? And I wonder what happens that causes that.
> 
> I have GDM enabled on all my sets, by the way. I can do 2T GDM off, but would that help anything at this point since I can run tCL 14? I can't run GDM off 1T, it's very unstable.
> 
> https://docs.google.com/spreadsheet...U9bPWH-1D5crB6vrGmpsv55aQs/edit#gid=148986667


Please write protect your sheets if you haven't 
I misinterpreted your analysis. Lower is better - but the difference is quite big too on the tRAS 30 (1) set 
Wonder why 
Well this is part #2 of the work, main one is the latency curve
I wish you could compare sets on the DRAM calculator latency curve 

But the variability could really be only the Boards Auto settings under AMD CBS :thinking:


----------



## Veii

Galaxypfm said:


> This is my result on 2x8GB Bdie 3600 16 16 16 36 but on 2x16GB 4000 19 19 19 39 there is a problem because it either does not turn on with the same or similar settings, after a few minutes there is an error in Prime 95 at max power. Anyone have any ready settings for 2x16GB bdie?


Can you show some pictures ?
It likely is 4 things
tRDWR +2 for dual rank
tWR double for dual rank 
tRFC usually can stay low between 160-210ns
tRC +2 if you want to cheat a bit, but no post is nearly always a fault of tRDWR


----------



## Galaxypfm

.....


----------



## heptilion

Veii said:


> tRAS 28
> 46ns which exactly, Inter-Core Latency or Inner-Core ?
> SiSandra Multi-Core efficiency test, is what interests you
> Comparing the latency curve between timings and later fine adjusting inner-core delays between cores
> 
> tRCD WR might have been too low, as it should be 13 to begin with
> Just change tRCD WR to 13 and benchmark it with SiSandra, this will be stable and won't break
> Then if you can , try this exotic set
> 
> 
> 
> 
> 
> 
> 
> 
> I'd love to know if this method of tWR & tRFC calculation works out
> ~ as always, benchmark and compare with SiSandra to your stable set under Detailed result and write down the Inter-Core latency of both sets
> EDIT:
> Usually tRFC mini shows 294-218-134 which would go well with tRTP 6 and tWR 12
> Maybe compare that change too - the latency curve should show subtle differences, only tRTP 6 might be low for you (unbenched)


Ok i've run these stable timings 3 times each and got inter core latency with GDM off 2T = 45.6ns GDM on 1T = 46.5ns 
Dram Latency curve also shows a similar pattern with GDM off 2T being better.

Trcd wr 13 with 2T timings gives me a latency between the two stable timings. 46.4ns

The complete exotic timings are giving me a latency of 46.2. if i drop trcd wr to 12 an d trtp 8 i get 46.1ns. not sure why i am getting lower latency with higher timings for my stable settings. I re-tested as well. weird!

I seem to be getting better results with 14-15-13-14-28-42 with twrrd. intercore latency dropped to 43.6(Lowest i have seen) but then jumped back up to 45.9 in next 2 runs.

What would bne the ideal ram timings that line up with all the ram rules? for example my tras should be 29( 14+15) and trc 43(14+29) right?


----------



## tcclaviger

3600XT new stable settings. Sadly, the single CCD hurts the memory scores more than I expected, not just write, everything. These same settings are 62ns on the 3900x 


2 Passes of Anta Extreme TM5 and a few hours gaming.


----------



## hmeh

Veii said:


> Please write protect your sheets if you haven't
> I misinterpreted your analysis. Lower is better - but the difference is quite big too on the tRAS 30 (1) set
> Wonder why
> Well this is part #2 of the work, main one is the latency curve
> I wish you could compare sets on the DRAM calculator latency curve
> 
> But the variability could really be only the Boards Auto settings under AMD CBS :thinking:


It should only be shared read only. I really have no idea why I'm seeing such large variability in latency. I could try turning PBO off for the testing just to have a little more stability. I also tried shutting down as many windows services as I could.

I looked at the latency curves and couldn't really see any differences. They looked identical.


----------



## rares495

tcclaviger said:


> 3600XT new stable settings. Sadly, the single CCD hurts the memory scores more than I expected, not just write, everything. These same settings are 62ns on the 3900x
> 
> 
> 2 Passes of Anta Extreme TM5 and a few hours gaming.


Yeah, a 3600XT won't match a 3900X obviously, but that's not because of the single CCD. It is mostly related to cache.


----------



## hmeh

Veii said:


> Inside your bios,
> Do you have inside AMD CBS -> DF or NBIO i think as it, next to Memory Channel Interleaving and hash interleaving
> Any kind of option to specify the interleaving size of it ?
> We still can play with tRRD_L and tWTR_L values a subtle bit in the future


I have Memory interleaving and Memory interleaving size which allows 256b, 512b, 1kb, 2kb

Also, I updated the sheet to do averaging of test runs and show the bandwidth curve (zoomed in on the important part) and the latency curve (also zoomed in). I should be able to add some more runs of each. I also took out the odd super low latency ones, though I wonder if I should actually be getting better latency than I'm getting.

Would power plans impact this? I'm using Ryzen balanced.


----------



## online123

Hi,
when I turn GDM off then it's unstable at TM5.
Can you help me to run stable with the GDM off? Thanks

It is stable TM5 (config: Extreme1 @*anta777* ) with the RAM settings (1,5V):










ProcODT: Auto
RttNom: Auto (RZQ/7)
RttWr: Auto (RZQ/2)
RttPark: Auto (RZQ/1)
CsOdtSetup: Auto (0)
AddrCmdSetup: Auto (0)
CkeSetup: Auto (0)
ClkDrvStren: 24
AddrCmdDrvStren: 20
CsOdtCmdDrvStren: 24
CkeDrvStren: 24

FCLK: Auto (1800)
All CPU settings are default expect visualisation (is turned on).

PC specs:
x570 Aorus Xtreme (F20)
G.Skill TridentZ NEO 3800cl14q 4x8GB
Ryzen 3900x(stock + visualisation on)


btw. I can't boot 3800Mhz with FCLK 1:1 (1900).


----------



## 2600ryzen

online123 said:


> Hi,
> when I turn GDM off then it's unstable at TM5.
> Can you help me to run stable with the GDM off? Thanks
> 
> It is stable TM5 (config: Extreme1 @*anta777* ) with the RAM settings (1,5V):
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ProcODT: Auto
> RttNom: Auto (RZQ/7)
> RttWr: Auto (RZQ/2)
> RttPark: Auto (RZQ/1)
> CsOdtSetup: Auto (0)
> AddrCmdSetup: Auto (0)
> CkeSetup: Auto (0)
> ClkDrvStren: 24
> AddrCmdDrvStren: 20
> CsOdtCmdDrvStren: 24
> CkeDrvStren: 24
> 
> FCLK: Auto (1800)
> All CPU settings are default expect visualisation (is turned on).
> 
> PC specs:
> x570 Aorus Xtreme (F20)
> G.Skill TridentZ NEO 3800cl14q 4x8GB
> Ryzen 3900x(stock + visualisation on)
> 
> 
> btw. I can't boot 3800Mhz with FCLK 1:1 (1900).





Raise Trcdrd to 14 and Tras to 28 when you disable GDM. I think GDM rounds those values up to 14-28 anyway.


----------



## online123

2600ryzen said:


> Raise Trcdrd to 14 and Tras to 28 when you disable GDM. I think GDM rounds those values up to 14-28 anyway.


Don't boots. It stuck on postcode C3. Need to clear CMOS to boot and configure it again.


----------



## heptilion

@Veii

I have managed to get these timings stable as well. Tried to follow the timings rules as much as possible. Passed TM5 25cycles. Please have a look here as well.


----------



## Streetdragon

that works good for me so far.
Even with "odd" numbers


----------



## online123

Streetdragon said:


> that works good for me so far.
> Even with "odd" numbers


 What your CPU settings (SoC, VDDG, VDDP, ProcODT, etc.
Can you send screenshots?


----------



## Streetdragon

online123 said:


> What your CPU settings (SoC, VDDG, VDDP, ProcODT, etc.
> Can you send screenshots?


SOC 1.15 llv Auto. CPU gets undervolt of -0.1V. Its stable for me. Cooler and multicore faster.
PBO everything Auto


Edit: But i must say, that i use that for gaming only. In HomeOffice i use only xmp, one ccd and undervolt the soc(1v) and core(-0.1v)
So the CPU uses only 18-22Watts


----------



## mongoled

Veii said:


> SOC as one and only voltage, the other one would be a VID SOC which belongs to APUs, and scales up from SOC (+100mV) while is different than the main SOC line
> Renoir has variable Fabric Clock, variable Mem clock & a variable SOC voltage up to load, thermals and the remain rest
> (STAMP algorithm taken from mobile)
> 
> I have seen and had issues with variable SOC, where SOC is predefined on Matisse in 3 powerstates
> P0 = Flat, P1 and P2 = low idle
> There is no P3 sleep, normally as its the main voltage line to the CPU aside from VCORE
> I've seen it dropping down to 400mhz, while we should know by now that the Fabric is one of the hottest and most powerhungry parts of the Zen architecture
> 
> SOC has to switch to P2 state when the cpu switches to idle
> When SOC goes down, so should also go VDDG ~ which literally means, Fabric clock does go down with it but not MCLK
> But this ends up a bit contradicting, as cLDO_VDDP can not be under 700mV and doesn't move a bit
> Unsure how that voltage to the memory controller keeps getting supplied, when the main SOC line is lower
> 
> The issue atm are two,
> The leakers and the information from the corresponding persons such as Tracks (AMD) and 1usmus are accurate
> Many more know about this, but not everything is allowed to be told.
> 1usmus mentioned according to the link i send you that XT units where able to hit more than 1900FCLK - by the research on his own
> The information from me on XT is halfway by the footage i got to see and the other half decided by logic of what i've seen


OK up to now I follow you 100% 

My confusion was your use of the word "variable" when referring to vSOC, if you had spoke about the power states than there is a good probability I would have twigged and understand what you meant by variable






Veii said:


> SOC TDC, SOC EDC exists since far beyond Renoir launch and before any leak of APUs
> PPT, TDC, EDC are key values which control the throttling of anything that has to do with voltage management and variable clock
> This goes on since gen 2, while gen 2 lacked access to VDDG voltage, making cLDO_VDDP key in preventing what was known as memory hole
> A frequency which has to match it's VDDP signals to the specific MCLK frequency, in order to prevent boot and alignment issues
> Discussed and researched here
> 
> Knowing out of personal research that in order to push FCLK, good signal integrity is key
> Where low procODT and low or variable voltages are very important
> Seeing variable VSOC and fabric clock on Matisse X units far before anything Renoir was mentioned
> The logic ends up pretty clear that in order to met the boosting targets, and now looking at the key feature-set of Renoir
> Variable frequency and variable voltage up to load is key in meeting higher fabric clocks


Its a pitty there is not a means to force P0 states across all the independant clock generators for troubleshooting purposes, as if I have understood correctly it is the timely manner in which the mclk, fclk and uclk along with the CPU clk must all work synchronised and in tandem not only with regards to frequency but more importantly voltages.




Veii said:


> Looking a bit on Threadripper and the current EPYC lineup - the fabric on it's own didn't change much
> It still suffers from the same thermal and signal integrity issues since 1st gen
> Issues by design, but preventable
> 
> Usually i get some specific answers fast, or if not several leakers would've figured this out already
> But it remains a big silence when it comes to variable SOC and variable FCLK together
> Indication for it's existence while disabled? remains not only with UncoreOC mode, but also APBDIS inside AMD CBS
> APBDIS put to 1 allows for an enforced SOC powerstate which is held - neverless of the LLC state or what SMU requests
> 
> What remains suspicious is not only the silence around that topic, or the hidden bios features since a long time
> But that it doesn't behave that way anymore after the latest PSP Firmware patch on AGESA 1006 (renamed 1005)
> While it did work by using 1005/1006 Renoir microcode inside pre 1006 bios (modified 1004BB)


Ahh, didnt read futher with regards to my above comment that you have now touched upon.

So APBDIS is the means to apply consistant power states, but this has been removed, or is something you guys have seen in the BIOS that is hidden, or in AMD documentation ??



Veii said:


> About the Robert Hallock topic,
> He decided to suspend his social media accounts and got a higher work position by AMD (promotion)
> They funnily add up, but he mentioned it has nothing to do with the Renoir whitepaper and the suspension was by his own decision
> That topic is on hold so far


Good for him





Veii said:


> But the PCIe link issues fit wonderfully with higher FCLK and variable voltages
> ~ will let you know once that mystery clears up
> 
> Neverless of that topic,
> SiSoftware Sandra shows scaling and pretty much also shows the Artifical limitation of Matisse units
> Some limits got lifted when it comes to inter-core latency (some call it improvements, although nothing changed) but the Fabric Clock remains locked at 1900-1930ish Mhz and going decoupled mode doesn't scale positive like it does on Threadripper
> A big and mysterious topic, why they are locked down and since quite some time. Also why XT units aren't at least unlocked anymore when the MemController seems like isn't replaced on the retail units.
> 1950FCLK and 220+ GB/s Inter-Core Bandwidth ~ would be a very welcoming boost
> https://ranker.sisoftware.co.uk/sho...a994a583ebd6e3c5bd80b197f297aa9abccff2c2&l=en
> The highest and best result remains 210GB/s with 53ns inter-core latency, no one even slightly peaking beyond 1900FCLK
> People get nearly identical results between 1.6Ghz IMC (193-200GB/s) and 1.9GHz IMC (192-210GB/s)
> 30-40GB/s as bump for example you by going 50Mhz higher, on an 8 core
> Here we have 300Mhz difference on a 16 core for just 10ish GB/s more, likely just a constant OC stability difference between the testers
> it doesn't scale, but SiSandra is not to blame
> 
> In the older days, i remember that we can boot beyond memory controllers limits +200/+300 above it, just it would crash on any kind of memory controller load
> Today we can't even post beyond 1900FCLK, where it is more of a lockdown than a "just not possible" issue
> Tho i'm drifting away
> What i want to say is, these people who share the data are trustful, just that data sadly doesn't seem to match up retail units at the current moment
> Maybe AMD could lift that limit, soo they can actually sell these overpriced XT units finally ^^''
> ~ or maybe not, as PCIe 4.0 seems to die out


Well I am happy to take your word for it from the mouths of those that passed the information down to you.

And we are all waiting for peeps to appear here at the forum with XTs so that we can see if the community can help to decipher the puzzle

 



Veii said:


> If we speak about the voltage anomaly it likely is fine.
> I think, i've misinterpreted your issue at the start in why you'd want to inspect the boards behavior
> 
> Can you try to fix on both X370 & X570 ~ PPT TDC EDC to 90-46-50 with PBO enabled X1 scalar
> This should result in cosy voltage behavior under allcore loads while nearly be identical to the 3600X specs
> It can be that X370 has lower "AMD Recommended" limits than X570 does, or doesn't change them up to CPU model
> cLDO_VDDP , VDDG, VSOC voltage issues just remain bios bugs (AGESA bugs) with messy predictions


I cannot explain why, there is a possibility that I mixed up the two sets of 2 x 8GB Viper Steel's.

My issue was never to do with PBO, I only mentioned that I was disabling PBO so that it was known that this was not effecting the stability of the IF/RAM clocks.

After reading and reading and seeing the "Mirror Move" error explantion, and having gone through so many troubleshooting steps it dawned on me that the copying of data from one bank to the other was probably voltage dependant, so to clear things up I simply upped VDIMM from 1.5v in BIOS to 1.54v and voila no more weird error popping up in TM5!

How many hours I spent on this, swapping rigs, countless settings, countless configurations, oh well. Sorta explains why the first TM5 runs would generally pass, but after a warm boot would fail.

I am going to have to go through the 4 sticks one by one and test what voltage they require for a specific timing set etc and this time mark them so I know whats what!

I am currently back to what I was testing several days ago

CPU vCore Auto, CPU LLC 2, BCLK 107.5625 mhz, CPU PPT @142w, TDC @95a, EDC @3a, CPU Scaler @auto, CPU Boost @100 mhz, 

this give exact 3800/1900 14-15-14-14-28-42-252-16, I dropped vDIMM to 1.52v in BIOS (1.536v load HWInfo64), vDDP 0.855v, vDDG 1.025v while vSOC is @ 1.069v under load, currently on cycle 9.


----------



## glnn_23

Veii said:


> Just to confirm, you set everything at once ~ correct ?
> tRCDWR as 7 not working is unfortunate - i need to redo the whole set then as the average latency on tRCD between both WRite and ReaD is awkward. I get 10.5 out instead of 11, it can make issues
> But alright, then the slower way
> Just please confirm to me that you tried the set as a big one
> 
> Try the same set with tRCD WR 9
> tRP will still be 12 as AVG tRCD latency between 9 and 15 = 12
> that should work with tRDWR 7 and tWRRD 4 then
> 
> If you still face post issues and between 1.44-1.52v dimm nothing happens
> (always make a trashcan profile, soo you can restore on cmos clear the whole memory training settings ~ PHY, and voltages)
> Try 1.44v, 1.46, 1.48, 1.52vDIMM
> Keep in mind, anything on auto except vCore will be an issue
> 
> Yes, if nothing happens, i will need to redo your whole set with tRCD 16
> But then you will have to closely benchmark for subtle differences with SiSoftware Sandra and DRAM Calculator benchmark + it's latency curve


Hi Veii yes I set everything at once and tRDWR 7 still was a no post for me.

Also spent a bit of time trying tRCDRD 14 and got errors in TM5 so back at 15.

This is where I am at the moment.

Vdimm 1.475
Soc -0.01875 offset 1.056 load.
Vddg ccd 1.0
Vddg iod 1.0
Vddp .925


----------



## KedarWolf

@Veii

How does this look?

I can't do tRDWR 8 at all on tCL 15, won't boot.

The rest look okay?


----------



## Espenn

Hello, all. I have a 4x8GB B-die kit with A2 PCBs. I can reliably post at 3800C14, but I'm having trouble stabilizing the configuration. I have spent quite a bit of time working on it. I can pass 3 cycle of TM5, but it errors out after that. I believe my timing relationships may be off, or I have some more adjustment to do on RTT. Can anyone assist?




SOC Voltage: 1.075V
VDDG_CCD: 1.0V
VDDG_IOD: 1.025V
CLDO_VDDP: 0.9V
VDIMM: 1.525V
RTT_Nom: 7
RTT_Wr: 3
RTT_Park: 1
CAD: 20/20/20/20
ODT: 28 ohm


Utilizing the attached timings.


----------



## fingon82

For starters, try raising TRCDRD to 15


----------



## rares495

Espenn said:


> Hello, all. I have a 4x8GB B-die kit with A2 PCBs. I can reliably post at 3800C14, but I'm having trouble stabilizing the configuration. I have spent quite a bit of time working on it. I can pass 3 cycle of TM5, but it errors out after that. I believe my timing relationships may be off, or I have some more adjustment to do on RTT. Can anyone assist?
> 
> 
> 
> 
> SOC Voltage: 1.075V
> VDDG_CCD: 1.0V
> VDDG_IOD: 1.025V
> CLDO_VDDP: 0.9V
> VDIMM: 1.525V
> RTT_Nom: 7
> RTT_Wr: 3
> RTT_Park: 1
> CAD: 20/20/20/20
> ODT: 28 ohm
> 
> 
> Utilizing the attached timings.


tRP 12,
tWR 12,
tRCDRD 15,
tRDWR 8,
tWRRD 1

Also a bit more information about your PC would help a lot.


----------



## Galaxypfm

......


----------



## fingon82

Probably nothing, mem controler on cpu cant handle that memory clock


----------



## rares495

fingon82 said:


> Probably nothing, mem controler on cpu cant handle that memory clock


It probably can, you just need to spend a lot of time tweaking everything.


----------



## fingon82

Doubt it, for 1st gen ryzens, there are cpus that cant handle more than 3000mhz mem, esp because its 32gb of ram. Maybe on super loose timings, cl 18 or less for 3400


----------



## rares495

fingon82 said:


> Doubt it, for 1st gen ryzens, there are cpus that cant handle more than 3000mhz mem, esp because its 32gb of ram. Maybe on super loose timings, cl 18 or less for 3400


I used to think that until I saw the Zen sheet in this doc:

https://docs.google.com/spreadsheet...FQZp15rwWadbPTVDNgO8vtyDCM/edit#gid=525963236


----------



## PuffyArgos

Veii said:


> Hello,
> You actually already made good progress
> There are just tiny bugs you couldn't have thought off before
> 
> VDDCR SOC runs at 1.363v
> What ryzen master shows is actually accurate
> That happens because your cLDO_VDDG is already at 1.1v while only the cLDO_VDDP is at 900mV
> Soo the board thinks
> "Oh he used 200mV stepping, let's continue to use it for stability sake"
> That's why you end up at near 1.3v SOC
> 
> Please enable UncoreOC mode inside AMD OVERCLOCKING
> Afterwards, drop procODT lower and fix vSOC to 1.1v
> Usually 1.1v should work well with 34-36,9
> It might be fine for 30ohm but will be a bit much for 28ohm
> * in case your board even allows to run 28 instead of 30ohm procODT
> 
> About your timings, really nothing to complain
> You might want to push tRTP down to 6, and lower tRDWR to 7 / tWRRD 1
> In order to get that 2T away, you will need to increase ClkDrvStrengh a tiny bit
> SLC both of them should be able to go down to 3 instead 4
> but that work is for a another day
> 
> As you run procODT 40ohm, hitting 1900FCLK will be far away
> Focus so far on lowering every voltage except vDIMM
> Which speaking of, please give it a bit more
> 1.46v shouldn't bother even bad ICs
> You run tRCD 14 on 3600MT/s which is not bad at all
> But A2 PCB-kits love voltage
> Either voltage or high ClkDrvStrengh impedance under CAD_BUS
> 
> Your work for now:
> - tRTP 6, tRDWR 7,
> - vDIMM >1.46,
> - procODT <36.9ohm, vSOC not higher than 1.125, better 1.1v
> - ClkDrvStrengh >24ohm
> - focus on going to 1867/1900 FCLK after you lowered every voltage


Hey Veii, thanks again for this feedback.

I've done a bit of work since this post and wanted to see if you could give me some more feedback.

I am now at 1900mhz 1:1:1 with the following:
VDIMM: 1.52v
VDDP: 0.925v
VDDG: 1.0v
VSOC: 1.075v
ProcODT: 28.2ohm
CAD: 40/20/20/24ohm
Timings: 14-14-14-14-26-40-240-2t (further detail in the attached photo)
EDIT: GDM: Disabled

I have been struggling to get down to 1t. I can boot, but I just get washed in errors running memtest.

I am on an x570 MB (Asus ROG Strix x570-F Gaming) with a 3950x.
VCore: 1.225v
UncoreOC: Enabled
PBO: Disabled
Multiplier: 42

Any thoughts on sub timings and that pesky 2t? Thanks again, you've been a big help.


----------



## Galaxypfm

On 2x8GB memories I got 3466mhz CL14 from Ryzen 1700. I don't know if the reason is 32GB or the memory is weak, it says that they are BCPB but what can mean RAW Card: B1?


----------



## Espenn

rares495 said:


> tRP 12,
> tWR 12,
> tRCDRD 15,
> tRDWR 8,
> tWRRD 1
> 
> Also a bit more information about your PC would help a lot.



Apologies. I thought the advice would be relatively generic. It's a 3900X with an Asus CH8H. I've customized the Digi+ menu already to improve VRM performance. I have active airflow on the DIMMs. Please let me know what other specs you'd like to see.


*EDIT: *tRP 12 is a definite no-go. Full of immediate errors when starting a memory tester. Seems to be working a bit better with the attached timings, but still too early to tell.


*EDIT 2: *The below timings pass 10 cycles of TM5 for me. I'd really like to find a way to bring the Vdimm down closer to 1.48V. I wonder if this is even possible. This is 925 CLDO_VDDP, 1540 Vdimm, 1075 Vsoc, 1025 Vddg_iod, 950 vddg_soc.


----------



## mongoled

Id like to hear peoples opinions on what they deem is "acceptable" for a dual kit of RAM with regards to voltages.

Example.

The first set of 2 x 8GB 4400 Viper Steel I purchased when each stick is tested seperatly both need 1.43v to be stable at 3600/1800 14-14-14-14-28-42-294

The second set of 2 x 8GB 4400 Viper Steel I purchased when each stick is tested seperatly one of the sticks need 1.43v to be stable at 3600/1800 14-14-14-14-28-42-294, while the other stick requires 1.47v a difference of 0.04v.

What do people think, would you accept such difference in a kit of RAM that is sold as a dual kit ?

Thanks


----------



## mongoled

nick name said:


> So kinda fun thing with the new 3600C15 kit. It can do speed better than my old 3600C15 kit. The old kit could easily do 4400MHz 18-20-18-18 and the new kit does 4400MHz 16-18-16-16 with tight timings. And the old kit would almost never POST at 4600MHz with craptastic timings while the new kit will easily POST 4600MHz 18-20-18-18 and tight timings.


Can you provide some info regards into what settings you were using for the 4400 mhz CL16 testing for

vSOC/vDDP/vDDG/vDIMM
ProcODT
RTT_NOM
RTT_WR
RTT_PARK
ClkDrv
AddrCmdDrv
CsOdtDrv
CkeDrv

Thanks


----------



## heptilion

mongoled said:


> Id like to here peoples opinions on what they deem is "acceptable" for a dual kit of RAM with regards to voltages.
> 
> Example.
> 
> The first set of 2 x 8GB 4400 Viper Steel I purchased when each stick is tested seperatly both need 1.43v to be stable at 3600/1800 14-14-14-14-28-42-294
> 
> The second set of 2 x 8GB 4400 Viper Steel I purchased when each stick is tested seperatly one of the sticks need 1.43v to be stable at 3600/1800 14-14-14-14-28-42-294, while the other stick requires 1.47v a difference of 0.04v.
> 
> What do people think, would you accept such difference in a kit of RAM that is sold as a dual kit ?
> 
> Thanks


i would find this to be very annoying but unless its not able to run at the rated speed with rated voltage, can't really do much


----------



## mongoled

heptilion said:


> i would find this to be very annoying but unless its not able to run at the rated speed with rated voltage, can't really do much


Well its through Amazon.de, but I reached out to the third party seller to see what they say.

The issue if this particular kit is running to spec is clouded because I would have to test them on an Intel setup which I do not own to be able to really see if they can run at the specs they are advertised at...


----------



## GhostCow

I read a review on newegg of the ram I just ordered that said it doesn't work on the asus prime x570-p and then another review from a user that said they did get it working but didn't say how. Googling the model number led me to this thread. I see another user in here was having trouble getting the g.skill F4-3600C16D-32GVKC to work. Has anyone here managed to get this memory working with a Ryzen cpu and if so, at what settings? I probably won't have a cpu to actually finish the build for a while so I'm pretty paranoid that I just bought something I won't be able to use or return. Maybe I'd be better off waiting for Zen 3 and hoping it has a better memory controller than Zen 2? Big mistake on my part. Ugh.


----------



## VPII

GhostCow said:


> I read a review on newegg of the ram I just ordered that said it doesn't work on the asus prime x570-p and then another review from a user that said they did get it working but didn't say how. Googling the model number led me to this thread. I see another user in here was having trouble getting the g.skill F4-3600C16D-32GVKC to work. Has anyone here managed to get this memory working with a Ryzen cpu and if so, at what settings? I probably won't have a cpu to actually finish the build for a while so I'm pretty paranoid that I just bought something I won't be able to use or return. Maybe I'd be better off waiting for Zen 3 and hoping it has a better memory controller than Zen 2? Big mistake on my part. Ugh.


Hi there, I had this set before I got a second set of G-Skill FlareX DDR4 3200 which I run now with two sets of the same memory at 3733 with 1866 FCLK. I did however run the set you posted without an issue, I actually ran it with my first set of G-Skill FLare X 2 x 8GB for total 24GB memory and it worked without an issue. I could not clock the memory higher though, but then again I did not test it higher all that much before I sold it again. But it should work without an issue at the rated speed and timings. Let me know when you have it running.


----------



## GhostCow

VPII said:


> Hi there, I had this set before I got a second set of G-Skill FlareX DDR4 3200 which I run now with two sets of the same memory at 3733 with 1866 FCLK. I did however run the set you posted without an issue, I actually ran it with my first set of G-Skill FLare X 2 x 8GB for total 24GB memory and it worked without an issue. I could not clock the memory higher though, but then again I did not test it higher all that much before I sold it again. But it should work without an issue at the rated speed and timings. Let me know when you have it running.


Thanks! This gives me hope! The issue might be specific to the motherboard I bought, but I see there was a bios update for it earlier this month that is supposed to improve dram compatibility. I'll return to this thread when I complete my build and let you know how it went. It will be before the end of the year. I'm still torn between buying a 3800x or waiting for Zen 3 but we'll see how much longer I feel like waiting once I have an Ampere card in my hands.


----------



## nick name

mongoled said:


> Can you provide some info regards into what settings you were using for the 4400 mhz CL16 testing for
> 
> vSOC/vDDP/vDDG/vDIMM
> ProcODT
> RTT_NOM
> RTT_WR
> RTT_PARK
> ClkDrv
> AddrCmdDrv
> CsOdtDrv
> CkeDrv
> 
> Thanks


Almost all of that was on Auto. 

SOC 1.106V (droop down to 1.1V)
VDDG 1.05V
DRAM Voltage ~ 1.6V


----------



## PuffyArgos

PuffyArgos said:


> Hey Veii, thanks again for this feedback.
> 
> I've done a bit of work since this post and wanted to see if you could give me some more feedback.
> 
> I am now at 1900mhz 1:1:1 with the following:
> VDIMM: 1.52v
> VDDP: 0.925v
> VDDG: 1.0v
> VSOC: 1.075v
> ProcODT: 28.2ohm
> CAD: 40/20/20/24ohm
> Timings: 14-14-14-14-26-40-240-2t (further detail in the attached photo)
> EDIT: GDM: Disabled
> 
> I have been struggling to get down to 1t. I can boot, but I just get washed in errors running memtest.
> 
> I am on an x570 MB (Asus ROG Strix x570-F Gaming) with a 3950x.
> VCore: 1.225v
> UncoreOC: Enabled
> PBO: Disabled
> Multiplier: 42
> 
> Any thoughts on sub timings and that pesky 2t? Thanks again, you've been a big help.


As an update, I have now cracked 1t.
I just had to bump CAD to 60/20/20/24ohm and increase timings to 14-14-14-14-28-42-252.

Stable at:
1900mhz 1:1:1
VDIMM: 1.52v
VDDP: 0.925v
VDDG: 1.0v
VSOC: 1.075v
ProcODT: 28.2ohm
CAD: 60/20/20/24ohm
Timings: 14-14-14-14-28-42-252-1t
GDM: Disabled


----------



## Veii

PuffyArgos said:


> As an update, I have now cracked 1t.
> I just had to bump CAD to 60/20/20/24ohm and increase timings to 14-14-14-14-28-42-252.
> 
> Stable at:
> 1900mhz 1:1:1
> VDIMM: 1.52v
> VDDP: 0.925v
> VDDG: 1.0v
> VSOC: 1.075v
> ProcODT: 28.2ohm
> CAD: 60/20/20/24ohm
> Timings: 14-14-14-14-28-42-252-1t
> GDM: Disabled


Wonderful 
Did you run before tWR 10 or tWR 12 
with 10 it could work, but with 12 
tCL 14 + tWR 12 + tBL 2 = 28 , 26 wouldn't have worked 

You might want to submit your result here
https://docs.google.com/spreadsheets/d/1HKPVfDcFO-aieAOXHFQZp15rwWadbPTVDNgO8vtyDCM/
Just for statistic and helping purposes for others
There aren't many kits who do flat CL 14 @ 1900MCLK


----------



## mongoled

PuffyArgos said:


> As an update, I have now cracked 1t.
> I just had to bump CAD to 60/20/20/24ohm and increase timings to 14-14-14-14-28-42-252.
> 
> Stable at:
> 1900mhz 1:1:1
> VDIMM: 1.52v
> VDDP: 0.925v
> VDDG: 1.0v
> VSOC: 1.075v
> ProcODT: 28.2ohm
> CAD: 60/20/20/24ohm
> Timings: 14-14-14-14-28-42-252-1t
> GDM: Disabled


I would like to see some stability tests with [email protected] as that is a very very rare thing when running at 3800/1900 !

** EDIT **
Will have to return to cracking it! Just when I thought I had finally tied down my rig to a 24/7 stable set up you post straight 14s


----------



## mongoled

nick name said:


> Almost all of that was on Auto.
> 
> SOC 1.106V (droop down to 1.1V)
> VDDG 1.05V
> DRAM Voltage ~ 1.6V


Ooouuuuuuu 1.6v 

:wheee:


----------



## nick name

mongoled said:


> Ooouuuuuuu 1.6v
> 
> :wheee:


Yeah. I don't think I'd run it daily.


----------



## nick name

I've added my new 3600C15 kit to my old 3600C15 kit and luckily I can run all 32GB at the settings of the old 3600C15. I was afraid I would have to back off due to the increased capacity, but it appears that I lucked out.


----------



## mongoled

nick name said:


> I've added my new 3600C15 kit to my old 3600C15 kit and luckily I can run all 32GB at the settings of the old 3600C15. I was afraid I would have to back off due to the increased capacity, but it appears that I lucked out.


Excellent!


----------



## nick name

mongoled said:


> Excellent!


It's not the crazy timings some folks are getting with the 2x16GB kits, but it isn't worse than I had.  

I wish I had a kit that could to 14-13-13-13. That blows my mind.


----------



## PuffyArgos

Veii said:


> Wonderful
> Did you run before tWR 10 or tWR 12
> with 10 it could work, but with 12
> tCL 14 + tWR 12 + tBL 2 = 28 , 26 wouldn't have worked
> 
> You might want to submit your result here
> https://docs.google.com/spreadsheets/d/1HKPVfDcFO-aieAOXHFQZp15rwWadbPTVDNgO8vtyDCM/
> Just for statistic and helping purposes for others
> There aren't many kits who do flat CL 14 @ 1900MCLK


I run tWR at 10, which is why I thought I could get away with 26-40-240. With 2t it worked just fine, and in fact, benches higher than 28-42-252 1t. I will likely revisit the attempt to get 26-40-240 1t, but that is a project for another day.

I will definitely contribute to the spreadsheet, hopefully it helps someone.

Edit: For clarity, 26-40-240 2t scores higher on xmrig (likely a function of the algorithm it uses), but 28-42-252 1t passes memtest quicker. Even though I built the computer to hash randomx, I don't actually care about maximising profit so I'm sticking with 1t. Mining was just an excuse to build another computer with a great cpu and quick memory. I've had a great time falling down the rabbit hole of RAM OC and have no intention of crawling out anytime soon.



mongoled said:


> I would like to see some stability tests with [email protected] as that is a very very rare thing when running at 3800/1900 !
> 
> ** EDIT **
> Will have to return to cracking it! Just when I thought I had finally tied down my rig to a 24/7 stable set up you post straight 14s


The whole process was about 6 weeks on and off, so it took some work. I'm pretty new to memory OC so I'm still working on getting reliable software for testing. Right now I use memtest for an initial test and xmrig to stress it out (runs 24/7). If you point me in the right direction I'd be happy to test some more and post results.

Edit: I'm in the UK so I don't have A/C. We're forecast to get up to 30 on Friday so I'll be back down to 1800 at 1.46v just to keep things cool. If I can't get some tests done before then, I'll get after it early next week.


----------



## mongoled

PuffyArgos said:


> I run tWR at 10, which is why I thought I could get away with 26-40-240. With 2t it worked just fine, and in fact, benches higher than 28-42-252 1t. I will likely revisit the attempt to get 26-40-240 1t, but that is a project for another day.
> 
> I will definitely contribute to the spreadsheet, hopefully it helps someone.
> 
> Edit: For clarity, 26-40-240 2t scores higher on xmrig (likely a function of the algorithm it uses), but 28-42-252 1t passes memtest quicker. Even though I built the computer to hash randomx, I don't actually care about maximising profit so I'm sticking with 1t. Mining was just an excuse to build another computer with a great cpu and quick memory. I've had a great time falling down the rabbit hole of RAM OC and have no intention of crawling out anytime soon.
> 
> 
> 
> The whole process was about 6 weeks on and off, so it took some work. I'm pretty new to memory OC so I'm still working on getting reliable software for testing. Right now I use memtest for an initial test and xmrig to stress it out (runs 24/7). If you point me in the right direction I'd be happy to test some more and post results.
> 
> Edit: I'm in the UK so I don't have A/C. We're forecast to get up to 30 on Friday so I'll be back down to 1800 at 1.46v just to keep things cool. If I can't get some tests done before then, I'll get after it early next week.


Hi!

Go here

https://www.overclock.net/forum/27937684-post4314.html

TM5 is a relatively quick memory test you can run.

In the "bin" directory open the "MT.cfg" file using notepad and at the top of the [Main Section] edit the line "Cycles" to 25.

Make sure you save the file as .cfg

You will probably have to have the option "show extension for known file types" enabled otherwise you wont be able to remove the .txt extension notepad will automatically add.

If you can run TM5 for 25 cycles than its a good sign that the memory is good for flat 14s.

Most people posting here, as yourself, have tried for days, weeks and some, months on end   to get flat 14s 3800/1900 with GDM off and 1T to be TM5 stable as tRCDRD does not respond to increase in voltage, its dependent on the binning of the modules (and probs PCB) and would have to be capable of tRCDRD at 14 at said mclk/fclk to be able to be TM5 stable.

I can get up to 6 cycles than it will crap out, but im on a X370 motherboard, my current stable settings below (TM5 25 Cycles, Y-Cruncher +6 hours)

BCLK @107.5625 (PCIe is set @Gen2)
EDC @3
vDIMM @1.536v (HWInfo64)
vSOC @1.440v (HWInfo64)
vDDP @0.805v
vDDG IOD/CCD @1.00v
ProcODT @28 ohms
RTT_NOM @off
RTT_WR @off
RTT_PARK @48 ohms
ClkDrv @20 ohms
AddrCmdDrv @20 ohms
CsOdtDrv @24 ohms
CkeDrv @24 ohms


----------



## nick name

So new G.Skill 4400C19 kit came in and it can do 14-13-13-13, but I can't get tCWL to 12.


----------



## 2600ryzen

nick name said:


> So new G.Skill 4400C19 kit came in and it can do 14-13-13-13, but I can't get tCWL to 12.



Can you run GDM off? I think trcd's get rounded up to even numbers with GDM.


----------



## rares495

nick name said:


> So new G.Skill 4400C19 kit came in and it can do 14-13-13-13, but I can't get tCWL to 12.


tCWL 14 or 12 is the same $h1t.

You can still work on a few timings.

Plus you can't say "it can do this and that" until you've passed 20 cycles in TM5.


----------



## nick name

2600ryzen said:


> Can you run GDM off? I think trcd's get rounded up to even numbers with GDM.


No, it won't POST with GDM off.

Edit:
Got it to POST but then BSOD during Aida.


----------



## nick name

rares495 said:


> tCWL 14 or 12 is the same $h1t.
> 
> You can still work on a few timings.
> 
> Plus you can't say "it can do this and that" until you've passed 20 cycles in TM5.


Yeah, tCWL lower than tCL doesn't seem to actually change performance, but I'm sure it does something. 

There aren't really any timings worth changing beyond what they are. At least in the sense of going lower.

And I can say "it can do this and that" as I clearly displayed what it could do. I didn't make any claim beyond what I posted. If I run something overnight then I'll show and call it such. The kit will also "do" 4600MHz at 16-18-16-16 and tight timings though it "does" it with high voltage and is unstable.


----------



## rastaviper

Veii said:


> Start with:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> See what you need to run this (voltage vise and maybe 2T at worst ?)
> 
> later push SD DD's down to 5-5-7-7
> 
> tRAS was too low at the start, needed to be at least 29, and tRC was just high without reasoning
> 
> tCWL 14 ≠ tCL was preventing tRDWR to be low, and as it can only be an even value even without GDM, 16 would've been better
> 
> tCL 15 + tWR 12 + tBL 2 = 29 , 28 was too low
> 
> EDIT:
> 
> Actually still push tCWL to 16 ~ forgot to add it
> 
> * rly need a better picture editor than ShareX


Managed to run all settings at 1T except the TRDWR that can't go any lower than 8.

Aida runs up to 4.500mhz with 62.5

Sent from my ONEPLUS A6003 using Tapatalk


----------



## Ortus

I left all the CAD values on auto while I was tuning this kit until I made another pass at tRCD 14. When I checked the auto values so I could go up/down a step, ClkDrv was on 60(!), a number I've never seen anyone using.

Lowering to the normal 24/20 range gives errors in HCI almost instantly, what's the deal?


----------



## rares495

nick name said:


> Yeah, tCWL lower than tCL doesn't seem to actually change performance, but I'm sure it does something.
> 
> There aren't really any timings worth changing beyond what they are. At least in the sense of going lower.
> 
> And I can say "it can do this and that" as I clearly displayed what it could do. I didn't make any claim beyond what I posted. If I run something overnight then I'll show and call it such. The kit will also "do" 4600MHz at 16-18-16-16 and tight timings though it "does" it with high voltage and is unstable.


That's not my definition of "doing" x and y with z voltage but ok. You "do" you.


----------



## Veii

Ortus said:


> I left all the CAD values on auto while I was tuning this kit until I made another pass at tRCD 14. When I checked the auto values so I could go up/down a step, ClkDrv was on 60(!), a number I've never seen anyone using.
> 
> Lowering to the normal 24/20 range gives errors in HCI almost instantly, what's the deal?


Common knowledge at this point, the calculator is just a bit old to reflect it 
See TechpowerUp 1usmus Matisse threadripper teardown and OC 
On Single Rank, you should use SD DDs as 1-5-5-1-7-7 instead of 1-4-4-1-6-6 
4-4 6-6 are for dual rank , lower here is not better
What you also can change is tRRD_S to 5 and tWTR_L to 10, later RRD_S to 4 , tWTR_S to 8

EDIT:
You could technically lower ClkDrvStrengh to 40
60 is mostly for A2 PCB kits, while the 4000C19 are A0 
Shouldn't need more than 30-40 ClkDrv
but higher does help in using lower procODT


----------



## mongoled

Veii said:


> Common knowledge at this point, the calculator is just a bit old to reflect it
> See TechpowerUp 1usmus Matisse threadripper teardown and OC
> On Single Rank, you should use SD DDs as 1-5-5-1-7-7 instead of 1-4-4-1-6-6
> 4-4 6-6 are for dual rank , lower here is not better
> What you also can change is tRRD_S to 5 and tWTR_L to 10, later RRD_S to 4 , tWTR_S to 8
> 
> EDIT:
> You could technically lower ClkDrvStrengh to 40
> 60 is mostly for A2 PCB kits, while the 4000C19 are A0
> Shouldn't need more than 30-40 ClkDrv
> but higher does help in using lower procODT


Well my Viper Steel 4400 sure dont follow that rule



I am using ClkDrvStrengh @20 ohms and ProcODT is @28 ohms while vSOC is 1.044v

I have a rock stable setup with BCLK @107.5625 3800/1900.

Must be an X370 thing ....


----------



## nick name

Veii said:


> Common knowledge at this point, the calculator is just a bit old to reflect it
> See TechpowerUp 1usmus Matisse threadripper teardown and OC
> On Single Rank, you should use SD DDs as 1-5-5-1-7-7 instead of 1-4-4-1-6-6
> 4-4 6-6 are for dual rank , lower here is not better
> What you also can change is tRRD_S to 5 and tWTR_L to 10, later RRD_S to 4 , tWTR_S to 8
> 
> -snip-


I've never heard that. Do you know why?


----------



## 2600ryzen

nick name said:


> Yeah, tCWL lower than tCL doesn't seem to actually change performance, but I'm sure it does something.
> 
> There aren't really any timings worth changing beyond what they are. At least in the sense of going lower.
> 
> And I can say "it can do this and that" as I clearly displayed what it could do. I didn't make any claim beyond what I posted. If I run something overnight then I'll show and call it such. The kit will also "do" 4600MHz at 16-18-16-16 and tight timings though it "does" it with high voltage and is unstable.



On my dual rank kit tcwl=(tcl - 2) lets me run twrrd at 1. Seems to help bandwidth.


----------



## nick name

So new G.Skill 4400C19 kit came in and it can do 14-13-13-13.


----------



## 2600ryzen

I think your trcd is really 14 because you have GDM enabled.


----------



## nick name

2600ryzen said:


> I think your trcd is really 14 because you have GDM enabled.


See that's hard for me to know because tCL will change from odd to even yet those timings don't change. I don't know what is actually happening.


----------



## 2600ryzen

You can benchmark the difference between 13-14 and if there's no difference then GDM is probably rounding it up to 14 anyway.


----------



## Ortus

Veii said:


> Common knowledge at this point, the calculator is just a bit old to reflect it
> See TechpowerUp 1usmus Matisse threadripper teardown and OC
> On Single Rank, you should use SD DDs as 1-5-5-1-7-7 instead of 1-4-4-1-6-6
> 4-4 6-6 are for dual rank , lower here is not better
> What you also can change is tRRD_S to 5 and tWTR_L to 10, later RRD_S to 4 , tWTR_S to 8


Changing SD DDs to the higher value didn't seem to make a difference in AIDA but noticeably increased the amount of time HCI took in dram calc, membench easy went from around 101s to around 108s. It looked like it was also increasing the time Kahru was taking but I didn't think to record times for Kahru the whole way down.


----------



## rastaviper

Veii said:


> Start with:
> 
> 
> 
> 
> 
> 
> 
> 
> See what you need to run this (voltage vise and maybe 2T at worst ?)
> later push SD DD's down to 5-5-7-7
> tRAS was too low at the start, needed to be at least 29, and tRC was just high without reasoning
> tCWL 14 ≠ tCL was preventing tRDWR to be low, and as it can only be an even value even without GDM, 16 would've been better
> tCL 15 + tWR 12 + tBL 2 = 29 , 28 was too low
> EDIT:
> Actually still push tCWL to 16 ~ forgot to add it
> * rly need a better picture editor than ShareX


 @Veii

As I have mentioned at a previous post, I have managed to run all of them with 1T, except the tRDWR which at 7 didn't allow my system to boot.
Anything else to push more? Can you explain what is the 5-5-7-7 for the SD DD's exactly?

And the tRas should be 27 as in your image or 29? Because I have it at 27 and it runs fine.


----------



## nick name

Since I can't find any concrete answer on odd primaries (tRCD) being changed to even I went ahead and just set 14-14-14-14 with tCWL at 12. Thanks to @2600ryzen for reminding me that I needed tWRRD set to 1 and tRDWR at 10 to drop tCWL below tCL. I used to leave those on Auto but this latest CH7 BIOS sets them super high when left on Auto. I set tRFC to 6 x tRC. Honestly, that's kinda why I liked 14-13-13-13 because I could set tRC to 40 and tRFC to 240. Setting tRFC to 252 just bugs me. 

So ten hours of Karhu. The warmest the DIMMs got was 42*C and I set 1.5V with a droop to 1.48V according to HWiNFO. I think I can drop the voltage a touch, but 1.5V is kinda my default. My SOC is 1.106V with a droop to 1.1V and VDDG 1.05V and VDDP 1.0V. Everything else set to Auto. 

GDM off results in immediate errors though it will POST and boot. 

So it appears that running straight 14s depends on your RAM and not your settings. I'm not sure what attribute of the RAM allows for it though. Whether it's die quality or something else. 

CPU cache is set to enabled in Karhu.


----------



## rares495

nick name said:


> Since I can't find any concrete answer on odd primaries (tRCD) being changed to even I went ahead and just set 14-14-14-14 with tCWL at 12. Thanks to @2600ryzen for reminding me that I needed tWRRD set to 1 and tRDWR at 10 to drop tCWL below tCL. I used to leave those on Auto but this latest CH7 BIOS sets them super high when left on Auto. I set tRFC to 6 x tRC. Honestly, that's kinda why I liked 14-13-13-13 because I could set tRC to 40 and tRFC to 240. Setting tRFC to 252 just bugs me.
> 
> So ten hours of Karhu. The warmest the DIMMs got was 42*C and I set 1.5V with a droop to 1.48V according to HWiNFO. I think I can drop the voltage a touch, but 1.5V is kinda my default. My SOC is 1.106V with a droop to 1.1V and VDDG 1.05V and VDDP 1.0V. Everything else set to Auto.
> 
> GDM off results in immediate errors though it will POST and boot.
> 
> So it appears that running straight 14s depends on your RAM and not your settings. I'm not sure what attribute of the RAM allows for it though. Whether it's die quality or something else.
> 
> CPU cache is set to enabled in Karhu.


tCWL 12 does nothing. tRDWR 10 is too high, even 8 is too much for tRCDRD 14 but you probably can't go lower than 8.


----------



## nick name

rares495 said:


> tCWL 12 does nothing. tRDWR 10 is too high, even 8 is too much for tRCDRD 14 but you probably can't go lower than 8.


I'm kind of of the same opinion. I am torn between whether setting tCWL lower with a higher tRDWR is worth it or not. Every time I do it I leave it for a while and then change my mind and adjust it. 

When I could leave it at Auto my mobo would set each channel a little different, but the values (tRDWR and tWRRD) would add up to either 10 or 11. So I try to use that as rule when I set it manually and I rationalize tRDWR at 10 because that and tWRRD still add up to the same. 

As far as tRCDRD and it's relation to other timings -- I can never remember.


----------



## rares495

nick name said:


> I'm kind of of the same opinion. I am torn between whether setting tCWL lower with a higher tRDWR is worth it or not. Every time I do it I leave it for a while and then change my mind and adjust it.
> 
> When I could leave it at Auto my mobo would set each channel a little different, but the values (tRDWR and tWRRD) would add up to either 10 or 11. So I try to use that as rule when I set it manually and I rationalize tRDWR at 10 because that and tWRRD still add up to the same.
> 
> As far as tRCDRD and it's relation to other timings -- I can never remember.


Veii can tell you more but lowering tRDWR was always the first thing he recommended. I think ideally you want it to be half of tRCDRD but it will never work so (tRCDRD/2)+1 is what most people end up using. As far as I could tell, it really matters more than tCWL for performance.


----------



## nick name

rares495 said:


> Veii can tell you more but lowering tRDWR was always the first thing he recommended. I think ideally you want it to be half of tRCDRD but it will never work so (tRCDRD/2)+1 is what most people end up using. As far as I could tell, it really matters more than tCWL for performance.


Welp, let's give that a go then.

Edit:
Yeah, I can't use tRCD / 2. I have to +1 it.


----------



## 2600ryzen

I think lower tcwl increases copy performance, not sure.


Edit: looks like it's the other way around, I just tested tcwl 14 trdwr 11-1 v tcwl 16 trdwr 8-3 and 8-3 had better copy BW.


----------



## Ortus

Turns out being unable to lower tRCDRD further might be entirely temperature related, all the other timings are fine up to 50c at least, but tRCDRD starts throwing errors at 30.5c, spewing them at 36, and crashing at 41.

Probably not cracking that when my room hits 25c ambient most of the year.


----------



## rares495

Ortus said:


> Turns out being unable to lower tRCDRD further might be entirely temperature related, all the other timings are fine up to 50c at least, but tRCDRD starts throwing errors at 30.5c, spewing them at 36, and crashing at 41.
> 
> Probably not cracking that when my room hits 25c ambient most of the year.


Very interesting. Will have to pop my 120 fan back in and test it.


----------



## Ortus

rares495 said:


> Very interesting. Will have to pop my 120 fan back in and test it.


My tests had a 120mm straight over the dimms with the case open and I still couldn't keep them below 30 for more than a few minutes :sadsmiley

Even when ambient is lower I assume relative humidity is too high to transfer heat properly anyway, hopefully you have better luck


----------



## rares495

Ortus said:


> My tests had a 120mm straight over the dimms with the case open and I still couldn't keep them below 30 for more than a few minutes :sadsmiley
> 
> Even when ambient is lower I assume relative humidity is too high to transfer heat properly anyway, hopefully you have better luck


Yeah, ambient is quite high here because there's no AC in my room, sadly.


----------



## chitos123

https://docs.google.com/spreadsheet...V3BjdL-dcfJJeyhdSAoJmuzJE/edit#gid=1439155382


Please test my calculator
And tell me, any mistake or wrong calculation


----------



## hazium233

Ortus said:


> Turns out being unable to lower tRCDRD further might be entirely temperature related, all the other timings are fine up to 50c at least, but tRCDRD starts throwing errors at 30.5c, spewing them at 36, and crashing at 41.
> 
> Probably not cracking that when my room hits 25c ambient most of the year.


I have wondered about this with my Rev E because this current set seems to be error free with tRCDRD at 10ns in GSAT for ~hour, but once tested with Karhu, TM5 or HCI the errors appear within a few minutes. Don't have dimm temp sensors though.


----------



## Veii

chitos123 said:


> https://docs.google.com/spreadsheet...V3BjdL-dcfJJeyhdSAoJmuzJE/edit#gid=1439155382
> 
> Please test my calculator
> And tell me, any mistake or wrong calculation











* and calculate tRAS with:
tCL+tWR+tBL if user decides so
Want to collaborate together or do you rush to make an own version ? 
Are you familiar with Android Studio or Apple XCode ?

Such switches are needed on google docs, as too much depends on patterns 
SR, DR are different , and amount of dimms change too
Exmpl:








Similar, with option boxes


----------



## Veii

Ortus said:


> Changing SD DDs to the higher value didn't seem to make a difference in AIDA but noticeably increased the amount of time HCI took in dram calc, membench easy went from around 101s to around 108s. It looked like it was also increasing the time Kahru was taking but I didn't think to record times for Kahru the whole way down.


If you've gone down to tRCD 14 instead of 15 - tRDWR 7 would be better than 8
tRCD RD / 2 = tRDWR has to work on 16Gb dimms, but it won't if you waste some latency somewhere


rares495 said:


> Veii can tell you more but lowering tRDWR was always the first thing he recommended. I think ideally you want it to be half of tRCDRD but it will never work so (tRCDRD/2)+1 is what most people end up using. As far as I could tell, it really matters more than tCWL for performance.
> 
> 
> 2600ryzen said:
> 
> 
> 
> I think lower tcwl increases copy performance, not sure.
> 
> Edit: looks like it's the other way around, I just tested tcwl 14 trdwr 11-1 v tcwl 16 trdwr 8-3 and 8-3 had better copy BW.
Click to expand...

Using low tCWL was on the intel side of things a tweak, as they have tRAS, tRFC, tREFI as scales and a lot of split optimisations on the 
tRDWR -> tRRDR
tWRRD -> tRRDD
AMD -> Intel 
Side of things
tRC i haven't seen anywhere changable and the "best way" to get lower performance was to drop tCWL
But tCWL <-> tRDWR go hand in hand
If you lower one, you have to up the other one by the same amount

on AMD , tRDWR i found to be next to SCL the biggest perf increase factor 
If tRDWR = tRCD RD / 2 won't work
just add a bit of latency on tWRRD, then it will work
Usually it shouldn't need it, only when you go -1 of half tRCD 
((tRCD RD/2)-1) on Single Rank dimms works even when you lower tRC -2 


rastaviper said:


> @Veii
> 
> As I have mentioned at a previous post, I have managed to run all of them with 1T, except the tRDWR which at 7 didn't allow my system to boot.
> Anything else to push more? Can you explain what is the 5-5-7-7 for the SD DD's exactly?
> 
> And the tRas should be 27 as in your image or 29? Because I have it at 27 and it runs fine.


I can't fully yet 
They are added transfer delays, while running 1-1-1-1-1-1 works on unstable kits but results in at least 8-10% perf drop
I follow 1usmus's research here, pretty sure dimm amount does define the values and likely also PCB revision ~ as they are just cutoff delays
tRAS i had as 27 in the picture because tWR was 10
What you see in black or whatever colour fits for the time, everything that is applied needs a change at the same time
If one thing is off, the set might break  
If nothing was written, just continue to use what you have
tRAS 29 was for your set, tRAs 27 was if you follow the remain timings which do include tWR at 10
As we know
tCL+tWR+tBL = tRAS 


nick name said:


> Since I can't find any concrete answer on odd primaries (tRCD) being changed to even I went ahead and just set 14-14-14-14 with tCWL at 12. Thanks to @2600ryzen for reminding me that I needed tWRRD set to 1 and tRDWR at 10 to drop tCWL below tCL. I used to leave those on Auto but this latest CH7 BIOS sets them super high when left on Auto. I set tRFC to 6 x tRC. Honestly, that's kinda why I liked 14-13-13-13 because I could set tRC to 40 and tRFC to 240. Setting tRFC to 252 just bugs me.
> 
> So ten hours of Karhu. The warmest the DIMMs got was 42*C and I set 1.5V with a droop to 1.48V according to HWiNFO. I think I can drop the voltage a touch, but 1.5V is kinda my default. My SOC is 1.106V with a droop to 1.1V and VDDG 1.05V and VDDP 1.0V. Everything else set to Auto.
> 
> GDM off results in immediate errors though it will POST and boot.
> 
> So it appears that running straight 14s depends on your RAM and not your settings. I'm not sure what attribute of the RAM allows for it though. Whether it's die quality or something else.
> 
> CPU cache is set to enabled in Karhu.


tRCD depends on the IC binning and the PCB, a bit on the voltage but the same goes for ClkDrvStrengh 
There has to be enough so the dimms can run GDM disabled and can be driven, but more won't do anything 
Could maybe pass-bye with 0.2v more to lower primaries one step further down, but then it also depends how the IC scales and if it can even run voltage beyond 1.56v
A bigger advantage of voltage you get by being able to lower tRP 
Which logically lowers tRC

You can test your luck on the dimms how low you can get tRC ~ likely micron has different scaling than b-dies
(Micron rev. E kits can use the same tRDWR math and -2 on it without breaking stability, it's just something only they can do)
B-dies without affecting any other timing, can go tRC down to -2 
Lower than that might need tCWL +1 = +2 as even number, to show positive benefits
Although the amount of positive benefits on this kind of shifting, i haven't tested ~yet~
It's an option to consider tho 

Overall clean tRAS -> tRC transition remains key, and won't be affected by Dual Rank or who knows 64gb dimms
But going lower than tRC-2 i can't see as viable option so far. 
If tRC-1 on DR works i haven't tested so far, but pretty much only Single Rank can abuse this tweak 
Same for tRDWR=((tRCD_RD/2) - 1) with added tWRRD delay, only SR exclusive



Ortus said:


> Turns out being unable to lower tRCDRD further might be entirely temperature related, all the other timings are fine up to 50c at least, but tRCDRD starts throwing errors at 30.5c, spewing them at 36, and crashing at 41.
> Probably not cracking that when my room hits 25c ambient most of the year.


Try it out, 
Capacitor discharge is Temp related, but i haven't seen anyone go under tRC*6 , *5 should be possible but i haven't gotten my hands on anything to work personally on recently
Voltage should only increase heat - it will increase the amount of charge and up to your timings, more will be left
But then higher heat has a negative effect and they will lose even faster the charge
tRP is there to adjust and help on this "issue" 

If your dimms get too hot, increase tRP
If you want less vDIMM, increase tRP
if you want to meet a tRFC target, decrease tRP and increase voltage
Only increasing voltage won't really grant you a good tRFC ~ as neverless what fixed refresh-cycle-delay you pick, tRP same as tRAS has to pass before anything can happen. The same goes for tRC, nothing will happen till that one elapses and tRAS being the only one that is autocorrected if it's ACTIVE timing ends up being too short.

EDIT:
_Little _ history lesson/notes 
After ROWs are ACTIVE'ated = tRAS
and are read, they lose charge ~ more like the charge is transferred to the sensing amplifiers
Soo they need to be (p)recharged again.
DDR4 can write data to this cells while they recharge, but every readout is a full loss of charge
tRC = the Row Cycle is scale-able and the end point of this one operation.

You can cheat and just increase it, where nothing will happen till this cycle ends
At the benefits of stability on lower voltage. 
Although again, this is cheating and should only be considered on awkward temperatures like XOC or your typical SpaceHeater system 
Intel altogether skips this value, as only a clean transition matters
Although intel users do often push tRAS higher and so tRP also higher to cover it
A technique is also to increase tREFI to the maximum and just let the memory time break after the 9th tRFC happens

This way the only thing the OCers could learn is, that tRFC is depending on charge
(tRP, so tRAS - well you get the point)
And the early answers that tRC for tRFC didn't matter and only depends on voltage, where kinda correct but also didn't show the whole picture

There is far back then , but let me reupload it again:
A wonderful 150+ page PDF of Abusing DDR-Heterogeneity 
Mr. Donghyuk focuses a lot on the tCL+tWR+tBL topic -> especially for tRAS
1usmus learned from this too but he is an engineer by himself, soo it likely wasn't the only source of information
Cycle-Stacking , or rather "discharge-stacking" is the method that allows such ruleset breaking "rules" to work 
This includes tRC-2 or factoring in tSTAG 
I hope we get to control tREFI and tAL (time added latency) helping us to calculate stuff tighter and with lower tWR limits


----------



## rares495

Veii said:


> If you've gone down to tRCD 14 instead of 15 - tRDWR 7 would be better than 8
> tRCD RD / 2 = tRDWR has to work on 16Gb dimms, but it won't if you waste some latency somewhere
> 
> Using low tCWL was on the intel side of things a tweak, as they have tRAS, tRFC, tREFI as scales and a lot of split optimisations on the
> tRDWR -> tRRDR
> tWRRD -> tRRDD
> AMD -> Intel
> Side of things
> tRC i haven't seen anywhere changable and the "best way" to get lower performance was to drop tCWL
> But tCWL <-> tRDWR go hand in hand
> If you lower one, you have to up the other one by the same amount
> 
> on AMD , tRDWR i found to be next to SCL the biggest perf increase factor
> If tRDWR = tRCD RD / 2 won't work
> just add a bit of latency on tWRRD, then it will work
> Usually it shouldn't need it, only when you go -1 of half tRCD
> ((tRCD RD/2)-1) on Single Rank dimms works even when you lower tRC -2


I could never post with tRDWR 7 even with tRCDRD 14. I might try again but I don't think it will work.


----------



## Veii

rares495 said:


> I could never post with tRDWR 7 even with tRCDRD 14. I might try again but I don't think it will work.


At least 7/4 should work 
if not even 7/2 SCL2 - else 7/4 SCL 3, 7/3 SCL >4 
Ruleset is, that it should come close to tRCD but not exceed it


----------



## Ortus

Veii said:


> Try it out,
> Capacitor discharge is Temp related, but i haven't seen anyone go under tRC*6 , *5 should be possible but i haven't gotten my hands on anything to work personally on recently
> Voltage should only increase heat - it will increase the amount of charge and up to your timings, more will be left
> But then higher heat has a negative effect and they will lose even faster the charge
> tRP is there to adjust and help on this "issue"
> 
> If your dimms get too hot, increase tRP
> If you want less vDIMM, increase tRP
> if you want to meet a tRFC target, decrease tRP and increase voltage
> Only increasing voltage won't really grant you a good tRFC ~ as neverless what fixed refresh-cycle-delay you pick, tRP same as tRAS has to pass before anything can happen. The same goes for tRC, nothing will happen till that one elapses and tRAS being the only one that is autocorrected if it's ACTIVE timing ends up being too short.


Tested some more adventures in flat 14s, increasing tRFC and lowering vdimm by 0.2v with the windows open so hottest dimm is 21c at idle is stable until they heat up to 29.5c.

21>29.5 with worse tRFC is only enough breathing room to run Karhu for 10 minutes, but in four test>error>cooling cycles the errors only occurred above 29.5c with the longest at 30.5c.

This is the coldest night forecast for the few weeks though so that's about all I can check.


----------



## nick name

Ortus said:


> Tested some more adventures in flat 14s, increasing tRFC and lowering vdimm by 0.2v with the windows open so hottest dimm is 21c at idle is stable until they heat up to 29.5c.
> 
> 21>29.5 with worse tRFC is only enough breathing room to run Karhu for 10 minutes, but in four test>error>cooling cycles the errors only occurred above 29.5c with the longest at 30.5c.
> 
> This is the coldest night forecast for the few weeks though so that's about all I can check.


I'm guessing it's the GDM off. Do you normally run GDM off?


----------



## nick name

Veii said:


> At least 7/4 should work
> if not even 7/2 SCL2 - else 7/4 SCL 3, 7/3 SCL >4
> Ruleset is, that it should come close to tRCD but not exceed it


I can't POST 7/4 either.


----------



## Gadfly

Ortus said:


> Tested some more adventures in flat 14s, increasing tRFC and lowering vdimm by 0.2v with the windows open so hottest dimm is 21c at idle is stable until they heat up to 29.5c.
> 
> 21>29.5 with worse tRFC is only enough breathing room to run Karhu for 10 minutes, but in four test>error>cooling cycles the errors only occurred above 29.5c with the longest at 30.5c.
> 
> This is the coldest night forecast for the few weeks though so that's about all I can check.


Nice OC, truly, but this really isn't the thread for this type of thing. 

This is the Ryzen 24/7 stable Memory OC thread. Submissions should include screen shots of your memory settings and valid testing results as described in the first post; and should be, exactly as the subject implies, 24/7 stable. Not stable for 10 test loops until your memory gets to only 30.5'C and requires open windows and only on the coldest night in weeks.


----------



## nick name

Gadfly said:


> Nice OC, truly, but this really isn't the thread for this type of thing.
> 
> This is the Ryzen 24/7 stable Memory OC thread. Submissions should include screen shots of your memory settings and valid testing results as described in the first post; and should be, exactly as the subject implies, 24/7 stable. Not stable for 10 test loops until your memory gets to only 30.5'C and requires open windows and only on the coldest night in weeks.


I can see where you're coming from, but I think people making attempts at 24/7 stability and showing what isn't working is helpful too.


----------



## rares495

Gadfly said:


> Nice OC, truly, but this really isn't the thread for this type of thing.
> 
> This is the Ryzen 24/7 stable Memory OC thread. Submissions should include screen shots of your memory settings and valid testing results as described in the first post; and should be, exactly as the subject implies, 24/7 stable. Not stable for 10 test loops until your memory gets to only 30.5'C and requires open windows and only on the coldest night in weeks.


This and the DRAM Calculator thread are not limited to their respective topics anymore. It's all about memory OC anyway. It would be very boring to see people just post results in here.


----------



## mongoled

So experimenting with values I have never tried before.

I got two completed runs (1st run passed, reboot, 2nd run passed) with the same settings as in screen shot below, but with tRP at 14.

But did not really see any performance benefits from the settings in my sig.

Dropping tRP to 12 clearly brought better performance, though I now have two new errrors.

Error 14,which Veii has explained as 



veii said:


> - it can error after the 2nd or 3rd pass if something is off my some ns and just "got lost"
> - i often hit it after 31min when the test takes 32min - can be heat related but then it's main reason is micro timeout x_x


But ive never come across an explanation for error 9.

Id love to get this stable, looks to be alot closer to stabilty than trying to run tRCDRD at 14!

Would increaing ClkDrvStrength help with these types of error as i have it set to 20 ohms .....


----------



## mongoled

Gadfly said:


> Nice OC, truly, but this really isn't the thread for this type of thing.
> 
> This is the Ryzen 24/7 stable Memory OC thread. Submissions should include screen shots of your memory settings and valid testing results as described in the first post; and should be, exactly as the subject implies, 24/7 stable. Not stable for 10 test loops until your memory gets to only 30.5'C and requires open windows and only on the coldest night in weeks.


This is 100% correct, though its been quite a long time that this thread had deviated from its original intent.

I think one of the reason is because there are not so many people posting at forums such as this one anymore, well at least compared to what it was like in its "heyday" so because of this the posting regards anything to do with RAM overclocking is stuck mainly in two threads .......


----------



## Gadfly

nick name said:


> I can see where you're coming from, but I think people making attempts at 24/7 stability and showing what isn't working is helpful too.


do it in another thread. This is supposed to help people find and compare stable results.


----------



## nick name

Gadfly said:


> do it in another thread. This is supposed to help people find and compare stable results.


If you want another thread then start another thread. Being able to compare failures and successes seems useful to me. 

I'm not sure exactly when people stopped following the guidelines that Silent Scone set, but it was a good while ago.


----------



## Eder

chitos123 said:


> https://docs.google.com/spreadsheet...V3BjdL-dcfJJeyhdSAoJmuzJE/edit#gid=1439155382
> 
> 
> Please test my calculator
> And tell me, any mistake or wrong calculation


Ooh new spreadsheets tot play with. Very Nice Veii. Bought a 32gb dual ranked kit but one dimm was faulty. Will test your calc when the replacement kit arrives!


----------



## Veii

Eder said:


> Ooh new spreadsheets tot play with. Very Nice Veii. Bought a 32gb dual ranked kit but one dimm was faulty. Will test your calc when the replacement kit arrives!


Wrong person, he/she did it all by himself 
Unless you mean this little cutout with the boxes on the quote ?
But this thing exists far before tRFC mini was published - it was taken from this bigger project, to help people as it was needed 
It's rough and not useful the docs screenshot

@chitos123 did good work ~ it just looks a bit complex to use, but this comes by time 
Oh you did also a wonderful job this page http://cooln.kr/bbs/37/224005 :thumb:
If you ever publish it on twitter, please let me retweet it 

@Eder , this cutout what you see is being on hold since long time
Too long tbh, but priority had a mobile app before this huge thing is published
It's goal is actual simulation prediction - prediction how autocorrect will work and simulate "timing efficiency" between clocks
So far it's not sharable, it's not better than chitos - chitos did very good and not all rulesets exist
SD, DD needs a strickt research and SCL needs a very strict research , same as tWTR_ range 
~ all up to PCB 

The rest pretty much is solid and calculable
tRFC part needs further research to drop lower than *6 and calculate tSTAG without user readout 
tREFI calculation misses and we AMD users need access to that value - without auto calculation


mongoled said:


> So experimenting with values I have never tried before.
> I got two completed runs (1st run passed, reboot, 2nd run passed) with the same settings as in screen shot below, but with tRP at 14.
> 
> But did not really see any performance benefits from the settings in my sig.
> Dropping tRP to 12 clearly brought better performance, though I now have two new errrors.
> 
> Error 14,which Veii has explained as
> But ive never come across an explanation for error 9.
> 
> Id love to get this stable, looks to be alot closer to stabilty than trying to run tRCDRD at 14!
> Would increaing ClkDrvStrength help with these types of error as i have it set to 20 ohms .....


Error 14 we know is MirrorMove 0mb, a timeout issue 
Error 9 burst test 4mb is a voltage stability issue 
If you've lowered tRP , increase vDimm a tiny bit
If you've increased tRP to longer delay, decrease vDIMM +0.01 , one tiny step 

14 remains a timeout issue, but the pattern shows
First it chokes, then it can't (p)recharge in time the cells 
soo first fix your timeout issue, later maybe the voltage will be fine for it
But by time heat will increase, cells will faster discharge and you'll get the same error 9 again 
First fix Error 14

Try if tRTP 8 fixes it
If not, use tRRD_L 5
if you still choke at the same time, push tWTR_L to 10 
And if you still have the issues,well increase vDIMM as tRP is too low at 12 
tRP 12 or tRP 14 shouldn't matter, tRC can go down to -2 on Single rank without feeling negative effects 
Only tRAS has to be perfectly accurate 
tRP scales by temperature and tRCD, but voltage dominates ~ it's all just discharge prediction at this point

... i actually see an issue
tCL 14 + tWR 10 + tBL 2 = 26 
28 might be too long for tRAS, 
What will happen if you just change tRP to 14 and tRAS to 26 ~ without any other changes ?

EDIT:
@chitos123


> tRFC 는 고정값이 아닙니다, 클린한 리프레시 사이클을 나타내는데 주로 사용되며
> 충전이 끝나기 전, 시간에 맟춰 행을 활성화 시킵니다
> 
> 하지만 메모리는 타임 브레이크(Time-Break) 능력이 있으며, 또한 모든 규칙을 무시할 수 있습니다
> 
> tRFC 는 이중 하나이며,시간에 맞춰 수동으로 작동되기도 하고, 자동으로 우회하여 필요할때 작동되기도 합니다
> 
> 낮은 tRFC 값, 혹은 제가말하는 "동기화 되지 않은 값은" 성능을 떨어 뜨릴수 있습니다
> 높은값도 동일합니다(너무 높을수 있습니다)


Auto-Translated:


Spoiler






> tRFC is not a fixed value, it is mainly used to represent a clean refresh cycle.
> Before charging is over, it activates the row at the time.
> 
> However, memory has a time-break capability and can also ignore all rules.
> 
> tRFC is one of them, it can be operated manually in time, or it can be automatically bypassed and operated when needed.
> 
> Low tRFC values, or "unsynchronized values" I'm talking about, can degrade performance
> High values are the same (may be too high)





This likely was the talk with Gadfly and me
There is a missunderstanding coming from Intel way of OC and AMD way
Intel users have no tRC and use tRAS plus tRFC + tREFI ~ missunderstandings happen

tRFC is a fixed delay value, 
tRC is also a fixed delay but a variable=scale-able (only tRAS is not scale-able, tRP adapts)
tRFC is a repeating refresh cycle a whole cycle inside tREFI range

It will happen and it will stay active till it happens, till it expires
If it happens not fast enough "too late" , it will be postponed up to 9* inside the whole tREFI range
tREFI is calculated by tRFC1-2-4 all 3 of them

Accuracy of tRFC remains important when you want a clean transition
if tRFC is too low, it will try to postpone, timebreak and repeat it self 
if tRFC is too high , it will wait till it elapses, stop everything else and wait for it to finish

tREFI range on AMD depends if memory clear is enabled or disabled
Recommended is Disabled, soo whole tREFI range will pass and no early random refresh happens
Memory will break tRFC rule if tRFC 2 or 4 is awkward, but it's a fixed delay and it will stay on it till this delay elapses
Same characteristics for tRC 

tRC has to finish before anything else can be done
You can abuse this a bit and lower it - the same way 1usmus knows a method to lower tRFC even further by using tSTAG
But every timing we can change are fixed delays
The rest are identical amount of realtime autocorrecting timings which adapt by the accuracy of the fixed delays
tMRD state and tMOD are one of them - tRFC whole set a -1/+1 rounding will mess up autocorrecting values, readable via old RTC and current 1.0.0.8 ZenTimings

In the future i hope that we can readout all autocorrecting timings including tAL on each primary
But this is a project in the future and an issue which needs to be resolved before Renoir fully launches
Let's say before consumer 4xxx launches with variable MCLK, FCLK, UCLK

EDIT 2:
tRFC will only be postponed if tRAS happened, Data was transferred to sensing amp, tRP tried to (p)recharge, tRC killed this cycle too early
tRFC will try to trigger with the same delay of tRAS+tRP multiple times , but after a point discharge happens too fast and it can't keep up. Then tRFC is postponed to another time after tRC ends again(the next cycle)
Little cheat-sheet


Spoiler














EDIT 3:
4.) in the writeup is very valuable, i understand my mistake and will need to retest and readjust the ruleset of tRAS & tRC
Haven't seen negative effects by going that high , but 14-14-14 making min tRAS=16 not 28 is a too big difference to ignore
Thank you again for collecting both sides of the learning experience. You never can learn enough. 1usmus explanation makes perfect sense 


> tRAS, Min = tRCD + tCL + (tBL-(tCL-1))-1
> = tRCD+tBL = tRCD +2


----------



## mongoled

veii said:


> Error 14 we know is MirrorMove 0mb, a timeout issue
> Error 9 burst test 4mb is a voltage stability issue
> If you've lowered tRP , increase vDimm a tiny bit
> If you've increased tRP to longer delay, decrease vDIMM +0.01 , one tiny step
> 
> 14 remains a timeout issue, but the pattern shows
> First it chokes, then it can't (p)recharge in time the cells
> soo first fix your timeout issue, later maybe the voltage will be fine for it
> But by time heat will increase, cells will faster discharge and you'll get the same error 9 again
> First fix Error 14
> 
> Try if tRTP 8 fixes it
> If not, use tRRD_L 5
> if you still choke at the same time, push tWTR_L to 10
> And if you still have the issues,well increase vDIMM as tRP is too low at 12
> tRP 12 or tRP 14 shouldn't matter, tRC can go down to -2 on Single rank without feeling negative effects
> Only tRAS has to be perfectly accurate
> tRP scales by temperature and tRCD, but voltage dominates ~ it's all just discharge prediction at this point
> 
> ... i actually see an issue
> tCL 14 + tWR 10 + tBL 2 = 26
> 28 might be too long for tRAS,
> What will happen if you just change tRP to 14 and tRAS to 26 ~ without any other changes ?


Thank you for the explanation, I will try some of those things out.

FYI,

I simply increased ClkDrvStrength from 20 ohms to 24 ohms and ran TM5, this time I had no error 9 or 14, but only one error that was 11.

Am going to reboot and re-run TM5 to see if its repeatable.

** EDIT **
2nd run had 5 errors in test 1

Going to re-run the settings that got me 9 & 14 errors to see if its reproducable, need to confirm that increasing ClkDrvStength is shifting where the errors are produced ...

** EDIT2 **
Ughhh, scratch the repeatable testing, once I changed some values in RM, max volts RM applies to vDIMM is 1.5v, I need 1.52v and since I am running these tests remotely, I will need to continue this when i am at the office

:\

This seems similar to what rares was seeing in April when he was playing with getting tRP stable at 12....


----------



## rares495

mongoled said:


> Thank you for the explanation, I will try some of those things out.
> 
> FYI,
> 
> I simply increased ClkDrvStrength from 20 ohms to 24 ohms and ran TM5, this time I had no error 9 or 14, but only one error that was 11.
> 
> Am going to reboot and re-run TM5 to see if its repeatable.
> 
> This seems similar to what rares was seeing in April when he was playing with getting tRP stable at 12....


Never seen errors 9 & 14. Never seen anyone else get them. Could this be related to your high BCLK? By the way, why are you not back to 100? Does it allow for higher CPU OC or something?


----------



## mongoled

rares495 said:


> Never seen errors 9 & 14. Never seen anyone else get them. Could this be related to your high BCLK? By the way, why are you not back to 100? Does it allow for higher CPU OC or something?


Yes, you did not have 9 & 14, but you were alternating between other batches of error codes

https://www.overclock.net/forum/10-...memory-stability-thread-352.html#post28408882 (only reference I found veii talk about error 9)



Yeah, nice boost speeds that are "automated" dependant on load,

Example TM5 runs 4500+ all core.

Prime95 runs 4380+ all core

Single core boosts 4600+

Ive done loads of testing when I was trying to work out those weird issues I was having 10 days ago. 

BCLK or high boost clocks was never the culprit, was just for some reason I needed slighly more vDIMM as in compared to what i previously stable ....


----------



## rares495

mongoled said:


> Yes, you did not have 9 & 14, but you were alternating between other batches of error codes
> 
> https://www.overclock.net/forum/10-...memory-stability-thread-352.html#post28408882 (only reference I found veii talk about error 9)
> 
> 
> 
> Yeah, nice boost speeds that are "automated" dependant on load,
> 
> Example TM5 runs 4500+ all core.
> 
> Prime95 runs 4380+ all core
> 
> Single core boosts 4600+
> 
> Ive done loads of testing when I was trying to work out those weird issues I was having 10 days ago.
> 
> BCLK or high boost clocks was never the culprit, was just for some reason I needed slighly more vDIMM as in compared to what i previously stable ....


So are you at 1.5V VDIMM yet?


----------



## mongoled

1.52v in BIOS, reads 1.536v in HWInfo64



** EDIT **
OK, looks like ive worked out the reason the required vDIMM changes, but do not know why it happens.

So I just finished a TM5 25 cycles with Veii suggestion of using tRAS @26.

It completed with no errors, however, I was looking at the load vDIMM and instead of being 1.536v it was @1.552v occasionaly dropping to 1.536v.

So it seems the vDIMM voltage is not a constant on each different reboot.

At least according to what HWInfo64 is relaying.

Ive now set in the BIOS 1.51v and now HWInfo64 is showing a steady 1.536v under load, hopefully this will pass the 25 cycle test and than will have to reboot and run it again just to make sure ...


----------



## nick name

mongoled said:


> 1.52v in BIOS, reads 1.536v in HWInfo64
> 
> 
> 
> ** EDIT **
> OK, looks like ive worked out the reason the required vDIMM changes, but do not know why it happens.
> 
> So I just finished a TM5 25 cycles with Veii suggestion of using tRAS @26.
> 
> It completed with no errors, however, I was looking at the load vDIMM and instead of being 1.536v it was @1.552v occasionaly dropping to 1.536v.
> 
> So it seems the vDIMM voltage is not a constant on each different reboot.
> 
> At least according to what HWInfo64 is relaying.
> 
> Ive now set in the BIOS 1.51v and now HWInfo64 is showing a steady 1.536v under load, hopefully this will pass the 25 cycle test and than will have to reboot and run it again just to make sure ...


I guess it's board (and BIOS) dependent as I see a droop in HWiNFO. Setting 1.5V droops down to ~1.48V and does not go higher than what is set. This isn't a behavior I remember from the period I was using my 2700X on the board, however.


----------



## KedarWolf

Zen Timings 1.0.8 released.

https://github.com/irusanov/ZenTimings/releases


----------



## KedarWolf

All credit goes to @GeneO who wrote this script. Rep him, not me, there is no way I could write this kind of thing myself, just good enough at math logic to edit it for our needs.

Here are AutoHotKey scripts for a 3950x, 3900x and 3800x (32 threads, 24 threads and 16 threads).

What makes it amazing is it allocates each instance of HCI MemTest Pro 7 to a single separate core on your CPU, so like core 1, one instance HCI on it, core 2, a second separate instance of HCI on it etc.

If you check on Windows task manager and click one instance and 'Go to details', then 'Set Affinity' you see each one is running on its own separate thread, that absolute best way to run HCI MemTest Pro!

It also spaces each instance evenly so you can see the error messages (or lack there-of) and progress.

You need to install the included AutoHotKey to run the raw AHK file or compile it to a .exe with AutoHotKey. It works using the HCI MemTest Pro 7 'MTPclassic.exe'. 

If you bought MemTest Pro less than a year ago you can email them for a free upgrade. If not, it only costs $5 USD.

You can adjust


Code:


size=800

 which is the memory allocated in each instance of HCI to make sure you are using 90% of your RAM in Task Manager. You need at least 90% for HCI verification in this thread.

I included the .zip with the files.


----------



## KedarWolf

KedarWolf - [email protected]/4.400/4.350/4.325GHz - 3800Mhz-C15-16-13-28 2T - 1.44v - SOC 1.15v---BIOS 7C34v193 - HCI 600% - F4-3600C16-16GTZN

Let it run all day, back to using my PC.


----------



## Veii

KedarWolf said:


> KedarWolf - [email protected]/4.400/4.350/4.325GHz - 3800Mhz-C15-16-13-28 2T - 1.44v - SOC 1.15v---BIOS 7C34v193 - HCI 600% - F4-3600C16-16GTZN
> 
> Let it run all day, back to using my PC.


Good result :thumb:
Do you want to be a testing rabbit for some new set ? 
Would love to check if i did understand 1usmus's tRAS explanation and if the awkward set will outperform this one :thinking:
But it might result in a CMOS reset ~ soo i'll only beg you, if you really have the time


----------



## KedarWolf

Veii said:


> Good result :thumb:
> Do you want to be a testing rabbit for some new set ?
> Would love to check if i did understand 1usmus's tRAS explanation and if the awkward set will outperform this one :thinking:
> But it might result in a CMOS reset ~ soo i'll only beg you, if you really have the time


Not sure what you're asking. Can you explain?


----------



## Veii

KedarWolf said:


> Not sure what you're asking. Can you explain?


Do you want to test one strange timing preset and compare it to this one.
I would like to try a new technique for calculation. Following something new learned by 1usmus
If you have the time to test, but it might result in a CMOS reset.


----------



## KedarWolf

Veii said:


> Do you want to test one strange timing preset and compare it to this one.
> I would like to try a new technique for calculation. Following something new learned by 1usmus
> If you have the time to test, but it might result in a CMOS reset.


Sure.


----------



## Veii

KedarWolf said:


> Sure.


Very awkward








Can you use TM5 at first, to know where it errors ~ if it can even post


----------



## KedarWolf

Veii said:


> Very awkward
> 
> 
> 
> 
> 
> 
> 
> 
> Can you use TM5 at first, to know where it errors ~ if it can even post


Might be a limitation of my motherboard but tRAS won't go below 21. 

It posts at that though. And AIDA bandwidth a bit better and latency when down from 62.4 to 62.1.

Edit: I put this, bandwidth increases all around, same 62.1 latency, and running TM5 now while I sleep.


----------



## Veii

KedarWolf said:


> Might be a limitation of my motherboard but tRAS won't go below 21.
> 
> It posts at that though. And AIDA bandwidth a bit better and latency when down from 62.4 to 62.1.


Oke give me a bit, the difference might be just because of lower tRFC. it should be a far bigger difference.
Hmm load your old profile and save it on an USB.
You can try to skip the limits if it let's you , from AMD CBS -> UMC -> Memory Controller -> DRAM configuration -> DRAM Timings
I think it was there, to manually put in the timings via HEX , just once you access this menu you have to work in HEX until you cmos reset
Soo making an USB profile is recommended 

I'll try to make something with bigger timings that follows the same ruleset, give me a tiny bit of time
EDIT:
15 = 0xF , or just F
16 = 0x10 or 10


----------



## Veii

KedarWolf said:


> Edit: I put this, bandwidth increases all around, same 62.1 latency, and running TM5 now while I sleep.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Veii said:
> 
> 
> 
> I'll try to make something with bigger timings that follows the same ruleset, give me a tiny bit of time
Click to expand...

What about:









Alright, sleep well


----------



## mongoled

Another one for reference



Thanks Veii, dropping tRAS to 26 is all what was required.

Will lower tRRD_S to 3 and shoot for tFAW @12 to see if there are any performance benefits


----------



## Veii

mongoled said:


> Another one for reference
> 
> 
> 
> Thanks Veii, dropping tRAS to 26 is all what was required.
> 
> Will lower tRRD_S to 3 and shoot for tFAW @12 to see if there are any performance benefits


You can shoot for 38 tRC to abuse the old -2 strategy 
Changing tRRD_ can cause a lot of issues 
tRRD_S to 3 shouldn't be allowed on current bioses :thinking:

Wish i would understand the tRAS formula better but it makes no sense so far, as autocorrection will trigger in 
Old method at least works ~ even tho it's mentioned as wrong 
@infraredbg , ZenTimings
if you can, please move tRFC ns before tRFC and write it fully out
Real tRFCns on this picture is "126.3157895" @ 14400 tREFI 
Even if it would only use 3533.33333334MT/s the real tRFC is "135.849056603xxxx"ns also @ 14400 tREFI
Can't get the last 4 digits correct as it's neither .3333333 nor .33333334 
Anyways, please at least for accuracy sake skip rounding (6-7 decimals should be accurate enough)
or if possible read out MCLK factoring BLCK then *2 for correct MT/s

Overall tREFi looks to be wrong - else if it's correct the board messes something up with fixed tRFC, tRFC 2 , tRFC 4 :thinking:
EDIT:
Coming closer, real tRFC for 3534MT/s is around 
135,8490566037735*X* ns
but here i go back to overflow 








This is why we have rounding issues, and why rounding stacks


----------



## rares495

Veii said:


> You can shoot for 38 tRC to abuse the old -2 strategy
> Changing tRRD_ can cause a lot of issues
> tRRD_S to 3 shouldn't be allowed on current bioses :thinking:


Already tried. Can't set lower RRDS than 4. Not even in CBS.


----------



## mongoled

Veii said:


> You can shoot for 38 tRC to abuse the old -2 strategy
> Changing tRRD_ can cause a lot of issues
> tRRD_S to 3 shouldn't be allowed on current bioses :thinking:
> 
> Wish i would understand the tRAS formula better but it makes no sense so far, as autocorrection will trigger in
> Old method at least works ~ even tho it's mentioned as wrong


OK will try tRC to 38

Oh never thought tRRD_S could be "naughty"



I thought I would try it as the XMP for these Viper 4400 is tRRDS 3 and tFAW @12



rares495 said:


> Already tried. Can't set lower RRDS than 4. Not even in CBS.


Awwww,

will have a try soon, want to let Y-Cruncher get to 4 hours


----------



## Yuke

Veii said:


> I would need to look closer, out of this range which one fits well for 3800MT/s
> 
> 
> 
> 
> 
> 
> 
> 
> But for example on 3733.3xxx4MT/s ~ the one that works well is 336, lower is always a bit tricky
> 
> The values you get suggested are correct, but in order to perform better - the rest of the set needs to be also correct
> Pushing tRC up will add wasted latency, and if tRFC delay is wrong or a tiny bit off, it will be postponed to another whole refresh cycle
> In tREFI main time, after all 9* this tRFC can happen, and be postponed before it closes
> Logically on AMD tREFI is auto calculated
> 
> You can lie and make your live easier by just pushing tRC up, and keeping tRAS correct
> But if tRAS is too low, it will be autocorrected up, if tRC is too low usually no autocorrect will happen and it will spill out errors
> (this means tho, using correct tRFC to begin with for this low tRC)
> If you use a "wrong" tRFC and tRC is too low, what only will happen is
> - tRFC will be postponed to the next cycle
> - memory will finish tRC cycle, look for refresh time, see tRFC got postponed and just wait till the next big cycle happens
> "next Cycle" tho as tRFC mostly is 6 cycles if calculated low enough, the delay and performance degrade by this "autocorrection" will be noticable


Thanks for the input.

Those were the timings before i changed them according to the excel sheet:










I passed 20 cycles TM5 and half a day of Karhu...also had 0.3ms faster latency. Any reason to not use them (besides having to push voltage from 1.38V to 1.44V just for better tRFC)?


----------



## Veii

Yuke said:


> Thanks for the input.
> Those were the timings before i changed them according to the excel sheet:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I passed 20 cycles TM5 and half a day of Karhu...also had 0.3ms faster latency. Any reason to not use them (besides having to push voltage from 1.38V to 1.44V just for better tRFC)?


No reason to not use them
Steps for tRC 48 @ 3800MT/s are 
*384*,360,*336*,312,*288*,264,*240* 
all of them will work, just the bold marked ones are whole cycles, the other are half 
If you want to use more VDIMM, you can lower tRP , lower tWR, get lower tRAS and lower tRC = lower tRFC 

You can also only go with odd tRFC but it can happen that they sometimes up to test or scenario get suspended = skipped 
Then you have more delay, well all depends up to testing. Lower tRFC often is faster unless it's broken, then it will be suspended and is slower
tRFC
264-196-121 works for you, soo why not
240-178-110 could likely also work but that's *5 , *5 is too unstable so far you can try it but idk if it would keep up stability
Might need tWR 10, which is hard to get on 32GB dimms. And afterwards a tRAS change (-2 tRAS, then +2 tRP, to keep same tRC)


----------



## mongoled

@Veii

If I lower tRC to 38 do I have to adjust tRFC also ? 

Or is the "cheat" not effecting tRFC ?



Oh and no tRRD_S lower than 4 on this MSI either ...


----------



## Veii

mongoled said:


> @Veii
> 
> If I lower tRC to 38 do I have to adjust tRFC also ?
> 
> Or is the "cheat" not effecting tRFC ?
> 
> 
> 
> Oh and no tRRD_S lower than 4 on this MSI either ...


Oh you have to adjust tRFC  
247-184-113 
Try if tWR won't cause you issues

else 266-198-122 should work too, only tRTP & tWR are strange for this one


----------



## chitos123

@*Veii*
Thank you for correcting the wrong calculation




Spoiler














Should I remove "If tCL ODD and tCWL=tCL+1 => tRD_WR -1"?

I don't understand why should i add that "tRTP value select box"
Could you please explain why not to just use
tRTP(manual)*2 = tWR
+++
[*EDIT1*] FIX "IF tCL ODD => tWR show 0 too
+++


Add Test4 for tRCD+tBL =tRAS



Could you please explain about DR, SR calculation differences and,
about SD(DD), tRRD, tWTR, SCL IC dependencies (or DR,SR), Low tRCD WR rule for the calculation too
Because i'm not sure of the difference in the "Ryzen-DRAM-Calculator-1.7.3" value




About that korean site, i need time to translate Accurately that you said above
Feedback on my translated text is very honorable
Thank you very much



This is new layout
(I merged two sheets of different functions.)



Spoiler














https://docs.google.com/spreadsheet...V3BjdL-dcfJJeyhdSAoJmuzJE/edit#gid=1083534502


----------



## nick name

I went ahead an acted on a suggestion from @rares495. Couldn't say if the values actually improve performance beyond Copy in Aida. Everything else seems about the same when benching it. 

Tests stable in Karhu for 30 minutes. Not gonna test longer without knowing if these are the actual values or corrected by the controller.


----------



## treestar

Can a temp difference between 4 sticks affect stability without crossing 45C? It can go up to 3 degrees.


----------



## nick name

treestar said:


> Can a temp difference between 4 sticks affect stability without crossing 45C? It can go up to 3 degrees.


I'm not sure if it's the difference that causes errors or just one particular DIMM that responds differently to temp. And if that's the case then move that DIMM to one of the outer slots for more air flow.


----------



## rastaviper

Veii said:


> I can't fully yet
> They are added transfer delays, while running 1-1-1-1-1-1 works on unstable kits but results in at least 8-10% perf drop
> I follow 1usmus's research here, pretty sure dimm amount does define the values and likely also PCB revision ~ as they are just cutoff delays
> tRAS i had as 27 in the picture because tWR was 10
> What you see in black or whatever colour fits for the time, everything that is applied needs a change at the same time
> If one thing is off, the set might break
> If nothing was written, just continue to use what you have
> tRAS 29 was for your set, tRAs 27 was if you follow the remain timings which do include tWR at 10
> As we know
> tCL+tWR+tBL = tRAS


Hey,
which one is the tBL? And since it's working as it is, should I mess with the tRAS?
Also which are the SD DD's that you have proposed to push down to 5-5-7-7?


----------



## nick name

rastaviper said:


> Hey,
> which one is the tBL? And since it's working as it is, should I mess with the tRAS?
> Also which are the SD DD's that you have proposed to push down to 5-5-7-7?


From 1usmus' techpowerup piece: "tBL for DDR4 = 4 or 2"


----------



## mongoled

Not quite there,

TM5 no problem, 1st run pass, reboot, 2nd run pass

Y-cruncher failed on FFT after about 1hr 20mins ...


----------



## rares495

mongoled said:


> Not quite there,
> 
> TM5 no problem, 1st run pass, reboot, 2nd run pass
> 
> Y-cruncher failed on FFT after about 1hr 20mins ...


Probably due to tRAS and tRC. I had issues getting them lower than 28-40.


----------



## nick name

mongoled said:


> Not quite there,
> 
> TM5 no problem, 1st run pass, reboot, 2nd run pass
> 
> Y-cruncher failed on FFT after about 1hr 20mins ...


Why don't you enable GDM and run at 3800MHz?

Edit:
Saw your signature. Are you just playing around with different speeds and timings?


----------



## mongoled

rares495 said:


> Probably due to tRAS and tRC. I had issues getting them lower than 28-40.


May take a look to see if I can tweak something to get y-cruncher to pass FFTs, whats in my sig is probably as tight as im going to get for 24/7 settings

vDDP is at 0.855v so I may play with increasing/decreasing that.



nick name said:


> Why don't you enable GDM and run at 3800MHz?
> 
> Edit:
> Saw your signature. Are you just playing around with different speeds and timings?


Yeah, just eeeking out as much as I can out of them, its a hobby and as business is pretty much non existant, I end up procrastinating on memory tweaking


----------



## 2600ryzen

mongoled said:


> Not quite there,
> 
> TM5 no problem, 1st run pass, reboot, 2nd run pass
> 
> Y-cruncher failed on FFT after about 1hr 20mins ...



+0.01v on vcore?


----------



## nick name

Looking at the Samsung DDR4 Device Operations Paper -- there is mention of timings that need to be even when using GDM. It doesn't appear to list tRCDWR/tRCDRD.


From the paper:
For the operation of geardown mode in 1/4 rate, the following MR settings should be applied.
CAS Latency (MR0 A[6:4,2]) : Even number of clocks
Write Recovery and Read to Precharge (MR0 A[11:9]) : Even number of clocks
Additive Latency (MR1 A[4:3]) : 0, CL -2
CAS Write Latency (MR2 A[5:3]) : Even number of clocks
CS to Command/Address Latency Mode (MR4 A[8:6]) : Even number of clocks
CA Parity Latency Mode (MR5 A[2:0]) : Even number of clocks

So am I just not seeing it? Because if it indeed can be an odd value then perhaps 14-15-14-14 is actually that and not changed to 14-16-14-14. Or perhaps 14-13-13-13 is not being changed to 14-14-14-13. 

The paper (page 82):
https://www.samsung.com/semiconduct.../11/DDR4_Device_Operations_Rev11_Oct_14-0.pdf


----------



## mongoled

2600ryzen said:


> +0.01v on vcore?


Nah, no more vCore



Im already using EDC @3 with vCore on AUTO, im lettings the PBO algorithm handle vCore.

It passed 4 hours Y-Cruncher when using tRAS @28 and tRC @40, so dropping to 26/38 shouldnt be effected by vCore.

May also play with LLC, but dont want to change too many things as im not wanting to introduce more unknowns


----------



## hazium233

nick name said:


> Looking at the Samsung DDR4 Device Operations Paper -- there is mention of timings that need to be even when using GDM. It doesn't appear to list tRCDWR/tRCDRD.
> 
> 
> From the paper:
> For the operation of geardown mode in 1/4 rate, the following MR settings should be applied.
> CAS Latency (MR0 A[6:4,2]) : Even number of clocks
> Write Recovery and Read to Precharge (MR0 A[11:9]) : Even number of clocks
> Additive Latency (MR1 A[4:3]) : 0, CL -2
> CAS Write Latency (MR2 A[5:3]) : Even number of clocks
> CS to Command/Address Latency Mode (MR4 A[8:6]) : Even number of clocks
> CA Parity Latency Mode (MR5 A[2:0]) : Even number of clocks
> 
> So am I just not seeing it? Because if it indeed can be an odd value then perhaps 14-15-14-14 is actually that and not changed to 14-16-14-14. Or perhaps 14-13-13-13 is not being changed to 14-14-14-13.
> 
> The paper (page 82):
> https://www.samsung.com/semiconduct.../11/DDR4_Device_Operations_Rev11_Oct_14-0.pdf


That also appears in JEDEC 79-4B on pg 81 "Control Gear Down Mode," or in the Micron 8Gbit data sheet pg 104-105 "Gear-Down Mode." I imagine in Hynix too because this is from JEDEC originally.

These timings have to go into mode registers which is why they are explicitly listed. The register for each is listed in your quote "MRx" with the address bits for each. tRTP and tWR share address bits.


----------



## nick name

hazium233 said:


> That also appears in JEDEC 79-4B on pg 81 "Control Gear Down Mode," or in the Micron 8Gbit data sheet pg 104-105 "Gear-Down Mode." I imagine in Hynix too because this is from JEDEC originally.
> 
> These timings have to go into mode registers which is why they are explicitly listed. The register for each is listed in your quote "MRx" with the address bits for each. tRTP and tWR share address bits.


Gotcha, but that doesn't speak to tRCD being an odd value. Do you have any opinion or reference to an answer?


----------



## hazium233

nick name said:


> Gotcha, but that doesn't speak to tRCD being an odd value. Do you have any opinion or reference to an answer?


What is DDR4 Memory Gear-Down Mode

I have meant to test this myself at 2666 where difference in 1t should be the biggest, but haven't gotten to it.

If the command / address are running at 1/2 frequency (aka 1/4 rate), then valid commands should only be able to have even spacing between them relative to the clock.

Otherwise, have not found another web source where this was explicitly stated. Probably because Intel doesn't support the mode.

edit: one place that implies this would be in the Gear Down section of the Micron data sheet, pg 106 "Comparision Between Gear Down Disable and Gear Down Enable," or in JEDEC 79-4B pg 83 with similar diagram.

They show where valid commands can be placed using "DES" (deselect), which happen to always line up with even ticks of the clock with GDM enabled.


----------



## 2600ryzen

hazium233 said:


> What is DDR4 Memory Gear-Down Mode
> 
> I have meant to test this myself at 2666 where difference in 1t should be the biggest, but haven't gotten to it.
> 
> If the command / address are running at 1/2 frequency (aka 1/4 rate), then valid commands should only be able to have even spacing between them relative to the clock.
> 
> Otherwise, have not found another web source where this was explicitly stated. Probably because Intel doesn't support the mode.
> 
> edit: one place that implies this would be in the Gear Down section of the Micron data sheet, pg 106 "Comparision Between Gear Down Disable and Gear Down Enable," or in JEDEC 79-4B pg 83 with similar diagram.
> 
> They show where valid commands can be placed using "DES" (deselect), which happen to always line up with even ticks of the clock with GDM enabled.



I've never heard anything "official" on odd trcd working with GDM on but benchmarking my system indicates odd trcd gets rounded up to an even number.
I compared 3600 16-18-16 2t GDM off vs GDM 1t on 16-18-16 and there 2t was 0.4ns faster than GDM. I also tested 3600 mhz 16-17-16 2t GDM off vs 16-17-16 GDM 1t on and 2t was faster by 0.8ns. 

I'm on rev E it could be different on different RAM I guess.


----------



## KedarWolf

I'm very happy with this.


----------



## nick name

hazium233 said:


> What is DDR4 Memory Gear-Down Mode
> 
> I have meant to test this myself at 2666 where difference in 1t should be the biggest, but haven't gotten to it.
> 
> If the command / address are running at 1/2 frequency (aka 1/4 rate), then valid commands should only be able to have even spacing between them relative to the clock.
> 
> Otherwise, have not found another web source where this was explicitly stated. Probably because Intel doesn't support the mode.
> 
> edit: one place that implies this would be in the Gear Down section of the Micron data sheet, pg 106 "Comparision Between Gear Down Disable and Gear Down Enable," or in JEDEC 79-4B pg 83 with similar diagram.
> 
> They show where valid commands can be placed using "DES" (deselect), which happen to always line up with even ticks of the clock with GDM enabled.


Yeah, I've read that commands are on every other rising face with GDM so even values make sense. But I probably don't understand precisely what the means precisely.

Really I just don't understand why the mentioned values in Samsung (and I'm assuming Micron) paper are the ones that actually change from odd to even whereas others do not.


----------



## nick name

KedarWolf said:


> I'm very happy with this.


Ooooh, GDM disabled. I can't do that without errors. Why are you running that tRCD at 16 instead of 15?

Edit:
Ahhh, I see the 2T now. But still why 16 instead of 15?


----------



## hazium233

nick name said:


> Yeah, I've read that commands are on every other rising face with GDM so even values make sense. But I probably don't understand precisely what the means precisely.
> 
> Really I just don't understand why the mentioned values in Samsung (and I'm assuming Micron) paper are the ones that actually change from odd to even whereas others do not.


The ones that go into mode registers are used internally by the ram to do things. The four that we can set tCL, tCWL, tRTP and tWR are necessary for the ram to know when it is time to precharge if a "Read With AutoPrecharge" or "Write With AutoPrecharge" command is sent, in which case the controller will not send a discrete Precharge command for that row afterwards. Those commands tell the ram that this is the last access to the row, and that it can be closed afterwards.

In the case of tRCD, the controller is always sending the Activate and then either of the four Read or Write commands, so I think that is why this is not spelled out in ram documents. Might be listed in controller literature.

At least above is my assumption, this is not my field. 

systemverilog.io DDR4 Basics has some blurbs about read or write with auto-precharge that might be more clear than what I said. But the gist is the ram needs to be able to know how long between the RDA or WRA command to wait before starting precharge.


----------



## nick name

Bottom line is I want to know which of these timings are as they present and which have been corrected that we can't observe.


----------



## KedarWolf

nick name said:


> Ooooh, GDM disabled. I can't do that without errors. Why are you running that tRCD at 16 instead of 15?
> 
> Edit:
> Ahhh, I see the 2T now. But still why 16 instead of 15?


In the past 15 has always given me TM5 errors, but I'm trying TM5 again now with 15. I get 61.8ms with it at 15.


----------



## glnn_23

Tightened a couple timings a small amount and upped IF a little here.


----------



## KedarWolf

Got tCWL at 12 to boot, helps my Read, Write and copy some, latency at 61.8ns. My Write is above 58k. 

If it works I think having tCWL 2 below tCL is best I've read I think.

Running TM5 now.

I had to put tRDWR at 10 to get it to boot but tWRRD at 2 works.


----------



## mongoled

KedarWolf said:


> I'm very happy with this.


Nice, are you running a light BCLK overclock ?



glnn_23 said:


> Tightened a couple timings a small amount and upped IF a little here.


Great, you are the first person to show consistent sub 100s and it looking to be a valid results due to the frequeuncy and timings used.

Looks like the memory i/o die on your XT CPU is excellent

:thumb:


----------



## 2600ryzen

KedarWolf said:


> Got tCWL at 12 to boot, helps my Read, Write and copy some, latency at 61.8ns. My Write is above 58k.
> 
> If it works I think having tCWL 2 below tCL is best I've read I think.
> 
> Running TM5 now.
> 
> I had to put tRDWR at 10 to get it to boot but tWRRD at 2 works.



Does twrrd = 1 not work?


----------



## 2600ryzen

I got GDM disabled to work finally, can't get 3800mhz stable though only 3733mhz. No testmem5 errors with 3800mhz but the computer randomly blackscreens 1-2hours into testing.
2t 3733mhz was stable with a lot of fiddling with drive strengths and data bus, 7-3-1 data bus and 40-20-24-24 cad bus. Some of my timings are a bit loose like tcrdwr-trp-tfaw but I can tighten them up later. 1t GDM disabled isn't stable past 3400mhz.
Bandwidth with 2t is slightly worse than GDM and the dram calc benchmark is 0.7secs slower with 2t. Latency is about 0.4ns better with 2t though so it feels faster to use.


----------



## KedarWolf

mongoled said:


> Nice, are you running a light BCLK overclock ?
> 
> 
> Great, you are the first person to show consistent sub 100s and it looking to be a valid results due to the frequeuncy and timings used.
> 
> Looks like the memory i/o die on your XT CPU is excellent
> 
> :thumb:


I noticed it ran to 360 total, not 480, might be the amount of RAM or some other cause. But the lower the total means less time. It's much lower when I turn SMT off too. And I get like 96 seconds or something crazy low with SMT off in the BIOS and the total is much lower.

I got a 101.3 I think it was, well under 102 recently on a 480 Total in MemBench. I can't see the time without running MemBench first in my saved results and I'm running TM5 right now at cycle 17 of 25 with tCWL 12.


----------



## mongoled

KedarWolf said:


> I noticed it ran to 360 total, not 480, might be the amount of RAM or some other cause. But the lower the total means less time. It's much lower when I turn SMT off too. And I get like 96 seconds or something crazy low with SMT off in the BIOS and the total is much lower.
> 
> I got a 101.3 I think it was, well under 102 recently on a 480 Total in MemBench. I can't see the time without running MemBench first in my saved results and I'm running TM5 right now at cycle 17 of 25 with tCWL 12.


Hi! My comment regards MemBench was directed at glnn_23

I was asking you if you were using a light BCLK as your IF is at 1903 mhz.

Regards your comments on MemBench, is turning off SMT a "trick" people are using to inflate their scores ???

That would not be very nice of them without them stating they are doing this.

Looks like I will be testing that next!

And I already asked one other person about their sub 100s results and I have not seen them posting since my last comment to them regards to the validity of their result as it did not fit within the range of what most people have posted.

But that person was not using fclk over 1900 and were using loose timings, at least glnn_23 is pushing IF and has tight timings ....

Oh and tCL -2 is relatively easy to get stable


----------



## KedarWolf

mongoled said:


> Hi! My comment regards MemBench was directed at glnn_23
> 
> I was asking you if you were using a light BCLK as your IF is at 1903 mhz.
> 
> Regards your comments on MemBench, is turning off SMT a "trick" people are using to inflate their scores ???
> 
> That would not be very nice of them without them stating they are doing this.
> 
> Looks like I will be testing that next!
> 
> And I already asked one other person about their sub 100s results and I have not seen them posting since my last comment to them regards to the validity of their result as it did not fit within the range of what most people have posted.
> 
> But that person was not using fclk over 1900 and were using loose timings, at least glnn_23 is pushing IF and has tight timings ....
> 
> Oh and tCL -2 is relatively easy to get stable.


Yes, I'm running a slight BCLM overclock at 100.2. And yes, SMT off inflates the scores. But their score might be a different CPU, a 3950x does 480 Total and takes longer. Lower core CPU's have a lower total I think and take a bit less time. With SMT off it only uses 16 cores on my 3950x in MemBench and the total is much lower.


----------



## KedarWolf

tCWL 12.


----------



## mongoled

KedarWolf said:


> tCWL 12.


You know, everytime I do a succesful TM5, I reboot and run it again one more time just to be sure no "error correction" takes place after reboot.

So many time TM5 has run fine and after a reboot, not so fine.

Its time consuming, but it confirms that the timings are "holding"


----------



## rares495

KedarWolf said:


> tCWL 12.


That looks disgusting. Ewww.


----------



## ribosome

I think my IMC (Ryzen 9 3900X) might be degraded. I used to be able to run at 1900 MHz MCLK/FCLK, although I had issues with my system randomly shutting off and rebooting (no different than if I had hit the reset button) unless I set a high SOC voltage, usually slightly less than 1.2 V. Even with that issue, my system would never encounter memory errors in memtest86 or in TM5. I typically ran this SOC voltage with max or near max SOC LLC. After changing motherboards (for an unrelated reason) from a Gigabyte X470 Aorus Gaming 7 WiFi to an MSI X570 Unify I now can't even POST at these settings, and I get the same random shutoff issue at 1800 MHz MCLK/FCLK unless I increase the SOC voltage as before. The higher the SOC voltage, the less frequent the resets, although they'd still happen even at 1.15 V. They seem completely eliminated at or just before 1.2 V. I typically ran Vddg at 1.075 V and CLDO Vddp at 1.1 V. Since at this point I'm worried that I did indeed degrade my IMC (since it seems extremely rare to encounter issues running at 1800 FCLK on these chips) I've backed off to running just at 1600 MHz MCLK/FCLK same as XMP, although with tighter timings, and it seems to run just fine at auto SOC voltage which seems pinned at 1.094 V.


On my previous board when I tried running at 1900 MHz I tried various combinations of Vsoc, Vddg, CLDO Vddp, but I never found a combination that actually let my system run continuously without the weird resets, except when I increased Vsoc. I could actually boot at 1.1 Vsoc, but the system was incredibly slow and got atrocious memory benchmark scores despite still showing the FCLK at 1900 MHz.


Am I doing something wrong, or am I correct in my assessment that I've damaged my processor? This is all while running the rest of the CPU at stock, auto voltages and auto clocks, PBO disabled.


----------



## SneakySloth

So this is my 'underclock' right now. Using Patriot Viper 4400 Bdie memory with a Ryzen 3600. Anyone know if I can improve anything further or is this the best I can expect? I actually got the SCLs down to 2 but the stability of the RAM isn't as good anymore so still playing with some voltages (specifically CLDO_VDDP) to get that stable. I didn't see any improvement in benchmarks though with the SCLs at 2 each. Current latency is around 62.5


----------



## Veii

@ribosome 1.05 cLDO_VDDP is about the maximum you should run 
1.1 is already borderline 
There is no reason on locked chips to push VDDP beyond 950mV, while even that is too much for 1900FCLK
900 it is , 975mV if you do exotic +20/-60c cooling.
There really is no reason to go higher.
Same would go with VDDG beyond 1.15v, useless - might be acceptable if VDDG CCD is 1.175 if you again do LN2 coolling and push per CCX OC
Else beyond 1.15 quite a waste of heat and signal quality
vSOC the same beyond 1.2, while already 1.15 is the peak that makes even a bit of sense
This will change with Renoir, but 1.1 for cLDO_VDDP is overvolting the memory controller to a borderline state ~ where a tiny bit of fluctuation can do permanent damage (tiny spike)
Keeping in mind a bigger spike about 100mV, which many PSUs can't filter easily away can with a constant running cLDO_VDDP 1.1=1.2 already hard damage the IMC. 
I don't want to mention the "kill" word as gladly people didn't sacrifice units. But running 1.1 on cLDO_VDDP is a very bad idea 

Pushing the memory controller won't lift the artificial limitation
Nor will higher vSOC fix audio issues
These come from a bad voltage set, not a too low or too high one
Since AGESA 1005/1006 Matisse CPUs permanently changed a bit, running under 1.1vSOC is recommended or 1.125 with strong LLC
It's bypassable if you use HEX VID under AMD CBS -> NBIO , but you will have no post issues with vSOC beyond 1.1 
Which would mean cLDO_VDDP 1v and VDDG 1.05v as absolute maximum

EDIT:
Overvolting VDDG is not much of an issue. Infinity fabric snowballs with heat and that snowballing increases by higher throughput, including going from quad channel to octa channel (80-86% higher heatoutput, nearly double)
But overall it's flexible, shouldn't "die/burn" just by more voltage. Might "burn" itself to dead tho purely by heat :devil:
Overvolting cLDO_VDDP is dangerous, don't do this, it has no benefits on Matisse ~ any Matisse while it's locked
Overvolting SOC is questionable, the higher heat and higher energy has to go somewhere - if VDDP and VDDG won't use it, you might degrade the CCX on their own. Something has to use it after all when it won't stay in the fabric, nor the memory controller. Likely will degrade PCIe signal quality and might first kill memory channels near 1.4v, but 1.3 should be enough to do permanent damage


----------



## treestar

Veii said:


> The extreme isn't by any chance T-Topolgy ?
> 4x A0 might be possible at 3734MT/s if you remain under 48procODT
> 3800 can work if you can run that at 34.4Ohm with cad_bus 120-20-20-24
> But if you have A1 or A2 kits, or even dual rank ~ your chance on a daisy chain one will be very low
> 3667 is usually the absolute max, while non A0 kits will have a hard time with only 25% of the signal on the 2nd row of dimms
> T-topology would be 50/50% with some struggle with A2 kits but higher success than daisy chain with 4 dimms


 Excuse me, is it for 64gb only or any 4 sticks scenario? Either way, can you comment on these specs from MSI b550 boards, which are supposed to be daisy chain but clocks 4 sticks higher than 2?


rares495 said:


> That looks disgusting. Ewww.


One 32gb cycle in 6.45 mins is very impressive.


----------



## nick name

rares495 said:


> That looks disgusting. Ewww.


That's kind of a crappy thing to tell someone after they post an accomplishment.


----------



## mongoled

@2600ryzen

here you go,

before 

CCD/IOD both @1.15v

simply changed

CCD @1.10v
IOD @1.15v

Now to test everything again


----------



## ribosome

Veii said:


> @*ribosome* 1.05 cLDO_VDDP is about the maximum you should run
> 1.1 is already borderline
> There is no reason on locked chips to push VDDP beyond 950mV, while even that is too much for 1900FCLK
> 900 it is , 975mV if you do exotic +20/-60c cooling.
> There really is no reason to go higher.
> Same would go with VDDG beyond 1.15v, useless - might be acceptable if VDDG CCD is 1.175 if you again do LN2 coolling and push per CCX OC
> Else beyond 1.15 quite a waste of heat and signal quality
> vSOC the same beyond 1.2, while already 1.15 is the peak that makes even a bit of sense
> This will change with Renoir, but 1.1 for cLDO_VDDP is overvolting the memory controller to a borderline state ~ where a tiny bit of fluctuation can do permanent damage (tiny spike)
> Keeping in mind a bigger spike about 100mV, which many PSUs can't filter easily away can with a constant running cLDO_VDDP 1.1=1.2 already hard damage the IMC.
> I don't want to mention the "kill" word as gladly people didn't sacrifice units. But running 1.1 on cLDO_VDDP is a very bad idea
> 
> Pushing the memory controller won't lift the artificial limitation
> Nor will higher vSOC fix audio issues
> These come from a bad voltage set, not a too low or too high one
> Since AGESA 1005/1006 Matisse CPUs permanently changed a bit, running under 1.1vSOC is recommended or 1.125 with strong LLC
> It's bypassable if you use HEX VID under AMD CBS -> NBIO , but you will have no post issues with vSOC beyond 1.1
> Which would mean cLDO_VDDP 1v and VDDG 1.05v as absolute maximum
> 
> EDIT:
> Overvolting VDDG is not much of an issue. Infinity fabric snowballs with heat and that snowballing increases by higher throughput, including going from quad channel to octa channel (80-86% higher heatoutput, nearly double)
> But overall it's flexible, shouldn't "die/burn" just by more voltage. Might "burn" itself to dead tho purely by heat :devil:
> Overvolting cLDO_VDDP is dangerous, don't do this, it has no benefits on Matisse ~ any Matisse while it's locked
> Overvolting SOC is questionable, the higher heat and higher energy has to go somewhere - if VDDP and VDDG won't use it, you might degrade the CCX on their own. Something has to use it after all when it won't stay in the fabric, nor the memory controller. Likely will degrade PCIe signal quality and might first kill memory channels near 1.4v, but 1.3 should be enough to do permanent damage


 My key takeaway from this was that my cLDO_VDDP was set way too high. I backed way down on it and am now running at 0.95 V cLDO_VDDP, 1.025 V cLDO_VDDG, and auto vSOC (which ends up being 1.1 set and 1.081 get under load) with auto LLC.


It's probably a bit premature to be writing this, but I'm 18 minutes into memtest and it hasn't reset yet. On the earlier settings I'm pretty sure it would've crashed well before this point. I'm thinking it was the excessively high cLDO_VDDP that was causing it.


It's really easy to fall into the trap of thinking more voltage = stability. I have to keep telling myself that isn't the case here.


----------



## 2600ryzen

nick name said:


> That's kind of a crappy thing to tell someone after they post an accomplishment.



It's a joke I thought it was funny.


----------



## rares495

nick name said:


> That's kind of a crappy thing to tell someone after they post an accomplishment.



Well visually those timings aren't great. That's all.


----------



## binder87

Hey people. Did anyone purchase karhu recently? I just paid today for the license and the download link around 2 hours ago, got the PayPal confirmation, and still haven't received any reply from karhu with the download link and license number ....kinda feel scammed lol. I also sent a message to the karhu support , but no answer yet. I wonder if anyone experienced the same .


----------



## 2600ryzen

I got the karhu email a few seconds after the paypal receipt.


----------



## binder87

2600ryzen said:


> I got the karhu email a few seconds after the paypal receipt.


Thats weird. Did you mention something is the instructions? Or did you just get it to your PayPal associated email? Im kinda pissed i payed 10 euros and didn't get the message.


----------



## nick name

Are we checking spam folders?


----------



## binder87

nick name said:


> Are we checking spam folders?


Of course 🙂


----------



## 2600ryzen

binder87 said:


> Thats weird. Did you mention something is the instructions? Or did you just get it to your PayPal associated email? Im kinda pissed i payed 10 euros and didn't get the message.



I got the product key and a link to download from [email protected]
I think they got my email from paypal.


----------



## nick name

binder87 said:


> Of course 🙂


Well aren't you a delight.


----------



## .Morello

Hello, guys. How are you doing? I've seem a lot of helpful posts like this. They had a lot of info, thanks.
I'm having trouble trying to get 1900 FLCK stable on my 3950X. I can boot and use the computer normally or run Cinebench, but it fails P95 and Y-Crunch. Memtest passed cleanly overnight, I'm running a Samsung B-Die 3200CL14 kit at 3800CL16 with loose timings. This same kit is stable at [email protected] and overall tight timings. My motherboard is an ASUS TUF X570-Plus. Uncore OC is enabled. 3950X is running on vanilla PBO settings.



The closest I got was with 890mV VDDP, 940 VDDG, 1.05V SoC. I passed all Y-Crunch tests once before rebooting. Haven't managed to replicate it though.
I don't get any error messages, it just instantly reboots. Any advice is appreciated.


----------



## nick name

.Morello said:


> Hello, guys. How are you doing? I've seem a lot of helpful posts like this. They had a lot of info, thanks.
> I'm having trouble trying to get 1900 FLCK stable on my 3950X. I can boot and use the computer normally or run Cinebench, but it fails P95 and Y-Crunch. Memtest passed cleanly overnight, I'm running a Samsung B-Die 3200CL14 kit at 3800CL16 with loose timings. This same kit is stable at [email protected] and overall tight timings. My motherboard is an ASUS TUF X570-Plus. Uncore OC is enabled. 3950X is running on vanilla PBO settings.
> 
> 
> 
> The closest I got was with 890mV VDDP, 940 VDDG, 1.05V SoC. I passed all Y-Crunch tests once before rebooting. Haven't managed to replicate it though.
> I don't get any error messages, it just instantly reboots. Any advice is appreciated.


Sounds like a voltage problem. 

You can probably go tighter on your RAM with 1.5V DRAM voltage.

My 3900X needs 1.1V on SOC and I use the corresponding VDDG and VDDP voltages. 

And lastly -- it might just be that you need to use a higher level of Load Line Calibration on the CPU.


----------



## .Morello

nick name said:


> Sounds like a voltage problem.
> 
> You can probably go tighter on your RAM with 1.5V DRAM voltage.
> 
> My 3900X needs 1.1V on SOC and I use the corresponding VDDG and VDDP voltages.
> 
> And lastly -- it might just be that you need to use a higher level of Load Line Calibration on the CPU.


 First, thanks for trying to help!
Yeah, I think this RAM can get stable at [email protected] Haven't tried it yet tho, want to get stable 1900 FLCK first. Even with very loose times, it already gives me a performance increase against tight 3600CL14.
I've tried going up on the SOC before (900VDDP, 950VDDG, 1.1VSOC / 890VDDP, 940VDDG, 1.05VSOC) and got similar results, but didn't try increasing the CPU LLC yet. Do you think this could be dangerous with PBO enabled?


----------



## Veii

mongoled said:


> @2600ryzen
> here you go,
> 
> before
> CCD/IOD both @1.15v
> 
> simply changed
> 
> CCD @1.10v
> IOD @1.15v
> 
> Now to test everything again


What's your VDDP at ?
950/1050 ?
soo you use AVG VDDG voltage of 1125 ? 
If you bump VDDG up that high, either you have to capture vSOC "stepping" at 1150 which is then 1.2 or 1.2125v with vdroop to 1.2
Or you use the avg point ~as VDDG voltage is split and shared anyways~ , for SOC stepping = 1125 = 50 or 75mV more

Really depends what your VDDP is,
If it was 1050, then you used 75mV stepping
If it was 875, then you used double 75mV stepping
well if VDDP is 1000mV , with double 50mV would work too - but it really depends
llc vdroop messes things things quite fast. What's your goal with that high voltage ?


.Morello said:


> I'm having trouble trying to get 1900 FLCK stable on my 3950X. I can boot and use the computer normally or run Cinebench, but it fails P95 and Y-Crunch. Memtest passed cleanly overnight, I'm running a Samsung B-Die 3200CL14 kit at 3800CL16 with loose timings. This same kit is stable at [email protected] and overall tight timings. My motherboard is an ASUS TUF X570-Plus. Uncore OC is enabled. 3950X is running on vanilla PBO settings.
> 
> The closest I got was with 890mV VDDP, 940 VDDG, 1.05V SoC. I passed all Y-Crunch tests once before rebooting. Haven't managed to replicate it though.
> I don't get any error messages, it just instantly reboots. Any advice is appreciated.
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> .Morello said:
> 
> 
> 
> I've tried going up on the SOC before (900VDDP, 950VDDG, 1.1VSOC / 890VDDP, 940VDDG, 1.05VSOC) and got similar results, but didn't try increasing the CPU LLC yet. Do you think this could be dangerous with PBO enabled?
Click to expand...

likely exactly that, PBO even on default it's a mess
Don't enable it unless you want to change it and know to what you change it
It's a mess, letting it on by default.
It pushes excessive allcore voltage with no gains except thermal and "preserving silicon quality" throttling , by having that high allcore voltage thanks to it
Soo disable it !


----------



## .Morello

Veii said:


> What's your VDDP at ?
> likely exactly that, PBO even on default it's a mess
> Don't enable it unless you want to change it and know to what you change it
> It's a mess, letting it on by default.
> It pushes excessive allcore voltage with no gains except thermal and "preserving silicon quality" throttling , by having that high allcore voltage thanks to it
> Soo disable it !


 Sorry for the dumb question, when you say "Don't enable it", you mean "Don't enable PBO" or changing the CPU LLC like the other user suggested?
I'm having the impression I get farther in the tests the lower my VDDP/VDDG/SOC values are. But I always tested with PBO on (though I planned on switching to a static OC once FLCK was stable).


----------



## nick name

.Morello said:


> First, thanks for trying to help!
> Yeah, I think this RAM can get stable at [email protected] Haven't tried it yet tho, want to get stable 1900 FLCK first. Even with very loose times, it already gives me a performance increase against tight 3600CL14.
> I've tried going up on the SOC before (900VDDP, 950VDDG, 1.1VSOC / 890VDDP, 940VDDG, 1.05VSOC) and got similar results, but didn't try increasing the CPU LLC yet. Do you think this could be dangerous with PBO enabled?


No on the LLC safety being a problem. I'd also up the SOC LLC as well. I'd go second highest on the SOC LLC and find whatever keeps your CPU stable on the CPU LLC (without using the highest level). 

I use SOC LLC 4.
SOC 1.1V
VDDG 1.05V
VDDP 1.00V


----------



## Espenn

Hello, everyone. I am continuing to work on my memory OC. Quick catchup:




I have 4X sticks of single-rank Teamgroup 3200C14 B-die.
The PCBs on all DIMMs are A2.
I have an Asus Crosshair VIII Hero and a Ryzen 9 3900X.
I have active cooling on the DIMMs (120mm Noctua fan)
I'm currently getting 63.3 to 63.5ns with these timings @ 1900 fclk/mclk.
I'm 25,000% Karhu stable/25 cycles TM5 stable.
Voltages are: 1.48V DIMM, 1.1V SOC, 1.05V VDDG, 0.95V VDDP.
RTT is: 7/3/1
CAD is: 24/20/24/24
ODT is: 34.3 ohms


63.3ns is not too bad, actually. It's quite good. But I'd be thrilled to shave off another 1-2ns. Is there anything I can try?


----------



## .Morello

nick name said:


> No on the LLC safety being a problem. I'd also up the SOC LLC as well. I'd go second highest on the SOC LLC and find whatever keeps your CPU stable on the CPU LLC (without using the highest level).
> 
> I use SOC LLC 4.
> SOC 1.1V
> VDDG 1.05V
> VDDP 1.00V


Thanks for the suggestions. Seems like increasing the SOC voltage was making it fail faster. I've lowered the values a lot and disabled PBO, and I passed Y-Cruncher 3 times without any issues. My CB20 score and Dota 2 fps took a hit tho (due to no PBO).
It ended like that:
SOC 1.05V
VDDG 900mV
VDDP 800mV

I might try a simple 4Ghz fixed overclock and see if it affects stability later.
3800CL16, even with very loose timings, got better latency than 3600CL14 on Aida64.

Do you have PBO enabled? Did your static overclock change anything regarding IF stability?


----------



## KedarWolf

mongoled said:


> You know, everytime I do a succesful TM5, I reboot and run it again one more time just to be sure no "error correction" takes place after reboot.
> 
> So many time TM5 has run fine and after a reboot, not so fine.
> 
> Its time consuming, but it confirms that the timings are "holding"


----------



## Veii

.Morello said:


> Thanks for the suggestions. Seems like increasing the SOC voltage was making it fail faster. I've lowered the values a lot and disabled PBO, and I passed Y-Cruncher 3 times without any issues. My CB20 score and Dota 2 fps took a hit tho (due to no PBO).
> It ended like that:
> SOC 1.05V
> VDDG 900mV
> VDDP 800mV
> 
> I might try a simple 4Ghz fixed overclock and see if it affects stability later.
> 3800CL16, even with very loose timings, got better latency than 3600CL14 on Aida64.
> 
> Do you have PBO enabled? Did your static overclock change anything regarding IF stability?


It shouldn't do much to the boosting result, but you can work with per CCX or later a fine adjusted PBO
PBO without voltage limits only does harm and nothing good
Your voltages are low, it has no scaling inside 
VDDP -> VDDG is 100mV.
VDDG -> SOC is 150mV
unsure if this will preserve stability, but if you go with 75mV, it should work
Example:
cLDO_VDDP 825mV
VDDG IOD (is your board daisy chain?) 875
VDDG CCD 925
VSOC 1050 

VDDG without splitting it would be 900mV
With a split you can push CCD higher where avg VDDG is 900mV between both
Yes i ment to disable PBO unless you know your exact workload voltages, know which CCX are good and know how to PBO (TDC,EDC) limit them
Continue from the quote of this discussion, to the next page
Should forward you to the CH7 page and that to the X370 Taichi one

But PBO will mess up the memory OC, like every core OC normaly would
For fixed allcore, focus on staying under 1.2875v vCore ~ till you know your actual safe upper limits
4.1ghz AC should work under 1.1, 4ghz under 1v and 4.2 near 1.2175v/1.2v

Without PBO, it's suggested to use 1usmus powerprofile or the latest ryzen balanced with enabled CPPC and CPPC preferred cores functionality from the bios


----------



## Veii

KedarWolf said:


> [/SPOILER]


Good work 
Try if you can post this








Later get tWRRD up to 3 before testing it again for 2'n a half hours


----------



## KedarWolf

Veii said:


> Good work
> Try if you can post this
> 
> 
> 
> 
> 
> 
> 
> 
> Later get tWRRD up to 3 before testing it again for 2'n a half hours


Read, write and copy lowered quite a bit, latency went up .2ns.


----------



## Veii

KedarWolf said:


> Read, write and copy lowered quite a bit, latency went up .2ns.


Hmm and if you put tWR back to 10 ?
it should be a bigger difference than that


----------



## .Morello

Veii said:


> It shouldn't do much to the boosting result, but you can work with per CCX or later a fine adjusted PBO
> PBO without voltage limits only does harm and nothing good
> Your voltages are low, it has no scaling inside
> VDDP -> VDDG is 100mV.
> VDDG -> SOC is 150mV
> unsure if this will preserve stability, but if you go with 75mV, it should work
> Example:
> cLDO_VDDP 825mV
> VDDG IOD (is your board daisy chain?) 875
> VDDG CCD 925
> VSOC 1050
> 
> VDDG without splitting it would be 900mV
> With a split you can push CCD higher where avg VDDG is 900mV between both
> Yes i ment to disable PBO unless you know your exact workload voltages, know which CCX are good and know how to PBO (TDC,EDC) limit them
> Continue from the quote of this discussion, to the next page
> Should forward you to the CH7 page and that to the X370 Taichi one
> 
> But PBO will mess up the memory OC, like every core OC normaly would
> For fixed allcore, focus on staying under 1.2875v vCore ~ till you know your actual safe upper limits
> 4.1ghz AC should work under 1.1, 4ghz under 1v and 4.2 near 1.2175v/1.2v
> 
> Without PBO, it's suggested to use 1usmus powerprofile or the latest ryzen balanced with enabled CPPC and CPPC preferred cores functionality from the bios


 Thanks for linking to that post! Very informative.
Yes, I think the TUF X570-Plus is Daisy Chain.
Unfortunately, even 4Ghz was enough to make it unstable. I tried it with both my original voltages and yours and they failed Y-Cruncher on the first run (second test IIRC, pic). Any chance I just have a bad 3950X? I think the lowest I could go for 4Ghz all core was 1.1225V*.
I'm cooling it with a 360mm AIO with Noctua fans. Temps don't become an issue as long as I don't try anything above 4.1Ghz (room temp of ~25 C). On the failures I described above, temps were never above 85C, and while stress testing, the CPU voltage was ~1.16V.
Thanks for the patience to write all this, I'm learning a lot.
If possible, I'd like to avoid doing the per-CCX/CCD route for a variety of reasons, even if it means less performance. AFAIK that would require Ryzen Master and I need something more cross-platform, hence the BIOS OC. 


*Edit:* meant 1.1225V for 4Ghz, not 1.22.


----------



## Veii

.Morello said:


> Thanks for linking to that post! Very informative.
> If possible, I'd like to avoid doing the per-CCX/CCD route for a variety of reasons, even if it means less performance. AFAIK that would require Ryzen Master and I need something more cross-platform, hence the BIOS OC.


You only need ryzen master to determine the current running voltage
Since AGESA 1004B Patch B we do have per CCX OC inside the bios

Under linux AMD has a performance checking utility, although at least for UNIX/Arch Linux there are depositories that factor in SMU readouts and deliver correct voltage results
The key for using RM is only to check current and avg voltage between workloads
Y-Cruncher should be also runnable on Unix.
I can't see any reason that prevents you run per CCX or a good PBO under any OS - even macOS :thinking:

4ghz 1.2+ is weak, hmm it can be that you have a bad CCX next to the 3 other ones
Wouldn't be far of reality, considering each of them have to be good in order for an allcore to work 
I mean, figure it out 
I think the data and screenshots should be enough to let you figure it out and measure your unit
Every silicon has different voltage characteristics - only maximum boost voltage is fixed near 1.485v.
Average and allcore voltage is always unique per silicon ~ as this depends on the quality of your CCX's


----------



## .Morello

Veii said:


> You only need ryzen master to determine the current running voltage
> Since AGESA 1004B Patch B we do have per CCX OC inside the bios
> 
> Under linux AMD has a performance checking utility, although at least for UNIX/Arch Linux there are depositories that factor in SMU readouts and deliver correct voltage results
> The key for using RM is only to check current and avg voltage between workloads
> Y-Cruncher should be also runnable on Unix.
> I can't see any reason that prevents you run per CCX or a good PBO under any OS - even macOS :thinking:
> 
> 4ghz 1.2+ is weak, hmm it can be that you have a bad CCX next to the 3 other ones
> Wouldn't be far of reality, considering each of them have to be good in order for an allcore to work
> I mean, figure it out
> I think the data and screenshots should be enough to let you figure it out and measure your unit
> Every silicon has different voltage characteristics - only maximum boost voltage is fixed near 1.485v.
> Average and allcore voltage is always unique per silicon ~ as this depends on the quality of your CCX's


 Nice. Thanks again for the detailed answer. I'll see if I can find a way to keep it stable at 4Ghz while maintaining 1900 FLCK. :thumb:
Note: this OC config is stable with 1800 FLCK.


----------



## chitos123

Veii said:


> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> * and calculate tRAS with:
> tCL+tWR+tBL if user decides so
> Want to collaborate together or do you rush to make an own version ?
> Are you familiar with Android Studio or Apple XCode ?
> 
> Such switches are needed on google docs, as too much depends on patterns
> SR, DR are different , and amount of dimms change too
> Exmpl:
> 
> 
> 
> 
> 
> 
> 
> 
> Similar, with option boxes





Veii said:


> Spoiler
> 
> 
> 
> @*chitos123* did good work ~ it just looks a bit complex to use, but this comes by time
> Oh you did also a wonderful job this page http://cooln.kr/bbs/37/224005 :thumb:
> If you ever publish it on twitter, please let me retweet it
> 
> EDIT:
> @*chitos123*
> 
> Auto-Translated:
> 
> This likely was the talk with Gadfly and me
> There is a missunderstanding coming from Intel way of OC and AMD way
> Intel users have no tRC and use tRAS plus tRFC + tREFI ~ missunderstandings happen
> 
> tRFC is a fixed delay value,
> tRC is also a fixed delay but a variable=scale-able (only tRAS is not scale-able, tRP adapts)
> tRFC is a repeating refresh cycle a whole cycle inside tREFI range
> 
> It will happen and it will stay active till it happens, till it expires
> If it happens not fast enough "too late" , it will be postponed up to 9* inside the whole tREFI range
> tREFI is calculated by tRFC1-2-4 all 3 of them
> 
> Accuracy of tRFC remains important when you want a clean transition
> if tRFC is too low, it will try to postpone, timebreak and repeat it self
> if tRFC is too high , it will wait till it elapses, stop everything else and wait for it to finish
> 
> tREFI range on AMD depends if memory clear is enabled or disabled
> Recommended is Disabled, soo whole tREFI range will pass and no early random refresh happens
> Memory will break tRFC rule if tRFC 2 or 4 is awkward, but it's a fixed delay and it will stay on it till this delay elapses
> Same characteristics for tRC
> 
> tRC has to finish before anything else can be done
> You can abuse this a bit and lower it - the same way 1usmus knows a method to lower tRFC even further by using tSTAG
> But every timing we can change are fixed delays
> The rest are identical amount of realtime autocorrecting timings which adapt by the accuracy of the fixed delays
> tMRD state and tMOD are one of them - tRFC whole set a -1/+1 rounding will mess up autocorrecting values, readable via old RTC and current 1.0.0.8 ZenTimings
> 
> In the future i hope that we can readout all autocorrecting timings including tAL on each primary
> But this is a project in the future and an issue which needs to be resolved before Renoir fully launches
> Let's say before consumer 4xxx launches with variable MCLK, FCLK, UCLK
> 
> EDIT 2:
> tRFC will only be postponed if tRAS happened, Data was transferred to sensing amp, tRP tried to (p)recharge, tRC killed this cycle too early
> tRFC will try to trigger with the same delay of tRAS+tRP multiple times , but after a point discharge happens too fast and it can't keep up. Then tRFC is postponed to another time after tRC ends again(the next cycle)
> Little cheat-sheet
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> EDIT 3:
> 4.) in the writeup is very valuable, i understand my mistake and will need to retest and readjust the ruleset of tRAS & tRC
> Haven't seen negative effects by going that high , but 14-14-14 making min tRAS=16 not 28 is a too big difference to ignore
> Thank you again for collecting both sides of the learning experience. You never can learn enough. 1usmus explanation makes perfect sense


 @*Veii* 
Thank you for correcting the wrong calculation




Spoiler














Should I remove "If tCL ODD and tCWL=tCL+1 => tRD_WR -1"?

I don't understand why should i add that "tRTP value select box"
Could you please explain why not to just use
tRTP(manual)*2 = tWR
+++
[EDIT1] FIX "IF tCL ODD => tWR show 0 too
+++


Add Test4 for tRCD+tBL =tRAS


Could you please explain about DR, SR calculation differences and,
about SD(DD), tRRD, tWTR, SCL IC dependencies (or DR,SR), Low tRCD WR rule for the calculation too
Because i'm not sure of the difference in the "Ryzen-DRAM-Calculator-1.7.3" value


About that korean site, i need time to translate Accurately that you said above
Feedback on my translated text is very honorable
Thank you very much



This is new layout
(I merged two sheets of different functions.)



Spoiler














https://docs.google.com/spreadsheet...V3BjdL-dcfJJeyhdSAoJmuzJE/edit#gid=1083534502


----------



## mongoled

Veii said:


> What's your VDDP at ?
> 950/1050 ?
> soo you use AVG VDDG voltage of 1125 ?
> If you bump VDDG up that high, either you have to capture vSOC "stepping" at 1150 which is then 1.2 or 1.2125v with vdroop to 1.2
> Or you use the avg point ~as VDDG voltage is split and shared anyways~ , for SOC stepping = 1125 = 50 or 75mV more
> 
> Really depends what your VDDP is,
> If it was 1050, then you used 75mV stepping
> If it was 875, then you used double 75mV stepping
> well if VDDP is 1000mV , with double 50mV would work too - but it really depends
> llc vdroop messes things things quite fast. What's your goal with that high voltage ?
> 
> likely exactly that, PBO even on default it's a mess
> Don't enable it unless you want to change it and know to what you change it
> It's a mess, letting it on by default.
> It pushes excessive allcore voltage with no gains except thermal and "preserving silicon quality" throttling , by having that high allcore voltage thanks to it
> Soo disable it !


Agggghh,

TYPO

I am at

vDDP @0.855v
vDDG IOD @1.015v
vDDG CCD @1.010v
vSOC @1.065v
ProcODT 28 ohms
ClkDrvStren 20 ohms

Sorry about that, could have saved you that type up



Should have stable TM5/Y-crucher 3800/1900 [email protected] [email protected] to show soon

:thumb:


----------



## 2600ryzen

Veii said:


> You only need ryzen master to determine the current running voltage
> Since AGESA 1004B Patch B we do have per CCX OC inside the bios
> 
> Under linux AMD has a performance checking utility, although at least for UNIX/Arch Linux there are depositories that factor in SMU readouts and deliver correct voltage results
> The key for using RM is only to check current and avg voltage between workloads
> Y-Cruncher should be also runnable on Unix.
> I can't see any reason that prevents you run per CCX or a good PBO under any OS - even macOS :thinking:
> 
> 4ghz 1.2+ is weak, hmm it can be that you have a bad CCX next to the 3 other ones
> Wouldn't be far of reality, considering each of them have to be good in order for an allcore to work
> I mean, figure it out
> I think the data and screenshots should be enough to let you figure it out and measure your unit
> Every silicon has different voltage characteristics - only maximum boost voltage is fixed near 1.485v.
> Average and allcore voltage is always unique per silicon ~ as this depends on the quality of your CCX's



Asus finally update my b350 tuf bios so now I have separate VDDG voltages.
I'm using 1.05v vsoc 0.975v iodVDDG 0.925v ccdVDDG and 0.9v VDDP would these be the correct stepping? I'm trying to use the 2 x 0.05v step and 0.05v step.


----------



## nick name

I tested the goofy low timings I've been playing with (timings that may be corrected by the controller) and it threw a few errors overnight. I was running it at 1.5V (which droops down to 1.48V) so that might be why. 

The other thing it might mean is that the (some) timings aren't actually being corrected.


----------



## mongoled

nick name said:


> I tested the goofy low timings I've been playing with (timings that may be corrected by the controller) and it threw a few errors overnight. I was running it at 1.5V (which droops down to 1.48V) so that might be why.
> 
> The other thing it might mean is that the (some) timings aren't actually being corrected.


But what are you attempting to achieve ??


----------



## nick name

mongoled said:


> But what are you attempting to achieve ??


The same as everyone. The lowest, stable timings with the best performance. So working toward that endeavor I am trying to identify timings that you can lower, but may not actually stay at the selected values. I know there are some that get visibly adjusted during training, but still haven't found any definitive answer as to the others.


----------



## mongoled

nick name said:


> The same as everyone. The lowest, stable timings with the best performance. So working toward that endeavor I am trying to identify timings that you can lower, but may not actually stay at the selected values. I know there are some that get visibly adjusted during training, but still haven't found any definitive answer as to the others.


But purposefully using auto correction so that the motherboard appends the timings is that going to be consistent across multiple reboots ??

And also each time you force a value "lower" to what it should be, other timings we dont have access to which in turn effect timings we do have access to change, this sort of leads us to a never ending cascading effect.

Now if you are just going after performance for benchmarking purposes than I get it as every little bit helps ....


----------



## mongoled

Another for reference

14-15-14-12-26-38-247-16
BCLK @107.5625
EDC @3
MCLK/FCLK @3800/1900
vDDP @0.855v
vDDG IOD @1.015v
vDDG CCD @1.010v
vSOC @1.065v
ProcODT 28 ohms
ClkDrvStren 20 ohms


----------



## nick name

mongoled said:


> But purposefully using auto correction so that the motherboard appends the timings is that going to be consistent across multiple reboots ??
> 
> And also each time you force a value "lower" to what it should be, other timings we dont have access to which in turn effect timings we do have access to change, this sort of leads us to a never ending cascading effect.
> 
> Now if you are just going after performance for benchmarking purposes than I get it as every little bit helps ....


But see that's my point. I don't know what settings are actually being set and staying at what they're set to. 

For example: tRCDWR can be set to 6 in BIOS but will then get changed to 8 during training. Yet there are those that say 8 isn't a valid value and is corrected by the memory controller. tRAS will do the same.


----------



## mongoled

And some Corsair CMK32GX4M2D3600C18 I tweaked for a clients PC

Can be used as a baseline, could not work out what ICs were on these


----------



## nick name

So testing tRCDWR -- going from 14 to 13 to 8 all increase (not by a lot) Write and Copy in Aida.


----------



## mongoled

nick name said:


> But see that's my point. I don't know what settings are actually being set and staying at what they're set to.
> 
> For example: tRCDWR can be set to 6 in BIOS but will then get changed to 8 during training. Yet there are those that say 8 isn't a valid value and is corrected by the memory controller. tRAS will do the same.


You are doing investigative research, great.

Is this for benchmarking or general purpose ?


----------



## 2600ryzen

mongoled said:


> You are doing investigative research, great.
> 
> Is this for benchmarking or general purpose ?



You can find stuff out you never would running weird timings like nickname. I didn't know tfaw could be set below 4 x trrds.


----------



## nick name

mongoled said:


> You are doing investigative research, great.
> 
> Is this for benchmarking or general purpose ?


Well for now I'm just trying to determine whether values get corrected by the controller. And then find the lowest, stable, most performant value for it.


----------



## nick name

2600ryzen said:


> You can find stuff out you never would running weird timings like nickname. I didn't know tfaw could be set below 4 x trrds.


I'm not entirely sure going below 16 actually does anything. I'm not sure how tFAW presents in benchmarks.


----------



## rares495

nick name said:


> I'm not entirely sure going below 16 actually does anything. I'm not sure how tFAW presents in benchmarks.



It would do something if tRRDS could be set to 3 or lower but nobody managed to set it lower than 4 due to BIOS limitations.


----------



## ribosome

ribosome said:


> My key takeaway from this was that my cLDO_VDDP was set way too high. I backed way down on it and am now running at 0.95 V cLDO_VDDP, 1.025 V cLDO_VDDG, and auto vSOC (which ends up being 1.1 set and 1.081 get under load) with auto LLC.
> 
> 
> It's probably a bit premature to be writing this, but I'm 18 minutes into memtest and it hasn't reset yet. On the earlier settings I'm pretty sure it would've crashed well before this point. I'm thinking it was the excessively high cLDO_VDDP that was causing it.
> 
> 
> It's really easy to fall into the trap of thinking more voltage = stability. I have to keep telling myself that isn't the case here.


 So update... I just got another reset even as I wasn't actually doing anything on the computer at all, although it passed memtest at 500+% just fine. So it's starting to seem again like my system really isn't stable at 1800. However I'm going to try now with 900 mV cLDO_VDDP, 1.05 V cLDO_VDDG, and override VSOC to 1.1 V with mode 2 LLC (2nd highest) so that it's pegged at 1.1 in HWiNFO64.


Let's see how long it lasts now before I get another reset.


----------



## Solohuman

ribosome said:


> So update... I just got another reset even as I wasn't actually doing anything on the computer at all, although it passed memtest at 500+% just fine. So it's starting to seem again like my system really isn't stable at 1800. However I'm going to try now with 900 mV cLDO_VDDP, 1.05 V cLDO_VDDG, and override VSOC to 1.1 V with mode 2 LLC (2nd highest) so that it's pegged at 1.1 in HWiNFO64.
> 
> 
> Let's see how long it lasts now before I get another reset.


If I were you I'd change one thing at at time, then retest. This is the only way you'll know that is actually causing the issue.


----------



## ribosome

Solohuman said:


> If I were you I'd change one thing at at time, then retest. This is the only way you'll know that is actually causing the issue.


I know that's normally a good way of going about it, but since I usually see hours or even days between resets that can often take a very long time. That said I just now got another reset. So I did change just one thing this time. I upped cLDO_VDDP to 1 V. I'm guessing it was too low at 900 mV and I doubt that the change to vSOC or its LLC made the difference here. If it resets again I'll try keeping cLDO_VDDP as-is but return vSOC and vSOC LLC to auto.


----------



## jeremy.b

ribosome said:


> Solohuman said:
> 
> 
> 
> If I were you I'd change one thing at at time, then retest. This is the only way you'll know that is actually causing the issue.
> 
> 
> 
> I know that's normally a good way of going about it, but since I usually see hours or even days between resets that can often take a very long time. That said I just now got another reset. So I did change just one thing this time. I upped cLDO_VDDP to 1 V. I'm guessing it was too low at 900 mV and I doubt that the change to vSOC or its LLC made the difference here. If it resets again I'll try keeping cLDO_VDDP as-is but return vSOC and vSOC LLC to auto.
Click to expand...

I have had some success finding voltage related issues using memtest86+ (5.31) of all things. Just today I was testing increasing cLDO_VDDP from 900 to 950mv on my DR BDIE set and would would trigger a reset consistently by manually running tests 3,5,6,7,8.

I'm contrast I have a DR Micron e die set that would throw errors in memtest86+ when transitioning from test 6 to 7 but would last for quite a while in tm5 and bumping cLDO_VDDP from 900 to 950 (while keeping clean 50mv steps on the rest of the soc voltages) cleaned that set up.

All that to say, I've found different tools can find errors more easily be than others sometimes.


----------



## ribosome

I'll have to see if I can find a consistent way of reproducing these resets myself. Right now my "stability test" is "use the computer as normal until it crashes"


As I said above if it reset again I would return vSOC and vSOC LLC to auto, and it did reset so that's what I tried. Lo and behold it still reset again, less than an hour later.


The one thing in common at this point with these quick resets is that I had increased cLDO_VDDG by 25 mV to 1050 mV. It seemed the most stable when it was at 1025 mV, and I hadn't tried any lower than that. So keeping everything else the same (currently 950 mV cLDO_VDDP, auto vSOC and LLC) I've tried lowering cLDO_VDDG to 1000 mV. Let's see how long it lasts this time. If it resets again I might be out of ideas. Although I haven't yet touched the DRAM voltage... maybe that's something to try.


----------



## Veii

chitos123 said:


> Veii,
> Thank you for correcting the wrong calculation
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Should I remove "If tCL ODD and tCWL=tCL+1 => tRD_WR -1"?


No need, if tRDWR math is correct, then tCWL=tCL+2=tRDWR-1
GDM does correct tCWL up to even values.
I have not confirmed if tRDWR can drop beyond -1 of tRCD RD/2-1 
Never seen it drop beyond -1. But this is a good topic to investigate
Will report back if I get some results, or people help me rest it

Atm my focus is learning 1usmus tRAS ruleset
Seems like that low how he explains it posts and makes sense
But we have a hard lock of 21 atm
Soo the only reasonable usecase is


----------



## chitos123

Veii said:


> Error 0 refresh stable error = voltage cutoff choke
> 
> Error 1= Simple Test 16mb ~ can be voltage related, can be tRFC issues,
> tiny timeout issues for example tRRD_L looks like a bit awkward
> 
> Error 2, 12 is a timeout issue, somewhere something ends too quickly or you lack voltage and cells are not recharged in time
> a sync issue with other words which's first culprit is voltage somewhere or resistance somewhere
> 
> Error 3 & 4 by checking the MT.cfg - are MirrorMove errors
> That set shows tRFC 2 issues and this tRFC "auto predicted" ? is wrong.
> tRFC is so far always even
> as tRFC stepping are 32,16,8,4,2 ,
> 
> Error 5 then 6 is a timings missmatch between dimms (data mirror move)
> 
> Error 6 is purely related to the IMC , be if procODT, CLDO_VDDP or vSOC
> ~ it translates to "i couldn't even start transfering data, i crashed"
> 4-6x error 6 result in full bluescreen
> 
> Error 7, 11 are burst tests
> - it will error out if if CAD_BUS is not optimal
> - will error out of tRFC is too low
> - mostly errors out only after time
> 
> Error 9 burst test 4mb is a voltage stability issue
> If you've lowered tRP , increase vDimm a tiny bit
> If you've increased tRP to longer delay, decrease vDIMM +0.01 , one tiny step
> 
> Error 10 mostly affects the first 5 main timings
> - noticed it can be tRCDWR to RD, can be tRP too, but it also can be the last two tRDWR & tRDRD which don't play well with your main tRCDWR/RD
> 
> Error 13 = Simple Test 64mb, timeout while transfering big data
> = full crash, nearly always related to voltage ~ as memory was not able to autocorrect it
> 
> Error 14 we know is MirrorMove 0mb, a timeout issue
> - it can error after the 2nd or 3rd pass if something is off my some ns and just "got lost"


TM5 error
0,1,2,3,4,5,6,7,9,10,11,12,13,14

Can't find
8,15 ???
And not sure about error 5

Anybody know? 5,8,15 ???


----------



## Cosminnn

KedarWolf said:


> I'm very happy with this.


What voltages did you used with this setup? Sorry if you posted and I missed it.


----------



## KedarWolf

Cosminnn said:


> What voltages did you used with this setup? Sorry if you posted and I missed it.


SoC is 1.13v in HWInfo.


----------



## nick name

ribosome said:


> So update... I just got another reset even as I wasn't actually doing anything on the computer at all, although it passed memtest at 500+% just fine. So it's starting to seem again like my system really isn't stable at 1800. However I'm going to try now with 900 mV cLDO_VDDP, 1.05 V cLDO_VDDG, and override VSOC to 1.1 V with mode 2 LLC (2nd highest) so that it's pegged at 1.1 in HWiNFO64.
> 
> 
> Let's see how long it lasts now before I get another reset.


Perhaps it's the CPU? Are you running the EDC bug? What are your CPU voltage settings and LLC?


----------



## Ortus

ribosome said:


> I'll have to see if I can find a consistent way of reproducing these resets myself. Right now my "stability test" is "use the computer as normal until it crashes"
> 
> 
> As I said above if it reset again I would return vSOC and vSOC LLC to auto, and it did reset so that's what I tried. Lo and behold it still reset again, less than an hour later.
> 
> 
> The one thing in common at this point with these quick resets is that I had increased cLDO_VDDG by 25 mV to 1050 mV. It seemed the most stable when it was at 1025 mV, and I hadn't tried any lower than that. So keeping everything else the same (currently 950 mV cLDO_VDDP, auto vSOC and LLC) I've tried lowering cLDO_VDDG to 1000 mV. Let's see how long it lasts this time. If it resets again I might be out of ideas. Although I haven't yet touched the DRAM voltage... maybe that's something to try.


I had very similar issues with stability on my Ace, which should have identical VRM to your Unify, the crashes were never consistent but always seemed to be when the CPU went from high>idle, so I assume it has something to do with transient response. 

I fixed it by setting VDDG_IOD within 40mV of SoC. I assume this clamped voltage spikes to a something the CPU can handle, but can't be sure.


----------



## nick name

I've been looking at the new 4750G Geekbench 5 scores and found one with IF at 2100MHz. I imagine there are more, but I ran over here after I found that one. 

Does anyone think that is going to be what the next Ryzen 4000 CPUs will do too? Should we be preparing to run 4200MHz RAM? Sounds like it's going to be a blast.


----------



## ribosome

nick name said:


> Perhaps it's the CPU? Are you running the EDC bug? What are your CPU voltage settings and LLC?


What EDC bug? I haven't heard of that before. My CPU voltage and LLC are both at auto, as are the multiplier and BCLK. I have PBO disabled.




Ortus said:


> I had very similar issues with stability on my Ace, which should have identical VRM to your Unify, the crashes were never consistent but always seemed to be when the CPU went from high>idle, so I assume it has something to do with transient response.
> 
> I fixed it by setting VDDG_IOD within 40mV of SoC. I assume this clamped voltage spikes to a something the CPU can handle, but can't be sure.


Do you mean that you had to set VDDG_IOD to no more than vSOC - 40 mV, or no less than vSOC - 40 mV? Right now I'm still on the settings in my last post, which have VDDG_CCD and VDDG_IOD both at vSOC - 100 mV, and they seem fine.


----------



## nick name

I just learned that my 2700X could do 3600MHz 14-15-14-14 with GDM disabled, but my 3900X cannot. Can anyone here with a Ryzen 3000 CPU run 3600C14 with GDM off?

Edit:
Turns out that it wasn't the difference in CPUs, but in memory kits. My older (July 2018) b-die that I used with my 2700X can run with GDM disabled on my 3900X, but my two newer (June/July 2020) b-die kits cannot.


----------



## mirzet1976

nick name said:


> I just learned that my 2700X could do 3600MHz 14-15-14-14 with GDM disabled, but my 3900X cannot. Can anyone here with a Ryzen 3000 CPU run 3600C14 with GDM off?


Here R5 3600


----------



## Veii

Ortus said:


> I had very similar issues with stability on my Ace, which should have identical VRM to your Unify, the crashes were never consistent but always seemed to be when the CPU went from high>idle, so I assume it has something to do with transient response.
> 
> I fixed it by setting VDDG_IOD within 40mV of SoC. I assume this clamped voltage spikes to a something the CPU can handle, but can't be sure.


Unless you set both at vSOC -40mV , you have issues
but there needs to be at least 48mV difference between VDDG constant current and vSOC = 50mV at least
if you only push one VDDG higher, it's fine you can go down to near 25mV difference ~ as voltage is split up to current needs
But if both peak at the same high current with barely difference to vSOC , you will have issues.


nick name said:


> I've been looking at the new 4750G Geekbench 5 scores and found one with IF at 2100MHz. I imagine there are more, but I ran over here after I found that one.
> 
> Does anyone think that is going to be what the next Ryzen 4000 CPUs will do too? Should we be preparing to run 4200MHz RAM? Sounds like it's going to be a blast.


Renoir can run 2100FCLK , and some made 2200FCLK to work
I don't think that we should focus on pin-pushing constant FCLK, but work with it's dynamic way


nick name said:


> I just learned that my 2700X could do 3600MHz 14-15-14-14 with GDM disabled, but my 3900X cannot. Can anyone here with a Ryzen 3000 CPU run 3600C14 with GDM off?


+1 
Tomorrow i'll show some results of another 3600 sample, he sleeps atm
We try 1900 GDM off CL14-14-15, we'll see 

Having issues with a Micron:A RX 5700 (Red Devil but only XT has samsung vram) which VRAM crashes (needs RMA), PCIe 4.0 keeps crashing @ 1900FCLK, 1867 works and 3600MT/s solely works too @ flat C14


----------



## nick name

mirzet1976 said:


> Here R5 3600


Stability test please.


----------



## glnn_23

Just trying different memory speed and timings here.


----------



## Solohuman

helsyeah said:


> I have had some success finding voltage related issues using memtest86+ (5.31) of all things. Just today I was testing increasing cLDO_VDDP from 900 to 950mv on my DR BDIE set and would would trigger a reset consistently by manually running tests 3,5,6,7,8.
> 
> I'm contrast I have a DR Micron e die set that would throw errors in memtest86+ when transitioning from test 6 to 7 but would last for quite a while in tm5 and bumping cLDO_VDDP from 900 to 950 (while keeping clean 50mv steps on the rest of the soc voltages) cleaned that set up.
> 
> All that to say, I've found different tools can find errors more easily be than others sometimes.


How come use old version of memtest86? v8.4 has refinements for better DDR4 fault finding. 
Lot of patience needed for OC testing I know...lol..

I always use diff apps for mem testing when in Windows. Heck, even the old prime 95 large FFTS is a good one still despite more modern stuff. 
But in the end it will depend on what one wants to use the machine for.


----------



## 2600ryzen

ribosome said:


> What EDC bug? I haven't heard of that before. My CPU voltage and LLC are both at auto, as are the multiplier and BCLK. I have PBO disabled.
> 
> 
> 
> Do you mean that you had to set VDDG_IOD to no more than vSOC - 40 mV, or no less than vSOC - 40 mV? Right now I'm still on the settings in my last post, which have VDDG_CCD and VDDG_IOD both at vSOC - 100 mV, and they seem fine.



atm I'm running 3666mhz 1.05vsoc, 0.9v VDDG CCD, 0.8v VDDG IOD, and 0.825v VDDP. Stable for 180cycles of tm5, 5 min p95 small fft and 5 min large fft, and 20 min of ycruncher.
Reducing VDDG IOD that much only seems to save about 1-2w PPT though, VDDG CCD is the one that does most work.


----------



## SneakySloth

Can someone tell me how I can be stable in Tm5 for 80 cycles (1usmus v3 profile) but get an error in karhu within 2 minutes? The overclock is 3 hours Prime95 blend, 3 hour y-cruncher and 80 cycles of tm5 stable. What should I be changing at that point to fix this? It could be a false positive as I'm running karhu again and this time its okay at 5 minutes and running but I dont know.


EDIT:


Got an error at 1800 coverage, 23 minutes. This is with cache enabled.


----------



## ribosome

Veii said:


> Unless you set both at vSOC -40mV , you have issues
> but there needs to be at least 48mV difference between VDDG constant current and vSOC = 50mV at least
> if you only push one VDDG higher, it's fine you can go down to near 25mV difference ~ as voltage is split up to current needs
> But if both peak at the same high current with barely difference to vSOC , you will have issues.


Is there a way to monitor what VDDG is actually running at? Ryzen Master only tells me what voltages are set to, not what they actually are, and no other tool I know of shows VDDG. Or do you mean that's what the difference needs to be after vSOC vdroop under load?


----------



## Veii

SneakySloth said:


> Can someone tell me how I can be stable in Tm5 for 80 cycles (1usmus v3 profile) but get an error in karhu within 2 minutes? The overclock is 3 hours Prime95 blend, 3 hour y-cruncher and 80 cycles of tm5 stable. What should I be changing at that point to fix this? It could be a false positive as I'm running karhu again and this time its okay at 5 minutes and running but I dont know.


TM5 does test the memory but ryzen 3rd gen is already quite talented in keeping up stability.
TM5 isn't able to detect memory controller issues ~ for such work you use all of the tests on y-cruncher and hope it's just a voltage issue which an AVX2 test will detect

Karhu likely also like Aia64 Cache+FPU test together, does focus on the cache side of things
Karhu with cache will fail if the IMC fails to hold this voltage, or also will fail if one of the cores fail by going into sleep (very rare)
Karhu same as every memtest can fail because of many things on such long durations.
It can be in your house a fridge or washing machine which goes on. It can be bad powerdraw from the outside.
H*ck it can be even sun eruption causing an EMI peak or some technician in the neighborhood having issues with the cellphone tower ~ which indeed do create and modify V/m or sometimes measured in Gauss (mG) on what Memory remains very sensitive (EMF/EMI)

It sounds contraproductive, but random events can happen on such extremely long testing durations and most are autocorrected
If Karhu instantly fails, reinstall Karhu for now
Try to put Powersuply Idle Control inside your bios to "Typical Current" to prevent sleep mode hangups, which some PSUs choke on (when the unit barely pulls current and the PSU thinks it's just "vampire draw/phantom load" )

You didn't mention under Prime95 exactly which version at what dataset
Although trusting you Y-Cruncher the whole testing suite passed several times, it's not AVX2 at least that causes issues
An advice is, to also add OCCT to your testing suite. Medium Dataset AVX2 is heavy and finds memory errors
Prime95 LargeFFT specific for a duration of 3 hours, finds also anomalies with the memory controller (voltages) 

At this point it can be everything in an unclear listed testing issue.
Could be heat after playing and then doublechecking Karhu to make the IMC crash ~ or a hot VRM setup which's loadline randomly drooped to low
Could be a one time only random event.
But my personal guess here is a sleep/suspension dropout issue by the PSU. 
Change this Idle Control option inside the bios 
(Standy will pull couple of watts more, but it's barely noticable. Should be 1 digit Watt only) 
And if nothing didn't change, just swap your dimms around and see if this fixes it.
Even reseats often fix such anomalies.

TM5's work is only to verify the memory timings, nothing around it
But it will also fail if the CPU can't keep up stability.
Karhu uses a different aproach


ribosome said:


> Is there a way to monitor what VDDG is actually running at? Ryzen Master only tells me what voltages are set to, not what they actually are, and no other tool I know of shows VDDG. Or do you mean that's what the difference needs to be after vSOC vdroop under load?


Sadly no 
VDDG does fluctuate. It's one of the reasons we can pass by with less than 50mV difference between the highest listed one
It can be abused to help , letting it prioritize on a specific part more voltage.
But it's one VDDG line. (well technically twice the access to different parts of one line) 
VDDG CCD inside the CPU and VDDG IOD outside of the cpu towards IO, Memory Dimms, PCIe 
And SOC being the main powerline. 
cLDO_VDDP is also only a fraction of this main SOC powerline, but it's one and only soo not splittable

No tool can report what it fluctuates too. Only Renoir and up can.
There is just no point after it is inside the CPU to monitor it. FIT knows it and you tell FIT via SMU what to do
If FIT does the job or not is a fundamental design "issue".
But we know the different VDDG splittings are applied correctly.
We don't know by how much they are off.
Well actually we do know a bit more, as Ryzen Master does report the values with Vdroop factored in.
But again, there is no 2nd probe to monitor the VDDG IOD voltage out off.
Such would be a board-design's work, and likely would add resistance into it by trying to read it out
Can see Asus getting their head around it ~ but Matisse has no sensor to track it. At least nothing we know


----------



## SneakySloth

Veii said:


> TM5 does test the memory but ryzen 3rd gen is already quite talented in keeping up stability.
> TM5 isn't able to detect memory controller issues ~ for such work you use all of the tests on y-cruncher and hope it's just a voltage issue which an AVX2 test will detect
> 
> Karhu likely also like Aia64 Cache+FPU test together, does focus on the cache side of things
> Karhu with cache will fail if the IMC fails to hold this voltage, or also will fail if one of the cores fail by going into sleep (very rare)
> Karhu same as every memtest can fail because of many things on such long durations.
> It can be in your house a fridge or washing machine which goes on. It can be bad powerdraw from the outside.
> H*ck it can be even sun eruption causing an EMI peak or some technician in the neighborhood having issues with the cellphone tower ~ which indeed do create and modify V/m or sometimes measured in Gauss (mG) on what Memory remains very sensitive (EMF/EMI)
> 
> It sounds contraproductive, but random events can happen on such extremely long testing durations and most are autocorrected
> 
> 
> If Karhu instantly fails, reinstall Karhu for now
> Try to put Powersuply Idle Control inside your bios to "Typical Current" to prevent sleep mode hangups, which some PSUs choke on (when the unit barely pulls current and the PSU thinks it's just "vampire draw/phantom load" )
> 
> You didn't mention under Prime95 exactly which version at what dataset
> Although trusting you Y-Cruncher the whole testing suite passed several times, it's not AVX2 at least that causes issues
> An advice is, to also add OCCT to your testing suite. Medium Dataset AVX2 is heavy and finds memory errors
> Prime95 LargeFFT specific for a duration of 3 hours, finds also anomalies with the memory controller (voltages)
> 
> At this point it can be everything in an unclear listed testing issue.
> Could be heat after playing and then doublechecking Karhu to make the IMC crash ~ or a hot VRM setup which's loadline randomly drooped to low
> Could be a one time only random event.
> But my personal guess here is a sleep/suspension dropout issue by the PSU.
> Change this Idle Control option inside the bios
> (Standy will pull couple of watts more, but it's barely noticable. Should be 1 digit Watt only)
> And if nothing didn't change, just swap your dimms around and see if this fixes it.
> Even reseats often fix such anomalies.
> 
> TM5's work is only to verify the memory timings, nothing around it
> But it will also fail if the CPU can't keep up stability.
> Karhu uses a different aproach



It was the latest version of prime95 with avx enabled. I ran the blend test for 2 hours and the the tests were either from the smallest fft or the large fft set. 

In y cruncher I enabled all the tests and ran it first for 3 runs, rebooted and ran again for 9 runs. All the tests passed in the runs.


For tm5 I did 20 cycles then 40 cycles. Rebooted and did 40 cycles again. No errors were found. 

I also played 2 hours of battlefiled 1 to see if I get any hardware errors in hwinfo, everything was fine there too. 

Karhu was supposed to be the final test for me. I was going to leave it overnight and hopefully have it pass so that my ram is stable in my eyes. But sadly it crashes first within 2 minutes and on a rerun it crashed again in 23 minutes.

Right now, I changed my tcwl = tcl, it was tcl-2 before. I'm running karhu again so let's see how far it goes this time. It it crashes again I'll definitely try your suggestion about the idle control option. I have manually overclocked the CPU btw. The stability for that was checked using prime95 small fft and realbench for 8 hours. 

I will also add occt to the list after karhu. Thank you for the suggestion.


----------



## 2600ryzen

SneakySloth said:


> Can someone tell me how I can be stable in Tm5 for 80 cycles (1usmus v3 profile) but get an error in karhu within 2 minutes? The overclock is 3 hours Prime95 blend, 3 hour y-cruncher and 80 cycles of tm5 stable. What should I be changing at that point to fix this? It could be a false positive as I'm running karhu again and this time its okay at 5 minutes and running but I dont know.
> 
> 
> EDIT:
> 
> 
> Got an error at 1800 coverage, 23 minutes. This is with cache enabled.



Try Karhu again with cpu cache set to default instead of enabled, you could also try disabled if that fails too.


----------



## nick name

2600ryzen said:


> Try Karhu again with cpu cache set to default instead of enabled, you could also try disabled if that fails too.


I wouldn't do that if you want to actually test.


----------



## 2600ryzen

nick name said:


> I wouldn't do that if you want to actually test.


You can test what's causing it to crash that way. His ram sounds stable, but so does his cpu.


----------



## chitos123

@*Veii* 



Veii said:


> Spoiler
> 
> 
> 
> No need, if tRDWR math is correct, then tCWL=tCL+2=tRDWR-1
> GDM does correct tCWL up to even values.
> I have not confirmed if tRDWR can drop beyond -1 of tRCD RD/2-1
> Never seen it drop beyond -1. But this is a good topic to investigate
> Will report back if I get some results, or people help me rest it


Fixed IF tCL-tCWL=Negative AND tRCD_RD ODD
-> then tRD_WR calculation A=B (A|B)
(Before it drop beyond -1)




> Spoiler
> 
> 
> 
> Atm my focus is learning 1usmus tRAS ruleset
> Seems like that low how he explains it posts and makes sense
> 
> But we have a hard lock of 21 atm
> Soo the only reasonable usecase is


----------



## nick name

2600ryzen said:


> You can test what's causing it to crash that way. His ram sounds stable, but so does his cpu.


Ahhh, I get what you're saying now.


----------



## SneakySloth

Veii said:


> TM5 does test the memory but ryzen 3rd gen is already quite talented in keeping up stability.
> TM5 isn't able to detect memory controller issues ~ for such work you use all of the tests on y-cruncher and hope it's just a voltage issue which an AVX2 test will detect
> 
> Karhu likely also like Aia64 Cache+FPU test together, does focus on the cache side of things
> Karhu with cache will fail if the IMC fails to hold this voltage, or also will fail if one of the cores fail by going into sleep (very rare)
> Karhu same as every memtest can fail because of many things on such long durations.
> It can be in your house a fridge or washing machine which goes on. It can be bad powerdraw from the outside.
> H*ck it can be even sun eruption causing an EMI peak or some technician in the neighborhood having issues with the cellphone tower ~ which indeed do create and modify V/m or sometimes measured in Gauss (mG) on what Memory remains very sensitive (EMF/EMI)
> 
> --snip--





2600ryzen said:


> You can test what's causing it to crash that way. His ram sounds stable, but so does his cpu.



I will definitely try that, thank you for the suggestion.


I have still to try the following two things:
1. Powersuply Idle Control set to typical current.
2. Run Karhu without cache to see if I get an error.


I have also attached my tm5 stable timings as a reference.



My last run where karhu crashed was at tcwl = tcl instead of tcwl = tcl - 2 (tcwl = 12 was stable in tm5). Karhu showed an error on that run at 12000(ish) coverage. I rebooted after that and changed the following in bios:
1. CLDO_VDDP to 0.960 (previously 0.965)
2. Changed power profile to Ryzen Balanced instead of 1usmus Ryzen Universal
3. Tcwl still at 14


Right now, karhu with cache enabled is at 20000 coverage and still running. At this point I do want to stop it and call it stable but in previous days I've had karhu show an error at around 23000 coverage with other settings so I'll let it run and see how far I can get. I am yet to try TM5, Prime95, Y-Cruncher and OCCT at these new settings.


----------



## mongoled

glnn_23 said:


> Just trying different memory speed and timings here.


Wow just wow,

where is all that extra performance coming from ?

Is the XT memory controller so much better than the non XTs ?

Ive attempted to do as close as I can like for like settings but the gap is huge.

Yes, I understand that is a 3900XT and I am using a 3600 its just that the gap is not so big when MCLK/FLCK is at 1:1 ratio between our rigs but once dividers are introduced your motherboard and CPU has not lost any throughput on the contrary you have gained throughput 

Where as on my X370 my throughput has dropped considerably when moving from a 1:1 MCLK/FLCK ratio.

Your the second person who has posted amazing improvements in the time required for a "MemBench Easy Mode" score, where are these improvements coming from as there is no radical improvements in timings, so im at a loss to understand where all the performance gain is coming from.

Are you using a tweaked Windows OS ??


----------



## 2600ryzen

Going to 2:1 only 'works' on the 3900x and up multi ccd chips because of the write bandwidth. Single ccd chips like the 3600 are too crippled to see any bandwidth improvement.


----------



## nick name

Does anyone have an idea as to why my older (July 2018) 3600C15 b-die kit can run 3600MHz 14-15-14-14 1T with GDM disabled, but my two newer kits (3600C15 from June 2020 and 4400C19 from July 2020) cannot run 3600MHz 14-15-14-14 with GDM disabled?


----------



## .Morello

I've made further testing and, as long as I keep the rest on stock, I can pass stress tests with 1900FLCK using a range of values for VDDP/VDDG/VSOC. CPU is a 3950X. 
I've also tested 1800 FLCK + PBO, and it's stable on P95 overnight.

However, PBO + 1900 FLCK makes my computer reboot after a few minutes of P95, and it makes all my static overclocks fail (while in 1800 FLCK they're stable well below the FIT voltage).
Are there any specific values I should look into changing to make it more stable under high load?


----------



## rares495

nick name said:


> Does anyone have an idea as to why my older (July 2018) 3600C15 b-die kit can run 3600MHz 14-15-14-14 1T with GDM disabled, but my two newer kits (3600C15 from June 2020 and 4400C19 from July 2020) cannot run 3600MHz 14-15-14-14 with GDM disabled?


Different PCB? July 2018 could be A0 and the others A2.


----------



## mongoled

2600ryzen said:


> Going to 2:1 only 'works' on the 3900x and up multi ccd chips because of the write bandwidth. Single ccd chips like the 3600 are too crippled to see any bandwidth improvement.


Is this your opinion or have you read some research somewhere showing this ?

How does write bandwidth effect the efficiency of read bandwidth ?

I hadnt come across such information before.


----------



## 2600ryzen

mongoled said:


> Is this your opinion or have you read some research somewhere showing this ?
> 
> How does write bandwidth effect the efficiency of read bandwidth ?
> 
> I hadnt come across such information before.



Just my opinion mainly from watching some of buildzoid's videos 2:1 memory overclocking.


----------



## nick name

rares495 said:


> Different PCB? July 2018 could be A0 and the others A2.


Definitely different PCB revisions. I just can't think of a reason why the older revision allows for GDM to be disabled at higher speeds/lower CL than the newer PCB revision which is the better overclocker.


----------



## SneakySloth

So what do I do if I just passed Karhu at 42000% coverage with cache enabled but get an error in Tm5 on the 12th cycle, error code 2? This was without rebooting, after 15ish minutes of Karhu ending.


----------



## nick name

SneakySloth said:


> So what do I do if I just passed Karhu at 42000% coverage with cache enabled but get an error in Tm5 on the 12th cycle, error code 2? This was without rebooting, after 15ish minutes of Karhu ending.


I had a problem like that and it was resolved with a touch more voltage.


----------



## SneakySloth

nick name said:


> I had a problem like that and it was resolved with a touch more voltage.



Which voltage? Dim voltage or one of the SOC ones? The problem is I'm currently at 1.5v on samsung B die and I dont want to go any higher.


One thing to note, I actually have the dim voltage set as 1.48 in the bios but it shows up as 1.5v in Hwinfo and the Bios reading so I'm guessing there is some form of offset in my motherboard's bios (X570 Tomahawk).


----------



## rares495

nick name said:


> Definitely different PCB revisions. I just can't think of a reason why the older revision allows for GDM to be disabled at higher speeds/lower CL than the newer PCB revision which is the better overclocker.


I don't know. Binning probably plays a part in this as well.


----------



## nick name

SneakySloth said:


> Which voltage? Dim voltage or one of the SOC ones? The problem is I'm currently at 1.5v on samsung B die and I dont want to go any higher.
> 
> 
> One thing to note, I actually have the dim voltage set as 1.48 in the bios but it shows up as 1.5v in Hwinfo and the Bios reading so I'm guessing there is some form of offset in my motherboard's bios (X570 Tomahawk).


Does HWiNFO tell you your DRAM voltage? Perhaps there is a little droop there. My 1.5V droops to ~1.48V -- so 1.52V gets me to 1.5V. 

I can't remember which voltage it was I increased though I wanna say SOC. I bumped it to 1.106V because it would droop slightly.


----------



## nick name

rares495 said:


> I don't know. Binning probably plays a part in this as well.


And that's what increases my confusion. The new kits are definitely better bins in respect to voltage, speed, timings. Just not command rate.


----------



## SneakySloth

nick name said:


> Does HWiNFO tell you your DRAM voltage? Perhaps there is a little droop there. My 1.5V droops to ~1.48V -- so 1.52V gets me to 1.5V.
> 
> I can't remember which voltage it was I increased though I wanna say SOC. I bumped it to 1.106V because it would droop slightly.



So i'm looking at the sensor reading for DIMM under my motherboard's sensor readings and that stays at 1.504 regardless of the load. So there really is no droop there which makes no sense as I assumed there always was some droop. So maybe the sensor isn't reading the value properly?


Whats strange is for me ryzen master shows the voltage as 1.48 (the one that I actually set in bios), so at this point I dont know what to trust. Searching the forum it does seem like a bunch of MSI motherboards report the memory voltage ~20mv higher than the one set in BIOS.


----------



## nick name

SneakySloth said:


> So i'm looking at the sensor reading for DIMM under my motherboard's sensor readings and that stays at 1.504 regardless of the load. So there really is no droop there which makes no sense as I assumed there always was some droop. So maybe the sensor isn't reading the value properly?
> 
> 
> Whats strange is for me ryzen master shows the voltage as 1.48 (the one that I actually set in bios), so at this point I dont know what to trust. Searching the forum it does seem like a bunch of MSI motherboards report the memory voltage ~20mv higher than the one set in BIOS.


How about SOC?


----------



## SneakySloth

nick name said:


> How about SOC?



That's constant too. It set to 1.1 in the bios and reported as 1.112 in Hwinfo.


----------



## jeremy.b

Solohuman said:


> How come use old version of memtest86? v8.4 has refinements for better DDR4 fault finding.
> Lot of patience needed for OC testing I know...lol..
> 
> I always use diff apps for mem testing when in Windows. Heck, even the old prime 95 large FFTS is a good one still despite more modern stuff.
> But in the end it will depend on what one wants to use the machine for.


Memtest86+: https://www.memtest.org/

Vs memtest86: https://www.memtest86.com/

There are different tools, one open source (the '+') and the other is not.

I have not tried the freeware version of memtest86 lately, and just defaulted to the open source one that I used in the past.

I wouldn't use either for long term stability testing when compared to ramtest or TM5, but for a fast basic stability test they seem to work well.


----------



## SneakySloth

Currently trying to troubleshoot error in test 13 in TM5. It showed up in the 32nd cycle. I was able to reproduce it after running a custom TM5 config with just tests 2 and 13, happened in the 27th cycle this time on test 13. This seems to have something to do with voltage but which voltage though? Memory, SOC, VDDG or VDDP?


Thanks


----------



## glnn_23

mongoled said:


> Wow just wow,
> 
> where is all that extra performance coming from ?
> 
> Is the XT memory controller so much better than the non XTs ?
> 
> Ive attempted to do as close as I can like for like settings but the gap is huge.
> 
> Yes, I understand that is a 3900XT and I am using a 3600 its just that the gap is not so big when MCLK/FLCK is at 1:1 ratio between our rigs but once dividers are introduced your motherboard and CPU has not lost any throughput on the contrary you have gained throughput
> 
> Where as on my X370 my throughput has dropped considerably when moving from a 1:1 MCLK/FLCK ratio.
> 
> Your the second person who has posted amazing improvements in the time required for a "MemBench Easy Mode" score, where are these improvements coming from as there is no radical improvements in timings, so im at a loss to understand where all the performance gain is coming from.
> 
> Are you using a tweaked Windows OS ??



Not sure of the reasons why and I’m not using any Windows OS tweaks

I ran the same set up today and got the same results.

This earlier run at 3800c14 is closer in MEMbench with 96.27 but 35s quicker in TM5 

https://www.overclock.net/forum/attachment.php?attachmentid=364248&d=1596589176


----------



## treestar

I've got this, tested with prime95 large, Y-cruncher, TM5 multiple times. Tried to lower tRCDWR, tFAW, tWTRL, GDM off at 2T - too unstable. Are timings good, did I treat tRRDL fair?


----------



## mongoled

2600ryzen said:


> Just my opinion mainly from watching some of buildzoid's videos 2:1 memory overclocking.
> 
> https://www.youtube.com/watch?v=nugwAOvijHQ
> 
> https://www.youtube.com/watch?v=MDKQGLFqrS0


Thanks, will have a watch later on



glnn_23 said:


> Not sure of the reasons why and I’m not using any Windows OS tweaks
> 
> I ran the same set up today and got the same results.
> 
> This earlier run at 3800c14 is closer in MEMbench with 96.27 but 35s quicker in TM5
> 
> https://www.overclock.net/forum/attachment.php?attachmentid=364248&d=1596589176


Yeah, i saw that result, i was actually comparing your two results that are running 1:1 to see where you were able to shave almost 3 seconds off the time.

Than I saw your 2:1 benchmark and was very suprised that your throughput went up, I could not find prior results of people pushing non XT CPUs 2:1 and getting such high throughput.

It must be something in the XT CPU, that small changes to timings and increase to IF are showing performance improvements that scale higher than non XT CPUs.

Or there is some other weird anomoly going on.

Ideally I am not in the best position to judge as my results are also on X370, hoping some others users with XT CPUs who know who to tweak RAM aggressively can bring their results to the table so we can see if they are also seeing performance scaling more efficiently when tweaking timings/mclk/fclk


----------



## nick name

glnn_23 said:


> Not sure of the reasons why and I’m not using any Windows OS tweaks
> 
> I ran the same set up today and got the same results.
> 
> This earlier run at 3800c14 is closer in MEMbench with 96.27 but 35s quicker in TM5
> 
> https://www.overclock.net/forum/attachment.php?attachmentid=364248&d=1596589176


I guess it's just a more mature memory controller on the XT? Even at slightly faster speeds I don't see the same bandwidth numbers. As far as latency -- I imagine it's the fixed clock speeds. I also see better latency when I use a static clock speed.


----------



## nick name

glnn_23 said:


> Not sure of the reasons why and I’m not using any Windows OS tweaks
> 
> I ran the same set up today and got the same results.
> 
> This earlier run at 3800c14 is closer in MEMbench with 96.27 but 35s quicker in TM5
> 
> https://www.overclock.net/forum/attachment.php?attachmentid=364248&d=1596589176


Wait, I forgot what happens when I use a little BCLK too. Though your numbers are still better.


----------



## mongoled

nick name said:


> Wait, I forgot what happens when I use a little BCLK too. Though your numbers are still better.


Can you mirror his settings and run "membench easy" then post the result?


----------



## nick name

mongoled said:


> Can you mirror his settings and run "membench easy" then post the result?


I can try very similar settings. One thing my kit doesn't like is GDM disabled at lower speed so that will be one difference. I also can't do BCLK and set a fixed CPU speed.

How do adjust the amount of RAM to test down to 6000 like he did?


----------



## mongoled

Just run Membench using "Easy" option, thats all glnn_23 was running


----------



## nick name

mongoled said:


> Just run Membench using "Easy" option, thats all glnn_23 was running


Yeah, but my Easy shows RAM size at 12000 and not 6000 like his.

NVM figured it out.


----------



## mongoled

nick name said:


> Yeah, but my Easy shows RAM size at 12000 and not 6000 like his.
> 
> NVM figured it out.


Thats another great result,

I must be doing something wrong then


----------



## binder87

Hi all...i have a sammy b die flarex 3200 cl 14 kit and a newer batch [email protected] 1.3v manual oc. I have been running my memory @3600, fclk 1800 with the timings specified in the attached pic with no issues, vdimm @1.488v, vsoc. 1.1v. i can maybe get some of the timings tighter (not tcl and trcdrd, they'll instantly error on 14) , but im satisfied with these as well. I have been trying to run 3800 and 1900fclk @ 1.5 vdimm, 16-16-16-16-36-52, other secondary and tertiary timings are little looser than on the 3600. It was tm5 stable for 35 cycle, however, i get audio cracking and occasional headset drop (usb) when playing csgo , which is cpu and mem dependent. The more i raise vsoc, the less frequent it becomes. On 1.17 vsoc, it basically didn't happen at all anymore. Obviously my imc doesnt like 1900 too much. Is there anyway to surpass it? I know up to 1.2 vsoc is somewhat safe, but i dont feel so comfortable going past 1.15 or so for 24/7....also, when checking ryzen master for vddg voltage, its at 1.15 when on a high vsoc, which according to my understanding, isnt good. I only ran it for 2-3 days, so i guess no damage was done. I'm pretty lost here, any suggestions? Should i just settle for 3600 1800?


----------



## nick name

binder87 said:


> Hi all...i have a sammy b die flarex 3200 cl 14 kit and a newer batch [email protected] 1.3v manual oc. I have been running my memory @3600, fclk 1800 with the timings specified in the attached pic with no issues, vdimm @1.488v, vsoc. 1.1v. i can maybe get some of the timings tighter (not tcl and trcdrd, they'll instantly error on 14) , but im satisfied with these as well. I have been trying to run 3800 and 1900fclk @ 1.5 vdimm, 16-16-16-16-36-52, other secondary and tertiary timings are little looser than on the 3600. It was tm5 stable for 35 cycle, however, i get audio cracking and occasional headset drop (usb) when playing csgo , which is cpu and mem dependent. The more i raise vsoc, the less frequent it becomes. On 1.17 vsoc, it basically didn't happen at all anymore. Obviously my imc doesnt like 1900 too much. Is there anyway to surpass it? I know up to 1.2 vsoc is somewhat safe, but i dont feel so comfortable going past 1.15 or so for 24/7....also, when checking ryzen master for vddg voltage, its at 1.15 when on a high vsoc, which according to my understanding, isnt good. I only ran it for 2-3 days, so i guess no damage was done. I'm pretty lost here, any suggestions? Should i just settle for 3600 1800?


Hmmm, I didn't need that much SOC voltage to cure the same problem. 

Which motherboard are you using?


----------



## binder87

nick name said:


> binder87 said:
> 
> 
> 
> Hi all...i have a sammy b die flarex 3200 cl 14 kit and a newer batch [email protected] 1.3v manual oc. I have been running my memory @3600, fclk 1800 with the timings specified in the attached pic with no issues, vdimm @1.488v, vsoc. 1.1v. i can maybe get some of the timings tighter (not tcl and trcdrd, they'll instantly error on 14) , but im satisfied with these as well. I have been trying to run 3800 and 1900fclk @ 1.5 vdimm, 16-16-16-16-36-52, other secondary and tertiary timings are little looser than on the 3600. It was tm5 stable for 35 cycle, however, i get audio cracking and occasional headset drop (usb) when playing csgo , which is cpu and mem dependent. The more i raise vsoc, the less frequent it becomes. On 1.17 vsoc, it basically didn't happen at all anymore. Obviously my imc doesnt like 1900 too much. Is there anyway to surpass it? I know up to 1.2 vsoc is somewhat safe, but i dont feel so comfortable going past 1.15 or so for 24/7....also, when checking ryzen master for vddg voltage, its at 1.15 when on a high vsoc, which according to my understanding, isnt good. I only ran it for 2-3 days, so i guess no damage was done. I'm pretty lost here, any suggestions? Should i just settle for 3600 1800?
> 
> 
> 
> Hmmm, I didn't need that much SOC voltage to cure the same problem.
> 
> Which motherboard are you using?
Click to expand...

 a ****ty b350 gaming plus from 2017....still serves me well though. Well its obviously an imc issue as increasing soc helps.


----------



## nick name

binder87 said:


> a ****ty b350 gaming plus from 2017....still serves me well though. Well its obviously an imc issue as increasing soc helps.


Perhaps the board isn't as up to the task as you'd hoped.


----------



## Martin778

Could be both the board or the CPU having anough in terms of IF frequency. 3600 is perfectly adequate, I'd rather go 3600/1800 with nice and tight secondary timings.

On my TR the 3200 CL14 Royals wouldn't do more than 3733 CL14 but a better bin (3800 C14, probably the best?) do run 3733 14-15-15-30. Sadly my 3960X won't even POST @ 3800 IF.
Will pass TM5 @ 1usmus CFG but not with 30*C+ ambient, the sticks must have active cooling for mem benching.


----------



## binder87

nick name said:


> binder87 said:
> 
> 
> 
> a ****ty b350 gaming plus from 2017....still serves me well though. Well its obviously an imc issue as increasing soc helps.
> 
> 
> 
> Perhaps the board isn't as up to the task as you'd hoped.
Click to expand...

Than why would it pass all mem tests and increasing vsoc fixes the problem ?


----------



## Martin778

There is always a point when sillicon will start soaking voltage to remain stable, this can be that point.


----------



## glnn_23

mongoled said:


> Thats another great result,
> 
> I must be doing something wrong then


No I don't think you're doing anything wrong.

Today I tested same settings with 1 ccd then 2 ccd to see the difference.

1 ccd 100.16 
2 ccd 96.77


----------



## Keith Myers

rares495 said:


> I don't know. Binning probably plays a part in this as well.


I would think that this is the case also. After all back then, B-die was still in production and the number of dies to bin for excellent overclocking was much greater I assume. Compared to the limited B-die stock procured as NOS or whatever now.


----------



## mongoled

glnn_23 said:


> No I don't think you're doing anything wrong.
> 
> Today I tested same settings with 1 ccd then 2 ccd to see the difference.
> 
> 1 ccd 100.16
> 2 ccd 96.77


Thanks for that,

This accounts for most of the difference compard to single CCD CPUs, did not think the read speed would be effected in such a way.

The rest is probably down to the X370 chipset im using.


----------



## binder87

nick name said:


> binder87 said:
> 
> 
> 
> Hi all...i have a sammy b die flarex 3200 cl 14 kit and a newer batch [email protected] 1.3v manual oc. I have been running my memory @3600, fclk 1800 with the timings specified in the attached pic with no issues, vdimm @1.488v, vsoc. 1.1v. i can maybe get some of the timings tighter (not tcl and trcdrd, they'll instantly error on 14) , but im satisfied with these as well. I have been trying to run 3800 and 1900fclk @ 1.5 vdimm, 16-16-16-16-36-52, other secondary and tertiary timings are little looser than on the 3600. It was tm5 stable for 35 cycle, however, i get audio cracking and occasional headset drop (usb) when playing csgo , which is cpu and mem dependent. The more i raise vsoc, the less frequent it becomes. On 1.17 vsoc, it basically didn't happen at all anymore. Obviously my imc doesnt like 1900 too much. Is there anyway to surpass it? I know up to 1.2 vsoc is somewhat safe, but i dont feel so comfortable going past 1.15 or so for 24/7....also, when checking ryzen master for vddg voltage, its at 1.15 when on a high vsoc, which according to my understanding, isnt good. I only ran it for 2-3 days, so i guess no damage was done. I'm pretty lost here, any suggestions? Should i just settle for 3600 1800?
> 
> 
> 
> Hmmm, I didn't need that much SOC voltage to cure the same problem.
> 
> Which motherboard are you using?
Click to expand...

What did you do to solve it if i may ask?


----------



## nick name

Keith Myers said:


> I would think that this is the case also. After all back then, B-die was still in production and the number of dies to bin for excellent overclocking was much greater I assume. Compared to the limited B-die stock procured as NOS or whatever now.


Well another odd bit is that 3800MHz 15-15-15-15 1T GDM off is unstable yet 4200MHz 1T GDM off is stable.


----------



## mongoled

nick name said:


> Well another odd bit is that 3800MHz 15-15-15-15 1T GDM off is unstable yet 4200MHz 1T GDM off is stable.


On a BIOS reset, when you input your mclk/fclk do you go straight to 3800/1900 or do you go, say, 3200/1600 --> 3600/1800 --> 3800/1900 ?

If you input 3800/1900 straight away, try to increase in steps reboot --> increase again etc


----------



## nick name

mongoled said:


> On a BIOS reset, when you input your mclk/fclk do you go straight to 3800/1900 or do you go, say, 3200/1600 --> 3600/1800 --> 3800/1900 ?
> 
> If you input 3800/1900 straight away, try to increase in steps reboot --> increase again etc


I go straight to 1900 FCLK. No need not to.

I have an older kit that can do 3600 at 1T GDM off, but the new kits can't. 

Something about the new kits (whether it's PCB revision or something else) keeps them from behaving the same as the old in regards to GDM. 

The fact the my 4400C19 kit can't run 3800C15 with GDM off, but can run 4200C15 with GDM off confounds me.

Edit:

I figured it out. At 4200MHz it's not 1:1. I can run 3800 when it isn't 1:1. So it turns out to be the IMC?


----------



## infraredbg

Veii said:


> @infraredbg , ZenTimings
> if you can, please move tRFC ns before tRFC and write it fully out
> Real tRFCns on this picture is "126.3157895" @ 14400 tREFI
> Even if it would only use 3533.33333334MT/s the real tRFC is "135.849056603xxxx"ns also @ 14400 tREFI
> Can't get the last 4 digits correct as it's neither .3333333 nor .33333334
> Anyways, please at least for accuracy sake skip rounding (6-7 decimals should be accurate enough)
> or if possible read out MCLK factoring BLCK then *2 for correct MT/s
> 
> Overall tREFi looks to be wrong - else if it's correct the board messes something up with fixed tRFC, tRFC 2 , tRFC 4 :thinking:
> EDIT:
> Coming closer, real tRFC for 3534MT/s is around
> 135,8490566037735*X* ns
> but here i go back to overflow
> 
> 
> 
> 
> 
> 
> 
> 
> This is why we have rounding issues, and why rounding stacks



Does this look better?
Unfortunately there's not much space to show it in full and also the only thing that accounts for bclk is the configuredClockSpeed from WMI memory.
Even reading MCLK, FCLK and UCLK from bios, blck is always detected as ~100MHz.
I've included the full value as a tooltip for tRFC (ns), TRFC2 and TRFC4 and TREFI (ns).
Tried to make it as compact as possible, but adding a third column couldn't be avoided.


----------



## nick name

infraredbg said:


> Does this look better?
> Unfortunately there's not much space to show it in full and also the only thing that accounts for bclk is the configuredClockSpeed from WMI memory.
> Even reading MCLK, FCLK and UCLK from bios, blck is always detected as ~100MHz.
> I've included the full value as a tooltip for tRFC (ns), TRFC2 and TRFC4 and TREFI (ns).
> Tried to make it as compact as possible, but adding a third column couldn't be avoided.


Ayyy, look at you doing cool things. Well done.


----------



## Keith Myers

mongoled said:


> On a BIOS reset, when you input your mclk/fclk do you go straight to 3800/1900 or do you go, say, 3200/1600 --> 3600/1800 --> 3800/1900 ?
> 
> If you input 3800/1900 straight away, try to increase in steps reboot --> increase again etc


Only way to get to 3600 with 4 X 8GB on one host for me is to step up from 3200Mhz.


----------



## 2600ryzen

Keith Myers said:


> Only way to get to 3600 with 4 X 8GB on one host for me is to step up from 3200Mhz.



Do you have to do that every reboot? What agesa version does it have?


----------



## Keith Myers

No, once I get it ramped up it sticks unless I remove power from the power supply. Survives reboots fine as long as the computer stays powered.

I am still on the 3004 BIOS with the older AGESA whatever that was. I have no way of checking being on Linux.


----------



## KedarWolf

infraredbg said:


> Does this look better?
> Unfortunately there's not much space to show it in full and also the only thing that accounts for bclk is the configuredClockSpeed from WMI memory.
> Even reading MCLK, FCLK and UCLK from bios, blck is always detected as ~100MHz.
> I've included the full value as a tooltip for tRFC (ns), TRFC2 and TRFC4 and TREFI (ns).
> Tried to make it as compact as possible, but adding a third column couldn't be avoided.


Where can I get that beta of Zen Timings, please?


----------



## mongoled

nick name said:


> I go straight to 1900 FCLK. No need not to.
> 
> I have an older kit that can do 3600 at 1T GDM off, but the new kits can't.
> 
> Something about the new kits (whether it's PCB revision or something else) keeps them from behaving the same as the old in regards to GDM.
> 
> The fact the my 4400C19 kit can't run 3800C15 with GDM off, but can run 4200C15 with GDM off confounds me.
> 
> Edit:
> 
> I figured it out. At 4200MHz it's not 1:1. I can run 3800 when it isn't 1:1. So it turns out to be the IMC?


The reason i asked because on my MSI if I jump to 3800/1900 from BIOS defaults and key in all my know stable timings I will get error in TM5.

If I do it stepping up gradually I dont get these errors.

Its as if the MSI has some timings that are not visible to us that get applied "correctly" when the mclk/fclk is increased in steps.

See a similar thing when i use BCLK also, up to 101.7, PC will boot normally after this point I either get a double post, or post hangs and I have to hold power button down and power back upn then I can all the way up to my tested stable 107.5625



Keith Myers said:


> Only way to get to 3600 with 4 X 8GB on one host for me is to step up from 3200Mhz.


Maybe you could update your BIOS ?


----------



## nick name

mongoled said:


> The reason i asked because on my MSI if I jump to 3800/1900 from BIOS defaults and key in all my know stable timings I will get error in TM5.
> 
> If I do it stepping up gradually I dont get these errors.
> 
> Its as if the MSI has some timings that are not visible to us that get applied "correctly" when the mclk/fclk is increased in steps.
> 
> See a similar thing when i use BCLK also, up to 101.7, PC will boot normally after this point I either get a double post, or post hangs and I have to hold power button down and power back upn then I can all the way up to my tested stable 107.5625
> 
> 
> Maybe you could update your BIOS ?



I see. 

Yeah, I know what's stable on my board -- I just like trying to find other settings that are too. I always start from a point of stability before I explore the new bits though.


----------



## Keith Myers

mongoled said:


> The reason i asked because on my MSI if I jump to 3800/1900 from BIOS defaults and key in all my know stable timings I will get error in TM5.
> 
> If I do it stepping up gradually I dont get these errors.
> 
> Its as if the MSI has some timings that are not visible to us that get applied "correctly" when the mclk/fclk is increased in steps.
> 
> See a similar thing when i use BCLK also, up to 101.7, PC will boot normally after this point I either get a double post, or post hangs and I have to hold power button down and power back upn then I can all the way up to my tested stable 107.5625
> 
> 
> Maybe you could update your BIOS ?


I'm loathe to fix what isn't broken. Not much information, other than generalities that I can apply, gathered in the OCN forums because every user other than myself uses Windows and has access to all the tools you quote so often. I have spent many an afternoon just trying to get anything past 3600 GDM off 1T CL14 working on my Trident Z F4-3200D-8GTZ B-dies. Never have even got close with errors on anything > 3600Mhz.

So for my use case of no gaming and only distributed computing, that is good enough. 3600 works for me.


----------



## nick name

Keith Myers said:


> I'm loathe to fix what isn't broken. Not much information, other than generalities that I can apply, gathered in the OCN forums because every user other than myself uses Windows and has access to all the tools you quote so often. I have spent many an afternoon just trying to get anything past 3600 GDM off 1T CL14 working on my Trident Z F4-3200D-8GTZ B-dies. Never have even got close with errors on anything > 3600Mhz.
> 
> So for my use case of no gaming and only distributed computing, that is good enough. 3600 works for me.


Are they an older or newer kit of b-die? Do you know the PCB version?


----------



## Keith Myers

nick name said:


> Are they an older or newer kit of b-die? Do you know the PCB version?


Older from several years ago. 2018. Have no clue what PCB version they are.


----------



## nick name

Keith Myers said:


> Older from several years ago. 2018. Have no clue what PCB version they are.


Sorry, I'm asking for my own curiosity. My older b-die (from 2018) can do 3600C14 1T GDM off, but my new kits can't. And the only visual difference is the PCB.

On top of that -- I've seen those that do have kits that do 3800C14 1T GDM off, but appear to be inferior bins to what I have. So it's something I can't figure out. Though now that I'm saying it out-loud it might be other factors. Like mobo and IMC. As my best kit confused me doing 1T GDM off at higher speeds, but not lower until I realized that it did that when things weren't 1:1. And at lower speeds at not 1:1 will do the same. So that seemingly points to the IMC. And maybe mobo?


----------



## Veii

chitos123 said:


> @*Veii*
> Fixed IF tCL-tCWL=Negative AND tRCD_RD ODD
> -> then tRD_WR calculation A=B (A|B)
> (Before it drop beyond -1)


IF tRCD_RD = ODD, = tRDWR /2 (+1 rounded up)
IF tRDWR /2 = odd, round up ~ or round down + use tWRRD delay


> Add ruleset of DR
> now min tRTP in DR is 8!


:thumb:


> Oh. i Was completely wrong SD,DD
> 155177 is more performance
> 
> SD,DD value Fixed


:thumb:
unsure if 1-6-6-1-8-8 would work 
It's "added delay" but more gives better perf
Unclear topic so far ~ 1usmus has more information 


> Rework all layout
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> https://docs.google.com/spreadsheet...V3BjdL-dcfJJeyhdSAoJmuzJE/edit#gid=1100326422


Some parts are still very very complicated.
It's the order that messes you up.
Compare our order and what you see on Zen Timings, vs yours


Spoiler














It's good & accurate intention to sort it to the links, but it's confusing for the user 
Even when i know my set, sadly i couldn't replicate it on the calculator.
I think the key reasons where:
- tRAS was wrong, because it doesn't use anymore AVG tRCD delay.
going with tRCD_WR can be too low, going with tRCD_RD is better. Lower option is avg delay of both or just tRP
- enforced tRP couple of times, but tRCD didn't change, and tWR didn't change.
i think you could give the user the ability to pick from tRFC multipliers which depend at the end on the voltage and user kit (rank amount and IC manufacture).
Unless i knew what to look for, i couldn't count on the results. They where too low to begin with
- it took me a lot of time and manual writing out, to figure out tRC as "additional input". Took time till i check why tRAS is strange. Manual set tRC didn't apply 


> I have a question
> 
> When will this formula be established?, Disable GDM?
> [ If "2x DR" then tWR and tRDWR are "2x SR"*2 ]


Kits exclusive, Dual Rank memory doesn't have to have high tRFC, they still work well with *7 or even *8
What they do need sometimes, is double tWR ~ double of the SR ruleset, just double 

If we used tRCD *7, soo tWR clean divider is 14, then Big capacity dual rank need 28 as tWR
tRAS won't need to change when tWR is that high. Same when tRTP is 8 or 9 , tWR still can be just 10 or 12 instead of 16,18 
tRP *2 = tWR is not always needed, it's recommended, but not crucial



> But i can't find "8,15"
> And not sure about error 5
> 
> What value is the problem for these errors ?


Error 15 is again a mirror move error but a bigger size one ~ 128mb
Error 5, 14 are identical just at a different "position" 
Error 4,15 are the same with bigger data-size 
Would suspect for 4,14 more tRDWR/tWRRD 
while for bigger datasets tRP, tRFC

Burst SimpleTests size 4,8mb [#9,10]
suspect tWR being too slow
Burst Simple Test size 2mb [#7]
suspect vDIMM to be +/- 1 step too high/low, tFAW be awkward value, or tRAS needing +1
Simple Test 0mb crashes [#8]
suspect tRRD_ & tWTR_ 
^ same ruleset goes for "RefreshStable" 0Mb tests [#0]
Nearly always tRRD_ & tWTR_ but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC)
Remain big dataset tests are mostly primaries


----------



## Veii

treestar said:


> I've got this, tested with prime95 large, Y-cruncher, TM5 multiple times. Tried to lower tRCDWR, tFAW, tWTRL, GDM off at 2T - too unstable. Are timings good, did I treat tRRDL fair?


If your kits allow tRRD_L to be that low (inside same bank), then adjust tWTR_L to *2 , for example 8
tWRRD = x * 4 = equal or < of tRCD_WR. 
X= 4 * 4 = 16 = tRCD_WR. 3 is not enough here 
Dual Rank kits like SD, DD's of 1-4-4-1-6-6 instead of 1-5-5-1-7-7 more, or are this 4x SR ?
cLDO_VDDP = 925 
cLDO_VDDG = 1025 (2* 50mV stepping)
vSOC = 1075 (75mV stepping ~ please decide in one)

If your board is low quality, you can keep VDDG IOD to 1025, and drop VDDG CCD to 975
That would put VDDG in reality to 1000mV (avg) and vSOC of 1075mV works as 75mV stepping across all 3
ProcODT you might want to try to lower to 38/39Ω


binder87 said:


> Hi all...i have a sammy b die flarex 3200 cl 14 kit and a newer batch [email protected] 1.3v manual oc. I have been running my memory @3600, fclk 1800 with the timings specified in the attached pic with no issues, vdimm @1.488v, vsoc. 1.1v. i can maybe get some of the timings tighter (not tcl and trcdrd, they'll instantly error on 14) , but im satisfied with these as well. I have been trying to run 3800 and 1900fclk @ 1.5 vdimm, 16-16-16-16-36-52, other secondary and tertiary timings are little looser than on the 3600. It was tm5 stable for 35 cycle, however, i get audio cracking and occasional headset drop (usb) when playing csgo , which is cpu and mem dependent. The more i raise vsoc, the less frequent it becomes. On 1.17 vsoc, it basically didn't happen at all anymore. Obviously my imc doesnt like 1900 too much. Is there anyway to surpass it? I know up to 1.2 vsoc is somewhat safe, but i dont feel so comfortable going past 1.15 or so for 24/7....also, when checking ryzen master for vddg voltage, its at 1.15 when on a high vsoc, which according to my understanding, isnt good. I only ran it for 2-3 days, so i guess no damage was done. I'm pretty lost here, any suggestions? Should i just settle for 3600 1800?











Please retest  
The set was awkward to begin with 


> Obviously my imc doesnt like 1900 too much. Is there anyway to surpass it?


Decreasing voltage is the way
Decreasing all 3 voltages including procODT as low as you can go
Voltage examples:
https://www.overclock.net/forum/18051-memory/1746444-oc-ing-t-force-4133-cl18.html#post28424814

Audio crackles exist because of voltage, often too much instead "not enough" voltage 
Mostly this happens because of procODT and either too high vSOC or too high procODT and low vSOC, depends 
If you put VDDG to 1.15 which is far to much, then minimum vSOC it can use is 1.2 - while it could happen that it overvolts too
You can use excessive SOC voltage if you really want, but keep VDDG and cLDO_VDDP lower, for the health of the IMC and fabric
On low end boards you can push VDDG IOD to fix random PCIe crashes, or sound issues.
Pushing SOC without reason, is not the way to go - it should only be pushed if you need to mask high voltages, or to create heat under exotic cooling envoirements
Fabric's heat still remains the biggest heat creator, it's not the cores anymore


infraredbg said:


> Does this look better?
> Unfortunately there's not much space to show it in full and also the only thing that accounts for bclk is the configuredClockSpeed from WMI memory.
> Even reading MCLK, FCLK and UCLK from bios, blck is always detected as ~100MHz.
> I've included the full value as a tooltip for tRFC (ns), TRFC2 and TRFC4 and TREFI (ns).
> Tried to make it as compact as possible, but adding a third column couldn't be avoided.


I see
I think people would start to be worried about that "variable" MCLK, FCLK, UCLK ~ haha
It's good to have it 
Also great work ~ very very useful ! :thumb:
just hope another PSP firmware update won't kill RTT readout  
Speaking of, is this AGESA 1005/1006 with the new update ?
Do you think , you can somehow request from FIT the current variable VDDG ? the exact split in IOD and CCD ?
I think it lacks a sensor, but FIT should be aware of what is applied :thinking:

One little note, 
Unless vSOC is variable on your side and not fixed at 1v, please drop cLDO_VDDP under VDDG at least 50mV if not more
I don't think VDDP of 700mV would cause issues for you, unless really SOC messes me up and it's not at constant 1v but variable :thinking:

On another sidenote,
You are correct, it does get bulky 
I have an idea how to keep it 2 rows, or at least shrink it down a bit 
Will update once my bad photoshop skills create something useful 
Also ty for the tRFC(ns) movement, now only tCKE position is bothering it to be symmetrical 
Can you try to get tMRD*PDA* and tMOD*PDA* also in there for comparison 
I think that's it then. 
Somehow tSTAG remains awkward, but except memory ban'ing (tRDRDBAN & tWRWRBAN) we should have everything ever needed from a readout tool
PHY data is interesting for the future (PHYWRD, PHYWRL, ,PHYRDL) if we start to play with PMU settings. But for now not relevant 
EDIT:
Memory banning we can't adjust anyways, and PHY data remains to be checked how useful it is
Soo it's not needed atm


----------



## chitos123

@*Veii* 


Veii said:


> Spoiler
> 
> 
> 
> IF tRCD_RD = ODD, = tRDWR /2 (+1 rounded up)
> IF tRDWR /2 = odd, round up ~ or round down + use tWRRD delay


Fixed Perfect to +1




> Spoiler
> 
> 
> 
> unsure if 1-6-6-1-8-8 would work
> It's "added delay" but more gives better perf
> Unclear topic so far ~ 1usmus has more information


What about 4x SR alt? 4466 or 6688, Rec is 5577
(2x, 4x DR is 4466,5577)



> Spoiler
> 
> 
> 
> Some parts are still very very complicated.
> It's the order that messes you up.
> Compare our order and what you see on Zen Timings, vs yours
> 
> 
> Spoiler
> 
> 
> 
> https://0x0.st/i3hB.png
> 
> 
> It's good & accurate intention to sort it to the links, but it's confusing for the user
> Even when i know my set, sadly i couldn't replicate it on the calculator.
> I think the key reasons where:
> - tRAS was wrong, because it doesn't use anymore AVG tRCD delay.
> going with tRCD_WR can be too low, going with tRCD_RD is better. Lower option is avg delay of both or just tRP
> - enforced tRP couple of times, but tRCD didn't change, and tWR didn't change.


Change Test 0,3 to tRCD =(RD+WR)/2
=This Wrong thought from "tRCD_RD >= tRCD_WR"


Looking at your quote, It's different from the rules I used to know
"tRCD_RD >= tRCD_WR" -> "tRCD_RD


----------



## rent0n

Since I got no answer in the IF thread - here - I'm going to ask the same question in this thread: has anyone had any luck pushing Samsung B-Dies to 3800MHz CL12 on a B450 board? I have a F4-3600C16D-16GVK Kit, July 2020. According to Thaiphoon each module has an A1 10-layer PCB, but I'm pretty sure it's an A2 layout, so that reading should be wrong. I am running a Ryzen 5 3600, which can go as high as 4.6-4.7GHz on air for benchmarking and so far the memory sticks have been running at 3800MHz (1900MHz FCLK) 14-14-14-28-1T-42-260, GDM off. I haven't had any luck booting at CL12 for a benchmark even with GDM enabled and voltages between 1.65V-1.8V, so I'm thinking either the bin of the kit is not that good, or the mainboard is just bad at memory overclocking, it's only a MSI B450 Tomahawk MAX. If anyone has any experience or suggestions, I would be glad to hear them.


In addition:

1.1. - I managed to boot at CL12, but tRFC has to be above 400 in order for it to work, which results in worse latency and reads
1.2. - for me the AGESA 1.0.0.6 made little to no difference regarding memory OC

Edit: Going to attach a screenshot with my settings later today.


----------



## infraredbg

Veii said:


> I see
> I think people would start to be worried about that "variable" MCLK, FCLK, UCLK ~ haha
> It's good to have it
> Also great work ~ very very useful ! :thumb:
> just hope another PSP firmware update won't kill RTT readout
> Speaking of, is this AGESA 1005/1006 with the new update ?
> Do you think , you can somehow request from FIT the current variable VDDG ? the exact split in IOD and CCD ?
> I think it lacks a sensor, but FIT should be aware of what is applied :thinking:


I have dumped all the possible values in the PM Table, but could not find a separate IOD and CCD. Thought I've found it at first, but that value stays fixed and doesn't change when I tweak VDDG voltages.
I'm testing on Crosshair VI Hero with latest bios (AGESA 1.0.0.6). It's possible to add those other values you've requested.
Currently there's a problem with first launch of the app after a reboot which I'm trying to solve.


----------



## nick name

rent0n said:


> Since I got no answer in the IF thread - here - I'm going to ask the same question in this thread: has anyone had any luck pushing Samsung B-Dies to 3800MHz CL12 on a B450 board? I have a F4-3600C16D-16GVK Kit, July 2020. According to Thaiphoon each module has an A1 10-layer PCB, but I'm pretty sure it's an A2 layout, so that reading should be wrong. I am running a Ryzen 5 3600, which can go as high as 4.6-4.7GHz on air for benchmarking and so far the memory sticks have been running at 3800MHz (1900MHz FCLK) 14-14-14-28-1T-42-260, GDM off. I haven't had any luck booting at CL12 for a benchmark even with GDM enabled and voltages between 1.65V-1.8V, so I'm thinking either the bin of the kit is not that good, or the mainboard is just bad at memory overclocking, it's only a MSI B450 Tomahawk MAX. If anyone has any experience or suggestions, I would be glad to hear them.
> 
> 
> In addition:
> 
> 1.1. - I managed to boot at CL12, but tRFC has to be above 400 in order for it to work, which results in worse latency and reads
> 1.2. - for me the AGESA 1.0.0.6 made little to no difference regarding memory OC
> 
> Edit: Going to attach a screenshot with my settings later today.


The only time I can remember anyone using CL12 was during one of Bearded Hardware's videos. He, though, was leaving much of the other timings on Auto (including tRFC). So I think it's likely as you've discovered -- you need a higher tRFC to reach such a low CL. 

I haven't been able to boot CL12 either on my 3600C15 or 4400C19 kit. I didn't back off tRFC in my attempts.


----------



## rent0n

nick name said:


> The only time I can remember anyone using CL12 was during one of Bearded Hardware's videos. He, though, was leaving much of the other timings on Auto (including tRFC). So I think it's likely as you've discovered -- you need a higher tRFC to reach such a low CL.
> 
> I haven't been able to boot CL12 either on my 3600C15 or 4400C19 kit. I didn't back off tRFC in my attempts.



buildzoid did manage to reach similar or even better settings in his 



 of the X570 Taichi's memOC capabilities, but I guess there is no room for comparison between that motherboard and mine. Furthermore, he used a 3700X. I've also seen some HWBOT submissions with a Zen 2 and 3800/CL12 B-Dies, but no details on all the settings. I have tried raising the ProcODT and the ClkDrvStren-CkeDrv, same results. The reason I asked is mainly because I'm not familiar with all the secondary and tertiary timings, and had the feeling I might be able to boot at CL12 after tweaking some settings.


----------



## nick name

rent0n said:


> buildzoid did manage to reach similar or even better settings in his preview of the X570 Taichi's memOC capabilities, but I guess there is no room for comparison between that motherboard and mine. Furthermore, he used a 3700X. I've also seen some HWBOT submissions with a Zen 2 and 3800/CL12 B-Dies, but no details on all the settings. I have tried raising the ProcODT and the ClkDrvStren-CkeDrv, same results. The reason I asked is mainly because I'm not familiar with all the secondary and tertiary timings, and had the feeling I might be able to boot at CL12 after tweaking some settings.


You could try this:


----------



## rent0n

nick name said:


> You could try this:



I'm already sitting on 61.9ns, but I'm going to check your settings out and see if I missed something. Cheers! )


----------



## nick name

rent0n said:


> I'm already sitting on 61.9ns, but I'm going to check your settings out and see if I missed something. Cheers! )


It's like you said -- the higher tRFC makes the lower CL moot.


----------



## Veii

chitos123 said:


> @*Veii*
> What about 4x SR alt? 4466 or 6688, Rec is 5577
> (2x, 4x DR is 4466,5577)


4x SR works well with 1-4-4-1-6-6, but that was computerbase testing
Both deliver good results, keep 4-4-6-6 for 4 dimms or 2x DR. 
Will update once i see better reasons, it needs testing across the whole range with SiSoftware Sandra Multi-Core effiency test (latency curve)



> Change Test 0,3 to tRCD =(RD+WR)/2
> =This Wrong thought from "tRCD_RD >= tRCD_WR"
> 
> Looking at your quote, It's different from the rules I used to know
> "tRCD_RD >= tRCD_WR" -> "tRCD_RD


----------



## Veii

Uhm 3600 CL14 requires around 1.42v
CL13 around 1.56v
CL12 around 1.68-1.73v

3800 CL14 ~ 1.48-1.52v
CL13 ~ 1.6
CL12 ~ 1.72-1.76v
1.8 looks "reasonable" 
Aroun 1.7~ is about the range for CL12, if your B-Die doesn't get unstable after 1.56v

Hynix MFR 3200 CL15 ~ 1.48v
CL14 ~ 1.56v
3400MT/s CL14 ~ 1.62v


----------



## betam4x

I bought some Micron E-Die CL18 DDR4 3600, does anyone know how well the chip performs/if timings can be tightened? Thinking about putting the hynix RAM in my wife's computer since my motherboard doesn't play all that nice with it.


----------



## SneakySloth

@Veii


Any idea what could be causing windows hardware errors? Specially, Cpu Bus/Interconnect WHEA error. I'm guessing that has something to do with both the VDDG voltages? I was getting them very early in Karhu before with cache enabled (before 10,000% coverage), changing the VDDG & VDDP voltages alongside the ClkdrvStren made them appear only in very long runs of Karhu.


I'm now getting a single error when running long stress tests e.g. I'd run Karhu for hours and only see 1 WHEA CPU Bus error at around 30,000 coverage always. My last run went all the way up to 45000% coverage with no errors in Karhu but instead a single WHEA error in Hwinfo.

I've done multiple karhu runs over the last day and all of them show a single WHEA error at around 25-30k coverage. All this is with cache enabled.

I have not been able to replicate these errors with both prime95 blend and y-cruncher with all tests enabled. Ran both for 2-3 hours each.


I've changed the VDDP and VDDG voltages again and currently I'm doing a TM5 run of 50 cycles and I'll see if I get any errors there. After that I'll run karhu again overnight to see if the errors appear in that or not.


Current Settings:
VDIMM = 1.49

VDDP = .900
VDDG_CCD = 950
VDDG_IOD = 1000
VSOC = 1.1 (with auto LLC, droops to 1.087/1.081).
ProcODT = 28.2 ohms
CAD_BUS = 40-20-20-24
RAM = Patriot Viper 4400 2x8GB


----------



## chitos123

@*Veii*



Veii said:


> Spoiler
> 
> 
> 
> 4x SR works well with 1-4-4-1-6-6, but that was computerbase testing
> Both deliver good results, keep 4-4-6-6 for 4 dimms or 2x DR.
> Will update once i see better reasons, it needs testing across the whole range with SiSoftware Sandra Multi-Core effiency test (latency curve)


[/SPOILER][/QUOTE]
Tested 1-5-5-1-7-7 1-6-6-1-8-8 in 2x SR and .. (I don't know difference  but,) slightly improved performance
Does Lower SD,DD is more stability ? (like 1-3-3-1-5-5)



> Spoiler
> 
> 
> 
> tRP timing is very variable, up to how much VDIMM you give
> GDDR6 (micron and samsung, both identical) and DRR4 use tRP +1 of tRCD, to cover for recharge
> But cells discharge Time depends on heat, voltage amount, cell quality, PCB quality
> You can only estimate it, where at best it is always = highest tRCD ~ covering highest delay.
> Meaning, it will pause and let this time elapse for recharge, the shorter tRP ~ the higher the chance of not enough charge and data "corruption"
> Higher heat increases discharge, but higher VDIMM increases overall charge. Too high vDIMM will overcharge anything above rated 1.35v will overcharge. Soo sometimes less is better
> If you freeze it, it will accept higher charge, if cells are hot they will leak voltage faster ~ only way to "degrade" memory
> 
> By this same principle i use average tRCD delay on the whole picture.
> tRP = tRCD_WR is the absolute minimum = correct
> BUT, this works only for short time and will someday choke because tRCD_RD difference can be big. People push tRCD_RD to cover for slower IC. Pushing tRCD_WR down is an AMD exclusive thing, and technically identical to pushing only one tRCD down = average tRCD
> Using average tRCD for tRP as baseline is a good method.
> Later you still can lower tRP if you overvolt it further or increase Impedance to lower tRC
> 
> Just as 1usmus mentioned, tRC is also AMD exclusive and a "time arrangement"
> We use tRC to cheat and finetune perf a bit, but mostly because i use tRFC Discharge ETA formula, which requires accurate tRC for it to work.
> all goes around average delay, autocorrection will happen anyways it tRC is too short or tRFC is too low (tRFC will be postpone)
> 
> Please do, this is better . tRCD_WR=tRP will work once, but very likely will drop out after long testing sessions. Ruleset baseline is = tRCD (not WR) or +1. GDDR6 uses +1


Changed tRP =tRCD AVG,MAX or tCL
And added +1 option

+All tRCD using value is now tRCD AVG

Anyway, what is that "amazing IC" ?
does tRCD_WR>tRCD_RD are better performance and stability in this IC ?



> Spoiler
> 
> 
> 
> you can use avg RCD delay also for tWRRD.
> i always use 4* X = < Avg tRCD delay.
> Same should apply to intel:
> tRRDD, result < or = 4*X of tRCD.
> need to check the intel thread for testing rabbits to check tRRDR (tRDWR) and tRRDD (tWRRD)
> But if result is > tRCD_RD it will not post. It also makes issues if you end up with tRDWR 9 and tWRRD 6, only one can be high not both.
> SCL for multiplier sometimes works sometimes doesn't on tWRRD. Rule of thumb is 4* X = < tRCD
> (which RCD you use depends, avg works well so far. Wrong value only will prevent post)


Now can select tRCD_WR, tRCD AVG to calculate tWRRD
but, IF tRCD_WR>tRCD_RD then "tRCD_WR" will be disabled

about tRCD AVG > tWRRD*4 
this work tRCD AVG > tWRRD*2 too?

I put it in the calculator, but I'm not sure it's working(Except 2x SR.)



> Spoiler
> 
> 
> 
> X is not tRTP
> tRTP has to be inside tRFC range, as clean divider, because tRFC can be moved around and postponed 9 times inside whole tREFI range.
> tRFC is a fixed delay, but when it will trigger is variable.
> Soo i use exact timing of tRC with *6 according to this discharge graph
> 
> ~ cloned from Donghyuk Lee's DDR Heterogeneity Research Paper
> *6 works well on Single Rank. i've seen people rarely get *7 to work
> My focus is half tCL delay, but sometimes result get in half decimal.
> tRFC is a big topic and i need more research into it getting *5 + tSTAG to work
> 
> tRTP and tWR have to be inside tRFC range as clean dividers. tRFC size doesn't matter much
> Both either are rounded up to even values with GDM, or are odd values without GDM.
> Exact divider is more important here, maximum down to half divider (XX.5 value)
> This means, even when tRFC is postponed on timings error or heat discharge issue, it won't crash because it remains still accurate after being postponed.
> Just baseline ruleset, but not key ruleset
> tWR = tRTP *2 is the same thing, clean divider is more important, *2 of tRTP not so much - they can be uneven as long as they are clean dividers
> Only goal is that when tRFC get's shifted, it remains accurate and the user doesn't only go for lowest possible latency.
> Too much autocorrection happens to predict every scenario, this is the reason for my ruleset. tWR calculation ruleset are accurate, all of them
> 
> Here something fast to get both correct:
> tRFC ~ =((tRCns*X)*MT/s)/2000
> tWR ~ =tRFC/(tRC/2)
> tRTP ~ =tWR/2 or just =tRFC/tRC
> EDIT: non of this math seems to work for custom tRFC 288 on CL14-tRC42 from DRAM calculator. But Yuri also use tRTP 8 which is a clean divider, same as tWR 12 is a clean divider


"X is not tRTP"
Now I finally took a tiny one step 

But seriously. 
The more i learn, the more i wonder XD

Have a question, 
Does more then tRC*8 =tRFC acceptable, or There is other calculated value?

In samsung C,D or Micron, their tRFC will be more then 300ns
= tRC*8+ is Necessary

Added tSTAG for testing.
But, not sure i calculated correct "tSTAG" value

And, does tRC*x+tSTAG is calculated value ?
Currently tSTAG SR, (tSTAG*2 DR ??)

To quote what you said

"tRC is also a fixed delay but a scalable" 
So all tRFC will work but,

"Accuracy of tRFC remains important when you want a clean transition"
->like "tRC*6" value

Then, back to square one.

Important is to figer out "Ryzen DRAM calculator" value, again and again !
which is only 1usmus know, as you said 



> Spoiler
> 
> 
> 
> I use 2 rulesets atm:
> Main rule is clean divider of tRFC_
> (there can be many results, 4-5 including 4 decimal one like .5=1/2, .25=1/4, .625=1/8th, .8175=1/16th results)
> Reason for this is that tRFC on it's own can go down to 1/32th accuracy. On 32 tRFC = value, as negative of positive steps
> 2nd rule is:
> Trying to match up tRAS by going tCL+tWR+tBL (2) according to Donghyuk Lee Research and "cheating" method for lowering tRAS
> result still can be 2 values as options (optional)
> 3rd rule if still options are left
> tRTP*2, but high tWR shows shows big stability impact.
> Rule 3 is only used for baseline calculation but often if you have tRTP 8, you can use either tWR 16 or 12. Then i strongly prefer 12 because the perf impact is big, and because i want tRAS low
> (baseline calculation ~ still trying to figure out 1usmus's method of tRCD+tBL)
> 
> Never used tCWL for this math, i don't know i'm sorry.
> tRP = RCD biggest value (stability)
> tRP = avg tRCD value if you tRCD_WR is < than tRCD_RD
> using always avg RCD as tRP makes it always correct. Using only tRCD_WR = tRP will make issues after time, because of cells discharge by heat. Manual tRP should be an option till we have a big dataset of how much VDIMM requires which IC before discharge issues happen


I tried changing it a little bit
But adding more stuff, Caused more harder to recognize XD



Spoiler














https://docs.google.com/spreadsheet...V3BjdL-dcfJJeyhdSAoJmuzJE/edit#gid=1100326422



> Spoiler
> 
> 
> 
> Cup arrived, was in a coffee shop to process all mentions before you send it
> seeing it slowly as daily work haha
> 
> Atm i save for an ITX B550 board, but they all are expensive (150-180€)
> Maybe middlestep will be biostar, but ugh i don't want to work on their bios
> Soo my eyes are on the Phantom Gaming ITX/AX, as the Impact is too expensive


I really want the B550I Arous PRO AX

Waiting for the price to go down 
But, only time can solve it :asleepysm


----------



## 2600ryzen

betam4x said:


> I bought some Micron E-Die CL18 DDR4 3600, does anyone know how well the chip performs/if timings can be tightened? Thinking about putting the hynix RAM in my wife's computer since my motherboard doesn't play all that nice with it.



Here's my timings for 3600mhz, my kit is cl16 3600mhz though so trcd rd and trc and a few other timings might be slightly different.


----------



## nick name

The bandwidth is garbage, but the latency is unbeatable.


----------



## acrvr

Hello


I recently acquired a nice Teamgroup ARGB Ram rated at 4000C18 with new Samsung B-dies (July 24 2020 according to Thaiphoon), and been trying to run 3600MHz C13 timings. At DRAM voltage of 1.55 it's been running quite well when I test it playing a few games of COD Warzone. Superb FPS, no crashes. It does have error problems if I run Memtest or TM5 anta777. I have been reading this thread and others on RAM overclocking to try to eliminate those errors but have not made any significant progress. 



Can anyone point me to what I should be checking for? I am very new at memory overclocking. 



CPU is Ryzen 3600 @ 4.4
Motherboard is MSI B550 A PRO
Memory is Teamgroup ARGB 4000C18
Windows 1909



Thank you


----------



## glnn_23

I have been comparing memory at 3828c14 to 4096c15

C8HW, 3900xt, Team Dark Pro 3600c14

These are the results so far

SuperPI 32M
3828c14. 8m 27.388s 
4096c15. 8m 27.773s


----------



## nick name

acrvr said:


> Hello
> 
> 
> I recently acquired a nice Teamgroup ARGB Ram rated at 4000C18 with new Samsung B-dies (July 24 2020 according to Thaiphoon), and been trying to run 3600MHz C13 timings. At DRAM voltage of 1.55 it's been running quite well when I test it playing a few games of COD Warzone. Superb FPS, no crashes. It does have error problems if I run Memtest or TM5 anta777. I have been reading this thread and others on RAM overclocking to try to eliminate those errors but have not made any significant progress.
> 
> 
> 
> Can anyone point me to what I should be checking for? I am very new at memory overclocking.
> 
> 
> 
> CPU is Ryzen 3600 @ 4.4
> Motherboard is MSI B550 A PRO
> Memory is Teamgroup ARGB 4000C18
> Windows 1909
> 
> 
> 
> Thank you


Have you tried increasing tRCDRD by 1?


----------



## speed_88

Any advice would be much appreciated

3733MHz 1.4v
SOC 1.1v
VDDG CCD 0.975v
DDG IOD 1.025v
CLDO VDDP 900v
TM5 0 erros 20 Cycles





















*Thaiphoon burner*


----------



## acrvr

nick name said:


> Have you tried increasing tRCDRD by 1?


Thanks. I tried increasing tRCDRD by 1 and then by 2. It got better, but still not free from errors. 

I'm thinking maybe I just need a better motherboard.... Idk


----------



## SneakySloth

So I think I've finally managed to get a stable overclock on both the Ram and the CPU. I know I can push the ram further but I didn't notice any difference in benchmarks and real world performance with tighter timings so these are good enough for me. Current voltages:
vDIMM = 1.49v
VSoc = 1.1v SET, 1.087v GET (idle and normal usage), 1.081v GET under stress testing
VDDP = 0.900v
VDDG_IOD = 1.00v
VDDG_CCD = 0.95
ProcODT = 28.2
CAD Bus Drive Strength = 40-20-20-24
Ram = Patriot Viper 4400 16GB


Stress Tests:
1. Karhu Ram Test = 43777% coverage
2. TestMem 5 1usmusv3 config = 50 cycles
3. Prime95 Large FFts = 4 hours
4. Y-cruncher - All tests enabled = 11 cycles
5. Realbench 2.43 = 6 hours - No Whea errors

*AIDA Results:*


Spoiler


----------



## acrvr

I'm trying to follow the guide that 1usmus wrote on techpowerup and I don't understand why he suggested to add to the timings on the debugging stage. Unless he miswrote the previous paragraph: 







> In half the cases, you can get a fully stable system at this stage. If the TM5 0.12 test package does not find errors, increase the range of test programs to check for stability. These can include Linx, HCI, Karhu, and other programs. If none of those programs find an error, continue to the next step—the debugging.


----------



## chitos123

I'm completely at a loss how to calculate *tSTAG* and *tREF* 
Anyone know about this. Please teach me


tSTAG



Spoiler

















tREF



Spoiler














 
https://docs.google.com/spreadsheet...JV3BjdL-dcfJJeyhdSAoJmuzJE/edit#gid=283210006


----------



## nick name

This setup wasn't stable enough for Chrome, but was enough for Aida. I was chasing 70000 MB/s Copy in Aida and finally hit it. Took me a while. I set 1.73V to boot and then upped it a little when I increased BCLK in Windows with TurboV.


----------



## rares495

nick name said:


> This setup wasn't stable enough for Chrome, but was enough for Aida. I was chasing 70000 MB/s Copy in Aida and finally hit it. Took me a while. I set 1.73V to boot and then upped it a little when I increased BCLK in Windows with TurboV.


Heh. Copy is the least important thing about Aida64. It basically pulls that number out of its a$$. Sometimes it's higher than the theoretical maximum bandwidth of a given frequency.


----------



## nick name

rares495 said:


> Heh. Copy is the least important thing about Aida64. It basically pulls that number out of its a$$. Sometimes it's higher that the theoretical maximum bandwidth of a given frequency.


Jesus, man. All you ever seem to do is ***** on people's parades.


----------



## rares495

nick name said:


> Jesus, man. All you ever seem to do is ***** on people's parades.


Heh, sorry about that.


----------



## Streetdragon

Even read and write are impressive! And the latency is low too! Nice nice

edit: Now CL14!


----------



## nick name

Streetdragon said:


> Even read and write are impressive! And the latency is low too! Nice nice
> 
> edit: Now CL14!


Are you talking to me?


----------



## rares495

nick name said:


> Are you talking to me?


----------



## Streetdragon

rares495 said:


> Heh, sorry about that.


sure^^


----------



## Eder

Having a great time with new dual rank kit. Just passed 20 cycles TM5 with 1.5v on the sticks.


----------



## rares495

Eder said:


> Having a great time with new dual rank kit. Just passed 20 cycles TM5 with 1.5v on the sticks.


Nice! Time to make it all unstable again.


----------



## KedarWolf

Eder said:


> Having a great time with new dual rank kit. Just passed 20 cycles TM5 with 1.5v on the sticks.


With GDM Enabled you're really doing 14-16-16-16-30-42 I think.

Run AIDA64 Cache And Memory test, then try the below and rerun it. I find the bandwidth I get is quite good.


----------



## nick name

KedarWolf said:


> With GDM Enabled you're really doing 14-16-16-16-30-42 I think.
> 
> Run AIDA64 Cache And Memory test, then try the below and rerun it. I find the bandwidth I get is quite good.


I'm still not convinced tRCD and tRP can't be odd values with GDM enabled. The white papers didn't mention them and they don't change during memory training. I wish there was some way to confirm.


----------



## Eder

KedarWolf said:


> Eder said:
> 
> 
> 
> Having a great time with new dual rank kit. Just passed 20 cycles TM5 with 1.5v on the sticks.
> 
> 
> 
> With GDM Enabled you're really doing 14-16-16-16-30-42 I think.
> 
> Run AIDA64 Cache And Memory test, then try the below and rerun it. I find the bandwidth I get is quite good. /forum/images/smilies/smile.gif
Click to expand...

My previous kits never had a problem with GDM so I totally forgot about it. Thanks! I will play with your 2T settings.


----------



## 2600ryzen

nick name said:


> I'm still not convinced tRCD and tRP can't be odd values with GDM enabled. The white papers didn't mention them and they don't change during memory training. I wish there was some way to confirm.



You can benchmark the difference, I think trp can be odd but trcdrd isn't. With GDM enabled raising trcdrd from 18 to 19 should raise it to 20 if it gets rounded up, a big measurable difference in benchmarking.


----------



## KedarWolf

Hey peeps,

If you have issues with being TM5 stable, then on reboots your not stable any more, when you ARE TM5 stable, reboot into BIOS right away, enable Memory Fast Boot or DRAM Fast Boot, whatever it is in your BIOS.

I think it should stop your memory from retraining every time you reboot, which may change things and make you unstable different reboots. :h34r-smi


----------



## algida79

KedarWolf said:


> Hey peeps,
> 
> If you have issues with being TM5 stable, then on reboots your not stable any more, when you ARE TM5 stable, reboot into BIOS right away, enable Memory Fast Boot or DRAM Fast Boot, whatever it is in your BIOS.
> 
> I think it should stop your memory from retraining every time you reboot, which may change things and make you unstable different reboots. :h34r-smi



I would argue that a mem OC that behaves differently across reboots or cold boots is not a particularly stable OC in the first place and this workaround would only mask the problem.


----------



## Dyngsur

Hello!

Got my memory stable, did 24 cycles TM5 etc.

But the HWinfo64 sometimes shows CPU/Bus error, tried to Google about it and it can be many things.

Someone know what it can be? 

Can it be cause of undervolting cpu/gpu etc? or can it be win10 thats acting strange or can it be HWinfo64 that aint working as it should, cause the computer working nice.

Can it be that win10 is corrupted and needs a reinstall?

I am asking if someone knows anything about it.


----------



## KedarWolf

algida79 said:


> I would argue that a mem OC that behaves differently across reboots or cold boots is not a particularly stable OC in the first place and this workaround would only mask the problem.


The reason I suggested this is between reboots with memory training enabled, there can be subtle changes in hidden timings and sub timings that can make your memory overclock stable one boot, then unstable on other boots.

The only real way to test my theory is to get TM5 stable, reboot into BIOS, disable memory training, then run TM5 after a few times after rebooting each time.


If TM5 holds up and you get no errors, this practice is good. If you DO get errors, then, my bad, I'm wrong.


----------



## nick name

KedarWolf said:


> The reason I suggested this is between reboots with memory training enabled, there can be subtle changes in hidden timings and sub timings that can make your memory overclock stable one boot, then unstable on other boots.
> 
> The only real way to test my theory is to get TM5 stable, reboot into BIOS, disable memory training, then run TM5 after a few times after rebooting each time.
> 
> 
> If TM5 holds up and you get no errors, this practice is good. If you DO get errors, then, my bad, I'm wrong.


On an ASUS board with Fast Boot enabled I think you can accomplish this by simply rebooting from Windows. Perhaps even without Fast Boot enabled. On a cold boot I always see memory training, but a simple reboot from Windows skips that. And in my case a reboot also produces better Aida results.

But relying on training to find stability can be infuriating. I tried for a while to get 3733 stable on my old 2700X. Some memory training instances produced a stable session, but many did not.


----------



## algida79

KedarWolf said:


> The reason I suggested this is between reboots with memory training enabled, there can be subtle changes in hidden timings and sub timings that can make your memory overclock stable one boot, then unstable on other boots.
> 
> The only real way to test my theory is to get TM5 stable, reboot into BIOS, disable memory training, then run TM5 after a few times after rebooting each time.
> 
> 
> If TM5 holds up and you get no errors, this practice is good. If you DO get errors, then, my bad, I'm wrong.


Oh I'm not disputing this theory, I have personally experienced the effect multiple times. I'm just implying that when it happens, you are usually at the edge of stability and if your BIOS does not expose enough settings to make the memory training more deterministic, a better long-term strategy imho would be to backtrack (go to next lowest RAM speed strap, loosen timings etc) instead.


----------



## Eder

nick name said:


> I'm still not convinced tRCD and tRP can't be odd values with GDM enabled. The white papers didn't mention them and they don't change during memory training. I wish there was some way to confirm.


Tried your timings and I'm getting similar benchmark results. Going to take some longer stability tests to figure out what's best. GDM off is a big no with 3800CL14 or I haven't figured it out. By the way, is there a reason your soc voltage is quite high?


----------



## KedarWolf

Eder said:


> Tried your timings and I'm getting similar benchmark results. Going to take some longer stability tests to figure out what's best. GDM off is a big no with 3800CL14 or I haven't figured it out. By the way, is there a reason your soc voltage is quite high?


I think you meant to ask me about the SoC voltage.

With a rather high CCX overclock and the tight RAM timings I need the VoC voltage a bit hgh or I get random reboots when stress testing etc.

I've even had this issue with CL15 timings, GDM off and on. I believe it's because the VoC voltage not only affects memory stability but also high CPU overclock stability.


----------



## nick name

Eder said:


> Tried your timings and I'm getting similar benchmark results. Going to take some longer stability tests to figure out what's best. GDM off is a big no with 3800CL14 or I haven't figured it out. By the way, is there a reason your soc voltage is quite high?


Did you mean to quote me? I get the feeling you didn't mean to quote me.


----------



## SneakySloth

KedarWolf said:


> I think you meant to ask me about the SoC voltage.
> 
> With a rather high CCX overclock and the tight RAM timings I need the VoC voltage a bit hgh or I get random reboots when stress testing etc.
> 
> I've even had this issue with CL15 timings, GDM off and on. I believe it's because the VoC voltage not only affects memory stability but also high CPU overclock stability.



Increasing the ram voltage doesn't help with the ram being more stable?


----------



## rares495

SneakySloth said:


> Increasing the ram voltage doesn't help with the ram being more stable?


Not always.


----------



## Eder

nick name said:


> Eder said:
> 
> 
> 
> Tried your timings and I'm getting similar benchmark results. Going to take some longer stability tests to figure out what's best. GDM off is a big no with 3800CL14 or I haven't figured it out. By the way, is there a reason your soc voltage is quite high?
> 
> 
> 
> Did you mean to quote me? I get the feeling you didn't mean to quote me.
Click to expand...

Whoops, my bad. I should get more sleep.


----------



## hazium233

Was working with 2x8GB Ballistix 3200 16-18-18-36 dimms (8Gb Rev E) at 3533 14-16/18-16-36-54 at 1.44V. I am not sure if I should juggle the timings around a bit more. It did have the best Sandra mce latencies. The bandwidth graphs largely overlapped for different timings, although this one didn't rate the highest for whatever average.

If I wanted to do more testing, what should I be juggling around here? Test tRTP 6, tWR 12? That puts tWR to ~6.8ns. Or I guess I could test tRFC 544.

I had tried tRC 56, tRFC 560 but that was slower in Blender. 54 is sort of cheating tRAS+tRP already.



Spoiler



SiSoftware Sandra

Benchmark Results
Inter-Core Bandwidth : 59.48GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Inter-Core Latency : 73.5ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Inter-Core Bandwidth : 3.72GB/s
No. Threads : 16
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 109.93W
Inter-Core Bandwidth : 554.06MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 6.69ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 188.63kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Inter-Core Bandwidth : 14.42MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 0.17ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 
U0-U2 Data Latency : 40.0ns
U0-U4 Data Latency : 42.3ns
U0-U6 Data Latency : 40.8ns
U0-U8 Data Latency : 104.5ns
U0-U10 Data Latency : 103.6ns
U0-U12 Data Latency : 106.3ns
U0-U14 Data Latency : 106.4ns
U0-U1 Data Latency : 14.3ns
U0-U3 Data Latency : 40.4ns
U0-U5 Data Latency : 42.3ns
U0-U7 Data Latency : 41.0ns
U0-U9 Data Latency : 104.6ns
U0-U11 Data Latency : 103.4ns
U0-U13 Data Latency : 106.7ns
U0-U15 Data Latency : 105.4ns
U2-U4 Data Latency : 41.3ns
U2-U6 Data Latency : 41.5ns
U2-U8 Data Latency : 101.9ns
U2-U10 Data Latency : 103.9ns
U2-U12 Data Latency : 103.2ns
U2-U14 Data Latency : 105.5ns
U2-U1 Data Latency : 41.7ns
U2-U3 Data Latency : 14.3ns
U2-U5 Data Latency : 38.6ns
U2-U7 Data Latency : 40.8ns
U2-U9 Data Latency : 102.5ns
U2-U11 Data Latency : 104.1ns
U2-U13 Data Latency : 103.4ns
U2-U15 Data Latency : 105.4ns
U4-U6 Data Latency : 42.3ns
U4-U8 Data Latency : 104.5ns
U4-U10 Data Latency : 102.4ns
U4-U12 Data Latency : 105.8ns
U4-U14 Data Latency : 104.3ns
U4-U1 Data Latency : 41.0ns
U4-U3 Data Latency : 41.4ns
U4-U5 Data Latency : 14.1ns
U4-U7 Data Latency : 41.9ns
U4-U9 Data Latency : 104.5ns
U4-U11 Data Latency : 102.4ns
U4-U13 Data Latency : 105.7ns
U4-U15 Data Latency : 104.8ns
U6-U8 Data Latency : 102.4ns
U6-U10 Data Latency : 104.6ns
U6-U12 Data Latency : 103.8ns
U6-U14 Data Latency : 105.8ns
U6-U1 Data Latency : 40.1ns
U6-U3 Data Latency : 41.9ns
U6-U5 Data Latency : 41.2ns
U6-U7 Data Latency : 14.2ns
U6-U9 Data Latency : 103.3ns
U6-U11 Data Latency : 104.8ns
U6-U13 Data Latency : 104.0ns
U6-U15 Data Latency : 105.6ns
U8-U10 Data Latency : 40.1ns
U8-U12 Data Latency : 42.1ns
U8-U14 Data Latency : 40.8ns
U8-U1 Data Latency : 104.0ns
U8-U3 Data Latency : 100.6ns
U8-U5 Data Latency : 104.4ns
U8-U7 Data Latency : 104.4ns
U8-U9 Data Latency : 14.0ns
U8-U11 Data Latency : 39.0ns
U8-U13 Data Latency : 41.9ns
U8-U15 Data Latency : 40.8ns
U10-U12 Data Latency : 41.1ns
U10-U14 Data Latency : 42.6ns
U10-U1 Data Latency : 102.2ns
U10-U3 Data Latency : 107.0ns
U10-U5 Data Latency : 106.0ns
U10-U7 Data Latency : 104.3ns
U10-U9 Data Latency : 39.6ns
U10-U11 Data Latency : 14.2ns
U10-U13 Data Latency : 40.8ns
U10-U15 Data Latency : 42.4ns
U12-U14 Data Latency : 44.0ns
U12-U1 Data Latency : 105.2ns
U12-U3 Data Latency : 103.6ns
U12-U5 Data Latency : 105.4ns
U12-U7 Data Latency : 105.5ns
U12-U9 Data Latency : 41.5ns
U12-U11 Data Latency : 40.1ns
U12-U13 Data Latency : 14.0ns
U12-U15 Data Latency : 42.0ns
U14-U1 Data Latency : 104.7ns
U14-U3 Data Latency : 108.1ns
U14-U5 Data Latency : 106.9ns
U14-U7 Data Latency : 107.7ns
U14-U9 Data Latency : 42.1ns
U14-U11 Data Latency : 41.5ns
U14-U13 Data Latency : 43.5ns
U14-U15 Data Latency : 14.0ns
U1-U3 Data Latency : 41.2ns
U1-U5 Data Latency : 42.1ns
U1-U7 Data Latency : 41.8ns
U1-U9 Data Latency : 105.6ns
U1-U11 Data Latency : 103.9ns
U1-U13 Data Latency : 105.6ns
U1-U15 Data Latency : 105.1ns
U3-U5 Data Latency : 41.4ns
U3-U7 Data Latency : 41.8ns
U3-U9 Data Latency : 104.3ns
U3-U11 Data Latency : 104.5ns
U3-U13 Data Latency : 105.9ns
U3-U15 Data Latency : 106.1ns
U5-U7 Data Latency : 43.5ns
U5-U9 Data Latency : 105.2ns
U5-U11 Data Latency : 105.1ns
U5-U13 Data Latency : 105.3ns
U5-U15 Data Latency : 105.4ns
U7-U9 Data Latency : 105.1ns
U7-U11 Data Latency : 109.2ns
U7-U13 Data Latency : 105.9ns
U7-U15 Data Latency : 107.9ns
U9-U11 Data Latency : 41.3ns
U9-U13 Data Latency : 42.7ns
U9-U15 Data Latency : 42.0ns
U11-U13 Data Latency : 41.4ns
U11-U15 Data Latency : 42.3ns
U13-U15 Data Latency : 43.9ns
1x 64bytes Blocks Bandwidth : 6.84GB/s
4x 64bytes Blocks Bandwidth : 17.57GB/s
4x 256bytes Blocks Bandwidth : 67.35GB/s
4x 1024bytes Blocks Bandwidth : 140.6GB/s
4x 4kB Blocks Bandwidth : 192.12GB/s
16x 4kB Blocks Bandwidth : 220.47GB/s
4x 64kB Blocks Bandwidth : 257.56GB/s
16x 64kB Blocks Bandwidth : 216.25GB/s
8x 256kB Blocks Bandwidth : 198.3GB/s
4x 1024kB Blocks Bandwidth : 16.58GB/s
8x 1024kB Blocks Bandwidth : 15GB/s
8x 4MB Blocks Bandwidth : 14.81GB/s

Benchmark Status
Result ID : AMD Ryzen 7 2700X Eight-Core Processor (8C 16T 4.22GHz, 1.77GHz IMC, 8x 512kB L2, 2x 8MB L3)
Microcode : MU8F08020B
Computer : ASUS ROG STRIX X370-F GAMING
Platform Compliance : x64
Buffering Used : No
No. Threads : 16
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 7 2700X Eight-Core Processor
Speed : 4.22GHz
Min/Max/Turbo Speed : 2.2GHz - 3.7GHz - 4.22GHz
Maximum Power : 109.93W - 136.91W
Cores per Processor : 8 Unit(s)
Cores per Compute Unit : 2 Unit(s)
Front Side Bus Speed : 100MHz
Revision/Stepping : 8 / 2
Microcode : MU8F08020B
L1D (1st Level) Data Cache : 8x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 8x 64kB, 4-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 8x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 8MB, 16-Way, Exclusive, 64bytes Line Size, 8 Thread(s)

Memory Controller
Speed : 1.77GHz (100%)
Min/Max/Turbo Speed : 883MHz - 1.77GHz


----------



## Solohuman

hazium233 said:


> Was working with 2x8GB Ballistix 3200 16-18-18-36 dimms (8Gb Rev E) at 3533 14-16/18-16-36-54 at 1.44V. I am not sure if I should juggle the timings around a bit more. It did have the best Sandra mce latencies. The bandwidth graphs largely overlapped for different timings, although this one didn't rate the highest for whatever average.
> 
> If I wanted to do more testing, what should I be juggling around here? Test tRTP 6, tWR 12? That puts tWR to ~6.8ns. Or I guess I could test tRFC 544.
> 
> I had tried tRC 56, tRFC 560 but that was slower in Blender. 54 is sort of cheating tRAS+tRP already.
> 
> 
> 
> Spoiler
> 
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Inter-Core Bandwidth : 59.48GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Inter-Core Latency : 73.5ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Inter-Core Bandwidth : 3.72GB/s
> No. Threads : 16
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 109.93W
> Inter-Core Bandwidth : 554.06MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Inter-Core Latency : 6.69ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 188.63kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Inter-Core Bandwidth : 14.42MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Inter-Core Latency : 0.17ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15
> U0-U2 Data Latency : 40.0ns
> U0-U4 Data Latency : 42.3ns
> U0-U6 Data Latency : 40.8ns
> U0-U8 Data Latency : 104.5ns
> U0-U10 Data Latency : 103.6ns
> U0-U12 Data Latency : 106.3ns
> U0-U14 Data Latency : 106.4ns
> U0-U1 Data Latency : 14.3ns
> U0-U3 Data Latency : 40.4ns
> U0-U5 Data Latency : 42.3ns
> U0-U7 Data Latency : 41.0ns
> U0-U9 Data Latency : 104.6ns
> U0-U11 Data Latency : 103.4ns
> U0-U13 Data Latency : 106.7ns
> U0-U15 Data Latency : 105.4ns
> U2-U4 Data Latency : 41.3ns
> U2-U6 Data Latency : 41.5ns
> U2-U8 Data Latency : 101.9ns
> U2-U10 Data Latency : 103.9ns
> U2-U12 Data Latency : 103.2ns
> U2-U14 Data Latency : 105.5ns
> U2-U1 Data Latency : 41.7ns
> U2-U3 Data Latency : 14.3ns
> U2-U5 Data Latency : 38.6ns
> U2-U7 Data Latency : 40.8ns
> U2-U9 Data Latency : 102.5ns
> U2-U11 Data Latency : 104.1ns
> U2-U13 Data Latency : 103.4ns
> U2-U15 Data Latency : 105.4ns
> U4-U6 Data Latency : 42.3ns
> U4-U8 Data Latency : 104.5ns
> U4-U10 Data Latency : 102.4ns
> U4-U12 Data Latency : 105.8ns
> U4-U14 Data Latency : 104.3ns
> U4-U1 Data Latency : 41.0ns
> U4-U3 Data Latency : 41.4ns
> U4-U5 Data Latency : 14.1ns
> U4-U7 Data Latency : 41.9ns
> U4-U9 Data Latency : 104.5ns
> U4-U11 Data Latency : 102.4ns
> U4-U13 Data Latency : 105.7ns
> U4-U15 Data Latency : 104.8ns
> U6-U8 Data Latency : 102.4ns
> U6-U10 Data Latency : 104.6ns
> U6-U12 Data Latency : 103.8ns
> U6-U14 Data Latency : 105.8ns
> U6-U1 Data Latency : 40.1ns
> U6-U3 Data Latency : 41.9ns
> U6-U5 Data Latency : 41.2ns
> U6-U7 Data Latency : 14.2ns
> U6-U9 Data Latency : 103.3ns
> U6-U11 Data Latency : 104.8ns
> U6-U13 Data Latency : 104.0ns
> U6-U15 Data Latency : 105.6ns
> U8-U10 Data Latency : 40.1ns
> U8-U12 Data Latency : 42.1ns
> U8-U14 Data Latency : 40.8ns
> U8-U1 Data Latency : 104.0ns
> U8-U3 Data Latency : 100.6ns
> U8-U5 Data Latency : 104.4ns
> U8-U7 Data Latency : 104.4ns
> U8-U9 Data Latency : 14.0ns
> U8-U11 Data Latency : 39.0ns
> U8-U13 Data Latency : 41.9ns
> U8-U15 Data Latency : 40.8ns
> U10-U12 Data Latency : 41.1ns
> U10-U14 Data Latency : 42.6ns
> U10-U1 Data Latency : 102.2ns
> U10-U3 Data Latency : 107.0ns
> U10-U5 Data Latency : 106.0ns
> U10-U7 Data Latency : 104.3ns
> U10-U9 Data Latency : 39.6ns
> U10-U11 Data Latency : 14.2ns
> U10-U13 Data Latency : 40.8ns
> U10-U15 Data Latency : 42.4ns
> U12-U14 Data Latency : 44.0ns
> U12-U1 Data Latency : 105.2ns
> U12-U3 Data Latency : 103.6ns
> U12-U5 Data Latency : 105.4ns
> U12-U7 Data Latency : 105.5ns
> U12-U9 Data Latency : 41.5ns
> U12-U11 Data Latency : 40.1ns
> U12-U13 Data Latency : 14.0ns
> U12-U15 Data Latency : 42.0ns
> U14-U1 Data Latency : 104.7ns
> U14-U3 Data Latency : 108.1ns
> U14-U5 Data Latency : 106.9ns
> U14-U7 Data Latency : 107.7ns
> U14-U9 Data Latency : 42.1ns
> U14-U11 Data Latency : 41.5ns
> U14-U13 Data Latency : 43.5ns
> U14-U15 Data Latency : 14.0ns
> U1-U3 Data Latency : 41.2ns
> U1-U5 Data Latency : 42.1ns
> U1-U7 Data Latency : 41.8ns
> U1-U9 Data Latency : 105.6ns
> U1-U11 Data Latency : 103.9ns
> U1-U13 Data Latency : 105.6ns
> U1-U15 Data Latency : 105.1ns
> U3-U5 Data Latency : 41.4ns
> U3-U7 Data Latency : 41.8ns
> U3-U9 Data Latency : 104.3ns
> U3-U11 Data Latency : 104.5ns
> U3-U13 Data Latency : 105.9ns
> U3-U15 Data Latency : 106.1ns
> U5-U7 Data Latency : 43.5ns
> U5-U9 Data Latency : 105.2ns
> U5-U11 Data Latency : 105.1ns
> U5-U13 Data Latency : 105.3ns
> U5-U15 Data Latency : 105.4ns
> U7-U9 Data Latency : 105.1ns
> U7-U11 Data Latency : 109.2ns
> U7-U13 Data Latency : 105.9ns
> U7-U15 Data Latency : 107.9ns
> U9-U11 Data Latency : 41.3ns
> U9-U13 Data Latency : 42.7ns
> U9-U15 Data Latency : 42.0ns
> U11-U13 Data Latency : 41.4ns
> U11-U15 Data Latency : 42.3ns
> U13-U15 Data Latency : 43.9ns
> 1x 64bytes Blocks Bandwidth : 6.84GB/s
> 4x 64bytes Blocks Bandwidth : 17.57GB/s
> 4x 256bytes Blocks Bandwidth : 67.35GB/s
> 4x 1024bytes Blocks Bandwidth : 140.6GB/s
> 4x 4kB Blocks Bandwidth : 192.12GB/s
> 16x 4kB Blocks Bandwidth : 220.47GB/s
> 4x 64kB Blocks Bandwidth : 257.56GB/s
> 16x 64kB Blocks Bandwidth : 216.25GB/s
> 8x 256kB Blocks Bandwidth : 198.3GB/s
> 4x 1024kB Blocks Bandwidth : 16.58GB/s
> 8x 1024kB Blocks Bandwidth : 15GB/s
> 8x 4MB Blocks Bandwidth : 14.81GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 7 2700X Eight-Core Processor (8C 16T 4.22GHz, 1.77GHz IMC, 8x 512kB L2, 2x 8MB L3)
> Microcode : MU8F08020B
> Computer : ASUS ROG STRIX X370-F GAMING
> Platform Compliance : x64
> Buffering Used : No
> No. Threads : 16
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 7 2700X Eight-Core Processor
> Speed : 4.22GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.7GHz - 4.22GHz
> Maximum Power : 109.93W - 136.91W
> Cores per Processor : 8 Unit(s)
> Cores per Compute Unit : 2 Unit(s)
> Front Side Bus Speed : 100MHz
> Revision/Stepping : 8 / 2
> Microcode : MU8F08020B
> L1D (1st Level) Data Cache : 8x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 8x 64kB, 4-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 8x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 8MB, 16-Way, Exclusive, 64bytes Line Size, 8 Thread(s)
> 
> Memory Controller
> Speed : 1.77GHz (100%)
> Min/Max/Turbo Speed : 883MHz - 1.77GHz


Your SoC is too low, I've had success with Memtest5 v0.12 & with 1usmus _v3 config @ 3533 with my 2600X on X570 board in my rigbuilder profile but have Hynix CJR chips. My SoC was 1.06.


----------



## Veii

Solohuman said:


> Your SoC is too low, I've had success with Memtest5 v0.12 & with 1usmus _v3 config @ 3533 with my 2600X on X570 board in my rigbuilder profile but have Hynix CJR chips. My SoC was 1.06.


Did you use procODT 60ohm for that or 53.3 ?
SOC seems high for 12nm 
How high did XFR2 / PBO boost ?


----------



## Ortus

Passed two 40 cycle tm5 runs, VDDG CCD is 1.035


----------



## hazium233

Solohuman said:


> Your SoC is too low, I've had success with Memtest5 v0.12 & with 1usmus _v3 config @ 3533 with my 2600X on X570 board in my rigbuilder profile but have Hynix CJR chips. My SoC was 1.06.


It goes through 20 cycles of 1usmus v3 at this voltage, hour of AIDA cache. Did a few loops of y-cruncher at a little looser timings. I suppose as an experiment I can try that and see if it is faster.


----------



## pipes

Tuf x570 gaming plus and new BIOS can take same DRAM oc 

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## KedarWolf

This is what I've settled on with my overclock on RAM.

My BLCK is at 100.45, I tried 246 tRFC but would get random reboots with TM5 running. They are gone with it at 252.

I get 61.7ns latency in AIDA64 and with tCWL at 12 I get decent Read, Write and Copy. 

I get Write well over 58k now. 

Oh, and I'm 25 rounds of TM5 stable. :drum:


----------



## Solohuman

Veii said:


> Did you use procODT 60ohm for that or 53.3 ?
> SOC seems high for 12nm
> How high did XFR2 / PBO boost ?


Can't recall exactly what procODT used but it was definitely either of those. 
But here is y-cruncher with loose timings @ 3533 - 8 runs
1.05 SoC carries it.
PBO acts with less boost than on my previous B450 board, however new bios out now for this X570 so will see what happens..


----------



## pipes

Solohuman said:


> Can't recall exactly what procODT used but it was definitely either of those.
> 
> But here is y-cruncher with loose timings @ 3533 - 8 runs
> 
> 1.05 SoC carries it.
> 
> PBO acts with less boost than on my previous B450 board, however new bios out now for this X570 so will see what happens..


Wich Viper steel model is? I can't take 3800 cl15 with new BIOS 

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## hazium233

I only bothered to run another two iterations of y-cruncher on the previous set, so only ~43 minutes. I can run ProcODT 43 at this frequency if I want, but had moved to 48 because I had thought it might actually do a hair better latency in sandra. My board is an X370-F, which is odd in that the SOC VRM is 4 x IR3555 "4 phase" (2 with doublers). In AIDA testing at least, phase to Extreme with switching bumped can be similar to a notch or so SOC with them at default. I have also been testing with core at default.

I increased SOC to 1.025V and just ran some tests, but if anything it caused slight performance drop in sandra, and a Classroom.

Anyway I decided to go back and simply look at the calculator "safe" 3533 profile. Phase/Switching actually I didn't touch here compared to a cl16 profile I loaded, although I thought if I couldn't stabilize it I would go back or see if I could quantify a difference with TM5.

One difference from preset is that this kit does tRCDRD 18t at 3533, so I wanted to use that instead of 19t in the calculator. I was more interested in the pattern of the secondaries, and the relationship between the tRC at 56 and the calculator's trFC of 565. I set tRFC 2 and 4 to 420 and 258. I originally tested at 1.360 vdimm, but had 2 errors in 20 cycles. 1.375V resulted in below. This safe preset gave one of the better intercore latencies, even if the bandwidth tested lower.

Ran it through an MCE, can post the text and the graph. In the comparison, the green set is the previously posted 3533c14 that was attached in full and had the best latency. The blue line is a set that happened to have best bandwidth score, it was sort of odd in that it had tRC 58 and tRFC 540, and ProcODT on 43.6.

Modified "Safe" preset MCE report



Spoiler



SiSoftware Sandra

Benchmark Results
Inter-Core Bandwidth : 58.9GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Inter-Core Latency : 73.7ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Inter-Core Bandwidth : 3.68GB/s
No. Threads : 16
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 109.93W
Inter-Core Bandwidth : 548.69MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 6.70ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 188.63kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Inter-Core Bandwidth : 14.28MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 0.17ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 
U0-U2 Data Latency : 39.8ns
U0-U4 Data Latency : 41.1ns
U0-U6 Data Latency : 41.6ns
U0-U8 Data Latency : 106.2ns
U0-U10 Data Latency : 105.7ns
U0-U12 Data Latency : 105.6ns
U0-U14 Data Latency : 108.0ns
U0-U1 Data Latency : 14.3ns
U0-U3 Data Latency : 39.9ns
U0-U5 Data Latency : 41.4ns
U0-U7 Data Latency : 41.6ns
U0-U9 Data Latency : 105.7ns
U0-U11 Data Latency : 106.8ns
U0-U13 Data Latency : 105.8ns
U0-U15 Data Latency : 108.1ns
U2-U4 Data Latency : 40.6ns
U2-U6 Data Latency : 42.1ns
U2-U8 Data Latency : 103.8ns
U2-U10 Data Latency : 103.8ns
U2-U12 Data Latency : 104.7ns
U2-U14 Data Latency : 105.5ns
U2-U1 Data Latency : 39.8ns
U2-U3 Data Latency : 14.2ns
U2-U5 Data Latency : 41.2ns
U2-U7 Data Latency : 42.4ns
U2-U9 Data Latency : 103.6ns
U2-U11 Data Latency : 104.5ns
U2-U13 Data Latency : 104.6ns
U2-U15 Data Latency : 105.8ns
U4-U6 Data Latency : 42.8ns
U4-U8 Data Latency : 104.7ns
U4-U10 Data Latency : 105.0ns
U4-U12 Data Latency : 105.8ns
U4-U14 Data Latency : 106.8ns
U4-U1 Data Latency : 41.3ns
U4-U3 Data Latency : 40.1ns
U4-U5 Data Latency : 14.1ns
U4-U7 Data Latency : 42.5ns
U4-U9 Data Latency : 104.2ns
U4-U11 Data Latency : 106.9ns
U4-U13 Data Latency : 105.1ns
U4-U15 Data Latency : 106.8ns
U6-U8 Data Latency : 104.2ns
U6-U10 Data Latency : 105.4ns
U6-U12 Data Latency : 104.7ns
U6-U14 Data Latency : 105.3ns
U6-U1 Data Latency : 41.8ns
U6-U3 Data Latency : 43.0ns
U6-U5 Data Latency : 42.7ns
U6-U7 Data Latency : 14.0ns
U6-U9 Data Latency : 104.4ns
U6-U11 Data Latency : 106.6ns
U6-U13 Data Latency : 104.9ns
U6-U15 Data Latency : 105.8ns
U8-U10 Data Latency : 39.4ns
U8-U12 Data Latency : 40.8ns
U8-U14 Data Latency : 41.1ns
U8-U1 Data Latency : 104.1ns
U8-U3 Data Latency : 104.3ns
U8-U5 Data Latency : 105.1ns
U8-U7 Data Latency : 106.2ns
U8-U9 Data Latency : 14.1ns
U8-U11 Data Latency : 39.4ns
U8-U13 Data Latency : 40.7ns
U8-U15 Data Latency : 41.1ns
U10-U12 Data Latency : 40.8ns
U10-U14 Data Latency : 42.8ns
U10-U1 Data Latency : 104.0ns
U10-U3 Data Latency : 105.1ns
U10-U5 Data Latency : 104.7ns
U10-U7 Data Latency : 106.1ns
U10-U9 Data Latency : 39.7ns
U10-U11 Data Latency : 14.1ns
U10-U13 Data Latency : 40.3ns
U10-U15 Data Latency : 42.5ns
U12-U14 Data Latency : 43.0ns
U12-U1 Data Latency : 105.7ns
U12-U3 Data Latency : 104.9ns
U12-U5 Data Latency : 106.0ns
U12-U7 Data Latency : 106.5ns
U12-U9 Data Latency : 41.5ns
U12-U11 Data Latency : 40.0ns
U12-U13 Data Latency : 14.1ns
U12-U15 Data Latency : 42.5ns
U14-U1 Data Latency : 104.1ns
U14-U3 Data Latency : 106.6ns
U14-U5 Data Latency : 105.4ns
U14-U7 Data Latency : 105.7ns
U14-U9 Data Latency : 42.1ns
U14-U11 Data Latency : 42.9ns
U14-U13 Data Latency : 42.7ns
U14-U15 Data Latency : 14.2ns
U1-U3 Data Latency : 39.5ns
U1-U5 Data Latency : 41.0ns
U1-U7 Data Latency : 40.8ns
U1-U9 Data Latency : 104.4ns
U1-U11 Data Latency : 104.9ns
U1-U13 Data Latency : 105.9ns
U1-U15 Data Latency : 107.4ns
U3-U5 Data Latency : 40.8ns
U3-U7 Data Latency : 42.8ns
U3-U9 Data Latency : 103.3ns
U3-U11 Data Latency : 104.9ns
U3-U13 Data Latency : 104.7ns
U3-U15 Data Latency : 106.5ns
U5-U7 Data Latency : 42.7ns
U5-U9 Data Latency : 104.7ns
U5-U11 Data Latency : 106.0ns
U5-U13 Data Latency : 105.6ns
U5-U15 Data Latency : 107.2ns
U7-U9 Data Latency : 104.6ns
U7-U11 Data Latency : 105.6ns
U7-U13 Data Latency : 105.3ns
U7-U15 Data Latency : 105.6ns
U9-U11 Data Latency : 39.8ns
U9-U13 Data Latency : 40.8ns
U9-U15 Data Latency : 41.0ns
U11-U13 Data Latency : 40.7ns
U11-U15 Data Latency : 42.6ns
U13-U15 Data Latency : 43.0ns
1x 64bytes Blocks Bandwidth : 6.63GB/s
4x 64bytes Blocks Bandwidth : 17.53GB/s
4x 256bytes Blocks Bandwidth : 67.37GB/s
4x 1024bytes Blocks Bandwidth : 140.58GB/s
4x 4kB Blocks Bandwidth : 192GB/s
16x 4kB Blocks Bandwidth : 220.92GB/s
4x 64kB Blocks Bandwidth : 257.75GB/s
16x 64kB Blocks Bandwidth : 217.87GB/s
8x 256kB Blocks Bandwidth : 199GB/s
4x 1024kB Blocks Bandwidth : 16.58GB/s
8x 1024kB Blocks Bandwidth : 14.16GB/s
8x 4MB Blocks Bandwidth : 14.24GB/s

Benchmark Status
Result ID : AMD Ryzen 7 2700X Eight-Core Processor (8C 16T 4.22GHz, 1.77GHz IMC, 8x 512kB L2, 2x 8MB L3)
Microcode : MU8F08020B
Computer : ASUS ROG STRIX X370-F GAMING
Platform Compliance : x64
Buffering Used : No
No. Threads : 16
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 7 2700X Eight-Core Processor
Speed : 4.22GHz
Min/Max/Turbo Speed : 2.2GHz - 3.7GHz - 4.22GHz
Maximum Power : 109.93W - 136.91W
Cores per Processor : 8 Unit(s)
Cores per Compute Unit : 2 Unit(s)
Front Side Bus Speed : 100MHz
Revision/Stepping : 8 / 2
Microcode : MU8F08020B
L1D (1st Level) Data Cache : 8x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 8x 64kB, 4-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 8x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 8MB, 16-Way, Exclusive, 64bytes Line Size, 8 Thread(s)

Memory Controller
Speed : 1.77GHz (100%)
Min/Max/Turbo Speed : 883MHz - 1.77GHz



I may try GDM disabled, which I haven't attempted at > 3200MT/s. If so I might try the fast set. I have been interested in 3533, despite it being an odd step, because I do not think this ram kit can do 18t tRCDRD at 3600.


----------



## jcpq

1.42v


----------



## Solohuman

pipes said:


> Wich Viper steel model is? I can't take 3800 cl15 with new BIOS
> 
> Inviato dal mio MI 9 utilizzando Tapatalk


PE000635-PVS416G373C7K (Hynix CJR)


----------



## SirPerfluous

I Think I've Got a couple Pretty decent E die sticks. Does this look good to anyone else?


----------



## 2600ryzen

SirPerfluous said:


> I Think I've Got a couple Pretty decent E die sticks. Does this look good to anyone else?



Yeah that looks good, best I've gotten on my 2 x 16Gb rev e is 65.8ns though my timings are slightly different.


----------



## Veii

jcpq said:


> 1.42v











Might need voltage bump to 1.44 for lower tRFC & tRTP, try without bump first and compare both results


SirPerfluous said:


> I Think I've Got a couple Pretty decent E die sticks. Does this look good to anyone else?











Please report back, 
tRC 50 could be to low, but anything else makes no sense. Had even to bump tCL up in order to "make sense" :ninja:
tWRRD you have to figure out what it likes more
tRRD_L & tWTR_L can be skipped if your ICs don't like it (doubt)


----------



## SirPerfluous

This is the best I've gotten with these, But I couldn't quite get it stable. I'm sure I could with more fiddling, But I've sorta settled for 3770 on these sticks. 

I've got a pair of F4-3600C15-8GTZ that I want to dial in next. Anyone else have a recently purchased Set of these? Thaiphoon won't confirm its B-die. K4A8G085W[B/D]-BCPB Is all I get. It does have Numbers 042X~X10B, so I'm reasonably confident it is. Sticker on the sides say July of 2020.
Is B-die still being made? Is it still good?


----------



## SirPerfluous

Veii said:


> Please report back,
> tRC 50 could be to low, but anything else makes no sense. Had even to bump tCL up in order to "make sense" :ninja:
> tWRRD you have to figure out what it likes more
> tRRD_L & tWTR_L can be skipped if your ICs don't like it (doubt)


Okay, Ill give it a try

Edit: unnecessary reply. Wish I wasn't so impatient.


----------



## SirPerfluous

Ok, I'm back with my stable profile. I knew I'd already hit a wall on tRAS and tRC, But I thought I'd give your numbers a try anyway. (tRC52) I did manage to get into windows, open HWI64 and run testmem for about 5 seconds before avalanche of errors and then bsod. would continue to post and boot though. 

I've already tried lowering the others on separate occasions (except tWRRD) with no luck. Is there any disadvantage to having tWRRD as 1?

If I'm gonna be putting more time into these, I'm sort of more interested in making my 3800 profile with tCL 15 work. I did lower tRFC to 525 though, and it's made it through 4 cycles.
Here's ZT1.1 screencap for voltage and Cadbus


----------



## Veii

SirPerfluous said:


> This is the best I've gotten with these, But I couldn't quite get it stable. I'm sure I could with more fiddling, But I've sorta settled for 3770 on these sticks.
> 
> I've got a pair of F4-3600C15-8GTZ that I want to dial in next. Anyone else have a recently purchased Set of these? Thaiphoon won't confirm its B-die. K4A8G085W[B/D]-BCPB Is all I get. It does have Numbers 042X~X10B, so I'm reasonably confident it is. Sticker on the sides say July of 2020.
> Is B-die still being made? Is it still good?


B-dies old good ones are EOL since ~Q3 2018
Around 2019 a lot of Samsung's release where C-Dies

This is interesting for you:


Spoiler






















K4A8G045WB & K4A8G085WB are made before B-Dies, near 2016
They can be A-Dies or C-Dies, but samsung mentions B-dies
Soo pretty much "bad bin aka B-die v2" on the calculator


SirPerfluous said:


> Ok, I'm back with my stable profile. I knew I'd already hit a wall on tRAS and tRC, But I thought I'd give your numbers a try anyway. (tRC52) I did manage to get into windows, open HWI64 and run testmem for about 5 seconds before avalanche of errors and then bsod. would continue to post and boot though.
> 
> I've already tried lowering the others on separate occasions (except tWRRD) with no luck. Is there any disadvantage to having tWRRD as 1?
> 
> If I'm gonna be putting more time into these, I'm sort of more interested in making my 3800 profile with tCL 15 work. I did lower tRFC to 525 though, and it's made it through 4 cycles.
> Here's ZT1.1 screencap for voltage and Cadbus


Do never only use one thing
Timings have a connection
tRFC is wrong with tRC 60
i would need to change the whole set if you have issues
The good thing is, you got it to boot - the bad thing is, it has different issues 
Usually bad timings would result in no post - but i got no report back what is wrong , just "it is wrong" 
If you have errors, share them ~ for my magic ball, you are too far away to be screen-tracked 

tWRRD of 1 is not bad, except that tRDWR has to be higher then
your vSOC is far to high 
Pick a set of rams, give a proper thaiphoon burner report and let's work slowly on one thing
this awkward samsung ones feature some interesting abilities ~ CWL up to -3 of tCL 
Would be an interesting toy, but likely your Rev.E are easier to your memory controller
We don't know at what voltage these random Samsung ICs scale too
All up to your time


----------



## t4t3r

Veii --- Any feedback on these? My latency is up around 64 which is higher than I expected for the timings. Still learning the relationships between each, but I'm sure some of these could use some tweaking. I have a Viper 4400 kit that can go even tighter, but this cheap little Gskill 3200c14 (screenshotted) punches pretty well for it's weight class.


----------



## t4t3r

SirPerfluous said:


> This is the best I've gotten with these, But I couldn't quite get it stable. I'm sure I could with more fiddling, But I've sorta settled for 3770 on these sticks.
> 
> I've got a pair of F4-3600C15-8GTZ that I want to dial in next. Anyone else have a recently purchased Set of these? Thaiphoon won't confirm its B-die. K4A8G085W[B/D]-BCPB Is all I get. It does have Numbers 042X~X10B, so I'm reasonably confident it is. Sticker on the sides say July of 2020.
> Is B-die still being made? Is it still good?


I just received a 3600c15 kit yesterday and same entries in Thaiphoon except mine is Aug 2020. Mine is also A2 pcb which I was hoping for, but to be honest I've been a bit disappointed testing it so far. I'm still learning about the various PCBs and layouts so maybe they just don't scale as well at lower speeds like A0 and A1? My Viper 4400 and Gskill 3200c14 kits seem to get tighter at 3800, and the Vipers are tighter still even at 4200 versus the 3600c15.


----------



## KedarWolf

t4t3r said:


> Veii --- Any feedback on these? My latency is up around 64 which is higher than I expected for the timings. Still learning the relationships between each, but I'm sure some of these could use some tweaking. I have a Viper 4400 kit that can go even tighter, but this cheap little Gskill 3200c14 (screenshotted) punches pretty well for it's weight class.


This gives me 61.7ns and on 2x16GB so I'm very happy!


----------



## rares495

KedarWolf said:


> This gives me 61.7ns and on 2x16GB so I'm very happy!


Try lowering tRDWR to 8 and tWRRD to 1. Might improve performance a bit.


----------



## KedarWolf

rares495 said:


> Try lowering tRDWR to 8 and tWRRD to 1. Might improve performance a bit.


With tCWL at 12 I can't go lower than 10, won't boot, and I get errors in TM5 at 1.


----------



## rares495

KedarWolf said:


> With tCWL at 12 I can't go lower than 10, won't boot, and I get errors in TM5 at 1.


I don't think tCWL 12 vs 14 does much.


----------



## KedarWolf

rares495 said:


> I don't think tCWL 12 vs 14 does much.


It increases my Read, Write and Copy in AIDA64, my write goes above 58k and my latency goes from 61.9 to 61.7.


----------



## Veii

KedarWolf said:


> It increases my Read, Write and Copy in AIDA64, my write goes above 58k and my latency goes from 61.9 to 61.7.


has a bigger benefit than tRDWR 9 with tWRRD 2 ?


----------



## KedarWolf

Veii said:


> has a bigger benefit than tRDWR 9 with tWRRD 2 ?


Yes, better than even 8-2 or 9-2...


----------



## Veii

Better than 8-2, hmm 
Maybe ryzen 3rd gen is different, maybe the set was already well made and is different 
I had different results back then ~ clearly noticeable on SiSandra MCE 
tCWL only was used at the very end 
Interesting indeed :thinking:
Especially since we can use it on another tRC math (tRCD_WR+tCWL+4+tWR)


----------



## rares495

Veii said:


> Better than 8-2, hmm
> Maybe ryzen 3rd gen is different, maybe the set was already well made and is different
> I had different results back then ~ clearly noticeable on SiSandra MCE
> tCWL only was used at the very end
> Interesting indeed :thinking:
> Especially since we can use it on another tRC math (tRCD_WR+tCWL+4+tWR)


Yup, I'll have to test this.


----------



## KedarWolf

Veii said:


> Better than 8-2, hmm
> Maybe ryzen 3rd gen is different, maybe the set was already well made and is different
> I had different results back then ~ clearly noticeable on SiSandra MCE
> tCWL only was used at the very end
> Interesting indeed :thinking:
> Especially since we can use it on another tRC math (tRCD_WR+tCWL+4+tWR)


Can't do 8-2, won't boot tCWL 14, had to do 8-3.

Here's my results.

tCWL 12 10-2










tCWL 14 8-3


----------



## Veii

KedarWolf said:


> Can't do 8-2, won't boot tCWL 14, had to do 8-3.
> 
> Here's my results.
> tCWL 12 10-2
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tCWL 14 8-3
> 
> 
> Spoiler


Can you try two little things, increase VDIMM to 1.48 and see if tCWL 14 result won'T get randomly better after you wait 2min for the OS services to finish
And then try for me please 231-172-106 tRFC with tRTP 7 
Can use it on both sets you always run 

What result do you actually get with tRDWR 10 and tWRRD 1 instead of 2 ?
I think this low tRFC should post with the higher tRDWR ~ else maaybe tWRRD 3 could be needed here to :thinking: just curious if you can post it


----------



## KedarWolf

Veii said:


> Can you try two little things, increase VDIMM to 1.48 and see if tCWL 14 result won'T get randomly better after you wait 2min for the OS services to finish
> And then try for me please 231-172-106 tRFC with tRTP 7
> Can use it on both sets you always run
> 
> What result do you actually get with tRDWR 10 and tWRRD 1 instead of 2 ?
> I think this low tRFC should post with the higher tRDWR ~ else maaybe tWRRD 3 could be needed here to :thinking: just curious if you can post it


VDIMM IS at 1.48v. 

10-1 gives me errors in TM5 last time I checked, 10-2 doesn't.

I'll try to post with that tRFC but I'm really sure it won't pass TM5. 

Edit: 231-172-106 blue screens booting into Windows with 10-3 tRTP 7.


----------



## Veii

KedarWolf said:


> VDIMM IS at 1.48v.
> 
> 10-1 gives me errors in TM5 last time I checked, 10-2 doesn't.
> Edit: 231-172-106 blue screens booting into Windows with 10-3 tRTP 7.



At least it posts, soo there is potential


----------



## jcpq

Veii said:


> Might need voltage bump to 1.44 for lower tRFC & tRTP, try without bump first and compare both results


Thanks,but with tRDWR below 10, there is no post.


----------



## rares495

jcpq said:


> Thanks,but with tRDWR below 10, there is no post.


That's due to your low tCWL. My experience with that was:

tCWL 14 -> works with tRDWR 8

tCWL 12 -> requires tRDWR 10

tCWL 11 -> requires tRDWR 11

tCWL 10 -> requires tRDWR 12

tCWL 9 -> requires tRDWR 13


----------



## jcpq

rares495 said:


> That's due to your low tCWL. My experience with that was:
> 
> tCWL 14 -> works with tRDWR 8
> 
> tCWL 12 -> requires tRDWR 10
> 
> tCWL 11 -> requires tRDWR 11
> 
> tCWL 10 -> requires tRDWR 12
> 
> tCWL 9 -> requires tRDWR 13


And changing tCWL to 14 and tRDWR to 8, what are the gains?


----------



## rares495

jcpq said:


> And changing tCWL to 14 and tRDWR to 8, what are the gains?


You have to test which one performs better: tRDWR 8 or tCWL 12.


----------



## KedarWolf

jcpq said:


> And changing tCWL to 14 and tRDWR to 8, what are the gains?


https://www.overclock.net/forum/10-...memory-stability-thread-453.html#post28583988


----------



## jcpq

rares495 said:


> You have to test which one performs better: tRDWR 8 or tCWL 12.


Ok thanks


----------



## jcpq

KedarWolf said:


> https://www.overclock.net/forum/10-...memory-stability-thread-453.html#post28583988


Is better tCWL 12 10-2.


----------



## Veii

@rares495 @KedarWolf , now that tCWL 12 runs better 
We should do some testing how low or rather how high you can push SD, DD's without killing perf on 16gb SR 
I think the result should be different now 
Lower usually killed perf, what about higher :thinking:


----------



## KedarWolf

Veii said:


> @rares495 @KedarWolf , now that tCWL 12 runs better
> We should do some testing how low or rather how high you can push SD, DD's without killing perf on 16gb SR
> I think the result should be different now
> Lower usually killed perf, what about higher :thinking:


I can try 5-5 7-7 when i get home from work, but 4-4 6-6 has always been the sweet spot for me.

Edit: I have 2x16GB DR RAM, which is pretty amazing the timings I'm getting.


----------



## Veii

KedarWolf said:


> I can try 5-5 7-7 when i get home from work, but 4-4 6-6 has always been the sweet spot for me.


mm~
Ment ones like 3-3 5-5
or 6-6 8-8 
now that tCWL ≠ tCL , it should be different


----------



## KedarWolf

Veii said:


> mm~
> Ment ones like 3-3 5-5
> or 6-6 8-8
> now that tCWL ≠ tCL , it should be different


Never could boot lower then 4-4 6-6 but I can try 5-5-7-7 and 6-6 8-8.

Edit: I'll try 3-3 5-5 though as an experiment.

Second edit: Should I try tCL 12, see if it posts?


----------



## bluehillday

how does ryzen apu's play along with ram OC? cause on my b450m mobo increasing the gfx voltage to OC the igpu frequency , equals to settings vsoc. for example setting 1.15v gfx sets the vsoc as well to 1.15v , but when OC ram for ryzen cpu's you need to lower it to work. in my case that wasn't true because i needed 1.15vsoc to OC make my micron 4gb b-die from 2666 to 3266 at 1.25V and 1.15vsoc , under 1.15vsoc it gives error in memtest.


----------



## KedarWolf

KedarWolf said:


> VDIMM IS at 1.48v.
> 
> 10-1 gives me errors in TM5 last time I checked, 10-2 doesn't.
> 
> I'll try to post with that tRFC but I'm really sure it won't pass TM5.
> 
> Edit: 231-172-106 blue screens booting into Windows with 10-3 tRTP 7.


*10-1*


----------



## SirPerfluous

So I Pulled my micron sticks out, threw the samsung set in, loaded up xmp and left my mobo to work out all the timings. This is what it gave me:

Really not sure why tRFC is like that. This is at 1.368v 

Fclk 1900 is easy for this chip. Should I start with 3800?


----------



## nick name

SirPerfluous said:


> So I Pulled my micron sticks out, threw the samsung set in, loaded up xmp and left my mobo to work out all the timings. This is what it gave me:
> 
> Really not sure why tRFC is like that. This is at 1.368v
> 
> Fclk 1900 is easy for this chip. Should I start with 3800?


Enable GDM.


----------



## KedarWolf

Messing with Memory Addressing, set it at 256.


----------



## rares495

Veii said:


> @rares495 @KedarWolf , now that tCWL 12 runs better
> We should do some testing how low or rather how high you can push SD, DD's without killing perf on 16gb SR
> I think the result should be different now
> Lower usually killed perf, what about higher :thinking:


Aida is so inconsistent but I don't want to use Sandra.


----------



## KedarWolf

Veii said:


> mm~
> Ment ones like 3-3 5-5
> or 6-6 8-8
> now that tCWL ≠ tCL , it should be different


3-3 5-5 doesn't boot. 5-5 7-7 and 6-6 8-8 much slower in AIDA64 and worse latency.

I also tried tCWL 10 and it was worse.


----------



## SirPerfluous

nick name said:


> Enable GDM.


Not gonna tinker with xmp settings. also, why enable gdm when I want an uneven cas timing of 15? 

been fiddling for a bit. not very lucky with these I guess. tm5 gives errors at most dram calc settings. Here's where I am for now at 1.42v:

posts at 3800 cas 14 above 1.48v and has posted with a sub 300 tRFC


----------



## Veii

SirPerfluous said:


> So I Pulled my micron sticks out, threw the samsung set in, loaded up xmp and left my mobo to work out all the timings. This is what it gave me:
> 
> Really not sure why tRFC is like that. This is at 1.368v
> 
> Fclk 1900 is easy for this chip. Should I start with 3800?


Error description:
64mb Data transfer, error
Mirror Move refresh, error
64mb data transfer from another bank, error
again refresh, error 

Either your primaries choke, or your tRDWR is too low for some reason
try 9-1 and see if that passes
else push tRCD_RD to 16 for now, till you feel comfortable with higher VDIMM beyond 1.42v
tRAS is a bit too high, but we'll see
tRFC get's predicted wrong as it has no starting point for such. There is no IC recognition functionality in the Bios , and math messes up
It's on every board ~ the same bug 

It doesn't matter if you start with 3734 or 3600
But if you struggle with tRCD 15 on 3600, something else is wrong
Less variables are better ~ soo get that one first sorted 
It's stable for a bit but crashes, tries to freshresh and crashes again
Either timeout of too low value issue
looks here like tRCD or tRDWR too low ~ but could be just too low voltage


----------



## Veii

SirPerfluous said:


> Not gonna tinker with xmp settings. also, why enable gdm when I want an uneven cas timing of 15?
> 
> been fiddling for a bit. not very lucky with these I guess. tm5 gives errors at most dram calc settings. Here's where I am for now at 1.42v:
> 
> posts at 3800 cas 14 above 1.48v and has posted with a sub 300 tRFC


This set, push vSOC to 1150 with stronger LLC so it droops to 1138mV under Cinebench R20 or Y-cruncher AVX2


----------



## nick name

SirPerfluous said:


> Not gonna tinker with xmp settings. also, why enable gdm when I want an uneven cas timing of 15?
> 
> been fiddling for a bit. not very lucky with these I guess. tm5 gives errors at most dram calc settings. Here's where I am for now at 1.42v:
> 
> posts at 3800 cas 14 above 1.48v and has posted with a sub 300 tRFC


Yeah, I should have said more. I meant GDM with tCL 14. 

I have a couple 3600C15 kits and have played with both quite a bit.


----------



## imajescape

i have OC'ed 2 sticks of crucial ballistix from 2666mhz cl16 to 3266mhz 16-19-19-19-37 at 1.24v , seen as 1.3V in hwinfo and bios. didn't expect i could do that lol.


----------



## minal

Can/should memory timings be different between DIMMs/channels?

I have only set DOCP in the BIOS of the C7HWIFI and have no manual memory timings.

I was surprised by this:


----------



## SirPerfluous

Here's where I am for now: 

Dropping to 4-6 instead of 5-7 Got rid of my errors in test 13

Currently at 1.52v dropping any lower gives errors in test 6, 2 and 10

I'm still playing, but I thought I'd update and see if Veii is around. I feel like I'm missing something


----------



## nick name

minal said:


> Can/should memory timings be different between DIMMs/channels?
> 
> I have only set DOCP in the BIOS of the C7HWIFI and have no manual memory timings.
> 
> I was surprised by this:


Yes, for that pair of timings that's normal. Though my board didn't use as high tWRRD.


----------



## minal

nick name said:


> Yes, for that pair of timings that's normal. Though my board didn't use as high tWRRD.


 To be clear, it's normal to have different values per channel for the same timing setting? i.e. tWRRD = 3 (CHA) & 4 (CHB). 

This caught my attention, because to my knowledge there isn't even a way to specify different values in BIOS manually for the same timing.


----------



## SirPerfluous

Now I'm here with a max temp of 42c @1.53v which is the voltage limit for this board :/ Errors if its anything below that.
I've got an x470 gaming 7 coming soon though, maybe I'll get more out of that.

Bandwidth seems a little low to me, 
But I'm gonna run hci or 60 cycles tm5 when I go to bed. Has passed 6 so far. 
I'll work on it more tomorrow, or late tonight if I end up awake.


----------



## nick name

minal said:


> To be clear, it's normal to have different values per channel for the same timing setting? i.e. tWRRD = 3 (CHA) & 4 (CHB).
> 
> This caught my attention, because to my knowledge there isn't even a way to specify different values in BIOS manually for the same timing.


Yes it is normal. And for me it's preferred. The latest BIOS versions break that Auto setting and sets those values very, very high. It's something that I wish was fixed in the latest BIOS versions from ASUS.


----------



## deepor

minal said:


> To be clear, it's normal to have different values per channel for the same timing setting? i.e. tWRRD = 3 (CHA) & 4 (CHB).
> 
> This caught my attention, because to my knowledge there isn't even a way to specify different values in BIOS manually for the same timing.



What you are seeing is strange, I feel. What you could maybe do is, you could try swapping your memory sticks and see what happens to the numbers. Or you could try your memory sticks separately, each one alone by itself. Maybe your sticks are not exactly the same and have a different profile programmed into them?

A related thing I remember, I have a Gigabyte board from years ago where I could do timings for the two channels separately in the BIOS menus. It is an Intel Ivy Bridge system from eight years ago.


----------



## nick name

SirPerfluous said:


> Now I'm here with a max temp of 42c @1.53v which is the voltage limit for this board :/ Errors if its anything below that.
> I've got an x470 gaming 7 coming soon though, maybe I'll get more out of that.
> 
> Bandwidth seems a little low to me,
> But I'm gonna run hci or 60 cycles tm5 when I go to bed. Has passed 6 so far.
> I'll work on it more tomorrow, or late tonight if I end up awake.


Try 
14(tCL)
15(tRCDRD)
14(tRCDWR)
14(tRP)
30(tRAS)
44(tRC)
4(tRDDS)
4(tRDDL)
16(tFAW)
4(tWTRS)
8(tWTRL)
10(tWR)
264(tRFC)
3(tRDRDSCL)
3(tWRWRSCL)
14(tCWL)
6(tRTP)
8(tRDWR)
2(tWRRD)
1(tRDRDSC)
6(tWRWRDD)
6(tWRWRSD)
1(tWRWRSC)
4(tRDRDDD)
4(tRDRDSD)
1(tCKE)

Same voltage.

And there are a couple timings that will be left at Auto in that list.


----------



## minal

nick name said:


> Yes it is normal. And for me it's preferred. The latest BIOS versions break that Auto setting and sets those values very, very high. It's something that I wish was fixed in the latest BIOS versions from ASUS.


Ok, thanks, good to know. I forgot to mention that it's a relatively old BIOS v2203. I've stayed on it because it works fine and I haven't had a reason to upgrade.



deepor said:


> What you are seeing is strange, I feel. What you could maybe do is, you could try swapping your memory sticks and see what happens to the numbers. Or you could try your memory sticks separately, each one alone by itself. Maybe your sticks are not exactly the same and have a different profile programmed into them?
> 
> A related thing I remember, I have a Gigabyte board from years ago where I could do timings for the two channels separately in the BIOS menus. It is an Intel Ivy Bridge system from eight years ago.


I'll keep it in mind in case I have issues, but this build has been fine for over two years and I don't really want to mess with it.  The memory sticks are from a kit (F4-3200C14D-32GTZ) so the specs should be the same. Thanks for mentioning your board with separate channel timings. I had no idea that was a thing, but it makes sense.


----------



## SirPerfluous

Well, tRP 14 Isn't working. Everything else stuck though. I still don't know why. I couldn't get tFAW and friends below 6-8-24 before.

Thanks for the set. is this what works for your kit?


----------



## pipes

I don't why but my RAM Need more than first times test.
Maybe it's damage yet? Need more of 0.03 volts

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## Veii

nick name said:


> Try
> 
> 
> Spoiler
> 
> 
> 
> 14(tCL)
> 15(tRCDRD)
> 14(tRCDWR)
> 14(tRP)
> 30(tRAS)
> 44(tRC)
> 4(tRDDS)
> 4(tRDDL)
> 16(tFAW)
> 4(tWTRS)
> 8(tWTRL)
> 10(tWR)
> 264(tRFC)
> 3(tRDRDSCL)
> 3(tWRWRSCL)
> 14(tCWL)
> 6(tRTP)
> 8(tRDWR)
> 2(tWRRD)
> 1(tRDRDSC)
> 6(tWRWRDD)
> 6(tWRWRSD)
> 1(tWRWRSC)
> 4(tRDRDDD)
> 4(tRDRDSD)
> 1(tCKE)
> 
> 
> Same voltage.
> 
> And there are a couple timings that will be left at Auto in that list.


Change tWRRD 2 to 3 
3*4 SCL or just *4 = 12, tRCD minimum is 14, 2*4=8 is too far away. Should be 3  @SirPerfluous


----------



## kratosatlante

minal said:


> Can/should memory timings be different between DIMMs/channels?
> 
> I have only set DOCP in the BIOS of the C7HWIFI and have no manual memory timings.
> 
> I was surprised by this:


Hello what version of bios are you using?


----------



## SirPerfluous

So for Fun I threw that Rev E kit in my 1200AF build and wound up with this after a couple minutes. think I could get sub 60?


----------



## nick name

SirPerfluous said:


> So for Fun I threw that Rev E kit in my 1200AF build and wound up with this after a couple minutes. think I could get sub 60?


I know that with Ryzen 2000 you could get sub 60ns, but I'm not sure about Ryzen 1000.


----------



## 2600ryzen

nick name said:


> I know that with Ryzen 2000 you could get sub 60ns, but I'm not sure about Ryzen 1000.



1200AF is zen+, I think sub 60ns is possible.


----------



## minal

kratosatlante said:


> Hello what version of bios are you using?


 2203.

Note to linux users: CoreFreq now shows memory timings (in the develop branch, still under active development). https://github.com/cyring/CoreFreq 

It is the only linux utility that I know of with this capability, along with a ton of other low level info and controls.


----------



## Cosminnn

minal said:


> 2203.
> 
> Note to linux users: CoreFreq now shows memory timings (in the develop branch, still under active development). https://github.com/cyring/CoreFreq
> 
> It is the only linux utility that I know of with this capability, along with a ton of other low level info and controls.


I am failing to install it under ClearLinux. Anyway I am not very experienced in Linux, but I can boot timings which are not working in Windows.


----------



## nick name

2600ryzen said:


> 1200AF is zen+, I think sub 60ns is possible.


I didn't even notice the AF. They should definitely shoot for 58ns.


----------



## Veii

SirPerfluous said:


> So for Fun I threw that Rev E kit in my 1200AF build and wound up with this after a couple minutes. think I could get sub 60?


You can, yes
Two questions
- does the 1200AF allow you to set cLDO_VDDP voltage ?
- does the Asus x470 pro have a performance enhancer option or performance bias option, for example CB15/Aida64 or geekbench mode ?

12nm should be able to hit 3734 with ease under 709mV cLDO_VDDP
Interesting is, if the stress is lower on the AF unit and your Rev.E's can hit 3800MT/s

My lapped 1200AF waits for a board to be tested and reviewed 
Even tho its already kinda irrelevant 
Try to hit 3734MT/s with it , you should be able to on 12nm with


----------



## jcpq

I need a little help.
I intend to improve latency.
I have already tested with tCWL 14; tRDWR 8 and tWRRD 3
But it is almost the same.
Any suggestion?


----------



## minal

Cosminnn said:


> I am failing to install it under ClearLinux. Anyway I am not very experienced in Linux, but I can boot timings which are not working in Windows.


And you installed the required development libraries? You can open an issue on github. The CoreFreq developer is very responsive.


----------



## SirPerfluous

Veii said:


> You can, yes
> Two questions
> - does the 1200AF allow you to set cLDO_VDDP voltage ?


Yep, It's isolated under dram timing menu on this board



Veii said:


> does the Asus x470 pro have a performance enhancer option or performance bias option, for example CB15/Aida64 or geekbench mode ?


It does, I get 2 CB15 Options, and a Geekbench/Aida. 



Veii said:


> My lapped 1200AF waits for a board to be tested and reviewed
> Even tho its already kinda irrelevant
> Try to hit 3734MT/s with it , you should be able to on 12nm with


----------



## Veii

SirPerfluous said:


> It does, I get 2 CB15 Options, and a Geekbench/Aida.


Put on Aia64 mode, it should improve L3 cache perf and a bit memory perf. Up to agesa age
Aiad64 mode could add 2ns on memory if it's the old "tweak" but if you have a new agesa and the cinebench gentle one will boost both worlds
Faster L3 cache with lower latency, and better memory latency
Else you add 2ns up to aida64 but it still results in better perf because of the lower L3 access time



SirPerfluous said:


> Why'd you lap it? sub zero? I haven't gone very heavy on the cpu yet so not sure how much heat this little thing is gonna make when I push it to the max, but I can't see it being too much.
> It does really well at low voltage. 1.24v set with llc2 can get me 4Ghz
> 
> My 1200 replaced a lapped fx-6300. Still have that system and its currently running 4.7 with an asus 970 board, And a lapped dark rock pro 4. Max temp it'll ever see is 55c @1.42v
> Could really get more out of it on a board with proper vrm.


Started with lapping the 1700X, out of pure passion and because i noticed at the very first, somehow the contact with the old dark rock pro 3 wasn't well
Although noticed later that the cpu was convex and the cooler was designed for concave intel units = convex too 
The only real contact it had, was on the sides of the CPU
Later recently, that hot 1700X idles at 22c inside the bios 

Yep, just passion to lap the units
It might not make a lot of difference if the contact is great. 
But considering nearly no cooler is designed for convex CPU's but for concave Intel units
The difference is quite significant


----------



## Yuke

Can anyone with latest CL14/3800Mhz overclock on dual rank kit 32gb (b-die) post their settings please?

I cant figure it out for my kit, even 1.52V is not enough with pretty loose timings to get no errors in Karhu/TM5.

Should i increase ClkDrvStr? I've seen that most have it around 60 when using a dual rank kit.

This is the best i can do for now:


----------



## nick name

Yuke said:


> Can anyone with latest CL14/3800Mhz overclock on dual rank kit 32gb (b-die) post their settings please?
> 
> I cant figure it out for my kit, even 1.52V is not enough with pretty loose timings to get no errors in Karhu/TM5.
> 
> Should i increase ClkDrvStr? I've seen that most have it around 60 when using a dual rank kit.
> 
> This is the best i can do for now:


I wanna say that my system uses RTTNOM and sets it to 7 when using dual rank.


----------



## rares495

nick name said:


> I wanna say that my system uses RTTNOM and sets it to 7 when using dual rank.


Really? Does ZenTimings show that?


----------



## usoldier

Hi guys i need a quick recomendation for 32gb using a CH8+3800x what kit should i buy for best performance.


----------



## Veii

usoldier said:


> Hi guys i need a quick recomendation for 32gb using a CH8+3800x what kit should i buy for best performance.


Dual rank 16GB dimms, or mixing A0 and A2 dimms A0/A2/A0/A2 as dimm order

CH8 is Daisy Chain,
Soo unless you know what PCB the dimms are on, don't go with 4 dimms on such a Topology
There are already 16Gb single rank units out there 
The TridentZ Neo's are dual rank , and some neo's ending with C in the model number are HynixCJR

There are 3600C16-16 16 GB dimms for about 260-280$ = 130$ per 16gb 
Which is kinda alright 
But there are also 3866 dimms out there as dual rank set with alright timings
At the end, your PCB you end up will mater the most
B1 or B2, maybe even random hynix or micron kit with B3 made Q1 2020

Its luck based, but dual rank kits is what you are looking for
Or mixing PCBs with one set 40000CL19-19 Viper Steels and one 4400CL19-19 set 
4400 being A2 layout

Ax = Single Rank
Bx = Dual Rank


----------



## mongoled

Veii said:


> Dual rank 16GB dimms, or mixing A0 and A2 dimms A0/A2/A0/A2 as dimm order
> 
> CH8 is Daisy Chain,
> Soo unless you know what PCB the dimms are on, don't go with 4 dimms on such a Topology
> There are already 16Gb single rank units out there
> The TridentZ Neo's are dual rank , and some neo's ending with C in the model number are HynixCJR
> 
> There are 3600C16-16 16 GB dimms for about 260-280$ = 130$ per 16gb
> Which is kinda alright
> But there are also 3866 dimms out there as dual rank set with alright timings
> At the end, your PCB you end up will mater the most
> B1 or B2, maybe even random hynix or micron kit with B3 made Q1 2020
> 
> Its luck based, but dual rank kits is what you are looking for
> Or mixing PCBs with one set 40000CL19-19 Viper Steels and one 4400CL19-19 set
> 4400 being A2 layout
> 
> Ax = Single Rank
> Bx = Dual Rank


Have you done this before A0 & A2 ??

I was going to buy a 5th set of A2, last attempt to get a good second pair and saw your post ...

This current set I am testing is stuggling to get 3800/1900 stable using CL15 ....


----------



## Veii

mongoled said:


> Have you done this before A0 & A2 ??
> 
> I was going to buy a 5th set of A2, last attempt to get a good second pair and saw your post ...
> 
> This current set I am testing is struggling to get 3800/1900 stable using CL15 ....


Recommended people to do it
It works with A0 and A1
A0 and A2 would work even better
But only for Daisy Chain boards

I wait to try it once more on a X570 Aorus Pro (good hw, very bad dual bios design)
But yes, i know it works well out of people's test results here
A2 can take more voltage, and the only way to fix Daisy Chain layout issues - is strong overvolting
Vipers can take a lot under A2 layout and A0 kits are easier too run, soo it's kinda fine 

For illustration purposes,


Spoiler



try to play with this tool
https://www.rapidtables.com/calc/electric/ohms-law-calculator.html
Put in:
1.2v @ 5.94W 

Impedance you influence by ClkDrvStrength and Data Bus Drive Strength
Also by the board design ~ which are many variables
I can't seem to record a gif, but if you change 1.2 to 1.6v you will see that ampere will spike up and powerdraw will spike
But if you fix instead of 2 values, 3 
Putting 1.2v @ 5.94W @ 0.25Ohm 
then decreasing Resistance from 0.25 to 0.2 (similar to what you do with higher ClkDrvStrength) you end up with 6A through the dimms 
Just that's not how it actually works
you not only decrease resistance but also "Multiply" voltage by using higher impedance
soo up voltage from 1.2 to 1.4 here for an extreme example 
We end up to 9.8W @ 7A 

Resistance of A2 PCBs is higher than on A0, ignoring for now that they are short trace layout
Try to change 0.2 ohm now to 0.5ohm, and this drops down to 2.8A @ 3.92W @ 1.4v 
Which means 2 things, to go back to our 7A current we need to do 2 things:
A: overvolt and increase vDIMM to 1.6v, but that only pushes us to 3.2A @ 5.12W
A2: decrease resistance overall , as example 0.3 instead 0.5 Ohm @ 1.4v would push us up to 4.67A @ 6.53W 
or
B: still overvolt memory with 1.6v @ 0.25ohm, resulting in 10W & 6.4A 

As you can see, it clearly is not the 7A at lower Wattage example above, but you can also see that higher resistance PCBs will need more voltage to work 
and lower resistance PCBs you can try, will need less voltage for about the same current (A) 

The same goes and works for the IMC as procODT & vSOC 
low procODT will allow a low vSOC voltage to run without decreasing fed current into it 
But we don't know on both of them the native resistance values
We can only multiply and so decrease resistance by higher impedance.
Higher impedance will pretty much multiply what they call "drive strength" 

And logically here again:
Increasing VDDG IOD increases current 
Increasing vSOC voltage also increases main Ampere current and draws more power
But in order for the unit to have enough current, you often end up better increasing impedance to decrease resistance or change thermals to very low ambiet, in order to decrease resistance

Increasing vDIMM here doesn't only increase voltage resulting in higher DIMM W=Heat
It also decreases Resistance, because more factors come into play, by just pushing higher VDIMM through it
Soo as end result,
- In order for fixing the strong current splitting difference between Two sets of dimm-slots (75-25%) you need to work with voltage and also utilize difference Resistance "units=PCBs" to change it
- Because there is no way, how we can change drive impedance per set of dimm slots, nor can we only overvolt the slave set to match equal Ampere/Current
~ powerconsumption fully put aside

Sorry for the wall with only half-way accuracy
I sadly don't know the resistance values of the PCBs as exact numbers ~ in order to provide solid numbers 
Only voltage to wattage creation. Which is the same for the Infinity fabric
Haven't analysed deeply how much vSOC to Wattage results on the IF
But i know on 2nd gen it was 50W less Powerdraw for -0.05v vSOC (220W down to 180W) and on a 3950X it was about the same between 1.15v and 1.075v (230 down to ~175W)
Threadripper was around 65-70W Fabric only usage under 1.075vSOC


----------



## thomasck

Hi guys, all good?
I discovered I'm having issues and I'd like some help if possible.
I've been using these attached settings since feb/march without any issues, but for some reason yesterday I've started Ram Test/Karhu before making dinner (I do it once a month) and for my surprise I found 01 error within 1h30m, this is at least weird cause I've tested it before few times and nothing was found.
Besides Ram Test I'm getting errors in TM5 1usmus profile too. So the issue is real. 
The specs are 3900x, taichi x370, 2x8gb hyperx predator 4000 cl19, bdie chips. fclk 1867 1:1.
Cpu stock, ram 1.475V, SoC 1.0625, VDDG/IOD 0.950V and VDDP 0.900V. Increasing SoC to 1.07 and VDDP to 0.950 did not help.


Timings,










I know I can just loose some timings, and bump some voltages but I've read many times that adjusting one flag or other would get rid of errors so I'd like some advice before just setting DRAM's recommendation for safe/fast which are a bit more loose. 

Any help is appreciated.


----------



## Veii

thomasck said:


> Besides Ram Test I'm getting errors in TM5 1usmus profile too. So the issue is real.
> The specs are 3900x, taichi x370, 2x8gb hyperx predator 4000 cl19, bdie chips. fclk 1867 1:1.
> Cpu stock, ram 1.475V, SoC 1.0625, VDDG/IOD 0.950V and VDDP 0.900V. Increasing SoC to 1.07 and VDDP to 0.950 did not help.
> 
> Timings
> 
> 
> 
> 
> 
> 
> 
> 
> Any help is appreciated.


Two things are awkward
So you drop near 1.05vSOC ?
Which bios, 6.20A or 6.40

You should be able to put tCWL as 15
Else might need to add tWRRD of at least 3, I'd try 4

You can drop VDDG CCD -25mV and push VDDG IOD +25mV
Taichi would need an IOD bump
Else decrease SOC Loadline once more
And please run y-cruncher all the tests for 3-4 cycles with hwinfo open for soc droop checking
Edit:
The thing is,
If you use tRC Formula=tRCD_WR+tCWL+4+tWR
You end up with 44 as full cycle 
42 as tRC would have worked and you use already -2 
But try to later drop tRCD_WR to 9 or 11
9 would allow you to go down with tRP 12 (9+15 then / 2 avg tRFC delay)
9+15CWL+12WR+4=40
tRAS 28+12 tRP=40 , soo works well 
tRAS=tCL+tWR+tBL (2)
15+12+2=29
Well nearly correct
But you get the reasoning 

I think at the end, tRC40 is too low without any changes on your side


----------



## mongoled

Veii said:


> Recommended people to do it
> It works with A0 and A1
> A0 and A2 would work even better
> But only for Daisy Chain boards
> 
> I wait to try it once more on a X570 Aorus Pro (good hw, very bad dual bios design)
> But yes, i know it works well out of people's test results here
> A2 can take more voltage, and the only way to fix Daisy Chain layout issues - is strong overvolting
> Vipers can take a lot under A2 layout and A0 kits are easier too run, soo it's kinda fine
> 
> For illustration purposes,
> 
> 
> Spoiler
> 
> 
> 
> try to play with this tool
> https://www.rapidtables.com/calc/electric/ohms-law-calculator.html
> Put in:
> 1.2v @ 5.94W
> 
> Impedance you influence by ClkDrvStrength and Data Bus Drive Strength
> Also by the board design ~ which are many variables
> I can't seem to record a gif, but if you change 1.2 to 1.6v you will see that ampere will spike up and powerdraw will spike
> But if you fix instead of 2 values, 3
> Putting 1.2v @ 5.94W @ 0.25Ohm
> then decreasing Resistance from 0.25 to 0.2 (similar to what you do with higher ClkDrvStrength) you end up with 6A through the dimms
> Just that's not how it actually works
> you not only decrease resistance but also "Multiply" voltage by using higher impedance
> soo up voltage from 1.2 to 1.4 here for an extreme example
> We end up to 9.8W @ 7A
> 
> Resistance of A2 PCBs is higher than on A0, ignoring for now that they are short trace layout
> Try to change 0.2 ohm now to 0.5ohm, and this drops down to 2.8A @ 3.92W @ 1.4v
> Which means 2 things, to go back to our 7A current we need to do 2 things:
> A: overvolt and increase vDIMM to 1.6v, but that only pushes us to 3.2A @ 5.12W
> A2: decrease resistance overall , as example 0.3 instead 0.5 Ohm @ 1.4v would push us up to 4.67A @ 6.53W
> or
> B: still overvolt memory with 1.6v @ 0.25ohm, resulting in 10W & 6.4A
> 
> As you can see, it clearly is not the 7A at lower Wattage example above, but you can also see that higher resistance PCBs will need more voltage to work
> and lower resistance PCBs you can try, will need less voltage for about the same current (A)
> 
> The same goes and works for the IMC as procODT & vSOC
> low procODT will allow a low vSOC voltage to run without decreasing fed current into it
> But we don't know on both of them the native resistance values
> We can only multiply and so decrease resistance by higher impedance.
> Higher impedance will pretty much multiply what they call "drive strength"
> 
> And logically here again:
> Increasing VDDG IOD increases current
> Increasing vSOC voltage also increases main Ampere current and draws more power
> But in order for the unit to have enough current, you often end up better increasing impedance to decrease resistance or change thermals to very low ambiet, in order to decrease resistance
> 
> Increasing vDIMM here doesn't only increase voltage resulting in higher DIMM W=Heat
> It also decreases Resistance, because more factors come into play, by just pushing higher VDIMM through it
> Soo as end result,
> - In order for fixing the strong current splitting difference between Two sets of dimm-slots (75-25%) you need to work with voltage and also utilize difference Resistance "units=PCBs" to change it
> - Because there is no way, how we can change drive impedance per set of dimm slots, nor can we only overvolt the slave set to match equal Ampere/Current
> ~ powerconsumption fully put aside
> 
> Sorry for the wall with only half-way accuracy
> I sadly don't know the resistance values of the PCBs as exact numbers ~ in order to provide solid numbers
> Only voltage to wattage creation. Which is the same for the Infinity fabric
> Haven't analysed deeply how much vSOC to Wattage results on the IF
> But i know on 2nd gen it was 50W less Powerdraw for -0.05v vSOC (220W down to 180W) and on a 3950X it was about the same between 1.15v and 1.075v (230 down to ~175W)
> Threadripper was around 65-70W Fabric only usage under 1.075vSOC


Hehehehee, I only asked if you had tried but as you always do you write a wall of text



Dont get me wrong, its great that you do that, just I feel guilty as obviously that takes time and energy, so thanks.

The PVS416G400C9K are guranteed to be A0, just like the PVS416G440C9K are guranteed to be A2 ?

If I go through with this will probably order 1 of each as the shipping from where I intend to buy is expensive so might as well get my monies worth (the cost of shipping one or two items is the same price)...

:thumb:


----------



## Veii

mongoled said:


> Hehehehee, I only asked if you had tried but as you always do you write a wall of text
> 
> Dont get me wrong, its great that you do that, just I feel guilty as obviously that takes time and energy, so thanks.
> 
> The PVS416G400C9K are guranteed to be A0, just like the PVS416G440C9K are guranteed to be A2 ?
> 
> If I go through with this will probably order 1 of each as the shipping from where I intend to buy is expensive so might as well get my monies worth (the cost of shipping one or two items is the same price)...
> :thumb:


Its not a waste or time to teach people
Its a waste of time repeating myself over and over without explanation 
PVS416G400C9K can very rarely, once each red moon be A1
About a 1/1000 units chance. The number is made up but its very very rare
Its A0 yes
PVS416G440C9K so far where 100% A2 
A1 can't run beyond 4200MT/s , but you could maybe hit A3
Which seem to exist but I haven't seen myself anything anywhere 
Maybe vipers are A3 because they used a custom A1/A2 mixture design.
Anywho, they are A2 yes 

High shipping wow
How about places like Joybuy, Aliexpress, TaoBao and eBay ?
Viper are located in Taiwan 
Maybe Gmarket global (korean) could sell them for cheaper


----------



## KedarWolf

61.6 ns.


----------



## jcpq

KedarWolf said:


> 61.6 ns.


Top
Voltage?


----------



## jcpq

1.44v
Hi 
Is it possible to improve anything here?


----------



## KedarWolf

jcpq said:


> Top
> Voltage?


RAM 1.48v, SoC 1.1375v, VDDP .900v, VDDG's .950v and 1.000v.


----------



## thomasck

Veii said:


> Two things are awkward
> So you drop near 1.05vSOC ?
> Which bios, 6.20A or 6.40
> 
> You should be able to put tCWL as 15
> Else might need to add tWRRD of at least 3, I'd try 4
> 
> You can drop VDDG CCD -25mV and push VDDG IOD +25mV
> Taichi would need an IOD bump
> Else decrease SOC Loadline once more
> And please run y-cruncher all the tests for 3-4 cycles with hwinfo open for soc droop checking
> Edit:
> The thing is,
> If you use tRC Formula=tRCD_WR+tCWL+4+tWR
> You end up with 44 as full cycle
> 42 as tRC would have worked and you use already -2
> But try to later drop tRCD_WR to 9 or 11
> 9 would allow you to go down with tRP 12 (9+15 then / 2 avg tRFC delay)
> 9+15CWL+12WR+4=40
> tRAS 28+12 tRP=40 , soo works well
> tRAS=tCL+tWR+tBL (2)
> 15+12+2=29
> Well nearly correct
> But you get the reasoning
> 
> I think at the end, tRC40 is too low without any changes on your side


Hi Veii, I'm in the 6.40 bios.

I'm going to try all that now, but apparently the problem is with the mobo. Both sticks work great in the A2 slot and both give me errors in the B2 slot. They also work fine in the A1 slot. Meh, bad luck.


----------



## Veii

thomasck said:


> Hi Veii, I'm in the 6.40 bios.
> 
> I'm going to try all that now, but apparently the problem is with the mobo. Both sticks work great in the A2 slot and both give me errors in the B2 slot. They also work fine in the A1 slot. Meh, bad luck.


4th slot gives errors or 1st slot ?

Also inspect the board closer next to the first slot if you see any oily residue


----------



## thomasck

Veii said:


> 4th slot gives errors or 1st slot ?
> 
> Also inspect the board closer next to the first slot if you see any oily residue


The 4th one, the B2. I will take a closer look tomorrow as it's dark now. I've seen this oily-ish (like a stain) in this board, or in the previous one. Gonna double check tomorrow morning, can't remember now but I'm 100% sure I've seen it. What about it?


----------



## Veii

thomasck said:


> The 4th one, the B2. I will take a closer look tomorrow as it's dark now. I've seen this oily-ish (like a stain) in this board, or in the previous one. Gonna double check tomorrow morning, can't remember now but I'm 100% sure I've seen it. What about it?


3xx boards start to fail now after 3 years 
but Taichi thread is not quite sure if the pads mixture turns conductive or the high heat of the oily substance, helps them push into little cracks, which increases resistance and make issue with components

Mostly noticeable on the Chipset where it was fixed after cleaning it up and changing the pads
But i personally had two boards which had the same sticky residue, even inside the dimm slots 
It's unclear so far if this thing is conductive ~ but the boards start to fail
Just doublecheck it and maybe WD-40 non oily conductive cleaner , clean it 

The chance that dimm slots "die" is far lower than PCIe slots "breaking" by the GPU sag


----------



## thomasck

Veii said:


> 3xx boards start to fail now after 3 years
> but Taichi thread is not quite sure if the pads mixture turns conductive or the high heat of the oily substance, helps them push into little cracks, which increases resistance and make issue with components
> 
> Mostly noticeable on the Chipset where it was fixed after cleaning it up and changing the pads
> But i personally had two boards which had the same sticky residue, even inside the dimm slots
> It's unclear so far if this thing is conductive ~ but the boards start to fail
> Just doublecheck it and maybe WD-40 non oily conductive cleaner , clean it
> 
> The chance that dimm slots "die" is far lower than PCIe slots "breaking" by the GPU sag


I can't really know for sure as I don't have any spare parts any more. My gpu has been held by a nice thick piece of EVA so no much sagging, perhaps it's even a bit upwards 

I did a quick search using a torch and I can see some of the residue on top of the chipset heat sink, check it out in the spoiler.

Right now I'm testing one stick in the "problematic" slot, the 4th one, full bios stock and no erros so far. Apparently as soon as I set to fclk 1867 etc I get errors in the 4th slot but no errors in the 2nd (A2) one. Not sure if I should open a rma straight away or try something else. 



Spoiler


----------



## Veii

thomasck said:


> I can't really know for sure as I don't have any spare parts any more. My gpu has been held by a nice thick piece of EVA so no much sagging, perhaps it's even a bit upwards
> 
> I did a quick search using a torch and I can see some of the residue on top of the chipset heat sink, check it out in the spoiler.
> 
> Right now I'm testing one stick in the "problematic" slot, the 4th one, full bios stock and no erros so far. Apparently as soon as I set to fclk 1867 etc I get errors in the 4th slot but no errors in the 2nd (A2) one. Not sure if I should open a rma straight away or try something else.
> 
> 
> 
> Spoiler


Ontop is hard to see, it's mostly under where the thermal pads are
ontop the memory dimms also mostly never happens , but it could be on the side and on the side of the cpu socket 
Pads do leak , for other residues i'm not sure
If caps leak, then we do have a serious problem

Try to just increase VDDG IOD and decrease CCD, soo it's a bit of a stronger signal for a further distance
and later try to push ClkDrvStrength also a bit higher


----------



## thomasck

Veii said:


> Ontop is hard to see, it's mostly under where the thermal pads are
> ontop the memory dimms also mostly never happens , but it could be on the side and on the side of the cpu socket
> Pads do leak , for other residues i'm not sure
> If caps leak, then we do have a serious problem
> 
> Try to just increase VDDG IOD and decrease CCD, soo it's a bit of a stronger signal for a further distance
> and later try to push ClkDrvStrength also a bit higher


I've tried the suggestions of all posts, nothing helped. Bumped ram voltage to 1.485V and still, errors with 5 seconds, 1 minute. It's really weird, the pc has been fine since march, and now this. Even more strange is the fact there are no freeze in windows or while gaming, I've just discovered cause last night I decided to run Ram Test while I was preping/having dinner. 

If I keep same settings used for 3733 and set fclk 1800 1:1 tm5 and ramtest go without errors, at least 1st 10 minutes. Also fclk1867 with ram at 1200 (2400mhz) won't give any error.

Anyhow, Amazon sent me off a new pair of the same sticks, it's very unlikely to be them, most likely the mobo.

Edit

I've increased ClkDrvStrength as suggested, from 40 to 60 and TestMem5 reports an error after 6 minutes, which is way better than before.. What is the impact of that change?

Edit 2

It just completed a second run with 1usmus profile. I don't know what to think.

Edit 3

As nothing else was changed, and TM5 passed I kept ClkDrvStrength 60. Then I've decrease the ram voltage from 1.47 to 1.46, tm5 passed. Then from 1.46 to 1.45 tm5 passed. How is this possible?


----------



## SneakySloth

jcpq said:


> 1.44v
> Hi
> Is it possible to improve anything here?



You could try reducing the SCLs to 2-2 or 3-3.


----------



## jcpq

A small update.
tRP 15 to 14 (tRP=tCL-1)
tRC 45 to 44 tRC=tRAS+tRP)
tRCD_WR 15 to 9


----------



## Arpeggio

hello, could someone point me to a stable configuration for Corsair CMK6GX4M2B3200C16 ver 5.39 on bios F21?
My current configuration is 2 CMK6GX4M2B3200C16 chA2 chB2 on Gigabyte X570 Elite + Ryzen 3600.
The only BIOS that works for me is F4g (only XMP enabled and all the rest by default), all recent bios make me crash applications and games every 10/20 minutes on windows 10.

Thank you


----------



## Yuke

Any input for a C14/3800Mhz attempt?

This is stable so far at 1.45V (BIOS). Very bloated system and AIDA sadly runs 70% of its time on my weakest core (Im one of those unlucky bastards where Core 0 = weakest)


----------



## mongoled

Veii said:


> Its not a waste or time to teach people
> Its a waste of time repeating myself over and over without explanation
> PVS416G400C9K can very rarely, once each red moon be A1
> About a 1/1000 units chance. The number is made up but its very very rare
> Its A0 yes
> PVS416G440C9K so far where 100% A2
> A1 can't run beyond 4200MT/s , but you could maybe hit A3
> Which seem to exist but I haven't seen myself anything anywhere
> Maybe vipers are A3 because they used a custom A1/A2 mixture design.
> Anywho, they are A2 yes
> 
> High shipping wow
> How about places like Joybuy, Aliexpress, TaoBao and eBay ?
> Viper are located in Taiwan
> Maybe Gmarket global (korean) could sell them for cheaper


Hey, I didnt say it was a waste of time



The shipping is high in comparative to say Amazon.de

Shipping is 23.86€ (though its express shipping so I get the item within 5 days, there is no option for Economy shipping..)
PVS416G400C9K is 114.26€
PVS416G440C9K is 135.96€

But the price for the modules is good.

So will let my impulse decide later this evening


----------



## mongoled

Yuke said:


> Any input for a C14/3800Mhz attempt?
> 
> This is stable so far at 1.45V (BIOS). Very bloated system and AIDA sadly runs 70% of its time on my weakest core (Im one of those unlucky bastards where Core 0 = weakest)


You have KedarWolf as a reference one page back,

He is using the exact same memory modules that you are using, can you not see that ???

He has also posted a wealth of information going back months of what he has tried and what has worked or not worked.

What are you waiting for? Some one to spoon feed you the information ?

I would understand you (and others like you) for requesting specific assistance for memory modules that are new in which there is no data, but you (and others) have a wealth of data regards the memory modules/ram you are running.

Your best solution is to read, read and read, then experiment, experiment and experiment.

It should be easy as you already have a wealth of other peoples experiences!

Hope you dont take this in a bad way .....

The only thing I would add is that for CL14 you need alot more vDIMM voltage in comparative to CL15!


----------



## Yuke

mongoled said:


> You have KedarWolf as a reference one page back,
> 
> He is using the exact same memory modules that you are using, can you not see that ???
> 
> He has also posted a wealth of information going back months of what he has tried and what has worked or not worked.
> 
> What are you waiting for? Some one to spoon feed you the information ?
> 
> I would understand you (and others like you) for requesting specific assistance for memory modules that are new in which there is no data, but you (and others) have a wealth of data regards the memory modules/ram you are running.
> 
> Your best solution is to read, read and read, then experiment, experiment and experiment.
> 
> It should be easy as you already have a wealth of other peoples experiences!
> 
> Hope you dont take this in a bad way .....
> 
> 
> The only thing I would add is that for CL14 you need alot more vDIMM voltage in comparative to CL15!


Hey, dont worry, im not made out of sugar.

I've seen it but im massively confused that his 2T timings with GDM Off is performing this way. So im hesitant...


----------



## mongoled

Yuke said:


> Hey, dont worry, im not made out of sugar.
> 
> I've seen it but im massively confused that his 2T timings with GDM Off is performing this way. So im hesitant...


Glad to hear that, though many are this day and age (sugar  ).

Jump in with both feet, no need to be hesitant!



Just remember RAM cooling is helpful when increasing voltage past 1.45v ...

** EDIT **
Oh and remember our components are all different even when they are the same model! Ive been through 4 different set of Viper Steel 4400 mhz RAM, only one set of sticks performs like those in my sig, all other "identical" sets are no where near ...


----------



## nick name

rares495 said:


> Really? Does ZenTimings show that?


I used Ryzen Master to check them.


----------



## Veii

Anyone want to try and confirm stability on this set ? :fez:
tCL 14
tRCD WR 10
tRCD RD 14
tRP 12
tRAS 26
tRC 38
tWR 12
tRFC 228-169-104
tRTP 6
tCWL 12

tRDWR can be whatever you want, likely 9 till 11
same for SCL, 2 to 5
As tCWL is 12, GDM is not allowed
VDIMM is up to user choice, likely between 1.48-1.62v required
MT/s shouldn't matter too, pick whatever your kit can run tRCD 14 on
Posting it should be enough, it will be stable if you get it to post 
more relaxed sets tomorrow


----------



## nick name

Veii said:


> Anyone want to try and confirm stability on this set ? :fez:
> tCL 14
> tRCD WR 10
> tRCD RD 14
> tRP 12
> tRAS 26
> tRC 38
> tWR 12
> tRFC 228-169-104
> tRTP 6
> tCWL 12
> 
> tRDWR can be whatever you want, likely 9 till 11
> same for SCL, 2 to 5
> As tCWL is 12, GDM is not allowed
> VDIMM is up to user choice, likely between 1.48-1.62v required
> MT/s shouldn't matter too, pick whatever your kit can run tRCD 14 on
> Posting it should be enough, it will be stable if you get it to post
> more relaxed sets tomorrow


That tRFC might be the challenge.

Edit:
Booted at 1.52V (droops to 1.5V in HWiNFO) no problem. Running TM5 Anta and it BSOD before any errors at around 7 minutes.


----------



## rares495

Veii said:


> Anyone want to try and confirm stability on this set ? :fez:
> tCL 14
> tRCD WR 10
> tRCD RD 14
> tRP 12
> tRAS 26
> tRC 38
> tWR 12
> tRFC 228-169-104
> tRTP 6
> tCWL 12
> 
> tRDWR can be whatever you want, likely 9 till 11
> same for SCL, 2 to 5
> As tCWL is 12, GDM is not allowed
> VDIMM is up to user choice, likely between 1.48-1.62v required
> MT/s shouldn't matter too, pick whatever your kit can run tRCD 14 on
> Posting it should be enough, it will be stable if you get it to post
> more relaxed sets tomorrow


No one can post with such low tRFC. 

EDIT: It actually might work at 3600 or lower.


----------



## nick name

Veii said:


> Anyone want to try and confirm stability on this set ? :fez:
> tCL 14
> tRCD WR 10
> tRCD RD 14
> tRP 12
> tRAS 26
> tRC 38
> tWR 12
> tRFC 228-169-104
> tRTP 6
> tCWL 12
> 
> tRDWR can be whatever you want, likely 9 till 11
> same for SCL, 2 to 5
> As tCWL is 12, GDM is not allowed
> VDIMM is up to user choice, likely between 1.48-1.62v required
> MT/s shouldn't matter too, pick whatever your kit can run tRCD 14 on
> Posting it should be enough, it will be stable if you get it to post
> more relaxed sets tomorrow


Booted at 1.52V (droops to 1.5V in HWiNFO) no problem. Running TM5 Anta and it BSOD before any errors at around 7 minutes. Trying 1.54V now.

Running at 3800MHz.


----------



## Veii

rares495 said:


> No one can post with such low tRFC.
> 
> EDIT: It actually might work at 3600 or lower.
> 
> 
> nick name said:
> 
> 
> 
> Booted at 1.52V (droops to 1.5V in HWiNFO) no problem. Running TM5 Anta and it BSOD before any errors at around 7 minutes. Trying 1.54V now.
> 
> Running at 3800MHz.
Click to expand...

The issue is, nothing else would work.
tRP is low and tRFC is low. It will need more voltage or lower speed. Feel free to trow till 1.6v onto it 

Steppings for tRFC i have:
38, 19 , 9.5 , 4.75, 2,375
Soo we pretty much can only use 38 and 19
247-184-113 is one, but this is neither working with tWR nor tRTP (can't touch these)
285-212-130 is the other one that could work, but it would always need to suspend it 3 times
304 doesn't work at all, 323 doesn't work. 
342-254-156 (190ns @ 3600, 180ns @ 3800) could work again, without breaking the rest


----------



## nick name

Veii said:


> The issue is, nothing else would work.
> tRP is low and tRFC is low. It will need more voltage or lower speed. Feel free to trow till 1.6v onto it
> 
> Steppings for tRFC i have:
> 38, 19 , 9.5 , 4.75, 2,375
> Soo we pretty much can only use 38 and 19
> 247-184-113 is one, but this is neither working with tWR nor tRTP (can't touch these)
> 285-212-130 is the other one that could work, but it would always need to suspend it 3 times
> 304 doesn't work at all, 323 doesn't work.
> 342-254-156 (190ns) could work again, without breaking the rest


1.54V is 13 minutes into TM5 Extreme1 anta777 with no errors.


----------



## Veii

nick name said:


> 1.54V is 13 minutes into TM5 Extreme1 anta777 with no errors.


Good news so far 
I'm unsure on tRDWR because of lower tCWL, but the set applies all the rulesets we've learned without breaking any
tCL 15 set is a broken mess, sit today 3h on it and gave up. Tomorrow i'll finish the more relaxed sets near tRCD 16

It might be possible to make something a bit better, but tCWL is unexplored territory bellow 12
CL14 set technically is GDM ready, except that tCWL has to be 12 here
Will see if i can figure out something that works well as tCWL=tCL
So far, it's only for GDM Disabled


----------



## nick name

Veii said:


> Good news so far
> I'm unsure on tRDWR because of lower tCWL, but the set applies all the rulesets we've learned without breaking any
> tCL 15 set is a broken mess, sit today 3h on it and gave up. Tomorrow i'll finish the more relaxed sets near tRCD 16
> 
> It might be possible to make something a bit better, but tCWL is unexplored territory bellow 12
> CL14 set technically is GDM ready, except that tCWL has to be 12 here
> Will see if i can figure out something that works well as tCWL=tCL
> So far, it's only for GDM Disabled


Here you go friend.


----------



## mongoled

nick name said:


> Here you go friend.


Huh TM5 3 cycles, 59 min ??

Whats going on there ?


----------



## Veii

nick name said:


> Here you go friend.
> 
> 
> mongoled said:
> 
> 
> 
> Huh TM5 3 cycles, 59 min ??
> 
> Whats going on there ?
Click to expand...

Thanks 
anta test should take 1:30h equal to TM5 1usmus_v3 20 cycles
They have the equal goal just the testing methodology is a bit different @nick name , i'm happy that this set is fast
And it would be good to have an Aida64 latency test too next to it 
But this is on GDM enabled 
Which is an issue 
GDM forces tCWL=tCL - autocorrects it
It should be without GDM 

I'm happy that these vipers can do tRCD 14 tho 
tRC ruleset breaks now with tCWL 14, but then it passes on 16GB 
tRC can be after all -2 on 16gb units

Make some benchmarks and retest the set please with GDM off
Be it 1T or 2T 
I can't submit/share it that way, as autocorrection happens on tCWL


----------



## nick name

Veii said:


> Thanks
> anta test should take 1:30h equal to TM5 1usmus_v3 20 cycles
> They have the equal goal just the testing methodology is a bit different
> @nick name , i'm happy that this set is fast
> And it would be good to have an Aida64 latency test too next to it
> But this is on GDM enabled
> Which is an issue
> GDM forces tCWL=tCL - autocorrects it
> It should be without GDM
> 
> I'm happy that these vipers can do tRCD 14 tho
> tRC ruleset breaks now with tCWL 14, but then it passes on 16GB
> tRC can be after all -2 on 16gb units
> 
> Make some benchmarks and retest the set please with GDM off
> Be it 1T or 2T
> I can't submit/share it that way, as autocorrection happens on tCWL


Well darn it. I can tell you this kit won't do 1T GDM off. 

And I've never read anywhere about GDM changing tCWL to tCL. What literature is that from?

And the Aida latency was 63ns first run. 62.9ns second run. And then settled at 62.8ns last few runs.


----------



## rares495

Veii said:


> Thanks
> anta test should take 1:30h equal to TM5 1usmus_v3 20 cycles
> They have the equal goal just the testing methodology is a bit different
> @nick name , i'm happy that this set is fast
> And it would be good to have an Aida64 latency test too next to it
> But this is on GDM enabled
> Which is an issue
> GDM forces tCWL=tCL - autocorrects it
> It should be without GDM
> 
> I'm happy that these vipers can do tRCD 14 tho
> tRC ruleset breaks now with tCWL 14, but then it passes on 16GB
> tRC can be after all -2 on 16gb units
> 
> Make some benchmarks and retest the set please with GDM off
> Be it 1T or 2T
> I can't submit/share it that way, as autocorrection happens on tCWL


Tried this set but as usual my kit won't do RCDRD 14 no matter what and requires 1.58V to not bsod instantly. Seems way faster than my standard timings (62.2 vs 62.8 ns); 61.0 ns in "fast degradation" mode(4725MHz manual on two cores) vs ~61.3 ns with my standard timings.


----------



## Veii

nick name said:


> Well darn it. I can tell you this kit won't do 1T GDM off.
> 
> And I've never read anywhere about GDM changing tCWL to tCL. What literature is that from?
> 
> And the Aida latency was 63ns first run. 62.9ns second run. And then settled at 62.8ns last few runs.


I have to browse through the documents again. It was on an Samsung JEDEC sheet
GDM changes:
tCWL=tCL
uses tCKE
allows tRTP only be an even number
and i'm a bit unsure still on the first 4 primaries till tRAS (rounding up)

But i'm pretty sure on tCL=tCWL , usually ZenTimings should've detected that
Maybe upgrade to 1.1.0 and recheck
One thing that also is awkward, is your PowerDown mode
Normal one for 4 dimms, Alternative is for 2 dimms 
Not going to judge on SD, DD's as people still have random results with these

Aida64 latency is a bit high tho
I'd suspect sub 61ns
GDM off 2T would work too, just tCWL 14 would break one ruleset
it would result in tRC 40
While it might pass with tRC -2 for Single Rank, it's not "perfect" yet with tCWL 14 :/

A2 Vipers with a lot of ClkDrvStrength should get GDM disabled :thinking:
I mean you pretty much have a new stable set, soo you can test what it needs to get GDM off 
To what i remember GDM adds exactly 2ns , you might be sub 61ns already ~ IF you get 1T to work
2T should be about equal to 1T when no autocorrection happens

This all assumes i'm right with GDM, but i'm pretty sure it did.
We'll figure it out later, tCWL 11 would break it for sure and tCWL 16 too 
tCWL 14 might be just borderline fine ~ although it should be 12 without GDM


----------



## Veii

rares495 said:


> Tried this set but as usual my kit won't do RCDRD 14 no matter what and requires 1.58V to not bsod instantly. Seems way faster than my standard timings (62.2 vs 62.8 ns); 61.0 ns in "fast degradation" mode(4725MHz on two cores)


Try tRCD_WR 9 , tRCD_RD 15 to average it out
Problem is, tRCD_WR 9 breaks it 
i can't let you use odd tWR to offset it ~ i think even with GDM disabled, it doesn't let me use tWR 13
Retry with 2T instead 1T 

Someday we'll figure it out, but odd number tRCD breaks calculation 
Main issue is that tWR can't be odd, even if tRTP can and we can somehow work to get tRP be an exact even number
Sit on it today along time ,, but unless tWR can be an odd number ~ there is no way how it can work with tRCD 15
Always end up with tRP as .5 value
Same for tCL 15, doesn't work without having another odd number ~ which must be tWR. 

Well anyways , try tRCD_WR 9 - for tRP at least to be correct 
tRCD_RD 15 with tRCD_WR 8 pushes required tRP as 11.5 
tRP 12 should work, but then that odd _WR breaks tRC math
If one little thing is off, it needs a whole redesign


----------



## rares495

Veii said:


> Try tRCD_WR 9 , tRCD_RD 15 to average it out
> Problem is, tRCD_WR 9 breaks it
> i can't let you use odd tWR to offset it ~ i think even with GDM disabled, it doesn't let me use tWR 13
> Retry with 2T instead 1T
> 
> Someday we'll figure it out, but odd number tRCD breaks calculation
> Main issue is that tWR can't be odd, even if tRTP can and we can somehow work to get tRP be an exact even number
> Sit on it today along time ,, but unless tWR can be an odd number ~ there is no way how it can work with tRCD 15
> Always end up with tRP as .5 value
> Same for tCL 15, doesn't work without having another odd number ~ which must be tWR.
> 
> Well anyways , try tRCD_WR 9 - for tRP at least to be correct
> tRCD_RD 15 with tRCD_WR 8 pushes required tRP as 11.5
> tRP 12 should work, but then that odd _WR breaks tRC math
> If one little thing is off, it needs a whole redesign


Yeah, can't use odd tWR or tCWL>12. I'll try 2T. Problem is that forces GDM on.

I need to buy a better memory kit though this isn't half bad for $120. Perhaps I'll get that sexy F4-4400C19D-16GTZKK if the price makes sense vs Viper steel 4400.


----------



## rares495

rares495 said:


> Yeah, can't use odd tWR or tCWL>12. I'll try 2T. Problem is that forces GDM on.
> 
> I need to buy a better memory kit though this isn't half bad for $120. Perhaps that I'll get that sexy F4-4400C19D-16GTZKK if the price makes sense vs Viper steel 4400.


Nevermind. It doesn't force GDM on. Latency decreased a bit, 62.1 vs 62.2 though that might be run to run variance.


----------



## nick name

Veii said:


> I have to browse through the documents again. It was on an Samsung JEDEC sheet
> GDM changes:
> tCWL=tCL
> uses tCKE
> allows tRTP only be an even number
> and i'm a bit unsure still on the first 4 primaries till tRAS (rounding up)
> 
> But i'm pretty sure on tCL=tCWL , usually ZenTimings should've detected that
> Maybe upgrade to 1.1.0 and recheck
> One thing that also is awkward, is your PowerDown mode
> Normal one for 4 dimms, Alternative is for 2 dimms
> Not going to judge on SD, DD's as people still have random results with these
> 
> Aida64 latency is a bit high tho
> I'd suspect sub 61ns
> GDM off 2T would work too, just tCWL 14 would break one ruleset
> it would result in tRC 40
> While it might pass with tRC -2 for Single Rank, it's not "perfect" yet with tCWL 14 :/
> 
> A2 Vipers with a lot of ClkDrvStrength should get GDM disabled :thinking:
> I mean you pretty much have a new stable set, soo you can test what it needs to get GDM off
> To what i remember GDM adds exactly 2ns , you might be sub 61ns already ~ IF you get 1T to work
> 2T should be about equal to 1T when no autocorrection happens
> 
> This all assumes i'm right with GDM, but i'm pretty sure it did.
> We'll figure it out later, tCWL 11 would break it for sure and tCWL 16 too
> tCWL 14 might be just borderline fine ~ although it should be 12 without GDM


Oh, I'm not using Vipers. I'm using the TridentZ 4400C19 kit. 

And the white papers say tCWL has to beven not that it gets set to tCL. 

Besides if tCWL got set to tCL when using GDM then I wouldn't need to raise tRDWR to 10 when I lower tCWL to 12.


----------



## Veii

rares495 said:


> Nevermind. It doesn't force GDM on. Latency decreased a bit, 62.1 vs 62.2 though that might be run to run variance.


Eehm
Compare this to your 61ns picture
especially the Cache :thinking: 
here Read and Copy are better by a big chunk
Perfect set would put Write to 30400MB/s. In perfect scenarios we would also hit 60800MB/s on Read, but the architecture here is the issue.


----------



## rares495

Veii said:


> Eehm
> Compare this to your 61ns picture
> especially the Cache :thinking:
> here Read and Copy are better by a big chunk
> Perfect set would put Write to 30400MB/s. In perfect scenarios we would also hit 60800MB/s on Read, but the architecture here is the issue.


61ns is dual core. That fks lots of things except for latency cuz write/read bandwidth is influenced by the CPU cores/frequency. Can't really compare. Perhaps I'll try to run it on 8 cores at a lower frequency like 4650 or something.


----------



## Veii

nick name said:


> Oh, I'm not using Vipers. I'm using the TridentZ 4400C19 kit.
> And the white papers say tCWL has to be even not that it gets set to tCL.
> Besides if tCWL got set to tCL when using GDM then I wouldn't need to raise tRDWR to 10 when I lower tCWL to 12.


Last point makes sense, hmmm
It should break with tCWL 14 anyways.
I wonder :thinking:

But even tWR bothers me . . . 
I can't get tCL 15, tRCD 15 sets to work that way :wheee:


----------



## nick name

rares495 said:


> Yeah, can't use odd tWR or tCWL>12. I'll try 2T. Problem is that forces GDM on.
> 
> I need to buy a better memory kit though this isn't half bad for $120. Perhaps I'll get that sexy F4-4400C19D-16GTZKK if the price makes sense vs Viper steel 4400.


I can only recall seeing one person with a Viper kit that can run 3800 14-14-14-14 and at 1T GDM off too. Pretty much every 4400C19 Viper kit I can remember seeing performed the same as a 3600C15 kit. 

And the TridentZ 4400C19 is $20 cheaper than what I paid a month ago. And folks are saying prices are going to continue to drop.


----------



## Veii

rares495 said:


> 61ns is dual core. That fks lots of things except for latency cuz write/read bandwidth is influenced by the CPU cores/frequency. Can't really compare. Perhaps I'll try to run it on 8 cores at a lower frequency like 4650 or something.


You got me haha
Nah it's fine 
Soon 1usmus should release his ClockTuner-Ryzen tool, then you can play with it
CCX Delta difference on 6c CCX/12c is 100mV , on 8c CCX/16c it should be 75mV 

For now i was just curious if that set works, especially that low tRFC which it requires
Got my information 
Will finish tomorrow more sets, which are easier to run 
but i have no idea how to work with tCL 15, tRCD 15 
EDIT:
I might push one more test round with tCWL 10 out there
We'll see if it's necessary


----------



## nick name

The Read bandwidth in the 1T the screenshot is higher than the average. The average of several runs is closer to 61300 MB/s.


----------



## nick name

Oh and I get a lower latency when I use a static OC of 45 CCD1 and 43.5 CCD2. It drops below 62ns.


----------



## rares495

nick name said:


> Oh and I get a lower latency when I use a static OC of 45 CCD1 and 43.5 CCD2. It drops below 62ns.


Yup. This is also a CPU frequency "contest".


----------



## Veii

nick name said:


> The Read bandwidth in the 1T the screenshot is higher than the average. The average of several runs is closer to 61300 MB/s.


I'm strongly confused. How can you hit 61800MB/s without BLCK OC when the maximum is 60800MB/s :thinking:
Are these Dual Rank by any chance ?


nick name said:


> Oh and I get a lower latency when I use a static OC of 45 CCD1 and 43.5 CCD2. It drops below 62ns.


Yep you get some boost on a static OC


----------



## nick name

Veii said:


> I'm strongly confused. How can you hit 61800MB/s without BLCK OC when the maximum is 60800MB/s :thinking:
> Are these Dual Rank by any chance ?
> Yep you get some boost on a static OC


No BCLK and not dual-rank but I am using BankGroupSwap. I grabbed a screen before I starting re-running the Write test and it never hit that number again and almost every run was above 61000 MB/s with maybe two runs at 60800 MB/s but I'd say an average of all at close to 61300 MB/s.

I enable BankGroupSwap for the extra bandwidth and I don't care about the few extra FPS in games I play.

Edit:
Just did more runs after several reboots and I haven't seen numbers as high as I did. All much more close together around 60800 MB/s ~ 61100 MB/s.


----------



## nick name

rares495 said:


> Yup. This is also a CPU frequency "contest".


You know it's funny. The latency doesn't drop until I get to 45 on CCD1. If I use 44.75 it's higher than 63ns and then once I get to 45 on CCD1 it drops below 62ns. I know we're talking about 1ns, but it's funny.


----------



## Veii

nick name said:


> No BCLK and not dual-rank but I am using BankGroupSwap. I grabbed a screen before I starting re-running the Write test and it never hit that number again and almost every run was above 61000 MB/s with maybe two runs at 60800 MB/s but I'd say an average of all at close to 61300 MB/s.
> 
> I enable BankGroupSwap for the extra bandwidth and I don't care about the few extra FPS in games I play.
> 
> Edit:
> Just did more runs after several reboots and I haven't seen numbers as high as I did. All much more close together around 60800 MB/s ~ 61100 MB/s.


mm~
To what i learned, is that Alt should be used for 2 dimms and Normal one for 4 dimms

You can try to drop tRDWR to 9 and tWRRD up to 3.
It should still be +2 of tRCD_RD/2=7, soo i think it can work 
Well, i might make another even more extreme set for you to try tmr. But this current set of timings should be scaleable up in MT/s without breaking 


nick name said:


> You know it's funny. The latency doesn't drop until I get to 45 on CCD1. If I use 44.75 it's higher than 63ns and then once I get to 45 on CCD1 it drops below 62ns. I know we're talking about 1ns, but it's funny.


This is likely because of the CCX delta
There was always something awkward in per CCX OC, noticed around March.
Gladly 1usmus seems like hit the same research pattern on his ClockTunerRyzen Tool ~ soo this anomaly is pretty much a confirmed thing 
Different core size of CCX scale with a different delta between them
There are good and bad CCD's but between CCX, there is a frequency delta ~ like an own characteristic of it

6core CCX liked 75-100mhz in between, while for the with equally bad CCX "founders" 3600 ~ 100Mhz delta worked better and it let me push it beyond 4.2
Else it was pretty much was limited to 4175, hit 4275 @ 1.25v AVX after figuring out the CCX Delta in between 
This likely could be your case, a tiny instability between them ~ or let's just say a "sync" issue
try 150mhz between them with 75 between CCDs, else just 50 between CCDs and 100 between CCX


----------



## nick name

Veii said:


> mm~
> To what i learned, is that Alt should be used for 2 dimms and Normal one for 4 dimms
> 
> You can try to drop tRDWR to 9 and tWRRD up to 3.
> It should still be +2 of tRCD_RD/2=7, soo i think it can work
> Well, i might make another even more extreme set for you to try tmr. But this current set of timings should be scaleable up in MT/s without breaking
> 
> This is likely because of the CCX delta
> There was always something awkward in per CCX OC, noticed around March.
> Gladly 1usmus seems like hit the same research pattern on his ClockTunerRyzen Tool ~ soo this anomaly is pretty much a confirmed thing
> Different core size of CCX scale with a different delta between them
> There are good and bad CCD's but between CCX, there is a frequency delta ~ like an own characteristic of it
> 
> 6core CCX liked 75-100mhz in between, while for the with equally bad CCX "founders" 3600 ~ 100Mhz delta worked better and it let me push it beyond 4.2
> Else it was pretty much was limited to 4175, hit 4275 @ 1.25v AVX after figuring out the CCX Delta in between
> This likely could be your case, a tiny instability between them ~ or let's just say a "sync" issue
> try 150mhz between them with 75 between CCDs, else just 50 between CCDs and 100 between CCX


When running dual-rank I can't seem to use BankGroupSwap. I haven't tried thoroughly enough to say it's impossible for me though. Or maybe that is a thing.

Where I got my info is from that AMD write up a while back.

https://community.amd.com/community...emory-oc-showdown-frequency-vs-memory-timings

And I can't set tRDWR less than 10 with tCWL at 12. I've tried. Sad face.


----------



## pipes

With setting in screenshot can boot but Stick at BIOS tuf screen









Inviato dal mio MI 9 utilizzando Tapatalk


----------



## pipes

tuf and asus are done with me, last time I buy asus cards ...

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## nick name

pipes said:


> tuf and asus are done with me, last time I buy asus cards ...
> 
> Inviato dal mio MI 9 utilizzando Tapatalk


From what I've gathered it's the TUF boards.


----------



## KedarWolf

SCLs at 2.


----------



## werks

Hey guys,

any improvements or changes that can be done to my timings?

they are e-die, so the tRC, tRCDRD are maxed out i think


----------



## pipes

nick name said:


> From what I've gathered it's the TUF boards.


Wich board do you use?

Inviato dal mio MI 9 utilizzando Tapatalk


----------



## thomasck

@Veii looks like playing with ClkDrvStr, AddrCmd, CsOdt and Cke solved the issue. Also allowed me to reduce the voltage from 1.47 to 1.455.










Any consideration within the AddrCmdSetup/CsOdt/Cke being set to 63 63 63?


----------



## nick name

pipes said:


> Wich board do you use?
> 
> Inviato dal mio MI 9 utilizzando Tapatalk


I'm running a Crosshair VII and it's been great. Are you on the latest BIOS? I've heard some say they found it very helpful when dealing with RAM.


----------



## Eder

KedarWolf said:


> SCLs at 2.


Fantastic, will try your settings tonight. I really had doubts about buying these sticks (hate rgb) but they keep on amazing me.


----------



## KedarWolf

Eder said:


> Fantastic, will try your settings tonight. I really had doubts about buying these sticks (hate rgb) but they keep on amazing me.


You on MSI X570 motherboard?

I can only get that with AGESA 1.0.0.5 BIOS found here.

https://station-drivers.com/index.p...570-unify-ms7c35&catid=268&Itemid=169&lang=en

Oh, and I'm going to PM you a question if it's okay.


----------



## pipes

nick name said:


> I'm running a Crosshair VII and it's been great. Are you on the latest BIOS? I've heard some say they found it very helpful when dealing with RAM.


after having hacked the previous card to try the flashback with flashrom, received the replacement card from amazon, the card mounted the bios version which in my opinion gives better performance with my configuration ... yesterday I tried to update the bios to last version I found myself in the same problem as the previous card (I hoped it would not happen again) practically overclock dram equal to zero or at least to 3800 cl15 where I was able with the bios 1407 version to keep my patriot 4000 cl19, now with the latest version of bios 2607 I can't and therefore I find myself unable to use the parameters that ryzen dram calculator sets me both fast and normal.


----------



## SirPerfluous

has passed 10 cycles so far, gonna run 50 more tonight.

Should I shoot for lower tRAS too?
this is at 1.53v 

new board seems to talk to the umc better


----------



## t4t3r

SirPerfluous said:


> has passed 10 cycles so far, gonna run 50 more tonight.
> 
> Should I shoot for lower tRAS too?
> this is at 1.53v
> 
> new board seems to talk to the umc better


What pcb are your sticks on?


----------



## SirPerfluous

t4t3r said:


> What pcb are your sticks on?


A2


----------



## jcpq

SirPerfluous said:


> has passed 10 cycles so far, gonna run 50 more tonight.
> 
> Should I shoot for lower tRAS too?
> this is at 1.53v
> 
> new board seems to talk to the umc better


1.53v it is not much?

Can it always be used?


----------



## t4t3r

SirPerfluous said:


> A2


Thanks. I must've gotten some poor A2 sticks in my 3600C15 kit. Maybe need to test further. I have another 3600C15 kit that is a little older on A0/A1 and it does tighter timings. I think I have a 3200C14 A2 kit that does tighter timings than the 3600C15 A2....


----------



## crakej

pipes said:


> after having hacked the previous card to try the flashback with flashrom, received the replacement card from amazon, the card mounted the bios version which in my opinion gives better performance with my configuration ... yesterday I tried to update the bios to last version I found myself in the same problem as the previous card (I hoped it would not happen again) practically overclock dram equal to zero or at least to 3800 cl15 where I was able with the bios 1407 version to keep my patriot 4000 cl19, now with the latest version of bios 2607 I can't and therefore I find myself unable to use the parameters that ryzen dram calculator sets me both fast and normal.


I have the Patriot's on my CH7 - since the new AGESA Combo 1004 (worse with 1006) I can not attain same results as before. I could do XMP 4400 - can't do it now. I could boot with my FCLK @ 1900 - I can't do that now. I just went back a few bios versions to experiment and was able to do those timings again. I can't figure out what they changed. I'm maxing out at 3733MTs currently.


----------



## treestar

crakej said:


> I can't figure out what they changed.


Perhaps this? https://www.overclock.net/forum/13-...membench-0-8-dram-bench-965.html#post28592274


----------



## crakej

treestar said:


> Perhaps this? https://www.overclock.net/forum/13-...membench-0-8-dram-bench-965.html#post28592274


Thanks! - interesting


----------



## heptilion

KedarWolf said:


> SCLs at 2.


I just ran these timing on my system on 3733 and got 64.2ns. could 3733 to 3800 make this much of an impact?


----------



## rares495

heptilion said:


> I just ran these timing on my system on 3733 and got 64.2ns. could 3733 to 3800 make this much of an impact?



3800 but also the CPU.


----------



## heptilion

rares495 said:


> 3800 but also the CPU.


Yeah maybe but with these timings ive been running stable for some time i get slightly lower latency so not sure whats what.


----------



## rares495

heptilion said:


> Yeah maybe but with these timings ive been running stable for some time i get slightly lower latency so not sure whats what.



Try a manual CPU OC.


----------



## nick name

Anyone else worried about how the new 3080 or 3090 Founders cards are going to **** with RAM overclocks? Those cards look like they're gonna cook RAM.


----------



## Jeffrey Kistler

Managed to get under 100s for the first time after pushing 1.5 vdimm and adjusting timings, haven't tested stability


----------



## deepor

nick name said:


> Anyone else worried about how the new 3080 or 3090 Founders cards are going to **** with RAM overclocks? Those cards look like they're gonna cook RAM.



The graphics card manufacturers will do their own custom coolers that are more traditional and not like Nvidia's reference model, you could get one of those.


----------



## SneakySloth

Got trcdWR down to 8(from 14) and tRC to 36 (from 42). Currently tested with Karhu at 30k and TM5 1usmusv3 at 20 cycles. I'm going to let tm5 run overnight to further test stability but I'm fairly sure this is stable.




Spoiler


----------



## Jeffrey Kistler

SneakySloth said:


> Got trcdWR down to 8(from 14) and tRC to 36 (from 42). Currently tested with Karhu at 30k and TM5 1usmusv3 at 20 cycles. I'm going to let tm5 run overnight to further test stability but I'm fairly sure this is stable.
> 
> 
> 
> 
> Spoiler


Are you at your chips limit? You could probably get below 62 ns at 4.4


----------



## rares495

Jeffrey Kistler said:


> Are you at your chips limit? You could probably get below 62 ns at 4.4



He won't get below with GDM enabled.


----------



## SneakySloth

Jeffrey Kistler said:


> Are you at your chips limit? You could probably get below 62 ns at 4.4



Not really. Thats 4.3 @ 1.160v prime95 small fft avx2 stable. So I can definitely push it up to 4.5 ghz I believe and stay within safe voltages. I did manage to get 61.9 while in safe mode but this is normal windows mode and consistent at 62.2.


----------



## Jeffrey Kistler

Nice


----------



## rares495

Jeffrey Kistler said:


> Nice



The 3600 is not a 3900X.


----------



## Jeffrey Kistler

You are right sir


----------



## SneakySloth

rares495 said:


> The 3600 is not a 3900X.



Apart from aiming for disabling GDM, anything else I could do to tighten the timings further?


----------



## rares495

SneakySloth said:


> Apart from aiming for disabling GDM, anything else I could do to tighten the timings further?



tRTP 6 or 8
tRDWR 10
tWRRD 1
tRFC lower, maybe 240-178-110 or something similar but it will autocorrect for better sync anyway


Maybe try tRCDRD 14 with 1.5V but that's pretty much it.


----------



## Jeffrey Kistler

dropping twr


----------



## mongoled

rares495 said:


> tRTP 6 or 8
> tRDWR 10
> tWRRD 1
> tRFC lower, maybe 240-178-110 or something similar but it will autocorrect for better sync anyway
> 
> 
> Maybe try tRCDRD 14 with 1.5V but that's pretty much it.


He may have to increase tCWL to 14 with those changes....


----------



## rares495

mongoled said:


> He may have to increase tCWL to 14 with those changes....



Don't think so because tRDWR 10 will allow tCWL 12.


----------



## Veii

SneakySloth said:


> Got trcdWR down to 8(from 14) and tRC to 36 (from 42). Currently tested with Karhu at 30k and TM5 1usmusv3 at 20 cycles. I'm going to let tm5 run overnight to further test stability but I'm fairly sure this is stable.


Either get tRCD_RD down to 14 or push it up to 16 with tRP 12 & tRAS 26
Anyways, at the end you have to get tRP 12 to work ~ only VDIMM will fail here
tRFC 252 was fine, but tRTP needs to be lower, 8 or 6

If you want to replicate this set, you need to go down to tRCD_WR 14 in order for everything to match up
Then you can run tRFC 240 or even 228 with tRTP 6 
Credits go to nick name for testing and confirming stability 

Your key issue here is just tRAS 26 and tRP which needs to be 12
Try for now that and push tRCD_RD 16 
Unless you out of random can run this tight tRCD_RD 14 set down bellow
SCL is PCB exclusive, soo ignore it for now


----------



## nick name

deepor said:


> The graphics card manufacturers will do their own custom coolers that are more traditional and not like Nvidia's reference model, you could get one of those.


The few I've seen also seem to move much more air through the backplate (at the DIMMs) this go around. Not as much as the Founders, but it seems to be in their design as well.


----------



## nick name

Veii said:


> Either get tRCD_RD down to 14 or push it up to 16 with tRP 12 & tRAS 26
> Anyways, at the end you have to get tRP 12 to work ~ only VDIMM will fail here
> tRFC 252 was fine, but tRTP needs to be lower, 8 or 6
> 
> If you want to replicate this set, you need to go down to tRCD_WR 14 in order for everything to match up
> Then you can run tRFC 240 or even 228 with tRTP 6
> Credits go to nick name for testing and confirming stability
> 
> Your key issue here is just tRAS 26 and tRP which needs to be 12
> Try for now that and push tRCD_RD 16
> Unless you out of random can run this tight tRCD_RD 14 set down bellow
> SCL is PCB exclusive, soo ignore it for now


I made two attempts to test that setup overnight. The first attempt was without a fan and the first error came when the DIMMs hit about 44*C. The second night I turned the fan back on and it passed, but the DIMMs didn't get above 40*C. The first night was at 1.54V and the second was at 1.55V. I didn't realize I still had the voltage at 1.55V from a benchmarking session earlier in the day.


----------



## mongoled

So tRCDRD @14 (3800mzh) is only possible with GDM enabled ???


----------



## Veii

mongoled said:


> So tRCDRD @14 (3800mzh) is only possible with GDM enabled ???


So far 
No one got that set stable without GDM


----------



## Veii

nick name said:


> I made two attempts to test that setup overnight. The first attempt was without a fan and the first error came when the DIMMs hit about 44*C. The second night I turned the fan back on and it passed, but the DIMMs didn't get above 40*C. The first night was at 1.54V and the second was at 1.55V. I didn't realize I still had the voltage at 1.55V from a benchmarking session earlier in the day.


mmm yes 
we know B-Dies change to get unstable is 42 and higher
When it will trigger is random
Either you have 0 headroom left and sensors have a 2c readout issue
or you have a tiny tiny bit of headroom still left with your current cooling solution 

Although someone should tell me again that memory cooling doesn't matter :wheee:
I wonder how worse it will be with Ampere's FE stock fan which pumps up the heat perfectly over the memory modules
Hopefully 4th gen will finally introduce 2x and 4x mode ~ soo our tRFC2 & tRFC4 does more than just help with other timings 
It would help a lot, for people who OC memory or have thermal constrains :handlebar


----------



## nick name

Veii said:


> mmm yes
> we know B-Dies change to get unstable is 42 and higher
> When it will trigger is random
> Either you have 0 headroom left and sensors have a 2c readout issue
> or you have a tiny tiny bit of headroom still left with your current cooling solution
> 
> Although someone should tell me again that memory cooling doesn't matter :wheee:
> I wonder how worse it will be with Ampere's FE stock fan which pumps up the heat perfectly over the memory modules
> Hopefully 4th gen will finally introduce 2x and 4x mode ~ soo our tRFC2 & tRFC4 does more than just help with other timings
> It would help a lot, for people who OC memory or have thermal constrains :handlebar


Yeah, with tRFC as low as it is I can't imagine temp not being a problem. I just wanted to see how much of an issue when I tested without the fan. As soon as it hit temp it threw an error. 

And yeah -- the new 3080/3090 cards seem like they're gonna be a problem. Even the AIB cards, but definitely the Founders.


----------



## rares495

nick name said:


> I made two attempts to test that setup overnight. The first attempt was without a fan and the first error came when the DIMMs hit about 44*C. The second night I turned the fan back on and it passed, but the DIMMs didn't get above 40*C. The first night was at 1.54V and the second was at 1.55V. I didn't realize I still had the voltage at 1.55V from a benchmarking session earlier in the day.


That kit is so sexyyyyyyy I want one


----------



## nick name

rares495 said:


> That kit is so sexyyyyyyy I want one


They're $35 cheaper than they were a month ago. $159 now at Newegg.

https://www.newegg.com/g-skill-16gb-288-pin-ddr4-sdram/p/N82E16820232621


----------



## rares495

nick name said:


> They're $35 cheaper than they were a month ago. $159 now at Newegg.
> 
> https://www.newegg.com/g-skill-16gb-288-pin-ddr4-sdram/p/N82E16820232621


I'm $159.99 too short.


----------



## nick name

rares495 said:


> I'm $159.99 too short.


I feel ya.


----------



## Veii

nick name said:


> Yeah, with tRFC as low as it is I can't imagine temp not being a problem. I just wanted to see how much of an issue when I tested without the fan. As soon as it hit temp it threw an error.
> 
> And yeah -- the new 3080/3090 cards seem like they're gonna be a problem. Even the AIB cards, but definitely the Founders.


Some people mention, it should be mounted vertically 
The kingpin 3090 looks funny 

Also, hey 228 / 120ns was unheard before ~ it didn't post for people, even with CL12 
I'll gladly take the crown on that till someone shows it lower and stable :graduated

Hmm, can you boot up CL12 under 1.7v ?
Want to try something a bit faster than this  

Need people with dual rank 
Looking at @KedarWolf - to confirm stability on the same pattern creation just for DR 

And later people with Micron Rev.E kits
Library of timings does grow
Unsure if i have the knowledge of making a calculation sheet for such 
~ but i think i have figured out the method to make presets following all the known rulesets out there
Only tRRD_S and tWR limits bother me so far :thinking: 
tRCD_WR+tCWL+4+tWR seems to work wonderfully. Only tRAS+tRP often overshoots if low tRP isn't used


----------



## nick name

Veii said:


> -snip-
> 
> Hmm, can you boot up CL12 under 1.7v ?
> Want to try something a bit faster than this
> 
> -snip-


What do you want to try?


----------



## Veii

nick name said:


> What do you want to try?


Please try first how much voltage you'd need to even post CL12 
Maybe also increase PMU training time to HEX "C" = 12, decimal 

Do you also have SiSandra MCE installed for comparisons ?
Would like to try if increasing tRRD_S and tWTR_S values to perfectly match tWR , would cause a loss or an increase in Perf
But overall trying to hit tRAS 21/22 with lower tRC.
120ns tRFC is a solid record, but tRAS is still high'ish

It could also be educational, if we can increase tRP to cover voltage requirements for low CL
Just educational shenanigans 

EDIT:
Beyond 1.56v you might notice cell dropout by the high voltage
But it should only happen when Windows loads and so it will BSOD
Mem Training should still pass and load into the Bios with voltage beyond 1.56v
More than 1.7v indicates a "bad bin" at least not such a good one
* using Buildzoid's lucky Viper 4400's as example


----------



## nick name

Veii said:


> Please try first how much voltage you'd need to even post CL12
> Maybe also increase PMU training time to HEX "C" = 12, decimal
> 
> Do you also have SiSandra MCE installed for comparisons ?
> Would like to try if increasing tRRD_S and tWTR_S values to perfectly match tWR , would cause a loss or an increase in Perf
> But overall trying to hit tRAS 21/22 with lower tRC.
> 120ns tRFC is a solid record, but tRAS is still high'ish
> 
> It could also be educational, if we can increase tRP to cover voltage requirements for low CL
> Just educational shenanigans
> 
> EDIT:
> Beyond 1.56v you might notice cell dropout by the high voltage
> But it should only happen when Windows loads and so it will BSOD
> Mem Training should still pass and load into the Bios with voltage beyond 1.56v
> More than 1.7v indicates a "bad bin" at least not such a good one
> * using Buildzoid's lucky Viper 4400's as example


Give me a tRFC target to use with the tCL target. That is really gonna determine how much voltage I need. 

And I do have Sandra MCE, but the only difference I ever see when playing with RAM is when increasing tFAW and it increasing that bandwidth at the right end of the graph.


----------



## Veii

nick name said:


> Give me a tRFC target to use with the tCL target. That is really gonna determine how much voltage I need.
> 
> And I do have Sandra MCE, but the only difference I ever see when playing with RAM is when increasing tFAW and it increasing that bandwidth at the right end of the graph.


Higher tFAW increases the right side , are you sure ?
Then you will need to increase tRRD_S and tRRD_L , if this is the case
Something is autocorrected
Hmm, tCL can be the same tRFC that you use on your current set
tRFC will have to pass anywho what the current delay situation looks like. It's only an issue if tRFC is too small, then it will be postponed, wait till this tRFC elapses, put everything on hold and retrigger it.
It can do that 9 times before it crashes fully
tREFI on AMD does auto adapt and is pre calculated so far. There is no method to enforce different tREFI so far

What really interests us , is pushing the first part of the curve
This does go hand in hand with L3 cache perf and IPC
Between 4x 256bytes & 4x 8kb is what makes the biggest difference
If you hit perfect sync this happens ~ old screenshot
The differences where only tertiary timings, primaries staid with 14-14-14-28-42


Spoiler














And if it's not 100% positive across the whole range,somewhere you have timing issues
A good result has a bump everywhere, without any negative drop

EDIT:
inside the bios, we should also check the "Latency Improvement" option with the latency curve
If nothing shows up there, then it's an invalid unused option
As it either has to improve / worse cache perf or memory perf


----------



## nick name

Veii said:


> Higher tFAW increases the right side , are you sure ?
> Then you will need to increase tRRD_S and tRRD_L , if this is the case
> Something is autocorrected
> Hmm, tCL can be the same tRFC that you use on your current set
> tRFC will have to pass anywho what the current delay situation looks like. It's only an issue if tRFC is too small, then it will be postponed, wait till this tRFC elapses, put everything on hold and retrigger it.
> It can do that 9 times before it crashes fully
> tREFI on AMD does auto adapt and is pre calculated so far. There is no method to enforce different tREFI so far
> 
> What really interests us , is pushing the first part of the curve
> This does go hand in hand with L3 cache perf and IPC
> Between 4x 256bytes & 4x 8kb is what makes the biggest difference
> If you hit perfect sync this happens ~ old screenshot
> The differences where only tertiary timings, primaries staid with 14-14-14-28-42
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> And if it's not 100% positive across the whole range,somewhere you have timing issues
> A good result has a bump everywhere, without any negative drop
> 
> EDIT:
> inside the bios, we should also check the "Latency Improvement" option with the latency curve
> If nothing shows up there, then it's an invalid unused option
> As it either has to improve / worse cache perf or memory perf


It's never been consistent enough for me to report it back to anyone but it seems to only go up with a higher than 16 tFAW. It's the 8x1MB second to last point on the graph. 

And I can't POST at 3800 with tCL 12 and tRFC 228 at 1.7V. Did you want me to try more voltage?


----------



## Veii

nick name said:


> It's never been consistent enough for me to report it back to anyone but it seems to only go up with a higher than 16 tFAW. It's the 8x1MB second to last point on the graph.
> 
> And I can't POST at 3800 with tCL 12 and tRFC 228 at 1.7V. Did you want me to try more voltage?


1.7 was the absolute max
Wouldn't go higher than that
But you should also try in steps
1.55, 1.60 (will droop to 1.58) , 1.62, 1.65, 1.7 (should overshoot to 1.72ish)

In steps, as either your PCB or your cells will cause issues on a far too high voltage spike 
You can also try to slowly increase voltage near the 1.65 range on the CL14 set
and later bump to 1.7(2) and try CL12
Helps with memory training


----------



## nick name

Veii said:


> 1.7 was the absolute max
> Wouldn't go higher than that
> But you should also try in steps
> 1.55, 1.60 (will droop to 1.58) , 1.62, 1.65, 1.7 (should overshoot to 1.72ish)
> 
> In steps, as either your PCB or your cells will cause issues on a far too high voltage spike
> You can also try to slowly increase voltage near the 1.65 range on the CL14 set
> and later bump to 1.7(2) and try CL12
> Helps with memory training


I get F9 after it fails to POST which is not enough voltage. 

What makes 1.7v your limit? Are you wanting to run some RAM tests if I can get it to POST?


----------



## Veii

nick name said:


> I get F9 after it fails to POST which is not enough voltage.
> What makes 1.7v your limit? Are you wanting to run some RAM tests if I can get it to POST?


It's not good for the cells and is already far more than i'd normally recommend
Cells will crash and you'd have to use maxmem if you run beyond 1.72v 
Usually already beyond 1.62v, maxmem 4096 should be used 

You can try with the same set of timings to drop it to 3200MT/s and check again with sub 1.62v
Many parts can fail, and simply choke on voltage - the same goes for provided VTT_MEM
1.92 is the absolute "borderline safe" limit for B-dies with a fan ontop of them and a naked PCB,
2.1(2.25v) is the maximum XOC limit ~ a tiny bit higher and you blow something up if it's not > -60° celsius


----------



## SneakySloth

Veii said:


> Either get tRCD_RD down to 14 or push it up to 16 with tRP 12 & tRAS 26
> Anyways, at the end you have to get tRP 12 to work ~ only VDIMM will fail here
> tRFC 252 was fine, but tRTP needs to be lower, 8 or 6
> 
> If you want to replicate this set, you need to go down to tRCD_WR 14 in order for everything to match up
> Then you can run tRFC 240 or even 228 with tRTP 6
> Credits go to nick name for testing and confirming stability
> 
> Your key issue here is just tRAS 26 and tRP which needs to be 12
> Try for now that and push tRCD_RD 16
> Unless you out of random can run this tight tRCD_RD 14 set down bellow
> SCL is PCB exclusive, soo ignore it for now



Thanks for the input, I really appreciate it. I played around with the timings and got tRP = 14(same), tRAS = 26(from 28), tRTP = 8(from 10) and tRDWR = 10 (from 11) TM5 50 cycles stable.


I just cant seem to get tRP down to 12. I got an error in basically all the tests at 1.49v SET and an error in about half the tests at 1.5v SET. Currently I'm testing tRP = 13 and I'm on the 18th cycle so its looking good so far. Do you think tRP = 13 works or should I just keep it at 14? I'm not sure if keeping GDM enabled has any affect on ODD values of tRP.


----------



## jcpq

I wanted to lower latency, can anyone help?


----------



## Veii

SneakySloth said:


> I just cant seem to get tRP down to 12. I got an error in basically all the tests at 1.49v SET and an error in about half the tests at 1.5v SET. Currently I'm testing tRP = 13 and I'm on the 18th cycle so its looking good so far. Do you think tRP = 13 works or should I just keep it at 14? I'm not sure id keeping GDM enabled has any affect on ODD values of tRP.


Odd primaries are an issue.
We can't use odd tWR except through Ryzen Master
And all the rulesets hang at tWR. 
Also GDM does auto round up primaries. 
We are not sure if tRP is affected too, but the main primaries are

tRP 13 is too high. Needs 12 in order to function properly 
Else it breaks tRC=tRAS+tRP ruleset
On & After Write it will be fine because of tRCD_WR+tCWL+4+tWR
But on Read it won't, it will choke 
tRAS is fine too because of tRCD avg =12 + tWR 12 + tBL 2 

Theoretically 16GB dimms allow tRC down to -2
But this has to be teste and confirmed from your side
And before doing such, you have to have a comparison baseline 
Which you currently don't have
Run SiSandra MCE with tRP 14, grab one result for later, save this as another profile
And try to get tRP 12 to run
It will require more voltage 
More than 1.5

It won't only be a good idea, if your kits are on A0 PCB and you will have negative scaling beyond 1.48v - sometimes even 1.46v
A1 can perfectly take 1.52v without negative scaling and A2 can up to 1.56v before the cells become a potential issue


----------



## SneakySloth

Veii said:


> Odd primaries are an issue.
> We can't use odd tWR except through Ryzen Master
> And all the rulesets hang at tWR.
> Also GDM does auto round up primaries.
> We are not sure if tRP is affected too, but the main primaries are
> 
> tRP 13 is too high. Needs 12 in order to function properly
> Else it breaks tRC=tRAS+tRP ruleset
> On & After Write it will be fine because of tRCD_WR+tCWL+4+tWR
> But on Read it won't, it will choke
> tRAS is fine too because of tRCD avg =12 + tWR 12 + tBL 2
> 
> Theoretically 16GB dimms allow tRC down to -2
> But this has to be teste and confirmed from your side
> And before doing such, you have to have a comparison baseline
> Which you currently don't have
> Run SiSandra MCE with tRP 14, grab one result for later, save this as another profile
> And try to get tRP 12 to run
> It will require more voltage
> More than 1.5
> 
> It won't only be a good idea, if your kits are on A0 PCB and you will have negative scaling beyond 1.48v - sometimes even 1.46v
> A1 can perfectly take 1.52v without negative scaling and A2 can up to 1.56v before the cells become a potential issue



Thank you again for all this, its really helping a lot. I was running TM5 with trp 13 and thats at its 32nd cycle, so it seems stable but I think I'll try for 12. 



I have the Patriot Viper 4400, which I believe are a A2 PCB? So anything under 1.56 should be safe for 24x7 then right?


----------



## Veii

SneakySloth said:


> Thank you again for all this, its really helping a lot. I was running TM5 with trp 13 and thats at its 32nd cycle, so it seems stable but I think I'll try for 12.
> 
> I have the Patriot Viper 4400, which I believe are a A2 PCB? So anything under 1.56 should be safe for 24x7 then right?


Higher is safe too, when you control the thermals
B-Dies will just start to fail near 1.56v and suddenly drop out
The A2 PCB likes voltage 
If you go very high with vdimm, drop ClkDrvStrength again further down
Even down to 20 if needed
High VDIMM will help running GDM off, doesn't have to be just ClkDrvStr
But A2 kits like more voltage overall 
Up to board and if T-Topology , they could also need not only high ClkDrvStr but also higher VDDG IOD 
Which you offset by decreasing VDDG CCD by the same amount you increase IOD (for example -25mV CCD = +25mV IOD) 
Really really depends, but A2 kits love current ~ soo work around it 

Hmm have to find my explanation towards nick name on how impedance, powerdraw - wattage & current work out ~ it's a balance thing
Higher Impedance will increase Current (Ampere) and too much current causes issues
Higher Impedance = lower voltage to balance Current 
Lower impedance = increase current by higher voltage ,or you work to clean signal integrity soo lower voltage is needed overall
VTT_MEM even tho it's a voltage, takes the function of Impedance as "current increaser" or also "voltage multiplier"


----------



## nick name

Veii said:


> Higher is safe too, when you control the thermals
> B-Dies will just start to fail near 1.56v and suddenly drop out
> The A2 PCB likes voltage
> If you go very high with vdimm, drop ClkDrvStrength again further down
> Even down to 20 if needed
> High VDIMM will help running GDM off, doesn't have to be just ClkDrvStr
> But A2 kits like more voltage overall
> Up to board and if T-Topology , they could also need not only high ClkDrvStr but also higher VDDG IOD
> Which you offset by decreasing VDDG CCD by the same amount you increase IOD (for example -25mV CCD = +25mV IOD)
> Really really depends, but A2 kits love current ~ soo work around it
> 
> Hmm have to find my explanation towards nick name on how impedance, powerdraw - wattage & current work out ~ it's a balance thing
> Higher Impedance will increase Current (Ampere) and too much current causes issues
> Higher Impedance = lower voltage to balance Current
> Lower impedance = increase current by higher voltage ,or you work to clean signal integrity soo lower voltage is needed overall
> VTT_MEM even tho it's a voltage, takes the function of Impedance as "current increaser" or also "voltage multiplier"



I have a VERY basic grasp on that though I didn't know about VTT MEM.


----------



## SneakySloth

Veii said:


> Higher is safe too, when you control the thermals
> B-Dies will just start to fail near 1.56v and suddenly drop out
> The A2 PCB likes voltage
> If you go very high with vdimm, drop ClkDrvStrength again further down
> Even down to 20 if needed
> High VDIMM will help running GDM off, doesn't have to be just ClkDrvStr
> But A2 kits like more voltage overall
> Up to board and if T-Topology , they could also need not only high ClkDrvStr but also higher VDDG IOD
> Which you offset by decreasing VDDG CCD by the same amount you increase IOD (for example -25mV CCD = +25mV IOD)
> Really really depends, but A2 kits love current ~ soo work around it
> 
> Hmm have to find my explanation towards nick name on how impedance, powerdraw - wattage & current work out ~ it's a balance thing
> Higher Impedance will increase Current (Ampere) and too much current causes issues
> Higher Impedance = lower voltage to balance Current
> Lower impedance = increase current by higher voltage ,or you work to clean signal integrity soo lower voltage is needed overall
> VTT_MEM even tho it's a voltage, takes the function of Impedance as "current increaser" or also "voltage multiplier"



tRP 12 might be out of reach for me. I cant seem to get it stable. Crashes instantly in Tm5 with VDIMM all the way up to 1.54. There is no change in stability from all the way to 1.49 -> 1.54. I also tried changing the VDDG_IOD/CCD voltages and the ClkDrvStr with different combinations of each.


If I stay at tRP 14, should I bump up tRC to 38 and tRFC to 266? This is with tCL 14 and tRCD_RD 16 and tRCD_WR 8? Would that math make sense?


----------



## crakej

SneakySloth said:


> tRP 12 might be out of reach for me. I cant seem to get it stable. Crashes instantly in Tm5 with VDIMM all the way up to 1.54. There is no change in stability from all the way to 1.49 -> 1.54. I also tried changing the VDDG_IOD/CCD voltages and the ClkDrvStr with different combinations of each.
> 
> 
> If I stay at tRP 14, should I bump up tRC to 38 and tRFC to 266? This is with tCL 14 and tRCD_RD 16 and tRCD_WR 8? Would that math make sense?


I'm going to try some of your timings/settings tomorrow on my CH7 as I have same memory...

Can I ask if anyone knows what happens with ProcODT as we increase speed? Does it rise or fall too? This is my 3733MTs current setup. Ram is at 1.475v


----------



## Veii

SneakySloth said:


> tRP 12 might be out of reach for me. I cant seem to get it stable. Crashes instantly in Tm5 with VDIMM all the way up to 1.54. There is no change in stability from all the way to 1.49 -> 1.54. I also tried changing the VDDG_IOD/CCD voltages and the ClkDrvStr with different combinations of each.
> 
> 
> If I stay at tRP 14, should I bump up tRC to 38 and tRFC to 266? This is with tCL 14 and tRCD_RD 16 and tRCD_WR 8? Would that math make sense?


Wouldn't make sense, if i follow now this type of rules (aka all of them) 








Won't get lower than that
tRP , and so also tRCD avg delay is just too high
I could ignore and break some rulesets, but i think this is now a cleaner method ~ as it applies to all of them

Try out if your kit can run tRDWR that low
else you might need to go up to 9 and then it depends if you need tWRRD or not. But you shouldn't need it
tCWL to lower was an option if i use tWR 10 ~ would even be a good boost
But it doesn't work with that tRCD, 16 is high and my mini calc suggests 252 not lower.
231-172-106 could work on this set, IF we can change tWR to 11 and tRTP to 7 (GDM off)
But tWR doesn't allow to be odd :handlebar soo nope, won't work 
Need to get tRP 12 to work or get tRCD 14 to work for better sets :^

tRTP 8 would work on too, but 6 is better 
Sometimes 6 doesn't work, just so you know ~ you have options there

EDIT:
We can test at the very end, if breaking the rulesets and using still tRC -2 , does work on Single Rank units 
(so we end up with tRC 40 and 240 tRFC)
But that needs excessive comparison for another time


----------



## SneakySloth

Veii said:


> Wouldn't make sense, if i follow now this type of rules (aka all of them)
> 
> 
> 
> 
> 
> 
> 
> 
> Won't get lower than that
> tRP , and so also tRCD avg delay is just too high
> I could ignore and break some rulesets, but i think this is now a cleaner method ~ as it applies to all of them
> 
> Try out if your kit can run tRDWR that low
> else you might need to go up to 9 and then it depends if you need tWRRD or not. But you shouldn't need it
> tCWL to lower was an option if i use tWR 10 ~ would even be a good boost
> But it doesn't work with that tRCD, 16 is high and my mini calc suggests 252 not lower.
> 231-172-106 could work on this set, IF we can change tWR to 11 and tRTP to 7 (GDM off)
> But tWR doesn't allow to be odd :handlebar soo nope, won't work
> Need to get tRP 12 to work or get tRCD 14 to work for better sets :^
> 
> tRTP 8 would work on too, but 6 is better
> Sometimes 6 doesn't work, just so you know ~ you have options there
> 
> EDIT:
> We can test at the very end, if breaking the rulesets and using still tRC -2 , does work on Single Rank units
> (so we end up with tRC 40 and 240 tRFC)
> But that needs excessive comparison for another time



Cheers, once again appreciate all your help right now. Cant thank you enough.




TRDWR below 10 doesn't post for me. I've tried both 8 and 9 and I've had to reset CMOS multiple times for them. So 10 seems to be the lowest I can go there. This was on previous sets of timings and not the combination you've just mentioned.


I've changed tRTP to 6 and running Tm5 again. Also changed tRCDWR to 12, tRAS to 28, tCWL to 14 and tRC to 42. I'll report back after TM5 either crashes or finishes.


Before this set you posted I was trying the combination below, seemed to be stable but I'm sure I got the math wrong (tRFC was 38*7 - 16 = 250).


----------



## t4t3r

Jeffrey Kistler said:


> Managed to get under 100s for the first time after pushing 1.5 vdimm and adjusting timings, haven't tested stability


Is this a newer kit of ripjaws? I have one from a couple weeks ago with June 2020 manu date on A2 pcb and it is awesome, better than I expected from a 3200c14 kit. Very similar timings.


----------



## SneakySloth

crakej said:


> I'm going to try some of your timings/settings tomorrow on my CH7 as I have same memory...
> 
> Can I ask if anyone knows what happens with ProcODT as we increase speed? Does it rise or fall too? This is my 3733MTs current setup. Ram is at 1.475v


Thank you for doing that. Hopefully you're able to get trp down to 12


----------



## crakej

SneakySloth said:


> Thank you for doing that. Hopefully you're able to get trp down to 12


What voltage are you having to give them for 3800MTs?


----------



## mongoled

@SneakySloth

I had mentioned that in an earlier post, 

You are going to have an extremely hard time to get [email protected] working stable.

At least you have spent xxx extra amount of time learning about your modules 



You should be able to run these stable, I am on X370, you have superior motherboard regards to memory clocking

Note: the below screen shot is 3800/1900, I am using BCLK of 107.5625 ....


----------



## mongoled

Veii said:


> So far
> No one got that set stable without GDM


Hahahahah, thought I was slacking


----------



## KedarWolf

Veii said:


> Some people mention, it should be mounted vertically
> The kingpin 3090 looks funny
> 
> Also, hey 228 / 120ns was unheard before ~ it didn't post for people, even with CL12
> I'll gladly take the crown on that till someone shows it lower and stable :graduated
> 
> Hmm, can you boot up CL12 under 1.7v ?
> Want to try something a bit faster than this
> 
> Need people with dual rank
> Looking at @KedarWolf - to confirm stability on the same pattern creation just for DR
> 
> And later people with Micron Rev.E kits
> Library of timings does grow
> Unsure if i have the knowledge of making a calculation sheet for such
> ~ but i think i have figured out the method to make presets following all the known rulesets out there
> Only tRRD_S and tWR limits bother me so far :thinking:
> tRCD_WR+tCWL+4+tWR seems to work wonderfully. Only tRAS+tRP often overshoots if low tRP isn't used


What is it exactly you want me to do? But I'm NOT going to try my RAM at 1.7v though.


----------



## SirPerfluous

Still working these sticks at the same voltage. 15 cycles stable so far. 

Does GDM actually change tCWL? 

Also,
With PBO on and off, this chip will suck down 1.36v in R20 and 1.325 in P95 small FFT.(VROUT&SVI2) Do I have good\bad silicon or has anyone here experienced this? 

I ask because its tempting me to push higher voltage on my all core oc. (62.5 is the lowest latency I can get at 4.3)
If its giving it that from the factory, It makes me think I should be a little less scared of pushing for 4.4+ all core at 1.35 get

I _know_ ryzen voltage scaling is garbage and There's likely little benefit for +100mhz if its costing me exponential levels of power/heat
I'm curious if this is something anyone else has seen. I initially wrote it off as an issue with my X370 Bios and 1.0.0.4B but it persists on this board with 1.0.0.6

PBO seems garbage for me too, 64ns is the lowest in Aida. For some reason it drops freq. on all cores during the latency test. I'm sure there's something I dont have set right.
I do see 4.45 single core on ~60% of the cores and 4.4/+.25 on the rest, but my all core frequency is trash. even with EDC bug and many other configs with plenty of fiddling, The best I could achieve was 4.25 all core, but it was always using 1.36v. It even hit 1.38 on a couple occasions with certain scalar settings.


----------



## jcpq

@1.44v
Anything to change to improve?


----------



## Veii

crakej said:


> Can I ask if anyone knows what happens with ProcODT as we increase speed? Does it rise or fall too? This is my 3733MTs current setup. Ram is at 1.475v


Yes procODT increases as fabric speed increases
Has to be increased
But high procODT decreases maximum FCLK 


KedarWolf said:


> What is it exactly you want me to do? But I'm NOT going to try my RAM at 1.7v though.


Nono 
i wouldn't on dual rank ^^'
Overall a dual rank set with the same rulesets
We'd have to figure out if every DR set needs high tWR or just many
What was the reason you can't go lower with tRAS again ?

Just need a bit more testing rabbits for couple of more sets on different dies
B-dies alone got figured out and booring so far


SirPerfluous said:


> Still working these sticks at the same voltage. 15 cycles stable so far.
> 
> Does GDM actually change tCWL?


Yes, it does round it up. But doesn't seem to change to tCL = tCWL
That last part is unclear still


----------



## SirPerfluous

I was wrong again. Here's a better latency at the same voltages and higher frequency.
I only had to increase soc llc and ODT for this to be stable.

Edit: Also I increased priority and stopped a bunch of unnecessary services for a sub 62


----------



## Veii

@SirPerfluous Try this
245-182-112 with the remain set
only concern is too low tRCD_WR and GDM
tWR 10 works still with 245


----------



## mongoled

Has there been any general consensus as to what is the cause for TM5 to stop working?

Is it vDIMM, vSOC, ODT, CadBus, related etc etc?

I'm troubleshooting a different set of vipers and sometimes they hiccup real late, like cycle 23/24. No errors, mouse will temporarily freeze, audio will stop, like a mini hang and then I will notice TM5 has stopped.

Nothing in error logs etc.

Searched, but have not found information as to what may be the cause.....

** EDIT **
For anyone else coming across this, increasing vSOC +25mv resolved this issue


----------



## Veii

mongoled said:


> Has there been any general consensus as to what is the cause for TM5 to stop working?
> 
> Is it vDIMM, vSOC, ODT, CadBus, related etc etc?
> 
> I'm troubleshooting a different set of vipers and sometimes they hiccup real late, like cycle 23/24. No errors, mouse will temporarily freeze, audio will stop, like a mini hang and then I will notice TM5 has stopped.
> 
> Nothing in error logs etc.
> Searched, but have not found information as to what may be the cause.....


Usually core crashes cause that
as a worker stops _working_
Pretty much related to voltages
SOC and procODT go together
VDIMM and CAD_BUS do too ~ but these have nothing to do with core crashes

Can be LLC, can be cLDO_ related


----------



## mongoled

Veii said:


> Usually core crashes cause that
> as a worker stops _working_
> Pretty much related to voltages
> SOC and procODT go together
> VDIMM and CAD_BUS do too ~ but these have nothing to do with core crashes
> 
> Can be LLC, can be cLDO_ related


OK, many variables 



Did you publish that set you were talking about, the tRCDRD @16 set ??

As these other newer sticks are not going to do tRCDRD @15 reliably,

im honing in on 14-10-16-14-28-40-6-252 [email protected], [email protected]


----------



## Jeffrey Kistler

t4t3r said:


> Is this a newer kit of ripjaws? I have one from a couple weeks ago with June 2020 manu date on A2 pcb and it is awesome, better than I expected from a 3200c14 kit. Very similar timings.


Not sure about my manufacture date, but mine are A1, bought them from newegg in July. I like them too


----------



## Veii

mongoled said:


> OK, many variables
> 
> 
> 
> Did you publish that set you were talking about, the tRCDRD @16 set ??
> 
> As these other newer sticks are not going to do tRCDRD @15 reliably,
> 
> im honing in on 14-10-16-14-28-40-6-252 [email protected], [email protected]


It's just some cores crashing , you can figure this out 
Y-cruncher has to show this
OCCT should do too
TM5 uses SSE , soo maybe Linpack Xtreme 1.1.1 should show this too or disabled AVX under OCCT MediumDataset

I forgot if you run per CCX or still the EDC bug,
But TM5 under PBO OC, does utilize the highest possible "maximum boost"
If autoOC is set to +200, it will try to run these
Soo on a 3600 it will try to run 4.4 if you set it to that

Thought you saw the old timings, these should work



Veii said:


> Or as a new set:
> 
> 
> Spoiler
> 
> 
> 
> tCL 16
> tRCD_WR 12
> tRCD_RD 16
> tRP 14
> tRAS 30
> tRC 44
> tRFC 308-229-141
> tRTP 8 or without GDM 7
> tWR 14
> tCWL 14
> SCL 3
> tRDWR 10
> tWRRD 4
> 
> 
> Same set but lower:
> 
> 
> Spoiler
> 
> 
> 
> tCL 16
> tRCD_WR 8
> tRCD_RD 16
> tRP 12
> tRAS 28
> tRC 40
> tRFC 280-208-128
> tRTP 8 or GDM off 7
> tWR 14
> tCWL 14
> SCL 3
> tRDWR 10
> tWRRD 2
> 
> You'll need to up VDIMM as tRP 12 is harsh (1.46-1.54v)
> tRP 14 should need around 1.44-1.48v
> tRCD 15 is pretty impossible to get running
> tRCD 14 , tCL 14 is only for high binned ICs and needs at minimum 1.54v
> Tho if you're brave:
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> On all 3 sets, trow voltage at them till they boot up
> They will be stable


Thought you saw them, but my bad for not positing it here after mentioning
i think i figured today how tRCD 15 can work on the same method
It ends up as .5 divider but it's still fine and not a random long decimal result
tWR 10 can work, even with ODD tRFC like 247

We'll see what i can get up with
But you can try too
Try to follow ALL the rules that are written


> tRAS
> tRCD[avg] + tCL
> tRCD[avg] + tWR + tBL
> tRC:
> tRAS+tRP
> tRCD_WR+tCWL+4+tWR
> 
> tWR:
> Clean divider of tRFC[ns] or .5 at worst
> Alt. = tRAS - tRCD
> ^ pick one, but it has to be an even number and not break tRClong ruleset


All these together rules out many timings options
Try to make one for yourself if above examples don't work


----------



## dspx

Anyone managed to go stable beyond 3466 on Zen+?


----------



## mongoled

Veii said:


> It's just some cores crashing , you can figure this out
> Y-cruncher has to show this
> OCCT should do too
> TM5 uses SSE , soo maybe Linpack Xtreme 1.1.1 should show this too or disabled AVX under OCCT MediumDataset
> 
> I forgot if you run per CCX or still the EDC bug,
> But TM5 under PBO OC, does utilize the highest possible "maximum boost"
> If autoOC is set to +200, it will try to run these
> Soo on a 3600 it will try to run 4.4 if you set it to that
> 
> Thought you saw the old timings, these should work
> 
> 
> Thought you saw them, but my bad for not positing it here after mentioning
> i think i figured today how tRCD 15 can work on the same method
> It ends up as .5 divider but it's still fine and not a random long decimal result
> tWR 10 can work, even with ODD tRFC like 247
> 
> We'll see what i can get up with
> But you can try too
> Try to follow ALL the rules that are written
> 
> All these together rules out many timings options
> Try to make one for yourself if above examples don't work


Thanks, didnt know you posted them in the other thread.

Yes, very familiar with your prior research and testing methodologies



Just wanted to compare your timings to what im currently dialing in


----------



## Nighthog

dspx said:


> Anyone managed to go stable beyond 3466 on Zen+?


Should be doable if the motherboard will accept and the memory is right.
I got 3733Mhz stable on B350 + Ryzen 1700.
Mostly it's the memory & motherboard that have to co-operate. Many motherboards in early gen1 & gen2 weren't good enough but with X570 & B550 most should clock well if your memory kits aren't bad and generally incompatible. 
I have a real early "bad-bin" Micon rev.E. they clock above 4000Mhz easy on X570. But one X470 motherboard didn't want to do above 3200Mhz compared to the B350 I had first that was stable 3733Mhz but could boot higher if I cranked the SoC voltage real high. 

As you have Tomahawk B550 & Micron rev.E I see no hindrance for you to be able to do it. Though I think you might need more SoC voltage than the usual recommended if you have a bad sample IMC on your CPU. 
And there is the general need for high timings for Rev.E to boot. If you try to low for a too high sped it will just refuse outright. Relax them main timings if they are too tight to see where frequency will take you and then try to see at what speed you want to settle for lowest timings. (only the best bin do tight timings)


----------



## dspx

Thank you @Nighthog for a comprehensive answer. I use this PC for work so stability is of utmost importance. That is why I did not want to test 3533 and higher when I saw TM5 showing errors, as I don't have enough time to test at the moment. I have a Ballistix 3600 CL16 2x8 GB kit, here are my settings, nothing fancy but rock stable. Did not want to update the BIOS to the latest AGESA ComboAm4v2PI 1.0.8.1 as I am not certain if that will **** anything up.


----------



## jcpq

Hi.
For values 15 (tCL) -15 (tRCD RD) -13 (tRP), do I have the correct tRAS and tRC?
In relation to tRP, do you recommend a different value?


----------



## Keith Myers

dspx said:


> Anyone managed to go stable beyond 3466 on Zen+?


I never did. Only able to go further with the same memory on Zen 2.


----------



## Leito360

Hello. I'm on a Aorus Elite X570. I was able to get 3733 stable on Micron E-Die (400+ plus on MEMTEST and 8 hours of Google StressApp).
My Vcore SOC voltage is 1.1V. Do I need to have activated "Vcore SOC LLC" on High or could I just put it on Auto? Is there any harm to have it always on High?

Screenshots below:


----------



## SirPerfluous

dspx said:


> Anyone managed to go stable beyond 3466 on Zen+?


I have a couple A2 D9WFL Rev. E sticks that have been ~stable at 3600c14 on a 1200AF
I'd offer more, but I have that machine torn apart right now :/

Edit: this required close to 1.5


----------



## dspx

Keith Myers said:


> I never did. Only able to go further with the same memory on Zen 2.





SirPerfluous said:


> I have a couple A2 D9WFL Rev. E sticks that have been ~stable at 3600c14 on a 1200AF
> I'd offer more, but I have that machine torn apart right now :/


Thank you. I will have a go at it as soon as I find some free time.


----------



## Mumee

Any idea where to improve?
tWR12-14 and tRP12-13 i couldn't make work, tried many different CADs, procODT and impedances.
tWR12-14 works with weaker timings like CL16.
My IMC cannot do 1900mhz.


----------



## Veii

Mumee said:


> Any idea where to improve?
> tWR12-14 and tRP12-13 i couldn't make work, tried many different CADs, procODT and impedances.
> tWR12-14 works with weaker timings like CL16.
> My IMC cannot do 1900mhz.


Two short questions
Have you tried tRCD_RD 18 ? @ what voltagedoes this set run
what's up with that low tWTR_ and tRRD_ ~ did you pick the lowest possible or tested them through ?
We speak about dual rank, higher capacity needs more delay here
The same goes for tWR, that's why you can't lower it

Or do you run 4x Rev E ?


----------



## Mumee

2x Rev E.
tRCDRD18 not stable anyhow i tried. 1,505V
I only have a picture about this test with these timings, but it is stable as:
HCIM 25k%
TM5 1usmus v3 x30
TM5 extreme anta777 x15

tWR 12-14 not stable even if i set tRC58+tRFC580+tWTRS4+tWTRL8+tRDRDSCL4+tWRWRSCL4
tWR14 gives error mostly in HCIM after like 4000% (tried many different CAD,procODT and impedances)
Same goes for tWR12, but that gives error before 1000%


----------



## Veii

Veii said:


> what's up with that low tWTR_ and tRRD_ ~ did you pick the lowest possible or tested them through ?
> We speak about dual rank, higher capacity needs more delay here
> The same goes for tWR, that's why you can't lower it
> 
> 
> Mumee said:
> 
> 
> 
> 2x Rev E.
> tRCDRD18 not stable anyhow i tried. 1,505V
> 
> tWR 12-14 not stable even if i set tRC58+tRFC580+tWTRS4+tWTRL8+tRDRDSCL4+tWRWRSCL4
Click to expand...

Question above about tWTR_
And have you tried lower tRC ?
Between 46, 48 , 50 ?

tRFC2 & 4 is wrong on your side
tRC and tRFC go together, as tRC is the "end" of a cycle and has to pass
tRFC defines when memory would need to refresh
if tRFC is too low, it will be postponed
if tRC cycle ends up too early inside tRFC cycle, it will start another one - try to fill remain tRFC error out and postpone it
in short ~ match tRC and tRFC together, else at best tRFC is postponed up to 9 times, and at worst it won't even pass memory checking on post

You used tRC 55 = tRFC 550-409-251
only tRC 50 would still fit in there
Digged a bit for information and JEDEC for 16GB is 350-260-160ns for tRFC
Resulting in around a 12* tRC

Also according to specs-sheet
tRRD_S 4 = 4nCK = 4 *
tRRD_L 6 = 4nCK = 6 *
tWTR_S 2 = 2nCK
tWTR_L 5 = 4nCK








^ this should be accurate if i didn't mess up 
this should be accurate then, soo forget my first question
tWTR_ really can be thaat low on Rev.E 

tWR according to specs is 15ns of MT/s = 28 value
Down to 14 should work if everything else is correct

Have to go now, but will edit the post
tWR 14 can and will work ~ will push a set in couple of hours or try through the phone 
Factor in tWR 14 for both rulesets
tRC = tRCD_WR+tCWL+4+tWR
tRAS = tRCD[avg] + tWR + 2
You'll likely need to push tRCD_WR up to have a good tRCD avg value 
tRFC would be 14* tRC here, down to 12* if we get tWR 12 to run (should, idk why it errors)


----------



## Mumee

@Veii 
I have only tried tRC 52-53-54. 52 no boot, 53-54 errors.
tRFC2-4 is on auto, in Ryzen Master it shows values of 486 and 299. Zentimings show it wrong for some reason (or RM does).
I can try it manually with your calculated timings, but i guess it should not change much in stability with tWR.

Previously when tested, increasing tRC and/or tRFC seemed to work with tWR14, but seemed slower than current setup.

I tried tRCD_WR 10-12-14 as well. Maybe i will try tRCD_WR 19 to match tRCD_RD then, but most of the time i only get error in HCIM only not TM5. If TM5 gives error it's mostly error 0, so it should be related to refresh.
tRC 56 and 58 with tRFC 560 and 580 did also not work.

Both tWR12 and 14 feels close to work, but somehow i could not manage to get it work.
I tried so many options i can't count and in the end they all failed with tWR lower than 16 even with some weird timings here and there.
As you can see below.


----------



## oRuin

Ryzen 3700x
Gigabyte Aorus Elite x570 (F21)
2x 8gb Patriot Viper Steel DDR4 4400mhz (16gb)

For the longest time I have been trying to get my memory to a command rate of 1T or GDM on.
This was one of the most frustrating issues I had with the machine when I first built it.
I could have all timings hugely relaxed, running at 3400mhz and still, anything other than 2T would make the system extremely unstable.
What am I doing wrong? Why can't I get even 1T with relaxed timings?

Below are my most optimal speed/timings so far. My Ryzens FLCK is weak at best, so 3666 on the memory is probably as good as it gets.


----------



## mongoled

Not familiar with your motherboard,

however, cannot see the reason why you cannot run 1T or GDM enabled as your memory is capable and so should your CPU and motherboard.

I am guessing you have tried different BIOS versions ?

Your vSOC is very high along with your ProcODT (yes they go in tandem).

Have you tried lower combination of vSOC and ProcODT ?

It could just be your CPU, have you tried a different CPU ?


----------



## oRuin

I have now lowered my SOC and VDDG, which so far seems stable.
ProcODT is now 40









I have tried my original bios - F4. Then F10, F20 and now F21.
With some of the earlier bios releases, I could get into Windows, but it would be unstable.
With the current F21, even the BIOS itself is unstable with 1T. Bios will actually crash.
I know it's not a big deal, but I am very surprised, even at the weakest of speeds/timings - that 1T causes so many problems.
Considering waiting on the 4000 releases to replace this 3700x. If that doesn't work, I'm going with a different motherboard.


----------



## coquiim

Hey guys, any tips to help me improve the oc?

DRAM V: 1.35v
VSoC: 1.025v
CLDO_VDPP: 0.900

CPU is stock with PBO off


----------



## Mumee

@Veii 
Couldn't make tWR14 or 12 work with many different tRC and tRFC pairs, but i could make tRP13 work.


----------



## Leito360

Hello. New 'here. Board: X570 Aorus Elite Wifi (F30a). Memory: Ballistix Sport LT (E-Die) 2x16GB 3200 stock (Now running @3733 1.38v)
So..... on my first run I was able to do 3733 16-20-16-38-60 at 1.35V. I ran memtest up to 400% and reported no errors, but GSAT was spitting errors like no tomorrow (miscompare on CPU). I raised the voltage to 1.38 and ran it again for 8 hours without issues at all.

Does anyone know what this miscompare error is? Also, is it too bad to be golden on Memtest but have errors on GSAT?
BTW, is ProcODT at 53.3 too high? Some people ar running it at 40 something or 34, but i really don't know.

I attach screenshots of zen timings, memtest and a photo of GSAT (I can't record a log since I run it from a flashdrive).


----------



## Keith Myers

Leito360 said:


> Hello. New 'here. Board: X570 Aorus Elite Wifi (F30a). Memory: Ballistix Sport LT (E-Die) 2x16GB 3200 stock (Now running @3733 1.38v)
> So..... on my first run I was able to do 3733 16-20-16-38-60 at 1.35V. I ran memtest up to 400% and reported no errors, but GSAT was spitting errors like no tomorrow (miscompare on CPU). I raised the voltage to 1.38 and ran it again for 8 hours without issues at all.
> 
> Does anyone know what this miscompare error is? Also, is it too bad to be golden on Memtest but have errors on GSAT?
> BTW, is ProcODT at 53.3 too high? Some people ar running it at 40 something or 34, but i really don't know.
> 
> I attach screenshots of zen timings, memtest and a photo of GSAT (I can't record a log since I run it from a flashdrive).
> 
> View attachment 2458749
> View attachment 2458750
> View attachment 2458754


Read the author's explanation. Miscompare reason


----------



## KedarWolf

More voltage often is NOT better. If I have my RAM at 1.47v, VOC at .900v and VDDGs at .975v and 1.025v GSAT fails immediately.

If I reduce the VDDGs to .950v and 1.000v GSAT passes just fine. It also happens when I raise my RAM voltage on my Dual Rank b-dies.


----------



## Leito360

KedarWolf said:


> More voltage often is NOT better. If I have my RAM at 1.47v, VOC at .900v and VDDGs at .975v and 1.025v GSAT fails immediately.
> 
> If I reduce the VDDGs to .950v and 1.000v GSAT passes just fine. It also happens when I raise my RAM voltage on my Dual Rank b-dies.


Of course, the less the voltage the better, unfortunately, it was the only way to pass the GSAT. I will try with less voltage and some other values later and see how it goes.
What is a good value for ProcODT?


----------



## Mumee

@Veii 
tWR <16 nicht stabil bekommen, bevor ich CsOdtDrvStr von 24 auf 20 gesenkt habe.
Tatsächlich war zuvor mit höherem procODT mit CsOdtDrvStr 20 auch instabil. ( nur in HCIM )
Es muss also eine Beziehung zwischen tWR und CsOdtDrvStr geben


----------



## mongoled

Please, this is an English speaking forum


----------



## .Morello

Veii said:


> It shouldn't do much to the boosting result, but you can work with per CCX or later a fine adjusted PBO
> PBO without voltage limits only does harm and nothing good
> Your voltages are low, it has no scaling inside
> VDDP -> VDDG is 100mV.
> VDDG -> SOC is 150mV
> unsure if this will preserve stability, but if you go with 75mV, it should work
> Example:
> cLDO_VDDP 825mV
> VDDG IOD (is your board daisy chain?) 875
> VDDG CCD 925
> VSOC 1050
> 
> VDDG without splitting it would be 900mV
> With a split you can push CCD higher where avg VDDG is 900mV between both
> Yes i ment to disable PBO unless you know your exact workload voltages, know which CCX are good and know how to PBO (TDC,EDC) limit them
> Continue from the quote of this discussion, to the next page
> Should forward you to the CH7 page and that to the X370 Taichi one
> 
> But PBO will mess up the memory OC, like every core OC normaly would
> For fixed allcore, focus on staying under 1.2875v vCore ~ till you know your actual safe upper limits
> 4.1ghz AC should work under 1.1, 4ghz under 1v and 4.2 near 1.2175v/1.2v
> 
> Without PBO, it's suggested to use 1usmus powerprofile or the latest ryzen balanced with enabled CPPC and CPPC preferred cores functionality from the bios


Hey, it's me again! Thanks for helping me back then.
Do you happen to have a working link to that discussion? Seems like it's broken. Wanna try your suggestions on a per-CCX overclock (just discovered my motherboard added it with a BIOS update).


----------



## jcpq

Hi
For my configuration / timings I think the latency (64.0ns) is a very high value.
What do you think?


----------



## rares495

jcpq said:


> Hi
> For my configuration / timings I think the latency (64.0ns) is a very high value.
> What do you think?
> View attachment 2458803


Looks normal to me. You'll have to OC your CPU and go way tighter on the memory to get 63ns and under.


----------



## jcpq

rares495 said:


> Looks normal to me. You'll have to OC your CPU and go way tighter on the memory to get 63ns and under.


I've seen systems here with the same CPU and the same timings where there are less than 62ns.
I do not understand.


----------



## mongoled

jcpq said:


> I've seen systems here with the same CPU and the same timings where there are less than 62ns.
> I do not understand.


Your AIDA screenshot shows the frequency of your CPU when you ran the benchmark.

The 64ns is because your CPU is only running at 4250mhz.

If you ran an all core overclock of 4.3Ghz and run the benchmark you score would be less than 63ns and if you ran a core core overclock of 4.4Ghz it would be less than 62ns ...


----------



## mongoled

So finally tuned my second set of Vipers 4400mhz, not as bad as i intially thought but not comparative to the set in my sig










Perhaps on a better board they could do SCL lower than 4 and tRCDRD @15 ......


----------



## rares495

mongoled said:


> Your AIDA screenshot shows the frequency of your CPU when you ran the benchmark.
> 
> The 64ns is because your CPU is only running at 4250mhz.
> 
> If you ran an all core overclock of 4.3Ghz and run the benchmark you score would be less than 63ns and if you ran a core core overclock of 4.4Ghz it would be less than 62ns ...


It's not that easy to get under 62.


----------



## mongoled

rares495 said:


> It's not that easy to get under 62.


Yeah maybe over stated as his tCL/tRCDRD is @15

But its also not that hard



** EDIT **
With the right hardware and knowledge


----------



## Yviena

How important is TRDWR for performance, is the difference between 9, and 10 negligible?

I managed to do 20 rounds TM5 v3 preset with 32gb with TRDWR at both 10, and 9 but the next reboot TRDWR at 9 failed after 10 runs, should I just keep it at 10, and 3800CL15-15-15-15-30-46 1T 276TRFC?


----------



## SirPerfluous

@Veii This Mobo won't let me set 7 as CDWR timing 
8 is the lowest manual value -auto doesn't post.
Maybe sometime in the future I'll swap the Asus board in here and see what it can do with these sticks.

I've just gotten the R3 back together, and soon I'm gonna start working the Rev. E properly.



jcpq said:


> I've seen systems here with the same CPU and the same timings where there are less than 62ns.
> I do not understand.


This is what it's taken for me to get sub 62 at 4.32 all core.
I'm sure this is a redundant post as these timings are already posted by me not long ago, but this is to hopefully highlight the not-insignificant difference in timings.

You definitely need more core clock though.
Also, optimize your os as best you can for running the bench


----------



## dspx

Here is an update for people having Zen+ CPUs, 3600 CL16 with safe settings was fine.
I managed to pass a couple of hours of TM5 (anta777) with no errors, I will try to test more as soon as I have more time.


----------



## HowYesNo

hi guys.
i am mostly at stock now (PBO auto, XMP loaded, and some settings for 1usumus power plan), just doing some testing, before trying some dram calc.
i tried TM5 with [email protected], after 10mins temps were 48/47 on ram (B-die G.Skill F4-3600C18-8GTZRX) are those safe temps for ram on stock settings 1.350V??
Also my VSOC temps seem a bit higher than what jcpq posted above. is that ok?
thanks for help.


----------



## jcpq

jcpq said:


> Hi
> For my configuration / timings I think the latency (64.0ns) is a very high value.
> What do you think?
> View attachment 2458803


I adjusted the ppt, tdc and edc values and reached 63.5ns


----------



## SirPerfluous

jcpq said:


> I adjusted the ppt, tdc and edc values and reached 63.5ns


I have never gotten below that with PBO on. even with the same timings as my previous post


----------



## jcpq

SirPerfluous said:


> @Veii This Mobo won't let me set 7 as CDWR timing
> 8 is the lowest manual value -auto doesn't post.
> Maybe sometime in the future I'll swap the Asus board in here and see what it can do with these sticks.
> 
> I've just gotten the R3 back together, and soon I'm gonna start working the Rev. E properly.
> 
> 
> This is what it's taken for me to get sub 62 at 4.32 all core.
> I'm sure this is a redundant post as these timings are already posted by me not long ago, but this is to hopefully highlight the not-insignificant difference in timings.
> 
> You definitely need more core clock though.
> Also, optimize your os as best you can for running the bench


Thanks


----------



## jcpq

SirPerfluous said:


> I have never gotten below that with PBO on. even with the same timings as my previous post


what settings do you use on the CPU to get this clock?
[email protected]?


----------



## KrampusKlaus

Hey guys, thinking of buying Zen 3 next month. Mobo budget is about $200. Looking to get a B550 or X570 board with strong BIOS support for memory overclocking 2x8. My main concern is avoiding mobos with poor memory training, and which ignore manual settings in the BIOS and just post whatever they feel like. Also, of course, avoiding boards with low PCB layers or T-Topology (as opposed to daisy chain). I'm not terribly worried about CPU overclocking, unless some boards just have horrible bugs with PBO that want to murder your chips with electricity.

Do y'all have any recommendations?


----------



## SirPerfluous

jcpq said:


> what settings do you use on the CPU to get this clock?
> [email protected]?


I've read that PBO can scale with base clock. When I used 100.5 with EDC @5 and AutoOC +125 I saw some decent single core frequency maximums.
my two good cores would hit 4497 all the time.

To get the lower numbers in that grey box I need an all core oc of 100.5x43 @ 1.35v SET LLC Medium(lvl3) vdroop to 1.306v in R20


----------



## Yviena

Does anyone know of any reasons why ram testing would restart my pc around 8-11 cycles in TM5, I literally have no idea what to change as I don't get any errors, especially when a restart would erase the error codes?

Also just curious but why is dram calculator recommending TWR at 12 with 4xSR B-die X570 when lowering it to 10 has increased my stability considerably.


----------



## rares495

Yviena said:


> Does anyone know of any reasons why ram testing would restart my pc around 8-11 cycles in TM5, I literally have no idea what to change as I don't get any errors, especially when a restart would erase the error codes?
> 
> Also just curious but why is dram calculator recommending TWR at 12 with 4xSR B-die X570 when lowering it to 10 has increased my stability considerably.


Restarts usually come from too little VDDG/SOC voltage. You should post a screenshot of ZenTimings though.

The calculator is just a basic tool for beginners. Once you get past a certain level, it's safe to ignore it and do your own thing.


----------



## Ark-07

Hi wanted to get some input on what else i can do to improve my ram settings.
*Stock 18-22-22-42 3600mhz hynix cjr @1.35v.
Overclocked 16-19-19-36 @1.36v with trc tweaked from 86 to 70 and tRFC from 630 to 490*. The second timing never boots below 19 i have managed 16-19-18-35 but I dont know if its ok to have that kind of timing? Do the first numbers in the timings have to be lower?

Ran aida64(2hrs), prime95 large fft(3hrs) and memtest86(8hrs) all passed . I did try 3800mhz with matching flck for my ryzen 3900xt keeps crashing while in windows. Did notice my soc voltage never goes above 1.075v stock and tried 1.12soc voltage and memory voltage at 1.4v I still crash so im sticking with 3600mhz and better timings. I wanted ask what other timings can i safely try change? I noticed changing the tRFC time changed other timings and improved them as well. Honestly changing that tRFC made a huge difference for me system feels far more responsive and benchmark scores improved as well.


----------



## Yviena

rares495 said:


> Restarts usually come from too little VDDG/SOC voltage. You should post a screenshot of ZenTimings though.
> 
> The calculator is just a basic tool for beginners. Once you get past a certain level, it's safe to ignore it and do your own thing.


Yeah will do, on another note does anyone have any RTT/ cad_bus recommendations for 4X8 SR on x570 motherboards?
I have a annoying error 11 that only appears during prolonged stress testing around 1-2 hour in, I've already tried clkdrvstr at 40/60.
ATM i'm just trying to get 3800CL16 stable as a baseline so i have something to fallback to if tightening timings further fail.
I had a somewhat easier time getting 4x8SR stable with my C6H at 3800CL16 GDM, the C6H didn't want to even booth without GDM at that frequency though so in some ways this board is both better, and worse, but 3800Cl16 i think is pretty good especially with 4XSR which should be equivalent in performance to 2XDR, or higher clocked 2xSR right?


----------



## paih85

Yviena said:


> Yeah will do, on another note does anyone have any RTT/ cad_bus recommendations for 4X8 SR on x570 motherboards?
> I have a annoying error 11 that only appears during prolonged stress testing around 1-2 hour in, I've already tried clkdrvstr at 40/60.
> ATM i'm just trying to get 3800CL16 stable as a baseline so i have something to fallback to if tightening timings further fail.
> I had a somewhat easier time getting 4x8SR stable with my C6H at 3800CL16 GDM, the C6H didn't want to even booth without GDM at that frequency though so in some ways this board is both better, and worse, but 3800Cl16 i think is pretty good especially with 4XSR which should be equivalent in performance to 2XDR, or higher clocked 2xSR right?



try procodt 30 ohm & clkdrvstr 40 ohm


----------



## mongoled

Yviena said:


> Yeah will do, on another note does anyone have any RTT/ cad_bus recommendations for 4X8 SR on x570 motherboards?
> I have a annoying error 11 that only appears during prolonged stress testing around 1-2 hour in, I've already tried clkdrvstr at 40/60.
> ATM i'm just trying to get 3800CL16 stable as a baseline so i have something to fallback to if tightening timings further fail.
> I had a somewhat easier time getting 4x8SR stable with my C6H at 3800CL16 GDM, the C6H didn't want to even booth without GDM at that frequency though so in some ways this board is both better, and worse, but 3800Cl16 i think is pretty good especially with 4XSR which should be equivalent in performance to 2XDR, or higher clocked 2xSR right?


I would first look at sorting out your trfc, how did you come to that value when using [email protected] ???

There are many tools out there for calculating the correct values.

Just the basics tRTP x tRC = tRFC so you have 8 x 48 = 384 and you are using 288 ??

Or you drop tRTP to 6, then 6 x 48 = 288

But you would also have to adjust tWR to be double tRTP you are currently using 10









Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com












tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com


----------



## Yviena

mongoled said:


> I would first look at sorting out your trfc, how did you come to that value when using [email protected] ???
> 
> There are many tools out there for calculating the correct values.
> 
> Just the basics tRTP x tRC = tRFC so you have 8 x 48 = 384 and you are using 288 ??
> 
> Or you drop tRTP to 6, then 6 x 48 = 288
> 
> But you would also have to adjust tWR to be double tRTP you are currently using 10
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com


EDIT: nvm dram calculator was giving me wrong TRTP values that's why I used tRTP at 8.


----------



## TwilightRavens

Did some more fine tuning on my dual rank 3800MHz b-die Neo kit, brought SoC down from 1.16v to 1.13v, adjusted CAD BUS and RTT NOM settings according to DRAM calc, adjusted a few sub timings that weren’t totally optimal, and overall lowered latenc a bit from 64.3ns to 63.7ns. Not a huge jump but I’m proud of it nonetheless. Personally not comfortable going above 1.452v on the RAM since it was a $320 kit when I bought it and I’m broke, even though I’m sure it would be fine. I might try to lower SoC a bit more to 1.12v once I’m sure this is stable but for now it seems fine. I do remember trying 1.5v and there wasn’t any gain in headroom but that was also before I got the Vengeance RAM cooler that blows air directly on the RAM.


----------



## Yviena

Hmm I was getting a error 4, or 5 after 7 passes with correct TRTP 6 TWR12, I tried setting TRDWR/TWRD from 10/3 to the recommended 9/4 but computer won't even power up the peripherals then with no display signal...

Also is FCLK supposed to move with the timings checker?


----------



## Ark-07

Are there any side effects of not following the ryzen dram calculator? Just changing trfc/rfc and timings?


----------



## TwilightRavens

Ark-07 said:


> Are there any side effects of not following the ryzen dram calculator? Just changing trfc/rfc and timings?


Non guaranteed stability, though DRAM calc can’t fully guarantee that either tbh.


----------



## Yviena

Managed to get my 3800Cl16 stable by putting in the.timings from the excel sheet than the dram calculator but... is there actually any performance loss running GDM, the latency is the same, and I can either choose GDM with TwrwrSc at 1, or GDM off with TwrwrSc at 4, looking at the dram calculator benchmark though I get a way better score with TwrwrSc at 1 with GDM than it set at 4, maybe i can squeeze it down to 2 instead as 4 was the auto value from the motherboard.


----------



## SneakySloth

Yviena said:


> Managed to get my 3800Cl16 stable by putting in the.timings from the excel sheet than the dram calculator but... is there actually any performance loss running GDM, the latency is the same, and I can either choose GDM with TwrwrSc at 1, or GDM off with TwrwrSc at 4, looking at the dram calculator benchmark though I get a way better score with TwrwrSc at 1 with GDM than it set at 4, maybe i can squeeze it down to 2 instead as 4 was the auto value from the motherboard.


It really doesn't seem like its worth it. I've tried for the last few days to disable GDM and still keep tight timings but its too much testing and effort required. Using B die, heat is definitely the biggest problem for myself.


----------



## Yviena

SneakySloth said:


> It really doesn't seem like its worth it. I've tried for the last few days to disable GDM and still keep tight timings but its too much testing and effort required. Using B die, heat is definitely the biggest problem for myself.


I think I've managed to get 3800CL16 1T with TwrwrSc at 1 stable, I got a error 0, but after changing procODT to 40 it's now at cycle 18ish in tm5 without errors, if it passes around 20-22 cycles i think i can call it stable.

I don't think I can even try to get CL15, or 14 stable as I'm already at 1.48v, I do have a ram air cooler but still...


----------



## rares495

Yviena said:


> I think I've managed to get 3800CL16 1T with TwrwrSc at 1 stable, I got a error 0, but after changing procODT to 40 it's now at cycle 18ish in tm5 without errors, if it passes around 20-22 cycles i think i can call it stable.
> 
> I don't think I can even try to get CL15, or 14 stable as I'm already at 1.48v, I do have a ram air cooler but still...


3800 CL16 with B-die subtimings is already better than everything else on the market.

Which kit do you own? Could you post a screenshot of the latest ZenTimings?


----------



## KedarWolf

I figured out if I set the below timings with SCL's at 4, reboot, enable Memory Fast Boot, reboot, set SCL's to 2, boot into Windows, I get a decent increase in AIDA64 bandwidth and TM5 passes which it doesn't if I don't enable Memory Fast Boot.

bbiab, see if I can do am hour of GSAT was well.


----------



## KedarWolf

KedarWolf said:


> I figured out if I set the below timings with SCL's at 4, reboot, enable Memory Fast Boot, reboot, set SCL's to 2, boot into Windows, I get a decent increase in AIDA64 bandwidth and TM5 passes which it doesn't if I don't enable Memory Fast Boot.
> 
> bbiab, see if I can do am hour of GSAT was well.


GSAT passed, TM5 Anta Extreme passed.


----------



## mongoled

KedarWolf said:


> I figured out if I set the below timings with SCL's at 4, reboot, enable Memory Fast Boot, reboot, set SCL's to 2, boot into Windows, I get a decent increase in AIDA64 bandwidth and TM5 passes which it doesn't if I don't enable Memory Fast Boot.
> 
> bbiab, see if I can do am hour of GSAT was well.


Glad to see other people are experimenting and seeing the "weirdness" with AIDA score dependent on enabling "Memory Fast Boot" and rebooting twice etc.

I wanted to take my investigations further so tried the following,

Disable read/write memory training, disable "Memory Fast Boot" and try to get something stable higher than 3533 mhz.

On my X370 it was not happening, pure carnage, was impossible to get anything stable.

As has been explained by Veii, there are many timings we do not have access to and without the read/write memory training we cant reach the frequency/timing combinations we are currently rocking.

However with the read/write memory training and "Memory Fast Boot" there is stuff going on that is not always producing the same results and we are never going to find out why .....

Would be interested to hear if others on X470/X570/B550 platforms experience the same issue when attempting to ramp up frequency/timings with both read/write memory training and "Memory Fast Boot" disabled.


----------



## nick name

mongoled said:


> Glad to see other people are experimenting and seeing the "weirdness" with AIDA score dependent on enabling "Memory Fast Boot" and rebooting twice etc.
> 
> I wanted to take my investigations further so tried the following,
> 
> Disable read/write memory training, disable "Memory Fast Boot" and try to get something stable higher than 3533 mhz.
> 
> On my X370 it was not happening, pure carnage, was impossible to get anything stable.
> 
> As has been explained by Veii, there are many timings we do not have access to and without the read/write memory training we cant reach the frequency/timing combinations we are currently rocking.
> 
> However with the read/write memory training and "Memory Fast Boot" there is stuff going on that is not always producing the same results and we are never going to find out why .....
> 
> Would be interested to hear if others on X470/X570/B550 platforms experience the same issue when attempting to ramp up frequency/timings with both read/write memory training and "Memory Fast Boot" disabled.


Of I definitely see better Aida scores after a reboot.


----------



## Yviena

rares495 said:


> 3800 CL16 with B-die subtimings is already better than everything else on the market.
> 
> Which kit do you own? Could you post a screenshot of the latest ZenTimings?


It crashed at round 20 so not stable yet, my entered timings is exactly the same ones as the ram calculator excel sheet gave me for 3800CL16, so not really sure why I'm unstable at 1.48v, higher voltages like 1.5 reduces stability.

EDIT: just swapped 2 of my sticks with my other PC, the same timings are now way more stable atm at tm5 cycle 25 of 30, possibly because all 4 sticks are now 3200CL14 instead of 2x 3200CL14, 2x 3600CL16.


----------



## KedarWolf

nick name said:


> Of I definitely see better Aida scores after a reboot.


I turn Memory Fast Boot off, set all my timings with SCLs at 4, reboot, it'll train my timings at what I set it at, then set Memory Fast Boot on, SCL's at 2, reboot again.

It'll keep the training at what I had it at, only with SCL's changed to 2. If I don't do it that way, both TM5 and GSAT will get errors.

And I still get decent bandwidth increase with having the SCL's at 2.


----------



## KedarWolf

Hey peeps, I get much better timings and memory overclock with tRP and tRAS set at 19-21 respectively rather than the traditional settings like DRAM Calculator suggests. 

I tried it on @Veii suggestions and improved my memory overclock and AIDA64 bandwidth quite a bit. Much easier to get stable with tighter timings.


----------



## Xplodonu

I tried CAS 14 but my latency went higher than it is at CAS 16. Can someone tell me if this is good PCB ram for overclocking. I can't get near 62 ns like some.

























If anyone see something that would help please tell me.


----------



## mongoled

Xplodonu said:


> I tried CAS 14 but my latency went higher than it is at CAS 16. Can someone tell me if this is good PCB ram for overclocking. I can't get near 62 ns like some.
> 
> If anyone see something that would help please tell me.


You will not get near 62ns regularily unless you are running an all core overclock.

From your screenshots it looks like you are using PBO.

Dont fret about the couple of ns, it makes no difference .........


----------



## mongoled

KedarWolf said:


> Hey peeps, I get much better timings and memory overclock with tRP and tRAS set at 19-21 respectively rather than the traditional settings like DRAM Calculator suggests.
> 
> I tried it on @Veii suggestions and improved my memory overclock and AIDA64 bandwidth quite a bit. Much easier to get stable with tighter timings.


Using those timings makes no difference for my setup with regards to AIDA64 bandwidth.

This could be because I am running 1T and only 16GB of RAM with a 3600.....

The only difference i saw was that the memory latency results were not consistent.

I.e. on my setup latency is usually between 62.5 to 62.9

However using the funky timings I have seen it jumping to as low as 61.8 which is unheard of for my setup and up to 63.4 while using [email protected], [email protected]

Me thinks AIDA is a benchmark that we should not rely on too much with regards to the results it throws out .


----------



## Xplodonu

Are you capable of going faster because you run 16GB of RAM? I will never be able to run that fast. Fastest I've seen it get only 1 time was 63.4. Not really worried just like playing around with it, but I know the results don't really change much even if all the timings are lower.


----------



## Xplodonu

I have disabled PBO, if I did an all core overclock does the voltage always stay high or can it scale up and down like it does currently?


----------



## Xplodonu

nevermind, it was pbo after resetting bios forgot to turn it back off.


----------



## mongoled

Xplodonu said:


> I have disabled PBO, if I did an all core overclock does the voltage always stay high or can it scale up and down like it does currently?


You must sit and read a few of the countless threads that are at this forum and across the Internet with regards to your question.

I cannot give you a nice and simple answer for your question, im sure somebody else may do, just dont understand why some people dont read about their hardware first before asking elementary questions.

Because your questions depends on many factors .

Please do yourself a favour and read the basics

*


ryzen all core overclock the basics - Google Search


*


----------



## Yviena

Managed to get this stable with 30 passes of tm5 V3 profile, anything i can do to tighten timings further without compromising stability, would 3800Cl14 2T be better than these timings on 1T if i manage to make it boot/stable?

Ram voltage is already at 1.48v but i don't think i can get it down to 3800Cl14 2T as i'm running 4xSR, maybe with 2xDR it would be possible...


----------



## crakej

Still experimenting with bios 3004. Cannot do over 3733 on it whatever I try. Higher voltage, loser timings etc.

I did some tests with timings at 3733, and though I'm getting tighter, it doesn't seem to make much difference. I have got latency down to 61.x ns, but not able to get better throughput. 4266 and 4400 XMP profile just won't work any more.

This is after TM5 run while general stuff was running - which passed even though there were 2 Windows hardware bus errors. Any obvious problems anyone can see here?


----------



## dspx

Anyone tried AGESA ComboV2 1.0.8.1?


----------



## crakej

I'm interested - what Digi Power settings do people use for their stable OCs including LLC and switching frequencies....

If I change to everything <extreme> in that section, I can't even boot...


----------



## TwilightRavens

crakej said:


> I'm interested - what Digi Power settings do people use for their stable OCs including LLC and switching frequencies....
> 
> If I change to everything in that section, I can't even boot...
> 
> 
> View attachment 2459558


Personally on my X570 Taichi I use the level 1 (which is the highest LLC setting on my board) for the CPU and level 2 or 3 (I can’t 100% remember) since there isn’t really any vdroop on SoC that I’ve noticed in the time i’ve used it for SoC if that helps.

Also I think buildzoid did some LLC switching frequencies explaining in a few of his videos that should apply to all X570 boards, can’t link it exactly but its in one of his overclocking videos, so that may be of more help than me.


----------



## crakej

TwilightRavens said:


> Personally on my X570 Taichi I use the level 1 (which is the highest LLC setting on my board) for the CPU and level 2 or 3 (I can’t 100% remember) since there isn’t really any vdroop on SoC that I’ve noticed in the time i’ve used it for SoC if that helps.
> 
> Also I think buildzoid did some LLC switching frequencies explaining in a few of his videos that should apply to all X570 boards, can’t link it exactly but its in one of his overclocking videos, so that may be of more help than me.


Thank you - I will look this up!

I've been using LLC 2 and 2 (Cpu, SoC) where 5 is max on my board....


----------



## Blue_Link

Been running these timings for about a month now, has been 100% stable. Looking to push it a little further than this, can anyone recommend any values I should try to reach? PC does not boot at 3800MHz/1900MCLK so that's a bummer. Kit is Crucial Ballistix RGB (2x8GB) 3600 CL16.


----------



## Yuke

Got tRFC 252 stable by going up to 1.48V in BIOS. No improvements at all in benchmarks compared to tRFC 264, tho...so not sure if its worth it.


----------



## PJVol

Blue_Link said:


> PC does not boot at 3800MHz/1900MCLK


What's the deal then running fclk at 1187 ?


----------



## Blue_Link

PJVol said:


> What's the deal then running fclk at 1187 ?


It's at 1866, just the FCLK fluctuates in this program


----------



## PJVol

Blue_Link said:


> It's at 1866, just the FCLK fluctuates in this program


Not sure it works that way, so i would double-check anyway.









PS:
If I get it right, the readings here (SMU related) mean nothing unless the corresponding values have been manually set in uefi
(for example VDDG and VDDP voltages in my case)


----------



## rares495

PJVol said:


> Not sure it works that way, so i would double check anyway.
> 
> View attachment 2460082


It does work that way.


----------



## Sakiz105

Blue_Link said:


> It's at 1866, just the FCLK fluctuates in this program


FLCK flactuates because of DF Cstate. it's to save energy. If you disable it it stays locked.

Same kit as you (BL8G36C16URL.M8FE1 , REV E, A2). MSI mortar max b450, ryzen 3600, all auto on cpu with pbo off.


Ram voltage is 1.38 (1.392 shows on hwinfo). try first with gdm on. Also ALWAYS disable memory fast boot, test and if everything is stable only then enable memory fast boot again. So far that's the "best" stable profile i have (dram benchmark is 117.78, latency 64.7, custom latency 69.9)


----------



## Yuke

Yuke said:


> Got tRFC 252 stable by going up to 1.48V in BIOS. No improvements at all in benchmarks compared to tRFC 264, tho...so not sure if its worth it.
> 
> View attachment 2460016


Sorry, forgot to mention. If something is "off" please tell me. :O


----------



## PJVol

rares495 said:


> It does work that way


Care to elaborate?



Sakiz105 said:


> FLCK flactuates because of DF Cstate. it's to save energy. If you disable it it stays locked.


You mean this?







If so, then apparently something's off with your claim, as the reported FCLK freq is rock stable. (previous setting was "AUTO")


----------



## rares495

PJVol said:


> Care to elaborate?
> 
> You mean this?
> View attachment 2460093
> 
> If so, then apparently something's off with your claim, as the reported FCLK freq is rock stable. (previous setting was "AUTO")


It happens sometimes.


----------



## Yuke

2T / GDM off timings attempt, please give input for improvement. Sadly cant beat my latency no matter what i try, always around 63.5ms in AIDA.


----------



## .Morello

Finally got it stable with 1900 FLCK / 3800CL14 and tweaked PBO.
I should have listened to @Veii earlier. Works great!


----------



## crakej

.Morello said:


> Finally got it stable with 1900 FLCK / 3800CL14 and tweaked PBO.
> I should have listened to @Veii earlier. Works great!


Which bit was it that worked for you?


----------



## Kildar

.Morello said:


> Finally got it stable with 1900 FLCK / 3800CL14 and tweaked PBO.
> I should have listened to @Veii earlier. Works great!


Please share your settings?


----------



## Yuke

I have set an unhealthy all core OC for a few AIDA benches to emulate my "Gaming Clocks".

It sure is faster than benching with PBO when all the tools use your weakest Core for most of the runtime...

Guess i could hit 61 with a decent FCLK OC...


----------



## Yuke

I'll try it here as well...what makes more sense?

tCWL = 16
tRDWR = 8

or

tCWL = 12
tRDWR = 10

Both are TM5 stable 

Thank you...


----------



## rares495

Yuke said:


> I'll try it here as well...what makes more sense?
> 
> tCWL = 16
> tRDWR = 8
> 
> or
> 
> tCWL = 12
> tRDWR = 10
> 
> Both are TM5 stable
> 
> Thank you...
> 
> View attachment 2460293


Lower tCWL might be beneficial but you'll have to test it yourself.


----------



## Yuke

rares495 said:


> Lower tCWL might be beneficial but you'll have to test it yourself.


Thanks! Is there btw a obvious reason why tCWL 12 + tRDWR 8 does not even boot with my timings?


----------



## rares495

Yuke said:


> Thanks! Is there btw a obvious reason why tCWL 12 + tRDWR 8 does not even boot with my timings?


That doesn't boot with any timings on any memory. tCWL 12 requires at least tRDWR 10.


----------



## .Morello

crakej said:


> Which bit was it that worked for you?





Kildar said:


> Please share your settings?


Sorry for the disappointing reply, but after further stress testing, I found out it wasn't stable. It would stay good in P95 for over one hour, but fail within 10 minutes of Aida64 stress test.
I assume it was stable because of how well it handled P95. Oh well.


----------



## werks

hello,
i just got some bdies, 
any tweaks to my timings?


----------



## Arni90

Just gonna post this here


----------



## Yuke

This is all i got without going over 1.5V in hwinfo64. 










tRCDWR = 10 would work but i could not find any information about whether changing it would make any sense.


----------



## ylpkm

Ran stable for an hour, might test further later. Procodt at 40 ohms is what stablized it, 28.2-36.9 all threw errors in karhu ram test within a min. vdimm at 1.53v.


----------



## drkCrix

Just got my new ram kit in yesterday. (32GB 2x 16 TridentZ Neo 3600C16-16-16-36)

Have them currently stable and am wondering if there are any timing tweaks or changes that you would recommend that I may have missed.

Ram is at 1.45v in bios

















Cheers and thanks,

Chris


----------



## xSneak

I just got a 3600x build setup. I was wondering what kind of voltage scaling to see on the soc, I've read that 1.2v is max and that's all I can find so far. I have the g.skill dual rank 32gb 4000mhz kit.


----------



## Yuke

Small update in tRP and tRCDWR...im probably going crazy but i have the feeling that i gained a tiny bit of latency...or my bloaty system is messing with me again...


----------



## Yviena

Quick question guys, my ram is stable 25+ cycles TM5, but I get bus interconnect errors in hwinfo64 when cinebench R20 is run, the cpu voltage/frequency was left at auto on my 3700x so what does those errors mean?


----------



## SneakySloth

Yviena said:


> Quick question guys, my ram is stable 25+ cycles TM5, but I get bus interconnect errors in hwinfo64 when cinebench R20 is run, the cpu voltage/frequency was left at auto on my 3700x so what does those errors mean?


I've found that to be related to SOC/VDDG voltages. Try bumping those up a little bit. Basically your infinity fabric isn't fully stable.


----------



## Yviena

SneakySloth said:


> I've found that to be related to SOC/VDDG voltages. Try bumping those up a little bit. Basically your infinity fabric isn't fully stable.


Hmm shouldn't tm5 capture those errors?


----------



## Esticbo

G.Skill FlareX 16GB DDR4 16GFX K2 3200 CL16 (2x8GB) / f4-3200c16d-16gfx
Samsung C die


----------



## mongoled

Yviena said:


> Hmm shouldn't tm5 capture those errors?


No, thats why people strongly suggest you run something FFT intensive after you have tested for stability with TM5, such as Y-Cruncher or Prime95 Large FFTs .....


----------



## rares495

mongoled said:


> No, thats why people strongly suggest you run something FFT intensive after you have tested for stability with TM5, such as Y-Cruncher or Prime95 Large FFTs .....


Prime and Y-Cruncher can be useless too. Same goes for any synthetic load. The best stress test is simply using the PC as you would normally. The more demanding AAA games also use a lot of memory so that would be perfect to test stability.


----------



## mongoled

rares495 said:


> Prime and Y-Cruncher can be useless too. Same goes for any synthetic load. The best stress test is simply using the PC as you would normally. The more demanding AAA games also use a lot of memory so that would be perfect to test stability.


SneakyClock responded to Yviena with regards to FCLK induced errors.

Any type of stress testing can be infered to as being useless, fail to see what you adding to the conversation by associating a negative anecdote to some possibly useful information......

Testing FCLK can be done in several ways, gaming is one of them, as is running Prime95 large FFTs and Y-Cruncher, also running hard drive benches from a nvme drive can also induce FCLK instabiity, as well is listening to audio quality.

Just dont get you posting negative info, there is no reason to do that, especially considering I never said anything was "useless" .........


----------



## rares495

mongoled said:


> SneakyClock responded to Yviena with regards to FCLK induced errors.
> 
> Any type of stress testing can be infered to as being useless, fail to see what you adding to the conversation by associating a negative anecdote to some possibly useful information......
> 
> Testing FCLK can be done in several ways, gaming is one of them, as is running Prime95 large FFTs and Y-Cruncher, also running hard drive benches from a nvme drive can also induce FCLK instabiity, as well is listening to audio quality.
> 
> Just dont get you posting negative info, there is no reason to do that, especially considering I never said anything was "useless" .........


Not trying to be negative, just don't get this overhype for synthetic tests. Yeah, they're great, but at the end of the day the best stress test is using the PC. That's all.


----------



## mongoled

rares495 said:


> Not trying to be negative, just don't get this overhype for synthetic tests. Yeah, they're great, but at the end of the day the best stress test is using the PC. That's all.


Personally have never hyped synthetic tests, always advocated a variety of tests for stability.

However, FCLK is very often quickly shown to be flaky when stressing the fabric using FFT tests, hence the reason I mentioned it, just didnt understand how you felt the need to answer the way you did.

And saying "just use the PC" to test for stability is not really the best advice because people use their PC in different ways. whats stable usage for one person may not be stable usage for another person.

So if you want a truly stable PC you need to run a variety of tests as well as using the PC for your usage case, keyword being "your". 

Its up to each person to decide what they feel is "stable" for the things they are going to do ........

Anyway this is off topic, back to giving helpful information and positive vibes.


----------



## Yuke

F... me...even tho my timings ran for ages yesterday in TM5/Karhu...this morning i had Karhu errors within minutes of running Karhu. Reduced tRFC to 264 to be in check with new tRC...maybe as a plus, i will be able to reduce DRAM voltage again, as i only needed it for tRFC 252 in the past...


----------



## DaniloFerracini

Using my old bios (from the end of last year, AGESA 1.0.0.4 A20) I was able to get 3800cl15 24/7 stable with these settings and using 1.45v, the only thing I did was use the attached manual profile and increase the voltage , however after updating the bios, my pc doesn't even boot when trying to 3800cl15, I messed with ProdcODT and CAD_BUS a little, but without success. Could someone give me some light ???


----------



## KedarWolf

drkCrix said:


> Just got my new ram kit in yesterday. (32GB 2x 16 TridentZ Neo 3600C16-16-16-36)
> 
> Have them currently stable and am wondering if there are any timing tweaks or changes that you would recommend that I may have missed.
> 
> Ram is at 1.45v in bios
> 
> View attachment 2460687
> View attachment 2460688
> 
> 
> Cheers and thanks,
> 
> Chris


Here's what I run one the same kit TM5 25 rounds stable but I'm using an older MSI AGESA 1.0.0.5 BIOS. Anything newer can't even boot 3800MHz.

Edit: I also run a BLCK overclock of 100.45.


----------



## SneakySloth

The best method in my case to test FCLK has been to run a CPU/Memory and GPU benchmark at the same time. So that could be a combination of TM5, Karhu, Y-Cruncher, Prime95 Small fft, Prime95 large fft, OCCT Small and large FFT and OCCT/AIDA GPU test. 

So pick a GPU stress test and run either a memory and cpu test alongside it. You'll stress the entire system significantly, raise temperature of the case and test a worst case scenario.

If anyone is into gaming, they should play overclock sensitive games like minecraft, overwatch, the division, battlefield etc. and see if any WHEA errors pop up. At the end of all my stress tests, it took overwatch to help me reach a stability level that I'm fairly satisfied with.


----------



## Mx King Sniper

KedarWolf said:


> Here's what I run one the same kit TM5 25 rounds stable but I'm using an older MSI AGESA 1.0.0.5 BIOS. Anything newer can't even boot 3800MHz.
> 
> Edit: I also run a BLCK overclock of 100.45.


Can I revert from 1.0.0.6 to 1.0.0.5?
How to do it? 
Should I flash new one directly?


----------



## KedarWolf

I don't think your board has an AGESA 1.0.0.5 BIOS.






X470 GAMING PLUS (MS7B79)


Asus ROG RAMPAGE VI EXTREME Bios & Drivers




www.station-drivers.com


----------



## nowarranty

here's a question for anyone who might be on in the next few hours.
i'm using a samsung b-die kit tightened to c14 3600mhz, a g skill kit.
i see a $99 sale on newegg for 32gb kit of c16 3200mhz xpg ram.
am I really going to lose out on that much performance? i know ryzen is heavily dependent on ram speeds and have no idea if that 3200mhz xpg kit can push 3600 or 3600 with decent timings. but for $99 i'd be getting twice the ram and that would help me with virtualization workloads.


----------



## Yviena

Ehh i think my CPU just can't do 1900 FCLK with GDM off, I remember I could do 3800C16 GDM on with my C6H, maybe i can do it with GDM enabled on my tomahawk x570 also, but I believe trying to get 3733CL15 GDM off will be better even if AIDA64 reports higher memory latency due to lower infinity fabric speed.

Also what does the error info mean when it says: 
suspect tWR being too slow

mostly affects the first 5 main timings 
- noticed it can be tRCDWR to RD, can be tRP too,

but it also can be the last two tRDWR & tRDRD 
which don't play well with your main tRCDWR/RD

does it mean to lower the timing, or increase it?


----------



## Mx King Sniper

KedarWolf said:


> I don't think your board has an AGESA 1.0.0.5 BIOS.
> 
> 
> 
> 
> 
> 
> X470 GAMING PLUS (MS7B79)
> 
> 
> Asus ROG RAMPAGE VI EXTREME Bios & Drivers
> 
> 
> 
> 
> www.station-drivers.com


It have, it was Max version
I updated from 1.0.0.4 to 1.0.0.6 directly. 
I can't able to boot 1900 flck but stable in 3733mhz GDM Off


----------



## Yviena

Weird I get one WHEA 19 error on startup every time I start TM5 but only on the first time after a reboot, even on 3733mhz, idk if it's a IF FCLK error anymore...

EDIT: seems i needed to put VDDG CCD/IOD to 1.080v isn't this a little high for just 3800/3733mhz?


----------



## DaniloFerracini

I got 3800cl15 again, it was all about the procODT and CAD_Bus, as I wasn't finding an old build of the DRam calculator I didn't know what parameters worked with me, I managed to find 1.7.0 and saw what worked. 
Would these parameters work in a newer BIOS? I heard that depending on the BIOS the Cad_Bus and procODT change a lot ...


----------



## KedarWolf

DaniloFerracini said:


> I got 3800cl15 again, it was all about the procODT and CAD_Bus, as I wasn't finding an old build of the DRam calculator I didn't know what parameters worked with me, I managed to find 1.7.0 and saw what worked.
> Would these parameters work in a newer BIOS? I heard that depending on the BIOS the Cad_Bus and procODT change a lot ...
> View attachment 2461255


To find old versions of Dram Calculator find the latest version on TechPowerUp and click the Older Versions link below and it'll bring up every version of it.


----------



## DaniloFerracini

Is 1.5v for 24/7 on b-die 100% safe? 

what would be the highest voltage for 24/7?


----------



## Yviena

Damn i need 1.47v just to get 3733CL16 with the timings the excel spreadsheet gave me just to be stable, I couldn't even use TWR 12 due to error 10, I must have really ****ty ram, or it could just be x570 daisy chain topology as I had 3800C16 stable with 1.45v on C6H


----------



## Dr. Vodka

Yviena said:


> Damn i need 1.47v just to get 3733CL16 with the timings the excel spreadsheet gave me just to be stable, I couldn't even use TWR 12 due to error 10, I must have really ****ty ram, or it could just be x570 daisy chain topology as I had 3800C16 stable with 1.45v on C6H


If you had 4 sticks of memory on your C6H, that's the ideal situation for a T-topology board, all slots populated with the same memory.

Daisy chain boards will struggle relative to a T-topology board with all slots populated when pushing for the maximum stable settings.


----------



## rares495

Yup. Slots 1 & 3 on a Daisy chain board are horrible. The solution is simple: buy 2x16GB.


----------



## Yuke

DaniloFerracini said:


> Is 1.5v for 24/7 on b-die 100% safe?
> 
> what would be the highest voltage for 24/7?


1.5V should be fine considering that G-Skill are selling kits rated at 1.5V.

Most people here even go higher for 24/7 it seems...i set my own limit to 1.5V hwinfo64 readout, which sucks because i could get a significant performance jump at 1.53V.


----------



## Yviena

Dr. Vodka said:


> If you had 4 sticks of memory on your C6H, that's the ideal situation for a T-topology board, all slots populated with the same memory.
> 
> Daisy chain boards will struggle relative to a T-topology board with all slots populated when pushing for the maximum stable settings.


Yeah but I needed a x570 board for the new 5800x/5900x

Seems i managed to stabilize FCLK at 1900mhz with
VDDP: 0.925v
CCD 1.0v
IOD: 1.075v
SOC: 1.150v

Dunno if 1.15v soc is safe, and how much worse temperatures are with higher soc values though, but maybe I can use 50mv stepping for SOC so 1.125v instead.

I also bumped up vdimm from 1.47 to 1.48 when testing 3800mhz now.


----------



## PJVol

rares495 said:


> It happens sometimes


Just have noticed, thats the case for my b550


----------



## Yuke

Hmmm, i had to up my VDDG after upgrading to F30.

VSoC: 1100mV
VDDP: 0950mV
VDDG: 1075mV

VDRAM: 1.5V

should be still fine for 24/7?


----------



## SneakySloth

Yuke said:


> Hmmm, i had to up my VDDG after upgrading to F30.
> 
> VSoC: 1100mV
> VDDP: 0950mV
> VDDG: 1075mV
> 
> VDRAM: 1.5V
> 
> should be still fine for 24/7?


Difference between VDDG and VSOC needs to be at least 40mv. You should up the VSOC to 1.125v


----------



## KedarWolf

Checked this thread for RTT settings. Changing to 5|3|1 helped me get SCL's stable at 2. I had 0|3|1 as recommended by DRAM calculator.


----------



## shenosuke

KedarWolf said:


> Checked this thread for RTT settings. Changing to 5|3|1 helped me get SCL's stable at 2. I had 0|3|1 as recommended by DRAM calculator.
> 
> View attachment 2461716
> 
> 
> View attachment 2461717


I read somewhere that run ClkDrvStr at 60 or 120ohms is risky to components. is it true or bullshit?


----------



## Notbn

Hey guys I have a set of 2x8GB Patriot Viper Steel 4400CL19 running at 3733CL16 1T @1.35V on an X570 Unify with a 3800X rock solid stable. My kit can do 3800CL16 easily, but I think my IF isn't quite stable at 1900.

My question is, if I add another 2x8GB kit, will I still be able to achieve 3733CL16? Should I just get a 2x16GB dual rank kit? Any recommendations?

I need some extra RAM as I find myself running a lot more CAD simulations as of late.


----------



## mongoled

mongoled said:


> Have you done this before A0 & A2 ??
> 
> I was going to buy a 5th set of A2, last attempt to get a good second pair and saw your post ...
> 
> This current set I am testing is stuggling to get 3800/1900 stable using CL15 ....


Sooooo, I have the A0 kit and an X570 Unify.

Firstly,

Booting 4 x A2s @3800/1900 2T-14-16-14-14-30-46 @1.5v was a piece of piss on this motherboard.

This was impossible on the X370.

Booting 2 x A2s + 2 x A0s @3800/1900 2T-14-16-14-14-30-46 @1.5v is also a piece of piss on this motherboard.

Which slots is preferable for the A2s?

I currently have them in B1/B2 (furthest from CPU) and the A0s are in A1/A2 (closest to CPU).

Currently establishing a baseline overclock so would prefer to start off with the RAM sticks in the "correct" slots

Using below settings, lets see how long this will run


----------



## Yviena

I'm trying to get another computer stable, and I'm getting error 10: Suspect TWR being too slow, after 12 passes does anyone know what this actually means?


----------



## rares495

Yviena said:


> I'm trying to get another computer stable, and I'm getting error 10: Suspect TWR being too slow, after 12 passes does anyone know what this actually means?


Error 10 is usually related to the 5 main timings but can also be tRDWR/tWRRD in relation to tRCDRD/tRCDWR.


----------



## SneakySloth

mongoled said:


> Sooooo, I have the A0 kit and an X570 Unify.
> 
> Firstly,
> 
> Booting 4 x A2s @3800/1900 2T-14-16-14-14-30-46 @1.5v was a piece of piss on this motherboard.
> 
> This was impossible on the X370.
> 
> Booting 2 x A2s + 2 x A0s @3800/1900 2T-14-16-14-14-30-46 @1.5v is also a piece of piss on this motherboard.
> 
> Which slots is preferable for the A2s?
> 
> I currently have them in B1/B2 (furthest from CPU) and the A0s are in A1/A2 (closest to CPU).
> 
> Currently establishing a baseline overclock so would prefer to start off with the RAM sticks in the "correct" slots
> 
> Using below settings, lets see how long this will run
> 
> View attachment 2462349


Why dont you try A0/A2/A0/A2?


----------



## mongoled

SneakySloth said:


> Why dont you try A0/A2/A0/A2?


That's how I have them


----------



## SneakySloth

mongoled said:


> That's how I have them


I thought you had it was A0/A0/A2/A2. My bad. The last set of timings didn't work I'm guessing? I'm waiting for a sale on a A0 Viper 4000MHZ set. Whenever they go on sale I'll try and test this out as well on a x570 tomahawk


----------



## rares495

SneakySloth said:


> I thought you had it was A0/A0/A2/A2. My bad. The last set of timings didn't work I'm guessing? I'm waiting for a sale on a A0 Viper 4000MHZ set. Whenever they go on sale I'll try and test this out as well on a x570 tomahawk


Why not get the 4400 vipers? They're better than the 4000 and are quite cheap atm.


----------



## mongoled

SneakySloth said:


> I thought you had it was A0/A0/A2/A2. My bad. The last set of timings didn't work I'm guessing? I'm waiting for a sale on a A0 Viper 4000MHZ set. Whenever they go on sale I'll try and test this out as well on a x570 tomahawk


Actually, its me bad

I assumed A1/A2 & B1/B2 are the correct designation, but its actually A1/B1, A2/B2 with A2/B2 being the optimised dimm slots.

So I have them in the correct slots, just did not explain that properly.

Anyhow, I now have a dead A0 stick



It happened after the PC went to sleep (after changing motherboard I forgot that the power options got reset) so I came out of sleep (did not re start) and re-started the test.

Before the PC went to sleep it had reached the 6th cycle with no errors.

On re-starting TM5, it instantly had 4 errors and then the PC froze.

I tired to boot and got the dreaded 27 --> 0d

Reset CMOS, nada

So I pull out all 4 dimms, insert both A2s, PC posts

Insert both A0s PC does not post

I test both A0s in slot B2, one of them posts, the other is dead.



So it looks like something happened when the PC went to sleep and came out of sleep.

Currently got the 4 x A2s plugged in ….



rares495 said:


> Why not get the 4400 vipers? They're better than the 4000 and are quite cheap atm.


Its been asserted (Veii) that its best to get one set of A0s and one set of A2s


----------



## mongoled

For those wanting to run 4 x 8GB A2s,

My first TM5 no errors result below










Having played with this mobo for a few days now, it seems that the read memory bandwidth, at least in AIDA is worse than my X370 motherboard.

I am going to have to do a clean install just to make sure as all my tinkering has been done on the same OS, I simply switched motherboards.


----------



## amd7674

Hi Guys,

I'm building two new PCs for my kids (their $$$ savings). I will be picking up either 5800x or 5900x on x570 tomahawk mobos. For ram they went for bling Corsair Dominator white 4x8gb Micron E-Die (CMT32GX4M4C3600C18W). it is not greatest, but does anyone know if it can be o/c?

Thanks in advance.


----------



## herericc

amd7674 said:


> Hi Guys,
> 
> I'm building two new PCs for my kids (their $$$ savings). I will be picking up either 5800x or 5900x on x570 tomahawk mobos. For ram they went for bling Corsair Dominator white 4x8gb Micron E-Die (CMT32GX4M4C3600C18W). it is not greatest, but does anyone know if it can be o/c?
> 
> Thanks in advance.


Yeah E-Die are good overclockers.


----------



## rares495

herericc said:


> Yeah E-Die are good overclockers.


Wouldn't call them good. They're alright.


----------



## amd7674

herericc said:


> Yeah E-Die are good overclockers.


Thanks


----------



## kratosatlante

[QUOTE = "mongoled, publicación: 28653848, miembro: 244543"]
Para aquellos que quieran ejecutar 4 x A2 de 8 GB,

Mi primer TM5 sin errores resulta a continuación

View attachment 2462509


Después de haber jugado con este mobo durante unos días, parece que el ancho de banda de la memoria de lectura, al menos en AIDA, es peor que mi placa base X370.

Voy a tener que hacer una instalación limpia solo para asegurarme de que, como todos mis retoques se han realizado en el mismo sistema operativo, simplemente cambié las placas base.
[/CITAR]
Hola, mismo carnero, prueba esto










1.54v en el BIOS


o este 2t gdm de








yots no work, have more configs, cl14 trfc 240 1.45-1.48 v


----------



## amd7674

Any good starting point for Corsair Dominator white 4x8gb Micron E-Die (CMT32GX4M4C3600C18W)?  KitGuru was able to run it quickly at 4000 at 1.5V. Since I'm awaiting zen3 CPU, I'm posting some pictures from the review stock and quick o/c. 

Any help would be much appreciated.


----------



## ryouiki

Any recommendations for the attached? I've been rebuilding one of my 3900X systems and made some adjustments to memory timings... this chip is not capable of IF @ 1900 regardless of settings, so even though the memory is perfectly capable, I'm stuck at 3733.

The RAM is 2 sticks of A0 B-Die (FlareX) and 2 sticks of A2 B-Die (Flare X) for 32GB SR.

One thing I haven't gotten to yet is trying to adjust VDDG, the motherboard seems to default to 1050mv once you go above 1800 IF unless told otherwise. Right now everything is stable (TM5 40 Cycles, Karhu 12000%), so I haven't really wanted to make voltage adjustments until I was 100% sure the current timings are working as expected.

GDM off seems just not worth the effort, I can get close to stable, but it seems to require far more voltage/heat then I would really like.


----------



## herericc

rares495 said:


> Wouldn't call them good. They're alright.


Sure, but relative to anything other than B die, they're "good".


----------



## rares495

herericc said:


> Sure, but relative to anything other than B die, they're "good".


They're also worse than Micron Rev. B


----------



## amd7674

rares495 said:


> They're also worse than Micron Rev. B


I'm not expert, but it seems decent.  Also this site says nice things about it... 

*8Gbit Rev.E <-- Assuming that's what I have, apologies in advance if I'm wrong... LOL *

_Characteristics_: 3466 14-17-17-36 and 3600 14-20-15-36 seen on Ryzen with GDM and 1.45V memory voltage, both fully stable. On intel, seen at 3400 13-18-18-36 2T 1.5V stable. Techpowerup also got a 3200 16-18-18 dual rank stick to 3800 16-18-18, which seemed to be limited by failure to loosen tRCD.

Seems to scale pretty well with voltage for benching.

Set a new memory frequency world record(!!!!) on 16th of may 2019 with an 8086k, memory and cpu both on LN2 cooling - DDR4-*5726* 24-31-31-63 at presumably very high voltage.

_Found on_: Seen in 2019 Crucial Ballistix 8GB sticks with DDR4-3000 15-16-16 1.35V XMP. _Presumably_ Corsair ver3.34 and Micron OEM sticks. Given the OC headroom, likely to be in higher rated Crucial kits as well - confirmed in DDR4-3600 Ballistix Elite and presumed in 2019 3200 and 3466 kits.

_Platform preferences_: Intel's combined tRCDtRP for 1151 is a limitation on this ram, does great on ryzen though with top tier daily settings.

_Recommended for_: Awesome option for cheap Ryzen daily, on Intel Hynix CJR is probably better as it does higher frequency and doesn't need tRCD as high, but this is still a very good option. Seems to be more consistent than Samsung B-die, so should outperform unbinned/OEM B-die on Ryzen. Turns out it's also good for smashing memory WRs - might be easier to run than b-die which probably contributes.


----------



## rares495

amd7674 said:


> with top tier daily settings.


LMAO.


----------



## amd7674

rares495 said:


> LMAO.


whatever float your boat


----------



## KedarWolf

amd7674 said:


> I'm not expert, but it seems decent.  Also this site says nice things about it...
> 
> *8Gbit Rev.E <-- Assuming that's what I have, apologies in advance if I'm wrong... LOL *
> 
> _Characteristics_: 3466 14-17-17-36 and 3600 14-20-15-36 seen on Ryzen with GDM and 1.45V memory voltage, both fully stable. On intel, seen at 3400 13-18-18-36 2T 1.5V stable. Techpowerup also got a 3200 16-18-18 dual rank stick to 3800 16-18-18, which seemed to be limited by failure to loosen tRCD.
> 
> Seems to scale pretty well with voltage for benching.
> 
> Set a new memory frequency world record(!!!!) on 16th of may 2019 with an 8086k, memory and cpu both on LN2 cooling - DDR4-*5726* 24-31-31-63 at presumably very high voltage.
> 
> _Found on_: Seen in 2019 Crucial Ballistix 8GB sticks with DDR4-3000 15-16-16 1.35V XMP. _Presumably_ Corsair ver3.34 and Micron OEM sticks. Given the OC headroom, likely to be in higher rated Crucial kits as well - confirmed in DDR4-3600 Ballistix Elite and presumed in 2019 3200 and 3466 kits.
> 
> _Platform preferences_: Intel's combined tRCDtRP for 1151 is a limitation on this ram, does great on ryzen though with top tier daily settings.
> 
> _Recommended for_: Awesome option for cheap Ryzen daily, on Intel Hynix CJR is probably better as it does higher frequency and doesn't need tRCD as high, but this is still a very good option. Seems to be more consistent than Samsung B-die, so should outperform unbinned/OEM B-die on Ryzen. Turns out it's also good for smashing memory WRs - might be easier to run than b-die which probably contributes.


On my Trident Z Neo b-die 2x16GB Dual Rank RAM I get 14-16-8-21-19-42 tRFC 252 TM5 25 rounds stable with really tight secondary timings. Get really great AIDA64 read, write and copy and 61.7 latency. I'm at work now, but have screenshots of it in earlier posts.


----------



## theguz4l

Just got these dimms: 8Gb x 2 Dimm: Team T-Force DARK Pro 16GB (2 x 8GB) 288-Pin DDR4 SDRAM DDR4 3200 (PC4 25600)
Samsung B-Die

DDR4 3200 (PC4 25600)
Timing 14-14-14-31
CAS Latency 14
Voltage 1.35V
Does the Ryzen DRAM tool help me get to DDR4 3600 CL16? Anyone have these chips?


----------



## herericc

theguz4l said:


> Just got these dimms: 8Gb x 2 Dimm: Team T-Force DARK Pro 16GB (2 x 8GB) 288-Pin DDR4 SDRAM DDR4 3200 (PC4 25600)
> Samsung B-Die
> 
> DDR4 3200 (PC4 25600)
> Timing 14-14-14-31
> CAS Latency 14
> Voltage 1.35V
> Does the Ryzen DRAM tool help me get to DDR4 3600 CL16? Anyone have these chips?


I have 2 sets of that DRAM - you should easily achieve 3600CL16 safe from DRAM CALC, assuming you're using a ryzen 3000 series CPU.
If you're lucky with your Infinity Fabric you should even be able to run 3800 safe on them too.

I haven't tweaked too too much lately since I'm hoping to get a ryzen5k (which i'll then tweak the crap out of my memory for)


----------



## ColdDeckEd

Yes it can help you get to 3600 cl16. No doubt it'll be easy with that ram.

Finally having some success getting my samsung c die (sp xpower turbine 3200 kit with K4A8G085WB-BCRC modules) from 3200 cl16 to 3600 cl18. These chips hate voltage above 1.35 which kind of limits your headroom but I dropped my latency from 72 ns to 68 ns so I'm happy with that.


----------



## Yuke

I officially declare 24/7 stability after testing over the last weeks ._.


----------



## mongoled

Yuke said:


> I officially declare 24/7 stability after testing over the last weeks ._.
> 
> View attachment 2463025


At last, someone with a 1 CCX CPU posted an AIDA with 32GB RAM using GDM enabled on X570 platform, thanks, I needed something to compare with as I think my results are a little low with regards to read throughput.

Below is my current stable settings, read throughput is similar to what you have, but I am running 4 x 8GB single rank modules










Disabling GDM I can boot fine with the above settings but TM5 errors almost instantly followed with a blue screen. 

Am waiting for a new pair of A0s to arrive as when I briefly tested 2 x A2s with 2 x A0s 1T was running stable, pitty one of the A0 stickd decided to die......


----------



## theguz4l

theguz4l said:


> Just got these dimms: 8Gb x 2 Dimm: Team T-Force DARK Pro 16GB (2 x 8GB) 288-Pin DDR4 SDRAM DDR4 3200 (PC4 25600)
> Samsung B-Die
> 
> DDR4 3200 (PC4 25600)
> Timing 14-14-14-31
> CAS Latency 14
> Voltage 1.35V
> Does the Ryzen DRAM tool help me get to DDR4 3600 CL16? Anyone have these chips?


So an update... I can't seem to get DDR4 3600 stable on these 8x2 b-die chips.
When I use the 'bad bin' setting which is 16-16-20-20-36 or something, I am able to go about 3 hours without errors but the 4th hour crashed. I tried 16-16-19-19-36 and it lasted about 20 minutes.
Could it be my FCLK is bad on my chip or is that unlikely? These DRAM chips may just be not great. I have a brand new 3900X chip, I was able to boot into windows at DDR4 3766/1866 FCLK but DDR4 3800/1900 did not boot and I had to clear CMOS with battery, so i wont try that again.

I tried DDR4 3400 recommended ryzen dram calc settings and instant errors. Maybe my chips are just not great at going past 3200? The guy I bought them from said he could only run 2933Mhz with 4 of the dimms on a 2700X. I just bought 2 of his 4 and figured it was because he was doing 4 dimms.

XMP settings (DDR4 3200 14-14-14-31) are rock solid and passed all benches after 6+ hours.

SOC Voltage is always 1.1 (1.087 in windows in HW Mon, 1.125 bios reading) and the DRAM VOltage is whatever Ryzen dram calc says to set recommended to.)
I have a brand new Phanteks P500a, so my case has excellent airflow and my 3900X is AIO cooled, doesnt go above 45c during ram testing.


----------



## KedarWolf

This with the TM5 1usmus_v3 config, but changed to be kinda like the Anta Extreme. 1000%, and three rounds. It runs each individual test for at least 5 minutes, stresses the IMC a lot.

If you want to run it overnight while you sleep for, on a 3950x, about 8 hours, change the 3 rounds to 8 rounds.









1usmus_v3_1000%.cfg







drive.google.com


----------



## Yuke

mongoled said:


> At last, someone with a 1 CCX CPU posted an AIDA with 32GB RAM using GDM enabled on X570 platform, thanks, I needed something to compare with as I think my results are a little low with regards to read throughput.
> 
> Below is my current stable settings, read throughput is similar to what you have, but I am running 4 x 8GB single rank modules
> 
> View attachment 2463258
> 
> 
> Disabling GDM I can boot fine with the above settings but TM5 errors almost instantly followed with a blue screen.
> 
> Am waiting for a new pair of A0s to arrive as when I briefly tested 2 x A2s with 2 x A0s 1T was running stable, pitty one of the A0 stickd decided to die......


looking good, i need 1.54V in BIOS for CL14 timings...maybe ill give it a try with Zen3 at some point but not worth running them 24/7 on my bad bin 3800x.


----------



## Yviena

Has anyone had the issue that RYZEN sometimes when cold booting trains wrong, and a ram overclock that is guaranteed stable, becomes unstable but all the values in bios are shown to be the same requiring to reload the profile instead to get it stable again?


----------



## nick name

Yviena said:


> Has anyone had the issue that RYZEN sometimes when cold booting trains wrong, and a ram overclock that is guaranteed stable, becomes unstable but all the values in bios are shown to be the same requiring to reload the profile instead to get it stable again?


That doesn't sound like a Ryzen issue, but a mobo/BIOS issue. Which mobo do you use?


----------



## KedarWolf

Yviena said:


> Has anyone had the issue that RYZEN sometimes when cold booting trains wrong, and a ram overclock that is guaranteed stable, becomes unstable but all the values in bios are shown to be the same requiring to reload the profile instead to get it stable again?


When I get my RAM overclock TM5 stable, I immediately reboot in BIOS and turn off the RAM Training, Enable Fast Boot, whatever it is on your board option, helps keep me stable between boots.


----------



## Yviena

The tomahawk x570 doesn't seem to have a disable clear training button like my C6H had, fast boot is on though.


----------



## mongoled

Yviena said:


> The tomahawk x570 doesn't seem to have a disable clear training button like my C6H had, fast boot is on though.


Go into the advanced memory section, I think its in the misc section look for

DFE Read Training
FFE Write Training

Set both to "Disabled"

** EDIT **
Doing this makes my RAM settings unstable!

Im unsure if there is another way to disable memory training


----------



## SneakySloth

Has anyone tried the 'MSI Latency Enhance' option in the fewer BIOS releases from MSI?


----------



## mongoled

SneakySloth said:


> Has anyone tried the 'MSI Latency Enhance' option in the fewer BIOS releases from MSI?


Yes, I did not see any improvement whatever setting I tried, all within the margin of error.

I only tested with AIDA64, with other applications maybe there is a difference ...


----------



## Price

theguz4l said:


> Just got these dimms: 8Gb x 2 Dimm: Team T-Force DARK Pro 16GB (2 x 8GB) 288-Pin DDR4 SDRAM DDR4 3200 (PC4 25600)
> Samsung B-Die
> 
> DDR4 3200 (PC4 25600)
> Timing 14-14-14-31
> CAS Latency 14
> Voltage 1.35V
> Does the Ryzen DRAM tool help me get to DDR4 3600 CL16? Anyone have these chips?


I am running 3733 16-16-16-32 @ 1.344v

[email protected]


----------



## ColdDeckEd

theguz4l said:


> So an update... I can't seem to get DDR4 3600 stable on these 8x2 b-die chips.
> When I use the 'bad bin' setting which is 16-16-20-20-36 or something, I am able to go about 3 hours without errors but the 4th hour crashed. I tried 16-16-19-19-36 and it lasted about 20 minutes.
> Could it be my FCLK is bad on my chip or is that unlikely? These DRAM chips may just be not great. I have a brand new 3900X chip, I was able to boot into windows at DDR4 3766/1866 FCLK but DDR4 3800/1900 did not boot and I had to clear CMOS with battery, so i wont try that again.
> 
> I tried DDR4 3400 recommended ryzen dram calc settings and instant errors. Maybe my chips are just not great at going past 3200? The guy I bought them from said he could only run 2933Mhz with 4 of the dimms on a 2700X. I just bought 2 of his 4 and figured it was because he was doing 4 dimms.
> 
> XMP settings (DDR4 3200 14-14-14-31) are rock solid and passed all benches after 6+ hours.
> 
> SOC Voltage is always 1.1 (1.087 in windows in HW Mon, 1.125 bios reading) and the DRAM VOltage is whatever Ryzen dram calc says to set recommended to.)
> I have a brand new Phanteks P500a, so my case has excellent airflow and my 3900X is AIO cooled, doesnt go above 45c during ram testing.


I'd be really surprised if your cpu couldn't hit 1900 fclk but I think you'll need to raise your voltage above 1.4. Maybe try turning on GDM and conservative timings (like 18 18 18 38?) to get it to boot and be stable, then work your timings down?


----------



## TwilightRavens

ColdDeckEd said:


> I'd be really surprised if your cpu couldn't hit 1900 fclk but I think you'll need to raise your voltage above 1.4. Maybe try turning on GDM and conservative timings (like 18 18 18 38?) to get it to boot and be stable, then work your timings down?


I would be too, on my 3900X I originally needed 1.16v on SoC to even POST but once I started messing with I/O and VDDG voltages I was able to drop it to 1.10v. However my dual rank b-die kit still needs 1.452v for 3800/C16, 1.5v lets me POST at C14 but I quickly get errors in HCI memtest. Maybe try messing with VDDG, VDDP and I/O and see if that nets anything if you are curious to try.


----------



## DroidGeek69

Ok I will start with I am total noob. Never tweaked my computer before. I did phone roms back in Droid 2 era. I think I can run fast with both CPU and memory but haven't figure the magic numbers yet. I have Windows 10 2004 and Asus PRIME B350-PLUS with Version 5602 bios and I am running a AMD Ryzen™ 7 1700 with CORSAIR Vengeance LPX 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 3600 (PC4 28800) Desktop Memory Model CMK32GX4M2Z3600C20. This is stable for me right now







Let me know if I forgot anything you need to help me out.


----------



## Esticbo

DroidGeek69 said:


> Ok I will start with I am total noob. Never tweaked my computer before. I did phone roms back in Droid 2 era. I think I can run fast with both CPU and memory but haven't figure the magic numbers yet. I have Windows 10 2004 and Asus PRIME B350-PLUS with Version 5602 bios and I am running a AMD Ryzen™ 7 1700 with CORSAIR Vengeance LPX 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 3600 (PC4 28800) Desktop Memory Model CMK32GX4M2Z3600C20. This is stable for me right now
> View attachment 2464314
> Let me know if I forgot anything you need to help me out.


You can start to enter in the bios / advance and enable docp then set memory clock to 3000


----------



## KedarWolf

Old memory testing program, still really good. HCI MemTest Pro. It has found errors for peeps even TM5 has missed.

I also have AutoHotKey scripts that open say 32 instances for a 3950x or 5950x and allocate each instance to a single separate thread, the absolute best way to run HCI.

Like first HCI running only on core 1, second only on core 2, third only on core 3 etc.

Let me know if anyone needs the AHK scripts. I have it for 32 threads but I think I need to configure it for 24 threads and 16 threads etc. for other AMD CPUs.


----------



## jelome1989

Hi all, I went from 250% to 600% coverage at HCI Memtest with a 50mhz difference (for each CCX) between the two. Does this mean that I found the right clocks for the current voltage? I have a 3900x. Also just noticed that there's a 1GB+ free system RAM during the test. For some reason, after running the test, my system managed to free 1GB of RAM (4gb used by system before testing accdg to Task Manager). Would this be OK?

Now going to move to other tests when I reach 1000%, hopefully. What's the gold standard for linpack extreme, y-cruncher? Also any recommendation for other stress testing program and their golden standards?


----------



## Martin778

The X570 Tomahawk is an amazing board, give it some highly binned B-Die and it flies:


----------



## rares495

Martin778 said:


> The X570 Tomahawk is an amazing board, give it some highly binned B-Die and it flies:
> View attachment 2464987


Very nice result.


----------



## jelome1989

jelome1989 said:


> Hi all, I went from 250% to 600% coverage at HCI Memtest with a 50mhz difference (for each CCX) between the two. Does this mean that I found the right clocks for the current voltage? I have a 3900x. Also just noticed that there's a 1GB+ free system RAM during the test. For some reason, after running the test, my system managed to free 1GB of RAM (4gb used by system before testing accdg to Task Manager). Would this be OK?
> 
> Now going to move to other tests when I reach 1000%, hopefully. What's the gold standard for linpack extreme, y-cruncher? Also any recommendation for other stress testing program and their golden standards?


Update: Got to 1000%. For the RAM timings and voltages, I just copied 1usmus DRAM Calc settings at 3200-Fast-BDie-A3/A2/B2 









I actually tested this with a CPU underclock, I wanted to find out the best clocks my CPU can do at 1.1v. Using 1usmus CTR tool, I got:
CCX1 - 3975
CCX2 - 3975
CCX3 - 3875
CCX4 - 3850

But this isn't stable, I got errors in a few minutes at linpack extreme. So I downclocked a bit and retested with HCI MemTest

For the 250% coverage:
CCX1 - 3900
CCX2 - 3875
CCX3 - 3800
CCX4 - 3725

For the 1000% coverage: 
CCX1 - 3850
CCX2 - 3825
CCX3 - 3750
CCX4 - 3675

So, does this mean I found the right clocks at 1.1v for my CPU? Also it seems my CPU is not a good clocker, no? Will test with other programs, or maybe try upping to 3600 RAM


----------



## Yviena

Martin778 said:


> The X570 Tomahawk is an amazing board, give it some highly binned B-Die and it flies:
> View attachment 2464987


What ram is that DR, or 4x8SR? A1, or A2?

I have the same board with 4xSR 3200CL14 sticks can't go tighter than 3733CL16 though at 1.48v, CPU also can't do 1900 FCLK.


----------



## Martin778

4x8GB 3800C14, SR, A2 (May 2020 production).
My 3200C14 Royals wouldn't do it either, 3733 C15 was the best they'd do.
This setup passed a few runs of TM5 with 1usmus's v3 config, no issues.

U wot m8s? This is absolutely bonkers, 4x8GB, 4000 CL14 Pass...


http://imgur.com/m6I61EF




http://imgur.com/o9hnDTh


----------



## dgoc18

Martin778 said:


> The X570 Tomahawk is an amazing board, give it some highly binned B-Die and it flies:
> View attachment 2464987


 can you run zentimings screenshot post here, by the way your awesome 53 latency.


----------



## mirzet1976

Is that normal speed for L3 cache


----------



## Dasa

102BCLK wont post but 101 seems ok.
Managed to get under 53ns at 1885IF but unable to post with 1900IF
Tried to up all the v as suggested by the DRAM calc but it made no difference.
Still trying to get it stable somewhere near this.


----------



## Gadfly

Has anyone had any luck running 4x8GB @ 4000 MT/s?


----------



## Martin778

Yes, please see my post above. G.Skill F4-3800C14Q-32GTZN.


----------



## Gadfly

Martin778 said:


> Yes, please see my post above. G.Skill F4-3800C14Q-32GTZN.


I have the same kit, having trouble getting 4x8gb to post over 3866.

Can you post a zentimings SS?

Thanks in advance!


----------



## ZealotKi11er

Just got 4000 CL19 kit, Oct 2020 production. 2000 could not boot. 3800 cl16-16-16 no issues.


----------



## vmanuelgm




----------



## vmanuelgm




----------



## kazablanka

5800x + f4-3600c16d


















At 4066mhz the latency is under 50ns but it needs more testing for stability .


----------



## fit949

Any fellow member have any recommendations for improving my timings.


----------



## Yviena

Hmm I wonder if it would be better to leave IF at 3800/3733 instead of chasing 4000 as the SoC IO core would steal power from the cores on all core loads.


----------



## nick name

Yviena said:


> Hmm I wonder if it would be better to leave IF at 3800/3733 instead of chasing 4000 as the SoC IO core would steal power from the cores on all core loads.


I guess that would boil down to how you're running your CPU. Whether you're using PBO, all-core OC, or the new Dark DOS feature.


----------



## Dasa

Managed to get 3800 1:1 to boot with 5800x
Trick was mostly rtt-wr 3 vs off
and lowering rrt-park to 2 vs 5 with each step lower getting further in hci memtest at 1885if
Checking for stability now and will continue to fine tune.


----------



## tandlion13

Hi, I'm running Ryzen 5 3600 and 2x8GB DDR4 on a B550 motherboard.
I managed to get DDR4-3600 CL16 with tuned timings to pass the 4 passes of memtest86 with no error.
But the system shows some weird behaviors while playing games.
Many crashes and got BSOD once with memory related errors.

The CPU is also overclocked to 4.4Ghz all core.
Although I've already validated the OC while running XMP (3200) I haven't done so with 1800 FCLK.

So do I need to increase the Vcore or lower the CPU OC to achieve stability?
The SOC voltage is set to 1.1V.
The motherboard is Asus TUF B550 Plus.
Tried different BIOS : 1004 / 1202 / 1212 all have the same issues.

By the way, is 1.435V DRAM Voltage good for long term use.
The kit is Team Delta TUF RGB 2x8GB DDR4-3200. Hynix CJR memory.


----------



## nexxusty

kazablanka said:


> 5800x + f4-3600c16d
> View attachment 2465184
> 
> 
> View attachment 2465185
> 
> 
> At 4066mhz the latency is under 50ns but it needs more testing for stability .


That write score is literally HALF of what it should be.

32gb/s? That's terrible, actually.


----------



## Dasa

nexxusty said:


> 32gb/s? That's terrible, actually.


It is excellent for a 5800X actually.
Any CPU 3800X\5800X and under get half the write speed of the 3900X\5900X and up.
Read\copy is a bit lower than what I am getting at a 3800 but that latency is great.


----------



## kazablanka

nexxusty said:


> That write score is literally HALF of what it should be.
> 
> 32gb/s? That's terrible, actually.


Amd has cut write bandwidth at half after zen+ for the one ccd cpus.


----------



## kazablanka

Dasa said:


> It is excellent for a 5800X actually.
> Any CPU 3800X\5800X and under get half the write speed of the 3900X\5900X and up.
> Read\copy is a bit lower than what I am getting at a 3800 but that latency is great.


What cpu do you have? Do you use the last aida version (it has lower score for copy now)


----------



## mongoled

Martin778 said:


> 4x8GB 3800C14, SR, A2 (May 2020 production).
> My 3200C14 Royals wouldn't do it either, 3733 C15 was the best they'd do.
> This setup passed a few runs of TM5 with 1usmus's v3 config, no issues.
> 
> U wot m8s? This is absolutely bonkers, 4x8GB, 4000 CL14 Pass...
> 
> 
> http://imgur.com/m6I61EF
> 
> 
> 
> 
> http://imgur.com/o9hnDTh


Well done! Nice to see peeps getting to 2000 MHz IF 1:1 tight timings

 


kazablanka said:


> 5800x + f4-3600c16d
> View attachment 2465184
> 
> 
> View attachment 2465185
> 
> 
> At 4066mhz the latency is under 50ns but it needs more testing for stability .


Kai esi, very nice, its a shame many of us are going to be late to this party, but im sure BIOS will be more mature by the time Ryzen 5000 stock shortages are fixed!

Beautiful latency

 



nexxusty said:


> That write score is literally HALF of what it should be.
> 
> 32gb/s? That's terrible, actually.


Dude, know what you talking about before you call something terrible

😄😄


----------



## billy1816

What do you guys think about this?
Any advice on how to lower L3 latency? I'm using the stock cooler, maybe throttle?


----------



## mongoled

billy1816 said:


> What do you guys think about this?
> Any advice on how to lower L3 latency? I'm using the stock cooler, maybe throttle?


Wait for a new BIOS.

Something is not working right at all.

I dont think you should waste your time attempting to improve that as something is seriously amiss.

Its not just the L3 cache results its also your 60ms memory latency and also your memory read will never be that high.

That AIDA64 is just all wrong .....


----------



## billy1816

mongoled said:


> Wait for a new BIOS.
> 
> Something is not working right at all.
> 
> I dont think you should waste your time attempting to improve that as something is seriously amiss.
> 
> Its not just the L3 cache results its also your 60ms memory latency and also your memory read will never be that high.
> 
> That AIDA64 is just all wrong .....


I don't know what can be wrong, memory is stable with testmem5 anta777 profile and cinebench scores are ok, SC 574 MC 4355. Maybe is just aida reading wrong the data? 
With BIOS default I still get super high L3 cache latency, so maybe you are right, I don't know...


----------



## Dasa

kazablanka said:


> What cpu do you have? Do you use the last aida version (it has lower score for copy now)


You are correct it was a old version of AIDA64 here is the new vs old.


----------



## fakestrawberryflavor

Is it possible for any kits to hit CL12 on a Zen 3/X570 platform? Curious to see the latency/performance of say 3200 12-12-12 vs 3800 14-14-14.


----------



## mongoled

Dasa said:


> You are correct it was a old version of AIDA64 here is the new vs old.
> View attachment 2465453


Good, you got to the bottom of it!

As you stated other things were working normally, just goes to show, new hardware often needs updated software.

The +68000 read was a real anomoly


----------



## rares495

fakestrawberryflavor said:


> Is it possible for any kits to hit CL12 on a Zen 3/X570 platform? Curious to see the latency/performance of say 3200 12-12-12 vs 3800 14-14-14.


Everything's possible once you throw enough voltage at the problem. I almost got 3800 11-11-11 to boot.


----------



## kazablanka

I need some good luck here


----------



## mongoled

kazablanka said:


> View attachment 2465496
> 
> 
> I need some good luck here


Forget about luck

 

Its all down to quality of parts, knowledge and how many volts you are willing to use


----------



## rares495

kazablanka said:


> I need some good luck here


I wouldn't go above 2000MHz FCLK if I were you.


----------



## kazablanka

rares495 said:


> I wouldn't go above 2000MHz FCLK if I were you.


Just trying to see what is the best I can do with my ram. I don't know yet if I will keep this settings for 24/7 

I am not even sure I'll stay at 4000mhz config


----------



## rares495

kazablanka said:


> Just trying to see what is best I can do with my ram. I don't know yet if I will keep this settings for 24/7


You better not.


----------



## billy1816

Well I actually was using an older AIDA64 version, so my new results look much better!


----------



## mongoled

rares495 said:


> You better not.


What is this ??

Do you know something nobody else knows ??

Is somethng bad going to happen to his hardware or something ??

I am hoping with newer more mature BIOS to see better results, if I had a 5000 series CPU I would be pushing for as much as I can get.

Personally I am interested in stable performance, but ofcourse would lke to see the limits of the hardware I am using.

Just dont understand why you are attempting to pursuade him from pushing his hardware, considering you push/have pushed many volts through your B-dies!

Please spill the beans if you know something.


----------



## rares495

mongoled said:


> What is this ??
> 
> Do you know something nobody else knows ??
> 
> Is somethng bad going to happen to his hardware or something ??
> 
> I am hoping with newer more mature BIOS to see better results, if I had a 5000 series CPU I would be pushing for as much as I can get.
> 
> Personally I am interested in stable performance, but ofcourse would lke to see the limits of the hardware I am using.
> 
> Just dont understand why you are attempting to pursuade him from pushing his hardware, considering you push/have pushed many volts through your B-dies!
> 
> Please spill the beans if you know something.


There is PCI-E 4.0 instability if you push FCLK over 2000. I'll test this myself on a 5950X tomorrow.


----------



## mongoled

OK, I know about that issue, happens with 3000 series also, we use VDDP to play around it, but you know this and it's not going to destroy your hardware. 

So he can experiment to his hearts content!


----------



## rares495

mongoled said:


> OK, I know about that issue, happens with 3000 series also, we use VDDP to play around it, but you know this and it's not going to destroy your hardware.
> 
> So he can experiment to his hearts content!


We don't know what it does since 2000 FCLK is a new thing. We couldn't test it with the 3000 series since no chip was able to hit 2000.


----------



## mongoled

Duh, obviously, it happens on 3000 series chips near 1900 mhz IF clocks....


----------



## rares495

mongoled said:


> Duh, obviously, it happens on 3000 series chips near 1900 mhz IF clocks....


I don't know about that. Never experienced it at "just" 1900. You must be thinking of something else.


----------



## elvior2

Hi @all,

I'm pretty new to this topic and also new to Ryzen platform but coming here for as a last chance before RMA, requesting some help that I would really apreciate for sure 

After following so many guidelines and reading so many posts about how to stabilice memory on Ryzen I can't make my system RAM to run fully stable. Many many days and weeks of testing.

Tried even at the lowest speed 2400mhz with all on Auto but it keeps firing some error in stress tests, sometimes just some minutes after the begining of the test and other times after hours wihout any error. On average same number of errors occurs at 2400 and other speeds like XMP 3200 or higher 3466.

These are the specs of the system:

MB: MSI B450M-MORTAR-MAX
CPU: Ryzen 5 3600
RAM: HX432C16FB3AK2/32 (Kingston HyperX Fury RGB DDR4 3200Mhz PC-25600 32GB 2x16GB CL16)
Notice that memory is supported in the QVL of the MB at rated speeds.

I'm doing the testing using: LinpackXtreme-1.1.3, TestMem5 v0.12 (best configs) using [email protected], Prime95 Small FFT, Large, Blend Custom, Memtest...

So far the most stable configuration with least number of errors is this one:
























































The errors that appears in TestMem5 v0.12 (best configs) using [email protected]:











Any help will be really appreciated. Let me know if you need to add more details about any configuration or something.

Thank you!!!!


----------



## Dasa

Tried one stick at a time?
Are the sticks in slots 2-4 which are the second and fourth from the CPU?


----------



## Lion-Sherbert241

elvior2 said:


> Hi @all,
> 
> I'm pretty new to this topic and also new to Ryzen platform but coming here for as a last chance before RMA, requesting some help that I would really apreciate for sure
> 
> After following so many guidelines and reading so many posts about how to stabilice memory on Ryzen I can't make my system RAM to run fully stable. Many many days and weeks of testing.
> 
> Tried even at the lowest speed 2400mhz with all on Auto but it keeps firing some error in stress tests, sometimes just some minutes after the begining of the test and other times after hours wihout any error. On average same number of errors occurs at 2400 and other speeds like XMP 3200 or higher 3466.
> 
> These are the specs of the system:
> 
> MB: MSI B450M-MORTAR-MAX
> CPU: Ryzen 5 3600
> RAM: HX432C16FB3AK2/32 (Kingston HyperX Fury RGB DDR4 3200Mhz PC-25600 32GB 2x16GB CL16)
> Notice that memory is supported in the QVL of the MB at rated speeds.
> 
> I'm doing the testing using: LinpackXtreme-1.1.3, TestMem5 v0.12 (best configs) using [email protected], Prime95 Small FFT, Large, Blend Custom, Memtest...
> 
> So far the most stable configuration with least number of errors is this one:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> The errors that appears in TestMem5 v0.12 (best configs) using [email protected]:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Any help will be really appreciated. Let me know if you need to add more details about any configuration or something.
> 
> Thank you!!!!



Bro, lower your CPU LLC (load line calibration) to 3 or more (or just Auto). LLC of 1 is dangerous, it has 0 Vdroop and can cause voltage upshoot even at high loads.

For the DDR4 memory controller it's the "CPU NB Loadline Calibration Control", which is the 2nd one. That's the northbridge/IMC LLC. Set it to 2 or 3. 

Check what RAM chips you're using as well, i.e. Samsung B, Micron E, Samsung C, or Hynix. You can use Thaiphoon Burner to determine what your RAM chips are.


----------



## elvior2

Thanks for the prompt answers!



Dasa said:


> Tried one stick at a time?
> Are the sticks in slots 2-4 which are the second and fourth from the CPU?


Yes, the ram modules are installed in 2 and 4 slots as recommended in the motherboard documentation.

Also tested isolated in single channel and they seem to be working without issues.

@Lion-Sherbert241 ok, I'll do the changes in LLC to be safe, but I have tested with different configurations of LLC and that doesn't seem to improve stability in this case.

About the RAM chips these are Hynix CJR, see image attached. I made the configuration using DRAM Calculator and following guidelines.









More things to test / check?


----------



## Lion-Sherbert241

elvior2 said:


> Thanks for the prompt answers!
> 
> 
> 
> Yes, the ram modules are installed in 2 and 4 slots as recommended in the motherboard documentation.
> 
> Also tested isolated in single channel and they seem to be working without issues.
> 
> @Lion-Sherbert241 ok, I'll do the changes in LLC to be safe, but I have tested with different configurations of LLC and that doesn't seem to improve stability in this case.
> 
> About the RAM chips these are Hynix CJR, see image attached. I made the configuration using DRAM Calculator and following guidelines.
> 
> View attachment 2465632
> 
> More things to test / check?


Regarding LLC.... LLC normally (2 and above) is supposed to “catch” the voltage drop when under load and bring it back to the dialed in voltage, but LLC Mode 1 goes beyond that and it pushes the voltage up some more.

Try upping the NB SoC voltage from 1.05 —> 1.1 volts. To rule out whether it’s the memory controller. Try forcing Command Rate to “Gear Down Mode” / “2T”. Hynix is more stable at 2T or GDM

Still it’s so strange as to why even at JEDEC-2400 spd default/non-overclocked it still isn’t stable and gives errors. If still unstable, try if another kit of ram works flawlessly then continue the RMA process for that Kingston kit.


----------



## Esticbo

I'm very Happy with my new system. My ram have Samsung C-Die


----------



## PowerK

What's the most popular (reliable) memory stability test these days?
Do you still use GSAT? I used GSAT and HCI Memtest. If I had to pick one, GSAT seems to be the best.


----------



## Dasa

Out of the free benchmarks GSAT is ok for finding RAM errors but HCI is the best I know of for memory controller errors.
HCI is bundled into Ryzen DRAM calc which makes it much easier to launch multiple instances at once.


----------



## jomama22

Any advise on getting gdm disables on 5950x @3800 and above? Not sure what drvstr and other setting to be shooting for. Thanks!


----------



## mongoled

Finally, after upgrading motherboard and receiving working parts I can publish new results

Stability testing
Prime95 Large FFTs - 2 hours
RealBench - 2 hours
Y-Cruncher - 3+ hours
TM5 - 25 Cycles

Memory Used (set to 1.53v in BIOS)
2 x 8GB Viper Steel 4000 mhz (Slots A1/B1)
2 x 8GB Viper Steel 4400 mhz (Slots A2/B2)

3800/1900, BCLK 107.60 mhz, EDC @2

This is stable for me


----------



## elvior2

Lion-Sherbert241 said:


> Regarding LLC.... LLC normally (2 and above) is supposed to “catch” the voltage drop when under load and bring it back to the dialed in voltage, but LLC Mode 1 goes beyond that and it pushes the voltage up some more.
> 
> Try upping the NB SoC voltage from 1.05 —> 1.1 volts. To rule out whether it’s the memory controller. Try forcing Command Rate to “Gear Down Mode” / “2T”. Hynix is more stable at 2T or GDM
> 
> Still it’s so strange as to why even at JEDEC-2400 spd default/non-overclocked it still isn’t stable and gives errors. If still unstable, try if another kit of ram works flawlessly then continue the RMA process for that Kingston kit.


I've made the changes one by one and then testing whole nigth and day.

These are the findings:

You were rigth about LLC, now setting for CPU has LLC Mode 2 and for NB/SoC LLC is Mode 3.
Upping the NB SoC from 1.05 to 1.1 doesn't seem to help. On the contrary I think it make it worse as the stress testing fails more quickly.
Changing Command Rate to 2T doesn't seem to work also. It's already running in “Gear Down Mode” from what I see in ZenTimings.
Changing CAD_BUS Block to following values seems to make the RAM more stable

ClkDvrStr: 40
AddrCmdDvrStr: 30
CsOdtDvrStr: 30
CkeDvrStr: 30
These make me pass:

LinpackXtreme-1.1.3: 25 cycles
TestMem5 v0.12 (best configs) using [email protected]: 8 cycles (arround 8h)
Prime95 Small FFT: 2h for ensuring CPU is stable
But Prime Large FFT (512-4096) and MemTest DRAM Calculator seems to have strange behaviour.

Each of those either it fails in a couple of minutes just after starting or it can stay running for hours without reporting any error.

So I'm totally lost on that side.

These are the current settings:










Any advice or setting to check or try?


----------



## kim nk

5600X PBO +200
ASUS ROG VIII X570 IMPACT
CL16 4400 (XMP) 8x2 ROYAL








































4700





























개선 할 시간을 알려주세요. 4200 cl14를 안정화하는 방법을 찾고 있습니다.


----------



## nick name

kim nk said:


> 5600x
> ASUS ROG VIII X570 IMPACT
> CL16 4400 (XMP) 8x2 ROYAL
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2465765
> 
> View attachment 2465767
> 
> 
> View attachment 2465766
> 
> 
> 
> View attachment 2465764
> 
> View attachment 2465768
> 
> 
> 
> View attachment 2465769
> 
> 
> View attachment 2465770
> 
> 
> 
> Please tell me the timimg to improve . and i`m looking for a way to stabilize the 4200 cl14


Have you tried increasing tRDWR? I'm not entirely certain there is a benefit to it being that low. And GDM might be needed if voltage isn't getting the job done.


----------



## adversary

*kim nk*

Hell nice latency even on 3800 Mhz.

What I heard (I still waiting for parts and have no direct AMD expirience) is that FLCK above 2000 or even 1966 may cause other issues. You may try 3933 or 4000, but with even lower timings to get/keep better latency.
Sure there is members who know much about tweaking of Zen timings so I'm sure they will help you with it.

Nice result anyway


----------



## mongoled

kim nk said:


> 5600X PBO +200
> ASUS ROG VIII X570 IMPACT
> CL16 4400 (XMP) 8x2 ROYAL
> 
> 
> View attachment 2465765
> 
> View attachment 2465767
> 
> 
> View attachment 2465766
> 
> 
> 
> View attachment 2465764
> 
> 
> 
> 
> 4700
> View attachment 2465768
> 
> 
> 
> View attachment 2465769
> 
> 
> View attachment 2465770
> 
> 
> 
> 개선 할 시간을 알려주세요. 4200 cl14를 안정화하는 방법을 찾고 있습니다.


Very nice and thanks for joining the forum to show us these.

Welcome, welcome



Funny thing,

Im testing 14-14-14-14-28-42 3800/1900 on my 3600 with the 2x8GB Viper Steels 4000 and 2x8GB Viper Steels 4400 and TM5 is almost one hour in with no errors !!

This is a first for me

The BIOS I am using on the Unify is the modified A42 version with Agesa 1.0.0.5.

Cant wait to get a 5000 series CPU and see what it does with this combo of RAM

 

** EDIT **
Completed TM5 25 cycles straight 14s


----------



## kim nk

[QUOTE = "kim nk, 게시물 : 28673100, 회원 : 641452"]
SUS ROG VIII X570 IMPACT
[/ 인용문]


nick name said:


> Have you tried increasing tRDWR? I'm not entirely certain there is a benefit to it being that low. And GDM might be needed if voltage isn't getting the job done.


yes, i tried to in crease it, but i released trcdrd and increased trdwr, but even cl 14 16 16 16 trdwr 8~10 timing errors occurred.


----------



## kim nk

[QUOTE = "kim nk, 게시물 : 28673100, 회원 : 641452"]
SUS ROG VIII X570 IMPACT
[/ 인용문]


adversary said:


> *kim nk*
> 
> Hell nice latency even on 3800 Mhz.
> 
> What I heard (I still waiting for parts and have no direct AMD expirience) is that FLCK above 2000 or even 1966 may cause other issues. You may try 3933 or 4000, but with even lower timings to get/keep better latency.
> Sure there is members who know much about tweaking of Zen timings so I'm sure they will help you with it.
> 
> Nice result anyway


I don`t speak english , so I read with a translator and write with a translation
I`ll learn a lot. Thank you~!


----------



## kim nk

[QUOTE = "kim nk, 게시물 : 28673100, 회원 : 641452"]
SUS ROG VIII X570 IMPACT


3800 CL 1314 13 21 40 GDM 비활성화 CR-1T 1.55V

[/ 인용문]









TM5 ADV5 40Cycles If it fails, try timing again
13-8-14-14-22-40or42 trdwr 7
What do you think if you do this?


----------



## KedarWolf

mongoled said:


> Im testing 14-14-14-14-28-42 3800/1900 on my 3600 with the 2x8GB Viper Steels 4000 and 2x8GB Viper Steels 4400 and TM5 is almost one hour in with no errors !!
> 
> 
> 
> Spoiler
> 
> 
> 
> This is a first for me
> 
> The BIOS I am using on the Unify is the modified A42 version with Agesa 1.0.0.5.
> 
> Cant wait to get a 5000 series CPU and see what it does with this combo of RAM
> 
> 
> 
> ** EDIT **
> Completed TM5 25 cycles straight 14s
> 
> 
> 
> View attachment 2465783


Yes, that's the unlocked BIOS I use on my 3950x. The 1.0.0.5 one I get CL14 with 2x16GB on it, highly recommend if not using a 5000 series CPU.


----------



## Dasa

elvior2 said:


> Any advice or setting to check or try?


Nice progress.
My Samsung b die likes RTNom RZQ/7 Not sure if Hynix C die will but it could be worth a try.


----------



## jomama22

Any tips on getting gdm disables @3800+? Not sure what drive strengths to be changing or voltages.


----------



## Lion-Sherbert241

elvior2 said:


> I've made the changes one by one and then testing whole nigth and day.
> 
> These are the findings:
> 
> You were rigth about LLC, now setting for CPU has LLC Mode 2 and for NB/SoC LLC is Mode 3.
> Upping the NB SoC from 1.05 to 1.1 doesn't seem to help. On the contrary I think it make it worse as the stress testing fails more quickly.
> Changing Command Rate to 2T doesn't seem to work also. It's already running in “Gear Down Mode” from what I see in ZenTimings.
> Changing CAD_BUS Block to following values seems to make the RAM more stable
> 
> ClkDvrStr: 40
> AddrCmdDvrStr: 30
> CsOdtDvrStr: 30
> CkeDvrStr: 30
> These make me pass:
> 
> LinpackXtreme-1.1.3: 25 cycles
> TestMem5 v0.12 (best configs) using [email protected]: 8 cycles (arround 8h)
> Prime95 Small FFT: 2h for ensuring CPU is stable
> But Prime Large FFT (512-4096) and MemTest DRAM Calculator seems to have strange behaviour.
> 
> Each of those either it fails in a couple of minutes just after starting or it can stay running for hours without reporting any error.
> 
> So I'm totally lost on that side.
> 
> These are the current settings:
> 
> View attachment 2465763
> 
> 
> Any advice or setting to check or try?


Wow you've managed to even OC to 3466 now. Great job there. 

Keep your vsoc at 1.05 if it crashes at 1.1.
I suggest checking whether lower procODT values give you better stability, since it remains unchanged at 48 now. Different RAM reacts differently, mine finds itself stable at 36.9-40ohm procODT. ProcODT first then CAD DrvStr (mine is stable at 30 20 20 20). 
Stabilizing RAM is tedious due to too many confounding variables to experiment with. Good luck bro


----------



## Veii

@kim nk very good results !
I have to warn you on one part
Vermeer didn't change when it comes to voltage spreading (inspection in progress)
You maybe run SOC of 1.2v if cLDO_VDDG IOD is 1.15v
Both VDDGs come from one SOC line - unless something changed, it can not be lower than SOC and AMD will push it's 50Mhz stepping on it

I need to doublecheck how this is, but a little warning so you know
IOD beyond 1.15v is already damaging

Can you confirm stability on this set for me, please ?


Spoiler: 14-10-14-12














I think you can go SCL 2
Confirm stability without GDM if you can
BGS you can ignore 

Another set you can try:








tRDWR can go down to 7. If you face "mirror move" issues on TM5 - remove tWRRD delay and set it as 1
If you want to go even lower, tCWL 10 with tRDWR 10, tWRRD 1 
Please try if this sample set works bellow 1.55v

For speeds beyond 4000MT/s , increase tRRD_L to 5 & tWTR_L to 10 & tRTP 8
For voltage compensation , running lower voltage should work with tWTR_L 12 + tCWL 14 & tRDWR 7 & tRTP 8


----------



## kim nk

[QUOTE = "Veii, 게시 : 28673465, 회원 : 609138"]
[USER = 641452] [USER = 641452] @kim nk [/ USER] [/ USER] 아주 좋은 결과입니다!
한 부분에 대해 경고해야합니다.
Vermeer는 발견과 관련하여 변경되지 않았습니다 (검사 진행 중).
cLDO_VDDG IOD가 1.15v이면 1.2v의 SOC를 사용할 수 있습니다.
두 VDDG는 하나의 SOC 라인에서 나옵니다. 변경하지 않는 한 SOC보다 낮을 수 없습니다 AMD는 50Mhz를 밟습니다.

이게 어떤지 다시 확인해야하는 약간의 경고가 다시 확인
1.15v 이상의 IOD는 이미 손상을 입었습니다.

이 세트의 안정성을 확인해 주시겠습니까?
[스포일러 = "14-10-14-12"]







[/ 스포일러]
SCL 2 갈 수있을 것 같아요
가능한 경우 GDM없이 안정성 확인
무시할 수있는 BGS 

시도해 볼 수있는 또 다른 세트 :








tRDWR은 7까지 내려갈 수 있습니다. TM5에서 "미러 이동"문제가 발생하면 tWRRD 지연을 제거하고 1로 설정합니다.
더 낮추고 페이지 tRDWR 10, tWRRD 1로 tCWL 10 
이 샘플 세트가 1.55v 이하로 작동하는지 시도하십시오.

4000MT / s 이상의 속도의 경우 tRRD_L을 5로, tWTR_L을 10 및 tRTP 8로 늘립니다.
보상의 경우, 저 필요 실행은 tWTR_L 12 + tCWL 14 & tRDWR 7 & tRTP 8에서 작동해야합니다.
[/ 인용문]
[QUOTE = "Veii, 게시 : 28673465, 회원 : 609138"]
[USER = 641452] @kim nk [/ USER] 아주 좋은 결과입니다!
한 부분에 대해 경고해야합니다
Vermeer는 전압 확산과 관련하여 변경되지 않았습니다 (검사 진행 중).
cLDO_VDDG IOD가 1.15v이면 1.2v의 SOC를 실행할 수 있습니다.
두 VDDG는 하나의 SOC 라인에서 나옵니다. 변경되지 않는 한 SOC보다 낮을 수 없으며 AMD는 50Mhz를 밟습니다.

이게 어떤지 다시 한번 확인해야하는데 약간의 경고가 있으니
1.15v 이상의 IOD는 이미 손상을 입었습니다.

이 세트의 안정성을 확인해 주시겠습니까?
[SPOILER = "14-10-14-12"]







[/ SPOILER]
SCL 2 갈 수있을 것 같아요
가능한 경우 GDM없이 안정성 확인
무시할 수있는 BGS 

시도해 볼 수있는 또 다른 세트 :








tRDWR은 7까지 내려갈 수 있습니다. TM5에서 "미러 이동"문제가 발생하면 tWRRD 지연을 제거하고 1로 설정합니다.
더 낮추고 싶다면 tRDWR 10, tWRRD 1로 tCWL 10 
이 샘플 세트가 1.55v 이하로 작동하는지 시도하십시오.

4000MT / s 이상의 속도의 경우 tRRD_L을 5로, tWTR_L을 10 및 tRTP 8로 늘립니다.
전압 보상의 경우, 저전압 실행은 tWTR_L 12 + tCWL 14 & tRDWR 7 & tRTP 8에서 작동해야합니다.
[/인용문]










드램 전압 1.72v
매우 불안정 ... ㅜㅜ


bios 1.54v









11/19

TRCDRD 14 (X) - 15 












실용 CL 14 14 14 22 40 타이밍 1.47v
VDDP에 어떤 가치를 입력해야합니까? VDDG IOD CCD VSOC 지금?
또는 적절한 값을 원합니다 ㅜㅜ
현재 사용 된 값 = 자동

아래 결과에서 적절한 값을 찾고 있습니다.
vddp. vddg iod ccd. vsoc. 타이밍


----------



## mongoled

Very nice results



As vSOC is 1.100v

vDDG IOD 1.050v (-0.050v from vSOC)
vDDG CCD 1.000v (-0.050v from vDDG IOD)
vDDP 0.9000v



KedarWolf said:


> Yes, that's the unlocked BIOS I use on my 3950x. The 1.0.0.5 one I get CL14 with 2x16GB on it, highly recommend if not using a 5000 series CPU.


Its very nice,

I am now pushing futher with it, this BIOS with combo of hardware in sig is gift that keeps giving



Testing TM5 @14-14-14-12-26-38-2T-240


----------



## rares495

mongoled said:


> 2T


😢


----------



## mongoled

rares495 said:


> 😢


Well its 32GB, I didnt find anyone pushing 1T with GDM disabled on 3000 series with any sort of stress tests.

Im sure with a better pair of A0 sticks 1T is possible, as the first set of A0 (that inexplicitly died) could post and run stress test at 1T with GDM disabled.

The current set I have fails more time than not to even post with 1T GDM disabled and when it does Windows may load (sometimes blue screen) and when it does load I cannot run AIDA64 memtest without crashing.

I did try many different combos of settings, voltages and position of dimms to get a stable 1T boot GDM disabled but it is not happening so now I am concentrating on tightening what I have.

Its still very good compared with all other results.

For goodness sake I am running flat 14s TM5 stable @3800/1900.

Show me anybody else who has achieved this



Currently testing this


----------



## rares495

mongoled said:


> Well its 32GB, I didnt find anyone pushing 1T with GDM disabled on 3000 series with any sort of stress tests.
> 
> Im sure with a better pair of A0 sticks 1T is possible, as the first set of A0 (that inexplicitly died) could post and run stress test at 1T with GDM disabled.
> 
> The current set I have fails more time than not to even post with 1T GDM disabled and when it does Windows may load (sometimes blue screen) and when it does load I cannot run AIDA64 memtest without crashing.
> 
> I did try many different combos of settings, voltages and position of dimms to get a stable 1T boot GDM disabled but it is not happening so now I am concentrating on tightening what I have.
> 
> Its still very good compared with all other results.
> 
> For goodness sake I am running flat 14s TM5 stable @3800/1900.
> 
> Show me anybody else who has achieved this
> 
> 
> 
> Currently testing this


1T is possible on dual rank with GDM on. Then you have some sort of a 1.5T instead of 2T.


----------



## mongoled

rares495 said:


> 1T is possible on dual rank with GDM on. Then you have some sort of a 1.5T instead of 2T.


I didnt see any difference in throughput and latency is slightly worse with 1T GDM disabled, at least when testing with AIDA64

I never understood how to use Sisoft sandra to compare results ....


----------



## jomama22

mongoled said:


> Well its 32GB, I didnt find anyone pushing 1T with GDM disabled on 3000 series with any sort of stress tests.
> 
> Im sure with a better pair of A0 sticks 1T is possible, as the first set of A0 (that inexplicitly died) could post and run stress test at 1T with GDM disabled.
> 
> The current set I have fails more time than not to even post with 1T GDM disabled and when it does Windows may load (sometimes blue screen) and when it does load I cannot run AIDA64 memtest without crashing.
> 
> I did try many different combos of settings, voltages and position of dimms to get a stable 1T boot GDM disabled but it is not happening so now I am concentrating on tightening what I have.
> 
> Its still very good compared with all other results.
> 
> For goodness sake I am running flat 14s TM5 stable @3800/1900.
> 
> Show me anybody else who has achieved this
> 
> 
> 
> Currently testing this
> 
> ...


Here's mine.
Using 2x16gb of gskill F4-4266C17D-32GVKB @ 1.45v
5950x @ 4825 all core @ 1.31v
Can get 14 on tRCDRD @ 1.55v with no errors but this is my daily.
so 14-15-11-28
TM5 stable for 6 hours overnight


----------



## mongoled

jomama22 said:


> Here's mine.
> Using 2x16gb of gskill F4-4266C17D-32GVKB @ 1.45v
> 5950x @ 4825 all core @ 1.31v
> Can get 14 on tRCDRD @ 1.55v with no errors but this is my daily.
> so 14-15-11-28
> TM5 stable for 6 hours overnight
> View attachment 2465832


Nice results



Is that 1.55v in BIOS or in HWInfo64 ?

Both MSIs I have had (X570/X370) overvolt the dimms, if I set 1.53v in BIOS then HWInfo64 reports 1.55x volts.

Are your Drive Strength values from AUTO settings are have you played around with those ?

Ive toyed for the last several hours to get 1T working with GDM disabled but its a no go.

For me 2T is better than 1T GDM enabled, 1T GDM enabled does not give consistent results when testing in AIDA64.

Also 2T give lower time in 1usmus DRAM Calc MemBench "Easy" mode.

Though using 1T GDM disabled there is a big difference!

I managed to get a couple of runs out in "Easy" mode, these were both around 98 seconds and that was with it throwing 6/7 error windows. Using exact same settings but 2T gives me around 103 seconds (I was only able to achieve this by setting ClkDrvStr to 120 ohms, this allowed me to run AIDA64, Membench without bluescreening).

Im working on getting stable 14-8-14-12-26-38-247-2T, the low tRFC is proving a little problematic, im hoping I can get round fixing that with different drive strengths ….


----------



## jomama22

mongoled said:


> Nice results
> 
> 
> 
> Is that 1.55v in BIOS or in HWInfo64 ?
> 
> Both MSIs I have had (X570/X370) overvolt the dimms, if I set 1.53v in BIOS then HWInfo64 reports 1.55x volts.
> 
> Are your Drive Strength values from AUTO settings are have you played around with those ?
> 
> Ive toyed for the last several hours to get 1T working with GDM disabled but its a no go.
> 
> For me 2T is better than 1T GDM enabled, 1T GDM enabled does not give consistent results when testing in AIDA64.
> 
> Also 2T give lower time in 1usmus DRAM Calc MemBench "Easy" mode.
> 
> Though using 1T GDM disabled there is a big difference!
> 
> I managed to get a couple of runs out in "Easy" mode, these were both around 98 seconds and that was with it throwing 6/7 error windows. Using exact same settings but 2T gives me around 103 seconds (I was only able to achieve this by setting ClkDrvStr to 120 ohms, this allowed me to run AIDA64, Membench without bluescreening).
> 
> Im working on getting stable 14-8-14-12-26-38-247-2T, the low tRFC is proving a little problematic, im hoping I can get round fixing that with different drive strengths ….


Yeah, in bios its set to 1.43v set but get is 1.452v. same with 1.53v1.552v. I noticed this as well when I was testing stuff.

I had asked a few times what people were doing to try and get gdm disabled as im having trouble posting at all with it disabled.

I haven't tried using 2t by itself, ill give it a shot and see what it does for me.

The drive strengths are straight auto and thats what they spit out. I haven't really messed with them yet except for when trying to get gdm disabled. Was more concerned with getting a nice baseline before starting to really dig into those as im not well versed on their affects on everything else atm.

Most of these settings were either post or no post, and when they posted, 99% of them they wouldn't get any errors on quick 20 min runs of tm5 using the extreme 1 a777 config. Once I had them all set, then I ran the 6 hour bench to solidify them.


----------



## mongoled

jomama22 said:


> Yeah, in bios its set to 1.43v set but get is 1.452v. same with 1.53v1.552v. I noticed this as well when I was testing stuff.
> 
> I had asked a few times what people were doing to try and get gdm disabled as im having trouble posting at all with it disabled.
> 
> I haven't tried using 2t by itself, ill give it a shot and see what it does for me.
> 
> The drive strengths are straight auto and thats what they spit out. I haven't really messed with them yet except for when trying to get gdm disabled. Was more concerned with getting a nice baseline before starting to really dig into those as im not well versed on their affects on everything else atm.
> 
> Most of these settings were either post or no post, and when they posted, they wouldn't get any errors on quick 20 min runs of tm5 using the extreme 1 a777 config. Once I had them all set, then I ran the 6 hour bench to solidify them.


Re GDM, I think most people dont have the patience in trying to troubleshoot getting it stable with GDM off and I can understand why!

Its only useful for posting "nice numbers" or benchmarking, for everything else it makes very little difference.

I like tweaking as a hobby, I dont participate in any benching, but do like the cutting edge numbers.

If you really want to go down the path of GDM disabled I think its all in the quality of your dimms, you can only do so much with drive strength and ODT.

I tried relaxing timings etc, increasing/decreasing voltages, it made no difference, the only thing that brought some stabiltiy was ClkDrvStr set to 120 ohms....

Re AUTO drive strength settings, only reason I asked is that my hardware combo default to 24-20-24-24


----------



## kim nk

TRCDRD14 . TRFC 228 --- X

TRCDRD15 TRFC 228 ---- ㅇ




















VDDG IOD 1.050 CCD 1.000 CLDO_VDDP 900 SOC 1.1

Very very THANK YOU ~~


----------



## qwrty

No chance I can go higher with FCLK right now :/
So I tightened timing.

4*8GB @1.45v



What you guys do you think ?


----------



## elvior2

Coming back @Lion-Sherbert241 and @Dasa with some new results and findings.

I've tried many things that you suggested one each time and for the time being the most stable setting I've found so far is this one:










With SoC: 1.05v, DRAM 1.36v, other voltages on Auto.

These make me pass:

LinpackXtreme-1.1.3: 25 cycles
Prime95 Small FFT: 2h
Prime95 Blend 6h
OCCT 1h
Memtest in Dram Calculator 350% coverage around 3h-4h
But still having some fails in test:

TestMem5 v0.12 using [email protected]: 3 cycles










Just want to make system fully stable first and then maybe I can think in adjusting the subtimings following your advices.

I suspect current AUTO values like TRC 80, TRFC 607 are too high probably and maybe some other, but first things first which I think is finding 100% stable config.

Indeed I'm strugling a lot trying to make it fully stable.

*Anything more to check or test?*

I really apreciate your help and also it's a great learning for me, this is an amazing world for learning new things.


----------



## Dasa

Your VDDG IOD is too high. it should be at least 0.05v below SOC I think maybe sombody else can confirm.
Maybe try 1.1-1.125VSOC, 1-1.025 VDDG IOD and 1.4 VDIMM.

Tried gear down mode on vs off now your at this point?


----------



## elvior2

Dasa said:


> Your VDDG IOD is too high. it should be at least 0.05v below SOC I think maybe sombody else can confirm.
> Maybe try 1.1-1.125VSOC, 1-1.025 VDDG IOD and 1.4 VDIMM.
> 
> Tried gear down mode on vs off now your at this point?


I've tried yesterday with GDM Enabled but that gives me less stability than 2T and also it seems to have better latency in AIDA64 with 2T than with GDM enabled.

I've adjusted IOD / CCD to 1.000v as SOC is 1.050v. Going higher on SOC is not helping. 
Tried this several times and is giving me more troubles making tests to fail much quicker.

Also already tested different ProcODT, RTTNom, RTTWR,...and the most stable config by far is with the following settings.

With VDDG IOD / CCD voltage adjustments a little improvement, but still 1 error...I don't know how to get rid of that one arggggg, failing always in Test 2. *What does this mean?*
.










I've been trying to changing DrvStr 24/20/24/24 and many more combinations but the best result so far is in Auto 24/24/24/24.
Also I've tried with little VDDP adjustments like 920mv, 925mv, but no chance.

Maybe some timing is not correct? I've only adjusted manually primary timings and the other subtimings etc are on AUTO.

Don't know what more to try. Any ideas?


----------



## kazablanka




----------



## Esticbo

elvior2 said:


> I've tried yesterday with GDM Enabled but that gives me less stability than 2T and also it seems to have better latency in AIDA64 with 2T than with GDM enabled.
> 
> I've adjusted IOD / CCD to 1.000v as SOC is 1.050v. Going higher on SOC is not helping.
> Tried this several times and is giving me more troubles making tests to fail much quicker.
> 
> Also already tested different ProcODT, RTTNom, RTTWR,...and the most stable config by far is with the following settings.
> 
> With VDDG IOD / CCD voltage adjustments a little improvement, but still 1 error...I don't know how to get rid of that one arggggg, failing always in Test 2. *What does this mean?*
> .
> 
> View attachment 2466019
> 
> 
> I've been trying to changing DrvStr 24/20/24/24 and many more combinations but the best result so far is in Auto 24/24/24/24.
> Also I've tried with little VDDP adjustments like 920mv, 925mv, but no chance.
> 
> Maybe some timing is not correct? I've only adjusted manually primary timings and the other subtimings etc are on AUTO.
> 
> Don't know what more to try. Any ideas?


which die have your ram?

You can try with setting:


----------



## elvior2

Esticbo said:


> which die have your ram?
> 
> You can try with setting:


It's Hynix C-die. Using RttPark RZQ/5 my system won't even POST.


----------



## Esticbo

[/QUOTE]


elvior2 said:


> It's Hynix C-die. Using RttPark RZQ/5 my system won't even POST.


And with this timens don't work your ram? If the ram doesn't work correctly may be a cpu problem (the memory controller)


----------



## mongoled

kazablanka said:


> View attachment 2466022
> 
> 
> 
> View attachment 2466023


Very nice!


----------



## elvior2

And with this timens don't work your ram? If the ram doesn't work correctly may be a cpu problem (the memory controller)
[/QUOTE]

Wow I hope that's not the case as I haven't done any kind of overclocking.

Indeed I've undervolted it to 4.00 Ghz and 1.200v to have better temperatures and more than enough power for my daily gaming, browsing, stuff.

But if that can be the case how can I check it? I'm able to pass Prime 95 small ffts small tests without issues (4h).

Any other thing to try?


----------



## elvior2

And with this timens don't work your ram? If the ram doesn't work correctly may be a cpu problem (the memory controller)
[/QUOTE]

Wow I hope that's not the case as I haven't done any kind of overclocking.

Indeed I've undervolted it to 4.00 Ghz and 1.200v to have better temperatures and more than enough power for my daily gaming, browsing, stuff.

But if that can be the case how can I check it? I'm able to pass Prime 95 small ffts small tests without issues (4h).

Any other thing to try?


----------



## Esticbo

elvior2 said:


> Wow I hope that's not the case as I haven't done any kind of overclocking.


It isn't a overclocking problem, but a hardware limit. You are using 32 GB.




elvior2 said:


> But if that can be the case how can I check it? I'm able to pass Prime 95 small ffts small tests without issues (4h).
> 
> Any other thing to try?


I prefer play to a game, before using prime 95 to test the stability of my pc


----------



## algida79

Hello friends!

Anyone having experience with Dual Rank 2x16GB Micron Rev.E on Zen+ that can share any ideas on what to try to push for the next speed strap (3533MT/s) on my system?

This is how far I was able to tune them at 3466MT/s with 1.35V Vdimm:


Spoiler: 3466MT/s maxed out timings















I am quite happy with the stability so far; while gradually tightening each timing, the PC was passing many successive overnight TM5 tests and 4h-long P95 1-8K FFT runs, always making sure to cold-boot every time after applying a new setting. Proof here:


Spoiler: 3466MT/s gradual tightening tests












s7_12_tm5_40cycles_pass.png







drive.google.com












s7_13_tm5_40cycles_pass.png







drive.google.com












s7_14_tm5_25cycles_pass.png







drive.google.com












s7_15_tm5_40cycles_pass.png







drive.google.com












s7_17_tm5_40cycles_pass.png







drive.google.com












s7_18_tm5_40cycles_pass.png







drive.google.com












s7_19_tm5_25cycles_pass.png







drive.google.com












s7_20_tm5_25cycles_pass.png







drive.google.com












s7_21_tm5_25cycles_pass.png







drive.google.com












s7_22_tm5_25cycles_pass.png







drive.google.com












s7_23_tm5_25cycles_pass.png







drive.google.com












s7_24_tm5_40cycles_pass.png







drive.google.com












s7_25_tm5_40cycles_pass.png







drive.google.com












s7_26_tm5_40cycles_pass.png







drive.google.com












s8_6_tm5_anta777_5cycles_pass.png







drive.google.com








After these successful results at 3466MT/s with these settings, I thought it a sensible approach to keep the same CLDO_VDDP, ProcODT, Rtt and CADBUS values as a baseline for 3533MT/s, moderately loosen the timings and just try to play with Vdimm and Vsoc as needed to achieve stability. Clearly this is not working; with 1.38V Vdimm I had these results:


Spoiler: 3533MT/s gradual tightening tests












s13_1_tm5_25cycles_pass.png







drive.google.com












s13_1_tm5_40cycles_pass.png







drive.google.com












s13_2_tm5_25cycles_pass.png







drive.google.com












s13_3_tm5_25cycles_pass.png







drive.google.com












s13_3_tm5_40cycles_fail.png







drive.google.com












s13_4_tm5_40cycles_fail.png







drive.google.com












s13_5_tm5_40cycles_fail.png







drive.google.com












s13_6_tm5_40cycles_fail.png







drive.google.com








Meanhwile, goofing around with friends on another forum I found out that the PC can POST up to 3866MT/s 1T GDM off, which please correct me if wrong but I believe is no mean feat for a Zen+ CPU driving 32GB of Dual Rank DIMMs:








kamikaze_aida64.png







drive.google.com




1.45V Vdimm, 1.1V Vsoc
but ofc it's not stable whatsoever 

What do you think is the issue here with the settings for 3533MT/s? Is it the CLDO_VDDP, ProcODT, Rtt, CADBUS values or something else? How would you proceed if you were me?

TIA


----------



## elvior2

Esticbo said:


> It isn't a overclocking problem, but a hardware limit. You are using 32 GB.
> 
> I hope that's not the issue as the motherboard support up to 128 GB, the ram kit that I bought is in the QVL of the motherboard in theory XMP should work.
> 
> I don't know we're the issue TBH. I don't know if it's the RAM or the CPU or both. I suspec
> 
> I prefer play to a game, before using prime 95 to test the stability of my pc


----------



## MikeS3000

I need some help explaining this issue. I have been running 2x8 gigabyte DJR ram at 3800 using dram calc fast and gdm disabled for about a year. I decided to upgrade and put two more sticks of the identical ram in my system 2 days ago. I entered the timings for dram calculator fast four sticks single rank. I even tried gdm off. It had no problem booting every time and it threw a couple errors on tm5 20 cycles. I decided to turn gdm on. It passes TM5 20 cycles and memtest 500%. Fast forward to today. Cold booting I had no issues. Every restart would lead to a blue screen and corrupted Windows files. I could not figure out what was going on. I got desperate and reinstalled windows. Finally I decided to enter dram calc settings and put in dual rank instead of single rank by four sticks. So far no issues. Was I supposed to select dual rank when using four single rank sticks for the purposes of the calculator?


----------



## elvior2

I'm starting to feel really really bored about my current memory ram kit and trully thinking of replacing it by a new set to see if I can get rid of all the instability issues and maybe get a bit better performance.

I'm thinking on replacing current kit https://www.kingston.com/dataSheets/HX432C16FB4AK2_32.pdf which is only causing me troubles by this other one F4-3200C14D-32GTZ-G.SKILL International Enterprise Co., Ltd.

Do you think it's worthy? What can I expect from that kit? Better clocks, better latency?


----------



## Dasa

elvior2 said:


> What can I expect from that kit?


Fully tweaked about 3733-4000c15-16 1.45-1.5v ~55ns provided your CPU\MB plays ball.

Just tried my 2x8GB 3200c14 kit out of 1:1 today and it topped out at 4400 with lose timings rather unstable but it seemed like it would be possible to get it stable around 4266 c16 1.48v
Bandwidth was much the same as 3800 1:1 so it seems like the IF is setting the bandwidth limit not the RAM frequency.
The latency was 6ns higher due to being out of 1:1 which is less of a hit than I expected.


----------



## elvior2

Dasa said:


> Fully tweaked about 3733-4000c15-16 1.45-1.5v ~55ns provided your CPU\MB plays ball.
> 
> Just tried my 2x8GB 3200c14 kit out of 1:1 today and it topped out at 4400 with lose timings rather unstable but it seemed like it would be possible to get it stable around 4266 c16 1.48v
> Bandwidth was much the same as 3800 1:1 so it seems like the IF is setting the bandwidth limit not the RAM frequency.
> The latency was 6ns higher due to being out of 1:1 which is less of a hit than I expected.


Well in my case my motherboard and cpu are budget ones:

Ryzen 5 3600 and MSI B450M Mortar Max, but I hope this kit will be much more stable than previous one and maybe with a bit more frecuency and better latencies.

I can't wait to try it!


----------



## qwrty

Do you guys have WHEAs errors on PCI/PCIe Bus errors reported by HWinfo64 after running AIDA memory stress test ONLY ?


----------



## elvior2

After so many many attemps with the hynix kit to run it stable (a month doing test, adjusting etc), it has been completely impossible to do so I've decided to bougth a new kit F4-3200C14D-32GTZ-G.SKILL International Enterprise Co., Ltd.

From the begining it seems like this kit is much more stable at least from what I've tried so far.

This is my current settings:

SoC: 1.050mv, DRAM: 1,39v



















Probably I can do a bit better? Any advice about adjusting or improving something?

Thanks in advance!


----------



## KedarWolf

Just a side note about stability, if your memory is the least bit unstable, you'll get game crashes on CoD Cold War and out and out BSODs on CoD Modern Warfare, the campaigns.

Even though I'm stable in TM5, the games won't run until I loosen my timings.

Not even sure how I can be TM5 stable, and games crashing or BSODing me.


----------



## nick name

KedarWolf said:


> Just a side note about stability, if your memory is the least bit unstable, you'll get game crashes on CoD Cold War and out and out BSODs on CoD Modern Warfare, the campaigns.
> 
> Even though I'm stable in TM5, the games won't run until I loosen my timings.
> 
> Not even sure how I can be TM5 stable, and games crashing or BSODing me.


I could always cure that with just a touch more DRAM voltage.


----------



## KedarWolf

nick name said:


> I could always cure that with just a touch more DRAM voltage.


I tried that, it helped with the game crashes, but then I'm not stable TM5 again.


----------



## Dasa

HWiNFO64 is reporting a few errors for me even at 3733 and a lot at 3800 even though HCI, TM5, Prime95 seem error free at both speeds.
I have not experienced any instability while gaming or in general use and benchmarks perform as they should.

My Samsung B die seems to get more errors in RAM stability tests once it goes over 1.5v despite running under 40c with a fan but at the same time it also becomes more benchmark stable at higher speeds if fed over 1.5v.


----------



## nick name

KedarWolf said:


> I tried that, it helped with the game crashes, but then I'm not stable TM5 again.


Then it's probably because your PSU is only 1600W. Lol I'm kidding of course. I wish I would have bought a more powerful PSU back when they were cheap.


----------



## KedarWolf

nick name said:


> Then it's probably because your PSU is only 1600W. Lol I'm kidding of course. I wish I would have bought a more powerful PSU back when they were cheap.


RAM is sensitive to which slots they are in. My 2x16GB I changed slots, same slots, just moved the DIMMs in the reverse order they were in (had moved them around when doing some motherboard stuff, wasn't sure if I had switched them), now I'm passing TM5 with a bit more voltage AND Modern Warfare and Cold War are not crashing. 

The lesson is peeps, move your sticks around, the order they are in the slots matter. Some test one DIMM at a time and put the best DIMM that overclocks with the best timings in the correct slot that is closer to the CPU. I never did that testing but have found switching them helps. 

They are still in slots A2 and B2 I mean, just moved the DIMMs in the reverse order they were in them.


----------



## PowerK

KedarWolf said:


> RAM is sensitive to which slots they are in. My 2x16GB I changed slots, same slots, just moved the DIMMs in the reverse order they were in (had moved them around when doing some motherboard stuff, wasn't sure if I had switched them), now I'm passing TM5 with a bit more voltage AND Modern Warfare and Cold War are not crashing.
> 
> The lesson is peeps, move your sticks around, the order they are in the slots matter. Some test one DIMM at a time and put the best DIMM that overclocks with the best timings in the correct slot that is closer to the CPU. I never did that testing but have found switching them helps.
> 
> They are still in slots A2 and B2 I mean, just moved the DIMMs in the reverse order they were in them.


The case is limited to daisy chained (RAM slot) motherboard. Because slots are daisy chained, slots show different characteristics.


----------



## mongoled

KedarWolf said:


> Just a side note about stability, if your memory is the least bit unstable, you'll get game crashes on CoD Cold War and out and out BSODs on CoD Modern Warfare, the campaigns.
> 
> Even though I'm stable in TM5, the games won't run until I loosen my timings.
> 
> Not even sure how I can be TM5 stable, and games crashing or BSODing me.


Because TM5 does not load the CPU as much as running something with Large FFTs does.

Yes I know you dont like the heat output, but you dont have to run Large FFTs for a long time, will usually root out instability within a couple of hours.

Looks like games will do it faster.

Re dimms and ram modules, I have my RAM modules numbered


----------



## herericc

KedarWolf said:


> RAM is sensitive to which slots they are in. My 2x16GB I changed slots, same slots, just moved the DIMMs in the reverse order they were in (had moved them around when doing some motherboard stuff, wasn't sure if I had switched them), now I'm passing TM5 with a bit more voltage AND Modern Warfare and Cold War are not crashing.
> 
> The lesson is peeps, move your sticks around, the order they are in the slots matter. Some test one DIMM at a time and put the best DIMM that overclocks with the best timings in the correct slot that is closer to the CPU. I never did that testing but have found switching them helps.
> 
> They are still in slots A2 and B2 I mean, just moved the DIMMs in the reverse order they were in them.


Firstly, congrats on your newfound stability!

I just wanted to mention though, if your DIMMs were already in slots A2 and B2, i doubt the order actually mattered - more than likely you had a bad insertion on one or both of the sticks, and re-seating them gave you a better connection to the ram socket. We test ICs at my job, and poor insertion is probably the main issue we are constantly dealing with. Extra resistance on a pin can and will totally throw off your signal integrity / strength.


----------



## SneakySloth

TM5 + a GPU load (at the same time) is what has helped me reach stability in everything. A GPU load could be AIDA64 or OCCT GPU stress tests. This should generate enough heat in the system to create a worst case scenerio for the memory.


----------



## elvior2

Continue tunning the F4-3200C14D-32GTZ-G.SKILL International Enterprise Co., Ltd.

Step by step, slowly. Current settings, stable so far.

SoC: 1.050mv, DRAM: 1,39v


















Any sugestion to improve it? Maybe changing something in primary timings?


----------



## mongoled

elvior2 said:


> Continue tunning the F4-3200C14D-32GTZ-G.SKILL International Enterprise Co., Ltd.
> 
> Step by step, slowly. Current settings, stable so far.
> 
> SoC: 1.050mv, DRAM: 1,39v
> View attachment 2466496
> 
> 
> View attachment 2466497
> 
> 
> Any sugestion to improve it? Maybe changing something in primary timings?


GDM off is not possible ??

You are better running 2T with GDM off, than 1T with GDM on.

See so many people doing this, 2T is better performance and more predicatable than 1T with GDM enabled.


----------



## Veii

elvior2 said:


> Continue tunning the F4-3200C14D-32GTZ-G.SKILL International Enterprise Co., Ltd.
> 
> Step by step, slowly. Current settings, stable so far.
> 
> SoC: 1.050mv, DRAM: 1,39v
> View attachment 2466496
> 
> 
> View attachment 2466497
> 
> 
> Any sugestion to improve it? Maybe changing something in primary timings?


tRRD_L to 7 , 8 is not balanced unless you push tWTR_L 16 (but this doesnt work on many boards)
tWR 16 tRFC 288-214-132
try this afterwards, if it's stable - use tWR 12
If it isn't stable tRFC 300-223-137 with tWR 12 ~ but first one should work if you trow VDIMM at it. 
288 = 154ns is not that low
Later work away SCL step by step. Up to PCB and setup, you can run SCL 2 at this freq

But GDM off 2T would be already progress
still try your luck above , down to SCL 4 down to tWR 12 ~ then with 2T work your primaries and tFAW away


----------



## Alyjen

Hi,

Any suggestions on improving this config? It's on 1.4V and I'm not sure if I want any higher. TM5 stable, OCCT (smal data set, sse) stable, game stable, also no random WHEA errors (which could happen even during TM5 test) with these settings.
I'd not like to go above 1.45V, so it's a matter of what can I get at 1.4V or improve by adding some voltage.

I tried to move tCWAL as DRAM calc suggests to 14 but it's instant BSOD 

Also about GDM, I tried to disable it, both 1T/2T and was not able to stabilize it, I think it requires to alter CAD_BUSes in a way I don't really understand now, and the config became super unstable, to the point it corrupted Windows within minutes.

Aida latency gives me around 54.x ns with this config.


----------



## elvior2

mongoled said:


> GDM off is not possible ??
> 
> You are better running 2T with GDM off, than 1T with GDM on.
> 
> See so many people doing this, 2T is better performance and more predicatable than 1T with GDM enabled.


Hi again!

I've just tried with GDM off and 2T but system seems to be a bit more unstable doing this and also not getting any improvement in latency.

BTW I've run a test overnight 75 cycles of TM5 and got 1 error arggggg....

I'm wondering now that maybe my VDDP, IOD, CCD have wrong values

In BIOS I have manually configured SoC to 1.050, seems to be the one that gives me better stability, but the others are on AUTO, so maybe they're wrong.

Can you mates give me advice about those ones???










Thank you!!!!


----------



## mongoled

elvior2 said:


> Hi again!
> 
> I've just tried with GDM off and 2T but system seems to be a bit more unstable doing this and also not getting any improvement in latency.
> 
> BTW I've run a test overnight 75 cycles of TM5 and got 1 error arggggg....
> 
> I'm wondering now that maybe my VDDP, IOD, CCD have wrong values
> 
> In BIOS I have manually configured SoC to 1.050, seems to be the one that gives me better stability, but the others are on AUTO, so maybe they're wrong.
> 
> Can you mates give me advice about those ones???
> 
> View attachment 2466690
> 
> 
> Thank you!!!!


Put DRAM to 1.45v (you can lower it later)

Before you have RttNom as 5, why you have this disabled ?

Set it to 7 or 5

Then for your 2 x 16GB you need at least vSOC of 1.0725v

Follow the below rule

If vSOC is 1.0725v
ProcODT 40 ohms

Then

vDDG IOD 1.025v (-0.050v from vSOC)
vDDG CCD 1.000v (-0.025v from vDDG IOD)
vDDP 0.9000v

Change

Cmd2T 2T
GDM Disabled
tRTP 7
tRFC 336
tRFC2 250
tRFC4 154
tRDWR 9
tRDRDSD 4
tWRWRSD 6

Hope this helps!


----------



## HamJeonghyeon

G.Skill 3200 CL14 8x4
5600x
ROG STRIX B550-XE GAMING WIFI . BIOS 1212
3080 GAMING OC

DRAM VOC 1.5


----------



## HamJeonghyeon

cancel


----------



## Veii

SMU 56.30 is love 
I have even BAR support
Never gonna install Patch C 
timings are still not serious ones, just to push FCLK


----------



## elvior2

mongoled said:


> Put DRAM to 1.45v (you can lower it later)
> 
> Before you have RttNom as 5, why you have this disabled ?
> 
> Set it to 7 or 5
> 
> Then for your 2 x 16GB you need at least vSOC of 1.0725v
> 
> Follow the below rule
> 
> If vSOC is 1.0725v
> ProcODT 40 ohms
> 
> Then
> 
> vDDG IOD 1.025v (-0.050v from vSOC)
> vDDG CCD 1.000v (-0.025v from vDDG IOD)
> vDDP 0.9000v
> 
> Change
> 
> Cmd2T 2T
> GDM Disabled
> tRTP 7
> tRFC 336
> tRFC2 250
> tRFC4 154
> tRDWR 9
> tRDRDSD 4
> tWRWRSD 6
> 
> Hope this helps!


Thank you so much for the tips.

For the time being this is the most stable configuration that I've achieved.

In BIOS

SoC: 1.0875V
cLDO_VDDP: 900mV
IOD: 1050mV
CCD: Auto
DRAM: 1.40v
LLC for CPU and NB: Mode 2










Don't know if it's worthy trying to reduce a bit more tRC, tRFC or it's fine like it is. Sugestions?

I've also tried decreasing primary timings but no chance and also going DDR3800, but it's unstable, so...


----------



## adversary

Veii said:


> SMU 56.30 is love
> I have even BAR support
> Never gonna install Patch C
> timings are still not serious ones, just to push FCLK




You get very good latency for 16-16-16 GDM on.

Usually what I see users get few ns worse latency compared to yours.

Is trick with all other properly tuned timings, or?  

What is about Patch C? It is now offered on most boards as I seen. Which one you use?


----------



## mongoled

elvior2 said:


> Thank you so much for the tips.
> 
> For the time being this is the most stable configuration that I've achieved.
> 
> In BIOS
> 
> SoC: 1.0875V
> cLDO_VDDP: 900mV
> IOD: 1050mV
> CCD: Auto
> DRAM: 1.40v
> LLC for CPU and NB: Mode 2
> 
> View attachment 2466885
> 
> 
> Don't know if it's worthy trying to reduce a bit more tRC, tRFC or it's fine like it is. Sugestions?
> 
> I've also tried decreasing primary timings but no chance and also going DDR3800, but it's unstable, so...


You need more vDIMM for higher frequency, tighter timings.

You still have not explained why you have RttNom disabled.

You need to increase ProcODT when you increase vSOC.

These things have been pointed out many times on these forums and to yourself in previous posts.

Personally I find it a little frustrating when posters seeking assistance comeback asking for more assistance when they are not following the assistance previously given.

It would be OK, if you contributed to the conversation people are having with you by acknowledging what they are asking you.

This comes across to me as a person who is always "give, give, give"


----------



## elvior2

mongoled said:


> You need more vDIMM for higher frequency, tighter timings.
> 
> You still have not explained why you have RttNom disabled.
> 
> You need to increase ProcODT when you increase vSOC.
> 
> These things have been pointed out many times on these forums and to yourself in previous posts.
> 
> Personally I find it a little frustrating when posters seeking assistance comeback asking for more assistance when they are not following the assistance previously given.
> 
> It would be OK, if you contributed to the conversation people are having with you by acknowledging what they are asking you.
> 
> This comes across to me as a person who is always "give, give, give"


I totally agree with what you're saying but trust me I'm not the kind of person of type "give, give, give". I'm so sorry if that was your impression.

I will try to answer now those questions.

This is my current settings:










*RttNom is disabled* because it was on AUTO on BIOS and given that now my system seems to be totally stable I thought I wouldn't need to fight with it...but maybe I'm wrong...

*Need to increase ProcODT when you increase vSOC*. Same reason as before it's on AUTO and now totally stable so I thought I wouldn't need to change it...but maybe I'm wrong..

Thank you so much for your tips and your transparency when speaking.

Should I change those or now focus on other timings, subtimings?

Thanks in advance!


----------



## mongoled

elvior2 said:


> I totally agree with what you're saying but trust me I'm not the kind of person of type "give, give, give". I'm so sorry if that was your impression.
> 
> I will try to answer now those questions.
> 
> This is my current settings:
> 
> View attachment 2466951
> 
> 
> *RttNom is disabled* because it was on AUTO on BIOS and given that now my system seems to be totally stable I thought I wouldn't need to fight with it...but maybe I'm wrong...
> 
> *Need to increase ProcODT when you increase vSOC*. Same reason as before it's on AUTO and now totally stable so I thought I wouldn't need to change it...but maybe I'm wrong..
> 
> Thank you so much for your tips and your transparency when speaking.
> 
> Should I change those or now focus on other timings, subtimings?
> 
> Thanks in advance!


Because you are asking for more from your RAM its not going to magically happen.

Leaving things on AUTO when you are wanting more and then and expecting more is like waiting for magical things to happen

 😂

So you need to establish a base when not on AUTO, it would be matter of changing the AUTO items to suggestions from those you trust.

If you dont deviate from AUTO, how will you even know what your setup likes or dislikes ?

Its only when you learn about your hardware can you push it more if that is what your aim is!

The impression of "give, give, give" is from the lack of feedback to those things that were asked of you, not providing adequate information regards these suggestions, then coming back for "more".

Hope you can understand the reasons it could come across this way. And I dont mean to say you are like that, but I can only go on what you provide in this forum......

Anyhow, if you want more, you must make the changes from AUTO, check stability. If stability remains then you must increase your vDIMM first.

When increasing your vDIMM you may need you to change other values, such a ProcODT and ClkDrvStr, its a balancing act when you start reaching limits!


----------



## mongoled

Oh and is this machine going to be used for critical applications ??

As the amount of hours you are running TM5 is unwarranted if not.

You could do max 25 cycles, but add other components for testing the RAM such as LargeFFTs which can be done using Y-Cruncher/Prime95 Large FFTs test.

As things may be TM5 stable but fail in minutes with other test, so you wasted 9 hours running TM5 without checking with other apps.

If you really want the 9+ hours TM5, do shorter tests with TM5/Y-cruncher/Prime95/RealBench etc and when these pass then go for the 9 hour TM5!


----------



## Esticbo

Veii said:


> SMU 56.30 is love
> I have even BAR support
> Never gonna install Patch C
> timings are still not serious ones, just to push FCLK


A big difference in super Pi (Patch C and SMU 56.34)


----------



## Veii

Esticbo said:


> A big difference in super Pi (Patch C and SMU 56.34)


Is this with the same timings like i used ?
Each boot, autocorrection behaves different
Each setup, up to used voltages seems also internally to autocorrect & cache perf differs

At this time & now i was playing around on many factors
What seems to make the biggest difference, is not only available power
(amount of cores sleeping) & distance from 90A EDC limit
But also the powerplan and it's current wake up idle state

Here some 6min results, same timings - just big difference around it
(stock boosting, stock wraith spire, PBO disabled to prevent variance)








Also finally i can post again ~ sigh spamfilter

EDIT:
Like look at this rollercoaster of cache performance
up to "powerplan idle state" an internal voltage "stepping difference"








I'm still figuring things out as we go
Dont take any of my benchmarks as "the best possible" result 
Mostly struggling since 3 days to get 2100FCLK to be stable
2066 is easy in comparison 

The voltages are replicatable 
also lower proc seems to work well, no need for 40ohm
same identical set works also for 2066FCLK


----------



## Esticbo

Veii said:


> Is this with the same timings like i used ?


NO, my memory is bad (samsung C die) only can reach FCLK and UCLK 1800 

That's why I wrote you that something was wrong in super Pi with the same cpu and stock frequency, but you with a better memory


----------



## Veii

Esticbo said:


> NO, my memory is bad (samsung C die) only can reach FCLK and UCLK 1800
> 
> That's why I wrote you that something was wrong in super Pi with the same cpu and stock frequency, but you with a better memory


mmm i see 
yes, i expected a bigger difference
but the cpu seems to only boost one core to 4.65 and uses only 8watts for superPi

i think our main difference is reserves
SOC alone for me uses 20Watts now, and CPU on this test only 8 
i think it cuts into the power reserves on stock

but can you give me your voltages and ohm setting
& try my voltage and procODT setting - to compare

Cache performance differs when you have these two set up differently
CPU does autocorrect a lot and auto adjust - it's hard to get the same results out
"little voltage difference = performance will be bad or better"


----------



## Esticbo

Veii said:


> mmm i see
> yes, i expected a bigger difference
> but the cpu seems to only boost one core to 4.65 and uses only 8watts for superPi
> 
> i think our main difference is reserves
> SOC alone for me uses 20Watts now, and CPU on this test only 8
> i think it cuts into the power reserves on stock
> 
> but can you give me your voltages and ohm setting
> & try my voltage and procODT setting - to compare
> 
> Cache performance differs when you have these two set up differently
> CPU does autocorrect a lot and auto adjust - it's hard to get the same results out
> "little voltage difference = performance will be bad or better"


At the moment my setting in bios are all in auto and pbo too


----------



## Veii

Esticbo said:


> At the moment my setting in bios are all in auto and pbo too


VDDP = IOD
and the rest has double 50mV stepping i see 
i will try this evening making a dump of my rom with profiles
flashing patch C and trying the same speed
curious to see how big the difference is

What is strange, is your tCKE is 0 - but GDM is enabled
this does not work in reality lol
but tCKE 16 is a good value to play with i figured
Memory Interleaving 512kb is still the best setting to use

I will replicate and cross benchmark, am curious
But 56.34 has an FCLK hardlock of 1900Mhz
56.30 has a FCLK hardlock of 2100Mhz (1mhz more refuses to post lol)

I got a bios with BAR support and still old SMU,
Sadly dont have a new enough GPU on hand to test,
only use CSM

Unsure how well SOC by default changes for you
But negative offset of -50mV hits always stable auto SOC across the whole range
2067 predicts 1.2v , -50 works here, 2100 predics 1.25vSOC , -50 is also fine

ProcODT 32 seems to be good for sub 1900FCLK
34 seems to be better for 2067Mhz
testing strongly 32 & 34ohm ,boosting behaves different with different procODT >_>
and behaves different with different powerplans
To top it off, Core quality in HWInfo changes with different procODT lol. not only curve optimizer does change them

VSOC 1120-1125 works perfect across all ranges
only 2100FCLK is still a not won fight, it needs something near 1181-1200mV SOC
but SOC hard crashes by "overcurrent protection" . . .


----------



## Veii

Can anyone with a MSI B550 or X570 board who has Vermeer, confirm for me the max Boost Clock override - Fmax , on their board (PBO Advanced)
If you have beyond 200Mhz, please attach a zentimings screenshot , so i can read out the SMU version


----------



## Veii

Oke so this is pretty clear for me at this point
But i want to repost it here too, so it get's more attention 

SMU 56.34 is BAD, very very bad
Idk yet what of it is that horrible but it has a 1900FCLK limit in there
Meaning - i can not even boot my 1900FCLK anymore. While 1867 boots & is stable without issues

I've seen and read the continues marketing attempts to bring people updating to 1.1.0.0 Patch C, updating to 1.1.8.0 and higher
But i can not understand as enthousiast ~ why anyone would fall for this and give away performance
AMD has done this once already , well several times for Matisse ~ slowly but surely cutting away features and maximum Fabric Clock

Now doing it again, is just plain wrong.
These CPUs, Vermeer is capable of holding 2100FCLK
Yes it's very hard to set up, and i have to admit to still struggle in getting it long stable
~ but 2067Mhz is like a childs toy , easy to stabilize under low voltage

There is absolutely nothing in newer Patches that justifies to trow away performance

no IPC gains
no higher boostclock
nothing done to cores in helping them to boost higher (core quality detection is variable up to used voltage and proc)
no higher single core boost
no higher render boost, for example SuperPi
Nothing 

Maybe the numbers are different & how "effective" fabric clock is now.
Soo maybe these are IPC improvements
But they remain a theoretical thing, when we have a hardlock on it
It makes no sense for me to not only trow away memory bandwidth and low latency - but also be limited in even trying to stabilize "unstable fabric clock"
At least on SMU 56.30 pre-patch C , i can try and work on 2100 FCLK
On the newer "standartized user enforced" one ~ i can not ! We users got pretty much locked

And all that, just so BAR mode "maaybe" functions better and the chance of PCIe crashes are lower
Although again, normal AGESA 1.1.0.0 SMU 56.30 does indeed haveBAR support & also Curve Optimizer support


----------



## Veii

Another post to round things up 
I have played with the "EDC BUG" a bit
It's interesting how, AMDs boosting mechanism "reverses" in itself
EDC BUG on this generation is triggerable with PBO EDC 1-3,

4A already is used, and 5A too
It will try to sustain an allcore of around 650Mhz with one single core staying near 3.1ghz
Thats common for these CPUs, as 4.65ghz Single Thread SuperPi only uses 8W / 12A for the whole run

5600X defaults move @
PPT 75W
TDC 50A
EDC 90A
where most of the times, EDC is triggered first under sustained allcore loads ~ enforcing lower vCore alltogether 

PPT limit is triggered in non AVX workloads, or mixed instruction set workloads
Games, Photo Editing, browsing, emulators, Audio Engineering
On these workloads, the cpu mostly triggers it by having more than 2 threads running full-speed boost
Which on statistic tracking utlitizes shows up as "all cores having 4.5+ boost"
well they are just switching position ~ to keep overall W & silicon strain, lower

If you want to extend the CPUs ability with PBO Max clock & your cores actually can keep up thanks to curve optimizer
It's recommended to still move in the defined limits, but just increase EDC a subtle bit and PPT a subtle bit
10W or 5A already go a long way 

Don't just open it up and let it throttle in itself,
High clocks like on the EDC bug, still result in worse performance, and Fabric latency thanks to continues throttle of 120+ ns (instead of sub 28ns for example)
Simply as "throttling" is the default state with the BUG, and non throttle is the "throttle state"
imagine reversed boosting 
That's all the EDC bug does
There might be a way to use it, but to my investigations - contineous FIT throttle with >120ns inter-core latency, is just very bad performance with very nice looking fake boosting numbers


----------



## Alyjen

Hi there, a noob question. How stable are higher FCLKs for you? I'm not asking about TM5, or Prime95 like stuff as it never crashes for me at 1900 but about these annoying WHEA 19 warnings. I had zero crashes or issues since I build my set (5800X Asus TUF B550 board, 1212 and 1216 BIOS) but heavy load like Prime95 or OCCT will make WHEA 19 warning appear. Tried to tweak voltages up and down without great success. I can make things worse and get WHEA while idle, but I was never able to get rid of them entirely. 

Timings and voltages attached. AIDA64 performance is where I want to be (unless they patch AGESA so much I'm able to stabilize FLCK at 2000MHz)


----------



## qwrty

Any tips to reach 1900 FCLK ?



I can't POST with anything else above 1800FCLK.
(X570 Strix / 2816 BIOS)

Is it my 4 sticks setup the problem ?


----------



## Veii

Alyjen said:


> Hi there, a noob question. How stable are higher FCLKs for you? I'm not asking about TM5, or Prime95 like stuff as it never crashes for me at 1900 but about these annoying WHEA 19 warnings. I had zero crashes or issues since I build my set (5800X Asus TUF B550 board, 1212 and 1216 BIOS) but heavy load like Prime95 or OCCT will make WHEA 19 warning appear. Tried to tweak voltages up and down without great success. I can make things worse and get WHEA while idle, but I was never able to get rid of them entirely.
> 
> Timings and voltages attached. AIDA64 performance is where I want to be (unless they patch AGESA so much I'm able to stabilize FLCK at 2000MHz)
> View attachment 2466995
> View attachment 2466996


It's very interesting that you can post 1900 
Read my posts above , there is a lock beyond 1900
for me idk why - guess i'm unlucky

Test stability with y-cruncher ,
press number 1 to "component test", then 6 "to select all tests" and 0 " to start "
it will take 18 min each loop - you nee to pass 4 cycles
Beyond 3
If you can pass that, then your problem is different

Your issue is your VDDP is higher than your VDDG CCD
VDDP + x = VDDG +x = VSOC
x always has to stay the same voltage stepping or a multiple of it
Zen 3 likes 40mV as stepping
you can use 2*40mV, 3*40mV and so on

As long as this scaling exists it will not have random crash-errors
This was since Matisse the case an still exists - just this time it's 40mV not 50mV minimum scaling
Readable here:
OC'ing T-Force 4133 cl18 bottom part of the post

I've attache before some screenshots of stable settings
for you
either you push VDDP down to 950mV and increase VDDG CCD to 1000mV
or you increase SOC to 1150 then you can push CCD to 1050
There is no issue ifboth VDDG are identical
but there is an issue if VDDP is too high or SOC too low

High IOD an low CCD are the advices i can give you for this generation
Too high VDDG CCD voltage causes crashes and issues
~ it's important not to ignore CCD voltage this time


qwrty said:


> Any tips to reach 1900 FCLK ?
> 
> 
> 
> I can't POST with anything else above 1800FCLK.
> (X570 Strix / 2816 BIOS)
> 
> Is it my 4 sticks setup the problem ?


yes, but not only
if you use 4 dimms try higher Clkdrvstr
4 dimms or dual rank can move beyond 60ohm
Zen 3 can post beyond 2000 fabric even with 58ohm procODT
Negative scaling wasnt found yet
2100 will run with 34-58ohm procODT, all off them work

SMU 56.34 is not able to go beyond 1900FCLK
But you run too low SOC
same post as the quote above
voltage stepping - is important
give SOC a bit more like 20mV
or if you stay on auto , try to use global -50mV offset
by default these AGESA's overvolt a bit on SOC
And Zen3 is very SOC hungry 

you can go up to 1.125v SOC without issues
2100 fabric will require you to run 1.2-1.25v SOC to have a chance of stability,
if you decide to downgrade the bios one step down to AGESA 1.1.0.0 non patch C


----------



## Alyjen

Veii said:


> It's very interesting that you can post 1900
> Read my posts above , there is a lock beyond 1900
> for me idk why - guess i'm unlucky
> 
> Test stability with y-cruncher ,
> press number 1 to "component test", then 6 "to select all tests" and 0 " to start "
> it will take 18 min each loop - you nee to pass 4 cycles
> Beyond 3
> If you can pass that, then your problem is different
> 
> Your issue is your VDDP is higher than your VDDG CCD
> VDDP + x = VDDG +x = VSOC
> x always has to stay the same voltage stepping or a multiple of it
> Zen 3 likes 40mV as stepping
> you can use 2*40mV, 3*40mV and so on
> 
> As long as this scaling exists it will not have random crash-errors
> This was since Matisse the case an still exists - just this time it's 40mV not 50mV minimum scaling
> Readable here:
> OC'ing T-Force 4133 cl18 bottom part of the post
> 
> I've attache before some screenshots of stable settings
> for you
> either you push VDDP down to 950mV and increase VDDG CCD to 1000mV
> or you increase SOC to 1150 then you can push CCD to 1050
> There is no issue ifboth VDDG are identical
> but there is an issue if VDDP is too high or SOC too low
> 
> High IOD an low CCD are the advices i can give you for this generation
> Too high VDDG CCD voltage causes crashes and issues
> ~ it's important not to ignore CCD voltage this time


Some manufactures introduced locks after 1900 with most recent updates, they got rid of WHEA at lower settings thou.
I'll read through this voltage recommendations, thank you! Mine are all on auto so far, only thing I did was VDDR SOC line calibration set to 5 (highest) as it made 1.1V flat, previously it was 1.081 and even less stable than now.

edit: also what you say with 40mV steppings could look like this? 

VDDP 0.94
VDDG 1.02
VSOC 1.10


----------



## Veii

Alyjen said:


> Some manufactures introduced locks after 1900 with most recent updates, they got rid of WHEA at lower settings thou.
> I'll read through this voltage recommendations, thank you! Mine are all on auto so far, only thing I did was VDDR SOC line calibration set to 5 (highest) as it made 1.1V flat, previously it was 1.081 and even less stable than now.


you can run 1.075 for 1900 FCLK ~ up to remain voltages
It should be an SMU lock an no manufacture lock
Manufactures just use what they get from AMD and compile it + add some own flair

It might be a microcode thing, but i will investigate where the lock exactly is in SMU / microcode
Because it clearly can run up to 2100FCLK & up to 2067 with 900 VDDP, 940 CCD, 1060 IOD, 1100 SOC
VDDP even on Matisse (same IMC like 2700X) doesn't need more than 900mV
but this depends on procODT state

Have toyed around enough last days, with the Wraith Spire
Time to use good cooling and work on memOC + PBO


----------



## Alyjen

Veii said:


> you can run 1.075 for 1900 FCLK ~ up to remain voltages
> It should be an SMU lock an no manufacture lock
> Manufactures just use what they get from AMD and compile it + add some own flair


true, my comment was based on my friends experience with MSI boards rather than solid knowledge 
they got tons of WHEA, unstable at anything above 3200MHz but they could post at 2000MHz and some even above, and with this new BIOSes they got rock stable up to 1900MHz and no post at 2000MHz


----------



## qwrty

Veii said:


> yes, but not only
> if you use 4 dimms try higher Clkdrvstr
> 4 dimms or dual rank can move beyond 60ohm
> Zen 3 can post beyond 2000 fabric even with 58ohm procODT
> Negative scaling wasnt found yet
> 2100 will run with 34-58ohm procODT, all off them work
> 
> SMU 56.34 is not able to go beyond 1900FCLK
> But you run too low SOC
> same post as the quote above
> voltage stepping - is important
> give SOC a bit more like 20mV
> or if you stay on auto , try to use global -50mV offset
> by default these AGESA's overvolt a bit on SOC
> And Zen3 is very SOC hungry
> 
> you can go up to 1.125v SOC without issues
> 2100 fabric will require you to run 1.2-1.25v SOC to have a chance of stability,
> if you decide to downgrade the bios one step down to AGESA 1.1.0.0 non patch C


Thx !

I’m on auto on vSOC/VDDP/VDDG/ IOD
I have tested 1.125v on VSOC but it did not help. 
Will try with your tips with procODT and clkdrvstr. 

I’m targeting 1900mhz. More will be too complicated with 4 stick anyway I think.


----------



## Dasa

I have been unable to post over 1900IF with any BIOS so I thought I would try undervolt the SOC.
[email protected] 1.47-1.5VDIMM
VSOC 0.9313V (Offset -0.5) vs Auto 1V
CLDO VDDP 0.8V vs Auto 0.9V
VDDG IOD\CCD 0.8471V (set 0.85V) vs Auto 0.9V

CLDO VDDP would not post at 0.7V and 0.75V was unstable.
Rest may be able to go lower but* Veii *suggested above that CLDO VDDP should be lower than the rest so I left it at that for now.


----------



## Veii

Alyjen said:


> edit: also what you say with 40mV steppings could look like this?
> 
> VDDP 0.94
> VDDG 1.02
> VSOC 1.10


Pretty much yes
although don't ignore VDDG, split it 
CCD can and should stay low this generation
too high CCD caused crashed for me on y-cruncher
high IOD is what is needed

It's funny,
on one hand this silicon is insanely power efficient
On the other hand also insanely powerhungry 
Renoir was very similar behaving (sometimes up to 1.3vSOC)
~ seems to be the colour change

Old Matisse days i kept recommending double stepping for VDDP-VDDG and double stepping or SOC
although only because you couln't expect 1v SOC to run 1900

Today, it's rather single stepping for VDDP->VDDG CCD, double stepping for IOD and then another double for SOC
The limits on CCD (1050) IOD (1150) i would continue to hold
VDDP beyond 1050 is damaging, CCD might be pushed to 1100 but already beyond 980mV i saw issues with it
IOD beyond 1100 is already too much for this already vintage 12nm I/O-Die 



Dasa said:


> I have been unable to post over 1900IF with any BIOS so I thought I would try undervolt the SOC.
> [email protected] 1.47-1.5VDIMM
> VSOC 0.9313V (Offset -0.5) vs Auto 1V
> CLDO VDDP 0.8V vs Auto 0.9V
> VDDG IOD\CCD 0.871V (set 0.85V) vs Auto 0.9V
> 
> CLDO VDDP would not post at 0.7V and 0.75V was unstable.
> Rest may be able to go lower but* Veii *suggested above that CLDO VDDP should be lower than the rest so I left it at that for now.
> View attachment 2467045


700 should work, we confirmed this on Matisse too
It should have the same voltage running abilities like a 2700X
What does make issues, is high procODT
Try that with 30ohm procODT
30 ohm are enough for 1900FCLK
(well even 28ohm where in the old days ~ but as this one needs more SOC overall, 28ohm is a bit too low)


> VSOC 0.9313V (Offset -0.5) vs Auto 1V


This is what i figured and recommend now too
it seems to work perfectly across the whole range of "auto predicted" voltages
from 1800 till 2100FCLK
-------------------------------------------------
Just 2100 is OCP hardlocking on me still
something with proc and CCD is not fin
~ still fighting with it for day #3
might be also just a core voltage thing , i'll figure it out it just needs time

The powerplan research is halfway done
If AMD CBS is open for you guys,

disable SMEE
enforce 512 Bytes memory interleaving
disable memory clear
under NBIO -> SMU, enforce both CPPC and CPPC Preferred Cores
APBDIS to 0 just for good measure once SOC gets unlocked to be variable again 

For the rest, we need to see what's open per user
Enforcing -50mV SOC offset seems to work well
I suggest also to watch HWInfo core "quality" sorting
You can "improve" which cores are "golden cores" just by playing either with the global negative vCore offset, or the PBO Curve optimizer option
For me even PBO Scaler x2, already was enough to give it a 40-50mV lift up and then filtered down with a global negative offset
Although global offset and curve optimizer together work better than this scalar
The scalar is a bit too agressive and already at x3 is too strong for me

Oh i also suggest to start with y-cruncher 3 loops in testing voltage stability
And having Aida64 by hand
If memory access latency jumps more than 0.3ns per test
then adjust procODT (first) and then voltages

Vermeer does throttle on many parts to maintain stability,
it's very hard to make it crash, but it's very easy to make it unhappy and deliver "fake" results


----------



## Dasa

Veii said:


> Oh i also suggest to start with y-cruncher 3 loops in testing voltage stability


Dam that is even more brutal than p95 small ftt. It goes from ~75c first pass instantly to 90c+ in the second test and the system restarts due to overheat.
Even undervolting CPU\SOC 0.05v doesn't help.
I am running a custom loop with temps lower than a lot of 5800X users.



Veii said:


> 700 should work, we confirmed this on Matisse too
> It should have the same voltage running abilities like a 2700X
> What does make issues, is high procODT
> Try that with 30ohm procODT
> 30 ohm are enough for 1900FCLK


30 ohm works nicely but it still fails to post at 700mv CLDO VDDP



Veii said:


> disable SMEE
> enforce 512 Bytes memory interleaving
> disable memory clear
> under NBIO -> SMU, enforce both CPPC and CPPC Preferred Cores
> APBDIS to 0 just for good measure once SOC gets unlocked to be variable again


Changed those settings I will have a play around and see if I can notice any change.

Edit: also found a oddity where I can boot at 1900IF tCL15 but it wont post at 1900IF tCL16.


----------



## glnn_23

I have just switched from 2x8gb to 4x8Gb 4400c16 @ 3800c14
Main changes are GDM enabled and tWRRD 1 to 2.


----------



## Comalive

Veii said:


> Can anyone with a MSI B550 or X570 board who has Vermeer, confirm for me the max Boost Clock override - Fmax , on their board (PBO Advanced)
> If you have beyond 200Mhz, please attach a zentimings screenshot , so i can read out the SMU version


Hi, I can go up to 500 MHz offset.








I am currently trying to get this running at good speeds while keeping low voltages, this constellation withstood AIDA64 cache and memory stress test for 1 hour, TestMem5 anta777 found 4 errors though.
So far I have changed (VDDG) CCD to .94 and IOD to 1.02, following your recommendations. I will do some stress tests with these new settings, further advice is appreciated.
Current VDIMM = 1.4 on 4 x 8GB.


----------



## craxton

hello, kinda new..ISH to ram overclocking in which i recently went from a hynix kit J die of 3466oc to 3600cl16 and am now on teamgroup c14 3200 2x8 and am curious as to what i can do to get these timings better besides not leaving most on auto in which i had used dram calc by importing the xmp profile but the kits only rated at 3200 so im unsure if using dram calc would work that way? anyhow here are some screenshots, replying to you in general as i see your name appear the most and yes i know my 3600XT is downclocked, thats just a matter of heat atm and just testing out ram overclocking as i wasnt sure if 4.5ghz cpu oc with 1.3375volts was the cause of a crash or not so i lowered the core clock, but quickly figured out that wasnt the issue have that solved now. but seeing as to how i bought this kit just for this purpose...do you have any suggestions i should try??


----------



## Veii

Dasa said:


> Dam that is even more brutal than p95 small ftt. It goes from ~75c first pass instantly to 90c+ in the second test and the system restarts due to overheat.
> Even undervolting CPU\SOC 0.05v doesn't help.
> I am running a custom loop with temps lower than a lot of 5800X users.


Lol 
Yea it's brutal, but it shouldn't be thaat extreme
i remember the 5800X was very interesting
branded as "low tdp" cpu "for gamers"
But once stresstested it instantly exceed 180W but only in all core loads
No idea why EDC was soo extremely high programme - rather the microcode allowing to ouble it's own capabilities
... oh wait you have no 5900X ~ well there is the answer 

Something on it is designed to exceeds it's capabilities only on multi core loads
I can't get my 5600X beyond 150W while on stock it stays @ 75W
It's really an interesting silicon ~ very efficient but can take soo much current if you let it


> Edit: also found a oddity where I can boot at 1900IF tCL15 but it wont post at 1900IF tCL16.


This is strange 
Yea i had one which it only wanted to post with loaded or change xmp
but not if xmp was never loaded

I will repeat again
"Don't fully open PBO, only limit it slowly. 10W PPT or 5A EDC already do a lot" 
The same counts also or Matisse
Well written article by our member @polkfan


Spoiler





__
https://www.reddit.com/r/Amd/comments/e8nne7



no need for EC bugs or per CCX OC
PBO finetuned can work even back then very well
no need to get ryzen master - HWInfo already shows all you need to know
But get it as inspiration and tutorial how things work out
AutoOC does work but shifts the boosting curve and messes stuff up on Matisse
Now we have curve optimizer to work against it 
Big topic but take a look 

In order to lower allcore voltages, you need to have EDC peaking at 100%
and TDC near 98%
PPT mostly goes for llight threaded workloads, but you need a powerplan with CPPC , soo cores actually sleep and draw less power
= more boosting headroom with less required voltage


> Changed those settings I will have a play around and see if I can notice any change.


That's all i could figure out till i open up more settings on my bios
The cpu is soo variable and sensitive. Each run is unique
Once you have your target FCLK, and target voltage stable under y-cruncher 3+ cycles (3*18min)
Keep memory testing on Aida64 and change procODT across the whole range.Till 90 ohm
Your cache perf and also memory perf will change because your effective boosting will change

Other changes like powerplan starting idle state
(i suggest 7 & 10% on a full idle powersave powerplan ~ WIP)
are visible on SiSandra Multi-Core Efficiency Test (highest latency category)
Lowest latency shows boosting behavior ~ but as every little voltage change affects the outcome
It's too variable and hard to track
Latency Curve visible under "detailed" view.
~ be sure to sort by date and local results only after running one test (refresh button)


Comalive said:


> Hi, I can go up to 500 MHz offset.
> View attachment 2467096
> 
> I am currently trying to get this running at good speeds while keeping low voltages, this constellation withstood AIDA64 cache and memory stress test for 1 hour, TestMem5 anta777 found 4 errors though.
> So far I have changed (VDDG) CCD to .94 and IOD to 1.02, following your recommendations. I will do some stress tests with these new settings, further advice is appreciated.
> Current VDIMM = 1.4 on 4 x 8GB.


This gives hope that AMD might not hardlock us out and repeat the matisse PCIe 4.0 nonsense all over again
Thank you !
I will see if i find anything valuable in this bios to extract and replicate
200Mhz override is not enough
You MSI guys also have 3 PBO profiles which seem to work very well


----------



## Veii

This is the difference between GDM ON & GDM OFF 2T
2T is faster than 1.5T
On top of that it wipes odd primaries autocorrection
Keep working on CAD BUS -> ClkDrvStrength, till you find a strong enough impedance setting for your memory kit to run GDM off 

















Lower looking boost ~ but that's the powerplan
Lazy CL16 flat timings @ 1.46v but i've poste them here already to replicate
Still stock boost no special tweaks , ust around it optimisations
Stepped up to humane cooling away from the Wraith Stealth
But i'm again since 22h awake zZZ
Tomorrow the 50ns wall will be gone. Still have a lot of headroom & PBO let to play with
Toyed enough the last couple of days with lame scores on the stock cooler


----------



## qwrty

Vei, one thing I did not understand, you suggested to me, that my SOC is too low at 1.08v for 4 sticks (auto value) but you recommend to lower it with a negative offset of -50mv ?

Can you clarify ? [emoji28]



glnn_23 said:


> I have just switched from 2x8gb to 4x8Gb 4400c16 @ 3800c14
> Main changes are GDM enabled and tWRRD 1 to 2.
> 
> View attachment 2467081


Give me some hope to get this 1800FCLK with my Strix X570 and 4 sticks. [emoji28]


----------



## Dasa

Veii said:


> will repeat again
> "Don't fully open PBO, only limit it slowly. 10W PPT or 5A EDC already do a lot"


That will teach me for thinking if I set my CPU back to stock clocks and default PBO settings that the MB would actually set default power limits.
Running nicely now I have set it manually to stay under 130w 85c.

Thanks a lot for sharing your knowledge\experience with us it is really appreciated.


----------



## mongoled

Veii said:


> This is the difference between GDM ON & GDM OFF 2T
> 2T is faster than 1.5T
> On top of that it wipes odd primaries autocorrection
> Keep working on CAD BUS -> ClkDrvStrength, till you find a strong enough impedance setting for your memory kit to run GDM off
> 
> View attachment 2467105
> View attachment 2467106
> 
> 
> ....snip


But "they" dont listen, none of them listen

It seems like having the "better" number is better than having the higher performing number

😂 😂



Dasa said:


> snip........Edit: also found a oddity where I can boot at 1900IF tCL15 but it wont post at 1900IF tCL16.


When you get such weirdness, have you tried simply going into BIOS and flicking through key timings/settings such as Cmd rate, CPU voltage by just moving the current value up/down one and then putting it back and then saving BIOS and seeing if it boots ??

I have seen such issues in the past, its as if some other settings are being changed in the background but are not showing in the BIOS menu, flicking the values then puts them where they should be....



glnn_23 said:


> I have just switched from 2x8gb to 4x8Gb 4400c16 @ 3800c14
> Main changes are GDM enabled and tWRRD 1 to 2.
> 
> View attachment 2467081


Hi, GDM enabled with 2T is not possible ???

Also, tRDRDSCL/tWRWRSCL have better read throughput on my 3600 when using 4x8GB @4/5 than 2/3 have you test this on the 5000 series ??


----------



## Alyjen

Veii said:


> Pretty much yes
> although don't ignore VDDG, split it
> CCD can and should stay low this generation
> too high CCD caused crashed for me on y-cruncher
> high IOD is what is needed
> 
> It's funny,
> on one hand this silicon is insanely power efficient
> On the other hand also insanely powerhungry
> Renoir was very similar behaving (sometimes up to 1.3vSOC)
> ~ seems to be the colour change
> 
> Old Matisse days i kept recommending double stepping for VDDP-VDDG and double stepping or SOC
> although only because you couln't expect 1v SOC to run 1900
> 
> Today, it's rather single stepping for VDDP->VDDG CCD, double stepping for IOD and then another double for SOC
> The limits on CCD (1050) IOD (1150) i would continue to hold
> VDDP beyond 1050 is damaging, CCD might be pushed to 1100 but already beyond 980mV i saw issues with it
> IOD beyond 1100 is already too much for this already vintage 12nm I/O-Die


Ok to I gave y-cruncher a go, this one is taken a while after 1st pass, it went like this longer, throwing WHEA warring in registry once in a while but test was stable,some of AVX tests pushed my cooling to 90C but chip reacted like it should and test continued stable 









I left VSOC at 1.1 with LLC at 5, which give flat 1.1V all the time (leaving it on auto gives 1.081 and errors appearing faster)
CLDO VDDP - dropped to 0.9V as suggested to have a working room for others
VDDG CCD - moved from auto (0,9V) to 0,94V to separate it from VDDP - I'm not sure if it's good idea
VDDG IOD - left on auto 1,05V 


Two questions:

seeing machine work, game & stress test stable how crazy I should be about these WHEA warnings?
where can I find extra stability, I can try and drop IOD to match double stepping so it'd be
VDDP 0,9V CCD 0,94V IOD 1.02 & then SOC still at 1.1V 

Like I wrote a while ago, I can make things worse by adjusting these voltages. Best I got was ~1 WHEA every 4-5 minutes, instead of 4 WHEA ever minute


----------



## glnn_23

mongoled said:


> Hi, GDM enabled with 2T is not possible ???
> 
> Also, tRDRDSCL/tWRWRSCL have better read throughput on my 3600 when using 4x8GB @4/5 than 2/3 have you test this on the 5000 series ??


I've only had the 2nd 16Gb a day so still woking it out.
2x8Gb I run these settings with GDM disabled but with 32Gb so far it is difficult to post so will spend more time on it.
Will test the tRDRDSCL/tWRWRSCL at the settings you suggested as well.
Thanks for your input.


----------



## kim nk

5600 x
ASUS ROG VIII X570 IMPACT BIOS 2702
CL16 4400 ROYAL (XMP, DOCP) 8X2

CLDO_VDDP 0.900V VDDG_IOD 1.050V VDDG_CCD 0.940 SOC 1.1V

CL14 3800 dream 1.48V


























Tested with 40mv 50mv stepping. 
Are there any parts to be fixed?
Please advise.


----------



## MikeS3000

I just installed a 5800x last night on my Aorus Pro Wifi. I am running 4x8 gb Trident Z Neo DJR RAM. I basically used the exact same setting that I used on my 3900x except for the VSOC, VDDP and VDDG values. I took @Veii 's advice and used increments of 40 mv when tuning the voltage values. I ran AUTO on everything just to see what the board would set. Looks like it selected 1.05v VSOC and 0.975 for all the other 3 voltages. It was decently stable, but Memtest stopped working so I had to change some values. I settled on VSOC 1.075v, VDDP 915 mv, VDDG IOD 995 mv and VDDG CCD 955 mv. Metest passed 20 cycles of 1usmus v3 and no WHEA errors! @Veii did I setup the voltages correctly based off of VSOC 1.075v?

Next, on this same BIOS I was able to POST and boot windows at FCLK 2000 (didn't try and push farther) at the default AUTO values above and set RAM at 3800. I really want to try and tune my DJR RAM and try for DDR 4000. What would be some reasonable settings to try?


----------



## Alyjen

MikeS3000 said:


> I just installed a 5800x last night on my Aorus Pro Wifi. I am running 4x8 gb Trident Z Neo DJR RAM. I basically used the exact same setting that I used on my 3900x except for the VSOC, VDDP and VDDG values. I took @Veii 's advice and used increments of 40 mv when tuning the voltage values. I ran AUTO on everything just to see what the board would set. Looks like it selected 1.05v VSOC and 0.975 for all the other 3 voltages. It was decently stable, but Memtest stopped working so I had to change some values. I settled on VSOC 1.075v, VDDP 915 mv, VDDG IOD 995 mv and VDDG CCD 955 mv. Metest passed 20 cycles of 1usmus v3 and no WHEA errors! @Veii did I setup the voltages correctly based off of VSOC 1.075v?
> 
> Next, on this same BIOS I was able to POST and boot windows at FCLK 2000 (didn't try and push farther) at the default AUTO values above and set RAM at 3800. I really want to try and tune my DJR RAM and try for DDR 4000. What would be some reasonable settings to try?


TM5 shouldn't generate any WHEA errors unless things are really bad, I could do this for hours, it's really good for checking memory subtimings. 
Prime95 Large FFTs no AVX will do it within minutes, same with OCCT. Like in my example, I don't get any WHEA in real life scenarios unless I mess the voltages really bad. 
I do get them sooner or later when I apply some heavy load & memory/controller stress, yet stress tests don't fail/crash


----------



## Esticbo

Samsung C die @3800 FCLK 1900 UCLK 1900 working in progress


----------



## Alyjen

Ok this is funny, I tried enabling ECO mode => all WHEA errors are gone, overall performance lower, but memory related results unaffected. 

So how does it change my FCLK & voltages vs WHEA situation? Does it mean they are caused by:

overheating
lack of power, or other power management issues with PBO on auto (CPU SoC power still goes to around 20W, while power left for CPU is not hitting nowhere near 120W+ anymore)
else?

I can live with that waiting for BIOS update.


----------



## craxton

dont know if it matters that i do have synapse software, afterburner and a few other apps running in the background but this is without GDM with one change to tRFC and the mentioned GDM being off and still in 1T. and passing 10 runs of tm5 . ive found that with these chips (teamgroups 3200mhz c14 kit, that within the third run errors pop up if its unstable cant say thats 100% always the case but so far everything that wasnt stable that brought errors did.


----------



## craxton

Esticbo said:


> Samsung C die @3800 FCLK 1900 UCLK 1900 working in progress


 ive got a set of lpx 2x8 kit with c die GOD forbid me from sticking that back into my system again. or at least thats what someone told me on buildzoids channel and is why i had such a hard time with the kit posting at XMP at all... (CMK16GX4M2D3600C18) is the kit. 4.32 is the version number which is where C die came into play.


----------



## Esticbo

craxton said:


> ive got a set of lpx 2x8 kit with c die GOD forbid me from sticking that back into my system again. or at least thats what someone told me on buildzoids channel and is why i had such a hard time with the kit posting at XMP at all... (CMK16GX4M2D3600C18) is the kit. 4.32 is the version number which is where C die came into play.


I've got 3200 4.32 and I know how hard to set it, but I can't spent more money in a ram, here the b-die can cost as a 3300x


The G. Skill work better and they are amd certificate 😂😂😂. I love old school oc


----------



## m3ta1head




----------



## Rujaza

Hi all, I've a set of 4x8Gb 3200c14 B-Die and this is my situation at 1.41v DRAM, no CPU OC or PBO tweak.










Is there more to squeez out of this set at this voltage? What should I consider to test?

The system right now is stable but now and then I hear an audio crack. Seems I delayed it by happening rising VDDG IOD but I'm not entirely sure It's the right parameter to tweak, any suggestions?


----------



## Jackalito

Alyjen said:


> Hi there, a noob question. How stable are higher FCLKs for you? I'm not asking about TM5, or Prime95 like stuff as it never crashes for me at 1900 but about these annoying WHEA 19 warnings. I had zero crashes or issues since I build my set (5800X Asus TUF B550 board, 1212 and 1216 BIOS) but heavy load like Prime95 or OCCT will make WHEA 19 warning appear. Tried to tweak voltages up and down without great success. I can make things worse and get WHEA while idle, but I was never able to get rid of them entirely.
> 
> Timings and voltages attached. AIDA64 performance is where I want to be (unless they patch AGESA so much I'm able to stabilize FLCK at 2000MHz)
> View attachment 2466995
> View attachment 2466996


What voltage are you pumping for the RAM itself?
Thanks for sharing your results.


----------



## craxton

Esticbo said:


> I've got 3200 4.32 and I know how hard to set it, but I can't spent more money in a ram, here the b-die can cost as a 3300x
> 
> 
> The G. Skill work better and they are amd certificate 😂😂😂. I love old school oc


considering i literally bought teamgroup DARKZa 4000mhz not paying attention X2 yes thats right 4 sticks 32gb 8gb sticks (which is C/Djr not to sure) not good for the price over the 3600 kit) and this c die kit as well as the 3200c14 bdie kit which im running now which TM5 with anta777 extreme profile has been going for around an hour and 26 minutes now with 3800mhz with one change from the screenshot above to timings and that being 16,15,15,15,32,38 trfc288 ect and the rest pretty much the same as before so pretty much just went from 3600 to 3800 and slightly loosened the timings with the same voltage @1.4v so far stable. point is ill be sending all the others back except for one of the 4000mhz kits to amazon...after tallying up what ive spent in ram this past week alone i could have literally got a third 3600XT before the price went ******edly high again (bought one got the 2nd free amazon made a mistake claiming i hadnt recieved the 1st one when i clearly sent them picks showing it in my hands but they insisted i take it and keep my mouth shut so thats what i did)... considering i have an old set of 2400mhz c14 TLred from teamgroup with J die, clocks to 3200mhz c16 pretty easy, and hyperX3466 kit j die i believe which was my best kit up till three days ago... for the cost difference it very well still may be my best kit lol....im currently working 12hours a day..well night and 6 days a week so money at this time isnt an issue...

if you lived closer id simply give this cdie kit to you so i could see it be used instead of being pawned off so someone believing that its amd ready like the listing says (checking corsairs website quickly shows its not)


----------



## craxton

just finished finally when i got done on my phone replying to you....perhaps at this time without anymore knowledge of what it is i should shoot for this is where ill stick too until i read a few more days on ram sub timings ect.... GDM was turned on and improved my aida score which swapped one timing from 14,15,15,32 to 16,15,15,32 ect. thats the only timing i seen swapped while using GDM...or then again perhaps ill see about getting a little tighter sub timings..perhaps that tfaw could use a cutting in half....


----------



## craxton

idk if this says anything or not but here is the hyperX kit i spoke of but that write speed is well...the best ive had yet....


----------



## Alyjen

Jackalito said:


> What voltage are you pumping for the RAM itself?
> Thanks for sharing your results.


Ram alone is 1.4V and it's passing all sort of memory focused tests so timings/voltage are fine.


----------



## Sp ceman Spiff

m3ta1head said:


> View attachment 2467156
> View attachment 2467157


Very impressed


----------



## Dasa

I had just gotten WHEA errors under control when GB releases a new BIOS for the B550 Aorus Pro that fixes the 1900IF hard limit and I can now boot at up to 2000IF.
However even 1866IF spews out WHEA errors and 2000IF seems to need gear down mode enabled to boot so far.

Currently testing 4000 RAM 1800IF and that seem stable shame it performs like crap.
Will keep playing around to see if I can find any rhyme or reason to it.


----------



## Alyjen

Dasa said:


> I had just gotten WHEA errors under control when GB releases a new BIOS for the B550 Aorus Pro that fixes the 1900IF hard limit and I can now boot at up to 2000IF.
> However even 1866IF spews out WHEA errors and 2000IF seems to need gear down mode enabled to boot so far.
> 
> Currently testing 4000 RAM 1800IF and that seem stable shame it performs like crap.
> Will keep playing around to see if I can find any rhyme or reason to it.


Similar with Asus on current and previous BIOS. I can boot all the whay up to 2000 IF but gives me WHEA even at idle, and terrible performance it doesn't look like I could stabilize it with current BIOS. 
1900 IF seems stable everywhere but heavy synthetic load like OCCT, Prime95, y-cruncher will eventually generate few WHEAs, one every few minutes. Here hope they are going to fix it.

You'll be always better with FLCK to MCLK ratio 1:1, so if best you can have is 1800IF then 3600 for RAM & go down with timings.


----------



## VPII

Okay, I've had this Ryzen 9 5950X for the past week or two and I've been struggling to get memory speeds in the same range as I had with my 3950X. AT present I have two sets of G-Skill Flare X DDR4 3200 CL14, thus 4 x 8GB sticks which in my old 3950X build I ran 3733 with FCLK and UCLK at 1866mhz. It was perfectly stable TM5 or Karhu memtest up to 20 000%. At present my system won't even boot if I set the memory, fclk or uclk at that speed. The highest I can go is 3600 CL16, 15, 15 30 1T and it is stable.

I did run 3800 with 1900 fclk and uclk with only two sticks but for some reason Aida64 latency was like 85.


----------



## Dasa

After spending the day tweaking the RAM in the new BIOS this is where it is at.
1986IF 3973c16 1.49v set (1.5-1.512v reported) 52.2ns
I am just ignoring the 1500 WHEA errors in HWiNFO for now.
VSOC ect. are all tuned to there lower limits.
TRCD could go a notch lower if I removed the one dud stick.


----------



## Jackalito

Alyjen said:


> Ram alone is 1.4V and it's passing all sort of memory focused tests so timings/voltage are fine.


Thanks!


----------



## craxton

after random restarts no error codes no bsod, i finally got stable with this. any suggestions or does this look "good enough for daily driven" dram voltage is 1.41 llc is at 2 which is flatlined on my board...perhaps all msi boards? HCI also passed overnight without errors.
also why is zen + write speeds so much greater than zen 2? can someone explain? same ram speed only quite a bit looser timings on zen+ over zen 2 (1600af specifically) ALSO how are you guys getting hwinfo to show errors? all i can see in errors in windows errors which always stays at 0 until i start killing stuff in task man for benchmarks.....??


----------



## MACHWC

This is a 2x16GB kit of Hynix CJR-VKC (according to Taiphoon) so possible DJR.

I am running it at 1.32-1.33V because it is ungodly hot once overvolted at all. It would however do CL17 at these timings with 1.38V.

As it is I'm quite satisfied by these results, but I'm interested is a second pair of eyes, is there anything in the secondary or tertiary timings that I've missed or am doing wrong?

tCWL will fail at 14 and yes I realize tRC should have been 59, oops.

Thank you


----------



## munternet

Hi
I have a question or 2
A friend is setting up a new PC with a 5600x, B550 Aorus Master and some G.Skill Trident Z RGB F4-3200C14D-16GTZR 16GB (2x8GB) DDR4, 3200MHz, 14-14-14-34, 1.35v
Is this a good choice of memory for the platform compared to the Neo and what overclock would he expect to get easily?
Cheers
I should add that he hasn't overclocked memory for a very long time and doesn't want to spend too much time learning but will follow some simple steps 
I haven't done anything with AMD yet but it looks like the time is near


----------



## Dasa

munternet said:


> 3200MHz, 14-14-14-34, 1.35v
> Is this a good choice of memory for the platform compared to the Neo and what overclock would he expect to get easily?


3200c14 is a good choice for someone that wants to OC but with a bit cheaper MB he could get a 2x16GB kit of Flare X 3200c14 without the RGB for the same total cost.
3600c15\3733c16 should be easy enough. Maybe 3600c14\3800c15 with some luck and time spent.
4000c16 may be possible with future BIOS.
Just following settings suggested by Ryzen DRAM calc would be a good starting point that has a fair chance of success and will bring much better performance than XMP.


----------



## Keith Myers

Should be a piece of cake for a simple overclock to 3600Mhz with ease. That is the same memory I run (without the RGB) at 3600 and 14-15-14-14-28-42 and 1.4V using the Ram Calculator settings. I run those setting on a 3950X and 3900X. Should be easier on Ryzen 5000 I would think.
Others have made those run at 3800Mhz.


----------



## Dasa

So I set 1966MHz and 102BCLK for 2006IF and it doesn't get the latency penalty seen with setting 2000IF directly on the GB B550 Aorus Pro.
Also it seems 2000IF set performs ~1ns better with GDM enabled while lower frequency tested seem to perform as good or ~0.5ns better with 2T GDM disabled.


----------



## DeusM




----------



## KedarWolf

I'm going to experiment and try something. Set my RAM at a lower divider like 2666MHz with the timings on Auto, reboot. Then set it at the 3800MHz I run it at with RAM Fast Boot on and the timings I use.

I know you can do it on Z390 to trick the motherboard to use lower RTLs and IOLs and it might lower some hidden and third timings I can't tweak in BIOS, thus reducing my latency.

Will try in a few hours when I'm home from work.


----------



## Muqeshem

KedarWolf said:


> I'm going to experiment and try something. Set my RAM at a lower divider like 2666MHz with the timings on Auto, reboot. Then set it at the 3800MHz I run it at with RAM Fast Boot on and the timings I use.
> 
> I know you can do it on Z390 to trick the motherboard to use lower RTLs and IOLs and it might lower some hidden and third timings I can't tweak in BIOS, thus reducing my latency.
> 
> Will try in a few hours when I'm home from work.


Hello

Are you going to buy a z490 with the new 11gen intel cpus ?
Also, you are still using A.42 beta modded ? correct ?
What was the lowest latency you got with system being stable ?

Those new ryzen cpus can easily achieve 55ns in latency and they boost really high, they made all ryzen 3000 series lackluster


----------



## LionAlonso

DeusM said:


> View attachment 2467906


Hi;
You need that high proc ODT? U can try to lower it a bit.


----------



## LionAlonso

Can anyone help me with L3 cache write vs speed difference? i have read that is vsoc unstable but in every stress test its okay...








==> difference (more than about 20GB/s) in READ vs. WRITE in LvL3 cache = SOC voltage wrong 
Thanks in advance!


----------



## DeusM

LionAlonso said:


> Hi;
> You need that high proc ODT? U can try to lower it a bit.


It was the first thing i did after it! down to 43


----------



## LionAlonso

DeusM said:


> It was the first thing i did after it! down to 43


how about 40? u didnt get it stable?


----------



## craxton

munternet said:


> Hi
> I have a question or 2
> A friend is setting up a new PC with a 5600x, B550 Aorus Master and some G.Skill Trident Z RGB F4-3200C14D-16GTZR 16GB (2x8GB) DDR4, 3200MHz, 14-14-14-34, 1.35v
> Is this a good choice of memory for the platform compared to the Neo and what overclock would he expect to get easily?
> Cheers
> I should add that he hasn't overclocked memory for a very long time and doesn't want to spend too much time learning but will follow some simple steps
> I haven't done anything with AMD yet but it looks like the time is near


ive not got the same kit your speaking about but my tforce kit is 3200c14,14,14,31 i managed 3800 16,15,15,15,32,36 with some other timings being altered (on a 3600XT). 1.4volts. stable. i agree with the other fellow said to you. my 5600x is supposed to be here by tuesday. will see if it doesnt magically get lost in the mail bc that happens ALOT where i live at unfortunately.

here is a screenshot of my timings. started with typhoon and exported my xmp profile to html then used dram calc and imported it started at 3600 c14 almost stable to stable then seen or read alot on here and tried 3800mhz and got stable


http://imgur.com/3HUsgsE


----------



## craxton

i also have my own question to which i tried or thought i tried to post the other day but i think it said the site was under maintenance of some sort? but anyhow, where are these error reports in HWinfo are you lot speaking of? is it just the WHEA errors or? asking anyone who understands what im asking lol


----------



## Spectre73

LionAlonso said:


> how about 40? u didnt get it stable?


Ok, why go lower if everything is stable. What are the advantages?


----------



## Dasa

craxton said:


> where are these error reports in HWinfo are you lot speaking of?


Look for the red text in the top left of HWiNFO reported as errors but if you look in windows logs they are WHEA errors.
Got a heap of them while givving y-cruncher a run and the CPU would hit 93c in a instant between tests before power limits had a chance to kick in dropping it back down to ~70-80c










I haven't noticed a effect on stability or performance from them but they probably are having a small impact on something.

Also took out two sticks and had a play cant get under 50ns with any degree of stability but 50.9ns is getting close.
1966IF @ 104 BCLK = 2045.5IF
4090c16-17









As for single vs dual rank performance at the same speed.

TimeSpy
Not the most sensitive program to RAM speed but it is fairly easy to test with relative consistency.

Dual rank 2.68% faster on average 3.47% max difference.
CPU score
13622
13681
13679

Single rank
CPU score
13453
13222
13234


----------



## VPII

At present I have two sets of G-Skill Flare X 2 x 8bg DDR4 3200 CL14 thus 4 x 8GB for 32gb of ram. Now I have never checked for WHEA errors as I only test my memory to see that it passes 20 cycles of TM5 or 15000 to 20000% running Kharu Memtest. However, since running the 5950X I am limited to 3600 memory and previously with my 3950X I could run 3733 all day long without an issue. I did try with only two sticks and I can do 3800 with 1900 fclk and uclk but performance is really bad, I mean Aida64 latency as in 85 or 86 where it should actually be much better.

I did however see after testing TM5 at 3600 and it passed that I was like sitting with 100's of WHEA errors. How does that work? If I run the memory at 3200 then I do not get any WHEA errors, but the moment I increase it, only be a little I get WHEA errors?

Can someone please explain to me what I am missing?


----------



## DeusM

VPII said:


> At present I have two sets of G-Skill Flare X 2 x 8bg DDR4 3200 CL14 thus 4 x 8GB for 32gb of ram. Now I have never checked for WHEA errors as I only test my memory to see that it passes 20 cycles of TM5 or 15000 to 20000% running Kharu Memtest. However, since running the 5950X I am limited to 3600 memory and previously with my 3950X I could run 3733 all day long without an issue. I did try with only two sticks and I can do 3800 with 1900 fclk and uclk but performance is really bad, I mean Aida64 latency as in 85 or 86 where it should actually be much better.
> 
> I did however see after testing TM5 at 3600 and it passed that I was like sitting with 100's of WHEA errors. How does that work? If I run the memory at 3200 then I do not get any WHEA errors, but the moment I increase it, only be a little I get WHEA errors?
> 
> Can someone please explain to me what I am missing?


Post up timings and Voltages, Also check bios to make sure your updated.


----------



## VPII

DeusM said:


> Post up timings and Voltages, Also check bios to make sure your updated.


Thanks you. I've updated to the latest official, tried the beta but not sure if it is all that good. Will try it again now and see if it changes. As for the rest, all stock and good.


----------



## VPII

DeusM said:


> Post up timings and Voltages, Also check bios to make sure your updated.


Thanks for the bios suggestion, tried two sticks with latest bios 3600 CL 16 and no WHEA errors. Seem to be working well. I'll try 3733 and 3800 with this bios to see if it works.


----------



## Comalive

LionAlonso said:


> Can anyone help me with L3 cache write vs speed difference? i have read that is vsoc unstable but in every stress test its okay...
> View attachment 2468022
> 
> ==> difference (more than about 20GB/s) in READ vs. WRITE in LvL3 cache = SOC voltage wrong
> Thanks in advance!


One thing to note is that the results vary widely between runs, just start the L3 test a couple of times and you will see. The other test also vary but not as much relative to the achieved speeds.
I have also read the post about finding SoC voltage by looking at L3 speeds, however, looking at the huge run to run variances makes this method quite useless imo. More importantly, what you actually need is a voltage that makes your system survive stress tests, only after that fine tuning makes any sense.
And on top of that, your speeds are better than mine by quite a bit already so I don't think you need to worry about those.


----------



## Dasa

Loading windows in diagnostic mode will reduce the run to run variance significantly since it is very sensitive to background processes.


----------



## craxton

Dasa said:


> Look for the red text in the top left of HWiNFO reported as errors but if you look in windows logs they are WHEA errors.
> Got a heap of them while givving y-cruncher a run and the CPU would hit 93c in a instant between tests before power limits had a chance to kick in dropping it back down to ~70-80c
> 
> 
> 
> thats just the thing tho, there isnt any red flavored text at the top. in fact the only flavored text period in hwinfo is what i set to stand out easier. although hwinfo does show at the bottom WHEA just not read and never any errors. showing top which shows version i have is different from yours, trying the beta version just freezes and doesnt run nor will task manager kill the process? and showing the bottom which shows WHEA
> 
> EDIT: NEVERMIND now i see. i got it. you simply moved yours to the top and changed the color to red. or thats what i believe youve done. which is what was confusing me.just currently about 4 days ago got my ram oc stable....and now im waiting for a 5600x to come in hopefully itll be here later today (monday) or latest tuesday. anyhow thanks for the response.


----------



## VPII

DeusM said:


> Post up timings and Voltages, Also check bios to make sure your updated.


Sorry for quoting you so many times. I actually got 3800 mem with 1900 fclk and uclk working now and stable so all good.


----------



## craxton

Dasa said:


> Loading windows in diagnostic mode will reduce the run to run variance significantly since it is very sensitive to background processes.


ok, now that wave established i know where the WHEA tab is and what its for, what fft size for prime 95 and what settings are you guys using in y cruncher for stressing stability?


----------



## Comalive

craxton said:


> ok, now that wave established i know where the WHEA tab is and what its for, what fft size for prime 95 and what settings are you guys using in y cruncher for stressing stability?


Start y-cruncher and then press 1, 7 and Enter.


----------



## mus1mus

B-Die from 2016...
GDM OFF
TRCDRD 18 is the key.

Waiting for AGESA Update to open up the FCLK 1900 Limit.


----------



## KedarWolf

mus1mus said:


> B-Die from 2016...
> GDM OFF
> TRCDRD 18 is the key.
> 
> Waiting for AGESA Update to open up the FCLK 1900 Limit.
> 
> View attachment 2468457


No newer BIOS like what the Unify has for the Godlike either.


----------



## jomama22

mus1mus said:


> B-Die from 2016...
> GDM OFF
> TRCDRD 18 is the key.
> 
> Waiting for AGESA Update to open up the FCLK 1900 Limit.
> 
> View attachment 2468457


 That's just single rank yeah? Find the secret for dual rank and then you'll be a hero.


----------



## craxton

Comalive said:


> Start y-cruncher and then press 1, 7 and Enter.


gotcha is that on the newest download available? first time using y-cruncher for anything.


----------



## mus1mus

jomama22 said:


> That's just single rank yeah? Find the secret for dual rank and then you'll be a hero.


Yeah? 

Send me your Dual Rank B-Dies and I will.


----------



## jomama22

mus1mus said:


> Yeah?
> 
> Send me your Dual Rank B-Dies and I will.


Lol plenty out there to buy bud


----------



## mus1mus

jomama22 said:


> Lol plenty out there to buy bud


LOL then command yourself to discover the secret sauce to GDM OFF on your Dual Rank Sticks and post it here and I'll call you the HERO.


----------



## jomama22

mus1mus said:


> LOL then command yourself to discover the secret sauce to GDM OFF on your Dual Rank Sticks and post it here and I'll call you the HERO.


That is not the type of torture I enjoy


----------



## mus1mus

You are a funny guy.


----------



## martin28bln

Does anybody have tested IF>1900 with newer Asus 3001 Bios Version. Thinking about to flash...still running IF1900 3800CL16 with 5950x and X570 Asus ITX


----------



## quarx2k

Hello guys. 
My ram is 2x F4-3200C14-16GTZ (dual rank) 
3800 CL14 and 1900FCLK, 1.504v. Board: Asus C8H Wi-fi with 3950x

Can anyone tell me, whats wrong with my timings or settings? I can't go below 63.5ns. Also tested on clean OS, latency the same =(
More details in attachments 
Thanks.


----------



## Alyjen

I don't think it's that easy for Zen 2 to go under 60ns. Most people posting results between 52-54ns are doing it with Zen 3 processors. I have 54ns with 3800CL16 on 5800X


----------



## quarx2k

Alyjen said:


> I don't think it's that easy for Zen 2 to go under 60ns. Most people posting results between 52-54ns are doing it with Zen 3 processors. I have 54ns with 3800CL16 on 5800X


I want at least 62 or 61ns. But no idea how others do it on 3950 with dual ranks. In this spreadsheet Zen RAM Overclocking


----------



## Alyjen

quarx2k said:


> I want at least 62 or 61ns. But no idea how others do it on 3950 with dual ranks. In this spreadsheet Zen RAM Overclocking


Have you checked for WHEA errors or warnings? If you have some instability at higher FCLK then it'll pass benchmarks but performance may be lower than expected. Other than that my experience with Zen 2 is rather limited.


----------



## quarx2k

Alyjen said:


> Have you checked for WHEA errors or warnings? If you have some instability at higher FCLK then it'll pass benchmarks but performance may be lower than expected. Other than that my experience with Zen 2 is rather limited.


No WHEA errors or warnings. Everything is stable.


----------



## craxton

well finally got my 5600x and i be dammed if i didnt drop the mfr and bend like 5 pins but needless to say that wasnt the first time thats happened with bent pins. first time dropping amd mounting sucks and the ek aio pulls it out of socket (3600xt) but didnt bend none this time around... anyhow booted no problem on the same bdie kit ive been using with my 3600xt no bar support of nothing msi mpg gaming edge wifi board, dont have amd 6 series gpu to try a newer bios so this is where ill probably stay unless someone has a better reason to go on forwards with bios updates....and no this inst tested just showing i literally just tried it and it worked with a preset and fclk 2000. THIS IS ALL AUTO remember that so if this cpu is anything like my 3600xt in ram and loving bdie these will hopefully go down quite a bit.


----------



## craxton

well as i stated id try my old settings as a base, and wow this thing runs WAY cooler than a 3600xt at the same frequency. perhaps due to way less voltage? idk but none the less.... any care to tell me where i should try to improve on this? cldo and iod are still on auto as im not familiar with this cpu.


----------



## VPII

I've been playing around with the 5950X for a while but could not get my memory to run higher than 3600 but even with that a lot of WHEA errors until a member here told me to try the latest bios and upon doing so I can happily run 3800mem with 1900 FCLK and UCLK.


----------



## Alyjen

@craxton 
Nice scores! FCLK 2000MHz without any errors is always impressive  your VDDG VDDP voltages seems rather high (and VSOC rather low), but if that's what your mobo things you need to run this frequency then maybe it's correct  looking forward to more info on how is the stability and performance. Before current BIOS update (AGESA 1.1.8.0.) I thought I have stable platform but any large fft stress test (prime/occt) could generate whea warnings within minutes.


----------



## craxton

Alyjen said:


> @craxton
> Nice scores! FCLK 2000MHz without any errors is always impressive  your VDDG VDDP voltages seems rather high (and VSOC rather low), but if that's what your mobo things you need to run this frequency then maybe it's correct  looking forward to more info on how is the stability and performance. Before current BIOS update (AGESA 1.1.8.0.) I thought I have stable platform but any large fft stress test (prime/occt) could generate whea warnings within minutes.


nah all voltages on this board in particular have been high. i just didnt go check and see what i should tune it too. cyberpunk released and well ya it was stable so i was up until 8a.m. this morning playing lol....gonna see about getting it down now. to be honest my 3466 kit does way better reads and writes at looser timings, and i dont understand that logic its micron j i do believe?
but seeing as to how the board does believe 3800 gdm off is achievable i tried it and well had to check error reports myself manually bc i wasnt sure if all the windows **** i killed wasnt reporting and well its working not sure if its telling HWinfo about them but there isnt any from windows itself only from games i force closed a few days past.... im also wondering if ANYONE has FTPM working on these chips as mine IS NOWHERE to be seen when turning it on in bios its MIA and i cant find jack about it anywhere...but all in all 3800 gdm off vs 4000 gdm on both stable even in prime95 128ffts (followed buildzoids directions in a few vids and thats what he did) so im unsure if im using prime correctly or not to even push it hard enough. but its stable 4.6ghz 1.25 volts, 1.4v on the ram on 4000 or 3800. so far im happy. havent tried any newer bios, which may be my cause of no tpm support but im unsure about that? as my current bios has bar support options inside the bios but running a 2070s i dont see the point in touching the settings there. (perhaps where i noobed out and dropped the cpu and bent more than a fair share of pins when installing the cpu it said bye bye to the tpm? idk i got em straightened out the best i could but 3 of them actually bent enough to curve them in which i couldnt straighten all the way out without fear of them coming all the way off. SAD SAD SAADDD. i cant blame it on amds mounting this time as the ek aio ripped out my 1600af and caused the same thing only 3 pins bent there but those are fine and you cant tell it happened. it even pulled out the 3600XT but nothing bad happened....this time its all on my for being to excited and dropping it right on the pcie slot ugh i still cant believe i did that. but none the less all is working fine. minus TPM????


----------



## craxton

Veii said:


> This is the difference between GDM ON & GDM OFF 2T
> 2T is faster than 1.5T
> On top of that it wipes odd primaries autocorrection
> Keep working on CAD BUS -> ClkDrvStrength, till you find a strong enough impedance setting for your memory kit to run GDM off
> 
> View attachment 2467105
> View attachment 2467106
> 
> 
> Lower looking boost ~ but that's the powerplan
> Lazy CL16 flat timings @ 1.46v but i've poste them here already to replicate
> Still stock boost no special tweaks , ust around it optimisations
> Stepped up to humane cooling away from the Wraith Stealth
> But i'm again since 22h awake zZZ
> Tomorrow the 50ns wall will be gone. Still have a lot of headroom & PBO let to play with
> Toyed enough the last couple of days with lame scores on the stock cooler











considering my recent posts and now having the 5600x installed and running 2000fclk without problems at all besides the fact that my cldo iod and well yea kinda no..IS HIGH...its on auto, so do you have any type of suggestions? the last things i read on vddg voltages from you were on 3000 series chips not 5000....


----------



## Dasa

craxton said:


> cldo iod and well yea kinda no..IS HIGH...its on auto, so do you have any type of suggestions?


Try these V they should work nicely with that level of SOC.
Apparently you want VDDG at least 50mV bellow SOC and CLDO 50mV bellow VDDG.
So that is 1.1v SOC for me but 1.05v SOC should work fine with these settings.
VDDP 900mV (quicly runs into post problems if you go to low for current IF)
IOD 1000mV (important for higher IF stability)
CCD 950mV


----------



## dante`afk

waiting to be able to buy a dark hero and test out fclk 2000


----------



## craxton

Dasa said:


> Try these V they should work nicely with that level of SOC.
> Apparently you want VDDG at least 50mV bellow SOC and CLDO 50mV bellow VDDG.
> So that is 1.1v SOC for me but 1.05v SOC should work fine with these settings.
> VDDP 900mV (quicly runs into post problems if you go to low for current IF)
> IOD 1000mV (important for higher IF stability)
> CCD 950mV


(EDIT) figured out that theres an actual ram test in prime... which is what im running now testing all well selected blend mode or whatever that is... as what i was selecting 128/128 wasnt using any ram and im pretty sure only hit the cpu... 

thanks, i wasn sure if it would be the same for 5800x as 5600x is not the same chip but is the same silicon.... anyhow this is where i ended up.... it would seem my l3 cache could be alot better. but atm cyberpunk has had my attention. running a periodic scan thru cmd sfc/ scannow to make sure nothing pops up and keeping tabs on event viewer as im unsure if hwinfo is able to see my errors at all. as stated i killed alot of tasks windows doesnt need to run. event viewer ect still works yes as i can see that 12:20 today while allowing hci to run overnight it restarted which threw an error. unsure if my ol ladies best friends baby is to blame there tho as she sneaks in here and presses the pretty buttons on my pc lol... but i havent had crashing or anything strange happen other than one crash in CP2077 a little bit ago but no error i believe it to be GOG wanting to update the game...or where i was messing with seeing if i could tell RT was actually doing anything besides cutting frames in hald and more...sure enough tho i could tell a major difference in covered areas ect. (if anyone is interested in playing the game for free lmk) no i paid for my copy but there isnt DRM on any CDPR games so its already being downloaded thru varies sites. aanyhow, gonna run a quick prime stress test then hop back into it. thanks for the help dasa!


----------



## drotaru

Is my RAM OC good or is there something i can do more or maybe some subtiming weirdly set? 

got a 3600x and a B450 Tomahawk max, mem vid is at 1.42v















seems stable thus far testmem5 extreme custom preset over 1h


----------



## Spectre73

So I could really use a little help in stabilizing my 1900 FCLK on 5800x. No images though, until I am back from work, but it really bothers me, so much so, that I am thinking about it on work - should not do that 

So: System is KARHU stable on 3800/1900 with B-die and fast settings.

Voltages are as follow on a x570 Master (F31o)

vSOC: 1.1 (LLC extreme, because the MB seems to undervolt vSOC quite a bit).
VDDP 900
VDDG IOD: 1050
VDD CCD: 950
rest as most here have it: ProcODT 43, 24-20-24-24 etc....

System is stable with the occasional (correctable) WHEA error (around 2-3) a day.

What bothers me a little bit: my AIDA DRAM latency is wildly fluctuating between 54,8 and up to 57ms (with most background appps closed).
I suspect that the system is on the edge of being unstable and there happens some error correction or whatever in the background. What settings would likely be responsible to stabilize the latency? Or should I just back off my FCLK to 3600?
Any help would be greatly appreciated.


----------



## Alyjen

Try to setup a baseline, when I was fighting my WHEA's at 1900 I found a test that could force them within minutes, OCCT large fft, sse (AVX it's not needed) or Prime95 Large/Blend (also no AVX) or y-cruncher should do.

I suspect, you'll get quite a few of them under heavy load, for me it was 2-3 whea a day but during stress test type of load I had ~2-3 every minute

And.. I tried tons of things and could not fight it entirely, there were some more promising things, like LLC on high/extreme as it allowed me to stick to 1.1V flat, while 1.125V with drop, was more unstable (that's why I mention benchmarks, they allow you to catch minor differences, if you have 1-2 error during 10 minutes run it's better than having 5 in the first minute)

Or putting PBO to ECO mode, which allowed me to run stress tests for hours without a single error, yet after a week of gaming by my son, there were 3 errors recorded..

What eventually helped me the most was new Asus BIOS, based on AGES 1.1.8.0. I could just load up defaults (which are kind of wrong for Asus boards) fire up Prime and it was stable, no WHEA. I'm pretty sure next BIOSes will improve things even further.

Thinks I haven't tried, and just may test in the future is.

Leaving PBO with slight overvolt (set + offset by 0,06V) as some people report that these errors are caused by occasional dips of CPU voltage rather than other things
All core OC, setting something like 4,6GHz with low voltage


----------



## Spectre73

Alyjen said:


> Try to setup a baseline, when I was fighting my WHEA's at 1900 I found a test that could force them within minutes, OCCT large fft, sse (AVX it's not needed) or Prime95 Large/Blend (also no AVX) or y-cruncher should do.
> 
> I suspect, you'll get quite a few of them under heavy load, for me it was 2-3 whea a day but during stress test type of load I had ~2-3 every minute
> 
> And.. I tried tons of things and could not fight it entirely, there were some more promising things, like LLC on high/extreme as it allowed me to stick to 1.1V flat, while 1.125V with drop, was more unstable (that's why I mention benchmarks, they allow you to catch minor differences, if you have 1-2 error during 10 minutes run it's better than having 5 in the first minute)
> 
> Or putting PBO to ECO mode, which allowed me to run stress tests for hours without a single error, yet after a week of gaming by my son, there were 3 errors recorded..
> 
> What eventually helped me the most was new Asus BIOS, based on AGES 1.1.8.0. I could just load up defaults (which are kind of wrong for Asus boards) fire up Prime and it was stable, no WHEA. I'm pretty sure next BIOSes will improve things even further.
> 
> Thinks I haven't tried, and just may test in the future is.
> 
> Leaving PBO with slight overvolt (set + offset by 0,06V) as some people report that these errors are caused by occasional dips of CPU voltage rather than other things
> All core OC, setting something like 4,6GHz with low voltage


Thanks for your reply, greatly appreciated. The WHEA errors do not bother me that much. I really think, they will vanish with later BIOSs. Can you tell me something about the variance with the cache latency? Could an increase in VDDP voltage help (to about 950?) I will try it in about an hour, but I already tried many different things without succes (raising/lowering VDDG, LLC settings, VRM phases) to no avail. I do not remember AIDA to have that much variance.


----------



## Alyjen

Spectre73 said:


> Thanks for your reply, greatly appreciated. The WHEA errors do not bother me that much. I really think, they will vanish with later BIOSs. Can you tell me something about the variance with the cache latency? Could an increase in VDDP voltage help (to about 950?) I will try it in about an hour, but I already tried many different things without succes (raising/lowering VDDG, LLC settings, VRM phases) to no avail. I do not remember AIDA to have that much variance.


it's similar for my setup, usually it hits 54.4 +/- 0.2 ns but once in a while it records above 56, I'm not that much concerned as it's super stable in everything and I don't see any weird drops in fps (taking my rather ancient gpu into consideration) which could indicate that there's something bad going on in the background. 
I'd blame that for antivirus, some auto update tool or other things that I never disable for this sort of testing.
Remember that what people show in net is the best case scenario, hardly anyone is admitting that they had to do 10 runs to get that perfect score


----------



## KedarWolf

40 Cycles of Ollie set to 32 threads. VDDGs are 1.00 and 1.05.


----------



## Alyjen

KedarWolf said:


> 40 Cycles of Ollie set to 32 threads. VDDGs are 1.00 and 1.05.
> 
> View attachment 2468907


TM5 is good to test if your timings are ok (btw pretty sweet timings!) but if you want to check if FCLK is stable you have to use different tester, Prime95, y-cruncher etc. and observe if you have any WHEA warnings


----------



## KedarWolf

Alyjen said:


> TM5 is good to test if your timings are ok (btw pretty sweet timings!) but if you want to check if FCLK is stable you have to use different tester, Prime95, y-cruncher etc. and observe if you have any WHEA warnings


I've ran 1344 FFTs Prime 95 several hours, Linpack Xtreme and y-cruncher with a custom .cfg for AMD Ryzen and they all pass just fine. And I've done it with HWInfo open, no WHEA errors. 

My phone autocorrected .cfg to .veg.


----------



## Alyjen

KedarWolf said:


> I've ran 1344 FFTs Prime 95 several hours, Linpack Xtreme and y-cruncher with a custom .cfg for AMD Ryzen and they all pass just fine. And I've done it with HWInfo open, no WHEA errors.
> 
> My phone autocorrected .cfg to .veg.


ok now I'm jealous  I hope my Zen 3 one day is going to be this stable!


----------



## KedarWolf

Alyjen said:


> ok now I'm jealous  I hope my Zen 3 one day is going to be this stable!


There are 16 people ahead of me at the local store I preordered my 5950x from, I called yesterday. And according to this link (not my store) retailers are supposed to have a lot of stock before the end of December.









AMD Ryzen 5000 CPU Stock Update


Missed out on a 5000 series CPU? New stock is coming in ready for Christmas. Here's where you can get hold of one!




www.wepc.com


----------



## MarcHays

Hi everyone. Guys do you think my AIDA64 scores are okay? I have everything on stock and memory on DOCP. Nothing is tweeked. My score is too low compared to what other here have:










Especially I'm bothered about L3 cache speed. Is there anything wrong with my system?


----------



## Esticbo

MarcHays said:


> Hi everyone. Guys do you think my AIDA64 scores are okay? I have everything on stock and memory on DOCP. Nothing is tweeked. My score is too low compared to what other here have:
> 
> View attachment 2468933
> 
> 
> Especially I'm bothered about L3 cache speed. Is there anything wrong with my system?



All is ok, l3 speed is a problem of latest asus bios, if you have all the setting in auto 😔


----------



## Veii

Edit [updated picture]








Soo, i've maxed out the platform,
It makes no sense to push Freq nor to run 2100 when i'm artifically slowed down by this Bios & ABL
(not possible to go sub sub 50ns at any frequency or FCLK)
Nor can i run higher than 115 EDC [PBO] where memory cuts into power reserves too , not only boost 

Still looking for a new bios or better ABL. Patch C is useless for me so far

Down bellow is a demonstration of autocorrection in 8:1 mode 
Fabric also works at 2133, 2167 i can not get to work
You can see how much it slows itself down ^^#


----------



## KedarWolf




----------



## Nighthog

@Veii did you try more VDDG_IOD or more SoC voltage?

I know on 3800X @ 1933FCLK if both were not high enough it would "slow" down.
Same on 4650G, too little SoC voltage for the FCLK frequency you boot into ~slow~ again. 

The slowdown might prevent errors but when you increase the voltage and it runs "proper" it might be unstable and needs more work to stabilize.


----------



## Dasa

Extra V may help in some situations but there is also points in the BIOS where when you reach a certain IF performance plummets and if you lower the set IF and surpass it using BCLK then performance is still great which goes to show it is the BIOS setting not the actual IF clock speed that is the problem.
But 287.5ns! dam I thought my 6ns higher when set to 2000IF was bad.


----------



## Veii

Nighthog said:


> @Veii did you try more VDDG_IOD or more SoC voltage?
> 
> I know on 3800X @ 1933FCLK if both were not high enough it would "slow" down.
> Same on 4650G, too little SoC voltage for the FCLK frequency you boot into ~slow~ again.
> 
> The slowdown might prevent errors but when you increase the voltage and it runs "proper" it might be unstable and needs more work to stabilize.


There is just a bug which puts it into 2:1 mode, later even in 4:1
Here some other missfortuned score


Spoiler














Although you are right on the SOC part - as i got at the end 2100 FCLK usable stable

But there are other issues which prevent me to go beyond
On stock the best i got is 50.8ns under 2000 1:1
Or with PBO 10.5 at 1900

The issue is, 3 things prevent me to go further:

Old ABL is nice but SMU sometimes turns into 2:1 mode out of random on 2100
50ns is the absolute lowest i can get , doesn't matter if with harsh timings or just boost perf (4200C16=3800C14)
unclear how intentional, but there is an PBO EDC lock of 115A ~ there is no way how i can pass it which limits my max boost

Tried many things, but the CPU intentionally slows itself down for whatever reason between different FCLKs
And the EDC powertarget bothers me strongly ~ usually 4.95 should run but i'm hardlocked on many tests at 4.75-4.65 because of the powerlock

Well 50.1 is already hard to beat, and okeish in single thread R20 ~ 635ish & 1626p R23


----------



## Nighthog

The EDC hard limit was there in 3000 series, only way to "disable" it was the EDC Bug.
Basically the PBO EDC setting only adjusted non-AVX instruction loads. Did nothing when you used AVX instructions, HARD CODE limit not adjustable for AVX on EDC.
This really means PBO = useless! It's not real OC without limits, artificial AMD limits are still in play.

Sadly they "fixed" it for newer processors... no more bug to be "utilized"

I can't adjust any of the EDC, TDC, PPT limits on my 4650G... not higher, only lower the limits. Higher limits are ignored & keep using the stock values.
I don't even have the +200 AUTOOC setting available! (hard capped @ stock 4.3Ghz)

UEFI/BIOS limits everywhere on these "unlocked" AMD processors. 

*NO ONE NOTICES! The gimps the utter crapload of artificial gimps put in place!* They won't allow you to play outside the "fenced garden" they have made.


Veii said:


> There is just a bug which puts it into 2:1 mode, later even in 4:1
> Here some other missfortuned score
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2469018
> 
> 
> 
> Although you are right on the SOC part - as i got at the end 2100 FCLK usable stable
> 
> But there are other issues which prevent me to go beyond
> On stock the best i got is 50.8ns under 2000 1:1
> Or with PBO 10.5 at 1900
> 
> The issue is, 3 things prevent me to go further:
> 
> Old ABL is nice but SMU sometimes turns into 2:1 mode out of random on 2100
> 50ns is the absolute lowest i can get , doesn't matter if with harsh timings or just boost perf (4200C16=3800C14)
> unclear how intentional, but there is an PBO EDC lock of 115A ~ there is no way how i can pass it which limits my max boost
> 
> Tried many things, but the CPU intentionally slows itself down for whatever reason between different FCLKs
> And the EDC powertarget bothers me strongly ~ usually 4.95 should run but i'm hardlocked on many tests at 4.75-4.65 because of the powerlock
> 
> Well 50.1 is already hard to beat, and okeish in single thread R20 ~ 635ish & 1626p R23
> View attachment 2469020


----------



## Veii

Dasa said:


> Extra V may help in some situations but there is also points in the BIOS where when you reach a certain IF performance plummets and if you lower the set IF and surpass it using BCLK then performance is still great which goes to show it is the BIOS setting not the actual IF clock speed that is the problem.
> But 287.5ns! dam I thought my 6ns higher when set to 2000IF was bad.


Try 1966 with 102 BLCK ~ should round up to 4000 MCLK 1:1 . . . so you can check i the 2:1 enforcement happens (10ns penalty)
Between 1933 (54.1ns) & 2000 (51.9ns) it's about a 2ns difference @ stock
Usually it's a bit wrong as both here where tested with the same timings - i should have dropped primaries by -1 on 1933 to match it

Really hard to give an exact scaling when even the Power-Headroom changes Aida64 results
But around 2.5-3ns should be the difference on 2 steps higher FCLK

If it isn't, some artificial slowdown is in place somewhere
Voltage, resistance, instability are the cause for that
Else Zen3 is pretty reliable with nearly no "testing tolerances" between runs


----------



## Veii

Nighthog said:


> The EDC hard limit was there in 3000 series, only way to "disable" it was the EDC Bug.
> Basically the PBO EDC setting only adjusted non-AVX instruction loads. Did nothing when you used AVX instructions, HARD CODE limit not adjustable for AVX on EDC.
> This really means PBO = useless! It's not real OC without limits, artificial AMD limits are still in play.
> 
> Sadly they "fixed" it for newer processors... no more bug to be "utilized"
> 
> I can't adjust any of the EDC, TDC, PPT limits on my 4650G... not higher, only lower the limits. Higher limits are ignored & keep using the stock values.
> I don't even have the +200 AUTOOC setting available! (hard capped @ stock 4.3Ghz)
> 
> UEFI/BIOS limits everywhere on these "unlocked" AMD processors.
> 
> *NO ONE NOTICES! The gimps the utter crapload of artificial gimps put in place!* They won't allow you to play outside the "fenced garden" they have made.


The EDC bug still works
But due to how the boosting autocorrects and slows itself down - beginning from cache to IF speed
It's not usable anymore
It puts you in a full throttle state and hits >120 Inter-Core latency

I have to find the report of mine where i discussed it ~ but it's useless on this gen 

The hardcap is mostly in ABL & on Renoir it should be also in GOP
GOP can be swapped and was updated recently for Renoir
I remember Reous got quite some crazy scores with it (2600 FCLK)

I need to see how to port over either the current old ABL 09084010 to Patch-C
or contact @stasio and beg for support in figuring out which new ABL works well with SMU 56.34 ala Patch-C
Well maybe even telling me near/at which GUID the ABL sits to transplant it
Saw people move in the 2000CLK region with current ABL
~ but seing how open 09084010 is - i'm unsure how things will develope

Certainly can recognize the lockown to prevent WHEA & PCIe dropout issues ~ making the platform appear more stable
Kinda unfortunate that we enthousiasts have no "unlock" option there
Not even the LN2 mode is really free and continues with the same lockdowns :/
Haven't seen even one WHEA error


----------



## Nighthog

Veii said:


> The EDC bug still works
> But due to how the boosting autocorrects and slows itself down - beginning from cache to IF speed
> It's not usable anymore
> It puts you in a full throttle state and hits >120 Inter-Core latency
> 
> I have to find the report of mine where i discussed it ~ but it's useless on this gen
> 
> The hardcap is mostly in ABL & on Renoir it should be also in GOP
> GOP can be swapped and was updated recently for Renoir
> I remember Reous got quite some crazy scores with it (2600 FCLK)
> 
> I need to see how to port over either the current old ABL 09084010 to Patch-C
> or contact @stasio and beg for support in figuring out which new ABL works well with SMU 56.34 ala Patch-C
> Well maybe even telling me near/at which GUID the ABL sits to transplant it
> Saw people move in the 2000CLK region with current ABL
> ~ but seing how open 09084010 is - i'm unsure how things will develope
> 
> Certainly can recognize the lockown to prevent WHEA & PCIe dropout issues ~ making the platform appear more stable
> Kinda unfortunate that we enthousiasts have no "unlock" option there
> Not even the LN2 mode is really free and continues with the same lockdowns :/
> Haven't seen even one WHEA error


X570 Xtreme says SMU: *55.73.00* on *F31* BIOS for me.
2500-2600FCLK how? I can't get it to get into windows @ 2300FCLK, just reboots on startup load.
Memtest86+ on USB returns lots of errors that I can't fix with any reasonable settings.
Golden binning needed for such FCLK? Or only LN2 like scenarios?

WHEA? I've not seen those in quite a while either. 3000 series launch month?


----------



## Veii

Nighthog said:


> X570 Xtreme says SMU: *55.73.00* on *F31* BIOS for me.
> 2500-2600FCLK how? I can't get it to get into windows @ 2300FCLK, just reboots on startup load.
> Memtest86+ on USB returns lots of errors that I can't fix with any reasonable settings.
> Golden binning needed for such FCLK? Or only LN2 like scenarios?
> 
> WHEA? I've not seen those in quite a while either. 3000 series launch month?


Do you have access to an AMD PBS menu before AMD CBS
"AMD Firmware" section,
listing ABL, GOP, SMU there

Oh it wasnt Reous
It was Icky from HardwareLuxx i think








AMD RAM overclocking


ZEN 2 - Matisse (7nm TSMC) s name,latency,FCLK,MT/s,timings,DIMMS,IC-type,part number,read,write,copy,VSOC,VDDG,VDIMM,VDDP,ProcODT,RTT,stability test,CPU,mainboard Reous,57,5 ns,1900 Mhz,3800 Mhz,<a href="https://abload.de/image.php?img=380014-14-13-1310000kzbkdb.png">14-13-14-13-30-44-247</a>...




docs.google.com


----------



## Nighthog

Veii said:


> Do you have access to an AMD PBS menu before AMD CBS
> "AMD Firmware" section,
> listing ABL, GOP, SMU there
> 
> Oh it wasnt Reous
> It was Icky from HardwareLuxx i think
> 
> 
> 
> 
> 
> 
> 
> 
> AMD RAM overclocking
> 
> 
> ZEN 2 - Matisse (7nm TSMC) s name,latency,FCLK,MT/s,timings,DIMMS,IC-type,part number,read,write,copy,VSOC,VDDG,VDIMM,VDDP,ProcODT,RTT,stability test,CPU,mainboard Reous,57,5 ns,1900 Mhz,3800 Mhz,<a href="https://abload.de/image.php?img=380014-14-13-1310000kzbkdb.png">14-13-14-13-30-44-247</a>...
> 
> 
> 
> 
> docs.google.com


No AMD PBS isn't visible for gigabyte standard BIOS.


----------



## Alyjen

Esticbo said:


> All is ok, l3 speed is a problem of latest asus bios, if you have all the setting in auto 😔


hmm for me it's exact opposite, I have noticeable higher scores with new BIOS


----------



## Veii

Alyjen said:


> hmm for me it's exact opposite, I have noticeable higher scores with new BIOS
> View attachment 2469039


This is rom one user on the gigabyte beta bios page








With latest ABL on same Patch-C SMU , they not only increased the FCLK limits (away from 1900)
but finally started to use the 2nd CCD - for full cache bandwidth access

It's only EDC limited 
The question is ust , which ABL version is this


----------



## Alyjen

Veii said:


> This is rom one user on the gigabyte beta bios page
> View attachment 2469049
> 
> With latest ABL on same Patch-C SMU , they not only increased the FCLK limits (away from 1900)
> but finally started to use the 2nd CCD - for full cache bandwidth access
> 
> It's only EDC limited
> The question is ust , which ABL version is this


Oh my, that's faster! And it's only 5600X so I don't really get it.. 
also what's ABL? you got me lost here  my result is with SMU 56.37.00 AGESA 1.1.8.0.


----------



## Esticbo

Alyjen said:


> hmm for me it's exact opposite, I have noticeable higher scores with new BIOS
> View attachment 2469039


I've problems with l3 cache (all setting in auto and clear cmos....)


----------



## Alyjen

Esticbo said:


> I've problems with l3 cache (all setting in auto and clear cmos....)
> 
> View attachment 2469098
> View attachment 2469102


yea but have you tried other benchmarks? something that would scale pretty good with memory? this may be some AIDA bug, I like to use Geekbench 5 for memory, it scales pretty good (base settings ~9500 points, after memory tuning 10700)


----------



## MarcHays

I had a problem with L3 cache too. I don't know how I fixed it. But after removing Ryzen Master and full CMOS I seems to be having L3 results on pair with users from previous page. Not sure what was the problem: software or hardware bug.


----------



## craxton

craxton said:


> thanks, i wasn sure if it would be the same for 5800x as 5600x is not the same chip but is the same silicon.... anyhow this is where i ended up.... it would seem my l3 cache could be alot better. but atm cyberpunk has had my attention. running a periodic scan thru cmd sfc/ scannow to make sure nothing pops up and keeping tabs on event viewer as im unsure if hwinfo is able to see my errors at all. as stated i killed alot of tasks windows doesnt need to run. event viewer ect still works yes as i can see that 12:20 today while allowing hci to run overnight it restarted which threw an error. unsure if my ol ladies best friends baby is to blame there tho as she sneaks in here and presses the pretty buttons on my pc lol... but i havent had crashing or anything strange happen other than one crash in CP2077 a little bit ago but no error i believe it to be GOG wanting to update the game...or where i was messing with seeing if i could tell RT was actually doing anything besides cutting frames in hald and more...sure enough tho i could tell a major difference in covered areas ect. (if anyone is interested in playing the game for free lmk) no i paid for my copy but there isnt DRM on any CDPR games so its already being downloaded thru varies sites. aanyhow, gonna run a quick prime stress test then hop back into it. thanks for the help dasa!
> View attachment 2468858





Veii said:


> Edit [updated picture]
> View attachment 2469009
> 
> Soo, i've maxed out the platform,
> It makes no sense to push Freq nor to run 2100 when i'm artifically slowed down by this Bios & ABL
> (not possible to go sub sub 50ns at any frequency or FCLK)
> Nor can i run higher than 115 EDC [PBO] where memory cuts into power reserves too , not only boost
> 
> Still looking for a new bios or better ABL. Patch C is useless for me so far
> 
> Down bellow is a demonstration of autocorrection in 8:1 mode
> Fabric also works at 2133, 2167 i can not get to work
> You can see how much it slows itself down ^^#
> View attachment 2468962


(EDIT) dont try patch D1 i couldnt FOR ANYTHIG even at super loose timings get my chip to post 2000fclk. i have now switched back to version C and before allowing the memory to boot or train i straight tried 4000/2000fclk with auto mem try it timings on msi boards. needless to say that worked no issues...

have you tried patch D1? I'm almost positive its by far superior for overclocking ram than that of patch C. speaking of which patch C for whatever reason had issues with initialization of the fTPM module in bios let alone windows believing the 5600x has one.... took me forever to decide to try patch D1 beta bios. but glad i did. max cpu boost frequency of 4.7ghz. all well under temp threshold at that. only running 3600fclk due to not wanting to stress and test and stress and test due to a certain game releasing but 2000fclk was easy done upon first boot. was running 2000 fclk 4000 on 16,15,15,15,32,36 timings. (bdie kit from teamgroup)


----------



## craxton

Esticbo said:


> I've problems with l3 cache (all setting in auto and clear cmos....)
> 
> View attachment 2469098
> View attachment 2469102


by problem i think you mean high latency? i too have the same issue...didnt know it was an actual issue tho....


----------



## Esticbo

craxton said:


> by problem i think you mean high latency? i too have the same issue...didnt know it was an actual issue tho....


The problem is the speed of l3 cache, if I change some settings in amd overclocking can had this:










The bios 1401 have agesa v2 pi 1.1.8.0 and PBO 2

AGESA V2 PI 1.1.8.0 formal release (non BETA)- Zen 3 / Ryzen 5000 Series CPU Support


----------



## craxton

by seeing this, id have to believe its best for no matter what your doing especially ram overclocking minus R23... for one to allow PBO to do the overclocking automatically? (the voltages you see in hwinfo are what ryzen master did itself in the auto oc section i set NO voltage to the cpu all was auto for the HWINFO section) on the r23 score was manual didn include the 10530 score bc it was complicated to get all that into the screenshot) 
considering i didnt change anything other than telling ryzen master to switch to manual mode which did cause reboot in which i didnt change anything inside the bios.... i have NO auto settings as of these screenshots. my L3 cache is the same as most the others here. so now im curious as to what people are claiming the problem is ? considering AUTO overclocking allows my chip to go way beyond what i can manually tune it to with safe (assumed safe) voltages the only downside i see is r23 scores being nowhere near 12k... they were exactly 12000 on multi but now its a tad low...perhaps where nahimic 3 decided to allow equalizer inside the app i decided to install it and thats whats slightly lowering my manual oc score there. but the fact that the ram speeds, timings, nothing has changed other than i kill razor synapse for the 4600mhz aida score and the 4850 score is pretty much running everything that normally runs on my pc in the background....but i am EXTREMLY new to PBO ect as the 3600xt i got was only 2 weeks old when i swapped out that for this 5600x. coming from a 1600af. learned alot but nowhere near enough since then. allot of which is still confusing on what some of you fellers say. anyhow DONT USE D1 bios...nothing i did would allow fclk to post past 1900. and i mean nothing. setting loose timings or auto all 1.5volts, 1.6volts just to try. even ALL AUTO only fclk 2000 and ram set to 4000mhz...nota thing would post. only 2 sticks at that so i would think it wouldnt have been impossible. perhaps one of you who are very well addressed in this sort of overclocking procedure will have luck. good news is flashing C back on my board now has fTPM again. so until amd can sort out the bug issues with the beta ect this is where ill stay for now....only try to stabilize 100% in all tests and not 3/4.


----------



## craxton

Esticbo said:


> The problem is the speed of l3 cache, if I change some settings in amd overclocking can had this:
> 
> View attachment 2469131
> 
> 
> The bios 1401 have agesa v2 pi 1.1.8.0 and PBO 2
> 
> AGESA V2 PI 1.1.8.0 formal release (non BETA)- Zen 3 / Ryzen 5000 Series CPU Support


...what settings exactly are you changing to get that???? im on a msi mpg x570 gaming edge wifi (i know the VRM are ****) but so far its been GREAT at everything ive thrown at it. granted i traded a 1080 strix a few months back in which i had nothing in the gpu (one fan blade was broke but still working today) the board i have is still under warranty registered under my name.... so if something would happen bc of VRM limitations and me blowing them up 30 bucks and well theyll send me out a new one after receiving this one. and my b450I can hold me off in the meantime. (sorry to get off topic do that alot) as for that L3 cache, what values would one need to tweak?


----------



## PJVol

Veii said:


> Nor can i run higher than 115 EDC


Hi! Is this limit somehow hardcoded ? I mean does it related to a certain firmware version or to the cpu itself?


----------



## Veii

Alyjen said:


> Oh my, that's faster! And it's only 5600X so I don't really get it..
> also what's ABL? you got me lost here  my result is with SMU 56.37.00 AGESA 1.1.8.0.


Agesa bootloader




__





AMD Family 17h in coreboot — coreboot 4.18-998-g5aabdf6e12 documentation






doc.coreboot.org




Which pretty much tells PSP Firmware on the chip what to allow and what not to allow to post
It communicates with SMU (boosting-table, voltage, chipset, FIT, PSP HW Security, PCIe) to tell what is allowed and what not
SMU communicates with FIT to exchange current health status, and the boosting/voltage table
SMU communication is fast, it happens in 10-24ms
FIT inside the CPU is faster , around 1-5ms

SMU only recieves data but doesnt control that much, because it's slow
ABL is mostly used on the start

All very simplified written
Here are interesting presentations to take a look at








GitHub - PSPReverse/psp-docs: Documentation about the reversed engineered PSP interfaces/hardware components.


Documentation about the reversed engineered PSP interfaces/hardware components. - GitHub - PSPReverse/psp-docs: Documentation about the reversed engineered PSP interfaces/hardware components.




github.com





EDIT: sorry it didn't send out yesterday in time


craxton said:


> (EDIT) dont try patch D1 i couldnt FOR ANYTHIG even at super loose timings get my chip to post 2000fclk. i have now switched back to version C and before allowing the memory to boot or train i straight tried 4000/2000fclk with auto mem try it timings on msi boards. needless to say that worked no issues...
> 
> have you tried patch D1? I'm almost positive its by far superior for overclocking ram than that of patch C. speaking of which patch C for whatever reason had issues with initialization of the fTPM module in bios let alone windows believing the 5600x has one.... took me forever to decide to try patch D1 beta bios. but glad i did. max cpu boost frequency of 4.7ghz. all well under temp threshold at that. only running 3600fclk due to not wanting to stress and test and stress and test due to a certain game releasing but 2000fclk was easy done upon first boot. was running 2000 fclk 4000 on 16,15,15,15,32,36 timings. (bdie kit from teamgroup)


I noticed memory training is fully broken on Patch C, at least on ABL 09284010 (SMU 56.34) while it wasn't on 090284010 (SMU 56.30)
Same goes for the "maximum bootable" FCLK

If the ASRock Bios team coud try to care for their only board they don't care much (B550 PG ITX)
Then i would try new bioses 
But no really, mocking aside~
I usually use flashrom to make a whole copy of the ROMchip - before trying anything new
Its far easier to compare clean flashes and i can just restore my profiles and working bios state with it

So far there is nothing new to test, nor did i get through the social media teams ~ working with their engineers
Unless i figure and sign it myself - or ask JZ for help/lend him a hand, there wont be much progress on the current issues
I probably should contact him ~ or just figure it out myself 

Oh please! try to write with linebreaks
It's soo hard to read big messages from you. Even harder to quote them


Alyjen said:


> yea but have you tried other benchmarks? something that would scale pretty good with memory? this may be some AIDA bug, I like to use Geekbench 5 for memory, it scales pretty good (base settings ~9500 points, after memory tuning 10700)


Aida64 is very stable - one of the most stable benchmarks for Vermeer.
But the powerplan is not very stable. Any variation within point 2-3ns is instability


PJVol said:


> Hi! Is this limit somehow hardcoded ? I mean does it related to a certain firmware version or to the cpu itself?


I had a short discussion with Robert Hallock - one that didn't went well.
I think yes, he declines anything even remotely similar and thinks it's the limits of my mainboard
I respect him a lot, but can smell from a big distance that half of it is nonsense ~ well it probably "will fix itself" after the new AGESA and this mysterious PBO2 ~ which i have no idea what should be different than what we already can use to some extend

It's funny,
Apparently
6x 90A ISL99390A + 2x 90A SOC chokes
should be maxed out at 120A . . . on a 6 core . . . on air 
Well at least he & ASRock got to read it, soo maybe something in the future will be fixed

But yes, i strongly think there are couple of hardcaps existing ~ it should not be on the microcode
although that one hasn't been updated on anything since mid August ~ was looking a new one somewhere
Either it's SMU or ABL - but ABL seems to change cache behavior and 2nd CCD utilisation
SMU has 2:1 mode bugs, but i need to figure out where ABL is to port it over and experiment further
Anywho, this little discussion gives good motivation to analyze this "lock" further
& go more public with it, after collecting more data

When you can't pass 120A on Air - for what is this LN2 switch even for
(it doesn't do anything except maybe remove a coldbug)
Will focus a bit further on powermanagement and try an allcore with very low voltage
Maybe it would allow me to push beyond 2133FCLK without autocorrecting throttle
Same thing then reverse - low FCLK CL12-10 with 5ghz boost
"No locks existing, suuure" 
But atm it makes no sense to push Fabric neither memory OC
~ when there is no way to surpass 50ns quoted as "Architectural limit"
~ and you have to focus on your fixed powerlimit


----------



## PJVol

Veii said:


> It's funny,
> Apparently
> 6x 90A ISL99390A + 2x 90A SOC chokes
> should be maxed out at 120A . . . on a 6 core . . . on air
> Well at least he & ASRock got to read it, soo maybe something in the future will be fixed
> 
> But yes, i strongly think there are couple of hardcaps existing ~ it should not be on the microcode
> although that one hasn't been updated on anything since mid August ~ was looking a new one somewhere
> Either it's SMU or ABL - but ABL seems to change cache behavior and 2nd CCD utilisation
> SMU has 2:1 mode bugs, but i need to figure out where ABL is to port it over and experiment further
> Anywho, this little discussion gives good motivation to analyze this "lock" further
> & go more public with it, after collecting more data
> 
> When you can't pass 120A on Air - for what is this LN2 switch even for
> (it doesn't do anything except maybe remove a coldbug)
> Will focus a bit further on powermanagement and try an allcore with very low voltage
> Maybe it would allow me to push beyond 2133FCLK without autocorrecting throttle
> Same thing then reverse - low FCLK CL12-10 with 5ghz boost
> "No locks existing, suuure"
> But atm it makes no sense to push Fabric neither memory OC
> ~ when there is no way to surpass 50ns quoted as "Architectural limit"
> ~ and you have to focus on your fixed powerlimit


Yeah, I just gave up at 52.5ns  as I don't see the benifit of digging further yet.
I saw your board, just curious how hot those Intersil's are? I read somewhere, 3950x was tested on this board and EDC was maxed at 140, though reviewer have noted of wrong power sensors reporting.


----------



## Alyjen

Ok this is super informative! thanks @Veii

Side question, while I messing around with memory and FCLK settings (meaning voltages, LLC, etc. to see if I can make FCLK 2000 stable) I've encounter this bug with my Asus board. 
After I boot both of my pcie cards (sound blaster & asus wlan card) are gone, no that windows gone (no drivers) just system don't see them at all. I was able to recover from it but it made me a bit worried. 
Which voltage or setting could cause such behaviour? Or it's not related and I'm missing some other factor.


----------



## kim nk

CL14 3821 시계 WHEA 오류 = 0


----------



## Veii

PJVol said:


> Yeah, I just gave up at 52.5ns  as I don't see the benifit of digging further yet.
> I saw your board, just curious how hot those Intersil's are? I read somewhere, 3950x was tested on this board and EDC was maxed at 140, though reviewer have noted of wrong power sensors reporting.


Some updates 
Well that discussion and Mr. Hallock follower made me look like an id*ot. lol
But i found some resolve for now

Pure simple ~ an flat allcore works.
Interestingly PBO Values still hardcap even the allcore ~ but at least now it does apply 150A limits and beyond
4.85 works for me under save voltages 4.95 works as short term max

100W-65A-150A ~ is what an 4.7Ghz allcore pulls @ 1.2VID / 1.275v VRM VCORE
(You can modify both independently VID & VCORE)
but it can run even with 120A limits without score loss


Spoiler














Quite some loss from my once hit 639p, but whatever
I'll get it back with memOC and +100Mhz more probably
Currently it's at 50.6ns ~ because it can not idle yet
But hey, at least i can do ~something~ again, without PBO EDC caps & random autocorrection

Another good news is,
I figured couple of SMU communication commands
Per-Core control like this works within the OS


Spoiler














Maybe @infraredbg when he finds time, can poke me ~ so we can work on ZenStates a bit
~ till AMD fixes their broken PBO and hopefully my ABL FCLK unlock push towards AMD/Frankenstein MOD works out

EDIT:
forgot to answer
They are cold but i have to test without a memory fan
My cooler is as big as the whole board 

And the fan technically cools them
Else 40-42c ?
I mean it's really cold
but i haven't played much with a fixed allcore
Will report later back with more info
Although on purchase i made sure to skip the "low end" Renesas Mosets
70 & 90A are the higher tier (ISL = Renesas)
400-700Khz Switching freq


Alyjen said:


> Ok this is super informative! thanks @Veii
> 
> Side question, while I messing around with memory and FCLK settings (meaning voltages, LLC, etc. to see if I can make FCLK 2000 stable) I've encounter this bug with my Asus board.
> After I boot both of my pcie cards (sound blaster & asus wlan card) are gone, no that windows gone (no drivers) just system don't see them at all. I was able to recover from it but it made me a bit worried.
> Which voltage or setting could cause such behaviour? Or it's not related and I'm missing some other factor.


Newer SMU , under Patch-C has a PCIe gen enforcement option under AMD CBS -> CPU Common options
Try to push it down to PCIe 3.0 , instead of 4.0 x8
It's kind of a known issue with Matisse back then, that Fabric beyond 2000Mhz starts to do random funky things
Most of the times it's either a voltage missmatch (too much remain voltage) or a too high procODT
Very often just both

Had couple of GPU Driver "reinstalls" and loses - but that was because of memory OC and too high voltages
Seems for me the resolve for 2100FCLK was VDDG CCD lower than 940 (900 worrked) and CPU VDDP 880mV instead of 930 (900 seems to work out too)

Overall a signal integrity thing
Undervolt Vermeer a bit and it should resolve itself + use y-cruncher on Vermeer
Too low voltages result in a hardcrash, same as too low SOC does
Often you need low IOD and very low CCD + high SOC to fix it
I nearly always utilize high voltage and strong drooping loadlines to fix such type of issues
Not many are a fan of loadlines ~ i like them personally
Help a bit to combat voltage degredation ~ because it's more variable


----------



## Alyjen

Great even more things I need to process 

PCIe slots I use for wlan and sound card are gen3 x1 slots anyway, bottom two slots since I wan to keep them as far as possibile from GPU. If this happens again I'll check what settings I can alter. Currently I'm in "let it run for a week and see if something breaks" mode before I'll tweak again. Otherwise I'll never know if broke something or it just was broken and only seemed stable. 

When you specify voltages do you think about what you set in BIOS or what lets say Z-timings is reporting?
Example, VSOC of 1.1V is reported as low as 1.0813V while idle, and it never reaches 1.1V under load (but it's higher under load) - this can be fixed by vddcr soc load line calibration set to max and then it's 1.1V flat
but then IOD/CCD and VDDP voltages also have some drop (not as spectacular but still) which is unaffected by vddcr soc load line calibration setting


----------



## Nighthog

@Veii 

My 4650G does not have VDDG voltage settings, no VDDG, VDDG_IOD, VDDG_CCD. I do not know if Renoir should have them but they are not avaible at all for this chip on my X570 Xtreme.
I know VDDG is quite important for FCLK on 3000 series and still is on 5000 series but do you need them on 4000 series? 
I've seen others seemingly have these options on other motherboard brands but not on my Gigabyte X570 Extreme for some reason. They never tested 4000 series on the board?
I'm a little sad with the lacklustre settings missing for this chip.


----------



## infraredbg

Veii said:


> Maybe @infraredbg when he finds time, can poke me ~ so we can work on ZenStates a bit
> ~ till AMD fixes their broken PBO and hopefully my ABL FCLK unlock push towards AMD/Frankenstein MOD works out


The commands are exactly the same as on Zen2, just the core mask is different, because we now have a maximum of 8 cores per ccx.
I've updated ZenStates (v2.0) some time ago, but sadly it is still unfinished, although I use it in my overclocking experiments.
I can control it per core, per ccx and ccd.


----------



## PJVol

Veii said:


> I'll get it back with memOC and +100Mhz more probably


How did you unlock that? ( i mean +100mhz)


----------



## Stoltzman1972

Hello. I need an expert look at this.
Do you think there is something wrong with my read and copy speed? Otherwise memory runs fine. It's 2x16 crucial ballistix kit, dual rank AES.
I havent tried other speeds, i was able to boot with 1900 fclk and proceeded with tightening timings. Read speed was around 50k with loosened test timings.


----------



## Alyjen

Stoltzman1972 said:


> Hello. I need an expert look at this.
> Do you think there is something wrong with my read and copy speed? Otherwise memory runs fine. It's 2x16 crucial ballistix kit, dual rank AES.
> I havent tried other speeds, i was able to boot with 1900 fclk and proceeded with tightening timings. Read speed was around 50k with loosened test timings.


These seems fine for the 5800X with the settings you have. When comparing online remember that 5900X/5950X and Zen 2 with two CCX will have some results way higher. If you want to tweak it I'd start from tRFC but that depends on the type of memory you have


----------



## Stoltzman1972

Alyjen said:


> These seems fine for the 5800X with the settings you have. When comparing online remember that 5900X/5950X and Zen 2 with two CCX will have some results way higher. If you want to tweak it I'd start from tRFC but that depends on the type of memory you have


Thank you. I think this is as tight as it goes for me at this point.
It wont boot above 1900 fclk and if i drop tRFC to 560 it shoots errors at me.
Maybe later.


----------



## MarcHays

Anyone here with 5900x and Asus Strix B550? I really need some help with overclocking F4-3200C14D-32GTZSW
all I want is [email protected] but when I set everything that DRAM calculator suggests it just won't boot. Black screen and I had to do CMOS. Perhaps there are more stuff I need to change except timings?
I mean if I want to set DRAM timings do I need to use DOCP or Manual or Auto?
What other stuff I need to change in Bios settings? I think I probably miss some additional BIOS settings besides timings that's why my PC won't boot.

If someone have similar setup I'd really appreciate for some quick tips and suggestions.


----------



## FleischmannTV

I have a question regarding the relationship between VDDG IOD and VDDG CCD. 

Many people, me included, run them synchronously without problems. On the other hand I have read in some places that IOD should always be a tad lower than CCD. Now with Ryzen5000 CPUs, Zen Timings can display both voltages and I see a lot of screenshots with IOD between 50 and 100 mV higher than CCD.

Now this leads me to the question of how it is supposed to be. Regarding this topic I have not found any solid information beyond "VDDG is derived from VSOC and can never be higher than VSOC minus 40-50 mV".


----------



## craxton

Veii said:


> Agesa bootloader
> 
> 
> 
> 
> __
> 
> 
> 
> 
> 
> AMD Family 17h in coreboot — coreboot 4.18-998-g5aabdf6e12 documentation
> 
> 
> 
> 
> 
> 
> doc.coreboot.org
> 
> 
> 
> 
> Which pretty much tells PSP Firmware on the chip what to allow and what not to allow to post
> It communicates with SMU (boosting-table, voltage, chipset, FIT, PSP HW Security, PCIe) to tell what is allowed and what not
> SMU communicates with FIT to exchange current health status, and the boosting/voltage table
> SMU communication is fast, it happens in 10-24ms
> FIT inside the CPU is faster , around 1-5ms
> 
> SMU only recieves data but doesnt control that much, because it's slow
> ABL is mostly used on the start
> 
> All very simplified written
> Here are interesting presentations to take a look at
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - PSPReverse/psp-docs: Documentation about the reversed engineered PSP interfaces/hardware components.
> 
> 
> Documentation about the reversed engineered PSP interfaces/hardware components. - GitHub - PSPReverse/psp-docs: Documentation about the reversed engineered PSP interfaces/hardware components.
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> EDIT: sorry it didn't send out yesterday in time
> 
> I noticed memory training is fully broken on Patch C, at least on ABL 09284010 (SMU 56.34) while it wasn't on 090284010 (SMU 56.30)
> Same goes for the "maximum bootable" FCLK
> 
> If the ASRock Bios team coud try to care for their only board they don't care much (B550 PG ITX)
> Then i would try new bioses
> But no really, mocking aside~
> I usually use flashrom to make a whole copy of the ROMchip - before trying anything new
> Its far easier to compare clean flashes and i can just restore my profiles and working bios state with it
> 
> So far there is nothing new to test, nor did i get through the social media teams ~ working with their engineers
> Unless i figure and sign it myself - or ask JZ for help/lend him a hand, there wont be much progress on the current issues
> I probably should contact him ~ or just figure it out myself
> 
> Oh please! try to write with linebreaks
> It's soo hard to read big messages from you. Even harder to quote them


ill keep that last line in mind when writing a book from now on. as per when i said all that i spoke with another member here who showed me the EDC bug (or i assume thats what it was) to get ones L3 cache to increase in speed without changing the speed or timings of the ram itself. to which it didnt go so well on my board (msi mpg edge wifi) but i didnt fair to ask what bios he was using.

considering ive now had time to test my fclk2000 jump from 3800 and TM5 anta, HCI, prime95 all saying good i didnt however try y cruncher as thats still new to me. im curious to test out my B450I gaming plus ac motherboard as its by far a better board for overclocking ect only its limit being (the lite bios) the last time i used it. but upon further checking its not supported for 5000 series chips yet. considering im not running gen 4 anything other than my GPU which doesnt run gen 4x16 instead 3x16 which im unsure why as stated no gen 4 m.2 in my system (8200sx pro 2tb b4 the controller being switch) anyhow

patch B on my board has this extreme problem as well to where i couldnt get 3800mhz to even boot on this chip and (something funky with the mouse happens to where its like 1 fps even if i set 20 mouse speed inside the bios under usb legacy options) maybe its the basilisk mouse im using idk. but what ive recently seen from this chip on patch C and patch D1 is that it boosts to 4.85 ghz patch D keeping way under 1.4volts and patch C hitting 1.45 volts. so i manually set it to 4.7ghz 1.25volts. which im unaware if thats concidered unsafe but i would assume its safer than the board always wanting to stay around 1.35 volts on auto when its not doing anything. 

now aside from my off topic mindset, how can i go about getting my L3 cache speed up to par with what it should be? as stated i limited ppt tdc edc to 150/100/100 curve to -20 and nothing changed. unsure if where there are 2 sets of amd overclocking parts in my bios as to if the main amd overclocking set isnt taking over but i set the other to the same and still nothing. but i do know that if they both arent on the same page (setting) then the pc will bootloop over and over like it needs more voltage. not 100% sure thats what the EDC bug is about entirely but none the less L3 cache is poor on my cpu atm...nowhere near what ive seen from you as well as others here... i also removed the limits in bios. PPT auto is 500? that correct or should that be way lower?


----------



## craxton

Stoltzman1972 said:


> Thank you. I think this is as tight as it goes for me at this point.
> It wont boot above 1900 fclk and if i drop tRFC to 560 it shoots errors at me.
> Maybe later.


i thought the same with my 3600XT but i was able to drop from 670 all the way down to 304 @1.4 volts same timings as what im using now on my 5600x both stable. which i could possible up voltage to 1.5v and lower timings some more and get a little more out of TRFC but atm thatll have to do. what bios patch are you using? i could post EASY on patch C on my board at 4000mhz before training upon first install fclk 2000 1.4volts. but patch B and D1 i could not. patch B wudn allow 3800. to where as D1 3800 was my limit with 1900fclk hard locked nothing would allow it to post. the bios wouldnt even recover from it had to manually clear cmos.


----------



## Dasa

Grabbed a kit of e die on sale for another system and decided to have a play unfortunatly one stick was DOA and the other seems to have topped out at 4866 18-26-14 1.55v.


----------



## halluzen

errors


----------



## Veii

infraredbg said:


> The commands are exactly the same as on Zen2, just the core mask is different, because we now have a maximum of 8 cores per ccx.
> I've updated ZenStates (v2.0) some time ago, but sadly it is still unfinished, although I use it in my overclocking experiments.
> I can control it per core, per ccx and ccd.


Ooh i have to check it 
Yes the mask is a bit different although a bit strange in the order with duplicate entries
Interesting is that "a ccx" mostly is a set of 2 cores & you can override/should change CPPC Preferred Cores order
In order to prefer your "faster set" od cores as "main" cores
Or at least put it to 1-1-1-1-1-1 ~ soo only internal quality scales

I'm not clear on everything by the SMU Mailbox
But Per-Core OC with per-Core F-Max Boost override should be the thing to go for
~ hopefully with working idle states
Well we'll see, maybe PBO "2.0" will magically resolve all the strange bugs and be useable again 🤭


----------



## KugelNacht

Hello everyone!

So I have an ASUS x570-e motherboard, bought a ram kit of 4x16 F4-3600C16QFZTNC (if im not wrong) and have a ryzen 5950X

For two days I had issues with this setup with constant restarts happening at random times. Digging a bit I found out that it was due to the ram config. Long story short, after multiple attempts to make them all work, i ended up just using 2 sticks in the recommended slots (marked with a * in the board)

Doing that seems to have solved the issue. I read that since this kit is dual rank, it was causing pain on the memory controller.

Question is, is that it? I have seen people saying that they gave gotten their 4xKits working even with them being dual rank.

Im so confused. Should I just try to return them and get a better kit? Thanks everyone and sorry before hand if I sound a bit too new.


----------



## VPII

KugelNacht said:


> Hello everyone!
> 
> So I have an ASUS x570-e motherboard, bought a ram kit of 4x16 F4-3600C16QFZTNC (if im not wrong) and have a ryzen 5950X
> 
> For two days I had issues with this setup with constant restarts happening at random times. Digging a bit I found out that it was due to the ram config. Long story short, after multiple attempts to make them all work, i ended up just using 2 sticks in the recommended slots (marked with a * in the board)
> 
> Doing that seems to have solved the issue. I read that since this kit is dual rank, it was causing pain on the memory controller.
> 
> Question is, is that it? I have seen people saying that they gave gotten their 4xKits working even with them being dual rank.
> 
> Im so confused. Should I just try to return them and get a better kit? Thanks everyone and sorry before hand if I sound a bit too new.


Hi man

I am using two sets of G-Skill FlareX DDR4 3200 CL14, so it is basically single rank memery dims but I am able to run them at 3800 CL16 with 1900 FCLK. I can understand that 4 sticks of dual rank could prove to be a challange for the memory controller, but maybe wait till the new bios update and see if it would work then.


----------



## qwrty

It could be a challenge even with 4 SR sticks to reach 1800+ FCLK. 
I changed my 4x8gb to 2x16gb and no more issue to push my FCLK.


----------



## Dasa

I have seen a few MB struggling with dual rank Hynix.
Maybe show us the settings it is running with ZenTimings since it is actualy booting and just unstable it may be possible to tweak something just enough to make it stable.


----------



## craxton

[QUOT


KugelNacht said:


> Hello everyone!
> 
> So I have an ASUS x570-e motherboard, bought a ram kit of 4x16 F4-3600C16QFZTNC (if im not wrong) and have a ryzen 5950X
> 
> For two days I had issues with this setup with constant restarts happening at random times. Digging a bit I found out that it was due to the ram config. Long story short, after multiple attempts to make them all work, i ended up just using 2 sticks in the recommended slots (marked with a * in the board)
> 
> Doing that seems to have solved the issue. I read that since this kit is dual rank, it was causing pain on the memory controller.
> 
> Question is, is that it? I have seen people saying that they gave gotten their 4xKits working even with them being dual rank.
> 
> Im so confused. Should I just try to return them and get a better kit? Thanks everyone and sorry before hand if I sound a bit too new.


i got my 4000mhz tforce kit working by down clocking to 3800mhz. xmp was 4000 c20. DarkZa kit 90 bucks a set on amazon. not dual rank. but you could simply look at QVL but as i just did that it seems there is one difference between your set and the set on the PDF file asus give for ram on 5000 series. so with that being said. manually set 3600 mhz with 1800FCLK with main timings at 19,19,20,20,42.
whats your XMP profile setting main timings to? have you looked? also ARE YOU TURNING OFF GDM before applying anything on ram side. also do use 2t instead of 1 for now. until you can get the machine to boot.

So check your XMP profile take a pic of it if you must with your phone or insert a flashdrive and screen capture and turn 2t command as youve alot of ram. download zen timings from here ( beta version btw). credits to @infraredbg and to whome ever else contributed to this. but download that and check your timings with what your XMP profile set inside the bios. if those dont add up id have to assume GDM is changing it maybe not but still. and if you can get it to post to check then go check backwards in this forum and check cldo iod voltages ect.bios arent really safe 100% yet...or if you truly dont wanna mess with it send the kit back and get a kit thats directly on your vendor list found here or just use 2 sticks and wait like someone else said. i didnt have 64 gb and i was using said ram on a 3600xt but seeing as to how it would run the 4000mhz but same random restarts ect jus like you.

its not safe btw thats errors happening which can kill your O.S. which is exactly what happened to me not realizing i wasnt truly stable. ive since learnt alot from this forum, and these people alone by simply asking, and reading back at least 5 pages before asking as sometimes it was only a few hours ago that question which you may have was already asked. so yeah, 64gb and its not on the QVL list dont mean it wont work. and depending on what the timings already are it may take some playing around with to get it to work. GL (EDIT/reason added shot for what zen timings will look like. and if youd rather go download from the source as im unsure if im allowed to share his work you can click his name and find zen timings in there as i did and download it that way.)


----------



## shotgunoclock

It's really easy to get the full version of AIDA64, just search youtube for like AIDA64 key or full version and copy the key he uses.. It works


----------



## craxton

shotgunoclock said:


> It's really easy to get the full version of AIDA64, just search youtube for like AIDA64 key or full version and copy the key he uses.. It works


lol who are you telling this too??? this is pretty much what most do id have to assume..... however i did pay for IDM before i knew that i would be getting support updates for only 3 years...


----------



## MarcHays

Hi. I'm running my memory with [email protected] using following timings:



















My RAM Frequency is 1.45,
SOC is 1.1
Both DDG* are 1.05.

I passed Extreme1 Anta777 preset in TestMem5 (the 2 hours one) with no error. However I want to run my memory 24/7.
I don't turn off PC when I leave house or go to bed so I want to make sure that my parameters and values are optimal for safe use?
I don't know much about memory overclock. If someone could tell me if there is anything I can change / lower to make it safer and stabler in long term I would really appreciate.

Also can anyone suggest some super heavy preset for TestMem5 that I can leave overnight for 8-10 hours to make sure I don't have any problems? Anta777 2 hours doesn't seems to "enough" in my opinion. Yesterday my game crashed without any error (no error in event viewer either) so I'm not sure if its just a game or memory related.


----------



## craxton

MarcHays said:


> Hi. I'm running my memory with [email protected] using following timings:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> My RAM Frequency is 1.45,
> SOC is 1.1
> Both DDG* are 1.05.
> 
> I passed Extreme1 Anta777 preset in TestMem5 (the 2 hours one) with no error. However I want to run my memory 24/7.
> I don't turn off PC when I leave house or go to bed so I want to make sure that my parameters and values are optimal for safe use?
> I don't know much about memory overclock. If someone could tell me if there is anything I can change / lower to make it safer and stabler in long term I would really appreciate.
> 
> Also can anyone suggest some super heavy preset for TestMem5 that I can leave overnight for 8-10 hours to make sure I don't have any problems? Anta777 2 hours doesn't seems to "enough" in my opinion. Yesterday my game crashed without any error (no error in event viewer either) so I'm not sure if its just a game or memory related.


you tried lowering proc ? but as c14 3600 needs to get extra warm im unsure if lowering is better. and yes go into the config file and set it to 5 passes try more passes if you wanna be sure, use HCI and y-cruncher as well.


----------



## MarcHays

*craxton*

What is proc? Besides that do you think the rest values are safe enough for everyday use?


----------



## TwilightRavens

MarcHays said:


> *craxton*
> 
> What is proc? -snip-


procODT


----------



## MarcHays

TwilightRavens said:


> procODT


Thanks. Do you guys thing I need to lower it or leave as it is?


----------



## craxton

MarcHays said:


> Thanks. Do you guys thing I need to lower it or leave as it is?


(reason for edit, adding beta zen timings suggestion) sorry bud, i shuda been more clear. it depends on if your willing to go through trial and error. as proc odt can help or make things worse same with CAD bus strength adjusting. Considering your test passed TM5extreme and only that its unclear. as you should test more to be safe unless you have copies of your O.S. backup incase your ram oc corrupts it. i will state that your L3 cache is pretty dam good to be honest. as it stands my 5600X at 4000mhz 2000fclk is NOWHERE near as good which is bad bc comparing it to my 3600XT with the same timings only it was at 3800mhz 1:1 mode was double the speed it is now with higher latency tho. (same timings and sub timings only frequency differences. both stable.

all in all tho i would for sure run some HCI overnight, re run TM5 extreme config (anta777) at least 5 passes) and use y-cruncher if not cruncher prime 95 memory test. which wont increase cpu temps to much. the reason im saying this is bc examples past in recent pages will show myself as well as many others passing Tm5 or HCI or prime y cruncher ect to where as another would fail. 1 error is a fail. like i said, up to you, i would test extensively considering i recently passed tm5 on my 3600xt but didnt test nothing else and had silent errors in the background to which i had to reinstall my o.s. from an extremely old backup. almost forgot, you can also use OCCT itll detect errors pretty fast. GoodLuck. i also SUGGEST zen timings BETA as itll show a bit more info for 5000 series chips as you can compare mine to yours under MCLK FCLK etc. it doesnt work on all boards tho. (doesnt show mem VTT VDIMM is what i mean. wont break nothing. worst you can do is not use it) will be standard soon enough.


----------



## MarcHays

*craxton*

Can you suggest me run time and maybe specific settings for the tests you metioned? LIke for example what is the memory test name in prime95 called? What Prime95 version I should use?
What is cruncher?


----------



## craxton

MarcHays said:


> *craxton*
> 
> Can you suggest me run time and maybe specific settings for the tests you mentioned? LIke for example what is the memory test name in prime95 called? What Prime95 version I should use?
> What is cruncher?


y-cruncher is an older program that wasnt actually made as a ram test and instead to determin pi or compute power in the older days of processors etc. but its now used more so as a ram based test i do believe (i only suggest y-cruncher because thats what the actual pros here use allot) which is used by most that get timings and scores ill probably never hit with a better b-die kit than they have. now with that being said, im not a pro ram overclocker or pro overclocker by any means. if you wanna go back a few pages perhaps start with the next page back and go about 10-15 pages back skimming thru youll see alot with the same cpu your running now. and to what timings they were able to daily mind it that most use like 1.5v or more (which those same settings probably will differ for you so you can get an idea of what to expect from your chip/motherbaord/bios revision... but yea, i suggested 5 cycles of TM5, overnight running of HCI (the memory test you can google unless you know what it is.(its not memtest 86) they're entirely different so remember that and dont use mem86. and trust it alone.

I suggest running any test at least 5 hours at the minimum, hci overnight, prime will crash or start to stop workers itself if either of those happens then your not stable.if i were you i wouldnt change anything, just stress the absolute **** out of what your running now. as from what i can find your proc odt is within spec and is considered safe, then again some ram like higher proc odt settings, others may like lower it just depends(so there really isnt a safe proc odt?). so just edit the config file using note pad and change cycles from 3 to 5 or more if you wanna wait for longer bc it will take more time. when thats done if it passes run HCI over night. or allow HCI to run from now until you get up if no errors are detected then, TM5 with 5 cycles or more to be safe, then prime.. i use the latest available prime 95 version on their website, remember you can use OCCT which is way easier to use IMO as it simply says memory test and shows errors, will crash out or stop, or keep going depending on settings/version you have. if its unstable. below is prime 95 on memory test didnt start otherwise that white page behind it would be filled with worker threads. and the other pic is OCCT
you can download prime from gimps here or occt from here (youll have to use the links and hit download from the page yourself. you can also download prime from guru3d here its up to you which to choose.

yet again (im not an expert and you should also ask some others. then again im sure i answered the same they would have (they being veii and dasa (being the two i remember most) only veii would have said some stuff you probably dont understand even more as he does me for sure. dasa is another that speaks english but its some kind of foreign tongue as well (to me lol) anyhow that should be all you need to find a ram overclock to be stable or not. OCCT is more than a ram test as youll find out if you use it. which i suggest you do over prime bc its more user friendly and not so scary when first starting it up. but each time you run and stop a test youll have to wait 10 seconds or pay a dono fee of (i cant remember) anyhow there you go man.


----------



## Kildar

Anyone have results for this memory:
G.SKILL TridentZ F4-3600C18D-32GTZR


----------



## MarcHays

*craxton*

Thank you for your recommendation. I did Prime95 for 7.4 hours and there is no errors.










Do I need to test it longer?


----------



## Veii

MarcHays said:


> Hi. I'm running my memory with [email protected] using following timings:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> My RAM Frequency is 1.45,
> SOC is 1.1
> Both DDG* are 1.05.
> 
> I passed Extreme1 Anta777 preset in TestMem5 (the 2 hours one) with no error. However I want to run my memory 24/7.
> I don't turn off PC when I leave house or go to bed so I want to make sure that my parameters and values are optimal for safe use?
> I don't know much about memory overclock. If someone could tell me if there is anything I can change / lower to make it safer and stabler in long term I would really appreciate.
> 
> Also can anyone suggest some super heavy preset for TestMem5 that I can leave overnight for 8-10 hours to make sure I don't have any problems? Anta777 2 hours doesn't seems to "enough" in my opinion. Yesterday my game crashed without any error (no error in event viewer either) so I'm not sure if its just a game or memory related.


Your result still is very high/slow.
By the RTT you use, it's surely dual rank ~ and i see how you got it probably stable
But two things are sub optimal

cLDO_VDDP beyond 900mV is not needed
Not even with 2100FCLK. It's a waste to push it high, only degrades signal integrity, and pushes minimum usable voltage up for no reason.
950mV would be already "high"
beyond 1000 is a waste , it doesn't help anything. Doesn't even help coreOC. Maaybe usable for -10c 24/7 XOC systems

tRC, you waste here 6 tCK or 1/8th of a cycle also for "nothing"
Well , pushing tRC usually is done for XOC scenarios and to make things easier (covering other non accurate timings)
In your case, covering dual rank "delay"
What you should focus on is pushing tRRD_& tWTR_ ~ which are PCB and IC dependent (capacity)
Keep tRC = tRP+tRAS
Maybe push tRP higher for dual rank if needed, but your main points of interest are tRRD & tWTR

On current boards with current CPUs , you can let tCKE be on auto even with GDM off
the PulseWidth is determined pretty accurate and can help stabilizing unstable kits
But non-there-less, get your tRC correct and use








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com




I'd suggest up to your time, to use a CL16 flat set and keep pushing FCLK a bit higher
At least up to 1867Mhz if not even 1900
Higher depends on your bios








Also suggest to use CAD_BUS
60-20-20-20 (dual rank) and try to stabilize 2T instead of GDM
Starting from 40-20-20-24
it gives you a bit more freedom to work on your timings
Really depends how much time you have to spare
Anywho, check out the Reddit Docs








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com




Which currently is the biggest Zen3 Database

For TM5, like KedarWolf suggested back then
using 1000% instead 100% on the TM5/bin/MT.cfg ~ changes the duration of the preset
I have not seen a need stressing memory for 8-9hours when the timings are fine
But if you want ~ that's the way to do it
Else a minimum cycle time of 20 rounds for 1usmus_V3 is required
Combined with y-cruncher 3-4 loops (all tests)

TM5 is there to find DIMM timing issues, not voltage or other signal integrity issues
For these, y-cruncher (4cycles), p95 large fft (3h), OCCT AVX2 medium dataset (>30min) are your tools to use


----------



## craxton

MarcHays said:


> *craxton*
> 
> Thank you for your recommendation. I did Prime95 for 7.4 hours and there is no errors.
> 
> Do I need to test it longer?


you see, thats Veii one of the two i mentioned...as you can see he said ALOT of things in which will be hard to understand as i dont understand some of what was said either. you can use D-RAM calc to find your TRFC values tho. so if you already have it it should be self explanatory on what to do (under advance tab) if you dont fully understand some of the terms that were used, google will guid you to some reddit post, that will explain what setting is what. some would say if you dont understand then you shouldn't be overclocking. but if that were the case noone would be overclocking without trial and error to learn what/or isn't possible. Now that hes responded im of no use as hes gave way more insight than i can. (if Veii isnt a he then someone do correct me) As Veii stated what you should do vs what you wanna do thats up to you. Since it was mentioned to focus more on tRRD_& tWTR thats what ill do myself.


----------



## craxton

Veii said:


> Your result still is very high/slow.
> By the RTT you use, it's surely dual rank ~ and i see how you got it probably stable
> But two things are sub optimal
> 
> cLDO_VDDP beyond 900mV is not needed
> Not even with 2100FCLK. It's a waste to push it high, only degrades signal integrity, and pushes minimum usable voltage up for no reason.
> 950mV would be already "high"
> beyond 1000 is a waste , it doesn't help anything. Doesn't even help coreOC. Maaybe usable for -10c 24/7 XOC systems
> 
> tRC, you waste here 6 tCK or 1/8th of a cycle also for "nothing"
> Well , pushing tRC usually is done for XOC scenarios and to make things easier (covering other non accurate timings)
> In your case, covering dual rank "delay"
> What you should focus on is pushing tRRD_& tWTR_ ~ which are PCB and IC dependent (capacity)
> Keep tRC = tRP+tRAS
> Maybe push tRP higher for dual rank if needed, but your main points of interest are tRRD & tWTR
> 
> On current boards with current CPUs , you can let tCKE be on auto even with GDM off
> the PulseWidth is determined pretty accurate and can help stabilizing unstable kits
> But non-there-less, get your tRC correct and use
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> I'd suggest up to your time, to use a CL16 flat set and keep pushing FCLK a bit higher
> At least up to 1867Mhz if not even 1900
> Higher depends on your bios
> View attachment 2469792
> 
> Also suggest to use CAD_BUS
> 60-20-20-20 (dual rank) and try to stabilize 2T instead of GDM
> Starting from 40-20-20-24
> it gives you a bit more freedom to work on your timings
> Really depends how much time you have to spare
> Anywho, check out the Reddit Docs
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Which currently is the biggest Zen3 Database
> 
> For TM5, like KedarWolf suggested back then
> using 1000% instead 100% on the TM5/bin/MT.cfg ~ changes the duration of the preset
> I have not seen a need stressing memory for 8-9hours when the timings are fine
> But if you want ~ that's the way to do it
> Else a minimum cycle time of 20 rounds for 1usmus_V3 is required
> Combined with y-cruncher 3-4 loops (all tests)
> 
> TM5 is there to find DIMM timing issues, not voltage or other signal integrity issues
> For these, y-cruncher (4cycles), p95 large fft (3h), OCCT AVX2 medium dataset (>30min) are your tools to use
> View attachment 2469797


Thank you Veii for correcting me (even if that wasnt your intentions) as i will take what you said and apply it to my own testing. Ill also try to see how this will improve using a 16 flat myself and trying to achieve lower tRRD&tWTR values. Of all the things ive lookedup for ryzen ram settings/overclocking ive never looked up what timings were most important nor did i ever ask. So these timings of my own could be way better even tho some would be higher values? And yes i know GDM is ugly to see, it actually runs without it at 15 flat i just got into cyberpunk and set my profile to what i knew was stable.


----------



## Veii

craxton said:


> Thank you Veii for correcting me (even if that wasnt your intentions) as i will take what you said and apply it to my own testing. Ill also try to see how this will improve using a 16 flat myself and trying to achieve lower tRRD&tWTR values. Of all the things ive lookedup for ryzen ram settings/overclocking ive never looked up what timings were most important nor did i ever ask. So these timings of my own could be way better even tho some would be higher values? And yes i know GDM is ugly to see, it actually runs without it at 15 flat i just got into cyberpunk and set my profile to what i knew was stable.
> View attachment 2469802


"After Veii has answered i seem to be useless"
You are NOT 

2000 FCLK is good to see
You know if this is stable ?
tRP 15 under 4000MT/s with just 1.4vDIMM is low
I really wonder if you have an A1 PCB. A2 needs more current and A0 starts to fail after 4000MT/s
4133 is the highest you can go with before you have random PCB crashes
But A0 can run very low SCL.
There are many little tricks you can utilize ,but you have to know which PCB your kits are on

tRFC and DRAM Calculator ~ Yuri (1usmus) does work very hard on his presets. I mean worked even back then very hard
But if you are not copying the set 1:1 ~ then the timings are not good
tRFC is a triggered refresh cycle - one that can and will be postponed by the memory up to 9 times in the whole tREFI range ~ if the whole cycle time is not calculated correctly
tREFI is being the whole refresh cycle (easily explained)

Because tRFC is variable, accuracy of it is important
the reason why this little tRFC mini calculator exists
And to fix all the roundings that happen

Unless you know the exact ns value which can be up to 11 decimals ~ you will have rounding issues by using Yuri's tRFC calculator, with any random set of timings
Same goes for the math of how you get out tRFC 2 & tRFC 4. Rounding errors stack
Which means, try to use tRC for your tRFC value.
1usmus presets are pretested and utilize what some call "refresh cycle stacking".
A method to use faster timings, and lower refresh time ~ while abusing remain/left charge in the caps.
Resulting in overall lower latency and faster burst operation.
just this needs excessive timings testing and can not be calculated fully.
Soo this little thing again exists for a reason 
Figuring out a baseline of timings where nearly no autocorrection happens








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com





Same ruleset goes for your tFAW
I played a bit with tFAW = 2x tRRD_S , but it's not in a usable or recommending state.
tFAW = 3* tRRD_S , is the same thing ~ just even more buggy and causes issues
tFAW (forth activate time window) is what should be used = 4* tRRD_S
as 5* will trigger a "time break" - on which the memory kills active delay commands and autocorrects
~ overall resulting in worse latency
Soo fix your tFAW please.
Lower than tRRD_S * 4 makes no sense unless you have it tested very extensively to lower it like -1 of 4*tRRD_S
--------------------
Another thing,
Are you sure you pass y-cruncher all tests
Especially FFT which has a big focus on memory ?
VDDG CCD is high for you, i noticed beyond 940mV hard crashes (shutdowns) on Vermeer


----------



## MarcHays

Veii said:


> Your result still is very high/slow.
> By the RTT you use, it's surely dual rank ~ and i see how you got it probably stable
> But two things are sub optimal
> 
> cLDO_VDDP beyond 900mV is not needed
> Not even with 2100FCLK. It's a waste to push it high, only degrades signal integrity, and pushes minimum usable voltage up for no reason.
> 950mV would be already "high"
> beyond 1000 is a waste , it doesn't help anything. Doesn't even help coreOC. Maaybe usable for -10c 24/7 XOC systems
> 
> tRC, you waste here 6 tCK or 1/8th of a cycle also for "nothing"
> Well , pushing tRC usually is done for XOC scenarios and to make things easier (covering other non accurate timings)
> In your case, covering dual rank "delay"
> What you should focus on is pushing tRRD_& tWTR_ ~ which are PCB and IC dependent (capacity)
> Keep tRC = tRP+tRAS
> Maybe push tRP higher for dual rank if needed, but your main points of interest are tRRD & tWTR
> 
> On current boards with current CPUs , you can let tCKE be on auto even with GDM off
> the PulseWidth is determined pretty accurate and can help stabilizing unstable kits
> But non-there-less, get your tRC correct and use
> 
> 
> 
> so in the summary you suggest cLDO_VDDP set to 900 or something else or auto?
> tRC - 42?
> 
> what about voltage? is 1.45 too high?
> 
> also i dont really understand what do you mean by saying my result is slow / high
Click to expand...


----------



## Ralm

Is anyone aware of some easy technical documentation regarding the DDR4 spec, to understand the relationship between the timings and subtimings? 
Thanks.


----------



## Veii

Ralm said:


> Is anyone aware of some easy technical documentation regarding the DDR4 spec, to understand the relationship between the timings and subtimings?
> Thanks.


Basics:








Introduction to DRAM (Dynamic Random-Access Memory) - Technical Articles


This article will examine the basic operation of Dynamic Random Access Memory (DRAM), along with how a DRAM chip is organized.




www.allaboutcircuits.com




Easier Basics
1.) systemverilog.io
2.) systemverilog.io
Timings overview and explanation
1.) systemverilog.io
2.) Community Update #4: Let's Talk DRAM!
Strictly technical
1.) https://ia903102.us.archive.org/7/items/arxiv-1604.08041/1604.08041.pdf
2.) http://people.ece.cornell.edu/martinez/doc/isca13-mukundan.pdf


----------



## Veii

MarcHays said:


> so in the summary you suggest cLDO_VDDP set to 900 or something else or auto?
> tRC - 42?
> 
> what about voltage? is 1.45 too high?
> 
> also i dont really understand what do you mean by saying my result is slow / high


Your result is slow for this kind of set - is what i mean
900mV cLDO_VDDP, more is not needed
tRC 42 would be correct, 48 is for a 16-16-16-32-48 set

You can also try your luck with tRDWR 7 instead of 8
But it depends on your kit
Normal b-dies can go down to -1 , like illustrated on my timings snipped attached
But as i can see you game a lot ~ higher FCLK is more interesting for you, not that much low timings


----------



## Alyjen

Any big mistakes, easy gains in these settings? I know my memory can go higher or tighter, I just don't feel too comfortable with higher voltages, current settings are at 1.4V and I'm thinking about dropping it to 1,35V


----------



## BluePaint

Veii said:


> You can also try your luck with tRDWR 7 instead of 8


Hi, do u know which other settings influence tRDWR the most? That is, which settings would I need to change to get lower tRDWR?
I noticed that if I want to run > 1900/3800, tRDWR has to be > 10, otherwise it will not even get into bios. It's a 2x16GB DS b-die kit which runs @ [email protected]


----------



## Alyjen

BluePaint said:


> Hi, do u know which other settings influence tRDWR the most? That is, which settings would I need to change to get lower tRDWR?
> I noticed that if I want to run > 1900/3800, tRDWR has to be > 10, otherwise it will not even get into bios. It's a 2x16GB DS b-die kit which runs @ [email protected]


It's not my research, person from Polish forum did this and he also helped me with my memory tuning, you can set one and leave the other on auto, otherwise like you said you won't even boot if you set it wrong.
tCWL 14 <-> tRDWR 8
tCWL 12 <-> tRDWR 10
tCWL 11 <-> tRDWR 11
tCWL 10 <-> tRDWR 12
tCWL 9 <-> tRDWR 13


----------



## Veii

BluePaint said:


> Hi, do u know which other settings influence tRDWR the most? That is, which settings would I need to change to get lower tRDWR?
> I noticed that if I want to run > 1900/3800, tRDWR has to be > 10, otherwise it will not even get into bios. It's a 2x16GB DS b-die kit which runs @ [email protected]


If you can find the page , it's from OCN
But since the update killed all my old links - i can not find the tutorial to it
(tRCD_RD /2) = tRDWR, can be equal or higher
(tRCD_WR /4) = tWRRD , should be equal or lower
tWRRD = SCL*X equal tRCD_WR or lower

If you want tRDWR -1, then tWRRD latency needs to be added
else tWRRD should always stay at 1

Also ruleset requires tCWL = tCL
else tRDWR goes by the same amount up, as you lower tCWL
If lower tCWL or lower tRDWR makes sense is up to users timings. I prefer tRDWR-1
Micron Rev-E can go tRDWR-2 but only them
Dual Rank needs often tRDWR+2, or +1 with added tWRRD delay
tWRRD can use either (tRCD_WR /4) or (tRCD_WR / SCL)
Only one of both can be a high value, either tRDWR or tWRRD not both.
Sometimes tWRRD 2 instead of 4 can work, or 3 instead of 6
~ because 6 is too high unless you run tRCD 24+ timings with tRDWR of 12+

EDIT:
AMD <-> Intel
tRDWR <-> tRRDR
tWRRD <-> tRRDD
If you want an alternative ruleset, probably buildzoid knows a bit or the Intel DRAM community here
But this is my ruleset above 
Board prediction works very similar (when it works.lol)

EDIT 2:
Overall it goes together with the same ruleset of tRCD_WR = tRCD_RD/2 as lowest
There you use half of tWRRD not the full one, else it chokes 
Meaning instead of 9-4 you use 9-2


----------



## 8McLovin5

Alyjen said:


> Any big mistakes, easy gains in these settings? I know my memory can go higher or tighter, I just don't feel too comfortable with higher voltages, current settings are at 1.4V and I'm thinking about dropping it to 1,35V
> View attachment 2469823
> View attachment 2469824


I am new here, and take this with a grain of salt. You might be able pick up some gain, if this is bootable with GDM Disabled. Also, your tRFC looks low according to other calculators. But I am new to this and researching the same as you. But there can be gains if GDM is disabled, in my research..


----------



## BluePaint

Thanks for the input. That should help stabilize > 3800 when there is a new agesa/bios available which takes care of the whea error issue.
These are my current settings @ 1.5v. Input always welcome!


----------



## Alyjen

8McLovin5 said:


> I am new here, and take this with a grain of salt. You might be able pick up some gain, if this is bootable with GDM Disabled. Also, your tRFC looks low according to other calculators. But I am new to this and researching the same as you. But there can be gains if GDM is disabled, in my research..


Yea I know about GDM, it's just last time when I tried to disable GDM I've ended up with fresh Win installation  Something was very unstable and OS got corrupted so fast and so hard that I had to reinstall it. I need to get a second installation or save an image somewhere to approach it again.
tRFC I could probably set more aggressive, but if I'm reading @Veii correctly I alerady have it a bit too high (meaning low) for my primary timings.


----------



## craxton

Veii said:


> "After Veii has answered i seem to be useless"
> You are NOT
> 
> 2000 FCLK is good to see
> You know if this is stable ?
> tRP 15 under 4000MT/s with just 1.4vDIMM is low
> I really wonder if you have an A1 PCB. A2 needs more current and A0 starts to fail after 4000MT/s
> 4133 is the highest you can go with before you have random PCB crashes
> But A0 can run very low SCL.
> There are many little tricks you can utilize ,but you have to know which PCB your kits are on
> 
> tRFC and DRAM Calculator ~ Yuri (1usmus) does work very hard on his presets. I mean worked even back then very hard
> But if you are not copying the set 1:1 ~ then the timings are not good
> tRFC is a triggered refresh cycle - one that can and will be postponed by the memory up to 9 times in the whole tREFI range ~ if the whole cycle time is not calculated correctly
> tREFI is being the whole refresh cycle (easily explained)
> 
> Because tRFC is variable, accuracy of it is important
> the reason why this little tRFC mini calculator exists
> And to fix all the roundings that happen
> 
> Unless you know the exact ns value which can be up to 11 decimals ~ you will have rounding issues by using Yuri's tRFC calculator, with any random set of timings
> Same goes for the math of how you get out tRFC 2 & tRFC 4. Rounding errors stack
> Which means, try to use tRC for your tRFC value.
> 1usmus presets are pretested and utilize what some call "refresh cycle stacking".
> A method to use faster timings, and lower refresh time ~ while abusing remain/left charge in the caps.
> Resulting in overall lower latency and faster burst operation.
> just this needs excessive timings testing and can not be calculated fully.
> Soo this little thing again exists for a reason
> Figuring out a baseline of timings where nearly no autocorrection happens
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> Same ruleset goes for your tFAW
> I played a bit with tFAW = 2x tRRD_S , but it's not in a usable or recommending state.
> tFAW = 3* tRRD_S , is the same thing ~ just even more buggy and causes issues
> tFAW (forth activate time window) is what should be used = 4* tRRD_S
> as 5* will trigger a "time break" - on which the memory kills active delay commands and autocorrects
> ~ overall resulting in worse latency
> Soo fix your tFAW please.
> Lower than tRRD_S * 4 makes no sense unless you have it tested very extensively to lower it like -1 of 4*tRRD_S
> --------------------
> Another thing,
> Are you sure you pass y-cruncher all tests
> Especially FFT which has a big focus on memory ?
> VDDG CCD is high for you, i noticed beyond 940mV hard crashes (shutdowns) on Vermeer


(edit for PCB revision on ram (thought you were asking about the motherboard for some reason) PCB on my kit is labeled as R2 not A2? im unsure the differences as R2 is what is listed on teams website and a google search says its extreme pcb what ever thats suppose to mean. at least thats what info i can find on teamgroups website for Tforce sets which such info can be seen here and where i bought my kit for (110 after tax is here do note that they have a 3466 kit of this which comes with bdie, but its not a guarantee one will get bdie even tho all the reviews that has received said kit has claimed bdie. As teamgroup said "bdie isnt a guarantee on out tforce dark pro 3466 kit as a ram shortage from our suppliers may occur, however our tforce dark pro 3200 c14 kit is always samsung bdie) if anyone wishes they can indead go and search 3466 part number and add bdie in the questions and find them answering me about it.

at this time ive used anta777 extreme config with what you suggested to use, hci over night, and prim95 for around 6 hours or so. didnt use occt (latest version) or y-cruncher (at all). but all the others passed and were stable. as for my motherboard, it is a CRAPTASTIC board from msi, ALOT of great features in general, but sadly its 4 layer pcb. (mpg gaming edge wifi) which is known for horrible VRM thermal issues when manually overclocking on the CPU. as for 1.4volts i actually started at 1.5 and worked down from there making only voltage changes. LLC3 is set so it is a minor overshoot when underload 50 to 100mv offset is what ive seen depending on what test ive used.

as for your recommendation about tfaw, tWRRD ect i have not tried as is was 7 am when i was replying to this thread this morning. is now noon in my area. the only reason my tFAW is lower like it is "lower is always better" type of thinking applied. which i know now is not the case. Im currently thinking on either a new b550 board to buy TODAY or another set of the 3200c14 tforce kit i have now. which the ram kit would be cheaper but im unsure my board will actually handle it. i have tested my ram config every day when i go to bed for about 6 days straight fiirst heating up the ram with prime then running tm5, hci, occt. as stated tho, i have not used occt latest version that is to test anything.

my actual aida scores (latest version) is what is troublesome to see or at least worries me. as for my VDDG iod and ccd values, you should see what auto thinks. which never crashed lol... my bios is patch C (is D1 but man i could get nothing to post) msi has not released the new agesa as of checking last night. as for prime 95 passing yes y-cruncher no. i asked how to use it but couldn't find the reply i got. the older program is strange to my eyes. so perhaps im not 100% stable. but there hasnt been any hard crashing or shutdowns other than when i manually overclock the cpu. to which it does. but on auto on the cpu it ramps to 1.45V during a gaming session and stays there? no curve settings applied, no X anything on pbo. just default as i have NO experience with PBO whatsoever.

there hasnt been one guide works for all on pbo values and what works for all chips in a set range from what i can find. then again i couldnt find how to change my signature either (on this website) to my defense thats bugged tho as it has no setting or options...


----------



## craxton

dont know why it created an extra message.


----------



## craxton

Kildar said:


> Anyone have results for this memory:
> G.SKILL TridentZ F4-3600C18D-32GTZR


is there a reason for 3600 18,20/22 set timings in mind? Ill have to assume your just looking for something that works out the box with RGB only (this family of RGB) ?


----------



## Kildar

craxton said:


> is there a reason for 3600 18,20/22 set timings in mind? Ill have to assume your just looking for something that works out the box with RGB only (this family of RGB) ?


No, I was just wondering if anyone had any luck overclocking or with tighter trimmings..


----------



## mirzet1976

Veii said:


> This is rom one user on the gigabyte beta bios page
> View attachment 2469049
> 
> With latest ABL on same Patch-C SMU , they not only increased the FCLK limits (away from 1900)
> but finally started to use the 2nd CCD - for full cache bandwidth access
> 
> It's only EDC limited
> The question is ust , which ABL version is this


I think it's a bug, I got the same thing when I used the OC profile from beta bios 1216 on 1401


----------



## Dasa

Veii said:


> cLDO_VDDP beyond 900mV is not needed


For my system.
4x8 b die 4000c16 850mV
4x8 bdie 4100c16 900mV
1x8 e die 4400c18 850mV
1x8 e die 4866c18 975mV
Not sure about 3600 but it would be less and cLDO_VDDP is a setting that often results in no post by being just 25mV below a stable setting which makes it fairly easy to find the lower limits.


----------



## craxton

so when using y-cruncher use 0 1 7 ? if so that passes....


----------



## craxton

@Veii (edit i still do not understand why my L3 cache is so much lower than yours or anyone elses for that matter, for my 3600XT ran lower 3800mhz with flat 16 and did double L3 cache? is this a bios issue? MSI has not released anything in a minute for my board)

does this look better than that of what i shared before? or is my settings still not quite right? i did up the voltage to 1.45 but im pretty sure i dont need it as ive ran this kit with 1.4 now for well over a week... im going to give 4 sticks of 4000mhz darkzA C/DJR kit a shot on this chip and compare to if im able to stabelize on 2t then shoot for 1T which is possibly why i wasnt ever able to get the kit running on ryzen 5 3600XT actually bc i had no insight at all about 1T vs 2T with 4 sticks at that time.

Anyhow im unsure what settings in y-cruncher im supposed to use? prime small fft also passes with cpu set to auto vs manual oc. negative 8 curve x4 pbo 500,200,200 set. as if i lower at all the whole thing hard locks or crashes. then again i havent tried since lowering VDDG CCD values to your suggested of lower than 940mv. crashed at anything less than 930mv on auto pbo no curve. (still not sure what curve does, or how to use pbo properly.) but im looking into it as much as possible so decrease voltage thru the cpu/less heat, better frequency. i dont understand how this 240mm ek aio is not as good as my ml240l with cheap cooler master fans on it vs the vardar fans as this aio seems to allow the cpu to reach higher temps vs the ml240l.


----------



## Alyjen

for y-cruncher you need go via 3 steps if I recall
select components test
enable all tests
press 0 to start

it's taking 18 minutes per one pass. 

btw with this FCLK at 2000MHz you get zero issues/warnings/wheas instabilities whatsoever? If so that is so nice.. I wish my mobo/cpu was so willing to cooperate.


----------



## Veii

BluePaint said:


> Thanks for the input. That should help stabilize > 3800 when there is a new agesa/bios available which takes care of the whea error issue.
> These are my current settings @ 1.5v. Input always welcome!
> 
> View attachment 2469852
> View attachment 2469861


2 dimms or 4 dimms ?
did you set yourself the SD & DD's at 1-5-4-1-7-6 ?
I remember boards did that for some time
Grab SiSoftware Sandra, and run the Multi-Core Efficiency test
to get a baseline
maybe run it twice to be sure the curve (detailed view) matches

Then filter to local results only ~ for comparison
There are still couple of things you can try, but here you need a lot of testing ~ as the set is already very low

tWTR_L you can not get to 6 without erroring ?
Can you try tRFC 252-187-115 with tWR 12 , tRTP 8 or 12
Later try tRDWR 8 instead of 9 ?

3800C14 mostly needs 1.5-1.51v, you can play a bit with it if something refuses to post
If you push ClkDrvStr to 40-20-24-24 it might be already enough to get GDM away under 2T
else try your luck with 60-20-20-20.
Too high ClkDrvStr and high VDIMM can cause the PCB on the dimms to crash
it's a balance thing
if 60 crashes, you can try the same thing at 1.48vDIMM just as 60-20-20-24

SC SD ones i would keep at
1-4-4-1-6-6
instead of
1-5-4-1-7-6

Oh another thing about ClkDrvStr
high ClkDrvStrengh will cause issues with high ProcODT
Usually you either use high proc or high ClkDrv to get memory to run
Both together are not playing well, soo if 60 makes an issue try to drop proc a bit
lower proc generally helps in using lower voltages and increases max FCLK limit
Also helps boost a bit 
High ClkDrv, only causes more heat on the dimms and a bit more heat on the PCB - but that's it
You can combat that with lower vDIMM for example


craxton said:


> so when using y-cruncher use 0 1 7 ? if so that passes....
> View attachment 2469927


Y-cruncher 1-6-0
Component stresstest
We don't need benchmarks for "stresstesting" 
For IPC & SC boost benchmarks, you can focus on SuperPi 1.5 SX

I suggest to NOT run y-cruncher with an open PBO
Limit EDC, else your poor chip will hardcrash or overheat 😅


----------



## BluePaint

I just read the previous pages and there is a EDC hard limit for PBO? Could this be the reason I saw erratic behavior and lower scores when the 5950X was boosting to 4800Mhz in CB (cooling with cold air for AIO) with PBO curve enabled ?


----------



## DeletedMember558271

I have a new problem since getting a new GPU that heats up my case and room significantly more, this is no longer stable and will throw out a couple errors pretty fast if I run TM5 right after gaming long enough to heat things up:








Below is what I'm running now:








I was running vDIMM 1.53v in BIOS (reported as 1.516-1.520v, any lower isn't stable) and just threw it down to 1.45v in BIOS, and it doesn't seem to overheat anymore. 52.7ns to 54.2ns though.
I wish I could at least get FCLK up to 1900 for 3800 for C16 assuming I wouldn't have to raise voltage much again.
So what should try? Or do I just leave it like this since 3733C14 is too hot


----------



## Veii

BluePaint said:


> I just read the previous pages and there is a EDC hard limit for PBO? Could this be the reason I saw erratic behavior and lower scores when the 5950X was boosting to 4800Mhz in CB (cooling with cold air for AIO) with PBO curve enabled ?


For me there was a limit, on an old bios
According to Robert Hallock, there is no limit on the chip/FIT itself

But no one got on the topic of "PBO is not intentionally slower than it has to be"
FCLK cuts into the powerlimit - while higher EDC does not resolve it
It intentionally boosts lower ~ for me
This should be noticed and hopefully soon resolved - but it depends on the bios and the board

Cinebench has to peak the EDC limit, in order to get good scores
Because that lowers allcore voltage, but does not lower boost
problem is, sometimes allcore voltage of 1.18-1.2v is applied because EDC limit can not be bypassed ~ resulting in very bad allcore load 
All depends on the bios


----------



## Veii

Dreamic said:


> I have a new problem since getting a new GPU that heats up my case and room significantly more, this is no longer stable and will throw out a couple errors pretty fast if I run TM5 right after gaming long enough to heat things up:
> View attachment 2469965
> 
> Below is what I'm running now:
> View attachment 2469967
> 
> I was running vDIMM 1.53v in BIOS (reported as 1.516-1.520v, any lower isn't stable) and just threw it down to 1.45v in BIOS, and it doesn't seem to overheat anymore. 52.7ns to 54.2ns though.
> I wish I could at least get FCLK up to 1900 for 3800 for C16 assuming I wouldn't have to raise voltage much again.
> So what should try? Or do I just leave it like this since 3733C14 is too hot


You can try to utilize tRAS=tRCDavg+tWR+2 rule
Working tRCD_WR down, increasing tRP and decreasing tRAS & tRC

Rules to utilze:
tRAS=tRCDavg + tWR + 2
tRC= tRCD_WR+tCWL+4+tWR

@KedarWolf's timings are an example of that
Gadfly i think too runs it very similar

Usually lowering tRCD_WR is used to lower avg tRCD, and match a lower tRP that way ~ working tRC down and tRFC down
but here you can use it to lower tRAS and increase tRP
as tRP is independent and mostly affected by voltage and heat


> 16
> 12
> 16
> 14
> 30
> 44
> 288-214-132
> tCWL 16


This should work and be easier to run than flat CL14
Else


> 14
> 8
> 14
> 18
> 26
> 44
> 288-214-132
> tCWL 14


should also work
Although your procODT is high, you can try to lower that by one step - and push ClkDrvStr to 40
Then try to lower vDIMM
EDIT:
I'm a bit unclear on tRFC, it's not quite optimal
tRC 48 would fit it better but, well ~ we'll see.
You have to test if it gets skipped or not. I think it's just borderline fine
Also increasing tRRD_ does help against heat and needs lower voltage


----------



## Cavokk

Hi guys

I have tried a lot of FCLKs on my system the last couple of weeks but I have a very strange issue that I hope some of you could help me with?:

On my newish 5950 build *I can do FCLK at 2000Mhz but NOT 1900Mhz no matter what settings, voltages etc I have tried in BIOS* ... For testing I have memory at stock 2133MT/s Jedec (and UCLK at 1066Mhz) to rule them out of the equation. Trying 1900 FCLK has always resulted in NO POST but 2000 FCLK boots into windows just fine allthough with a few WHEAs piling up during use. (My current daily settings with tight 14,13,13,14,26 timing at 1866 FCLK is stable as a rock with ALL voltages set to Auto in BIOS except MEM which is at 1.5v (set by D:O:H:C)

I am aware there is work going on by AMD optimizing AGESA to make FCLK stable over 1800Mhz but simply cannot understand why 2000 FCLK is sort of working and 1900 FLCK is completely nogo.. And yes no matter what FCLK setting I can only get my RAM working at 3733MT/S which also is a pain as I bought them for the 1900 KHZ sweetspot









Hope any of you have some insights, ideas or pointers I can chase as I really want to run 1:1:1 @ 1900Mhz to get my Gskills to work at published 3800MT/s (my ASUS MB is on the G-SKill QVL for my quad 8Gb sticks F4-3800C14Q-32GZTN )

EDIT: (Mem can do 2000Mhz/4000MT/s easily with only two sticks on mobo with 2000:2000:2000 FCLK:MCLK:UCLK but not been able to do it in quads yet but that is another story







- makes NO difference for the completely unobtainable 1900Mhz FCLK though)

Thanks in advance

Cheers

C


----------



## Veii

@Cavokk You do run your settings on manual correct ?
Can you do an aida64 cache bench between your highest stable 1867Mhz for example and 2000Mhz
It can be that you bug out and run 2:1 mode
I have that on 2100Mhz , it uses the required voltages for it. It runs it
But in reality it's 2:1 mode

And also attach a ZenTimings screenshot








Releases · irusanov/ZenTimings


Contribute to irusanov/ZenTimings development by creating an account on GitHub.




github.com


----------



## craxton

Veii said:


> Y-cruncher 1-6-0
> Component stresstest
> We don't need benchmarks for "stresstesting"
> For IPC & SC boost benchmarks, you can focus on SuperPi 1.5 SX
> 
> I suggest to NOT run y-cruncher with an open PBO
> Limit EDC, else your poor chip will hardcrash or overheat 😅


as i looked ALL OVER for actual settings for PBO and CURVE? mostly what the curve is about? i couldn't really find enough to clear my head on it i believe negative curve makes it so that it allows more of something rather than less? or allows it to get more voltage/doesnt limit it as much? idk as stated what i could find and actually understand on the matter were people using negative curve had better scoring so i would have to assume its not as limiting somehow. Now for PBO i tried several things i "thought" would work but it would seem to if 200 120 120 but thats when i would get crashes, but if left to manual, negative 8 curve i believe, and x4 pbo the only time i hit 80 or more was in prime. since then i havent ran y-cruncher again when i did run it was at defualt pbo values, +200mhz allowed boost, negative 20 curve again(thats what ive seen ALOT of people using) and some to which showed difference to their L3 cache speed? 
*You mention limiting EDC but to what should i shoot for benchmarking wise?*
Speaking of which, whats the issue with L3 cache speeds on ALL msi boards ive seen being tested with aida? i have guesses to why, but im a "sure fire answer" type of person and im all about in depth answers, which may or may not show. I actually went and gave patch D1 another try again and well, i got 3800 working 1900fclk but nothing past that. at no amount of voltage no CAD_bus settings nothing in proc_ODC would help at all. So once again i flashed back. If all D1 does is give bar support as there isnt any info on whats in the bios new other than that one mention then i dont need it considering evga 2070s ftw3 ultra isnt "supported" thru bar. 

Again ill ask what PBO settings (limiting values for PPT etc one should use?) just tell me yours and thats what ill try out and work from there. i will state my power delivery on this mpg gaming wifi edge isnt the greatest which is why im looking into a gigabyte aorus B550 pro AX which considering its price for a full atx board and all the goodies it comes with (minus no post code or EZ debug led) it has everything im looking for and is budget friendly while being ( "top" ) tier spec quite a bit better than my x570... 

i am sorry im semi scattered brained, its part of that "in depth" problem i mentioned slightly. if someone else who has knowledge on PBO, CURVE optimizations wishes to give insight ill gladly accept all overloads possible.


----------



## Veii

craxton said:


> as i looked ALL OVER for actual settings for PBO and CURVE? mostly what the curve is about? i couldn't really find enough to clear my head on it i believe negative curve makes it so that it allows more of something rather than less? or allows it to get more voltage/doesnt limit it as much? idk as stated what i could find and actually understand on the matter were people using negative curve had better scoring so i would have to assume its not as limiting somehow. Now for PBO i tried several things i "thought" would work but it would seem to if 200 120 120 but thats when i would get crashes, but if left to manual, negative 8 curve i believe, and x4 pbo the only time i hit 80 or more was in prime. since then i havent ran y-cruncher again when i did run it was at defualt pbo values, +200mhz allowed boost, negative 20 curve again(thats what ive seen ALOT of people using) and some to which showed difference to their L3 cache speed?
> *You mention limiting EDC but to what should i shoot for benchmarking wise?*
> Speaking of which, whats the issue with L3 cache speeds on ALL msi boards ive seen being tested with aida? i have guesses to why, but im a "sure fire answer" type of person and im all about in depth answers, which may or may not show. I actually went and gave patch D1 another try again and well, i got 3800 working 1900fclk but nothing past that. at no amount of voltage no CAD_bus settings nothing in proc_ODC would help at all. So once again i flashed back. If all D1 does is give bar support as there isnt any info on whats in the bios new other than that one mention then i dont need it considering evga 2070s ftw3 ultra isnt "supported" thru bar.
> 
> Again ill ask what PBO settings (limiting values for PPT etc one should use?) just tell me yours and thats what ill try out and work from there. i will state my power delivery on this mpg gaming wifi edge isnt the greatest which is why im looking into a gigabyte aorus B550 pro AX which considering its price for a full atx board and all the goodies it comes with (minus no post code or EZ debug led) it has everything im looking for and is budget friendly while being ( "top" ) tier spec quite a bit better than my x570...
> 
> i am sorry im semi scattered brained, its part of that "in depth" problem i mentioned slightly. if someone else who has knowledge on PBO, CURVE optimizations wishes to give insight ill gladly accept all overloads possible.


PBO is quite an advanced topic and tbh - i haven't seen anyone making an in-depth video
There are a lot of older 2700X days ASUS documents to read
And PBO hasn't really changed much from that day ~ but still it lacks of content

My last sentence was to someone who plays with PBO of follows some tutorials
Do not use a too high open PBO without a reasoning - it will crash on harsh tests like y-cruncher.
This is what was linked and spread around




I have to correct myself a bit. There seem to be many videos about it on youtube already.
Seems like i've ignored many of them and learned it by myself

The goal you want to achieve is using the nearly same voltage as stock ~ with higher boost
Many people just enable PBO , let it push more current, see this short time high frequency numbers and be happy
But of course when you push more voltage, higher freq will run. I mean Matisse could run 5ghz with high enough voltage 

You need to make a spread sheet
Note your VID per core at X frequency (now every core has an own one lol)
Note applied SVI2 Vcore voltage, and the temperature
Also once PBO is enabled even with 0-0-0 as "auto" limits , HWinfo will have the load listed and the % rating of PPT, TDC, EDC

Go through all that work between all y-cruncher tests and both cinebenches + Aida64
Maybe even a taxing game of choice

PPT ~ Is mostly capped at the TDP the CPU is rated at. 75W, 125W, 175W ~ depends
The 5800X is an exception and breaks their limits - on harsh tests it can exceed up to 180W PPT on default settings
PPT limits you usually use as powerdraw limits. Like Killowatt-Hour, these limits are variable, they are not a "peak current" limit but an average. PPT limit on the CPU behave similar
They are not a brickwall hardcap in wattage, but let the CPU boost and throttle itself constantly to maintain that powertarget.
The EcoMode is often just a flat out 45W-65W PPT limit without anything else. The remain limits are auto adjusted.
PPT is one of the "real limits" you want to be lifted and be set very high ~ unless you are under thermal constrains.
Limiting PPT only is for example an easy and good method while gaming to lower overall powerdraw. Ignoring any other PBO optimisations.

TDC ~ Noted as Thermal limit.
I have to be honest, still at this point - i have no idea what causes it to spike much. But it seems to be more single core load focused. My rule of thumb was always to limit it to 98% of the harshest computational load (cinebench, adobe, rendering) i had
As 100% will let it frequency throttle.
It will peak 100% on harsh benchmarks and lower effective frequency and so also voltage. But it will not on benchmarks where scores matter. Games never make it peaking, nor do Single core tests like SuperPi or even only some y-cruncher tests peak it. As it's noted as thermal limit, i know it will throttle on many parts if 100% is hit, soo 98% goes well with the EDC limits you mainly should focus on.

EDC ~ That's a big one.
Into EDC limit goes close to everything. FCLK hits into these power-reserves, allcore 100% peaks on it
It's an Ampere limit, and can be compared to a "load strain" limit.
100% Peaking EDC limits have to be hit in order to gain a better score. Zen CPUs are designed on default to do such.
A peaking EDC does lower general supplied voltage, but is never hit on any kind of "normal load". Only if you stress more than 80% of the threads, you approach this limit.
What you should use it for, is not only to combat thermal output but mainly to "restore" the boost voltage you had on stock.
FIT module on it's own is very competent, and so are usually the limits put by AMD in place.They are well calculated
Soo instead of opening PBO to unhuman limits allowing the CPU to pull too much current ~ it's advertised to work with the stock behavior of the chip. Not "overriding" Precission boost ,but "overdriving" Precission boost 
Meaning,
In order to even use PBO correct - you need to know how your chip boosts and what frequency under which type of load with what voltage is applied.
Then adjust the EDC limits slowly upwards to cover for the higher hit on the powerbudget you introduced by memOC ~ while not breaking the initial boosting and throttling behavior 

For me, 75-50-90 ?
i think where the limits, actually i did forget ~ touched on it couple of pages back 2 weeks ago
My current PBO was 135-78-115
Beyond 120 was not working and higher EDC pushed too much allcore voltage "firetrucking" up my benchmarks
+10W PPT, +5 TDC
are good steps to take.
But as the 5800X does surpass it's limits anyways , it might not be applicable.
Check what load Cinebench R20 and R23 hit on the 5800X on HWinfo and replicate that for now - else y-cruncher will overheat that little unit 

Curve optimizer you should be able to learn from the linked video
I only used it to leverage core quality out. But i can see it being used as enhancer for good cores or helper for them hitting 5ghz. I personally only wanted to have close to equal performing boosting cores and not one who can hit 4.9 while the other 2 can barely hold 4.7. It was messing up benchmarks, even when CPPC should try to assign the load to correct "good cores".

Overdrive scalar, i could not explore much because of the fixed powerlimit i was hanging on
The same goes for pushing memory much. I'll revisit it once RL is a bit more tame and PBO is not an unifinished limited thing.
Let's call it "buggy" , not "limited" 
You can see overdrive scalar 1X-10X like an interacting loadline and working together with FIT
It will allow higher supplied and higher peak voltage for single core loads - moving under 1.485v peak
It will also change the "height" position of the voltage to frequency curve.
Similar to how Curve Optimizer behaves ~ just that curve optimizer touches on the last parts of the curve per core
Overdrive Scalar lifts up the whole curve downwards or upwards, and allows more current to be pushed through as maximum limit

More on this PBO topic another time,
It's already huge and still not covering that much
BAR support btw exists since AGESA 1.1.0.0 Patch B
It's marketing nonsense that you need patch C or higher.
Patch C not only broke memory training for many (should be hopefully soon fixed) but also updated ABL with an enforced FCLK limit to "minimize" WHEA errors.
I haven't seen any, but you know ~ not a big fan of intentional hardlocks in the AGESA Bootloader , just soo PCIe 4.0 functions more stable for the mainstream 
Done with Matisse ~ not accepting it again on Vermeer when 2100FCLK can run well enough IF unlocked


----------



## Cavokk

Veii said:


> @Cavokk You do run your settings on manual correct ?
> Can you do an aida64 cache bench between your highest stable 1867Mhz for example and 2000Mhz
> It can be that you bug out and run 2:1 mode
> I have that on 2100Mhz , it uses the required voltages for it. It runs it
> But in reality it's 2:1 mode
> 
> And also attach a ZenTimings screenshot
> 
> 
> 
> 
> 
> 
> 
> 
> Releases · irusanov/ZenTimings
> 
> 
> Contribute to irusanov/ZenTimings development by creating an account on GitHub.
> 
> 
> 
> 
> github.com


Hi Veii, - thanks for stepping in - highly appreciated 

To get FCLK running at 2000Mhz I had to use manual voltages as depicted below. I just redid all my tests and remembered to take the screenshots this time  

So first one is my current running config at 1866 1:1:1 with 4 pcs of 8GB DIMMS:










Next one is same config reset to Standard Jedec memory timings but with FCLK set at 2000 MHz:










To do 2000:2000:2000 I have to remove 2 DIMMs and I just set some relaxed primary timings and let the mobo auto the rest and the result is:










For the sake of easy comparison I then just lowered to 1866:1866:1866 with no other change:










Hope this can give some insights and I am very thankfull for any feedback 

Would LOVE to get all 4 sticks running at 1900 1:1:1  

Cheers

C


----------



## MakisOne

Hi.

I have a F4-3600C18Q-128GTRG (hynix mjr) memory with a 5950X and Crosshair 8 Hero Wifi.


















I have used the calculator values for cjr / djr.

I would like to be able to raise the ram to 3800mhz but it is impossible to boot at more than 3600mhz.




















*Any suggestions to optimize a bit more?*


----------



## Hmm on

Only what i can see now on this forum. I dont buy a cpu now


----------



## DeletedMember558271

Veii said:


> You can try to utilize tRAS=tRCDavg+tWR+2 rule
> Working tRCD_WR down, increasing tRP and decreasing tRAS & tRC
> 
> Rules to utilze:
> tRAS=tRCDavg + tWR + 2
> tRC= tRCD_WR+tCWL+4+tWR
> 
> @KedarWolf's timings are an example of that
> Gadfly i think too runs it very similar
> 
> Usually lowering tRCD_WR is used to lower avg tRCD, and match a lower tRP that way ~ working tRC down and tRFC down
> but here you can use it to lower tRAS and increase tRP
> as tRP is independent and mostly affected by voltage and heat
> 
> This should work and be easier to run than flat CL14
> Else
> 
> should also work
> Although your procODT is high, you can try to lower that by one step - and push ClkDrvStr to 40
> Then try to lower vDIMM
> EDIT:
> I'm a bit unclear on tRFC, it's not quite optimal
> tRC 48 would fit it better but, well ~ we'll see.
> You have to test if it gets skipped or not. I think it's just borderline fine
> Also increasing tRRD_ does help against heat and needs lower voltage


Thanks, I'll have to try all this if a new BIOS doesn't help, I think I might just wait for that at this point cause I'm tired of all this and resetting CMOS now practically requires me to remove my GPU which is a pain in the ass. B550 Tomahawk + 3080 Asus TUF, with GPU in I can get the battery out but not back in, might be able to get something in there to short JBAT1 but idk yet.
3733C16 kinda sucks, not what I wanted when I spent this much on RAM, but if a new BIOS lets me get 1900+ FCLK then maybe I can do 3800C16 or even 3867C16, 3933C16 without raising voltage/temp as high as before, don't know if 4000C16 would be cool enough.
Otherwise I don't want to lower 3733 to like 3600 so I can keep C14 and lower voltage/temp, and GDM Off for 3733 15-15-15-15-30-45-1T seems impossible doesn't even post, and just turning off GDM for my current 1T 3733C16 settings BSOD's TM5 fast.
I'm tired of everything lol

The easiest thing to do would be just raise MCLK until I need more voltage/higher temp but I can't cause of FCLK


----------



## Veii

Dreamic said:


> Thanks, I'll have to try all this if a new BIOS doesn't help, I think I might just wait for that at this point cause I'm tired of all this and resetting CMOS now practically requires me to remove my GPU which is a pain in the ass. B550 Tomahawk + 3080 Asus TUF, with GPU in I can get the battery out but not back in, might be able to get something in there to short JBAT1 but idk yet.
> 3733C16 kinda sucks, not what I wanted when I spent this much on RAM, but if a new BIOS lets me get 1900+ FCLK then maybe I can do 3800C16 or even 3867C16, 3933C16 without raising voltage/temp as high as before, don't know if 4000C16 would be cool enough.
> Otherwise I don't want to lower 3733 to like 3600 so I can keep C14 and lower voltage/temp, and GDM Off for 3733 15-15-15-15-30-45-1T seems impossible doesn't even post, and just turning off GDM for my current 1T 3733C16 settings BSOD's TM5 fast.
> I'm tired of everything lol
> 
> The easiest thing to do would be just raise MCLK until I need more voltage/higher temp but I can't cause of FCLK


Hmmm why don't you put your RESET header to the CMOS clear switch


Spoiler














I can understand how annoying it is - but often a lower tCL fully refuses to post
Some settings are just too low to initialize a board only cmos
Yes, put your tiny reset switch there and fold it a bit
Usually it does fit perfectly infront of the gpu or just barely under their plastic enclosure

3800C16 you can usually expect to run with most b-die kits who can run 3400C14
GDM disabled has to work for you 
It's probably a settings issue
Can you confirm all 4 dimm PCBs (on both sides) look perfectly identical ?
Not that you got for example a B1 and B2 kit mixed ?
It can happen ~ still not every brand takes care on what PCB they put their ICs on - as long as it passes their QC suite
If the kits are not perfectly identical, or even the PCB is different ~ it makes a big difference 
-----------
@Cavokk
The same goes to you


> Can you confirm all 4 dimm PCBs (on both sides) look perfectly identical ?
> Not that you got for example a B1 and B2 kit mixed ?
> It can happen ~ still not every brand takes care on what PCB they put their ICs on - as long as it passes their QC suite


Beyond 4000MT/s is not easy
PCB's start to play a role and how you power them
Only VDIMM doesn't resolve everything


----------



## Cavokk

Veii said:


> -----------
> @Cavokk
> The same goes to you
> 
> Beyond 4000MT/s is not easy
> PCB's start to play a role and how you power them
> Only VDIMM doesn't resolve everything


Hi Veii.

Thanks - yes all 4 PCB´s look exactly identical in my case - secondly did you manage to see on my AIDA / Zen timings screenshots above if I hit the 2:1 as you suspected going to 2000 FCLK from 1866? Again very strange that I can do 2000 FCLK but not 1900 no matter what  

Cheers.

C


----------



## Veii

Cavokk said:


> Hi Veii.
> 
> Thanks - yes all 4 PCB´s look exactly identical in my case - secondly did you manage to see on my AIDA / Zen timings screenshots above if I hit the 2:1 as you suspected going to 2000 FCLK from 1866? Again very strange that I can do 2000 FCLK but not 1900 no matter what
> 
> Cheers.
> 
> C


I did see that 20ns more
It's not even 2:1 mode at this point 
as the taxing on 2:1 mode is exactly 10ns

Something more is to your screenshots, soo my first doubt next to the high VDDP and low CCD ~ is just the results
They look strange and wrong. Soo i thought your memory is not stable at this speed ~ ignoring fabric and anything around the cpu


----------



## Cavokk

Veii said:


> I did see that 20ns more
> It's not even 2:1 mode at this point
> as the taxing on 2:1 mode is exactly 10ns
> 
> Something more is to your screenshots, soo my first doubt next to the high VDDP and low CCD ~ is just the results
> They look strange and wrong. Soo i thought your memory is not stable at this speed ~ ignoring fabric and anything around the cpu


Thanks Veii 

Is´nt the 20ns difference with going from 1:1:1 back do 1:2:1 with DDR4 at Jedec standard between screenshot 1 and 2?  - if you compare screenshot 3 and 4 there is no big latency penalty going from 1866 to 2000 FCLK only 1.7ish ns.

C


----------



## mus1mus

Just testing 4 Cheapo Hynix Dual Rank Sticks.


----------



## Veii

Cavokk said:


> Thanks Veii
> 
> Is´nt the 20ns difference with going from 1:1:1 back do 1:2:1 with DDR4 at Jedec standard between screenshot 1 and 2?  - if you compare screenshot 3 and 4 there is no big latency penalty going from 1866 to 2000 FCLK only 1.7ish ns.
> 
> C


You are right, i made a mistake.
I tried to factor in the additional delay difference between the speeds
But totally ignored the 18-20...94 set. This difference now makes sense
I was having the same timings in my head as to my examples
1933 @ 54.1ns 
2000 @ 51.9ns
2074 @ 50.1ns
your jumps seem to varry smaller, but tootally missed tRCD 20 on it. That one now makes sense 

Like, i don't know how to help you without knowing where you struggle. Why at least
Pushing ClkDrvStr , pushing IOD higher. Overall using higher proc than for 2 dimms
Increasing tRRD_ and starting with double tWR. Using BankGroupSwap instead of Alt mode, and having SD DD's as 1-4-4-1-6-6 instead of 1-5-5-1-7-7

All are usually common procedures
Soo i'm not sure where you even fail 
Using the better binned set as slave and the weaker on Main ~ is also the way to go , as the slave set on Daisy Chain get's less "current" (not voltage) overall
You should not have issues at all on 4000MT/s. Unless your dimms are on A0 PCB 
You will have issues with sub 1.42vDIMM, but beyond 1.46 there should be non. Soo i am not sure where to help


----------



## Cavokk

Veii said:


> Like, i don't know how to help you without knowing where you struggle. Why at least
> Pushing ClkDrvStr , pushing IOD higher. Overall using higher proc than for 2 dimms
> Increasing tRRD_ and starting with double tWR. Using BankGroupSwap instead of Alt mode, and having SD DD's as 1-4-4-1-6-6 instead of 1-5-5-1-7-7
> 
> All are usually common procedures
> Soo i'm not sure where you even fail
> Using the better binned set as slave and the weaker on Main ~ is also the way to go , as the slave set on Daisy Chain get's less "current" (not voltage) overall
> You should not have issues at all on 4000MT/s. Unless your dimms are on A0 PCB
> You will have issues with sub 1.42vDIMM, but beyond 1.46 there should be non. Soo i am not sure where to help


Cheers Veii. 

Basically my ultimate goal is to get my 4 sticks of 3800CL14's to run at their rated "XMP/DOCP" speed at 1900Mhz as they are listed on G-SKill QVL for my MoBo and I specifically bought them to compliment my 5950x. 

As noted earlier the mystic issue is that 1900MHz FCLK does not work but 2000 FCLK *does work* and even do it in 1:1:1 mode with 2 DIMMs - No matter what MCLK setting I cannot even POST at 1900FCLK but boot fine into windows at 2000FCLK  and as I think getting 4 sticks to work at 2000:2000:2000 might be too big a stretch on my daisychain mobo I at least want 1900:1900:1900 to work  

Thanks again for your tips outlined above - will experiment further Sunday based on your input .
'
C


----------



## mus1mus

Is 2000 FCLK working without performance penalty on your setup?

Verify with scores while keeping the CPU Clock static. You should be looking into around Cinebench 200 points lower for the penalty difference.

This is not a penalty for not running 1:1:1 ratio. Some older BIOS did this. If you however see gains, then just proceed to stabilize the 2000FCLK at 1:1:1.

Your memory kit should be able to handle the frequency with either a couple of timing tweaks or a bump in VDimm.


----------



## mus1mus

Hi guys, I am looking for that guy who asked me to do 3800 RAM GDM OFF on Dual Ranks Ranks B-die so he can call me a "hero".

Since I don't have dual ranks B-Dies, maybe *4 Dual Ranks Hynix JJRs* will do?

ROFL 😂😂🤣🤣


----------



## Dasa

mus1mus said:


> Is 2000 FCLK working without performance penalty on your setup?


B550 AORUS PRO BIOS 11n allowed running over 1900IF but Latency in AIDA64 jumped ~5-8ns when setting 2000IF however if set to 1966IF with 104BCLK for 2045IF there was no Latency increase instead latency dropped in line with what you would expect.
Unfortunately 11n BIOS also introduced WHEA errors but then so does the latest beta F12b but F12b does not allow over 1885IF.


----------



## mus1mus

Dasa said:


> B550 AORUS PRO BIOS 11n allowed running over 1900IF but Latency in AIDA64 jumped ~5-8ns when setting 2000IF however if set to 1966IF with 104BCLK for 2045IF there was no Latency increase instead latency dropped in line with what you would expect.
> Unfortunately 11n BIOS also introduced WHEA errors but then so does the latest beta F12b but F12b does not allow over 1885IF.


Are you keeping the timings the same when jumping from 1900 to 2000? 

If Timings are kept the same, I find no reason why latency would go up unless the Uncore is not running 1:1. BCLK does magical things.  

My previous BIOS allows for 2000 IF and 2000 Memory is not a problem. However, things are running slower. So something is amiss.


----------



## Dasa

mus1mus said:


> Are you keeping the timings the same when jumping from 1900 to 2000?


Yes although tCKE was left auto and it went from 1 to 16 but I tried it manually set back to 1 and the latency increase was still there although my memory was wrong it is only ~3ns not 5-8ns.
Just a quirk with that BIOS revision I believe although I have seen other people with different MB experience similar behavior over 2000IF.


----------



## mus1mus

Interesting. It may have something to do with how IF is implemented then. 

It is unusual for sure. I do know for a fact that my MSI has an early Ryzen 5000 bios that does 4000 IF and seems to run at 1:1:1. But there is a decrease in performance numbers that can not be directly seen with just Aida64. 

Either way, you have a running config that works better and as intended.  Thanks for sharing.


----------



## Veii

@Dasa tCKE is used even with GDM off on this gen
For whatever or whyever reason 🤔
But it does positively help


----------



## Mastakony

*AMD Ryzen 9 3900X @4.35GHz (SMT OFF)* 
That's the best I can do before I receive my 5900X.............


----------



## Alyjen

lots of results for IF 2000 1:1 I saw were in some way or another unstable, e.g. you get tens of whea warnings per minute then there's no way your results will improve,
example below, 1866 1:1 average timings yet results on pair with some of the FLCK 2000 people are posting here


----------



## BluePaint

FCLK 2000 or higher is definitely nice. My 5800 did 2033 on .142 Tomahawk bios but with WHEA errors ofc. Still, the memory sensitive benchmarks with synthetic and games (TR, Total-War,...) were higher 4066CL16 than 3800CL14. With .151 bios 1900FCLK is hard limit.


----------



## Dasa

Alyjen said:


> lots of results for IF 2000 1:1 I saw were in some way or another unstable, e.g. you get tens of whea warnings per minute then there's no way your results will improve,
> example below, 1866 1:1 average timings yet results on pair with some of the FLCK 2000 people are posting here


In some situations it may be a stability thing but not all.
With the 11n BIOS that allows over 1900IF I was getting ~100 WHEA errors a minute at 3733 and 2000+.
The latest beta cant even hit 1900IF but it also gets ~100 WHEA errors a minute at 3733 while the previous BIOS was fine at much the same settings with the exception of tWRRD 2 vs tWRRD 1 on the stable BIOS as it wont post any lower on the latest.

Also by using 104 BCLK I was able to set just below 2000IF and run 2045IF with improved performance but loads of WHEA errors.
Just waiting for them to release a BIOS with the 2000IF fix and without whatever is creating all the WHEA errors as they seem to be separate things.

Stability probably had something to do with the low L2,L3 bandwidth scores in this test though.


----------



## mus1mus

I have success eliminating WHEA Errors by either tuning down or up the CHIP CLDO Voltage. Not CLDO VDDP.

On my MSI it defaults to 1.2ish Volts.










Try locating that Voltage on your BIOS.


----------



## Pictus

Veii said:


> Oh another thing about ClkDrvStr
> high ClkDrvStrengh will cause issues with high ProcODT
> Usually you either use high proc or high ClkDrv to get memory to run
> Both together are not playing well, soo if 60 makes an issue try to drop proc a bit
> *lower proc generally helps in using lower voltages* and increases max FCLK limit
> Also helps boost a bit


Hi Veii!
It is not the other way around, higher ProcODT for lower voltages?
AMD Ryzen Memory Tweaking & Overclocking Guide


----------



## Veii

Pictus said:


> Hi Veii!
> It is not the other way around, higher ProcODT for lower voltages?
> AMD Ryzen Memory Tweaking & Overclocking Guide


i didn't mean DRAM voltage, but dram voltage lowers with more procODT
The same effect happens if you push CAD_BUS instead of proc
and the reason why ClkDrv helps using lower proc for example

but my point was rather lower proc = lower vddp, vddg, vsoc 
Two different things

The only positive effect of higher procODT to dram is, if DRAM was "underpowered"
lower proc helps in better signal integrity which helps in lower voltages anywhere overall
This above is a short test, but not the whole picture


----------



## Alyjen

Ok so if I was to disable Gear Down mode with below settings, what should I change/which order?
Lets say I want to have GMD off, at CL15, but that's later after I know GDM itself is fine.
Current memory voltage is 1.4V


----------



## Veii

Alyjen said:


> Ok so if I was to disable Gear Down mode with below settings, what should I change/which order?
> Lets say I want to have GMD off, at CL15, but that's later after I know GDM itself is fine.
> Current memory voltage is 1.4V
> View attachment 2470335


24-20-20-24 , 1.42vDIMM & a short TM5, up till 4 rounds or just 20min
tRRDL_5, SCL 5 ~ same short TM5

tCKE 6, ClkDrvStr 40 ~ same thing , but should be fine
(if you have mirror move errors up tCKE to 9, but 6 should work
~ i'm guessing here the boards trace length)

now try 60-20-20-20, and check if you can post
if not, lower proc -1,VDIMM back to 1.4 and try again

Posting alone is enough, then you can try 2T
If that one refuses to post, you need to up tRFC
Example:
tRFC 336-250-154, tWR 14 , tRTP 7 ~ 2T
that should then for sure post

Usually what you want to achieve is a bit current "change"
high voltage will destabilize things.Changing these main parts like ClkDrvStr and procODT does change more than just one little thing
GDM off also changes internal MUX chips from half speed 400?mhz to fullspeed 800mhz
Which means also that couple of "refresh" timings like tWR, tRP, tRTP , tRFC ~ can destabilize
Later you can lower them again, but GDM on to off transition needs a bit of "slower" timings to begin with
And probably also a bit more voltage, like 20-30mV more


----------



## Alyjen

Veii said:


> 24-20-20-24 , 1.42vDIMM & a short TM5, up till 4 rounds or just 20min
> tRRDL_5, SCL 5 ~ same short TM5
> 
> tCKE 6, ClkDrvStr 40 ~ same thing , but should be fine
> (if you have mirror move errors up tCKE to 9, but 6 should work
> ~ i'm guessing here the boards trace length)
> 
> now try 60-20-20-20, and check if you can post
> if not, lower proc -1,VDIMM back to 1.4 and try again
> 
> Posting alone is enough, then you can try 2T
> If that one refuses to post, you need to up tRFC
> Example:
> tRFC 336-250-154, tWR 14 , tRTP 7 ~ 2T
> that should then for sure post
> 
> Usually what you want to achieve is a bit current "change"
> high voltage will destabilize things.Changing these main parts like ClkDrvStr and procODT does change more than just one little thing
> GDM off also changes internal MUX chips from half speed 400?mhz to fullspeed 800mhz
> Which means also that couple of "refresh" timings like tWR, tRP, tRTP , tRFC ~ can destabilize
> Later you can lower them again, but GDM on to off transition needs a bit of "slower" timings to begin with
> And probably also a bit more voltage, like 20-30mV more


Got it.. I think! thanks! I'll get a separate image to play with and give it ago. Last time when I disabled GMD my windows got corrupted on a first BSOD so that's why I'm more careful this time.

Shall I start with GDM off, 1T? My priority is to stabilize GDM and then work on tighter timings, CL15 should be doable without generating too much of an extra heat and that's the ultimate goal, I want to avoid situation when later when I add heat from GPU all these settings become invalid.


----------



## Dasa

mus1mus said:


> I have success eliminating WHEA Errors by either tuning down or up the CHIP CLDO Voltage. Not CLDO VDDP.


Interesting I wonder if that is something they have changed in the background that has affected stability although they have set the default SOC to 1.2v in the last few GB BIOS you would think that if they cranked it up they may crank some other things to but maybe not.
I have a sensor called Chipset Core 1.056v but no adjustment for it and nothing at all for CHIP CLDO.


----------



## Veii

Alyjen said:


> Got it.. I think! thanks! I'll get a separate image to play with and give it ago. Last time when I disabled GMD my windows got corrupted on a first BSOD so that's why I'm more careful this time.
> 
> Shall I start with GDM off, 1T? My priority is to stabilize GDM and then work on tighter timings, CL15 should be doable without generating too much of an extra heat and that's the ultimate goal, I want to avoid situation when later when I add heat from GPU all these settings become invalid.


3733C15 = 3534MT/s C14 
1T is harder than 2T
3734C14 would need about 75-90mV more than what you run, soo probably near 1.46-1.47v


----------



## mus1mus

Dasa said:


> Interesting I wonder if that is something they have changed in the background that has affected stability although they have set the default SOC to 1.2v in the last few GB BIOS you would think that if they cranked it up they may crank some other things to but maybe not.
> I have a sensor called Chipset Core 1.056v but no adjustment for it and nothing at all for CHIP CLDO.


It's just called CHIP CLDO in HWInfo and I am pretty sure that is named differently per Brand. 

This rail does also affect my Windows Audio as I previously thought this as CLDO VDDP and turned it down to 1.025V and once I am in Windows, Audio is scratchy and all sort of WHEA Errors popped up. I am doing things at 1.15 now. 




Veii said:


> 3733C15 = 3534MT/s C14
> 1T is harder than 2T
> 3734C14 would need about 75-90mV more than what you run, soo probably near 1.46-1.47v


I always start at 1T and GDM OFF. Same amount of work and tweaking needed at the end of the day.


----------



## mus1mus

Making a little headway lowering the TRCD and TRP a notch each to the expense of more VDimm and higher TRFC. 

4*16GB take 15 minutes to finish a pass. Anta Extreme takes more than an hour. lol

VDDGs can be lowered I guess. I just tried things and got stuck on the values shown.










Where do you guys get that TM5 with all English Language btw? 😂


----------



## Alyjen

TM5 - Google Drive 
at least last time I got it from here it was all english


----------



## mus1mus

Thanks man.. I'll check that one.


----------



## Nighthog

mus1mus said:


> Thanks man.. I'll check that one.


You can edit the *MT.cfg* by renaming to* MT.txt* and then just set language in the file, it's either 0 or 1 for English. Then save and rename to *.cfg* again.


----------



## craxton

Alyjen said:


> lots of results for IF 2000 1:1 I saw were in some way or another unstable, e.g. you get tens of whea warnings per minute then there's no way your results will improve,
> example below, 1866 1:1 average timings yet results on pair with some of the FLCK 2000 people are posting here
> View attachment 2470297


cant say ive had one WHEA error with my 2000fclk oc on my 5600x. am awaiting a new b550 gaming edge wifi board to swap into. will see if i can get better results with that over my x570 board now as its not to good with power delivery etc. let alone overheating VRM issues with PBO alone.


----------



## Alyjen

craxton said:


> cant say ive had one WHEA error with my 2000fclk oc on my 5600x. am awaiting a new b550 gaming edge wifi board to swap into. will see if i can get better results with that over my x570 board now as its not to good with power delivery etc. let alone overheating VRM issues with PBO alone.


Never said that all  but if fclk 2000 is followed by subpar benchmark results then there's something going on in the background. It's good to see that it's possibile but I still wonder how big percentage of chips is going to run at 2000 without any issues.


----------



## mus1mus

I would have to say it's the boards' bios rather than the chips that limits people to 1900 FCLK on Ryzen 5000.

Those having issues reaching 1900 using 5000 series chips are either challenged by their Memory settings or their patience.


----------



## Alyjen

For me it's definitely the patience. I have saved the profile with 1900/3800CL16 tight subtimings which gives me one whea warning every few days. I don't have the patience to correct this since it's not that easy to force this error. I saved another profile where the only change is 1866/3733, same subtimings & voltages and haven't seen this warning for over a week now, and computer was used & abused. One day I'll give it another go, or not. I treat it more as a hobby rather than real need and now thinking more about changing main timings to CL15 or 14 even rather than hoping for FLCK 2000 anytime soon.


----------



## mongoled

mus1mus said:


> I would have to say it's the boards' bios rather than the chips that limits people to 1900 FCLK on Ryzen 5000.
> 
> Those having issues reaching 1900 using 5000 series chips are either challenged by their Memory settings or their patience.


This is not true in my case

 

I have mine fine tuned using BCLK and the limits is real, max post 1894/6, max stable 1890/2 !

Found no setting to assist with this and I have spent many hours trying to find something that works.

Also, I have a friend who has almost the exact same config as me accept VGA, PSU and CPU, he has 5800X and he has the same limit. It cant post 3800/1900, it results in 07 error and needs BIOS reset.

So its looking like its motherboard BIOS issue in combination with certain CPUs.

Of course some users dont have the patience


----------



## mus1mus

On the Unify? 07 is memory related. 

Anyway, you are in a better situation as my board won't even post with BCLK other than 100.1 

Maybe post your BIOS Screens? Since we both have MSIs. I'll try to check your values.


----------



## Veii

It's a bios limitation for sure 
I don't think my chip is exceptionally well at all, maybe 28% of 100% on binning - 0-10% being silicon lottery
It needs more voltage for boosting, has two bad cores and IMC is okeish
Every chip should be able to hit 2100+ FCLK
2133 i saw already struggle, 2167 was my hard limit ~ but it could be also just a bios limitation again, as beyond 2100 you start to have 2:1 mode "bugs"


----------



## kingmob

How's this looking boys. Obviously need more lengthy testing to confirm.


----------



## Dasa

kingmob said:


> How's this looking boys. Obviously need more lengthy testing to confirm.


There is others that know more than me but I will take a stab at what I see and it will be interesting to see if they make any other changes or see a mistake in my suggestion.

See how you go with GDM disabled for a start.

You can probably drop
tRP to ~13
tCWL to 12 but for this you would need to raise tRDWR 10
tCKE 1
tRFC 260-275 depends on what VDIMM you are running though.
tRDRD## 4
Both #####SCL 3-4
CLDO VDDP 825-900

Most seem to gain stability with RttPark RZQ/1 although on a early BIOS my system did better with 2 and RttWR RZQ/3
~30-40 for ProcODT seems to be suggested.


----------



## mus1mus

At 3733, you don't need GDM ON. Turn it OFF and try the primary as the ff:
TCL 14
TRCDRD 16 - safe can go lower depending on your VDIMM and memory quality
TRCDWR 8
TRAS 14
1T

B-Die TRFC can go down to 233 or even lower. Just observe if there are drops in latency figures 
FIX your SCLs to both as 4
TCWL - 9 or 11

Always test before making further changes and save known good profiles.


----------



## Hale59

Any guidance/suggestions about is appreciated.
G.Skill F4-3600C16-32GTZN - using 1 stick only


----------



## Alyjen

Veii said:


> 3733C15 = 3534MT/s C14
> 1T is harder than 2T
> 3734C14 would need about 75-90mV more than what you run, soo probably near 1.46-1.47v


Help  this is best I have after 2 hours of trials and errors today, memory voltage is 1.45V

GDM:OFF, 1T, performance is there, and it's not instant crashing, BUT it's not stable either :/ sooner or later, but usually before 10 minutes (3rd to 4 pass) TM5 with 1usmus_v3 config gives me some kind of error. Not that they go in tens, but one error here and there. 

One time it went for over 30 minutes without any error it was when I set only main timings and everything else was on auto (which for ASUS is super high, like tRDWR 18, tFAW 40 etc.)

How should I approach it?


----------



## DeletedMember558271

Is it really normal that I'm stable at these settings 1.36v (3733 16-16-16-16-32-48) but I need to go all the way to *1.53v* for 3733 14-14-14-14-28-42? Only changing those 6 timings nothing else requires that much more voltage not to error. I don't know how people are at even higher like 3800C14 with 1.5v or less. Not mention I question if any of these peoples setups would be stable in my case or full system load, as even with a Noctua NF-A14 blowing directly on the RAM it will still heat up enough to error once you get the GPU & CPU also under heavy load for a while like if you're playing a game with uncapped FPS it will heat up your whole room, Asus 3080 TUF.








1.35v locked up the system 5 minutes in and 1.34v struggled to load Windows and test errored when it did.
I know GDM Off probably requires a lot of work and changing settings but I was curious just how close to stable it would be if I turned it off and yep it errors like crazy with these settings even at 1.5v


----------



## Alyjen

Dreamic said:


> Is it really normal that I'm stable at these settings 1.36v (3733 16-16-16-16-32-48) but I need to go all the way to *1.53v* for 3733 14-14-14-14-28-42? Only changing those 6 timings nothing else requires that much more voltage not to error. I don't know how people are at even higher like 3800C14 with 1.5v or less. Not mention I question if any of these peoples setups would be stable in my case or full system load, as even with a Noctua NF-A14 blowing directly on the RAM it will still heat up enough to error once you get the GPU & CPU also under heavy load for a while like if you're playing a game with uncapped FPS it will heat up your whole room, Asus 3080 TUF.
> View attachment 2470793
> 
> 1.35v locked up the system 5 minutes in and 1.34v struggled to load Windows and test errored when it did.
> I know GDM Off probably requires a lot of work and changing settings but I was curious just how close to stable it would be if I turned it off and yep it errors like crazy with these settings even at 1.5v


Yes, jump from CL16 to CL14 is HUGE when it comes to voltage. People who have it stable at 1.5V usually have better luck in silicon lottery.
Then having stable OC at 1.5V+ that's another lucky draw, doing all of the above with 4 sticks, that's just hard.
We have same kits, Patriot have very cheap heatsinks, and quite often you can get a kit where this adhesive thermal compound is not even covering the whole die, so there's air between some of the dies and heatsink as a result you get timings that are bench stable, but will overheat.

edit: tRCDRD is the biggest blocker, leave it at 15 (14-14-15-14-28-42) and you should get away with lower voltage, I'm testing these right now, and it looks way better than flat 15 GMD:OFF
currently at 1.48V but it was a shoot as I needed something above 1.45 not really sure how much, I'll try to lower it later. 
also some sub still need adjustment.


----------



## mus1mus

Yes, TRCDRD is sometimes the culprit with B-Dies if you can't post or need higher VDIMM over 3600. If you look back a few pages, my settings show 14-17-8-14 for 3800 on my old B-Die. 

Actually, even on Hynix, TRCDRD changes require higher VDIMM changes to stabilize.

@Alyjen, try to set TCWL to 9. TRCDRD to 16 and GDM OFF. You might be able to drop VDimm to 1.45. Or touch 3800.


----------



## Alyjen

mus1mus said:


> Yes, TRCDRD is sometimes the culprit with B-Dies if you can't post or need higher VDIMM over 3600. If you look back a few pages, my settings show 14-17-8-14 for 3800 on my old B-Die.
> 
> Actually, even on Hynix, TRCDRD changes require higher VDIMM changes to stabilize.
> 
> @Alyjen, try to set TCWL to 9. TRCDRD to 16 and GDM OFF. You might be able to drop VDimm to 1.45. Or touch 3800.


I need to rest for a while and test if what I did today is really stable, managed to complete few TM5 runs while I was fixing subs and tRFC 
AIDA latency is at 53.5, but other than that I don't think it's any real life difference  

I could do 3800 right now, but if I set FCLK to 1900 I'm still getting occasional whea 19 warning, while it's at 3733 I haven't seen any for over a week. 

and yes, next time I'll go after GDM:OFF I'll start from tRCDRD 16, so something like 15-15-16-15-30-45


----------



## DeletedMember558271

Alyjen said:


> Yes, jump from CL16 to CL14 is HUGE when it comes to voltage. People who have it stable at 1.5V usually have better luck in silicon lottery.
> Then having stable OC at 1.5V+ that's another lucky draw, doing all of the above with 4 sticks, that's just hard.
> We have same kits, Patriot have very cheap heatsinks, and quite often you can get a kit where this adhesive thermal compound is not even covering the whole die, so there's air between some of the dies and heatsink as a result you get timings that are bench stable, but will overheat.
> 
> edit: tRCDRD is the biggest blocker, leave it at 15 (14-14-15-14-28-42) and you should get away with lower voltage, I'm testing these right now, and it looks way better than flat 15 GMD:OFF
> currently at 1.48V but it was a shoot as I needed something above 1.45 not really sure how much, I'll try to lower it later.
> also some sub still need adjustment.
> 
> View attachment 2470799


I'm not having luck with such settings even at 1.51v, which is probably still too hot anyway.
I think I'm just going to keep an eye on this Zen Overclocking Spreadsheet and wait for a better BIOS for 1900+ FCLK.
These are all the 4x8GB results so far, I have the best by far as everything about Lepe's is invalid if you look at the screenshot he provided on the doc, he doesn't even have 4 sticks...








I basically have copied shadowie's settings from the ZenTimings screenshot he provided for now, and will keep watch for something better to copy.
Seems a lot of people have no idea what they're doing but submit anyway, lots of worse results/latency with somehow lower timings.
I seem to be only one stuck at 3733 somehow... impossible to post 1900. Nobody else is on a MSI board though besides a couple on the Unify which I believe has got a more capable BIOS, my B550 Tomahawk hasn't had an update since Nov 16th and the BIOS before that is WHEA errors above 3200.
Besides the invalid 4000 result most are hitting 3800 and then some guy at 3833 but with a trash result.
So this is what I'm running now:


----------



## Veii

Alyjen said:


> Help  this is best I have after 2 hours of trials and errors today, memory voltage is 1.45V
> 
> GDM:OFF, 1T, performance is there, and it's not instant crashing, BUT it's not stable either :/ sooner or later, but usually before 10 minutes (3rd to 4 pass) TM5 with 1usmus_v3 config gives me some kind of error. Not that they go in tens, but one error here and there.
> 
> One time it went for over 30 minutes without any error it was when I set only main timings and everything else was on auto (which for ASUS is super high, like tRDWR 18, tFAW 40 etc.)
> 
> How should I approach it?
> 
> View attachment 2470785


If you would have only provided the errors. I can kinda decrypt them most of the times
You struggle because tRRD_ and tWTR_ is very low
Your kit should be capable of that but still, it's low. Especially tWTR_L

Usually RTT_Park RQZ/5 should be enough at this "low" MT/s
Try my current settings , but they are not suited for low voltage
RTT 7/0/6
CAD_BUS 60-20-40-20

If VDDG CCD is 940mV - give IOD a bit more, 1060mV is your target ~ unless you are trying something else
Try a bit higher proc, 34 for now till you can stabilize 3800

Memory training is very broken. but CsOdtDrvStr 40 seems to make it work most of the times
24 is apparently still too low. With it i get 1/5 tries a successful training on 2100, and continues success on 2000ish
(yes apparently even the old 1.1.0.0 Patch B, the "good one" had broken memory training...)

Try to hit 1900 with BLCK bump and 30mV positive vCore (offset)
Just to check if it's an ABL bug, or simply broken memory training
tWR 10 is also too low - 12+ at 3800 range unless you know your timings are perfect and tRFC is low enough to use tWR 10

@Dreamic - yes i'm one of these 3800C14 people ~ and it is stable 
But 4200C16 is far harder :')
Memory will destabilize between 1.49-1.52 unless you use correct RTT & CAD settings
1.5v for 3800C14 flat is common
I need about 1.51-1.52 (up to settings) for 4200C16=3800C14
1.53 destabilizes everything. 1.56 makes my ICs hardcrash, and i lose the lanes
(lucky memory survived, but high voltage is not always helping)

Although i think i'll stay at lower speeds, as fabric is not ready for 2100, slows itself down (bugs)


----------



## DeletedMember558271

Veii said:


> @Dreamic - yes i'm one of these 3800C14 people ~ and it is stable
> But 4200C16 is far harder :')
> Memory will destabilize between 1.49-1.52 unless you use correct RTT & CAD settings
> 1.5v for 3800C14 flat is common
> I need about 1.51-1.52 (up to settings) for 4200C16=3800C14
> 1.53 destabilizes everything. 1.56 makes my ICs hardcrash, and i lose the lanes
> (lucky memory survived, but high voltage is not always helping)
> 
> Although i think i'll stay at lower speeds, as fabric is not ready for 2100, slows itself down (bugs)


My 3733C14 flat is 100% stable too at 1.53v (reported as 1.516-1.520v), until you start adding more temperature to it from GPU & CPU. If they were both watercooled instead of exhausting all of the heat into the case, I think I would be fine, but the RAM just can't handle all the heat the 3080 puts out, pushes it over the edge. Or if I had a less power hungry GPU like a 3070 or less, could also be stable. Case ambient temp just gets too high so I'm trying 1.45v which seems fine but not for 3733C14


----------



## Veii

Dreamic said:


> My 3733C14 flat is 100% stable too at 1.53v (reported as 1.516-1.520v), until you start adding more temperature to it from GPU & CPU. If they were both watercooled instead of exhausting all of the heat into the case, I think I would be fine, but the RAM just can't handle all the heat the 3080 puts out, pushes it over the edge. Or if I had a less power hungry GPU like a 3070 or less, could also be stable. Case ambient temp just gets too high so I'm trying 1.45v which seems fine but not for 3733C14


1.48 would probably be needed
But you can really just go for CL15 flat and later optimize it a bit
ClkDrvStr does warm up everything , but as exchange - you need less VDIMM
40-20-30-20 instead of 60

Maybe 40-24-24-24 for your setup
and bit higher proc, to help with VDIMM

You can also just increase tRFC and then focus to lower tRDWR & SCL , to gain lower latency
There are coupe of things you can do to get it stable under lower voltage
Slower tWR doesn't always have to result in lower latency
Just keep it a clean divider of tRFC
tRTP the same, clean divider for "baseline" work
CL15 i think would need around 1.45-1.46v at this speed

3600CL12 i've tried , but memory training is too "stupid" on it's current state
Beyond 3400C12 it's just not an option
Till around 2070Mhz FCLK you have positive scaling - 2080-2090 starts to be messy. 2100 is plain buggy and a pure mess right now
Play with BLCK more. There are too many FCLK bugs currently. 1833 + 102 BLCK likely will perform better and boost Single Core perf a bit more
Just for BCLK work, give it a bit more vCore (25-35mV positive offset) to cover the shift on stock ~ without having to touch PBO

EDIT:
Or you go back to GDM; enable power down - stay on tCKE 6
and lower tRFC sub *6 multiplier
GDM on will run MUX chips at half speed, soo the chance of thermal crashing will also be lower 
But you have to work with even timings to skip double and tripple auto correction
I mean it's bearable, not that bad ~ just have to think a bit different when you change timings


----------



## VPII

Dreamic said:


> I'm not having luck with such settings even at 1.51v, which is probably still too hot anyway.
> I think I'm just going to keep an eye on this Zen Overclocking Spreadsheet and wait for a better BIOS for 1900+ FCLK.
> These are all the 4x8GB results so far, I have the best by far as everything about Lepe's is invalid if you look at the screenshot he provided on the doc, he doesn't even have 4 sticks...
> View attachment 2470822
> 
> I basically have copied shadowie's settings from the ZenTimings screenshot he provided for now, and will keep watch for something better to copy.
> Seems a lot of people have no idea what they're doing but submit anyway, lots of worse results/latency with somehow lower timings.
> I seem to be only one stuck at 3733 somehow... impossible to post 1900. Nobody else is on a MSI board though besides a couple on the Unify which I believe has got a more capable BIOS, my B550 Tomahawk hasn't had an update since Nov 16th and the BIOS before that is WHEA errors above 3200.
> Besides the invalid 4000 result most are hitting 3800 and then some guy at 3833 but with a trash result.
> So this is what I'm running now:
> View attachment 2470823


I using a MSI Meg X570 Ace motherboard, the last bios which was released 13 November 2020 but it is beta was the one with which I was able to get 1900 FCLK and UCLK running. The previous bios was throwing WHEA errors like crazy, but now all good. The timings I am using now is actually a little better as in 16-15-15-15-30 and latency is also better.


----------



## KedarWolf

VPII said:


> I using a MSI Meg X570 Ace motherboard, the last bios which was released 13 November 2020 but it is beta was the one with which I was able to get 1900 FCLK and UCLK running. The previous bios was throwing WHEA errors like crazy, but now all good. The timings I am using now is actually a little better as in 16-15-15-15-30 and latency is also better.
> View attachment 2470857


Why is your latency so high? Peeps getting 55ns in some cases. 

Might be the FLCK bug where it's not really running 1/1 synced even though BIOS says it is. :/


----------



## Veii

KedarWolf said:


> Why is your latency so high? Peeps getting 55ns in some cases.
> 
> Might be the FCLK bug where it's not really running 1/1 synced even though BIOS says it is. :/


Likely.
But 50ns on 1:1 with tRCD 15 is a bit too low. (-10ns 2:1 delay)
Strange for sure. Could be the high proc
I hit 54ns on 3600 C14 flat SCL 2 tRDWR 7. SCL 4 pushes it to 54.8 @ 4.65Ghz
58ns could be expected from 3800C16, but it's likely near 56ns with the 200mhz higher bump.

For memory training fix use CsOdtDrvStr 40 or even 60 when you go tRCD 13 or 12
24 is too low - and memory training is borked since Patch B. Much worse after Patch C
40Ω seems to fix it ~ 60-20-40-20 for example


----------



## KedarWolf

Veii said:


> Likely.
> But 50ns on 1:1 with tRCD 15 is a bit too low. (-10ns 2:1 delay)
> Strange for sure. Could be the high proc
> I hit 54ns on 3600 C14 flat SCL 2 tRDWR 7. SCL 4 pushes it to 54.8 @ 4.65Ghz
> 58ns could be expected from 3800C16, but it's likely near 56ns with the 200mhz higher bump.
> 
> For memory training fix use CsOdtDrvStr 40 or even 60 when you go tRCD 13 or 12
> 24 is too low - and memory training is borked
> 40 seems to fix it ~ 60-20-40-20 for example


Oh, I thought the AIDA pic said 60ns, it's fuzzy.


----------



## Veii

KedarWolf said:


> Oh, I thought the AIDA pic said 60ns, it's fuzzy.


No it's true, 60ns
but 2:1 mode adds 10ns ontop
2:1 bug triggers for me automatically at 2000.9Mhz , even with BLCK push. 2075ish has the best result without added delay

it could be buggy for him, but 2:1 mode would add more delay. And for 50ns his timings are a bit too high
Shouldn't be a 2:1 mode bug


----------



## Veii

Fooling around 
This is a baseline for people.
54.2ns is a flat C14 set
Read is maxed, Copy is 28799 of 28800, Write needs still work
My Core's [allcore] are slow under stock EDC limit ~ ignore the testing duration
just pushing the timings for people who want to replicate


----------



## VPII

KedarWolf said:


> Why is your latency so high? Peeps getting 55ns in some cases.
> 
> Might be the FLCK bug where it's not really running 1/1 synced even though BIOS says it is. :/


It may be, lowest latency I got was like 59.2 but I know it should be better. Will have to check with new bios maybe. But thanks for pointing that out.


----------



## Alyjen

Veii said:


> If you would have only provided the errors. I can kinda decrypt them most of the times
> You struggle because tRRD_ and tWTR_ is very low
> Your kit should be capable of that but still, it's low. Especially tWTR_L
> 
> Usually RTT_Park RQZ/5 should be enough at this "low" MT/s
> Try my current settings , but they are not suited for low voltage
> RTT 7/0/6
> CAD_BUS 60-20-40-20
> 
> If VDDG CCD is 940mV - give IOD a bit more, 1060mV is your target ~ unless you are trying something else
> Try a bit higher proc, 34 for now till you can stabilize 3800
> 
> Memory training is very broken. but CsOdtDrvStr 40 seems to make it work most of the times
> 24 is apparently still too low. With it i get 1/5 tries a successful training on 2100, and continues success on 2000ish
> (yes apparently even the old 1.1.0.0 Patch B, the "good one" had broken memory training...)
> 
> Try to hit 1900 with BLCK bump and 30mV positive vCore (offset)
> Just to check if it's an ABL bug, or simply broken memory training
> tWR 10 is also too low - 12+ at 3800 range unless you know your timings are perfect and tRFC is low enough to use tWR 10


Ok, noted down and will try some of it later  now that I have Windows on USB stick I'm not that afraid of OS corruption 

VDDG CCD & other voltages are now on auto. They seem fine maybe apart from CLDO VDDP that Asus tends to set on 1V, and I was working for weeks with 0.9V - worth lowering this one, or let it be?

I'm not playing with this currently as my story of high IF with recent BIOS is:
1866 - no errors, y-cruncher stable, prime95 stable, normal use stable, not a single whea warning 
1900 - some warnings, like few per week, hard to force, prime95 - no errors, but y-cruncher 1-2 warnings per run
1933+ - warnings everywhere, tens of errors while in idle, but I can boot up to 2000 on default settings 
So I decide to let it be and focus on having proper memory profile for 3733 

Below is what I tested yesterday, next time I'll note down errors, but they were mostly 2, 6, 12 (if I was getting closer) and all around the place if I was further away with settings.

I'm at 1.48V currently so the settings you pointed out that are aggressive (tWTR S/L) are even lower and it's still stable but. tRRDS/S tFAW combo I was using for weeks with CL16 at 1.4V no issues. Dram calc suggest even more aggressive tRRDS 3 tFAW 12 

but, it seems fine, it's somehow faster than 3733CL16, but not by a lot, it's slower than 3733CL15 GDM:OFF, so I think there may be some diminishing returns I hit.


----------



## Yviena

Are there any recommendations for RTT values on the new 5xxx series with x570, and 4 sticks single rank b-die?

I hope to be able to get my 3200 C14 A1 PCB sticks under 54ns.


----------



## Dasa

Yviena said:


> Are there any recommendations for RTT values on the new 5xxx series with x570, and 4 sticks single rank b-die?
> 
> I hope to be able to get my 3200 C14 A1 PCB sticks under 54ns.


I am running 4x8 3200c14 A1 on a B550 Aorus pro and for me 7\3\1 seems to be best on the current BIOS although 7\3\2 was better on a early BIOS.
Your board\sticks may prefer some values varied from that but see if that improves stability vs auto.


----------



## thegr8anand

I changed from a 3900x to 5900x few days back. I put in ram timings that 1.5 year back i could tighten as much as i could, seem to be working fine except the latency seems higher than others. Voltage is also 1.49v.

I just a quick ram test but these timings were tested thoroughly before and will do the same later if latency could be improved.









Timings test back in Aug-19. At the time i was unable to hit 3800 and was already using high voltages. Didn't think the timings could be as tight by moving to 3800 from 3733 so never tried afterwards and have been using it since then. I see user @craxton is running 4000 with the exact same ram so maybe i can now but will it be such an improvement?


Spoiler


----------



## craxton

thegr8anand said:


> I changed from a 3900x to 5900x few days back. I put in ram timings that 1.5 year back i could tighten as much as i could, seem to be working fine except the latency seems lower than others. Voltage is also 1.49v.
> 
> I just a quick ram test but these timings were tested thoroughly before and will do the same later if latency could be improved.
> View attachment 2470942
> 
> 
> Timings test back in Aug-19. At the time i was unable to hit 3800 and was already using high voltages. Didn't think the timings could be as tight by moving to 3800 from 3733 so never tried afterwards and have been using it since then. I see user @craxton is running 4000 with the exact same ram so maybe i can now but will it be such an improvement?
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2470944


considering my L3 cache is trash, i cant say myself for sure, but i do know from 3800 to 4000 mhz i had improvements however, i have a b550 msi board now that im about to swap out my current x570 gaming edge wifi board for as its quite a bit better at ram overclocking, and features in general. if my timings were set correctly other than what they are stable now my score may go up. but thats not proven on my end yet. will update shortly after installing board and getting up and running. my tforce dark pro kit is the 14,14,14,14,31 kit not the 14,14,14,14,34 version...unsure what the big differences are or if there is an actual difference period just thought id share that info.


----------



## thegr8anand

Mine is Nighthawk Legend but same timings 14-14-14-31.


----------



## Hale59

Hale59 said:


> Any guidance/suggestions about is appreciated.
> G.Skill F4-3600C16-32GTZN - using 1 stick only
> 
> View attachment 2470742
> View attachment 2470743
> View attachment 2470744


Can I get some suggestions here please.


----------



## mus1mus

Use 2 sticks.


----------



## thegr8anand

thegr8anand said:


> I changed from a 3900x to 5900x few days back. I put in ram timings that 1.5 year back i could tighten as much as i could, seem to be working fine except the latency seems higher than others. Voltage is also 1.49v.
> 
> I just a quick ram test but these timings were tested thoroughly before and will do the same later if latency could be improved.
> View attachment 2470942
> 
> 
> Timings test back in Aug-19. At the time i was unable to hit 3800 and was already using high voltages. Didn't think the timings could be as tight by moving to 3800 from 3733 so never tried afterwards and have been using it since then. I see user @craxton is running 4000 with the exact same ram so maybe i can now but will it be such an improvement?
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2470944


Need your thoughts @mus1mus @Veii


----------



## Hale59

mus1mus said:


> Use 2 sticks.


If that reply was for me, there are no 2 sticks at moment.
I am more concerned about the timings.


----------



## mus1mus

Hale59 said:


> If that reply was for me, there are no 2 sticks at moment.
> I am more concerned about the timings.


You are losing a lot of perf using a single stick.

For timings,
TRFC can go lower to 233
TWTRL and TWR can both go lower to 8
TCWL 9
TRCDWR 8




thegr8anand said:


> Need your thoughts @mus1mus @Veii


Latency results are somewhat OS dictated. A Clean OS always score better.
You can try the above.
Are you sure of those SCLs? They may be showing that but could have been replaced arbitrarily by the board. I can't even boot with SCL 3 after 3600.  Try 4



VPII said:


> I using a MSI Meg X570 Ace motherboard, the last bios which was released 13 November 2020 but it is beta was the one with which I was able to get 1900 FCLK and UCLK running. The previous bios was throwing WHEA errors like crazy, but now all good. The timings I am using now is actually a little better as in 16-15-15-15-30 and latency is also better.
> View attachment 2470857


I use the same BIOS.


----------



## thegr8anand

mus1mus said:


> Latency results are somewhat OS dictated. A Clean OS always score better.
> You can try the above.
> Are you sure of those SCLs? They may be showing that but could have been replaced arbitrarily by the board. I can't even boot with SCL 3 after 3600.  Try 4


It does show the same in bios but will try changing to 4 if it makes a difference. Correct about latency. It was originally 59 for me and only dropped to 57 after closing steam/origin/etc. But still far away from some numbers i see around 53ns.

Also what do you think about L1/L2/L3 numbers. Compared to other 5900x/5950x numbers (MB/s) i have seen my L1/L2 are lower but L3 higher. Why could that be?


----------



## mus1mus

L1 is CPU Core Clock dependent from what I can see.

They are also dependent on the version of Aida 64 used.


----------



## Veii

SCL's are PCB dependent
They scale upwards up to used frequency
They can not be faked.
Same goes for tRDWR which depends on IC - primaries & PCB
SCLs do not depend on the ICs much
Even HynixMfr can run SCL 2-2


----------



## Veii

Hale59 said:


> Can I get some suggestions here please.


You can try if you get that one to boot 


Spoiler














tRP 12 at this freq mostly needs around 1.52-1.55v
Gdm off should help it run 120ns trfc
Later you can drop SCL down to 2-2
Might even be able to run it off trdwr 9 - twtr 3 (SCL 2) or 4 (SCL 3)
_working atm on it - remaking it with my dimms and gdm off
~ as nearly no one could run it without gdm_


----------



## xVanilla

Any G.Skill Flare X 3200 CL14 32gb owners here who OC their dimms? would be interested in your results!


----------



## craxton

thegr8anand said:


> Mine is Nighthawk Legend but same timings 14-14-14-31.


how much did you pay for the kit? if you dont mind me asking??


----------



## thegr8anand

craxton said:


> how much did you pay for the kit? if you dont mind me asking??


Way too much. Prices were high back in July 19 and it cost around $145 and another $110 for duty and shipping to my country.


----------



## halcyonon

Veii said:


> Fooling around
> This is a baseline for people.
> 54.2ns is a flat C14 set
> Read is maxed, Copy is 28799 of 28800, Write needs still work
> My Core's [allcore] are slow under stock EDC limit ~ ignore the testing duration
> just pushing the timings for people who want to replicate
> View attachment 2470875


Why is your write score half of read? Is that due to 2T?


----------



## Comalive

halcyonon said:


> Why is your write score half of read? Is that due to 2T?


That is because of his CPU, it has only one CCD.


----------



## mirzet1976

Comalive said:


> That is because of his CPU, it has only one CCD.


Older SMU, here is mine but this bios is no longer available to download on Asus site now is latest beta bios 1216.


----------



## halcyonon

Comalive said:


> That is because of his CPU, it has only one CCD.


Ahhhh I had no idea that also impacted memory performance, thanks.


----------



## Gadfly

Anyone have a good base timing set for 2x16gb b-die to post at 2000mhz (4000)?

I have a set of older 16GB 3200C14 B-dies (A0 pcb) I am trying to get to run at 4000 and I think I am missing something. I can post and run stable at 3800C14, I can run stable at 3866C16, but 3933+ at any timings will not post at all. 

Thanks in advance for any zen timings ss of 2x16gb at 4k.


----------



## Hale59

Veii said:


> You can try if you get that one to boot
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRP 12 at this freq mostly needs around 1.52-1.55v
> Gdm off should help it run 120ns trfc
> Later you can drop SCL down to 2-2
> Might even be able to run it off trdwr 9 - twtr 3 (SCL 2) or 4 (SCL 3)
> _working atm on it - remaking it with my dimms and gdm off
> ~ as nearly no one could run it without gdm_


What now?
Just to remind you this is dual rank.
And for those saying 2 sticks is better...my dog decided to oc the other stick.
RAM voltage ~n Bios is 1.55v, but mobo puts it up 2 notches.


----------



## mus1mus

Hale59 said:


> What now?
> Just to remind you this is dual rank.
> And for those saying 2 sticks is better...my dog decided to oc the other stick.
> RAM voltage ~n Bios is 1.55v, but mobo puts it up 2 notches.


Hmmm. Can't really see your point here. Your figures including latency are worse than my Hynix Dual ranks. 




mirzet1976 said:


> Older SMU, here is mine but this bios is no longer available to download on Asus site now is latest beta bios 1216.
> View attachment 2471180


Very nice old friend. Very nice seeing you back...


----------



## t4t3r

Gadfly said:


> Anyone have a good base timing set for 2x16gb b-die to post at 2000mhz (4000)?
> 
> I have a set of older 16GB 3200C14 B-dies (A0 pcb) I am trying to get to run at 4000 and I think I am missing something. I can post and run stable at 3800C14, I can run stable at 3866C16, but 3933+ at any timings will not post at all.
> 
> Thanks in advance for any zen timings ss of 2x16gb at 4k.


A0 doesn’t scale well above 4000mhz so you just may be running into a pcb layout wall although I’d be surprised they would just fall off a cliff right at 4000. You didn’t mention what voltage so if you’re not feeding them at least 1.5, 3200 sticks may need even more to hit 4000. Same for your board as you didn’t mention what you’re using but 2x16 will be tougher to run as you go up in speed as well.


----------



## halcyonon

I've got some Corsair Dominator Platinum RGB sticks, 4x16GB (64GB total), rated at [email protected] 1.35V, they are B-die. Running them on a Dark Hero with 5950x.

Current stable Karhu run at 17.5hours, running 1.38v:









Would appreciate any suggestions on next steps of what to incrementally improve and test for stability. 

I've tried the fast and safe timings from the Ryzen calculator for B-die A2 2 rank with 4 dimms, but not had luck getting them stable, with voltage up into the 1.42-1.44v range and GDM on. My 2 inner sticks are warm, 58C currently at 1.38V, and only get warmer with more voltage, despite having a 120mm rad exhaust fan right next to them. Case temp is 34C.

Thanks!


----------



## Gadfly

t4t3r said:


> A0 doesn’t scale well above 4000mhz so you just may be running into a pcb layout wall although I’d be surprised they would just fall off a cliff right at 4000. You didn’t mention what voltage so if you’re not feeding them at least 1.5, 3200 sticks may need even more to hit 4000. Same for your board as you didn’t mention what you’re using but 2x16 will be tougher to run as you go up in speed as well.


Yep, all true, was looking to see if anyone had a 2x16gb running at 2000mhz. 

I have a similar issue with 4x8gb as well. I can run 1933mhz at 14-14-12-28 without any issues, but I can even post at 2000mhz. 

Thus far the only way I have been able to run at 2000mhz memclk is 2x8gb; which sucks as I need 32gb of ram.

My fclk will run upto 2100mhz. I can run 2000mhz fclk without error at 0.95v vddg ccd, and 0.985v vddg iod, soc 1.1v, pll 1.9v so I was really hoping to find a way to run 32gb of memory at 2000mhz.


----------



## Comalive

Gadfly said:


> Yep, all true, was looking to see if anyone had a 2x16gb running at 2000mhz.
> 
> I have a similar issue with 4x8gb as well. I can run 1933mhz at 14-14-12-28 without any issues, but I can even post at 2000mhz.
> 
> Thus far the only way I have been able to run at 2000mhz memclk is 2x8gb; which sucks as I need 32gb of ram.
> 
> My fclk will run upto 2100mhz. I can run 2000mhz fclk without error at 0.95v vddg ccd, and 0.985v vddg iod, soc 1.1v, pll 1.9v so I was really hoping to find a way to run 32gb of memory at 2000mhz.


I can run my 4x8GB sticks at 4000 1.39v with 2000 fclk. Memtests are fine, I just cannot get it to consistently survive stress tests. The memory side of things is fine for me, but the fclk is what leads to crashes during stress tests for me.


----------



## Gadfly

Comalive said:


> I can run my 4x8GB sticks at 4000 1.39v with 2000 fclk. Memtests are fine, I just cannot get it to consistently survive stress tests. The memory side of things is fine for me, but the fclk is what leads to crashes during stress tests for me.


Can you post your zen timings SS? + any other changes you made?


----------



## Comalive

Gadfly said:


> Can you post your zen timings SS? + any other changes you made?











Imagine this at 4000/2000, tRRDS/L were at 5/7 and tWR was at 26 I believe.


----------



## Gadfly

Comalive said:


> View attachment 2471194
> 
> Imagine this at 4000/2000, tRRDS/L were at 5/7 and tWR was at 26 I believe.


Intreasting, I never tried 7/2/3 on the RTT's. I will give it a shot.


----------



## Comalive

Gadfly said:


> Intreasting, I never tried 7/2/3 on the RTT's. I will give it a shot.


All of those are just on auto for me. I've tried different combinations of the usual ProcODT, rtt and DrvStr settings you find recommended everywhere... while my auto values look quite different, they just work so that's fine with me there. Might wanna try what auto values your board gives you.


----------



## Dasa

My 4x8GB 3200c14 A0 can boot at 4400 unstable and passed some stability tests at 4266 16-18-18 outside of 1:1 but with 1:1 The max it has gone is 4090 116-18-18 but with WHEA errors due to BIOS but the RAM itself seems stable.


----------



## Comalive

mirzet1976 said:


> Older SMU, here is mine but this bios is no longer available to download on Asus site now is latest beta bios 1216.
> View attachment 2471180


Are you planning on tuning your memory further? Looking at the benchmark results, there should be some headroom left.


----------



## Gadfly

Dasa said:


> My 4x8GB 3200c14 A0 can boot at 4400 unstable and passed some stability tests at 4266 16-18-18 outside of 1:1 but with 1:1 The max it has gone is 4090 116-18-18 but with WHEA errors due to BIOS but the RAM itself seems stable.


Can you share a zen timings on the 4400 unstable set up? I'd like to see the RTT's / ClkDrvStr etc. You used.


----------



## Hale59

mus1mus said:


> Hmmm. Can't really see your point here. Your figures including latency are worse than my Hynix Dual ranks.


There is no point at all.
Just trying to follow @Veii directions.


----------



## Hale59

@Veii 
Followed your suggestions but it gives me errors on TM5.
And I had to increase voltage to 1.56.


----------



## VPII

Hale59 said:


> What now?
> Just to remind you this is dual rank.
> And for those saying 2 sticks is better...my dog decided to oc the other stick.
> RAM voltage ~n Bios is 1.55v, but mobo puts it up 2 notches.
> View attachment 2471185
> View attachment 2471183
> 
> View attachment 2471184


Hi @Hale59 I am getting a little p....d with this Pasmark Performance test. My result is rediculously high but for some reason just after the first 3d test the fnal scene would hang while the test continue to run. Not sure why, I tried various means by which to bypass it but not go it keep happening.


----------



## VPII

@Hale59 just to show you.... I







cannot even move anything in the bench as the moment I go off it, it shows the final scene of the first 3d test taking over half or more of the screen.


----------



## Merutsu

xVanilla said:


> Any G.Skill Flare X 3200 CL14 32gb owners here who OC their dimms? would be interested in your results!


Haven't tested above 3800 yet, just updated to agesa 1.1.9.0 and overclocked the ram, seems it's stable at 3800mhz cl16 1.436V


Spoiler















Both sticks from kit what I've got had gaps between memory chips and heatsink on one side, so I swapped heatsinks with a custom and more efficient. Now temp. is ~40C max.


Spoiler


----------



## Hale59

VPII said:


> @Hale59 just to show you.... I
> View attachment 2471234
> cannot even move anything in the bench as the moment I go off it, it shows the final scene of the first 3d test taking over half or more of the screen.


Looks like that the ram I sold you are doing well.
I had my dog chewing my sticks and I salvaged one. Until I get another set I have ro survive with this stick.


----------



## VPII

Hale59 said:


> Looks like that the ram I sold you are doing well.
> I had my dog chewing my sticks and I savaged one. Until I get another set I have ro survive with this stick.


Shame that is not nice.... yes the memory works great, I cannot complain. Running all 4 sticks 3800 CL16 so all good.


----------



## Hale59

@Veii
TM5 1T gives me errors.
First time I tried TM5 with 1T, it gave me an error, but did not show on the test number. Then gave me a blue screen, and telling me something is wrong.
Increased voltage to 1.56 in Bios (HWinfo is 1.58). From there no more problems with reboots.

TM5 2T passes with no errors.

However, I cannot lower trdwr to 9 on both of them.

Waiting for more suggestions. Thanks


----------



## Dasa

Gadfly said:


> Can you share a zen timings on the 4400 unstable set up? I'd like to see the RTT's / ClkDrvStr etc. You used.


Looks like I only save 4266 which should have similar settings.
From memory I may have raised ProcODT and the three V below VSOC a bit.
VDIMM would have been ~1.5v











Hale59 said:


> However, I cannot lower trdwr to 9 on both of them.


tRDWR is related to tCWL
I cant go below 11 with tCWL at 12 and need to run tCWL 14 for tRDWR 9
Also you should try lower your CLDO VDDP to ~800-900


----------



## Gadfly

Dasa said:


> Looks like I only save 4266 which should have similar settings.
> From memory I may have raised ProcODT and the three V below VSOC a bit.
> VDIMM would have been ~1.5v
> View attachment 2471325
> 
> 
> 
> tRDWR is related to tCWL
> I cant go below 11 with tCWL at 12 and need to run tCWL 14 for tRDWR 9
> Also you should try lower your CLDO VDDP to ~800-900


Thanks, I can run 2x8gb to 2400mhz or higher, but 4x8gb I can't seem to get over 1933 mhz, no matter what I do. I also have some older 3200C14 16GB A0 b-die sticks that I also can't get over 1966 mhz. 

It is really disappointing as I can run 2100mhz fclk, but I need 32gb of ram.

I believe it is the C8H motherboard, and the crappy BIOS.


----------



## Comalive

@Dasa What are you running your memory stable at? Your scores are quite low for that memclk, the 2:1 mode must be an insane performance hit there.


----------



## kratosatlante

[QUOTE = "Gadfly, publicación: 28703286, miembro: 532972"]
Gracias, puedo ejecutar 2x8gb a 2400 mhz o más, pero 4x8gb parece que no puedo superar los 1933 mhz, no importa lo que haga. También tengo algunos sticks antiguos 3200C14 16GB A0 b-die que tampoco puedo superar los 1966 mhz.

Es realmente decepcionante, ya que puedo ejecutar 2100 mhz fclk, pero necesito 32 GB de RAM.

Creo que es la placa base C8H y la BIOS de mierda.
[/CITAR]
yo tienen ch7wif y puede hacer 4067 4x8 sin embargo estable, pero 4000cl6 está bien, puede ser la falla está en el límite de carnero llegar a su


















prueba 4000cl15


----------



## Dasa

Comalive said:


> @Dasa What are you running your memory stable at? Your scores are quite low for that memclk, the 2:1 mode must be an insane performance hit there.


Read\Write speed is bottlenecked by the IF speed.
While copy does go up a little with higher RAM speed when you break 1:1 it is at the expense of latency.

Something around this with the most recent beta BIOS.








Or close to this if I go back to a early beta BIOS with a heap of WHEA errors.









Seems that using a ALL core OC doubles the L3 benchmark score vs using boost which only runs one core at max boost and the rest at idle during the L3 benchmark.


----------



## Pilcsy

Hello

Someone can help what is problem with those timmings?
Testmem 5 gives me lot of error in first cycle
vDIMM: 1,44v

Setup:
R5 3600 (stock)
Asus Prime x570 P (latest 3001 bios)
Crucial 32GB KIT DDR4 3200MHz CL16 Ballistix Black (dual rank, micron e-die)

(sorry, my english is trash)


----------



## Pictus

Pilcsy said:


> Hello
> 
> Someone can help what is problem with those timmings?
> Testmem 5 gives me lot of error in first cycle
> vDIMM: 1,44v
> 
> Setup:
> R5 3600 (stock)
> Asus Prime x570 P (latest 3001 bios)
> Crucial 32GB KIT DDR4 3200MHz CL16 Ballistix Black (dual rank, micron e-die)


HI!
Same RAM here, with my 3600 I had it like this. 
procODT = 43.6
CADs = 60-20-20-24
They are plain newbie settings, but works...
vDIMM 1.44V seems a bit too much for me...









----------------

Now I am using with vDIMM 1.38V 
procODT = 40 
CADs = 40-20-20-24
Asus TUF B550 + Ryzen 5600X(need different voltages) 
VSOC = 1.060V (here works well)
CLDO VDDP = 0.900V (more than enough for 3733MHz) 
VDDG IOD = 1.020V (here works well)
VDDG CCD = 0.900V (seems to not like more than 0.940V)


----------



## VPII

@Hale59 so I've done a complete reinstall of Windows 10 as I had too many funny things happening. I still sit with the problem in the Passmark Performance test where the last scene of the first 3d test freeze on screen but the test continue to run. Still the result now is pretty good.


----------



## Hale59

@Dasa 


> ...tRDWR is related to tCWL
> I cant go below 11 with tCWL at 12 and need to run tCWL 14 for tRDWR 9
> Also you should try lower your CLDO VDDP to ~800-900


What will be the performance impact if I change tcwl to 14 and trdwr to 9?


----------



## KedarWolf

Dasa said:


> Spoiler
> 
> 
> 
> Looks like I only save 4266 which should have similar settings.
> From memory I may have raised ProcODT and the three V below VSOC a bit.
> VDIMM would have been ~1.5v
> View attachment 2471325
> 
> 
> 
> tRDWR is related to tCWL
> I cant go below 11 with tCWL at 12 and need to run tCWL 14 for tRDWR 9
> Also you should try lower your CLDO VDDP to ~800-900





Spoiler






Dasa said:


> Looks like I only save 4266 which should have similar settings.
> From memory I may have raised ProcODT and the three V below VSOC a bit.
> VDIMM would have been ~1.5v
> View attachment 2471325








Dasa said:


> tRDWR is related to tCWL
> I cant go below 11 with tCWL at 12 and need to run tCWL 14 for tRDWR 9
> Also you should try lower your CLDO VDDP to ~800-900


This is tCWL at 12 with tRDWR at 10, I need 9 at lowest for tCWL at 14 though.


----------



## mirzet1976

Hahaha penalty


----------



## Dasa

Hale59 said:


> What will be the performance impact if I change tcwl to 14 and trdwr to 9?


Difference has been to small for me to measure accuratly with run to run variance but then one guide sais to run tCWL within -1 to -2 of tCL and I have tCL at 15 so maybe that has a impact.
Try a few tests at both and let me know what you find.


----------



## Hale59

Dasa said:


> Difference has been to small for me to measure accuratly with run to run variance but then one guide sais to run tCWL within -1 to -2 of tCL and I have tCL at 15 so maybe that has a impact.
> Try a few tests at both and let me know what you find.


I cannot move any of those 2. PC will not reboot into windows.
However I was able to place cldo_vddp to 0.900


----------



## kratosatlante

[QUOTE = "mirzet1976, publicación: 28704621, miembro: 426660"]
Pena jajaja

View attachment 2471582
View attachment 2471583

[/CITAR]
What is your configuration to reach 5025, I could do it only once and it was not stable at all


----------



## mirzet1976

kratosatlante said:


> [QUOTE = "mirzet1976, publicación: 28704621, miembro: 426660"]
> Pena jajaja
> 
> View attachment 2471582
> View attachment 2471583
> 
> [/CITAR]
> What is your configuration to reach 5025, I could do it only once and it was not stable at all


On this motherboard Max CPU Boost Clock Override can go up to 2000 for 5025mhz I enter 375, CPU voltage offset +0.0375 + PBO + Curve optimizer


----------



## craxton

has anyone tried the new bios update for the B550 gaming edge wifi board yet? just updated to the latest release (msi) that was finally done by msi on their b550 board and i must say way better benchmarks and 2000fclk is still possible! No i didnt fix my timings as was suggested but still even with this, stable so far l3 cache is closer to where id call better than it was anyhow. fresh boot btw didnt have time to finish booting before i ran this. so it could be a tad better/worse depending on what i killed or allowed to run.


----------



## sisay

I have 5950x, default in cb20 is 9300.
My edc and tdc is 100% when tested, cpu power only 95w...
I raised tdc to 110 and edc to 160, curve -15 all core = cinebench 20 10200
This result is still worse than the default in the reviews
The temperature during the test was only 63C
The processor is only 3800mhz (with increased power limit) and 3700mhz default during the cinebench test.

I do not know what's going on, so bad silicon lottery?
Asus Strix-e X570 + Noctua D15

Sorry for my English


----------



## Pilcsy

Pictus said:


> HI!
> Same RAM here, with my 3600 I had it like this.
> procODT = 43.6
> CADs = 60-20-20-24
> They are plain newbie settings, but works...
> vDIMM 1.44V seems a bit too much for me...
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ----------------
> 
> Now I am using with vDIMM 1.38V
> procODT = 40
> CADs = 40-20-20-24
> Asus TUF B550 + Ryzen 5600X(need different voltages)
> VSOC = 1.060V (here works well)
> CLDO VDDP = 0.900V (more than enough for 3733MHz)
> VDDG IOD = 1.020V (here works well)
> VDDG CCD = 0.900V (seems to not like more than 0.940V)


Yeah, reducing voltage to 1,37v helps a lot .
1,05v SOC voltage cause WHEA errors so i put 1.07v.
When everything is stable, i reduce VDDG and CLDO voltages too.
I run Testmem5 (1usmus conf) with 40 cycle, then i report back
This is the current state


----------



## DeletedMember558271

sisay said:


> I have 5950x, default in cb20 is 9300.
> My edc and tdc is 100% when tested, cpu power only 95w...
> I raised tdc to 110 and edc to 160, curve -15 all core = cinebench 20 10200
> This result is still worse than the default in the reviews
> The temperature during the test was only 63C
> The processor is only 3800mhz (with increased power limit) and 3700mhz default during the cinebench test.
> 
> I do not know what's going on, so bad silicon lottery?
> Asus Strix-e X570 + Noctua D15
> 
> Sorry for my English


Your CPU isn't boosting, restore BIOS settings to default and make sure nothing in Windows is altering its behavior and see if it boosts then. No such thing as silicon lottery that bad unless it's actually a faulty chip and you need to RMA, something is almost certainly configured incorrectly somewhere keeping it at base clock.


----------



## domdtxdissar

After wasting a few days on bios 3103 for the crosshair viii hero motherboard i'm back to the 3003 bios and have finalized my everyday 24/7 settings.

32gigabyte @ 1900MT/S 4x8gigabyte b-die gskill memory
Prettymuch all timings and voltages are handtuned/maximized/minimized.

Zero errors/WHEA after 1 hour in TestMeM5 with the 1usmus preset. (9 cycles for 32gig)








Screenshot show all settings and voltages, but i can write them also:
dram = 1.56 volt (warmest memorystick reached 44 degrees in TestMeM, normal temp is 32 degrees)
vsoc = 1.1188 volt
cldo vddp = 0.8796 volt
vddg iod = 1.0477 volt
vddg ccd = 0.8796 volt
ProcODT = 43.6

If anyone see something that can be improved/mistakes in the timings, please let me know


----------



## heptilion

@Veii I have come back to bother you again!  I've been trying to stabilize my ram timings for 5950x and would like some advice.

These are the timings that i have been using with my 3800x all this time and it has been stable. dram voltage is at 1.5v 








I tried to run these same settings with my 5950x and instantly got whea bus/interconnect errors which i have managed to fix by dropping vddg ccd voltage to 0.9. anything higher than that i get whea error and this is also what auto setting defaults to.








But after fixing this im now getting errors in tm5. Error on test 1 and 13 after 6-7 cycles. I have tried playing around with proc odt and cad bus strength but no change.


----------



## Alyjen

Quick one guys. How reliable are AIDA latency tests for you? Are they impacted by background programs? Or lets say you can run it 10 times and you'll get same or very similar scores all the time? 
Dram calc memory latency gives me pretty consistent results. AIDA varies and I don't know if it's something worth further investigation.


----------



## Dollar

Alyjen said:


> Quick one guys. How reliable are AIDA latency tests for you? Are they impacted by background programs? Or lets say you can run it 10 times and you'll get same or very similar scores all the time?
> Dram calc memory latency gives me pretty consistent results. AIDA varies and I don't know if it's something worth further investigation.


I have found SOC voltage to affect AIDA latency consistency. For example with borderline but stable SOC voltage I can see the latency jump up by nearly 1ns every third or fourth AIDA latency test but with more SOC voltage I can test 20 times in a row with a stable result that only deviates by 0.1ns from windows being windows. This is reproducible, if I go back and reduce SOC voltage the inconsistent latency returns. And yes, everything should be closed without anything running in the tray.


----------



## IceB

Memory training inconsistencies on X570.
I have built a new machine about 2 months ago : CH8 wifi | 5900x | G.SKILL F4-4000C15Q-32GVK.
Tweaking a RAM takes me a while to get as much stable overclock results as possible. Now - after weeks of tweak, stress, record cycles, my conclusion makes me feel not very comfortable.
Let's say I tweaked the primaries and the secondaries and had a whole bunch of tests : hci 1000%-2000%, hours of prime blend, real bench etc. and all the tests are good. So I have recorded the data on my data sheet and saved the bios profile. The the next cycle comes with whole bunch of tweaks and at some point of time I clear the cmos and load the "stable" profile and rerun the tests - all of the sudden hci memtest returns errors. First I was thinking that my records were inconsistent, but the same pattern showed up again and again with different settings - it is stable at some point, then after clearing the bios and reloading the same settings - it is unstable. I has happened on the previous BIOS i was using 2502, and later on 3003. After switching BIOS version all the settings were dialed manually - no data was loaded from the profile.
I have searched the boards and found several reports on the inconsistencies on the RAM training on AMD platform. How do I manage it with this behavior. Is there any particular order I should consider while saving and applying different BIOS settings or any voodoo magic to get over this inconsistency issue ?


----------



## Alyjen

Dollar said:


> I have found SOC voltage to affect AIDA latency consistency. For example with borderline but stable SOC voltage I can see the latency jump up by nearly 1ns every third or fourth AIDA latency test but with more SOC voltage I can test 20 times in a row with a stable result that only deviates by 0.1ns from windows being windows. This is reproducible, if I go back and reduce SOC voltage the inconsistent latency returns. And yes, everything should be closed without anything running in the tray.


thank's I'll increase VSOC LLC a bit to get better voltage stability and retest 
ok just by disabling HWiNFO & MSI Afterburner my results are consistent 53.x ns if I have these two enabled variance is greater


----------



## Dasa

Alyjen said:


> How reliable are AIDA latency tests for you? Are they impacted by background programs?


background processes have a large impact on it so I run in diagnostic mode then disable windows defender to try get some consistency.


----------



## hsn

Zen timings got error "failed to read AMD ACPI,,some parameter will be empty"

is this bug software or what?


----------



## dr.Rafi

Dollar said:


> I have found SOC voltage to affect AIDA latency consistency. For example with borderline but stable SOC voltage I can see the latency jump up by nearly 1ns every third or fourth AIDA latency test but with more SOC voltage I can test 20 times in a row with a stable result that only deviates by 0.1ns from windows being windows. This is reproducible, if I go back and reduce SOC voltage the inconsistent latency returns. And yes, everything should be closed without anything running in the tray.


VDDGIOD too can pump your Aida memory results.


----------



## craxton

now this is more like it....left is without anything running in the background that windows doesnt need to stay alive.... the right is well, PX1, msi afterburner, HWinfo, razor synapse, IDM, and windows defender.... as i ran this test about ten times they were all pretty consistent with each other....about to try some 4000mhz darkzA 4x8 sticks and see what i can get with those. CJR tho so the timings are horrible but still double the ram....


----------



## domdtxdissar

craxton said:


> now this is more like it....left is without anything running in the background that windows doesnt need to stay alive.... the right is well, PX1, msi afterburner, HWinfo, razor synapse, IDM, and windows defender.... as i ran this test about ten times they were all pretty consistent with each other....about to try some 4000mhz darkzA 4x8 sticks and see what i can get with those. CJR tho so the timings are horrible but still double the ram....
> View attachment 2472065


Are you sure you dont have lots of WHEA errors making your overclock unstable ?
Your bandwidth numbers should be higher @ 2000:4000.. (i have ~59k read @ 1900:3800)

When i force my infinity fabric to high i get unstable performance and lots of WHEA errors..


----------



## KedarWolf

I ran Anta Extreme but with it changed to 1500% instead of 500% so each cycle is 3 times as long.










Here the Anta Extreme .cfg I used, I let it run overnight while I sleep. 



Code:


Memory Test config file v0.02
Copyrights to the program belong to me.
Serj
testmem.tz.ru
[email protected]

[Main Section]
Config Name=Extreme1
Config Author=anta777
Cores=0
Tests=16
Time (%)=1500
Cycles=3
Language=0
Test Sequence=4,6,1,12,2,4,12,2,5,7,1,13,2,5,13,2,8,9,1,14,2,8,14,2,10,11,1,15,2,10,3

[Global Memory Setup]
Channels=2
Interleave Type=1
Single DIMM width, bits=64
Operation Block, byts=64
Testing Window Size (Mb)=1536
Lock Memory Granularity (Mb)=16
Reserved Memory for Windows (Mb)=128
Capable=0x0
Debug Level=7

[Window Position]
WindowPosX=6
WindowPosY=687

[Test0]
Enable=1
Time (%)=100
Function=RefreshStable
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=0
Test Block Size (Mb)=0

[Test1]
Enable=1
Time (%)=20
Function=MirrorMove
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=4
Test Block Size (Mb)=0

[Test2]
Enable=1
Time (%)=100
Function=MirrorMove128
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=2
Test Block Size (Mb)=0

[Test3]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=1
Pattern Param0=0x1E5F
Pattern Param1=0x45357354
Parameter=256
Test Block Size (Mb)=4

[Test4]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=0
Test Block Size (Mb)=4

[Test5]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=0
Test Block Size (Mb)=0

[Test6]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=2
Test Block Size (Mb)=4

[Test7]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=2
Test Block Size (Mb)=0

[Test8]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=2
Pattern Param0=0x1E5F
Pattern Param1=0x45357354
Parameter=0
Test Block Size (Mb)=4

[Test9]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=2
Pattern Param0=0x2305B
Pattern Param1=0x97893FB2
Parameter=2
Test Block Size (Mb)=4

[Test10]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=2
Pattern Param0=0x98FB
Pattern Param1=0x552FE552
Parameter=0
Test Block Size (Mb)=0

[Test11]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=2
Pattern Param0=0xC51C
Pattern Param1=0xC5052FE6
Parameter=2
Test Block Size (Mb)=0

[Test12]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=256
Test Block Size (Mb)=4

[Test13]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=256
Test Block Size (Mb)=0

[Test14]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=2
Pattern Param0=0xB79D9
Pattern Param1=0x253B69D4
Parameter=256
Test Block Size (Mb)=4

[Test15]
Enable=1
Time (%)=100
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=2
Pattern Param0=0x2305A
Pattern Param1=0x1789AB54
Parameter=256
Test Block Size (Mb)=0


----------



## mus1mus

@KedarWolf 

Have you checked if your Godlike has the updated BIOS? 

I saw one on the Ace and 4000/2000/1:1:1 is working.


----------



## KedarWolf

mus1mus said:


> @KedarWolf
> 
> Have you checked if your Godlike has the updated BIOS?
> 
> I saw one on the Ace and 4000/2000/1:1:1 is working.


Yeah, there is, but I STILL haven't gotten my 5950x yet and 1.93 still best for me.


----------



## craxton

domdtxdissar said:


> Are you sure you dont have lots of WHEA errors making your overclock unstable ?
> Your bandwidth numbers should be higher @ 2000:4000.. (i have ~59k read @ 1900:3800)
> 
> When i force my infinity fabric to high i get unstable performance and lots of WHEA errors..


Haven't had any errors at all. Nota one. Other than when I force close razor software or task kill certain things. My timings can be adjusted slightly which veii said to do. But given I'm working 12hr nights 7 days a week I've not been on much to do any thing other than chrome browsing. All tests pass, crunch, prime, hci, TM5 anta777, and occt none failed or flagged any errors. (Besides when manually overclocking the cpu with the voltage I have set currently which is low granted I'll never push the chip that hard it runs just fine. Prime being the only crash during that time with manual voltage at 4.7/75ghz.) Msi just released this bios as well which there last my aida scores were way worse. Not much difference in bandwidth and latency but l3 cache was 350... Now it's almost doubled that. I've also only had this board for about a week now, still dialing in certain things. Currently tweaking 4 sticks of cjr running 2000fclk. Scores are worse but the timings are xmp 2t command.


----------



## KedarWolf

mus1mus said:


> @KedarWolf
> 
> Have you checked if your Godlike has the updated BIOS?
> 
> I saw one on the Ace and 4000/2000/1:1:1 is working.


Check your AIDA64 bandwidth with other memory speeds. On other BIOS's some peeps that hit 4000 had worse bandwidth than at 3800 etc.


----------



## mus1mus

No perf penalty. Just switching OS atm as W8.1 seems to be throwing fits without doing anything. 

Will report back later. 4000 1:1:1 is max though.


----------



## VPII

Okay so yesterday I saw that MSI finally added a new bios 1.1.9.0 for the MSI e X570 Ace so I downloaded it and updated my bios. However, I found that my previous 3800mem with 1900 fibre clock is no longer stable. I'll fall back onto the previous bios to test again for stablility but it would mean that I am losing the undervolt curve in the bios which is a pitty as my all core for the 5950X was 4.475 to 4.5ghz using -20 curve setting.


----------



## dr.Rafi

mus1mus said:


> No perf penalty. Just switching OS atm as W8.1 seems to be throwing fits without doing anything.
> 
> Will report back later. 4000 1:1:1 is max though.


I did 4066/2033 stable on 5950x Asus motherboard


----------



## mus1mus

VPII said:


> Okay so yesterday I saw that MSI finally added a new bios 1.1.9.0 for the MSI e X570 Ace so I downloaded it and updated my bios. However, I found that my previous 3800mem with 1900 fibre clock is no longer stable. I'll fall back onto the previous bios to test again for stablility but it would mean that I am losing the undervolt curve in the bios which is a pitty as my all core for the 5950X was 4.475 to 4.5ghz using -20 curve setting.


Yes.
Terrible BIOS this 1D5.

Throws all errors on my previous config.



dr.Rafi said:


> I did 4066/2033 stable on 5950x Asus motherboard


Well, there are peeps that run 2200/4400 stable on Asus.

What's your point?


----------



## Ridianod

Guys, interestingly, I do not get an error from tm5, but if I close the program after a certain period of time, there is a big lag in the computer. Youtube video pictures, websites are not loaded. Restarting the computer resolves the problem. I wonder if this is a problem with unloading the ram or something? I don't remember encountering such a problem before the last tightening values I reached. Do you think this is normal? my timings;


----------



## YoungChris

Do any of you know the highest documented functional FCLK so far with Zen 3? Such as no AIDA/other bench performance degradation.


----------



## Boldish

I added my results to the Google Sheet. I'm the first entry with sub 10 ns L3 cache. Not sure if that really matters though.

I'm wondering if I can tighten tRAS and tRFC a bit more. Not sure how much that will affect latency though.

I can post 4000/2000 but I get WHEA errors. I'm thinking it's a BIOS issue so I'll try to get that stable in a newer bios version.


----------



## phoenixibs

Hi guys,

I have just finished building my PC.

CPU: 5800x
RAM: Corsair 2x8GB 3600Mhz c18
Motherboard: ASUS X570-F (BIOS ver 3201)
Cooler: corsair h115i

latest chipset installed from AMD website.

I have enabled D.O.C.P.

I have been spending a few days testing and I just cant figure out one thing which I just cant figure out.

I have ran OCCT LinPack for 1 hour only and it has no errors.(D.O.C.P enabled)
I have ran Asus RealBench which also came back with no errors.(D.O.C.P enabled)
I have run Memtest with 4 passes and no errors have come up. (D.O.C.P enabled)
I have run small FFT for 12 hours with no errors (D.O.C.P enabled)

When I run Prime95 ver 30.3B6 in small FFT for 12 hours I had no errors with DOCP enabled. I then ran a blend Test which came back with rounding error. This happens after around 2 hours.
I set everything to default in bios including memory and ran prime95 again and I had same issue with blend test giving out error after around 2 hours.


I have now enabled D.O.C.P and have run the prime95 large FFT this failed after 4 hours and one worker stopped with rounding error.
I have now tested small FFT again with D.O.C.P enabled and it has been running for over 12 hours and has had no errors. 



I have not had any BSOD or WHEA errors.









this is my current details with large fft running. Default in BIOS with exception of DOCP being enabled.

my temps are fine. it does fluctuate and sometime goes upto 79 degrees for a while and then drops back down again. I can see the voltage change and clock speed change when it does increase in temp.

I have ordered another set of RAM just to test with which is a G SKILL F4-3600C16D-16GTZR.

I just can't figure out why the blend test specifically fails and small FFT and large FFT doesn't.

Has anyone had this issue?


----------



## mirzet1976

Boldish said:


> View attachment 2472262
> 
> 
> I added my results to the Google Sheet. I'm the first entry with sub 10 ns L3 cache. Not sure if that really matters though.
> 
> I'm wondering if I can tighten tRAS and tRFC a bit more. Not sure how much that will affect latency though.
> 
> I can post 4000/2000 but I get WHEA errors. I'm thinking it's a BIOS issue so I'll try to get that stable in a newer bios version.


Enable PBO FMax Enhancer in bios and your L3 cache will go up alot.


----------



## Boldish

mirzet1976 said:


> Enable PBO FMax Enhancer in bios and your L3 cache will go up alot.


I purposely have that disabled. I noticed it caused performance degradation in benchmarks. On paper it caused my clocks to go up, but the effective clocks were lower than with it disabled.


----------



## mirzet1976

Boldish said:


> I purposely have that disabled. I noticed it caused performance degradation in benchmarks. On paper it caused my clocks to go up, but the effective clocks were lower than with it disabled.


I know that and to have both L3 Cache high and performance CPU needs more voltage.


----------



## domdtxdissar

Boldish said:


> View attachment 2472262
> 
> 
> I added my results to the Google Sheet. I'm the first entry with sub 10 ns L3 cache. Not sure if that really matters though.
> 
> I'm wondering if I can tighten tRAS and tRFC a bit more. Not sure how much that will affect latency though.
> 
> I can post 4000/2000 but I get WHEA errors. I'm thinking it's a BIOS issue so I'll try to get that stable in a newer bios version.


I also have sub 10ms L3 but your bandwith numbers are low no ?

PBO FMax Enhancer= disabled as its bugged for ryzen 5000 and lower the effective clocks


----------



## VPII

Okay I've tried various means by which to get 3800 with 1900 fibre clock to work with the latest bios for my MSI Meg X570 Ace mobo. The bios is 1.1.9.0 which works great for the cpu clocks with PBO. I finally figured out that due to high ambient temps here as in 30C or there about the memory was running a little too hot. This morning however with some rain I finally got it to work without GearDown and it appears to be stable. Unfortunately the latency is higher than it should be, or so it seems. Now my setup it as follow:

AMD Ryzen 9 5950X
4 x 8GB G-Skill DDR4 3200CL14, as such it is two sets combined.
MSI Meg X570 Ace mobo










ANy idea what I can do to get my latency a little better?


----------



## KevyMatts

Hi, i updated my bios (MSI B450 Pro Carbon) till latest one released with support to new cpus, now my RAM overclock memory isn't stable should I revert back to previous one?


----------



## newls1

VPII said:


> Okay I've tried various means by which to get 3800 with 1900 fibre clock to work with the latest bios for my MSI Meg X570 Ace mobo. The bios is 1.1.9.0 which works great for the cpu clocks with PBO. I finally figured out that due to high ambient temps here as in 30C or there about the memory was running a little too hot. This morning however with some rain I finally got it to work without GearDown and it appears to be stable. Unfortunately the latency is higher than it should be, or so it seems. Now my setup it as follow:
> 
> AMD Ryzen 9 5950X
> 4 x 8GB G-Skill DDR4 3200CL14, as such it is two sets combined.
> MSI Meg X570 Ace mobo
> 
> View attachment 2472317
> 
> 
> ANy idea what I can do to get my latency a little better?


enable fmax in bios... your L3 cache speeds are tanked


----------



## Alyjen

newls1 said:


> enable fmax in bios... your L3 cache speeds are tanked


ok but is this like a real world improvement (something you'll see anywhere in games or work) or test only? I ask because I read that also using all core OC rather than PBO will change this result


----------



## domdtxdissar

newls1 said:


> enable fmax in bios... your L3 cache speeds are tanked


How many times does this need to be said ?

the stilt fmax is bugged with ryzen 5000 series, dont use it.
It only gives you fake high* L3 numbers in Aida but clock stretches everything.. your effective clocks will be very low and your cpu will underperform in all benchmarks.
* = ~same as static oc

fmax should only be used with ryzen 3000 series.

Please stop spreading misinformation / bad advice.


----------



## newls1

domdtxdissar said:


> How many times does this need to be said ?
> 
> the stilt fmax is bugged with ryzen 5000 series, dont use it.
> It only gives you fake high* L3 numbers in Aida but clock stretches everything.. your effective clocks will be very low and your cpu will underperform in all benchmarks.
> * = ~same as static oc
> 
> fmax should only be used with ryzen 3000 series.
> 
> Please stop spreading misinformation / bad advice.


didnt know this...


----------



## mus1mus

@VPII 

Are you checking for WHEA errors? 1D5 is giving me all errors even when idling on the desktop.


----------



## KedarWolf

mus1mus said:


> @VPII
> 
> Are you checking for WHEA errors? 1D5 is giving me all errors even when idling on the desktop.


On 3000 CPU's the A.42 MSI Agesa 1.0.0.5 BIOS is rock solid. I've had HWInfo open an hour, browsing, watching Twitch, no WHEA errors at all, and this with super tight memory settings at 3800 below.

STILL waiting on my preorder 5950x I ordered Nov. 5th on launch day.


----------



## blu3dragon

B550-F, 5800x (PBO+200+curve), 2x16Gb Gskill 3200cl14 at 4000cl16 (1.48v) BIOS 1216 HCI ~1000%

Recently upgraded from a 4790k and learning all about PB2, PBO and FCLK... taken about a week to get here. I'm yet to see a single WHEA error, but I've also not used the system for long like this. Ran p95, y-cruncher and linpack to test stability. y-cruncher N64 gives errors pretty quickly with lower CCD and IOD. As it is, I get an occasional failed post, but once it posts, it seems stable. Not sure if that is FLCK or memory related. Let me know if anyone has any thoughts on how to fix that, or what to tune beyond this.

p95 single thread no-avx had me tuning curve offset for many hours and linpack 1.1.3 threw me for a bit as it errors straight away, but 1.1.5 has fix for amd cpus and I was able to do 20 passes with that.


----------



## Gaav

Asus b550-a strix/ 5600x / patriot Viper 4400cl19 . Bios 1601 agesa(1.9.0.0). Stable 2000fclk cl17cr2 55ns for past 2 days. I can also run 2100fclk windows stable but crashes on any avx benchmark. Highest bootable fclk is 2166mhz. Highest stable fclk i can do is 2066mhz 1.45v mem soc vdds 1.15v soc phase extrem and +110% power. Dont have time but i think 2100mhz fclk is doable with tweaks. But my 5600x is trash ocer... 4700mhz 1.4v ... 4725 1.4v instant crash i run 4650mhz 1.375v at 4000cl17. So i guess platinum imc silver core clock... 8hours overwatch. Two 4hour bf1 sessions. 2h cyberpunk 2h horizon. 3-4whea errors per day.


----------



## KedarWolf

mus1mus said:


> @VPII
> 
> Are you checking for WHEA errors? 1D5 is giving me all errors even when idling on the desktop.


Linpack Extreme 1.1.3 is a really great program for checking if your overclock is stable. If all your residuals are exactly the same, it's good.

This is me with HWInfo open, 5 cycles, no WHEA errors, matching residuals.








.


----------



## mus1mus

@KedarWolf 

I have a theory on what's happening. I just tested 1D5 bios again and it is stable from the previous configs, If IO Voltages are tuned higher than previous BIOS. We are looking at 0.85 vs 0.95

Im gonna test if that affects the issue on higher than 3800 RAM. Trouble is it seems that this bios is easily corruptible.


----------



## VPII

mus1mus said:


> @VPII
> 
> Are you checking for WHEA errors? 1D5 is giving me all errors even when idling on the desktop.


Yes I am and all good.


----------



## VPII

newls1 said:


> enable fmax in bios... your L3 cache speeds are tanked


Not sure if it is maybe named differently in the MSI bios but I cannot find it. I have adjusted the voltage curve in the bios under PBO advance but that is about it.


----------



## Toddimus

mus1mus said:


> @KedarWolf
> 
> I have a theory on what's happening. I just tested 1D5 bios again and it is stable from the previous configs, If IO Voltages are tuned higher than previous BIOS. We are looking at 0.85 vs 0.95
> 
> Im gonna test if that affects the issue on higher than 3800 RAM. Trouble is it seems that this bios is easily corruptible.


I totally agree. VSoC and VDDG IOD both need to be higher with A85. Especially IOD. I went from something like 0.950 or 1.000v to needing 1.150v on VDDG IOD to avoid WHEA errors and crashes. Actually seems pretty stable now though. 

VDDP is still good at 0.870v as is VDDG CCD at 0.950v, as I used on A82. 

This is on a x570 Unify with 5900x, by the way. Realized I wasn’t posting in the Unify thread. 

Sent from my iPhone using Tapatalk


----------



## mus1mus

Toddimus said:


> I totally agree. VSoC and VDDG IOD both need to be higher with A85. Especially IOD. I went from something like 0.950 or 1.000v to needing 1.150v on VDDG IOD to avoid WHEA errors and crashes. Actually seems pretty stable now though.
> 
> VDDP is still good at 0.870v as is VDDG CCD at 0.950v, as I used on A82.
> 
> Sent from my iPhone using Tapatalk


Looks like it's confirmed for MSI latest bios.

4133 boots.. oops..

Testing 4000 for WHEA and wow! From .95 to needing over 1.12 on IOD.

Not worth it. It just duck swinging at this point for me..


----------



## Toddimus

mus1mus said:


> Looks like it's confirmed for MSI latest bios.
> 
> 4133 boots.. oops..
> 
> Testing 4000 for WHEA and wow! From .95 to needing over 1.12 on IOD.
> 
> Not worth it. It just duck swinging at this point for me..


Yeah. I tried a run for 1933 and 2000 fclk with no real success. I was able to boot at 1933 1:1:1 but got WHEA 19 errors. Higher voltages reduced errors but it was just too much voltage for me to blindly be pushing on my poor chip. 


Sent from my iPhone using Tapatalk


----------



## mus1mus

Very true.
No amount of Voltages allow removal of the WHEA errors for now. 

MSI is just doing a terrible job with BIOS support at this point. 




On a side note, brace for more expensive GPU pricing until crypto craze dies.


----------



## VPII

mus1mus said:


> Very true.
> No amount of Voltages allow removal of the WHEA errors for now.
> 
> MSI is just doing a terrible job with BIOS support at this point.
> 
> 
> 
> 
> On a side note, brace for more expensive GPU pricing until crypto craze dies.


I thought so at first with the latest bios for my MSI Mg X570 Ace until it actually worked pretty well. even better than before yesterday when I tested it. It was a much cooler day which helped but now I am finally set on 3800 with 1900 FCLK an 1T command rate with Geard Down disabled..... so I cannot complain.


----------



## mus1mus

1900 is no problem but it needs more VDDP and IOD voltages than 1D2. 

I am refreshing my BIOS and try again. I will try 1D2 first. 

 Maybe the voltages are keeping it from doing more than 1900/3800.


----------



## Gaav

AGESA 1.9.0.0 Stable for past 3-4days 1 WHEA error so far during 1h AIDA64 full stress test.
Im able to boot with 4100FCLK in to widows but crashes after 2-3min. 

4066FCLK crashes after 10min managed to do aida64. 
4033FCLK gives 100+ errors in seconds while doing any test did not crash. 
Maybe i should try to increase VSOC to 1,175 and VDDP to like 1.0v ?


----------



## Comalive

Gaav said:


> AGESA 1.9.0.0 Stable for past 3-4days 1 WHEA error so far during 1h AIDA64 full stress test.
> Im able to boot with 4100FCLK in to widows but crashes after 2-3min.
> 
> 4066FCLK crashes after 10min managed to do aida64.
> 4033FCLK gives 100+ errors in seconds while doing any test did not crash.
> Maybe i should try to increase VSOC to 1,175 and VDDP to like 1.0v ?
> View attachment 2472531
> 
> View attachment 2472532


Rerun your benchmark, your read speed result is buggy.


----------



## mus1mus

True..


----------



## newls1

anyone running this 2x16GB G.skill CL14 kit here? Trying to stabilze 3800/1900 settings and looking for assistance. This is the ram im using
G.SKILL Ripjaws V Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 3600 (PC4 28800) Intel XMP 2.0 Desktop Memory Model F4-3600C14D-32GVK - Newegg.com


----------



## mikalcarbine

Hey all, I'm trying to tighten up my timings and could use some advice. I'm running 32GB of Micron E die with a 5600X on a MSI B550M Mag Mortar with AGESA 1.1.9.0. I can boot up to 4133 MHz 1:1 but it inconsistently posts and the BIOS screen gets artifacts so I dialed it back down to 4000 MHz. I'd like to get a baseline here for 24/7 and then see if I can push things up to or past 4200 MHz. I had everything tightened up prior and started running into errors so I put everything but the primary timings back to auto. 

A few notes:
I tried disabling GDM at this frequency but had zero luck. Changing ClkDrvStr to 120 allows me to post but it's very unstable. I tried increasing VDIMM to 1.5v as well
I can't seem to run tRP of 16 no matter what I try, any tips?
Micron E die seems to be walled with tRCDRD, I can boot at 20 but it produces many errors
Lowering my tWR to 16 seems to produce errors, I usually see this value being run much lower though

















Any tips would be appreciated


----------



## blu3dragon

blu3dragon said:


> B550-F, 5800x (PBO+200+curve), 2x16Gb Gskill 3200cl14 at 4000cl16 (1.48v) BIOS 1216 HCI ~1000%
> 
> Recently upgraded from a 4790k and learning all about PB2, PBO and FCLK... taken about a week to get here. I'm yet to see a single WHEA error, but I've also not used the system for long like this. Ran p95, y-cruncher and linpack to test stability. y-cruncher N64 gives errors pretty quickly with lower CCD and IOD. As it is, I get an occasional failed post, but once it posts, it seems stable. Not sure if that is FLCK or memory related. Let me know if anyone has any thoughts on how to fix that, or what to tune beyond this.
> 
> p95 single thread no-avx had me tuning curve offset for many hours and linpack 1.1.3 threw me for a bit as it errors straight away, but 1.1.5 has fix for amd cpus and I was able to do 20 passes with that.
> View attachment 2472434
> 
> 
> View attachment 2472433


More testing with y-crucher showed that this wasn't fully stable. The two NTT tests (N32 and N64) will either error or cause a reboot if run in a loop for 30-60 minutes... Tried increasing VSOC and IOD to 1.15 and 1.10 respectively. That helped but did not fix it completely. Going back to 1900 FCLK for now as I don't want to run VSOC much higher than that and still have the occasional failure to post with 2000 FCLK as well. I did figure out that I could lower CCD though.


----------



## blu3dragon

Gaav said:


> AGESA 1.9.0.0 Stable for past 3-4days 1 WHEA error so far during 1h AIDA64 full stress test.
> Im able to boot with 4100FCLK in to widows but crashes after 2-3min.
> 
> 4066FCLK crashes after 10min managed to do aida64.
> 4033FCLK gives 100+ errors in seconds while doing any test did not crash.
> Maybe i should try to increase VSOC to 1,175 and VDDP to like 1.0v ?
> View attachment 2472531
> 
> View attachment 2472532


Try increasing VDDG IOD to 1.075 or 1.1V.
At 1.1V you will also need to increase VSOC to 1.15 (it should be at least 50mV higher than IOD).
You can probably lower VDDG, but do that separately.


----------



## KedarWolf

blu3dragon said:


> More testing with y-crucher showed that this wasn't fully stable. The two NTT tests (N32 and N64) will either error or cause a reboot if run in a loop for 30-60 minutes... Tried increasing VSOC and IOD to 1.15 and 1.05 respectively. That helped but did not fix it completely. Going back to 1900 FCLK for now as I don't want to run VSOC much higher than that and still have the occasional failure to post with 2000 FCLK as well. I did figure out that I could lower CCD though.


*Try this y-cruncher .cfg save it as memtest.cfg, right-click on your y-cruncher, make a shortcut in the same folder as your y-cruncher exe.

Run y-cruncher from the shortcut as Admin.

Right-click on the shortcut, go to Properties, put this in your Target, with the path as the path to your y-cruncher .exe.*



Code:


"D:\y-cruncher v0.7.8.9507\y-cruncher v0.7.8.9507\y-cruncher.exe" pause:1 config memtest.cfg

*The .cfg.*



Code:


//  y-cruncher Configuration File
//  Version: 0.7.8 Build 9507
//
//  Load this from y-cruncher or run directly:
//      y-cruncher config filename.cfg
//
//  If you're copying Windows file paths into here, be sure to replace
//  all backslashes "\" with forward slashes "/". Backslash is an
//  escape character.
//

{
    Action : "StressTest"
    StressTest : {
        AllocateLocally : "true"
        LogicalCores : [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31]
        TotalMemory : 30064771072
        SecondsPerTest : 200
        SecondsTotal : 3600
        StopOnError : "false"
        Tests : [
            "BKT"
            "FFT"
            "N32"
            "N64"
            "VST"
            "C17"
        ]
    }
}

*The TotalMemory is for 32GB, make it TotalMemory : 13958643712 for 16GB.*

It avoids the SMALL FFT tests etc. that cause insane temps and instant reboots on 3000 and 5000 series CPUs.

If you're on a 5900x or other CPU, remove the cores count like for a 5900x.

*Remember the '0' is the first core, so like 24 cores/threads is 0-23.*



Code:


LogicalCores : [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23]


----------



## blu3dragon

KedarWolf said:


> *Try this y-cruncher .cfg save it as memtest.cfg, right-click on your y-cruncher, make a shortcut in the same folder as your y-cruncher exe.
> 
> Run y-cruncher from the shortcut as Admin.
> 
> Right-click on the shortcut, go to Properties, put this in your Target, with the path as the path to your y-cruncher .exe.*
> 
> 
> 
> Code:
> 
> 
> "D:\y-cruncher v0.7.8.9507\y-cruncher v0.7.8.9507\y-cruncher.exe" pause:1 config memtest.cfg
> 
> *The .cfg.*
> 
> 
> 
> Code:
> 
> 
> //  y-cruncher Configuration File
> //  Version: 0.7.8 Build 9507
> //
> //  Load this from y-cruncher or run directly:
> //      y-cruncher config filename.cfg
> //
> //  If you're copying Windows file paths into here, be sure to replace
> //  all backslashes "\" with forward slashes "/". Backslash is an
> //  escape character.
> //
> 
> {
> Action : "StressTest"
> StressTest : {
> AllocateLocally : "true"
> LogicalCores : [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31]
> TotalMemory : 30064771072
> SecondsPerTest : 200
> SecondsTotal : 3600
> StopOnError : "false"
> Tests : [
> "BKT"
> "FFT"
> "N32"
> "N64"
> "VST"
> "C17"
> ]
> }
> }
> 
> *The TotalMemory is for 32GB, make it TotalMemory : 13958643712 for 16GB.*
> 
> It avoids the SMALL FFT tests etc. that cause insane temps and instant reboots on 3000 and 5000 series CPUs.
> 
> If you're on a 5900x or other CPU, remove the cores count like for a 5900x.
> 
> *Remember the '0' is the first core, so like 24 cores/threads is 0-23.*
> 
> 
> 
> Code:
> 
> 
> LogicalCores : [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23]


Thanks. I just finished a 75min loop of nothing but N32 and N64 at 1900 FCLK. N64 in particular seems to fail if FCLK is not stable.


----------



## Alyjen

When I was still playing with my settings y-cruncher was pretty good to force whea warnings. Prime/OCCT were stable, TM5 all well (no surprise) but 1 pass of y-cruncher was enough to have few of them recorded. But I never had any issues with instant reboots, test closing, PC freezing or other errors, all tests finished without any issues. Yes, small fft tests caused temperatures to reach 90 and it just stayed there for the test duration.


----------



## newls1

newls1 said:


> anyone running this 2x16GB G.skill CL14 kit here? Trying to stabilze 3800/1900 settings and looking for assistance. This is the ram im using
> G.SKILL Ripjaws V Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 3600 (PC4 28800) Intel XMP 2.0 Desktop Memory Model F4-3600C14D-32GVK - Newegg.com


anyone, please!


----------



## Comalive

I just updated to AGESA 1.1.9.0. (B550 Gaming Edge Wifi). I was running at 1900 fclk before, I could boot at 2000 (and maybe more) before. 1866 works perfectly now, 1900, however, suddenly creates problems. The boot process fails at VGA (Debug LED) for some reason, it's really strange. Does anyone know what might be going on there besides a buggy BIOS?


----------



## DeletedMember558271

So I finally got around to flashing 7C91vA53 (ComboAM4PIV2 1.1.9.0) to my B550 Tomahawk now that I'm done Cyberpunk and still no luck posting 1900 FCLK.
I don't know what else I can try but I've tried throwing 1.150 VSOC, 1.000 VDDP, 1.100 IOD, 1.100 CCD at it, even thought it's 100% stable at 1867 FCLK with all of those -.050v, I just tried bumping them all +.050v.

I seem to be the only one on the Zen Overclocking Spreadsheet with a B550 Tomahawk as well, so don't really know if anyone is doing better, I'm also 4x8GB.
Really disappointing this new BIOS doesn't seem to improve anything regarding this.








If this is stable what am I supposed to do to get 1900+ FCLK?
It doesn't matter if all BIOS settings are default, DRAM timings loose and frequency low, with auto or manual voltages that should be more than enough.
1867 rock solid, 1900 impossible to even turn on.
Also I could probably lower vDIMM quite a bit if not all voltages with current settings, just haven't got around to bothering.
I feel like I'm at the mercy of MSI and they don't seem to give a **** maybe my B550 Tomahawk isn't a board that's important enough...

Edit:


Comalive said:


> I just updated to AGESA 1.1.9.0. (B550 Gaming Edge Wifi). I was running at 1900 fclk before, I could boot at 2000 (and maybe more) before. 1866 works perfectly now, 1900, however, suddenly creates problems. The boot process fails at VGA (Debug LED) for some reason, it's really strange. Does anyone know what might be going on there besides a buggy BIOS?


Good to know I'm not the only one and it's not just my board I guess, pretty specific to both be locked at 1867. Hopefully that means they get around to it but jesus this is taking a long time if they can actually do anything about it, I hope they don't just **** everyone over that didn't buy their most expensive boards


----------



## mus1mus

How are you setting up your OC? 

Often times, I do my OC in steps just to avoid training issues and the like. 

From a Default state (ideally, fresh BIOS install)
1. Set up Voltages - Core, SOC, IO, RAM etc. 
Reboot to BIOS
2. Set up Timings. Try 18-18-18-18-38 for giggles.
Reboot to BIOS
3. Set up Clocks. RAM and FCLK, UCLK. It is also good to start with a static CPU Clock
Hopefully you can reboot to BIOS. 

If you get this far, try tuning your Memory down. 

Might also be a good practice to save OC Profile after each step or after you boot to each step before changing anything so you can revert back if something goes wrong. 

Hopefully this gets you to 1900 FCLK.


----------



## Comalive

O.K. so just setting it to 2000 works, I guess it is just 1900 (and maybe other frequencies) which are straight up buggy. Very strange.


----------



## mus1mus

Lucky you..  mine is just at 1900 and 2000 is WHEA-plagued..

You can check for WHEA errors at 2000 and if everything's good, enjoy the boost.


----------



## DeletedMember558271

Comalive said:


> O.K. so just setting it to 2000 works, I guess it is just 1900 (and maybe other frequencies) which are straight up buggy. Very strange.


Ok I have to go to sleep before I can check for errors or stability, but I just tried 1933 FCLK without changing anything else and it booted into Windows fine.
What the ****.
So 1900 FCLK is just a black hole and **** me for thinking obviously nothing higher would work why would it right?...
Also this new MSI BIOS broke PBO... +200mhz is now the same as +0mhz, doesn't boost over 4800 anymore where it did 5000mhz+ before, found a few others mentioning such issue with recent Asus BIOS which they apparently pulled down off the site.

This will be a shame now if 1933 errors cause too high, if dropping to 1900 would have be fine, cause have to drop to 1867... or do BCLK maybe but ugh


----------



## Comalive

mus1mus said:


> Lucky you..  mine is just at 1900 and 2000 is WHEA-plagued..
> 
> You can check for WHEA errors at 2000 and if everything's good, enjoy the boost.


How important are WHEA-errors anyway? I was running 1900 fclk before and I passed y-cruncher, prime95 and AIDA64 stress test just fine, despite getting WHEA-errors. Depending on the test, stress tests give about 101 errors every 1-2 minutes.


----------



## BluePaint

I also ran 2033 fclk with whea fine for a while but I wouldn't want that on a PC where I do work/important stuff.
Also, since I dialed in my 1900 fclk and ram timings/voltages, Windows startup is super quick and smooth.


----------



## Sam64

"Depending on the test, stress tests give about 101 errors every 1-2 minutes. "

It means, that you lose performance every 1-2 minutes, because the OS is busy correcting these 101 errors.


----------



## mus1mus

WHEA can relate to hardware issues. My audio is wonky with super high WHEA error count. Corrupted my OS. And so on. What else will be affected? Can't tell.


----------



## Comalive

So I just passed 3 iterations/54 min of y-cruncher which generated ~2850 errors. So I suppose that if everything works for me, I can disregard the WHEA-errors, right? The ones I get are all CPU Bus/Interconnect Errors, which should stem from my fclk overclock.


----------



## bonet69

newls1 said:


> anyone running this 2x16GB G.skill CL14 kit here? Trying to stabilze 3800/1900 settings and looking for assistance. This is the ram im using
> G.SKILL Ripjaws V Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 3600 (PC4 28800) Intel XMP 2.0 Desktop Memory Model F4-3600C14D-32GVK - Newegg.com


I have similar kit, this are my settings:



I am able to run it with 1.49v but that might be not your case, try first with timings 14-8-15-14-28-42 at 1.5v if that gives you no error go for 14-8-14-14 and then 14-8-14-13

Regards


----------



## Alyjen

Comalive said:


> So I just passed 3 iterations/54 min of y-cruncher which generated ~2850 errors. So I suppose that if everything works for me, I can disregard the WHEA-errors, right? The ones I get are all CPU Bus/Interconnect Errors, which should stem from my fclk overclock.


I don't think it's good to keep it like this. I was getting ~few (1-5) whea 19 warnings during single y-cruncher pass and I considered this unsable. I'm pretty sure that performance you're getting is worse than any confing you can have with minimal (or 0) of these warnings. Sound issues, USB lag, microshutter in games this kind of issues is the best case scenario.


----------



## Comalive

Yeah my errors are also WHEA 19 errors... I wonder though: while HWInfo lists them as errors, the windows event log classifies them only as warnings. Also it says "corrected hardware error" so I guess it's really just a small loss of performance for fixing those errors and nothing else.


----------



## Sphex_

Comalive said:


> So I just passed 3 iterations/54 min of y-cruncher which generated ~2850 errors. So I suppose that if everything works for me, I can disregard the WHEA-errors, right? The ones I get are all CPU Bus/Interconnect Errors, which should stem from my fclk overclock.


No. You want to reduce the number of errors to 0. Things may be running, but as others have said, your performance is likely worse. On top of that, these errors will likely sneak up on you in the worst moment (updating your pc, working on a paper, the final circle in Warzone) and you won't be happy. OS Corruption is possible as well.

Trust me, I want to run 2000+ FCLK just as much as you, but I went back to 1900 for the reasons I mentioned above. It's just not worth it right now.



Comalive said:


> Yeah my errors are also WHEA 19 errors... I wonder though: while HWInfo lists them as errors, the windows event log classifies them only as warnings. Also it says "corrected hardware error" so I guess it's really just a small loss of performance for fixing those errors and nothing else.


Run an AIDA64 performance test or something. You'll see that your memory latency actually increased. I just went through all of this yesterday.


----------



## Comalive

Sphex_ said:


> No. You want to reduce the number of errors to 0. Things may be running, but as others have said, your performance is likely worse. On top of that, these errors will likely sneak up on you in the worst moment (updating your pc, working on a paper, the final circle in Warzone) and you won't be happy. OS Corruption is possible as well.
> 
> Trust me, I want to run 2000+ FCLK just as much as you, but I went back to 1900 for the reasons I mentioned above. It's just not worth it right now.
> 
> 
> Run an AIDA64 performance test or something. You'll see that your memory latency actually increased. I just went through all of this yesterday.


Yeah I am currently trying to prevent the errors, I just can't seem to figure out how to get there. Doesn't matter if I increase or decrease voltages, the errors still come 
I am pretty happy with my memory performance though and latency specifically is the best it's ever been, funnily enough.


----------



## Alyjen

I've seen better latency scores (even in my case) with FCLK 1900 memory 3800CL16. Now with FCLK 1866 memory 3733CL14 I have 53.x ns


----------



## Sphex_

Comalive said:


> Yeah I am currently trying to prevent the errors, I just can't seem to figure out how to get there. Doesn't matter if I increase or decrease voltages, the errors still come
> I am pretty happy with my memory performance though and latency specifically is the best it's ever been, funnily enough.


Yeah, I struggled with the same thing and the only thing I really found was increase VSOC helped mitigate the errors but I still got a ton when running any kind of stability test. 

You results are decent but I'm telling you the WHEA errors are hurting your performance. Look at the latency myself and others have been able to achieve at 1900 FCLK. Zen RAM Overclocking


----------



## newls1

bonet69 said:


> I have similar kit, this are my settings:
> 
> 
> 
> I am able to run it with 1.49v but that might be not your case, try first with timings 14-8-15-14-28-42 at 1.5v if that gives you no error go for 14-8-14-14 and then 14-8-14-13
> 
> Regards


i couldnt post using your trdrdscl 2 and twrwrscl 2, so i used 4 and i chose to use 14/15/15/15/35 primaries using a little less vdimm. thank you so much for your input here. im currently using memtest pro and testing to 100% coverage.. Crossing my fingers


----------



## Gadfly

mus1mus said:


> Lucky you..  mine is just at 1900 and 2000 is WHEA-plagued..
> 
> You can check for WHEA errors at 2000 and if everything's good, enjoy the boost.


Raise your 1.8v PLL to 1.95v


----------



## bonet69

newls1 said:


> i couldnt post using your trdrdscl 2 and twrwrscl 2, so i used 4 and i chose to use 14/15/15/15/35 primaries using a little less vdimm. thank you so much for your input here. im currently using memtest pro and testing to 100% coverage.. Crossing my fingers


Yup i forgot to advise SCL at 2 not always work (better at 4)  How much voltage do you need for that stable?

You can still lower tRAS and tRC:

14 - 8 (free performance) - 15 - 15 - 28 (tRAS=tCL+tWR+4) - 43 (tRC=tRAS+tRP)

Regards


----------



## YoungChris

bonet69 said:


> Yup i forgot to advise SCL at 2 not always work (better at 4)  How much voltage do you need for that stable?
> 
> You can still lower tRAS and tRC:
> 
> 14 - 8 (free performance) - 15 - 15 - 28 (tRAS=tCL+tWR+4) - 43 (tRC=tRAS+tRP)
> 
> Regards


lower tRP is also free performance


----------



## DeletedMember558271

Comalive said:


> So I just passed 3 iterations/54 min of y-cruncher which generated ~2850 errors. So I suppose that if everything works for me, I can disregard the WHEA-errors, right? The ones I get are all CPU Bus/Interconnect Errors, which should stem from my fclk overclock.


Yea exact same situation here at 1933 FCLK, and since 1900 FCLK doesn't work for us doesn't even post we have to go 1867 FCLK.
I'm reverting to old beta BIOS 7C91vA51 anyway since PBO +200mhz actually worked, nothing else seems improved.
Maybe someday MSI will release a BIOS that makes something better, or at least not worse. Would be nice since at 3733C14 runs too hot and errors if I'm stressing 3080 at the same time, even with a fan on the RAM.

Edit: regarding PBO I'm dumb maybe but I guess they changed the behavior? I can get higher clocks still but only if I enable Curve Optimizer now and enter some pretty extreme negative values, wasn't like this last BIOS


----------



## blu3dragon

Alyjen said:


> When I was still playing with my settings y-cruncher was pretty good to force whea warnings. Prime/OCCT were stable, TM5 all well (no surprise) but 1 pass of y-cruncher was enough to have few of them recorded. But I never had any issues with instant reboots, test closing, PC freezing or other errors, all tests finished without any issues. Yes, small fft tests caused temperatures to reach 90 and it just stayed there for the test duration.


I kind of have the opposite experience. I'm yet to see a single whea error, but y-cruncher (N64 in particular) will either error out, freeze or cause an instant reboot depending on how it feels and how far off a stable FCLK I am. I wonder if hwinfo is not reporting those errors for me, or if there is something else going on with y-cruncher 🤷


----------



## blu3dragon

Grr. Feels like I'm chasing my tail here. >12hrs of memtest passed. 2.5hrs of y-cruncher looping n32 and n64. Then it goes and fails in n64 on the first loop of all tests?


----------



## DeletedMember558271

So does anyone (or @Veii) know what could be going on with the BIOS that stops me and @Comalive and probably lots of other from booting at 1900FCLK specifically, but we can boot 1933, 1966, 2000, etc but with WHEA errors? Is there anything we can do to get it working when without changing any other settings we can go from 1867 to 1933+, something very strange about 1900 specifically.
Basically every other 4x8GB on the Zen Overclocking Spreadsheet has 1900/3800, it bothers me I can't get it working when it could be stable but 1933+ idk if I can solve WHEA errors.
I just don't understand how 1933 posts but only lowering that to 1900 changing nothing else it doesn't, how? Why? BIOS doing something very stupid


----------



## blu3dragon

Dreamic said:


> So does anyone (or @Veii) know what could be going on with the BIOS that stops me and @Comalive and probably lots of other from booting at 1900FCLK specifically, but we can boot 1933, 1966, 2000, etc but with WHEA errors? Is there anything we can do to get it working when without changing any other settings we can go from 1867 to 1933+, something very strange about 1900 specifically.
> Basically every other 4x8GB on the Zen Overclocking Spreadsheet has 1900/3800, it bothers me I can't get it working when it could be stable but 1933+ idk if I can solve WHEA errors.
> I just don't understand how 1933 posts but only lowering that to 1900 changing nothing else it doesn't, how? Why? BIOS doing something very stupid


It sounds like a bug... possibly you just need to wait and see if it gets resolved. 33/1900 is ~1.7%, so I wouldn't sweat too much about going 1866 or 1933. Just work on getting the rest stable at one of those speeds.


----------



## blu3dragon

Same memory and FCLK as my last post, but now with my PBO offset set back to +0 and cpu curve offsets to 0, LLC 3 on the cpu (since auto LLC is unstable with 0 curve offset).










Now the question is, was this just a lucky run, or were my earlier errors and reboots due to cpu rather than FCLK instability?
I feel like this is starting to cost a little too much in electric bills to figure out


----------



## Veii

Dreamic said:


> So does anyone (or @Veii) know what could be going on with the BIOS that stops me and @Comalive and probably lots of other from booting at 1900FCLK specifically, but we can boot 1933, 1966, 2000, etc but with WHEA errors? Is there anything we can do to get it working when without changing any other settings we can go from 1867 to 1933+, something very strange about 1900 specifically.
> Basically every other 4x8GB on the Zen Overclocking Spreadsheet has 1900/3800, it bothers me I can't get it working when it could be stable but 1933+ idk if I can solve WHEA errors.
> I just don't understand how 1933 posts but only lowering that to 1900 changing nothing else it doesn't, how? Why? BIOS doing something very stupid


Try two things:
101 BLCK with 1866FCLK + 6mV positive Core offset (or 10 with more drooping LLC)
test and try then 101,5 BLCK with 10mV positive Core offset (or 15mV with stronger drooping LLC)

Either the "command" 1900 is bugged and triggers something
Or the ABL Memory training is bugged at this specific frequency and changes mode beyond 1900

Likely both are the issues soo try to set CsOdtDrvStr to 40 and see if you have any type of different behavior
procODT for 2 dimms should be 32 between both, while 34 runs
for 4 dimms 39ohm
dual rank 2 dimms 34ohm 
dual rank 4 dimms 42ohm


----------



## Sphex_

I know there are a few people who've been able to get an FCLK of 1933+ stable (no WHEA) but I, for the life of me, can't get it done. Starting to think a new BIOS / AGESA is needed. I've spent hours trying combinations of different voltages and here's what I've found so far:

Memory @ 3800 MHz / FCLK @ 1900 MHz, no WHEA errors. Anything passed that introduces them.

*VSOC* must be >1.125V otherwise the number of WHEA errors vastly increases
VDDP has no effect. I've settled on 900 mV for now
VDDG IOD has no effect. I've set it to 1060 mV for now.
*VDDG CCD* must be >980 mV otherwise the number of WHEA errors dramatically increases. 1020 and 1060 mV produced the same amount of errors, but much less than 940 and 980 mV. Perhaps 1100 mV is needed?
Disabling PBO had no effect on the amount of errors
LLC is set to Mode 2 for VSOC, which keeps it at exactly what it's set to in the BIOS, even under load. No overshoot, no vdroop.
Not really sure what else to tweak at this point. Within 6 seconds of running Y-Cruncher, I get about 20 WHEA errors, give or take. I'm thinking at this point I just have to hope and wait for another BIOS update this month. Or perhaps I got a poor quality CPU. :/ Just looking for some guidance here, if possible.

MSI MPG B550 Gaming Carbon WiFi
G.Skill F4-4266C19-16-GTZKW (4266 CL19 Kit, B-Die, Single Rank, A1 PCB)


----------



## Veii

Sphex_ said:


> I know there are a few people who've been able to get an FCLK of 1933+ stable (no WHEA) but I, for the life of me, can't get it done. Starting to think a new BIOS / AGESA is needed. I've spent hours trying combinations of different voltages and here's what I've found so far:
> 
> Memory @ 3800 MHz / FCLK @ 1900 MHz, no WHEA errors. Anything passed that introduces them.
> 
> *VSOC* must be >1.125V otherwise the number of WHEA errors vastly increases
> VDDP has no effect. I've settled on 900 mV for now
> VDDG IOD has no effect. I've set it to 1060 mV for now.
> *VDDG CCD* must be >980 mV otherwise the number of WHEA errors dramatically increases. 1020 and 1060 mV produced the same amount of errors, but much less than 940 and 980 mV. Perhaps 1100 mV is needed?
> Disabling PBO had no effect on the amount of errors
> LLC is set to Mode 2 for VSOC, which keeps it at exactly what it's set to in the BIOS, even under load. No overshoot, no vdroop.
> Not really sure what else to tweak at this point. Within 6 seconds of running Y-Cruncher, I get about 20 WHEA errors, give or take. I'm thinking at this point I just have to hope and wait for another BIOS update this month. Or perhaps I got a poor quality CPU. :/ Just looking for some guidance here, if possible.
> 
> MSI MPG B550 Gaming Carbon WiFi
> G.Skill F4-4266C19-16-GTZKW (4266 CL19 Kit, B-Die, Single Rank, A1 PCB)


Same board, lowest voltage undervolting test/result 








Main difference between bioses & boards, to me was CPU VDDP
930mV default is bad
900mV crashes near 2033
880mV let's up to 2100 to run, 2133 double slows down
860mV let's allcore OC beyond 4.8 crash, neverless of the Curve optimizer or vSoC state

WHEA errors and crashes are pretty much the same, you guys just have WHEA errors. I only get hard crashes without errors
Anywho, screenshot above should be a demonstration of lowest possible voltage 
28 & 30ohm wheren't possible yet ~ some voltage is still too high, to enable it. 30Ohm performs far worse

EDIT:
Loadline 8 for vSoC
PBO uses 90-70-110 to cover SOC powerdraw into the powercap
(75-60-90 is the default for a 5600X)
User is going for a tiny build with an undervolted 2070
His memory is a very bad FlareX A1 kit ~ visible by the timings
Memory retry count 6, Memory Fastboot off,
PHY memory training enable-enable, pattern duration 10
RTT 706 instead of 005 as that filters better higher ClkDrvStr and allows for higher voltage range than 005
005 with ClkDrvStr 40-20-40-24 or 706 with 60-20-40-20

EDIT2:
About 1933+ and voltages








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




CCD 940 IOD of 1060 should be enough to cover anything till 4033
vSOC for 4033 should be near 1.1313 readable (1.1375 with LLC droop)
Remain restrictions are either broken memory training (always since patch C) or ABL locked


----------



## Veii

blu3dragon said:


> Grr. Feels like I'm chasing my tail here. >12hrs of memtest passed. 2.5hrs of y-cruncher looping n32 and n64. Then it goes and fails in n64 on the first loop of all tests?
> 
> View attachment 2472694
> 
> 
> View attachment 2472693
> 
> 
> 
> View attachment 2472692


Drop cLDO_VDDG CCD by 10mV
940 instead 950, or use VDDG IOD of 1000 instead of 980
- pick one of both
N64 same as FFT relate to CCD voltage instability or vSoC

Also to CPU VDDP
if you have access to that, and it defaults to 930mV , drop it to 880mV
They don't usually write CPU VDDP, soo you have to figure out what is CPU and what is cLDO_VDDP


----------



## FleischmannTV

Does access to CPU VDDP depend on CPU generation or mainboard / BIOS?


----------



## Sphex_

Veii said:


> Same board, lowest voltage undervolting test/result
> (picture)
> 
> 
> Spoiler
> 
> 
> 
> Main difference between bioses & boards, to me was CPU VDDP
> 930mV default is bad
> 900mV crashes near 2033
> 880mV let's up to 2100 to run, 2133 double slows down
> 860mV let's allcore OC beyond 4.8 crash, neverless of the Curve optimizer or vSoC state
> 
> WHEA errors and crashes are pretty much the same, you guys just have WHEA errors. I only get hard crashes without errors
> Anywho, screenshot above should be a demonstration of lowest possible voltage
> 28 & 30ohm wheren't possible yet ~ some voltage is still too high, to enable it. 30Ohm performs far worse
> 
> EDIT:
> Loadline 8 for vSoC
> PBO uses 90-70-110 to cover SOC powerdraw into the powercap
> (75-60-90 is the default for a 5600X)
> User is going for a tiny build with an undervolted 2070
> His memory is a very bad FlareX A1 kit ~ visible by the timings
> Memory retry count 6, Memory Fastboot off,
> PHY memory training enable-enable, pattern duration 10
> RTT 706 instead of 005 as that filters better higher ClkDrvStr and allows for higher voltage range than 005
> 005 with ClkDrvStr 40-20-40-24 or 706 with 60-20-40-20
> 
> 
> 
> EDIT2:
> About 1933+ and voltages
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> CCD 940 IOD of 1060 should be enough to cover anything till 4033
> vSOC for 4033 should be near 1.1313 readable (1.1375 with LLC droop)
> Remain restrictions are either broken memory training (always since patch C) or ABL locked


Thanks for the swift reply and tons of info! I have no problem getting 3800 MCLK / 1900 FCLK stable, but there seems to be a wall there. I've tried many different combinations and just this morning I tried a few more using the info you gave me. Lowering VDDG_CCD has a drastic negative effect on the amount of WHEA errors produced during the N32 test in Y-Cruncher. I usually let the test run for 5-6 seconds and cancel it if there's WHEA errors. Lowering VDDG_CCD below 980 mV nearly doubles the amount. I tried setting VSOC to 1.1375V with LLC on Mode 2 (no droop, no overshoot), VDDP at 900, VDDG_IOD at 1060. I tried VDDG_CCD at both 940 and 900 and it produced more errors than a higher voltage. My chip seems to behave in the direct opposite to yours, it makes no sense.

If I can run 3800 MHz with no issues, no errors, 24/7 completely stable at the following settings








Then how does setting the MCLK just one measily step up to 3866 MHz (1933 FCLK) suddenly start creating tons of errors? It just doesn't make sense. Does that extra 33 MHz really make that much of a difference? I gotta be missing something here.


----------



## Veii

Sphex_ said:


> Thanks for the swift reply and tons of info! I have no problem getting 3800 MCLK / 1900 FCLK stable, but there seems to be a wall there. I've tried many different combinations and just this morning I tried a few more using the info you gave me. Lowering VDDG_CCD has a drastic negative effect on the amount of WHEA errors produced during the N32 test in Y-Cruncher. I usually let the test run for 5-6 seconds and cancel it if there's WHEA errors. Lowering VDDG_CCD below 980 mV nearly doubles the amount. I tried setting VSOC to 1.1375V with LLC on Mode 2 (no droop, no overshoot), VDDP at 900, VDDG_IOD at 1060. I tried VDDG_CCD at both 940 and 900 and it produced more errors than a higher voltage. My chip seems to behave in the direct opposite to yours, it makes no sense.
> 
> If I can run 3800 MHz with no issues, no errors, 24/7 completely stable at the following settings
> View attachment 2472772
> 
> Then how does setting the MCLK just one measily step up to 3866 MHz (1933 FCLK) suddenly start creating tons of errors? It just doesn't make sense. Does that extra 33 MHz really make that much of a difference? I gotta be missing something here.


Can you try to replicate the exact settings
They go hand in hand
You use a too high procODT for what you try to achieve
And high procODT wont work with low voltage at all
High ClkDrvStr and GDM on is not working well together
Also high ClkDrvStr is used to run lower procODT - having both high increases the issue strongly
I'm not wondered at all that you have issues hitting low voltages

SOC loadline of 8 with more SOC seems to work out well on this board, at least in hitting the voltage you want to have
Try that and maybe swap away RTT from 005 to 706.I had a better result with high ClkDrv and these stronger RTT values - than with lower RTT values and lower ClkDrvStr

33Mhz up to programmed ABL make a big difference
At this state it's more a big thing than anything around it
But i have to say, with this setup/settings you strain your dimms a bit much
Either GDM off with 60-20-40-20 (potentially 60-20-30-20 @ 706 RTT) or 40-20-24-24 @ 005 RTT and GDM off
But GDM on should be lower, 30-20-24-24 at best


FleischmannTV said:


> Does access to CPU VDDP depend on CPU generation or mainboard / BIOS?


Purely on the mercy of the bios developers 
But we didn't have issues on Matisse with CPU VDDP @ 900. Same for Zen1+ @ 700
It's there by default, only access is not
Same for PHY either from AMD CBS-NBIO-PHY Memory Training
or directly inside DRAM options
And the same goes to BAR mode and PCIe gen settings since Patch B ~ they are there on 1.1.0.0 SMU 56.30


----------



## drotaru

are my aida64 scores abnormally low for my timings / frequency ? specially copy score , iv seen 54000 on a regular basis but i cant break 49000 no matter what i set ( the ones i can set without erros or no boot at all ) cant find enough Hynix CJR timings to compare


----------



## sisay

I have a very strange situation. 
When the cpu is in stock or pbo I can run aida cache & memory benchmark as many times as I want. When I adjust manual 4200, pc resets with a memory error. I can add some voltage on the cpu or reduce the frequency, it doesn't matter - it will always reset. Why does pbo or stock setup cpu not reset?


----------



## Sphex_

Veii said:


> Can you try to replicate the exact settings
> They go hand in hand
> You use a too high procODT for what you try to achieve
> And high procODT wont work with low voltage at all
> High ClkDrvStr and GDM on is not working well together
> Also high ClkDrvStr is used to run lower procODT - having both high increases the issue strongly
> I'm not wondered at all that you have issues hitting low voltages
> 
> SOC loadline of 8 with more SOC seems to work out well on this board, at least in hitting the voltage you want to have
> Try that and maybe swap away RTT from 005 to 706.I had a better result with high ClkDrv and these stronger RTT values - than with lower RTT values and lower ClkDrvStr
> 
> 33Mhz up to programmed ABL make a big difference
> At this state it's more a big thing than anything around it
> But i have to say, with this setup/settings you strain your dimms a bit much
> Either GDM off with 60-20-40-20 (potentially 60-20-30-20 @ 706 RTT) or 40-20-24-24 @ 005 RTT and GDM off
> But GDM on should be lower, 30-20-24-24 at best


Alright I've replicated your settings exactly.








Mode 8 on VSOC LLC causes my VSOC (which is set to 1.05V) to droop to 1.0313V, even at idle. I adjusted it to 1.0625 which results as 1.0438 with droop.

I'm a little confused. If I want to run 1T and GDM on, ProcODT should still be 32 and just use the suggested ClkDrvStr settings that you mentioned last (30-20-24-24)? Should I try hitting 1933 FCLK from here?


----------



## blu3dragon

So it looks like the last bit of y-cruncher instability was actually caused by CPU rather than FCLK for me. Setting all my curve voltages back to 0 has resolved things. I was even able to lower VSOC and VDDG IOD by a little bit.

I think I will leave FCLK alone for a bit and see if I can tune the memory timings a little more from here. Currently at 1.4V on the memory (2x16Gb 3200cl14 gskill ripjaws V).

My conclusion so far on the cpu is that it is tuned very close to the limit from AMD already. Trying to increase clocks or lower voltages is very tricky if you want to maintain 100% stability.


----------



## DeletedMember558271

Veii said:


> Try two things:
> 101 BLCK with 1866FCLK + 6mV positive Core offset (or 10 with more drooping LLC)
> test and try then 101,5 BLCK with 10mV positive Core offset (or 15mV with stronger drooping LLC)
> 
> Either the "command" 1900 is bugged and triggers something
> Or the ABL Memory training is bugged at this specific frequency and changes mode beyond 1900
> 
> Likely both are the issues soo try to set CsOdtDrvStr to 40 and see if you have any type of different behavior
> procODT for 2 dimms should be 32 between both, while 34 runs
> for 4 dimms 39ohm
> dual rank 2 dimms 34ohm
> dual rank 4 dimms 42ohm


No luck, 101 BCLK + 12.5mv(0.0125) which is lowest positive offset I can set but double your recommended 6mv, doesn't post.
40 CsOdtDrvStr and 43.6 or 40 procODT (closest to what you suggested) don't help or change anything either.
Every other 4x8GB on Zen Overclocking Spreadsheet seems to get 1900/3800 I'm literally the only person 3733, nobody else has a B550 Tomahawk though. The other two 4x8GB MSI users have X570 Unify and 1900/3800.
Wonder if MSI will ever care to fix or will ever even know about this issue I doubt many people are reporting 1900 specifically, but maybe they'll fix WHEA errors 1933+ which would also be fine if 1900 never works, shouldn't have to spend $300+ on a motherboard to get things fixed, B550 Tomahawk is still pretty top tier VRMs can handle anything


----------



## Hale59

From twatter...a couple of minutes ago


----------



## DeletedMember558271

Hale59 said:


> From twatter...a couple of minutes ago
> View attachment 2472855


Are they talking about the 1.1.9.0 BIOS I already got that doesn't post 1900 and WHEA errors 1933+?


----------



## mus1mus

Latest MSI bios for me is a bit of work but seems very good performance wise. 

Also allowed me to do SCL 3 which is good. I was only able to do SCL 4 on previous BIOS.


----------



## Hale59

@Veii 

1T


----------



## Hale59

@Veii

2T


----------



## ViTosS

Hello guys, I'm new here (from Intel), my friend has an 5800x in a MSI X570 Unify motherboard and bought that 2x8GB [email protected] RAM kit, this is his result using the DRAM Calculator for Ryzen to tweak the timings, is there anything he can do to improve the latency? And what about the WRITE bandwidth, is it normal like that?


----------



## mirzet1976

ViTosS said:


> Hello guys, I'm new here (from Intel), my friend has an 5800x in a MSI X570 Unify motherboard and bought that 2x8GB [email protected] RAM kit, this is his result using the DRAM Calculator for Ryzen to tweak the timings, is there anything he can do to improve the latency? And what about the WRITE bandwidth, is it normal like that?
> View attachment 2472973


First update Aida64 and than rerun benchmark, forR5 5600X yes but for 5800X no


----------



## Comalive

mirzet1976 said:


> First update Aida64 and than rerun benchmark, forR5 5600X yes but for 5800X no


The 5800X also only has 1 CCD so the write speed is normal.


----------



## Cavokk

Hale59 said:


> From twatter...a couple of minutes ago
> View attachment 2472855


great - can anyone enlighten me on what a passive X570 Motherboard is? - is it passive cooling, no chipset (then what makes it an X570  ) or something else?

Thanks for any insights.

C


----------



## Hale59

Cavokk said:


> great - can anyone enlighten me on what a passive X570 Motherboard is? - is it passive cooling, no chipset (then what makes it an X570  ) or something else?
> 
> Thanks for any insights.
> 
> C


No Chipset fan


----------



## Sphex_

Cavokk said:


> (then what makes it an X570  )


Extra PCI-E 4.0 lanes.


----------



## craxton

newls1 said:


> enable fmax in bios... your L3 cache speeds are tanked


what the hell is fmax? is this on MSI ??? some reason my L3 cache speed has went from 650ish to 150? havent changed anything other than hooking up usb-c nvme drive enclosure


----------



## blu3dragon

ViTosS said:


> Hello guys, I'm new here (from Intel), my friend has an 5800x in a MSI X570 Unify motherboard and bought that 2x8GB [email protected] RAM kit, this is his result using the DRAM Calculator for Ryzen to tweak the timings, is there anything he can do to improve the latency? And what about the WRITE bandwidth, is it normal like that?
> View attachment 2472973


As per the other posts, this looks normal.
Latency is higher on Ryzen compared with what you see on intel due to the chiplet design (memory controller is on a separate chip to the cpu cores).
Also write bandwidth is reported as approx half the read bandwidth on a single chiplet cpu (5600x or 5800x).
This is nothing to worry about as actual performance is still very good. You just can't compare these bandwidth and latency measurements between platforms.

One thing you could check is cpu clock. For me on a 5800x it is reported as 4850 MHz, which is the stock top boost for a 5800x.
This might be dependent on the cooler (since the cpu will clock lower from around 60C and up) or PBO settings.


----------



## blu3dragon

craxton said:


> what the hell is fmax? is this on MSI ??? some reason my L3 cache speed has went from 650ish to 150? havent changed anything other than hooking up usb-c nvme drive enclosure


It's an option available on ASUS boards. But, it makes real world performance worse if you enable it. So don't worry about it 
For some reason it increases the L3 cache speed readings in AIDA though. I don't know why that is, or if there is some other way to increase them again, but there seems to be no correlation with any real benchmark.


----------



## craxton

blu3dragon said:


> It's an option available on ASUS boards. But, it makes real world performance worse if you enable it. So don't worry about it
> For some reason it increases the L3 cache speed readings in AIDA though. I don't know why that is, or if there is some other way to increase them again, but there seems to be no correlation with any real benchmark.


as it stands it sounds about like "msi latency enhance" which doesnt really do anything ive noticed. although for some strange reason my L3 cache speeds have went from 650 ish down to 250ish no bios updates since the latest patch the other day, no new drivers, no changes to the timings...kinda wondering atm. my 4000mhz 2000fclk speeds are what i see most get at 3800 1:1 where as my 3800mhz 1:1 is what others would get at 3600.....kinda concerning the more i think about it. on the 5600x on a b550 gaming edge wifi mobo, same as the carbon pretty much...


(EDIT) im such a mfn idiot!!! all this time i had been using manual OC set hard locked to 4.75/50 ghz at 1.27v llc3. to where now im using PBO as i was worried about safe voltages even tho MSI has released some info, AMD has released some info, and i just found some rather interesting stuff about here which is pretty interesting honestly. Yet unverified in anyway as these are still new, but still based off 3000 series then again new at the same time?? anyhow i know why my L3 speeds were hitting so low and there now back to 650/700 again.... nevermind and Dram latency enhance makes a .3ns difference for latency ive noticed within the last 20 minutes? cant be sure but i was in and out the bios ALOT and killing everything i could in task manager. (NOT IN SAFE MODE)


----------



## mirzet1976

blu3dragon said:


> It's an option available on ASUS boards. But, it makes real world performance worse if you enable it. So don't worry about it
> For some reason it increases the L3 cache speed readings in AIDA though. I don't know why that is, or if there is some other way to increase them again, but there seems to be no correlation with any real benchmark.


Have you observed what happens when you enable fmax and that is that the CPU voltage is lower and therefore the performance goes down, in order to return to the previous state of performance you need to increase voltage to CPU.


----------



## aditrex

Yo guyz can someone help me out what could be wrong in my timings i get occt pass but i get random crashes to desktop when playing BFV multiplayer


----------



## blu3dragon

mirzet1976 said:


> Have you observed what happens when you enable fmax and that is that the CPU voltage is lower and therefore the performance goes down, in order to return to the previous state of performance you need to increase voltage to CPU.


Assuming you are talking about PBO Fmax Enhancer in the ASUS bios, what happens for me is that the boost clocks increase slightly and the cpu is more likely to hold a higher boost clock, but it does that by clock stretching and so actual performance in any benchmark is lower than without it. I just checked quickly and voltages look the same for a given boost clock. So basically it clocks higher and holds a higher voltage and makes me think for example that I'm at an all core clock speed of 4.6Hz, but the way it is hitting 4.6Ghz is by clock stretching so that the effective clocks are around 4.18GHz.

OR I can disable it and running the same stress test be at an all core boost of 4.4Ghz with effective clock also at 4.4Ghz.

FMAX enhancement on:


















FMAX enhancement off:


----------



## blu3dragon

aditrex said:


> Yo guyz can someone help me out what could be wrong in my timings i get occt pass but i get random crashes to desktop when playing BFV multiplayer
> View attachment 2473042


You could try loosening your timings a little ;-)

First thing I would confirm is whether it is memory or something else though. Are you able to pass a memory stress test?
Are you getting any WHEA errors reported in HW info?


----------



## PJVol

blu3dragon said:


> For some reason it increases the L3 cache speed readings in AIDA though


Don't know guys how it works on your cpu's, but I've recently found, that L3 bandwidth aida reports, depends on what edc value I set in pbo, so basically, I can make it report any value from ~ 200 to ~600.


----------



## blu3dragon

Well now I'm seeing WHEA errors for the first time. The only difference I am aware of is that I updated to the latest version of windows. Did that add support for reporting these errors?


----------



## Comalive

blu3dragon said:


> Well now I'm seeing WHEA errors for the first time. The only difference I am aware of is that I updated to the latest version of windows. Did that add support for reporting these errors?


Was added with 2004 afaik. I was also quiet surprised to see them after updating from 1909.


----------



## craxton

hey @Veii does this trigger you in anyway?? lol i know fix my tfaw, but as it stand currently this has pass ALL TESTS fft, y-crucher, HCI overnight, TM5 etc. (with the cpu clock speed set to auto limiting pbo values of course) simply locked the cpu speed for the aida bench. anyhow, finally got some improvements where it counted....


i went back to like page 167 and started reading from there where all the voltage issues and talking's were and decided to try lowering my voltage, and well was able to lower voltages by quite the margin. still unsure what JEDEC RC 2.0 PCB actually is, but i have wrote teamgroup and asked. simply waiting for a reply (considering this is all stable at 1.4volts ??????? anyhow no errors no crashes no stutters no fallouts in chrome etc.....
(edit adding pic)
added my error report, (keep in mind the only errors im getting is due to trying to hoot up my SSK nvme enclosure on my case to which something is wrong with the ?enclosure, cable, port, header? unsure whats the actual issue. but it would crash windows explorer nearly everytime and lag out the desktop. both usb-c ports (front and rear do the same thing.) the drive works fine on type a ports, and all my other devices work fine on both usb-c ports, i have a usb-c 5gbs cable cominginstead of trying thunderbolt cables, and regular usb-c cables to where one gives to much and overloads the drive (or i think thats whats going on) and the other simply hits 40mbs instead of 1000....

will also note that im on latest windows build 19042.685 version 20H2 uptodate, latest bios released for my board, latest driver from MSI side as i believe 2.10.26.336 is newer than 2.10.13.408 (can someone let me know if this is the case? amd hasnt released a new update to where 336 is the current version from MSI and i do use DC which kept wanting to update the driver so i allowed it. (did nothing to help usb-c issues dont believe its a board problem)
anyhow, no errors other than the ones i created with the usb-c issues and the ones i made due to task killing razor software, and other software that auto start when my pc boots. will clear and use for the next few days and post error report again to show all is well under the hood of this (timing config to which doesnt look able to be stable)


----------



## Comalive

craxton said:


> hey @Veii does this trigger you in anyway?? lol i know fix my tfaw, but as it stand currently this has pass ALL TESTS fft, y-crucher, HCI overnight, TM5 etc. (with the cpu clock speed set to auto limiting pbo values of course) simply locked the cpu speed for the aida bench. anyhow, finally got some improvements where it counted....
> 
> 
> i went back to like page 167 and started reading from there where all the voltage issues and talking's were and decided to try lowering my voltage, and well was able to lower voltages by quite the margin. still unsure what JEDEC RC 2.0 PCB actually is, but i have wrote teamgroup and asked. simply waiting for a reply (considering this is all stable at 1.4volts ??????? anyhow no errors no crashes no stutters no fallouts in chrome etc.....
> (edit adding pic)
> added my error report, (keep in mind the only errors im getting is due to trying to hoot up my SSK nvme enclosure on my case to which something is wrong with the ?enclosure, cable, port, header? unsure whats the actual issue. but it would crash windows explorer nearly everytime and lag out the desktop. both usb-c ports (front and rear do the same thing.) the drive works fine on type a ports, and all my other devices work fine on both usb-c ports, i have a usb-c 5gbs cable cominginstead of trying thunderbolt cables, and regular usb-c cables to where one gives to much and overloads the drive (or i think thats whats going on) and the other simply hits 40mbs instead of 1000....
> 
> anyhow, no errors other than the ones i created with the usb-c issues and the ones i made due to task killing razor software, and other software that auto start when my pc boots. will clear and use for the next few days and post error report again to show all is well under the hood of this (timing config to which doesnt look able to be stable)


Since we have the same board and same fclk, I'm just gonna post my stuff here, maybe that will help you.


----------



## craxton

Comalive said:


> Since we have the same board and same fclk, I'm just gonna post my stuff here, maybe that will help you.
> View attachment 2473109
> View attachment 2473110


cant really relate your scores to mine as your running a 5900x....???? all 5900x chips ive seen even without optimal timings get way better scores than those of a 5600x. your TRFC can use a fix tho, maybe this will help you with that. but yea, your running 4 sticks, 5900x not comparable to what ill see ever with a 5600x lol. go look at all the 5600x and compare those to the 5900x or 5800x vise versa.

you can look here for what 5600x usually get compared to 5900x and the other 5000 series chips....mines pretty much right with those shown in the google doc, and most have way better timings than i have. im unsure how much more im willing to go thru trial and error before i have a full head of grey hair at 31. but needless to say, the only thing wrong with my timings were Tfaw, and TRC to which veii was stating how one should go about getting these etc. if these are set to how was mentioned, scores go way down. and i start getting random hangs. 

do remember, a 5900x will beat the 5600x most the time in bandwidth across the board....and if you do look at the gdoc shown, youll see im well i think i already said that?? but yea i wont see your numbers on my half size chip...


----------



## Comalive

I didn't know that the CPU makes that much of a difference, Write Speed aside. I figured my timings might help you as I see that some of yours are worse than mine, while you have B-Die and I don't. That is assuming B-Die is just the best across the board, which of course might be wrong, I am still new to this after all

I might try lowering tRFC, I was going off a spreadsheet which suggested 600 for 4000 MT/s and I already set it lower than that. Maybe pushing it down ever further works at the same voltage, I don't want to just pump up voltage and brute force stuff though. I already added 10mV to get rid of the 1 error I found during memory testing.


----------



## craxton

Comalive said:


> (EDIT SPELL CHECK)
> 
> I didn't know that the CPU makes that much of a difference, Write Speed aside. I figured my timings might help you as I see that some of yours are worse than mine, while you have B-Die and I don't. That is assuming B-Die is just the best across the board, which of course might be wrong, I am still new to this after all
> 
> I might try lowering tRFC, I was going off a spreadsheet which suggested 600 for 4000 MT/s and I already set it lower than that. Maybe pushing it down ever further works at the same voltage, I don't want to just pump up voltage and brute force stuff though. I already added 10mV to get rid of the 1 error I found during memory testing.


i could be wrong, but im fairly sure the cpu will make a difference. and your running 4 sticks vs 2 which even my CJR 4000 darkzA kit (4x8) has better read and write speeds at 4000mhz 2000fclk with cl20 timings over what my 2x8 kit of bdie does now...but thats 4vs2 in my use case someone else may find better findings and have way tighter timings than what i have.

but if you click the first link i sent you, its pretty auto for what your gonna need. ill give you two options to choose from, if i can manage to get it working as for whatever reason its not allowing me to change any info to give trfc inputs that are correct for your timings. hold on a moment... got it, you can use either one of these and find stability which they should be stable granted your timings are correctly configured.
448-333-205 or392-291-179 which corresponds with your 4000mhzTCL16tRC 56. i usually always go for the lower set. but since your the safer out of us both, give the first set a try. dont adjust the first two TRFC values in bios options for our board. thats why your trfc is flat and the same all across scale. (fixed the error i caused there. sometimes this trfc mini calculator selects 3800mhz instead of what i selected which was 4000


----------



## craxton

Comalive said:


> I didn't know that the CPU makes that much of a difference, Write Speed aside. I figured my timings might help you as I see that some of yours are worse than mine, while you have B-Die and I don't. That is assuming B-Die is just the best across the board, which of course might be wrong, I am still new to this after all
> 
> I might try lowering tRFC, I was going off a spreadsheet which suggested 600 for 4000 MT/s and I already set it lower than that. Maybe pushing it down ever further works at the same voltage, I don't want to just pump up voltage and brute force stuff though. I already added 10mV to get rid of the 1 error I found during memory testing.


here ya go, figured out what was wrong with the tRFC calculator. but yea here it is thank Veii for this as i believe he made it/or she have yet to get confirmation on gender(not important) but yea, save that in bookmarks as itll be very usable over ryzen calcs trfc finder. Veii stated why if you wanna go back about 20 pages and find what was said. but in short, 1usmus calc is great for what it is, but for finding trfc values correctly one should try to use the mini calc linked above.


----------



## Comalive

craxton said:


> here ya go, figured out what was wrong with the tRFC calculator. but yea here it is thank Veii for this as i believe he made it/or she have yet to get confirmation on gender(not important) but yea, save that in bookmarks as itll be very usable over ryzen calcs trfc finder. Veii stated why if you wanna go back about 20 pages and find what was said. but in short, 1usmus calc is great for what it is, but for finding trfc values correctly one should try to use the mini calc linked above.


Thanks again, I had already looked at the calculator when you posted it the first time, you just had the htmlview still in the link as you also figured out by now. According to my information, ~290ns (tRFC = 580) is the low end of what my die can achieve. I am curious to see if the values you suggested would work, that would be quite the surprise for me. 

My tRFC values are flat because the option for all tRFCs, for some reason, overwrote the individual settings when being left on auto which is definitely not supposed to happen. It worked on the previous BIOS version, with the current one, however, it did behave in this strange manner. Then again, tRFC 2 and 4 don't matter anyway so that is a non-issue.

I will report back if your suggest tRFC will work for me, although I think I tried 560 before and that wouldn't boot. Anyway, I will report back on how it goes.


----------



## craxton

aditrex said:


> Yo guyz can someone help me out what could be wrong in my timings i get occt pass but i get random crashes to desktop when playing BFV multiplayer


first off before making any changes, save your profile to a USB flash drive so if you clear cmos and reset the bios your profile will still be there, from what i recall tho, boards set rather high voltages for VDDP, IOD, CCD etc. so from looking at yours it seems your voltages for VDDP, IOD, CCD are on the high side. if you click back about 15/20 pages Veii discusses this, and a few others comment on their own findings as well. your trfc values can be adjusted correctly too. also, if you have an overclock on your gpu lower it a little and see if that helps. i could go find this page i suppose which i did, 

this is what was stated by Veii
"cLDO_VDDP beyond 900mV is not needed
Not even with 2100FCLK. It's a waste to push it high, only degrades signal integrity, and pushes minimum usable voltage up for no reason.
950mV would be already "high"
beyond 1000 is a waste , it doesn't help anything. Doesn't even help coreOC. Maybe usable for -10c 24/7 XOC systems" 

there was other mentions etc but i couldn't find those mentioning's and gave up looking. was mentioned about crashes which your getting now play battlefield. so it may very well be just a minor voltage issue.


----------



## Comalive

I cannot even boot tRFC = 570 so I am pretty good with my 580. I am just gonna assume that Veii's calculator is for B-Die which has way lower tRFC (and tRC) values than anything else.


----------



## craxton

Comalive said:


> I cannot even boot tRFC = 570 so I am pretty good with my 580. I am just gonna assume that Veii's calculator is for B-Die which has way lower tRFC (and tRC) values than anything else.


you shouldnt set tRFC all the same value. at least set 2-4 correctly lol... and no, i dont believe this is only for bdie and where are you getting 570? 560-416-256 is what it should be...ill go to my bios and screenshot what im saying to change and not change...as two of the trfc options set a flat number which would be 580-580-580


----------



## craxton

Comalive said:


> I cannot even boot tRFC = 570 so I am pretty good with my 580. I am just gonna assume that Veii's calculator is for B-Die which has way lower tRFC (and tRC) values than anything else.


It's trfc1 560, trfc2 416, trfc4 256. Not trfc1/2/4 if trc=56 and tcl=16

It keeps auto changing to 516 but don't use that...


----------



## craxton

Comalive said:


> I cannot even boot tRFC = 570 so I am pretty good with my 580. I am just gonna assume that Veii's calculator is for B-Die which has way lower tRFC (and tRC) values than anything else.


(EDIT: updated trfc 580 to be with what your using currently) you wont have boot issues with these changes.

go to page 261 on this thread. youll see trfc1-2-4 all matter as rounding errors stack. so you for sure should find the correct values for the set.

since 580 is what works for you, this will be correct trfc1 580 trfc2 431 trfc4 265. enter those in. might not see any change but it will decrease any errors your not catching. (even if 570 is what it should be based on the calculator granted its correct based on what was just mentioned below my comment not accounting for dual rank kits in mind and needs updated later on to do so)


----------



## Veii

Comalive said:


> I cannot even boot tRFC = 570 so I am pretty good with my 580. I am just gonna assume that Veii's calculator is for B-Die which has way lower tRFC (and tRC) values than anything else.


Sorry let me get to you later too

It's IC universal - as it's based on tRC and tCL is trown in there "for good measure"
Initially it was based on other factors, but a bit of rounding issues happened
Lower than *6 is pretty hard to run - but that is also based on the "old ruleset" of "baseline stability"
Baseline timings to skip as much autocorrection as possible

If some of your timings are wrong to begin with, it wont work
But i know it doesn't factor in Dual Rank dies
It maybe shouldn't, as these only need a push on tRRD_ & tWTR_
According to JEDEC, i would need to factor them in, but i'll have to make a new range especially for 32gb dimms and higher (don't have anything to test & i guess people can figure out their tRFC range in ns)

Both Pre-Release (WIP) sheets have a manual mode
You can do the math and try to find a multiple of tRC
On some Dual Rank kits it would be 12* , on some it can go down to 10*tRC
Put that number in the right little box, and "manual" will display you the correct ones

tRFC 2 & 4 do matter like tCKE does now matter even with disabled GDM
I learned recently a lot on CAD_BUS Timings & 1x tFAW mode by psone from Chiphell [CH]
GDM On = 2.5T not 1.5T.
Knew GDM_Off 2T performed better but this pretty much confirms it too

@craxton
tFAW according to JEDEC is 4* tRRD_S. Over it, memory time breaks and stops the delay ~ it wastes a bit of time doing so
But there is another way to use it, soo i won't annoy people that much to fix it
It still should be a lower or equal than 4* tRRD_S ~ while most predictions put it higher
2x tFAW without fully shifting how timings behave under 1T is useless. 4* performs better as the transition is cleaner
1x tFAW of 6-10 will be explained another time, still a bit to research

About Vermeer,
Current vSoC implementation, behaves very similar to Intels IO/SA voltage
You sometimes need voltage in order to lower mem-latency, till a point where it won't lead any improvements anymore
I keep running lower voltage, but the same ruleset applies
4.6 Allcore CL18 flat timings @ 1.49v 1T
10Min R23 as stability test









4000MT/s up to my own testing needs 1.1375vSOC applied
usually it will scale till ~1.15v positive
His numbers are @ 1150VDDP,VDDG,32Ohm procODT
My range is @ 900-940-1060 34Ohm
But i've tested 1000VDDP,1000VDDG 32Ohm proc
feel a bit uncomfortable running beyond 1050 on my IMC, as it's not a bad one
_~but for testing purposes, these are the ranges / also readable here~








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




_
More information and help another time 
There is still a lot to research


----------



## aditrex

trying to get this kit stable but for some reason i always get some errors in memtest any suggestion what should i lose for timings?


----------



## craxton

aditrex said:


> trying to get this kit stable but for some reason i always get some errors in memtest any suggestion what should i lose for timings?


give 16,16,16,16,32,48 a try and fix your tRFC 1 tRFC 2 and tRFC 4 a fix. your correct values for trfc 1, 2, 4 should be 1, 480, 2, 357 3, 219 also, could try cabBUS 40 24 24 24 before hand and try that. it may very well solve your issue. but do fix tRFC can (to simply put it) instead of tRFC1/2/4 do tRFC 1 tRFC 2 tRFC 4 and input the values given. (NOTE: cadbus stranght can make or break that error you have. may make it better or make it worse. also, what voltage are you running for dram??

can use this to find your correct tRFC values for 1, 2, and 4 here


----------



## Comalive

craxton said:


> (EDIT: updated trfc 580 to be with what your using currently) you wont have boot issues with these changes.
> 
> go to page 261 on this thread. youll see trfc1-2-4 all matter as rounding errors stack. so you for sure should find the correct values for the set.
> 
> since 580 is what works for you, this will be correct trfc1 580 trfc2 431 trfc4 265. enter those in. might not see any change but it will decrease any errors your not catching. (even if 570 is what it should be based on the calculator granted its correct based on what was just mentioned below my comment not accounting for dual rank kits in mind and needs updated later on to do so)


Changed the tRFCs..not that I expect that to do anything, but hey.

Meanwhile I've tried to get rid of the WHEA 19 errors, this time for 1933 fclk. I managed to get it to not spit errors during desktop/web browsing with quite a few combinations, cache stressing still produces errors though. I am just not sure which voltages are the most important ones here, especially among the VDDGs. On top of that, increasing vSOC leads to more errors most of the time...what's the deal there?


----------



## Sphex_

Comalive said:


> Meanwhile I've tried to get rid of the WHEA 19 errors, this time for 1933 fclk. I managed to get it to not spit errors during desktop/web browsing with quite a few combinations, cache stressing still produces errors though. I am just not sure which voltages are the most important ones here, especially among the VDDGs. On top of that, increasing vSOC leads to more errors most of the time...what's the deal there?


This is where I'm at as well. No errors during idle and browsing, but under stress, WHEA 19 errors occur. What's interesting to me is that my chip seems to react in the opposite way. Raising vSOC *reduces* errors for me. Additionally, lowering VDDG, seems to cause them as well, specifically VDDG_CCD. Makes no sense how something can be 24/7 rock solid stable at 1900 FCLK, but bumping it up a mere 33 MHz suddenly causes WHEA errors with the same settings.


----------



## blu3dragon

Comalive said:


> Was added with 2004 afaik. I was also quiet surprised to see them after updating from 1909.


OK, well last night I couldn't get anything over 3200 FLCK stable!
Asus just released a new bios: 1602 with AGESA 1.1.9.0. I guess I'll give that a try...


----------



## Yviena

Just curious but what l3 cache bandwidth is normal for a 5900x?


----------



## halcyonon

Sphex_ said:


> Makes no sense how something can be 24/7 rock solid stable at 1900 FCLK, but bumping it up a mere 33 MHz suddenly causes WHEA errors with the same settings.


Welcome to the club, I can't get anything over 3600 to be stable, but am just fine at CL14 timings at 3600.


----------



## aditrex

craxton said:


> give 16,16,16,16,32,48 a try and fix your tRFC 1 tRFC 2 and tRFC 4 a fix. your correct values for trfc 1, 2, 4 should be 1, 480, 2, 357 3, 219 also, could try cabBUS 40 24 24 24 before hand and try that. it may very well solve your issue. but do fix tRFC can (to simply put it) instead of tRFC1/2/4 do tRFC 1 tRFC 2 tRFC 4 and input the values given. (NOTE: cadbus stranght can make or break that error you have. may make it better or make it worse. also, what voltage are you running for dram??
> 
> can use this to find your correct tRFC values for 1, 2, and 4 here


i cant change trfc 2 3 becouse its locked out in my bios ive was trying cl 16 timing like u suggested but still got error even faster lmao there is some funky things going in bios or just got with unlucky ram sticks again  im back to this not


----------



## KedarWolf

craxton said:


> Spoiler
> 
> 
> 
> first off before making any changes, save your profile to a USB flash drive so if you clear cmos and reset the bios your profile will still be there, from what i recall tho, boards set rather high voltages for VDDP, IOD, CCD etc. so from looking at yours it seems your voltages for VDDP, IOD, CCD are on the high side. if you click back about 15/20 pages Veii discusses this, and a few others comment on their own findings as well. your trfc values can be adjusted correctly too. also, if you have an overclock on your gpu lower it a little and see if that helps. i could go find this page i suppose which i did,
> 
> 
> 
> this is what was stated by Veii
> "cLDO_VDDP beyond 900mV is not needed
> Not even with 2100FCLK. It's a waste to push it high, only degrades signal integrity, and pushes minimum usable voltage up for no reason.
> 950mV would be already "high"
> beyond 1000 is a waste , it doesn't help anything. Doesn't even help coreOC. Maybe usable for -10c 24/7 XOC systems"
> 
> 
> 
> Spoiler
> 
> 
> 
> there was other mentions etc but i couldn't find those mentioning's and gave up looking. was mentioned about crashes which your getting now play battlefield. so it may very well be just a minor voltage issue.


Some peeps on 5000 series CPU had to raise the VDDP higher than .900v and raise VDDGs to get rid of WHEA errors.


----------



## marik123

It seems to me no matter what I tried, I just can't get 1900mhz FCLK to work on my system. I have a 5900x, x570 tuf board with latest 3202 BIOS and 4 sticks of b-die 3200c14 RAM o/c to 3733mhz. The highest RAM speed I can post with 4 stick in this motherboard is 3800mhz only with infinity fabric set to 1:2 ratio. As soon as I try 1:1 ratio, then stress test will either auto reboot or blue screen. I have tried and push the SOC voltage higher but then as soon as I try more than 1.1v SOC the system refused to boot. What can I do to resolve this problem? The only settings I touched so far is in the following..

CPU Vcore = 1.3v Manual mode
RAM Voltage = 1.4v
SOC voltage = 1.1v
everything else left at auto


----------



## blu3dragon

blu3dragon said:


> OK, well last night I couldn't get anything over 3200 FLCK stable!
> Asus just released a new bios: 1602 with AGESA 1.1.9.0. I guess I'll give that a try...


This bios gets me to 1866 without spitting out whea errors as soon as I start y-cruncher. Had to manually set voltages to post 1800 and above.

1900 refuses to post and I need to clear cmos to recover. 1933 posts the same as 1866, but it's instant whea errors. Tried raising voltages to no avail so I'm back to 1866 now.


----------



## blu3dragon

marik123 said:


> It seems to me no matter what I tried, I just can't get 1900mhz FCLK to work on my system. I have a 5900x, x570 tuf board with latest 3202 BIOS and 4 sticks of b-die 3200c14 RAM o/c to 3733mhz. The highest RAM speed I can post with 4 stick in this motherboard is 3800mhz only with infinity fabric set to 1:2 ratio. As soon as I try 1:1 ratio, then stress test will either auto reboot or blue screen. I have tried and push the SOC voltage higher but then as soon as I try more than 1.1v SOC the system refused to boot. What can I do to resolve this problem? The only settings I touched so far is in the following..
> 
> CPU Vcore = 1.3v Manual mode
> RAM Voltage = 1.4v
> SOC voltage = 1.1v
> everything else left at auto


Try manually setting VDDG IOD to 1.05 and CCD to 0.95.
If that fails you can try raising both VSOC and IOD 0.025v at a time (keeping IOD 0.05v lower than VSOC and don't go any higher than. 1.2v for VSOC)


----------



## halcyonon

mus1mus said:


> How are you setting up your OC?
> 
> Often times, I do my OC in steps just to avoid training issues and the like.
> 
> From a Default state (ideally, fresh BIOS install)
> 1. Set up Voltages - Core, SOC, IO, RAM etc.
> Reboot to BIOS
> 2. Set up Timings. Try 18-18-18-18-38 for giggles.
> Reboot to BIOS
> 3. Set up Clocks. RAM and FCLK, UCLK. It is also good to start with a static CPU Clock
> Hopefully you can reboot to BIOS.
> 
> If you get this far, try tuning your Memory down.
> 
> Might also be a good practice to save OC Profile after each step or after you boot to each step before changing anything so you can revert back if something goes wrong.
> 
> Hopefully this gets you to 1900 FCLK.


For step 2, what are you setting all your other timings to? Auto? I'm trying to figure out what "loose enough" timings I should have when trying to just boot at higher frequencies.. and what voltages etc should be tried just to find a starting point.


----------



## halcyonon

Couple questions:
1) Has anyone seen TM5 "hang" during test 3? The symptoms are it releases nearly all the memory, cpu usage drops to zero, and it doesn't move on to the next cycle, but also reports no errors. I can't tell if this is effectively an error itself in my memory, or some kind of bug with the program. Here is an example screenshot:









2) Can any of the pros here check my timings below and see if anything seems way off? I would have hoped latency should be lower than it is (and 58.6 in the screenshot below seems to be the lowest AIDA run I've had, most of the time it is more like 59-60ns)

RAM: 4x16GB B-die, Corsair Dominator Platinum RGB [email protected] 1.35v XMP.

VDIMM below is 1.43v.










Thanks!!


----------



## Nighthog

@halcyonon , it's unstable. 
Usually a voltage issue. Some part in the memory chain might need a little extra. Try VSOC ->VMEM ->VDDG ->VDDP etc.
Changing DrvStr, RTT & procODT might fix it as well if you have not optimized it fully yet.


----------



## YoungChris

I know this isn't a 24/7 screen but I figured you daily/experienced Zen 3 users would have the information I needed.








I noticed my L3$ bandwidth is pretty low, only 340gb/s or so. I've seen other single CCD user in the 670gb/s range, is there something I'm missing? I have experience with memory tuning in general, but I don't have much experience with AMD. My Geekbench 3 performance is still good, but I'd think running at half L3$ bandwidth would gimp my score somewhat.


----------



## Gadfly

I have a request; I am looking for a Zentimings screenshot of a 2x16GB setup running at 4000MT/s

Thanks!


----------



## blu3dragon

Memtest stable, vdimm at 1.48v, but NOT y-cruncher (or other FCLK stress test) stable ;-)


----------



## halcyonon

blu3dragon said:


> Memtest stable, vdimm at 1.48v, but NOT y-cruncher (or other FCLK stress test) stable ;-)


Saw you using Memtest, any opinion on which finds errors faster out of it, TM5 with Anta or 1usmus, or Karhu?


----------



## halcyonon

YoungChris said:


> I noticed my L3$ bandwidth is pretty low, only 340gb/s or so. I've seen other single CCD user in the 670gb/s range, is there something I'm missing? I have experience with memory tuning in general, but I don't have much experience with AMD. My Geekbench 3 performance is still good, but I'd think running at half L3$ bandwidth would gimp my score somewhat.


Mine looks like this too on a 5950x, I think this is an artifact and doesn't represent reality.. if I turn on Fmax enhancer in the bios it immediately goes to >1,200GB/s, and posts a slightly higher peak speed, but loses performance in R20/23, so I personally am not worried about it.


----------



## juan197

Hello!! , I am going to change 4x8gb (Micron E-die) sticks of Crucial Ballistix MAX RGB 4000 cl18 Crucial Ballistix MAX RGB 16GB Kit (2 x 8GB) DDR4-4000 Desktop Gaming Memory (Black) | BLM2K8G40C18U4BL | Crucial.com for a kit 2x16gb F4-3600C16D-32GTZN F4-3600C16D-32GTZN-G.SKILL International Enterprise Co., Ltd.
Going to change to dual rank B-die, because I don't feel comfortable with all the slots occupied. I keep well at 3733 16-18-18-18-38 IF 1:1 but I can't get expected latencies (always at 60 / 61ns) and I have a hard time playing a lot to keep 3800 with 1: 1 IF having to raise the Vdimm a lot and relaxing latencies to get worse results, same with @ 4000 (with A-XMP is disastrous and for 4000 cl16 it is torture)
My setup 5900x + MSI x570 Tomahawk Wifi.
Can I have expectations with these GSkill memories from a 3800/3866 and can I play a bit at 4000 cl16?
Anyway, I think the change can't be bad at all.


----------



## craxton

aditrex said:


> i cant change trfc 2 3 becouse its locked out in my bios ive was trying cl 16 timing like u suggested but still got error even faster lmao there is some funky things going in bios or just got with unlucky ram sticks again  im back to this not


do note that if you set a value for tRFC 1/2/4 in bios it wont allow you to adjust indivually tRFC 1 tRFC 2 or tRFC 4 as one should be able to. i thought i was locked out until seeing that i was changing 1/2/4 all together when they have their own induvial vale settings.


----------



## craxton

just got these scores and finally adjusted pbo values to where i dont blue screen, no WHEA errors of any kind. TM5 passed 1000% HCI passed overnight stressing, y cruncher finally passed as well, but did hit 85c so i may lower pbo values a little more....


----------



## blu3dragon

craxton said:


> just got these scores and finally adjusted pbo values to where i dont blue screen, no WHEA errors of any kind. TM5 passed 1000% HCI passed overnight stressing, y cruncher finally passed as well, but did hit 85c so i may lower pbo values a little more....
> View attachment 2473358


Nice work, I think that's a good chip if you are y-cruncher stable with no WHEA errors at 2000 FLCK!


----------



## mikalcarbine

craxton said:


> just got these scores and finally adjusted pbo values to where i dont blue screen, no WHEA errors of any kind. TM5 passed 1000% HCI passed overnight stressing, y cruncher finally passed as well, but did hit 85c so i may lower pbo values a little more....
> View attachment 2473358


What SOC and other voltages did you use?


----------



## blu3dragon

So after exploring DDR4-4000, discovering WHEA errors at anything over DDR4-3200 (FLCK 1600) after updating windows, updating to the latest bios and getting it back to 3733, I'm now settling on 3600 (FCLK 1600) as the best place to be for maximum real world performance with 24/7 stability.

5800x, ASUS B550-F, latest BIOS (1602 AGESA V2 PI 1.1.9.0), 2x16Gb Gskill Ripjaws V DDR4-3200 CL14 

Running at DDR4-3600 14-14-14-28 CR1 at 1.44v. Memtest 1000% & y-cruncher N32 & N64 looped for >1hr with no WHEA errors. Also single core p95 no avx stable set affinity to each core for several minutes each, to two worst cores for ~1hr each and to all cores for >1hr.

I can get to an FLCK of 1866 without WHEA errors. BUT, I need to raise VSOC and IOD to do that which puts more heat into the cpu, which then means it doesn't boost quite as high as if I keep FCLK at 1800 where I don't need to raise any voltages from the defaults. The difference is very small, but after some tuning of the memory timings at DDR4 3600 I am now at my highest stable 3dmark cpu score to date (12,900). That almost matches my previous best of 13,000, which I got at ddr-4000 cl16, but with WHEA errors and PBO curve settings not 100% stable allowing the cores to boost slightly higher.


----------



## mikalcarbine

halcyonon said:


> Couple questions:
> 1) Has anyone seen TM5 "hang" during test 3? The symptoms are it releases nearly all the memory, cpu usage drops to zero, and it doesn't move on to the next cycle, but also reports no errors. I can't tell if this is effectively an error itself in my memory, or some kind of bug with the program. Here is an example screenshot:
> View attachment 2473199





Nighthog said:


> @halcyonon , it's unstable.
> Usually a voltage issue. Some part in the memory chain might need a little extra. Try VSOC ->VMEM ->VDDG ->VDDP etc.
> Changing DrvStr, RTT & procODT might fix it as well if you have not optimized it fully yet.


Are you 100% this is a sign of instability? I've had a many periods where TM5 will hang between cycles with either 1usmus or Anta Extreme configs but I test stable with long run tests of y-cruncher, MT and Kahru.


----------



## bwana

B550 Unify, 5950x CPU stock w PBO enabled
Memory 16-16-16-36-4000 @ 1.45v









Boots and windows runs but fails Karhu as well as TM5 w AntaExtreme settings









On the TM5 thread it lists several types of errors but obviously TM5 is speaking a language my PC does not. How can I further figure out how to increase memory stability?


----------



## DeletedMember558271

craxton said:


> just got these scores and finally adjusted pbo values to where i dont blue screen, no WHEA errors of any kind. TM5 passed 1000% HCI passed overnight stressing, y cruncher finally passed as well, but did hit 85c so i may lower pbo values a little more....
> View attachment 2473358


B550 Gaming Edge? Shouldn't be any better than my B550 Tomahawk or getting any better BIOS treatment, I don't know if it could be cause I'm 4x8GB or what's different about my config that WHEA errors 1933+, 1900 doesn't post.
I tried your voltages, you didn't even have to set any of them that high.
I wish I knew how other B550 Tomahawk owners were doing, especially if they're 4x8GB


----------



## mikalcarbine

bwana said:


> B550 Unify, 5950x CPU stock w PBO enabled
> Memory 16-16-16-36-4000 @ 1.45v
> View attachment 2473401
> 
> 
> Boots and windows runs but fails Karhu as well as TM5 w AntaExtreme settings
> View attachment 2473402
> 
> 
> On the TM5 thread it lists several types of errors but obviously TM5 is speaking a language my PC does not. How can I further figure out how to increase memory stability?


Try swapping over to the 1usmus v3 config and see what errors it gives. I know they are similar but some are flipped around. You can then use the TM5 error drop down on this sheet to help troubleshoot what the source may be









Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com


----------



## bwana

mikalcarbine said:


> Try swapping over to the 1usmus v3 config and see what errors it gives. I know they are similar but some are flipped around. You can then use the TM5 error drop down on this sheet to help troubleshoot what the source may be
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com


Thank you. I'll try that later. But I upped the vDIMM to 1.47v, set command rate to 2T, and disabled gear down. Got it Karhu stable to 400%. How long should I run TM5? Is 1.47v tolerable for a daily driver? It's silly how I cannot use an odd number for tCL.


----------



## DeletedMember558271

bwana said:


> Thank you. I'll try that later. But I upped the vDIMM to 1.47v, set command rate to 2T, and disabled gear down. Got it Karhu stable to 400%. How long should I run TM5? Is 1.47v tolerable for a daily driver? It's silly how I cannot use an odd number for tCL.
> View attachment 2473457


63.6ns might be by far the worst result I've seen








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com




I don't see the point stress testing these settings, they need to change.
Also do you need VDDP, CCD, and IOD higher than vSOC? And any WHEA errors?


----------



## WuffMiau

Hello,
I have a question regarding what to use in order to test memory (Ballistix E-Die) for stability.
I used TM5 with [email protected] (@1500%) over night and it completed without errors.
Then I used 1usmus_v3 (@1000%) and got two errors after two cycles...

I have then used y-cruncher because I have red about it here, and it also ran without issues.
You can find my timings below, DRAM voltage is set to 1,40 V

I had also used the membench in the 1usmus DRAM calc, and in the morning the PC had always rebooted (according to CPU start time it ran ~2,5h).

So what test am I supposed to do? Must they all complete without error?

Thx for an advice, I know there is also a ton of information in this topic, but it is quite hard to find it in all those pages.

I have a little thermal camera, and I got temp readings of 65 °C after the 8h test overnight, that is also the reason why I do not really want to increas DRAM voltage.


----------



## Nighthog

mikalcarbine said:


> Are you 100% this is a sign of instability? I've had a many periods where TM5 will hang between cycles with either 1usmus or Anta Extreme configs but I test stable with long run tests of y-cruncher, MT and Kahru.


It's a stability issue if a little extra tuning gets it fixed in most cases. I've allways found a way to fix this error when it occurs by a little extra tweaking. As said, you can try several things to see what in the end is the trouble point, as you no longer will get this issue when you get it stable 100% rather than 99.999%.


----------



## Chili195

bonet69 said:


> I have similar kit, this are my settings:
> 
> 
> 
> I am able to run it with 1.49v but that might be not your case, try first with timings 14-8-15-14-28-42 at 1.5v if that gives you no error go for 14-8-14-14 and then 14-8-14-13
> 
> Regards


This is really useful thanks. I have the same 2x16GB kit and tried your exact settings but still having some real trouble trying to tighten up my timings at 3800. It seems to fine on 16-19-19-19 at v1.42. Even upping the VDIMM to 1.5v though and I can't get 14-15-15-15 to work. It'll run fine in Y-Cruncher and three cycles of [email protected] on TM5. But Karhu will usually throw an error a few thousand percent in. 










Any ideas?


----------



## craxton

mikalcarbine said:


> What SOC and other voltages did you use?


since for whatever reason anything i screenshot in the bios using a flash drive i cant see when im in windows (maybe the drive isnt formatted in the correct way unsure) but yea my bad. here is the settings im running. no errors other than as i always state (THE ONES I CREATE) lol. as in task killing or force killing apps. only time i had any crashes was when messing with CURVE settings....


----------



## craxton

Chili195 said:


> This is really useful thanks. I have the same 2x16GB kit and tried your exact settings but still having some real trouble trying to tighten up my timings at 3800. It seems to fine on 16-19-19-19 at v1.42. Even upping the VDIMM to 1.5v though and I can't get 14-15-15-15 to work. It'll run fine in Y-Cruncher and three cycles of [email protected] on TM5. But Karhu will usually throw an error a few thousand percent in.
> 
> View attachment 2473490
> 
> 
> Any ideas?


you can try proc odt increasing be the easiest way to solve an error. if your throwing just one or two that late into a test anyhow.


----------



## halcyonon

mikalcarbine said:


> Are you 100% this is a sign of instability? I've had a many periods where TM5 will hang between cycles with either 1usmus or Anta Extreme configs but I test stable with long run tests of y-cruncher, MT and Kahru.


I'm looking to validate that now... currently at 500+% on MemTestPro. I think there is a decent chance it could just be a bug in TM5, it doesn't scream to me that it is the most well written piece of software.


----------



## Comalive

halcyonon said:


> I'm looking to validate that now... currently at 500+% on MemTestPro. I think there is a decent chance it could just be a bug in TM5, it doesn't scream to me that it is the most well written piece of software.


The dude behind it is writing memtest software since the 90s so that is an interesting view you have.


----------



## craxton

Dreamic said:


> 63.6ns might be by far the worst result I've seen
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> I don't see the point stress testing these settings, they need to change.
> Also do you need VDDP, CCD, and IOD higher than vSOC? And any WHEA errors?


if they're not killing any background tasks or apps, latency will shoot SKY HIGH... mine will run 63.1/7 without killing synapse, PX1, AB, IDM, etc. but once i shut those down, its 52.3/5 depending on if im running zen timings or not and turning off windows defender.

clock speed also affects latency as well as L3 and L1 cache speeds.... (only thing different between the two runs are killing tasks, turning off defender, and using ryzen master to set static 4850 clock speeds. as it would seem my last visit inside the bios i removed my 200mhz auto oc for whatever reason....i will state mine didnt shoot to 63 anywhere near it. but point still shows my claims... only thing in the foreground that was running during tests was AIDA, task manager was pulled after the runs were finished.


----------



## craxton

halcyonon said:


> I'm looking to validate that now... currently at 500+% on MemTestPro. I think there is a decent chance it could just be a bug in TM5, it doesn't scream to me that it is the most well written piece of software.


you could use prime95 SFF or Y-CRUNCHER if your that worried TM5 isnt correctly stressing your ram as you want it to be? best to run several tests once one is finished back to back to provide a daily stable anyhow tho. OCCT is another you can use.


----------



## halcyonon

Comalive said:


> The dude behind it is writing memtest software since the 90s so that is an interesting view you have.


Then isn't it logical to assume that after two decades, if it is an actual error, that the software would be able to report said error instead of releasing memory, stopping all CPU usage, and just hanging out? Just because software is "old", regardless how many releases/revisions it has had (and TM hasn't had that many for that amount of time), it doesn't mean it is bug free.


----------



## halcyonon

craxton said:


> you could use prime95 SFF or Y-CRUNCHER if your that worried TM5 isnt correctly stressing your ram as you want it to be? best to run several tests once one is finished back to back to provide a daily stable anyhow tho. OCCT is another you can use.


100% agree, in progress now.


----------



## bwana

Dreamic said:


> 63.6ns might be by far the worst result I've seen
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> I don't see the point stress testing these settings, they need to change.
> Also do you need VDDP, CCD, and IOD higher than vSOC? And any WHEA errors?


Yeah, I actually have better latency at CAS 14 DDR 3600 (60 ns). I could not understand why the latency became bad- sort of paradoxical. Here are some more images:


















This fellow on you tube had similar paradoxical results

https://www.youtube.com/watch?v=dhXq...levatedSystems

poorer performance at higher memory speeds. He attributed it to the power budget of the cpu. As you increase memory demand, the cpu has less power to 'boost' with, and so it down clocks. Although memory latency isnt technically a cpu function, the actual transaction - reading writing and copying- is initiated by the cpu.

And no, the only voltage increased is vDIMM to 1.45. The only change to the CPU OC section is enabling PBO but no changes to the curve optimizer, no auto overclock, nothing else. I need to do a more controlled study. I have to clear cmos and run a stock bios with out any changes except DDR speed. Who knows what PBO is doing, really. It's supposed to simply allow the cpu to drink more power (and mine certainly does reaching 220w - that's double the TDP) My temps never exceed 60 degrees. Ram stays cool as well- the board is on a bench.


----------



## halcyonon

bwana said:


> Yeah, I actually have better latency at CAS 14 DDR 3600 (60 ns). I could not understand why the latency became bad- sort of paradoxical. Here are some more images:
> 
> This fellow on you tube had similar paradoxical results
> 
> https://www.youtube.com/watch?v=dhXq...levatedSystems
> 
> poorer performance at higher memory speeds. He attributed it to the power budget of the cpu. As you increase memory demand, the cpu has less power to 'boost' with, and so it down clocks. Although memory latency isnt technically a cpu function, the actual transaction - reading writing and copying- is initiated by the cpu.
> 
> And no, the only voltage increased is vDIMM to 1.45. The only change to the CPU OC section is enabling PBO but no changes to the curve optimizer, no auto overclock, nothing else. I need to do a more controlled study. I have to clear cmos and run a stock bios with out any changes except DDR speed. Who knows what PBO is doing, really. It's supposed to simply allow the cpu to drink more power (and mine certainly does reaching 220w - that's double the TDP) My temps never exceed 60 degrees. Ram stays cool as well- the board is on a bench.


I've been wondering if there is something about the 5950s that also increases latency.. I've tested with identical memory timings to others here on 56/5800s, and seen theirs be 2-3ns faster. There are lots of variables of course, but it is on a clean Windows install with no gunk, Dark Hero mobo on the latest non-beta bios.


----------



## DeletedMember558271

A lot of your timings are also just stupid high, like for that 3800 pic tRC, tRRDS, tRRDL, tFAW, tWR, tRTP could all be like halved


----------



## Dollar

Dreamic said:


> A lot of your timings are also just stupid high, like for that 3800 pic tRC, tRRDS, tRRDL, tFAW, tWR, tRTP could all be like halved


All of those combined are not going to cause a 6ns+ latency penalty especially with a 200MHz memory clock bump. Something else is wrong.

@bwana what does 3666/3733 look like with the same timings?


----------



## bwana

ok.
I set the pc to safe mode.
Cleared CMOS
Set vDIMM to 1.46v for all testing
CPU settings were stock for the first tests and then PBO was enabled for a few more.
The data were gathered using Aida and tabulated in Google sheets here:






Google Sheets: Sign-in


Access Google Sheets with a personal Google account or Google Workspace account (for business use).



docs.google.com





best results were at 4000/2000. Although I could run at 4066/2033, the results were worse.
Also, PBO causes L# cache read speeds to take a massive hit.

I will be repeating some of these tests in regular mode. I will stop certain processes and services before each run. 
BTW, in safe mode neither zen timings nor ryzen master will run so I have no data on other physical parameters.


----------



## bwana

I will be testing the following two configurations in addition to safe mode.
Regular mode which has these processes running in the background:










and a Minimal Mode which has these:










Basically, I killed steam, dropbox, cortana, afterburner ,rtss, macrium ( a backup svc), everything( search indexing service), microsoft edge (I never noticed but it runs in the background-I guess that's why people think it is 'faster'),microsoft store, microsoft text input, microsoft photos.

And for reference, this is what safe mode looks like


----------



## KingEngineRevUp

bwana said:


> Yeah, I actually have better latency at CAS 14 DDR 3600 (60 ns). I could not understand why the latency became bad- sort of paradoxical. Here are some more images:
> 
> 
> View attachment 2473547
> 
> 
> This fellow on you tube had similar paradoxical results
> 
> https://www.youtube.com/watch?v=dhXq...levatedSystems
> 
> poorer performance at higher memory speeds. He attributed it to the power budget of the cpu. As you increase memory demand, the cpu has less power to 'boost' with, and so it down clocks. Although memory latency isnt technically a cpu function, the actual transaction - reading writing and copying- is initiated by the cpu.
> 
> And no, the only voltage increased is vDIMM to 1.45. The only change to the CPU OC section is enabling PBO but no changes to the curve optimizer, no auto overclock, nothing else. I need to do a more controlled study. I have to clear cmos and run a stock bios with out any changes except DDR speed. Who knows what PBO is doing, really. It's supposed to simply allow the cpu to drink more power (and mine certainly does reaching 220w - that's double the TDP) My temps never exceed 60 degrees. Ram stays cool as well- the board is on a bench.


I'm no expert but even I can tell a lot of your timings are off. Sure you set nice primary timings but everything else can be more better optimized.


----------



## BluePaint

@bwana 
Use this for trfc trfc calculator


----------



## Fanu

I've been following guides on getting lower temps on my 5800X 

I've set curve optimizer to -25 (-10 for fastest 2 cores) and PBO +100MHz - with these settings I get better performance then stock but I still hit 90C on CPU

so I started lowering PPT/TDC/EDC, lowered EDC first and noticed AIDA64 reporting significantly slower L3 cache speeds in memory benchmark (from stock 350~ to 200~)

Is this an issue? Are all the guides online suggesting PPT/TDC/EDC be lowered for same performance but much lower operating temps (up to 15C) wrong (temps are lower, but performance is as well)?


----------



## Spectre73

Fanu said:


> I've been following guides on getting lower temps on my 5800X
> 
> I've set curve optimizer to -25 (-10 for fastest 2 cores) and PBO +100MHz - with these settings I get better performance then stock but I still hit 90C on CPU
> 
> so I started lowering PPT/TDC/EDC, lowered EDC first and noticed AIDA64 reporting significantly slower L3 cache speeds in memory benchmark (from stock 350~ to 200~)
> 
> Is this an issue? Are all the guides online suggesting PPT/TDC/EDC be lowered for same performance but much lower operating temps (up to 15C) wrong (temps are lower, but performance is as well)?


I do not know if this is working as intended but thiss is normal behaviour with the current UEFI implementations. You can increase throughput by increasing EDC higher and higher. The L3 throughput increases, but overall performance in benchmarks (synthetic) decreases. Someone reported better 0.1% lows in games but I have read no confirmation of this.


----------



## Fanu

Spectre73 said:


> I do not know if this is working as intended but thiss is normal behaviour with the current UEFI implementations. You can increase throughput by increasing EDC higher and higher. The L3 throughput increases, but overall performance in benchmarks (synthetic) decreases. Someone reported better 0.1% lows in games but I have read no confirmation of this.


so there is no real downside to lowering EDC ? Are there any benefits to lower EDC (longer sustained boost clocks, higher performance, etc)?


----------



## bwana

YoungChris said:


> I know this isn't a 24/7 screen but I figured you daily/experienced Zen 3 users would have the information I needed.
> View attachment 2473258
> 
> I noticed my L3$ bandwidth is pretty low, only 340gb/s or so. I've seen other single CCD user in the 670gb/s range, is there something I'm missing? I have experience with memory tuning in general, but I don't have much experience with AMD. My Geekbench 3 performance is still good, but I'd think running at half L3$ bandwidth would gimp my score somewhat.


I found that enabling PBO cuts read copy speed in the L3 cache by half on an msi unify


----------



## bwana

Dreamic said:


> A lot of your timings are also just stupid high, like for that 3800 pic tRC, tRRDS, tRRDL, tFAW, tWR, tRTP could all be like halved


Ok I get that. I would like to set them myself. Do you have specific recommendations? I will set those and rerun tests


----------



## bwana

Dreamic said:


> 63.6ns might be by far the worst result I've seen
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> I don't see the point stress testing these settings, they need to change.
> Also do you need VDDP, CCD, and IOD higher than vSOC? And any WHEA errors?


this fellow has a similar latency at ddr 4000



https://hardforum.com/threads/ryzen-5900x-overclocking-help.2005401/page-4



he is on a dark hero and cannot get below tCl 18 though


----------



## bwana

Here is the pic from his thread

View attachment 2473597


----------



## elvior2

Hi @all,

After reading so many posts and following the explanations / tips that are suggested in this forum, I think I've managed to achieve a pretty stable config, nothing crazy better step by step.

Probably many things can be still be improved and I would really apreciate more suggestions, but I have one doubt regading VDDG IOD and CCD voltages.

Which is the relationship between those? Should the have the same voltage? CCD lower than IOD?

The only thing that is more or less clear from what I've read is that VDDG IOD has to be -0.050 lower than SoC but what about CCD?

I leave it on Auto at the begining but thing is I cannot which is the value as software is not monitoring it (RyzenMaster, ZenTimings, and Bios neither), so I putted both IOD and CCD to 1025mv.

In BIOS

SoC: 1.0875V (1.0750 under load)
cLDO_VDDP: 900mv
IOD: 1025mv
CCD: 1025mv
DRAM: 1.37v
LLC for CPU and NB: Mode 3



















Thanks in advance!


----------



## Chili195

craxton said:


> you can try proc odt increasing be the easiest way to solve an error. if your throwing just one or two that late into a test anyhow.


Thanks, I had upped it to 43.6 but still not stable after a while. I ended up getting fed up and setting all the memory related voltages (except VDIMM) to Auto and using what the motherboard set and funnily enough those seem to have gone fine (9000% in Karhu and TM5/Y-Cruncher passing fine). 

















I'll now either try and lower the memory voltage from 1.5v (as I'm pretty sure some of the instability was from temperature related issues) or tighten the timings a bit and see how far I can get. 

Just out of interest, what sort of cooling solution (if any) are people using on their Samsung B-Dies at 1.5v?


----------



## dr.Rafi

Fanu said:


> I've been following guides on getting lower temps on my 5800X
> 
> I've set curve optimizer to -25 (-10 for fastest 2 cores) and PBO +100MHz - with these settings I get better performance then stock but I still hit 90C on CPU
> 
> so I started lowering PPT/TDC/EDC, lowered EDC first and noticed AIDA64 reporting significantly slower L3 cache speeds in memory benchmark (from stock 350~ to 200~)
> 
> Is this an issue? Are all the guides online suggesting PPT/TDC/EDC be lowered for same performance but much lower operating temps (up to 15C) wrong (temps are lower, but performance is as well)?


To Lower temp reduce only PPT till you get what you like with load temp, will reduce performance but less costly than reducing EDC and TDC


----------



## bwana

Thank you Dreamic and KingEngineRevup. I tightened things up and am now here at 1.5vDIMM









I didnt know how to use that calculator. I might try to go lower on tRAS.
Is 1.5v not recommended for daily?


----------



## bonet69

Chili195 said:


> Thanks, I had upped it to 43.6 but still not stable after a while. I ended up getting fed up and setting all the memory related voltages (except VDIMM) to Auto and using what the motherboard set and funnily enough those seem to have gone fine (9000% in Karhu and TM5/Y-Cruncher passing fine).
> 
> View attachment 2473631
> View attachment 2473632
> 
> 
> I'll now either try and lower the memory voltage from 1.5v (as I'm pretty sure some of the instability was from temperature related issues) or tighten the timings a bit and see how far I can get.
> 
> Just out of interest, what sort of cooling solution (if any) are people using on their Samsung B-Dies at 1.5v?


This ram will throw errors and fps drops if you pass 45 degress (at 1.5v+-), i have this timings (if you are lucky you should be able to lower tRCDRD to 14 if not 15 its fine):










Also tRCDWR to 8 will work for sure, and tRP to 14 should be ez too, i am currently running at 1.49v without errors, but as said not all sticks can do it, also SCLs to 2 should be fine.

EDIT: i read now u quoted me before, the errors are probably temp related monitor (with hwinfo) you dont go over 45 degress, up the speed of the nearest fans to the ram or think about additional fan for ram, i dont need it now, but maybe in summer i will need it.... Also you can try copyng my voltages, soc, vddp, vddgs...



bwana said:


> Thank you Dreamic and KingEngineRevup. I tightened things up and am now here at 1.5vDIMM
> View attachment 2473644
> 
> 
> I didnt know how to use that calculator. I might try to go lower on tRAS.
> Is 1.5v not recommended for daily?


Are you sure that its not throwing WHEA errors? You can check doing a test with OCCT (SSE test extreme should throw them fast or dont if its stable) I can boot at 2033 fclk but i get whea errors in hwinfo or occt with more than 1900+ fclk....

Regards!


----------



## bigblueshock

I have a Gigabyte Aorus Master X570
3900x
GeForce 1080 Ti
Four sticks of 8GB G.Skill 3600 C15 B-Die


Add me to the WHEA Error 18 club. Hopefully someone could give me advice on slight adjustment of memory timings.

I was (or so I thought) 100% stable. Ran 1usmus Ryzen DRAM Calculator Memtest for over 5 hours, no crashing in hours of gaming, or any other time. Haven't done a TM5 test or anything else. No problems since I put together my rig really, other than minor tweaks to DRAM timings. No CPU OC's, just strictly memory.

Due to the recent "crypto craze" I decided to fire up mining software just to play around with it. It is GPU Only mining, no GPU Overclock. I let it run for 2 hours, boom, reboot with WHEA Error 18. Rinse and repeat, every 2 hours. Very odd!

Thought it could be the Video Card, but I tried another nVidia card with same issue. Also have the latest drivers.

I find it hard to believe it's the cards.

Things I've tried (I've since switched back):
1) Raised ProcODT to 40+
2) Raised VDDG to 1.05


I have not touched SOC, it's currently at 1.1 - Also below are my ZenTimings.

Any recommendations?

Thank you!


----------



## halcyonon

bwana said:


> Thank you Dreamic and KingEngineRevup. I tightened things up and am now here at 1.5vDIMM
> 
> 
> I didnt know how to use that calculator. I might try to go lower on tRAS.
> Is 1.5v not recommended for daily?


What RAM is that, and is it stable??


----------



## halcyonon

bigblueshock said:


> I was (or so I thought) 100% stable. Ran 1usmus Ryzen DRAM Calculator Memtest for over 5 hours, no crashing in hours of gaming, or any other time.


5h test is not very long, I've observed errors occur routinely at the 20-22 hour mark in my own testing. And these are not 'new' errors where suddenly the memory got warmer 20 hours in, they were at peak temp 30 minutes into testing and stayed that way.


----------



## bigblueshock

halcyonon said:


> 5h test is not very long, I've observed errors occur routinely at the 20-22 hour mark in my own testing. And these are not 'new' errors where suddenly the memory got warmer 20 hours in, they were at peak temp 30 minutes into testing and stayed that way.


I agree. I may try running it for 24 hours. I also have a memory cooler so that helps a lot. Even when stress testing, the DIMM's do not go above 40c. I just find it odd it occurs when CPU is completely idle, close to 0% usage.


----------



## Xetag

halcyonon said:


> What RAM is that, and is it stable??


Sorry, I'm not OP, but that is G.Skill F4-3600C14-16GTZN


----------



## DeletedMember558271

bonet69 said:


> This ram will throw errors and fps drops if you pass 45 degress (at 1.5v+-), i have this timings (if you are lucky you should be able to lower tRCDRD to 14 if not 15 its fine):
> 
> View attachment 2473691
> 
> 
> Also tRCDWR to 8 will work for sure, and tRP to 14 should be ez too, i am currently running at 1.49v without errors, but as said not all sticks can do it, also SCLs to 2 should be fine.
> 
> EDIT: i read now u quoted me before, the errors are probably temp related monitor (with hwinfo) you dont go over 45 degress, up the speed of the nearest fans to the ram or think about additional fan for ram, i dont need it now, but maybe in summer i will need it.... Also you can try copyng my voltages, soc, vddp, vddgs...
> 
> 
> 
> Are you sure that its not throwing WHEA errors? You can check doing a test with OCCT (SSE test extreme should throw them fast or dont if its stable) I can boot at 2033 fclk but i get whea errors in hwinfo or occt with more than 1900+ fclk....
> 
> Regards!


Damn... 4x8GB 4400C19 Vipers here and I need 1.53v for 3733C14 (can't post 1900 on B550 Tomahawk), and even with an NF-A14 blowing directly on the RAM it will overheat and error if I'm stressing the GPU & CPU enough to warm up my case and room. Play a demanding game/benchmark that gets 3080 and 5800x 100% and fire up TM5 right after before anything cools down, errors.

I think you're lucky 1.49v, what is your latency?
My sticks don't even have temp sensors so I have no idea what they're at, but now that I'm thinking about it maybe I should've gone 2x16GB for the free space between the DIMMs so they might not be so hot, easier for air to blow in there too. Maybe the most meaningful difference between 4x8GB and 2x16GB and I didn't even think about it


----------



## blu3dragon

dr.Rafi said:


> To Lower temp reduce only PPT till you get what you like with load temp, will reduce performance but less costly than reducing EDC and TDC


Or just set a lower platform thermal throttle limit in the bios and let PB figure out the power limit for you to keep it below whatever temp you are comfortable with. At least, that's the way I did it and it seems to work pretty well.


----------



## bonet69

Dreamic said:


> Damn... 4x8GB 4400C19 Vipers here and I need 1.53v for 3733C14 (can't post 1900 on B550 Tomahawk), and even with an NF-A14 blowing directly on the RAM it will overheat and error if I'm stressing the GPU & CPU enough to warm up my case and room. Play a demanding game/benchmark that gets 3080 and 5800x 100% and fire up TM5 right after before anything cools down, errors.
> 
> I think you're lucky 1.49v, what is your latency?
> My sticks don't even have temp sensors so I have no idea what they're at, but now that I'm thinking about it maybe I should've gone 2x16GB for the free space between the DIMMs so they might not be so hot, easier for air to blow in there too. Maybe the most meaningful difference between 4x8GB and 2x16GB and I didn't even think about it












You should be able to check ram temps in hwinfo i think, 4 sticks will be able to get a little bit less latency than 2 dual rank sticks and it will be easier to make gdm off with single rank sticks, thats where u get more performance than dual ranked, but of course 4 sticks will be hotter than 2 sticks sr or dr. If i increase cpu speed i get even lower latency but i found 4.6 ghz is the sweet spot for my cpu ( i dont care for 1-2 fps more of 4.7 ghz if its not 100% stable)

I know i could lower even more some subtimings and while it will achieve lower latency it will also give me lower fps in games, sooo this is the best i could do!

Regards


----------



## qwrty

Hello

@Veii

Do you know why L3 cache bandwidth is bad when using new SMU ?
Did AMD do something in latest SMU to restricted bandwidth ?

With 5950x on older SMU I had 600/700 gbit/s , now between 500/600 gbit/s.


----------



## halcyonon

qwrty said:


> Hello
> 
> @Veii
> 
> Do you know why L3 cache bandwidth is bad when using new SMU ?
> Did AMD do something in latest SMU to restricted bandwidth ?
> 
> With 5950x on older SMU I had 600/700 gbit/s , now between 500/600 gbit/s.


Are you using PBO[2]?


----------



## juan197

Hello!!
My Ram F4-3600C16D-32GTZN arrived and I try "memory try it" from the motherboard they make 3866 cl16-18-18-18-38 IF 1: 1 easy which was unthinkable with my previous 4x8 Crucial Max sticks.
I know I didn't do work but before this anything over 3733 was hard though they Crucial were already 4000 cl18

Does anyone have a setting that is stable @ 4000 IF 1: 1 and can post it for me to test?


----------



## Alyjen

qwrty said:


> Hello
> 
> @Veii
> 
> Do you know why L3 cache bandwidth is bad when using new SMU ?
> Did AMD do something in latest SMU to restricted bandwidth ?
> 
> With 5950x on older SMU I had 600/700 gbit/s , now between 500/600 gbit/s.


These measurements are wrong, they change depends on how your CPU is boosting, you'll get different results with all core OC vs PBO. For my 5800X they are 2/3 of what I should be getting (and on previous BIOS it was half) but it's enough to enable Fmax enhancer to get 100% score ( but Fmax suck in all other aspects). I'd say just ignore them and if you want to check performance use something different e.g. Geek Bench, is very sensitive to memory OC, IF instabilities etc. if you mess things up your score will drop.


----------



## Joeking78

bigblueshock said:


> I have a Gigabyte Aorus Master X570
> 3900x
> GeForce 1080 Ti
> Four sticks of 8GB G.Skill 3600 C15 B-Die
> 
> 
> Add me to the WHEA Error 18 club. Hopefully someone could give me advice on slight adjustment of memory timings.
> 
> I was (or so I thought) 100% stable. Ran 1usmus Ryzen DRAM Calculator Memtest for over 5 hours, no crashing in hours of gaming, or any other time. Haven't done a TM5 test or anything else. No problems since I put together my rig really, other than minor tweaks to DRAM timings. No CPU OC's, just strictly memory.
> 
> Due to the recent "crypto craze" I decided to fire up mining software just to play around with it. It is GPU Only mining, no GPU Overclock. I let it run for 2 hours, boom, reboot with WHEA Error 18. Rinse and repeat, every 2 hours. Very odd!
> 
> Thought it could be the Video Card, but I tried another nVidia card with same issue. Also have the latest drivers.
> 
> I find it hard to believe it's the cards.
> 
> Things I've tried (I've since switched back):
> 1) Raised ProcODT to 40+
> 2) Raised VDDG to 1.05
> 
> 
> I have not touched SOC, it's currently at 1.1 - Also below are my ZenTimings.
> 
> Any recommendations?
> 
> Thank you!
> 
> 
> 
> View attachment 2473734


Try ClkDrvStr at 60.

I have a dual rank gskill 2 x16gb kit 3200 c14 at 3733 c14 and 60 ClkDrvStr got my overclock stable. ProcOdt to 43.6 too


My timings below, still tweaking but waiting for a new board to arrive tomorrow


----------



## kratosatlante

[QUOTE = "Dreamic, publicación: 28715767, miembro: 558271"]
Maldita sea ... 4x8GB 4400C19 Vipers aquí y necesito 1.53v para 3733C14 (no puedo publicar 1900 en B550 Tomahawk), e incluso con un NF-A14 soplando directamente en la RAM, se sobrecalentará y producirá un error si estoy estresando la GPU Y CPU suficiente para calentar mi carcasa y mi habitación. Juegue un juego / punto de referencia exigente que obtenga 3080 y 5800x 100% y active TM5 justo después antes de que cualquier cosa se enfríe, errores.

Creo que tienes suerte 1.49v, ¿cuál es tu latencia?
Mis sticks ni siquiera tienen sensores de temperatura, así que no tengo ni idea de en qué están, pero ahora que lo estoy pensando, tal vez debería haber elegido 2x16GB para el espacio libre entre los DIMM para que no estén tan calientes. , más fácil para que el aire entre allí también. Quizás la diferencia más significativa entre 4x8GB y 2x16GB y ni siquiera lo pensé
[/CITAR]

Estoy seguro de que no son la víbora, uso esta configuración y uso más voltaje 1.63 y 1.65 vbios durante las semanas 3800/1900 cl 13, ahora 3800/1900 cl 14 trfc 221 1.59vbios










Fmax enable









4000/2000 cl16 está bien, pero algunos errores WHEA











Pd: i have ram cooler corsair airflow 2


----------



## DeletedMember558271

bonet69 said:


> View attachment 2473773
> 
> 
> You should be able to check ram temps in hwinfo i think, 4 sticks will be able to get a little bit less latency than 2 dual rank sticks and it will be easier to make gdm off with single rank sticks, thats where u get more performance than dual ranked, but of course 4 sticks will be hotter than 2 sticks sr or dr. If i increase cpu speed i get even lower latency but i found 4.6 ghz is the sweet spot for my cpu ( i dont care for 1-2 fps more of 4.7 ghz if its not 100% stable)
> 
> I know i could lower even more some subtimings and while it will achieve lower latency it will also give me lower fps in games, sooo this is the best i could do!
> 
> Regards


Patriot Vipers just don't have temp sensors unfortunately, would be cool to know if I had a bad stick that was just getting really hot or something, probably not the case though. I did get 52.7ns at 3733C14 1.53v but I can't stay at that, it's 100% TM5 stable but that doesn't stress my 3080 & 5800x at the same time which is what makes too much heat and errors.


kratosatlante said:


> I am sure they are not the viper, I use this configuration and use more voltage 1.63 and 1.65 vbios during the weeks 3800/1900 cl 13, now 3800/1900 cl 14 trfc 221 1.59vbios
> 
> Pd: i have ram cooler corsair airflow 2


Yea idk if I'm ever going to be getting under 53ns without 1.5v+ which is probably too hot, so far every sub 54ns 4x8GB on the Zen Overclocking Spreadsheet is 1.53v-1.56v.
I still have a bit a breathing room with what I'm at now that I could probably bump to 1900/3800 without changing timings and stay under 1.5v, wish a BIOS would unlock that, 1900 FCLK specifically is bugged and 1933+ WHEA errors so not really any choice but 1867...








This doesn't save 1.53v from a 3080's heat, this old pic still has a 1070 but it's Asus 3080 TUF now.
Can't really get the fan much more on the RAM than that.

Also I did try contact MSI about the 1900 FCLK no post issue on my B550 Tomahawk that I know is effecting people on other boards too and they said: 
"Thank you for reporting this issue, we will forward this to the BIOS software team." so maybe something actually happens?
More people are complaining about the 1933+ WHEA errors but I don't know if they can do anything about that, that one might be on AMD AGESA


----------



## KingEngineRevUp

bwana said:


> Thank you Dreamic and KingEngineRevup. I tightened things up and am now here at 1.5vDIMM
> View attachment 2473644
> 
> 
> I didnt know how to use that calculator. I might try to go lower on tRAS.
> Is 1.5v not recommended for daily?


G. skills runs their b-dies at 1.5V and their heatsinks on those rans are essentially the same, if not warmer due to RGB lighting (my sticks don't have RGB).

I don't see issues with running them at 1.5V if Trident Z b-die is running at those temperature.

From my experience, ram will start becoming unstable if it reaches 45C+ but that was on my 3900X. I had a fan blowing over my RAM then to keep them under and at 40C.

On my 5900X, my ram passed 8 hours of karhu and dram calculator stability test at 50C. So the IMC can also come into play. I don't have a ram fan bloei at them right now.

When it comes to stability, there are way too many variables. It's a case by case basis.


----------



## qwrty

halcyonon said:


> Are you using PBO[2]?


Yes with Curve Optimizer.



Alyjen said:


> erformance use something diff


I run exactly the same BIOS settings, but older perf better, even with multiple run.
That's why i'm wondering.


----------



## kratosatlante

[QUOTE = "Dreamic, publicación: 28716269, miembro: 558271"]
Los Patriot Vipers simplemente no tienen sensores de temperatura, desafortunadamente, sería genial saber si tengo un palo malo que se está calentando mucho o algo así, aunque probablemente no sea el caso. Obtuve 52.7ns a 3733C14 1.53v pero no puedo quedarme en eso, es 100% TM5 estable pero eso no estresa a mi 3080 y 5800x al mismo tiempo, que es lo que genera demasiado calor y errores.

Sí, no sé si alguna vez voy a tener menos de 53 ns sin 1.5v +, lo cual probablemente sea demasiado caliente, hasta ahora, cada sub 54ns 4x8GB en la hoja de cálculo Zen Overclocking es 1.53v-1.56v.
Todavía tengo un poco de espacio para respirar con lo que estoy ahora que probablemente podría pasar a 1900/3800 sin cambiar los tiempos y permanecer por debajo de 1.5v, desearía que un BIOS lo desbloqueara, 1900 FCLK específicamente tiene errores y 1933+ errores WHEA así que no hay otra opción que 1867 ... [ATTACH = full] 2473833 [/ ATTACH]
Esto no ahorra 1.53v del calor de un 3080, esta vieja foto todavía tiene un 1070, pero ahora es Asus 3080 TUF.
Realmente no se puede hacer que el ventilador tenga mucho más en la RAM que eso.

También intenté contactar a MSI sobre el 1900 FCLK sin problema de publicación en mi Tomahawk B550 que sé que también está afectando a las personas en otros tableros y dijeron:
"Gracias por informar de este problema, se lo enviaremos al equipo de software de BIOS". ¿Entonces tal vez algo realmente sucede?
Más personas se quejan de los errores WHEA de 1933+, pero no sé si pueden hacer algo al respecto, ese podría estar en AMD AGESA
[/CITAR]
Many users who achieve very low latencies use modified OS or do it in win safe mode, with all background processes paused or closed, use turvo evo to increase vsoc from windows until latency measurement in aida does not vary, too Pll v leave it between 1.80 to 1.85 check that by passing 1.85 I get lantecia penalty
Modo asegurar tener este









por lo segundo proceso avión casi cerrada 









No puedo bajar de 51,8

same here have whea errors if pas from 3800/1900 to 1967 or 2000


----------



## elvior2

Joeking78 said:


> Try ClkDrvStr at 60.
> 
> I have a dual rank gskill 2 x16gb kit 3200 c14 at 3733 c14 and 60 ClkDrvStr got my overclock stable. ProcOdt to 43.6 too
> 
> 
> My timings below, still tweaking but waiting for a new board to arrive tomorrow
> View attachment 2473817


Interesting I have the same kit as you, but the one without RGB and I'm still struggling a bit to make it fully stable at 3600. Of course it would be amazing if a can run one level higher at 3733.

Would you mind sharing your BIOS voltages info, cause maybe can be very useful for identifying the culprit.

These are my settings, that are 99% stable but some very rare errors occurs during long stress testing sessions (+ 6h). Temps are fine < 43c

In BIOS

SoC: 1.0875V (1.0750 under load)
cLDO_VDDP: 900mv
IOD: 1025mv
CCD: 1025mv
DRAM: 1.37v
LLC for CPU and NB: Mode 3


----------



## Joeking78

elvior2 said:


> Interesting I have the same kit as you, but the one without RGB and I'm still struggling a bit to make it fully stable at 3600. Of course it would be amazing if a can run one level higher at 3733.
> 
> Would you mind sharing your BIOS voltages info, cause maybe can be very useful for identifying the culprit.
> 
> These are my settings, that are 99% stable but some very rare errors occurs during long stress testing sessions (+ 6h). Temps are fine < 43c
> 
> In BIOS
> 
> SoC: 1.0875V (1.0750 under load)
> cLDO_VDDP: 900mv
> IOD: 1025mv
> CCD: 1025mv
> DRAM: 1.37v
> LLC for CPU and NB: Mode 3
> 
> View attachment 2473923


Hi,

Will check when I get home but my DRAM voltage is 1.5v, temps as yours are at 42c under stress test.

Try ClkDrvStr at 60 and ProcOdt at 43.6...helped get me stable at C14 3733


----------



## elvior2

With the following config I'm getting a couple of errors in TM5. Any suggestion?

Don't know what's the meaning of those errors.

Memtest in DRAM Calculator passed with 2000% coverage in each one (arround 16h running)

In BIOS

SoC: 1.1V (1.092 under load)
cLDO_VDDP: 905mv
IOD: 1050mv
CCD: 1025mv
DRAM: 1.37v
LLC for CPU and NB: Mode 2


----------



## craxton

Edit, currently passing iteration 7 N32 everything else has passed this far. No changes made to timings (timings I showed in past few days postings) I suppose once finished prime95 fft it is with avx2.
hey @Veii you said for y-crucher to do 1-7-0 enter after each number right?? in other words simply turning on all tests for stressing everything thru y-cruncher? pbo limits currently are 76-60-75


----------



## craxton

elvior2 said:


> With the following config I'm getting a couple of errors in TM5. Any suggestion?
> 
> Don't know what's the meaning of those errors.
> 
> Memtest in DRAM Calculator passed with 2000% coverage in each one (arround 16h running)
> 
> In BIOS
> 
> SoC: 1.1V (1.092 under load)
> cLDO_VDDP: 905mv
> IOD: 1050mv
> CCD: 1025mv
> DRAM: 1.37v
> LLC for CPU and NB: Mode 2




try 40-20-20-20 cadbus or leave as is and up proc odt and retest. are these errors happening after sometime in TM5? or right at the start? or have you payed any attention?
could also try 40-24-24-24 cadbus. normally a few errors can be solved by cadbus or proc increases. dont change both (proc and cadbus) just one or the other....


----------



## KingEngineRevUp

I hope someone can help me with this, about to call it quits and return the extra pair of RAM sticks I bought.

Runnings 5900X
Got 2X 8GB B-Die to run 3800 MHz CL16 fine, latency is around 54ns
Decided to buy a second separate kit, got all 4 to run together at 3800 MHz CL16
Was posting fine with older BIOs for ASUS C8H
*Updated BIOs, now when I boot up the RAM needs to go through a few training cycles, it's annoying*
I've applied a VDIMM of 1.50V and these timings here:









*I'm just sick and tired of having to wait for my PC to retrain itself, it shuts on and off like 5 times or more before it can boot up.* When it does, I was able to pass 8 hours of RAM test with Karhu and DRAM Calculator Memtest...

Perhaps it's not stable as it seems otherwise it would have no problem booting up with one try.

Last night, I decided to just pull the new sticks out and I'm debating about returning them. Specially since benchmarks I have done show that there is no benefit of going Single to Dual rank when your latency is so low.

Thoughts?
























]

Maybe it's not worth keeping the extra kit?


----------



## halcyonon

qwrty said:


> Yes with Curve Optimizer.


This is why your l3 cache numbers are low, it's almost certainly not accurate so don't worry about it.


----------



## halcyonon

KingEngineRevUp said:


> I hope someone can help me with this, about to call it quits and return the extra pair of RAM sticks I bought.
> 
> Runnings 5900X
> Got 2X 8GB B-Die to run 3800 MHz CL16 fine, latency is around 54ns
> Decided to buy a second separate kit, got all 4 to run together at 3800 MHz CL16
> Was posting fine with older BIOs for ASUS C8H
> *Updated BIOs, now when I boot up the RAM needs to go through a few training cycles, it's annoying*
> I've applied a VDIMM of 1.50V and these timings here:
> 
> 
> *I'm just sick and tired of having to wait for my PC to retrain itself, it shuts on and off like 5 times or more before it can boot up.* When it does, I was able to pass 8 hours of RAM test with Karhu and DRAM Calculator Memtest...
> 
> Perhaps it's not stable as it seems otherwise it would have no problem booting up with one try.
> 
> Last night, I decided to just pull the new sticks out and I'm debating about returning them. Specially since benchmarks I have done show that there is no benefit of going Single to Dual rank when your latency is so low.
> 
> Thoughts?
> 
> Maybe it's not worth keeping the extra kit?


A couple thoughts.. will you benefit from 16->32GB of RAM in any of your non-gaming workloads? If yes, how often do you really reboot your system? As long as it will consistently eventually boot properly, AND you can run a much longer stability test (I'd suggest 24+H of MTP, TM5, or Karhu) successfully while generating max heat in your case by simultaneously running something like FurMark on your GPU, then maybe don't worry about it.


----------



## domdtxdissar

halcyonon said:


> This is why your l3 cache numbers are low, it's almost certainly not accurate so don't worry about it.


L3 number also depend very much on EDC limit and boosting, but no need to worry about it as AIDA L3 numbers are meaningless..


----------



## craxton

halcyonon said:


> This is why your l3 cache numbers are low, it's almost certainly not accurate so don't worry about it.


L3 cache speeds will be low looking when allowing cpu to boost auto, if a static oc is set itll look way better when benchmarking. same timings, voltage etc, only one is static oc, vs auto oc...


----------



## Akex

I still have some timings to optimize but overall I'm satisfied for a 3200mhz kit. Before going to the suite I would have liked opinions. I tried to put the CAS on 13/12, I only succeeded once to post. No matter the tension, it's totally unstable. What value do you think improves my situation? I have thermal headroom on my 4x8 BDIE and I can afford to push hard vdimm. I spent 3x 1usmus v3 over 20 cycles and 2x Anta Extreme over 20 cycles, and 24h Membench in DRAM Calculator.



https://cdn.discordapp.com/attachments/632568966233063425/799103343410151446/unknown.png



My kit is overvolted, I didn't want to mess around with vdimm, I usually pay it last. I am at 1.65v currently but I know that at 1.54v I am stable too. Which leaves me a good margin


----------



## KingEngineRevUp

halcyonon said:


> A couple thoughts.. will you benefit from 16->32GB of RAM in any of your non-gaming workloads? If yes, how often do you really reboot your system? As long as it will consistently eventually boot properly, AND you can run a much longer stability test (I'd suggest 24+H of MTP, TM5, or Karhu) successfully while generating max heat in your case by simultaneously running something like FurMark on your GPU, then maybe don't worry about it.


You know what... I got the second kit because I was hoping "Dual Rank" would give me a performance enhancement. But discussing it with others, it seems like when you reach low latencies, Dual Rank vs. Single Rank doesn't matter anymore. Another bottleneck elsewhere is hit. 

I'm just going to return the b-die.


----------



## bwana

craxton said:


> L3 cache speeds will be low looking when allowing cpu to boost auto, if a static oc is set itll look way better when benchmarking. same timings, voltage etc, only one is static oc, vs auto oc...
> .
> .
> .


I have been struggling with this L3 hit from trying to OC the CPU. I have tried various configs with PBO but no matter what I do, the L3 speeds are bad unless I disable PBO. Are you saying that AIDA does not measure L3 cache speed properly or are you saying that L3 cache is expected to drop significantly when PBO is engaged? I have been sure to specify a 1:1 divider in the bios for FCLK and MCLK so I dont understand why this memory speed is affected by a cpu function.


----------



## Alyjen

bwana said:


> I have been struggling with this L3 hit from trying to OC the CPU. I have tried various configs with PBO but no matter what I do, the L3 speeds are bad unless I disable PBO. Are you saying that AIDA does not measure L3 cache speed properly or are you saying that L3 cache is expected to drop significantly when PBO is engaged? I have been sure to specify a 1:1 divider in the bios for FCLK and MCLK so I dont understand why this memory speed is affected by a cpu function.


Just enable Fmax enhancer if you want to see nice scores. It'll hurt your performance otherwise but it'll prove that everything is fine. Default/auto is disabled so you have to locate this option in BIOS and set to enabled.
I think, the reason behind it is how PBO reacts to this AIDA test and how cores are boosted. This has nothing to to with real life performance.


----------



## mc conor

What load line calibration settings do you guys use and why?

Does anyone know what auto is equivalent to?


----------



## Akex

Auto = Level 3 / Asus MB


----------



## craxton

mc conor said:


> What load line calibration settings do you guys use and why?
> 
> Does anyone know what auto is equivalent to?


im using LLC3 on msi for a little more than what i set since im setting 1.5 for vdimm thats to ensure its not drooping to avoid errors.. for cpu side i use flat depending on where my voltage is. but recently found info stating for cpu overclocking on ryzen if your not trying to degrade your cpu to fast vdroop is something you wanna see?? 



bwana said:


> I have been struggling with this L3 hit from trying to OC the CPU. I have tried various configs with PBO but no matter what I do, the L3 speeds are bad unless I disable PBO. Are you saying that AIDA does not measure L3 cache speed properly or are you saying that L3 cache is expected to drop significantly when PBO is engaged? I have been sure to specify a 1:1 divider in the bios for FCLK and MCLK so I dont understand why this memory speed is affected by a cpu function.


yes, but that depends on what bios revision you have. on patch C bios for b550 gaming edge board and x570 counter nothing i did would increase L3 speeds latency showed there was no issue but the bandwidth was bad always until latest beta bios release 1.1.9.0


----------



## Pictus

mc conor said:


> What load line calibration settings do you guys use and why?


I only use small LLC, I am afraid of the spikes...








Load-Line Calibration (LLC) - WikiChip


Load-Line Calibration (LLC) is a mechanism offered to overclockers designed to compensate for large voltage droops when a CPU or GPU is under increased load. The mechanism attempts to compensate for the sudden sagging in voltage by preemptively applying additional voltage. The LLC, which is part...




en.wikichip.org













VRM Load-Line Visualized - ElmorLabs


How does motherboard load-line settings really work and how does the voltage output change with it? Check these oscilloscope pictures to find out.




elmorlabs.com


----------



## blu3dragon

Akex said:


> Auto = Level 3 / Asus MB


Is there a way to look this up?

On my B550-F with a 5800x and latest bios auto appears to be equivalent to Level 1 or 2. Manually setting to level 3 I get less voltage drop. This is noticeable since it impacts stability for single core p95 with PBO. I actually need a higher (more positive) curve offset setting with auto, level 1 or 2 compared with level 3. For now I've settled on manually setting to level 3.


----------



## VPII

I'm really amazed at the amount of people using LLC. Look I know it is different with the mobo I have now, but I remember when I tested it on my CH7 on the probelt measurement points that when I left it on AUTO it was way better than any of the LLC settings. So now when I use my MSI Meg X570 Ace I also leave it on auto, yes there is a vcore drop of around 0.0025 or there about but it just works for me.


----------



## DeletedMember558271

So this guys 4x8GB result ****s on everyone elses, but barely a stress test only 6 mins and probably has WHEA errors but man I wish these FCLK's were WHEA error free for me.
51.2ns without exceeding 1.5v, worse/slower results with higher voltages on the spreadsheet. Maybe won the lottery since I need 1.53v for 3733C14 52.7ns, idk if my sticks could do this 51.2ns with 1.5v, which might still error too hot when the 3080 gets going.








Achieves this but doesn't know how to figure out DRAM Part Number on the spreadsheet and just put the Memory Chips twice...
ZenTimings they're 4400C19 Vipers it looks like, same as mine.
This Total Errors graph he has up is WHEA errors yes?








Zen RAM OC Leaderboards


ATTENTION Unfortunately, we can't have nice things. Because of vandalism by what looks to be salty Chinese users, this document has been placed under review by Google. I've decided to lock the sheet and weather the storm while the doc is under review and prevent any spread of malware that could...




docs.google.com


----------



## Sphex_

Dreamic said:


> So this guys 4x8GB result ****s on everyone elses, but barely a stress test only 6 mins and probably has WHEA errors but man I wish these FCLK's were WHEA error free for me.
> 51.2ns without exceeding 1.5v, worse/slower results with higher voltages on the spreadsheet. Maybe won the lottery since I need 1.53v for 3733C14 52.7ns, idk if my sticks could do this 51.2ns with 1.5v, which might still error too hot when the 3080 gets going.
> 
> 
> 
> 
> 
> 
> 
> 
> Achieves this but doesn't know how to figure out DRAM Part Number on the spreadsheet and just put the Memory Chips twice...
> ZenTimings they're 4400C19 Vipers it looks like, same as mine.
> This Total Errors graph he has up is WHEA errors yes?
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> ATTENTION Unfortunately, we can't have nice things. Because of vandalism by what looks to be salty Chinese users, this document has been placed under review by Google. I've decided to lock the sheet and weather the storm while the doc is under review and prevent any spread of malware that could...
> 
> 
> 
> 
> docs.google.com


Yeah, so he got 204 WHEA errors in a 6 minute TM5 run lol. I'm the maintainer of the sheet. 

Should we consider WHEA errors as unstable? The system can run, but I'm not entirely ready to call the persistence of WHEA errors stable. Unless other people here disagree. Then I'll leave the submission up.


----------



## DeletedMember558271

Sphex_ said:


> Yeah, so he got 204 WHEA errors in a 6 minute TM5 run lol. I'm the maintainer of the sheet.
> 
> Should we consider WHEA errors as unstable? The system can run, but I'm not entirely ready to call the persistence of WHEA errors stable. Unless other people here disagree. Then I'll leave the submission up.


I personally don't care or am impressed about anyones result that has WHEA errors, it's technically unstable whether it's the BIOS or whatever, I'm not interested in running or copying anything with WHEA errors and I wouldn't recommend it, apparently some people have corrupted their OS.
Problem for you is most of the results already have no indication of whether they have WHEA errors or not, and I think I remember people saying things like new Windows versions started reporting WHEA errors that were previously going unreported which would complicate things even more. Feel like you'd basically have to start the sheet over, though it's really only the results over 1900 FCLK I'm taking with a grain of salt if they say nothing about WHEA errors, I think they probably do unless they show otherwise. Think a couple on there even admitted in a note or whatever they have some but otherwise seems stable.
I don't really know what to suggest, but if there was a way to differientiate between results that have WHEA errors or not I can tell you which ones I care a lot more about


----------



## Sphex_

Dreamic said:


> I personally don't care or am impressed about anyones result that has WHEA errors, it's technically unstable whether it's the BIOS or whatever, I'm not interested in running or copying anything with WHEA errors and I wouldn't recommend it, apparently some people have corrupted their OS.
> Problem for you is most of the results already have no indication of whether they have WHEA errors or not, and I think I remember people saying things like new Windows versions started reporting WHEA errors that were previously going unreported which would complicate things even more. Feel like you'd basically have to start the sheet over, though it's really only the results over 1900 FCLK I'm taking with a grain of salt if they say nothing about WHEA errors, I think they probably do unless they show otherwise. Think a couple on there even admitted in a note or whatever they have some but otherwise seems stable.
> I don't really know what to suggest, but if there was a way to differientiate between results that have WHEA errors or not I can tell you which ones I care a lot more about


Yeah, I'm leaning towards calling anything with WHEA errors unstable. You do bring up a good point about previous submissions most likely having them as well, but as you pointed out, there's no way to tell. I did not foresee, when creating the sheet, errors other than memory errors being in the spotlight, much like Zen 2 (I remember WHEA errors popping up in Zen 2 but it seemed few and far between and sometimes indicated a defective CPU. That isn't the case anymore lol.)

I can try editing the FAQ and top banner and mention an HWInfo screenshot being required for proof of stability, some people might listen, but I also think a lot of people like submitting unstable results just to flex their e-peen.


----------



## DeletedMember558271

Sphex_ said:


> I also think a lot of people like submitting unstable results just to flex their e-peen.


This is what I think of all high vDIMM results now, pushed to the edge of temp stability. TM5 only stresses your RAM while everything else is cool and idle, my 3080 when stressed long enough to heat everything up will push stable results over the edge and vDIMM will have to be lowered, my whole room heats up if I stress 3080 for hours like playing a demanding game uncapped FPS.
This is with an NF-A14 blowing directly on the RAM, mind you it is 4x8GB and 2x16GB would maybe dissipate heat better, gaps for air to get in between easier.
But unless someone has a **** GPU that doesn't even create much heat or they have it on water so it's not exhausting right on to the RAM, I don't trust it. I don't know if having the RAM on water would even help if you still had a 3080 blowing on it.
These edge of stability tests aren't full system load stable, just RAM load stable. Throw a lot more heat at it and it falls apart.
Probably running fans at 100% too for the test and if they have one blowing on it, which nobody actually does 24/7 wanting to listen to that unless your PC is in another room.
Probably have to lower settings if they want to use the rest of their PC components simultaneously like you need for playing a game, maybe some don't even think to run TM5 after heating everything up to see if its still stable, erroring away the entire time they're playing a game. Gotta run TM5 after gaming uncapped FPS for hours, immediately after closing before things cool down. That's the real temp stability test


----------



## elvior2

craxton said:


> try 40-20-20-20 cadbus or leave as is and up proc odt and retest. are these errors happening after sometime in TM5? or right at the start? or have you payed any attention?
> could also try 40-24-24-24 cadbus. normally a few errors can be solved by cadbus or proc increases. dont change both (proc and cadbus) just one or the other....


Yes, I payed attention and the few errors are always happening after "long" periods of testing (> 3h in TM5, > 8h in DRamCalculator Memtest...). I don't think it's related to temperatures as my ram modules were < 44c but not sure.

Given your suggestion I've mainly focused on proc odt (now 43.6), leaving cadbus on auto (24-24-24-24) and also doing small adjustments in the voltages.

For some reason that I don't fully understand this config with lower voltages is passing all the stress test so far.

These is the new config in BIOS

SoC: 1.0625V (1.050 under load)
cLDO_VDDP: 900mv
IOD: 1000mv
CCD: 1000mv
DRAM: 1.36v
LLC for CPU and NB: Mode 3
Also I've been able to reduce tRFC and some other little adjustments











Next steps? Lower some timings? 3733? Would really appreciate any suggestions.


----------



## Xiph

My whole pc setup is 1,5 month old and had tCL14 3733Mhz setup which was fully tested many times with long TM5 runs and confirmed as stable. Used those ram settings 4 weeks without errors.
Then I focused to curve optimizing and cpu overclocking for a one week. After that I once again run same ram test in TM5 and it is giving easily single errors in 15 minutes. Tested with older bioses and multiple settings and fact is that this ram can't do no more tCL14 with 1.50V. With 1.52V it's stable.

I know I was near limit at the beginning with 1.50V 3733Mhz as 3800Mhz was not possible with 1.54V.
I did only very short test with higher voltages than 1.50V.
Is it possible that b-die 3200C14-16GTZN degredation can happen in one month with 1.50V?


----------



## Spectre73

Xiph said:


> My whole pc setup is 1,5 month old and had tCL14 3733Mhz setup which was fully tested many times with long TM5 runs and confirmed as stable. Used those ram settings 4 weeks without errors.
> Then I focused to curve optimizing and cpu overclocking for a one week. After that I once again run same ram test in TM5 and it is giving easily single errors in 15 minutes. Tested with older bioses and multiple settings and fact is that this ram can't do no more tCL14 with 1.50V. With 1.52V it's stable.
> 
> I know I was near limit at the beginning with 1.50V 3733Mhz as 3800Mhz was not possible with 1.54V.
> I did only very short test with higher voltages than 1.50V.
> Is it possible that b-die 3200C14-16GTZN degredation can happen in one month with 1.50V?


Everyone says 1,50v is fine for b-die. I do not believe it. I know there are b-die kits out there that are specified for 1.5v xmp operation to run at advertised speeds but these kits are especially binned and tested for that voltage. IMHO (and I have no experience with degradation) it could well be that 1.5v is just too much for your sticks and they suffer from degradation or general instability now, even though they ran fine a few weeks ago.
This is why I am cautious with all the claims of "1.5v is fine". I am very hesitant to go over 1,45v. Not very helpful, I know, but who can say what happened to your sticks?


----------



## KedarWolf

Dreamic said:


> This is what I think of all high vDIMM results now, pushed to the edge of temp stability. TM5 only stresses your RAM while everything else is cool and idle, my 3080 when stressed long enough to heat everything up will push stable results over the edge and vDIMM will have to be lowered, my whole room heats up if I stress 3080 for hours like playing a demanding game uncapped FPS.
> This is with an NF-A14 blowing directly on the RAM, mind you it is 4x8GB and 2x16GB would maybe dissipate heat better, gaps for air to get in between easier.
> But unless someone has a **** GPU that doesn't even create much heat or they have it on water so it's not exhausting right on to the RAM, I don't trust it. I don't know if having the RAM on water would even help if you still had a 3080 blowing on it.
> These edge of stability tests aren't full system load stable, just RAM load stable. Throw a lot more heat at it and it falls apart.
> Probably running fans at 100% too for the test and if they have one blowing on it, which nobody actually does 24/7 wanting to listen to that unless your PC is in another room.
> Probably have to lower settings if they want to use the rest of their PC components simultaneously like you need for playing a game, maybe some don't even think to run TM5 after heating everything up to see if its still stable, erroring away the entire time they're playing a game. Gotta run TM5 after gaming uncapped FPS for hours, immediately after closing before things cool down. That's the real temp stability test


My b-die G.Skill is really sensitive to heat. If I run my RAM fans at 6800 RPM, which is kind of loud, can just hear it over my headset, my RAM temps top out at 31C and Ollie TM5 running 6 hours passes all tests.

If I run my RAM fans at 3000 RPM which is silent, my RAM tops at 41C, and Ollie RAM test running 6 hours spewed out 31 errors.









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You can get the same fans cheaper here, but shipping can take a month or more from China to the USA/Canada.









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My RAM fans I put in this frame.









14.43US $ 23% OFF|ALSEYE RAM Cooler PC Fan DDR Memory Cooler with Dual 60mm Fan PWM 1500 4000RPM Cooler for DDR2/3/4|memory cooler|ram coolerram memory cooler - AliExpress


Smarter Shopping, Better Living! Aliexpress.com




www.aliexpress.com


----------



## Alyjen

Xiph said:


> My whole pc setup is 1,5 month old and had tCL14 3733Mhz setup which was fully tested many times with long TM5 runs and confirmed as stable. Used those ram settings 4 weeks without errors.
> Then I focused to curve optimizing and cpu overclocking for a one week. After that I once again run same ram test in TM5 and it is giving easily single errors in 15 minutes. Tested with older bioses and multiple settings and fact is that this ram can't do no more tCL14 with 1.50V. With 1.52V it's stable.
> 
> I know I was near limit at the beginning with 1.50V 3733Mhz as 3800Mhz was not possible with 1.54V.
> I did only very short test with higher voltages than 1.50V.
> Is it possible that b-die 3200C14-16GTZN degredation can happen in one month with 1.50V?


I think there's more to it and I find it hard to believe it's caused by degradation. BIOS quality, memory training, how your mobo reacts to change of even seemingly unrelated setting. I saw weird things going on with current BIOSes and Zen 3 chips. e.g. once I disabled serial port (which I don't use/have) and after reboot my PC saw no pci-e cards  eventually I did clear CMOS, applied all settings from scratch and everything was fine. 

Friend of mine had case when he thought his memory OC was stable, but it acctualy never was and it was just memory training of his MSI board playing with him. Also if you check TM5 after fresh boot it'll be a little different to what you'll get after lets say 1h of OCCT or other stress test that will heat up your CPU & memory controller a lot.


----------



## Akex

Akex said:


> I still have some timings to optimize but overall I'm satisfied for a 3200mhz kit. Before going to the suite I would have liked opinions. I tried to put the CAS on 13/12, I only succeeded once to post. No matter the tension, it's totally unstable. What value do you think improves my situation? I have thermal headroom on my 4x8 BDIE and I can afford to push hard vdimm. I spent 3x 1usmus v3 over 20 cycles and 2x Anta Extreme over 20 cycles, and 24h Membench in DRAM Calculator.
> 
> 
> 
> https://cdn.discordapp.com/attachments/632568966233063425/799103343410151446/unknown.png
> 
> 
> 
> My kit is overvolted, I didn't want to mess around with vdimm, I usually pay it last. I am at 1.65v currently but I know that at 1.54v I am stable too. Which leaves me a good margin


Up and update > https://cdn.discordapp.com/attachments/587387498569793575/799576853747597322/unknown.png

Neither of you have an idea to hit the CL on 13 at least? I have a doubt about tCWL, I think it is he who is worrying me.


----------



## kratosatlante

Akex said:


> Up and update > https://cdn.discordapp.com/attachments/587387498569793575/799576853747597322/unknown.png
> 
> Neither of you have an idea to hit the CL on 13 at least? I have a doubt about tCWL, I think it is he who is worrying me.


need 1.6v +


http://imgur.com/m9wi5mL

with 5600x its same, at 3800cl14 tight dont need more,same performance at cl13























cl14 very tight work well, with 5900x or 5950x may be gain more performance at cl13, but for 5600x no


----------



## Akex

I tried until 1.8v .... I already have very low timings. It's not a voltage problem.
Look my zentimings Zen-Timings-Screenshot and my bench cachemem
I need to try to figure out what's stuck for CL13 - CL12


----------



## kratosatlante

Akex said:


> I tried until 1.8v .... I already have very low timings. It's not a voltage problem.
> Look my zentimings Zen-Timings-Screenshot and my bench cachemem
> I need to try to figure out what's stuck for CL13 - CL12


first find your best stick and worst, put best (need lower voltaje) at a1, closed to cpu and worst to b2

and try trfc be a multile of 6 or more, for me dont work 6 , work 6.5 trc 34 x 6.5 at least, try lower your trc 
for your actual config try trfc 273 
and then try
trwr 9 or 10
twrrd 4
try proodt 40 or 43
rtnm 7
rttwr of
rtpark 5


----------



## Akex

Thansk for the advice, however I have four sticks.


----------



## kratosatlante

[QUOTE = "Akex, publicación: 28718485, miembro: 638354"]
Thansk por el consejo, sin embargo tengo cuatro palos.
[/CITAR]
same, best a1, second best a2, third b1, four b2


----------



## fairbanksBR

I am having a weird time with my ram stability.
My rig is this:
ryzen 3600 ("golden sample" according to clock tuner)
2x8gb ripjaws V 3000 cl 15 (Hynix CJR)
asus b350m-a prime
EVGA 600W 80+ Bronze power supply

So, I have my CPU OCed to 4.275ghz at 1.175v and I ram prime95 blend test for a night without errors, so I assume it is quite stable (got these values on clock tuner)
My ram without XMP runs at 2133. With it I run it at 3066 (changing the ram speed and with everything else on XMP - no timings tunning) and this I'm pretty sure is quite stable as I ran it for over 3 years with my ryzen 1600 without any errors or windows, prime95, gaming or anything like that (got the 3600 about 20 days ago). But I've never ran a memtest86 on the ryzen 1600.

So, I got to trying a proper OC on my ram. And I'm getting some really weird and inconsistent results. At first I got it to work at 3200 on 1.4v ram voltage and 16-17-16-17-35 with everything else on auto. It was stable for a few days (4 passes on memtest86 and no errors) and then, suddenly it started throwing errors always on test 7 on pass 2. So I got it back to 3066 and it worked ok. I assumed 3200 wasn't stable. So after a few days AGAIN the same thing, but now at 3066 15-16-16-16-35 (xmp timings for 3000). I did tweak a bit on other timings on these tries, and it was stable with some good ones, but then, even setting everything to auto, I still got errors. I tried tweaking on cadbus (tried 24-30-24-24, 24-20-24-24, 40-24-20-24 and pretty much all combinations dram calculator throwed at me), setting the voltages for ram, soc, cldo. tried the rtt stuff (all as grouped on dram calculator. and setting it back to auto before chaging anything else once I got an error).
So I went all out and tried setting the ram to default 2133 and everything auto and... STILL errors! And one thing I noted is: the error ALWAYS involve CPU 6, so always the same thread.
Without much more options, I tried to change ram slots and went in the BIOS and set everything to default (including CPU OC, MOBO leds config and all) and ram memtest86 like that and... it passed.
So, now I suspect my CPU OC is generating ram instability?

But the thing is: I got as far as 1.15v for SOC, tried all other voltages and had no effect. And the cpu clock I set seems pretty low and achievable for a 3600 golden sample. So my question is: could the problem be my CPU CORE voltage? would getting it up a little maybe help stability? I think it so weird that it can run fine for 4 or 5 days and then go into that state of ALWAYS throwing errors on test 7 pass 2. It's inconsistent, I'd expect about the same proportion of errors in a given period. Not sure what else I can do... any thoughts?


----------



## Akex

memtest86 is useless, go TM5 1usmus_v3 and anta777 extreme.


----------



## fairbanksBR

Akex said:


> memtest86 is useless, go TM5 1usmus_v3 and anta777 extreme.


Why is that? I'd love to know if there is some software problem with memtest86 running on ryzen 3000, this would put my mind at ease haha. Do you have any links where I can learn more about that?


----------



## Akex

TestMem support page - TestMem V


Hardware testing. TestMem III



testmem.tz.ru





It's not that it doesn't work, it's that it is more suitable.


----------



## fairbanksBR

Akex said:


> TestMem support page - TestMem V
> 
> 
> Hardware testing. TestMem III
> 
> 
> 
> testmem.tz.ru
> 
> 
> 
> 
> 
> It's not that it doesn't work, it's that it is more suitable.


hmmm, is this russian on the link? I don't speak russian ><
I get it, did a little googling and it seems some people get stability on memtest86 and not on windows. But in my case, seeing as memtest86 is throwing errors it doesn't seem to apply.
I'll give a try to these tests when I get home and see what happens. But even if it passes flawlessly, that memtest86 will keep bugging me haha I don't think I'll be able to let it go hahaha


----------



## Yviena

Is it worth updating to 1.1.9.0 AGESA for the possibility for more stable IF, i seem to get 300-350 less points in CB R23 due to it boosting 50-65mhz less though from 4.25-4,275 to mostly 4.25-4.230


----------



## Akex

fairbanksBR said:


> hmmm, is this russian on the link? I don't speak russian ><
> I get it, did a little googling and it seems some people get stability on memtest86 and not on windows. But in my case, seeing as memtest86 is throwing errors it doesn't seem to apply.
> I'll give a try to these tests when I get home and see what happens. But even if it passes flawlessly, that memtest86 will keep bugging me haha I don't think I'll be able to let it go hahaha


google trad ^^


----------



## sdimmu

Yviena said:


> Is it worth updating to 1.1.9.0 AGESA for the possibility for more stable IF, i seem to get 300-350 less points in CB R23 due to it boosting 50-65mhz less though from 4.25-4,275 to mostly 4.25-4.230


AGESA V2 PI 1.2.0.0 is available now for Asus boards but I didnt try yet, with 1.1.9.0 I´m WHEA free at 3800mhz


----------



## Alyjen

sdimmu said:


> AGESA V2 PI 1.2.0.0 is available now for Asus boards but I didnt try yet, with 1.1.9.0 I´m WHEA free at 3800mhz


yea I don't think I'll move to 1.2.0.0. unless I see version without big red BETA warning, currently at 3733 tight timings


----------



## kratosatlante

sdimmu said:


> AGESA V2 PI 1.2.0.0 is available now for Asus boards but I didnt try yet, with 1.1.9.0 I´m WHEA free at 3800mhz


sin errores whea 3800/1900 pero con errores a flck 2000, y voltaje elevado para vddp en auto 1.047


----------



## sdimmu

Alyjen said:


> yea I don't think I'll move to 1.2.0.0. unless I see version without big red BETA warning, currently at 3733 tight timings


3733mhz works perfect for 24/7, almost the same performance than 3800mhz



kratosatlante said:


> sin errores whea 3800/1900 pero con errores a flck 2000, y voltaje elevado para vddp en auto 1.047


Im using 

VSOC = 1.1v
VDDP = 0.900V
VDDG IOD = 1.05V
VDDG CCD = 0.950V


----------



## kratosatlante

sdimmu said:


> 3733mhz works perfect for 24/7, almost the same performance than 3800mhz
> 
> 
> 
> Im using
> 
> VSOC = 1.1v
> VDDP = 0.900V
> VDDG IOD = 1.05V
> VDDG CCD = 0.950V


----------



## Pictus

fairbanksBR said:


> hmmm, is this russian on the link? I don't speak russian ><
> I get it, did a little googling and it seems some people get stability on memtest86 and not on windows. But in my case, seeing as memtest86 is throwing errors it doesn't seem to apply.
> I'll give a try to these tests when I get home and see what happens. But even if it passes flawlessly, that memtest86 will keep bugging me haha I don't think I'll be able to let it go hahaha


Make sure to use the proper slots









Microsoft Chromium or Google Chrome does an excellent job of translating foreign languages.

Not all software is the same, memtest86 = "água com açúcar"
TM5 is way more demanding, maybe your RAM is bad, send it back and get (probably Micron E-die chips)








Memoria Crucial Ballistix 16GB (2x8) DDR4 3200Mhz Preta, BL2K8G32C16U4B


Memoria Crucial Ballistix 16GB (2x8) DDR4 3200Mhz Preta, BL2K8G32C16U4B, Tipo de memória DDR4, Capacidade 16GB (2 x 8GB), Frequência 3200 MHz, Pichau info




www.pichau.com.br





Does your case has a good airflow?
Here I keep the case FANs blowing air at the RAM sticks and before doing any tests, I set the speed of the FANs to 90%.


----------



## Pictus

Alyjen said:


> yea I don't think I'll move to 1.2.0.0. unless I see version without big red BETA warning, currently at 3733 tight timings


Hehehe
I tested today and it is OK, but not tested higher than 3733MHz


----------



## halcyonon

If I decouple FCLK from my memory clock, and leave my memory clock at say 3600, but slowly raise my FCLK, will that tell me what my IMC is capable of if I had RAM that was also capable of those speeds?


----------



## devoker

I can do 3800 Mhz 1:1 on my system (asrock b450 itx and ryzen 3600) but something is wrong with audio. No whea errors but there is some crackling noises coming during gaming. Spc voltage was 1.1 and tried lowering it to 1.05 and 1.09 but neither solved. Should I increase it more?


----------



## Alyjen

@halcyonon that's one way of checking how farm you can push your FCLK, esspecialy if you are unsure if you ram can go as high, if you have good RAM then I'd rather set ram and IF to 1:1 but very loose timings
@devoker crackling sound issues is one of the most obvious sign of instability.use Zen Timings to check your voltages and then you can think about rising voltages, vsoc & vddg iod being usual suspects, there's a lot of information about how to set them in this thread and also here AMD max overclocking voltage


----------



## CrashMclarson

Does this look good? Any suggestions on tightening these timings up? Thanks


----------



## sechsterangriff

CrashMclarson said:


> Does this look good? Any suggestions on tightening these timings up? Thanks
> 
> View attachment 2474591


I always find it suspicious when people show ZenTimings screenshots omitting voltage values. The only time that happened to me I was having a bunch of WHEA errors in the background.


----------



## MaxT

Hello everyone,
I have a few questions I was not able to find good infromaton on, so looking for some help:

1) Can someone please tell me whether tRCDRD and tRP can be lower than tCL? I am running b-die 2x16GB (dual rank sticks) at 3733 14-13-13-13-27-40 (GDM enabled 1T) and it POSTs just fine and seems to be TM5 Anta777 Extreme1 stable. Does it make sense to keep it like this or should I switch it to 14-14-14-14-28-42?

2) Also, my board seems to be able to do tRAS without the +2 buffer. Should I keep it that way?

3) Does lowering tRCDWR below tRCDRD actually have any notable performance impact (on writes)? I've seen people get this as low as 8.

4) Gear Down Mode doesn't affect all odd timings, but only some, correct? I would love to run pure 1T, but I couldn't get my system to POST, even at 3200.

Thoughts? @Veii ?

Thank you.


----------



## CrashMclarson

sechsterangriff said:


> I always find it suspicious when people show ZenTimings screenshots omitting voltage values. The only time that happened to me I was having a bunch of WHEA errors in the background.


Are you talking about the 3 that are grayed out? They have always been that way for me.


----------



## sechsterangriff

CrashMclarson said:


> Are you talking about the 3 that are grayed out? They have always been that way for me.


Yeap, it should look something like this.










The only time those were not displaying for me was when I was having WHEA errors on the background. The system seemed stable but once I opened the event viewer "oh boy.... " lol

But I wouldn't be surprised if it's just the case that the program can't read those of your motherboard. Still I would advise your to check for errors just in case you haven't yet.


----------



## devoker

Alyjen said:


> @halcyonon that's one way of checking how farm you can push your FCLK, esspecialy if you are unsure if you ram can go as high, if you have good RAM then I'd rather set ram and IF to 1:1 but very loose timings
> @devoker crackling sound issues is one of the most obvious sign of instability.use Zen Timings to check your voltages and then you can think about rising voltages, vsoc & vddg iod being usual suspects, there's a lot of information about how to set them in this thread and also here AMD max overclocking voltage


I also read that high soc or vddp vddg voltage may cause audio issues. I tested eith tm5 and prime95 various tests and I got no whea errors.


----------



## Nizzen

Tested new bios on Dark Hero. 3800/1900 was no chance too boot. 3866/1933 is booting up like nothing.

Cpu= Auto
C14-14-14-28- trfc 280
Rest is Auto










Now I can start tweaking the memory.

Under 60GB/s read is pretty bad if you have played with 10900k and apex 😅


----------



## DeletedMember558271

Nizzen said:


> Tested new bios on Dark Hero. 3800/1900 was no chance too boot. 3866/1933 is booting up like nothing.
> 
> Cpu= Auto
> C14-14-14-28- trfc 280
> Rest is Auto
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Now I can start tweaking the memory.
> 
> Under 60GB/s read is pretty bad if you have played with 10900k and apex 😅


You probably have WHEA errors at 1933.
This 1900 specific bug is so stupid and it's not specific to one brand or motherboard I guess, I don't understand.
Just has to be the highest FCLK that doesn't have WHEA errors probably that doesn't post... missing out on performance.
I want to know if anyone with this issue has got it to post


----------



## CrashMclarson

sechsterangriff said:


> Yeap, it should look something like this.
> 
> View attachment 2474772
> 
> 
> The only time those were not displaying for me was when I was having WHEA errors on the background. The system seemed stable but once I opened the event viewer "oh boy.... " lol
> 
> But I wouldn't be surprised if it's just the case that the program can't read those of your motherboard. Still I would advise your to check for errors just in case you haven't yet.


0 errors, so must be my board. Thanks


----------



## Nizzen

Dreamic said:


> You probably have WHEA errors at 1933.
> This 1900 specific bug is so stupid and it's not specific to one brand or motherboard I guess, I don't understand.
> Just has to be the highest FCLK that doesn't have WHEA errors probably that doesn't post... missing out on performance.
> I want to know if anyone with this issue has got it to post


Will check for WHEA errors with hwinfo in the background. 

This is AMD after all LOL


----------



## Alyjen

CrashMclarson said:


> 0 errors, so must be my board. Thanks


it is the board, in previous version of ZenTimings some of the voltages were not presented at all, now they are all listed but for many motherboards greyed out.


----------



## Karagra

Started this last night to go to 2000% but I woke up before it hit that mark haha.... What would you guys recommend changing? Sitting at Dram 1.4v, VDDP .950, CCD 1.050, IOD 1.050 (if the thing about those 3 not showing because of instability I would guess I just need to slightly up the dram voltage.) I am running the Steel Viper 4400mhzcl19 ram *PVS416G440C9K*


----------



## kratosatlante

Karagra said:


> Started this last night to go to 2000% but I woke up before it hit that mark haha.... What would you guys recommend changing? Sitting at Dram 1.4v, VDDP .950, CCD 1.050, IOD 1.050 (if the thing about those 3 not showing because of instability I would guess I just need to slightly up the dram voltage.) I am running the Steel Viper 4400mhzcl19 ram *PVS416G440C9K*
> 
> View attachment 2474980


with 3600 and 2 kit same ram need this


http://imgur.com/Vv7FIZy

 vddg io not show, but i set same 0.977 or + 0.50 from vddg ccd depend from bios version witch work
viper 4400 dont like T1 gdm off, try 1t gdm on or t2 gmd off, tRDWR and tWRRD to low no work well with high flck, try 8-3 or 9-3 ,for 3800/1900 need 10-3 for four sticks


----------



## Karagra

1.5v for the Dram @ 3800mhz?


----------



## kratosatlante

Karagra said:


> 1.5v for the Dram @ 3800mhz?


3800/1900 cl 14 trfc 245 only need 1.45 v very good chip, in general need 1.5 or more, 1.55v its safe for 24/7


----------



## Gaav

I need input on AGESA 1.2.0.0 vs 1.1.9.0

With AGESA 1.2.0.0, no WHEA errors with this settings:
VSOC 1.15V
VDDP: auto
VDDG: auto
VDIMM: 1.47V
[email protected], aida64, R20, Games (only whea errors in prime95 blender)

If i manualy set vddp and vddg to the exact same settings i get whea just by launching windows WUT?

2nd part:
With AGESA 1.1.9.0 i had higher READ, COPY and L3 Cache by alot as you can see in screenshots below with almost the same settings and i was running it for like 10days without any game crashing and 0 whea errors.

PS.
1. FCLK1933 is not stable with this settings IDK?
2. FCLK2033 is stable with this settings
3. FCLK2066 whea errors in window does not crash (performance degradation)
4. FCLK2100 sound errors, windows crashes after 2-3min.
5. AGESA 1.1.9.0 maximum windows FCLK was 2066
5. Should i return to 1.1.9.0?
6. Should i bother with further sub timings ?


AGESA 1.2.0.0









AGESA 1.1.9.0 (asus pulled this bios after 24h coz of broken usb/M2)


----------



## Gaav

Also there is, a hidden limit for UCLK even if you set DIV1 MCLK=UCLK it does not work...
I did MCLK: 2300 mhz FCLK: 2000 mhz but uclk was at 1150 mhz...
[email protected] 4600mhz/cl19 resulted in 62ns latency not bad ?
If i could set MCLK=UCLK 1:1 it would prolly drop to 57ns w/o FCLK 1:1:1
Wonder what, a 2000fclk and mclk=uclk 5200mhz.


----------



## mc conor

Does anyone with fast RAM have any benchmarks in a game that likes fast memory with zen3? I am interested to see the real world performance benefit between the usual 3600c16/3200c14 and the very high 3800c14+


----------



## kratosatlante

mc conor said:


> Does anyone with fast RAM have any benchmarks in a game that likes fast memory with zen3? I am interested to see the real world performance benefit between the usual 3600c16/3200c14 and the very high 3800c14+


short answer, only benefit with high end gpu, search reviews from hardrware unboxed,


----------



## Gaav

mc conor said:


> Does anyone with fast RAM have any benchmarks in a game that likes fast memory with zen3? I am interested to see the real world performance benefit between the usual 3600c16/3200c14 and the very high 3800c14+


Or high fps with medium quality.

3600x (4.4ghz 3733cl15) overwatch 240-360fps, horizon zero dawn 78fps
5600x (4.7ghz 4000cl16) overwatch 399-400fps , horizon zero dawn 84 fps


----------



## halcyonon

Gaav said:


> Or high fps with medium quality.


And low resolution.


----------



## Manuru

Hello guys! I've recently swapped 3600 CL18 kit with 3800 CL14 kit and I don't see any latency improvements.
My setup:

5900x
MSI B550 Gaming Edge
current ram: 2x16 dual rank 3800Mhz CL14 G.Skill F4-3800C14D-32GTZN
previous ram: 2x16 single rank 3600Mhz CL18 Kingston.
G.Skill has an even worse latency result.
I tried fast timings from Ryzen Dram Calculator without touching the voltages and anything else, but it gave me ~5 ns improvement: from 67 down to 62, still bad.
DRAM voltage is 1.5V. What should I do next? Try to tighten timings further?
Also I'll definitely run memtest on G.Skill, maybe something wrong with the kit itself.


----------



## BluePaint

@Manuru
RAM is fine. It's all in the subtimings. Post your Zentimings screen so that we can have a look.

Btw, if u don't chase the last 1 percentage, it's usually enough to get the cheapest B-die RAM u can find and with some more voltage and tuning it will perform very very close to the more expensive bins, especially on Ryzen because u can't clock as high as on Intel. I have G-Skill 3600CL16 DR 16GB RAM and I use it 24h with 3800CL14 tRFC 252 with 53ns AIDA latency. It also worked @ 4066CL16 with my 5800X. Both on 1.5v. 

As u experience yourself, for optimal performance u have to finetune anyway. 3800CL14 with loose subtimings will perform worse than hand optimized 3600CL16. High frequency and tight main timings are primarily for selling the kits at a higher price. Sub-timings are kept loose for stability and best compatibility since they don't want uninformed people to return the RAM when the XMP setting fails.


----------



## Dannyz

Hello, 

I recently upgraded my main rig from a 3900X to a 5900X. Been playing around with getting my RAM OC stable but I feel like I'm making no progress so I could use some advice here.

Here are my specs 
CPU: Ryzen 9 5900X
CPU cooler: NH-D15
RAM: G Skill Trident Z 32GB (4x8GB) 3600MHz CL15 (two of these kits F4-3600C15D-16GTZ)
Motherboard: Gigabyte X570 Aorus Master Rev 1.0 (using F32 bios Agesa 1.1.0.0D)
SSD: Samsung 970 Evo Plus 1TB
GPU: RTX 2080
PSU: EVGA 750G2

At first I tried just the XMP and that works successfully but performance wasn't where I would have liked it to be and latency was quite high around 60ns due to really loose auto timings. 
Then I tried manual tight timings at 3600MHz and that works as well but I feel like I can do better. 
Tried going balls to the wall with 3800MHz 14-14-14-28 and it wasn't successful. After playing around with it some more no matter what I did, 3800MHz at CL14 just simply wont boot for me. 
3733MHz with those timings does boot and I can get into windows but errors out a couple mins into Karhu. 
I said screw it, turn everything back to auto except mem frequency and left it at auto and just wanted to see what the mobo would try. It set the primary timings at 16-15-15-35 which isn't terrible but the subtimings weren't great and latency was back at around 58-60Ns 

I then just tried lowering my TRC and TRFC and ended up with this








I feel like I can take this somewhere but its not stable. PC restarts 5-15mins into Karhu ram test. 
I tried upping Dram voltage to 1.5V wasn't stable 
Tried VDDG voltages at 1050mV not stable 

You guys got any suggestions?


----------



## mismatchedyes

Would anyone please give me some advice?

I was offered a very good deal for 128GB kit, 4x32GB 3600 C18.

At first I installed the kit and was not able to get over 3200 Mhz. I read online that it can be of a benefit to check the sticks individually and fit into the A2/B2 the worst performing sticks and A1/B1 the better sticks. 

I have done this and now the system will boot XMP and seems stable.










I have made some very slight adjustments to sub timings which has reduced latency by approx 5ms and improved read by around 4GB/S but I was hoping with the right settings I could achieve better performance.

I have no idea what to try with chipset/IMC voltages or DrvStr for this memory. Would anyone have any ideas? The only thing I have done to start is set SOC to 1.15v and CDDG/CLDO to 0.9v. I have not made any other adjustments yet.

I am sure the limit is the IMC as the worst performing stick was able to run 3866mhz on its own with the same subtimings.

If I am able to find settings that make things easier for the IMC I am hoping I can either tighten the timings a little or increase the clock speed.

It is very appealing to have 128GB but the latency is nearly 10ms more than my 32GB E die memory so I am hoping I can be closer than this.

Thank you in advance for any advice.

PS These memories have lights on them. I have never seen this before! Very fancy.


----------



## Manuru

BluePaint said:


> @Manuru
> RAM is fine. It's all in the subtimings. Post your Zentimings screen so that we can have a look.
> 
> Btw, if u don't chase the last 1 percentage, it's usually enough to get the cheapest B-die RAM u can find and with some more voltage and tuning it will perform very very close to the more expensive bins, especially on Ryzen because u can't clock as high as on Intel. I have G-Skill 3600CL16 DR 16GB RAM and I use it 24h with 3800CL14 tRFC 252 with 53ns AIDA latency. It also worked @ 4066CL16 with my 5800X. Both on 1.5v.
> 
> As u experience yourself, for optimal performance u have to finetune anyway. 3800CL14 with loose subtimings will perform worse than hand optimized 3600CL16. High frequency and tight main timings are primarily for selling the kits at a higher price. Sub-timings are kept loose for stability and best compatibility since they don't want uninformed people to return the RAM when the XMP setting fails.


Thank you for the explanation.
You were right, RAM is fine. I double-checked everything and found out that I had to manually force 1:1:1 ratio in BIOS. After I did that, AIDA64 gave me expected latency below 60ns.

I decided to get a pricey kit because I expected it to be easier to overclock, but maybe it was too naive. I tried safe and fast presets from Ryzen Dram Calculator, but both of them led to errors in TM5. Stock XMP works fine. I think I'll wait AGESA 1.2.0.0 for my motherboard first.


----------



## BluePaint

Dont have much time. For better latency, u can reduce trc, tfaw and trfc.
for 1900 fclk u should be able to use lower voltages, esp vddp. Vddp 0.9, vddg ccd 0.95, vddg iod 1.0
Here is my 3609cl16 b die kit @ 2033/4066, gaming stable but ofc with whea errors. Its an older try and now i would probably use somewhat lower secondary voltages, esp vddp


----------



## Karagra

Hey guys, been testing out 3800 all today and was wondering if you guys had some advice on tightening the timings at all? Dram 1.45v, Soc 1.125, VDDG's 1.050, and CLDO .950 atm.. Passed 400% Single on the Dram Calculator memtest.


----------



## obscurehifi

Hi everyone, I was hoping someone could help me understand what the DOCP profile of this equivalent ram would be if it was the AMD NEO version, not the Intel XMP version that I ended up buying. I have a 5800x that I'm pairing it with.

I attached the Zentimings photo of the XMP profile of the F4-3600C14-16GTZR TridentZ RGB. I'll upload a better quality screenshot in the morning... I have it running decently with modifications for AMD at 3600 14 but it really seems finicky and often won't post with changes that I think are okay, or at least were easier on the Crucial sticks they are replacing.

Does anyone have the DOCP profile of the 3600C14 TridentZ NEO, or equivalent, they could post please? Or any other brand's 3600C14 B-die? 









EDIT: Replaced my smart phone image of zentimings with the actual screen shot of zen timings. This is the original Intel XMP before I changed the settings to better match AMD.

Sent from my SM-G973U using Tapatalk


----------



## MaxT

obscurehifi said:


> Hi everyone, I was hoping someone could help me understand what the DOCP profile of this equivalent ram would be if it was the AMD NEO version, not the Intel XMP version that I ended up buying. I have a 5800x that I'm pairing it with.
> 
> I attached the Zentimings photo of the XMP profile of the F4-3600C14-16GTZR TridentZ RGB. I'll upload a better quality screenshot in the morning... I have it running decently with modifications for AMD at 3600 14 but it really seems finicky and often won't post with changes that I think are okay, or at least were easier on the Crucial sticks they are replacing.
> 
> Does anyone have the DOCP profile of the 3600C14 TridentZ NEO, or equivalent, they could post please? Or any other brand's 3600C14 B-die?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sent from my SM-G973U using Tapatalk


You shouldn't really be relying on DOCP much, as it only sets the Primary timings. What voltage are you running for RAM? You are also running with GDM off 1T, which is harder to do than GDM on (but that's a good thing for performance).


----------



## Dannyz

Alright follow up to my last post 

All I did was slightly reduce Vsoc and lowered frequency and IF clock to run 3733MHz and ended up with this. 









No errors. 

So now I think that my 5900X might just be garbage bin quality. It doesn't score very high on single threaded tests, and I wasn't able to stabilize it at 3800MHz mem. Or the latest bios F32 for the X570 Aorus master is holding it back. Hoping its the latter. But I'm going to call it here for now and start tuning the CPU itself.


----------



## obscurehifi

MaxT said:


> You shouldn't really be relying on DOCP much, as it only sets the Primary timings. What voltage are you running for RAM? You are also running with GDM off 1T, which is harder to do than GDM on (but that's a good thing for performance).


I tried the Intel XMP settings (posted above) out of curiosity when I started them up for the first time but the results weren't great compared to my 3600-18 Crucial LPX 16GB that I had running at 3733-16 and 3800-18 with better results.









After that I came up with these timings and they run pretty decent and appear to be stable. I've also tried 3600-14-14-15-14-28-42 with the all the other timings the same and it also seems to work well and increases the bandwidth result a little. I'm running at 1.45V. I was hoping to compare with NEO XMP to see how close I am to what AMD puts out but I realize I can do without them.










I have also tried this but didn't run OCCT on it yet but the results are encouraging. Maybe that's what I'll do now actually.









Any thoughts on ways to improve? BTW, I'm running 3402 AGESA 1.2.0.0 on x570 Gaming Tuf Plus Wifi Board.


----------



## hisXLNC

cant post with FCLK above 1800 with latest asus 3202 bios. kit is rated for 4000mhz cl15 running it at these. anything to change? (using 1.385v).


----------



## brucechow

What do you guys think of karhu test nowadays? My rig:
B450-F gaming latest 4202 bios
5900x
4x8gb ripjaws V 3200cl14

I used this combo for a whole month without issues, then 2 days ago I decided to test my dram with karhu and I got a reboot with whea error (machine check exception, with cache hierarchy error with variable ID numbers for APIC cores). My previous ryzen 3600 passed 12 hours without issues at the same config.

The thing is, under normal daily usage my pc is completely fine, no crashes on hours of cb23, prime95, small, smallest or large and memtest86 as well. Tried relaxed timings and raised VSoC 1.1 and 1.45 for dram without success, best I got was a karhu run for 2 hours and then the pc rebooted. With docp I can open warzone, cyberpunk, dbd, lol, csgo, eso, borderlands 3, chrome and discord at the same time without errors. Do you guys think I should consider my cpu+Mobo+ram stable???


----------



## devoker

Deleted


----------



## MaxT

brucechow said:


> What do you guys think of karhu test nowadays? My rig:
> B450-F gaming latest 4202 bios
> 5900x
> 4x8gb ripjaws V 3200cl14
> 
> I used this combo for a whole month without issues, then 2 days ago I decided to test my dram with karhu and I got a reboot with whea error (machine check exception, with cache hierarchy error with variable ID numbers for APIC cores). My previous ryzen 3600 passed 12 hours without issues at the same config.
> 
> The thing is, under normal daily usage my pc is completely fine, no crashes on hours of cb23, prime95, small, smallest or large and memtest86 as well. Tried relaxed timings and raised VSoC 1.1 and 1.45 for dram without success, best I got was a karhu run for 2 hours and then the pc rebooted. With docp I can open warzone, cyberpunk, dbd, lol, csgo, eso, borderlands 3, chrome and discord at the same time without errors. Do you guys think I should consider my cpu+Mobo+ram stable???


Did that happen right when you started the test? This sounds more like the idle reboot you get with Curve Optimizer. Those can creep up any time, even after days of stability. If you are using CO, then make the note of the APIC ID and adjust the curve offset for the appropriate core. This may not be related to RAM.


----------



## brucechow

MaxT said:


> Did that happen right when you started the test? This sounds more like the idle reboot you get with Curve Optimizer. Those can creep up any time, even after days of stability. If you are using CO, then make the note of the APIC ID and adjust the curve offset for the appropriate core. This may not be related to RAM.


I have pbo2 and everything on auto besides docp. Not using curve optimizer and I also left my pc on idle for 3 hours and nothing happened. Only karhu triggers it


----------



## MaxT

brucechow said:


> I have pbo2 and everything on auto besides docp. Not using curve optimizer and I also left my pc on idle for 3 hours and nothing happened. Only karhu triggers it


How about TM5? I would still make a not of which APIC ID it was. Does it happen every time with Karhu? Is it always the same APIC ID in the log?


----------



## brucechow

MaxT said:


> How about TM5? I would still make a not of which APIC ID it was. Does it happen every time with Karhu? Is it always the same APIC ID in the log?


It’s not the same apic id, can go from 16, 6, 27, 23. Only happens on karhu with docp, I can do whatever I want with my pc, even running cyberpunk with cb23 doesn’t crash.

Didn’t have much time to test without docp though, but I did it for 20 minutes without issues. Usually it reboots in less than 5 min. I will try to run tm5 later when I get home and let it run overnight without docp


----------



## devoker

Can anyone tell me why do I have so low benchmark scores? 1.4V 3600 Mhz CL18 but it is nowhere near where it should score.
Is this a terrible kit? (Adata xpg gammix d30 3000 16-20-20-38)

My setup:
asrock b450 itx
r5 3600


----------



## Shoey Peachew

Here are my settings. Passes TestMem5 1usmus test ([email protected] crashes on startup), 4hrs Memtest86, OCCT 1hour extreme test, 4hours prime95.









Lian Li PC-011D Black ~
Gigabyte X570 AORUS Pro Wifi ~
Corsair RMX 850W ~
AMD Ryzen 5800X (All cores -15 and boost to 5100mhz work in progress) ~
EKWD EK-Kit X360 ~
G.SKILL Trident Neo 32GTZN 3600 OC 1:1 3800 14 14 14 28 1.51v ~
x2 Sabrent 1TB Rocket NVMe 4.0 Gen4 PCIe ~
Zotac 3070 Twin Edge Core Offset +100 Memory +1100 ~
Acer 165Hz XB270HU ~
BenQ 244hz XL2546K ~


----------



## MaxT

brucechow said:


> It’s not the same apic id, can go from 16, 6, 27, 23. Only happens on karhu with docp, I can do whatever I want with my pc, even running cyberpunk with cb23 doesn’t crash.
> 
> Didn’t have much time to test without docp though, but I did it for 20 minutes without issues. Usually it reboots in less than 5 min. I will try to run tm5 later when I get home and let it run overnight without docp


Also, if you want an ultimate stability test, run y-cruncher. Not much will stress test your whole system (cpu/ram/memory controller) more than this. Just keep an eye on temps. You will hit over 90c easily. Personally, I don't consider my system stable unless I pass TM5 18+ (anta777 extreme or 1usmus_v3) hours and y cruncher 12+ hours with 0 errors and 0 WHEA errors.


----------



## kratosatlante

Shoey Peachew said:


> Here are my settings. Passes TestMem5 1usmus test ([email protected] crashes on startup), 4hrs Memtest86, OCCT 1hour extreme test, 4hours prime95.
> View attachment 2475441
> 
> 
> Lian Li PC-011D Black ~
> Gigabyte X570 AORUS Pro Wifi ~
> Corsair RMX 850W ~
> AMD Ryzen 5800X (All cores -15 and boost to 5100mhz work in progress) ~
> EKWD EK-Kit X360 ~
> G.SKILL Trident Neo 32GTZN 3600 OC 1:1 3800 14 14 14 28 1.51v ~
> x2 Sabrent 1TB Rocket NVMe 4.0 Gen4 PCIe ~
> Zotac 3070 Twin Edge Core Offset +100 Memory +1100 ~
> Acer 165Hz XB270HU ~
> BenQ 244hz XL2546K ~


for this voltaje 1.51 you can run trfc 245 or lees, los perfromance with your actual trfc 346, first try 280-208-128


----------



## obscurehifi

Definitely made some huge improvements since yesterday. I followed @MaxT advice and also went off a NEO 32GB Zentimings screenshot I found that got me started. In the end, this is almost exactly the 1usmus DRAM Calculator recommendation at the limits of what it says is supported for Zen2 and the max frequency it will accept of 3867. With these settings of 3867-16-16-16-16-32-48 everything appears to be stable. I'm sure there are some more error tests I should probably run and will eventually. One thing I can say is that my system won't post at 3933-16-16-16-16 or 3867-14-16-16-16 or 3867-15-16-16-16 (GDM off); even with voltage bumped to 1.51. So the 3867-16 @1.45V seems to be a winner.

This is more than a 10% improvement over the Intel XMP settings (read bandwidth) that came in the TridentZ RGB 3600c14 32GB kit (I posted those above). This has completed the OCCT SSE test for 30 minutes. I'll do the AVX later but I've never had AVX not pass when SSE passes. I am running 1.45V on the ram which apparently isn't reported by my mobo. I also ran it through the entire 3DMark Suite and noticed some improvements, namely stability at high OC settings on my 3080 from benchmark to benchmark.

My system is:
Antec P9 Window Case
EVGA 850W G2
ASUS Tuf Gaming x570-Plus Wifi Bios 3402
Ryzen 5800X at all stock settings (haven't overclocked it at all yet)
Noctua nh-d15S Cooler on turbo fan setting
G. Skill TridentZ RGB 2x16GB B-Die
Gigabyte AORUS Xtreme 3080 Waterforce at +135 (1980) core and +2400 (21402) mem. (I max the gpu fans when benching graphics)
Samsung 970 1TB Evo Plus

This image is kind of a mess but there's only so much real estate.

















With exception of tRFC, CAD_BUS AddrCmdDrv, and DRAM Voltage, I'm running exactly what the DRAM Calculator recommends for the Fast Preset for B-die, A3/A2/B2, Dual Rank, 3866. I haven't actually tried changing tRFC to CAD_BUS AddrCmdDrv match but what I have seems to work fine. I progressed from the safe secondary and tertiary timings in chunks from safe to fast while check to see if my system would post.









I'm pretty happy with this as I seem to have reached a pretty high bandwidth while having a pretty low latency for a 5800x. Thoughts? Suggestions?

EDIT, minor grammar and adding the word almost above.

EDIT2, removed HWinfo screenshot and added result from TM5.


----------



## DeletedMember558271

I lose my mind a little bit every time someone posts basically their entire HWinfo except the WHEA error part
Also I wish my B-Die had temp sensors


----------



## obscurehifi

Dreamic said:


> I lose my mind a little bit every time someone posts basically their entire HWinfo except the WHEA error part
> Also I wish my B-Die had temp sensors


Shoot, I actually intended to sure that very last line of HWinfo showing 0 WHEA... Sorry to contribute to you losing a bit of your mind lol. 

Sent from my SM-G973U using Tapatalk


----------



## Shoey Peachew

kratosatlante said:


> for this voltaje 1.51 you can run trfc 245 or lees, los perfromance with your actual trfc 346, first try 280-208-128


Thanks for the suggestion!


----------



## obogobo

Dreamic said:


> This 1900 specific bug is so stupid and it's not specific to one brand or motherboard I guess, I don't understand.
> ...
> I want to know if anyone with this issue has got it to post


Just adding that I've experienced the same issue today.
[1800, 1867] = OK
1900 = NO POST
1933 = OK (does crash in Prime95 after a while, read this could be due to _too much _IOD/CCD voltage when using AVX instructions)

was using 1.125V for SOC, IOD, and CCD with 5900x on x570 Aorus Xtreme (BIOS F33a). Really just want IF 1900, nothing higher. Would make it easy to match the 3800 XMP profile on my kit.


----------



## MaxT

Here is my almost final (not bad for a dual rank 16GB x 2 bdie):










I am still lowering the voltages for VDIMM/VSOC/VDDG to see how low they will go. VDIMM is at 1.49v right now (not visible to Windows/Zen Timings/HWInfo64).
My weak spot is TFAW. 36 and lower wasn't stable, so I have to leave it at 40 (not a big deal).

I will post a final screenshot in a few days, once I fully lower my voltages and will add HWInfo64 and TM5/y-cruncher to the list.

If anyone has any suggestions on timings, let me know.


----------



## CrashMclarson

MaxT said:


> Here is my almost final (not bad for a dual rank 16GB x 2 bdie):
> 
> View attachment 2475505
> 
> 
> I am still lowering the voltages for VDIMM/VSOC/VDDG to see how low they will go. VDIMM is at 1.49v right now (not visible to Windows/Zen Timings/HWInfo64).
> My weak spot is TFAW. 36 and lower wasn't stable, so I have to leave it at 40 (not a big deal).
> 
> I will post a final screenshot in a few days, once I fully lower my voltages and will add HWInfo64 and TM5/y-cruncher to the list.
> 
> If anyone has any suggestions on timings, let me know.


What memory are you using? I couldn't even boot up after getting 3402 bios. Thanks


----------



## DeletedMember558271

obogobo said:


> Just adding that I've experienced the same issue today.
> [1800, 1867] = OK
> 1900 = NO POST
> 1933 = OK (does crash in Prime95 after a while, read this could be due to _too much _IOD/CCD voltage when using AVX instructions)
> 
> was using 1.125V for SOC, IOD, and CCD with 5900x on x570 Aorus Xtreme (BIOS F33a). Really just want IF 1900, nothing higher. Would make it easy to match the 3800 XMP profile on my kit.


Let us know if you ever find out how to post at 1900 or get rid of WHEAs 1933+
Cause I haven't seen anyone else figure it out and would like to be higher than 1867 too


----------



## MaxT

CrashMclarson said:


> What memory are you using? I couldn't even boot up after getting 3402 bios. Thanks


It's in the Zen Timings sceenshot at the bottom: F4-3200C14D-32GTZN (16TZN x 2)


----------



## CrashMclarson

MaxT said:


> It's in the Zen Timings sceenshot at the bottom: F4-3200C14D-32GTZN (16TZN x 2)


Thanks...Have you been able to hit 1900 fclock on that board? I have tried everything with the Plus board.


----------



## MaxT

CrashMclarson said:


> Thanks...Have you been able to hit 1900 fclock on that board? I have tried everything with the Plus board.


I have. I had no WHEA errors. But this RAM won't do 3800c14 at 1.5v, so I haven't tried staying with 1900, as I don't want to go higher than 1.5v. Looks like I am staying at 1866 at 1.49v.


----------



## devoker

Anyone?



devoker said:


> Can anyone tell me why do I have so low benchmark scores? 1.4V 3600 Mhz CL18 but it is nowhere near where it should score.
> Is this a terrible kit? (Adata xpg gammix d30 3000 16-20-20-38)
> 
> My setup:
> asrock b450 itx
> r5 3600
> View attachment 2475428


----------



## BluePaint

@devoker
Benchmarks look normal for that kind of kit and CPU.
If u want better performance you have to look for Micron-E RAM overclocking guide. Preferably for your kind of 16GB modules.
Here is a link to a german (use google translate) OC guide for Micron E RAM, but it's for 8GB sticks (don't have the experience to tell how transferable these settings are).
Crucial Ballistix Tactical Tracer RGB mit Micron E-Die im Test


----------



## devoker

BluePaint said:


> @devoker
> Benchmarks look normal for that kind of kit and CPU.
> If u want better performance you have to look for Micron-E RAM overclocking guide. Preferably for your kind of 16GB modules.
> Here is a link to a german (use google translate) OC guide for Micron E RAM, but it's for 8GB sticks (don't have the experience to tell how transferable these settings are).
> Crucial Ballistix Tactical Tracer RGB mit Micron E-Die im Test


Thanks. I think it's the best I can do with this kit. At CL 16 soc 1.1 system keeps crashing during boot and in bios. Had to reset cmos everytime.


----------



## acivi

Same as others, can't post 1900if, but all above works fine without touching any other seetting. And I'm full stable 2000if/ 4000ram but I get whea warnings no matter what I do.

ASUS B550F, any of past 5ish bios versions back..

And also seeing those weird L3 read speeds, 3733 vs 4000 speeds 1:1


----------



## MaxT

My final OC:










All the specifics are here:

__
https://www.reddit.com/r/overclocking/comments/kmryeg


----------



## acivi

@MaxT I think you have same issue as me, look at your l3 reads, i have similarly bad ones runing that RAM speeds, and if you check my 4000mhz ram PIC above, i have same or better latencies than you without any tweaking of ram runing much bigger timings, which makes no sense, just rams stock 4000mhz profile, and L3 cache reads are just fine than, just dont get whats going on..


----------



## halcyonon

devoker said:


> Can anyone tell me why do I have so low benchmark scores? 1.4V 3600 Mhz CL18 but it is nowhere near where it should score.
> Is this a terrible kit? (Adata xpg gammix d30 3000 16-20-20-38)
> 
> My setup:
> asrock b450 itx
> r5 3600


I'm not super familiar with Zen2, and what it should be scoring, but I believe that Micron E die is better at higher frequencies than it is at tight timings at frequencies such as 3600.


----------



## MaxT

acivi said:


> @MaxT I think you have same issue as me, look at your l3 reads, i have similarly bad ones runing that RAM speeds, and if you check my 4000mhz ram PIC above, i have same or better latencies than you without any tweaking of ram runing much bigger timings, which makes no sense, just rams stock 4000mhz profile, and L3 cache reads are just fine than, just dont get whats going on..


I've described that in my reddit post, and here as well I think. AIDA64 L3 cache does't seem to work right for Zen3. We are supposed to be getting over 1100 with dual CCD chips like 5900x or 5950x, but you get half of that to begin with and if you start changing your TDC/EDC limits, then the scores can drop even more. This seems to be related to PBO, especially once you start using Curve Optimizer. If you do a manual all core overclock, your scores will be where they should. Asus boards have a feature called Fmax optimizer. If you enable it, you also get scores over 1100. So the consensus seems to be that AIDA64 L3 cache scores are irrelevant, as no other regular benchmarks or game benchmarks are affected. It's either a bug with AIDA64 or AGESA for Zen3. And if it is not a bug, it doesn't seem to affect anything. You can probably test this with SiSoft Sandra, as it measures the L3 cache as well, but I haven't bothered until there is more information on this "potential" issue.

What tCAS/TRFC are you running at 4000? If you look at the community spreadsheet for Zen3, you will see that people get much lower latency that you at 4000, once they tighten their timings, so your latency looks normal for 4000 untweaked. My latency is among the lowest for 3733c14 (and I haven't pushed my tRFC as low as I could).


----------



## KedarWolf

I went from 60-20-20-24 ClkDrvStr etc. to 24-24-24-24 and now I'm at ProcODT 36.9 TM5 1usmus_v3, [email protected] and stressapptest stable.

2x16GB b-die RAM.


----------



## acivi

MaxT said:


> I've described that in my reddit post, and here as well I think. AIDA64 L3 cache does't seem to work right for Zen3. We are supposed to be getting over 1100 with dual CCD chips like 5900x or 5950x, but you get half of that to begin with and if you start changing your TDC/EDC limits, then the scores can drop even more. This seems to be related to PBO, especially once you start using Curve Optimizer. If you do a manual all core overclock, your scores will be where they should. Asus boards have a feature called Fmax optimizer. If you enable it, you also get scores over 1100. So the consensus seems to be that AIDA64 L3 cache scores are irrelevant, as no other regular benchmarks or game benchmarks are affected. It's either a bug with AIDA64 or AGESA for Zen3. And if it is not a bug, it doesn't seem to affect anything. You can probably test this with SiSoft Sandra, as it measures the L3 cache as well, but I haven't bothered until there is more information on this "potential" issue.
> 
> What tCAS/TRFC are you running at 4000? If you look at the community spreadsheet for Zen3, you will see that people get much lower latency that you at 4000, once they tighten their timings, so your latency looks normal for 4000 untweaked.


I dont use Curve optimiser as i get Idle reboots. And between 2 pics i posted only difference is RAM and IF speed.I do use PBO with manual settings on both.
And i tried Curve Optimiser with 2000IF and L3 reads where fine.

Also i cant boot 1900IF(not even post), but i can boot anything above.

So my conclusion is that BIOSes are fcked and nothing more, its only realted to IF speeds from what i see.


----------



## MaxT

KedarWolf said:


> I went from 60-20-20-24 ClkDrvStr etc. to 24-24-24-24 and now I'm at ProcODT 36.9 TM5 1usmus_v3, [email protected] and stressapptest stable.
> 
> 2x16GB b-die RAM.
> 
> View attachment 2475626


Looks pretty good!


----------



## MaxT

acivi said:


> I dont use Curve optimiser as i get Idle reboots. And between 2 pics i posted only difference is RAM and IF speed.I do use PBO with manual settings on both.
> And i tried Curve Optimiser with 2000IF and L3 reads where fine.
> 
> Also i cant boot 1900IF(not even post), but i can boot anything above.
> 
> So my conclusion is that BIOSes are fcked and nothing more, its only realted to IF speeds from what i see.


Idle reboots are easily fixed. My all core workloads boost to 4.8 GHz effective with CO (during TM5 runs for example). Can't beat it. It's absolutely worth it.
Interesting observation on the IF speed and L3 cache scores. Once again, I am considering this an AIDA64 bug, until there is proof it's something else. They have a forum where the developers respond, maybe it is worth asking there.

Edit: here is the link to the Community Spreadsheet for Zen3: Zen RAM Overclocking


----------



## acivi

MaxT said:


> Idle reboots are easily fixed. My all core workloads boost to 4.8 GHz effective with CO (during TM5 runs for example). Can't beat it. It's absolutely worth it.
> Interesting observation on the IF speed and L3 cache scores. Once again, I am considering this an AIDA64 bug, until there is proof it's something else. They have a forum where the developers respond, maybe it is worth asking there.
> 
> Edit: here is the link to the Community Spreadsheet for Zen3: Zen RAM Overclocking


Thing is i just want to run my RAM at 4000 (1:1) as its (Crucial Balistix, 4000mhz), i didint bother with timings as i get WHEA errors on anything above 1866 IF and i run it just for test, so im running it lower speed where i get no WHEA, but its stupid coz i get better latencies and speed just runing RAM stock speeds(4000), im stuck until the asus fixes bioses...

Also this is MIcron B die, cant find much help on net about overclocking it, from what i was trying it doesnt like touching some stuff unlike samsung b dies do..


----------



## MaxT

acivi said:


> Thing is i just want to run my RAM at 4000 (1:1) as its (Crucial Balistix, 4000mhz), i didint bother with timings as i get WHEA errors on anything above 1866 IF and i run it just for test, so im running it lower speed where i get no WHEA, but its stupid coz i get better latencies and speed just runing RAM stock speeds(4000), im stuck until the asus fixes bioses...


I hear you. Not to be a downer, but there is a possibility they never will. Anything over 1800 will not be guaranteed from what I've read. @1usmus says up to 1900 should be WHEA error free with AGESA 1.2.0.0 (but not anything over 1900). Yet some people already seem to run 2000 just fine.


----------



## acivi

MaxT said:


> I hear you. Not to be a downer, but there is a possibility they never will. Anything over 1800 will not be guaranteed from what I've read. @1usmus says up to 1900 should be WHEA error free with AGESA 1.2.0.0 (but not anything over 1900). Yet some people already seem to run 2000 just fine.


Im sure 1900 would be WHEA free if i could even get POST


----------



## Jaeyger

What is a safe tRFC for 8GB B-die modules at 3800, or what is the proper method for dialing it in? I tried to research but not much online about how to set this one. My current setup below.


----------



## MaxT

Jaeyger said:


> What is a safe tRFC for 8GB B-die modules at 3800, or what is the proper method for dialing it in? I tried to research but not much online about how to set this one. My current setup below.
> 
> View attachment 2475634


I've read 160ns-180ns, but I've seen people go lower. I think only long-term tests show instability. Some say running OCCT 3d stress test at the same time at TM5 or Karhu, heats up the RAM more (which is true because of the video card heat), and shows tRFC errors quicker.

I'm at 154ns at 3733 and could probably go lower if I wanted to.


----------



## Nizzen

Is it just med that miss Intel cpu and Asus Apex MB when trying to "overclock" the memory on 5900x/5950x?

I'm testing Asus Dark hero with 5900x, and it's a mess with WHEA and no boot with 1900 fclk 😂

Why couldn't AMD just go all in with Ryzen 3 and make fclk @ 4600mhz easy ! About 60GB/s read max (daily stable) with Ryzen 3 is just sad


----------



## Jaeyger

MaxT said:


> I've read 160ns-180ns, but I've seen people go lower. I think only long-term tests show instability. Some say running OCCT 3d stress test at the same time at TM5 or Karhu, heats up the RAM more (which is true because of the video card heat), and shows tRFC errors quicker.


I found this post that explains what it is pretty well. 









Lowering TRFC. Are specific values needed?


So I have my memory stable at 4100mhz 16 17 17 37. Auto set TRFC to 718 which I believe it very high? I have read lowering TRFC is the next most beneficial timing after the primaries? I have also read TRFC needs to be specific values? You can't just throw random numbers like 400 at it? Any...




www.overclock.net





Seems no one really knows how low is too low...? I'm hesitant to go too low cuz of what I've read about it being a "silent killer", but it does seem like this timing affects latency quite a bit.


----------



## MaxT

Jaeyger said:


> I found this post that explains what it is pretty well.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Lowering TRFC. Are specific values needed?
> 
> 
> So I have my memory stable at 4100mhz 16 17 17 37. Auto set TRFC to 718 which I believe it very high? I have read lowering TRFC is the next most beneficial timing after the primaries? I have also read TRFC needs to be specific values? You can't just throw random numbers like 400 at it? Any...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> Seems no one really knows how low is too low...? I'm hesitant to go too low cuz of what I've read about it being a "silent killer", but it does seem like this timing affects latency quite a bit.


All true.


----------



## KedarWolf

This passed an hour of usmus TM5 at 1000%. I find if it'll pass that quick test, it'll pass anything I throw at it.


----------



## Hale59

KedarWolf said:


> This passed an hour of usmus TM5 at 1000%. I find if it'll pass that quick test, it'll pass anything I throw at it.


I did this with only 1 stick of RAM.

Would you be able to try these timings (We have the same RAM) to see what latency you get with your 2 sticks please. Thanks


----------



## KedarWolf

Hale59 said:


> I did this with only 1 stick of RAM.
> 
> Would you be able to try these timings (We have the same RAM) to see what latency you get with your 2 sticks please. Thanks
> 
> View attachment 2475667


I can't run tRCDRD 15 stable let alone 14, even with that RAM voltage, so won't try it.


----------



## Hale59

KedarWolf said:


> I can't run tRCDRD 15 stable let alone 14, even with that RAM voltage, so won't try it.


Suppose the rest of the hardware is different. But RAM voltage at 1.56v, well, this is ocn, isn't it? I thought you were keen to go down the rabbit hole. And anyway, this is not for 24/7.


----------



## Hale59

KedarWolf said:


> I can't run tRCDRD 15 stable let alone 14, even with that RAM voltage, so won't try it.


And by the way, there are people going 1.93v and more at this AMD competition. Actually a good way to check timings:





Overclocking, overclocking, and much more! Like overclocking.


HWBOT is a site dedicated to overclocking. We promote overclocking achievements and competitions for professionals as well as enthousiasts with rankings and a huge hardware database.




hwbot.org


----------



## KedarWolf

Hale59 said:


> Suppose the rest of the hardware is different. But RAM voltage at 1.56v, well, this is ocn, isn't it? I thought you were keen to go down the rabbit hole. And anyway, this is not for 24/7.


I'm not afraid to run 1.56v, I already know at that voltage I can't run what I said stable at 15 let alone 14 with 2x16GB Dual Rank RAM.


----------



## KedarWolf

Hale59 said:


> And by the way, there are people going 1.93v and more at this AMD competition. Actually a good way to check timings:
> 
> 
> 
> 
> 
> Overclocking, overclocking, and much more! Like overclocking.
> 
> 
> HWBOT is a site dedicated to overclocking. We promote overclocking achievements and competitions for professionals as well as enthousiasts with rankings and a huge hardware database.
> 
> 
> 
> 
> hwbot.org


I'm surprised this booted. All kinds of error in TM5.


----------



## KedarWolf

Six hours of TM5 Ollie with these timings.

As well, it passes y-cruncher stress tests and y-cruncher 5,000,000,000 interactions.


----------



## Manuru

Tightened secondary and tertiary timings on my DDR4-3800MHz CL14-16-16-36 2x16. Tried 14-14-14-28 but tm5 fails immediately, so back to stock xmp primary except tRAS.


----------



## obogobo

Manuru said:


> Tightened secondary and tertiary timings on my DDR4-3800MHz CL14-16-16-36 2x16. Tried 14-14-14-28 but tm5 fails immediatly, so back to stock xmp primary except tRAS.
> 
> View attachment 2475771
> View attachment 2475772
> View attachment 2475773


How many sticks of RAM is that, 2, 4?
Nevermind. So I should probably try removing two of my 8GB sticks and see if I can POST @ 1900. I have the same GSKill kit but in 4x single rank sticks.

Edit: Nope! No POST @ 1900 IF. 1933 just fine though...


----------



## Hale59

KedarWolf said:


> Six hours of TM5 Ollie with these timings.
> 
> As well, it passes y-cruncher stress tests and y-cruncher 5,000,000,000 interactions.


I have tried your timings. 

At 1.48v in Bios, PC sort of freezes and completely reboots. I could sense there was not enough RAM voltage.
Increase voltage 1 notch (1.49v), was able to enter windows, started TM5 and got frozen.
Increase voltage 1 notch (1.50v), enter windows and initiated TM5. AT the first error, I rebooted and increased RAM voltage to 1.51v. After that I was able to run TM5 without errors.

My latency is lower than yours, because there are many variables, the main one being a weaker CPU, and on top of that, is only 1 stick of RAM. I was also running BCLK like you, at 100.45


----------



## Hale59

KedarWolf said:


> I'm surprised this booted. All kinds of error in TM5.


SuperPI 32M with BenchMate, my timings gives this result. Could have been better if I had a stronger CPU and 2 sticks of RAM.











**With your Timings I get a weaker result*. *Did not save the results.*


----------



## Hale59

KedarWolf said:


> Six hours of TM5 Ollie with these timings.
> 
> As well, it passes y-cruncher stress tests and y-cruncher 5,000,000,000 interactions.


I went down further into the rabbit hole, and got my tCL 12 were you can see the timings.
Got a better result.


----------



## Hale59

Hale59 said:


> I went down further into the rabbit hole, and got my tCL 12 were you can see the timings.
> Got a better result.


@KedarWolf, still @ tCL12, got even a better result (same timings as above)


----------



## Hale59

@KedarWolf, with your timings and 2 sticks of RAM, please run SuperPI 32M with BenchMate to check the results.






BenchMate







benchmate.org


----------



## KedarWolf

Hale59 said:


> @KedarWolf, with your timings and 2 sticks of RAM, please run SuperPI 32M with BenchMate to check the results.
> 
> 
> 
> 
> 
> 
> BenchMate
> 
> 
> 
> 
> 
> 
> 
> benchmate.org


Nope, not doing it through BenchMate, it has a virus.


----------



## Hale59

KedarWolf said:


> Nope, not doing it through BenchMate, it has a virus.


What kind of virus?


----------



## Nizzen

KedarWolf said:


> Nope, not doing it through BenchMate, it has a virus.


LOL


----------



## Manuru

Manuru said:


> Tightened secondary and tertiary timings on my DDR4-3800MHz CL14-16-16-36 2x16. Tried 14-14-14-28 but tm5 fails immediately, so back to stock xmp primary except tRAS.


Did 30m anta777 test fine and tried usmus config again - got an error. What timings should I increase at first?


----------



## DeletedMember558271

obogobo said:


> How many sticks of RAM is that, 2, 4?
> Nevermind. So I should probably try removing two of my 8GB sticks and see if I can POST @ 1900. I have the same GSKill kit but in 4x single rank sticks.
> 
> Edit: Nope! No POST @ 1900 IF. 1933 just fine though...


From another thread


ManniX-ITA said:


> It's the same for almost everyone.
> Totally WHEA error free above 1900 is really hard and at 2000 and above almost impossible.
> Tried as well all the suggestions from @Veii with the Master F33a BIOS, which is 1.2.0.0.
> Didn't help, still get a couple of errors every now and then.
> What really helped was to lower the VSOC and VDDG voltages just before it goes unstable.
> With the Unify-X my 5950x doesn't POST at all with low voltages at FCLK 2000.
> Another big help was setting the OCP to Medium.
> 
> *There are a lot of CPUs that for some reason can't boot 1900, it's an AGESA bug for sure.
> It's hopefully going to be fixed soon.*


And in the DRAM Calc thread there's a person: "I cannot go above 1866 FCLK stable. 1900 doesn't post and 1933-2000 is WHEA city".
I've probably seen like 50+ people mention this problem alone and nobody has found a solution, its been 3 months and AMD has done nothing. It's not specific to a brand or board.
So I guess we just keep waiting forever and hope someday people somehow figure out how to do their jobs and fix something, WHEA or no post.


----------



## ManniX-ITA

KedarWolf said:


> Nope, not doing it through BenchMate, it has a virus.


Really?


----------



## DeletedMember558271

There's a new FCLK record on the Zen Sheet that's apparently WHEA free, 2133/4267








Crazy lucky? 1.6vDIMM though, my 3080 would overheat it, would have to tone it down myself for 24/7.
If people are already pulling this off I gotta be able to get 1933 4x8GB with no WHEA someday right? If 1900 FCLK no post AGESA bug is never going to be fixed. I want 1900 minimum


----------



## KedarWolf

Good old HCI.


----------



## Akex

Dreamic said:


> There's a new FCLK record on the Zen Sheet that's apparently WHEA free, 2133/4267
> 
> 
> 
> 
> 
> 
> 
> 
> Crazy lucky? 1.6vDIMM though, my 3080 would overheat it, would have to tone it down myself for 24/7.
> If people are already pulling this off I gotta be able to get 1933 4x8GB with no WHEA someday right? If 1900 FCLK no post AGESA bug is never going to be fixed. I want 1900 minimum


WHEA is mainly in heavy load like OCCT SSE / Small or Large Data, with Super Pi although this is very very good it is not necessarily representative
I would have preferred to see a 1usmus_v3 or Anta Extreme with at least 20 passes to have no doubts


----------



## Hale59

KedarWolf said:


> Good old HCI.
> 
> View attachment 2476034
> 
> 
> View attachment 2476035


I doubt BenchMate has virus. HWBOT is using it.

I don't wish to insist, but I would like toknow the results of SuperPi - 32M with your timings.
You can download SuperPi standalone version here: Overclocking, overclocking, and much more! Like overclocking.
If you do run it, push your CPU to the max.
I would appreciate


----------



## KedarWolf

Hale59 said:


> I doubt BenchMate has virus. HWBOT is using it.
> 
> I don't wish to insist, but I would like toknow the results of SuperPi - 32M with your timings.
> You can download SuperPi standalone version here: Overclocking, overclocking, and much more! Like overclocking.
> If you do run it, push your CPU to the max.
> I would appreciate


This with a PBO overclock, but I'm running a 3950x, not 5000 series.


----------



## obscurehifi

Akex said:


> WHEA is mainly in heavy load like OCCT SSE / Small or Large Data, with Super Pi although this is very very good it is not necessarily representative
> I would have preferred to see a 1usmus_v3 or Anta Extreme with at least 20 passes to have no doubts


I thought I would give your suggested test methods a shot tonight. I'm new to running these tests, so I'm learning every day. What are some other suggested methods for testing for stability?

This is with the same 3867-16 setting I posted several days ago except I changed the AddrCmdDrvStr from 24 to 20 ohm because it helped higher frequencies post (as did a higher ProcODT of 53), so I decided to see how it worked at 1933. The below two images were done in the same HWinfo session shown in the second image showing the total time of nearly 4 hours. I still can't run without WHEA @ 1967 or 2000 Fclk but 1933 seems rock steady. It's unfortunate the faster speeds aren't error free because they sure do have higher bandwidth and lower latency...


----------



## Akex

obscurehifi said:


> I thought I would give your suggested test methods a shot tonight. I'm new to running these tests, so I'm learning every day. What are some other suggested methods for testing for stability?
> 
> This is with the same 3867-16 setting I posted several days ago except I changed the AddrCmdDrvStr from 24 to 20 ohm because it helped higher frequencies post (as did a higher ProcODT of 53), so I decided to see how it worked at 1933. The below two images were done in the same HWinfo session shown in the second image showing the total time of nearly 4 hours. I still can't run without WHEA @ 1967 or 2000 Fclk but 1933 seems rock steady. It's unfortunate the faster speeds aren't error free because they sure do have higher bandwidth and lower latency...
> View attachment 2476060
> 
> 
> View attachment 2476061


For the RAM once the adjustment is done, I do at least 1usmus_v3 80cycles and AntaExtreme 25cycles. Once I have finished all the RAM settings I run a DRAM calculator for 24 hours minimum so I never have to worry about the RAM again.

For WHEAs, do an OCCT / AVX2 / Large Data for at least 2 hours so as to have no doubts afterwards.
Be careful with SSE mode, some Ryzen 5000 are not originally stable with SSE. If you are optimizing with Curve Optimizer, do for each core individually an OCCT / 1T / SSE / Large Data and in the windows task manager assigned the affinity on the core under test, example core#0 = UC0 / core#1 = UC2 / core#2 = UC4 etc

If you need I have created a table for the CO test :
For 5600X-5800X-5900X-5950X > https://cdn.discordapp.com/attachme...bleau_Akex_-_5600X-5800X_Curve_Optimizer.docx
And part2 5900X-5950X > https://cdn.discordapp.com/attachme...bleau_Akex_-_5900X-5950X_Curve_Optimizer.docx


----------



## ManniX-ITA

Dreamic said:


> There's a new FCLK record on the Zen Sheet that's apparently WHEA free, 2133/4267
> 
> 
> 
> 
> 
> 
> 
> 
> Crazy lucky? 1.6vDIMM though, my 3080 would overheat it, would have to tone it down myself for 24/7.
> If people are already pulling this off I gotta be able to get 1933 4x8GB with no WHEA someday right? If 1900 FCLK no post AGESA bug is never going to be fixed. I want 1900 minimum


I can do a perfect WHEA error free FCLK 2067 with memory in-sync as well.
Problem is that works only with the benching Windows install which is super clean and boots from USB.
As soon I boot from the main bloated Windows install from the M.2 SSD then I get tons of WHEA errors.


----------



## Alyjen

Dreamic said:


> There's a new FCLK record on the Zen Sheet that's apparently WHEA free, 2133/4267
> 
> 
> 
> 
> 
> 
> 
> 
> Crazy lucky? 1.6vDIMM though, my 3080 would overheat it, would have to tone it down myself for 24/7.
> If people are already pulling this off I gotta be able to get 1933 4x8GB with no WHEA someday right? If 1900 FCLK no post AGESA bug is never going to be fixed. I want 1900 minimum


I can run higher FCLK than 1766/3733 without WHEA, and it'll do SuperPI calculations, big parts of Y-Cruncher, or few minutes of OCCT/Prime, but only few, or even if it's stable longer, then during regular use these WHEAs will appear, one every few days but it's not something I consider WHEA free. 
Don't say it's the same case, but provided evidence is hardly enough, still impressive results.


----------



## Akex

I think the ranking is completely obsolete in the sense that it would take at least an OCCT / Prime95 screen of at least one hour to be sure that the WHEA do not appear, or at least even if it is every two days it is already viable to make a classification. Anyone, me the first can post 4000+ without WHEA with the bench Anta or 1usmus, however I do not do more than half a day without WHEA.

Validated with SuperPI it's just nonsense, it's mono core and more if I'm not mistaken ...

I think we should start on a new basis, redo the ranking for Ryzen 5000. People who are really stable, will have no problem giving their score and then I think that everyone keeps the profiles recorded even if it is only for benchmarking


----------



## VPII

Akex said:


> I think the ranking is completely obsolete in the sense that it would take at least an OCCT / Prime95 screen of at least one hour to be sure that the WHEA do not appear, or at least even if it is every two days it is already viable to make a classification. Anyone, me the first can post 4000+ without WHEA with the bench Anta or 1usmus, however I do not do more than half a day without WHEA.
> 
> Validated with SuperPI it's just nonsense, it's mono core and more if I'm not mistaken ...
> 
> I think we should start on a new basis, redo the ranking for Ryzen 5000. People who are really stable, will have no problem giving their score and then I think that everyone keeps the profiles recorded even if it is only for benchmarking


If I may ask, where do you see the ranking. I did not even know there was a ranking? I'm busy testing my memory 3800 with 1900 IF using Karhu Memtest. TM5 keeps changing when I use it, for some reason where it runs 15 instances it changes to only use 5. I also don't know where to download it. My reason for testing the memory now is ambient temps which is a little cooler today for when I test the memory temps will go into the 40c range pretty quickly.


----------



## ManniX-ITA

VPII said:


> If I may ask, where do you see the ranking. I did not even know there was a ranking? I'm busy testing my memory 3800 with 1900 IF using Karhu Memtest. TM5 keeps changing when I use it, for some reason where it runs 15 instances it changes to only use 5. I also don't know where to download it. My reason for testing the memory now is ambient temps which is a little cooler today for when I test the memory temps will go into the 40c range pretty quickly.


Ranking:








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com





TM5:








NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking...


OK I'm officially throwing in the towel. I'm done, no matter what I try I cannot overclock my G.Skill F4-3200C14 RAM on my CH6. Nothing works it's just not doable without throwing a ton of V at it and then it gets to hot when gaming and fails. I give up and just stick to 3200. Try new BIOS...




www.overclock.net


----------



## VPII

ManniX-ITA said:


> Ranking:
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> TM5:
> 
> 
> 
> 
> 
> 
> 
> 
> NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking...
> 
> 
> OK I'm officially throwing in the towel. I'm done, no matter what I try I cannot overclock my G.Skill F4-3200C14 RAM on my CH6. Nothing works it's just not doable without throwing a ton of V at it and then it gets to hot when gaming and fails. I give up and just stick to 3200. Try new BIOS...
> 
> 
> 
> 
> www.overclock.net


Thank you. I thought I'll add this, I finally found a means by which the get my latency lower than 59.8 and was surprised when I got it using a different power plan. But I took a screenshot while it is running already past 10 000% Karhu but to see that there is no WHEA errors. 2000 IF will not start for me and 1933 throw WHEA errors like it is going out of fashion.


----------



## ManniX-ITA

VPII said:


> Thank you. I thought I'll add this, I finally found a means by which the get my latency lower than 59.8 and was surprised when I got it using a different power plan. But I took a screenshot while it is running already past 10 000% Karhu but to see that there is no WHEA errors. 2000 IF will not start for me and 1933 throw WHEA errors like it is going out of fashion.
> 
> View attachment 2476082


Maybe you could improve a bit raising the VSOC; only 30mV from VDDG is not enough.
Should be at least 50-60mV higher, better a bit more for performances.
I'd set it at 1100mV which you should see as 1083mV in ZenTimings.
For best and stable latency use the Ultimate Performance power plan.


----------



## VPII

ManniX-ITA said:


> Maybe you could improve a bit raising the VSOC; only 30mV from VDDG is not enough.
> Should be at least 50-60mV higher, better a bit more for performances.
> I'd set it at 1100mV which you should see as 1083mV in ZenTimings.
> For best and stable latency use the Ultimate Performance power plan.


Thank you for the advice my good Sir.... I really appreciate it. Just waiting to reach 12000 to 15000% Karhu then I'll play with those.


----------



## MikeS3000

Akex said:


> For the RAM once the adjustment is done, I do at least 1usmus_v3 80cycles and AntaExtreme 25cycles. Once I have finished all the RAM settings I run a DRAM calculator for 24 hours minimum so I never have to worry about the RAM again.
> 
> For WHEAs, do an OCCT / AVX2 / Large Data for at least 2 hours so as to have no doubts afterwards.
> Be careful with SSE mode, some Ryzen 5000 are not originally stable with SSE. If you are optimizing with Curve Optimizer, do for each core individually an OCCT / 1T / SSE / Large Data and in the windows task manager assigned the affinity on the core under test, example core#0 = UC0 / core#1 = UC2 / core#2 = UC4 etc
> 
> If you need I have created a table for the CO test :
> For 5600X-5800X-5900X-5950X > https://cdn.discordapp.com/attachme...bleau_Akex_-_5600X-5800X_Curve_Optimizer.docx
> And part2 5900X-5950X > https://cdn.discordapp.com/attachme...bleau_Akex_-_5900X-5950X_Curve_Optimizer.docx


So you are the first person who has mentioned failing SSE tests. This is exactly what happens to my 5900x at stock. It fails Prime95 and OCCT on just my best core using SSE tests and one thread while isolating that core. Usually it is stable running AVX or AVX2 at the same settings which doesn't make much sense unless SSE being a lighter workload will cause higher boost frequency than AVX therefore the errors show.


----------



## VPII

ManniX-ITA said:


> Maybe you could improve a bit raising the VSOC; only 30mV from VDDG is not enough.
> Should be at least 50-60mV higher, better a bit more for performances.
> I'd set it at 1100mV which you should see as 1083mV in ZenTimings.
> For best and stable latency use the Ultimate Performance power plan.


Interesting I see....


----------



## ManniX-ITA

VPII said:


> Interesting I see....
> 
> View attachment 2476090


You should also see a small bump up in some benchmarks; if I'm not wrong CPU-z and some GB5 tests.
Others will not be affected, depends.


----------



## VPII

ManniX-ITA said:


> You should also see a small bump up in some benchmarks; if I'm not wrong CPU-z and some GB5 tests.
> Others will not be affected, depends.


Thank you kindly...


----------



## Sphex_

Has anyone run into the weird behavior where simply lowering primary timings by 1 will lead to the computer not POSTing and having the CPU debug light come on?

Currently running my F4-4266C19-16GTZKW kit at 3800 MHz 16-15-15-15-32-48-288-1T @1.4V. If I lower tCL to 15, save and exit, the lights and fans stay on but nothing happens. The CPU debug light illuminates and requires a manual power down and CMOS clear to properly boot again. No memory training, nothing, the PC simply just doesn't boot. Not sure if this is a motherboard specific issue or if my kit just really doesn't like going below a tCL of 16. Motherboard in my sig, running the latest 1.1.9.0 AGESA BIOS.


----------



## ManniX-ITA

Sphex_ said:


> Has anyone run into the weird behavior where simply lowering primary timings by 1 will lead to the computer not POSTing and having the CPU debug light come on?
> 
> Currently running my F4-4266C19-16GTZKW kit at 3800 MHz 16-15-15-15-32-48-288-1T @1.4V. If I lower tCL to 15, save and exit, the lights and fans stay on but nothing happens. The CPU debug light illuminates and requires a manual power down and CMOS clear to properly boot again. No memory training, nothing, the PC simply just doesn't boot. Not sure if this is a motherboard specific issue or if my kit just really doesn't like going below a tCL of 16. Motherboard in my sig, running the latest 1.1.9.0 AGESA BIOS.


I'd be really surprised if you could run tCL [email protected] at 1.4V.
Try setting 1.55V to see if it's a VDIMM issue, if so scale down till it still works.


----------



## obscurehifi

I have noticed this on my F4-3600C14 kit as well when running higher frequencies. It's pretty much the same behavior where it requires a physical reset of the bios 3402 (1.2.0.0) and doesn't do the triple boot thing. Tcl 15 shows this behavior even if GDM is disabled which I believe is needed for odd numbered Tcl to about it rounding to the next higher even number but could be mistaken. I am able to run at 16 and 18 at 3800, 3867, and 18 at 4000 but 4000 isn't stable. I've tested lots of different combinations and most do the triple boot behavior and some won't boot. I'm not always sure why the difference but lowering Tcl one step or more beyond stable seems to be the reason I think. That all said, since then I found that raising ProcODT as well as lowering AddrCmdDrvStr seemed to make some of my later settings at higher frequencies post, so maybe that would help this behavior. I'm not sure I've tried 15 Tcl since making that finding. 

Sent from my SM-G973U using Tapatalk


----------



## Not a redditor

KedarWolf said:


> Good old HCI.
> 
> View attachment 2476034
> 
> 
> View attachment 2476035


 Can you post a bios ss for this setup ? ^_^


----------



## halcyonon

For those if you with Asus boards, what are you setting VDDSOC LLC to? And VDDSOC Phase Control? I understand LLC preventing droop which is valuable, but have you seen any benefit from modifying phase control from auto?


----------



## Pictus

halcyonon said:


> For those if you with Asus boards, what are you setting VDDSOC LLC to? And VDDSOC Phase Control? I understand LLC preventing droop which is valuable, but have you seen any benefit from modifying phase control from auto?



VDDCR SOC Load Line Calibration [Level 1]
VDDCR SOC Current Capability [100%]
VDDCR SOC Switching Frequency [350]
VDDCR SOC Power Phase Control [Extreme] (extreme = all phases stay ON)

VDDCR SOC Voltage Override [1.08125]
DRAM Voltage [1.37500]
VDDG CCD Voltage Control [0.890]
VDDG IOD Voltage Control [1.040]
CLDO VDDP voltage [0.890]


----------



## halcyonon

Pictus said:


> VDDCR SOC Load Line Calibration [Level 1]
> VDDCR SOC Current Capability [100%]
> VDDCR SOC Switching Frequency [350]
> VDDCR SOC Power Phase Control [Extreme] (extreme = all phases stay ON)
> 
> VDDCR SOC Voltage Override [1.08125]
> DRAM Voltage [1.37500]
> VDDG CCD Voltage Control [0.890]
> VDDG IOD Voltage Control [1.040]
> CLDO VDDP voltage [0.890]


VDDCR SOC Load Line Calibration [Level 1] 
* isn't this Maximizing droop? I thought lower number == more droop

VDDCR SOC Switching Frequency [350]
* What is accomplished by changing this from default? IE how should I think about this number?


----------



## Hale59

KedarWolf said:


> This with a PBO overclock, but I'm running a 3950x, not 5000 series.


Thanks for the input.

Here is my CL16 results with 1 stick of RAM.


----------



## Pictus

halcyonon said:


> VDDCR SOC Load Line Calibration [Level 1]
> * isn't this Maximizing droop? I thought lower number == more droop


Yes, Level 1 is weak LL and results in higher vdroop, but less voltage spikes.
For CPU I keep it L2, I think the AUTO = L3



> VDDCR SOC Switching Frequency [350]
> * What is accomplished by changing this from default? IE how should I think about this number?


Yes, 350 is the max here, I guess yours goes to 500.


----------



## PJVol

Sphex_ said:


> If I lower tCL to 15, save and exit, the lights and fans stay on but nothing happens.


1.4v seems too low. My kit needs 1.44-1.45 Vdimm for CL15. Other timings and voltages:


----------



## KedarWolf

Not a redditor said:


> Can you post a bios ss for this setup ? ^_^


This is with an unlocked BIOS only works with 3000 series CPUs. Let me know if you need a link to it.



Spoiler: BIOS Screenshots Below, Click On Spoiler


----------



## Akex

MikeS3000 said:


> So you are the first person who has mentioned failing SSE tests. This is exactly what happens to my 5900x at stock. It fails Prime95 and OCCT on just my best core using SSE tests and one thread while isolating that core. Usually it is stable running AVX or AVX2 at the same settings which doesn't make much sense unless SSE being a lighter workload will cause higher boost frequency than AVX therefore the errors show.


Yes I have been warning people for several months, but it seems that not many people are worried. People are more concerned with making big scores at the expense of their stability. You just have to see here AMD 5800X AMD Curve Optimizer Boost set up to 5050Mhz...

I am French, and with us on the HFR forum, people have understood when I explained the situation and made do with it today. Just like seeing people putting CO -5 on the best cores and -15 or -20 on the bad ones is stupid, each core does not have the same voltage / frequency curve, too. is stupid of them. But when you do an SSE / 1T test you realize that finally my curve is completely bad and has to be redone. For my part as an example with a 5800X I am at -16 / -15 / + 5 / -30 / -10 / -30 / -30 / -17 and this is the only way to be stable at 2000% regardless the instruction, AVX or SSE. Imagine that I could do like the others, put -5 on my best cores and -20 on the bad ones, I would absolutely not be stable at all ... Besides, my best core asks me for +5 and the second -15.

We have set up a test protocol that seems viable to see stability with the curve optimizer, I have proposed a base and the members of HFR have contributed to improve it thereafter. If you need to let me know.


----------



## Sphex_

PJVol said:


> 1.4v seems too low. My kit needs 1.44-1.45 Vdimm for CL15. Other timings and voltages:
> View attachment 2476188


Tried 1.45V and the same result. My guess is it either needs a ton more voltage or my kit just isn't up to the task. Patiently awaiting MSI to fix their BIOSes so I can get 4000+ MHz without WHEAs.


----------



## PJVol

Sphex_ said:


> Tried 1.45V and the same result. My guess is it either needs a ton more voltage or my kit just isn't up to the task


They seem to be a new Hynix chips, that I have no experience with, sorry.


----------



## VPII

Akex said:


> Yes I have been warning people for several months, but it seems that not many people are worried. People are more concerned with making big scores at the expense of their stability. You just have to see here AMD 5800X AMD Curve Optimizer Boost set up to 5050Mhz...
> 
> I am French, and with us on the HFR forum, people have understood when I explained the situation and made do with it today. Just like seeing people putting CO -5 on the best cores and -15 or -20 on the bad ones is stupid, each core does not have the same voltage / frequency curve, too. is stupid of them. But when you do an SSE / 1T test you realize that finally my curve is completely bad and has to be redone. For my part as an example with a 5800X I am at -16 / -15 / + 5 / -30 / -10 / -30 / -30 / -17 and this is the only way to be stable at 2000% regardless the instruction, AVX or SSE. Imagine that I could do like the others, put -5 on my best cores and -20 on the bad ones, I would absolutely not be stable at all ... Besides, my best core asks me for +5 and the second -15.
> 
> We have set up a test protocol that seems viable to see stability with the curve optimizer, I have proposed a base and the members of HFR have contributed to improve it thereafter. If you need to let me know.


I have to say, I am with you on this. I was able to do my curve -30 on all cores and it was bench stable no issue. When I ran OCCT just normally for stress test it litterally dropped errors after a minute or so. I went down to -15 for all the cores and still errors but after a while. I tested with -10 on all cores and it passed an hour without an issue. I state all cores as I do not have the patience to test each core individually, when I have a setting that works on all cores I'll play with the poorer / worse cores and up their curve a bit. I also tested -12 all cores which also passed so now I am testing -13 and so I will continue.

-30 for all the cores is fine for bench runs but not fine when using it for work.


----------



## Not a redditor

KedarWolf said:


> This is with an unlocked BIOS only works with 3000 series CPUs. Let me know if you need a link to it.
> 
> 
> 
> Spoiler: BIOS Screenshots Below, Click On Spoiler


i did try ur settings , pc doesnt start, but i tryed a older version of ur ram oc and it works , i only need more volts on the ram like 0.050 something like that 

i got the 3200cl14 32gb and x570 unify


----------



## KedarWolf

Not a redditor said:


> i did try ur settings , pc doesnt start, but i tryed a older version of ur ram oc and it works , i only need more volts on the ram like 0.050 something like that
> 
> i got the 3200cl14 32gb and x570 unify


Checked in the Unify thread, I posted the unlocked A42 BIOS, if you're using a 3000 series CPU absolute best BIOS. If 5000 series, I dunno, this BIOS will not work with them.


----------



## Not a redditor

KedarWolf said:


> Checked in the Unify thread, I posted the unlocked A42 BIOS, if you're using a 3000 series CPU absolute best BIOS. If 5000 series, I dunno, this BIOS will not work with them.


in a few days bios a86 will be realease for unify , any ideas on how it will perform vs the a42 ?


----------



## Sphex_

PJVol said:


> They seem to be a new Hynix chips, that I have no experience with, sorry.


Taiphoon reads them as good ol' Samsung B-Die.


----------



## KedarWolf

Not a redditor said:


> in a few days bios a86 will be realease for unify , any ideas on how it will perform vs the a42 ?


On 3000 series CPUs every new BIOS I tried including the A86 performs worse. I couldn't even get it stable at 3800 with near the same timings.


----------



## TeslaHUN

I have 4x8gb patriot viper 3400 cl16ram. On xmp profile it cant boot. Modules looks identical but they are different chips . 2 Samsung b-die and 2 hynix C-die. Soc voltage is 0.99V on auto setting. Shall I overvolt it a little ?


----------



## thomasck

Hi guys, all good? I've been using these settings for a long while, no problems at all. I wonder if there something else to improve?
The modules are 2x8GB HyperX 4000 CL19 Bdie.


----------



## Jaeyger

TeslaHUN said:


> I have 4x8gb patriot viper 3400 cl16ram. On xmp profile it cant boot. Modules looks identical but they are different chips . 2 Samsung b-die and 2 hynix C-die. Soc voltage is 0.99V on auto setting. Shall I overvolt it a little ?


SOC voltage should be about 1.1V. Set that and set VDIMM to about 1.45V. If it doesn't boot, raise VDIMM until it does. If it does boot at 1.45, lower VDIMM until it doesn't then bump back up to when it did.


----------



## KedarWolf

Got my 5950x last night!!

Can do 1933 and 1966 as well WHEA free, but latency goes up 5ns with very little performance gain. 

As you can see, single-core boost is good.


----------



## craxton

well hello all, been quite the minute since ive last been on. had a few personal issues arise blah blah, anyone tried the new 1.2 agesa code for msi b550 boards? gaming edge specifically?


----------



## Sphex_

thomasck said:


> Hi guys, all good? I've been using these settings for a long while, no problems at all. I wonder if there something else to improve?
> The modules are 2x8GB HyperX 4000 CL19 Bdie.


That's honestly pretty damn good. I don't see any glaring things there that you should approve upon. Nicely done!
May I ask what voltage you're running?


----------



## thomasck

@Sphex_ Thank you! ATM I'm at 1.455V, due to upping ClkDrvStr from 40 to 60 allowed me to reduce the voltage from 1.475V somehow. I can lower tRFC to around 265, but I did not see any improvements, maybe tRCDWR too but I did not try.


----------



## Not a redditor

KedarWolf said:


> Got my 5950x last night!!
> 
> Can do 1933 and 1966 as well WHEA free, but latency goes up 5ns with very little performance gain.
> 
> As you can see, single-core boost is good.
> 
> View attachment 2476402


congrats on the 5950x, ill be missing you on the 3950x =[


----------



## ManniX-ITA

KedarWolf said:


> Got my 5950x last night!!
> 
> Can do 1933 and 1966 as well WHEA free, but latency goes up 5ns with very little performance gain.
> 
> As you can see, single-core boost is good.
> 
> View attachment 2476402


Finally! Congratz 

You may probably go down to 1.16V VSOC and IOD 1060mV with those settings.


----------



## Hale59

KedarWolf said:


> Got my 5950x last night!!
> 
> Can do 1933 and 1966 as well WHEA free, but latency goes up 5ns with very little performance gain.
> 
> As you can see, single-core boost is good.
> 
> View attachment 2476402


Congrats.
But as far ram oc is concerned, you walked back in time.

Glad I held the urge to buy the new 5000s. I will wait until they mature, if they do at all.
Having fun with my little 3000.


----------



## Shoey Peachew

I was able to lower my voltage from from 1.51v to 1.49v by increasing ClkDrvStr from 24 to 30 ohm .


----------



## Akex

It's impossible in 22min to see if you are stable or not ....


----------



## Shoey Peachew

Akex said:


> It's impossible in 22min to see if you are stable or not ....


I know that was just a quick test. I did this test at 1.51v. I'll do a more thorough test at 1.49v, but now I want to try hitting 4000MHz.


----------



## Pictus

Hale59 said:


> Congrats.
> But as far ram oc is concerned, you walked back in time.
> 
> Glad I helg the urge to buy the new 5000s. I will wait until they mature, if they do at all.
> Having fun with my little 3000.


I had one 3600 with static 4.2Mhz OC and changed to 5600X, for my Photoshop stuff the 5600X it is much better...
But I was very satisfied with the 3600.


----------



## Comalive

craxton said:


> well hello all, been quite the minute since ive last been on. had a few personal issues arise blah blah, anyone tried the new 1.2 agesa code for msi b550 boards? gaming edge specifically?


fclk 1900 still doesn't boot and I seem to get the same amount of WHEA 19 errors as previously (after doing short tests only so far)


----------



## KedarWolf

KedarWolf said:


> This with a PBO overclock, but I'm running a 3950x, not 5000 series.


My 5950x is soooo much faster.


----------



## Hale59

KedarWolf said:


> My 5950x is soooo much faster.


If your ram is so limited for a 5000, your CPU is a dud. I would suggest to buy a new one, just saying.


----------



## KedarWolf

Hale59 said:


> If your ram is so limited for a 5000, your CPU is a dud. I would suggest to buy a new one, just saying.


I know the IMC is average, but I don't have the disposable income to just buy another CPU. 

I CAN go higher TM5 stable, but not without WHEA errors. I see peeps showing their TM5 but no OCCT or anything seeing if they are getting WHEA errors, so I don't put much stock in those posts.


----------



## Hale59

KedarWolf said:


> I know the IMC is average, but I don't have the disposable income to just buy another CPU.
> 
> I CAN go higher TM5 stable, but not without WHEA errors. I see peeps showing their TM5 but no OCCT or anything seeing if they are getting WHEA errors, so I don't put much stock in those posts.


Sure, but there is a great demand for those CPUs. Rather be patient, sell it, and make another order. You will end up get a better one. No need to rush. Sometime running after the cutting edge, you get a cutting edge dud.
But anyway, enjoy it.

Anyway, like your CPU, look at this one:


----------



## obogobo

I just made a ticket with Gigabyte regarding the 1900MHz specific Infinity Fabric bug. We'll see what they say! As 1866 and 1933 run completely fine... it must be an AGESA issue so hopefully they can put in a ticket with AMD or something.

edit: if everyone else with this issue could do the same, we might make some progress on getting 1900 IF to POST more easily


----------



## ManniX-ITA

KedarWolf said:


> I know the IMC is average, but I don't have the disposable income to just buy another CPU.
> 
> I CAN go higher TM5 stable, but not without WHEA errors. I see peeps showing their TM5 but no OCCT or anything seeing if they are getting WHEA errors, so I don't put much stock in those posts.


It may easily be a BIOS limitation instead of IMC.
Wait to see what you can do with the Unify-X.
Anyway for me it was pointless to go over 1900 so far; couldn't get rid of WHEA.


----------



## madjacko

Hi,

i'm completely new to overclocking and have just built a new PC

5800x, x570 gaming carbon wifi, 5700XT EVOKE, G.Skill F4-3600C16-16GTZNC RAM








i have tried to follow the ryzen calculator but i just keep getting errors when booting and have to resort back to XMP










is there anything you guys can suggest looking at these settings?


----------



## BluePaint

Your RAM is probably not b die since u have stock 3600 16 19 19 39 timings
Gskill 3600 b die is 16 16 i think


----------



## ManniX-ITA

BluePaint said:


> Your RAM is probably not b die since u have stock 3600 16 19 19 39 timings
> Gskill 3600 b die is 16 16 i think


Indeed it's a Hynix DJR, select CJR in DRAM Calc.

To check if it's a B-die usually this works:






B-Die Finder


Find Samsung B-Die DDR 4 memory kits on Amazon, Newegg and many more.




benzhaomin.github.io





Had some timings saved.
Be careful with tRFC at around 480 starts to be unstable, you need 1.40V - 1.45V:


----------



## madjacko

BluePaint said:


> Your RAM is probably not b die since u have stock 3600 16 19 19 39 timings
> Gskill 3600 b die is 16 16 i think


ah ok thank you both for your suggestions









do these timings look better?


----------



## ManniX-ITA

madjacko said:


> ah ok thank you both for your suggestions
> View attachment 2476725
> 
> 
> do these timings look better?


You can try but tCL 14 never worked for me and tRFC 471 was unstable.


----------



## madjacko

ManniX-ITA said:


> You can try but tCL 14 never worked for me and tRFC 471 was unstable.


what values would you go for?
tcl 15-16 and trfc 480?


----------



## ManniX-ITA

madjacko said:


> what values would you go for?
> tcl 15-16 and trfc 480?


I've posted the ZenTimings screenshots

The first one with tRFC 480 is better, the 2nd more safe
I was using the first one with tRFC 480 (or something very similar)


----------



## madjacko

ManniX-ITA said:


> I've posted the ZenTimings screenshots
> 
> The first one with tRFC 480 is better, the 2nd more safe
> I was using the first one with tRFC 480 (or something very similar)


sorry just seen them.

i want a more stable so will try the second image.

do you think there will be a big performance improvement compared to XMP?


----------



## ManniX-ITA

madjacko said:


> sorry just seen them.
> 
> i want a more stable so will try the second image.
> 
> do you think there will be a big performance improvement compared to XMP?


Definitely yes!


----------



## madjacko

ManniX-ITA said:


> Definitely yes!


thank you i will give them a go!


----------



## obscurehifi

madjacko said:


> ah ok thank you both for your suggestions
> View attachment 2476725
> 
> 
> do these timings look better?


Out of curiosity, why are you using "manual" DRAM PCB Revision? Did you have an XMP profile that you imported? That might be holding you back. I compared what you show in your image to the A3/A2/B2 revision safe preset, and there are quite a few differences that I would imagine are being restrained to the imported XMP, or at least the manually entered 10 cells in the lower left. Just an observation. The most notable difference is a tCL 16 vs 14.


----------



## madjacko

obscurehifi said:


> Out of curiosity, why are you using "manual" DRAM PCB Revision? Did you have an XMP profile that you imported? That might be holding you back. I compared what you show in your image to the A3/A2/B2 revision safe preset, and there are quite a few differences that I would imagine are being restrained to the imported XMP, or at least the manually entered 10 cells in the lower left. Just an observation. The most notable difference is a tCL 16 vs 14.


i was just following a video tutorial to be honest.

i have changed it to what you said:

















are these any better?


----------



## obscurehifi

madjacko said:


> i was just following a video tutorial to be honest.
> 
> i have changed it to what you said:
> View attachment 2476762
> 
> View attachment 2476763
> 
> 
> are these any better?


All memory is dependent upon the silicon lottery, so only your testing can tell for sure. The main thing is that I've noticed that manually entering the XMP profile timings change the suggested timings based on the profile that came with your memory (assuming it was pulled from Typhoon from your memory and not the tutorial). In my limited experience, this seems to work well for calculating timings at the default frequency but don't seem to work well for higher frequencies. I would also think that if the XMP profile in your memory is meant for Intel instead of AMD, then that would really throw things off.

In my case, I actually just tested this and the settings derived from the manual entries worked well for my default frequency (3600) and 3666 but once I got to 3733, I started getting errors with both the safe and fast presets. If I use the numbers that are derived from the A3/A2/B2 revision, I get a stable performance all the way to 3866 using the fast preset.

In the end, you'll just have to do a bunch of testing!


----------



## obscurehifi

madjacko said:


> i was just following a video tutorial to be honest.
> 
> i have changed it to what you said:
> View attachment 2476762
> 
> View attachment 2476763
> 
> 
> are these any better?


Also, looks like you have dual rank memory (16GB on each stick based on the second 16 in the stick part number from your zen timings above) so you should change the Memory Rank to 2 in your settings (currently 1 in your images). That will change most of the settings in the two lower right boxes that will help your system post, and of course with stability.


----------



## Not a redditor

Is Techpowerup Memtest64 good for checking stability? how much time must pass for a stable ram oc ?


----------



## Akex

Not a redditor said:


> Is Techpowerup Memtest64 good for checking stability? how much time must pass for a stable ram oc ?











Memory Testing with TestMem5 TM5 with custom configs


Hello everybody I am just making a very light tutorial with a collection of custom config files and a DOWNLOAD LINK for TM5 v0.12 anta777 absolut config *Official* Intel DDR4 24/7 Memory Stability Thread None of the work is mine but it seems like a pretty good and fast testing app




www.overclock.net


----------



## KedarWolf

The below is OCCT WHEA free and no random reboots. If I put it on HWBot it would be #2 Cinebench R20 for someone with an AIO.


----------



## obogobo

1867 FCLK is the place to be it seems, same for me on 5900X


----------



## obscurehifi

obogobo said:


> 1867 FCLK is the place to be it seems, same for me on 5900X


I'm really curious what the limiting factor is. For me the place to be to 1933 and it seems to work for others too. Others it's 1800 or 1867 or 1733. What gives I wonder? Doesn't seem to have a common thread. Not sure if it's finding just the perfect combination of hardware, bios, AGESA, OS, or what. 

Sent from my SM-G973U using Tapatalk


----------



## heptilion

@KedarWolf I'm using the same kit as you have and managed to run it at 3800 but at cl16. cant seem to drop trfc or main timings. tried upping ram voltage up to 1.53v but not go.

I tried going up to 3933 which gave me whea errors and bios was lagging.

passed 1 hour of occt large avx on below timings and voltage as well.


----------



## domdtxdissar

domdtxdissar said:


> One last hurrah for bios 3003 before i update to a bios with AMD AM4 AGESA V2 PI 1.2.0.0 and support for Nvidia smart access memory.
> Cold air benching with EK custom waterloop+TechN Zen3 waterblock
> Curve optimizer = -30 allcore
> Stable in everything i throw at it, and no WHEA errors.
> 
> 
> 
> 
> 
> 
> 
> 
> Cinebench r23 multithread = 32229 points
> Cinebench r23 singlethread = 1729 points
> 
> Cinebench r20 multithread = 12441 points
> Cinebench r20 singlethread = 674 points
> 
> Cinebench r15 multithread = 5404 points
> Cinebench r15 multithread = 288 points
> 
> CPU-Z validator @ AMD Ryzen 9 5950X @ 4798.88 MHz - CPU-Z VALIDATOR
> 
> Some Asus realbench + Passmark performancetest numbers @ PassMark Software - Display Baseline ID# 1359214 (This machine is ranked #36 out of 156355 results globally)
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Geekbench 4 @ ASUS System Product Name - Geekbench Browser
> Singlethread = 8215 points
> Multithread = 74733 points
> 
> Geekbench5 @ ASUS System Product Name - Geekbench Browser
> Singlethread = 1844 points
> Multithread = 20054 points
> 
> Some heavy IBT high+very high and Y-Cruncher numbers:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Did also run a full sweep of all 3dmarks, but i will post that in one other thread
> 
> 
> 
> Spoiler: Bios dump
> 
> 
> 
> [2021/01/20 16:26:21]
> Ai Overclock Tuner [Manual]
> BCLK Frequency [100.0000]
> Memory Frequency [DDR4-3800MHz]
> FCLK Frequency [1900MHz]
> Core Performance Boost [Enabled]
> CPU Core Ratio [Auto]
> Core VID [Auto]
> CCX0 Ratio [Auto]
> CCX0 Ratio [Auto]
> TPU [Keep Current Settings]
> Performance Bias [Auto]
> PBO Fmax Enhancer [Auto]
> Precision Boost Overdrive [Manual]
> PPT Limit [300]
> TDC Limit [235]
> EDC Limit [245]
> Precision Boost Overdrive Scalar [Manual]
> Customized Precision Boost Overdrive Scalar [4X]
> Max CPU Boost Clock Override [50]
> Platform Thermal Throttle Limit [Auto]
> DRAM CAS# Latency [14]
> Trcdrd [15]
> Trcdwr [8]
> DRAM RAS# PRE Time [12]
> DRAM RAS# ACT Time [24]
> Trc [36]
> TrrdS [4]
> TrrdL [4]
> Tfaw [16]
> TwtrS [4]
> TwtrL [10]
> Twr [12]
> Trcpage [Auto]
> TrdrdScl [2]
> TwrwrScl [2]
> Trfc [252]
> Trfc2 [187]
> Trfc4 [115]
> Tcwl [14]
> Trtp [6]
> Trdwr [9]
> Twrrd [2]
> TwrwrSc [1]
> TwrwrSd [6]
> TwrwrDd [6]
> TrdrdSc [1]
> TrdrdSd [5]
> TrdrdDd [5]
> Tcke [Auto]
> ProcODT [40 ohm]
> Cmd2T [1T]
> Gear Down Mode [Enabled]
> Power Down Enable [Disabled]
> RttNom [RZQ/7]
> RttWr [RZQ/3]
> RttPark [RZQ/1]
> MemAddrCmdSetup [Auto]
> MemCsOdtSetup [Auto]
> MemCkeSetup [Auto]
> MemCadBusClkDrvStren [24.0 Ohm]
> MemCadBusAddrCmdDrvStren [20.0 Ohm]
> MemCadBusCsOdtDrvStren [24.0 Ohm]
> MemCadBusCkeDrvStren [24.0 Ohm]
> Mem Over Clock Fail Count [Auto]
> Voltage Monitor [Die Sense]
> CPU Load-line Calibration [Level 3]
> CPU Current Capability [140%]
> CPU VRM Switching Frequency [Manual]
> Fixed CPU VRM Switching Frequency(KHz) [500]
> CPU Power Duty Control [T.Probe]
> CPU Power Phase Control [Extreme]
> CPU Power Thermal Control [120]
> VDDSOC Load-line Calibration [Level 3]
> VDDSOC Switching Frequency [Auto]
> VDDSOC Phase Control [Extreme]
> DRAM Current Capability [130%]
> DRAM Power Phase Control [Extreme]
> DRAM Switching Frequency [Auto]
> CPU Core Current Telemetry [Auto]
> CPU SOC Current Telemetry [Auto]
> Force OC Mode Disable [Disabled]
> SB Clock Spread Spectrum [Auto]
> VTTDDR Voltage [Auto]
> VPP_MEM Voltage [Auto]
> DRAM CTRL REF Voltage on CHA [Auto]
> DRAM CTRL REF Voltage on CHB [Auto]
> VDDP Voltage [Auto]
> 1.8V Standby Voltage [Auto]
> CPU 3.3v AUX [Auto]
> 1.2V SB Voltage [Auto]
> DRAM R1 Tune [Auto]
> DRAM R2 Tune [Auto]
> DRAM R3 Tune [Auto]
> DRAM R4 Tune [Auto]
> PCIE Tune R1 [Auto]
> PCIE Tune R2 [Auto]
> PCIE Tune R3 [Auto]
> PLL Tune R1 [Auto]
> PLL reference voltage [Auto]
> T Offset [Auto]
> Sense MI Skew [Auto]
> Sense MI Offset [Auto]
> Promontory presence [Auto]
> Clock Amplitude [Auto]
> CPU Core Voltage [Offset mode]
> 
> Offset Mode Sign [+]
> CPU Core Voltage Offset [0.01250]
> CPU SOC Voltage [Manual]
> - VDDSOC Voltage Override [1.11875]
> DRAM Voltage [1.54500]
> VDDG CCD Voltage Control [0.890]
> VDDG IOD Voltage Control [Auto]
> CLDO VDDP voltage [0.880]
> 1.00V SB Voltage [Auto]
> 1.8V PLL Voltage [Auto]
> TPM Device Selection [Discrete TPM]
> Erase fTPM NV for factory reset [Enabled]
> PSS Support [Enabled]
> PPC Adjustment [PState 0]
> NX Mode [Enabled]
> SVM Mode [Disabled]
> SMT Mode [Auto]
> Core Leveling Mode [Automatic mode]
> CCD Control [Auto]
> SATA Port Enable [Enabled]
> SATA Mode [AHCI]
> NVMe RAID mode [Disabled]
> SMART Self Test [Enabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> HD Audio Controller [Enabled]
> PCIEX16_1 Bandwidth Bifurcation configuration [Auto Mode]
> PCIEX16_2 Bandwidth Bifurcation configuration [Auto Mode]
> When system is in working state [All On]
> Q-Code LED Function [POST Code Only]
> When system is in sleep, hibernate or soft off states [All On]
> Realtek 2.5G LAN Controller [Enabled]
> Realtek PXE OPROM [Disabled]
> Intel LAN Controller [Enabled]
> Intel LAN OPROM [Disabled]
> ASM1074 Controller [Enabled]
> Wi-Fi 6 (802.11ax) Controller [Disabled]
> Bluetooth Controller [Enabled]
> USB power delivery in Soft Off state (S5) [Enabled]
> PCIEX16_1 Mode [Auto]
> PCIEX16_2 Mode [Auto]
> PCIEX1 Mode [Auto]
> PCIEX16_3 Mode [Auto]
> M.2_1 Link Mode [Auto]
> M.2_2 Link Mode [Auto]
> SB Link Mode [Auto]
> ErP Ready [Disabled]
> Restore AC Power Loss [Power Off]
> Power On By PCI-E [Disabled]
> Power On By RTC [Disabled]
> Above 4G Decoding [Enabled]
> Re-Size BAR Support [Auto]
> SR-IOV Support [Disabled]
> Legacy USB Support [Enabled]
> XHCI Hand-off [Enabled]
> Corsair Voyager GTX 0 [Auto]
> USB Device Enable [Enabled]
> U32G2_2 [Enabled]
> U32G2_3 [Enabled]
> U32G2_4 [Enabled]
> U32G1_10 [Enabled]
> U32G1_11 [Enabled]
> USB12 [Enabled]
> USB13 [Enabled]
> U32G2_7 [Enabled]
> U32G2_8 [Enabled]
> U32G2_C9 [Enabled]
> Network Stack [Disabled]
> Device [SATA6G_7: Samsung SSD 850 PRO 1TB]
> CPU Temperature [Monitor]
> CPU Package Temperature [Monitor]
> MotherBoard Temperature [Monitor]
> VRM Temperature [Monitor]
> T_Sensor Temperature [Monitor]
> Water In T Sensor Temperature [Monitor]
> Water Out T Sensor Temperature [Monitor]
> CPU Fan Speed [Monitor]
> CPU Optional Fan Speed [Monitor]
> Chassis Fan 1 Speed [Monitor]
> Chassis Fan 2 Speed [Monitor]
> Chassis Fan 3 Speed [Monitor]
> High Amp Fan Speed [Monitor]
> W_PUMP+ Speed [Monitor]
> AIO PUMP Speed [Monitor]
> PCH Fan Speed [Monitor]
> Flow Rate [Monitor]
> CPU Core Voltage [Monitor]
> 3.3V Voltage [Monitor]
> 5V Voltage [Monitor]
> 12V Voltage [Monitor]
> CPU Fan Q-Fan Control [Auto]
> CPU Fan Step Up [2.1 sec]
> CPU Fan Step Down [0 sec]
> CPU Fan Speed Low Limit [600 RPM]
> CPU Fan Profile [Manual]
> CPU Fan Upper Temperature [70]
> CPU Fan Max. Duty Cycle (%) [100]
> CPU Fan Middle Temperature [50]
> CPU Fan Middle Duty Cycle (%) [50]
> CPU Fan Lower Temperature [30]
> CPU Fan Min Duty Cycle (%) [40]
> Chassis Fan 1 Q-Fan Control [Auto]
> Chassis Fan 1 Q-Fan Source [CPU]
> Chassis Fan 1 Step Up [0 sec]
> Chassis Fan 1 Step Down [0 sec]
> Chassis Fan 1 Speed Low Limit [600 RPM]
> Chassis Fan 1 Profile [Manual]
> Chassis Fan 1 Upper Temperature [70]
> Chassis Fan 1 Max. Duty Cycle (%) [100]
> Chassis Fan 1 Middle Temperature [50]
> Chassis Fan 1 Middle Duty Cycle (%) [65]
> Chassis Fan 1 Lower Temperature [20]
> Chassis Fan 1 Min Duty Cycle (%) [60]
> Chassis Fan 2 Q-Fan Control [Auto]
> Chassis Fan 2 Q-Fan Source [CPU]
> Chassis Fan 2 Step Up [0 sec]
> Chassis Fan 2 Step Down [0 sec]
> Chassis Fan 2 Speed Low Limit [600 RPM]
> Chassis Fan 2 Profile [Manual]
> Chassis Fan 2 Upper Temperature [65]
> Chassis Fan 2 Max. Duty Cycle (%) [100]
> Chassis Fan 2 Middle Temperature [45]
> Chassis Fan 2 Middle Duty Cycle (%) [60]
> Chassis Fan 2 Lower Temperature [40]
> Chassis Fan 2 Min Duty Cycle (%) [60]
> Chassis Fan 3 Q-Fan Control [Auto]
> Chassis Fan 3 Q-Fan Source [CPU]
> Chassis Fan 3 Step Up [0 sec]
> Chassis Fan 3 Step Down [0 sec]
> Chassis Fan 3 Speed Low Limit [600 RPM]
> Chassis Fan 3 Profile [Manual]
> Chassis Fan 3 Upper Temperature [70]
> Chassis Fan 3 Max. Duty Cycle (%) [100]
> Chassis Fan 3 Middle Temperature [45]
> Chassis Fan 3 Middle Duty Cycle (%) [100]
> Chassis Fan 3 Lower Temperature [40]
> Chassis Fan 3 Min Duty Cycle (%) [100]
> High Amp Fan Q-Fan Control [Auto]
> High Amp Fan Q-Fan Source [CPU]
> High Amp Fan Step Up [0 sec]
> High Amp Fan Step Down [0 sec]
> High Amp Fan Speed Low Limit [600 RPM]
> High Amp Fan Profile [Manual]
> High Amp Fan Upper Temperature [70]
> High Amp Fan Max. Duty Cycle (%) [100]
> High Amp Fan Middle Temperature [45]
> High Amp Fan Middle Duty Cycle (%) [70]
> High Amp Fan Lower Temperature [30]
> High Amp Fan Min Duty Cycle (%) [60]
> Water Pump+ Q-Fan Control [Auto]
> Water Pump+ Q-Fan Source [CPU]
> Water Pump+ Upper Temperature [70]
> Water Pump+ Max. Duty Cycle (%) [100]
> Water Pump+ Middle Temperature [50]
> Water Pump+ Middle Duty Cycle (%) [65]
> Water Pump+ Lower Temperature [30]
> Water Pump+ Min Duty Cycle (%) [60]
> AIO Pump Q-Fan Control [Auto]
> AIO Pump Q-Fan Source [CPU]
> AIO Pump Upper Temperature [70]
> AIO Pump Max. Duty Cycle (%) [100]
> AIO Pump Middle Temperature [50]
> AIO Pump Middle Duty Cycle (%) [65]
> AIO Pump Lower Temperature [30]
> AIO Pump Min Duty Cycle (%) [60]
> Above 4GB MMIO Limit [39bit (512GB)]
> Fast Boot [Enabled]
> Next Boot after AC Power Loss [Fast Boot]
> Boot Logo Display [Disabled]
> Bootup NumLock State [On]
> POST Report [5 sec]
> Wait For 'F1' If Error [Enabled]
> Option ROM Messages [Force BIOS]
> Interrupt 19 Capture [Disabled]
> Setup Mode [Advanced Mode]
> Launch CSM [Disabled]
> OS Type [Other OS]
> AMI Native NVMe Driver Support [Enabled]
> Flexkey [Reset]
> Setup Animator [Disabled]
> Load from Profile [5]
> Profile Name [20.01 minus 30]
> Save to Profile [5]
> DIMM Slot Number [DIMM_A1]
> Bus Interface [PCIEX16_1]
> Download & Install ARMOURY CRATE app [Enabled]
> CPU Frequency [0]
> CPU Voltage [0]
> CCD Control [Auto]
> Core control [Auto]
> SMT Control [Auto]
> Overclock [Enabled ]
> Memory Clock Speed [Auto]
> Tcl [Auto]
> Trcdrd [Auto]
> Trcdwr [Auto]
> Trp [Auto]
> Tras [Auto]
> Trc Ctrl [Auto]
> TrrdS [Auto]
> TrrdL [Auto]
> Tfaw Ctrl [Auto]
> TwtrS [Auto]
> TwtrL [Auto]
> Twr Ctrl [Auto]
> Trcpage Ctrl [Auto]
> TrdrdScL Ctrl [Auto]
> TwrwrScL Ctrl [Auto]
> Trfc Ctrl [Auto]
> Trfc2 Ctrl [Auto]
> Trfc4 Ctrl [Auto]
> Tcwl [Auto]
> Trtp [Auto]
> Tcke [Auto]
> Trdwr [Auto]
> Twrrd [Auto]
> TwrwrSc [Auto]
> TwrwrSd [Auto]
> TwrwrDd [Auto]
> TrdrdSc [Auto]
> TrdrdSd [Auto]
> TrdrdDd [Auto]
> ProcODT [Auto]
> Power Down Enable [Auto]
> Cmd2T [Auto]
> Gear Down Mode [Auto]
> CAD Bus Timing User Controls [Auto]
> CAD Bus Drive Strength User Controls [Auto]
> Data Bus Configuration User Controls [Auto]
> Infinity Fabric Frequency and Dividers [Auto]
> ECO Mode [Disable]
> Precision Boost Overdrive [Advanced]
> PBO Limits [Motherboard]
> Precision Boost Overdrive Scalar [Auto]
> Curve Optimizer [Per Core]
> Core 0 Curve Optimizer Sign [Negative]
> Core 0 Curve Optimizer Magnitude [30]
> Core 1 Curve Optimizer Sign [Negative]
> Core 1 Curve Optimizer Magnitude [30]
> Core 2 Curve Optimizer Sign [Negative]
> Core 2 Curve Optimizer Magnitude [30]
> Core 3 Curve Optimizer Sign [Negative]
> Core 3 Curve Optimizer Magnitude [30]
> Core 4 Curve Optimizer Sign [Negative]
> Core 4 Curve Optimizer Magnitude [30]
> Core 5 Curve Optimizer Sign [Negative]
> Core 5 Curve Optimizer Magnitude [30]
> Core 6 Curve Optimizer Sign [Negative]
> Core 6 Curve Optimizer Magnitude [30]
> Core 7 Curve Optimizer Sign [Negative]
> Core 7 Curve Optimizer Magnitude [30]
> Core 8 Curve Optimizer Sign [Negative]
> Core 8 Curve Optimizer Magnitude [30]
> Core 9 Curve Optimizer Sign [Negative]
> Core 9 Curve Optimizer Magnitude [30]
> Core 10 Curve Optimizer Sign [Negative]
> Core 10 Curve Optimizer Magnitude [30]
> Core 11 Curve Optimizer Sign [Negative]
> Core 11 Curve Optimizer Magnitude [30]
> Core 12 Curve Optimizer Sign [Negative]
> Core 12 Curve Optimizer Magnitude [30]
> Core 13 Curve Optimizer Sign [Negative]
> Core 13 Curve Optimizer Magnitude [30]
> Core 14 Curve Optimizer Sign [Negative]
> Core 14 Curve Optimizer Magnitude [30]
> Core 15 Curve Optimizer Sign [Negative]
> Core 15 Curve Optimizer Magnitude [30]
> Max CPU Boost Clock Override [0MHz]
> Platform Thermal Throttle Limit [Auto]
> LN2 Mode [Auto]
> SoC/Uncore OC Mode [Disabled]
> VDDP Voltage Control [Auto]
> VDDG Voltage Control [Auto]
> NUMA nodes per socket [Auto]
> Custom Pstate0 [Auto]
> L1 Stream HW Prefetcher [Auto]
> L2 Stream HW Prefetcher [Auto]
> Core Watchdog Timer Enable [Auto]
> SMEE [Auto]
> Core Performance Boost [Auto]
> Global C-state Control [Disabled]
> Power Supply Idle Control [Typical Current Idle]
> SEV ASID Count [Auto]
> SEV-ES ASID Space Limit Control [Auto]
> Streaming Stores Control [Auto]
> Local APIC Mode [Auto]
> ACPI _CST C1 Declaration [Auto]
> MCA error thresh enable [Auto]
> PPIN Opt-in [Auto]
> Fast Short REP MOVSB [Enabled]
> Enhanced REP MOVSB/STOSB [Enabled]
> RdRand Speedup Disable [Enabled]
> IBS hardware workaround [Auto]
> DRAM scrub time [Auto]
> Poison scrubber control [Auto]
> Redirect scrubber control [Auto]
> Redirect scrubber limit [Auto]
> NUMA nodes per socket [Auto]
> Memory interleaving [Auto]
> Memory interleaving size [Auto]
> 1TB remap [Auto]
> DRAM map inversion [Auto]
> ACPI SRAT L3 Cache As NUMA Domain [Auto]
> ACPI SLIT Distance Control [Auto]
> ACPI SLIT remote relative distance [Auto]
> GMI encryption control [Auto]
> xGMI encryption control [Auto]
> CAKE CRC perf bounds Control [Auto]
> 4-link xGMI max speed [Auto]
> 3-link xGMI max speed [Auto]
> xGMI TXEQ Mode [Auto]
> PcsCG control [Auto]
> Disable DF to external downstream IP SyncFloodPropagation [Auto]
> Disable DF sync flood propagation [Auto]
> CC6 memory region encryption [Auto]
> Memory Clear [Auto]
> Overclock [Enabled]
> Memory Clock Speed [Auto]
> Tcl [Auto]
> Trcdrd [Auto]
> Trcdwr [Auto]
> Trp [Auto]
> Tras [Auto]
> Trc Ctrl [Auto]
> TrrdS [Auto]
> TrrdL [Auto]
> Tfaw Ctrl [Auto]
> TwtrS [Auto]
> TwtrL [Auto]
> Twr Ctrl [Auto]
> Trcpage Ctrl [Auto]
> TrdrdScL Ctrl [Auto]
> TwrwrScL Ctrl [Auto]
> Trfc Ctrl [Auto]
> Trfc2 Ctrl [Auto]
> Trfc4 Ctrl [Auto]
> Tcwl [Auto]
> Trtp [Auto]
> Tcke [Auto]
> Trdwr [Auto]
> Twrrd [Auto]
> TwrwrSc [Auto]
> TwrwrSd [Auto]
> TwrwrDd [Auto]
> TrdrdSc [Auto]
> TrdrdSd [Auto]
> TrdrdDd [Auto]
> ProcODT [Auto]
> Power Down Enable [Auto]
> Disable Burst/Postponed Refresh [Auto]
> DRAM Maximum Activate Count [Auto]
> Cmd2T [Auto]
> Gear Down Mode [Auto]
> CAD Bus Timing User Controls [Auto]
> CAD Bus Drive Strength User Controls [Auto]
> Data Bus Configuration User Controls [Auto]
> Data Poisoning [Auto]
> DRAM Post Package Repair [Default]
> RCD Parity [Auto]
> DRAM Address Command Parity Retry [Auto]
> Write CRC Enable [Auto]
> DRAM Write CRC Enable and Retry Limit [Auto]
> Disable Memory Error Injection [True]
> DRAM ECC Symbol Size [Auto]
> DRAM ECC Enable [Auto]
> DRAM UECC Retry [Auto]
> TSME [Auto]
> Data Scramble [Auto]
> DFE Read Training [Auto]
> FFE Write Training [Auto]
> PMU Pattern Bits Control [Auto]
> MR6VrefDQ Control [Auto]
> CPU Vref Training Seed Control [Auto]
> Chipselect Interleaving [Auto]
> BankGroupSwap [Auto]
> BankGroupSwapAlt [Auto]
> Address Hash Bank [Auto]
> Address Hash CS [Auto]
> Address Hash Rm [Auto]
> SPD Read Optimization [Enabled]
> MBIST Enable [Disabled]
> Pattern Select [PRBS]
> Pattern Length [6]
> Aggressor Channel [1 Aggressor Channel]
> Aggressor Static Lane Control [Disabled]
> Target Static Lane Control [Disabled]
> Worst Case Margin Granularity [Per Chip Select]
> Read Voltage Sweep Step Size [1]
> Read Timing Sweep Step Size [1]
> Write Voltage Sweep Step Size [1]
> Write Timing Sweep Step Size [1]
> IOMMU [Auto]
> Precision Boost Overdrive [Auto]
> Precision Boost Overdrive Scalar [Auto]
> FCLK Frequency [Auto]
> SOC OVERCLOCK VID [0]
> UCLK DIV1 MODE [Auto]
> VDDP Voltage Control [Auto]
> VDDG Voltage Control [Auto]
> SoC/Uncore OC Mode [Auto]
> LN2 Mode [Auto]
> ACS Enable [Auto]
> PCIe ARI Support [Auto]
> PCIe ARI Enumeration [Auto]
> PCIe Ten Bit Tag Support [Auto]
> cTDP Control [Auto]
> EfficiencyModeEn [Auto]
> Package Power Limit Control [Auto]
> APBDIS [Auto]
> DF Cstates [Auto]
> CPPC [Auto]
> CPPC Preferred Cores [Auto]
> NBIO DPM Control [Auto]
> Early Link Speed [Auto]
> Presence Detect Select mode [Auto]
> Preferred IO [Auto]
> CV test [Auto]
> Loopback Mode [Auto]
> Data Link Feature Exchange [Disabled]


So i have finally updated my crosshair viii hero to bios 3204.
No major changes compared to bios 3003 other than i don't need to run with cpu +voltage offset anymore and UBS ports are alittle less buggy with the hp reverb g2 vr headset.

Have seen alot of talk about the OCCT "large data set" stresstest in regards to WHEA errors and how hard it was to run error-free, so i decided to give it a 1 hour run 

















Completed without any errors on my 24/7 settings, which are: (fans on auto)

-30 allcore curve optimizer
4x8gigabyte samsung b-die @ 1900/3800mhz 1:1 with the infinity fabric.
This is my bloaty gaming windows, so latency are alittle on the high side.


----------



## bonet69

Hello, after trying 3 different 5800x cpu i can tell for sure that whea errors coming with high fclk 1900+ are cpu deppendant and they come at the limit of your imc, i couldnt get rid of whea errors in2 cpu over 1900+ fclk but with the third one i can tell for sure no whea errors tested until 2050 fclk (i cant boot with more ram speed using 32gb dual ranked) and probably it could go higher using 2x8gb instead of mine:










I have good IF but cpu oc speeds are average 4.6ghz with 1.32v at 2033 fclk (with higher fclk it needs even more voltage) i am still tweaking vddp and vddg but i get no whea errors no matter what voltages i use, just a little bit performance gains or loses depending of voltages.

Regards


----------



## KedarWolf

I got this WHEA free, and I just checked Event Viewer while watching Twitch and in Discord for about five hours, zero WHEA errors.

My ambient temps are warmer though then a few days ago, I had it uncomfortably cold in my place this winter, so not getting 15-16-8-19-21 1T GDM Enabled 240 tRFC stable any more to be comfortable in my place. 

I can run much higher if I ignore the WHEA errors but my PC OCD will not allow that and I've heard some say they are getting random reboots if they ignore them.


----------



## halcyonon

domdtxdissar said:


> This is my bloaty gaming windows, so latency are alittle on the high side.


54.6ns as "high" latency .. I'm not even getting to that booting into diagnostic mode, and when I boot to normal mode windows it adds a full 5ns - be happy, that is awesome!


----------



## halcyonon

Looking for some tips, my memory seems to have a really hard time training, ie at the 3666mhz settings below it will power cycle 2-3 times to get to the point it posts and boots in to Windows. Once there it is stable (24h anta extreme TM5 tests pass).. but I'm wondering if I should be concerned, or if there is something I can do to make it have less difficulty training. And is training a boolean, ie it either trains or it doesn't, and if it does it will just work? Or is there a possibility that on some boot it trains with bad parameters and causes instability?

For reference, at the same timings and slightly less voltage at 3600 it posts 100% of the time on the first boot.

RAM: Corsair Dominator 64GB Platinum RGB Pro (4x16GB dual sided B-die [email protected])
Mobo: Asus Dark Hero running bios 3003/3204 (doesn't seem to make any difference which version)
CPU: 5950X

VDimm set to 1.46V in bios, current capability set to 120%
Soc set to 1.14375 in bios, phase set to extreme, and LLC set to 3


----------



## Kezanian

Hale59 said:


> Sure, but there is a great demand for those CPUs. Rather be patient, sell it, and make another order. You will end up get a better one. No need to rush. Sometime running after the cutting edge, you get a cutting edge dud.
> But anyway, enjoy it.
> 
> Anyway, like your CPU, look at this one:
> View attachment 2476627


I also have the dark hero and my timings below which are stable based on long tests, but just wondering how did you come up with the RTT and CAD bus values? mine are auto and ryzen calculator gave me completely different ones, just wondering if there's science behind selecting what values to put in there or reasoning for the ones you chose. appreciate your help


----------



## heptilion

Managed to drop the timings down with 1.5v vdimm. passed 30 cycles of testmem5 2 hours occt and 3 cycles of y cruncher. 

Not sure what more i could try. my aida64 latency is at 54.9ms which seems to be on the high side i feel like.

suggestions please @Veii

CL14 isnt working. tried upping to 3966 but windows and bios both get very laggy and lots of whea errors. also


----------



## Hale59

Kezanian said:


> I also have the dark hero and my timings below which are stable based on long tests, but just wondering how did you come up with the RTT and CAD bus values? mine are auto and ryzen calculator gave me completely different ones, just wondering if there's science behind selecting what values to put in there or reasoning for the ones you chose. appreciate your help


Those are not my timings. Cannot give an explanation.


----------



## Akex

Kezanian said:


> I also have the dark hero and my timings below which are stable based on long tests, but just wondering how did you come up with the RTT and CAD bus values? mine are auto and ryzen calculator gave me completely different ones, just wondering if there's science behind selecting what values to put in there or reasoning for the ones you chose. appreciate your help
> 
> View attachment 2477137


My English is very bad, difficult for me to explain to you, what I can tell you is to try GDM OFF 2T with 60-20-20-24 and 50-50-50. I have a kit similar to yours and I am at 3800Mhz C14 GDM OFF 2T, the CAD help me to be stable on GDM OFF


----------



## Kezanian

Akex said:


> My English is very bad, difficult for me to explain to you, what I can tell you is to try GDM OFF 2T with 60-20-20-24 and 50-50-50. I have a kit similar to yours and I am at 3800Mhz C14 GDM OFF 2T, the CAD help me to be stable on GDM OFF


Your English is good! 

Thanks, I will give that a shot this weekend, do you mind sharing your zentimings? what's your latency in Aida?


----------



## KedarWolf

This is looking good. 3800MHz with decent timings for 2x16GB b-dies. UNLIKE my 3950x, my 5950x need the L2N modes in BIOS off, not on, to be WHEA free. Took me a long time to figure that out.


----------



## craxton

Comalive said:


> fclk 1900 still doesn't boot and I seem to get the same amount of WHEA 19 errors as previously (after doing short tests only so far)


thats unfortunate man, sorry. im currently still running my 5600x on my b550 gaming edge wifi board with c16 flat on some dark pro team kits, waiting for a second pair to come from newegg should arrive tomorrow or friday. (CROSSES FINGERS) if i can manage to get all 4 sticks to run the same timings at 4000 mhz from 3200 with fclk set to 2000 ill be a happy camper. (are you running bdie?) if so try these settings. this is with the updated bios as well. here are my aida scores and my r23 score with pbo on etc with a -.075 offset to voltage while leaving it on auto with a auto 200mhz oc, r20 score is 4587 ran back to back several times. dont recall the r23 at this time as its not saved in my logs. hereis my aida score along with the timings again for good measure. (bios isnt updated with aida but scores did change after updating so i didnt think it would matter.


----------



## Veii

heptilion said:


> Managed to drop the timings down with 1.5v vdimm. passed 30 cycles of testmem5 2 hours occt and 3 cycles of y cruncher.
> 
> Not sure what more i could try. my aida64 latency is at 54.9ms which seems to be on the high side i feel like.
> 
> suggestions please @Veii
> 
> CL14 isnt working. tried upping to 3966 but windows and bios both get very laggy and lots of whea errors. also
> 
> View attachment 2477138


tRDWR should go down at least -1 more
Try to change driving behavior of the dimms a bit by using
3800MT/s @ tCKE 9, CAD_BUS Timings 3-3-15, CAD_BUS 40-20-20-20

check if that passes TM5, and later try to work with RTT 6/3/3 (nom, park, wr) 
What you feel here, is autocorrection happening ~ as you should move near 52ns with this set
ProcODT 36 probably runs better for you but try to increase vSOC a bit more
Also keep testing with Aida64 Cache/Mem and SiSoftware Sandra MCE (detailed view)

Latency will improve as you increase SOC, and keep CPU VDDP sub or equal 900mV


----------



## KedarWolf

@Veii 

This passes OCCT WHEA free and TM5. I'm very happy to get this.

I'm new with 5000 series, any suggestions?


----------



## Veii

KedarWolf said:


> @Veii
> 
> This passes OCCT WHEA free and TM5. I'm very happy to get this.
> 
> I'm new with 5000 series, any suggestions?
> 
> View attachment 2477163


The same response as above  
Try to change the powering mode 
procODT 36 should be plenty for dual rank @ 3800MT/s
Maybe try to find CPU VDDP and drop it to 880mV, if 900mV is not set


----------



## heptilion

Veii said:


> tRDWR should go down at least -1 more
> Try to change driving behavior of the dimms a bit by using
> 3800MT/s @ tCKE 9, CAD_BUS Timings 3-3-15, CAD_BUS 40-20-20-20
> 
> check if that passes TM5, and later try to work with RTT 6/3/3 (nom, park, wr)
> What you feel here, is autocorrection happening ~ as you should move near 52ns with this set
> ProcODT 36 probably runs better for you but try to increase vSOC a bit more
> Also keep testing with Aida64 Cache/Mem and SiSoftware Sandra MCE (detailed view)
> 
> Latency will improve as you increase SOC, and keep CPU VDDP sub or equal 900mV


I ran aida64 with procodt 32 34 36 40 and they all came up with 55.0 and 55.1ns so not much deviance. with proc odt 34.6 i consistently got 54.9ns. i did try increasing vsoc up from ranges 1.125 - 1.15v (increased proc odt to 36 and 40) with clk at 24 and 40 both. which was giving me error 6 in testmem.

also i started with trdwr at 9 initially and then got error 10 so increased to +1 to combat that.

I have set dram R1 to zero. Hw prefetcher enabled, memory interleaving size 512bytes etc.. as per dram calculator. Should I keep it at that?

Is CPU vddp different to cldo vddp? I have crosshair 8 hero mobo.

mind you i got all of my testmem errors between 6-12cycles. so not sure if it is heat related as well since rams were running at 58c.

tried the timings you suggested but latency has increased slightly to 55.2ns


----------



## craxton

o..k... kinda confused as to what or why some of you with 5000 series chips cant get two sticks of ram running fclk 2000 when the chip i have has been dropped with an entire row of pins being bent when i got it (straight now and cant tell at all) but im able to run 4 3200c14 dark pro sticks at 4000mhz 2000fclk on a 5600x without issue, granted my timings could be better i know but still...B550 gaming edge wifi board btw. just got this kit early this morning had no issues with getting it going. simply applied my already saved profile from a usb and it ran without issue or question.....


----------



## domdtxdissar

craxton said:


> o..k... kinda confused as to what or why some of you with 5000 series chips cant get two sticks of ram running fclk 2000 when the chip i have has been dropped with an entire row of pins being bent when i got it (straight now and cant tell at all) but im able to run 4 3200c14 dark pro sticks at 4000mhz 2000fclk on a 5600x without issue, granted my timings could be better i know but still...B550 gaming edge wifi board btw. just got this kit early this morning had no issues with getting it going. simply applied my already saved profile from a usb and it ran without issue or question.....
> View attachment 2477278


Now try the same with a 4700mhz+ static OC or pushed PBO CO on a dual CCX CPU 
Also your latencies seems alittle high for 2000fclk(?), could already indicate WHEA errors.
Maybe you should try to run OCCT large dataset for 1 hour like the people above you, if you wanna be sure


----------



## craxton

domdtxdissar said:


> Now try the same with a 4700mhz+ static OC or pushed PBO CO on a dual CCX CPU
> Also your latencies seems alittle high for 2000fclk(?), could already indicate WHEA errors.
> Maybe you should try to run OCCT large dataset for 1 hour like the people above you, if you wanna be sure


if i had killed tasks etc latency would look more like this image instead of allowing synapse, hwinfo, afterburner, PX1, CFospeed, all tasks that start when the pc does...and ill not run any static oc at this time due to running a -.075mv offset to voltage. so max voltage is around 1.38 for 4.85 auto oc....PBO is set to well the other image below that i added after editing.


----------



## craxton

domdtxdissar said:


> Now try the same with a 4700mhz+ static OC or pushed PBO CO on a dual CCX CPU
> Also your latencies seems alittle high for 2000fclk(?), could already indicate WHEA errors.
> Maybe you should try to run OCCT large dataset for 1 hour like the people above you, if you wanna be sure


as for stress testing, you can see i use TM5, OCCT, prime95, HCI, and ycruncher. prime runs HOT with pbo set to where its at. but passes anyhow. in all honesty idk why people praise the EK 240mm aio as my masterliquid ml240L is actually better imo for keeping temps cool. but there are no errors other than tasks ive killed myself and the most known error i get is from usb-c port thru my SSK nvme enclosure. never have figured out the issue with whats the cause. have tried MANY MANY MANY different cables etc but none seem to work. the drive will work for a moment then act as if its been unhooked only no disconnect has happened and it still shows, just lags out the desktop. even at stock xmp or lower ram speeds does the same. as i first thought it was ram related. seems its the enclosure as i ordered the proper one, but they sent the wrong one which was ordered a year ago. i had used said enclosure only as usb-A all this time up till now. does work on 480mbs data C cables but none that allow faster transfers.


----------



## heptilion

@Veii 

played around with timings you suggested but latency lies between 54.9-55.1ns upped vsoc from 1.1 to 1.5 with clk 40 but nothing seems to affect latency  his is whea free and tm5 stable


----------



## Redlurkeraite

Any suggestions?

I am able to boot up at 4000Mhz (with wheas) and 3800Mhz (without wheas). 
However at the two frequencies above even at CL16 I get random reboots within windows. 
Any suggestions that I can make to get it stable at those frequencies? 

I'm using 3200CL14 16GBX2.


----------



## Veii

heptilion said:


> I ran aida64 with procodt 32 34 36 40 and they all came up with 55.0 and 55.1ns so not much deviance. with proc odt 34.6 i consistently got 54.9ns. i did try increasing vsoc up from ranges 1.125 - 1.15v (increased proc odt to 36 and 40) with clk at 24 and 40 both. which was giving me error 6 in testmem.
> 
> also i started with trdwr at 9 initially and then got error 10 so increased to +1 to combat that.
> 
> I have set dram R1 to zero. Hw prefetcher enabled, memory interleaving size 512bytes etc.. as per dram calculator. Should I keep it at that?
> 
> Is CPU vddp different to cldo vddp? I have crosshair 8 hero mobo.
> 
> mind you i got all of my testmem errors between 6-12cycles. so not sure if it is heat related as well since rams were running at 58c.
> 
> tried the timings you suggested but latency has increased slightly to 55.2ns
> 
> View attachment 2477180


cLDO_VDDP is very different from CPU VDDP
cLDO_VDDP should stay at 900, unless you want to spend many hours and days to check for autocorrection
CPU VDDP moves between 930-880mV
900mV works well, but 880mV works better - depends on the ryzen you got

I have to say tho, that my ryzen is a gimped unit, and from the testing, they work on 1 & 2 CCD units
VDDG CCD minimum range seems to differ between CPUs, 1CCD units like it below or equal 940mV
VDDG IOD 1060 works on both 1 and 2 CCD units up till the hardlock wall of 2167MT/s FCLK


heptilion said:


> @Veii
> 
> played around with timings you suggested but latency lies between 54.9-55.1ns upped vsoc from 1.1 to 1.5 with clk 40 but nothing seems to affect latency  his is whea free and tm5 stable
> 
> View attachment 2477372


5ghz 10.3ns L3 is still slightly clock-stretching.
10.9ns = 4.65 (stock)
10.7ns = 4.75
10.4ns = 4.9
and so on 
about 100mhz each 0.2ns

I see a lot of people try to hit 51ns with CPU OC, but you can get that on stock too, once you play a bit with CO to equalize all cores perform the same
Negative CO on good cores, will also help and allow worse ones to get more voltage without actually increasing total SVI2 supplied voltage


Spoiler: Your 52ns Baseline














This should be hittable by everyone of you (RTT values will differ by the dimm capacity)
And you can later work procODT down and SOC down
4000MT/s CL16-16 users with good voltages can hit 50.5ns on stock @ 4.65Ghz once they adjust the curves better

54ns, is too high
It can't be that my CL16-16 flat timings perform better than your 15-15 ones 


Spoiler: 54.1ns C16 Low Voltage















My advice would be, to play with procODT till you find yourself in a position where you get less than 0.2ns variance between runs
Usually less than 0.1ns on Memory
Because 0.3ns and higher already does indicate instability or auto-correction

Voltages from DRAM calculator do not work anymore, neither do RTT values nor Chipset interleaving sizes
Probably 512 runs better on 2 CCD units, although 256 runs better on Vermeer overall

Currently 36 proc runs better than 34, at least for 4000MT/s 36 is needed
Manual CAD_BUS timings on GDM off also run better ~ as these are already old results
On CL15-15 testing GDM on/off is a bit hard - but on C16 it clearly shows when the dmms are not powered well/enough
0.5ns gain is there from GDM off 2T, compared with GDM on 1T
And it really can't be that CL16 timings outperform your set 
I'd settle for the same CL16 set, and work with Curve Optimizer and y-cruncher and SiSandra MCE
till everything is consistent and no autocorrection happens

Later then continue @ stock with memOC
Pushing coreOC only masks your issues.
51ns @ 4.65 Precission Boost, should be hittable by anybody with CL16 or lower sets


----------



## KedarWolf

Veii said:


> tRDWR should go down at least -1 more
> Try to change driving behavior of the dimms a bit by using
> 3800MT/s @ tCKE 9, CAD_BUS Timings 3-3-15, CAD_BUS 40-20-20-20
> 
> check if that passes TM5, and later try to work with RTT 6/3/3 (nom, park, wr)
> What you feel here, is autocorrection happening ~ as you should move near 52ns with this set
> ProcODT 36 probably runs better for you but try to increase vSOC a bit more
> Also keep testing with Aida64 Cache/Mem and SiSoftware Sandra MCE (detailed view)
> 
> Latency will improve as you increase SOC, and keep CPU VDDP sub or equal 900mV


@Veii Can't do 6-3-3 Nom, Park and Wr, get random reboots.
This passed last night, usmus at 2500%, two cycles. Next, I'm going to try the CAD timings at 3-3-15 with usmus overnight.

@Veii is my tRDWR and tWRRD fine?


----------



## Veii

KedarWolf said:


> @Veii Can't do 6-3-3 Nom, Park and Wr, get random reboots.
> This passed last night, usmus at 2500%, two cycles. Next, I'm going to try the CAD timings at 3-3-15 with usmus overnight.
> 
> @Veii is my tRDWR and tWRRD fine?
> 
> View attachment 2477472


It looks to be fine
Random shutdowns aside, you could work on it 
But you still don't use CAD_BUS Timings  
please put them in


----------



## KedarWolf

Veii said:


> It looks to be fine
> Random shutdowns aside, you could work on it
> But you still don't use CAD_BUS Timings
> please put them in


Yes, I ran that last night before you explained what the CAD BUS timings were, I was confused. I've put them in now, going to run usmus tonight and OCCT again.


----------



## heptilion

@Veii 

I have been testing the cl16 flat 3800 timings you suggested with different proc odt timings and soc voltage

tested in safe mode to reduce variances. Pbo disabled.

36.9 pro odt seems to be slightly more stable than 34 but 55ns is the best can do.


----------



## KedarWolf

Veii said:


> It looks to be fine
> Random shutdowns aside, you could work on it
> But you still don't use CAD_BUS Timings
> please put them in


Had to go back to 0-0-0, at 3-3-15 game store app wouldn't install, Chrome froze, with sound, couldn't scroll the page and Twitch video froze. Closing it force quit it. 

Everything working fine again at 0-0-0. 

Kept tCKE 9 and 40-20-20-20 though. That passed TM5 and OCCT last night.


----------



## Veii

KedarWolf said:


> Had to go back to 0-0-0, at 3-3-15 game store app wouldn't install, Chrome froze, with sound, couldn't scroll the page and Twitch video froze. Closing it force quit it.
> 
> Everything working fine again at 0-0-0.
> 
> Kept tCKE 9 and 40-20-20-20 though. That passed TM5 and OCCT last night.


Uh, hmmm strange
They define voltage cut times, but they should be fine 
What if you try them with 7/3/3 and then with 6/3/3


----------



## KedarWolf

Veii said:


> Uh, hmmm strange
> They define voltage cut times, but they should be fine
> What if you try them with 7/3/3 and then with 6/3/3


7/3/3 usmus at 1000% 1 cycle, which I find if it passes that is a bit less than an hour, will pass anything I throw at it. 

Zero issues, no freezes, no reboots, app that wouldn't install runs just fine now, it wouldn't even start to run at 3/3/15, even on a reboot.

Rebooting into 6/3/3 now.


----------



## Veii

KedarWolf said:


> 7/3/3 usmus at 1000% 1 cycle, which I find if it passes that is a bit less than an hour, will pass anything I throw at it.
> 
> Zero issues, no freezes, no reboots, app that wouldn't install runs just fine now, it wouldn't even start to run at 3/3/15, even on a reboot.
> 
> Rebooting into 6/3/3 now.
> 
> View attachment 2477494


Nono , sorry my bad
7/3/3 is RTT, same as 6/3/3
3-3-15 = CAD_BUS timings 
same as 4-4-18


----------



## KedarWolf

Veii said:


> Nono , sorry my bad
> 7/3/3 is RTT, same as 6/3/3
> 3-3-15 = CAD_BUS timings
> same as 4-4-18


3-3-15 is what messed me up on the CAD BUS timings. Apps wouldn't install, Chrome freezing, even on a reboot. Should I try 7/3/3 RTT and 4-4-18 CAD BUS timings?


----------



## KedarWolf

KedarWolf said:


> 3-3-15 is what messed me up on the CAD BUS timings. Apps wouldn't install, Chrome freezing, even on a reboot. Should I try 7/3/3 RTT and 4-4-18 CAD BUS timings?


I figured it out by reading back, but RTT 7/3/3 with CAD BUS timings 3-3-15 gives me .2ns more latency than me previous settings at 54.6 and lower read, write and copy.

Didn't keep it long enough to test stability, I ran AIDA 4 times.

But if I go NOM Disabled, Wr 3 and Park 1 with 0-0-0 and 40-20-24-24 I'm .2ns faster at 54.2ns instead of 54.4 I had at my previous settings, read, write and copy just a tiny bit higher and single-core boost the same at 5175MHz.


----------



## wertonez

Hello guys, what rtt values do you recommend for 4 single rank b die sticks? 3900x + x570 strix
I feel like those from dram calc do not work properly


----------



## heptilion

wertonez said:


> Hello guys, what rtt values do you recommend for 4 single rank b die sticks? 3900x + x570 strix
> I feel like those from dram calc do not work properly


Try 7 3 1


----------



## Yviena

heptilion said:


> @Veii
> 
> played around with timings you suggested but latency lies between 54.9-55.1ns upped vsoc from 1.1 to 1.5 with clk 40 but nothing seems to affect latency  his is whea free and tm5 stable
> 
> View attachment 2477372


I too am stuck between 54.7-55ns with the 3800CL16 settings given by the ram excel sheet, 1933-2000 gives me tons of whea errors too even when I tried more relaxed timings at 2000mhz.


----------



## heptilion

Yviena said:


> I too am stuck between 54.7-55ns with the 3800CL16 settings given by the ram excel sheet, 1933-2000 gives me tons of whea errors too even when I tried more relaxed timings at 2000mhz.


yeah man. After 14 hours and 4 pages of notes later, I still can't do better than 54.9ns.

@Veii I tried each proc odt from 32 to 44 and vsoc 1.1 .1125 1.125 1.14 for each of those pro odts and also clk 24 up to 60 for each of these and the best results in safe mode pbo off. All came at 54.5ns 

Except for this setting where I got 54.4ns but after third run jumped up to 54.7ns which suggests instability.
34.9 40 20 20 20 tcke 1 cad bus 0-0-0 at 1.1125


----------



## BluePaint

What is the reason for consistently lower (about 3%) CB R15 (other benchmarks are affected as well) benchmark scores with fixed cpu frequency when raising fclk/ram from 1900/3800 to 1933/3866 despite AIDA showing better performance on higher clock and no wheas during benchmark run?

Its an agesa 1.2 bios on msi tomahawk x570 board and 5950 cpu


----------



## mongoled

BluePaint said:


> What is the reason for consistently lower (about 3%) CB R15 (other benchmarks are affected as well) benchmark scores with fixed cpu frequency when raising fclk/ram from 1900/3800 to 1933/3866 despite AIDA showing better performance on higher clock and no wheas during benchmark run?
> 
> Its an agesa 1.2 bios on msi tomahawk x570 board and 5950 cpu


It's been said that a possible reason is because the higher IF clock eats into the power budget of the CPU. 

Am unsure if this is the case


----------



## Pictus

Veii said:


> My advice would be, to play with procODT till you find yourself in a position where you get less than 0.2ns variance between runs
> Usually less than 0.1ns on Memory
> Because 0.3ns and higher already does indicate instability or auto-correction


Master Veii!
To test AIDA in a clean(bloatware free) Windows environment, Sergei Strelec's WinPE 2021.01.05 
is a good choice and it has AIDA 








Download Sergei Strelec's WinPE - MajorGeeks


WinPE creates a bootable DVD or thumb drive for computer maintenance, partitioning, backup and restore, diagnostics, data recovery, and more. Backups include Acronis, Nortons Ghost, Disk2vhd, Macrium and more. Drive utilities include MiniTool, Macrorit, Defraggler, Auslogics Disk Defrag...



m.majorgeeks.com


----------



## BluePaint

mongoled said:


> It's been said that a possible reason is because the higher IF clock eats into the power budget of the CPU.
> 
> Am unsure if this is the case


Its weird. Raising vddg iod + vddg ccd a lot (up to 1.16 iod tested), i can counteract the performance penalty somewhat but not completely.

Also, back in November, with agesa 1.1 patch C, i didnt notice that behaviour on my 5800x running 2033/4066, despite some wheas.

That lack of progress makes me want to test the limits of that RAM on an intel platform which i dont have, lol


----------



## jomama22

Veii said:


> cLDO_VDDP is very different from CPU VDDP
> cLDO_VDDP should stay at 900, unless you want to spend many hours and days to check for autocorrection
> CPU VDDP moves between 930-880mV
> 900mV works well, but 880mV works better - depends on the ryzen you got
> 
> I have to say tho, that my ryzen is a gimped unit, and from the testing, they work on 1 & 2 CCD units
> VDDG CCD minimum range seems to differ between CPUs, 1CCD units like it below or equal 940mV
> VDDG IOD 1060 works on both 1 and 2 CCD units up till the hardlock wall of 2167MT/s FCLK
> 
> 5ghz 10.3ns L3 is still slightly clock-stretching.
> 10.9ns = 4.65 (stock)
> 10.7ns = 4.75
> 10.4ns = 4.9
> and so on
> about 100mhz each 0.2ns
> 
> I see a lot of people try to hit 51ns with CPU OC, but you can get that on stock too, once you play a bit with CO to equalize all cores perform the same
> Negative CO on good cores, will also help and allow worse ones to get more voltage without actually increasing total SVI2 supplied voltage
> 
> 
> Spoiler: Your 52ns Baseline
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This should be hittable by everyone of you (RTT values will differ by the dimm capacity)
> And you can later work procODT down and SOC down
> 4000MT/s CL16-16 users with good voltages can hit 50.5ns on stock @ 4.65Ghz once they adjust the curves better
> 
> 54ns, is too high
> It can't be that my CL16-16 flat timings perform better than your 15-15 ones
> 
> 
> Spoiler: 54.1ns C16 Low Voltage
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> My advice would be, to play with procODT till you find yourself in a position where you get less than 0.2ns variance between runs
> Usually less than 0.1ns on Memory
> Because 0.3ns and higher already does indicate instability or auto-correction
> 
> Voltages from DRAM calculator do not work anymore, neither do RTT values nor Chipset interleaving sizes
> Probably 512 runs better on 2 CCD units, although 256 runs better on Vermeer overall
> 
> Currently 36 proc runs better than 34, at least for 4000MT/s 36 is needed
> Manual CAD_BUS timings on GDM off also run better ~ as these are already old results
> On CL15-15 testing GDM on/off is a bit hard - but on C16 it clearly shows when the dmms are not powered well/enough
> 0.5ns gain is there from GDM off 2T, compared with GDM on 1T
> And it really can't be that CL16 timings outperform your set
> I'd settle for the same CL16 set, and work with Curve Optimizer and y-cruncher and SiSandra MCE
> till everything is consistent and no autocorrection happens
> 
> Later then continue @ stock with memOC
> Pushing coreOC only masks your issues.
> 51ns @ 4.65 Precission Boost, should be hittable by anybody with CL16 or lower sets


Are you getting whea with fclk of 2000?


----------



## Karagra

Any suggestions to lower the latency? VSoc is 1.16 in bios, Ram is 1.46v, PPL 1.85 this was stable on a 200% run with 1sumus stress test.


----------



## craxton

hmmm....each run back to back to back....latency goes down quite a bit without killing anything else and nor am i opening anything....instability? havent changed anything other than seeing some errors to swapped a few bus settings and proc as well as lowered vdimm voltage which then only showed 2 errors for 1000% test instead of 9 for 570% testing thru HCI....(twice tested with HCI errors show around the same time around the same % of the testing... NOTES 4 sticks now instead of two. i do believe the two sticks of dark pro i had prior were better in the case that well the timings shown below for XMP values i think would indicate that.....new sticks are slot 1 and 3 old sticks are 2 and 4 (edit) looking at the boxes etc says there the exact same kits which is what i was buying, perhaps im dead wrong on my assumption and thats just how the second stick per 2 stick kits are idk. but can someone share some insight on stabilizing 4 sticks single rank bdie????


----------



## Joeking78

bonet69 said:


> Hello, after trying 3 different 5800x cpu i can tell for sure that whea errors coming with high fclk 1900+ are cpu deppendant and they come at the limit of your imc, i couldnt get rid of whea errors in2 cpu over 1900+ fclk but with the third one i can tell for sure no whea errors tested until 2050 fclk (i cant boot with more ram speed using 32gb dual ranked) and probably it could go higher using 2x8gb instead of mine:
> 
> View attachment 2477044
> 
> 
> I have good IF but cpu oc speeds are average 4.6ghz with 1.32v at 2033 fclk (with higher fclk it needs even more voltage) i am still tweaking vddp and vddg but i get no whea errors no matter what voltages i use, just a little bit performance gains or loses depending of voltages.
> 
> Regards


Seems that way.

I discovered all the review websites such as techpowerup, guru3d, pcmag, etc were given the same batch number of 5800x (2036SUS), you can see the image on each of their websites...I figured AMD would give them good samples so I spent half a day on Saturday looking for that batch on local stores...I found 2040SUS and its a good cpu so far.

2000 and 2066 IF tested with 1:1 and WHEA free, all cores boosting to 5025mhz under PBO in single core and all cores boosting to 4.65ghz under PBO in multi core tasks


----------



## KedarWolf

craxton said:


> hmmm....each run back to back to back....latency goes down quite a bit without killing anything else and nor am i opening anything....instability? havent changed anything other than seeing some errors to swapped a few bus settings and proc as well as lowered vdimm voltage which then only showed 2 errors for 1000% test instead of 9 for 570% testing thru HCI....(twice tested with HCI errors show around the same time around the same % of the testing... NOTES 4 sticks now instead of two. i do believe the two sticks of dark pro i had prior were better in the case that well the timings shown below for XMP values i think would indicate that.....new sticks are slot 1 and 3 old sticks are 2 and 4 (edit) looking at the boxes etc says there the exact same kits which is what i was buying, perhaps im dead wrong on my assumption and thats just how the second stick per 2 stick kits are idk. but can someone share some insight on stabilizing 4 sticks single rank bdie????
> View attachment 2477607
> View attachment 2477608
> View attachment 2477609
> 
> View attachment 2477612


I can do 4000, but only 3800 WHEA free.


----------



## KedarWolf

1usmus_v3, 1 cycle, but at 2500%, not 100%.


----------



## Veii

jomama22 said:


> Are you getting whea with fclk of 2000?


non 








My current toys
Two Dark Hero systems , both with a 5900X and not bad at all but very taxing 4x A2 memory
I'm having a big fight with ASUS , AMD and their fMAX "nonsense"
Don't want to call it bad, because The Stilt took a loong time to research on it
But it pushes inter-core latency to avg 43ns, instead of consistently down to 24ns ~ some cores peak to >62ns


Spoiler: SiSandra














I respect The Stilt again quite a lot, but this is far worse ~ even inside 1 CCD
compared to


Spoiler














The Cache numbers look really nice , but it's not recommendable
Anywho
,i just want to share and double-confirm that my little voltage presets work also for 2 CCD unit


> 900 CPU VDDP
> 900 CLDO_VDDP
> 940 VDDG CCD
> 1060 VDDG IOD
> 1.2xxx (work in progress) SOC beyond 1.2+
> tCKE 11, 4-4-18 CAD_BUS , 40-20-20-20
> 1.544vDIMM (1.54) RTT 6/3/3


 ^ This should be a preset for people who want to run 2000+ FCLK on SMU 56.45 (maybe even 44)
tCKE , CAD_BUS / CAD_BUS Timings and votlages you can pretty much reuse
2x 8gb guys, rather stay at 7/0/6 RTT
6/3/3 is only for 4 dimm and 2 dimm dual rank people 
3800 still likes tCKE 9, 3-3-15 & >4000 it's tCKE 11, 4-4-18
(single and dual rank)

You only need to test if BGS normal one does affect and break the CAD_BUS Timings & tCKE
BGS Alt works that way at least
512kb chipset interleaving for 2 CCD users, 256 for 1 CCD users or gimped hibernated CCD users

For better more clonable results , give me couple more days
It's a bad Aida64 result, but at least in a usable proof of concept state
No WHEA even at 2000FCLK

EDIT:
Probably most important one








SMU 56.45 (AGESA 1.2.0.0) finally applies what should be standard since 1.0.8.0 last year
ProcODT, RTT and well you can read 
Finally apply to the Bios
Peak range is 480ohm not 240 , soo your old drive and impedance settings are pretty much invalid 
Still haven't seen functioning Mem-Pstates, but the Dark Hero seems to have them hidden in the Bios
And still wait for DLDO Per Core C-State, and per Core Freq OC (somedayTM zZZZ)
Also you guys have Cezanne/Lucien support since 1.1.9.1 Patch D - after SMU 56.40+


----------



## heptilion

@Veii How come you aida64 latency at 53.9ns? i thought it should be much lower from what you explained to me?

also where in bios for dark hero cpu vddp located?


----------



## Veii

heptilion said:


> @Veii How come you aida64 latency at 53.9ns? i thought it should be much lower from what you explained to me?
> 
> also where in bios for dark hero cpu vddp located?


It's the normal VDDP inside tweakers paradise (CPU VDDP)
I don't have a dark hero infront of me
It's remote OC to two people/friends/clients ~ just helping people

I only have my 2x 8GB A0 vipers and the strange 5600X
It should be lower than 52ns ~ but the CPU doesn't boost well at all
Soo it should only show proof of concept that the voltages can run decently well ~ error free at least
But the memory timings are not that good, eh the 5900X is just not boosting fine ~ barely can hold 4.95Ghz stock boosting

Buggy PBO and buggy fMax which keeps being active - bother me atm
Need 1-2 more days to have good shareable results
The Dark hero has no visible or trackable EDC Limit.
You do not know if it applies at all and what it does. A pure mess with PBO atm


----------



## wertonez

heptilion said:


> Try 7 3 1


And what proc odt do you recommend? Currently running 43


----------



## heptilion

Veii said:


> It's the normal VDDP inside tweakers paradise (CPU VDDP)
> I don't have a dark hero infront of me
> It's remote OC to two people/friends/clients ~ just helping people
> 
> I only have my 2x 8GB A0 vipers and the strange 5600X
> It should be lower than 52ns ~ but the CPU doesn't boost well at all
> Soo it should only show proof of concept that the voltages can run decently well ~ error free at least
> But the memory timings are not that good, eh the 5900X is just not boosting fine ~ barely can hold 4.95Ghz stock boosting
> 
> Buggy PBO and buggy fMax which keeps being active - bother me atm
> Need 1-2 more days to have good shareable results
> The Dark hero has no visible or trackable EDC Limit.
> You do not know if it applies at all and what it does. A pure mess with PBO atm


Understood 

I just tried those timings with my 4x8gb bdie kits at 3800 and get 55ns on crosshair 8 hero wifi. I guess something is up with my processor or mobo cus both 2 dimm dual rank and 4 dimm Sr giving me same aida latency. 

Or I am completely missing something which is what most likely to be the case.


----------



## heptilion

wertonez said:


> And what proc odt do you recommend? Currently running 43


This is what i was using on my 3800x with 4dimm bdie. clkdrv 40-20-20-24 might work better for you. vdimm 1.5v


----------



## mongoled

Just playing with this












Unsure what has done the trick. May have to do with the 1.2v SOC voltage.

I dont think its the RTT settings as I accidently used the settings for 2 dimms, and there were no WHEA errors with those settings. Have tCKE @11, as per @Veii I cant set the 4-4-18 values. Results in F2 error. Can you name these as the order you have them quoted may be different on other motherboards. I assumed these values are for CAD_BUS AddrCmd (4), CsODT (4) & Cke (18) ?


----------



## craxton

(edit) NOPE turns out not fully stable.... bout to give up... and just revert back to two sticks since I've found a few things that will increase a few speeds elsewhere... But still :/

FINALLY!!!!!!! forgot to grab passing in TM5, and my woman closed HCI earlier when she checked her (tax refund advance account status) but anyhow....only variation difference being was leaving zen timings running added .1ns to testing latency?... timings can be way better but im content with what i have at this time as ive gained half a head of grey hair due to adding two sticks. will come back later and update this with passes as it takes along while to test 32gb over 16gb....


----------



## craxton

KedarWolf said:


> 1usmus_v3, 1 cycle, but at 2500%, not 100%.
> 
> View attachment 2477698
> 
> 
> View attachment 2477657
> 
> 
> View attachment 2477659


Are you running 4 sticks? Or is that 2x16gb sticks? I've literally read everything veii has said to you and tried all configs mentioned with cad timings etc and if I so much as let the pc think I'm setting anything other than 0,0,0 for cad bus timings it simply will not boot. Tcke 1 is where I've had the most sucess where as veii stated 11 is best for 4 sticks etc. 

I'm burnt atm can't believe it took a few chrome pages going "aww snap something broke" smdh...also vdimm for these 4 sticks of dark pro seem to love being at 1.45 1.46 and doesn't like 1.5 or anything higher at all... Super confusing....especially from everything I've read. And all 4 sticks are the same after digging thru emails from team I indeed got the same set I already had just from a different time period. 

Anyhow, supposing I'll finally give cmdt2 a shot since you, and the few others running (I believe) 4 sticks or at least dual rank, are running t2 since it's somewhat easier to manage.


----------



## jomama22

Veii said:


> It's the normal VDDP inside tweakers paradise (CPU VDDP)
> I don't have a dark hero infront of me
> It's remote OC to two people/friends/clients ~ just helping people
> 
> I only have my 2x 8GB A0 vipers and the strange 5600X
> It should be lower than 52ns ~ but the CPU doesn't boost well at all
> Soo it should only show proof of concept that the voltages can run decently well ~ error free at least
> But the memory timings are not that good, eh the 5900X is just not boosting fine ~ barely can hold 4.95Ghz stock boosting
> 
> Buggy PBO and buggy fMax which keeps being active - bother me atm
> Need 1-2 more days to have good shareable results
> The Dark hero has no visible or trackable EDC Limit.
> You do not know if it applies at all and what it does. A pure mess with PBO atm


When you say above "gimped ccd hibernate" are you referring to idle full power shutdown (not reboots) when using c states enabled?

Also, with the DH, you need to set the edc and such limits in both the tweakers menu and amd overclocking, apply, reboot, go back into bios, change amd overclocking pbo to auto, apply, reboot, then check the edc limit in hwinfo (just run an all core bench) and the edc value it hits will be the limit.


----------



## KedarWolf

I've read you can run tRC at +2 to -2 tRP+tRAS and using 19-21 42 I get the same latency as always but higher Read and Write.


----------



## heptilion

@Veii this is whea error free OCCT. Aida64 latency safe mode 54.6ns.

So can confirm these cad bus timings and tcke work on my ch8 hero wifi board. But latency no difference.


----------



## Veii

mongoled said:


> I dont think its the RTT settings as I accidently used the settings for 2 dimms, and there were no WHEA errors with those settings. Have tCKE @11, as per @Veii I cant set the 4-4-18 values. Results in F2 error. Can you name these as the order you have them quoted may be different on other motherboards. I assumed these values are for CAD_BUS AddrCmd (4), CsODT (4) & Cke (18) ?





Spoiler














They are like written here, CAD_BUS Timings
You can set between 0-63 there
They are needed if you run CAD_BUS X-20-20-20
X defines memory capacity and RTT values do influence it. Same as procODT does
60-20-20-20 with CAD_BUS Timing's, caused many PCB crashes
40-20-20-20 or 40-20-30-20 without the timing-delays are a better option, and just different RTT values

RTT range changed, i would not run /1 on close to any setup. Maybe /2 , depends really
I have to excuse myself to strongly criticize The Stilt on FMax from the last post.
There is a bit more going on and architecturally not possible on 2 CCD units to go sub 40ns Inter-core Latency (avg)
It ranges between 13,24,60ns up to link location. For now it's not possible neverless if you stay on an older bios or newer

SMU 56.45 caused for me big issues with anything PBO related. The whole boosting system messed up
The sample seems to be Gold. 1175mV for 4700/4625. Might be able to do stable 4800 per CCX , but 1175mV is already 210W / >200A EDC and y-cruncher can not pass. Hit OTP (overthermal protection beyond 90c ~ WIP)

Downgraded to SMU 56.43 which is 1190,but that one has a fixed EDC lock 200A
The main and the AMD Overclocking PBO do not function, the AMD CBS is locked at 200A neverless what you do
Yet nothing more i can share with it
Maybe this current SiSandra Run to compare


Spoiler: MCE Inter-Core Latency






Code:


SiSoftware Sandra

Benchmark Results
Inter-Core Bandwidth : 151.09GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
Inter-Core Latency : 44.0ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Inter-Core Bandwidth : 6.3GB/s
No. Threads : 24
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Speed
Inter-Core Bandwidth : 31.74MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 0.09ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23
U0-U2 Data Latency : 24.0ns
U0-U4 Data Latency : 25.1ns
U0-U6 Data Latency : 24.2ns
U0-U8 Data Latency : 25.4ns
U0-U10 Data Latency : 24.8ns
U0-U12 Data Latency : 61.1ns
U0-U14 Data Latency : 61.2ns
U0-U16 Data Latency : 60.8ns
U0-U18 Data Latency : 60.7ns
U0-U20 Data Latency : 62.0ns
U0-U22 Data Latency : 62.5ns
U0-U1 Data Latency : 12.8ns
U0-U3 Data Latency : 24.2ns
U0-U5 Data Latency : 25.1ns
U0-U7 Data Latency : 24.3ns
U0-U9 Data Latency : 25.5ns
U0-U11 Data Latency : 24.8ns
U0-U13 Data Latency : 61.5ns
U0-U15 Data Latency : 61.8ns
U0-U17 Data Latency : 60.7ns
U0-U19 Data Latency : 61.1ns
U0-U21 Data Latency : 62.0ns
U0-U23 Data Latency : 62.4ns
U2-U4 Data Latency : 24.8ns
U2-U6 Data Latency : 25.0ns
U2-U8 Data Latency : 25.1ns
U2-U10 Data Latency : 25.2ns
U2-U12 Data Latency : 61.6ns
U2-U14 Data Latency : 61.1ns
U2-U16 Data Latency : 61.0ns
U2-U18 Data Latency : 61.0ns
U2-U20 Data Latency : 62.8ns
U2-U22 Data Latency : 63.0ns
U2-U1 Data Latency : 24.1ns
U2-U3 Data Latency : 12.7ns
U2-U5 Data Latency : 24.4ns
U2-U7 Data Latency : 25.1ns
U2-U9 Data Latency : 25.0ns
U2-U11 Data Latency : 25.2ns
U2-U13 Data Latency : 61.4ns
U2-U15 Data Latency : 61.2ns
U2-U17 Data Latency : 61.3ns
U2-U19 Data Latency : 61.0ns
U2-U21 Data Latency : 62.4ns
U2-U23 Data Latency : 63.4ns
U4-U6 Data Latency : 26.4ns
U4-U8 Data Latency : 28.9ns
U4-U10 Data Latency : 27.9ns
U4-U12 Data Latency : 60.6ns
U4-U14 Data Latency : 61.3ns
U4-U16 Data Latency : 61.0ns
U4-U18 Data Latency : 61.7ns
U4-U20 Data Latency : 63.1ns
U4-U22 Data Latency : 61.9ns
U4-U1 Data Latency : 25.0ns
U4-U3 Data Latency : 24.6ns
U4-U5 Data Latency : 12.9ns
U4-U7 Data Latency : 26.3ns
U4-U9 Data Latency : 28.7ns
U4-U11 Data Latency : 27.8ns
U4-U13 Data Latency : 60.6ns
U4-U15 Data Latency : 61.3ns
U4-U17 Data Latency : 61.1ns
U4-U19 Data Latency : 61.2ns
U4-U21 Data Latency : 61.1ns
U4-U23 Data Latency : 61.7ns
U6-U8 Data Latency : 26.2ns
U6-U10 Data Latency : 26.9ns
U6-U12 Data Latency : 60.2ns
U6-U14 Data Latency : 60.4ns
U6-U16 Data Latency : 60.1ns
U6-U18 Data Latency : 60.4ns
U6-U20 Data Latency : 61.4ns
U6-U22 Data Latency : 61.6ns
U6-U1 Data Latency : 24.0ns
U6-U3 Data Latency : 25.0ns
U6-U5 Data Latency : 25.2ns
U6-U7 Data Latency : 12.7ns
U6-U9 Data Latency : 25.8ns
U6-U11 Data Latency : 27.0ns
U6-U13 Data Latency : 59.5ns
U6-U15 Data Latency : 59.5ns
U6-U17 Data Latency : 60.7ns
U6-U19 Data Latency : 61.6ns
U6-U21 Data Latency : 61.6ns
U6-U23 Data Latency : 62.4ns
U8-U10 Data Latency : 26.6ns
U8-U12 Data Latency : 60.1ns
U8-U14 Data Latency : 61.8ns
U8-U16 Data Latency : 61.1ns
U8-U18 Data Latency : 61.6ns
U8-U20 Data Latency : 61.9ns
U8-U22 Data Latency : 62.4ns
U8-U1 Data Latency : 25.9ns
U8-U3 Data Latency : 25.1ns
U8-U5 Data Latency : 25.8ns
U8-U7 Data Latency : 25.8ns
U8-U9 Data Latency : 13.3ns
U8-U11 Data Latency : 26.5ns
U8-U13 Data Latency : 60.5ns
U8-U15 Data Latency : 61.2ns
U8-U17 Data Latency : 61.1ns
U8-U19 Data Latency : 62.2ns
U8-U21 Data Latency : 63.2ns
U8-U23 Data Latency : 63.8ns
U10-U12 Data Latency : 60.9ns
U10-U14 Data Latency : 60.5ns
U10-U16 Data Latency : 60.4ns
U10-U18 Data Latency : 61.0ns
U10-U20 Data Latency : 61.9ns
U10-U22 Data Latency : 62.4ns
U10-U1 Data Latency : 24.7ns
U10-U3 Data Latency : 26.1ns
U10-U5 Data Latency : 25.6ns
U10-U7 Data Latency : 27.2ns
U10-U9 Data Latency : 26.4ns
U10-U11 Data Latency : 13.1ns
U10-U13 Data Latency : 60.8ns
U10-U15 Data Latency : 60.2ns
U10-U17 Data Latency : 61.4ns
U10-U19 Data Latency : 62.0ns
U10-U21 Data Latency : 61.8ns
U10-U23 Data Latency : 61.5ns
U12-U14 Data Latency : 23.8ns
U12-U16 Data Latency : 24.0ns
U12-U18 Data Latency : 24.7ns
U12-U20 Data Latency : 26.8ns
U12-U22 Data Latency : 25.6ns
U12-U1 Data Latency : 57.9ns
U12-U3 Data Latency : 61.7ns
U12-U5 Data Latency : 60.6ns
U12-U7 Data Latency : 62.1ns
U12-U9 Data Latency : 60.4ns
U12-U11 Data Latency : 61.5ns
U12-U13 Data Latency : 13.2ns
U12-U15 Data Latency : 26.0ns
U12-U17 Data Latency : 24.1ns
U12-U19 Data Latency : 24.9ns
U12-U21 Data Latency : 26.3ns
U12-U23 Data Latency : 25.6ns
U14-U16 Data Latency : 25.6ns
U14-U18 Data Latency : 25.9ns
U14-U20 Data Latency : 25.4ns
U14-U22 Data Latency : 25.4ns
U14-U1 Data Latency : 60.4ns
U14-U3 Data Latency : 61.7ns
U14-U5 Data Latency : 60.7ns
U14-U7 Data Latency : 61.5ns
U14-U9 Data Latency : 62.3ns
U14-U11 Data Latency : 61.4ns
U14-U13 Data Latency : 23.6ns
U14-U15 Data Latency : 13.4ns
U14-U17 Data Latency : 23.8ns
U14-U19 Data Latency : 24.7ns
U14-U21 Data Latency : 25.3ns
U14-U23 Data Latency : 26.7ns
U16-U18 Data Latency : 26.7ns
U16-U20 Data Latency : 26.2ns
U16-U22 Data Latency : 26.1ns
U16-U1 Data Latency : 60.3ns
U16-U3 Data Latency : 61.5ns
U16-U5 Data Latency : 62.2ns
U16-U7 Data Latency : 61.0ns
U16-U9 Data Latency : 62.1ns
U16-U11 Data Latency : 62.0ns
U16-U13 Data Latency : 24.4ns
U16-U15 Data Latency : 24.0ns
U16-U17 Data Latency : 13.2ns
U16-U19 Data Latency : 26.4ns
U16-U21 Data Latency : 26.6ns
U16-U23 Data Latency : 27.1ns
U18-U20 Data Latency : 29.4ns
U18-U22 Data Latency : 28.6ns
U18-U1 Data Latency : 60.2ns
U18-U3 Data Latency : 60.4ns
U18-U5 Data Latency : 62.4ns
U18-U7 Data Latency : 61.1ns
U18-U9 Data Latency : 62.2ns
U18-U11 Data Latency : 61.3ns
U18-U13 Data Latency : 25.2ns
U18-U15 Data Latency : 24.9ns
U18-U17 Data Latency : 25.9ns
U18-U19 Data Latency : 13.4ns
U18-U21 Data Latency : 26.8ns
U18-U23 Data Latency : 26.4ns
U20-U22 Data Latency : 29.9ns
U20-U1 Data Latency : 62.9ns
U20-U3 Data Latency : 61.3ns
U20-U5 Data Latency : 62.6ns
U20-U7 Data Latency : 62.3ns
U20-U9 Data Latency : 62.5ns
U20-U11 Data Latency : 62.5ns
U20-U13 Data Latency : 25.7ns
U20-U15 Data Latency : 25.7ns
U20-U17 Data Latency : 26.6ns
U20-U19 Data Latency : 28.5ns
U20-U21 Data Latency : 13.4ns
U20-U23 Data Latency : 29.4ns
U22-U1 Data Latency : 61.5ns
U22-U3 Data Latency : 61.8ns
U22-U5 Data Latency : 62.7ns
U22-U7 Data Latency : 63.3ns
U22-U9 Data Latency : 63.2ns
U22-U11 Data Latency : 63.5ns
U22-U13 Data Latency : 26.2ns
U22-U15 Data Latency : 26.7ns
U22-U17 Data Latency : 27.9ns
U22-U19 Data Latency : 27.4ns
U22-U21 Data Latency : 26.9ns
U22-U23 Data Latency : 13.4ns
U1-U3 Data Latency : 25.2ns
U1-U5 Data Latency : 25.0ns
U1-U7 Data Latency : 24.2ns
U1-U9 Data Latency : 25.0ns
U1-U11 Data Latency : 24.9ns
U1-U13 Data Latency : 61.8ns
U1-U15 Data Latency : 58.5ns
U1-U17 Data Latency : 62.2ns
U1-U19 Data Latency : 61.7ns
U1-U21 Data Latency : 62.5ns
U1-U23 Data Latency : 61.1ns
U3-U5 Data Latency : 24.4ns
U3-U7 Data Latency : 25.9ns
U3-U9 Data Latency : 25.0ns
U3-U11 Data Latency : 25.9ns
U3-U13 Data Latency : 63.3ns
U3-U15 Data Latency : 60.8ns
U3-U17 Data Latency : 60.4ns
U3-U19 Data Latency : 61.5ns
U3-U21 Data Latency : 60.5ns
U3-U23 Data Latency : 61.4ns
U5-U7 Data Latency : 25.0ns
U5-U9 Data Latency : 26.7ns
U5-U11 Data Latency : 28.3ns
U5-U13 Data Latency : 60.6ns
U5-U15 Data Latency : 61.8ns
U5-U17 Data Latency : 61.4ns
U5-U19 Data Latency : 61.7ns
U5-U21 Data Latency : 62.2ns
U5-U23 Data Latency : 62.6ns
U7-U9 Data Latency : 28.0ns
U7-U11 Data Latency : 26.5ns
U7-U13 Data Latency : 60.1ns
U7-U15 Data Latency : 62.2ns
U7-U17 Data Latency : 61.4ns
U7-U19 Data Latency : 61.7ns
U7-U21 Data Latency : 62.1ns
U7-U23 Data Latency : 62.5ns
U9-U11 Data Latency : 29.4ns
U9-U13 Data Latency : 63.3ns
U9-U15 Data Latency : 60.7ns
U9-U17 Data Latency : 61.4ns
U9-U19 Data Latency : 61.9ns
U9-U21 Data Latency : 62.9ns
U9-U23 Data Latency : 62.8ns
U11-U13 Data Latency : 62.1ns
U11-U15 Data Latency : 63.2ns
U11-U17 Data Latency : 61.8ns
U11-U19 Data Latency : 62.5ns
U11-U21 Data Latency : 62.3ns
U11-U23 Data Latency : 62.7ns
U13-U15 Data Latency : 24.7ns
U13-U17 Data Latency : 25.5ns
U13-U19 Data Latency : 24.9ns
U13-U21 Data Latency : 26.8ns
U13-U23 Data Latency : 25.6ns
U15-U17 Data Latency : 25.6ns
U15-U19 Data Latency : 25.5ns
U15-U21 Data Latency : 25.2ns
U15-U23 Data Latency : 25.5ns
U17-U19 Data Latency : 26.9ns
U17-U21 Data Latency : 26.1ns
U17-U23 Data Latency : 26.5ns
U19-U21 Data Latency : 29.2ns
U19-U23 Data Latency : 29.3ns
U21-U23 Data Latency : 28.1ns
1x 64bytes Blocks Bandwidth : 14.89GB/s
4x 64bytes Blocks Bandwidth : 22.48GB/s
4x 256bytes Blocks Bandwidth : 84.64GB/s
4x 1kB Blocks Bandwidth : 259.33GB/s
4x 4kB Blocks Bandwidth : 345.18GB/s
16x 4kB Blocks Bandwidth : 423.6GB/s
4x 64kB Blocks Bandwidth : 672GB/s
16x 64kB Blocks Bandwidth : 627.29GB/s
8x 256kB Blocks Bandwidth : 616.52GB/s
4x 1MB Blocks Bandwidth : 618.72GB/s
8x 1MB Blocks Bandwidth : 45.17GB/s
8x 4MB Blocks Bandwidth : 18.14GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5900X 12-Core Processor (12C 24T 4.88GHz, 1.9GHz IMC, 12x 512kB L2, 2x 32MB L3)
Microcode : MUAF210009
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII DARK HERO)
Platform Compliance : x64
Buffer Memory Accesses : No
No. Threads : 24
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5900X 12-Core Processor
Speed : 4.88GHz
Min/Max/Turbo Speed : 2.2GHz - 3.7GHz - 4.88GHz
Cores per Processor : 12 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : MUAF210009
L1D (1st Level) Data Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 12x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz




There seems to be a strange 135MB cache 5900X out there, aside from the other 70.38MB ones








Details for Component AMD Ryzen 9 5900X 12-Core







ranker.sisoftware.co.uk




Sadly forgot my userdata for now, but 151 @ 44ns shouldn't be beatable that fast 
* There might be a way to fix these slow link-speed transitions in the future or with a full AMD CBS
** i need more time to understand DynamicOC mode ~ but still not a big fan of SMU 56.45
*__*
Also something important 
HWInfo is broken @ManniX-ITA
The last one which you could track actually suspending cores (white mode) is 6.35.43*20
(*enable CPU Snapshot Pooling)

Your snappy v1 profile does seem to work and suspend cores once you lower minimum powerstate
Unclear if i can replicate the boost ~ trying to utilize DynamicOC mode atm, because the allcore is not coolable even at such low voltage.

PBO on the other hand is EDC locked again , while Motherboard limits are useless when i need to limit EDC in order to tame allcore voltages
We'll see

Haven't found a useful bios, but 3101 (1190) seems to be acceptable ~for now~
Needs testing if 2000FCLK 4xA2 runs or is slowed down. 1933 posts for now
Then it needs testing if BLCK~FCLK2000+ lets you push to 2067 without it switching to 2:1 mode
First this CPU needs to be tamed. It's hot



heptilion said:


> @Veii this is whea error free OCCT. Aida64 latency safe mode 54.6ns.
> 
> So can confirm these cad bus timings and tcke work on my ch8 hero wifi board. But latency no difference.
> 
> 
> View attachment 2477764


Keep on increasing SOC till you have a good latency result. Voltages are fine. It's just more stable with tCKE and CAD_BUS Timings
You might want to try 1-6-6-1-8-8 , if it increases performance for you 
And later try to run tRC 29, tRDWR 21, tFAW 6, tWR 16, tRTP 8, tRFC 232-172-106 @ 1.56+ VDIMM


Spoiler: Something cursed like this


----------



## ManniX-ITA

@Veii 151 @ 44ns with what? 5600x?

Yes HWInfo is a bit broken, was working more or less the previous beta but since I've updated to the latest which fixes random reboots with Vermeer it doesn't work anymore...


----------



## mongoled

BluePaint said:


> Its weird. Raising vddg iod + vddg ccd a lot (up to 1.16 iod tested), i can counteract the performance penalty somewhat but not completely.
> 
> Also, back in November, with agesa 1.1 patch C, i didnt notice that behaviour on my 5800x running 2033/4066, despite some wheas.
> 
> That lack of progress makes me want to test the limits of that RAM on an intel platform which i dont have, lol


Am unsure if IOD is really helping.

Were ambient temps the same when you compared your CB23 scores between lets say running 3800/1900 to 2033/4066 ??

Currently using vSOC @1.2v for my error free WHEA @4133/2067 runs and CB scored 121xx.

That is what I score with 3800/1900 (will do a double check as the 3800/1900 score was run another day and ambients are a little cooler today....)



Veii said:


> They are like written here, CAD_BUS Timings
> You can set between 0-63 there
> They are needed if you run CAD_BUS X-20-20-20
> X defines memory capacity and RTT values do influence it. Same as procODT does
> 60-20-20-20 with CAD_BUS Timing's, caused many PCB crashes
> 40-20-20-20 or 40-20-30-20 without the timing-delays are a better option, and just different RTT values
> 
> RTT range changed, i would not run /1 on close to any setup. Maybe /2 , depends really
> I have to excuse myself to strongly criticize The Stilt on FMax from the last post.
> There is a bit more going on and architecturally not possible on 2 CCD units to go sub 40ns Inter-core Latency (avg)
> It ranges between 13,24,60ns up to link location. For now it's not possible neverless if you stay on an older bios or newer


Thanks for clarification, will give them another try. I was setting them in the correct order but F2 almost every time.

Tried to set them one by one, again F2 almost every time.

Are you saying these values should only be used with X-20-20-20 settings ??

Right now testing 2066/4133 with 24-20-24-24 (4 x A2), 10 mins into TM5 and no WHEA errors so far.



Veii said:


> SMU 56.45 caused for me big issues with anything PBO related. The whole boosting system messed up
> The sample seems to be Gold. 1175mV for 4700/4625. Might be able to do stable 4800 per CCX , but 1175mV is already 210W / >200A EDC and y-cruncher can not pass. Hit OTP (overthermal protection beyond 90c ~ WIP)
> 
> Downgraded to SMU 56.43 which is 1190,but that one has a fixed EDC lock 200A
> The main and the AMD Overclocking PBO do not function, the AMD CBS is locked at 200A neverless what you do
> Yet nothing more i can share with it


I am testing on Eder A85 BIOS which is based on 1.1.9.0 aka SMU .43 and I dont think I have an EDC lock at 200A.

Setting EDC to 200A lowers L3 Cache bandwidth considerably when compared to EDC 280A.

TM5 threw an error, not WHEA related. Never run this frequency/timings combination before....


----------



## Veii

ManniX-ITA said:


> @Veii 151 @ 44ns with what? 5600x?
> 
> Yes HWInfo is a bit broken, was working more or less the previous beta but since I've updated to the latest which fixes random reboots with Vermeer it doesn't work anymore...


It's in the MCE Spoiler
5900X ~ visible 60ns slowdown between specific cores
_We really need a tool that makes pictures out of SiSandra MCE reports_


mongoled said:


> Thanks for clarification, will give them another try. I was setting them in the correct order but F2 almost every time.
> Tried to set them one by one, again F2 almost every time.
> Are you saying these values should only be used with X-20-20-20 settings ??
> Right now testing 2066/4133 with 24-20-24-24 (4 x A2), 10 mins into TM5 and no WHEA errors so far.
> 
> 
> I am testing on Eder A85 BIOS which is based on 1.1.9.0 aka SMU .43 and I dont think I have an EDC lock at 200A.
> Setting EDC to 200A lowers L3 Cache bandwidth considerably when compared to EDC 280A.
> TM5 threw an error, not WHEA related. Never run this frequency/timings combination before....
> 
> View attachment 2477871


It pretty much goes towards tRFC and tRRD/tWTR as an issue
DATA docs








Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com




Why do you use again the combined tRFC and not the split one ?
288-214-132 
tRRD_L 6,
tWTR_L 12
should work
else just try
tRRD_ 5-6
tFAW 20
tWTR_ 4-12
tWRRD probably should be 3 not 4

And yes, use them only on X-20-20-20
they are the finecontrol replacement for them
X-20-24-20 might stack too high
but maybe on this frequency it's already tCKE 12 @ 5-5-21

They are timings, and will show if something is off


Spoiler












쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네


출처:https://blog.asset-intertech.com/test_data_out/2014/11/memory-training-testing-and-margining.ht



coolenjoy.net


----------



## heptilion

Veii said:


> Spoiler
> 
> 
> 
> 
> View attachment 2477853
> 
> 
> 
> Keep on increasing SOC till you have a good latency result. Voltages are fine. It's just more stable with tCKE and CAD_BUS Timings
> You might want to try 1-6-6-1-8-8 , if it increases performance for you
> And later try to run tRC 29, tRDWR 21, tFAW 6, tWR 16, tRTP 8, tRFC 232-172-106 @ 1.56+ VDIMM
> 
> 
> Spoiler: Something cursed like this


I just tried increasing vsoc bit by bit till 1.2v (40mv steppings) but at 1.2 it didn't boots so increased proc odt to 36.9 and till 40ohm. But no change latency. I know you say it will reduce latency but I'm seeing no difference.

Suggest me some more please. I shall be your guinea pig 😋


----------



## BluePaint

mongoled said:


> Am unsure if IOD is really helping.


The rise in CB R15 score (with fixed frequency) for each increment of IOD was consistent and approaching the score when using FCLK 1900.

I don't have enough knowledge what the exact mechanism is but I assume that there is some error correction going on (might be affecting especially high load scenarios since there is no real difference in any AIDA values) and raising IOD seems to help in this case.

Since the CPU has big problems at FCLK 2000 and somewhat less @ 1966 I am trying to figure out how to get most out of that with [email protected] (fixed frequency gives better latency of 1-2 ns):


----------



## ManniX-ITA

Veii said:


> It's in the MCE Spoiler
> 5900X ~ visible 60ns slowdown between specific cores
> _We really need a tool that makes pictures out of SiSandra MCE reports_


Pictures how?
Maybe a Google spreadsheet importing XML/CSV would work.

Doesn't look that impressive that result with the 5900x, I did 201.27 @ 44.4 (6.3 GB/s per thread, 13-64ns) with the Master (don't remember how).
What I'm missing?


----------



## Not a redditor

vsoc 1.2 for cpu oc to not crash or give random reboots vddp 0975 ccd 0975
ll3 ln22 disable 
cpu oc 45.25 / 45 , 44.25/44 with a vcore 1.4 gets to 1.35 temps goes upto 99-100 in cbr20 in a 2 min loop 

from what i saw my latency goes down up to 60.00 ns if i oc the cpu even higher , copy/read/write goes up 100-500 mbs

i get 1 error in memtest64 after 1 hour 
any ideas on how to improve stability ?


----------



## mongoled

Veii said:


> It's in the MCE Spoiler
> 5900X ~ visible 60ns slowdown between specific cores
> _We really need a tool that makes pictures out of SiSandra MCE reports_
> 
> It pretty much goes towards tRFC and tRRD/tWTR as an issue
> DATA docs
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Why do you use again the combined tRFC and not the split one ?
> 288-214-132
> tRRD_L 6,
> tWTR_L 12
> should work
> else just try
> tRRD_ 5-6
> tFAW 20
> tWTR_ 4-12
> tWRRD probably should be 3 not 4
> 
> And yes, use them only on X-20-20-20
> they are the finecontrol replacement for them
> X-20-24-20 might stack too high
> but maybe on this frequency it's already tCKE 12 @ 5-5-21
> 
> They are timings, and will show if something is off


The settings I used were just quick and dirty, I only wanted to see if WHEA warnings are triggered at a higher FCLK/MCLK combination

But thanks anyway



Will look into that table regards 4-4-18 etc.



BluePaint said:


> The rise in CB R15 score (with fixed frequency) for each increment of IOD was consistent and approaching the score when using FCLK 1900.
> 
> I don't have enough knowledge what the exact mechanism is but I assume that there is some error correction going on (might be affecting especially high load scenarios since there is no real difference in any AIDA values) and raising IOD seems to help in this case.
> 
> Since the CPU has big problems at FCLK 2000 and somewhat less @ 1966 I am trying to figure out how to get most out of that with [email protected] (fixed frequency gives better latency of 1-2 ns):
> View attachment 2477874


This looks to be what I will end up doing.

Along with the inconsistencies with WHEA warnings its proving very time consuming trying to figure out what is going on!

I have managed to trigger WHEA errors in both 4066/2033 and 4133/2067 but there is no pattern to it!

Settings make no difference, sometimes it will boot and have no WHEA warning and other times many WHEA warnings!

Ive been pulling my hair out the last hour trying to find a pattern in the hope that I can work out whats going on, but this is way too complex.

Hopefully one day these shenanigans will be a distant memory



This is the conclusion I have come to, all CPUs are able to post at certain ranges of FCLK. The "wall" is not a wall, but a "hole". There are gaps in the FCLK frequency range where a CPU can post, unfortunately I have not seen anyone find a consistent and reproducible means in which we can shift the frequency range.

The range also seems to have good/bad regions.

Example
Using 4066/2033, getting the PC to post is not reliable. Sometimes it will post OK and sometimes it wont
Using 4133/2067 post every single time. On reboot, cold boot, warm boot, no problem. Sometime it will give an issue if you change a setting in the BIOS but after one hard shutdown it posts normally.

Personally I believe that certain variable need to be applied in the correct order on post for the CPU to not have WHEA warning. Over 1900 FCLK something is going amiss with this order resulting in inconsistent results with regards to WHEA warnings.


----------



## Veii

There are memory training issues still in existence
CAD_BUS x-x-40-x , between 30-40 should be used on Vermeer
CPU VDDP defaults to 930mV on some boards. This is too high. 900mV works , but 2100 only was stable at 880mV and probably lower
2100 FCLK needs 1.25v SOC , no way around that ~ but only 1060 IOD still. Maybe 1080 at worst
VDDG CCD starts to play a role in passing FFT tests on higher than 2050 FCLK, same as CPU VDDP does
cLDO_VDDP was on no system ever needed to be pushed beyond 900mV.
Maybe 950 on it could help get 2167 to run, but that likely would want 1.275-1.288vSOC.
2133 is possible and realizable - but the walls are ABL related and the useless package throttle which we can not turn off if desired.

The other way to get consistent results is learn tCKE behavior - but that goes into mem territory
From my perspective - the memory near 4100 (the PCB) starts to be a more likely troublemaker , than the saturated/exhausted fabric clock



ManniX-ITA said:


> Pictures how?
> Maybe a Google spreadsheet importing XML/CSV would work.
> 
> Doesn't look that impressive that result with the 5900x, I did 201.27 @ 44.4 (6.3 GB/s per thread, 13-64ns) with the Master (don't remember how).
> What I'm missing?
> 
> 
> View attachment 2477882


Rendered pictures like this








They use google docs , but it would be complicated to set up as redundant setup
A tool that recognizes the core amount and adds important information like the efficiency, latency fluctuation and still does colour code ~ would be quite useful 


heptilion said:


> I just tried increasing vsoc bit by bit till 1.2v (40mv steppings) but at 1.2 it didn't boots so increased proc odt to 36.9 and till 40ohm. But no change latency. I know you say it will reduce latency but I'm seeing no difference.
> 
> Suggest me some more please. I shall be your guinea pig 😋


Nono, less SOC and less procODT is fine
Just so you can try it out.
Fluctuation of 0.3ns between tests is autocorrecting-instability


----------



## domdtxdissar

Noe idea what any of this means, but here is my 5950x


----------



## Veii

domdtxdissar said:


> Noe idea what any of this means, but here is my 5950x
> View attachment 2477888


Detailed view
only used for personal comparison 
You shouldn't keep online results in there


----------



## BluePaint

I haven't found CPU VDDP in the MSI Tomahawk X-570 BIOS. Is this not accessible or does it have a different name?


----------



## ManniX-ITA

BluePaint said:


> I haven't found CPU VDDP in the MSI Tomahawk X-570 BIOS. Is this not accessible or does it have a different name?


Maybe it's not accessible, the Unify-X doesn't have it.


----------



## BluePaint

Just noticed that I can't get whea free 1900 fclck anymore since I switched from AGESA 1.1.9 BIOS with SMU 56.34.00 to AGESA 1.2 SMU56.44 version on my MSI X570 Tomahawk.

Looked back into my Windows event log, no WHEA for weeks.
Now same settings (or settings based on latest recommendations here) WHEAs even on fclk 1900, lol. 
The older BIOS is hard locked at 1900 which is why I couldn't test > 1900 fclks. Now I can, but I get errors on speeds which were error free before. This is getting tedious.


----------



## Alyjen

if you want a quick benchmark with good memory scaling use Geekbench 5, it scales with memory pretty good, it detects "fake" meaning full of error memory & IF settings as well as performance will just go down while Cinebench is still happy even if you get hundreds of whea's in background


----------



## craxton

BluePaint said:


> I haven't found CPU VDDP in the MSI Tomahawk X-570 BIOS. Is this not accessible or does it have a different name?


It's just called VDDP Voltage on msi boards. My x570 gaming edge and b550 gaming edge both have it. Don't see why neither of those boards wouldn. But be sure to turn it to expert mode after pressing f7 to switch to advanced overclocking mode. (These are no longer my settings just thought I'd let that be known)


----------



## craxton

@Veii ive been following your conversation with mongol for a bit now, trying to figure out what and how to solve this issue myself, best ive done was manage to get down to 1 error thru tm5 and hci prior to these changed here. and pulling my hair out as i couldnt get nothing to stay consistent with latency....(since) swapping from 2sticks of 3200c14 to 4 sticks of bdie (none of which care much for being over 1.45/48volts but will run 1.5 just can run these settings lower without latency changed etc. anyhow anything here you (WILL OR CARE) to input that i change? (note to consider) RZQ anything when you speak it im dumbfounded and when trying to use amd overclocking section msi always takes priority to which nothing sticks in amd advanced section on either board i have at this time.

any how if you will at least answer this, 4 sticks of single rank are to be treated as 2 sticks of dual rank? i ask because a few things ive read that you mentioned a few pages back now has me confused. i get no WHEA errors even when 9 errors arise thru HCI or just a few thru TM5. if i try the addr,csODTsetup, and Ckesetup timings you mentioned to anyone i get no posting so 0,0,0 OR auto is what it stays at.

yes i know veii veii veii which is what everyone asks or mentions lol... but ive wrote several people and taken there advise as well to no avail. rttnom,wr,park are all set to auto (these are single rank dark pro sticks, never did find out what pcb revision they are actually as team just says R2 but i believe them to be A2 from what i could gather else where. (its not a 4stick kit either) but there all the same only differences are manufacturing dates.


----------



## domdtxdissar

Veii said:


> Detailed view
> only used for personal comparison
> You shouldn't keep online results in there


Okai thanks 



Spoiler: Here are my Sandra numbers



SiSoftware Sandra

Benchmark Results
Inter-Core Bandwidth : 152.84GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
Inter-Core Latency : 43.3ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Inter-Core Bandwidth : 4.78GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Speed
Inter-Core Bandwidth : 30.69MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31 
U0-U2 Data Latency : 24.2ns
U0-U4 Data Latency : 24.5ns
U0-U6 Data Latency : 24.2ns
U0-U8 Data Latency : 23.6ns
U0-U10 Data Latency : 24.1ns
U0-U12 Data Latency : 24.2ns
U0-U14 Data Latency : 24.1ns
U0-U16 Data Latency : 61.2ns
U0-U18 Data Latency : 60.9ns
U0-U20 Data Latency : 60.6ns
U0-U22 Data Latency : 61.4ns
U0-U24 Data Latency : 59.7ns
U0-U26 Data Latency : 60.5ns
U0-U28 Data Latency : 60.6ns
U0-U30 Data Latency : 60.7ns
U0-U1 Data Latency : 12.4ns
U0-U3 Data Latency : 24.9ns
U0-U5 Data Latency : 25.0ns
U0-U7 Data Latency : 24.3ns
U0-U9 Data Latency : 23.7ns
U0-U11 Data Latency : 24.2ns
U0-U13 Data Latency : 24.2ns
U0-U15 Data Latency : 24.1ns
U0-U17 Data Latency : 61.3ns
U0-U19 Data Latency : 61.0ns
U0-U21 Data Latency : 60.3ns
U0-U23 Data Latency : 61.3ns
U0-U25 Data Latency : 60.1ns
U0-U27 Data Latency : 61.1ns
U0-U29 Data Latency : 60.9ns
U0-U31 Data Latency : 60.6ns
U2-U4 Data Latency : 25.0ns
U2-U6 Data Latency : 24.8ns
U2-U8 Data Latency : 24.0ns
U2-U10 Data Latency : 24.1ns
U2-U12 Data Latency : 24.2ns
U2-U14 Data Latency : 24.3ns
U2-U16 Data Latency : 61.2ns
U2-U18 Data Latency : 61.2ns
U2-U20 Data Latency : 60.9ns
U2-U22 Data Latency : 60.8ns
U2-U24 Data Latency : 60.5ns
U2-U26 Data Latency : 61.0ns
U2-U28 Data Latency : 60.2ns
U2-U30 Data Latency : 60.7ns
U2-U1 Data Latency : 24.9ns
U2-U3 Data Latency : 12.6ns
U2-U5 Data Latency : 24.3ns
U2-U7 Data Latency : 24.5ns
U2-U9 Data Latency : 24.1ns
U2-U11 Data Latency : 24.1ns
U2-U13 Data Latency : 24.2ns
U2-U15 Data Latency : 24.4ns
U2-U17 Data Latency : 61.1ns
U2-U19 Data Latency : 61.2ns
U2-U21 Data Latency : 60.7ns
U2-U23 Data Latency : 60.7ns
U2-U25 Data Latency : 60.5ns
U2-U27 Data Latency : 60.9ns
U2-U29 Data Latency : 60.4ns
U2-U31 Data Latency : 60.8ns
U4-U6 Data Latency : 24.5ns
U4-U8 Data Latency : 24.2ns
U4-U10 Data Latency : 24.5ns
U4-U12 Data Latency : 25.7ns
U4-U14 Data Latency : 25.7ns
U4-U16 Data Latency : 61.9ns
U4-U18 Data Latency : 62.1ns
U4-U20 Data Latency : 61.6ns
U4-U22 Data Latency : 61.4ns
U4-U24 Data Latency : 61.4ns
U4-U26 Data Latency : 62.0ns
U4-U28 Data Latency : 61.4ns
U4-U30 Data Latency : 61.8ns
U4-U1 Data Latency : 24.7ns
U4-U3 Data Latency : 24.5ns
U4-U5 Data Latency : 12.9ns
U4-U7 Data Latency : 24.2ns
U4-U9 Data Latency : 24.1ns
U4-U11 Data Latency : 24.6ns
U4-U13 Data Latency : 25.7ns
U4-U15 Data Latency : 25.7ns
U4-U17 Data Latency : 61.8ns
U4-U19 Data Latency : 62.9ns
U4-U21 Data Latency : 62.2ns
U4-U23 Data Latency : 61.9ns
U4-U25 Data Latency : 61.5ns
U4-U27 Data Latency : 61.9ns
U4-U29 Data Latency : 62.2ns
U4-U31 Data Latency : 62.1ns
U6-U8 Data Latency : 24.3ns
U6-U10 Data Latency : 24.4ns
U6-U12 Data Latency : 26.0ns
U6-U14 Data Latency : 25.8ns
U6-U16 Data Latency : 62.4ns
U6-U18 Data Latency : 62.3ns
U6-U20 Data Latency : 61.3ns
U6-U22 Data Latency : 62.0ns
U6-U24 Data Latency : 61.8ns
U6-U26 Data Latency : 62.0ns
U6-U28 Data Latency : 62.1ns
U6-U30 Data Latency : 61.8ns
U6-U1 Data Latency : 24.6ns
U6-U3 Data Latency : 24.9ns
U6-U5 Data Latency : 24.0ns
U6-U7 Data Latency : 12.6ns
U6-U9 Data Latency : 24.1ns
U6-U11 Data Latency : 24.4ns
U6-U13 Data Latency : 25.8ns
U6-U15 Data Latency : 25.9ns
U6-U17 Data Latency : 62.3ns
U6-U19 Data Latency : 62.2ns
U6-U21 Data Latency : 61.6ns
U6-U23 Data Latency : 61.7ns
U6-U25 Data Latency : 61.7ns
U6-U27 Data Latency : 62.5ns
U6-U29 Data Latency : 62.0ns
U6-U31 Data Latency : 61.8ns
U8-U10 Data Latency : 25.8ns
U8-U12 Data Latency : 27.4ns
U8-U14 Data Latency : 27.3ns
U8-U16 Data Latency : 61.1ns
U8-U18 Data Latency : 61.3ns
U8-U20 Data Latency : 60.6ns
U8-U22 Data Latency : 61.0ns
U8-U24 Data Latency : 61.2ns
U8-U26 Data Latency : 61.2ns
U8-U28 Data Latency : 61.6ns
U8-U30 Data Latency : 61.4ns
U8-U1 Data Latency : 23.8ns
U8-U3 Data Latency : 23.9ns
U8-U5 Data Latency : 24.4ns
U8-U7 Data Latency : 24.9ns
U8-U9 Data Latency : 12.5ns
U8-U11 Data Latency : 25.5ns
U8-U13 Data Latency : 27.2ns
U8-U15 Data Latency : 27.3ns
U8-U17 Data Latency : 61.7ns
U8-U19 Data Latency : 61.4ns
U8-U21 Data Latency : 61.1ns
U8-U23 Data Latency : 61.6ns
U8-U25 Data Latency : 60.4ns
U8-U27 Data Latency : 61.1ns
U8-U29 Data Latency : 61.3ns
U8-U31 Data Latency : 61.5ns
U10-U12 Data Latency : 27.5ns
U10-U14 Data Latency : 27.6ns
U10-U16 Data Latency : 61.3ns
U10-U18 Data Latency : 62.1ns
U10-U20 Data Latency : 60.8ns
U10-U22 Data Latency : 61.1ns
U10-U24 Data Latency : 61.3ns
U10-U26 Data Latency : 61.5ns
U10-U28 Data Latency : 61.1ns
U10-U30 Data Latency : 61.3ns
U10-U1 Data Latency : 24.1ns
U10-U3 Data Latency : 24.4ns
U10-U5 Data Latency : 24.7ns
U10-U7 Data Latency : 24.4ns
U10-U9 Data Latency : 25.6ns
U10-U11 Data Latency : 12.6ns
U10-U13 Data Latency : 27.4ns
U10-U15 Data Latency : 27.4ns
U10-U17 Data Latency : 61.4ns
U10-U19 Data Latency : 61.8ns
U10-U21 Data Latency : 60.8ns
U10-U23 Data Latency : 61.5ns
U10-U25 Data Latency : 60.8ns
U10-U27 Data Latency : 61.6ns
U10-U29 Data Latency : 61.5ns
U10-U31 Data Latency : 61.1ns
U12-U14 Data Latency : 28.4ns
U12-U16 Data Latency : 61.7ns
U12-U18 Data Latency : 60.9ns
U12-U20 Data Latency : 61.1ns
U12-U22 Data Latency : 60.6ns
U12-U24 Data Latency : 61.0ns
U12-U26 Data Latency : 61.0ns
U12-U28 Data Latency : 61.6ns
U12-U30 Data Latency : 61.6ns
U12-U1 Data Latency : 25.1ns
U12-U3 Data Latency : 24.7ns
U12-U5 Data Latency : 25.9ns
U12-U7 Data Latency : 25.8ns
U12-U9 Data Latency : 27.3ns
U12-U11 Data Latency : 27.4ns
U12-U13 Data Latency : 12.6ns
U12-U15 Data Latency : 28.0ns
U12-U17 Data Latency : 61.5ns
U12-U19 Data Latency : 61.7ns
U12-U21 Data Latency : 61.1ns
U12-U23 Data Latency : 61.3ns
U12-U25 Data Latency : 60.6ns
U12-U27 Data Latency : 61.4ns
U12-U29 Data Latency : 61.1ns
U12-U31 Data Latency : 61.4ns
U14-U16 Data Latency : 61.8ns
U14-U18 Data Latency : 61.3ns
U14-U20 Data Latency : 60.1ns
U14-U22 Data Latency : 61.1ns
U14-U24 Data Latency : 61.0ns
U14-U26 Data Latency : 61.1ns
U14-U28 Data Latency : 61.6ns
U14-U30 Data Latency : 61.4ns
U14-U1 Data Latency : 24.7ns
U14-U3 Data Latency : 24.7ns
U14-U5 Data Latency : 25.9ns
U14-U7 Data Latency : 25.8ns
U14-U9 Data Latency : 27.2ns
U14-U11 Data Latency : 27.6ns
U14-U13 Data Latency : 28.2ns
U14-U15 Data Latency : 12.6ns
U14-U17 Data Latency : 60.2ns
U14-U19 Data Latency : 60.1ns
U14-U21 Data Latency : 59.9ns
U14-U23 Data Latency : 60.1ns
U14-U25 Data Latency : 61.1ns
U14-U27 Data Latency : 61.5ns
U14-U29 Data Latency : 61.0ns
U14-U31 Data Latency : 61.1ns
U16-U18 Data Latency : 24.6ns
U16-U20 Data Latency : 24.9ns
U16-U22 Data Latency : 24.8ns
U16-U24 Data Latency : 24.6ns
U16-U26 Data Latency : 24.6ns
U16-U28 Data Latency : 24.8ns
U16-U30 Data Latency : 24.8ns
U16-U1 Data Latency : 59.7ns
U16-U3 Data Latency : 60.4ns
U16-U5 Data Latency : 61.7ns
U16-U7 Data Latency : 59.7ns
U16-U9 Data Latency : 60.0ns
U16-U11 Data Latency : 60.2ns
U16-U13 Data Latency : 60.7ns
U16-U15 Data Latency : 60.7ns
U16-U17 Data Latency : 12.8ns
U16-U19 Data Latency : 25.5ns
U16-U21 Data Latency : 25.0ns
U16-U23 Data Latency : 24.9ns
U16-U25 Data Latency : 24.3ns
U16-U27 Data Latency : 24.4ns
U16-U29 Data Latency : 24.6ns
U16-U31 Data Latency : 24.8ns
U18-U20 Data Latency : 24.8ns
U18-U22 Data Latency : 25.3ns
U18-U24 Data Latency : 24.3ns
U18-U26 Data Latency : 24.6ns
U18-U28 Data Latency : 24.5ns
U18-U30 Data Latency : 24.6ns
U18-U1 Data Latency : 61.0ns
U18-U3 Data Latency : 61.1ns
U18-U5 Data Latency : 61.2ns
U18-U7 Data Latency : 60.8ns
U18-U9 Data Latency : 60.5ns
U18-U11 Data Latency : 60.4ns
U18-U13 Data Latency : 60.0ns
U18-U15 Data Latency : 60.4ns
U18-U17 Data Latency : 25.3ns
U18-U19 Data Latency : 12.7ns
U18-U21 Data Latency : 24.5ns
U18-U23 Data Latency : 25.1ns
U18-U25 Data Latency : 24.3ns
U18-U27 Data Latency : 24.8ns
U18-U29 Data Latency : 24.6ns
U18-U31 Data Latency : 24.6ns
U20-U22 Data Latency : 24.7ns
U20-U24 Data Latency : 24.6ns
U20-U26 Data Latency : 24.7ns
U20-U28 Data Latency : 26.1ns
U20-U30 Data Latency : 25.8ns
U20-U1 Data Latency : 60.8ns
U20-U3 Data Latency : 60.9ns
U20-U5 Data Latency : 60.6ns
U20-U7 Data Latency : 60.7ns
U20-U9 Data Latency : 60.7ns
U20-U11 Data Latency : 60.6ns
U20-U13 Data Latency : 61.0ns
U20-U15 Data Latency : 60.3ns
U20-U17 Data Latency : 25.4ns
U20-U19 Data Latency : 24.7ns
U20-U21 Data Latency : 12.7ns
U20-U23 Data Latency : 24.2ns
U20-U25 Data Latency : 24.3ns
U20-U27 Data Latency : 24.8ns
U20-U29 Data Latency : 25.9ns
U20-U31 Data Latency : 25.9ns
U22-U24 Data Latency : 24.8ns
U22-U26 Data Latency : 24.7ns
U22-U28 Data Latency : 26.0ns
U22-U30 Data Latency : 26.0ns
U22-U1 Data Latency : 61.1ns
U22-U3 Data Latency : 61.0ns
U22-U5 Data Latency : 61.6ns
U22-U7 Data Latency : 61.2ns
U22-U9 Data Latency : 60.8ns
U22-U11 Data Latency : 61.1ns
U22-U13 Data Latency : 60.6ns
U22-U15 Data Latency : 60.6ns
U22-U17 Data Latency : 24.8ns
U22-U19 Data Latency : 25.1ns
U22-U21 Data Latency : 24.5ns
U22-U23 Data Latency : 12.9ns
U22-U25 Data Latency : 24.6ns
U22-U27 Data Latency : 24.4ns
U22-U29 Data Latency : 26.0ns
U22-U31 Data Latency : 26.2ns
U24-U26 Data Latency : 26.2ns
U24-U28 Data Latency : 27.8ns
U24-U30 Data Latency : 27.8ns
U24-U1 Data Latency : 61.4ns
U24-U3 Data Latency : 61.1ns
U24-U5 Data Latency : 61.0ns
U24-U7 Data Latency : 61.5ns
U24-U9 Data Latency : 61.1ns
U24-U11 Data Latency : 61.2ns
U24-U13 Data Latency : 61.4ns
U24-U15 Data Latency : 61.7ns
U24-U17 Data Latency : 24.7ns
U24-U19 Data Latency : 24.5ns
U24-U21 Data Latency : 24.8ns
U24-U23 Data Latency : 25.0ns
U24-U25 Data Latency : 12.7ns
U24-U27 Data Latency : 26.1ns
U24-U29 Data Latency : 27.9ns
U24-U31 Data Latency : 27.9ns
U26-U28 Data Latency : 28.1ns
U26-U30 Data Latency : 28.2ns
U26-U1 Data Latency : 61.5ns
U26-U3 Data Latency : 62.4ns
U26-U5 Data Latency : 61.8ns
U26-U7 Data Latency : 61.5ns
U26-U9 Data Latency : 61.4ns
U26-U11 Data Latency : 61.9ns
U26-U13 Data Latency : 61.7ns
U26-U15 Data Latency : 61.5ns
U26-U17 Data Latency : 24.5ns
U26-U19 Data Latency : 24.6ns
U26-U21 Data Latency : 24.9ns
U26-U23 Data Latency : 24.9ns
U26-U25 Data Latency : 26.1ns
U26-U27 Data Latency : 12.8ns
U26-U29 Data Latency : 27.9ns
U26-U31 Data Latency : 27.9ns
U28-U30 Data Latency : 28.9ns
U28-U1 Data Latency : 61.2ns
U28-U3 Data Latency : 60.9ns
U28-U5 Data Latency : 61.5ns
U28-U7 Data Latency : 60.6ns
U28-U9 Data Latency : 61.7ns
U28-U11 Data Latency : 60.8ns
U28-U13 Data Latency : 61.6ns
U28-U15 Data Latency : 61.1ns
U28-U17 Data Latency : 25.2ns
U28-U19 Data Latency : 25.0ns
U28-U21 Data Latency : 26.3ns
U28-U23 Data Latency : 26.4ns
U28-U25 Data Latency : 27.8ns
U28-U27 Data Latency : 28.0ns
U28-U29 Data Latency : 12.8ns
U28-U31 Data Latency : 28.6ns
U30-U1 Data Latency : 61.1ns
U30-U3 Data Latency : 61.5ns
U30-U5 Data Latency : 61.0ns
U30-U7 Data Latency : 61.4ns
U30-U9 Data Latency : 61.1ns
U30-U11 Data Latency : 61.4ns
U30-U13 Data Latency : 61.2ns
U30-U15 Data Latency : 61.3ns
U30-U17 Data Latency : 25.2ns
U30-U19 Data Latency : 25.1ns
U30-U21 Data Latency : 26.3ns
U30-U23 Data Latency : 26.4ns
U30-U25 Data Latency : 27.7ns
U30-U27 Data Latency : 28.2ns
U30-U29 Data Latency : 26.5ns
U30-U31 Data Latency : 12.8ns
U1-U3 Data Latency : 22.8ns
U1-U5 Data Latency : 23.3ns
U1-U7 Data Latency : 23.0ns
U1-U9 Data Latency : 23.5ns
U1-U11 Data Latency : 23.9ns
U1-U13 Data Latency : 24.5ns
U1-U15 Data Latency : 24.2ns
U1-U17 Data Latency : 57.8ns
U1-U19 Data Latency : 58.3ns
U1-U21 Data Latency : 58.9ns
U1-U23 Data Latency : 59.6ns
U1-U25 Data Latency : 59.6ns
U1-U27 Data Latency : 58.6ns
U1-U29 Data Latency : 60.1ns
U1-U31 Data Latency : 60.5ns
U3-U5 Data Latency : 23.2ns
U3-U7 Data Latency : 23.2ns
U3-U9 Data Latency : 23.8ns
U3-U11 Data Latency : 23.8ns
U3-U13 Data Latency : 24.4ns
U3-U15 Data Latency : 24.4ns
U3-U17 Data Latency : 58.8ns
U3-U19 Data Latency : 58.4ns
U3-U21 Data Latency : 59.0ns
U3-U23 Data Latency : 59.1ns
U3-U25 Data Latency : 59.3ns
U3-U27 Data Latency : 59.7ns
U3-U29 Data Latency : 59.8ns
U3-U31 Data Latency : 60.3ns
U5-U7 Data Latency : 23.7ns
U5-U9 Data Latency : 24.5ns
U5-U11 Data Latency : 24.5ns
U5-U13 Data Latency : 25.7ns
U5-U15 Data Latency : 24.9ns
U5-U17 Data Latency : 59.6ns
U5-U19 Data Latency : 59.4ns
U5-U21 Data Latency : 60.1ns
U5-U23 Data Latency : 60.4ns
U5-U25 Data Latency : 60.1ns
U5-U27 Data Latency : 60.6ns
U5-U29 Data Latency : 61.2ns
U5-U31 Data Latency : 61.2ns
U7-U9 Data Latency : 24.4ns
U7-U11 Data Latency : 24.6ns
U7-U13 Data Latency : 25.0ns
U7-U15 Data Latency : 25.0ns
U7-U17 Data Latency : 58.6ns
U7-U19 Data Latency : 58.9ns
U7-U21 Data Latency : 59.9ns
U7-U23 Data Latency : 60.6ns
U7-U25 Data Latency : 60.7ns
U7-U27 Data Latency : 60.1ns
U7-U29 Data Latency : 61.4ns
U7-U31 Data Latency : 61.3ns
U9-U11 Data Latency : 25.3ns
U9-U13 Data Latency : 25.8ns
U9-U15 Data Latency : 25.6ns
U9-U17 Data Latency : 60.1ns
U9-U19 Data Latency : 58.9ns
U9-U21 Data Latency : 59.4ns
U9-U23 Data Latency : 60.6ns
U9-U25 Data Latency : 60.8ns
U9-U27 Data Latency : 61.3ns
U9-U29 Data Latency : 61.5ns
U9-U31 Data Latency : 61.4ns
U11-U13 Data Latency : 26.1ns
U11-U15 Data Latency : 25.8ns
U11-U17 Data Latency : 59.9ns
U11-U19 Data Latency : 59.3ns
U11-U21 Data Latency : 60.2ns
U11-U23 Data Latency : 60.9ns
U11-U25 Data Latency : 60.4ns
U11-U27 Data Latency : 60.8ns
U11-U29 Data Latency : 61.9ns
U11-U31 Data Latency : 61.4ns
U13-U15 Data Latency : 26.2ns
U13-U17 Data Latency : 60.5ns
U13-U19 Data Latency : 59.8ns
U13-U21 Data Latency : 61.0ns
U13-U23 Data Latency : 61.4ns
U13-U25 Data Latency : 61.7ns
U13-U27 Data Latency : 61.4ns
U13-U29 Data Latency : 61.9ns
U13-U31 Data Latency : 62.1ns
U15-U17 Data Latency : 59.5ns
U15-U19 Data Latency : 59.6ns
U15-U21 Data Latency : 60.7ns
U15-U23 Data Latency : 61.1ns
U15-U25 Data Latency : 61.4ns
U15-U27 Data Latency : 61.9ns
U15-U29 Data Latency : 61.7ns
U15-U31 Data Latency : 62.1ns
U17-U19 Data Latency : 23.1ns
U17-U21 Data Latency : 23.7ns
U17-U23 Data Latency : 23.5ns
U17-U25 Data Latency : 24.2ns
U17-U27 Data Latency : 24.2ns
U17-U29 Data Latency : 25.1ns
U17-U31 Data Latency : 24.8ns
U19-U21 Data Latency : 23.5ns
U19-U23 Data Latency : 23.6ns
U19-U25 Data Latency : 24.1ns
U19-U27 Data Latency : 24.2ns
U19-U29 Data Latency : 24.7ns
U19-U31 Data Latency : 24.7ns
U21-U23 Data Latency : 24.3ns
U21-U25 Data Latency : 24.9ns
U21-U27 Data Latency : 25.0ns
U21-U29 Data Latency : 25.6ns
U21-U31 Data Latency : 25.3ns
U23-U25 Data Latency : 24.9ns
U23-U27 Data Latency : 24.9ns
U23-U29 Data Latency : 25.4ns
U23-U31 Data Latency : 25.5ns
U25-U27 Data Latency : 25.7ns
U25-U29 Data Latency : 26.4ns
U25-U31 Data Latency : 26.1ns
U27-U29 Data Latency : 26.4ns
U27-U31 Data Latency : 26.1ns
U29-U31 Data Latency : 26.4ns
1x 64bytes Blocks Bandwidth : 18.64GB/s
4x 64bytes Blocks Bandwidth : 27.74GB/s
4x 256bytes Blocks Bandwidth : 108.56GB/s
4x 1kB Blocks Bandwidth : 316.08GB/s
4x 4kB Blocks Bandwidth : 462.48GB/s
16x 4kB Blocks Bandwidth : 626.5GB/s
4x 64kB Blocks Bandwidth : 834GB/s
16x 64kB Blocks Bandwidth : 296.49GB/s
8x 256kB Blocks Bandwidth : 364.41GB/s
4x 1MB Blocks Bandwidth : 377.81GB/s
8x 1MB Blocks Bandwidth : 47GB/s
8x 4MB Blocks Bandwidth : 19.78GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (16C 32T 5.1GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : MUAF210009
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
Platform Compliance : x64
Buffer Memory Accesses : No
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
Speed : 5.1GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5.1GHz
Cores per Processor : 16 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : MUAF210009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Performance will not be consistent!
Tip 2 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## Veii

craxton said:


> It's just called VDDP Voltage on msi boards. My x570 gaming edge and b550 gaming edge both have it. Don't see why neither of those boards wouldn. But be sure to turn it to expert mode after pressing f7 to switch to advanced overclocking mode. (These are no longer my settings just thought I'd let that be known)
> View attachment 2477962


Main menu VDDP is cLDO_VDDP
You can doublecheck it on ZenTimings
CPU VDDP only got visible by the modded X570 Unify bios
Test it, but this should be cLDO_VDDP

Maybe you can control with with an MSI tool
ASUS has it split - stiill named "VDDP only" but it's a different one there
ASRock does name it CPU VDDP
Gigabyte i think also has it split.
Check, and if it misses, request for it to be added
It's needed for higher FCLK


----------



## craxton

Veii said:


> Main menu VDDP is cLDO_VDDP
> You can doublecheck it on ZenTimings
> CPU VDDP only got visible by the modded X570 Unify bios
> Test it, but this should be cLDO_VDDP
> 
> Maybe you can control with with an MSI tool
> ASUS has it split - stiill named "VDDP only" but it's a different one there
> ASRock does name it CPU VDDP
> Gigabyte i think also has it split.
> Check, and if it misses, request for it to be added
> It's needed for higher FCLK


it would seem im wrong my apologies. thank you for correcting me and clearing that up for whoever i almost steered the wrong direction. (no modded bios for the boards i have or none i can find) and thanks for clearing that up for me as well. MSI dragon center has no option inside the utility atm to change cpu cLDO voltage. 

where would one go to request for it to be added?


----------



## Veii

craxton said:


> where would one go to request for it to be added?
> View attachment 2477992


Wish i could give you contacts to ask
But Board-Design Companies don't like me 

Try to ask on twitter or directly via mail towards their Tech-Support
The only direct contact i know is @Shimizu_OC , but he takes over the Japanese Region
Or Mathe_MSI, which takes over the german region (although just rather as sales representative)

I don't know sorry
Via Support Mail, or maybe you get lucky with Shimizu on Twiitter


----------



## Saiger0

Does anyone have insight in what exactly the "DRAM Latency Enhance" mode found in some msi or gigabyte biosses is?
My guess is it has something to do with fault tolerances maybe? Which would make this setting pointless in a 24/7 usecase.


----------



## BelluX

Is this RAM ok for my 5600X?










i need to tweak something? it's just the D.O.C.P profile.

I posted here because in games i'm experiencing some stuttering.


----------



## BluePaint

@BelluX
Post some AIDA ram benchmark results.
What's the exact name of your RAM?
Could be B-die. If it is, there is a good chance of improving RAM performance quite a bit.
Also which are the games u r experience stuttering, which GPU do u have and and which resolution+settings are u running your games?
I would also adivse to use MSI Afterburner for monitoring GPU (and CPU) utilization in-game to see whether your GPU is fully utilized in order to determine whether there is a GPU- or CPU/RAM bottleneck.



mongoled said:


> Am unsure if IOD is really helping.
> Were ambient temps the same when you compared your CB23 scores between lets say running 3800/1900 to 2033/4066 ??


It was just an interesting observation with CB R15 that it showed lower performance after switching from fclk 1800 to fclk 1900 at the same fixed CPU frequency.
5150 points vs 5300 before. There were also no WHEAs during the CB R15 run.

While trying to figure out the cause of the issue I found that IOD has a direct and reproducible influence on the CB R15 result in that case.
CB R15 is pretty quick so I set IOD in bios, start Windows, wait a minute for it to settle, run 3 times CB R15. Scores are very close if not identical for all 3 runs. If I lower IOD scores goes down. If I raise IOD, score goes up. I can't explain that effect, but it's there in that configuration.

At least I found that I can use CB R15 as a quick check whether there is something off about RAM settings. The interesting bit is that CB R15 score itself is pretty independent of RAM speed. 2133 RAM gives 5250 points and 3800 RAM 5300 points. So it's some kind of error correction or slow down which affects CPU performance. It was also interesting that I didn't see a similar change in AIDA scores.


----------



## heptilion

@Veii What LLC level are you using on the dark hero? And switching frequency for vsoc? Should I play around with LLC for CPU as well?


----------



## Esticbo

BelluX said:


> Is this RAM ok for my 5600X?
> 
> View attachment 2478014
> 
> 
> i need to tweak something? it's just the D.O.C.P profile.
> 
> I posted here because in games i'm experiencing some stuttering.



Yes your ram is ok, but you have a Ferrari and user it as a Panda. Try with fclk and mclk to 1800 and more mem vtt.

Your experience of some stuttering might be a driver problem o some program in background


----------



## BluePaint

Do we know what causes USB disconnect/reconnect events during load (testing on MSI X570) ? 
Is it more related to CPU vcore, RAM voltages or chipset ?


----------



## ManniX-ITA

BluePaint said:


> Do we know what causes USB disconnect/reconnect events during load (testing on MSI X570) ?
> Is it more related to CPU vcore, RAM voltages or chipset ?


VDDG, mainly IOD but could also be CCD.
Usually safe to avoid issues:
IOD 1060mV
CCD 1000mV
VSOC 1120mV


----------



## mongoled

BluePaint said:


> @BelluX
> ........................snip
> 
> It was just an interesting observation with CB R15 that it showed lower performance after switching from fclk 1800 to fclk 1900 at the same fixed CPU frequency.
> 5150 points vs 5300 before. There were also no WHEAs during the CB R15 run.
> 
> While trying to figure out the cause of the issue I found that IOD has a direct and reproducible influence on the CB R15 result in that case.
> CB R15 is pretty quick so I set IOD in bios, start Windows, wait a minute for it to settle, run 3 times CB R15. Scores are very close if not identical for all 3 runs. If I lower IOD scores goes down. If I raise IOD, score goes up. I can't explain that effect, but it's there in that configuration.
> 
> At least I found that I can use CB R15 as a quick check whether there is something off about RAM settings. The interesting bit is that CB R15 score itself is pretty independent of RAM speed. 2133 RAM gives 5250 points and 3800 RAM 5300 points. So it's some kind of error correction or slow down which affects CPU performance. It was also interesting that I didn't see a similar change in AIDA scores.


I shall give CB R15 a try.

I tested 3800/1900 vs 4066/2033 vs 4133/2067 in CB R23 multi and the score was always 121xx.

I always set the exe to high priority, in this way the benchmark cannot be effected by other processes going on in the system.


----------



## mongoled

Veii said:


> There are memory training issues still in existence
> CAD_BUS x-x-40-x , between 30-40 should be used on Vermeer
> CPU VDDP defaults to 930mV on some boards. This is too high. 900mV works , but 2100 only was stable at 880mV and probably lower
> 2100 FCLK needs 1.25v SOC , no way around that ~ but only 1060 IOD still. Maybe 1080 at worst
> VDDG CCD starts to play a role in passing FFT tests on higher than 2050 FCLK, same as CPU VDDP does
> cLDO_VDDP was on no system ever needed to be pushed beyond 900mV.
> Maybe 950 on it could help get 2167 to run, but that likely would want 1.275-1.288vSOC.
> 2133 is possible and realizable - but the walls are ABL related and the useless package throttle which we can not turn off if desired.
> 
> The other way to get consistent results is learn tCKE behavior - but that goes into mem territory
> From my perspective - the memory near 4100 (the PCB) starts to be a more likely troublemaker , than the saturated/exhausted fabric clock
> ............snip


The issue I am describing with FCLK is not to do with MCLK.

If I reset BIOS and set only MCLK/FCLK to either 3866/1933, 4066/2033 or 4133/2066 and leaves everything else so the BIOS can decide what to set then sometimes the system will boot and there will be no WHEA warnings or there will be WHEA warnings.

The higher the FCLK the less consistantly does the PC boot without WHEA warnings.

When the PC boots without WHEA warnings I can run benchmarks, let it sit idle and there will be no WHEA warnings.

Its the most strange thing!


----------



## BluePaint

i don't think the R15 effect i noticed (it also affected all other benchmarks i tested, R15 is just very quick) applies to many situations. it was just something i experienced when raising fclk. 
Meanwhile i did a clear CMOS and reset the BIOS again and started all over and i can't observe that effect > 1900 fclk anymore, lol. 
I also have WHEA free 1900 fclk again it seems.


----------



## mongoled

Also just tried, reset bios, set fclk to 2033, set manual voltages and that's it! System boots 1066/2033/1066 (MCLK/FCLK/UCLK) and many many WHEA warnings.

I'm going to go back to old skool CMOS reset, i.e. power down psu, take out CMOS battery. Reset bios. Let sit overnight.....


----------



## BluePaint

The sudden USB disconnect/reconnect happens when I run AIDAs memory read test and I have about 1.25v or more for the CPU, independent of CPU clock. It draws > 200W package power it seems. There are essentially no relevant power limits configured with the manual fixed CPU frequency.



ManniX-ITA said:


> VDDG, mainly IOD but could also be CCD.
> Usually safe to avoid issues:
> IOD 1060mV
> CCD 1000mV
> VSOC 1120mV


Raising those voltages didn't help with the problem so far. LLC on VSOC is already on 3rd highest setting. I will investigate some more. Maybe it needs even more of those voltages or others. It's most certainly some kind of voltage drop caused by the power spike of the CPU.


----------



## mongoled

BluePaint said:


> The sudden USB disconnect/reconnect happens when I run AIDAs memory read test and I have about 1.25v or more for the CPU, independent of CPU clock. It draws > 200W package power it seems. There are essentially no relevant power limits configured with the manual fixed CPU frequency.
> 
> 
> 
> Raising those voltages didn't help with the problem so far. LLC on VSOC is already on 3rd highest setting. I will investigate some more. Maybe it needs even more of those voltages or others. It's most certainly some kind of voltage drop caused by the power spike of the CPU.


Have you tried a different PSU?


----------



## BluePaint

mongoled said:


> Have you tried a different PSU?


No, but that would be interesting (and annoying) to test. The Seasonic 860 Platinum is quite some years old and who knows how that affects voltage stability. Meanwhile it seems that raising vddp helped, have to perform more tests though.

I should probably focus on ram first and use lower cpu voltage + clocks for testing, in order to eliminate potential error sources.


----------



## BelluX

BluePaint said:


> @BelluX
> Post some AIDA ram benchmark results.
> What's the exact name of your RAM?
> Could be B-die. If it is, there is a good chance of improving RAM performance quite a bit.
> Also which are the games u r experience stuttering, which GPU do u have and and which resolution+settings are u running your games?
> I would also adivse to use MSI Afterburner for monitoring GPU (and CPU) utilization in-game to see whether your GPU is fully utilized in order to determine whether there is a GPU- or CPU/RAM bottleneck.


Hi,

my ram are the G.Skill TridentZ Neo with 3200MHz CL14 with B-Die.

i'm not searching tweak for increase performance but only OC guide for a 5000 Ryzen processor because i think mine has some sort of energy saving in caused by a setting setted in auto mode.


----------



## KedarWolf

BelluX said:


> Hi,
> 
> my ram are the G.Skill TridentZ Neo with 3200MHz CL14 with B-Die.
> 
> i'm not searching tweak for increase performance but only OC guide for a 5000 Ryzen processor because i think mine has some sort of energy saving in caused by a setting setted in auto mode.


That RAM will do 3733 cl14 easy, maybe 3800.

And you need the Sync on the memory to be 1/1, I'm at work, but when I'm home can show you the settings.


----------



## BluePaint

Again, after going from fclk 1966 to 2000, I have CPU performance loss (100 points less in CB R15 with fixed frequency) and with higher IOD (1060 -> 1150), that can be counteracted to some extent. Seems to be the limit of my CPU and IOD is helping that it doesn't fall off the cliff. VSOC doesn't make a difference. Oh well, seems that I just have to stay under 2000.

And what does it mean that HWInfo lists WHEAs but Windows event log does not (Windows event log also shows the typical fclk WHEAs but not everytime HWInfo does) ?


----------



## Veii

2100 didn't need higher than 1060 IOD








@BluePaint this shows 920-940-1080-1125 (45 / 90mV stepping)
but what lead to y-cruncher stability @ 2100 was
cLDO_VDDP 900
VDDG CCD 900
VDDG IOD 1050
VSOC 1175 (read out)

CPU VDDP 880
ProcODT 34.3Ω
tCKE 16
CAD_BUS 60-20-20-20

it's an old result, and things improved since then (December 6th) ~ so as my timings did
Currently 50.5 is hittable on stock 10.9ns L3 cache, boost - not 4.85
but as illustrational purpose ~ you don't need more than 1060mV IOD. Less is better 
Referring back to this thread here








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net





The only negative point of the whole thing was the EDC limit
A limit which shouldn't exist according to Mr. Hallock
But a limit which pretty much equalizes core clock to memory clock
Meaning, it makes no sense to push FCLK higher, when cores will be slowed down by lack of powerbudget
^ and one i see again on the 5900X 1190-1200 Agesa as 200A

EDIT:
PBO limits also do take over on fixed frequency 
Even when they should not


----------



## dimi0815

@Veii

How does Dual Rank (2x 16 GB) vs. Single Rank (2x 8 GB, both only taking into account B-Dies) affect latency results?

Would those 50.5 ns be achievable on a a 2x 16 GB setup as well?

Best result I got so far on a 5900X + Unify-X using 2x 16 GB (4200 MHz 16-16-16-32 with 2100 IF and 1:1 setting) was* 52.5 ns* / 0.8 ns / 2.4 ns / 10.2 ns in AIDA benchmark, which is about the same as the best 2x 16 GB result I found in the results spreadsheet.

The setting was basically stable throughout tests, benchmarks, gaming and in daily office use, BUT it always gave me exactly one single WHEA warning (ID 19) immediately when I booted up the system. Tried different procODT / RTT combinations, but couldn't get rid of it. That warning count remained at 1 and never changed though and I've never had my system reboot or shut down randomly...


----------



## Hale59

For a Ryzen 3100 with 2X8GB single rank, not bad. 3200MHz pushed to CL14 - 3800/1900 for a quick bench.

@Veii, any comment, suggestions?


----------



## MageTank

dimi0815 said:


> @Veii
> 
> How does Dual Rank (2x 16 GB) vs. Single Rank (2x 8 GB, both only taking into account B-Dies) affect latency results?
> 
> Would those 50.5 ns be achievable on a a 2x 16 GB setup as well?
> 
> Best result I got so far on a 5900X + Unify-X using 2x 16 GB (4200 MHz 16-16-16-32 with 2100 IF and 1:1 setting) was* 52.5 ns* / 0.8 ns / 2.4 ns / 10.2 ns in AIDA benchmark, which is about the same as the best 2x 16 GB result I found in the results spreadsheet.
> 
> The setting was basically stable throughout tests, benchmarks, gaming and in daily office use, BUT it always gave me exactly one single WHEA warning (ID 19) immediately when I booted up the system. Tried different procODT / RTT combinations, but couldn't get rid of it. That warning count remained at 1 and never changed though and I've never had my system reboot or shut down randomly...


I haven't seen any negative impacts of using dual rank DIMM's vs single rank other than attempting to stabilize higher frequencies at tighter timings due to IMC stress brought about by DR tertiary timings. I will say that the advantage of having real rank interleaving far outweighs any potential latency penalty, so you'll probably be better off trying to get those DIMM's stable even at the cost of a little latency vs swapping to a single rank kit and pushing for lower latency.


----------



## dimi0815

MageTank said:


> I haven't seen any negative impacts of using dual rank DIMM's vs single rank other than attempting to stabilize higher frequencies at tighter timings due to IMC stress brought about by DR tertiary timings. I will say that the advantage of having real rank interleaving far outweighs any potential latency penalty, so you'll probably be better off trying to get those DIMM's stable even at the cost of a little latency vs swapping to a single rank kit and pushing for lower latency.


Oh, swapping them for single ranked DIMMs was never even an option I'd consider. I'll keep those dual-ranked modules for sure (for both rank interleaving and twice the total capacity).

I was just wondering whether the 50.5 ns latency was something only achievable with single ranked DIMMs, i.e. whether at the exact same primary, secondary and tertiary timings (assuming identical stability, too) I would still have to expect different latency results due to double the amount of ranks.


----------



## mongoled

That latency is a best case scenario! No reason to get stuck on it.

It should be achievable on "good pairs" of B die modules with multi layered PCB.


----------



## MageTank

dimi0815 said:


> Oh, swapping them for single ranked DIMMs was never even an option I'd consider. I'll keep those dual-ranked modules for sure (for both rank interleaving and twice the total capacity).
> 
> I was just wondering whether the 50.5 ns latency was something only achievable with single ranked DIMMs, i.e. whether at the exact same primary, secondary and tertiary timings (assuming identical stability, too) I would still have to expect different latency results due to double the amount of ranks.


You can absolutely push lower latency on DR DIMM's, it's just far more difficult as it's a bit more stressful on the IMC and the DIMM's themselves are less tolerant to higher frequencies/tighter timings when you have more IC's to worry about on a DIMM. Here is a *very unstable* result of mine at 3600 C12 on my B550 Unify (non-X):









I can get a ZenTimings screenshot when I get home from work, but I strongly advise against using the timings as it's extremely unstable. Still, it does serve to illustrate that there isn't a magical barrier that prevents DR DIMM's from achieving lower latency results, it's just a matter of time and effort like everything else.

The big takeaways I found with DR DIMM's is that they scale less with voltage compared to single rank DIMM's, and using more voltage will likely hurt your chances of achieving decent results. Second, thermals are a very big deal for these DIMM's. This partly plays into the voltage piece earlier as well, as using lower volts will result in lower thermals, but my results above were done on water and keeping your DIMM's cool is important for stability. My ambient temperature in my basement is 60F/15.5C and my fluid temp with 2x360mm rads and 2x240mm rads doesn't get much hotter than that.

Lastly, choice in DIMM's matters a lot. When you have a dozen IC's on a single DIMM, making sure they are properly binned is going to be insanely important as just one being subpar is going to hold back the entire DIMM. I bought a pretty decent kit for my overclocking endeavors: F4-4266C17D-32GVKB-G.SKILL International Enterprise Co., Ltd.

I am still working on achieving 24/7 stability, but my results are looking very close to yours. @Veii 's latency result isn't common, nor should you consider it to be given his experience. You'll likely get there over time, but if this is your first time memory overclocking on AMD, or your first attempt at it since the old Phenom days like mine, expect there to be some bumps along the way.


----------



## Snipie-PT

@Veii , can you please give me some advise to achieve IF2000 without WHEA?
Currently running the below settings and stable, I can even achieve IF2100 but always with WHEA errors and I have no idea where to start.
Some advise or guide would be great, running 4 SR DIMM's (B-Die).


----------



## Pictus

BluePaint said:


> Do we know what causes USB disconnect/reconnect events during load (testing on MSI X570) ?
> Is it more related to CPU vcore, RAM voltages or chipset ?


Set PCIe to GEN3 may help...

__
https://www.reddit.com/r/Amd/comments/k8mtes


----------



## BluePaint

@Snipie-PT
The problem with WHEAs is that they most certainly also depend on silicon lottery of your CPUs memory controller. And no tweaking will overcome that at a certain point.

I might reinstall my 5800X just to see how it behaves with the latest BIOS so that I can compare the fclk behavior to the 5950X. I don't see much other way to find out whether it's a limitation of the CPU or the MB, BIOS or RAM. The 5800X was running 2033 fclk in November. With the same BIOS the 5950X couldn't get much past 1900. Now the limit for the 5950X seems to be fclk 2000.

@Pictus
Thanks, I will try that.


----------



## Yviena

@Veii do you have any suggestion for timings/voltages to try to get 2000 FCLK whea/error free with 4xSR B-DIE?

i've managed to get the timings that the excel sheet gives me stable at 3800/1900FCLK but anything over has tons of WHEA errors, also would you recommend 1.1.9.0 AGESA, or 1.1.0.0 as i seem to score around 300-400 points lower in MT CB23 with the newer AGESA.


----------



## hlreijnders

So after upgrading my 2700X to a 5800X and my 16GB B-die kit to a 32GB Rev. B kit, I started playing with my RAM again. At stock XMP profile I got a couple of WHEA's, but after manually adjusting everything this is what's stable for now (6 Hours of Karhu and 4 hours HCI Memtest):

















I'm having doubts for my VSOC and VDDG voltages. At stock I would get WHEA's, but I wonder if my manual voltages are safe for 24/7? Also, for now I'm happy with the results, as I also use my PC for work. So tighter timings are not really a necessity, stability is. But I'm probably going to tweak it further when I get bored.


----------



## craxton

can someone please explain if 4 sticks of single rank work similar as dual rank 2 sticks? or 4 sticks of dual rank etc???? i asked @Veii but hes gotta load to respond to. (asking anyone who knows and not taking a guess.) also, i wrote MSI about adding CPU VDDP voltage to their b550 bios but havent received anything back yet. ALSO running 4000mhz stable with 2000fclk with 1.46Vdimm (llc3) on the darkpro sticks from teamgroup. something to consider i suppose for those not willing to use 1.5 volts for anything around 4000mhz considering most all need 1.5 or higher. 52.3ns latency etc. so far best ive gotten. 

TM5, HCI both passed. have yet to try y-cruncher or prime. as im working first shift and not a morning person to which when i get home im ready for no more headaches....


----------



## bonet69

dimi0815 said:


> @Veii
> 
> How does Dual Rank (2x 16 GB) vs. Single Rank (2x 8 GB, both only taking into account B-Dies) affect latency results?
> 
> Would those 50.5 ns be achievable on a a 2x 16 GB setup as well?
> 
> Best result I got so far on a 5900X + Unify-X using 2x 16 GB (4200 MHz 16-16-16-32 with 2100 IF and 1:1 setting) was* 52.5 ns* / 0.8 ns / 2.4 ns / 10.2 ns in AIDA benchmark, which is about the same as the best 2x 16 GB result I found in the results spreadsheet.
> 
> The setting was basically stable throughout tests, benchmarks, gaming and in daily office use, BUT it always gave me exactly one single WHEA warning (ID 19) immediately when I booted up the system. Tried different procODT / RTT combinations, but couldn't get rid of it. That warning count remained at 1 and never changed though and I've never had my system reboot or shut down randomly...


I cant boot with ram (2x16gb DR) over 4066/4100mhz any ideas why? Its the limit for my board?



Spoiler: 4066 cl15 15 14 2t













safe mode:











I dont have wheas. Regards


----------



## Esticbo

bonet69 said:


> I cant boot with ram (2x16gb DR) over 4066/4100mhz any ideas why? Its the limit for my board?
> 
> 
> 
> Spoiler: 4066 cl15 15 14 2t
> 
> 
> 
> 
> View attachment 2478220
> 
> 
> safe mode:
> View attachment 2478221
> 
> 
> 
> 
> I dont have wheas. Regards


You can try with asynchronos boot, IF to 2100 and memory to 2000 or reverse


----------



## Dasa

I was able to get past some weird BIOS limits with BCLK 101-104.


----------



## mongoled

So........

I decided to start investigation the WHEA warnings by moving to Linux (Ubuntu)

After running the "Google Stress Test" application the system rebooted and the error in the journal log is the following

Feb 10 20:46:26 andrew-MS-7C35 kernel: [Hardware Error]: Corrected error, no action required.
Feb 10 20:46:26 andrew-MS-7C35 kernel: [Hardware Error]: CPU:0 (19:21:0) MC27_STATUS[Over|CE|MiscV|-|-|-|SyndV|-|-|-]: 0xd82000000002080b
Feb 10 20:46:26 andrew-MS-7C35 kernel: [Hardware Error]: IPID: 0x0001002e00000500, Syndrome: 0x000000005a020001
Feb 10 20:46:26 andrew-MS-7C35 kernel: [Hardware Error]: Power, Interrupts, etc. Ext. Error Code: 2, Link Error.
Feb 10 20:46:26 andrew-MS-7C35 kernel: [Hardware Error]: cache level: L3/GEN, mem/io: IO, mem-tx: GEN, part-proc: SRC (no timeout)

Interestingly the message points to a L3 cache error.

Would be great if others who are able to run Linux distros to post their journal log after a crash to see if their errors also reference the CPU L3 cache.

Now I can turn my troubleshooting to see if I can find ways to effect the L3 cache, we already know that when using PBO on auto settings the L3 bandwidth is reduced unless we increase EDC limit.

So EDC shall be the target for experimentation...


----------



## mongoled

Dasa said:


> I was able to get past some weird BIOS limits with BCLK 101-104.


Yup, BCLK is great for getting past certain issues as it give us a way of fine tuning the frequency ranges we can play in


----------



## Dasa

I had a feeling the WHEA could be cache related since I don't get any with memory tests but fire up prime95 small ftt and my 5800X spews them out when over 3733.
Small ftt should fit within L1\L2 cache but it may still go through L3.

Using GB B550 Aorus Pro BIOS F13a - AMD AGESA ComboV2 1.2.0.0.
3733 stable while 1900IF has heaps of WHEA along with USB2 drop out and really scratchy audio but 1933IF works ok other than a few WHEA when doing CPU heavy work like prime95 but not during TM5.

CTR 2.0 reports my 5800X as a silver level CPU.
Seems I am unable to run more than 101BCLK on this BIOS.


----------



## BluePaint

Dasa said:


> CTR 2.0 reports my 5800X as a silver level CPU.


The CTR classification does probably not include the IO die quality since it essentially tests the undervolting capabilities with a fixed CPU frequency. 
So I guess u could have a platinum CPU with horrible fclk capabilities and vice versa.


----------



## BelluX

KedarWolf said:


> That RAM will do 3733 cl14 easy, maybe 3800.
> 
> And you need the Sync on the memory to be 1/1, I'm at work, but when I'm home can show you the settings.


Man, can you please share your settings? Thank you.


----------



## BarrettDotFifty

Hey guys. I'm using a 5900X running curve optimizer (-25 -20 -5) and a pair of 2x16GB dual-rank B-Die.

I've been struggling to get 1900 FCLK to be stable with a huge variety of voltage and ProcODT combinations, without much success. Decided to stay with 3600 14-15-14-28 which has been perfectly stable for more than a month, until AMD fixes AGESA or someone figures out the root cause of the WHEAs at 1900+ FCLK. Any ideas whether there's anything that can be done better with this setup now?


----------



## bigblueshock

Anyone with 4 DIMMS running a 5000 series at 3800 mhz/ 1900 FCLK? Right now I'm stable at 3733/1866 Cas14 just as I was with my old 3900x. I'm trying to get Cas 14 at 3800/1900.

I tried adjusting some timings but did not have luck booting 3800/1900 1.50V at Cas 14. I have a Memory Cooler and am using decent B-Die: F4-3600C15D-16GTZ

Is there a baseline somewhere of Important Timings? For instance: TCL, tRCDWR, tRCDRD, tRP, tRAS. ProcODT, RttNom, RttWr, RttPark, and all the DrvStr's. GDM Enabled considering I'm running 4 sticks. VSOC, VDDG/VDDP? I assume I will at least need 1.50V to run 3800 Cas 14.


----------



## heptilion

BarrettDotFifty said:


> Hey guys. I'm using a 5900X running curve optimizer (-25 -20 -5) and a pair of 2x16GB dual-rank B-Die.
> 
> I've been struggling to get 1900 FCLK to be stable with a huge variety of voltage and ProcODT combinations, without much success. Decided to stay with 3600 14-15-14-28 which has been perfectly stable for more than a month, until AMD fixes AGESA or someone figures out the root cause of the WHEAs at 1900+ FCLK. Any ideas whether there's anything that can be done better with this setup now?
> 
> View attachment 2478280


You can try these timings. im using vsoc 1.5 in bios but with vdroop sits between 1.11 and 1.125. 1.5v vdimm


----------



## MageTank

craxton said:


> *can someone please explain if 4 sticks of single rank work similar as dual rank 2 sticks? or 4 sticks of dual rank etc????* i asked @Veii but hes gotta load to respond to. (asking anyone who knows and not taking a guess.) also, i wrote MSI about adding CPU VDDP voltage to their b550 bios but havent received anything back yet. ALSO running 4000mhz stable with 2000fclk with 1.46Vdimm (llc3) on the darkpro sticks from teamgroup. something to consider i suppose for those not willing to use 1.5 volts for anything around 4000mhz considering most all need 1.5 or higher. 52.3ns latency etc. so far best ive gotten.
> 
> TM5, HCI both passed. have yet to try y-cruncher or prime. as im working first shift and not a morning person to which when i get home im ready for no more headaches....
> View attachment 2478219


I can try, but understand that some of this information might not be entirely accurate (I do not have precise information on how AMD's memory controller handles ranks across different DIMM's in different channels, but I am sure others more knowledgeable can confirm or dispute my theory)

Two dual rank DIMM's in my personal testing has out-performed 4 single rank DIMM's consistently when all variables are controlled (timings, frequency, voltage, etc). My theory for this is that with 4 single rank DIMM's, all DIMM's operate in parallel. It's 8 groups, 4 sticks, 4 ranks, and all recharging halts the entire stack. With dual rank DIMM's, even with just 2 of them, it's 8 groups, 2 sticks, 4* ranks, and the ranks do not operate in parallel, they operate interleaved. This means that while 1 is recharging, the CPU can use the other, resulting in no dead time.

DDR4 did introduce an improved bank-interleave and _DG interleave which was definitely an improvement, but it's still not akin to real rank interleaving, where you could read from one rank while simultaneously writing to another. You can get lockstep rank interleave with 4 single rank sticks, but only at the cost of half of your capacity and heavy tweaking of _DG (different group) timings in order to maintain performance improvement. This depends heavily on the IMC though, and if Ryzen's IMC doesn't support this, then you do not get rank interleaving with 4 single rank DIMM's, but given the performance boost everyone is seeing when using 4 single rank DIMM's, I am left to assume it does support this lockstep rank interleaving. 

Again, this is just theoretical, I do not know this to be fact as I myself just purchased my 5950X a few months back, jumping ship from Intel after almost a decade long hiatus from AMD. If someone more experienced with Ryzen's memory controller could chime in, I'd appreciate it.


----------



## BarrettDotFifty

heptilion said:


> You can try these timings. im using vsoc 1.5 in bios but with vdroop sits between 1.11 and 1.125. 1.5v vdimm
> 
> View attachment 2478282


Thanks. Do you think the vdroop could be a cause of instability/WHEAs? I'm trying to figure out a way to test stability with as least side effects as possible.


----------



## KedarWolf

bigblueshock said:


> Anyone with 4 DIMMS running a 5000 series at 3800 mhz/ 1900 FCLK? Right now I'm stable at 3733/1866 Cas14 just as I was with my old 3900x. I'm trying to get Cas 14 at 3800/1900.
> 
> I tried adjusting some timings but did not have luck booting 3800/1900 1.50V at Cas 14. I have a Memory Cooler and am using decent B-Die: F4-3600C15D-16GTZ
> 
> Is there a baseline somewhere of Important Timings? For instance: TCL, tRCDWR, tRCDRD, tRP, tRAS. ProcODT, RttNom, RttWr, RttPark, and all the DrvStr's. GDM Enabled considering I'm running 4 sticks. VSOC, VDDG/VDDP? I assume I will at least need 1.50V to run 3800 Cas 14.


This is what I use. It's WHEA free as well.


----------



## Ramad

I'm posting this as a help for those that are looking for usable and tested timings that are stable. This may help you achieve 3800MT/s if you are too is using the same memory as mine on an X570 motherboard.

*Hardware, voltages and settings:*

Motherboard: MSI X570 Tomahawk
CPU: Ryzen 2700X (Zen+) clocked at 4.2GHz @1.375V Vcore, SOC @1.05V, CLDO_VDDP @1V, CPU 1.8V @1.85V
RAM: 2 X 8GB Crucial rev. E (8 Gbit, single rank) @1.35V, VTT @0.6V (you can use any voltage between VDDR/2 to 0.6V), VPP @2.6V
RTT (-NOM, -WR, -Park): I have made 2 runs, both are stable as long as RTTNOM is disabled (the RAM will error at some point if RTTNOM is enabled at any value):
 1: Disabled - RZQ/3 (80 Ohm)- RZQ/1 (240 Ohm) 2: Disabled - RZQ/3 (80 Ohm) - RZQ/5 (48 Ohm) 
Edit: made a 3rd run using: Disabled - RZQ/3 (80 Ohm)- RZQ/2 (120 Ohm) (and PROCODT of 43.6 Ohm instead of 48 Ohm, 43.6 Ohm used to be unstable at training/boot when used with run 1, this is why 48 Ohm is used for run 1 and 2 so 43.6 Ohm may also be stable using a run 2 settings. This is a minor change and may very well be limited to my CPU, but it's a change and I feel that have to be noted here).


*Used timings:*

Primaries are tuned manually (tCL to tRC)
Secondary timings are 2133MT/s timings for a 1KB page size (applies to tRRD_S/-_L and tFAW)
IMC timings are manually tuned
tRFC/-2/-4 are calculated for 3800MT/s
Gear Down: Enabled @1T

*RTT (-NOM, -WR, -Park): Disabled - RZQ/3 (80 Ohm)- RZQ/1 (240 Ohm), testing with 12GB of RAM: *











*RTT (-NOM, -WR, -Park): Disabled - RZQ/3 (80 Ohm) - RZQ/5 (48 Ohm), testing with 12GB of RAM:*











*RTT (-NOM, -WR, -Park): Disabled - RZQ/3 (80 Ohm) - RZQ/2 (120 Ohm), testing with 12GB of RAM :








*


----------



## KedarWolf

KedarWolf said:


> This is what I use. It's WHEA free as well.


----------



## Sleepycat

Anyone running 64GB RAM (4 sticks of 16GB B-die) at any speed higher than 3600? I understand that this is a big strain on the CPU's memory controller.

Regardless of SOC and DRAM voltage, I have not been able to go beyond the 3600 wall and even POST successfully. At 3600, everything is very nice. CL14-15-14-28 CR1, GDM on. But nothing works at 3666 or higher. 

Taking out 2 sticks, I can reach 3866 CL16-16-16-32 CR1.


----------



## heptilion

KedarWolf said:


> View attachment 2478362


why such high proc odt? i thought you were stable on 36.9


----------



## heptilion

BarrettDotFifty said:


> Thanks. Do you think the vdroop could be a cause of instability/WHEAs? I'm trying to figure out a way to test stability with as least side effects as possible.


i think vdroop can cause whea errors. i was stable testmem occt ycruncher at 1.3125 bios( 1.1 in hwinfo) but get odd whea error when play warzone. so i have upped my vsoc a bit. have passed testmem and occt on the timings i have given you above and so far warzone is whea free fingers crossed.


----------



## KedarWolf

heptilion said:


> why such high proc odt? i thought you were stable on 36.9


In long TM5 tests, I was getting a few errors, like in seven-hour tests. So I raised it.

I probably get away with 40 or something but haven't tested it.


----------



## Veii

craxton said:


> can someone please explain if 4 sticks of single rank work similar as dual rank 2 sticks? or 4 sticks of dual rank etc???? i asked @Veii but hes gotta load to respond to.
> View attachment 2478219


Yes 
tWRRD is a bit lower on 2 dimms, but yes
tWR is a bit higher on 2 dimms, going by the capacity

This is stable right ?
tCKE 11 doesnt work for you ?
11 would be for 4000 , 12 already near 4167

What's the latency on this set ?
SCL 4-4 , tWRRD 4 doesn't work out ?

Do you use CAD_BUS 40-20-20-20 because it works
or because you where told to do so ?
i miss CAD_BUS Timings, with that X-20-20-20




Snipie-PT said:


> @Veii , can you please give me some advise to achieve IF2000 without WHEA?
> Currently running the below settings and stable, I can even achieve IF2100 but always with WHEA errors and I have no idea where to start.
> Some advise or guide would be great, running 4 SR DIMM's (B-Die).
> 
> View attachment 2478167


no "L" in the name 
Lower CPU VDDP if you have access to it
And use IOD of 1060 
then adjust SOC accordingly ~ although yours is "fine" already

give CCD -10mV
and lower CCD till you hit CPU_VDDP equilibrium 
Keep using Y-cruncher FFT tests, overall all tests 
till you can pass 2 loops of all (at best 4 loops)
if you have no errors there ~ then WHEA is from something else
They have numbers , these WHEA errors ~ and always mean something else 

could be ethernet that's erroring, could be PCIe 4.0 which crashes
could be many things ~ soo start with being y-cruncher stable
* Also you'd want to have PBO limits in place, else your system will overheat on the 2nd and 3rd test


----------



## Veii

dimi0815 said:


> I was just wondering whether the 50.5 ns latency was something only achievable with single ranked DIMMs, i.e. whether at the exact same primary, secondary and tertiary timings (assuming identical stability, too) I would still have to expect different latency results due to double the amount of ranks.
> 
> 
> MageTank said:
> 
> 
> 
> m still working on achieving 24/7 stability, but my results are looking very close to yours. @Veii 's latency result isn't common, nor should you consider it to be given his experience. You'll likely get there over time, but if this is your first time memory overclocking on AMD, or your first attempt at it since the old Phenom days like mine, expect there to be some bumps along the way.
Click to expand...

Near 52 is achievable for 4 dimms @dimi0815
But your Core "voltage supply" starts to matter

This is from psone @ chiphell


Spoiler














And a similar from me


Spoiler














His needed 1.72v, my atm 1.6v
I think it can be better - but it still hits 50.3ns
The real limit is the powerlimit and the "apparently not hardlocked" EDC limit per chip
5600X being 120A before fixes, 5900X being 200A

Unless your board has a "motherboard" PBO limit, which overrides that nonsense (under Scalar X1)
you will continuously fall into the EDC limit and let your cores throttle
Effectively nullifying your memOC ~ although bandwidth is higher and technically game perf is higher by higher FCLK alltogether
Just as exchange, render perf is lower - as it will hit faster the EDC limit

52-53ns is normal
Lower then 52 you need to adjust Curve Optimizer making all cores behave pretty much equal on allcore loads ~ which not only counts Cinebench, but also Y-Cruncher
(fixing loadlines to droop more , or fixing them higher with an allcore)
* although an allcore beyond 1.2v , on AVX2 FFT small tests from y-cruncher . .. unclear
It will crash quite fast beyond 1.18v ~ eh you'll notice 


heptilion said:


> @Veii What LLC level are you using on the dark hero? And switching frequency for vsoc? Should I play around with LLC for CPU as well?





Spoiler: These are loadlines setup for CTR





















They are not perfect but slightly lower results - result in too fast voltage chokes/shutdowns

Although even these ones do have shutdowns at 1.087v @ 4.7
But let's say quality of them is 98%
It can be better ~ but they are already well usable
As for normal PBO operation ~ the C8DH is plagued by 40ghz spikes. Haven't found a good PBO loadline ~ except that you need to let it droop
Also it's plagued by 3 broken PBOs , which all of them have a 200A EDC hardlock
4.7 @ 1.15VID needs 200W cooling ~ soo it's work in progress (watercool in progress) 



Sleepycat said:


> Anyone running 64GB RAM (4 sticks of 16GB B-die) at any speed higher than 3600? I understand that this is a big strain on the CPU's memory controller.
> 
> Regardless of SOC and DRAM voltage, I have not been able to go beyond the 3600 wall and even POST successfully. At 3600, everything is very nice. CL14-15-14-28 CR1, GDM on. But nothing works at 3666 or higher.
> 
> Taking out 2 sticks, I can reach 3866 CL16-16-16-32 CR1.


Work in progress by「halcyonon」
but yet not showcase'able
He's thermal crashing so far ~ soo you might have better luck


Spoiler














RTTs need a change
Forget GDM, work with GDM off 2T
GDM on masks badly powered dimms 
Also it's 0.4 - 0.5ns faster without additional needed voltage


----------



## craxton

Veii said:


> Yes
> tWRRD is a bit lower on 2 dimms, but yes
> tWR is a bit higher on 2 dimms, going by the capacity
> 
> This is stable right ?
> tCKE 11 doesnt work for you ?
> 11 would be for 4000 , 12 already near 4167
> 
> What's the latency on this set ?
> SCL 4-4 , tWRRD 4 doesn't work out ?
> 
> Do you use CAD_BUS 40-20-20-20 because it works
> or because you where told to do so ?
> i miss CAD_BUS Timings, with that X-20-20-20
> 
> 
> 
> no "L" in the name
> Lower CPU VDDP if you have access to it
> And use IOD of 1060
> then adjust SOC accordingly ~ although yours is "fine" already
> 
> give CCD -10mV
> and lower CCD till you hit CPU_VDDP equilibrium
> Keep using Y-cruncher FFT tests, overall all tests
> till you can pass 2 loops of all (at best 4 loops)
> if you have no errors there ~ then WHEA is from something else
> They have numbers , these WHEA errors ~ and always mean something else
> 
> could be ethernet that's erroring, could be PCIe 4.0 which crashes
> could be many things ~ soo start with being y-cruncher stable
> * Also you'd want to have PBO limits in place, else your system will overheat on the 2nd and 3rd test


its what i was told to use, i switched tcke to auto and 16 is what the board set that as. no its not HCI stable, TM5 stable yes at 1.45 vdimm even???? just testing tRC 50 and tRAS 34 as two sticks (same as the other two but tRC on two is 47 the other two is tRC 97?) 

had switched sticks around where each was in its own lane, to now where one stick is working with the lesser stick, but still not stable. and 40 20 20 20 worked better than what im sharing now. was down to one error. now am stacking 4 per 1000% HCI.

(did not switch tRFC as i wasnt thinking but did go back and switch it with what your mini calc said to switch it to). but still not stable. noticing a big difference when using procODT 34 with high variances with latency and read speeds. I am not however running a fan over these sticks so, they perhaps are stable with what timings you gave mogol but are heat soaking. then again its rather cold year round in my room here at home.

tCKE 11 works fine as well as 9 does too, will edit shortly with what i had with 1 error out of 5 HCI runs each one returned 1 error around 800% to 1000% runs.
ClkDrvStr 40 works best on my sticks period and 52.3 is latency even when errors come about. if i try AddrCmd, CsOdt, CkeSetup timings at all the board goes into a nopost and doesnt come back to where i must reset the bios.


----------



## KedarWolf

heptilion said:


> why such high proc odt? i thought you were stable on 36.9


Ran TM5 for seven hours last night. Stable at 40 proc odt.


----------



## craxton

Veii said:


> Yes
> tWRRD is a bit lower on 2 dimms, but yes
> tWR is a bit higher on 2 dimms, going by the capacity
> 
> This is stable right ?
> tCKE 11 doesnt work for you ?
> 11 would be for 4000 , 12 already near 4167
> 
> What's the latency on this set ?
> SCL 4-4 , tWRRD 4 doesn't work out ?
> 
> Do you use CAD_BUS 40-20-20-20 because it works
> or because you where told to do so ?
> i miss CAD_BUS Timings, with that X-20-20-20
> 
> 
> 
> no "L" in the name
> Lower CPU VDDP if you have access to it
> And use IOD of 1060
> then adjust SOC accordingly ~ although yours is "fine" already
> 
> give CCD -10mV
> and lower CCD till you hit CPU_VDDP equilibrium
> Keep using Y-cruncher FFT tests, overall all tests
> till you can pass 2 loops of all (at best 4 loops)
> if you have no errors there ~ then WHEA is from something else
> They have numbers , these WHEA errors ~ and always mean something else
> 
> could be ethernet that's erroring, could be PCIe 4.0 which crashes
> could be many things ~ soo start with being y-cruncher stable
> * Also you'd want to have PBO limits in place, else your system will overheat on the 2nd and 3rd test


so far so good on Prime 95 Small FFT hitting 84c right now tho so kinda iffy to leave it running while i take a trip to another town which will take a few hours....


----------



## craxton

Veii said:


> Yes
> tWRRD is a bit lower on 2 dimms, but yes
> tWR is a bit higher on 2 dimms, going by the capacity
> 
> This is stable right ?
> tCKE 11 doesnt work for you ?
> 11 would be for 4000 , 12 already near 4167
> 
> What's the latency on this set ?
> SCL 4-4 , tWRRD 4 doesn't work out ?
> 
> Do you use CAD_BUS 40-20-20-20 because it works
> or because you where told to do so ?
> i miss CAD_BUS Timings, with that X-20-20-20


A little update, passed 3 hours of sff prime95, passed 3 runs of y-cruncher, now on to HCI overnight and if that passes without errors I'll retest y-cruncher for 4 full passes. Then prime again overnight. 

Used 4-4-18 and that WORKED don't know why it did not before. Will grab a shot of the timings and aida bench tomorrow as midnight approaches here and work is early. Anyhow, just thought I'd say thank you for the insight you've given. 

And to @MageTank thank you as well for you response which helped more than I imagined as it was clear and I knew what to look for, with veii document links etc.


----------



## Veii

Nothing special yet, just low voltage timings for 4 x 8GB A2
3967 works, 4000 refuses on this Bios fully ~ it's a less broken mess than 3204
Negative vCore because of curve optimizer (as test) on Core 6 as +18








It's an interesting sample, but CCD2 is plain bad
CCD one runs at 1150mV near 4.6, CCD2 just is able to run 4.35
It's investigation in progress if Curve Optimizer helped that bad Core

Good loadlines stay the same as above, just with CPU VRM Phase to Extreme = Full Phase Mode
Also CTR user - be sure it's y-cruncher stable
This means BBP, SFT, FFT, C17 stable
Yuri's tests are not harsh enough. SFT & BBP AVX2 small data set pretty much wr*cks his founded settings
* P95 Small FFT is also not harsh enough
ZenState 2.0, TurboV and Y-Cruncher are your friends

ASUS users can apply the VID it spills out or they tested by themself ~ in the per CCX Tab
But use a positive vCore offset ontop of Curve Optimizer ~ for Per CCX / Hybrid Mode OC Stability @ X1 Scalar
OTP is 90c unless changed manually by AMD Overclocking PBO 
CBS & Main Menu PBO are a mess. Motherboard limits are a mess
Set throttle limit to 95c instead of 92, else you will keep on having OTP shutdowns on y-cruncher (per CCX guys)


----------



## LicSqualo

Hi Veii, I'm happy to discover (today) that I was your "Arch'enemy" in Sisoft Sandra inter-core bandwith. Happy to have push you on the first rank


----------



## Veii

LicSqualo said:


> Hi Veii, I'm happy to discover (today) that I was your "Arch'enemy" in Sisoft Sandra inter-core bandwith. Happy to have push you on the first rank


Haha 
It needs work - 3.8 was the max it wanted. A too hot chip
But memory can take some work. Good Job !

There was one person which played with BLCK, but got invalidated 
Still have the chip here, it's lapped and shiny ~ but Vermeer is more interesting right now
1200AF is also here waiting lapped for tests ~ but eh someday


----------



## mongoled

Is it normal that our Sandra scores are not "validated" because they are outliers ??

Ive hit 89GB+ on this 5600x, but its never accepted as a valid result ...

:/


----------



## Veii

mongoled said:


> Is it normal that our Sandra scores are not "validated" because they are outliers ??
> 
> Ive hit 89GB+ on this 5600x, but its never accepted as a valid result ...
> 
> :/


The leaderboard should also have "invalid" results
but you need to be logged in to upload it
Invalid in "too high coefficiency/variability" or which type of "invalid" ?


----------



## mongoled

Veii said:


> The leaderboard should also have "invalid" results
> but you need to be logged in to upload it
> Invalid in "too high coefficiency/variability" or which type of "invalid" ?


Ahhh, i never sign in.

The message where the result is "Variable Result: Large Deviation ".

I have the top result with my previous X370/3600 combo, but its obviously an erroneous score, but there is no way to delete it!

LOL, managed to create this search query

Top Processor Multi-Core Efficiency Ranks : SiSoftware Official Live Ranker 

Most are mine

😆😆


----------



## Veii

mongoled said:


> Ahhh, i never sign in.


The button is sadly hidden, i forgot where it is. User Experience on this tool is really bad ~ but it's useful 
Once it asks you to login , you can just put your name there. A Random e-mail you have to remember, and a password
Also select the Team if either global or brand focused ~ well or by having an own Team
I'm registered as Global, but forgot my account data (kinda) 

Change then the login delay to 99 days, instead of 3 - and you are good to go
They don't send any verification mails, nor can you password reset (haven't figured it out ~ seems to be no option at all)


----------



## LicSqualo

These are my actual settings (same for 4 years from 2017)


----------



## Veii

LicSqualo said:


> These are my actual settings (same for 4 years from 2017)
> 
> View attachment 2478584


Does it pass linpack extreme (version 1.1.1) or y-cruncher
i wonder why Sandra shows too large result deviation ~ something is strange for them

I wonder about cLDO_VDDP 950
Is this perfect for memory hole, or did you use it for some other logic. 3500MT/s is really high on 1700X 
You can not run tRC 35 with different tRFC ?
You beat my by a big bit on coreOC, but somehow your memOC part is not great

I think you still have a bit to gain from this CPU 😇


----------



## LicSqualo

Veii said:


> Does it pass linpack extreme (version 1.1.1) or y-cruncher
> i wonder why Sandra shows too large result deviation ~ something is strange for them
> 
> I wonder about cLDO_VDDP 950
> Is this perfect for memory hole, or did you use it for some other logic. 3500MT/s is really high on 1700X
> You can not run tRC 35 with different tRFC ?
> You beat my by a big bit on coreOC, but somehow your memOC part is not great
> 
> I think you still have a bit to gain from this CPU 😇


Just tried y-cruncher, passed.
cLDO_VDDP is in auto, never changed. 
I will try tRC at 35, as you proposed. tRFC will be good at 250 or better at 248?
My best clock is 4140 MHz, with x41 and 101 bclk, not stable because i never passed 1,42V with LLC3. Perhaps with more volts...
Thank you for your interesting, much appreciated.


----------



## craxton

@Veii THANK YOU THANKYOU THANNNKKKK YOOOUUUU!!!!!!!! i do believe i can lower vdimm a tad, and possibly SOC as well. but for now this passed, TM5 100%, HCI 1000% (overnight) and 4 runs of y-cruncher back to back infinite loop which is using keys 1,7,0. the cadbus timings in your list a few pages back i took screen shots of on my phone (as i do with dam near everything you say about timings for 4dimm, dual channel etc. but anyhow passed finally. now i wonder if this will stabilize 1T..... copy speed goes go from 569** to 57*** so idk if thats saying something is not right or if thats normal. latency stays the same at 52.4 or 52.3 never any higher or lower .1 variations is normal from what i recall you stating a few more pages back.

i still didnt allow prime to do an overnight stress test, but i couldnt not come on and spam the post with 3 tests passing (i didnt get proof but taking my word you must.) i did however change tfaw to 4xtRRDS which is what you suggest on page 261 (have that page bookmarked as many others should as well considering theres quite some info to help struggles be passed.) anyhow these are my results. 4x8gb teamgroup 3200c14 dark pro *TDPGD416G3200HC14ADC01 (*amazon is out of stock, but newegg has the kits listed but the tRC timing is no longer 45 as the sticks once were. its now 97.) id guess there is more left in these sticks somewhere. but rather or not i find it ill pass for now.


----------



## Veii

LicSqualo said:


> Just tried y-cruncher, passed.
> cLDO_VDDP is in auto, never changed.
> I will try tRC at 35, as you proposed. tRFC will be good at 250 or better at 248?
> My best clock is 4140 MHz, with x41 and 101 bclk, not stable because i never passed 1,42V with LLC3. Perhaps with more volts...
> Thank you for your interesting, much appreciated.
> 
> View attachment 2478601


y-cruncher all tests (1-7-0)
Increase tRRD_L to 5, lower tWTR_L to 10 and see if there is any improvement
Try tRFC 245-182-112, tWR 14 tRTP 10 or 6, 
or get GDM off 2T and tWR 14, tRTP 7 ~ on the same tRFC 245


craxton said:


> @Veii THANK YOU THANKYOU THANNNKKKK YOOOUUUU!!!!!!!! i do believe i can lower vdimm a tad, and possibly SOC as well. but for now this passed, TM5 100%, HCI 1000% (overnight) and 4 runs of y-cruncher back to back infinite loop which is using keys 1,7,0. the cadbus timings in your list a few pages back i took screen shots of on my phone (as i do with dam near everything you say about timings for 4dimm, dual channel etc. but anyhow passed finally. now i wonder if this will stabilize 1T..... copy speed goes go from 569** to 57*** so idk if thats saying something is not right or if thats normal. latency stays the same at 52.4 or 52.3 never any higher or lower .1 variations is normal from what i recall you stating a few more pages back.
> 
> i still didnt allow prime to do an overnight stress test, but i couldnt not come on and spam the post with 3 tests passing (i didnt get proof but taking my word you must.) i did however change tfaw to 4xtRRDS which is what you suggest on page 261 (have that page bookmarked as many others should as well considering theres quite some info to help struggles be passed.) anyhow these are my results. 4x8gb teamgroup 3200c14 dark pro *TDPGD416G3200HC14ADC01 (*amazon is out of stock, but newegg has the kits listed but the tRC timing is no longer 45 as the sticks once were. its now 97.) id guess there is more left in these sticks somewhere. but rather or not i find it ill pass for now.
> View attachment 2478606
> View attachment 2478607


I'm happy it worked for you
It's strange that you need CAD_BUS X-20-24-24 instead of X-20-20-20 , but it's good to know
Also very good to know that 4-4-18 works for you.

Noted it down, thank you for confirming
But doublecheck Aida64 with 40 and 36.9 procODT
9-4 like visible a bit above @ 1.35v should run on 3800
Meaning likely it will run for you too.

But that's something for another time to test.
The most important part, is WHEA free and RTT + CAD_BUS settings are correct
It's rarely "replicatable" by the variance of dimms that exist.
Eh , i'm happy it works.
But keep








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Anyone with 4 DIMMS running a 5000 series at 3800 mhz/ 1900 FCLK? Right now I'm stable at 3733/1866 Cas14 just as I was with my old 3900x. I'm trying to get Cas 14 at 3800/1900. I tried adjusting some timings but did not have luck booting 3800/1900 1.50V at Cas 14. I have a Memory Cooler and...




www.overclock.net




as fallback option for very easy to run timings @ 1.36v (probably 1.35 works too)
Low tRFC doesn't always have to use high vDIMM 

EDIT:
tRRD_L 7 doesn't work for you ?
Can you doublecheck if it makes any perf difference without stability testing


----------



## mongoled

Re Sandra,

here is what Sandra says

"Unexpected Result: Outlier (outside 99.7% Confidence Interval)"










I also noted that there are very few entries for 5600x CPUs in the Sandra Processor Multi-Core Efficiency database

** shrug **


----------



## craxton

Veii said:


> I'm happy it worked for you
> It's strange that you need CAD_BUS X-20-24-24 instead of X-20-20-20 , but it's good to know
> Also very good to know that 4-4-18 works for you.
> 
> Noted it down, thank you for confirming
> But doublecheck Aida64 with 40 and 36.9 procODT
> 9-4 like visible a bit above @ 1.35v should run on 3800
> Meaning likely it will run for you too.
> 
> But that's something for another time to test.
> The most important part, is WHEA free and RTT + CAD_BUS settings are correct
> It's rarely "replicatable" by the variance of dimms that exist.
> Eh , i'm happy it works.
> But keep
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Anyone with 4 DIMMS running a 5000 series at 3800 mhz/ 1900 FCLK? Right now I'm stable at 3733/1866 Cas14 just as I was with my old 3900x. I'm trying to get Cas 14 at 3800/1900. I tried adjusting some timings but did not have luck booting 3800/1900 1.50V at Cas 14. I have a Memory Cooler and...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> as fallback option for very easy to run timings @ 1.36v (probably 1.35 works too)
> Low tRFC doesn't always have to use high vDIMM
> 
> EDIT:
> tRRD_L 7 doesn't work for you ?
> Can you doublecheck if it makes any perf difference without stability testing


Not an issue, i only use x-20-24-24 bc thats what the board wanted so thats what i set it to in the bios
keep it from switching or doing something strange. did pass so im leaving those alone for the time being.

with tRRD L 7 latency goes up and down but does lower it to 52.1 from 52.3 but isnt consistent
this is with 0-1%cpu usage and the minimal tasks running to keep windows happy enough
i did drop vdimm down to 1.46, tried soc 1.16/17 but was showing instability with latency and read speeds
fluctuating up and down to much so i raised it back up and saved the profile to a flash drive incase i tinker
thus needing to reset the bios which sometimes clears all profiles saved to the board

i have yet tested procODT down from 40 but ill give it a shot and report back with my findings.
copy speeds with tRRD_L 7 still go up and down from 574xx to 568xx ill still assume this is normal.
if i use the timings i currently have and use 3800, 39xx, or anything under 4000mhz my memory score
drops SIGNIFICANTLY and latency hits 60ns at best.

i did not however check the timings of the 3800mhz you mentioned so perhaps those are quite a bit better at 3800
while performing the same as 4000 while keep soc under 1.2 for degradation sakes and vdimm under 1.45 for heat soaking.

i will note that it was (*EXTRA*) cold in my room last night while running HCI. and i left the side panel off for all the tests ive managed so far.
with 100% full tilt to all 9 120mm fans, and all 3 of the 2070S ftw3 ultra fans as well.
i did however turn it all down and ran y-cruncher again 3 times back to back and had no issues
CPU didnt boost however due to how i limited PBO values with ryzen master to keep throttling from happening, but all else was fine.

will test procODT settings now and see if latency continues to drop, or shows signs of instability
i also changed tRFC to 288-214-132 which i believe is as tight on tRFC as i can get without causing more issues
and adding voltage.


----------



## kratosatlante

mongoled said:


> Re Sandra,
> 
> here is what Sandra says
> 
> "Unexpected Result: Outlier (outside 99.7% Confidence Interval)"
> 
> View attachment 2478654
> 
> 
> I also noted that there are very few entries for 5600x CPUs in the Sandra Processor Multi-Core Efficiency database
> 
> ** shrug **


mine similar result, old test for temperature compare(cb20 raise temperature to 83c , aida multicore to 88c), bios 4007 ch7wifi firs pbo + 275, 2nd pbo + 150 and curve optimizer dont remember the numer, same all core














working now, retest tonigh with actual config and last bios


----------



## craxton

did a user bench run with curve applied for a change (per core curve i forget atm what i set but 4 cores are -10 and the other 2 are -3 i think?)



MSI MPG B550 GAMING EDGE WIFI (MS-7C91) Performance Results - UserBenchmark


----------



## craxton

mongoled said:


> Re Sandra,
> 
> here is what Sandra says
> 
> "Unexpected Result: Outlier (outside 99.7% Confidence Interval)"
> 
> View attachment 2478654
> 
> 
> I also noted that there are very few entries for 5600x CPUs in the Sandra Processor Multi-Core Efficiency database
> 
> ** shrug **


What tests are you guys running in sisandra? Have seen it brought about one to many times for my curiosity not to get the best of me now. So I downloaded, but are you fellas using static cpu oc, auto cpu oc, and are you running cpu tests only, all tests, or just memory tests?


----------



## domdtxdissar

craxton said:


> did a user bench run with curve applied for a change (per core curve i forget atm what i set but 4 cores are -10 and the other 2 are -3 i think?)
> 
> 
> 
> MSI MPG B550 GAMING EDGE WIFI (MS-7C91) Performance Results - UserBenchmark


Here is my 5950x with PBO CO -30 allcore on agesa 1.2.0.0 bios
4x 8gigabyte @ 1900/3800 mem on dual CCX CPU which is harder to run than single CCX


Asus ROG CROSSHAIR VIII HERO (WI-FI) Performance Results - UserBenchmark



Seems like i have lower latency in userbenchmark and/or dram calculator bench (?)








Geekbench latency:
GB4 @ ASUS System Product Name - Geekbench Browser
GB5 @ ASUS System Product Name - Geekbench Browser

And some Y-crusher numbers:










_edit_
Found a screenshot with lower aida latency on ~same settings with a older bios with agesa 1.1.8.0
1 hour prime with AVX, small ffts run


----------



## Dasa

I have been trying to fine tune settings to reduce WHEA when running OCCT at 1933IF but there seems to be to much variance in training at boot with some boots getting 15 WHEA per minute and other boots getting under 1 WHEA per minute.
A lot of these settings could be a bit loser than they need to be and V may be a fair bit higher than it needs it is just hard to know how much difference the changes I make are having with that variance of settings that cant be seen.
Kinda makes me wish for the days of DFI BIOS where there was enough settings to bury you alive even if they were a bit twitchy.


----------



## KedarWolf

OCCT again, but with the Extreme preset. It's more likely to find WHEA errors than the default preset.


----------



## craxton

whats this mean exactly ?? and how do i use it @ ANYONE familiar with CTR ? ctr ran for almost 2 hours btw. only thing i changed was cycle time and set 1300mv for diag voltage.


----------



## craxton

(EDIT) since ive not been answered ive went and searched and looked 
(on this thread and all of google across other search engines as well.)
i do not know what operations is underneath WHEA errors inside the event logger but, 
ive ran OCCT 8.0.0.b8 beta under extreme, AVX2, large, extreme, variable, all threads for 30 minutes now and 
no errors inside the event viewer under WHEA error folder section came up. 

so, i suppose the operations section i need not worry about? 
i also installed the HDMI audio, and USB-C drivers for the graphics card cleared the log after rebooted the pc, 
under the operations tab the same thing noted below still came about. 

so, unless someone states that this is indeed a WHEA error then im happy. 
if not, then i suppose ill reset the bios (having saved the profile) and check to see if the problem still comes about. 
*all i wish to know is yes this is an error or no its nothing to worry about.*

found this which tells me event ID 42 is WHEALOGR_PCIXBUS_NODEVICEID_ERROR 
which i can find no info to if its related to display (PCI) or a pci lane, or ? lost on it honestly.

does not create more logs whatsoever. only time it shows this under operations (underneath WHEA error tab) is when i reboot the pc.
other than that, nothing. cant make it happen with stress tests, benchmarks, or none of the like. 

(original-> Question), im showing some screenshots, i cleared the kernel log last error it had reported was december something 14th i think


----------



## ManniX-ITA

craxton said:


> (EDIT) since ive not been answered ive went and searched and looked
> (on this thread and all of google across other search engines as well.)
> i do not know what operations is underneath WHEA errors inside the event logger but,
> ive ran OCCT 8.0.0.b8 beta under extreme, AVX2, large, extreme, variable, all threads for 30 minutes now and
> no errors inside the event viewer under WHEA error folder section came up.
> 
> so, i suppose the operations section i need not worry about?
> i also installed the HDMI audio, and USB-C drivers for the graphics card cleared the log after rebooted the pc,
> under the operations tab the same thing noted below still came about.
> 
> so, unless someone states that this is indeed a WHEA error then im happy.
> if not, then i suppose ill reset the bios (having saved the profile) and check to see if the problem still comes about.
> *all i wish to know is yes this is an error or no its nothing to worry about.*
> 
> found this which tells me event ID 42 is WHEALOGR_PCIXBUS_NODEVICEID_ERROR
> which i can find no info to if its related to display (PCI) or a pci lane, or ? lost on it honestly.
> 
> does not create more logs whatsoever. only time it shows this under operations (underneath WHEA error tab) is when i reboot the pc.
> other than that, nothing. cant make it happen with stress tests, benchmarks, or none of the like.
> 
> (original-> Question), im showing some screenshots, i cleared the kernel log last error it had reported was december something 14th i think
> 
> View attachment 2478752


You could have an issue with the WHEA-Logger and it's not correctly reporting the errors.

What you are looking at are the logs for the Logger, no the actual events with details.
To check the events you should create a custom filter like this under Custom Views:










Does the Event ID 5 in Operational looks like this?










Note that I have a clean Windows install without all the drivers, no AV, almost any software installed and it doesn't report a single WHEA error at any FCLK.
But the real Windows install I use it does report them as soon starts loading the desktop and all the massive amount of stuff I've installed.
So don't be surprised if at some point it starts reporting them out of the blue (hopefully not).


----------



## Veii

kratosatlante said:


> mine similar result, old test for temperature compare(cb20 raise temperature to 83c , aida multicore to 88c), bios 4007 ch7wifi firs pbo + 275, 2nd pbo + 150 and curve optimizer dont remember the numer, same all core
> View attachment 2478670
> View attachment 2478671
> working now, retest tonigh with actual config and last bios


The first 6 cores are not interesting - the frequency
Effective Core Frequency T0 is interesting. The first one can be with clock stretching.
On HWinfo Enable CPU Snapshot pooling (first settings menu, not sensor settings)
and use 6.35-4320 or 4330 for hibernated core tracking

10.6ns L3 is a bit on the high side for an OC
This seems to work although its not thaat optimal








jedi95/BoostTester


Simple tool for generating loads that should trigger maximum CPU boost clocks. - jedi95/BoostTester




github.com


----------



## mongoled

kratosatlante said:


> mine similar result, old test for temperature compare(cb20 raise temperature to 83c , aida multicore to 88c), bios 4007 ch7wifi firs pbo + 275, 2nd pbo + 150 and curve optimizer dont remember the numer, same all core
> View attachment 2478670
> View attachment 2478671
> working now, retest tonigh with actual config and last bios


I get a valid result when I set the PBO limits for the CPU to "Auto", once I define PPT/TDC/EDC to 142/95/280 then I get the "Outlier" message.

I think the Sandra database is offline for new entires.

Even with a "valid" result the new results dont appear online, just resolve to a dead link.



craxton said:


> What tests are you guys running in sisandra? Have seen it brought about one to many times for my curiosity not to get the best of me now. So I downloaded, but are you fellas using static cpu oc, auto cpu oc, and are you running cpu tests only, all tests, or just memory tests?


Only testing the Processor Multi-Core Efficiency test as Veii says it shows more accurately acute differences in changes in RAM frequency/timings


----------



## mirzet1976

HWinfo taken after SiSandra run


----------



## craxton

ManniX-ITA said:


> You could have an issue with the WHEA-Logger and it's not correctly reporting the errors.
> 
> What you are looking at are the logs for the Logger, no the actual events with details.
> To check the events you should create a custom filter like this under Custom Views:
> 
> View attachment 2478755
> 
> 
> Does the Event ID 5 in Operational looks like this?
> 
> View attachment 2478756
> 
> 
> Note that I have a clean Windows install without all the drivers, no AV, almost any software installed and it doesn't report a single WHEA error at any FCLK.
> But the real Windows install I use it does report them as soon starts loading the desktop and all the massive amount of stuff I've installed.
> So don't be surprised if at some point it starts reporting them out of the blue (hopefully not).


considering nothings changed since (January) not December. i believe id have to guess they are being reported correctly, but just to make sure i have a clean install from November i checked with. does the same thing, and this is a fresh, clean, ripped copy directly from Microsoft, created a small partion on one of my sata drives and well, it still does the exact same thing. i can create errors but not WHEA errors. idk, atm im not going to worry about it (i am worried about it) and am removing everything off an entire drive to make 100%sure and installing windows to it to test one more time) . i tried switching gen auto to gen 3 in bios for all pci options, installed the other two drivers i never use nor had installed ever, it could possibly have something to do with my pci extension cable. Then again who knows? and yes thats the same thing mine says but with 3 other entries that are the exact same thing event id 42. level: INFORMATION opCODE: INFO ???








(edit) on a new install completely fresh fully wiped, same thing. i do get one random thing that happens. (on both installs actually) my razor basilisk ultimate mouse (while hooked thru usb for charging) will act like its being disconnected and reconnected upon every 3rd or 4th click. but, from what i can gather its common for amd 5000 with this mouse at this time. supposed issue with razor software not amd in general? so im unsure.

anyhow shows the exact same 4 things in event viewer, which i cleared just now to restart the pc again after responding to this. will reedit and update if something different comes back, ran OCCT extreme for 30 minutes on both my win 10 installs and neither threw a single error nor did y-cruncher have any issues.

perhaps it actually is something hardware sided with my riser cable idk. running out of options to try and figure this out at this time. but yes it looks 100% like what you shared only 3 other entries and all say error id labeled as information i.d. 42. (to be clear, i only cleared the operations folder) and now am rebooting) 

after about 15 seconds ive rebooted and checked again, same 4 came back, nothing under errors only in operations so im lost...


----------



## craxton

mongoled said:


> I get a valid result when I set the PBO limits for the CPU to "Auto", once I define PPT/TDC/EDC to 142/95/280 then I get the "Outlier" message.
> 
> I think the Sandra database is offline for new entires.
> 
> Even with a "valid" result the new results dont appear online, just resolve to a dead link.
> 
> 
> Only testing the Processor Multi-Core Efficiency test as Veii says it shows more accurately acute differences in changes in RAM frequency/timings


so, this is the score id go by?


----------



## mongoled

craxton said:


> so, this is the score id go by?
> View attachment 2478803


That is the correct result for a CPU where the PBO is set to "Auto" settings, which I am assuming is what you are doing.?


----------



## craxton

mongoled said:


> That is the correct result for a CPU where the PBO is set to "Auto" settings, which I am assuming is what you are doing.?


(EIDT-->UPDATE) AUTO PBO, auto scaler no settings on cpu tuned by me. just ram is tuned....this good or bad?








no, pbo isnt on auto actually. 180,90,140 scalerx3 undervolted .0750mv. ill fix that shortly.

does sisa say theres a bios update in the tips section for you? when there isnt a bios update for your board?


----------



## ManniX-ITA

@craxton 
Looks to me all right, it may be error free

For the mouse, could be you may need more IOD?
I see you should be at 1060, maybe try 1080/1100.


----------



## KedarWolf

Passed OCCT Large Data Set Extreme and the latest OCCT Beta as well.


----------



## craxton

ManniX-ITA said:


> @craxton
> Looks to me all right, it may be error free
> 
> For the mouse, could be you may need more IOD?
> I see you should be at 1060, maybe try 1080/1100.


thought the same thing increased to 1100mv and tried auto. still happens while using charging cable.
(adding this bc i found that issue) i keep most services for things turned off or manual 
and run when i need them unless its certain things for windows. 

with that being sad, 
the usb cutout thru the mouse issue happens....WHEN i close razor software? 
bc its a memory hog and benchmark kill all on its own. 
my IOD at this time (has been since a few days now is at 1070mv with vdroop its 1068mv. 

so i believe this to be solved. and i installed the latest chipset drivers
and now closing razor software no longer causes the mouse to cut-out like it were before.
so perhaps it were amd driver issues? unsure but thank-you for your help much appreciated!


----------



## Trusconi85

Hello all,
i just go from x470 GB + 2700X to B550 Strix + 5600X
With everything stock (only xmp enabled) i have a CPUz score of 615/4750 and CB20 score of 4225
I have tested also the 5600x on the x470 with beta bios and result was 630/4800 and 4300
I have 4 stick of FlareX 3200c14
In another thread i ask to have some setting to OC the memory and you can see the result in attached files..








Asus ROG Strix B550-F Gaming/(WiFi) thread


Guys I noticed that there's new NON BETA BIOS for the E. And I downloaded it and now its gone from the website lol. Here's link if someone wants it. I dont know why ASUS removed it so fast -> ROG-STRIX-B550-E-GAMING-ASUS-1804.ZIP




www.overclock.net




I am not completely heppy because the scores of CB20 and CPUz are worse than stock+xmp
Can some one help me to find the best setting?

Thank you in advance

Manu


----------



## PJVol

Trusconi85 said:


> some one help me to find the best setting?


Not an asus board owner, but have seen it quite a few times, that their bioses have something like "fmax" feature set by default. If so, try to disable it and see if it will help.

*PS: Found it: "PBO FMax Enhancer" - it should be disabled with ryzen 5000's *


----------



## Frizzle012

Im trying to stabilize Corsair Dominator 4000 with Ryzen 9 5900x. 

Specs:
Corsair Dominator Platinum RGB 2x16 4000MHz
Asus ROG Crosshair VIII Dark Hero
Ryzen 9 5900x

I can turn on XMP and the memory will run seemingly without issues, but I was hoping to try and get the fabric clock closer to in line with the memory clock which I know is important for AMD CPU's.
The XMP profile is running at:
mclk: 4000
fclk: 1800
uclk: 1000
19-23-23-45 @ 1.35V

I CANT get the system to POST when setting my memory clock to 4000 and FCLK to 2000, however the system does POST for all values up to 3933/1966. I figured since it does POST and run at a 1:1:1 I could start here and optimize for this speed?

Is this a bad approach? Also, when running at 3933MHz the system is unusable, most applications take a long time to open and everything lags pretty bad. I was thinking that maybe I need to increase some voltages to stabilize the system at this frequency.

Reading here:https://www.tomshardware.com/reviews...zen-3-review/3 they got a similar configuration to run reliably by increasing the fabric voltages: "We had great results with memory overclocking with the Ryzen 9 5900X — we dialed in a 2000 MHz fabric and DDR4-4000 at a 1:1:1 fclk/uclk/mclk ratio, beating the best results we've reached with the previous-gen Matisse processors due to the general limit of a 1900 MHz fabric with the previous-gen chips. Just dial up the CCD and IOD voltage to 1.15V (not higher than 1.2V), and you should be good to go to increase the fabric clock to 2000 MHz."

Ive seem some folks say to increase the DRAM voltage as well to 1.40-1.45. I didnt want to make any of these tweaks yet until someone gave me a bit of a sanity check on if that should be the next step or if I should rewind a bit. Im new at this, so sorry for any ignorance.


----------



## craxton

Trusconi85 said:


> Hello all,
> i just go from x470 GB + 2700X to B550 Strix + 5600X
> With everything stock (only xmp enabled) i have a CPUz score of 615/4750 and CB20 score of 4225
> I have tested also the 5600x on the x470 with beta bios and result was 630/4800 and 4300
> I have 4 stick of FlareX 3200c14
> In another thread i ask to have some setting to OC the memory and you can see the result in attached files..
> 
> 
> 
> 
> 
> 
> 
> 
> Asus ROG Strix B550-F Gaming/(WiFi) thread
> 
> 
> Guys I noticed that there's new NON BETA BIOS for the E. And I downloaded it and now its gone from the website lol. Here's link if someone wants it. I dont know why ASUS removed it so fast -> ROG-STRIX-B550-E-GAMING-ASUS-1804.ZIP
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> I am not completely heppy because the scores of CB20 and CPUz are worse than stock+xmp
> Can some one help me to find the best setting?
> 
> Thank you in advance
> 
> Manu


are you using PBO scaler? are you enabling 200mhz auto oc?
are you using pbo values and not just leaving them to auto, or off? 
also, you should have lower latency than what your showing. 
when testing in aida close all programs and background tasks 
windows doesnt need to run before running your test to see if your tests are staying within a set range. 
as if nothing if running in the background, then latency shouldnt change more than .1ns if it does thats a sign of instability.

i currently just got 4 sticks of bdie (my kits are 2 kits (2x8) bought at different times, but are the same model)
(teamgroups dark pro) running on my 5600x stable. 
you can try my settings (as some are a copy and paste for 4 sticks) at 3800mhz and see what you get.
or even 4000. i do suggest, setting SOC voltage to at least 1.2, 
VDDG IOD voltage to 1060mv or 1070mv (testing without apps running back to back to see if your being consistent with latency etc. 
set CLDO VDDP voltage around .900mv or a tad more depends. 
shouldn need more than that tho. 
and lastly VDDG CCD .990mv (1000mv vdroop is still a thing even with LLC3 on an MSI b550 board with good vrms.

VDIMM on my sticks runs fine at 1.46/47 and doesnt really like anything higher than 1.48 so, 
thats on you. (make sure to set PBO values accordingly when running prime95, y-cruncher, OCCT etc. 
or itll make your chip extremely toasty. 

(i do believe your sticks should do these timings pretty easy 
as i copied most of them from a better ram kit (3800 c14 bdie kit) 
they worked fine for me. 

CADBUS TIMINGS ARE EXTREMLY IMPORTANT AND DO NOT FORGET THEM! 
otherwise it'll not get stable (or it may but itll be alot easier with correct cadbus timings.
I at least didnt see any sign of stability for a good while no matter what i did. 

my pbo (WIDE OPEN VALUES for R20, R23 benchmarks etc are 180-90-140.
but i do limit those with ryzen master when i run stress tests for WHEA errors etc.

im not an expert, but i do read most of everything i can that relates to ram/5000 series on this thread (coming from certian people)
you can look a few pages back, i believe someone has your kits running 3800 already.
try looking here this is an actual expert with ram (said these can be copied+pasted) you can try my timings if you wish
but the link given is a few pages back and is spoken for a true copy paste. (my results with these timings as well) good luck!


----------



## mongoled

craxton said:


> (EIDT-->UPDATE) AUTO PBO, auto scaler no settings on cpu tuned by me. just ram is tuned....this good or bad?
> View attachment 2478815
> 
> 
> no, pbo isnt on auto actually. 180,90,140 scalerx3 undervolted .0750mv. ill fix that shortly.
> 
> does sisa say theres a bios update in the tips section for you? when there isnt a bios update for your board?


Set your PBO like mine, 142/95/280, I think the low EDC value may be skewing your results

Your sig says you are running 4000 mhz MCLK, does that mean that you are using 2000 mhz FCLK ?

As hardly anybody is free of WHEA warnings using anything above 1900 mhz FCLK.

If you are using 2000 FCLK you score should be alot higher than what you are posting.

So you are either

1/ Running 2000 FCLK with WHEA warning, which is giving you lower results and will possibly end up corrupting your Windows install and data.
2/ Your EDC value is holding back your throughput.

If I am to guess its your FCLK that is not stable, as raising EDC would give you better L3 cache results, but dont believe it should effect the throughput.

For reference I hit 85 GB/sec with 142/95/280, 10x, 200 mhz.

I think the MCLK/FCLK was at 3866/1933


----------



## Not a redditor

Does the ram Latency in ns ( nano secounds ) affect anything in real life ?


----------



## BluePaint

Not a redditor said:


> Does the ram Latency in ns ( nano secounds ) affect anything in real life ?


Some games which are sensitive to it, e.g. all Total War games because they handle 10.000 units in realtime


----------



## Veii

Do you 5950X guys know the PBO limits on stock
CH8DH uses 5900X limits 125-90-140 for a 5950X
I remember it was something 200A EDC, but i cant remember more
Bios 3204 also pushes 1100mV cLDO_VDDP on XMP @ 3800MT/s
Be sure to lower this down to 900/950
1100 is close to damaging territory 😐

At least procODT is not 60 ohm amymore


----------



## ManniX-ITA

Veii said:


> Do you 5950X guys know the PBO limits on stock
> CH8DH uses 5900X limits 125-90-140 for a 5950X
> I remember it was something 200A EDC, but i cant remember more
> Bios 3404 also pushes 1100mV cLDO_VDDP on XMP @ 3800MT/s
> Be sure to lower this down to 900/950
> 1100 is close to damaging territory 😐
> 
> At least procODT is not 60 ohm amymore


Pretty sure on the Unify-X is 142/90/140, TDP at 105W.
Not sure about the Master but I think same.


----------



## Not a redditor

beside rendering and other application/software that depends on this


BluePaint said:


> Some games which are sensitive to it, e.g. all Total War games because they handle 10.000 units in realtime


so basicly high cpu demanding games ? that has to do alot of calculation ? was woundering if 50 ns vs 60 ns does have any realife effect on ppl , like 144hz vs 165hz = 0 human reception notice


----------



## mongoled

As per "Gamers Nexus" article

*Package Power Tracking (“PPT”): *The PPT threshold is the allowed socket power consumption permitted across the voltage rails supplying the socket. Applications with high thread counts, and/or “heavy” threads, can encounter PPT limits that can be alleviated with a raised PPT limit.

Default for Socket AM4 is at least 142W on motherboards rated for 105W TDP processors.
Default for Socket AM4 is at least 88W on motherboards rated for 65W TDP processors.
*Thermal Design Current (“TDC”): *The maximum current (amps) that can be delivered by a specific motherboard’s voltage regulator configuration in thermally-constrained scenarios.

Default for socket AM4 is at least 95A on motherboards rated for 105W TDP processors.
Default for socket AM4 is at least 60A on motherboards rated for 65W TDP processors.
*Electrical Design Current (“EDC”): *The maximum current (amps) that can be delivered by a specific motherboard’s voltage regulator configuration in a peak (“spike”) condition for a short period of time.

Default for socket AM4 is 140A on motherboards rated for 105W TDP processors.
Default for socket AM4 is 90A on motherboards rated for 65W TDP processors.
I imagine the 5900x is rated as a 105W TDP CPU

Based on above its default values should be 142/95/140


----------



## ManniX-ITA

Not a redditor said:


> beside rendering and other application/software that depends on this
> 
> so basicly high cpu demanding games ? that has to do alot of calculation ? was woundering if 50 ns vs 60 ns does have any realife effect on ppl , like 144hz vs 165hz = 0 human reception notice


It has to do on how the game engine has been built.
Shadow of the Tomb Raider and Assassin's Creed series are two other examples where FPS is highly dependent on memory timings.
So not only calculations; good timings with CPU bounds settings can vary even 20-30 fps for max.


----------



## ManniX-ITA

@mongoled 
Yes mine was a typo, 95A.


----------



## BluePaint

Not a redditor said:


> so basicly high cpu demanding games ? that has to do alot of calculation ? was woundering if 50 ns vs 60 ns does have any realife effect on ppl , like 144hz vs 165hz = 0 human reception notice


CPU demanding doesn't automatically mean RAM speed demanding. Cinebench for example doesn't care much about RAM speed. The more RAM an application/game uses actively the more likely it is that it will benefit from quick RAM access.

In Total War games, a 30% increas in RAM performance gives about 15% better performance in CPU/RAM bottlenecked situation where fps are lowest and that is very noticeable. Ofc, if it's about 1 or 2 ns more or less, no, that won't be perceptible.


----------



## Frizzle012

craxton said:


> are you using PBO scaler? are you enabling 200mhz auto oc?
> are you using pbo values and not just leaving them to auto, or off?
> also, you should have lower latency than what your showing.
> when testing in aida close all programs and background tasks
> windows doesnt need to run before running your test to see if your tests are staying within a set range.
> as if nothing if running in the background, then latency shouldnt change more than .1ns if it does thats a sign of instability.
> 
> i currently just got 4 sticks of bdie (my kits are 2 kits (2x8) bought at different times, but are the same model)
> (teamgroups dark pro) running on my 5600x stable.
> you can try my settings (as some are a copy and paste for 4 sticks) at 3800mhz and see what you get.
> or even 4000. i do suggest, setting SOC voltage to at least 1.2,
> VDDG IOD voltage to 1060mv or 1070mv (testing without apps running back to back to see if your being consistent with latency etc.
> set CLDO VDDP voltage around .900mv or a tad more depends.
> shouldn need more than that tho.
> and lastly VDDG CCD .990mv (1000mv vdroop is still a thing even with LLC3 on an MSI b550 board with good vrms.
> 
> VDIMM on my sticks runs fine at 1.46/47 and doesnt really like anything higher than 1.48 so,
> thats on you. (make sure to set PBO values accordingly when running prime95, y-cruncher, OCCT etc.
> or itll make your chip extremely toasty.
> 
> (i do believe your sticks should do these timings pretty easy
> as i copied most of them from a better ram kit (3800 c14 bdie kit)
> they worked fine for me.
> 
> CADBUS TIMINGS ARE EXTREMLY IMPORTANT AND DO NOT FORGET THEM!
> otherwise it'll not get stable (or it may but itll be alot easier with correct cadbus timings.
> I at least didnt see any sign of stability for a good while no matter what i did.
> 
> my pbo (WIDE OPEN VALUES for R20, R23 benchmarks etc are 180-90-140.
> but i do limit those with ryzen master when i run stress tests for WHEA errors etc.
> 
> im not an expert, but i do read most of everything i can that relates to ram/5000 series on this thread (coming from certian people)
> you can look a few pages back, i believe someone has your kits running 3800 already.
> try looking here this is an actual expert with ram (said these can be copied+pasted) you can try my timings if you wish
> but the link given is a few pages back and is spoken for a true copy paste. (my results with these timings as well) good luck!
> 
> View attachment 2478860
> 
> View attachment 2478861


so when you say my latencies shouldnt change by say .1ns do you mean if I run AIDA64 benchmark 3 or 4 times in a row I should get the same memory latency? or is there a different metric youre referring to? If thats the case im around +/- .2ns each time with the below setup.

I ended up getting 3933MHz running fairly stable for now, I think. I have a bunch of testing to do. But I havent used PBO, I was poking around the BIOS, but didnt see the individual settings for PPT/TDC/EDC that youre referring to. Maybe I have to enable it first? Although I thought somewhere I read it should be on by default?

Anyways, the only thing I changed so far are some voltages and it made a dramatic difference in my memory benchmarks.

mclk/fclk/uclk are 1:1:1 @ 1966.67










soc 1.2v
dram 1.4v
ccd 0.975v
iod 1.075v

From my AIDA64 benchmark, my Read and Write bandwidths are around 94% and 93% on average respectively without doing anything more than this for now.










Do you think I should try setting the PBO maxes and then start tightening timings after that? What metrics would I want to see improve as I change PBO values?


----------



## Trusconi85

craxton said:


> are you using PBO scaler? are you enabling 200mhz auto oc?
> are you using pbo values and not just leaving them to auto, or off?
> also, you should have lower latency than what your showing.
> when testing in aida close all programs and background tasks
> windows doesnt need to run before running your test to see if your tests are staying within a set range.
> as if nothing if running in the background, then latency shouldnt change more than .1ns if it does thats a sign of instability.


Everything stock on 5600x CPU (the only difference are in the first image of the link i post above)



craxton said:


> i currently just got 4 sticks of bdie (my kits are 2 kits (2x8) bought at different times, but are the same model)
> (teamgroups dark pro) running on my 5600x stable.
> you can try my settings (as some are a copy and paste for 4 sticks) at 3800mhz and see what you get.
> or even 4000. i do suggest, setting SOC voltage to at least 1.2,
> VDDG IOD voltage to 1060mv or 1070mv (testing without apps running back to back to see if your being consistent with latency etc.
> set CLDO VDDP voltage around .900mv or a tad more depends.
> shouldn need more than that tho.
> and lastly VDDG CCD .990mv (1000mv vdroop is still a thing even with LLC3 on an MSI b550 board with good vrms.


Also i have 2+2 stick bought in different moment but they are both FlareX 3200C14
I can run them at 3800/1900 with 1.4v without modify anything else



craxton said:


> VDIMM on my sticks runs fine at 1.46/47 and doesnt really like anything higher than 1.48 so,
> thats on you. (make sure to set PBO values accordingly when running prime95, y-cruncher, OCCT etc.
> or itll make your chip extremely toasty.
> 
> (i do believe your sticks should do these timings pretty easy
> as i copied most of them from a better ram kit (3800 c14 bdie kit)
> they worked fine for me.


I would like to run them 3800c14 insted of 4000c16if is possible



craxton said:


> CADBUS TIMINGS ARE EXTREMLY IMPORTANT AND DO NOT FORGET THEM!
> otherwise it'll not get stable (or it may but itll be alot easier with correct cadbus timings.
> I at least didnt see any sign of stability for a good while no matter what i did.


Are the 3 parameter in the corcer of your "print screen" setting?



craxton said:


> my pbo (WIDE OPEN VALUES for R20, R23 benchmarks etc are 180-90-140.
> but i do limit those with ryzen master when i run stress tests for WHEA errors etc.
> 
> im not an expert, but i do read most of everything i can that relates to ram/5000 series on this thread (coming from certian people)
> you can look a few pages back, i believe someone has your kits running 3800 already.
> try looking here this is an actual expert with ram (said these can be copied+pasted) you can try my timings if you wish
> but the link given is a few pages back and is spoken for a true copy paste. (my results with these timings as well) good luck!
> 
> View attachment 2478860
> 
> View attachment 2478861


Thank you, i will try them. I have to only to check everything i have to set


----------



## Trusconi85

Veii said:


> View attachment 2478569
> 
> Nothing special yet, just low voltage timings for 4 x 8GB A2
> 3967 works, 4000 refuses on this Bios fully ~ it's a less broken mess than 3204
> Negative vCore because of curve optimizer (as test) on Core 6 as +18
> View attachment 2478568
> 
> It's an interesting sample, but CCD2 is plain bad
> CCD one runs at 1150mV near 4.6, CCD2 just is able to run 4.35
> It's investigation in progress if Curve Optimizer helped that bad Core
> 
> Good loadlines stay the same as above, just with CPU VRM Phase to Extreme = Full Phase Mode
> Also CTR user - be sure it's y-cruncher stable
> This means BBP, SFT, FFT, C17 stable
> Yuri's tests are not harsh enough. SFT & BBP AVX2 small data set pretty much wr*cks his founded settings
> * P95 Small FFT is also not harsh enough
> ZenState 2.0, TurboV and Y-Cruncher are your friends
> 
> ASUS users can apply the VID it spills out or they tested by themself ~ in the per CCX Tab
> But use a positive vCore offset ontop of Curve Optimizer ~ for Per CCX / Hybrid Mode OC Stability @ X1 Scalar
> OTP is 90c unless changed manually by AMD Overclocking PBO
> CBS & Main Menu PBO are a mess. Motherboard limits are a mess
> Set throttle limit to 95c instead of 92, else you will keep on having OTP shutdowns on y-cruncher (per CCX guys)


Hello, do you think i can try your memory setting on my B550 STRIX + 5600X?
Thank you


----------



## PJVol

Trusconi85 said:


> I have to only to check everything i have to set


Did you check, what I wrote in this post ?








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


mine similar result, old test for temperature compare(cb20 raise temperature to 83c , aida multicore to 88c), bios 4007 ch7wifi firs pbo + 275, 2nd pbo + 150 and curve optimizer dont remember the numer, same all core working now, retest tonigh with actual...




www.overclock.net


----------



## mirzet1976

PJVol said:


> Not an asus board owner, but have seen it quite a few times, that their bioses have something like "fmax" feature set by default. If so, try to disable it and see if it will help.
> 
> *PS: Found it: "PBO FMax Enhancer" - it should be disabled with ryzen 5000's *


FMax when enabled it reduces the voltage to the CPU using PBO (_see CPU TDC and CPU EDC in image FMax enabled_) so you lose multicore performance but by increasing the voltage to the CPU via + offset you are back to the previous performance

FMax disabled










FMax enabled


----------



## KedarWolf

How dependent is a Ryzen 9 CPU memory overclock on the motherboard?

I ask because I'm stable if I use the exact same settings on my 5950x in RAM timings etc as I did on my 3950x.

Just the CAD BUS and stuff is a tiny bit different.


----------



## craxton

mongoled said:


> Set your PBO like mine, 142/95/280, I think the low EDC value may be skewing your results
> 
> Your sig says you are running 4000 mhz MCLK, does that mean that you are using 2000 mhz FCLK ?
> 
> As hardly anybody is free of WHEA warnings using anything above 1900 mhz FCLK.
> 
> If you are using 2000 FCLK you score should be alot higher than what you are posting.
> 
> So you are either
> 
> 1/ Running 2000 FCLK with WHEA warning, which is giving you lower results and will possibly end up corrupting your Windows install and data.
> 2/ Your EDC value is holding back your throughput.
> 
> If I am to guess its your FCLK that is not stable, as raising EDC would give you better L3 cache results, but dont believe it should effect the throughput.
> 
> For reference I hit 85 GB/sec with 142/95/280, 10x, 200 mhz.
> 
> I think the MCLK/FCLK was at 3866/1933


yes, running 4 sticks of bdie at 4000 mhz using the timings VEII was telling you to run actually. worked wonderfully for me, WHEA free since january even while i wasnt stable havent had any WHEA errors since patch C bios for the MSI B550 GAMING EDGE WIFI board.... CTR claims my chips a "platinum" so id assume me not knowing how to use PBO properly might be why my numbers arent looking correctly. but yes running 2ghz fclk 4ghz memclock.... stable thru TM5, HCI, Prime95, Y-cruncher on loop 7 sessions with a limited PBO to reduce throttle.


----------



## PJVol

mirzet1976 said:


> FMax when enabled


I dont get what you're trying to say here, other than confirming it's clear buggy behavior with Zen3. OP was asking for help and from his screens, CPU performance was obviously crippled, and from what I heard about it and from your findings as well, it definitely should be Disabled by default, instead of being Auto.


----------



## neobpm

I have a 5800x + x570 Tomahawk with 2x8gb of Crucial Ballistix Max (4000cl18) and I set it at 3800cl16, in Aida64 I get 54gbs/30gbs/49gbs with a 57.1ns of latency. 

I think this is a poor result for a rig like this, how I can improve the ram performance? I want better read and writte numbers and less latency. Any help?


----------



## mongoled

craxton said:


> yes, running 4 sticks of bdie at 4000 mhz using the timings VEII was telling you to run actually. worked wonderfully for me, WHEA free since january even while i wasnt stable havent had any WHEA errors since patch C bios for the MSI B550 GAMING EDGE WIFI board.... CTR claims my chips a "platinum" so id assume me not knowing how to use PBO properly might be why my numbers arent looking correctly. but yes running 2ghz fclk 4ghz memclock.... stable thru TM5, HCI, Prime95, Y-cruncher on loop 7 sessions with a limited PBO to reduce throttle.
> View attachment 2479045
> View attachment 2479044


I am hoping that as with B550 chipset, where a number of peeps are running WHEA free above 1933 mhz, will happen for the X570 chipset!

Unfortunately I cant run your settings to do a direct comparison as my FCLK range is up to 1933, then I have a frequency hole that results in no post and clear CMOS, then I am good from 2033 to 2066 mhz.

I can see from your settings you are running boost override of 200 mhz and EDC is at either auto value or set to 140A.

I will run a sandra at 3866/1933 and then at 4066/2033 with [email protected] 140A and boost override at 200 mhz and will compare results!


----------



## mongoled

EDC @140A (PPT @142W, TDC @95A), Boost Override @200mhz

3866/1933 - 80.83GB/s









4066/2033 - 81.37GB/s









4133/2066 - 81.18GB/s









I will now run the same settings with PBO at AUTO


----------



## mongoled

PBO @auto, Boost Override @200mhz

3866/1933 - 74.28GB/s









4066/2033 - 74.27GB/s









4133/2066 - 75GB/s









Its clear, results are very much effected by PBO settings!

Here is a 
PPT @142W, TDC @95A & EDC @280A, Boost Override @200mhz

3866/1933 - 86.83GB/s









MCLK/FCLK do not effect the results.

Hope the data is useful!


----------



## neobpm

mongoled said:


> PBO @auto, Boost Override @200mhz
> 
> 3866/1933 - 74.28GB/s
> View attachment 2479070
> 
> 
> 4066/2033 - 74.27GB/s
> View attachment 2479071
> 
> 
> 4133/2066 - 75GB/s
> View attachment 2479072
> 
> 
> Its clear, results are very much effected by PBO settings!
> 
> Here is a
> PPT @142W, TDC @95A & EDC @280A, Boost Override @200mhz
> 
> 3866/1933 - 86.83GB/s
> View attachment 2479073
> 
> 
> MCLK/FCLK do not effect the results.
> 
> Hope the data is useful!


What are the better PBO settings for a 5800x?


----------



## mongoled

neobpm said:


> What are the better PBO settings for a 5800x?


You have all the data to choose for yourself!

Define what you mean by "better"? 

What is better for you, better performance? Better stability? Better efficiency? Better temps? 

I am not a mind reader...


----------



## neobpm

mongoled said:


> You have all the data to choose for yourself!
> 
> Define what you mean by "better"?
> 
> What is better for you, better performance? Better stability? Better efficiency? Better temps?
> 
> I am not a mind reader...


Better performance.


----------



## mongoled

Your CPU is a 105W TDP CPU, so you can start with the values I use for my 5600x, which are [email protected], [email protected] and [email protected] 

Be warned, [email protected] will put out alot of heat when running stress tests that push the memory/cpu subsystem, so you should have cooling that can handle it!


----------



## KedarWolf

An old standby, GSAT in Windows for two hours.


----------



## kratosatlante

Veii said:


> The first 6 cores are not interesting - the frequency
> Effective Core Frequency T0 is interesting. The first one can be with clock stretching.
> On HWinfo Enable CPU Snapshot pooling (first settings menu, not sensor settings)
> and use 6.35-4320 or 4330 for hibernated core tracking
> 
> 10.6ns L3 is a bit on the high side for an OC
> This seems to work although its not thaat optimal
> 
> 
> 
> 
> 
> 
> 
> 
> jedi95/BoostTester
> 
> 
> Simple tool for generating loads that should trigger maximum CPU boost clocks. - jedi95/BoostTester
> 
> 
> 
> 
> github.com


Hi veii, how reduce l3 cache? try raise vsoc to 1.125, 1.15, 1.18,get same arround 10.7- 10.8, if pass pll 1.87 get penalty, for pll 1.95 get l3 11.2 , memory latency in runs vary from 52.7 to 53.3 in bot configs trfc 234 and 221
try rtt 6-3-3 i see work in various users, but at 4hs runing normal use web, gaming get 1 whea error, not sure its for rtt o vddp 880, for now need to now how reduce l3 latency, i see other user 5600xget 10.2-10.4
llc3 , cpu power auto, phases extreme, pbo mother limit, curve opt conservative, 4 4 best cores, 7-11-19-15


----------



## kompira

first gen Zen
2x8GB B-die A2 single rank
AGESA 1.2.0.0 SMU 25.86.0
flat14 GDM OFF CR 1T
3600MT/s tCKE 7 CAD BUS Setup 1-1-12 CAD BUS 40-20-20-20 RTT 7-0-6


----------



## Trusconi85

PJVol said:


> Did you check, what I wrote in this post ?
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> mine similar result, old test for temperature compare(cb20 raise temperature to 83c , aida multicore to 88c), bios 4007 ch7wifi firs pbo + 275, 2nd pbo + 150 and curve optimizer dont remember the numer, same all core working now, retest tonigh with actual...
> 
> 
> 
> 
> www.overclock.net


No, because i am out for work and i am writing here through a notebook :-(


----------



## craxton

mongoled said:


> PBO @auto, Boost Override @200mhz
> 
> 3866/1933 - 74.28GB/s
> View attachment 2479070
> 
> 
> 4066/2033 - 74.27GB/s
> View attachment 2479071
> 
> 
> 4133/2066 - 75GB/s
> View attachment 2479072
> 
> 
> Its clear, results are very much effected by PBO settings!
> 
> Here is a
> PPT @142W, TDC @95A & EDC @280A, Boost Override @200mhz
> 
> 3866/1933 - 86.83GB/s
> View attachment 2479073
> 
> 
> MCLK/FCLK do not effect the results.
> 
> Hope the data is useful!


power went out and hasnt came back temps dropped to 41f inside my home, packed up and went to my parents lol

but it went out literally right when i left the bios setting your recc settings to rerun sisoft so... here you go.
142/95/280 PBO values in bios, x10, 200mhz (240mm ek wb aio) still seem low?
(EDIT) yes my EDC value was at 140 in bios, but limited to 100 in ryzen master, tests below are what you mentioned to do. 
this is without any ( - offset ) to cpu voltage like i had been doing which, running a -.07xx mv offset 
gives over 12000 r23 scores? but greatly henders siso benches????


----------



## craxton

kompira said:


> first gen Zen
> 2x8GB B-die A2 single rank
> AGESA 1.2.0.0 SMU 25.86.0
> flat14 GDM OFF CR 1T
> 3600MT/s tCKE 7 CAD BUS Setup 1-1-12 CAD BUS 40-20-20-20 RTT 7-0-6
> View attachment 2479100
> 
> View attachment 2479101


pretty impressive for a 14nm 1600. considering my 1600af did 3800mhz barely this makes me feel like my chip isnt as "golden" as i believe it to be lol

but i never played with timings at all, just the presets inside MSI bios. and i didnt own B-DIE kits at the time of owning the 1600af well using it anyhow
as im now running my 5600x, debating to throw the spare parts i have together and see what the old refresh node will achieve now that im more fimilar with ram and overclocking it.
and perhaps getting the 3600xt to stabilize 3800mhz 1:1 4 sticks of CJR 4000 darkz....(are you killing all running background tasks when testing aida?)


----------



## craxton

Frizzle012 said:


> so when you say my latencies shouldnt change by say .1ns do you mean if I run AIDA64 benchmark 3 or 4 times in a row I should get the same memory latency? or is there a different metric youre referring to? If thats the case im around +/- .2ns each time with the below setup.
> 
> I ended up getting 3933MHz running fairly stable for now, I think. I have a bunch of testing to do. But I havent used PBO, I was poking around the BIOS, but didnt see the individual settings for PPT/TDC/EDC that youre referring to. Maybe I have to enable it first? Although I thought somewhere I read it should be on by default?
> 
> Anyways, the only thing I changed so far are some voltages and it made a dramatic difference in my memory benchmarks.
> 
> mclk/fclk/uclk are 1:1:1 @ 1966.67
> 
> View attachment 2478953
> 
> 
> soc 1.2v
> dram 1.4v
> ccd 0.975v
> iod 1.075v
> 
> From my AIDA64 benchmark, my Read and Write bandwidths are around 94% and 93% on average respectively without doing anything more than this for now.
> 
> View attachment 2478951
> 
> 
> Do you think I should try setting the PBO maxes and then start tightening timings after that? What metrics would I want to see improve as I change PBO values?


if your closing all background tasks I.E stuff like razor software, Afterburner, (personally i close HWINFO when running an aida bench) 
pretty much make sure everything thats running windows doesnt need close it. 
unless something you use like your mouse wont work without it, 
then i suggest wired mode and kill the software anyhow. 

from the looks of your latency score your not killing background tasks are you?
if this is the case do be sure to KILL background tasks and (make sure their services arent running) 
some windows services can throw latency way off as well, like (backup, update etc) 

PBO values should be under (advanced/AMD overclocking) im not sure on your board, but on MSI you dont need to 
go thru AMD overclocking as the main CPU section of the bios where P-states etc are located is where you can change these values
let alone itll take priority over anything set inside AMD overclocking no matter what. (or it always does on my two MSI boards (B550/X570 gaming edge wifi)


----------



## Veii

kratosatlante said:


> Hi veii, how reduce l3 cache? try raise vsoc to 1.125, 1.15, 1.18,get same arround 10.7- 10.8, if pass pll 1.87 get penalty, for pll 1.95 get l3 11.2 , memory latency in runs vary from 52.7 to 53.3 in bot configs trfc 234 and 221
> try rtt 6-3-3 i see work in various users, but at 4hs runing normal use web, gaming get 1 whea error, not sure its for rtt o vddp 880, for now need to now how reduce l3 latency, i see other user 5600xget 10.2-10.4
> llc3 , cpu power auto, phases extreme, pbo mother limit, curve opt conservative, 4 4 best cores, 7-11-19-15
> View attachment 2479084
> View attachment 2479085


First you have a rounding issue on tRFC - wherever you got the one from
234-174-107 is the correct, not
234-173-106
believing in tRFC Calculator (mini) or not
manual mode should show it clear that you have rounding issues 

L3 Cache latency depends on allcore effective boost 
If cores can not hit the advertised boost, the result will be lower
People nearly always hit high numbers but only on one core
each 100mh, you go down 0.2ns in latency
4.75 = 10.9ns
4.85 = 10.7ns

L3 Bandwidth , depends on Cache allcore utilisation and active time
Allcore sets will have it higher, or PBO effective allcore will increase it 
In this case EDC limit is the one you look for to increase it


----------



## obogobo

Started a thread on reddit to talk about the 1900 FCLK no POST issue if people are interested in chiming in:

__
https://www.reddit.com/r/Amd/comments/llet7x


----------



## _frame_

After a lot of time spent trying to get stable IF 2000 Mhz, I just realized that my G.Skill 2x8 gb 3200C14 rev A1on B.Die is not capable of stable 2000 Mhz 
And weird thing, the maximum voltage for it is 1,4 V, if I try to push more I get more errors...
My stable setting is 1900 Mhz 1:1:1 with 16-16-16-32 1T and 1.4 V
Who knows, why my sticks does not like more than 1.4 V?


----------



## Veii

_frame_ said:


> After a lot of time spent trying to get stable IF 2000 Mhz, I just realized that my G.Skill 2x8 gb 3200C14 rev A1on B.Die is not capable of stable 2000 Mhz
> And weird thing, the maximum voltage for it is 1,4 V, if I try to push more I get more errors...
> My stable setting is 1900 Mhz 1:1:1 with 16-16-16-32 1T and 1.4 V
> Who know, why my sticks does not like more than 1.4 V?


Try 706 as RTT , and CAD_BUS 40-20-30-20 (without CAD_BUS timings ~ tCKE 1)
that is enough to power them with a bigger voltage range
Mine are A0s , and that helps them scale up till 4300 instead of ~4000
Just need to check and probably increase VDIMM a bit more
It shouldn't make them crash @ 1.51v anymore

Try with GDM off, 2T
for GDM enabled, these settings might be too harsh and cause the PCB to crash

EDIT:
Advanced option
706, 40-20-20-20, tCKE 11,4-4-18 (cad_bus setup timing)
as the next step to hit 4000, or 3-3-15 & tCKE 9 for 3800
* only for 2x8GB


----------



## _frame_

Veii said:


> Try 706 as RTT , and CAD_BUS 40-20-30-20 (without CAD_BUS timings ~ tCKE 1)
> that is enough to power them with a bigger voltage range
> Mine are A0s , and that helps them scale up till 4300 instead of ~4000
> Just need to check and probably increase VDIMM a bit more
> It shouldn't make them crash @ 1.51v anymore
> 
> Try with GDM off, 2T
> for GDM enabled, these settings might be too harsh and cause the PCB to crash
> 
> EDIT:
> Advanced option
> 706, 40-20-20-20, tCKE 11,4-4-18 (cad_bus setup timing)
> as the next step to hit 4000, or 3-3-15 & tCKE 9 for 3800
> * only for 2x8GB


Thank you for your reply!
But unfortunately it did not work for me.
Later I'll try "advanced option".
Vdimm 1.4 or 1.45 or 1.5 no luck.
Vsoc and etc also I've tried in every combination. To get stable I have to change only MCLK to 1900


----------



## Dasa

obogobo said:


> Started a thread on reddit to talk about the 1900 FCLK no POST issue if people are interested in chiming in:
> 
> __
> https://www.reddit.com/r/Amd/comments/llet7x


1900IF posts for me but audio crackles something fierce and USB2 ports stutter.
1866 is stable and 1933 gets WHEA in CPU stress tests but is otherwise stable.
1933 could get far less WHEA with further work on the BIOS I believe as it seems to vary from 1 WHEA per minute to ~15 WHEA per minute depending on the boot training.


----------



## VPII

I've been looking around on here just to see what some people are doing and I noticed @Veii posting various settings. One I have never really changed as I've set it as the Ryzen Memory Calculator stated. But I noticed @Veii mentioning 9 or so for it and mine has always been at 1 and 100% stable. But I thought I would give it a try at 9 and 16 just to see if there is a differenc when running Aida64. Now look my latency is not actually where it should be, have been playing around with settings with some help from others and got it a little better but still not where it should be. But here is what I found.

tCKE at 1










tCKE at 9










tCKE at 16











I will try higher a little later to see, but at some point higher will not be better.


----------



## BluePaint

_frame_ said:


> But unfortunately it did not work for me.
> Vdimm 1.4 or 1.45 or 1.5 no luck.
> Vsoc and etc also I've tried in every combination. To get stable I have to change only MCLK to 1900


Have u checked RAM temps? Using an extra fan is often a good idea.


----------



## hsn

fclk 2066 can boot, but audio became shuttering


----------



## hisXLNC

Running at 4x8 @ 3733Mhz as I saw somewhere (cant remember where) that theres diminishing returns past this point. CLD0 (.950) now (screenshot is before the change). VSOC is 1.125 in bios and running 1.47v. CPU is running stock right now. KARHU found an error


What should I change?


----------



## Veii

_frame_ said:


> Thank you for your reply!
> But unfortunately it did not work for me.
> Later I'll try "advanced option".
> Vdimm 1.4 or 1.45 or 1.5 no luck.
> Vsoc and etc also I've tried in every combination. To get stable I have to change only MCLK to 1900


Excuse me, but you don't follow suggestion's
cLDO_VDDP is too high at 1v
It should not be higher than VDDG CCD as worst, unless IOD Is higher and follows a specific voltage stepping/pattern

You get pretty much every error on this chart
Starting with " RAM Overheating"









Your errors also mention tRRD issues (which i can see, they are too high)
And also mention tRDWR/tWRRD issues, which i can also see

Too high timings wont magically run because they are high to begin with
You'd be better of AUTO'ing stuff you dont know what to set at 
Considering ERROR 13 is a hardcrash on a hig dataset transfer
It's either RTT values which break data eye, or heat which breaks it
Something is quite messed up on your set
I just hope the board wasnt thaat buggy to predict bad values


----------



## _frame_

BluePaint said:


> Have u checked RAM temps? Using an extra fan is often a good idea.


Yes, sure! I have fan blowing to the memory. Temps up to 36 C while testing.


----------



## _frame_

Veii said:


> cLDO_VDDP is too high at 1v


I've written that I tried Vsoc and others in different combinations. cLDO_VDDP was from 0.9 to 1 V. And 1 V it is Auto setting for Asus. So 0,9 and 0,95 did not help. Vsoc 1,05 - 1,1 - 1,15 - 1,2 also. CCD 1 and 1,05 V also.


Veii said:


> You get pretty much every error on this chart


Every time I run this test I have different errors.


Veii said:


> You'd be better of AUTO'ing stuff you dont know what to set at


Actually it is everything on AUTO. Only main timings are manually set: 16-16-16-16-32-48.
I do not think it is heat as HWinfo shows 36 C


----------



## LuckyImperial

Hey Guys/Gals,

I've been lurking for the past 6 or 10 pages, and I've seen a lot of timings posted for BDie in _very fast_ configurations paired with a 5000 series CPU, but I think it's time that I ask for help. 

I have two 8Gb sticks of GSkill Trident Z 3200 CL14. I know it's Bdie (what version I don't know). Right now it's sitting in DOCP. At one point I punched in values from Ryzen Memory Calculator for 3466 Fast, see below, and everything ran well, but I'd like to get your help implementing a conservative OC/timings for my memory. Were my timings with the calculator pretty decent? Should I just go back to those?

I'm a newb when it comes to memory OCing, but I know my way around the BIOS fairly well and to reiterate; I'm looking for help reaching a stable, conservative memory OC for a gaming PC.


----------



## Joeking78

LuckyImperial said:


> Hey Guys/Gals,
> 
> I've been lurking for the past 6 or 10 pages, and I've seen a lot of timings posted for BDie in _very fast_ configurations paired with a 5000 series CPU, but I think it's time that I ask for help.
> 
> I have two 8Gb sticks of GSkill Trident Z 3200 CL14. I know it's Bdie (what version I don't know). Right now it's sitting in DOCP. At one point I punched in values from Ryzen Memory Calculator for 3466 Fast, see below, and everything ran well, but I'd like to get your help implementing a conservative OC/timings for my memory. Were my timings with the calculator pretty decent? Should I just go back to those?
> 
> I'm a newb when it comes to memory OCing, but I know my way around the BIOS fairly well and to reiterate; I'm looking for help reaching a stable, conservative memory OC for a gaming PC.
> 
> View attachment 2479239


I have the same kit in 2x16gb

You should easily be able to hit 3733 C14 1.5V, 4000 C16 1.47v ish...3600 C14 would be a nice overclock with around 1.42v to 1.45v would be my guess for daily use.

3733 C14, 1.5v










4000 C16 1.48v









4066 C16 1.52v


----------



## Veii

_frame_ said:


> I've written that I tried Vsoc and others in different combinations. cLDO_VDDP was from 0.9 to 1 V. And 1 V it is Auto setting for Asus. So 0,9 and 0,95 did not help. Vsoc 1,05 - 1,1 - 1,15 - 1,2 also. CCD 1 and 1,05 V also.


900mV as long as you don't y-cruncher crash , is fine
920 or 950 is what you should run at worst
Higher than 900mV only degrades the signal, which goes hand in hand for "minimum needed procODT"
But voltages go as tripplets, well in this case together because cLDO_VDDP doesn't need to be touched at all

Real positive or rather "not negative" effect they surely have
But TM5 wouldn't care about them. It only tests timings, but can Error 6 fail, if its CPU related


> Every time I run this test I have different errors.


Note them down, the order and the time when they appear. Depending on what comez after what, it will mean something else 

It crashes on X test, but not always only X was the issue. Often it depends on the chain why it starts to fail
The remain errors will snowball then 
But the list is for specific errors
For "failing on everything" the problem is more severe


> Actually it is everything on AUTO. Only main timings are manually set: 16-16-16-16-32-48.
> I do not think it is heat as HWinfo shows 36 C


Then this bios is big times messed up
tRDWR is way to much
It would be fine if you run tRCD 30. But not 18 

If you have no baseline
Please follow 1usmus presets
I could give you many sets but before considering working with timings, you should fix the CPU side of things
Voltages and procODT

Then later fix RTT values and work with CAD_BUS @ tCKE 1
After that is stable on a baseline timings set
I dont think it makes sense to do that many jumps at once
Else you'd already know what is wrong 😃
Take a look at what people run here








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com




Maybe you can find a decent baseline
But be sure its y-cruncher (all tests) 4 loops stable (1-7-0 key combination)
Before considering going for memOC
Probably on 5xxx even fix curve optimizer with upped PBO limits ~ before doing anything away from XMP @ cLDO_VDDP 900mV

Cores need to behave equal and hit the same boost on all cores == equalizing L3 cache
Before you go for memoryOC ~ if you want to get a good place on this leaderboard


----------



## _frame_

Joeking78 said:


> I have the same kit in 2x16gb
> 
> You should easily be able to hit 3733 C14 1.5V, 4000 C16 1.47v ish...3600 C14 would be a nice overclock with around 1.42v to 1.45v would be my guess for daily use.


Yes I know, it should be easy! but my kit give me more errors when the voltage goes more than 1.4 V, I guess this is the reason I could not get 4000 MCLK stable.
I have tried similar timings to yours, except tRCDRD 17.


Veii said:


> Cores need to behave equal and hit the same boost on all cores == equalizing L3 cache
> Before you go for memoryOC ~ if you want to get a good place on this leaderboard


Thank you again! I'll try!
I do not use PBO, I'm with static overclock. My cpu is golden sample according to CTR 2.0
So for memory testing I'm in 4600 Mhz 1.3 V which is pretty easy for this cpu.


----------



## Joeking78

_frame_ said:


> Yes I know, it should be easy! but my kit give me more errors then the voltage goes more than 1.4 V, I guess this is the reason I could not get 4000 MCLK stable.
> I have tried similar timings to yours, except tRCDRD 17.
> 
> Thank you again! I'll try!


TRCDRD 16 at 4000mhz needs much voltage for me for some reason, same with TRCDRD 14 at 3733mhz.


----------



## _frame_

Veii said:


> But voltages go as tripplets, well in this case together because cLDO_VDDP doesn't need to be touched at all


In case of Asus mobo it should be touched because AUTO = 1 V with latest BIOS, with beta it was 0.95 by default


----------



## Veii

_frame_ said:


> Thank you again! I'll try!
> I do not use PBO, I'm with static overclock. My cpu is golden sample according to CTR 2.0
> So for memory testing I'm in 4600 Mhz 1.3 V which is pretty easy for this cpu.


1.3v is not easy
I've played with CTR on 2 golden samples
The voltage it recommends is too high
It nearly never will pass y-cruncher with his settings
His tool is nice and handy, but his load is not harsh enough
Y-cruncher close to always fails on it because 1.3v even with fixed AVX2 droop and maybe subtle loadline drop, is still way to high
Some of the tests run on less than 1.18v, some more than 1.36

The problem on all that is his viewpoint of function and goal
The tool expects the user to run an as low as possible loadline
But then will catastrophically fail because there is barely loadline droop on tests that need it
I do suggest to still use CTR for debug and analysis
But go back to ZenState 2.0 (@irusanovBG and all other peoples opensource research) and manually tune CCX stability with it

At least you'd know what to select as you've tested stability
Sorry but as great as his tool is, the load it pushes is not even remotely harsh enough to destabilize the voltage it fixes
Without set loadline droop, it guaranteed will be unstable on AVX2 renders

It's the design around the tool that's problematic, not the software itself


----------



## LuckyImperial

Joeking78 said:


> I have the same kit in 2x16gb
> 
> You should easily be able to hit 3733 C14 1.5V, 4000 C16 1.47v ish...3600 C14 would be a nice overclock with around 1.42v to 1.45v would be my guess for daily use.


I think I'm gonna shoot for the easy one for daily use, 3600 C14 @ ~1.42v-1.45V.

Should I just steal your timings/settings/voltages that you have shown for 3733 C14 and make an attempt at 3600MHz 1.45ish Volts?


----------



## Joeking78

LuckyImperial said:


> I think I'm gonna shoot for the easy one for daily use, 3600 C14 @ ~1.42v-1.45V.
> 
> Should I just steal your timings/settings/voltages that you have shown for 3733 C14 and make an attempt at 3600MHz 1.45ish Volts?


Pretty much 👍


----------



## kratosatlante

Joeking78 said:


> Pretty much 👍


3600cl12, 1.62v


----------



## _frame_

Veii said:


> Sorry but as great as his tool is, the load it pushes is not even remotely harsh enough to destabilize the voltage it fixes
> Without set loadline droop, it guaranteed will be unstable on AVX2 renders


I use LLC 3 or 4 always.
And I do not follow CTR recommendations, but was good to know that cpu is golden 
CTR diagnostic suggest was 4775 Mhz at 1.3 V, but of course it is not real. My cpu is very very hot. Planning for delidding. Tried another one and it was 12 degrees cooler on the same settings same cooler same everything!


----------



## Veii

_frame_ said:


> I use LLC 3 or 4 always.
> And I do not follow CTR recommendations, but was good to know that cpu is golden
> CTR diagnostic suggest was 4775 Mhz at 1.3 V, but of course it is not real. My cpu is very very hot. Planning for delidding. Tried another one and it was 12 degrees cooler on the same settings same cooler same everything!


Do you have fluctuations between both CCDs on die temp ?
Delidding soldered units barely makes sense
But lapping them does a lot


----------



## LuckyImperial

_frame_ said:


> I use LLC 3 or 4 always.
> And I do not follow CTR 2.0 recommendations, but was good to know that cpu is golden
> CTR diagnostic suggest was 4775 Mhz at 1.3 V, but of course it is not real. My cpu is very very hot. Planning for delidding. Tried another one and it was 12 degrees cooler on the same settings same cooler same everything!


I've noticed that CTR 2.0 will not recommend voltages higher than 1300mV on 5600X. It has other weird tuning bugs, where it will never give you a recommended frequency above stock PBO despite reference frequencies starting well above stock PBO cap. What cooler are you on again?



Veii said:


> Do you have fluctuations between both CCDs on die temp ?
> Delidding soldered units barely makes sense
> But lapping them does a lot


I agree. Delidding soldered isn't going to yield much. A lap is a great idea though.



Joeking78 said:


> Pretty much 👍


Awesome. I'll let you know how it goes.


----------



## _frame_

Veii said:


> Do you have fluctuations between both CCDs on die temp ?


How to check it?


Veii said:


> Delidding soldered units barely makes sense
> But lapping them does a lot


How to explain 12 degrees difference on 2 cpus 5600X? Both IHS was pretty flat


----------



## _frame_

LuckyImperial said:


> It has other weird tuning bugs, where it will never give you a recommended frequency above stock PBO despite reference frequencies starting well above stock PBO cap. What cooler are you on again?


Stock PBO limit is 4650 Mhz all cores. While "tuning" I got recommendations of 4700-4750 Mhz.
DeepCool Assassin III. One of the best air cooler. On par with D15.


----------



## Veii

_frame_ said:


> How to check it?
> 
> How to explain 12 degrees difference on 2 cpus 5600X? Both IHS was pretty flat


Idk the "IHS is perfectly flat" part
They never where
Not with first gen and not with 3rd gen 
This one is not different

5600X if it has 2x die temp (hwinfo) means it has 2 CCDs
While one is supposed to deep sleep
If the difference is only that much, it does mean the headspreader does do its job to spread heat

If you mean 5600X to 5600X
Means, something else is going on
Heatspreaders from the same factory, nearly always have the same pressure patterns
The solder is most of the times equalized
But the "needed voltage for X frequency" changes a lot between units
So alsp temperature will change

Unless you tracked VDDP,VDDG,SOC predicted voltage and know they where set equal
The data you got without VID tracking is invalid 
But i can see for example on a 5950X and 5900X that there is a 8c delta between both CCDs
That was half because of the CCD quality and half because of the CPUs being concave
Although centered by intention higher designed and convex (like a little soundwave/water drop)


----------



## LuckyImperial

_frame_ said:


> How to check it?
> 
> How to explain 12 degrees difference on 2 cpus 5600X? Both IHS was pretty flat


I think the easiest way to "check" your flatness is just by dismounting the cooler and looking at the thermal paste. If there's big thick portions of paste next to very thin portions of paste then you can get a feel for how good your mount is, and how flat the IHS is. Your cooler is a nice cooler, so it's going to have a pretty nice surface flatness.

@Veii might disagree, but higher LLC levels will result in excessive ringing when load drops...at least according to Raja and gang. Back in C6H OC days...Elmor, Stilt, and Raja all agreed it's better to simply run higher set voltages with lower LLC levels rather than running higher LLC levels with lower voltages.


----------



## _frame_

Veii said:


> If the difference is only that much, it does mean the headspreader does do its job to spread heat


There are up to 5 degrees difference, not much I guess.


Veii said:


> Unless you tracked VDDP,VDDG,SOC predicted voltage and know they where set equal
> The data you got without VID tracking is invalid


I mean 2 cpu were in my hand and I switch them back to back. Clocks and voltage were the same for both.


LuckyImperial said:


> Your cooler is a nice cooler, so it's going to have a pretty nice surface flatness.


Actually they make convex "for a reason"! And it is bad for Ryzen...


----------



## Veii

LuckyImperial said:


> I think the easiest way to "check" your flatness is just by dismounting the cooler and looking at the thermal paste. If there's big thick portions of paste next to very thin portions of paste then you can get a feel for how good your mount is, and how flat the IHS is. Your cooler is a nice cooler, so it's going to have a pretty nice surface flatness.
> 
> @Vei


The coolers are designed for intel CPUs , which are fully concave ~ soo the coolers are convex
The same cooler on AMD IHS only pressures the corners 
I dont want to advertise, but am on my phone

__ https://twitter.com/i/web/status/1268534911012671489
This shows it well, but its the wrong channel for this discussion
It will be interesting to see how current GLFO handles Vermeer , if they optimized it
Early gens had raw pressure stamps of the machines used for soldering , while the sideclamps remained
But that again us the wrong channel for discussion :}

Can not suggest that you push it trough an oven, as 180c will be needed to melt the indium layer
Lapping makes sense, but desoldering not that much
Only custom loop blocks are near flat, while also arent flat at all


----------



## _frame_

Veii said:


> The same cooler on AMD IHS only pressures the corners


Opposite. The cooler pressures in the center only.


Veii said:


> Can not suggest that you push it trough an oven, as 180c will be needed to melt the indium layer


Yes, was thinking about it. will do by the end of the week.


----------



## Veii

_frame_ said:


> Opposite. The cooler pressures in the center only.












AUROS retweet back then about LGA and PGA
But the actual illustration fits
The center and the sides where bent higher when they where send to the factory
The heat and pressure clamps then went strongly into the layers
The center was pushed down and the sides where pushed down
Creating such type of waterdrop effect while still remaining convex (a tiny ring at the center, a bigger ring on the outside)
The sides are higher than the center, soo in reality with convex coolers, only the outer ring is cooled unless you use a lot of paste
The "center" changed slowly between TSMC and GFLO, and it has to be seen if the head spreader is send to GLFO or made locally

But it remains that the outer ring has a higher position than the center
Well its processed and by intention deformed before its put through the soldering process, to offset it
But as its not optimal, or at least wasn't ~ it created a ripple wave type of effect


----------



## _frame_

Veii said:


> But it remains that the outer ring has a higher position than the center


Maybe this was in the past. Both 5600X I've tested has contact point with convex base of Assassin III in the center. I can make a photo later.


----------



## Veii

_frame_ said:


> Maybe this was in the past. Both 5600X I've tested has contact point with convex base of Assassin III in the center. I can make a photo later.


They really try to improve the heatspreader and keep the top layer as flat as possible
But once you start lapping the top layer away, the layers and pressure stamps appear 
Can't deny you, 5600X still waits to be lapped
I like my sample and likely will do it
Only has 2 mediocre cores, the other ones are platinum 1's

I am curious what type of solder machine they use, 
(If they changed the factory)
the variations of stamps really is interesting and fascinating 😇
Like a fingerprint if the factory


----------



## _frame_

Veii said:


> Can't deny you, 5600X still waits to be lapped


It is easy to make lapping for cpu. But how to do it properly for convex base of cooler?


----------



## Veii

_frame_ said:


> It is easy to make lapping for cpu. But how to do it properly for convex base of cooler?


Oh ignore the cooler 
Or lap the cooler afterwards
I started with 800 & 1200 grit, and still think to keep the same method
Takes 2h per layer with water on an ∞ loop/hand movement

You press the cpu on the pins with 3 fingers/flat and listen to music
It needs contineous 2h a layer at the same hand movement speed
First top layer till you reach copper, then clean the sandpaper a bit with more water and continue till the paper is fully brown gold'ish
Then you switch to 1200 grit and continue for 1-2 more hours
600 or 800 grit is just to remove the top silver layer
The clamp side stamps will take the longest to remove and flatten out fully

I would not use LM on the silver metal layer, its ot a good idea and not very clean mixture
Edit:
* it needs to be done on a glas or smooth ceramic surface
As every little cut, dent or spike will appear on the heatspreader
Soo you want something as liquid smooth as possible for a surface


----------



## _frame_

Veii said:


> Oh ignore the cooler


No reason to lap only cpu, the cooler must be flat as well. Again, I know how to do it with cpu. But the same way will not work with convex cooler.


----------



## Veii

_frame_ said:


> No reason to lap only cpu, the cooler must be flat as well. Again, I know how to do it with cpu. But the same way will not work with convex cooler.


Home sweet home 

Why wouldn't it ?
the 3 fingers holding/pressing method
just that you hold a bigger chunk of cooler and equal movement is harder 
there should be space between the heatpipes and the block 

I see no issue with any shape and form of cooler 
all ends up flat 
there is a point to do it , as the thick heatsink gets smaller.
you do get couple of degrees out

i just dont know how you'd get equal movement on a cpu block (AIO) but on a normal cooler it should be fine at just lower movement speed
Unless you use a machine or something else.
I only know the manual by hand method - and see no reason why any surface height would make a difference


----------



## _frame_

Veii said:


> Why wouldn't it ?


have you tried it by yourself? I mean convex base of a cooler. I did. And it does not work, unless you are going to shave 3+ mm. Because there is no way you can hold the cooler for every lapping movement in the exact position to lap only center of it. It will always be on the side! I see the only 1 way: it is to glue something to the corners of the base of a cooler to match height difference with the center. And then start lapping.


----------



## Veii

_frame_ said:


> have you tried it by yourself? I mean convex base of a cooler. I did. And it does not work, unless you are going to shave 3+ mm. Because there is no way you can hold the cooler for every lapping movement in the exact position to lap only center of it. It will always be on the side! I see the only 1 way: it is to glue something to the corners of the base of a cooler to match height difference with the center. And then start lapping.


you do infinite circles , 8's and hold the same speed
only the weight of the thing you hold matters but not really the shape

i'm not lapping specific parts of it 
flat = flat  
however many layers it takes to reach flat 
on the cpu you can see it by the different materials
on the cooler it's harder ~ soo mostly only time plays a role
after you reach copper on the CPU , you also work blind your way down 

I don't know how to describe "feeling" 
but i see no difference between both 
the only problematic part could be an AIO
where you should tape the radiator to your arm, soo no random tube movements gets in your way


----------



## Veii

LuckyImperial said:


> Hey Guys/Gals,
> 
> I've been lurking for the past 6 or 10 pages, and I've seen a lot of timings posted for BDie in _very fast_ configurations paired with a 5000 series CPU, but I think it's time that I ask for help.
> 
> I have two 8Gb sticks of GSkill Trident Z 3200 CL14. I know it's Bdie (what version I don't know). Right now it's sitting in DOCP. At one point I punched in values from Ryzen Memory Calculator for 3466 Fast, see below, and everything ran well, but I'd like to get your help implementing a conservative OC/timings for my memory. Were my timings with the calculator pretty decent? Should I just go back to those?
> 
> I'm a newb when it comes to memory OCing, but I know my way around the BIOS fairly well and to reiterate; I'm looking for help reaching a stable, conservative memory OC for a gaming PC.
> 
> View attachment 2479239


You can use this set to stabilize voltages & push FCLK & BLCK








Runs at <1.35v @ 3800MT/s or 1.46v at 4200MT/s 
3800MT/s requires tCKE 9, 3-3-15 CAD_BUS Setup time
* If your PCB can't do tRDWR 7, give it +1

Dual Rank & 4 dimm people, need +2 on tRDWR @ 36.9 proc & RTT 6/3/3
4x 16GB people need tRRD 6-8 , tFAW 24 & tRDWR +3/+4 @ procODT 44ohm
both at 1-4-4-1-6-6 SD, DD

** 1T or 2T doesn't matter, only changes required voltage
it's equally well on 2T mode


----------



## Flash1228

Veii said:


> You can use this set to stabilize voltages & push FCLK & BLCK
> View attachment 2479280
> 
> Runs at <1.35v @ 3800MT/s or 1.46v at 4200MT/s
> 3800MT/s requires tCKE 9, 3-3-15 CAD_BUS Setup time
> * If your PCB can't do tRDWR 7, give it +1
> 
> Dual Rank & 4 dimm people, need +2 on tRDWR @ 36.9 proc & RTT 6/3/3
> 4x 16GB people need tRRD 6-8 , tFAW 24 & tRDWR +3/+4 @ procODT 44ohm
> both at 1-4-4-1-6-6 SD, DD
> 
> ** 1T or 2T doesn't matter, only changes required voltage
> it's equally well on 2T mode


Would these settings be similar and/or relevant to Micron rev. E? I know a decent bit about differences in settings between ICs (B-die vs CJR vs DJR etc.) so I'm assuming these settings wouldn't directly translate to my setup.

I've got a 5800x and a set of 4x8GB Ballistix 4000CL18 that I've been running at 3800CL16 without issues using a combination of the Ryzen DRAM calculator and the GitHub page. I can boot 4000 with 1:1 fclk, but I get tons of WHEA warnings in event viewer. 

I've got a fair amount of experience in overclocking a 2x8GB set of CJR I had with my 2700X and obviously the trial and error with this Ballistix, but I have really no idea where to go with getting rid of the WHEAs.


----------



## LuckyImperial

@Veii This may be obvious but I want to confirm that when you say "3-3-15 CAD_BUS Setup Time" you are referring to tRDRDSCL, tWRWRSCL and tCWL?

I wish I knew what the acronyms meant. Gamers Nexus seems like they've started a guide but haven't finished it.


----------



## Veii

LuckyImperial said:


> @Veii This may be obvious but I want to confirm that when you say "3-3-15 CAD_BUS Setup Time" you are referring to tRDRDSCL, tWRWRSCL and tCWL?


CAD_BUS Setup Time = Data Bus Setup Time


----------



## craxton

Veii said:


> Idk the "IHS is perfectly flat" part
> They never where
> Not with first gen and not with 3rd gen
> This one is not different
> 
> 5600X if it has 2x die temp (hwinfo) means it has 2 CCDs
> While one is supposed to deep sleep
> If the difference is only that much, it does mean the headspreader does do its job to spread heat
> 
> If you mean 5600X to 5600X
> Means, something else is going on
> Heatspreaders from the same factory, nearly always have the same pressure patterns
> The solder is most of the times equalized
> But the "needed voltage for X frequency" changes a lot between units
> So alsp temperature will change
> 
> Unless you tracked VDDP,VDDG,SOC predicted voltage and know they where set equal
> The data you got without VID tracking is invalid
> But i can see for example on a 5950X and 5900X that there is a 8c delta between both CCDs
> That was half because of the CCD quality and half because of the CPUs being concave
> Although centered by intention higher designed and convex (like a little soundwave/water drop)





Veii said:


> View attachment 2479259
> 
> 
> AUROS retweet back then about LGA and PGA
> But the actual illustration fits
> The center and the sides where bent higher when they where send to the factory
> The heat and pressure clamps then went strongly into the layers
> The center was pushed down and the sides where pushed down
> Creating such type of waterdrop effect while still remaining convex (a tiny ring at the center, a bigger ring on the outside)
> The sides are higher than the center, soo in reality with convex coolers, only the outer ring is cooled unless you use a lot of paste
> The "center" changed slowly between TSMC and GFLO, and it has to be seen if the head spreader is send to GLFO or made locally
> 
> But it remains that the outer ring has a higher position than the center
> Well its processed and by intention deformed before its put through the soldering process, to offset it
> But as its not optimal, or at least wasn't ~ it created a ripple wave type of effect


sorry to chime in fellas, but
i would assume this is why my ML240L (coolermaster) AIO cools better than my EK 240D-rgb 240mm aio?

upto 7c difference between the two, using MX4 thermal paste, and cheap fans on the ML240L
where as the EK (USING MX4 on all coolers) using VARDAR fans only on it. 

im so confused as to why the cheaper product cools better,
when people praise the EK D-RGB so much more when its nearly 2.5x the price in US currency at this time, 
IF NOT MORE?

thinking about lapping the block on the EK, bc there is clearly something wrong when the ML doesnt see 76c
on prime stress tests, but the EK sees at best (FULL TILT ON all 9 120mm fans) 83c (this is without limiting PBO) 
never allow it to run long. was simply testing out the coolers. (are the cooler master fans that much better?) 
surly not, cant be, they dont look like theyll blow a piece of paper away?


----------



## LuckyImperial

@Veii 

Sweet, I got your 3800MT/s settings to work! I'm running it at 1.4v, just to be on the safe side. 

I also had to use 8 for tRDWR, since 7 didn't seem to want to boot. I set tCKE to 9 and used 3-3-15 for Data Bus Setup Time. 

Do you advise any stability testing? Memtest?


----------



## craxton

LuckyImperial said:


> Do you advise any stability testing? Memtest?


im not Veii, but its been said a-lot bc many of us have asked this same question, which has been answered
several times throughout this threads life within the short few months ive been here.

HCI memtest overnight, OCCT (1 hour at least, TM5 by 1usmus most (ive seen) use anta777 config file
(>EDIT-as someone (manna which can be seen below) corrected me, why its best to use 1usmus preset as itll tell what caused the error<)
(unsure why tho never asked | edit, now i know why),
prime95 (SFF overnight), y-cruncher (4 loops minimum)

(edit) (by the screenshots shared of OCCT most using version 7.0.0 (unsure why that is either)
(re-edit limit your PBO for OCCT, PRIME, and Y-cruncher) otherwise itll run your chip rather warm/hot

you can find all these on google for free. HCI can be paid for to avoid having to open several windows,
i would upload the full version thru gdrive, but considering how cheap it is, and most wont need to use the pro
just using the free version is good enough does the same thing.


----------



## ManniX-ITA

LuckyImperial said:


> @Veii might disagree, but higher LLC levels will result in excessive ringing when load drops...at least according to Raja and gang. Back in C6H OC days...Elmor, Stilt, and Raja all agreed it's better to simply run higher set voltages with lower LLC levels rather than running higher LLC levels with lower voltages.


Might disagree, don't know about earlier Ryzen but for 3000 and 5000 never have been successful with low LLC on anything.
When you are borderline with OC, either static or PBO or CO with 5000 you need high LLC.
Low LLC could work if you just need to run memory benchmarks or tests but not for general usage or more stressing benchmarks.
The CPU has a very nasty feature which is the Over Current Protection; low LLC levels will trigger it and the CPU will reset.

That's why the OCP range should be always set to 400mV; you can see how it kicks in playing with the range and LLC levels.
If you are too low in LLC and/or OCP just starting P95 Small FFT will reset the CPU.
Smaller you go with OCP and higher LLC you need to avoid resets.

Plus, at least on GB boards, OCP is bugged with 5000.
With 3000 works better the Enhanced level, with 5000 it's worse. Most stable is Medium and doesn't make sense.
On the MSI Unify-X setting either Auto or Enhanced doesn't really make a difference; seems always to kick in too easy.



craxton said:


> HCI memtest overnight, OCCT (1 hour at least, TM5 by 1usmus most use anta777 config file (unsure why tho never asked?),
> prime95 (SFF overnight), y-cruncher (4 loops minimum)


For TM5 we most use 1usmus config; there are detailed info on what could be the trigger for each error, with anta777 config you are on your own


----------



## wisebear

@ManniX-ITA Talking about LLC, in what situations one might want to raise the SOC one instead?


----------



## ManniX-ITA

wisebear said:


> @ManniX-ITA Talking about LLC, in what situations one might want to raise the SOC one instead?


Usually less critical than CPU.
Memory overclock, tight timings and high frequency can get unstable or less performant with low LLC.
CPU overlock with PBO; very important for 3000 with EDC bug and 5000 with CO.
Latest AGESA needs more LLC; early in the days with the 3000 could run with SOC Medium and even Low in some cases, latest releases they need High also on SOC.

I've recently tried to lower SOC LLC and PWM on the Unify-X and couldn't achieve it.
At best latency started to wiggle a lot; I'm back at LLC 2 and 1000 KHz cause at some point was always getting unstable.
Tight CO negative counts are very though; at LLC 4 and/or 700 PWM the 5950x can't make it.
Sometimes, especially cold boot, doesn't even boot into Windows.
Without CO is much easier, can run LLC 4 and PWM 700.


----------



## craxton

ManniX-ITA said:


> For TM5 we most use 1usmus config; there are detailed info on what could be the trigger for each error, with anta777 config you are on your own


for most posts ive seen, they speak of anta. most usually if someone sees an error they arent looking at whats the cause of it
especially someone who isnt extremely knowledgeable with ram etc, theyll see an error and start tweaking things.
i can see if these errors relate to what timings (perhaps, what part of the test is testing what timing?) 

this is something i didnt know, as stated most ive seen talk about not just thru this site, but others as well speak of anta777 extreme
as i stand corrected tho, ill correct what i said to Lucky.


----------



## T884G63

Veii said:


> You can use this set to stabilize voltages & push FCLK & BLCK
> View attachment 2479280
> 
> Runs at <1.35v @ 3800MT/s or 1.46v at 4200MT/s
> 3800MT/s requires tCKE 9, 3-3-15 CAD_BUS Setup time
> * If your PCB can't do tRDWR 7, give it +1
> 
> Dual Rank & 4 dimm people, need +2 on tRDWR @ 36.9 proc & RTT 6/3/3
> 4x 16GB people need tRRD 6-8 , tFAW 24 & tRDWR +3/+4 @ procODT 44ohm
> both at 1-4-4-1-6-6 SD, DD
> 
> ** 1T or 2T doesn't matter, only changes required voltage
> it's equally well on 2T mode


Hmm settings still don't get me above 1933 fclk
On 5900x Dark Hero, with 4 different sets of b-die
A0,A1, and A2 all easily do 3800C14

Can only go higher than 1933 fclk if out of sync

I haven't done a new build since x99 intel and haven't
ran AMD since old ass K6-2 and usually avoided 
touching ram timings outside of primaries.

Trying to wrap my head around exactly how to find 
the right Cad bus and Rtt settings at the same time 
as having zero understanding of how to calculate 
ram timings outside of Dram Calc is making my 
head spin lol.

Seeing people using widely different settings with no
connection to cpu sku, board models or ram pcb Rev
is quite interesting seems a lot of people are just 
shooting in the dark other than it looks like we have 
all realized we can back down on voltages.

I can hard mod and sub zero cool all day but this is a 
different ball game lol


----------



## wisebear

ManniX-ITA said:


> Latest AGESA needs more LLC; early in the days with the 3000 could run with SOC Medium and even Low in some cases, latest releases they need High also on SOC.


That is pretty much my experience aswell in terms of AGESA versions: on 1.1.0.0 i could get away with CPU LLC on AUTO (or worst case scenario, 'standard') to fix light load instabilities.
On AGESA 1.2.0.0 i can basically forget about keeping it on AUTO, even on a conservative OC.
The irony is of course having my 5800x capped at 5025 on AGESA 1.2.0.0 and still needing more LLC to basically achieve lower scores than i had on 1.1.0.0 anyway.

(BTW I tried F33b and, at least on my X570 Elite, it's the worst of them all so far in terms of CPU OC)


----------



## ManniX-ITA

craxton said:


> for most posts ive seen, they speak of anta. most usually if someone sees an error they arent looking at whats the cause of it
> especially someone who isnt extremely knowledgeable with ram etc, theyll see an error and start tweaking things.
> i can see if these errors relate to what timings (perhaps, what part of the test is testing what timing?)
> 
> this is something i didnt know, as stated most ive seen talk about not just thru this site, but others as well speak of anta777 extreme
> as i stand corrected tho, ill correct what i said to Lucky.


I mean about this thread 

Like @Veii posted earlier this:











And this one:










They are all related to 1usumus config.
If you run the anta config it's very likely you don't get this amount of info or help about it.


----------



## FleischmannTV

This setting has been running stable for me for months. It's 4x8GB Micron E-Die with VDDG CCD 950mV. 
Now I've tried _GDM disabled_ with _CR 2T_ and it posted and booted into Windows. Upon running TM5 1usmus_v3 the system crashed instantly with a BSOD. Any tips which settings to change first?


----------



## Veii

FleischmannTV said:


> This setting has been running stable for me for months. It's 4x8GB Micron E-Die with VDDG CCD 950mV.
> Now I've tried _GDM disabled_ with _CR 2T_ and it posted and booted into Windows. Upon running TM5 1usmus_v3 the system crashed instantly with a BSOD. Any tips which settings to change first?
> 
> 
> View attachment 2479361


Start with tRRD_L down to 6 , or rather better, tWTR_ up to 5-14 (for now)
Do try ClkDrvStr 60-20-40-20 , rev.e usually needs higher ClkDrvStr

Also try as alternative solution
40-20-20-20 , tCKE 9 with CAD_BUS Setup timings 3-3-15
This should likely work for 4 dimms (89% sure ~ unless something else is off)

You'd want to run 1-4-4-1-6-6 as SD , DD values for 4 dimms
Try
16
16
20
18
34
52
520-386-238
tWR 26
tRTP 13
tRDWR 11

else
576-428-263
tWR 24
tRTP 12

Get that baseline stable on 2T with correct RTT values
later you can go for 16-18-18 sets


T884G63 said:


> Hmm settings still don't get me above 1933 fclk
> On 5900x Dark Hero, with 4 different sets of b-die
> A0,A1, and A2 all easily do 3800C14
> 
> 
> T884G63 said:
> 
> 
> 
> I can hard mod and sub zero cool all day but this is a
> different ball game lol
Click to expand...

Sadly i can't say anything positive about the dark hero bioses
tried 8 of them , and maybe 3003 looks promising
But all of them have WHEA and FCLK lock issues

The only good bios was under SMU 56.30, but that is 1100 Patch B
while this and the unify start from Patch C with 1900FCLK hardlock
Unless someone ports SMU and ABL down on this bios - i see nothing good with it
even 1mhz higher than 1900 causes already a whea error rain
it's sad , but you can't do much 
Maybe you can find a decent 1180 AGESA biosor 1100 Patch D, but if that one really would have the new ABL is to be seen
currently it's a mess


----------



## T884G63

On previous Dark Hero bios's the work around for me
to get 1900 or higher fclk is always starting with

1. Set all voltages reboot
2. Set timings reboot
3. Start low Dram frequency and Fclk ie 3200/1600 reboot
4. Start walking up Dram / Fclk one step at a time
and reboot in between each step up

This worked like a charm for me every single time
across all earlier bios revisions.

On 3204 I am able to load a saved profile of 3800C14
1900 Fclk perfectly every time.

Higher than 1933 Fclk will still only go if not in sync.

@Veii I'm gonna try your CAD_BUS and Rtt settings
but with all digi LLC at auto and work up from auto
power settings.


----------



## Veii

T884G63 said:


> On previous Dark Hero bios's the work around for me
> to get 1900 or higher fclk is always starting with
> 
> 1. Set all voltages reboot
> 2. Set timings reboot
> 3. Start low Dram frequency and Fclk ie 3200/1600 reboot
> 4. Start walking up Dram / Fclk one step at a time
> and reboot in between each step up
> 
> This worked like a charm for me every single time
> across all earlier bios revisions.
> 
> On 3204 I am able to load a saved profile of 3800C14
> 1900 Fclk perfectly every time.
> 
> Higher than 1933 Fclk will still only go if not in sync.
> 
> @Veii I'm gonna try your CAD_BUS and Rtt settings
> but with all digi LLC at auto and work up from auto
> power settings.


I mean, we can boot 2000 FCLK with lower CPU VDDP , near 880mV and IOD at 1060
SOC near 1.2ish 
but it makes no sense, as there is a fundamental bios issue on AGESA 1.2.0.0 
eh everything beyond 1.1.0.0 Patch B, tbh


----------



## FleischmannTV

@Veii 

16-16-20-18 is meant as shown in ZenTimings, right? I'm asking because in MSI's BIOS the order is different.

Regarding tRAS 34 tRC 52, I think one of them may be too tight for my E-Dies, because I cannot post with these settings. I've seen examples with that tight tRAS, but tRC is always around 60 at 3800 MHz. Regarding tRFC, I have a 300 ns wall, so I didn't even try 520-386-238 and went with 576-428-263 instead.

Anyway, these settings seem to be running well so far, Latency is still 0.2 ns lower und it survived the first 90 minutes of Karhu, then I had to stop because I needed the PC.


----------



## Veii

FleischmannTV said:


> @Veii
> 
> 16-16-20-18 is meant as shown in ZenTimings, right? I'm asking because in MSI's BIOS the order is different.
> 
> Regarding tRAS 34 tRC 52, I think one of them may be too tight for my E-Dies, because I cannot post with these settings. I've seen examples with that tight tRAS, but tRC is always around 60 at 3800 MHz. Regarding tRFC, I have a 300 ns wall, so I didn't even try 520-386-238 and went with 576-428-263 instead.
> 
> Anyway, these settings seem to be running well so far, Latency is still 0.2 ns lower und it survived the first 90 minutes of Karhu, then I had to stop because I needed the PC.
> 
> View attachment 2479426


Rev.E PCB do have a tRFCns wall near 300 but it's not perfect 300
tRC should be lower
at least that runs
here is a rev.E set by cm87








It's lower than 300ns 
but i think tRC should be able to get lower
You can also see that tWR 16 could work

EDIT:
One more thing, Rev.E should allow you to run tRDWR down to tRCD /2 (-2) 
8 should work, 9 will work


----------



## T884G63

@Veii what LLC / power settings have you been
testing with?

1.8 PLL for 1900-2000+?

I was just able to boot 1966 in sync with auto LLC /
power settings with just your voltages but auto
ram timings.

Gonna try my 3800C14 profile LLC / power settings
but with your voltage settings on auto timings and
see if I can finally get boot 2000


----------



## LuckyImperial

Spoiler: 3800 @ 1.35v






Veii said:


> You can use this set to stabilize voltages & push FCLK & BLCK
> View attachment 2479280
> 
> Runs at <1.35v @ 3800MT/s or 1.46v at 4200MT/s
> 3800MT/s requires tCKE 9, 3-3-15 CAD_BUS Setup time
> * If your PCB can't do tRDWR 7, give it +1
> 
> Dual Rank & 4 dimm people, need +2 on tRDWR @ 36.9 proc & RTT 6/3/3
> 4x 16GB people need tRRD 6-8 , tFAW 24 & tRDWR +3/+4 @ procODT 44ohm
> both at 1-4-4-1-6-6 SD, DD
> 
> ** 1T or 2T doesn't matter, only changes required voltage
> it's equally well on 2T mode






Unfortunately, although 3800MT/s settings would boot with 1.4v, it failed memtest pretty quick. I might go back and try @Joeking78 timings for 3733MT/s CL14 at 1.5v.


----------



## T884G63

Hmm did you try up to 1.45v ? Those are fairly loose
timings for b-die

My best so far is 3800C14 using Dram Calc settings
plus the above voltages and CAD_BUS and Rtt settings
shaved a few latency.

I'm running 1.52vdimm though


----------



## T884G63

@Veii any chance you could take quick look at my
Timings outside of the Dram Calc this is over my
head lol and you seem to have most of it memorized.

4x8 B-die

Thank you in advance if you can


----------



## craxton

T884G63 said:


> @Veii any chance you could take quick look at my
> Timings outside of the Dram Calc this is over my
> head lol and you seem to have most of it memorized.
> 
> 4x8 B-die
> 
> Thank you in advance if you can


as per Veii stated, these are something you can copy paste for 3800mhz, here


----------



## Veii

T884G63 said:


> @Veii any chance you could take quick look at my
> Timings outside of the Dram Calc this is over my
> head lol and you seem to have most of it memorized.
> 
> 4x8 B-die
> 
> Thank you in advance if you can
> 
> 
> View attachment 2479449





http://imgur.com/UPsV9Ya

tRTP 9, forgot to add it


----------



## T884G63

Sweet thank you I will give it try.

It was was best compromise between speed and
latency I could do, not really understanding timings
outside of Dram calc lol


----------



## JoneKone

Veii said:


> Oh ignore the cooler
> Or lap the cooler afterwards
> I started with 800 & 1200 grit, and still think to keep the same method
> Takes 2h per layer with water on an ∞ loop/hand movement
> 
> You press the cpu on the pins with 3 fingers/flat and listen to music
> It needs contineous 2h a layer at the same hand movement speed
> First top layer till you reach copper, then clean the sandpaper a bit with more water and continue till the paper is fully brown gold'ish
> Then you switch to 1200 grit and continue for 1-2 more hours
> 600 or 800 grit is just to remove the top silver layer
> The clamp side stamps will take the longest to remove and flatten out fully
> 
> I would not use LM on the silver metal layer, its ot a good idea and not very clean mixture
> Edit:
> * it needs to be done on a glas or smooth ceramic surface
> As every little cut, dent or spike will appear on the heatspreader
> Soo you want something as liquid smooth as possible for a surface


No do not listen to what this man says, He knows nothing about how to lap. One does not continuosly do a single move lapping, this is how hand bias is created and the surface will reflect that effect with single sided and lopsided geometry. 



 Here is a video about thermal interface materials AND Lapping.


----------



## ManniX-ITA

JoneKone said:


> No do not listen to what this man says, He knows nothing about how to lap. One does not continuosly do a single move lapping, this is how hand bias is created and the surface will reflect that effect with single sided and lopsided geometry.
> 
> 
> 
> Here is a video about thermal interface materials AND Lapping.


LoL and that's your first post?
Congratz, really.


----------



## VPII

@ManniX-ITA so I did a full 1 hour OCCT run to check system stability as well as the TM% anta777 Extreme. THe temps shown in OCCT for CPU is a little off taken what Hwinfo64 is showing, but I stand to be corrected on that. I still do not like this PBO setup on the processor as temps is a little too high for my liking. This is with an all core -25 curve optimizer which I tested several times with OCCT. What I can do is leave the setup as is and disable the PBO limits then cpu temps would be way lower but so would performance. Still I am happy with it as is right now. Dimm temps was getting a little hot as in 44 during TM5, but then up to 46 while running OCCT but they held so I am happy. I do have two 120mm fans blowing over the memory which helped. My latency seems a little too high for the memory speed. The lowest I've had it was 56.9 but it was just after a fresh startup.


----------



## kratosatlante

Veii said:


> Oh ignore the cooler
> Or lap the cooler afterwards
> I started with 800 & 1200 grit, and still think to keep the same method
> Takes 2h per layer with water on an ∞ loop/hand movement
> 
> You press the cpu on the pins with 3 fingers/flat and listen to music
> It needs contineous 2h a layer at the same hand movement speed
> First top layer till you reach copper, then clean the sandpaper a bit with more water and continue till the paper is fully brown gold'ish
> Then you switch to 1200 grit and continue for 1-2 more hours
> 600 or 800 grit is just to remove the top silver layer
> The clamp side stamps will take the longest to remove and flatten out fully
> 
> I would not use LM on the silver metal layer, its ot a good idea and not very clean mixture
> Edit:
> * it needs to be done on a glas or smooth ceramic surface
> As every little cut, dent or spike will appear on the heatspreader
> Soo you want something as liquid smooth as possible for a surface


hi, how much reduce the temp lapping the cpu, work for air cooler or only if have water custom? now have air 212 evo but thinkin in upgrade to aio 360rad or custom + 240 x2


----------



## ManniX-ITA

VPII said:


> @ManniX-ITA so I did a full 1 hour OCCT run to check system stability as well as the TM% anta777 Extreme. THe temps shown in OCCT for CPU is a little off taken what Hwinfo64 is showing, but I stand to be corrected on that. I still do not like this PBO setup on the processor as temps is a little too high for my liking. This is with an all core -25 curve optimizer which I tested several times with OCCT. What I can do is leave the setup as is and disable the PBO limits then cpu temps would be way lower but so would performance. Still I am happy with it as is right now. Dimm temps was getting a little hot as in 44 during TM5, but then up to 46 while running OCCT but they held so I am happy. I do have two 120mm fans blowing over the memory which helped. My latency seems a little too high for the memory speed. The lowest I've had it was 56.9 but it was just after a fresh startup.
> 
> View attachment 2479466


OCCT is using HWInfo now to monitor; if you run both in parallel the readings will be slightly messed up as they have to fight to access the same driver.

The temps seems in check; if the average temp running OCCT is 65-75c it's normal. You need something very special to cool it better than that.

DIMMs temp are nothing to worry about at 44c.
I'm running at 1.54v and they tops 53-54c after 1h TM5 without any issue.
I have a single 140mm fan blowing down at 1100rpm.

The latency seems to be way too high....
The power plan, background running programs, anything can influence it.
You need to test 10-15 times till it gets flat to be sure is right.
And definitely test it before opening HWInfo or any other bench/monitoring software like OCCT, CPU-Z, GB...

What you should fix:

tRC 48
tRFC multiple of 16

Try:

tCKE to 1 unless 24 is really needed
tCWL 14
ProcODT to 37
Higher VDIMM, 1.47v it's a sweet spot and reduce tRFC, bring SCL down to 2/3 (may need different tRDWR,tWRRD, I use for DR 10/1 for SCL 2)
Higher VSOC at 1.15v and higher CCD/IOD 1000/1060; better scores


----------



## VPII

ManniX-ITA said:


> OCCT is using HWInfo now to monitor; if you run both in parallel the readings will be slightly messed up as they have to fight to access the same driver.
> 
> The temps seems in check; if the average temp running OCCT is 65-75c it's normal. You need something very special to cool it better than that.
> 
> DIMMs temp are nothing to worry about at 44c.
> I'm running at 1.54v and they tops 53-54c after 1h TM5 without any issue.
> I have a single 140mm fan blowing down at 1100rpm.
> 
> The latency seems to be way too high....
> The power plan, background running programs, anything can influence it.
> You need to test 10-15 times till it gets flat to be sure is right.
> And definitely test it before opening HWInfo or any other bench/monitoring software like OCCT, CPU-Z, GB...
> 
> What you should fix:
> 
> tRC 48
> tRFC multiple of 16
> 
> Try:
> 
> tCKE to 1 unless 24 is really needed
> tCWL 14
> ProcODT to 37
> Higher VDIMM, 1.47v it's a sweet spot and reduce tRFC, bring SCL down to 2/3 (may need different tRDWR,tWRRD, I use for DR 10/1 for SCL 2)
> Higher VSOC at 1.15v and higher CCD/IOD 1000/1060; better scores


Hi, shot I will give that a try... problem is when running Aida64 I almost always have Hwinfo64 running so that might be part of the problem.


----------



## ManniX-ITA

VPII said:


> Hi, shot I will give that a try... problem is when running Aida64 I almost always have Hwinfo64 running so that might be part of the problem.


Indeed, running HWInfo will cost you 1-3 ns in latency.
I know cause sometimes I forget it's there in the systray and wonder what is happening


----------



## Not a redditor

hey, can i improve the latency from this point ? i can only see improvement from cpu oc but i cannot be stable after 4.5-4.5/4.4-4.4 ram voltage needed 1.55 for stability and fro0m what i saw vsoc this high is needed for lower vcore to be stable to output less heat


----------



## LuckyImperial

T884G63 said:


> Hmm did you try up to 1.45v ? Those are fairly loose
> timings for b-die
> 
> My best so far is 3800C14 using Dram Calc settings
> plus the above voltages and CAD_BUS and Rtt settings
> shaved a few latency.
> 
> I'm running 1.52vdimm though


I just dialed it up to 1.45v and memtest seems to be happy. I guess I'm just a little surprised that it took more than 1.4v, but I guess I shouldn't be. It's a pretty hefty OC for my 3200 sticks.

Now I need to save my profile, write my timings/voltages down, and never have to deal with this again (fingers crossed haha).


----------



## Veii

Not a redditor said:


> hey, can i improve the latency from this point ? i can only see improvement from cpu oc but i cannot be stable after 4.5-4.5/4.4-4.4 ram voltage needed 1.55 for stability and fro0m what i saw vsoc this high is needed for lower vcore to be stable to output less heat


Half procODT - it's too high , only pushes minimum required voltage high
36.9 should run, but even 40 is way better than 60
tRDWR 9, tWRRD 3

Lower is not always better on tRRD and tWTR
better run tCWL = tCL and work your way on tRP down
^ also gives the ability to lower tRDWR which does help quite a bit

SCL you can probably go down later -1 and using tWRRD 4 , but you have to check
This set looks scuffed ^^'
If you're already going for low tertiaries and high tRDWR, go for tRAS 28, tRC 29
EDIT 2:
Dual Rank units need tWRRD delay, between 2-4


Spoiler: Example

















LuckyImperial said:


> I just dialed it up to 1.45v and memtest seems to be happy. I guess I'm just a little surprised that it took more than 1.4v, but I guess I shouldn't be. It's a pretty hefty OC for my 3200 sticks.
> 
> Now I need to save my profile, write my timings/voltages down, and never have to deal with this again (fingers crossed haha).
> 
> View attachment 2479486


you can try if tRDWR 7 would boot on your dimms
Only good PCBs can do -1 
If you can manage it, then you pretty much can drop SCL to 2 afterwards with 10mV more on VDIMM

EDIT:
Also you are running 1:1:2 mode
UCLK is halfed on your side
enforce UCLK == MCLK ,under AMD OVERCLOCKING - Infinity Fabric & Memory Dividers 

Should be also visible under CBS - NBIO - XFR Enchancements
But check first AMD OVERCLOCKING


----------



## LuckyImperial

Veii said:


> Half procODT - it's too high , only pushes minimum required voltage high
> 36.9 should run, but even 40 is way better than 60
> tRDWR 9, tWRRD 3
> 
> Lower is not always better on tRRD and tWTR
> better run tCWL = tCL and work your way on tRP down
> ^ also gives the ability to lower tRDWR which does help quite a bit
> 
> SCL you can probably go down later -1 and using tWRRD 4 , but you have to check
> This set looks scuffed ^^'
> If you're already going for low tertiaries and high tRDWR, go for tRAS 28, tRC 29
> EDIT 2:
> Dual Rank units need tWRRD delay, between 2-4
> 
> 
> Spoiler: Example
> 
> 
> 
> 
> View attachment 2479487
> 
> 
> 
> 
> you can try if tRDWR 7 would boot on your dimms
> Only good PCBs can do -1
> If you can manage it, then you pretty much can drop SCL to 2 afterwards with 10mV more on VDIMM
> 
> EDIT:
> Also you are running 1:1:2 mode
> UCLK is halfed on your side
> enforce UCLK == MCLK ,under AMD OVERCLOCKING - Infinity Fabric & Memory Dividers
> 
> Should be also visible under CBS - NBIO - XFR Enchancements
> But check first AMD OVERCLOCKING


I didn't find anything under AMD Overclock ->Infinity Fabric & Memory Dividers. That only had FCLK set values.

Under CBS->NBIO->XFR Enhancments I set UCLK == MCLK, but it doesn't seem to stick.

I still have the same 850MHz UClock.


----------



## Veii

LuckyImperial said:


> I didn't find anything under AMD Overclock ->Infinity Fabric & Memory Dividers. That only had FCLK set values.
> 
> Under CBS->NBIO->XFR Enhancments I set UCLK == MCLK, but it doesn't seem to stick.
> 
> I still have the same 850MHz UClock.
> View attachment 2479495


enforce FCLK frequency there too - and search for armory crate , to disable ASUS Bloatware 
Else you might need to downgrade to 3402 

But just in case, enable UncoreOC mode


----------



## LuckyImperial

Veii said:


> enforce FCLK frequency there too - and search for armory crate , to disable ASUS Bloatware
> Else you might need to downgrade to 3402
> 
> But just in case, enable UncoreOC mode



I set fCLK to 1800 under XMP Enhancements, along with enabling UncoreOC Mode, and I'm still at 950MHz. 

I never installed Armory Crate...and Windows search doesn't find anything.

Bummer, I think this is either a BIOS bug or a disabled setting for Asus TUF Gaming X570-Plus in 3405 bios.


----------



## FleischmannTV

Veii said:


> Do try ClkDrvStr 60-20-40-20 , rev.e usually needs higher ClkDrvStr
> Also try as alternative solution
> 40-20-20-20 , tCKE 9 with CAD_BUS Setup timings 3-3-15


If both methods work, is there a reason to prefer one over the other?


----------



## T884G63

Veii said:


> http://imgur.com/UPsV9Ya
> 
> tRTP 9, forgot to add it


Hmm no go, it bios locked on me gonna have to
rest cmos and start fresh


----------



## Veii

LuckyImperial said:


> I set fCLK to 1800 under XMP Enhancements, along with enabling UncoreOC Mode, and I'm still at 950MHz.
> 
> I never installed Armory Crate...and Windows search doesn't find anything.
> 
> Bummer, I think this is either a BIOS bug or a disabled setting for Asus TUF Gaming X570-Plus in 3405 bios.


Bios search 
Else it will preload (already did) a resource service which opts you into using armory crate and keeps running in the background directly after the reinstall
(don't want to call it Spyware out of respect, but that's about what spyware usually does)

The set you run, should move near 54-55.2ns at worst
If you peak at 58ns, you know that 2:1 mode is engaged

Can you do me a favor and check if this bios is usable ?
dlcdnets.asus.com/pub/ASUS/mb/SocketAM4/TUF_GAMING_X570-PLUS/TUF-GAMING-X570-PLUS-ASUS-2802.ZIP
I've checked all the links from 2607-2812 and there is no SMU 56.30
The best i could find is 56.33
It's unclear if it's the Patch-C or still B, as C with 56.34 had a 1900FCLK hardlock and broken memory training
But maybe up to 2100FCLK is usable on this one

BAR support and PCIe revision change existed since 56.30, and Patch-C was a marketing lie
Same as negative Curve Optimizer existed on 56.30 and not broken C or D


FleischmannTV said:


> If both methods work, is there a reason to prefer one over the other?


CAD_BUS Setup timings should only be used with tCKE ,
tCKE is a powerdown feature same as RTT control on die termination impedance ~ or dynamic on-die termination
Both are very important to keep the Data-Eye clean and don't make the signal reflect backwards

I think finetuned tCKE helps a lot with stability and it's being reported that it has positive latency effects
But it needs a specific set, else it wont work 
And tCKE + Setup Time is MCLK specific. It changes by speeds


T884G63 said:


> Hmm no go, it bios locked on me gonna have to
> rest cmos and start fresh


Probably vDIMM was too low for the low tRFC
How much do you use ?
increase it


----------



## T884G63

LuckyImperial said:


> I didn't find anything under AMD Overclock ->Infinity Fabric & Memory Dividers. That only had FCLK set values.
> 
> Under CBS->NBIO->XFR Enhancments I set UCLK == MCLK, but it doesn't seem to stick.
> 
> I still have the same 850MHz UClock.
> View attachment 2479495


Strange for me on Asus x570 all I have to do is use
the Extreme Tweaker page and manually set FCLK
to half of Memory frequency and it always locks
1:1:1 I have never had to touch anything in the AMD
menus


----------



## LuckyImperial

Veii said:


> Bios search
> Else it will preload (already did) a resource service which opts you into using armory crate and keeps running in the background directly after the reinstall
> (don't want to call it Spyware out of respect, but that's about what spyware usually does)
> 
> The set you run, should move near 54-55.2ns at worst
> If you peak at 58ns, you know that 2:1 mode is engaged
> 
> Can you do me a favor and check if this bios is usable ?
> dlcdnets.asus.com/pub/ASUS/mb/SocketAM4/TUF_GAMING_X570-PLUS/TUF-GAMING-X570-PLUS-ASUS-2802.ZIP
> I've checked all the links from 2607-2812 and there is no SMU 56.30
> The best i could find is 56.33
> It's unclear if it's the Patch-C or still B, as C with 56.34 had a 1900FCLK hardlock and broken memory training
> But maybe up to 2100FCLK is usable on this one


Eh, flashing BIOS's back and forth is not something I want to do. I'm just too lazy for that.

I wanted to OC my memory easily, and this is becoming quite the process haha.



T884G63 said:


> Strange for me on Asus x570 all I have to do is use
> the Extreme Tweaker page and manually set FCLK
> to half of Memory frequency and it always locks
> 1:1:1 I have never had to touch anything in the AMD
> menus


Also, I was able confirm that uclk and mclk "preload" 1:1 when my mclk is 1733MHz. I haven't tested anything higher than that yet.


----------



## T884G63

VPII said:


> @ManniX-ITA so I did a full 1 hour OCCT run to check system stability as well as the TM% anta777 Extreme. THe temps shown in OCCT for CPU is a little off taken what Hwinfo64 is showing, but I stand to be corrected on that. I still do not like this PBO setup on the processor as temps is a little too high for my liking. This is with an all core -25 curve optimizer which I tested several times with OCCT. What I can do is leave the setup as is and disable the PBO limits then cpu temps would be way lower but so would performance. Still I am happy with it as is right now. Dimm temps was getting a little hot as in 44 during TM5, but then up to 46 while running OCCT but they held so I am happy. I do have two 120mm fans blowing over the memory which helped. My latency seems a little too high for the memory speed. The lowest I've had it was 56.9 but it was just after a fresh startup.
> 
> View attachment 2479466


Wow 4x8 @1T with GDM off running @3800 in sync!

I just had to try your setting and first I ran with Veii's
recommended CAD_BUS, Rtt, ProcODT, and voltage
settings and was a no go.

Then tried your CAD_BUS, Rtt, and ProcODT with
Veii's voltages and no go.

But copied your settings to a T and bam posted and
Booted first go ***

Been trying to run 4x8 1T @3800+ on AMD coming
from intel has been a nightmare.


----------



## T884G63

Veii said:


> Probably vDIMM was too low for the low tRFC
> How much do you use ?
> increase it


Shouldn't be was at 1.53v


----------



## Trusconi85

PJVol said:


> Not an asus board owner, but have seen it quite a few times, that their bioses have something like "fmax" feature set by default. If so, try to disable it and see if it will help.
> 
> *PS: Found it: "PBO FMax Enhancer" - it should be disabled with ryzen 5000's *


 just found it and disabled : nothing changed
(yes, 5600x is still stock, i am playing only with memory now)


----------



## Veii

T884G63 said:


> Shouldn't be was at 1.53v


Then probably it was too much voltage







^ by @Bravoroni
1.35-1.36v works








There are 3 points i try to make

RTT values have a specific voltage range
705 for example (2x8) works worse than 706, PCB crashes after 1.52v
005 works better at low voltages but is too much strain on higher one

713 vs 013 is the same thing
633 is something new and should only be used by a specific method
This also includes sharing CAD_BUS 40-20-20-20 without SETUP time
They go together and only work with correct tCKE
Using them without tCKE worsens the experience and makes no sense to recommend

The same goes for 706
both are custom and new
But if you do not replicate it correctly ~ it wont work
I hope people stop sharing 3-3-15 Setup Timings without everything that belongs to them
They don't go alone

Oh last thing,
You where on 15-15-15 , this is 16-16-16
Bump it up 200mhz, to 4000 and we have the same "harshness" on the dimms
-1 tCL, -1 tRCD is a big jump
Don't overestimate it please. Of course 16-16-16 on 3800 is easy to run
But check the latency results. @VPII needs to check his set or voltages
something is quite slow compared to what i (he) get(s) on both CPUs @ stock (with curve optimizer fixes)


----------



## _frame_

Joeking78 said:


> I have the same kit in 2x16gb
> 
> You should easily be able to hit 3733 C14 1.5V, 4000 C16 1.47v ish...3600 C14 would be a nice overclock with around 1.42v to 1.45v would be my guess for daily use.
> 
> 3733 C14, 1.5v
> 
> View attachment 2479243
> 
> 
> 4000 C16 1.48v
> View attachment 2479244
> 
> 
> 4066 C16 1.52v
> View attachment 2479245


Thank you very much!
This was exactly what I need! As soon as I set tRCDRD to 17 instead of 16, my system become stable! 2000 Mhz 1:1:1
Vdimm 1.4 V !









* Veii*
Sadly but none of your recommendations works in my case. The only solution was tRCDRD = 17
As you can see on the screenshot above. CLDO VDDP = 1 V (auto on Asus board) is fine. RTT and CMD auto (default)
And screenshot with AUTO subtimings:


----------



## T884G63

Veii said:


> Then probably it was too much voltage
> 
> 
> 
> 
> 
> 
> 
> ^ by @Bravoroni
> 1.35-1.36v works
> 
> 
> 
> 
> 
> 
> 
> 
> There are 3 points i try to make
> 
> RTT values have a specific voltage range
> 705 for example (2x8) works worse than 706, PCB crashes after 1.52v
> 005 works better at low voltages but is too much strain on higher one
> 
> 713 vs 013 is the same thing
> 633 is something new and should only be used by a specific method
> This also includes sharing CAD_BUS 40-20-20-20 without SETUP time
> They go together and only work with correct tCKE
> Using them without tCKE worsens the experience and makes no sense to recommend
> 
> The same goes for 706
> both are custom and new
> But if you do not replicate it correctly ~ it wont work
> I hope people stop sharing 3-3-15 Setup Timings without everything that belongs to them
> They don't go alone
> 
> Oh last thing,
> You where on 15-15-15 , this is 16-16-16
> Bump it up 200mhz, to 4000 and we have the same "harshness" on the dimms
> -1 tCL, -1 tRCD is a big jump
> Don't overestimate it please. Of course 16-16-16 on 3800 is easy to run
> But check the latency results. @VPII needs to check his set or voltages
> something is quite slow compared to what i (he) get(s) on both CPUs @ stock (with curve optimizer fixes)


Hmm so started fresh copied your 3800/4200
settings to a T and lowered vdimm to 1.51
can't post higher than 3400

But copying @VPII settings to a T posts and boots
@3800 1T first try.... can 1T vs 2T not be that big of
deal for AMD coming from intel it's quite a
difference.


----------



## _frame_

And some AIDA results. CPU at 4800 Mhz is not fully stable yet.


----------



## Trusconi85

_frame_ said:


> And some AIDA results. CPU at 4800 Mhz is not fully stable yet.
> View attachment 2479519


My best score...maybe Veii can suggest something to improve 
1T does not work even at 1.4v
i try also this parameter but @4000








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Opposite. The cooler pressures in the center only. AUROS retweet back then about LGA and PGA But the actual illustration fits The center and the sides where bent higher when they where send to the factory The heat and pressure clamps then went strongly into the layers The center was pushed...




www.overclock.net




but won't boot


----------



## kratosatlante

_frame_ said:


> Thank you very much!
> This was exactly what I need! As soon as I set tRCDRD to 17 instead of 16, my system become stable! 2000 Mhz 1:1:1
> Vdimm 1.4 V !
> View attachment 2479517
> 
> 
> * Veii*
> Sadly but none of your recommendations works in my case. The only solution was tRCDRD = 17
> As you can see on the screenshot above. CLDO VDDP = 1 V (auto on Asus board) is fine. RTT and CMD auto (default)
> And screenshot with AUTO subtimings:
> View attachment 2479534


too short run as admin, and more clycles, i have capture pas tm5 20 cycles at fclk 2000





















but other test occt o ycruncher get whea


----------



## T884G63

Trusconi85 said:


> My best score...maybe Veii can suggest something to improve
> 1T does not work even at 1.4v
> i try also this parameter but @4000
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Opposite. The cooler pressures in the center only. AUROS retweet back then about LGA and PGA But the actual illustration fits The center and the sides where bent higher when they where send to the factory The heat and pressure clamps then went strongly into the layers The center was pushed...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> but won't boot


Lol ya I don't think your gonna get 4 dimm's to run 
@1T on AMD with decent timings.

3800 is this highest I can get @1T with GDM off
even up 1.6vdimm with 4x8 b-die across A0,A1,and A2 PCB's


----------



## T884G63

Finally posted and booted above 1933 fclk...
Got where I was aiming 4000/2000 and surprisingly
was only able to get there by using *Auto* ProcODT,
Rtt, DrvStr

As well as had to increase voltages across the board
and still had to walk the fclk up from 1800 while
keeping the memory locked at 4000 until I got it to
2000 and it still didn't want to had to go up and down
a few times before it locked in....

And all that got into windows and the Latency is
higher as well as R/W is lower than 3733/1866
3800/1900 LOL ***... 

I'm assuming it is correlated to voltages being off
currently adjusting to see if anything changes.


----------



## _frame_

kratosatlante said:


> too short run as admin, and more clycles, i have capture pas tm5 20 cycles at fclk 2000


Yes, I know. But before I had errors during this short test, so for now it is huge progress. I'll test more...


----------



## Sleepycat

Mine is not as high bandwidth or as low latency as your benches, but I am running 64GB (4x16GB) Samsung B-die. So this is what people recommend not to use, and I am feeling it with the lower max RAM speed that I can achieve. With just 2 sticks, I can run at 3866 / 1933 IF. But with 4 sticks, I'm limited to 3600 / 1800 IF.


----------



## craxton

here are TWO kits, one bought from amazon
the other bought from newegg, the (seemingly)
better kit is from amazon which is older, the other newegg.

both kits again, not a 4 pack, but are the same name, model, product sku.
have wrote team and all they tell me is YOU CAN NOT overclock our 3200mhz ram to 4000mhz 
its not able, and begins to direct me to there 4000c16 kit which "is the best they offer which is rated for"

all i really wanted to know was, why the switch with 4 different timings,
and at best to find out what PCB revision these kits are. as the response from "amazon"
and team-groups people there stated they dont use a standard PCB for t-force memory kits?

if typhoon burner wasn't a guessing game, it says A2.
but its been "proven" typhoon is just an educated guesser with someone changing a few things etc
cant explain but google can direct. (unsure if typhoon can be trusted with what pcb layer ram sticks are, but its suppose to take 
an educated guess at what DIE a stick is using,

here are the timings which was taking from typhoon burner, but the bios, aida, and CPUz all show 
that the timings for tRC, tFAW, TRRD_L, TRRD_S have changed quite some jump. 

Does this happen to (high performance "overclocking" ram) often?


----------



## mirzet1976

Here is mine


----------



## KedarWolf

mirzet1976 said:


> Here is mine
> View attachment 2479609


Can you run OCCT Large Data Set Extreme preset, see if you get WHEA errors?


----------



## mirzet1976

KedarWolf said:


> Can you run OCCT Large Data Set Extreme preset, see if you get WHEA errors?


There is no need for that I know I have them  i see them in HWInfo64


----------



## domdtxdissar

Have been running real (not aida64) memory benchmarks and pushing my 4x8gigs memory to the max, these are my results 
Seems to be able to ~match or atleast come close to 10900k's @ 5500mhz, 5000mhz uncore and ddr 4600cl6 in memory intensive benchmarks.
What works in Aida64 dont don't necessary work in real world / games.. 








Tomb Raider 1080 medium cpu+memory bench = 261 average CPU Game fps
*Free game on stream if anyone else want to try *
Only interested in "CPU Game" score, so gpu dont matter here.








Far cry 5 1080 ultra cpu+memory bench = 202 average fps
























All benchmarks performed on my old windows install with lots of bloatware... Think its gimping my scores. And my stock air cooler + stock bios(450w max) 3090 is also not helping.


----------



## PJVol

What's the point in your results? I found them almost useless and have nothing to do with memory performance, as long as the gpu impact involved in total score, be it overall or CPU only.


----------



## BluePaint

TR is a good benchmark for RAM performance in a game, imho
Here an older run on 5950X with 3800CL14 and 3080: 265 fps CPU Game


----------



## domdtxdissar

PJVol said:


> What's the point in your results? I found them almost useless and have nothing to do with memory performance, as long as the gpu impact involved in total score, be it overall or CPU only.


My point is that some people are tweaking their memory purely for latency AIDA numbers, which dont always correlate to real world performance..
How many low latency aida screenshots have i seen with lackbuster bandwidth and/or no proof of non-WHEA numbers and/or how it is performing in the real world. (underperform in anything other then AIDA64 latency bench?)

Look above in this very page..

Like if your _dual CCX cpu is_ running above 1933/3866 your read bandwidth numbers in aida should be above 60k otherwise there is something wrong/bad timings.
I'm getting 59.3k @ 1900:3800, above 60k @ 1933:3866 but lower real world performance and its only after prolong stresstesing the WHEA errors show up. The Tomb Raider 1080 medium cpu+memory bench picks it up straight anyway -> system is underperforming @ 1933/3866. And like i wrote, GPU means nothing here as we are looking at "CPU Game".

_OCCT is also very good to find errors that dont trip/show up in the windows WHEA log, its preferably to run the "power stresstest" as its both a cpu and gpu load to generate maximum heat for your memory, to simulate a real gaming session. Complete 1 hour avx and 1 hour sse without any errors and your system is at least good to go stability-wise in my book. (performance still unknown at this point )_

Other common problem is that your SOC is throttling/underperforming without you knowing it. (not giving any errors..) It could be related to wrong (too high and/or too low) voltages for VDDP, CCD or IOD etc ? (while memory is often running fine without problems) Or its simply could be clockstreeching. ? How would you know without testing it in something real ?

How much faster is DR with interleaving compared to SR ? At what clockspeed, or does it stay the same for the whole spectrum ?

How does Cmd1T compare to Cmd2T or Cmd"1.5T" with geardown mode in a real benchmark other than Aida ? (seems like t2 is the new thing in aida lately..)

Iam suggesting to use real world programs/benchmarks together with AIDA to tweak your systems.

_edit
Added some parts for clarity._


----------



## _frame_

20 cycles of TestMem5 pass. 2000 Mhz 1:1:1 
VDIMM 1.4 V
VSOC 1.1 V
No WHEA. I guess there is a room for lowering subtimings. Have not tried yet.


----------



## Joeking78

domdtxdissar said:


> My point is that some people are tweaking their memory purely for latency AIDA numbers, which dont always correlate to real world performance..
> How many sub "53ms" aida screenshots have i seen with lackbuster bandwidth, no proof of non-WHEA numbers or how it is performing in the real world. (underperform in anything other then AIDA64 latency bench?)
> 
> Look above in this very page..
> 
> Like if your running above 1933/3866 your read bandwidth numbers in aida should be above 60k otherwise there is something wrong/bad timings.
> I'm getting 59.3k @ 1900:3800, above 60k @ 1933:3866 but lower real world performance and its only after prolong stresstesing the WHEA errors show up. The Tomb Raider 1080 medium cpu+memory bench picks it up straight anyway -> system is underperforming @ 1933/3866. And like i wrote, GPU means nothing here as we are looking at "CPU Game".
> 
> Common problem is that your SOC is throttling/underperforming without you knowing it.. Could be related to wrong (too high and/or too low) voltages for VDDP, CCD or IOD etc ? (while memory is running fine) Or its simply clockstreeching. ? How would you know without testing it in something real ?
> 
> How much faster is DR with interleaving compared to SR ? At what clockspeed, or does it stay the same for the whole spectrum ?
> 
> How does Cmd1T compare to Cmd2T or Cmd"1.5T" with geardown mode in a real benchmark other than Aida ? (seems like t2 is the new thing in aida lately..)
> 
> Iam suggesting to use real world programs/benchmarks together with AIDA to tweak your systems.


Correct me if I'm wrong but the sub 60k aida results you mention are 5600/5800x results...you're using a 5950x which will improve bandwidth?

Only a few 5600x/5800x in the link below breach 60k



https://docs.google.com/spreadsheets/u/0/d/1dsu9K1Nt_7apHBdiy0MWVPcYjf6nOlr9CtkkfN78tSo/htmlview#


----------



## domdtxdissar

Joeking78 said:


> Correct me if I'm wrong but the sub 60k aida results you mention are 5600/5800x results...you're using a 5950x which will improve bandwidth?
> 
> Only a few 5600x/5800x in the link below breach 60k
> 
> 
> 
> https://docs.google.com/spreadsheets/u/0/d/1dsu9K1Nt_7apHBdiy0MWVPcYjf6nOlr9CtkkfN78tSo/htmlview#


Yes you are correct, single CCX maxes out @ 57.5k bandwidth read @ 1900/3800 speeds


----------



## Veii

JoneKone said:


> No do not listen to what this man says, He knows nothing about how to lap. One does not continuosly do a single move lapping, this is how hand bias is created and the surface will reflect that effect with single sided and lopsided geometry.
> 
> 
> 
> Here is a video about thermal interface materials AND Lapping.


"Single hand movement" ?
i dont move in one direction nor repeat the direction
Didn't write such stuff 🤔

I know what you mean but that's not how it ends up on my side
there are no single perspective lines, nor is it even a single directional move

Video = make a circle, turn 90° , make a circle
that is more prone to what you call "lopsided geometry"
Eh but on both parts it's similar

Not going to judge, everyone learned from somewhere else
But i certainly do not do "single directional" lapping. lol
I'd notice this on the end results with all the stripes and if it was that bad, i would be able see directional marks and don't get away with the material symmetrically to reveal the pressure pattern

Probably should share pictures or next time a video
As currently i'm being judged based on blind assumption 🧐


----------



## Veii

@domdtxdissar
The appearances are deceptive 
We don't "only" run Aida64 

Aida64 is maybe useful as a personal to personal comparison and is useful to show timings-efficiency , on 1 CCD units
If they can hit perfect half maximum memory speed

But for better comparisons some people here use SiSoftware Sandra, Multi-Core Efficiency Test (SiSandra MCE)
The detailed view shows a curve which illustrates memory effectiveness in processing specific dataset sizes 
That way you also can optimize chipset interleaving and optimize the powerplan to perform and boost this curve
(at the very end)

This forum is a "memory stability" thread, not only a memory performance benchmark thread
Tomb raider in their illustrational graph i find a bit deceiving
It shows over 30fps difference between 3600-3800 sets
But running that benchmark over with CapFrameX , does show far different FPS numbers - tiny to nearly non

I wonder where it gets up with these numbers
But you are right on the game benchmark part. 
The same thing you can see in SiSandra MCE on the curve , and is reflected in the games ~ you won't see in Aida numbers

We (i hope) ,all here know that it's a random latency oriented benchmark
On that and the remain parts, like L3 cache - we do focus (L2 scales with memory and IPC)
But it's nothing more than just a baseline for orientation
People who want to optimize for performance, do more than one specific test

Sadly the UI of SiSandra is really hard to get used to ~ but that's advanced finetuning
Advanced finetuning makes no sense to tap into ~ when you can't even reach a decent baseline (52 to sub 50ns)
Step by step 
Benchmarking games , wasting time there instead of slowly working on your baseline foundation
We are not even close to finetuning timing efficiency, nor to speak about game benchmarks
The Zen chart still shows a huge majority beyond 54ns 
When you move in near or sub 50ns, then you can finetune it with SiSandra and later test your results in games
Game benchmarks take such a long time and all these launchers are resource eaters ~ a waste of time for now,


----------



## ManniX-ITA

Veii said:


> "Single hand movement" ?
> i dont move in one direction nor repeat the direction
> Didn't write such stuff 🤔
> 
> I know what you mean but that's not how it ends up on my side
> there are no single perspective lines, nor is it even a single directional move
> 
> Video = make a circle, turn 90° , make a circle
> that is more prone to what you call "lopsided geometry"
> Eh but on both parts it's similar
> 
> Not going to judge, everyone learned from somewhere else
> But i certainly do not do "single directional" lapping. lol
> I'd notice this on the end results with all the stripes and if it was that bad, i would be able see directional marks and don't get away with the material symmetrically to reveal the pressure pattern
> 
> Probably should share pictures or next time a video
> As currently i'm being judged based on blind assumption 🧐


No you aren't being judged by anyone else than the smart guy... that clearly never lapped anything in his lifetime.
And just to add to the ridiculousness, it's pretty obvious that what he's referring to, "single move lapping", it's exactly what's been done in the video; it's your position and the object that's being changed.

I don't think I'd pleased to spend a few hours lapping AND walking around a barrel.
For sure much more comfortable to sit on a chair as always 
Not to mention that I wouldn't have any use or space where to fit such a big bin in my apartment...
Love this guy's videos, learned a lot about thermals for my TECs but he has a Lab.
Most of the stuff he's doing are out of reach of most and are more business oriented than for enthusiast. 

If you are willing to make a video about how you do lapping, please do, would be really interesting.
No judgments!


----------



## moshimoshi1

Issues with memory G.SKILL Aegis 16GB DDR4 3000MHz F4-3000C16D-16GISB
I have 4 sticks but I'm using just two of them
I just upgraded my old Ryzen 7 17000 with a new Ryzen 7 3700X
Motherboard is Asrock AB350M Pro4 with latest Bios 6.60
Can' t get the memory to work at 3000mhz enabling XMP, just at 2133mhz.
Have been trying DRAM Calculator, upping the vcore voltage and no luck.
Please help!


----------



## Not a redditor

Veii said:


> Half procODT - it's too high , only pushes minimum required voltage high
> 36.9 should run, but even 40 is way better than 60
> tRDWR 9, tWRRD 3
> 
> Lower is not always better on tRRD and tWTR
> better run tCWL = tCL and work your way on tRP down
> ^ also gives the ability to lower tRDWR which does help quite a bit
> 
> SCL you can probably go down later -1 and using tWRRD 4 , but you have to check
> This set looks scuffed ^^'
> If you're already going for low tertiaries and high tRDWR, go for tRAS 28, tRC 29
> EDIT 2:
> Dual Rank units need tWRRD delay, between 2-4
> 
> tRC 29 no go until 34
> tWRRD 4
> tRDWR 9 or 8 no go only 10 works, didnt try lower then 8


----------



## LuckyImperial

Well, I haven't been able to find any Asus settings in BIOS that look fishy, and I've disabled Performance Enhancement and FMax, which seem like Asus specific performance settings. 

I was able to verify that I run 1:1:1 up to 3600MHz DRAM Frequency. As soon as I set 3666MHz I start running 1:1:2 mCLK:fCLK:uCLK, 1833MHz:1800MHz:916.50MHz. 

Sooooo...right now I'm running 3600MHz CL16 at 1.4v, at least until I can find out how to force 1:1:1. XMP Enhancments-> mCLK===uCLK doesn't do anything unfortunately. 

If I can find the magic setting to force 1:1:1 I know that I can run these CL16 timings at 3800MT/s at 1.45v stable.


----------



## Veii

LuckyImperial said:


> Well, I haven't been able to find any Asus settings in BIOS that look fishy, and I've disabled Performance Enhancement and FMax, which seem like Asus specific performance settings.
> 
> I was able to verify that I run 1:1:1 up to 3600MHz DRAM Frequency. As soon as I set 3666MHz I start running 1:1:2 mCLK:fCLK:uCLK, 1833MHz:1800MHz:916.50MHz.
> 
> Sooooo...right now I'm running 3600MHz CL16 at 1.4v, at least until I can find out how to force 1:1:1. XMP Enhancments-> mCLK===uCLK doesn't do anything unfortunately.
> 
> If I can find the magic setting to force 1:1:1 I know that I can run these CL16 timings at 3800MT/s at 1.45v stable.


use the bios search optoin
search for 

FCLK
UCLK
Fabric

put all of them at the fixed frequency  
and disable armory crate
i know it's there
just search for it inside the bios


----------



## domdtxdissar

Veii said:


> Aida64 is maybe useful as a personal to personal comparison and is useful to show timings-efficiency , on 1 CCD units
> If they can hit perfect half maximum memory speed
> 
> But for better comparisons some people here use SiSoftware Sandra, Multi-Core Efficiency Test (SiSandra MCE)
> The detailed view shows a curve which illustrates memory effectiveness in processing specific dataset sizes
> That way you also can optimize chipset interleaving and optimize the powerplan to perform and boost this curve
> (at the very end)


That's exactly what i was saying in my last post.
"Iam suggesting to use real world programs/benchmarks *together* with AIDA to tweak your systems."


> This forum is a "memory stability" thread, not only a memory performance benchmark thread


Also agree, but lately it seems like this is the "aida64 latency" thread, and when i post some real life memory benchmarks they are called "useless".


> Tomb raider in their illustrational graph i find a bit deceiving
> It shows over 30fps difference between 3600-3800 sets
> But running that benchmark over with CapFrameX , does show far different FPS numbers - tiny to nearly non.
> I wonder where it gets up with these numbers


Not sure i agree, just need to look at the first 5 seconds of the benchmark to know if its a good run or not. But indeed there is alittle to much run to run variance for my liking.


> We (i hope) ,all here know that it's a random latency oriented benchmark
> On that and the remain parts, like L3 cache - we do focus (L2 scales with memory and IPC)
> But it's nothing more than just a baseline for orientation
> People who want to optimize for performance, do more than one specific test


This is at the heart of the matter I'm takling about, it seems to me that its mostly latency numbers people focus on while they neglect other important parts..











> Sadly the UI of SiSandra is really hard to get used to ~ but that's advanced finetuning
> Advanced finetuning makes no sense to tap into ~ when you can't even reach a decent baseline (52 to sub 50ns)
> Step by step


There is very very few dual CCX CPUs with 4x8gigs and/or 2x16gigs DR setups that will ever reach sub 52 ms while retaining any kind of stability/usability.. And when you have reached this point where the CPU/SOC simply wont go any higher fclock whatever settings you try , there is not much to do other then optimize for "real world" performance in games, if that's your primary use for your computer..

And for almost 80% of the people in this thread (guesstimate) i think their time is better spent overclocking their cpus with a static OC after they have activated XMP/copied a profile from dram calc, if its real world performance they are after...
Things like gaming, rendering, streaming etc which ppl actually use their computer for pretty much always scale better from pure CPU clockspeed than memory tuning beyond basic import from dram calc.


----------



## LuckyImperial

Veii said:


> use the bios search optoin
> search for
> 
> FCLK
> UCLK
> Fabric
> 
> put all of them at the fixed frequency
> and disable armory crate
> i know it's there
> just search for it inside the bios


I've never used the BIOS search tool before. Pretty cool.

fCLK yielded two values so I set them both to 1800MHz.
uCLK yielded the dividing value, so I set that to UCLK==MEMCLK
Fabric yielded Infinity Fabric Frequency and Dividers, so I set that to 1800MHz.
Crate yielded "Download & Install ARMOURY CRATE app", I set that to Disable.

After those changes I'm still at 1833MHz:1800MHz:916.5MHz if I try DRAM Freq 3666MHz 

EDIT: I've also enabled SoC/Uncore OC with no luck.


----------



## Veii

domdtxdissar said:


> There is very very few dual CCX CPUs with 4x8gigs and/or 2x16gigs DR setups that will ever reach sub 52 ms while retaining any kind of stability/usability.. And when you have reached this point where the CPU/SOC simply wont go any higher fclock whatever settings you try , there is not much to do other then optimize for "real world" performance in games, if that's your primary use for your computer..
> 
> And for almost 80% of the people in this thread (guesstimate) i think their time is better spent overclocking their cpus with a static OC after they have activated XMP/copied a profile from dram calc, if its real world performance they are after...
> Things like gaming, rendering, streaming etc which ppl actually use their computer for pretty much always scale better from pure CPU clockspeed than memory tuning beyond basic import from dram calc.


The problem is more on the bios side of things
we are still testing rabbits

One of the best bioses which allowed up to 2100FCLK (2167 as peak) wasn't even released for many boards and skipped (SMU 56.30 , ABL 09084010)
The update afterwards intentionally was hardlocked to 1900FCLK
It's a fight and a half ~ 2000FCLK before some scores where set and AMD being mocked about it
Where not even consider a real thing
And yet nealy everyone on these new bioses, suffers from the autocorrecting WHEA tracking nonsense
Back then it wasn't a thing at all. The system purely hardlocks or shutdowns if something is off, but doesn't try to autocorrect and make our lifes hard

We should be moving between 48-52ns , nearly all of us
While 4x8gb sticks can stay easily at 56ns or lower
It's just a combination of autocorrection, and we as alpha bios testing rabbits
Kind of a one sided fight without success, soo i can see your point on cpuOC

Cache bandwidth , to be clear inter-connect bandwidth doubled since 1.1.0.0 Patch D (ABL update)
before 1180/1190/1200 was "allowed" to be shared
AMD tries to change link speed and optimize for IPC improvements. I can clearly see that on single core benchmarks at the same frequency
But that takes maximum FCK soo far down. Then not forgetting broken memory training since Patch-C
It's annoying to say at least

Curve optimizer on it's own and PBO are still a mess
and variable FCLK / SOC , is still disabled and no one cares to answer or talk about it
probably has to do with dLDO load calibration , and also has to do with per-core C states
Honestly, they are optimizing the release while it's being already released.
So far everything positive including PCIe 4.0 stability goes at the expense of memoryOC capabilities, training and all nice broken bugs and current limits

Eh, i think aida64 on this generation shows far more than on Matisse
It very clearly shows if autocorrection happens , with a run-to-run deviation of 0.3ns (instead of being perfect or 0.1ns)
That's why we focus on this test, and run SiSandra MCE (some)
Aida64 and LatencyMonitor , are good tools to track cpu voltage autocorrection and package throttling

Vermeer is not all about FCLK
The most annoying work we have to do, is 5-10mV adjust voltages to stop package throttling and error correction (cpu side)
soo we run a lot of the cache tests
It very clearly shows if voltages are off, once latency differences become quite distant between us users
Bad voltages alone will cost you 3-4ns















Source





详解5800X（ZEN3）如何最高稳定你的FCLK！ - 电脑讨论 - Chiphell - 分享与交流用户体验


详解5800X（ZEN3）如何最高稳定你的FCLK！,说明：BIOS版本差异存在巨大，本贴所用BIOS版本为1.1.00，另外1.2.00准备上一新BIOS另一贴，请留意。 ZEN3经过一系列的优化和微调架构后其性能已超越同期的英特尔 ...,电脑讨论,讨论区-技术与经验的讨论 ,Chiphell - 分享与交流用户体验




www.chiphell.com






LuckyImperial said:


> I've never used the BIOS search tool before. Pretty cool.
> 
> fCLK yielded two values so I set them both to 1800MHz.
> uCLK yielded the dividing value, so I set that to UCLK==MEMCLK
> Fabric yielded Infinity Fabric Frequency and Dividers, so I set that to 1800MHz.
> Crate yielded "Download & Install ARMOURY CRATE app", I set that to Disable.
> 
> After those changes I'm still at 1833MHz:1800MHz:916.5MHz if I try DRAM Freq 3666MHz
> 
> EDIT: I've also enabled SoC/Uncore OC with no luck.


Nice that you found it
Yes i don't know
DL-Link search for 3402 (that one works, but has EDC limit issues and 1900FCLK, at least 3800MT/s works)

or be my testing rabbit and confirm SMU 56.33 is not identical to 56.34 (Patch-C)and has no 1900FCLK lock with 1900Mhz broken memory training
~ the bios i shared for you to try
as there is no Patch-B out there for this board either. checked 200 download links in order and nothing exists in their database


----------



## ManniX-ITA

LuckyImperial said:


> I've never used the BIOS search tool before. Pretty cool.
> 
> fCLK yielded two values so I set them both to 1800MHz.
> uCLK yielded the dividing value, so I set that to UCLK==MEMCLK
> Fabric yielded Infinity Fabric Frequency and Dividers, so I set that to 1800MHz.
> Crate yielded "Download & Install ARMOURY CRATE app", I set that to Disable.
> 
> After those changes I'm still at 1833MHz:1800MHz:916.5MHz if I try DRAM Freq 3666MHz
> 
> EDIT: I've also enabled SoC/Uncore OC with no luck.


The only other reason that could be is that memory training is failing.
The MSI Unify-X and GB Master are doing the same.
I'd try different CAD bus settings and/or timings, but it's usually more the CAD settings.
You may need some out of the ordinary settings, maybe your DIMMs does not play well together with the board.


----------



## dr.Rafi

Veii said:


> Oh ignore the cooler
> Or lap the cooler afterwards
> I started with 800 & 1200 grit, and still think to keep the same method
> Takes 2h per layer with water on an ∞ loop/hand movement
> 
> You press the cpu on the pins with 3 fingers/flat and listen to music
> It needs contineous 2h a layer at the same hand movement speed
> First top layer till you reach copper, then clean the sandpaper a bit with more water and continue till the paper is fully brown gold'ish
> Then you switch to 1200 grit and continue for 1-2 more hours
> 600 or 800 grit is just to remove the top silver layer
> The clamp side stamps will take the longest to remove and flatten out fully
> 
> I would not use LM on the silver metal layer, its ot a good idea and not very clean mixture
> Edit:
> * it needs to be done on a glas or smooth ceramic surface
> As every little cut, dent or spike will appear on the heatspreader
> Soo you want something as liquid smooth as possible for a surface


You can use the original cpu packaging cover the pins while lapping so no accendental pins damage simply cut the package and use only the side that cove the pins.


----------



## Manuru

Why do you guys think? Is latency OK for these timings?


----------



## DeletedMember558271

So has even a single person ever got 1900 FCLK to boot that hasn't been able to even though they could boot 1933+ just fine?
Or is it actually impossible for everyone with this issue so far?

I don't know how to get rid of 1933+ WHEA or if its even possible for my setup so I'm stuck at 1867 forever as it stands... but it seems like fixing 1933+ WHEAs would be more possible than booting 1900 since it seems like some people have actually done it, then again still impossible for many if not almost all.

B550 Tomahawk, 5800x, 4x8GB, PCIe 4.0 M.2 SSD & GPU


----------



## Dasa

1900IF boots for me but far less stable than 1933 with a heap more WHEA along with crackly stuttering audio and USB2 ports.


----------



## Merutsu

Here is my OC of dual rank b-die, 2x16GB G.Skill FlareX 







vdimm: 1.41v in bios, hwinfo reports 1.432v
vsoc: 1.0625v with llc mode4, because of vdroop it's ~1.050v
max ram temps with custom heatsinks are 43-44C even after hours of gaming.


----------



## Veii

Manuru said:


> Why do you guys think? Is latency OK for these timings?
> View attachment 2479683
> View attachment 2479684
> 
> View attachment 2479689
> View attachment 2479686


Try this








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Anyone with 4 DIMMS running a 5000 series at 3800 mhz/ 1900 FCLK? Right now I'm stable at 3733/1866 Cas14 just as I was with my old 3900x. I'm trying to get Cas 14 at 3800/1900. I tried adjusting some timings but did not have luck booting 3800/1900 1.50V at Cas 14. I have a Memory Cooler and...




www.overclock.net




and take away 150mV of your current VDIMM voltage
you run 5150 (hopefully all cores can hit that) 
Your latency result should be with them near 52.5-53ns 
later you can try how much you need to drop tRDWR -1 how you have it right now
Pretty much replicate the set , RTT; CAD_BUS , Setup Timings, tCKE


----------



## Yviena

I still can't no matter what i try get anything over 1900 FLCK to be WHEA free on 1.1.8.0 AGESA, there is a new 1.2.0.0 but people seem to say that 1.2.0.0/1.1.8.0 has worse boosting performance than 1.1.0.0

Though i think my 4X8SR b-die ram is capable of atleast 3866-4000mhz at CL16 when using 1.48v.


----------



## Veii

Yviena said:


> I still can't no matter what i try get anything over 1900 FLCK to be WHEA free on 1.1.8.0 AGESA, there is a new 1.2.0.0 but people seem to say that 1.2.0.0/1.1.8.0 has worse boosting performance than 1.1.0.0


Do you have 1.1.0.0 Patch B to use ?
SMU 56.30
if yes, stay on that one or find Patch D which is an updated 56.34 SMU (34 is Patch C and D)
56.30 allows you up to 2100 FCLK without 2:1 mode, 2167 is the peak but bugs out in 2:1 mode

1.1.8.0 was what many people had success with 2000FCLK
but it's still low
back then 2100 was possible 
Sadly AMD never released Patch-B for most of the boards
1080 is the earliest AGESA , Vermeer runs on
1180 is the earliest AGESA Cezanne/VanGoth/Lucien runs on


----------



## Yviena

Veii said:


> Do you have 1.1.0.0 Patch B to use ?
> SMU 56.30
> if yes, stay on that one or find Patch D which is an updated 56.34 SMU (34 is Patch C and D)
> 56.30 allows you up to 2100 FCLK without 2:1 mode, 2167 is the peak but bugs out in 2:1 mode
> 
> 1.1.8.0 was what many people had success with 2000FCLK
> but it's still low
> back then 2100 was possible
> Sadly AMD never released Patch-B for most of the boards
> 1080 is the earliest AGESA , Vermeer runs on
> 1180 is the earliest AGESA Cezanne/VanGoth/Lucien runs on


Hmm there is a 1.1.0.0 Patch C for my X570 tomahawk should i try that?

also i'm a bit confused is RTT 7/3/1, or 6/3/3 the correct one for 4xSR?


----------



## Spectre73

Is my observation correct, that GDM vs. 2T GDM decreases latency while improving memory read? 2T was consistently around 0,4ns faster...while read was aroun 500MB slower.


----------



## craxton

@Veii its been well, long enough now that ive been setting on "stable" timings,
and haven't seen any new configurations or information (could have missed the posts)
on 4x8 sets of single rank, im currently still running the same configuration that i last had








still setting around 52.1 52.2 depending on what services i can keep from starting up, even if theyre disabled.
if i can surpass 60k bandwith, well thats mainly what im after, even if i have to use only two sticks instead of 4.









if you have some suggestions, throw em at me. (ive also re-ran) all memory stress tests this week.
as well as switched to 1usmus config for TM5 as it was mentioned if errors come out whats the potential cause etc
ran tm5 at 100% 2 times then at 1000% on the third (i forget why 1000% is or isnt a good/bad thing?)

sisandra is very strange indeed, and my scores well, idk if there good or bad.
and for some reason i didnt save any screenshots nor do i know how/where i can find what results ive had
which seems irrelevant.

ive also became aware that my AIO orentation matter quite alot and have fixed it to the top of my case,
which now seems to pull 2x more air in the front, and the same for out the top (push config)

anyhow, im fine with not being stable, just wanting to play around some more, and soak all i can understand about RAM on ryzen.


----------



## VPII

T884G63 said:


> Wow 4x8 @1T with GDM off running @3800 in sync!
> 
> I just had to try your setting and first I ran with Veii's
> recommended CAD_BUS, Rtt, ProcODT, and voltage
> settings and was a no go.
> 
> Then tried your CAD_BUS, Rtt, and ProcODT with
> Veii's voltages and no go.
> 
> But copied your settings to a T and bam posted and
> Booted first go ***
> 
> Been trying to run 4x8 1T @3800+ on AMD coming
> from intel has been a nightmare.


HI man, thanks it is the memory and probably the cpu that can do it, I'm just lucky. But I hope you come right. When I ran 4 sticks of memory the first time it was a mission getting it to work, much more so at the speed I wanted.


----------



## Veii

Spectre73 said:


> Is my observation correct, that GDM vs. 2T GDM decreases latency while improving memory read? 2T was consistently around 0,4ns faster...while read was aroun 500MB slower.


I don't think so
At least from the logical side of things
GDM on is 2.5T
It was 1.5T on DDR3 , but we have one MUX each bank group (4 mux each) and one master MUX
Auto correction happens twice in the loop, well 2.5 times
It might not do it at the very main mux line and it wont be noticed expect of tWR, tRTP and tCL purely being refused as odd value
But i'm very sure at this point that all primaries are rounded upwards

Another observation is
GDM on, all of the MUX run at half speed 400mhz, instead 800
The overall strain to the memory is lower, and tRFC can be very low because of that
The powering requirement's are pretty much masked with GDM on, ans very well shown if you go for 2T

It makes from many parts on the technical side of things, no sense why it should be faster
I've tested it and my results show 0.4-0.5ns improvement on GDM off
It also shows again very clearly if DIMMs are powered wrongly 
But aside from my results with a big difference and another users test that showed no difference
I think on both cases, your dimms where not powered well enough
That is CAD_BUS and RTT setting's place and thing to manage 
------
@craxton there is something work in progress
Trying very hard to stabilize 14-8-14-12-26-38 (120ns) on 4x A2
I can see that 6/3/3 is not perfect but 14-8-15-13-26-39 (120ns) is only possible with 3-3-15 @ 36ohm @ 40-20-20-20 tCKE 9

tCKE 9,16,24 all work with 60-20-40-20 - also 40-20-30-20 @ 6/3/3 (Setup time 0-0-0)
But the powerdown timings from RTT dont align well on 4 dimm boards
Data-Eye starts to be problematic at @ 1.56v. Many Error 6s

I have a feeling that like written above, it's fantastic for 2 dimm boards but CKE high overshoots and reverse back
It hardlocks between full cycles and on the idle state once CKE raises
Soo that needs a bit more work before i can share proof of concept results for 4x A2 2T
140ns works but i want to get 120ns at 14-14 to run  
Currently it times out and the high voltage doesnt play well with this RTT values

Will update once we have usable results
6/3/3 if used correctly with tCKE works well for voltages between 1.35-1.51v
Higher than 1.54 makes issues , and flat C14 without GDM still makes issues
On 2 dimm boards it's top for dual rank, on 4 dimm boards, it needs a subtle change


----------



## VPII

ManniX-ITA said:


> OCCT is using HWInfo now to monitor; if you run both in parallel the readings will be slightly messed up as they have to fight to access the same driver.
> 
> The temps seems in check; if the average temp running OCCT is 65-75c it's normal. You need something very special to cool it better than that.
> 
> DIMMs temp are nothing to worry about at 44c.
> I'm running at 1.54v and they tops 53-54c after 1h TM5 without any issue.
> I have a single 140mm fan blowing down at 1100rpm.
> 
> The latency seems to be way too high....
> The power plan, background running programs, anything can influence it.
> You need to test 10-15 times till it gets flat to be sure is right.
> And definitely test it before opening HWInfo or any other bench/monitoring software like OCCT, CPU-Z, GB...
> 
> What you should fix:
> 
> tRC 48
> tRFC multiple of 16
> 
> Try:
> 
> tCKE to 1 unless 24 is really needed
> tCWL 14
> ProcODT to 37
> Higher VDIMM, 1.47v it's a sweet spot and reduce tRFC, bring SCL down to 2/3 (may need different tRDWR,tWRRD, I use for DR 10/1 for SCL 2)
> Higher VSOC at 1.15v and higher CCD/IOD 1000/1060; better scores


HI @ManniX-ITA so I tried your settings but found the following:

tCKE for this I've ran tests and 24 gives me way better latency than 1, as in 2 to 3ns better, you see the screenshot done while closing everything I could before running.
tCWL 14 is a no go, system does not even start up.
ProcODT I changed
Vdimm no difference so I am back at 1.4v for now
Same with CCD and IOD voltage
TRFC, I tried going lower but it would not work or fail during Aida64 and going higher meant higher latency.... I do have to try it again as in 16 x 18 as in 288 for TRFC. As for the other two TRFC is seems TRFC 2 and 4 appears to be TRFC 2 = TRFC x 0.73 and TRFC 4 = TRFC x 0.45 or 0.46.... but I stand to be corrected on this.


----------



## Karagra

Hey guys I tested vsoc 1.125v dram 1.45v vddp 0.950 and vddg 1.050. Is there any timings you guys think I could tighten? I havn't tested lower voltage yet probably will again over night.. Also you guys think its worth upgrading to a 5800x? Are they all guaranteed 1900fclk+?


----------



## Br3ach

Karagra said:


> Hey guys I tested vsoc 1.125v dram 1.45v vddp 0.950 and vddg 1.050. Is there any timings you guys think I could tighten? I havn't tested lower voltage yet probably will again over night.. Also you guys think its worth upgrading to a 5800x? Are they all guaranteed 1900fclk+?


At 1.45-1.50 VDIMM you should be able to make tCL14. If you, do you may need to bump ClkDrvStr to 40 Ohms for stability. tRFC can probably go lower (130-140 ns), tRTP can do 6 and tWR 10, best benchmark.


----------



## Karagra

Br3ach said:


> At 1.45-1.50 VDIMM you should be able to make tCL14. If you, do you may need to bump ClkDrvStr to 40 Ohms for stability. tRFC can probably go lower (130-140 ns), tRTP can do 6 and tWR 10, best benchmark.


Yeah I tried up to 1.47v was a bit unstable then 1.5v let me boot check aida and run a cinebench.. only .4 less latency and cinebench scores 7560 and the first hits 7460 in cinebench not sure if going from 1.45v to 1.5v is worth that difference?


----------



## _frame_

I have F4-3200C14-16GTZ kit and I've got F4-3200C14-16GTZ*N *to test. GTZ was made on Nov 2018, GTZN was made on Jan 2021.
Funny thing, Thaiphoon Burner shows exactly the same info on both kits. I do not think GTZN is A1 revision, for sure it is newer.
Also ZenTimings 1.2.2 shows same name for both kits: GTZ. Weird.
So, GTZ as I posted before was stable (20 cycles TM5) at 1:1:1 2000 Mhz 16-17-16-32 1T at 1.4v.
I insert NEO sticks and with the same setting TM5 give me errors. 1.45v the same and 1.5v the same! I changed CR to 2T and magically it became stable at 1.45v. Also tRCDRD =16 is fine for this sticks (my GTZ stable only at 17). And I've tried tCL = 15, it works with 1.5v but not stable.
Findings: Old b.die is not bad  Newer does not always mean better.
PS. I did not try 4x8 config.


----------



## ManniX-ITA

VPII said:


> HI @ManniX-ITA so I tried your settings but found the following:
> 
> tCKE for this I've ran tests and 24 gives me way better latency than 1, as in 2 to 3ns better, you see the screenshot done while closing everything I could before running.
> tCWL 14 is a no go, system does not even start up.
> ProcODT I changed
> Vdimm no difference so I am back at 1.4v for now
> Same with CCD and IOD voltage
> TRFC, I tried going lower but it would not work or fail during Aida64 and going higher meant higher latency.... I do have to try it again as in 16 x 18 as in 288 for TRFC. As for the other two TRFC is seems TRFC 2 and 4 appears to be TRFC 2 = TRFC x 0.73 and TRFC 4 = TRFC x 0.45 or 0.46.... but I stand to be corrected on this.
> View attachment 2479752


Never tested too much tCKE but I'm sure it doesn't change nothing for me about latency.
According to @Veii it should be used with specific CAD settings and yours are not.
Maybe it's a sign something is off but I can't tell what.
With your settings the latency should be at least 1-3 ns less.


----------



## VPII

ManniX-ITA said:


> Never tested too much tCKE but I'm sure it doesn't change nothing for me about latency.
> According to @Veii it should be used with specific CAD settings and yours are not.
> Maybe it's a sign something is off but I can't tell what.
> With your settings the latency should be at least 1-3 ns less.


Yes I know it should be, but I cannot seem to get the right settings.


----------



## Yviena

Does anyone know what's the recommended max voltage daily for B-DIE, is it 1.5v?
1.5v on ram has removed the WHEA errors i get at 1933FCLK, i do have active cooling on them though.


----------



## ManniX-ITA

Yviena said:


> Does anyone know what's the recommended max voltage daily for B-DIE, is it 1.5v?
> 1.5v on ram has removed the WHEA errors i get at 1933FCLK, i do have active cooling on them though.


You just need to keep them cool enough to not error after 1h30m of TM5.
I'm running 1.54V daily with just one 140mm on top of the case blowing down, tops 53c degrees.


----------



## craxton

_frame_ said:


> I have F4-3200C14-16GTZ kit and I've got F4-3200C14-16GTZ*N *to test. GTZ was made on Nov 2018, GTZN was made on Jan 2021.
> Funny thing, Thaiphoon Burner shows exactly the same info on both kits. I do not think GTZN is A1 revision, for sure it is newer.
> Also ZenTimings 1.2.2 shows same name for both kits: GTZ. Weird.
> So, GTZ as I posted before was stable (20 cycles TM5) at 1:1:1 2000 Mhz 16-17-16-32 1T at 1.4v.
> I insert NEO sticks and with the same setting TM5 give me errors. 1.45v the same and 1.5v the same! I changed CR to 2T and magically it became stable at 1.45v. Also tRCDRD =16 is fine for this sticks (my GTZ stable only at 17). And I've tried tCL = 15, it works with 1.5v but not stable.
> Findings: Old b.die is not bad  Newer does not always mean better.
> PS. I did not try 4x8 config.


(edit due to spoilers not working, or the user created their own error, as i probably dont know what im doing with those it seems...)

i dont have the kits you have, but i do have 2 kits of dark pro from team 3200c14. one kit is

Module Manufacturing Date: Week 43, 2020
Manufacturing Date Decoded: October 19-23, 2020

while the other is 

Module Manufacturing Date: Week 12, 2020
Manufacturing Date Decoded: March 16-20, 2020

both kits the same, yet entirely different.... timings show quite a few big BAD changed not listed
anywhere.
week 43 (october kit) which was bought first two months ago.


Active to Active/Refresh Delay Time (tRC):45TN/AFour Activate Window Delay Time (tFAW):34TN/AShort Activate to Activate Delay Time (tRRD_S):6TN/ALong Activate to Activate Delay Time (tRRD_L):7TN/A

week 12 (march kit) which was bought about 2 weeks ago


Active to Active/Refresh Delay Time (tRC):97TN/AFour Activate Window Delay Time (tFAW):48TN/AShort Activate to Activate Delay Time (tRRD_S):12TN/ALong Activate to Activate Delay Time (tRRD_L):12TN/A

tRC, tFAW, tRRD_S, tRRD_L all 4 have changed. again, same exact kits just purchased at different times. (older kit was off amazon, newer (later purchased kit aka the lesser sticks? newegg)
i manged to get stablity tho with quite a bit of help from the fellas here. at 1.45V c16 flat T2 my timings are posted quite alot and havent changed
so ill leave out the photos for now.
So, i could not agree more that newer/updated isnt always better


----------



## Yviena

Interesting AGESA 1.2.0.0 seems to be more stable at 2000FCLK opening browser, and going to a video doesn't trigger WHEA errors each second so i think stability wise it's better, maybe i can actually get it WHEA stable in TM5 this time.


----------



## craxton

Trusconi85 said:


> My best score...maybe Veii can suggest something to improve
> 1T does not work even at 1.4v
> i try also this parameter but @4000
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Opposite. The cooler pressures in the center only. AUROS retweet back then about LGA and PGA But the actual illustration fits The center and the sides where bent higher when they where send to the factory The heat and pressure clamps then went strongly into the layers The center was pushed...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> but won't boot


if this is 4x8 sticks, use CAD_bus timings 4,4,18 or try at least. 
(EDIT- quickly raised soc, vdimm back up. Vdim to 1.47 llc3 and soc back 1.21and iod back to 1060 lol, the first run of that was fine, but the last 5 with more tasks killed etc showed something was way off. It turned out to be all 3 voltages.

i have since lowered vdimm voltage to 1.45, and SOC to 1.12v and lowered iod to 1030mv. 
these are presumably WHEA free as no errors come around inside event viewer inside kernel-whea folder
nor are there any showing in HWinfo. there is a few pages back mentioned about running 4 sticks and what cad_bus timings to use
i cant recall the page, and its more than two by now. but the cad_bus timings may help you post.

i just know this is what was mentioned for 4x8 single rank sticks (and sometimes i think 2sticks of dual rank)


----------



## Phynicle

Does my latency seem high to anyone else given my timings?


----------



## VPII

Phynicle said:


> Does my latency seem high to anyone else given my timings?
> 
> View attachment 2479862


Yes, I sit with the same issue as my latency is higher than what it should be.


----------



## dr.Rafi

Phynicle said:


> Does my latency seem high to anyone else given my timings?
> 
> View attachment 2479862


Should be between 54,1 and 55, you can try to close all running background applications and double click on memory latency,it will refresh the test ,try it many times ,the actual reading should be repeating itself many times.
and lossing the primaries can give better perfomace like 15 15 15 15, also trfc you can try 262 instead of 288, trdrdsd/dd on 5 5 is faster than 4 4 and twrwrsd/dd faster to use 7 7.


----------



## Joeking78

Phynicle said:


> Does my latency seem high to anyone else given my timings?
> 
> View attachment 2479862


Maybe you have a lot of background apps running?

You could try again in safe mode or regular Windows and kill apps like virus programs, rgb software, etc and stop some services 

If I run aida with regular windows my latency is around 55ns, with a tweaked OS its around 53ns


----------



## Phynicle

Joeking78 said:


> Maybe you have a lot of background apps running?
> 
> You could try again in safe mode or regular Windows and kill apps like virus programs, rgb software, etc and stop some services
> 
> If I run aida with regular windows my latency is around 55ns, with a tweaked OS its around 53ns


It's literally a fresh install, it only just has benchmark apps and antivirus


----------



## _frame_

dr.Rafi said:


> trdrdsd/dd on 5 5 is faster than 4 4 and twrwrsd/dd faster to use 7 7.


Always? With any combinations of timings?


Phynicle said:


> antivirus


this


----------



## _frame_

dr.Rafi said:


> Should be between 54,1 and 55


With 2x8 gb I have 54.7 with 1900 Mhz and 16-16-16-16-32 2T
32 gb Cl 14 1T could be lower I guess


----------



## Phynicle

_frame_ said:


> Always? With any combinations of timings?
> 
> this


Really antivirus.... 

Right let me give that a try


----------



## gwolf2u

for some reason I can't seem to be able to boot with XMP set to 3600 on any F30+ BIOS with 5900X no PBO or anything
RAM KIT is VENGEANCE LED 32GB (4 x 8GB) 3600MHz C18 - CMU32GX4M4C3600C18 (link) paired with GB X570 AORUS ELITE and used to run fine for a month or so until I started getting WHEA error and soft reboot from Windows
updated to newer F31, F32 and now F33c
seems that now it just fails to memory train and reverts back to stock 2133 MHz for RAM even if XMP profile is selected
beeps 3 times, restarts, beeps 3 times again, restarts, beeps once and reverted to stock settings
anyway, managed to downclock to 3400 with 16-17-17-38 timings and that seems fine for now, but getting those 3 beeps at start anyway (even if I tried to disable CMS)
seems to happen only after a long shutdown period (12h+) and starting cold

not sure what am missing here to be honest


----------



## craxton

Phynicle said:


> Really antivirus....
> 
> Right let me give that a try


when you have a fresh install, you have **** like XBOX services running, windows update services running
and all that other **** that dont need to be running...

close or force kill those services, and do as one other stated and kill your antivirus by turning it off when 
running aida.

HWinfo can alter latency just a bit too, you should have 1-0% cpu usage and if 32gb of ram like 6-7% usage total....
before running aida benchmark...


----------



## KedarWolf

craxton said:


> when you have a fresh install, you have **** like XBOX services running, windows update services running
> and all that other **** that dont need to be running...
> 
> close or force kill those services, and do as one other stated and kill your antivirus by turning it off when
> running aida.
> 
> HWinfo can alter latency just a bit too, you should have 1-0% cpu usage and if 32gb of ram like 6-7% usage total....
> before running aida benchmark...


Added Win10ISO only links, Benching O/S only and a file with everything in it.

Link to stripped benching O/S. Testing as working today. Windows install ISO you need to set up with Autoruns and an already set up preconfigured Macrium image, no Autoruns, nothing needed, install the image, run Benchmate, select benchmark. Macrium Free, RUFUS and Autoruns included. Tested as working with no sound, no printing, all unneeded services disabled etc. Has Internet access though.

*Read the InstructionsREADME!!!!!.txt included in the zip!!*

Oh, and if you need to install MSI Afterburner and I think I might have missed video card drivers, Run the included Autoruns64.exe as Admin, uncheck all the Hide options in Options, go to Services, enable TrustedInstaller, reboot, install Afterburner and/or your GPU drivers.






Benching - Google Drive







drive.google.com





Attachment is what is stripped from Windows.


----------



## domdtxdissar

KedarWolf said:


> Added Win10ISO only links, Benching O/S only and a file with everything in it.
> 
> Link to stripped benching O/S. Testing as working today. Windows install ISO you need to set up with Autoruns and an already set up preconfigured Macrium image, no Autoruns, nothing needed, install the image, run Benchmate, select benchmark. Macrium Free, RUFUS and Autoruns included. Tested as working with no sound, no printing, all unneeded services disabled etc. Has Internet access though.
> 
> *Read the InstructionsREADME!!!!!.txt included in the zip!!*
> 
> Oh, and if you need to install MSI Afterburner and I think I might have missed video card drivers, Run the included Autoruns64.exe as Admin, uncheck all the Hide options in Options, go to Services, enable TrustedInstaller, reboot, install Afterburner and/or your GPU drivers.
> 
> 
> 
> 
> 
> 
> Benching - Google Drive
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> 
> Attachment is what is stripped from Windows.


Sorry for being a total newb, but is it possible to install this benchOS on a USB stick ?


----------



## Dasa

Phynicle said:


> Does my latency seem high to anyone else given my timings?


Also see if you can disable GDM even if you need to run 2T.


----------



## KedarWolf

domdtxdissar said:


> Sorry for being a total newb, but is it possible to install this benchOS on a USB stick ?


I don't think you can with the Macrium Reflect image but with the Win10ISO I think you can if you use Windows To Go with the included RUFUS like below.

Read the included ReadMe what you need to do to finish setting it up for benching though.


----------



## dr.Rafi

_frame_ said:


> Always? With any combinations of timings?
> 
> this


I am not expert in memory, but that what I usually notice, I think it is not hard to give it try


----------



## dr.Rafi

_frame_ said:


> With 2x8 gb I have 54.7 with 1900 Mhz and 16-16-16-16-32 2T
> 32 gb Cl 14 1T could be lower I guess


Cl14 @ 1900/3800 is over stressing some 5000 series fclk and make it slow down especially with dualrank memory, you have to try loosing primeries, secondries and tertiary timing to get more performance sometimes or use tighter timing but with lower fclk. especially if you not expert in memory timing calculations, I personally noticed using 15 15 15 15 28 37 and then only adjust tfaw to 16 , trfc to 262 , scl's to 4 and trdrd, twrwr to 5 5, 7 7 and leave the rest to auto, only start tweaking Vsoc, vddg's and vddp, one each time and test to find the sweet spot for that voltage reducing voltage can give better performance so not using higher mean better always, and get me better performance than copy many other expert timing setting with super tight timing or using cl14.


----------



## FleischmannTV

Lord @Veii 

Thanks to your observation I've tried GDM off 2T and have observed performance improvements as well. Even with more relaxed timings 2T is still faster. Latency has dropped consistently by 0.3 ns.


----------



## Sleepycat

Phynicle said:


> Does my latency seem high to anyone else given my timings?
> 
> View attachment 2479862


Your tRFC values don't match your RAM frequency, tCL and tRC. It should be tRFC (224), tRFC2 (166) and tRFC4 (102). Try to see if this boots for you, but tighter tRFC can also help reduce the latency slightly.


----------



## Sleepycat

Karagra said:


> Hey guys I tested vsoc 1.125v dram 1.45v vddp 0.950 and vddg 1.050. Is there any timings you guys think I could tighten? I havn't tested lower voltage yet probably will again over night.. Also you guys think its worth upgrading to a 5800x? Are they all guaranteed 1900fclk+?
> View attachment 2479756


Plug in your current RAM settings into this form and it will tell you the right tRFC to use: tRFC Calculator (mini)


----------



## Sleepycat

gwolf2u said:


> for some reason I can't seem to be able to boot with XMP set to 3600 on any F30+ BIOS with 5900X no PBO or anything
> RAM KIT is VENGEANCE LED 32GB (4 x 8GB) 3600MHz C18 - CMU32GX4M4C3600C18 (link) paired with GB X570 AORUS ELITE and used to run fine for a month or so until I started getting WHEA error and soft reboot from Windows
> updated to newer F31, F32 and now F33c
> seems that now it just fails to memory train and reverts back to stock 2133 MHz for RAM even if XMP profile is selected
> beeps 3 times, restarts, beeps 3 times again, restarts, beeps once and reverted to stock settings
> anyway, managed to downclock to 3400 with 16-17-17-38 timings and that seems fine for now, but getting those 3 beeps at start anyway (even if I tried to disable CMS)
> seems to happen only after a long shutdown period (12h+) and starting cold
> 
> not sure what am missing here to be honest


I keep seeing issues with Corsair's kits. Not sure how they are performing their binning, but I am seeing more and more Corsair kits not being able to run at XMP/DOCP. If you could run a single stick, see if it is able to run XMP/DOCP. If it still doesn't, then you need to test with a different brand of memory to isolate the cause to the Corsair Vengeance.


----------



## Phynicle

Sleepycat said:


> Your tRFC values don't match your RAM frequency, tCL and tRC. It should be tRFC (224), tRFC2 (166) and tRFC4 (102). Try to see if this boots for you, but tighter tRFC can also help reduce the latency slightly.


Damn didn't work, and had to clear bios otherwise wouldn't start. 
Some settings for whatever reason I change a Lil bit and I have to clear bios. I'm thinking is my mobo b550 unify x


----------



## dr.Rafi

Sleepycat said:


> Your tRFC values don't match your RAM frequency, tCL and tRC. It should be tRFC (224), tRFC2 (166) and tRFC4 (102). Try to see if this boots for you, but tighter tRFC can also help reduce the latency slightly.


Trfc 224 need 1.53 vdimm or over to boot.


----------



## dr.Rafi

Phynicle said:


> Damn didn't work, and had to clear bios otherwise wouldn't start.
> Some settings for whatever reason I change a Lil bit and I have to clear bios. I'm thinking is my mobo b550 unify x


As I explained to you extreme setting and you run in more issues, those setting iam using tested with 3 different ram kits all working fine, PBO and CO off.


----------



## domdtxdissar

Anyone have any ideas what i should change ?








Cant find a explanation for error 15..


----------



## mirzet1976

domdtxdissar said:


> Anyone have any ideas what i should change ?
> View attachment 2480005
> 
> Cant find a explanation for error 15..
> View attachment 2480006


By Error15 see Error 3


----------



## Veii

domdtxdissar said:


> Anyone have any ideas what i should change ?
> View attachment 2480005
> 
> Cant find a explanation for error 15..
> View attachment 2480006


Ryzen Google Calculator DATA Sheet

I need to update it further, couple of errors now make more sense and can be pinpointed better
For your set, tWRRD is missing ~ either 2x16 or 4x8 , this goes through as dual rank, with the only difference it having different RTT values for 4 dimm boards , while 6/3/3 works for 2 dimms better

The error belongs to the "mirror move" category
In this case it's 128mb mirror move, which is dimm to dimm ~ but i am not in clear if it's Bank Group to Bankgroup or it stays in the 2 dimm "chain" (without going to the slave kit)
Neverless - your issue is a mirroring timeout
It's either tRFC or tRDWR/tWRRD. tWRRD in your case
use tWRRD 4 here

For your specific issue, Dark Hero, 4 dimms, tRCD 15 (very likely)
Swap to 6/3/3 RTT (with a maximum allowed voltage of <1.54vDIMM)
But before resorting to that - first try increasing tRRD to 4-5-16, tWTR 4-10 
Please report back ~ there should be soon something nice done for Dark Hero users


----------



## Veii

2nd post to separate this, as it's critical ⚠
Do NOT use CTR 2.0 RC3 public (RC1 is free from this dangerous bug)
I requested personal assistance to clear it up with 1usmus & fix it
(tracked the 8ghz+ boost issue down and perm loss of boost frequency)
~ but till he responds or wants to respond to the report, i strongly suggest anyone not to run TUNE on this version

The bug belongs to this kind of issue


Spoiler























I don't want to de-fame him, as bugs happen (till he fixes that successfully)
~ but the telemetry fix that was submitted triggers a stack of bugs

Anyone who experiences this boosting spikes above or loss of frequency on PBO OC (200+ mhz)
Has run into this bug ~ which is permanently sealed into the CPU now (no agesa change can fix this)
It does affect the whole lineup with 2 CCX/CCDs. (meaning also christmas 5600/5800X units)

I don't think it's permanently F*_, but till he in person pushes a fix, it is permanently f*_
Spend the last days working on it, and there is no way to fix it as it sitts in the tiny ARM chip inside the CPU

EDIT
Example of the bug on me was a broken Core 0 , as Core-Map layout bugged out
RC1 did not have the bug and it's not core-stretching, as i'm tracking that one down very slowly
"Telemetry Fix" was also submitted to AMD for AGESA 1.2.0.0 as SMU 56.45
It's majorly broken, soo i hope AMD took a short look on it before accepting his submission


Spoiler






















EDIT 2:
I could talk with 1usmus, and the bug belongs to a low powerstate which interferes while P2 and P1 where active under hybrid OC
Explaining results like this:


Spoiler














For me the issue was more sever, as it happened on a core-map layout remap
From his perspective, every change CTR does ~ runs "in software" and has no bios access
About this part we have to see, as my first core was permanently bugged

But the resolve has to be:

uninstall chipset drivers & reboot
get new CTR releasing on 25/02/2021
run diagnosis, let it finish ~ maybe put in P2 and P1 , then disable them
clean exit CTR
this has to fix the "overboosting" issues and potentially overvoltage issues
(CTR should not be run with any vcore , manual or offset bug out equal)

About my "bad" bugged core
Chipset drivers did not fix it ~ but as the change was "temporary" strangely big AGESA jumps did not help
His interaction with Mode Registers, should hopefully be fixed by now
Soo anyone who had that "permanent" boosting bug from RC3 , run the newest one (2.1Beta6 or 2.0 related)

At the end, i'm happy he acknowledged it ~ although "thousands of people have tested it"
which makes me sad that no one even noticed such severe issue
Anywho, acklowledged ~ hopefully fully fixed and hopefully fully forgotten


----------



## Br3ach

Hello, I've recently joined the mem overclocking OCD club. Spent last week tweaking and memtesting... Keeping silent so far, as still reading and learning. Three questions and one comment:

1) Question 1: Is there any sure technique to calculate optimal Rtt values? I see Veii recommends 6/3/3 for 4 DIMMs (SR or DR?). I'm also running 7/3/1 on 4xSR now. Or is it just trial and error?
2) Question 2: Seems tCWL/tRDWR/tWRRD are all linked - either 14/8/3 or 10/11/1, etc. is there such a thing as optimal combination? Or should I benchmark?
2) Question 3: I managed to stabilize 4xSR DIMMs 3800 MT/sec, 1T, GDM off with ClkDrvStr 120 Ohms, would different Rtts help reduce ClkDrvStr to 60 or lower?
4) Comment: ProcODT for stability, sharing my observations while trying to stabilise tRTP 5:


At 28.2 Ohms, I was getting an Error 11 in TMT 1usmus_v3. Didn't see it mentioned in the description of the error, so I want to point it out as one of the possible reasons.
30, 32, 34.3 Ohms would pass TM5 (quick 3x 1usmus_v3) without any issue, but would error out in Karhu (the lower, the quicker). That's perhaps a good (but slow) way to find the ProcODT sweetspot for a specific config too. E.g.

tRTP = 5, tWR = 10, tRAS = 28, tRC = 40, tRFC = 240

ProcODT 30, fail at 7%
ProcODT 32, fail at ca 150%
ProcODT 34.3, fail at ca 450%
ProcODT 36.9, fail at 9.100%, also caught very quickly by anta777 extreme (Test 4)
ProcODT 40.0, same, single errors with anta777, test 4
ProcODT >= 43, I getting blue screens with anta777 test 4.

So, I guess sweetspot ProcODT for me is around 40.


----------



## domdtxdissar

mirzet1976 said:


> By Error15 see Error 3





Veii said:


> Ryzen Google Calculator DATA Sheet
> 
> I need to update it further, couple of errors now make more sense and can be pinpointed better
> For your set, tWRRD is missing ~ either 2x16 or 4x8 , this goes through as dual rank, with the only difference it having different RTT values for 4 dimm boards , while 6/3/3 works for 2 dimms better
> 
> The error belongs to the "mirror move" category
> In this case it's 128mb mirror move, which is dimm to dimm ~ but i am not in clear if it's Bank Group to Bankgroup or it stays in the 2 dimm "chain" (without going to the slave kit)
> Neverless - your issue is a mirroring timeout
> It's either tRFC or tRDWR/tWRRD. tWRRD in your case
> use tWRRD 4 here
> 
> For your specific issue, Dark Hero, 4 dimms, tRCD 15 (very likely)
> Swap to 6/3/3 RTT (with a maximum allowed voltage of <1.54vDIMM)
> But before resorting to that - first try increasing tRRD to 4-5-16, tWTR 4-10
> Please report back ~ there should be soon something nice done for Dark Hero users


Thanks for your responses
I managed to resolve the problem by setting the correct tRFC-1/2/3 values for tRC 34 @ tCL14 
Could also lower vdim to 1.536-1.544 volt.
Running 4x8gigs on the normal crosshair viii hero.


My new 24/7 settings with fans on auto, bloatware windows and normal 22 degrees ambient.
















My current PBO CO settings are tweaked for singlethread performance.

Also: Bios 3003 is a few NS faster than my current bios 3204.
The only reason i use bios 3204 is because its needed for Nvidia SAM, whenever they finally decide to release the driver.


----------



## Alemancio

Is it me or how come *there are virtually no 2x16GB Samsung B-Die kits for sale*, for months. Anybody know why or got any link I can grab?


----------



## tefla

Alemancio said:


> Is it me or how come *there are virtually no 2x16GB Samsung B-Die kits for sale*, for months. Anybody know why or got any link I can grab?


Those kits were fewer in number to begin with. I went through the struggle of finding a decently binned 2x16 kit in the past few weeks and ended up settling for a 3600 cl16 G-Skill neo kit (F4-3600C16D-32GTZN). I basically ran through every single 2x16 b-die kit that was documented on hardwareluxx and there are very, very few that you can get readily without an obscene markup from major retailers like Newegg or Amazon. I'd honestly suggest monitoring Ebay and setup some restock alerts for the SKUs you're particularly interested in. Keeping in mind that some of these kits may never get restocked at this point.


----------



## Alemancio

tefla said:


> Those kits were fewer in number to begin with. I went through the struggle of finding a decently binned 2x16 kit in the past few weeks and ended up settling for a 3600 cl16 G-Skill neo kit (F4-3600C16D-32GTZN). I basically ran through every single 2x16 b-die kit that was documented on hardwareluxx and there are very, very few that you can get readily without an obscene markup from major retailers like Newegg or Amazon. I'd honestly suggest monitoring Ebay and setup some restock alerts for the SKUs you're particularly interested in. Keeping in mind that some of these kits may never get restocked at this point.


Yeah I've tried the same, googled over 30 kits, all OOS. There is a 4000Mhz 2x16GB but not AMD QVL'd for about $350, too much IMHO.

What were your results with the GSkills?


----------



## Serchio

Since we started talking about 2x16GB B-Die, which set would you recommend? Prices are horrible of course...

F4-3600C16D-32GTZN
F4-3600C14D-32GVK
F4-4000C16D-32GTZR
F4-4266C17D-32GVKB


----------



## tefla

Alemancio said:


> Yeah I've tried the same, googled over 30 kits, all OOS. There is a 4000Mhz 2x16GB but not AMD QVL'd for about $350, too much IMHO.
> 
> What were your results with the GSkills?



















1.52v (I could do it on less, but i wanted to find my max thermally stable voltage for further tightening.) I think there's a fair bit of headroom, but I simply haven't had time to tinker more. This is rock solid, 10+ hours karhu, 25+ cycles TM5 1usmus config, etc. 

I've been spending some time reading this thread since there's so much amazing information from people like @Veii but it's difficult gathering it across 309 pages. TBH I'd love some suggestions on where to start for improving these timings. 😅

I think I will go GDM off, 2T and continue tightening from there (since i saw that suggested earlier). Beyond that though, I'm not sure. Most seem to be running 2x8 single rank, not 2x16.


----------



## BarrettDotFifty

Serchio said:


> F4-3600C16D-32GTZN


That's what I'd go for and tweak it myself to my liking.


----------



## Veii

tefla said:


> View attachment 2480054
> View attachment 2480053
> 
> 
> 1.52v (I could do it on less, but i wanted to find my max thermally stable voltage for further tightening.) I think there's a fair bit of headroom, but I simply haven't had time to tinker more. This is rock solid, 10+ hours karhu, 25+ cycles TM5 1usmus config, etc.
> 
> I've been spending some time reading this thread since there's so much amazing information from people like @Veii but it's difficult gathering it across 309 pages. TBH I'd love some suggestions on where to start for improving these timings. 😅
> 
> I think I will go GDM off, 2T and continue tightening from there (since i saw that suggested earlier). Beyond that though, I'm not sure. Most seem to be running 2x8 single rank, not 2x16.


It's korean, but the person did a wonderful job of collecting crucial information
쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네 ~ A, B, C, (D) 
suggested to use bing or yandex translate
google and "asian" languages is quite messy 
It always messes up with different non latin writing systems

Start with GDM off 2T, and get that RTT, CAD_BUS, tCKE (9) stable


----------



## Hale59

Alemancio said:


> Is it me or how come *there are virtually no 2x16GB Samsung B-Die kits for sale*, for months. Anybody know why or got any link I can grab?


Yeah, right here.
The only problem is they sell inside the borders only. No export.
If you know someone locally who can purchase for you and then ship it...


https://www.wootware.co.za/g-skill-f4-3600c16d-32gtzn-trident-z-neo-32gb-2x16gb-ddr4-3600mhz-cl16-1-35v-black-desktop-memory.html



*EDIT: This is ZA (Rands)*


----------



## craxton

KedarWolf said:


> Added Win10ISO only links, Benching O/S only and a file with everything in it.
> 
> Link to stripped benching O/S. Testing as working today. Windows install ISO you need to set up with Autoruns and an already set up preconfigured Macrium image, no Autoruns, nothing needed, install the image, run Benchmate, select benchmark. Macrium Free, RUFUS and Autoruns included. Tested as working with no sound, no printing, all unneeded services disabled etc. Has Internet access though.
> 
> *Read the InstructionsREADME!!!!!.txt included in the zip!!*
> 
> Oh, and if you need to install MSI Afterburner and I think I might have missed video card drivers, Run the included Autoruns64.exe as Admin, uncheck all the Hide options in Options, go to Services, enable TrustedInstaller, reboot, install Afterburner and/or your GPU drivers.
> 
> 
> 
> 
> 
> 
> Benching - Google Drive
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> 
> Attachment is what is stripped from Windows.


thank you for this as there is loads out there that claim stripped etc but you never can tell, 
at the moment online scouting for either a mi 10 pro or mi 11
just got home from " Great wolf lodge" with the family, and havent been online a few minutes yet. 

can one use Viper to add certain services to this install, or do you suggest only installing this stripped down version, 
only on a separate partition/drive for benchmarking etc? at the moment ive got quite a bit i allow to run at start up, 
AB, razor synapse, PX1, HWinfo, N/CP, GeForce experience etc, but
for things like xbox services there disabled, phone services, print etc pretty much everything...

whats your usage set at with this install??


----------



## PowerK

This sucker (2x16GB B-die) won't run at tRCDRD 14.


----------



## lmfodor

Serchio said:


> Since we started talking about 2x16GB B-Die, which set would you recommend? Prices are horrible of course...
> 
> F4-3600C16D-32GTZN
> F4-3600C14D-32GVK
> F4-4000C16D-32GTZR
> F4-4266C17D-32GVKB


Hi, do you know of all the above are bdie? I only found available the F4-4000C16D-32GTZR but can’t find it there are bdie. Thanks!


Sent from my iPhone using Tapatalk Pro


----------



## Serchio

lmfodor said:


> Hi, do you know of all the above are bdie? I only found available the F4-4000C16D-32GTZR but can’t find it there are bdie. Thanks!
> 
> 
> Sent from my iPhone using Tapatalk Pro


Yes, all from the list are B-Die. You can check this page to have up to date information about B-die kits.


----------



## lmfodor

Serchio said:


> Since we started talking about 2x16GB B-Die, which set would you recommend? Prices are horrible of course...
> 
> F4-3600C16D-32GTZN
> F4-3600C14D-32GVK
> F4-4000C16D-32GTZR
> F4-4266C17D-32GVKB


What I found is that any of this kit and extremely hard to find. I usually buy at Amazon since I live outside US and I have a special service from Amazon for a door to door services. Last couple of weeks I was looking for any newer kit for low latencies, rayzen 5000 ready. I have an Asia CrossHero VIII, but no matter the price, there aren’t available


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

lmfodor said:


> What I found is that any of this kit and extremely hard to find. I usually buy at Amazon since I live outside US and I have a special service from Amazon for a door to door services. Last couple of weeks I was looking for any newer kit for low latencies, rayzen 5000 ready. I have an Asia CrossHero VIII, but no matter the price, there aren’t available
> 
> 
> Sent from my iPhone using Tapatalk Pro


Proshop has many DR kits scheduled to arrive the 9th of March:






G.Skill Trident Z RGB DDR4-4266 C17 DC - 32GB | Günstig


329,81 € Memory (RAM), 32 GB: 2 x 16 GB (Dual Channel), DIMM 288-PIN, DDR4, 4266 MHz / PC4-34100, CL17-18-18-38, 1.5 V, unbuffered, non-ECC - G.Skill TridentZ RGB series.




www.proshop.de


----------



## lmfodor

ManniX-ITA said:


> Proshop has many DR kits scheduled to arrive the 9th of March:
> 
> 
> 
> 
> 
> 
> G.Skill Trident Z RGB DDR4-4266 C17 DC - 32GB | Günstig
> 
> 
> 329,81 € Memory (RAM), 32 GB: 2 x 16 GB (Dual Channel), DIMM 288-PIN, DDR4, 4266 MHz / PC4-34100, CL17-18-18-38, 1.5 V, unbuffered, non-ECC - G.Skill TridentZ RGB series.
> 
> 
> 
> 
> www.proshop.de


I found this F4-4000C17D-16GTZR. It seems to be Bdie and low latency for 4000mhz. However I know they aren’t the latest version released for Rayzen 5000. But I see it in my Asus CH8 QVL for Raizen 5000. What do you think. It would be fine?


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

lmfodor said:


> I found this F4-4000C17D-16GTZR. It seems to be Bdie and low latency for 4000mhz. However I know they aren’t the latest version released for Rayzen 5000. But I see it in my Asus CH8 QVL for Raizen 5000. What do you think. It would be fine?
> 
> 
> Sent from my iPhone using Tapatalk Pro


Almost 100% of all good B-die kits are going to work perfectly fine even if not in the QVL.
Not being in the QVL is risky mostly for non B-die and cheap kits.

That said I wouldn't buy the F4-4000C17D-16GTZR myself.
You'll struggle to reduce timings even at 3800; it's a not so great 4000 MHz binning.
Much better a low latency 3800 in my opinion, like the F4-3800C14D-16GTZN which is similarly priced.
That's a very good binning at 3800 and will probably have the same good behavior at 4000.


----------



## lmfodor

ManniX-ITA said:


> Almost 100% of all good B-die kits are going to work perfectly fine even if not in the QVL.
> Not being in the QVL is risky mostly for non B-die and cheap kits.
> 
> That said I wouldn't buy the F4-4000C17D-16GTZR myself.
> You'll struggle to reduce timings even at 3800; it's a not so great 4000 MHz binning.
> Much better a low latency 3800 in my opinion, like the F4-3800C14D-16GTZN which is similarly priced.
> That's a very good binning at 3800 and will probably have the same good behavior at 4000.


Ok, that’s good. I found this model also available but it’s not in the QVL. 
both model are at the same price. So.. I will follow your suggestion. I hope it’s work well!



Sent from my iPhone using Tapatalk Pro


----------



## LTC

Hi, I cant seem to get my memory stable on my Ryzen 2700x system. 

Using a pair of 8GB F4-3600C17-8GVK, in my X470 Aorus Ultra Gaming board, and have set the timings as per Ryzen DRAM Calculator









DRAM voltage is however increased to 1.4V to see if I could get it stable.
I'm running into errors on test 9 with the extreme configuration by anta777.


----------



## KedarWolf

PowerK said:


> View attachment 2480094
> 
> 
> This sucker (2x16GB B-die) won't run at tRCDRD 14.


Try this, on my 2x16GB.


----------



## PowerK

KedarWolf said:


> Try this, on my 2x16GB.
> 
> View attachment 2480122


Thanks. I'll try them.


----------



## slayer6288

Hello all I am coming from a 10900k with decent to solid knowledge of overclocking ram so I wanted to ask a few questions as I am switching to a 5950x with a dark hero viii. So the ram I have is this. Are you a human?. What I can do on the intel system is 15-15-15-35 at 1.4 volts 2t. No way it would do 1t on the intel system. Is this something I can translate over to the ryzen system? what voltages act as the vccio and vcssa? What should i look out for as a amd ryzen noob. Will I be stuck with gear down mode on since its dual rank essentially?


----------



## Ferdmert

Alemancio said:


> Yeah I've tried the same, googled over 30 kits, all OOS. There is a 4000Mhz 2x16GB but not AMD QVL'd for about $350, too much IMHO.
> 
> What were your results with the GSkills?


I have the G-Skill 4000mhz 2x16gb. I love them.


----------



## domdtxdissar

BluePaint said:


> TR is a good benchmark for RAM performance in a game, imho
> Here an older run on 5950X with 3800CL14 and 3080: 265 fps CPU Game


Seems like i was benching the wrong version of the game. Free version on steam was v505 (patch 15) which was missing 4 performance updates 
Version 298 = patch 19

CPU Game = Average 282 fps


----------



## Veii

slayer6288 said:


> Hello all I am coming from a 10900k with decent to solid knowledge of overclocking ram so I wanted to ask a few questions as I am switching to a 5950x with a dark hero viii. So the ram I have is this. Are you a human?. What I can do on the intel system is 15-15-15-35 at 1.4 volts 2t. No way it would do 1t on the intel system. Is this something I can translate over to the ryzen system? what voltages act as the vccio and vcssa? What should i look out for as a amd ryzen noob. Will I be stuck with gear down mode on since its dual rank essentially?


Likely, but on Intel you are not fighting against signal integrity degradation
And on AMD you have to go one step further, tuning Termination Impedance (resistance in this case) from the memory controller to the dimms (trace distance) ~ in order to keep the Data-Eye open
In short = RTT values, which change by dimm amount, dimm capacity and trace length
RZQ = 240ohm

But on the bright side, this gives you more playroom and potentially better OC results 
Although translated differently and from the technical side of things, used for different usecases
AMD <-> Intel
tRDWR -> tRRDR
tWRRD -> tRRDD
They behave pretty much equal in the result.
please don't ask me why, it's just how it is. it makes no sense, but they scale exactly identical 

VCCIO should be cLDO_VDDG IOD
VCCSA should bec cLDO_VDDP
i hope i didn't mess that up

But as short basic explanation
cLDO_VDDP is the iMC
VDDG CCD is inside the fabric the CCX/CCDs (lower is better for signal integrity)
VDDG IOD is the fabric to memory controller (both VDDGs are weighted, changing one changes the other ~ balance is key)
SOC is the System-On-Chip voltage (fabric) and pretty much the main dataline you should be worried on

In the technical terminology
cLDO_VDDP is taken from SOC and VDDG is taken from SOC & balanced
a top to bottom terminology

In the autocorrection terms, it's the opposite
cLDO_VDDP is taken as the voltage basesline.
VDDG then on Vermeer must be at least 40mV higher (Matisse 50mV minimum)
And SOC must be as absolute lowest , the same voltage higher than VDDG

On Matisse, if you had by accident, 1000mV VDDP
VDDG can be as absolute lowest 1050mV (but it can be also 1000 CCD and 1100 IOD ~ balanced, again)
SOC then automatically will be 1100mV as absolute lowest and ignore user input. It will autocorrect upwards unless UncoreOC mode was enabled (throttling bugs, bug that's a long other story)

You can orient to this post for "voltage stepping"
(bottom part of the post, but Vermeer is still identical, just with 40mV stepping)








OC'ing T-Force 4133 cl18


I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...




www.overclock.net




And to this post, for the minimum requirements to reach specific FCLK
(continues post are recommended to be read too)








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net





4 dimms on the Dark Hero either wants 
RTT 7/3/1 
or 
RTT 6/3/3
later one needing tCKE into play 
(9 for 3800, 11 for 4000-4133)

You should start with GDM disabled, 2T 
GDM enabled is an option, but the results are slower and mask powering issues. also round primaries
Suggested is also to disable all performance enhancers, armory crate, fMax enhancers and use PBO Scalar 2x
Also suggested is to run vCore Phase Control on Extreme for full phase & SOC on Phase Response, Fast


Spoiler: Loadlines In-case you want to use CTR






















Even if you dont use CTR (skip RC3 btw)
DRAM loadlines can be cloned and reused 
Although if you have random load-to-idle , hardcrashes by using RTT6/3/3 ~ switch to 350khz switching freq

Getting GDM away , needs higher ClkDrvStr == CAD_BUS settings
beyond 3800MT/s without WHEA is bios dependent. You probably can forget it till the new bios, unless you find 1.1.0.0 patch B or 1.1.8.0 AGESA 


Spoiler: Timing Examples












^ this is rock stable on 4xA2 dimms, but misses tCKE and CAD_BUS Setup times. It looks a bit exotic








^ Very easy to run baseline @ 1.36VDIMM 
(this has tCKE + Setup time, and so powerdown works wonderfully and needs less voltage)








^ and this is my current toy
Needs 1.6v, but might be able to run lower
2x 16, 4x 8gb need tRDWR 10. But might maybe who knows, get away with 9 ~ to to PCB


Something more to add,

tFAW is not anymore 4* tRRD_S, it allows to run lower than that without negative effects
tCKE is used neverless of the GDM and Global Powerdown State/Flag
more than 900mV cLDO_VDDP is not needed on any type of exotic set.
CPU_VDDP beyond 900mV has negative effects. Stay at 880 or 900mV
~ signal integrity is still king, soo lower = better


----------



## RonLazer

Veii said:


> Likely, but on Intel you are not fighting against signal integrity degradation
> And on AMD you have to go one step further, tuning Termination Impedance (resistance in this case) from the memory controller to the dimms (trace distance) ~ in order to keep the Data-Eye open
> In short = RTT values, which change by dimm amount, dimm capacity and trace length
> RZQ = 240ohm
> 
> But on the bright side, this gives you more playroom and potentially better OC results
> Although translated differently and from the technical side of things, used for different usecases
> AMD <-> Intel
> tRDWR -> tRRDR
> tWRRD -> tRRDD
> They behave pretty much equal in the result.
> please don't ask me why, it's just how it is. it makes no sense, but they scale exactly identical
> 
> VCCIO should be cLDO_VDDG IOD
> VCCSA should bec cLDO_VDDP
> i hope i didn't mess that up
> 
> But as short basic explanation
> cLDO_VDDP is the iMC
> VDDG CCD is inside the fabric the CCX/CCDs (lower is better for signal integrity)
> VDDG IOD is the fabric to memory controller (both VDDGs are weighted, changing one changes the other ~ balance is key)
> SOC is the System-On-Chip voltage (fabric) and pretty much the main dataline you should be worried on
> 
> In the technical terminology
> cLDO_VDDP is taken from SOC and VDDG is taken from SOC & balanced
> a top to bottom terminology
> 
> In the autocorrection terms, it's the opposite
> cLDO_VDDP is taken as the voltage basesline.
> VDDG then on Vermeer must be at least 40mV higher (Matisse 50mV minimum)
> And SOC must be as absolute lowest , the same voltage higher than VDDG
> 
> On Matisse, if you had by accident, 1000mV VDDP
> VDDG can be as absolute lowest 1050mV (but it can be also 1000 CCD and 1100 IOD ~ balanced, again)
> SOC then automatically will be 1100mV as absolute lowest and ignore user input. It will autocorrect upwards unless UncoreOC mode was enabled (throttling bugs, bug that's a long other story)
> 
> You can orient to this post for "voltage stepping"
> (bottom part of the post, but Vermeer is still identical, just with 40mV stepping)
> 
> 
> 
> 
> 
> 
> 
> 
> OC'ing T-Force 4133 cl18
> 
> 
> I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> And to this post, for the minimum requirements to reach specific FCLK
> (continues post are recommended to be read too)
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> 4 dimms on the Dark Hero either wants
> RTT 7/3/1
> or
> RTT 6/3/3
> later one needing tCKE into play
> (9 for 3800, 11 for 4000-4133)
> 
> You should start with GDM disabled, 2T
> GDM enabled is an option, but the results are slower and mask powering issues. also round primaries
> Suggested is also to disable all performance enhancers, armory crate, fMax enhancers and use PBO Scalar 2x
> Also suggested is to run vCore Phase Control on Extreme for full phase & SOC on Phase Response, Fast
> 
> 
> Spoiler: Loadlines In-case you want to use CTR
> 
> 
> 
> 
> View attachment 2480202
> 
> View attachment 2480203
> 
> 
> 
> Even if you dont use CTR (skip RC3 btw)
> DRAM loadlines can be cloned and reused
> Although if you have random load-to-idle , hardcrashes by using RTT6/3/3 ~ switch to 350khz switching freq
> 
> Getting GDM away , needs higher ClkDrvStr == CAD_BUS settings
> beyond 3800MT/s without WHEA is bios dependent. You probably can forget it till the new bios, unless you find 1.1.0.0 patch B or 1.1.8.0 AGESA
> 
> 
> Spoiler: Timing Examples
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ^ this is rock stable on 4xA2 dimms, but misses tCKE and CAD_BUS Setup times. It looks a bit exotic
> 
> 
> 
> 
> 
> 
> 
> 
> ^ Very easy to run baseline @ 1.36VDIMM
> (this has tCKE + Setup time, and so powerdown works wonderfully and needs less voltage)
> View attachment 2480205
> 
> ^ and this is my current toy
> Needs 1.6v, but might be able to run lower
> 2x 16, 4x 8gb need tRDWR 10. But might maybe who knows, get away with 9 ~ to to PCB
> 
> 
> Something more to add,
> 
> tFAW is not anymore 4* tRRD_S, it allows to run lower than that without negative effects
> tCKE is used neverless of the GDM and Global Powerdown State/Flag
> more than 900mV cLDO_VDDP is not needed on any type of exotic set.
> CPU_VDDP beyond 900mV has negative effects. Stay at 880 or 900mV
> ~ signal integrity is still king, soo lower = better


Do you have any documentation or experiment data to prove your claims on tCKE? I've been reading a lot of your posts and learned a bunch of useful stuff, but I cannot replicate your results with tCKE and CAD setup times at all. I see no variation in Aida64 or Geekbench3 results from varying tCKE when Powerdown mode is off.


----------



## KedarWolf

KedarWolf said:


> Try this, on my 2x16GB.
> 
> View attachment 2480122


If the other I showed not working, try this.


----------



## magnusavr

Got a question in regards to memory. I see that Veii recommends some voltages regarding 40mV steps. He also recommends minimum 1.075 for 3800MHz.

Currently using the following voltages:

SOC 1.06 (bios changes this to 1.0625)
VDDG CCD 0.940
VDDG IOD 0.980
CLDO VDDP 0.900

Using Ryzen 5950x and x570 hero (3204 bios) with 2x16GB dual rank B-Die running 3800MHz. System passes TM5 tests just fine.

*But if I want to give it a tiny bit more SOC voltage, say 1.08 og 1.1 just to make sure. Do I have to adjust any of the other voltages listed above? Veii said something about voltage steps in 40mV increments. Does that also apply for the SOC voltage itself? If I adjust SOC voltage to 1.1 I can leave those other voltages I listed above at the same values right? *

If I leave all those Voltages on Auto Asus adjusts them to:
SOC: 1.080 bios (ryzen master says 1.1)
VDDG CCD 0.9474 (ryzen master)
VDDG IOD 1.0477 (ryzen master)
CLDO VDDP 1.0979 (ryzen master)

Reason for wanting a tiny bit more SOC voltage is also perhaps a tiny bit increase in performance. I saw someone listing performance numbers in regards to SOC voltage increase and the performance numbers went up with the voltages.


----------



## magnusavr

Also see 2T being recommended over 1T GDM now. Here is one test with 2T and one with 1T GDM. 2x16GB. Any recommendations?


----------



## YoungChris

Figuring out AMD's equivalent to RTL and IOL (RDL and MRL)


I'm looking into AMD's equivalent of RTL and IOL, which are RDL and MRL. I remember @chew* and @I.nfraR.ed mentioning these were configurable in OS on K10. I have now found evidence of two sets of memory, when training the exact same configurable timings and voltages, reporting different RDL and ...



community.hwbot.org




Calling anyone who may be able to provide input or is curious.


----------



## domdtxdissar

magnusavr said:


> Also see 2T being recommended over 1T GDM now. Here is one test with 2T and one with 1T GDM. 2x16GB. Any recommendations?
> 
> View attachment 2480453
> 
> 
> View attachment 2480454


Something wrong with your T2 numbers.. Read bandwidth is far too low.

This is my numbers taken in windows safemode to reduce interference from bloatware etc.
4x8gigs sticks

T2 with GDM disabled








T1 with GDM enabled








Both runs used same memory settings:








My overall finds is that T1 GDM enabled gives a few hundred mb/sec higher read/write numbers, but is 0.1-0.2 NS slower in latency. (on average over multiple runs)
PS: Du kunne spurt meg for mer data på det norske forumet 

_edit_
*Veii's RTT 6-3-3 tcke9 3800 T2 GDM disabled















*
Latency numbers seems more stable: 5/5 times 54.1 ns


----------



## Martin778

I wonder if running Aida with priority set to "realtime" would make the difference between consecutive runs even smaller? We could ask the developer aswell to make a looped version of the memory/cache bench.


----------



## KedarWolf

Anyone test with DRAM Calculator For Ryzen?

I get this, but only after replacing the memtest.exe in it with my MTPclassic.exe from HCI MemTest 7.0 and rename it to memtest.exe.


----------



## magnusavr

domdtxdissar said:


> Something wrong with your T2 numbers.. Read bandwidth is far too low.


Nickname på diskusjon?

I am going to retest it later. In case it was something in the background affecting it. The only change was disabling GDM and switching to 2T on the 5950x system. Just did the same test on my tv computer (5800x) and there latency dropped by 0.4ns without the read spead taking a big hit.


Update. Guess it was that run. Did 3 new runs (1.06v SOC)


----------



## Veii

RonLazer said:


> Do you have any documentation or experiment data to prove your claims on tCKE? I've been reading a lot of your posts and learned a bunch of useful stuff, but I cannot replicate your results with tCKE and CAD setup times at all. I see no variation in Aida64 or Geekbench3 results from varying tCKE when Powerdown mode is off.


I'm sorry, but to answer this exactly how you ask me, i'd need to collect data through 4 months of testing.
tCKE is only used on Vermeer without GDM & Powerdown's flag doesn't matter
There are two theories on that. Using it enables powerdown neverless of the state (doubt) & it's a different state of powerdown (rather this)

RTTs used already do dynamic on-die termination changes and shape CKE high and CKE low correspondingly
Using RTTs i use with a 2nd powerdown shaping - is usually a very bad idea. But i guess it works very well atm
I can clearly say tho, that tCKE does influence how RTT behaves and _"probably" _ will only do a change if DynamicODT works = with 706 (2x8GB or 633 4x8GB/2x16GB / in this case also 713)








쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네


출처:https://blog.asset-intertech.com/test_data_out/2014/11/memory-training-testing-and-margining.ht



coolenjoy.net




This thread should give you an idea how tCKE behaves on it's core ~ but it might not be easily understandable
I will write someday a better review ~ but to answer your question the way you ask me, i can't atm. Information is too spread between discords, forums (chiphell) and threads on OCN.








This is what i want to share again for people who keep asking about 2T and "no differrence"
* yes i by accident used wrong tCKE values from my 4000+ sets, but they have a bit of playroom (-75 to -80MT/s / +75 to +80MT/s ~ soo about 200MT/s or +/- 3 steps)
Not to forget that some boards also use tCKE after 3600.
It working without GDM or PDM, is purely a Vermeer thing ~ but a major memOC stability factor for me @ 4200MT/s

EDIT:
I use them purely as Stability Enhancers and high voltage Tamer (starting to daily 1.58v-1.6vDIMMM)
That they help getting GDM off 2T or even 1T & even for some add 0.1-0.5ns benefits, is just a nice sideeffect bonus
For me they are purely a stability thing and go together with RTT, CAD_BUS & their Setup timings
While Setup Timings & tCKE do change by MCLK
Same as tMAW ~ you'll read down bellow

RCPage right now you guys can set as perfect half of tRFC ~ if you use tRFC mini
If you get "PFN_List Corrupt" BSODs after the 15th cycle, then it was wrongly set up
~ a better tutorial and usable "ruleset" will come soon ~ it's test in progress
But RCPage == tMAW.MAC
"The minimum average time in memory clock cycles within a refresh window, from an activate command to another activate command"
You should focus on tRRD & tFAW but the math is complicated. Half of used tRFC works well 
It's a big timing like tREFI is, and rather a "just do it/stability thing" like tRFC 2/tRFC 4 is
** but it's too experimental to recommend as "always being used"

Meanwhile tCKE 9 needs to have it's corresponding CAD-BUS Setup Timings. It doesn't work well without them
Do NOT use it alone @domdtxdissar
*** same goes for SETUP Timings without 40-20-20-20 . They all go in pairs


----------



## domdtxdissar

Veii said:


> This is what i want to share again for people who keep asking about 2T and "no differrence"


Just like my findings from above: "T1 GDM enabled gives a few hundred mb/sec higher read/write numbers, but is 0.1-0.2 NS slower in latency compared to T2. (on average over multiple runs) "




Veii said:


> Meanwhile tCKE 9 needs to have it's corresponding CAD-BUS Setup Timings. It doesn't work well without them
> Do NOT use it alone @domdtxdissar
> *** same goes for SETUP Timings without 40-20-20-20 . They all go in pairs


Hmm i have just completed stability testing without the CAD-BUS Setup Timing and SETUP Timings.. Everything seemed fine without them.








Is there risk for any harm to run without them ?

_edit_
This is what you want me to run, correct ?


----------



## Veii

domdtxdissar said:


> Hmm i have just completed stability testing without the CAD-BUS Setup Timing and SETUP Timings.. Everything seemed fine without them.
> 
> Is there risk for any harm to run without them ?
> 
> _edit_
> This is what you want me to run, correct ?
> View attachment 2480594


The only risk are random shutdowns if tCKE and Setup times dont match / which are not trackable via TM5 ~ unless it crashes on Error #15
Setup time missmatch by 1 value already results in instability between programm full load, and idle
They just go together with the RTT values above.
6/3/3 for 4 dimms are not fully perfect yet - they fail on flat C14 sets, but that takes a long time to find ones that work well
I think they are fine, and definitely better than 713 ~ just better voltage range without instability

when testing latency, be sure to make 2-3 runs
the first after reboot runs the cpu on 100% powerstate, and can be off ~ because many services are delayed
I use a frequency matched minimum powerstate (7% @ 4.65Ghz)
Different frequency needs differrent minimum powerstates, but 0% works on new 1.2.0.0 to fully suspend some cores
The main reason why you see different/low frequency on my tests (my powerplan is a bit too slow to start)
But starting with a suspended cores state ~ gives the best Aida64 mem-test accuracy


----------



## YpsiNine

I've been trying to get 1900+ infinity fabric to work but I can't get rid of the WHEA's. So I've decided to stick with 1866 for now.

So I have a pair of 16 GB b-die that I want to run at 3733 M/T at around 1.4V max.
During some 30 minute run I'm getting errors on TM5 1usmus test 3 and 5, and according to the error list that could be related to tRDWR/TWRRD or tRP, tRFC - both which I find relatively unlikely.
Shouldn't tCL 16 on this kind of M/T be relatively safe, especially at 2T?

Does anyone have any idea what to adjust next? Or maybe somebody has another relatively fast config for around 1.4V at 3733 M/T?
This config is based on the Ryzen DRAM Calculator, only difference is I'm running 2T instead of GDM ON.
tRFC/2/4 was configured with what I thought was a conservative value of 180 ns by using Veii calculator.


----------



## Veii

YpsiNine said:


> I've been trying to get 1900+ infinity fabric to work but I can't get rid of the WHEA's. So I've decided to stick with 1866 for now.
> 
> So I have a pair of 16 GB b-die that I want to run at 3733 M/T at around 1.4V max.
> During some 30 minute run I'm getting errors on TM5 1usmus test 3 and 5, and according to the error list that could be related to tRDWR/TWRRD or tRP, tRFC - both which I find relatively unlikely.
> Shouldn't tCL 16 on this kind of M/T be relatively safe, especially at 2T?
> 
> Does anyone have any idea what to adjust next? Or maybe somebody has another relatively fast config for around 1.4V at 3733 M/T?
> This config is based on the Ryzen DRAM Calculator, only difference is I'm running 2T instead of GDM ON.
> tRFC/2/4 was configured with what I thought was a conservative value of 180 ns by using Veii calculator.
> 
> 
> View attachment 2480599


tRDWR should be 9 here, not 8
(Dual Rank = +2 or +1 & tWRRD delay. tRCD / 2 = 8+1 = 9 , not 8 as absolute lowest)
But you fail because of far too high procODT and too weak ClkDrvStr to get 2T stable
No tCKE usage would be 40-20-30-20 or 60-20-40-20 as CAD_BUS, 24 is too weak

What means "relative fast" ?
6/3/3 RTT would be perfect for 2x16, but only 90% fine for 4x8GB
This is easy to run at 1.36v @ 3800








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Anyone with 4 DIMMS running a 5000 series at 3800 mhz/ 1900 FCLK? Right now I'm stable at 3733/1866 Cas14 just as I was with my old 3900x. I'm trying to get Cas 14 at 3800/1900. I tried adjusting some timings but did not have luck booting 3800/1900 1.50V at Cas 14. I have a Memory Cooler and...




www.overclock.net




clone "everything"
If you can find CPU VDDP , set that to 880mV - if you can't , set all VDDPs you find to 900
tCKE 9 , 3-3-15 should still be fine for 3733, but give 3800 another try

Also dual rank of 4 dimms need 1-4-4-1-6-6 as SD, DD's


----------



## YpsiNine

Veii said:


> tRDWR should be 9 here, not 8
> (Dual Rank = +2 or +1 & tWRRD delay. tRCD / 2 = 8+1 = 9 , not 8 as absolute lowest)
> But you fail because of far too high procODT and too weak ClkDrvStr to get 2T stable
> No tCKE usage would be 40-20-30-20 or 60-20-40-20 as CAD_BUS, 24 is too weak
> 
> What means "relative fast" ?
> 6/3/3 RTT would be perfect for 2x16, but only 90% fine for 4x8GB
> This is easy to run at 1.36v @ 3800
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Anyone with 4 DIMMS running a 5000 series at 3800 mhz/ 1900 FCLK? Right now I'm stable at 3733/1866 Cas14 just as I was with my old 3900x. I'm trying to get Cas 14 at 3800/1900. I tried adjusting some timings but did not have luck booting 3800/1900 1.50V at Cas 14. I have a Memory Cooler and...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> clone "everything"
> If you can find CPU VDDP , set that to 880mV - if you can't , set all VDDPs you find to 900
> tCKE 9 , 3-3-15 should still be fine for 3733, but give 3800 another try
> 
> Also dual rank of 4 dimms need 1-4-4-1-6-6 as SD, DD's


Appreciated with you chiming in, I need to learn. Was not aware that 2T required different setup than what's presented in the DRAM Calculator for GDM.
I tried this again at 1900 infinity fabric first and it would boot and run fine, but the WHEA's immediately started showing up so I went back to 1866.
So it's looking good so far, 31+ minutes in and counting without any problems, after adjusting some parameters:

tRDWR 8 -> 9
procODT 43.6 -> 36.9
RTT -/3/1 -> 6/3/3
CAD_BUS 24/20/24/24 -> 40/20/20/20
tCKE 1 -> 9
ClkDrv 0/0/0 -> 3/3/15
tRFC 317/236/145 -> 288/214/132
CPU VDDP -> 880 mV
_CLDO VDDP remains at 900 mV_
_VSOC remains at 1.1 V_
VDDG CCD 940 mV -> 950 mV
VDDG IOD 980 mV -> 1000 mV (your IOD at 1060 mV feels a bit high for my taste...)
DRAM 1.4V -> 1.38V
I left the SC, SD and DD at 1-5-5-1-7-7 since I have dual rank of 2x16 dimms, not 4x8.
So comparing your setup to mine now, it seems you have tRTP at 9 instead of 8 and generally you have some other more relaxed timings (like tRRDS/tRRDL/tFAW etc.). Any particular reason for that, do they harmonize better with the other parameters?


----------



## PowerK

AFAIK, if Power Down Mode (power saving feature of DDR4) is disabled, tCKE has no effect.


----------



## KedarWolf

Pretty happy with this for 3800.

Note, I have tCWL at 12. And yes, I know I'm breaking some known timing rules, but bandwidth much higher and latency better than ever.


----------



## Merutsu

KedarWolf said:


> And yes, I know I'm breaking some known timing rules, but bandwidth much higher and latency better than ever.


Nope, something is wrong. I have very similar results with timings 16-16-16-32-48:


Merutsu said:


> Here is my OC of dual rank b-die, 2x16GB G.Skill FlareX
> View attachment 2479903
> 
> vdimm: 1.41v in bios, hwinfo reports 1.432v
> vsoc: 1.0625v with llc mode4, because of vdroop it's ~1.050v
> max ram temps with custom heatsinks are 43-44C even after hours of gaming.


----------



## KedarWolf

Merutsu said:


> Nope, something is wrong. I have very similar results with timings 16-16-16-32-48:


My CL14 is marginally better, somewhat better on the caches. But yeah, it should be a lot better. :/

I get this with CL16.


----------



## craxton

(EDIT) since i got no answer, i figured there was already an answer out,
i suppose 1.29soc would be pushing "safe daily" but at least i know this is considered safe since
motherboards are auto setting this voltage (joke) but still 3000 suppose to be safe at 1.2/1.29 

one thing ive not asked nor paid a bit of mind to, but
how is degradation with 1.2soc voltage while ones running 4000mhz frequency etc?

is there nothing to provide any info yet, is it a guaranteed thing that will happen,
lowering soc below 1.2 isnt possible with 4000mhz as it throws latency ALL OVER the place
as well as read/copy/write speeds all differentiate as well.

anyone got anything on this? should one assume its the same as 3000 series chips where it degrades
signal integrity, if it does, is it just as fast, slow, long time before noticing ?


----------



## GribblyStick

Hey all, coming from a different thread, but it's not really on topic anymore so I figured I'd ask here.

Had a suspected bad IMC so I went and got a new 5900x, along with better memory.
That allowed me to go from 3600 max to 4000/2000 and GMD disabled (on 3600) where it wasn't possible previously...buuuut.
I'm still in the process of testing, but so far I see this. GMD disabled only seems to boot at 3600 and is a blue screen of death bonanza, but it boots all the way into windows if it feels like it.
I didn't bother trying to get it stable and instead tried to get my xmp profile at least, that being 4000 CL15, 4-4000C15Q-32GTZR .

No dice, since I reckon that, it being rated at CL15 means it auto disables GMD and thus won't boot.
If I turn that on manually I can get a boot, and after a few minutes of TM5 no immediate errors (CL16-16-16-36). except, I'm noticing that it is running slow as molasses.
Aida is showing me sub 10000 read/write speeds and even BIOS will be slow, like unbearabl slow. The other timings being all auto are obviously not great but it shouldn't be THIS slow.
It takes me a few seconds to even open windows explorer, so something must be going, but I have no idea where to start since it seems otherwise stable.

Any ideas?












If I take the exact same settings and run at 3800/1900 I get the expected performance. Everything runs normally.
At 4000 it does actually crash if I run testmem5, but it's weird. It runs for like 10 minutes, no issue, then it will hard crash.
It reboots with no error or bluecreen or anything. It just reboots out of the blue (successfully but yea)

I still have no clue what's going on. 
It's not just 4000 though, anything above 3800 does the same thing but its even slower than 4000/2000.
To the point I'm not even able to shutdown because it takes so long to open the menu.
How can I have seemingly no errors yet have such a horrible experience?


----------



## PowerK

Tightened a bit more. Passed TM5 anta777 overnight. Pretty happy with it.

GDM









And 2T


----------



## Veii

PowerK said:


> AFAIK, if Power Down Mode (power saving feature of DDR4) is disabled, tCKE has no effect.


Two rules are different on Vermeer
tCKE works neverless of the powerdown flag and doesn't require GDM to be enabled either - also goes together with dynamic On-Die-Termination
tFAW doesn't have to be 4* tRRD_S anymore, and lower does function and is accepted

Enabling PDM flag does no change if tCKE is supplied
Different supplied tCKE does a change
You'll notice it after going to a point where DIMM instability happens and Powerdown is needed to tame high voltages



YpsiNine said:


> Appreciated with you chiming in, I need to learn. Was not aware that 2T required different setup than what's presented in the DRAM Calculator for GDM.
> 
> 
> CPU VDDP -> 880 mV
> _CLDO VDDP remains at 900 mV_
> _VSOC remains at 1.1 V_
> VDDG CCD 940 mV -> 950 mV
> VDDG IOD 980 mV -> 1000 mV (your IOD at 1060 mV feels a bit high for my taste...)
> DRAM 1.4V -> 1.38V
> I left the SC, SD and DD at 1-5-5-1-7-7 since I have dual rank of 2x16 dimms, not 4x8.
> So comparing your setup to mine now, it seems you have tRTP at 9 instead of 8 and generally you have some other more relaxed timings (like tRRDS/tRRDL/tFAW etc.). Any particular reason for that, do they harmonize better with the other parameters?
> 
> View attachment 2480629


Relaxing tRRD, tWTR is PCB dependent
I don't have a good memory kit, and it helps to shift the delay there instead of elsewhere
(My ICs are well, but if i want to daily 1.56v-1.65v, it needs specific taming else the PCB crashes at 1.52v - A0 PCB)
1-4-4-1-6-6 still functions better on Dual Rank, it's not only a 4 dimm thing
But you need to test this closely with SiSoftware Sandra (Multi-Core Efficiency test) and maybe SuperPi 1.5 SX

Pushing tRRD to twice your value and running tFAW as 1* mode, for example is an option
Couple of reasons to that, but it generally is required. The timings where borrowed from my 4200 set and are just easy to run
If you want something tighter, you need higher VDIMM. Little change there would skyrocket your required VDIMM while tRFC is just low enough to be covered by this voltage. It would be a waste of heat
This was the source of baseline timings


Spoiler: Old low voltage Timings














But i find the tCKE,Setup-Time, CAD_BUS method - a bit more stable for higher voltage
(differences between them are just a "i figured it out later/finetuned it later" - time kind of thing)
And yes , it clearly is used - but that's an 3 month old story by now 
Increasing vSOC is needed. 1060 IOD was just required for 2100 FCLK and scaled well down
Soo i don't touch what isn't broken. WHEAs are annoying enough on their own already. Voltage testing takes too much time
If you want it lower, move in 40mV steps from cLDO_VDDP
CPU VDDP 880mV is required for higher FCLK - 930mV is the stock which is plain bad. 900mV works too but 880 is better (single and dual CCD)
AMD max overclocking voltage this whole thread

DRAM Calculator at this point is old.
"What works on Matisse works on Vermeer"
Is kind of correct.
But
"What works on Vermeer, doesn't work on Matisse"
is also correct 
This ones are just better for Vermeer

I just wish to have finally usable bioses with openFCLK
Not the moved package throttle from 2100 down to 2000 , while barely anyone could move in the 4K area still. Shame-


----------



## munternet

A friend is having trouble crashing out of BFV after installing and overclocking his new ram
I have no idea with AMD memory tuning so I thought I would ask the experts
5600x and G.Skill Trident-Z 3200-14-14-14-34 2x8GB Gigabyte B550 Aorus Master
His ram is running mid 40s°c which seems a little warm
Can anyone see any obvious problems and is there a vccio and vccsa equivalent?
Cheers


----------



## ManniX-ITA

@Veii 
I'm using this config now and I confirm 100% (A/B testing 3 times) that in idle I get random reboots with tCKE at 1 and none with tCKE at 9:










With both tCKE values no errors with TM5 but I went only up to 5 cycles.


----------



## Veii

ManniX-ITA said:


> @Veii
> I'm using this config now and I confirm 100% (A/B testing 3 times) that in idle I get random reboots with tCKE at 1 and none with tCKE at 9:
> 
> View attachment 2480721
> 
> 
> With both tCKE values no errors with TM5 but I went only up to 5 cycles.


What made you pick 238 as tRFC ?
the lowest i can figure out is 231-172-106, and that only works with tWR 14, tRTP 7 (under my absurd math) 

You should try 40-20-20-20 CAD_BUS and use SETUP timings of 3-3-15, to finalize tCKE
Actually there are a few things you can try
Running tRC as 29 can work well , if you set tFAW to behave in 1x mode - meaning doubling your current tRRD settings running SCL as 4, running tRDWR +1 and tFAW as 8
(later you can drop SCL)
tRRD 7-9-8 work , or 8-8-8 
for tFAW 6 to work out, you need SCL 6-6, and tRRD 8-11 , tWTR 4-15, 1-6-6-1-10-10 SD,DD 
(1-5-5-1-9-9 for dual rank if 1-4-4-1-6-6 was used before)

I initially asked you about tRFC, so you can try tRCPAGE and maybe push memory a bit or try to lower voltage for it when CKE is accurate
PS: 60-20-20-20 also works with 3-3-15 setup time, for 1T absurdness 


munternet said:


> A friend is having trouble crashing out of BFV after installing and overclocking his new ram
> I have no idea with AMD memory tuning so I thought I would ask the experts
> 5600x and G.Skill Trident-Z 3200-14-14-14-34 2x8GB Gigabyte B550 Aorus Master
> His ram is running mid 40s°c which seems a little warm
> Can anyone see any obvious problems and is there a vccio and vccsa equivalent?
> Cheers
> View attachment 2480720


[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread this post
Please share a zentimings "system info" screenshot from the latest beta





beta - Google Drive







drive.google.com




Expand the whole set if you can 

EDIT2:
These are the most obvious problems
Unclear if you use any PBO enchancers or voltage offsets - but you have might have clock stretching
These values have to match up









SOC is low, soo probably the remain values (CPU VDDP, cLDO_VDDP , VDDG, SOC )
Are not set 

Be sure to test "stock" behavior with this tool








Release 1.1 · jedi95/BoostTester


Added SMT detection.




github.com


----------



## ManniX-ITA

Veii said:


> What made you pick 238 as tRFC ?
> the lowest i can figure out is 231-172-106, and that only works with tWR 14, tRTP 7 (under my absurd math)
> 
> You should try 40-20-20-20 CAD_BUS and use SETUP timings of 3-3-15, to finalize tCKE
> Actually there are a few things you can try
> Running tRC as 29 can work well , if you set tFAW to behave in 1x mode - meaning doubling your current tRRD settings running SCL as 4, running tRDWR +1 and tFAW as 8
> (later you can drop SCL)
> tRRD 7-9-8 work , or 8-8-8
> for tFAW 6 to work out, you need SCL 6-6, and tRRD 8-11 , tWTR 4-15, 1-6-6-1-10-10 SD,DD
> 
> I initially asked you about tRFC, so you can try tRCPAGE and maybe push memory a bit or try to lower voltage for it when CKE is accurate
> PS: 60-20-20-20 also works with 3-3-15 setup time, for 1T absurdness


Testing tRFC 238 as /tCL 14 = 17.
Doesn't seem to help much if at all, probably going back to 252 to try to reduce VDIMM.

Next I'm going to try is indeed tFAW at 1x but I'm still not sure how 

You mean SCL at 4; tRDWR at 11 or 9?; tFAW at 8 and tRRDS/L 8/8 or 7/9?
What about tWRRD? One mis-step there and I have to clear CMOS...

Will try this indeed:



Veii said:


> for tFAW 6 to work out, you need SCL 6-6, and tRRD 8-11 , tWTR 4-15, 1-6-6-1-10-10 SD,DD


So far no luck with 40-20-20-20 or 60-20-20-20 with 3-3-15 with Off/3/1 or 6/3/3, gets always unstable.
But I have still to test there.

What do you mean with try tRCPAGE?
Thought it doesn't work; it's always a dash in the BIOS "-", looks like it's not being used.
Or maybe I'm confusing it with something else? Have to check.


----------



## Veii

ManniX-ITA said:


> So far no luck with 40-20-20-20 or 60-20-20-20 with 3-3-15 with Off/3/1 or 6/3/3, gets always unstable.
> But I have still to test there.
> 
> What do you mean with try tRCPAGE?
> Thought it doesn't work; it's always a dash in the BIOS "-", looks like it's not being used.
> Or maybe I'm confusing it with something else? Have to check.


Keep trying with 40-20-20-20 / 60-20-20-20 / 120-20-20-20
Probably skip first and try to finetune your RTT , for example 7/3/1
But this has an annoying limit of minimum VDIMM near 1.46-1.48 anything lower is strangely unstable
0/X/X works down to 1.2v but is very unstable beyond 1.52v
6/3/3 is very special - but i think i need to redo it. It's great for 2x16gb, but a bit unstable for 4x8. Probably a SETUP time missmatch, testing it is annoying

You run 4x16 or 2x32 ?
I try to skip using RTT_Park as /1, as RZQ seems to have changed on Vermeer since 1081 AGESA.
Overall 240 or 480ohm is too strong. Not a good thing for signal integrity.

Maybe we can create something X / 3 / 2 or X /2 / 2
Usually RTTNom you want to have as weak as possible under /7
i saw you pinged me in the gigabyte/msi ?!? thread about it, but i can not give a good enough explanation to it yet.
Still learning to utilize Dynamic ODT , as it's better than fixed ODT for CKE high and CKE low

The problem with them is, they only result in hard crashes without BSOD and only between the states of full load -> idle
Another problem is, they go hand in hand with tCKE. While in the technical sense, you should use either RTT ODT as powerstate control , or tCKE as powerdown state
Using the nonsense i do, should not work - unless it's perfect. Sadly i can not explain why it doesn't break by using 2 powerdown states combined and synced
Just that "it works well somehow that way"

A lot was inspired by the user PSONE from chiphell, but i took my own testing take on it. He shared it only for one frequency
Same goes for the 1x tFAW part. He noticed it exists - i just noticed tCKE works without GDM for some absurd reason, as it was the key to stabilize 2100 FCLK for me (my cheapo 80 bucks b-dies 🤷‍♂️)
Research you get to know here, is my take on it using a very unstable A0 PCB and couple of tests from other more exotic configurations
I never share untested rulesets, maybe only "experiments" for you to try & help the research

RCPAGE = tMAW.MAC
Bioses report as 0, which it can not be / unless it could be just "skipped"
It's range is like tRFC 1-999.
"The minimum average time in memory clock cycles within a refresh window, from an activate command to another activate command"
^ is a very interesting command, but while being average like tRFC "could be" average postponed. Is a bit hard to actually set "correctly"
Just looking for more testing rabbits - but it's in a very "early research in progress" state.
Start to understand it, but not something i can share or teach without multiple confirmations it actually does something positive.
It's like tRFC something that only breaks or works after 10+ cycles and only with memory clear disabled 


Spoiler: My Take on tFAW 6














But i think tFAW 8 is a bit better. This one needed far to much tRDWR & SCL to keep up stability
4000C14-14-14 tRC 29 is voltage hell on my side. I need above 1.66v to keep up stability. Need to utilize DynamicODT here (RTT_WR) and increase -something- to lower it down to 1.6v. Don't want to daily 1.66v 
About tWRRD,
the old rulesets continue to apply.
tWRRD * SCL = equal or less than tRCD_WR. At worst equal or less than tRCDavg
Sadly 4 dimms need it always supplied as at least "2". Which breaks a bit the ability to go low on tRDWR
High tRRD and 1x tFAW are required for tRAS+1 = tRC to work. 1x tFAW for sure. Else that low tRC breaks fully
tRAS as tRCD+tBL math, i'm still figuring out
Same time figuring out how to get 2167 to post , and beating my head against macOS not wanting to post because of the broken 4G Modes inside recent bioses - without support from ASRock (5-6 month old bios) 


ManniX-ITA said:


> You mean SCL at 4; tRDWR at 11 or 9?; tFAW at 8 and tRRDS/L 8/8 or 7/9?


Both 
You will notice wrong tRRD on issues with Error #2 and #11
Updated the error docs a bit








Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com




Error #15 / crash every cycle is a very interesting one - thanks goes out to @&&Devin
RCPage BSOD or reboot (powerdown looking issue) happens also on test 15 after the cycle ends and memory goes into low powerstate and restores it's full size


----------



## zGunBLADEz

FIRST TRY on the 5900x/mobo/ram combo with one of my kits.. Just dial 16s/[email protected] 16 tfaw and 310 trfc call it a day in everything else on auto and walla.. getting better results than most running with 13s & 14s and such












also trying to figure out the l3 cache speed :/ theres a setting in the bios interfering with it 









scratch that.... now this rams i highly doubt will do 3933 or 4000 error free im dialing settings i know they stable. like i have them bin for 3800 on my x299 rig never got them to boot @ 3933


----------



## jcpq

Hello.
Is it possible to improve any aspect of my configuration?
Thanks


----------



## Gregix

Hi folks!
Just asking not for myself, as I run Intel (so far), but:
Does Msi b450 Tomahawk Max runs well with 4*8Gb sticks? Like b-die 3200c14. They run flawlessly 3800c15/c14 with not so bad voltage(2*8Gb that is), but, can b450 AND 3700x handle them in 4*8Gb configuration? Does anyone had experience with such a setup?


----------



## Nizzen

Does anyone have a Asus Dark Hero profile for 2x16GB b-die memory.

I have 4266c17 2x16GB memory, and about to give up with my 5900x. 3800mhz does not work, so I have to go 3733mhz. 3866 or higher, WHEA errors like crazy.

Thank you


----------



## nexxusty

Veii said:


> What made you pick 238 as tRFC ?
> the lowest i can figure out is 231-172-106, and that only works with tWR 14, tRTP 7 (under my absurd math)
> 
> You should try 40-20-20-20 CAD_BUS and use SETUP timings of 3-3-15, to finalize tCKE
> Actually there are a few things you can try
> Running tRC as 29 can work well , if you set tFAW to behave in 1x mode - meaning doubling your current tRRD settings running SCL as 4, running tRDWR +1 and tFAW as 8
> (later you can drop SCL)
> tRRD 7-9-8 work , or 8-8-8
> for tFAW 6 to work out, you need SCL 6-6, and tRRD 8-11 , tWTR 4-15, 1-6-6-1-10-10 SD,DD
> (1-5-5-1-9-9 for dual rank if 1-4-4-1-6-6 was used before)
> 
> I initially asked you about tRFC, so you can try tRCPAGE and maybe push memory a bit or try to lower voltage for it when CKE is accurate
> PS: 60-20-20-20 also works with 3-3-15 setup time, for 1T absurdness
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread this post
> Please share a zentimings "system info" screenshot from the latest beta
> 
> 
> 
> 
> 
> beta - Google Drive
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> Expand the whole set if you can
> 
> EDIT2:
> These are the most obvious problems
> Unclear if you use any PBO enchancers or voltage offsets - but you have might have clock stretching
> These values have to match up
> 
> View attachment 2480722
> 
> SOC is low, soo probably the remain values (CPU VDDP, cLDO_VDDP , VDDG, SOC )
> Are not set
> 
> Be sure to test "stock" behavior with this tool
> 
> 
> 
> 
> 
> 
> 
> 
> Release 1.1 · jedi95/BoostTester
> 
> 
> Added SMT detection.
> 
> 
> 
> 
> github.com


Impressive bro, you have done your research.

I'm having trouble getting 3800mhz 14-14-14-30-1T (NO GDM) stable. I have it completely stable with GDM on. 20 hours of GSAT with a pass to verify that.

These sticks are 4x8gb B-Die (Patriot Viper 4400mhz). Right now I have my ProcODT set to 43.6, RttNom set to RZQ/7, RttWr set to Off, RttPark set to RZQ/5, MemAddrCmdSetup to 0, CsOdtSetup & CkeSetup are set to 0 as well. Finally my CAD_BUS settings are 24-20-24-24.

Any tips for a brother? Lol. I usually don't ask for help, however I've never delved this far into overclocking RAM. I'm quite positive my chip, RAM and Mobo can do this as it takes a minute or so for GSAT to throw an error. I've rarely had a setting I couldn't stabilize if it was quasi-usable already.

Thank you man!


----------



## Swazimodo

I recently had a stable 4000mgz memory oc and lost the config after a bios update. I didn't have the number written down anymore and had to start again from scratch. I am new to this and I have no idea what I did last time. Just found this site and you guys have a great community here. 

CPU: 5600x
motherboard: strix b550-e
ram: 16gb x 2 (b-die DR kit)

Here is where I'm at right now. I think my timings are fairly good because but I'm not sure what to do with the voltages. The as I tweak them the latency seems fairly random. It's been as low as ~60.5 or as high as 64. When I test with prime95 I'll typically start seeing errors around the 10 minute mark. If someone could confirm my timings are good and provide some guidance on what to do with my voltages that would be very appreciated. I would love to try under volting the cpu but I want this stable before I do anything else.


----------



## nexxusty

Try SOC at 1.2v. For 2000mhz, I've been told it's necessary to stabilize latency.

I'd simply see if upping it a bit has any effect.

Looking good so far. I need to learn more about this. I have close to the same setup as you. 5600x with 4x8 B-Die. If you can get that stable I should be able to as well. These are Patriot Viper 4400mhz B-Dies I'm running.

I just don't understand ProcODT and CAD_BUS as well as I need to adapt your settings to mine. From what I know, that's the key to getting 4x8 to work like 2x16. The memory controller doesn't know the difference.

I'm so close to 3800mhz CL14 1T GDM Off. I can taste it.

So I'm seeing over and over that 2T GDM OFF is better than 1T GDM ON. The numbers back this up 100%. So considering I and many others just thought of GDM as "1.5T", clearly it adds latency. Am I even shooting to attain a faster setting? Meaning is 3800 CL14 1T GDM OFF faster than 2T GDM OFF?

I feel like I have to ask now, and are we SURE this wasn't an SoC voltage issue? Honestly don't remember GDM being a detriment beforehand, fairly sure this is a Ryzen 3000-5000 thing. I'm positive GDM didn't do this on Zen1 and Zen+.

_Edit_

Always save your stable memory (Or otherwise) configuration to a USB drive brother! Just try to get in the habit of doing it like I have.

This has happened to me more than once and I finally got sick of it.


----------



## PowerK

A question. Does tRRDL has to be tRRDS + 2 ??
I set both at 4 and stability-wise, I see no problem. But if it has to be tRRDS+2 so the board/dimm auto-corrects it, there must a latency penalty.

Another question would be tWRRD. I have it at 2 with GDM1T setting. But with 2T, I cannot POST with tWRRD at 2. Hence I raised it to 4 for 2T. Any idea how I should bring it down to 2 for 2T?

Below is the timings I've settled on. Comments are welcome.


----------



## nexxusty

PowerK said:


> A question. Does tRRDL has to be tRRDS + 2 ??
> I set both at 4 and stability-wise, I see no problem. But if it has to be tRRDS+2 so the board/dimm auto-corrects it, there must a latency penalty.
> 
> Another question would be tWRRD. I have it at 2 with GDM1T setting. But with 2T, I cannot POST with tWRRD at 2. Hence I raised it to 4 for 2T. Any idea how I should bring it down to 2 for 2T?
> 
> Below is the timings I've settled on. Comments are welcome.
> View attachment 2480825


Your IOD is too high. Over 1.05V apparently can damage and degrade. Its also not within 40mv of SoC.

Fix that bro. ;-)


----------



## PowerK

nexxusty said:


> Your IOD is too high. Over 1.05V apparently can damage and degrade. Its also not within 40mv of SoC.
> 
> Fix that bro. ;-)


Thanks! I thought IOD should be around less than 50mV from SoC.
So, I put the following in the BIOS:
SoC = 1125 mV
VDDP = 950 mV
VDDG CCD = 1050 mV (-0.025V from VDDG IOD)
VDDG IOD = 1075 mV (-0.050V from SoC voltage)

So, IOD and SoC are about 50 mV apart. You mean to lower IOD further ?


----------



## nexxusty

I was advised via a post, that there needed to AT MOST a 40mv delta between IOD and SOC. Meaning IOD mv cannot approach, but not be over within 40mv of SOC mv. Better to ask someone else here with more knowledge to be sure. Veil seems to be the one here with the most research done. I would ask him. AFAIK though, if your difference is 50mv currently, the obvious choice, knowing this information, would be to lower it 10mv.

Can't hurt.

I have asked him something myself.

I do believe it was him who I am getting this from. Essentially, this man has already done much of the work and testing for us. He even seems to have ranges to offer and not just any one setting, which IMO denotes multiple kits tested, possibly even multiple CPU's.

I really think that man can help me stabilize 3800mhz CL14 GDM OFF.

I just tested GDM OFF 2T at those settings. Definitely worse on my end. Simply not tweaked enough I assume. I think it's a matter of 2T GDM off VS 1T GDM on CAN be faster. With some tweaking. Where as 1T GDM ON can never be as fast as a properly tweaked 2T GDM off setup.

At least this is what I assume, I'm not left with much else explanation wise, as my tests indicate no inherent speed increase.


----------



## PowerK

No problem, bud.  Thanks for your input.


----------



## Veii

The information spread is a bit missleading
I judge myself for not writing it out correctly and well understandable








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




^ voltage examples
SOC is GET (value) readout, VDDP, VDDG are SET values

Old scaling example of voltage "steppings"








OC'ing T-Force 4133 cl18


I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...




www.overclock.net




Keep in mind, even when this was Matisse | it's an illustration how you scale it upwards
Real "dangerous" territory on Vermeer is:
cLDO_VDDP 1100,
cLDO_VDDG CCD 1150
cLDO_VDDG IOD 1175-1200 (little peaks over 1200 likely will fry the io-die | dont ever exceed 1150)
VDCCR SOC 1300-1317-25 | make it 1325mV

Keeping the others lower and SOC at worst 1.4v only works near -8 ~ -20c
Dont ever run beyond 1.3v above the freezing point
1250 is what is by default applied for 2100 FCLK, and sub 1.3 for the 2167 wall

I would never run beyond 1120 IOD. While 1060 is enough till 4133/2067
Tested it yesterday for 4220+ and 1160 IOD is purely bad. Instability hell
You can run 1100 if you really desire, but that requires high procODT for high voltages
High procODT = lower chance of ever hitting high FCLK
Lower procODT = harder to balance dimm powering, but allows lower voltages & so better signal integrity

Let me handwire-reflash my board and i'll answer the mem requests.
Tried crossflashing because ASRock ignores their B550 boards. Hardlocked myself on a gigabyte bios without usb boot ability haha

Questions asked here are double tripple answered
Please scroll back at least 3-4 pages before asking the same answered question 😇
EDIT:
There is not one "correct" stepping
You can run whatever you want, but keep the scaling consistent
40mV appears to be the lowest reasonable without AVX2 hardcrashes


----------



## PowerK

All right, Veii. Thanks.
I just started running TM5 1usmus_v3 config with:
vDIMM = 1.510 V (Vdroop to 1.50V) (down from 1.520)
VSoC = 1100 mV (down from 1125)
VDDP = 900 mV (down from 950)
VDDG CCD =900 mV (down from 1025)
VDDG IOD = 1000 mV (down from 1050)


----------



## magnusavr

Veii said:


> The information spread is a bit missleading
> I judge myself for not writing it out correctly and well understandable
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> ^ voltage examples
> SOC is GET (value) readout, VDDP, VDDG are SET values
> 
> Old scaling example of voltage "steppings"
> 
> 
> 
> 
> 
> 
> 
> 
> OC'ing T-Force 4133 cl18
> 
> 
> I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> Keep in mind, even when this was Matisse | it's an illustration how you scale it upwards
> Real "dangerous" territory on Vermeer is:
> cLDO_VDDP 1100,
> cLDO_VDDG CCD 1150
> cLDO_VDDG IOD 1175-1200 (little peaks over 1200 likely will fry the io-die | dont ever exceed 1150)
> VDCCR SOC 1300-1317-25 | make it 1325mV
> 
> Keeping the others lower and SOC at worst 1.4v only works near -8 ~ -20c
> Dont ever run beyond 1.3v above the freezing point
> 1250 is what is by default applied for 2100 FCLK, and sub 1.3 for the 2167 wall
> 
> I would never run beyond 1120 IOD. While 1060 is enough till 4133/2067
> Tested it yesterday for 4220+ and 1160 IOD is purely bad. Instability hell
> You can run 1100 if you really desire, but that requires high procODT for high voltages
> High procODT = lower chance of ever hitting high FCLK
> Lower procODT = harder to balance dimm powering, but allows lower voltages & so better signal integrity
> 
> Let me handwire-reflash my board and i'll answer the mem requests.
> Tried crossflashing because ASRock ignores their B550 boards. Hardlocked myself on a gigabyte bios without usb boot ability haha
> 
> Questions asked here are double tripple answered
> Please scroll back at least 3-4 pages before asking the same answered question 😇
> EDIT:
> There is not one "correct" stepping
> You can run whatever you want, but keep the scaling consistent
> 40mV appears to be the lowest reasonable without AVX2 hardcrashes


Sorry for bothering you with this. But you said steps of 40mV. Got two questions

But can it also be like triple steps for the SOC (3x40)? example

SOC 1.1
VDDG CCD 0.940
VDDG IOD 0.980
CLDO VDDP 0.900

Soc seems to be stable 3800MHz at 1.06 SOC. But want to give it a little extra just make sure. Maybe 1.08 is better than going all the way to 1.1. But for 1.08 what should the rest be? example

SOC 1.08
VDDG CCD 0.920
VDDG IOD 0.960
CLDO VDDP 0.880


----------



## Sleepycat

nexxusty said:


> Your IOD is too high. Over 1.05V apparently can damage and degrade. Its also not within 40mv of SoC.
> 
> Fix that bro. ;-)


Then he won't be able to follow your advice of SOC of 1.2V, which means IOD has to be at 1.16V, which is definitely too high?

Personally, I'd just set VDDG IOD and VDDG CCD to 1.05V for both, CLDO VDDP to 0.95V, and then SOC to suit (I prefer to keep mine below 1.1V)


----------



## PowerK

Well.. decreased voltages further and end up with:
VSoC = 1050mV
VDDP = 900mV
VDDG CCD = 940mV
VDDG IOD = 980mV
vDIMM = 1.510V
Passed 10 cycles of TM5 1usmus_v3 preset. 
Perhaps, I can lower them further but I think I'll settle for now and run TM5 anta777 extreme preset overnight.


----------



## Veii

Soc can be high, it's just recommendation's because it mattered
But for people without errors, you can increase SOC as much as you like
I run for my experiments right now
880-900-940-1060-1260
CPU VDDP - cLDO_VDDP - CCD - IOD - SOC
(It's for 4146+ but couldn't be bothered to lower it when testing harsher timings @ low speed) 

There are unique by samples/CPUs which need more or less SOC
SOC substrate on its own loves voltage,
But the parts in there, don't at all
VDDG CCD hates voltage and IOD follows it's 12nm limits
CPU VDDP i haven't found the lowest limits, 880 was perfect, 900 runs oke'ish, but 930 stock is bad for anything beyond 2000Mhz

Just play with procODT & SOC till the combination leads the lowest latency on aida64
And balance your cores with curve optimizer and positive voltage (1X/2X scalar) ~ under cpu-z bench
(Also no CO and just -5/-25mV offset works too)

Lower proc is the main priority, but often +1 is needed, else the cpu slows itself down and eats 3-6ns

A variance of 0.3ns in aida64 between runs = instability/autocorrection.
It will keep varying if it really is unstable
A variance of 0.1ns, is just run to run variance

When you play with voltages & aida64 is consistent,
It has to pass these y-cruncher tests:
SFT, FFT, C19
SFT failure means too high TDC limit
FFT is VDDG/VDDP failure
(Also can be catastrophic mem timings ~ but TM5 should spill our error 6's and 0's if this is the case)
C19 is a very harsh AVX2 test which requires 75-100mV vDROOP (1.25 -> 1.18v)
It will crash if PBO is open or loadlines are too flat
First two tests will create the most heat and likely crash CTR presets


----------



## Joeking78

Veii said:


> Soc can be high, it's just recommendation's because it mattered
> But for people without errors, you can increase SOC as much as you like
> I run for my experiments right now
> 880-900-940-1060-1260
> CPU VDDP - cLDO_VDDP - CCD - IOD - SOC
> (It's for 4146+ but couldn't be bothered to lower it when testing harsher timings @ low speed)
> 
> There are unique by samples/CPUs which need more or less SOC
> SOC substrate on its own loves voltage,
> But the parts in there, don't at all
> VDDG CCD hates voltage and IOD follows it's 12nm limits
> CPU VDDP i haven't found the lowest limits, 880 was perfect, 900 runs oke'ish, but 930 stock is bad for anything beyond 2000Mhz
> 
> Just play with procODT & SOC till the combination leads the lowest latency on aida64
> And balance your cores with curve optimizer and positive voltage (1X/2X scalar) ~ under cpu-z bench
> (Also no CO and just -5/-25mV offset works too)
> 
> Lower proc is the main priority, but often +1 is needed, else the cpu slows itself down and eats 3-6ns
> 
> A variance of 0.3ns in aida64 between runs = instability/autocorrection.
> It will keep varying if it really is unstable
> A variance of 0.1ns, is just run to run variance
> 
> When you play with voltages & aida64 is consistent,
> It has to pass these y-cruncher tests:
> SFT, FFT, C19
> SFT failure means too high TDC limit
> FFT is VDDG/VDDP failure
> (Also can be catastrophic mem timings ~ but TM5 should spill our error 6's and 0's if this is the case)
> C19 is a very harsh AVX2 test which requires 75-100mV vDROOP (1.25 -> 1.18v)
> It will crash if PBO is open or loadlines are too flat
> First two tests will create the most heat and likely crash CTR presets


Interesting regarding ProcODT.

I dropped proc ODT from 40 to 34 in my regular 4000 C15 and finally got sub 50ns in Aida, before with higher procODT was hovering around 50.9-51.2.

Stability test image as previous procODT...should I stability test again after changing this value?

Going to apply the same logic to 4133.


----------



## Joeking78

Seems like 40 procODT is the sweet spot for 4133

34 procODT
Read - 60451
Write - 33085
Latency - 50.3

37 procODT
Read - 60894
Write - 33047
Latency - 50.3

43.6 procODT
Read - 60961
Write - 33160
Latency - 50.3

40 procODT
Read - 61320
Write - 33491
Latency - 49.8

40 proc ODT test just now almost identical to the results in Aida performed on the weekend.


----------



## YpsiNine

Veii said:


> Relaxing tRRD, tWTR is PCB dependent
> I don't have a good memory kit, and it helps to shift the delay there instead of elsewhere
> (My ICs are well, but if i want to daily 1.56v-1.65v, it needs specific taming else the PCB crashes at 1.52v - A0 PCB)
> 1-4-4-1-6-6 still functions better on Dual Rank, it's not only a 4 dimm thing
> But you need to test this closely with SiSoftware Sandra (Multi-Core Efficiency test) and maybe SuperPi 1.5 SX
> 
> Pushing tRRD to twice your value and running tFAW as 1* mode, for example is an option
> Couple of reasons to that, but it generally is required. The timings where borrowed from my 4200 set and are just easy to run
> If you want something tighter, you need higher VDIMM. Little change there would skyrocket your required VDIMM while tRFC is just low enough to be covered by this voltage. It would be a waste of heat
> This was the source of baseline timings
> 
> 
> Spoiler: Old low voltage Timings
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But i find the tCKE,Setup-Time, CAD_BUS method - a bit more stable for higher voltage
> (differences between them are just a "i figured it out later/finetuned it later" - time kind of thing)
> And yes , it clearly is used - but that's an 3 month old story by now
> Increasing vSOC is needed. 1060 IOD was just required for 2100 FCLK and scaled well down
> Soo i don't touch what isn't broken. WHEAs are annoying enough on their own already. Voltage testing takes too much time
> If you want it lower, move in 40mV steps from cLDO_VDDP
> CPU VDDP 880mV is required for higher FCLK - 930mV is the stock which is plain bad. 900mV works too but 880 is better (single and dual CCD)
> AMD max overclocking voltage this whole thread
> 
> DRAM Calculator at this point is old.
> "What works on Matisse works on Vermeer"
> Is kind of correct.
> But
> "What works on Vermeer, doesn't work on Matisse"
> is also correct
> This ones are just better for Vermeer
> 
> I just wish to have finally usable bioses with openFCLK
> Not the moved package throttle from 2100 down to 2000 , while barely anyone could move in the 4K area still. Shame-


Thank you for your continued support.

Yesterday I did a complete overhaul of my CPU CO settings (1C/2T P95 + OCCT torture) and that has given great results for my RAM progress.
So over night I finished a 3 hour 1usmus TM5 run all the way down at 1.36 VDIMM. Maybe these sticks aren't terrible after all...










Today I'm moving from 2T to 1T GDM OFF to see if I can get that stable. Shouldn't be a problem, looking good so far and still only on 1.36V.
And I've also moved from 1.1 to 1.075 V for SOC.

Here's a picture of my work in progress for 3733 CL16 1T GDM OFF, if you have any comments for the timings or ProcODT/RTT/DrvStr please feel free to chime in.
Mind you, this should preferably stay at max 1.4 VDIMM.










Then tomorrow I want to try to get some sort of good 3733 CL14 template applied to see if I can make it work, I don't mind going to around ~1.44 VDIMM for that.
CL14 should give quite a boost in games vs CL16. Shout if you have a good template for that.


----------



## BloodDivine

@Veii is there any y-cruncher test that shows vSoC instability?


----------



## Veii

YpsiNine said:


> Thank you for your continued support.
> 
> Yesterday I did a complete overhaul of my CPU CO settings (1C/2T P95 + OCCT torture) and that has given great results for my RAM progress.
> So over night I finished a 3 hour 1usmus TM5 run all the way down at 1.36 VDIMM. Maybe these sticks aren't terrible after all...
> 
> View attachment 2480934
> 
> 
> Today I'm moving from 2T to 1T GDM OFF to see if I can get that stable. Shouldn't be a problem, looking good so far and still only on 1.36V.
> And I've also moved from 1.1 to 1.075 V for SOC.
> 
> Here's a picture of my work in progress for 3733 CL16 1T GDM OFF, if you have any comments for the timings or ProcODT/RTT/DrvStr please feel free to chime in.
> Mind you, this should preferably stay at max 1.4 VDIMM.
> 
> View attachment 2480935
> 
> 
> Then tomorrow I want to try to get some sort of good 3733 CL14 template applied to see if I can make it work, I don't mind going to around ~1.44 VDIMM for that.
> CL14 should give quite a boost in games vs CL16. Shout if you have a good template for that.


That's probably already the lowest you can go , maaybe tRTP 6 could run 
Why can't you increase IOD a bit - for 3800MT/s ?
Maybe also tRDWR 11, tCWL 14 could run (maaybe if you have a tiny bit of reserves left)
But it could need tWR 16 - you have to try 


BloodDivine said:


> @Veii is there any y-cruncher test that shows vSoC instability?


Quite honestly, SOC is the whole chip 
And the whole chip does autocorrect continuously in the hidden
FFT crashes the IMC - but insufficient SOC will just result in higher latency and package throttle


----------



## BloodDivine

Veii said:


> Quite honestly, SOC is the whole chip
> And the whole chip does autocorrect continuously in the hidden
> FFT crashes the IMC - but insufficient SOC will just result in higher latency and package throttle


Thank you for your support, is there anything else besides Y-cruncher that can catch voltage instabilities on Zen+? Already run TM5 25 cycles and it came out without errors


----------



## Veii

BloodDivine said:


> Thank you for your support, is there anything else besides Y-cruncher that can catch voltage instabilities on Zen+? Already run TM5 25 cycles and it came out without errors


y-cruncher, all tests 4 loops is the norm (4* (2*9min))
autocorrection you can only catch with own research and testing.
I'm sorry, but there is no easy way. Vermeer is very hard to overclock
Package throttling happens even on stock. it's all about finetuning voltages.

Probably also this one Single core Prime95 test script for Zen 3 curve offset...
But y-cruncher is harsher than the typical p95 load's
OCCT Extreme 30min, might be an option - just y-cruncher again is harsher on the 48min loop (4 cycles, all selected tests)


----------



## YpsiNine

Veii said:


> That's probably already the lowest you can go , maaybe tRTP 6 could run
> Why can't you increase IOD a bit - for 3800MT/s ?
> Maybe also tRDWR 11, tCWL 14 could run (maaybe if you have a tiny bit of reserves left)
> But it could need tWR 16 - you have to try


I've tested with tRTP 6 and so far so good. Thanks for the tip.

I've done a few tries at 1900/3800 again with IOD up to 1060 mV, but the WHEA's are still there as soon as I start TM5. The system seems stable though, but I really don't like having them in the "background".
I also tried 1933/3866 just to see if there was a wall, but at this speed the system wouldn't even POST.


----------



## nexxusty

nexxusty said:


> Impressive bro, you have done your research.
> 
> I'm having trouble getting 3800mhz 14-14-14-30-1T (NO GDM) stable. I have it completely stable with GDM on. 20 hours of GSAT with a pass to verify that.
> 
> These sticks are 4x8gb B-Die (Patriot Viper 4400mhz). Right now I have my ProcODT set to 43.6, RttNom set to RZQ/7, RttWr set to Off, RttPark set to RZQ/5, MemAddrCmdSetup to 0, CsOdtSetup & CkeSetup are set to 0 as well. Finally my CAD_BUS settings are 24-20-24-24.
> 
> Any tips for a brother? Lol. I usually don't ask for help, however I've never delved this far into overclocking RAM. I'm quite positive my chip, RAM and Mobo can do this as it takes a minute or so for GSAT to throw an error. I've rarely had a setting I couldn't stabilize if it was quasi-usable already.
> 
> Thank you man!


@Veii 

Hate to be "that guy", lol, I didn't see an answer to my query, if you don't know, that's ok.

Or anyone else that knows, doesn't have to be Veil. I'll fill my time until then shooting for 2000mhz. Seems like C16 is what to shoot for. I can't see C16 2000mhz being that much better. 200mhz IF though.... Yeah, scratch that, it will be. C16 is pretty low for 2000mhz.


----------



## Bruizer

Could use some help.

I have a a 5900x and Dark Hero motherboard that I was running this RAM (F4-3200C14D-16GFX , Are you a human?) stable at 3600 safe timings w/ Geardown Disabled at 1.45v and 1.05 soc. It was 2x8, single rank, bdie, A1 pcb revision.









I tried to buy another set and run 4x8 but the system wasn't having it, even with higher soc. So, I bought this 2x16, dual rank, B1 pcb revision RAM kit (F4-3600C16D-32GTZR , Are you a human?) to settle my woes. But it really hasn't. First, I tried running the RAM at XMP. This required a bump up to 1.1v on the soc and 1.4v DRAM instead of the rated 1.35v. Then, in order to get the 3600 calc safe times, I had to bump voltage to 1.125 soc and 1.45v DRAM. So this is where I'm at.









I feel like the voltages are higher than they should have to be on the soc/vdimm. I updated the bios but no change. If I try lowering the vdimm to say 1.4v or the soc to 1.1v, OCCT after 10-30 minutes doesn't error, my computer just black screens (no blue screen) and restarts. Is there a setting I'm off on or did I just lose hard on the IMC lottery?


----------



## Veii

nexxusty said:


> Impressive bro, you have done your research.
> 
> I'm having trouble getting 3800mhz 14-14-14-30-1T (NO GDM) stable. I have it completely stable with GDM on. 20 hours of GSAT with a pass to verify that.
> 
> These sticks are 4x8gb B-Die (Patriot Viper 4400mhz). Right now I have my ProcODT set to 43.6, RttNom set to RZQ/7, RttWr set to Off, RttPark set to RZQ/5, MemAddrCmdSetup to 0, CsOdtSetup & CkeSetup are set to 0 as well. Finally my CAD_BUS settings are 24-20-24-24.
> 
> Any tips for a brother? Lol. I usually don't ask for help, however I've never delved this far into overclocking RAM. I'm quite positive my chip, RAM and Mobo can do this as it takes a minute or so for GSAT to throw an error. I've rarely had a setting I couldn't stabilize if it was quasi-usable already.
> 
> Thank you man!
> 
> 
> 
> 
> nexxusty said:
> 
> 
> 
> @Veii
> 
> Hate to be "that guy", lol, I didn't see an answer to my query, if you don't know, that's ok.
> 
> Or anyone else that knows, doesn't have to be Veii. I'll fill my time until then shooting for 2000mhz. Seems like C16 is what to shoot for. I can't see C16 2000mhz being that much better. 200mhz IF though.... Yeah, scratch that, it will be. C16 is pretty low for 2000mhz.
Click to expand...

That's not how asking / demanding , for help works 😇

you could have tried the RTT suggestions people post for dual rank/4 dimms, but you didn't
could try 2T over GDM, to spend your time getting your powering issues stable, didn't
could just browse through my old posts or overall this forum here, probably also didn't
Meanwhile i have to write the same thing over and over again
If you rush for a build, that's acceptable ~ but all the research is out there for free
Don't push that blame on me  ~ anywho

*>* 4400C19-19 Vipers are on a custom A2 PCB
*>* Daisy Chain splits the signal in 25/75%
*>* A2 PCBs need more current (ampere) to start functioning, soo as the loss on the slave set is higher, you should start to voltage bin them ~ and put the ones which work with less voltage, on the slave set
*>* You forgot to post a ZenTimings screenshot here, but i guess you run SD, DDs as 1-4-4-1-6-6 right ?
*>* ClkDrvStr needs to be higher if you want to use lower procODT. Lower procODT is required for high FCLK. 4x8/2x16GB need around 36.9ohm procODT, at worst 40. Lower it
*>* For GDM Off you'd need CAD_BUS somewhere near 40-20-30-20 or 60-20-40-20. 3rd value fixes memory training on Vermeer (slightly). Another option is: 40-20-20-20, tCKE 9, Setup Time 3-3-15 (3800, or tCKE 11 4-4-16 @ 4000+)
*>* While 3800C14 requires 1.48-1.56v, 4000C14 requires 1.62-1.67vDIMM.
*>* + 200MT/s = +1 tCL, +1 tRCD for the same latency, same strain @ same required voltage ~ just with higher throughput
*>* CPU VDDP needs to be 900 or 880Mhz for 2000+ to work.880mV for 2100+. cLDO_VDDP ≠ CPU VDDP
*> *use tRFC mini, always fill tRFC1/2/4, and set tWR as clean divider of tRFC and tRTP half of it
*> *follow tWR rule and tRC = tRAS+tRP for now , till you understand how to lower them by yourself (Baseline rules)

I think that's all you need to know.
You probably want to fix:

Memory Clear ~ Disable
Memory Interleaving ~ 256kb
Memory Address Hash ~ enabled
TSME ~ disabled
HW Prefetcher ~ both enabled
PHY Memory controller (DF -> DDR4 common options) PMU Pattern bits , manual ~ A (a/10 - it's in HEX) and both training options DFE, PME/PMU? ~ enabled
CPPC & CPPC Preferred cores, enabled (NBIO - SMU/XFR)
^ Inside AMD CBS

Keep MCLK =/= UCLK 1:1 , enabled in AMD OVERCLOCKING, Infinity fabric section ~ else you go into 1:1:2 mode


PowerK said:


> A question. Does tRRDL has to be tRRDS + 2 ??
> I set both at 4 and stability-wise, I see no problem. But if it has to be tRRDS+2 so the board/dimm auto-corrects it, there must a latency penalty.
> 
> Another question would be tWRRD. I have it at 2 with GDM1T setting. But with 2T, I cannot POST with tWRRD at 2. Hence I raised it to 4 for 2T. Any idea how I should bring it down to 2 for 2T?
> 
> Below is the timings I've settled on. Comments are welcome.
> View attachment 2480825


tRRD_L can be anything over tRRD_S.
But you might want to have tWTR_L = tRRD_L *2 for consistency
Sadly tWTR_L only goes up till 14

The cleanest way is +2, but you can lower it to +1 with tWTR_L 10 for example
Equalizing it, usually causes more problems - even tho it looks low.
You use SCL 2-2 , old rulesets for tWRRD where 4x X = tRCD_WR or lower than it
But X * SCL works too.
tWRRD delay will be needed once you lower tRDWR below (tRCD /2) +2.
It also will be needed if you go for tCWL ≠ tCL. This one is a Libra. You lower one by two, you have to increase the other by two. (Or by 1 if you trow in tWRRD delay)
The board doesn't touch tRRD and tWTR delays. But the memory does autocorrect tFAW if it's too high.
As for "too low" it did on Matisse/Renoir, but doesn't anymore on Vermeer/Cezanne

@Bruizer
DRAM Calculator is outdated at this point. Only the timings are very useful 
Check here for voltage examples
AMD max overclocking voltage (whole thread probably)
And focus on running 2T GDM Off with your timings (15-15-15)
RTT you can try 7/3/1 instead of 0/3/1, or 6/3/3
Also SD,DD 1-4-4-1-6-6 is for 2x dual rank / 4 dimms
(If you want to run my tCKE shenanigans, you need to match RTT & Setup Time. tCKE & CAD_BUS Setup Time, changes by MCLK)


----------



## nexxusty

Bruizer said:


> Could use some help.
> 
> I have a a 5900x and Dark Hero motherboard that I was running this RAM (Are you a human?) stable at 3600 safe timings w/ Geardown Disabled at 1.45v and 1.05 soc. It was 2x8, single rank, bdie, A1 pcb revision.
> View attachment 2480987
> 
> 
> I tried to buy another set and run 4x8 but the system wasn't having it, even with higher soc. So, I bought this 2x16, dual rank RAM kit (Are you a human?) to settle my woes. But it really hasn't. First, I tried running the RAM at XMP. This required a bump up to 1.1v on the soc and 1.4v DRAM instead of the rated 1.35v. Then, in order to get the 3600 calc safe times, I had to bump voltage to 1.125 soc and 1.45v DRAM. So this is where I'm at.
> View attachment 2480988
> 
> 
> I feel like the voltages are higher than they should have to be on the soc/vdimm. I updated the bios but no change. If I try lowering the vdimm to say 1.4v or the soc to 1.1v, OCCT after 10-30 minutes doesn't error, my computer just black screens (no blue screen) and restarts. Is there a setting I'm off on or did I just lose hard on the IMC lottery?


You just paid money to downgrade.... Why?

I don't understand.

This isn't a problem you can throw money at. I'm going to tell you that right now. You've got to spend the time brother.


Veii said:


> That's not how asking / demanding , for help works 😇
> 
> you could have tried the RTT suggestions people post for dual rank/4 dimms, but you didn't
> could try 2T over GDM, to spend your time getting your powering issues stable, didn't
> could just browse through my old posts or overall this forum here, probably also didn't
> Meanwhile i have to write the same thing over and over again
> If you rush for a build, that's acceptable ~ but all the research is out there for free
> Don't push that blame on me  ~ anywho
> 
> *>* 4400C19-19 Vipers are on a custom A2 PCB
> *>* Daisy Chain splits the signal in 25/75%
> *>* A2 PCBs need more current (ampere) to start functioning, soo as the loss on the slave set is higher, you should start to voltage bin them ~ and put the ones which work with less voltage, on the slave set
> *>* You forgot to post a ZenTimings screenshot here, but i guess you run SD, DDs as 1-4-4-1-6-6 right ?
> *>* ClkDrvStr needs to be higher if you want to use lower procODT. Lower procODT is required for high FCLK. 4x8/2x16GB need around 36.9ohm procODT, at worst 40. Lower it
> *>* For GDM Off you'd need CAD_BUS somewhere near 40-20-30-20 or 60-20-40-20. 3rd value fixes memory training on Vermeer (slightly). Another option is: 40-20-20-20, tCKE 9, Setup Time 3-3-15 (3800, or tCKE 11 4-4-16 @ 4000+)
> *>* While 3800C14 requires 1.48-1.56v, 4000C14 requires 1.62-1.67vDIMM.
> *>* + 200MT/s = +1 tCL, +1 tRCD for the same latency, same strain @ same required voltage ~ just with higher throughput
> *>* CPU VDDP needs to be 900 or 880Mhz for 2000+ to work.880mV for 2100+. cLDO_VDDP ≠ CPU VDDP
> *> *use tRFC mini, always fill tRFC1/2/4, and set tWR as clean divider of tRFC and tRTP half of it
> *> *follow tWR rule and tRC = tRAS+tRP for now , till you understand how to lower them by yourself (Baseline rules)
> 
> I think that's all you need to know.
> You probably want to fix:
> 
> Memory Clear ~ Disable
> Memory Interleaving ~ 256kb
> Memory Address Hash ~ enabled
> TSME ~ disabled
> HW Prefetcher ~ both enabled
> PHY Memory controller (DF -> DDR4 common options) PMU Pattern bits , manual ~ A (a/10 - it's in HEX) and both training options DFE, PME/PMU? ~ enabled
> CPPC & CPPC Preferred cores, enabled (NBIO - SMU/XFR)
> ^ Inside AMD CBS
> 
> Keep MCLK =/= UCLK 1:1 , enabled in AMD OVERCLOCKING, Infinity fabric section ~ else you go into 1:1:2 mode
> 
> tRRD_L can be anything over tRRD_S.
> But you might want to have tWTR_L = tRRD_L *2 for consistency
> Sadly tWTR_L only goes up till 14
> 
> The cleanest way is +2, but you can lower it to +1 with tWTR_L 10 for example
> Equalizing it, usually causes more problems - even tho it looks low.
> You use SCL 2-2 , old rulesets for tWRRD where 4x X = tRCD_WR or lower than it
> But X * SCL works too.
> tWRRD delay will be needed once you lower tRDWR below (tRCD /2) +2.
> It also will be needed if you go for tCWL ≠ tCL. This one is a Libra. You lower one by two, you have to increase the other by two. (Or by 1 if you trow in tWRRD delay)
> The board doesn't touch tRRD and tWTR delays. But the memory does autocorrect tFAW if it's too high.
> As for "too low" it did on Matisse/Renoir, but doesn't anymore on Vermeer/Cezanne
> 
> @Bruizer
> DRAM Calculator is outdated at this point. Only the timings are very useful
> Check here for voltage examples
> AMD max overclocking voltage (whole thread probably)
> And focus on running 2T GDM Off with your timings (15-15-15)
> RTT you can try 7/3/1 instead of 0/3/1, or 6/3/3
> Also SD,DD 1-4-4-1-6-6 is for 2x dual rank / 4 dimms
> (If you want to run my tCKE shenanigans, you need to match RTT & Setup Time. tCKE & CAD_BUS Setup Time, changes by MCLK)


Wow.

Thank you.

I have actually never asked for help in the 27 years I've been a tech geek. I just realized you knew much more than I did, and had already done the research.

I'm sorry if I came across like I expected help like an ass. Honestly, that was not my intention. I'd like to at least buy you a lunch or something for your trouble writing that man. I seriously appreciate it a lot. That was always my plan depending on the response.

One can always SAY they appreciate something done for them. I for one feel the need to SHOW it.



Cheers!

_edit_

I did browse a bunch of your responses. I will admit I gave up quickly and just asked instead. I'm willing to admit that.

Lol. Absolutely.

Added a ZenTimings screenshot as well. I am/was running SD, DD's at 1-5-5-1-7-7. They have been changed now accordingly. So far, no luck, however I haven't tried all combinations.

I think my RTT's are causing issues. So far the suggestions I've tried act the exact same stability wise. To me that seems like its something else set incorrectly. Trying with ProcODT @ 36.9 too.

Thanks brother!


----------



## Bruizer

Veii said:


> DRAM Calculator is outdated at this point. Only the timings are very useful
> Check here for voltage examples
> AMD max overclocking voltage (whole thread probably)
> And focus on running 2T GDM Off with your timings (15-15-15)
> RTT you can try 7/3/1 instead of 0/3/1, or 6/3/3
> Also SD,DD 1-4-4-1-6-6 is for 2x dual rank / 4 dimms
> (If you want to run my tCKE shenanigans, you need to match RTT & Setup Time. tCKE & CAD_BUS Setup Time, changes by MCLK)


Thank you! I'll give your suggestions a whirl!



nexxusty said:


> You just paid money to downgrade.... Why?
> 
> I don't understand.
> 
> This isn't a problem you can throw money at. I'm going to tell you that right now.


One is a single rank 16gb B-die kit rated for 3200 cl14 @1.35v. The other is a dual rank 32gb b-die kit rated for 3600 cl16 @1.35v. I initially bought another kit of the first set but 4x8 is harder on the controller. So I bought the second kit. Based off everything I read, they seemed close to equal and more like a side grade that in theory should have made it easier for me to run 32gb @3600 with tight timings.


----------



## nexxusty

Bruizer said:


> Thank you! I'll give your suggestions a whirl!
> 
> 
> 
> One is a single rank 16gb B-die kit rated for 3200 cl14 @1.35v. The other is a dual rank 32gb b-die kit rated for 3600 cl16 @1.35v. I initially bought another kit of the first set but 4x8 is harder on the controller. So I bought the second kit. Based off everything I read, they seemed close to equal and more like a side grade that in theory should have made it easier for me to run 32gb @3600 with tight timings.


AFAIK 3600mhz C16 is worse binned B-Die than 3200mhz C14.

Also, 4x8 is not hard to stabilize if you're willing to put in a bit of time. I stabilized 3800mhz CL14 in a matter of hours once I found the right timings. I started with DRAM Calc and went from there. I'm no n00b, however I'm not an l33t RAM overclocker either. It was honestly quite easy. What could be considered hard is 3800CL14 1T GDM off.

Which is what I am shooting for now.

I literally JUST found settings that doesn't immediately reboot my system after Windows 10 loads, or immediately give me errors in Google Stress App Test. 600 seconds and it's still running.

What's astonishing... Is how little margin for error I had getting here. I haven't changed much from 3800 CL14 GDM ON. I believe I changed ProcODT from 43.6 to 40, RTT's to 7/3/1 from 7/0/1, specifically set ClkDrvStr and the like to Auto, and left CAD_BUS at 24-20-24-24. I honestly cannot believe there is this much progress.


I added 2x50mm cooling fans so I could use 1.5v+ 24/7 without worry, the problem is... I'm not sure which setting attained stability.

Usually I am too happy to even bother testing and just enjoy it. This ends up with no real lessons learned. I very much so want to learn more of the inner workings of RAM.

I'll post my new ZenTimings once this passes 2 hours of GSAT. This is a gaming machine, so I usually only test with GSAT, so far anything that can run GSAT can run games without any issues, and its not like GSAT is a weak test or anything. I just have issues with anita777 TM5 configuration just stopping. Even on stock settings.


----------



## PowerK

GSAT is all right. But It's very memory focused. This was the purpose Google made it for QA newly imported memory modules for their server.
It does not hit cache, IMC and/or FLCK hard enough. GSAT is good when troubleshooting to see if ruling out memory is ok or not.


----------



## nexxusty

PowerK said:


> GSAT is all right. But It's very memory focused. This was the purpose Google made it for QA newly imported memory modules for their server.
> It does not hit cache, IMC and/or FLCK hard enough. GSAT is good when troubleshooting to see if ruling out memory is ok or not.



Good to know.

I am positive my IMC is a good one, FCLK is stable at 1900 for sure.

I'll toss a TM5 test in there for good measure though.

Appreciate the advice.


----------



## Veii

nexxusty said:


> I'm sorry if I came across like I expected help like an ass. Honestly, that was not my intention. I'd like to at least buy you a lunch or something for your trouble writing that man. I seriously appreciate it a lot. That was always my plan depending on the response.
> 
> One can always SAY they appreciate something done for them. I for one feel the need to SHOW it.
> 
> 
> 
> Cheers!


I don't do this for money ~ would lose the fun that way. Strongly dislike researching "for" money
Just browse around, really - this forum has soo much information spread 


> I did browse a bunch of your responses. I will admit I gave up quickly and just asked instead. I'm willing to admit that.
> Lol. Absolutely.
> Added a ZenTimings screenshot as well. I am/was running SD, DD's at 1-5-5-1-7-7. They have been changed now accordingly. So far, no luck, however I haven't tried all combinations.
> 
> I think my RTT's are causing issues. So far the suggestions I've tried act the exact same stability wise. To me that seems like its something else set incorrectly. Trying with ProcODT @ 36.9 too.
> 
> Thanks brother!


On the tCKE part, you have to be very cautious
I'm not 100% happy with them for 4 dimm setups, but for 2 dimm setups or dual rank (nearly equal in the requirements)
they should be fine

On 4 dimm setups, (4xA2 was usually pure hell to work with on daisy chain)
They can cause random reboots , if something is a tiny bit off
This would mean the bottom 3 PHY "delay" timings
On your example they look better than from most people. MSI boards usually use these

One thing to note 
RTT values are termination impedances, they are listed as impedance values and the ohm/ampere/votlage math applies here
But in reality are used as "cut off resistances" , termination resistances
You want to have less here - IF you push high voltage
High means 1.52+
Memory is not sillicon which can degrade, but the caps can overcharge and die. Mostly it happens by load, by heat or at best the PCB just hardcrashes (most likely event you'll encounter)

If you research the ohm to ampere rule, you can see that mostly trowing voltage at something @ low impendance is not a good idea
SOC behaves very similar here
The key on memOC is to keep signal integrity up.
You have X voltage send out from the chip as procODT impedance ~ which multiplies it's end Ampere that arrives
(the higher the procODT impedance the easier high capacity dimms can be powered / part of the story)

Memory has RTT values as termination impedance for CKE (clock signal) high and low and dynamic termination ~ which is then RTT_WR
RTT_Park often goes as the strongest value. See it as the main dataline "signal chopper". The donkey which keeps on pushing the cart - step by step
Without a push, the signal won't move upwards and without a "wall or reflection" it won't fall downwards and make a nice sinus curve

A good sinus curve is consistent, and this sinus curve / frequency changes and increases in density but also in noise ~ the higher you go with on MCLK


Spoiler














Too high RTT values, will cause the signal to reflect back and is the most common issue when OCing memory or "training memory"
Bad training values will set the borders wrongly, too high VDIMM will overshoot
Soo each RTT value has their "voltage range"

0/X/X usually are ment for low voltage scenarios, they provide the cleanest signal integrity but have the least dampening
They are also the most damaging, because high voltage will nearly always crash the PCB near 1.51ish vDIMM
Then comes 7/X/X (735 DR / 705 SR)
These ones have a very high starting point of near 1.46-1.48v as minimum voltage, but their can power harsh PCBs like A2 or A3. Overall are stronger but the cut-off point is set too harsh, soo you need a strong voltage to begin with

633 DR / 706 SR
Are a bit of a mixed bag
The 2nd value (RTT_WR) enables dynamic on-die termination ~ but that's another huge topic of probably 2 pages or 3 big posts

If you want to spend the time translating and diving deeper into this rabbit hole
This page has all the information collected - between A, B, C, (D) threads








쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네


출처 Veii 님https://www.overclock.net/forum/28385690-post3279.htmlhttps://www.overclock.net/forum/28385



coolenjoy.net




Google is not good with korean language, bing / yandex do a far better job - just try 








Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com




This tool exists, but it's hard to use and requires the user to know what to select
Soo i suggest to go the harder way and check the KR link above 
Only use the DOCS for error meaning checking








OC'ing T-Force 4133 cl18


I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...




www.overclock.net




This thread has another piece of information (KR link should list it too) with voltage stepping and a further down bellow a TM5 with 20 cycles 1usmus_v3 preset preselected


Spoiler: Visualized Example














This looks like a mess to be honest ~ i can't pull every information in one post 
Purple & sky blue = baselines ~ always working baselines

Green is advanced, as you usually use tRRD_S * 4 = tFAW
(Forth Activate Time window ~ more than 4* is timebroken by the memory and wastes latency)

tRC higher than tRAS+tRP, wastes latency and hides issues
tRDWR higher than the math, hides issues
Higher SD, DD add performance, but can cut into other timings - only works on 1x tFAW mode = tRRD_L or min 1x tRRD_S

tCKE , RTT , CAD_BUS are the main things you should focus on with any timings
If they increase performance, then you did something wrong before
If they don't do anything , then you are not on the limits of your DIMM PCBs
They help, but only work if are correct - focus on 쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네 if you want to be perfectly accurate (expert, else follow it blindly)
tCKE 9 range works till 4066 without breaking, 4133 as expections
4000+ likes tCKE 11, 4-4-18 more

CAD_BUS 40-20-20-20 or 60-20-20-20, is your clean foundation for providing dimms with enough current (ampere)
X-20-20-20 are low, very low - they only work if you control the SETUP Time delays accurately
Else
X-20-Y-20, / Y > 30 is needed to prevent post issues, as memory training is a mess since AGESA 1.1.0.0 Patch C
* it helps a tiny tiny bit, but it helps. Without it only 1/8 times 3800CL14-14 posts for me on Patch C 
** But setup timings do the magic work ~ most of it 

Overall to short it down

you need ClkDrvStr to power the dimms without GDM (thanks 1usmus for the early pointed research)
X-20-20-20 is advanced and needs full-control, wrong settings will cause all sorts of funkiness
too high ClkDrvStr will cause the PCB to crash or optimally just not post at all
too low tRDWR values will prevent you to post
Dual Rank and 4 dimms need tWRRD neverless of the timings working method
there is not only "one" correct method, every overclocker has own tricks. Memory timings are optimized to dataset sizes. For this you use SiSoftware Sandra, Multi-Core Efficiency test (detailed view) to offline! compare your personal results
Aida64 variance of 0.3ns between many tests is instability and autocorrection. You only care about hitting the same consistent latency ~ for anything else Aida64 remains a personal compare tool, nothing more 
CPU-Z Benchmark, is a very fast way to verify if cores are clock stretching or not / use it to work with global voltage offsets
Increase EDC limit slightly, as memory falls into the boosting-powerreserves. Verify stock limits with y-cruncher & HWInfo. PPT (W) ,TDC (A) ,EDC (A) Limit % == 100% 

Good luck and success 
Don't fear to push high voltages, but you have to pick with what RTT values you start with to build your foundation


Spoiler: Very Easy 4xA2 Foundation ~ for FCLK testing












Credits DJMarkBravo ~ timings me? i guess





Spoiler: 1.52v 1x tFAW Model / 2x 16GB












Credits Bloax
inspired by psone [Chiphell]





Spoiler: 2x 8GB near 1.6vDIMM / tFAW 1x












Personal Shenanigan's, back to the drawing board @ stock 4.65Ghz


----------



## PowerK

Thanks, Veii

*@nexxusty, *is 1T even possible with 4 sticks on this daisy chain DIMM setup? I haven't even tried.


----------



## PowerK

Guys, which is correct between these two formula? I've searched around and all I get is contradicting opinions rather than a fact.
1. tWR = tRRDS x tWTRS
or
2. tWR = 2 x tRTP

I have tRTP at 6, tRRDS at 4 and tWTRS at 4.
So,
1. 4 x 4 = *16* = tWR
2. 2 x 6 = *12* = tWR

if 1 & 2 are mutually correct, then I need to have tRTP at 8 then? This means tRFI needs to be changed, too. Because tRFI = tRC x tRTP.
or.. have either of tRRDS or tWRTS at 2. Hmm..


----------



## PowerK

Guys.. where are you?
North/South America and Europe! Wake up! It's your time. And I'm going to bed. :-D
Good night to Aussies, too.


----------



## nexxusty

PowerK said:


> Thanks, Veii
> 
> *@nexxusty, *is 1T even possible with 4 sticks on this daisy chain DIMM setup? I haven't even tried.


According to Veil it is, but very hard. He described it as "Hell", lol.

I am beginning to understand why too. His extremely thoughtful and thorough explanation in his last post will explain why if you care to read it.

Essentially, with Daisy Chain, the amperage is 25/75 for channels A & B respectively. This is why it's so hard to stabilize because you have to account for that with CAD_BUS and RTT values, and one timing, TCKE. This is also why he mentioned voltage binning my PCB's as the PCB's that will require less voltage will do better on the B channel. Makes perfect sense.

Lol, I'm never up this early usually. Had to take my pup in for grooming, so I am up. Took him for a walk and was beautiful out, and I feel energetic now. I think morning walks and me need to be acquainted better.

@Veil, responding to your post after this. It requires more than a quote I feel. Hehe.


----------



## Veii

PowerK said:


> Guys, which is correct between these two formula? I've searched around and all I get is contradicting opinions rather than a fact.
> 1. tWR = tRRDS x tWTRS
> or
> 2. tWR = 2 x tRTP
> 
> I have tRTP at 6, tRRDS at 4 and tWTRS at 4.
> So,
> 1. 4 x 4 = *16* = tWR
> 2. 2 x 6 = *12* = tWR
> 
> if 1 & 2 are mutually correct, then I need to have tRTP at 8 then? This means tRFI needs to be changed, too. Because tRFI = tRC x tRTP.
> or.. have either of tRRDS or tWRTS at 2. Hmm..


Non 
Rulesets = only correct answer , is "non"
Too many "it depends" points.

1 is clearly wrong
it should be tRRD_S *+ *tWTR_S
but this is not correct either. Other timings depend on this and never "only one" operation happens at the same time
The stack of operations is 5-6 rows "at the same time" ~ it's all about what you schedule together with what
And there is where "my" rulesets come from.
They have no technical ground *

* They do have technical education, as much as i could look, test, verify, read and try again ~ do as a one man army without support.

tREFI not tRFI - is automatically set on AMD by frequency and timings - and a lot around it
tRCPAGE = tMAW.MAC , is the closest one relating to tREFI on AMD , but we do not short REFI time window ~ we work with tRFC

tWR has many many "potentially" possible methods do be used
at least 5 of them you probably saw on the community calculator docs
And yet, following technical JEDEC rule for "one instruction" is still not the way to go.
As again "a lot happens at the same time and varies up to dataset size"

tRRD_ & tWTR_
Even tho guides look and spread the same thing, as being connected
They are not fully. They do have a link (can have a link, sorry)
But they have non and are split from each other.
You will get to know how to match them, once they are off ~ while the minimum and maximum range of them depends on other timings and way of calculation or "working method"

DDR4 is not running as PAM4, to use X multiplied by Y, method
It's added, subtracted, or running in integers of multiple
But it's neither PAM4 nor Quantum Computing to run in "multiplied by itself" values

Soo again while i do try to work with integer rules creating connected points, and other overclockers work with minimum till crash values
Not always is lower better, nor is one rule "absolute"
As it will always depend on the optimization around it ~ because memory is dynamic and the timings you can change as user are half of what really goes on in the hidden.

Try, confirm results, test a lot, note, learn and make your own rules
Following it blindly, is jumping from one rabbit hole to another 🐇


----------



## Veii

nexxusty said:


> According to Veil it is, but very hard. He described it as "Hell", lol.
> 
> I am beginning to understand why too. His extremely thoughtful and thorough explanation in his last post will explain why if you care to read it.
> 
> Essentially, with Daisy Chain, the amperage is 25/75 for channels A & B respectively. This is why it's so hard to stabilize because you have to account for that with CAD_BUS and RTT values, and one timing, TCKE.
> 
> @Veil, responding to your post after this. It requires more than a quote I feel. Hehe.


who is this Veil i keep reading ?

It was hell before digging the RTT rabbit hole
Now it's less bad and actually possible - but still very unfortunate and not optimal 
Mixing PCB revisions for different locations is a better method ~ than driving min-max survive voltages
(keeping the slave set alive,while trying not to overvolt the main set at the same time)


----------



## Yviena

@Veii wait so CAD_BUS 40-20-20-20 is fine with TCKE at 11 4-4-16 at 2000mhz FLCK, or can i still use xx-20-30-20?


----------



## Veii

Yviena said:


> @Veii wait so CAD_BUS 40-20-20-20 is fine with TCKE at 11 4-4-16 at 2000mhz FLCK, or can i still use xx-20-30-20?


SETUP Timings, need X-20-20-20 , they are low termination impedances, as the setup "time" controls when the cut has to happen
You wont need fixed impedance to do a cut 

tCKE can be used neverless of the CAD_BUS state
but it depends on the RTT values
both control the powerdown mode , but from different aspects and sides

SETUP time method, is more accurate and has better finecontrol
but if you get no good result, just use the old 40-20-30-20 or 60-20-40-20 , or even 60-20-20-24 CAD_BUS option 

Both methods work, but X-20-20-20 with setup time, is more accurate


----------



## Bruizer

@Veii

So I took your advise and turned off GDM dropping to 2T, changed to 7/3/1, and lowered voltage on the SOC to 1.075 (from 1.125) and...STABLE! Haven't had time to test other voltages. Still 1.45vdimm. Any additional thoughts on timings or other things I might change/try? I'm at like 58 latency. Would really just like to focus on timings unless its just stupid for me not to try 3733 or higher.


----------



## Veii

Bruizer said:


> @Veii
> 
> So I took your advise and turned off GDM dropping to 2T, changed to 7/3/1, and lowered voltage on the SOC to 1.075 (from 1.125) and...STABLE! Haven't had time to test other voltages. Still 1.45vdimm. Any additional thoughts on timings or other things I might change/try? I'm at like 58 latency. Would really just like to focus on timings unless its just stupid for me not to try 3733 or higher.
> 
> View attachment 2481046


tRC 45, adjust tRFC correspondingly
If it causes issues and errors - then you hide timing issues with high tRC 
SD, DD's 1-4-4-1-6-6

You changed only RTTs,
Pretty much did nothing, as proc is too high - CAD_BUS is bad (24-20-24-24) is the minimum you should run
24-24-24-24 is a zen 1 thing but even there 24-20-20-24 provides better signal integrity

High latency can be because of many things. Vermeer is a dynamic system
At least tRDWR and tWRRD look fine now

Before going tFAW that low, start with tRRD_S * 4
Which currently are a bit too high (tRRD & tWTR both)









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


That's probably already the lowest you can go , maaybe tRTP 6 could run Why can't you increase IOD a bit - for 3800MT/s ? Maybe also tRDWR 11, tCWL 14 could run (maaybe if you have a tiny bit of reserves left) But it could need tWR 16 - you have to try I've tested with tRTP 6 and so far so...




www.overclock.net




Bottom had preset examples. I see no issue just reusing them and later lowering stuff step by step
If you can't hit 3733 , then something is significantly wrong on your setup
Could also be oxidized traces/gold-contacts on the dimms which need cleaning once


----------



## domdtxdissar

_I have done some testing on a Norwegian forum in regards to T1 GDM vs T2, and Veii bus timings vs standard bus timings. Guess i can share them here also, make of them what you want.


AMD Zen 3 (Ryzen 5xxx)


(Since iam lazy i have just used a translator to translate the text into english)

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------_

"This took much longer than expected, so i'm tired of running benchmarks in SotTR now.. 
If someone is not happy with the data collected, want other settings, bench in something else etc etc -> you are free to collect data yourself and share with the rest of us.

If i were to change anything, I might go for a restart between each run as the numbers change a bit between each restart it looks like ..









Benched in SotTR @ 1080 medium settings, all collected data is "CPU Game" numbers
Static OC 4.4ghz allcore
SMT off
T2:
253fps average, 184fps 95%, 174fps min
251fps average, 183fps 95%, 176fps min
249fps average, 179fps 95%, 171fps min
251fps average, 180fps 95%, 173fps min
254fps average, 184fps 95%, 173fps min
_reboot_

T1 GDM:
240fps average, 174fps 95%, 168fps min
235fps average, 175fps 95%, 166fps min
237fps average, 172fps 95%, 164fps min
237fps average, 177fps 95%, 167fps min
235fps average, 176fps 95%, 170fps min
_reboot_

T2:
240fps average, 175fps 95%, 170fps min
241fps average, 179fps 95%, 170fps min
248fps average, 181fps 95%, 170fps min
_restart SotTR_
252fps average, 182fps 95%, 173fps min
253fps average, 184fps 95%, 178fps min
_reboot_

T1 GDM:
247fps average, 180fps 95%, 173fps min
246fps average, 183fps 95%, 171fps min
241fps average, 179fps 95%, 167fps min
_restart SotTR_
249fps average, 176fps 95%, 168fps min
250fps average, 185fps 95%, 176fps min
248fps average, 180fps 95%, 169fps min (bonus run since last was T1 GDM's first over 250 average)
252fps average, 182fps 95%, 169fps min (bonus 2)
239fps average, 173fps 95%, 165fps min (bonus 3)
_reboot_

T2 =


Average average-fps = 249.2 fps
Average 95% lows = 182.1 fps
Average minimums = 172.8 fps


T1 GDM =


Average average-fps = 242.7 fps
Average 95% lows = 177.8 fps
Average minimums = 168.7 fps
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------










Benched in SotTR @ 1080 medium settings, all collected data is "CPU Game" numbers
Static OC 4.4ghz allcore
SMT off
T2:
257fps average, 184fps 95%, 176fps min
258fps average, 184fps 95%, 179fps min
254fps average, 185fps 95%, 173fps min
252fps average, 183fps 95%, 177fps min
251fps average, 181fps 95%, 169fps min

_reboot_

T1 GDM:
260fps average, 189fps 95%, 178fps min
258fps average, 193fps 95%, 183fps min
258fps average, 187fps 95%, 179fps min
258fps average, 189fps 95%, 176fps min
252fps average, 181fps 95%, 176fps min

_reboot_

T2:
257fps average, 190fps 95%, 181fps min
259fps average, 187fps 95%, 173fps min
251fps average, 180fps 95%, 169fps min
255fps average, 184fps 95%, 177fps min
253fps average, 182fps 95%, 173fps min

_reboot_

T1 GDM:
248fps average, 181fps 95%, 175fps min
247fps average, 180fps 95%, 165fps min
244fps average, 179fps 95%, 168fps min
245fps average, 177fps 95%, 166fps min
252fps average, 180fps 95%, 167fps min
245fps average, 178fps 95%, 171fps min (bonus run since sudden spike to 252, not counted)

_reboot_

T2 =


Average average-fps = 254.7 fps
Average 95% lows = 184 fps
Average minimums = 174.7 fps
T1 GDM =


Average average-fps = 252.2 fps
Average 95% lows = 183.6 fps
Average minimums = 173.3 fps
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Dram calculator bench


Static OC 4.4ghz allcore
Booted in windows safe mode
Dram calc "default" benchmark based on memtest used.
Same memory settings, only difference is T2 vs T1GDM
All recorded numbers are in seconds
*T2:*
194,81
193,23
193,40
193,50
192,87
193,36

Average = 193,52833 sec

*T1 GDM:*
194,64
193,39
193,56
193,53
192,89
194,14 (outlier, data not used)
193,66

Average = 193,61166 sec

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

My conclusion is that it dont really matter if you use T2 or T1 GDM for the overall game performance as the run to run variance difference is greater than the "performance difference", as long as you dont hunt for the last 0.1 to 0.3 ns in the AIDA64 latency bench.

But I notice that T1 GDM has the highest achieved results both in average fps, 95%'s and minimum's .. Hard to say if this is run to run differences or if GDM actually has higher potential "when the stars align" 

Veii's bus timings are not recommended at all for my 4x8gigs setup, but if you decide to use them, then T2 is much faster than T1 GDM."


----------



## GribblyStick

OK, I'm pretty confused at this point.
I came in herein an attempt to understand why my system throws no errors at 4000/2000 but becomes super slow.
Now I'm seeing things contradicting pretty much everything I thought I knew lol.
Sooo, Let's try something else then.

I don't want to break records, I just want to get the best safe daily settings.
Now I'm no longer sure what safe is? Am I getting this right (for safe dailying)?
IOD needs to be within 40mv ideally of SOC, that would mean SOC is limited to no more than 1,090 V because IOD shouldn't go above 1,050 V
This would put my max clock at 3800 following Veiis min specs (or slightly above):


Spoiler: Min Soc voltages



Minimum Requirements of VSOC mV @ Frequency

3200 - 980-1000mV
3400 - <1040mV
3600 - <1060mV
3800 - <1075mV
4000 - <1137,5mV
4067 - 1165-1200mV
4200 - 1187,5-1225mV
maximum being 1300mV, while 2100 defaults to 1250mV SOC.


And this while attempting to drive down proc ODT as much as possible for better latencies.
And whatever gives the best results between 1/2T and GDM ON/OFF for my kit.

But then I'm also seeing Veii talk about soc 1260 and IOD now where near within 40mv...meaning 1,2 SOC max could be fine too and thus by extension 4000 ?


----------



## domdtxdissar

Try to understand what Veii have actually said:



GribblyStick said:


> IOD needs to be within 40mv ideally of SOC, that would mean SOC is limited to no more than 1,090 V because IOD shouldn't go above 1,050 V


No, the gap between IOD and SOC can *minimum* be 50mv

Soc @ 1.15v and IOD @ 1.05v(1.06v) is fine, and it can even be recommended as a starting point for basic tweaking



GribblyStick said:


> Min Soc voltages"]Minimum Requirements of VSOC mV @ Frequency
> 
> 3200 - 980-1000mV
> 3400 - <1040mV
> 3600 - <1060mV
> 3800 - <1075mV
> 4000 - <1137,5mV
> 4067 - 1165-1200mV
> 4200 - 1187,5-1225mV
> maximum being 1300mV, while 2100 defaults to 1250mV SOC.


Run whatever voltages you want, values above are only *minimum voltage* recommendations he tested and know to work for his own setup and likely 90% of the zen3 systems out there.

I realize you didn't ask me, but in my opinion these voltages can be used a simple 1900:3800 baseline for when you start to tweak your memory settings. (later you try to work your way down on the voltage ladder as the cpu/soc scale with lower VDDG, CLDO_VDDP and VDDP voltage)

SOC @ 1.125v
VDDG IOD @ 1.05/1.06v
VDDG CCD @ 0.92/0.94v
CLDO_VDDP @ 0.88/0.9v
VDDP @ 0.88/0.9v

When you say system throw no error @ 2000:4000, do you mean memory error or whea error ?

And you dont HAVE to follow the suggested "40mv stepping", i get best results with both VDDG CCD and CLDO_VDDP @ 0.88v.
Almost nothing is written in stone for memory tweaking voltages... Below is on example from a SotTR benchmark thread on a other forum (These are unstable settings and dont try to copy them)








CLDO_VDDP @ 0.75v
tRFC under 120ns o_0

Still i won with "CPU Game" average 284fps in SotTR


----------



## GribblyStick

I appreciate any answers 
Minimum makes more sense, thanks. but the 1,050 thing is still the max recommended for IOD then?

As for the 2000 FLCK thing, I mean it boots, not seeing any errors.TM5 runs for around 10 minutes with no error at all, then the system reboots.
All that time it's slow, even in bios, like extremely slow. At the moment of restart I get a single WHEA error, but none when using the system, although it's not like I did any kind of extensive testing given the slowness was a dead give away that SOMETHING was wrong.


----------



## domdtxdissar

GribblyStick said:


> I appreciate any answers
> Minimum makes more sense, thanks. but the 1,050 thing is still the max recommended for IOD then?
> 
> As for the 2000 FLCK thing, I mean it boots, not seeing any errors.TM5 runs for around 10 minutes with no error at all, then the system reboots.
> All that time it's slow, even in bios, like extremely slow. At the moment of restart I get a single WHEA error, but none when using the system, although it's not like I did any kind of extensive testing given the slowness was a dead give away that SOMETHING was wrong.


Why do you want to be above 1.05v VDDG IOD ?
As a basic rule of thumb, stick under 1.06v IOD before you know what your doing, and have finished your baseline memory overclock.
You can compare the settings/voltages other people use here: Zen RAM Overclocking

I dont know what setup you are running, but getting 2000:4000 stable is hard, and its even harder if you use 32gigs memory, and its very very hard if you use 4x8 sticks and its very very very if you have 4x8 sticks + a dual CCX CPU (5900/5950) 

Suggest starting at 1900:3800 and tune voltages and timings before you try to work your way up to 2000:4000.


----------



## GribblyStick

don't need to be above 1,05, just want to know what my limits are before I inadvertently fry something.

That page is what I was comparing to, to get an idea. Currently I'm running the auto docp settings it gave me for 4000, but at 3800, just ever so slightly tightened because RFC & RC were set really high. Oddly enough I had to increase soc/procodt over the auto settings when I entered the same numbers manually (although now I'm thinking that might have been the wrong reflex):


Spoiler: unmodified DOCP with GDM forced on and 1T















The intent not being on optimizing 3800 yet but figuring out why 4000 was acting up. Just didn't know where to start debugging yet.
My understanding was that that basically, more voltage was needed for higher frequencies and that might require higher odt, so I just would just bump those up whenever something blocked.
And maybe try a different set of RTT, but since it booted and didn't throw any immediate errors, I was stumped as to why it would run so slow. I figured that if it was that unstable I would see something during memory testing. As in errors showing up under 2 minutes, but that wasn't the case.

And the settings look similar to what other people have gotten, only looser. I'm going to try again this weekend, but play more with the voltages, see what happens.


----------



## BarrettDotFifty

I see less and less people mentioning WHEAs in this thread lately, especially considering that most people posting their overclocks are using Vermeer CPUs. Did I miss a workaround for addressing CPU/bus interconnect WHEAs at 1900 FCLK and above? I'm running a 5900X with a pair of 2x16GB dual-rank B-die and can't figure out a way around these errors above 1900 FCLK. Errors start popping up in HWinfo seconds after running TM5 stress tests.


----------



## jomama22

BarrettDotFifty said:


> I see less and less people mentioning WHEAs in this thread lately, especially considering that most people posting their overclocks are using Vermeer CPUs. Did I miss a workaround for addressing CPU/bus interconnect WHEAs at 1900 FCLK and above? I'm running a 5900X with a pair of 2x16GB dual-rank B-die and can't figure out a way around these errors above 1900 FCLK. Errors start popping up in HWinfo seconds after running TM5 stress tests.


I think you just have more people who have decided to stay at what's stable for them as genuinely, the gains from going above 1900/3800 are quite marginal it the grand scheme of things. There are more worthwhile ways to expend energy then trying to gain 1-2% overall using memory overclocking on amd. Getting better clock speeds on the cores will always be a better endgame then trying for 100-200+ mhz on the fclock/memclock.

It should be noted that if you use pbo, higher soc voltages will reduce your max pbo clock. So if you need to throw .1-.2v more just to squeeze out 1ms of latency or increase fclock, your pbo overclock will suffer.


----------



## thigobr

Regarding FCLK I posted on the MB topic, re-posting here:

I was struggling to get 1900MHz FCLK without WHEA until I tried lowering ProcODT. I was settling for 1866/3733MHz 24x7 but ever now and then I try to fiddle with 1900MHz

Even on stock settings (SPD on this Crucial is 2666MHz CL19-19-19) the BIOS was setting it to 60ohm.

Using 0.900V / 0.950V / 0.990V/ 1.100V cldo_VDDP/VDDG CCD/VDDG IOD/vSOC and just overclocking the FCLK async to 1900MHz (memory/uclk at 1333MHz) it was almost stable getting 1~2 WHEA errors per hour on y-cruncher or OCCT. Then I lowered ProcODT to 34ohm and then I left y-cruncher running with no WHEA errors! I then increased memory to 3800MHz 1:1:1 using ProcODT 36ohm now, passed 5h of y-cruncher so far without WHEA.

Anybody has similar experience? I will monitor the system for longer but it's already more stable than before... I had no idea ProcODT could help even when trying to increase FCLK async.

View attachment 2481090
View attachment 2481091


----------



## craxton

domdtxdissar said:


> Dram calculator bench
> 
> 
> Static OC 4.4ghz allcore
> Booted in windows safe mode
> Dram calc "default" benchmark based on memtest used.
> Same memory settings, only difference is T2 vs T1GDM
> All recorded numbers are in seconds
> *T2:*
> 194,81
> 193,23
> 193,40
> 193,50
> 192,87
> 193,36
> 
> Average = 193,52833 sec
> 
> *T1 GDM:*
> 194,64
> 193,39
> 193,56
> 193,53
> 192,89
> 194,14 (outlier, data not used)
> 193,66
> 
> Average = 193,61166 sec
> 
> --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> 
> My conclusion is that it dont really matter if you use T2 or T1 GDM for the overall game performance as the run to run variance difference is greater than the "performance difference", as long as you dont hunt for the last 0.1 to 0.3 ns in the AIDA64 latency bench.
> 
> But I notice that T1 GDM has the highest achieved results both in average fps, 95%'s and minimum's .. Hard to say if this is run to run differences or if GDM actually has higher potential "when the stars align"
> 
> Veii's bus timings are not recommended at all for my 4x8gigs setup, but if you decide to use them, then T2 is much faster than T1 GDM."


did you try 4-4-18? 













these are Veii bus timings (wasnt suggested to me) but these are what got me stable t2 GDM off. 
i did not try T1 gdm on or off after finding these BUS_timings, were what stabilized my 4x8 3200c14 sticks 
to run daily.
i did try to lower my SOC, but that wasnt happening as i instantly had issues with BSOD, crashings,
major signs of instability.


----------



## nexxusty

My RAM OC was no longer stable...

It wouldn't POST every time. Changing ProcODT, CAD_BUS, and RTT to AUTO made it post every time.

AUTO sets it to 36.9/24-20-24-24/7-3-1 respectively, which I have been told is where I should be anyway.

Have to retest, still don't understand why it started acting like that.


----------



## Veii

nexxusty said:


> Went to use my system today and my memory OC is no longer stable. Well, it's stable, but it won't POST every time.


Don't overthink it. This is common and from me reported as "broken memory training since patch C"
It's really common and there are subtle attempts to fix this - yet it still is broken
The 3rd CAD_BUS Value is there to work against cold/warm boot issues
It's the reason Vermeer requires now 30+ ohm, instead of 24. But CsODT , strength also depends on RTT values
I keep it at 20, because you can be accurate with the setup timings there. But as dimm amount and trace length-difference changes ~ you can need more

Sadly a common problem, which is already strongly worked against - yet never able to be fixed.
I still get boot freezes after applying bios settings - which need a manual reboot
(the issue is, reboots don't actually do cold boots anymore)
and someday (rarely now) it needs two reboot attempts to wake up from a cold boot
This continues to be an AGESA issue - and barely anything you can do more about it
Except for:

increase CsOdtDrvStr or the corresponding setup time slightly
fix PHY under AMB CBS for longer memory training attempts
overall use slightly more VDIMM and eat the lower FCLK by increasing procODT
(higher proc = easier to boot, but will cause DIMM-PCB crashes with high ClkDrvStr)

There is really nothing more you can do, just accept the fact that memtraining is a broken mess for anything non Micron Rev.E

@domdtxdissar Thank you for testing this thoroughly !
This was my take on it ~ if it was skipped










> tCKE
> T2 =
> 
> Average average-fps = 249.2 fps
> Average 95% lows = 182.1 fps
> Average minimums = 172.8 fps
> T1 GDM =
> 
> Average average-fps = 242.7 fps
> Average 95% lows = 177.8 fps
> Average minimums = 168.7 fps
> =============================
> Non tCKE
> T2 =
> 
> Average average-fps = 254.7 fps
> Average 95% lows = 184 fps
> Average minimums = 174.7 fps
> T1 GDM =
> 
> Average average-fps = 252.2 fps
> Average 95% lows = 183.6 fps
> Average minimums = 173.3 fps


What i find really surprising, is how small the difference is on your odd timings set between GDM and non GDM
Wouldn't be surprised at all that they lose a bit of perf, as you introduce effectively a delay in there and powerdown waking up delay is a thing

It clearly confirms that they should not be used "for performance" & if you gained perf, then it means the old set was unstable to begin with
Also shows very well, that GDM's slowed MUX completely break on minimum FPS ~ as the cuts dont happen in the correct time

Thank you @domdtxdissar
I take from all this long consuming testing 3 points:

4 dimms need different SETUP times than 2 dimms, at least slightly different
i surely need to fix RTTs for 4 dimms. 6/3/3 is just not perfect for 4 dimms but great for 2x16 (known but reconfirmed)
GDM users need a different cutting timing, as it's not suited for it
(kind of expected, but unsure if the needed to spend time figuring it out ~ is even worth it.
No one should use GDM at this point) 

Expecting a perf difference on a stability suggestion, was strange to begin with 
Kind of surprising it made such a big one for some people.
At least it's very useful in daily'ing 1.56~1.6 volt when the powerdowns happen in the correct time 😇


----------



## zGunBLADEz

this system perse is so random on performance that trying to centralize numbers specially using normal amd boosting behavior will throw off numbers in benchmarks run over and over again..


----------



## nexxusty

@Veil.

I tried setting 40-20-30-20, didn't seem to help. I'll test more in the morning. For now I've reached 3866mhz CL14 GDM ON stable.

I've paid close attention to what you've been saying, I appreciate everything man. So much, honestly.

Going to start tuning GDM off tomorrow. I read and re-read everything you typed and I finally understand that GDM rounds up to an even number with EVERY timing. Not just primaries, correct?

This is definitely something I need to do. You boys keep saying GDM on is worse, I have no reason not to believe that. So 2T it is. 2T is hard to use in my head for some reason. I blame it on Core 2 Duo's. Lol.

_edit_

Done. 3866mhz CL14 GDM OFF 2T is stable.

That was easy, actually. 53.6NS rock solid. Going to be using this for a bit. 53.6NS is really good for a system that only games.

I and MANY others are under the impression GDM=1.5T. Clearly, it's not, its 2.5T. I honestly can't believe I was thinking it was better. Ugh. That basically makes every setting I stabilized at 2.5T (Almost) a complete waste of time.



zGunBLADEz said:


> this system perse is so random on performance that trying to centralize numbers specially using normal amd boosting behavior will throw off numbers in benchmarks run over and over again..


0.3ns DRAM variance is your max. If you get variance over that, your OC is unstable.

I can run MemBench 5x in a row and my latency is identical every time.

Don't take offense to this, but some people seriously are terrible at setting up Windows. Are you SURE its not something like random (or otherwise) CPU usage?

If you have any bloat installed on Windows, you will get variance like that. I don't get any because I painstakingly setup my system for gaming and adjust a ton of settings.

Just some food for thought.


----------



## Veii

nexxusty said:


> Going to start tuning GDM off tomorrow. I read and re-read everything you typed and I finally understand that GDM rounds up to an even number with EVERY timing. Not just primaries, correct?
> 
> This is definitely something I need to do. You boys keep saying GDM on is worse, I have no reason not to believe that. So 2T it is. 2T is hard to use in my head for some reason. I blame it on Core 2 Duo's. Lol.


I've needed quite a bit of time to verify it too, it's clearly not 1.5T because rounding happens twice in the stage, not only once
It slows down MUX to half speed, and we have more than one main MUX to the Sensoring Die
It happens twice on DDR4. Sadly companies still don't gray out the command rate option and people confuse it for 1.X T
(one time and halfed speed - well it clearly isn't) 

What you can see in the bios is autorounding of tCWL, tCL, tRTP, tWR
and tRFC looks like it can be lower than it actually has to be

But i do have a strong suspicion since very early, that it rounds more than tCL and rounds the main 5 primaries in the hidden
It surely does round up and not down - but the sequence has to match it twice not only once
3800C14 1T was hard to get stable 




nexxusty said:


> Done. 3866mhz CL14 GDM OFF 2T is stable.
> 
> That was easy, actually. 53.6NS rock solid. Going to be using this for a bit. 53.6NS is really good for a system that only games.


Good job 
Be sure to check procODT -1 and +1 to see if you see any improvement in Aida64 at the same voltages
Only one works well without variance ~ soo you should be able to spot it easily


----------



## zGunBLADEz

nexxusty said:


> 0.3ns DRAM variance is your max. If you get variance over that, your OC is unstable.
> 
> I can run MemBench 5x in a row and my latency is identical every time.
> 
> Don't take offense to this, but some people seriously are terrible at setting up Windows. Are you SURE its not something like random (or otherwise) CPU usage?
> 
> If you have any bloat installed on Windows, you will get variance like that. I don't get any because I painstakingly setup my system for gaming and adjust a ton of settings.
> 
> Just some food for thought.


trust me i been playing with ryzen setups and ram overlocks for a long long time.. the numbers & power and such are not 100% accurate at all the times.. system does what he wants.
The ram variance i would not take too serious im getting 53-55ns with a mere 3800/cl16 dial in and i got better numbers on aida than most ppl with 13s/14s and tighter timings and thats just a base run... the -or+ 2ns difference is ruled out as a margin of error in my book... why bother only point forward would be 1900+ more ram mhz over 3800 matching your fclk..

havent got into tweaking it yet till i manage to 0 out the random performance first on the mhz shown vs real perfomance numbers between threads loaded..

theres not use for what im seeing "so far" to forze such timings theres no point on it.. other than creating stability issues for placebo gains
havent even put out yet my 4400 kit b die lol

This is just 16s/32 tfaw 16 cmd 1t trfc @ 310 nothing else touched once i tweak the rest the copy will go up and thats it no more to look for.. in the meantime im more into how to squeeze the behavior/voltage etc on the 5900x and the random boosting behavior it does that i dont like as the mhz reported are not an indication on perf given.. seeing it boost tp x MHz vs the reported score :rollseyes:










this 2 sticks is a set of 4 validated on this timings on a x299 system on quad channel over a HCI 70+ hr run


----------



## nexxusty

Veii said:


> I've needed quite a bit of time to verify it too, it's clearly not 1.5T because rounding happens twice in the stage, not only once
> It slows down MUX to half speed, and we have more than one main MUX to the Sensoring Die
> It happens twice on DDR4. Sadly companies still don't gray out the command rate option and people confuse it for 1.X T
> (one time and halfed speed - well it clearly isn't)
> 
> What you can see in the bios is autorounding of tCWL, tCL, tRTP, tWR
> and tRFC looks like it can be lower than it actually has to be
> 
> But i do have a strong suspicion since very early, that it rounds more than tCL and rounds the main 5 primaries in the hidden
> It surely does round up and not down - but the sequence has to match it twice not only once
> 3800C14 1T was hard to get stable
> 
> 
> 
> Good job
> Be sure to check procODT -1 and +1 to see if you see any improvement in Aida64 at the same voltages
> Only one works well without variance ~ soo you should be able to spot it easily


Good to know we agree on this now then. I am a 2T convert all the way. You've done much more testing I'm sure. It's interesting the behavior 2.5T has (We should really start calling that I believe), what really sucks IMO is it's enabled in most systems by default.

2.5T by default doesn't sound like a company confident in it's memory subsystem... LOL. I absolutely agree with 3800 C14 1T being hard to stabilize. I've tried for 3 days so far, 3 hours or so each time and still haven't gotten too far. I still have some learning to do. Hahaha.

I will definitely test out ProcODT -1 % +1. Now that I have the system booting every time, cold boot, warm boot, doesn't matter. 100% first boot rate. That took awhile, 2-3 hours tonight. I didn't even smoke anything tonight and I'm VERY Canadian if you know what I mean. 

Overclocking just captivates me sometimes. We've all been there, I know I'm not the only one.

Thanks again for the help brother. I do appreciate it.


----------



## Hibbing

craxton said:


> did you try 4-4-18?
> View attachment 2481098
> View attachment 2481099
> 
> these are Veii bus timings (wasnt suggested to me) but these are what got me stable t2 GDM off.
> i did not try T1 gdm on or off after finding these BUS_timings, were what stabilized my 4x8 3200c14 sticks
> to run daily.
> i did try to lower my SOC, but that wasnt happening as i instantly had issues with BSOD, crashings,
> major signs of instability.


Your write speeds are hilariously low.


----------



## Joeking78

Hibbing said:


> Your write speeds are hilariously low.


Pretty normal for a 5600x I'd say


----------



## MageTank

Hibbing said:


> Your write speeds are hilariously low.


I would actually argue his write speeds are suspiciously close to perfect, lol. Single CCD setups are known to incur a write penalty of 1/2 by design, so what you are seeing there is entirely normal, but to achieve almost 32GB/s exactly at DDR4 4000 is extraordinary to me. That implies he is achieving almost perfect bandwidth efficiency (4000 x 8 = 32,000, he is sitting at 31,999) and didn't need to compromise on his tertiary timings to achieve that 4000mhz overclock. I'd say it's a solid result.


----------



## Oberst

Sharing my experience with Patriot Vipers 4000 CL19. Still learning the platform since I'm coming from SB 2600k.

I got them stable at 3800 CL16 - vdimm 1,43. SoC below is high as the board overvolts. It's around 1,1v. I managed to correct it by LLC 6-7.



http://imgur.com/a/mxBn8N0


Currently testing (seems stable):

SoC - 1,0750v (getting ~ 1,084v after adjusting LLC)
VDDP 0,880v
VDDG CCD - 0,930v
VDDG IOD - 0,980v


Seems I got a good IMC on this R5 3600, I can do CL14 flat but not stable. Will try to work on this later.



http://imgur.com/a/G8eNQm6


----------



## tefla

Could i get a quick sanity check for my results? I feel like my latency is higher than it should be for the timings I'm using. I've seen similar timings from others that are better. I'm quite obsessive about keeping background processes and bloatware to an absolute minimum, so I'm not convinced that's the contributor. My run-to-run variation is ~0.2-0.3ns. 54.6 being the lowest I've seen. Stability seems OK. No WHEA, 1000% kahru, 10 cycles 1usmus. I need to run overnight to confirm since this is inadequate, but I think it's stable "enough" for the validity of this aida bench.

I've been following and implementing some advice from @Veii and others, so still very much a work in progress--it's a lot to wrap my mind around.

2x16gb, vdimm=1.55 (1.56 reported--not necessary for stability, but this is my max voltage I'm comfortable with so I'd like to build my timings around it)


----------



## nexxusty

bonet69 said:


> This ram will throw errors and fps drops if you pass 45 degress (at 1.5v+-), i have this timings (if you are lucky you should be able to lower tRCDRD to 14 if not 15 its fine):
> 
> View attachment 2473691
> 
> 
> Also tRCDWR to 8 will work for sure, and tRP to 14 should be ez too, i am currently running at 1.49v without errors, but as said not all sticks can do it, also SCLs to 2 should be fine.
> 
> EDIT: i read now u quoted me before, the errors are probably temp related monitor (with hwinfo) you dont go over 45 degress, up the speed of the nearest fans to the ram or think about additional fan for ram, i dont need it now, but maybe in summer i will need it.... Also you can try copyng my voltages, soc, vddp, vddgs...
> 
> 
> 
> Are you sure that its not throwing WHEA errors? You can check doing a test with OCCT (SSE test extreme should throw them fast or dont if its stable) I can boot at 2033 fclk but i get whea errors in hwinfo or occt with more than 1900+ fclk....
> 
> Regards!


I feel this needs to be said.

When DDR4 temp rises over 45c, any type, what's called "Wandering bits" can happen. This is why when I am overclocking DRAM I take OFF the heatspreaders (Most of them do not help with reducing temps and are actually insulating the DRAM IC's) and have active cooling on them.



Hibbing said:


> Your write speeds are hilariously low.


Your knowledge is hilariously low.

Know what you're talking about before you speak up like that.



tefla said:


> Could i get a quick sanity check for my results? I feel like my latency is higher than it should be for the timings I'm using. I've seen similar timings from others that are significantly better. I'm quite obsessive about keeping background processes and bloatware to an absolute minimum, so I'm not convinced that's the contributor. My run-to-run variation is ~0.2-0.3ns. 54.6 being the lowest I've seen. Stability seems OK. No WHEA, 1000% kahru, 10 cycles 1usmus. I need to run overnight to confirm since this is inadequate, but that doesn't seem like the cause.
> 
> I've been following and implementing some advice from @Veii and others, so still very much a work in progress--it's a lot to wrap my mind around.
> 
> 2x16gb, vdimm=1.55 (1.56 reported--not necessary for stability, but this is my max voltage I'm comfortable with so I'd like to build my timings around it)
> 
> View attachment 2481142
> 
> View attachment 2481143
> View attachment 2481144


Looks right on point to me.

I run 3866 14-14-14-14-30 2T GDM OFF @ 1.55V (Pretty sure I can lower voltage a bit, at 1.52v this was not stable) and I get 53.6NS.

You're bang on I should say. The important thing is, does your DRAM latency fluctuate more than 0.3NS in any direction each test? If not, what you're seeing is accurate for latency.

@Veii has taught me SO much in the past two days. I really respect that guy.


----------



## mongoled

tefla said:


> Could i get a quick sanity check for my results? I feel like my latency is higher than it should be for the timings I'm using. I've seen similar timings from others that are significantly better. I'm quite obsessive about keeping background processes and bloatware to an absolute minimum, so I'm not convinced that's the contributor. My run-to-run variation is ~0.2-0.3ns. 54.6 being the lowest I've seen. Stability seems OK. No WHEA, 1000% kahru, 10 cycles 1usmus. I need to run overnight to confirm since this is inadequate, but that doesn't seem like the cause.
> 
> I've been following and implementing some advice from @Veii and others, so still very much a work in progress--it's a lot to wrap my mind around.
> 
> 2x16gb, vdimm=1.55 (1.56 reported--not necessary for stability, but this is my max voltage I'm comfortable with so I'd like to build my timings around it)
> 
> View attachment 2481142
> 
> View attachment 2481143
> View attachment 2481144


Increase tRDRDSCL and tWRWRSCL to 4 or 5, compare to your prior results


----------



## Veii

@tefla try if tRDWR 9 can boot and at the same time fix SD,DD's to 1-4-4-1-6-6 (tWRWR is 6)
It looks pretty spot on, just that this CL does nearly nothing and only wastes voltage

you can compare them to the flat 16-16 set taken from this post








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


That's probably already the lowest you can go , maaybe tRTP 6 could run Why can't you increase IOD a bit - for 3800MT/s ? Maybe also tRDWR 11, tCWL 14 could run (maaybe if you have a tiny bit of reserves left) But it could need tWR 16 - you have to try I've tested with tRTP 6 and so far so...




www.overclock.net




9-4 tRDWR/tWRRD should be possible for you


----------



## Hibbing

nexxusty said:


> Your knowledge is hilariously low.
> 
> Know what you're talking about before you speak up like that.
> 
> 
> 
> L


Another idiot, clueless and worshipping in the wrong place.


----------



## nexxusty

Hibbing said:


> Another idiot, clueless and worshipping in the wrong place.


"The wrong place"

Lol.

I'm clueless, yet I knew 1 CCD Ryzens since 3000 series post up half the write speed? Common knowledge around here. Yet, you didn't know.

Who's the "clueless idiot" now?


----------



## Veii

@Oberst use RTT 7/0/6 for A0 Vipers 
This allows to push them beyond 1.52v without the PCB crashing

Also you can run them tRCD_RD /2 -1 with added tWRRD delay
6-3 for SCL 2, tRCD 14
6-4 for SCL 3 
7-4 for tRCD 16, SCL 3
and so on 

You also can drop procODT down to 28ohm for Matisse, if you run IOD as 950mV (enough for 3800)
Else just run them at 32ohm - no need for anything beyond 36


----------



## Br3ach

PowerK said:


> Thanks, Veii
> 
> *@nexxusty, *is 1T even possible with 4 sticks on this daisy chain DIMM setup? I haven't even tried.


Probably, if the stars are aligned... This here is _almost_ stable at tCL 15 (no other timings tuned). Almost, being the operative word, and I've spent like close to a week trying to stabilize it... no luck (A1 10 layer PCB).


----------



## nexxusty

Br3ach said:


> Probably, if the stars are aligned... This here is _almost_ stable at tCL 15 (no other timings tuned). Almost, being the operative word, and I've spent like close to a week trying to stabilize it... no luck (A1 10 layer PCB).
> 
> View attachment 2481154


Nice! Close hmm?

Bandwidth/Latency?


----------



## Br3ach

nexxusty said:


> Nice! Close hmm?
> 
> Bandwidth/Latency?


With these timings? Relatively crappy.


----------



## Dasa

Any thoughts on these settings with 4x8GB 3200c14 A1-10L.
Went a little crazy tightening things up this time even if it didnt make a noticable difference.
One stick is a dud and the reason for the high tRCD.
With a clean boot AIDA64 can report as low as 53.6ns at 3733 using these settings.
Also works with C14 240tRFC but needs 1.52v set ~1.54v actual for ~0.5ns lower latency.
ClkDrvStr 40-60 was helpfull in getting higher V stable but probably not needed at 1.46v.

Gave up on 3800+ for now as the GB BIOS is still just too hit and miss on the training with a huge variance in WHEA between posts at the same settings.

Currently testing same settings with 101 BCLK but seeing the odd error 15 which seems to be due to me not calculating tRFC correctly and that extra 24MHz on the CPU has made curves seriously unstable in AIDA64 cache benchmark resulting in frequent blue screens despite prime95 passing just fine.


----------



## Redlurkeraite

Hey Guys, 

Is there anything I can do to tighten the items or maybe get it running more stable?


----------



## kim nk

Tsme 비활성화
SME 비활성화
lnterleaving 크기 256
메모리 지우기 비활성화
Blck-100.5625
5900X CPU 클록-46.75
3800-> 3821
SOC 1.1 VDDG IOD 1.060 CLDO_VDDP 0.900 VDDG CCD 0.940
SOC LLC 레벨 4140 % 위상 제어-극한
드램 전압-BIOS 1.5 v

*TFAW = 16 *










*TFAW = 6*


























안녕하세요 NICE 님, 항상 감사의 마음으로 veii의 게시물을 배웁니다.
나는 이것을 시도했지만 여기에 수정해야 할 사항과 조언이 있습니까?
영어를 번역자로 사용할 때 오타가있을 수 있습니다 ...
좋은 하루 되세요 ~ !!


----------



## Veii

@kim nk strangely tFAW looks to be too low, the result is slower
tRP 12 is no option for you bellow 1.56v ?

Please try 2 things + baseline:
RTT change to 7/0/6 and see if the same voltage passes 6 cycles of TM5 (3min each cycle)

Then test with
tRP 14, tRAS 22, tRC 36 , tFAW 16, tRFC 252-187-115, tWR 14, tRTP 7, tRCPage 126 , tCKE 9, tWRRD 4

And also make a test with
14-14-14-14-22-33 , tRRD_6-8, tFAW 8, tRFC 231-172-106, tWR 14, tRTP 7, RCPAGE 0, tCKE 9, tWRRD 4, SD & DD 1-6-6-1-10-10 @ 1.58-1.6v
~ if stable, drop voltage lower. If you have post issues add CAD_BUS Setup Time

If still unstable , try CAD_BUS 40-20-40-20, tCKE 1, RTT 705 or 005
but 005 will crash the PCB near 1.52v


Spoiler: You can try to replicate the bottom set:














Should have better latency than me ~ 4.7GHz > 4.65 
Your goal,
increase tWRRD and other timings (tRRD_) to drop tRC to tRAS+tRP (tFAW 4* tRRD_S)
Then if you go for 1x tFAW - use tRAS+1 = tRC


----------



## Veii

Dasa said:


> Any thoughts on these settings with 4x8GB 3200c14 A1-10L.


Add tWRRD delay, you use 4 dimms  , tWRRD 3 here
tRP 14, tRC 42 , tRFC 252-187-115, tWR 14, tRTP 9

tFAW 6 doesn't "just like that" work out 😇
But the main critical thing i see, is too high RTTs
And TM5 is too short
https://www.overclock.net/attachments/tm5-zip.341454/
20 cycles preconfigured, else increase your own version to 25 in MT.cfg
19+ is needed for tRFC check & 1h to reach thermal equilibrium

I mean you can give 6/3/3 RTT's a try
They are not perfect for 4 dimms, but the voltage stability range is still higher than 7/3/1 or 701 - X/X/1 is just too strong for the poor 8gb dimms


----------



## jcpq

Hi
I would like to fix my ram at 3800Mhz @ CL14, 1.5v or less.
It's possible? What settings do you suggest?


----------



## Trusconi85

Redlurkeraite said:


> Hey Guys,
> 
> Is there anything I can do to tighten the items or maybe get it running more stable?
> 
> View attachment 2481186


Voltage?


----------



## _frame_

Br3ach said:


> (A1 10 layer PCB).


G.Skill NEO is on A2 pcb. THAIPHOON BURNER is wrong.



Trusconi85 said:


> Voltage?


He has 4x16 gb confing. It is completely different than yours.


----------



## kim nk

[QUOTE = "Veii, 게시 : 28751516, 회원 : 609138"]
상하게 tFAW가 너무 낮은 것입니다. 결과가 느려집니다.
tRP 12는 1.56v 이하의 옵션이 아닙니다.
[/ 인용문]
[QUOTE = "Veii, 게시 : 28751516, 회원 : 609138"]
안정 널
[/ 인용문]


Veii said:


> @kim nk strangely tFAW looks to be too low, the result is slower
> tRP 12 is no option for you bellow 1.56v ?
> 
> Please try 2 things + baseline:
> RTT change to 7/0/6 and see if the same voltage passes 6 cycles of TM5 (3min each cycle)
> 
> Then test with
> tRP 14, tRAS 22, tRC 36 , tFAW 16, tRFC 252-187-115, tWR 14, tRTP 7, tRCPage 126 , tCKE 9, tWRRD 4
> 
> And also make a test with
> 14-14-14-14-22-33 , tRRD_6-8, tFAW 8, tRFC 231-172-106, tWR 14, tRTP 7, RCPAGE 0, tCKE 9, tWRRD 4, SD & DD 1-6-6-1-10-10 @ 1.58-1.6v
> ~ if stable, drop voltage lower. If you have post issues add CAD_BUS Setup Time
> 
> If still unstable , try CAD_BUS 40-20-40-20, tCKE 1, RTT 705 or 005
> but 005 will crash the PCB near 1.52v
> 
> 
> Spoiler: You can try to replicate the bottom set:
> 
> 
> 
> 
> View attachment 2481234
> 
> 
> 
> Should have better latency than me ~ 4.7GHz > 4.65
> Your goal,
> increase tWRRD and other timings (tRRD_) to drop tRC to tRAS+tRP (tFAW 4* tRRD_S)
> Then if you go for 1x tFAW - use tRAS+1 = tRC












There was no problem so far, but from tcke 9 setup i get an error










5900x has more latency then 5600x .. stretches over 1.1 ns

This is the timing currently in use for 3 months. Is it okay to continue using this timing?
Currently, this timing has the lowest latency..

5600x max pbo max manual 4.9










5900x 4.7 clock manual fixation


































Current actual use timing

TRFC 240 -178- 110 - DRAM VOLTAGE 1.50V
TRFC 252 -187-115 DRAM VOL TAGE 1.48V









tm5 adv5 This is the timing that all 40 cycles have passed.

Onlyh the wrong timing from the timings being used above seek advice...

I`m sorry that I don`t understand properly because I always interpret It with google translator.
I`m always tring to understand as much as possible.
Thank you all the time.!


----------



## JustTyko

Hello guys,
Is there anything that I should change? These timings completed 12hours of Karhu Ram test and 25 looped tests of TestMem5 with 1usmus profile without any error. GDM off is unstable with 1T (with 2T is stable). 2x8GB Patriot Viper 4133Mhz A0. Voltage in bios 1.56V, hwinfo64 shows 1.584V.


----------



## jcpq

JustTyko said:


> Hello guys,
> Is there anything that I should change? These timings completed 12hours of Karhu Ram test and 25 looped tests of TestMem5 with 1usmus profile without any error. GDM off is unstable with 1T (with 2T is stable). 2x8GB Patriot Viper 4133Mhz A0. Voltage in bios 1.56V, hwinfo64 shows 1.584V.
> 
> View attachment 2481266


Have you tried GDM OFF and tCL15?


----------



## Owterspace

Just curious how often these Zen 3's scale past 2000 IF?


----------



## mongoled

Owterspace said:


> Just curious how often these Zen 3's scale past 2000 IF?


They scale more often than not, but they have WHEA warnings



Another template for 4 x 8GB A2 users...

Also ran 90 minutes Y-Cruncher tests 15/16 and Y-Cruncher all tests for 2+ hours


----------



## Oberst

@Veii Thanks, will try those RTT values. 

I had already lowered procODT after having fixed SoC overvolting. It was not stable below procODT 40 due to high SoC (overvolting ~1,1v).

Tested and it is stable now with vSoC 1,0750 and procODT 28.

Also I will adjust tRDWR and tWRRD, found your post explaining the rule.


----------



## Yviena

Interesting seems my CPU likes either lower CCD, or CLDO_VDDP voltage from 0.94/0.90v currently at 0.88v.

Also how come that, TRC 48 = 288/214/132 when TRTP is at 9 shouldn't it be TRC*TRTP?


----------



## JustTyko

jcpq said:


> Have you tried GDM OFF and tCL15?


GDM OFF with tCL15 also has errors in TestMem (in second loop, same as it was with tCL14).


----------



## Br3ach

Yviena said:


> Interesting seems my CPU likes either lower CCD, or CLDO_VDDP voltage from 0.94/0.90v currently at 0.88v.


Same here, I think mine likes <0.900 CLDO_VDDP. e.g. 0.820-0.860.


----------



## Veii

Yviena said:


> Interesting seems my CPU likes either lower CCD, or CLDO_VDDP voltage from 0.94/0.90v currently at 0.88v.
> 
> Also how come that, TRC 48 = 288/214/132 when TRTP is at 9 shouldn't it be TRC*TRTP?


My rules work in ns values
Inside tRFC 288 fits several values if you turn it into ns

tRTP and tWR are scalable and "modular"
what really leads to performance you have to test
but when it comes to stability, these are the values by math which work
they are full decimals or 0.5 values
anywho, there is no right answer

the "easiest" answer is half of tWR, while the same applies to tWR and tRFC
you still can use tWR 12 , tRTP 9 ~ if your value allows it
many dimms or higher capacity can need high tRTP too
rulesets exist only for stability, and exceptions exist too 
what counts later is the result ~ not how you get there

Oh, yes i haven't seen positive scaling over 940mV VDDG CCD


----------



## Dasa

Veii said:


> Add tWRRD delay, you use 4 dimms  , tWRRD 3 here
> tRP 14, tRC 42 , tRFC 252-187-115, tWR 14, tRTP 9


Testing now thanks and so far so good with 60min of TM5 just needed to step up 1.49V at 3771c15 due to tRFC and loss of stability from relaxed RTT.
Performance may have dropped a little but I will have to run a few times to verify since it was a very small change.
I usually leave tWRRD on auto and depending on settings chosen it will often change between 1-2 and occasionally 3 but if it helps stability and doesn't hurt performance then it can stay at 3-4.

C14 seems a fair way from stable at 3771 even with 1.55v set which is probably ~1.57-1.58v actual with not much change in the number of errors once going over 1.53v but then there was a lot of different errors so that may remain out of reach for these kits.



Veii said:


> tFAW 6 doesn't "just like that" work out 😇


Figured as much but gave it a go anyway and it seemed the same or faster than 16. Will see if there is a measurable performance difference vs 8 once it is all stable or would that requier tweaking other settings for ideal performance?



Veii said:


> I mean you can give 6/3/3 RTT's a try
> They are not perfect for 4 dimms, but the voltage stability range is still higher than 7/3/1 or 701 - X/X/1 is just too strong for the poor 8gb dimms


Ah so that is how they work higher stability with 7/3/1 but a balancing act with the amount of VDIMM.

Thanks very much for taking the time to help I have spent months reading this thread and tweaking but some of it is still sinking in, some of it never will and too much is already forgotten.


----------



## Veii

Dasa said:


> Thanks very much for taking the time to help I have spent months reading this thread and tweaking but some of it is still sinking in, some of it never will and too much is already forgotten.


Thank you for dealing with me 

There is a huge book around how Dynamic ODT works, and how high and how low CKE can be (signal CKE - which has to move in a balance up and fall in the same but be captured save and pushed up)

Pretty much the opposite of a powerdown "cut"
They are , dumb to speak - cutting ranges
working as impedances, but imaginable as "gates" which only let specific signal strength through
(strength as in volume/amount, not as in peak high)

RTT_PARK the bottom one , under RZQ 1 = 240ohm - is just too strong
Not only are they acting as "gates" but as the nature of ohm impedances, they are also boosters/multipliers
A strong RTT impedance very often and nearly always will crash the PCB , while wrong ones will fully refuse to post at all

Bioses to this day are not IC aware, just slightly PCB aware and amount aware
They don't know what works well for this ICs and can only on the "very short" memory training and trace distance check, guess what could be correct
But the problem is a stacking one
Not only are people complaining about longer boot times, soo memory training gets faster and even less accurate
But the faster it is, with often lack of knowledge or even option to increase PHY memory training delay & amount
~ the more inaccurate they become

It's pretty much a bruteforce trial method of trowing preconfigured sets of timings at it - till it posts
Soo having correct RTT values is critical
Except the little unknown change, that since 1.0.8.1 (Vermeer) a lot of memory training and minimum impedance changes happened
RTTs on Matisse, simply are not optimal and too strong at this point ~ for Vermeer

No one except maybe 4x 32GB people, should run RTT_Park at 1
There is another story about using RTT_WR (2nd value) and working with dynamic ODT
(recommended a value of RZQ/3)
compared to flat out going with 7/0/X

But that's not only for debate, but also hard to research ~ as on-die termination missmatch only shows up after long testing sessions
and then also likely after you quit them and had couple of idle states
Very annoying to figure them out and clearly not explainable in short posts
You will notice what works better once you are on a point where it matters
But overall there are big voltage "range" differences , before PCBs start to crash
ClkDrvStr (first cad_bus value) plays a big role in how much ampere the dimms recieve at the end, and when "too much" is "too much"

"bad voltage scaling" ~ seems to end up pretty much only at the "wrongly powered" part
Soo it's very good if you guys pretty much start with 2T
Even when "games" might show a neglectable difference ~ there is a measurable one between GTM & 2T
Every little positive change is a good change, and you learn to power them correctly with potentially lower timings at the end. Win Win


----------



## Yviena

I wonder why ram sticks haven't got circuitry that monitors, and adjusts signal strength values on the fly, or is this a DDR5 thing?


----------



## Dasa

Still one error #15 at some stage after the first hour of TM5
Will try tWRRD 4 and 1.5VDIMM and maybe give the IOD and SOC a nudge to see if that helps.


----------



## Veii

Dasa said:


> Still one error #15 at some stage after the first hour of TM5
> Will try tWRRD 4 and 1.5VDIMM and maybe give the IOD and SOC a nudge to see if that helps.
> View attachment 2481321












It fixed for me on tRDWR decrease , and because tCWL was awkward
You can try these 3 parts 
tRDWR decreased only by one after hitting the correct tWRRD. The other one would fully fail to boot
Or you can just increase tCWL and get it away with lower tRDWR overall


Yviena said:


> I wonder why ram sticks haven't got circuitry that monitors, and adjusts signal strength values on the fly, or is this a DDR5 thing?


That's DynamicODT for. They do , but you have to "enable" it 
and configure correctly 
RTT values are not inside the DIMM


----------



## GribblyStick

OK, tried again with a more varied voltage setting.
I set 1,2 Soc, 1,5 DIMM and 1,05 IOD with the intent to lower them if I can get a normal boot, but otherwise being fine if I have to keep those.
I see a lot of CLDO_VDDP of 0,880 so I figured I'd give that a shot and then 0,940 CCD
GDM OFF and 2T to start with. CADBUS settings were set manually.
All timings are on auto DOCP settings

I started with procODT at 32, no boot (tried with up to 60 ClkDrvStr)
Then with ODT 34 I got a boot. (screenshot below)

I am surprised I was able to boot with GDM off, but otherwise I still get the crippling system slow down.
I am barely able to post this comment. Could this be a sign of some incompatibility?
I'll try and add an aida scan later if I manage.









Ok this took a while to complete, but as you can see, this is just unusable:


----------



## Iarwa1N

Hi guys, I have 2x8GB D9TBH (MT40A1G8WE-083E:B), Micron B-dies and I am really new to memory overclocking. I just started by copying the timings of someone who has Micron E-die from the Zen Ram Overclocking sheet. I tested the values with TM5 and only got 2 errors, 3-14. Here is my timings, any suggestions to where to start and what to try? Thanks. (Vdimm is at 1.4V)









.


----------



## DeletedMember558271

So 7C91vA61, AGESA 1.2.0.1, SMU 56.46.0 is out for my B550 Tomahawk and 1900 FCLK still doesn't post, 1933+ does.
Are none of the minds at AMD, MSI, or here like @Veii ever going to figure out how to boot/fix these FCLK holes so many people are having? Cause I'm not. Why do I have one at 1900?
Idk if I can get rid of WHEA 1933+, I wish my unbootable FCLK hole was 1867 instead so I could boot 1900 probably highest without WHEA.
CMOS reset + all BIOS defaults 1867 = post, 1933+ = post, 1900 = no. All other settings remain identical/unchanged.
This stupid **** is never going to get fixed nobody is ever going to figure it out are they haven't seen 1 person solve it for themselves no suggested solutions have worked for anyone


----------



## Owterspace

mongoled said:


> They scale more often than not, but they have WHEA warnings


Sweet no errors or warnings, not losing my mind lol. Thanks.


----------



## Comalive

Dreamic said:


> So 7C91vA61, AGESA 1.2.0.1, SMU 56.46.0 is out for my B550 Tomahawk and 1900 FCLK still doesn't post, 1933+ does.


On my B550 Gaming Edge Wifi I can now boot with 1900. A quick L3 cache speed test shows increases of 50 - 100% compared to before so they did some great work there!


----------



## jcpq

Hi
I got to this configuration, TM5 stable, with 1.43v
My question is:
Can I improve this or should I invest in 3800 @ cl14
For cl14, I did preliminary tests where it needed more than 1.5v.
What is your suggestion?


----------



## domdtxdissar

Today i found out how much latency difference there really is between a 1CCD and 2CCD Zen3 CPU 
(5600x + 5800x VS 5900x + 5950x)

I disabled one CCD on my 5950x to simulate a 5800x
1 CCD = 51.7 ns in aida64
2 CCD = 54.2 ns in aida64 








Running 4x8gigs bdie memory and PBO CO 24/7 settings


----------



## zGunBLADEz

you guys are lowering those "timings" too low.. with barely no gains..
infinity fabric perse is limiting/caping the ram performance/bw... trying to forze those timings can pop up an error eventually sooner or later.


----------



## Br3ach

GribblyStick said:


> Ok this took a while to complete, but as you can see, this is just unusable:


Your IF is really unstable, that's why. VSOC/IOD are already pretty high, so I'm afraid 4000 seems to be out of reach for your chip.


----------



## BluePaint

Br3ach said:


> Your IF is really unstable, that's why. VSOC/IOD are already pretty high, so I'm afraid 4000 seems to be out of reach for your chip.


That! My 5950X looses CPU performance on each fclk step above 1900. It can run 2000 AIDA just fine, but CPU performance is 10-50% lower than on 1900. The more CPU voltage/power usage the bigger the performance delta to 1900.

My 5800X on the other hand runs fine up to 2033 fclk performance wise but with some WHEAs ofc.


----------



## BloodDivine

Hey @Veii is it possible to have an error list for y-cruncher like we have with TM5?
So far I'm aware of 
SFT: TDC too high
FFT-N64: VDDP/G/SoC voltage too low

Thanks in advance


----------



## GribblyStick

Br3ach said:


> Your IF is really unstable, that's why. VSOC/IOD are already pretty high, so I'm afraid 4000 seems to be out of reach for your chip.


That.....would really suck. This is my second 5900x, I already replaced the first one because I was not able to go past 3600/1800 on that one.
It was from a pre-built so I figured it might just have been an oem kind of thing. This one is able to run 3800 no problem, but I was aiming to run my RAM at their XMP values at least..


----------



## Veii

BloodDivine said:


> Hey @Veii is it possible to have an error list for y-cruncher like we have with TM5?
> So far I'm aware of
> SFT: TDC too high
> FFT-N64: VDDP/G/SoC voltage too low
> 
> Thanks in advance


I dont have that much issues collected from it yet
It would take a long time for this request 

I'll think about it
Usually everything goes haywire, if PBO is "too open" and the chip overvolts ittself
They don't crash for me anymore, FFT & C19 are one of the most important
But N64 is harsh too to the memory controller
C19 is tests loadline droop as the AVX test has to run sub 1.18v
FFT barerly uses resources but tests the memory controller (Both VDDPs, Both VDDGs, and anything SOC related)


----------



## BloodDivine

Veii said:


> I dont have that much issues collected from it yet
> It would take a long time for this request
> 
> I'll think about it
> Usually everything goes haywire, if PBO is "too open" and the chip overvolts ittself
> They don't crash for me anymore, FFT & C19 are one of the most important
> But N64 is harsh too to the memory controller
> C19 is tests loadline droop as the AVX test has to run sub 1.18v
> FFT barerly uses resources but tests the memory controller (Both VDDPs, Both VDDGs, and anything SOC related)


Any information would be helpful at all. Most likely what's crashes on me is the HNT/VST


----------



## Veii

GribblyStick said:


> OK, tried again with a more varied voltage setting.
> I set 1,2 Soc, 1,5 DIMM and 1,05 IOD with the intent to lower them if I can get a normal boot, but otherwise being fine if I have to keep those.
> I see a lot of CLDO_VDDP of 0,880 so I figured I'd give that a shot and then 0,940 CCD
> GDM OFF and 2T to start with. CADBUS settings were set manually.
> All timings are on auto DOCP settings
> 
> I started with procODT at 32, no boot (tried with up to 60 ClkDrvStr)
> Then with ODT 34 I got a boot. (screenshot below)
> 
> I am surprised I was able to boot with GDM off, but otherwise I still get the crippling system slow down.
> I am barely able to post this comment. Could this be a sign of some incompatibility?
> I'll try and add an aida scan later if I manage.
> View attachment 2481338
> 
> 
> Ok this took a while to complete, but as you can see, this is just unusable:
> View attachment 2481360


A collection of issues
Start with the first easy to run 16-16 set (at the bottom of the post)








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


That's probably already the lowest you can go , maaybe tRTP 6 could run Why can't you increase IOD a bit - for 3800MT/s ? Maybe also tRDWR 11, tCWL 14 could run (maaybe if you have a tiny bit of reserves left) But it could need tWR 16 - you have to try I've tested with tRTP 6 and so far so...




www.overclock.net




and clone the voltages
Also a bit more readable here


https://www.overclock.net/threads/amd-max-overclocking-voltage.1775745/post-28703233v



Proc 34 is needed , but you more in a loop of issues
CPU VDDP lower than 900mV is also needed - optimally 880mV (probably lower in the future)


----------



## Veii

BloodDivine said:


> Any information would be helpful at all. Most likely what's crashes on me is the HNT/VST


C19 passes , if you skip both ?
Loop FFT, N64, C17 for 4 cycles and report back if this is fine 

Both usually are more mem focused, but they've never crashed for me


----------



## BloodDivine

Veii said:


> C19 passes , if you skip both ?
> Loop FFT, N64, C17 for 4 cycles and report back if this is fine
> 
> Both usually are more mem focused, but they've never crashed for me


I'm on Zen+, not Zen2 or Zen3 
It was some time ago when I tried to stabilize 3533 with a Rev E kit and a 2600X, I had several HNT/VST crashes, N64 just crashed once and never again after I raised the vSOC


----------



## jcpq

I have a doubt?

What values to use in these timings?

tWRWRSD / tWRWRDD 

tRDRDSD / tRDRDDD


----------



## Veii

jcpq said:


> I have a doubt?
> 
> What values to use in these timings?
> 
> tWRWRSD / tWRWRDD
> 
> tRDRDSD / tRDRDDD


Have a distance of 2 values between RD , and WR
a distance of 4 seems to work out for awkward kits - looks to provide a subtle improvement, but it's test-in-progress

1-5-5-1-7-7 for 2x 8gb
1-4-4-1-6-6 for 4x 8, or 2x 16

Tighter / higher values = better performance ~ but have a chance of overlapping
==================================
Can you guys update Aida64 to the current Beta
6.32.5635 and higher
And check if there is one unit which does not have a K19.2 FCH & IMC ?
Something is fishy. I hope it's not a readout bug ~ but there is no unit to disprove it being a bug


----------



## GribblyStick

Spoiler: Veii






Veii said:


> A collection of issues
> Start with the first easy to run 16-16 set (at the bottom of the post)
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> That's probably already the lowest you can go , maaybe tRTP 6 could run Why can't you increase IOD a bit - for 3800MT/s ? Maybe also tRDWR 11, tCWL 14 could run (maaybe if you have a tiny bit of reserves left) But it could need tWR 16 - you have to try I've tested with tRTP 6 and so far so...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> and clone the voltages
> Also a bit more readable here
> 
> 
> https://www.overclock.net/threads/amd-max-overclocking-voltage.1775745/post-28703233v
> 
> 
> 
> Proc 34 is needed , but you more in a loop of issues
> CPU VDDP lower than 900mV is also needed - optimally 880mV (probably lower in the future)






Thanks for having a look, you're my last hope basically lol.

I wasn't entirely sure how much you wanted me to copy so I just took all the settings and changed procODT to 34. VDIMM I Ieft at 1,5
It didn't boot with VSOC at 1,175 though so I changed that 1,2 and it worked.
I also couldn't find a CPU VDDP setting.

I set the one in the AMD overclocking settings under advanced (right under the uncore oc option), to 880 hoping that would be the one.
But looking at HW64 I am a little confused. That reports a VDDP of a measly 0,2ish V ? I had set CLDO VDDP to 0,900 and that is getting read from ZEN so I'm not sure the VDDP I set there was even taken into account.

Anyway I ran 10 minutes of TM5, got no error. No WHEA errors either, but I noticed that running AIDA on the old settings in 4000 did trigger a whole lot of WHEA errors.
Unfortunately, despite this being "Easy" settings for 3800 I saw huge swings in latency in AIDA: 60,9; 59,4; 57,8


----------



## GribblyStick

Under the beta I do indeed get 19.2:


----------



## Veii

GribblyStick said:


> Thanks for having a look, you're my last hope basically lol.
> 
> I wasn't entirely sure how much you wanted me to copy so I just took all the settings and changed procODT to 34. VDIMM I Ieft at 1,5
> It didn't boot with VSOC at 1,175 though so I changed that 1,2 and it worked.
> I also couldn't find a CPU VDDP setting.
> 
> I set the one in the AMD overclocking settings under advanced (right under the uncore oc option), to 880 hoping that would be the one.
> But looking at HW64 I am a little confused. That reports a VDDP of a measly 0,2ish V ? I had set CLDO VDDP to 0,900 and that is getting read from ZEN so I'm not sure the VDDP I set there was even taken into account.
> 
> Anyway I ran 10 minutes of TM5, got no error. No WHEA errors either, but I noticed that running AIDA on the old settings in 4000 did trigger a whole lot of WHEA errors.
> Unfortunately, despite this being "Easy" settings for 3800 I saw huge swings in latency in AIDA: 60,9; 59,4; 57,8
> 
> 
> View attachment 2481450
> View attachment 2481451
> View attachment 2481453


Give it a tiny bit more SOC voltage
you really should not worry about using more. 1.3v is the limit not 1.2v for this gen
CPU VDDP , on asus the VDDP under Tweakers Paradise - is CPU VDDP and a different one than CBS cLDO_VDDP and main menu VDDP
All these, also inside AMD Overclocking are PHY cLDO_VDDPs
You need to lower CPU VDDP in order to reach higher FCLK

They s*ck with the naming haha
You can also check it through the TurboV software 

I would suggest to search and disable armory crate and use








Autoruns for Windows - Sysinternals


See what programs are configured to startup automatically when your system boots and you login.



docs.microsoft.com




to disable specific asus services that preinstall like spyware ~ if you forget that Armory Crate flag in the bios

Can you try ClkDrvStr 60ohm
with 603 and 703 - RTT
To see if you can combat the variance

The settings are fine, it seems to be a powering issue
tCKE should also be fine at this frequency
SETUP Timings are for the other 3 CAD_BUS values , soo they should be fine too (just adjust by freq sadly)
RTT 6/3/3 are not perfect for 4 dimms as it seems - for many users


----------



## Veii

GribblyStick said:


> Under the beta I do indeed get 19.2:
> View attachment 2481454


yes, needs more samples - hopefully we can find one as 17.7 to disprove this bug
Or it was 7nm to begin with and just not read out


----------



## Iarwa1N

Iarwa1N said:


> Hi guys, I have 2x8GB D9TBH (MT40A1G8WE-083E:B), Micron B-dies and I am really new to memory overclocking. I just started by copying the timings of someone who has Micron E-die from the Zen Ram Overclocking sheet. I tested the values with TM5 and only got 2 errors, 3-14. Here is my timings, any suggestions to where to start and what to try? Thanks. (Vdimm is at 1.4V)
> 
> 
> View attachment 2481350
> .
> View attachment 2481351


Any suggestions for me?


----------



## GribblyStick

Veii said:


> Give it a tiny bit more SOC voltage
> you really should not worry about using more. 1.3v is the limit not 1.2v for this gen
> CPU VDDP , on asus the VDDP under Tweakers Paradise - is CPU VDDP and a different one than CBS cLDO_VDDP and main menu VDDP
> All these, also inside AMD Overclocking are PHY cLDO_VDDPs
> You need to lower CPU VDDP in order to reach higher FCLK
> 
> They s*ck with the naming haha
> You can also check it through the TurboV software
> 
> I would suggest to search and disable armory crate and use
> 
> 
> 
> 
> 
> 
> 
> 
> Autoruns for Windows - Sysinternals
> 
> 
> See what programs are configured to startup automatically when your system boots and you login.
> 
> 
> 
> docs.microsoft.com
> 
> 
> 
> 
> to disable specific asus services that preinstall like spyware ~ if you forget that Armory Crate flag in the bios
> 
> Can you try ClkDrvStr 60ohm
> with 603 and 703 - RTT
> To see if you can combat the variance
> 
> The settings are fine, it seems to be a powering issue
> tCKE should also be fine at this frequency
> SETUP Timings are for the other 3 CAD_BUS values , soo they should be fine too (just adjust by freq sadly)
> RTT 6/3/3 are not perfect for 4 dimms as it seems - for many users


Hmm, not the desired effect . I tried this.
VDDP in the tweaker menu to 0,880 (it corrects it to 0,885), HW64 is still showing around 0,2 as VDDP.
ClkDrvStr 60 with 6/0/3 and SOC 1,2125

It had no real effect on the latency, still between 59,9 and 57,6.
So I figured, maybe 1,2125 was too similar and was going to try 1,220 (corrects to 1,225)
This then caused it to fail to boot and not only that, I was then unable to go back to 1,2125 or 1,2.
Though I managed to boot again in 1,2125 after trying twice.

*Update*
I tried again with 1,225. Took me 3 reboots but it then it went through.
it seemed better at first with three runs: 59,8; 59,2; 59,3
but then it dipped down to 57,8 again. so really, no change.
I'll try with 7/0/3.

*Update 2*
Same thing, 59,9 to 57,2


----------



## DeletedMember558271

Comalive said:


> On my B550 Gaming Edge Wifi I can now boot with 1900. A quick L3 cache speed test shows increases of 50 - 100% compared to before so they did some great work there!


And you could boot everything 1867 and below, 1933 and higher before?
You're the only person out of like 100+ I've seen with this issue from various forums and reddit get it solved, and magically by a BIOS update, lucky.
Wonder what it changed and why everyone else is still ****ed

Here's the most commented thread on Reddit about it

__
https://www.reddit.com/r/Amd/comments/llet7x
Not a single person has found a solution that worked for themselves or anyone else.

Curious why @Veii isn't up for the challenge of figuring this out? If it's too hard for you I think we're all screwed


----------



## Veii

Dreamic said:


> Not a single person has found a solution that worked for themselves or anyone else


I wish we could know which ABL you are on
But AMD PBS is nearly always hidden/locked on these bioses

And not everyone shares a Zentimings System info report (latest ZT beta/debug)
there are interesting things out, and interesting options to modify
But it's too advanced and probably many still are debugging other things

I personally still focus on this annoying throttle limit > & = 2100FLCK
it's a loss of 3ns, but at least i get no WHEA at all - only hard crashes

There are many little things to focus on
And it's probably just a badly compiled bios and even more likely with an ABL that has strange limits
Put broken memory training on it, and we have "non bootable" holes @ 1900
I had that on Patch C and didn't want to touch it ever again
Took ASRock 4-5 months to release a fixed non 1.1.0.0 broken AGESA
Which had a broken ACPI 6.3 table ~ bad firmware on it's own
(could be tested with SSDTTime - Dump DSDT ~ hackintosh)

It's not ignored, but we can just hope for new bioses ,till X person starts to push out mods for all the boards
Who ever X person is, will be seen 
We are still in the research & learning phase of "what works well" and "what is broken"

Which speaking of,
DF_C-States got broken on 1.2.0.X (ty amd) 
They result in random reboots or at best WHEA errors ~ disable them but keep Global-C States Generation functioning

EDIT:
B550 boards are compiled and build on ACPI 6.3 standard
X570 are on 5.X - B550 have own children illnesses on their own
Barely any brand cares to make a clean DSDT, as it's not needed when you follow the microsoft compiler ~ it doesn't check for errors
Barely anyone focuses on ACPI standards to fix errors 😐



> Curious why @Veii isn't up for the challenge of figuring this out? If it's too hard for you I think we're all screwed


I have an idea what it is and why
But not only do i lack confidential signing tools for firmwares
But also the time to shape my IDE knowledge
In short ~ i s*ck at it still , but have atm other priorities like the "maximizing" FCLK part & figure out working voltages for 2167 FCLK
ASRock doesn't have WHEA's, soo i'm free from that suffer at least 

Oh i would need to clone myself 2 more times too have enough time in researching everything i want
& getting somehow to money , in order to pay the rent 
~ too much, can't always do 30h sessions 

EDIT2:
Current bios is wonderful , but they've broken DF_C-States 
well it took them long time to fix this DSDT issue _(released yesterday)_


----------



## Comalive

Dreamic said:


> And you could boot everything 1867 and below, 1933 and higher before?
> You're the only person out of like 100+ I've seen with this issue from various forums and reddit get it solved, and magically by a BIOS update, lucky.
> Wonder what it changed and why everyone else is still ****ed
> 
> Here's the most commented thread on Reddit about it
> 
> __
> https://www.reddit.com/r/Amd/comments/llet7x
> Not a single person has found a solution that worked for themselves or anyone else.
> 
> Curious why @Veii isn't up for the challenge of figuring this out? If it's too hard for you I think we're all screwed


I could always boot 1866-2000 (didn't test higher, a few lower values worked as well), only 1900 became buggy for me when it did for everyone else (AGESA 1.1.9.0 I believe it was). What I have noticed it that I cannot always boot 1900, there are still instances where the bug still occurs.
Originally I had left everything at default values and only changed the fclk to 1900, that booted without issues. Using my whole settings for 1866 and increasing only fclk to 1900 didn't boot again. Then in a different test case it booted again....I think I left the voltages on auto when it booted, meaning they were way higher than what I am running (like 1.2 SoC and 1.1 CCD/IOD).
So maybe voltage is the deciding factor here, just an assumption from a few quick tests though.


----------



## Bruizer

@Veii 

How does all this look? (2x16 Dual Rank @ 1.45v)









Do you see any potential issues with timings, etc? Do you recommend 1-4-4-1-6-6 even for 2x16? And should I lower ProcODT? Is this about as good as its going to get at 3600mhz?


----------



## Sleepycat

Whoa, the latest beta bios update for my C8H Hero with AGESA 1.2.0.1 managed to pass a 1 hour OCCT Large Data Set, Extreme test. With the previous 1.2.0.0, it would throw errors about 2 minutes into the test with the same settings. Heck, it would throw errors about 4 minutes in even with optimised defaults and DOCP 3200 CL14 (every thing else default).


----------



## Veii

Bruizer said:


> @Veii
> 
> How does all this look? (2x16 Dual Rank @ 1.45v)
> View attachment 2481529
> 
> 
> Do you see any potential issues with timings, etc? Do you recommend 1-4-4-1-6-6 even for 2x16? And should I lower ProcODT? Is this about as good as its going to get at 3600mhz?


dual rank & 4 dimms should use 1-4-4-1-6-6 yes
Also yes, 36-39ohm is the range for 4000+ 
meaning you can go even lower

-1 CL makes naerly sense, only causes issues and looks nice. 
Also use 6/3/3 RTT on 2x Dual Rank & use CAD_BUS 40-20-40-20 as a start. 60-20-40-24 works too
tWRRD 3 , (X* SCL = lower or equal to tRCD_WR)


----------



## Sleepycat

Bruizer said:


> @Veii
> 
> How does all this look? (2x16 Dual Rank @ 1.45v)
> View attachment 2481529
> 
> 
> Do you see any potential issues with timings, etc? Do you recommend 1-4-4-1-6-6 even for 2x16? And should I lower ProcODT? Is this about as good as its going to get at 3600mhz?


Check my timings out. I'm running 4x16GB b-die.


----------



## Oberst

Managed to find 14-14-15-14-28 stable base @ vdimm - 1,52. For some reason I couldn't get tRCD - 14 stable, maybe more volts needed.
I tried tRDWR / tWRRD - 7 1, 6 3 but can't post. 7 4 or 8 1 for 16-16-16 didn't post either.



http://imgur.com/bhbWF8U


Now testing tWTRS - 4, tWTRL - 8, tRFC - 240



http://imgur.com/AnfOuhP


All above at: VDDP - 0,880, VDDG CCD - 0,930, VDDG IOD - 0,980


----------



## jcpq

Veii said:


> Have a distance of 2 values between RD , and WR
> a distance of 4 seems to work out for awkward kits - looks to provide a subtle improvement, but it's test-in-progress
> 
> 1-5-5-1-7-7 for 2x 8gb
> 1-4-4-1-6-6 for 4x 8, or 2x 16
> 
> Tighter / higher values = better performance ~ but have a chance of overlapping
> ==================================
> Can you guys update Aida64 to the current Beta
> 6.32.5635 and higher
> And check if there is one unit which does not have a K19.2 FCH & IMC ?
> Something is fishy. I hope it's not a readout bug ~ but there is no unit to disprove it being a bug


thank you very much ️


----------



## Br3ach

Oberst said:


> Managed to find 14-14-15-14-28 stable base @ vdimm - 1,52. For some reason I couldn't get tRCD - 14 stable, maybe more volts needed.


tRCD doesn't scale/scales very little with voltage. 15 is normal for b-die circa 1.5V.



Oberst said:


> I tried tRDWR / tWRRD - 7 1, 6 3 but can't post. 7 4 or 8 1 for 16-16-16 didn't post either.


tRCDRD 15 needs tRDWR of min 8.



Oberst said:


> Now testing tWTRS - 4, tWTRL - 8, tRFC - 240


For tWTRS / tWTRL make sure to also benchmark, in my experience sometimes looser is better there.


----------



## Owterspace

I've been running mine like this for a couple of days. It runs everything. No errors or crashing, she's good I think. I cant manually run it over 4600 1.225v, but can boot into windows all the way up to 4900, but wont pass serious testing. Weird. I am letting it run itself right now so cache scores are a bit weak because of it, but I'm sure if I ran it a few times I could bump em up a bit..


----------



## GribblyStick

Not sure you saw my last post on the previous page Veii, needed mod approval for some reason.
But TLR running 1,225 SOC now with the settings you recommmended. Unfortunately it still swings in terms of timings, but I've since realized it also may not cold boot.
I needed to reboot twice today.


----------



## Veii

GribblyStick said:


> Hmm, not the desired effect . I tried this.
> VDDP in the tweaker menu to 0,880 (it corrects it to 0,885), HW64 is still showing around 0,2 as VDDP.
> ClkDrvStr 60 with 6/0/3 and SOC 1,2125
> 
> It had no real effect on the latency, still between 59,9 and 57,6.
> So I figured, maybe 1,2125 was too similar and was going to try 1,220 (corrects to 1,225)
> This then caused it to fail to boot and not only that, I was then unable to go back to 1,2125 or 1,2.
> Though I managed to boot again in 1,2125 after trying twice.
> 
> *Update*
> I tried again with 1,225. Took me 3 reboots but it then it went through.
> it seemed better at first with three runs: 59,8; 59,2; 59,3
> but then it dipped down to 57,8 again. so really, no change.
> I'll try with 7/0/3.
> 
> *Update 2*
> Same thing, 59,9 to 57,2


0.885 is fine, it's just sub 900 whichs is required
Well 930mV stock is bad - even 900 does fix most of the issues - the lower the better 
(870 you have to try, 860 was unstable for me)

Dont worry about SOC that much,the fabric needs it
but inside it hates high voltages - VDDG CCD hates high voltages
Try ManniX's Ultimate Performance powerplan, if you get any varriation 
The first 1-2 runs always are bad, because windows services try to load up & if the CPU knows how to idle down, it also takes one run of some kind of load, before C6 & DF states kick in

If you skip tCKE and Setup timings for now , you can try
60-20-40-20,40-20-40-20, 60-20-30-24
as CAD_BUS options 
6/3/3 surely will run, but it needs a bit of ClkDrvStr 
Cold boot issues purely relate to the 3rd CAD_BUS value, which you either push beyond 30 , or run 20ohm @ SETUP time value 
Sadly SETUP Time value scales by MCLK same as tCKE 
soo you have to spend a lot of time figuring the correct one out 

40-20-20-20, 3-3-15 @ 3800MT/s surely works well on 2x16gb @ tCKE 9 
But tCKE varies. You could try 16 there too or 11 
really depends on MCLK and RTTs what tCKE you use


----------



## Oberst

Br3ach said:


> tRCDRD 15 needs tRDWR of min 8.


I was following @Veii 's info on tRDWR as half of tRCDWR or -1/-2 and setting tWRRD by multiplying with SCL value or by 4. Result should be as near as possible to tRCDRD. I hope I haven't messed things up.



Br3ach said:


> For tWTRS / tWTRL make sure to also benchmark, in my experience sometimes looser is better there.


I noticed better results with tighter timmings on these. But will check again.

tRFC 240 gave me an error in test 12 after 40 minutes.

Managed to finish the test at tRFC 260.



http://imgur.com/xM9cUMq


----------



## GribblyStick

Veii said:


> 0.885 is fine, it's just sub 900 whichs is required
> Well 930mV stock is bad - even 900 does fix most of the issues - the lower the better
> (870 you have to try, 860 was unstable for me)
> 
> Dont worry about SOC that much,the fabric needs it
> but inside it hates high voltages - VDDG CCD hates high voltages
> Try ManniX's Ultimate Performance powerplan, if you get any varriation
> The first 1-2 runs always are bad, because windows services try to load up & if the CPU knows how to idle down, it also takes one run of some kind of load, before C6 & DF states kick in
> 
> If you skip tCKE and Setup timings for now , you can try
> 60-20-40-20,40-20-40-20, 60-20-30-24
> as CAD_BUS options
> 6/3/3 surely will run, but it needs a bit of ClkDrvStr
> Cold boot issues purely relate to the 3rd CAD_BUS value, which you either push beyond 30 , or run 20ohm @ SETUP time value
> Sadly SETUP Time value scales by MCLK same as tCKE
> soo you have to spend a lot of time figuring the correct one out
> 
> 40-20-20-20, 3-3-15 @ 3800MT/s surely works well on 2x16gb @ tCKE 9
> But tCKE varies. You could try 16 there too or 11
> really depends on MCLK and RTTs what tCKE you use


Thanks, I'll give these a shot, but since you mentioned 2x16, a reminder just in case.
I am running 4x8.


----------



## Yviena

Is it usually procODT that affects aida64 variable latency, or other timings/voltages?


----------



## Owterspace

I didn't do any of that, what a lot of work lol. I tried using dram calculator but it did not help me at all, just made things worse iirc. To get to my current settings I loaded docp and saved the secondary's, saved my primary's, changed mem speed and IF save and exit and let er rip. Now I don't have to fight my board and my CPU, and I get wicked performance. I bet a lot of you guys could get past 1900 or 2000. I am a total noob and that is what I did.


----------



## Veii

Yviena said:


> Is it usually procODT that affects aida64 variable latency, or other timings/voltages?


all 3 of them, proc just being the leader
SOC & ClkDrvStr - affect the procODT range
CPU VDDP affects fabric stability, cLDO_VDDP affects memory controller signal quality & spectrum/phase
VDDG affect anything internally 
SOC affects the substrate and from outside to inside 

procODT is not only a "gate" inside, but also the palace guard outside 
Still it's behavior depends on outer factors too


----------



## craxton

Comalive said:


> On my B550 Gaming Edge Wifi I can now boot with 1900. A quick L3 cache speed test shows increases of 50 - 100% compared to before so they did some great work there!


have you tried the latest bios released ?AM4PIV2 1.2.0.1 

about to update myself just to see if i can still get the same 4000mhz/2000fclk oc
i already had, no nothings broke, but perhaps MSI added a setting to the bios 
to allow a "certain" voltage to be changed.

anyhow, if anyone on the B550 Gaming edge wifi board his tried this bios out, or
any board with 1.2.0.1 code, any improvements, or is it worse?


----------



## Yviena

Veii said:


> all 3 of them, proc just being the leader
> SOC & ClkDrvStr - affect the procODT range
> CPU VDDP affects fabric stability, cLDO_VDDP affects memory controller signal quality & spectrum/phase
> VDDG affect anything internally
> SOC affects the substrate and from outside to inside
> 
> procODT is not only a "gate" inside, but also the palace guard outside
> Still it's behavior depends on outer factors too


Hmm max variance I have is 0.1ns with sometimes 0.2ns but that may be background tasks I sometimes see a 0.4-0.6 jump in latency on the first run then it goes down.

Also has anyone noticed that agesa 1.1.0.0 has around 0.7-0.8ns lower latency, with the exact same timings I get 55-55.1ns with 1.1.9.0 but 1.1.0.0 gives me 54.2-54.3ns.


----------



## Comalive

craxton said:


> have you tried the latest bios released ?AM4PIV2 1.2.0.1
> 
> about to update myself just to see if i can still get the same 4000mhz/2000fclk oc
> i already had, no nothings broke, but perhaps MSI added a setting to the bios
> to allow a "certain" voltage to be changed.
> 
> anyhow, if anyone on the B550 Gaming edge wifi board his tried this bios out, or
> any board with 1.2.0.1 code, any improvements, or is it worse?


Well what I wrote pertains to v161, so yes, 1.2.0.1.


----------



## Yviena

craxton said:


> have you tried the latest bios released ?AM4PIV2 1.2.0.1
> 
> about to update myself just to see if i can still get the same 4000mhz/2000fclk oc
> i already had, no nothings broke, but perhaps MSI added a setting to the bios
> to allow a "certain" voltage to be changed.
> 
> anyhow, if anyone on the B550 Gaming edge wifi board his tried this bios out, or
> any board with 1.2.0.1 code, any improvements, or is it worse?


I wonder if anyone has reported to MSI that CPU VDDP affects stability, and should be unhidden in the BIOS, or maybe mod it in myself if it's easy.


Also @Veii did you manage to find RTT values that work perfectly with 4dimm?


----------



## Veii

Yviena said:


> I wonder if anyone has reported to MSI that CPU VDDP affects stability, and should be unhidden in the BIOS, or maybe mod it in myself if it's easy.
> 
> 
> Also @Veii did you manage to find RTT values that work perfectly with 4dimm?


Has been 
Sadly no. The people i got to use their setup & teach them ~ are busy recently
It's been around 2 days ago & less than 10 since RTT values where found. 
People need a break. I just played with CL12 settings , trying there to work with DynamicODT @ 1.66v

Nothing moved on that topic. Just have my two Patriot Viper's on me


----------



## Br3ach

Yviena said:


> Also @Veii did you manage to find RTT values that work perfectly with 4dimm?


On that topic, i wonder where 7/3/1 comes from? At least for b-die, and for IDD testing, the datasheet says:
RTT_NOM = RZQ/6 (40 Ohm in MR1); RTT_WR = RZQ/2 (120 Ohm in MR2); RTT_PARK = Disable; 

Not saying that it's better... though going to waste 3 more days testing that now ;-)


----------



## GribblyStick

Ok, I just tested with 0,8550 CPU VDDP, looks at least initially stable (30 mins or so TM5).
Latencies are improving a bit but still swinging. Now I'm between 58,4 and 57,2.
I don't suppose there is any risk in going lower voltage? at most it would be unstable?

Might it also be an idea to attempt lowering ODT again?


----------



## Veii

GribblyStick said:


> Ok, I just tested with 0,8550 CPU VDDP
> I don't suppose there is any risk in going lower voltage? at most it would be unstable?


If that passes y-cruncher maybe
TM5 is no CPU stability test , only a timings test


----------



## GribblyStick

Veii said:


> If that passes y-cruncher maybe
> TM5 is no CPU stability test , only a timings test


Which settings should I be running?
I ran two iterations of the stress tester, but it's getting late and I wasn't sure that was the test to apply?
This is with a lower still VDDP at 0,840









Haven't changed the CADBUS values from before yet, just wanted to see how low I could go with VDDP.
That would be next on the agenda I guess (after really verifying 0,840 is fine)
Still fluctuating latency, so I doubt going even lower on CPU CDDP is going to do much for that. What's the effect of lowering CPU VDDP so much?


----------



## Comalive

GribblyStick said:


> Which settings should I be running?
> I ran two iterations of the stress tester, but it's getting late and I wasn't sure that was the test to apply?


Run all the tests, 2 cycles are a bit too few though, it's easily possible that your system dies during the 3rd cycle, for example. Let it run for a few hours and see what happens I suppose.


----------



## Veii

GribblyStick said:


> Which settings should I be running?


4 cycles all tests,
special focus on BBP, SFT, FFT, N64, C19
4*18min , but maybe tomorrow then 
even 5 loops would be fine - to reach thermal equilibrium


----------



## kratosatlante

Veii said:


> Has been
> Sadly no. The people i got to use their setup & teach them ~ are busy recently
> It's been around 2 days ago & less than 10 since RTT values where found.
> People need a break. I just played with CL12 settings , trying there to work with DynamicODT @ 1.66v
> 
> Nothing moved on that topic. Just have my two Patriot Viper's on me


busy= all mining ETH or other crypto


----------



## Veii

kratosatlante said:


> busy = all mining ETH or other crypto


I don't own any crypto at all & do not do any types of stock/trading
Optimizing systems for accelerated processing is fun * ~ but stays far away from me.
* the process, not the earnings

EDIT:
And they don't seem to mine


----------



## craxton

Yviena said:


> I wonder if anyone has reported to MSI that CPU VDDP affects stability, and should be unhidden in the BIOS, or maybe mod it in myself if it's easy.
> 
> 
> Also @Veii did you manage to find RTT values that work perfectly with 4dimm?


i wrote MSI thru there EMAIL support link, but have NOT heard ANYTHING AT ALL BACK, 
i also wrote about it in the forums, i mean considering how beefy this board actually is
one should think it to have all the settings one can use? 

then again i suppose thats where the "unify" and "godlike" lineup 
come into play, as one wouldnt have any reason to go for those, other than bios reset button on board,
and "maybe" a digi readout of post codes. but since most MSI boards now days, have the LED (i would rather have it)
i could care less for a post code to trouble shoot, especially on amd side of things as sometimes its useless anyhow.

i tried the latest bios, 4 passes of y-crucher, HCI 700%, and tm5 1usmus preset 4 runs back to back, all clear with my
past settings applied. and NOTHING new in the bios, nothing i noticed anyhow. havent ran prime95 
perhaps ill allow it to run here shortly while my head hits the pillows..


----------



## yrelbirb

What do you think? Anything wrong with voltages? Micron E-die Ballistix kits

I changed my mobo from garbage gigabyte to a better msi board (for a very low cost), wondered if there's anything wrong with the new one. Apparently I have more freedom over more settings this time, SoC LLC, more voltage settings and such.


----------



## GribblyStick

OK - 5 cycles done, mostly through the 6th:


Spoiler: y-cruncher tests



Iteration: 0 Total Elapsed Time: 3.084 seconds ( 0.051 minutes )
Running BKT: Passed Test Time: 120.025 seconds ( 2.000 minutes )
Running BBP: Passed Test Time: 122.775 seconds ( 2.046 minutes )
Running SFT: Passed Test Time: 120.016 seconds ( 2.000 minutes )
Running FFT: Passed Test Time: 120.672 seconds ( 2.011 minutes )
Running N32: Passed Test Time: 121.894 seconds ( 2.032 minutes )
Running N64: Passed Test Time: 122.511 seconds ( 2.042 minutes )
Running HNT: Passed Test Time: 123.419 seconds ( 2.057 minutes )
Running VST: Passed Test Time: 121.551 seconds ( 2.026 minutes )
Running C17: Passed Test Time: 123.292 seconds ( 2.055 minutes )

Iteration: 1 Total Elapsed Time: 1099.244 seconds ( 18.321 minutes )
Running BKT: Passed Test Time: 120.012 seconds ( 2.000 minutes )
Running BBP: Passed Test Time: 122.017 seconds ( 2.034 minutes )
Running SFT: Passed Test Time: 120.022 seconds ( 2.000 minutes )
Running FFT: Passed Test Time: 120.711 seconds ( 2.012 minutes )
Running N32: Passed Test Time: 122.269 seconds ( 2.038 minutes )
Running N64: Passed Test Time: 123.007 seconds ( 2.050 minutes )
Running HNT: Passed Test Time: 123.309 seconds ( 2.055 minutes )
Running VST: Passed Test Time: 121.170 seconds ( 2.019 minutes )
Running C17: Passed Test Time: 122.983 seconds ( 2.050 minutes )

Iteration: 2 Total Elapsed Time: 2194.748 seconds ( 36.579 minutes )
Running BKT: Passed Test Time: 120.014 seconds ( 2.000 minutes )
Running BBP: Passed Test Time: 122.615 seconds ( 2.044 minutes )
Running SFT: Passed Test Time: 120.016 seconds ( 2.000 minutes )
Running FFT: Passed Test Time: 120.482 seconds ( 2.008 minutes )
Running N32: Passed Test Time: 121.958 seconds ( 2.033 minutes )
Running N64: Passed Test Time: 123.432 seconds ( 2.057 minutes )
Running HNT: Passed Test Time: 123.312 seconds ( 2.055 minutes )
Running VST: Passed Test Time: 121.406 seconds ( 2.023 minutes )
Running C17: Passed Test Time: 123.329 seconds ( 2.055 minutes )

Iteration: 3 Total Elapsed Time: 3291.314 seconds ( 54.855 minutes )
Running BKT: Passed Test Time: 120.015 seconds ( 2.000 minutes )
Running BBP: Passed Test Time: 122.478 seconds ( 2.041 minutes )
Running SFT: Passed Test Time: 120.023 seconds ( 2.000 minutes )
Running FFT: Passed Test Time: 120.591 seconds ( 2.010 minutes )
Running N32: Passed Test Time: 121.700 seconds ( 2.028 minutes )
Running N64: Passed Test Time: 123.597 seconds ( 2.060 minutes )
Running HNT: Passed Test Time: 123.071 seconds ( 2.051 minutes )
Running VST: Passed Test Time: 121.574 seconds ( 2.026 minutes )
Running C17: Passed Test Time: 123.466 seconds ( 2.058 minutes )

Iteration: 4 Total Elapsed Time: 4387.834 seconds ( 73.131 minutes )
Running BKT: Passed Test Time: 120.037 seconds ( 2.001 minutes )
Running BBP: Passed Test Time: 122.694 seconds ( 2.045 minutes )
Running SFT: Passed Test Time: 120.018 seconds ( 2.000 minutes )
Running FFT: Passed Test Time: 120.595 seconds ( 2.010 minutes )
Running N32: Passed Test Time: 122.200 seconds ( 2.037 minutes )
Running N64: Passed Test Time: 122.570 seconds ( 2.043 minutes )
Running HNT: Passed Test Time: 123.451 seconds ( 2.058 minutes )
Running VST: Passed Test Time: 121.773 seconds ( 2.030 minutes )
Running C17: Passed Test Time: 123.388 seconds ( 2.056 minutes )



Hope C17 is fine, I don't see a C19 option. I'll continue testing RAM settings after work.
That said, given that you said 0,860 was unstable for you and 0,840 seems fine, should I keep trying to lower this?
Same for CLDO VDDP and CCG actually, I never tried lower settings I simply went with what you had in some posts. CLDO VDDP 0,900 (from the Easy setup, previously 0,880) and CCG of 0,940.
I was now going to try the different CADBUS settings between RTT 703, 603 and 633 and leaving procODT at 34.
I only tried launching once with 32, before moving to 34 but I realize I could maybe get lower to work with multiple boots.


----------



## mongoled

@Veii,

I see you keep saying this as if it is some golden rule for all samples but for all the 5600x I have tested on my current motherboard I have not seen this to be the case.

What am I refering to? I am refering to VDDG CCD.

For my setup, its like clock work. If VDDG CCD is too low, I see it instantly on AIDA64 latency results.

Anything lower that 1.0v results in higher L1 latency when pushing past 4000 mhz MCLK, the more I drop VDDG CCD the higher the latency goes.

Ideally I need another motherboard to test, but with my X570 Unify, this is what I see.

For 3800 mhz I use 1.005v, for +4033 mhz I use 1.025v.

And I dont know why you dont want to answer my questions either through PM or through normal forum posts.

Ive asked several times and you just avoid the subject, in the past you mentioned running A0 with A2, so I tested this and it killed both A0 sets.

I thought this maybe just bad luck and asked you if you had seen anybody else experience this but you never answer.

Today I found out that some one on hwbot also had a pair of A0 die when used it tandem with A2s.

Now its not an issue for me with regards to "blaming" someone, but its very rude not to acknowledge someone when they simply decided to take the risk and follow some advice !

So I hope you finally decide to take some responsibility with the advice you have given and understand that where I may be quite relaxed about some hardware dying, others may not be, hence the reason to be clear, open and honest about any issues we see.........


----------



## hazium233

Yviena said:


> I wonder if anyone has reported to MSI that CPU VDDP affects stability, and should be unhidden in the BIOS, or maybe mod it in myself if it's easy.





craxton said:


> i wrote MSI thru there EMAIL support link, but have NOT heard ANYTHING AT ALL BACK,
> i also wrote about it in the forums, i mean considering how beefy this board actually is
> one should think it to have all the settings one can use?


Does AMIBCP work for MSI B550? I haven't tried it, although I have looked in the B550 Gaming Edge bioses and CPU VDDP is in the Overclocking tab in between CLDO VDDP and CPU 1.8.

Reason I was looking though is that I can't find VTT DDR. Do the MSI B550s not have this at all, or am I blind?


----------



## BloodDivine

yrelbirb said:


> View attachment 2481701
> 
> 
> What do you think? Anything wrong with voltages? Micron E-die Ballistix kits
> 
> I changed my mobo from garbage gigabyte to a better msi board (for a very low cost), wondered if there's anything wrong with the new one. Apparently I have more freedom over more settings this time, SoC LLC, more voltage settings and such.


Try that, the only questionable thing that you might need to change it SoC but you should be able to get away with 1.05 LLC3


----------



## Trusconi85

Owterspace said:


> I've been running mine like this for a couple of days. It runs everything. No errors or crashing, she's good I think. I cant manually run it over 4600 1.225v, but can boot into windows all the way up to 4900, but wont pass serious testing. Weird. I am letting it run itself right now so cache scores are a bit weak because of it, but I'm sure if I ran it a few times I could bump em up a bit..
> 
> 
> 
> View attachment 2481580


How many Watt need the 5600X to run @ 4850?
Mine stock use 76W and @4700 (with stock voltage) take 101w


----------



## Veii

@mongoled wait a bit
"Acknowledge potentially Hardware dying" ~ on "too low" VDDG CCD ?
I don't underatand the point

I'll check PMs, usually do but not always answer.
If its something easy i answer the moment i read it
If its asking for help requiring a long session, i answer when i have the time to spare

Quite honestly, i'm reading this for the first time. The part about too low voltage doing hardware damage & being responsible
Although as you might know, i do follow all 3, gigabytes, msi unify's and asus crosshair's thread
There is interesting information to read ~ soo i do know about the usb issues, audio crackling issues and nvme crashing issues

But the thing is,
I can not relate 😐
I don't know the answer on that question
It simply doesn't apply to me, soo i have no idea where to start looking for
Absolutely it can be an issue and that is for people to figure out what voltage they use
As an entry point, my set didnt make issues on neither asrock nor asus boards 
~ soo i really don't know what us wrong on gigabyte and msi setups
Asus has own issues, but that's beside the point 
Even played cross porting bioses to learn stuff, but i dont know about the "being responsible" you want from me.
I simply don't know about the audio issues you guys have

I'll check PMs today again, like checked yesterday too & will double check if i've missed something from you
Today's been 12 notification & i just woke up
Yesterday around 7
I really don't understand the "starting to be responsible" part. Something seems missjudged 😐


----------



## Yviena

hazium233 said:


> Does AMIBCP work for MSI B550? I haven't tried it, although I have looked in the B550 Gaming Edge bioses and CPU VDDP is in the Overclocking tab in between CLDO VDDP and CPU 1.8.
> 
> Reason I was looking though is that I can't find VTT DDR. Do the MSI B550s not have this at all, or am I blind?


*** how come cheaper boards come with CPU VDDP but not x570 tomahawk.

@Veii it also seems 7/3/1 RTT with TCKE 1 and 000 setup time is more stable than 6/3/3 with 3315 on my 4x8 setup idk why.


----------



## ManniX-ITA

@mongoled 

Me and Veii discussed more than once here on the forum the right VDDG CCD voltage.
And we both stated multiple times that _*it's always dependent on the specific CPU sample*_.

Whatever "golden rule" is advised, like everything else stated here, it's *our *golden rule.
Based on our and others experience, knowledge and opinion.

We don't do it for business, nor we are a testing center with hundreds of platforms to verify.
We don't work for AMD or any board manufacturer.
It's always a personal opinion and it's up to you to judge how to treat the information you get.

What @Veii suggested is proven to work most of the times for 5600/5800x CPUs.
Your could be an exception.

What I suggest for 5900x/5950x is to keep it higher; works best for me and I've also explained how to test it.
Seems to work most of the times for CPUs with a 2nd CCD as reported many times.
But still there could be exceptions there too.

This is almost all reverse engineering, deductions.
There are too many hidden variables to be 100% sure of anything.



mongoled said:


> Now its not an issue for me with regards to "blaming" someone, but its very rude not to acknowledge someone when they simply decided to take the risk and follow some advice !
> 
> So I hope you finally decide to take some responsibility with the advice you have given and understand that where I may be quite relaxed about some hardware dying, others may not be, hence the reason to be clear, open and honest about any issues we see.........


I guess you mean about these A0 kits dying when mixed with A2?

I think it's unfair to blame him, which is what you are doing.
It's not like you paid for this information and got a warranty over it.
If he suggested to test mixing them and they died, you have to bear the responsibility.
Your missing acknowledgment is just that as everyone here that tries to help and like to experiment, he does it in best effort mode.

Honestly I would have suggested the same.
There's absolutely no reason why an A0 kit should die when mixed with an A2.
Seems more likely to me these A0 kits where defective from the start.

Unless you applied insane voltages, which you would have mentioned I guess.
Even catastrophic resistance settings for the termination are unlikely to burn a PCB so easily.
But I've never seen anyone complaining about A0 kits dying like that just testing some settings.


----------



## ManniX-ITA

hazium233 said:


> Does AMIBCP work for MSI B550? I haven't tried it, although I have looked in the B550 Gaming Edge bioses and CPU VDDP is in the Overclocking tab in between CLDO VDDP and CPU 1.8.
> 
> Reason I was looking though is that I can't find VTT DDR. Do the MSI B550s not have this at all, or am I blind?


For what I've read it doesn't work anymore.
You can use it to check the Form ID for the option you need.
The only way to change it is to extract the Setup package with IFR and change the visibility with an Hex editor.
MSI BIOS is even more nasty than the usual due to some peculiarities in the packaging.

The Unify-X does have VTT voltage:



Spoiler


----------



## mongoled

You both misunderstand me, I don't attribute blame to anyone! We are a community here sharing information, my issue is that I asked Veii about the issue of dying A0s when paired with A2s in a couple of threads and by PM with no acknowledgement, that is my gripe, nothing more.

The vddg ccd has nothing to do with dying A0s, I was just saying that of the 5 Ryzen CPUs I've tried on this motherboard, non of them followed what what's being said regards using VERY low VDDG CCD.

Thats all, as many new peeps come here and read this stuff, so just wanted it to be known that my experience with x570 unify don't mirror the low vddg ccd characteristic


----------



## ManniX-ITA

mongoled said:


> You both misunderstand me, I don't attribute blame to anyone! We are a community here sharing information, my issue is that I asked Veii about the issue of dying A0s when paired with A2s in a couple of threads and by PM with no acknowledgement, that is my gripe, nothing more.
> 
> The vddg ccd has nothing to do with dying A0s, I was just saying that of the 5 Ryzen CPUs I've tried on this motherboard, non of them followed what what's being said regards using VERY low VDDG CCD.
> 
> Thats all, as many new peeps come here and read this stuff, so just wanted it to be known that my experience with x570 unify don't mirror this characteristic


It was indeed not very well expressed 
We are also all non-native English speakers so it's hard sometimes.

Acknowledge is fine but "taking responsibility" can be literally read as "it's your fault, I'm blaming you".
As said, he's here helping and sharing info for fun. Best effort.
Let's not stress him please, we enjoy his presence! 

Thanks for sharing the info about CCD voltage, it's interesting.
Were those all 5600x and tested on one motherboard?


----------



## hazium233

Yviena said:


> *** how come cheaper boards come with CPU VDDP but not x570 tomahawk.


Sorry if I wasn't clear above. VDDP isn't exposed in the bios, but if you go into the AMIBCP editor then it is listed in between the values I quoted.

If this was an old Asus 300 series, then I might just be able to change the "access / use" field from Default to User or something, and expose it. But guess it needs hex editing as ManniX-ITA says to mod it in.


----------



## Veii

mongoled said:


> You both misunderstand me, I don't attribute blame to anyone! We are a community here sharing information, my issue is that I asked Veii about the issue of dying A0s when paired with A2s in a couple of threads and by PM with no acknowledgement, that is my gripe, nothing more.
> 
> The vddg ccd has nothing to do with dying A0s, I was just saying that of the 5 Ryzen CPUs I've tried on this motherboard, non of them followed what what's being said regards using VERY low VDDG CCD.
> 
> Thats all, as many new peeps come here and read this stuff, so just wanted it to be known that my experience with x570 unify don't mirror the low vddg ccd characteristic


Now i understand what you mean

2 things 


> I did not recommend anymore pairing A0s and A2s together since you had issues.


That part of "taking responsibility" should be invalid. I've noticed the issue but at the time back and still a bit today, had no idea what the issue could be


> The voltage example shared, you probably mean here AMD max overclocking voltage is still valid and was tested on a single CCX 5800X, my dual CCX 5600X, a 5900 & a 5950X. Actually 3 5950X but one intensively


Neither of audio issues nor crashing USB issues. It has to be an MSI and Gigabyte Bios thing ~ but i remember very well that my old post 2 months at this point before Patch-C mentioned that this "might change on newer AGESA"
Currently i have not encountered issues on SMU 56.44/45
But i give you a point, because maybe potentially SOC Voltage does mask it ~ >1.2.0.0 with dLDO_Injection voltage control ~ needs to be researched more

About the dying A0 dimms issue
My current set are Viper 4000, A0's
I've only recently nearly killed one of the dimms (temporary loss of one memory channel)
~ where the issue was pairing high RTT (0/0/5) with voltage @ and beyond 1.56v. 1.52 caused PCB hardcrashes already
This was one of the reasons i researched more and spared a lot of time to figure out 7/0/6 for them with how tCKE works and overall powerdown
Meanwhile i'm dailying 1.58-1.62v on them

I think the issue has to do with far to strong RTT values (which where usually advertised for 4 dimms) ~ RTT Park being the target
But even looking back at it, it continues to barely make sense
Slave sets on Daisy Chain should not get more voltage but rather less
For a critical spike to have happen - it would need 1.6v as a baseline on your setup , then maybe paired with strong RTTs , it could be an issue
But it yet makes no sense ~ as a crash should happen or a loss of a memory channel (temporary)
But not a perma death.

Nevertheless from which perspective i take a look at it, it makes no sense
A0s are sensitive, but to really kill them instantly ~ it would need a spike of >1.7v or at least continueous 1.6v
The only thing i can relate back now ~recently~ , is my nearly death experience on them. But that was purely my fault for shoving high voltage on them and torturing them
Yet they survived. I just don't know what to answer on your issue. It makes no sense
It needs more information and what RTTs you used (again only knowing now it could be an issue)
but i still don't know what to tell you.
"Unfortunate" but it seems not to be the "pairing A0 with A2 or A1" part that was the issue.
It's either high voltage, or high RTT combined with high voltage. Or even something completely external.
~I don't know~

I'm sorry & sad that you had only a negative experience & something unforeseen was the issue
But the "pairing A0 with A2" part ~ i don't think was the issue for the failure.
First it makes no sense whatsoever, alone by how Daisy Chain boards are designed
And 2nd, i don't know how or where it's been messed up "twice".

This probably needs a research for which RTTs on this combination really are dangerous,
But it sounds like a wasteful mission. Someday the research should be done ~ right now i can't afford it.
Nevertheless, you where neither ignored nor i try to hide anything.
I'm sorry for your loss, but i simply do not know (back then) while having only subtle an idea now, what could've gone wrong 🙇‍♂️🙇‍♂️


----------



## Dasa

mongoled said:


> For my setup, its like clock work. If VDDG CCD is too low, I see it instantly on AIDA64 latency results.
> Anything lower that 1.0v results in higher L1 latency when pushing past 4000 mhz MCLK, the more I drop VDDG CCD the higher the latency goes.


Had a look back through all my AIDA64 tests and they all have exactly the same L1 latency 0.8ns and it is currently undervolted to 900mv.
Good to know it can happen though thanks.


----------



## Comalive

ManniX-ITA said:


> What I suggest for 5900x/5950x is to keep it higher; works best for me and I've also explained how to test it.
> Seems to work most of the times for CPUs with a 2nd CCD as reported many times.


What voltage (range) would you recommend me to test?
I am running a 5900X with 2000 fclk and while I pass all the stress tests, I also get WHEA 19 errors like there's no tomorrow.
I was using .94 v VDDG CCD most of the time, I also tried .9 and .86...still tons of WHEA 19s.
Now I am testing .98v after reading your post, that still doesn't seem to alleviate the error spam.


----------



## ManniX-ITA

Comalive said:


> What voltage (range) would you recommend me to test?
> I am running a 5900X with 2000 fclk and while I pass all the stress tests, I also get WHEA 19 errors like there's no tomorrow.
> I was using .94 v VDDG CCD most of the time, I also tried .9 and .86...still tons of WHEA 19s.
> Now I am testing .98v after reading your post, that still doesn't seem to alleviate the error spam.


If you get tons of WHEA then it's very likely something you can't fix with a different CCD voltage.
I'd check anyway with SOC at 1.1V and higher and IOD at 1060.
But it's very likely you need to wait the long time promised and never delivered fix from AMD to run properly at FCLK 2000.


----------



## GribblyStick

@Veii 
tried 
60-20-40-20 -> Bluescreens
40-20-40-20 -> froze the system and required CMOS + diagnosis to post.
60-20-30-20/24 was worse in variance, however, it also led to the lowest latency so far.

It went from 56,5 - 59,3 on CkeDrvStr : 20 and 56,7 - 62 on 24.
This was all on 7/0/3 RTT. 

Still curious if there is a benefit to trying lower CCD/CLDO/CPU VDDP/procodt? 
I mean in terms of combating the variance.


----------



## mackbolan

Veii said:


> I wish we could know which ABL you are on
> But AMD PBS is nearly always hidden/locked on these bioses
> 
> And not everyone shares a Zentimings System info report (latest ZT beta/debug)
> there are interesting things out, and interesting options to modify
> But it's too advanced and probably many still are debugging other things
> 
> I personally still focus on this annoying throttle limit > & = 2100FLCK
> it's a loss of 3ns, but at least i get no WHEA at all - only hard crashes
> 
> There are many little things to focus on
> And it's probably just a badly compiled bios and even more likely with an ABL that has strange limits
> Put broken memory training on it, and we have "non bootable" holes @ 1900
> I had that on Patch C and didn't want to touch it ever again
> Took ASRock 4-5 months to release a fixed non 1.1.0.0 broken AGESA
> Which had a broken ACPI 6.3 table ~ bad firmware on it's own
> (could be tested with SSDTTime - Dump DSDT ~ hackintosh)
> 
> It's not ignored, but we can just hope for new bioses ,till X person starts to push out mods for all the boards
> Who ever X person is, will be seen
> We are still in the research & learning phase of "what works well" and "what is broken"
> 
> Which speaking of,
> DF_C-States got broken on 1.2.0.X (ty amd)
> They result in random reboots or at best WHEA errors ~ disable them but keep Global-C States Generation functioning
> 
> EDIT:
> B550 boards are compiled and build on ACPI 6.3 standard
> X570 are on 5.X - B550 have own children illnesses on their own
> Barely any brand cares to make a clean DSDT, as it's not needed when you follow the microsoft compiler ~ it doesn't check for errors
> Barely anyone focuses on ACPI standards to fix errors 😐
> 
> 
> I have an idea what it is and why
> But not only do i lack confidential signing tools for firmwares
> But also the time to shape my IDE knowledge
> In short ~ i s*ck at it still , but have atm other priorities like the "maximizing" FCLK part & figure out working voltages for 2167 FCLK
> ASRock doesn't have WHEA's, soo i'm free from that suffer at least
> 
> Oh i would need to clone myself 2 more times too have enough time in researching everything i want
> & getting somehow to money , in order to pay the rent
> ~ too much, can't always do 30h sessions
> 
> EDIT2:
> Current bios is wonderful , but they've broken DF_C-States
> well it took them long time to fix this DSDT issue _(released yesterday)_


I have an AsRock X570 Phantom Gaming 4S, TeamForce Extreeme 3733 DDR4 Gaming (running with custom timings) 1867 IF, and a new 5600X (manual all core OC 4675 1.29v) with a Corsair H110i GTX and Thermal Grizzly Kryonaut. Problem I have is the "3800/1900 hole" is still in this 1.2.0.0 (3.90) BIOS! So I'm stuck at 3733/1867 or oddly, I can jump to 4000/2000 with a few minor adjustments to my RAM to pass TM5 and MemTest Hci, but have forever WHEA 19's. I can scale the SOC up or down to a point, 1.15 seems "ok'ish", CLDO VDDP .947, CCD 1.04, IOD 1.04. Any variation doesn't end the error 19's. I tried turning off DF states and C-States but you say to leave c-states on, so I can try that. I'll post my Zen Timings, but I think this BIOS is also broken since I can go to any setting above 3800/1900 (no post), 3933, 3966 work but same error 19 an instability is worse than 4000/2000. It's nearly stable at that but will crash on an Aida Stability test and higher workloads. Is 1.0.0.8 or 1.0.0.0 D better? I really think the CPU can do it and the RAM or it wouldn't boot into Windows. Maybe going to an Asus TUF Gaming Pro or a Gigabyte Aorus something $200 or less USD would work? This board doesn't even have LLC! So my voltages don't stay real tight, feels like I'm going a little high to hit a steady lower voltage. Educated guessing...


----------



## Veii

GribblyStick said:


> @Veii
> tried
> 60-20-40-20 -> Bluescreens
> 40-20-40-20 -> froze the system and required CMOS + diagnosis to post.
> 60-20-30-20/24 was worse in variance, however, it also led to the lowest latency so far.
> 
> It went from 56,5 - 59,3 on CkeDrvStr : 20 and 56,7 - 62 on 24.
> This was all on 7/0/3 RTT.
> 
> Still curious if there is a benefit to trying lower CCD/CLDO/CPU VDDP/procodt?
> I mean in terms of combating the variance.


Soo 60 was too strong for your dimms for some reason. /3 Park shouldn't be that strong, but you can give these CAD_BUS values another try at 634
If you still BSOD or it fully refuse to post , then it's just too strong ~ but i doubt, since 4 dimm users can go up till 120ohm ClkDrvStr (reasonability aside, but they can)

I wonder why you have issues with CsOdtDrvStr at 40 🤔

Soo you've eliminated the probability of powerplan issues ?
Can you try to increase the EDC limit a bit, or put it under AMD Overclocking - PBO - Advanced - Motherboard limits
Just to doublecheck if it's a run to run power reserve variance ?
The last thing that remains is your windows potentially being bloaty ~ to have such a big variance when y-cruncher passes and TM5 too ?
=================
@Comalive you might want to try RTT_PARK as /4 instead of /3
RTT_WR /3 is easy, but /2 is already very hard to maintain and strong 
You likely want to "increase" RTT Park value , rather "make it lower, take away the strength of it" , soo a higher divider
If it refuses to post, you'll have learned something about your dimms at least 

But i think it would work
even /3 is already too much


----------



## Veii

mackbolan said:


> I have an AsRock X570 Phantom Gaming 4S, TeamForce Extreeme 3733 DDR4 Gaming (running with custom timings) 1867 IF, and a new 5600X (manual all core OC 4675 1.29v) with a Corsair H110i GTX and Thermal Grizzly Kryonaut. Problem I have is the "3800/1900 hole" is still in this 1.2.0.0 (3.90) BIOS! So I'm stuck at 3733/1867 or oddly, I can jump to 4000/2000 with a few minor adjustments to my RAM to pass TM5 and MemTest Hci, but have forever WHEA 19's. I can scale the SOC up or down to a point, 1.15 seems "ok'ish", CLDO VDDP .947, CCD 1.04, IOD 1.04. Any variation doesn't end the error 19's. I tried turning off DF states and C-States but you say to leave c-states on, so I can try that. I'll post my Zen Timings, but I think this BIOS is also broken since I can go to any setting above 3800/1900 (no post), 3933, 3966 work but same error 19 an instability is worse than 4000/2000. It's nearly stable at that but will crash on an Aida Stability test and higher workloads. Is 1.0.0.8 or 1.0.0.0 D better? I really think the CPU can do it and the RAM or it wouldn't boot into Windows. Maybe going to an Asus TUF Gaming Pro or a Gigabyte Aorus something $200 or less USD would work? This board doesn't even have LLC! So my voltages don't stay real tight, feels like I'm going a little high to hit a steady lower voltage. Educated guessing...
> View attachment 2481748
> View attachment 2481750


I don't think your bios is "new"
i can read SMU 56.43 not 56.44
ASRock has the AMD PBS menu open for everyone
Can you check the ABL version there

You don't want to run 24-24-24-24 CAD_BUS
This did not work well on Matisse and still doesn't work well on Vermeer

Is that 3733 1T set really stable ?
tWR looks off , too low & at what voltage.

Anyways, CAD_BUS you want to run "at least" 24-20-20-24
But this will cause post issues and issues with memory training on Vermeer
Soo we run it higher 40-20-30-20, 40-20-40-40 ,60-20-30-24
Anything with 30+ on the 3rd value, to combat broken memory training since AGESA 1.1.0.0 Patch C
60-20-20-20, can also run , but 2x 8gb rather likes 40-20-20-20 with CAD_BUS Setup Timings matched to the frequency

My main set used 40-20-24-24 ~ before figuring out a better method








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com





If you have on your board
I just checked, never seen the "S" Special edition of the PG4
But bios 3.40 is SMU 56.33 (Patch B)
While the one you use is NOT 1.2.0.0 but 1.1.9.1 or 1.1.9.0v2
It's the alpha pre-release of 1.2.0.0 with the Cache fix
It pretty much should have the same buggy symptoms that 1.1.9.0/1.1.8.0 users had

Problem is, you don't have any "good" bios to fall back
They skipped the good release, and directly went to Patch-C with the 1900 FCLK lock (i mean maybe ASRock didn't know)
Do you want to request and write the support team for a bios with
SMU 56.44 ABL 0C074010
or an old one before 3.40 with
SMU 56.30 & ABL 09084010

Both have no 2000 FCLK Lock and can go up till 2167 (2100 package throttles, but that's besides the point)
Both have no WHEA issues either (i couldn't find any, i just get hard shutdowns on little problems)

You can also try to downgrade to 3.40 and see if you can post 1967/2000 FCLK or there is a 1900FCLK lock (for science)
But i think, you are out of luck here
Try to write them, or downconvert with flashrom from The Stilt's instructions & post #4 for visualisation








AGESA FW stack patched bioses for 3rd gen


I decided to put these under a separate thread, since there are already quite many bioses available. File naming: Original bios build (version), M = modified, FI (4649 ASCII, i.e. SMU 46.49). Besides the actual SMU FW, these files also contain up to date PSP, PMU (IMC) FWs, bootloaders and...




www.overclock.net




The bioses here are old, but the flashrom flash utility is usable for our AM4 boards
(with little exceptions of boards with internal bios flash buttons)

EDIT:


> Maybe going to an Asus TUF Gaming Pro or a Gigabyte Aorus something $200 or less USD would work? This board doesn't even have LLC! So my voltages don't stay real tight, feels like I'm going a little high to hit a steady lower voltage. Educated guessing...


Sinopower
SM4337
30V, 55A, 7.1mΩ
(high-side x1)
&
SM4336
30V, 65A, 5.3mΩ
(low-side x1)

Are kind of Low end , overall the SM lineup
But quite honestly ~ ASRock hides switching frequency and loadlines on many of the bioses
I do like them because of many reasons - but there are a lot of little things , they mess up
(I give them maybe too often a hard time ~ i guess)
Here is an example:


Spoiler














Meanwhile "marketing lies"


Spoiler














Also coming back to

__ https://twitter.com/i/web/status/1348312213715562499
I don't understand ASRock sometimes
They update their X570 lineup first and let B550 users wait a lot
Then they try not to care about the good boads like the X570 ITX or B550 ITX
Or mess up the X570 Taichi on the layout and PCIe lanes spread
Put good Renesas 90A stages only on 2 boards while the rest has to run lower end Vishay = Renesas, 50A stages
I don't understand the designer teams priority ~ yet when they update the bios, they do more than the competitor's
I just wish them to make less tiny errors in the future.
Currently Biostar leads on the "open bios" side of things for their 130/140$ boards with the same powerstages the 200$ B550 ITX/AX comes with

EDIT 2:
uPi Semi uP1961S 4 Phase drivers & doublers
They either didn't get the EFI module for loadline support , or it simply is not possible
I think Asus uses the same on their current boards but i am not entirely sure
They rebrand their PWM and Mosfets 
But this is the reason you miss frequency and loadline control
Above reasons are just ASRock intentionally being lazy


----------



## Dasa

Had to back off on the tRFC a bit but have now been able to drop V a lot and it has passed several loops of y-cruncher, Prime95 Single thread and hours of TM5.
1.49+ VDIMM was running into issues when the ambient hit 35c even with a 2200RPM 90mm fan hard against the RAM.

Any other settings I should try? 


TimeSpy CPU Score 13496









101x48.5=4898.5MHz max and distance below max during per core prime95
Scaler X3, LLC OFF.
CORE #0 13 CPPC-150, Curve-11 =1304mV max 15.510W
CORE #1 9 CPPC-146, Curve+1 =1384mV -50MHz 18.136W
CORE #2 6 CPPC-139, Curve-5 =1385mV -10MHz 18.814W
CORE #3 0 CPPC-127, Curve-5 =1374mV -40MHz 18.276W
CORE #4 3 CPPC-135, Curve-6 =1386mV -20MHz 17.573W
CORE #5 5 CPPC-143, Curve-3 =1384mV -20MHz 17.499W
CORE #6 5 CPPC-131, Curve-2 =1364mV -100MHz 16.470W
CORE #7 12 CPPC-150, Curve-17 =1271mV max 15.179W

Even in a 12c ambient with a custom loop the 5800X still quickly hits 90c and thermal throttles while running Y cruncher with default PBO limits. I am seriously considering lapping this CPU.


----------



## PJVol

Veii said:


> 2100 package throttles, but that's besides the point


Curious, what you meant ).
Just PM'd you, but forgot to mention, that in a 1933-2133 range, the 2000 IF run is somehow fall out of context, since PC is simply unusable with it (sometimes turn desktop anination in windows to slideshow). Any other fclk in that range may give from a 10's to 100's WHEA's, and, despite performance degrade, PC works.

PS: here's abl and other parts


----------



## Veii

PJVol said:


> Curious, what you meant ).
> Just PM'd you, but forgot to mention, that in a 1933-2133 range, the 2000 IF run is somehow fall out of context, since PC is simply unusable with it (sometimes turn desktop anination in windows to slideshow). Any other fclk in that range may give from a 10's to 100's WHEA's, and, despite performance degrade, PC works.
> 
> PS: here's abl and other parts
> View attachment 2481767


Your bios is exactly the same as mine
Nearly one to one
















It's funny how you get WHEA errors and i don't get any ever. Same for the X570 ITX/TB3
No WHEAs on anything, just insta shutdowns on little issues

I wish you had a SPI Flasher - soo you can jump to the ITX bios
Sadly ASRock seems special on this lineup , and only Gigabyte and Biostar users can convert back and forth
Maybe MSI users too ~ but i would not suggest to change brand-convert with ASRock boards
This is a bit "much" voltage & it tries to be applied on post 







=====================
Package Throttle means:
The CPU & Cache slows itself intentionally down after a certain Fabric clock
It adds latency to keep itself stable & for us cache latency freezes at 10.9ns beyond 3800MT/s
I think that was the resolve to prevent WHEAs while keeping high Cache Speed up
Frequency doesn't change it anymore sub 10.9ns and inter-core latency increases a bit
Although i hit 92GB/s finally on it instead of 80

The cache boost fix seems to relate to the ABL - although i tested it breaking with different Performance Enchancers modes
Soo it's an MSR Mode Register that is clonable down to older bioses_
It's neither AGESA nor a microcode that fixes L3 boost ~ the unlock is different and kind of "stupid/easy"

I think the MSI Latency enhance, and ASUS fMax (part of it) does play a similar role
Gigabyte on their current bioses >F33a does have a 150Mhz Clock override on stock
I think ASUS does the same in the hidden but runs under 2X Scalar
Brands cheat these days ~ you can not trust & compare them 1:1 anymore & on "manual" you break more & think you lose performance ~ compared to hidden defined AUTO values
=====================
For me the loss is around 3ns added latency after using 2100FCLK (if tamed)
Compared to being on the 20.67 multiplier & using BLCK
I think on more parts throttle happens, as the only way to get sub 50ns is to use BLCK.
By a normal method the CPU throttles down somehow ~ it's strange





详解5800X（ZEN3）如何最高稳定你的FCLK！ - 电脑讨论 - Chiphell - 分享与交流用户体验


详解5800X（ZEN3）如何最高稳定你的FCLK！,说明：BIOS版本差异存在巨大，本贴所用BIOS版本为1.1.00，另外1.2.00准备上一新BIOS另一贴，请留意。 ZEN3经过一系列的优化和微调架构后其性能已超越同期的英特尔 ...,电脑讨论,讨论区-技术与经验的讨论 ,Chiphell - 分享与交流用户体验




www.chiphell.com




This is the thread about the intentional SOC latency throttle and Package Throttle part


----------



## mackbolan

Veii said:


> I don't think your bios is "new"
> i can read SMU 56.43 not 56.44
> ASRock has the AMD PBS menu open for everyone
> Can you check the ABL version there
> 
> You don't want to run 24-24-24-24 CAD_BUS
> This did not work well on Matisse and still doesn't work well on Vermeer
> 
> Is that 3733 1T set really stable ?
> tWR looks off , too low & at what voltage.
> 
> Anyways, CAD_BUS you want to run "at least" 24-20-20-24
> But this will cause post issues and issues with memory training on Vermeer
> Soo we run it higher 40-20-30-20, 40-20-40-40 ,60-20-30-24
> Anything with 30+ on the 3rd value, to combat broken memory training since AGESA 1.1.0.0 Patch C
> 60-20-20-20, can also run , but 2x 8gb rather likes 40-20-20-20 with CAD_BUS Setup Timings matched to the frequency
> 
> My main set used 40-20-24-24 ~ before figuring out a better method
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> If you have on your board
> I just checked, never seen the "S" Special edition of the PG4
> But bios 3.40 is SMU 56.33 (Patch B)
> While the one you use is NOT 1.2.0.0 but 1.1.9.1 or 1.1.9.0v2
> It's the alpha pre-release of 1.2.0.0 with the Cache fix
> It pretty much should have the same buggy symptoms that 1.1.9.0/1.1.8.0 users had
> 
> Problem is, you don't have any "good" bios to fall back
> They skipped the good release, and directly went to Patch-C with the 1900 FCLK lock (i mean maybe ASRock didn't know)
> Do you want to request and write the support team for a bios with
> SMU 56.44 ABL 0C074010
> or an old one before 3.40 with
> SMU 56.30 & ABL 09084010
> 
> Both have no 2000 FCLK Lock and can go up till 2167 (2100 package throttles, but that's besides the point)
> Both have no WHEA issues either (i couldn't find any, i just get hard shutdowns on little problems)
> 
> You can also try to downgrade to 3.40 and see if you can post 1967/2000 FCLK or there is a 1900FCLK lock (for science)
> But i think, you are out of luck here
> Try to write them, or downconvert with flashrom from The Stilt's instructions & post #4 for visualisation
> 
> 
> 
> 
> 
> 
> 
> 
> AGESA FW stack patched bioses for 3rd gen
> 
> 
> I decided to put these under a separate thread, since there are already quite many bioses available. File naming: Original bios build (version), M = modified, FI (4649 ASCII, i.e. SMU 46.49). Besides the actual SMU FW, these files also contain up to date PSP, PMU (IMC) FWs, bootloaders and...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> The bioses here are old, but the flashrom flash utility is usable for our AM4 boards
> (with little exceptions of boards with internal bios flash buttons)


Thanks for the quick reply. Yes, that tWR is stable, it was "12" and "stoney" from the AsRock Discord said to try it at "10", it did get me lower DRAM Calc scores and he had me change the tRRDS/tRRDL to "4" and that all increased my write/read/copy quite a bit and lowered the DRAM Calc test time. The tRFC is a bit low and should be more like "304" or there about, DRAM voltage is 1.41v and I've run Memtest Hci to 800% or overnight. For the "4000" RAM OC I increased the DRAM voltage to 1.45v. I'm not sure why the DRAM voltage isn't showing in Zen Timings. The BIOS is the latest for my board, listed on AsRock's site as 3.90, which i had to do with my former 3600X CPU. ASRock > X570 Phantom Gaming 4S is the page. I see that the FW isn't the same number as most are listing as "new", are you sure you're not looking at the "new" 1.2.0.1 AGESA that AsRock hasn't released for my board yet?

I have been back and forth with AsRock since last April when I bought this on sale, instead of paying ~$50 more for the Gigabyte Elite. This wouldn't post to 3733 with the 3600X for 4 months. I had to figure out how to time RAM for the first time in my 25 years building PC's, lol. I ran it at 3600/1800 until the 3.10 BIOS where it allowed for the 3733 but not with 1867, got WHEA errors. So, I went back to 3600/1800, tightened the RAM timings further down and lived with it. I found out that the 5600X could run at 1900 IF or even 2000, and I wanted to upgrade to match my overpriced RX 6800, so I bought one. 

The PBO 2 is garbage, I learned that rather quickly, and moved on to all core OC of 4700/1.30v but the temps weren't the greatest with TG-7 paste, so I backed down to 4675 and 1.275v and stayed there even after getting the Thermal Grizzly yesterday. Now I hit ~77c after 3 minutes of Aida Stability test or 60c during CB23 multicore. No errors if I stay at 3733/1867 and OC the crap out of the GPU as well. In games, CPU never goes over 60c and the GPU hotspot never over 70c. PBO 2 was fight and couldn't get to 4650 full load, forget about the former "+200" of Zen 2, voltage was hitting 1.456v and higher on 3 cores at a time with temps on CB23 at ~86c. Curve Optimizer is a joke and a bad one. Every benchmark score was lower than going with the all core OC. 4700/4800 are possible but it won't pass an all core stability test due to hitting ~86c and a BSOD. It would do everyday things like browse and game without issues though. I think the "comfortable wall" has been hit at 4675/1.2750v (1.288 under stress), max temps at ~77c and that fluctuates down or steady. I haven't tried pushing for a higher CPU clock since applying The Thermal Grizzly, I might for "science", lol. Here's a pic of the AsRock BIOS page with the specs they list for version 3.90. I'll reboot and check the main screen and AMD PBS, and take a pic with my phone.









I had this running at 4000/2000 but just got tons of WHEA 19's in a continuous stream. It passed both TM5, 6 passes and Memtest Hci to 200% no errors. Aida 64 memory tests were fast and good. Stability test would crash the PC in ~60 secs. That's when I looked in event Viewer.

Flashrom I messed with years ago and bricked a board. Then managed to get one BIOS altered only to find out I messed it up too. So I best leave that alone, lol. I have an old laptop I could load XP or Windows 7 on and have the right environment for MS-DOS or I could grab that "dll" from there. I guess I could grab it from any media I have that's XP or windows 7? However, the boards listed on that page are not this one and the closest is the Taichi with the 3.40 BIOS. I could use FlashRom to open an existing BIOS, no? But then what? I have no clue what to alter after that that would fix this issue. Back to thinking about buying a better board. The Asus TUF Gaming X570-PLUS or PRO, or the Gigabyte Aorus Elite, seem to be capable of this new AGESA and more RAM compatible in general too. Both run ~$200 USD right now.


----------



## Comalive

Veii said:


> @Comalive you might want to try RTT_PARK as /4 instead of /3
> RTT_WR /3 is easy, but /2 is already very hard to maintain and strong
> You likely want to "increase" RTT Park value , rather "make it lower, take away the strength of it" , soo a higher divider
> If it refuses to post, you'll have learned something about your dimms at least
> 
> But i think it would work
> even /3 is already too much


I set those values, what changes am I to expect now? Also using 1.1v SoC and 1.06v IOD as Manni suggested.


----------



## Br3ach

Comalive said:


> What voltage (range) would you recommend me to test?
> I am running a 5900X with 2000 fclk and while I pass all the stress tests, I also get WHEA 19 errors like there's no tomorrow.


Try bumping up Vsoc up to 1.2V and GCD up to 1.08V. But if you have lots of them though it's unlikely you will be able to stabilise. For my infinity fabric instability manifests as audio crackling, difficult to catch at low levels, I would rather have WHEA errors  not sure some people get WHEAs and some don't, but the instability is still there.

Btw very much surprised to see that you are running stable with GDM disabled.[/QUOTE]


----------



## Veii

Comalive said:


> I set those values, what changes am I to expect now? Also using 1.1v SoC and 1.06v IOD as Manni suggested.
> View attachment 2481772


Not much changes, just less harsh powering of the dimms
RTT_WR /2 is harsh ~ RTT_PARK was too much

Nono, 7/3/4 will run absolutely
72/3 was too much
soo you should try
6/2/4 or 7/2/4
just lifting RTT_PARK a bit, as /3 is a bit too much when you use RTT_WR that strong
RTT_WR , if set correctly ~ changes it to dynamic On-Die Termination, and will dynamically clean up the Data Eye
Eh, rather do clean cuts by algorithms. it's a technique Micron uses for their "easy die" Rev.E
The Secrets of PC Memory: Part 4 | bit-tech.net Thread








Getting it correctly tho, is another side of the story

Overall "what should it bring"
Stability ~ which you should test , or at least remember if you ever get hard shutdowns or PCB Crash errors
My suggestion was only that you change away RTT_PARK , nothing else ~ or stick to RTT_WR /3 instead /2 *
* unless you run >1.58v . Then feel free to use RTT_WR /2 with something weaker on RTT_PARK
Too Strong RTT_PARK causes issues. We don't want them


----------



## Comalive

Br3ach said:


> Try bumping up Vsoc up to 1.2V and GCD up to 1.08V. But if you have lots of them though it's unlikely you will be able to stabilise. For my infinity fabric instability manifests as audio crackling, difficult to catch at low levels, I would rather have WHEA errors  not sure some people get WHEAs and some don't, but the instability is still there.
> 
> Btw very much surprised to see that you are running stable with GDM disabled.


[/QUOTE]
Audio crackling means your vSoC is too low, as far as I know. I only got audio problems when I tested really low vSoCs like .9v. I tried 1.2v SoC before, I'll also try higher CCD voltages as well, currently still testing .98v.
The WHEA 19 errors (2000-4000 per hour) don't really do anything besides being "annoying", what is an issue though is when your system randomly reboots.
Why are you surprised at seeing GMD off running stable though?


----------



## mackbolan

Veii said:


> I don't think your bios is "new"
> i can read SMU 56.43 not 56.44
> ASRock has the AMD PBS menu open for everyone
> Can you check the ABL version there
> 
> You don't want to run 24-24-24-24 CAD_BUS
> This did not work well on Matisse and still doesn't work well on Vermeer
> 
> Is that 3733 1T set really stable ?
> tWR looks off , too low & at what voltage.
> 
> Anyways, CAD_BUS you want to run "at least" 24-20-20-24
> But this will cause post issues and issues with memory training on Vermeer
> Soo we run it higher 40-20-30-20, 40-20-40-40 ,60-20-30-24
> Anything with 30+ on the 3rd value, to combat broken memory training since AGESA 1.1.0.0 Patch C
> 60-20-20-20, can also run , but 2x 8gb rather likes 40-20-20-20 with CAD_BUS Setup Timings matched to the frequency
> 
> My main set used 40-20-24-24 ~ before figuring out a better method
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> If you have on your board
> I just checked, never seen the "S" Special edition of the PG4
> But bios 3.40 is SMU 56.33 (Patch B)
> While the one you use is NOT 1.2.0.0 but 1.1.9.1 or 1.1.9.0v2
> It's the alpha pre-release of 1.2.0.0 with the Cache fix
> It pretty much should have the same buggy symptoms that 1.1.9.0/1.1.8.0 users had
> 
> Problem is, you don't have any "good" bios to fall back
> They skipped the good release, and directly went to Patch-C with the 1900 FCLK lock (i mean maybe ASRock didn't know)
> Do you want to request and write the support team for a bios with
> SMU 56.44 ABL 0C074010
> or an old one before 3.40 with
> SMU 56.30 & ABL 09084010
> 
> Both have no 2000 FCLK Lock and can go up till 2167 (2100 package throttles, but that's besides the point)
> Both have no WHEA issues either (i couldn't find any, i just get hard shutdowns on little problems)
> 
> You can also try to downgrade to 3.40 and see if you can post 1967/2000 FCLK or there is a 1900FCLK lock (for science)
> But i think, you are out of luck here
> Try to write them, or downconvert with flashrom from The Stilt's instructions & post #4 for visualisation
> 
> 
> 
> 
> 
> 
> 
> 
> AGESA FW stack patched bioses for 3rd gen
> 
> 
> I decided to put these under a separate thread, since there are already quite many bioses available. File naming: Original bios build (version), M = modified, FI (4649 ASCII, i.e. SMU 46.49). Besides the actual SMU FW, these files also contain up to date PSP, PMU (IMC) FWs, bootloaders and...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> The bioses here are old, but the flashrom flash utility is usable for our AM4 boards
> (with little exceptions of boards with internal bios flash buttons)
> 
> EDIT:
> 
> Sinopower
> SM4337
> 30V, 55A, 7.1mΩ
> (high-side x1)
> &
> SM4336
> 30V, 65A, 5.3mΩ
> (low-side x1)
> 
> Are kind of Low end , overall the SM lineup
> But quite honestly ~ ASRock hides switching frequency and loadlines on many of the bioses
> I do like them because of many reasons - but there are a lot of little things , they mess up
> (I give them maybe too often a hard time ~ i guess)
> Here is an example:
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2481762
> 
> 
> 
> Meanwhile "marketing lies"
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2481763
> 
> 
> 
> Also coming back to
> 
> __ https://twitter.com/i/web/status/1348312213715562499
> I don't understand ASRock sometimes
> They update their X570 lineup first and let B550 users wait a lot
> Then they try not to care about the good boads like the X570 ITX or B550 ITX
> Or mess up the X570 Taichi on the layout and PCIe lanes spread
> Put good Renesas 90A stages only on 2 boards while the rest has to run lower end Vishay = Renesas, 50A stages
> I don't understand the designer teams priority ~ yet when they update the bios, they do more than the competitor's
> I just wish them to make less tiny errors in the future.
> Currently Biostar leads on the "open bios" side of things for their 130/140$ boards with the same powerstages the 200$ B550 ITX/AX comes with
> 
> EDIT 2:
> uPi Semi uP1961S 4 Phase drivers & doublers
> They either didn't get the EFI module for loadline support , or it simply is not possible
> I think Asus uses the same on their current boards but i am not entirely sure
> They rebrand their PWM and Mosfets
> But this is the reason you miss frequency and loadline control
> Above reasons are just ASRock intentionally being lazy


They are lazy. You're not too hard on them. I've gone round and round and round with their support that takes days to weeks to reply. They told me my RAM wouldn't work because they don't support anything over 3200, not that it wasn't on the QVL. Besides they advertise all over how the board supports this and that OC RAM. It's all B.S. They wasted so much time i got stuck with the board, when I could have swapped it for a different brand! The resizable bar is in my BIOS but you need to disable CSM and enable above 4G decoding for it to work, meaning I lose my DVD/RW for SAM support on games I don't play.... Also I play at 1080p, mostly FPS, driving sims, so SAM really doesn't come into use. I could load up Resident Evil 3 but I really suck and die a lot. Of course, I had that loaded when I was running the 3600x and an RX 5600 XT, this 5600x and RX 6800 might make the game go faster than 40 FPS. I know the boards I mentioned are still mid-range boards at best, but they both have a much better VRM and overall power delivery. And a better to use BIOS too. The Crosshair Hero VIII is out of my range or not worth my range unless I had a 5900X, 32GB or more RAM, and a 4TB Gen 4 M.2. As it is I have re-spent what it cost me to build this rig with a 3600x and a RX 5600 XT GPU last April with this CPU, GPU, and for good measure the PSU was replaced with a Corsair RM750x too. I was running an RM1000 from 2013, still looked good, powers seemed ok but dunno, age? So I'll put those CAD BUS values in and try again? Also lower the CCD and CLDO since they're on the high side.


----------



## Br3ach

Comalive said:


> Audio crackling means your vSoC is too low, as far as I know. I only got audio problems when I tested really low vSoCs like .9v. I tried 1.2v SoC before



Yeah, well for me stays the same up till VSoc 1.25V VDDG 1.1. If VSoc is really low it's of course a disaster, point is higher VSoc doesn't necessarily fix it. Silicon lottery I guess.<2000 MHz is fine. Both audio crackling and WHEAs are indicative of IF instability AFAIK. I just haven't seen a lot of folks doing 1T GDM off, but then again you are rocking 2x16. Consider yourself lucky, 4 DIMMs GDM off is hell, at least at high frequencies.


----------



## Veii

mackbolan said:


> So I'll put those CAD BUS values in and try again? Also lower the CCD and CLDO since they're on the high side.


I mean you can try to follow my advice from here








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




At least on ASUS and ASRock Boards, we had no issues
I don't know what's up with Gigabyte & MSIs bios , but they have issues with my low voltages 😐

Reconsider the Biostar Racing B550GTA,
I don't know about the WHEA part , but their current bioses have a fully open AMD CBS
Eh not that you can't do it on other brands, but it takes too much time going through all of the 30-40 CBS menus in HEX and unlocking them








B550 VRM DB sheet


시트1 Feedback : [email protected] Don't requst permission / You can leave comment :) Product,Price,Config,Phase Type,VRM Type,MOSFET (Vcore),PWM Controller,LAN,Wireless LAN,Audio ASUS ROG STRIX B550-XE Gaming WiFi,$ 330,14+2,Dual-Output,DrMOS,TI X95410RR 90A,ASP1405i (7+1),Intel I225-V (2.5...




docs.google.com




Here a little overview
I would focus on Renesas stuff, till you can afford Infineon TDAs (overkill for a 5600X with a 120A EDC fuse limit ~ ty AMD) but eh why not
The B550 Gaming Edge WiFi, looks interesting from MSI
But if this ASRock ITX board wouldn't get decent bios support ~ i probably would jump to Biostar and give them a go
I think as underdog, they'd be open to accept support 🤔
Eh i hope ASRock improves, but they lost a good bios engineer ~ or something happened. Their work feels different
ASRock JP does a good job, but it's not their main division as it seems


----------



## Comalive

Br3ach said:


> I just haven't seen a lot of folks doing 1T GDM off, but then again you are rocking 2x16. Consider yourself lucky, 4 DIMMs GDM off is hell, at least at high frequencies.


Well I am running 4x8GB, so.......

@Veii 7/2/4 boots, will test 6/2/4 later as well.


----------



## Veii

Comalive said:


> Well I am running 4x8GB, so.......
> 
> @Veii 7/2/4 boots, will test 6/2/4 later as well.


Beautiful 
I can only boot RTT_WR /2 @ RTT_PARK /5 or lower, RTT_PARK /6 like my usual 706 set ~ did not work
RTT_WR /3 works on 706 (736) same as 607 works
Investigating and fooling around








i strongly dislike benchable suicide runs or ones at 1.8+ volt
only stable ones for normal people matter
The rest is having fun, without teachable benefits 
This is at 1.66v but i work the voltage slowly down ~ at least give my best to do so

EDIT:
i'm not sure if tBURST would change with BankGroupSwap "normal" instead of "alternative"
BGSAlt would keep tBURST at 4, unsure if BGS normal, ~ wouldn't push tBURST up to 8 (4 dimms)
Need to test if tBURST 2 exploit still works someday later
Want first at least 3600C12 daily usable


----------



## mackbolan

Veii said:


> I mean you can try to follow my advice from here
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> At least on ASUS and ASRock Boards, we had no issues
> I don't know what's up with Gigabyte & MSIs bios , but they have issues with my low voltages 😐
> 
> Reconsider the Biostar Racing B550GTA,
> I don't know about the WHEA part , but their current bioses have a fully open AMD CBS
> Eh not that you can't do it on other brands, but it takes too much time going through all of the 30-40 CBS menus in HEX and unlocking them
> 
> 
> 
> 
> 
> 
> 
> 
> B550 VRM DB sheet
> 
> 
> 시트1 Feedback : [email protected] Don't requst permission / You can leave comment :) Product,Price,Config,Phase Type,VRM Type,MOSFET (Vcore),PWM Controller,LAN,Wireless LAN,Audio ASUS ROG STRIX B550-XE Gaming WiFi,$ 330,14+2,Dual-Output,DrMOS,TI X95410RR 90A,ASP1405i (7+1),Intel I225-V (2.5...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Here a little overview
> I would focus on Renesas stuff, till you can afford Infineon TDAs (overkill for a 5600X with a 120A EDC fuse limit ~ ty AMD) but eh why not
> The B550 Gaming Edge WiFi, looks interesting from MSI
> But if this ASRock ITX board wouldn't get decent bios support ~ i probably would jump to Biostar and give them a go
> I think as underdog, they'd be open to accept support 🤔
> Eh i hope ASRock improves, but they lost a good bios engineer ~ or something happened. Their work feels different
> ASRock JP does a good job, but it's not their main division as it seems


So I tried to put those CAD values in but they seem to have just defaulted to 20 across the board as you can see by this Zen Timings pic. The BIOS is indeed saying it's the 1.2.0.0 but the FW reads as it does in the other pic. So dunno what's going on there. Running at 4000/2000, 4675/1.275v and one wouldn't know there's any error unless you look in Event Viewer. If I lower certain voltages other than SOC my audio starts freaking out. The SOC is happy, I think at 1.156. i have a SS of HWinFO voltages, new Zen Timing but you'll see the CAD didn't stick to 40-20-30-20, went straight 20. I did it from top to bottom and left everything else auto. I have an Aida RAM test pic too.


----------



## Yviena

Hmm weird is it normal for Aida latency to go down after around 3-4 rounds then be stable with only 0.1ns variance, this happens even if I do completely stable settings.


----------



## Veii

@mackbolan aah so it was you ~ i always wanted to ask
Why did you change the wrong tRCD value higher
or was it intentional ?
tRCD_RD should be higher if you can not get stability elsehow
tRCD_WR usually can drop to half of tRCD_RD



Yviena said:


> Hmm weird is it normal for Aida latency to go down after around 3-4 rounds then be stable with only 0.1ns variance?


0.3ns variance = autocorrection & instability
0.1ns is common test to test , boost difference
you should not move the mouse while the test finishes and you need to run all of them together
else the boosting won't reach it's peak if you only run one specific test or category


----------



## craxton

hazium233 said:


> Does AMIBCP work for MSI B550? I haven't tried it, although I have looked in the B550 Gaming Edge bioses and CPU VDDP is in the Overclocking tab in between CLDO VDDP and CPU 1.8.
> 
> Reason I was looking though is that I can't find VTT DDR. Do the MSI B550s not have this at all, or am I blind?


from what i have searched, thru the windows inside the bios (from patch B to the latest released on MSI website, 1.2.0.1 i cant see any CPU VDDP
only VDDP voltage which was stated by Veii (i gave a screenshot of the image) that this wasnt the CPU VDDP voltage which was being spoken about.

find this info here and the screenshot here, and do respond back and show if what you see is different? perhaps your talking
about inside AMD overclocking section? all these settings were old pic was for reference
(my pic is also on this page of the B550 gaming edge wifi bios, last version tho, i do believe?)


----------



## Veii

Yep , test it 
If it changes inside ZenTimings , then it's cLDO_VDDP and not CPU VDDP


----------



## craxton

mackbolan said:


> So I tried to put those CAD values in but they seem to have just defaulted to 20 across the board as you can see by this Zen Timings pic. The BIOS is indeed saying it's the 1.2.0.0 but the FW reads as it does in the other pic. So dunno what's going on there. Running at 4000/2000, 4675/1.275v and one wouldn't know there's any error unless you look in Event Viewer. If I lower certain voltages other than SOC my audio starts freaking out. The SOC is happy, I think at 1.156. i have a SS of HWinFO voltages, new Zen Timing but you'll see the CAD didn't stick to 40-20-30-20, went straight 20. I did it from top to bottom and left everything else auto. I have an Aida RAM test pic too.
> View attachment 2481780
> View attachment 2481781
> View attachment 2481782


did you add these settings from the (MAIN) overclocking page of your board, or thru the Advanced "AMD" section?
yes it matters as from what ive found no matter what is set inside "AMD overclocking section" the main section will
take priority.


----------



## Yviena

Veii said:


> @mackbolan aah so it was you ~ i always wanted to ask
> Why did you change the wrong tRCD value higher
> or was it intentional ?
> tRCD_RD should be higher if you can not get stability elsehow
> tRCD_WR usually can drop to half of tRCD_RD
> 
> 
> 0.3ns variance = autocorrection & instability
> 0.1ns is common test to test , boost difference
> you should not move the mouse while the test finishes and you need to run all of them together
> else the boosting won't reach it's peak if you only run one specific test or category


Hmm I always only run the latency one, though no matter what I have tried I get the occasional 0.2ns higher latency sometimes but can that be because of random windows processes opening/closing?

Upping the TRDWR to 10 seems to have lowered my latency a bit to between 54.9-55.1 though still stable 20+ cycles memtest with both 9-10 TRDWR.

I wonder if TRDWR/RD at 10/5 would lower latency/variability even more


----------



## craxton

hazium233 said:


> Does AMIBCP work for MSI B550? I haven't tried it, although I have looked in the B550 Gaming Edge bioses and CPU VDDP is in the Overclocking tab in between CLDO VDDP and CPU 1.8.
> 
> Reason I was looking though is that I can't find VTT DDR. Do the MSI B550s not have this at all, or am I blind?


(EDIT) <after looking a little to figure out what AMIBCP was a few pages back, i myself am interested in trying out 
a way to unlock settings inside the bios, but with me simply put, just finding out what it is....although i do have an eprom flasher and 
use it quite alot for "fake gpus" etc, it seems like theres a pretty straight forward set of instructions on "HOW TO" use this program.

if i understood correctly, you havent tried it on this board? but claim CPU VDDP is in the bios, or are you saying you used the program, and the setting 
is inside the bios and is simply put "hidden" for whatever reason?>

after restarting my board a moment ago just to go look since i updated to the latest bios, (dont understand what your asking with AMIBCP?)

these are the only settings inside the bios, there is no CPU VDDP voltage. (forgive the fact that i had to screenshot my screenshots, the website wont allow bmp images to be uploaded,
changed to png and jpg as well but it simply states the files werent images as expected? anyhow, there is 1P8 voltage, changed from
advanced mode does nothing to unhide it, its there. (on the latest bios) it wasnt there on the last version, or at least none of the pics i have
saved shows it anywhere.


----------



## mackbolan

@Veii , @craxton I indeed inserted the 17 where 16 should be or that's how it looks, lmao. I tried booting straight 16's but it was a no-go but I did have the tRFC at 298, I was using the 3733 values. I then used a preset from last night. Those timings are from DRAM Calc for Samsung B-Die at 3800, I think, the fastest high frequency timings I could find that looked close. So you're saying 16, 8,17,16? To Craxton, these are entered off the OC Tweaker page or "main page" in AsRock, not the hidden AMD area deep inside, lmao!


----------



## craxton

Veii said:


> Yep , test it
> If it changes inside ZenTimings , then it's cLDO_VDDP and not CPU VDDP


its cLDO as you and i discussed this a little while back and i tested it.

you dont own any MSI boards? i see you mention "possible" use and unlocks of hidden settings inside MSI bios,
but havent stated a sure thing. No, im not saying to try it lol, im asking if you have? Considering all the boards ive seen you mention tho,
MSI isnt on the list for boards you use personally. mostly ASRock it would seem. and the ITX being your go-to.

at this time i kinda wished i hadnt learned there is a "maybe" chance this AMIBCP software can unlock settings inside the bios, as im now highly tempted
to test this, but considering my only "other" board to fall back on is the X570 version of the b550 i have....i suppose i could try the x570 gaming edge wifi instead
since if i brick it, i wont mind nearly at all.... but yea, the setting isnt inside the bios without being unlocked/unhidden. 

(EDIT) adding pic, for context smu is 56.46 same timings i was running on the last bios (fully stable) minus prime95. ran literally EVERYTHING else tho.


----------



## Veii

@craxton
I'm not brand loyal - just jumped to the one that does have better specs
I was strongly tempted to go with Biostar this time, but they had a very bad bios on X370 and X470.
Convert flashed the B550 and it looks . . . how it's supposed to be. A fully open AMD CBS.
A shame ASRock doesn't follow what made them great back then "an open CBS".
For them it gets less and less open every bios.
An asking to change brands from my view ~ when they do the same restrictive nonsense ASUS keeps doing for their lower end boards.

I've played with a bios modded Unify and saw it there functional
And as AGESA is AGESA, nevertheless of the board ~ it is there, hidden but it's there.

AMIBCP is a bios editing program with copyright to American Megatrends (AMI ~ APTIO)
There is a better one ,but to get this one you have sign an NDA and be a board Manufacture or somewhere near the field of PCB creation.

As comparison, the Gaming Edge Wifi is on Renesas 60A stages with the same Renesas RAA 229004 PWM on 5+2 Phase mode (doubled 10+2)
You/We should have switching frequency access of 400-900Khz (biostar)
meanwhile on ASRock we get up till 700 (i run 500-600 most of the times) and i think MSI has it near 600Khz

Overall we share the same PWM and Mosfets - just that you are on 5+2, while i am on 6+2 true phase
OK this was easy
















It can't be more obviously shown
You guys have Relaxed EDC Throttling. Turn that thing off if you see it


----------



## BloodDivine

@Veii Relaxed EDC throttling on Auto is disabled on MSI motherboards, or do you mean to Enable it?


----------



## Veii

BloodDivine said:


> @Veii Relaxed EDC throttling on Auto is disabled on MSI motherboards, or do you mean to Enable it?
> View attachment 2481797


"recommendation" and "Auto" can do many things 
it was enabled back then - failsafe is only disabled for debugging purposes
Same as Gigabyte's "auto" boost extender , is in reality a 100mhz boost override. No wonder people are thankful about hitting 5050Mhz - although maybe on 3-4 cores at best


----------



## Veii

BloodDivine said:


> View attachment 2481797


What in reality it does, is package throttle the CPU - and slow it intentionally down.
It was since 1700X an issue and staid enable.
Disabling it was "not recommended" but actually a better option ~ as the CPU will just crash/freeze and not slow itself down on issues


----------



## mackbolan

mackbolan said:


> @Veii , @craxton I indeed inserted the 17 where 16 should be or that's how it looks, lmao. I tried booting straight 16's but it was a no-go but I did have the tRFC at 298, I was using the 3733 values. I then used a preset from last night. Those timings are from DRAM Calc for Samsung B-Die at 3800, I think, the fastest high frequency timings I could find that looked close. So you're saying 16, 8,17,16? To Craxton, these are entered off the OC Tweaker page or "main page" in AsRock, not the hidden AMD area deep inside, lmao!


@Veill also I have "uncore oc" enabled, should that be disabled and me just set the SOC and let the rest "auto"?
EDIT:
Ok, so I got the CAD BUS to stick but unfortunately after multiple tries at various voltages, Googling while in BIOS via my phone, reading all @Veii 's posts as of late in regards to achieving 1900 or 2000 IF is just not gonna happen on this board. It's clearly missing the main FW update to 56.54? It's got the resize BAR added and that's it. They call it 1.2.0.0 but it's not the whole deal, lmao! As above, it shows in FlashRom it's missing a lot for a long time. Went back to reliable 3733 and set my tRFC to 300, tWR to 12, added the CAD BUS settings, reduced my all core to 4675, turned off DF-States, and that's it. Ran a quick Aida RAM Cache test and it passed without making my A/V light blink and no WHEA errors. SOC is 1.10, the rest is auto. DRAM is at 1.41v and found out via all this that it doesn't allow for more than 1.45v in the BIOS. Some "cap" on that. I can say moving the SOC over 1.18 and the IOD at least to 1.05 seemed to increase stability but there was no end in sight. When I can I'm going to grab another board, like the Asus or the Gigabyte I mentioned earlier since there's proven individuals able to easily hit the minimum 3800/1900 and many getting to the 2000 mark on the Asus board with BIOS 1.2.0.1. This is an AsRock mess for certain and they've lost me as a customer for good. I had 2 Intel 1150's blow RAM slots with normal RAM and a simple i5 in it. No OC, nothing, even a beat GPU and both died within a week of owning them. So called "mining boards" too, could run 6 GPU's or some crazy crap with riser's. I bought them because one went bad from an eBay sale and they refused to warranty it and due to price I bought another from Newegg. Now this piece of garbage I've fought with since last April. How many complaints about the boards and GPU's recently on the AMD forum and the AsRock Discord concerning mostly AMD boards but some Intel too. Their RX 6800, RX 6800 XT and RX 6900 XT are all junk too. Those I tell people flat out to RMA. Their name suits them "AsRock" much like a useless rock. 

Thanks to all who attempted the impossible and for finding out that I was duped into thinking I had a "real" BIOS update. The bright side is when I replace it, it can be put on a shelf because it does the bare minimum that a $60 board would do and that's about all it's worth used. I still have my 3600X, I can build a backup rig or what my 66 year old mom would think is a screaming PC, instead of me screaming at it. on AsRock


----------



## Veii

mackbolan said:


> . Thanks to all who attempted the impossible and for finding out that I was duped into thinking I had a "real" BIOS update. The bright side is when I replace it, it can be put on a shelf because it does the bare minimum that a $60 board would do and that's about all it's worth used. I still have my 3600X, I can build a backup rig or what my 66 year old mom would think is a screaming PC, instead of me screaming at it. on AsRock


Please write with linebreaks
This was painful to read. Books have linebreaks too

ASRock is not to blame for the FCLK issues
It's an ongoing AMD issue, and only since recently they started to focus on 2000 FCLK
Mostly thanks to our community and well me, for pushing 2133+ showing it is clearly possible
But i got lucky too
Most of the new boards don't even have SMU 56.30 at all , they start with Patch C which is 56.34 ~ which got a 1900FCLK hardcap
My old one appeared to be without limits and the current one appeared to be without limits
But on the negative side, curve optimizer is fully broken for my gimped dual CCD 5600X
i have no access to anything per core ~ well and DF sleep states are broken

That's about the tribute i pay.
Beyond 2000 is CPU bin dependent, while 2000 FCLK is bios dependent
Some people got it finally working on AGESA 1.1.8.0, others still haven't without WHEA
The only one which was fine , is a bios which doesn't really exist on most of the boards

Quite honestly , you can not do much
nevertheless what board you pick - you will have the same bios issues everywhere else
The brand doesn't matter and is only a part responsible. AGESA is equal everywhere
I know the price of the board looks expensive , but you bought one of the lowest end X570's
150$ is the cost of the bare PCB and chipset alone if you go X570
the rest is for VRMs
and what i can read, it's about average to A520 boards, while often even lower end than many

It's just a low end board, X570 over 300 is decent, at least over 280$ - soo the money can actually be spend on ethernet and decent Mosfets and a decent PWM controller
And even then, 1900FCLK is the norm on most boards you pick
As it's not the boards fault
For AMD 3800MT/s stable is already an achievement. 2133 was never ment to be

EDIT:
I think this is about equal to a B350 Tomahawk with the mosfet capabilities 🤔


----------



## mongoled

Veii said:


> @mongoled wait a bit
> "Acknowledge potentially Hardware dying" ~ on "too low" VDDG CCD ?
> I don't underatand the point
> 
> I'll check PMs, usually do but not always answer.
> If its something easy i answer the moment i read it
> If its asking for help requiring a long session, i answer when i have the time to spare
> 
> Quite honestly, i'm reading this for the first time. The part about too low voltage doing hardware damage & being responsible
> Although as you might know, i do follow all 3, gigabytes, msi unify's and asus crosshair's thread
> There is interesting information to read ~ soo i do know about the usb issues, audio crackling issues and nvme crashing issues
> 
> But the thing is,
> I can not relate 😐
> I don't know the answer on that question
> It simply doesn't apply to me, soo i have no idea where to start looking for
> Absolutely it can be an issue and that is for people to figure out what voltage they use
> As an entry point, my set didnt make issues on neither asrock nor asus boards
> ~ soo i really don't know what us wrong on gigabyte and msi setups
> Asus has own issues, but that's beside the point
> Even played cross porting bioses to learn stuff, but i dont know about the "being responsible" you want from me.
> I simply don't know about the audio issues you guys have
> 
> I'll check PMs today again, like checked yesterday too & will double check if i've missed something from you
> Today's been 12 notification & i just woke up
> Yesterday around 7
> I really don't understand the "starting to be responsible" part. Something seems missjudged 😐


Just to be clear,

I am sure that I speak for all, we are very happy to have you here in this community sharing all knowledge with users of this forum and providing countless hours of personalised "support", as I have mentioned this to you in the past, your actions here at this forum are commendable



I dont even want to imagine how many requests and PMs you get so I totally understand that you cant answer or see all these requests and yes many will fall by the wayside and I am not one to push for things, so I didnt, just from time to time and in several threads where I saw you post and a couple of PMs I asked you regards the A0/A2 "issue", this was over a period of a couple of months.

I found it a little strange that having seen you being a "strong advocate" of these PCBs version being a good match for equalising dimm signal strength and without hardly anyone forth coming with purchasing this combo that my results (the dying of two A0 sets) did not seem to cause you concern.

If I remember correctly (and all this info is available) I think I must have posted 3 to 4 times about this, directed @Veii, as well as the few PMs.

The only "being responsible" thing is not about being responsible for any things we may break, but being responsible with the information we are sharing and at least acknowledging the feedback I was giving regards the A0/A2s as this could save other users from killing hardware without knowing the reasons for it......



ManniX-ITA said:


> @mongoled
> 
> Me and Veii discussed more than once here on the forum the right VDDG CCD voltage.
> And we both stated multiple times that _*it's always dependent on the specific CPU sample*_.
> 
> Whatever "golden rule" is advised, like everything else stated here, it's *our *golden rule.
> Based on our and others experience, knowledge and opinion.
> 
> We don't do it for business, nor we are a testing center with hundreds of platforms to verify.
> We don't work for AMD or any board manufacturer.
> It's always a personal opinion and it's up to you to judge how to treat the information you get.
> 
> What @Veii suggested is proven to work most of the times for 5600/5800x CPUs.
> Your could be an exception.


Fully understand everything you have said here and almost agree with everything you have wrote except for the last statement,

"is proven to work most of the times for 5600/5800x CPUs"

I dont think anything has been "proven", the basis for this is very simple, with so many different agesa being used, different manufacturers implementing BIOS in different way, along with all the other variations in hardware sample, such as CPU, RAM and motherboard etc, there can be no "proven", at least not at this stage of the platforms development.





ManniX-ITA said:


> ...............snip
> I guess you mean about these A0 kits dying when mixed with A2?
> 
> ...............snip
> 
> Honestly I would have suggested the same.
> There's absolutely no reason why an A0 kit should die when mixed with an A2.
> Seems more likely to me these A0 kits where defective from the start.
> 
> Unless you applied insane voltages, which you would have mentioned I guess.
> Even catastrophic resistance settings for the termination are unlikely to burn a PCB so easily.
> But I've never seen anyone complaining about A0 kits dying like that just testing some settings.


I totally agree, mixing PCB/RAM should never kill anything, thats why I was concerned about what I was seeing and wanted Veii to at least acknowledge what I had experienced not once but twice!

As regards to the voltage, nothing extreme, if I remember correctly, set 1.53 in bios which gave me 1.55v ....

If you want me to find these posts let me know and I will send them in PM as I dont want to clutter this thread any longer with this and will be done with these last posts ....



ManniX-ITA said:


> It was indeed not very well expressed
> We are also all non-native English speakers so it's hard sometimes.
> 
> Acknowledge is fine but "taking responsibility" can be literally read as "it's your fault, I'm blaming you".
> As said, he's here helping and sharing info for fun. Best effort.
> Let's not stress him please, we enjoy his presence!
> 
> Thanks for sharing the info about CCD voltage, it's interesting.
> Were those all 5600x and tested on one motherboard?


As explained earlier, it was never my intention to put fault for the actions I have taken, I think we have all understood this now




Veii said:


> Now i understand what you mean
> 
> 2 things
> 
> That part of "taking responsibility" should be invalid. I've noticed the issue but at the time back and still a bit today, had no idea what the issue could be
> 
> Neither of audio issues nor crashing USB issues. It has to be an MSI and Gigabyte Bios thing ~ but i remember very well that my old post 2 months at this point before Patch-C mentioned that this "might change on newer AGESA"
> Currently i have not encountered issues on SMU 56.44/45
> But i give you a point, because maybe potentially SOC Voltage does mask it ~ >1.2.0.0 with dLDO_Injection voltage control ~ needs to be researched more
> 
> About the dying A0 dimms issue
> My current set are Viper 4000, A0's
> I've only recently nearly killed one of the dimms (temporary loss of one memory channel)
> ~ where the issue was pairing high RTT (0/0/5) with voltage @ and beyond 1.56v. 1.52 caused PCB hardcrashes already
> This was one of the reasons i researched more and spared a lot of time to figure out 7/0/6 for them with how tCKE works and overall powerdown
> Meanwhile i'm dailying 1.58-1.62v on them
> 
> I think the issue has to do with far to strong RTT values (which where usually advertised for 4 dimms) ~ RTT Park being the target
> But even looking back at it, it continues to barely make sense
> Slave sets on Daisy Chain should not get more voltage but rather less
> For a critical spike to have happen - it would need 1.6v as a baseline on your setup , then maybe paired with strong RTTs , it could be an issue
> But it yet makes no sense ~ as a crash should happen or a loss of a memory channel (temporary)
> But not a perma death.
> 
> Nevertheless from which perspective i take a look at it, it makes no sense
> A0s are sensitive, but to really kill them instantly ~ it would need a spike of >1.7v or at least continueous 1.6v
> The only thing i can relate back now ~recently~ , is my nearly death experience on them. But that was purely my fault for shoving high voltage on them and torturing them
> Yet they survived. I just don't know what to answer on your issue. It makes no sense
> It needs more information and what RTTs you used (again only knowing now it could be an issue)
> but i still don't know what to tell you.
> "Unfortunate" but it seems not to be the "pairing A0 with A2 or A1" part that was the issue.
> It's either high voltage, or high RTT combined with high voltage. Or even something completely external.
> ~I don't know~
> 
> I'm sorry & sad that you had only a negative experience & something unforeseen was the issue
> But the "pairing A0 with A2" part ~ i don't think was the issue for the failure.
> First it makes no sense whatsoever, alone by how Daisy Chain boards are designed
> And 2nd, i don't know how or where it's been messed up "twice".
> 
> This probably needs a research for which RTTs on this combination really are dangerous,
> But it sounds like a wasteful mission. Someday the research should be done ~ right now i can't afford it.
> Nevertheless, you where neither ignored nor i try to hide anything.
> I'm sorry for your loss, but i simply do not know (back then) while having only subtle an idea now, what could've gone wrong 🙇‍♂️🙇‍♂️


Again to be very clear,

I dont/didnt expect you to give me a definitive answer!! That is impossible with the knowledge we currently share and IMHO would not be a realistic request.

Just an acknowledgement that this had happened twice and that there is a "responsibility" of having a look at this and possibly giving a warning to the community about this.

That's the "taking responsibility" part I am talking about, not a responsibility for my hardware



And yes, it could just be bad luck, its just the other day I found out another user on hwbot had the same thing happen to them (this info was given to me by someone else I have not verified it) and thats why I brought it up again



Let me know if you want me to provide details of those values you requested, I will simply have to crawl through my post history and post these to you....



Dasa said:


> Had a look back through all my AIDA64 tests and they all have exactly the same L1 latency 0.8ns and it is currently undervolted to 900mv.
> Good to know it can happen though thanks.


At what mclk/fclk combination did you try ?

At 3800/1900 its not so evident, but once I moved to 4066/2033 & 4133/2067 you can see it like clockwork!

Now regards CPU VDDP, those of you who can run low CCDs voltage, do you also have access to CPU VDDP ???

As on this x570 Unify that voltage option is not available, I tried to unhide it yesterday using AMIBCP v5.02.0031, change the selection to "USER" save the BIOS, flashed it with M-Flash, cleared BIOS, but nothing appeared in the BIOS ....

Anyone can provide link how to get the settings to stick ???


----------



## ManniX-ITA

mongoled said:


> The only "being responsible" thing is not about being responsible for any things we may break, but being responsible with the information we are sharing and at least acknowledging the feedback I was giving regards the A0/A2s as this could save other users from killing hardware without knowing the reasons for it......


You probably just had to shout louder 
It's very easy to come back after a one day and miss a big bunch of posts.
I don't get many PM but I'm pretty sure Veii does and a lot.



mongoled said:


> Fully understand everything you have said here and almost agree with everything you have wrote except for the last statement,
> 
> "is proven to work most of the times for 5600/5800x CPUs"
> 
> I dont think anything has been "proven", the basis for this is very simple, with so many different agesa being used, different manufacturers implementing BIOS in different way, along with all the other variations in hardware sample, such as CPU, RAM and motherboard etc, there can be no "proven", at least not at this stage of the platforms development.


Yes, nothing can be sure 100%. For "proven" I mean how many users reported success with it.
Not that I keep and document precise statistics but I keep a mental record of the most interesting stuff.

I know that most users that posted feedback about CCD voltages on 1 CCD CPUs had more luck with low voltages and with 2 CCDs had more luck with higher voltages.
Unless I did a mistake in my counting which is possible as well 
But in both cases is really CPU dependent; there are a lot of exceptions and the AGESA, which version and how has been integrated and on which board, matters.
It's not like 99% a golden rule, I'd say more 80/20 or 70/30.



mongoled said:


> At 3800/1900 its not so evident, but once I moved to 4066/2033 & 4133/2067 you can see it like clockwork!


I wouldn't mix FLCK > 1900 with < 1900.
Doesn't work yet properly; whatever voodoo magic is needed to make things works > 1900, I wouldn't consider it relevant.
It's an issue mitigation which is very likely going to change if and when AMD fixes it.
I had to do funny stuff for FCLK 2067 but it's that, funny stuff.

BTW as well as others, never had a sizeable change in L1 cache benchmark due to CCD voltage.
Nothing I noticed at least.
But I can clearly see the correct voltage with GeekBench 5 AES-XTS Single Core test score.


----------



## GribblyStick

Veii said:


> Soo 60 was too strong for your dimms for some reason. /3 Park shouldn't be that strong, but you can give these CAD_BUS values another try at 634
> If you still BSOD or it fully refuse to post , then it's just too strong ~ but i doubt, since 4 dimm users can go up till 120ohm ClkDrvStr (reasonability aside, but they can)
> 
> I wonder why you have issues with CsOdtDrvStr at 40 🤔
> 
> Soo you've eliminated the probability of powerplan issues ?
> Can you try to increase the EDC limit a bit, or put it under AMD Overclocking - PBO - Advanced - Motherboard limits
> Just to doublecheck if it's a run to run power reserve variance ?
> The last thing that remains is your windows potentially being bloaty ~ to have such a big variance when y-cruncher passes and TM5 too ?


First of all, current settings, I think you might be mixing some things, which is not surprising given you are juggling help for like 10 people .
(VDIMM 1,5)


Spoiler: current settings















You didn't answer regarding the lowering of other voltages, so I just tried myself.
I couldn't really tell much of a difference though. Tried setting VLDO_VDDP to 0,880 and CCG to 0,900 and 1,05 while also lowering procODT to 32.
Haven't tried lowering either further than that. Those seemed to me to be at their most sensibly low value. 
Overall I got pretty much the same numbers I've been getting since your default "easy" 3800 setting.

However I got a little bit more consistent results with 0,920 CCG, 56,9-57,6. (no difference between 0900 and1050 compared to 0940) That also got me the most consistently high write speeds so far. (on the settings I just posted)
I don't think 60 is too strong for CADBUS, I've been running that for most of my tests with the 3800 easy set.
I'll try going back to 6/3/3 tonight or 6/3/4, see what happens.

As for the power plan I am using the ultimate performance plan now as you suggested, didn't really notice a difference though.
My windows is a fairly new install, with only really some games installed and then a bunch of benchmarking stuff. I had to do a clean of asus software but I didn't go as far as manually cleaning registry records.

I'll check this edc setting after the 633 tests, but maybe going 920 with slighter tighter variance gives you an idea?
It seems to me so far, I can try a bunch of settings for voltage/cadbus/rtt but so far I've seen very little actual change except maybe going down a little bit in latency. Initially it was more around 60.
But everything so far has been stable in terms of no visible errors, except for those cadbus 40 settings on ODTDrvStr.


----------



## Veii

@GribblyStick "too strong ClkDrvStr" in the sense of "probably too strong for 8gb dimms on average"
And probably "too strong" given that you run RTT_PARK near /3

/3 is kind of expected on many dimm setups, even more on daisy chain - but i where here just asking.
Lowering voltages, i can not answer
I mean i did - the voltages figured work up till 2133+
I think they are fine how they are and go well together with the "high" SOC voltage ~ which still remains fine. The limit i set as 1.3v, as 1.25v is pushed by the bioses on their own. Sillicon substrate "litography colour" changed, and so did voltage scaling , compared to powersaving Matisse

But i can not predict how it will go, just forward you to the tools which we could use.
Pretty much no different than all the work 1usmus did with his DRAM Calculator
Suggesting up to date settings which work & also giving an undervolting example for 3800MT/s on the same thread








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




"Hard set rule ~ or not rule"
That's been my early point of look and testing since November/December on the unit.
It's up to you to try and follow and shape it * ~ only 2167 i can't yet get figured out 
* but i ask myself, why the out of nowhere disproval ~ i didn't see such event when 1usmus shared his long tested values.

I mean people still often complained that the early versions of timings and voltages did sometimes not work ~ and this shaped it well through months of updates
But what's all this judgement all of a sudden. Bored ? (generally/globaly asking)
I do also wish some better low voltage settings ~ as this SOC is still eating 18W of the power-reserves for itself
But hey, this is what worked out so far ~ maaybe we'll magically all be able to run 2133 FCLK when AMD decides to stop the Package Throttle autocorrection train.
But until them, it's a fight against it ~ where there is no real answer when it maybe might supposedly be stable, away from it's always autocorrecting state 
(it's always stable, 213ns memory latency & 30ns L3 ~ buuut doesn't fail any tests. ECC 🔥)


mongoled said:


> Let me know if you want me to provide details of those values you requested, I will simply have to crawl through my post history and post these to you....


If this is an ongoing issue like you mentioned - then it surely needs research. To prevent future damage
I don't understand it still.
PCBs should not be able to communicate with each other ~ to even care what you mix with what
They should not be able to enforce own internal termination values to request->override what the board sets

I can't understand why there is even a consideration of critical failure when mixing anything random that has no crosstalk to it ~ by utilizing it's strengths
These RTT values you use from DRAM calculator, i mean also come from somewhere
I can see that sometimes they are suboptiomal
(considering a lot of changes happened on 1.0.8.1 AGESA @ Vermeer release)
But to actually find "dangerous" ones ~ would be useful i think.
Sadly there is not much to contribute with my ITX board on this research of failure 
(except for "Don't Pair 0/0/5 RTTs with >1.53v on A0 dimms"
~ this might kill it on a too big voltage spark
"stay at 1.48v max or change RTTs to something more filtering")


----------



## yrelbirb

Hmm some observations

After changing mobo (from gigabyte b450 to msi b450 a pro), I've seen some differences in behavior

In Gigabyte b450, the ballistix kits never were able to boot with geardown mode off + 1t
In Msi b450, they perfectly do, and stable

GDM Off + 1T + 4-6-TFAW 16 = largefft error in prime95 (in mere minutes)
Gdm on + 1t + 4-6-tfaw 16 = no error in prime95 for 1 hour

other subtimings are mostly unaffected (most of them being tight)

so my question is,

should i go for "tfaw 16+ gdm on" or "tfaw 35 + gdm off"?

i tried a middle ground at tfaw 24, but no avail. quickly errors in prime95 largefft

why was the other board could not post with gdm off+1t but this one can? can motherboard really affect this=? i thought it was the kits that were unable to boot with gdm off+1t 

i actually wasn't aware it was booting with gdm off. for some reason, in auto mode, bios decided to give me geardown mode off. so i got errors in prime95. i didnt even think it would be the case, but then i tried adjusting timings and found out tfaw was the culprit. at first, i thought mobo was acting up. but then i realized it was gdm off. i turned on geardown mode, and tfaw 16 became stable in prime95 again.

so now i've tradeoff options

current settings

cpu 2700x

dram 1.39v
soc 1.062v
vddp 0.95v (auto)


----------



## kompira

yrelbirb said:


> After changing mobo (from gigabyte b450 to msi b450 a pro), I've seen some differences in behavior
> 
> In Gigabyte b450, the ballistix kits never were able to boot with geardown mode off + 1t
> In Msi b450, they perfectly do, and stable


The reason is that Gigabyte motherboards set AddrCmdSetup to 11 when we are with Zen or Zen+ and with this value it cannot work with GDM OFF 1T. By comparison, Asus puts 61 and it works with true 1T at high frequencies.
Same here, but there is a solution - manual settings of the Setup times, for example:


kompira said:


> first gen Zen
> 2x8GB B-die A2 single rank
> AGESA 1.2.0.0 SMU 25.86.0
> flat14 GDM OFF CR 1T
> 3600MT/s tCKE 7 CAD BUS Setup 1-1-12 CAD BUS 40-20-20-20 RTT 7-0-6
> View attachment 2479100
> 
> View attachment 2479101


----------



## Karagra

So after a few nights of testing lower voltages of VDDP, VDDG, SoC, and VRAM my 5800x is running at whats shown below. 1.0 VDDG, .900 VDDP, VSoc 1.06, and VRAM 1.44v at 1900fclk. 400% DRAM Calculator tested overnight. (I could probably tweak a bit more but I am happy with those results over the higher voltages my 3900x took for the same settings). What should I do to test out 2100- FCLK.. would like to run 2000 or 2033 if possible.. I can boot all the way up to 2100 but the entire computer feels like its running off a 3200rpm HDD and AIDA64 ns comes out at 125+. This is every interval above 1900. Does anyone have any recommendations?


----------



## yrelbirb

kompira said:


> The reason is that Gigabyte motherboards set AddrCmdSetup to 11 when we are with Zen or Zen+ and with this value it cannot work with GDM OFF 1T. By comparison, Asus puts 61 and it works with true 1T at high frequencies.
> Same here, but there is a solution - manual settings of the Setup times, for example:


i see, so can i make an assumption?

actually, tfaw 16 or 24 was never stable and gdm on was covering for the errors it was producing (so that it seemed stable from outside), right?

so when gdm is out of the picture, it started to produce visible errors in stress testing, is it right to make such an assumption?

i actually remembering setting those three Addr parameters to 0-0-0, but also remember i tried settimg them 57-57-57 and then I managed to boot with gdm off 1t, but Veii said it caused latency loss and performance would be similar to GDM On, so i didnt bothered with that at that time and used 0-0-0 instead (since i dont even know what are these three parameters do at all and no info about their safety/long term for ram and cpu)

but msi board seems to be succesfull setting them at 0 0 0 and still boot with gdm off so dunno


----------



## Yviena

ManniX-ITA said:


> For what I've read it doesn't work anymore.
> You can use it to check the Form ID for the option you need.
> The only way to change it is to extract the Setup package with IFR and change the visibility with an Hex editor.
> MSI BIOS is even more nasty than the usual due to some peculiarities in the packaging.
> 
> The Unify-X does have VTT voltage:
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2481730


Can't hex edut be automated though.


----------



## ManniX-ITA

Yviena said:


> Can't hex edut be automated though.


Unfortunately not; you need to find the ID and change the value to unhide the option manually.
Then on MSI BIOS seems there are multiple sections for different CPU types.
Then you need to repackage the BIOS replacing the Setup portion.


----------



## hazium233

craxton said:


> (EDIT) <after looking a little to figure out what AMIBCP was a few pages back, i myself am interested in trying out
> a way to unlock settings inside the bios, but with me simply put, just finding out what it is....although i do have an eprom flasher and
> use it quite alot for "fake gpus" etc, it seems like theres a pretty straight forward set of instructions on "HOW TO" use this program.
> 
> if i understood correctly, you havent tried it on this board? but claim CPU VDDP is in the bios, or are you saying you used the program, and the setting
> is inside the bios and is simply put "hidden" for whatever reason?>
> 
> after restarting my board a moment ago just to go look since i updated to the latest bios, (dont understand what your asking with AMIBCP?)
> 
> these are the only settings inside the bios, there is no CPU VDDP voltage. (forgive the fact that i had to screenshot my screenshots, the website wont allow bmp images to be uploaded,
> changed to png and jpg as well but it simply states the files werent images as expected? anyhow, there is 1P8 voltage, changed from
> advanced mode does nothing to unhide it, its there. (on the latest bios) it wasnt there on the last version, or at least none of the pics i have
> saved shows it anywhere.
> 
> View attachment 2481786
> View attachment 2481787
> View attachment 2481788


Looks like veii beat me to it. No I don't see it when I go into bios at boot, but it is visible in AMIBCP. Pic of 150 bios opened in AMIBCP, but it also is in the same place in 120, 130, 140 and 161... probably all of the various betas.

I asked about the program because I had no experience using it on anything other than Asus 300 series.


----------



## Yviena

Hmmm does TWR affect bandwidth, or latency, unsure if i want to try to tighten it from 16 to 12, as i finally managed to get my 4x8 sticks stable at 3800CL16.


----------



## The Pook

first Ryzen build, first time OCing dual rank, and first time OCing SODIMM 

can't raise vDIMM above 1.35v, but got this kit (DDR4-3200 16-18-18-36) @ DDR4-3533 16-17-18-36










trying a bit tighter secondaries/tertiaries now, but the ^same^ timings at 3600 boots but it has wonky graphics issues


----------



## craxton

Veii said:


> @craxton
> 
> You guys have Relaxed EDC Throttling. Turn that thing off if you see it


by turning this off, does one need to use the bios mod/editing program you mentioned? 
or are you saying if one sees the option inside the bios to turn it off? as ive searched every setting inside the bios theres 
nothing to turn off on EDC throttling.


----------



## Veii

craxton said:


> by turning this off, does one need to use the bios mod/editing program you mentioned?
> or are you saying if one sees the option inside the bios to turn it off? as ive searched every setting inside the bios theres
> nothing to turn off on EDC throttling.


Quite honestly I would use the tool and permanently change it, if there is no way to make "the category" and "the field" visible, after setting it to USER

Haven't seen any CPU which does behave negatively with 880mV CPU VDDP
While 900 works and is questionable what is better beyond 2133
880mV was certainly needed for 2100 to pass all the y-cruncher torture. Well and tCKE , but that's been my dimms exclusive under 4200C16-16

Testflash this, and see if you can see all the changes
E7C91AMS.16(3)








MyAirBridge.com | Send or share big files up to 20 GiB for free


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mab.to




1.2.0.1 has interesting Vermeer and Cezanne specific override features
And seems to feature STAMP mode too + telemetry offset override ~ for tricking the boost system in thinking you have more power reserves
Usually asus does use this

You can open and take a look , but not only do you change the window flag inside one category, but also go outside and change the corresponding category to "user"
A pyramid system of permissions. Even if the little field has user permission, it won't make a change if the higher hierarchy denies it


----------



## Flash1228

Been following this thread for the past few weeks trying to learn what I can to get my RAM tuned as best as I can. I can boot 4000 w/ 2000 fclk but with consistent WHEAs. From the way it sounds GDM off w/ 2T would be better, so I tried that and I can boot into Windows fine, but I get errors in testmem5 pretty much immediately and I'm not sure what to do to try and stabilize it. Any suggestions?


















Also, @Veii the Aida beta shows 19.2 for me as well if you're still looking for others to try and compare


----------



## Veii

Flash1228 said:


> Also, @Veii the Aida beta shows 19.2 for me as well if you're still looking for others to try and compare


I still do. As long as there is not even one unit that is on K17.7 
Then it's either a readout bug, or it was 7nm altogether at the beginning


----------



## KedarWolf

Veii said:


> Haven't seen any CPU which does behave negatively with 880mV CPU VDDP
> While 900 works and is questionable what is better beyond 2133
> 880mV was certainly needed for 2100 to pass all the y-cruncher torture. Well and tCKE , but that's been my dimms exclusive under 4200C16-16


At .880v I get reboots running Cinebench R20, even random reboots on idle that I don't get at .900v, but my RAM settings are at the cutting edge of what is stable, which might be why.


----------



## Veii

KedarWolf said:


> At .880v I get reboots running Cinebench R20, even random reboots on idle that I don't get at .900v, but my RAM settings are at the cutting edge of what is stable, which might be why.


i see
I'll retest 900mV a bit more then 
930mV on stock certainly is too much


----------



## Dasa

mongoled said:


> At what mclk/fclk combination did you try ?
> 
> At 3800/1900 its not so evident, but once I moved to 4066/2033 & 4133/2067 you can see it like clockwork!


Since I start getting WHEA at 1900IF 2045IF 104BCLK is as far as I have pushed at which it was running 950mV VDDG CCD and at 2006IF 102BCLK it was using 900mV.
Cant remember if 950mV was needed for 2045IF or if I had just nudged everything up pushing for the limits.
Reason for the BCLK is that was with the first BIOS that allowed the MB to post over 1900IF but it had a latency hole when setting the IF to 2000+

Not sure how far past 2000IF I can get with this latest BIOS but I will see if I can give it a run with GeekBench 5 .


----------



## Veii

I've taken a recent inspiration on @mongoled & @ManniX-ITA voltages


Veii said:


> But i give you a point, because maybe potentially SOC Voltage does mask it ~ >1.2.0.0 with dLDO_Injection voltage control ~ needs to be researched more


And there is surely a stability reason to it.
My "old" known presets are under at least 1.25vSOC while still working under lower settings

These ones - 80mV lower, seems to be worthy for consideration
But i am not sure, if higher CCD and IOD voltage is worth the 80mV cut of SOC
Currently it still takes 23W and cuts into the boosting budget ~ buut it certainly is an alternative also working resolve 

It has to be seen how scaling behaves beyond 2100 FCLK & if stability can be kept up
But i certainly give you the point that SOC could potentially mask up lack of voltage issues. *

Profile was @ 1.62vDIMM, 880-900-1050-1100-1187,5
CPU VDDP, cLDO_VDDP, VDDG CCD, VDDG IOD, SOC

It's been a continuous fight on two fronts
EDC budget of 120A (fuse), and memory stability on these poor A0 kits
At least the timing effectiveness is a bit better, but i'm still not happy
4000C14 flat 1.66v *vs* 4067 C15 flat 1.62v *vs *4134C16 1.58v ~~ 50.3ns - 50.1ns (up to boost)
i think i improve , but at the cost of higher voltage
Need to continue the work and lower it somehow 








Proof-of-work for alternative voltage stability
IOD still feels a bit too high for me
* on both methods, there is no audio crackling for me ~ soo i'm undecided what path really is "the better" method.
Fabric color change certainly doesn't mind till 1.3vSOC. It might show a difference on manual OC. We'll see~

PS:
I need to fix my allcore CO slightly
But i guess it's fine for now
CO and per core OC got broken on this SMU. Can't do any per core values. Guess it's fine for now...
-12 allcore (-13 is better) , +35mV offset, +200 boost override, 2X scalar, Motherboard limits.
EDC is hardcaped at 120A Fuse. Nothing i can do to bypass that as for PBO ~ no telemetry voltage faking possible yet


----------



## VPII

The Pook said:


> first Ryzen build, first time OCing dual rank, and first time OCing SODIMM
> 
> can't raise vDIMM above 1.35v, but got this kit (DDR4-3200 16-18-18-36) @ DDR4-3533 16-17-18-36
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> trying a bit tighter secondaries/tertiaries now, but the ^same^ timings at 3600 boots but it has wonky graphics issues


Great stuff, well done being stuck at 1.35vdimm. I am impressed. If I may ask, why stuck at 1.35vdimm, or can't raise it above 1.35v.


----------



## Yviena

Gonna flash my Tomahawk with modded AMIBCP bios hopefuly i did it correct setting CPU VDDP and related folder to USER.


----------



## The Pook

VPII said:


> Great stuff, well done being stuck at 1.35vdimm. I am impressed. If I may ask, why stuck at 1.35vdimm, or can't raise it above 1.35v.


BIOS limitation, it's just the "X300" board in the AsRock DeskMini.


----------



## Veii

Spoiler: Hmmm 🎁


----------



## KedarWolf

Veii said:


> Spoiler: Hmmm 🎁
> 
> 
> 
> 
> View attachment 2481925


If you can pass OCCT Large Data Set, Extreme preset, you're good.


----------



## Veii

KedarWolf said:


> If you can pass OCCT Large Data Set, Extreme preset, you're good.


it's the same set as above , but had an error 3 on mirror move timeouts @ higher freq
fixed it with different tWTR ~ and confirmed stability on the timing change

i want to play a bit more with it, before doing again a 2-3 hour bench break
Anything special that should be noted for OCCT extreme ? ~ benchmark-time amount ?
Don't think it would be worse than y-cruncher under AVX2

EDIT:
I'm still not happy with the powering (RTT, tCKE, CAD_BUS), and high voltage
i mean it's fine and all ~ but naah, this can be better

EDIT2:
Score needs to be at least 48ns, if i want to update the docs result


----------



## KedarWolf

Veii said:


> it's the same set as above , but had an error 3 on mirror move timeouts @ higher freq
> fixed it with different tWTR ~ and confirmed stability on the timing change
> 
> 
> i want to play a bit more with it, before doing again a 2-3 hour bench break
> Anything special that should be noted for OCCT extreme ? ~ benchmark amount ?
> Don't think it would be worse than y-cruncher under AVX2
> 
> EDIT:
> I'm still not happy with the powering, and high voltage
> i mean it's fine and all ~ but naah, this can be better


OCCT is really great for finding WHEA errors.


----------



## VPII

The Pook said:


> BIOS limitation, it's just the "X300" board in the AsRock DeskMini.


Okay thanks for explaining but still then great stuff and well done.


----------



## Veii

KedarWolf said:


> OCCT is really great for finding WHEA errors.


Yea, i don't get them anyways 
I'll check it, if it by any chance crashes
WHEA are for me hard crashes on any little error 
If the tests pass , i can sleep in peace 

But i never had any WHEA , except for testing with CTR ~ on a too strong UV it found some
OCCT always had a testing delay amount ~ what's your current "stability standard" ?


----------



## KedarWolf

Veii said:


> Yea, i don't get them anyways
> I'll check it, if it by any chance crashes
> WHEA are for me hard crashes on any little error
> If the tests pass , i can sleep in peace
> 
> But I never had any WHEA, except for testing with CTR ~ on a too strong UV it found some
> OCCT always had a testing delay amount ~ what's your current "stability standard"?


TM5, OCCT and this.









GitHub - jasonpoly/per-core-stability-test-script: Test script developed for for easier testing of Zen 3 curve offsets


Test script developed for for easier testing of Zen 3 curve offsets - GitHub - jasonpoly/per-core-stability-test-script: Test script developed for for easier testing of Zen 3 curve offsets




github.com





Edit: I change the code in the .ps1 file to the below and let it run overnight. And to use the latest P95.

Note: you need to use the 'Code' download from the GitHub and put the P95 .zip in the same extracted folder.



Code:


$p95path="p95v304b9.win64.zip"; # path to p95 .zip you want to extract and use

# adjust the following to customize length of time to run
$core_loop_test=$true;    # Default=$true.  Basic test to loop around all cores.  Set to $falue to disable.
$loops=1;                 # Default=1. Number of times to loop around all cores.
$cycle_time=2400;          # Default=60.  Approx time in s to run on each core. 
$cooldown=1;             # Default=1.  Time in s to cool down between testing each core.


----------



## Veii

KedarWolf said:


> TM5, OCCT and this.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - jasonpoly/per-core-stability-test-script: Test script developed for for easier testing of Zen 3 curve offsets
> 
> 
> Test script developed for for easier testing of Zen 3 curve offsets - GitHub - jasonpoly/per-core-stability-test-script: Test script developed for for easier testing of Zen 3 curve offsets
> 
> 
> 
> 
> github.com


👍
Yet again, "how long should OCCT run" ?
if CO is unstable, i can't fix it ~ it's broken on this bios ~ but i'll check someday later
i read that a 6 core would need 72h of continuous testing to figure per core values out.
I kind of did it but do not apply them ~ as i can't on this bios (blame the 2nd ccd and ASRrock breaking code)

Fixing boost is at the barrel of the priority now, as long as they hit 4.85 consistently 
Wish i'd had higher fMax limit, telemetry override, or even beyond 200 boost override
No luxury for me yet ~ seems like AMD CBS needs to be unlocked fully, yet questioning if i should stay on this bios when the cache boost is just a performance enhancer thing, as it seems

Also speaking of
Lower procODT does increase the consistency of the cache boost
it still is variable like always, but the peaks are a bit higher


----------



## KedarWolf

Veii said:


> 👍
> Yet again, "how long should OCCT run" ?
> if CO is unstable, i can't fix it ~ it's broken on this bios ~ but i'll check someday later
> i read that a 6 core would need 72h of continuous testing to figure per core values out.
> I kind of did it but do not apply them ~ as i can't on this bios (blame the 2nd ccd and ASRrock breaking code)
> 
> Fixing boost is at the barrel of the priority now, as long as they hit 4.85 consistently
> Wish i'd had higher fMax limit, telemetry override, or even beyond 200 boost override
> No luxury for me yet ~ seems like AMD CBS needs to be unlocked fully, yet questioning if i should stay on this bios when the cache boost is just a performance enhancer thing, as it seems
> 
> Also speaking of
> Lower procODT does increase the consistency of the cache boost
> it still is variable like always, but the peaks are a bit higher


I can only run OCCT for an hour on the free version but that's usually fine. You'll get WHEA errors if you're going to get them before it's done.


----------



## Veii

KedarWolf said:


> I can only run OCCT for an hour on the free version but that's usually fine. You'll get WHEA errors if you're going to get them before it's done.


mmm, ii'll test overnight stuff when i'm happy with the memory timings
This board never had them , and the X570 ITX series doesn't get them
We only have hard shutdowns, and subtle autocorrection that is trackable via latency tests and SiSandra MCE
also LatencyMon 

Still unhappy with the high IOD voltage ~ and torturing it 12+ hours on it, i don't know ~ i like this unit, want them lower first. 1100mV IOD hurts a bit 
2100 seems also to work @ 49.1ns ~ should be near 48ish. No added 3ns penalty yet
Eh too early do finalize stability tests. I need a lot more voltage , RTT, timings tests before wasting time on the thaat part


----------



## craxton

Veii said:


> Quite honestly I would use the tool and permanently change it, if there is no way to make "the category" and "the field" visible, after setting it to USER
> 
> Haven't seen any CPU which does behave negatively with 880mV CPU VDDP
> While 900 works and is questionable what is better beyond 2133
> 880mV was certainly needed for 2100 to pass all the y-cruncher torture. Well and tCKE , but that's been my dimms exclusive under 4200C16-16
> 
> Testflash this, and see if you can see all the changes
> E7C91AMS.16(3)
> 
> 
> 
> 
> 
> 
> 
> 
> MyAirBridge.com | Send or share big files up to 20 GiB for free
> 
> 
> We will transfer your files easily, safely and rapidly from one place to another. You can send them directly to an email address or share files using a unique link.
> 
> 
> 
> 
> mab.to
> 
> 
> 
> 
> 1.2.0.1 has interesting Vermeer and Cezanne specific override features
> And seems to feature STAMP mode too + telemetry offset override ~ for tricking the boost system in thinking you have more power reserves
> Usually asus does use this
> 
> You can open and take a look , but not only do you change the window flag inside one category, but also go outside and change the corresponding category to "user"
> A pyramid system of permissions. Even if the little field has user permission, it won't make a change if the higher hierarchy denies it


As ive not used, opened, or downloaded the bios editing program as of yet, before flashing, i may use the program 
to check and poke around, although i haven't reset my bios, which was the first step in the directions i was reading about 
to use the program and what one should do first. 

by test flashing, this would be like flashing a normal bios update ill assume? and yes before i continue asking how/what to do,
i will go do research on the program. and thank you for sending this.

can one simply download the bios update off MSI website, then use the program and load the bios file (without extracting the files from the boards chip) 
and use this tool that way?

(OFF TOPIC)
never heard of the site you used to host the download tho, IDM doesnt see a download there, it does ask to allow permission
which i never give chrome permissions to do anything (webpages) but i still was able to download normally....
this website you use, reminds me ALOT of weboas.is which some may find useful even tho most of this comment is irrelevant


----------



## paih85

Hi @Veii ,

need ur help. Is this timing ok? this dual rank kit 2x16gb seems don't really like GDM disable and will get many errors when running TM5. my old kit single rank 2x8gb easy to tune GDM disable @1T. any chance i get better performance with this max limit vdimm 1.45v?


----------



## Veii

paih85 said:


> Hi @Veii ,
> 
> need ur help. Is this timing ok? this dual rank kit 2x16gb seems don't really like GDM disable and will get many errors when running TM5. my old kit single rank 2x8gb easy to tune GDM disable @1T. any chance i get better performance with this max limit vdimm 1.45v?
> 
> 
> View attachment 2481929


Where did you copy CAD_BUS 40-20-20-20 from ?
And why do you start with 1T GDM off, instead 2T ?
You would have 4-5 different problems needing to take care at the same time

timings
RTT powering
cad_bus
voltages
WHEA errors or autocorrection

too many things , don't just go in without a plan
step by step - achieving what other users run here








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com




can take weeks of testing , or spread trough several weeks as short sessions

40-20-20-20 alone on it's own, is not correct
RTT are too strong on their own too
use 6/3/3 for 2x 16gb


----------



## ManniX-ITA

@Veii 
Just curious if it works for others, did you check with Geekbench 5 at which CCD voltage the AES-XTS score drops?


----------



## Veii

craxton said:


> As ive not used, opened, or downloaded the bios editing program as of yet, before flashing, i may use the program
> to check and poke around, although i haven't reset my bios, which was the first step in the directions i was reading about
> to use the program and what one should do first.
> 
> by test flashing, this would be like flashing a normal bios update ill assume? and yes before i continue asking how/what to do,
> i will go do research on the program. and thank you for sending this.
> 
> can one simply download the bios update off MSI website, then use the program and load the bios file (without extracting the files from the boards chip)
> and use this tool that way?
> 
> (OFF TOPIC)
> never heard of the site you used to host the download tho, IDM doesnt see a download there, it does ask to allow permission
> which i never give chrome permissions to do anything (webpages) but i still was able to download normally....
> this website you use, reminds me ALOT of weboas.is which some may find useful even tho most of this comment is irrelevant


Here it is reuploaded somewhere else


Free File Hosting - Online Storage; Upload Mp3, Videos, Music. Backup Files


Just picked a random site that was used on me
Check








AGESA FW stack patched bioses for 3rd gen


I decided to put these under a separate thread, since there are already quite many bioses available. File naming: Original bios build (version), M = modified, FI (4649 ASCII, i.e. SMU 46.49). Besides the actual SMU FW, these files also contain up to date PSP, PMU (IMC) FWs, bootloaders and...




www.overclock.net




and post #4 , how to use flashrom
make a backup of your current rom - soo you have all the profiles and the warranty saved
then use flashrom to clean flash the shared bios
It's modified, soo it won't pass in-bios signing key check
but it's not broken modified, soo it will 100% pass the flash

If flashrom finds nothing "no flash-chip"
then your board has an external flash chip & you should follow the manufactures procedures in using that one (away from the bios)

You can also google the tool with the exact same model number in order to find it
I did quite a few modifications, soo i wonder if you can see any changes after you flash it ~ without much more work involved in unhiding stuff via hex
I can't share AMI copyright software ~ but you can easily get your hands on it if you search


ManniX-ITA said:


> @Veii
> Just curious if it works for others, did you check with Geekbench 5 at which CCD voltage the AES-XTS score drops?


I didn't try to destroy it yet, as my take on it "just worked" ~ the first time i tried
SOC could maybe go down 20mV but i didn't bother to touch something that runs well
Geekbench i still need to run, but it passed my usual abusive test of y-cruncher 4 loops ~ soo at least it's not broken
About autocorrection, we have to see later how much better the results can get
Currently the end result is better and consistent.
Later when i am stuck again with my memory (am already at 4200 lol) & RTTs + powerdown topic is cleared
then i'll try to compare which voltage works even better
so far it's an improvement in latency, but i still feel that it's a bit too much for my taste (IOD)
Unsure yet if the tradeoff is worth it , pushing that high VDDG CCD on it (1050 peaking)

If i get 2100 stable (i think the FCLK side is fine on this set of voltages)
then it should move in the 48ns range
currently it rarely drops bellow 49 ~ slightly peaks bellow but it's too unstable yet
The bad PCB shines through & i really don't want to increase voltage beyond 1.62v 

EDIT:
Give me couple of "weeks" haha, to stabilize 4200 C15 which doesn't need these 1.66v the 4000 C14 requires
(please don't take that long)
Then i'll see what i can do with the CPU section of it & min-max the voltages


----------



## GribblyStick

@Veii 


Spoiler: current state...1,5 VDIMM, 0,840 CPU VDDP














Regarding the disapproval, I can't say that was my impression from this thread. Certainly not a sentiment from me. I only understand half of what you say but it's still been helpful lol.

I tried a few things and now I'm looking at 56,3 -58,3 at the current settings, though the majority are in the 56ish ns range, so I feel like we're getting closer. And if nothing else latency is improving.
Since lowering seems to be working better, I lowered SOC again, and that seemed to help a bit, but the settings are getting more sensitive now. I am no longer able to run 6/3/3 or 6/3/4, That said, the last run on 6/3/3 had the least variance, but higher latency than the current settings. I tried at CLDO VDDP 0,840 but that was worse (from 0,850), then 0,860 and 0,855 wouldn't boot.
Setting PBO limits to motherboard was worse, I went from 56ish to 59ish in latency and it was still swinging.

I tried with tcke 1 just to see what that would do, but I didn't notice any difference. Had to lower ClkDrvStr to 40, but I don't remember the exact settings I had for that test.
Not sure what to try next? I 've seen some people run with RttNOM disabled, I haven't tried that yet.


----------



## Veii

GribblyStick said:


> @Veii
> 
> 
> Spoiler: current state...1,5 VDIMM, 0,840 CPU VDDP
> 
> 
> 
> 
> View attachment 2481943
> 
> 
> 
> Regarding the disapproval, I can't say that was my impression from this thread. Certainly not a sentiment from me. I only understand half of what you say but it's still been helpful lol.
> 
> I tried a few things and now I'm looking at 56,3 -58,3 at the current settings, though the majority are in the 56ish ns range, so I feel like we're getting closer. And if nothing else latency is improving.
> Since lowering seems to be working better, I lowered SOC again, and that seemed to help a bit, but the settings are getting more sensitive now. I am no longer able to run 6/3/3 or 6/3/4, That said, the last run on 6/3/3 had the least variance, but higher latency than the current settings. I tried at CLDO VDDP 0,840 but that was worse (from 0,850), then 0,860 and 0,855 wouldn't boot.
> Setting PBO limits to motherboard was worse, I went from 56ish to 59ish in latency and it was still swinging.
> 
> I tried with tcke 1 just to see what that would do, but I didn't notice any difference. Had to lower ClkDrvStr to 40, but I don't remember the exact settings I had for that test.
> Not sure what to try next? I 've seen some people run with RttNOM disabled, I haven't tried that yet.


use tRC of 52 for now (fix tRFC then) , else drop tRAS to 32 again
if you use tCKE and SETUP Times - you need to have X-20-20-20 CAD_BUS , else it's getting too strong
on X-20-20-20, you then sync the cutting times correctly 
soo either 40-20-20-20 or 60-20-20-20, but they do not go alone  
tCKE can go alone ~ but once you use SETUP times, you have to frequency match it correctly
(which you technically do but CAD_BUS is wrong)

You can give 900-1050-1100-1187.5 a chance
VDDP , CCD, IOD, SOC 
if it improves latency


----------



## PowerK

Slightly tuned voltages down. Passed overnight TM5.


----------



## paih85

Veii said:


> Where did you copy CAD_BUS 40-20-20-20 from ?
> And why do you start with 1T GDM off, instead 2T ?
> You would have 4-5 different problems needing to take care at the same time
> 
> timings
> RTT powering
> cad_bus
> voltages
> WHEA errors or autocorrection
> 
> too many things , don't just go in without a plan
> step by step - achieving what other users run here
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> can take weeks of testing , or spread trough several weeks as short sessions
> 
> 40-20-20-20 alone on it's own, is not correct
> RTT are too strong on their own too
> use 6/3/3 for 2x 16gb


noted @Veii 

done test GDM off/2T.


----------



## GribblyStick

Veii said:


> use tRC of 52 for now (fix tRFC then) , else drop tRAS to 32 again
> if you use tCKE and SETUP Times - you need to have X-20-20-20 CAD_BUS , else it's getting too strong
> on X-20-20-20, you then sync the cutting times correctly
> soo either 40-20-20-20 or 60-20-20-20, but they do not go alone
> tCKE can go alone ~ but once you use SETUP times, you have to frequency match it correctly
> (which you technically do but CAD_BUS is wrong)
> 
> You can give 900-1050-1100-1187.5 a chance
> VDDP , CCD, IOD, SOC
> if it improves latency


I thought above 1,050 IOD would be considered dangerous already. As in that will likely cause degradation over time? 
In that sense I am already not exactly comfortable with 1,06. Or has this limit also gone up?


----------



## craxton

@Veii this is the (guide) i speak of, which is rather old by now. but
im pretty sure the same ruleset still applies?


Veii said:


> Here it is reuploaded somewhere else
> 
> 
> Free File Hosting - Online Storage; Upload Mp3, Videos, Music. Backup Files
> 
> 
> Just picked a random site that was used on me
> Check
> 
> 
> 
> 
> 
> 
> 
> 
> AGESA FW stack patched bioses for 3rd gen
> 
> 
> I decided to put these under a separate thread, since there are already quite many bioses available. File naming: Original bios build (version), M = modified, FI (4649 ASCII, i.e. SMU 46.49). Besides the actual SMU FW, these files also contain up to date PSP, PMU (IMC) FWs, bootloaders and...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> and post #4 , how to use flashrom
> make a backup of your current rom - soo you have all the profiles and the warranty saved
> then use flashrom to clean flash the shared bios
> It's modified, soo it won't pass in-bios signing key check
> but it's not broken modified, soo it will 100% pass the flash
> 
> If flashrom finds nothing "no flash-chip"
> then your board has an external flash chip & you should follow the manufactures procedures in using that one (away from the bios)
> 
> You can also google the tool with the exact same model number in order to find it
> I did quite a few modifications, soo i wonder if you can see any changes after you flash it ~ without much more work involved in unhiding stuff via hex
> I can't share AMI copyright software ~ but you can easily get your hands on it if you search


as im unsure what you mean by "google the tool with the exact same model number"
i dont know if you mean google flashrom msib550 gaming edge wifi, or
ive read that entire post, your comment included (post #4) and still dont quite understand 
as ive downloaded from unmentioned, but when extracting the contents, it gives, C files, H files etc with no exe?

you didnt need to reupload, i already downloaded the file. i had just never heard of that site, reminds of weboasis 
which has alot of one click methods for well, pretty much anything someone could ask for in terms of internet ....if you click 
youll know what i mean. 

(am i suppose to open this using command line?)


----------



## Veii

GribblyStick said:


> I thought above 1,050 IOD would be considered dangerous already. As in that will likely cause degradation over time?
> In that sense I am already not exactly comfortable with 1,06. Or has this limit also gone up?


AMD max overclocking voltage this post mentioned it very well
The hardcap for CCD is near 1050, for IOD at exactly 1150, on SOC at exactly 1.3v
for cLDO_VDDP also 1050 (which is far to much btw) 

the SOC limit went up as 100mV before starting to do any harm
I'm still a bit uncomfortable running 1100mV IOD (actually more uncomfortable with CCD, less on IOD ~ as 2133+ FCLK needs 1100 IOD)
But at the end of the day, VDDG is still one line and dynamically adjusts both ~ soo one can be lower than the other while the higher one is pushing the average up

At the end, 49.5 ns look good, but i have to see if the 80mV loss on required SOC with over 100mV bump on VDDG , is worth the trade
Thermal density wise and stability & latency wise
Let me first get a good 48.X ns result and have my RTTs once and for all ~ fixed
Then i'll focus again on it
2100 is nearly perfect with the same voltages, but i see a little package throttle, as memory doesn't hit a perfect half on Write speeds anymore. It intentionally is slowed down by a tiiny bit ~ because the lack of voltage

Although my main current issue, is 4200C15-15 at 1.62v ~ 1.64 runs, but i want less not more of it
10mV more would resolve the issue, but it's no resolve for me 



craxton said:


> which has alot of one click methods for well, pretty much anything someone could ask for in terms of internet ....if you click
> youll know what i mean.
> 
> (am i suppose to open this using command line?)


look up how and where to get that exact AMIBCP version, i should not share it 
Read the flashrom guide by The Stilt, and the demonstration & backup illustration on post #4

Prepare windows to run the custom rufus with the missing diskcopy.dll and make a tiny MS_DOS (not freedos) USB
place the flashrom & it's exe files on the root of the USB, just on the made by rufus usb
place the named bios file i uploaded on the usb
make a backup of your whole rom chip, like post #4 suggests for warranty reasons and if the bios is buggy to revert (or revert back, at anytime in the future)
afterwards write-flash the changed bios and see if you spot any major differences
(there should be many)
If YES, then check what i changed with AMIBCP, if NO ignore what i changed but still check it ~ as that's the order how it should be done 
if NO, head to winraid and maybe ask & learn from LOST_IN_BIOS user, how to unlock AMD CBS and overall unhide stuff "in NVRAM, as AMIBCP was not enough"


----------



## Veii

paih85 said:


> noted @Veii
> 
> done test GDM off/2T.
> 
> View attachment 2481962


on this tRFC, tWR 12 and 16 work
also tRTP 6,8,9 work
now try to run 1T and give it a bit more voltage (+10mV is enough) ~ update ZenTimings 

Keep an eye on the DATA log for TM5








Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com




Potentially increase tRRD_ with tFAW and if needed tWTR_

Good luck


----------



## Br3ach

PowerK said:


> Slightly tuned voltages down. Passed overnight TM5.
> 
> View attachment 2481954


Thanks for sharing man, your Rtts also work for me. 3866 stable at 2T (4x SR DIMMs), unlike 7/3/1. For me 28.8 procodt results in a hard reboot though (no blue screen).


----------



## Karagra

Does anyone have a loose timing 4000mhz setup I can try to start with for a base? my 3800mhz is stable I don't know if its me just messing up with 4000mhz or my chip just isnt having 2000 fclk


----------



## Veii

Karagra said:


> Does anyone have a loose timing 4000mhz setup I can try to start with for a base? my 3800mhz is stable I don't know if its me just messing up with 4000mhz or my chip just isnt having 2000 fclk


[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread 
On a 2 Dimm board, pretty much clone everything - unless you have better voltages
tCKE 11 is for 4000+
tCKE 12-14 is for 4200+


----------



## mongoled

Will catch up later on this thread, unfortunately my dedicated server was in the OVH Strasburg complex 😕

Hoping to have emails back up and running by tomorrow evening with website following later, thankfully my backups are all intact..


----------



## Flash1228

Hey, @Veii 

I've been having another go at 4000 just using xmp timings to try and get it WHEA free before mucking about too much. I started with constant spams of WHEA errors and after reading through a lot of your posts (and a lot of trial and error lol) with these settings I can do testmem5 without errors and no WHEAs showing up, but as soon as I start AIDA benchmark WHEAs start rolling in. I've tried increasing/decreasing vSOC, CLDO VDDP, both VDDGs changing procODT around and anything but this setup gives at least a few WHEAs as soon as I get into Windows. I changed VDDP in AMD > CBS to .880 and with .900.

Any suggestions? Or am I just kinda out of lock on 2000fclk for now at least lol


----------



## Veii

Flash1228 said:


> Hey, @Veii
> 
> I've been having another go at 4000 just using xmp timings to try and get it WHEA free before mucking about too much. I started with constant spams of WHEA errors and after reading through a lot of your posts (and a lot of trial and error lol) with these settings I can do testmem5 without errors and no WHEAs showing up, but as soon as I start AIDA benchmark WHEAs start rolling in. I've tried increasing/decreasing vSOC, CLDO VDDP, both VDDGs changing procODT around and anything but this setup gives at least a few WHEAs as soon as I get into Windows. I changed VDDP in AMD > CBS to .880 and with .900.
> 
> Any suggestions? Or am I just kinda out of lock on 2000fclk for now at least lol
> 
> View attachment 2481985


You auto correct and probably overvolt the poor dimms. GDM on and yet high ClkDrv & decently high RTTs
get it stable at 2T GDM off
About WHEA, i think many are out of luck
It's a bios issue , if WHEA is #19 then there is barely anything you can do
You could try to keep global C-States on but disable DF_C-State generation near CPPC

I can't help you much. it's broken agesa (ABL) that causes issues
Fabric WHEA can have a connection with Ethernet issues, USB Issues, PCIe 4.0 issues ~ many things

I dont get WHEAs, only hard crashes on little issues and active autocorrection
(where benchmark consistency matters the most for my setup)
Else on this set pretty much everything is awkward, but that's XMP + board prediction


----------



## GribblyStick

@Veii 
sorry I don't like spamming like this but maybe I have a misconception about voltages.



> AMD max overclocking voltage





> this post mentioned it very well
> The hardcap for CCD is near 1050, for IOD at exactly 1150, on SOC at exactly 1.3v
> for cLDO_VDDP also 1050 (which is far to much btw)


I read the thread, but it was my understanding that it's not just "perfectly chill" -> "risk of frying"
In other words, I understood the 1,050 to be the safe limit up to which you should be fine.
Then a gray zone which still works without the risk of frying your parts, but that probably will degrade your components over time.
And only then do you enter no mans land where you experiment at your own risk.

So up to 1,05 would be safe long term (for IOD in this case), and up to 1,150 you risk degradation over time, and then you start risking killing stuff.
In my case I intend to run this setup for 5+ years, so degradation becomes an issue and I'd rather miss out on the best my parts can do if I have to.
What your saying is anything up to the limits is actually fine to use long term?


----------



## Karagra

Veii said:


> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> On a 2 Dimm board, pretty much clone everything - unless you have better voltages
> tCKE 11 is for 4000+
> tCKE 12-14 is for 4200+


Yeah my bios still goes into slow motion.. almost like its going through selections at like 1fps trying to change frames.. you think its the processor or the ram? If its the processor I am happy with 1900fclk but if its the ram I don't mind grabbing a new set.


----------



## Flash1228

Veii said:


> You auto correct and probably overvolt the poor dimms. GDM on and yet high ClkDrv & decently high RTTs
> get it stable at 2T GDM off
> About WHEA, i think many are out of luck
> It's a bios issue , if WHEA is #19 then there is barely anything you can do
> You could try to keep global C-States on but disable DF_C-State generation near CPPC
> 
> I can't help you much. it's broken agesa (ABL) that causes issues
> Fabric WHEA can have a connection with Ethernet issues, USB Issues, PCIe 4.0 issues ~ many things
> 
> I dont get WHEAs, only hard crashes on little issues and active autocorrection
> (where benchmark consistency matters the most for my setup)
> Else on this set pretty much everything is awkward, but that's XMP + board prediction


Thanks for taking a look! I'll try changing up clkdrv and RTTs and then give 2t/GDM off a go. I've got DF Cstates disabled. It is WHEA #19 that I'm getting which I kinda figured it was a BIOS thing. Is that something I should be concerned about if it's not causing crashes or stability issues?


----------



## _frame_

Question. Does really IF 2000 Mhz faster than 1900 Mhz considering same timings and cpu clocks?
With 5600X it is for sure faster, I've tested and have proofs. But in Russian forum (overclockers.ru) they believe that IF 1900 Mhz is faster at least with 5900X.


----------



## Karagra

_frame_ said:


> Question. Does really IF 2000 Mhz faster than 1900 Mhz considering same timings and cpu clocks?
> With 5600X it is for sure faster, I've tested and have proofs. But in Russian forum (overclockers.ru) they believe that IF 1900 Mhz is faster at least with 5900X.


I have 53ns at 1900 where some dont seem to get that low at 2000FCLK. But I also have a massive noticeable difference in fps in-game with a all core overclock to 4.6ghz on my 5800x over letting PBO boost it to 5ghz. Same with my cinebench results so who knows anymore on anything rofl


----------



## nada324

Hello, Currently running Bdie single rank 2x8 patriot 4133 series, i suspect there is something wrong with my timings as i get " high " latency to be at 1900 IF.


----------



## _frame_

Karagra said:


> I have 53ns at 1900 where some dont seem to get that low at 2000FCLK. But I also have a massive noticeable difference in fps in-game with a all core overclock to 4.6ghz on my 5800x over letting PBO boost it to 5ghz. Same with my cinebench results so who knows anymore on anything rofl


My question is only about Infinity Fabric with 5900X and 5950X! 2*ССD processors.
2000 vs 1900 (1866) Mhz
Same settings for cpu, same timings, 1:1:1.
Which is faster 2000 or 1900 (1866)?


----------



## Dasa

ManniX-ITA said:


> did you check with Geekbench 5 at which CCD voltage the AES-XTS score drops?


This is my findings with CCD

VDDG CCD 880mV (850mV results in WHEA in TM5) 
AES-XTS 
4326 7.37 GB/sec 
4370 7.45 GB/sec

VDDG CCD 950mV 
AES-XTS 
4349 7.41 GB/sec 
4352 7.42 GB/sec

Using these settings except it is at 101BCLK which Zentimings doesn't show correctly and -80mV from CPU VDDP=840-852mV.


----------



## Oberst

Got my Vipers stable at 3800 - 14-14-15-14-28-40-240 - 1,52 vdimm, RTT 7/0/6 Thanks @Veii ! Also set tRFC2/tRFC4 according to the calculator, totally forgot about that previously. With tRCDRD - 14 I get errors in TM5 - test 10, I think I have to play around with tRDWR/tWRRD.


----------



## adversary

I have running my first AMD PC ever for few days (was waiting for CPU to arrive, there was delay). I have no any direct expirience except what I read and catch here on forum. Still total novice and noob  . So please understand that I may totally miss some of setting in RAM settings.

Here is my expirience and questions, and setup :

5600X
Asus TUF B550 Gaming Plus motherboard
GSkill 2X16GB RAM 3600 C14-15-15 1.45V (it should be Samsung B-Die). Ram is exactly this one :









F4-3600C14D-32GTZR - G.SKILL International Enterprise Co., Ltd.


Trident Z RGB DDR4-3600 CL14-15-15-35 1.45V 32GB (2x16GB) Featuring the award-winning Trident Z heatspreader design, the Trident Z RGB memory series combines vivid RGB lighting with awesome DDR4 DRAM performance.




www.gskill.com





At first, I did run XMP which is 3600-14-15-15. SOC voltage is all time on Auto, which show in BIOS 1.100V, in HWInfo 1.087V. Latency was 58.5ns.
After that I did, without touching any timings, set FLCK to 1900 and RAM to 3800. It required to up RAM voltage, if I recall well, to about 1.485V. It did cut off latency just slightly, to about 57.X range.
Than I turned off GDM (interesting, it did not required any voltage boost). Command rate auto switched to 2T, but latency gone down, to about 56ns.

I did try to set command rate to 1T, but no matter voltage I did try, it did not returned me to BIOS asking for F1 (as happen when I screw up something), but it try to boot to Windows and than some error message appear, and it auto restarts.

After that, I did restart BIOS to default and started from 0. Did not load XMP, but did manually set everything, including some tweaking of RAM which I attach as picture. This required setting RAM voltage slightly more than 1.5V, but produced nice 53ns (alond with Read and Copy boost) latency, sometimes few ns 0.X less or more.

For ProcODT, it seems it can work with less than 40, but I did leave it at 40.

As I said I have not much knoweledge about this still, so I even do not know what is for example RttNom, ClkDrvStr, CsOdtDrvStr, etc. I just did set ClkDrvStr to 60 as I did read somewhere Veii advised someone to set it higher, besided that I had no idea what I'm doing with such settings. All others are left on Auto.

So far, this settings works nicely for me, along with PBO, in application I'm running. CPU is on custom EKWB watercooling, RAM is on air cooling (set strong fan to blow air on it, but I have EKWB equipment for RAM cooling, if need arise). Application which I run is very RAM demanding and will crash on any RAM instability. With fan, even with 1.5V+, it never goes above 35C during prolonged use of application. No crash happened.

I also did Memtest (first time for me), I set 16GB value (correct me if it have to be used in different way), not all night, but for some time, and no error happened.


Please, correct me for whatever I did set wrongly, or what can be done better.


Now, something about FLCK above 1900. I did not have any success with it. No matter SOC and other voltages, for 1966 and 2000 FLCK, I always end with returning to BIOS claiming it detected instability.

On some occasions, I was able to run 1933 FLCK, with SOC voltage of 1.15V. But I have feeling something is wrong there, it simply do not work always.

And when I was able to run 1933 FLCK, voltage demand on RAM was very high. Only to maintain 14-15-15 (without any addition tweaking - which also need little more voltage) on 3866, I needed about 1.6V. And it produce worse result than 1900 FLCK with tweaked timings on little more than 1.5V.

This should be Samsung B-Die. It have no logic to me, why it can run timings showed in attachment at 3800 at little more than 1.5V, but need 1.6V for 3866-14-15-15 with no any additional timings tweaking (all other timings on Auto) ?

What I did wrong, and how I would be able to run more than 1900 FLCK properly? Of course, I'm aware I may totally mistaken some settings, as I have no knoweledge about it (that would be best case scenario, because simply by correcting some settings from advices of others, higher FLCK may become possible).

Could it also be bad luck with lottery, regarding CPU, or RAM, or ever motherboard?

This BIOS have AGESA V2 PI 1.2.0.0, and SMU 56.45.0. It is not hardlocked to 1900 FLCK or?

@Veii mentioned something like "up to 2000 FLCK is BIOS dependant, after it it is up to CPU or RAM".


----------



## SaarN

Hey guys,
I think I made a mistake and posted my first message in the wrong thread, so I'll make it quicker this time.
I'm new to OCing but read the guides and I would love to get some feedback on my first ever attempt.
I got a DR 3600CL18 kit from Corsair with SK Hynix chips that are probably DJR (since can go lower than 450 TRFC).
DRAM voltage is 1.42v and the kit really doesn't handle heat well.
I'm pretty sure I made a mistake with the TRDWR and TWWRD values, they should be 3\13 if my memory serves me right.
How can I shave those last 4 secs? I'm feeling like better DRV\RTT values may give addtional breathing room, but I have no idea how to work with them.


----------



## PJVol

@*Veii*
Hi! Do you now what "FCLK OC Mode" is?


----------



## Flash1228

PJVol said:


> @*Veii*
> Hi! Do you now what "FCLK OC Mode" is?


Not Veii, but I imagine that lets you manually set fclk as after a certain memory speed it'll drop from 1:1 to 2:1 if set to auto


----------



## Dasa

Flash1228 said:


> Not Veii, but I imagine that lets you manually set fclk as after a certain memory speed it'll drop from 1:1 to 2:1 if set to auto


More likely something that reduces performance in exchange for some stability at higher IF by changing hidden BIOS settings.



PJVol said:


> Hi! Do you now what "FCLK OC Mode" is?


Something that popped up in a recent BIOS or has it always been there on your MB?


----------



## Comalive

Flash1228 said:


> It is WHEA #19 that I'm getting which I kinda figured it was a BIOS thing. Is that something I should be concerned about if it's not causing crashes or stability issues?


Just use your system, I would expect you to get random system reboots at some point.


----------



## PJVol

Dasa said:


> Something that popped up in a recent BIOS or has it always been there on your MB?


There's corresponding wmi method in AMD_ACPI instance, listed from ZenTimings debug log.

I'm just trying to understand, is it possible to set certain params via WMI bios request. Instance itself can be get through Get-WmiObject -namespace "root/WMI" AMD_ACPI

There's also EDC Throttler Control


----------



## heptilion

@Veii 

Do you have all these three enabled or on auto?

Address hash bank
Address hash CS
Address hash Rm


----------



## GribblyStick

PSA for ASUS crosshair 8 hero (wifi):

Version 3302
2021/03/10 20.43 MBytes
ROG CROSSHAIR VIII HERO(WI-FI) BIOS 3302

Update AMD AM4 AGESA V2 PI 1.2.0.1
Improved system performance
Improved system compatibility
Improved memory performance


----------



## H1N1-JohnyBoy

*Registered* just to thank you all! Especially the guy everyone seems to look up to *@Veii* Thank you so much dude! (BEWARE I AM A NOOB DON'T COPY ME)

-* Context:* bought *5800x* around launch date + 2x16gb Trident Z Neo F4-3600C14D-32GTZN *dual rank*,

I tried all the bios and beta bios from asus but was stuck to get past *FCLK 1866*, 1900 didnt boot, until I learned about the *1900 fclk black hole *

tried and booted up to 2000 flck, was happy but also I knew I had to check for those *WHEA errors* (which I was happy never had before lol) and of course I had whea errors in *HWinfo* with *y-cruncher* ,

currently running :

*bios 3405* on *Asus X570-e gaming *with *FCLK 1966 vsoc LLC 4 *
Trident Z Neo F4-3600C14D-32GTZN *3933 mhz 16-16-16-32-48 DUAL RANK *

Finally my system looks stable no errors after 40min y-crunsher and also with testmem5 [email protected]

*BUT*

From what I gathered from Veii here and there but maybe the context was different :

*- Dual rank 2 dimm* could use : timing 1-4-4-1-6-6 , procodt 34.3 (also 36-69ohm is range for 4000+), use 6/3/3 RTT with CAD BUS 40-20-40-20 as a start, 60-20-40-24 works too

*- CR2T GDM off* could use : CAB BUS 24-20-20-24 or 60-20-20-20 , if problem posting you need to up tRFC, also read 40-20-24-24 to get away with CR2t
High procodt and high CLKDRV not good, we want balance, so if 60 clkdrv try to drop procodt a bit
*
-HIGHER FLCK*: lower procodt helps reach max fclk

*Problem *is mixing all the above into a one!

So I tried procodt 34.3 with 6/3/3RTT CAD BUS 40-20-40-20 or 60-20-40-24 or 60-20-20-20 but its unstable (and a **** ton of other combos)

I then reloaded an older bios profile I had made for CR2T at that time with 3733mhz, changed the settings to 3933mhz + the timing but left all the procdt and cad bus like it was and

booooom voilà, it works!!

So basically what I changed from instable to stable was exactly this: procodt from 34.3 to 40ohm RTT 6/3/3 to 0/3/1 and cadbus to 60-20-20-20 (What do you think was the problem?)










*Would appreciate if the man himself could take a look at my settings, *but feel free to give your advice if you think you can help


----------



## PJVol

It nice, that you find a way to run IF>1900 stable, that's the issue for the majority here. And as far as i can tell, its not related to memory settings in any way. I set ram with really loose timings @3600, and with any IF in 1933-2100 range whea starts dropping. That is MCE interrupts at least, which needs to be handled, hence the performance drop.
Need to test with 56.45 or 56.46 though, to make final conclusions. Or...

install that cpu in work PC, with msi board, to check, whether asrock mess with their latest firmware.


----------



## GribblyStick

I'm going to start from scratch with the new bios but at least for me , it did nothing to combat variance or support of 4000/2000, still WHEA city on top of becoming a slideshow.
On the plus side though, it did double my L3 read/write/copy speeds. So I've got that going for me.


----------



## Hale59

heptilion said:


> @Veii
> 
> Do you have all these three enabled or on auto?
> 
> Address hash bank
> Address hash CS
> Address hash Rm


What does DRAM Calculator tell you?


----------



## Flash1228

Hale59 said:


> What does DRAM Calculator tell you?


DRAM calculator doesn't have these options listed. I've got these in the AMD CBS menu in BIOS too and the choices are auto, disabled, or enabled.


----------



## paih85

Veii said:


> on this tRFC, tWR 12 and 16 work
> also tRTP 6,8,9 work
> now try to run 1T and give it a bit more voltage (+10mV is enough) ~ update ZenTimings
> 
> Keep an eye on the DATA log for TM5
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Potentially increase tRRD_ with tFAW and if needed tWTR_
> 
> Good luck


huhu..still no luck with gdm off/1T. already test up to 1.47v. maybe need to touch trrd/tfaw/twtr later.


----------



## paih85

H1N1-JohnyBoy said:


> *Registered* just to thank you all! Especially the guy everyone seems to look up to *@Veii* Thank you so much dude! (BEWARE I AM A NOOB DON'T COPY ME)
> 
> -* Context:* bought *5800x* around launch date + 2x16gb Trident Z Neo F4-3600C14D-32GTZN *dual rank*,
> 
> I tried all the bios and beta bios from asus but was stuck to get past *FCLK 1866*, 1900 didnt boot, until I learned about the *1900 fclk black hole *
> 
> tried and booted up to 2000 flck, was happy but also I knew I had to check for those *WHEA errors* (which I was happy never had before lol) and of course I had whea errors in *HWinfo* with *y-cruncher* ,
> 
> currently running :
> 
> *bios 3405* on *Asus X570-e gaming *with *FCLK 1966 vsoc LLC 4 *
> Trident Z Neo F4-3600C14D-32GTZN *3933 mhz 16-16-16-32-48 DUAL RANK *
> 
> Finally my system looks stable no errors after 40min y-crunsher and also with testmem5 [email protected]
> 
> *BUT*
> 
> From what I gathered from Veii here and there but maybe the context was different :
> 
> *- Dual rank 2 dimm* could use : timing 1-4-4-1-6-6 , procodt 34.3 (also 36-69ohm is range for 4000+), use 6/3/3 RTT with CAD BUS 40-20-40-20 as a start, 60-20-40-24 works too
> 
> *- CR2T GDM off* could use : CAB BUS 24-20-20-24 or 60-20-20-20 , if problem posting you need to up tRFC, also read 40-20-24-24 to get away with CR2t
> High procodt and high CLKDRV not good, we want balance, so if 60 clkdrv try to drop procodt a bit
> 
> *-HIGHER FLCK*: lower procodt helps reach max fclk
> 
> *Problem *is mixing all the above into a one!
> 
> So I tried procodt 34.3 with 6/3/3RTT CAD BUS 40-20-40-20 or 60-20-40-24 or 60-20-20-20 but its unstable (and a **** ton of other combos)
> 
> I then reloaded an older bios profile I had made for CR2T at that time with 3733mhz, changed the settings to 3933mhz + the timing but left all the procdt and cad bus like it was and
> 
> booooom voilà, it works!!
> 
> So basically what I changed from instable to stable was exactly this: procodt from 34.3 to 40ohm RTT 6/3/3 to 0/3/1 and cadbus to 60-20-20-20 (What do you think was the problem?)
> 
> View attachment 2482057
> 
> 
> *Would appreciate if the man himself could take a look at my settings, *but feel free to give your advice if you think you can help


what ur vdimm? can share here?


----------



## Veii

heptilion said:


> @Veii
> 
> Do you have all these three enabled or on auto?
> 
> Address hash bank
> Address hash CS
> Address hash Rm


I have them on enabled, and if your CBS allows it - enforce BGSAlt to enable
It gives you a HEX value to further play with
If your's is different, we maybe can align it
Haven't seen any specific reason to not run them ~ yet
It's on the waiting list, priorities for research are on other places for now.
At least they don't bother. If they are beneficial at all, has to be seen


H1N1-JohnyBoy said:


> *Registered* just to thank you all!
> @Veii Thank you so much dude!
> *Problem *is mixing all the above into a one!
> 
> So I tried procodt 34.3 with 6/3/3RTT CAD BUS 40-20-40-20 or 60-20-40-24 or 60-20-20-20 but its unstable (and a **** ton of other combos)
> 
> I then reloaded an older bios profile I had made for CR2T at that time with 3733mhz, changed the settings to 3933mhz + the timing but left all the procdt and cad bus like it was and
> 
> booooom voilà, it works!!
> 
> So basically what I changed from instable to stable was exactly this: procodt from 34.3 to 40ohm RTT 6/3/3 to 0/3/1 and cadbus to 60-20-20-20 (What do you think was the problem?)


Thank you~ 🙇‍♂️
Also thank you for sharing the RTT information 
Sadly i couldn't figure out what vDIMM you run

These RTTs and the impedance settings around them, are for high voltage
and only to keep up stability and not overvolt the poor PCB
I think your errors would come on Idle or between tests
On sub 1.5v it shouldn't matter, but i do not suggest to run RTT_PARK /1 on anything . . . at all
It's too high 
Even if you figure out a combination with X/X/2 , would be better , high but still better
The limits changed on Vermeer and it's not recommended to follow the old RTTs that where suggested
2 dimms need it even less than 4 dimms

I kind of have a suspicion, that Daisy Chain still only provides 75% to one set - even if there is no 2nd set plugged in
As 6/3/3 was found on an X570 ITX board
Atm i try my luck with 6/3/6 on 2x8 - but we'll see. It's instability hell for me @ 4200C15-15 , have to utilize all the tricks i know 

Anyways, i doubt a bit your stability
Run y-cruncher with ALL of the tests ~ as 4 loops
4*18min (2min *9 tests)
If that doesn't crash out of nowhere, then you are fine for now

But before doing so , 3 little things

grab TurboV for your board ~ soo you have access to the external voltage regulation chip and can test stuff like CPU VDDP @ 880mV / away from 930mV on stock ~ unless asus changed it finally down to 900mV
increase your default boosting limits, as you are clock stretching , simply as memory OC falls into your boosting target
what we can do now with the current bios is running EDC set as 400 to hit the short term cache boost ~ but limit TDC to 98 or 100A, and PPT up to 160W
Depends really what you can cool, but SOC will take 18-20W for itself, soo increase the powerlimits higher
We want an tight TDC limit to prevent instability and the CPU overvolting itself with open PBO limits.
In the older days EDC was used to limit provided allcore voltage and TDC to limit boost voltage
Sadly this does not work anymore if you want that cache boost. Soo TDC needs to be our voltage limit and subtle bit the PPT limit (which is a global current limit ~ PSU limit)
Report back 


PJVol said:


> @*Veii*
> Hi! Do you now what "FCLK OC Mode" is?


It's the flag that disables CPU voltage autocorrection and disables variable FCLK/MCLK
The first part of this feature mattered a bit ~ but it goes together with APBDIS


Spoiler: Here is a little bug of it














No wonder it's disabled
Sadly i haven't looked into flags for enforcing/overriding MCLK & FCLK
Else it would be useful to only set a "target FCLK" - the variability of it would provide a higher boost
Because you lose 20W of the powerbudget, by running a high MCLK
The same cut goes into the EDC limit , which is a FUSE limit. Nothing we can do about it
It might appear higher, but FIT won't allow to bypass that FUSE limit at any cost.
Logically this limits your allcore performance a lot, on a high FCLK (sad)
It's only bypassable on a fixed frequency ~ and likely why 1usmus now prefers his allcore over PBO

I'm still a PBO person, but if his tool continues to get better ~ likely jump to his PX "internal boost override" algorithm at the end
Depends if i can cool that 
Mr. Hallock doesn't want to acknowledge the "fuse" EDC limit that exits.
While the cache boost, is a temporary short term internal overdrive boost.
Which strongly throttles down later ~ which you can see on CPU-Z Benchmarks

Maybe you have read the sentence "You are driving ryzen like a sportscar, it's a dynamic system"
That's part of the reason 
I run APBDIS Mission mode 0, and force disabled SOC Overclock mode ~ with SOC provided by the PWM controller not the SOC OC VID model
In case AMD decides to allow us someday back the variable MCLK, FCLK part


Oberst said:


> Got my Vipers stable at 3800 - 14-14-15-14-28-40-240 - 1,52 vdimm, RTT 7/0/6 Thanks @Veii ! Also set tRFC2/tRFC4 according to the calculator, totally forgot about that previously. With tRCDRD - 14 I get errors in TM5 - test 10, I think I have to play around with tRDWR/tWRRD.


3800 on ours need around ~1.54-1.56v
The PCB is to blame
If you can't go higher , drop tRDWR one or even 2 (on 14-14-14) down
A0 dimms can run -1 on tRDWR without issues

Check this 








28ohm procODT runs, but you should test couple of Aida64 runs to confirm you aren't autocorrecting
You can exceed now 1.52v as long as you don't go back to RTT_PARK /5
005 will very likely kill your PCB near 1.54-1.56v and only keep stability up till 1.51/1.52v
706 or anything with XX6 will allow you to go near 1.6+
I run 1.62v on them now
(although try to find a sweet spot near 1.62 with 636 now ~ experimenting with powerdown & Dynamic ODT)








I think i figured it out - let's see 
No more annoying error 1, or 11 crashes 😐
Voltages need to be a tad higher, but maybe they are fine ~ i think i still slowly package throttle. Like 0.4% loss of perf


Flash1228 said:


> Thanks for taking a look! I'll try changing up clkdrv and RTTs and then give 2t/GDM off a go. I've got DF Cstates disabled. It is WHEA #19 that I'm getting which I kinda figured it was a BIOS thing. Is that something I should be concerned about if it's not causing crashes or stability issues?


Uhm, go with it ~ if it keeps up being only Error#19
It's a "bios thing"
But WHEA will appear for peripheral too. Which includes also the buggy Realtek 2.5gbit ethernet and usb issues
(i also dont have lol)

@GribblyStick
I can't tell , as we are atm not even sure if this is really 12nm IMC from the 2700X
Considering it is reported as K19.2 now , which is 7nm 

I can give you a concrete answer if i knew what sillicon colour was changed. On which units
On the whole fabric for sure, as the limit is now 1.3v for normal users ~ not 1.2v anymore
IOD depends on the IO/Die 
But 1150 was it , not 1050
1050 was CCD , but matisse autocorrected both and they still are leveraged together

Even if one was higher and the other one low
Like i started with 
900-940-1060-1250
instead of 
900-1050-1100-1200 (now for 2100)

It has to be seen which voltage path we should take
Either high SOC and letting VDDG take as much as it really needs with low set limits
Or overall everything high, but with as tight / less ~ as possible, play room

Can't answer this without knowing if the IODie and IMC really was remade and swapped out in secret or not
Degradation should already show on the longer testing sessions
At least on SOC i haven't seen anything.
Personally i feel more uncomfortable pushing high VDDG CCD, than pushing high IOD
at the end the little memory controller only gets 900mV cLDO_VDDP ~ and the IO-Die , is well for "I/O"  and the links outside of the fabric
I wouldn't worry too much about that one ~ but if it's unstable, you should get strange symptoms like USB, Audio, PCIe 4.0 crashes 
All sort of I/O funkiness ~ even high DPCLatency 

But again, i do worry more about the VDDG CCD at 1050 , than IOD at all


----------



## PJVol

Veii said:


> I run APBDIS Mission mode 0, and force disabled SOC Overclock mode


Ain't setting it to 0 suggests following setting Soc P0 to some value, or it will stay fixed anyway?


----------



## shaolin95

wrong thread


----------



## Hale59

Flash1228 said:


> DRAM calculator doesn't have these options listed. I've got these in the AMD CBS menu in BIOS too and the choices are auto, disabled, or enabled.


Did you ever look at the advanced Tab of the DRAM Calculator?
All suggested ram tweaks are there.


----------



## Flash1228

Hale59 said:


> Did you ever look at the advanced Tab of the DRAM Calculator?
> All suggested ram tweaks are there.


This is what I see. Memory interleaving size, Memory interleaving, and Channel interleaving hash, but not address has bank, address hash cs, or address hash rm. Unless I'm missing something?


----------



## H1N1-JohnyBoy

PJVol said:


> It nice, that you find a way to run IF>1900 stable, that's the issue for the majority here. And as far as i can tell, its not related to memory settings in any way. I set ram with really loose timings @3600, and with any IF in 1933-2100 range whea starts dropping. That is MCE interrupts at least, which needs to be handled, hence the performance drop.
> Need to test with 56.45 or 56.46 though, to make final conclusions. Or...
> 
> install that cpu in work PC, with msi board, to check, whether asrock mess with their latest firmware.





paih85 said:


> what ur vdimm? can share here?


vdimm 1.5v totally forgot


----------



## T[]RK

Anyone got luck to disable GDM on Team Group RAM (Samsung B-die)? I currently tune my XMP timings, got stable boot in windows and pass some benchmarks (Cinebench R20, 3DMark Time Spy CPU test, AIDA64 CPU PhotoWorxx), but if i disable GDM with 1T - blue screen before windows log in screen.

Here my current timings (basicly it's heavy tuned XMP profile)








I used Google Ryzen Calculator for timings, but didn't touched CAD_BUS block (it's currently in Auto) and Termination block, except procODT (53.3 => 34.3).

I tested procODT in AIDA64 Cache & Memory benchmark. Procedure was simple: run test, click on "Write" box when CPU load at 0-1% and let benchmark fill all text data in window, next was "latency" box - same when CPU load drop to 0%. 4 measurements in a row. Usually one will be higher. If diffirence between them more or equal then 1 ns => re-run test from start.

Example:
40Ω
58.7/58.6/58.9/58.6ns | 0.1/0.3/0.3
34.3Ω
58.8/58.7/58.9/58.8ns | 0.1/0.2/0.1

I tested 53.3, 43.6, 40, 36,9 and 32. Lowest latency was with 34.3Ω. And maybe it's just me, but mouse so fast and accurate now... I did few runs in CS:GO with bots and no problem. It's not TM5 test, but i just need to know it can run it "as is".

If there is better way to compare results (not only procODT, but also CAD_BUS) - i would like to know it.


----------



## craxton

T[]RK said:


> Anyone got luck to disable GDM on Team Group RAM (Samsung B-die)? I currently tune my XMP timings, got stable boot in windows and pass some benchmarks (Cinebench R20, 3DMark Time Spy CPU test, AIDA64 CPU PhotoWorxx), but if i disable GDM with 1T - blue screen before windows log in screen.
> 
> Here my current timings (basicly it's heavy tuned XMP profile)
> View attachment 2482113
> 
> I used Google Ryzen Calculator for timings, but didn't touched CAD_BUS block (it's currently in Auto) and Termination block, except procODT (53.3 => 34.3).
> 
> I tested procODT in AIDA64 Cache & Memory benchmark. Procedure was simple: run test, click on "Write" box when CPU load at 0-1% and let benchmark fill all text data in window, next was "latency" box - same when CPU load drop to 0%. 4 measurements in a row. Usually one will be higher. If diffirence between them more or equal then 1 ns => re-run test from start.
> 
> Example:
> 40Ω
> 58.7/58.6/58.9/58.6ns | 0.1/0.3/0.3
> 34.3Ω
> 58.8/58.7/58.9/58.8ns | 0.1/0.2/0.1
> 
> I tested 53.3, 43.6, 40, 36,9 and 32. Lowest latency was with 34.3Ω. And maybe it's just me, but mouse so fast and accurate now... I did few runs in CS:GO with bots and no problem. It's not TM5 test, but i just need to know it can run it "as is".
> 
> If there is better way to compare results (not only procODT, but also CAD_BUS) - i would like to know it.


tforce dark pro 3200c14 4x8  stable daily runner. i was stable with 1t with 2x8 config,
took a while to get 2t stable. (if i had payed a little attention to what was being said to others in the comments tho?)

as for 1t with 4 sticks im unsure as i have yet to change anything. but am about to start at it again.
EDIT: vdimm is set to 1.47 (LLC3 for northbridge) 600khz switching frequency, cpu is on PBO. ive got
no WHEA from what i can gather checking the logger, no issues with FPS games (razer basilisk ultimate) anyhow, if your running 4 sticks, this
may be something you can copy paste for 3800. 
Veii may correct me if that suggestion is wrong.

as for TM5, if your not passing all ram stress tests then i suggest you keep trying until you do,
or youll end up with a new windows install and ALL your games etc GONE!
had this happen to me just 3 months ago, lucky enough i had a backup from October i was able to restore from

anyhow goodluck!


----------



## Hale59

Flash1228 said:


> This is what I see. Memory interleaving size, Memory interleaving, and Channel interleaving hash, but not address has bank, address hash cs, or address hash rm. Unless I'm missing something?
> 
> View attachment 2482110


I am not on my PC right now, so I can't give you a screenshot of that section in my Bios.
But Bios differ according to different motherboards.
When my DRAM calculator suggested 'Channel intervaling hash' enabled, I placed all 'hash' items in my Bios 'enabled'.
Note that some of those sugestions are not available in certain mobos.
For example, there is 1 or 2 items that are specific to Asus mobos. My msi does not have it.
In my mobo, whatever I cannot have enabled, I simple leave it on Auto.


----------



## Flash1228

Hale59 said:


> I am not on my PC right now, so I can't give you a screenshot of that section in my Bios.
> But Bios differ according to different motherboards.
> When my DRAM calculator suggested 'Channel intervaling hash' enabled, I placed all 'hash' items in my Bios 'enabled'.
> Note that some of those sugestions are not available in certain mobos.
> For example, there is 1 or 2 items that are specific to Asus mobos. My msi does not have it.
> In my mobo, whatever I cannot have enabled, I simple leave it on Auto.


I've got an Asus Prime x470 Pro which used to have the settings laid out the same as in DRAM calculator, but since the BIOS updates for 5000 they've changed around a lot so I didn't wanna just flip settings I don't understand on lol


----------



## Br3ach

@Veii do you know if stable Rtts change depending on vdimm or other voltages or are static/scaling?

I know that ProcODT depends on VSoc. My own shenegians have shown longest stable time on unstable settings, with ProcODT 60 ohms at VSoc 1.125 for example. I am now brute forcing lots of RTT combinations to see which combinations take longest-time-to-error. 

But if RTT resistances similarly depend on vdimm or other voltages that would complicate things


----------



## Oberst

Veii said:


> 3800 on ours need around ~1.54-1.56v
> The PCB is to blame
> If you can't go higher , drop tRDWR one or even 2 (on 14-14-14) down
> A0 dimms can run -1 on tRDWR without issues
> 
> Check this


I've seen that screenshot, noticed 7-4 (14-14-14) but I couldn't replicate it.

I can't post at tRDWR/tWRRD 7-1 on 14-14-14. 6-3 is a no go too.
Tried auto timmings on all secondaries, except main and tRDWR/tWRRD -> no post. Tried relaxed manual timings, still no go.

For 16-16-16 I can use 8-1 which is ideal. For 15-15-15 I need 9-2. tRDWR lower than 9 -> no post. Maybe I'm the problem or the dimms.



Veii said:


> 28ohm procODT runs, but you should test couple of Aida64 runs to confirm you aren't autocorrecting


What's the variation that can show autocorrecting taking place?


----------



## adversary

@Veii 
This is what I get so far. I still know very little how setting like Rtt"XXX" or "XXX"DrvStr should be applied related to each other and other settings overall.

Please correct me if I set some of timings wrong way.

This RAM by default work at 3600 14-15-15 1.45V.
Running it at 3800/1900 14-15-15 with all other timings on Auto, except turning off GDM, seems to need 1.5V. But in that case latency is around 56ns (and also lower Read and Copy).

Running this settings I posted in attached picture require 1.55V to be stable, but it is 53ns or slighty less (and solid gains on Read and Copy).

I was able to run 3866/1933, with exact same timings (no SOC or other voltages related to it was needed to be pushed up), which provided about 1GB more on Read and Copy, and about 1ns better latency, but required 1.6V on RAM.

I was not able to run FLCK of 1966 or 2000 no matter what I did try with SOC and other voltages. But it can easily be due to fact I do not have expirience with it and hence I do not know how to adjust all other voltages related to SOC properly. Whatever combination I did try, even with more than 1.2V on SOC, I was not able to run 1966 FLCK (with relaxed RAM timings of course, to try to isolate RAM as cause).

Just to note - SOC voltage is set on Auto, and it always apply in BIOS 1.1V, in case I run 1800, 1900, or 1933 FLCK.


----------



## Veii

PJVol said:


> Ain't setting it to 0 suggests following setting Soc P0 to some value, or it will stay fixed anyway?


0 is keeping it on "mission mode"
it waits for action and is listening
it wont find anything to listen to because the bios disables it once you enforce any ram frequency

1 enforces to fix itself at selected Powertarget
sadly neither P2 nor P3 do anything
AMD is to blame here.
Maybe they do , but no brand on any bios has a feature to enforce specific ram timings

But MSI's bioses look interesting
not only do they have STAMP mode for Vermeer and Cezanne, but also specific telemetry overrides
I wonder if @craxton ever got to try the bios i gave him


Oberst said:


> I've seen that screenshot, noticed 7-4 (14-14-14) but I couldn't replicate it.
> 
> I can't post at tRDWR/tWRRD 7-1 on 14-14-14. 6-3 is a no go too.
> Tried auto timmings on all secondaries, except main and tRDWR/tWRRD -> no post. Tried relaxed manual timings, still no go.
> 
> For 16-16-16 I can use 8-1 which is ideal. For 15-15-15 I need 9-2. tRDWR lower than 9 -> no post. Maybe I'm the problem or the dimms.
> 
> What's the variation that can show autocorrecting taking place?


I know they can do it, but you need to power them well in order to do it and your timings being perfect
If tWRRD is off by 1, it won't post at all 

Variation for instablity on a clean OS
(use WPD & Autoruns for Windows - Windows Sysinternals to disable win-cr*p)
is 0.3ns = instability/autocorrection
0.1ns = run to run variance
Always use the "start benchmark" button ~ never run them in categories, as it won't reach peak boost that way
it needs the preparation phase to warm up


Br3ach said:


> @Veii do you know if stable Rtts change depending on vdimm or other voltages or are static/scaling?
> 
> I know that ProcODT depends on VSoc. My own shenegians have shown longest stable time on unstable settings, with ProcODT 60 ohms at VSoc 1.125 for example. I am now brute forcing lots of RTT combinations to see which combinations take longest-time-to-error.
> 
> But if RTT resistances similarly depend on vdimm or other voltages that would complicate things


They do , the last sentence
They are funny and mostly break on idle states
RTT settings break inside tests and change how proc,soc and clkdrvstr behaves
tCKE then changes the slope between tests and the low power states (soo it scales by MCLK)
SETUP time changes the remain 3 values of CAD_BUS and also is a timed cut, but this one is a global powering one ~ soo you need to start with 20ohm there X-20-20-20 CAD_BUS.
AddrCmdSetup & CsOdtSetup are equal, CkeSetup scales in both together, times 2 & + X (it depends)
Or between tests , for example (2-2-12, 3-3-15, 4-4-18, 5-5-21) between each of the last value scales by +3
2-2-12 would be for 3600, 3-3-15 would be for 3800, 4-4-18 for 4000+ , 5-5-21 for 4200+
(this needs testing if it isn't 5-5-22)
쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네 technical explanation
Anyways, they have a bit of playroom up and down
RTTs if RTT_WR is used, turn into DynamicODT mode, which has only 3 steps + high-z
I haven't figured High-Z out, but for high capacity dimms, you run /2, else /3 works well enough

tCKE is a powerdown on an already functioning powerdown thanks to RTTs
6/3/3 was a combination with X-20-20-20 with tCKE together
Often it runs on alone, but i can see why it might not be fine for some. it just lacks other settings around it
It's not perfect for 4 dimms tho, but is 95% fine
Perfect in the sense of "one RTT to rule them all"
706 for 2x8gb is very very good already but depends on tCKE to be even better
I try to run 636 now - to have 3 powerdown modes together.

As RTT_NOM is used with RTT_PARK ~ you have one powerdown to controll CKE high and CKE low (CKE signal)
If dynamicODT is used, then not only is up and low scope controlled, but also is dynamicly shifted to keep data-eye clean and with less ripple
tCKE ontop then controlls the time between load and after load ~ same as RTT_NOM+PARK, but it's outside of the load , not inside
SETUP time, then like CAD_BUS controls the signal cuts from the IO-Die to the memory
just that SETUP time, makes accurate timed cuts ~ compared to "automatic by load/gate" running CAD_BUS Termination Impedance
(higher the termination impedance = resistance = gate) the harsher the cut but also only at a higher load
SETUP times do allow to time the cut properly ,and using 20ohm as starting values ~ makes the cut softer

High ClkDrvStr does work similar to procODT ~ they are still termination impedances, but also boost the signal in strength. How typical impedances behave with voltage
Too high of one value, will cause crashes and lower the other values
Too low of one value will need equalization from the other value
High ClkDrvStr needs low proc
Low procODT only runs on low voltages and so on
proc still acts like a resistance and won't allow high values to pass, there are upper and lower limits

And yes RTTs are still in impedance values, and do also amplify used voltage
0/0/5 is a strong one for 2 dimms, and without limits can kill dimms on high voltage
it's perfectly fine sub 1.48v and does help positive ~ but is strongly negative beyond 1.51v. Death can occur near 1.56v if you have a sensitive PCB like A0's are


----------



## Veii

adversary said:


> View attachment 2482164
> 
> 
> 
> 
> @Veii
> This is what I get so far. I still know very little how setting like Rtt"XXX" or "XXX"DrvStr should be applied related to each other and other settings overall.
> 
> Please correct me if I set some of timings wrong way.
> 
> This RAM by default work at 3600 14-15-15 1.45V.
> Running it at 3800/1900 14-15-15 with all other timings on Auto, except turning off GDM, seems to need 1.5V. But in that case latency is around 56ns (and also lower Read and Copy).
> 
> Running this settings I posted in attached picture require 1.55V to be stable, but it is 53ns or slighty less (and solid gains on Read and Copy).
> 
> I was able to run 3866/1933, with exact same timings (no SOC or other voltages related to it was needed to be pushed up), which provided about 1GB more on Read and Copy, and about 1ns better latency, but required 1.6V on RAM.
> 
> I was not able to run FLCK of 1966 or 2000 no matter what I did try with SOC and other voltages. But it can easily be due to fact I do not have expirience with it and hence I do not know how to adjust all other voltages related to SOC properly. Whatever combination I did try, even with more than 1.2V on SOC, I was not able to run 1966 FLCK (with relaxed RAM timings of course, to try to isolate RAM as cause).
> 
> Just to note - SOC voltage is set on Auto, and it always apply in BIOS 1.1V, in case I run 1800, 1900, or 1933 FLCK.


Your issue are several
Didn't fix any voltage neither cLDO_VDDP nor VDDG & you use as low as possible tWTR & tRRD
often a bump there is what is needed in order to run lower primaries
Try this at 6/3/3
Voltages you can select between
900-940-1060-1.250 (loadline to 1.225)
or
900-1040-1080-1187.5mV (1.2 with loadline droop)
Both are perfectly fine









==============================================
Also @KedarWolf you get a virtual point/cookie from me for the OCCT suggestion
I still don't WHEA on ~anything~ but it killed stability and i needed to redo the voltages for 2100
(for 2067 they where fine)
Here as requested 


















I improved 
But the voltages missmatch
This is currently my 4th TM5 run, because i was getting random hang-ups on OCCT and was slowly package throttling (0.2% max but still)
The latency results are identical
Just dont want to run the 5th time OCCT and TM5, just to get all in one picture
Waiting another 1:30h for TM5 now (did some tRFC / tRC changes) and later again y-cruncher for an hour 

I hope this proofs stability for you finally
1050 CCD was too high as expected, IOD is okeish (first picture is more up to date with voltages)
trying 830mV CPU VDDP
overall i keep re-running all these 1h tests to get all in one picture, ready for submission 
OCCT Large Dataset, Extreme, AVX2, Variable Pattern, will now remain in my test suite for a freeze check ~ ty


----------



## H1N1-JohnyBoy

paih85 said:


> what ur vdimm? can share here?





paih85 said:


> what ur vdimm? can share here?


1.5vdimm oops tought I put it


----------



## adversary

Veii said:


> Your issue are several
> Didn't fix any voltage neither cLDO_VDDP nor VDDG & you use as low as possible tWTR & tRRD
> often a bump there is what is needed in order to run lower primaries
> Try this at 6/3/3
> Voltages you can select between
> 900-940-1060-1.250 (loadline to 1.225)
> or
> 900-1040-1080-1187.5mV (1.2 with loadline droop)
> Both are perfectly fine





Thank you for reply and help.
Pardon me for all questions I have (and confusion I have), I'm totally new to AMD, have this PC running for just few days and it is first AMD for me ever. I try to catch things reading forum all time, looking at other users settings and results, and your posts, that is how I figured out anything so far.


What you exactly mean by tWTR & tRRD ? As I do not see that exact names anywhere in Zen timings list. Can you state exact name of timing you mention? I guess you refer to tWRRD, but I would not like to go adjust timings wrongly without proper understanding what you exactly mean.

I will try SOC and other related voltages exactly as you recommended to try to see if higher than 1933 FLCK will work for me.

I also read another post from you here, and you state 0/0/5 can kill RAM if used with voltage at 1.56V. As I run 1.55V at moment, I need to know. Is 6/3/3 OK to counter that and be able to run higher RAM voltage?
Just to note, I did try to set higher (I mean, higher number like 4,5,6,7) RttPark, but it can't boot at anything higher than RZQ/3. Not with this tuned timings, not without tuned timings.

My RAM is exactly this one :









F4-3600C14D-32GTZR - G.SKILL International Enterprise Co., Ltd.


Trident Z RGB DDR4-3600 CL14-15-15-35 1.45V 32GB (2x16GB) Featuring the award-winning Trident Z heatspreader design, the Trident Z RGB memory series combines vivid RGB lighting with awesome DDR4 DRAM performance.




www.gskill.com





And I have no idea is that B1 or B2 layout. It is Samsung B-Die 20nm as far as I know. If you know more let me know please.



EDIT - I did try voltages you recommended, and after it failed, some other mix of combinations, but nothing works. Than I did reset BIOS to defaults, set only primary timings pretty relaxed, leave others timings on Auto, try again, but no way, it won't ever boot at anything higher than 1933 FLCK.

One more detail - you recommend to set CLDO VDDP to 0.9V ? Ask because by Auto, it seems to run at 1.0V for me (with some droop, so in Zen timings it ends slightly below 1.0V).

Could it be that CPU is simply have a wall of 1933? Or maybe this BIOS is not ready for that, I have no idea.


----------



## Iarwa1N

Hi guys, I hope someone will answer my question. When I increase memory clock and fckl from 2000 to 2033, aida64 memory read/copy/write scores are increasing each about 500 MB/s but interestingly my latency is increasing from 56 to around 57. Do I need to increase some voltage to improve latency as well?


----------



## Yviena

Hmm i can't seem to find memory interleaving options with AMIBCP with the msi bios for x570 tomahawk, has anyone else found it?


----------



## KedarWolf

Veii said:


> Spoiler
> 
> 
> 
> Your issue are several
> Didn't fix any voltage neither cLDO_VDDP nor VDDG & you use as low as possible tWTR & tRRD
> often a bump there is what is needed in order to run lower primaries
> Try this at 6/3/3
> Voltages you can select between
> 900-940-1060-1.250 (loadline to 1.225)
> or
> 900-1040-1080-1187.5mV (1.2 with loadline droop)
> Both are perfectly fine
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ==============================================
> Also @KedarWolf you get a virtual point/cookie from me for the OCCT suggestion
> I still don't WHEA on ~anything~ but it killed stability and i needed to redo the voltages for 2100
> (for 2067 they where fine)
> Here as requested
> 
> View attachment 2482167
> 
> View attachment 2482168
> 
> 
> 
> 
> Spoiler
> 
> 
> 
> I improved
> But the voltages missmatch
> This is currently my 4th TM5 run, because i was getting random hang-ups on OCCT and was slowly package throttling (0.2% max but still)
> The latency results are identical
> Just dont want to run the 5th time OCCT and TM5, just to get all in one picture
> Waiting another 1:30h for TM5 now (did some tRFC / tRC changes) and later again y-cruncher for an hour
> 
> I hope this proofs stability for you finally
> 1050 CCD was too high as expected, IOD is okeish (first picture is more up to date with voltages)
> trying 830mV CPU VDDP
> overall i keep re-running all these 1h tests to get all in one picture, ready for submission
> OCCT Large Dataset, Extreme, AVX2, Variable Pattern, will now remain in my test suite for a freeze check ~ ty


For your Curve Optimzer overclock, try this.

I can find the GitHub now, but with the attachment change .txt to .zip and unzip.

Here. Download from the Code link. 









GitHub - jasonpoly/per-core-stability-test-script: Test script developed for for easier testing of Zen 3 curve offsets


Test script developed for for easier testing of Zen 3 curve offsets - GitHub - jasonpoly/per-core-stability-test-script: Test script developed for for easier testing of Zen 3 curve offsets




github.com





You can change the main test duration to 60 seconds for a quick test, then to 1200 seconds for a 6 hour overnight test.

The below is about six hours.

I got +30 on all cores except my best two at 19-23 with this test Cinebench R20 and R23 stable. Boost 200, Scaler 10, voltages on Motherboard setting.



Code:


$p95path="p95v304b9.win64.zip"; # path to p95 .zip you want to extract and use

# adjust the following to customize length of time to run
$core_loop_test=$true;    # Default=$true.  Basic test to loop around all cores.  Set to $falue to disable.
$loops=1;                 # Default=1. Number of times to loop around all cores.
$cycle_time=1200;          # Default=60.  Approx time in s to run on each core.
$cooldown=1;             # Default=1.  Time in s to cool down between testing each core.

$core_jumping_test=$true;      # Default=$true.  Test to move process from core to core.  Set to $falue to disable.
$core_jumping_loops=5;         # Default=5. Number of loops to run.
$core_jumping_cycle_time=120;   # Default=10.  Approx time in s to run on each core.

# adjust next two values to limit testing to a specific range of cores
$first_core=0;   # First core to test in each loop.  Default=0.  Any cores lower than this number will not be tested.
$last_core=31;   # Last core to test in each loop.  Any cores (that exist) higher than this number will not be tested.
                 # Will automaticlly get adjusted down to the actual number of detected cores.
                 # Default and MAX value=31.  Cores 32 or higher will result in an Error: "Arithmetic operation resulted in an overflow."

# additional settings
$stop_on_error=$false; # Default=$false.  $true will stop if an error is found, otherwise skip to the next core.
$timestep=1;           # Minimum time to run stress test.  Will check for errors every this many seconds.
$use_smt=$true;        # Default=$true.  $false will only enable one thread on each physical core even if SMT (Hyperthreading) is enabled on the system.

$fatal_error=$false;   # Default=$false.  Script sets this to true if there is an unrecoverable error.  Any subsequent tests will then be skipped.


----------



## Hale59

adversary said:


> ...
> What you exactly mean by tWTR & tRRD ? As I do not see that exact names anywhere in Zen timings list. Can you state exact name of timing you mention? I guess you refer to tWRRD, but I would not like to go adjust timings wrongly without proper understanding what you exactly mean.


tWTRS/tWTRL
tRRDS/tRRDL


----------



## shaolin95

Hello @Veii,
Any suggestions on how can I improve my latency? I understand 4x16GB is not as easy but maybe there is some hope 









Thank you!


----------



## Veii

KedarWolf said:


> For your Curve Optimzer overclock, try this.


someday i will
CO is broken on this bios
Can't do anything per core. It doesn't recognize my cores


----------



## Merutsu

Veii said:


> Quite honestly I would use the tool and permanently change it


how to do that? 
can't make it visible on msi b550m mortar + latest bios with agesa 1.2.0.1. On this board I can't even see the actual voltage, MSI HW monitor section in bios displays "N/A" for CPU VDDP.


----------



## H1N1-JohnyBoy

Here are my tonight findings, whea problem on my end came from HWINFO, no whea error if I don't monitor while doing y-cruncher no problemo
Meaning I might be fclk 2000+ stable but it also means I wasted so many nights testing for nothing because people said you had to monitor with hwinfo and even set a sound bip when whea error occurs hahaha ***, am a noob but this is incredible, only reason I tested without hwinfo is because I read on their forum that version 6.4.3 that I was previously using was producing whea error when using a 6000gpu and hwinfo, but they said they fixed it and update to version 7 I think so I did that, all my pc is up to date, so yeah I'm stupid also for not figuring it out or start using program and never had a need before
ALso means I can start testing with a lower vsoc, and so on, start from scratch loool

Hope it will help someone else
good luck all I'm out

some other monitoring program maybe could do this also, like zentiming I also shutdown that program for my latest test ,
so this is my recommendation, uninstall all that **** and just run y-crunsher and check event viewer yourself
peace I'm out


----------



## Br3ach

Okay, so I have tested (almost) all 0/X/X, 6/X/X and 7/X/X Rtt combinations are here are my results (4x SR DIMMs)
https://pastebin.com/hQ0KBXui
Difficult to draw any conclusions for now, except that X/1/X is really bad (which we knew). X/X/5 and X/X/6 seem to be the best here, but may also depend on the Rtt_Nom and Rtt_Wr... Then again, 7/2/5 would be seemingly worse than any other 7/2/X combination, so go figure... But Veii's recommended 6/3/6 do look like a good idea so far!

Edit: OK, I've tested these at 40 ClkDrvStr (even less stable), and here are the best performing combinations I've found (in that order): 6/3/7, 0/0/6, 0/3/5, 0/2/7, 0/0/5, 7/3/5, 6/0/4.


----------



## KedarWolf

H1N1-JohnyBoy said:


> Here are my tonight findings, whea problem on my end came from HWINFO, no whea error if I don't monitor while doing y-cruncher no problemo
> Meaning I might be fclk 2000+ stable but it also means I wasted so many nights testing for nothing because people said you had to monitor with hwinfo and even set a sound bip when whea error occurs hahaha ***, am a noob but this is incredible, only reason I tested without hwinfo is because I read on their forum that version 6.4.3 that I was previously using was producing whea error when using a 6000gpu and hwinfo, but they said they fixed it and update to version 7 I think so I did that, all my pc is up to date, so yeah I'm stupid also for not figuring it out or start using program and never had a need before
> ALso means I can start testing with a lower vsoc, and so on, start from scratch loool
> 
> Hope it will help someone else
> good luck all I'm out


What about just running OCCT Large Data Set with the Extreme preset?

A very effective way of producing and finding WHEA errors.


----------



## H1N1-JohnyBoy

KedarWolf said:


> What about just running OCCT Large Data Set with the Extreme preset?
> 
> A very effective way of producing and finding WHEA errors.


Yeah why not, but its only one hour right? If you want I can do it just want to finish y-crunsher first


----------



## H1N1-JohnyBoy

this is where I'm at, how long should I keep going (with hwinfo info I would already have had an error, never did a test so long )


----------



## H1N1-JohnyBoy

cpu reaching 90c without monitoring isnt fun, dont even want to run ryzen master, too risky lol


----------



## H1N1-JohnyBoy

KedarWolf said:


> What about just running OCCT Large Data Set with the Extreme preset?
> 
> A very effective way of producing and finding WHEA errors.


Sir you still there? If OCCT is using the same sort of monitoring as HWinfo it will produce whea if my theory is correct? And from my limited knowledge on the matter
my tonights finding should be ****ing praised , or at least some of you should be mad for wasting so much time, or be very happy little noob found the problem hehe
I was pissed when I announced my findings, still am so I hope I don't sound like a D


----------



## H1N1-JohnyBoy

any other program I could use without integrated monitoring stuff, to check fclk, like y-crunsher isn't enough? if day to day task no reboot, no crash, gaming no problem, ycrunsher, cinebench, all stress test no problem, but only situation I can produce whea is with the use of a monitoring software, you can draw your conclusions but unless I'm missing something which is tottaly possible because I didn't sleep, please enlighten me guys


----------



## KedarWolf

H1N1-JohnyBoy said:


> any other program I could use without integrated monitoring stuff, to check fclk, like y-crunsher isn't enough? if day to day task no reboot, no crash, gaming no problem, ycrunsher, cinebench, all stress test no problem, but only situation I can produce whea is with the use of a monitoring software, you can draw your conclusions but unless I'm missing something which is tottaly possible because I didn't sleep, please enlighten me guys


You can run things like Prime95 112 FFTs In Place AVX disabled or large FFTs AVX enabled to stress test memory, clear your log in Event Viewer and check for WHEA errors after an overnight run. If you want to check your Curve Optimiser overclock per core, try this. Clear event viewer first as well.









GitHub - jasonpoly/per-core-stability-test-script: Test script developed for for easier testing of Zen 3 curve offsets


Test script developed for for easier testing of Zen 3 curve offsets - GitHub - jasonpoly/per-core-stability-test-script: Test script developed for for easier testing of Zen 3 curve offsets




github.com


----------



## H1N1-JohnyBoy

KedarWolf said:


> You can run things like Prime95 112 FFTs In Place AVX disabled or large FFTs AVX enabled to stress test memory, clear your log in Event Viewer and check for WHEA errors after an overnight run. If you want to check your Curve Optimiser overclock per core, try this. Clear event viewer first as well.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - jasonpoly/per-core-stability-test-script: Test script developed for for easier testing of Zen 3 curve offsets
> 
> 
> Test script developed for for easier testing of Zen 3 curve offsets - GitHub - jasonpoly/per-core-stability-test-script: Test script developed for for easier testing of Zen 3 curve offsets
> 
> 
> 
> 
> github.com


OK thanks,
before stopping my ycrunsher test I decided to launch ryzen master and zentiming just to see if I could still use those and no, at least one of those creates the whea conflict as well, 
had like 40 whea soon after I opened them, it's so sick!!!


----------



## H1N1-JohnyBoy

OK so now I dropped my IOD from 1.06 to 0.980 and vscoc from 1.15v to 1.1v and so far so good eventhough it's still early to call it a victory I think it will hold, so happyyyy


----------



## H1N1-JohnyBoy

nope got whea this time gonna try with iod 1.02


----------



## Not a redditor

dram v 1.55 for stability

vsoc 1.1750 so i can have vcore of 1.3625
vddp 0925
0955
1105

dram ch_a and b 0.740

CAD BUS 6 3 3 
Phy enabled/enabled/ 8 bit

on a clean shutdown and restart or what ever combination of "pure' OS startup latency goes down to 61.3 from this point i can lower latency with CPU OC raising from 4.5/4.5 - 4.4/4.4 to what ever but i lose stability from CPU bcuz is bios limited, i booted 4.8 on the first ccx but cannot run CineBenchR20 single core, i could only run CBR20 with 4.7 
reminder this is 3950x.

any suggestions on improving latency from this point ? ( without a modified bios )


----------



## Not a redditor

forgot to change tRTP to 10 , 6 was from another config, was testing 6-8 with this config but only works 10 for stability


----------



## slayer6288

Hi @Veii i see u recommend 40mv stepping for ryzen 5000 cpus but on the spreadsheet u linked it doesnt look like many use it. I currently have a 5950x using vddp at .9v ccd/iod at .950v and soc at 1.0875v. I am stable in occt and daily use. Should i be worried i am not using 40mv stepping? I am using 3600/1800 ram/fclk. If I shouldnt be worried where does the 40mv stepping come in? extreme overclocks? thanks for helping a noob on ryzen


----------



## PJVol

H1N1-JohnyBoy said:


> nope got whea this time gonna try with iod 1.02


Its funny, but managed to "pass" aida memtest whea-free (event logger) with soc 1.160.
Didn't opened hwinfo64 yet (lol)









Unfortunately, that doesn't change the fact that something is really wrong. Here's the illustration

















Any other synthetic that proved to be memory intensive, show similar performance regression. GB5 for example, MT 9800 vs. 8000, and so on.
So the problem is still pending for me.

@Veii
Does it look like the L3 throttling you mentioned, or I screw up something as usual  ?


----------



## Veii

PJVol said:


> Its funny, but managed to "pass" aida memtest whea-free (event logger) with soc 1.160.
> Didn't opened hwinfo64 yet (lol)
> 
> View attachment 2482256
> 
> 
> Unfortunately, that doesn't change the fact that something is really wrong. Here's the illustration
> 
> View attachment 2482270
> View attachment 2482280
> 
> 
> Any other synthetic that proved to be memory intensive, show similar performance regression. GB5 for example, MT 9800 vs. 8000, and so on.
> So the problem is still pending for me.
> 
> @Veii
> Does it look like the L3 throttling you mentioned, or I screw up something as usual  ?


You did not screw up, it's the powerbudget where memOC eats into it
For me SOC takes 22+ watt and eats into the EDC Fuse limit
If you can take a look here


http://imgur.com/a/OWvfX7s

TM5 also was slower

You have a strong multi-core penalty with high SOC
At this point i consider to go an allcore and work with 1usmus PX boosting method
At least this prevents package throttle and the intentional Fuse limits

On stock the EDC limit is around 90, lifiting it up helped
But you still peak 120A. Where for the 5800X i think it was 140-150A
for the 5900 and 5950X both it's 200A ~ soo technically speaking, the 5900X could perform better than the 5950X
Simply by the preconfigured and non bypassable silicon Fuse limit 

But it is what it is
PBO is neat and all that, fMax limits are also annoying and all that
But as long as we can not bypass or override that FUSE limit ~ PBO2.0v3 or v4 wouldn't matter
Only an undervolting would matter to have "more powerbudget"
It's sad, but i think it is what it is atm

Only allcores bypass these "apparently non existant" EDC Hardlocks 😐

EDIT:
it was acceptable for gaming, where single core mattered
(while we have annoying artificial fMax boost limits here)
PBO was useful,but on very high FCLK OC - PBO starts to make no sense with the EDC Hardlock
Performance is slightly bellow stock while only boost is acceptable
Increasing IPC but degrading allcore performance ~ not a good trade at all
Soo CTR it is for now


----------



## _frame_

H1N1-JohnyBoy said:


> nope got whea this time gonna try with iod 1.02


Try to lower your cpu OC. Something like static 4400-4500 Mhz all core 1.3 V just to check for WHEA. I have some WHEA because of high OC (even with PBO +200) and not because of IF 2000 Mhz.


----------



## T[]RK

Veii said:


> Soo CTR it is for now


I ask in another thread (max overclocking voltage), but no respond about it. There is recommendation before use CTR to set VDDG CCD to 1.05-1.1V. Ain't it max limit for Vermeer? I mean, is it save? Or i may get results with high voltage and lower it later, what's the point then? Maybe use lower (like 940mv for VDDG CCD) right from start?


----------



## Veii

T[]RK said:


> I ask in another thread (max overclocking voltage), but no respond about it. There is recommendation before use CTR to set VDDG CCD to 1.05-1.1V. Ain't it max limit for Vermeer? I mean, is it save? Or i may get results with high voltage and lower it later, what's the point then? Maybe use lower (like 940mv for VDDG CCD) right from start?


I put in my current figured voltages out, changed loadline to 1 under flat @ 600khz switching freq (instead of 700) and the sample turned "gold" instead of silver @ 2100FCLK pre-set 








1usmus on it's own i hear recommends 900-1050-1100 as cLDO_VDDP- VDDG CCD - VDDG IOD
I think too that this is enough, although i had stability issues with VDDG CCD at 1050 and everything was fine at 1020 again

The limit, IF we are on 12nm (doubt at this point)
are 1050 CCD, 1150 IOD - before you start to have degrading issues
The thing is, 1120 IOD on my side already showed consistently worse results and AVX2 test crashes
Also CPU Throttling too ~ quite significant at 1-2ns loss and L1 to 1300 instead 1800

I do think my research here still applies








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




even on AGESA 1.2.0.0
But i seems like took the other path than just increasing VDDG higher
Still think both methods are fine , but haven't decided yet what ends up as the better one
Because i neither have Intel NIC, USB, ALC 1220 issues at any of these settings nor WHEA errrors
SOC high surely does no damage, i am very confident on that statement
VDDG CCD at 1050 is kind of borderline - it's fine but we have to see
IOD is less of an issue, as it's not the IMC which some are worried about
What really makes me worry, is people pushing 1020 cLDO_VDDP or bugs pushing 1050 :x
This then indeed is borderline high - "dancing on the rope of stability and instant frying on a PSU spike"
While 1050 still technically falls into the "allowed category for both cLDO_VDDP and VDDG CCD"
~ yet i am worried on both strongly.

But hey, OCCT extrerme and y-cruncher very well showed instability at such high CCD, soo i'm fine with it again @ 1020 
First found voltages 1-2 pages back @ 2067 FCLK where fine, but my current one at 2100 are 100% fine @ 860mV CPU VDDP
Working atm my testing on allcore and CTR PX boost mode ~ no issues neither with SOC voltage nor 2100 FCLK.. At least no EDC Package throttle anymore


----------



## Veii

I can't seen to find the post of the person who asked about Standby VDDP voltage
It's not this one, it's purely called VDDP
Maybe it was @craxton


Spoiler: Example picture














This is what i got as "example" how it writes itself and looks


----------



## H1N1-JohnyBoy

Veii said:


> I can't seen to find the post of the person who asked about Standby VDDP voltage
> It's not this one, it's purely called VDDP
> Maybe it was @craxton
> 
> 
> Spoiler: Example picture
> 
> 
> 
> 
> View attachment 2482329
> 
> 
> 
> This is what i got as "example" how it writes itself and looks


THx I think was me in pm 
So do you think I should install a modded bios for x570-e with access to this cpu vddp votage (will be using fclk 1866 for now)


----------



## H1N1-JohnyBoy

Also if anyone could help for my dual rank
Vdimm is 1.5v (can I go higher, what's the max safe for 24/7 couldnt find a trusty answer)
I get 1 error after testmem5 [email protected] with those settings









What would you guys change to make it stable?


----------



## Veii

H1N1-JohnyBoy said:


> THx I think was me in pm
> So do you think I should install a modded bios for x570-e with access to this cpu vddp votage (will be using fclk 1866 for now)


I see, that's why i couldn't find it 
Always install modded bioses , if it's proofen to work by at least one person
The modder would have found an issue and fixed it the best he could. 
Even if you might not notice the issue, if there was one asking that much work to do ~ it's always worth it


----------



## H1N1-JohnyBoy

Guess I will test it, been itching me to do it for a while now, just needed to hear the right words


----------



## H1N1-JohnyBoy

Wait, new bios is here


----------



## H1N1-JohnyBoy

With bios 3602 my l3 cache went from smth like 400 to 600 +-


----------



## Veii

H1N1-JohnyBoy said:


> With bios 3602 my l3 cache went from smth like 400 to 600 +-
> 
> View attachment 2482353
> View attachment 2482354


How high is your default EDC & TDC limit on this @ stock ?
If it is 140A how i think it is 
Test with 400A and lower TDC by 5A


----------



## Iarwa1N

Veii said:


> You did not screw up, it's the powerbudget where memOC eats into it
> For me SOC takes 22+ watt and eats into the EDC Fuse limit
> If you can take a look here
> 
> 
> http://imgur.com/a/OWvfX7s
> 
> TM5 also was slower
> 
> You have a strong multi-core penalty with high SOC
> At this point i consider to go an allcore and work with 1usmus PX boosting method
> At least this prevents package throttle and the intentional Fuse limits
> 
> On stock the EDC limit is around 90, lifiting it up helped
> But you still peak 120A. Where for the 5800X i think it was 140-150A
> for the 5900 and 5950X both it's 200A ~ soo technically speaking, the 5900X could perform better than the 5950X
> Simply by the preconfigured and non bypassable silicon Fuse limit
> 
> But it is what it is
> PBO is neat and all that, fMax limits are also annoying and all that
> But as long as we can not bypass or override that FUSE limit ~ PBO2.0v3 or v4 wouldn't matter
> Only an undervolting would matter to have "more powerbudget"
> It's sad, but i think it is what it is atm
> 
> Only allcores bypass these "apparently non existant" EDC Hardlocks 😐
> 
> EDIT:
> it was acceptable for gaming, where single core mattered
> (while we have annoying artificial fMax boost limits here)
> PBO was useful,but on very high FCLK OC - PBO starts to make no sense with the EDC Hardlock
> Performance is slightly bellow stock while only boost is acceptable
> Increasing IPC but degrading allcore performance ~ not a good trade at all
> Soo CTR it is for now


Are you getting that latency with PBO or fixed clock? If I use the same voltages as you for VSOC 1.2, CCD 1.02, IOD 1.1 and VDDP 0.86 on FCLK 2100, my latency dips huge even if I use it with undervolted PBO. I had to lower to CCD to 0.925 make the latency normal but this time I am barely getting the same latency I get with FCLK 2000.


----------



## T[]RK

Veii said:


> I put in my current figured voltages out, changed loadline to 1 under flat @ 600khz switching freq (instead of 700) and the sample turned "gold" instead of silver @ 2100FCLK pre-set


Hm... interesting. Worth to try i guess. I got "Golden sample" with stock setting on my motherboard (except that VDDG CCD=1,05V and VDDG IOD=1,05V). I was smart enough to enter lower recommended value instead of higher (1.1V). Thanks for respond!


----------



## Veii

T[]RK said:


> Hm... interesting. Worth to try i guess. I got "Golden sample" with stock setting on my motherboard (except that VDDG CCD=1,05V and VDDG IOD=1,05V). I was smart enough to enter lower recommended value instead of higher (1.1V). Thanks for resspond!


IOD can take it, they both average out at the end 
CCD and IOD

One of the reasons why i could pump SOC and let it decide on it's own what it wants
but ManniX's and mongoled suggestion works well so far
Heh, you can run CTR with 2100FCLK - no issues there 

CCD at 1050 was just unstable for me, 1040 worked but 1020 was better


----------



## PJVol

Veii said:


> You have a strong multi-core penalty with high SOC
> At this point i consider to go an allcore and work with 1usmus PX boosting method
> At least this prevents package throttle and the intentional Fuse limits
> 
> On stock the EDC limit is around 90, lifiting it up helped
> But you still peak 120A. Where for the 5800X i think it was 140-150A
> for the 5900 and 5950X both it's 200A ~ soo technically speaking, the 5900X could perform better than the 5950X
> Simply by the preconfigured and non bypassable silicon Fuse limit


Well, it will be fine if that was the case, but unfortunately, it's not. Today I've run several tests with my 5600x on a workplace PC. It has:

MSI mortar titanium b450 with 1.2.0.0 based bios. Luckily, SMU the same as on my Asrock extreme4, 56.44.0
2x8gb g.skill low bin b-dies (3200 CL15)
cheap air cooling - Gammax 300
Results were interesting, but a bit later about that, first, regarding my "home" PC:

1) I haven't ever been limited by EDC, since cooling is good enough for CPU to reach higher clocks within lower power budget, and typically max edc i've seen was ~ 105-110 amps. The only hard limit is 140w of power consumed from the socket.
2) with Asrock b550, at IF >1900, huge throttling occured in memory intensive benchmarks, such as dram calc's memory bench, where CPU obviosly was Max Freq. limited and all cores were sustained at 4850 effective clock. Edc max were 105 amps.
Other benches, that don't give a s**t for what ram speed is, such as CB R20/23, CPU-Z, give basically the same results, as with IF 1900. So edc limit doesn't prevent cpu from it either.
3) and finally, let's back to my 5600x - msi b450 tests:
the conclusion i've come to, after trying my cpu with other mobo, that current Asrock 1.2.0.0 bios is ** BIG PIECE OF S**T **.
Despite the ram used were quite low quality, compared to my HOF's, i managed to run it at 3933 and 4000 mt/s with CL16, and IF 1966 and 2000 respectively.
Benched in aida, dram calc's memtest, CB R20, cpu-z
and what do you think...
there were no a single f***ng WHEA error, neither in event log, nor in HWInfo64 sensor panel. Not a single one, ZERO, NADA...
And of course, I looked at the performance in dram calc bench and other mem-stressing apps
- there were nothing, that might indicate any throttling:
Dram calc easy preset - 109 sec. ( 150 on extreme4)
TM5 finished in ~ 11 min ( not 17 !!! )

Other test, such as CB, Cpu-z showed absolutely normal results, inline with what was expected from the hardware used.

So, I'm afraid, the verdict still, Asrock managed to mess up with their latest firmware.


----------



## Veii

@PJVol 
I have to say, MSI does cheat same as Gigabyte and asus all cheat on their own methods

But the interesting thing is ABL and the boosting table version
Something has to be different
Wait did you share an AMD PBS screenshot like this


----------



## PJVol

*@Veii*
May be, here it is, anyway









PS: CPU is just back home, and finally I personally got an idea of what 5600X on modest air cooling is capable of 
And have to say, that even with gammax 300, it still a quite a beast (if one to avoid edge OC)
One more thing:
msi didn't limit Boost Override in that Bios in PBO (1.2.0.0/56.44.0), but it seems Agesa did. So any value over 200 ignored.Of course, it'd be nice if someone here with Giga or Asus board prove me wrong.


----------



## Veii

PJVol said:


> *@Veii*
> May be, here it is, anyway
> View attachment 2482413
> 
> 
> PS: CPU is just back home, though I've got an idea, what 5600X on modest air cooling look like
> And have to say, that even with gammax 300, it still a quite a beast.
> One more thing, msi didn't limit Boost Override in its Bios in PBO, but it seems Agesa did. So any value over 200 ignored. Though it'd be nice if someone here with Giga or Asus board prove me wrong.


Thank you 
Now the question on the msi board becomes, what does "it" run
But this bios is identical to mine ~ you should have no issues up till 2133 FCLK

WHEA would logically mean , that IO is not correct
try to drop PCIe to gen 3, still X16 mode, disable data link saving feature in AMD PBS
and in AMD CBS -> NBIO , enable SRIS and AER Cap,(ACS enabled)

If you keep getting errors, it's purely related to the realtek nic
Because my and the X570 ITX which get no whea, both are on intel nic
other asrock boards and all the people who report them seem to be on realtek 2.5gbit


----------



## PJVol

Veii said:


> try to drop PCIe to gen 3, still X16 mode, disable data link saving feature in AMD PBS
> and in AMD CBS -> NBIO , enable SRIS and AER Cap,(ACS enabled)
> 
> If you keep getting errors, it's purely related to the realtek nic
> Because my and the X570 ITX which get no whea, both are on intel nic
> other asrock boards and all the people who report them seem to be on realtek 2.5gbit


Thanks!
PCIe gen 3 did nothing, tried before. Not sure about sris and aer, though the later seem enabled, but should doublecheck anyway.

The Realtek thing is very interesting, indeed. Just curious, is it possible to disable it just for science 
btw, MSI b450 mortar titanium has Realtek® RTL8111H-CG Gigabit onboard, and lack PCI-E gen 4.


----------



## Dasa

Just orderd 2x8 Patriot Viper 4400c19 to pair with two of my better 3200c14 sticks so hopefully the A1 and A0 PCB play nice together and get tRCD from 17 down to ~15.


----------



## PJVol

Veii said:


> try to drop PCIe to gen 3, still X16 mode, disable data link saving feature in AMD PBS
> and in AMD CBS -> NBIO , enable SRIS and AER Cap,(ACS enabled)


Nah...
Tried all that with no avail.
Disabling LAN in bios didn't help either. The one thing is thought to help is to look at agesa parts versions on msi.

PS: you know, what puzzles me most, is why such a sharp transition in that behavior occured. All rock stable under 1900, literally with random voltages and other params set. The oddities start at 1900+, as if they were programmed to appear when fclk crossed that borderline.


----------



## Veii

Dasa said:


> Just orderd 2x8 Patriot Viper 4400c19 to pair with two of my better 3200c14 sticks so hopefully the A1 and A0 PCB play nice together and get tRCD from 17 down to ~15.


Do NOT run RTT_PARK at /1 on them and don't exceed 1.48v without significant lowering of RTTs
I don't want to see another dead A0 set here 😪


----------



## PJVol

@Veii
Forgot to ask you, mate! Do you see it make sense to grab ram sticks from office PC (g.skill ripjaws 3200cl15) and try them on asrock PC, to exclude ram influencing factor?


----------



## GribblyStick

*edit* just realized I forgot to @ you, sorry***
@Veii
OK, I started from scratch on 12.0.0.1 on pretty low Voltages to see what that would get me and give me some room for improvement.

This is what I cam up with following the "regular" formulas and starting from the auto settings.
Meaning
VDIMM 1,5
CPU VDDP 0,855
CLDO VDDP 0,850
CCD 0,850
IOD 1,050
SOC 1,100



Spoiler: Regular formulas



tRAS= tCL + tRP
tRC= tRAS+tRC
tWR= tRAS - tRCD
tRTP= tWR/2
tRRDS as low as possible
tRRDL > tRRDS, set to 6 to stay even
tFAW= 4 x tRRDS
tWTRS as low as possible
tWTRL = tRRDL+2
tRFC = (5 * tRC) + 8
t..SCLI just left at 5
tCWL I left at 14
tRDWR= (tRCD / 2) +2
tWRRD= X * SCL so I set it the same as SCL
couldn't find any formula on the other RDRD/WRWR settings so I went with Veiis 1/5/5 .. 1/7/7
tcke= 9 with setup 3/3/15
proc ODT I just left as is
RTT set to 7/0/5
CADBUS changed to 40/20/20/20





Spoiler: Regular OC
























Spoiler: On GDM 1T















Could not get it to run at 1T GDM off with those voltages. Going to CL14 boots but gives a ton of error 6 in TM5.

Tried some alternative formulas, but I can't say that improved anything.


Spoiler: alternative formulas



tRAS= tRCD + tBL, assuming tBL is burst length / 2 which I understand is 8 on DDR4 so tBL would be 4
tFAW = RRDS
tWR= tRRDS + tWTRS
haven't tried tcke 1





Spoiler: alternate OC






















Although I bumped tFAW/RRDS a bit because the lowest my BIOS allows on tWR is 10, so I pushed tRRDS up to match tWTRS
Lowering tRFC further wouldn't really boot and got stuck on various qcodes.

4000/2000 still has WHEA errors and is super slow, haven't tried pushing past 3900, but I expect much the same.
Any suggestions on where to go next? be that CL14 or higher FLCK or optimizing timings/voltages.
The RAM sheets says they support CL10 but I haven't seen anybody do anything below 14 so I doubt that or 12 are an option


----------



## dgoc18

Memory 3800 CAS 14/1900 now working beautiful, I used Dram Calc 1.60.

In BIOS I set

SOC 1.125V

VDDG CCD 1.050

VDDG IOD 1.050

CLDO VDDP 0.950

DRAM 1.52V


----------



## Veii

dgoc18 said:


> Memory 3800 CAS 14/1900 now working beautiful, I used Dram Calc 1.60.
> 
> In BIOS I set
> 
> SOC 1.125V
> 
> VDDG CCD 1.050
> 
> VDDG IOD 1.050
> 
> CLDO VDDP 0.950
> 
> DRAM 1.52V
> View attachment 2482452


You messed up the order, tRCD_RD is to boost not tRCD_WR
and TM5 needs 20+ cycles to call stable, 6min is not a stability test
https://www.overclock.net/attachments/tm5-zip.341454/ pre-made config


PJVol said:


> @Veii
> Forgot to ask you, mate! Do you see it make sense to grab ram sticks from office PC (g.skill ripjaws 3200cl15) and try them on asrock PC, to exclude ram influencing factor?


I don't know 
up to your time, but WHEA seems to be reported for anything ~ except for memory


----------



## hazium233

Veii said:


> Do NOT run RTT_PARK at /1 on them and don't exceed 1.48v without significant lowering of RTTs
> I don't want to see another dead A0 set here 😪


This is down in ohms, not divisor? Like moving from RZQ/5 to RZQ/6. At least that is what I thought based on two SR.


----------



## drnilly007

So these settings are for Hynix MJR stock DOCP, no cpu overclock, ASUS just released a new bios for Dark Hero and says added memory stability. So I wanted to see if I could get the DOCP to work but still getting WHEA 19 errors.


----------



## Veii

hazium233 said:


> This is down in ohms, not divisor? Like moving from RZQ/5 to RZQ/6. At least that is what I thought based on two SR.


Lower in the sense of higher impedance (lower divider) caused more issues than with lower termination impedance


----------



## Redlurkeraite

Hey @Veii, if possible could you give any suggestions on how I could improve these timings?
I'm just getting error 0, however, by changing procodt and the cadbus timings i'm still unable to get rid of it.
1.63 vidimm


----------



## Br3ach

OK, here's the best I can do at tCL 14 (4x SR DIMMs). Sharing here and also submitted to the google sheet. Unfortunately, at 2000 IF I get very slight audio crackling, so my IF isn't fully stable. 

Maybe I'll give it another go when AGESA 1.2.0.2 comes out, but for now I've wasted enough hours on this ;-) Cheers guys, good luck!


----------



## Iarwa1N

PJVol said:


> *@Veii*
> May be, here it is, anyway
> View attachment 2482413
> 
> 
> PS: CPU is just back home, and finally I personally got an idea of what 5600X on modest air cooling is capable of
> And have to say, that even with gammax 300, it still a quite a beast (if one to avoid edge OC)
> One more thing:
> msi didn't limit Boost Override in that Bios in PBO (1.2.0.0/56.44.0), but it seems Agesa did. So any value over 200 ignored.Of course, it'd be nice if someone here with Giga or Asus board prove me wrong.


Same 200 Mhz PBO boost limit with Asus B550-F. I am hate this limit, I know some of my cores can do more than 4850 but limited by AMD for no reason at all.


----------



## Oberst

Veii said:


> I know they can do it, but you need to power them well in order to do it and your timings being perfect
> If tWRRD is off by 1, it won't post at all


Still testing on this 



Veii said:


> Variation for instablity on a clean OS
> (use WPD & Autoruns for Windows - Windows Sysinternals to disable win-cr*p)
> is 0.3ns = instability/autocorrection
> 0.1ns = run to run variance
> Always use the "start benchmark" button ~ never run them in categories, as it won't reach peak boost that way
> it needs the preparation phase to warm up


Tested, no high variation with procODT at 28, just the usual 0.1 ns.

In the mean time i got 15-15-15-15-30-258 @ 3800 stable at 1,44 vdimm. vSOC - 1,0750 (BIOS), CLDO VDDP - 0,880 / VDDG CCD - 0,930 / VDDG IOD - 0,980.
I had a strange no post issue with vSOC at 1,0850 during testing, the rest same exact settings. Also after BIOS reset and profile loading I get + 0,1000V for vcore offset instead of - 0,1000V offset as I'm usually running (PBO off, vcore auto).


----------



## craxton

Sorry @Veii been preparing my flight trip to Florida for the week, leaving north eastern Ky for vacation
(first time being there) ive not had a chance to try the bios, as im unsure if im just suppose to flash it
using msi flashback? or if i need the tools to flash it, and i asked quite some time back about VDDP voltage
unsure if we spoke about standby or not.

have not really done much of anything with overclocking at all this week due to this "trip"
if all i gotta do is flash it normally then ill try it now, and report back, if i need tools, list these tools again pls,
i have the downloads of rufus, and flashrom exe (FRZN zip) if those are all i need ill begin to reset the bios straight away and
begin testing.

(EDIT) <nevermind, found your instructions in my mentions, going thru it now >
(EDIT2) it would seem, FRZN rar after extraction process is completed, the exe doesnt run on my pc,
however when i tried to run flashrom thru elevated command process the steps mentioned doesnt work in post #4
from the page you linked a few pages back now.

im so lost about how to use this program? lol, do i need to use my cprom flasher for this to work????

EDIT# 3 i have a
*CH341A + SOIC8 Clip + 1.8V & SOIC8 Adapter*
so, after scratching my head a little, ive found this is needed in order to flash custom bios/mods? 
if so, then it will have to wait until i return. but the pic below is th CH341A flasher i have, read that USB type flashers are 
somewhat harder to use for bios flashing? however i did find the correct driver for this tool using google search, so i have
pretty much everything i need.

unless this tool isnt needed at all, and im over thinking this like i do with nearly everything....









also, MSI does allow past 200mhz auto oc, but no matter if i set 300mhz auto oc, amd doesnt allow.
i dont have any other boards and im unsure if im the proper one to test if it evolves instructions that are plainly written
rather than me needing gibberish...


----------



## drnilly007

What to do to relate the trfc settings between all three. Im working it down from a 1000+ trfc docp setting. My board doesnt auto fill like at the moment trfc is 800/ 2 is at 192/ 4 is at 132. From what ive researched is they should scale in a much different way.

The 2 and 4 setting are from the docp of trcp of 500 something but zentimings would report it at over 1000 so I tried 600 no go and working it down now.


----------



## dgoc18

Veii said:


> You messed up the order, tRCD_RD is to boost not tRCD_WR
> and TM5 needs 20+ cycles to call stable, 6min is not a stability test
> https://www.overclock.net/attachments/tm5-zip.341454/ pre-made config
> 
> @Veli,
> Thanks for link, sorry im noob you are right test mem is not stable, see attach pix and what do you mean"tRCD_RD is to boost not tRCD_WR”, what is your suggestion? Should I change it?


----------



## drnilly007

Can anyone look over these timings let me know if you see any deficieny or wrong calculations. Hynix MJR just fyi


----------



## drnilly007

These are the results with DOCP 2000IF and 4000mem speed but got tons of whea error 19 as a comparison.


----------



## _frame_

Can someone explain me this:
*y-cruncher* -more than 3 hours: no WHEA.
*Prime95* small FFT's - more than 1 hour 17 minutes: no WHEA.
*TM5 *20 cycles: no WHEA
*OCCT *large data set, extreme - 1 hour: 10 WHEAs
2000 Mhz 1:1:1. 5600X PBO +200 CO -10 all cores


----------



## _frame_

Veii said:


> WHEA would logically mean , that IO is not correct
> try to drop PCIe to gen 3, still X16 mode, disable data link saving feature in AMD PBS
> and in AMD CBS -> NBIO , enable SRIS and AER Cap,(ACS enabled)
> 
> If you keep getting errors, it's purely related to the realtek nic
> Because my and the X570 ITX which get no whea, both are on intel nic
> other asrock boards and all the people who report them seem to be on realtek 2.5gbit


Does not work for me. At least in OCCT.
Intel NIC.


----------



## mackbolan

Veii said:


> Please write with linebreaks
> This was painful to read. Books have linebreaks too
> 
> ASRock is not to blame for the FCLK issues
> It's an ongoing AMD issue, and only since recently they started to focus on 2000 FCLK
> Mostly thanks to our community and well me, for pushing 2133+ showing it is clearly possible
> But i got lucky too
> Most of the new boards don't even have SMU 56.30 at all , they start with Patch C which is 56.34 ~ which got a 1900FCLK hardcap
> My old one appeared to be without limits and the current one appeared to be without limits
> But on the negative side, curve optimizer is fully broken for my gimped dual CCD 5600X
> i have no access to anything per core ~ well and DF sleep states are broken
> 
> That's about the tribute i pay.
> Beyond 2000 is CPU bin dependent, while 2000 FCLK is bios dependent
> Some people got it finally working on AGESA 1.1.8.0, others still haven't without WHEA
> The only one which was fine , is a bios which doesn't really exist on most of the boards
> 
> Quite honestly , you can not do much
> nevertheless what board you pick - you will have the same bios issues everywhere else
> The brand doesn't matter and is only a part responsible. AGESA is equal everywhere
> I know the price of the board looks expensive , but you bought one of the lowest end X570's
> 150$ is the cost of the bare PCB and chipset alone if you go X570
> the rest is for VRMs
> and what i can read, it's about average to A520 boards, while often even lower end than many
> 
> It's just a low end board, X570 over 300 is decent, at least over 280$ - soo the money can actually be spend on ethernet and decent Mosfets and a decent PWM controller
> And even then, 1900FCLK is the norm on most boards you pick
> As it's not the boards fault
> For AMD 3800MT/s stable is already an achievement. 2133 was never ment to be
> 
> EDIT:
> I think this is about equal to a B350 Tomahawk with the mosfet capabilities 🤔


Well finally got the Asus TUF Gaming X570-PLUS (non-WIFI) flashed to Agesa 1.2.0.1, even put out extra for a Corsair 750D Airflow Edition with the hopes that once

and for this mess would be over. Sadly it's not. The thing will not post at 3800/1900 with ANY timing or voltage combo. So, for "science" I tried 4000/2000, other under

4000/2000 but over 1900 IF, with various timings and it goes into Windows no problems but still tosses 100's of WHEA 19's after 1866 IF. Now I have all the settings in

BIOS one could wish for and one's that do nothing and no change except the complexity is sky high with this board.

Here's a pic of Zen Timings and Aida Cache test, Agesa is not fixed, if anything worse. LLC means less stability at 3, better on auto. Can't run my all core OC of 4675

anymore, it crashes on Aida Memory Cache test at any CPU setting. On the AsRock it passed. Still stuck at 3733/1866 Cl 16 at 1.43v, PBO "enabled" but all at "auto",

max boost on 3 cores is 4650 default. I haven't tried higher than 4000/2000 given WHEA's at that setting. Why would higher work and how high? I also think my Aida Memory Cache results were better before this BIOS.

A nice thing is I have 2 x USB 2.0 headers so I can connect my Corsair pump internally and the board is thicker, so the cooler fits snug. On the AsRock if you took the

pump off the CPU bracket was loose, the plate is snug now. Temps are down a bit as well, possibly due to the better fit. Thoughts , feelings? Get a 5900X? Give up, sell this and go Intel?


----------



## mackbolan

Ok so I tried @craxton 's timings for 4000/2000 since he's got an Asus something close to this board. It worked and not. His timings work if I run in 2T and use the same voltages, CAD BUS settings in the post. I have similar RAM in 3733 by Team Group with Samsung B-die 2 X 8GB at 1.44v set to 4000 as per @craxton 's settings and a 5600X. 

I still get WHEA 19's but they come like 5 at a time in a 60 second time frame. It goes for a few hours it seems with none. This passes TM5, runs DRAM's test in 106 seconds, passes Aida and blasts through 3D mark Time Spy with decent score, 100 less than when I ran an all core 4675 but with PBO I'm getting 4750,so dunno why it's lower. Single core score is 610 vs. 640 on CPU-Z. 

Here's my Zen Timing, Aida results, and the error log.


----------



## Dasa

_frame_ said:


> Can someone explain me this:
> *y-cruncher* -more than 3 hours: no WHEA.
> *Prime95* small FFT's - more than 1 hour 17 minutes: no WHEA.
> *TM5 *20 cycles: no WHEA
> *OCCT *large data set, extreme - 1 hour: 10 WHEAs
> 2000 Mhz 1:1:1. 5600X PBO +200 CO -10 all cores


My guess is that if you ran prime95 blend or large ftt it would get WHEA as well since they often seem to be cache related.


----------



## judorange

Hi all,

First time RAM overclocker here.
So after unsuccessfully trying to get my IF to 2000Mhz with pretty much every voltage combinations possible, I gave up and settled on 3800 with 1:1.
I am still not done with the tightening :


Spoiler: ZenTimings















It just passed MemTest 1200%(and anta777 extreme1 for 8 cycles) so this is not a too bad foundation I hope.

I need to read some more on the topic of higher IF because I really found a wall and putting higher voltages(VSOC, VDDP, VDDGs) had pretty much no effect: I always got WHEA errors(corrected ones, but still).

BIOS: MSI B500 Tomahawk 7C91vA5 ComboAM4PIV2 1.2.0.0


----------



## _frame_

Dasa said:


> My guess is that if you ran prime95 blend or large ftt it would get WHEA as well since they often seem to be cache related.


Prime95 Large FFTs more than 1 hour: no WHEA.
And "Large" it is not heavy on cache, according to it's description it is heavy on memory controller and RAM. Small FFTs are heavy on cache.

*The point is, should we consider WHEA as a sign of instability? *if everything is running perfect, but WHEA could popup in some specific test. in my case it is only OCCT.


----------



## _frame_

Update, managed to pass OCCT - large - extreme without WHEA by rising CLDO VDDP from 0.91 to 0.97 V
Update №2: PCIE x16 was in GEN3 mode (on yesterday's screenshots as well). As soon as I switch back to "Auto", WHEA started all over again.


----------



## judorange

_frame_ said:


> Prime95 Large FFTs more than 1 hour: no WHEA.
> And "Large" it is not heavy on cache, according to it's description it is heavy on memory controller and RAM. Small FFTs are heavy on cache.
> 
> *The point is, should we consider WHEA as a sign of instability? *if everything is running perfect, but WHEA could popup in some specific test. in my case it is only OCCT.


When you say no WHEA are you talking about BSOD(=unrecoverable) or logged(=corrected) ones?
Because you may be spammed with WHEA errors at IF 2000MHz even you do not have BSODs.
See this for details.

Have you ever gotten it 100% stable at < 2000 before without any WHEA, and without perf regression?
If not you should start at 3600/3800, then tighten the timings, and then move to 2000 if your silicon, motherboard and bios allow it.


----------



## _frame_

judorange said:


> When you say no WHEA are you talking about BSOD(=unrecoverable) or logged(=corrected) ones?
> Because you may be spammed with WHEA errors at IF 2000MHz even you do not have BSODs.
> See this for details.
> 
> Have you ever gotten it 100% stable at < 2000 before without any WHEA, and without perf regression?
> If not you should start at 3600/3800, then tighten the timings, and then move to 2000 if your silicon, motherboard and bios allow it.


I guess it is "logged" WHEA. Do not have actual BSOD.
There is no performance regression considering I'm using only 1.4 vdimm and have not tried something like 3800 Mhz 14-14-14 which will require at least 1.5 vdimm. On the same timings 2000 is faster than 1900.
But, I have bios profile with exactly same settings and at the same time slower performance than my current one. 3 ns difference in AIDA latency. I made it by resetting bios to default and entering all settings manually. My current profile were made on previous bioses. Trying to figure out what is going on...


----------



## judorange

_frame_ said:


> I guess it is "logged" WHEA. Do not have actual BSOD.
> There is no performance regression considering I'm using only 1.4 vdimm and have not tried something like 3800 Mhz 14-14-14 which will require at least 1.5 vdimm. On the same timings 2000 is faster than 1900.
> But, I have bios profile with exactly same settings and at the same time slower performance than my current one. 3 ns difference in AIDA latency. I made it by resetting bios to default and entering all settings manually. My current profile were made on previous bioses. Trying to figure out what is going on...


Sure, but with that many WHEA I would not stay on 2000.
And realistically with tight 2000 vs tight 3800 you would only loose bandwidth. Which you should not affect anything in your day to day, only benchmarks.

Maybe you have the same problem as I have: no way to go beyond 1900 IF.
If a new agesa fixes this, I will try; else I will just learn to live with my measly DDR4 3800 cl16(or 14?).


----------



## _frame_

judorange said:


> Sure, but with that many WHEA I would not stay on 2000.


Again, I have WHEA during only 1 single test: OCCT. And only if PCIEx16 is set to auto or gen4. I do not have such "errors" during other tests or games.
I do not care about WHEA any more. What is the reason, if my system is stable and fast?


----------



## judorange

_frame_ said:


> Again, I have WHEA during only 1 single test: OCCT. And only if PCIEx16 is set to auto or gen4. I do not have such "errors" during other tests or games.
> I do not care about WHEA any more. What is the reason, if my system is stable and fast?


WHEA means it is not stable, period. The error was corrected, but there was an error.
Your screenshot shows quite a bunch of WHEA from the Event Viewer on at least 2 days; are you sure it was only during OCCT?
OCCT shows them by default, but it does *not *mean they do not happen during other tests, only that they are hidden.

Are you sure it is fast? Compare your AIDA64 with this(make a copy, and then you can filter by frequency, or anything else).
Is it stable run-to-run?
[note that the link states _"no whea_" highlighted in red next to _"Please provide proof of stability"_]


----------



## _frame_

judorange said:


> Your screenshot shows quite a bunch of WHEA from the Event Viewer on at least 2 days; are you sure it was only during OCCT?


Yes, I'm sure. Have you read my yesterday's post on a previous page? Looks like no.


judorange said:


> Are you sure it is fast? Compare your AIDA64 with this(make a copy, and then you can filter by frequency, or anything else).
> Is it stable run-to-run?


52.1 ns is it fast? For 1.4 vdimm it is fast enough I guess.
Yes, TFaw is wrong. I changed it to 20.


----------



## mackbolan

All this WHEA 19 stuff might be some Windows Update issue or Agesa still isn't right. When is it ever? I tried @craxton 's settings because we both have TeamGroup RAM with B-die and I get no errors just doing normal things and note I do need to leave it at 2T or it spams all kinds of WHEA. If I run any RAM test it shows no error but pops about 1-5 WHEA 19's not consistent, and it otherwise passes. No BSOD's or data loss, yet... I noticed putting my LLC at 4 so the SOC stays at 1.20, made a huge reduction in the number of WHEA's, always 19. 

I'm running my 5600X at PBO +100, Motherboard, LLC 4, which gives me 4750 boost and 81c CB23 temps. I tried to get this to run an all core of 4675 at 1.275 but that didn't work out on this board. I might go for it again now that I got the LLC to where it holds within .001 of a mv or V where I set any voltage. All core at 4675-4700 I was having temps at 77c CB23 or Time Spy on my former AsRock board. This Asus is trickier but at least has LLC.

Also, no Time Spy WHEA's at all. These happen only if I run a RAM test. Passes HCi to 600%, so dunno what the deal is. Say it's "unstable" but like if there's zero operational defect visually showing, no BSOD's or hangs, this could possibly be a "unicorn" of an error that we'll chase until software or Agesa fixes the issue. 6K + posts mostly regarding how to hit 4000/2000 or 3800/1900 ( I can't even boot that one speed), something is missing here and it's not silicon or board specific as @Veii has said before. 

I'm typing this at 4000/2000 and getting zero WHEA's. Ran this last night for hours with no WHEA's. Run a RAM test and it passes but a few WHEA's and not a lot. 1-5 at most. It's random weirdness. How many setting can one mess with and find the only truly non-WHEA causing RAM/IF is really 3600/1800 on the 5600X anyway. I can be what one is calling "stable" at 3733/1866, no WHEA but it still pops up once every few days or I'll get crackly audio. So far, not happening at this speed or at 3600/1800. 

I'm going to try a few games to see how this behaves. Because "real world" use is the best bench test. I'm not trying to run a mega corporation or server that has zero fault tolerance or win the right to be on the spreadsheet. How many are on that with all the drivers and programs you normally use daily, loaded and most Windows services on, coming up with "no WHEA"? It doesn't seem plausible given the number of us with WHEA 19's and we have all the regular stuff we use installed. Maybe if I gut the OS to bare minimum and only have OCCT, Prime 95, and just the chipset driver installed I'd be WHEA free? 

The alternative is that AMD has built CPU's that are mostly defective or just falsely advertised to be able to hit even 3800/1900. Because my particular RAM has no barrier to that speed, the board does for whatever reason or the CPU memory controller does. That means the 10 or so on this forum that actually can run truly at 4000/2000 or 3800/1900 have good CPU's and the rest of us struggling have crappy CPU's. Making AMD's defect rate about 90% for the 5600X and about 70% for any other CPU higher. Right now one hour and no WHEA. I'm thinking these RAM testers are causing more WHEA than anything. Pre-boot 600% HCi passes? Only happens when I run a test? 

Sure some settings matter a lot, like SOC voltage, timings, but there comes a point where I think something in the OS is triggering the error, erroneously. Running the Asus TUF Gaming X570-PLUS (no Wi-Fi) with BIOS 3602 Agesa 1.2.0.1

I know, I'm a "heretic" for questioning the logic and results behind these tests. However, they are all made pre-Ryzen 3 and those that updated might have a "bug" tripping this error more than normal. IMHO


----------



## PJVol

Anyone, who believe he has running IF 2000 stable and just a couple of whea's here and there do not affect the performance overall, can you run DRAM Calculator Membench easy preset and confirm that the result is as expected, i.e. elapsed time is at least no more than with IF1900.
If it were so on my ASRock setup, I personally would consider it stable.


----------



## _frame_

PJVol said:


> Anyone, who believe he has running IF 2000 stable and just a couple of whea's here and there do not affect the performance overall, can you run DRAM Calculator Membench easy preset and confirm that the result is as expected, i.e. elapsed time is at least no more than with IF1900.
> If it were so on my ASRock setup, I personally would consider it stable.


Did not expect so much difference, but it is 5% in favor of 2000 Mhz.


----------



## hyroglyphixs

I was hoping you guys could help me out. I've spent all day yesterday and today trying to get my 2x16gb Dual Rank B-die stable with somewhat loose timings to no avail. I think I'm on the verge of stability (both 1 hour OCCT test passed) but TM5 Extreme1 will give an error during cycle 2.

This is what I tested earlier:


http://imgur.com/LHsiIdJ


And this is what I'm testing now:


http://imgur.com/lRCZsZT


By all accounts B die (especially on this mobo) should have no problems getting to 3800+ (tons of errors with that yesterday), let alone at 3600..


----------



## ManniX-ITA

hyroglyphixs said:


> By all accounts B die (especially on this mobo) should have no problems getting to 3800+ (tons of errors with that yesterday), let alone at 3600..


I'm slowly working on a 6/3/3 profile to get tFAWx1.
So far this one works really well.
VDIMM is 1.52 in BIOS and VTT 0.735.

CCD is up to your sample, I would keep it at least at 1000.
IOD at least 1020, have to keep mine at 1080 to avoid USB issues with an external SSD.










And DIGITALL Power settings:


Spoiler















VRM settings are mostly needed for PBO and CO but they could affect RAM stability if Auto settings are not doing a good job.


----------



## hyroglyphixs

ManniX-ITA said:


> VRM settings are mostly needed for PBO and CO but they could affect RAM stability if Auto settings are not doing a good job.


Thanks for the reply, do you think it's worth it going for your tune? I'm on the verge of stability with my 3600 tune right now.


----------



## ManniX-ITA

hyroglyphixs said:


> Thanks for the reply, do you think it's worth it going for your tune? I'm on the verge of stability with my 3600 tune right now.


Run AIDA64 and save your profile when it's stable.
Then tune my settings and compare it.

You need to test at least 1h30m with TM5 1usmus config, 12 cycles, to really be sure it's stable.
Better if 25 cycles, it's more than 3 hours.

I think you'll have a hard time getting tRCDRD working at 15 even with GDM on and at 3600.
I could barely get it stable at 3800 and only loosening a lot of tertiary timings.
At the end it was a loss; if you can't get it stable try to set it at 16.


----------



## hyroglyphixs

ManniX-ITA said:


> Run AIDA64 and save your profile when it's stable.
> Then tune my settings and compare it.
> 
> You need to test at least 1h30m with TM5 1usmus config, 12 cycles, to really be sure it's stable.
> Better if 25 cycles, it's more than 3 hours.
> 
> I think you'll have a hard time getting tRCDRD working at 15 even with GDM on and at 3600.
> I could barely get it stable at 3800 and only loosening a lot of tertiary timings.
> At the end it was a loss; if you can't get it stable try to set it at 16.


Gotcha, thanks! I'll try tRCDRD at 16 if I get another error. tRCDWR doesn't have to match that though right? I'll try setting it to 8 like what you have..


----------



## mackbolan

PJVol said:


> Anyone, who believe he has running IF 2000 stable and just a couple of whea's here and there do not affect the performance overall, can you run DRAM Calculator Membench easy preset and confirm that the result is as expected, i.e. elapsed time is at least no more than with IF1900.
> If it were so on my ASRock setup, I personally would consider it stable.


In game it produces tons of error 19's but otherwise runs fine. I can't boot to 3800/1900, I can boot to 3600/1800 no issues, 3733/1866 occasional issues but most stable, 3933/1966, 4000/2000, all using Cl 16 timings and common sub-timings staying at 1.44v DRAM. I get zero memory errors via tests, only in Event Viewer at 4000/2000 or any speed than max 3733/1866. Here's a pic


----------



## PJVol

Thanks to all responded

Gonna try my HOF's with 5600X on a MSI board tomorrow at office. Something doesn't add up up with my Asrock platform atm.


----------



## ManniX-ITA

hyroglyphixs said:


> Gotcha, thanks! I'll try tRCDRD at 16 if I get another error. tRCDWR doesn't have to match that though right? I'll try setting it to 8 like what you have..


You can set it half tRCDRD or like tCL.
The rule is tRCDWR should be higher or equal than SCL*tWRRD.
Which I break with my profile currently; seems working fine but I'm looking for a better config.
So far anything with SCL higher than 2 is slower.


----------



## domdtxdissar

Like i wrote in a other thread some days ago, i have changed back to Agesa 1.1.8.0 because both boost clocks and latencies are better on older bios without training wheels.








ASUS ROG X570 Crosshair VIII Overclocking &amp...


Has anyone got any deep experience with tRFC2/tRFC4? Keep seeing the rule that: tRFC2 = tRFC / 1.346 tRFC4 = tRFC2 / 1.625 But I can push tRFC2 = tRFC / 1.415 (with an improvement in performance over tRFC2 = tRFC / 1.346) and tRFC4 seems to be ignored (can set it to the minimum 60 or as high...




www.overclock.net





After spending a few days finetuning i have now found my new 24/7 memory settings which iam pretty happy with, considering i'm running 4x8GB sticks and my 5950x wont run WHEA-free above 1900/3800 

Included some numbers for MLC for those interested.
(have to say its much easier to get low latency with single CCD CPU like 5600x or 5800x)









Both CCD's enabled:









Stability testing in my bloaty windows install (lost 0.2ns compared to safemode)
Could have run 50 cycles or more with 1usmus cfg as these settings are 24/7 safe settings and dont fail








No WHEA-errors on any of the runs.
Think this is also the fastest L3 latency i have seen, all thanks to the much better singlecore boosting in agesa 1.1.8.0

@Veii
Do you have any suggestions in regards to timings or should i be happy with this at 1900:3800 ?
tcke 9 + 3-3-15 is no bueno, no matter what drvstr i try. (unsable)


----------



## hyroglyphixs

ManniX-ITA said:


> You can set it half tRCDRD or like tCL.
> The rule is tRCDWR should be higher or equal than SCL*tWRRD.
> Which I break with my profile currently; seems working fine but I'm looking for a better config.
> So far anything with SCL higher than 2 is slower.












Ugh, still getting errors, any ideas on what to tune?


----------



## ManniX-ITA

hyroglyphixs said:


> Ugh, still getting errors, any ideas on what to tune?


Would definitely try lower ProcODT, 43 Ohm is very high for the Unify-X.
Wouldn't go either below VSOC 1.1V.
If you run 1usmus config in TM5 you can also get some hints about the errors.


----------



## hyroglyphixs

ManniX-ITA said:


> Would definitely try lower ProcODT, 43 Ohm is very high for the Unify-X.
> Wouldn't go either below VSOC 1.1V.
> If you run 1usmus config in TM5 you can also get some hints about the errors.


I'll try that, thanks a lot for the help!


----------



## hyroglyphixs

XMP is looking more bearable by the minute, haha. I'll try chaging tRAS to 34 since it's breaking the tRAS = tCL + tRCD(RD) + 2 rule..


----------



## ManniX-ITA

hyroglyphixs said:


> XMP is looking more bearable by the minute, haha. I'll try chaging tRAS to 34 since it's breaking the tRAS = tCL + tRCD(RD) + 2 rule..


Shouldn't be a problem with B-die.
Main culprit for both errors 12 and 13 is lack of voltage; 1.48V is probably not enough for CL14.
I know it's not for my kit; I need at least 1.50V, tighter timings and lower tRFC as above profile needs 1.52V.


----------



## hyroglyphixs

ManniX-ITA said:


> Shouldn't be a problem with B-die.
> Main culprit for both errors 12 and 13 is lack of voltage; 1.48V is probably not enough for CL14.
> I know it's not for my kit; I need at least 1.50V, tighter timings and lower tRFC as above profile needs 1.52V.


I'll try higher voltage then, thanks again for the help


----------



## ManniX-ITA

hyroglyphixs said:


> I'll try higher voltage then, thanks again for the help


Use this as a reference for TM5 errors:









Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com


----------



## hyroglyphixs

ManniX-ITA said:


> Use this as a reference for TM5 errors:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com


Good info, thanks! Pretty much got an immediate Error 2 which means a problem with voltage or resistance somewhere?


----------



## ManniX-ITA

hyroglyphixs said:


> Good info, thanks! Pretty much got an immediate Error 2 which means a problem with voltage or resistance somewhere?


Did it happen when you raised the voltage?
Then yes you need different settings for the bus.
Try lowering ProcODT.
Or use different DrvStr, all 24 Ohm is not optimal; try 40-20-24-20.

But at this point maybe it's time to test 36.9 - 6-3-3 - 40-20-20-20 - 3-3-15


----------



## hyroglyphixs

ManniX-ITA said:


> Did it happen when you raised the voltage?
> Then yes you need different settings for the bus.
> Try lowering ProcODT.
> Or use different DrvStr, all 24 Ohm is not optimal; try 40-20-24-20.
> 
> But at this point maybe it's time to test 36.9 - 6-3-3 - 40-20-20-20 - 3-3-15


Yeah, raised the voltage. I'll try those new settings now. Should I also be changing the Digitall power settings like your previous post?


----------



## ManniX-ITA

hyroglyphixs said:


> Yeah, raised the voltage. I'll try those new settings now. Should I also be changing the Digitall power settings like your previous post?


If you keep struggling with stability, that's what I use.
But they are needed to get tight PBO and CO overclocking reliable, not sure how much they help memory OC.
Never really tested just memory OC with all in Auto.


----------



## hyroglyphixs

ManniX-ITA said:


> If you keep struggling with stability, that's what I use.


Just a follow up question: 36.9 - 6-3-3 - 40-20-20-20 - 3-3-15 

Is the 6-3-3 referring to the Rtt's? So RZQ/6, RZQ/3, RZQ/3?

And the 3-3-15 referring to the 3 "setups"?

Thanks again


----------



## ManniX-ITA

hyroglyphixs said:


> Just a follow up question: 36.9 - 6-3-3 - 40-20-20-20 - 3-3-15


Yes check the Zentimings that I've posted, you can try to use those settings for the bus with your timings.


----------



## hyroglyphixs

Cad bus incorrect? I wonder if my sticks are getting hot.. I took my front panel off for more airflow though.


----------



## ManniX-ITA

hyroglyphixs said:


> Cad bus incorrect? I wonder if my sticks are getting hot.. I took my front panel off for more airflow though.


So quickly too high is unlikely.
Could be the timings; try an higher SCL at 3 or 4 or the bus.
tCKE may need to be adjusted; 1 is fine for my settings, maybe you need something different, test 6 / 9 / 16 / 24.


----------



## hyroglyphixs

ManniX-ITA said:


> So quickly too high is unlikely.
> Could be the timings; try an higher SCL at 3 or 4 or the bus.
> tCKE may need to be adjusted; 1 is fine for my settings, maybe you need something different, test 6 / 9 / 16 / 24.












I think I'll go back to XMP for now, spending too much time on this. I'll circle back around to this after the weekend 

Thanks for the help!


----------



## GribblyStick

@Veii 
Last post attached as quote since it's been a few pages by now.
But regarding variances, I tried running AIDA on safe mode to see if that makes a difference and it did.
So much so that I have to wonder if this is expected? This is the same 1T GDM: ON settings as in the quote below, but there is a drop of 3-4 ns.
And on top of that, the variance is now less than 0,3ns, down from 1-2 ns. Just from booting in safe mode? That seems like a lot.



Spoiler: 1T GDM on, safe mode



















GribblyStick said:


> *edit* just realized I forgot to @ you, sorry***
> @Veii
> OK, I started from scratch on 12.0.0.1 on pretty low Voltages to see what that would get me and give me some room for improvement.
> 
> This is what I cam up with following the "regular" formulas and starting from the auto settings.
> Meaning
> VDIMM 1,5
> CPU VDDP 0,855
> CLDO VDDP 0,850
> CCD 0,850
> IOD 1,050
> SOC 1,100
> 
> 
> 
> Spoiler: Regular formulas
> 
> 
> 
> tRAS= tCL + tRP
> tRC= tRAS+tRC
> tWR= tRAS - tRCD
> tRTP= tWR/2
> tRRDS as low as possible
> tRRDL > tRRDS, set to 6 to stay even
> tFAW= 4 x tRRDS
> tWTRS as low as possible
> tWTRL = tRRDL+2
> tRFC = (5 * tRC) + 8
> t..SCLI just left at 5
> tCWL I left at 14
> tRDWR= (tRCD / 2) +2
> tWRRD= X * SCL so I set it the same as SCL
> couldn't find any formula on the other RDRD/WRWR settings so I went with Veiis 1/5/5 .. 1/7/7
> tcke= 9 with setup 3/3/15
> proc ODT I just left as is
> RTT set to 7/0/5
> CADBUS changed to 40/20/20/20
> 
> 
> 
> 
> 
> Spoiler: Regular OC
> 
> 
> 
> 
> View attachment 2482437
> View attachment 2482435
> 
> 
> 
> 
> 
> 
> Spoiler: On GDM 1T
> 
> 
> 
> 
> View attachment 2482436
> 
> 
> 
> 
> Could not get it to run at 1T GDM off with those voltages. Going to CL14 boots but gives a ton of error 6 in TM5.
> 
> Tried some alternative formulas, but I can't say that improved anything.
> 
> 
> Spoiler: alternative formulas
> 
> 
> 
> tRAS= tRCD + tBL, assuming tBL is burst length / 2 which I understand is 8 on DDR4 so tBL would be 4
> tFAW = RRDS
> tWR= tRRDS + tWTRS
> haven't tried tcke 1
> 
> 
> 
> 
> 
> Spoiler: alternate OC
> 
> 
> 
> 
> View attachment 2482438
> View attachment 2482439
> 
> 
> 
> 
> Although I bumped tFAW/RRDS a bit because the lowest my BIOS allows on tWR is 10, so I pushed tRRDS up to match tWTRS
> Lowering tRFC further wouldn't really boot and got stuck on various qcodes.
> 
> 4000/2000 still has WHEA errors and is super slow, haven't tried pushing past 3900, but I expect much the same.
> Any suggestions on where to go next? be that CL14 or higher FLCK or optimizing timings/voltages.
> The RAM sheets says they support CL10 but I haven't seen anybody do anything below 14 so I doubt that or 12 are an option


----------



## craxton

mackbolan said:


> All this WHEA 19 stuff might be some Windows Update issue or Agesa still isn't right. When is it ever? I tried @craxton 's settings because we both have TeamGroup RAM with B-die and I get no errors just doing normal things and note I do need to leave it at 2T or it spams all kinds of WHEA. If I run any RAM test it shows no error but pops about 1-5 WHEA 19's not consistent, and it otherwise passes. No BSOD's or data loss, yet... I noticed putting my LLC at 4 so the SOC stays at 1.20, made a huge reduction in the number of WHEA's, always 19.
> 
> I'm running my 5600X at PBO +100, Motherboard, LLC 4, which gives me 4750 boost and 81c CB23 temps. I tried to get this to run an all core of 4675 at 1.275 but that didn't work out on this board. I might go for it again now that I got the LLC to where it holds within .001 of a mv or V where I set any voltage. All core at 4675-4700 I was having temps at 77c CB23 or Time Spy on my former AsRock board. This Asus is trickier but at least has LLC.
> 
> Also, no Time Spy WHEA's at all. These happen only if I run a RAM test. Passes HCi to 600%, so dunno what the deal is. Say it's "unstable" but like if there's zero operational defect visually showing, no BSOD's or hangs, this could possibly be a "unicorn" of an error that we'll chase until software or Agesa fixes the issue. 6K + posts mostly regarding how to hit 4000/2000 or 3800/1900 ( I can't even boot that one speed), something is missing here and it's not silicon or board specific as @Veii has said before.
> 
> I'm typing this at 4000/2000 and getting zero WHEA's. Ran this last night for hours with no WHEA's. Run a RAM test and it passes but a few WHEA's and not a lot. 1-5 at most. It's random weirdness. How many setting can one mess with and find the only truly non-WHEA causing RAM/IF is really 3600/1800 on the 5600X anyway. I can be what one is calling "stable" at 3733/1866, no WHEA but it still pops up once every few days or I'll get crackly audio. So far, not happening at this speed or at 3600/1800.
> 
> I'm going to try a few games to see how this behaves. Because "real world" use is the best bench test. I'm not trying to run a mega corporation or server that has zero fault tolerance or win the right to be on the spreadsheet. How many are on that with all the drivers and programs you normally use daily, loaded and most Windows services on, coming up with "no WHEA"? It doesn't seem plausible given the number of us with WHEA 19's and we have all the regular stuff we use installed. Maybe if I gut the OS to bare minimum and only have OCCT, Prime 95, and just the chipset driver installed I'd be WHEA free?
> 
> The alternative is that AMD has built CPU's that are mostly defective or just falsely advertised to be able to hit even 3800/1900. Because my particular RAM has no barrier to that speed, the board does for whatever reason or the CPU memory controller does. That means the 10 or so on this forum that actually can run truly at 4000/2000 or 3800/1900 have good CPU's and the rest of us struggling have crappy CPU's. Making AMD's defect rate about 90% for the 5600X and about 70% for any other CPU higher. Right now one hour and no WHEA. I'm thinking these RAM testers are causing more WHEA than anything. Pre-boot 600% HCi passes? Only happens when I run a test?
> 
> Sure some settings matter a lot, like SOC voltage, timings, but there comes a point where I think something in the OS is triggering the error, erroneously. Running the Asus TUF Gaming X570-PLUS (no Wi-Fi) with BIOS 3602 Agesa 1.2.0.1
> 
> I know, I'm a "heretic" for questioning the logic and results behind these tests. However, they are all made pre-Ryzen 3 and those that updated might have a "bug" tripping this error more than normal. IMHO


I've gotta MSI MPG B550 Gaming edge wifi board. But the values should still work, if running four sticks, at 2t command rate. 

The voltages I used is pretty common for the most part minus my ram voltage being lower then most claim stable. For some reason I can run at 1.46 in bios, currently running 1.47,get 1.48 llc3 north bridge. 

If error 19 is audio crackle or usb drop out, then that's not really ram doing this, it's agesa. Supposedly amd is releasing 1.2.2 I think in April for most boards in beta bios, to check if the issue with audio crackling, usb dropout, pci4 issues etc are going away. 

Maybe they think it's 2000fclk? Hope not, considering I'm whea free. Have been for sometime.


----------



## craxton

PJVol said:


> Anyone, who believe he has running IF 2000 stable and just a couple of whea's here and there do not affect the performance overall, can you run DRAM Calculator Membench easy preset and confirm that the result is as expected, i.e. elapsed time is at least no more than with IF1900.
> If it were so on my ASRock setup, I personally would consider it stable.


I'll test for ya on my board running 2000fclk "claimed whea free and stable daily" when I get home shortly. Using the phone atm.


----------



## craxton

mackbolan said:


> All this WHEA 19 stuff might be some Windows Update issue or Agesa still isn't right. When is it ever? I tried @craxton 's settings because we both have TeamGroup RAM with B-die and I get no errors just doing normal things and note I do need to leave it at 2T or it spams all kinds of WHEA. If I run any RAM test it shows no error but pops about 1-5 WHEA 19's not consistent, and it otherwise passes. No BSOD's or data loss, yet... I noticed putting my LLC at 4 so the SOC stays at 1.20, made a huge reduction in the number of WHEA's, always 19.
> 
> I'm running my 5600X at PBO +100, Motherboard, LLC 4, which gives me 4750 boost and 81c CB23 temps. I tried to get this to run an all core of 4675 at 1.275 but that didn't work out on this board. I might go for it again now that I got the LLC to where it holds within .001 of a mv or V where I set any voltage. All core at 4675-4700 I was having temps at 77c CB23 or Time Spy on my former AsRock board. This Asus is trickier but at least has LLC.
> 
> Also, no Time Spy WHEA's at all. These happen only if I run a RAM test. Passes HCi to 600%, so dunno what the deal is. Say it's "unstable" but like if there's zero operational defect visually showing, no BSOD's or hangs, this could possibly be a "unicorn" of an error that we'll chase until software or Agesa fixes the issue. 6K + posts mostly regarding how to hit 4000/2000 or 3800/1900 ( I can't even boot that one speed), something is missing here and it's not silicon or board specific as @Veii has said before.
> 
> I'm typing this at 4000/2000 and getting zero WHEA's. Ran this last night for hours with no WHEA's. Run a RAM test and it passes but a few WHEA's and not a lot. 1-5 at most. It's random weirdness. How many setting can one mess with and find the only truly non-WHEA causing RAM/IF is really 3600/1800 on the 5600X anyway. I can be what one is calling "stable" at 3733/1866, no WHEA but it still pops up once every few days or I'll get crackly audio. So far, not happening at this speed or at 3600/1800.
> 
> I'm going to try a few games to see how this behaves. Because "real world" use is the best bench test. I'm not trying to run a mega corporation or server that has zero fault tolerance or win the right to be on the spreadsheet. How many are on that with all the drivers and programs you normally use daily, loaded and most Windows services on, coming up with "no WHEA"? It doesn't seem plausible given the number of us with WHEA 19's and we have all the regular stuff we use installed. Maybe if I gut the OS to bare minimum and only have OCCT, Prime 95, and just the chipset driver installed I'd be WHEA free?
> 
> The alternative is that AMD has built CPU's that are mostly defective or just falsely advertised to be able to hit even 3800/1900. Because my particular RAM has no barrier to that speed, the board does for whatever reason or the CPU memory controller does. That means the 10 or so on this forum that actually can run truly at 4000/2000 or 3800/1900 have good CPU's and the rest of us struggling have crappy CPU's. Making AMD's defect rate about 90% for the 5600X and about 70% for any other CPU higher. Right now one hour and no WHEA. I'm thinking these RAM testers are causing more WHEA than anything. Pre-boot 600% HCi passes? Only happens when I run a test?
> 
> Sure some settings matter a lot, like SOC voltage, timings, but there comes a point where I think something in the OS is triggering the error, erroneously. Running the Asus TUF Gaming X570-PLUS (no Wi-Fi) with BIOS 3602 Agesa 1.2.0.1
> 
> I know, I'm a "heretic" for questioning the logic and results behind these tests. However, they are all made pre-Ryzen 3 and those that updated might have a "bug" tripping this error more than normal. IMHO


Also, I updated from a 1600af, to a 3600xt, then to a 5600x app within the same month time frame no new windows install. (I did install windows on a different drive to check whea with all my normal program services) 

Considering the minute I pulled my cpu out the package and went to install it into the new b550 board I literally DROPPED IT yes, BENT AN ENTIRE ROW of pins....I didn't get them perfectly straight upon first install, but good enough. I then swapped coolers a few times, and if you used an EK 240, 120, or 360 d-rgb aio, it pulls the chip right outa socket everytime....no matter if the boards warm or not. But, that straightened the pins out back to 100%. 

Anyhow, if I'm one of these 10% my chip would have been platinum to where it's now gold lol.... Unlikely dripping it did anything really since everything's working in order.


----------



## craxton

PJVol said:


> Anyone, who believe he has running IF 2000 stable and just a couple of whea's here and there do not affect the performance overall, can you run DRAM Calculator Membench easy preset and confirm that the result is as expected, i.e. elapsed time is at least no more than with IF1900.
> If it were so on my ASRock setup, I personally would consider it stable.


(edit) after looking at the posts i couldnt see before,
it would seem im quite some ways ahead of the rest running 2000fclk, (my pc doesnt show anything inside WHEA error log)
so, with this little bit of testing from the lot of you, and my 3 runs back to back (only showing one, they were all consistant)
WHEA is GREATLY killing performance, unless most of you are allowing every service and app on startup to stay 
running under the sun. 

kill your tasks, even nvidia Local system display container (not the one with LS) you can kill it too, 
just dont try using AB, or any gpu overclocking tools after wards. (i have 0-1% cpu util, and 7-8% of 32gb ram util while i do any
stress test, benchmarks etc....this is a big factor, to kill services not needed, tasks/apps that doesnt do anything for the pc
besides slow a bench down. ( you can set some services to manual and run those when needed) 
DONT change any if you arent sure what they are/do/for, as you can stop programs/app/windows from working all together correctly

(Ill have to assume most who are ram overclocking AT ALL know everything i just mentioned and then some)
if you arent sure, simply go back (quite some pages now) cant recall if it was @mongoled or not
who shared a stripped down windows to run benchmarks from?

ok, so i dont have any tests for 3800mhz 1900fclk and it dont believe it would be optimal
for me to just simply run my fclk at 1900 with the same timings considering i (therotically) should
be able to tighten up by some margin.

but here is my 4000mhz dram calc easy run. (the saved results were i think my 1600af, if not then it had to be the 3600xt. pretty sure its the 1600af as i eventually hit 3800mhz stable
right before swapping out the cpu.









*If someone has a 5600x with fclk running 1900 
compare your score to mine and if your beating me with similar timings then id have to assume pjvol to be correct
that some of us (4000/2000fclk stable) arent stable at all.....but BUT I SAY*

since ive ran my pc daily 24/7 running cod cold war zombies, valheim, cyberpunk, dying light, and so many more games
without issues (cod still crashes tho on outbreak which i suppose everyone has this issue from time to time) claiming the gpu driver 
is bad or some b.s. anyhow, ANYONE? @Veii does my dram calc test look to be accurate? 

or can you not verify? im not familiar with dram calc memtest scores at all.... i do know latency is higher on dram vs aida,
perhaps due to the app needing more resources? or using more cpu utilization?


----------



## craxton

domdtxdissar said:


> Like i wrote in a other thread some days ago, i have changed back to Agesa 1.1.8.0 because both boost clocks and latencies are better on older bios without training wheels.
> 
> 
> 
> 
> 
> 
> 
> 
> ASUS ROG X570 Crosshair VIII Overclocking &amp...
> 
> 
> Has anyone got any deep experience with tRFC2/tRFC4? Keep seeing the rule that: tRFC2 = tRFC / 1.346 tRFC4 = tRFC2 / 1.625 But I can push tRFC2 = tRFC / 1.415 (with an improvement in performance over tRFC2 = tRFC / 1.346) and tRFC4 seems to be ignored (can set it to the minimum 60 or as high...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> After spending a few days finetuning i have now found my new 24/7 memory settings which iam pretty happy with, considering i'm running 4x8GB sticks and my 5950x wont run WHEA-free above 1900/3800
> 
> Included some numbers for MLC for those interested.
> (have to say its much easier to get low latency with single CCD CPU like 5600x or 5800x)
> View attachment 2482642
> 
> 
> Both CCD's enabled:
> View attachment 2482643
> 
> 
> Stability testing in my bloaty windows install (lost 0.2ns compared to safemode)
> Could have run 50 cycles or more with 1usmus cfg as these settings are 24/7 safe settings and dont fail
> View attachment 2482644
> 
> No WHEA-errors on any of the runs.
> Think this is also the fastest L3 latency i have seen, all thanks to the much better singlecore boosting in agesa 1.1.8.0
> 
> @Veii
> Do you have any suggestions in regards to timings or should i be happy with this at 1900:3800 ?
> tcke 9 + 3-3-15 is no bueno, no matter what drvstr i try. (unsable)


ive noticed no changes between the agea versions. considering tho, i was stable on patch C back then
im unsure if i can contribute much to finding out what works without causing WHEA errors....

0 whea in 126 days and counting... (still have the operations log when i restart the pc tho) not an error just a log of sorts.


----------



## Veii

craxton said:


> @Veii does my dram calc test look to be accurate?


I can't hold to this challenge
My "5600X", is a dual CCD 8 core unit (5950X, lucked out)
Inter-core Latency cuts into it, at nevertheless what speed
It makes me a bit happy on Aida64 (if it also eats this 2ns penalty)
But there is no way how i can beat you 

















For debugging, DRAM Calculator doesn't tell much
But your tRDWR can drop 1 and tWRRD should be 3 not 4 with this SCL
If you struggle with Error 1, 10, 11 stability ~ increase tRRD adjust tWTR for balancing

Maaybe i can come close at 4.85 PBO
But it was not stated if this is purely stock or not
Nevertheless what i do, custom latency is sitting at 3.2/3.3
Maybe AGESA difference

EDIT/Update:
Here is the update with 4.85 @ -30 CO + 40mV
I really think, my 2nd CCD is killing the performance, or your MSI board uses some latency enhancements












GribblyStick said:


> @Veii
> Last post attached as quote since it's been a few pages by now.
> But regarding variances, I tried running AIDA on safe mode to see if that makes a difference and it did.
> So much so that I have to wonder if this is expected? This is the same 1T GDM: ON settings as in the quote below, but there is a drop of 3-4 ns.
> And on top of that, the variance is now less than 0,3ns, down from 1-2 ns. Just from booting in safe mode? That seems like a lot.
> 
> 
> 
> Spoiler: 1T GDM on, safe mode
> 
> 
> 
> 
> View attachment 2482664


Look a bit over this quote and compare it with this








Don't be like this 
Don't be a fool !

Not only don't you use power management, but also it performs worse
It's pretty much cheating and hiding the fact that you didn't really take care of curve optimizer or your windows & doesn't let it boost

It's only hiding your incapability's
I was hoping for a 48ns result as cheating demonstration ~ but i'll take the generally worse one too , as bad example
Don't be like these people and actually work hard.
If you're getting used to cheating early or in high school, getting used to do stuff half-hearted ~ how will you be able to work hard when it actually matters 

I hope the Zen Document maintainer, invalids all results that miss the memory bus and frequency
It's showing an example far from reality & is a bad demonstration of replicatable performance 

EDIT 2:
A little fast trick i've discoverd
Boost tester, check on HWInfo (CPU Snapshot Pooling) - if all your cores hit the effective boost frequency
Now open TM5, check if you can match on absolutely all cores the same target boost frequency
If YES ?, then you did CO right
If NO , lower CO till you can't boot and add positive offset VCore 


Spoiler: Example


----------



## hyroglyphixs

Random question: Is there a reason all the RAM reading software (ZenTimings, Thaiphoon, etc) detects my F4-3200C14-32GTZR (16GB) as F4-3200C14-16GTZR (which should be a 8GB DIMM)?

Is this normal? Seems kinda odd..

Example:









I think I might roll back my B550 Unify X BIOS, I wonder if my terrible time with this memory OC is because I'm using the beta (A21) instead of the production (A1)..


----------



## YpsiNine

hyroglyphixs said:


> Random question: Is there a reason all the RAM reading software (ZenTimings, Thaiphoon, etc) detects my F4-3200C14-32GTZR (16GB) as F4-3200C14-16GTZR (which should be a 8GB DIMM)?
> 
> Is this normal? Seems kinda odd..


The name of the kit is 32GTZR.

The name of one DIMM (as these programs read) is 16GTZR.

Nothing strange about this...


----------



## Merutsu

hyroglyphixs said:


> Random question: Is there a reason all the RAM reading software (ZenTimings, Thaiphoon, etc) detects my F4-3200C14-32GTZR (16GB) as F4-3200C14-16GTZR (which should be a 8GB DIMM)?


F4-3200C14Q - kit of four
F4-3200C14D - kit of two
F4-3200C14 - single ram stick


----------



## nobody.nowhere

Hello all.

I'm hoping someone can recommend any timing changes for my configuration that might help me close the gap on latency (but also open to bandwidth advice).
Hynix MJR on a 3970x - So I'm not going to win any latency speed challenges anytime soon...

Ram is G.Skill F4-3600C18Q-128GTZR (4x 32GB) 2Rx8 B1 1.35v
















Auto settings for tRDRD__ and tWRWR__, tRDWR, tWRRD, tRFC2/4, and all voltages and resistances (except for a slightly lowered vSOC - 1.1v down to 1.075v).
I haven't yet performed a full stability test, but it's passed 20 hours of prime95 large FFTs, no hardware errors or Prime95 errors.
I had the above timings running at 1866 / 3733, but I got an infinity fabric L3 cache error after about 9 hours of testing, and decided not to go down the path of VDDG over-volting.


Spoiler: Kernel error after 9 hours at 1866 / 3733




mce: [Hardware Error]: Machine check events logged
[Hardware Error]: Corrected error, no action required.
[Hardware Error]: CPU:0 (17:31:0) MC27_STATUS[-|CE|MiscV|-|-|-|SyndV|-|-|-]: 0x982000000002080b
[Hardware Error]: IPID: 0x0001002e00001e01, Syndrome: 0x000000005a020009
[Hardware Error]: Power, Interrupts, etc. Ext. Error Code: 2, Link Error.
[Hardware Error]: cache level: L3/GEN, mem/io: IO, mem-tx: GEN, part-proc: SRC (no timeout)​




I can lower tRC to ~62, but then my ratios are out with tRC, tRTP, and tWR all being factors of tRFC - without detailed testing, I'm not sure if divisible factors, or lowest timings are more important.

Any advice appreciated, as not many people seem to be running this type of setup. Thanks.


----------



## nobody.nowhere

WHEA - My 2 cents...

If you're purely aiming for bench-marking top scores, WHEA events are probably not a concern.. But this is a stability thread.
The majority of WHEA events in relation to overclocking will be of the Machine Check Exception form - Machine-check exception (wikipedia)

WHEA / MCE is an example of the hardware trying a last-line-of-defence type of recovery from an inherently unstable situation (CPU core, Cache, IO, RAM), and if it can't recover, BSOD / hang.
In other words, if you're seeing these errors, your using every bit of your hardware to go as fast as possible, and effectively rendering the in-built error recovery characteristics of the CPU useless, as they are now focused on the everyday running of the CPU, rather than the once in a lifetime recovery during that critical moment we all have when our PCs must not fail.

A poor analogy might be to take the brakes off a car, as they add weight and slow you down from a theoretical top speed, by some small margin - although car brakes are by design needed much more often than MCE is intended by it's design.

The other option, if you're not overclocking, is that you genuinely have some kind of fault / bug in hardware / firmware.

My advice (for anyone who cares to hear my advice)... as soon as you see 1 WHEA, consider your setup unstable, just as you would for a memtest / prime95 / other failure, and begin diagnosing / adjusting your overclocking parameters.


----------



## GribblyStick

Spoiler: Quote






Veii said:


> I can't hold to this challenge
> My "5600X", is a dual CCD 8 core unit (5950X, lucked out)
> Inter-core Latency cuts into it, at nevertheless what speed
> It makes me a bit happy on Aida64 (if it also eats this 2ns penalty)
> But there is no way how i can beat you
> View attachment 2482692
> 
> View attachment 2482693
> 
> 
> For debugging, DRAM Calculator doesn't tell much
> But your tRDWR can drop 1 and tWRRD should be 3 not 4 with this SCL
> If you struggle with Error 1, 10, 11 stability ~ increase tRRD adjust tWTR for balancing
> 
> Maaybe i can come close at 4.85 PBO
> But it was not stated if this is purely stock or not
> Nevertheless what i do, custom latency is sitting at 3.2/3.3
> Maybe AGESA difference
> 
> EDIT/Update:
> Here is the update with 4.85 @ -30 CO + 40mV
> I really think, my 2nd CCD is killing the performance, or your MSI board uses some latency enhancements
> View attachment 2482695
> 
> 
> 
> 
> Look a bit over this quote and compare it with this
> View attachment 2482696
> 
> Don't be like this
> Don't be a fool !
> 
> Not only don't you use power management, but also it performs worse
> It's pretty much cheating and hiding the fact that you didn't really take care of curve optimizer or your windows & doesn't let it boost
> 
> It's only hiding your incapability's
> I was hoping for a 48ns result as cheating demonstration ~ but i'll take the generally worse one too , as bad example
> Don't be like these people and actually work hard.
> If you're getting used to cheating early or in high school, getting used to do stuff half-hearted ~ how will you be able to work hard when it actually matters
> 
> I hope the Zen Document maintainer, invalids all results that miss the memory bus and frequency
> It's showing an example far from reality & is a bad demonstration of replicatable performance
> 
> EDIT 2:
> A little fast trick i've discoverd
> Boost tester, check on HWInfo (CPU Snapshot Pooling) - if all your cores hit the effective boost frequency
> Now open TM5, check if you can match on absolutely all cores the same target boost frequency
> If YES ?, then you did CO right
> If NO , lower CO till you can't boot and add positive offset VCore
> 
> 
> Spoiler: Example
> 
> 
> 
> 
> View attachment 2482697





@Veii
huh?
I'm sorry, I'm really confused.
My own quoted post has my current OC where I am (still) looking for feedback . I only included it for convenience, none of that was on safe mode.
The new comment was an addition to that. Since I find it impossible to get the run-to-run latency variance down to acceptable levels, I thought it would be worth a shot to try in safe mode.
That way I could eliminate any bloat I might have. So I expected the results to be a bit more stable, but not to the extent that I got.

Your screenshot actually makes me question that even more. In my case I dropped a whopping 3-4 ns on top of being more stable.
In your case the results are actually worse, but still really close.
My intent was not to go "hey look, I have a decent OC", the intent was to find out if this big of a difference offers any insight into why I am seeing latency this variable.

I'm still curious how I could improve my current settings, regardless of latency, but my thought was that this is too big of a difference to be normal if simply accounting for various services.
This is more than I have been able to lower the latency down from DOCP settings. I just don't have the chops to even begin to suspect what might be causing that.

As of for an CPU overclocking, I haven't touched anything at all regarding PBO or all core overclocking.
My impression was that overclocking the cpu offers very little gain on day-to-day systems compared to stock pbo.
So contrary to popular opinion I wanted to get my memory configured first and then see what I can do on CPU side with whatever wiggle room I have left.


----------



## Veii

GribblyStick said:


> @Veii
> huh?
> I'm sorry, I'm really confused.
> 
> Your screenshot actually makes me question that even more. In my case I dropped a whopping 3-4 ns on top of being more stable.
> In your case the results are actually worse, but still really close.
> My intent was not to go "hey look, I have a decent OC", the intent was to find out if this big of a difference offers any insight into why I am seeing latency this variable.
> 
> 
> As of for an CPU overclocking, I haven't touched anything at all regarding PBO or all core overclocking.
> My impression was that overclocking the cpu offers very little gain on day-to-day systems compared to stock pbo.
> So contrary to popular opinion I wanted to get my memory configured first and then see what I can do on CPU side with whatever wiggle room I have left.


It was not you as a target, but generally speaking. Maybe because the response was split ~ it got confusing
I think SMU 56.44 and higher broke also Package C-State generation & not only DF_States
I try to fix it, but the loss of 2ns is too much to ignore it
I remember they worked well, but it's strange

Yes something certainly is broken between Global C-States, DF_C-States & 4G mode
sometimes i lose 2ns , sometimes i have 2ns more - but not between tests but between AMD CBS changes
They stick then till i CMOS reset
it's really awkward

You should try to disable both manually and see if there is any latency improvement
It should be a big one of at least 1ns ~ else it's testing just instability and not a bios bug

C-States and powerplans sometimes cause random reboots , i try to investigate


----------



## craxton

Veii said:


> For debugging, DRAM Calculator doesn't tell much
> But your tRDWR can drop 1 and tWRRD should be 3 not 4 with this SCL
> If you struggle with Error 1, 10, 11 stability ~ increase tRRD adjust tWTR for balancing
> 
> Maaybe i can come close at 4.85 PBO
> But it was not stated if this is purely stock or not
> Nevertheless what i do, custom latency is sitting at 3.2/3.3
> Maybe AGESA difference
> 
> EDIT/Update:
> Here is the update with 4.85 @ -30 CO + 40mV
> I really think, my 2nd CCD is killing the performance, or your MSI board uses some latency enhancements


I thought that dual CCD were supposed to be better lol ?
i personally dont use any latency enhancer inside the bios, its set to disabled and has been since a
started using the 5600x, unsure if it actually does anything to help it while its on auto, or set to MSI
as ive noticed no difference other than taking longer to boot from time to time with it being on

atm, im on route to the air port, so i cant change anything regarding the timings

i was curious tho, if the timings were 100% the best they "should" be, (not what youd do with then lol)
im not sure if your directing the CO to me or the other being mentioned in your comment,
i cant get CO 30 to turn on at all, so i dont think ill be doing much there.

i just have a -0.100mv offset inside the bios, (its set to something like that)

hopefully this trip goes good and i snag a 3080 while im in florida somewhere....
be nice to start allowing the chip to stretch its legs while running games lol.

(EDIT) made the wife turn around just so i could go (get something) try this...
got PER CORE CO, which is some random as* shi* i just put in, but none the less it worked...
with a +.0375 offset since when i set .40mv my pc starting DING DONG (windows doing this for some reason)
like it was telling me something without any error, any messages etc.
i think CO was, -23,-17,-22,-27,-27,-17 something like that. will dial it in (after i get back from vacation)
since were already supposed to be in toledo to meet up with her gf etc...

anyhow, i swapped the timings you mentioned as well, this is what i got 
(EDIT#2) it would seem as if im scoring worse? would that be correct due to having CO now vs a all core -.10mv?

im never gonna make it to florida lol once i start messing with overclocks/ram i dont stop for weeks.....


----------



## Veii

craxton said:


> I thought that dual CCD were supposed to be better lol ?
> i personally dont use any latency enhancer inside the bios, its set to disabled and has been since a
> started using the 5600x, unsure if it actually does anything to help it while its on auto, or set to MSI
> as ive noticed no difference other than taking longer to boot from time to time with it being on
> 
> atm, im on route to the air port, so i cant change anything regarding the timings
> 
> i was curious tho, if the timings were 100% the best they "should" be, (not what youd do with then lol)
> im not sure if your directing the CO to me or the other being mentioned in your comment,
> i cant get CO 30 to turn on at all, so i dont think ill be doing much there.
> 
> i just have a -0.100mv offset inside the bios, (its set to something like that)
> 
> hopefully this trip goes good and i snag a 3080 while im in florida somewhere....
> be nice to start allowing the chip to stretch its legs while running games lol.


Dual CCDs have a latency penalty of 2ns
I get some awkward strangeness and overboosting to 5.1ghz according to ACPI values ~ which is bizarre

I couldn't run -30 CO also without added vCore offset
but it appears the better method , maxing out CO and then dampening it with vcore
compared to the other way around 
dLDO_injector will then offset and smooth out the voltage differences

There is indeed some strangeness going on with the basic powerplans and C-State, DF-CState
sometimes they work, on other powerplans the shifting is too fast and it voltage crashes
On other times it overboosts. Really really bizzare 
C-State + DF State, can run and give me the same result @ 48.9ns + random overboosting score boosts
C-State + DF State disable, randomly give me 48.7ns but only if powerplans are set up well. but it doesn't go bellow APCI value 20. No sleeping and no cache boost 

Very Strange
But try around if you see big latency differences ~ i personally think that up to chipset installation default powerplans are actually broken. Well something is broken for sure.
About CO ~ TM5 needs to hit the same maximum frequency on all cores. Lower CO till you can sustain it 
Then damp it with vCore and per-core stability test it if you have the time. But it will randomly reboot if it's wrong


----------



## craxton

Veii said:


> Dual CCDs have a latency penalty of 2ns
> I get some awkward strangeness and overboosting to 5.1ghz according to ACPI values ~ which is bizarre
> 
> I couldn't run -30 CO also without added vCore offset
> but it appears the better method , maxing out CO and then dampening it with vcore
> compared to the other way around
> dLDO_injector will then offset and smooth out the voltage differences
> 
> There is indeed some strangeness going on with the basic powerplans and C-State, DF-CState
> sometimes they work, on other powerplans the shifting is too fast and it voltage crashes
> On other times it overboosts. Really really bizzare
> C-State + DF State, can run and give me the same result @ 48.9ns + random overboosting score boosts
> C-State + DF State disable, randomly give me 48.7ns but only if powerplans are set up well. but it doesn't go bellow APCI value 20. No sleeping and no cache boost
> 
> Very Strange
> But try around if you see big latency differences ~ i personally think that up to chipset installation default powerplans are actually broken. Well something is broken for sure.
> *About CO ~ TM5 needs to hit the same maximum frequency on all cores. Lower CO till you can sustain it
> Then damp it with vCore and per-core stability test it if you have the time. But it will randomly reboot if it's wrong*


i couldnt tell if i have strange things happen with C-states/DF states or not, i dont have issues waking the pc
or issues with the cpu not boosting/sleeping when needed be.

i thought what i shared there, was all cores/threads boosting the same?

am i missing something in hwinfo lol?

(re-edited) that post above, dram calc score got worse, is this normal with CO


(adding aida bench) this is the best aida bench ive had to date...minor improvements but, still improvements are better 
so, thankyou for pointing out my timing errors, care to tell if these are correct? ill stress test later.

(edit #3) im not looking to change rtt, or cad_bus strengths. if i set to 
what you mention to the others with single rank 4x8 dimms then i have way WAY to many issues
trying to counter. but, seeing how i have no signs of instability issues, id have to assume there
what my board/sticks wishes to have, i probably could adjust but thats a headache trying to balance.


----------



## _frame_

Veii said:


> Dual CCDs have a latency penalty of 2ns


*domdtxdissar *has proven on a previous page that if 1 CCD is disabled then there is no 2 ns penalty. I guess you do not have this 2 ns penalty... But the dram calc result is strange!


----------



## craxton

_frame_ said:


> *domdtxdissar *has proven on a previous page that if 1 CCD is disabled then there is no 2 ns penalty. I guess you do not have this 2 ns penalty... But the dram calc result is strange!


how, are you guys selecting what you quote? 
are you quoting then removing parts of the message, then leaving what your responding to?


----------



## _frame_

craxton said:


> how, are you guys selecting what you quote?


highlight the text you are going to quote and there appears popup menu (in Chrome at least)


----------



## craxton

_frame_ said:


> highlight the text


AHHHH thank you!!!!!!!!!!!!!!


----------



## craxton

...........#hastobebugged-
my last score was 4335 i think that was my best, unsure.









and of course i add r23 which my best was 12001 but its not saved...







this is what curve does?????


----------



## _frame_

craxton said:


> I'll test for ya on my board running 2000fclk "claimed whea free and stable daily" when I get home shortly.


Have you tried OCCT - large data set - extreme for 1 hour? Found it is most heavy for WHEA testing =)


----------



## craxton

_frame_ said:


> Have you tried OCCT - large data set - extreme for 1 hour? Found it is most heavy for WHEA testing =)


yep, ive ran OCCT, prime FFT, tm5 1usmus and anta777 1000%, HCI, and y-cruncher 4 runs back to back 3 times ina row. 

no whea, no crashing, notta thing. 
ive been almost 130 days now WHEA free with 1 crash due to MSI dragon center. (supposedly a known thing that happens to others)

as far as i can tell, i cant make it throw any WHEA with stress testing. from what i was told, over on AMD reddit page
operations log folder simply states that WHEA error source 
trackers are active which should be to find WHEA errors. 

i have 4 every time i restart the pc. so as you see its got quite long since feb when i restart the pc to adjust something or whatnot...

(i ran OCCT 7.3.2, 8.0.0.8, and 8.0.0.3 all for well over an hour each) and no errors were thrown.
i thought that i had an issue due to how many actually have WHEA at even 3600mhz ram oc.
so i reinstalled windows on a different drive, and sure enough.
the same thing, no errors.

did however have the same 4 things under operations log. anyhow, so far
on all bios after patch C for this board, ive been WHEA free. 

patch B/C tho, i had WHEA quite alot....


----------



## mackbolan

nobody.nowhere said:


> WHEA - My 2 cents...
> 
> If you're purely aiming for bench-marking top scores, WHEA events are probably not a concern.. But this is a stability thread.
> The majority of WHEA events in relation to overclocking will be of the Machine Check Exception form - Machine-check exception (wikipedia)
> 
> WHEA / MCE is an example of the hardware trying a last-line-of-defence type of recovery from an inherently unstable situation (CPU core, Cache, IO, RAM), and if it can't recover, BSOD / hang.
> In other words, if you're seeing these errors, your using every bit of your hardware to go as fast as possible, and effectively rendering the in-built error recovery characteristics of the CPU useless, as they are now focused on the everyday running of the CPU, rather than the once in a lifetime recovery during that critical moment we all have when our PCs must not fail.
> 
> A poor analogy might be to take the brakes off a car, as they add weight and slow you down from a theoretical top speed, by some small margin - although car brakes are by design needed much more often than MCE is intended by it's design.
> 
> The other option, if you're not overclocking, is that you genuinely have some kind of fault / bug in hardware / firmware.
> 
> My advice (for anyone who cares to hear my advice)... as soon as you see 1 WHEA, consider your setup unstable, just as you would for a memtest / prime95 / other failure, and begin diagnosing / adjusting your overclocking parameters.



Adding my 2 cents too. I noticed all these "proof" shots on the spreadsheet have these tests I pass but yet still have WHEA in the "Event Viewer". No one posts the pic of the Windows "Event Viewer"/ "System" to prove there was actually no WHEA. Even OCCT misses them unless it's truly a crappy RAM timing. Like HWiNFO showed me having WHEA's when I tried some ridiculous RAM timings that also failed DRAM Calc. For instance, I plugged in my pre-set for "stable" 4000/2000 that has @craxton 's settings in it (running 2 X 8GB , not 4 like him but it works). I have no errors, hangs, games run good, but it tosses WHEA 19's like no tomorrow in "Event Viewer" when a RAM test is run where it shows no error and passing. 

I'm really interested to see people's "Event Viewer", like I posted one with redacted system name, showing my WHEA history. That would be true proof that these 3800/1900's and 4000/2000 runners are really error free. Even @craxton said he turns off every non-essential service to benchmark. While that's nice so one can pass a test, I think most of us are looking for daily 24/7 type stability. 

So if I'm correct and no one can post a clean "Event Viewer" log, running any one of these RAM tests, one can't be positive that the PC is indeed WHEA free. The only no clean "Event Viewer" screen shots I can post happen with 3733/1866 after the 1.2.0.1 update or 3600/1800. Any other higher setting is a WHEA fest with any timing, any voltage but appears stable and passes all these tests that are being shown as "proof" of stability. 

I'm WHEA free now but load this up with a game or RAM test and the WHEA 19's flow. The game will run fine for hours, no hitch but I noticed post gamer it will not open the window for AMD Radeon from the task bar to full screen. Everything else is fine. Run another game, surf the web, etc. No issue. check in "Event Viewer" and anything other than surfing, watching a movie, will result in WHEA 19 using 4000/2000. 

I noticed some people posting "proof" where they must be using only one core active or serious LN2 to hit 5Ghz on a 5600X consistently. One ran in safe mode with 1 CCX disabled to achieve the score. Neither is proving a 24/7 stable system. None have a screen shot of "Event Viewer" where hidden WHEA's go. Some are using higher BLCK to overcome FCLK limits, would be nice to hear how to do it without making it so your drives still work and GPU. How far can one go? I'm thinking possibly to 102 before a serious issue.

Researching it just seems some are stretching more than clocks and don't want to look in "Event Viewer", call it clean after many RAM tests pass and no BSOD's. Because mine will pass all these tests fine but the Windows log doesn't lie. If error 19 doesn't matter there, then I've been stable at several speeds. All this is regarding results from the 5600X and running higher than 1866 IF without a WHEA 19. Sure, 5900X or 5950X have a much better chance at the very elusive 1900 or 2000 IF. The 5600X and 5800X are not so lucky, IMHO.

Prove me wrong and post some Windows logs that show no WHEA 19's. I'm not even saying people are purposely evading the truth, they assume by these test results there is no WHEA. I bet there's a very small handful of people that have a 5600X or 5800X that have clean logs running normal with a 1900 or 2000 IF in 1:1:1 and a medium sized with a 5900x or higher.

In any case, if you're claiming no WHEA 19 and you have them in the Windows Event Viewer, you're fooling yourself and some people hoping to find the "unicorn". Many will keep chasing after 3800/1900 or 4000/2000 because it seems like nearly all on here can achieve that. However, if the passing standard is providing the results from TM5, HCi, DRAM Calc, y cruncher, etc., showing zero errors found, then I should be posting my results as well. The real proof would look like this pic but error free, so the time/date match the rest. You can see my DRAM Calc shows no errors.


----------



## domdtxdissar

mackbolan said:


> Adding my 2 cents too. I noticed all these "proof" shots on the spreadsheet have these tests I pass but yet still have WHEA in the "Event Viewer". No one posts the pic of the Windows "Event Viewer"/ "System" to prove there was actually no WHEA. Even OCCT misses them unless it's truly a crappy RAM timing. Like HWiNFO showed me having WHEA's when I tried some ridiculous RAM timings that also failed DRAM Calc. For instance, I plugged in my pre-set for "stable" 4000/2000 that has @craxton 's settings in it (running 2 X 8GB , not 4 like him but it works). I have no errors, hangs, games run good, but it tosses WHEA 19's like no tomorrow in "Event Viewer" when a RAM test is run where it shows no error and passing.
> 
> I'm really interested to see people's "Event Viewer", like I posted one with redacted system name, showing my WHEA history. That would be true proof that these 3800/1900's and 4000/2000 runners are really error free. Even @craxton said he turns off every non-essential service to benchmark. While that's nice so one can pass a test, I think most of us are looking for daily 24/7 type stability.
> 
> So if I'm correct and no one can post a clean "Event Viewer" log, running any one of these RAM tests, one can't be positive that the PC is indeed WHEA free. The only no clean "Event Viewer" screen shots I can post happen with 3733/1866 after the 1.2.0.1 update or 3600/1800. Any other higher setting is a WHEA fest with any timing, any voltage but appears stable and passes all these tests that are being shown as "proof" of stability.
> 
> I'm WHEA free now but load this up with a game or RAM test and the WHEA 19's flow. The game will run fine for hours, no hitch but I noticed post gamer it will not open the window for AMD Radeon from the task bar to full screen. Everything else is fine. Run another game, surf the web, etc. No issue. check in "Event Viewer" and anything other than surfing, watching a movie, will result in WHEA 19 using 4000/2000.
> 
> I noticed some people posting "proof" where they must be using only one core active or serious LN2 to hit 5Ghz on a 5600X consistently. One ran in safe mode with 1 CCX disabled to achieve the score. Neither is proving a 24/7 stable system. None have a screen shot of "Event Viewer" where hidden WHEA's go. Some are using higher BLCK to overcome FCLK limits, would be nice to hear how to do it without making it so your drives still work and GPU. How far can one go? I'm thinking possibly to 102 before a serious issue.
> 
> Researching it just seems some are stretching more than clocks and don't want to look in "Event Viewer", call it clean after many RAM tests pass and no BSOD's. Because mine will pass all these tests fine but the Windows log doesn't lie. If error 19 doesn't matter there, then I've been stable at several speeds. All this is regarding results from the 5600X and running higher than 1866 IF without a WHEA 19. Sure, 5900X or 5950X have a much better chance at the very elusive 1900 or 2000 IF. The 5600X and 5800X are not so lucky, IMHO.
> 
> Prove me wrong and post some Windows logs that show no WHEA 19's. I'm not even saying people are purposely evading the truth, they assume by these test results there is no WHEA. I bet there's a very small handful of people that have a 5600X or 5800X that have clean logs running normal with a 1900 or 2000 IF in 1:1:1 and a medium sized with a 5900x or higher.
> 
> In any case, if you're claiming no WHEA 19 and you have them in the Windows Event Viewer, you're fooling yourself and some people hoping to find the "unicorn". Many will keep chasing after 3800/1900 or 4000/2000 because it seems like nearly all on here can achieve that. However, if the passing standard is providing the results from TM5, HCi, DRAM Calc, y cruncher, etc., showing zero errors found, then I should be posting my results as well. The real proof would look like this pic but error free, so the time/date match the rest. You can see my DRAM Calc shows no errors.
> View attachment 2482741
> View attachment 2482743


HWinfo reports WHEA errors, that's why some of us have it included as proof, but lots of ppl run unstable systems and try to hide it by not showing the report.


----------



## domdtxdissar

craxton said:


> ok, so i dont have any tests for 3800mhz 1900fclk and it dont believe it would be optimal
> for me to just simply run my fclk at 1900 with the same timings considering i (therotically) should
> be able to tighten up by some margin.
> 
> 
> 
> 
> 
> 
> 
> 
> but here is my 4000mhz dram calc easy run. (the saved results were i think my 1600af, if not then it had to be the 3600xt. pretty sure its the 1600af as i eventually hit 3800mhz stable
> right before swapping out the cpu.


Here is my fastet run with my daily 24/7 memory settings with fans on auto etc i linked 2 pages ago, at *1900:3800 speeds*








More settings can be found in my original post: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## hyroglyphixs

So, if any of you have read my previous posts, I've been having quite a bit of trouble getting my RAM OC stable, so I decided to go XMP with some sub-timings tuned. After finally getting _something _stable (TM5 Usmus 10 cycles with no errors, OCCT no errors), I ran AIDA benchmark and I'm getting drastically lowered read speeds, does anyone know what's going on? No other settings in BIOS is being changed..

XMP:









Subtimings "re-done":


----------



## craxton

mackbolan said:


> Adding my 2 cents too. I noticed all these "proof" shots on the spreadsheet have these tests I pass but yet still have WHEA in the "Event Viewer". No one posts the pic of the Windows "Event Viewer"/ "System" to prove there was actually no WHEA. Even OCCT misses them unless it's truly a crappy RAM timing. Like HWiNFO showed me having WHEA's when I tried some ridiculous RAM timings that also failed DRAM Calc. For instance, I plugged in my pre-set for "stable" 4000/2000 that has @craxton 's settings in it (running 2 X 8GB , not 4 like him but it works). I have no errors, hangs, games run good, but it tosses WHEA 19's like no tomorrow in "Event Viewer" when a RAM test is run where it shows no error and passing.
> 
> I'm really interested to see people's "Event Viewer", like I posted one with redacted system name, showing my WHEA history. That would be true proof that these 3800/1900's and 4000/2000 runners are really error free. Even @craxton said he turns off every non-essential service to benchmark. While that's nice so one can pass a test, I think most of us are looking for daily 24/7 type stability.
> 
> So if I'm correct and no one can post a clean "Event Viewer" log, running any one of these RAM tests, one can't be positive that the PC is indeed WHEA free. The only no clean "Event Viewer" screen shots I can post happen with 3733/1866 after the 1.2.0.1 update or 3600/1800. Any other higher setting is a WHEA fest with any timing, any voltage but appears stable and passes all these tests that are being shown as "proof" of stability.
> 
> I'm WHEA free now but load this up with a game or RAM test and the WHEA 19's flow. The game will run fine for hours, no hitch but I noticed post gamer it will not open the window for AMD Radeon from the task bar to full screen. Everything else is fine. Run another game, surf the web, etc. No issue. check in "Event Viewer" and anything other than surfing, watching a movie, will result in WHEA 19 using 4000/2000.
> 
> I noticed some people posting "proof" where they must be using only one core active or serious LN2 to hit 5Ghz on a 5600X consistently. One ran in safe mode with 1 CCX disabled to achieve the score. Neither is proving a 24/7 stable system. None have a screen shot of "Event Viewer" where hidden WHEA's go. Some are using higher BLCK to overcome FCLK limits, would be nice to hear how to do it without making it so your drives still work and GPU. How far can one go? I'm thinking possibly to 102 before a serious issue.
> 
> Researching it just seems some are stretching more than clocks and don't want to look in "Event Viewer", call it clean after many RAM tests pass and no BSOD's. Because mine will pass all these tests fine but the Windows log doesn't lie. If error 19 doesn't matter there, then I've been stable at several speeds. All this is regarding results from the 5600X and running higher than 1866 IF without a WHEA 19. Sure, 5900X or 5950X have a much better chance at the very elusive 1900 or 2000 IF. The 5600X and 5800X are not so lucky, IMHO.
> 
> Prove me wrong and post some Windows logs that show no WHEA 19's. I'm not even saying people are purposely evading the truth, they assume by these test results there is no WHEA. I bet there's a very small handful of people that have a 5600X or 5800X that have clean logs running normal with a 1900 or 2000 IF in 1:1:1 and a medium sized with a 5900x or higher.
> 
> In any case, if you're claiming no WHEA 19 and you have them in the Windows Event Viewer, you're fooling yourself and some people hoping to find the "unicorn". Many will keep chasing after 3800/1900 or 4000/2000 because it seems like nearly all on here can achieve that. However, if the passing standard is providing the results from TM5, HCi, DRAM Calc, y cruncher, etc., showing zero errors found, then I should be posting my results as well. The real proof would look like this pic but error free, so the time/date match the rest. You can see my DRAM Calc shows no errors.
> View attachment 2482741
> View attachment 2482743


You not in whea logger lol, go under applications and services, microsoft, windows, kernel WHEA.

That's where actual whea errors are stored. The log you posted are services etc. Info is what's filled in mine. I just shared a shot of whea log in event viewer a few hours ago.

Not ona pc now and won't be for a week at the least. I'm using no bclk work around, no tricks to hide whea, my only thing I hide is my pc name being called blackBOSS lol so people don't say I'm racist or something...the pc is black none the less....

Anyhow, not many claim whea free. I'm not on the spread sheet, but I don't just claim whea free I have been since feb or later.

Last error I had was right after swapping to the 5600x. I have a 2x8 config you can copy paste that has better timings. Since what your copying now is for 4 sticks. 

As stated tho, it'll be sometime before I'm on my PC again. It's in the comments here somewhere just gotta go back at least 20/30 pages

(Edit) I'm 24/7 daily stable, idk if you noticed tho, most here all have whea errors out the wazoo and can't fix it either. There's only a handful who run 4000/2000 stable without whea. 

It may be due to the chip, ram, board idk, I'd try a b550 gaming edge board and if you come out whea clean then we know where the issue lies. Perhaps that's why msi is slow as a mofo about getting bios releases done?


----------



## domdtxdissar

craxton said:


> You not in whea logger lol, go under applications and services, microsoft, windows, kernel WHEA.
> 
> That's where actual whea errors are stored. The log you posted are services etc. Info is what's filled in mine. I just shared a shot of whea log in event viewer a few hours ago.


Lol you guys are talking about different WHEA errors.

ID19 = event viewer -> windows logs ->system
ID20 = event viewer -> applications and services -> microsoft -> windows -> kernel WHEA.

As far as i know, its mostly event19 people have problems with on Zen3 platform.. So its maybe not so strange you have no event20 errors @ *craxton ? *(have you checked for event19 ?)

Its atleast WHEA error event 19 iam getting when i try to push past 1900:3800

Quick google search:









Ryzen 3800x, WHEA-Logger Event 19.


Evening everyone, I was curious if anyone could help me with an issue I've been having on my computer: Operating System: Windows 10 Pro 64-bitCPU: AMD Ryzen 7 3800X 8-Core Processor RAM: G.Skill F4-3600C16D-16GTZR (16.0GB) (@ 3733CL16) Motherboard: ASUS ROG STRIX X570-E GAMING (2802 BIOS)...




www.overclock.net








__





Whea 19 events with 3700X


Hello, I've been receiving WHEA-19 warnings (Unknown Error Source and Corrected Machine Check, with type of No Error from Processor Core) for my machine the last couple of months (since last year november maybe). It started with a BIOS update: BIOS 1403 (ASUS PRIME X570-PRO) fixed a WHEA-17...




community.amd.com












WHEA-Logger Event 19 errors on 3900X


CPU: Ryzen 9 3900X CPU Cooler: Noctua NH-D15 Chromax Black Thermal Compound: Noctua NT-H2 GPU: Zotac RTX 2070 Mini RAM: 2x 16 GB G.Skill Ripjaws V 3600 MHz CL16 Mobo: ASUS ROG Strix B550-F, BIOS Ver. 1202, AGESA 1.1.0.0 Patch B PSU: Corsair CX 650 2017 80+ Bronze Non-Modular Storage: 1x 500 GB...




www.techpowerup.com












Ryzen 5000 WHEAs


I was lucky to get 5950x on the launch day and put in into my MSI B550 Tomahawk. The CPU is as good as described by reviewers but I think the Zen2 story returned. I get a lot of WHEA (Bus/Interconnection) errors. No problem with stability but errors perstist with new BIOS, fresh Windows and...




www.techpowerup.com





That thread linked a few pages back that talked about event20 is from 2012 that was affecting mostly Intel systems..


----------



## PJVol

domdtxdissar said:


> but lots of ppl run unsable systems and try to hide it by not showing the report.


 good nominee for "Best conspiracy theory" winning award.


----------



## _frame_

OMG
ok 2 screenshots for 1 test LOL
no WHEA19, no WHEA20


----------



## RonLazer

It's not a hoax, I could run 2000 FCLK with absolutely any stress test, Linpack, OCCT, p95, mixed GPU/CPU/RAM tests etc. Then a few days ago something seems to have broken and now I can't go over 1900. Unsure if it was:

1. running an all-core static OC for a few hours - ([email protected], 2nd lowest LLC, SMT disabled)
2. testing TurboV - (only tried lowering SOC in windows by 25mV to check it was reflected in HWiNFO, which seems innocent, but the WHEAs started immediately after).
3. AGESA 1.2.0.1 - but no one else seems to have had issues with WHEAs on previously stable chips.


----------



## Br3ach

hyroglyphixs said:


> does anyone know what's going on?


What ICs? If that's C-die, it's allergic to high voltage. See if going back to 1.3 - 1.35V makes a difference in terms of AIDA scores.


----------



## hyroglyphixs

Br3ach said:


> What ICs? If that's C-die, it's allergic to high voltage. See if going back to 1.3 - 1.35V makes a difference in terms of AIDA scores.


These are definitely B-Die sticks. I actually figured out something very strange. When I read the XMP profile in Thaiphoon and AIDA, this is what I get:

















And then when I load XMP and look at the timings, this is what I see:









tRC, tFAW, tRRDS and tRRDL are all not matching the XMP profile, is this normal?


----------



## Sleepycat

hyroglyphixs said:


> These are definitely B-Die sticks. I actually figured out something very strange. When I read the XMP profile in Thaiphoon and AIDA, this is what I get:
> View attachment 2482776
> 
> View attachment 2482779
> 
> 
> And then when I load XMP and look at the timings, this is what I see:
> View attachment 2482777
> 
> 
> tRC, tFAW, tRRDS and tRRDL are all not matching the XMP profile, is this normal?


Normal, DOCP in most motherboards only sets the tCL, tRCDWR, tRCDRD, tRP, tRAS and DIMM voltage. Everything else is left on Auto, even if the XMP profile includes tRC, tFAW, tRRDS and tRRDL.


----------



## thigobr

Small addendum: HWiNFO will report WHEAS only if it happened while the program is running... If you were running tests and had WHEA errors before opening HWiNFO it won't show anything.


----------



## hyroglyphixs

Sleepycat said:


> Normal, DOCP in most motherboards only sets the tCL, tRCDWR, tRCDRD, tRP, tRAS and DIMM voltage. Everything else is left on Auto, even if the XMP profile includes tRC, tFAW, tRRDS and tRRDL.


Gotcha, thanks! I'm having such a hard time finding stability, I'm actually currently running TM5 Anta trying 3600 CL16 XMP settings for the G Skill B Die kit (I have the 3200 CL14 G Skill B Die kit) and I entered in the XMP 16-16-16-16-36 1.35V, plus the tRC, tFAW, tRRDS and tRRDL and everything else on auto.. hopefully this will work


----------



## RonLazer

I tried flashing back to AGESA 1.2.0.0 and the WHEAs are still there, although I noticed something very odd, they occur at exactly 60s intervals, and are not set off by any stress tests. Even OCCT Large AVX2 doesn't affect the rate, just a single WHEA Event 19 once per minute.


----------



## Veii

craxton said:


> I thought that dual CCD were supposed to be better lol ?
> i personally dont use any latency enhancer inside the bios, its set to disabled and has been since a
> started using the 5600x, unsure if it actually does anything to help it while its on auto, or set to MSI
> as ive noticed no difference other than taking longer to boot from time to time with it being on
> 
> atm, im on route to the air port, so i cant change anything regarding the timings
> 
> i was curious tho, if the timings were 100% the best they "should" be, (not what youd do with then lol)
> im not sure if your directing the CO to me or the other being mentioned in your comment,
> i cant get CO 30 to turn on at all, so i dont think ill be doing much there.
> 
> i just have a -0.100mv offset inside the bios, (its set to something like that)
> 
> hopefully this trip goes good and i snag a 3080 while im in florida somewhere....
> be nice to start allowing the chip to stretch its legs while running games lol.
> 
> (EDIT) made the wife turn around just so i could go (get something) try this...
> got PER CORE CO, which is some random as* shi* i just put in, but none the less it worked...
> with a +.0375 offset since when i set .40mv my pc starting DING DONG (windows doing this for some reason)
> like it was telling me something without any error, any messages etc.
> i think CO was, -23,-17,-22,-27,-27,-17 something like that. will dial it in (after i get back from vacation)
> since were already supposed to be in toledo to meet up with her gf etc...
> 
> anyhow, i swapped the timings you mentioned as well, this is what i got (will update after i get it ina moment)
> View attachment 2482714


Nono get that 3090 if you can 


Spoiler: Overboost but not really overboost ?

















Spoiler: lowest CO ~ TM5 fullspeed example














if it's by point 1 or point 2 off, you're still missing a bit of negative CO or push too much vcore 


craxton said:


> I thought that dual CCD were supposed to be better lol ?
> 
> 
> _frame_ said:
> 
> 
> 
> *@domdtxdissar *has proven on a previous page that if 1 CCD is disabled then there is no 2 ns penalty. I guess you do not have this 2 ns penalty... But the dram calc result is strange!
Click to expand...

I was looking back to


http://imgur.com/a/PNZBEGD

 from exactly him
It's unsure how much to trust SafeMode results when the lack of any powermanagement
But this 2ns penalty i've heard for several times now

I didn't mean voltage penalty or FCLK penalty

Although researching further yesterday, the issue gets more and more strange
The stock powerplan and sleep states are messed up - DF & C-States together with dLDO_Injection

Stock powerplans current one that come installed via chipset update, have an infinite boost limit, after waking up from suspended cores
Usually what i utilized as little boost and exploit by "accident" (as my powerplans had a 5100/5200Mhz boost limit)
apparently is a big issue and causes overboosting
If it bugs out , it even reaches beyond 1 CCD write bandwidth for me








33620 MB/s being maximum possible on 1 CCD @ 4200MT/s
while this overboost it throttled back by the sample (if stability is kept up)

It randomly boosts to 200 ACPI value, which equal about 5ghz
160-165 sustained is what my 4.85 boost @ allcore SSE loads reaches
Controlled via a powerplan , it wont exceed 200 Peaks (picture above)
but on the stock powerplan and with enabled DF-C_States, it peaks 8500 ACPI Value, readable as 44ghz back then when CTR had a bug with Package C6 states

What 1usmus struggled and worked on to fix, i clearly can feel
because once it overboosts and throttles - i only can stay in the 49.5-49.8ns range
But if it doesn't throttle and everything including the powerplan works how it should ~ then it stays at 48.7-48.8ns

Sadly this behavior changes between C, DF and 4G mode + powerplans
Something is strongly broken for sure here , and the stock powerplans do not suspend cores fully




craxton said:


> thought what i shared there, was all cores/threads boosting the same?
> 
> am i missing something in hwinfo lol?
> 
> (re-edited) that post above, dram calc score got worse, is this normal with CO


The first picture you shared sadly still had throttling issues and a not correct CO
they have to hold it at perfect fullspeed like shown above 
They will lose speed if you give it too much added positive vCore
or if negative CO is not enough

they will throttle only because of EDC, but they will throttle
negative CO and positive vcore for stability help this
Sadly you are far away & i can not predict why it fails on your side. It just looks unbalanced according to HWInfo.
Cores are not reaching their correct boostt


mackbolan said:


> Adding my 2 cents too. I noticed all these "proof" shots on the spreadsheet have these tests I pass but yet still have WHEA in the "Event Viewer". No one posts the pic of the Windows "Event Viewer"/ "System" to prove there was actually no WHEA. Even OCCT misses them unless it's truly a crappy RAM timing. Like HWiNFO showed me having WHEA's when I tried some ridiculous RAM timings that also failed DRAM Calc. For instance, I plugged in my pre-set for "stable" 4000/2000 that has @craxton 's settings in it (running 2 X 8GB , not 4 like him but it works). I have no errors, hangs, games run good, but it tosses WHEA 19's like no tomorrow in "Event Viewer" when a RAM test is run where it shows no error and passing.


HWInfo, OCCT and CTR do instantly report errors if they see it in the log
Some people want to hide it, others have it open since the starrt
but even if they where before, OCCT Extreme AVX2 , should instantly cause them to appear
I spend a whole day redoing TM5 for the 5th time and adjusting voltages , till OCCT didn't cause random reboots ~ just to get a full picture, as people would question

There where no WHEA anywhere, yet OCCT broke voltage stability
But i can see your point - and the spread sheet certainly should not accept Safe Mode results without active drivers and without powermanagement
As this is very far away of replicable on windows usable performance 

===========================

@PJVol & @infraredbg another reason that i have a 16 core
Check ACPI Event ID ~ number 55


Spoiler






Code:


Processor 0 in group 0 exposes the following power management capabilities:
Idle state type: ACPI Idle (C) States (1 state(s))

Performance state type: ACPI Collaborative Processor Performance Control
Nominal Frequency (MHz): 3693
Maximum performance percentage: 133
Minimum performance percentage: 46
Minimum throttle percentage: 15

Processor 1 in group 0 exposes the following power management capabilities:
Idle state type: ACPI Idle (C) States (1 state(s))

Performance state type: ACPI Collaborative Processor Performance Control
Nominal Frequency (MHz): 3701
Maximum performance percentage: 133
Minimum performance percentage: 46
Minimum throttle percentage: 15

Processor 2 in group 0 exposes the following power management capabilities:
Idle state type: ACPI Idle (C) States (1 state(s))

Performance state type: ACPI Collaborative Processor Performance Control
Nominal Frequency (MHz): 3693
Maximum performance percentage: 137
Minimum performance percentage: 46
Minimum throttle percentage: 15

Processor 3 in group 0 exposes the following power management capabilities:
Idle state type: ACPI Idle (C) States (1 state(s))

Performance state type: ACPI Collaborative Processor Performance Control
Nominal Frequency (MHz): 3701
Maximum performance percentage: 137
Minimum performance percentage: 46
Minimum throttle percentage: 15

Processor 4 in group 0 exposes the following power management capabilities:
Idle state type: ACPI Idle (C) States (1 state(s))

Performance state type: ACPI Collaborative Processor Performance Control
Nominal Frequency (MHz): 3693
Maximum performance percentage: 140
Minimum performance percentage: 46
Minimum throttle percentage: 15

Processor 5 in group 0 exposes the following power management capabilities:
Idle state type: ACPI Idle (C) States (1 state(s))

Performance state type: ACPI Collaborative Processor Performance Control
Nominal Frequency (MHz): 3701
Maximum performance percentage: 140
Minimum performance percentage: 46
Minimum throttle percentage: 15

Processor 6 in group 0 exposes the following power management capabilities:
Idle state type: ACPI Idle (C) States (1 state(s))

Performance state type: ACPI Collaborative Processor Performance Control
Nominal Frequency (MHz): 3693
Maximum performance percentage: 129
Minimum performance percentage: 46
Minimum throttle percentage: 15

Processor 7 in group 0 exposes the following power management capabilities:
Idle state type: ACPI Idle (C) States (1 state(s))

Performance state type: ACPI Collaborative Processor Performance Control
Nominal Frequency (MHz): 3701
Maximum performance percentage: 129
Minimum performance percentage: 46
Minimum throttle percentage: 15




And also


Spoiler














It very well shows that it's a dual CCD 8 core
strangely i can only keep up stability with PBO or CTR
when i assigns the correct load
An allcore would trigger load on all of the 16 cores ~ and at best thermal shutdown
if not even voltage shutdown 

2nd CCD according to RMSU is permanently active and sleeping ~ but not hibernated
It just doesn't get any load, as ACPI only assigns a core layout from 0-11, while 12-31 are unused and free
Microcode needs spoofing soo reads it as 5950X and not 5600X how it should be
I looked but couldn't figure out what to spoof yet, as they look identical on close to everything


Spoiler














Also good morning guys ☕


----------



## Veii

hyroglyphixs said:


> tRC, tFAW, tRRDS and tRRDL are all not matching the XMP profile, is this normal?


GDM on does autocorrect on the first stage tCK, tWR, tRTP
on the 2nd stage it's the first 5 primaries that are rounded up ~ if it decides that it missmatches
GDM is 2.5T not 1.5T

Try to be GDM off 2T stable at first , till you have your CAD_BUS and RTT settings correct to power your dimms well


craxton said:


> so, thankyou for pointing out my timing errors, care to tell if these are correct? ill stress test later.
> 
> (edit #3) im not looking to change rtt, or cad_bus strengths. if i set to
> what you mention to the others with single rank 4x8 dimms then i have way WAY to many issues
> trying to counter. but, seeing how i have no signs of instability issues, id have to assume there
> what my board/sticks wishes to have, i probably could adjust but thats a headache trying to balance


Hmm, you really can start to focus on going CL15-15-15
Maybe similar to my timings with high tRRD & tWTR 
don't forget 4x8 or 2x16 need tRDC_RD / 2 + 2 = tRDWR
~ with added tWRRD delay up to SCL state
* optionally you can run +1 instead of +2 but this needs every other timing to be aligned

Else you can test if RTT_WR /2 & maybe that + RTT_NOM /5 , breaks everything for you
(instability by them will be shown instantly on Error 1,11,10,6,15 ~ or full refusal to post at all)
And you can check if CsOdtDrvStr, 30ohm ~ causes instability on your current set & maybe if you get RTT_WR /2 to work, haha

It looks fine tbh, but it makes more sense to lower primaries and increase the delay between Read and between Write
tRRD & tWTR
instead of slowing down the main operation on the primaries


----------



## Sleepycat

hyroglyphixs said:


> Gotcha, thanks! I'm having such a hard time finding stability, I'm actually currently running TM5 Anta trying 3600 CL16 XMP settings for the G Skill B Die kit (I have the 3200 CL14 G Skill B Die kit) and I entered in the XMP 16-16-16-16-36 1.35V, plus the tRC, tFAW, tRRDS and tRRDL and everything else on auto.. hopefully this will work


I have the same kit as yours, but I am running 4x16GB. The B-die kits sometimes need a bit more voltage to get better stability as it also depends on your motherboard layout (even though they are the same daisy chain topology).

Don't be afraid to bump up your DIMM voltage to 1.4V. This is what I can achieve with 4x16GB. So if you are running 2x16GB or 4x8GB, you can go way faster and tighter than my timings.

My DIMM voltage is 1.46V and VSOC is 1.09V.


----------



## KedarWolf

mackbolan said:


> Adding my 2 cents too. I noticed all these "proof" shots on the spreadsheet have these tests I pass but yet still have WHEA in the "Event Viewer". No one posts the pic of the Windows "Event Viewer"/ "System" to prove there was actually no WHEA. Even OCCT misses them unless it's truly a crappy RAM timing. Like HWiNFO showed me having WHEA's when I tried some ridiculous RAM timings that also failed DRAM Calc. For instance, I plugged in my pre-set for "stable" 4000/2000 that has @craxton 's settings in it (running 2 X 8GB , not 4 like him but it works). I have no errors, hangs, games run good, but it tosses WHEA 19's like no tomorrow in "Event Viewer" when a RAM test is run where it shows no error and passing.
> 
> I'm really interested to see people's "Event Viewer", like I posted one with redacted system name, showing my WHEA history. That would be true proof that these 3800/1900's and 4000/2000 runners are really error free. Even @craxton said he turns off every non-essential service to benchmark. While that's nice so one can pass a test, I think most of us are looking for daily 24/7 type stability.
> 
> So if I'm correct and no one can post a clean "Event Viewer" log, running any one of these RAM tests, one can't be positive that the PC is indeed WHEA free. The only no clean "Event Viewer" screen shots I can post happen with 3733/1866 after the 1.2.0.1 update or 3600/1800. Any other higher setting is a WHEA fest with any timing, any voltage but appears stable and passes all these tests that are being shown as "proof" of stability.
> 
> I'm WHEA free now but load this up with a game or RAM test and the WHEA 19's flow. The game will run fine for hours, no hitch but I noticed post gamer it will not open the window for AMD Radeon from the task bar to full screen. Everything else is fine. Run another game, surf the web, etc. No issue. check in "Event Viewer" and anything other than surfing, watching a movie, will result in WHEA 19 using 4000/2000.
> 
> I noticed some people posting "proof" where they must be using only one core active or serious LN2 to hit 5Ghz on a 5600X consistently. One ran in safe mode with 1 CCX disabled to achieve the score. Neither is proving a 24/7 stable system. None have a screen shot of "Event Viewer" where hidden WHEA's go. Some are using higher BLCK to overcome FCLK limits, would be nice to hear how to do it without making it so your drives still work and GPU. How far can one go? I'm thinking possibly to 102 before a serious issue.
> 
> Researching it just seems some are stretching more than clocks and don't want to look in "Event Viewer", call it clean after many RAM tests pass and no BSOD's. Because mine will pass all these tests fine but the Windows log doesn't lie. If error 19 doesn't matter there, then I've been stable at several speeds. All this is regarding results from the 5600X and running higher than 1866 IF without a WHEA 19. Sure, 5900X or 5950X have a much better chance at the very elusive 1900 or 2000 IF. The 5600X and 5800X are not so lucky, IMHO.
> 
> Prove me wrong and post some Windows logs that show no WHEA 19's. I'm not even saying people are purposely evading the truth, they assume by these test results there is no WHEA. I bet there's a very small handful of people that have a 5600X or 5800X that have clean logs running normal with a 1900 or 2000 IF in 1:1:1 and a medium sized with a 5900x or higher.
> 
> In any case, if you're claiming no WHEA 19 and you have them in the Windows Event Viewer, you're fooling yourself and some people hoping to find the "unicorn". Many will keep chasing after 3800/1900 or 4000/2000 because it seems like nearly all on here can achieve that. However, if the passing standard is providing the results from TM5, HCi, DRAM Calc, y cruncher, etc., showing zero errors found, then I should be posting my results as well. The real proof would look like this pic but error free, so the time/date match the rest. You can see my DRAM Calc shows no errors.
> View attachment 2482741
> View attachment 2482743


I ran OCCT for an hour, my Windows log. It had zero WHEAs before I cleared it for OCCT as well.


----------



## hyroglyphixs

Veii said:


> GDM on does autocorrect on the first stage tCK, tWR, tRTP
> on the 2nd stage it's the first 5 primaries that are rounded up ~ if it decides that it missmatches
> GDM is 2.5T not 1.5T
> 
> Try to be GDM off 2T stable at first , till you have your CAD_BUS and RTT settings correct to power your dimms well





Sleepycat said:


> I have the same kit as yours, but I am running 4x16GB. The B-die kits sometimes need a bit more voltage to get better stability as it also depends on your motherboard layout (even though they are the same daisy chain topology).
> 
> Don't be afraid to bump up your DIMM voltage to 1.4V. This is what I can achieve with 4x16GB. So if you are running 2x16GB or 4x8GB, you can go way faster and tighter than my timings.
> 
> My DIMM voltage is 1.46V and VSOC is 1.09V.
> 
> View attachment 2482785


Thanks guys, I might give it another shot this weekend. Already spent 3 days trying to figure this out, this is the last result before I "gave up".

View attachment 2482646


Pretty loose timings overall, but I was still getting errors out the wazoo..

Currently using the primaries from the 3600CL16-16-16-36 kit with everything else on auto and I finally got some stability. I've lost a lot of hair over this for sure.. I'm not too sad about the small performance gains I've lost out on but I do get envious when I see people with same hardware (5900x, B550 Unify X, 2x16 B die) get to 3800/4000 MHz with 2:1 FLCK, and when I try their settings, I can't even post


----------



## domdtxdissar

hyroglyphixs said:


> View attachment 2482646
> 
> Pretty loose timings overall, but I was still getting errors out the wazoo..


Pretty sure tCWL12 is the problem there.. If you wanna give it a other try i suggest sticking to tCWL14. (tCL = tCWL if you dont want to use much higher Vdimm)


----------



## GribblyStick

@Veii 
Ok I tried running off DF C-states and global C-states, but if it makes any difference at all, the results are maybe a bit worse.
Especially on the write speeds, though globally the results I got are about the same.



Spoiler: Current config (not final)



VDIMM 1,5
CPU VDDP 0,855
CLDO VDDP 0,850
CCD 0,850
IOD 1,050
SOC 1,100

Regular formulas
tRAS= tCL + tRP
tRC= tRAS+tRC
tWR= tRAS - tRCD
tRTP= tWR/2
tRRDS as low as possible
tRRDL > tRRDS, set to 6 to stay even
tFAW= 4 x tRRDS
tWTRS as low as possible
tWTRL = tRRDL+2
tRFC = (5 * tRC) + 8
t..SCLI just left at 5
tCWL I left at 14
tRDWR= (tRCD / 2) +2
tWRRD= X * SCL so I set it the same as SCL
couldn't find any formula on the other RDRD/WRWR settings so I went with Veiis 1/5/5 .. 1/7/7
tcke= 9 with setup 3/3/15
proc ODT I just left as is
RTT set to 7/0/5
CADBUS changed to 40/20/20/20

1T is better, but only runs in GDM on with these settings.


----------



## Alyjen

mackbolan said:


> Adding my 2 cents too. I noticed all these "proof" shots on the spreadsheet have these tests I pass but yet still have WHEA in the "Event Viewer". No one posts the pic of the Windows "Event Viewer"/ "System" to prove there was actually no WHEA. Even OCCT misses them unless it's truly a crappy RAM timing. Like HWiNFO showed me having WHEA's when I tried some ridiculous RAM timings that also failed DRAM Calc. For instance, I plugged in my pre-set for "stable" 4000/2000 that has @craxton 's settings in it (running 2 X 8GB , not 4 like him but it works). I have no errors, hangs, games run good, but it tosses WHEA 19's like no tomorrow in "Event Viewer" when a RAM test is run where it shows no error and passing.
> 
> I'm really interested to see people's "Event Viewer", like I posted one with redacted system name, showing my WHEA history. That would be true proof that these 3800/1900's and 4000/2000 runners are really error free. Even @craxton said he turns off every non-essential service to benchmark. While that's nice so one can pass a test, I think most of us are looking for daily 24/7 type stability.
> 
> So if I'm correct and no one can post a clean "Event Viewer" log, running any one of these RAM tests, one can't be positive that the PC is indeed WHEA free. The only no clean "Event Viewer" screen shots I can post happen with 3733/1866 after the 1.2.0.1 update or 3600/1800. Any other higher setting is a WHEA fest with any timing, any voltage but appears stable and passes all these tests that are being shown as "proof" of stability.
> 
> I'm WHEA free now but load this up with a game or RAM test and the WHEA 19's flow. The game will run fine for hours, no hitch but I noticed post gamer it will not open the window for AMD Radeon from the task bar to full screen. Everything else is fine. Run another game, surf the web, etc. No issue. check in "Event Viewer" and anything other than surfing, watching a movie, will result in WHEA 19 using 4000/2000.
> 
> I noticed some people posting "proof" where they must be using only one core active or serious LN2 to hit 5Ghz on a 5600X consistently. One ran in safe mode with 1 CCX disabled to achieve the score. Neither is proving a 24/7 stable system. None have a screen shot of "Event Viewer" where hidden WHEA's go. Some are using higher BLCK to overcome FCLK limits, would be nice to hear how to do it without making it so your drives still work and GPU. How far can one go? I'm thinking possibly to 102 before a serious issue.
> 
> Researching it just seems some are stretching more than clocks and don't want to look in "Event Viewer", call it clean after many RAM tests pass and no BSOD's. Because mine will pass all these tests fine but the Windows log doesn't lie. If error 19 doesn't matter there, then I've been stable at several speeds. All this is regarding results from the 5600X and running higher than 1866 IF without a WHEA 19. Sure, 5900X or 5950X have a much better chance at the very elusive 1900 or 2000 IF. The 5600X and 5800X are not so lucky, IMHO.
> 
> Prove me wrong and post some Windows logs that show no WHEA 19's. I'm not even saying people are purposely evading the truth, they assume by these test results there is no WHEA. I bet there's a very small handful of people that have a 5600X or 5800X that have clean logs running normal with a 1900 or 2000 IF in 1:1:1 and a medium sized with a 5900x or higher.
> 
> In any case, if you're claiming no WHEA 19 and you have them in the Windows Event Viewer, you're fooling yourself and some people hoping to find the "unicorn". Many will keep chasing after 3800/1900 or 4000/2000 because it seems like nearly all on here can achieve that. However, if the passing standard is providing the results from TM5, HCi, DRAM Calc, y cruncher, etc., showing zero errors found, then I should be posting my results as well. The real proof would look like this pic but error free, so the time/date match the rest. You can see my DRAM Calc shows no errors.
> View attachment 2482741
> View attachment 2482743


This was my case and that's why I settled for 3733CL14 rather than 3800CLanything. IF 1900, eventually, sometimes after few days it'd register a WHEA 19 warning, single one, at random occasions, so it was not like "I game or stress and I get errors" but they were there. I gave up and tuned my IF1866 settings, it has been months since I did that and 0 whea errors.


----------



## Veii

hyroglyphixs said:


> Thanks guys, I might give it another shot this weekend. Already spent 3 days trying to figure this out, this is the last result before I "gave up".
> 
> View attachment 2482646
> 
> 
> Pretty loose timings overall, but I was still getting errors out the wazoo..
> 
> Currently using the primaries from the 3600CL16-16-16-36 kit with everything else on auto and I finally got some stability. I've lost a lot of hair over this for sure.. I'm not too sad about the small performance gains I've lost out on but I do get envious when I see people with same hardware (5900x, B550 Unify X, 2x16 B die) get to 3800/4000 MHz with 2:1 FLCK, and when I try their settings, I can't even post


It's A LOT , of work 
It looks easy when the result is "just stable"








Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com




Check the DATA page for information on what each error means
it's average, but i think quite useful


GribblyStick said:


> @Veii
> Ok I tried running off DF C-states and global C-states, but if it makes any difference at all, the results are maybe a bit worse.
> Especially on the write speeds, though globally the results I got are about the same.
> 
> 
> 
> Spoiler: Current config (not final)
> 
> 
> 
> VDIMM 1,5
> CPU VDDP 0,855
> CLDO VDDP 0,850
> CCD 0,850
> IOD 1,050
> SOC 1,100
> 
> Regular formulas
> tRAS= tCL + tRP
> tRC= tRAS+tRC
> tWR= tRAS - tRCD
> tRTP= tWR/2
> tRRDS as low as possible
> tRRDL > tRRDS, set to 6 to stay even
> tFAW= 4 x tRRDS
> tWTRS as low as possible
> tWTRL = tRRDL+2
> tRFC = (5 * tRC) + 8
> t..SCLI just left at 5
> tCWL I left at 14
> tRDWR= (tRCD / 2) +2
> tWRRD= X * SCL so I set it the same as SCL
> couldn't find any formula on the other RDRD/WRWR settings so I went with Veiis 1/5/5 .. 1/7/7
> tcke= 9 with setup 3/3/15
> proc ODT I just left as is
> RTT set to 7/0/5
> CADBUS changed to 40/20/20/20
> 
> 1T is better, but only runs in GDM on with these settings.
> 
> View attachment 2482806
> View attachment 2482804


I have something interesting to share soon - something to abuse with DF states
for now DF states should be disabled 
You can use overboost to your favor
With DF States utilizing all boost possible


Spoiler














Without DF states, if it's too unstable for some


Spoiler














More information in couple of days 🚀
Currently it's a bit too explosive and causes issues for CTR users


----------



## Veii

hyroglyphixs said:


> Thanks guys, I might give it another shot this weekend. Already spent 3 days trying to figure this out, this is the last result before I "gave up".
> 
> View attachment 2482646
> 
> 
> Pretty loose timings overall, but I was still getting errors out the wazoo..
> 
> Currently using the primaries from the 3600CL16-16-16-36 kit with everything else on auto and I finally got some stability. I've lost a lot of hair over this for sure.. I'm not too sad about the small performance gains I've lost out on but I do get envious when I see people with same hardware (5900x, B550 Unify X, 2x16 B die) get to 3800/4000 MHz with 2:1 FLCK, and when I try their settings, I can't even post


Balancing issues








But both of your issues say "timeout issue, lack of voltage or resistance"
This should be better for the start


----------



## Flash1228

After (a lot) of trial and error I got GDM 2T stable. tRFC seems to cap out around 285-290ns and tRC I can boot 54 with errors, but any lower and gotta reset CMOS. Any other suggestions?


----------



## Veii

Flash1228 said:


> After (a lot) of trial and error I got GDM 2T stable. tRFC seems to cap out around 285-290ns and tRC I can boot 54 with errors, but any lower and gotta reset CMOS. Any other suggestions?
> 
> View attachment 2482830
> View attachment 2482831


These timings by cm87 where good for Rev.E 









Please compare how they perform
i think your RTTs are good , way better than RTT_PARK 1

Also good job !
Finally you can start to work with awkward experimental timings


----------



## hyroglyphixs

Veii said:


> It's A LOT , of work
> It looks easy when the result is "just stable"
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Check the DATA page for information on what each error means
> it's average, but i think quite useful


I've been using this, this is a great resource, thanks for working on it 



Veii said:


> Balancing issues
> 
> 
> 
> 
> 
> 
> 
> 
> But both of your issues say "timeout issue, lack of voltage or resistance"
> This should be better for the start


I'll be sure to try those, thanks!


----------



## Veii

hyroglyphixs said:


> I've been using this, this is a great resource, thanks for working on it
> 
> 
> 
> I'll be sure to try those, thanks!


If tWRRD 5 fails, 4 will work 
If CAD_BUS 40-20-30-20 fails, 60-20-20-24 will work 
If you still have random issues , for example error 11 or 1 - then give tRTP 14 a shot (half of tWR)
and if you still won't get error 1 or then maybe 10 away,you have to increase tRRD & tWTR (no way around it)
or just increase VDIMM +1 

If you Error 0,10,6,1 (#1 together with the rest) then you need to change RTT or CAD_BUS (both likely)


----------



## jcpq

Is it possible to improve anything in my configuration?


----------



## hyroglyphixs

Veii said:


> If tWRRD 5 fails, 4 will work
> If CAD_BUS 40-20-30-20 fails, 60-20-20-24 will work
> If you still have random issues , for example error 11 or 1 - then give tRTP 14 a shot (half of tWR)
> and if you still won't get error 1 or then maybe 10 away,you have to increase tRRD & tWTR (no way around it)
> or just increase VDIMM +1
> 
> If you Error 0,10,6,1 (#1 together with the rest) then you need to change RTT or CAD_BUS (both likely)












Something is strange though, I even checked twice and tWR is for sure 28 in the BIOS..

And according to 13 it's most likely voltage related, I'll bump up VDIMM slightly and change my tCWL to 14 like @domdtxdissar mentioned


----------



## Veii

hyroglyphixs said:


> View attachment 2482847
> 
> 
> Something is strange though, I even checked twice and tWR is for sure 28 in the BIOS..
> 
> And according to 13 it's most likely voltage related, I'll bump up VDIMM slightly and change my tCWL to 14 like @domdtxdissarn mentioned


ZenTimings reads what the bios sets
it's strange
Will tWR 14 post at all ?
also try tWRRD 4 afterwards


----------



## Bojamijams

Veii said:


> These timings by cm87 where good for Rev.E
> View attachment 2482842
> 
> 
> Please compare how they perform
> i think your RTTs are good , way better than RTT_PARK 1
> 
> Also good job !
> Finally you can start to work with awkward experimental timings


Isn't tRAS = tCL + tRCDRD + x? That tRAS is too low even without the +x? 

I've read +2 and +4 for tRAS. For my Rev.E 4x8 config on a 5900x, +2 gives worse scores than +4 in latency


----------



## hyroglyphixs

Veii said:


> ZenTimings reads what the bios sets
> it's strange
> Will tWR 14 post at all ?
> also try tWRRD 4 afterwards












I'll lower VDIMM back down and try what you suggested, thanks for the help!


----------



## Veii

hyroglyphixs said:


> View attachment 2482849
> 
> 
> I'll lower VDIMM back down and try what you suggested, thanks for the help!


6 & 12 are powering issues, which are also voltage issues
You can try if tCKE 6 / 7 will resolve this


----------



## nada324

Hey, @Veii got viper SR 2x8 16 but i get such " high " latency results, i couldnt get trcdrd to 15 no matter what i did

Thank you!!


----------



## Veii

nada324 said:


> Hey, @Veii got viper SR 2x8 16 but i get such " high " latency results, i couldnt get trcdrd to 15 no matter what i did
> 
> Thank you!!
> 
> View attachment 2482851


Tested 20min ago








Both options work
But 6-3-6 are better RTTs than 706
Just require tCKE and CAD_BUS SETUP time
They do not work with 40-20-30-20
14-14-14 needs for me 1.56v, on 633 or 1.58v on 706
15-15-15 needs exactly 1.52v but your timings are messy
Don't go tCWL=tCL -2 when you don't have the rest figured out 

Your cLDO_VDDP is too high, 900mV is all you need
VDDG CCD on this frequency can be either 940mV or 1030 (depends how high you want to push SOC ~ lower CCD higher SOC)
VDDG IOD for this frequency is enough as 980mV, but i run 1100 from my 2100 FCLK set

procODT 34 is enough for 3800, but you can run 36 there too till 2100FCLK
If you have access to CPU VDDP, get it down to 880mV or 860mV - 900mV at worst. Stock is 930mV which is bad


----------



## hyroglyphixs

Well, time for me to start working 

I'll try and tune some more this weekend! Thanks again


----------



## Veii

Bojamijams said:


> Isn't tRAS = tCL + tRCDRD + x? That tRAS is too low even without the +x?
> 
> I've read +2 and +4 for tRAS. For my Rev.E 4x8 config on a 5900x, +2 gives worse scores than +4 in latency


You are not wrong - kinda
tRAS has nothing to do with tCL, except for when you use tCL+ both tRCDs /3 - orr also tRCD *2 + tBURST
There are exceptions for tRAS lower than tRCD * 2 without tBURST need
but according to JEDEC , it's tRCD *2 + tBL (4 or 8) , on XMP profiles


hyroglyphixs said:


> View attachment 2482855
> 
> View attachment 2482857
> 
> View attachment 2482858
> 
> 
> Well, time for me to start working
> 
> I'll try and tune some more this weekend! Thanks again


11 & 2 are very fun ones, 1 & 11 are annoying "fun" ones
2 is a timeout issue , mostly overlapping timings issue
Try tRDWR 10 on the tWR 14 set
and maaybe see if SCL 3 passes with tWRRD 3

You'll have much fun getting 2 and 11 away 
if nothing helps , increase tRRD_L +1 and add +1 on tWRWR SD & DD, but decrease tRDRD SD & DD -1 (soo a difference of 4 is there instead of 2)


----------



## nada324

Veii said:


> Tested 20min ago
> 
> 
> 
> 
> 
> 
> 
> 
> Both options work
> But 6-3-6 are better RTTs than 706
> Just require tCKE and CAD_BUS SETUP time
> They do not work with 40-20-30-20
> 14-14-14 needs for me 1.56v, on 633 or 1.58v on 706
> 15-15-15 needs exactly 1.52v but your timings are messy
> Don't go tCWL=tCL -2 when you don't have the rest figured out
> 
> Your cLDO_VDDP is too high, 900mV is all you need
> VDDG CCD on this frequency can be either 940mV or 1030 (depends how high you want to push SOC ~ lower CCD higher SOC)
> VDDG IOD for this frequency is enough as 980mV, but i run 1100 from my 2100 FCLK set
> 
> procODT 34 is enough for 3800, but you can run 36 there too till 2100FCLK
> If you have access to CPU VDDP, get it down to 880mV or 860mV - 900mV at worst. Stock is 930mV which is bad


No luck for me haha


----------



## Not a redditor

Vdram 1.55 for stability
vSoc 1175 for cpu oc so i can lower voltage to cpu 
blk 100.05 

any suggestion from this point ?


----------



## Bonevi

Hello, I have a pretty strange behavior in my system and hope someone might have and idea. Here is the system:








The memory is PVS432G360C8K with Samsung A-die. I am unable to get over 3533, but that might be explained by the 1.27V memory voltage. What is strange is that this is the most stable voltage. Increasing or reducing it makes the memory less stable. If I use 1.31V I get BSOD, if I put 1.33V I cannot even boot into Windows. I have not played with the timings, these are on auto as I was hoping to see where the frequency can go first, but without increasing the voltage this seems to be the maximum. I've played with VSOC, VDDP, CDD and IOD, but no matter what increasing the VDIMM makes things more unstable. Does anyone know what I might be missing?


----------



## Br3ach

Not a redditor said:


> any suggestion from this point ?


Well, for starters, stress test it for at least 3 hours, e.g. 25 1usmus TM5 runs, I would say. There are errors which only show up after a couple of hours (unfortunately)... Then again, it depends on your stability tolerance levels. Otherwise looks good, you may want to tighten tRTP a bit more, also in my case tRDRDSD / tWWRWRSD / _SCLs can go lower, but that's against the advice here... anyway, don't think it'll make a huge difference. tCWL 14 / tRDWR 8 / tWRRD 3 may be better.

Another edit: Also, this latency is way to high - I assume because you have apps running, measure on a clean boot - you should be in the lower 50s.


----------



## Flash1228

Veii said:


> These timings by cm87 where good for Rev.E
> View attachment 2482842
> 
> 
> Please compare how they perform
> i think your RTTs are good , way better than RTT_PARK 1
> 
> Also good job !
> Finally you can start to work with awkward experimental timings


First, thanks for your help/suggestions!

Had to bump voltage up to 1.43 to be able to boot, but with the those settings I'm on cycle 10 of 1usmus testmem5 without errors so far. I can't for the life of me get into Windows on 1T with these settings or previous. Furthest I can get is Windows login and then BSOD.


----------



## Not a redditor

Br3ach said:


> Well, for starters, stress test it for at least 3 hours, e.g. 25 1usmus TM5 runs, I would say. There are errors which only show up after a couple of hours (unfortunately)... Then again, it depends on your stability tolerance levels. Otherwise looks good, you may want to tighten tRTP a bit more, also in my case tRDRDSD / tWWRWRSD / _SCLs can go lower, but that's against the advice here... anyway, don't think it'll make a huge difference. tCWL 14 / tRDWR 8 / tWRRD 3 may be better.
> 
> Another edit: Also, this latency is way to high - I assume because you have apps running, measure on a clean boot - you should be in the lower 50s.


its a 3950x not a 5950x


----------



## Dasa

Not a bad start for the new 4400c19 A0 kit 3771 14-15-1T ~1.48v










Edit: Spoke to soon error 14 at 28min and error 10 at 30min with most timings on auto it is possible something other than the primary's or 1T is the reason for the error.
Edit: Nudged vdimm up a notch and 35 min so far so good.


----------



## GribblyStick

@Veii

Tried pushing voltages with CL14 since it boots, but even pushing VDIMM to 1,56 TM5 spams error 6.
The XMP profile is rated for 4000 at CL15 with 1,5, so 1,56 on 3800 should be more than enough no? 
I've seen people keeping CL16 while lowering the other primaries for very similar results though, while keeping a lower Voltage.
Is there any particular ratio to respect with asynchronous primaries like that?



Spoiler: C14 Test












Tried ClkDrvStr at 60 too


----------



## Dasa

Currently testing my 4x3200c14 sticks individually and TM5 spamming error six seems to happen when tRCD is overly tight and extra vdimm doesn't seem to help although I haven't really pushed it.
So far I know that one stick can only do tRCD [email protected]/s

Currently testing another two sticks which together can do tCL 15 tRCD 16.
Alone one seems to be doing 14-16 so far but doesn't like 15-15.
So I am guessing the other will top out at 15-15 or 15-16 when tested alone.

Edit: Ok found how tight each can go at 3771 ~1.49-1.5v reported 1.47v set
Flare X 3200c14
S1 14-16 1.5v
S2 15-16 1.5v error at c14

Rimjaws V 3200c14
S1 15-16 1.5v bsod on boot at c14
S2 15-16 1.5v heaps of errors in TM5 so this is the 15-17 stick


----------



## nada324

Dasa said:


> Currently testing my 4x3200c14 sticks individually and TM5 spamming error six seems to happen when tRCD is overly tight and extra vdimm doesn't seem to help although I haven't really pushed it.
> So far I know that one stick can only do tRCD [email protected]/s
> 
> Currently testing another two sticks which together can do tCL 15 tRCD 16.
> Alone one seems to be doing 14-16 so far but doesn't like 15-15.
> So I am guessing the other will top out at 15-15 or 15-16 when tested alone.
> 
> Edit: Ok found how tight each can go at 3771 ~1.49-1.5v reported 1.47v set
> Flare X 3200c14
> S1 14-16 1.5v
> S2 15-16 1.5v error at c14
> 
> Rimjaws V 3200c14
> S1 15-16 1.5v bsod on boot at c14
> S2 15-16 1.5v heaps of errors in TM5 so this is the 15-17 stick


Yeah have same problem as you, seems that we dont have "good bin of b die".











If i put TRCDRD to 15 it doesnt like it, even at 1.58v dimm.


----------



## Veii

I see the same errors over and over again, do you guys even try 
I can't resolve them without more work from you - am no magician
Don't just give up on the first or 2nd set of errors
4200C15-15 == 3800C13-13 didn't work instantly - neither do i have even remotely good dimms
It required 12h of error fixing
You guys have soo much better setups but give up on the first or 2nd failure , come on 

11 & 2 go together , 6 is a powering issue, which also can be tCKE or voltage related
It relates to Error 0 which are PCB crashes or some type of timeout . Overall a catastrophic failure if you get it
Soo you either lack voltage or something else bothers
Error 6 can also be IMC related which is usually what should be confirmed first with y-crucher
Stability on all selected (not stock) tests @ 4 loops

tFAW 15 has no pattern on anything @nada324
It is neither 1x tFAW (which need tRAS+1 = tRC & a lot of tRDWR delay)
And it also isn't 4* tRRD_S = Forth ACTIVE timewidow (4* tRRD_S) ~ (tFAW)

@GribblyStick 14-14-14 can need between 1.48-1.56v , sometimes 1.58v
It should need about the same voltage as 3200C11-11-11 (it's not easy to run)
I only see low tRRD & low tWTR
In comparison









Needed tRRD_S that high and tRFC that high
Give your best, this so far is not your bet 
Error 6 is the same thing, "badly powered or catastrophic timeout"

More errors won't always mean it gets worse
6 & 0 need to be gone
1 & 11 are tRRDs , tWTR or tRDWR / tWRRD issues

3800C14-14 are perfectly possible - you just need to shift tertiaries higher
Lower primaries have a higher priority and do more changes 
For 16Gb dimms, use the google spreadsheet the big calculator on tRFC2 = B2 mode (higher capacity)
else higher density dimms need higher tRRD, tWTR, a bit more tWR, and a bit more tRP + more tRFCns

The rest is pretty much identical and the failure on 4 dimm setups is mostly the bad layout/sorting
Good dimms need to be on the slave set, which can work at lower voltage (user binning required)
Worse sets, need to sit at the main slots, as they get more current ~ thanks to the daisy chain layout


----------



## nada324

Veii said:


> I see the same errors over and over again, do you guys even try
> I can't resolve them without more work from you - am no magician
> Don't just give up on the first or 2nd set of errors
> 4200C15-15 == 3800C13-13 didn't work instantly - neither do i have even remotely good dimms
> It required 12h of error fixing
> You guys have soo much better setups but give up on the first or 2nd failure , come on
> 
> 11 & 2 go together , 6 is a powering issue, which also can be tCKE or voltage related
> It relates to Error 0 which are PCB crashes or some type of timeout . Overall a catastrophic failure if you get it
> Soo you either lack voltage or something else bothers
> Error 6 can also be IMC related which is usually what should be confirmed first with y-crucher
> Stability on all selected (not stock) tests @ 4 loops
> 
> tFAW 15 has no pattern on anything @nada324
> It is neither 1x tFAW (which need tRAS+1 = tRC & a lot of tRDWR delay)
> And it also isn't 4* tRRD_S = Forth ACTIVE timewidow (4* tRRD_S) ~ (tFAW)
> 
> @GribblyStick 14-14-14 can need between 1.48-1.56v , sometimes 1.58v
> It should need about the same voltage as 3200C11-11-11 (it's not easy to run)
> I only see low tRRD & low tWTR
> In comparison
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Needed tRRD_S that high and tRFC that high
> Give your best, this so far is not your bet
> Error 6 is the same thing, "badly powered or catastrophic timeout"
> 
> More errors won't always mean it gets worse
> 6 & 0 need to be gone
> 1 & 11 are tRRDs , tWTR or tRDWR / tWRRD issues
> 
> 3800C14-14 are perfectly possible - you just need to shift tertiaries higher
> Lower primaries have a higher priority and do more changes
> For 16Gb dimms, use the google spreadsheet the big calculator on tRFC2 = B2 mode (higher capacity)
> else higher density dimms need higher tRRD, tWTR, a bit more tWR, and a bit more tRP + more tRFCns
> 
> The rest is pretty much identical and the failure on 4 dimm setups is mostly the bad layout/sorting
> Good dimms need to be on the slave set, which can work at lower voltage (user binning required)
> Worse sets, need to sit at the main slots, as they get more current ~ thanks to the daisy chain layout


Thank you, so the more tcke " more power "? 
I may try putting in A1 and B1 slots


----------



## Veii

Br3ach said:


> also in my case tRDRDSD / tWWRWRSD / _SCLs can go lower,


Lower SD, DDs eat performance don't "add" performance
Higher add preformance but can overlapp with other timings

Lower SCL adds performance, a quite significant one - but is PCB dependend and needs revaluated tRDWR and tWRRD scaling
Increasing SCL adds stability if needed, But lowering it is a good suggestion - just won't always work



Bonevi said:


> Hello, I have a pretty strange behavior in my system and hope someone might have and idea. Here is the system:
> View attachment 2482873
> 
> The memory is PVS432G360C8K with Samsung A-die. I am unable to get over 3533, but that might be explained by the 1.27V memory voltage. What is strange is that this is the most stable voltage. Increasing or reducing it makes the memory less stable. If I use 1.31V I get BSOD, if I put 1.33V I cannot even boot into Windows. I have not played with the timings, these are on auto as I was hoping to see where the frequency can go first, but without increasing the voltage this seems to be the maximum. I've played with VSOC, VDDP, CDD and IOD, but no matter what increasing the VDIMM makes things more unstable. Does anyone know what I might be missing?


Are these 2x 16 , if yes RTT_PARK is wrong that's for 8gb dimms
If they are on a 4x8 set, then you still have too low RTT_PARK , and need something at leasst at RZQ/3 or /2
It depends, but whereever you got this one, it's for 2x8 nothing 32gb related 

CAD_BUS is wrong, that's for Zen+
Zen 2 had 24-20-24-24 or 24-20-20-24 as minimum, same values did not do anything positive
You can run 24-20-20-24 if these ICs are that sensitive, but i dont think so
You can run 40-20-24-24 for Vermeer , or better is 40-20-30-20
I just think that you dont power them correctly. It certainly looks like it, if you start with GDM off 1T
If 2T is fine, then you 100% dont power them well

tRAS is low, start with at least 44 or 48 on your set, both tRCDs together as the minimum
tFAW should be 36 instead of 40, but these are bad XMP predictions 
(tRRD_S * 4 = tFAW)



nada324 said:


> Thank you, so the more tcke " more power "?
> I may try putting in A1 and B1 slots


More tCKE means a harsher powerdown between loads - it's a slope and is frequency dependent
3800 need tCKE 9 or 16
You can leave it or put it back to 1 (which means no powerdown only constant idle)

tCKE & CAD_BUS Setup times go together and they go together with CAD_BUS
Where CAD_BUS goes together with RTT
And RTT goes together with VDIMM
A combined combination 

6 often is resolved by just more or less vdimm
But big powering changes need everything in a set
If you see it being bad and have all timings options passed (doubt, as i saw only couple bad results)
Then you have to change the powering method. But i don't think you need to yet
60-20-20-20 was for your example, but high ClkDrvStr needs also less procODT
Less procODT needs less SOC voltage 
If you only get several error 6 at the same time, then it's a powering issue
If you get 1 or 2, and not an explosion of them (5* error 6 = BSOD) , then it's something else
If you get it only once, it could be a powerdown issue
If you get it once after a very long time, it could be too low tRFC or heat - but it should not appear alone


nada324 said:


> I may try putting in A1 and B1 slots


Binn them
Get 2 dimms out, check which one of the 4 need less VDIMM for a 16 set
(be sure to CMOS reset & change RTTs for 2x 8gb)
Get something harsh to run like 3800 CL14
(i have trust in you guys being able to run it - it's not thaat hard)
But even 3733 C14-14 at 1.46-1.54v is fine
Check which dimms need the least amount of voltage and then put them on the slave set
Soo the weaker dimms get more current (ampere) when they sit on the main slots


----------



## Dasa

Veii said:


> Get something harsh to run like 3800 CL14
> (i have trust in you guys being able to run it - it's not thaat hard)
> But even 3733 C14-14 at 1.46-1.54v is fine


So you think my worst stick is capable of that?
Mind giving me a list of settings for a single 8GB A1 stick focused on nothing more than achieving 3771 14-14 at any performance penalty from other timings and I will stick it back in the system so we can work through the errors if your interested.


----------



## nada324

@Veii I left pbo disabled 1.13v soc and ycrunch will crash, i will test ycrunch again with xmp timings but 3800mhz.

Seems like imc is the problem


----------



## hsn

Something strange on my rig

Why the score on fclk 2066 is smaller than fclk 2033? I only increased the FCLK, while the RAM timing was exactly the one used in the FCLK 2033 (DDR4 4066). 

i am using 5600x, aorus b550i, viper 4400


----------



## Bojamijams

hsn said:


> Something strange on my rig
> 
> Why the score on fclk 2066 is smaller than fclk 2033? I only increased the FCLK, while the RAM timing was exactly the one used in the FCLK 2033 (DDR4 4066).
> 
> i am using 5600x, aorus b550i, viper 4400


You're not running in sync with your memory controller that's why. Go to 4133 or get your fclk back to 2033


----------



## T[]RK

I have got question about procODT, RTTs and CAD_BUS included it's Timings: how i track positive results? I got stock value (for example my motherboard set procODT 53.3), i can change it on something diffirent - no problem. But how i can track better (or worse) result? For example - i can get in Windows with procODT from 53.3 to 28.2. Run hours of TM5? What if i got no errors with diffirent values?

I used Google Ryzen calculator for timings. Work well for both: [email protected] and [email protected] (not really ready to deal with CL14 till i find solution to disable GDM). Set timings, check it in AIDA64 cache & memory (Read\Write\Copy\Latency) or in fast TM5 scans. No problem here.

CAD_BUS Timings i saw in this topic for 3600 (2-2-12), 3800 (3-3-15) and 4000 MHz (4-4-18). Know frequency - set correct values and done.

My current settings:








procODT and RTTs are default values.
CAD_BUS also set by board - default values.
CAD_BUS Timings set recommended for such frequency (3800 - 3-3-15).
tRDRDSCL\tWRWRSCL i set to 4, but i can get in windows with 2 without problem.

My ccurrent goal is - find way to disable GDM with 1T on Team Group RAM. Should i try temorarly set vDIMM to 1.5V? Since it's B-die there should not be a problem with degradation (just cooling).



Veii said:


> More tCKE means a harsher powerdown between loads - it's a slope and is frequency dependent
> 3800 need tCKE 9 or 16


So, should i start with tCKE 9, since my frequency is 3800? Is it a range or just two possible values? Also, what's range tCKE for 3600 MHz? Since my original XMP is 3600CL16 i may test it too.



Veii said:


> You can run 40-20-24-24 for Vermeer , or better is 40-20-30-20
> I just think that you dont power them correctly.


Power them correctly? More vDIMM or you mean something else?



Veii said:


> But 6-3-6 are better RTTs than 706
> Just require tCKE and CAD_BUS SETUP time
> They do not work with 40-20-30-20


I completely don't get it...RTTs 6-3-6 need tCKE+CAD_BUS Setup times, but don't work with procODT=40 and CAD_BUS=20-30-20? It's RTTs=6-3-3 so special? Can i use RTTs=7-0-6 with procODT=40 and CAD_BUS=20-30-20? Or it's just impossible to set everything (tCKE\CAD_BUS\RTTs\CAD_BUS_Timings)?


----------



## nada324

Got rid of the Error 6, by changing cad bus from 60-20-20-20 to 40-20-24-20, now to fix other errors.


----------



## Karagra

what do you guys think is the best buy?
Steel Viper 4400mhz
Thermaltake 4400mhz
Ballistix Max 4400mhz


----------



## kratosatlante

Karagra said:


> what do you guys think is the best buy?
> Steel Viper 4400mhz
> Thermaltake 4400mhz
> Ballistix Max 4400mhz


you have viper 4400, why ask? i have 2kits , buy another


----------



## Pictus

..


----------



## nada324

Finnally got this stuff to pass test, @Veii

The trick was to put in Auto, all tw sd dd, and trd sd dd, and also TCKE.


----------



## T[]RK

So, i added RTTs, CAD_BUS and CAD_BUS Timings to my so called "Tuned XMP". Original XMP profile is trash (CPU PhotoWorxx in AIDA64 have got only about 17k, after tune - ~26k!).

Also, as an experiment i lowered (again!) cLDO_VDDP, VDDG (both: CCD & IOD) to 860-900-940, but vSOC is 1060 (just for 3600 MHz).








Since my CPU is UnderVolted, TM5 was runned at 4425 MHz and 1138 mV. Before i get decent TIM i can only run it on my Graphite Pad. But if i get errors - i get errors. If there is no - there is no. Right? TM5's 10 cycle show no errors, so... 20 maybe?


----------



## RosaPanteren

Any tip for Cad bus timings for 2x16GB dual rank sticks @3800c14

I have seen 3-3-15 and 6-3-3 used, could some of these settings be a starting point for this setup?

I also tried tCKE 9 & 16 but these threw an error after approx 1.5 runs of Anta777, 6 seems stable though.....

Any tips on things to improve would be greatly appreciated  I think next step for me would be to pin down trfc2&4, does 169 - 104 sound within reason?










Tried reading through the 30 or so last pages and also google Cad bus timings with no specific luck, but I might have missed out on that info.....please point me in a direction if I have missed already stated info


----------



## nexxusty

RosaPanteren said:


> Any tip for Cad bus timings for 2x16GB dual rank sticks @3800c14
> 
> I have seen 3-3-15 and 6-3-3 used, could some of these settings be a starting point for this setup?
> 
> I also tried tCKE 9 & 16 but these threw an error after approx 1.5 runs of Anta777, 6 seems stable though.....
> 
> Any tips on things to improve would be greatly appreciated  I think next step for me would be to pin down trfc2&4, does 169 - 104 sound within reason?
> 
> View attachment 2483002
> 
> 
> Tried reading through the 30 or so last pages and also google Cad bus timings with no specific luck, but I might have missed out on that info.....please point me in a direction if I have missed already stated info


Throwing an error well into the second test is almost guaranteed a temperature issue. RAM doesn't just pass like 3+ hours of Anta777 and then suddenly become unstable half way through the second test.

I'm extremely sure that's "wandering bits", A.K.A DIMMs above 45c, causing random errors.


----------



## DeletedMember558271

nexxusty said:


> Throwing an error well into the second test is almost guaranteed a temperature issue. RAM doesn't just pass like 3+ hours of Anta777 and then suddenly become unstable half way through the second test.
> 
> I'm extremely sure that's "wandering bits", A.K.A DIMMs above 45c, causing random errors.


If everyone here had 3080's or an equally heat outputting GPU 90% of these 1.5v+ results would be overheating if they tried to play a game with uncapped FPS.
3080 is almost like a hairdryer blowing on your RAM.

The whole "24/7" stability of this thread is a bit of a joke, unless that is no one here ever actually plays video games or stress other components like GPU.
24/7 as long as the rest of my components are idle lol.
Everyone pushing to the edge of temperature stability with everything else idle, throw some heat from GPU and it all falls apart.
I hope nobody here actually has a power hungry GPU, "my RAM is stable but if I try to play Cyberpunk I get 1000's of errors" lol.

100% load 3080 for an hour, run TM5 immediately after before RAM cools down, guarantee almost nothing in this thread is stable


----------



## Dasa

Dreamic said:


> The whole "24/7" stability of this thread is a bit of a joke, unless that is no one here ever actually plays video games or stress other components like GPU.


Some of us are running custom loops 
Non reference 3080 would be ok for RAM provided you had very high case airflow with something like Silverstone FT02.

But on days where the ambient hits 45c obviusly I need the AC running to keep it stable.


Now have the 4400c19 A0 in with the 3200c14 A1 and it is working nicely at old settings except it cant run 1T with 4 sticks anymore only with two.
As soon as it is set to 1T with the mixed sets it blue screens at 3771 or at 3773 it throws constant error 6 then error 12 with a few 0\2 thrown in before I gave up or running TM5 and tried to stabilize it but nothing I changed helped.


----------



## RosaPanteren

nexxusty said:


> Throwing an error well into the second test is almost guaranteed a temperature issue. RAM doesn't just pass like 3+ hours of Anta777 and then suddenly become unstable half way through the second test.
> 
> I'm extremely sure that's "wandering bits", A.K.A DIMMs above 45c, causing random errors.


Im pretty sure I kept the dimms below 40c(usually strive to keep them below 37c when stress testing in general) when testing tcke 9 & 16, but it might have been the issue.

I’ll test a bit more tomorrow to rule out temp issues👍

Any idea on cad bus timings?


----------



## DeletedMember558271

Dasa said:


> Some of us are running custom loops
> Non reference 3080 would be ok for RAM provided you had very high case airflow with something like Silverstone FT02.


My case has probably better airflow than most, 5x Noctua fans one of which is basically touching the RAM blowing on it at high speed, still gets too hot at 1.52v if I play a game like Apex Legends uncapped FPS for hours, whole room gets a lot warmer even, 3080 is a heater exhausting right onto the RAM.

If I never stress the GPU or had some trash 60hz monitor and capped games at 60fps I'd be fine though.
You're right watercooled 3080 maybe save this but most people aren't doing that.

Anyone with a weak low TDP GPU like a 1060 should be cautious if upgrading to something like a 3080 though, if already pushed RAM to the temp limit it's not going to be stable anymore going to have to dial your vDIMM back.


----------



## RosaPanteren

Dreamic said:


> If everyone here had 3080's or an equally heat outputting GPU 90% of these 1.5v+ results would be overheating if they tried to play a game with uncapped FPS.
> 3080 is almost like a hairdryer blowing on your RAM.
> 
> The whole "24/7" stability of this thread is a bit of a joke, unless that is no one here ever actually plays video games or stress other components like GPU.
> 24/7 as long as the rest of my components are idle lol.
> Everyone pushing to the edge of temperature stability with everything else idle, throw some heat from GPU and it all falls apart.
> I hope nobody here actually has a power hungry GPU, "my RAM is stable but if I try to play Cyberpunk I get 1000's of errors" lol.
> 
> 100% load 3080 for an hour, run TM5 immediately after before RAM cools down, guarantee almost nothing in this thread is stable


Well i run a 3090 with a max power draw of approx 480w on nothing but stock air at the moment, and yesterday I gamed bfv for 3 hours straight with dimms @1.55v

It’s true that the dimms do get warmer by this compared to stress testing with gpu on idle, but not more than 41-42c, and so far(only been running 1.55v for a week) I’ve had no issue with game crashes, bsod or anything

Now i got an open case and fans blowing directly on the dimms so with a closed off case there might be heat issues if the air flow wasn’t sufficient


----------



## Br3ach

Dreamic said:


> If everyone here had 3080's or an equally heat outputting GPU 90% of these 1.5v+ results would be overheating if they tried to play a game with uncapped FPS.


I'm still number 85 in the 3080 queue, but that's why I always stability test while GPU folding at the same time. Not all single errors are heat generated though.


----------



## nexxusty

Dreamic said:


> If everyone here had 3080's or an equally heat outputting GPU 90% of these 1.5v+ results would be overheating if they tried to play a game with uncapped FPS.
> 3080 is almost like a hairdryer blowing on your RAM.
> 
> The whole "24/7" stability of this thread is a bit of a joke, unless that is no one here ever actually plays video games or stress other components like GPU.
> 24/7 as long as the rest of my components are idle lol.
> Everyone pushing to the edge of temperature stability with everything else idle, throw some heat from GPU and it all falls apart.
> I hope nobody here actually has a power hungry GPU, "my RAM is stable but if I try to play Cyberpunk I get 1000's of errors" lol.
> 
> 100% load 3080 for an hour, run TM5 immediately after before RAM cools down, guarantee almost nothing in this thread is stable


I mean..... That's a pretty specific scenario, albeit a semi common one in this day and age. Heh heh.

Before I sold my 3080, it definitely released a lot of hot air, however I run a Thermaltake X9 open case (No side, top or front panels) and it honestly made no difference whatsoever.

My Patriot Viper Steel 4400mhz (B-Die, A2 PCB) 4X8Gb kits are 100% stable at 3866 14-14-14-14-30 2T @ 1.52v, GDM OFF. Actively cooled. They simply never go over 35c. B-Die, 1.5v+ and low temperatures make these claims perfectly believable.

Kinda seems like you might be "projecting" a little? Maybe? I know for a fact certain members here can be taken for their word. This is actually quite a respected, and respectable forum. I've been here for over a decade and this is one of the finest places on the internet for people looking to learn overclocking.

I think you're being silly, to be quite honest.

You also shouldn't be playing any competitive FPS uncapped. That's absolute n00b material man. Always, always at the bare minimum cap to 4fps under the hz of your monitor (If over 60hz, 60hz users use 59fps). I have a 1080Ti with a 5600x, in Apex, with my previously mentioned RAM configuration, playing at 1440p, almost everything low (Except textures). I capped it at 140fps and it's perfect. You also should cap close to the performance of what your GPU can do FPS wise, on a per game basis.

With a high end CPU and a 1080ti @ 2100mhz+ and 6000mhz VRAM, 140fps is right around the average FPS a 1080ti gets in Apex with that hardware configuration.

Yeah, it does more than 140fps about 85% of the time, however that 15% inconsistency matters. It's easier, and quicker to develop muscle memory at a constant steady FPS. This is a proven fact.

_edit_

Regarding using these 24/7 overclocks while using 99-100% GPU.... I was playing Shadow of War with everything Ultra @ 1440p, WITH 125% render scale for about 7 hours straight, without even a single stutter (Of which, I attribute to my fast AF, STABLE RAM) let alone a crash.


----------



## RosaPanteren

Dreamic said:


> My case has probably better airflow than most, 5x Noctua fans one of which is basically touching the RAM blowing on it at high speed, still gets too hot at 1.52v if I play a game like Apex Legends uncapped FPS for hours, whole room gets a lot warmer even, 3080 is a heater exhausting right onto the RAM.
> 
> If I never stress the GPU or had some trash 60hz monitor and capped games at 60fps I'd be fine though.
> You're right watercooled 3080 maybe save this but most people aren't doing that.
> 
> Anyone with a weak low TDP GPU like a 1060 should be cautious if upgrading to something like a 3080 though, if already pushed RAM to the temp limit it's not going to be stable anymore going to have to dial your vDIMM back.


No window ? 🙃

You probably got better air flow than most



















Those are for the cpu loop


----------



## PowerK

Dreamic said:


> If everyone here had 3080's or an equally heat outputting GPU 90% of these 1.5v+ results would be overheating if they tried to play a game with uncapped FPS.
> 3080 is almost like a hairdryer blowing on your RAM.
> 
> The whole "24/7" stability of this thread is a bit of a joke, unless that is no one here ever actually plays video games or stress other components like GPU.
> 24/7 as long as the rest of my components are idle lol.
> Everyone pushing to the edge of temperature stability with everything else idle, throw some heat from GPU and it all falls apart.
> I hope nobody here actually has a power hungry GPU, "my RAM is stable but if I try to play Cyberpunk I get 1000's of errors" lol.
> 
> 100% load 3080 for an hour, run TM5 immediately after before RAM cools down, guarantee almost nothing in this thread is stable


Guarantee, huh?
No problem at all. You need a good case with good air flow and active cooling on RAM and VRM.
All fans are Noctua NF-A12x25


----------



## Karagra

kratosatlante said:


> you have viper 4400, why ask? i have 2kits , buy another


Probably to know if its worth even grabbing a different kit, or attempting at getting another viper. you know asking in a overclocking forum for ram where people might have experience with one vendor selling extremely bad binned chips


----------



## Karagra

Dreamic said:


> If everyone here had 3080's or an equally heat outputting GPU 90% of these 1.5v+ results would be overheating if they tried to play a game with uncapped FPS.
> 3080 is almost like a hairdryer blowing on your RAM.
> 
> The whole "24/7" stability of this thread is a bit of a joke, unless that is no one here ever actually plays video games or stress other components like GPU.
> 24/7 as long as the rest of my components are idle lol.
> Everyone pushing to the edge of temperature stability with everything else idle, throw some heat from GPU and it all falls apart.
> I hope nobody here actually has a power hungry GPU, "my RAM is stable but if I try to play Cyberpunk I get 1000's of errors" lol.
> 
> 100% load 3080 for an hour, run TM5 immediately after before RAM cools down, guarantee almost nothing in this thread is stable


Does a 6800xt matter? I don't only game on this I stream 12-15 hours some days with my gpu crammed into this tiny case with the door attached.


----------



## hsn

Bojamijams said:


> You're not running in sync with your memory controller that's why. Go to 4133 or get your fclk back to 2033


What I mean is this:
1 . fclk 2033 ddr4 4066 cl16-16-16-32 aida score is 52ns
2 . fclk 2066 ddr4 4133 cl16-16-16-32 aida score is 57ns

all subtimings are exactly the same only difference in fclk and ram frequencies


----------



## DeletedMember558271

Karagra said:


> Does a 6800xt matter? I don't only game on this I stream 12-15 hours some days with my gpu crammed into this tiny case with the door attached.
> View attachment 2483035


All I can say is my case definitely has way better airflow/ambient temp than yours then and 3733C14 1.52v Patriot 4400C19 4x8GB overheats into errors after an hour of uncapped FPS Apex Legends with a Noctua NF-A14 100% speed touching the DIMMs... my room temperature isn't high either but it does get warm for me with the 3080.

The other people who replied to me have open cases with active cooling on the RAM also and/or like 15 fans in their PC, yea I would probably be fine in that situation too.
Patriot 4400C19 don't have temp sensors so I don't actually know what mine are ever at.



nexxusty said:


> You also shouldn't be playing any competitive FPS uncapped. That's absolute n00b material man. Always, always at the bare minimum cap to 4fps under the hz of your monitor (If over 60hz, 60hz users use 59fps). I have a 1080Ti with a 5600x, in Apex, with my previously mentioned RAM configuration, playing at 1440p, almost everything low (Except textures). I capped it at 140fps and it's perfect. You also should cap close to the performance of what your GPU can do FPS wise, on a per game basis.
> 
> With a high end CPU and a 1080ti @ 2100mhz+ and 6000mhz VRAM, 140fps is right around the average FPS a 1080ti gets in Apex with that hardware configuration.
> 
> Yeah, it does more than 140fps about 85% of the time, however that 15% inconsistency matters. It's easier, and quicker to develop muscle memory at a constant steady FPS. This is a proven fact.
> 
> _edit_
> 
> Regarding using these 24/7 overclocks while using 99-100% GPU.... I was playing Shadow of War with everything Ultra @ 1440p, WITH 125% render scale for about 7 hours straight, without even a single stutter (Of which, I attribute to my fast AF, STABLE RAM) let alone a crash.


So much of this is actually wrong misconception regarding FPS that just gets parroted around cause it's half true for certain situations but it's too much to get into, you don't need to cap Apex or Valorant or CSGO etc and I get a locked 299fps with Apex anyway which is as high as it can go, it is better to have the framerate in excess of your refresh rate.
Also just because the game isn't stuttering or crashing doesn't mean the RAM isn't erroring away... Apex was running fine for me but TM5 was a ****show immediately after.
You're at 3866 idk if you also have WHEA errors going on in the background but think it's fine and stable just because no stuttering or crashing slapping you in the face?
I would be fine too if I had an open case and 1080 Ti capped at less than half the framerate I'm running... my 3080 power limit is 375w not sure what your capped 1080 Ti is doing but probably less than 250w


----------



## mackbolan

craxton said:


> You not in whea logger lol, go under applications and services, microsoft, windows, kernel WHEA.
> 
> That's where actual whea errors are stored. The log you posted are services etc. Info is what's filled in mine. I just shared a shot of whea log in event viewer a few hours ago.
> 
> Not ona pc now and won't be for a week at the least. I'm using no bclk work around, no tricks to hide whea, my only thing I hide is my pc name being called blackBOSS lol so people don't say I'm racist or something...the pc is black none the less....
> 
> Anyhow, not many claim whea free. I'm not on the spread sheet, but I don't just claim whea free I have been since feb or later.
> 
> Last error I had was right after swapping to the 5600x. I have a 2x8 config you can copy paste that has better timings. Since what your copying now is for 4 sticks.
> 
> As stated tho, it'll be sometime before I'm on my PC again. It's in the comments here somewhere just gotta go back at least 20/30 pages
> 
> (Edit) I'm 24/7 daily stable, idk if you noticed tho, most here all have whea errors out the wazoo and can't fix it either. There's only a handful who run 4000/2000 stable without whea.
> 
> It may be due to the chip, ram, board idk, I'd try a b550 gaming edge board and if you come out whea clean then we know where the issue lies. Perhaps that's why msi is slow as a mofo about getting bios releases done?


It doesn't matter where you look. The area you specify shows it as "kernel 19" whatever, it's the exact same error time and number "19" that will not always present during an HWiNFO test session. I've been away, tuning this thing to the hilt and finally can say it's 10000000000000000000% stable at 1933/1966 1.4v. Veii has an "enigma" 2 x CCD 5600X, a bit unfair advantage it seems as I read down this thread, lol. Reads/Writes/Copies like a 5900X. I had to stop with the all core attempt and settle for PBO +100, which nets me ~4750 on 5 cores and 4790 on one. I have no WHEA errors not a single issue. I also had to get rid of the Kryonaut I put on, my CPU was running ~10-15c higher and spiking to ~86 with just CPU-Z, so getting anything stable was really challenging. I put on ThermalTake TG-7 (inferior I know) and my temps are 34c idle/70c full tilt gaming/79-80c peak during a stress test. But you can see in my Zen Timings, Aida test it's fine. I'm not after getting my spot on the board, so not bothering with all the confirmations. Take it or leave it, it's stable. I did say to redact your PC name if you post a screen shot of your Windows log, that's just good sense even if no one is likely going to identify you online and use some NSA type stuff to hack in, lol. I grabbed the system log because the kernel log is full of WHEA 20 from 3/16/21 before I was stable and had nothing in it newer.

My next step is going to be trying a set of Team Dark Za 4000, since I read there's some doubt about the Patriot Steel 4000 or maybe it was 4400, either way the Team is Samsung B-die. So if I fail to get a stable 4000/2000 I'll be able to fall back to this setting pretty easy. This RAM is going back into my AsRock X570 board with the 3600X and my mom is going to use it to watch LMN movies. "Fast Tears & Fears on LMN", lol


----------



## mackbolan

Dreamic said:


> All I can say is my case definitely has way better airflow/ambient temp than yours then and 3733C14 1.52v Patriot 4400C19 4x8GB overheats into errors after an hour of uncapped FPS Apex Legends with a Noctua NF-A14 100% speed touching the DIMMs... my room temperature isn't high either but it does get warm for me with the 3080.
> 
> The other people who replied to me have open cases with active cooling on the RAM also and/or like 15 fans in their PC, yea I would probably be fine in that situation too.
> Patriot 4400C19 don't have temp sensors so I don't actually know what mine are ever at.
> 
> 
> So much of this is actually wrong misconception regarding FPS that just gets parroted around cause it's half true for certain situations but it's too much to get into, you don't need to cap Apex or Valorant or CSGO etc and I get a locked 299fps with Apex anyway which is as high as it can go, it is better to have the framerate in excess of your refresh rate.
> Also just because the game isn't stuttering or crashing doesn't mean the RAM isn't erroring away... Apex was running fine for me but TM5 was a ****show immediately after.
> You're at 3866 idk if you also have WHEA errors going on in the background but think it's fine and stable just because no stuttering or crashing slapping you in the face?
> I would be fine too if I had an open case and 1080 Ti capped at less than half the framerate I'm running... my 3080 power limit is 375w not sure what your capped 1080 Ti is doing but probably less than 250w


I was blasting away for hours on FarCry 5 and BF4 running 4000/2000, no real heat issue but the Kryonaut I mention in my post. However, WHEA 19's the entire time I was gaming. HWiNFO was clean. I never cap games, FreeSync and a 185Hz Sceptre 32" 1800R 1080p works just fine with full FPS. In fact I put the command into the console for BF4 to cap frames at 400, I only ever hit 230 or so but it goes above the default 200. I run my RAM at 1.40v in a Corsair 750D Airflow Edition, nothing gets warm other than the parts that normally do like CPU to 60-70c gaming, SB to 45c or so, GPU gets to ~70c peak but floats more around the 60c mark. You can see my post, no WHEA today. None since 3/16/21 my last day of messing around with RAM speeds and finding the Kryonaut issue. 15 fans only work if they flow right. There's a case with 16 fans that actually performs terrible in thermal tests. I forget what it's called, GN reviewed it months ago. Airflow front to rear and slight bottom up to get a tiny bit of positive case pressure. Acts like a vacuum in pulling hopefully cooler ambient air in. When I pull a side off while running the fans kick up a notch, I know it's right. Not loud either, some noise under load but if you want power, it's not exactly quiet. Think about race cars and exhaust, loud due to low back pressure, more power.


----------



## Karagra

Dreamic said:


> All I can say is my case definitely has way better airflow/ambient temp than yours then and 3733C14 1.52v Patriot 4400C19 4x8GB overheats into errors after an hour of uncapped FPS Apex Legends with a Noctua NF-A14 100% speed touching the DIMMs... my room temperature isn't high either but it does get warm for me with the 3080.


Well my Viper 4400cl19 2x8GB ram does not overheat at 3800cl15 1.47v in this case.. again thats streaming to twitch and gaming with uncapped fps and my gpu is running overclocked at 2600mhz/2150/+15 Power. Whatever your issue is.. no offense but sounds isolated to you.


----------



## domdtxdissar

Since we are all sharing pictures now, this is my system which i run with no sidepanels 
All noctua 140*140mm and 200*200mm fans in this picture
Cooling is custom EK with TechN Zen3 block + THICK 360*120mm (6fans push/pull)+ 280*140mm (2 fans) rads
(Also have a 300*300mm fan on the backside of the motherboard, cooling VRM + socket area from behind)








Not pretty, but above average airflow... With a dedicated 140mm fan for the ram i have no problems with my 3090 overheating my memory OC, even after hourslong gaming sessions..

@ *Dreamic*

Iam running 4x8gb @ 1.58v
Max temp = 41 degrees on one of the sticks (other a ~2-3 degrees cooler)


----------



## Alyjen

Karagra said:


> Well my Viper 4400cl19 2x8GB ram does not overheat at 3800cl15 1.47v in this case.. again thats streaming to twitch and gaming with uncapped fps and my gpu is running overclocked at 2600mhz/2150/+15 Power. Whatever your issue is.. no offense but sounds isolated to you.


2 vs 4 dims for AMD should never be compared, it's so much easier to run 2 dims than 4, and it's not only memory controller but also heat disposal, and no what Dreamic writes is not isolated to his case. For some people it's enough to run TM5 right after serious CPU stress tests all there are errors everywhere for otherwise stabile timings. 
It' just that some bins of b-dies handle heat better than others, they will work or not and there's not much you can do about it other than voiding the warranty and replacing heatsinks. These Vipers have joke of a heatsinks on them and quite often poorly applied thermal compound so there's air between die and heatsink.


----------



## DeletedMember558271

mackbolan said:


> I run my RAM at *1.40v*





Karagra said:


> Well my Viper 4400cl19 *2x8GB* ram does not overheat at 3800cl15 *1.47v* in this case.. again thats streaming to twitch and gaming with uncapped fps and my gpu is running overclocked at 2600mhz/2150/+15 Power. Whatever your issue is.. no offense but sounds isolated to you.


Its late just looking at this before going to bed so all im going to say is why did you guys even reply to me in the first place?
I specifically said 1.5v+, wow you're a whole 0.02v over spec of default 1.45 XMP voltage...
My 3080 is pushed to its limits too as is my 5800x.
Same RAM as you, it runs fine 1.45v and is probably ok 1.47v too even 4x8GB which I know I wasn't talking about in my original post, maybe I'd even be fine 1.52v+ if I was 2x8GB.
Nobody should be overheating near default XMP 1.45v or lower especially if only 2 DIMMs.

Again @domdtxdissar you have an open case like 10 fans 2x 200mm where 99% of peoples side panel would be "above average" no **** top 1% your PC I'm sure that could handle 1.5v+ easy, which you didn't mention yours it better not be near 1.45v.

I just want to point out 0 of the people that have replied to me have a normal closed case and 1.5v+, everyone has open cases or less than 1.5v.

You don't have to worry about case ambient temp when you basically dont have a case, your room ambient temp is now your case ambient temp.


----------



## RosaPanteren

Dreamic said:


> Its late just looking at this before going to bed so all im going to say is why did you guys even reply to me in the first place?
> I specifically said 1.5v+, wow you're a whole 0.02v over spec of default 1.45 XMP voltage...
> My 3080 is pushed to its limits too as is my 5800x.
> Same RAM as you, it runs fine 1.45v and is probably ok 1.47v too even 4x8GB which I know I wasn't talking about in my original post, maybe I'd even be fine 1.52v+ if I was 2x8GB.
> Nobody should be overheating near default XMP 1.45v or lower especially if only 2 DIMMs.
> 
> Again @domdtxdissar you have an open case like 10 fans 2x 200mm where 99% of peoples side panel would be "above average" no **** top 1% your PC I'm sure that could handle 1.5v+ easy, which you didn't mention yours it better not be near 1.45v.
> 
> I just want to point out 0 of the people that have replied to me have a normal closed case and 1.5v+, everyone has open cases or less than 1.5v.
> 
> You don't have to worry about case ambient temp when you basically dont have a case, your room ambient temp is now your case ambient temp.


Well you addressed the community in an overclocking forum with;

*"The whole "24/7" stability of this thread is a bit of a joke, unless that is no one here ever actually plays video games or stress other components like GPU. 24/7 as long as the rest of my components are idle lol."

"guarantee almost nothing in this thread is stable"

"My case has probably better airflow than most, 5x Noctua fans"*

And now you end with;

*"I just want to point out 0 of the people that have replied to me have a normal closed case and 1.5v+, everyone has open cases or less than 1.5v."*

What were you expecting from people in an overclocking community......that everybody here have mass-produced office desktops with no air flow nor other appropriate cooling solutions, and that nobody had a clue about what effect heat have on the components and how to optimize temperature?

I think you should open a separate thread where you address your temperature issues, and then maybe some of the people you have talked down too in the last couple of posts will help you out with how they succesuflly managed good temps and air flow.

Good for you if you got the 3080 and 5800x pushed to the limits, now i expect that those limits are your limits and not necessarily the components.....be open and humble and hopefully people will share experience and knowledge


5800x kinda optimized for temp(got max temp dropped by approx 10c with lapping and TechN block later on) and half way pushed for perf.(boost override increased from 150 to 200MHz now) 

All cores boost to 5GHz at the same time after 1 houre and 15 min of looping Y-Cruncher, now this boost holds for the whole duration of FFT test

This only applies to FFT test as it's a relatively easy workload and the boost is all PBO and temp. setup dependent


----------



## MageTank

@Dreamic Stability is a very simple subject my friend. You are stable until you are not. That's it. This applies to absolutely everyone and can also differ based on our own standards that we define for stability. You might consider yourself stable if you do not crash under any of the normal workloads you perform, and I might not consider myself stable unless I pass random arbitrary tests I may never even use under thermal loads that are far beyond my anticipated use-case, but it doesn't matter as long as we achieve the level of stability we are looking for in our given build.

That said, it's not your place (or anyone's really) to question the stability of another's system. If you don't believe their system is stable, fine, but that's their problem to deal with, not yours. I am confident that I need not explain the differences in silicon quality to you or how something as simple as motherboards can require binning in order to achieve stability with a given memory OC (ignoring IMC binning & memory IC binning), so I'll leave that alone, but it stands to reason that those with identical hardware can still achieve two completely different overclocks and relative stability despite having identical setups. It's why you can't simply copy another OC and expect it to work outright as the quality of your hardware or the environment in which you are using it may not be the same as the person whom you've copied.

One other truth about stability is that it is always fleeting. No overclock is stable forever, and what might be stable now may not be stable after time. This can be caused by changes in ambient temperature as the weather changes, or as the quality of your hardware begins to diminish over time, but it does eventually happen. Arguing stability is simply silly because it's practically subjective these days.

I don't really understand where your frustration is coming from. If it stems from seeing others tout their overclocks while yours isn't achieving their particular level, then continue to work at it. If you can't achieve a stable 3800, settle for a tighter 3600. I also agree with @RosaPanteren in that it is expected for an overclocking community to utilize less conventional cooling solutions & chassis to achieve higher overclocks. I had a pink desk fan mounted over top of my RAM for years to maintain a decent OC which was definitely unconventional at the time for normal users, but normal in my circle of overclocking friends. If you want to compare your results to people running less voltage and traditional cases, survey those people and compare the results.


----------



## Veii

Dreamic said:


> 5x noctua fans one of which is basically touching the RAM blowing on it at high speed, still gets too hot at 1.52v


This post of yours was edited and i want to say that you are wrong against us all and the "reason" for this thread
voltage does not increase heat
my 1.64v barely heat the dimms up at. they do have an "only" 500-600rpm fan vertical on them
but barely get over 30c, likely less - are cold during TM5

powerdown is to thank and low RTTs
Ampere that arrives creates heat - not used voltage
Voltage to resistance to impedance , please look it up

you are wrong ~ is all i wanted to say
I do not bother with cases, my room is big enough as heat dissipater
but i also run only a sub 50 bucks cooler
your case likely is good - but your explanation of voltage = heat, is wrong

To thank for the higher heatoutput is the bad design of nvidia gpu's pushing heat into the cpu&memory area
it's not our fault that you have a hot gpu - which's thermal creation is twice that of your CPU and ram
i dont need a 250W gpu, not even a 100W one to be satisfied with my needs.
Please don't trow us all under the same bus. And even if we all run 250+ watt GPUs wiith bad thermal design
it's you that missunderstands why dimms get warm or don't get warm. It's not the dimm voltage that heats them up
current doesn't create heat


----------



## MageTank

Veii said:


> This post of yours was edited and i want to say that you are wrong against us all and the "reason" for this thread
> *voltage does not increase heat*
> my 1.64v barely heat the dimms up at. they do have an "only" 500-600rpm fan vertical on them
> but barely get over 30c, likely less - are cold during TM5
> 
> powerdown is to thank and low RTTs
> *Ampere that arrives creates heat - not used voltage*
> Voltage to resistance to impedance , please look it up
> 
> you are wrong ~ is all i wanted to say
> I do not bother with cases, my room is big enough as heat dissipater
> but i also run only a sub 50 bucks cooler
> your case likely is good - but your explanation of voltage = heat, is wrong
> 
> To thank for the higher heatoutput is the bad design of nvidia gpu's pushing heat into the cpu&memory area
> it's not our fault that you have a hot gpu - which's thermal creation is twice that of your CPU and ram
> i dont need a 250W gpu, not even a 100W one to be satisfied with my needs.
> Please don't trow us all under the same bus. And even if we all run 250+ watt GPUs wiith bad thermal design
> it's you that missunderstands why dimms get warm or don't get warm. It's not the dimm voltage that heats them up
> current doesn't create heat


I think we might be splitting hairs here. Current by itself does not produce heat, the same is said of voltage. It is a combination of the two that results in the production of heat. It is important to remember that heat is a quadratic function. Power requires both current AND voltage, and increasing either while leaving the other the same will indeed increase the heat produced. Assuming the current to your DIMM's remains unchanged regardless of voltage input, increasing voltage will increase the power throughput of the DIMM, which will increase the heat. I have personally seen this in practice and it's not difficult to test/prove either. It's also why throwing voltage at an OC isn't always ideal when you cannot tame the resulting thermals as you'll handicap yourself with the resulting change in resistance impacting your overall stability at a given voltage.

That said, it's important to remember that voltage is simply potential, and that it's current that kills. I am sure you already know this, but not many do, and you often see threads asking about "safe voltages" when they run uncapped current limits on their boards, lol.


----------



## Not a redditor

RosaPanteren said:


> Well you addressed the community in an overclocking forum with;
> 
> *"The whole "24/7" stability of this thread is a bit of a joke, unless that is no one here ever actually plays video games or stress other components like GPU. 24/7 as long as the rest of my components are idle lol."
> 
> "guarantee almost nothing in this thread is stable"
> 
> "My case has probably better airflow than most, 5x Noctua fans"*
> 
> And now you end with;
> 
> *"I just want to point out 0 of the people that have replied to me have a normal closed case and 1.5v+, everyone has open cases or less than 1.5v."*
> 
> What were you expecting from people in an overclocking community......that everybody here have mass-produced office desktops with no air flow nor other appropriate cooling solutions, and that nobody had a clue about what effect heat have on the components and how to optimize temperature?
> 
> I think you should open a separate thread where you address your temperature issues, and then maybe some of the people you have talked down too in the last couple of posts will help you out with how they succesuflly managed good temps and air flow.
> 
> Good for you if you got the 3080 and 5800x pushed to the limits, now i expect that those limits are your limits and not necessarily the components.....be open and humble and hopefully people will share experience and knowledge
> 
> 
> 5800x kinda optimized for temp(got max temp dropped by approx 10c with lapping and TechN block later on) and half way pushed for perf.(boost override increased from 150 to 200MHz now)
> 
> All cores boost to 5GHz at the same time after 1 houre and 15 min of looping Y-Cruncher, now this boost holds for the whole duration of FFT test
> 
> This only applies to FFT test as it's a relatively easy workload and the boost is all PBO and temp. setup dependent
> View attachment 2483059


Can i replay to him that i have 1.55v jn a closed case ? Ans that no1 is replaying to my posts either even tho im having a 3950x not a mainstream cpu i get ignored ? Even tho i post and repost event viewr cct and tm5 stability + gaming and browsing and installing and using random softwares this i didnt say in my topics, i just say its stable, with all this i berly get a replay , only Veii replayed to me once a week or some days ago , from there im invisible. + i tryes to get ppl to work on 3950x to be stable on 4.8 but the obly response i get is a random thought and they mistake thinking im having a 5950x just like my previous post i post aida showing that is a 3950x and ppl asume its a 5950x, yes i booted a 3950x with 4.8/4.7 4.5/4.5 clocks , it was stable only for cbr20 single core.


----------



## Karagra

Alyjen said:


> These Vipers have joke of a heatsinks on them and quite often poorly applied thermal compound so there's air between die and heatsink.


Thanks you answered a question I asked earlier with this.. was debating on testing out these.. Crucial Max 4400mhzcl19 1.4v or test another set of vipers.. Now I am 100% going to just test the Crucial ram.


----------



## RosaPanteren

MageTank said:


> I think we might be splitting hairs here. Current by itself does not produce heat, the same is said of voltage. It is a combination of the two that results in the production of heat. It is important to remember that heat is a quadratic function. Power requires both current AND voltage, and increasing either while leaving the other the same will indeed increase the heat produced. Assuming the current to your DIMM's remains unchanged regardless of voltage input, increasing voltage will increase the power throughput of the DIMM, which will increase the heat. I have personally seen this in practice and it's not difficult to test/prove either. It's also why throwing voltage at an OC isn't always ideal when you cannot tame the resulting thermals as you'll handicap yourself with the resulting change in resistance impacting your overall stability at a given voltage.
> 
> That said, it's important to remember that voltage is simply potential, and that it's current that kills. I am sure you already know this, but not many do, and you often see threads asking about "safe voltages" when they run uncapped current limits on their boards, lol.


If I understand correctly this is what you see in practice everytime you open HWinfo, not speaking about dimms but the cpu though...

For light workloads you might see something like 1.45v........but at the same time only 35A is applied and that equals too approx 51w of power draw and the cpu temp will be something in the mid 30c with decent cooling....

For heavy workloads the voltage will often be lower maybe like 1.25v but amperage would be considerably much higher than on the light workload, and in the range of perhaps something like a 100A for a 5800x, and then net 125w with a temp closer to 80c


Disclaimer: I'm a complete n00b and what I seamingly try to explain "for myself" should under no circumstances be taken as valid information before someone with knowledge confirm/disconfirm

However for dimms the voltage is more or less fixed(assuming no tcke/powerdown) and also amps should be stable(?), so then applied ohmic resistance by RTT's (*and tcke/powerdown?) comes more into play for heat output as @Veii explains.........if I understand correctly.....idk......like 1.5v compared to 1.4v with let's say 25A would only give a difference of 2.5w power draw and in such a case not so much different heat dissipation given same or at best low resistance? Or am I completely misunderstanding all of this?

* but how does powerdown come into play if it's only applied in and out of idle? Or do I misunderstand powerdown functionality and that this is also in affect during normal operations?


----------



## Alyjen

Karagra said:


> Thanks you answered a question I asked earlier with this.. was debating on testing out these.. Crucial Max 4400mhzcl19 1.4v or test another set of vipers.. Now I am 100% going to just test the Crucial ram.


no problem  I have these Vipers, good set so no issues with heatsinks but they are just cheaper (for most of the time) than anything else in this range, good bin, but not without flaws


----------



## GribblyStick

quick question, how would one go about voltage binning?
I mean I guess I would leave in one stick and then switch out the other 3 running only two sticks at a time to see which combination can run at lower voltages and then I put the remaing two in the primary slots. But are there any timing considerations or so? would it be enough to take, say the default auto settings and then just manually reduce main timings until something gives?
How exact do you need this to be? are we just looking to find a setting that boots with one pair but not the other? I image that the would be pretty close?


----------



## DeletedMember558271

MageTank said:


> I think we might be splitting hairs here. Current by itself does not produce heat, the same is said of voltage. It is a combination of the two that results in the production of heat. It is important to remember that heat is a quadratic function. Power requires both current AND voltage, and increasing either while leaving the other the same will indeed increase the heat produced. Assuming the current to your DIMM's remains unchanged regardless of voltage input, increasing voltage will increase the power throughput of the DIMM, which will increase the heat. I have personally seen this in practice and it's not difficult to test/prove either. It's also why throwing voltage at an OC isn't always ideal when you cannot tame the resulting thermals as you'll handicap yourself with the resulting change in resistance impacting your overall stability at a given voltage.
> 
> That said, it's important to remember that voltage is simply potential, and that it's current that kills. I am sure you already know this, but not many do, and you often see threads asking about "safe voltages" when they run uncapped current limits on their boards, lol.


Yea we are splitting hairs, getting attacked with pointless semantics for not unnecessarily going into detail, and I'm not even wrong as you said anyway. He also backed up my point that a lot of peoples stability does come from not having a 375w GPU, obviously, that helps a lot. Like not living in Egypt. If you've pushed to the limits with a GPU that puts out half the heat, you would have to dial it back if you got one that doubles it, your limit has now been pushed back. If Veii sent me his motherboard, RAM, and settings, I would get them to overheat and error in my room in my case with my 3080.

I still stand 100% by that too many people are just running TM5 and thinking they're "24/7" stable, I am too as long as my 3080 is idle 24/7. But if it's not idle, extreme load for a long time, I have to lower my vDIMM so my RAM doesn't get too hot and error... which is what I've done and it works. If I take all the panels off my case I could probably be fine too would probably help a lot but I like to keep dust out and noise in. Ideal scenario would be an open case in another room, still would get way dustier though without filters.

I've also seen people run all their fans 100% speed when testing an individual component, it's just dumb. Then they never run their fans anywhere near 100% and have the rest of their components being stressed at the same time and just assume they're still stable, not if you were actually at the limit before in the best case scenario and that's what it needed to pass.


----------



## Sleepycat

domdtxdissar said:


> Since we are all sharing pictures now, this is my system which i run with no sidepanels
> All noctua 140*140mm and 200*200mm fans in this picture
> Cooling is custom EK with TechN Zen3 block + THICK 360*120mm (6fans push/pull)+ 280*140mm (2 fans) rads
> (Also have a 300*300mm fan on the backside of the motherboard, cooling VRM + socket area from behind)
> View attachment 2483047
> 
> Not pretty, but above average airflow... With a dedicated 140mm fan for the ram i have no problems with my 3090 overheating my memory OC, even after hourslong gaming sessions..
> 
> @ *Dreamic*
> 
> Iam running 4x8gb @ 1.58v
> Max temp = 41 degrees on one of the sticks (other a ~2-3 degrees cooler)


Last time I saw something with this much airflow was back during the AMD Athlon Thunderbird days!

I suspect I had OCCT Extreme errors previously because of RAM temperatures which hit over 57 ºC. I got a 2 fan DIMM cooler off Aliexpress for $15 (it's tiny, measuring 6x12 cm), and now it stays at 44 ºC maximum and don't get any OCCT errors nor WHEA. 

My case is closed, with only a single NF-A14 PPC3000 for the intake and an NF-A12x25 as the exhaust to give a slight positive pressure. The CPU is cooled successfully by the NH-U12A, 10 minutes of CB R23 brings the CPU to 81 ºC at its peak. I also have hot air dumped into the case by my EVGA 3080 XC3 Ultra, but the single intake and exhaust fans are able to keep the hot air moving by ramping up based on the internal thermal probe just above the GPU location.


----------



## Veii

Last couple of pages hurt to read
The point i tried to make is that VDIMM does not imply warmer dimms ~ even when it seems logical
At the right moment, i do push 1.65vDIMM on A0s ~ BUT with different RTTs (adjusted my settings for better again)
During the test i did indeed do browser things and other stuff - people love to break to the helpful doc ~ soo the result took more time
Nevertheless it keeps being stable and cold to the touch
Even if we say that some vipers dont have good heatsink contacts, while also relating to corsair LPX having bad heatsink contact
On both points - it does not apply to me
Dimms get either warm or don't get warm.
Neither stability breaks, nor i do open the window. I like my place be warm

There are many assumptions thrown into this thread, and if i would have to hold a hairdryer at my setup
Suurely someday it will get unstable. There are many methods with what i can come up with that destabilizes a setup
But neither do i have to forcefully buy an interestingly designed Ampere founders edition to meet some kind of stability targets
Nor do i have to heat them up intentionally, to proof another point

What remains stable in your system under your feeling well conditions, and comfortable enough noisefloor with or without a heating element
Remains your system and your scenario
It's not even worth it getting a point to consider comparing people's home setups
Oh also the open PC build sits about 15cm away from my room heating element . . .
Let's please not start ideal room requirements and cooling abilities or airflow discussions 
Some people don't like cases, others can not afford watercooling gear nor a case
~ i'm ticking both boxes here and work with what i have

I've seen discussions here about people complaining with bad memory chips either, which all still cost more than my equipment
Not to forget reminding some, that i started with 2666CL16-18 HynixMFR
Do not find reasons to justify your struggle please~
Reasons to justify not wanting to focus on resolving your issue , is a reason to justify being lazy
But searching for reasons to mark up your ability (because you don't want to work on it) , is purely wrong
If you don't want to invest time into it, don't blame others for not helping you
Nor do expect people to help you instantly ~ no one here is intentionally ignored 

Really hurts to read the amount of points we try to find, in justifying our annoyingness on something


> The point i tried to make is that VDIMM does not imply warmer dimms ~ even when it seems logical
> ....During the test i did indeed do browser things and other stuff...
> ...the result took more time...
> Nevertheless it keeps being stable and cold to the touch


RTTs matter
Impedance and resistance you trow into the equation matters
I didn't expect it to matter that much (before all these complains),
but my cheap case fan from who knows when 2008? ~ is enough to cool it, as they are cold during the test


Spoiler






















I keep optimizing my stuff and know if something is unstable ~ there are no "fake or prepared to be stable" results
50.4 to 49.6 on pure stock stock, is an improvement to my eyes 
Was worried about going higher than my 1.62v goal, while it first needed 1.64 with higher tRFC and tRAS+tRC
But they are perfectly fine ~ i won't worry anymore
RTTs and tCKE do their job - they are cold

But if i would push1.52v on 0/0/5 , the world would look completely different ~ toasty 
"VDIMM does not matter and generate heat"
It's the amperage you get out at the very end
Soo if your setup is hot , work on RTTs @Dreamic
I only now figured out how much they matter in heat output, thanks again 
_~but please don't question everyone's home compared to your setup, and trust the people here a bit more~_


----------



## Veii

GribblyStick said:


> quick question, how would one go about voltage binning?
> I mean I guess I would leave in one stick and then switch out the other 3 running only two sticks at a time to see which combination can run at lower voltages and then I put the remaing two in the primary slots. But are there any timing considerations or so? would it be enough to take, say the default auto settings and then just manually reduce main timings until something gives?
> How exact do you need this to be? are we just looking to find a setting that boots with one pair but not the other? I image that the would be pretty close?


Pretty much, same voltage on a pretested preset
Something you know X serial number part can reach on your setup with RTTs for 2 dimms
then lower voltage till it starts to error and try swapping one dimm till it passes

timings & voltage always go from the weakest link in the chain
but binning takes time
waiting time for stability tests to start failing - where you have to also factor in room temperature , or at least run a config that takes over 1 hour ~ soo dimms reach thermal equilibrium


RosaPanteren said:


> * but how does powerdown come into play if it's only applied in and out of idle? Or do I misunderstand powerdown functionality and that this is also in affect during normal operations?


Powerdown's functionality , in this case only tCKE - does instantly react between loads
It takes less than 1 sec making the system crash after you close TM5
or making it crash between tests

RTTs do adjust at the very start
But dynamic ODT (RTT_WR) if enabled, is constantly updating and adjusting signal quality to keep a clean data-eye open
Both of them can crash randomly or between test jumps
Usually tCKE's crash between , before and after load ~ and they are slopes you have to time by MCLK


Not a redditor said:


> only Veii replayed to me once a week or some days ago , from there im invisible.


You are not ignored because of your old CPU
but quite honestly, there is already soo much data out about Matisse and barely about Vermeer

DRAM OC didn't change that much between them, but this exists
Zen RAM Overclocking (ZEN 2) ~ Reddit made
and this OCN madeone








AMD RAM overclocking


ZEN 2 - Matisse (7nm TSMC) s name,latency,FCLK,MT/s,timings,DIMMS,IC-type,part number,read,write,copy,VSOC,VDDG,VDIMM,VDDP,ProcODT,RTT,stability test,CPU,mainboard Reous,57,5 ns,1900 Mhz,3800 Mhz,<a href="https://abload.de/image.php?img=380014-14-13-1310000kzbkdb.png">14-13-14-13-30-44-247</a>...




docs.google.com




there are soo many resources to compare how you stand up against other similar rresults

But to be again honest with you
The only reason i did not answer instantly , or skipped it
Is that i don't know what you can improve on your set
I don't know any new secret that could make it better ~ with this strange 14-8-15 set
I can only ask, why you won't spend more time to try and get 14-14-14 to run ?
A flat timings set nearly always performs better, unless the awkward one ticks couple of strange boxes


mackbolan said:


> Veii has an "enigma" 2 x CCD 5600X, a bit unfair advantage it seems as I read down this thread, lol. Reads/Writes/Copies like a 5900X.


Hahaha,
It's 2x 8c CCD
But it doesn't behave like one yet ~ microcode of a 6 core is enforced, till i figure out what to change and where
2nd CCD might be permanently active, but it doesn't get any load. it can't get any as the microcode doesn't give a correct core layout to the system (ACPI Layout)
soo they stay unused and can not have any benefits

It's a big piece of problematic CPU, there are no positives in it's current state that boost me anywhere on anything
I can not use allcores and only PBO can attach to the correct cores ~ where this little thing is limited at 4.85ghz (+200Mhz boost-target override) , while it can reach 5025Mhz in reality
(CTR but that's a secret topic for now & doesn't work with Aida64 well)
* also i work on a little powerplan that utilizes these overboost 6+ ghz spikes and gifts 0.3-0.4ns more & 20GB/s cache, but it's not done yet and wasn't used on the leaderboard
Example: https://twitter.com/VeiiTM/status/1372128316942135297


mackbolan said:


> I had to stop with the all core attempt and settle for PBO +100, which nets me ~4750 on 5 cores and 4790 on one. I have no WHEA errors not a single issue


Settle a bit lower to 4750 guaranteed and lower CO a bit further with added positive vcore offset
The system will autocorrect & clock-stretch. This costs you latency
4.75 on all cores should be 10.7ns L3 or 10.6 if you get it well

Timings are fine, good job on 1T GDM off !
If you feel like doing more, go for weaker RTTs (higher divider number) and run 60-20-40-20 on it (increased ClkDrvStr)
You should not need 40ohm procODT
and you should not need VDDG CCD that high
(voltage crashes are verifiable with y-cruncher all tests 4 loops 4*8min & later OCCT Extrerme AVX2, Large Dataset)
If both pass then you are fine, but you will need lower voltages if you want lower procODT = higher potential FCLK
Check if you can find CPU_VDDP to lower it down to 880 or 860mV


----------



## nada324

@Veii Can you do a Sumary or a guide of optimizing RTT values and TCKE for each frequency?


----------



## Veii

Karagra said:


> what do you guys think is the best buy?
> Steel Viper 4400mhz
> Thermaltake 4400mhz
> Ballistix Max 4400mhz


Probably too late
But the B-Die Ballistix Max is on a great A3 PCB
Their 19-19-19 set
even tho Viper 4400 are on a custom A2 PCB, they can not hold against ballistix's option 
Thermaltake showed good ICs, but 4400 @ 1.4v instead 1.45 on the Vipers @ tRCD 19, is purely better on any point


T[]RK said:


> Since my CPU is UnderVolted, TM5 was runned at 4425 MHz and 1138 mV. Before i get decent TIM i can only run it on my Graphite Pad. But if i get errors - i get errors. If there is no - there is no. Right? TM5's 10 cycle show no errors, so... 20 maybe?


make that 25
20 is the minimum required stability to reach thermal equilibrium - but 25 are a good option
There are tests which fail on the end of the 19th cycle and are tRFC related (most of the time)
Make it 25 to be sure , 20 on 32+ GB systems is enough. It will take long enough to warm-up


nada324 said:


> Finnally got this stuff to pass test, @Veii
> 
> The trick was to put in Auto, all tw sd dd, and trd sd dd, and also TCKE.
> View attachment 2482985


I wonder why you had issues with tWRRD
Shouldn't have issues with 1-5-5-1-7-7 SD, DDs
The other ones with 4 steps in between instead of 2, where to cover for the increased tRRD & tWTR ~ against 1's and 11's
Error 6 was usually ment to be fixed with slightly more vdimm +1 , but a powering issue can also be it








Do you want to test if my example at tCKE 9, would lead you anything positive ?
4200 CAD_BUS SETUP timings are 5-5-20 , not 5-5-21
but i can not get it coexist with the remain two powerdown methods of RTT and tCKE , it's problematic still
* also i can not get RTT_WR /2 to work, it's too strong or something bothers it
with 1.65vDIMM i surely don't want to go down to RTT_PARK /5 ~ it requires 


nada324 said:


> @Veii Can you do a Sumary or a guide of optimizing RTT values and TCKE for each frequency?


I'm not there yet 
too many little exceptions and examples to cover
actually, i do need more test examples
Feels like except 2-3 people , the only one who considers them being such a big deal

When i have enough information to make a full guide or roundup, i will
I can not promise it for now ~ many other issues which sitt on my arms that pull me down from what i like to do @ this community & the pc
It's actually really problematic, but i don't want to complain

EDIT:
4000 MT/s was tCKE 11 ~ if you're looking for it after running 3966 
CAD_BUS 60-20-40-20 remains top, but it can cause you issues with RTTs
40-20-30-20 and 40-20-40-20 where good examples to use without focusing on SETUP timings (which can break stability quite fast if they are slightly wrong)
4-4-18 was for 4000, you can also try 4-4-16 (haven't tested it ~ with 40-20-20-20 or 60-20-20-20)


----------



## nada324

Veii said:


> Probably too late
> But the B-Die Ballistix Max is on a great A3 PCB
> Their 19-19-19 set
> even tho Viper 4400 are on a custom A2 PCB, they can not hold against ballistix's option
> Thermaltake showed good ICs, but 4400 @ 1.4v instead 1.45 on the Vipers @ tRCD 19, is purely better on any point
> 
> make that 25
> 20 is the minimum required stability to reach thermal equilibrium - but 25 are a good option
> There are tests which fail on the end of the 19th cycle and are tRFC related (most of the time)
> Make it 25 to be sure , 20 on 32+ GB systems is enough. It will take long enough to warm-up
> 
> I wonder why you had issues with tWRRD
> Shouldn't have issues with 1-5-5-1-7-7 SD, DDs
> The other ones with 4 steps in between instead of 2, where to cover for the increased tRRD & tWTR ~ against 1's and 11's
> Error 6 was usually ment to be fixed with slightly more vdimm +1 , but a powering issue can also be it
> 
> 
> 
> 
> 
> 
> 
> 
> Do you want to test if my example at tCKE 9, would lead you anything positive ?
> 4200 CAD_BUS SETUP timings are 5-5-20 , not 5-5-21
> but i can not get it coexist with the remain two powerdown methods of RTT and tCKE , it's problematic still
> * also i can not get RTT_WR /2 to work, it's too strong or something bothers it
> with 1.65vDIMM i surely don't want to go down to RTT_PARK /5 ~ it requires
> 
> I'm not there yet
> too many little exceptions and examples to cover
> actually, i do need more test examples
> Feels like except 2-3 people , the only one who considers them being such a big deal
> 
> When i have enough information to make a full guide or roundup, i will
> I can not promise it for now ~ many other issues which sitt on my arms that pull me down from what i like to do @ this community & the pc
> It's actually really problematic, but i don't want to complain
> 
> EDIT:
> 4000 MT/s was tCKE 11 ~ if you're looking for it after running 3966
> CAD_BUS 60-20-40-20 remains top, but it can cause you issues with RTTs
> 40-20-30-20 and 40-20-40-20 where good examples to use without focusing on SETUP timings (which can break stability quite fast if they are slightly wrong)
> 4-4-18 was for 4000, you can also try 4-4-16 (haven't tested it ~ with 40-20-20-20 or 60-20-20-20)


 Its fine, i have been strugling to pass the #6 error for the past two days, changing soc voltage, rtts, tcke also but nope. My imc does not like TRCRD 15.


----------



## Veii

nada324 said:


> Its fine, i have been strugling to pass the #6 error for the past two days, changing soc voltage, rtts, tcke also but nope. My imc does not like TRCRD 15.
> 
> View attachment 2483130


Maybe your board doesn't like these SETUP Timings
Get them away & try it at tCKE 9
You shouldn't need 1.6, 1.58 would be fine for sure
Drop RTT_NOM down to /5 just to test


----------



## nada324

Veii said:


> Maybe your board doesn't like these SETUP Timings
> Get them away & try it at tCKE 9
> You shouldn't need 1.6, 1.58 would be fine for sure
> Drop RTT_NOM down to /5 just to test


Nah, made it worse, i guess i need some daisy-chain mobo.


----------



## Veii

nada324 said:


> Nah, made it worse, i guess i need some daisy-chain mobo.
> 
> View attachment 2483131


"without SETUP Times"
Honestly see noo difference here to the above, you Error 12 & Error 0 PCB crash still
Daisy Chain is worse 
2 DIMM board maybe


----------



## T[]RK

Veii said:


> make that 25
> 20 is the minimum required stability to reach thermal equilibrium - but 25 are a good option


k, will do. Look's like i may need fan for it (to exclude errors pop-up because of temperature).. I have open stand, but on CPU is huge two tower Phanteks heatsink - PH-TC14PE and it's front fan right on top of RAM modules.


----------



## nada324

Veii said:


> "without SETUP Times"
> Honestly see noo difference here to the above, you Error 12 & Error 0 PCB crash still
> Daisy Chain is worse
> 2 DIMM board maybe


If i make TRCDRD 16 no more #6 error, so mobo doesnt like TRCDRD 15 then


----------



## Veii

nada324 said:


> If i make TRCDRD 16 no more #6 error, so mobo doesnt like TRCDRD 15 then


You actually should be able to run CL14-14 then, if it was a board issue


Spoiler: For example


----------



## Veii

T[]RK said:


> k, will do. Look's like i may need fan for it (to exclude errors pop-up because of temperature).. I have open stand, but on CPU is huge two tower Phanteks heatsink - PH-TC14PE and it's front fan right on top of RAM modules.
> View attachment 2483133


Maybe some airflow from the far, but the heatsinks on this one actually do their job 
My setup doesn't look better at all
One dimm is even slightly curved ? 













Fan is behind it but barely does cool it. The only "cooling" job does this 500-900RPM DC fan
For you it's above , soo maybe something from the side


----------



## nada324

Veii said:


> You actually should be able to run CL14-14 then, if it was a board issue
> 
> 
> Spoiler: For example
> 
> 
> 
> 
> View attachment 2483134


Yeah, board issue.


----------



## Veii

nada324 said:


> Yeah, board issue.
> View attachment 2483153











Didn't copy either CAD_BUS, neither RTT nor CAD_BUS Setup timings or real timings
Are you trolling ?!


----------



## nada324

Veii said:


> Didn't copy either CAD_BUS, neither RTT nor CAD_BUS Setup timings or real timings
> Are you trolling ?!


Didnt copy those cause i would get error #6 and trcdrd is 16 because 15 is a nono (for my board)

Atm i will use this


----------



## Veii

nada324 said:


> trcdrd is 16 because 15 is a nono (for my board)


Thought you wanted to test it
Error 6 means powering issues or lack of VDIMM
i see no error log, nothing of "issues with lower than tRCDRD"

you use soo much voltage, they should run
Board issue i don't believe
A board would not post CL14-14 if it was a board issue
Your board has a good VRM setup too and was one of the few gigabyte boards without hardware overvoltage issue
I don't belive you 

My old B350 Tomahawk could run low timings
T-Topology just needs more current (A) & impedance
But the board does not control much the low timings ~ only the maximum frequency and minimum procODT
Where max freq is still near 4133-4200
Timings are not the boards work , it's memory to memory not memory to board
Signal quality is boards work * = procODT & RTT + CAD_BUS
* distance and signal degradation = a more stronger signal needs to be send with higher impedance ohm values


----------



## nada324

Veii said:


> Thought you wanted to test it
> Error 6 means powering issues or lack of VDIMM
> see no error log nothing of "issues with lower than tRCDRD
> 
> you use soo much voltage, they should run
> Board issue i don't
> A board would not post CL14-14 if it was a board issue
> Your board has a good VRM setup too and was one of the few gigabyte boards without hardware overvoltage issue
> I don't belive you
> 
> My old B350 Tomahawk could run low timings
> T-Topology just needs more current (A) & impedance
> But the board does not control much the low timings ~ only the maximum frequency and minimum procODT
> Where max freq is still near 4133-4200
> Timings are not the boards work , it's memory to memory not memory to board
> Signal quality is boards work = procODT & RTT + CAD_BUS


Later i will copy yours before ones and test it and see. Thank you!!


----------



## Boldish

@Veii What was the highest stable frequency you were able to hit when you were playing around with the dark hero board?

I can get a rock solid 3800cl14, but pushing to 4000 has been troublesome. I've upgraded to a newer bios to see if that improved anything for me but so far no dice.


----------



## Veii

Boldish said:


> @Veii What was the highest stable frequency you were able to hit when you were playing around with the dark hero board?
> 
> I can get a rock solid 3800cl14, but pushing to 4000 has been troublesome. I've upgraded to a newer bios to see if that improved anything for me but so far no dice.


It was 3800
1mhz higher pushed you into a WHEA land

Sadly i didn't have any good experience
Overall no good experience with 4 dimms on any board
haven't been able to figure out solid RTTs for them either 

I think the board trains well, and recovers fast
But some IO looks to cause big WHEA issues
something is broken on it
The bios options are fine and it keeps AMD CBS settings in the profile ~ soo it's also good
But really, something with the board is not right ~ it feels like it performs worse than the normal Crosshair Hero or Strix-E
Maybe because it's an X570 instead B550 , i am not sure


----------



## Boldish

Veii said:


> It was 3800
> 1mhz higher pushed you into a WHEA land


Well, crap. I only have 2 dimms but I haven't found the right combination of settings to make it stable.

Any thoughts on these settings? I'm running 1.5V










I tried pushing to 1.55V to try to lower tRCDRD to 14 but no dice. I may keep trying.


----------



## Veii

Boldish said:


> Well, crap. I only have 2 dimms but I haven't found the right combination of settings to make it stable.
> 
> Any thoughts on these settings? I'm running 1.5V
> 
> View attachment 2483182
> 
> 
> I tried pushing to 1.55V to try to lower tRCDRD to 14 but no dice. I may keep trying.


2x16 is an option
Why does everyone keep running 14-8-15-12 
Where do you get it from ? 
it looks soo unbalanced 
Minimum tRAS is even if we use an alternative calculation method (tRCDavg *2 + tBURST) 23+8=31
Not 24 
Even with an exploit it's 25

RTTs you can clone as 6/3/3 , CAD_BUS 40-20-20-20 & tCKE 9
on GDM off
who ever shares this GDM on set, it's purely autocorrected 
I have nothing to add to it - it looks like a mess , but if it functions, it functions


----------



## T[]RK

Veii said:


> make that 25


Done. Zero errors.










Veii said:


> Maybe some airflow from the far, but the heatsinks on this one actually do their job


Here is my small fan. Very old case fan (side fan) from ThermalTake Soprano. Nice airflow between memory modules.


----------



## Veii

T[]RK said:


> Done. Zero errors.
> View attachment 2483202
> 
> 
> Here is my small fan. Very old case fan (side fan) from ThermalTake Soprano. Nice airflow between memory modules.
> View attachment 2483203


Sorry to bother you, but the RTTs (likely the ClkDrvStr) is a bit strong for GDM on
Give it a go directly at GDM off 1T

and you might want to give 5/3/6 @ 60-20-40-20 a try
First before everything, get it GDM off stable ~ then we can talk 

About the fan, i was thinking about it - but you have to put it slower
Else the wind turbulence would be too strong (rather the air canal) and fully prevent the CPU cooler from getting air in


----------



## nada324

@Veii Well, just clone your suggested setup for 3800 c14 but got ton of #6 erros now lol:


----------



## Veii

nada324 said:


> @Veii Well, just clone your suggested setup for 3800 c14 but got ton of #6 erros now lol:
> 
> View attachment 2483204


Go up in voltage & start with 2T
i have to find the old post again








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Hi, I cant seem to get my memory stable on my Ryzen 2700x system. Using a pair of 8GB F4-3600C17-8GVK, in my X470 Aorus Ultra Gaming board, and have set the timings as per Ryzen DRAM Calculator DRAM voltage is however increased to 1.4V to see if I could get it stable. I'm running into errors...




www.overclock.net




This one 
it's surely possible, but you need to see what prevents you
Soo start lower at 2T

You can also increase tRRD and tRDWR , if you face stability issues
tFAW & SCL stay how they are


----------



## nada324

Veii said:


> Go up in voltage & start with 2T
> i have to find the old post again
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Hi, I cant seem to get my memory stable on my Ryzen 2700x system. Using a pair of 8GB F4-3600C17-8GVK, in my X470 Aorus Ultra Gaming board, and have set the timings as per Ryzen DRAM Calculator DRAM voltage is however increased to 1.4V to see if I could get it stable. I'm running into errors...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> This one
> it's surely possible, but you need to see what prevents you
> Soo start lower at 2T
> 
> You can also increase tRRD and tRDWR , if you face stability issues
> tFAW & SCL stay how they are


With 2T its worse i think, i need other CAD BUS stuff or RTTs to 6 3 6 maybe i will test


----------



## T[]RK

Veii said:


> About the fan, i was thinking about it - but you have to put it slower


I have no control over it RPM, it's only ON\OFF (only two wires via 4-pin Molex).



Veii said:


> Else the wind turbulence would be too strong (rather the air canal) and fully prevent the CPU cooler from getting air in


Nah, it's not Delta fan. =) Just small wind at another side on modules. CPU cooler have got powerful 2x 140mm PWM fans, but CPU is undervolted anyway and can't overheat.



Veii said:


> Sorry to bother you, but the RTTs (likely the ClkDrvStr) is a bit strong for GDM on
> Give it a go directly at GDM off 1T
> 
> and you might want to give 5/3/6 @ 60-20-40-20 a try


I can try it, but Team Group modules have got weird reaction on GDM Off + 1T. I will try it with native (for XMP) 1.35V, next 1.45V and then 1.55V.



Veii said:


> First before everything, get it GDM off stable ~ then we can talk


That's my goal: XMP => Tune XMP => 3800CL16 => 3800CL14.


----------



## domdtxdissar

Veii said:


> Why does everyone keep running 14-8-15-12
> Where do you get it from ?
> it looks soo unbalanced


You didn't ask me, but i run pretty much the same timings.
tRCDWR 8 = _Buildzoid_ recommended it in one of his videos for like 1 year ago. Lower is better right ?
tRCDRD 15 = Whatever voltage or settings i try, i can never get it stable at 14 above 1833/1866mhz.
TRP 12 = Lower is better right ?

If i want to run lowest possible (stable) tRFC and keep the relation between tRC and tRFC, i need to run "lower then calculated" tRAS. Do you know any other ways around this ?

These are my latest stable settings








60min OCCT large dataset
100min memtest
150min karhu ram test
170min testmem 1usmus cfg

Question for you:
Why does your settings score so low (106sec) in dram calc easy benchmark ? Shouldn't your 2100:4200 settings pretty much crush everything else here, or is your setup (OS +powerplan etc) only optimized for aida64 latency bench and nothing else "real world" ?


----------



## T[]RK

domdtxdissar said:


> _Buildzoid_ recommended it in one of his videos for like 1 year ago.


I watch BZ videos from time to time, but also keep in mind that BZ don't care about daily stability. Throw 2V on RAM and Geekbench pass = memory stable. It's not overclocking (buy for cheap => overclock => get more, save money), it's XOC (limit ram in windows, throw a lot voltage, fans on RAM, LN2, +1 point in benchmark is evething). A bit diffirent thing.


----------



## Dasa

Veii said:


> Do you want to test if my example at tCKE 9, would lead you anything positive ?


Thought I would add another data point for you using these sticks
Rimjaws V 3200c14
S1 15-16 1.5v bsod on boot at c14
S2 15-17 1.5v

tRCD 15 resulted in BSOD on boot so had to dorp back to 16 at those settings.
Also running 3771 as I get WHEA at 3800 with any settings.


----------



## Veii

domdtxdissar said:


> Question for you:
> Why does your settings score so low (106sec) in dram calc easy benchmark ? Shouldn't your 2100:4200 settings pretty much crush everything else here, or is your setup (OS +powerplan etc) only optimized for aida64 latency bench and nothing else "real world" ?


This sounds very sarcastic
4 things
i am 4.85ghz limited at best
i keep hitting the 120A EDC Fuse limit because SOC alone takes 23W out of the whole powerbudget
i don't have any performance enchancer tweaks Asus & MSI user can/do use on stock (this includes latency enchancers)
i don't know, the test showed well from 3800 to 4200 that it's not FCLK related ~ but remains equally bad
I blame the dual CCD bugginess, unsure

Oh also don't mix up the dates
the work in progress plan has nothing to do with any scores that are known


domdtxdissar said:


> Lower is better right ?


is not
There is a trick to have it half of tRCDRD - that makes sense
but anything else doesn't, unless you use another math for tRC
overall nearly always it ends up slower ~ except tiny exceptions

I would hope BZ didn't recommend it with GDM on
On off, it's less bad


Dasa said:


> Thought I would add another data point for you using these sticks
> Rimjaws V 3200c14
> S1 15-16 1.5v bsod on boot at c14
> S2 15-17 1.5v
> 
> tRCD 15 resulted in BSOD on boot so had to dorp back to 16 at those settings.
> Also running 3771 as I get WHEA at 3800 with any settings.
> 
> View attachment 2483220


0's are crashing PCB related (powering)
Not timings related


----------



## Dasa

Veii said:


> 0's are crashing PCB related (powering)
> Not timings related


Yeah seems 1.6v was just to much juice for them now testing to find the max v at 15-17 using those settings now then will try tighten it back up.


----------



## Veii

Dasa said:


> Yeah seems 1.6v was just to much juice for them now testing to find the max v at 15-17 using those settings now then will try tighten it back up.


Oh i see the issue, tCKE 13 is for 4200 not for yours
Probably tCKE 7 or 8
9 is for 3800 MT/s ~ 6 for 3600


----------



## LuckyImperial

LuckyImperial said:


> I've never used the BIOS search tool before. Pretty cool.
> 
> fCLK yielded two values so I set them both to 1800MHz.
> uCLK yielded the dividing value, so I set that to UCLK==MEMCLK
> Fabric yielded Infinity Fabric Frequency and Dividers, so I set that to 1800MHz.
> Crate yielded "Download & Install ARMOURY CRATE app", I set that to Disable.
> 
> After those changes I'm still at 1833MHz:1800MHz:916.5MHz if I try DRAM Freq 3666MHz
> 
> EDIT: I've also enabled SoC/Uncore OC with no luck.


So I finally figured out why my uclk wasn't syncing to my mclk. It was because my Fabric was auto downclocking to 1800MHz. As soon as I fixed that to 1900MHz to match DRAM, uclk starting running 1:1. 

It turns out if your mclk and fclk are different, then uclk will always run 1:2 with mclk.


----------



## Dasa

Veii said:


> Oh i see the issue, tCKE is for 4200 not for yours
> Probably tCKE 7 or 8
> 9 is for 3800 MT/s ~ 6 for 3600


Ok thanks.
Passed 5min with those settings at 15-17 1.45v tCKE 13
Will swap to 1.5v and tCKE 8 to see what happens.


----------



## nada324

@Veii maybe my errors are heat related, inma buy a industrial 3k rpm noctua fan haha


----------



## Veii

nada324 said:


> @Veii maybe my errors are heat related, inma buy a industrial 3k rpm noctua fan haha


you reaally shouldn't need it
but some fan yes
might be better to fully remove the heatspreader or swap the thermal pads , instead of investing that much

Fractal Design Venturi lineup, is to recommend ~ but you pay for the quality
HF for mass airflow, HP for close up pressure
or Arctic P12 , for close ups


----------



## Dasa

Was seeing error 0 at 1.55v and error 4 & 10 at 1.5-1.53v
1.49v seems to be the borderline max at these settings for two passes of TM5

Dropped back down to 15-16 and error 6 is gone! but plenty of others remain.
Dropping from 1.49v down to 1.45v seemed to reduce the amount of 0\10 errors each pass but is getting a bit low for stability and may be introducing some new errors.
Will see what tCKE 7 does.


----------



## Veii

Dasa said:


> Was seeing error 0 at 1.55v and error 4 & 10 at 1.5-1.53v
> 1.49v seems to be the borderline max at these settings for two passes of TM5
> 
> Dropped back down to 15-16 and error 6 is gone! but plenty of others remain.
> Dropping from 1.49v down to 1.45v seemed to reduce the amount of 0\10 errors each pass but is getting a bit low for stability and may be introducing some new errors.
> Will see what tCKE 7 does.
> View attachment 2483234


0,4,8,14 are all PCB "start" issues or "dimm to dimm copy" issues
0 & 4 are PCB crashes
soo you should try to lower ClkDrvStr for now
if you change primaries , the rest is offsync
changing one timing needs to follow 2-3 more
only changing tRCD needs adjustment in tRAS, tRC

It might be better to stay with RTT 706 , till you get your timings correctly 
Fighting on two fronts, Powering and Timing issues, is hard


----------



## Sleepycat

nada324 said:


> @Veii maybe my errors are heat related, inma buy a industrial 3k rpm noctua fan haha


I have that fan, NF-A14 PPC3000 on my intake. And no, it doesn't really make a big impact to DIMM temperatures even at the stupidly loud 3000 rpm. Those tiny ones that mount directly on top of the DIMMs work great though.

I got this and it lowered my full load peak DIMM temperature from 57 to 44 ºC








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----------



## Dasa

Veii said:


> 0,4,8,14 are all PCB "start" issues or "dimm to dimm copy" issues
> 0 & 4 are PCB crashes
> soo you should try to lower ClkDrvStr for now
> if you change primaries , the rest is offsync
> changing one timing needs to follow 2-3 more
> only changing tRCD needs adjustment in tRAS, tRC
> 
> It might be better to stay with RTT 706 , till you get your timings correctly
> Fighting on two fronts, Powering and Timing issues, is hard


Well 15-15 now boots but error 6 is back.










And with the RTT changes you suggested.


----------



## Sleepycat

Dasa said:


> Well 15-15 now boots but error 6 is back.
> 
> View attachment 2483241
> 
> 
> And with the RTT changes you suggested.
> View attachment 2483242


Is there a reason you chose to run tWRRD (1)?

Not sure if you want to try this, but I had TM5 errors (can't remember which ones) (and later on OCCT Extreme errors), but fixed it by changing ProcODT to 53.3 and ClkDrvStr/AddrCmdDrvStr/CsOdtDrvStr/CkeDrvStr to 24.0 for all of them. I also keep RttNom/RttWr/RttPark all at Auto, which is RZQ/7, RZQ/3 and RZQ/1, respectively.

Doing this, I could run 4x16GB dual rank B-die at 3600 CL14-15-14-14 (both 2T GDM Off, and 1T GDM On) with 1.46V and VSOC 1.09V (LLC2).


----------



## Dasa

Sleepycat said:


> Is there a reason you chose to run tWRRD (1)?


Just using the settings* Veii* suggested to somebody else having trouble lowering tRCD
But have since tried tRCD at 2 along with setting tRFC and tWR back to auto with 1.44v this kit now getting far less errors at 15-16 there is just four error 10 and two error 2 in the first 4 passes of TM5.












Sleepycat said:


> and ClkDrvStr/AddrCmdDrvStr/CsOdtDrvStr/CkeDrvStr to 24.0 for all of them.


My system really seems to like ClkDrvStr 40-60 but the rest have far less impact.



Sleepycat said:


> I also keep RttNom/RttWr/RttPark all at Auto, which is RZQ/7, RZQ/3 and RZQ/1, respectively.


I was running that as well with 4x8GB but it is apparently very hard on the sticks and was able to stabilize it with 6/3/3 which is apparently much safer.

Currently just testing my two worst sticks one of which had hit a wall at 15-17 to see if they can go lower with some help from others here and then that knowledge may help me get more out of my best sticks as well which range from 14-15 to 15-16.


----------



## Sleepycat

Dasa said:


> But have since tried tRCD at 2 along with setting tRFC and tWR back to auto with 1.44v this kit now getting far less errors at 15-16 there is just four error 10 and two error 2 in the first 4 passes of TM5.


I run tWRRD (4), so much looser. If you are still getting errors, you can test it at 4.



Dasa said:


> My system really seems to like ClkDrvStr 40-60 but the rest have far less impact.


ClkDrvStr would be increased if signalling integrity was weak by the time you hit your 4th DIMM slot. I believe that if you increase it, the signal strength would be increased, but it also amplifies any noise in the signal too, leading to a higher chance of uncorrectable errors.

In addition, I saw your vSOC is also at 1.2V. The SOC seems to have a sweet spot for voltage for a given IF and memory speed. Going higher than the sweet spot introduces more instability. I used 1.09V for 3800 / 1900IF when I was running 2x16GB, so it is likely that you can reduce your vSOC to 1.1V to gain more stability.



Dasa said:


> I was running that as well with 4x8GB but it is apparently very hard on the sticks and was able to stabilize it with 6/3/3 which is apparently much safer.


Were you also getting errors with 7/3/1? Or were you running at 6/3/3 from the start? I'm running 4x16GB, which limits me to 3600 CL14, but I agree, it becomes a very fine line between getting into Windows and not being able to POST at all. My setup for example won't post properly with 1.45V, but is perfect with 1.46V (passes OCCT large extreme and TM5)



Dasa said:


> Currently just testing my two worst sticks one of which had hit a wall at 15-17 to see if they can go lower with some help from others here and then that knowledge may help me get more out of my best sticks as well which range from 14-15 to 15-16.


Cool, hope you are able to find a setting that works. Also something to consider is that signalling gets worse when you get to DIMM slot A1 and B1 (furthest away from SOC). So you can put your best RAM sticks into A1 and B1, and the worst ones into A2 and B2. This should even them out and hopefully reduce signalling issues.

There are still many options you can explore. The various settings also interact with each other to affect stability, so there are many combinations that would work but it will take a lot of time to identify. I rebooted my PC over 700 times in the first 2 weeks to find the right memory settings to support the timings I was aiming for with 4x16GB.

You should be able to eventually find a setting that works without errors. But also keep an open mind as memory performance and errors don't just rely on the RAM sticks, but also on the SOC. So you could be limited by your CPU as well when you are running 4 sticks.

I explored 2 sticks (2x16GB) for a short while but didn't really optimise it. These settings got into Windows, and was able to run TM5 and Aida64 successfully with vDIMM 1.40V. If you still can't become error-free after trying all the options here, you can try out my settings if you want. They should hit CL14, just remember to recalculate the tRAS, tRC, tFAW and tRFC's for 3733MHz and CL14.


----------



## Dasa

Sleepycat said:


> If you still can't become error-free after trying all the options here, you can try out my settings if you want. They should hit CL14, just remember to recalculate the tRAS, tRC, tFAW and tRFC's for 3733MHz and CL14.


2x16GB is usually a bit different in requirements to 2x8GB but those exact settings do work with 1.43V other than a few WHEA errors due to my CPU\MB at 3800.
But I have my doubts that they will work with higher V required for c14\c15 as these sticks just don't seem to like it.

The tRFC calc here doesn't seem to be working for me at the moment








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com





Edit: tested same settings again with 1.46v up from 1.43v and it has 46 errors vs 0 in 30min
error 0\2\10\13\14\11\15\9\5\6


----------



## Nighthog

For Gigabyte motherboards, the X570 Xtreme I've had best luck using 6/3/1 for RTT RZQ settings when using 4x dimms.
7/2/1 was good on earlier bios but latest have preferred 6/3/1 for best frequencies.

Be aware the Gigabyte boards have variable Voltage needs, there are "bad range" voltages depending on your choice of RTT & DrvStr settings. Like memory holes, you have "voltage holes" where anything you might try will not work on that particular voltage.
I've seen them come around the 1.41-1.43v, 1.51-1.54V, 1.61-1.65V ranges, 
Basically 1.6V is OK but then you need to jump to 1.65V or go for 1.69-1.70V.
I've seen this same thing appear in the 1.40 is OK but then you need 1.45V or go for 1.47-1.50V.


----------



## nobody.nowhere

drnilly007 said:


> View attachment 2482515
> View attachment 2482516
> 
> Can anyone look over these timings let me know if you see any deficieny or wrong calculations. Hynix MJR just fyi


I'm on Hynnix MJR as well, although a very different kit and setup: 4x32GB dual rank on a 3970X...


nobody.nowhere said:


> Hello all.
> 
> I'm hoping someone can recommend any timing changes for my configuration that might help me close the gap on latency (but also open to bandwidth advice).
> Hynix MJR on a 3970x - So I'm not going to win any latency speed challenges anytime soon...
> 
> Ram is G.Skill F4-3600C18Q-128GTZR (4x 32GB) 2Rx8 B1 1.35v
> View attachment 2482706
> View attachment 2482707
> 
> 
> Auto settings for tRDRD__ and tWRWR__, tRDWR, tWRRD, tRFC2/4, and all voltages and resistances (except for a slightly lowered vSOC - 1.1v down to 1.075v).
> I haven't yet performed a full stability test, but it's passed 20 hours of prime95 large FFTs, no hardware errors or Prime95 errors.
> I had the above timings running at 1866 / 3733, but I got an infinity fabric L3 cache error after about 9 hours of testing, and decided not to go down the path of VDDG over-volting.
> 
> 
> Spoiler: Kernel error after 9 hours at 1866 / 3733
> 
> 
> 
> 
> mce: [Hardware Error]: Machine check events logged
> [Hardware Error]: Corrected error, no action required.
> [Hardware Error]: CPU:0 (17:31:0) MC27_STATUS[-|CE|MiscV|-|-|-|SyndV|-|-|-]: 0x982000000002080b
> [Hardware Error]: IPID: 0x0001002e00001e01, Syndrome: 0x000000005a020009
> [Hardware Error]: Power, Interrupts, etc. Ext. Error Code: 2, Link Error.
> [Hardware Error]: cache level: L3/GEN, mem/io: IO, mem-tx: GEN, part-proc: SRC (no timeout)​
> 
> 
> 
> 
> I can lower tRC to ~62, but then my ratios are out with tRC, tRTP, and tWR all being factors of tRFC - without detailed testing, I'm not sure if divisible factors, or lowest timings are more important.
> 
> Any advice appreciated, as not many people seem to be running this type of setup. Thanks.


I'm a bit of a novice, but I'll give it a shot...
tCWL probably shouldn't be -4 from tCL. Maybe try raising it to 18 if you're unstable.
tRDWR and tWRRD seem extremely high, are these auto values?
tRFC should be a multiple of tRC, and ideally tRTP and tWR should be also (but less important)
I don't think tRAS can be lower than tCL + tRCDRD, which in your case would be 37 at minimum.
I'm not sure which timings are rounded up to even numbers when Geardown is enabled - obviously tCL is, not sure of tRCD, tRP, tRAS?
my kit fails with tFAW at 16, and even 20, but you might have more luck given you're on single rank lower density - although it took me hours of prime95 to find this failure.
tWR also fails for me at 12 - I've raised to be equal with my tCL.

Keen to hear if you've made any progress in the past few days.


----------



## drnilly007

nobody.nowhere said:


> I'm on Hynnix MJR as well, although a very different kit and setup: 4x32GB dual rank on a 3970X...
> 
> 
> I'm a bit of a novice, but I'll give it a shot...
> tCWL probably shouldn't be -4 from tCL. Maybe try raising it to 18 if you're unstable.
> tRDWR and tWRRD seem extremely high, are these auto values?
> tRFC should be a multiple of tRC, and ideally tRTP and tWR should be also (but less important)
> I don't think tRAS can be lower than tCL + tRCDRD, which in your case would be 37 at minimum.
> I'm not sure which timings are rounded up to even numbers when Geardown is enabled - obviously tCL is, not sure of tRCD, tRP, tRAS?
> my kit fails with tFAW at 16, and even 20, but you might have more luck given you're on single rank lower density - although it took me hours of prime95 to find this failure.
> tWR also fails for me at 12 - I've raised to be equal with my tCL.
> 
> Keen to hear if you've made any progress in the past few days.











Pretty much the same had to raise tras and trc. Been very stable. One big issue im glad i caught was my mb was auto setting the cldo voltage to 1.1-1.15 which according to some is waay too high.
Been trying out higher speeds but whea error 19 just increases as i go higher. Just keep waiting for more bios agesa updates. Every once in awhile I go back in and try to get higher speed. Its very elusive at this point
Also tfaw is a calculated by trrds x trrdl other combinations commonly used are 4 x 6 tfaw of 24


----------



## Veii

Sleepycat said:


> ClkDrvStr would be increased if signaling integrity was weak by the time you hit your 4th DIMM slot. I believe that if you increase it, the signal strength would be increased, but it also amplifies any noise in the signal too, leading to a higher chance of uncorrectable errors.


Yes and no
Signal integrity (noise) is only bad if,
~ we start with too high procODT (which also limits maximum FCLK)
~ start with very high RTT_PARK
~ overall start with high VDDG and VDDP voltages

Reasons to prefer higher procODT than 40ohm
~ higher capacity dimms 4x16, 2x32
~ low voltage SOC
~ weak mainboard PCB
~ T-Topology and 64gb set
~ 4x B2 PCB (but that can be resolved better)
~ older ryzen generation

ClkDrvStr, RTT, SOC, procODT
all go hand in hand

Weak RTT_PARK will have the side effect that it's "weaker" and might not be able to power the dimms correctly
But for that we have ClkDrvStr & potentially well timed CAD_BUS SETUP timings
The voltage range of each RTT setting changes drastically & so also the amperage that arrives at the dimms

Using strong RTT and high voltage, can lead to some bad results, or on more sensitive X0 PCBs to even full death
While hopefully just a loss of a memory channel at first ~ without anything bad to it
Strong RTTs do have a benefit for XMP scenarios and voltages sub 1.4v
But i'd rather have more voltage & tamed, soo timings can generally be lower ~ than high impedance and very little voltage range + more heat

EDIT:
I forgot to mention about RTT_WR ~ enabling Dynamic On-Die Termination Impedance
Which is a completely different topic, ontop of the weaker RTTs
For example instead of 706 to 636
607 and 706 both worked well as an easy mode for 2 dimms
but 636 adds dynamicODT ~ which smooths out jitter even more








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Carrying on from DDR1 and DDR2 in Part 3, Ryan investigates what makes DDR3 so special, by looking in-depth at its unique features like the Fly-By topology, Read/Write levelling, Dynamic On-Die Termination & ZQ Driver Calibration.




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Just is another dynamic part to tame, when you already work with set CKE High & CKE Low
Probably set CAD_BUS SETUP times that are MCLK specifc
And also set tCKE which is MCLK specific
~ is hard to keep an overview , why your PCB is crashing. It doesn't have to be high voltage to cause a "crash/choke"


----------



## T[]RK

Veii said:


> Give it a go directly at GDM off 1T


Nope. Got Violet Screen of Death after Windows logon (i run ZenTimings to check and AIDA64 - and got it right after).


Veii said:


> First before everything, get it GDM off stable ~ then we can talk


Tested same timings at 1.35V, 1.45V and 1.5V (it's absolute maximum of the board, can't set higher). No luck, always got Violet Screen after run something (like AIDA64).


Veii said:


> i keep hitting the 120A EDC Fuse limit because SOC alone takes 23W out of the whole powerbudget


You see EDC 120A in Ryzen Master? I got similar problem on my GIGABYTE. I solved it by Disable PBO in AMD CBS, but set it to Auto in AMD Overclocking. Now i see in Ryzen Master EDC 140A. It's weird.


----------



## Nd4spdvn

This is what I have settled to since yesterday on my B550 Aorus Pro V2 and 5900x with 4 sticks of 4400 Vipers. No case here using OBT with no fan cooling on DIMMs, though I did reverse the CPU fans on the Noctua NH-D15 having them blow some on the closest CPU DIMM. Not sure if it helps, but in my view some airflow even if hotter is better than no airflow. Previously ran a C16 set at 1.42V rock solid. This C15 one is a bit unusual on the TRAS and TRC, kept them from C16. I tried to boot RAS 30 and RC31 but got some windows autorepair shenanigans and left it for awhile. This CPU is on CO PBO around -18 with positive vcore offset of 0.018V and with a EDC 200A limit set by me and I tried to optimize PBO for all cores to hit 4.95-4.975GHz individually, basically to facilitate all cores oclock (instead of hunting for highest ST frequency), thus optimize for latency as Ryzen is very latency sensitive.
Forgot to take a pic, latest Sandra MCE measured 43.5ns MC intercore latency with 62.5GB BW and 43.9ns MC interthread latency with 144GB BW, these are the best results I got so far in this test/benchmark. I am following this thread with great interest as per Veii's recommendations and advise I feel it is very important to hit the correct/optimized powering on our boards and dimms. Hope this maybe help others with similar setups.


----------



## domdtxdissar

Nd4spdvn said:


> This is what I have settled to since yesterday on my B550 Aorus Pro V2 and 5900x with 4 sticks of 4400 Vipers. No case here using OBT with no fan cooling on DIMMs, though I did reverse the CPU fans on the Noctua NH-D15 having them blow some on the closest CPU DIMM. Not sure if it helps, but in my view some airflow even if hotter is better than no airflow. Previously ran a C16 set at 1.42V rock solid. This C15 one is a bit unusual on the TRAS and TRC, kept them from C16. I tried to boot RAS 30 and RC31 but got some windows autorepair shenanigans and left it for awhile. This CPU is on CO PBO around -18 with positive vcore offset of 0.018V and with a EDC 200A limit set by me and I tried to optimize PBO for all cores to hit 4.95-4.975GHz individually, basically to facilitate all cores oclock (instead of hunting for highest ST frequency), thus optimize for latency as Ryzen is very latency sensitive.
> Forgot to take a pic, latest Sandra MCE measured 43.5ns MC intercore latency with 62.5GB BW and 43.9ns MC interthread latency with 144GB BW, these are the best results I got so far in this test/benchmark. I am following this thread with great interest as per Veii's recommendations and advise I feel it is very important to hit the correct/optimized powering on our boards and dimms. Hope this maybe help others with similar setups.


Here is my 24/7 auto settings for 5950x + 4x8 gigabyte @ 3800:1900
Bloated windows install with nothing disabled











Spoiler: recorded multithreaded (MT) data 



SiSoftware Sandra

Benchmark Results
Inter-Core Bandwidth : 152.42GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
Inter-Core Latency : 42.8ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Inter-Core Bandwidth : 4.76GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Speed
Inter-Core Bandwidth : 43.35MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 0.12ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-U2 Data Latency : 24.0ns
U0-U4 Data Latency : 26.5ns
U0-U6 Data Latency : 23.9ns
U0-U8 Data Latency : 24.9ns
U0-U10 Data Latency : 24.2ns
U0-U12 Data Latency : 25.6ns
U0-U14 Data Latency : 24.7ns
U0-U16 Data Latency : 59.3ns
U0-U18 Data Latency : 58.4ns
U0-U20 Data Latency : 59.3ns
U0-U22 Data Latency : 59.4ns
U0-U24 Data Latency : 59.6ns
U0-U26 Data Latency : 59.2ns
U0-U28 Data Latency : 59.5ns
U0-U30 Data Latency : 59.5ns
U0-U1 Data Latency : 12.3ns
U0-U3 Data Latency : 22.8ns
U0-U5 Data Latency : 24.5ns
U0-U7 Data Latency : 23.5ns
U0-U9 Data Latency : 24.5ns
U0-U11 Data Latency : 26.7ns
U0-U13 Data Latency : 25.6ns
U0-U15 Data Latency : 24.6ns
U0-U17 Data Latency : 57.7ns
U0-U19 Data Latency : 57.4ns
U0-U21 Data Latency : 58.2ns
U0-U23 Data Latency : 59.4ns
U0-U25 Data Latency : 58.8ns
U0-U27 Data Latency : 59.5ns
U0-U29 Data Latency : 59.6ns
U0-U31 Data Latency : 59.6ns
U2-U4 Data Latency : 23.5ns
U2-U6 Data Latency : 25.1ns
U2-U8 Data Latency : 23.9ns
U2-U10 Data Latency : 26.0ns
U2-U12 Data Latency : 24.6ns
U2-U14 Data Latency : 25.7ns
U2-U16 Data Latency : 56.9ns
U2-U18 Data Latency : 57.6ns
U2-U20 Data Latency : 58.2ns
U2-U22 Data Latency : 58.5ns
U2-U24 Data Latency : 58.9ns
U2-U26 Data Latency : 59.2ns
U2-U28 Data Latency : 60.8ns
U2-U30 Data Latency : 59.3ns
U2-U1 Data Latency : 22.6ns
U2-U3 Data Latency : 12.8ns
U2-U5 Data Latency : 23.3ns
U2-U7 Data Latency : 25.2ns
U2-U9 Data Latency : 23.9ns
U2-U11 Data Latency : 26.0ns
U2-U13 Data Latency : 24.6ns
U2-U15 Data Latency : 25.8ns
U2-U17 Data Latency : 57.5ns
U2-U19 Data Latency : 57.4ns
U2-U21 Data Latency : 58.1ns
U2-U23 Data Latency : 58.6ns
U2-U25 Data Latency : 58.8ns
U2-U27 Data Latency : 59.1ns
U2-U29 Data Latency : 59.1ns
U2-U31 Data Latency : 60.5ns
U4-U6 Data Latency : 24.2ns
U4-U8 Data Latency : 26.5ns
U4-U10 Data Latency : 24.9ns
U4-U12 Data Latency : 27.0ns
U4-U14 Data Latency : 25.9ns
U4-U16 Data Latency : 58.3ns
U4-U18 Data Latency : 57.9ns
U4-U20 Data Latency : 58.7ns
U4-U22 Data Latency : 58.9ns
U4-U24 Data Latency : 60.0ns
U4-U26 Data Latency : 59.5ns
U4-U28 Data Latency : 60.2ns
U4-U30 Data Latency : 60.1ns
U4-U1 Data Latency : 24.6ns
U4-U3 Data Latency : 23.4ns
U4-U5 Data Latency : 12.9ns
U4-U7 Data Latency : 24.2ns
U4-U9 Data Latency : 26.6ns
U4-U11 Data Latency : 24.9ns
U4-U13 Data Latency : 27.1ns
U4-U15 Data Latency : 25.9ns
U4-U17 Data Latency : 58.7ns
U4-U19 Data Latency : 58.2ns
U4-U21 Data Latency : 58.8ns
U4-U23 Data Latency : 59.2ns
U4-U25 Data Latency : 59.5ns
U4-U27 Data Latency : 59.9ns
U4-U29 Data Latency : 60.4ns
U4-U31 Data Latency : 60.2ns
U6-U8 Data Latency : 24.5ns
U6-U10 Data Latency : 26.7ns
U6-U12 Data Latency : 25.1ns
U6-U14 Data Latency : 26.2ns
U6-U16 Data Latency : 59.8ns
U6-U18 Data Latency : 58.3ns
U6-U20 Data Latency : 59.0ns
U6-U22 Data Latency : 59.3ns
U6-U24 Data Latency : 59.5ns
U6-U26 Data Latency : 60.2ns
U6-U28 Data Latency : 59.9ns
U6-U30 Data Latency : 60.7ns
U6-U1 Data Latency : 23.2ns
U6-U3 Data Latency : 25.1ns
U6-U5 Data Latency : 24.0ns
U6-U7 Data Latency : 12.8ns
U6-U9 Data Latency : 24.5ns
U6-U11 Data Latency : 26.7ns
U6-U13 Data Latency : 25.2ns
U6-U15 Data Latency : 26.2ns
U6-U17 Data Latency : 58.8ns
U6-U19 Data Latency : 59.5ns
U6-U21 Data Latency : 58.6ns
U6-U23 Data Latency : 59.7ns
U6-U25 Data Latency : 60.2ns
U6-U27 Data Latency : 60.4ns
U6-U29 Data Latency : 60.0ns
U6-U31 Data Latency : 60.5ns
U8-U10 Data Latency : 25.1ns
U8-U12 Data Latency : 27.5ns
U8-U14 Data Latency : 26.1ns
U8-U16 Data Latency : 58.6ns
U8-U18 Data Latency : 58.5ns
U8-U20 Data Latency : 59.1ns
U8-U22 Data Latency : 59.7ns
U8-U24 Data Latency : 60.1ns
U8-U26 Data Latency : 60.1ns
U8-U28 Data Latency : 60.8ns
U8-U30 Data Latency : 61.1ns
U8-U1 Data Latency : 24.4ns
U8-U3 Data Latency : 23.8ns
U8-U5 Data Latency : 26.3ns
U8-U7 Data Latency : 24.5ns
U8-U9 Data Latency : 12.4ns
U8-U11 Data Latency : 25.1ns
U8-U13 Data Latency : 27.6ns
U8-U15 Data Latency : 26.1ns
U8-U17 Data Latency : 58.5ns
U8-U19 Data Latency : 58.4ns
U8-U21 Data Latency : 59.0ns
U8-U23 Data Latency : 59.5ns
U8-U25 Data Latency : 59.5ns
U8-U27 Data Latency : 60.0ns
U8-U29 Data Latency : 60.6ns
U8-U31 Data Latency : 60.6ns
U10-U12 Data Latency : 25.7ns
U10-U14 Data Latency : 26.9ns
U10-U16 Data Latency : 59.4ns
U10-U18 Data Latency : 59.1ns
U10-U20 Data Latency : 59.4ns
U10-U22 Data Latency : 59.9ns
U10-U24 Data Latency : 60.1ns
U10-U26 Data Latency : 60.6ns
U10-U28 Data Latency : 61.2ns
U10-U30 Data Latency : 60.8ns
U10-U1 Data Latency : 24.2ns
U10-U3 Data Latency : 27.2ns
U10-U5 Data Latency : 24.6ns
U10-U7 Data Latency : 26.6ns
U10-U9 Data Latency : 25.2ns
U10-U11 Data Latency : 12.8ns
U10-U13 Data Latency : 25.8ns
U10-U15 Data Latency : 26.9ns
U10-U17 Data Latency : 58.8ns
U10-U19 Data Latency : 59.2ns
U10-U21 Data Latency : 59.4ns
U10-U23 Data Latency : 59.8ns
U10-U25 Data Latency : 60.3ns
U10-U27 Data Latency : 60.0ns
U10-U29 Data Latency : 60.5ns
U10-U31 Data Latency : 60.6ns
U12-U14 Data Latency : 26.8ns
U12-U16 Data Latency : 59.7ns
U12-U18 Data Latency : 59.0ns
U12-U20 Data Latency : 59.9ns
U12-U22 Data Latency : 60.1ns
U12-U24 Data Latency : 60.8ns
U12-U26 Data Latency : 60.6ns
U12-U28 Data Latency : 61.2ns
U12-U30 Data Latency : 61.9ns
U12-U1 Data Latency : 25.8ns
U12-U3 Data Latency : 24.4ns
U12-U5 Data Latency : 27.0ns
U12-U7 Data Latency : 24.9ns
U12-U9 Data Latency : 27.5ns
U12-U11 Data Latency : 25.6ns
U12-U13 Data Latency : 12.7ns
U12-U15 Data Latency : 26.8ns
U12-U17 Data Latency : 59.8ns
U12-U19 Data Latency : 59.1ns
U12-U21 Data Latency : 59.8ns
U12-U23 Data Latency : 60.0ns
U12-U25 Data Latency : 60.9ns
U12-U27 Data Latency : 60.7ns
U12-U29 Data Latency : 61.3ns
U12-U31 Data Latency : 61.2ns
U14-U16 Data Latency : 59.9ns
U14-U18 Data Latency : 58.9ns
U14-U20 Data Latency : 59.5ns
U14-U22 Data Latency : 59.9ns
U14-U24 Data Latency : 60.1ns
U14-U26 Data Latency : 60.7ns
U14-U28 Data Latency : 60.2ns
U14-U30 Data Latency : 61.3ns
U14-U1 Data Latency : 24.4ns
U14-U3 Data Latency : 25.6ns
U14-U5 Data Latency : 25.5ns
U14-U7 Data Latency : 28.5ns
U14-U9 Data Latency : 26.1ns
U14-U11 Data Latency : 27.0ns
U14-U13 Data Latency : 26.6ns
U14-U15 Data Latency : 12.8ns
U14-U17 Data Latency : 59.5ns
U14-U19 Data Latency : 59.7ns
U14-U21 Data Latency : 58.9ns
U14-U23 Data Latency : 60.3ns
U14-U25 Data Latency : 60.4ns
U14-U27 Data Latency : 60.8ns
U14-U29 Data Latency : 61.1ns
U14-U31 Data Latency : 60.9ns
U16-U18 Data Latency : 23.2ns
U16-U20 Data Latency : 25.1ns
U16-U22 Data Latency : 24.1ns
U16-U24 Data Latency : 25.5ns
U16-U26 Data Latency : 27.1ns
U16-U28 Data Latency : 26.2ns
U16-U30 Data Latency : 25.1ns
U16-U1 Data Latency : 57.6ns
U16-U3 Data Latency : 58.1ns
U16-U5 Data Latency : 58.3ns
U16-U7 Data Latency : 60.0ns
U16-U9 Data Latency : 58.5ns
U16-U11 Data Latency : 59.5ns
U16-U13 Data Latency : 59.2ns
U16-U15 Data Latency : 59.5ns
U16-U17 Data Latency : 13.0ns
U16-U19 Data Latency : 23.4ns
U16-U21 Data Latency : 25.0ns
U16-U23 Data Latency : 24.1ns
U16-U25 Data Latency : 25.5ns
U16-U27 Data Latency : 24.7ns
U16-U29 Data Latency : 28.9ns
U16-U31 Data Latency : 25.1ns
U18-U20 Data Latency : 23.7ns
U18-U22 Data Latency : 25.7ns
U18-U24 Data Latency : 24.5ns
U18-U26 Data Latency : 26.4ns
U18-U28 Data Latency : 25.0ns
U18-U30 Data Latency : 26.2ns
U18-U1 Data Latency : 57.8ns
U18-U3 Data Latency : 58.1ns
U18-U5 Data Latency : 58.2ns
U18-U7 Data Latency : 59.2ns
U18-U9 Data Latency : 58.5ns
U18-U11 Data Latency : 59.2ns
U18-U13 Data Latency : 59.7ns
U18-U15 Data Latency : 59.4ns
U18-U17 Data Latency : 23.2ns
U18-U19 Data Latency : 12.9ns
U18-U21 Data Latency : 23.8ns
U18-U23 Data Latency : 25.7ns
U18-U25 Data Latency : 24.5ns
U18-U27 Data Latency : 26.5ns
U18-U29 Data Latency : 25.1ns
U18-U31 Data Latency : 26.2ns
U20-U22 Data Latency : 24.5ns
U20-U24 Data Latency : 26.7ns
U20-U26 Data Latency : 25.3ns
U20-U28 Data Latency : 27.4ns
U20-U30 Data Latency : 26.2ns
U20-U1 Data Latency : 56.9ns
U20-U3 Data Latency : 57.6ns
U20-U5 Data Latency : 58.6ns
U20-U7 Data Latency : 58.6ns
U20-U9 Data Latency : 59.3ns
U20-U11 Data Latency : 59.2ns
U20-U13 Data Latency : 59.5ns
U20-U15 Data Latency : 59.3ns
U20-U17 Data Latency : 25.1ns
U20-U19 Data Latency : 23.7ns
U20-U21 Data Latency : 12.9ns
U20-U23 Data Latency : 24.5ns
U20-U25 Data Latency : 26.9ns
U20-U27 Data Latency : 25.3ns
U20-U29 Data Latency : 27.6ns
U20-U31 Data Latency : 26.0ns
U22-U24 Data Latency : 25.1ns
U22-U26 Data Latency : 27.1ns
U22-U28 Data Latency : 25.6ns
U22-U30 Data Latency : 26.6ns
U22-U1 Data Latency : 58.4ns
U22-U3 Data Latency : 58.9ns
U22-U5 Data Latency : 58.8ns
U22-U7 Data Latency : 59.6ns
U22-U9 Data Latency : 59.2ns
U22-U11 Data Latency : 59.8ns
U22-U13 Data Latency : 60.4ns
U22-U15 Data Latency : 60.5ns
U22-U17 Data Latency : 23.8ns
U22-U19 Data Latency : 25.6ns
U22-U21 Data Latency : 24.4ns
U22-U23 Data Latency : 13.0ns
U22-U25 Data Latency : 25.1ns
U22-U27 Data Latency : 27.1ns
U22-U29 Data Latency : 25.6ns
U22-U31 Data Latency : 26.7ns
U24-U26 Data Latency : 25.6ns
U24-U28 Data Latency : 28.1ns
U24-U30 Data Latency : 26.7ns
U24-U1 Data Latency : 58.2ns
U24-U3 Data Latency : 58.4ns
U24-U5 Data Latency : 59.4ns
U24-U7 Data Latency : 60.0ns
U24-U9 Data Latency : 60.2ns
U24-U11 Data Latency : 59.8ns
U24-U13 Data Latency : 60.9ns
U24-U15 Data Latency : 60.0ns
U24-U17 Data Latency : 25.6ns
U24-U19 Data Latency : 24.3ns
U24-U21 Data Latency : 26.7ns
U24-U23 Data Latency : 24.9ns
U24-U25 Data Latency : 12.9ns
U24-U27 Data Latency : 25.6ns
U24-U29 Data Latency : 28.2ns
U24-U31 Data Latency : 26.6ns
U26-U28 Data Latency : 26.2ns
U26-U30 Data Latency : 30.1ns
U26-U1 Data Latency : 59.5ns
U26-U3 Data Latency : 59.5ns
U26-U5 Data Latency : 59.8ns
U26-U7 Data Latency : 60.0ns
U26-U9 Data Latency : 60.5ns
U26-U11 Data Latency : 61.2ns
U26-U13 Data Latency : 60.5ns
U26-U15 Data Latency : 60.8ns
U26-U17 Data Latency : 24.5ns
U26-U19 Data Latency : 26.3ns
U26-U21 Data Latency : 25.1ns
U26-U23 Data Latency : 27.0ns
U26-U25 Data Latency : 25.7ns
U26-U27 Data Latency : 13.0ns
U26-U29 Data Latency : 26.2ns
U26-U31 Data Latency : 27.4ns
U28-U30 Data Latency : 30.5ns
U28-U1 Data Latency : 59.4ns
U28-U3 Data Latency : 59.3ns
U28-U5 Data Latency : 60.2ns
U28-U7 Data Latency : 60.3ns
U28-U9 Data Latency : 60.9ns
U28-U11 Data Latency : 60.8ns
U28-U13 Data Latency : 60.7ns
U28-U15 Data Latency : 61.4ns
U28-U17 Data Latency : 24.5ns
U28-U19 Data Latency : 24.7ns
U28-U21 Data Latency : 25.0ns
U28-U23 Data Latency : 25.4ns
U28-U25 Data Latency : 25.8ns
U28-U27 Data Latency : 25.8ns
U28-U29 Data Latency : 13.1ns
U28-U31 Data Latency : 26.5ns
U30-U1 Data Latency : 59.5ns
U30-U3 Data Latency : 59.6ns
U30-U5 Data Latency : 60.1ns
U30-U7 Data Latency : 61.4ns
U30-U9 Data Latency : 61.5ns
U30-U11 Data Latency : 60.8ns
U30-U13 Data Latency : 61.5ns
U30-U15 Data Latency : 61.5ns
U30-U17 Data Latency : 24.8ns
U30-U19 Data Latency : 24.9ns
U30-U21 Data Latency : 25.2ns
U30-U23 Data Latency : 25.7ns
U30-U25 Data Latency : 25.7ns
U30-U27 Data Latency : 26.3ns
U30-U29 Data Latency : 26.5ns
U30-U31 Data Latency : 13.2ns
U1-U3 Data Latency : 22.5ns
U1-U5 Data Latency : 23.1ns
U1-U7 Data Latency : 23.7ns
U1-U9 Data Latency : 23.6ns
U1-U11 Data Latency : 24.2ns
U1-U13 Data Latency : 24.5ns
U1-U15 Data Latency : 24.6ns
U1-U17 Data Latency : 57.7ns
U1-U19 Data Latency : 57.2ns
U1-U21 Data Latency : 58.2ns
U1-U23 Data Latency : 58.3ns
U1-U25 Data Latency : 58.9ns
U1-U27 Data Latency : 59.3ns
U1-U29 Data Latency : 59.9ns
U1-U31 Data Latency : 60.9ns
U3-U5 Data Latency : 24.5ns
U3-U7 Data Latency : 25.5ns
U3-U9 Data Latency : 24.0ns
U3-U11 Data Latency : 26.1ns
U3-U13 Data Latency : 24.6ns
U3-U15 Data Latency : 25.7ns
U3-U17 Data Latency : 60.5ns
U3-U19 Data Latency : 60.2ns
U3-U21 Data Latency : 59.6ns
U3-U23 Data Latency : 60.4ns
U3-U25 Data Latency : 60.4ns
U3-U27 Data Latency : 59.7ns
U3-U29 Data Latency : 60.3ns
U3-U31 Data Latency : 60.4ns
U5-U7 Data Latency : 24.0ns
U5-U9 Data Latency : 26.4ns
U5-U11 Data Latency : 24.7ns
U5-U13 Data Latency : 26.8ns
U5-U15 Data Latency : 25.5ns
U5-U17 Data Latency : 60.7ns
U5-U19 Data Latency : 60.7ns
U5-U21 Data Latency : 60.9ns
U5-U23 Data Latency : 60.8ns
U5-U25 Data Latency : 60.8ns
U5-U27 Data Latency : 60.7ns
U5-U29 Data Latency : 60.4ns
U5-U31 Data Latency : 61.4ns
U7-U9 Data Latency : 24.3ns
U7-U11 Data Latency : 26.4ns
U7-U13 Data Latency : 25.9ns
U7-U15 Data Latency : 26.4ns
U7-U17 Data Latency : 60.3ns
U7-U19 Data Latency : 60.7ns
U7-U21 Data Latency : 61.3ns
U7-U23 Data Latency : 61.0ns
U7-U25 Data Latency : 60.9ns
U7-U27 Data Latency : 60.9ns
U7-U29 Data Latency : 60.6ns
U7-U31 Data Latency : 60.9ns
U9-U11 Data Latency : 26.1ns
U9-U13 Data Latency : 27.1ns
U9-U15 Data Latency : 26.9ns
U9-U17 Data Latency : 60.0ns
U9-U19 Data Latency : 60.1ns
U9-U21 Data Latency : 60.9ns
U9-U23 Data Latency : 60.5ns
U9-U25 Data Latency : 61.2ns
U9-U27 Data Latency : 60.6ns
U9-U29 Data Latency : 60.8ns
U9-U31 Data Latency : 60.8ns
U11-U13 Data Latency : 27.5ns
U11-U15 Data Latency : 27.4ns
U11-U17 Data Latency : 60.7ns
U11-U19 Data Latency : 60.9ns
U11-U21 Data Latency : 59.6ns
U11-U23 Data Latency : 60.8ns
U11-U25 Data Latency : 60.4ns
U11-U27 Data Latency : 60.5ns
U11-U29 Data Latency : 60.7ns
U11-U31 Data Latency : 60.1ns
U13-U15 Data Latency : 28.3ns
U13-U17 Data Latency : 59.8ns
U13-U19 Data Latency : 59.2ns
U13-U21 Data Latency : 60.5ns
U13-U23 Data Latency : 60.3ns
U13-U25 Data Latency : 59.9ns
U13-U27 Data Latency : 60.5ns
U13-U29 Data Latency : 61.2ns
U13-U31 Data Latency : 61.4ns
U15-U17 Data Latency : 60.4ns
U15-U19 Data Latency : 60.9ns
U15-U21 Data Latency : 60.2ns
U15-U23 Data Latency : 60.6ns
U15-U25 Data Latency : 60.6ns
U15-U27 Data Latency : 60.9ns
U15-U29 Data Latency : 60.7ns
U15-U31 Data Latency : 60.9ns
U17-U19 Data Latency : 25.3ns
U17-U21 Data Latency : 25.7ns
U17-U23 Data Latency : 24.6ns
U17-U25 Data Latency : 25.5ns
U17-U27 Data Latency : 24.6ns
U17-U29 Data Latency : 26.2ns
U17-U31 Data Latency : 24.9ns
U19-U21 Data Latency : 25.0ns
U19-U23 Data Latency : 26.0ns
U19-U25 Data Latency : 24.6ns
U19-U27 Data Latency : 26.5ns
U19-U29 Data Latency : 25.0ns
U19-U31 Data Latency : 26.1ns
U21-U23 Data Latency : 24.6ns
U21-U25 Data Latency : 27.0ns
U21-U27 Data Latency : 25.1ns
U21-U29 Data Latency : 27.4ns
U21-U31 Data Latency : 26.0ns
U23-U25 Data Latency : 24.9ns
U23-U27 Data Latency : 26.8ns
U23-U29 Data Latency : 26.3ns
U23-U31 Data Latency : 26.9ns
U25-U27 Data Latency : 26.5ns
U25-U29 Data Latency : 27.6ns
U25-U31 Data Latency : 27.5ns
U27-U29 Data Latency : 28.1ns
U27-U31 Data Latency : 27.8ns
U29-U31 Data Latency : 28.8ns
1x 64bytes Blocks Bandwidth : 19GB/s
4x 64bytes Blocks Bandwidth : 26.7GB/s
4x 256bytes Blocks Bandwidth : 100.75GB/s
4x 1kB Blocks Bandwidth : 314.12GB/s
4x 4kB Blocks Bandwidth : 459.66GB/s
16x 4kB Blocks Bandwidth : 625.22GB/s
4x 64kB Blocks Bandwidth : 838GB/s
16x 64kB Blocks Bandwidth : 342.14GB/s
8x 256kB Blocks Bandwidth : 388.27GB/s
4x 1MB Blocks Bandwidth : 394.55GB/s
8x 1MB Blocks Bandwidth : 39.37GB/s
8x 4MB Blocks Bandwidth : 19.71GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (16C 32T 3.6GHz/5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : MUAF210009
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
Platform Compliance : x64
Buffer Memory Accesses : No
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
Speed : 3.6GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
Cores per Processor : 16 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : MUAF210009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Tip 223 : CPU speed, under load, lower than rated speed. Check power management settings.
Notice 242 : Dynamic OverClocking/Turbo engaged. Performance will not be consistent!
Tip 2 : Double-click tip or press Enter while a tip is selected for more information about the tip.





Spoiler: recorded multi-core only (MC) data



SiSoftware Sandra

Benchmark Results
Inter-Core Bandwidth : 78GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
Inter-Core Latency : 44.3ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Inter-Core Bandwidth : 4.87GB/s
No. Threads : 16
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Speed
Inter-Core Bandwidth : 22.17MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 0.12ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U6 U2-U8 U4-U10 U12-U14 U16-U26 U18-U24 U20-U22 U28-U30
U0-U2 Data Latency : 24.7ns
U0-U4 Data Latency : 25.1ns
U0-U6 Data Latency : 24.2ns
U0-U8 Data Latency : 24.4ns
U0-U10 Data Latency : 24.2ns
U0-U12 Data Latency : 25.7ns
U0-U14 Data Latency : 24.4ns
U0-U16 Data Latency : 60.5ns
U0-U18 Data Latency : 60.6ns
U0-U20 Data Latency : 60.9ns
U0-U22 Data Latency : 59.6ns
U0-U24 Data Latency : 60.2ns
U0-U26 Data Latency : 61.0ns
U0-U28 Data Latency : 60.2ns
U0-U30 Data Latency : 60.5ns
U2-U4 Data Latency : 24.8ns
U2-U6 Data Latency : 25.6ns
U2-U8 Data Latency : 23.9ns
U2-U10 Data Latency : 26.1ns
U2-U12 Data Latency : 24.5ns
U2-U14 Data Latency : 25.6ns
U2-U16 Data Latency : 60.6ns
U2-U18 Data Latency : 60.7ns
U2-U20 Data Latency : 60.8ns
U2-U22 Data Latency : 59.9ns
U2-U24 Data Latency : 60.7ns
U2-U26 Data Latency : 59.8ns
U2-U28 Data Latency : 60.2ns
U2-U30 Data Latency : 60.1ns
U4-U6 Data Latency : 24.3ns
U4-U8 Data Latency : 26.6ns
U4-U10 Data Latency : 24.8ns
U4-U12 Data Latency : 27.0ns
U4-U14 Data Latency : 25.7ns
U4-U16 Data Latency : 61.5ns
U4-U18 Data Latency : 60.9ns
U4-U20 Data Latency : 60.8ns
U4-U22 Data Latency : 61.3ns
U4-U24 Data Latency : 61.5ns
U4-U26 Data Latency : 61.5ns
U4-U28 Data Latency : 61.2ns
U4-U30 Data Latency : 61.5ns
U6-U8 Data Latency : 24.3ns
U6-U10 Data Latency : 26.4ns
U6-U12 Data Latency : 25.7ns
U6-U14 Data Latency : 26.4ns
U6-U16 Data Latency : 60.9ns
U6-U18 Data Latency : 60.2ns
U6-U20 Data Latency : 60.9ns
U6-U22 Data Latency : 60.4ns
U6-U24 Data Latency : 60.1ns
U6-U26 Data Latency : 60.6ns
U6-U28 Data Latency : 60.5ns
U6-U30 Data Latency : 60.4ns
U8-U10 Data Latency : 26.1ns
U8-U12 Data Latency : 27.1ns
U8-U14 Data Latency : 26.9ns
U8-U16 Data Latency : 60.2ns
U8-U18 Data Latency : 59.7ns
U8-U20 Data Latency : 60.8ns
U8-U22 Data Latency : 60.1ns
U8-U24 Data Latency : 60.0ns
U8-U26 Data Latency : 60.5ns
U8-U28 Data Latency : 61.5ns
U8-U30 Data Latency : 60.3ns
U10-U12 Data Latency : 27.5ns
U10-U14 Data Latency : 27.4ns
U10-U16 Data Latency : 60.2ns
U10-U18 Data Latency : 60.5ns
U10-U20 Data Latency : 60.5ns
U10-U22 Data Latency : 60.0ns
U10-U24 Data Latency : 60.4ns
U10-U26 Data Latency : 60.6ns
U10-U28 Data Latency : 60.5ns
U10-U30 Data Latency : 61.0ns
U12-U14 Data Latency : 28.3ns
U12-U16 Data Latency : 60.4ns
U12-U18 Data Latency : 59.3ns
U12-U20 Data Latency : 59.8ns
U12-U22 Data Latency : 59.6ns
U12-U24 Data Latency : 60.6ns
U12-U26 Data Latency : 60.3ns
U12-U28 Data Latency : 61.0ns
U12-U30 Data Latency : 60.6ns
U14-U16 Data Latency : 60.1ns
U14-U18 Data Latency : 60.1ns
U14-U20 Data Latency : 60.1ns
U14-U22 Data Latency : 60.0ns
U14-U24 Data Latency : 60.8ns
U14-U26 Data Latency : 60.6ns
U14-U28 Data Latency : 60.8ns
U14-U30 Data Latency : 61.1ns
U16-U18 Data Latency : 25.3ns
U16-U20 Data Latency : 25.5ns
U16-U22 Data Latency : 24.6ns
U16-U24 Data Latency : 25.5ns
U16-U26 Data Latency : 24.5ns
U16-U28 Data Latency : 26.2ns
U16-U30 Data Latency : 24.9ns
U18-U20 Data Latency : 24.9ns
U18-U22 Data Latency : 26.0ns
U18-U24 Data Latency : 24.4ns
U18-U26 Data Latency : 26.5ns
U18-U28 Data Latency : 24.9ns
U18-U30 Data Latency : 26.1ns
U20-U22 Data Latency : 24.5ns
U20-U24 Data Latency : 26.9ns
U20-U26 Data Latency : 25.0ns
U20-U28 Data Latency : 27.3ns
U20-U30 Data Latency : 25.9ns
U22-U24 Data Latency : 24.7ns
U22-U26 Data Latency : 26.7ns
U22-U28 Data Latency : 26.3ns
U22-U30 Data Latency : 26.8ns
U24-U26 Data Latency : 26.5ns
U24-U28 Data Latency : 27.6ns
U24-U30 Data Latency : 27.3ns
U26-U28 Data Latency : 28.0ns
U26-U30 Data Latency : 27.8ns
U28-U30 Data Latency : 28.8ns
1x 64bytes Blocks Bandwidth : 3.2GB/s
4x 64bytes Blocks Bandwidth : 5.5GB/s
4x 256bytes Blocks Bandwidth : 21.44GB/s
4x 1kB Blocks Bandwidth : 95.82GB/s
4x 4kB Blocks Bandwidth : 178.67GB/s
16x 4kB Blocks Bandwidth : 129GB/s
4x 64kB Blocks Bandwidth : 150.87GB/s
16x 64kB Blocks Bandwidth : 268GB/s
8x 256kB Blocks Bandwidth : 419.62GB/s
4x 1MB Blocks Bandwidth : 417.85GB/s
8x 1MB Blocks Bandwidth : 415.47GB/s
8x 4MB Blocks Bandwidth : 20.48GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (16C 32T 3.6GHz/5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : MUAF210009
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
Platform Compliance : x64
Buffer Memory Accesses : No
No. Threads : 16
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
Speed : 3.6GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
Cores per Processor : 16 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : MUAF210009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Tip 223 : CPU speed, under load, lower than rated speed. Check power management settings.
Notice 242 : Dynamic OverClocking/Turbo engaged. Performance will not be consistent!
Tip 2 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## Nd4spdvn

domdtxdissar said:


> Here is my 24/7 auto settings for 5950x + 4x8 gigabyte @ 3800:1900
> Bloated windows install with nothing disabled
> View attachment 2483282
> 
> 
> 
> 
> Spoiler: recorded multithreaded (MT) data
> 
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Inter-Core Bandwidth : 152.42GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> Inter-Core Latency : 42.8ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Inter-Core Bandwidth : 4.76GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Speed
> Inter-Core Bandwidth : 43.35MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Inter-Core Latency : 0.12ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-U2 Data Latency : 24.0ns
> U0-U4 Data Latency : 26.5ns
> U0-U6 Data Latency : 23.9ns
> U0-U8 Data Latency : 24.9ns
> U0-U10 Data Latency : 24.2ns
> U0-U12 Data Latency : 25.6ns
> U0-U14 Data Latency : 24.7ns
> U0-U16 Data Latency : 59.3ns
> U0-U18 Data Latency : 58.4ns
> U0-U20 Data Latency : 59.3ns
> U0-U22 Data Latency : 59.4ns
> U0-U24 Data Latency : 59.6ns
> U0-U26 Data Latency : 59.2ns
> U0-U28 Data Latency : 59.5ns
> U0-U30 Data Latency : 59.5ns
> U0-U1 Data Latency : 12.3ns
> U0-U3 Data Latency : 22.8ns
> U0-U5 Data Latency : 24.5ns
> U0-U7 Data Latency : 23.5ns
> U0-U9 Data Latency : 24.5ns
> U0-U11 Data Latency : 26.7ns
> U0-U13 Data Latency : 25.6ns
> U0-U15 Data Latency : 24.6ns
> U0-U17 Data Latency : 57.7ns
> U0-U19 Data Latency : 57.4ns
> U0-U21 Data Latency : 58.2ns
> U0-U23 Data Latency : 59.4ns
> U0-U25 Data Latency : 58.8ns
> U0-U27 Data Latency : 59.5ns
> U0-U29 Data Latency : 59.6ns
> U0-U31 Data Latency : 59.6ns
> U2-U4 Data Latency : 23.5ns
> U2-U6 Data Latency : 25.1ns
> U2-U8 Data Latency : 23.9ns
> U2-U10 Data Latency : 26.0ns
> U2-U12 Data Latency : 24.6ns
> U2-U14 Data Latency : 25.7ns
> U2-U16 Data Latency : 56.9ns
> U2-U18 Data Latency : 57.6ns
> U2-U20 Data Latency : 58.2ns
> U2-U22 Data Latency : 58.5ns
> U2-U24 Data Latency : 58.9ns
> U2-U26 Data Latency : 59.2ns
> U2-U28 Data Latency : 60.8ns
> U2-U30 Data Latency : 59.3ns
> U2-U1 Data Latency : 22.6ns
> U2-U3 Data Latency : 12.8ns
> U2-U5 Data Latency : 23.3ns
> U2-U7 Data Latency : 25.2ns
> U2-U9 Data Latency : 23.9ns
> U2-U11 Data Latency : 26.0ns
> U2-U13 Data Latency : 24.6ns
> U2-U15 Data Latency : 25.8ns
> U2-U17 Data Latency : 57.5ns
> U2-U19 Data Latency : 57.4ns
> U2-U21 Data Latency : 58.1ns
> U2-U23 Data Latency : 58.6ns
> U2-U25 Data Latency : 58.8ns
> U2-U27 Data Latency : 59.1ns
> U2-U29 Data Latency : 59.1ns
> U2-U31 Data Latency : 60.5ns
> U4-U6 Data Latency : 24.2ns
> U4-U8 Data Latency : 26.5ns
> U4-U10 Data Latency : 24.9ns
> U4-U12 Data Latency : 27.0ns
> U4-U14 Data Latency : 25.9ns
> U4-U16 Data Latency : 58.3ns
> U4-U18 Data Latency : 57.9ns
> U4-U20 Data Latency : 58.7ns
> U4-U22 Data Latency : 58.9ns
> U4-U24 Data Latency : 60.0ns
> U4-U26 Data Latency : 59.5ns
> U4-U28 Data Latency : 60.2ns
> U4-U30 Data Latency : 60.1ns
> U4-U1 Data Latency : 24.6ns
> U4-U3 Data Latency : 23.4ns
> U4-U5 Data Latency : 12.9ns
> U4-U7 Data Latency : 24.2ns
> U4-U9 Data Latency : 26.6ns
> U4-U11 Data Latency : 24.9ns
> U4-U13 Data Latency : 27.1ns
> U4-U15 Data Latency : 25.9ns
> U4-U17 Data Latency : 58.7ns
> U4-U19 Data Latency : 58.2ns
> U4-U21 Data Latency : 58.8ns
> U4-U23 Data Latency : 59.2ns
> U4-U25 Data Latency : 59.5ns
> U4-U27 Data Latency : 59.9ns
> U4-U29 Data Latency : 60.4ns
> U4-U31 Data Latency : 60.2ns
> U6-U8 Data Latency : 24.5ns
> U6-U10 Data Latency : 26.7ns
> U6-U12 Data Latency : 25.1ns
> U6-U14 Data Latency : 26.2ns
> U6-U16 Data Latency : 59.8ns
> U6-U18 Data Latency : 58.3ns
> U6-U20 Data Latency : 59.0ns
> U6-U22 Data Latency : 59.3ns
> U6-U24 Data Latency : 59.5ns
> U6-U26 Data Latency : 60.2ns
> U6-U28 Data Latency : 59.9ns
> U6-U30 Data Latency : 60.7ns
> U6-U1 Data Latency : 23.2ns
> U6-U3 Data Latency : 25.1ns
> U6-U5 Data Latency : 24.0ns
> U6-U7 Data Latency : 12.8ns
> U6-U9 Data Latency : 24.5ns
> U6-U11 Data Latency : 26.7ns
> U6-U13 Data Latency : 25.2ns
> U6-U15 Data Latency : 26.2ns
> U6-U17 Data Latency : 58.8ns
> U6-U19 Data Latency : 59.5ns
> U6-U21 Data Latency : 58.6ns
> U6-U23 Data Latency : 59.7ns
> U6-U25 Data Latency : 60.2ns
> U6-U27 Data Latency : 60.4ns
> U6-U29 Data Latency : 60.0ns
> U6-U31 Data Latency : 60.5ns
> U8-U10 Data Latency : 25.1ns
> U8-U12 Data Latency : 27.5ns
> U8-U14 Data Latency : 26.1ns
> U8-U16 Data Latency : 58.6ns
> U8-U18 Data Latency : 58.5ns
> U8-U20 Data Latency : 59.1ns
> U8-U22 Data Latency : 59.7ns
> U8-U24 Data Latency : 60.1ns
> U8-U26 Data Latency : 60.1ns
> U8-U28 Data Latency : 60.8ns
> U8-U30 Data Latency : 61.1ns
> U8-U1 Data Latency : 24.4ns
> U8-U3 Data Latency : 23.8ns
> U8-U5 Data Latency : 26.3ns
> U8-U7 Data Latency : 24.5ns
> U8-U9 Data Latency : 12.4ns
> U8-U11 Data Latency : 25.1ns
> U8-U13 Data Latency : 27.6ns
> U8-U15 Data Latency : 26.1ns
> U8-U17 Data Latency : 58.5ns
> U8-U19 Data Latency : 58.4ns
> U8-U21 Data Latency : 59.0ns
> U8-U23 Data Latency : 59.5ns
> U8-U25 Data Latency : 59.5ns
> U8-U27 Data Latency : 60.0ns
> U8-U29 Data Latency : 60.6ns
> U8-U31 Data Latency : 60.6ns
> U10-U12 Data Latency : 25.7ns
> U10-U14 Data Latency : 26.9ns
> U10-U16 Data Latency : 59.4ns
> U10-U18 Data Latency : 59.1ns
> U10-U20 Data Latency : 59.4ns
> U10-U22 Data Latency : 59.9ns
> U10-U24 Data Latency : 60.1ns
> U10-U26 Data Latency : 60.6ns
> U10-U28 Data Latency : 61.2ns
> U10-U30 Data Latency : 60.8ns
> U10-U1 Data Latency : 24.2ns
> U10-U3 Data Latency : 27.2ns
> U10-U5 Data Latency : 24.6ns
> U10-U7 Data Latency : 26.6ns
> U10-U9 Data Latency : 25.2ns
> U10-U11 Data Latency : 12.8ns
> U10-U13 Data Latency : 25.8ns
> U10-U15 Data Latency : 26.9ns
> U10-U17 Data Latency : 58.8ns
> U10-U19 Data Latency : 59.2ns
> U10-U21 Data Latency : 59.4ns
> U10-U23 Data Latency : 59.8ns
> U10-U25 Data Latency : 60.3ns
> U10-U27 Data Latency : 60.0ns
> U10-U29 Data Latency : 60.5ns
> U10-U31 Data Latency : 60.6ns
> U12-U14 Data Latency : 26.8ns
> U12-U16 Data Latency : 59.7ns
> U12-U18 Data Latency : 59.0ns
> U12-U20 Data Latency : 59.9ns
> U12-U22 Data Latency : 60.1ns
> U12-U24 Data Latency : 60.8ns
> U12-U26 Data Latency : 60.6ns
> U12-U28 Data Latency : 61.2ns
> U12-U30 Data Latency : 61.9ns
> U12-U1 Data Latency : 25.8ns
> U12-U3 Data Latency : 24.4ns
> U12-U5 Data Latency : 27.0ns
> U12-U7 Data Latency : 24.9ns
> U12-U9 Data Latency : 27.5ns
> U12-U11 Data Latency : 25.6ns
> U12-U13 Data Latency : 12.7ns
> U12-U15 Data Latency : 26.8ns
> U12-U17 Data Latency : 59.8ns
> U12-U19 Data Latency : 59.1ns
> U12-U21 Data Latency : 59.8ns
> U12-U23 Data Latency : 60.0ns
> U12-U25 Data Latency : 60.9ns
> U12-U27 Data Latency : 60.7ns
> U12-U29 Data Latency : 61.3ns
> U12-U31 Data Latency : 61.2ns
> U14-U16 Data Latency : 59.9ns
> U14-U18 Data Latency : 58.9ns
> U14-U20 Data Latency : 59.5ns
> U14-U22 Data Latency : 59.9ns
> U14-U24 Data Latency : 60.1ns
> U14-U26 Data Latency : 60.7ns
> U14-U28 Data Latency : 60.2ns
> U14-U30 Data Latency : 61.3ns
> U14-U1 Data Latency : 24.4ns
> U14-U3 Data Latency : 25.6ns
> U14-U5 Data Latency : 25.5ns
> U14-U7 Data Latency : 28.5ns
> U14-U9 Data Latency : 26.1ns
> U14-U11 Data Latency : 27.0ns
> U14-U13 Data Latency : 26.6ns
> U14-U15 Data Latency : 12.8ns
> U14-U17 Data Latency : 59.5ns
> U14-U19 Data Latency : 59.7ns
> U14-U21 Data Latency : 58.9ns
> U14-U23 Data Latency : 60.3ns
> U14-U25 Data Latency : 60.4ns
> U14-U27 Data Latency : 60.8ns
> U14-U29 Data Latency : 61.1ns
> U14-U31 Data Latency : 60.9ns
> U16-U18 Data Latency : 23.2ns
> U16-U20 Data Latency : 25.1ns
> U16-U22 Data Latency : 24.1ns
> U16-U24 Data Latency : 25.5ns
> U16-U26 Data Latency : 27.1ns
> U16-U28 Data Latency : 26.2ns
> U16-U30 Data Latency : 25.1ns
> U16-U1 Data Latency : 57.6ns
> U16-U3 Data Latency : 58.1ns
> U16-U5 Data Latency : 58.3ns
> U16-U7 Data Latency : 60.0ns
> U16-U9 Data Latency : 58.5ns
> U16-U11 Data Latency : 59.5ns
> U16-U13 Data Latency : 59.2ns
> U16-U15 Data Latency : 59.5ns
> U16-U17 Data Latency : 13.0ns
> U16-U19 Data Latency : 23.4ns
> U16-U21 Data Latency : 25.0ns
> U16-U23 Data Latency : 24.1ns
> U16-U25 Data Latency : 25.5ns
> U16-U27 Data Latency : 24.7ns
> U16-U29 Data Latency : 28.9ns
> U16-U31 Data Latency : 25.1ns
> U18-U20 Data Latency : 23.7ns
> U18-U22 Data Latency : 25.7ns
> U18-U24 Data Latency : 24.5ns
> U18-U26 Data Latency : 26.4ns
> U18-U28 Data Latency : 25.0ns
> U18-U30 Data Latency : 26.2ns
> U18-U1 Data Latency : 57.8ns
> U18-U3 Data Latency : 58.1ns
> U18-U5 Data Latency : 58.2ns
> U18-U7 Data Latency : 59.2ns
> U18-U9 Data Latency : 58.5ns
> U18-U11 Data Latency : 59.2ns
> U18-U13 Data Latency : 59.7ns
> U18-U15 Data Latency : 59.4ns
> U18-U17 Data Latency : 23.2ns
> U18-U19 Data Latency : 12.9ns
> U18-U21 Data Latency : 23.8ns
> U18-U23 Data Latency : 25.7ns
> U18-U25 Data Latency : 24.5ns
> U18-U27 Data Latency : 26.5ns
> U18-U29 Data Latency : 25.1ns
> U18-U31 Data Latency : 26.2ns
> U20-U22 Data Latency : 24.5ns
> U20-U24 Data Latency : 26.7ns
> U20-U26 Data Latency : 25.3ns
> U20-U28 Data Latency : 27.4ns
> U20-U30 Data Latency : 26.2ns
> U20-U1 Data Latency : 56.9ns
> U20-U3 Data Latency : 57.6ns
> U20-U5 Data Latency : 58.6ns
> U20-U7 Data Latency : 58.6ns
> U20-U9 Data Latency : 59.3ns
> U20-U11 Data Latency : 59.2ns
> U20-U13 Data Latency : 59.5ns
> U20-U15 Data Latency : 59.3ns
> U20-U17 Data Latency : 25.1ns
> U20-U19 Data Latency : 23.7ns
> U20-U21 Data Latency : 12.9ns
> U20-U23 Data Latency : 24.5ns
> U20-U25 Data Latency : 26.9ns
> U20-U27 Data Latency : 25.3ns
> U20-U29 Data Latency : 27.6ns
> U20-U31 Data Latency : 26.0ns
> U22-U24 Data Latency : 25.1ns
> U22-U26 Data Latency : 27.1ns
> U22-U28 Data Latency : 25.6ns
> U22-U30 Data Latency : 26.6ns
> U22-U1 Data Latency : 58.4ns
> U22-U3 Data Latency : 58.9ns
> U22-U5 Data Latency : 58.8ns
> U22-U7 Data Latency : 59.6ns
> U22-U9 Data Latency : 59.2ns
> U22-U11 Data Latency : 59.8ns
> U22-U13 Data Latency : 60.4ns
> U22-U15 Data Latency : 60.5ns
> U22-U17 Data Latency : 23.8ns
> U22-U19 Data Latency : 25.6ns
> U22-U21 Data Latency : 24.4ns
> U22-U23 Data Latency : 13.0ns
> U22-U25 Data Latency : 25.1ns
> U22-U27 Data Latency : 27.1ns
> U22-U29 Data Latency : 25.6ns
> U22-U31 Data Latency : 26.7ns
> U24-U26 Data Latency : 25.6ns
> U24-U28 Data Latency : 28.1ns
> U24-U30 Data Latency : 26.7ns
> U24-U1 Data Latency : 58.2ns
> U24-U3 Data Latency : 58.4ns
> U24-U5 Data Latency : 59.4ns
> U24-U7 Data Latency : 60.0ns
> U24-U9 Data Latency : 60.2ns
> U24-U11 Data Latency : 59.8ns
> U24-U13 Data Latency : 60.9ns
> U24-U15 Data Latency : 60.0ns
> U24-U17 Data Latency : 25.6ns
> U24-U19 Data Latency : 24.3ns
> U24-U21 Data Latency : 26.7ns
> U24-U23 Data Latency : 24.9ns
> U24-U25 Data Latency : 12.9ns
> U24-U27 Data Latency : 25.6ns
> U24-U29 Data Latency : 28.2ns
> U24-U31 Data Latency : 26.6ns
> U26-U28 Data Latency : 26.2ns
> U26-U30 Data Latency : 30.1ns
> U26-U1 Data Latency : 59.5ns
> U26-U3 Data Latency : 59.5ns
> U26-U5 Data Latency : 59.8ns
> U26-U7 Data Latency : 60.0ns
> U26-U9 Data Latency : 60.5ns
> U26-U11 Data Latency : 61.2ns
> U26-U13 Data Latency : 60.5ns
> U26-U15 Data Latency : 60.8ns
> U26-U17 Data Latency : 24.5ns
> U26-U19 Data Latency : 26.3ns
> U26-U21 Data Latency : 25.1ns
> U26-U23 Data Latency : 27.0ns
> U26-U25 Data Latency : 25.7ns
> U26-U27 Data Latency : 13.0ns
> U26-U29 Data Latency : 26.2ns
> U26-U31 Data Latency : 27.4ns
> U28-U30 Data Latency : 30.5ns
> U28-U1 Data Latency : 59.4ns
> U28-U3 Data Latency : 59.3ns
> U28-U5 Data Latency : 60.2ns
> U28-U7 Data Latency : 60.3ns
> U28-U9 Data Latency : 60.9ns
> U28-U11 Data Latency : 60.8ns
> U28-U13 Data Latency : 60.7ns
> U28-U15 Data Latency : 61.4ns
> U28-U17 Data Latency : 24.5ns
> U28-U19 Data Latency : 24.7ns
> U28-U21 Data Latency : 25.0ns
> U28-U23 Data Latency : 25.4ns
> U28-U25 Data Latency : 25.8ns
> U28-U27 Data Latency : 25.8ns
> U28-U29 Data Latency : 13.1ns
> U28-U31 Data Latency : 26.5ns
> U30-U1 Data Latency : 59.5ns
> U30-U3 Data Latency : 59.6ns
> U30-U5 Data Latency : 60.1ns
> U30-U7 Data Latency : 61.4ns
> U30-U9 Data Latency : 61.5ns
> U30-U11 Data Latency : 60.8ns
> U30-U13 Data Latency : 61.5ns
> U30-U15 Data Latency : 61.5ns
> U30-U17 Data Latency : 24.8ns
> U30-U19 Data Latency : 24.9ns
> U30-U21 Data Latency : 25.2ns
> U30-U23 Data Latency : 25.7ns
> U30-U25 Data Latency : 25.7ns
> U30-U27 Data Latency : 26.3ns
> U30-U29 Data Latency : 26.5ns
> U30-U31 Data Latency : 13.2ns
> U1-U3 Data Latency : 22.5ns
> U1-U5 Data Latency : 23.1ns
> U1-U7 Data Latency : 23.7ns
> U1-U9 Data Latency : 23.6ns
> U1-U11 Data Latency : 24.2ns
> U1-U13 Data Latency : 24.5ns
> U1-U15 Data Latency : 24.6ns
> U1-U17 Data Latency : 57.7ns
> U1-U19 Data Latency : 57.2ns
> U1-U21 Data Latency : 58.2ns
> U1-U23 Data Latency : 58.3ns
> U1-U25 Data Latency : 58.9ns
> U1-U27 Data Latency : 59.3ns
> U1-U29 Data Latency : 59.9ns
> U1-U31 Data Latency : 60.9ns
> U3-U5 Data Latency : 24.5ns
> U3-U7 Data Latency : 25.5ns
> U3-U9 Data Latency : 24.0ns
> U3-U11 Data Latency : 26.1ns
> U3-U13 Data Latency : 24.6ns
> U3-U15 Data Latency : 25.7ns
> U3-U17 Data Latency : 60.5ns
> U3-U19 Data Latency : 60.2ns
> U3-U21 Data Latency : 59.6ns
> U3-U23 Data Latency : 60.4ns
> U3-U25 Data Latency : 60.4ns
> U3-U27 Data Latency : 59.7ns
> U3-U29 Data Latency : 60.3ns
> U3-U31 Data Latency : 60.4ns
> U5-U7 Data Latency : 24.0ns
> U5-U9 Data Latency : 26.4ns
> U5-U11 Data Latency : 24.7ns
> U5-U13 Data Latency : 26.8ns
> U5-U15 Data Latency : 25.5ns
> U5-U17 Data Latency : 60.7ns
> U5-U19 Data Latency : 60.7ns
> U5-U21 Data Latency : 60.9ns
> U5-U23 Data Latency : 60.8ns
> U5-U25 Data Latency : 60.8ns
> U5-U27 Data Latency : 60.7ns
> U5-U29 Data Latency : 60.4ns
> U5-U31 Data Latency : 61.4ns
> U7-U9 Data Latency : 24.3ns
> U7-U11 Data Latency : 26.4ns
> U7-U13 Data Latency : 25.9ns
> U7-U15 Data Latency : 26.4ns
> U7-U17 Data Latency : 60.3ns
> U7-U19 Data Latency : 60.7ns
> U7-U21 Data Latency : 61.3ns
> U7-U23 Data Latency : 61.0ns
> U7-U25 Data Latency : 60.9ns
> U7-U27 Data Latency : 60.9ns
> U7-U29 Data Latency : 60.6ns
> U7-U31 Data Latency : 60.9ns
> U9-U11 Data Latency : 26.1ns
> U9-U13 Data Latency : 27.1ns
> U9-U15 Data Latency : 26.9ns
> U9-U17 Data Latency : 60.0ns
> U9-U19 Data Latency : 60.1ns
> U9-U21 Data Latency : 60.9ns
> U9-U23 Data Latency : 60.5ns
> U9-U25 Data Latency : 61.2ns
> U9-U27 Data Latency : 60.6ns
> U9-U29 Data Latency : 60.8ns
> U9-U31 Data Latency : 60.8ns
> U11-U13 Data Latency : 27.5ns
> U11-U15 Data Latency : 27.4ns
> U11-U17 Data Latency : 60.7ns
> U11-U19 Data Latency : 60.9ns
> U11-U21 Data Latency : 59.6ns
> U11-U23 Data Latency : 60.8ns
> U11-U25 Data Latency : 60.4ns
> U11-U27 Data Latency : 60.5ns
> U11-U29 Data Latency : 60.7ns
> U11-U31 Data Latency : 60.1ns
> U13-U15 Data Latency : 28.3ns
> U13-U17 Data Latency : 59.8ns
> U13-U19 Data Latency : 59.2ns
> U13-U21 Data Latency : 60.5ns
> U13-U23 Data Latency : 60.3ns
> U13-U25 Data Latency : 59.9ns
> U13-U27 Data Latency : 60.5ns
> U13-U29 Data Latency : 61.2ns
> U13-U31 Data Latency : 61.4ns
> U15-U17 Data Latency : 60.4ns
> U15-U19 Data Latency : 60.9ns
> U15-U21 Data Latency : 60.2ns
> U15-U23 Data Latency : 60.6ns
> U15-U25 Data Latency : 60.6ns
> U15-U27 Data Latency : 60.9ns
> U15-U29 Data Latency : 60.7ns
> U15-U31 Data Latency : 60.9ns
> U17-U19 Data Latency : 25.3ns
> U17-U21 Data Latency : 25.7ns
> U17-U23 Data Latency : 24.6ns
> U17-U25 Data Latency : 25.5ns
> U17-U27 Data Latency : 24.6ns
> U17-U29 Data Latency : 26.2ns
> U17-U31 Data Latency : 24.9ns
> U19-U21 Data Latency : 25.0ns
> U19-U23 Data Latency : 26.0ns
> U19-U25 Data Latency : 24.6ns
> U19-U27 Data Latency : 26.5ns
> U19-U29 Data Latency : 25.0ns
> U19-U31 Data Latency : 26.1ns
> U21-U23 Data Latency : 24.6ns
> U21-U25 Data Latency : 27.0ns
> U21-U27 Data Latency : 25.1ns
> U21-U29 Data Latency : 27.4ns
> U21-U31 Data Latency : 26.0ns
> U23-U25 Data Latency : 24.9ns
> U23-U27 Data Latency : 26.8ns
> U23-U29 Data Latency : 26.3ns
> U23-U31 Data Latency : 26.9ns
> U25-U27 Data Latency : 26.5ns
> U25-U29 Data Latency : 27.6ns
> U25-U31 Data Latency : 27.5ns
> U27-U29 Data Latency : 28.1ns
> U27-U31 Data Latency : 27.8ns
> U29-U31 Data Latency : 28.8ns
> 1x 64bytes Blocks Bandwidth : 19GB/s
> 4x 64bytes Blocks Bandwidth : 26.7GB/s
> 4x 256bytes Blocks Bandwidth : 100.75GB/s
> 4x 1kB Blocks Bandwidth : 314.12GB/s
> 4x 4kB Blocks Bandwidth : 459.66GB/s
> 16x 4kB Blocks Bandwidth : 625.22GB/s
> 4x 64kB Blocks Bandwidth : 838GB/s
> 16x 64kB Blocks Bandwidth : 342.14GB/s
> 8x 256kB Blocks Bandwidth : 388.27GB/s
> 4x 1MB Blocks Bandwidth : 394.55GB/s
> 8x 1MB Blocks Bandwidth : 39.37GB/s
> 8x 4MB Blocks Bandwidth : 19.71GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (16C 32T 3.6GHz/5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : MUAF210009
> Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
> Platform Compliance : x64
> Buffer Memory Accesses : No
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> Speed : 3.6GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
> Cores per Processor : 16 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : MUAF210009
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Tip 223 : CPU speed, under load, lower than rated speed. Check power management settings.
> Notice 242 : Dynamic OverClocking/Turbo engaged. Performance will not be consistent!
> Tip 2 : Double-click tip or press Enter while a tip is selected for more information about the tip.
> 
> 
> 
> 
> 
> Spoiler: recorded multi-core only (MC) data
> 
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Inter-Core Bandwidth : 78GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> Inter-Core Latency : 44.3ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Inter-Core Bandwidth : 4.87GB/s
> No. Threads : 16
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Speed
> Inter-Core Bandwidth : 22.17MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Inter-Core Latency : 0.12ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U6 U2-U8 U4-U10 U12-U14 U16-U26 U18-U24 U20-U22 U28-U30
> U0-U2 Data Latency : 24.7ns
> U0-U4 Data Latency : 25.1ns
> U0-U6 Data Latency : 24.2ns
> U0-U8 Data Latency : 24.4ns
> U0-U10 Data Latency : 24.2ns
> U0-U12 Data Latency : 25.7ns
> U0-U14 Data Latency : 24.4ns
> U0-U16 Data Latency : 60.5ns
> U0-U18 Data Latency : 60.6ns
> U0-U20 Data Latency : 60.9ns
> U0-U22 Data Latency : 59.6ns
> U0-U24 Data Latency : 60.2ns
> U0-U26 Data Latency : 61.0ns
> U0-U28 Data Latency : 60.2ns
> U0-U30 Data Latency : 60.5ns
> U2-U4 Data Latency : 24.8ns
> U2-U6 Data Latency : 25.6ns
> U2-U8 Data Latency : 23.9ns
> U2-U10 Data Latency : 26.1ns
> U2-U12 Data Latency : 24.5ns
> U2-U14 Data Latency : 25.6ns
> U2-U16 Data Latency : 60.6ns
> U2-U18 Data Latency : 60.7ns
> U2-U20 Data Latency : 60.8ns
> U2-U22 Data Latency : 59.9ns
> U2-U24 Data Latency : 60.7ns
> U2-U26 Data Latency : 59.8ns
> U2-U28 Data Latency : 60.2ns
> U2-U30 Data Latency : 60.1ns
> U4-U6 Data Latency : 24.3ns
> U4-U8 Data Latency : 26.6ns
> U4-U10 Data Latency : 24.8ns
> U4-U12 Data Latency : 27.0ns
> U4-U14 Data Latency : 25.7ns
> U4-U16 Data Latency : 61.5ns
> U4-U18 Data Latency : 60.9ns
> U4-U20 Data Latency : 60.8ns
> U4-U22 Data Latency : 61.3ns
> U4-U24 Data Latency : 61.5ns
> U4-U26 Data Latency : 61.5ns
> U4-U28 Data Latency : 61.2ns
> U4-U30 Data Latency : 61.5ns
> U6-U8 Data Latency : 24.3ns
> U6-U10 Data Latency : 26.4ns
> U6-U12 Data Latency : 25.7ns
> U6-U14 Data Latency : 26.4ns
> U6-U16 Data Latency : 60.9ns
> U6-U18 Data Latency : 60.2ns
> U6-U20 Data Latency : 60.9ns
> U6-U22 Data Latency : 60.4ns
> U6-U24 Data Latency : 60.1ns
> U6-U26 Data Latency : 60.6ns
> U6-U28 Data Latency : 60.5ns
> U6-U30 Data Latency : 60.4ns
> U8-U10 Data Latency : 26.1ns
> U8-U12 Data Latency : 27.1ns
> U8-U14 Data Latency : 26.9ns
> U8-U16 Data Latency : 60.2ns
> U8-U18 Data Latency : 59.7ns
> U8-U20 Data Latency : 60.8ns
> U8-U22 Data Latency : 60.1ns
> U8-U24 Data Latency : 60.0ns
> U8-U26 Data Latency : 60.5ns
> U8-U28 Data Latency : 61.5ns
> U8-U30 Data Latency : 60.3ns
> U10-U12 Data Latency : 27.5ns
> U10-U14 Data Latency : 27.4ns
> U10-U16 Data Latency : 60.2ns
> U10-U18 Data Latency : 60.5ns
> U10-U20 Data Latency : 60.5ns
> U10-U22 Data Latency : 60.0ns
> U10-U24 Data Latency : 60.4ns
> U10-U26 Data Latency : 60.6ns
> U10-U28 Data Latency : 60.5ns
> U10-U30 Data Latency : 61.0ns
> U12-U14 Data Latency : 28.3ns
> U12-U16 Data Latency : 60.4ns
> U12-U18 Data Latency : 59.3ns
> U12-U20 Data Latency : 59.8ns
> U12-U22 Data Latency : 59.6ns
> U12-U24 Data Latency : 60.6ns
> U12-U26 Data Latency : 60.3ns
> U12-U28 Data Latency : 61.0ns
> U12-U30 Data Latency : 60.6ns
> U14-U16 Data Latency : 60.1ns
> U14-U18 Data Latency : 60.1ns
> U14-U20 Data Latency : 60.1ns
> U14-U22 Data Latency : 60.0ns
> U14-U24 Data Latency : 60.8ns
> U14-U26 Data Latency : 60.6ns
> U14-U28 Data Latency : 60.8ns
> U14-U30 Data Latency : 61.1ns
> U16-U18 Data Latency : 25.3ns
> U16-U20 Data Latency : 25.5ns
> U16-U22 Data Latency : 24.6ns
> U16-U24 Data Latency : 25.5ns
> U16-U26 Data Latency : 24.5ns
> U16-U28 Data Latency : 26.2ns
> U16-U30 Data Latency : 24.9ns
> U18-U20 Data Latency : 24.9ns
> U18-U22 Data Latency : 26.0ns
> U18-U24 Data Latency : 24.4ns
> U18-U26 Data Latency : 26.5ns
> U18-U28 Data Latency : 24.9ns
> U18-U30 Data Latency : 26.1ns
> U20-U22 Data Latency : 24.5ns
> U20-U24 Data Latency : 26.9ns
> U20-U26 Data Latency : 25.0ns
> U20-U28 Data Latency : 27.3ns
> U20-U30 Data Latency : 25.9ns
> U22-U24 Data Latency : 24.7ns
> U22-U26 Data Latency : 26.7ns
> U22-U28 Data Latency : 26.3ns
> U22-U30 Data Latency : 26.8ns
> U24-U26 Data Latency : 26.5ns
> U24-U28 Data Latency : 27.6ns
> U24-U30 Data Latency : 27.3ns
> U26-U28 Data Latency : 28.0ns
> U26-U30 Data Latency : 27.8ns
> U28-U30 Data Latency : 28.8ns
> 1x 64bytes Blocks Bandwidth : 3.2GB/s
> 4x 64bytes Blocks Bandwidth : 5.5GB/s
> 4x 256bytes Blocks Bandwidth : 21.44GB/s
> 4x 1kB Blocks Bandwidth : 95.82GB/s
> 4x 4kB Blocks Bandwidth : 178.67GB/s
> 16x 4kB Blocks Bandwidth : 129GB/s
> 4x 64kB Blocks Bandwidth : 150.87GB/s
> 16x 64kB Blocks Bandwidth : 268GB/s
> 8x 256kB Blocks Bandwidth : 419.62GB/s
> 4x 1MB Blocks Bandwidth : 417.85GB/s
> 8x 1MB Blocks Bandwidth : 415.47GB/s
> 8x 4MB Blocks Bandwidth : 20.48GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (16C 32T 3.6GHz/5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : MUAF210009
> Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
> Platform Compliance : x64
> Buffer Memory Accesses : No
> No. Threads : 16
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> Speed : 3.6GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
> Cores per Processor : 16 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : MUAF210009
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Tip 223 : CPU speed, under load, lower than rated speed. Check power management settings.
> Notice 242 : Dynamic OverClocking/Turbo engaged. Performance will not be consistent!
> Tip 2 : Double-click tip or press Enter while a tip is selected for more information about the tip.





domdtxdissar said:


> Here is my 24/7 auto settings for 5950x + 4x8 gigabyte @ 3800:1900
> Bloated windows install with nothing disabled


Interesting Sandra results, thanks for sharing. Your unusual timings seem to help with sub 60ns intercore latecies.


----------



## Nd4spdvn

@domdtxdissar btw how did you get the sandra results in text format?


----------



## domdtxdissar

Nd4spdvn said:


> @domdtxdissar btw how did you get the sandra results in text format?


----------



## Dasa

So far from all the settings I have tried it seems like the only thing that has improved stability with lower tRCD is to lower VDIMM but that decreases stability with other timings being tight.
I have tried every step in v from 1.43v to 1.55v and it just seems to scale without holes on this MB.
When VDIMM goes to high with a low tRCD it seems to throw almost every error there is which sent me chasing my tale in all directions.

So the best setting for this kit\MB may be a low V strong driver setting.
I had hoped that I could find a weaker driver\Rtt or timing setting that would improve stability with higher V but no such luck as yet. 0\0\5 7\0\6 7\3\1 6\3\3 and a few other small variations on those don't seem to have had much effect.
But maybe I didnt hit that sweet spot with the correct Rtt paired with the correct driver strength at the same time.



Sleepycat said:


> Also something to consider is that signalling gets worse when you get to DIMM slot A1 and B1 (furthest away from SOC). So you can put your best RAM sticks into A1 and B1, and the worst ones into A2 and B2. This should even them out and hopefully reduce signalling issues.


If one of the three sticks is worse than the rest is there any difference between A1 and B1? or just A1 and A2.


----------



## GribblyStick

@Veii
Ok so I want to make this a two parter.


Spoiler: Part 1 - results



here's the best I can manage after re-arranging the dimms ( didn't seem to change much).
14/14/14 still boots and still throws a bunch of error 6s.
I lowered 
tRRDS/L to 7/9
tWTRS/L to 5/14
tRFC 294/218/134
tWR 14
tRTP 7
tFAW 28
upping voltages from CCD/VDDP 0,850/0,850 to 0,940/0,900 helped a little bit, but not enough.
Upping voltages further from there, be it SOC/VDIMM or others seemed to induce more rather than less errors.

I was able to run 14/14/14 on two of the sticks when I was testing pairs of sticks, but oddly enough I saw no difference in performance.
After re-arranging I am able to at least boot 1T GDM OFF on 16/16/16/, but it bluescreens and enters diagnostics.
Lowering timings as above stops bluescreening but I haven't been able to pass training then.

So I tried improving timings 16/16/16 instead, ending with the following results:


Spoiler: 16/16/16















I had a spike at 59500/58400 but I haven't been able to reproduce that.
Also tried running at 1T GDM ON, which worked, but oddly had slightly worse results.
Not sure running 0,900/0,950 is really better than 0,850/0,850 though.






Spoiler: Part 2 - ratios



I hear a lot of people(not just here) talking about "high" or "low" values, "right" ratios.
Nobody seems to give actual values, and then there seems to be different usable but mutually exclusive sets you can use?

So could somebody fill me in on what is supposed to work?
Here's what I've understood to be the basics:


Spoiler: normal ratios



even values are preferred overall
lower is better: tCL/tRCD*/tRP/tRRDS/tWTRS/tRDRDSCL/_SCL/tRDRD_/tWRWR*
tCL/tRCP*/tRP should all be equal
*SCL should equal
tRAS=tCL+tRP
tRC=tRAS+TCL
tWR=tRAS-tRCDRD or tRRDS+tWRTS, whichever is lower.
tRTP=tWR/2
tFAW=4x tRRDS
tWTRL = 2x tRRDL
tRFC=5/6/7x tRC
tCWL=tCL
tRDWR=(tRCD/2)+2
tWRRD=some factor of *SCL

tCKE I have no idea
I have seen people use 1, or whatever was the lowest value. Veii suggest this depending on frequency





Spoiler: alternatives



Burst length being 8 for DDR4, tBL being half of burst length
tRFC= tRTP x tRC
tRC=tRAS+tCL
tRAS=TCL+tRCDRD+2
tRAS=tRCDRD+tBL+tWR
tRAS=tRCDRD+tBL
tRAS=tCL+tRTP
tRAS=tCL+tRTP+(tRP/2)+2
tWR=tCL-1+(burst length /2)+tWTR
seen a bunch of people getting good results by lowering tCL/tRCD/tRP as loq as they go
tRRDL > tRRDS with nothing non how far the gap should be
tWTRL=TRRDL+2
tCWL up to 3 lower than tCL
tFAW=tRRDS



For all of these, while I don't know if some of these require certain ratios beyond the formulas, at least I can run AIDA and see if I get better results.

for RTT/CADBUS/CADBUS setup times/voltages I have no idea.
I can throw all sorts of settings at my dimms and I see no difference in stability.
Some configurations may provide slightly better results, but not always.
There is no way that I know of to confirm you are generating a clean signal?
Only difference so far is that it may help in passing training/booting.

Beyond that, which frequency you can run is a total lottery?
Between your board/IMC/Specific DIMMs/BIOS/chipset/procODT I have seen people run all sorts of setups.
Personally I still can't run 4000 and I'm not even 100% sure my 3800 is running correctly.
I haven't really been able to copy any setups I thought were decent. Even if I threw way more voltage at them.
Veii is doing 4200 while other are failing to run 3800 on way worse timings.
I have no idea what is required to run 1T with GDM OFF, or what is specific to 2 sticks/single/dual rank. I just get the creeping suspicion that B550 handles that better than X570.
X570 in general seems to do worse.

As for values, I still have no idea what is safe.
Heat isn't the only concern, high enough current/voltage could fry the memory/cpu just the same.
It's been a while but I saw a vid of Buildzoid showing just that, and there it snapped in the neighborhood of 1,5V
What I gather from Veiis tests though is that whatever values used to be considered safe, don't seem to be valid now.
But also that with 1,5ish you could still end up frying depending on your resistances and I have no idea what to look out for here.
I have run 3800 as low as
CCD 0,850
CLDO VDDP 0,840
CPU VDDP 0,840
IOD I don't remember the lowest.
Might have been able to run lower, but I didn't try.

From Veii we know you can go as high as 
1,3 VSOC
proc ODT no idea, at least one person here went down to 28, and I've seen settings in the 50ies.
VDIMM as high as 1,6 something
IOD 1100
CCD/CLDO VDDP up to 1,05

the ryzen calculator, app and google doc are outdates as far as I know?
I have an A1 board, which isn't even an option on the doc.
Except for tRFC and the error messages


----------



## Karagra

Well my Crucial Ballistix MAX 4400 MHz CL19 BLM2K8G44C19U4B just came in.. time to see what this kit can do


----------



## tefla

Wanted to give an update after posting a little over two weeks ago. I've been slowly chipping away trying to get tighter timings.

Redid all my timings and managed to shave off another 0.4ns. Here's my latest stability tested results @ 54.2ns. No WHEA 19s in event viewer. VDDG CCD should be lower but I'm encountering a bios bug where it's forced to be equal to IOD--will need to figure out. DRAM @ 1.55v (max before thermal issues in my setup). @Veii had suggested trying to get 1-4-4-1-6-6 for tRDRD and tWRWR but I could not get this to even boot no matter what I tried, not sure I'm doing wrong. Going straight 14 for primaries doesn't seem possible on this voltage--I get voltage related errors in TM5.

I would love to get under 54.0ns stable for fun, but based on how long it took me to get down to 54.2--it may not be possible. Perhaps in safe mode with fewer background processes I could do it.😅 I attempted 3933 and 4000 and it can pass stability test, but gets thousands of bus/interconnect errors in background--seems like a no-go on this bios + AGESA unfortunately. Thanks again to all the discussion here. I started a total noob and I've learned a lot from reading here. Even my girlfriend is familiar with how my bios looks now ahahah.


----------



## Veii

GribblyStick said:


> I hear a lot of people(not just here) talking about "high" or "low" values, "right" ratios.
> Nobody seems to give actual values, and then there seems to be different usable but mutually exclusive sets you can use?


Simply because neither is perfectly correct
There are hard limits of which you can check ones on the ryzen google calculator
But minimum limits do not mean stability limits
Many are made for stability - and yet it depends on the datasize where memory does indeed internally autocorrect in realtime and adjust up to dataset size

Although pessimistic and questionable ~ you don't always want to lower results to the absolute minimum, 
As you can not be sure this absolute minimum or this "range" will be followed through all dataset sizes
Also not to forget, timings on intel and timings on AMD are slightly different. Different page length & size, different BURST length
Different tSTAG up to generation and platform
It keeps on being different ~ also AMD has trick in the sleeve, where a write can follow a write without a precharge and without any delay at all
It was half-way undocumented and is against JEDEC rules ~ soo following only JEDEC rules at first, is the wrong path to take

Early on tFAW had cover as absolute minimum 4* the tRRD_S range, while being able to ignore a tRRD_L range
Vermeer breaks this again, and allows it to go to 1x tFAW - but only at very specific usecases. Including running tRAS+1 as tRC
(which should not be done under normal conditions (it's an exploit))

ttBURST as 2 is also an exploit, 4 or 8 should be used for tRAS (tRCD*2 + BURST), unless we skip the burst length and only run tRAS as tRCD*2 (no tCL ~ but old rulesets wherre tRCD+tCL)









tRFC2 & 4 seem to change slightly for Dual Rank dimms on higher capacity and the mini tool needs an update
But i want to research it myself, without copying done research. Would be disrespectful against the shared knowledge and private access to the Ryzen Community Calculator (copying their work)



GribblyStick said:


> tRC=tRAS+TCL


This one is wrong, it's tRAS+tRP
Or as also an exploit it's tRCD_WR + tCWL + BURST + WR
(But on this the result is different and needs adjustment elsewhere ~ it's an exploit, not a ruleset to follow for "baselines")


GribblyStick said:


> tFAW=tRRDS


This one should only be used for 1* tFAW exploit, it's not a ruleset
1* tFAW needs masking in SCL, higher tRRD & tWTR, and couple of other little tweaks, to function
tFAW should match equally or be double of SCL (minimum range is 6+ for tFAW)
* it can be lower than tRRD_S ~ again, exploit not a ruleset


GribblyStick said:


> tRDWR=(tRCD/2)+2


+2 only for dual rank or 4 dimms
Micron Rev.E run it -2 , because of the PCB and their own manufacturing secrets=exploits


GribblyStick said:


> tRFC= tRTP x tRC


Real ruleset has tSTAG factored in and page size - but page size varies
This is alternative research & personal research for a "baseline" / neither following JEDEC nor being the ultimative lowest option. It's there for stability and accuracy. We don't want autocorrection


GribblyStick said:


> tWR=tRAS-tRCDRD or tRRDS+tWRTS, whichever is lower.


Both are correct, but both are optimized for different datasets ~ it moving inside tRFC range, seems to be the most universal one ~ but i am biast here 


GribblyStick said:


> tWRRD=some factor of *SCL


Should be used for 4 dimms, or for dual rank
Doesn't have to be used if PCB allows it (1).
* But if tRDWR is lower, this one is what you have to increase to add a bit of delay. Low tRDWR does a lot, this one is also an "exploit"

Pretty much barely anyone is correct, as memory can be optimized to different dataset sizes (SiSandra MCE) and for different usecases
There are no hard-rules & JEDEC is not the book of wisdom to blindly follow 








Ryzen Google Calculator!


Ryzen Google Calculator! https://docs.google.com/spreadsheets/d/1cJmhO62WHPLNKGBtsJV3BjdL-dcfJJeyhdSAoJmuzJE_ Created from "Google Sheets" For mobile users, you need the Google Sheets app. Made for me to learn about timings I'd appreciate it if anyone tell me any advice or improvements...




www.overclock.net




This where couple of suggestions with "patterns" as you've asked
But even that was 7 months old. Exploits improved, and balancing improved
I don't see many people push alternative research, but only push people down with bad words who want to bring research further
(here probably i'm biased again ~ just know how these JEDEC following people behave against me)
Glad that This Community Calculator starts to be a thing and people who usually dislike each other, work on something
=========================================


tefla said:


> @Veii had suggested trying to get 1-4-4-1-6-6 for tRDRD and tWRWR but I could not get this to even boot no matter what I tried.


This is because your tRDWR is already borderline low - usually it should be 9. (7.5 + 2 = 9.5, -1 because tWRRD = is 8.5, not 8 ~ you'd have to waste latency somewhere else to cover it)
Although i think a pure 15-15 set might be a better option , but you have to test
It's strange seeing what typically is an "MSI Board" thing - on ASUS boards , that 1-5-4-1-7-6 pattern
Couldn't understand why it would be better, but it might be a thing if it's the reason for the low tRDWR (tRDWR gives the biggest boost, out of all timings)
But i think your main issue for a flat 14-14 set, is the low tRRD and tWTR
You have dual rank dimms, the PCB is two sided - the traces also longer in reality
You can't expect Single rank tRRD & tWTR to run on it ~ running them thaat low. Voltage rarely fixes that, but increasing them does lower required voltage 
Better to waste latency there, instead wasting it with slower primaries. ~~ i still can't get mine bellow 7-9 & 5-14 ~~ even when 4-5 & 4-10 worked on higher primaries
They don't cut that much timing effectiveness away - the main lower primaries, are more effective as for higher speeds and lower latency 


Dasa said:


> The tRFC calc here doesn't seem to be working for me at the moment


Grab the one from








Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com




Put tRFC2 option to B-2 if you have 16gb dimms , else the mini one ~ should work for 8gb dimms (amount doesn't matter)


domdtxdissar said:


> Bloated windows install with nothing disabled


Run that in powershell


Code:


iex ((New-Object System.Net.WebClient).DownloadString('https://git.io/JJ8R4'))

It's by Sycnex/Windows10Debloater , him 
But this one is newer








GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11


:zap: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11 - GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-t...




github.com




i will need to see what Sophia improved
Code above launches a gui and doesn't do any changes
but make a restore point before messing with windows update and removing W-Apps like Candy Crush and Little Witch Saga ~ bubble game


----------



## KedarWolf

I had a really weird issue. Latency went up to 70ns+, I tried everything to fix it.

Also, task manager was showing things like Chrome with Very High Power Usage, other processes as well.

Eventually reinstalled Windows, clean install. Now at 54.5ns.


----------



## Ramad

It's sad to see how much wrong information that has and is being spread regarding RAM in this and other threads, when all you need to do is look up in the data sheet of your DDR4 RAM. All the information you are looking up is there on these data sheets. OCN members should be on top of it.

*Bank groups: 

Samsung B-die:*










*Micron Rev.E:*










*SKhynix CJR:*












*Maximum DDR4 RAM voltage:

Samsung B-die:










Micron Rev.E:











SKhynix CJR:








*

Note: Since you can never know what voltage is passing through Vss (Ground pin), you should *never* set your VDDR higher than 1.5V. Unless you don't care about damaging your RAM and only care about score, then...good luck.

The last one that I want to point out is, there is no Command Rate of 2.5, never have been and will never be.

Command Rate can be configured as 1T, 2T or Gear Down Mode. 

The Command Rate will change between 1T and 2T in Gear Down Mode as follows:

*-* 1T during power up/reset/initialization
*-* 2T during normal operation (read/write)
*-* 1T during self-refresh

Now you know the reason when your BIOS displays 1T even if you are running GDM at 2T, and this also the reason that you can boot using 1T with GDM enabled and fails to to boot or runs very unstable if you set Command Rate to 1T and disable GDM. Gear Down Mode is a different Command Rate method.


















I hope this will encourage you to take a data sheet and look for any information you want instead of relaying on others to tell you what you could learn easily.

Last note: tRFC has nothing to do with tRC, they are not related in any shape or form so I don't know why some of you are making tRFC a product of tRC, like tRFC = X*tRC. These two timing has nothing to do with each other.


----------



## ManniX-ITA

Ramad said:


> It's sad to see how much wrong information that has and is being spread regarding RAM in this and other threads, when all you need to do is look up in the data sheet of your DDR4 RAM. All the information you are looking up is there on these data sheets. OCN members should be on top of it.


I think you missed the fundamental difference between a memory IC and a memory module.
There's almost anything easy to learn in a DDR4 datasheet and very few bits that are helpful in configuring a kit.


----------



## GribblyStick

anybody that can translate the above to english?


----------



## Ramad

ManniX-ITA said:


> I think you missed the fundamental difference between a memory IC and a memory module.
> There's almost anything easy to learn in a DDR4 datasheet and very few bits that are helpful in configuring a kit.


I think you missed the point of my post. You may find a data sheet useful if you read one. 
Beside that, I don't think anything will change here at OCN, it did not take long for the first negative post. The same old OCN.


----------



## _frame_

AGESA V2 PI 1.2.0.1 *Patch A *is out... SMU 56.50.0
Asus has beta bios
And it is terrible. I had fully stable IF 2000 and now it is not


----------



## Sleepycat

_frame_ said:


> AGESA V2 PI 1.2.0.1 *Patch A *is out... SMU 56.50.0
> Asus has beta bios
> And it is terrible. I had fully stable IF 2000 and now it is not


After some testing, it doesn't work with CTR2.0.

It does improve the USB situation with the Reverb G2 though.


----------



## zGunBLADEz

_frame_ said:


> AGESA V2 PI 1.2.0.1 *Patch A *is out... SMU 56.50.0
> Asus has beta bios
> And it is terrible. I had fully stable IF 2000 and now it is not


I rolled back bcuz it messed up my power table and core usage.. 
My main ccx fastest cores are 1/5 my power plan have every core parked on idle except 2 cores which were 1/5 on bios 1803 on b550-i now with the new bios the 2 active cores on idle are 0/1 instead and always use core 0 as the main 1st core instead of 1&5 then 0 is the 3rd fastest core... rolledback to 1803 this affected every reading on low loads as they not using the fastest cores anymore on low loads.

Well truth to be told the real numbers on latency should come from the multiplier used on a all core load instead of the fastest cores anyway that false sense of speed in that regards xD


----------



## ManniX-ITA

Ramad said:


> I think you missed the point of my post. You may find a data sheet useful if you read one.
> Beside that, I don't think anything will change here at OCN, it did not take long for the first negative post. The same old OCN.


LoL. You basically asked for a negative post and you got it of course.
It's not the same old OCN, maybe this time it's about you.

You've posted; Hey folks, here's the the hot water. Wake up, read the datasheets instead of blabbing without knowledge.
There's people here testing for weeks a couple of timings and you are telling them that they are dumb and you are smart.
Seriously?



Ramad said:


> It's sad to see how much wrong information that has and is being spread regarding RAM in this and other threads, when all you need to do is look up in the data sheet of your DDR4 RAM


If you want to really learn something, don't be arrogant.
I've read the last 150 pages, each message, before posting here.

There are a lot of DDR4 guides online, look for them and try to understand.
You'll notice a lot of the material is coming form the DDR4 datasheet.
They are much easier to read and are actually explaining how it works.

Still after all this you'll have learnt just the basics.
Without experience, yours and form others, it's like knowing something about how an engine works but actually not being able to drive.

Almost all the datasheets are made from the same template; you don't really need to read all of them.
Except maybe the base tRFC timing, there's almost any valuable info that can help you about the timings.

How the memory kit works doesn't purely depend on the single IC; the PCB and the layout matters.
You don't watch a bird flying and suddenly understand how migrations works.

The info on the datasheets about timings are mostly related to JEDEC specs.
Most kits, even those sold at JEDEC speeds, are "overclocking" the ICs and the timings are better that those in the datasheets.
The datasheet is telling you with which settings the IC is guaranteed to work in harsh conditions at 1.2V at standard speeds.
You are not going to find really much anything that can helpful for running a kit based on that IC at 1.35V and 3200 MHz or higher.

That's the info you can find here.



Ramad said:


> Note: Since you can never know what voltage is passing through Vss (Ground pin), you should *never* set your VDDR higher than 1.5V. Unless you don't care about damaging your RAM and only care about score, then...good luck.


The rating is very conservative, of course.
And there's a lot more about the termination that can make the voltage dangerous for the module.
With proper settings a B-die kit can run perfectly safe at 1.55V, many hi-end kits are sold with the XMP profile at that voltage.
If you make such bold and absolute statements without reading about first, you'll obviously get criticized...



Ramad said:


> The last one that I want to point out is, there is no Command Rate of 2.5, never have been and will never be.


GDM is referred often as 1.5T because it's a mix of 1T and 2T.
Here we often call it 2.5T, I think @Veii introduced this naming convention, for a very good reason.
GDM is forcing some timings to be even and is auto-correcting a lot of timings and termination parameters.
The result is that in almost all cases a fine-tuned 2T profile can beat in latency a fine-tuned GDM profile.
Hence the 2.5T naming.


----------



## GribblyStick

I can't help but feel that my post is being considered a negative one.
I'm not sure why though? I wasn't attacking, I literally have no idea what to do with the information presented.
I'm here to learn how to push my RAM, but at the same time I have no intention of understanding the physics behind it.
I'm here to benefit from people that understand way more than I do and I'm not afraid to put time into to this.

At this point I have binge-watched several seasons of stuff waiting for benchmarking runs and changing configs.
That doesn't mean I want to be reading scientific papers and literature, I am not interested in OC as a hobby.
I simply want to get more out of my RAM and XMP is nice and all but clearly there is much more to be had.

I 've looked at what thaiphoon spits out but it made no sense to me.
The settings I can identify are waaayyy worse than what I am currently running. In my case RFC is listed as 700 when I am running 248.
So to me all this means is that the spec sheets are for settings that are simply not being run in the wild.
My sheet for an XMP profile of 2000(x2) only lists up to 1067 , so I figured it would be useless. Nobody is going to be running their sticks at 1067 IF.
So how are those sheets supposed to help at double the speeds? Never mind people who have successfully pushed far past what their kits were rated at.
So I have always considered those specs pretty pointless aside from telling you what PCB you have ( which I'm also not entirely sure what to do with)


----------



## ManniX-ITA

@GribblyStick 

The PCB info it's useful when you ask for advice, someone with enough knowledge like Veii can make good use of it.
It does matter about the right voltage and termination settings for a given frequency.

The Taiphoon info is very unreliable, you have to take out the DIMM and look yourself comparing to the reference image to find out which one is it.



Spoiler: PCB layout reference image















If you have a common kit or any B-die it's a good idea to start with a tested timing.
Knowing the PCB layout of your kit and looking around you can also find a similar one in the spreadsheet, if it's not present.









Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com


----------



## T[]RK

Ramad said:


> All the information you are looking up is there on these data sheets


Hm... i got Samsung B-die Single Rank (all chips on one side), 8Gb Modules (4 chips on left and another 4 chips on right). Total chips is 8 and that mean it's 8x 1Gb chips. According to table there is Page size - 1Kb. Is it mean i can set in Bios tPAGE? I always have it on Auto.


----------



## Iarwa1N

@Veii Can you please take a look at my situation? I was fully stable (TM5 25 cycles) with the timings below when my PBO was +200. After increasing PBO to +350 I started getting error #5 on TM5 on the first or second cycle. I tried everything, increasing vsoc, decreasing vsoc, increased/decrease iod/ccd or vddp voltages or tried other RTTs, and even on XMP I always get the same error. I know that my cpu is fully stable at +350, I tested it using OCCT Large Extreme, both cycling single cores for hours and all cores for hours without any error. My rams are Micron B die and I get 54.5 ns on Aida with these timings. I can also get your suggestions about making the timings tighter if you have any. Thanks.


----------



## Nighthog

Iarwa1N said:


> @Veii Can you please take a look at my situation? I was fully stable (TM5 25 cycles) with the timings below when my PBO was +200. After increasing PBO to +350 I started getting error #5 on TM5 on the first or second cycle. I tried everything, increasing vsoc, decreasing vsoc, increased/decrease iod/ccd or vddp voltages or tried other RTTs, and even on XMP I always get the same error. I know that my cpu is fully stable at +350, I tested it using OCCT Large Extreme, both cycling single cores for hours and all cores for hours without any error. My rams are Micron B die and I get 54.5 ns on Aida with these timings. I can also get your suggestions about making the timings tighter if you have any. Thanks.
> 
> View attachment 2483373


Might mean you cpu cores might need more voltage. I've seen the PBO cause similar stuff on my system and it usually wanted more voltage to the cores for the memory speed I wanted when it would occur.


----------



## Iarwa1N

Nighthog said:


> Might mean you cpu cores might need more voltage. I've seen the PBO cause similar stuff on my system and it usually wanted more voltage to the cores for the memory speed I wanted when it would occur.


Thanks for the reply, I will try increasing offset voltage to see if it makes any difference.


Sent from my iPhone using Tapatalk


----------



## Ramad

*@ManniX-ITA*

I know the difference between a memory IC and a memory module, but you assumed that I don't know that, why is that?

I assume that you have a RAM based on 8Gb Samsung B-die, every die in your RAM has 16 banks, grouped in 4 bank groups(4 banks pr. group). Since your RAM is single ranked, that means that the RAM stick has 8 dies which translates to 8 x 4 groups = 32 groups and 8 x 16 banks = 128 banks in total.
Is this is the answer you were looking for?

There is no 1.5 or 2.5 command rates. If you want to name them correctly, and you should, since you have been giving RAM and settings advice to members around her, then you should name them correctly as 1T, 2T and GDM.

I'm curios to know your understanding of "Absolute Maximum DC Ratings" mentioned in every data sheet?
If you buy a washing machine and the manufacturer stats in the manual that the "Absolute Maximum AC Rating" is 240V AC, does that mean it's safe for the washer machine to operate at 270V AC or 300V AC?

Anyway, if you just are replying to pick up a fight then I will disappoint you. The data sheets are there, you can use them or not, that is up to you, and I did not post anything of my own making.



T[]RK said:


> Hm... i got Samsung B-die Single Rank (all chips on one side), 8Gb Modules (4 chips on left and another 4 chips on right). Total chips is 8 and that mean it's 8x 1Gb chips. According to table there is Page size - 1Kb. Is it mean i can set in Bios tPAGE? I always have it on Auto.


Correct. You should set that value to 1KB because it's the correct value for your RAM dies.


----------



## _frame_

Sleepycat said:


> After some testing, it doesn't work with CTR2.0.


Also HWinfo doesn't show everything.


zGunBLADEz said:


> I rolled back


Me too


----------



## Veii

Ramad said:


> Command Rate can be configured as 1T, 2T or Gear Down Mode.
> 
> The Command Rate will change between 1T and 2T in Gear Down Mode as follows:
> 
> *-* 1T during power up/reset/initialization
> *-* 2T during normal operation (read/write)
> *-* 1T during self-refresh
> 
> 
> 
> ManniX-ITA said:
> 
> 
> 
> GDM is referred often as 1.5T because it's a mix of 1T and 2T.
> Here we often call it 2.5T, I think @Veii introduced this naming convention, for a very good reason.
> GDM is forcing some timings to be even and is auto-correcting a lot of timings and termination parameters.
> The result is that in almost all cases a fine-tuned 2T profile can beat in latency a fine-tuned GDM profile.
> Hence the 2.5T naming.
Click to expand...

2T During normal operation but yet slower than GDM Off 2T

I was driving the 1.5T train for at least a year, but at some time it made no sense.
What was shared as specs information, be it shared correctly or not ~ never aligned with the test results
Soo i looked at other places, for example the big piece on korean Naver & Chinese Chiphell ~ sites
This changed the "1.5T to 2.5T" terminology
While you are correct that it's variable , and an own thing ~ actually yes i do agree, no xT but just GDM would make more sense to call it

But it certainly is not 1.5T what people called it for illustration purposes - and it also is quite slower than 2T
I just changed information resources away from reddit and ocn for this ~ as what was teached here the last couple of years, doesn't align up with any test results

The same goes for JEDEC,
There are many iterations of it - but we since a long time do not follow it
Neither does AMD nor does Micron (Micron makes their own rules and own working conditions on own PCBs)
Everyone uses that technical JEDEC book as source ~ but trying to unify one specs sheet as the global rule, doesn't work
It's exceptions and rulebreakers ontop of exceptions


ManniX-ITA said:


> Without experience, yours and from others, it's like knowing something about how an engine works but actually not being able to drive.


This quote i think sums it up quite well
Following only technical rules does keep you on the same foundation
Test new things, break rules then you maybe see how things scale. I've also read a lot of them but they are conservative.
It changes nearly every 3-4 months while everyone of these researchers goes back to the main JEDEC foundation and trows away every research that was made ~ in order to set up a new JEDEC spec

Memory is dynamic, and adjusted up to dataset size and working conditions (required conditions)
No specs sheet is wrong, nor is each of them correct
You'd be going crazy to learn the quirks of each revisions, and if you do hold up and actually get up with a new rule
Then you'd be in a state to publish another "revision" of the at least 40+ that are out there for the last 3-4 years
It makes no sense to focus the viewpoint on one resource 



Ramad said:


> Last note: tRFC has nothing to do with tRC, they are not related in any shape or form so I don't know why some of you are making tRFC a product of tRC, like tRFC = X*tRC. These two timing has nothing to do with each other.


I don't know either why you expect it to have a link.
It's my anchor point. Early on it was tCL , but this is far more accurate.
Till i can simulate tSTAG with all the variables needed and so use it for tRFC calculation ~ this anchor point is the closest that makes sense

Sense, i don't think i'll try to explain again & keep it as my own rulesets 
I tried to share how i work, but was on this exact topic already for the 4th time put to  with a grouped intention of making my day bad
The problem was that these groups of people where not discussion capable nor to speak without swearing.
They keep repeating and increasing ~ soo i stop to explain the reason for it
Use it or don't use it 
You can give it a try and check how it works ~ but technical explanations won't work here, as it's just my anchor point for something bigger

I feel everyone who judges on it, hasn't even bothered to try. Their only intention is to destructively break everything that doesn't align with their methods.
Don't ask me how often i have to revert the little docs against groups who intentionally break it


> it's just my anchor point for something bigger


Initially, this module shouldn't even be published yet ~ but i got annoyed that people keep using wrong tRFC2/4 values
Which still do matter without memory exceeding the 75-80c switching point
It's success remains on over 99.8%
(exceptions are people who intentionally mess up tRC or high capacity that expect it magically to consider it's maximum and minimum tRFCns range) ~ it will get there maybe, i'll see if i have the motivation to do so

If it was such a pain and against your mentality,
Where is your motivation to even talk about it ?
Keep using the fixed ns tRFC values. 120/130/140 and so on
I was there, but to me this makes far more trouble, than it's worth it


T[]RK said:


> Hm... i got Samsung B-die Single Rank (all chips on one side), 8Gb Modules (4 chips on left and another 4 chips on right). Total chips is 8 and that mean it's 8x 1Gb chips. According to table there is Page size - 1Kb. Is it mean i can set in Bios tPAGE? I always have it on Auto.


 RCPage = tMAW.MAC 


> "The minimum average time in memory clock cycles within a refresh window, from an activate command to another activate command"


It's an average value, it's something completely different 
I've played with it, and had mixed results 
I think it can be useful , but because on it's nature being "average & variable" like tRFC is "variable and postponable"
It needs time to build up rules for it.
I can't share anything reasonable for it yet
A wrong value behaves like tRFC - random and only crashing after a loong long time.
It still shows up inside the 20 loops of TM5, but it's something very variable that you need to test
Auto says 0 ~ but it's range is 1-999 (usually the same exact range as tRFC)

Don't touch it, unless you want to play around and explore 
Bad values will introduce random issues ~ keep that in mind haha, but feel free to explore it


----------



## T[]RK

Ramad said:


> Correct. You should set that value to 1KB because it's the correct value for your RAM dies.


I did one attempt to do it. I founded tRCPAGE in BIOS, but it not let me enter 1024 or 2048. I can enter 512, but it's not my option. Maybe i must enter "1" or "2" (which is possible), but how then people enter "512"? Strange. Set it in Auto...



Veii said:


> RCPage = tMAW.MAC


Oh-h-h... Another parameter which isn't in calculator (ZenTimings). Nice. =)



Veii said:


> Initially, this module shouldn't even be published yet ~ but i got annoyed that people keep using wrong tRFC2/4 values


Yeah, about that. There is rumor: "Ryzen don't have physical realization of tRFC2 and tRFC4". So everyone recommend to set in on "Auto". I tried to find source of it, but didn't founded any. When i read "set it on auto", i just calculate correct value.

Since i started my "game" with RAM, i founded one problem: how to compare results? There are obvious results, like BSOD or segnificant drop in latency\read\write, but some just unknown. I changed value, but don't know how to find result. It's like shooting with closed eyes. And after shot you open them and look around what you hit (and find nothing).


----------



## Veii

T[]RK said:


> I did one attempt to do it. I founded tRCPAGE in BIOS, but it not let me enter 1024 or 2048. I can enter 512, but it's not my option. Maybe i must enter "1" or "2" (which is possible), but how then people enter "512"? Strange. Set it in Auto...
> 
> Oh-h-h... Another parameter which isn't in calculator (ZenTimings). Nice. =)
> 
> 
> Yeah, about that. There is rumor: "Ryzen don't have physical realization of tRFC2 and tRFC4". So everyone recommend to set in on "Auto". I tried to find source of it, but didn't founded any. When i read "set it on auto", i just calculate correct value.
> 
> Since i started my "game" with RAM, i founded one problem: how to compare results? There are obvious results, like BSOD or significant drop in latency\read\write, but some just unknown. I changed value, but don't know how to find result. It's like shooting with closed eyes. And after shot you open them and look around what you hit (and find nothing).


It is in the debug window, i asked it to be added
but it also reads it out as 0 . But it can not be 0 because it's "minimum average"
It has to be ~something~ on stock
Sadly ZT can not track it

You can start by going half of tRFC, but it doesn't lead to always good results
it made issues together with tCKE - soo i stopped testing on it for a bit.
Auto is fine, after all memory is dynamic

SiSoftware Sandra - Multi-Core efficiency, test (is your best friend)
Passmark has also one that shows a curve between different dataset sizes

I got  on that my system is "too stable" and how horrible Aida64 latency test is, what a bad program
The person had a sheet infront of him, masking half of the viewpoint ~ that the issue is his system being variable down to 2-4ns , instead of 0.1ns
Usually aida64 tells this story quite fast and TM5 does on errors

On effectiveness, you have to test with SiSandra MCE
I think every test (Timespy CPU, Cinebench R15/20/23 and SuperPi 1.5 SX) do show differences
Subtle, but they are there. 
Sadly subtle changes need a controlled environment, else you can not see the squirrel in a Forrest full of trees.
Before Sandra MCE makes sense, you need to be sure your L3 cache is fine and you have no clock stretching
(curve optimizer)

5600X = 120A Fuse EDC
5800X= 140A Fuse EDC / but it is strange and bypasses all it's limits
5900X & 5950X = 200A Fuse EDC

Memory OC will go into PPT and EDC limit , the SOC used ~ soo a little fixed liftoff is needed
Since 1.2.0.0 AGESA, you can use 400A EDC on 1CCD units & 600A EDC on 2 CCD units to have a cache speed bump ~ but you need to limit TDC lower , (sub 100 on 1CCD ~ near 150-170 on 2 CCD)
on 1.2.0.1 , that EDC tweak is not needed 
But lifting them up higher, is needed on memOC


----------



## T[]RK

Veii said:


> SiSoftware Sandra - Multi-Core efficiency, test (is your best friend)
> Passmark has also one that shows a curve between different dataset sizes


Cool, that's already something. I will look for it.



Veii said:


> issue is his system being variable down to 2-4ns , instead of 0.1ns


Yeah, exactly. I have to wait till Task Manager show less then 1% load on system before hit "Start" button. It give me sort of relible data and diffirence between latency result was 0.1ns, 0.3ns. But then i start collect not 3 in a row, but 5 runs and things go wrong... it sometime jump on 1.2 - 1.4ns out from nowhere. But mainly i was focused on procODT during this tests, maybe it wrong benchmark for it. But in general data start to show that lower procODT got higher latency (maybe i should test with diffirent CAD_BUS, but it requied at least building procedure how to test).



Veii said:


> I think every test (Timespy CPU, Cinebench R15/20/23 and SuperPi 1.5 SX) do show differences


I got TimeSpy from one of the sales, so i may use it for testing. But ain't it pure CPU test? Also, it's so short (~15 seconds). I did few tests with diffirent procODT and results was strange. 3 in a row tests show degradation (each next test show lower result) and i have no idea why. But results was indeed idffirent between procODT values.



Veii said:


> Before Sandra MCE makes sense, you need to be sure your L3 cache is fine and you have no clock stretching
> (curve optimizer)


Since i am on UnderVolted CPU, i don't have Curve Optimizer, only PBO Auto. But L3 cache is broken anyway since i still on AGESA 1.2.0.0 and no news from GIGABYTE about 1.2.0.1, and i don't want to unbox my ASUS Dark Hero yet (it already got 1.2.0.1) to collect dust in open bench.


----------



## Pictus

Veii said:


> There are no hard-rules & JEDEC is not the book of wisdom to blindly follow
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Ryzen Google Calculator! https://docs.google.com/spreadsheets/d/1cJmhO62WHPLNKGBtsJV3BjdL-dcfJJeyhdSAoJmuzJE_ Created from "Google Sheets" For mobile users, you need the Google Sheets app. Made for me to learn about timings I'd appreciate it if anyone tell me any advice or improvements...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> This where couple of suggestions with "patterns" as you've asked
> But even that was 7 months old. Exploits improved, and balancing improved


Hi Master!

It is a Crucial Ballistix [email protected] 2x16GB dual rank Micron Rev.E
The Thaiphoon report here.
































The integralfx/MemTestHelper mention tRFC(ns) for Rev.E to be in the range of 290-310ns, but I decided to stay safe with VDIMM 1.38V and tRFC 321ns

It is stable, no problems with Y-cruncher, TM5 and Prime95.
it is just to be stable, no record breaking or too much in the edge, 3733MHz is fine.
I hope I didn't make any mistakes...
Any recommendation?

Thank you!! 🍻


----------



## T[]RK

Veii said:


> First before everything, get it GDM off stable ~ then we can talk


Have to cheat here. GDM [email protected] 10 cycles of TM5. Zero errors. Changed CAD_BUS, removed CAD_BUS_Timings, tested RTTs 0/0/5 (will do 5/3/6 and 7/0/6 too).









I also tested GDM [email protected] It was DISASTER: purple screens of death after log in in Windows or run AIDA64. TM5 show A LOT errors #6 (like 30-40 instantly).

Also tested original XMP timings with motherboard procODT (53.3), RTTs (0/0/5) and CAD_BUS (24-24-24-24), no CAD_BUS_Timings (0-0-0). No boot till i change ClkDrvStr on 40. With "40" i can get in windows, but TM5 show me A LOT errors. I don't want to fix this...it's a mess.

So i returned to Tuned XMP profile, but with CAD_BUS 60-20-20-20. It was more stable, since i can complete at least one TM5 cycle. There was errors 10 then I changed tRDWR 8 => 10 & tWRRD 3 => 5 got error 9, changed tWR 12 => 22 and VDIMM 1.40 => 1.45, RTTs 7/0/6 => 0/0/5 and got error 12.. Still, very small amout of time before error. So unstable comparing 2T...


----------



## Ramad

T[]RK said:


> I did one attempt to do it. I founded tRCPAGE in BIOS, but it not let me enter 1024 or 2048. I can enter 512, but it's not my option. Maybe i must enter "1" or "2" (which is possible), but how then people enter "512"? Strange. Set it in Auto...


Page Size is not a timing, Page Size is called "Memory Interleaving Size" and you can find it under AMD CBS / DF Common Options, if it's available in your BIOS.

If you have the options in the BIOS:

Memory Interleaving : Set to *Die* or *Socket*
Memory Interleaving Size: Set to *1KB*












Veii said:


> 2T During normal operation but yet slower than GDM Off 2T
> 
> I was driving the 1.5T train for at least a year, but at some time it made no sense.
> What was shared as specs information, be it shared correctly or not ~ never aligned with the test results
> Soo i looked at other places, for example the big piece on korean Naver & Chinese Chiphell ~ sites
> This changed the "1.5T to 2.5T" terminology
> While you are correct that it's variable , and an own thing ~ actually yes i do agree, no xT but just GDM would make more sense to call it
> 
> But it certainly is not 1.5T what people called it for illustration purposes - and it also is quite slower than 2T
> I just changed information resources away from reddit and ocn for this ~ as what was teached here the last couple of years, doesn't align up with any test results
> 
> The same goes for JEDEC,
> There are many iterations of it - but we since a long time do not follow it
> Neither does AMD nor does Micron (Micron makes their own rules and own working conditions on own PCBs)
> Everyone uses that technical JEDEC book as source ~ but trying to unify one specs sheet as the global rule, doesn't work
> It's exceptions and rulebreakers ontop of exceptions
> 
> -----------
> 
> I don't know either why you expect it to have a link.
> It's my anchor point. Early on it was tCL , but this is far more accurate.
> Till i can simulate tSTAG with all the variables needed and so use it for tRFC calculation ~ this anchor point is the closest that makes sense
> 
> Sense, i don't think i'll try to explain again & keep it as my own rulesets
> I tried to share how i work, but was on this exact topic already for the 4th time put to  with a grouped intention of making my day bad
> The problem was that these groups of people where not discussion capable nor to speak without swearing.
> They keep repeating and increasing ~ soo i stop to explain the reason for it
> Use it or don't use it
> You can give it a try and check how it works ~ but technical explanations won't work here, as it's just my anchor point for something bigger
> 
> I feel everyone who judges on it, hasn't even bothered to try. Their only intention is to destructively break everything that doesn't align with their methods.
> Don't ask me how often i have to revert the little docs against groups who intentionally break it
> 
> ---------------


Why bother with parameters you can't control, such as tSTAG, BL8 or BC4. Why even include them into consideration when the RAM itself and/or the IMC takes care of them for the user. 

And when you are dealing with parameters that you can calculate correctly (assuming you know how) using the data sheet, which then translates to something that your RAM can understand. You will end up with something like this:











This is my timings calculator since 2018, which I use to calculate timings such as tRFC according to the manufacturers data sheet. From the image above I will extract the timings for tRFC and IMC timings the I change the memory speed in the ark to get the rest of timings that I want to run my RAM at:










I could very well use the combination of tRFC and IMC timing from the first image and the subtimings from the second image to run my RAM at 3800MT/s as an example. I have this ark in my mobile phone, and this is how I calculate my timings using the ark in my phone. And this is an actual calculator, not a preset container.



Spoiler


----------



## TimeDrapery

Hello all,

My Cache & Memory Benchmark and ZenTimings screenshot










*Edit: Just realized I can display the screenshot here in my reply*

The above link contains my current configuration and performance info

I'm seeking advice/constructive criticism on what I can do to improve the performance and stability of my 2×8GB K4A8G085WB-BCPB kit (TEAMGROUP-UD4-4000)

If you've got a second and you take a look/provide feedback, thank you in advance!!!


----------



## Br3ach

Do you have a stability problem...? tRCDRD 15 should be possible, tCWL 14 / tRDWR 8 / tWRRD 3 is potentially better. The rest looks good to me.


----------



## Br3ach

Veii said:


> Lower SD, DDs eat performance don't "add" performance
> Higher add preformance but can overlapp with other timings
> 
> Lower SCL adds performance, a quite significant one - but is PCB dependend and needs revaluated tRDWR and tWRRD scaling
> Increasing SCL adds stability if needed, But lowering it is a good suggestion - just won't always work


Hmmm... I've actually benchmarked them all, and honestly difference between 2 and 4 SCLs and 1 vs 4 SDs was within the margin of error. Maybe compensated by other timings? By the way tFAW 6 does seem to benchmark higher, at least in my case.


----------



## Nighthog

Had issues randomly with my MEM OC when increasing heat & longevity of tests. (4200+)

Needed to redo my settings for most part to try find the cause, as it was random.
After a longer period more and more errors kept coming to what seemed to have been stable earlier.

Was for the most part a issue with tRDWR to tRCDRD/tRCDWR & then issues with the tRDRDSD/tRDRDDD & tWRWRSD/tWRWRDD after a lengthy 2 day diagnosis of settings.
I thought it was voltage or DrvStr & Ohm issue but kept getting no fix changing those around. So many variables.

Got a 20 cycle pass for once, need to better the timings now as I finally found the main culprits.
Though most likely I finally gonna try 4333Mhz now as the same issue was the main culprit there for stability.


----------



## TimeDrapery

Br3ach said:


> Do you have a stability problem...? tRCDRD 15 should be possible, tCWL 14 / tRDWR 8 / tWRRD 3 is potentially better. The rest looks good to me.


Yessir, I do have a stable profile but this one I'm trying to work down from my last stable values and I'm encountering errors in TM5... Should have completed the latest test iteration by the time I'm in the house so I'll see what came of this go round

*Edit: Here's the results of the latest round of TM5...*


----------



## Veii

Ramad said:


> Why bother with parameters you can't control, such as tSTAG, BL8 or BC4. Why even include them into consideration when the RAM itself and/or the IMC takes care of them for the user.


Because nevertheless what dimms do , it's according to the range of your setup
Which depends on the dataset sizes used, and pretty much the range you put for:
tFAW, tRAS, tRC, SD/DDs, tRDWR/tWRRD & SCL
* well technically also tRFC

up to these parameters [IF stable]
(faster or slower not taking into consideration)
The remain 20+ timings in the hidden adjust to it

This is why i follow my own rules for this system
If we'd talk for intel's IMC, probably couple of sets would change ~ as the rules are different and minimum values are different


Ramad said:


> This is my timings calculator since 2018, which I use to calculate timings such as tRFC according to the manufacturers data sheet. From the image above I will extract the timings for tRFC and IMC timings the I change the memory speed in the ark to get the rest of timings that I want to run my RAM at:


You know what i find interesting,
The tRTP part 
It randomly matches to the same conclusion i came ~ although what i use, was own research without a manual by hand

tRTP and tWR i do take tRFC as anchor point , but tRTP & tWR together are a "failsafe always working" method 
Try to turn both into ns values, and see what is a clean divider of target tRFC. optimally 1 digit decimal, at worst 4 digit decimal.


Ramad said:


> Why bother with parameters you can't control, such as tSTAG


tSTAG changes not only by frequency & i have a feeling that it can be used for positive
At least for tRFC.
The little one you saw online is not the lowest ruleset. i used to play with tRFC on "cycles"
Cycles in the sense of 1/2, 1/4, 1/8, 1/16, 1/32th

values from X tRFC, of which you can decrease it by ~ to trigger a stacking refresh cycle or "overcharge"
No i should call it, "using left current in the cells for pushing one more read stage through"
Idk how to call it ~ anyways it's an exploit / and the reason why i considered tBURST in the first place
* if you drop it by 1,2,3 random value, it will be "offsync" and postponed at best or crashing at worst after some time

But it needs precise timing, which i can't at all do without understanding how tSTAG is even made and created
Soo i just focused on other anchor points ~ and down to 116ns tRFC , they remain functional.
Haven't seen big problems with the method, except that it certainly lacks capacity awareness.








Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com




The DATA and pre-release sheets get well worken on. It makes good progress, but it would be unfair to just "borrow" and re-use the research/formula from everyone else ~ to better up my tools.
I'm glad your little calculator looks well build with good logic
Good Job !  Surely took a lot of time


Nighthog said:


> Got a 20 cycle pass for once, need to better the timings now as I finally found the main culprits.
> Though most likely I finally gonna try 4333Mhz now as the same issue was the main culprit there for stability.


Also great job, you'll get there 😇
4200 is indeed quite hard, haha. You'll notice very fast how one little change destabilizes everything


Br3ach said:


> Hmmm... I've actually benchmarked them all, and honestly difference between 2 and 4 SCLs and 1 vs 4 SDs was within the margin of error. Maybe compensated by other timings? By the way tFAW 6 does seem to benchmark higher, at least in my case.
> View attachment 2483440


You missed (maybe) the point that it needs tRAS+1 = tRC - exploit, for 1x tFAW exploit to work
Else it won't work and misstime
In order for tRC exploit to work, you need to cover up the delay elsewhere
Meaning, tRRD_S/_L , tWTR , and tRDWR
Likely also SD,DDs but i think it can work also on 1-4-4-1-6-6




T[]RK said:


> Have to cheat here. GDM [email protected] 10 cycles of TM5. Zero errors. Changed CAD_BUS, removed CAD_BUS_Timings, tested RTTs 0/0/5 (will do 5/3/6 and 7/0/6 too).
> View attachment 2483432
> 
> 
> I also tested GDM [email protected] It was DISASTER: purple screens of death after log in in Windows or run AIDA64. TM5 show A LOT errors #6 (like 30-40 instantly).
> 
> Also tested original XMP timings with motherboard procODT (53.3), RTTs (0/0/5) and CAD_BUS (24-24-24-24), no CAD_BUS_Timings (0-0-0). No boot till i change ClkDrvStr on 40. With "40" i can get in windows, but TM5 show me A LOT errors. I don't want to fix this...it's a mess.
> 
> So i returned to Tuned XMP profile, but with CAD_BUS 60-20-20-20. It was more stable, since i can complete at least one TM5 cycle. There was errors 10 then I changed tRDWR 8 => 10 & tWRRD 3 => 5 got error 9, changed tWR 12 => 22 and VDIMM 1.40 => 1.45, RTTs 7/0/6 => 0/0/5 and got error 12.. Still, very small amout of time before error. So unstable comparing 2T...


Increase that tRRD, tWTR
Don't keep them low. I know it looks very good and my advice sounds very bad.
But primaries have more priority than tRRD_ and tWTR_ or tFAW delays
Get your primaries low and 1T (first 2T with powering) under control

These + tRDWR + SD,DD & SCLs
you later can get under control
Primaries matter more. Even more than low tRFC & tWR

Depending on the voltage you use (i think you can go with just 706 or even 607)
even 705 is better (but needs >1.48v) than 005
Get the powering correct. Staying on 005 is only good for low voltages
Sadly not healthy for high voltages
But you should be able to run a flat 14-14 set
Or can fully "yolo" and go 15-15 for higher frequency & just keep increasing voltage
Well 16-16 should run, soo get your tertiaries higher. Can't be that you have issues with such easy to run set
Which speaking off ~ is


Spoiler: this












eeh my tRFC2 was messed up here, it's 288-214-132


 really unstable for you @ 1T ?


----------



## zGunBLADEz

GDM on/off it shouldnt be a issue if you can boot straight to 1t. Idk why ppl throwing a hissy fit for it. It helps on booting up sticks specially DR kits. Even when use 2t alone the sticks wont post so gdm help to post and also help with cold boot issues.

Also the way pbo/boosting behavior works for aida readings specially latency i would not take too seriously.
Bios 1803 pre agesa usb/l3 cache fix i was getting 54ns as windows was choosing the right cores to boost. With the new bios it went up to 57ns as its choosing the first core which is my 3rd best core in the line up on the silicon.

Like i said latency should be taken on the multiplier used on an all core load instead. So if your cpu boost all cores to 46x thats where it should be measure instead as cpu usage goes up your latency goes up thats the end of it. That goes the same way on what mobo/bios/os detect your best cores thats why alot of people seeing discrepancys also the utter max the cpu is capable of boosting. More mhz less latency in the time of reading. Every sku is different in that regards. Also surfing thru the pages im seeing alot of users with ridiculous timings like [email protected]/14s. Ending with the same "aida readings" when i know for a fact that the IF is holding the kit back even @ 1900.. So whats the point? Loose those timings up.. if having issues a ram stress test probably will pass or later on that the road the way pbo behaves would throw errors at you. 

Amd cheat his way up also you will be lying to yourself as well. That false sense of performance with pbo xD not saying aint useful at all just in this case or some synthetic benchmarks.


----------



## hsn

Can i get more timing with 1.47v?
because i use mini itx casing. and i dont put fan onmy ram.


----------



## eliwankenobi

hsn said:


> Can i get more timing with 1.47v?
> because i use mini itx casing. and i dont put fan onmy ram.
> View attachment 2483472


You should be able to push CL14 timings. If not maybe at 1.5volts...


----------



## T884G63

Ok guys I need a little help from everyone can you post what you have changed as far as power state / power plan options in your bios?

Since there are a good amount of forum lurkers and this thread is getting a lot of random traffic from Google searching for people trying to get help with settings.

And seeing as there is ZERO similarities across any of the zen 3 cpu's or motherboards
SOC, VDDP, VDDG, CCD all wildly different in the Google Overclocking DOC that nothing can be tracked.

I have been doing a lot of testing with:
2x Dark Hero's
2x 5600x
2x 5800x
2x 5900x
1x 5950x

And with my newest 5950x I have been able to run 2000 fclk 1:1 stable (2033 highest but Aida test shows lowered cache speeds) @ any combination of voltages I throw at it. And I mean any down to 850mv soc, vddp, vddg, ccd
and up to 1200mv across all.

100% stable under all tests but I get a recurring whea 19 "0" when in a lower idle state for longer then 60sec but under any light to heavy load nothing... 850mv to 1200mv no difference in any test and cache latencies remain same.

Having seen first hand that there must be a massive variance across the silicon that some of these samples are so extremely finicky that if all the voltages aren't within 10-30mv of that particular samples sweet spot is then pushing flck is a no go.


----------



## GribblyStick

zGunBLADEz said:


> GDM on/off it shouldnt be a issue if you can boot straight to 1t. Idk why ppl throwing a hissy fit for it. It helps on booting up sticks specially DR kits. Even when use 2t alone the sticks wont post so gdm help to post and also help with cold boot issues.
> 
> Also the way pbo/boosting behavior works for aida readings specially latency i would not take too seriously.
> Bios 1803 pre agesa usb/l3 cache fix i was getting 54ns as windows was choosing the right cores to boost. With the new bios it went up to 57ns as its choosing the first core which is my 3rd best core in the line up on the silicon.
> 
> Like i said latency should be taken on the multiplier used on an all core load instead. So if your cpu boost all cores to 46x thats where it should be measure instead as cpu usage goes up your latency goes up thats the end of it. That goes the same way on what mobo/bios/os detect your best cores thats why alot of people seeing discrepancys also the utter max the cpu is capable of boosting. More mhz less latency in the time of reading. Every sku is different in that regards. Also surfing thru the pages im seeing alot of users with ridiculous timings like [email protected]/14s. Ending with the same "aida readings" when i know for a fact that the IF is holding the kit back even @ 1900.. So whats the point? Loose those timings up.. if having issues a ram stress test probably will pass or later on that the road the way pbo behaves would throw errors at you.
> 
> Amd cheat his way up also you will be lying to yourself as well. That false sense of performance with pbo xD not saying aint useful at all just in this case or some synthetic benchmarks.


that has not been my experience at all. It Massively difficult to boot on 1T GDM OFF compared to 1T GDM ON.
I can boot 2T GDM off no issue, 1T GDM ON same, but I find it damn near impossible to run any settings on 1T GDM OFF.
Here's my current setup that will probably stay that way until I get a custom loop installed, not that I expect that to change much, my RAM temperatures at a little over 30 after an overnight Prime95.


Spoiler: timings






















If I switch this to 1T, it will immediately start blue screening and diagnosing, doesn't even train near as I can tell.
If I try loosening timing then it will start training but no combination of timings/voltages seems to work to get a successful boot.
So I have no idea what is most helpful in getting 1T stable.

I haven't tried setting this memory interleaving manually but that will have to wait until I take the dimms apart to install the RAM cooler. To be sure what PCB I have.
I can probably run C14 too but I have no idea how to fix the errors I get. It boots just fine, even without loosening timings but I get wwwaayy too many error 6s to bother fixing for now. This is despite being able to run CL14 with those settings on 2 sticks without error (not a full run, but no immediate errors at least) and 1T on C14 and 16 without training failures between switching ,but both with errors on TM5. 2000 IF just doesn't work right and I'll have to wait for the next AGESA before retrying that.


----------



## GribblyStick

T884G63 said:


> Ok guys I need a little help from everyone can you post what you have changed as far as power state / power plan options in your bios?
> 
> Since there are a good amount of forum lurkers and this thread is getting a lot of random traffic from Google searching for people trying to get help with settings.
> 
> And seeing as there is ZERO similarities across any of the zen 3 cpu's or motherboards in the Google Overclocking DOC that can be tracked.
> 
> I have been doing a lot of testing with:
> 2x Dark Hero's
> 2x 5600x
> 2x 5800x
> 2x 5900x
> 1x 5950x
> 
> And with my newest 5950x I have been able to run 2000 fclk 1:1 stable (2033 highest but Aida test shows lowered cache speeds) @ any combination of voltages I throw at it.
> 
> 100% stable under all tests but I get whea's when in a lower idle state for longer then 60sec but under any light to heavy load nothing...
> 
> Having seen first hand that there must be a massive variance across the silicon that some of these samples are so extremely finicky that if all the voltages aren't within 10-30mv of that particular samples sweet spot is then pushing flck is a no go.


Only thing I have changed in terms of power was to install ManniX-ITAs max performance plan in windows, as suggested by @Veii: ultimate performance
And setting LLC to 5 as that seemed to be the only setting that actually sets SOC to what I have in BIOS (as per ZEN), but I don't know how I feel about that.
Heard it might not be ideal.


----------



## nikpoth

[QUOTE = "Veii, post: 28761606, μέλος: 609138"]



up to these parameters [IF stable]
View attachment 2483459

eeh my tRFC2 was messed up here, it's 288-214-132[/SPOILER] really unstable for you @ 1T ?
[/QUOTE]
What are your settings vddp, soc,vddg iod and ram voltage in bios?


----------



## DarkEmpire

4x8gb
vdimm voltage 1.4

tell me how you can further reduce latency?
when the tRC is lowered to 56, errors #0 and #2 begin to crawl into TM5, I don't know what to do anymore...


----------



## zGunBLADEz

GribblyStick said:


> that has not been my experience at all. It Massively difficult to boot on 1T GDM OFF compared to 1T GDM ON.
> I can boot 2T GDM off no issue, 1T GDM ON same, but I find it damn near impossible to run any settings on 1T GDM OFF.
> Here's my current setup that will probably stay that way until I get a custom loop installed, not that I expect that to change much, my RAM temperatures at a little over 30 after an overnight Prime95.
> 
> 
> Spoiler: timings
> 
> 
> 
> 
> View attachment 2483478
> View attachment 2483477
> 
> 
> 
> 
> If I switch this to 1T, it will immediately start blue screening and diagnosing, doesn't even train near as I can tell.
> If I try loosening timing then it will start training but no combination of timings/voltages seems to work to get a successful boot.
> So I have no idea what is most helpful in getting 1T stable.
> 
> I haven't tried setting this memory interleaving manually but that will have to wait until I take the dimms apart to install the RAM cooler. To be sure what PCB I have.
> I can probably run C14 too but I have no idea how to fix the errors I get. It boots just fine, even without loosening timings but I get wwwaayy too many error 6s to bother fixing for now. This is despite being able to run CL14 with those settings on 2 sticks without error (not a full run, but no immediate errors at least) and 1T on C14 and 16 without training failures between switching ,but both with errors on TM5. 2000 IF just doesn't work right and I'll have to wait for the next AGESA before retrying that.


Was talking about how gdm on let you boot DR kits better in that regards..

Now to your question/dilemma...

Looking a few pages back probably some timing issues xD..

Cant comment on that when i see my [email protected] getting the same amount of scores that most kits here with ridiculous low timings. At least i know my kit is stable at those timings.. Outside that amd/IF cap which is "make believe" xD


----------



## eliwankenobi

GribblyStick said:


> that has not been my experience at all. It Massively difficult to boot on 1T GDM OFF compared to 1T GDM ON.
> I can boot 2T GDM off no issue, 1T GDM ON same, but I find it damn near impossible to run any settings on 1T GDM OFF.
> Here's my current setup that will probably stay that way until I get a custom loop installed, not that I expect that to change much, my RAM temperatures at a little over 30 after an overnight Prime95.
> 
> 
> Spoiler: timings
> 
> 
> 
> 
> View attachment 2483478
> View attachment 2483477
> 
> 
> 
> 
> If I switch this to 1T, it will immediately start blue screening and diagnosing, doesn't even train near as I can tell.
> If I try loosening timing then it will start training but no combination of timings/voltages seems to work to get a successful boot.
> So I have no idea what is most helpful in getting 1T stable.
> 
> I haven't tried setting this memory interleaving manually but that will have to wait until I take the dimms apart to install the RAM cooler. To be sure what PCB I have.
> I can probably run C14 too but I have no idea how to fix the errors I get. It boots just fine, even without loosening timings but I get wwwaayy too many error 6s to bother fixing for now. This is despite being able to run CL14 with those settings on 2 sticks without error (not a full run, but no immediate errors at least) and 1T on C14 and 16 without training failures between switching ,but both with errors on TM5. 2000 IF just doesn't work right and I'll have to wait for the next AGESA before retrying that.


I am no expert.. but in my short experience working with my Zen 2 CPU and short experience with my Zen3 ... GDM is a godsend... weird that it isn't stable with GDM ON. At least you can boot at 3800mhz. My 5900x only did 3733mhz max but was RMA'd due to other issue.


----------



## Flash1228

DarkEmpire said:


> 4x8gb
> vdimm voltage 1.4
> 
> tell me how you can further reduce latency?
> when the tRC is lowered to 56, errors #0 and #2 begin to crawl into TM5, I don't know what to do anymore...


I've got a similar setup with 4x8GB Micron Rev. E at 1.43v. Dunno if any of these timings help, but FWIW once I updated to AGESA 1.2.0.1 SD/DD/SC values changed. Auto values used to follow the Ryzen Google Calculator A1 numbers, but now I get this. If I change it to the previous values of 1-5-4-1-7-6 I get errors. Same as with 1-4-4-1-6-6 like you have. You should have a go at 2T GDM off.


----------



## T[]RK

Veii said:


> Depending on the voltage you use (i think you can go with just 706 or even 607)
> even 705 is better (but needs >1.48v) than 005
> Get the powering correct. Staying on 005 is only good for low voltages
> Sadly not healthy for high voltages


But what "low voltages" exactly is? 1.35V (which is default for my XMP) is "low"? Or it's up to 1.45V? Everything that more then 1.5V are "high"?



Veii said:


> Don't keep them low. I know it looks very good and my advice sounds very bad.
> But primaries have more priority than tRRD_ and tWTR_ or tFAW delays


No-no, it's sound good. When i used Google Ryzen Calculator i saw options for tFAW=20, i just selected 16 as recommended "A-1" option. And it work well for GDM [email protected], can't complain about that. Stable timings i got completely from Google Ryzen Calculator (mostly A-1 options with small calculation and confirmations).



Veii said:


> Or can fully "yolo" and go 15-15 for higher frequency & just keep increasing voltage


I want to deal with 3600CL16 first, then move to 3800CL16 and only after that to CL14. Jump around not good thing, especially when Team Group rare to see (mostly G.Skill). Get things right and maybe later somebody may use this settings.



Veii said:


> Well 16-16 should run, soo get your tertiaries higher. Can't be that you have issues with such easy to run set
> Which speaking off ~ is
> 
> 
> Spoiler: this
> 
> 
> 
> eeh my tRFC2 was messed up here, it's 288-214-132
> 
> 
> really unstable for you @ 1T ?


When i try G.Skill settings on Team Group RAM it's mostly No-Go, but THIS settings actually better: POST is O.K., LogIn in Windows also O.K., no mouse lag on desktop, in TM5 at 3 complete cycles i got 3x Error #1. And it's about tRRD and tWR timings in error's description (voltage is already high - 1.45V, and tRFC calculated correctly, included 2 and 4).


----------



## DarkEmpire

Flash1228 said:


> I've got a similar setup with 4x8GB Micron Rev. E at 1.43v. Dunno if any of these timings help, but FWIW once I updated to AGESA 1.2.0.1 SD/DD/SC values changed. Auto values used to follow the Ryzen Google Calculator A1 numbers, but now I get this. If I change it to the previous values of 1-5-4-1-7-6 I get errors. Same as with 1-4-4-1-6-6 like you have. You should have a go at 2T GDM off.
> 
> View attachment 2483507


do you have elite? they seem to be much better at chasing than ordinary ones like mine, well, besides, my motherboard is worse
Is it worth turning off the GDM for 2t? What are your results in aida64?


----------



## Flash1228

DarkEmpire said:


> do you have elite? they seem to be much better at chasing than ordinary ones like mine, well, besides, my motherboard is worse
> Is it worth turning off the GDM for 2t? What are your results in aida64?


I do have Ballistix Elites rated at 4000CL18, but since I get ton of WHEAs with IF over 1900 I've been working on tuning them at 3800. I'd say it's worth trying to stabilize 2T w/GDM off as GDM enabled will round up a lot (maybe all?) odd number timings. So your tRCDWR - 15, tRCDRD - 19, and tRP - 15 are effectively 16, 20, and 16.


----------



## DarkEmpire

Flash1228 said:


> WHEAs with IF over 1900


exactly the same problem, =1933+ there are WHEA errors


----------



## T884G63

If you really want to get GDM off try this in this order:
(My experience is that these bios's do not like too many changes at once but seem to work easier with incremental steps)

Save your bios profile if you have one you don't want to lose.
Reset Cmos
Leave everything Auto just go into Dram menu and disable power down and gear down reboot.

Now same but just change cmd to 1T and reboot.
Set Dram voltage reboot.

Now once those are set, set your desired memory and fclk speeds and reboot.

Then do your timings but only put in your primaries and reboot.
Then put in the rest of your timings but leave trfc's on Auto and all procODT cadbus termination on Auto reboot.

Now put in your trfc's.

If that doesn't work same thing but lock in your primary timings only but then do your memory / fclk speeds.

A ton of these Bios's are a little buggy but this is just an old-school way of incrementally doing Bios changes from my early days of overclocking 90's--2000's as some Bios's just don't have enough of an internal delay /stepping when applying settings that hinge on other settings.


----------



## T[]RK

GribblyStick said:


> If I switch this to 1T, it will immediately start blue screening and diagnosing, doesn't even train near as I can tell.
> If I try loosening timing then it will start training but no combination of timings/voltages seems to work to get a successful boot.
> So I have no idea what is most helpful in getting 1T stable.


I see only two things

1. Since you got CAD_BUS Timings 3-3-15;
2. CAD_BUS 40-20-30-20
keep only something one:

A.) CAD_BUS 40-20-30-20 + CAD_BUS Timings 0-0-0 OR
B.) CAD_BUS 40-20-20-20 + CAD_BUS Timings 3-3-15.

I saw @Veii post about CAD_BUS Timings work only if CAD_BUS have got mask XX-20-20-20. I tested it with ClkDrvStr 40 and 60 and 40 was minimum to get in Windows. Below then 40 is BSOD (ACPI BIOS Error and another one) right before Windows. If i keep CAD_BUS 40-24-24-24 and add CAD_BUS Timings 2-2-12 (in my case) - i got PSOD (Purple Screen of Death) after POST or right after Windows boot. If i was fast enought and run TM5 - there was TONNS of Error #6 = BSOD.

Here is one more example:

GDM [email protected] 1T:
1. procODT: 53.3;
2. CAD_BUS Timings: 2-2-12; (for 3600 MHz)
3. CAD_BUS: 40-20-20-20;
4. RTTs: 0/0/5

Result: POST - O.K., Windows Boot - O.K., but rundom Windows FREEZE.


----------



## T884G63

If you can Post and Boot with GDM off @1T but have issues once windows have you tried running some memory testing in Safe Mode?


----------



## MMAxp11

Hi guys

I have Crucial Ballistix Sport LT 16GB 3000 Mhz CL15 (BLS8G4D30AESBK). I also have stock Ryzen 5 3600 and MSI Tomahawk MAX. Now I am on 3733 CL16 and it looks stable in OCCT and TM5 but sometimes I'm getting audio crackling and stuttering. After some time it usually disappears. I know it's IF instability, but is it voltage issue or should I lower frequency? Also my copy looks strange.


----------



## ManniX-ITA

MMAxp11 said:


> Hi guys
> 
> I have Crucial Ballistix Sport LT 16GB 3000 Mhz CL15 (BLS8G4D30AESBK). I also have stock Ryzen 5 3600 and MSI Tomahawk MAX. Now I am on 3733 CL16 and it looks stable in OCCT and TM5 but sometimes I'm getting audio crackling and stuttering. After some time it usually disappears. I know it's IF instability, but is it voltage issue or should I lower frequency? Also my copy looks strange.
> View attachment 2483529
> View attachment 2483530


You should raise the SOC voltage and set stronger LLC.
You have it set at 1.125V but it goes down to 1.081V.
Which is too close to the 1.050V VDDG IOD.
Try with 1.15V and be sure it's reported above 1.1V in Zentimings.
If LLC is set to Auto try 3 or 4.

Can be also that 950 CCD is too low, you could try to set it at 1000.
VDDG at 1050 could be necessary but could also be too high.
I've give a try to 1000 in case.


----------



## TimeDrapery

Alright, here are this morning's results for performance benching in AIDA64 and stability testing with TestMem5 (TM5) with the 1usmus_v2 configuration applied...










Please take a look and leave me some feedback as I'm having to work through the overclocking process again due to my having flashed the most recent (F13f) Gigabyte B550 AORUS MASTER beta BIOS available

Thanks in advance!


----------



## lmfodor

Hi, yesterday I received a new memories GSkill Tridenz Neo 3800CL14 which is the new series optimized for Raizen 5000 (I have a 5900x) that it supposed to have low latency. However with the XMP profile I didn’t see a good latency +60ns and a colleague from this forum help me to quick OC and the improvement was very good at least for me. The temps before the OC was 39/41 and after when playing I’m about 45 and in a memtech it reaches almost 52 degrees. 

Configuration optimized 








Timings after the OC








Before the OC, XMP profile









What do you think about the results? 

I ran memtest86, memtest84.. I would try TM5.. anything else to try?

Thanks 


Sent from my iPhone using Tapatalk Pro


----------



## lmfodor

Delete


----------



## PowerK

Guys, for 4x8GB sticks of b-die, is 
RttNom/RttWr/RttPark = RZQ6/RZQ3/RZQ1 setting optimal?

I ask because, on X570 Aorus Extreme I had them at disabled/off/RZQ5. But changing motherboard to Asus X570 Dark Hero, the disabled/off/RZQ5 no longer works (POST failure). I could get 6/3/3 to work. Everything else being equal.

This is the current stable setting on ROG Dark Hero.










And this was the setting I used for several months on X570 Aorus Extreme.


----------



## deehoC

I just started tinkering around with a new combo (went from a 3700x and a ASUS Crosshair VI Hero to a 5800x and MSi B550 Unify-X) and so far I'm pretty happy with the results. My memory kit is a pretty old 2x8GB set of G.SKILL F4-3600C16-8GTZR 16-16-16-36 1.35v but it is currently running 2T GDM off 3800mhz/1900mhz stable and will post/bench 4000mhz/2000mhz with the same settings but isn't stable. My end goal would be to run 4000/2000 with tightened timings but I'm not quite sure how best to proceed from here. Should I find the limits of my frequency first then work on timings or start pulling the timings down and then work on achieving stable 4000?

I've set these in BIOS for voltages: 1.1v SoC, 1.05v VDDG CCD, 1.05v VDDG IOD, 1.4v VDIMM and the rest are all on auto.

I've set the primary timings to 16-16-16-16-36-52 and changed TRFC1 to 631, tRRDS 7, tRRDL 10 and tFAW 44. All of those values are from my kit's XMP profile and the rest are on auto so I'm sure there is some room for improvement in regard to my timings.

Are any of my voltages out of whack? I've done a lot of reading and tried to glean some information and some of the things I've read include: 

- Increasing the 1.8v PLL voltage a little bit would be beneficial to a high fabric clock

- Minimum Requirements of VSOC mv @ 4000mhz - <1137,5mV

- cLDO VDDP over 950mV is a waste

plus a lot more I can't remember off the top of my head...


I ran Karhu over night and then while at work I ran TM5 with the [email protected] and got 0 errors on both @ 3800mhz/1900mhz. For fun I tried testing the 4000mhz and managed to get 3902% Coverage in Karhu before getting an error so I'm hoping getting it stable isn't a pipedream.


----------



## Pictus

deehoC said:


> I've set these in BIOS for voltages: 1.1v SoC, 1.05v VDDG CCD, 1.05v VDDG IOD, 1.4v VDIMM and the rest are all on auto.


VDDG CCD = 1.05v seems a bit too much, check








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net






*--------------------------------------------------------*




PowerK said:


> Guys, for 4x8GB sticks of b-die, is
> RttNom/RttWr/RttPark = RZQ6/RZQ3/RZQ1 setting optimal?
> 
> I ask because, on X570 Aorus Extreme I had them at disabled/off/RZQ5. But changing motherboard to Asus X570 Dark Hero, the disabled/off/RZQ5 no longer works (POST failure). I could get 6/3/3 to work. Everything else being equal.



Sorry I do not know the answer, but I would like to ask what do you prefer, the Dark Hero or the XTREME?
BTW, I guess there are new beta BIOS for you motherboards








[Übersicht] - Ultimative AM4 UEFI/BIOS/AGESA Übersicht


Inhaltsverzeichnis: UEFI Collection | Hersteller Support Links | UEFI Mods | Weiterführende Links Keine weiteren Updates mehr geplant! AM5 UEFI/BIOS/AGESA Übersicht ASRock ASUS Biostar Gigabyte MSI EVGA NZXT B350 B450 B550 X370 X470 X570 B350 B450 B550 X370 X470 X570 B350 B450...




www.hardwareluxx.de






*--------------------------------------------------------*





lmfodor said:


> Hi, yesterday I received a new memories GSkill Tridenz Neo 3800CL14 which is the new series optimized for Raizen 5000 (I have a 5900x) that it supposed to have low latency. However with the XMP profile I didn’t see a good latency +60ns and a colleague from this forum help me to quick OC and the improvement was very good at least for me. The temps before the OC was 39/41 and after when playing I’m about 45 and in a memtech it reaches almost 52 degrees.
> 
> What do you think about the results?
> 
> I ran memtest86, memtest84.. I would try TM5.. anything else to try?











Your CLDO VDDP is tooooooooooooooo high!  💀
Set CLDO VDDP = 0.900
Check AMD max overclocking voltage


Memtest is no good, TM5 is good and I like Y-cruncher, press 1>8>14>0


y-cruncher - A Multi-Threaded Pi Program


and Prime95





GIMPS - Free Prime95 software downloads - PrimeNet


GIMPS has free software available for Windows, Linux, FreeBSD, Mac OSX. Contribute to the effort by using your computer's spare processing power.




www.mersenne.org


----------



## lmfodor

[IMG said:


> http://imgur.com/v9qM68z
> 
> Your CLDO VDDP is tooooooooooooooo high!  [emoji88]
> Set CLDO VDDP = 0.900
> 
> Memtest is no good, TM5 is good and I like Y-cruncher, press 1>8>14>0
> 
> 
> y-cruncher - A Multi-Threaded Pi Program
> 
> 
> and Prime95
> 
> 
> 
> 
> 
> GIMPS - Free Prime95 software downloads - PrimeNet
> 
> 
> GIMPS has free software available for Windows, Linux, FreeBSD, Mac OSX. Contribute to the effort by using your computer's spare processing power.
> 
> 
> 
> 
> www.mersenne.org



Ok! You really scared me!!! I’m a really noob with memory OC. I just selected the XMP profile that is supposed to be optimized for Raizen 5000 and I knew that this mem runs with 1.5v. That’s all I know. This is the memory:










And now the results updated, it is fine? Anything else at first sight to change?


















Indeed I just run for the first time the TM5 v0.12 with two configurations (2020 Extreme Anta777 and 1usmusv3) and both failed. I never used it. Could it be the VDDP?

Regarding MTF, I downloaded a version that include several config files (best config) Is it only a single MT5.exe without any other file in the directory? Then I have a folder with several configs. I only run with admin privileges, am I fine?

I had run last night memtesr86 without any issue. Today I ran Memtest64 also without issue. I also run OOCT for and hour without any issue.
Now I’m running again MT5 with the extreme anta.. let’s see if it fails. And also I’m gonna run y cruncher.. thanks!!

Sent from my iPhone using Tapatalk Pro


----------



## T[]RK

lmfodor said:


> Anything else at first sight to change?


I remember @Veii post about RTT_PARK 1 and High vDIMM voltage. DONT USE IT! It may kill you hardware. You already got RAM with XMP 1.5V. I guess RTT_Park at this stage should be 3 minimum. Untill you understand how it’s act.









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


try to drop PCIe to gen 3, still X16 mode, disable data link saving feature in AMD PBS and in AMD CBS -> NBIO , enable SRIS and AER Cap,(ACS enabled) Nah... Tried all that with no avail. Disabling LAN in bios didn't help either. The one thing is thought to help is to look at agesa parts...




www.overclock.net


----------



## PowerK

Pictus said:


> Sorry I do not know the answer, but I would like to ask what do you prefer, the Dark Hero or the XTREME?
> BTW, I guess there are new beta BIOS for you motherboards


No problem. They both are good. Can't say which one is better. (We're using both at home). However, I really like Dynamic Overclock Switcher of the Dark Hero.


----------



## lmfodor

T[]RK said:


> I remember @Veii post about RTT_PARK 1 and High vDIMM voltage. DONT USE IT! It may kill you hardware. You already got RAM with XMP 1.5V. I guess RTT_Park at this stage should be 3 minimum. Untill you understand how it’s act.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> try to drop PCIe to gen 3, still X16 mode, disable data link saving feature in AMD PBS and in AMD CBS -> NBIO , enable SRIS and AER Cap,(ACS enabled) Nah... Tried all that with no avail. Disabling LAN in bios didn't help either. The one thing is thought to help is to look at agesa parts...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> Also, CAD_BUS is diffirent on you Dark Hero and Xtreme screens.


Hi, this is the first time I read about RTT_PARK1. I didn’t touch anything in BIOS. I’m googling it to find out where to change to 3, is that the recommended value for high voltage DIMMs? My mobo is a CH8 Wifi, not the dark .. 

Thanks!


Sent from my iPhone using Tapatalk Pro


----------



## GribblyStick

lmfodor said:


> Ok! You really scared me!!! I’m a really noob with memory OC. I just selected the XMP profile that is supposed to be optimized for Raizen 5000 and I knew that this mem runs with 1.5v. That’s all I know. This is the memory:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> And now the results updated, it is fine? Anything else at first sight to change?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Indeed I just run for the first time the TM5 v0.12 with two configurations (2020 Extreme Anta777 and 1usmusv3) and both failed. I never used it. Could it be the VDDP?
> 
> Regarding MTF, I downloaded a version that include several config files (best config) Is it only a single MT5.exe without any other file in the directory? Then I have a folder with several configs. I only run with admin privileges, am I fine?
> 
> I had run last night memtesr86 without any issue. Today I ran Memtest64 also without issue. I also run OOCT for and hour without any issue.
> Now I’m running again MT5 with the extreme anta.. let’s see if it fails. And also I’m gonna run y cruncher.. thanks!!
> 
> Sent from my iPhone using Tapatalk Pro


 That's pretty much what I have on the same board/processor:


Spoiler: crosshair 8 / 5900x


----------



## T[]RK

lmfodor said:


> I didn’t touch anything in BIOS.


But on you screenshot of ZenTimings RTT_Park is 1. =) Maybe you didn't touched it, but it's is there.



lmfodor said:


> My mobo is a CH8 Wifi, not the dark ..


Yes, my mistake. @PowerK got Dark Hero. iPhone 6s screen is too small for all this screenshots. %)



PowerK said:


> RttNom/RttWr/RttPark = RZQ6/RZQ3/RZQ1 setting optimal?


Same as @lmfodor, be careful with RTT_Park=1 and High vDIMM voltage.

Here is another quote:


Veii said:


> On sub 1.5v it shouldn't matter, but i do not suggest to run RTT_PARK /1 on anything . . . at all
> It's too high
> Even if you figure out a combination with X/X/2 , would be better , high but still better





PowerK said:


> I could get 6/3/3 to work. Everything else being equal.


CAD_BUS is diffirent on screenshots: 24-20-24-24 on Dark Hero, and 60-20-24-24 on Xtreme.


----------



## GribblyStick

I tried with 1T, everything else on auto except voltages, and frequency, 3200 runs, but I start getting errors on 3600. 
On auto it sets primaries at 25. that is so high I can't even follow the suggested values by the ryzen calculator sheet as I hit the upper limits of my bios.
By manually setting RTTs/CADBUS I got it almost stable, but still, that was at voltage settings similar to what I am running for 2T 3800.

I stopped trying there because that didn't really seem worth the energy if I have to run timings THAT loose to run 1T and I wasn't even at 3800 yet.
When I tried lowering it to 22 so I could at least follow suggested values, I wasn't even able to post anymore.
Or is there such a thing as TOO loose?


----------



## RosaPanteren

T[]RK said:


> I remember @Veii post about RTT_PARK 1 and High vDIMM voltage. DONT USE IT! It may kill you hardware. You already got RAM with XMP 1.5V. I guess RTT_Park at this stage should be 3 minimum. Untill you understand how it’s act.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> try to drop PCIe to gen 3, still X16 mode, disable data link saving feature in AMD PBS and in AMD CBS -> NBIO , enable SRIS and AER Cap,(ACS enabled) Nah... Tried all that with no avail. Disabling LAN in bios didn't help either. The one thing is thought to help is to look at agesa parts...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> Also, CAD_BUS is diffirent on you Dark Hero and Xtreme screens.


I think the Rtt_Park = 1 / 240ohm was a PCB specific issue related to A0 PCB design

His PCB is probably B2 or smth exotic so it shouldn't matter, his XMP probably defaults to Rtt_Park = 1 @1.5v




lmfodor said:


> Hi, this is the first time I read about RTT_PARK1. I didn’t touch anything in BIOS. I’m googling it to find out where to change to 3, is that the recommended value for high voltage DIMMs? My mobo is a CH8 Wifi, not the dark ..


If the sticks XMP profile set Rtt_Park to 1 it is most likely fine. However if you venture beyond 1.5v I believe the recommendation is to set this to a lower ohm, 1=240 ohms, 2=120 ohm ect...... Rtt's is always 240 so the number you see in Zen timings is the dividing value, 3 would then be 80 ohms

Not that it is recommended but I ran Rtt_Park 1 @1.55v on probably a similar PCB design as yours and it was fine for the couple of weeks I tested this. So don't stress out and think your sticks will explode anytime soon.


Broad setup profiles like XMP need to cater for a lot of different senarios, different mobo, cpu and other hardware related differances so these profiles are "tuned" to work within their specs(3800c14) at the "worst case" senarios
So most likely Rtt_Park(edit: Rtt_Park 1) is to cater for a bad senario in some sort, meaning that you could most likely find a lower ohm value that works better given that your mobo, imc and other components are working good


----------



## lmfodor

T[]RK said:


> But on you screenshot of ZenTimings RTT_Park is 1. =) Maybe you didn't touched it, but it's is there.
> 
> 
> Yes, my mistake. @PowerK got Dark Hero. iPhone 6s screen is too small for all this screenshots. %)
> 
> Same as @Imfodor, be careful with RTT_Park=1 and High vDIMM voltage.
> 
> CAD_BUS is diffirent on screenshots: 24-20-24-24 on Dark Hero, and 60-20-24-24 on Xtreme.
> 
> Here is another quote:


I swear I am learning by force. It happens that the subject is not so easy for newbies! so very grateful for the help!

Here I corrected the RTTPark. I left it at 3 like you suggested








And here the TestMem5 results. This test does not say anything about where the problem could be. Any suggestion? what could change? so far it is the one app that gives me errors











Sent from my iPhone using Tapatalk Pro


----------



## T[]RK

RosaPanteren said:


> I think the Rtt_Park = 1 / 240ohm was a PCB specific issue related to A0 PCB design
> 
> His PCB is probably B2 or smth exotic so it shouldn't matter, his XMP probably defaults to Rtt_Park = 1 @1.5v


Maybe, but it's better to point on it then press start button next day and PC did nothing. Especially for newbies.



RosaPanteren said:


> If the sticks XMP profile set Rtt_Park to 1 it is most likely fine.


Yes, if it's part of XMP = then it's manufacturer tested. It's provide warranty on that RAM.



lmfodor said:


> And here the TestMem5 results. This test does not say anything about where the problem could be. Any suggestion?


It's show same with RTT_PARK = 1? Errors was at the end of start of the test? 2 hours just too long to test again. =) I personally don't use anta777 config. I don't know error's legend for it (only from 1usmus_v3).

Check in you BIOS two things: RTT_Park=1 is part of XMP profile? Disable XMP and and find it's value and then enable it and find again.


----------



## lmfodor

RosaPanteren said:


> I think the Rtt_Park = 1 / 240ohm was a PCB specific issue related to A0 PCB design
> 
> His PCB is probably B2 or smth exotic so it shouldn't matter, his XMP probably defaults to Rtt_Park = 1 @1.5v
> 
> 
> 
> 
> If the sticks XMP profile set Rtt_Park to 1 it is most likely fine. However if you venture beyond 1.5v I believe the recommendation is to set this to a lower ohm, 1=240 ohms, 2=120 ohm ect...... Rtt's is always 240 so the number you see in Zen timings is the dividing value, 3 would then be 80 ohms
> 
> Not that it is recommended but I ran Rtt_Park 1 @1.55v on probably a similar PCB design as yours and it was fine for the couple of weeks I tested this. So don't stress out and think your sticks will explode anytime soon.
> 
> 
> Broad setup profiles like XMP need to cater for a lot of different senarios, different mobo, cpu and other hardware related differances so these profiles are "tuned" to work within their specs(3800c14) at the "worst case" senarios
> So most likely Rtt_Park is to cater for a bad senario in some sort, meaning that you could most likely find a lower ohm value that works better given that your mobo, imc and other components are working good


Ok, so leaving RTTPark to 3 would not affect, it es better to have a lower ohms.. right? I have to learn more about memory clocking... so far I have the errors with the TestMem5 .. I’m gonna run y -cruncher right now to see what happen


Sent from my iPhone using Tapatalk Pro


----------



## lmfodor

T[]RK said:


> Maybe, but it's better to point on it then press start button next day and PC did nothing. Especially for newbies.
> 
> Yes, if it's part of XMP = then it's manufacturer tested. It's provide warranty on that RAM.


I completely agree. better prevent. Thank you for your advice. Anything else about the errors I get in TM5?

Now I’m fine with the RTTPark? I also see a RTTwr that is on Auto and also shows RXW/4...

Sent from my iPhone using Tapatalk Pro


----------



## T[]RK

lmfodor said:


> Now I’m fine with the RTTPark?


Yes, untill you find information about RTT_Park=1 is part of XMP. If it is - return it back and run TM5 test again (maybe not 2 hours long) and see if there is still same errors (#14). If they disapear - it's proably because RTT_Park=3. It's just weird to see G.Skill Sumsung B-die with 1.5V vDIMM and RTT_PARK=1 included in XMP profile. But if G.Skill tested it, say it O.K. and provide warranty on it... O.K. then. =)



lmfodor said:


> I also see a RTTwr that is on Auto and also shows RXW/4...


Stick with XMP for now (don't change settings you don't know). =) Personally don't know what RXW/4... didn't saw it before. Maybe i just don't have it on my GIGABYTE.


----------



## lmfodor

Pictus said:


> VDDG CCD = 1.05v seems a bit too much, check
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> 
> *--------------------------------------------------------*
> 
> 
> 
> 
> 
> 
> 
> 
> Your CLDO VDDP is tooooooooooooooo high!  [emoji88]
> Set CLDO VDDP = 0.900
> Check AMD max overclocking voltage
> 
> 
> Memtest is no good, TM5 is good and I like Y-cruncher, press 1>8>14>0
> 
> 
> y-cruncher - A Multi-Threaded Pi Program
> 
> 
> and Prime95
> 
> 
> 
> 
> 
> GIMPS - Free Prime95 software downloads - PrimeNet
> 
> 
> GIMPS has free software available for Windows, Linux, FreeBSD, Mac OSX. Contribute to the effort by using your computer's spare processing power.
> 
> 
> 
> 
> www.mersenne.org


Well something is wrong I don’t know if it is related to memory OC or to PBO2.. could it be the value of core offset?








So are my timings now


----------



## PowerK

T[]RK said:


> CAD_BUS is diffirent on screenshots: 24-20-24-24 on Dark Hero, and 60-20-24-24 on Xtreme.


You're right. I forgot. 
On Dark Hero, 60-20-24-24 won't post.


----------



## PowerK

T[]RK said:


> Same as @lmfodor, be careful with RTT_Park=1 and High vDIMM voltage


Ah.. sorry. It was a typo. (This is what happens when you use smartphone too much.
It's 6-3-3, not 6-3-1.


----------



## ManniX-ITA

T[]RK said:


> Yes, untill you find information about RTT_Park=1 is part of XMP. If it is - return it back and run TM5 test again (maybe not 2 hours long) and see if there is still same errors (#14). If they disapear - it's proably because RTT_Park=3. It's just weird to see G.Skill Sumsung B-die with 1.5V vDIMM and RTT_PARK=1 included in XMP profile. But if G.Skill tested it, say it O.K. and provide warranty on it... O.K. then. =)


RTT 0/3/1 is standard for all DR B-die; I've run my kit for hours up to 1.9V with it and it's still working 

Indeed the warning about 240 Ohm is more related to the Viper A0 PCB.
As a general rule it's better to try to run with lower impendence but you can't just change one termination setting, not going to work.
You need to adjust the whole thing or it will flock errors.

What @Veii is recommending is to test 6/3/3 but you need to adjust the whole to make it work.
These are my settings now:










The 3-3-15 Setup timings is mandatory and also the DrvStr at 40-20-20-20 (or 60-20-20-20).
ProcODT also needs to be adjusted; for me on the Unify-X with 2 slots seems better 34 Ohm but as suggested by Veii could be too low for 32GB.
I would recommend to test between 37 and 43.
With these settings higher than 43 and lower than 34 starts erroring.
tCKE as well needs to be tested and finetuned; still testing but got better results with 1.
Many can make it work only with 6/9 or higher.


----------



## Nighthog

RTT_PARK = 1 (240Ohm)

Has caused me no issues on my X570 Xtreme or any other board I've run it as such.
7/3/1 -> 7/2/1 -> 6/3/1 are my standard best RZQ combinations I get most out of all the kits I've used on Gigabyte motherboards. (4x8GB)

I run 6/3/1 1.700V for more than a year now on my Micron Rev.E kit without any issues.

The specific RZQ values depend on the motherboard vendor, ASUS, MSI etc have other combinations that are better for their layouts/designs.
I've never heard of anyone having issues with RTT_PARK = RZQ/1 (240Ohm) on a Gigabyte board.


----------



## lmfodor

Well I found a page with a review of these new TridentZ 3800CL14 memories. I notice that the VDDP is also set very high as well as the RTTPark is set to 1.. and when I see his timings, I see that his OC is higher than mine, but he achieves lower temperatures. I'm running y-cruncher at 51 degrees, which is high. It makes me wonder whether to go back to the XMP profile without OC and use lower temperatures.

Does the new high-end RAM for Ryzen 5000 live up to its promise? - G.SKILL DDR4-3800 CL14 2x 16GB kit put through its paces | Page 3 | igor´sLAB

The good news is that the y-cruncher helped me to detect errors in the PBO curve. I had to raise the voltage of the CCD2 cores to -15 and so I no longer had errors. What Prime95, OOCT, Core Cycler did not detect is detected by the Y-Crumcher. I still have to see why I did not pass the TM5 test. It may be as it says in the note that it is because of the temperature, although at 45 it does not seem to me that the TM5 should fail.











Sent from my iPhone using Tapatalk Pro


----------



## RosaPanteren

lmfodor said:


> Hi, yesterday I received a new memories GSkill Tridenz Neo 3800CL14 which is the new series optimized for Raizen 5000 (I have a 5900x) that it supposed to have low latency. However with the XMP profile I didn’t see a good latency +60ns and a colleague from this forum help me to quick OC and the improvement was very good at least for me. The temps before the OC was 39/41 and after when playing I’m about 45 and in a memtech it reaches almost 52 degrees.
> 
> Configuration optimized
> 
> 
> 
> 
> 
> 
> 
> 
> Timings after the OC
> 
> 
> 
> 
> 
> 
> 
> 
> Before the OC, XMP profile
> 
> 
> 
> 
> 
> 
> 
> 
> 
> What do you think about the results?
> 
> I ran memtest86, memtest84.. I would try TM5.. anything else to try?
> 
> Thanks
> 
> 
> Sent from my iPhone using Tapatalk Pro


Congratz on the ram kit, that kit is crazy epxensive at least in my country

I'm new to AMD platform so I got a very limited experiance and knowledge about the peculiars of AMD ram OC, but I do have some experiance from ram oc from before and have been testing on this platform for a couple of months now.

If you are new to ram oc I would advise you to read up a bit and get some kind of general understanding of the different components and their characteristics, what oc'ing ram implies and the general risks, data corruption and that you more than likely will need to clear cmos during the process....idk if I misunderstood your base of knowledge and if so I apologize

To give you a bit of information to start out with your kit has Samsung B die's and are dual ranked per dimm so it would be preferable for you to look towards setups from similar kind of dimms, size and also manufacturer

I got a similar kind'ish kit(2x16GB, G.skill, dual rank, Sammies and I guess PCB design wouldn't differ that much), but less recent and expensive, that I'm in the process of tightening the timings and optimizing setup on for @3800c14 to the best of my abilities

This is how far I have gotten til now(do mind I push a "somewhat" high voltage)










the Aida "score"(should only be used as a light referance to perf. and if things are moving in the right direction) will also be affected by the cpu(dual or single CCD) and potential tweaking of this


----------



## zGunBLADEz

and its not the same cpu as well so latency and r/w/c are different including l's cache so its better to compare between the same cpu sku instead

this is a 5900x









this is a kit as old as it comes... i used this on my 1700/1800x/2700x/8700k so i know him from top to bottom XD
dialed up timings call it a day after a hci run that i posted a few pages back..

Didnt have the need to kill myself testing something that is literally capped bcuz of the infinity fabric.

Those are "proper timings" that perform as such without that "if" holding gate capping the ram performance..


----------



## nikpoth

Some idea for improvement whea error?


----------



## Veii

nikpoth said:


> View attachment 2483633
> 
> Some idea for improvement whea error?


You can give 34 ohm a shot 
If this set is stable
also test voltages:
CPU VDDP (Tweakers paradise VDDP) ~ 860
cLDO_VDDP 900mV
VDDG CDD 1030mV
VDDG IOD 1100
SOC 1230 (1215mV read out)

On your set you do hold the minimum 40mV seping mid OS
But during TM5 or y-cruncher, it will drop stronger 
Probably just a loadline problem , soo start with increasing SOC by +1
If it doesn't help - replicate what i gave you and the errors should be gone

If there is no Tweakers Paradise (ASUS) VDDP, then ignore it 
But i think you can google for TurboV
A lot of Asus 500 series boards have the "external" voltage controller
Soo TurboV should have access to more boards than just the crosshair or impact lineup


----------



## T884G63

@Veii 1230 SOC? Isn't that a bit much for 1900 fclk?

Or have you discovered something new?


----------



## RosaPanteren

lmfodor said:


> Ok, so leaving RTTPark to 3 would not affect, it es better to have a lower ohms.. right? I have to learn more about memory clocking... so far I have the errors with the TestMem5 .. I’m gonna run y -cruncher right now to see what happen
> 
> 
> Sent from my iPhone using Tapatalk Pro


Lol brother I feel kinda bad for you! It was quite a rough start you got there, with alarms going off from every angle 

For Rtt_Park it should be fine with value 1 = 240 Ohm for now, as several others have commented, as this is also what your mobo/xmp defaults too......down the road you might want to tweak this but for now it seems you got more pressing issues if you are not certaint that your PBO CO is stable


Where you able to run all Y-cruncher tests before starting to oc ram? Test 15, 16 and 19 are the quickest to pin point bad offsets(test 19 on negative offsets from 0 to -10, and 15&16 for -10 to -30 in my experience). Once you think your stable run all test, option 7

If you were able to run YC in consecutive loops for at least a couple of hours(I've had offsets fail after 3 hours) then it's the Rtt_Park change or some of the timings you made that is unstable


----------



## lmfodor

RosaPanteren said:


> Congratz on the ram kit, that kit is crazy epxensive at least in my country
> 
> To give you a bit of information to start out with your kit has Samsung B die's and are dual ranked per dimm so it would be preferable for you to look towards setups from similar kind of dimms, size and also manufacturer
> 
> I got a similar kind'ish kit(2x16GB, G.skill, dual rank, Sammies and I guess PCB design wouldn't differ that much), but less recent and expensive, that I'm in the process of tightening the timings and optimizing setup on for @3800c14 to the best of my abilities
> 
> This is how far I have gotten til now(do mind I push a "somewhat" high voltage)
> 
> View attachment 2483603
> 
> 
> the Aida "score"(should only be used as a light referance to perf. and if things are moving in the right direction) will also be affected by the cpu(dual or single CCD) and potential tweaking of this


Hi RosaPanteren, thanks for your help. 

I have to say that in my country this memory kit are very expensive. Indeed a payed +50% above the Amazon price. Around 750usd! What happened in my country is the the products that doesn’t have much rotation or are “exclusives” the importers do not bring them, they are the large distributors that feed the stocks of the local stores. But since we have a double exchange rate, that means that there are products that you buy here cheaper than in the US, at MSRP values and even lower. The last year in December before the price madness I was about to buy an EVGA 3090 FTW3 at 1600 usd. It was a unique opportunity and although you may not believe it, the one who made me give up was the official EVGA forum where they threw the card down for the amount of RMA and its BIOS for OC. Sorry for the offtopic but I couldn't stop telling this anectode!

Returning to my concern about inexperience about the concepts of OC, the only thing I could do is copy values from another that has already tried adjusting the timings as I see in that note that I shared here where the VDDP is at 1.09v which is typically discouraged by what I read and you told me here The truth I must say that whatever value you put on these memories, I have a post. In that sense you can see that they are very good 

My only concern beyond the TM5, since the y-crunch works perfect, is the temperatures. Only when I test I see that they go up to 50/51 degrees maximum. I do not know if this is acceptable, if it would generate errors, but we start from the basis that your XMP profile pulls a VDIMM voltage of 1.5v I expected that in games and other tasks did not exceed 45 degrees.. I don’t want to watercool the memories
Compare the timings of the review with the mine.. should I copy them and try? Would I have an increase in temps?
These are my timings now!








This would be an stable version.. but I think it has a more OC than mine








and this flat timings were TM5 failed..








Should I mimic those timings to try?


----------



## lmfodor

RosaPanteren said:


> Lol brother I feel kinda bad for you! It was quite a rough start you got there, with alarms going off from every angle
> 
> For Rtt_Park it should be fine with value 1 = 240 Ohm for now, as several others have commented, as this is also what your mobo/xmp defaults too......down the road you might want to tweak this but for now it seems you got more pressing issues if you are not certaint that your PBO CO is stable
> 
> 
> Where you able to run all Y-cruncher tests before starting to oc ram? Test 15, 16 and 19 are the quickest to pin point bad offsets(test 19 on negative offsets from 0 to -10, and 15&16 for -10 to -30 in my experience). Once you think your stable run all test, option 7
> 
> If you were able to run YC in consecutive loops for at least a couple of hours(I've had offsets fail after 3 hours) then it's the Rtt_Park change or some of the timings you made that is unstable


Hey! I just answered your yesterday advices. 

And yes! I have alarms everywhere and I go out as a firefighter to change parameters blindly. It is true, one thing in an undervoltage of a CPU and another is to know each value of memory OC well and how it relates to the others. I would love to know that if I only play a value low temps but not affect performance .. and so on. 

Regarding the y-cruncher I was pleasantly surprised. I was able to correct PBO curves and spend two hours of stress testing using only FTT .. now I am going to test what you suggest for 3 hours .. and well, I will be waiting to understand why the TM5 fails: it is not an app that says much why or where it fails

I let know you how it goes! Thanks 


Sent from my iPhone using Tapatalk Pro


----------



## RosaPanteren

zGunBLADEz said:


> and its not the same cpu as well so latency and r/w/c are different including l's cache so its better to compare between the same cpu sku instead
> 
> this is a 5900x
> View attachment 2483631
> 
> 
> this is a kit as old as it comes... i used this on my 1700/1800x/2700x/8700k so i know him from top to bottom XD
> dialed up timings call it a day after a hci run that i posted a few pages back..
> 
> Didnt have the need to kill myself testing something that is literally capped bcuz of the infinity fabric.
> 
> Those are "proper timings" that perform as such without that "if" holding gate capping the ram performance..


True 👍 i tried to explain that in a somewhat unstructred and less insightful way at the end 🙃 So good that you point that out

My intention was to share timings as Imfodor got kinda similar dimms; dual rank 2x16GB ect. and was looking too tighten up timings @3800c14

Now there is probably a better way to tighten up than the route I went and get a flat 14-14-14 @3800


----------



## nikpoth

Veii said:


> You can give 34 ohm a shot
> If this set is stable
> also test voltages:
> CPU VDDP (Tweakers paradise VDDP) ~ 860
> cLDO_VDDP 900mV
> VDDG CDD 1030mV
> VDDG IOD 1100
> SOC 1230 (1215mV read out)
> 
> On your set you do hold the minimum 40mV seping mid OS
> But during TM5 or y-cruncher, it will drop stronger
> Probably just a loadline problem , soo start with increasing SOC by +1
> If it doesn't help - replicate what i gave you and the errors should be gone
> 
> If there is no Tweakers Paradise (ASUS) VDDP, then ignore it
> But i think you can google for TurboV
> A lot of Asus 500 series boards have the "external" voltage controller
> Soo TurboV should have access to more boards than just the crosshair or impact lineup












This is the set I want to make stable.
After an hour y-cruncher, 1 error.
I do not know what else to try.
cldo vddp 0.900
vddg ccd 1.050
vddg iod 1.050
soc 1.1
dram v 1.42
considered excessive voltage??


----------



## Pictus

lmfodor said:


> Returning to my concern about inexperience about the concepts of OC, the only thing I could do is copy values from another that has already tried adjusting the timings as I see in that note that I shared here where the VDDP is at 1.09v which is typically discouraged by what I read and you told me here The truth I must say that whatever value you put on these memories, I have a post. In that sense you can see that they are very good


Check the Influence of СLDO_VDDP on MEMCLK "holes"


----------



## RosaPanteren

lmfodor said:


> Hi RosaPanteren, thanks for your help.
> 
> I have to say that in my country this memory kit are very expensive. Indeed a payed +50% above the Amazon price. Around 750usd! What happened in my country is the the products that doesn’t have much rotation or are “exclusives” the importers do not bring them, they are the large distributors that feed the stocks of the local stores. But since we have a double exchange rate, that means that there are products that you buy here cheaper than in the US, at MSRP values and even lower. The last year in December before the price madness I was about to buy an EVGA 3090 FTW3 at 1600 usd. It was a unique opportunity and although you may not believe it, the one who made me give up was the official EVGA forum where they threw the card down for the amount of RMA and its BIOS for OC. Sorry for the offtopic but I couldn't stop telling this anectode!
> 
> Returning to my concern about inexperience about the concepts of OC, the only thing I could do is copy values from another that has already tried adjusting the timings as I see in that note that I shared here where the VDDP is at 1.09v which is typically discouraged by what I read and you told me here The truth I must say that whatever value you put on these memories, I have a post. In that sense you can see that they are very good
> 
> My only concern beyond the TM5, since the y-crunch works perfect, is the temperatures. Only when I test I see that they go up to 50/51 degrees maximum. I do not know if this is acceptable, if it would generate errors, but we start from the basis that your XMP profile pulls a VDIMM voltage of 1.5v I expected that in games and other tasks did not exceed 45 degrees.. I don’t want to watercool the memories
> Compare the timings of the review with the mine.. should I copy them and try? Would I have an increase in temps?
> These are my timings now!
> 
> 
> 
> 
> 
> 
> 
> 
> This would be an stable version.. but I think it has a more OC than mine
> 
> 
> 
> 
> 
> 
> 
> 
> and this flat timings were TM5 failed..
> 
> 
> 
> 
> 
> 
> 
> 
> Should I mimic those timings to try?


Edit: get a fan to blow on your sticks

I think your better off asking some of the knowledgeable people in this forum....

On a general basis ram oc depends on more than your dimms, as important is the imc(every silicon is different) and the mobo

Find what ranges are mostly used for the parameters beneath with similar kits, and ofc what is deemed «safe»

Then I would start out with getting a sens of what vsoc, vddp, ccd and iod your dimms like (and not like) @1.5v, look at Veii’s last post for referance(and find older posts), and then the same for procODT, Rtt’s and DrvStr

Everyone need to find what their own components and setup like, but could look to others for clues. Discussions and experiance about these values and settings have been posted multiple times during the last 100 pages and you would also need to test for yourself.


----------



## Dekaohtoura

Good evening from Greece...I decided to celebrate our 200 years of independence (let's just leave it to that) trying to make a 5600X work on a X370 Asrock Taichi (for the fun of it).

It worked, but not until I took out one of my ram sticks...couldn't get past code 27 with both (2x8) on.

I'm far behind on my mem o/c, since right until 2h ago I was happy with my R1700 and a 3400/16 mem profile.

Are there any specific standards about cad strength, resistances etc that I should use as a baseline, in order to be able to use both of my sticks and start testing any o/c?

Thank you in advance.


----------



## lmfodor

RosaPanteren said:


> Edit: get a fan to blow on your sticks
> 
> I think your better off asking some of the knowledgeable people in this forum....
> 
> On a general basis ram oc depends on more than your dimms, as important is the imc(every silicon is different) and the mobo
> 
> Find what ranges are mostly used for the parameters beneath with similar kits, and ofc what is deemed «safe»
> 
> Then I would start out with getting a sens of what vsoc, vddp, ccd and iod your dimms like (and not like) @1.5v, look at Veii’s last post for referance(and find older posts), and then the same for procODT, Rtt’s and DrvStr
> 
> Everyone need to find what their own components and setup like, but could look to others for clues. Discussions and experiance about these values and settings have been posted multiple times during the last 100 pages and you would also need to test for yourself.


First of all thank you very much for your help. There are many concepts that I do not know and now I am beginning to read with the VDDP note and the memory holes. Really very good, that's why I left the value at 0.9 and I understand that the VDDGs (that there are two and I can't quite understand which one needs to be modified) should be 500mv below the SOC value. When you say to understand that it suits my DIMMS better, starting from the base that the rayzen Calc recommends 1.45 as maximum while the XMP profile of these memories is in 1.5 it makes me think that the app is outdated. That is why I prefer to have your suggestions to try with manual changes. I think the VSOC that in my timings at 1.08 (auto) is fine, close to 1.1v. Then the VDDP leave it at 0.9. I would like to try the two VDDGs that I see high. And finally when you mention procODT, which I don't know what it is, RTTs, that I leave the Park at 3, and DrvStr I don't know what it is. What could I modify? For now, a test would be to copy the values of the note. But I would like to work on my current timing and pass the TM5 tests, the rest are all passed by P95, OCCT, Memtesr86 and techpowerup.
this is the tester’s “safe” OC timings







These are my actual timings:







and this my TM5 errors







Then load the profile in Thipoon and with the Rayzen Calculator to see what it recommended that there are some differences on my values in comparison with the test on the review, but what surprises me is that it suggests a lower voltage, it may be that these apps have been outdated for certain types of memory? In fact Tiphoon cannot read the Trident model, he puts them as unknown








What could improve? Could I copy the values from the review? they seem tighter. In fact my only concern besides not passing the TM5 test is that while I run the test the temperature of the memories rises to 51 degrees.. they do not pass there, I am at the limit, right? I do not have a WHEA error or anything weird

Another think that I read in my mobo forums (Asus CH8 Wifi) is to disable Global C-states, set the PSU idle to Typical Current Idle, and just that. I read also about disabling Spread Spectrum. To change or not de LLC value, I leave it on Auto.. just a few question. I think they all are related! Thanks a lot for your help


----------



## hsn

gigabyte released bios beta agesa 1.2.0.1 patch A , and when I tried it it turned out that it worked on 1.46v
Next try to work with cl14


----------



## zGunBLADEz

lmfodor said:


> First of all thank you very much for your help. There are many concepts that I do not know and now I am beginning to read with the VDDP note and the memory holes. Really very good, that's why I left the value at 0.9 and I understand that the VDDGs (that there are two and I can't quite understand which one needs to be modified) should be 500mv below the SOC value. When you say to understand that it suits my DIMMS better, starting from the base that the rayzen Calc recommends 1.45 as maximum while the XMP profile of these memories is in 1.5 it makes me think that the app is outdated. That is why I prefer to have your suggestions to try with manual changes. I think the VSOC that in my timings at 1.08 (auto) is fine, close to 1.1v. Then the VDDP leave it at 0.9. I would like to try the two VDDGs that I see high. And finally when you mention procODT, which I don't know what it is, RTTs, that I leave the Park at 3, and DrvStr I don't know what it is. What could I modify? For now, a test would be to copy the values of the note. But I would like to work on my current timing and pass the TM5 tests, the rest are all passed by P95, OCCT, Memtesr86 and techpowerup.
> this is the tester’s “safe” OC timings
> 
> 
> 
> 
> 
> 
> 
> These are my actual timings:
> 
> 
> 
> 
> 
> 
> 
> and this my TM5 errors
> 
> 
> 
> 
> 
> 
> 
> Then load the profile in Thipoon and with the Rayzen Calculator to see what it recommended that there are some differences on my values in comparison with the test on the review, but what surprises me is that it suggests a lower voltage, it may be that these apps have been outdated for certain types of memory? In fact Tiphoon cannot read the Trident model, he puts them as unknown
> 
> 
> 
> 
> 
> 
> 
> 
> What could improve? Could I copy the values from the review? they seem tighter. In fact my only concern besides not passing the TM5 test is that while I run the test the temperature of the memories rises to 51 degrees.. they do not pass there, I am at the limit, right? I do not have a WHEA error or anything weird
> 
> Another think that I read in my mobo forums (Asus CH8 Wifi) is to disable Global C-states, set the PSU idle to Typical Current Idle, and just that. I read also about disabling Spread Spectrum. To change or not de LLC value, I leave it on Auto.. just a few question. I think they all are related! Thanks a lot for your help


put a fan on your sticks while stress testing if it have any leds turn them off.. thats up to 10c hotter with them on.. after that you can remove the fan.. you aint going to see them that hot ever again on a day to day basics..

stay away from prime95 and y cruncher (NOT REALISTIC LOADS) use hci or ramtest even gsat for ram tm5 anta extreme is cool as well but i prefer hci a long run .. use rog bench and blender benchmark or classroom test in a loop for stress testing. This are more realistic loads. p95 is just a power virus and theres no use to use it for stress testing specially in this cpus.


----------



## craxton

well, im back fellas. had possibly the BEST MFN WEEK of my 31 years of life that ive EVER HAD
in florida. MINUS miami bc it MFN BLOWS DONKEY SLONGS!!!!!

anyhow, before i left a week ago to go to keywest, cape coral, fort myers, and toledo/detroit. i changed 
from AUTO 200mhz oc (auto cpu core voltage as well) to what @Veii suggested, or mentioned with a .03xxmv offset positive 
(something like that) with curve settings, and use TM5 to test and see if one is getting all core/threads boosting to 4.85ghz, 
which my curve settings were ALL over the place honestly (otherwise it didnt boost the same)

ANYHOW, now that im back and have ran the pc for a while today with idk, less tabs than i normally have open, 
i just had a crash (14 tabs (4x8 sticks) so not using near enough ram. and i be hammed
if i go check the kernel WHEA logger inside EVENT VIEWER, and well, there is finally an actual error there with event ID 20. 
running sfc /scannow in CMD came back with nothing. 

Curious to know, if curve can cause crashes when its ran ALL DAY without issues and throw a random out of the blue error??????


----------



## lmfodor

zGunBLADEz said:


> put a fan on your sticks while stress testing if it have any leds turn them off.. thats up to 10c hotter with them on.. after that you can remove the fan.. you aint going to see them that hot ever again on a day to day basics..
> 
> stay away from prime95 and y cruncher (NOT REALISTIC LOADS) use hci or ramtest even gsat for ram tm5 anta extreme is cool as well but i prefer hci a long run .. use rog bench and blender benchmark or classroom test in a loop for stress testing. This are more realistic loads. p95 is just a power virus and theres no use to use it for stress testing specially in this cpus.


Ok! I have two Noctua fans behind the vertical GPU that push air to the top, so the airflow goes to the memory. What I’m doing right now is trying TM5 anta extreme and I set all the coolers at Max.. so the temps now don’t exceed 45 degrees. I didn't know about turning off the RGB. I’m going to download the software to try it

The y-cruncher helps me to fix the PBO curve. Really good tool. I will try HCI and gsat. I just read about them here in the forum but never tried. 

Today I played with my child a lot of games so.: in the real world.. it seems it’s running fine ( CP2077, FH4 and Need for speed Heat).. I think I’m close to find an stable configuration. I need to tweak some timings or voltages. 
Much appreciated for your response 


Sent from my iPhone using Tapatalk Pro


----------



## zGunBLADEz

lmfodor said:


> Ok! I have two Noctua fans behind the vertical GPU that push air to the top, so the airflow goes to the memory. What I’m doing right now is trying TM5 anta extreme and I set all the coolers at Max.. so the temps now don’t exceed 45 degrees. I didn't know about turning off the RGB. I’m going to download the software to try it
> 
> The y-cruncher helps me to fix the PBO curve. Really good tool. I will try HCI and gsat. I just read about them here in the forum but never tried.
> 
> Today I played with my child a lot of games so.: in the real world.. it seems it’s running fine ( CP2077, FH4 and Need for speed Heat).. I think I’m close to find an stable configuration. I need to tweak some timings or voltages.
> Much appreciated for your response
> 
> 
> Sent from my iPhone using Tapatalk Pro


problem with p95 and y cruncher used as stress tester is related to how they force/use the instructions sets. p95 will hammer your cpu and you end overvolting it to try stabilize it. same applies with y cruncher... day to day basics you dont do that type of workload... so you end overvolting your cpu and loosing mhz etc.... and your mind as well lol...

Most you use is sse instructions that dont require that much effort to run.. rog bench use programs like 7zip/x264 and blender to stress test your cpu simultaneously is closer to a day to day use basics... blender would be your hardest load common use on a day to day basics...


You bombarding the system with this power viruses for no reason...

I ditch p95 yrs and yrs ago... Now, i just use that and never encounter a bsod after i validated my overclocks.. Also, i try to test them as well with different ambients.. Only thing im a 100% thru is the ram overclock as this can corrupt your whole os in a unwanted crash... this i use hci for it in a long run to make them hot...
my last 2 runs were the vipers 4400 on my x299 over 70hrs and my team xtreem 3733 64gb kit as well 70+ hrs runs

if you need to run serious data/cientific data stuff i always recommend have a close to stock set baseline on the bios for that alone.. like a server/data center..


----------



## nikpoth

nikpoth said:


> View attachment 2483679
> 
> 
> This is the set I want to make stable.
> After an hour y-cruncher, 1 error.
> I do not know what else to try.
> cldo vddp 0.900
> vddg ccd 1.050
> vddg iod 1.050
> soc 1.1
> dram v 1.42
> considered excessive voltage??


It is stable whea free when I adjust pci gen 3.
Pci gen 4 = whea error.
Is there a logical explanation for this?


----------



## T[]RK

T[]RK said:


> Done. Zero errors.


It may look strange, that i quote myself, but it may be useful is case of backtracking results. Here is another TM5 test (25 cycles), but with some changes:










1. tCKE 1 => 6 (recommended for 3600 MHz);
2. GDM [email protected] => GDM [email protected];
3. CAD_BUS 40-20-24-24 => 60-20-40-20
4. CAD_BUS Timings 2-2-12 => 0-0-0 (was incorrect for CAD_BUS)

Later i want to try boot with same timings, but with GDM [email protected] and roll range of procODT (28.2-53.3) to collect errors. I did it already for another combintation, but i want to collect it on stable timings.


----------



## Blameless

nikpoth said:


> View attachment 2483679
> 
> 
> This is the set I want to make stable.
> After an hour y-cruncher, 1 error.
> I do not know what else to try.
> cldo vddp 0.900
> vddg ccd 1.050
> vddg iod 1.050
> soc 1.1
> dram v 1.42
> considered excessive voltage??


Bus/Interconnect errors often need more vDDG to resolve.



nikpoth said:


> It is stable whea free when I adjust pci gen 3.
> Pci gen 4 = whea error.
> Is there a logical explanation for this?
> View attachment 2483795


PCI-E 4.0 is more stressful on the SoC, but it's also possible the error just hasn't cropped up yet.


----------



## Nighthog

Any suggestions for this?

Not getting progress for a stable run on 4333/2166.

Errors 3,1,8 & 0.


----------



## nikpoth

Blameless said:


> Bus/Interconnect errors often need more vDDG to resolve.
> 
> 
> 
> PCI-E 4.0 is more stressful on the SoC, but it's also possible the error just hasn't cropped up yet.


This is exactly what happened. The error occurred later. In a new attempt: VDDG CCD Voltage Control 1.000 / VDDG IOD Voltage Control 1.150. Shows Stable without error but is it safe at these voltages?


----------



## PJVol

Veii said:


> up to your time


Some update and still nothing new (BIOS L1.92)  The same old s...load of 19-whea's:


----------



## T[]RK

T[]RK said:


> Later i want to try boot with same timings, but with GDM [email protected] and roll range of procODT (28.2-53.3) to collect errors.


O-o-oh, it was actually interesting and rewarding. Not a won war, but won small battle. I configured TM5 for 3 cycles total, so it will not take HUGE amount of time.

procODT - Error Number @ Cycle Number

28.2 - #1,11 @C1, #11 @C2 or C3 (don't wrote it)
30.0 - #11 @C1 (Only 1 Error)
32.0 - #1 @C1, #10 @C3
34.3 - #12 @C2, #0 @C3
36.9 - #11 @C1, #12 @C2
40.0 - #12,12 @C1, 0,12,6 @C3 (Worse Run, closed without finish)
43.6 - #2 @C2, #13 @C3
48.0 - ZERO ERRORS (That was actually surprise)









So, i may guess that i can now try to run procODT = 48 for longer (maybe 10 runs now) and wait for errors. So far it's best run.


----------



## Esticbo

Nighthog said:


> Any suggestions for this?
> 
> Not getting progress for a stable run on 4333/2166.
> 
> Errors 3,1,8 & 0.


You can try changing the value of tRP (26) with 28 and set tRFC to 750


----------



## Nighthog

Esticbo said:


> You can try changing the value of tRP (26) with 28 and set tRFC to 750


Tested it a while back but it was no good, the cause is not there.
I'm kinda pushing the limit on what the board wants to do in 4x8GB configuration but maybe the kit isn't just good enough for these speeds. 
I got it down to do only error 1 once (30min) in a while or a bluescreen but changing anything else just caused more trouble, like upping or lowering voltage. Took a pause as I have other things to consider with a secondary computer with a cheap B550MH Biostar board and my GPU upgrade in my main system (which I'm trying to push the limits on)

The 4650G gains performance for each increase on memory/flck speed why I want to push it to maximum, but seems I'm pushing the kit too far for it's comfort.


----------



## Blameless

nikpoth said:


> This is exactly what happened. The error occurred later. In a new attempt: VDDG CCD Voltage Control 1.000 / VDDG IOD Voltage Control 1.150. Shows Stable without error but is it safe at these voltages?


The ~1.2v SoC you need to actually run 1.150 VDDG IOD is pushing it.

Interconnect errors are often at least as dependent on VDDG CCD as IOD. So, unless you're sure you need 1.150 VDDG IOD, you could try reducing that and SoC voltage a long with it, while keeping VDDG CCD the same, or increasing it as necessary.

You could also check the details of the interconnect errors in the event log, which may give a better indication of where the issue actually is.


----------



## jomama22

Blameless said:


> The ~1.2v SoC you need to actually run 1.150 VDDG IOD is pushing it.
> 
> Interconnect errors are often at least as dependent on VDDG CCD as IOD. So, unless you're sure you need 1.150 VDDG IOD, you could try reducing that and SoC voltage a long with it, while keeping VDDG CCD the same, or increasing it as necessary.
> 
> You could also check the details of the interconnect errors in the event log, which may give a better indication of where the issue actually is.


Not sure what details can be extrapolated fr the bus/interconnect errors to help point in a direction. Any advice would help


----------



## PJVol

*@jomama22*
Not much, im afraid. In my asrock pc they follow one simple f..ng rule:
1900 - no matter what voltages, ohms, amperes, or whatever s..t you set in bios, NOTHING and rock solid.
1933 - slightly depending on above and moon phases as well, from sporadic to noticeable amount of whea
1966+ - no matter what, s..ttons of whea.

All that "increase vddg", "vddp is too high" and so on, is total bullshit. There's something seriously broken in the whole power/system management chain, and all that tinkering is useless until it fixed, or fclk would be hardcapped to healthy limits.


----------



## Blameless

jomama22 said:


> Not sure what details can be extrapolated fr the bus/interconnect errors to help point in a direction. Any advice would help


The source and processor APCI ID are potentially relevant.

In my limited experience, if you're always getting an error from the same processor ID, CCD is more likely to be the issue than IOD.

If the error source is a hard/uncorrected Machine Check Exception then you probably need to reduce FCLK, unless you have a lot of headroom or different firmware to try. Either your FCLK is too high for the samples involved, or your settings are so far from stability that basic assumptions need to be reconsidered.


----------



## jomama22

Blameless said:


> The source and processor APCI ID are potentially relevant.
> 
> In my limited experience, if you're always getting an error from the same processor ID, CCD is more likely to be the issue than IOD.
> 
> If the error source is a hard/uncorrected Machine Check Exception then you probably need to reduce FCLK, unless you have a lot of headroom or different firmware to try. Either your FCLK is too high for the samples involved, or your settings are so far from stability that basic assumptions need to be reconsidered.


Great thanks! Personally, I don't get any sort of bsod or hard crashes from the bus/interconnected wheas, they just happen while running anything above 1900 fclk. Always same ID of 0 for me. 

Thanks for the tips!


----------



## PJVol

jomama22 said:


> Always same ID of 0 for me.


Thats not APIC ID.


Blameless said:


> The source and processor APCI ID are potentially relevant.


There's no source and no useful info either from logged corrected bus/interconnect code 19.
Just curious, how your theory apply to the case, when the same CPU running fclk 2000, produces tons of whea's in one PC (asrock board), and not a single one in another (msi board). Both boards have the same base fw (psp, smu, abl)


----------



## MyComputerIsDying

Hey, noob here with dumb questions to ask..
I am using 16GB of samsung B die memory and overclocked it to [email protected]

1. How can I try and calculate the performance hit of going from 2 sticks to 4 sticks on this motherboard gigabye x570 aorus master (daisy chain topology right?)
2. Will I actually notice the performance hit or is it more a placebo and some gaming fps % loss
3. Is non B die memory with slower timings going to be perceivable in day to day usage? I love to tweak things and can usually notice inconsistencies in my system because of a constant workflow, I want to make sure everything I do isn't 1.5 seconds slower because of this. Price is really the issue... $250-300 for 32gb b die or half of that for other options.

Anything else I might need to consider when downgrading ram or increasing sticks? I could buy another set of my ram for probably about $120 and use 4 sticks b die but I believe I'll also lose my overclock, I'm using heavy voltage right now. I don't want to end up with 4 sticks of b die at low overclocks which ends up being negligible to other memory when 2 or 4 sticks

all help will be appreciated


----------



## Blameless

jomama22 said:


> Personally, I don't get any sort of bsod or hard crashes from the bus/interconnected wheas, they just happen while running anything above 1900 fclk. Always same ID of 0 for me.


What CPU and board is this, and what SoC and VDDG voltages are you running?



PJVol said:


> There's no source and no useful info either from logged corrected bus/interconnect code 19.


The corrected errors have no source, but uncorrected ones usually come with a more critical error that does have a source, usually machine check exception.

The CPU that reports either corrected or uncorrected errors can vary as well. In my experience, if it's always the same core, especially on dual CCD parts, raising VDDG CCD can often resolve correctable errors.

The general recommendation for high FCLKs on Zen 2/3 parts usually feature much higher VDDG IOD than CCD, because this what can get high FCLKs to POST. However, when all is said and done, I usually wind up with bopth VDDGs around the same voltage because of intermittent correctable bus//interconnect errors at lower VDDG CCD.



PJVol said:


> Just curious, how your theory apply to the case, when the same CPU running fclk 2000, produces tons of whea's in one PC (asrock board), and not a single one in another (msi board). Both boards have the same base fw (psp, smu, abl)


The theory in question is that the type of error and the processor ID reporting it might hint at whether a given FCLK can be made stable and if so, whether focusing on the CCDs or IOD is likely to be more beneficial. I haven't made any claims to the effect that all errors are solvable, that all settings apply equally to all boards, nor that all boards are equal when it comes to FCLK capability.

Different boards, or even different samples of the same board model, can have different power delivery/reporting. 2000 FCLK may need different settings (more voltage, different VRM switching frequency, different LLC settings, etc), or may be flatly impossible, on the less advantageous board.

Also, even with the same AGESA version, the firmware is not going to be identical between different boards/brands. Microcode can still vary and OEMs still have a lot of control over relevant aspects of firmware.


----------



## Dekaohtoura

Dekaohtoura said:


> Good evening from Greece...I decided to celebrate our 200 years of independence (let's just leave it to that) trying to make a 5600X work on a X370 Asrock Taichi (for the fun of it).
> 
> It worked, but not until I took out one of my ram sticks...couldn't get past code 27 with both (2x8) on.
> 
> I'm far behind on my mem o/c, since right until 2h ago I was happy with my R1700 and a 3400/16 mem profile.
> 
> Are there any specific standards about cad strength, resistances etc that I should use as a baseline, in order to be able to use both of my sticks and start testing any o/c?
> 
> Thank you in advance.


Bump...

I managed to get the same settings I used with the R1700 to work, but can't get any higher.










(on the left R1700, on the right 5600X. The added 0.02V are for stability during trials, now I'm on 1.41)

Tried with ProcODT 48, but it was unstable (restart on AIDA mem bench), tried 3466 with 53, same behavior.

Your input, please.

TY.


----------



## scosey

ManniX-ITA said:


> RTT 0/3/1 is standard for all DR B-die; I've run my kit for hours up to 1.9V with it and it's still working
> 
> Indeed the warning about 240 Ohm is more related to the Viper A0 PCB.
> As a general rule it's better to try to run with lower impendence but you can't just change one termination setting, not going to work.
> You need to adjust the whole thing or it will flock errors.
> 
> What @Veii is recommending is to test 6/3/3 but you need to adjust the whole to make it work.
> These are my settings now:
> 
> View attachment 2483593
> 
> 
> The 3-3-15 Setup timings is mandatory and also the DrvStr at 40-20-20-20 (or 60-20-20-20).
> ProcODT also needs to be adjusted; for me on the Unify-X with 2 slots seems better 34 Ohm but as suggested by Veii could be too low for 32GB.
> I would recommend to test between 37 and 43.
> With these settings higher than 43 and lower than 34 starts erroring.
> tCKE as well needs to be tested and finetuned; still testing but got better results with 1.
> Many can make it work only with 6/9 or higher.


Hi

I'm new around here and after days of trial and error of testing I decided to try your settings.
I've copied every single entry except voltages and what can I say, it's running stable since hours so far 

One thing I don't understand, I do get a slightly lower latency with GDM off and 2T (53.1ns) but GDM on/1T results in a slightly higher bandwith by a few 100mb across the board and it's reproducable.

I've also noted that the 5800X IOD uses about 10W less under full load (14W) compared to my 5950x (24W) applying the same voltages. (VSOC 1.1, VDDG IOD 1.05, VDDG CCD 0.95, CLDO VDDP 0.9V). I guess the 2nd CCD makes quite a difference.

On top of that my 5800X requires much less voltage so the difference is even bigger with only 12W.


----------



## Nighthog

EDIT: Nevermind... was wrong.


----------



## ManniX-ITA

scosey said:


> One thing I don't understand, I do get a slightly lower latency with GDM off and 2T (53.1ns) but GDM on/1T results in a slightly higher bandwith by a few 100mb across the board and it's reproducable.


That probably means there's something that can be improved in the profile.
GDM is auto-correcting; unless it's a correction that is sacrificing latency for bandwidth.
I get 53.2 ns with the profile below, slightly modified since then, with 1 CCD 5950x.
You are running fine then.

I'm testing RCPage in the spare time.
So far seems setting 252T same as tRFC is improving considerably the latency stability test with AIDA.


----------



## Evil Penguin

Hi all, I'm trying to up frequency to 3400 MHz from 3200 MHz and I'm having a rough time getting stable.
So far I've set the SOC voltage to 1.1v and memory voltage to 1.42v (everything else is stock).
Anything stand out that I should be changing?
Thanks for your input!


----------



## T[]RK

T[]RK said:


> 48.0 - ZERO ERRORS (That was actually surprise)


It was actually a bug (TM5 toy with me!). Next day i run same test, but with 10 Cycles and got errors: #11 @C1, #15,12 @C2. After that i decided to test another good option - procODT 30, since there was only 1 error before. At 10 cycles was error #5 @C6. Did few attemts to stabilize it: tWRRD 1 => 4, but failed - #12, 2, 10 @C2. Second attempt also was unsuccesful: tRDWR 8 => 10 give me #4,4 @C1.

At this point i returned to @Veii suggestion (G.Skill screenshot) and tested it again - there was same error #1 @C1 and #3 @C3. Did attempt to stabilize it with tWTRS 4 => 5 and tWTRL 12 => 14. Fix was actually suggested to Error #3 in list. Surprisingly (AGAIN!) it was stable @C10. Tested with Fan on RAM. 









I don't know for sure it's "legit" or TM5 toy with me again. Changes with my screenshot was big:

1. tRRDS 4 => 5
2. tRRDL 6 => 7
3. tFAW 16 => 20
4. tWTRS 4 => 5
5. tWTRL 12 => 14
6. tRTP 6 => 9
7. tWRRD 1 => 4
8. tRDRDSD 4 => 5
9. tRDRDDD 4 => 5
10. tWRWRSD 6 => 7
11. tWRWRDD 6 => 7
12. procODT 34.3 => 32

Later i will try to run maybe 25 cycles, but want to test again 10 cycles, but without fan on ram.


----------



## ManniX-ITA

Evil Penguin said:


> So far I've set the SOC voltage to 1.1v and memory voltage to 1.42v (everything else is stock).
> Anything stand out that I should be changing?


With VDDG at 1050mV and SOC at 1100mV you could have stability issues.
Either lower VDDG to 1000 or raise VSOC at least to 1120mV.

You have a B-die kit so I'd recommend to start from some tested timings here unless you really want to run at 3400 MHz:









Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com


----------



## mongoled

Veii said:


> Do NOT run RTT_PARK at /1 on them and don't exceed 1.48v without significant lowering of RTTs
> I don't want to see another dead A0 set here 😪


Thank you for getting this information out there!

Ive gone and looked to see what RttPark values were set when I was running the A2/A0 combinations and yup, with both A0 set's it was set at RZQ/1 (240 ohms) and running 1.53v in BIOS which was 1.55v in Windows.

At least now we know and such warnings can be made clear to peeps who are participating on this journey when using A0 Viper PCBs (are other A0s effected ??)



On a side note a little disappointed with some of the 'bickering' that has gone down the last few pages.

All I would like to say on this matter is that there are a number of people who have posted here who have dedicated oh so many hours in tweaking their memory while sharing their results.

Not acknowledging this fact however "incorrect" this information may be is at best ignorant.

I found the manner of the "attacks" incredulous and the arrogance in the way the posts were put across (those who came to criticize).

I can only guess that was not their intention as it made no sense (the manner of the posting).....


----------



## jomama22

Blameless said:


> What CPU and board is this, and what SoC and VDDG voltages are you running?
> 
> 
> 
> The corrected errors have no source, but uncorrected ones usually come with a more critical error that does have a source, usually machine check exception.
> 
> The CPU that reports either corrected or uncorrected errors can vary as well. In my experience, if it's always the same core, especially on dual CCD parts, raising VDDG CCD can often resolve correctable errors.
> 
> The general recommendation for high FCLKs on Zen 2/3 parts usually feature much higher VDDG IOD than CCD, because this what can get high FCLKs to POST. However, when all is said and done, I usually wind up with bopth VDDGs around the same voltage because of intermittent correctable bus//interconnect errors at lower VDDG CCD.
> 
> 
> 
> The theory in question is that the type of error and the processor ID reporting it might hint at whether a given FCLK can be made stable and if so, whether focusing on the CCDs or IOD is likely to be more beneficial. I haven't made any claims to the effect that all errors are solvable, that all settings apply equally to all boards, nor that all boards are equal when it comes to FCLK capability.
> 
> Different boards, or even different samples of the same board model, can have different power delivery/reporting. 2000 FCLK may need different settings (more voltage, different VRM switching frequency, different LLC settings, etc), or may be flatly impossible, on the less advantageous board.
> 
> Also, even with the same AGESA version, the firmware is not going to be identical between different boards/brands. Microcode can still vary and OEMs still have a lot of control over relevant aspects of firmware.


This is with the asus Dark Hero. All errors are correctable so it's hard to find any real source for the issue. I'm probably going to just start disabling features, pcie speed, etc just to see what exactly may be causing the issue. I may end up rma'ing the board anyhow as it doesn't handle c states properly and does the ol' '00' hard lock at idle while the msi ace I have doesn't suffer from the same issue. CPU ccd's also run about 2-3C warmer at exact clocks/voltages/load when compared to the MSI ace I have, which is strange as well.

For 1900/3800 SOC is 1.056(after droop), cldo vddp is 1.0v with vddg's at 1.0v as well. This voltage spread gives me the best results/most stable latencies in benchmarking and games I have noticed. 0 stability issues what so ever with these.

I'm using bios 3003 which I think is 1.2.0.0 agesa version.


----------



## Yviena

@Veii how do I actually get modified bios for x570 tomahawk to apply I set all main folders/sub folders to USER, and CPU VDDP to user but it still doesn't show up after flashing.


----------



## Blameless

jomama22 said:


> For 1900/3800 SOC is 1.056(after droop), cldo vddp is 1.0v with vddg's at 1.0v as well. This voltage spread gives me the best results/most stable latencies in benchmarking and games I have noticed. 0 stability issues what so ever with these.


Eliminating those last few errors can eat up a fair bit of voltage, but you still have a lot of headroom. Might be worth trying 1.1v SoC and 1.05v on both VDDGs, if it doesn't harm performance.

I have a 3900X in an ASRock B550 ITX that was getting one correctable error every 3-5 hours of load at 1v VDDG CCD, one every _sixty_ hours at 1.05v, and none in a straight week of 24/7 randomx hashing at 1.075v...which is just about my limit (with 1.125v SoC) before running into intermittent PCI-E 4.0 issues.


----------



## craxton

kind of off topic, but i was recently (last night) trying to jailbreak an iphone to bypass icloud lockdown
and it would get stuck mid ways and just set there and do nothing, turns out after searching for a few minutes
its due to AM4 not liking checkra1n software or the software not liking checkra1n (prob due to the usb cutout issues)

first time ive had anything happen with usb disconnecting period. has anyone got hold of the new bios agesa release yet?
and does it solve the USB drop issues?


----------



## zGunBLADEz

craxton said:


> kind of off topic, but i was recently (last night) trying to jailbreak an iphone to bypass icloud lockdown
> and it would get stuck mid ways and just set there and do nothing, turns out after searching for a few minutes
> its due to AM4 not liking checkra1n software or the software not liking checkra1n (prob due to the usb cutout issues)
> 
> first time ive had anything happen with usb disconnecting period. has anyone got hold of the new bios agesa release yet?
> and does it solve the USB drop issues?


i discover if you put an android phone on it and just let it charge and do heavy runs like cb the usb will drop in&out like crazy


----------



## Trusconi85

Evil Penguin said:


> Hi all, I'm trying to up frequency to 3400 MHz from 3200 MHz and I'm having a rough time getting stable.
> So far I've set the SOC voltage to 1.1v and memory voltage to 1.42v (everything else is stock).
> Anything stand out that I should be changing?
> Thanks for your input!
> 
> View attachment 2484040


If you stay on bios 1805 you can try this settings. If you go to 2003 or 2006 they does not work...


----------



## Veii

Yviena said:


> @Veii how do I actually get modified bios for x570 tomahawk to apply I set all main folders/sub folders to USER, and CPU VDDP to user but it still doesn't show up after flashing.


The main user control is on another level and AMIBCP only changes the flags for these menu's
What is used for full modification is AMITSE
AMITSE controls the order of the menu's, controls which HEX represents a menu
And "options = fields" (you can name the menu's however you want)
are another set of HEX, which are listed in the "BIOS Strings" section of the bios

Technically it's a lot of work (to get the Tokens Address correct),
but you could just copy paste the strings and features from another board into yours (if you miss something)
Just need to be sure, the adress of the remain parts is correct. And they will differ ~ because the structural order is different


Spoiler














Here a little orientation point EZbook 3 Pro - How to unlock the BIOS - TechTablets
But the more technical resources are on win-raid & mydigitallife , forum



T[]RK said:


> At this point i returned to @Veii suggestion (G.Skill screenshot) and tested it again - there was same error #1 @C1 and #3 @C3. Did attempt to stabilize it with tWTRS 4 => 5 and tWTRL 12 => 14. Fix was actually suggested to Error #3 in list. Surprisingly (AGAIN!) it was stable @C10. Tested with Fan on RAM.


was it tCKE that end up helping you run 706 or was it ClkDrvStr 60 ~ oor overall more VDIMM ?
Maybe less procODT ?!?

I get a lot of complains that my samples are not replicable on different board layouts - while RTT only is for the memory.
CAD_BUS and procODT , (procODT then with other voltages around it) ~ strongly depend on the board and "voltage baseline" you use 

You can give latter 636 and 536 a shot , it's a bit better than 706 + gives you more playroom in the 1.6v region
But also harder to set up and likely will need CAD_BUS Setup timings
(you can try after you have a stable set to fallback to) 

========================
Something else i think quite critical
I've recommended C-States and DF_States together
I don't think you need *DF_States* at all to have sleepy cores
Auto values are random between bioses, but for everyone beyond AGESA 1.1.0.0 D (or 1.2.0.0 and higher) , disable DF-States
Overboost will cause random reboots and issues
This bug is well abusable , but the tradeofff for stability is too big ~ soo *disable* it till you know it won't cause you random reboots or other funny idle to load issues :.)

Oh and little update
Been busy recently with supporting another ryzen project and working on random boost inconsistencies on ryzen. Overall working with ryzen, but a bit less on memoryOC


Spoiler: Sneak Peek




















CPPC aware, but still overriding CPPC table


----------



## T[]RK

Veii said:


> was it tCKE that end up helping you run 706 or was it ClkDrvStr 60 ~ oor overall more VDIMM ?
> Maybe less procODT ?!?


I didn't touched vDIMM at all, always was default for my kit (1.35V). tCKE i set for frequency (also default 3600 MHz) and didn't changed it. I indeed didn't tested it separately from each other, but ClkDrvStr 40 was absolute minimum to boot in Windows. Anything lower - POST O.K., Windows - No. So, that's why i use 60. I may try 40, but 40-20-40-20 look... unbalanced for me. I got notes, that 40-20-20-20 worked, but if it add CAD_BUS Timings (2-2-12) - windows will freeze, so i may test it without them.

It's unstable anyway even when test show it's pass and no errors:

Error #1 @C6 (0 changes made)

Error #4,0 @C3 = PSOD (0 changes, No Fan)

Error #15 @C25 (vDIMM 1.36v)








(such a joke, right when test end)

Error #3 @C1 (vDIMM 1.37v) Right after previous test.

Error # N\A (Reboot during test, changed tRDWR 8 => 9, tWRRD 4 => 5)

Don't get me wrong, i ain't mad. I understand that memory (DRAM) one of most complicated thing in PC. It work with tiny voltages, timings and cycles. Also, no such problems at 2T, it's only on 1T. It's look that there is only one configuration which work, but i didn't founded it yet.



Veii said:


> You can give latter 636 and 536 a shot , it's a bit better than 706 + gives you more playroom in the 1.6v region


Yeah, i think i try diffirent RTTs. My board have got maximum 1.5V (weak, cheap GIGABYTE for $70).


----------



## Veii

T[]RK said:


> Yeah, i think i try diffirent RTTs. My board have got maximum 1.5V (weak, cheap GIGABYTE for $70).


About the errors, i'll answer once i know 100% fixes 
Error 15 is a funny one, but that's why you test with many cycles haha 
tRFC mini keeps getting updated with error descriptions, once new reasons are figured out
well and gets consistently broken by trolls. . .

Look around for the user Kai, on Win-Raid 
He starts to do bios mods for many boards , and should fix that useless 1.5v lock


----------



## T[]RK

Veii said:


> About the errors, i'll answer once i know 100% fixes


And with so many variables it's difficult.  Understandable. I just share my experience with RAM made by Team Group. 



Veii said:


> tRFC mini keeps getting updated with error descriptions, once new reasons are figured out


It's actually nice. And it's help.



Veii said:


> well and gets consistently broken by trolls. . .


Can you lock it for edit only by youself? Or maybe separate Mini Calculator from Errors list if there is no separation of rights for edit.



Veii said:


> He starts to do bios mods for many boards , and should fix that useless 1.5v lock


Nah, it's fine. I better keep it with default BIOS. I will sold it anyway when unbox Dark Hero (i just don't want head ache with Windows re-activation when change motherboard and mSATA SSD on M.2 SSD).


----------



## nada324

@Veii hey do you remember ProcODT values and Cad bus for Summer ridge?, I just want to try my old 1700x just for jiggles.


----------



## craxton

zGunBLADEz said:


> i discover if you put an android phone on it and just let it charge and do heavy runs like cb the usb will drop in&out like crazy


well, i haven't really had issues out of using android the pc my MI 11 runs just fine....

i really just hope its solved honestly. cant afford bricking devices...


----------



## Veii

nada324 said:


> @Veii hey do you remember ProcODT values and Cad bus for Summer ridge?, I just want to try my old 1700x just for jiggles.


24-20-20-24 on the newer bioses
procODT was 48-53
60 was bad
some people could run 48 on micron kits
but 53.3 it was
check my signature


----------



## craxton

@Veii anything look "off" with this 2x8 config? this was my daily stable runner for months 
before swapping to the 4x8 2t set. (vdimm was way to high as 1.46 llc3 is all thats needed)

just looking for something to give others in other places something to go by.


----------



## nada324

Veii said:


> 24-20-20-24 on the newer bioses
> procODT was 48-53
> 60 was bad
> some people could run 48 on micron kits
> but 53.3 it was
> check my signature


Btw, can i use same RTTs as vermer? 636/706?


----------



## Trusconi85

Upgrade bios from 1805 to 2003 and later to 2006B on my B550F Strix and now i am not able to run old 4000 c16 with 2000 FCLK setup...any suggestion?

I try with 1.46v but it won't boot, now i am running everything stock with XMP profile on all 4 stick of 8 gb

Thanks in advance


----------



## Tobiman

ManniX-ITA said:


> RTT 0/3/1 is standard for all DR B-die; I've run my kit for hours up to 1.9V with it and it's still working
> 
> Indeed the warning about 240 Ohm is more related to the Viper A0 PCB.
> As a general rule it's better to try to run with lower impendence but you can't just change one termination setting, not going to work.
> You need to adjust the whole thing or it will flock errors.
> 
> What @Veii is recommending is to test 6/3/3 but you need to adjust the whole to make it work.
> These are my settings now:
> 
> View attachment 2483593
> 
> 
> The 3-3-15 Setup timings is mandatory and also the DrvStr at 40-20-20-20 (or 60-20-20-20).
> ProcODT also needs to be adjusted; for me on the Unify-X with 2 slots seems better 34 Ohm but as suggested by Veii could be too low for 32GB.
> I would recommend to test between 37 and 43.
> With these settings higher than 43 and lower than 34 starts erroring.
> tCKE as well needs to be tested and finetuned; still testing but got better results with 1.
> Many can make it work only with 6/9 or higher.


Is this TM5/memtest error free?


----------



## kompira

nada324 said:


> @Veii hey do you remember ProcODT values and Cad bus for Summer ridge?, I just want to try my old 1700x just for jiggles.


As @Veii said ProcODT is 48 or 53.3. CAD BUS 24-20-20-24, just adjust ClkDrvStr according to your ProcODT in GDM OFF mode.



nada324 said:


> Btw, can i use same RTTs as vermer? 636/706?


Yes, all these Rtts can work with all Zen generations: 705/706 or 636/536 (for 2x8GB SR). They matter to memory.
For example, this is my 3533MT/s set with Zen1, 2x8GB B-die A2's and 2 DIMM B450 board:
ProcODT 48, CAD BUS 40-20-20-24, cad bus setup 1-1-0, Rtt 636


----------



## ManniX-ITA

Tobiman said:


> Is this TM5/memtest error free?


Yes, I'm using these settings now but I haven't tested yet:










Damn MSI still hasn't fixed profile management...


----------



## jcpq

Hello
For a patriot viper ([email protected]) in [email protected], what is the best configuration for ProcODT, CAD BUS, cad bus setup and RTT?
This for 3800Mhz @ 14-14-14-28-42?


----------



## TexasAVI03

Can someone confirm they see the critical error KERNEL-Power ID 41 (63) BEFORE (10-20s prior) to WHEA ID 18? TIA

[I have been going through a lot of scenarios found on the AMD.com discussion board & I am curious if folks have that error 1st in this crowd. Most are not aware of the decade plus this error (Kernel-Power) has plagued AMD+Windows. This scenario appeared to be isolated primarily to laptops when on battery, but that is not case anymore.]

I have my 64GB (4x 16GB, Single) Corsair B-Die at 1.45v on my ASUS B550-E running 1800/3600 Auto detected timings.


----------



## zGunBLADEz

TexasAVI03 said:


> Can someone confirm they see the critical error KERNEL-Power ID 41 (63) BEFORE (10-20s prior) to WHEA ID 18? TIA
> 
> [I have been going through a lot of scenarios found on the AMD.com discussion board & I am curious if folks have that error 1st in this crowd. Most are not aware of the decade plus this error (Kernel-Power) has plagued AMD+Windows. This scenario appeared to be isolated primarily to laptops when on battery, but that is not case anymore.]
> 
> I have my 64GB (4x 16GB, Single) Corsair B-Die at 1.45v on my ASUS B550-E running 1800/3600 Auto detected timings.


have a plethora of them lol


----------



## jomama22

TexasAVI03 said:


> Can someone confirm they see the critical error KERNEL-Power ID 41 (63) BEFORE (10-20s prior) to WHEA ID 18? TIA
> 
> [I have been going through a lot of scenarios found on the AMD.com discussion board & I am curious if folks have that error 1st in this crowd. Most are not aware of the decade plus this error (Kernel-Power) has plagued AMD+Windows. This scenario appeared to be isolated primarily to laptops when on battery, but that is not case anymore.]
> 
> I have my 64GB (4x 16GB, Single) Corsair B-Die at 1.45v on my ASUS B550-E running 1800/3600 Auto detected timings.





zGunBLADEz said:


> have a plethora of them lol
> View attachment 2484307


Core voltage. Whea 18's will indicate the core that crashed with the ID#. (0,1 is core 0, 2,3 is 1, etc.). I'm assuming the whea 18's are a machine check with a cache hierarchy being the cause? Not a memory issue most likely.


----------



## zGunBLADEz

i get 0 wheas tho.... only have 1 whea in the whole event viewer and that one i did on purpose looking for the issue i have as we speak not so long ago


----------



## GribblyStick

TexasAVI03 said:


> Can someone confirm they see the critical error KERNEL-Power ID 41 (63) BEFORE (10-20s prior) to WHEA ID 18? TIA
> 
> [I have been going through a lot of scenarios found on the AMD.com discussion board & I am curious if folks have that error 1st in this crowd. Most are not aware of the decade plus this error (Kernel-Power) has plagued AMD+Windows. This scenario appeared to be isolated primarily to laptops when on battery, but that is not case anymore.]
> 
> I have my 64GB (4x 16GB, Single) Corsair B-Die at 1.45v on my ASUS B550-E running 1800/3600 Auto detected timings.


I have the error but not with WHEAs and when I tested settings that threw WHEA errors, the timing was not related at all.
Haven't had any for a few days now so I assume it's related to restarting over and over when testing a new setup.


----------



## jomama22

TexasAVI03 said:


> Can someone confirm they see the critical error KERNEL-Power ID 41 (63) BEFORE (10-20s prior) to WHEA ID 18? TIA
> 
> [I have been going through a lot of scenarios found on the AMD.com discussion board & I am curious if folks have that error 1st in this crowd. Most are not aware of the decade plus this error (Kernel-Power) has plagued AMD+Windows. This scenario appeared to be isolated primarily to laptops when on battery, but that is not case anymore.]
> 
> I have my 64GB (4x 16GB, Single) Corsair B-Die at 1.45v on my ASUS B550-E running 1800/3600 Auto detected timings.


I should add: try disabling global c-states and see how it goes.


----------



## TexasAVI03

zGunBLADEz said:


> have a plethora of them lol
> View attachment 2484307


Thank you. Well that answers that. I think this is our major issue. From AMD.com folks getting processors RMA'd (screaming never had the issue with my Intel...) to this group with memory clock issues to the graphics card forum guys complaining about new cards & relating it to HWiNFO64 & AIDA64 being the cause to the Windows forum guys blaming 20H2 recent update.

On my ASUS mobo I have done this:
If you "Disable" DRAM Power Options under AiTweaker>DRAM Timing Control>Power Down Enable
Also located in Advance>AMD OC'ing>AMD OC'ing>DDR & Infinity Fabric Frequency/Timings>DDR Frequency & Timings>DRAM Controller Configuration>DRAM Power Options: "Disable"

IMO this has helped. However, I have changed several other board voltage tweaks, to ensure at idle & core sleep the voltage doesn't error too low then sudden boost spikes do not trigger the Kernel-Power event. I have logged these for 2 months since building this new PC and compared to my ASUS mobo + 3900X with similar Corsair Memory.

Also, as stated previously, Windows in Power Mode Performance with all power-saving items off.

If you research that error it will take you way back over the last 10-15 years. It is a terrible rabbit hole of *** that the industry just let go for all these years...why?


----------



## TexasAVI03

GribblyStick said:


> I have the error but not with WHEAs and when I tested settings that threw WHEA errors, the timing was not related at all.
> Haven't had any for a few days now so I assume it's related to restarting over and over when testing a new setup.


Ok, thanks for the feedback


----------



## TexasAVI03

jomama22 said:


> I should add: try disabling global c-states and see how it goes.


Agree, C-State set to "Disable"

Also "Power Supply Idle Control" set to "Typical Current Idle"


----------



## TexasAVI03

zGunBLADEz said:


> i get 0 wheas tho.... only have 1 whea in the whole event viewer and that one i did on purpose looking for the issue i have as we speak not so long ago
> View attachment 2484315


Do you have any "Critical" errors in that log?


----------



## bloodyember

I just finished my first memory OC. I have a 16gb kit of Viper steel 4400cl19(B550 Tomahawk + 5600x). 
I did a anta777 extreme memtest and passed 3 cycles without errors. I plan to do another mem test over the night today with HCI to be sure it's okay. 

I was wondering if one of you could take a look at my numbers and tell me if the settings are passable for long term usage or if there are any problems in it. I had problems with instability until I adjusted my ProcODT and ClkDrv. 

I would be very grateful for any info.


----------



## TexasAVI03

Food For Thought - Shared On Reddit (I do not condone or support anything posted at the link below. Just simply sharing another's opinion and their research to help the group.)









MemTestHelper/DDR4 OC Guide.md at master · integralfx/MemTestHelper


C# WPF to automate HCI MemTest. Contribute to integralfx/MemTestHelper development by creating an account on GitHub.




github.com


----------



## PJVol

bloodyember said:


> I was wondering if one of you could take a look at my numbers and tell me if the settings are passable for long term usage or if there are any problems in it. I had problems with instability until I adjusted my ProcODT and ClkDrv


WRRD 1, ProcODT 32-37 depending on fclk, and with IF1900, everything that follows in ZenTimings screen can be left at Auto.
You may try mine, they are tm5 stable and 24/7 for about a month. Keep in mind, your ram chips are better binned (Vdimm 1.45V)

PS: and I woudnt expect good results on 5600X with static OC.


----------



## TimeDrapery

Here's the results for my latest set, with GDM set to "Enabled"...









Anyone have any good ideas for me at this point?

I've yet to work tRFC down and test for stability as I'll be doing that overnight tonight...

Thanks!


----------



## Veii

T[]RK said:


> Can you lock it for edit only by youself? Or maybe separate Mini Calculator from Errors list if there is no separation of rights for edit.


Microsoft Docs is too stupid - it misses specific type of permissions (separation what public accounts can and can not do)
But all permissions are set up


scosey said:


> One thing I don't understand, I do get a slightly lower latency with GDM off and 2T (53.1ns) but GDM on/1T results in a slightly higher bandwith by a few 100mb across the board and it's reproducable.


could replicate the same thing, GDM is a bit easier for the PCBs ~ a bigger bit
But GDM does autocorrect and masks all kind of powering issues
GDM off, 2T is the way to go ~ harder entry, but lower latency and no strange randomness. Timings behave how they should 
1T then is very hard. GDM is kind of cheating for barely any gain.


nikpoth said:


> View attachment 2483679
> 
> 
> This is the set I want to make stable.
> After an hour y-cruncher, 1 error.
> I do not know what else to try.
> cldo vddp 0.900
> vddg ccd 1.050
> vddg iod 1.050
> soc 1.1
> dram v 1.42
> considered excessive voltage??


SOC is GET value, the other ones are SET value
need higher SOC in the bios like 1.125 with a loadline - to drop to 1.1
soo it will only drop to 1.0975 or worst 1.09 up to test
currently it falls under VDDG IOD and likely randomly chokes ~ needs a bit more ,40mV is the absolute minimum difference if VDDG is already the lowest possible

It can also be VDDG CCD a bit too high
(CPU likes near 940-1030mV, less is better)
y-cruncher should have told you if there was an issue , while letting all 9 test run for 4 loops = 48min
(run till manually stopped)
OCCT Extreme AVX2 then will tell you if you have the random voltage chokings (that also runs alone for 1h and stops)


TexasAVI03 said:


> Agree, C-State set to "Disable"
> 
> Also "Power Supply Idle Control" set to "Typical Current Idle"


Focus on disabling DF-C_States inside AMD CBS - NBIO - SMU
Global C & DF states generation , should work ~ it's crucial to sustain higher boost and preserve signal integrity
but overboosting bug will happen with hibernate to wake up states
DF States need to be off - till you can powerplan tame them , else they boost to 45+ ghz and crash instantly on wakeup (after cores sleep)

USBs should never be set to sleep and probably hibernation should be disabled via CMD
Typical current idle works on some boards, on some it bugs out and auto is better
LN2 Mode should be disabled , as also that bugs out on some boards

Do not trust "AUTO" values
APBDIS let to 0 (mission mode) , uncoreOC should be disabled too - use fixed SOC through the loadline settings not through UncoreSOC VID mode

Only DF-States, chipset drivers and powerplans that are delivered ~ cause big issues and random reboots 
(it's a mess AMD tries to hide with forcely disabled sleep states and overseen buggy powerplans)
if you struggle with 2000+ FCLK , just drop down PCIe gen , disable whatever serial port or excessive chipset feature that exists
fix all voltages , including for chipset and if RTX or RX 5xxx/6xxx cards are used - give PCIE 4.0 x8 a chance for resolving your WHEAs
For older cards, enforce 3.0 x16 ~ do not trust auto values, again 

if that doesn't fix it
give the chipset 20mV more, and disable internal audio
if that doesn't fix it (neither does PCIe 3.0 x8)
then it's the ethernet controller that triggers WHEA or the NVME

Give swapping SATA ports a chance - they work together with the chipset
WHEA is mostly IO related at this point , only is Fabric-IO related, if you fail y-cruncher and OCCT Extreme tests (voltage)


----------



## paih85

any idea? vdimm: 1.475v


----------



## Veii

paih85 said:


> any idea? vdimm: 1.475v
> 
> View attachment 2484366











more information to follow , when i have valuable info to share & the will, to debug exotic timings on my dimms 
i want to make a community and personal submenu of "error stacks" , not only "single error" descriptions
Last post means "lower RTT nom to a lower divider" , or a stronger impedance
* it's my notes , nothing to share really ~ maybe you can find it useful

But here i think it's just missing tCKE - if you go the 633 route
Try first 523 , see if it posts - but it can very likely need a cmos reset (make a profile !)
if that fails, go for 533
If that fails, go for 534 with 60-20-20-20 CAD_BUS and tCKE 7
* i haven't gotten RTT_WR /2 to work so far, would be good if there is an easier method than just dropping RTT_PARK down to something stronger

or overall keep tCKE 7 in mind
3667 is such an awkward stepping
You can consider increasing voltage now that you do not run that harsh RTT_PARK
And go for 3733 with tCKE 8

EDIT:
Aah wait, tRFC 2 and 4 is wrong for dual rank dimms
252-160-119

likely you don't need to do anything else , except fixing tRFC
* i need to add in compatibility for dual rank dimms on the mini, but don't want to steal/borrow @chitos123 work 
Need to figure out myself another formula


----------



## Yviena

Think i'm just gonna stick with 4x8 3800CL16 with 7/3/1 RTT for me it's the most stable 55ns with no variance, i did try to get 6/3/3 to work but worse variance in aida64, and i can't really bother spending more time testing, i wanna play the gamez instead.


----------



## MyComputerIsDying

Do they just not make this kit anymore F4-3600C15D-16GTZ ?
It was a 2x8GB [email protected] kit and I can't seem to find it anywhere.
What do i call this now? Just out of luck? Rare kit? Better options?
At the time it was ~$130 for the kit, I really don't want to upgrade and mix ram sticks, some advice will help a lot. I have the 3900x and x570 aorus master, i wanted to get 32gb and was going to go 4 dimms. I've been reading a lot about b die vs non b die and daisy chain vs T topology. 2x16GB b die costs an arm and a leg right now, im a bit confused on the grand scheme of things


----------



## Sphex_

Veii said:


> WHEA is mostly IO related at this point , only is Fabric-IO related, if you fail y-cruncher and OCCT Extreme tests (voltage)


So has it been all but concluded that WHEA for FCLK beyond 1900 MHz is just Infinity Fabric lottery at this point? Or can we hope for further AGESA and BIOS Updates in the future that may aid in pushing FCLK further? I find it extremely strange that bumping the FCLK even 33 MHz (from 1900 to 1933) suddenly causes tons of errors.


----------



## PJVol

Sphex_ said:


> I find it extremely strange that bumping the FCLK even 33 MHz (from 1900 to 1933) suddenly causes tons of errors.


Yeah...


----------



## Veii

Sphex_ said:


> So has it been all but concluded that WHEA for FCLK beyond 1900 MHz is just Infinity Fabric lottery at this point? Or can we hope for further AGESA and BIOS Updates in the future that may aid in pushing FCLK further? I find it extremely strange that bumping the FCLK even 33 MHz (from 1900 to 1933) suddenly causes tons of errors.


Both 
bump to 1mhz higher with BLCK and you'll have WHEA

Over 2000+ is sillicon lottery related
It's rather PCIe 4.0 related and ABL
ABL and AGESA go together - but the main issue is rather board related and PCIe 4.0

They tried to hardlock it at 1900 before on the Patch C update, as a preparation for Patch D ABL update (L3 and IPC bump) but i tried to fight back on it
Gladly the whole community did with this big Reddit sheet
Soo we got no lock but some boards reports WHEA on something that's just firmware related , "autocorrection"

Only Vishay Mosfets on most boards, and unstable Realtek Ethernet doesn't help it
But i see many more people get 2000 FCLK stable
2100... is rare 

Need to get one more board, in order to figure it out fully

broken sleepstates
buggy realtek ethernet
usb issues
all don't help the issue at all
As each of them will trigger WHEA 19
~ which is IO related


----------



## zGunBLADEz

jomama22 said:


> I should add: try disabling global c-states and see how it goes.


i try that bcuz i thought it was idling too low bcuz of the curve -30 but no


----------



## Sphex_

Veii said:


> Both
> bump to 1mhz higher with BLCK and you'll have WHEA
> 
> Over 2000+ is sillicon lottery related
> It's rather PCIe 4.0 related and ABL
> ABL and AGESA go together - but the main issue is rather board related and PCIe 4.0
> 
> They tried to hardlock it at 1900 before on the Patch C update, as a preparation for Patch D ABL update (L3 and IPC bump) but i tried to fight back on it
> Gladly the whole community did with this big Reddit sheet
> Soo we got no lock but some boards reports WHEA on something that's just firmware related , "autocorrection"
> 
> Only Vishay Mosfets on most boards, and unstable Realtek Ethernet doesn't help it
> But i see many more people get 2000 FCLK stable
> 2100... is rare
> 
> Need to get one more board, in order to figure it out fully
> 
> broken sleepstates
> buggy realtek ethernet
> usb issues
> all don't help the issue at all
> As each of them will trigger WHEA 19
> ~ which is IO related


Very interesting. So some boards are reporting normal behavior as WHEAs? I have no problems booting at 2033 with very little effort (haven't tried to go further) but WHEAs spring up at 1933+. I haven't had any USB issues or ethernet problems with my B550 board (although it does have Realtek ethernet). Guess I'll just hope for future BIOS updates to sort it out. Really want to stretch the legs on this 4266 Kit I have.


----------



## Veii

Sphex_ said:


> Very interesting. So some boards are reporting normal behavior as WHEAs? I have no problems booting at 2033 with very little effort (haven't tried to go further) but WHEAs spring up at 1933+. I haven't had any USB issues or ethernet problems with my B550 board (although it does have Realtek ethernet). Guess I'll just hope for future BIOS updates to sort it out. Really want to stretch the legs on this 4266 Kit I have.


Both ASRock X570 ITX/TB3 and B550 ITX/AX - don't report such WHEA's
They do report WHEAs but they don't get them 
For us it's just "stable" or full shutdowns
Well and the typical power budget autocorrection and throttling of cores


----------



## GribblyStick

What about the massive slow downs after 3800? I only saw like one other person reporting that.
Everybody else seems to be getting WHEA errors without much impact. Random restarts but that's about it, sometimes they don't even realize they have them.
Booting on 4000 is no problem, it's "just" not usable.


----------



## Alyjen

GribblyStick said:


> What about the massive slow downs after 3800? I only saw like one other person reporting that.
> Everybody else seems to be getting WHEA errors without much impact. Random restarts but that's about it, sometimes they don't even realize they have them.
> Booting on 4000 is no problem, it's "just" not usable.


+1 to this. Friend of mine did lots of tests with Geekbench 5 (it's quick and scales good with memory) and various settings, if you start getting WHEAs, and not like one a day, but tens or hundreds then performance goes down and settings that are faster on paper are in fact not. Even if the system won't crash.


----------



## bloodyember

PJVol said:


> WRRD 1, ProcODT 32-37 depending on fclk, and with IF1900, everything that follows in ZenTimings screen can be left at Auto.
> You may try mine, they are tm5 stable and 24/7 for about a month. Keep in mind, your ram chips are better binned (Vdimm 1.45V)
> 
> PS: and I woudnt expect good results on 5600X with static OC.


I applied your recommendations. When I put everything on auto my ClkDrv was 24... Tm5 was throwing error 6 like crazy. Had to up it to 40 and it's stable. Thanks for the help.


----------



## Veii

GribblyStick said:


> What about the massive slow downs after 3800? I only saw like one other person reporting that.
> Everybody else seems to be getting WHEA errors without much impact. Random restarts but that's about it, sometimes they don't even realize they have them.
> Booting on 4000 is no problem, it's "just" not usable.
> 
> 
> Alyjen said:
> 
> 
> 
> +1 to this. Friend of mine did lots of tests with Geekbench 5 (it's quick and scales good with memory) and various settings, if you start getting WHEAs, and not like one a day, but tens or hundreds then performance goes down and settings that are faster on paper are in fact not. Even if the system won't crash.
Click to expand...

Something like this:








Very well known and shows when voltages are wrong and package throttling activates
Vermeer is fantastic at autocorrection on soo many places
Where i can't repeat it enough - testing testing testing 

If Aida64 doesn't give a better result but a worse on 3-4 runs, then i don't even bother to waste 1:30h with TM5
If L3 cache is slowed by Package throttle or PBO limits, or CO instability
The same thing. Either it's perfectly consistent on a as clean as possible OS ~ or i don't give it a chance to proof itself stable
Because likely it will be stable, but still throttle and autocorrect internally

Latency has to go down, not up when you increase FCLK
This certainly means that
A.) your memory can't handle these timings
~ you increase voltage
If nothing betters then it's
B.) Your set of voltage and procODT doesn't work anymore and you can trial and error test in 5mV steps what finally ends up as "consistent stable" + verify with y-cruncher all 9 tests
This means, less than 0.3ns deviation on memory, and at worst 0.1ns deviation on L3 latency

The whole cache system is dynamic, soo results will jump up to power reserves
But access latency and for 1CCD units (maximum WRITE timings efficiency) need to be as accurate as possible
I got it down to 0.0ns deviation between runs on mem
But 0.1ns is acceptable. Vermeer can do it, i can do it ~ soo everyone else can also have a consistent Aida64 test 
0.3ns means something is wrong already

The first test you can nearly always trow away, as powermanagement and idle states start to function after the first type of load was applied
Soo the first test might appear better but is for trow-away


----------



## Bojamijams

does tWTRS and tWTRL have to be at a ratio? Like 1:2, 1:3? I'm stable at tWTRL12 and tWTRS 4 but trying to go tWTRL10 is a very late single error on test 2 with Anta777 (cycle 8, 6+ hours into it). I'm wondering if I should be trying tWTRL 8. This is a 4x8 combination with Micron Rev.E

tRTP to 8 also cause a very late single error on test2. 

Would appreciate any tips


----------



## nada324

bloodyember said:


> I applied your recommendations. When I put everything on auto my ClkDrv was 24... Tm5 was throwing error 6 like crazy. Had to up it to 40 and it's stable. Thanks for the help.


I got 4133 SR viper almost same as you, left all auto, and got error #13, sticks are not hot so its RTT problem, in my case mobo set it up to 005 same as yours, setting it to 636 will make other errors show up, cad bus is 24242424 (auto).

@Veii 

Now that i finnally got power && pcb crashes error out, idk with this two, error #10 even with TWRRD set to 3 it will output same thing, and error #13 idk what to change related to RTT, cad bus timings setup is 0 0 0, auto.


----------



## neox387

I had a launch day 5900x that with refused to boot on 1900 (tried different vddp) , but would boot 1933-1967-2000 unstable but only 1867 whea free

Swapped with a new 5600x and this boots fine on 1900 tried up to 2000 and this still boots very smooth did not try higher since from 1933 onwards whea =(

Tried different suggestions:

disable onboard audio
disable realtek lan
disable sata
disable ln2
disable df state
went down to pci gen 3 x8
running 900-1040-1080-1.200

Also Gigabyte b550i doesn't help for ram overclocking
Set 1.47v in bios and gives idle 1.5v and on load 1.53v

This is how much I need to get the following stable 1 stick just touched 50°c with minimal cooling while running Tm5, 3733c15 needed 1.5v. The ram refuses to run cl14 stable tried up to 1.57v

Donno if these rtts are good just trying to follow some of @Veii information, and might try some lower voltages 880-940-1020-1100?


----------



## RosaPanteren

Veii said:


> 5800X= 140A Fuse EDC / but it is strange and bypasses all it's limits


@Veii I've been testing different EDC values on a 5800x and as you have mentioned earlier there is some kind of power "budget" that applies.

Stock EDC=140A for A91 bios and on yields about 650GB/s L3 cache Read/Write/Copy and 10.4ns latency

If I set EDC=450A(A91 MSI bios, this value used to be 350 on A82 bios) there seems to be a significant L3 cache increase for Read/Write/Copy by approx 100GB/s, as well as a 0.2ns latency decrease to 10.2ns.

If I set EDC=600A I get the same L3 cache bandwidth but I get an improvement of both memory latency and L3 cache latency improves by approx 0.2ns and to 10.0ns for L3 cache

The max EDC use reported in HWinfo is ~163A for both EDC=450&600, setting EDC=165A doesn't yield any improvement if I remember correct. So just increasing the limit without seeing more amp usage will have an affect as to my testing.

My knowledge of electrical physics is very limited as is my experience with what these chips can handle in terms of current for a prolonged time, but do you have any take on usage of ~163A for a longer period would potentially be damaging for the chip?

I get that the 140A limit most likely is there for a reason(💡), but with adequate cooling could we make usage of higher PBO limits as a workaround for this power "budget" or is there any other way to unleash L3 bandwidth and memory latency improvement?


----------



## Tobiman

I struggled to get this kit stable at 1.5v. I bumped it up to 1.55v, and voila! I'll have to find time to do an extensive Memtest, but it passed a quick 1-hour test.


----------



## FleischmannTV

@Tobiman 

As far as I remember, @Veii recommended tCKE 9 with this RTT, CAD Bus DrvStr and Setup combination.


----------



## Nighthog

RosaPanteren said:


> @Veii I've been testing different EDC values on a 5800x and as you have mentioned earlier there is some kind of power "budget" that applies.
> 
> Stock EDC=140A for A91 bios and on yields about 650GB/s L3 cache Read/Write/Copy and 10.4ns latency
> 
> If I set EDC=450A(A91 MSI bios, this value used to be 350 on A82 bios) there seems to be a significant L3 cache increase for Read/Write/Copy by approx 100GB/s, as well as a 0.2ns latency decrease to 10.2ns.
> 
> If I set EDC=600A I get the same L3 cache bandwidth but I get an improvement of both memory latency and L3 cache latency improves by approx 0.2ns and to 10.0ns for L3 cache
> 
> The max EDC use reported in HWinfo is ~163A for both EDC=450&600, setting EDC=165A doesn't yield any improvement if I remember correct. So just increasing the limit without seeing more amp usage will have an affect as to my testing.
> 
> My knowledge of electrical physics is very limited as is my experience with what these chips can handle in terms of current for a prolonged time, but do you have any take on usage of ~163A for a longer period would potentially be damaging for the chip?
> 
> I get that the 140A limit most likely is there for a reason(💡), but with adequate cooling could we make usage of higher PBO limits as a workaround for this power "budget" or is there any other way to unleash L3 bandwidth and memory latency improvement?


We had a way to disable the EDC Limit on Ryzen 3000 series but no fix for 4000 & 5000 series yet that I've seen. It's the performance killer. EDC limit is a gimp on overall performance on these cpu's with PBO usage.


----------



## Tobiman

FleischmannTV said:


> @Tobiman
> 
> As far as I remember, @Veii recommended tCKE 9 with this RTT, CAD Bus DrvStr and Setup combination.


Thanks for the heads up. I'll check it out.


----------



## zGunBLADEz

Veii said:


> Something like this:
> View attachment 2484409
> 
> Very well known and shows when voltages are wrong and package throttling activates
> Vermeer is fantastic at autocorrection on soo many places
> Where i can't repeat it enough - testing testing testing
> 
> If Aida64 doesn't give a better result but a worse on 3-4 runs, then i don't even bother to waste 1:30h with TM5
> If L3 cache is slowed by Package throttle or PBO limits, or CO instability
> The same thing. Either it's perfectly consistent on a as clean as possible OS ~ or i don't give it a chance to proof itself stable
> Because likely it will be stable, but still throttle and autocorrect internally
> 
> Latency has to go down, not up when you increase FCLK
> This certainly means that
> A.) your memory can't handle these timings
> ~ you increase voltage
> If nothing betters then it's
> B.) Your set of voltage and procODT doesn't work anymore and you can trial and error test in 5mV steps what finally ends up as "consistent stable" + verify with y-cruncher all 9 tests
> This means, less than 0.3ns deviation on memory, and at worst 0.1ns deviation on L3 latency
> 
> The whole cache system is dynamic, soo results will jump up to power reserves
> But access latency and for 1CCD units (maximum WRITE timings efficiency) need to be as accurate as possible
> I got it down to 0.0ns deviation between runs on mem
> But 0.1ns is acceptable. Vermeer can do it, i can do it ~ soo everyone else can also have a consistent Aida64 test
> 0.3ns means something is wrong already
> 
> The first test you can nearly always trow away, as powermanagement and idle states start to function after the first type of load was applied
> Soo the first test might appear better but is for trow-away


The problem with aida is the inconsistency of readings of pbo. I dont have a dark where i can tweak a single boost where i get consistency on the latency readings. For example, latency is always read on core 0 thats not my faster core. Its only consistent on an static overclock. Last 2 bios have been a pita on stability versus 1803 bios.

Newest bios at least in my board using pbo are limiting boosting clocks and L cache readings. 1musmus posted something similar about this reporting less boosting and flags on L3 specially. I wonder if this was the cause of the usb issues to begin with.. That explains my way to duplicate a crash bombarding the L3 cache reads on aida on static where L cache reads are way higher than single pbo bcuz oc higher clocks. Same behavior is visible with the phone usb just charging and doing cb runs where the usb will go in and out.

I can also duplicate a bootloop using afterburner where i have a autostart stable clock. Crash the gpu on purpose pc will auto crash go back to windows and get into a bootloop sort of things. Funny tho the profile loaded on msi autostart is a stable overclock. Have to get into safemode to turn off autostart and that would fix the issue.


----------



## 0verpowered

Just wanted to share my findings for those having trouble OC'ing IF to 1800mhz. My setup is:
Asrock x370 taichi beta 6.61 bios
5800x
Patriot viper steel 4400(b-die)

At first i tried using XMP default settings and just changing IF to 1800 and ram to 3600. At default settings would get hard resets after running AIDA64 mem benchmark 1 or 2 times. When playing around with different SoC and vddp, vddg ccd/iod i would get weird audio glitches and sometimes USB devices not being recognized. After scouring various articles and threads and trial and error i found sticking to these rules are helpful:
1. Vddp seems to be best around .900
2. Keep vddg ccd and vddg iod the same
3. Make sure vddg ccd and vddg iod are at least .05 less than SoC. Ie: if SOC is 1.1 then IOD and CCD should be 1.05 or lower.
4. if still having stability issues try increasing procodt to 43 or higher if still having issues when increasing voltages arent helping.

I started to get some stability with the following voltages:

SoC 1.1
Vddp 0.9
Vddg ccd 1.0
Vddg iod 1.0

But still would reboot after running AIDA 4-5 times.

I tried setting CR to 2T and disabling gear down mode, but still crashed after 5 times or so. Keep in mind the default XMP settings were 19-19-19-19 so the RAM wasnt the issue.

Then i tried setting procODT to 43.6 and was able to run AIDA 8-9 times before crashing.

Then raised ProcODT to 48ohms and now seems stable after 15+ AIDA runs and gaming.

Once stable now you can start tuning timings.

I would also log your settings and results after each change on paper or something so you know whats working and whats not.


----------



## MyComputerIsDying

MyComputerIsDying said:


> Do they just not make this kit anymore F4-3600C15D-16GTZ ?
> It was a 2x8GB [email protected] kit and I can't seem to find it anywhere.
> What do i call this now? Just out of luck? Rare kit? Better options?
> At the time it was ~$130 for the kit, I really don't want to upgrade and mix ram sticks, some advice will help a lot. I have the 3900x and x570 aorus master, i wanted to get 32gb and was going to go 4 dimms. I've been reading a lot about b die vs non b die and daisy chain vs T topology. 2x16GB b die costs an arm and a leg right now, im a bit confused on the grand scheme of things


any suggestion on how to upgrade here?


----------



## Veii

MyComputerIsDying said:


> any suggestion on how to upgrade here?


Dual rank 2x16 do end up as a better option for OC, while being an equal option to 4 dimms - as for maximum bandwidth
(chipset interleaving and rank interleaving - are the keywords here)

They are expensive, but so are also 4 dimms
For me at least, they cost the same thing.
Manufactures charge by capacity which is correct. Some retailers overcharge by demand, which is not correct 

Currently i do have my eyes on the BLM2K8G44C19U4B
Which are also 4400-19-19-19 dimms, but at 1.4v instead of 1.45v like the Vipers
They do cost 60$ more tho and where once for 170 instead 180€

The reason i want them aside from the better binning, is the A3 PCB 
But it's still a conflicting decision because of the high b-die price like the old days (180-220€ per 16gb kit)
And also questionable, when AM4 is soon EOL , same for DDR4

I can't help you, except advice to go for 2x16 instead of 4x8
Sadly there are rarely any "great" 2x16, like tRCD 15 3600 kits, or 4000 tRCD 18 or 19 kits 
soo there is not really a recommendable option out there
But typical 16-16-16 16gb dimms are oke'ish , they are at least not bad ~ but you have to luck out on the PCB 
It could be B1 or B2 on 3600 
Only B2 is guaranteed at 4100+ rated dimms - where Vipers are A0 (B0) on 4000 , and only A2/B2 at 4400+

Well what you end up with, 4x8 or 2x16 is luck based - and monetary
But 2x16 is a better option for OC - IF there are good sets out there
From the price perspective, both options should cost equal ~ equally much


----------



## Veii

Tobiman said:


> I struggled to get this kit stable at 1.5v. I bumped it up to 1.55v, and voila! I'll have to find time to do an extensive Memtest, but it passed a quick 1-hour test.
> 
> View attachment 2484475


Get GDM away, 2T or 1T
There is no reason why you should run GDM and odd timings
Maybe going 14-14-14 on it would be acceptable

But yes, tCKE 9 on this
These RTTs need high voltage, but they will not heat up the dimms much
And "high" voltage also means , better timings scaling
I daily 1.65 right now, jumping between 1.64 and 1.66 for my RTT tests
Don't be afraid to daily higher voltage, as long as RTT_PARK is weaker

Entry point on these is higher, than 706 , or 703 for dual rank (entry point is 1.48v)
But i feel they are better
While currently being undecided on 536 or 436 - both without CAD_BUS SETUP timings
(can't get these to align anymore, while tCKE still works)

If you struggle with GDM off , 2T - increase both tWTR and tRRD (tRRD_L specific)


RosaPanteren said:


> @Veii I've been testing different EDC values on a 5800x and as you have mentioned earlier there is some kind of power "budget" that applies.
> 
> 
> RosaPanteren said:
> 
> 
> 
> I get that the 140A limit most likely is there for a reason(💡), but with adequate cooling could we make usage of higher PBO limits as a workaround for this power "budget" or is there any other way to unleash L3 bandwidth and memory latency improvement?
Click to expand...

I haven't seen beyond 400A an improvement , but i'll give 600A a shot too

There are many powerbudgets, but the EDC FUSE limit is what you could read out on HWInfo
There is nothing you can do to exceed this annoying limit - and sadly SOC and FCLK will cut into it
Soo your only option is -30 CO and positive vcore offset ~ oor telemtry faking

Negative CO , does work similar to telemetry faking - and overall the "reported powerdraw" will be lower
While maybe not accurate by SMU, but still "lower"
That's one of the reasons you should finetune your PBO and watch L3 latency in ns
It will show if you have clock stretching. 10.5/10.4ns is 4.85Ghz sustainable for a brief moment on all cores
10.7 = 4.75
10.9 = 4.65
Higher will mean that you hit the EDC limit or cores can not sustain the frequency

The EDC limit you apply on PBO is one of the flags , and only a trick since Patch D till 1.2.0.0
1201(A) seems to finally fix cache boosting without the requirements for this lifted EDC limit ~ but i still wait for a bios update
Biostar pushed it out on the 5th of March, ASRock only covered 4-5 boards out of 30 at this date.

Anyways, it's known 
That boost is what gave them a big IPC lead again - where before i hit 610cb R20, current's it's 640cb
or 604p CPU-Z , currently 677p
Sadly at the cost of limiting Curve Optimizer to -30 at max, and limiting Boost freq to 200Mhz at max
Likely because CPUs will hit FMax afterwards, and it makes no sense to add more as an option

Stupid artificial limits, but it is what it is~
CTR is there for such, and makes progress - but it's yet far off done
I shouldn't report much more than this picture here
Don't have anything signed and wouldn't too ~ but out of respect








Maybe you notice something on the CCX ACPI numbers 
3 & 6, in this care 5 & 8 are my better cores

Sadly by having to lift EDC limit that high (not that it won't be throttled internally anyways)
You should limit TDC, as lifting EDC that high without negative CO - will strongly increase supplied voltage & many allcore loads will fail
Try my trick , lowest possible CO and mask it with positive vcore
But do not use any vcore offset with CTR ! ~ you can use negative CO and high scalar to improve things , but it's also not recommendable for normal finetuners. Far too much debugging required



zGunBLADEz said:


> The problem with aida is the inconsistency of readings of pbo. I dont have a dark where i can tweak a single boost where i get consistency on the latency readings. For example, latency is always read on core 0 thats not my faster core. Its only consistent on an static overclock. Last 2 bios have been a pita on stability versus 1803 bios.


I don't either, HybridOC performs worse and messes up L3 cache + L3 access latency (inner-core)

Memory test is not only single core based, but you are right that it does use core affinity
A good PBO should be set up soo all cores hit the set frequency
Higher numbers are nice and dandy, but the CPU will clock stretch and throttle back - not only adding inconsistency but also eating latency for it's throttling work

All cores have to boost to the same value = a good PBO
Better use less boost override but have a consistent frequency
It makes no sense to fake boost and add clock stretching
The CPU will prefer the better cores anyways
But causing clock stretching on the worst

If the sample is that unbalanced, better focus on CTR
Although i still prefer my PBO over CTR
It's still outperforming it 

They only won't hit the same allcore freq (in TM5 and Aida64)
If you hit the EDC Fuse limit before that 
Which is for a 5900X and 5950X == 200A
Only negative CO and telemtry faking, does help against this hard limit 
But when it comes to "per core boost" 
Each and every core has to hit the same overriten boost frequency

ASUS Gigabyte and MSI do cheat a bit with boost override
Manually enforce it to 0mhz , till you fix your boosting system to hit 4.95 or 4.85 (up to CPU)
on each of the cores
For me it's 4.85 with +200, can't go higher without modifications any exploits
Well or CTR, just that CTR needs more work


----------



## PowerK

Veii said:


> But yes, tCKE 9 on this


Veii,
what's the formula for correct tCKE? And what would be the optimal RTT values for 4 sticks of 8GB SR ?


----------



## Veii

PowerK said:


> Veii,
> what's the formula for correct tCKE? And what would be the optimal RTT values for 4 sticks of 8GB SR ?


It's frequency dependent
Each 200MT/s = +2 tCKE
3600 = 6/7
3800 = 9
4000 = 11
4200 = 13

Stock 3600 = 6, but 7 say my findings
probably it goes in stepping's of 3 like CkeSetup Timing


----------



## mongoled

Veii said:


> Currently i do have my eyes on the BLM2K8G44C19U4B


I started a thread in the "Memory" forum asking about

CMK16GX4M2Z4000C16 with no response from anyone.

So I come to post in the "wrong" place...... again.

Have you seen anybody using these as I would like to know what PCB is on these dimms as they look to be a possible contender for highly binned modules .....


----------



## Veii

mongoled said:


> I started a thread in the "Memory" forum asking about
> 
> CMK16GX4M2Z4000C16 with no response from anyone.
> 
> So I come to post in the "wrong" place...... again.
> 
> Have you seen anybody using these as I would like to know what PCB is on these dimms as they look to be a possible contender for highly binned modules .....


Really no, i didn't expect to see a tRCD 16 4000 kit 
the timings look runnable by my 4000 kit - and soo i'm sceptical of this A0 readout
But sadly no. It probably would need a teardownt to check
A3's are rare. i got my only view on the crucials because crucial does as always own things and redefines JEDEC by their technical team
The PCB i've seen is neither A1 nor A2 - and A0 beyond 4133 will fail miserably, unless you do some powering tweaks
4000 is usually the highest they sell it, but with a custom PCB then - Viper 4000s are custom A0's. I thought at first it was A1 on mine

That would be 4400 tRCD 18 , instead of 19 - hmm, i'm interested curious now too
But then it depends on the manufacture. If this was only crucial


----------



## _frame_

Has anyone tried Patriot Viper Blackout 4400MHz CL*18* ?
PVB416G440C8K
It was on sale for 115 euro for 2x8gb
Tested Timings: 18-26-26-46 
Tested Voltage for Profile 1: 1.45V
Is it b-die?


----------



## zGunBLADEz

Veii said:


> I don't either, HybridOC performs worse and messes up L3 cache + L3 access latency (inner-core)
> 
> Memory test is not only single core based, but you are right that it does use core affinity
> A good PBO should be set up soo all cores hit the set frequency
> Higher numbers are nice and dandy, but the CPU will clock stretch and throttle back - not only adding inconsistency but also eating latency for it's throttling work
> 
> All cores have to boost to the same value = a good PBO
> Better use less boost override but have a consistent frequency
> It makes no sense to fake boost and add clock stretching
> The CPU will prefer the better cores anyways
> But causing clock stretching on the worst
> 
> If the sample is that unbalanced, better focus on CTR
> Although i still prefer my PBO over CTR
> It's still outperforming it
> 
> They only won't hit the same allcore freq (in TM5 and Aida64)
> If you hit the EDC Fuse limit before that
> Which is for a 5900X and 5950X == 200A
> Only negative CO and telemtry faking, does help against this hard limit
> But when it comes to "per core boost"
> Each and every core has to hit the same overriten boost frequency
> 
> ASUS Gigabyte and MSI do cheat a bit with boost override
> Manually enforce it to 0mhz , till you fix your boosting system to hit 4.95 or 4.85 (up to CPU)
> on each of the cores
> For me it's 4.85 with +200, can't go higher without modifications any exploits
> Well or CTR, just that CTR needs more work



Look what the new bios on my board introduced (i also used this to trigger my kernel panicks without any whea... still dont explain the crashes on idle or maybe in that idle moment gets to that l3 cache of "1200" in a brief moment which will crash the system)

heres a video of how i trigger it on my system





it dont happen on pbo bcuz i dont get that high on pbo and "supposedly" its boosting to 46.50x avg on all cores on pbo which should be higher l3 cache reads.. not only that my boosting is worst than bios 1803..










My system was stable before on bios 1803 @ 48x/47x with 1.305v... The problem on the new bios on my system starts when the L3 Reads gets around the 1200 mark which pbo dont get me there on the new bios and that confirms what 1musmus say about his findings


----------



## Veii

_frame_ said:


> Has anyone tried Patriot Viper Blackout 4400MHz CL*18* ?
> PVB416G440C8K
> It was on sale for 115 euro for 2x8gb
> Tested Timings: 18-26-26-46
> Tested Voltage for Profile 1: 1.45V
> Is it b-die?


It's not 
any odd value timings they sell, is hynix C-Die
only the 4133 the oldmodels have two profiles as 19-19-19 and 18-20-20 for example
this is either DJR or CJR
but hynix for sure


zGunBLADEz said:


> Look what the new bios on my board introduced (i also used this to trigger my kernel panicks without any whea... still dont explain the crashes on idle or maybe in that idle moment gets to that l3 cache of "1200" in a brief moment which will crash the system)
> 
> heres a video of how i trigger it on my system
> 
> 
> 
> 
> 
> it dont happen on pbo bcuz i dont get that high on pbo and "supposedly" its boosting to 46.50x avg on all cores on pbo which should be higher l3 cache reads.. not only that my boosting is worst than bios 1803..
> View attachment 2484587
> 
> 
> 
> My system was stable before on bios 1803 @ 48x/47x with 1.305v... The problem on the new bios on my system starts when the L3 Reads gets around the 1200 mark which pbo dont get me there on the new bios and that confirms what 1musmus say about his findings
> View attachment 2484586


Ok ok i see
Thanks a lot for the recording and voiceover
This is very appreciated !
* and honestly even more personal

I'm in touch with Yuri since , let's say a bit ~ after annoying him and always keeping a "rivals" relationship
There is stuff i can talk about and stuff on the development i shouldn't talk about

He is right here, 1201 is fully different and slipped another potential rewrite of the Boosting and Powermanagement
This is AMDs third time in about 2 months ~ while they are fully aware of the idle crashes they introduced after AGESA 1.1.0.0 Patch D
The so called "allcore L3 overdrive ~ cache boost" and big IPC gain

If you've maybe followed my rare posts on twitter, we talk about "OverBoost"
Something CTR users are a plagued off, or the random idle shutdowns ~ and i also think random WHEA that pop up on people's system under cache load (bless that i don't have this poop ~ but do have the crashes)

It needs a huge wall of text to explain what is kind of going on, but let's say the variable L3 cache is "normal" & "dynamic"
If you want very consistent results - put the autoclicker to 2sec. Let it a bit of time to idle down
If you want to stick your nose further in the problematic rabbit hole
Open ComputerManagement -> Performance -> Performance Monitoring -> Green *+* sign -> Processor Information -> % Processor Performance
Add each of the threads in there 0,1 / 0,2 / 0,31 and so on
Do not add any total or combined instances, only thread by thread
Then double-click on one of the threads -> Graph -> change the ACPI size to 200 instead of 100

Now keep it on track.


Spoiler: If you see any huge spikes like this














^ this are 3 dynamic modes combined - including the idle + AMDs boosting (can't say more till the information is public)
If this happens, up to 190-200 or more, then you trigger one of the bugs of the recent 2 months and the thing nobody wants to talk about

An EDC Fuse Limit will not trigger on single core boosting - but an overboost will surely trigger if the conditions are right:

cores do hibernate and not only sleep. they reach bellow 550mhz state
DF_C-States are on or Generation of Global C+DF states are on *and* do generate more than they should
* Global C States function and should be enabled . DF-States function but are broken because of the overdrive "method" AMD used. It can be tamed but for nearly everyone it's broken.

 the powerplan which is shipped with the chipset drivers, uses a newer implemented Rocket mode
(a harsh multi core boosting algorithm and overdrive. something @ManniX-ITA would be interested about)
instead of the old Single , specific golden core boosting method ~ which like an atom drives it's friendly cores with up *and* down.
Rocket boosting method, is aggressive, very aggressive & if you don't have stability taming with it, it will surely crash the CPU. Alone by the sheer amount of voltage changes and frequency changes in too little time.
This is where dLDO_injection came into play. Digital Low Dropout voltage regulator and voltage additive.
A hidden feature that was already backed into these samples but never activated before the 1100 Patch D, or 1.1.8.0/8.1 public testing rabbit "beta"

Sadly this overdrive feature, as amazing as the IPC gain was with it (is). It's instability and sacrifices are kept into the dark.

Forbidding sleep states to take a round over the problem instead of addressing and testing it before the wild release (although masked under changelogs)
Trying to push onto us first via 1.1.0.0 Patch C, a 1900 FCLK lock , in order to keep up with fabric and voltage stability
taking away dynamic MCLK and SOC (cutting for us 20-30W of potential boosting freedom) because PCIe 4.0 stability and high FCLK don't go well together (cutting lanes on mobile Renoir was another option)
And now who knows what another sensor out of at least 30+ sensoring and prevention mechanism is added into play, to use even more extraordinary features to boost performance more and likely overvolt more (1.5v "limit" is nothing. Shouldn't say more)

This generation even when thoughtfully designed on it's core. Is a hassle for normal consumers !
As much as i appreciate the continuous invention and usage of extraordinary methods and features
The hiddenness in order to prevent algorithm leakage and cloning ~ the lack of openness to it's own userbase who do all the annoying debugging.
Is what really drives people away from the platform.
As amazing and cutting edge as this current usable technology is !
============================
This is what kept me the recent days/weeks busy
And why the powerplan still isn't done or i barely do memOC pushing (down to 48.7ns for now) 
* wondering if i should just increase FCLK into the further unobtanium territory ~ to lower latency that way further


Spoiler: PP Visualization & CPPC awareness

















Spoiler: CPPC Focus & another OB "Taming" demonstration














If you have the time @zGunBLADEz , track it
But you'll fall deep into another rabbit hole.
Soo be sure DF-C_States are off or have the motivation to edit your default powerplans with a limiter in them

Well or option 3, wait a bit longer and use the powerplan that i'll share.
Hopefully by the time, other options will be finetuned and public, and every board will have 1201AB(B).
Hopefully without IO WHEA, but this part is more a dream than reality. AMD's focus is to dominate and shape their boosting further and further.
About us FCLK "freaks" they will only care at the very end ~ till we get us heard & they can't hide it's existence anymore
Soo keep pushing 🔥


----------



## zGunBLADEz

So it is what i imagine then, interesting.
I will try to follow later as im short of time i just want to drop a quick line to thx for the info..

Now, aida64 is amds achilles heel :/


----------



## jomama22

Veii said:


> Get GDM away, 2T or 1T
> There is no reason why you should run GDM and odd timings
> Maybe going 14-14-14 on it would be acceptable
> 
> But yes, tCKE 9 on this
> These RTTs need high voltage, but they will not heat up the dimms much
> And "high" voltage also means , better timings scaling
> I daily 1.65 right now, jumping between 1.64 and 1.66 for my RTT tests
> Don't be afraid to daily higher voltage, as long as RTT_PARK is weaker
> 
> Entry point on these is higher, than 706 , or 703 for dual rank (entry point is 1.48v)
> But i feel they are better
> While currently being undecided on 536 or 436 - both without CAD_BUS SETUP timings
> (can't get these to align anymore, while tCKE still works)
> 
> If you struggle with GDM off , 2T - increase both tWTR and tRRD (tRRD_L specific)
> 
> I haven't seen beyond 400A an improvement , but i'll give 600A a shot too
> 
> There are many powerbudgets, but the EDC FUSE limit is what you could read out on HWInfo
> There is nothing you can do to exceed this annoying limit - and sadly SOC and FCLK will cut into it
> Soo your only option is -30 CO and positive vcore offset ~ oor telemtry faking
> 
> Negative CO , does work similar to telemetry faking - and overall the "reported powerdraw" will be lower
> While maybe not accurate by SMU, but still "lower"
> That's one of the reasons you should finetune your PBO and watch L3 latency in ns
> It will show if you have clock stretching. 10.5/10.4ns is 4.85Ghz sustainable for a brief moment on all cores
> 10.7 = 4.75
> 10.9 = 4.65
> Higher will mean that you hit the EDC limit or cores can not sustain the frequency
> 
> The EDC limit you apply on PBO is one of the flags , and only a trick since Patch D till 1.2.0.0
> 1201(A) seems to finally fix cache boosting without the requirements for this lifted EDC limit ~ but i still wait for a bios update
> Biostar pushed it out on the 5th of March, ASRock only covered 4-5 boards out of 30 at this date.
> 
> Anyways, it's known
> That boost is what gave them a big IPC lead again - where before i hit 610cb R20, current's it's 640cb
> or 604p CPU-Z , currently 677p
> Sadly at the cost of limiting Curve Optimizer to -30 at max, and limiting Boost freq to 200Mhz at max
> Likely because CPUs will hit FMax afterwards, and it makes no sense to add more as an option
> 
> Stupid artificial limits, but it is what it is~
> CTR is there for such, and makes progress - but it's yet far off done
> I shouldn't report much more than this picture here
> Don't have anything signed and wouldn't too ~ but out of respect
> View attachment 2484569
> 
> Maybe you notice something on the CCX ACPI numbers
> 3 & 6, in this care 5 & 8 are my better cores
> 
> Sadly by having to lift EDC limit that high (not that it won't be throttled internally anyways)
> You should limit TDC, as lifting EDC that high without negative CO - will strongly increase supplied voltage & many allcore loads will fail
> Try my trick , lowest possible CO and mask it with positive vcore
> But do not use any vcore offset with CTR ! ~ you can use negative CO and high scalar to improve things , but it's also not recommendable for normal finetuners. Far too much debugging required
> 
> 
> I don't either, HybridOC performs worse and messes up L3 cache + L3 access latency (inner-core)
> 
> Memory test is not only single core based, but you are right that it does use core affinity
> A good PBO should be set up soo all cores hit the set frequency
> Higher numbers are nice and dandy, but the CPU will clock stretch and throttle back - not only adding inconsistency but also eating latency for it's throttling work
> 
> All cores have to boost to the same value = a good PBO
> Better use less boost override but have a consistent frequency
> It makes no sense to fake boost and add clock stretching
> The CPU will prefer the better cores anyways
> But causing clock stretching on the worst
> 
> If the sample is that unbalanced, better focus on CTR
> Although i still prefer my PBO over CTR
> It's still outperforming it
> 
> They only won't hit the same allcore freq (in TM5 and Aida64)
> If you hit the EDC Fuse limit before that
> Which is for a 5900X and 5950X == 200A
> Only negative CO and telemtry faking, does help against this hard limit
> But when it comes to "per core boost"
> Each and every core has to hit the same overriten boost frequency
> 
> ASUS Gigabyte and MSI do cheat a bit with boost override
> Manually enforce it to 0mhz , till you fix your boosting system to hit 4.95 or 4.85 (up to CPU)
> on each of the cores
> For me it's 4.85 with +200, can't go higher without modifications any exploits
> Well or CTR, just that CTR needs more work


Focusing on the PBO stuff. MSI (at least the ACE and the 1.1.0.0 patch C (may be D)) seems to have a fuse limit of 215 amps, as edc defaults to such a 'motherboard' value in AMD's own pbo section in the bios. When using that motherboard, I was able to achieve better multicore results in r20 than anything possible with my Dark Hero I have installed atm, to the tune of 1-2%. Nothing huge, but just a genuine note.

I have also noticed that depending on how you set your pbo limits and voltages greatly varies your result. Doing any sort of voltage offset will destroy your milti-core pbo boosting. While it may help single thread boosting, it will compromise any milti-core pbo boosting efforts. 

Also, I do not believe telemetry faking is doing much of anything with the current boost algo as I see only margin of error type differences between soc and cpu telemetry muckery compared to just leaving them alone (on both the MSI ace and dark hero).

Somthing else interesting to note, with the dark hero, I use the dynamic OC switcher. Currently, I am running bios 3003 which I believe is 1.8.0.0 patch C. Setting the switching amperage to 60 or below will always allow aida's l3 to report properly (1500 or so with my [email protected] 4800), above 60 and it will fall into the PBO trap of low l3 bandwidth. With the known fact that higher ecd will yield better l3 bandwidth under pbo and watching how aida behaves power wise (does a large inrush of power usage and then tampers off) I'm guessing that pbo was stalling at the same moment aida was trying to start forcing l3 writes (or reads), only allowing a core or two to become active in any meaningful way. Using higher edc limits (even beyond the "fuse" limit) must still be used in some predictive algorithm for pbo clocking.

Using dynamic oc switcher is interesting when it comes to L3 latency as it will always read 9.9ns. I believe this is using the pbo side of the oc switcher and now changing to all core as running a pure all core overclock seems to net me around 10.3-10.5ns (@4800).

I have also noticed negative clock stretching (clock shrinking? Lol) happening when messing with edc limits and dynamic oc switcher. Can get better single core r20 scores under pbo while reporting even less effective clock that at pure stock settings with no pbo. This can be done by raising edc to somthing like 245 when using dynamic oc switcher. Clock stretching begins to really start happening when I begin to lower edc below 140 or so. 

Either way, just throwing this out there.


----------



## gabian

Veii said:


> It's frequency dependent
> Each 200MT/s = +2 tCKE
> 3600 = 6/7
> 3800 = 9
> 4000 = 11
> 4200 = 13
> 
> Stock 3600 = 6, but 7 say my findings
> probably it goes in stepping's of 3 like CkeSetup Timing


As i do not know about this formula, I had put 1 on tCKE. Does it mean 9 (i am at 3800) would have better perf than 1 ?


----------



## jomama22

Veii said:


> It's not
> any odd value timings they sell, is hynix C-Die
> only the 4133 the oldmodels have two profiles as 19-19-19 and 18-20-20 for example
> this is either DJR or CJR
> but hynix for sure
> 
> Ok ok i see
> Thanks a lot for the recording and voiceover
> This is very appreciated !
> * and honestly even more personal
> 
> I'm in touch with Yuri since , let's say a bit ~ after annoying him and always keeping a "rivals" relationship
> There is stuff i can talk about and stuff on the development i shouldn't talk about
> 
> He is right here, 1201 is fully different and slipped another potential rewrite of the Boosting and Powermanagement
> This is AMDs third time in about 2 months ~ while they are fully aware of the idle crashes they introduced after AGESA 1.1.0.0 Patch D
> The so called "allcore L3 overdrive ~ cache boost" and big IPC gain
> 
> If you've maybe followed my rare posts on twitter, we talk about "OverBoost"
> Something CTR users are a plagued off, or the random idle shutdowns ~ and i also think random WHEA that pop up on people's system under cache load (bless that i don't have this poop ~ but do have the crashes)
> 
> It needs a huge wall of text to explain what is kind of going on, but let's say the variable L3 cache is "normal" & "dynamic"
> If you want very consistent results - put the autoclicker to 2sec. Let it a bit of time to idle down
> If you want to stick your nose further in the problematic rabbit hole
> Open ComputerManagement -> Performance -> Performance Monitoring -> Green *+* sign -> Processor Information -> % Processor Performance
> Add each of the threads in there 0,1 / 0,2 / 0,31 and so on
> Do not add any total or combined instances, only thread by thread
> Then double-click on one of the threads -> Graph -> change the ACPI size to 200 instead of 100
> 
> Now keep it on track.
> 
> 
> Spoiler: If you see any huge spikes like this
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ^ this are 3 dynamic modes combined - including the idle + AMDs boosting (can't say more till the information is public)
> If this happens, up to 190-200 or more, then you trigger one of the bugs of the recent 2 months and the thing nobody wants to talk about
> 
> An EDC Fuse Limit will not trigger on single core boosting - but an overboost will surely trigger if the conditions are right:
> 
> cores do hibernate and not only sleep. they reach bellow 550mhz state
> DF_C-States are on or Generation of Global C+DF states are on *and* do generate more than they should
> * Global C States function and should be enabled . DF-States function but are broken because of the overdrive "method" AMD used. It can be tamed but for nearly everyone it's broken.
> 
> the powerplan which is shipped with the chipset drivers, uses a newer implemented Rocket mode
> (a harsh multi core boosting algorithm and overdrive. something @ManniX-ITA would be interested about)
> instead of the old Single , specific golden core boosting method ~ which like an atom drives it's friendly cores with up *and* down.
> Rocket boosting method, is aggressive, very aggressive & if you don't have stability taming with it, it will surely crash the CPU. Alone by the sheer amount of voltage changes and frequency changes in too little time.
> This is where dLDO_injection came into play. Digital Low Dropout voltage regulator and voltage additive.
> A hidden feature that was already backed into these samples but never activated before the 1100 Patch D, or 1.1.8.0/8.1 public testing rabbit "beta"
> 
> Sadly this overdrive feature, as amazing as the IPC gain was with it (is). It's instability and sacrifices are kept into the dark.
> 
> Forbidding sleep states to take a round over the problem instead of addressing and testing it before the wild release (although masked under changelogs)
> Trying to push onto us first via 1.1.0.0 Patch C, a 1900 FCLK lock , in order to keep up with fabric and voltage stability
> taking away dynamic MCLK and SOC (cutting for us 20-30W of potential boosting freedom) because PCIe 4.0 stability and high FCLK don't go well together (cutting lanes on mobile Renoir was another option)
> And now who knows what another sensor out of at least 30+ sensoring and prevention mechanism is added into play, to use even more extraordinary features to boost performance more and likely overvolt more (1.5v "limit" is nothing. Shouldn't say more)
> 
> This generation even when thoughtfully designed on it's core. Is a hassle for normal consumers !
> As much as i appreciate the continuous invention and usage of extraordinary methods and features
> The hiddenness in order to prevent algorithm leakage and cloning ~ the lack of openness to it's own userbase who do all the annoying debugging.
> Is what really drives people away from the platform.
> As amazing and cutting edge as this current usable technology is !
> ============================
> This is what kept me the recent days/weeks busy
> And why the powerplan still isn't done or i barely do memOC pushing (down to 48.7ns for now)
> * wondering if i should just increase FCLK into the further unobtanium territory ~ to lower latency that way further
> 
> 
> Spoiler: PP Visualization & CPPC awareness
> 
> 
> 
> 
> View attachment 2484611
> 
> 
> 
> 
> 
> 
> Spoiler: CPPC Focus & another OB "Taming" demonstration
> 
> 
> 
> 
> View attachment 2484612
> 
> 
> 
> If you have the time @zGunBLADEz , track it
> But you'll fall deep into another rabbit hole.
> Soo be sure DF-C_States are off or have the motivation to edit your default powerplans with a limiter in them
> 
> Well or option 3, wait a bit longer and use the powerplan that i'll share.
> Hopefully by the time, other options will be finetuned and public, and every board will have 1201AB(B).
> Hopefully without IO WHEA, but this part is more a dream than reality. AMD's focus is to dominate and shape their boosting further and further.
> About us FCLK "freaks" they will only care at the very end ~ till we get us heard & they can't hide it's existence anymore
> Soo keep pushing 🔥


So then what agesa is recommended to attempt stable above 1900 fclock? I get the damn bus/interconnect correctable wheas anywhere above 1900. 

Also, I wouldn't be surprised if this type of boosting behavior is eating into the PBO limits, hence the reduction in multi core pbo score.


----------



## Veii

gabian said:


> As i do not know about this formula, I had put 1 on tCKE. Does it mean 9 (i am at 3800) would have better perf than 1 ?


It would regulate supplied memory voltage and regulate down "active" time
1 means always active

A wrong value does create instability
A used value does add a bit of latency, but helps relieve a lot of strain from the PCB.
Also without strong RTTs, helps to daily 1.6v and more
Not to forget that the dimms stay cooler. Anything variable, as long as tamed is a good thing
Frequency and voltage. It allows hardware to be pushed beyond it's limits

The little 0.2ns (you actually have to fight a lot for that much)
Are dealable with, as you can use more voltage and so lower timings + relieving a bit of strain 



jomama22 said:


> So then what agesa is recommended to attempt stable above 1900 fclock? I get the damn bus/interconnect correctable wheas anywhere above 1900.
> 
> Also, I wouldn't be surprised if this type of boosting behavior is eating into the PBO limits, hence the reduction in multi core pbo score.


The reduction of multi is because of the hardcoded EDC *Fuse* Limit, which actively Package throttles back
Sadly even my gimped lottery unit, only has to follow the 120/125A 5600X Fuse Limit

Don't forget that SOC will eat into the powering budget
Which is why users see better boosting on less FCLK
My advice is again, highest possible negative CO and added vcore offset, to cover for it
This fakes telemetry and allows more powerdraw, but fakes the wattage and ampere results

Do NOT use any offset with CTR !

Edit:
Any agesa except for 1100 Patch C (SMU 56.34) works and has no FCLK limit


----------



## FleischmannTV

Lord @Veii,

is tCKE 9 @ 3800 dependent on 6/3/3 | 40-20-20-20 | 3-3-15 or can you run it independent from RTT, CAD Bus DrvStr and Setup?


----------



## jomama22

Veii said:


> It would regulate supplied memory voltage and regulate down "active" time
> 1 means always active
> 
> A wrong value does create instability
> A used value does add a bit of latency, but helps relieve a lot of strain from the PCB.
> Also without strong RTTs, helps to daily 1.6v and more
> Not to forget that the dimms stay cooler. Anything variable, as long as tamed is a good thing
> Frequency and voltage. It allows hardware to be pushed beyond it's limits
> 
> The little 0.2ns (you actually have to fight a lot for that much)
> Are dealable with, as you can use more voltage and so lower timings + relieving a bit of strain
> 
> 
> The reduction of multi is because of the hardcoded EDC *Fuse* Limit, which actively Package throttles back
> Sadly even my gimped lottery unit, only has to follow the 120/125A 5600X Fuse Limit
> 
> Don't forget that EDC will eat into the powering budget
> Which is why users see better boosting on less FCLK
> My advice is again, highest possible negative CO and added vcore offset, to cover for it
> This fakes telemetry and allows more powerdraw, but fakes the wattage and ampere results
> 
> Do NOT use any offset with CTR !


Yeah, I understand how to tune CO/pbo and have good results. But my comment is more towards my previous comments I made about the MSI ace vs dark hero and their respective milti-core pbo scores. With 1.1.0.0 patch C (or D, hard to tell which it is), AMDs own motherboard edc limits report a limit of 215, which is definitely interesting. Tuning edc to 210 manually on that board provided the best results for milti-core testing while retaining a single core boost score:









Meanwhile, the dark hero on 1.1.8.0 (bios 3003) maxes out at an all core score of ~ 12200, with motherboard limits being the typical 200 edc.

This score advantage is seen up and down the entire milti-core score realm. So either some division of edc is taking place for every n threads or there is some other factor in play reducing performance.

But again, what agesa do you recommend for the best fclock performance? I see no degradation in performance (I actually see quite a performance benefit) when using 4000/2000, but those pesky whea 18 bus/interconnect correctable errors just pop their head up.


----------



## KingEngineRevUp

I got a new 4X 8GB of sticks, any recommendations on settings I could change to lower my latency? Or have I reached a pinnacle for 4X sticks? I know it's harder to OC 4 sticks together.


----------



## Veii

FleischmannTV said:


> Lord @Veii,
> 
> is tCKE 9 @ 3800 dependent on 6/3/3 | 40-20-20-20 | 3-3-15 or can you run it independent from RTT, CAD Bus DrvStr and Setup?


Oh don't start this title trend too 
I dont understand who got up with that trolling 

tCKE works on everything, but if the higher wakeup power is enough, has to be seen
RTTs do introduce an own powerdown
tCKE works as another powerdown
And RTT_WR does dynamically adjust

It can make problems for some RTTs, but it alone works on every set
Just some RTTs will behave differently and can cause issues (different synced powerdown types)


jomama22 said:


> Yeah, I understand how to tune CO/pbo and have good results. But my comment is more towards my previous comments I made about the MSI ace vs dark hero and their respective multi-core pbo scores. With 1.1.0.0 patch C (or D, hard to tell which it is), AMDs own motherboard edc limits report a limit of 215, which is definitely interesting. Tuning edc to 210 manually on that board provided the best results for milti-core testing while retaining a single core boost score:
> View attachment 2484623
> 
> 
> Meanwhile, the dark hero on 1.1.8.0 (bios 3003) maxes out at an all core score of ~ 12200, with motherboard limits being the typical 200 edc.
> 
> This score advantage is seen up and down the entire multi-core score realm. So either some division of edc is taking place for every n threads or there is some other factor in play reducing performance.
> 
> But again, what agesa do you recommend for the best fclock performance? I see no degradation in performance (I actually see quite a performance benefit) when using 4000/2000, but those pesky whea 18 bus/interconnect correctable errors just pop their head up.


I think i wrote it already
Manufactures cheat in the hidden
By different scalar settings and different per default boost overrides
EDC FUSE limit is not bypassable with the motherboard-limit flag
It does lift the normal EDC limits, but there are different ones that are hardcoded

Also if CO is predefined , then the scores will be better 
You would need to compare them one to one with CTRs readout for CPU telemtry and predefined CO values (readout/diagnosis)

Zentimings does report the SMU and table version
SMU 56.30 , AGESA 1.1.0.0A is fine SMU 56.30 had no FCLK limit
SMU 56.44 also has no limit AGESA 1.2.0.0 (1.1.9.2v2 pre release of 1.2.0.0)
Every except 56.34 is fine
Please check the public Zen RamOC sheet to see what people run

Anything higher than 1.1.0.0 Patch D, SMU >56.36 is fine 
Has the cache boost but also its problem's
56.30 lacks the newer ABL but was the most stable one. 
Sadly neither of the newer boards , Unify-X or Crosshair lineup, ever got it


----------



## Yviena

Ummmh what's up with my L3 cache scores this is on a fresh installed windows, re-flashed 1.61 bios, the only thing i have changed is dialed in my stable RAM overclock and SOC/VDDP/VDDG voltages, everything else is either on auto, or untouched.


----------



## FleischmannTV

Veii said:


> Oh don't start this title trend too
> I dont understand who got up with that trolling


Sorry, it was not intended as trolling. 😮


----------



## thigobr

I am trying to tune and stabilize this 2x32GB Crucial 3600MHz kit...

I have been reading this thread and all the good comments around GDM/2T/RTTs.

So far I got this, backing up to 2T instead of 1T GDM gave me better results. It's stable 4h TM5 (I will still leave overnight at some point)...

But the DIMMs are warm reaching more than 55°C while under TM5 and my case is well ventilated. I wonder if working with tCKE/Power Down or adjusting RTTs would bring a temperature reduction in this case.


----------



## Veii

jomama22 said:


> Focusing on the PBO stuff. MSI (at least the ACE and the 1.1.0.0 patch C (may be D)) seems to have a fuse limit of 215 amps, as edc defaults to such a 'motherboard' value in AMD's own pbo section in the bios. When using that motherboard, I was able to achieve better multicore results in r20 than anything possible with my Dark Hero I have installed atm, to the tune of 1-2%. Nothing huge, but just a genuine note.
> 
> I have also noticed that depending on how you set your pbo limits and voltages greatly varies your result. Doing any sort of voltage offset will destroy your milti-core pbo boosting. While it may help single thread boosting, it will compromise any milti-core pbo boosting efforts.
> 
> Also, I do not believe telemetry faking is doing much of anything with the current boost algo as I see only margin of error type differences between soc and cpu telemetry muckery compared to just leaving them alone (on both the MSI ace and dark hero).
> 
> Somthing else interesting to note, with the dark hero, I use the dynamic OC switcher. Currently, I am running bios 3003 which I believe is 1.8.0.0 patch C. Setting the switching amperage to 60 or below will always allow aida's l3 to report properly (1500 or so with my [email protected] 4800), above 60 and it will fall into the PBO trap of low l3 bandwidth. With the known fact that higher ecd will yield better l3 bandwidth under pbo and watching how aida behaves power wise (does a large inrush of power usage and then tampers off) I'm guessing that pbo was stalling at the same moment aida was trying to start forcing l3 writes (or reads), only allowing a core or two to become active in any meaningful way. Using higher edc limits (even beyond the "fuse" limit) must still be used in some predictive algorithm for pbo clocking.
> 
> Using dynamic oc switcher is interesting when it comes to L3 latency as it will always read 9.9ns. I believe this is using the pbo side of the oc switcher and now changing to all core as running a pure all core overclock seems to net me around 10.3-10.5ns (@4800).
> 
> I have also noticed negative clock stretching (clock shrinking? Lol) happening when messing with edc limits and dynamic oc switcher. Can get better single core r20 scores under pbo while reporting even less effective clock that at pure stock settings with no pbo. This can be done by raising edc to somthing like 245 when using dynamic oc switcher. Clock stretching begins to really start happening when I begin to lower edc below 140 or so.
> 
> Either way, just throwing this out there.


Thank you
Sorry,i totally skimped over this message
It appeared the same time i send the other one, while i read your bottom one only

I understand, but wonder about the Hybrid OC range
I wonder if Aida64 wasn't dual CCD aware on L3 , or something else is going on there on 1201
Till i get this Bios from ASRock (Biostar released it on the 5th of March btw) 
i will need couple of more weeks , to start testing

ASUS PBO and FMAX enchancer + latency/performance enchancers, which's shenanigans also MSI do
are sadly out of reach for me so far. Till i decompile their bios and replicate it ~ but that takes too much time and the priority of it is very low right now.
First "SpiHostAccessMacRomEn & SpiAccessMacRomEn" flag - needs to be found, and disabled
Probably a once perma solution and not something temporary ~ as AMD introduced an SPI flash lock.
On a bios lineup , that's very experimental (since 1200). Which is a plain . . . strange, move.
Probably to preserve bricks with an upcoming or "done" PSP Firmware update on 1201 , who knows.

After that is done, i'll stick my nose more into bios mods and feature porting. We need access to many of the low end features. It's a shame how enthusiasts are treated bios update after bios update, having less and less access to options
And after that is done, investigate more the random WHEA issue ~ if it isn't resolved by then.
WHEA #18 is a CPU voltage issue (vcore or loadlines)  , #19 is IO & chipset related.

It was known from Matisse, that limiting PBO and finetuning voltages - supplies less voltage to the chips
Powerbudget increases, and allcore frequency increases on lower frequency.
4900 can be run at 1450mV and also at 1375mV
4950 can be run at 1400mV and lower
5000 can be run at sub 1400 with higher input voltage (meaning negative CO to lower voltage requirements)

CO does telemetry faking, and positive CO plus negative vCore , result in the EDC FUSE limit to be hit faster
You should test what your absolute peak limits are on y-cruncher
Ignore the % usage readout, as the PBO limits you lift there, still are throttled on a 2nd stage after cache acceleration.
Sadly because more voltage is supplied by let's say EDC 400, the CPU will actively throttle back on "overvoltage"
Soo the TDC limit is to be used for such type of overvoltage limiting

What frequency are you looking at to report "lower frequency/higher frequency" ?
There is requested frequency which is "optimistic and upon boosting table borders"
and there is effective clock, which does not measure BLCK changes, and calculates IPC in post
Slower, but more accurate ~ but needs CPU Snapshot pooling to be really accurate


FleischmannTV said:


> Sorry, it was not intended as trolling. 😮


I know i know, just don't want from outside of the community people to think, that i only respond with such treatment and title. Or give people special treatment because of such
I mean it sounds funny and i feel honored, but please no


----------



## GribblyStick

@Veii
Not sure if it makes a difference but they are starting to roll out the resizeable bar Vbios updates, so maybe another thing to consider.

Asus:


Spoiler: Resizable Bar Asus 30 series



Version -
2021/03/30 10.9 MBytes
NVIDIA Resizable BAR flashing tool
This VBIOS update enables Resizable BAR technology, which gives a system’s CPU direct access to the entire GPU frame buffer. Multiple CPU to GPU transfers can be made concurrently instead of being queued, leading to a performance boost for memory-intensive games and workloads.

The tool can be used on all ASUS GeForce RTX™ 30 series graphics cards. Learn more from NVIDIA:
NVIDIA Resizable BAR blog: GeForce RTX 30 Series Performance Accelerates With Resizable BAR Support | GeForce News | NVIDIA
NVIDIA Resizable BAR BIOS update information: NVIDIA Resizable BAR Firmware Update Tool | NVIDIA

Name: RTX3090_V3.exe
Size: 11425856 bytes (10 MiB)
SHA256: 49F147AC5177C4BFB3A2DFF61073EF52BC27826BC82072AF9F243C44076FE4CC


----------



## jomama22

Veii said:


> Thank you
> Sorry,i totally skimped over this message
> It appeared the same time i send the other one, while i read your bottom one only
> 
> I understand, but wonder about the Hybrid OC range
> I wonder if Aida64 wasn't dual CCD aware on L3 , or something else is going on there on 1201
> Till i get this Bios from ASRock (Biostar released it on the 5th of March btw)
> i will need couple of more weeks , to start testing
> 
> ASUS PBO and FMAX enchancer + latency/performance enchancers, which's shenanigans also MSI do
> are sadly out of reach for me so far. Till i decompile their bios and replicate it ~ but that takes too much time and the priority of it is very low right now.
> First "SpiHostAccessMacRomEn & SpiAccessMacRomEn" flag - needs to be found, and disabled
> Probably a once perma solution and not something temporary ~ as AMD introduced an SPI flash lock.
> On a bios lineup , that's very experimental (since 1200). Which is a plain . . . strange, move.
> Probably to preserve bricks with an upcoming or "done" PSP Firmware update on 1201 , who knows.
> 
> After that is done, i'll stick my nose more into bios mods and feature porting. We need access to many of the low end features. It's a shame how enthusiasts are treated bios update after bios update, having less and less access to options
> And after that is done, investigate more the random WHEA issue ~ if it isn't resolved by then.
> WHEA #18 is a CPU voltage issue (vcore or loadlines)  , #19 is IO & chipset related.
> 
> It was known from Matisse, that limiting PBO and finetuning voltages - supplies less voltage to the chips
> Powerbudget increases, and allcore frequency increases on lower frequency.
> 4900 can be run at 1450mV and also at 1375mV
> 4950 can be run at 1400mV and lower
> 5000 can be run at sub 1400 with higher input voltage (meaning negative CO to lower voltage requirements)
> 
> CO does telemetry faking, and positive CO plus negative vCore , result in the EDC FUSE limit to be hit faster
> You should test what your absolute peak limits are on y-cruncher
> Ignore the % usage readout, as the PBO limits you lift there, still are throttled on a 2nd stage after cache acceleration.
> Sadly because more voltage is supplied by let's say EDC 400, the CPU will actively throttle back on "overvoltage"
> Soo the TDC limit is to be used for such type of overvoltage limiting
> 
> What frequency are you looking at to report "lower frequency/higher frequency" ?
> There is requested frequency which is "optimistic and upon boosting table borders"
> and there is effective clock, which does not measure BLCK changes, and calculates IPC in post
> Slower, but more accurate ~ but needs CPU Snapshot pooling to be really accurate
> 
> I know i know, just don't want from outside of the community people to think, that i only respond with such treatment and title. Or give people special treatment because of such
> I mean it sounds funny and i feel honored, but please no


All clock observation is using effective clocks for the same time frame (2000ms). 

With the asus board, fmax enhancer is disabled as well as any latency shenanigans, same with the msi board.


----------



## Yviena

Just curious but does setting EDC limit higher actually increase L3 performance, or is it just showing a higher number?


----------



## hsn

Why when use renoir, BGS become automatically Enable?
should i change BGS Disable?


----------



## adversary

I did put now RAM under custom watercooling also and temps are definitely better. Also I changed (to existing tuning I did so far on my RAM) just Tcke from Auto to 9. So I do not know reason which of these two changes contibuted, but so far, stress test do not crash at little higher RAM and FLCK frequency, and voltage requirement seems a little bit lower. But more testing would be needed.

Also, after some period of using my new AMD build, crakling sound and similar sound issues started and afterwards was happening sometimes during games. I did not notice performance drop, just sound issues. First I try to further raise SOC but it did not help. I lowered RAM and FLCK speed a little and problem was gone. But yesterday appeared again one time.

Is that BIOS issue or what it could be? I'm still on 1.2.0.0 AGESA. All works fine mostly, except that sound issues which happened (I do not know source of problem, or it is random problem).

Soon I belive for my motherboard will be released AGESA 1.2.0.2. Did some of you start to use it? I would like to hear is there improvements and some specific fixes?


----------



## lmfodor

TexasAVI03 said:


> Thank you. Well that answers that. I think this is our major issue. From AMD.com folks getting processors RMA'd (screaming never had the issue with my Intel...) to this group with memory clock issues to the graphics card forum guys complaining about new cards & relating it to HWiNFO64 & AIDA64 being the cause to the Windows forum guys blaming 20H2 recent update.
> 
> On my ASUS mobo I have done this:
> If you "Disable" DRAM Power Options under AiTweaker>DRAM Timing Control>Power Down Enable
> Also located in Advance>AMD OC'ing>AMD OC'ing>DDR & Infinity Fabric Frequency/Timings>DDR Frequency & Timings>DRAM Controller Configuration>DRAM Power Options: "Disable"
> 
> IMO this has helped. However, I have changed several other board voltage tweaks, to ensure at idle & core sleep the voltage doesn't error too low then sudden boost spikes do not trigger the Kernel-Power event. I have logged these for 2 months since building this new PC and compared to my ASUS mobo + 3900X with similar Corsair Memory.
> 
> Also, as stated previously, Windows in Power Mode Performance with all power-saving items off.
> 
> If you research that error it will take you way back over the last 10-15 years. It is a terrible rabbit hole of *** that the industry just let go for all these years...why?


Hi, I've never read about this setting and if It could avoid WHEA's errors. The other day I had to recover the BIOS values after a memory OC and although they all seemed to be there, the backup had not saved the c-states or the Power Supply Idle Controlset. So I immediately started having reboots and some WHEAs. I thought it was something from memory but no, just by modifying these settings I did not have any more restarts or WHEAs like months ago. As far as I know these are a must settings:

C-State set to "Disable"
Power Supply Idle Controlset to "Typical Current Idle”

What you indicate about DRAM Power Options: "Disable" should also be added to avoid WHEAs or restarts? I never read about it and if it have some implications in other aspects of Memory OC! Thanks 


Sent from my iPhone using Tapatalk Pro


----------



## zGunBLADEz

@Veii
ok i did a couple of more tests i manage to use a static overclock problem is i cant pass around that 1150-1200 L3 cache readings it will crash so 12 core and static overclock is non existent right (pbo aint a overclock to me) now which will cause all kind of crashes outside pbo.... even on idle and my 200+ and counting kernel panics which i know now are related to that.

so my workaround was to disable 2 cores so instead of 12 i have now 10.... i can do some overclock on it..I lost 1-2x (0.25x) notches in the multiplier need to restest again bcuz of the new bios "agesa fixes..."

Now my dilemma is that the stock cpu its not working as intended other than normal pbo itself which is automatic and this cpu should be overclockable as such as is advertized as such "overclockable" its an unlock cpu after all..like 42-43x (you can get to that l3 cache reading at those clocks need to test further) on all cores its unacceptable for all core overclock on the 5th series... pbo is with holding the performance on that aspect...

I bombarded again the L3 cache with 10 cores instead and 0 problems as long as it dont touch that 1150-1200 range cpu is ok

so i guess this issue only plagues 5900x+ and up bcuz 5600&5800x dont get there
now whos to blame asus or amd its my question im more inclined to amd this time



Spoiler











tested drooping fclk below 1900 and is not that either trust me if the cpu cannot do 1900fclk it would be rma.. i dont want to do a rma on something im going to experience on another cpu i can even get a worst sample so who knows...


also i notice on auto/pbo this "LEGENDARY AMD BUG is back"
i dont know if you remember the previous 1st ryzen xfr bug


Spoiler










its back and not such extreme case but i manage to trigger it on cb15 lol
======
another bombardment of l3 cache
47x all cores
100ms x 500 times


Spoiler















this is how aida use the cpu (on pbo) to do her readings i read you mention it a few posts back


Spoiler







}


----------



## jomama22

zGunBLADEz said:


> @Veii
> ok i did a couple of more tests i manage to use a static overclock problem is i cant pass around that 1150-1200 L3 cache readings it will crash so 12 core and static overclock is non existent right (pbo aint a overclock to me) now which will cause all kind of crashes outside pbo.... even on idle and my 200+ and counting kernel panics which i know now are related to that.
> 
> so my workaround was to disable 2 cores so instead of 12 i have now 10.... i can do some overclock on it..I lost 1-2x (0.25x) notches in the multiplier need to restest again bcuz of the new bios "agesa fixes..."
> 
> Now my dilemma is that the stock cpu its not working as intended other than normal pbo itself which is automatic and this cpu should be overclockable as such as is advertized as such "overclockable" its an unlock cpu after all..like 42-43x (you can get to that l3 cache reading at those clocks need to test further) on all cores its unacceptable for all core overclock on the 5th series... pbo is with holding the performance on that aspect...
> 
> I bombarded again the L3 cache with 10 cores instead and 0 problems as long as it dont touch that 1150-1200 range cpu is ok
> 
> so i guess this issue only plagues 5900x+ and up bcuz 5600&5800x dont get there
> now whos to blame asus or amd its my question im more inclined to amd this time
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tested drooping fclk below 1900 and is not that either trust me if the cpu cannot do 1900fclk it would be rma.. i dont want to do a rma on something im going to experience on another cpu i can even get a worst sample so who knows...
> 
> 
> also i notice on auto/pbo this "LEGENDARY AMD BUG is back"
> i dont know if you remember the previous 1st ryzen xfr bug
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> its back and not such extreme case but i manage to trigger it on cb15 lol
> ======
> another bombardment of l3 cache
> 47x all cores
> 100ms x 500 times
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2484730
> 
> 
> 
> 
> this is how aida use the cpu (on pbo) to do her readings i read you mention it a few posts back
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> }


You said earlier this only occurs with the newest bios you tested yeah? Didn't have this issue before on the older bios? If that's the case, then I would just use the older bios. Unless there is some critical fix you need with the newer bios', then just keep the old one.

I tested this issue on my 5950x @ 4.8, netting 1480-1520 on l3 read and do not have this issue on bios 3003.


----------



## zGunBLADEz

Little more testing... rolled back all way to 1202.... have to use bios flashback as i cant do it from bios itself...

So now i get it... amd created this issues to benefit their pbo which included those panic kernels and usb issues..
48/47x 1000 times bombardment @ 100ms












jomama22 said:


> You said earlier this only occurs with the newest bios you tested yeah? Didn't have this issue before on the older bios? If that's the case, then I would just use the older bios. Unless there is some critical fix you need with the newer bios', then just keep the old one.
> 
> I tested this issue on my 5950x @ 4.8, netting 1480-1520 on l3 read and do not have this issue on bios 3003.


what mobo?
never mind the dark right? so for me that bios would be 1401 then i would flash back that one one notch more lol that one i havent try yet :/


----------



## Kitsune2431

Hey. Big beginner here. I tried overclocking my 3200c14 32gb dual ranked b-die kit. A lot of terminology escapes me and i admit i was too lazy to read whole thread in search of information.

Here are my current timings (soc is 1.075 and vddp, both vddg are 0.9 in bios, but zentimings show way lower numbers)









I ended up with these timings by combination of auto and copying @Veii suggestions on page 314/315. Changed them one by one with auto voltages and changed stuff if it didn't post or instant errors and then i lowered all the voltages.

For now i only tested 11h in tm5 1usmus config with 0 errors. I plan to do more tests from github ram oc guide, but i wonder if anything looks off and should i change something. By off i mean like tcke rule that was mentioned by Veii a page ago. I want to focus more on stability than performance. I checked performance and got 10%+ more fps in cod warzone, so i'm satisfied. Do you guys have some recommendations or should i leave it as it is, if it turns out to be stable?


----------



## jomama22

zGunBLADEz said:


> Little more testing... rolled back all way to 1202.... have to use bios flashback as i cant do it from bios itself...
> 
> So now i get it... amd created this issues to benefit their pbo which included those panic kernels and usb issues..
> 48/47x 1000 times bombardment @ 100ms
> View attachment 2484774
> 
> 
> 
> 
> what mobo?
> never mind the dark right? so for me that bios would be 1401 then i would flash back that one one notch more lol that one i havent try yet :/


Yeah, I would only ever use bios flashback anyway. Just feels cleaner to me, lol.

It's possible that is the root cause but it's all speculation at the end of the day. And tbf, you are creating quite an odd scenario to cause the issue. It could be insofar as to an issue with aida itself. If you aren't having issues anywhere else except when you do that (I'm guessing you ran r15 after doing your l3 hammering) then I would be inclined to believe it's just an odd big you found out how to exploit.

If I were you, I would just use the pc and see how it goes. Constantly recreating the issue in your specific test really doesn't show us any type on normal interaction.

If you were/are getting shutdowns outside of that case, then yeah, somthing to talk about.

Also, it does beg the question as to whether you memory or cpu oc's are stable and you aren't just finding a way to trigger the instability.


----------



## zGunBLADEz

jomama22 said:


> Yeah, I would only ever use bios flashback anyway. Just feels cleaner to me, lol.
> 
> It's possible that is the root cause but it's all speculation at the end of the day. And tbf, you are creating quite an odd scenario to cause the issue. It could be insofar as to an issue with aida itself. If you aren't having issues anywhere else except when you do that (I'm guessing you ran r15 after doing your l3 hammering) then I would be inclined to believe it's just an odd big you found out how to exploit.
> 
> If I were you, I would just use the pc and see how it goes. Constantly recreating the issue in your specific test really doesn't show us any type on normal interaction.
> 
> If you were/are getting shutdowns outside of that case, then yeah, somthing to talk about.
> 
> Also, it does beg the question as to whether you memory or cpu oc's are stable and you aren't just finding a way to trigger the instability.


Looking into my 200+ some kernel panics without wheas i got to recreate a similar scenario. I get the same kernel panics on event viewer like that.

I dont even have to bombard it with a few repeating clics would crash lol... but will pass rog bench stress test and ram tests 0 problems.. and run cbs all day long. But will have random/idle crashes followed by kernel panics with no wheas...


it does at idle as well the l3 cache reading can be read it so fast it aint funny and hit that number without you seeing some type of load/usage and get in to that magic number, problem is triggered at that specific cache reading speed... thats probably where this kernel panics with no wheas are coming from..

did you try the same way im doing? instead of just doing one read?
in the newest bios i can only use pbo. cant use musmus app bcuz it will eventually crash or do a kernel panic at idle or whenever it feels like... if i use an static overclock. its "only stable on the bioses where the L3 are that low or not "correct"" i have triggered at multiplier as low as 42/43x... it doesnt happen on 10cores on the new bioses bcuz it dont get into that l3 reads 1150-1200.. tho i managed to get 49/47x 12x cores on bios 1202 0 problems. but the l3 cache readings are not that high tho and cant boot at 3800&1900.. it doesnt happen on latest bios with pbo either bcuz amd have it literally capped around the 1000 read. I get 46.50x all cores pbo and L3 dont get even to the 1000s. But a lower static overclock would reach 1100-1200 no problems. So no musmus or static overclock bcuz of it. Can be sporadic and using the hybrid part maybe it took longer to manifest that way. But after 1803 clock tuner here got broken in the new bioses. That's when i swapped to try static overclocks from the bios thats when the kernel panics started.. So i noticed and start digging. Was using hybryd mode which mix pbo with the static oced.


1402 was a no go worst bios of the 4 that i can use.. fclk was horrible, ram as well.. i get better infinity fabric 1900 on new bioses and ram overclock, but have that issue.. if you see this pic i can control those "crashes" at will and bombard as i please as long i dont hit that magic number. LoL










it aint the ram









i used this same kit on a few amd systems 1700/1800x/2700x and 8700k this kit is binned for 3933 on the 8700k

im debating to rma it.. problem is what if is not the cpu??


----------



## lmfodor

I’m happy to share this impressive results at least for me as a noob with the new memories that bought last week. This would not have been possible without the great daily help of RosaPanteren who was guiding me step by step with each value .. I know that there is still some sub-timing to go down but I am super satisfied and maintaining the normal voltage for these memories of 1.5, not really I wanted to take them to 1.55v






















Sent from my iPhone using Tapatalk Pro


----------



## jomama22

zGunBLADEz said:


> Looking into my 200+ some kernel panics without wheas i got to recreate a similar scenario. I get the same kernel panics on event viewer like that.
> 
> I dont even have to bombard it with a few repeating clics would crash lol... but will pass rog bench stress test and ram tests 0 problems.. and run cbs all day long. But will have random/idle crashes followed by kernel panics with no wheas...
> 
> 
> it does a stock as well, problem is triggered at that specific cache reading... did you try the same way im doing? instead of just doing one read?
> in the newest bios i can only use pbo. cant use musmus app bcuz it will eventually crash or do a kernel panic at idle or whenever it feels like... if i use an static overclock. its "only stable on the bioses where the L3 are that low or not "correct"" i have triggered at multiplier as low as 42/43x... it doesnt happen on 10cores on the new bioses bcuz it dont get into that l3 reads 1150-1200.. tho i managed to get 49/47x 12x cores on bios 1202 0 problems. but the l3 cache readings are not that high tho and cant boot at 3800&1900.. it doesnt happen on latest bios with pbo either bcuz amd have it literally capped around the 1000 read. I get 46.50x all cores pbo and L3 dont get even to the 1000s. But a lower static overclock would reach 1100-1200 no problems. So no musmus or static overclock bcuz of it. Can be sporadic and using the hybrid part maybe it took longer to manifest that way. But after 1803 clock tuner here got broken in the new bioses. That's when i swapped to try static overclocks from the bios thats when the kernel panics started.. So i noticed and start digging. Was using hybryd mode which mix pbo with the static oced.
> 
> 
> 1402 was a no go worst bios of the 4 that i can use.. fclk was horrible, ram as well.. i get better infinity fabric 1900 on new bioses and ram overclock, but have that issue.. if you see this pic i can control those "crashes" at will and bombard as i please as long i dont hit that magic number. LoL
> 
> View attachment 2484793
> 
> 
> it aint the ram
> View attachment 2484794
> 
> 
> i used this same kit on a few amd systems 1700/1800x/2700x and 8700k this kit is binned for 3933 on the 8700k
> 
> im debating to rma it.. problem is what if is not the cpu??


Yeah, could possibly just be a bad cpu. I believe you said you had tried to disable c states and df states if I remember correctly? Not as though that should matter on an all core oc as most low c-states are disabled by default in that case.

If you are getting idle reboots, even at 100% stock (full defaults in bios as well) I would gander it's probably a cpu issue.

I would say though that it very well could be the mobo being bad. This dark hero gives me idle issues when using pbo with c-states enabled if I have any of the digi+ parameters changed from default beyond the core current capability.

My msi ace does not exhibit any of those issues though and runs the chip cooler to boot.

If ctr gets to a point where it makes sense to use over co/pbo, I'll probably just ditch this dark hero.


----------



## wden

Hello,

It seems this is the best OC I can achieve. I've tried different combinations and recommendations both from this thread and the Zen RAM Overclocking spreadsheet to no avail. I have also tried raising and lowering VSOC, VDIMM, VDDG CCD/IOD, VDDP with no luck.

I'm also unable to POST when attempting 1900IF. I bought this RAM kit back in 2018, not sure if that affects anything.

The best I have been able to get is this. Could it be my motherboard that's causing issues? RAM getting too hot? Any suggestions or ideas to possibly lower the timings or reach 1900IF would be appreciated? Thanks.


----------



## Veii

Kitsune2431 said:


> For now i only tested 11h in tm5 1usmus config with 0 errors. I plan to do more tests from github ram oc guide, but i wonder if anything looks off and should i change something. By off i mean like tcke rule that was mentioned by Veii a page ago. I want to focus more on stability than performance. I checked performance and got 10%+ more fps in cod warzone, so i'm satisfied. Do you guys have some recommendations or should i leave it as it is, if it turns out to be stable?


tRC drop to 40
tRFC 320-204-151
tRDWR 12 , tWRRD 2

You could exploit some more stuff 

Next step is RTT 633
with 60-20-40-20
and higher VDIMM @ tCKE 9 , SETUP Time 3-3-15
or you ignore it and go for FCLK

Compare both with 4 Aida64 runs
or 2 SiSoftware Sandra - Multi-Core Efficiency runs


lmfodor said:


> I know that there is still some sub-timing to go down but I am super satisfied and maintaining the normal voltage for these memories of 1.5, not really I wanted to take them to 1.55v





Spoiler: Purple 🧙‍♂️ 














tRP 12 won't run sub 1.54v, but it will be required in the future - if you want to tighten things down further


jomama22 said:


> Yeah, could possibly just be a bad cpu. I believe you said you had tried to disable c states and df states if I remember correctly? Not as though that should matter on an all core oc as most low c-states are disabled by default in that case.


That's the logical thinking
DF States still function , and cause overboost
Disable DF_States, normal ones can and should stay


----------



## gabian

Any Advices on improving the RAM ?


----------



## jomama22

@Veii here's an odd question for you. Do you know what causes soc power to skyrocket (and I mean, to like 17-18w idle) when manually setting soc/vddg voltages? When left to their own on auto, at idle and under r20 benches, the have no problem staying sub 10w. C states not df states touches this as no matter that setting, behavior stays the same. I had also tried disabling soc/uncore oc mode to no avail. 

Really just looking at how to grab to more pbo headroom.


----------



## Tobiman

gabian said:


> View attachment 2484815
> 
> 
> Any Advices on improving the RAM ?


That looks pretty solid. Here's mine. Is your mem OC stable?


----------



## TimeDrapery

Ramad said:


> I did not post anything of my own making.


Then do so... Or go away


----------



## hazium233

I have been running a 2700X on a B550 Gaming Edge Wifi while I was waiting to get a Zen3, and just to see how it would work.

I had been going along nicely until I decided to dust off Linpack Xtreme 1.1.1 and see how it would work. At 10GB problem size, the mouse disappeared and the system became unresponsive in the first loop, even though cursor on window blinked and hwinfo would still update. This was at first with a 4.1 AC setting I was testing. No big deal, reverted it to regular Precision Boost, and it did it again.

Ok maybe the ram OC was bad. Same thing. Long story short, did it all the way down to 2133MT/s. Thought it could be core instability or VRM weirdness, or just that it was the unsupported cpu. Tried LinX 0.7 and ran 5 loops easily. Tried Linpack Xtreme 1.1.5 and it did the same thing. But I noticed something odd about the memory allocation.

For the 35000 problem size, LinX shows memory amount as 9374 MiB, which is near 10GB.

Linpack Xtreme (either 1.1.1 or 1.1.5) listed 1210769504... which I believe is in bytes and works out to a whole 1154.7 MiB.

I compared the 2GB through 10GB sizes in Linpack Xtreme to LinX by entering problem size manually and letting the latter configure the memory. Pic below.









At 2GB or 15825 problem size, the difference between the programs seems to be only 13.1 MiB. Incidentally, I could pass that one in Xtreme. I am on Windows 20H2.

I noticed in an older screenshot, KedarWolf passed with the odd memory allocation, so I don't know if that is really to blame for my problem. I might have to bring out the X370-F and try on that. The ram was more or less set similar to Stilt's Safe preset, and that had done some mprime large FFT for an hour, y cruncher two loops, and Karhu at 1.31V dimm (for the hell of it), and had passed TM5 1usmus 20 cycles several times at regular 1.35V and same SOC settings.


----------



## gabian

Tobiman said:


> That looks pretty solid. Here's mine. Is your mem OC stable?
> View attachment 2484840
> View attachment 2484841


My OC is stable tm5 extreme anta, hci and 24h karhu run ( don’t have screen now)

Here is the aida


----------



## MyComputerIsDying

Veii said:


> Dual rank 2x16 do end up as a better option for OC, while being an equal option to 4 dimms - as for maximum bandwidth
> (chipset interleaving and rank interleaving - are the keywords here)
> 
> They are expensive, but so are also 4 dimms
> For me at least, they cost the same thing.
> Manufactures charge by capacity which is correct. Some retailers overcharge by demand, which is not correct
> 
> Currently i do have my eyes on the BLM2K8G44C19U4B
> Which are also 4400-19-19-19 dimms, but at 1.4v instead of 1.45v like the Vipers
> They do cost 60$ more tho and where once for 170 instead 180€
> 
> The reason i want them aside from the better binning, is the A3 PCB
> But it's still a conflicting decision because of the high b-die price like the old days (180-220€ per 16gb kit)
> And also questionable, when AM4 is soon EOL , same for DDR4
> 
> I can't help you, except advice to go for 2x16 instead of 4x8
> Sadly there are rarely any "great" 2x16, like tRCD 15 3600 kits, or 4000 tRCD 18 or 19 kits
> soo there is not really a recommendable option out there
> But typical 16-16-16 16gb dimms are oke'ish , they are at least not bad ~ but you have to luck out on the PCB
> It could be B1 or B2 on 3600
> Only B2 is guaranteed at 4100+ rated dimms - where Vipers are A0 (B0) on 4000 , and only A2/B2 at 4400+
> 
> Well what you end up with, 4x8 or 2x16 is luck based - and monetary
> But 2x16 is a better option for OC - IF there are good sets out there
> From the price perspective, both options should cost equal ~ equally much


thank you so much for elaborating deeply on this.
well, this will be fun! going to need to spend 3x what the plan was do meet the goal 
I will start looking at some of those crucial kits, I've never knew of the a#/b# until I used the ryzen memory tool and saw it was a thing. irc the dominators are always overpriced and I don't now about their pcb.

I forgot to even look at any >3600 kits because I was so focused on getting something identical. Also remembering I was trying to run a 1:1 chipset and ram.

genuinely torn, awesome kit just not available anymore and I can't add another 2x8GB to try and save money (if i plan on keeping an overclock).


----------



## Veii

jomama22 said:


> @Veii here's an odd question for you. Do you know what causes soc power to skyrocket (and I mean, to like 17-18w idle) when manually setting soc/vddg voltages? When left to their own on auto, at idle and under r20 benches, the have no problem staying sub 10w. C states not df states touches this as no matter that setting, behavior stays the same. I had also tried disabling soc/uncore oc mode to no avail.
> 
> Really just looking at how to grab to more pbo headroom.


It's variable FCLK / MCLK & SOC
Something i bother AMD's engineers a lot and get silently ignored
Something nobody wants to talk about - the lack of functional APBDIS aka variable FCLK
Nothing you can do - till somebody figures out the correct MSR SME/SMU Mailbox code to override a "peak" memory frequency

Wasted energy for nothing *
* i know it brings PCIe stability, but still ~ annoying
It's 30W/14A for me , from SOC 
Soo extend the stock boosting limits, else you will lose boost performance by doing any MemOC
It eats strongly into the powerbudget (125W, 65W CPU , 30+ W the fabric and IMC) ~ lol, thank you AMD


----------



## paih85

Kitsune2431 said:


> Hey. Big beginner here. I tried overclocking my 3200c14 32gb dual ranked b-die kit. A lot of terminology escapes me and i admit i was too lazy to read whole thread in search of information.
> 
> Here are my current timings (soc is 1.075 and vddp, both vddg are 0.9 in bios, but zentimings show way lower numbers)
> View attachment 2484780
> 
> 
> I ended up with these timings by combination of auto and copying @Veii suggestions on page 314/315. Changed them one by one with auto voltages and changed stuff if it didn't post or instant errors and then i lowered all the voltages.
> 
> For now i only tested 11h in tm5 1usmus config with 0 errors. I plan to do more tests from github ram oc guide, but i wonder if anything looks off and should i change something. By off i mean like tcke rule that was mentioned by Veii a page ago. I want to focus more on stability than performance. I checked performance and got 10%+ more fps in cod warzone, so i'm satisfied. Do you guys have some recommendations or should i leave it as it is, if it turns out to be stable?


woww..ur vdimm super low @3800c16. fully stable?


----------



## lmfodor

Veii said:


> tRC drop to 40
> tRFC 320-204-151
> tRDWR 12 , tWRRD 2
> 
> You could exploit some more stuff
> 
> Next step is RTT 633
> with 60-20-40-20
> and higher VDIMM @ tCKE 9 , SETUP Time 3-3-15
> or you ignore it and go for FCLK
> 
> Compare both with 4 Aida64 runs
> or 2 SiSoftware Sandra - Multi-Core Efficiency runs
> 
> 
> 
> Spoiler: Purple
> 
> 
> 
> 
> View attachment 2484812
> 
> 
> 
> tRP 12 won't run sub 1.54v, but it will be required in the future - if you want to tighten things down further
> 
> That's the logical thinking
> DF States still function , and cause overboost
> Disable DF_States, normal ones can and should stay


Hi Veil! I just see your screenshot edited. I will fix this values.. I guess the latency is too low for this settings. As this memory comes with an XMP “optimized” with a default VDIMM value to 1.50, I’d prefer to stay on this value to not increase so much the temps . But if you say that tRP 12 won’t run sub 1.54 I’d have to change the tRP or try to rise the VDIMM to 1.54 as Max and see how it behave. I live in Argentina and it’s summer now so the air conditioner cools very well but it freeze the entire room! So I’m looking for a balance between performance and low latency, and keeping a relative cool ambient. I have a fan over the memories that low the temps very well

Please let me know if you see another thing to improve. Thanks!
Best Martin 


Sent from my iPhone using Tapatalk Pro


----------



## Ramad

TimeDrapery said:


> Then do so... Or go away


LOL....What?


----------



## adversary

@Veii 
Hello. I did try number of things you suggested last time, and fixed some things you told me. But still I lack info and knoweledge what exactly I should do further, as I can't get 3800/1900 stable in MemTest5 (1usmus_v3)
Also I read what you suggest to others and try such things.

Picture I attached is what I did try today - I upped SOC to 1.175 from 1.12.
I did try MT5 now with SOC 1.175, it did not show any error after cycle 1, but during cycle 2 it just goes black screen and rebooted.
At SOC 1.12, it did number of errors - and they were : 0,4,10,14

And I did try RAM voltage from 1.55V to 1.6V, nothing seems to help.

Same configuration, but run at 3733/1866 never get errors in MT5 (but sometimes, randomly, it seems I get some crakling sound in games for a moment)..

I'm still on 1.2.0.0 AGESA. I did not try 1.2.0.1 Beta Patch A which is available for my motherboard now. Perhaps soon 1.2.0.2 will be available so maybe I should than try again.
But until than I would like to try to get 3800/1900 stable and with good latency, or if not possible on current BIOS, than 3733/1866 fully tuned with best latency I can get.


I will provide you additional information so you can get best information on my system (and maybe correct me if some of these things are mistakes).

I run with PBO now plus +offset to core voltage. Found sweet spot for added voltage (beyong that additional heat will negate any benefit from added voltage). I'm on custom EKWB watercooling so temperatures are really good overall (and lower temps are, CPU will always boost more under load). RAM is also watercooled.

Advanced\AMD CBS\NBIO Common Options\SMU Common Options\DF Cstates ----------- I disabled this (as I found you suggested that for another user).

I did fix CLDO VDDP to 0.9V as you suggested. However, I can't find CPU VDDP in BIOS, or at least, it is not under that name. You can see motherboard name in attached picture.

Setting tCKE at 9, seems to helped much with stability, compared to Auto (which is 1 I think). Even 3733/1866 would not be stable without it.

CsOdtDrvStr - I can't raise it at 40, it won't work, I just get stuck with black screen before BIOS load (maybe it would be possible with some other overall configuration, but with this one seems not).

Did try AddrCmdSetup, CsOdtSetup, CkeSetup timings as 3 3 15 as I seen you suggest - run immidiately into problems. Will not boot into Windows, but show error message and return me to BIOS. Than BIOS freeze.


I have no idea what to try from this point on, I would need to know what exactly to fix.

If you belive that newer AGESA would help, I can wait for it, as 3733/1866 at this moment works well for my needs. If we can't get 3800/1900 to work at this moment let me know, no problem, in that case lets just try to tune further 3733/1866 for best latency and stick with it for some time, and try again in future with newer AGESA. However if inability to get 3800/1900 is pure due to my mistakes, let me know what to do and I will try to make it work.
I asked myself if maybe my RAM is bad bin and do not like higher speed, but again, it is only jump from 3600 to 3800, should not be problem for new B-Die kit I belive.

If issue is with tRFC (2 & 4) or tRDRDSCL and tWRWRSCL, it would be pity if I have to raise them, as lowering these timings indeed helped with RAM speed and latency.


----------



## Taraquin

Input on my settings?

Karhu i stable, I get rare error 6 (too high soc voltage?) after 5-10 cycles in TM5 usmus. Infinity fabric seems unstable if I lower soc or iod-voltage, I got random reboots when both where 0.02V lower. CPU-clock is stable, currently running [email protected] Any input of what to change, improve etc? The B-die is a ****ty bin btw and due to GPU sending hot air straight at it anything above 1.45V tends to be unstable.


----------



## Kitsune2431

paih85 said:


> woww..ur vdimm super low @3800c16. fully stable?


I don't know yet. I only tested 11h tm5 1usmus config. Yesterday i tried timings suggested by @Veii and i needed more vdimm to even post. Tbh i set it to 1.45 when i started overclocking, but i forgot to set it back when my profiles disappeared after cmos reset and mobo set it to 1.35 and it worked, so i left it like that.

With new timings i had 4 errors in 3h with 1.4 vdimm and 1 error in 4h with 1.43vdimm. Currently went back to my old vdimm, trc and trfc and only left new trdwr and twrrd, because my dimm temps are already ~57C with 27C ambient and while mining to simulate gaming. I don't want them to end up being unstable in summer, so i think i won't tighten them down.

I also tried rtt, setup time and tcke that Veii suggested and got very similar results in aida, but latency was very inconsistent. Even 0.5ns more than normal, so i went back to auto.

My initial goal was 3800c16 xmp'ish. Performance increase is around 10-20% in game, so i'm very satisfied. I just hope these settings will pass all tests. Thanks for suggestions. Will ask for help if they end up erroring out and i can't find quick fix.


----------



## scosey

My IOD hates high voltages and runs stable with the values shown and only 11W fully loaded. vDIMM is high -> 1.55V but they stay surprisingly cool at 48°C, no WHEAs whatsoever, I only start get them with FCLK 2000.

GDM on/1T still results in higher bandwith with over 57000MB/s Read but latency is higher and less consistent. I also noticed that single CCD has overall lower bandwith, not just the write speeds. Dual CCD CPUs easily reach 59000MB/s+ Read with worst timings.

My previous 5950x generated WHEAs at FCLK 1900 and the IOD required much higher voltages to get rid of them and limiting my boost clocks. That Chip I got shortly after launch wasn't even stable on default settings and required positive CO values of +5 on two cores and only 5 others ran stable at -10.

This 5800x is stable with -30 on 5 Cores / -26 on 2 Cores / -16 on 1 core

Maybe I just got lucky or the newer chips are simply better.










This is inside an Ncase M1 and the heat from the 3090 is a non issue as all 5 fans push the hot air outside at the bottom and the left side of the case and it helps keeping the sticks cool as they are being cooled by the air being pulled in from the top and the right side of the case.










Any tips go get this thing below 52ns? GDM off/1T seems impossible.


----------



## jomama22

Veii said:


> It's variable FCLK / MCLK & SOC
> Something i bother AMD's engineers a lot and get silently ignored
> Something nobody wants to talk about - the lack of functional APBDIS aka variable FCLK
> Nothing you can do - till somebody figures out the correct MSR SME/SMU Mailbox code to override a "peak" memory frequency
> 
> Wasted energy for nothing *
> * i know it brings PCIe stability, but still ~ annoying
> It's 30W/14A for me , from SOC
> Soo extend the stock boosting limits, else you will lose boost performance by doing any MemOC
> It eats strongly into the powerbudget (125W, 65W CPU , 30+ W the fabric and IMC) ~ lol, thank you AMD


Yeah, figured as much. Thanks!



adversary said:


> @Veii
> Hello. I did try number of things you suggested last time, and fixed some things you told me. But still I lack info and knoweledge what exactly I should do further, as I can't get 3800/1900 stable in MemTest5 (1usmus_v3)
> Also I read what you suggest to others and try such things.
> 
> Picture I attached is what I did try today - I upped SOC to 1.175 from 1.12.
> I did try MT5 now with SOC 1.175, it did not show any error after cycle 1, but during cycle 2 it just goes black screen and rebooted.
> At SOC 1.12, it did number of errors - and they were : 0,4,10,14
> 
> And I did try RAM voltage from 1.55V to 1.6V, nothing seems to help.
> 
> Same configuration, but run at 3733/1866 never get errors in MT5 (but sometimes, randomly, it seems I get some crakling sound in games for a moment)..
> 
> I'm still on 1.2.0.0 AGESA. I did not try 1.2.0.1 Beta Patch A which is available for my motherboard now. Perhaps soon 1.2.0.2 will be available so maybe I should than try again.
> But until than I would like to try to get 3800/1900 stable and with good latency, or if not possible on current BIOS, than 3733/1866 fully tuned with best latency I can get.
> 
> 
> I will provide you additional information so you can get best information on my system (and maybe correct me if some of these things are mistakes).
> 
> I run with PBO now plus +offset to core voltage. Found sweet spot for added voltage (beyong that additional heat will negate any benefit from added voltage). I'm on custom EKWB watercooling so temperatures are really good overall (and lower temps are, CPU will always boost more under load). RAM is also watercooled.
> 
> Advanced\AMD CBS\NBIO Common Options\SMU Common Options\DF Cstates ----------- I disabled this (as I found you suggested that for another user).
> 
> I did fix CLDO VDDP to 0.9V as you suggested. However, I can't find CPU VDDP in BIOS, or at least, it is not under that name. You can see motherboard name in attached picture.
> 
> Setting tCKE at 9, seems to helped much with stability, compared to Auto (which is 1 I think). Even 3733/1866 would not be stable without it.
> 
> CsOdtDrvStr - I can't raise it at 40, it won't work, I just get stuck with black screen before BIOS load (maybe it would be possible with some other overall configuration, but with this one seems not).
> 
> Did try AddrCmdSetup, CsOdtSetup, CkeSetup timings as 3 3 15 as I seen you suggest - run immidiately into problems. Will not boot into Windows, but show error message and return me to BIOS. Than BIOS freeze.
> 
> 
> I have no idea what to try from this point on, I would need to know what exactly to fix.
> 
> If you belive that newer AGESA would help, I can wait for it, as 3733/1866 at this moment works well for my needs. If we can't get 3800/1900 to work at this moment let me know, no problem, in that case lets just try to tune further 3733/1866 for best latency and stick with it for some time, and try again in future with newer AGESA. However if inability to get 3800/1900 is pure due to my mistakes, let me know what to do and I will try to make it work.
> I asked myself if maybe my RAM is bad bin and do not like higher speed, but again, it is only jump from 3600 to 3800, should not be problem for new B-Die kit I belive.
> 
> If issue is with tRFC (2 & 4) or tRDRDSCL and tWRWRSCL, it would be pity if I have to raise them, as lowering these timings indeed helped with RAM speed and latency.
> 
> 
> 
> 
> 
> View attachment 2484886


Should probably tune up tRFC to like 252 at minimum, tRCDRD to 15, tRAS to 29, and procODT to 40 and test for stability. If that works, then try to tune stuff back down one by one.


----------



## lmfodor

Veii said:


> tRC drop to 40
> tRFC 320-204-151
> tRDWR 12 , tWRRD 2
> 
> You could exploit some more stuff
> 
> Next step is RTT 633
> with 60-20-40-20
> and higher VDIMM @ tCKE 9 , SETUP Time 3-3-15
> or you ignore it and go for FCLK
> 
> Compare both with 4 Aida64 runs
> or 2 SiSoftware Sandra - Multi-Core Efficiency runs
> 
> 
> 
> Spoiler: Purple
> 
> 
> 
> 
> View attachment 2484812
> 
> 
> 
> tRP 12 won't run sub 1.54v, but it will be required in the future - if you want to tighten things down further
> 
> That's the logical thinking
> DF States still function , and cause overboost
> Disable DF_States, normal ones can and should stay


@Veii
I read your notes. This is how I have my timings now:








And this is your notes over my previous timings








I think that I should change tWRRD to 3 instead of 7, and tRDWR to 10 instead of 8, since your are adding 2, am I right?
I fixed tRC to 38 and tWR is still in. 14
That's how they look with the modifications you suggested:









When you draw a line between those values until the bottom I read “BURST = 8”. What is that, when should I change this value? Is the VDIMM voltage?
Anything else to fix / improve? Thanks for your great support!
Best Martin


Sent from my iPhone using Tapatalk Pro


----------



## PJVol

adversary said:


> DF Cstates ----------- I disabled this


Doing this your read and write copy bandwidth might decrease up to 1000 Mb/s.


----------



## lmfodor

PJVol said:


> Doing this your read and write bandwidth might decrease up to 1000 Mb/s.


Uh, I didn’t know that. So I should back to set DF states enabled? I just read here as a recommendation in conjunction or C-States. So enable is the way to to?


Sent from my iPhone using Tapatalk Pro


----------



## PJVol

Veii said:


> Wasted energy for nothing


Just curious, could it be thе same energy, that stretch clocks in my CB R20 MT run @IF2000, and doesn't in CPU-Z...
At least, 13-14W doesn't seem much
(Of course, @IF1900 both showed no stretching)


----------



## lmfodor

PJVol said:


> Just curious, could it be thе same energy, that stretch clocks in my CB R20 MT run @IF2000, and doesn't in CPU-Z...
> At least, 13-14W doesn't seem much
> 
> View attachment 2484929


Ok, but about the c-states I have to disable. If not reboot or WHEA Log appears. For that reason I was in doubt about DF states 
Thanks


----------



## _frame_

Latency 50,8 ns
Vdimm 1.42 V 
This is the limit for my ram with this cpu and mobo... couldn't get stability with tighter timings and more voltage.


----------



## Omi-

Hello,
first time trying to oc, I would like some tips on how I should proceed with all of this. 
Currently, these are my settings and I get errors 0,6,8 with 1usmus v3 config. The marked area on zen timings is what is set to auto.


















As far as I understand, I should try as low procODT as possible, but rtt's are specific on the amount of dimms I run right? Not sure about drvStr's,
Currently, I am thinking I should probably loosen tWRRD and see how it goes.
My cpu currently is not oc'd since I am stuck with stock cooler till I get a better one, should I use pbo2 curve optimizer undervolting so that I get less variance in Aida runs? If so, should I go with an all core or per core offset?

Thank you in advance.


----------



## Nighthog

Got this finally to work:









Worse result than F31 Bios could do at this speed. Much worse in general.
F33f has been a disappointment in general for MEM OC. Everything refuses to work. Lots of extra effort to try and figure out why it doesn't do it properly for a 20 cycle.

tCKE @ 15 was one requirement I guess and still unsure if 1T will work, didn't work earlier on this F33f bios.
1T works for 4200/2100 but not 4266/2133 to get stable for all my efforts.

I have results for CL 16 at this speed for earlier BIOS but F33f doesn't even boot @ CL18 right now.


----------



## Flash1228

Omi- said:


> Hello,
> first time trying to oc, I would like some tips on how I should proceed with all of this.
> Currently, these are my settings and I get errors 0,6,8 with 1usmus v3 config. The marked area on zen timings is what is set to auto.
> View attachment 2484947
> 
> View attachment 2484969
> 
> 
> 
> As far as I understand, I should try as low procODT as possible, but rtt's are specific on the amount of dimms I run right? Not sure about drvStr's,
> Currently, I am thinking I should probably loosen tWRRD and see how it goes.
> My cpu currently is not oc'd since I am stuck with stock cooler till I get a better one, should I use pbo2 curve optimizer undervolting so that I get less variance in Aida runs? If so, should I go with an all core or per core offset?
> 
> Thank you in advance.


I'm no expert, but from my understanding RTT of 6/3/3 is a good starting place for 2 dual rank sticks. I've got 4 single rank on daisy chain topology so my RTTs are a different mess lol.

For cadbus (drvstr) I've seen Veii mention Vermeer likes something like X-20-30-20 so maybe 60-20-30-20 or 40-20-30-20 (I've been using this for 4x8 3800mhz w/5800x). The reasoning behind this I'm unsure of.


----------



## nada324

Hey, so i have been trying stuff like changing cad bus timings with no luck. My bdie kit just dont like TRCD at 15 at all..., tried more ProcODT, more ClkDRV, tck1 still same issue.

Btw, @Veii what can i try to fix error #13? I dont see changing RTT stuff


----------



## PJVol

lmfodor said:


> So I should back to set DF


All these "tips" are basically a wild guess, since most of the info is proprietary and not gonna be disclosed in near time. And we are all experimenting here as well. Try and share your experience. I've shared mine already.
At least its not gonna brick your hardware in any way


----------



## mirzet1976

nada324 said:


> Hey, so i have been trying stuff like changing cad bus timings with no luck. My bdie kit just dont like TRCD at 15 at all..., tried more ProcODT, more ClkDRV, tck1 still same issue.
> 
> Btw, @Veii what can i try to fix error #13? I dont see changing RTT stuff
> 
> View attachment 2484975


tRC=tRP+tRAS, try tCL-14, tWRRD-2


----------



## craxton

Trusconi85 said:


> Upgrade bios from 1805 to 2003 and later to 2006B on my B550F Strix and now i am not able to run old 4000 c16 with 2000 FCLK setup...any suggestion?
> 
> I try with 1.46v but it won't boot, now i am running everything stock with XMP profile on all 4 stick of 8 gb
> 
> Thanks in advance


i dont know if anyone has answered you or not just yet, but first allow the system to boot normally before trying to overclock your ram

then once you have done an actual full boot cycle, try applying your overclock again. i know if i reset my bios
with my stable ram oc, i cant simply go straight into bios, apply my oc and boot it just doesnt work on b550 gaming edge wifi.

so give that a try first, if it doesnt work....well hopefully it does. if you were actually stable running before....

(to whome ever i sent this to first my apoligies for some reason i responded to the wrong person...)


----------



## craxton

*has anyone got the new bios ("fix for usb") for AM4 boards yet? or has none of the motherboard makers released it yet? *

or is it simply not time to release it? i thought amd said it would be the 1st of april......probably not, but wishful thinking as
my phones are in need of rooting/jailbreaking yes (droid, and iphone) while the usb drop out still happens no chance ill
give a shot at bricking my mi 11.... (great phone minus the CN rom which is unneeded in the USA) if you buy one, 
be sure to get an actual case straight away......


----------



## T[]RK

craxton said:


> or is it simply not time to release it?


I remember AMD said it will be in April?

Yep, founded it:
_*Customers can expect downloadable BIOSes containing AGESA 1.2.0.2 to begin with beta updates in early April (c) AMD*_

I updated my board page and there is new BIOS - F61a (AGESA 1.2.0.1A) with fixed L3 Cache. Will try it.


----------



## mirzet1976

Trusconi85 said:


> Upgrade bios from 1805 to 2003 and later to 2006B on my B550F Strix and now i am not able to run old 4000 c16 with 2000 FCLK setup...any suggestion?
> 
> I try with 1.46v but it won't boot, now i am running everything stock with XMP profile on all 4 stick of 8 gb
> 
> Thanks in advance


For me completely unstable 2003 and 2006, i can't boot with 3800mhz and 4000mhz i went back to 1602 bios.


----------



## Insidious Supra

craxton said:


> *has anyone got the new bios ("fix for usb") for AM4 boards yet? or has none of the motherboard makers released it yet? *
> 
> or is it simply not time to release it? i thought amd said it would be the 1st of april......probably not, but wishful thinking as
> my phones are in need of rooting/jailbreaking yes (droid, and iphone) while the usb drop out still happens no chance ill
> give a shot at bricking my mi 11.... (great phone minus the CN rom which is unneeded in the USA) if you buy one,
> be sure to get an actual case straight away......


Gigagyte has had this update out since March 15 or 16 I want to say, maybe sooner. Current BIOS version says the 26th, but I have the save version, and had downloded/installed it prior to the 17th.

To contribute to the thread, I use cl16 3600 Ripjawz v (4x8gb). Set xmp profile 1, manually change multiplier to 38, voltage to 1.39, and change fclk to 1900. b550 pro ac board, and 5800x which also runs past 5ghz on 4 cores stable. My cpu core voltage I set to 1.32, and soc voltage to 1.08. Running higher soc voltage was making my ram unstable somehow.

I tried fine tuning ram timings further, but the system adjusts them automatically when you change the multiplier. And anything tighter just doesnt post. For me, anyhow.


----------



## AmateurRanger

Got a XPG kit off Amazon and looks like they are fairly tightly binned B-die. Problem is I will get few errors starting from 30mins mark of testing. Any ideas? Right now it's 1.44V, 1.42V was similar. 1V VDDG, might try lower CCD a bit for now.


----------



## Flash1228

After what feels like literally forever I've finally found something that passes stability.


----------



## KedarWolf

Flash1228 said:


> After what feels like literally forever I've finally found something that passes stability.
> 
> View attachment 2485041
> 
> View attachment 2485042


But can you pass OCCT Large Data Set, Extreme with no WHEA errors though?


----------



## mongoled

adversary said:


> @Veii
> Hello. I did try number of things you suggested last time, and fixed some things you told me. But still I lack info and knoweledge what exactly I should do further, as I can't get 3800/1900 stable in MemTest5 (1usmus_v3)
> Also I read what you suggest to others and try such things.
> 
> Picture I attached is what I did try today - I upped SOC to 1.175 from 1.12.
> I did try MT5 now with SOC 1.175, it did not show any error after cycle 1, but during cycle 2 it just goes black screen and rebooted.
> At SOC 1.12, it did number of errors - and they were : 0,4,10,14
> 
> And I did try RAM voltage from 1.55V to 1.6V, nothing seems to help.
> 
> Same configuration, but run at 3733/1866 never get errors in MT5 (but sometimes, randomly, it seems I get some crakling sound in games for a moment)..
> 
> I'm still on 1.2.0.0 AGESA. I did not try 1.2.0.1 Beta Patch A which is available for my motherboard now. Perhaps soon 1.2.0.2 will be available so maybe I should than try again.
> But until than I would like to try to get 3800/1900 stable and with good latency, or if not possible on current BIOS, than 3733/1866 fully tuned with best latency I can get.
> 
> 
> I will provide you additional information so you can get best information on my system (and maybe correct me if some of these things are mistakes).
> 
> I run with PBO now plus +offset to core voltage. Found sweet spot for added voltage (beyong that additional heat will negate any benefit from added voltage). I'm on custom EKWB watercooling so temperatures are really good overall (and lower temps are, CPU will always boost more under load). RAM is also watercooled.
> 
> Advanced\AMD CBS\NBIO Common Options\SMU Common Options\DF Cstates ----------- I disabled this (as I found you suggested that for another user).
> 
> I did fix CLDO VDDP to 0.9V as you suggested. However, I can't find CPU VDDP in BIOS, or at least, it is not under that name. You can see motherboard name in attached picture.
> 
> Setting tCKE at 9, seems to helped much with stability, compared to Auto (which is 1 I think). Even 3733/1866 would not be stable without it.
> 
> CsOdtDrvStr - I can't raise it at 40, it won't work, I just get stuck with black screen before BIOS load (maybe it would be possible with some other overall configuration, but with this one seems not).
> 
> Did try AddrCmdSetup, CsOdtSetup, CkeSetup timings as 3 3 15 as I seen you suggest - run immidiately into problems. Will not boot into Windows, but show error message and return me to BIOS. Than BIOS freeze.
> 
> 
> I have no idea what to try from this point on, I would need to know what exactly to fix.
> 
> If you belive that newer AGESA would help, I can wait for it, as 3733/1866 at this moment works well for my needs. If we can't get 3800/1900 to work at this moment let me know, no problem, in that case lets just try to tune further 3733/1866 for best latency and stick with it for some time, and try again in future with newer AGESA. However if inability to get 3800/1900 is pure due to my mistakes, let me know what to do and I will try to make it work.
> I asked myself if maybe my RAM is bad bin and do not like higher speed, but again, it is only jump from 3600 to 3800, should not be problem for new B-Die kit I belive.
> 
> If issue is with tRFC (2 & 4) or tRDRDSCL and tWRWRSCL, it would be pity if I have to raise them, as lowering these timings indeed helped with RAM speed and latency.
> 
> 
> 
> 
> 
> View attachment 2484886


What exactly are you expecting as an answer ?

You are asking for a "fix" and not just a fix, but for someone to tell you _exactly_ what to fix as if such an answer even exisited......

Now, if you were running setting that were not overly aggresive than I could sort of understand the reasoning about what you are asking for, but you are far far far from that.

Has it not crossed your mind that what you want to run stable with up to 1.6v is not possible with the settings you are using (and may not be possible simply because those are the limits of the hardware...) ?

Please find anybody else on the Internet who is pushing 3800/1900 tCL @14, tRP @13, tRCDRD @14 tRFC @232 who is TM5 stable, not to mention that TM5 is not enough for stability, add Y-Cruncher, Prime95 (Large FFTs) to your testing suite and you will never get those settings stable.

Is it the smaller numbers for epeen that you are chasing as some of the numbers you are using are giving you lower performance, lower does not always equal better !

For a start, when using 4 x 8GB (think its the same when using 2 x 16GB) tRDRDSCL/tWRWRSCL @2/3 gives lower throughput than @4/5.

Below is the max you should be aiming for.

I mean come on, you want to tRP @13, tRDCRD @14 and _AND_ tRFC @232 and expect to find stability and for what, its going to make no difference in the every day tasks you do when compared to the setting shown below.

If you were going for competitive benching then OK, but expecting to be stable, well that is not happening and if you happened to get a TM5 to pass, it definatly wont be passing after consecutive reboots, shutdown cycles .....


----------



## lmfodor

A quick question, why can it be that ZenTimmings doesn’t read me the VDIMM values? I have an Asus CH8 Wifi mobo. Thanks!


Sent from my iPhone using Tapatalk Pro


----------



## PJVol

The quick answer: ask developer - he may be seen here








ZenTimings


ZenTimings A simple and lightweight windows application which aims to show memory-related timings and settings on AMD Zen platform. Supported features vary between different SKUs and motherboards. BEWARE: The official site is https://zentimings.protonrom.com/ Any other site pretending to be...




www.overclock.net


----------



## zGunBLADEz

wden said:


> Hello,
> 
> It seems this is the best OC I can achieve. I've tried different combinations and recommendations both from this thread and the Zen RAM Overclocking spreadsheet to no avail. I have also tried raising and lowering VSOC, VDIMM, VDDG CCD/IOD, VDDP with no luck.
> 
> I'm also unable to POST when attempting 1900IF. I bought this RAM kit back in 2018, not sure if that affects anything.
> 
> The best I have been able to get is this. Could it be my motherboard that's causing issues? RAM getting too hot? Any suggestions or ideas to possibly lower the timings or reach 1900IF would be appreciated? Thanks.
> View attachment 2484805




try different bios i got bad luck with old bioses on that regard... i only have 5 bios to choose from in this board.. one of them is useless. the oldest one overclock the highest but it have poor l3 readings and no 1900 fclk and no 3800 achievable with this particular kit... 32gb gskill b die old old kit 
the other ones are a mix bag... Latest 3 one have that l3 bug thingy that i have been fighting for ahwile.. technically all of them have it on static overclock...
cant use musmus ctr on the last 2 so i stick to 1803 bios for now.. Latest bios fixed the random crashes on pbo but l3 is limited to 1000s on l3s (boosting @ 46.50x on all cores. get more than that on [email protected]) as you see amd is well aware of this.... outside pbo overclocking this cpu is useless.... i would need ctr for that and having a hybrid oc but the l3 crash still there.


what i have experience so far cpu/mhz =====> ram/flck and everything else... and amd eco system is a beta tester bug paradise


----------



## Flash1228

KedarWolf said:


> But can you pass OCCT Large Data Set, Extreme with no WHEA errors though?


I'll give it a go. I can boot up to 2000 fclk, but get WHEAs for even thinking about over 1900 lol


----------



## BarrettDotFifty

@Veii Hey, can I ask for some tips on how to run this setup with GDM off? No matter what I try, I'm having training issues and/or BSODs later on best case scenario. The setup below has been stable for months, but I still feel like I can squeeze more with that 1.44V VDIMM.

Thanks in advance.


----------



## PuffyArgos

BarrettDotFifty said:


> @Veii Hey, can I ask for some tips on how to run this setup with GDM off? No matter what I try, I'm having training issues and/or BSODs later on best case scenario. The setup below has been stable for months, but I still feel like I can squeeze more with that 1.44V VDIMM.
> 
> Thanks in advance.
> 
> View attachment 2485079


I know you were looking for Veii's thoughts, but my own experience in a similar position as you with an x570 was more ClkDrvStr. It's worth fiddling with anyway.


----------



## PJVol

Just finished testing it in TM5 1usmus v3. Preliminary stable.


----------



## jcpq

@*ManniX-ITA*
Thanks for the tips


----------



## BarrettDotFifty

PuffyArgos said:


> ClkDrvStr


Would you consider it possible for GDM disabled to run with the RTT as shown in my ZenTimings shot?


----------



## lmfodor

mongoled said:


> What exactly are you expecting as an answer ?
> 
> You are asking for a "fix" and not just a fix, but for someone to tell you _exactly_ what to fix as if such an answer even exisited......
> 
> Now, if you were running setting that were not overly aggresive than I could sort of understand the reasoning about what you are asking for, but you are far far far from that.
> 
> Has it not crossed your mind that what you want to run stable with up to 1.6v is not possible with the settings you are using (and may not be possible simply because those are the limits of the hardware...) ?
> 
> Please find anybody else on the Internet who is pushing 3800/1900 tCL @14, tRP @13, tRCDRD @14 tRFC @232 who is TM5 stable, not to mention that TM5 is not enough for stability, add Y-Cruncher, Prime95 (Large FFTs) to your testing suite and you will never get those settings stable.
> 
> Is it the smaller numbers for epeen that you are chasing as some of the numbers you are using are giving you lower performance, lower does not always equal better !
> 
> For a start, when using 4 x 8GB (think its the same when using 2 x 16GB) tRDRDSCL/tWRWRSCL @2/3 gives lower throughput than @4/5.
> 
> Below is the max you should be aiming for.
> 
> I mean come on, you want to tRP @13, tRDCRD @14 and _AND_ tRFC @232 and expect to find stability and for what, its going to make no difference in the every day tasks you do when compared to the setting shown below.
> 
> If you were going for competitive benching then OK, but expecting to be stable, well that is not happening and if you happened to get a TM5 to pass, it definatly wont be passing after consecutive reboots, shutdown cycles .....
> 
> View attachment 2485050


Hi, very interesting point a view, I’m looking something similar to you. I have a new memories 3800CL14 that with an standard XMP profile has a gold bandwidth but Lower latency (60ns) so I’m working to get the lower as it can but considering stability, bandwidth and low latency with lower mem temps.. my memories run by default at 1.5.. so I’d prefer to not exceed 1.52. 

This was my best timings.. I tried to improve but now I can achieve the values or latency
















This is the Veii notes to improve my timings but I’m a little bit confuse on how to apply it 









And this is how I’m running now.: I quite lost about some many changes that I did to achieve the same results







I can’t lower 56ns.. always closer to 57ns. Any suggestion or advise?

Thanks!


Sent from my iPhone using Tapatalk Pro


----------



## Flash1228

lmfodor said:


> Hi, very interesting point a view, I’m looking something similar to you. I have a new memories 3800CL14 that with an standard XMP profile has a gold bandwidth but Lower latency (60ns) so I’m working to get the lower as it can but considering stability, bandwidth and low latency with lower mem temps.. my memories run by default at 1.5.. so I’d prefer to not exceed 1.52.
> 
> This was my best timings.. I tried to improve but now I can achieve the values or latency
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This is the Veii notes to improve my timings but I’m a little bit confuse on how to apply it
> 
> 
> 
> 
> 
> 
> 
> 
> 
> And this is how I’m running now.: I quite lost about some many changes that I did to achieve the same results
> 
> 
> 
> 
> 
> 
> 
> I can’t lower 56ns.. always closer to 57ns. Any suggestion or advise?
> 
> Thanks!
> 
> 
> Sent from my iPhone using Tapatalk Pro


Did you try tWRRD of 3?
Does it work with SCL of 4 instead of 5?


----------



## lmfodor

Yes, I've tried. I'm just done correcting them. that value is the floor, try several latency tests and they were always 56.2 up. I set back tWRRD to 3 and SCL to 4









Before, I had a very tight values but see the latency









Any ideas to improve? I'm really baffled. Something's limiting me and I don't know what it is.
Thanks!


----------



## lmfodor

Well, I went back to the adjusted values. Slowly it seems to be lowering latency. What do you think, anything else to adjust? Regarding the TRP that is at 12, would I support it with 1.52v? That's the VDIMM I have now.


----------



## craxton

T[]RK said:


> I updated my board page and there is new BIOS - F61a (AGESA 1.2.0.1A) with fixed L3 Cache. Will try it.


yeah, i looked a little after i asked and found they said early april as well.



Insidious Supra said:


> Gigagyte has had this update out since March 15 or 16 I want to say, maybe sooner. Current BIOS version says the 26th, but I have the save version, and had downloded/installed it prior to the 17th.


thats the thing, theyre almost always one of the first. and MSI seems to be one of the last.
but, ive had 4000mhz running on ALL patches since patch B was a thing in december.

have yet to see any update since 03/05 for the b550 board....
msi may be last as i said, but theyre near always stable (have been for me)



AmateurRanger said:


> Got a XPG kit off Amazon


can you link this kit ? or pm it to me by chance??? SURE i dont need more bdie, but well

my 4sticks of tforce 3200c14 sticks are well....they have nothing near me to contend with now lol...
sold all my ram this past month with my spare parts i.e. mobo, gpus, etc...

@ANYONE with 1.2.0.2 bios, have you tested usb dropout issues? 
unsure how, simply grab an iphone and try to jailbreak it. if it works then usb is perhaps solved, 
if not then its still busted....(perhaps, i truly dont have usb dropout issues. as someone stated ch3ckra1n 
doesnt like amd and doesnt run very well regardless?) it does however work on my uncles
old phenom processor.... I dont have any whea errors telling me im having USB dropout issues
tried running stock profile with 2 and just 1 dimm. but still the same.

(i mention jailbreaking an iPhone bc this is the ONLY time ive ever actually had an instance of 
anything related to USB issues or USB not working properly. but since i have no issues with the phone just copying files etc
im now unsure i have a usb issue at all. NO I _*HATE IPHONE!!!*_ its for a child! 

anyone experiencing USB dropout, are you having this at any ram frequency, on your mouse/keyboard, headphones,
monitor, etc ???


----------



## Flash1228

lmfodor said:


> Well, I went back to the adjusted values. Slowly it seems to be lowering latency. What do you think, anything else to adjust? Regarding the TRP that is at 12, would I support it with 1.52v? That's the VDIMM I have now.
> View attachment 2485153


Out of curiosity, how did you come up with tRRDS and tRRDL values?
Idk how much of a difference it makes, but if you haven't already maybe try tRRDS - 4 tRRDL - 6 and tFAW 16?


----------



## lmfodor

Flash1228 said:


> Out of curiosity, how did you come up with tRRDS and tRRDL values?
> Idk how much of a difference it makes, but if you haven't already maybe try tRRDS - 4 tRRDL - 6 and tFAW 16?


Actually both values were in 4 and 4.. and tFAW in 16. I leave tFAW in 24 due to a Veii recommendation that should be tRRDSx 4









I will try tRRDS 4 (so tFAW to 16) and tRRDL to 6 and let you know how it goes...thanks!



Sent from my iPhone using Tapatalk Pro


----------



## lmfodor

Well, Like my friend @*RosaPanteren *told me, I had to try Safe Mode. Look the at the difference.
This are the values with normal startup








Loot at the latency!!








This is a normal behavior?
Now I'm gonna try TM5 to see if these timings are fine. My VDIMM is 1.52. I don't know if that'll be enough.


----------



## Veii

Clean your OS if you feel latency variation or make a new partition for one without Peripherals Software Bloat








Autoruns for Windows - Sysinternals


See what programs are configured to startup automatically when your system boots and you login.



docs.microsoft.com




SafeMode disables video drivers, disables powermanagement, disables audio, hides to what your boost

Unrealistic on close to every point possible.
If this 4.95 boost above would be sustainable in reality without clock stretching - you need to hit 10.3ns not 10.5 or 10.6ns L3
Maybe feasible for XOC record hunting, but this is the wrong thread to show such results. Neither should the Reddit ZEN RamOC Docs accept such results either.
Also showing that L3 cache on the example above is close to identical, means that its not your OS that slows down CPU performance. Fix that first. Get CO and power management correctly set up.
The example couldn't show better what clock stretching means.


nada324 said:


> Hey, so i have been trying stuff like changing cad bus timings with no luck. My bdie kit just dont like TRCD at 15 at all..., tried more ProcODT, more ClkDRV, tck1 still same issue.
> 
> Btw, @Veii what can i try to fix error #13?
> View attachment 2484975


tRAS+1 won't work out , unless tFAW is low








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


i get 0 wheas tho.... only have 1 whea in the whole event viewer and that one i did on purpose looking for the issue i have as we speak not so long ago




www.overclock.net




Bottom post


























nada324 said:


> I dont see changing RTT stuff


Sorry, i don't see how i can help you then
536 could work , or more voltage

But tRC is too low, or tFAW too high if you want to use this tRC exploit
Unsure if you would be able to. To get it to work, you need a lot of changes on SCL, tRRD, tWTR ~ to balance it out
You seem to struggle with "basic" error readouts and independent work, to figure it out
Maybe staying at tRC 45 would be easier for you ~ unsure


adversary said:


> Advanced\AMD CBS\NBIO Common Options\SMU Common Options\DF Cstates ----------- I disabled this (as I found you suggested that for another user).


Yes, it's slower and kills performance but prevents Overboosting. Acceptable tradeoff to keep up stability "for now". Till AMD get's their cache boosting and sleep states boosting together.


adversary said:


> CsOdtDrvStr - I can't raise it at 40, it won't work, I just get stuck with black screen before BIOS load (maybe it would be possible with some other overall configuration, but with this one seems not).
> 
> Did try AddrCmdSetup, CsOdtSetup, CkeSetup timings as 3 3 15 as I seen you suggest - run immidiately into problems. Will not boot into Windows, but show error message and return me to BIOS. Than BIOS freeze.
> 
> 
> 
> adversary said:
> 
> 
> 
> However if inability to get 3800/1900 is pure due to my mistakes, let me know what to do and I will try to make it work.
> I asked myself if maybe my RAM is bad bin and do not like higher speed, but again, it is only jump from 3600 to 3800, should not be problem for new B-Die kit I belive.
Click to expand...

It's my flaw that i can't give you better powerring settings for 4 dimms
High ClkDrvStr is required for GDM off, or high VDIMM , or high procODT
you don't want high procODT

I have worse B-Dies than nearly each one of you guys. That's not an excuse. 3800C13-13 == 4200C15-15


adversary said:


> If issue is with tRFC (2 & 4) or tRDRDSCL and tWRWRSCL, it would be pity if I have to raise them, as lowering these timings indeed helped with RAM speed and latency.


Are you sure you ever got it stable at 14-14-14 flat ?


adversary said:


> And I did try RAM voltage from 1.55V to 1.6V, nothing seems to help.


That's around the range you should move. But i think too that you do "too much at once"

Do you know that FCLK is even stable with a 16-16-16 set on these voltages ?
Do we know RTT and tCKE work for you on a 16-16-16 set ?
Do we know they are fine on a 14-14-14 set ?
Which errors do you get and have you checked
tRFC Calculator (mini) for an error description - or Kim's public ryzen calculator doc
Ryzen Google Calculator which people destroy even more often than mine and it's a bit hard to use, but useful nevertheless

Too many little jumps if you can't answer me all of these questions with YES
tWTR_L you should keep at start 2* tRRD_L
Probably even switch up to 5-14, instead 4-12
Many dimm setups need generally higher tWR and tRDWR

You ask me about powering settings, but yet run low timings
Sure it's only the powering settings preventing you from keeping stability up ?


Nighthog said:


> Got this finally to work:
> View attachment 2484970
> 
> 
> Worse result than F31 Bios could do at this speed. Much worse in general.
> F33f has been a disappointment in general for MEM OC. Everything refuses to work. Lots of extra effort to try and figure out why it doesn't do it properly for a 20 cycle.
> 
> tCKE @ 15 was one requirement I guess and still unsure if 1T will work, didn't work earlier on this F33f bios.
> 1T works for 4200/2100 but not 4266/2133 to get stable for all my efforts.
> 
> I have results for CL 16 at this speed for earlier BIOS but F33f doesn't even boot @ CL18 right now.


Good job 
tCKE 15 should be for 4400, likely tCKE 14 should suite here
Although i think 13 would still cover this one jump upwards. It does for me at least


_frame_ said:


> Latency 50,8 ns
> Vdimm 1.42 V
> This is the limit for my ram with this cpu and mobo... couldn't get stability with tighter timings and more voltage.


Good Job !
Open up EDC to 400A under AMD OVERCLOCKING, 1.1.9.0 AGESA should have the new ABL that allows the cacheboost
Unsure how you got 5.1 to run, but that should result in 9.9ns L3
You likely do a bit clock stretch , around 200mhz
677p, is around 4.9Ghz realistic clock ~ boost - at best near 4.95
Nice memory efficiency result, 31999

tRC to my math get's as 44 out
You can try to run 1-5-4-1-7-6 on SD, DD's and see if you get tRDWR 8 ~somehow~ stable
tRCD_WR , tCWL, tWR ~ all together are on 4 values too much
Try to spread 4 values somewhere. Probably tRCDWR 15 should be fine. But i feel like you can run 16-16-16 with a bit more work. It's not that impossible.
You can give 635 a shot


Spoiler: Something like this














it wouldn't need SETUP Times, just tCKE and generally higher VDIMM
The same thing i tell you, should be told to me ~ i know 
But it's fine for now, i got it already down to tRAS 30


Taraquin said:


> Input on my settings?
> 
> Karhu i stable, I get rare error 6 (too high soc voltage?) after 5-10 cycles in TM5 usmus. Infinity fabric seems unstable if I lower soc or iod-voltage, I got random reboots when both where 0.02V lower. CPU-clock is stable, currently running [email protected] Any input of what to change, improve etc? The B-die is a ****ty bin btw and due to GPU sending hot air straight at it anything above 1.45V tends to be unstable.
> View attachment 2484893


tRFC








Don't judge the poor dimms, it's a far better set then i have
4000C16-16-16 = 3800C15-15-15
With more work and more VDIMM you can get 15-15-15 to run. Near 1.48-1.5 should be enough. That's still 60mV less than what usually people need at 3800C14-14
If correct tRFC doesn't fix it, give tWRRD 3 a try


----------



## mongoled

@lmfodor 

Increase vSOC to 1.175v
Increase vDDP to 0.905/0/915v
Increase vDDG CCD to 1.005v

Then do a direct comparisson with previous results.

Your latency using tRCDRD @16 and tFAW @24 is generally in the right range.

Safe mode always reduces latency as it simply stops "background noise", use safe mode as a baseline diagnostic tool when comparing changes you have made from one set of timings/voltages/settings to another.


----------



## lmfodor

Well, Well, as *@Veii* mentioned, it seems that the voltage doesn't hold up the TRP below 1.54v. Does anyone know what this error means?









So I went back to TRP of 14 with a tRAS of 22 and TRC 36. Could it hold these timings at 1.5? or should I loose other one?









This are the timings in Safe Mode: 









Thanks!!!


----------



## Veii

lmfodor said:


> Well, Well, as *@Veii* mentioned, it seems that the voltage doesn't hold up the TRP below 1.54v. Does anyone know what this error means?


Error #12 = Error #2
(most of the times)


----------



## lmfodor

mongoled said:


> @lmfodor
> 
> Increase vSOC to 1.175v
> Increase vDDP to 0.905/0/915v
> Increase vDDG CCD to 1.005v
> 
> Then do a direct comparisson with previous results.
> 
> Your latency using tRCDRD @16 and tFAW @24 is generally in the right range.
> 
> Safe mode always reduces latency as it simply stops "background noise", use safe mode as a baseline diagnostic tool when comparing changes you have made from one set of timings/voltages/settings to another.


Well. it gave me an error in TM5 1usmus.. I changed TRP of 14 with a tRAS of 22 and TRC 36. 
I have set VSOC to 1.14, VDDP 0.9v and 0.95. Should I rise with these new values of TRP?
Thanks!


----------



## mongoled

lmfodor said:


> Well. it gave me an error in TM5 1usmus.. I changed TRP of 14 with a tRAS of 22 and TRC 36.
> I have set VSOC to 1.14, VDDP 0.9v and 0.95. Should I rise with these new values of TRP?
> Thanks!


No,

dont change any of your prior settings!!!!!

Just change the voltages and see if there are any changes in your latency, thats all ......


----------



## Veii

lmfodor said:


> So I went back to TRP of 14 with a tRAS of 22 and TRC 36. Could it hold these timings at 1.5? or should I loose other one?


How does stronger RTT_Nom hold up ?
Would heat increase ?
You shouldn't be afraid to push more than 1.5v on lose RTT_PARK
It wouldn't really heat it up more
tWTR_L is low. You'd want to likely run ttRRD_L 5, tWTR_L 10

Or if you feel like increasing tRRD and running tWTR_L at 12 (4-12)
you can get a bit more headroom. They don't do thaat much in terms of latency
Lower primaries are more important

I also do feel like tRAS should be 24 here, instead of 22
Anywho, your lack of better latency is the unstable boost with a lot of clock stretching ~ strongly visible on the high L3 cache latency (4.75Ghz sustained)


----------



## lmfodor

Veii said:


> Error #12 = Error #2
> (most of the times)


Hi @Veii, yes, I followed your guide.. I try rising VDIMM to 1.55 but I couldn't get POST.. So I prefer to loosen the trimmings like this, do you think it's okay for 1.5v?


----------



## Veii

lmfodor said:


> Hi @Veii, yes, I followed your guide.. I try rising VDIMM to 1.55 but I couldn't get POST.. So I prefer to loosen the trimmings like this, do you think it's okay for 1.5v?
> View attachment 2485187


You fully had a post refuse on 1.55 ?
Are you very sure ?

Or do you mean a refuse with a timings change
If 1.55v refuses to post , or 1.54 crashes midwhile 
Then i would not try 1.56v. It's a PCB overvoltage crash and can end up with a loss of a memory channel
IF i understand you correctly


----------



## lmfodor

Veii said:


> You fully had a post refuse on 1.55 ?
> Are you very sure ?


Yes. When I found the error immediately reboot and only changes the vales from 1.52v to 1.55. The mobo (asus CH8 Wifi) try to boot up several times and can't get POST. Luckily I didn't have to reset the CMOS, it gave me the possibility to go back to the previous values. Do you think if I try these current values now, I go up to 1.55v and then lower TRP to 12, tRAS 22 and TRC 34 as before?


----------



## Veii

lmfodor said:


> Yes. When I found the error immediately reboot and only changes the vales from 1.52v to 1.55. The mobo (asus CH8 Wifi) try to boot up several times and can't get POST. Luckily I didn't have to reset the CMOS, it gave me the possibility to go back to the previous values. Do you think if I try these current values now, I go up to 1.55v and then lower TRP to 12, tRAS 22 and TRC 34 as before?


Nono, if the PCB actually crashes because of overvoltage
Then you have to redo RTTs

I've tested them and they where fine, but this should not happen. Not with these temps
Seems like they are still way to strong. . .
Please don't try 1.56v and stay bellow 1.51v till you get weaker RTT_PARK to run, or turn down procODT 1-2 steps

Make a profile and maybe try for me RTT_NOM /5, RTT_WR /2
But don't exceed higher than 1.51v
Just as a test if RTT_WR /2 could already work. You will need to cmos reset if it doesn't accept it


----------



## lmfodor

Veii said:


> Nono, if the PCB actually crashes because of overvoltage
> Then you have to redo RTTs
> 
> I've tested them and they where fine, but this should not happen. Not with these temps
> Seems like they are still way to strong. . .
> Please don't try 1.56v and stay bellow 1.51v till you get weaker RTT_PARK to run, or turn down procODT 1-2 steps
> 
> Make a profile and maybe try for me RTT_NOM /5, RTT_WR /2
> But don't exceed higher than 1.51v
> Just as a test if RTT_WR /2 could already work. You will need to cmos reset if it doesn't accept it


Just to recap, I keep on TRP 14+TRAS 22 and TRFC to 36. right? and I set RTT_NOM to 5 and RTTWR 2 right?


----------



## KedarWolf

lmfodor said:


> Hi @Veii, yes, I followed your guide.. I try rising VDIMM to 1.55 but I couldn't get POST.. So I prefer to loosen the trimmings like this, do you think it's okay for 1.5v?
> View attachment 2485187


This is what works for me, I had issues with random reboots at 6-3-3 RTTs etc.


----------



## lmfodor

Veii said:


> Nono, if the PCB actually crashes because of overvoltage
> Then you have to redo RTTs
> 
> I've tested them and they where fine, but this should not happen. Not with these temps
> Seems like they are still way to strong. . .
> Please don't try 1.56v and stay bellow 1.51v till you get weaker RTT_PARK to run, or turn down procODT 1-2 steps
> 
> Make a profile and maybe try for me RTT_NOM /5, RTT_WR /2
> But don't exceed higher than 1.51v
> Just as a test if RTT_WR /2 could already work. You will need to cmos reset if it doesn't accept it


There we go. The latency is not the real.. I mean non in Safe mode.. I always run two times.. first 56.7 and the 56.1ns. What do you think? Should I change RTT Park or porcODT?


----------



## lmfodor

KedarWolf said:


> This is what works for me, I had issues with random reboots at 6-3-3 RTTs etc.
> 
> View attachment 2485192


It seems you have the same memory type but 3600C16 and mine is 3800C14. I don't know why I can see VDIMM values in my ZenTimings.. Mine is set to 1.5v that is the standard voltage. I see you have more voltage on VSOC, CCD and IOD. I wonder if I should rise all of them...


----------



## lmfodor

mongoled said:


> No,
> 
> dont change any of your prior settings!!!!!
> 
> Just change the voltages and see if there are any changes in your latency, thats all ......


Hi! Yes, the things is that I won't to stay in 1.55v for the heat.. even having a cooler on top of the memories I prefer to stay low.. @Veii told me that TRP in 12 wont run sub 1.54v. That's why I rise to 14 (could be 13?) and then follow the rule for the remaining values. Maybe my VSOC, VDDG and IOD are low..


----------



## mongoled

Dude, its real simple.

Use the settings you had before the 1.55v and simply change the voltages i suggested and compare.

Its a 2 minutes job!


----------



## lmfodor

mongoled said:


> Dude, its real simple.
> 
> Use the settings you had before the 1.55v and simply change the voltages i suggested and compare.
> 
> Its a 2 minutes job!


Yes, I tried! But I didn't get POST! I rise VDIMM to 1.55v and the mobo started..stopped..several times, and the 4th time it let me change the values. Luckily I don't had to clear CMOS


----------



## lmfodor

Veii said:


> How does stronger RTT_Nom hold up ?
> Would heat increase ?
> You shouldn't be afraid to push more than 1.5v on lose RTT_PARK
> It wouldn't really heat it up more
> tWTR_L is low. You'd want to likely run ttRRD_L 5, tWTR_L 10
> 
> Or if you feel like increasing tRRD and running tWTR_L at 12 (4-12)
> you can get a bit more headroom. They don't do thaat much in terms of latency
> Lower primaries are more important
> 
> I also do feel like tRAS should be 24 here, instead of 22
> Anywho, your lack of better latency is the unstable boost with a lot of clock stretching ~ strongly visible on the high L3 cache latency (4.75Ghz sustained)


Well, this are the values in Safe Mode..








and this in normal startup








@Veii How do you see it? For your comments should I change>


RTT Park to 1
tRRD_L 5, tWTR_L 10
tRAS 24
and what about procODT?
I don't understood this: Anywho, your lack of better latency is the unstable boost with a lot of clock stretching ~ strongly visible on the high L3 cache latency (4.75Ghz sustained)
I'm gonna change this settings to see what happens. Thanks!


----------



## lmfodor

Veii said:


> Nono, if the PCB actually crashes because of overvoltage
> Then you have to redo RTTs
> 
> I've tested them and they where fine, but this should not happen. Not with these temps
> Seems like they are still way to strong. . .
> Please don't try 1.56v and stay bellow 1.51v till you get weaker RTT_PARK to run, or turn down procODT 1-2 steps
> 
> Make a profile and maybe try for me RTT_NOM /5, RTT_WR /2
> But don't exceed higher than 1.51v
> Just as a test if RTT_WR /2 could already work. You will need to cmos reset if it doesn't accept it


Well much better!! 








I kept thinking about what you said about high L3 cache latency.. I still have a lot of *clock stretching* ?


----------



## Veii

lmfodor said:


> Well, this are the values in Safe Mode..
> View attachment 2485196
> 
> and this in normal startup
> View attachment 2485197
> 
> @Veii How do you see it? For your comments should I change>
> 
> 
> RTT Park to 1
> tRRD_L 5, tWTR_L 10
> tRAS 24
> and what about procODT?
> I don't understood this: Anywho, your lack of better latency is the unstable boost with a lot of clock stretching ~ strongly visible on the high L3 cache latency (4.75Ghz sustained)
> I'm gonna change this settings to see what happens. Thanks!


Soo WR /2 works, good !
well at least posts ~ stability checks will clear up the picture

RTT_PARK at /1 is far stronger than RTT_PARK /3 
Where /3 was too strong to the looks of it.
If you go for /1 , lower VDIMM further ~ it's "not a good idea" to run strong RTT_PARK and high VDIMM 
a plain bad idea

High means 1.51+
Unless the PCB can take it

TM5 test it , make it 4-5 cycles, and change to RTT_PARK /4 
See if that runs now
Error 11 would relate to RTT_NOM 
It depends, RTT_WR will contineously auto autoadjust
It's a bit more aggressive on /2 , but when you had PCB crashes on 1.55v, then you have to redo the RTTs 
I see them as dangerous even (beyond 1.55v) ~ if you really had this type of crashes

It makes me wonder what PCB you run (not a thaiphon burner report)


----------



## Veii

lmfodor said:


> Well much better!!
> View attachment 2485200
> 
> I kept thinking about what you said about high L3 cache latency.. I still have a lot of *clock stretching* ?


Clock Stretching = fake frequency
Relative Core frequency matters
i wrote it easy to understand
10.9ns L3 = 4.65ghz applied during the cache test
10.7ns = 4.75Ghz
10.5ns = 4.85Ghz (it's 10.4 in reality, for me)
10.3ns = 4.95Ghz and so on

You mentioned you had a 140A EDC limit
the 5900 and 5950X are stock FUSE Limited on 200A
Memory OC and FLCK go into the EDC limit - open it up. The EDC limit , increase it how it should be


----------



## lmfodor

Veii said:


> Soo WR /2 works, good !
> well at least posts ~ stability checks will clear up the picture
> 
> RTT_PARK at /1 is far stronger than RTT_PARK /3
> Where /3 was too strong to the looks of it.
> If you go for /1 , lower VDIMM further ~ it's "not a good idea" to run strong RTT_PARK and high VDIMM
> a plain bad idea
> 
> High means 1.51+
> Unless the PCB can take it
> 
> TM5 test it , make it 4-5 cycles, and change to RTT_PARK /4
> See if that runs now
> Error 11 would relate to RTT_NOM
> It depends, RTT_WR will contineously auto autoadjust
> It's a bit more aggressive on /2 , but when you had PCB crashes on 1.55v, then you have to redo the RTTs
> I see them as dangerous even (beyond 1.55v) ~ if you really had this type of crashes
> 
> It makes me wonder what PCB you run (not a thaiphon burner report)


Oh, I understood the opposite, I thought you wanted me to adjust the RTTPark more so assume 1, if 4 is better the direct change. I have problems with TM5 Anta777 that I do not know because it does not finish the tests, it seems to be a common error.. I'm using the 1usmus, is that okay? I run several cycles continues...


----------



## Veii

lmfodor said:


> Oh, I understood the opposite, I thought you wanted me to adjust the RTTPark more so assume 1, if 4 is better the direct change. I have problems with TM5 Anta777 that I do not know because it does not finish the tests, it seems to be a common error.. I'm using the 1usmus, is that okay? I run several cycles continues...


We can not read Anta's errors
1usmus_v3 is more effective too, but it needs a bit of time to heat up the dimms.
The stock 3 cycles are not enough. 20-25 are needed, minimum 20

RZQ = 240ohm (questionable, should be 480ohm now)
/2 = half = stronger than /3 (1/3rd)


----------



## lmfodor

Veii said:


> We can not read Anta's errors
> 1usmus_v3 is more effective too, but it needs a bit of time to heat up the dimms.
> The stock 3 cycles are not enough. 20-25 are needed, minimum 20
> 
> RZQ = 240ohm (questionable, should be 480ohm now)
> /2 = half = stronger than /3 (1/3rd)


@Veii 
@Veii I've go it, .RZQ are the sum of RTT + procODT, so I should rise procODT to 480 minus the sum of RTT 5/2/1 right?


----------



## Veii

lmfodor said:


> Ok, much better! Actually my PBO are set to 220/200/200, so EDC it's fine or should I rise? my CO is set to -25 Cores of CCD1, -15 two best cores of CCD1 and all cores of CDD2 to -20, + 200 boost override.. what do you think?


I think that you are never hitting this +200 boost and clock stretch
The readouts tell it

Two options , grab latest CTR and "boost test"
See visually that not all cores are hitting the same peak frequency
This autocorrection causes latency increases
Soo your CO values are bad 
Maybe they are fine but you need positive VCORE offset

Do *no*t use positive *vcore offset* on the public CTR build
But it's for you to visualize , that your cores do not boost equally
This should be likely the first priority to fix before continuing memOC

CTR or








Releases · jedi95/BoostTester


Simple tool for generating loads that should trigger maximum CPU boost clocks. - jedi95/BoostTester




github.com




Both work, but CTR is more "realistic" on it's boost tester section
You can also track this on HWInfo with settings "CPU Snapshot pooling" - on Effective clock T0

EDIT:
TDC should be lower than both PPT & EDC
Soo near 135-150A
Scalar should move between 2X and 6X
Higher causes issues
Throttle temp should be at 90c

If you are on SMU 56.44(3) or 56.45 , then use EDC 400A
if you are on the later 1201+ with the "cache boost fix" then it makes no sense to open it up further
Any value you input there will hang at the CPU FUSE Limit, which is not bypassable unless you are in manualOC mode (allcore or CTR)
Soo don't worry about it
But 200-210A EDC is required for memOC
5600X will limit it to 120-125A, 5800X will limit it to ~140A

If you don't override your stock PBO limits, you do lose boost
Because FCLK and SOC take a lot from the boosting power-budget away

EDIT2:


Spoiler: Boost-Tester Example














If you can not sustain on each core the same boost frequency and don't want to spend hours finetuning it
Then it makes no sense to run a boost override which only causes clock stretching.
This stretching does add a latency penalty for autocorrection and frequency faking.
Fix that, there is no benefit running +XYZ frequency when it's not used anywhere


----------



## lmfodor

Veii said:


> I think that you are never hitting this +200 boost and clock stretch
> The readouts tell it
> 
> Two options , grab latest CTR and "boost test"
> See visually that not all cores are hitting the same peak frequency
> This autocorrection causes latency increases
> Soo your CO values are bad
> Maybe they are fine but you need positive VCORE offset
> 
> Do not use positive vcore offset on the public CTR build
> But it's for you to visualize , that your cores do not boost equally
> This should be likely the first priority to fix before continuing memOC
> 
> CTR or
> 
> 
> 
> 
> 
> 
> 
> 
> Releases · jedi95/BoostTester
> 
> 
> Simple tool for generating loads that should trigger maximum CPU boost clocks. - jedi95/BoostTester
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> Both work, but CTR is more "realistic" on it's boost tester section
> You can also track this on HWInfo with settings "CPU Snapshot pooling" - on Effective clock T0
> 
> EDIT:
> TDC should be lower than both PPT & EDC
> Soo near 135-150A
> Scalar should move between 2X and 6X
> Higher causes issues
> Throttle temp should be at 90c
> 
> If you are on SMU 56.44(3) or 56.45 , then use EDC 400A
> if you are on the later 1201+ with the "cache boost fix" then it makes no sense to open it up further
> Any value you input there will hang at the CPU FUSE Limit, which is not bypassable unless you are in manualOC mode (allcore or CTR)
> Soo don't worry about it
> But 200-210A EDC is required for memOC
> 5600X will limit it to 120-125A, 5800X will limit it to ~140A
> 
> If you don't override your stock PBO limits, you do lose boost
> Because FCLK and SOC take a lot from the boosting power-budget away
> 
> EDIT2:
> 
> 
> Spoiler: Boost-Tester Example
> 
> 
> 
> 
> View attachment 2485201
> 
> 
> 
> If you can not sustain on each core the same boost frequency and don't want to spend hours finetuning it
> Then it makes no sense to run a boost override which only causes clock stretching.
> This stretching does add a latency penalty for autocorrection and frequency faking.
> Fix that, there is no benefit running +XYZ frequency when it's not used anywhere


And I thought I'd made a good curve. I always preferred to assemble it manually, without CTR, but I'm going to use it to see what you're reviewing. I have a 5900x. So at EDC I'm fine. I should change the curve. I'm think I'm fine with PPT 220 and EDC 200, maybe TCD to 150 would it fine, right?
Scalar I leave to AUTO and Throttle temp is set to 85. The thing is the curve.. In the spoiler you may see the Effective Clock T0



Spoiler: HWInfo while running CB20


----------



## Veii

lmfodor said:


> And I thought I'd made a good curve. I always preferred to assemble it manually, without CTR, but I'm going to use it to see what you're reviewing. I have a 5900x. So at EDC I'm fine. I should change the curve. I'm think I'm fine with PPT 220 and EDC 200, maybe TCD to 150 would it fine, right?
> Scalar I leave to AUTO and Throttle temp is set to 85. The thing is the curve.. In the spoiler you may see the Effective Clock T0
> PS: So as not to be off topic, what are *RQZ*, I want to change it meanwhile!
> 
> 
> Spoiler: HWInfo while running CB20
> 
> 
> 
> 
> View attachment 2485202


RZQ is the metric


Spoiler














It's just the name of it like DQ & DQS (Data Bus & Data Bus Strobe)
DATA_BUS Bios values go in RZQ divided by , values
I don't know how to explain it, but i'm suspicious that Vermeer has far higher RZQ now.
What worked for Matisse, is not replicable on Vermeer

Cine R20 the normal way uses AVX2 extension - you will hit the EDC Fuse limit, before anything else and throttle
you can run more than 4.6ghz allcore
CTR you don't need to run any diagnose or use it's changed boost system.
It just is useful for you, to make Cinebench run with core affinity switching between each thread (Boost Tester field)
Else the boost tester github thing is fine too, just not 100% realistic

TM5 is a light SSE load.
You should be able to run the maximum boost frequency on all cores ~ on it
4850 or 4950


----------



## lmfodor

Ok


Veii said:


> RZQ is the metric
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2485204
> 
> 
> 
> It's just the name of it like DQ & DQS (Data Bus & Data Bus Strobe)
> DATA_BUS Bios values go in RZQ divided by , values
> I don't know how to explain it, but i'm suspicious that Vermeer has far higher RZQ now.
> What worked for Matisse, is not replicable on Vermeer


Ok, so when you said RZQ = 240ohm (questionable, should be 480ohm now), what I did is to divide 240/RTT5 + 240//RTT2 + 240/RTT4 = 228 ohms. So if I should be on 480ohm should I rise ProcODT a lot, or am I saying anything? I am completely noob but eager to learn!


----------



## lmfodor

Veii said:


> Cine R20 the normal way uses AVX2 extension - you will hit the EDC Fuse limit, before anything else and throttle
> you can run more than 4.6ghz allcore
> CTR you don't need to run any diagnose or use it's changed boost system.
> It just is useful for you, to make Cinebench run with core affinity switching between each thread (Boost Tester field)
> Else the boost tester github thing is fine too, just not 100% realistic
> 
> TM5 is a light SSE load.
> You should be able to run the maximum boost frequency on all cores ~ on it
> 4850 or 4950


Yes, the first thing I did was to build the curve without boost override, leave it at 0. I started with -30 in as much as I could and went down. Help me at CoreCycler and y-cruncher who quickly reported crash to me, then I was fixing. But I'm unbalanced because for CCD2 cores I can't exceed -20.. and in CCD1 the best cores the maximum that arrives was -15, having rest to go down in the remaining ones to -25.. I don't know how to stabilize her. I know it's off topic, if you have any recommendations send me a PM? Thank you!


----------



## Nighthog

Veii said:


> Good job
> tCKE 15 should be for 4400, likely tCKE 14 should suite here
> Although i think 13 would still cover this one jump upwards. It does for me at least


I never got it stable with 13 & 14 tCKE, only when I did turn it to 15 did I get a stable 20 cycle pass.

I updated BIOS to F33h and redoing it.
I found and odd bug with these SMU 55.78.0 these both are based on.

tCL = tCWL doesn't boot, Error [60] at post.
meaning tCL 16 & tCWL 16, tCL 18 & tCWL 18, tCL 20 tCWL 20 are no good for some reason.

tCL 19 & tCWL 18 OK, tCL 17 & tCWL 16 OK, 
But also works to use tCL 16 & tCWL 14, tCL 18 & tCWL 16.

tCWL needs -1 or -2 from tCL.


----------



## lmfodor

Veii said:


> Soo WR /2 works, good !
> well at least posts ~ stability checks will clear up the picture
> 
> RTT_PARK at /1 is far stronger than RTT_PARK /3
> Where /3 was too strong to the looks of it.
> If you go for /1 , lower VDIMM further ~ it's "not a good idea" to run strong RTT_PARK and high VDIMM
> a plain bad idea
> 
> High means 1.51+
> Unless the PCB can take it
> 
> TM5 test it , make it 4-5 cycles, and change to RTT_PARK /4
> See if that runs now
> Error 11 would relate to RTT_NOM
> It depends, RTT_WR will contineously auto autoadjust
> It's a bit more aggressive on /2 , but when you had PCB crashes on 1.55v, then you have to redo the RTTs
> I see them as dangerous even (beyond 1.55v) ~ if you really had this type of crashes
> 
> It makes me wonder what PCB you run (not a thaiphon burner report)


I just set RTT Park to 4.Maybe a slightly lower values in write or copy but pretty similar. I will test with these values. I don't know if you want me to try a higher procODT. Thanks!


----------



## Veii

lmfodor said:


> Ok
> 
> Ok, so when you said RZQ = 240ohm (questionable, should be 480ohm now), what I did is to divide 240/RTT5 + 240//RTT2 + 240/RTT4 = 228 ohms. So if I should be on 480ohm should I rise ProcODT a lot, or am I saying anything? I am completely noob but eager to learn!


On old metrics
RZQ/5 = 48ohm
RZQ/7 = 34.3ohm

Some bioses use direct AMD CBS values and have it that way
MSI uses written out values and goes only with full ohm values
It's questionable tho, if RZQ really is still 240ohm ~ i start to doubt it

ProcODT is an own thing, it is written out in correct ohm values
some have it up till 480ohm, some have it peaking at 240ohm or 120 & High-Z mode


lmfodor said:


> Yes, the first thing I did was to build the curve without boost override, leave it at 0. I started with -30 in as much as I could and went down. Help me at CoreCycler and y-cruncher who quickly reported crash to me, then I was fixing. But I'm unbalanced because for CCD2 cores I can't exceed -20.. and in CCD1 the best cores the maximum that arrives was -15, having rest to go down in the remaining ones to -25.. I don't know how to stabilize her. I know it's off topic, if you have any recommendations send me a PM? Thank you!


It's not that much offtopic, it's about lowering latency and L3 cache target-latency you can not hit
If both CCDs are that much different - at least let it hit the same peak frequency on the whole CCD
It can put CCDs to sleep, and per-core C-States do function since dLDO_injector is active after SMU 56.44 (1.2.0.0)

But an uneven CCD is not good at all
At best both CCDs can hold the same peak frequency and they should be able to hold advertised boost (4.8ghz)
On each of the cores - else it wouldn't pass validation.

Curve optimizer values are pre-programmed into the CPUs
doing a manual setting, overrides it with offsets
Doing a "allcore" one , is easier ~ but against all the community research that is done here on OCN and HWLuxx

Just a negative CO and an allcore value, does already fix most of the boosting budget issues
Cores will retain their pre-programmed offset values on stock , and just all-together request less VID
This you can compensate with a global vCore offset (just again do not use any offset on CTR, it will bug out to 1.55v)
* actually i think you can run boost-tester alone. It does nothing except run Cinebench ~ soo it shouldn't bug out

Anywho, you have to get your effective clock to be at least the advertised 4.8
If you think the whole CCD can run that +200 = 5ghz boost - go on 
But running a boost extend without being able to hold this frequency, causes latency penalties & auto correction because of clock stretching
Also generally makes the unit perform worse, as you destabilize/change the Voltage/Frequency Curve


----------



## Veii

Nighthog said:


> I never got it stable with 13 & 14 tCKE, only when I did turn it to 15 did I get a stable 20 cycle pass.
> 
> I updated BIOS to F33h and redoing it.
> I found and odd bug with these SMU 55.78.0 these both are based on.
> 
> tCL = tCWL doesn't boot, Error [60] at post.
> meaning tCL 16 & tCWL 16, tCL 18 & tCWL 18, tCL 20 tCWL 20 are no good for some reason.
> 
> tCL 19 & tCWL 18 OK, tCL 17 & tCWL 16 OK,
> But also works to use tCL 16 & tCWL 14, tCL 18 & tCWL 16.
> 
> tCWL needs -1 or -2 from tCL.


h*ck 
What did they mess up this time
Are you on a new microcode already ?
I wish ASRock wouldn't take more than a month to push an AGESA update to all of their boards 

What about CL14 , tCWL 16 ?
that was known to cause bugs


----------



## Veii

lmfodor said:


> I just set RTT Park to 4.Maybe a slightly lower values in write or copy but pretty similar. I will test with these values. I don't know if you want me to try a higher procODT. Thanks!
> View attachment 2485205


You want to lower procODT , generally lower increases the maximum possible FCLK
but procODT is needed for dimm powering - soo if we focus on ClkDrvStr and RTTs
you can lower procODT alltogether

Lower procODT means also lower possible SOC voltage
and generally allows lower voltage to run = better signal integrity = stacking effect of higher FCLK altogether
Test if RTT_WR /2 would even run.
We want to get it running, but it will not run with too weak RTT_PARK
We don't want high RTT_PARK, because at the end voltage multiplication (with impedance) will be too high, and DIMM-PCBs will crash or even die (>1.56v is dangerous , uncontrolled)

Soo weaker RTT_PARK = more VDIMM range before crash
stronger RTT_PARK = less vdimm works, but more ampere ends up on the dimms and heats them up exponentially more
My dimms on >1.66v are cold 
Currently playing with 1.7v on RTT_PARK /7 
fooling around

EDIT:
At the end you outweigh
Strong RTT_PARK with low voltage near 1.35-1.46v, but lower timings
Weak RTT_PARK with high voltage, with higher voltage starting point (1.5+) but harsher timings and usually less heat (just needs more babysitting to finetune it)


----------



## lmfodor

Veii said:


> Curve optimizer values are pre-programmed into the CPUs
> doing a manual setting, overrides it with offsets
> Doing a "allcore" one , is easier ~ but against all the community research that is done here on OCN and HWLuxx
> 
> Just a negative CO and an allcore value, does already fix most of the boosting budget issues
> Cores will retain their pre-programmed offset values on stock , and just all-together request less VID
> This you can compensate with a global vCore offset (just again do not use any offset on CTR, it will bug out to 1.55v)
> * actually i think you can run boost-tester alone. It does nothing except run Cinebench ~ soo it shouldn't bug out
> 
> Anywho, you have to get your effective clock to be at least the advertised 4.8
> If you think the whole CCD can run that +200 = 5ghz boost - go on
> But running a boost extend without being able to hold this frequency, causes latency penalties & auto correction because of clock stretching
> Also generally makes the unit perform worse, as you destabilize/change the Voltage/Frequency Curve


I didn't know that all core retain pre-programmed offset.. I will try with boost-tester! Honestly I wanted to achieve the highest frequency without Boost Override. If all core fix it I'll go in that way. Thanks for your great support!



Veii said:


> On old metrics
> RZQ/5 = 48ohm
> RZQ/7 = 34.3ohm
> 
> Some bioses use direct AMD CBS values and have it that way
> MSI uses written out values and goes only with full ohm values
> It's questionable tho, if RZQ really is still 240ohm ~ i start to doubt it
> 
> ProcODT is an own thing, it is written out in correct ohm values
> some have it up till 480ohm, some have it peaking at 240ohm or 120 & High-Z mode


Well I don't have much to say here, the truth I didn't understand how you got to the conclusion that I'm at 240ohms and it should be at 480ohms. For now your RTT recommendations and values greatly optimized my OC. I wonder where to get PCB info other than Taiphoon


----------



## lmfodor

@Veii you're very fast! Ok, lets test RTTWR/2 to see if it works and then adjust the RTT Park.. Thanks a lot


----------



## Nighthog

Veii said:


> h*ck
> What did they mess up this time
> Are you on a new microcode already ?
> I wish ASRock wouldn't take more than a month to push an AGESA update to all of their boards
> 
> What about CL14 , tCWL 16 ?
> that was known to cause bugs


F33h is latest with the (patch A) for USB connectivity issues. (F33f was used earlier)
Never tried tCWL higher than tCL.

I'm testing if tCL 15 with tCWL 14 will be stable right now. As it booted.
EDIT: tCL 15 seems stable (~7 cycle ok)
Needed to add +0.010V DRAM Termination voltage to stabilize, as far as I can tell for it to work.

EDIT2: tCL 14 with tCWL 16 doesn't boot, [F9], most likely can't run tCL14 @ 4266MHz unless I add more voltage.


----------



## T[]RK

Veii said:


> CTR you don't need to run any diagnose or use it's changed boost system.


I got CTR 2.0 RC5 and i got "Boost Tester" button, but i can't press on it. I have got P1 Profile activated only. I able to press only "Diagnostic", "Tune" and "Check Stability". Maybe it's not availible at my RC5...


----------



## kompira

Inspired by this psone's guide
[内存] 完全解析ZEN3（5800X）FCLK，能开即能稳！
and old knowledge
just a "lite" 2T rock stable set with [email protected]/s and tight subtimings


----------



## PuffyArgos

BarrettDotFifty said:


> Would you consider it possible for GDM disabled to run with the RTT as shown in my ZenTimings shot?


I do not pretend to be a master, I'm still working on understanding memory OC better myself. I can show you what has worked for me on an X570 board, the caveat being that I'm on a 3950x, not 5XXX. I believe the resistences are determined by what the board/chipset likes (x570, b550, b450, etc.).

Keep in mind that I am using single rank sticks, so our DDs and SDs will be different. I'm using 1-5-5-1-7-7, I believe you've correctly used 1-4-4-1-6-6.



Spoiler: ZenTimings












CPU is at 1.2125v
VDIMM is at 1.47v


----------



## Mr.Pink

@Veii i need help. i'm struggling with my ddr4 G.skill 4x8 F4-4000C18-8GVK, chip hynix djr H5AN8G8NDJR-TFC single rank. 
i can't find a good timing settings. my conf is ryzen 5800x+msi x570 unify (agesa 1.2.0.0)
i'm working with 3 fclk 1:1 1800, 1867, 1900, because CPU isn't stable at higher freq.
basically at each of fclk steps, i have poor bandwith and latency. here is an example


----------



## Martin778

Should I even bother tuning this? It's stock XMP with GDM ON (also the default XMP setting). 
1.1VSOC


----------



## Mr.Pink

Martin778 said:


> Should I even bother tuning this? It's stock XMP with GDM ON (also the default XMP setting).
> 1.1VSOC
> 
> View attachment 2485275


wow, wich ram do you use?


----------



## AmateurRanger

craxton said:


> yeah, i looked a little after i asked and found they said early april as well.
> 
> 
> thats the thing, theyre almost always one of the first. and MSI seems to be one of the last.
> but, ive had 4000mhz running on ALL patches since patch B was a thing in december.
> 
> have yet to see any update since 03/05 for the b550 board....
> msi may be last as i said, but theyre near always stable (have been for me)
> 
> 
> can you link this kit ? or pm it to me by chance??? SURE i dont need more bdie, but well
> 
> my 4sticks of tforce 3200c14 sticks are well....they have nothing near me to contend with now lol...
> sold all my ram this past month with my spare parts i.e. mobo, gpus, etc...
> 
> @ANYONE with 1.2.0.2 bios, have you tested usb dropout issues?
> unsure how, simply grab an iphone and try to jailbreak it. if it works then usb is perhaps solved,
> if not then its still busted....(perhaps, i truly dont have usb dropout issues. as someone stated ch3ckra1n
> doesnt like amd and doesnt run very well regardless?) it does however work on my uncles
> old phenom processor.... I dont have any whea errors telling me im having USB dropout issues
> tried running stock profile with 2 and just 1 dimm. but still the same.
> 
> (i mention jailbreaking an iPhone bc this is the ONLY time ive ever actually had an instance of
> anything related to USB issues or USB not working properly. but since i have no issues with the phone just copying files etc
> im now unsure i have a usb issue at all. NO I _*HATE IPHONE!!!*_ its for a child!
> 
> anyone experiencing USB dropout, are you having this at any ram frequency, on your mouse/keyboard, headphones,
> monitor, etc ???








Are you a human?







www.newegg.com





These. I got the white kit from Amazon. Newegg lately has some 10% deals ant his can be had for pretty good prices.

So here is the thing: there's actually another set of these with C19-21, those are known b-dies if I'm not mistaken. Also I believe there's a C19 flat version of these. Could just be different bins. The ones I got are C19-23 and I may want to take my words back a bit after doing some quick research, they might be C-die. Part number ends with BCRC. Thaiphoon Burner reads them as B-die but it isn't the most accurate thing in this world lol


----------



## Veii

Little updated timings, nothing special
Move around 48.7-48.9ns
Likely 48.8-48.7 in safe mode

Same latency as before but about 250-300MB/s faster Copy and 700MB/s faster Read
That's with the DF states off penalty , which turned my last setup from 48.9 to 49.6ns. Soo pretty much back to square zero
Oh also subtly higher tRFC and different powering @ 1.66v











kompira said:


> Inspired by this psone's guide
> [内存] 完全解析ZEN3（5800X）FCLK，能开即能稳！
> and old knowledge
> just a "lite" 2T rock stable set with [email protected]/s and tight subtimings
> View attachment 2485251


Браво ! 
He is a knowledgeable person - psone & 3600 on zen1 is not easy
Was going with his research too to learn a bit about 1x tFAW mode


Martin778 said:


> Should I even bother tuning this? It's stock XMP with GDM ON (also the default XMP setting).
> 1.1VSOC
> 
> View attachment 2485275


L3 cache latency, should be 10.2 not 10.4 - that's 4.85 not 4.95 effective clock
You can bother tuning the CPU a bit.
I expect near 1200-1300 GB/s Cache bandwidth for a 5950X


----------



## craxton

AmateurRanger said:


> they might be C-die. Part number ends with BCRC. Thaiphoon Burner reads them as B-die but it isn't the most accurate thing in this world lol


i know all to well how bad thaiphoon burner is, told me i got b-die sticks once before, yet
i had samsung E die...3600mhz (WORST STICKS I EVER HAD)
completly crashed my entire OS install, couldn get stable on ANY frequency at all.
was supposedly verified for AMD setups, but there was one character difference in the part number which stated on 
corsairs website (LPX) that stated it was in fact NOT for amd at all. 

sent those back and got a 970 evo ssd instead as i found the tforce dark kit 2x8 for 90 bucks at the time
i later bought a second set for 130. sad thing is both kits are bdie c14 flat, but the TRFC timings are different and
a few other timings are not the same, first kit being WAY better binned and the second 
having quite (those few i cant think of) looser timings. worked out tho, 

first kit was from amazon, second was from new egg. team cant tell me nothing on about why the product specs state 
there the EXACT same model numbers, but are in fact quite different actually.

you can write XPG and give them part number, serial number, and date it was made and they can tell you what die it is.
i know teamgroup does this.


----------



## lmfodor

Veii said:


> You want to lower procODT , generally lower increases the maximum possible FCLK
> but procODT is needed for dimm powering - soo if we focus on ClkDrvStr and RTTs
> you can lower procODT alltogether
> 
> Lower procODT means also lower possible SOC voltage
> and generally allows lower voltage to run = better signal integrity = stacking effect of higher FCLK altogether
> Test if RTT_WR /2 would even run.
> We want to get it running, but it will not run with too weak RTT_PARK
> We don't want high RTT_PARK, because at the end voltage multiplication (with impedance) will be too high, and DIMM-PCBs will crash or even die (>1.56v is dangerous , uncontrolled)
> 
> Soo weaker RTT_PARK = more VDIMM range before crash
> stronger RTT_PARK = less vdimm works, but more ampere ends up on the dimms and heats them up exponentially more
> My dimms on >1.66v are cold
> Currently playing with 1.7v on RTT_PARK /7
> fooling around
> 
> EDIT:
> At the end you outweigh
> Strong RTT_PARK with low voltage near 1.35-1.46v, but lower timings
> Weak RTT_PARK with high voltage, with higher voltage starting point (1.5+) but harsher timings and usually less heat (just needs more babysitting to finetune it)


Hi @Veii! RTT_Park 4 worked well with good temps! Reading your commentes I don't know what I have to set as final value in RTT_Park. The previous value was 1.. but it will heat up my memories right? Maybe try 3? what should I do? Thanks!


----------



## Veii

lmfodor said:


> Hi @Veii! RTT_Park 4 worked well with good temps! Reading your commentes I don't know what I have to set as final value in RTT_Park. The previous value was 1.. but it will heat up my memories right? Maybe try 3? what should I do? Thanks!
> 
> View attachment 2485301


whatever allows you to run 1.55v , posts and run
as you had powering issues

Out of my testing, stronger RTT_Nom, allowed more voltage to work out 
But i also think , that it limits "minimum working" voltage too

You can try and replicate my 15-15-15 set for you , as "stepup" from the tRCD 16 one


----------



## lmfodor

Veii said:


> whatever allows you to run 1.55v , posts and run
> as you had powering issues
> 
> Out of my testing, stronger RTT_Nom, allowed more voltage to work out
> But i also think , that it limits "minimum working" voltage too
> 
> You can try and replicate my 15-15-15 set for you , as "stepup" from the tRCD 16 one


Well, I'm at 1.55v and only run TM5 1usmusv3 once. Temperatures are on edge (for me it would be 55 degrees) I had to freeze the ambient temperature. I don't know if I could take it with another test. In fact I usually try Memtest Deluxe and leave it overnight until I have at least a coverage of 400x Latency is better because I ran the program that you suggested to me from sysinternals and disable several services that should not be running in background

Actually the real test is playing, which is what I use the PC for. With the heat of the GPU. I only have one fan on top of the memories spinning to 1100RPM.. I could try another faster or not, maybe replace that glue /thermal pad that comes with the heatsink of Gskill Tridenz Neo.I have some thicker pads to cool NVMEs.. or else I buy one for memories and try.

What else do think I should improve now? In parallels I'm working with my PBO. I will reset all values to AUTO and try CTR boost tester and start over with the curve.. Thanks!


----------



## Veii

lmfodor said:


> What else do think I should improve now? In parallels I'm working with my PBO. I will reset all values to AUTO and try CTR boost tester and start over with the curve.. Thanks!


Get tCKE to work , 9 or 16 as a value will guaranteed work @ 3800MT/s
If not then it's an CKE Low & CKE High issue
(i don't have it in my mind right now which was which , RTT_PARK or RTT_NOM , one of both was CKE LOW)

If CKE 9 for 3800 does cause you issues, then it's up to the issue if CKE Low (the lower part of the sinus wave)
or CKE High (the peaking part of the sinus wave which needs a cut)
errors between test are CKE High
Wake up issues or "programm shutdown crashes" / "idle crashes" have to be CKE Low (drooping too low)

RTTs both are behaving like the game ping-pong (tabletop tennis ?!)
One hits the signal down from a specific border, the other has to hit/push the signal up again , soo it creates a nicely fluid signal wave
We want RTT_WR to function, as this automatically adjusts the "border size" and the phase (stupidly speaking)

I'm still learning as we speak, but you do want CKE to be able to suspend in time
Else the heat gets out of control
And mostly only stresstests do fully fill all ICs
Games barely do ~ soo these thermals here are still a worst case scenario

You can make a profile and test if 1.58 would post ,
If yes, then the RTTs are correct
But before that get tCKE to function "in time"
What you do with CAD_BUS, CAD_BUS SETUP & RTTs, is a never-ending fight
higher VDIMM needs more filtering, needs less strong ClkDrvStr, less procODT different RTTs & you end up fighting again against timings stability when lower ones want more input voltage, but PCBs get more sensitive on high MT/s and need less arriving current
and so on... Never ending fight 

I think you should start with having tCKE to run, eating this little latency penalty it gives
Being sure that your RTTs are fine for higher voltage, but staying on the lowest possible one
Working to get tRDWR to be tRCD_RD / 2 (dual rank +2)
Flattening out primaries
Getting tRRD and tWTR as low as possible ~ after you had to increase them, in order to lower primaries
Decreasing voltage again
* high tWR and tRFC is not a big latency issue ~ when primaries are low, it still ends up positive & beneficial
** i had to start with tRDWR 22 and move step by step down. latency is identical only Copy does decrease/increase by too high tRDWR








EDIT:
*** don' t move your mouse while testing with Aida64 and use the Start Benchmark Button, soo it fully turbo's up (in case you don't know)
You might also want to give farag2/Windows-10-Sophia-Script a look 
69 Processes or lower should be running on an OS start


Spoiler


----------



## lmfodor

Veii said:


> t tCKE to wo





Veii said:


> Get tCKE to work , 9 or 16 as a value will guaranteed work @ 3800MT/s
> If not then it's an CKE Low & CKE High issue
> (i don't have it in my mind right now which was which , RTT_PARK or RTT_NOM , one of both was CKE LOW)
> 
> If CKE 9 for 3800 does cause you issues, then it's up to the issue if CKE Low (the lower part of the sinus wave)
> or CKE High (the peaking part of the sinus wave which needs a cut)
> errors between test are CKE High
> Wake up issues or "programm shutdown crashes" / "idle crashes" have to be CKE Low (drooping too low)
> 
> RTTs both are behaving like the game ping-pong (tabletop tennis ?!)
> One hits the signal down from a specific border, the other has to hit/push the signal up again , soo it creates a nicely fluid signal wave
> We want RTT_WR to function, as this automatically adjusts the "border size" and the phase (stupidly speaking)
> 
> I'm still learning as we speak, but you do want CKE to be able to suspend in time
> Else the heat gets out of control
> And mostly only stresstests do fully fill all ICs
> Games barely do ~ soo these thermals here are still a worst case scenario
> 
> You can make a profile and test if 1.58 would post ,
> If yes, then the RTTs are correct
> But before that get tCKE to function "in time"
> What you do with CAD_BUS, CAD_BUS SETUP & RTTs, is a never-ending fight
> higher VDIMM needs more filtering, needs less strong ClkDrvStr, less procODT different RTTs & you end up fighting again against timings stability when lower ones want more input voltage, but PCBs get more sensitive on high MT/s and need less arriving current
> and so on... Never ending fight
> 
> I think you should start with having tCKE to run, eating this little latency penalty it gives
> Being sure that your RTTs are fine for higher voltage, but staying on the lowest possible one
> Working to get tRDWR to be tRCD_RD / 2 (dual rank +2)
> Flattening out primaries
> Getting tRRD and tWTR as low as possible ~ after you had to increase them, in order to lower primaries
> Decreasing voltage again
> * high tWR and tRFC is not a big latency issue ~ when primaries are low, it still ends up positive & beneficial
> ** i had to start with tRDWR 22 and move step by step down. latency is identical only Copy does decrease/increase by too high tRDWR
> View attachment 2485334
> 
> EDIT:
> *** don' tmove your mouse while testing
> You want to give farag2/Windows-10-Sophia-Script a look
> 69 Services or lower should be running on an OS start
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2485335


----------



## lmfodor

Hello Veii, if you are learning while writing that we are left to those of us who are just getting started!! 😀 I'm having a hard time following you, really. Okay, so just to summarize next step,

set CKE to 9. How do I know if it cause issues? running TM5?
rising VDIMM to 1.58 to see if I get the POST
get tRDWR to be tRCD_RD/2 and there I am fine since I am at 16/8.. Should I go to 14/7?
go down tRRD and tWTR, I'm at 3 and 10.should I go down even more?
Meanwhile I set back my PBO to Auto (and debloat windows with your tool) surprisingly the numbers are slightly better than with my PBO limits and Curve.. the question is.. could the base values, I mean, PBO limits on Auto (EDC too low), not allow me to continue making the memory settings?
These are the values with PBO auto, and C-States enabled again..










Last question, in your timings I see 15-15-15-15-30. My basic question is you don't follow the rule of tRDWR to be tRCD_RD/2, and you have a DR memories, Am I right?


----------



## Veii

lmfodor said:


> set CKE to 9. How do I know if it cause issues? running TM5?


Pretty much, it will spill out errors if it's wrong, and can make the OS crash randomly without any tests running


lmfodor said:


> rising VDIMM to 1.58 to see if I get the POST


Afterwards yes, that means you moved away from the 1.55/1.56v issue and RTTs are better and not thaat strong anymore


lmfodor said:


> get tRDWR to be tRCD_RD/2m and there I am fine since I am at 16/8.. Should I go to 14/7?


Yours is already fine, but you want to get a 15-15-15 set now stable or move up in FCLK


lmfodor said:


> go down tRRD and tWTR, I'm at 3 and 10. should I go down even more?


nono, first increase them soo you can lower primaries. similar to what i run
Then lower them after primaries are already low
15-15-15 should be easy on 1.52v or higher 
14-14-14 would need around the 1.54-1.56 mark. On slower sets 1.5v but they utilize strong RTTs
15-15-15 is fine , scalable till 4000MT/s without an issue bellow 1.6v 
4200 15-15-15 = 3800 13-13-13 , would require you to move in the 1.64-1.66v range 
* i think it's fine, but you have to see how you cool them and again need to rework RTTs to prevent PCB crashing or even PCB/IC dying 
** beyond 1.55v is already a dangerous territory


----------



## lmfodor

Veii said:


> Pretty much, it will spill out errors if it's wrong, and can make the OS crash randomly without any tests running
> 
> Afterwards yes, that means you moved away from the 1.55/1.56v issue and RTTs are better and not thaat strong anymore
> 
> Yours is already fine, but you want to get a 15-15-15 set now stable or move up in FCLK
> 
> nono, first increase them soo you can lower primaries. similar to what i run
> Then lower them after primaries are already low
> 15-15-15 should be easy on 1.52v or higher
> 14-14-14 would need around the 1.54-1.56 mark. On slower sets 1.5v but they utilize strong RTTs
> 15-15-15 is fine , scalable till 4000MT/s without an issue bellow 1.6v
> 4200 15-15-15 = 3800 13-13-13 , would require you to move in the 1.64-1.66v range
> * i think it's fine, but you have to see how you cool them and again need to rework RTTs to prevent PCB crashing or even PCB/IC dying
> ** beyond 1.55v is already a dangerous territory


Ok, I'll do it, at least start with the tCKE to 9. I wonder if my current settings with PBO on Auto will allow me to continue or if I should rise some values like EDC... You may see in my previous post my timings with PBO on Auto, L3 seems to be more consistent.



Veii said:


> wo options , grab latest CTR and "boost test"
> See visually that not all cores are hitting the same peak frequency
> This autocorrection causes latency increases
> Soo your CO values are bad
> Maybe they are fine but you need positive VCORE offset
> 
> Do *no*t use positive *vcore offset* on the public CTR build
> But it's for you to visualize , that your cores do not boost equally
> This should be likely the first priority to fix before continuing memOC
> 
> CTR or
> 
> 
> 
> 
> 
> 
> 
> 
> Releases · jedi95/BoostTester
> 
> 
> Simple tool for generating loads that should trigger maximum CPU boost clocks. - jedi95/BoostTester
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> Both work, but CTR is more "realistic" on it's boost tester section
> You can also track this on HWInfo with settings "CPU Snapshot pooling" - on Effective clock T0


I went crazy trying to make CTR work, I put all the required values, until I got to reset the BIOS and start from scratch, with XMP and the few requirements, C-states enabled, LLC Auto, phases in Extreme mode, and CPPC - Enabled, CPPC Preferred Cores - Enabled. 
I start with the Diagnosis.. runs CB20 and stays.. doing nothing. Wait 30 minutes. then try the stability test and it gives me error. I just wanted to try the Boost Tester, but it's disabled. After rebooting CTR shows: 


Spoiler: CTR Errors



*ClockTuner for Ryzen 2.0 RC5 by 1usmus*
AMD Ryzen 9 5900X 12-Core Processor
ASUS ROG CROSSHAIR VIII HERO (WI-FI)
BIOS ver. 3401 SMU ver. 56.50.00
TABLE ver. 3672069
DRAM speed 3800 MHz
04/05/2021 01:02:03


Phoenix - hello there 
CTR completed diagnostic in alternative mode


DIAGNOSTIC RESULTS
AMD Ryzen 9 5900X 12-Core Processor
CPU VID: 1200
CPU TEL: 0
Max temperature: 60°
Energy efficient: Infinity
Your CPU is PLATINUM SAMPLE
Recomended CCX delta: 0
Theoretical maximum CCX delta: 25
Recomended values for overclocking (P1 profile):
Reference voltage: 1175 mV
Reference frequency: 4225 MHz
Recomended values for overclocking (P2 profile):
Reference voltage: 1275 mV
Reference frequency: 4375 MHz
Recomended values for undervolting:
Reference voltage: 1000 mV
Reference frequency: 3875 MHz

Phoenix deactivated!


01:25:34: Stability check!
1:25:40 AM: CCX1 overclocking failure detected!
1:25:40 AM: Thread# 0 fall down!
1:25:41 AM: Stress test stopped.
Phoenix ready!
Cinebench R20 started


----------



## Veii

lmfodor said:


> I went crazy trying to make CTR work, I put all the required values, until I got to reset the BIOS and start from scratch, with XMP and the few requirements, C-states enabled, LLC Auto, phases in Extreme mode, and CPPC - Enabled, CPPC Preferred Cores - Enabled.
> I start with the Diagnosis.. runs CB20 and stays.. doing nothing. Wait 30 minutes. then try the stability test and it gives me error. I just wanted to try the Boost Tester, but it's disabled. After rebooting CTR shows:


Yes i didn't expect Yuri to put in placeholder buttons
Then with the next free public release it could work
Or with the Patreon 2.1 release, it does work for sure

But we can ignore CTR then
Really thought he would make it publicly working when the button exists.
Next release then 

Boost Tester github app works, but it doesn't push too that much load to each core
And setting up y-cruncher , 48min for each core is annoying too


lmfodor said:


> Ok, I'll do it, at least start with the tCKE to 9. I wonder if my current settings with PBO on Auto will allow me to continue or if I should rise some values like EDC.


Increase the limits. PPT +40, TDC +15 EDC + 30 of the stock limits
or just fully run EDC @ 400A.
The answer is yes, memoryOC & SOC do go into the powerbudget and lower potential boost


----------



## lmfodor

Veii said:


> Yes i didn't expect Yuri to put in placeholder buttons
> Then with the next free public release it could work
> Or with the Patreon 2.1 release, it does work for sure
> 
> But we can ignore CTR then
> Really thought he would make it publicly working when the button exists.
> Next release then
> 
> Boost Tester github app works, but it doesn't push too that much load to each core
> And setting up y-cruncher , 48min for each core is annoying too
> 
> Increase the limits. PPT +40, TDC +15 EDC + 30 of the stock limits
> or just fully run EDC @ 400A.
> The answer is yes, memoryOC & SOC do go into the powerbudget and lower potential boost


It seems that with tCKE at 9 I have a slight increase in latency. It's amazing how leaving PBO all in Auto and just climbing the PBO limits I have almost the same value as with my previous curve! 8800 on CB20









Ok, I will run some test in TM5 to see the stability. What do you think about the increase of latency changing only tCKE? Thanks!!


----------



## lmfodor

Veii said:


> It makes me wonder what PCB you run (not a thaiphon burner report)


The only review I found of my memory kit was made by Igor's Lab. They have the same ones because I also I found them in a review of the new CTR .. you can see the PCB info in there (thaiphoon) It is a good review, but I was hoping that it will develop more overclocking of these memories. 
Does the new high-end RAM for Ryzen 5000 live up to its promise? - G.SKILL DDR4-3800 CL14 2x 16GB kit put through its paces | igor´sLAB




Sent from my iPhone using Tapatalk Pro


----------



## Veii

lmfodor said:


> What do you think about the increase of latency changing only tCKE? Thanks!!





Veii said:


> I think you should start with getting tCKE to run, eating this little latency penalty it gives
> Being sure that your RTTs are fine for higher voltage, but staying on the lowest possible one
> Working to get tRDWR to be tRCD_RD / 2 (dual rank +2)
> Flattening out primaries
> Getting tRRD and tWTR as low as possible ~ after you had to increase them, in order to lower primaries
> Decreasing voltage again





lmfodor said:


> The only review I found of these memories was made by Igor's Lab. They have the same ones because I also I found them in a review of the new CTR .. you can see the PCB info in there (thaiphoon) It is a good review, but I was hoping that it will develop more overclocking of these memories.


Same product numbers still can lead to different used PCBs and chips
But it likely is the same, as they are "limited stock"
============================
I wonder if i can get 2:1 mode to work
7ns are to beat soo about 6 jumps , or 400MT/s hmm
Wonder if Crucial Max B-dies can run 4600 CL16-16
Wonder if it's worth to spend 180 bucks on a better b-dies bin
Probably not, saving for cezanne likely makes more sense


----------



## lmfodor

Veii said:


> Same product numbers still can lead to different used PCBs and chips
> But it likely is the same, as they are "limited stock"
> ============================
> I wonder if i can get 2:1 mode to work
> 7ns are to beat soo about 6 jumps , or 400MT/s hmm
> Wonder if Crucial Max B-dies can run 4600 CL16-16
> Wonder if it's worth to spend 180 bucks on a better b-dies bin
> Probably not, saving for cezanne likely makes more sense


I think you can save it. I bought this kit because it seemed optimized for the new Rayzen but I don't think the price is justified, with good knowledge you save some money.

What do yo think about my last results with the increase of tCKE to 9? It’s running fine, at this moment is on the 7th cycle of TM5 without errors .. I notice a little increase in latency. Could it be? How should I continue? increasing the voltage more to see if the RTT support it? should I test that with TM5?

Sent from my iPhone using Tapatalk Pro


----------



## Veii

lmfodor said:


> What do yo think about my last results with the increase of tCKE to 9? It’s running fine, at this moment is on the 7th cycle of TM5 without errors .. I notice a little increase in latency. Could it be?


You don't read what i write
3rd time mentioned, that it's normal. Accept this increase
Functional powerdown mode is beneficial for thermals and stability
You can get that latency later away. 0.3ns is "little" it's a big increase but you can fix it.
You will already win a lot if you fix your cores

Boost Tester jedi95/BoostTester test at least that all cores hit the same stock frequency
if not, you have to use negative curve optimizer, and later ontop a bit of positive vcore offset


lmfodor said:


> How should I continue? increasing the voltage more to see if the RTT support it?


Also wrote it for the 2nd time (now 3rd)
See if it can even boot up - if not , redo RTTs till it can boot it. Then later go down again and find minimum voltage limits.
Or instead of minimum, stay at acceptable if thermals are now better with tCKE and work on lowering timings.

Makes more sense at the end , to go with lower primaries


----------



## lmfodor

Veii said:


> You don't read what i write
> 3rd time mentioned, that it's normal. Accept this increase
> Functional powerdown mode is beneficial for thermals and stability
> You can get that latency later away. 0.3ns is "little" it's a big increase but you can fix it.
> You will already win a lot if you fix your cores
> 
> Boost Tester jedi95/BoostTester test at least that all cores hit the same stock frequency
> if not, you have to use negative curve optimizer, and later ontop a bit of positive vcore offset
> 
> Also wrote it for the 2nd time (now 3rd)
> See if it can even boot up - if not , redo RTTs till it can boot it. Then later go down again and find minimum voltage limits.
> Or instead of minimum, stay at acceptable if thermals are now better with tCKE and work on lowering timings.
> 
> Makes more sense at the end , to go with lower primaries


Yes, I read you !! what happens is that for example re doing the RTTs is still not easy for me. In fact, I had read about "best configurations" that many repeated but you have helped me with concrete data and everything improved a lot! Understood about the latency, I continue with the procedure. So far very happy with the result. I'm going around the to improve the curve! Thank you very much for all the help!!


Sent from my iPhone using Tapatalk Pro


----------



## dk_mic

I have noticed i can go this low with VDDP and VDDG CCD.
0.8 V on both resulted in WHEA, but 0.82 (in BIOS) is totally stable.
Are there any benefits or disadvantages of having it that low?









Another thing: Any advice on how to get tRCDRD down to 14?


----------



## Veii

dk_mic said:


> I have noticed i can go this low with VDDP and VDDG CCD.
> 0.8 V on both resulted in WHEA, but 0.82 (in BIOS) is totally stable.
> Are there any benefits or disadvantages of having it that low?
> View attachment 2485350
> 
> 
> Another thing: Any advice on how to get tRCDRD down to 14?


SETUP times are for 3600 not 3800MT/s
3-3-15 is for 3800
AMD max overclocking voltage Voltage descriptions
"How to get tRCD_RD down to 14"
add 60-70mV on your current VDIMM and likely increase tRRD and tWTR to something similar i run
6-8-24 & 5-14
SD, DDs to 1-4-4-1-6-6 for dual rank
later you can go for 5-7-20-4-12
then for 4-5-16-4-10

Good luck ! 
you likely might need tCKE 9 or tCKE 16 for taming voltage beyond 1.54+
between1.54-1.56 is normal for a flat 14-14-14-14 set
else at least 1.5v with too strong RTT_PARK
you'll figure it out, keep trying


Spoiler: Something like this















EDIT:
I start to figure out a pattern for SD, DD's
They have a direct connection with tRRD and tWTR
Their correctness also influence minimum tRDWR ~ which is one of the main perf boost timings 

Soon more to it
You guys might have noticed my strange tWTR, there is a reason behind it
But it's still very experimental
I need to get low tWTR_L to run, near the 2-6 range
Need to understand how to work with that one


----------



## Nighthog

I saw you guys use [RZQ/6, RZQ/3, RZQ/3] and decided to explore it a little more than I have.

My 4266/2133 4x8GB settings I had stable also work with those [6/3/3] *IF* I Increase my DRAM Voltage from 1.690->1.710V to go with the change from my earlier [RZQ/6, RZQ/3, RZQ/1] go-to setup.

Otherwise I've been trying to lower tRRDS/tRRDL & tWTRS/tWTRL but anything lower just returns errors.


----------



## wden

zGunBLADEz said:


> try different bios i got bad luck with old bioses on that regard... i only have 5 bios to choose from in this board.. one of them is useless. the oldest one overclock the highest but it have poor l3 readings and no 1900 fclk and no 3800 achievable with this particular kit... 32gb gskill b die old old kit
> the other ones are a mix bag... Latest 3 one have that l3 bug thingy that i have been fighting for ahwile.. technically all of them have it on static overclock...
> cant use musmus ctr on the last 2 so i stick to 1803 bios for now.. Latest bios fixed the random crashes on pbo but l3 is limited to 1000s on l3s (boosting @ 46.50x on all cores. get more than that on [email protected]) as you see amd is well aware of this.... outside pbo overclocking this cpu is useless.... i would need ctr for that and having a hybrid oc but the l3 crash still there.
> 
> 
> what i have experience so far cpu/mhz =====> ram/flck and everything else... and amd eco system is a beta tester bug paradise


Thanks, I hear ya. I'm going to stick right now with 3733/1836. Will try to lower timings instead and fine tune it instead. Yeah this kit is old(date is Nov. 2018) as you mentioned, but I didn't know if that would be a potential cause for not being able to match some of the results of other g.skill 32GB b-die kits.
Hopefully the later BIOS to come out will be better for ocing.


----------



## BarrettDotFifty

PuffyArgos said:


> I do not pretend to be a master, I'm still working on understanding memory OC better myself. I can show you what has worked for me on an X570 board, the caveat being that I'm on a 3950x, not 5XXX. I believe the resistences are determined by what the board/chipset likes (x570, b550, b450, etc.).
> 
> Keep in mind that I am using single rank sticks, so our DDs and SDs will be different. I'm using 1-5-5-1-7-7, I believe you've correctly used 1-4-4-1-6-6.
> 
> 
> 
> Spoiler: ZenTimings
> 
> 
> 
> 
> View attachment 2485255
> 
> CPU is at 1.2125v
> VDIMM is at 1.47v


It turned out you were right. Setting ClkDrvStr to 40 Ohm and ProcODT to 40 Ohm, GDM disabled at 1T allowed me to boot just fine and shaved off a couple ns in latency as well, with a slight adjustment to the tertiaries. Running TestMem now but so far it seems stable. Thanks.


----------



## craxton

Veii said:


> farag2/Windows-10-Sophia-Script


i gotta assume this is a process killer? so one doesnt have to task/force kill processes and services?


----------



## jomama22

zGunBLADEz said:


> try different bios i got bad luck with old bioses on that regard... i only have 5 bios to choose from in this board.. one of them is useless. the oldest one overclock the highest but it have poor l3 readings and no 1900 fclk and no 3800 achievable with this particular kit... 32gb gskill b die old old kit
> the other ones are a mix bag... Latest 3 one have that l3 bug thingy that i have been fighting for ahwile.. technically all of them have it on static overclock...
> cant use musmus ctr on the last 2 so i stick to 1803 bios for now.. Latest bios fixed the random crashes on pbo but l3 is limited to 1000s on l3s (boosting @ 46.50x on all cores. get more than that on [email protected]) as you see amd is well aware of this.... outside pbo overclocking this cpu is useless.... i would need ctr for that and having a hybrid oc but the l3 crash still there.
> 
> 
> what i have experience so far cpu/mhz =====> ram/flck and everything else... and amd eco system is a beta tester bug paradise


It really should be noted that aida's l3 bandwidth tests aren't exactly real world scenarios nor are their bugs actually affecting your work or gaming in any meaningful way. Remember, all those bandwidth tests are doing to filling the l3 with data and then reading out that using instructions that they know will find the cached data in l3.

This is not real world at all nor actually inherent of how well l3 will be read from each core in any other scenario. The l3 bug in aida is/was just an issue of pulling every core out of sleep or low idle state and properly writing and reading from l3 in the time the test gives it to do so.

If the instructions from aida were predicted in the prefetch to be performed fastest by only utilizing a handful of cores, then that's what it would do and that's why you would have low l3 scores.

Those bandwidth tests are really just attempting to trick the cpu into filling up l3 and ONLY l3, which would never happen, ever, in the real world. Some data would go to l1, some would go to l2, and some would make it's way to dram.

I'll give you this job if you're up for it. Go find some program, game, w.e., where you see any difference if it's result, where it's time, score or fps, that are outside variance while keeping all other factors equal (clocks, memory, etc).

Core bandwidth to the l3 cache is not going to change no matter what changed they make for aida's l3 to read differently. 

My guess as to what was happening in older bios' with pbo and aida's l3 test is that the algorithm to predict what power requirement was needed for those tests exceeded edc, so power limits kick in and reduce with core clocks or amount of cotes/thread (most likely the latter). At the same time, the instructions were predicted to only need to use a handful of cores/threads anyway. In turn, instead of using every thread available to read/write/copy data to l3 (which is needed to maximize and get a maximum bandwidth reading from the l3 to the cores) it was only using a few.

Having a lower edc in this situation would exacerbate this issue, as we saw with older bios'. My guess is all amd did was says "Look, under this exact coding scenario, allow all cores to activate, ignore the branch predictions and prefetcher". Edc still plays a role in just how much bandwidth you get from l3 and pbo in newer bios', so they did not touch any part of pbo's algo to change this.

Much older bios' had even all core oc's l3 cut in half, but only on the 5900 and 5950, leading me to believe that it most definitely had/has somthing to do with prediction of thread creation and core utilization. It probably had no problem just running the code execution all on the same die/ccx (remember, that is genuinely what you want to happen to reduce core to core latency penalties). 

Really, all I'm saying is don't take aidas l3 test as some gospel of what the cpu is doing everywhere else. It's not some end all be all test of how the cpu works (or the memory for that matter). 

I would much rather have higher boost and better benchmark scores, higher fps, better production times than caring about what aida's l3 cache bandwidth test reads.


----------



## mongoled

Veii said:


> Really no, i didn't expect to see a tRCD 16 4000 kit
> the timings look runnable by my 4000 kit - and soo i'm sceptical of this A0 readout
> But sadly no. It probably would need a teardownt to check
> A3's are rare. i got my only view on the crucials because crucial does as always own things and redefines JEDEC by their technical team
> The PCB i've seen is neither A1 nor A2 - and A0 beyond 4133 will fail miserably, unless you do some powering tweaks
> 4000 is usually the highest they sell it, but with a custom PCB then - Viper 4000s are custom A0's. I thought at first it was A1 on mine
> 
> That would be 4400 tRCD 18 , instead of 19 - hmm, i'm interested curious now too
> But then it depends on the manufacture. If this was only crucial


CMK16GX4M2Z4000C16

The Corsairs referenced above look to be on an A2 PCB.



http://imgur.com/a/2wzOpln


----------



## nada324

@Veii Thanks for your tips, but after trying 536 same error 13, also tried to lower vdimm -10 to 1.490v from 1.5, and rtt to 436 and same issue, for error #11 tried trc 45, same issue;
I read on the calculator that it can be tras +1, tried it but no luck. Also tried puting on it more vdimm to 1.53v but now it would throw error #2 and error #12, read that its a resistence or vdimm issue so tried changing cad bus with no luck, so i changed ProcODT and seems to be fixed. 
So stronger RTT means -1? or +1?


----------



## Veii

nada324 said:


> @Veii Thanks for your tips, but after trying 536 same error 13, also tried to lower vdimm -10 to 1.490v from 1.5, and rtt to 436 and same issue, for error #11 tried trc 45, same issue;
> I read on the calculator that it can be tras +1, tried it but no luck. Also tried puting on it more vdimm to 1.53v but now it would throw error #2 and error #12, read that its a resistence or vdimm issue so tried changing cad bus with no luck, so i changed ProcODT and seems to be fixed.
> So stronger RTT means -1? or +1?
> 
> View attachment 2485380


Stronger RTT means more impedance, means lower divider
i wrote it once , twice , 3 times already
#11 and #1 go together , they can also be RTT_NOM related and they can be voltage related
Error 1 is tRRD, tWTR (combination) related
if it turned into 11's it's still them or RTT_NOM


----------



## nada324

Veii said:


> Stronger RTT means more impedance, means lower divider
> i wrote it once , twice , 3 times already
> #11 and #1 go together , they can also be RTT_NOM related and they can be voltage related
> Error 1 is tRRD, tWTR (combination) related
> if it turned into 11's it's still them or RTT_NOM


 Thank you, and for error #2 same as #12 what it can be vdimm or procodt?


----------



## Veii

nada324 said:


> Thank you, and for error #2 same as #12 what it can be vdimm or procodt?


Pretty much, but it appears randomly
I lack more data

it can be anything from RTT to CAD_BUS
any type of voltage or resistance


----------



## PuffyArgos

@Veii @mongoled

Hey guys, I just wanted to drop back in and say thank you for the help some months ago. I got pulled away for a bit during the pandemic (seems counter-intuitive huh?), but I'm back on and after it.

Last time we had correspondence you were helping me with testing software and wanted to see some results of my 1900 1:1:1 settings. Apologies it has taken me a while, I hope it is still relevant. I've noticed some of the methodology has changed, such as tke, setups, Rtt settings, and lower tCRDWR. I plan to rebuild my system on a b550 board with updated memory topology; when I've done this I will run some benchmarks for the spreadsheet (after stability checks of course).

My recent focus has been on tightening down the 3600 MT/s. I'm having trouble getting it to POST with tRDWR at 7. Do you think this is related to my tWR being too low at 10?

Also, what are your thoughts on running ClkDrvStr at 120 ohms in my 3800 MT/s setup?

I appreciate your thoughts, thanks guys.



Spoiler: 3600 MT/s












VDIMM - 1.47v





Spoiler: 3800 MT/s












VDIMM - 1.58v


----------



## PuffyArgos

BarrettDotFifty said:


> It turned out you were right. Setting ClkDrvStr to 40 Ohm and ProcODT to 40 Ohm, GDM disabled at 1T allowed me to boot just fine and shaved off a couple ns in latency as well, with a slight adjustment to the tertiaries. Running TestMem now but so far it seems stable. Thanks.


That's really great to hear. Be sure to post a screenshot of your updated ZenTimings if you're stable.


----------



## Veii

PuffyArgos said:


> My recent focus has been on tightening down the 3600 MT/s. I'm having trouble getting it to POST with tRDWR at 7. Do you think this is related to my tWR being too low at 10?
> 
> Also, what are your thoughts on running ClkDrvStr at 120 ohms in my 3800 MT/s setup?


Give 1-5-4-1-7-6 SD,DD a try 
with tRDWR 7 tWRRD 3

120ohm on x8 gb is a bad idea
especially pairing high voltage and RTT_PARK /5 is a very bad idea 

tRAS need to be 28 here - soo tRC should be 42
You should be able to run tRDWR 6 not 7 , but you have issues elsewhere as it seems

Low tRRD & tWTR are not that beneficial , compared to low primaries


----------



## neox387

@Veii

About all cores boosting to the same frequency, maybe it's only for the 5600x but I need at least +175Mhz to be able to reach lowest memory latency possible. 

I had a curve set to +50 gave me 52.7ns, +200 with curve at 0 gives 52.2ns ..


----------



## MrHoof

Hello, First time posting here.
System is in a coolermaster n200p with no fan on the RAM thats why my temps get quite high.
Well those sticks dont seem to care much about temperature, over 1 month 0 WHEA in Eventlogger. 
Today I updated the bios and retestet my OC and everything seems still stable.
Just wanted to know if anyone of you guys see anything I could improve or something that is really off. 

Asus x570-i itx
CO: Best 2 Cores -15 others -30
ppt:146 tdc:95 edc:160
RAM XMP: Gskill 3600 cl17-18-18-18-35 A2(99% sure)
1.51v vdimm


----------



## Veii

neox387 said:


> @Veii
> 
> About all cores boosting to the same frequency, maybe it's only for the 5600x but I need at least +175Mhz to be able to reach lowest memory latency possible.
> 
> I had a curve set to +50 gave me 52.7ns, +200 with curve at 0 gives 52.2ns ..


Boost override always will leave changes on the table
lowest curve optimizer is needed , in order to run more frequency at the same clock
Memory latency always improves with CPU frequency. Any frequency lift is a good one. There is not fully a "frequency limit" ~ and if then your FCLK is not even close to it

I keep seeing a difference between 4750 and 4850, but it's still not a bottleneck. Probably 4650 would also run 4200MT/s easily. No cache bottleneck found yet
Negative CO should be maxed out as much as possible and dampened with positive vcore offset
Else the voltage drop is too strong from "only using CO" . This is required in order to prevent hitting the EDC FUSE limit and throttling back in frequency
-28 + 45mV works well for me, same as -13+5 is functioning . Just allcore freq is lower with lower CO


----------



## neox387

Highest my worst core reached in ctr 2.1 boost tester on -30 was 4822 tried with a range of 6 to 100 mV positive vcore, Tm5 all core also stuck around 4800, guess im out of Luck there 

Redoing curve for +200 and will compare aftwards if higher co with positive vcore gives better result, still frustraded over 1900 whea free limit

Did some tests in safe mode no whea corrected warnings there.. Boot untill 2067 but CB scores went down from 2000+ (all on 900-1020-1080-1200) tested a quick probably unstable 4000c15 with 50.8ns damn 🤤

Tested some lower voltages and still stable, for sure my prev 5900x would have not posted on 800 vddp, IOD needed at least ~950 or memory latency increases, cpu vddp at -40mv for 876mv according to bios

cl14 doesn't gain much expect for ~0.3ns but needs more volts and could not get it stable









vdimm @1.53v instead of 1,47v (GB fail)


----------



## PJVol

neox387 said:


> Did some tests in safe mode no whea corrected warnings there.. Boot untill 2067 but CB scores went down from 2000+ (all on 900-1020-1080-1200) tested a quick probably unstable 4000c15 with 50.8ns damn 🤤


Im afraid no whea's in safe mode doesn't prevent from some EDC throttling at 1933+, rather it's kinda turned off. Did some tests recently and managed to accomplish 4000cl15 tm5, but first I had to fight the throttling occured in my case, which I finally have managed to, by setting CPU VDD 1.8 to 2.0V min for IF2000 and 1.90-1.95V for IF1933-1966. Still lots of whea, but I think it has minor effect on performance by itself, rather indicating some other limitation come into force.
Here are Dram Calc's Membench runs, one [email protected], [email protected], with VDD CPU1.8 1) default, 2) 1.9V and 3) 2.0V. While AIDA latency didnt suffer at all, you may see the performance in memory intensive app is degraded massively at default CPU VDD1.8:


























And here is comparision of the same Membench running at default CPU VDD 1.8, [email protected] and [email protected]:








To alleviate throttling, besides CPU VDD, I had to keep some voltages in a certain range. For me they were
VDDP 0.9-0.92
VDDG CCD 0.94-0.98
VDDG IOD 1.04-1.08
VSOC depends on IF
for 2000 it should be minimum 1.15 (+vdroop)
for 1933 and 1966 1,10-1.11 were enough


----------



## RonLazer

PJVol said:


> Im afraid no whea's in safe mode doesn't prevent from some EDC throttling at 1933+, rather it's kinda turned off. Did some tests recently and managed to accomplish 4000cl15 tm5, but first I had to fight the throttling occured in my case, which I finally have managed to, by setting CPU VDD 1.8 to 2.0V min for IF2000 and 1.90-1.95V for IF1933-1966. Still lots of whea, but I think it has minor effect on performance by itself, rather indicating some other limitation come into force.
> Here are Dram Calc's Membench runs, one [email protected], [email protected], with VDD CPU1.8 1) default, 2) 1.9V and 3) 2.0V. While AIDA latency didnt suffer at all, you may see the performance in memory intensive app is degraded massively at default CPU VDD1.8:
> View attachment 2485422
> View attachment 2485423
> View attachment 2485418
> View attachment 2485419
> 
> 
> And here is comparision of the same Membench running at default CPU VDD 1.8, [email protected] and [email protected]:
> View attachment 2485421
> 
> 
> To alleviate throttling, besides CPU VDD, I had to keep some voltages in a certain range. For me they were
> VDDP 0.9-0.92
> VDDG CCD 0.94-0.98
> VDDG IOD 1.04-1.08
> VSOC depends on IF
> for 2000 it should be minimum 1.15 (+vdroop)
> for 1933 and 1966 1,10-1.11 were enough


By CPU VDD 1.8V do you mean PLL/1P8?


----------



## _frame_

RonLazer said:


> By CPU VDD 1.8V do you mean PLL/1P8?


This one


----------



## gabian

Hi Veii, do you have any suggestion on theses settings ? May be incoherent timings or values i can improve.


----------



## RonLazer

_frame_ said:


> This one


Yup thats the PLL voltage, out of curiosity how low can you set it, and do you see negative effects? My Unify-X has the setting but I can't see any change from dropping it to 1.6V or raising to 2.1V. What benchmarks specifically show up changes?


----------



## nada324

@Veii So it seems that for this set of timings, tras + 1 = TRC is working fine,

Still i couldnt get stable that trcd to 15, im struggling lot of fixing error #2 and #12, i will try more on the weekend


----------



## PJVol

RonLazer said:


> What benchmarks specifically show up changes?


It is not about how it affects benchmarks score, but about stabilizing cpu in general, at high fclk (1933+). Look at my post above, where I gave an example of the impact it has on my system when running DRAM Calculator Membench. With the default value of 1.8V, the performance regression at 1966-2000 was so massive, that there's not much sense to even consider the score as having any value.
Regarding the supposed range, above 2.0V didn't seem to benefit me in any way (as well as lowering it below default value)


----------



## Veii

neox387 said:


> Did some tests in safe mode no whea corrected warnings there.


There is no WHEA logging in safemode
WMI, Powerrmanagement, GPU Drivers, Sound Drivers, Ethernet ~ all are disabled, unless you only load ethernet drivers with it

It's staying as cheating mode, because all of these things are missing
Soo the WHEA possibility even if you get WMI logger to work, are close to 0



PJVol said:


> Here are Dram Calc's Membench runs, one [email protected], [email protected],
> with VDD CPU 1.8 1) default, 2) 1.9V and 3) 2.0V.
> While AIDA latency didnt suffer at all, you may see the performance in memory intensive app is degraded massively at default CPU VDD1.8:


I'll test this, sounds interesting 


PJVol said:


> To alleviate throttling, besides CPU VDD, I had to keep some voltages in a certain range. For me they were
> VDDP 0.9-0.92
> VDDG CCD 0.94-0.98
> VDDG IOD 1.04-1.08
> VSOC depends on IF
> for 2000 it should be minimum 1.15 (+vdroop)
> for 1933 and 1966 1,10-1.11 were enough
> 
> 
> Veii said:
> 
> 
> 
> I'm sadly not in clear, if they mixed different "types of substrates". . . color types - to have such an abnormal behavior
> (loving low voltage, scaling well with high voltage)
> But to split it:
> 
> CCDs have positive scaling with low voltage and low VDDP (CPU VDDP)
> IMC remains to have positive scaling with low voltage and so better signal integrity
> VDDG IOD remains to have the same scaling like Matisse, while it feels comfortable near 980-1080mV
> VDDG CCD has negative scaling beyond 950-980mV. It has positive scaling sub 940mV. Down to 850mV
> SOC has a big range 980-1280mV
> (depends on the remain voltages and voltage "patterns=fixed voltage multiplied")
> 
> Minimum Requirements of VSOC mV @ Frequency
> 
> 3200 - 980-1000mV
> 3400 - <1040mV
> 3600 - <1060mV
> 3800 - <1075mV
> 4000 - <1137,5mV
> 4067 - 1165-1200mV
> 4200 - 1187,5-1225mV
> maximum being 1300mV, while 2100 defaults to 1250mV SOC.
Click to expand...

Matches very well with this range , good job in figuring it out and confirming
Autocorrecting is subtle but always active. Tracking it is annoyingly hard, soo good job for sure ! 


gabian said:


> View attachment 2485486
> 
> 
> Hi Veii, do you have any suggestion on theses settings ? May be incoherent timings or values i can improve.


Up tCL to 15, and run GDM off - at lower procODT
With higher ClkDrvStr and higher CsOdtDrvStr
CsODT between 30-40, ClkDrvStr between 40-120
120 only on high capacity dimms, and dual rank ~ requiring lower procODT overall
Many dimms or Dual Rank ~ requires SD, DDs @ 1-4-4-1-6-6. 1-5-5-1-7-7 is for dual 8gb dimms.
The higher the values the better the performance, but it will cross-talk ~ overlap with other timings if you have them too high. Dual Rank again needs it lower

Don't run Odd Primaries with GDM


nada324 said:


> @Veii So it seems that for this set of timings, tras + 1 = TRC is working fine,
> 
> Still i couldnt get stable that trcd to 15, im struggling lot of fixing error #2 and #12, i will try more on the weekend
> 
> View attachment 2485507


It runs but you won't get the improvement with tFAW staying at 4* tRRD_S.
tRAS+1=tRC exploit, needs 1x tFAW between 6-8

Same for +1 on tRCDRD. Big loss in memory performance.
Going down on tRCDWR also leads to a big loss in performance unless you match it with the rest

Focus on getting 15-15-15-15 to work
You can focus later on exploit testing, but currently your priority aside from having the powering correct for GDM.
~ Getting primaries as low as possible. Down to 14-14-14-14 if you feel comfortable to move in the 1.5-1.6v range with weaker RTT_PARK


----------



## neox387

No luck with positive vcore, could only get worst core from -19 to -23 with +42mV while best core only went up by 1 meaning everything would run even worse =(

so this is no positive vcore and curve looks way worse then @Veii s with everything glued to 4848 xP









safe mode vs normal boot looses 0.6ns without at least pbo +175 52.7ns was the limit in safe mode


----------



## thismock

This thread has been immensely helpful for me, so I’d like to give back with some data about Micron Rev E tuning at 2000+ FCLK. I’m hoping this will serve as a guide or reference for other folks trying to tune Rev E; I figured it’d be helpful since this thread primarily has info and timings for B-die.

— Edit: After I posted this, Veii provided a ton of useful input and feedback, mostly to correct some of my inaccurate / incorrect assumptions. I’ve added many of his notes in-line, in places where I was wrong or incomplete, in an attempt to make this specific post a more complete resource. Veii’s notes are bracketed with [[ and ]]. —

I’m running a Ryzen 5600x on a B450 motherboard. I’m working with a set of Crucial Ballistix 2x8gb 3600 cl16. This set seems to have a hard cap of 280ns TRFC, and a cap of 19 TRCDRD at 4000mhz and above.

I’m quite constrained by my motherboard (Asrock B450 Fatal1ty Gaming-ITX), which has some idiosyncrasies around voltage tuning. For VDIMM, the BIOS has a hard cap of 1.5v and only allows 50mv stepping (1.5v, 1.45v, 1.4v, etc.) VSOC is adjusted with an offset value of -35, -70, or -105 — so 2000 FCLK only allows 1.1v (-105), 1.375v (-70), 1.75v (-35), or 1.21v (no offset). The reality of this is that I have to tighten timings around the voltage options available to me, rather than going for tightened timings and adjusting voltage in small steps to make it work. So it goes.










—

I started tuning with command rate 1T, GDM off, and loose timings: 16-20/20-20-40, 16 TCWL, AUTO everything else). The following power-related settings have worked flawlessly for me for all configurations at 4000+ MHz. Veii has posted these numbers about a hundred times across this thread, so these numbers shouldn’t be a surprise — I’m just confirming that they work well for single-rank, 2x8gb Rev E in my experience:

CLDO VDDP: 0.9v
VDDG CCD: 0.94v
VDDG IOD: 1.0v

VSOC: 1.1v for 2000 FCLK, 1.1375v for 2033+
VDIMM: 1.5v

ProcODT: 34.3
RTT: 7-off-6
ClkDrvStr: 40-20-20-20
CKESetup: 4-4-18
TCKE: 11

Once I had the power stuff dialed in and confirmed stable, I focused on tightening timings. This is essentially the order for how I tightened things, and why I chose what I did:

TCL + TCWL: I’m able to run CL15 up to 4067, and CL16 up to 4200. Unsurprisingly, 4067cl15 is faster than 4133/4200c16. TCL 15 implies TCWL 14, TCL 16 implies TCWL 16. [[ 4067C15 flat, should match 4267C16 (2133) FCLK. It's a bit hard to compare, because tertiaries like tRRD also scale up by frequency and +1 already does a big change ~ where the higher the MCLK the bigger the jump-difference, but +200 MT/s = +1 tCL + 1 tRCD , is pretty much on point (same downwards) ]]

*SCL: I can’t post on anything lower than 4/4, so that’s where I keep it.

TRCDRD: is really fickle at 18 for 4000+; I spent a lot of time trying to make it work and just couldn’t. So I run 19.

TRCDWR: this works as low as 12 for me, possibly lower, but I didn’t see a measurable performance increase, so I left it at 18 (from when I was trying to get TRCDRD to work at 18). [[ Only beneficial if you get it down to perfect half, else it adds latency and desync's the set. It's hanging with tCWL and tWR together. Pretty much an exploit type of thing.
Soo keep it equal to tCL or in case ttRCD_RD is not higher than tCL ~ match it and make it a flat set. ]]

TRP: ideally set to the lower of TRCDRD/TRCDWR, so in this case 18 (to match TRCDWR).

TRDWR + TWRRD: set to 9/4, the reasoning here is that (TRDWR * 2) [18] is less than TRCDRD [19], so I need to add latency with TWRRD. The formula is TRCDWR < (TWRRD * SCL). I know TRCDWR is 19, SCL is 4, so 4 is the largest value for TWRRD that’s still less than 19. 10/1 is an option as well for more stability, less performance.

TRAS: TCL + TRP, in this case 34. [[ tCL or tCWL + tRP + BURST-length (up to capacity), is one of the methods to match it under tCL or tCWL ~ but that is also an exploit type of thing. A more natural method is to focus on the primaries. tCL and tCWL both being nominators while they can vary by voltage and by scenarios. The main and most important timings are/is tRCD. Both tRCD or tRCD & tCL , is a method to align it. Generally you can lower it till you choke instruction sets. It's the "gate keep up" or in technical terms "ROW ACTIVE Time". Minimum limit is 21 on AMD (sadly) soo you can not get it to behave in "burst" methods. In short: "keep it higher, it's cleaner" or "lower it as low as you can keep it stable and go the beating-head-against-a-wall, benchmarking method ]]

TRC / TRFC: seems most advice around B-die recommends setting the lowest TRC possible, and then setting TRFC accordingly. However, Rev E requires higher TRC and TRFC, and these numbers need to be multiples of one another, so the fastest combination may not be the lowest TRC -or- TRFC that is stable.

[[ tRC is an arbitrary number, but also like tRAS a "sync thing.”. Unlike tRAS which does a direct effect on the chain. tRC is an additive "mind-set" delay. This "wait-for-action" additive delay, is used on several parts, but also to focus the delays elsewhere ~ soo you can lower the remain tertiaries and still get a beneficial effect out. There is an exploit out there for AMD, to align as tRCDWR+tCWL+tWR+BURST. Nearly identical to tRAS. There is another exploit i figured to make it tRAS+1 , but this needs tFAW to be down to less or equal than tRRD_L . It should be equal or bit lower than tRRD_S (one time, not 4*). So the general rule on it remains TRAS+TRP. But if every other timing is higher, you can fully skip it and match it perfectly to TRAS. XOC cheat is to push this high - it does add stability, but the whole chain hangs on tRC then , as it will wait-for-action ]]

The first step is to find the fastest TRFC, which for my set is 280ns. This is done through basic trial and error, trying to find the lowest value that passes a 25-cycle TM5 run. This number is converted from nanoseconds, so for 4067mhz: 280ns * (4067 / 2000) = 569.

The second step is to find the lowest stable TRC, which has a reasonable floor of TRP (18) + TRAS (34) - 2 == 50. I can’t boot anything less than 54, so my TRC floor is 54.

Then take these two numbers (TRC min 54, TRFC min 569) and find the fastest combination where TRC is a factor of TRFC. There’s a possible option here of TRC 57 and TRFC 570 (TRC * 10). Another possible option is TRC 54 / TRFC 594 (TRC * 11). For reasons to come, TRC 58 / TRFC 580 (TRC * 10) is also an option.

TWR / TRTP: from my testing and reading, TWR is ideally a factor of TRFC, and TRTP is itself ideally a factor of TWR. It’s my understanding that TWR must be an even number. I was wrong about this, as Veii told me:

[[ This is a bad spread i take credit for ~ by not knowing it better early on. tWR same as tRTP only has to be an even value if GDM is engaged. My personal sync point is a clean or .5 decimal of tRFCns = "not half of tWR" , but "half of tWR" works perfectly and is often needed to gain stability  tWR should be able to go down to 8, but that's an AMD limitation we have here. Actually even down to 6. ]]

Back to my Rev E testing, at the time I was assuming TWR needed to be a factor of TRFC...

Since TWR >= TRRDS+TWTRS, the lowest reasonable value for TWR is ~10. 

So looking at the three TRC+TRFC combinations, I have the following even factors in the 10-to-30 range:

TRC 54 - TRFC 594: 18, 22
TRC 57 - TRFC 570: 10
TRC 58 - TRFC 580: 10, 20

From this, the best-reasonable combinations for each set are:

TRC 54 - TRFC 594 - TWR 18 - TRTP 9
TRC 57 - TRFC 570 - TWR 10 - TRTP 5
TRC 58 - TRFC 580 - TWR 10 - TRTP 5

After stability testing these, my sticks can’t handle a TWR of 10, no matter how much TRRD + TWTR tuning I try, so that leaves me with these combinations:

TRC 54 - TRFC 594 - TWR 18 - TRTP 9
TRC 58 - TRFC 580 - TWR 20 - TRTP 5 (or 10)

Performance and stability testing these, the latter comes out the winner. By extension TRFC2 = 431, TRFC4 = 265. See Veii’s DRAM calc spreadsheet for these numbers.

TRRD / TFAW / TWTR: I started with a reasonably loose set in 7-9-28 for TRRDS-TRRDL-TFAW, and TWTR auto-ed to 6-14. I haven’t been able to do better than these settings, yet. Interestingly enough, the 1x TFAW setup is stable for me (6/8/8), but it requires a higher TWR (26), and is ultimately a net loss in performance (probably doesn’t make sense anyway because of the high TRC, but it was interesting to try).

[[ 1x tFAW exploit, needs to run tRAS+1 = tRC, else you have performance regressions & 4* tRRD_S = tFAW makes more sense and is cleaner. It again is to noted that this doesn't work on Renoir or lower, it's a new thing.  ]]

[[ tRRD and tWTR , between _S & _L, depend fully on the PCB density, trace length and capacity. They give a significant perf, as they are "holders" between different primaries actions (elementary explained), but i've figured that increasing them for stability & reducing primaries generally has a bigger speed effect, than just lowering anything else lower. The speed and lower primaries at X time (4200C15-15 = 3800C13-13) has just a far bigger perf effect  ]]

*SC/SD/DD: I left these on AUTO, which was ultimately set for 1-6-6-1-4-4. I haven’t played with changing these numbers yet.

I’ve tried ProcODT values between 32 and 36, and 34.3 has worked the most consistently for all configurations in the 4000-4133 range.

—

My fastest config is 4067c15 with ~52.6ns at stock CPU settings (no PBO, CO, or AutoOC). There’s probably a little more room to improve here, either getting cl15 to work at 4133, TRCDRD down to 18 on the 4067 config, or 2100+ FCLK to be reasonably performant. I’ve put a fair bit of work into each of these options, without any success yet.

The stable 4133c16 config performs around 53.4ns.

4200/2100 works fine for me and is stable, but autocorrection seems to be killing my performance (55-56+ns), even with increased IOD, CCD, and SOC voltages. I haven’t tried aggressively exploring ClkDrv and ProcODT variations. Interestingly, TCKE 11 + CKESetup 4/4/18 works for 4200 for me, as well as TCKE 13 + CKSetup 5/5/20.

Strangely enough, I have a 2x8gb set of Viper Steel 4400, which is supposed to be quality-binned B-die .. and it performs like garbage in my system. The best I can do with it is 3800cl15; I can’t even post 4000cl16 when using TCKE 11 and CKESetup 4-4-18. It may just be an unusually bad set of silicon. I’m way happier with the performance of this Micron Rev E set.

—

That’s a lot of text, but hopefully it’s helpful to someone at some point. I’m open to any suggestions or recommendations for anything I’ve listed here. Many thanks for all the hard work everyone’s done and contributed in this thread already!


----------



## glnn_23

Picked up a 4650G the other day just to see what they do. At 4533Mhz 1:1 so far.


----------



## craxton

@Veii regarding C/O and what you mentioned quite sometime back using tm5 with all threads/core boosting to 4.85 equal neg 30 co with positive 3xx mv to cpu core offset.

I've tried and tried, I did actually manage to get all boosting to 4.85 with random c/o of....
well atm I can't recall, but I kept getting this ding ding type of windows sound that I had never heard before. 
I found it inside windows somewhere. It's called, (after searching for a while)
"Windows "notify.wav" which did NOT stop unless i ran aida, r20/23 or stress test someway.

the pc didnt crash or anything, but seeing how i had never heard this sound before, its rather...well
alarming to not know whats going on, and why using Curve -30 with some added mv increases to cpu core
made it do this.

can you re-tell (i search all the way back to a months past in posts and i either missed it, 
or its further back) what your Curve recommended settings were, -30 and what + in voltage? 
using TM5 and hwinfo to see if all core/threads are boosting to 4.85? 

or was the mv increase just what you had to use to get your cpu boosting correctly? atm, with just NO CO at all
and a -.07xx offset to voltage with x3 i boost to 4.75 all T/C.


----------



## neox387

craxton said:


> @Veii regarding C/O and what you mentioned quite sometime back using tm5 with all threads/core boosting to 4.85 equal neg 30 co with positive 3xx mv to cpu core offset.
> 
> I've tried and tried, I did actually manage to get all boosting to 4.85 with random c/o of....
> well atm I can't recall, but I kept getting this ding ding type of windows sound that I had never heard before.
> I found it inside windows somewhere. It's called, (after searching for a while)
> "Windows "notify.wav" which did NOT stop unless i ran aida, r20/23 or stress test someway.
> 
> the pc didnt crash or anything, but seeing how i had never heard this sound before, its rather...well
> alarming to not know whats going on, and why using Curve -30 with some added mv increases to cpu core
> made it do this.
> 
> can you re-tell (i search all the way back to a months past in posts and i either missed it,
> or its further back) what your Curve recommended settings were, -30 and what + in voltage?
> using TM5 and hwinfo to see if all core/threads are boosting to 4.85?
> 
> or was the mv increase just what you had to use to get your cpu boosting correctly? atm, with just NO CO at all
> and a -.07xx offset to voltage with x3 i boost to 4.75 all T/C.


He replied recently: -28 with +48mv, for me positive vcore trickery did not really help  









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


@Veii Thanks for your tips, but after trying 536 same error 13, also tried to lower vdimm -10 to 1.490v from 1.5, and rtt to 436 and same issue, for error #11 tried trc 45, same issue; I read on the calculator that it can be tras +1, tried it but no luck. Also tried puting on it more vdimm to...




www.overclock.net


----------



## BarrettDotFifty

Running this dual rank b-die kit stable at 1.45V as a 24/7 setup. Can't be bothered to go higher frequencies than 3600. Anyone have some ideas for timing improvements? What should I look into tightening next?


----------



## paih85

BarrettDotFifty said:


> Running this dual rank b-die kit stable at 1.45V as a 24/7 setup. Can't be bothered to go higher frequencies than 3600. Anyone have some ideas for timing improvements? What should I look into tightening next?
> 
> View attachment 2485574


TM5 20 cycles?


----------



## craxton

neox387 said:


> He replied recently: -28 with +48mv, for me positive vcore trickery did not really help
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> @Veii Thanks for your tips, but after trying 536 same error 13, also tried to lower vdimm -10 to 1.490v from 1.5, and rtt to 436 and same issue, for error #11 tried trc 45, same issue; I read on the calculator that it can be tras +1, tried it but no luck. Also tried puting on it more vdimm to...
> 
> 
> 
> 
> www.overclock.net


ok, thank you.

but the windows notify sound is still something ive not heard on my system before.

the only time it does so is when i use curve.

FIGURED OUT what the dam noise was, i had set an alert for any cpu core voltage over 1.45 in hwinfo
using notify wav lol....needless to say, i set it to over 1.45 now, flash, and got neg 23 curve with .002x voltage offset applied, 
well one from the minimum MSI will allow and now im boosting 4.85 all Cores and threads and voltage is lower now
than what it was when i simply ran a negative offset to cpu voltage..still no whea errors.


----------



## TimeDrapery

Anybody see anything I could do better here?


----------



## Theo164

3800 4x8 b-die @ 1.42v stable no memory errors or whea but can't post / train higher frequencies... any suggestions?


----------



## TimeDrapery

Theo164 said:


> Spoiler
> 
> 
> 
> 3800 4x8 b-die @ 1.42v stable no memory errors or whea but can't post / train higher frequencies... any suggestions?



Increase your VDIMM


----------



## TimeDrapery

BarrettDotFifty said:


> Spoiler
> 
> 
> 
> Running this dual rank b-die kit stable at 1.45V as a 24/7 setup. Can't be bothered to go higher frequencies than 3600. Anyone have some ideas for timing improvements? What should I look into tightening next?
> 
> View attachment 2485574



Try:

lower *tCWL*, like "*12*", while increasing *tRDWR* to "*10*" and dropping *tWRRD* to "*1*" (or just set those two to "*Auto*" and drop *tCWL* to "*12*"
lower *tRTP* to "*6*"
*tRDRDSCL* and *tWRWRSCL* can likely come down to "*2*", if not then try "*3*"
lower *tRCDWR* to "*8*", if that won't work try "*10*"
lower *tRP* to "*13*", try "*12*" if that works out


----------



## Theo164

I've tried higher voltages in general like VDIMM, VSOC, VDDG CCD, VDDG IOD... no luck


----------



## hazium233

I hereby present the world's slowest (and second slowest) B-die timings.

















I originally just wanted to stabilize the XMP timings at 3533 using 1.35V but I was too incompetent or lazy to be able to do this and needed 1.36V. Maybe if I had better termination it would have worked.

But given that the semi-auto subs were over 1 hour worse in TM5 than 3466C14 (ha!), I thought I would speed it up slightly with some tweaks. Tweaked down RRDS/L and FAW (6-9-24) along with a couple other things, including tRFC to ~ 190ns (336). Those timings were apparently terrible and resulted in error 1 and or 11. Tried vdimm adjustment, then tried WTRS then WTRL, played with RDWR and WRRD. But I ended up tweaking chassis fans, fixing CAD, moving voltage down a step and just going back to 50*8 RFC, then XMP RRDS/L and FAW.

I think CLDO VDDP 0.865 is ok for this kit at this speed. Really this was a lot of test time to blow on stupid timings where 16-16-16-32-48 is probably better.


----------



## craxton

Theo164 said:


> can't post / train higher frequencies... any suggestions?


you can "try" my 4x8 setup here

stable no whea, there was one thing i was supposed to change, but i was off on a trip and forgot
to which theres been ALOT posted since then now.. best ive gotten with killing tasks,runtime, etc is 51.8 but
dont have a screenshot. these are NOT the best sticks but they are dam good none the less.
try some VDDG voltage settings as well, and you may need more vdimm than what i use as
1.46 with llc3 is set in bios on northbridge.

















my dram calc scores are pretty good as well, 







this was before getting Curve setup properly.
have NOT retested anything since.


----------



## thismock

I managed to crack 4267 FCLK thanks to PJVol’s finding about increasing CPU VDD 1.8v to reduce throttling at high FCLKs. The latency is what I’d expect for these timings, the read bandwidth seems a little low. I think I’ve managed to fend off most of the throttling since the test completed in 1:55.39 — very close to the same time it takes my 4067c15 config to run the same number of cycles (1:55.07).

The setting I tweaked in my Asrock BIOS is called “CPU 1.8v”, which I set to 2.00v and shows up in HWinfo64 as “VTT” with a value of “1.968v”. My understanding is this is voltage for the IMC on the CPU. Read/write/copy performance scaled linearly from the original 1.8v value, which I could only test in 50mv steps. It’s possible there’s room for more performance above 2.0v, but I have no idea what a safe upper bound is for this setting on a Zen 3 chip. Anyone happen to know?

Read/write/copy performance also improved measurably by increasing VSOC from 1.175v to 1.21v; not surprising, but good to see it confirmed. I’m again hampered by my BIOS only allowing large jumps in VSOC voltage. The next available step up in VSOC is 1.25v, and I’m hesitant to run that high.

I forgot to set TCKE to 13, so I’m doing another lengthy run to see if that works — it ~should~ work with the 5/5/20 CKESetup values. TBD.

I don’t think I’m going to be able to get TRCDRD below 20, which I think is ultimately going to limit performance pretty considerably. 4267c16 w/ TRCDRD 19 is throwing the same errors I saw with trying to get 4000c15 w/ TRCDRD 18 to work: lots of error 6+0.


----------



## craxton

Can someone *PLEASE TELL ME* what *ITERATIONS* are in OCCT memory test?

No errors period ever, but iterations????? googling comes up with NOTHING lol?? 
makes me wonder is iterations are simply put "errors" or how many different tests it throwing
since its been 3 mins for 3 iterations? confused atm....


----------



## zGunBLADEz

jomama22 said:


> It really should be noted that aida's l3 bandwidth tests aren't exactly real world scenarios nor are their bugs actually affecting your work or gaming in any meaningful way. Remember, all those bandwidth tests are doing to filling the l3 with data and then reading out that using instructions that they know will find the cached data in l3.
> 
> This is not real world at all nor actually inherent of how well l3 will be read from each core in any other scenario. The l3 bug in aida is/was just an issue of pulling every core out of sleep or low idle state and properly writing and reading from l3 in the time the test gives it to do so.
> 
> If the instructions from aida were predicted in the prefetch to be performed fastest by only utilizing a handful of cores, then that's what it would do and that's why you would have low l3 scores.
> 
> Those bandwidth tests are really just attempting to trick the cpu into filling up l3 and ONLY l3, which would never happen, ever, in the real world. Some data would go to l1, some would go to l2, and some would make it's way to dram.
> 
> I'll give you this job if you're up for it. Go find some program, game, w.e., where you see any difference if it's result, where it's time, score or fps, that are outside variance while keeping all other factors equal (clocks, memory, etc).
> 
> Core bandwidth to the l3 cache is not going to change no matter what changed they make for aida's l3 to read differently.
> 
> My guess as to what was happening in older bios' with pbo and aida's l3 test is that the algorithm to predict what power requirement was needed for those tests exceeded edc, so power limits kick in and reduce with core clocks or amount of cotes/thread (most likely the latter). At the same time, the instructions were predicted to only need to use a handful of cores/threads anyway. In turn, instead of using every thread available to read/write/copy data to l3 (which is needed to maximize and get a maximum bandwidth reading from the l3 to the cores) it was only using a few.
> 
> Having a lower edc in this situation would exacerbate this issue, as we saw with older bios'. My guess is all amd did was says "Look, under this exact coding scenario, allow all cores to activate, ignore the branch predictions and prefetcher". Edc still plays a role in just how much bandwidth you get from l3 and pbo in newer bios', so they did not touch any part of pbo's algo to change this.
> 
> Much older bios' had even all core oc's l3 cut in half, but only on the 5900 and 5950, leading me to believe that it most definitely had/has somthing to do with prediction of thread creation and core utilization. It probably had no problem just running the code execution all on the same die/ccx (remember, that is genuinely what you want to happen to reduce core to core latency penalties).
> 
> Really, all I'm saying is don't take aidas l3 test as some gospel of what the cpu is doing everywhere else. It's not some end all be all test of how the cpu works (or the memory for that matter).
> 
> I would much rather have higher boost and better benchmark scores, higher fps, better production times than caring about what aida's l3 cache bandwidth test reads.





jomama22 said:


> It really should be noted that aida's l3 bandwidth tests aren't exactly real world scenarios nor are their bugs actually affecting your work or gaming in any meaningful way. Remember, all those bandwidth tests are doing to filling the l3 with data and then reading out that using instructions that they know will find the cached data in l3.
> 
> This is not real world at all nor actually inherent of how well l3 will be read from each core in any other scenario. The l3 bug in aida is/was just an issue of pulling every core out of sleep or low idle state and properly writing and reading from l3 in the time the test gives it to do so.
> 
> If the instructions from aida were predicted in the prefetch to be performed fastest by only utilizing a handful of cores, then that's what it would do and that's why you would have low l3 scores.
> 
> Those bandwidth tests are really just attempting to trick the cpu into filling up l3 and ONLY l3, which would never happen, ever, in the real world. Some data would go to l1, some would go to l2, and some would make it's way to dram.
> 
> I'll give you this job if you're up for it. Go find some program, game, w.e., where you see any difference if it's result, where it's time, score or fps, that are outside variance while keeping all other factors equal (clocks, memory, etc).
> 
> Core bandwidth to the l3 cache is not going to change no matter what changed they make for aida's l3 to read differently.
> 
> My guess as to what was happening in older bios' with pbo and aida's l3 test is that the algorithm to predict what power requirement was needed for those tests exceeded edc, so power limits kick in and reduce with core clocks or amount of cotes/thread (most likely the latter). At the same time, the instructions were predicted to only need to use a handful of cores/threads anyway. In turn, instead of using every thread available to read/write/copy data to l3 (which is needed to maximize and get a maximum bandwidth reading from the l3 to the cores) it was only using a few.
> 
> Having a lower edc in this situation would exacerbate this issue, as we saw with older bios'. My guess is all amd did was says "Look, under this exact coding scenario, allow all cores to activate, ignore the branch predictions and prefetcher". Edc still plays a role in just how much bandwidth you get from l3 and pbo in my man have a 5950ewer bios', so they did not touch any part of pbo's algo to change this.
> 
> Much older bios' had even all core oc's l3 cut in half, but only on the 5900 and 5950, leading me to believe that it most definitely had/has somthing to do with prediction of thread creation and core utilization. It probably had no problem just running the code execution all on the same die/ccx (remember, that is genuinely what you want to happen to reduce core to core latency penalties).
> 
> Really, all I'm saying is don't take aidas l3 test as some gospel of what the cpu is doing everywhere else. It's not some end all be all test of how the cpu works (or the memory for that matter).
> 
> I would much rather have higher boost and better benchmark scores, higher fps, better production times than caring about what aida's l3 cache bandwidth test reads.


i know man, but like im saying this exactly replicate those kernel panics on idle or whenever she feels like it and as long i know is possible to trigger it from there im going to keep checking it every bios update..


have 2 friends with 5950xs and one of them also have a asus b550-itx they duplicated my same issues on their ends.. as a matter of fact one of them on pbo get lower cache reads on l3 than me on the 5900x ...

so its not me or the system..


the worst offender here is* i cant overclock on static or using clock tuner *as this will introduce those crashes mentioned which are related to that "L3 bug" its like amd sold me a system "cpu unlocked" to run on just stock like :rollseyes: nope they better get it together and fix it.


----------



## jomama22

zGunBLADEz said:


> i know man, but like im saying this exactly replicate those kernel panics on idle or whenever she feels like it and as long i know is possible to trigger it from there im going to keep checking it every bios update..
> 
> 
> have 2 friends with 5950xs and one of them also have a asus b550-itx they duplicated my same issues on their ends.. as a matter of fact one of them on pbo get lower cache reads on l3 than me on the 5900x ...
> 
> so its not me or the system..
> 
> 
> the worst offender here is* i cant overclock on static or using clock tuner *as this will introduce those crashes mentioned which are related to that "L3 bug" its like amd sold me a system "cpu unlocked" to run on just stock like :rollseyes: nope they better get it together and fix it.


You can just overclock and run the system, stress/stability check, use system.

Again, if you feel so inclined, rma the cpu.

Your friends low l3 DOES NOT MATTER. I get 350gb/s on mine in pbo with dynamic oc, then on the static side if dos, get 1500.

I have personally tested it. 0 difference in games/benches/programs. AIDA l3 does not matter.


----------



## zGunBLADEz

It matters to me bcuz i CANT static overclock or use CTR cannot do nothing with it outside pbo.

The aida crap is just to trigger the obvious "worm big hole" amd have on the thing that is all.


----------



## hazium233

craxton said:


> Can someone *PLEASE TELL ME* what *ITERATIONS* are in OCCT memory test?
> 
> No errors period ever, but iterations????? googling comes up with NOTHING lol??
> makes me wonder is iterations are simply put "errors" or how many different tests it throwing
> since its been 3 mins for 3 iterations? confused atm....


You may need to ask the dev and see if they would give a specific response. It is probably like other programs where one iteration is one loop of testing, I don't know if it changes the pattern each time. Don't know how or if it tries to hit or avoid cache.


----------



## kompira

Veii said:


> Браво !
> He is a knowledgeable person - psone & 3600 on zen1 is not easy
> Was going with his research too to learn a bit about 1x tFAW mode


Мерси.
1T now, Rtt 636, VDIMM ~1.47V


----------



## craxton

jomama22 said:


> You can just overclock and run the system, stress/stability check, use system.
> 
> Again, if you feel so inclined, rma the cpu.
> 
> Your friends low l3 DOES NOT MATTER. I get 350gb/s on mine in pbo with dynamic oc, then on the static side if dos, get 1500.
> 
> I have personally tested it. 0 difference in games/benches/programs. AIDA l3 does not matter.


Low l3 cache speed shouldn't be a thing anymore since newer bios releases at least upto 1.2.0.x 

On some boards it has something called fmax or something like that, turn it off. And make sure your boosting correctly. As well as cooling adequately.


----------



## madjacko

hi all im having a second go at this as i had little success first time round.

im completely new to overlocking ram etc

I've ran these following tests.

before i start editing any values does anyone have any recommendations for the same ram?
G.Skill F4-3600C16-16GTZNC


----------



## thismock

@Veii did you have any luck getting 4333mhz / 2167 FCLK to post? I’m rock-stable on 4267/2133, but I can’t get 2167 to post no matter how much power/cad tweaking I do.


----------



## jomama22

craxton said:


> Low l3 cache speed shouldn't be a thing anymore since newer bios releases at least upto 1.2.0.x
> 
> On some boards it has something called fmax or something like that, turn it off. And make sure your boosting correctly. As well as cooling adequately.


Has nothing to do with that. I'm using 3003 as it provides the best core performance and memory latency with all bios releases.

My l3 is so low because I manually set edc to 140A on the 5950x since it provides no clock stretching and produces the best pbo results. I am using dynamic oc on a dark hero to multi core performance beyond 75 amps (which my all core oc is set to switch at) does not matter.

Again, aida l3 bandwidth is just a number. That's it. It does not reflect actually performance in any way. The "l3 fix" was merely a workaround to have , specifically, aida report higher bandwidth numbers. That's it.

There is 0 other benefit to the workaround. No affects of performance in games or programs.


----------



## jomama22

zGunBLADEz said:


> It matters to me bcuz i CANT static overclock or use CTR cannot do nothing with it outside pbo.
> 
> The aida crap is just to trigger the obvious "worm big hole" amd have on the thing that is all.


Again, if you are having stability issues with all core overclocks, rma the cpu.

If the only way you can cause that crash is by hammering an auto-clicker at the l3 bandwidth test in aida, then use the cpu normally and how you would and see what happens. If it crashed, rma the cpu.

Nothing more too it.


----------



## DeletedMember558271

New 1.2.0.2 BIOS for MSI B550 Tomahawk, 1900 FCLK still has a hole and doesn't boot and 1933+ has WHEA.
I don't believe either of these things are ever going to be improved, what incentive does AMD or MSI have? It's not going to make them more money.

1867/3733 forever I guess... waste of 4400 memory and just disappointing CPU can't even do 1900, it probably could without WHEA if it could boot unlike 1933+ but of course the boot hole has to be conveniently 1900 instead of 1867 or 1933, highest possible WHEA-free FCLK gets the bug, which was the minimum I was wanting and expecting when this all started and 2000+ FCLK if I was lucky.

They could fix the hole so I could boot 1900 or fix the WHEA so I could run 1933 but they probably aren't ever going to do either, cool.


----------



## zGunBLADEz

jomama22 said:


> Again, if you are having stability issues with all core overclocks, rma the cpu.
> 
> If the only way you can cause that crash is by hammering an auto-clicker at the l3 bandwidth test in aida, then use the cpu normally and how you would and see what happens. If it crashed, rma the cpu.
> 
> Nothing more too it.


You using a old bios which the l3 cache thing is not there. i get better pbo and overclocks on old bios but cant do 3800 ram or 1900fclk. Again the hammering the l3 cache thing has alot to do with the kernel panics im having on static overclocks by bios or clock tuner it will crash randomly on idle or whenever feels like it.. Its not the cpu or the motherboard bcuz i can control it and replicate at will any bios woth the fix will crash.. I need the new bios bcuz i was having the usb issues. PBO works just fine 0 issues on new bioses.. No crashes or kernel panics. But, cant use a static overclock.


----------



## jomama22

zGunBLADEz said:


> You using a old bios which the l3 cache thing is not there. i get better pbo and overclocks on old bios but cant do 3800 ram or 1900fclk. Again the hammering the l3 cache thing has alot to do with the kernel panics im having on static overclocks by bios or clock tuner it will crash randomly on idle or whenever feels like it.. Its not the cpu or the motherboard bcuz i can control it and replicate at will any bios woth the fix will crash.. I need the new bios bcuz i was having the usb issues. PBO works just fine 0 issues on new bioses.. No crashes or kernel panics. But, cant use a static overclock.


You said you tried disabling c states and df states and turning idle current to 'typical' from auto or low. The only other thing I could suggest is either running a core offset voltage in addition to a fixed voltage to pull up idle voltages slightly (not sure this is possible tbh, havnt looked, I believe it was on my msi board). Could try raising llc higher then normal as well.

Either that or try a ridiculous oc like 4.5 @ 1.35v get (set depending on your llc) to fully make sure the cpu is stable at all times during the manual oc.


----------



## Tobiman

My best result so far. It seems like raising ClkDrvStr to 60 ohms fixed my random error 12 in TM5. It's either that or increasing TRCDRD to 15 that fixed it.


----------



## Danny.ns

Dreamic said:


> New 1.2.0.2 BIOS for MSI B550 Tomahawk, 1900 FCLK still has a hole and doesn't boot and 1933+ has WHEA.
> I don't believe either of these things are ever going to be improved, what incentive does AMD or MSI have? It's not going to make them more money.
> 
> 1867/3733 forever I guess... waste of 4400 memory and just disappointing CPU can't even do 1900, it probably could without WHEA if it could boot unlike 1933+ but of course the boot hole has to be conveniently 1900 instead of 1867 or 1933, highest possible WHEA-free FCLK gets the bug, which was the minimum I was wanting and expecting when this all started and 2000+ FCLK if I was lucky.
> 
> They could fix the hole so I could boot 1900 or fix the WHEA so I could run 1933 but they probably aren't ever going to do either, cool.


Been having the same issue since I bought the 5900x, Dark Hero and F4-3600C16D-32GTZN in december.

FCLK 1933: Can post, boot, play games (WHEAs).
FCLK 1966: Can post, boot, play games (WHEAs).
FCLK 2000: Can post, boot, play games (WHEAs).
FCLK 1866: Can post, boot, play games, stress test. Stable.
FCLK *1900*: Can't post, qcode 07. Tried VDDG 0.9-1.2V.VDDP 0.9-1.2V. VSOC 1.1-1.25V. Tried PLL at 2.0V. VDIMM 1.5V (despite being set at 2400mhz auto timings while testing). Tried setting jumper to LN2-mode. I tried praying to both the old gods and the new. It simply will not post.


----------



## Alyjen

Well don't hold your breath for 1900 either, I can boot at 1900 no problem but I'll get single whea every few days, and that's beyond annoying.It has very little to do with new BIOSes it's just CPU memory controller limitation and rightfully so, since it's the same from Zen 2. Maybe future Zen3+ will have this fixed, but for Zen 3 it is what it is.


----------



## Danny.ns

I get what you are saying. But at this point I am not talking about how high of a stable overclock I can get with zen3. I'm simply talking about what looks to be an obvious bug in AGESA - selecting FCLK 1900 multiplier causes the motherboard to not even POST (ie. i cannot even reach BIOS). I *can* reach BIOS, windows and play games with FCLK at *2000*MHz.

Heck I can even choose the FCLK 1866MHz multiplier, and up the BCLK clock to get FCLK 1900 and it will POST and boot fine. For us affected (and I've seen plenty), this bug is really stupid and annoying.


----------



## Q Tech

Hi Guys,

I've recently discovered that, for me at least, Windows 10 versions 2004 and onwards have significantly lower WHEA-free FCLK overclocking headroom compared to 1909. I can run a 2000Mhz FCLK on 1909, but have to drop down to 1900Mhz on 2004 or 2009.

I've created a separate thread (warning: long read) for the issue, so please try and keep discussion over there if possible. But the long and short of it is that it appears that possibly some of the code AMD provided to Microsoft for these newer Windows versions is limiting the maximum WHEA-free Infinity Fabric overclocking headroom.

I'm posting here as I've been following this thread for a few months now and there's clearly some very knowledgeable people here, so I'd be interested to hear everyone's thoughts.


----------



## neox387

Q Tech said:


> Hi Guys,
> 
> I've recently discovered that, for me at least, Windows 10 versions 2004 and onwards have significantly lower WHEA-free FCLK overclocking headroom compared to 1909. I can run a 2000Mhz FCLK on 1909, but have to drop down to 1900Mhz on 2004 or 2009.
> 
> I've created a separate thread (warning: long read) for the issue, so please try and keep discussion over there if possible. But the long and short of it is that it appears that possibly some of the code AMD provided to Microsoft for these newer Windows versions is limiting the maximum WHEA-free Infinity Fabric overclocking headroom.
> 
> I'm posting here as I've been following this thread for a few months now and there's clearly some very knowledgeable people here, so I'd be interested to hear everyone's thoughts.
> 
> Edit: Looks like the thread is awaiting mod approval, hopefully will be up soon


Interesting also read something like this but running older windows version doesn't seeem so great


----------



## Q Tech

neox387 said:


> Interesting also read something like this but running older windows version doesn't seeem so great


No, I agree, especially as security updates for 1909 are ending in May of this year.

The hope is that AMD can identify the cause of the lower FCLK stability in 2004 and later and fix it in a future update.

The thread is now live by the way.


----------



## craxton

jomama22 said:


> Has nothing to do with that. I'm using 3003 as it provides the best core performance and memory latency with all bios releases.
> 
> My l3 is so low because I manually set edc to 140A on the 5950x since it provides no clock stretching and produces the best pbo results. I am using dynamic oc on a dark hero to multi core performance beyond 75 amps (which my all core oc is set to switch at) does not matter.
> 
> Again, aida l3 bandwidth is just a number. That's it. It does not reflect actually performance in any way. The "l3 fix" was merely a workaround to have , specifically, aida report higher bandwidth numbers. That's it.
> 
> There is 0 other benefit to the workaround. No affects of performance in games or programs.


not one time did i claim it impacts performance, (assuming performance would indeed include games etc)

im unsure what "work around" you speak of. i just know my L3 number were
around 350/380 in recent bios releases, now there more on where they should be. 
im on a 5600x and can limit EDC to 60 without it affecting L3 cache.

as for 3003, im not on or using nor have used the board your inclining about, just MSI particularly 
which are the SLOWEST at releasing bios updates, then again there nearly always stable and dont mess with
other parts in which would cause issues where there was none before hand. 

again, L3 speeds arent important, but since recent bios releases, L3 cache speeds should be 
around or near relative performance.


----------



## craxton

has anyone had an issue with turning off "IMMOU" in bios, to randomly start pinging CPU usage to 100%
in task manager?

process explorer shows this NOT to be true however, but still. reinstalled windows, removed so many apps, downgraded drivers etc
just finally was able to narrow it down to IMMOU....(no tasks or process show usage that high either, so 
i thought i had obtained a virus somewhere)


----------



## juan197

Dreamic said:


> New 1.2.0.2 BIOS for MSI B550 Tomahawk, 1900 FCLK still has a hole and doesn't boot and 1933+ has WHEA.
> I don't believe either of these things are ever going to be improved, what incentive does AMD or MSI have? It's not going to make them more money.
> 
> 1867/3733 forever I guess... waste of 4400 memory and just disappointing CPU can't even do 1900, it probably could without WHEA if it could boot unlike 1933+ but of course the boot hole has to be conveniently 1900 instead of 1867 or 1933, highest possible WHEA-free FCLK gets the bug, which was the minimum I was wanting and expecting when this all started and 2000+ FCLK if I was lucky.
> 
> They could fix the hole so I could boot 1900 or fix the WHEA so I could run 1933 but they probably aren't ever going to do either, cool.





Danny.ns said:


> Been having the same issue since I bought the 5900x, Dark Hero and F4-3600C16D-32GTZN in december.
> 
> FCLK 1933: Can post, boot, play games (WHEAs).
> FCLK 1966: Can post, boot, play games (WHEAs).
> FCLK 2000: Can post, boot, play games (WHEAs).
> FCLK 1866: Can post, boot, play games, stress test. Stable.
> FCLK *1900*: Can't post, qcode 07. Tried VDDG 0.9-1.2V.VDDP 0.9-1.2V. VSOC 1.1-1.25V. Tried PLL at 2.0V. VDIMM 1.5V (despite being set at 2400mhz auto timings while testing). Tried setting jumper to LN2-mode. I tried praying to both the old gods and the new. It simply will not post.


Same here with a Tomahawk X570.
Luckily I was able to change 4x8gb 4000mhz Microns that were useless in this situation for a 2x16 3600 Bdie Kit that I know can be OC but yes, I have to be at 1866.
It's frustrating to be able to post almost everything but 1900 and everything above 1866 gets Wheas.
Danny.ns has summed it up perfectly. (by the way with the same Kit as me)


----------



## SesioN

Here are my current results: 











I'm just a newbie who googled some info about memory OC so any constructive feedback on how to improve is really welcome!

What could I mess with / change to get even better results? Also I didn't run a 1h test yet, only a couple 6m tests in a row.


----------



## craxton

SesioN said:


> What could I mess with


your tRFC values from what tRFC mini calc (veii made) says
228
169
104

try that for starters. 

bookmark this (tRFC calc)


----------



## SesioN

craxton said:


> your tRFC values from what tRFC mini calc (veii made) says
> 228
> 169
> 104
> 
> try that for starters.
> 
> bookmark this (tRFC calc)


That results in a boot failure, had to reset cmos.


----------



## Alyjen

Q Tech said:


> Hi Guys,
> 
> I've recently discovered that, for me at least, Windows 10 versions 2004 and onwards have significantly lower WHEA-free FCLK overclocking headroom compared to 1909. I can run a 2000Mhz FCLK on 1909, but have to drop down to 1900Mhz on 2004 or 2009.
> 
> I've created a separate thread (warning: long read) for the issue, so please try and keep discussion over there if possible. But the long and short of it is that it appears that possibly some of the code AMD provided to Microsoft for these newer Windows versions is limiting the maximum WHEA-free Infinity Fabric overclocking headroom.
> 
> I'm posting here as I've been following this thread for a few months now and there's clearly some very knowledgeable people here, so I'd be interested to hear everyone's thoughts.


You can find lots about it on Reddit. This may just be addition to Windows that did not report some types of errors earlier, or some fck up in power management as lots of these whea events is related to low power states.
My bet is that the errors where there, just hidden


----------



## MrHoof

Alyjen said:


> You can find lots about it on Reddit. This may just be addition to Windows that did not report some types of errors earlier, or some fck up in power management as lots of these whea events is related to low power states.
> My bet is that the errors where there, just hidden


Well i had a 3600 before that was "stable" at 1900fclk 1 year, then suddenly started to WHEA. My guess they improved WHEA detection with 2004. My 5800x didnt report any WHEA at 1900 for now.


----------



## Sleepycat

SesioN said:


> Here are my current results:
> 
> View attachment 2485901
> 
> 
> 
> I'm just a newbie who googled some info about memory OC so any constructive feedback on how to improve is really welcome!
> 
> What could I mess with / change to get even better results? Also I didn't run a 1h test yet, only a couple 6m tests in a row.


Reduce your ClkDrvStr to 24. Also consider increasing CsOdtDrvStr and CkeDrvStr to 24. With your kit, ProcODT should run fine at 43 as well. I would also increase VDDG CCD and VDDG IOD to 1.05V, then try for 3800 / 1900IF.


----------



## mongoled

MrHoof said:


> Well i had a 3600 before that was "stable" at 1900fclk 1 year, then suddenly started to WHEA. My guess they improved WHEA detection with 2004. My 5800x didnt report any WHEA at 1900 for now.


I'm thinking something along the same lines. 

The important thing for me being that the reporting of the WHEA warning is not specific to the actual "failing" component/resource etc. 

For example, on 1909 and above and using an FCLK > 1900, would result sometimes with a single error warning notification in event viewer and then all of a sudden the event viewer will fill with exactly 100 additional warnings. 

Although the event viewer reports these as the same, I'm pretty sure they are not, it's just the description is defaulting to some catch all message. 

Why? Well testing with Windows 1909, with a non tweaked ("correct" voltages) at 2066/4133 I get a single WHEA warning on boot. 

Once I tweak the voltages I get no WHEA warning on boot and no WHEA while running the OS or so far no warnings while running TM5

With anything prior to 1909, I get 101 warnings on boot, so the 1 warning will be for a different reason then the other 100.

If only we could get more detailed information to what is the exact cause of the WHEA warning....


----------



## Veii

SesioN said:


> Here are my current results:
> 
> View attachment 2485901
> 
> 
> 
> I'm just a newbie who googled some info about memory OC so any constructive feedback on how to improve is really welcome!
> 
> What could I mess with / change to get even better results? Also I didn't run a 1h test yet, only a couple 6m tests in a row.
> 
> 
> craxton said:
> 
> 
> 
> your tRFC values from what tRFC mini calc (veii made) says
> 228
> 169
> 104
> 
> try that for starters.
> 
> bookmark this (tRFC calc)
Click to expand...

It misses correct calculation for 16gb dimms
For such use rather:








Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com





Haven't figured out another way to calculate tRFC for 16gb dimms (dual rank) & i don't want to borrow/steal his code 
Also more people worked on it there. Would be unfair to just copy it.


----------



## Veii

Had big issues after finally receiving SMU 56.50 - 1.2.0.1 (maybe A maybe not A; unsure) ~ finally after the 6th week

USB dropout issues i never had, started to appear (mouse and keyboard dropout)
2100 FCLK at any timings errors out in TM5 with random errors, and it looks like it's my timings (while they are not)
L3 access time increased from 10.9 up to 11.4 sometimes 11.7 - only after using again EDC 400, it got back to 10.9ns while reaching only 430GB/s on stock, compared to 550-600 on stock
on 4.85 PBO it's down to 630-580-600 compared to 680-640-650 & i can't go bellow 10.7ns , although it has to be 10.4

Overall inter-core latency increased and IMC firmware ?! probably got updated
Something strangely changed
Also PSP Firmware looks to be updated, as ZenStates finally reads out CCX cores correctly. Still dual CCD but it's a broken mess

I'll need more time to figure out if PSP Firmware really changed
Currently downgrading soo i can get the old flashed back on the chip & will then check if USB issues now permanently affect me too

Still running the old 20H2, but since the whole powermanagement rewrite on 1201 , it's nothing but issues.
More to come, still figuring bugs out
No WHEA error difference (still zero) , but just so you know


----------



## mongoled

I gather when you did your above tests you stuck to your tried and tested vDDG CCD < 1.0v ??

You should have tried increasing CCD to something like 1.005v ....


----------



## lmfodor

Veii said:


> Pretty much, it will spill out errors if it's wrong, and can make the OS crash randomly without any tests running
> 
> Afterwards yes, that means you moved away from the 1.55/1.56v issue and RTTs are better and not thaat strong anymore
> 
> Yours is already fine, but you want to get a 15-15-15 set now stable or move up in FCLK
> 
> nono, first increase them soo you can lower primaries. similar to what i run
> Then lower them after primaries are already low
> 15-15-15 should be easy on 1.52v or higher
> 14-14-14 would need around the 1.54-1.56 mark. On slower sets 1.5v but they utilize strong RTTs
> 15-15-15 is fine , scalable till 4000MT/s without an issue bellow 1.6v
> 4200 15-15-15 = 3800 13-13-13 , would require you to move in the 1.64-1.66v range
> * i think it's fine, but you have to see how you cool them and again need to rework RTTs to prevent PCB crashing or even PCB/IC dying
> ** beyond 1.55v is already a dangerous territory


Hi @Veii, as you will see I read you and a lot. These days I've been working on optimizing the curve. I think I'm in stable values, but I'm still testing. It's not that I didn't read you, it's that I had a hard time following your advice as I needed to better understand how some parameters worked. You're going too fast for newbies. 


Spoiler: Curve Optimized



To summarize, start from scratch. I started setting all the cores to -30 and PBO Limits the Motherboard and then with the Core Cycler with different P95 tests added to several Y-C ttest 15 and 16 I can say that it reaches a maximized curve. Then add some BO, +125, and there I stay. I don't want that Core Stretching you taught me . I spent almost 4 days with continuous tests, half frustrating the theme of optimizing the curve. Also try other methods, such as the one you told me about setting All-Cores to an offset, for example -15 or -20, which thus kept the AMD algorithm. And then, also, reading a lot in OCN I saw that several added on a maxed out curve a small offset going from 0.025v to 0.05V.. LLC 1 or 2.. But never get the boost on such low values, my curve end up with this values:

-28,
-26,
-26,
-28,
-24,
-26,
-28,
-25,
-24,
-26,
-25
-28,
PBO Limits of 300/235/245,
Scalar Auto

As I told you, try the curve as much as possible to avoid core stretching. When I put +125 I see that it only affects a couple of cores, so I don't have that much difference with the Effective Core
One of the mistakes I may have made is using a new Core Cycler test developed by Germans on a Rayzen 5000 OC guide. That new test, which includes Moderate mode, Heavy and Heavy short wasted a lot of time, maybe because I'm not stable with my memory overclocking yet, and that's why it may be giving me mistakes.
This is the link, in german, with the guide and the discussion: Leserartikel - Curve Optimizer Guide Ryzen 5000

Then there are also other parameters that can influence the OC of the curve, for example CPPEC and CPPEC Preferred Cores enabled, or for example C-states disabled to prevent idle restarts.In fact that's how I have them now, CCPC enabled and C-States disabled


Going back to the memories I followed your advice and raise the voltage to *1.58v *to test the RTTs. I had no problem getting post, or following weird bugs. No temperature, either. I Encouraged me to test what safe mode values look like compared to normal Windows startup. The difference is awesome, inclusive on CB20! I'm going to have to work on that since I have too many active processes, twice as many as you have. I'm looking at the Sophia App you passed me.

Here's the results at 1.58v:









And this is in Safe Mode (1.58v)








Before returning to 1.55v test running a quick test of TM5 1usmusv3 and in the third cycle start with errors.. so record them to share them and restart to get back to 1.55. It seems to me that I must have a problem with the vSOC, vCCD and IOD values, and I also do not have the correct values in the BIOS, such as VDDSOC LLC that I have in Auto and I think it should be in 3 and the VDDSOC Phase Control in Extreme.









What are these errors to, could it be because my vSOC, CCD and IOD values are very low? Another thing it could be is the DRAM values as I mentioned before: Here's my BIOS Values (I went back to 1.55v). I bet that I should change VDDSOC LLC to 3 and VDDSOC Phase Control to Extreme



Spoiler: BIOS Screenshots























It seems to me, and you can correct me, that I don't have that much stretching, here you can see it on CB20


Spoiler: CB20 Results with VDIMM 1.58v












And this is the score in Safe Mode.. Impressive the multiscore value











Well, how do you suggest I go on? We already know that I have no temperature problems, nor of getting post at 1.58. TM5 errors can indicate something. Maybe I should go to more aggressive RTTs, for example go back to RTTPark 1 or 3 and lower the voltage to 1.5. What else could I prove? I really have to thank you very much for your great help, the performance improved a lot

Thanks @Veii !!


----------



## Veii

mongoled said:


> I gather when you did your above tests you stuck to your tried and tested vDDG CCD < 1.0v ??
> 
> You should have tried increasing CCD to something like 1.005v ....


Mean me ?
I tried the two Timing sets, 16-16-16 and my newer 15-15-15-30, also the 15-15-15-34
Errors appear randomly , and TM5 errors out. Some interrupts happen & usb droupsout
I do run 1030 CCD - and played a bit to make it work with 1201, but the reason is something else

I got an updated PSP Firmware, can now confirm it.
It doesn't flash back neither by downgrading to the first bios for 5xxx nor by then flashrom upgrade upwards
I'm stock with it now
















vs








^ old picture, but it shows very well NumCoresInCCX = 0

SMU 56.50 / AGESA 1.2.0.1 flashed a new PSP-Firmware
We'll see if i keep having usb issues again on 56.44 1.2.0.0 & IMC issues
But they 100% updated something i can not revert back with any tools i have


----------



## mongoled

Veii said:


> Mean me ?
> I tried the two Timing sets, 16-16-16 and my newer 15-15-15-30, also the 15-15-15-34
> Errors appear randomly , and TM5 errors out. Some interrupts happen & usb droupsout
> I do run 1030 CCD - and played a bit to make it work with 1201, but the reason is something else
> 
> I got an updated PSP Firmware, can now confirm it.
> It doesn't flash back neither by downgrading to the first bios for 5xxx nor by then flashrom upgrade upwards
> I'm stock with it now
> View attachment 2485980
> 
> View attachment 2485981
> 
> vs
> View attachment 2485982
> 
> ^ old picture, but it shows very well NumCoresInCCX = 0
> 
> SMU 56.50 / AGESA 1.2.0.1 flashed a new PSP-Firmware
> We'll see if i keep having usb issues again on 56.44 1.2.0.0 & IMC issues
> But they 100% updated something i can not revert back with any tools i have


Yes you

 

Thats very weird, that they release a fix and where as before you didnt have issues but now with the "fix" you do ...

And that you cant roll back, thats not so good!

Have you seen the recent threads regards no WHEA errors when using Windows OS no version higher than 1909 ??


----------



## Veii

mongoled said:


> Yes you
> 
> 
> 
> Thats very weird, that they release a fix and where as before you didnt have issues but now with the "fix" you do ...
> 
> And that you cant roll back, thats not so good!
> 
> Have you seen the recent threads regards no WHEA errors when using Windows OS no version higher than 1909 ??


Barely, but i heard about it
Same for HWInfo and RyzenMaster introducing it

Haven't been affected and i don't think it's windows related at all - rather board related. But i don't get them at all
Even now i don't get them

But with this new PSP Firmware, it hardlocks even at 2033 FCLK, while 2000 FCLK boots easy.
I try to debug and figure it out - but it's been nothing but issues.
Sadly yes, unless i manage to break the internal PSP-FW like on a 1700X by memory timings
Where the whole bios turned chinese and it force reset ~ i don't know how to fix it
It's inside an ARM chip , inside the CPU ~ and is only one way updatable

There is nothing i can do , to restore an old bios one . . .
Let me first figure out why i can't post beyond 2000 FCLK now > . >

EDIT:
After waiting 4-5min till memory resets itself
2033 posted - for now
Unsure if it's even stable at this point
USB Dropout needs to be tested for now , but yes ~ it's a mess. . .

EDIT2:
Aand randomly shutdowns while gaming, lovely
Trying my other set and 2T ~ and checking overboost bug issues
Also tested @PJVol 1.8v Tweak before the PSP FW update mess, it was funny
1.83v is stock for me, 1.850 posted but was unstable, 1.90v got to the bios but couldn't load win, 1.95v fully refused to post at all

Don't think it works for me 
Tried it at 900mV CPU VDDP and 860mV, well actually also 880mV but only one set & it refused to post
Maybe now with this PSP Firmware it's different
But honestly, everything is different ~ it can't tell so far what is a bug and what functionally was kept. It's just plain broken on everything

Without using EDC 400A, TDC TEL 90A and EDC TEL 90A (the 2 under EDC)
It can't even come anywhere close to the stock Cache bandwidth or latency.
No IPC improvement , nothing - but i got away from 56.50, it's too broken
"Cache FIX & USB FIX" - the exact opposite, borken cache and introducement of USB droupouts
If you've updated to the latest ASRock firmware - go down a step
Then go down another step to 56.26 
Ryzen-SMU-Checker-1208.zip 
update with flashrom up , if you want or don't 
but update step by step 

PSP-FW Update still remains in there and will continue to cause you issues
but at least 56.44 is less broken, no random TM5 errors at this point


----------



## _frame_

AGESA V2 PI 1.2.0.2 anyone?


----------



## Veii

lmfodor said:


> It seems to me, and you can correct me, that I don't have that much stretching, here you can see it on CB20
> 
> 
> Spoiler: CB20 Results with VDIMM 1.58v
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> And this is the score in Safe Mode.. Impressive the multiscore value
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Well, how do you suggest I go on? We already know that I have no temperature problems, nor of getting post at 1.58. TM5 errors can indicate something. Maybe I should go to more aggressive RTTs, for example go back to RTTPark 1 or 3 and lower the voltage to 1.5. What else could I prove? I really have to thank you very much for your great help, the performance improved a lot
> 
> Thanks @Veii !!


tRDWR is 1 too low if this is a dual rank set.

Downgrade away from your current bios. SMU 56.50 is broken. Go one down or one up
56.44 is fine 56.45 is fine
Both have the IPC bump and cache boost

Just run 400A EDC, & 90A SOC TDC and SOC EDC 
That does the same thing, actually perf is better than their supposed "fix" which broke everything including memOC 

This is what you want to run on the crosshair lineup - when it comes to LLCs


http://imgur.com/a/jFg2jPc

 - gallery link
You can enable full phase mode - by changing Power Phase Control to Extreme
But i've had a user who reported 40mV telemetry issues with a CH8 , where +40mV offset was needed to keep it stable under CTRs test. as V-TEL was dropping to 1038mV while CTR tried to set V-VID of 1078mV


----------



## Q Tech

Alyjen said:


> You can find lots about it on Reddit. This may just be addition to Windows that did not report some types of errors earlier, or some fck up in power management as lots of these whea events is related to low power states.
> My bet is that the errors where there, just hidden


Do you have any links please?

Regarding the errors being hidden, that was one of my first thoughts as well. However the errors on 2004 and newer are actually accompanied by instability as well, whereas there's no such instability on 1909.

If you haven't already, I encourage you to check out the thread I created regarding the issue, as I've documented there all of the testing I did before coming to this conclusion.


----------



## Q Tech

MrHoof said:


> My guess they improved WHEA detection with 2004.


That was one of my first thoughts too, however there is actual instability accompanying the errors in 2004 and newer. 1909 has no errors or instability, so it seems like it's not just down to better detection, but rather something is limiting how far the FCLK can be pushed before errors are caused on the newer versions.


----------



## PJVol

Veii said:


> on 4.85 PBO it's down to 630-580-600 compared to 680-640-650 & i can't go bellow 10.7ns , although it has to be 10.4


Just checked this and didn't see much difference from 56.44 results. Rather the opposite, no way I can get 10.4-10.5ns with smu 56.44 @EDC 300-350 amps

















This one was made with EDC 350, since I'm currently trying to balancing with this limit, so that it has minimal impact on performance either in heavy loads and medium memory stressing ones.


----------



## Veii

PJVol said:


> Just checked this and didn't see much difference from 56.44 results
> 
> View attachment 2485995
> View attachment 2485996
> 
> 
> This one was made with EDC 350, since I'm currently trying to balancing with this limit, so that it has minimal impact on performance either in heavy loads and medium memory stressing ones.


In CBS increase both Package Throttle limits to 400W 
And SOC TDC, SOC EDC on PBO to 90A 
You should be hitting 680-650-630 at least
Beyond 650 on L3 @ 10.4 yes


----------



## SD...

5950x Dark hero Bios 3302 Ram g.skill 3600cl14 DR
Anyone can help me get this ram stable, I keep getting errors in Tm5 (error 10) lowered my twr from 14-10 and still get the same error.


----------



## SesioN

Sleepycat said:


> Reduce your ClkDrvStr to 24. Also consider increasing CsOdtDrvStr and CkeDrvStr to 24. With your kit, ProcODT should run fine at 43 as well. I would also increase VDDG CCD and VDDG IOD to 1.05V, then try for 3800 / 1900IF.


I've tried reducing the ClkDrvStr from my current setting 60 to the following values:
24, 40

With 24 it barely boots windows, ended up with a freeze.
With 40 it it didn't freeze but did error out quite quickly on mem test.

While with 60 it seems stable.

Also ProcODT 48 is more stable for me than 43. With my current settings 43 seems to error out after a while on mem test.

Question 1)
What benefits would I get by lowering that value?

Question 2)
Is that setting maybe bound to other settings? As I only tested lowering that one setting value. No other settings were changed in that test run.

Question 3)
What benefits would I expect from setting CsOdtDrvStr and CkeDrvStr to 24 instead of 20?


----------



## SesioN

Veii said:


> It misses correct calculation for 16gb dimms
> For such use rather:
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> Haven't figured out another way to calculate tRFC for 16gb dimms (dual rank) & i don't want to borrow/steal his code
> Also more people worked on it there. Would be unfair to just copy it.


I've tried using that by entring 3733, 2x DR, 14, 8, 15, 14 but the calculated TRFC is way higher than my current settings. So I don't get it. Probably misunderstood something :/


----------



## AmateurRanger

Thought I had a stable build, no whea, OCCT ran for 4+ hrs but then I got 2 errors in TM5 Extreme1, #9 and #10 one each. I've tried to search this thread but haven't seemed to find a definitive answer. Does anyone by chance know what problems these 2 tests represent? Newbie here any help is highly appreciated. Many thanks!!


----------



## PJVol

Veii said:


> In CBS increase both Package Throttle limits to 400W
> And SOC TDC, SOC EDC on PBO to 90A
> You should be hitting 680-650-630 at least
> Beyond 650 on L3 @ 10.4 yes


If you mean cTDP and Package Power Limit (cause there's nothing more like those you mentioned), they didn't seem to affect L3 bw for me. The max I've seen is 650-ish.
In my case, setting the correct PPT limit turned out to be way more important. I found it's optimal value to be a couple watts above what it used to reach in heavy load.
Otherwise (when it's set to something like mb limit) clocks start stretching massively in heavy load, as if SMU is unaware of the part of power budget, that throttling data fabric eats out.


----------



## lmfodor

Veii said:


> tRDWR is 1 too low if this is a dual rank set.
> 
> Downgrade away from your current bios. SMU 56.50 is broken. Go one down or one up
> 56.44 is fine 56.45 is fine
> Both have the IPC bump and cache boost
> 
> Just run 400A EDC, & 90A SOC TDC and SOC EDC
> That does the same thing, actually perf is better than their supposed "fix" which broke everything including memOC
> 
> This is what you want to run on the crosshair lineup - when it comes to LLCs
> 
> 
> http://imgur.com/a/jFg2jPc
> 
> - gallery link
> You can enable full phase mode - by changing Power Phase Control to Extreme
> But i've had a user who reported 40mV telemetry issues with a CH8 , where +40mV offset was needed to keep it stable under CTRs test. as V-TEL was dropping to 1038mV while CTR tried to set V-VID of 1078mV


Hi @Veii, you are a genius! Thanks for your help [emoji4]. I’m gonna downgrade the BIOS, I just upgrade to this new version because of the Update to AGESA V2 PI 1.2.0.2. I will find what BIOS versions belongs to SMU 56.45

Another question, where did you see that I have tRDWR in 1? Actually is set to 8


Spoiler














What I noticed is tCKE was set back to 1 instead of 9. Maybe when I loaded some profile I lost this value. 

Do you want me to try again 1.58v with TCKE at 9? To see if the TM5 errors continues? When I set back to 1,55v doesn’t appear anymore..

Thanks for the screens of the Asus VDDSOC LLC and phase control. I will try with those settings

So recap, I should go back to previous bios, change the tCKE to 9.. and I don’t know what to do with tRDWR.. and final, sorry for the noob question, I’m gonna set EDC to 400A, but when to said set “SOC EDC and SOC TDC to 90A” is another option? I never heard or read about this settings, only those that are in PBO limits

And last question, mongoled suggested to increase my VSOC from 1.14v to 1.175, then VDDP from 0.9 to 0.905 and CCD from 0.95 to 1.005v. I tried this but TM5 reported 1 error. Would you see fine this increase? I mean to be in line with my timings and more now that I’m running 1.55 without any issue. 

Thanks again @Veii!!


Sent from my iPhone using Tapatalk Pro


----------



## mirzet1976

AmateurRanger said:


> Thought I had a stable build, no whea, OCCT ran for 4+ hrs but then I got 2 errors in TM5 Extreme1, #9 and #10 one each. I've tried to search this thread but haven't seemed to find a definitive answer. Does anyone by chance know what problems these 2 tests represent? Newbie here any help is highly appreciated. Many thanks!!
> 
> View attachment 2486002


See here Ryzen Google Calculator


----------



## Martin778

Mr.Pink said:


> wow, wich ram do you use?


G.Skill TridentZ Neo 3800 CL14, 4x8GB.


----------



## PJVol

mongoled said:


> If only we could get more detailed information to what is the exact cause of the WHEA warning....


If im not mistaken, most 19 WHEA's with IF 1933+ are hardware corrected errors, at least in my log viewer. They are MCEs and according to control and status fields, that bank mapped to PIE block, and the error is "generic bus" and type "GMI link error"


----------



## Veii

lmfodor said:


> Hi @Veii, you are a genius! Thanks for your help
> 
> 
> 
> 
> 
> 
> 
> . I’m gonna downgrade the BIOS, I just upgrade to this new version because of the Update to AGESA V2 PI 1.2.0.2. What is SMU?
> 
> Another question, where did you see that I have tRDWR in 1? Actually is set to 8
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> What I noticed is tCKE was set back to 1 instead of 9. Maybe when I loaded some profile I lost this value.
> 
> Do you want me to try again 1.58v with TCKE at 9? To see if the TM5 errors continues? When I set back to 1,55v doesn’t appear anymore..
> 
> Thanks for the screens of the Asus VDDSOC LLC and phase control. I will try with those settings
> 
> So recap, I should go back to previous bios, change the tCKE to 9.. and I don’t know what to do with tRDWR.. and final noob question, I’m gonna set EDC to 400, but where should I set SOC TDC and SOC EDC to 90? I never see that options!
> 
> And last question, mongoled suggested to increase my VSOC from 1.14v to 1.175, then VDDP from 0.9 to 0.905 and CCD from 0.95 to 1.005v. I tried this but TM5 reported 1 error. Would you see fine this increase? I mean to be in line with my timings and more now that I’m running 1.55 without any issue.
> 
> Thanks again @Veii!!
> 
> 
> Sent from my iPhone using Tapatalk Pro


SOC TDC & SOC EDC are under EDC on the AMD OVERCLOCKING -> PBO ADVANCED limits menu
tRDWR should be 1 higher . Your current value is 1 too low ~ make it 9.
I mean if 8 works, then nice
It's not unexpected that you have to increase tRRD & tWTR higher for higher speeds
Really depends on the PCB.

tCKE is nice to have and does help, but using it adds latency
It should not be a "required" stability thing - unless you have voltage stability issues.

Your voltages can be fine - i just had issues with 950mV VDDG CCD, it had to be lower than 940 with a lot of SOC voltage
or both higher (1030-1100 for 2100 FCLK) while i also run 2100 FCLK before with 940-1120 @ 1.25vSOC
Depends really

I'm finally back to usable settings, but should have tested it before TM5. It's always updating interface eats around 0.4ns


Spoiler














There is usually no need to be 5mV specific , it will autocorrect downwards and split it. 
VDDG is split & will continue to autocorrect both values. There is no reason to make it "read" a perfect value. 
You can't even. If you change CCD, IOD adjusts. If you change IOD, CCD adjusts. 
Only SOC matters as GET voltage (including loadines). The rest are SET voltages


----------



## GribblyStick

OK, so if everything goes right, I should be able to start installing my custom loop sometime next week or so. I'll start testing again in earnest then.
In the mean time, it seems you guys have a better handle on how to configure CPU related settings by now, so I went and got CTR 2.0 RC5 and ran some diagnostics.










That was the best out of 3, the previous two runs returned it as a silver sample.
What I changed about CPU settings was to adopt the power regulation settings @Veii suggested. That's it, everything else should still be on auto.
I haven't touched anything related to PBO or all core. Nor anythign with TPC or EDC.

My RAM performance didn't really change far as I can tell, maybe lost some latency, but I ran a Cinebench R20 before and after the LLC modifications and went went from average of around 8266 to 8100, so I seem to have lost a little there. I don't want to mess around much with the curve optimizer until I have the loop installed but I guess I can already modify some other settings?

That would be the following? (not quite sure yet here to find them)
400A EDC,
90A SOC TDC and SOC EDC

Windows:









Current RAM config: (1,5 VDIMM)









PS.
I also have another 5900x that previously wasn't able to run above 3600, but in retrospective, I may have jumped the gun buy getting another.
I have yet to benchmark that with CTR, Do you think I should give it a shot as well? 
I had more issues with memory but it also boosted up over 5GHz on default settings , which this new has not yet. And the issues my have been simply a lack of OC experience.
Thouhg I imagine if I already had issues with 3800 before I can't really expect much of a difference between the two? 
(Can't say I'm keen on reinstalling the AIO, the mounting system is a bit iffy)


----------



## lmfodor

Veii said:


> SOC TDC & SOC EDC are under EDC on the AMD OVERCLOCKING -> PBO ADVANCED limits menu
> tRDWR should be 1 higher . Your current value is 1 too low ~ make it 9.
> I mean if 8 works, then nice
> It's not unexpected that you have to increase tRRD & tWTR higher for higher speeds
> Really depends on the PCB.
> 
> tCKE is nice to have and does help, but using it adds latency
> It should not be a "required" stability thing - unless you have voltage stability issues.
> 
> Your voltages can be fine - i just had issues with 950mV VDDG CCD, it had to be lower than 940 with a lot of SOC voltage
> or both higher (1030-1100 for 2100 FCLK) while i also run 2100 FCLK before with 940-1120 @ 1.25vSOC
> Depends really
> 
> I'm finally back to usable settings, but should have tested it before TM5. It's always updating interface eats around 0.4ns
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2486046
> 
> 
> 
> There is usually no need to be 5mV specific , it will autocorrect downwards and split it.
> VDDG is split & will continue to autocorrect both values. There is no reason to make it "read" a perfect value.
> You can't even. If you change CCD, IOD adjusts. If you change IOD, CCD adjusts.
> Only SOC matters as GET voltage (including loadines). The rest are SET voltages


Hi @Veii , How you doing? 
I didn't rollback the BIOS yet. But what I did is to set the VDDSOC LLC and its phase control as the settings you send me in the screenthost to see if the increase that @mongoled suggested me, I now with just on TM5 1usmus I could pass. I'd need to test at least for 25 cycles to see if it holding well. So now I will

1) Increase tRDWR to 9.
2) I could increase also tRRD & tWTR. What values do you suggest to try? I have faith on my PCB 🙏 
3) About VDDG CCD, in fact I had it set to 0.95v before and the reading from ZenTimings was 0..94xx. I increased all voltage values following the Mondoled suggestion.. So far it seems well.. But first I will try 25 cycles of TM5 
4) Regarding increase EDC to I did increase to 400 from 245 as you recommended me at first, but then I'm confused about how I should set an specific VSOC EDC and VSOC TDC, I mean, is not the same parameter? I mean, the only way to change PPT, TDC and EDC are in the main menu of Asus Bios under PBO, and in Advance OC -> PBO, and I only only this section to change PBO limits, I leave the PBO Limits in the main menu as AUTO.. So, EDC should be 400A or 90A? TDC I can lower from 235 to 90. Am I right? Sorry if I confused with this


Spoiler: PBO Limits Advanced Overclocking Menu














This is how it's running now. I need to debloat windows.. working on it!. How do you see?










Thanks!!


----------



## PJVol

Veii said:


> I'm finally back to usable settings


Nice. 
Sadly, i seem to reach the limit of my sticks, since 1.2.0.1 wants me to up vdimm from 5.12 to 5.24 for the same preset to pass TM5 3 cycles at least. Pushing it further leads to #13 1usmus' errors, that requires additional fans for the memory, which I dont wanna deal with tbf ))


----------



## RonLazer

@Veii 

Our of curiosity, what in your opinion is the best AGESA version for FCLK overclocking Zen3 currently? Does it vary by board vendor?


----------



## lmfodor

Veii said:


> SOC TDC & SOC EDC are under EDC on the AMD OVERCLOCKING -> PBO ADVANCED limits menu
> tRDWR should be 1 higher . Your current value is 1 too low ~ make it 9.
> I mean if 8 works, then nice
> It's not unexpected that you have to increase tRRD & tWTR higher for higher speeds
> Really depends on the PCB.
> 
> tCKE is nice to have and does help, but using it adds latency
> It should not be a "required" stability thing - unless you have voltage stability issues.
> 
> Your voltages can be fine - i just had issues with 950mV VDDG CCD, it had to be lower than 940 with a lot of SOC voltage
> or both higher (1030-1100 for 2100 FCLK) while i also run 2100 FCLK before with 940-1120 @ 1.25vSOC
> Depends really
> 
> I'm finally back to usable settings, but should have tested it before TM5. It's always updating interface eats around 0.4ns
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2486046
> 
> 
> 
> There is usually no need to be 5mV specific , it will autocorrect downwards and split it.
> VDDG is split & will continue to autocorrect both values. There is no reason to make it "read" a perfect value.
> You can't even. If you change CCD, IOD adjusts. If you change IOD, CCD adjusts.
> Only SOC matters as GET voltage (including loadines). The rest are SET voltages


Hi @Veii , I follow your instructions and I tell you what I did:
1) Just increase tRDWR, run TM5 25 cycles without any error and test the curve. The Core and Effective core almost match, so I think the curve is fine, a pretty stable yet. I also ran Sophia, and lower the Windows process to the half.. but still I'm above 120 process. I have the typical games services, you know, Microsoft Game Pass, EA Sport, some Asus Lighting and Fan Services.. I need to work to lower this serices because is impacting in the latency. However, in this scenario what I want to do is to increase the speed with tRRD & tWTR, for instance,
- Rising tRRD_S and _L from 4/5 to 7/9 as you? The same for tWTRS and L from, 4/10 to 5/14 would be fine?
And also remeber when you recommend me this after lowering the tRRD & tWTR to lower primaries and after increasing them to do the following:
_Decreasing voltage again_
_* high tWR and tRFC is not a big latency issue ~ when primaries are low, it still ends up positive & beneficial _
So with TWR at 14 should be fine? I'm always looking your timings to compare, and tRFCis set to 252, should I increase it?










Well, and as I read you I took my time to do all the homework, I copied all your settings in two steps:


Spoiler: Veii's Timings - Primaries and tRRD / TWTR



As you can see, as a first step I copied the primaries and values until tRFC to see I could get POST.. I ran AIDA in normal mode and in safe mode to see the difference. Pretty similar to my previous timings in terms of results.. but a lot of errors!










Then:


Spoiler: Veii's Timings all values (except Tertiary, 1T, and Voltage Values)



I tried once more time to enable 1T, and even I get POST, I also get a BSOD. I don't know why, what are limiting to enable it, could be more hard to achieve in dual rank?
As the numbers were low, I decide to share with you to give me your advises.. 











For now I continue with the original configuration, with the aim of increasing the values of tRRD / TWTR to increase speed, reducing voltage, adjusting the tRFCs and if it is necessary to adjust some RTT, which is what you had originally suggested to me, Am I right?

Thanks!


----------



## jomama22

Veii said:


> SOC TDC & SOC EDC are under EDC on the AMD OVERCLOCKING -> PBO ADVANCED limits menu
> tRDWR should be 1 higher . Your current value is 1 too low ~ make it 9.
> I mean if 8 works, then nice
> It's not unexpected that you have to increase tRRD & tWTR higher for higher speeds
> Really depends on the PCB.
> 
> tCKE is nice to have and does help, but using it adds latency
> It should not be a "required" stability thing - unless you have voltage stability issues.
> 
> Your voltages can be fine - i just had issues with 950mV VDDG CCD, it had to be lower than 940 with a lot of SOC voltage
> or both higher (1030-1100 for 2100 FCLK) while i also run 2100 FCLK before with 940-1120 @ 1.25vSOC
> Depends really
> 
> I'm finally back to usable settings, but should have tested it before TM5. It's always updating interface eats around 0.4ns
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2486046
> 
> 
> 
> There is usually no need to be 5mV specific , it will autocorrect downwards and split it.
> VDDG is split & will continue to autocorrect both values. There is no reason to make it "read" a perfect value.
> You can't even. If you change CCD, IOD adjusts. If you change IOD, CCD adjusts.
> Only SOC matters as GET voltage (including loadines). The rest are SET voltages


Just want to let you know that SOC TDC and SOC EDC aren't available for most motherboard bios' unlsss an apu is detected as installed. So recommending changing these will probably cause confusion (unless in an asrock MB).

They simply so not show for most motherboards.


----------



## lmfodor

jomama22 said:


> Just want to let you know that SOC TDC and SOC EDC aren't available for most motherboard bios' unlsss an apu is detected as installed. So recommending changing these will probably cause confusion (unless in an asrock MB).
> 
> They simply so not show for most motherboards.


Thanks! I didn’t understand if Veii suggested me to change the “‘normal” EDC or the VSOC EDC and TDP.. it seems strange for me that a mobo Asus ROG doesn’t have it ..
Thanks for the clarification!!



Sent from my iPhone using Tapatalk Pro


----------



## FastOne8

Guys i might need some help. My gskill memory reaches 55-60*c in stock DOCP profile (1.35, [email protected]). I didn't even overclock anything!

PC:

Case: Phanteks P500A.
CPU cooler: Noctua D15S
CPU: Ryzen 5900x
Motherboard Asus B550-F
RAM: Gskill Trident Z [email protected] DOCP (not overclocked)
GPU: RTX 380
PSU: Corsair rm850x

3 intake fans, 2 exhaust on top and 1 exhaust on the back.

Today when I was playing Cyberpunk I checked HFInfo and noticed that both of my DIMM modules are at 55*C each.
I asked around and people say that even overclocked memory at 1.5 v won't reach that much and I'm basically ****ed.

I decided to see how far my temperatures on DIMM will go and ran TestMem5 + Furmark for 15 minutes and during that time the temperatures climbed to 60*C and they keep increasing. I'm sure if I didn't pause the test it would go even higher.
My RAM doesn't have any RGB so I can't turn it off to get better cooling. Also my CPU is really really hot. I probably lost silicon loterrey but in Cyberpunk it sits around 75-76*C while GPU around 65-67. It doesn't error out, crash or bsod. But it's pretty toasty

What options do I have? What do I need to change?
Switching to AIO (For example Arctic Liquid Freezer ii 360) can make ram cooler in this current setup?


----------



## mackbolan

Veii said:


> Pretty much, same voltage on a pretested preset
> Something you know X serial number part can reach on your setup with RTTs for 2 dimms
> then lower voltage till it starts to error and try swapping one dimm till it passes
> 
> timings & voltage always go from the weakest link in the chain
> but binning takes time
> waiting time for stability tests to start failing - where you have to also factor in room temperature , or at least run a config that takes over 1 hour ~ soo dimms reach thermal equilibrium
> 
> Powerdown's functionality , in this case only tCKE - does instantly react between loads
> It takes less than 1 sec making the system crash after you close TM5
> or making it crash between tests
> 
> RTTs do adjust at the very start
> But dynamic ODT (RTT_WR) if enabled, is constantly updating and adjusting signal quality to keep a clean data-eye open
> Both of them can crash randomly or between test jumps
> Usually tCKE's crash between , before and after load ~ and they are slopes you have to time by MCLK
> 
> You are not ignored because of your old CPU
> but quite honestly, there is already soo much data out about Matisse and barely about Vermeer
> 
> DRAM OC didn't change that much between them, but this exists
> Zen RAM Overclocking (ZEN 2) ~ Reddit made
> and this OCN madeone
> 
> 
> 
> 
> 
> 
> 
> 
> AMD RAM overclocking
> 
> 
> ZEN 2 - Matisse (7nm TSMC) s name,latency,FCLK,MT/s,timings,DIMMS,IC-type,part number,read,write,copy,VSOC,VDDG,VDIMM,VDDP,ProcODT,RTT,stability test,CPU,mainboard Reous,57,5 ns,1900 Mhz,3800 Mhz,<a href="https://abload.de/image.php?img=380014-14-13-1310000kzbkdb.png">14-13-14-13-30-44-247</a>...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> there are soo many resources to compare how you stand up against other similar rresults
> 
> But to be again honest with you
> The only reason i did not answer instantly , or skipped it
> Is that i don't know what you can improve on your set
> I don't know any new secret that could make it better ~ with this strange 14-8-15 set
> I can only ask, why you won't spend more time to try and get 14-14-14 to run ?
> A flat timings set nearly always performs better, unless the awkward one ticks couple of strange boxes
> 
> Hahaha,
> It's 2x 8c CCD
> But it doesn't behave like one yet ~ microcode of a 6 core is enforced, till i figure out what to change and where
> 2nd CCD might be permanently active, but it doesn't get any load. it can't get any as the microcode doesn't give a correct core layout to the system (ACPI Layout)
> soo they stay unused and can not have any benefits
> 
> It's a big piece of problematic CPU, there are no positives in it's current state that boost me anywhere on anything
> I can not use allcores and only PBO can attach to the correct cores ~ where this little thing is limited at 4.85ghz (+200Mhz boost-target override) , while it can reach 5025Mhz in reality
> (CTR but that's a secret topic for now & doesn't work with Aida64 well)
> * also i work on a little powerplan that utilizes these overboost 6+ ghz spikes and gifts 0.3-0.4ns more & 20GB/s cache, but it's not done yet and wasn't used on the leaderboard
> Example: https://twitter.com/VeiiTM/status/1372128316942135297
> 
> Settle a bit lower to 4750 guaranteed and lower CO a bit further with added positive vcore offset
> The system will autocorrect & clock-stretch. This costs you latency
> 4.75 on all cores should be 10.7ns L3 or 10.6 if you get it well
> 
> Timings are fine, good job on 1T GDM off !
> If you feel like doing more, go for weaker RTTs (higher divider number) and run 60-20-40-20 on it (increased ClkDrvStr)
> You should not need 40ohm procODT
> and you should not need VDDG CCD that high
> (voltage crashes are verifiable with y-cruncher all tests 4 loops 4*8min & later OCCT Extrerme AVX2, Large Dataset)
> If both pass then you are fine, but you will need lower voltages if you want lower procODT = higher potential FCLK
> Check if you can find CPU_VDDP to lower it down to 880 or 860mV


I've been busy and just read this. So what's happened since before is I went to an ASUS TUF X570 Gaming-PLUS and had a newer BIOS with the proper SMU and it was stable at the pics I shared. The AIDA shot showing 4750 is just during the test not an all core thing, it what it reads I guess because that's what PBO +100 delivers. Fast forward to now. 4/9/21 ASUS released a new BIOS with AGESA 1.2.0.2, which made my RAM unstable in AIDA and caused a single error in TM5. It did correct the way too high voltage/current to the CPU during boost and improved PBO quite a bit.

I got my RAM stable again by increasing CAD BUS to 40-20-30-20 but I noticed decreased read/write in the RAM. So I started messing with 4000/2000 again and it still runs fine aside from error 19's under load that don't seem to affect anything but the Event Viewer. Not one error in TM5 or any other test! I kept the same timings as for 3933/1966 but increased DRAM voltage to 1.45v at the end to rid me of a single error I got during TM5. 

I can try lowing those voltages as you said but I think I had issues with lowering SOC to keep that FCLK. The other voltages I picked off some other posts that seemed to stabilize others using the same 3933/1966 I was. In fact, I think there might be some on the spreadsheet? I looked for those running B-die to get an idea of what they were using for VDDP, CCD and IOD was raised to clear up an audio defect. I thought B-die needed 40Ohm procODT but searching I think I get where you're going is if I find the right RTT's and use the higher CAD's, I can lower procODT to like 34.3 and reduce heat or lower my DRAM voltage. The latter is probably best at 1.45v for running at 3933 or 4000 and keeping CL16 flat. 

This new BIOS really sent me in a whirl, since it tossed my RAM settings that previously worked into an instant BSOD on trying AIDA, yet fixed the vCore and boost issue. I could probably go back to my all core 4675 at 1.275v thanks to this AGESA version. First, I'd like to try to eliminate this error 19 and run at 4000/2000. It looks like the problem is actually in the L1/L2 cache read/write speeds. More so the L2 is off by a whopping 98GB! So according to some reading that's SOC too high or ... low? I've heard of people going slightly over the 1.2 area but below 1.3. 

Lastly, I found a thread in regards to phase, LLC and frequency where I have LLC 4 set but only run my phases "optimized", when "extreme" might be better with frequency set to 400 vs. 200. It goes up to 500 but I'm not sure if that high is ok.


----------



## mackbolan

Veii said:


> You actually should be able to run CL14-14 then, if it was a board issue
> 
> 
> Spoiler: For example
> 
> 
> 
> 
> View attachment 2483134


There's a post about AMD Zen 3 in particular not liking odd CL's, hence 15 won't work without GDM=on, which makes the IMC round the CL to 16. So either make it run 14 or do 16, but use even numbers at least with Zen 3 and I found Zen 2 to be the same like my 3600X in my other system
.


----------



## Theo164

I need help to boot 4x8 g.skill b-die ram above 3800, I've try voltage up to 1.5v auto subtimings, manual loose timings/subtimings, 2T-GDM off but no luck...
Cpu can boot 2000fclk, 1933/1966 doesn't
3800/1900 24/7 tested no memory errors no whea


----------



## lmfodor

Veii said:


> SOC TDC & SOC EDC are under EDC on the AMD OVERCLOCKING -> PBO ADVANCED limits menu
> tRDWR should be 1 higher . Your current value is 1 too low ~ make it 9.
> I mean if 8 works, then nice
> It's not unexpected that you have to increase tRRD & tWTR higher for higher speeds
> Really depends on the PCB.
> 
> tCKE is nice to have and does help, but using it adds latency
> It should not be a "required" stability thing - unless you have voltage stability issues.
> 
> Your voltages can be fine - i just had issues with 950mV VDDG CCD, it had to be lower than 940 with a lot of SOC voltage
> or both higher (1030-1100 for 2100 FCLK) while i also run 2100 FCLK before with 940-1120 @ 1.25vSOC
> Depends really
> 
> I'm finally back to usable settings, but should have tested it before TM5. It's always updating interface eats around 0.4ns
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2486046
> 
> 
> 
> There is usually no need to be 5mV specific , it will autocorrect downwards and split it.
> VDDG is split & will continue to autocorrect both values. There is no reason to make it "read" a perfect value.
> You can't even. If you change CCD, IOD adjusts. If you change IOD, CCD adjusts.
> Only SOC matters as GET voltage (including loadines). The rest are SET voltages


Hi @Veii, I think I can make a good step not only with the bandwidth, the latencies and also the curve. What I did was raise the tRRDs, tWRTS, lower the voltage to 1.52v and return to the values of vSOC, VDDP, CCD and IOD previously defined. I put the RTTs at 7-3-1 (strong) so I should lower the volatge even further? And I also went back to tCKE in 1. Also, optimize Windows processes more, not much, just a few more. And I think it was essential to set the values of LLC, Phased Control, Switching Frecuenty as recommended. I think the result is good. I ran several tests. 25 of TM5, OCCT Large, cycling cores, and 4 iterations of y-cruncher all test. You can see below in the HWInfo screenshot the maximum consumptions of ECD TDC and PPT. Really high and regarding the temperatures I also consider them good, just above 40 degrees in memories and 82C in the CPU in one of the hardest tests. CB20 +9100 and single core 636. Do you notice any inconsistency, any value to optimize or to consider? Lower the voltage even further? I'm super happy with the result. 😀 


















Spoiler: VRMs LLC Settings from DRAM Calculator



I hadn't noticed the recommendations here. They're the ones you sent me.










Thanks for your great support!


----------



## Pictus

FastOne8 said:


> Guys i might need some help. My gskill memory reaches 55-60*c in stock DOCP profile (1.35, [email protected]). I didn't even overclock anything!
> 
> PC:
> 
> Case: Phanteks P500A.
> CPU cooler: Noctua D15S
> CPU: Ryzen 5900x
> Motherboard Asus B550-F
> RAM: Gskill Trident Z [email protected] DOCP (not overclocked)
> GPU: RTX 380
> PSU: Corsair rm850x
> 
> 3 intake fans, 2 exhaust on top and 1 exhaust on the back.
> 
> Today when I was playing Cyberpunk I checked HFInfo and noticed that both of my DIMM modules are at 55*C each.
> I asked around and people say that even overclocked memory at 1.5 v won't reach that much and I'm basically ****ed.


I would update the BIOS


ROG STRIX B550-F GAMING | ROG Strix | Gaming Motherboards｜ROG - Republic of Gamers｜ROG Global


Verify the settings(voltages/impedances) with 








ZenTimings


ZenTimings is a simple and lightweight app for monitoring memory timings on Ryzen platform.




zentimings.protonrom.com




And set the first case top fan to blow air into the RAM sticks.


----------



## gabian

Hi, i have question about TEMP. i have F4-3800C14Q-32GTZN . Upon TM5, temp goes at 50°C . Is it too high ? Is there a particular timings involving more heat ?


----------



## lmfodor

gabian said:


> Hi, i have question about TEMP. i have F4-3800C14Q-32GTZN . Upon TM5, temp goes at 50°C . Is it too high ? Is there a particular timings involving more heat ?


Yes, is very high. It shouldn’t run above 45 degrees, cause error would appear. My suggestion is to put a fan on top the memories at Max speed..and keep a cool ambient temperature. With these 2 thing you should be 29/30 on idle .. 33/34 under normal use and around 32 in stress test. 


Sent from my iPhone using Tapatalk Pro


----------



## mongoled

A baseline for those who have the hardware to run 4133/2066.

Bare in mind this is on Windows 1909 hence WHEA warning free, on anything higher than 1909 it becomes a WHEA warningfest !!

Also not yet stable with Y-Cruncher, after around two hours the PC will reboot, still toying with what the cause of the stability is.

Oh and benchmark results are a little lower than what they could be as they were run with HWInfo64 running.


----------



## gabian

lmfodor said:


> Yes, is very high. It shouldn’t run above 45 degrees, cause error would appear. My suggestion is to put a fan on top the memories at Max speed..and keep a cool ambient temperature. With these 2 thing you should be 29/30 on idle .. 33/34 under normal use and around 32 in stress test.
> 
> 
> Sent from my iPhone using Tapatalk Pro


Do you have advice for a RAM cooler which would do the job ?


----------



## lmfodor

gabian said:


> Do you have advice for a RAM cooler which would do the job ?


The are a lot, but I use a common CPU tan spinning at 1100RPM and it works very well.. I will buy a RAM cooler, but I have to find one that adapt to my componentes. Meanwhile the single Noctua Fan do the job very well


Sent from my iPhone using Tapatalk Pro


----------



## shaolin95

Hello guys!

I am running 64GB but wondering if you see anything I could try to tweak my RAM more. I have tried 1T with GDM On but I seem to get a bit better performance with 2T and GDM OFF. Still, I am happy to test.


----------



## MrHoof

lmfodor said:


> Yes, is very high. It shouldn’t run above 45 degrees, cause error would appear. My suggestion is to put a fan on top the memories at Max speed..and keep a cool ambient temperature. With these 2 thing you should be 29/30 on idle .. 33/34 under normal use and around 32 in stress test.
> 
> 
> Sent from my iPhone using Tapatalk Pro


Well mine dont, tight timings and still stable at 55°C can see that on page 359, dont wanna post that big screenshot again. Since then I also ran karhu overnight and also no errors.

edit: the Hwinfo screenshot shows the temp after anta777 extreme 3 cycles


----------



## GribblyStick

huh, I just "upgraded" my PSU to an ax1600i. I lost up to 400 points in R20 and I'm all over the place with CTR, I went down to bronze after failing even the first diagnostic step and can't seen to undervolt below 1097 now (before 1073). What gives, I literally changed nothing and only swapped out the psu?


----------



## glnn_23

Paying around a bit more with my 4650g . Settings for Aida64 only.


----------



## TimeDrapery

@Veii,

You mention the following in one of your posts to another user...



Spoiler






Veii said:


> In CBS increase both Package Throttle limits to 400W
> And SOC TDC, SOC EDC on PBO to 90A
> You should be hitting 680-650-630 at least
> Beyond 650 on L3 @ 10.4 yes






How do you confirm this change is applied? My understanding of this submenu is very limited...

Would you please recommend some documentation/resources that I could look through in order to remedy my lack of knowledge?


----------



## PJVol

*@TimeDrapery*

Allow me to answer for him. Probably those settings are Asrock boards related only.


----------



## Veii

jomama22 said:


> Just want to let you know that SOC TDC and SOC EDC aren't available for most motherboard bios' unlsss an apu is detected as installed. So recommending changing these will probably cause confusion (unless in an asrock MB).
> 
> They simply so not show for most motherboards.


Yes, can't account for that 
Interestingly they do a change - same as NBIO CLCK DPM leveler does a change, without having an APU
But it's affects i couldn't not explore by this date. It surely matters more with an APU.
Seems like STAMP is nevertheless active, at least purely for cache related speedup (internally) without touching CPU clock telemetry
* Nevertheless to add, it does influence it a bit


thismock said:


> TCL + TCWL: I’m able to run CL15 up to 4067, and CL16 up to 4200. Unsurprisingly, 4067cl15 is faster than 4133/4200c16. TCL 15 implies TCWL 14, TCL 16 implies TCWL 16.


4067C15 flat, should match 4267C16 (2133) FCLK. 
It's a bit hard to compare, because tertiaries like tRRD also scale up by frequency and +1 already does a big change ~ where the higher the MCLK the bigger the jump-difference
But +200 MT/s = +1 tCL + 1 tRCD , is pretty much on point (same downwards)


thismock said:


> TRCDWR: this works as low as 12 for me, possibly lower, but I didn’t see a measurable performance increase, so I left it at 18 (from when I was trying to get TRCDRD to work at 18).


Only beneficial if you get it down to perfect half, else it adds latency and desync's the set. It's hanging with tCWL and tWR together. Pretty much an exploit type of thing.
Soo keep it equal to tCL or in case ttRCD_RD is not higher than tCL ~ match it and make it a flat set.


thismock said:


> TRAS: TCL + TRP, in this case 34.


Don't want to be the guy that "corrects", it's been done on me and it's really annoying to discourage new research methods
tCL or tCWL + tRP + BURST-length (up to capacity) , is one of the methods to match it under tCL or tCWL
~ but that is also an exploit type of thing
A more natural method is to focus on the primaries. tCL and tCWL both being nominators while they can vary by voltage and by scenarios
The main and most important timings are/is tRCD 
Both tRCD or tRCD & tCL , is a method to align it

Generally you can lower it till you choke instruction sets. It's the "gate keep up" or in technical terms "ROW ACTIVE Time".
While only reads need a full recharge and there are many little mechanisms and exploits that change this "JEDEC Behavior". Soo other methods work too
Generally again, you can lower it till it chokes.
Or you prefer to sync match it either with the exploit or an "avg" tRCD delay ~ capturing the write too, not only the read.
Minimum limit is 21 on AMD (sadly) soo you can not get it to behave in "burst" methods. You can not split them apart
~ which in easy understandings mean "keep it higher, it's cleaner" or "lower it as low as you can keep it stable and go the beating-head-against-a-wall , benchmarking method 


thismock said:


> The second step is to find the lowest stable TRC, which has a reasonable floor of TRP (18) + TRAS (34) - 2 == 50. I can’t boot anything less than 54, so my TRC floor is 54.


tRC is an arbitrary number, but also like tRAS a "sync thing"
Unlike tRAS which does a direct effect on the chain. tRC is an additive "mind-set" delay.
On intel systems down to DDR3 it was a mind value & no one really bothered considering it (tested tRFC mini on SO-DIMM DD3, my anchor works there too)

This "wait-for-action" additive delay, is used on several parts, but also to focus the delays elsewhere ~ soo you can lower the remain tertiaries and still get a beneficial effect out
It's a new thing, and on the newer JEDEC revisions maybe or maybe not mentioned. Although it has no "fixed" ruleset
I hope we are on the same path that this is a "sync" value. A variable on
There is an exploit out there for AMD, too to align as tRCDWR+tCWL+tWR+BURST. Nearly identical to tRAS
There is another exploit i figured to make it tRAS+1 , but this needs tFAW to be down to less or equal than tRRD_L . It should be equal or bit lower than tRRD_S (one time, not 4* )

The general rule on it remains tRAS+tRP. 
But if every other timing is higher, you can fully skip it and match it perfectly to tRAS. Technically it's not needed
Soo a rule of thumb to judge people's sets is "does it match tRAS+tRP or are you wasting delays to cover your mistakes" 
XOC cheat is to push this high - it does add stability, but the whole chain hangs on tRC then , as it will wait-for-action ~ till the whole tRC is over & isn't able to bypass and time-break, this one


thismock said:


> TWR / TRTP: from my testing and reading, TWR is ideally a factor of TRFC, and TRTP is itself ideally a factor of TWR. It’s my understanding that TWR must be an even number. Since TWR >= TRRDS+TWTRS, the lowest reasonable value for TWR is ~10.


This is a bad spread i take credit for ~ by not knowing it better early on
tWR same as tRTP only has to be an even value if GDM is engaged
My personal sync point is a clean or .5 decimal of tRFCns = "not half of tWR" , but "half of tWR" works perfectly and is often needed to gain stability 
tWR should be able to go down to 8, but that's an AMD limitation we have here. Actually even down to 6.


thismock said:


> TRRD / TFAW / TWTR: I started with a reasonably loose set in 7-9-28 for TRRDS-TRRDL-TFAW, and TWTR auto-ed to 6-14. I haven’t been able to do better than these settings, yet. Interestingly enough, the 1x TFAW setup is stable for me (6/8/8), but it requires a higher TWR (26), and is ultimately a net loss in performance (probably doesn’t make sense anyway because of the high TRC, but it was interesting to try).
> 
> *SC/SD/DD: I left these on AUTO, which was ultimately set for 1-6-6-1-4-4. I haven’t played with changing these numbers yet.


tRC pointing above is a little synching timing. A helping thing we get to use on AMD. 
tRRD_ and tWTR_ have a direct connection with SD, DD's i figured
Which then have a connection with the most affecting tRDWR timing

To be more clear "the difference in delay between RDRD and WRWR 
More to it when i can give a full tutorial.
A distance of 2 remains to be the "currently" best.
A value of 3 or 4 as a distance changes the pattern between _S & _L on both tRRD & tWTR

1x tFAW exploit, needs to run tRAS+1 = tRC, else you have performance regressions & 4* tRRD_S = tFAW makes more sense and is cleaner
It again is to noted that this doesn't work on Renoir or lower, it's a new thing. 
DDR3 can work with 2* tRRD but this exploit is really not beneficial on anything else than Vermeer and higher
2x tRRD_S = tFAW even when it sounds logical , does also kill performance. 

tRRD and tWTR , between _S & _L depend fully on the PCB density, trace length and capacity
They give a significant perf, as they are "holders" between different primaries actions (elementary explained) , but i've figured that increasing them for stability & reducing primaries generally has a bigger speed effect, than just lowering anything else lower.
The speed and lower primaries at X time (4200C15-15 = 3800C13-13) has just a far bigger perf effect 

Good writeup , helps to capture old split information into a linkable topic !


----------



## Veii

BarrettDotFifty said:


> Running this dual rank b-die kit stable at 1.45V as a 24/7 setup. Can't be bothered to go higher frequencies than 3600. Anyone have some ideas for timing improvements? What should I look into tightening next?
> 
> View attachment 2485574


Pretty much the same thing i tell everyone
_Have a stable main set, before starting_

First focus on weakening RTT_PARK, to something lower
Soo dimms heat up less / you can then use more voltage to push things / and the PCB has less strain
Also helps you get procODT a bit lower

Then after that's done, increase close to everything
tRRD, tWTR, tWR, tRTP
and try to get these flat primaries stable
AFTER you are already done with pushing frequency up ~ with a weaker 16-16-16 set

It can happen that you need to losen tRFC a bit, as tighter primaries will demand more voltage and so cause more strain
It's expected that the PCB won't be thaat stable (the main reason you should weaken your powering in the first place to lower heat and strain a bit, before continuing)
Later you can at any time tighten down tWR, tRTP & tRFC without issues 
But bad primaries will be masked by tens of thousand possible issues with powering or tertiary timings ~ soo focus on your primaries at the very end staring again with a "weaker" but tested secondary's baseline 


TimeDrapery said:


> View attachment 2485594
> 
> View attachment 2485593
> 
> 
> Anybody see anything I could do better here?


Same thing, tRCDRD 14, go go go 
I can do it with weak A0 PCBs - so you can do too
Before all that, get that GDM away and run 2T , soo your odd i think BZ ? timings patterns make sense. They don't on GDM on


Theo164 said:


> 3800 4x8 b-die @ 1.42v stable no memory errors or whea but can't post / train higher frequencies... any suggestions?


Many dimms generally need increased tWR and added tWRRD delay
Later one you got covered
They also want tRDWR = tRCDavg /2 (+1)
+2 for dual rank , +1 & tWRRD for many dimm single rank

You mask issues with tRC, it's 48 for you but you run +2 there
Get it stable at 48, and if it isn't possible, you have other timeouts in the chain

You run tRRD_L as 8,
Up tWTR as 5-14 instead of 4-14
I think your 1-4-4-1-7-7 is the "masking" issue here
move down to 1-4-4-1-6-6 for many dimms or dual rank scenarios
1-5-5-1-7-7 can work as it's still single rank, but 1-4-4-1-6-6 although slower is a bit better here

Also be sure to binn your dimms individually, and put the weakest set on the main (master) position (slot 2 & 4)
But the better ones to the (slave) set , 1 & 3

tRFC mini works for 8gb dimms, but it looks without checking correct
Be sure to hold tRFC 2 & 4 correctly ~ for whatever tRFC you pick


thismock said:


> @Veii did you have any luck getting 4333mhz / 2167 FCLK to post? I’m rock-stable on 4267/2133, but I can’t get 2167 to post no matter how much power/cad tweaking I do.


Didn't investigate why it didn't work. But the XOC CornerJack got it posted & running on 2167 FCLK 

__ https://twitter.com/i/web/status/1367013800273182726Soo it surely is a possible thing - i just didn't go further than 2133, when 2133 had 8:1 or even 16:1 mode bugging out and autocorrecting up to 210ns 
Will give it another shot or maybe get a better DIMM-PCB and then try again. Am already beyond the limits of these cute A0s


_frame_ said:


> AGESA V2 PI 1.2.0.2 anyone?


In 1 month when ASRock's "single" bios engineer get's it together 


GribblyStick said:


> OK, so if everything goes right, I should be able to start installing my custom loop sometime next week or so. I'll start testing again in earnest then.
> In the mean time, it seems you guys have a better handle on how to configure CPU related settings by now, so I went and got CTR 2.0 RC5 and ran some diagnostics.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> That was the best out of 3, the previous two runs returned it as a silver sample.
> What I changed about CPU settings was to adopt the power regulation settings @Veii suggested. That's it, everything else should still be on auto.


You still have a bit of playroom , and vdroop on LLC - for purely CTR usage


Spoiler: CTR Optimum














You can achieve this by adding negative CO & balancing it with positive vcore
Keep in mind, on the "not so new" versions, adding any vcore offset ~ will bug it out and run 1.55v through it. Soo be sure to test it or don't use any vcore offset at all 
Too big negative CO, will fake the results and cause actual crashes ~ same for too big vcore offset will push too much voltage through the chip ~ as it goes as "additive voltage"

I started with 1072 Silver Sample ~ don't have such a good unit 
Also use the high-perf powerplan for now and disable DF states , if you want to use CTR


lmfodor said:


> I put the RTTs at 7-3-1 (strong) so I should lower the volatge even further? And I also went back to tCKE in 1.


Up to you, if you use strong RTT_PARK, then you should use less VDIMM ~ generally speaking
If you have thermal headroom and get RTTs weaker (which i think still is the better option & worth it fixing the powering)
You can push higher voltage and soo lower timings


shaolin95 said:


> Hello guys!
> 
> I am running 64GB but wondering if you see anything I could try to tweak my RAM more. I have tried 1T with GDM On but I seem to get a bit better performance with 2T and GDM OFF. Still, I am happy to test.
> 
> 
> View attachment 2486313


Update ZenTimings, unsure if these are Dual Rank 4 dimms or 2x 32gb
You want to increase ClkDrvStr higher to 60-120 (for dual rank) or 40-60 for 4x16gb "single rank"
something like 40-20-40-20, 60-20-40-20, or trying out 60-20-20-20 with SETUP Timings of 2-2-12

I think your result is already good, just that tRCDRD 15 is bothering 
Likely want to increase tRRD, tWTR, tWR & tRTP till 14-14-14-14 is stable
Else just lower tRTP to 6, or run a higher tRFC of 294 @ tWR 14, tRTP 7

Really depends, usually you want to run SD, DD's as 1-4-4-1-6-6 for "many dimms or dual rank"
But your result is already good ~ except the high procODT which limits you
Oh you surely want to run cLDO_VDDP to 900mV & lower CPU VDDP (VDDP in tweakers paradise) to 900mV , 880mV or 860mV (up to what your sample allows you)
cLDO_VDDP shouldn't be higher than 900mV 
Maaybe 920-960-1000-1080
SOC is GET, the rest is SET
But i think you are perfectly fine with 900mV cLDO_VDDP

Take a read at








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




and scroll further down
There is a low power set. The voltages should work for you 
but CPU VDDP is what you surely want to lower to the lowest possible ~ under Tweakers Paradise (VDDP)
The rest is cLDO_VDDP for PHY


----------



## chroniclard

Hi all,

I have overclocked my 3200 8Pack Teamgroup memory to the following. This runs at the stock 1.35v, which seems quite good to me.

I briefly tried 3800 but it would not boot, even with bumping voltage a bit, so think will focus on tuning this to the max.

Any tips on what I could potentially tweak further?


----------



## mongoled

Veii said:


> Also be sure to binn your dimms individually, and put the weakest set on the main (master) position (slot 2 & 4)
> But the weaker ones to the (slave) set , 1 & 3


Great post, but please amend this as you say "weakest" twice.


----------



## T[]RK

Veii said:


> SOC is GET, the rest is SET


Is it mean, that i need to "find" correct voltage? Because i tested some vSOC values on my cheap board and founded next:

*Minimum vSOC for selected frequency:*
3600 MHz - <1,060 mV
3800 MHz - <1,075 mV
4000 MHz - <1,138 mV (rounded)

Here is small table: vSOC in BIOS (SET) | vSOC in ZenTimings (SVI2 @ Idle) | vSOC in ZenTimings (SVI2 @Load - TM5)

*For 3600 MHz:*
1,068 mV | 1,062 mV (-6 mV) | 1,056 mV (-12 mV)
1,069 mV | 1,069 mV (0 mV) | 1,062 mV (-6 mV)
1,070 mV | 1,069 mV (-1 mV) | 1,062 mV (-8 mV)

*For 3800 MHz:*
1,081 mV | 1,075 mV (-6 mV) | 1,069 mV (-12 mV)
1,082 mV | 1,081 mV (-1 mV) | 1,075 mV (-6 mV)
1,083 mV | 1,081 mV (-2 mV) | 1,075 mV (-8 mV)

So, it's have "steps" when delta is smaller (0 mV - [email protected]) and bigger (-12 [email protected]). For 3600 MHz i must set not 1,060 mV in BIOS, but 1,069 mV to get 1,062 mV under load. Same with 3800 MHz - not 1,075 mV, but 1,082 mV. Another situation when i try to increase voltage when i need it, but it's actually don't rise, but stay on same spot unless i increase it even more (like 1,082 mV for 3600 MHz). I didn't check same thing for 4000 MHz since i can't (yet) boot with it.


----------



## wuttman

Excuse me, I don't understand people running odd timings at GDM on. Isn't it supposed to adjust it by +1 anyway?


----------



## jcpq

@Veii 
I would like your help.
I am trying to lower the L3 latency, but without success.
Any suggestion?


----------



## SesioN

Any suggestions for further timings / latency improvement?


----------



## wuttman

SesioN said:


> Any suggestions for further timings / latency improvement?


tFAW


----------



## gabian

Hi

I spend time to make this stable. With 2x16GB Gskill 3800C14. I try to tight everything to the minimum.

Is there anything useless in my timings ? (like too tight for being usefull)

On TM5 ram is heating at 49c, Karhu and TM5 are OK, but may be too hot for daily ?


----------



## TimeDrapery

PJVol said:


> Spoiler
> 
> 
> 
> *@TimeDrapery*
> 
> Allow me to answer for him. Probably those settings are Asrock boards related only.



Thanks for the reply!

The settings @Veii is referencing are talked about in some of AMD's EPYC tuning guides found on their public site

I always assumed they're exposed in AMD CBS because of the requirements to make the BIOS settings found in there... Common 😂😂😂😂😂

It would be nice to know what these options actually impact on CPUs that _aren't_ EPYC...

You listening, AMD? If they impact nothing on Ryzen, why expose them? Lazy mobo vendors?


----------



## TimeDrapery

Veii said:


> Spoiler
> 
> 
> 
> Pretty much the same thing i tell everyone
> _Have a stable main set, before starting_
> 
> First focus on weakening RTT_PARK, to something lower
> Soo dimms heat up less / you can then use more voltage to push things / and the PCB has less strain
> Also helps you get procODT a bit lower
> 
> Then after that's done, increase close to everything
> tRRD, tWTR, tWR, tRTP
> and try to get these flat primaries stable
> AFTER you are already done with pushing frequency up ~ with a weaker 16-16-16 set
> 
> It can happen that you need to losen tRFC a bit, as tighter primaries will demand more voltage and so cause more strain
> It's expected that the PCB won't be thaat stable (the main reason you should weaken your powering in the first place to lower heat and strain a bit, before continuing)
> Later you can at any time tighten down tWR, tRTP & tRFC without issues
> But bad primaries will be masked by tens of thousand possible issues with powering or tertiary timings ~ soo focus on your primaries at the very end staring again with a "weaker" but tested secondary's baseline
> 
> Same thing, tRCDRD 14, go go go
> I can do it with weak A0 PCBs - so you can do too
> Before all that, get that GDM away and run 2T , soo your odd i think BZ ? timings patterns make sense. They don't on GDM on
> 
> Many dimms generally need increased tWR and added tWRRD delay
> Later one you got covered
> They also want tRDWR = tRCDavg /2 (+1)
> +2 for dual rank , +1 & tWRRD for many dimm single rank
> 
> You mask issues with tRC, it's 48 for you but you run +2 there
> Get it stable at 48, and if it isn't possible, you have other timeouts in the chain
> 
> You run tRRD_L as 8,
> Up tWTR as 5-14 instead of 4-14
> I think your 1-4-4-1-7-7 is the "masking" issue here
> move down to 1-4-4-1-6-6 for many dimms or dual rank scenarios
> 1-5-5-1-7-7 can work as it's still single rank, but 1-4-4-1-6-6 although slower is a bit better here
> 
> Also be sure to binn your dimms individually, and put the weakest set on the main (master) position (slot 2 & 4)
> But the weaker ones to the (slave) set , 1 & 3
> 
> tRFC mini works for 8gb dimms, but it looks without checking correct
> Be sure to hold tRFC 2 & 4 correctly ~ for whatever tRFC you pick
> 
> Didn't investigate why it didn't work. But the XOC CornerJack got it posted & running on 2167 FCLK
> 
> __ https://twitter.com/i/web/status/1367013800273182726Soo it surely is a possible thing - i just didn't go further than 2133, when 2133 had 8:1 or even 16:1 mode bugging out and autocorrecting up to 210ns
> Will give it another shot or maybe get a better DIMM-PCB and then try again. Am already beyond the limits of these cute A0s
> 
> In 1 month when ASRock's "single" bios engineer get's it together
> 
> You still have a bit of playroom , and vdroop on LLC - for purely CTR usage
> 
> 
> Spoiler: CTR Optimum
> 
> 
> 
> 
> View attachment 2486372
> 
> 
> 
> You can achieve this by adding negative CO & balancing it with positive vcore
> Keep in mind, on the "not so new" versions, adding any vcore offset ~ will bug it out and run 1.55v through it. Soo be sure to test it or don't use any vcore offset at all
> Too big negative CO, will fake the results and cause actual crashes ~ same for too big vcore offset will push too much voltage through the chip ~ as it goes as "additive voltage"
> 
> I started with 1072 Silver Sample ~ don't have such a good unit
> Also use the high-perf powerplan for now and disable DF states , if you want to use CTR
> 
> Up to you, if you use strong RTT_PARK, then you should use less VDIMM ~ generally speaking
> If you have thermal headroom and get RTTs weaker (which i think still is the better option & worth it fixing the powering)
> You can push higher voltage and soo lower timings
> 
> Update ZenTimings, unsure if these are Dual Rank 4 dimms or 2x 32gb
> You want to increase ClkDrvStr higher to 60-120 (for dual rank) or 40-60 for 4x16gb "single rank"
> something like 40-20-40-20, 60-20-40-20, or trying out 60-20-20-20 with SETUP Timings of 2-2-12
> 
> I think your result is already good, just that tRCDRD 15 is bothering
> Likely want to increase tRRD, tWTR, tWR & tRTP till 14-14-14-14 is stable
> Else just lower tRTP to 6, or run a higher tRFC of 294 @ tWR 14, tRTP 7
> 
> Really depends, usually you want to run SD, DD's as 1-4-4-1-6-6 for "many dimms or dual rank"
> But your result is already good ~ except the high procODT which limits you
> Oh you surely want to run cLDO_VDDP to 900mV & lower CPU VDDP (VDDP in tweakers paradise) to 900mV , 880mV or 860mV (up to what your sample allows you)
> cLDO_VDDP shouldn't be higher than 900mV
> Maaybe 920-960-1000-1080
> SOC is GET, the rest is SET
> But i think you are perfectly fine with 900mV cLDO_VDDP
> 
> Take a read at
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> and scroll further down
> There is a low power set. The voltages should work for you
> but CPU VDDP is what you surely want to lower to the lowest possible ~ under Tweakers Paradise (VDDP)
> The rest is cLDO_VDDP for PHY



Thanks for the reply!

I'll set GDM to Disabled and Command Rate to 2T, loosen subs, and do my best to get a flat 14 timing set running stable...

What advantages does 2T offer versus 1T/GDM Enabled? Less autocorrection activity and, thusly, better performance?


----------



## wuttman

Lower\weaker park


Veii said:


> First focus on weakening RTT_PARK, to something lower


Forgive the brainlet, weaker means lower divider or lower value itself?


----------



## mongoled

wuttman said:


> Lower\weaker park
> 
> Forgive the brainlet, weaker means lower divider or lower value itself?


RZQ/1 is "stronger" than RZQ/3

Using a "stronger" RttPark value with vDIMM > 1.48v can lead to dimm death especially if they are A0 pcb's ....

So its preferable to use a weaker RttPark value when adding more vDIMM voltage


----------



## Veii

mongoled said:


> Great post, but please amend this as you say "weakest" twice.


oops, fixed
Thank you~


T[]RK said:


> Is it mean, that i need to "find" correct voltage?


It means, that every board has split SOC Mosfets and so a Loadline for their controller
What is read out under load matters ~ at least matters for the "minimum" rating i tried to push out as overview couple of months ago

Likely a better CPU can do better, but i think it's a decent orientation point
Lower might or might not post, but the written values are one which worked for sure 


jcpq said:


> @Veii
> I would like your help.
> I am trying to lower the L3 latency, but without success.
> Any suggestion?
> View attachment 2486408


Tried EDC 400 ?
And both cTDP and Package power limit to 400W inside AMD CBS - NBIO - SMU ?
Else i am not sure i can help you with finetuning and working with CurveOptimizer
At least not without sitting together and looking over your shoulder. Something around that idea
No really, no idea how to help you ~ except suggest to use a big negative allcore CO and give it near 40-50mV positive vcore

Also disabling DF states and likely downgrading, as SMU 56.50 killed L3 cache performance , in comparison to 56.44 for example.
1.1.9.0 or 1.2.0.0 where "ok" ~ IF you lift the EDC upwards soo internal limits lift
(it still will follow the FUSE EDC limit, just use more allcore voltage, by the broken nature of how PBO functions since Matisse)


SesioN said:


> Any suggestions for further timings / latency improvement?
> 
> View attachment 2486410


tRDWR down at least one, with added tWRRD of at least value 2 or higher
In the future then getting a flat CL14-14-14 set , or a 3800C15-15-15 set for the beginning


TimeDrapery said:


> You listening, AMD? If they impact nothing on Ryzen, why expose them? Lazy mobo vendors?


The exact opposite of your writing ~ is my intention
Brands keep locking them down further and further. We have only 10-12% of what can be set
EPYC == AM4
Same IO-Die , same CCDs

What functions there, functions here
I haven't gotten to unlock this bios, and miss ASRocks old charm of proving an unlocked AMD CBS & PBS
MSI, Gigabytee and Asus users have twice the options i can play with & they do change things
Inter-core things are not easy to track ~ same as Ram Performance -> IPC bump, is not easy


----------



## wuttman

Veii said:


> & lower CPU VDDP (VDDP in tweakers paradise) to 900mV , 880mV or 860mV (up to what your sample allows you)


MSI bios doesn't have it?


----------



## RonLazer

wuttman said:


> MSI bios doesn't have it?


No, even on the Unify-X.


----------



## TimeDrapery

Veii said:


> Spoiler
> 
> 
> 
> ...
> 
> Also disabling DF states and likely downgrading, as SMU 56.50 killed L3 cache performance , in comparison to 56.44 for example.
> 1.1.9.0 or 1.2.0.0 where "ok" ~ IF you lift the EDC upwards soo internal limits lift
> (it still will follow the FUSE EDC limit, just use more allcore voltage, by the broken nature of how PBO functions since Matisse)
> 
> ...
> 
> The exact opposite of your writing ~ is my intention
> Brands keep locking them down further and further. We have only 10-12% of what can be set
> EPYC == AM4
> Same IO-Die , same CCDs
> 
> What functions there, functions here
> I haven't gotten to unlock this bios, and miss ASRocks old charm of proving an unlocked AMD CBS & PBS
> MSI, Gigabytee and Asus users have twice the options i can play with & they do change things
> Inter-core things are not easy to track ~ same as Ram Performance -> IPC bump, is not easy



I believe ya, you are doing great work and I appreciate you!

I figured we're missing quite a bit of options in most publicly available BIOS considering the EPYC and Ryzen similarities... That's very disappointing but it is what it is

Considering the similarities between the CPUs with regards to CBS -> SMU Options one thing I'm wondering is what the cTDP limits are on Ryzen processors

For example, EPYC CPUs have upper and lower limits users can configure their systems within... What would these limits be on Ryzen systems?


----------



## T[]RK

Veii said:


> Likely a better CPU can do better, but i think it's a decent orientation point
> Lower might or might not post, but the written values are one which worked for sure


I tested (just in case) my current config with TM5 (25 cycles) and it pass without errors. But when i decided to test CB20 - i got crash after few seconds.








And first my guess was that not enough CPU voltage at CLDO_VDDP, VDDG CCD\IOD, so i switched from 860-900-940 to 900-940-980. Since RAM was tested and it pass long test without error. New run of CB20 crashed again, a bit later, but still! I tested RTTs 6\0\7 - no effect. I loaded Default XMP profile and no problem - CB20 pass. So, problem was in RAM, not in CPU and i switched back my voltages. Then i load my Tuned XMP profile again and changed EXACT ONE value - ProcODT 34.3 => 36.9 (one step UP). CB20 Pass. So, now all values are correct. Interesting, that i was able to run 3DMark Time Spy at ProcODT 34.3 and no crash. Only CB20 make high enought load for crash.


----------



## Veii

wuttman said:


> MSI bios doesn't have it?
> 
> 
> RonLazer said:
> 
> 
> 
> No, even on the Unify-X.
Click to expand...

They do, all MSI boards have it - it's only hidden from the user
More people need to force the department to "unhide" it inside AMITSE - soo AMIBCP change stticks
or just AMIBCP change it to 900mV - which will 100% work on all CPUs
Lower than 900mV is required for 2100 FCLK stability, but 2100 runs at 900mV too


TimeDrapery said:


> Considering the similarities between the CPUs with regards to CBS -> SMU Options one thing I'm wondering is what the cTDP limits are on Ryzen processors
> For example, EPYC CPUs have upper and lower limits users can configure their systems within... What would these limits be on Ryzen systems?


They should be identical to the PPT limit
I haven't tested if an override there overrides PPT limits ~ like the ECO mode does (Although ECO mode does DPM LCLK slow it down ~ inside infinity fabric)
This thread and discussion with CapFrameX ~ especially this picture

__ https://twitter.com/i/web/status/1347149309779845121Watch the SiSandra Inner-Core link differences and benchmark result differences


T[]RK said:


> I tested (just in case) my current config with TM5 (25 cycles) and it pass without errors. But when i decided to test CB20 - i got crash after few seconds.
> 
> 
> Veii said:
> 
> 
> 
> 
> 3600 - <1060mV
> 3800 - <1075mV
Click to expand...

FCLK , is still inside the CPU
Technically a memory crash can be cpu voltage stability
Not only vcore , but also can be vcore

Rule of thumb was +3 steps on 2700X over the lowest AVX2 stable voltage ~ to cover the higher strain of FCLK OC
Determine minimum working voltages with y-cruncher (Key-Combination: 1-7-0 , looping 4 cycles everything = 48min)
Cinebench is a lightweight load in comparison to all AVX2 tests y-cruncher has
OCCT AVX2 Extreme, only ticks the box of "extended linpack test under large dataset ~ making internal heat destabilize voltage splitting of VDDG" == crash or stability issues
Before all that, y-cruncher will tell you with all 9 tests enabled, if anything major is broken to begin with 

This also includes CTR "predicted" voltages, which fully break once AVX2 adds own voltage offset ontop of loadline offset
But CTR has something newly interesting soon after 2.1 RC5 or likely "freeby RC6" ~ to combat such
(pushing you to my 5ghz allcore TM5 screeny ~ reposted here)









High SOC will require high procODT
There are minimum and maximum limits with it
High proc allows usage of "less SOC and less VDIMM" but low voltages only work with "low" procODT
Bit of a paradox


----------



## shaolin95

Veii said:


> Really depends, usually you want to run SD, DD's as 1-4-4-1-6-6 for "many dimms or dual rank"
> But your result is already good ~ except the high procODT which limits you
> Oh you surely want to run cLDO_VDDP to 900mV & lower CPU VDDP (VDDP in tweakers paradise) to 900mV , 880mV or 860mV (up to what your sample allows you)
> cLDO_VDDP shouldn't be higher than 900mV
> Maaybe 920-960-1000-1080
> SOC is GET, the rest is SET
> But i think you are perfectly fine with 900mV cLDO_VDDP
> 
> Take a read at
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> and scroll further down
> There is a low power set. The voltages should work for you
> but CPU VDDP is what you surely want to lower to the lowest possible ~ under Tweakers Paradise (VDDP)
> The rest is cLDO_VDDP for PHY


First of all THANK YOU for the detailed explanation. Really appreciated 
I tried dropping procODT a little but I get reboots even doing the AIDA mem test.
Same thing if I try to do 1-4-4-1-6-6
I am not very clear on the voltages recommendations so I took a photo to share with you of my current settings. And also the newer version of Zen Timings


----------



## RonLazer

Veii said:


> They do, all MSI boards have it - it's only hidden from the user
> More people need to force the department to "unhide" it inside AMITSE - soo AMIBCP change stticks
> or just AMIBCP change it to 900mV - which will 100% work on all CPUs
> Lower than 900mV is required for 2100 FCLK stability, but 2100 runs at 900mV too


Can I just edit that value in AMIBCP and save the BIOS file again and it will work? Do you have any guides on this?


----------



## SesioN

wuttman said:


> tFAW


But isn't the rule for tFAW as follow:

tFAW (tRRDS *4 <= best value <= tRRDS *6

If that's the case, then my tFAW is already maxed out?



Veii said:


> tRDWR down at least one, with added tWRRD of at least value 2 or higher
> In the future then getting a flat CL14-14-14 set , or a 3800C15-15-15 set for the beginning


Okay thank you, I will see how the RDWR and WRRD changes affect stability and results. I'll let you know.

I don't think that hitting 14-14-14 is possible. As soon as I change tRCDRD to 14 I start getting errors on testing. 
So unless it's possible and worth to relax some others settings that might help with this I can't do it.

(And my memory is quite hot, I'm like 52-53C at full load and that's at 1.48V)


----------



## GribblyStick

@Veii

Ok, let me get this straight:
In terms of CPU we should try the power settings you shared earlier, plus:

Uncore OC off (don' remember where. In Advanced/AMD CBS/?)

Advanced/AMD CBS/NBIO Common Options/SMU Commen Options
DF C-States off disabled
cTDP Control -> 400
Package Power Limit -> 400
APBDIS disabled
CCLK DPM = 0 (Efficiency mode En 0 is performance optimization)
NBIO DPM options are there but no idea what to set.

Advanced/AMD CBS/CPU Common Options
global C-States enabled

Advanced/AMD Overclocking/Precision Boost Overdrive
PBO limits manual or motherboard limit?
if manual EPC 400, TDC90, PPT also 400?
There is also the fmax enhancer option in the extreme tweaker menu, not clear to me whether that should be on or off.
Max boost set to 200, seems better to lower all core negative offset than to lower the max boost?

Then for CO is this about right?
-30 all core would be considered very good
-15 good
-5 to 10 would be more realistic

offset on the main menu then +0,03 or lower to match the negative CO?
And then run TM5 to confirm the effective and target clock are identical.
And check y-cruncher/cinebench/CTR/games/etc for stability.
Then CPU VDDP in Tweaker menu as low as possible( to test via benchmarking)

Also, do you have on estimation on safe relations for RTT_PARK/ProcODT/VDIMM/CAD resistances yet?
IIRC you went all the way up to 1,7. So Past VDIMM 1,5 you want at least RTT_PARK/3?
For 1,7 I would then guess you need at least RTT_PARK/6 or even 7.
I guess it's not that simple because I am pretty sure I already had 1,5 with RTT_PARK even OFF.
Also depends on the particular PCB. I understand you want weaker RTTs to go higher in VDIMM in order to get a higher IC.
It's not so clear to me where to draw the line in actual numbers.


----------



## Ramad

RonLazer said:


> Can I just edit that value in AMIBCP and save the BIOS file again and it will work? Do you have any guides on this?


CPU VDDP on MSI motherboards can't be controlled by the user. If you mod the BIOS to show the option, the motherboard does not understand or display the value correctly. There is also no read/probe for this voltage rail under Hardware Monitor. The default value is 900mV or 950mV which works fine for ZEN+ and up, it was useful to set this voltage down to 855mV on ZEN (first Ryzen) in the beginning but had no effect on later AGESA releases (that is back in 2017/2018).


----------



## SesioN

shaolin95 said:


> View attachment 2486455


Isn't tRFC suppose to be X times of tRC? so either 252 or 294 for you.


----------



## SesioN

Veii said:


> tRDWR down at least one, with added tWRRD of at least value 2 or higher
> In the future then getting a flat CL14-14-14 set , or a 3800C15-15-15 set for the beginning


So I tried lowering tRDWR by 1 while increasing tWRRD by 2 or even 4. Sadly that resulted in a no boot situation where a CMOS clear was needed.


----------



## craxton

@Veii apologies to tag as i literally see your swamped with tags/questions daily, 

but i tried 2033fclk 1:1 mode, and well..















anyhow, my Question is "does this look correct"? no errors from any tests at all. 
but, around two months ago something was mentioned that i have some error correction happening somewhere,
while i was away from my pc (around 9 days away from it) and i cant find this post. ill wait for your response.

just let me know IF you dont mind to look over this. (yes best score ive gotten, C/O -15 with +60mv offset) 
pc will crash or do random things while anything less than 60mv, core voltage in hwinfo never goes over 1.41.


----------



## kratosatlante

SesioN said:


> Any suggestions for further timings / latency improvement?
> 
> View attachment 2486410


try this 1.57-1.58v









or this 1.56v


----------



## mongoled

kratosatlante said:


> try this 1.57-1.58v
> 
> 
> 
> 
> 
> 
> 
> 
> 
> or this 1.56v


You are loosing 300-400mb in memory read throughput by using tRDRDSCL/tRWRWSCL at 2 and for no reason other than being fixated on smaller values.

Increase tRDRDSCL/tRWRWSCL to 4 or 5 and compare the read bandwidth to 2 or 3 and you will see what I am talking about.

Your read throughput should be close to 57000 MB/s with those setting not 56000 MB/s !


----------



## kratosatlante

mongoled said:


> You are loosing 300-400mb in memory read throughput by using tRDRDSCL/tRWRWSCL at 2 and for no reason other than being fixated on smaller values.
> 
> Increase tRDRDSCL/tRWRWSCL to 4 or 5 and compare the read bandwidth to 2 or 3 and you will see what I am talking about.
> 
> Your read throughput should be close to 57000 MB/s with those setting not 56000 MB/s !


you are right , thanks


















last version aida


----------



## mongoled

kratosatlante said:


> you are right , thanks
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> last version aida


tRDRDSCL/tWRWRSCL of 2/3 are good for 16GB though when moving to 32GB we need to raise these values.

I have seen Veii is investgating the relationship of SCLs with other factors


----------



## lmfodor

I found two colleagues we share the same memory kit @gabian @SesioN and I think we can work together to find the best result as all share the same SMU and even with one the same Mobo. @mongoled @Veii can you help us with some tips?

This are my actual timings 








@SesioN This are your timings. I wonder how you enabled 1T GDM off. I tried several times but I’ve got BSOD








@gabian these are yours. I see you have 1T+GDM on








And this my AIDA64 results that I considered very good. What do you thing about results?


Spoiler














This is my high level analysis comparing the all the timings 

At first sight I see all of us use the same latest BIOS/AGESA
1. tRCDRD I’m more conservative with the tRCDRD in 16. I know as per Igor’s review this will impact in a higher temps. However as I have an active cooling I should try to flat the primaries instead of use tRCDRD/2 to set the tRCDWR
2. My tRAS is the lower set in 24, and I even tried 22
3. My tRRD and tWRD are set more looser to get more read write performance 
4. My TWR is higher, they set it to 12 and I 14
5. My tRFC2 is wrong. Should be lower 
6. For me my SCL’s set them to 4 are fine and also the tCWL at 14
7. My tRP and TRDWR are tight, I know there is a rule to set then. I don’t know if I should rise them to 10
8. My Sd/Dd seems to be fine at 1-4-4-1-6-6 for a dual rank 
9. All we share the same tCKE to 1
10. My VSOC is the higher in 1.14 but my VDDP is the lowest at 0.9 which for me seems to be fine, also de CCD 0.95 and IOD 1.05
11. My prodOTC is the the lowest and I wondering if I should set back to 40 instead of 36. I know there’s a relation with VDIMM, I indeed I have a high VDIMM starting at 1.5 and I’d will rise if I need to lower primaries 
12. My RTT with Park set as 3 is weaker to support a higher VDIMM. Previous to this 7-3-3 I was tried 5-2-4, very weaker with the objetive of lowering primaries 
13. And CADBUD I guess I should set to 60-20-20-20 or similar 


Sent from my iPhone using Tapatalk Pro


----------



## mongoled

lmfodor said:


> I found two colleagues we share the same memory kit (@kratosatlante @SesioN) and I think we can work together to find the best result as all share the same SMU and even with one the same Mobo. @mongoled @Veii can you help us with some tips?
> 
> This are my actual timings
> 
> 
> 
> 
> 
> 
> 
> 
> @SesioN This are your timings. I wonder how you enabled 1T GDM off. I tried several times but I’ve got BSOD
> 
> 
> 
> 
> 
> 
> 
> 
> @kratosatlante these are yours. I see you have 1T+GDM on
> 
> 
> 
> 
> 
> 
> 
> 
> And this my AIDA64 results that I considered very good. What do you thing about results?
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This is my high level analysis comparing the all the timings
> 
> At first sight I see all of us use the same latest BIOS/AGESA
> 1. tRCDRD I’m more conservative with the tRCDRD in 16. I know as per Igor’s review this will impact in a higher temps. However as I have an active cooling I should try to flat the primaries instead of use tRCDRD/2 to set the tRCDWR
> 2. My tRAS is the lower set in 24, and I even tried 22
> 3. My tRRD and tWRD are set more looser to get more read write performance
> 4. My TWR is higher, they set it to 12 and I 14
> 5. My tRFC2 is wrong. Should be lower
> 6. For me my SCL’s set them to 4 are fine and also the tCWL at 14
> 7. My tRP and TRDWR are tight, I know there is a rule to set then. I don’t know if I should rise them to 10
> 8. My Sd/Dd seems to be fine at 1-4-4-1-6-6 for a dual rank
> 9. All we share the same tCKE to 1
> 10. My VSOC is the higher in 1.14 but my VDDP is the lowest at 0.9 which for me seems to be fine, also de CCD 0.95 and IOD 1.05
> 11. My prodOTC is the the lowest and I wondering if I should set back to 40 instead of 36. I know there’s a relation with VDIMM, I indeed I have a high VDIMM starting at 1.5 and I’d will rise if I need to lower primaries
> 12. My RTT with Park set as 3 is weaker to support a higher VDIMM. Previous to this 7-3-3 I was tried 5-2-4, very weaker with the objetive of lowering primaries
> 13. And CADBUD I guess I should set to 60-20-20-20 or similar
> 
> 
> Sent from my iPhone using Tapatalk Pro


There comes a time where the knowledge others have shared with you and guided you (in this case Veii) should be learned from so that you are in a position to make your own decisions! 

Veii, to this forums credit has guided you (and many many others) by the hand, step by step, does there not come a point where you are able to make your own decisions? 

You have most of the knowledge required to make your own decisions, so start to expirement and play with your hardware to learn what it likes and does not like so that you will be in a position to help others. 

And I have not understood what else you are wanting for your hardware? Is it just you need more epeen? Looking for the "perfect" result or are you participating in competive benchmarking? 

As from what you currently have is already in the top 10% of "best" results.


----------



## lmfodor

mongoled said:


> There comes a time where the knowledge others have shared with you and guided you (in this case Veii) should be learned from so that you are in a position to make your own decisions!
> 
> Veii, to this forums credit has guided you (and many many others) by the hand, step by step, does there not come a point where you are able to make your own decisions?
> 
> You have most of the knowledge required to make your own decisions, so start to expirement and play with your hardware to learn what it likes and does not like so that you will be in a position to help others.
> 
> And I have not understood what else you are wanting for your hardware? Is it just you need more epeen? Looking for the "perfect" result or are you participating in competive benchmarking?
> 
> As from what you currently have is already in the top 10% of "best" results.


Hi @mongoled, Not at all. In fact, I consider myself a newbie that I dedicate many nights to and I plan to do it more because I’m a passionate about the subject and I learned a lot from the help of @Veii's, really. However, there are parts that I still don't understand because we just don't follow many rules and there are relationships between the values that, no matter how much I read, it is still hard for me to understand. In fact I want to keep improving to learn and to improve the return on investment. I do not intend a competition at all, but to achieve a good balance, which I think I have achieved and I am very grateful with @Veii and @RosaPanteren who by PM helped me a lot, day by day, step by step with each configuration. But I would like to understand for example why the 1T is limiting me and then for example I encouraged him to copy the values of Veii but I had several problems. It is a lack of knowledge to fix it but I am very grateful to all who helped me, I confess that it cost me to follow Veii que that go to fast! but it allowed me to read and learn. So I hope you get it right. I thought that since we have the same new kit, and at least for me it is quite expensive and I’d like to reach the best performance, without going to an extreme OC as I saw in techpowerup with a user carrying 1.7V and incredible performance. And my goal is to be able to return this great help that OCN has given me to other users, from the assembly of a PBO2 curve until tomorrow to be able to help many in memory OC, which whenever I try it cost me and little by little I am managing to understand the concepts

I hope Do not get it wrong! 

Here’s for instance my intent to copy the @Veii values, in two stage, but with errors
My first attempt copying primaries and values until tRFC 








And then a full copy of value. I rise the voltage but it doesn’t seems stable









Sent from my iPhone using Tapatalk Pro


----------



## mongoled

lmfodor said:


> Hi @mongoled, Not at all. In fact, I consider myself a newbie that I dedicate many nights to and I plan to do it more because I’m a passionate about the subject and I learned a lot from the help of @Veii's, really. However, there are parts that I still don't understand because we just don't follow many rules and there are relationships between the values that, no matter how much I read, it is still hard for me to understand. In fact I want to keep improving to learn and to improve the return on investment. I do not intend a competition at all, but to achieve a good balance, which I think I have achieved and I am very grateful. But I would like to understand for example why the 1T is limiting me and then for example I encouraged him to copy the values of Veii but I had several problems. It is a lack of knowledge to fix it but I am very grateful to all who helped me, I confess that it cost me to follow Veii que that go to fast! but it allowed me to read and learn. So I hope you get it right. I thought that since we have the same new kit, and at least for me it is quite expensive to reach the best performance, without going to an extreme OC as I saw in techpowerup with a user carrying 1.7V and incredible performance. I hope Do not get it wrong!
> 
> Here’s for instance my intent to copy the @Veii values, in two stage, but with errors
> My first attempt copying primaries and values until tRFC
> 
> 
> 
> 
> 
> 
> 
> 
> And then a full copy of value. I rise the voltage but it doesn’t seems stable
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sent from my iPhone using Tapatalk Pro


Regards 1T 32GB,

In the time that you have been participating in this forum did you see anybody running 1T with GDM disabled using 32GB of RAM while pushing 3800/1900 and be TM5 (along with other stress tests) stable ???

Myself personally have not, this should tell you something.

Wanting to know the reasons why, well there is not one answer, actually there is no "clear and definitive" answer other than its the limits of what is possible with the hardware we are using.

Now it would bring me great happiness that someone who is new to memory overclocking provides a "solution" for this, but this can only happen if those new to this are able to think for themselves and maybe see something that all us other people have not seen in all this time.

The only time I had some sucess with 32GB 1T and GDM disabled was when I followed Veii advice and paired a good set of A2s with a good set of A0s, but unfortunately at that time we did not know that RttPark running at RZQ/1 had the capacity to kill the A0s dimms.

So I learned the hard way, as well as others, that while we learn, we also have to experiment and find issues in so that others dont destroy things by accident because we already did it

😂😂😂

To wrap up, all the answer you seek have been repeated over and over in these forums, a little time spent reading and searching will lead you to these answers, but as is with most people, the first thing is to want to not spend time looking but to seek answers afresh, something along the lines of the parabole of the Horse & Cart where Veii is the "God" and the cartman is those people who are @Veii @Veii @Veii

 

I laugh, but cant help worry for the health of Veii as the demands of the cartmen is many and he is only one person (actually he may be a machine but he does not know it 😂)


----------



## lmfodor

mongoled said:


> Regards 1T 32GB,
> 
> In the time that you have been participating in this forum did you see anybody running 1T with GDM disabled using 32GB of RAM while pushing 3800/1900 and be TM5 (along with other stress tests) stable ???
> 
> Myself personally have not, this should tell you something.


Well, although I searched and read in various forums, I also looked for this type of memory and beyond the review of Igor's Lab where he enables it, I found a Techpowerup user (which I cannot attest to is stable), but yes for Example here @SesioN I see that it has it enabled with GDM off. But hey, it's not an obsession, if it's difficult, I get it. So I don’t wanna be clearing CMOS every day!  



mongoled said:


> Regards 1T 32GB,
> Now it would bring me great happiness that someone who is new to memory overclocking provides a "solution" for this, but this can only happen if those new to this are able to think for themselves and maybe see something that all us other people have not seen in all this time.
> 
> The only time I had some sucess with 32GB 1T and GDM disabled was when I followed Veii advice and paired a good set of A2s with a good set of A0s, but unfortunately at that time we did not know that RttPark running at RZQ/1 had the capacity to kill the A0s dimms.
> 
> So I learned the hard way, as well as others, that while we learn, we also have to experiment and find issues in so that others dont destroy things by accident because we already did it
> 
> 
> 
> To wrap up, all the answer you seek have been repeated over and over in these forums, a little time spent reading and searching will lead you to these answers, but as is with most people, the first thing is to want to not spend time looking but to seek answers afresh, something along the lines of the parabole of the Horse & Cart where Veii is the "God" and the cartman is those people who are @Veii @Veii @Veii
> 
> 
> 
> I laugh, but cant help worry for the health of Veii as the demands of the cartmen is many and he is only one person (actually he may be a machine but he does not know it )


Thanks for the sense or humor and yes, @Veii is the "God", I really don't know how he can do it, handling a lot of questions in parallel and hitting the right spot. I read many users grateful for the help of this thread, but not only for fixing their timing, but also for giving this help back to others to improve their systems.


Sent from my iPhone using Tapatalk Pro


----------



## SesioN

lmfodor said:


> I found two colleagues we share the same memory kit @gabian @SesioN and I think we can work together to find the best result as all share the same SMU and even with one the same Mobo. @mongoled @Veii can you help us with some tips?


@SesioN This are your timings. I wonder how you enabled 1T GDM off. I tried several times but I’ve got BSOD
Here I can recommend trying 60 ClkDrvStr, for me that brings stability in general. But I can't do it at 3800 anyways unless I put higher timings into play.


At first sight I see all of us use the same latest BIOS/AGESA
1. tRCDRD I’m more conservative with the tRCDRD in 16. I know as per Igor’s review this will impact in a higher temps. However as I have an active cooling I should try to flat the primaries instead of use tRCDRD/2 to set the tRCDWR
With my current settings I can't go under tRCDRD 15. I haven't tried setting tRCDWR any lower than 8 yet.

2. My tRAS is the lower set in 24, and I even tried 22
I believe that I have tried going lower than 26 but that resulted in errors. At least without adjusting voltage or other timings.

3. My tRRD and tWRD are set more looser to get more read write performance
What is your AIDA score? Also I'm running only 3733 instead of 3800 for stability reasons.

6. For me my SCL’s set them to 4 are fine and also the tCWL at 14
My SCLs are not stable at lower than 5.

7. My tRP and TRDWR are tight, I know there is a rule to set then. I don’t know if I should rise them to 10
The only reason my TRDWR is set to 10, is because I can't boot with lower.

9. All we share the same tCKE to 1
For me this is AUTO setting. I don't know if adjusting this would help as my knowledge is not good enough.

10. My VSOC is the higher in 1.14 but my VDDP is the lowest at 0.9 which for me seems to be fine, also de CCD 0.95 and IOD 1.05
I am still experimenting with how LOW my voltage can go without loosing stability. I want to keep all voltage as low as possible with good results.

11. My prodOTC is the the lowest and I wondering if I should set back to 40 instead of 36. I know there’s a relation with VDIMM, I indeed I have a high VDIMM starting at 1.5 and I’d will rise if I need to lower primaries
I am unstable under 48 with my current settings.


Here is my current AIDA:


----------



## Ramad

@lmfodor 

The timings you are using are not balanced. Minimum tFAW must not be set lower than 16CK, tRC is tRP + tRAS and should be 45CK according to the timings you are using. tRRD and tWTR are not correct either, you can use tRRDS (4CK) tRRDL (7CK) and tWTRS (3CK) and tWTRL (9CK), I have picked those values according to the primary timings you are using. 

If the RAM is operate correctly, then it needs timings that it can understand.


----------



## SesioN

Ramad said:


> @lmfodor
> 
> The timings you are using are not balanced. Minimum tFAW must not be set lower than 16CK, tRC is tRP + tRAS and should be 45CK according to the timings you are using. tRRD and tWTR are not correct either, you can use tRRDS (4CK) tRRDL (7CK) and tWTRS (3CK) and tWTRL (9CK), I have picked those values according to the primary timings you are using.
> 
> If the RAM is operate correctly, then it needs timings that it can understand.


@Ramad Anything incorrect here?


----------



## lmfodor

Ramad said:


> @lmfodor
> 
> The timings you are using are not balanced. Minimum tFAW must not be set lower than 16CK, tRC is tRP + tRAS and should be 45CK according to the timings you are using. tRRD and tWTR are not correct either, you can use tRRDS (4CK) tRRDL (7CK) and tWTRS (3CK) and tWTRL (9CK), I have picked those values according to the primary timings you are using.
> 
> If the RAM is operate correctly, then it needs timings that it can understand.


Hi @Ramad, so tFAW should be fine as it set to 16, right? tRC is 38 that is the sum of tRP +tRS (14+24). So far it seems to be fine right? The thing is the tRRDS and L, I had set to 6 and then I decide to match @Veii values to loose a bit the values and improve performance. And also I read that tRRDL should be rRRDS +2 as a rule. DRAM calculator recommends 3/8
Regarding twTRS and L I also follow Veii and DRAM calculator that recommends 5 14. Do you see it unbalanced? What is the value that influence in tRRDS to be 4, and why tRRDL is not 6? Thanks for your help!



Sent from my iPhone using Tapatalk Pro


----------



## zGunBLADEz

jomama22 said:


> You said you tried disabling c states and df states and turning idle current to 'typical' from auto or low. The only other thing I could suggest is either running a core offset voltage in addition to a fixed voltage to pull up idle voltages slightly (not sure this is possible tbh, havnt looked, I believe it was on my msi board). Could try raising llc higher then normal as well.
> 
> Either that or try a ridiculous oc like 4.5 @ 1.35v get (set depending on your llc) to fully make sure the cpu is stable at all times during the manual oc.


i did all that. its not that.. its exactly what i mention... it only happens on static overclocks on new bios with the l3 cache fix. remember you using a old bios which have the cap on the l cache so you never going to notice this not even using static overclocks i can confirm this myself with the first 2 bioses 0 crashes on static overclock as L3 reads dont get as high. performance wise like you said apart from the weird numbers you get in aida its rock solid and its there.. BUT, i cant do 3800 ram or 1900 fclk and also have usb issues... can do 49x/47x on the old bios too tho lol like its a trade im not willing to do..

*i think i found my problem* the auto crap on ppw/edc/tdc wasnt cutting it.... i only had [email protected] on it.. the other ones on auto values given on edc/tdc i guess wasnt enough which shouldn't be an issue to be honest but now im bombarding it. i put it by motherboard instead for now while i keep testing it.. Lets see. *Nope*, still doing it :/


----------



## Ramad

SesioN said:


> @Ramad Anything incorrect here?
> 
> View attachment 2486529


The RAM does not care if tRCDWR is set to 8, it will run this timing at tRCDRD, so 15CK here. tRP should equal tRCD, so 15CK and tRAS is going to be 15CK+15CK = 30CK.
New tRC would be (tRP+tRAS) 15CK+30CK= 45CK. I'm talking minimums here. I would set tRAS to 30CK+2CK and tRC to 45CK+2CK for stability. These timings would still be tight for a RAM at 3733MT/s even if they seem higher and the RAM would be happy with them.

If I calculate subtimings for 3733MT/s, I would use subtimings for a 2133MT/s, 2400MT/s or 2666MT/s to preserve the relationship between these delays.



Spoiler: 2133MT/s

















Spoiler: 2400MT/s

















Spoiler: 2666MT/s















I would tune the primeries and use the subtimings (always round up).

Getting the IMC timings is by using 3733MT/s in my calculator. There is room for tuning here too, because memory controllers differs greatly, but I consider this a safe start.



Spoiler: IMC_3733MT/s















I hope this helps a little. 

Edit: Use values for 1KB.

@lmfodor
I hope that you can use the screenshots above to use the right values.


----------



## lmfodor

SesioN said:


> @SesioN This are your timings. I wonder how you enabled 1T GDM off. I tried several times but I’ve got BSOD
> Here I can recommend trying 60 ClkDrvStr, for me that brings stability in general. But I can't do it at 3800 anyways unless I put higher timings into play.
> 
> 
> At first sight I see all of us use the same latest BIOS/AGESA
> 1. tRCDRD I’m more conservative with the tRCDRD in 16. I know as per Igor’s review this will impact in a higher temps. However as I have an active cooling I should try to flat the primaries instead of use tRCDRD/2 to set the tRCDWR
> With my current settings I can't go under tRCDRD 15. I haven't tried setting tRCDWR any lower than 8 yet.
> 
> 2. My tRAS is the lower set in 24, and I even tried 22
> I believe that I have tried going lower than 26 but that resulted in errors. At least without adjusting voltage or other timings.
> 
> 3. My tRRD and tWRD are set more looser to get more read write performance
> What is your AIDA score? Also I'm running only 3733 instead of 3800 for stability reasons.
> 
> 6. For me my SCL’s set them to 4 are fine and also the tCWL at 14
> My SCLs are not stable at lower than 5.
> 
> 7. My tRP and TRDWR are tight, I know there is a rule to set then. I don’t know if I should rise them to 10
> The only reason my TRDWR is set to 10, is because I can't boot with lower.
> 
> 9. All we share the same tCKE to 1
> For me this is AUTO setting. I don't know if adjusting this would help as my knowledge is not good enough.
> 
> 10. My VSOC is the higher in 1.14 but my VDDP is the lowest at 0.9 which for me seems to be fine, also de CCD 0.95 and IOD 1.05
> I am still experimenting with how LOW my voltage can go without loosing stability. I want to keep all voltage as low as possible with good results.
> 
> 11. My prodOTC is the the lowest and I wondering if I should set back to 40 instead of 36. I know there’s a relation with VDIMM, I indeed I have a high VDIMM starting at 1.5 and I’d will rise if I need to lower primaries
> I am unstable under 48 with my current settings.


Hi! Have you tried your XMP profile? It let to manage 3800/1900 easily. Did you try it?
This is my Aida score 








Maybe you are not getting 1900 IF because the voltage. This memory’s comes with an standard XMP profile with a a base voltage of 1.5V and I see you are running below or it 
You could also lower your VDDP to 0.9, rise your VSOC to 1.14, set your CCD 0.95 and IOD to 1.05 and try if you get 3800/1900
And maybe you should disable 1T GDM off to 2T GDM off. It seems that is hard to get in 2x16GB DR..
I think that what is producing instability could be your voltage for this memories that comes standard at 1.5V. Maybe it can be lowered but I don’t know how impact on timings 

Sent from my iPhone using Tapatalk Pro


----------



## devoker

hsn said:


> Zen timings got error "failed to read AMD ACPI,,some parameter will be empty"
> 
> is this bug software or what?


Could you solve this AMD ACPI error? After updating the bios I started getting the same error (Asrock b450 itx 4.40 bios agesa 1.2.0.0).


----------



## SesioN

lmfodor said:


> Hi! Have you tried your XMP profile? It let to manage 3800/1900 easily. Did you try it?
> This is my Aida score
> 
> 
> 
> 
> 
> 
> 
> 
> Maybe you are not getting 1900 IF because the voltage. This memory’s comes with an standard XMP profile with a a base voltage of 1.5V and I see you are running below or it
> You could also lower your VDDP to 0.9, rise your VSOC to 1.14, set your CCD 0.95 and IOD to 1.05 and try if you get 3800/1900
> And maybe you should disable 1T GDM off to 2T GDM off. It seems that is hard to get in 2x16GB DR..
> I think that what is producing instability could be your voltage for this memories that comes standard at 1.5V. Maybe it can be lowered but I don’t know how impact on timings
> 
> Sent from my iPhone using Tapatalk Pro


Sadly my setup doesn't work well with infinity fabric at 1900.
That leads to instant reboots on boot start. No matter what voltage I supply to VDDP, VSOV, CCD and IOD..

1933 or 1966 doesn't reboot but leads to "instant" WHEA errors while OCCT.

That's why I'm trying to get max out of 3733 by tuning all the timings. Like compared to your score with 3800, I'm not that far off, which is great.

I like to game at 1440p and in Warzone good memory timings bring 20-30 FPS!


----------



## thismock

@Veii: Thank you for taking time to provide additional information and corrections for my Rev E mini-guide posting a few pages back. I added your notes in-line [[bracketed like this]] to make that post a more complete and accurate reference. Let me know if you’re not OK with this; I can reverse the edits.

@PJVol and @Veii: I think both of you run Asrock B550 motherboards for high-end memory overclocking. Are you happy with your boards and would you recommend them? 

I’m considering replacing my Asrock B450 ITX, which has been good to me, but has some pretty serious overclocking limitations (max 1.5 vdimm, 50mv vdimm steps, 35mv vsoc steps, no CPU VDDP, etc). I’m certain that I’m blocked from further progress by my motherboard. The Asrock B550 Phantom Gaming ITX is probably the best fit for me, as long as you’ve had positive experiences with Asrock’s B550 BIOS (understanding that they’re slower to provide new BIOSes with AGESA updates). It also helps that it ~seems~ the Asrock boards have the fewest problems with WHEAs at high FCLKs. Otherwise I’m looking at the Asus Crosshair VIII Impact or B550i Strix.

On a related note, it’s a real pain to find which motherboards and their BIOSes provide access to which tuning settings (example: CPU VDDP), let alone their min-max values and steps. I’ve found that most motherboard manuals do not provide a complete list of BIOS options, so I have to use screenshots from hardware reviews.. which can be out-of-date or incomplete. Maybe there’s a resource out there that already has this info — if anyone knows of one, please let me know!


----------



## wmunn

Any suggestions on how to get this stable at 3800 ?
I am good at 3733 but fails at 3800
I can pass mem test with these settings running 1867 MCLK, FCLK and UCLK
memory is 

Module Manufacturer:G.SkillModule Part Number:F4-3600C16-16GTZNCModule Series:Trident Z NeoDRAM Manufacturer:HynixDRAM Components:H5AN8G8N[C/D]JR-TFC


----------



## Oversemper

Hello, Everybody! I'd appreciate if somebody can help me in the following situation.
I had Ryzen 3800x (Asus x570-f) with a nice RAM overclock from 3200 to 3733, FSBIF 1866 (BLS2K16G4D32AESE 3733 16-19-16-36 1T 1.35v). It was with Radeon vii (pci 3.0). Today I changed it to radeon 6900xt and my PC did not post. Bios reset and it posted alright. So, I tried to overclock ram again and I cannot increase FSBIF higher than 1633. FSBIF 1666 does not post for me even with SOC voltage at 1.2. I've updated bios to the last stable (agesa 1.2.0.1)

Does it mean that FSBIF 1633 is the maximum frequency at which my 3800x can work with a PCI 4.0 card? Or may be there some options to tweak? Obviously, I'm not going to lower PCI to 3.0 over that.


----------



## Hale59

On the superpi 32m amd zen low clock challenge, I'm the top ryzen 3000s with this little road runner. Just 2 seconds behind a 5800X.


----------



## RonLazer

Ramad said:


> The RAM does not care if tRCDWR is set to 8, it will run this timing at tRCDRD, so 15CK here. tRP should equal tRCD, so 15CK and tRAS is going to be 15CK+15CK = 30CK.
> New tRC would be (tRP+tRAS) 15CK+30CK= 45CK. I'm talking minimums here. I would set tRAS to 30CK+2CK and tRC to 45CK+2CK for stability. These timings would still be tight for a RAM at 3733MT/s even if they seem higher and the RAM would be happy with them.
> 
> If I calculate subtimings for 3733MT/s, I would use subtimings for a 2133MT/s, 2400MT/s or 2666MT/s to preserve the relationship between these delays.
> 
> 
> 
> Spoiler: 2133MT/s
> 
> 
> 
> 
> View attachment 2486531
> 
> 
> 
> 
> 
> 
> Spoiler: 2400MT/s
> 
> 
> 
> 
> View attachment 2486532
> 
> 
> 
> 
> 
> 
> Spoiler: 2666MT/s
> 
> 
> 
> 
> View attachment 2486533
> 
> 
> 
> 
> I would tune the primeries and use the subtimings (always round up).
> 
> Getting the IMC timings is by using 3733MT/s in my calculator. There is room for tuning here too, because memory controllers differs greatly, but I consider this a safe start.
> 
> 
> 
> Spoiler: IMC_3733MT/s
> 
> 
> 
> 
> View attachment 2486534
> 
> 
> 
> 
> I hope this helps a little.
> 
> Edit: Use values for 1KB.
> 
> @lmfodor
> I hope that you can use the screenshots above to use the right values.


Can you post a copy of this spreadsheet for people to have a go with?


----------



## lmfodor

Ramad said:


> The RAM does not care if tRCDWR is set to 8, it will run this timing at tRCDRD, so 15CK here. tRP should equal tRCD, so 15CK and tRAS is going to be 15CK+15CK = 30CK.
> New tRC would be (tRP+tRAS) 15CK+30CK= 45CK. I'm talking minimums here. I would set tRAS to 30CK+2CK and tRC to 45CK+2CK for stability. These timings would still be tight for a RAM at 3733MT/s even if they seem higher and the RAM would be happy with them.
> 
> If I calculate subtimings for 3733MT/s, I would use subtimings for a 2133MT/s, 2400MT/s or 2666MT/s to preserve the relationship between these delays.
> 
> 
> 
> Spoiler: 2133MT/s
> 
> 
> 
> 
> View attachment 2486531
> 
> 
> 
> 
> 
> 
> Spoiler: 2400MT/s
> 
> 
> 
> 
> View attachment 2486532
> 
> 
> 
> 
> 
> 
> Spoiler: 2666MT/s
> 
> 
> 
> 
> View attachment 2486533
> 
> 
> 
> 
> I would tune the primeries and use the subtimings (always round up).
> 
> Getting the IMC timings is by using 3733MT/s in my calculator. There is room for tuning here too, because memory controllers differs greatly, but I consider this a safe start.
> 
> 
> 
> Spoiler: IMC_3733MT/s
> 
> 
> 
> 
> View attachment 2486534
> 
> 
> 
> 
> I hope this helps a little.
> 
> Edit: Use values for 1KB.
> 
> @lmfodor
> I hope that you can use the screenshots above to use the right values.


Hi @Ramad! What a good spreadsheet! Should I use the second group of tables right? (I mean the Below ones). Can you share this excel with us? It would be great to write down and tune ..

Thanks! Martin 


Sent from my iPhone using Tapatalk Pro


----------



## wden

Hello all,
I've been testing new settings based on the information on this thread and it seems the below is the best I can get with this RAM. 
I've tried disabling GDM but was unable to run TM5 without errors. I also tried lowering tCL below 16 and it would not POST. Raising the voltages did not help either so I settled with these recommended voltages and these timings that run TM5 25 cycles without errors.
Are there any potential additional tweaks that I could do?


----------



## mirzet1976

Hale59 said:


> On the superpi 32m amd zen low clock challenge, I'm the top ryzen 3000s with this little road runner. Just 2 seconds behind a 5800X.


To slow for 4.875GHz


----------



## paih85

mirzet1976 said:


> To slow for 4.875GHz
> 
> View attachment 2486651


----------



## Nighthog

Added both my RX 6900XT & RX Vega 64... nothing more to be said that it was too much for my loop. 50C water temperature caused my water-cooled memory to overheat @ 4266MHz & 4200MHz...
4266MHz starts to give trouble @ 38C and 4200MHz works to around 45C before there is trouble. Had to open the case up to let it cool down and have to reconsider a major upgrade to my loop.

I thought it was unstable a GPU that was causing issues but it was overheating memory AGAIN!

600-700W isn't meant for a single 360mm & 120mm radiator. (closed case 50C, open case ~40C)


----------



## SesioN

Ramad said:


> The RAM does not care if tRCDWR is set to 8, it will run this timing at tRCDRD, so 15CK here. tRP should equal tRCD, so 15CK and tRAS is going to be 15CK+15CK = 30CK.
> New tRC would be (tRP+tRAS) 15CK+30CK= 45CK. I'm talking minimums here. I would set tRAS to 30CK+2CK and tRC to 45CK+2CK for stability. These timings would still be tight for a RAM at 3733MT/s even if they seem higher and the RAM would be happy with them.
> 
> If I calculate subtimings for 3733MT/s, I would use subtimings for a 2133MT/s, 2400MT/s or 2666MT/s to preserve the relationship between these delays.
> 
> 
> 
> Spoiler: 2133MT/s
> 
> 
> 
> 
> View attachment 2486531
> 
> 
> 
> 
> 
> 
> Spoiler: 2400MT/s
> 
> 
> 
> 
> View attachment 2486532
> 
> 
> 
> 
> 
> 
> Spoiler: 2666MT/s
> 
> 
> 
> 
> View attachment 2486533
> 
> 
> 
> 
> I would tune the primeries and use the subtimings (always round up).
> 
> Getting the IMC timings is by using 3733MT/s in my calculator. There is room for tuning here too, because memory controllers differs greatly, but I consider this a safe start.
> 
> 
> 
> Spoiler: IMC_3733MT/s
> 
> 
> 
> 
> View attachment 2486534
> 
> 
> 
> 
> I hope this helps a little.
> 
> Edit: Use values for 1KB.
> 
> @lmfodor
> I hope that you can use the screenshots above to use the right values.


Thank you allot. I've taken your advice and tried to apply all timings by book.

I've went to 1T GDM enabled and corrected RCDWR, RCDRD, tRTP, tRP, tRAS, tRFC and more.. Now everything should be correct. Tho I decided to not apply the +2 for extra stability just "yet".

Running y-cruncher with all 9 tests for at least 5 passes is my target. Then running OCCT for at least 5 hours.

If you still see anything to be improved please let me know! 

Also I've a question:
Is it bad that my ProcODT is 48 and myClkDrvStr 60?
I've made the experience with my ram modules that putting those lower leaded to instability. (But maybe it was also duo to bad timings set etc.)

@Ramad Would it provide any advantage to play with those values more? (ProcODT, rttNom, rttWr, rttPark, Bus..)


----------



## lmfodor

Hi! I was trying to lower the primaries and take the opportunity as a reference to copy the values from the Igors Lab review. Adapt some values, adjust, release, however I don’t see much difference with my previous values that I made with the help of @Veii where the times were looser, and it used 1.5V of VDIMM vs the new ones more adjusted to 1.55v. I must be at the limit of performance, and for the results I would stay with the previous values, due to the lower voltage and also because I did many stability tests, not so with the copy of Igor's I thought that with flat values 14-14-14 24 would be better, or maybe I should raise the tRAS to 28 and try ..








AIDA timings


----------



## SesioN

lmfodor said:


> Hi! I was trying to lower the primaries and take the opportunity as a reference to copy the values from the Igors Lab review. Adapt some values, adjust, release, however I don’t see much difference with my previous values that I made with the help of @Veii where the times were looser, and it used 1.5V of VDIMM vs the new ones more adjusted to 1.55v. I must be at the limit of performance, and for the results I would stay with the previous values, due to the lower voltage and also because I did many stability tests, not so with the copy of Igor's I thought that with flat values 14-14-14 24 would be better, or maybe I should raise the tRAS to 28 and try ..
> 
> 
> 
> 
> 
> 
> 
> 
> AIDA timings
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sent from my iPhone using Tapatalk Pro


Your first screenshot is unreadable, terrible low resolution.


----------



## FleischmannTV

Right-Click on the picture and open in new tab.


----------



## lmfodor

SesioN said:


> Your first screenshot is unreadable, terrible low resolution.


Hi! Yes, I uploaded again. Now should be better! The results are very similar. 


Sent from my iPhone using Tapatalk Pro


----------



## RosaPanteren

paih85 said:


> View attachment 2486664


----------



## Hale59

mirzet1976 said:


> To slow for 4.875GHz
> 
> View attachment 2486651


For a 3100? LOL


----------



## lmfodor

SesioN said:


> Thank you allot. I've taken your advice and tried to apply all timings by book.
> 
> I've went to 1T GDM enabled and corrected RCDWR, RCDRD, tRTP, tRP, tRAS, tRFC and more.. Now everything should be correct. Tho I decided to not apply the +2 for extra stability just "yet".
> 
> Running y-cruncher with all 9 tests for at least 5 passes is my target. Then running OCCT for at least 5 hours.
> 
> If you still see anything to be improved please let me know!
> 
> Also I've a question:
> Is it bad that my ProcODT is 48 and myClkDrvStr 60?
> I've made the experience with my ram modules that putting those lower leaded to instability. (But maybe it was also duo to bad timings set etc.)
> 
> @Ramad Would it provide any advantage to play with those values more? (ProcODT, rttNom, rttWr, rttPark, Bus..)
> 
> 
> View attachment 2486667


Hi @SesioN, I would try your timings. Can you share your AIDA64 benchmarks results? 

I think you should have to loose a bit tRRD to 6/8 or 7/9 and tWRD to 5/14
Last question, what is your VDIMM? Thanks 

Sent from my iPhone using Tapatalk Pro


----------



## KedarWolf

lmfodor said:


> Hi @SesioN, I would try your timings. Can you share your AIDA64 benchmarks results?
> 
> I think you should have to loose a bit tRRD to 6/8 or 7/9 and tWRD to 5/14
> Last question, what is your VDIMM? Thanks
> 
> Sent from my iPhone using Tapatalk Pro


I'll do AIDA64 with 2x16GB when I get home from work.

The only difference from the screenshot is I'm on A21O BIOS now and 1.48v memory.

I'm OCCT and TM5 WHEA free and stable.


----------



## lmfodor

KedarWolf said:


> I'll do AIDA64 with 2x16GB when I get home from work.
> 
> The only difference from the screenshot is I'm on A21O BIOS now and 1.48v memory.
> 
> I'm OCCT and TM5 WHEA free and stable.
> 
> 
> View attachment 2486698


It would be great if you can share your AIDA results. I will try to replicate some of your settings. I wonder what you have a TRP so high? Mine is 14. And also why tRAS so low at 21.. let’s see your AIDA results. And you finally updates to latest BIOS:SMU, the same that I’m using 


Sent from my iPhone using Tapatalk Pro


----------



## KedarWolf

lmfodor said:


> It would be great if you can share your AIDA results. I will try to replicate some of your settings. I wonder what you have a TRP so high? Mine is 14. And also why tRAS so low at 21.. let’s see your AIDA results. And you finally updates to latest BIOS:SMU, the same that I’m using
> 
> 
> Sent from my iPhone using Tapatalk Pro


I know, weird tRP and tRAS but after a suggestion by someone, I find it benches better and easier to get stable than 14-28. Technically I should run it at 21-21 but 19-21 a bit better in benches.

Edit: I went back to A21O BIOS as both R20 multicore and SuperPi 32M are better for me with that BIOS than A24.

A24 does a bit better in AIDA64 though.


----------



## Veii

KedarWolf said:


> Edit: I went back to A21O BIOS as both R20 multicore and SuperPi 32M are better for me with that BIOS than A24.
> 
> A24 does a bit better in AIDA64 though.


Any information on the SMU used there ?
56.50 i got to check performed badly with the powermanagement rewrite

EDIT:
Oh something else,
Are your MSI bioses already AMD CBS unlocked ?
The 56.50 ?
Any news about 1202 behavior and Realtek NUC/USB Droupt issues / fix ?


----------



## KedarWolf

Veii said:


> Any information on the SMU used there ?
> 56.50 i got to check performed badly with the powermanagement rewrite


A20O



Code:


Scanning: E7D13AMS.121O (32,768 KB) ComboAM4v2PI 1.2.0.1
   56.46.0 (125 KB) [01131C00 - 01150EA0]
   56.46.0 (  1 KB) [01170E00 - 01171220]
   56.46.0 ( 55 KB) [01190E00 - 0119E9C0]
   46.68.0 (110 KB) [01222E00 - 0123E4A0]
   46.68.0 (  1 KB) [0123E500 - 0123E920]
   46.68.0 ( 52 KB) [0123EA00 - 0124BA60]
   55.78.0 (132 KB) [01366500 - 013874C0]
   55.78.0 ( 63 KB) [013A6B00 - 013B6500]
   64.41.0 (134 KB) [014E6500 - 01507B40]
   64.41.0 ( 68 KB) [01527200 - 01538060]

A24



Code:


Scanning: E7D13AMS.A24 (32,768 KB) ComboAM4v2PI 1.2.0.2
   56.50.0 (125 KB) [01131C00 - 011511A0]
   56.50.0 (  1 KB) [01171100 - 01171520]
   56.50.0 ( 55 KB) [01190E00 - 0119EAB0]
   46.70.0 (110 KB) [01223000 - 0123E880]
   46.70.0 (  1 KB) [0123E900 - 0123ED20]
   46.70.0 ( 52 KB) [0123EE00 - 0124BE70]
   55.78.0 (132 KB) [01366500 - 013874C0]
   55.78.0 ( 63 KB) [013A6B00 - 013B6500]
   64.44.0 (134 KB) [014E6500 - 01507BE0]
   64.44.0 ( 68 KB) [01527200 - 015380A0]


----------



## Veii

KedarWolf said:


> A20O
> 
> 
> 
> Code:
> 
> 
> Scanning: E7D13AMS.121O (32,768 KB) ComboAM4v2PI 1.2.0.1
> 56.46.0 (125 KB) [01131C00 - 01150EA0]
> 56.46.0 (  1 KB) [01170E00 - 01171220]
> 56.46.0 ( 55 KB) [01190E00 - 0119E9C0]
> 46.68.0 (110 KB) [01222E00 - 0123E4A0]
> 46.68.0 (  1 KB) [0123E500 - 0123E920]
> 46.68.0 ( 52 KB) [0123EA00 - 0124BA60]
> 55.78.0 (132 KB) [01366500 - 013874C0]
> 55.78.0 ( 63 KB) [013A6B00 - 013B6500]
> 64.41.0 (134 KB) [014E6500 - 01507B40]
> 64.41.0 ( 68 KB) [01527200 - 01538060]
> 
> A24
> 
> 
> 
> Code:
> 
> 
> Scanning: E7D13AMS.A24 (32,768 KB) ComboAM4v2PI 1.2.0.2
> 56.50.0 (125 KB) [01131C00 - 011511A0]
> 56.50.0 (  1 KB) [01171100 - 01171520]
> 56.50.0 ( 55 KB) [01190E00 - 0119EAB0]
> 46.70.0 (110 KB) [01223000 - 0123E880]
> 46.70.0 (  1 KB) [0123E900 - 0123ED20]
> 46.70.0 ( 52 KB) [0123EE00 - 0124BE70]
> 55.78.0 (132 KB) [01366500 - 013874C0]
> 55.78.0 ( 63 KB) [013A6B00 - 013B6500]
> 64.44.0 (134 KB) [014E6500 - 01507BE0]
> 64.44.0 ( 68 KB) [01527200 - 015380A0]


Uhm, A20O or A21O performed better for you
If you don't have much to do:

Lift cTDP limit to 400W, Package Power limit to 400W (AMD CBS - NBIO - SMU Common options)
Lift EDC to 450A & if you have access to SOC TDC and SOC EDC (AMD OVERCLOCKING - ADVANCED PBO - MANUAL) put them at 90A
Put under AMD CBS - NBIO - SMU - DPM LCLK both states to 2-1-1-1-2-1-1-1 (only Level 0 being at "2" = 600mhz)
DF States disabled
Global C-State generation enabled
And compare please how Aida64 behaves in L3 latency & bandwidth @ high-perf powerplan *
High-perf powerplan is required to keep up boosting stability . It's also broken but "less broken" than balance or low-power
* whenever you find time to do so
** a SiSandra MCE run with both Inter-core latency readout.txt next to each other would also help illustrate the positive or negative rewrite of the boosting-algo
*** it's unclear if they fixed it on 1202 AGESA , as 56.50 is 1201 & plain broken. Also seems to have changes on the IMC FW. Something there causes memOC issues
**** i do have a suspicion that they tried first broke SMU fully on 56.50 on their rewrite of the prediction algorithm to try and fix "overboosting-bug" & work against the Spectre v4 issue


----------



## Ramad

@RonLazer @lmfodor 

I will see how to make the spreadsheet easier to use upload it her hopefully tomorrow, it's close to midnight here. 



SesioN said:


> Thank you allot. I've taken your advice and tried to apply all timings by book.
> 
> I've went to 1T GDM enabled and corrected RCDWR, RCDRD, tRTP, tRP, tRAS, tRFC and more.. Now everything should be correct. Tho I decided to not apply the +2 for extra stability just "yet".
> 
> Running y-cruncher with all 9 tests for at least 5 passes is my target. Then running OCCT for at least 5 hours.
> 
> If you still see anything to be improved please let me know!
> 
> Also I've a question:
> Is it bad that my ProcODT is 48 and myClkDrvStr 60?
> I've made the experience with my ram modules that putting those lower leaded to instability. (But maybe it was also duo to bad timings set etc.)
> 
> @Ramad Would it provide any advantage to play with those values more? (ProcODT, rttNom, rttWr, rttPark, Bus..)
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2486667


I find PROCODT and Rtt depending on combination of used RAM, Motherboard and CPU, so my advice is to use the best settings for your system. If your system is stable using PROCODT = 48 Ohm and Clock driver strength = 60 Ohm, then these are the correct settings for your system. The same goes for Rtt. 

I'm using X570 Tomahawk with 2700X and Crucial Rev. E RAM @3800MT/s, I'm using a flat 20 Ohm driver strength for all settings and PROCODT @48 Ohm with Rtt settings of (RttNOM, -WR, -PARK) Disabled - RZQ/3- RZQ-5, because my hardware combination likes these settings best. My tests are linked in my sig.

I'm trying to say that it's best to find the best setting combination for your system, the run 2 hours of y-cruncher, OCCT or prime95, if the system is stable then you are done and can start enjoying using your system.


----------



## Veii

RonLazer said:


> Can I just edit that value in AMIBCP and save the BIOS file again and it will work? Do you have any guides on this?


Yes you can. Stock is 930 not 900
We could expect it was 900mV but it isn't
They hopefully stalk this and many other threads to notice, but it wasn't
sub 900mV is required for 2100+ FCLK
Speculations are one thing, results are another.

My results show that A0 need specific powering settings beyond the casual "A0 stops functioning beyond 4133 MT/s" information
2100 FCLK needs to follow specific undervolting rules to even have a chance of posting and not Package throttling down.
900mV CPU VDDP is already the minimum requirement for it. But it was staying at 930mV
Seeing it "hopefully" now fixed at 900mV ~ would mean that i did everything correctly with spreading the issue. I hope this is really the case

Lower values like 880mV and 860mV sadly are chip-exclusive
870 and 890 do make issues, soo it's hard to recommend doing a fix there.

An AMIBCP guide would mean, sharing the information about what version you need of the tool which is under NDA by AMI
And helping with breaking their TOS by using it and sharing guides on it.
I should not do this 
But i can tell you to look in Win-Raid and check the guide shared by 1usmus on his "How to update the Bios" thread here on OCN
AMIBCP_v5.02.0031 is the lowest required version that supports the current bioses
32mb bioses need to be split at the perfect half, as AMIBCP is not able to split recognize SETUP_VAR from both bioses


Spoiler: Like here














Split it, edit it, save it , combine/replace it 
It won't warn you about the size, if they are identical in length

To unhide stuff, it can need an edit in AMITSE.
Which pretty much defines the menu order of xxx hex menu item and xxx hex submenu function
AMIBCP will show you the whole list of potential possible named options, which may or may be missing in AMITSE
Which just means, that AMIBCP can not see them as "menu points". Soo you can't unhide something that doesn't have a link or "doesn't exist"

A permanent change in AMIBCP as "optimal" ~ will be loaded AFTER a CMOS reset and after a profile has been made which keeps the value at Auto
On a CMOS reset, it will temporary! enter the Failsafe settings in order to boot up and post
It's technically to 92% impossible that you brick the board by having bad "optimal" values
But the risk can exist, as we should not trust bios engineers having a clean and functioning CMOS restore method.
I mean we "should" trust them , but reality shows that we "can't" hope and trust. Same for Auto timing's, don't trust in variance but trust in set values 


craxton said:


> anyhow, my Question is "does this look correct"? no errors from any tests at all.


tCKE 11 is for 4000MT/s
4067 goes more into the 11.5 range
Likely the 12 range
See if tCKE 12 is stable
* meaning, test it and use your system. Bad tCKE will cause random reboots and random strange application crashes ~ it won't crash on consistent full load, unless it's off by a big bit



craxton said:


> (yes best score ive gotten, C/O -15 with +60mv offset)
> pc will crash or do random things while anything less than 60mv, core voltage in hwinfo never goes over 1.41.


Nice 
As long as PBO is in place, don't mind it going higher
You can move in the 1.35v "constant voltage" range ~ as long as it's consistent. Even for AVX2 tests
FIT will trigger failsafe protection and crash if AVX2 loads which require max voltage of 1.18v run beyond 1.3v ~ soo don't worry too much

As for boost voltage, don't worry going to 1.52 for 1 core
There is a huge book of information to this, half of which 1usmus knows way more about
But also half of which is not allowed to be talked about ~ kind of sad, but if you want extended-knowledge you need to restrain the spread. Sad
Anywho, good job !


lmfodor said:


> I found two colleagues we share the same memory kit @gabian @SesioN and I think we can work together to find the best result as all share the same SMU and even with one the same


Starting with "don't use SMU 56.50" haha 
No i hope you have better experience with it. But this one is broken in terms of inter-core bandwidth and inner-core access time = lower IPC overall , but maybe? more secure


lmfodor said:


> 3. My tRRD and tWRD are set more looser to get more read write performance


this point is very specific
Lower does increase bandwidth, but higher doesn't lose that much. Lower primaries benefit more than lower tRRD & tWTR
Memory might not autocorrect it, but the IMC does actively autocorrect on Vermeer
If lower values while remaining TM5 stable, lead to worse perf ~ then it's actively error-correcting.
It's good that you keep testing, but the statement is the opposite

Lower values do indeed increase throughput, but what runs and what is autocorrected. This line keeps blurring more and more , as Vermeer is fantastic at it's autocorrection Job 


lmfodor said:


> And CADBUD I guess I should set to 60-20-20-20 or similar


Linking you this current re-written writeup (same thing just re'mentioned as it gets lost)








MSI B550 Unify / Unify-X Overclocking & Discussions...


Command center allows to change vdimm? Never knew..




www.overclock.net




X-20-20-20 shall only be used IF you use CAD_BUS SETUP timings. Else use X-20-40-20 or X-20-30-20/24
CsOdtDrvStr (3rd value) is needed, to work against the mediocre memory training we got since AGESA 1.1.0.0A


lmfodor said:


> I decide to match @Veii values to loose a bit the values and improve performance. And also I read that tRRDL should be rRRDS +2 as a rule. DRAM calculator recommends 3/8
> Regarding twTRS and L I also follow Veii and DRAM calculator that recommends 5 14. Do you see it unbalanced? What is the value that influence in tRRDS to be 4, and why tRRDL is not 6? Thanks for your help!


DRAM Calculator and my results are different 
Timings on DRAM Calculator only work "as a whole" . If you don't match one thing of Yuri's presets, their efficiency goes down or fully breaks
They are shared as a whole ~ while the "calculated = imported" timings are rather Beta and an attempt. It misses current research and is not optimal for Vermeer.
Either fully clone the presets, or don't use it ~ doing blind modifications will destroy his pre-tested timings 

There is not a +2 rule, not fully
There is a +2 distance rule on SD, DD's
But it has to do with tRRD & tWTR
As there is no done public writing & illustration of it's scaling ~ there is only a "suggestion" what to use
It's no unified rule, as there are too many unwritten exceptions. I can't call this a rule and didn't write it that way
You can use tRRD as 4-5 , same as 4-7 ~ it depends

The only half-way followable universal rule is to match tWTR_L to 2x of tRRD_L
But even that has tiny exceptions, if you decide to use a different SD,DD layout ~ like MSI loves to do with 1-5-4-1-7-6
Soo "no rule" , just slight missunderstood suggestion from old topics


thismock said:


> I’m considering replacing my Asrock B450 ITX, which has been good to me, but has some pretty serious overclocking limitations (max 1.5 vdimm, 50mv vdimm steps, 35mv vsoc steps, no CPU VDDP, etc). I’m certain that I’m blocked from further progress by my motherboard. The Asrock B550 Phantom Gaming ITX is probably the best fit for me, as long as you’ve had positive experiences with Asrock’s B550 BIOS (understanding that they’re slower to provide new BIOSes with AGESA updates). It also helps that it ~seems~ the Asrock boards have the fewest problems with WHEAs at high FCLKs. Otherwise I’m looking at the Asus Crosshair VIII Impact or B550i Strix.
> 
> On a related note, it’s a real pain to find which motherboards and their BIOSes provide access to which tuning settings (example: CPU VDDP), let alone their min-max values and steps. I’ve found that most motherboard manuals do not provide a complete list of BIOS options, so I have to use screenshots from hardware reviews.. which can be out-of-date or incomplete. Maybe there’s a resource out there that already has this info — if anyone knows of one, please let me know!


At this stage, of sloow bios support ~ i consider the Biostar lineup with the same required specs to have as few issues as possible , on the current testing

Renesas 60-90A Mosfets
Renesas or TDA PWM controller
Intel NUC , not Realtek
Not being X570 because chipset PCIe 4.0 does cause issues

















That's about it
There are couple more which come into play, but it requires hope that all Realtek 2.5gbit ethernet issues are resolved
Then the added options are
































Sadly i keep hearing WHEA issues from all MSI users on their thread beyond 2000 FCLK
Soo i can not recommend it. Don't think they got it figured out at this point.
I wish for it, but wishing won't resolve Realtek EFI driver issues & other strange unfigured out WHEA #19 issues

Another option to select is the X570 ITX/TB3
and maybe some more X570 options ~ if you want to trust that the brand has AMD PBS visible , for enforcing PCIe 3.0 on the chipset and not 4.0
Both ASRock ITX lineups don't have any WHEAs whatsoever. Autocorrection keeps existing. Upper limits keep staying at 2167 FCLK for both Dual CCD gimped and single CCDs not gimped units
But the 1+ month added delay (vs the Rival company) on bios updates ~ is frustrating.
For normal consumers i guess wonderful, as the bios might be stable (current one is not , but that's not ASRocks fault but broken SMU 56.50)
But for enthousiasts or explorers like me ~ a locked down CBS, a bare minimum bios options showcase. No special enchancers, no boost extenders beyond AMDs set 200mhz. It's booring without a full AMD CBS unlock
Biostar's bios is currently better, but they love to use offsets, like gigabyte does ~ sad sad

Downside to both ITX boards, we lack memory voltage readouts
And X570 users lack switching frequency ~ while it's there in the bios just hidden to make people buy their more expensive but worse spec'd hardware. 

__ https://twitter.com/i/web/status/1348312213715562499 illustration & example. Still ignored
Soo up to you 
I am very happy with the board specs & performance, but very unhappy with the bios update delay. It's booring in all honesty


wmunn said:


> Any suggestions on how to get this stable at 3800 ?
> I am good at 3733 but fails at 3800
> 
> 
> Spoiler: ZenTimings


What does "fails" mean ?
which errors do appear
Don't use odd timings and GDM
Even them out, or try to get at lower speeds GDM off , 2T ~ stable
It doesn't need any added voltage for it, just a change in RTT's and CAD_BUS
(IF they where broken, which GDM off will show very clearly)


Oversemper said:


> Hello, Everybody! I'd appreciate if somebody can help me in the following situation.
> I had Ryzen 3800x (Asus x570-f) with a nice RAM overclock from 3200 to 3733, IF 1866 (BLS2K16G4D32AESE 3733 16-19-16-36 1T 1.35v).
> It was with Radeon vii (pci 3.0).
> 
> Today I changed it to radeon 6900xt and my PC did not post
> 
> IF 1633 is the maximum frequency at which my 3800x can work with a PCI 4.0 card?
> Or may be there some options to tweak? Obviously, I'm not going to lower PCI to 3.0 over that.


Its the link between IO-Die to Chipset, these PCIe 4.0 lanes cause issues
If you have AMD PBS or maybe find it somewhere in the bios
Undervolt the X570 chipset slightly - tiny bit like 5-10mV less
And drop it to PCIe 3.0

The X16 slot from the CPU will remain at 4.0 x16 speeds
I can see that a 6900 (XTE) will require the higher bandwidth, but FCLK at least till 1900 should be doable without any PCIe 4.0 conflicts
After 2000+ you start to see them

if you can't drop the chipset lanes because of ~reasons~
then give VDDG IOD a bit higher voltage (less than 1150 please)
And give VDDG CCD a bit higher voltage (less than 1050 please)

Overall , share more information and a ZenTimings screenshot. We are guessing blindly here 





ZenTimings_v1.2.3.200-debug.zip







drive.google.com




^ Zentimings 1.2.3-200 Beta



Nighthog said:


> I thought it was unstable a GPU that was causing issues but it was overheating memory AGAIN!


Yikes
Any idea what to do ?
Thermodynamics wouldn't allow you a change even with a fan placed ontop of the dimms 
Hmm complicated


mongoled said:


> Regards 1T 32GB,
> 
> In the time that you have been participating in this forum did you see anybody running 1T with GDM disabled using 32GB of RAM while pushing 3800/1900 and be TM5 (along with other stress tests) stable ???
> 
> Myself personally have not, this should tell you something.


I've seen it possible, on 2x16gb DR , but i need to get a proof of stability result too





Tuned - Google Drive







drive.google.com






mongoled said:


> The only time I had some sucess with 32GB 1T and GDM disabled was when I followed Veii advice and paired a good set of A2s with a good set of A0s, but unfortunately at that time we did not know that RttPark running at RZQ/1 had the capacity to kill the A0s dimms.
> 
> So I learned the hard way, as well as others, that while we learn, we also have to experiment and find issues in so that others dont destroy things by accident because we already did it
> 
> 😂😂😂


Still saddens. Really sorry about the dimms 
Sadly the sacrifice didn't lead to the result, as it happened "randomly"
Only now we kind of have an idea what it was. Before nearly frying my own kit too haha.
Did you get out of the financial situation decently ?
Anything i can do to help , except sending you a kit ~ as you are too far away 🙁


mongoled said:


> I laugh, but cant help worry for the health of Veii


Eh, it's borderline 
RL bothers me more , than just the repetitive answers here.
Don't mind it much. The end goal is to push the bar a bit higher.
50.2ns is what people get. Soo identical to the old 50.1ns result
Now you have to go sub 50ns 

I give myself a bit of time off from here, soo it's fine
Thank you for thinking about me 🙇‍♂️


----------



## heptilion

@Veii 

As per your post above this what the google doc calculator ask me to input which is perfectly stable and ive been running for a couple of months now. aida latency is 54.6-56.8 variance. Am i having any timeout issues or incorrect timings mismatch?


----------



## Veii

heptilion said:


> @Veii
> 
> As per your post above this what the google doc calculator ask me to input which is perfectly stable and ive been running for a couple of months now. aida latency is 54.6-56.8 variance. Am i having any timeout issues or incorrect timings mismatch?
> 
> View attachment 2486719


Can't see any issues ~ but the lattency results are a bit weak
But you can test something for me if you want to bother 
Please first doublecheck with Safe-Mode boot , how big the difference is to your OS one

If you want to keep up stability on higher FCLK's, tRRD and tWTR have to go up
Is this near 1.48vDIMM ?
maybe bellow 1.52v ?
Or does maybe tCWL 14 eat at least 1.55 ?


----------



## heptilion

Veii said:


> Can't see any issues ~ but the lattency results are a bit weak
> But you can test something for me if you want to bother
> Please first doublecheck with Safe-Mode boot , how big the difference is to your OS one
> 
> If you want to keep up stability on higher FCLK's, tRRD and tWTR have to go up
> Is this near 1.48vDIMM ?
> maybe bellow 1.52v ?
> Or does maybe tCWL 14 eat at least 1.55 ?


This is with safe mode boot. With normal boot with 200+ processes its 55.3. I have tried playing around with for a month testing voltages to get the latency to get down but this is the best i could do 
Dram Voltage is at 1.48v

Yes I shall be your guinea pig. I will try testing for you


----------



## Veii

heptilion said:


> This is with safe mode boot. With normal boot with 200+ processes its 55.3. I have tried playing around with for a month testing voltages to get the latency to get down but this is the best i could do
> Dram Voltage is at 1.48v
> 
> Yes I shall be your guinea pig. I will try testing for you


Hmmm, that Sophia script didn't help to remove a bit of the bloat ?








GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11


:zap: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11 - GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-t...




github.com





A guinea pig needs to deliver consistent results, haha
Please try SD, DDs @ 1-4-4-1-5-5 and drop tWTR to 3-8
Just Aida64 confirm it's faster

If not , ignore it and try 1-4-3-1-5-4 with tRDWR to 10
See if you can even boot that up 

Don't forget to make profiles, as these things easily can result in a full post refuse
If tRDWR at 10 is not stable at all under your current 4-6,4-12 tRRD, tWTR (with these SD, DDs)
Then give 1-5-4-1-7-6 a shot @ tRRD 5-7-20-5-14 (it would lower perf, but the result has to be nearly equal because of the lower tRDWR ~ which gives a big perf jump , if overlapping is synced correctly)

1.48v is expected haha, good job btw
Set looks exemplary 
* tWRWR is always the bigger value
** wish we could drop tRRD_S to 3, then i could give you something more harsh


----------



## KedarWolf

Veii said:


> Uhm, A20O or A21O performed better for you
> If you don't have much to do:
> 
> Lift cTDP limit to 400W, Package Power limit to 400W (AMD CBS - NBIO - SMU Common options)
> Lift EDC to 450A & if you have access to SOC TDC and SOC EDC (AMD OVERCLOCKING - ADVANCED PBO - MANUAL) put them at 90A
> Put under AMD CBS - NBIO - SMU - DPM LCLK both states to 2-1-1-1-2-1-1-1 (only Level 0 being at "2" = 600mhz)
> DF States disabled
> Global C-State generation enabled
> And compare please how Aida64 behaves in L3 latency & bandwidth @ high-perf powerplan *
> High-perf powerplan is required to keep up boosting stability . It's also broken but "less broken" than balance or low-power
> * whenever you find time to do so
> ** a SiSandra MCE run with both Inter-core latency readout.txt next to each other would also help illustrate the positive or negative rewrite of the boosting-algo
> *** it's unclear if they fixed it on 1202 AGESA , as 56.50 is 1201 & plain broken. Also seems to have changes on the IMC FW. Something there causes memOC issues
> **** i do have a suspicion that they tried first broke SMU fully on 56.50 on their rewrite of the prediction algorithm to try and fix "overboosting-bug" & work against the Spectre v4 issue


Yeah, I meant A21O. Tring those now.


----------



## Veii

KedarWolf said:


> Yeah, I meant A21O. Tring those now.


These should be the things that need to change, in order for both SMU 56.44 till 56.46 (still AGESA 1.2.0.0 or 1.1.8.1 and up)
to reach peak Cache bandwidth and L3 speedup

Sadly lifting these limits will push more voltage to the cores and FIT can trigger backwards.
Soo it's not unexpected that you need to increase negative CO , or at least -5mV negative offset ~ the supplied voltage

The current focus is only maximum cache peak bandwidth between these AGESA changes (voltage adjustments later)
As this is what AMD messed up recently, and keeps throttling ~ because the boost is a bit too aggressive and powerplans break
Soo internally randomly 50Ghz is requested ~ FIT shock-throttles back & at best users just have random hickups
At worst users have forced random reboots

It can be made usable and halfway fixing AMDs messed up issues
But only halfways
Soo it's better to keep DF-States fully disabled for now
Btw, CTR does enable DF-States again , while it runs
Soo it needs either a "nearly not variable" powerplan == high-perf one, or one with integrated frequency boost limits ~ to prevent random idle-wakeup crashes

Big story
Your current focus is something you can not change
"Internal Cache Overdrive range and lowest access time"
Use the SMU which can deliver this, as foundation for everything else
I'm sure 56.50 is broken , and only get's to "stock" L3 results, if you lift all limits up
Then comparing this max range with the older 1200 range, 1200 wins in bandwidth and latency == IPC 

EDIT:
Don't mind to doubleclick each L3 result to retest and retest
We look for the absolute best result the chip can possibly get under XYZ SMU version 
I hope that 1202 fixes the mess they created on 1201, but i want to be proofed wrong ~ so far 1201 broke far more than only the boosting range


----------



## Veii

@KedarWolf








BLCK OC ?
Haven't seen ZT report BCLK changes so far
Ryzen-SMU-Checker-1208.zip
In case you still miss it


----------



## KedarWolf

Veii said:


> @KedarWolf
> 
> 
> 
> 
> 
> 
> 
> 
> BLCK OC ?
> Haven't seen ZT report BCLK changes so far
> Ryzen-SMU-Checker-1208.zip
> In case you still miss it


Oh yes, that was from trying 4000 on RAM, fixed now.


----------



## lmfodor

Veii said:


> Starting with "don't use SMU 56.50" haha
> No i hope you have better experience with it. But this one is broken in terms of inter-core bandwidth and inner-core access time = lower IPC overall , but maybe? more secure
> 
> this point is very specific
> Lower does increase bandwidth, but higher doesn't lose that much. Lower primaries benefit more than lower tRRD & tWTR
> Memory might not autocorrect it, but the IMC does actively autocorrect on Vermeer
> If lower values while remaining TM5 stable, lead to worse perf ~ then it's actively error-correcting.
> It's good that you keep testing, but the statement is the opposite
> 
> Lower values do indeed increase throughput, but what runs and what is autocorrected. This line keeps blurring more and more , as Vermeer is fantastic at it's autocorrection Job
> 
> Linking you this current re-written writeup (same thing just re'mentioned as it gets lost)
> 
> 
> 
> 
> 
> 
> 
> 
> MSI B550 Unify / Unify-X Overclocking & Discussions...
> 
> 
> Command center allows to change vdimm? Never knew..
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> X-20-20-20 shall only be used IF you use CAD_BUS SETUP timings. Else use X-20-40-20 or X-20-30-20/24
> CsOdtDrvStr (3rd value) is needed, to work against the mediocre memory training we got since AGESA 1.1.0.0A
> 
> ...
> 
> There is not a +2 rule, not fully
> There is a +2 distance rule on SD, DD's
> But it has to do with tRRD & tWTR
> As there is no done public writing & illustration of it's scaling ~ there is only a "suggestion" what to use
> It's no unified rule, as there are too many unwritten exceptions. I can't call this a rule and didn't write it that way
> You can use tRRD as 4-5 , same as 4-7 ~ it depends
> 
> The only half-way followable universal rule is to match tWTR_L to 2x of tRRD_L
> But even that has tiny exceptions, if you decide to use a different SD,DD layout ~ like MSI loves to do with 1-5-4-1-7-6
> Soo "no rule" , just slight missunderstood suggestion from old topics


Hello @Veii, each answer of yours is a breath of air for those of us who are starting !! Very good what you sent me about the tRDD and tWTR. There are many unwritten rules it is true. Also about what you sent me from CADBUS. I'm going to test with the values you put. Where if I have problems is when I modify the SC DD. I am in 1-4-4-1-6-6 and if for example I try to download or put 1-5-4-1-7-6 I can't get a POST or even enter safe mode. So I must clear the cmos and start from a profile. I tried many variants. I do not know if it is related to some voltage or to the RTTs or something that is the only value that when modified the mobo does not start. Another piece of information that I found relevant and unwritten is whether tCWL could need 1.55V. I found that I have a lot of room to increase the voltage. With 1.55v I do not exceed 42 degrees with good ambient temperature. So I decided to copy values as a stepup, for example copy yours with 15 flat for the primaries and even all the other values, but I found that the benchs are not that good and also TM5 gives me errors almost immediately. Copy the best values from Igor's Lab, and although I have a fairly similar performance TM5 gives me "many" errors in the first cycle, so I cancel. That is, I keep trying to lower the primaries even though the configuration you helped me build is the one that performs the best and you still spend days of stress testing. Maybe there are values that do not seem to be well related but I have been playing, using the PC for all kinds of tasks and never a WHEA or error. Here I share my last attempt with Igor's values .. performance just below "our configuration" but many errors.
This is “our” timings at 1.55








This is the Igor’s timings - very low primaries.. a lot of errors in TM5 (the grey are de Igor’s and the white mine adapted










Sent from my iPhone using Tapatalk Pro


----------



## KedarWolf

Veii said:


> Any information on the SMU used there ?
> 56.50 i got to check performed badly with the powermanagement rewrite
> 
> EDIT:
> Oh something else,
> Are your MSI bioses already AMD CBS unlocked ?
> The 56.50 ?
> Any news about 1202 behavior and Realtek NUC/USB Droupt issues / fix ?


No, I only have the A21O BIOS unlocked. I tested your settings. It would reboot trying to boot. I narrowed it down the the CBS menu global c-states and disabling them stopped it.

The rest, no noticeable difference in AIDA64 but R20 dropped 300 points and SuperPi dropped almost .100ms.


----------



## Veii

lmfodor said:


> Hello @Veii, each answer of yours is a breath of air for those of us who are starting !! Very good what you sent me about the tRDD and tWTR. There are many unwritten rules it is true. Also about what you sent me from CADBUS. I'm going to test with the values you put. Where if I have problems is when I modify the SC DD. I am in 1-4-4-1-6-6 and if for example I try to download or put 1-5-4-1-7-6 I can't get a POST or even enter safe mode. So I must clear the cmos and start from a profile. I tried many variants. I do not know if it is related to some voltage or to the RTTs or something that is the only value that when modified the mobo does not start. Another piece of information that I found relevant and unwritten is whether tCWL could need 1.55V. I found that I have a lot of room to increase the voltage. With 1.55v I do not exceed 42 degrees with good ambient temperature. So I decided to copy values as a stepup, for example copy yours with 15 flat for the primaries and even all the other values, but I found that the benchs are not that good and also TM5 gives me errors almost immediately. Copy the best values from Igor's Lab, and although I have a fairly similar performance TM5 gives me "many" errors in the first cycle, so I cancel. That is, I keep trying to lower the primaries even though the configuration you helped me build is the one that performs the best and you still spend days of stress testing. Maybe there are values that do not seem to be well related but I have been playing, using the PC for all kinds of tasks and never a WHEA or error. Here I share my last attempt with Igor's values .. performance just below "our configuration" but many errors.
> This is “our” timings at 1.55
> 
> 
> 
> 
> 
> 
> 
> 
> This is the Igor’s timings - very low primaries.. a lot of errors in TM5 (the grey are de Igor’s and the white mine adapted
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sent from my iPhone using Tapatalk Pro


Please write with linebreaks (shift+enter)
Do you know who gives it to igor or who spread it








Both of these can not work , it's uneven
1-5-4-1-7-6 is for 8gb dimms not 16gb
Maaybe 1-4-3-1-6-5 could work , maybe
Lower values are "weaker" not faster

I would like to know who gave this to igor
as it should be 14-8-16-*12-*24-36 not 14 
Same for the set people got from Buildzoid the 14-8-15-14
Technically it's correct and it looks faster while using less voltage ~ it does work "halfway"
But that's not the correct exploit , it should be used differently
Here is one old result that has it correctly








But it should be under GDM off. Only 2 kits could run it under GDM disabled 2T ~ so far
I need to test it
Dual rank as always should add +2 on tRDWR 

For the exploit , tRP needs to match tRCDavg value
and tRAS is double that value then
tRP can be equal to highest tRCD value and tCL, but for the exploit to work 100% , it needs to be the tRCDavg value = tRP
Else it's slower and a flat set most of the times is faster 


KedarWolf said:


> It would reboot trying to boot. I narrowed it down the the CBS menu global c-states and disabling them stopped it.


The reboot should only happen if DF states cause cores to fully suspend and then the wakeup triggers overboost and crashes
C-State generation doesn't suspend cores , it slows them down but they do not hibernate with it

It's something else
Doublecheck that DF-State didn't turn itself on, or disable it by hand
What you else can do is ask irusanovBG for the current ZenState 2.0 - to manually disable Package C6 state
That would also turn of DF States
Something enables them, else there is no reason why you have Overboost reboots


----------



## KedarWolf

Veii said:


> Spoiler
> 
> 
> 
> Please write with linebreaks (shift+enter)
> Do you know who gives it to igor or who spread it
> View attachment 2486734
> 
> Both of these can not work , it's uneven
> 1-5-4-1-7-6 is for 8gb dimms not 16gb
> Maaybe 1-4-3-1-6-5 could work , maybe
> Lower values are "weaker" not faster
> 
> I would like to know who gave this to igor
> as it should be 14-8-16-*12-*24-36 not 14
> Same for the set people got from Buildzoid the 14-8-15-14
> Technically it's correct and it looks faster while using less voltage ~ it does work "halfway"
> But that's not the correct exploit , it should be used differently
> Here is one old result that has it correctly
> View attachment 2486735
> 
> But it should be under GDM off. Only 2 kits could run it under GDM disabled 2T ~ so far
> I need to test it
> Dual rank as always should add +2 on tRDWR
> 
> For the exploit , tRP needs to match tRCDavg value
> and tRAS is double that value then
> tRP can be equal to highest tRCD value and tCL, but for the exploit to work 100% , it needs to be the tRCDavg value = tRP
> 
> 
> Else it's slower and a flat set most of the times is faster
> 
> The reboot should only happen if DF states cause cores to fully suspend and then the wakeup triggers overboost and crashes
> C-State generation doesn't suspend cores , it slows them down but they do not hibernate with it
> 
> It's something else
> Doublecheck that DF-State didn't turn itself on, or disable it by hand
> What you else can do is ask irusanovBG for the current ZenState 2.0 - to manually disable Package C6 state
> That would also turn of DF States
> Something enables them, else there is no reason why you have Overboost reboots


I had DF-States disabled already and they were disabled manually.

I'll check again, see if they enabled.

I DID have C-States in the main menu disabled though, I don't mean the CBS menu, I wonder if that was it.


----------



## KedarWolf

This is my SuperPi on a very bloated Windows install with MSI Dragon Centre installed (it installs a bunch of services) and a bunch of other crap as well.


----------



## Veii

I do think people need to have access to more than one google timings calculator.
For example Ramad's

Too many people share and use exploit timings, then maybe it doesn't work on their set (RRD, WTR, tRFC , tWR)
and stay clueless as to why it doesn't work or doesn't perform ~ same goes for reviewers out there who share these broken sets

We should get some baseline calculator following JEDEC rules
I see too many exotic sets and many users don't really have any clue why they use it.

Flat timings perform better, unless the exploit ones are correctly in sync.
People see them as "easy to run" and just use them - without putting work in actually lowering primaries (tRCD)
At this point close to everyone here should be able to run a flat CL14-14 set @ 3800 ~ with all the information that's out there in this thread
Later fix RTTs and step up to 3800C13-13-13 in the range of 1.64-1.68v
if frequency can't be pushed higher to for example 4000C14-14-14 or 4200C15-15-15

Don't focus your time on exploits when you aren't even close to 3800CL14-14-14 
Just as a suggestion and rant~


----------



## lmfodor

Veii said:


> Please write with linebreaks (shift+enter)
> Do you know who gives it to igor or who spread it
> View attachment 2486734
> 
> Both of these can not work , it's uneven
> 1-5-4-1-7-6 is for 8gb dimms not 16gb
> Maaybe 1-4-3-1-6-5 could work , maybe
> Lower values are "weaker" not faster
> 
> I would like to know who gave this to igor
> as it should be 14-8-16-*12-*24-36 not 14
> Same for the set people got from Buildzoid the 14-8-15-14
> Technically it's correct and it looks faster while using less voltage ~ it does work "halfway"
> But that's not the correct exploit , it should be used differently


Hi @Veii, yes you were right, I don't know why them publish some OC values that seems to be fine, at least they ran TM5 Anta777 Extreme, however I copied the exact timings and I get a lot of errors.



Veii said:


> Here is one old result that has it correctly
> View attachment 2486735
> 
> But it should be under GDM off. Only 2 kits could run it under GDM disabled 2T ~ so far
> I need to test it
> Dual rank as always should add +2 on tRDWR
> 
> For the exploit , tRP needs to match tRCDavg value
> and tRAS is double that value then
> tRP can be equal to highest tRCD value and tCL, but for the exploit to work 100% , it needs to be the tRCDavg value = tRP
> Else it's slower and a flat set most of the times is faster
> 
> The reboot should only happen if DF states cause cores to fully suspend and then the wakeup triggers overboost and crashes
> C-State generation doesn't suspend cores , it slows them down but they do not hibernate with it
> 
> It's something else
> Doublecheck that DF-State didn't turn itself on, or disable it by hand
> What you else can do is ask irusanovBG for the current ZenState 2.0 - to manually disable Package C6 state
> That would also turn of DF States
> Something enables them, else there is no reason why you have Overboost reboots


Well, this is much better to try lowering.. sadly I couldn't see what CCD IOD and VDDP are use him. I tried with mine values, I guess that for 1.55V I should set ProctOCT to 40, RTT_WR2, and Park 5. I think that my mistake is to have enable de DF States.. I'm gonna change it. And the C-States I've set to disabled to avoid the reboot on idle..
PS: I didn't change the TWRRD. When I tried to lower from 3 almost always I couldn't get POST. I'm gonna try DF States Off..








I read your guide about TM5 errors.. 6, 0, should be a lot of thinks, VDIMM, and the 2 Is a timeout issue, somewhere something ends too quickly


----------



## Veii

@lmfodor You didn't read the post
"Dual rank needs +2 tRDWR"
It's fascinating that you can even post that
It was on Matisse  - VDDG wouldn't matter
but 6 & 12 are PCB crashes or "not enough voltage"

Between 1.55-1.58 would be needed for it

If that doesn't fix it, then you need SCL at least one up to 4


----------



## KedarWolf




----------



## lmfodor

Veii said:


> @lmfodor You didn't read the post
> "Dual rank needs +2 tRDWR"
> It's fascinating that you can even post that
> It was on Matisse  - VDDG wouldn't matter
> but 6 & 12 are PCB crashes or "not enough voltage"
> 
> Between 1.55-1.58 would be needed for it
> 
> If that doesn't fix it, then you need SCL at least one up to 4


Hi @Veii! Yes I read it! I thought those timings were for DR. My bad.
I disabled DF States
I rise VDIMM to 1.58V
Set SCL to 4
and tRDWR to 12.
You can't say I'm not trying to lower the primaries!! I bet you've never seen so many TM5 errors together!! 6 0 12 all of it 
Do you think I need more voltage? Because errors appear to the instant in the first cycle, and test by test are increased rapidly. It must be something very obvious, or I'm trying too hard the timings

Regarding the exploit, tRP to match tRCDavg value so could I try tRP to 14 and tRAS 28.. , right?


----------



## Veii

lmfodor said:


> Hi @Veii! Yes I read it! I thought those timings were for DR. My bad.
> I disabled DF States
> I rise VDIMM to 1.58V
> Set SCL to 4
> and tRDWR to 12.
> You can't say I'm not trying to lower the primaries!! I bet you've never seen so many TM5 errors together!! 6 0 12 all of it
> Do you think I need more voltage? Because errors appear to the instant in the first cycle, and test by test are increased rapidly. It must be something very obvious, or I'm trying too hard the timings
> 
> Regarding the exploit, tRP to match tRCDavg value so could I try tRP to 14 and tRAS 28.. , right?
> View attachment 2486766


#10 says it's an read to write issue 
what about SCL 5 and tWRRD 2

You can also lift tRRD's a bit up 
4-5-16,4-10 

These settings are extreme
Looks like just a spam of 10's
Soo SCL,tRCD , tRRD+ tWTR & the two tRDWR + tWRRD

play around till you get a good combination that's fine for getting #10 away
2 you can ignore, as long as you don't have 6 or 12's , you make progress


----------



## Veii

KedarWolf said:


> View attachment 2486765


I should have double-mentioned that current Aida64 is broken








Test each of the SMUs on 6.32.5600 or 6.32.5644 BETA ~ 6.32.5700 is broken with it's EPYC fix
you should hit atleast 1380 consistently on 4.85ghz for a 12 core
A 16 core i expect near the 1500 range 

Btw i might be able to get another 16core dual CCD gimped unit
Thinking about a 5800X gimped this time - usually wanted to save for Cezanne, but i am not sure
Maybe Cezanne will be PC#3 then , as i have enough GPUs to just get a 5800X gimped

Or i ignore Cezanne and focus on Rembrandt/Lucienne mobile , and practice there fabric OC on SO_DIMMs 
Unsure about it
For sure need the Asus ProArt B550 Creator - to finally release !


----------



## mirzet1976

RosaPanteren said:


> View attachment 2486676


----------



## lmfodor

Veii said:


> #10 says it's an read to write issue
> what about SCL 5 and tWRRD 2
> 
> You can also lift tRRD's a bit up
> 4-5-16,4-10
> 
> These settings are extreme
> Looks like just a spam of 10's
> Soo SCL,tRCD , tRRD+ tWTR & the two tRDWR + tWRRD
> 
> play around till you get a good combination that's fine for getting #10 away
> 2 you can ignore, as long as you don't have 6 or 12's , you make progress


Ok


Veii said:


> I should have double-mentioned that current Aida64 is broken
> 
> 
> 
> 
> 
> 
> 
> 
> Test each of the SMUs on 6.32.5600 or 6.32.5644 BETA ~ 6.32.5700 is broken with it's EPYC fix
> you should hit atleast 1380 consistently on 4.85ghz for a 12 core
> A 16 core i expect near the 1500 range
> 
> Btw i might be able to get another 16core dual CCD gimped unit
> Thinking about a 5800X gimped this time - usually wanted to save for Cezanne, but i am not sure
> Maybe Cezanne will be PC#3 then , as i have enough GPUs to just get a 5800X gimped
> 
> Or i ignore Cezanne and focus on Rembrandt/Lucienne mobile , and practice there fabric OC on SO_DIMMs
> Unsure about it
> For sure need the Asus ProArt B550 Creator - to finally release !


Yes, definitely I should go back to several previous BIOS version..
This are my benchs.. with the "bad values"







.


----------



## Veii

mirzet1976 said:


> View attachment 2486768


Vs old 4.85 result from december
EDIT:
48.5 mulitplier * 101 BLCK = 4930 Mhz , sorry
but yes, wrong thread for such 
You can open a Ryzen 5xxx SuperPi record hunt ~ thread , if you want


Spoiler














We should not compare different CPUs on SuperPi
It's all about single core with 18W load
like come on
If we are hunting for unreal scenarios let me get up CTR with 5.2 single boost

5ghz allcore i hope is y-cruncher stable for you 
(this here is a 24/7 thread, please don't mistake it for a suicide run score posting thread)

But so far, good score~
5ghz allcore, should need no more than 1.37v


Spoiler


----------



## lmfodor

Veii said:


> #10 says it's an read to write issue
> what about SCL 5 and tWRRD 2
> 
> You can also lift tRRD's a bit up
> 4-5-16,4-10
> 
> These settings are extreme
> Looks like just a spam of 10's
> Soo SCL,tRCD , tRRD+ tWTR & the two tRDWR + tWRRD
> 
> play around till you get a good combination that's fine for getting #10 away
> 2 you can ignore, as long as you don't have 6 or 12's , you make progress


Well, I will try right now.. I hope I can lower the tWRRD to 2 and get POST.
Regarding tRRD's I should only modify them or also the tWTR? from 4-4 to 4-5 or 4-10? in that case tWTRL shoul be the same as I keep the value of tRRDL (x2)
I will try with these to see how it goes..


----------



## heptilion

Veii said:


> Please try SD, DDs @ 1-4-4-1-5-5 and drop tWTR to 3-8
> Just Aida64 confirm it's faster
> 
> If not , ignore it and try 1-4-3-1-5-4 with tRDWR to 10
> See if you can even boot that up
> 
> Don't forget to make profiles, as these things easily can result in a full post refuse
> If tRDWR at 10 is not stable at all under your current 4-6,4-12 tRRD, tWTR (with these SD, DDs)
> Then give 1-5-4-1-7-6 a shot @ tRRD 5-7-20-5-14 (it would lower perf, but the result has to be nearly equal because of the lower tRDWR ~ which gives a big perf jump , if overlapping is synced correctly)
> 
> 1.48v is expected haha, good job btw
> Set looks exemplary
> * tWRWR is always the bigger value
> ** wish we could drop tRRD_S to 3, then i could give you something more harsh


Both red highlighted didn't post 

But i can run TRDWR at 10 by itself but this didnt change my aida latency.

I tried running flat cl14 with 1.56dram but was getting a lot of errors so didn't want to increase more because wasn't sure what RTT park to use.


----------



## Veii

heptilion said:


> was getting a lot of errors so didn't want to increase more because wasn't sure what RTT park to use.


Lots of errors sadly says nothing 
Your RTTs are fine. It's not RTT_PARK RZQ/1 
3 is fully fine


----------



## heptilion

Veii said:


> Lots of errors sadly says nothing
> Your RTTs are fine. It's not RTT_PARK RZQ/1
> 3 is fully fine


Good point. This is with 1.59dram voltage


----------



## Mastakony

My settings in GDM enabled
Could help.....


----------



## lmfodor

Veii said:


> Please write with linebreaks (shift+enter)
> Do you know who gives it to igor or who spread it
> View attachment 2486734
> 
> Both of these can not work , it's uneven
> 1-5-4-1-7-6 is for 8gb dimms not 16gb
> Maaybe 1-4-3-1-6-5 could work , maybe
> Lower values are "weaker" not faster
> 
> I would like to know who gave this to igor
> as it should be 14-8-16-*12-*24-36 not 14
> Same for the set people got from Buildzoid the 14-8-15-14
> Technically it's correct and it looks faster while using less voltage ~ it does work "halfway"
> But that's not the correct exploit , it should be used differently
> Here is one old result that has it correctly
> View attachment 2486735
> 
> But it should be under GDM off. Only 2 kits could run it under GDM disabled 2T ~ so far
> I need to test it
> Dual rank as always should add +2 on tRDWR
> 
> For the exploit , tRP needs to match tRCDavg value
> and tRAS is double that value then
> tRP can be equal to highest tRCD value and tCL, but for the exploit to work 100% , it needs to be the tRCDavg value = tRP
> Else it's slower and a flat set most of the times is faster
> 
> The reboot should only happen if DF states cause cores to fully suspend and then the wakeup triggers overboost and crashes
> C-State generation doesn't suspend cores , it slows them down but they do not hibernate with it
> 
> It's something else
> Doublecheck that DF-State didn't turn itself on, or disable it by hand
> What you else can do is ask irusanovBG for the current ZenState 2.0 - to manually disable Package C6 state
> That would also turn of DF States
> Something enables them, else there is no reason why you have Overboost reboots


@Veii, tried a lot but I was unable to stop the TM5 errors with my previous timings. So I took your suggestion over the Igor's timings and at least until TM5 cycle 3 I had no errors! Much better.. so now I guess I should rise the SCL to 4 or 5, and increase a bit TWRRD from 1 to 2 or 3, TRRD and tWTR from 4-4/4-8 to 4-6/4-12 and with the tRDWR I'm confuse, I know I should add 2, and I starting from 10, so I'm at 12..I don't know is I should increase for instance to 13..
But much much better 










I also kept thinking about what you were saying about the exploit. The truth is that to be in 1.57V VDIMM you should achieve 14-14-14.. try hard enough but don't make it. With that data you send me, I started getting closer. I think I'm one step behind. But I'm coming!


----------



## craxton

Veii said:


> See if tCKE 12 is stable


Not at all, only thing changed was tCKE 11 to 12 and 3 errors in HCI 
within the first 30 minutes, tried upping vdimm voltage but no give.

but tCKE 11 actually stayed working at normal voltages i had already preset
prior to changing to 12.




Veii said:


> As for boost voltage, don't worry going to 1.52 for 1 core


this is something i was curious about, even mentioning 1.35 being ok for sustained loads
makes me feel quite a bit better and not so stressed about what im running now, with that being said

below ive added a hwinfo shot of TM5 running for around an hour or so
(passed was playing a game on droid and not paying attention to grab a shot)









ill assume this would be ok ? (70c was a momentary stress with wide open ppt/edc/tdc values.)




Veii said:


> There is a huge book of information to this, half of which 1usmus knows way more about


where might one find this book, as trying to get 1usmus to respond is rather difficult
since hes busy with CTR and such, as well as im not one well known with Ryzen/IMC overclocking.


----------



## nada324

Finnaly, @Veii, i just only get error #11,

Tried changing cad bus from 40-20-30-20 to 60-20-30-20 no luck at all, also tried 30-20-30-20, tfaw and tras seems fine.
Trfc used your mini calculator.
Tried little more vdimm from 1.5 to 1.51 with no change at all.
Not using setup timings for now.

Ignore UCLK, seems bugged, also FCLK and IOD CCD voltages (Tried 4000mhz xmp but whea hehe) forgot later to get them back.


----------



## TimeDrapery

@Veii

Okay, GDM is off and I'm stability testing my slightly tightened set now...



Spoiler


----------



## Veii

nada324 said:


> Finnaly, @Veii, i just only get error #11,
> 
> Tried changing cad bus from 40-20-30-20 to 60-20-30-20 no luck at all, also tried 30-20-30-20, tfaw and tras seems fine.
> Trfc used your mini calculator.
> Tried little more vdimm from 1.5 to 1.51 with no change at all.
> Not using setup timings for now.
> 
> Ignore UCLK, seems bugged, also FCLK and IOD CCD voltages (Tried 4000mhz xmp but whea hehe) forgot later to get them back.
> View attachment 2486794


I don't think it's "randomly bugged"

It clearly shows that the board loads a 1800 FCLK strap but goes to 2:1 mode because MCLK is not 1800 but 1900
Good job on the memory , nearly. TM5 should stay stable even on 2:1 mode
But you should work with RTT_NOM for #11 or #1
Too strong RTT_NOM (lower divider = higher value) will help against #1's
But it can turn them into 11's

Didn't pass the first cycle , there are many many more errors that can come the first 6 cycles
But good job on getting 1-5-4-1-7-6 to post
Sadly it's not beneficial on it's current state.
It should help to lower tRDWR lower, but you have a target of 7.5 , or up-rounded "8"
Give it +1 because GDM is "one lower than tCL", soo your target is 8.5.
Oke no it's nearly fine, but the SD, DDs currently do nothing for you

Their target is to "help" lowering tRDWR
They won't break the rule of tRCDRD/2 = tRDWR (single rank, or +2 for DR)
But if you add in tWRRD of 3 ~ you maaybe can run 8-3 there
IF we end up only at this little #11

But first resolve that.
See if getting RTT_NOM back to /7 will help you
You don't use "much voltage" at all, there is no need to go down to /6
/6 should be used near i guess 1.62v
/5 should be used around 1.69-1.70v.
Was fooling with it today , and another drop was needed around 1.68-1.69v
Else /5 is fine
For you , clearly /7 is sufficient ~ beyond 1.48v but bellow 1.6v

Oh i have to note, that your tRFC is "off"
At least tWR and tRTP around it
294 maybe was created on a math with tRC 49 ~ IF tWR is to believe 
tRTP 8 is wrong at any point
Go for 270-X-X tWR 12 tRTP 6, or go for 315-X-X but increase tWR to 14 and tRTP to 7
I suggest to do the slower tedious step and be sure everything is stable first

Oh else congrats on 15-15-15, nearly 
Keep trying~


----------



## mongoled

Veii said:


> Still saddens. Really sorry about the dimms
> Sadly the sacrifice didn't lead to the result, as it happened "randomly"
> Only now we kind of have an idea what it was. Before nearly frying my own kit too haha.
> Did you get out of the financial situation decently ?
> Anything i can do to help , except sending you a kit ~ as you are too far away 🙁


Nothing for you to be sorry about, its not like anybody knew!

I RMA'd the RAM, just left with the guilt having found out later that it was me who killed the RAM using RttPark set at RZQ/1



Veii said:


> Eh, it's borderline
> RL bothers me more , than just the repetitive answers here.
> Don't mind it much. The end goal is to push the bar a bit higher.
> 50.2ns is what people get. Soo identical to the old 50.1ns result
> Now you have to go sub 50ns
> 
> I give myself a bit of time off from here, soo it's fine
> Thank you for thinking about me


Well you are a extremely valuable member of this community, I'm pretty sure you are single handidly bringing most of the traffic to OC.net, so many peeps are looking for the "Memory God" !

 

Ahhh sub 50ns with the stability we like to have is not happening at this current time, that would probably need a FCLK > 2200 and 2067 is the limit (WHEA warnings) of the CPU I have and thats when using Windows 1909, otherwise 1900 is the max on anything after 1909 ....

Been doing my best to see if I can at least get a stable 4133/2067 across all applications, but its looking to be a bridge too far.

From the time ive spent so far, looks to be stable in almost everything I throw at it, but its boaderline stable, which means any there will always be doubt in my mind about what is the cause of the crash.

Sidenote: Is it normal to get some audio glitches when running at 100% load, glitches being occasional crackling/popping sounds


----------



## Flash1228

Veii said:


> They won't break the rule of tRCDRD/2 = tRDWR (single rank, or +2 for DR)


Does +2 apply to 4 SR sticks? Also, do you still do -2 for Micron and then just ignore the +2?

It's possible I'm completing misunderstanding this. I'm just trying to figure out where the -2 for Micron fits into determining tRDWR.


----------



## Oversemper

Veii said:


> Its the link between IO-Die to Chipset, these PCIe 4.0 lanes cause issues
> If you have AMD PBS or maybe find it somewhere in the bios
> Undervolt the X570 chipset slightly - tiny bit like 5-10mV less
> And drop it to PCIe 3.0
> 
> The X16 slot from the CPU will remain at 4.0 x16 speeds
> I can see that a 6900 (XTE) will require the higher bandwidth, but FCLK at least till 1900 should be doable without any PCIe 4.0 conflicts
> After 2000+ you start to see them
> 
> if you can't drop the chipset lanes because of ~reasons~
> then give VDDG IOD a bit higher voltage (less than 1150 please)
> And give VDDG CCD a bit higher voltage (less than 1050 please)
> 
> Overall , share more information and a ZenTimings screenshot. We are guessing blindly here


@Veii, thank you very much for the input! I've managed to do the same "PCI 3.0 era" RAM overclock (3733 16-19-16-36 1T 1.35v) for PCI 4.0 GPU and my way to make motherboard POST above IF of 1633Mhz was kinda unexplainable and lucky for me. It was like this:

(ROG Strix X570-F Gaming, bios stable release 3603 AGESA V2 PI 1.2.0.1 Patch A)
-do bios reset, reflash, reset again, everything default auto, RAM in 2400 mode, IF 1200 MHz;
-enable XMP 3200, IF 1600 MHz, SoC voltage auto-set to 1.083v;
-booted alright;
now my original actions which led to a unPOSTable board:
-XMP to MANUAL, everything auto, RAM to 3266, IF to 1633;
-booted alright, SoC was auto-set to 1.1v (*remember that value!*);
-RAM to 3333, IF to 1666, everything left auto;
-DID NOT POST, clear CMOS to revive;
and now my kinda "lucky" actions which let me to go beyond IF of 1633 MHz:
-do bios reset, reflash, reset again, everything default auto, RAM in 2400 mode, IF 1200 MHz;
-enable XMP 3200, IF 1600 MHz, SoC voltage auto-set to 1.083v;
-*leave XMP be*, everything auto, RAM to 3266, IF to 1633;
-booted alright, SoC was auto-set to 1.1v;
-RAM to 3333, IF to 1666, *SoC manually to 1.1v*, *forgot about XMP being left (XMP timings 16-18-18-36-72)*;
-it BOOTed alright!
Then I thought that it was all by the grace of 1.1.v SoC and changed XMP to manual which set all timings to auto and guess what! It did not POST!
-cleared CMOS;
-RAM to 3333, IF to 1666, back to "lucky" XMP timings, SoC manually to 1.1v;
-It BOOTed alright!
-Now changing RAM and IF up to 3733 and 1866 with SoC 1.1 and XMP timings On and everything boots alright!

So, for me, after going for a PCI 4.0 card it was two things which did not let me go beyond IF of 1633:
-SoC auto voltage which I had to manually set to 1.1.v;
-primary auto timings which I had to set (either via enabling XMP or manually) to 16-18-18-36-72.

I'm still testing 3733 16-19-16-36 1T 1.35v for stability but it looks like it works well just like with previous PCI 3.0 GPU. No stability issues and no WHEA errors. The only things different from the "PCI 3.0 era" are: SoC from 1.05 to 1.1v; VDDG IOD/CCD both from 0.975 to 1.05; CLDO VDDP from 0.875 to 0.950. Other than that, everything is just like it was for PCI 3.0 GPU. I'm glad that I also do not seem to have USB connectivity issues which I red a lot about.


----------



## craxton

@Veii upon further stress testing with 1usmus preset,
errors 9, 11, 13 rose up with 6 cycles. (tCKE 11 where as tCKE 12 had 27 errors within an hour.)

going to check and see what errors these are then do some more testing.. just thought id
share that errors indeed rose aboutz

(EDIT) scratch that, tests were not valid, tRFC 1-2-4 were all default? which do NOT in any
way go side-by-side with the frequency i have currently. 

unsure why my b550 gaming edge board did this, but it did. id didnt fail to boot either?
also, FOUND out that there is a "reading" inside bios (on b550 gaming edge wifi) for
CPU VDDP but reads N/A atm. so, my guess is your bios feature unlocking trick mentioned sometime back,
would have worked if i would have tested/tried it. 

anyhow, off to retest/redownload the normal config so i know for sure what errors are what.


----------



## lmfodor

Veii said:


> I do think people need to have access to more than one google timings calculator.
> For example Ramad's
> 
> Too many people share and use exploit timings, then maybe it doesn't work on their set (RRD, WTR, tRFC , tWR)
> and stay clueless as to why it doesn't work or doesn't perform ~ same goes for reviewers out there who share these broken sets
> 
> We should get some baseline calculator following JEDEC rules
> I see too many exotic sets and many users don't really have any clue why they use it.
> 
> Flat timings perform better, unless the exploit ones are correctly in sync.
> People see them as "easy to run" and just use them - without putting work in actually lowering primaries (tRCD)
> At this point close to everyone here should be able to run a flat CL14-14 set @ 3800 ~ with all the information that's out there in this thread
> Later fix RTTs and step up to 3800C13-13-13 in the range of 1.64-1.68v
> if frequency can't be pushed higher to for example 4000C14-14-14 or 4200C15-15-15
> 
> Don't focus your time on exploits when you aren't even close to 3800CL14-14-14
> Just as a suggestion and rant~


I kept thinking about what you said Veii, it's very true. There is a lot of information, for the newest it takes a bit to manage some relationships. But I know I'm going to make it! in fact last night I tried it .. but TM5 gave me countless errors. I think, and maybe I'm wrong, that to achieve it I would need more than 1.6V and I also don't know more about IOD and CCD ... and about the timings, more or less it will be a matter of loosing some more, calculating the tRFCs and then a good combination of RTT and CadBus. But I don't know why I see that the key is to increase the voltage. maybe with 1.57 not reach. Thank you as always for your great help and contribution to all OCN members


Sent from my iPhone using Tapatalk Pro


----------



## craxton

Considering im unsure how to post this from another section, this was made by Veii a few months back (8 or so it says)

this will HELP ALL who are trying, are close to stable but not 100% stable

copied and pasted, again this was wrote by @Veii (if you mind me copy/pasting this, simply lmk and ill remove asap)
unsure if the inital data was conducted only by veii, but none the less, credit where its due has been processed.

(will be using this myself, make a bookmark of it new comers itll come in handy quite a bit)


Spoiler

tCL 16 up to IC & every 4 steps or 200Mhz +1 tCL
tRCD = tCL +2
tRP = tRCD
tRAS = tCL + tRCD
tRC = tRAS+tRP
tRFC = (0.35*(MT/s /2)) <- JEDEC, or my method ((tCLns*tRC)*MT/s)/2000.
tFAW = 8* tRRD_S. SR= 4-6 . . DR=6-8
tWR = tRCD-tRAS <- SR, double (*2) for DR
tRTP = tWR/2
tWTR_ = 4-12 SR , 6-16 DR
tRDWR = tRCD/2+2, tWRRD=1
Stable
Spoiler

tCL manual input, user should have run Failsafe first
tRCD = tCL +2
tRP = tRCD
*tRAS* = tCL+tWR+4
tRC = tRP+tRAS
tRFC = *8** tRCns
tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
*tWR* = tRTP*2 ~ SR, *4 for DR
tRTP = use tRFC multiplier = always 8
tWTR_ = 4-12 SR , 5-14 DR
tRDWR = tRCD/2+1, tWRRD=tRCD/4, round down
Fast
Spoiler

tCL manual input, round up if GDM is enabled
tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
*tRCD_WR* = ^ _RD-2
tRP = tRCD_RD+tRCD_WR / 2 = round up
tRAS = tCL+tWR+4
*tRC* = tRCD_WR+tWR+tCWL+4
*tRFC* = tCL/2 * tRCns
tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
tWR = tRTP*2 ~ SR, *4 for DR
tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
tWTR_S = tRRD_S
*tWTR_L* = tRRD_L * 2
tRDWR = tRCD_RD/2 + 1, tWRRD=tRCDavg / 4, round down
Extreme
Spoiler

tCL manual input, round up if GDM is enabled
tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
tRCD_WR = ^ _RD*-4*
tRP = tRCD_RD+tRCD_WR / 2 = round up
tRAS = tCL+tWR+4
tRC = tRCD_WR+tWR+tCWL+4
tRFC = *6 ** tRCns
tFAW = 4* tRRD_S. SR= 4-4 . .* DR=*4-6
tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
tWR = tRTP*2 ~ SR, *4 for DR
tWTR_S = tRRD_S
tWTR_L = tRRD*_S * 2*
tRDWR = tRCD_RD/2, *tWRRD=*4*SCL, round down


----------



## TimeDrapery

Spoiler: General






Dollar said:


> If anyone is interested I found an amazing review by Reous which tests the performance benefit of tightening each timing. Why bother running some timings at the bleeding edge of stability when it doesn't really increase performance much?
> 
> 
> 
> https://www.hardwareluxx.de/communi...fluss-auf-spiele-und-anwendungen-amd.1269156/





Veii said:


> You go step by step
> 
> Doing too many changes, puts you in a rabbit hole situation
> 
> Where you just don't know where you've messed up
> 
> Increasing frequency , increasing resistance, changing procODT
> 
> all can lead to a startover with timings creation
> 
> Soo you lower stuff step by step and see where it fails
> 
> after all every kit is unique - only the "baseline" is calculable
> 
> Tightening it more is from kit to kit unique , and even from the same model number unique








Spoiler: Benchmarking






Veii said:


> The benchmark [#y-cruncher], will end after all tests are done - but it's considerable to loop it twice at least





Veii said:


> SiSandra is a valid benchmark to notice timing differences ^^'








Spoiler: Stability Testing






Keith Myers said:


> In the configuration setup there is a toggle for "stop on error" But if no errors found, it [#y-cruncher] will loop continuously until you stop it.





Veii said:


> It [#y-cruncher] behaves very similar to LinpackXtreme
> 
> It will loop forever
> 
> A stresstest after all





Veii said:


> Just test everything  [#y-cruncher]
> 
> All of the tests use different instruction sets and so applied current voltage will differ
> 
> You want to run stresstest mode and select all tests
> 
> Time to pass, are results times ~ usually it takes 2-3min each test for about 8 tests
> 
> Passing two times the whole set of tests is usually enough, but likely we can optimize that in the future better
> 
> First 3 tests will always fail if there is an issue with fabric clock
> 
> Some ryzen chips fail that on stock, but usually non should fail this





rares495 said:


> Error 11 seems to be related to timings. [#TM5]





Veii said:


> @pikmin define passed
> 
> 6 rounds or 20 rounds [#TM5]
> 
> some errors like bad tRFC appears only after 19 rounds - about 1:30h exactly before TM5 20 rounds end
> 
> Another good testing tool is passing y-cruncher the first 3 tests couple of times
> 
> As they will fail when the memory controller fails
> 
> ^ which are then more voltage related by still go hand in hand with memory OC





Veii said:


> EDIT:
> 
> You run SerJ's config on TM5
> 
> Results on that one don't matter
> 
> What you want is the 1usmus_v3 config 20 rounds, which is 1:30h for 16GB or 3h for 32GB
> 
> I've attached my TM on it, if you don't want to search, but yes - you load the wrong config for the test








Spoiler: Voltages






rares495 said:


> VDDG should be at least 50mV lower than the SOC voltage (which goes up to 1.1V "safely") => max VDDG = 1.050V





2600ryzen said:


> found GDM needed 0.01v/0.02v more DRAM voltage than 2t for some reason, if GDM is throwing errors in testmem5 then that's what's probably caused it to benchmark worse too.





2600ryzen said:


> Ryzen master shows the correct SOC/VDDG/VDDP voltages, if you set the SOC/VDD voltages under the AMB CBS/Overclocking menu in bios. I have to have my motherboard SOC voltage control on auto for that to work though.





Veii said:


> Anyways, it's a precharge delay issue, on a small burst test
> 
> If 1.53v doesn't resolve that, you rly have to change timings a bit
> 
> EDIT: Having low tRP needs higher voltage soo current remains a bit





Veii said:


> VDDP might be uselessly that high , could try cutting 25mV on it too ~ might be even 50mV away
> 
> As 950mV cLDO_VDDP, 1025mV cLODO_VDDG and same 1.1v vSOC
> 
> if VDDP is too low, your procODT is a bit too high
> 
> work with CAD_BUS against it to fix it - the first value





Veii said:


> Error test 10 is under a simple test size 8mb, it's a burst test / mostly voltage related, more delay related on cell precharge
> 
> Test 11 error is a normal delay for 16mb block size, this is rather timings related
> 
> I can imagine it's copy, error, read error, copy error - what happened here
> 
> tRP is either to low, tWR too low or you lowered vDIMM voltage
> 
> anyhow, somewhere you choke on a burst write and read test
> 
> But it's not a chargeback error, else test 9 would error with a blocksize of 4mb
> 
> (that is rather a SOC voltage or too low vDIMM error)
> 
> Error 6 and 12 belong to the memory controller
> 
> which come together, first error 6 size 1mb that is initialization error , either 4-5 times error 6=BSOD or 6,12
> 
> Error on test 12 is blocksize 32mb error
> 
> Very often just resistance choke, either by too low vSOC or too high procODT/cad_BUS
> 
> rly depends on the amount of errors followed one after another
> 
> This current one is more a burst test error, which is either delay or voltage related
> 
> mostly precharge delay, because of error 11 which is more a writeback error after test 10
> 
> EDIT:
> 
> As it either is delay or tRP/voltage related - try to push tWRRD to 3 instead of two
> 
> Or put tRP higher





Veii said:


> Can't say at what point Samsung B-dies require maxmem , but it should be near that value
> 
> afterwards it needs to drop to 2gb per IC - in order to use voltages like 1.6 or 1.72v
> 
> an architectural flaw on b-dies
> 
> Don't entirely know 20nm degradation point, except 1.5v is known as the widespread JEDEC max spec for 24/7 operation on this nm nodesize
> 
> haven't had a dead memory kit so far to say what's absolute max
> 
> But it's known that near 1.56-1.58v it will require maxmem 4096mb in order to even post to windows





Veii said:


> You are at 3800MT/s
> 
> CL15 is no joke on this speed
> 
> Some need 1.56v on 3600MT/s to hit CL14
> 
> 1.5v on very good kits can run 3800CL14
> 
> not unexpected to need 1.48v for very low tRFC and low timings
> 
> 1.46v is about the sweetspot for bad and good b-dies, 1.48v only for good binns of b-dies
> 
> the bad ones don't like over 1.46v





RonLazer said:


> Sorry to be clear this is for solving memory holes, not issues with FCLK not posting. The only suggestion I have on that front is to try booting at 1867MHz, setting 1.15V SOC and 1.95V PLL (might be called 1P8 if you have an MSI board) and rebooting (still at 1867MHz) then setting 1900MHz FCLK and rebooting. This is because some voltages seem to be modified later in the boot process than the FCLK clock is set, so I always modify voltages THEN set FCLK.








Spoiler: Timings






Spoiler






Ramad said:


> Some of you have been asking for the spreadsheet that I use to calculate timings. I made it more user friendly for you with 4 input fields. You can fill the first 3 fields (1-3) and ignore the fourth field if you don't want to use tRC_Page option in the BIOS (set to 0 in the BIOS).
> 
> How to use:
> 
> There are 4 fields that can be used, the rest of the spreadsheet is locked, to prevent mistyping that can lead to miscalculating. The 4 input fields that can be used are colored light green and are marked Input 1 to Input 4.
> 
> Input 1: in MT/s is used to calculate the required primary and subtimings.
> 
> Input 2: in MT/s is used to calculate IMC timings.
> 
> Input 3: in MT/s is used to calculate tRFC, tRFC/2 and tRFC/4 timings.
> 
> Input 4: chose 200, 300, 400, 500, 600 or 700 to calculate tRC_PAGE timing.
> 
> Example:
> 
> I want to run my RAM at 3800MT/s and want tighter timings than default 380MT/s timings. I choose to use 2133MT/s or 2400MT/s...etc. timings for my RAM that is to run at 3800MT/s. This is how it's done:
> 
> Input 1: Write 2133
> Input 2: Write 3800
> Input 3: Write 3800
> Input 4: Write 200 (that is 200K). You don't have to fil this field if you don't want to activate tRC_PAGE function in the BIOS, 0 in the BIOS means that tRC_PAGE is deactivated.
> The spreadsheet will display the following result :
> 
> 2486942
> 
> My RAM dies have a density of 8Gb (gigabit), so I will be using 8Gb tRFC timings and 1KB values for tRRD_S, tRRD_L and tFAW.
> 
> Rounding up:
> 
> The calculated timings must be rounded up, i.e. 3.04CK = 4CK, 13.75CK = 14CK and 5.5 = 6CK.
> 
> IMC timings:
> 
> These are based on my experience with Zen and Zen+, your IMC may be able to tolerate tighter timings or require looser timings, that's up to the quality of the silicone.
> 
> tRC_PAGE:
> 
> AMD provides 2 methods to calculate tRC_PAGE:
> 
> Approximation: tRC_PAGE = tMAW/MAC
> 
> Exact: tRC_PAGE = (tMAW - tRFC*(tMAW/tREFI))/MAC
> 
> The results of the calculations above will be in [ns] that is required to be converted to clock cycles.
> 
> Note:
> 
> tMAW = 64ms.
> 
> tREFI = 7.8us.
> 
> MAC: number of accessible rows.
> 
> I hope that find this tool useful.
> 
> Link: DDR4 Timings for AMD ZEN
> 
> (SHA256: F2A6B863109FAD9D2A2F75A5F209D4B12FB6B230C55A5A45A349EE5A469CBA00)





Veii said:


> Yes, this tRFC was not possible he got errors - not even with factoring in tSTAG to lower it, it was far to low and needs tRFC 40 at least
> 
> or minimum 42, 44 was far too high for it ~ 240 works on lower timings but not on this set
> 
> tRFC 240 would be 126.3157895ns with tRC 40
> 
> It would make more sense to use something like this set:
> 
> Where 140ns update time is less harsh to the chips, than going <130ns update cycle
> 
> EDIT:
> 
> You can optionally use that for 32gb Dimms, or also go even further down to tRAS 26
> 
> - but tBL 4 won't work with this set, it's based on tBL 2
> 
> You will need to go tWR 10 for that in order to get tRAS formular right
> 
> And in order to go tWR 10, it needs to be tRAS-tRCD which works only with tRCD RD 6 + tCL 12
> 
> tRCD RD 8, WR 14 results in 12 average
> 
> 26 tRAS - 12 tRCD = 12 tWR not 10 tWR
> 
> and tRRD_S+tWTR_S = 8 tWR not 10
> 
> It's complicated
> 
> If you push tWTR_S/L as 6-6 , this formula might work to run tRAS 26
> 
> Else we need bios-mods allowing to use tWR 8 :ninja:





2600ryzen said:


> TRTP needs to be at least half of TWR on my kit or it wont post. Try TRPT of 10 with TWR of 20, or 8/16.





Veii said:


> Two things
> 
> get tRFC2 and tRFC4 correct because you use GDM
> 
> soo tCKE will work too
> 
> if you already did , then try to scale up tCKE to 6 slowly
> 
> and even if at 6 it doesn't do anything
> 
> try tRRDL on 5
> 
> Unsure about tWTRL on 8, 3-10 would it be or 4-12





Veii said:


> Your optimal tWR is between 10,12,14, at least tRAS-tRCD is 14 or 16
> 
> Yes 16 can run well but try to change for now tWRRD to 3
> 
> If that doesn't work it's tWR to 16 try - if it doesn't post, you have to keep it 14 or lower
> 
> if you use 14, better use tRTP 8 not 6
> 
> Else tWR 12





Veii said:


> tWR should be in sync with tRFC if possible , if not possible at least tRTP has to be
> 
> Preferable to keep tWR in sync and see if how tRTP behaves, if 6 is possible else just half of current tWR
> 
> I am pretty sure with tSTAG inside the tRFC calculation , it will show what of both has to be a perfect half
> 
> But i have the suspension, it doesn't matter here that much
> 
> Because in order for it to matter a lot, timings have to be turned into ns and the math being done
> 
> there is too much variability on whole virtual values to predict perfect results
> 
> At worst the board does autocorrect anyways, but try to keep it a divider if you can
> 
> It's no "has to be" rule - it's a strong recommendation for tWR to be a divider of tRFC
> 
> The less wasted latency you have across the remain timings, the less it would matter if it's a tiny tiny bit offsync ~ as it's corrected anyways





Veii said:


> tWR is optimally near the 8ns which is 8*MT/s divided by 2000
> 
> (8*3734)/2000= 14.936ns, 15 would be the optimal - BUT
> 
> according to 1usmus's research is lower tWR still beneficial
> 
> I'm doubting that formular a bit as write recovery depends on more than just running frequeuncy
> 
> It depends on tCL and tRTP , but i have no perfect formular for it - 1usmus knows more
> 
> Lowest tWR=
> 
> tRRDS+tWTRS
> 
> Highest tWR=
> 
> tCL + tRTP
> 
> Alternative Option:
> 
> tRAS-tRCD (Biggest)
> 
> Recommended is value between lowest tWR
> 
> And Alt. - one in between, should be mostly lowest tWR +2, or Alt tWR -2
> 
> tWR has to be an even value, but as there is more to it than 8ns of x Frequency, use the math formular above only to orient yourself where you want to be
> 
> For 3200MT/s for example 8*3200/2000=12.8 and tWR 12 runs wonderfully there
> 
> Divided by 2000 is for turning virtual values into nanosecounds
> 
> tCL 16 = 8.57ns
> 
> ((8,57*3734)/2000)= 16,00019
> 
> To be more accurate, tCL 16 = 8.56989823245849ns
> 
> Soo you can see why boards do autocorrect
> 
> Starting with 3734MT/s being more like 3733,333336 - which is a fundamental error in getting perfect timings
> 
> The DDR frequency is already rounded down which causes math errors, and tRFC accuracy does suffer from that
> 
> tRDWR & tWRRD has no perfect rule, only one that is trial and error
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Overclock.net
> 
> 
> A forum community dedicated to overclocking enthusiasts and testing the limits of computing. Come join the discussion about computing, builds, collections, displays, models, styles, scales, specifications, reviews, accessories, classifieds, and more!
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> It's flawed and depends on dual or single ranked, but it's functional and usable
> 
> We noticed tCWL = tCL , for this ruleset
> 
> If it's lower, it will prevent low tRDWR to post





Veii said:


> 1-1-1 1-1-1 was an alternative when you use awkward timings, it does lower performance but is more stable





Veii said:


> SLC you have to drop to at least 3, tRDWR might be workable with
> 
> and then maybe something 16-14-14-16 can run in the future with lower tRAS and tRC
> 
> You need to go methodological on it
> 
> First is lowering SLC and testing how low you can get tRFC before the kits start to choke by too high latency from the main 3 timings (tCL,tRCD,tRP)
> 
> Later you lower tRCD and at the same time always finetune tRDWR & tWRRD
> 
> Then you check how low tRP can go with your voltage and at best and last try if you can lower tCL
> 
> tCL goes at last





Veii said:


> tRFC is lower than usual because tRC is already -2
> 
> -4 is about the max i've seen, but i didn't see a testing rabbit to explore what it negatively affects by going that low in tRC
> 
> surely messes up something
> 
> -2 on dual rank is hard, but on single rank kits it's easy to do and let's you use very low tRFC
> 
> but tRAS has to stay as a clean transition or on slow ICs with (like you mentioned) added artificial delay
> 
> Although, just increasing tRP instead tRAS does work too - at the end both will influence tRC
> 
> * depends really if recharge after write was too slow or just globally everything was too harsh soo tRP bump would help





Veii said:


> low tRAS only results in a wait-for-command-completion-before-action scenario
> 
> It does nothing than just slow down things and at worst error out memory tests for mysterious reasons
> 
> Appearing that often, makes me think it's some guide somewhere
> 
> tRAS can only be lower than tCL+tRTC if you abuse memory heterogeneity ~ which i doubt many read
> 
> And that tCL+tWR+tBL method for it, would nearly always cause trouble if the rest is not as tight as possible





Veii said:


> Seen this issue today for the 3rd time already
> 
> minimum tRAS for you is not 28 - it's far to low
> 
> 30 or 32 is your value
> 
> tRC doesn't have to be a clean perfect math, but tRAS has to be, else it waits the whole time for commands to pass
> 
> Put tRAS to 30 and at best & increase tWR to 14
> 
> only memory voltage is preventing you to boot CL15 , but you can try later adding tWRRD 3 if it changes stability
> 
> But it will lower timing efficiency
> 
> Else next step is lowering SCL to 3
> 
> EDIT:
> 
> Will this post under 1.48vDIMM








Spoiler: Timing Sets






Spoiler: Failsafe



tCL 16 up to IC & every 4 steps or 200Mhz +1 tCL
tRCD = tCL +2
tRP = tRCD
tRAS = tCL + tRCD
tRC = tRAS+tRP
tRFC = (0.35*(MT/s /2)) <- JEDEC, or my method ((tCLns*tRC)*MT/s)/2000.
tFAW = 8* tRRD_S. SR= 4-6 . . DR=6-8
tWR = tRCD-tRAS <- SR, double (*2) for DR
tRTP = tWR/2
tWTR_ = 4-12 SR , 6-16 DR
tRDWR = tRCD/2+2, tWRRD=1





Spoiler: Stable



tCL manual input, user should have run _Failsafe_ first
tRCD = tCL +2
tRP = tRCD
tRAS = tCL+tWR+4
tRC = tRP+tRAS
tRFC = 8* tRCns
tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
tWR = tRTP*2 ~ SR, *4 for DR
tRTP = use tRFC multiplier = always 8
tWTR_ = 4-12 SR , 5-14 DR
tRDWR = tRCD/2+1, tWRRD=tRCD/4, round down





Spoiler: Fast



tCL manual input, round up if GDM is enabled
tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
tRCD_WR = ^ _RD-2
tRP = tRCD_RD+tRCD_WR / 2 = round up
tRAS = tCL+tWR+4
tRC = tRCD_WR+tWR+tCWL+4
tRFC = tCL/2 * tRCns
tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
tWR = tRTP*2 ~ SR, *4 for DR
tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
tWTR_S = tRRD_S
tWTR_L = tRRD_L * 2
tRDWR = tRCD_RD/2 + 1
*tWRRD* = *(tRCD_RD + tRCD_WR) ÷ 4* (round down)





Spoiler: Extreme



*tCL* ---> lowest stable value (round up to the next highest even value if GDM is set to _Enabled_)
*tRCD_RD* ---> = *tCL* (if equipped with Samsung B-die, set = *tCL + 1* [*GDM* set to _Disabled_], everything not equipped with B-die, set = *tCL + 2* [or B-die with *GDM* set to _Enabled_])
*tRCD_WR* ≤ *tRCD_RD - 4*
*tRP* = *(tRCD_RD + tRCD_WR) ÷ 2* (round up)
*tRAS* = *tCL + tWR + 4
tRC* = *tRCD_WR + tWR + tCWL + 4
tRFC* = *tRC (in ns) × 6
tFAW* = *tRRD_S × 4
tRTP* = *tRFC* multiplier (round down if *GDM* is set to _Disabled_, up if *GDM* is set to _Enabled_)
*tWR* = *tRTP × 2* (_SR_); *× 4* (_DR_)
*tWTR_S* = *tRRD_S
tWTR_L* = *tRRD_S × 2
tRDWR* = *tRCD_RD ÷ 2
tWRRD*= *SCL(s) × 2* (round down)


----------



## lmfodor

craxton said:


> Considering im unsure how to post this from another section, this was made by Veii a few months back (8 or so it says)
> 
> this will HELP ALL who are trying, are close to stable but not 100% stable
> 
> copied and pasted, again this was wrote by @Veii (if you mind me copy/pasting this, simply lmk and ill remove asap)
> unsure if the inital data was conducted only by veii, but none the less, credit where its due has been processed.
> 
> (will be using this myself, make a bookmark of it new comers itll come in handy quite a bit)
> 
> 
> Spoiler
> 
> tCL 16 up to IC & every 4 steps or 200Mhz +1 tCL
> tRCD = tCL +2
> tRP = tRCD
> tRAS = tCL + tRCD
> tRC = tRAS+tRP
> tRFC = (0.35*(MT/s /2)) s)/2000.
> tFAW = 8* tRRD_S. SR= 4-6 . . DR=6-8
> tWR = tRCD-tRAS
> tRTP = tWR/2
> tWTR_ = 4-12 SR , 6-16 DR
> tRDWR = tRCD/2+2, tWRRD=1
> Stable
> Spoiler
> 
> tCL manual input, user should have run Failsafe first
> tRCD = tCL +2
> tRP = tRCD
> *tRAS* = tCL+tWR+4
> tRC = tRP+tRAS
> tRFC = *8** tRCns
> tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
> *tWR* = tRTP*2 ~ SR, *4 for DR
> tRTP = use tRFC multiplier = always 8
> tWTR_ = 4-12 SR , 5-14 DR
> tRDWR = tRCD/2+1, tWRRD=tRCD/4, round down
> Fast
> Spoiler
> 
> tCL manual input, round up if GDM is enabled
> tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
> *tRCD_WR* = ^ _RD-2
> tRP = tRCD_RD+tRCD_WR / 2 = round up
> tRAS = tCL+tWR+4
> *tRC* = tRCD_WR+tWR+tCWL+4
> *tRFC* = tCL/2 * tRCns
> tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
> tWR = tRTP*2 ~ SR, *4 for DR
> tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
> tWTR_S = tRRD_S
> *tWTR_L* = tRRD_L * 2
> tRDWR = tRCD_RD/2 + 1, tWRRD=tRCDavg / 4, round down
> Extreme
> Spoiler
> 
> tCL manual input, round up if GDM is enabled
> tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
> tRCD_WR = ^ _RD*-4*
> tRP = tRCD_RD+tRCD_WR / 2 = round up
> tRAS = tCL+tWR+4
> tRC = tRCD_WR+tWR+tCWL+4
> tRFC = *6 ** tRCns
> tFAW = 4* tRRD_S. SR= 4-4 . .* DR=*4-6
> tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
> tWR = tRTP*2 ~ SR, *4 for DR
> tWTR_S = tRRD_S
> tWTR_L = tRRD*_S * 2*
> tRDWR = tRCD_RD/2, *tWRRD=*4*SCL, round down


Great summary! It will help us a lot!! Thanks 


Sent from my iPhone using Tapatalk Pro


----------



## zGunBLADEz

lmfodor said:


> Hi! I was trying to lower the primaries and take the opportunity as a reference to copy the values from the Igors Lab review. Adapt some values, adjust, release, however I don’t see much difference with my previous values that I made with the help of @Veii where the times were looser, and it used 1.5V of VDIMM vs the new ones more adjusted to 1.55v. I must be at the limit of performance, and for the results I would stay with the previous values, due to the lower voltage and also because I did many stability tests, not so with the copy of Igor's I thought that with flat values 14-14-14 24 would be better, or maybe I should raise the tRAS to 28 and try ..
> View attachment 2486668
> 
> AIDA timings
> View attachment 2486669


everything there both results are margin of error choose the stable one call it a day if is less voltage even better you aint going to win vs the hard cap of IF
only IF you can do more than 1900 thats that


----------



## lmfodor

zGunBLADEz said:


> everything there both results are margin of error choose the stable one call it a day if is less voltage even better you aint going to win vs the hard cap of IF
> only IF you can do more than 1900 thats that


It's not really a good comparison since I never really got 3800-14-14-14. Although it managed to boot into windows, in TM5 it was full of errors. Today I spent about 6 hours reading and testing .. TM5 gave me 6 errors in the first 1usmus test and sometimes it gave me 3 zeros and 3 sixes, so reading the errors and their events from Veii's worksheet, check the SCL values, the tWRRD, then when it only had 6 continuous errors .. then it also looked for the voltage .. I got to VDIMM of 1.6 .. I followed all the rules that I could but I couldn't. It can't be that hard, I know I'm close so I'll keep reading and trying. Always with the caution of use a weak RTTs so as not to have problems with high voltage. I'll do it, it's not that easy. And of course the results of the bench that I shared are not reliable since with so many errors it must be auto correcting everything .. so I will continue another day.

I see that many achieve it with memories of 3200 or 3600, and these that are a new model 3800CL14 should be easier, but it is not! at least for me.
Sent from my iPhone using Tapatalk Pro


----------



## mongoled

lmfodor said:


> It can't be that hard......
> 
> Sent from my iPhone using Tapatalk Pro


😂😂😂

Good luck with that, I really mean it, as the reality shows that 3800/1900 using flat 14s is extremely difficult to achieve otherwise we would seen many users posting legitimate results under memory subsystem stresstests, but we dont see this!

You either need to have tremendous fortune in having hardware that can do it from the get go, or you need to start binning memory modules and CPUs and maybe even motherboards to get to those flat 14s, no amount of tweaking is going to get you there unless the hardware is capable.

The killer is tRCDRD, ive spent many hours trying, often return to it every once in the while after learning something "new" but only to have the same results, failure.

Also you need to be aware, although we have rulesets, what these dont take into account is the differenence in electrical characteristics of the PCBs that the memory modules sit on, my experience when dealing with this issue is that voltage is only going to get you so far, many times you need to reduce voltage and tweak other values such as Rtt's and drive strength values, but ofcourse this also changes depending on the frequency/timings you are aiming for.

Example 4133/2067 using flat 16s will error out using 1.52v for vDIMM but works fine using 1.47v !


----------



## lmfodor

mongoled said:


> [emoji23][emoji23][emoji23]
> 
> Good luck with that, I really mean it, as the reality shows that 3800/1900 using flat 14s is extremely difficult to achieve otherwise we would seen many users posting legitimate results under memory subsystem stresstests, but we dont see this!
> 
> You either need to have tremendous fortune in having hardware that can do it from the get go, or you need to start binning memory modules and CPUs and maybe even motherboards to get to those flat 14s, no amount of tweaking is going to get you there unless the hardware is capable.
> 
> The killer is tRCDRD, ive spent many hours trying, often return to it every once in the while after learning something "new" but only to have the same results, failure.
> 
> Also you need to be aware, although we have rulesets, what these dont take into account is the differenence in electrical characteristics of the PCBs that the memory modules sit on, my experience when dealing with this issue is that voltage is only going to get you so far, many times you need to reduce voltage and tweak other values such as Rtt's and drive strength values, but ofcourse this also changes depending on the frequency/timings you are aiming for.
> 
> Example 4133/2067 using flat 16s will error out using 1.52v for vDIMM but works fine using 1.47v !


Well yeah I'm a little tired but then Veii appears and says let's go! Anyone could do it with all the information in this forum. Also, I had an expectation about this new 380CL14 native memory, maybe it's just marketing. But I paid what would be 2 kits of some ballistixs easily. That leads me to continue. Also, I saw Igor's lab review and all the timings are there but, as Veii mentioned, some seem to be wrong. I must admit that my timings that I achieved with the help of Veii are incredible. Good bandwidth. Low latency. I should leave everything like this. He also helps me with the curve, and I have a very good PBO2 curve, the only thins is the latest BIOS that seems to have something broken. But so far I’m extremely happy with my results. 


Sent from my iPhone using Tapatalk Pro


----------



## Katana1074

Big thanks to Veii and Kedarwolf....

Ive been a long time lurker here and im only just delving into ryzen dram timings

Progress so far...


----------



## _frame_

craxton said:


> tRDWR = tRCD_RD/2, *tWRRD=*4*SCL, round down


Extreme. Maybe tWRRD=*SCL/4* ? As far as I know most used SCL = 4 and tWRRD = 1 or 3 but not 16


----------



## paih85

craxton said:


> Considering im unsure how to post this from another section, this was made by Veii a few months back (8 or so it says)
> 
> this will HELP ALL who are trying, are close to stable but not 100% stable
> 
> copied and pasted, again this was wrote by @Veii (if you mind me copy/pasting this, simply lmk and ill remove asap)
> unsure if the inital data was conducted only by veii, but none the less, credit where its due has been processed.
> 
> (will be using this myself, make a bookmark of it new comers itll come in handy quite a bit)
> 
> 
> Spoiler
> 
> tCL 16 up to IC & every 4 steps or 200Mhz +1 tCL
> tRCD = tCL +2
> tRP = tRCD
> tRAS = tCL + tRCD
> tRC = tRAS+tRP
> tRFC = (0.35*(MT/s /2)) <- JEDEC, or my method ((tCLns*tRC)*MT/s)/2000.
> tFAW = 8* tRRD_S. SR= 4-6 . . DR=6-8
> tWR = tRCD-tRAS <- SR, double (*2) for DR
> tRTP = tWR/2
> tWTR_ = 4-12 SR , 6-16 DR
> tRDWR = tRCD/2+2, tWRRD=1
> Stable
> Spoiler
> 
> tCL manual input, user should have run Failsafe first
> tRCD = tCL +2
> tRP = tRCD
> *tRAS* = tCL+tWR+4
> tRC = tRP+tRAS
> tRFC = *8** tRCns
> tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
> *tWR* = tRTP*2 ~ SR, *4 for DR
> tRTP = use tRFC multiplier = always 8
> tWTR_ = 4-12 SR , 5-14 DR
> tRDWR = tRCD/2+1, tWRRD=tRCD/4, round down
> Fast
> Spoiler
> 
> tCL manual input, round up if GDM is enabled
> tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
> *tRCD_WR* = ^ _RD-2
> tRP = tRCD_RD+tRCD_WR / 2 = round up
> tRAS = tCL+tWR+4
> *tRC* = tRCD_WR+tWR+tCWL+4
> *tRFC* = tCL/2 * tRCns
> tFAW = 4* tRRD_S. SR= 4-6 . . DR=5-7
> tWR = tRTP*2 ~ SR, *4 for DR
> tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
> tWTR_S = tRRD_S
> *tWTR_L* = tRRD_L * 2
> tRDWR = tRCD_RD/2 + 1, tWRRD=tRCDavg / 4, round down
> Extreme
> Spoiler
> 
> tCL manual input, round up if GDM is enabled
> tRCD_RD = tCL if B-die, +1 GDM off, +2 GDM on everything that's not B-die
> tRCD_WR = ^ _RD*-4*
> tRP = tRCD_RD+tRCD_WR / 2 = round up
> tRAS = tCL+tWR+4
> tRC = tRCD_WR+tWR+tCWL+4
> tRFC = *6 ** tRCns
> tFAW = 4* tRRD_S. SR= 4-4 . .* DR=*4-6
> tRTP = use tRFC multiplier ~ if GDM off round down, if GDM on round up (if 7.5 round to 8)
> tWR = tRTP*2 ~ SR, *4 for DR
> tWTR_S = tRRD_S
> tWTR_L = tRRD*_S * 2*
> tRDWR = tRCD_RD/2, *tWRRD=*4*SCL, round down


so for my DR kit 2x16gb tWR need tRTP*4 ?


----------



## TimeDrapery

Alright, I think I'm damn near finished working up a "2T/GDM Disabled" timing set... I guess we'll see once the TM5 cycles are all completed



Spoiler: Screenshots



Second to last iteration of tuning/testing for stability (passed 60× cycles of TM5 with 1usmus config file)








Current iteration of tuning/testing for stability, I'm liking the lesser temps


----------



## Ramad

Some of you have been asking for the spreadsheet that I use to calculate timings. I made it more user friendly for you with 4 input fields. You can fill the first 3 fields (1-3) and ignore the fourth field if you don't want to use tRC_Page option in the BIOS (set to 0 in the BIOS). 

*How to use: *

There are 4 fields that can be used, the rest of the spreadsheet is locked, to prevent mistyping that can lead to miscalculating. The 4 input fields that can be used are colored light green and are marked Input 1 to Input 4.

*Input 1:* in MT/s is used to calculate the required primary and subtimings. 
*Input 2:* in MT/s is used to calculate IMC timings.
*Input 3:* in MT/s is used to calculate tRFC, tRFC/2 and tRFC/4 timings.
*Input 4:* chose 200, 300, 400, 500, 600 or 700 to calculate tRC_PAGE timing.

*Example:* 
I want to run my RAM at 3800MT/s and want tighter timings than default 380MT/s timings. I choose to use 2133MT/s or 2400MT/s...etc. timings for my RAM that is to run at 3800MT/s. This is how it's done:


*Input 1:* Write *2133*
*Input 2:* Write *3800*
*Input 3:* Write *3800*
*Input 4:* Write *200 *(that is 200K). You don't have to fil this field if you don't want to activate tRC_PAGE function in the BIOS, 0 in the BIOS means that tRC_PAGE is deactivated.
The spreadsheet will display the following result : 










My RAM dies have a density of 8Gb (gigabit), so I will be using 8Gb tRFC timings and 1KB values for tRRD_S, tRRD_L and tFAW. 

*Rounding up:* 
The calculated timings must be rounded up, i.e. 3.04CK = 4CK, 13.75CK = 14CK and 5.5 = 6CK.

*IMC timings:* 
These are based on my experience with Zen and Zen+, your IMC may be able to tolerate tighter timings or require looser timings, that's up to the quality of the silicone. 

*tRC_PAGE:* 
AMD provides 2 methods to calculate tRC_PAGE:

*Approximation: tRC_PAGE = tMAW/MAC
Exact: tRC_PAGE = (tMAW - tRFC*(tMAW/tREFI))/MAC*

The results of the calculations above will be in [ns] that is required to be converted to clock cycles.

*Note:
tMAW =* 64ms.
*tREFI =* 7.8us.
*MAC:* number of accessible rows. 

I hope that find this tool useful. 

Link: DDR4 Timings for AMD ZEN
(SHA256: F2A6B863109FAD9D2A2F75A5F209D4B12FB6B230C55A5A45A349EE5A469CBA00)


----------



## BarrettDotFifty

Guys, I have an issue with TestMem5, 1usmus_v3 profile. Sometimes the test would stop (randomly) and just hangs, looks like in between the cycles. The memory is deallocated, and it says <number> mS/Gb and the current test number isn't marked blue anymore. The config seems to be stable, other tests show no erros. Anyone happen to have the same issue?


----------



## RonLazer

Ramad said:


> Some of you have been asking for the spreadsheet that I use to calculate timings. I made it more user friendly for you with 4 input fields. You can fill the first 3 fields (1-3) and ignore the fourth field if you don't want to use tRC_Page option in the BIOS (set to 0 in the BIOS). I will be adding a short "how to use" guide in this post.
> 
> Link: DDR4 Timings for AMD ZEN
> (SHA256: F2A6B863109FAD9D2A2F75A5F209D4B12FB6B230C55A5A45A349EE5A469CBA00)


It just says the sheet is protected if I try and change anything?


----------



## lmfodor

BarrettDotFifty said:


> Guys, I have an issue with TestMem5, 1usmus_v3 profile. Sometimes the test would stop (randomly) and just hangs, looks like in between the cycles. The memory is deallocated, and it says mS/Gb and the current test number isn't marked blue anymore. The config seems to be stable, other tests show no erros. Anyone happen to have the same issue?


Yes, the same things happens to me but with Anta777. I don’t know why. I installed a new copy.. because it’s the last one but sometimes it’s stop. 



Sent from my iPhone using Tapatalk Pro


----------



## weleh

mongoled said:


> 😂😂😂
> 
> Good luck with that, I really mean it, as the reality shows that 3800/1900 using flat 14s is extremely difficult to achieve otherwise we would seen many users posting legitimate results under memory subsystem stresstests, but we dont see this!
> 
> You either need to have tremendous fortune in having hardware that can do it from the get go, or you need to start binning memory modules and CPUs and maybe even motherboards to get to those flat 14s, no amount of tweaking is going to get you there unless the hardware is capable.
> 
> The killer is tRCDRD, ive spent many hours trying, often return to it every once in the while after learning something "new" but only to have the same results, failure.
> 
> Also you need to be aware, although we have rulesets, what these dont take into account is the differenence in electrical characteristics of the PCBs that the memory modules sit on, my experience when dealing with this issue is that voltage is only going to get you so far, many times you need to reduce voltage and tweak other values such as Rtt's and drive strength values, but ofcourse this also changes depending on the frequency/timings you are aiming for.
> 
> Example 4133/2067 using flat 16s will error out using 1.52v for vDIMM but works fine using 1.47v !


Everything is possible if you shove enough Volts at it.

I've been running true 1T 3800c14 (RD 14 tRP 13) since Zen 2 era, when I first got my bdie SR kit (3600c16 Dark Pros so nothing amazing).
Eventhough I agree RD is sometimes the stability killer due to IMC's ****ting themselves, doing flat 14's isn't hard.

I've helped so many people tune their ram and have never encountered an issue with running flat 14 primaries...

I've done this on Unify X, Bazooka, B450 board, Dark Hero, so many different boards...


----------



## lmfodor

weleh said:


> Everything is possible if you shove enough Volts at it.
> 
> I've been running true 1T 3800c14 (RD 14 tRP 13) since Zen 2 era, when I first got my bdie SR kit (3600c16 Dark Pros so nothing amazing).
> Eventhough I agree RD is sometimes the stability killer due to IMC's ****ting themselves, doing flat 14's isn't hard.
> 
> I've helped so many people tune their ram and have never encountered an issue with running flat 14 primaries...
> 
> I've done this on Unify X, Bazooka, B450 board, Dark Hero, so many different boards...


Hey! It would be great tour advise. I learnt that 1T GDM disabled it doesn’t work with dual rank. And also, 3800-14 flat with dual rank it’s a little bit harder.. a least in 2x16GB. I will share you my results and advances so you can give some advise to try. I ended up following @Veii best timings for 3800 flat using the exploit. I started lowering TRDS fro 16 to 15.. and some errors appear, but with 14 TM5 gave a. Lot of 6 en the first test so I had to rebuild my RTTs and ProcOCT, and see voltages values. In a couple of hours when I’m staying at home I’ll share you my work. I know is hard but I want to thing with it could be achieve 
These are the @Veii timings for 3800 flat








My doubts here are what are the VDIMM he’s running because of RTTPARK 6 that maybe he is running above 1.62V. Besides the VSOC value seems to be high. And then the exploit of tRAS +1 and TFAW same as tRRDL. I don’t remember if he’s RAM is single rank. Maybe I just have to tweak more being mines DR 
Thanks!


Sent from my iPhone using Tapatalk Pro


----------



## BarrettDotFifty

lmfodor said:


> Yes, the same things happens to me but with Anta777. I don’t know why. I installed a new copy.. because it’s the last one but sometimes it’s stop.
> 
> 
> 
> Sent from my iPhone using Tapatalk Pro


I've contacted the guys at overclockers ru at the place where anta777 hangs out and other guys discussing this TestMem5. I'll let you know if they know of a fix.


----------



## Ramad

RonLazer said:


> It just says the sheet is protected if I try and change anything?


Use the light green fields, below Input1, Input 2...etc.


----------



## TimeDrapery

Okay, just kidding about being done after that last iteration... 😂😂😂😂😂



Spoiler: Screenshots







































































































I'm off to read more about why what happened happened during this go around of memory overclocking so I can try to determine where to go from this point...

If anyone's got any suggestions I'd appreciate hearing them! Thanks!


----------



## adversary

@mongoled 

I did take your advices, especially one regarding TRDRDSCL and TWRWRSCL setting from 2 to 4 (should also test 5) for 32GB dual rank. you were right, direct improvement on speeds. I'm simply new to AMD and first time owning B-Die RAM so all I know is what I get here

apologies for not answering earlier (about 2 weeks passed), I was pretty much occupied by other things last period, but I did grab some time to do again overclock on RAM and test it

however, I pushed one configuration (this one, tested with number of tests, I will explain more detailed later in post, and get it totally stable - up to one temperature point) again. more on this later


@Veii 

same big thanks for you

for someone who is learning it may be hard to remember all ot once, also it is not easy to scroll all of forum thread when you need info - so I can to idea to copy or screenshoot some of your posts. up to now I have small gallery and it is useful trust me 

I may still making errors in RAM overclock, may still be unaware of some things (leading to wrong combinations of some timings), but always feel free to correct me, if you wish. it helps much


---------------------------















well there we have 3800 14-14-12 1.6V
this is best I get so far with latency (if we do not mind crazy attempts which are not stable, this one is tested stable for days - more on that later). this is not in safe mode

Windows10 20H2 - now, for what I read at forum recently, newer Win10 versions are more error prone with RAM overclocking

any attempt to make it 3866/1933 - errors one after another, no matter how much I relax timings or set another specific setting

AGESA is now 1.2.0.1 Patch A (not longer in Beta) - but I also read here that 1.2.0.1 is bugged for some things

RAM is placed under EKWB custom watercooling - and this is very important part as I will explain - not only temps get lowered (RAM was already cooled by direct strong fan), but max possible temperature will always stay stable according to water coolant temperture, and stress it have - you can know exact maximum value it may have, it can't go 0.1C above it - proven very imporatant for Samsung B-Die

now is 52.3ns ok for 3800/1900? at least there was no variance in repeating tests (just sometimes 0.1ns, if any)

tRFC is indeed very aggressive - I did try to apply Veii post about it relation with tRC (if I did understand properly how stepping there should work)

I did set VDDG IOD and CCD, again, according to what Veii was saying about "75mV steppings" relative to SOC voltage, taking IOD and CCD average value. SOC voltage, taking vdroop into accout. now did I mistaken something while doing this, I do not know, but it worked properly

I did test also combinations with more IOD, CCD, SOC, it did not bring any benefit, did not allow me more overclock headroom nor it lowered latency.
well, less SOC voltage = lower CPU overall temps = better cores boost possible

setting higher (I mean higher number, higher divider) RttPark is not possible unless RttWr is set to RZQ/2
so I did stick for 6/3/3
is 1.6V OK in this case? maybe. not sure is PCB B1 or B2, but it is not B0. with RttPark 3, tCKE 9, with good cooling, maybe it should be fine.

I did not know at moment of doing this overclock, that CAD BUS timings are possible only (if I understand right?) if XX-20-20-20 are used. So I did not try timings 3-3-15 as I intended as it could not work with 60-20-30-20. I may try this next time

last thing, I can't regulate CPU VDDP, nor I can see it. can't find it in BIOS. I did try to install Asus TurboV EVO, but it says it can't work on this board. however, looking at specs on internet for this board, it say it support TurboV EVO.



so what made biggest change is fact I started finally to use proper programs to do stress test, prior to this I did not perform such tests and most probably was having errors all time.

because, after testing and setting this one to be error free, there was not anymore stutters in games or apps, not crackling sound, or weird game or app crash.

for stress tests, did not use all possible, but used : TM5, SuperPi 1.5, Prime95 LargeFFT, Y-Cruncher, Aida64

TM5 - did run 1usmus_v3 endless times - not single error
SuperPi - did all tests, but mostly repeated 16MB and 32MB - no errors
Prime95 - LargeFFT. seems to heat up RAM most of all. did burn it for few hours. repeated in few different days. 0 errors or warnings upon test stop.
Aida64 - simply left it for few hours on Stress system RAM - nothing happened
Y-Cruncher - did set time to 240 seconds (120 default), and additionally enabled FFT (fast fourier transform). so what was tested is : BKT, BBP, SFT, FFT, N64, HNT, VST. again, run on different days, let test self repeat number of times -0 errors

for some of mentined tests, I had HWInfo opened, there was not WHEA errors registered


I concluded it as stable and run fine for days (and it is) - up to one evening - all issues suddenly returned - stutters, sound crackling, game freeze (even in menu). prior to that, tested with uncapped fps 500+ without problem.
it did not take me long to find what is issue - coolant temperature gone high (32C) simply because room ambient temperature get to about same (there we have little specific situation with insulated room, no windows, only way to let air is by opening doors). so depending what you do, even not in summer time, it is possible in this room to get ambient at 32C, assuming you do not open doors for prolonged time - and that exactly happened

for some reason, game I did run at that moment is hard on RAM, and if Prime95 LargeFFT heat up RAM at +6C difference relative to coolant tempertaure, this game will do it at about 5.5C (1.6V RAM voltage)

tested TM5 in that conditions, and it immidiately started to throw number of different errors
get room temperature at lets say 25C, repeat all tests, there will be no single error
and now we can see how Samsung B-Die is temperature sensitive in case of aggressive timings
saying that "up to 40C (or 50C) there will be not impact on RAM" is not true in this case at all - there we have totally different scenarios at RAM with around maximum 32C or above 37C, one is stable and one is totally unstable

because of various reasons (there will be chiller upgrade to watercooling + some other things, plus there is already AGESA 1.2.0.2 but in Beta for my motherboard, and 1.2.0.1 is mentioned as bugged, I will for sure do BIOS update in some future), I decided not to bother much with again finding stable overclock at higher temperatures, I simply pulled back to 3733/1866 and called it a day - for now.
I performed tests further to see what will happen with 3733/1866 on higher temperatures. at 37 or 38C it is now going to be stable, all way up to 45-46C (to get that high temperature was possible only by removing few fans from radiatior and heating it quickly with hairdryer  ) . and yes 3733/1866 can work with slighly less voltage than 1.6V

as only CPU and RAM is watercooled, 5600X no matter settings and stress, is not able to have impact on coolant temperature, at this moment this watercooling is overkill for this CPU - it may bring change to 1C and no more. but as this is my first AMD build ever, I decided for 5600X and this cheaper board, first to learn it (and it is anyway big performance upgrade compared to my old 4 core Intel). possible upgrade, in time it comes fully as matured product, would probably be Zen3+ (I hope for it) with 12 cores, but it is not still decided of course. have to keep in mind that for example 12 cores CPU would be able to have more impact on cooling temperatures than 6 core 5600X

however, I planned already for some time, Hailea chiller upgrade, as not only for RAM, also same for CPU in case of Zen3, temperatures are going to have big influence from my expirience with it so far. I plan to place order for chiller next week, but it will take time until I get it into my crap country. when I get it running, I will keep you updated

in preparations for chiller use, I already get good temperature and humidity meter for room (to know dew point), additional 5L of coolant, and 15 W/mK thermal pads (EKWB is, I think, 2.5 W/mK)

apologies for long post, but I find it as best way to explain all details. hope my expirience with temperatures will be usuful for others.

I will probably keep 3733/1866, it is fine for my need at moment (can run 3800/1900 without problem but would need to be aware of ambient temperature all time and summer is coming), however I will attempt to overclock again when we get BIOS update, chiller, and summer is coming so best to do tuning in that conditions, so I belive best thing is to wait for some time and later attempt again RAM overclock experiments.
in meantime I will collecting all info here 

if I did commit any big error in timing of course let me know


----------



## craxton

so, ran some tests since i hadnt ran a stress test in sometime or checked to see now
that its heated up in my area that my timings/4x8 SR kits were still stable

now, i had no issues with HCI (wife thought it was cute to use pc and closed that out tho (1280% run)
TM5 clean and clear 1000%, unless somethings wrong with the config file and 1000% didnt run at all?
OCCT mem test, and AVX extreme version 7xxx passes,

now, y-cruncher crashes, comes to find out my C/O profile saved i hadnt swapped 50mv to 60mv
and thats where i crashed. anyhow, @Veii what all is needed and how to i go about getting on the Gdoc
for ryzen ram calc?




































here is the ONLY WHEA error ive had since installing the 5600x


















again, the WHEA error is due to Vcore offset not being set in place. will run another loopx4 run of y-crucher and post back.
but for now, posting before i missplace said pics/doc or someone calls for help elsewhere.

(EDIT Adding y-cruncher shots) 











*Had to change C/O to -15, 13,13,13,15,15 
still with +60mv offset range. limiting PBO to 88,75,80*

EDIT: Summary page in event viewer is the only critical events shown, as
i deleted logs yesterday morning while making a new os and EFI system partition to 
test and double/triple check my WHEA logger was indeed running as it should be. 
(in some sense im glad it crashed finally so i could see a WHEA kernel event log
with some form of ID behind it) 

Im still unsure where im supposed to submit proof of actual stability at this time. 
theres nothing on where submissions are supposed to be sent in FAQ section.


----------



## Robby37

adversary said:


> @mongoled
> 
> I did take your advices, especially one regarding TRDRDSCL and TWRWRSCL setting from 2 to 4 (should also test 5) for 32GB dual rank. you were right, direct improvement on speeds. I'm simply new to AMD and first time owning B-Die RAM so all I know is what I get here
> 
> apologies for not answering earlier (about 2 weeks passed), I was pretty much occupied by other things last period, but I did grab some time to do again overclock on RAM and test it
> 
> however, I pushed one configuration (this one, tested with number of tests, I will explain more detailed later in post, and get it totally stable - up to one temperature point) again. more on this later
> 
> 
> @Veii
> 
> same big thanks for you
> 
> for someone who is learning it may be hard to remember all ot once, also it is not easy to scroll all of forum thread when you need info - so I can to idea to copy or screenshoot some of your posts. up to now I have small gallery and it is useful trust me
> 
> I may still making errors in RAM overclock, may still be unaware of some things (leading to wrong combinations of some timings), but always feel free to correct me, if you wish. it helps much
> 
> 
> ---------------------------
> 
> 
> 
> View attachment 2486991
> 
> 
> 
> 
> 
> well there we have 3800 14-14-12 1.6V
> this is best I get so far with latency (if we do not mind crazy attempts which are not stable, this one is tested stable for days - more on that later). this is not in safe mode
> 
> Windows10 20H2 - now, for what I read at forum recently, newer Win10 versions are more error prone with RAM overclocking
> 
> any attempt to make it 3866/1933 - errors one after another, no matter how much I relax timings or set another specific setting
> 
> AGESA is now 1.2.0.1 Patch A (not longer in Beta) - but I also read here that 1.2.0.1 is bugged for some things
> 
> RAM is placed under EKWB custom watercooling - and this is very important part as I will explain - not only temps get lowered (RAM was already cooled by direct strong fan), but max possible temperature will always stay stable according to water coolant temperture, and stress it have - you can know exact maximum value it may have, it can't go 0.1C above it - proven very imporatant for Samsung B-Die
> 
> now is 52.3ns ok for 3800/1900? at least there was no variance in repeating tests (just sometimes 0.1ns, if any)
> 
> tRFC is indeed very aggressive - I did try to apply Veii post about it relation with tRC (if I did understand properly how stepping there should work)
> 
> I did set VDDG IOD and CCD, again, according to what Veii was saying about "75mV steppings" relative to SOC voltage, taking IOD and CCD average value. SOC voltage, taking vdroop into accout. now did I mistaken something while doing this, I do not know, but it worked properly
> 
> I did test also combinations with more IOD, CCD, SOC, it did not bring any benefit, did not allow me more overclock headroom nor it lowered latency.
> well, less SOC voltage = lower CPU overall temps = better cores boost possible
> 
> setting higher (I mean higher number, higher divider) RttPark is not possible unless RttWr is set to RZQ/2
> so I did stick for 6/3/3
> is 1.6V OK in this case? maybe. not sure is PCB B1 or B2, but it is not B0. with RttPark 3, tCKE 9, with good cooling, maybe it should be fine.
> 
> I did not know at moment of doing this overclock, that CAD BUS timings are possible only (if I understand right?) if XX-20-20-20 are used. So I did not try timings 3-3-15 as I intended as it could not work with 60-20-30-20. I may try this next time
> 
> last thing, I can't regulate CPU VDDP, nor I can see it. can't find it in BIOS. I did try to install Asus TurboV EVO, but it says it can't work on this board. however, looking at specs on internet for this board, it say it support TurboV EVO.
> 
> 
> 
> so what made biggest change is fact I started finally to use proper programs to do stress test, prior to this I did not perform such tests and most probably was having errors all time.
> 
> because, after testing and setting this one to be error free, there was not anymore stutters in games or apps, not crackling sound, or weird game or app crash.
> 
> for stress tests, did not use all possible, but used : TM5, SuperPi 1.5, Prime95 LargeFFT, Y-Cruncher, Aida64
> 
> TM5 - did run 1usmus_v3 endless times - not single error
> SuperPi - did all tests, but mostly repeated 16MB and 32MB - no errors
> Prime95 - LargeFFT. seems to heat up RAM most of all. did burn it for few hours. repeated in few different days. 0 errors or warnings upon test stop.
> Aida64 - simply left it for few hours on Stress system RAM - nothing happened
> Y-Cruncher - did set time to 240 seconds (120 default), and additionally enabled FFT (fast fourier transform). so what was tested is : BKT, BBP, SFT, FFT, N64, HNT, VST. again, run on different days, let test self repeat number of times -0 errors
> 
> for some of mentined tests, I had HWInfo opened, there was not WHEA errors registered
> 
> 
> I concluded it as stable and run fine for days (and it is) - up to one evening - all issues suddenly returned - stutters, sound crackling, game freeze (even in menu). prior to that, tested with uncapped fps 500+ without problem.
> it did not take me long to find what is issue - coolant temperature gone high (32C) simply because room ambient temperature get to about same (there we have little specific situation with insulated room, no windows, only way to let air is by opening doors). so depending what you do, even not in summer time, it is possible in this room to get ambient at 32C, assuming you do not open doors for prolonged time - and that exactly happened
> 
> for some reason, game I did run at that moment is hard on RAM, and if Prime95 LargeFFT heat up RAM at +6C difference relative to coolant tempertaure, this game will do it at about 5.5C (1.6V RAM voltage)
> 
> tested TM5 in that conditions, and it immidiately started to throw number of different errors
> get room temperature at lets say 25C, repeat all tests, there will be no single error
> and now we can see how Samsung B-Die is temperature sensitive in case of aggressive timings
> saying that "up to 40C (or 50C) there will be not impact on RAM" is not true in this case at all - there we have totally different scenarios at RAM with around maximum 32C or above 37C, one is stable and one is totally unstable
> 
> because of various reasons (there will be chiller upgrade to watercooling + some other things, plus there is already AGESA 1.2.0.2 but in Beta for my motherboard, and 1.2.0.1 is mentioned as bugged, I will for sure do BIOS update in some future), I decided not to bother much with again finding stable overclock at higher temperatures, I simply pulled back to 3733/1866 and called it a day - for now.
> I performed tests further to see what will happen with 3733/1866 on higher temperatures. at 37 or 38C it is now going to be stable, all way up to 45-46C (to get that high temperature was possible only by removing few fans from radiatior and heating it quickly with hairdryer  ) . and yes 3733/1866 can work with slighly less voltage than 1.6V
> 
> as only CPU and RAM is watercooled, 5600X no matter settings and stress, is not able to have impact on coolant temperature, at this moment this watercooling is overkill for this CPU - it may bring change to 1C and no more. but as this is my first AMD build ever, I decided for 5600X and this cheaper board, first to learn it (and it is anyway big performance upgrade compared to my old 4 core Intel). possible upgrade, in time it comes fully as matured product, would probably be Zen3+ (I hope for it) with 12 cores, but it is not still decided of course. have to keep in mind that for example 12 cores CPU would be able to have more impact on cooling temperatures than 6 core 5600X
> 
> however, I planned already for some time, Hailea chiller upgrade, as not only for RAM, also same for CPU in case of Zen3, temperatures are going to have big influence from my expirience with it so far. I plan to place order for chiller next week, but it will take time until I get it into my crap country. when I get it running, I will keep you updated
> 
> in preparations for chiller use, I already get good temperature and humidity meter for room (to know dew point), additional 5L of coolant, and 15 W/mK thermal pads (EKWB is, I think, 2.5 W/mK)
> 
> apologies for long post, but I find it as best way to explain all details. hope my expirience with temperatures will be usuful for others.
> 
> I will probably keep 3733/1866, it is fine for my need at moment (can run 3800/1900 without problem but would need to be aware of ambient temperature all time and summer is coming), however I will attempt to overclock again when we get BIOS update, chiller, and summer is coming so best to do tuning in that conditions, so I belive best thing is to wait for some time and later attempt again RAM overclock experiments.
> in meantime I will collecting all info here
> 
> if I did commit any big error in timing of course let me know











I am running quad dr 16gb 3200 cl14 bdie and i was wondering if you had any input on my timings i am gonna try your trfc and primaries but i mainly wanted to know if oyu had any idea what i can do to lower my proc odt . Also @Veii i a have read most of this thread and i have soeaked up alot but i have hard time finding info for my setup cause alot of the 4 stick advice you give is for sr or the 64gb advice is fro 2 sticks. I may try raising my soc voltage and then see if i can lower procodt but usually it ends up with a no boot. I have disable gear down and 1t as i see you recommend that all the time.


----------



## wmunn

I am so close to getting this to run 3800 / 1900 IF
errors once in a while.
Here is my timings etc.. when stable @ 3733
Ram kit is G.Skill Trident Z Neo 16GB x 2 - cl16 3600


----------



## adversary

Robby37 said:


> I am running quad dr 16gb 3200 cl14 bdie and i was wondering if you had any input on my timings i am gonna try your trfc and primaries but i mainly wanted to know if oyu had any idea what i can do to lower my proc odt . Also @Veii i a have read most of this thread and i have soeaked up alot but i have hard time finding info for my setup cause alot of the 4 stick advice you give is for sr or the 64gb advice is fro 2 sticks. I may try raising my soc voltage and then see if i can lower procodt but usually it ends up with a no boot. I have disable gear down and 1t as i see you recommend that all the time.



You can try all and test. What I realised is how important is to do all test after your overclock. And there is even more tests which can be run

But keep in mind I'm novice and I may doing things wrongly, you will have much better input from some other members

Good luck with OC


----------



## RonLazer

@Ramad 

Thanks a bunch for sharing it! I'm unclear on why the sheet is so thoroughly locked down though? I was hoping to look into the formulas and relations between timings that you're working with to try and understand them better. 

In terms of usage, is the point to use the same frequency across inputs, or to set each one as low as you can run that set of timings at? Because for example if I lower Input 1 frequency until it suggests 14 on the primaries then it also suggests 3/7 on tWTRS/tWTRL - which I know is unstable. 

The tRFC timings are unnecessarily loose for B-die, but since I've never tested tRC_PAGE off auto I'm not sure if I can set a lower frequency for that set and have it still work with that timing.


----------



## TimeDrapery

RonLazer said:


> Spoiler
> 
> 
> 
> @Ramad
> Thanks a bunch for sharing it! I'm unclear on why the sheet is so thoroughly locked down though? I was hoping to look into the formulas and relations between timings that you're working with to try and understand them better.
> 
> In terms of usage, is the point to use the same frequency across inputs, or to set each one as low as you can run that set of timings at? Because for example if I lower Input 1 frequency until it suggests 14 on the primaries then it also suggests 3/7 on tWTRS/tWTRL - which I know is unstable.
> 
> The tRFC timings are unnecessarily loose for B-die, but since I've never tested tRC_PAGE off auto I'm not sure if I can set a lower frequency for that set and have it still work with that timing.


If you navigate to "View" you should find a checkbox option labeled "Show Formulas" which should be sufficient for you to see why something funky is being calculated

If you'd like an unprotected copy of the Excel workbook I can send one your way...

Although it sure would be nice to have the gentleman user that posted the spreadsheet to share with us simply post an unprotected copy...


----------



## PJVol

craxton said:


> here is the ONLY WHEA error ive had since installing the 5600x


Hi! Did reinstalling windows helped to stabilize your system at the high IF rate, i.e. whea-19-free, or was it stable before?


----------



## Ramad

RonLazer said:


> @Ramad
> 
> Thanks a bunch for sharing it! I'm unclear on why the sheet is so thoroughly locked down though? I was hoping to look into the formulas and relations between timings that you're working with to try and understand them better.
> 
> In terms of usage, is the point to use the same frequency across inputs, or to set each one as low as you can run that set of timings at? Because for example if I lower Input 1 frequency until it suggests 14 on the primaries then it also suggests 3/7 on tWTRS/tWTRL - which I know is unstable.
> 
> The tRFC timings are unnecessarily loose for B-die, but since I've never tested tRC_PAGE off auto I'm not sure if I can set a lower frequency for that set and have it still work with that timing.


I'm afraid that you are not using the spreadsheet correctly. The primaries are marked "Tunable", so you can tune them just like Corsair, G.Skill...etc are doing by tuning the primaries and letting the subtimings be at default, this is the content of an XMP profile in general, default subtimings and tuned primaries.

Example:










Tune the primaries to 14-14-14-14-30-46 and use the rest. These tRFC may be so tight for your RAM, but it's an example that shows that you have a great deal of flexibility.

As for tRFC timings, I did separate those from the rest of other timings to give the user a choice, if the user wants to tighten them more.

tRC_PAGE is an AMD specific delay that, according to AMD, should minimize or eliminate the possibility for data corruption. The user does not have to use this function, setting it to 0 in the BIOS will turn it off.

I was going to post the password, but chose not to because I have no time to deal with "why it's not working correctly?" or "What was in xyz fields that I have deleted?"

As for formulas, I have been urging members to read data sheets and make their own calculators and I have provided the tools and the how to several times, that has led anywhere.
Here is the "How to" from 2017: ASUS ROG Zenith Extreme X399 ThreadRipper Overclocking /...


----------



## Robby37

@Ramad I am gonna try your spreadsheet right now I have my ram stable and my 200mhz pbo undervolt 10 or more every core stable for the core cycler and y cruncher 6 hrs each but i see alot of mention that I should be changing my drive strengths and I love my primaries but I see alot of advice saying that some timings should be diff. I just am not sure of all the relationship so don't get why i am running like tcke 9 but others run 1 and i was soomewhat stable with 60202424 and 4,4,18 setup timings but i don't know whats better.


----------



## craxton

PJVol said:


> Hi! Did reinstalling windows helped to stabilize your system at the high IF rate, i.e. whea-19-free, or was it stable before?


i didnt have stability issues before nor after, just after using Curve settings
that were stable in everything but y-cruncher and prime

re-installing windows simply reminded me why i dread ever having to actaully re-install windows period lol
as the amount of services that are unneeded and cpu/ram usage upon boot is well, way to high.

turns out, the only WHEA i had was easy solved by slightly adjusting curve to -15,-12,-12,-12,-15,-15 with 60mv positive offset to 
core voltage, other than that no issues, no warnings, no crashes what-so-ever.

that crash was the ONLY crash id had btw, when i got my ram stable, i hadnt messed with C/O
at all, (well enough to know that i was NEVER getting -30 anything) but since then
alot has been posted and reference shares have been made to what one can try.

ive not had whea 19 at all, just the one whea-18-ID which from what all i could find 
CPU V-Core was 99% always the cause. (again, this is the only WHEA ive had, and 
im 100% sure its due to C/O as i can remove curve settings and voltage offset and let the 
motherboard control voltage ranges etc and get no issues or WHEA events, but if 
i set C/O back to -15 all core with 60mv positive offset then it crashes mid ways thru AVX section on 
y-crucher, then change to 15,12,12,12,15,15 with 60mv and no crashes..

i only re-installed windows and created a new EFI file system to test if my WHEA logger was indeed running 
as i had never gotten any WHEA errors since "i got stable" so i thought i had broke something somewhere
turns out its working just fine as i formatted/cleaned that new install and am now back on my old win10 home 
debloated install.


----------



## weleh

WHEA 18 is related to Curve/Undervolt.

WHEA 19 is fCLK.


----------



## Iarwa1N

Hi guys, I had Micron E dies 2x8 which can do 4200/2100 fckl. I upgraded to 2x16 Samsung B dies 3200/14 but whatever I do they wont go over 3400mhz. The sticks are F4-3200C14D-32GTZR, mobo is Asus B550 Strix-F, cpu 5600x. Any idea what can I try? I tried most of the timings and voltages people had on the memory overclock spreadsheet.


----------



## PJVol

craxton said:


> i didnt have stability issues before nor after


Ahh...ok, thanks. The reason I asked is there are some who think reinstalling windows or rolling back to some previous builds can help to aleviate GMI-related whea's. And btw, I didn't have WHEA 19 and stability issues with my 5600X on a b450 mortar titanium PC either  . Actually I'm trying to collect info which mb's are least troublesome for high IF, as I'm pretty sure atm that the IF instability origin is the vrm and pwm vendor's implementation.


----------



## weleh

Iarwa1N said:


> Hi guys, I had Micron E dies 2x8 which can do 4200/2100 fckl. I upgraded to 2x16 Samsung B dies 3200/14 but whatever I do they wont go over 3400mhz. The sticks are F4-3200C14D-32GTZR, mobo is Asus B550 Strix-F, cpu 5600x. Any idea what can I try? I tried most of the timings and voltages people had on the memory overclock spreadsheet.


What are you trying to boot?
Rule of thumb should be very loose timings.

SOC? 
VDDP?
VDDG IOD/CCD?
VDIMM?


----------



## tefla

Updated windows to 20H2 and it seems my once WHEA-19 warning free settings are now... not WHEA-19 warning free. Such a pain to deal with, dropping to 3733 as I've tried everything I can think of. I can boot and run 100% stable tm5 1usmus.cfg and karhu @ any % or number of cycles w/ 4000mhz flat 15, but get hundreds of WHEA-19 warnings. Part of me just wants to ignore the warnings and run the settings anyway if they are "stable" 😂


----------



## craxton

PJVol said:


> Ahh...ok, thanks. The reason I asked is there are some who think reinstalling windows or rolling back to some previous builds can help to aleviate GMI-related whea's. And btw, I didn't have WHEA 19 and stability issues with my 5600X on a b450 mortar titanium PC either  . Actually I'm trying to collect info which mb's are least troublesome for high IF, as I'm pretty sure atm that the IF instability origin is the vrm and pwm vendor's implementation.


i recently have been seeing the same thing popping up in reddit, and Microsoft forums.
i personally wasnt testing that theory tho. 
considering i came from the X570 version of this board i couldnt get ANYTHING 4x8 stable period
and sometimes couldnt get to post when it was near stable. 

today agesa 1.2.0.2 has been released for this board. may flash and test to see if USB dropout has been solved...

im running a b550 gaming edge wifi/5600x on 4x8 SR 3200c14 tforce dark pro sticks btw
for sure recommend it. hoping MSI added CPU VDDP adjustment options inside bios
"fingers crosses"


----------



## craxton

lmfodor said:


> It's not really a good comparison since I never really got 3800-14-14-14. Although it managed to boot into windows, in TM5 it was full of errors. Today I spent about 6 hours reading and testing .. TM5 gave me 6 errors in the first 1usmus test and sometimes it gave me 3 zeros and 3 sixes, so reading the errors and their events from Veii's worksheet, check the SCL values, the tWRRD, then when it only had 6 continuous errors .. then it also looked for the voltage .. I got to VDIMM of 1.6 .. I followed all the rules that I could but I couldn't. It can't be that hard, I know I'm close so I'll keep reading and trying. Always with the caution of use a weak RTTs so as not to have problems with high voltage. I'll do it, it's not that easy. And of course the results of the bench that I shared are not reliable since with so many errors it must be auto correcting everything .. so I will continue another day.
> 
> I see that many achieve it with memories of 3200 or 3600, and these that are a new model 3800CL14 should be easier, but it is not! at least for me.
> Sent from my iPhone using Tapatalk Pro


3800c14 can be done on 2 sticks SR pretty easy as thats what i ran for sometime 
had vdimm set to 1.46 LLC3 (MSI LLC)


----------



## craxton

TimeDrapery said:


> Okay, just kidding about being done after that last iteration... 😂😂😂😂😂
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2486988
> 
> View attachment 2486959
> 
> View attachment 2486986
> 
> View attachment 2486985
> 
> View attachment 2486992
> 
> View attachment 2486998
> 
> View attachment 2486999
> 
> View attachment 2487000
> 
> View attachment 2487001
> 
> 
> 
> 
> I'm off to read more about why what happened happened during this go around of memory overclocking so I can try to determine where to go from this point...
> 
> If anyone's got any suggestions I'd appreciate hearing them! Thanks!


can you explain or "simple enough put it"
what in y-cruncher is telling you your not good???


----------



## PJVol

craxton said:


> im running a b550 gaming edge wifi


So far haven't seen it in stock at local retailers, but will certainly consider it as candidate for possible asrock abandonment )


----------



## Danny.ns

I believe this is roughly the best I can do with my stuff and 1.5 vdimm. I can post/boot with 14-14-14, 14-15-15 and 14-16-16 but testing throws some errors after a little while - I tested these with AUTO sec and tert timings (so veeeeeeery loose). I'm one of those that cannot for the life of me POST at FCLK 1900 (I can POST 1933, 1966, 2000, 2033 all day every day) so thats a no go as well. I wanted to try CL15 with 2T (+GDM off) but I cant post when i set that - not sure whats up with that. I know tRFC wont POST at these settings with 1.45Vdimm, 1.5V was required - but I didnt try much lower.


----------



## craxton

Hmm, updated bios.
No issues posting 4000 1:1:1 even tho I've seen complaints stating they were no longer able.

However what the hell are these

















And @Veii is this possibly CPU VDDP finally added? Or is it still the same VDDP voltage that's no help










Correction, IT IS CPU VDDP it would seem that MSI finally listened, check
your HWinfo page VDDP voltage is there finally. atm its not reading correctly tho, maybe 
it doesnt work, or perhaps i need to reboot. but cpu vddp voltage is now a thing on 
MSI b550 gaming edge wifi


----------



## craxton

PJVol said:


> So far haven't seen it in stock at local retailers, but will certainly consider it as candidate for possible asrock abandonment )


im unsure about local stock, but i got mine USED-GOOD off amazon (said it would be opened etc,)
it wasnt, had EVERYTHING a new unopened one would have lol and i was able to register it.

(the box was opened, but the MOBO static bag had not been, nor were any other parts included.

here is a used-good for 151 off amazon (USD) i would NOT buy this board for 200.00 bucks anywhere!\
let alone another other board for that matter unless it was able to set 3200c14 sticks at 4000 mhz itself and tighten timings 
accordingly lol

this is the link, just go down to the new and used section. (unsure if your in the us or not)


----------



## weleh

craxton said:


> Hmm, updated bios.
> No issues posting 4000 1:1:1 even tho I've seen complaints stating they were no longer able.
> 
> However what the hell are these
> View attachment 2487178
> 
> View attachment 2487179
> 
> 
> And @Veii is this possibly CPU VDDP finally added? Or is it still the same VDDP voltage that's no help
> View attachment 2487180
> 
> 
> 
> Correction, IT IS CPU VDDP it would seem that MSI finally listened, check
> your HWinfo page VDDP voltage is there finally. atm its not reading correctly tho, maybe
> it doesnt work, or perhaps i need to reboot. but cpu vddp voltage is now a thing on
> MSI b550 gaming edge wifi


bruh...

That VDDP is CLDO_VDDP, nothing to do with VDDP 1.8V that I believe Veii and others are talking about.
It's been there for ages.


----------



## craxton

weleh said:


> bruh...
> 
> That VDDP is CLDO_VDDP, nothing to do with VDDP 1.8V that I believe Veii and others are talking about.
> It's been there for ages.


Last bios revision didn't have it. 
Had CLDO VDDP, 
At this time I'm testing to see if it works or not.


----------



## PJVol

There's vdd 1.8, not vddp. As for that mysterious cpu vddp, i am personally not sure it even exists, and that in some mb's its not just double reference to actual cldo vddp.
I appreciate, if you give some evidence of it existence, i mean some amd docs or reports from monitoring software referred to, and not just someone's ramblings based on what names mb vendors give to the settings in bios.


----------



## RonLazer

PJVol said:


> There's vdd 1.8, not vddp. As for that misterious cpu vddp, i am personally not sure it even exists, and that in some mb's its not just double reference to actual cldo vddp.


It exists, it powers the PHY interface for the CPU to receive signals, whereas CLDO_VDDP powers the memory controller PHY.


----------



## PJVol

RonLazer said:


> It exists, it powers the PHY interface for the CPU to receive signals, whereas CLDO_VDDP powers the memory controller PHY


Would you provide the source of that interesting info?
For example, where is that mysterious "PHY interface for the CPU to receive signals" on this Zen diagram:


----------



## weleh

craxton said:


> Last bios revision didn't have it.
> Had CLDO VDDP,
> At this time I'm testing to see if it works or not.


Even my B450 board has that VDDP which is CLDO VDDP for the Phy controller and nothing to do with the "secret" voltage for fCLK stability.
That voltage has been there forever, I guarantee you.


----------



## craxton

weleh said:


> Even my B450 board has that VDDP which is CLDO VDDP for the Phy controller and nothing to do with the "secret" voltage for fCLK stability.
> That voltage has been there forever, I guarantee you.


yes, your quite right. but it has added something inside hwinfo to see cpu vddp voltage
which doesnt actually show anything.

atm i am having MAJOR issues booting 4000 mhz what was once stable is stable NOMORE!
the VDDP voltage inside the bios now is for memory so its nothing new sadly. possibly flashing back to the earlier bios
i was on since NOTHING is working now.... running at 2400mhz just to get into windows is BAADD

scratch that, MSI removed the bios revision that was before this one and now is no longer available
to which i do NOT have it saved anywhere....


----------



## PJVol

craxton said:


> However what the hell are these


From wikichip:
"*LClk* - Link Clock - The clock at which the I/O Hub Controller communicates with the chip"


----------



## mongoled

PJVol said:


> Would you provide the source of that interesting info?
> For example, where is that mysterious "PHY interface for the CPU to receive signals" on this Zen diagram:
> 
> View attachment 2487181


Interesting, 

MSI "support" told me that "CPU VDDP" is only for APU and is not available for 5600x.

So I asked them why Asrock and Gigabyte have this available in their BIOSs when 5000 series CPUs are being used.

No reply so far from them....


----------



## PJVol

mongoled said:


> So I asked them why Asrock and Gigabyte have this available


Have never seen it on my two ASRock boards, X370 Taichi and current B550 Extreme4


----------



## craxton

mongoled said:


> Interesting,
> 
> MSI "support" told me that "CPU VDDP" is only for APU and is not available for 5600x.
> 
> So I asked them why Asrock and Gigabyte have this available in their BIOSs when 5000 series CPUs are being used.
> 
> No reply so far from them....


wait, you actually got a response from msi...

ive sent 9 emails within 3 months and have got JACK SQUAT back lol... it would seem others in MSI forums are trying to get
this unlocked as well.


----------



## craxton

PJVol said:


> Would you provide the source of that interesting info?
> For example, where is that mysterious "PHY interface for the CPU to receive signals" on this Zen diagram:
> 
> View attachment 2487181


On the board itself it states that VDDP powers this "PHY" interface. If mines not set to 900mv I don't get a post.


----------



## craxton

NOTES to ANYONE running a b550 gaming edge wifi, or perhaps thinking of 
running bios 1.2.0.2 DONT, posted one time with fclk 2000/4000mhz and that was it
after that, Ram overclock failed "F1 to run bios setup"


----------



## PJVol

craxton said:


> On the board itself it states that VDDP powers this "PHY" interface


Its what CLDO_VDDP for. What I am asking is where and what is that "available to only limited circle of people" CPU VDDP voltage.


----------



## craxton

PJVol said:


> From wikichip:
> "*LClk* - Link Clock - The clock at which the I/O Hub Controller communicates with the chip"
> 
> View attachment 2487183


if it has anything to do with why i had issues posting 2000fclk then ill just take the usb
cutout issues (since they only happen on iphone anyhow lol)
i dont use iphone, and never have dropped USB issues on my razor mouse, or G413 carbon keyboard. 

i do have strange display switching randomness happen tho, when switching from my monitor to 
the tv mounted above head to watch movies etc, itll cutout 2x after its already switched and indicate 
the sound of hardware being removed and reattached.


----------



## PJVol

Honestly, I wouldn't touch those settings till someone enlighten why are those suddenly have been exposed.


----------



## craxton

PJVol said:


> Its what CLDO_VDDP for. What I am asking is where and what is that "available to only limited circle of people" CPU VDDP voltage.


yes, but as to why they changed the name from CLDO_VDDP 
in the bios released (before the past two releases as im now back on previous 1.2.0.1 agesa version) 
it has only VDDP as well, but the one before that had cldo.

there is some boards showing CPU_VDDP voltage and actually showing how much current etc running thru said options.

but from my stand point, ive not had a board between my MSI b450I gaming edge wifi, x570/b550 gaming edge wifi boards have
CPU_VDDP control at all...however, the inside the bios, where it shows voltage (while in advance mode using F7 the right side info panel)
has CPU_VDDP as N/A so im unsure if the board is able to read it at this point. then again ?


----------



## craxton

PJVol said:


> Honestly, I wouldn't touch those settings till someone enlighten why are those suddenly have been exposed.


noway for me to touch those settings lol, i found the download i had of past bios version i was using 
and flashed back immediately considering i could post simple XMP profile, and when i first booted 4000/2000
i went to bios, and it was frozen three reboots still frozen, finally a complete power cycle while unplugging psu cable 
allowed me to move inside the bios again. unsure what that was about.

none the less, im staying clear of this new "fix" for USB issues until i have no choice but to use it.


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> can you explain or "simple enough put it"
> what in y-cruncher is telling you your not good???
> View attachment 2487175


Those were screenshots of benchmark results, I don't _think_ (although [likely due to my low levels of self-confidence], due to your question I'm now wondering if I'm missing something that _does_ indicate I'm not "good" 😂😂😂😂😂) that they indicate that I'm not "good"...

This timing set appears, to me, relatively stable (the remainder of the screenshots are stability test results) and highly performant at this point in time

I was simply sharing the results I attained this go-around in order to add to the heaping pile of data that's out there just in case someone finds them useful

Thanks so much for taking your time to reply to my post, I really appreciate that

When I ask for advice or input I'm trying to get some good learning going by hearing about how you (and the community) see the timing set and how you'd go about improving my system's memory (or general) performance and/or stability so I can learn more about overclocking and improve my processes

Like, in this case...

• Would you move on to spinning up a 1T CR/GDM Disabled timing set?
• Would the increase in performance between this configuration and a 1T/GDM Disabled timing set be sufficient to trade for however much of a decrease in stability I'd inherit alongside the enhanced capacity and speed?
• How would you go about spinning this set up from here?
• Clear CMOS and start fresh from failsafe timings but disable GDM and set 1T at the start?​• Attempt disabling GDM and setting 1T CR while leaving this current 2T/GDM Disabled profile in place so everything else stays the same?​• Some other way I'm not presently thinking of?​
I have a very limited understanding of how best to power the memory while overclocking (RTTs, CAD BUS, ProcODT, etc.) and I believe this is probably why I still encounter so much difficulty in attaining the level of stability I desire while spinning up a 1T/GDM Disabled timing set.

Would you (or anyone else out there in the community) happen to know where I should navigate my way towards in order to find references that I could learn more about optimally powering memory during overclocking from?

Again, thanks a ton for replying to me!!!


----------



## RonLazer

PJVol said:


> Would you provide the source of that interesting info?
> For example, where is that mysterious "PHY interface for the CPU to receive signals" on this Zen diagram:
> 
> View attachment 2487181


That's a simplified block diagram, I'm very confused why you think every single component or voltage rail would be labeled. It's only purpose is to show features, for example I might ask "where is the PSP on this diagram?" - but we know the PSP exists.

You can see the VDDP, and VDDP_sense pins here: https://en.wikichip.org/w/images/f/f8/OPGA-1331_pinmap.svg
I can't find any explicit documentation right now, but it's referenced as the external voltage here: Community Update #4: Let's Talk DRAM!

It's possible that it serves some other function, but that seems incredibly unlikely given we know the AM4 pinout precedes the introduction of any LDOs on an AMD CPU. There has to be a PHY (physical interface) to convert signals from the motherboard into data in order to communicate with the CPU prior to being powered on. This is how the CPU controller determines that it's in a suitable motherboard, compatible chipset, is being issued a valid bootloader key etc. Given they seemed to use a single voltage prior to splitting off the new UMC in the Zen2 design, CPU VDDP is likely powering the PHY receiver for "PCIe PHY" and "USB PHY" on your diagram. 

It's also why it's not a required voltage accessible in the AGESA spec - it shouldn't need to be changed regardless of which XMP profile is used - so there's no requirement to expose it. MSI don't even allow you to change it on their XOC boards like the Unify-X, although I've heard this is because they used a fix voltage supply for it and hence can't change it even if the BIOS setting was exposed. Not been able to confirm this, but even the modified BIOS I use doesn't have a setting for it, so it seems reasonable.


----------



## RonLazer

Oh and for anyone confused between CPU VDDP and CLDO_VDDP, the latter will be exposed in the first level of your overclocking menu, and shouldn't need you to venture into any sub-menus. This is because it's tied to your SOC voltage and UCLK frequency. the CLDO indicates this voltage is sourced off the CPUs "low dropout regulator" which converts the SOC voltage into other voltages used in normal operation, including the CCD and IOD voltages.

In MSI BIOS its just called "VDDP" but will show up in Zentimings and RyzenMaster as CLDO_VDDP if changed. As far as I know its been in the same location in the overclocking menu since at least AGESA 1.1.0.0.

It is 0.9V by default, but will jump up to 1.1V or 1.2V if you increase SOC or UCLK frequency. This seems to cause pretty serious problems for most overclocks, so I suggest fixing it at 0.9V and only increasing it as a last resort for unreliable memory training or trying to run aggressive overclocks. The other use-case is when you encounter the infamous 1900MHz memory hole, where 1867MHz boots fine but suddenly you can't post at 1900MHz, but can post at 1933MHz. I found that dropping CLDO_VDDP to 0.85V fixed this issue, and it worked on 2 different motherboards and a few other people I suggested it to said it fixed the problem.


----------



## Iarwa1N

weleh said:


> What are you trying to boot?
> Rule of thumb should be very loose timings.
> 
> SOC?
> VDDP?
> VDDG IOD/CCD?
> VDIMM?


I tried all the settings who also had dual rank 2x16 bdies people had success on this spreadsheet but nothing worked. I tried;
SOC 1.25, 
VDDP 1, 
IOD 1.15, 
CCD 1.1
I also reset any PBO settings I had, default CPU settings, 3600 MHZ did not boot whatever timings I have tried. I even tried 18-18-18-18 but to no avail.

This is my XMP profile;


----------



## Sleepycat

Iarwa1N said:


> I tried all the settings who also had dual rank 2x16 bdies people had success on this spreadsheet but nothing worked. I tried;
> SOC 1.25,
> VDDP 1,
> IOD 1.15,
> CCD 1.1
> I also reset any PBO settings I had, default CPU settings, 3600 MHZ did not boot whatever timings I have tried. I even tried 18-18-18-18 but to no avail.
> 
> This is my XMP profile;
> 
> View attachment 2487209


Here, try my settings. I'm running the non-RGB version of your kit, and I have 4x16GB, stable without errors at 3600/1800 IF at much tighter timings. It also works at 1T GDM on, which I was using before setting to 2T GDM off to test. I tested using TM5, OCCT Extreme Large and Prime95 Large.

vSOC 1.09V (LLC1)
CLDO VDDP 1.0V
VDDG CCD 0.95V
VDDG IOD 1.05V
vDIMM 1.46V


----------



## RonLazer

Iarwa1N said:


> I tried all the settings who also had dual rank 2x16 bdies people had success on this spreadsheet but nothing worked. I tried;
> SOC 1.25,
> VDDP 1,
> IOD 1.15,
> CCD 1.1
> I also reset any PBO settings I had, default CPU settings, 3600 MHZ did not boot whatever timings I have tried. I even tried 18-18-18-18 but to no avail.
> 
> This is my XMP profile;
> 
> View attachment 2487209


Your SOC voltage is absurdly high. 1800MHz will need 1.1V SOC at most. 

The only voltage you don't mention is DRAM. Are you increasing your DRAM voltage?

In terms of DR dimms the issue is that the auto timings can conflict with any other timings you set. Try manually setting some subtimings looser than you need, e.g. tRDWR/tWRRD at 12/4, tRRDS/tRRDL/tFAW at 5/7/28, set tCWL=tCL, tWTRS/tWTRL at 5/14, and then set primaries+tRC at 16/16/16/16/34/52. This should boot with 1.45V at 3600MHz, then you can tighten from there. 

tRDRDSCL and tWRWRSCL seem to benefit from being even values on a lot of boards, so trying lowering them to 4 as well.


----------



## craxton

TimeDrapery said:


> Those were screenshots of benchmark results, I don't _think_ (although [likely due to my low levels of self-confidence], due to your question I'm now wondering if I'm missing something that _does_ indicate I'm not "good" 😂😂😂😂😂) that they indicate that I'm not "good"...
> 
> This timing set appears, to me, relatively stable (the remainder of the screenshots are stability test results) and highly performant at this point in time
> 
> I was simply sharing the results I attained this go-around in order to add to the heaping pile of data that's out there just in case someone finds them useful
> 
> Thanks so much for taking your time to reply to my post, I really appreciate that
> 
> When I ask for advice or input I'm trying to get some good learning going by hearing about how you (and the community) see the timing set and how you'd go about improving my system's memory (or general) performance and/or stability so I can learn more about overclocking and improve my processes
> 
> Like, in this case...
> 
> • Would you move on to spinning up a 1T CR/GDM Disabled timing set?
> • Would the increase in performance between this configuration and a 1T/GDM Disabled timing set be sufficient to trade for however much of a decrease in stability I'd inherit alongside the enhanced capacity and speed?
> • How would you go about spinning this set up from here?
> • Clear CMOS and start fresh from failsafe timings but disable GDM and set 1T at the start?​• Attempt disabling GDM and setting 1T CR while leaving this current 2T/GDM Disabled profile in place so everything else stays the same?​• Some other way I'm not presently thinking of?​
> I have a very limited understanding of how best to power the memory while overclocking (RTTs, CAD BUS, ProcODT, etc.) and I believe this is probably why I still encounter so much difficulty in attaining the level of stability I desire while spinning up a 1T/GDM Disabled timing set.
> 
> Would you (or anyone else out there in the community) happen to know where I should navigate my way towards in order to find references that I could learn more about optimally powering memory during overclocking from?
> 
> Again, thanks a ton for replying to me!!!


to test using y-cruncher usually one uses 1-7-0 with a minimum of 4 loops
if your unstable itll show rather usually quickly.

at this time you can find what your looking for on this forum somewhere, i just looked for around 15 min
and couldn't find it, perhaps i overlooked it (regarding proc/databus settings to use)

i can say, since your running a 3000 series chip, going back at least 100 pages is where you can start searching for
what works and doesnt. then again??

are you running 2x16 or 4x8? and 2t GDM off is easier to run, while not having much
penalty from what ive gathered.

this link and this one too will help somewhat. but the one i was looking for had
timings for 2000 chips, 3000, and 5000 chips. but as stated above i couldnt find it.

those are verified working with proof of stability. but again, i couldnt find it.
perhaps someone reading will share it in a reply 

i myself (on a 3600xt) was only able to get 3800mhz stable 1T CR c16 flat 2x8 config.

so, if your stable (not only with TM5) but with y-crunch ( 1,7,0 ) OCCT, HCI, and prime 95 then
id settle for that personally lol.

(wouldnt i be elsewhere tho if i could persanally settle with 4000mhz stable? 😆)

im not the best equipped to answer most of your question, its not likely youll get a response due
to most of what your asking already being (back further in this thread as this pertains to Ryzen of all nodes)
as well as most are focused on 5000 chips.

have you given dram calc a shot? export your xmp profile in nanseconds using T/B then import to dram calc?


----------



## Iarwa1N

Sleepycat said:


> Here, try my settings. I'm running the non-RGB version of your kit, and I have 4x16GB, stable without errors at 3600/1800 IF at much tighter timings. It also works at 1T GDM on, which I was using before setting to 2T GDM off to test. I tested using TM5, OCCT Extreme Large and Prime95 Large.
> 
> vSOC 1.09V (LLC1)
> CLDO VDDP 1.0V
> VDDG CCD 0.95V
> VDDG IOD 1.05V
> vDIMM 1.46V
> 
> View attachment 2487210
> 
> View attachment 2487211


Your settings didn't post either, thank you for the response. It won't event post at 3400 mhz with your settings.



RonLazer said:


> Your SOC voltage is absurdly high. 1800MHz will need 1.1V SOC at most.
> 
> The only voltage you don't mention is DRAM. Are you increasing your DRAM voltage?
> 
> In terms of DR dimms the issue is that the auto timings can conflict with any other timings you set. Try manually setting some subtimings looser than you need, e.g. tRDWR/tWRRD at 12/4, tRRDS/tRRDL/tFAW at 5/7/28, set tCWL=tCL, tWTRS/tWTRL at 5/14, and then set primaries+tRC at 16/16/16/16/34/52. This should boot with 1.45V at 3600MHz, then you can tighten from there.
> 
> tRDRDSCL and tWRWRSCL seem to benefit from being even values on a lot of boards, so trying lowering them to 4 as well.


Thank you for the response. I only tried that high VSOC and other voltages because it wouldn't post with anything lower and I know that my previous 2x8 Micron B dies was working at 4066 mhz with VSOC 1.2125, VDDP 0.86, CCD 0.925, IOD 1.14.

I tried the timings you said but it wouldn't post at 3600, it posts with 3400 but nothing higher. I tried increasing VDIMM to 1.6 but it wouldn't post. These are the timings now I can post with 3400mhz;


----------



## craxton

Iarwa1N said:


> Your settings didn't post either, thank you for the response. It won't event post at 3400 mhz with your settings.
> 
> 
> 
> Thank you for the response. I only tried that high VSOC and other voltages because it wouldn't post with anything lower and I know that my previous 2x8 Micron B dies was working at 4066 mhz with VSOC 1.2125, VDDP 0.86, CCD 0.925, IOD 1.14.
> 
> I tried the timings you said but it wouldn't post at 3600, it posts with 3400 but nothing higher. I tried increasing VDIMM to 1.6 but it wouldn't post. These are the timings now I can post with 3400mhz;
> 
> View attachment 2487215


loosen your tRFC a little, with this

also one can try these timings at 3466 (make sure to add AddrCmdSetup/odt/cke setup timings that
are at the bottom right of the page.
(setting northbridge soc llc to 3 helps on my board) these are bdie sticks that im sharing timings for.
or you can try exporting in nano seconds thru thiaphoon burner, then importing thru dram calc to get a more accurate measure of
what your kit will do. THEN use the mini tRFC calc.

4x8 set btw also, downgrade to agesa 1.2.0.1 as 1.2.0.2 is TRASH from what ive seen so far on getting ram stable.


----------



## PJVol

RonLazer said:


> That's a simplified block diagram, I'm very confused why you think every single component or voltage rail would be labeled. It's only purpose is to show features, for example I might ask "where is the PSP on this diagram?" - but we know the PSP exists.
> 
> You can see the VDDP, and VDDP_sense pins here: https://en.wikichip.org/w/images/f/f8/OPGA-1331_pinmap.svg
> I can't find any explicit documentation right now, but it's referenced as the external voltage here: Community Update #4: Let's Talk DRAM!
> 
> It's possible that it serves some other function, but that seems incredibly unlikely given we know the AM4 pinout precedes the introduction of any LDOs on an AMD CPU. There has to be a PHY (physical interface) to convert signals from the motherboard into data in order to communicate with the CPU prior to being powered on. This is how the CPU controller determines that it's in a suitable motherboard, compatible chipset, is being issued a valid bootloader key etc. Given they seemed to use a single voltage prior to splitting off the new UMC in the Zen2 design, CPU VDDP is likely powering the PHY receiver for "PCIe PHY" and "USB PHY" on your diagram.
> 
> It's also why it's not a required voltage accessible in the AGESA spec - it shouldn't need to be changed regardless of which XMP profile is used - so there's no requirement to expose it. MSI don't even allow you to change it on their XOC boards like the Unify-X, although I've heard this is because they used a fix voltage supply for it and hence can't change it even if the BIOS setting was exposed. Not been able to confirm this, but even the modified BIOS I use doesn't have a setting for it, so it seems reasonable.


I didn't mean every rail should have been shown on that diagram, rather wanted to point out that VDDP seem to has little to do with IO PHY powering (the am4 pins layout you provide suggests something bigger).
For more reading you may check out some SVI2 specs (if you manage to find any) or gather some useful info from pwm datasheets as well (linked below). Corsair refered to it in their Llano DDR docs as something that help to stabilize gpu, memory and whatever else...

What I think (of course I may be wrong here) is VDDP (pumped voltage?) related to a gate drivers along with a certain PWM (Intersil for example), at least you may see it mentioned in 62771, 6377 datasheet, which has them integrated, hence VDDP pin description therefrom:
VDDP: Input voltage bias for the internal gate drivers.
https://www.renesas.com/eu/ja/document/dst/isl6377-datasheet
http://www.sun-flytech.com/images/pdf/20150224ad2d4.pdf

DRAM power controllers has vddp either, btw.
Of course, it would be nice if someone knowlegable shed the light on it further, though R.Hallock explicitly said in the post you linked, it's pre-1.0.0.6 setting, so in other words, deprecated.



RonLazer said:


> This is because it's tied to your SOC voltage and UCLK frequency. the CLDO indicates this voltage is sourced off the CPUs "low dropout regulator" which converts the SOC voltage into other voltages used in normal operation, including the CCD and IOD voltages.


Oh and btw, BIOS devs from Asrock and MSI (see Craxton's screenshot) can argue with you here:


----------



## Iarwa1N

craxton said:


> loosen your tRFC a little, with this
> 
> also one can try these timings at 3466 (make sure to add AddrCmdSetup/odt/cke setup timings that
> are at the bottom right of the page.
> (setting northbridge soc llc to 3 helps on my board) these are bdie sticks that im sharing timings for.
> or you can try exporting in nano seconds thru thiaphoon burner, then importing thru dram calc to get a more accurate measure of
> what your kit will do. THEN use the mini tRFC calc.
> 
> 4x8 set btw also, downgrade to agesa 1.2.0.1 as 1.2.0.2 is TRASH from what ive seen so far on getting ram stable.
> View attachment 2487222


Thanks for the reply. I tried the tRFC values from the link you provided but it didn't worked until I increased the Vdimm to 1.75V  At 1.75v I can boot into windows with this timings;










I didn't see lots of 5600x with dual rank b-dies on the zen ram overclock spreadsheet. Is there a limitation on 5600x that prevents me from going further? I don't think I can use 1.75v as daily :/ I also tried downgrading to 1.2.0.1 but nothing changed.


----------



## Robby37

@Iarwa1N try that and i could not post 1900 even with 16 flat tiings but my fclock is good at 2k so i think its a memory hole but i am pretty stable right now i have been hoping others thatknow more can tell me if i have any area for improvement.I just figure may be worth a shot for you as this posted on my 5800x to and i have 3200 c14 dr 16gb sticks same as you. vdimm is 1.5 and 1.48 worked to


----------



## Iarwa1N

Robby37 said:


> View attachment 2487227
> @Iarwa1N try that and i could not post 1900 even with 16 flat tiings but my fclock is good at 2k so i think its a memory hole but i am pretty stable right now i have been hoping others thatknow more can tell me if i have any area for improvement.I just figure may be worth a shot for you as this posted on my 5800x to and i have 3200 c14 dr 16gb sticks same as you. vdimm is 1.5 and 1.48 worked to


Thanks for the reply. I could only post at 3400 mhz with your timings, nothing higher worked 😞


----------



## Danny.ns

RonLazer said:


> Oh and for anyone confused between CPU VDDP and CLDO_VDDP, the latter will be exposed in the first level of your overclocking menu, and shouldn't need you to venture into any sub-menus. This is because it's tied to your SOC voltage and UCLK frequency. the CLDO indicates this voltage is sourced off the CPUs "low dropout regulator" which converts the SOC voltage into other voltages used in normal operation, including the CCD and IOD voltages.
> 
> In MSI BIOS its just called "VDDP" but will show up in Zentimings and RyzenMaster as CLDO_VDDP if changed. As far as I know its been in the same location in the overclocking menu since at least AGESA 1.1.0.0.
> 
> It is 0.9V by default, but will jump up to 1.1V or 1.2V if you increase SOC or UCLK frequency. This seems to cause pretty serious problems for most overclocks, so I suggest fixing it at 0.9V and only increasing it as a last resort for unreliable memory training or trying to run aggressive overclocks. The other use-case is when you encounter the infamous 1900MHz memory hole, where 1867MHz boots fine but suddenly you can't post at 1900MHz, but can post at 1933MHz. I found that dropping CLDO_VDDP to 0.85V fixed this issue, and it worked on 2 different motherboards and a few other people I suggested it to said it fixed the problem.


I'm one of those that can never POST at fclk1900, but have no problem POSTing at much higher fclk (e.g. 2000). I feel like I have tried "everything" - things like LN2 mode, upping voltages like crazy (1.5vdimm, 1.3vsoc, 1.2v VDDP etc at stock memory settings 2400mhz/auto timings) and still FCLK1900 wont even POST.

I will try your TIP regarding locking/dropping CLDO_VDDP to 0.85V and see if I can POST later today.


----------



## weleh

*Iarwa1N*


Are you on latest bios?

Do a full bios reset (load optimized defaults).

VSOC - 1.125V (no need for LLC).
VDIMM - 1.5V
VDDP - 0.95V
VDDG_CCD - 0.85 to 0.9V
VDDG_IOD - 0.95 to 1.05V

fCLK manually set to 1900
DRAM manually set to 3800
fCLK = uCLK

SoC Uncore = Enabled

ProcODT - 40 Ohm
RTTNOM - RZQ/7
RTTWR - RZQ/3
RTTPARK - RZQ/1

ClkDrvStr - 24 Ohm
CmdDrvStr - 20 Ohm
OdtDrvStr - 24 Ohm
CkeDrvStr - 24 Ohm

GDM On
PowerDown Off
BGS -Off
BGS Alt - On

As for timings don't load XMP, just leave it be and do something like 18 - 20 - 20 - 20 - 40 - 60
Leave the rest on JEDEC.

See if it posts. If it does then you can go down on everything and start tuning. If it doesn't something clearly wrong with your bios.


----------



## Danny.ns

weleh said:


> Are you on latest bios?
> 
> Do a full bios reset (load optimized defaults).
> 
> VSOC - 1.125V (no need for LLC).
> VDIMM - 1.5V
> VDDP - 0.95V
> VDDG_CCD - 0.85 to 0.9V
> VDDG_IOD - 0.95 to 1.05V
> 
> fCLK manually set to 1900
> DRAM manually set to 3800
> fCLK = uCLK
> 
> SoC Uncore = Enabled
> 
> ProcODT - 40 Ohm
> RTTNOM - RZQ/7
> RTTWR - RZQ/3
> RTTPARK - RZQ/1
> 
> ClkDrvStr - 24 Ohm
> CmdDrvStr - 20 Ohm
> OdtDrvStr - 24 Ohm
> CkeDrvStr - 24 Ohm
> 
> GDM On
> PowerDown Off
> BGS -Off
> BGS Alt - On
> 
> As for timings don't load XMP, just leave it be and do something like 18 - 20 - 20 - 20 - 40 - 60
> Leave the rest on JEDEC.
> 
> See if it posts. If it does then you can go down on everything and start tuning. If it doesn't something clearly wrong with your bios.


This isnt anything new for me, it has been like this since december when I got these parts (5900x, dark hero, b die dual rank). I've had every BIOS on the Dark Hero (since release) but I am not on the latest BETA atm, I'm on the latest non-BETA.

I mean, I have tried things like "load optiomized default", and then set;
VSOC - 1.3V
VDIMM - 1.5V
VDDP - 1.2V
VDDG_CCD - 1.2V
VDDG_IOD - 1.2V
(I obviously tried lower values as well as AUTO)
Leaving RAM at 2400mhz (I have obviously also tried 1:1 mode with loose timings) and all timings on AUTO (loose). No POST as soon as I try FCLK 1900. I have tried high procODT (60ohm) and low procODT (28ohm) - no change, no POST. I always have to clear CMOS.

I am not sure if you are aware @weleh, but there are many with these exact same symptoms. There are people in this very thread reporting the exact same thing with different motherboards and BIOSes. I have seen people with MSI, Gigabyte and ASUS motherboards have the same issue.


----------



## mongoled

PJVol said:


> Have never seen it on my two ASRock boards, X370 Taichi and current B550 Extreme4


I am only going from what I have read from Veii and the quick googlefoo I did.

Did you have access to a 5000 series CPU in any of those motherboards when you checked ??


----------



## weleh

Danny.ns said:


> This isnt anything new for me, it has been like this since december when I got these parts (5900x, dark hero, b die dual rank). I've had every BIOS on the Dark Hero (since release) but I am not on the latest BETA atm, I'm on the latest non-BETA.
> 
> I mean, I have tried things like "load optiomized default", and then set;
> VSOC - 1.3V
> VDIMM - 1.5V
> VDDP - 1.2V
> VDDG_CCD - 1.2V
> VDDG_IOD - 1.2V
> (I obviously tried lower values as well as AUTO)
> Leaving RAM at 2400mhz (I have obviously also tried 1:1 mode with loose timings) and all timings on AUTO (loose). No POST as soon as I try FCLK 1900. I have tried high procODT (60ohm) and low procODT (28ohm) - no change, no POST. I always have to clear CMOS.
> 
> I am not sure if you are aware @weleh, but there are many with these exact same symptoms. There are people in this very thread reporting the exact same thing with different motherboards and BIOSes. I have seen people with MSI, Gigabyte and ASUS motherboards have the same issue.


Sorry wasn't meant for you but the other dude having issues.


----------



## mongoled

craxton said:


> wait, you actually got a response from msi...
> 
> ive sent 9 emails within 3 months and have got JACK SQUAT back lol... it would seem others in MSI forums are trying to get
> this unlocked as well.


Then the first time you asked a question it must have been a question they didnt like so they blanked you ??

😂😂 

The pattern for me is that they repond at first and then if its a question they dont have an answer to or goes against what they "know to be true" they then start blanking you.

Do you log in to your MSI account to see if there is an answer to your ticket ??


----------



## weleh

Danny.ns said:


> This isnt anything new for me, it has been like this since december when I got these parts (5900x, dark hero, b die dual rank). I've had every BIOS on the Dark Hero (since release) but I am not on the latest BETA atm, I'm on the latest non-BETA.
> 
> I mean, I have tried things like "load optiomized default", and then set;
> VSOC - 1.3V
> VDIMM - 1.5V
> VDDP - 1.2V
> VDDG_CCD - 1.2V
> VDDG_IOD - 1.2V
> (I obviously tried lower values as well as AUTO)
> Leaving RAM at 2400mhz (I have obviously also tried 1:1 mode with loose timings) and all timings on AUTO (loose). No POST as soon as I try FCLK 1900. I have tried high procODT (60ohm) and low procODT (28ohm) - no change, no POST. I always have to clear CMOS.
> 
> I am not sure if you are aware @weleh, but there are many with these exact same symptoms. There are people in this very thread reporting the exact same thing with different motherboards and BIOSes. I have seen people with MSI, Gigabyte and ASUS motherboards have the same issue.


I've seen some other dude with a 1900 fCLK hole on a X570 Unify.
Very unlucky.

This is a dude I helped recently.
1.5V dimm


----------



## PJVol

mongoled said:


> Did you have access to a 5000 series CPU in any of those motherboards when you checked ??


(Lol, forgot to quote your post)
Yes, 5600x is in extreme4 now, 100% sure vddp wasnt there ever, just curious, what it has to do with 5000 series. TBH, it possibly was in Taichi long ago, x570 bios screens kinda refreshed my memory )), and as Hallock said, its pre-1.0.0.6 setting, and then it simply gone.


----------



## Sleepycat

Iarwa1N said:


> Thanks for the reply. I tried the tRFC values from the link you provided but it didn't worked until I increased the Vdimm to 1.75V  At 1.75v I can boot into windows with this timings;
> 
> View attachment 2487225
> 
> 
> I didn't see lots of 5600x with dual rank b-dies on the zen ram overclock spreadsheet. Is there a limitation on 5600x that prevents me from going further? I don't think I can use 1.75v as daily :/ I also tried downgrading to 1.2.0.1 but nothing changed.


Have you tried setting tRCDRD to 15?


----------



## paih85

Iarwa1N said:


> Your settings didn't post either, thank you for the response. It won't event post at 3400 mhz with your settings.
> 
> 
> 
> Thank you for the response. I only tried that high VSOC and other voltages because it wouldn't post with anything lower and I know that my previous 2x8 Micron B dies was working at 4066 mhz with VSOC 1.2125, VDDP 0.86, CCD 0.925, IOD 1.14.
> 
> I tried the timings you said but it wouldn't post at 3600, it posts with 3400 but nothing higher. I tried increasing VDIMM to 1.6 but it wouldn't post. These are the timings now I can post with 3400mhz;
> 
> View attachment 2487215



try trdwr / twrrd = 8 / 3


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> to test using y-cruncher usually one uses 1-7-0 with a minimum of 4 loops
> if your unstable itll show rather usually quickly.
> 
> at this time you can find what your looking for on this forum somewhere, i just looked for around 15 min
> and couldn't find it, perhaps i overlooked it (regarding proc/databus settings to use)
> 
> i can say, since your running a 3000 series chip, going back at least 100 pages is where you can start searching for
> what works and doesnt. then again??
> 
> are you running 2x16 or 4x8? and 2t GDM off is easier to run, while not having much
> penalty from what ive gathered.
> 
> this link and this one too will help somewhat. but the one i was looking for had
> timings for 2000 chips, 3000, and 5000 chips. but as stated above i couldnt find it.
> 
> those are verified working with proof of stability. but again, i couldnt find it.
> perhaps someone reading will share it in a reply
> 
> i myself (on a 3600xt) was only able to get 3800mhz stable 1T CR c16 flat 2x8 config.
> 
> so, if your stable (not only with TM5) but with y-crunch ( 1,7,0 ) OCCT, HCI, and prime 95 then
> id settle for that personally lol.
> 
> (wouldnt i be elsewhere tho if i could persanally settle with 4000mhz stable? 😆)
> 
> im not the best equipped to answer most of your question, its not likely youll get a response due
> to most of what your asking already being (back further in this thread as this pertains to Ryzen of all nodes)
> as well as most are focused on 5000 chips.
> 
> have you given dram calc a shot? export your xmp profile in nanseconds using T/B then import to dram calc?


Yup, it's been stable throughout TM5, OCCT (Linpack, CPU, and Memory tests), P95's large FFTs, I just ran y-cruncher (like you'd said to) overnight from last night until this morning... Should be stable enough








I'll head to those links you posted and start digging my way back here from like... Page 200 or something... to read more on Zen 2

Thanks dude! I really appreciate your help and your time!


----------



## craxton

mongoled said:


> Then the first time you asked a question it must have been a question they didnt like so they blanked you ??
> 
> 😂😂
> 
> The pattern for me is that they repond at first and then if its a question they dont have an answer to or goes against what they "know to be true" they then start blanking you.
> 
> Do you log in to your MSI account to see if there is an answer to your ticket ??


yea actually im logged in now, but still no reply.
its possible they have blanked me honestly. i truly dont understand why its so hard
to unlock this option inside the bios since it only takes a few seconds to do so.

i never sent it in form of a ticket. i just wrote support directly, but NOW that you
MENTIONED this. ive wrote another response using their ticket option.  thanks


----------



## Danny.ns

RonLazer said:


> It is 0.9V by default, but will jump up to 1.1V or 1.2V if you increase SOC or UCLK frequency. This seems to cause pretty serious problems for most overclocks, so I suggest fixing it at 0.9V and only increasing it as a last resort for unreliable memory training or trying to run aggressive overclocks. The other use-case is when you encounter the infamous 1900MHz memory hole, where 1867MHz boots fine but suddenly you can't post at 1900MHz, but can post at 1933MHz. I found that dropping CLDO_VDDP to 0.85V fixed this issue, and it worked on 2 different motherboards and a few other people I suggested it to said it fixed the problem.


Just to update, I tried: 
1900FCLK CLDO_VDDP 0.85V
1900FCLK CLDO_VDDP 0.80V
1900FCLK CLDO_VDDP 0.75V
1900FCLK CLDO_VDDP 0.85V + VSOC 1.1
(rest of bios reset to defaults)

No POST.


----------



## craxton

RonLazer said:


> It is 0.9V by default, but will jump up to 1.1V or 1.2V if you increase SOC or UCLK frequency.


im unsure this is the case? see attached zen timings, or further iterate why
mine is not fluctiaing as you stated upping SOC as mine is 1.2xx otherwise instability shows
drastically.











Danny.ns said:


> Just to update, I tried:
> 1900FCLK CLDO_VDDP 0.85V
> 1900FCLK CLDO_VDDP 0.80V
> 1900FCLK CLDO_VDDP 0.75V
> 1900FCLK CLDO_VDDP 0.85V + VSOC 1.1
> (rest of bios reset to defaults)


why under 900mv? and what CCD/IOD voltage ranges have you tried?
cad_bus strengths can and will make or break your ram training all together or kill
dimms as another user here has had happened his name ill leave out.

but yea, i didnt catch all of what your ram is, SR DR? or 4x8 (would run similar to 2x16)
i can post these timings all the way up to 4066 i believe on MSI bios revision E7C91AMS.161 (agesa 1.2.0.1)
b550 gaming edge board while, the latest bios released i cant post but one time with these timings (yes the first boot)

right after the flashing was done, i re did all my timings/settings etc, and posted no issues, then upon rebooting
trying to go to bios, my speakers popped?? but once inside bios it was hung...( point is if your on MSI dont use the latest bios )
somethings not quite right with it...

considering i believe your running the latest bios, do try a flashback off another bios revision and test again
applying what you know now to where you didnt before.


----------



## PJVol

craxton said:


> why
> mine is not fluctiaing as you stated upping SOC as mine is 1.2xx otherwise instability shows
> drastically.


SMU init code will set vddp/vddg too high if you for example set Vsoc in bios to 1.200 and leave the rest at "auto", and of course it won't override them if implicitly set.


----------



## craxton

PJVol said:


> won't override them if implicitly set


mines set to auto tho lol.

thats why im curious.


----------



## PJVol

You're lucky then ))


----------



## RonLazer

My Dark Hero keeps CLDO_VDDP around 0.9V but my MSI boards will yeet it if allowed to on auto, and I know at least some gigabyte boards do the same.


----------



## RonLazer

Danny.ns said:


> Just to update, I tried:
> 1900FCLK CLDO_VDDP 0.85V
> 1900FCLK CLDO_VDDP 0.80V
> 1900FCLK CLDO_VDDP 0.75V
> 1900FCLK CLDO_VDDP 0.85V + VSOC 1.1
> (rest of bios reset to defaults)
> 
> No POST.


Sorry to be clear this is for solving memory holes, not issues with FCLK not posting. The only suggestion I have on that front is to try booting at 1867MHz, setting 1.15V SOC and 1.95V PLL (might be called 1P8 if you have an MSI board) and rebooting (still at 1867MHz) then setting 1900MHz FCLK and rebooting. This is because some voltages seem to be modified later in the boot process than the FCLK clock is set, so I always modify voltages THEN set FCLK.

I can't promise it will work, every chip has a certain frequency which it will just fail to post at, on both my chips its 2100MHz, but I know some people can't do 1933 or even 1900 (in 1 case I know of).


----------



## craxton

PJVol said:


> You're lucky then ))


yes i have to assume im possibly the luckiest here since i dont have 
WHEA errors, no usb dropout, no audi crackle, really no issues at all really.
OTHER than the ones i make for myself by adjusting/trying to tighten 4x8 bdie sticks (that are NOT a 4 stick set)
they are the same name/model/maker etc, but were made at different times to which tRFC, tRAS, TRRD_S/L on two sticks are 
way WAY better than the other two which were bought at a later time from newegg. the better set was bought 
off amazon. i believe this is why i cant really get much better out of 4 sticks.


----------



## TimeDrapery

RonLazer said:


> Spoiler
> 
> 
> 
> Sorry to be clear this is for solving memory holes, not issues with FCLK not posting. The only suggestion I have on that front is to try booting at 1867MHz, setting 1.15V SOC and 1.95V PLL (might be called 1P8 if you have an MSI board) and rebooting (still at 1867MHz) then setting 1900MHz FCLK and rebooting. This is because some voltages seem to be modified later in the boot process than the FCLK clock is set, so I always modify voltages THEN set FCLK.
> 
> I can't promise it will work, every chip has a certain frequency which it will just fail to post at, on both my chips its 2100MHz, but I know some people can't do 1933 or even 1900 (in 1 case I know of).


Great info! Thanks for that clarification!


----------



## lmfodor

RonLazer said:


> That's a simplified block diagram, I'm very confused why you think every single component or voltage rail would be labeled. It's only purpose is to show features, for example I might ask "where is the PSP on this diagram?" - but we know the PSP exists.
> 
> You can see the VDDP, and VDDP_sense pins here: https://en.wikichip.org/w/images/f/f8/OPGA-1331_pinmap.svg
> I can't find any explicit documentation right now, but it's referenced as the external voltage here: Community Update #4: Let's Talk DRAM!
> 
> It's possible that it serves some other function, but that seems incredibly unlikely given we know the AM4 pinout precedes the introduction of any LDOs on an AMD CPU. There has to be a PHY (physical interface) to convert signals from the motherboard into data in order to communicate with the CPU prior to being powered on. This is how the CPU controller determines that it's in a suitable motherboard, compatible chipset, is being issued a valid bootloader key etc. Given they seemed to use a single voltage prior to splitting off the new UMC in the Zen2 design, CPU VDDP is likely powering the PHY receiver for "PCIe PHY" and "USB PHY" on your diagram.
> 
> It's also why it's not a required voltage accessible in the AGESA spec - it shouldn't need to be changed regardless of which XMP profile is used - so there's no requirement to expose it. MSI don't even allow you to change it on their XOC boards like the Unify-X, although I've heard this is because they used a fix voltage supply for it and hence can't change it even if the BIOS setting was exposed. Not been able to confirm this, but even the modified BIOS I use doesn't have a setting for it, so it seems reasonable.


Wow, this is very interesting. I must admit that in this time I learned a little about Mem OC and one of the concepts is to think about relationships, values, which are often not fulfilled, because there are a lot of unwritten rules. The mistake is to think of Benchmarks, as if one touches a value and everything improves. This I learned from reading the entire thread from the beginning. There's a lot of valuable information. However, I find myself locked in great challenge, and not obsessive but wanting to get the most out of new RAMs that are 3800CL14 1.5V of manufacture, and that many are running in 3800-14-14-14-28 easily and I can't get it. As well under tRCD, at 15 or 14, with any of the combinations of tWRD/tWTR, and TRP, tRWCRD, among others, I have a constant and unlimited 6 error in TM5 1usmus. But on the other hand, with my current configuration, super stable, having passed more than 10 tests of 25 cycles of 1usmus, HCI memtest Deluxe, OOCT, y-cruncher all test for hours many times, I have excellent bandwidth and latency. And I also listened to master @Veii and lowered the BIOS version to SMU 54.45 and incredibly the L3 cache values are much lower and more real, but most importantly than quite similar. I had read that one way to determine if the SOC values are correct is that between read and write values there should not be a difference greater than 50GBs.

These are my current settings. 










Maybe I can optimize relationships. I know that tRASiis in line with the rule of tRCD + TRP +2, and then tRC, I also tight tRRD and tWRD, also tFAW and maybe I could lower tWR. tRFS seems to be fine, could be lower, then the SCL are fine in 4, tRTP match ther rule, and as I have DR tRDWR should be 9 by rule, tWRDD could be 2, and the SC, DD are fine for DR 1-4-4-16-6. Regarding ProcODT and RTT / CAD-BUS I think a should leave on AUTO, I mean, with the defaulf values that are ProctODT in 43ohms, RTTNom Disables, RttWr in 3, RttParkin 1, and Cad-Bus24 flat. All this with 1.5v of VDIMM that is the default. I need to understand better the relationship between the tRRDs and tWRDs and the tRDWR andt WRRD, that for me are almost a fixed value.. So I'm still doesn't understand what should tight or loose if I change the tRRDs and tWRDs.

I found that I share almost the same configuration with @gabian. Both have the same memory kit, he has the CH8 Dark Hero and I the Wifi version, he has a 5950 and I the 5900. He can run 3800-14-14-14 and just a few subtimings and all the rest set in Auto, the tRFC, the ProctODT, the Rtts, Cad-Bus and even all voltage on Auto. Even the Digi - Power Menu all in Auto and he hasn't had any errors in TM5. So what I did? I ask him for with BIOS auto and copied all the values.. same PBO, the exact same values.. but I didn't word. And also I see that Igors, even with all in Auto (VSOC, 1.5 VDIMM, RTTs, CADBUS, he could run 3800-14-14-14 flat with the only issue of a little heat due he didn't have an active cooler in his test. An he runs a MSI Board. So in conclusion, it's my mobo and some Voltage Settings that prevent memories from starting to work due to some IMC settings, I mean a Voltage value.

This is how @gabian is running (whit 14 flat, tRCD in 14)









I also try @Veiis settings, with the AMD exploit of tRC = tRAS +1 and tFAW lower to 8, with tight tWRR and TRDDs. Yes, I copied his VSOC that is extremly high but I know Veii is running a higher VDIMM. This would be a mistake for my setup, because this memory kits seems to run fine with 1.5v 14-14-14 flat.. so there's no need to increase the voltage at least for this settings. Maybe I'm wrong. I've increased the VDIMM to 1.58V, 1.6, 1.55.. tried a lower vSOC of 1.07/8/10 and so on until 1.15. Also I tried VDDG and IOD until 1, but I respect the rule of .5mV below of VSOC for the IOD and CCD below 0.95 and always VDDP below 0.9.









Well, as you can see I'm a little bit lost of what would be my next step. If you were in my place, and would you like to try 3800 14 flat, which is proven to be achieved, what would you do in a step by step? I mean to keep testing and learning. 
Thanks a lot!


----------



## RonLazer

lmfodor said:


> Wow, this is very interesting. I must admit that in this time I learned a little about Mem OC and one of the concepts is to think about relationships, values, which are often not fulfilled, because there are un written rules. The mistake is to think of Benchmarks, as if one touches a value and everything improves. This I learned from reading the entire thread from the beginning. There's a lot of valuable information. However, I find myself locked in great challenge, and not obsessive but wanting to get the most out of new RAMs that are 3800CL14 1.5V of manufacture, and that many are running in 3800-14-14-14-28 easily and I can't get it. As well under tRCD, at 15 or 14, with any of the combinations of tWRD/tWTR, and TRP, tRWCRD, among others, I have a constant and unlimited 6 error in TM5 1usmus. But on the other hand, with my current configuration, super stable, having passed more than 10 tests of 25 cycles of 1usmus, HCI memtest Deluxe, OOCT, y-cruncher all test for hours many times, I have excellent bandwidth and latency. And I also listened to master @Veii and lowered the BIOS version to SMU 54.45 and incredibly the L3 cache values are much lower and more real, but most importantly than quite similar. I had read that one way to determine if the SOC values are correct is that between read and write values there should not be a difference greater than 50GBs.
> 
> This is my current settings.
> 
> View attachment 2487288
> 
> 
> Maybe I can optimize relationships. I know that tRASiis in line with the rule of tRCD + TRP +2, and then tRC, I also tight tRRD and tWRD, also tFAW and maybe I could lower tWR. tRFS seems to be fine, could be lower, then the SCL are fine in 4, tRTP match ther rule, and as I have DR tRDWR should be 9 by rule, tWRDD could be 2, and the SC, DD are fine for DR 1-4-4-16-6. Regarding ProcODT and RTT / CAD-BUS I think a should leave on AUTO, I mean, with the defaulf values that are ProctODT in 43ohms, RTTNom Disables, RttWr in 3, RttParkin 1, and Cad-Bus24 flat. All this with 1.5v of VDIMM that is the default. I need to understand better the relationship between the tRRDs and tWRDs and the tRDWR andt WRRD, that for me are almost a fix value.. So I'm still doesn't understand what should tight or loose if I change the tRRDs and tWRDs.
> 
> I found that I share almost the same configuration with @gabian. Both have the same memory kit, he has the CH8 Dark Hero and I the Wifi version, he has a 5950 and I the 5900. He can run 3800-14-14-14 and just a few subtimings and all the rest set in Auto, the tRFC, the ProctODT, the Rtts, Cad-Bus and even all voltage on Auto. Even the Digi - Power Menu all in Auto and he hasn't had any errors in TM5. So what I did? I ask him for with BIOS auto and copied all the values.. same PBO, the exact same values.. but I didn't word. And also I see that Igors, even with all in Auto (VSOC, 1.5 VDIMM, RTTs, CADBUS, he could run 3800-14-14-14 flat with the only issue of a little heat due he didn't have an active cooler in his test. An he runs a MSI Board. So in conclusion, it's my mobo and some Voltage Settings that prevent memories from starting to work due to some IMC settings, I mean a Voltage value.
> 
> This is how @gabian is running (whit 14 flat, tRCD in 14)
> View attachment 2487289
> 
> 
> I also try @Veiis settings, with the AMD exploit of tRC = tRAS +1 and tFAW lower to 8, with tight tWRR and TRDDs. Yes, I copied his VSOC that is extremly high but I know Veii is running a higher VDIMM. This would be a mistake for my setup, because this memory kits seems to run fine with 1.5v 14-14-14 flat.. so there's no need to increase the voltage at least for this settings. Maybe I'm wrong. I've increased the VDIMM to 1.58V, 1.6, 1.55.. tried a lower vSOC of 1.07/8/10 and so on until 1.15. Also I tried VDDG and IOD until 1, but I respect the rule of .5mV below of VSOC for the IOD and CCD below 0.95 and always VDDP below 0.9.
> View attachment 2487290
> 
> 
> Well, as you can see I'm a little bit lost of what would be my next step. If you were in my place, and would you like to try 3800 14 flat, which is proven to be achieved, what would you do in a step by step? I mean to keep testing and learning.
> Thanks a lot!


I've actually never seen proof of anyone running tRCDRD 14 at 3800MHz or higher, I think the Zen3 memory controller simply cannot handle below 7.5ns, since 4000MHz tRCDRD 15 works, and 3733MHz tRCDRD 14 also works. Using dual-rank dimms is going to kill any chance of stretching the memory controller limit even if it was possible. I would suspect your friend is either not running proper stress tests, or got extremely lucky in the silicon lottery.

You'll have to drop to 3733MHz or increase tRCDRD to 15.


----------



## lmfodor

RonLazer said:


> I've actually never seen proof of anyone running tRCDRD 14 at 3800MHz or higher, I think the Zen3 memory controller simply cannot handle below 7.5ns, since 4000MHz tRCDRD 15 works, and 3733MHz tRCDRD 14 also works. Using dual-rank dimms is going to kill any chance of stretching the memory controller limit even if it was possible. I would suspect your friend is either not running proper stress tests, or got extremely lucky in the silicon lottery.


Yes, i know the voltage and subs are all out of sync. If you see the Igor’s review he also runs all on auto. I know it’s bad, in fact his bench’s are lower than mine. But I just want to try a procedure, step but step to try to lower my TRCD starting from my current stable settings. It’s not than easy

I even suspect about my LLC values.. and some other settings like SOC Uncore, I have the DF and C states disabled, CCPC And preferred cores enable. Broad spectrum disabled and a good curve very worked of PBO2
This are my DIGI-Power Sub menu (LLCs) that Veii sent me


Spoiler














I don’t know if the SOC/uncore enabled could impact in my errores. I have set the DPM LCK to 2-1-1-1-2-1-1-1. 

If you see my first picture with my stable settings you would see how the L3 changed .: before the values were above 1GBs and all out of sync. 

I wonder what would be a good procedure to try to lower my primaries, better said my tRCD.. that’s my challenge. 

PS: I also thought to change my mobo.. or to the dark Hero that has a better VRM or to a MSI Unify-x.. but I do not want to lower my arms, I want to continue testing to understand where the problem is, why do I have so many errors 6 in TM5 1usmus?.. that according to what I read are related to some value of voltage or resistance

Thanks!


Sent from my iPhone using Tapatalk Pro


----------



## Robby37

Iarwa1N said:


> Thanks for the reply. I could only post at 3400 mhz with your timings, nothing higher worked 😞


Try my timings but trfc at 288 i have a very aggressive setting actually here lmk try something


----------



## Robby37

RonLazer said:


> I've actually never seen proof of anyone running tRCDRD 14 at 3800MHz or higher, I think the Zen3 memory controller simply cannot handle below 7.5ns, since 4000MHz tRCDRD 15 works, and 3733MHz tRCDRD 14 also works. Using dual-rank dimms is going to kill any chance of stretching the memory controller limit even if it was possible. I would suspect your friend is either not running proper stress tests, or got extremely lucky in the silicon lottery.
> 
> You'll have to drop to 3733MHz or increase tRCDRD to 15.


The odd thing is i run very tight cl14 at 3733 and i can run 4000 on fclock but i cannot post 1900 for my life and i have 4 dual rank sticks at 64gb so i am stressing the controller hard. also i need 40202020 or 60202020 with 4,4,18 rtt timings and i have posted the threadripper drive strengths but its intermittent so i stick to the 40.20.20.20


----------



## Robby37

Iarwa1N said:


> Thanks for the reply. I could only post at 3400 mhz with your timings, nothing higher worked 😞










try that with trfc 288 and the other trfcs on auto or maybedo all on autoor the next multiple up think 324 or something


----------



## Robby37

Sleepycat said:


> Here, try my settings. I'm running the non-RGB version of your kit, and I have 4x16GB, stable without errors at 3600/1800 IF at much tighter timings. It also works at 1T GDM on, which I was using before setting to 2T GDM off to test. I tested using TM5, OCCT Extreme Large and Prime95 Large.
> 
> vSOC 1.09V (LLC1)
> CLDO VDDP 1.0V
> VDDG CCD 0.95V
> VDDG IOD 1.05V
> vDIMM 1.46V
> 
> View attachment 2487210
> 
> View attachment 2487211


Why the 8 trcdwr? and why so high trc


----------



## craxton

@TimeDrapery i found what i was looking for the other day.

this is it sad truth is, it was indeed bookmarked and right on my bookmark toolbar none the less.

anyhow there ya go, zen OF ALL NODES bud. good luck


----------



## craxton

@Veii who do i submit or where do i submit my zen timings shot at or too? 
with OCCT, TM5, and y-cruncher sets as well as windows logs?

to get on this zen timings list? ive looked over the entire page, the question of "where do i submit to"
is not among the questions in FAQ


----------



## craxton

RonLazer said:


> some voltages seem to be modified later in the boot process


considering once a bios flash is done, (same bios in mind) 
what was stable wont post. but one can post defaults then, load previous settings

(4000mhz or whatever they had) and posting happens, so ill be sure to keep this in mind as well.
since ive noticed soc voltage does the same (not all the time) but sometimes when i reflash a bios back 
to stock. 

i honestly believe the AMD overclocking section under "advanced" inside MSI bios is an issue that really
should NOT be there to begin with, since NO MATTER whats set there in AMD section of the bios
the main page will always take priority. (on both MSI boards ive ran 5000 chips on have anyhow)
persay, setting 1.2 soc on main, and 1100 in AMDs section, always does the main page set 1.2.

so, i dont use AMDs section to overclock. unsure if anyone else uses it or not, but honestly does anyone know the point of 
why its included? even PBO values dont take if something else has been set inside the main overclocking page.


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> @TimeDrapery i found what i was looking for the other day.
> 
> this is it sad truth is, it was indeed bookmarked and right on my bookmark toolbar none the less.
> 
> anyhow there ya go, zen OF ALL NODES bud. good luck



@craxton

Happens to me all the time! Still haven't found the best way to manage all my bookmarks... 😂😂😂😂😂










😁😁😁😁😁


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> @Veii who do i submit or where do i submit my zen timings shot at or too?
> with OCCT, TM5, and y-cruncher sets as well as windows logs?
> 
> to get on this zen timings list? ive looked over the entire page, the question of "where do i submit to"
> is not among the questions in FAQ



@craxton 

Insert a new row at the bottom of the sheet you linked me to, utilize an image hosting site to obtain a link to your screens, and include that link as a note on the stability test cell of your new row


----------



## Iarwa1N

Thanks for the help guys.



weleh said:


> *Iarwa1N*
> 
> 
> Are you on latest bios?
> 
> Do a full bios reset (load optimized defaults).
> 
> VSOC - 1.125V (no need for LLC).
> VDIMM - 1.5V
> VDDP - 0.95V
> VDDG_CCD - 0.85 to 0.9V
> VDDG_IOD - 0.95 to 1.05V
> 
> fCLK manually set to 1900
> DRAM manually set to 3800
> fCLK = uCLK
> 
> SoC Uncore = Enabled
> 
> ProcODT - 40 Ohm
> RTTNOM - RZQ/7
> RTTWR - RZQ/3
> RTTPARK - RZQ/1
> 
> ClkDrvStr - 24 Ohm
> CmdDrvStr - 20 Ohm
> OdtDrvStr - 24 Ohm
> CkeDrvStr - 24 Ohm
> 
> GDM On
> PowerDown Off
> BGS -Off
> BGS Alt - On
> 
> As for timings don't load XMP, just leave it be and do something like 18 - 20 - 20 - 20 - 40 - 60
> Leave the rest on JEDEC.
> 
> See if it posts. If it does then you can go down on everything and start tuning. If it doesn't something clearly wrong with your bios.


I tried your suggestion on both Agesa 1.1.9.0 and on latest 1.2.0.2 but it didn't even post on 3600. It did boot up on 3600 when I increased vDimm to 1.75v, but nothing below 1.75v works.



paih85 said:


> try trdwr / twrrd = 8 / 3


It didn't worked with the timings I posted below at 3600, only worked if I increased vDimm to 1.75v as I said below.



Robby37 said:


> Try my timings but trfc at 288 i have a very aggressive setting actually here lmk try something


Your timings with trfc 288 didn't boot at 3600 unless I increased the vDimm to 1.75v, then it boots.



Sleepycat said:


> Have you tried setting tRCDRD to 15?


I tried 15 but didn't work as well, even if I try 18-20-20-20-40-60 as I said above it doesn't boot even at 3600 unless I increase vDimm to 1.75, then it boots.



Robby37 said:


> View attachment 2487297
> try that with trfc 288 and the other trfcs on auto or maybedo all on autoor the next multiple up think 324 or something


Thanks for the help. It didn't boot at 3600 with this timings and I tried tRFC 288, 352, 440, all on auto, tRCDRD 15. It did boot with your exact timings at 3600 with 1.75v on dimms.


----------



## TimeDrapery

Iarwa1N said:


> Spoiler
> 
> 
> 
> Thanks for the help guys.
> 
> 
> 
> I tried your suggestion on both Agesa 1.1.9.0 and on latest 1.2.0.2 but it didn't even post on 3600. It did boot up on 3600 when I increased vDimm to 1.75v, but nothing below 1.75v works.
> 
> 
> 
> It didn't worked with the timings I posted below at 3600, only worked if I increased vDimm to 1.75v as I said below.
> 
> 
> 
> Your timings with trfc 288 didn't boot at 3600 unless I increased the vDimm to 1.75v, then it boots.
> 
> 
> 
> I tried 15 but didn't work as well, even if I try 18-20-20-20-40-60 as I said above it doesn't boot even at 3600 unless I increase vDimm to 1.75, then it boots.
> 
> 
> 
> Thanks for the help. It didn't boot at 3600 with this timings and I tried tRFC 288, 352, 440, all on auto, tRCDRD 15. It did boot with your exact timings at 3600 with 1.75v on dimms.



@Iarwa1N 

Are you setting 1.7500V VDIMM to overcome some obstacle preventing you from running your kit that's imposed by your system's hardware?

Where in your BIOS are you configuring your timing sets/voltages?


----------



## craxton

TimeDrapery said:


> @craxton
> 
> Insert a new row at the bottom of the sheet you linked me to, utilize an image hosting site to obtain a link to your screens, and include that link as a note on the stability test cell of your new row


theres no option to add a new row, or anyway i can edit the page. its been locked down due to others
not being able to keep there own scores straight and not mess with others.


was it recently you added your own? i could have sworn in the FAQ it states its locked and is edited and sorted thursdays.

NEVER MIND once again the answer was in front of me, to which i
didnt look at #view to which needed edit or to simply remove it all together. SMH


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> theres no option to add a new row, or anyway i can edit the page. its been locked down due to others
> not being able to keep there own scores straight and not mess with others.
> 
> 
> was it recently you added your own? i could have sworn in the FAQ it states its locked and is edited and sorted thursdays.





Spoiler















You just gotta scroll to the bottom and start typing in the first blank row there

It's the submitted and sorted results that are locked from what I understand... People gotta make sure we all remember why we can't have nice things so we don't get complacent and start acting all civilized...ish 😂😂😂😂😂


----------



## Iarwa1N

TimeDrapery said:


> @Iarwa1N
> 
> Are you setting 1.7500V VDIMM to overcome some obstacle preventing you from running your kit that's imposed by your system's hardware?
> 
> Where in your BIOS are you configuring your timing sets/voltages?


I am configuring the timings on the Asus side of the bios, voltages and the timings under the AI Tweaker tab. Do I need to make them on the AMD specific sub-menus which are on the advanced tab? Does that make any difference? I had 2x8 Micron B-dies and I had no trouble making them run at 4066 with FCKL 2033 using the same Asus side of the bios. The cpu and the mobo is the same, only change is the memory, 2x16 Samsung B-die. I set the vdimm to 1.75v just to see if it will work at all, I was frustrated that nothing works above 3400 mhz not even with absurd timings like 22-22-22. What does it tells if the timings does not work below 1.75v, does it mean that I get really bad Samsung b-dies?


----------



## craxton

TimeDrapery said:


> You just gotta scroll to the bottom and start typing in the first blank row there


lol not quite, if you click the link i posted which is here
it should make it so your in VIEWER mode only and not allow edit/adding
anything of your own. but, i noticed i was in edit mode, since i had the same thing with
tRFC mini calc that was posted to which i (for an entire day) couldnt use the thing lol

yes, im not to familiar with gdoc/sheets at all. but im getting there. i simply wished i would have
read what it said about being able to add multiple screen shots/how to do so.

Its no wonder i was never answered, probably wondering WT# did i mean, where....
if it were a snake it wuda bit me right in the mfn nose.



Spoiler: (random input)



dropped something on my keyboard earlier G413 carbon and now im getting like 4 fff)
time to tear down and resolder again... lasted 3 years so far lol....good thing i have other replacement keys...
last time it was k, num pad /, *, -, + and 8 sometimes best 20 bucks ever spent


----------



## lmfodor

Well, tired of trying 3800-14-14-14 encourages me to try 4000-14-16-16-16 with a low voltage (1.6 VDIMM) and I have much less error in TM5! Incredible, I also have errors 6, and then 12, and then 2.. but much less frequent and in different tests, it does not fail as much as in 3800.... So.. Any one I accept any advice to continue. I am in very deep and dangerous waters!! Let's go! shoot me, I know should I rise VDIMM.. I know VDDP is high. SC DDs are bad. I'm trying to stay safe with weaker RTT to sustain the voltage. What should I do to improve, raise the voltage to 1.64..up from 1mv? or touch SC DD, GDM Off, 2T, TRfS first? Thank you!


----------



## TimeDrapery

Iarwa1N said:


> Spoiler
> 
> 
> 
> I am configuring the timings on the Asus side of the bios, voltages and the timings under the AI Tweaker tab. Do I need to make them on the AMD specific sub-menus which are on the advanced tab? Does that make any difference? I had 2x8 Micron B-dies and I had no trouble making them run at 4066 with FCKL 2033 using the same Asus side of the bios. The cpu and the mobo is the same, only change is the memory, 2x16 Samsung B-die. I set the vdimm to 1.75v just to see if it will work at all, I was frustrated that nothing works above 3400 mhz not even with absurd timings like 22-22-22. What does it tells if the timings does not work below 1.75v, does it mean that I get really bad Samsung b-dies?



@Iarwa1N 



Iarwa1N said:


> Do I need to make them on the AMD specific sub-menus which are on the advanced tab?


No, but... Yes 😂😂😂😂😂... I'll explain



Iarwa1N said:


> Does that make any difference?


Where they're entered doesn't matter as much (from what I've observed while working with various Socket AM4 motherboards) as it does to ensure that they're either only entered in one of the menus or filled the same in all three (although, the AMD Overclocking DRAM submenu is less bossy than the AMD CBS submenu that requires you to input hexadecimal values, so maybe you'd get away with that one being different...)

I find it interesting, and it's what prompted me to investigate this further, that inputting your values and configuring your overclock using Ryzen Master with the persistent values option enabled edits and/or fills all three DRAM submenus

When you OC in the vendor's OC section you'll notice the CBS submenu is modified after a successful boot (this is part of why clearing CMOS properly is so essential) and if you go back to the vendor side and modify your timing set again, and successfully boot, the CBS submenu will change to match

If your system ****s it all up, as it is wont to do... no sweat, they all are, and you don't POST or you cut the power during memory training ad infinitum, whatever happens... Some things changed based off your input, some didn't

So you get back in BIOS, load your last known stable profile, try to boot but then find your once stable profile will not get you to your OS anymore

Should've just cleared CMOS right away, it's what must be done now and you'd have saved time

Only the settings that are exposed are the ones that can be observed... Who knows what havoc was wreaked on the hidden settings or the exposed ones on Auto

Some nuts go so far as to USB Flashback on a failure to POST, that seems silly but I'll bet there's something I'm missing about why they're going to such lengths that would have it make sense



Iarwa1N said:


> What does it tells if the timings does not work below 1.75v, does it mean that I get really bad Samsung b-dies?


That's a very good question, one which I'd like to know the answer to as well


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> lol not quite, if you click the link i posted which is here
> it should make it so your in VIEWER mode only and not allow edit/adding
> anything of your own. but, i noticed i was in edit mode, since i had the same thing with
> tRFC mini calc that was posted to which i (for an entire day) couldnt use the thing lol
> 
> yes, im not to familiar with gdoc/sheets at all. but im getting there. i simply wished i would have
> read what it said about being able to add multiple screen shots/how to do so.
> 
> Its no wonder i was never answered, probably wondering WT# did i mean, where....
> if it were a snake it wuda bit me right in the mfn nose.
> 
> 
> 
> Spoiler: (random input)
> 
> 
> 
> dropped something on my keyboard earlier G413 carbon and now im getting like 4 fff)
> time to tear down and resolder again... lasted 3 years so far lol....good thing i have other replacement keys...
> last time it was k, num pad /, *, -, + and 8 sometimes best 20 bucks ever spent



Here, let's test...

I just tapped the link in your post and input "aaa" into the first cell in the first column of the first open row on the Zen 2 DRAM OC sheet

Now you tap the same link and navigate to where I described inputting "aaa" and tell me if you see it there

Here's a screenshot of my edit


Spoiler

















Spoiler



That's a bummer about the keyboard! Can you put it in the dishwasher??? 😂😂😂😂😂

Edit: Oh! I think I misunderstood! 😂😂😂😂😂, you mean you dropped an object (not food or drink) on it and now it's activated funky mode?!? Bummer! That's pretty cool it's rebuildable though, I've always wanted to build a keyboard but I've yet to commit as I'm scurred of bad wireless and I'm totally unfamiliar with what's on the market so it's difficult for me to discern what's reasonable and of good quality


----------



## craxton

lmfodor said:


> 4000-14-16-16-16


16-16-16-16-16-32-48 would be way easier. also have you tried tCKE 12?
as well as tried cad_bus timings? i forget what ones it was for DR, but
seeing how im running what was said to work for dual rank dimms....

those/these errors in TM5 are telling you whats actually wrong (in most errors that is)
so, take note of what errors your get and go check the page. ive linked it
several times throughout the past few pages to the other fellow speaking to you now.

some voltages look fine, while others are high. SOC voltage for 4000mhz is usually a minimum 1.2v
100% sure on my 5600x its needed otherwise well latency/read/write jumps all over the place.

man, wished i had known how to use this site properly back when veii was posting
all the info about CCD/IOD voltage ranges as a good portion of what youve just asked has
been answered time and time again. (are you going for 24/7 stability?)

go check Thaiphoon burner, and check the part number, if its K4A8G085WB-BCPB
then it should be more than decent enough (B-DIE) overclock as thats what the majority
has running 3600-4000mhz as is.

EDIT seeing how you have 3800mhz c14 sticks tho, you really should 
not have much problems with all the information here, and having sticks binned CAS14 

im not sure whats actually holding you back. 
again, have you tried another bios revision? (if if you stated this earlier, i did not see it)
but some/most bios revisions will work on some boards, to where others will not.





mongoled said:


> Then the first time you asked a question it must have been a question they didnt like so they blanked you ??


well, i got a response.

Thanks for contacting MSI technical support.

Regarding your concern, do you mean the CPU VDDP Voltage option? We are really sorry, this option only appear when you use the CPU which has iGPU.

Thanks for your cooperation in advance!

Best Regards,

MSI Technical Support Team

seems as if its the same thing they told you, (i clear and plainly said CPU_VDDP and stated NOT CLDO_VDDP)
so somewhere along the lines someone's misinformed either at AMD, or MSI....


----------



## craxton

TimeDrapery said:


> Now you tap the same link and navigate to where I described inputting "aaa" and tell me if you see it there


Nope, dont see it and this is what im seeing


Spoiler: pic
















TimeDrapery said:


> I think I misunderstood





Spoiler



lol yea, for sure misunderstood what i meant. dropped a heavy object. 
the keys are pinned to the pcb and soldered at that, so its not to hard. rather simple if im honest
just a little steady hand and heat is all it takes (knowing which keys as well)





TimeDrapery said:


> Spoiler
> 
> 
> 
> I've always wanted to build a keyboard but I've yet to commit as I'm scurred of bad wireless and I'm totally unfamiliar with what's on the market so it's difficult for me to discern what's reasonable and of good quality





Spoiler: off topic



i didnt so much make this keyboard, at all in fact. simply just tore it down, and fifxed the bad keys. 
this keyboards been out for well, a few years time now. ive had some good luck with it and will
consider Logitech again in the future. Was my first (light up) keyboard red* not changeable or RGB
however, i did NOT have such luck with corsair and there M65 pro mouse. 
anyhow, should probably finish with off topic matters lol


----------



## lmfodor

craxton said:


> 16-16-16-16-16-32-48 would be way easier. also have you tried tCKE 12?
> as well as tried cad_bus timings? i forget what ones it was for DR, but
> seeing how im running what was said to work for dual rank dimms....
> 
> those/these errors in TM5 are telling you whats actually wrong (in most errors that is)
> so, take note of what errors your get and go check the page. ive linked it
> several times throughout the past few pages to the other fellow speaking to you now.
> 
> some voltages look fine, while others are high. SOC voltage for 4000mhz is usually a minimum 1.2v
> 100% sure on my 5600x its needed otherwise well latency/read/write jumps all over the place.
> 
> man, wished i had known how to use this site properly back when veii was posting
> all the info about CCD/IOD voltage ranges as a good portion of what youve just asked has
> been answered time and time again. (are you going for 24/7 stability?)
> 
> go check Thaiphoon burner, and check the part number, if its K4A8G085WB-BCPB
> then it should be more than decent enough (B-DIE) overclock as thats what the majority
> has running 3600-4000mhz as is.
> 
> EDIT seeing how you have 3800mhz c14 sticks tho, you really should
> not have much problems with all the information here, and having sticks binned CAS14
> 
> im not sure whats actually holding you back.
> again, have you tried another bios revision? (if if you stated this earlier, i did not see it)
> but some/most bios revisions will work on some boards, to where others will not.


Hi @craxton, thanks for you reply.
Well it seems I'm lucky at least with the B-DIE.


DRAM Components:*K4A8G085WB-BCTD*

I tried a lot to lower my primaries with 3800 and also to have 14 flat, but the amount of errors that I had in TM5 were very many, almost 100 per minute and it canceled, mostly they were 6, 12 and 2. I read about the errors, they seem to be voltage or voltage or resistance. I'm really was lost. So I decided to try 4000-14-16-16-16 (which gives me the same errors as 16-16-16. What puzzles me about these 3800CL14 DR memories is that they seem to run fine with 1.5V, at least in a few cases I know. What I did see are many 2x8GB SRs that achieve the result much easier, with 1T and much tighter subtimings. I just realized that each TM5 test gives its error, I did not know that, as now the errors slower I realized and there are no more errors 6 than they were where they always failed .It would seem that I am closer to stabilizing this configuration than 3800 14-14-14. Regarding the CAD BUS I left it at 24-24-24-24 because they are the values that come by default XMP Profile and that I saw in the review, with 53ohms of ProctODT (which could go down since it comes standard with 43) and RTTs like this, RttNom Disabled, WR in 2 .. 3 it costs a little to get POST, and Park at 5 to be more consistent with the voltage

Regarding vSOC, I've seen everything, I don't know if Single Rank or Dual Rank have a difference, but I see from 1.12V, 1.14V, 1.16V and 1.22V where I think Veii leads the podium. IOD and CCD some I see matching them, others trying to put the CCD at 0.94 or at least close to 1V and the IOD 0.5mV below vSOC. And the VDDP as a rule I think it is convenient in 0.9 to 0.85 .. but I see several configurations with VDDP above 1.1. So I'm a bit lost, I already read all the TM5 errors. What I lack is a test procedure, that is, look for a baseline and go playing one by one, otherwise it is like it is lost. There are several rules that I try to follow, for example I know that SC DDs at 1-4-4-1-6-6 go well for DR. TWRCD has to be +2 because it's DR, that's why it's at 10. SCLs at 4 also seem to be fine. Maybe the TWR can lower it a bit. At this point I prefer an advice from you or a calculator to guide me. I think DRAM Calculator is old enough to calculate such fine values. I saw a Veii calculator but it seems broken, or at least I am missing data, I wish I could download it. I hope you can help me or guide me. I think I have a lot of room to improve, the temperatures are good and I want to continue advancing little by little. This is the calculator that I found but some values are broken:Ryzen Google Calculator
I just downgraded mi BIOS for the latest version to the SMU 56.45 and the L3 cache it's more real and consistent. 
And yes, the configuration I am looking for is 7/24. And now for the first time I'm getting a lots of WHEA logs and one reboot, so I went back to my stabilized profile to continue tomorrow.

I would much appreciate any help or guidance!!









Thanks!


----------



## mongoled

craxton said:


> 16-16-16-16-16-32-48 would be way easier. also have you tried tCKE 12?
> as well as tried cad_bus timings? i forget what ones it was for DR, but
> seeing how im running what was said to work for dual rank dimms....
> 
> those/these errors in TM5 are telling you whats actually wrong (in most errors that is)
> so, take note of what errors your get and go check the page. ive linked it
> several times throughout the past few pages to the other fellow speaking to you now.
> 
> some voltages look fine, while others are high. SOC voltage for 4000mhz is usually a minimum 1.2v
> 100% sure on my 5600x its needed otherwise well latency/read/write jumps all over the place.
> 
> man, wished i had known how to use this site properly back when veii was posting
> all the info about CCD/IOD voltage ranges as a good portion of what youve just asked has
> been answered time and time again. (are you going for 24/7 stability?)
> 
> go check Thaiphoon burner, and check the part number, if its K4A8G085WB-BCPB
> then it should be more than decent enough (B-DIE) overclock as thats what the majority
> has running 3600-4000mhz as is.
> 
> EDIT seeing how you have 3800mhz c14 sticks tho, you really should
> not have much problems with all the information here, and having sticks binned CAS14
> 
> im not sure whats actually holding you back.
> again, have you tried another bios revision? (if if you stated this earlier, i did not see it)
> but some/most bios revisions will work on some boards, to where others will not.
> 
> 
> 
> 
> well, i got a response.
> 
> Thanks for contacting MSI technical support.
> 
> Regarding your concern, do you mean the CPU VDDP Voltage option? We are really sorry, this option only appear when you use the CPU which has iGPU.
> 
> Thanks for your cooperation in advance!
> 
> Best Regards,
> 
> MSI Technical Support Team
> 
> seems as if its the same thing they told you, (i clear and plainly said CPU_VDDP and stated NOT CLDO_VDDP)
> so somewhere along the lines someone's misinformed either at AMD, or MSI....


Latest response from MSI



> Thanks for your reply ！
> In fact, the CPU VDDP voltage in msi MB BOS is controlled hardware. Due to the hardware spec, the option will be just for the APU. Thus you will not get it when you install the 5000 series CPU.
> Thanks!


Someone is telling porkies!


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> lol not quite, if you click the link i posted which is here
> it should make it so your in VIEWER mode only and not allow edit/adding
> anything of your own. but, i noticed i was in edit mode, since i had the same thing with
> tRFC mini calc that was posted to which i (for an entire day) couldnt use the thing lol
> 
> yes, im not to familiar with gdoc/sheets at all. but im getting there. i simply wished i would have
> read what it said about being able to add multiple screen shots/how to do so.
> 
> Its no wonder i was never answered, probably wondering WT# did i mean, where....
> if it were a snake it wuda bit me right in the mfn nose.
> 
> 
> 
> Spoiler: (random input)
> 
> 
> 
> dropped something on my keyboard earlier G413 carbon and now im getting like 4 fff)
> time to tear down and resolder again... lasted 3 years so far lol....good thing i have other replacement keys...
> last time it was k, num pad /, *, -, + and 8 sometimes best 20 bucks ever spent


Ah, you're on the Zen 3 RAM OC sheet... That one's not locked either, I just did the same thing on the first open row there

I'm gonna go undo my edits now so as not to add to the housekeeping!


----------



## lmfodor

lmfodor said:


> Hi @craxton, thanks for you reply.
> Well it seems I'm lucky at least with the B-DIE.
> 
> 
> DRAM Components:*K4A8G085WB-BCTD*
> 
> I tried a lot to lower my primaries with 3800 and also to have 14 flat, but the amount of errors that I had in TM5 were very many, almost 100 per minute and it canceled, mostly they were 6, 12 and 2. I read about the errors, they seem to be voltage or voltage or resistance. I'm really was lost. So I decided to try 4000-14-16-16-16 (which gives me the same errors as 16-16-16. What puzzles me about these 3800CL14 DR memories is that they seem to run fine with 1.5V, at least in a few cases I know. What I did see are many 2x8GB SRs that achieve the result much easier, with 1T and much tighter subtimings. I just realized that each TM5 test gives its error, I did not know that, as now the errors slower I realized and there are no more errors 6 than they were where they always failed .It would seem that I am closer to stabilizing this configuration than 3800 14-14-14. Regarding the CAD BUS I left it at 24-24-24-24 because they are the values that come by default XMP Profile and that I saw in the review, with 53ohms of ProctODT (which could go down since it comes standard with 43) and RTTs like this, RttNom Disabled, WR in 2 .. 3 it costs a little to get POST, and Park at 5 to be more consistent with the voltage
> 
> Regarding vSOC, I've seen everything, I don't know if Single Rank or Dual Rank have a difference, but I see from 1.12V, 1.14V, 1.16V and 1.22V where I think Veii leads the podium. IOD and CCD some I see matching them, others trying to put the CCD at 0.94 or at least close to 1V and the IOD 0.5mV below vSOC. And the VDDP as a rule I think it is convenient in 0.9 to 0.85 .. but I see several configurations with VDDP above 1.1. So I'm a bit lost, I already read all the TM5 errors. What I lack is a test procedure, that is, look for a baseline and go playing one by one, otherwise it is like it is lost. There are several rules that I try to follow, for example I know that SC DDs at 1-4-4-1-6-6 go well for DR. TWRCD has to be +2 because it's DR, that's why it's at 10. SCLs at 4 also seem to be fine. Maybe the TWR can lower it a bit. At this point I prefer an advice from you or a calculator to guide me. I think DRAM Calculator is old enough to calculate such fine values. I saw a Veii calculator but it seems broken, or at least I am missing data, I wish I could download it. I hope you can help me or guide me. I think I have a lot of room to improve, the temperatures are good and I want to continue advancing little by little. This is the calculator that I found but some values are broken:Ryzen Google Calculator
> I just downgraded mi BIOS for the latest version to the SMU 56.45 and the L3 cache it's more real and consistent.
> And yes, the configuration I am looking for is 7/24. And now for the first time I'm getting a lots of WHEA logs and one reboot, so I went back to my stabilized profile to continue tomorrow.
> 
> I would much appreciate any help or guidance!!
> View attachment 2487335
> 
> 
> Thanks!


@craxton, @RonLazer Can I ask you for any positive feedback or advise to continue testing?, I would like to make a little procedure. I mean. Changing ProcOTC, RTTs and Cad Bus leaving the remaining values equals, or touch some values that you think may improve my settings. What I won’t is to touch many values together neither want to copy values from others, just think what would be affecting my settings and test in some order, step by step to see it TM5 lower the quantities of errors. Much appreciate for your great help as always
Best Martin


Sent from my iPhone using Tapatalk Pro


----------



## craxton

lmfodor said:


> but the amount of errors that I had in TM5 were very many


have you tried adding the BUS timings i mentioned??? and tried those from the zen 3
overclocking page that were either running 4x8 or 2x16gb sticks?

without those values my board will either not post AT ALL or
throw errors OUT THE WAZOO....

use the main page for ram timings config to change these values. they are called
(i think) data bus timings) they are not RZQ/ whatever tho, completely different
but are still related.

for tCL 14 1.5vdimm is needed and a few other things apply.
the information is quite a ways back, but user Veii has posted ALOT
(enough for a 200 page book) about it.

EDIT (before trying tCL 14 do try to get 16 flat stable first)
would be alot easier to see what it takes to stabilize c16 flat 
to know if your capable of c14 at 3800mhz as its not well known.


----------



## craxton

Dreamic said:


> B550 Gaming Edge? Shouldn't be any better than my B550 Tomahawk or getting any better BIOS treatment, I don't know if it could be cause I'm 4x8GB or what's different about my config that WHEA errors 1933+, 1900 doesn't post





Spoiler



dunno why this just popped up stating i had this from you,
but there the EXACT same board just look slightly different.

i have got 4x8 stable tho at 4000mhz no WHEA at all, with C/O running as well.

below is what my timings consist of. 1.2125V soc, IOD 1.075v, CCD .990, VDDP 910, Vdimm 1.48V
llc 3 on northbridge, 300mv overvoltage protction
800khz cpu switching freq, 600khz CPU NB/SOC switching freq
X4 pbo scaler, 200mhz auto oc





Spoiler


----------



## PJVol

craxton said:


> i have got 4x8 stable tho at 4000mhz no WHEA at all, with C/O running as well.


I've got 2x8 stable as well at 4066 with C/O and a lots of WHEA 19 (which I don't give a s**t about )


----------



## craxton

PJVol said:


> a lots of WHEA 19 (which I don't give a s**t about )


honestly if it worked and it wasnt actually interfering with anything,
i dont think id give a dang about WHEA errors either.

my 2x8 config looked like this

with the same kits i have now just 2 less sticks tho.SR
i tried 4066 but couldnt stabilize 4x8 then again i only tried for a few hours.

EDIT (i think this was before i fixed my tFAW tho.) but scores didnt change none the less.
just something that drove Veii mad about 3 months back lol


----------



## PJVol

craxton said:


> my 2x8 config looked like this


Yeah, this is exactly the agesa version we are (asrock users) missing, 56.43, which doesn't limit fclk and boost override value at the same time. Fot the 5600X owners it's golden combo ))


----------



## craxton

PJVol said:


> Yeah, this is exactly the agesa version we are (asrock users) missing, 56.43, which doesn't limit fclk and boost override value at the same time. Fot the 5600X owners it's golden combo ))


it would seem your doing something quite different than i...???? i know it made (even unstable) a
world of difference in speeds from 4000 to 4066 but still....THAT much difference ?
dram bench is old but i dont believe ive changed anything...















edit, i couldnt get the sophia scipt to run for some reason,
unsure if your using that, but i do have "most" tasks killed to where 
cpu usage is either 0 or 1% depending on if the mouse is moved.

i will state there is some kind of bug/issue with windows power plan disappearing
and jumping back and fourth (in the old win 7 version) it disappears from the new win 10 view point tho. 
when it does this tho, it jumps CPU to 100% while nothing shown as being used nor does it slow the pc down or heat up?


----------



## PJVol

Yeah, the latency improved more than usual 0.5ns for one step in fclk/mclk, almost 1ns (@4000 it was 50.6). That is the thing surprised me most. I didn't use any "debloating" scripts and safe mode benching, though my OS is as clean as "legally" possible ))

As for other results they are basically inline with fclk/mclk increase (you may see all of them in "proof" pics in dram oc spreadsheet in zen3 tab).


craxton said:


> it would seem your doing something quite different than i...????


Forgot to say, possibly I am. Running 4066 stable required setting vdd18 to its limit - 2.1 volts. (@4000 2.0 was enough)


----------



## DeletedMember558271

RonLazer said:


> Sorry to be clear this is for solving memory holes, not issues with FCLK not posting. The only suggestion I have on that front is to try booting at 1867MHz, setting 1.15V SOC and 1.95V PLL (might be called 1P8 if you have an MSI board) and rebooting (still at 1867MHz) then setting 1900MHz FCLK and rebooting. This is because some voltages seem to be modified later in the boot process than the FCLK clock is set, so I always modify voltages THEN set FCLK.
> 
> I can't promise it will work, every chip has a certain frequency which it will just fail to post at, on both my chips its 2100MHz, but I know some people can't do 1933 or even 1900 (in 1 case I know of).


I also tried the 0.85 cldo vddp, 1.15 soc, 1.95 pll/1p8, (along with a million other different suggested voltages/tweaks in the past) still no 1900 boot.


craxton said:


> Spoiler
> 
> 
> 
> dunno why this just popped up stating i had this from you,
> but there the EXACT same board just look slightly different.
> 
> i have got 4x8 stable tho at 4000mhz no WHEA at all, with C/O running as well.
> 
> below is what my timings consist of. 1.2125V soc, IOD 1.075v, CCD .990, VDDP 910, Vdimm 1.48V
> llc 3 on northbridge, 300mv overvoltage protction
> 800khz cpu switching freq, 600khz CPU NB/SOC switching freq
> X4 pbo scaler, 200mhz auto oc
> 
> 
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2487425
> View attachment 2487426


Copied all your settings so every number in ZenTimings was identical and copied the other settings you mentioned that are outside of ZenTimings except I even disabled/auto PBO to rule out that instability, hundreds of WHEA 19's instantly at idle.







Shame cause it's a nice 51.5ns
Back to 1867... forever I guess as AMD/MSI are never going to help improve anything


----------



## craxton

Dreamic said:


> I also tried the 0.85 cldo vddp, 1.15 soc, 1.95 pll/1p8, (along with a million other different suggested voltages/tweaks in the past) still no 1900 boot.
> 
> Copied all your settings so every number in ZenTimings was identical and copied the other settings you mentioned that are outside of ZenTimings except I even disabled/auto PBO to rule out that instability, hundreds of WHEA 19's instantly at idle.
> View attachment 2487450
> 
> Shame cause it's a nice 51.5ns
> Back to 1867... forever I guess as AMD/MSI are never going to help improve anything


you placed the CAD_BUS timings in as well? best i could get was 51.9
but i have pbo/co being set as well. so perhaps manual oc would be a little better.

EDIT sad you didnt get these timings to work out,
these are the errors i see, (only WHEA errors ive gotten was when getting CO stable)
other than that 99% of any warning log i see is from task killing services
that windows bitXhes about when they aint running.


----------



## craxton

To all of you with one WHEA error code (by one i mean the same error code more than one time) 
have you ran a script to remove windows BLOAT WARE,

I.E. ONE DRIVE, killing cortana, stuff like that????
setting here wondering why im WHEA free but those with more 
knowledge and know how than i still get these errors on better hardware.
(cortana is killed and disabled in my registry, as well as one drive is completely removed down to the service
being the only thing left while being set to disabled. theres quite a few other bloatware things windows comes with
(ZOOM, MEET, stuff like that, that ive ran batch files to remove and changed values for these
in registry to completely disable) the only thing i couldnt get rid of entirely was EDGE 
as it always comes back. 

this may not be relevant, but if someone has the know how and hasnt done so, GIVE IT A SHOT.....


----------



## lmfodor

Hi @craxton! Thank you a lot for your great help! I only got a 10 error in TM5, compared to the large quantity of errors I had before it' s an incredible breakthrough. Really thank you very much for all your help in off. What I had to do to make it happened was kind of weird. I couldn't make many adjustments with the voltage of 1.55, so I decided to take it to 1.6 to modify as much as possible. In fact, it cost a lot of memory training to get POST. The only thing I couldn't get off is the *ProctODT of 43,* I tried a lot but I couldn't do it, maybe bringing it to more voltage, I don't know. But it was the only thing, the rest of them managed to replicate your configuration with just that difference. But I still had a lot of mistakes, back 6 and 12 error in TM5 again.. and little tired I remembered something that Mongoled had told me, that in this test and adjust game, which in addition to the rules sets we follow, we have to take into consideration the electrical characteristics of PCBs and that from their experience not always the solution was to raise the voltage but quite the opposite, and gave me an example that at 4133/2067 using flat 16 I had errors with 1.52V but with 1.48V he had no errors. So I decide to set your voltage to 1.48 and magically all the errors disappeared! At lest a lot of them. So I went into analyzing the errors, I realized that the tRDWR should be 10 per rule, instead of 11 (tRCDWR and RD/2+2 for DR). So I corrected that. And now I only have to see because I have 1 error only 10 that from what I see in Veii's description of TM5 can be:









So, I tried to increase tWR to 14, the tTRP to 7, and then tRFCs of around 315-234-144. But I also had another few errors. So I'm thinking about to loosen or tight the last two tRDWR and tWRRD, for instance 4/6/16/4/12/12 (including tFAW and tWR) or even more tight 4/4/16/4/8/10 or the opposite, keeping as a fixed value tRDWR at 10, try 5/7/20/5/14 that would be fine for tRDWR cause one time Veii suggested me that. Besides I noticed that now I have a lot of WHEA Log Errors, so something else should be fixed. I keep my previous stable PBO Curve, I didn't change anything from my last settings (DF States and Global C-Stated Disabled, CPPC and Preferred Cores Enabled, SocUncore Enabled, Thypical Current Idle, and nothing else. never had Whea error even when I worked with my Curve Optimizer..









What do you think? What else should I try? It's a really great advanced! 

Beside I was wondering if a higher vSOC i'ts really needed, but better solve one thing at a time










Thanks for your help!


----------



## KedarWolf

lmfodor said:


> Hi @craxton! Thank you a lot for your great help! I only got a 10 error in TM5, compared to the large quantity of errors I had before it' s an incredible breakthrough. Really thank you very much for all your help in off. What I had to do to make it happened was kind of weird. I couldn't make many adjustments with the voltage of 1.55, so I decided to take it to 1.6 to modify as much as possible. In fact, it cost a lot of memory training to get POST. The only thing I couldn't get off is the *ProctODT of 43,* I tried a lot but I couldn't do it, maybe bringing it to more voltage, I don't know. But it was the only thing, the rest of them managed to replicate your configuration with just that difference. But I still had a lot of mistakes, back 6 and 12 error in TM5 again.. and little tired I remembered something that Mongoled had told me, that in this test and adjust game, which in addition to the rules sets we follow, we have to take into consideration the electrical characteristics of PCBs and that from their experience not always the solution was to raise the voltage but quite the opposite, and gave me an example that at 4133/2067 using flat 16 I had errors with 1.52V but with 1.48V he had no errors. So I decide to set your voltage to 1.48 and magically all the errors disappeared! At lest a lot of them. So I went into analyzing the errors, I realized that the tRDWR should be 10 per rule, instead of 11 (tRCDWR and RD/2+2 for DR). So I corrected that. And now I only have to see because I have 1 error only 10 that from what I see in Veii's description of TM5 can be:
> View attachment 2487500
> 
> 
> So, I tried to increase tWR to 14, the tTRP to 7, and then tRFCs of around 315-234-144. But I also had another few errors. So I'm thinking about to loosen or tight the last two tRDWR and tWRRD, for instance 4/6/16/4/12/12 (including tFAW and tWR) or even more tight 4/4/16/4/8/10 or the opposite, keeping as a fixed value tRDWR at 10, try 5/7/20/5/14 that would be fine for tRDWR cause one time Veii suggested me that. Besides I noticed that now I have a lot of WHEA Log Errors, so something else should be fixed. I keep my previous stable PBO Curve, I didn't change anything from my last settings (DF States and Global C-Stated Disabled, CPPC and Preferred Cores Enabled, SocUncore Enabled, Thypical Current Idle, and nothing else. never had Whea error even when I worked with my Curve Optimizer..
> View attachment 2487502
> 
> 
> What do you think? What else should I try? It's a really great advanced!
> 
> Beside I was wondering if a higher vSOC i'ts really needed, but better solve one thing at a time
> 
> View attachment 2487501
> 
> 
> Thanks for your help!


Now if it passes OCCT you're golden.


----------



## lmfodor

KedarWolf said:


> Now if it passes OCCT you're golden.


Do you think? I have a lot of WHEA! Something should be wrong.. I was happy with the single TM5 error but with the WHEAs I don’t know what could it be!


Sent from my iPhone using Tapatalk Pro


----------



## Antiarch

*Crucial Ballistix Sport LT 32GB (2x16GB) 3200 MHz Gray*


Long time reader of this thread, first time poster wanting to add to the stability thread and ask some questions. I don't see much with dual rank Micron Rev-E posted for Vermeer so I figured I'd share. This is tested with y-cruncher with all component stress tests enabled at 8 hours with no errors and TM5 1usmus_v3 20 cycles tested with no errors. I've gamed for hours playing DX12 games at these settings and no crashes, stutters, reboots except when I undervolt the graphics card too much. This is also with a manual setting of the current to the SOC where current to the SOC generally runs under 6 A and total power fluctuates between 5 - 6 Watts to the SOC between idle and testing loads as reported by the voltage regulators via HWiNFO64 (see settings below - following guidelines posted here by Veii - someone call me out if I messed settings up. I know the CsOdtDrvStr could be 40 Ohm but I'm not asking the board to figure out my timings for me).

VSOC was set as fixed and not under the quick OC menu in External Voltage Setting and SOC/Uncore set to disabled under the quick OC menu

AMD PBS > Adjust VddcrVddcrVddfull Mode > Auto
AMD PBS > Adjust VddcrVddcrSocfull Mode > Manual > VddcrVddfull Scale Current > 35 (I have no idea with the unit is for this or if it's just a multiplier but the BIOS will let me set it to 1000000, not that I attempted to boot it at that)

AMD Overclocking > PBO > Disabled
AMD Overclocking > LN2 Mode > Disabled

AMD CBS > CPU Common Options > SMEE > Disabled
AMD CBS > CPU Common Options > Global C-state > Enabled

AMD CBS > DF Common Options > Memory Clear > Disabled
AMD CBS > DF Common Options > Memory Addressing > Memory Interleaving Size > 1 KB (specific to the 8gb ICs in this kit)

AMD CBS > NBIO Common Options > SRIS > Auto
AMD CBS > NBIO Common Options > SMU Common Options > APBDIS > 0
AMD CBS > NBIO Common Options > SMU Common Options > DF Cstates > Disabled
AMD CBS > NBIO Common Options > SMU Common Options > CPPC > Enabled
AMD CBS > NBIO Common Options > SMU Common Options > CPPC Preferred Cores > Enabled

OC Tweaker > External Voltage Setting and LLC > VDDP > 0.880 V
OC Tweaker > External Voltage Setting and LLC > DRAM > 1.43
Loadlines are set to level 2 for the SOC and level 3 for the CPU

Everything else to defaults for this board.


I lowered the current to the SOC on this board because I tested this processor in my ASRock X570 Phantom Gaming X and it was placing that much power and amps into the SOC by default after I booted it up at with those settings and same RAM to see if the processor could go to 1900 or more FCLK. This less current was stable on that board so I figured I'd try it on the ITX board. Otherwise, the ITX runs at 3.5x that power with Amps in the 12 - 13 range and power at 14 - 16 Watts range with the above screenshot settings. I know the RAM is certainly capable of running at that speed with my old R5 3600 that used to be in this board and my R9 3950X.

The issue being is that when I attempt to boot this board at 1900 FCLK 1:1:1 with loose timings on the RAM, it'll boot to Windows, but will randomly reboot within 1 - 2 minutes no matter where I set the SOC voltages, loadlines, DRAM voltages, give the CPU portion an offset over/under current, change ClkDrvStrs, up the PLL, experiment with different ProcODTs, Rtts, etc be it the CPU is under load or just sitting at idle. If I go to 1933+ FCLK 1:1:1 I have to up the voltages as expected on the SOC and its associated voltages and then it at least won't randomly reboot but I'm getting WHEA error 19s with y-cruncher testing, contrary to Veii's findings with this board. I can lessen those errors depending on the various settings that affect the SOC but I can't make them go away. I've tried setting my RX 5700 XT to gen 3 speeds. Nada. I've changed the CLDO VDDP by 0.005 increments up from 0.8 and everything seems more stable (read less WHEA errors) at around 0.900 - 0.910 V. 0.8 - 0.840 V just hard crashes and the board gets itself back to "sane" voltages for a boot. My X570 board will run this processor with this RAM with the power supply I'm using to supply the above stable screenshoted settings at 1933 FCLK 1:1:1 with a SOC of 1.12, CLDO VDDP of 0.900, VDDG CCD of 1.040, and VDDG IOD of 1.080 with all those settings above except for messing with currents and leaving the RAM timings loose because I wasn't interested in tightening them - just seeing if the processor was capable of 1900+ FCLKs. I did test those voltages on the X570 board with y-cruncher for 6 hours and it was stable with no WHEA errors. I'm sure I could lower the SOC and other associated voltages lower with tweaking, but, again, that wasn't my interest. And I think that means I've eliminated the CPU and power supply as a cause of the errors.

I have no idea why this ASRock B550 Gaming-ITX/ax board is giving me WHEA error 19s at above 1867 FCLK and why 1900 is so unstable but anything higher is more stable than unstable. I've run out of things to change in the BIOS on this board that might do something to stabilize the situation. It runs contrary to everything I've seen Veii post about his B550 Phantom. After weeks of testing intermittently when I'm not working, I think the board is a dud. It certainly _seems_ with the stable settings at 1867, it wouldn't take much to get this board to boot at 1900+ FCLK. I did try the latest Beta BIOS for this board which is L2.0.2 with AGESA 1201 Patch A, but it's just as bad as the stable 2.00 AND it knocked out my 4 rear USB 3.0 ports.

Thoughts? Questions? Suggestions?

Thanks.


----------



## craxton

lmfodor said:


> Hi @craxton! Thank you a lot for your great help! I only got a 10 error in TM5, compared to the large quantity of errors I had before it' s an incredible breakthrough. Really thank you very much for all your help in off. What I had to do to make it happened was kind of weird. I couldn't make many adjustments with the voltage of 1.55, so I decided to take it to 1.6 to modify as much as possible. In fact, it cost a lot of memory training to get POST. The only thing I couldn't get off is the *ProctODT of 43,* I tried a lot but I couldn't do it, maybe bringing it to more voltage, I don't know. But it was the only thing, the rest of them managed to replicate your configuration with just that difference. But I still had a lot of mistakes, back 6 and 12 error in TM5 again.. and little tired I remembered something that Mongoled had told me, that in this test and adjust game, which in addition to the rules sets we follow, we have to take into consideration the electrical characteristics of PCBs and that from their experience not always the solution was to raise the voltage but quite the opposite, and gave me an example that at 4133/2067 using flat 16 I had errors with 1.52V but with 1.48V he had no errors. So I decide to set your voltage to 1.48 and magically all the errors disappeared! At lest a lot of them. So I went into analyzing the errors, I realized that the tRDWR should be 10 per rule, instead of 11 (tRCDWR and RD/2+2 for DR). So I corrected that. And now I only have to see because I have 1 error only 10 that from what I see in Veii's description of TM5 can be:
> View attachment 2487500
> 
> 
> So, I tried to increase tWR to 14, the tTRP to 7, and then tRFCs of around 315-234-144. But I also had another few errors. So I'm thinking about to loosen or tight the last two tRDWR and tWRRD, for instance 4/6/16/4/12/12 (including tFAW and tWR) or even more tight 4/4/16/4/8/10 or the opposite, keeping as a fixed value tRDWR at 10, try 5/7/20/5/14 that would be fine for tRDWR cause one time Veii suggested me that. Besides I noticed that now I have a lot of WHEA Log Errors, so something else should be fixed. I keep my previous stable PBO Curve, I didn't change anything from my last settings (DF States and Global C-Stated Disabled, CPPC and Preferred Cores Enabled, SocUncore Enabled, Thypical Current Idle, and nothing else. never had Whea error even when I worked with my Curve Optimizer..
> View attachment 2487502
> 
> 
> What do you think? What else should I try? It's a really great advanced!
> 
> Beside I was wondering if a higher vSOC i'ts really needed, but better solve one thing at a time
> 
> View attachment 2487501
> 
> 
> Thanks for your help!


atm, in PM i think we will try those options out before moving forward.
but this is where you need to be.

id almost ignore that error 19 for now if i were you. and focus soly on passing
TM5, then HCI, as well as OCCT and lastly not getting hopes up until y-cruncher ( 1, 7, 0) passes 4 runs at least.

one can try whats here as well and double check


----------



## TimeDrapery

I'm currently working on a 1T CR/GDM disabled timing set at 3800MT/s...


Spoiler






























I've heard that once things start getting tighter later on in this process attaining stability can become a bit of a pain in the ass so if anyone's got any feedback on my _baseline_ timing set (depicted in the screenshot above) I'd love to hear it!


----------



## PJVol

Antiarch said:


> Thoughts? Questions? Suggestions?


1. I wouldn't mess with that pbs->Adjust Vddcr and return it to defaults (till someone clarify what's the purpose of it)
2. Keep in mind that Veii's CPU is kinda unique, since it's derived from 2CCD bins and may behave much differently with the same config, so I wouldn't rely too much on his settings either
3. I dont see the reason why you should keep SOC power so low, I think theres nothing wrong with ~12-15W SOC power at high fclk rates.
4. What else worries you when running 1933+ on this board, besides WHEA 19 ?


----------



## Antiarch

PJVol said:


> 1. I wouldn't mess with that pbs->Adjust Vddcr and return it to defaults (till someone clarify what's the purpose of it)
> 2. Keep in mind that Veii's CPU is kinda unique, since it's derived from 2CCD bins and may behave much differently with the same config, so I wouldn't rely too much on his settings either
> 3. I dont see the reason why you should keep SOC power so low, I think theres nothing wrong with ~12-15W SOC power at high fclk rates.
> 4. What else worries you when running 1933+ on this board, besides WHEA 19 ?


1. The only thing I can note about this is that lowering the current to the SOC did lower how quickly I would see WHEAs in y-cruncher runs. Just now I tried more VSOC and adjusted CCD and IOD upward and I didn't get a WHEA until I hit N32 test in y-cruncher at 1933. But I could reboot and redo the same thing all over again and I'll start seeing errors at the SFT test. Adjusting Vddcrvdd didn't do as much and too high or too low would cause instability in terms of reboots within a minute or 2. Boosting didn't change much either but that's not suprising since we're talking saving ~10 W.

2. I will reset to defaults in terms of changes in PBS and CBS and recheck but the rest of the values I got were through simply running the gambit of my RAM, the CPU, and the board.

3. A little less heat for the heatsink, I suppose  It's just a note that it can be stable with less power.

4. It's just odd. I'm trained as a scientist and work in medicine, it's not logically following. I like things to make sense. It doesn't seem like it would take much adjustment to get to 1900+, but it's unstable. I do realize that this board and my other board are different and there could be a lot of different things at play that I don't know about, but it's an ITX board, it should have less of an issue than a full size ATX with 4 DIMM slots at OC'ing. No matter how much I tweak or adjust, eventually an uncorrectable error will get me and force a reboot. It seems the more I decrease WHEA 19s seen during y-cruncher testing, the longer this will take to happen but it will happen.


----------



## mongoled

adversary said:


> @mongoled
> 
> I did take your advices, especially one regarding TRDRDSCL and TWRWRSCL setting from 2 to 4 (should also test 5) for 32GB dual rank. you were right, direct improvement on speeds. I'm simply new to AMD and first time owning B-Die RAM so all I know is what I get here
> 
> apologies for not answering earlier (about 2 weeks passed), I was pretty much occupied by other things last period, but I did grab some time to do again overclock on RAM and test it
> 
> however, I pushed one configuration (this one, tested with number of tests, I will explain more detailed later in post, and get it totally stable - up to one temperature point) again. more on this later
> 
> 
> @Veii
> 
> same big thanks for you
> 
> for someone who is learning it may be hard to remember all ot once, also it is not easy to scroll all of forum thread when you need info - so I can to idea to copy or screenshoot some of your posts. up to now I have small gallery and it is useful trust me
> 
> I may still making errors in RAM overclock, may still be unaware of some things (leading to wrong combinations of some timings), but always feel free to correct me, if you wish. it helps much
> 
> 
> ---------------------------
> 
> 
> 
> View attachment 2486991
> 
> 
> 
> 
> 
> well there we have 3800 14-14-12 1.6V
> this is best I get so far with latency (if we do not mind crazy attempts which are not stable, this one is tested stable for days - more on that later). this is not in safe mode
> 
> Windows10 20H2 - now, for what I read at forum recently, newer Win10 versions are more error prone with RAM overclocking
> 
> any attempt to make it 3866/1933 - errors one after another, no matter how much I relax timings or set another specific setting
> 
> AGESA is now 1.2.0.1 Patch A (not longer in Beta) - but I also read here that 1.2.0.1 is bugged for some things
> 
> RAM is placed under EKWB custom watercooling - and this is very important part as I will explain - not only temps get lowered (RAM was already cooled by direct strong fan), but max possible temperature will always stay stable according to water coolant temperture, and stress it have - you can know exact maximum value it may have, it can't go 0.1C above it - proven very imporatant for Samsung B-Die
> 
> now is 52.3ns ok for 3800/1900? at least there was no variance in repeating tests (just sometimes 0.1ns, if any)
> 
> tRFC is indeed very aggressive - I did try to apply Veii post about it relation with tRC (if I did understand properly how stepping there should work)
> 
> I did set VDDG IOD and CCD, again, according to what Veii was saying about "75mV steppings" relative to SOC voltage, taking IOD and CCD average value. SOC voltage, taking vdroop into accout. now did I mistaken something while doing this, I do not know, but it worked properly
> 
> I did test also combinations with more IOD, CCD, SOC, it did not bring any benefit, did not allow me more overclock headroom nor it lowered latency.
> well, less SOC voltage = lower CPU overall temps = better cores boost possible
> 
> setting higher (I mean higher number, higher divider) RttPark is not possible unless RttWr is set to RZQ/2
> so I did stick for 6/3/3
> is 1.6V OK in this case? maybe. not sure is PCB B1 or B2, but it is not B0. with RttPark 3, tCKE 9, with good cooling, maybe it should be fine.
> 
> I did not know at moment of doing this overclock, that CAD BUS timings are possible only (if I understand right?) if XX-20-20-20 are used. So I did not try timings 3-3-15 as I intended as it could not work with 60-20-30-20. I may try this next time
> 
> last thing, I can't regulate CPU VDDP, nor I can see it. can't find it in BIOS. I did try to install Asus TurboV EVO, but it says it can't work on this board. however, looking at specs on internet for this board, it say it support TurboV EVO.
> 
> 
> 
> so what made biggest change is fact I started finally to use proper programs to do stress test, prior to this I did not perform such tests and most probably was having errors all time.
> 
> because, after testing and setting this one to be error free, there was not anymore stutters in games or apps, not crackling sound, or weird game or app crash.
> 
> for stress tests, did not use all possible, but used : TM5, SuperPi 1.5, Prime95 LargeFFT, Y-Cruncher, Aida64
> 
> TM5 - did run 1usmus_v3 endless times - not single error
> SuperPi - did all tests, but mostly repeated 16MB and 32MB - no errors
> Prime95 - LargeFFT. seems to heat up RAM most of all. did burn it for few hours. repeated in few different days. 0 errors or warnings upon test stop.
> Aida64 - simply left it for few hours on Stress system RAM - nothing happened
> Y-Cruncher - did set time to 240 seconds (120 default), and additionally enabled FFT (fast fourier transform). so what was tested is : BKT, BBP, SFT, FFT, N64, HNT, VST. again, run on different days, let test self repeat number of times -0 errors
> 
> for some of mentined tests, I had HWInfo opened, there was not WHEA errors registered
> 
> 
> I concluded it as stable and run fine for days (and it is) - up to one evening - all issues suddenly returned - stutters, sound crackling, game freeze (even in menu). prior to that, tested with uncapped fps 500+ without problem.
> it did not take me long to find what is issue - coolant temperature gone high (32C) simply because room ambient temperature get to about same (there we have little specific situation with insulated room, no windows, only way to let air is by opening doors). so depending what you do, even not in summer time, it is possible in this room to get ambient at 32C, assuming you do not open doors for prolonged time - and that exactly happened
> 
> for some reason, game I did run at that moment is hard on RAM, and if Prime95 LargeFFT heat up RAM at +6C difference relative to coolant tempertaure, this game will do it at about 5.5C (1.6V RAM voltage)
> 
> tested TM5 in that conditions, and it immidiately started to throw number of different errors
> get room temperature at lets say 25C, repeat all tests, there will be no single error
> and now we can see how Samsung B-Die is temperature sensitive in case of aggressive timings
> saying that "up to 40C (or 50C) there will be not impact on RAM" is not true in this case at all - there we have totally different scenarios at RAM with around maximum 32C or above 37C, one is stable and one is totally unstable
> 
> because of various reasons (there will be chiller upgrade to watercooling + some other things, plus there is already AGESA 1.2.0.2 but in Beta for my motherboard, and 1.2.0.1 is mentioned as bugged, I will for sure do BIOS update in some future), I decided not to bother much with again finding stable overclock at higher temperatures, I simply pulled back to 3733/1866 and called it a day - for now.
> I performed tests further to see what will happen with 3733/1866 on higher temperatures. at 37 or 38C it is now going to be stable, all way up to 45-46C (to get that high temperature was possible only by removing few fans from radiatior and heating it quickly with hairdryer  ) . and yes 3733/1866 can work with slighly less voltage than 1.6V
> 
> as only CPU and RAM is watercooled, 5600X no matter settings and stress, is not able to have impact on coolant temperature, at this moment this watercooling is overkill for this CPU - it may bring change to 1C and no more. but as this is my first AMD build ever, I decided for 5600X and this cheaper board, first to learn it (and it is anyway big performance upgrade compared to my old 4 core Intel). possible upgrade, in time it comes fully as matured product, would probably be Zen3+ (I hope for it) with 12 cores, but it is not still decided of course. have to keep in mind that for example 12 cores CPU would be able to have more impact on cooling temperatures than 6 core 5600X
> 
> however, I planned already for some time, Hailea chiller upgrade, as not only for RAM, also same for CPU in case of Zen3, temperatures are going to have big influence from my expirience with it so far. I plan to place order for chiller next week, but it will take time until I get it into my crap country. when I get it running, I will keep you updated
> 
> in preparations for chiller use, I already get good temperature and humidity meter for room (to know dew point), additional 5L of coolant, and 15 W/mK thermal pads (EKWB is, I think, 2.5 W/mK)
> 
> apologies for long post, but I find it as best way to explain all details. hope my expirience with temperatures will be usuful for others.
> 
> I will probably keep 3733/1866, it is fine for my need at moment (can run 3800/1900 without problem but would need to be aware of ambient temperature all time and summer is coming), however I will attempt to overclock again when we get BIOS update, chiller, and summer is coming so best to do tuning in that conditions, so I belive best thing is to wait for some time and later attempt again RAM overclock experiments.
> in meantime I will collecting all info here
> 
> if I did commit any big error in timing of course let me know


I am going to say well done, irrespective that you are using watercooling on the memory modules

 

Going by my experience in running 4 x 8GB dimms I would say that watercooling the dimms is providing more benefits to the cooling of the PCB substrate rather than than the actual ram modules.

Ive noted that as I start to increase voltages over 1.56v while using 4 dimms that the errors I see when pushing tRCDRD to 14 are not related to the ram modules but the PCBs.

Using a fan over the modules is not enough to keep the PCBs temps down, thus lowering electrical noise.

I am going to give 1.6v another go while playing with Rtt values to see if I can take the step to flat 14s!

Nice setup btw, often considered water cooling the dimms but always though it was overkill, although it all looks very nice when done well


----------



## Nighthog

craxton said:


> considering once a bios flash is done, (same bios in mind)
> what was stable wont post. but one can post defaults then, load previous settings
> 
> (4000mhz or whatever they had) and posting happens, so ill be sure to keep this in mind as well.
> since ive noticed soc voltage does the same (not all the time) but sometimes when i reflash a bios back
> to stock.
> 
> i honestly believe the AMD overclocking section under "advanced" inside MSI bios is an issue that really
> should NOT be there to begin with, since NO MATTER whats set there in AMD section of the bios
> the main page will always take priority. (on both MSI boards ive ran 5000 chips on have anyhow)
> persay, setting 1.2 soc on main, and 1100 in AMDs section, always does the main page set 1.2.
> 
> so, i dont use AMDs section to overclock. unsure if anyone else uses it or not, but honestly does anyone know the point of
> why its included? even PBO values dont take if something else has been set inside the main overclocking page.


AMD_OVERCLOCKING is the best point of the bios to use!

I'm dismayed my 4650G doesn't have this fully unlocked on my X570 and my B550MH doesn't have this menu with my 3800X!

Means I only get "locked" PBO. Can't increases stock limits! It's a joke!

If i put my 3800X in my X570 it's pure godsend that you have access to the full AMD_OVERCLOCKING category. 
You want this section available.

It's the only section that allows unrestricted PBO usage and takes priority above AMD_CBS settings which can be set randomly by the motherboard BIOS however it wants them irregardless of your wishes. It allows you to override BIOS AUTO behaviour. And set custom AUTO/default voltages for BIOS post.(the voltage it boots with not adjusted after boot)


----------



## craxton

Nighthog said:


> AMD_OVERCLOCKING is the best point of the bios to use!
> 
> I'm dismayed my 4650G doesn't have this fully unlocked on my X570 and my B550MH doesn't have this menu with my 3800X!
> 
> Means I only get "locked" PBO. Can't increases stock limits! It's a joke!
> 
> If i put my 3800X in my X570 it's pure godsend that you have access to the full AMD_OVERCLOCKING category.
> You want this section available.
> 
> It's the only section that allows unrestricted PBO usage and takes priority above AMD_CBS settings which can be set randomly by the motherboard BIOS however it wants them irregardless of your wishes. It allows you to override BIOS AUTO behaviour. And set custom AUTO/default voltages for BIOS post.(the voltage it boots with not adjusted after boot)


ok, i get your point. But why does the AMD page not take priority?

why does the amd page also look WAY different when in the ram timings page to where 
its not just numbers but letters as well? 

So your saying to bypass PBO limits i need to use the AMD section and not the main page?


----------



## thismock

Antiarch said:


> The issue being is that when I attempt to boot this board at 1900 FCLK 1:1:1 with loose timings on the RAM, it'll boot to Windows, but will randomly reboot within 1 - 2 minutes no matter where I set the SOC voltages, loadlines, DRAM voltages, give the CPU portion an offset over/under current, change ClkDrvStrs, up the PLL, experiment with different ProcODTs, Rtts, etc be it the CPU is under load or just sitting at idle. If I go to 1933+ FCLK 1:1:1 I have to up the voltages as expected on the SOC and its associated voltages and then it at least won't randomly reboot but I'm getting WHEA error 19s with y-cruncher testing, contrary to Veii's findings with this board. I can lessen those errors depending on the various settings that affect the SOC but I can't make them go away. I've tried setting my RX 5700 XT to gen 3 speeds. Nada. I've changed the CLDO VDDP by 0.005 increments up from 0.8 and everything seems more stable (read less WHEA errors) at around 0.900 - 0.910 V. 0.8 - 0.840 V just hard crashes and the board gets itself back to "sane" voltages for a boot. My X570 board will run this processor with this RAM with the power supply I'm using to supply the above stable screenshoted settings at 1933 FCLK 1:1:1 with a SOC of 1.12, CLDO VDDP of 0.900, VDDG CCD of 1.040, and VDDG IOD of 1.080 with all those settings above except for messing with currents and leaving the RAM timings loose because I wasn't interested in tightening them - just seeing if the processor was capable of 1900+ FCLKs. I did test those voltages on the X570 board with y-cruncher for 6 hours and it was stable with no WHEA errors. I'm sure I could lower the SOC and other associated voltages lower with tweaking, but, again, that wasn't my interest. And I think that means I've eliminated the CPU and power supply as a cause of the errors.
> 
> I have no idea why this ASRock B550 Gaming-ITX/ax board is giving me WHEA error 19s at above 1867 FCLK and why 1900 is so unstable but anything higher is more stable than unstable. I've run out of things to change in the BIOS on this board that might do something to stabilize the situation. It runs contrary to everything I've seen Veii post about his B550 Phantom. After weeks of testing intermittently when I'm not working, I think the board is a dud. It certainly _seems_ with the stable settings at 1867, it wouldn't take much to get this board to boot at 1900+ FCLK. I did try the latest Beta BIOS for this board which is L2.0.2 with AGESA 1201 Patch A, but it's just as bad as the stable 2.00 AND it knocked out my 4 rear USB 3.0 ports.


In my limited experience, high FCLK seems to be very dependent on the silicon lottery of your motherboard (in addition to getting lucky with your RAM and CPU).

I have a set of single rank Rev. E (3600c16) that I can run stable, WHEA-free at 4267c16, 2133 FCLK on an Asrock B450 Fatal1ty Gaming-ITX/AC motherboard.

Using the exact same components and just switching out the motherboard to an ASUS Crosshair VIII Impact (X570), the highest I could get stable was 3867c16, 1933 FCLK. No matter how much voltage tweaking and BIOS manipulation I tried (and the ASUS x570 board has wayyy more options than the Asrock B450), I was unable to get the system to post at 3933:1967 or higher. Which is bananas because the ASUS is a much more expensive, and supposedly higher quality, motherboard.

I suspect I was unlucky with my ASUS board, since there are others running the Crosshair VIII Impact at 2000+ FCLK stable, WHEA-free — and I know my CPU and memory can perform at that level. You may also have an unlucky board, since Veii (and I think some others?) are running 2000+ FCLK on the Asrock B550 Phantom Gaming ITX.


----------



## craxton

ok, where do i go from here ??
(i know there are "guides" but none that know
what it is there actually doing?

yes i know this is the wrong page to ask this as well....but still
having a "golden chip" and not knowing what to do with it,
or what that actually means????


----------



## PJVol

craxton said:


> ok, where do i go from here ??
> (i know there are "guides" but none that know
> what it is there actually doing?
> 
> yes i know this is the wrong page to ask this as well....but still
> having a "golden chip" and not knowing what to do with it,
> or what that actually means????


Lets figure it out together ))


----------



## craxton

PJVol said:


> Lets figure it out together ))


Wished I hadn been at work all day
Id be trying to figure it out now.



Spoiler



Now I'm omw to Toledo Ohio to "watch" 
Mortal combat which is 5 hours from my home.
Bought HBO max to watch it yet we'll, my ol lady...idk



Will be Sunday before I can touch my PC again. 😭😶


----------



## hsn

after updating agesa, soc must use 1.15v, below it is not stable.


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> ok, i get your point. But why does the AMD page not take priority?



I think he's saying that the "AMD Overclocking" menu (not the "AMD CBS [Common BIOS Settings]") takes priority regarding what settings are run

"AMD CBS" takes input on most settings in hexadecimal values, hence why some of the fields allow letters to be entered

From what I've seen the mobo vendor's OC menu simply sets the "AMD CBS" values unless you're adjusting something like a VCORE override when it would, obviously, insert itself to override VID requests... seems to me like with RAM settings it's just translating your regular everyday into hexadecimal for you

I've noticed it does not adjust "AMD Overclocking" settings, however, "AMD Overclocking" settings do adjust "AMD CBS" settings... Ryzen Master adjusts the mobo vendor's menu, "AMD CBS", and "AMD Overclocking" settings when you've got "Persistent PCV Values" enabled

I end up leaving more confused than before I entered most of the time 😂😂😂😂😂


----------



## Veii

TimeDrapery said:


> I think he's saying that the "AMD Overclocking" menu (not the "AMD CBS [Common BIOS Settings]") takes priority regarding what settings are run


AMD's main menu settings are translation links directed to AMD CBS & PBS
AMD CBS runs of HEX and is a low firmware level
Some brands do not translate everything into user decimal values to avoid bugs. (procODT, RTTs)

AMD OVERCLOCKING is a newer implemented "direct call" method.
It sends out "SMU calls" (easy formulated). But it does send "ovverrides"

Because AMD CBS & PBS are low firmware level, an extended override will "override" them.
A boot failure on AMD OVERCLOCKING will continue to be loaded until CMOS reset, but AMD OVERCLOCKING settings will not stick into Bios profiles.

AMD CBS is again "low-level firmware". Technically and stupidly both are "direct calls", but in comparison ~ they stick.
CBS settings have the highest priority unless they are overwritten by the similar/same command by "another method".
Main menu settings, even when they are direct links from CBS - can often bug out and not change CBS settings. CBS again has the highest priority unless priority on specific point get's overwritten before/on post.

A fully unlocked CBS, is all people need.
Consumers & sadly enthusiasts see at best 12-13% of the whole CBS & usable options.
AMD "OVERCLOCKING" is a 1 step backwards, 2 steps forwards thing.
CBS gets locked down further and further & the consumer is given a tiny crumble of the cookie as an "allowed to use" menu - to keep a bit of access & make him adjust to the bakers recipe.
The real meal you have to cook yourself "free"

Ryzen Master does neither stay in CBS nor in AMD OVERCLOCKING.
Like AMD OVERCLOCKING, it does push NVRAM "request-tasks". Soo they stay permanent till CMOS reset
But are also wiped upon CMOS reset & will need a CMOS reset (mostly) to restore the board to Optimal Defaults


----------



## ManniX-ITA

RonLazer said:


> CPU VDDP is likely powering the PHY receiver for "PCIe PHY" and "USB PHY" on your diagram.


My understanding is CLDO_VDDP, or just VDDP, is the DDR4 PHY on the cIOD SouthBound Interface; the one facing the physical DIMM sockets.
There is another set of DDR4 PHY in the cIOD but on the NorthBound Interface; they encapsulate DDR4 data over the IF and communicate with a DDR4 PHY which is on each CCD (max 2 on Ryzen, more on TR and EPYC).
Those DDR4 PHY VDDP can be adjusted by CPU_VDDP.

Now something for those interested in more stability for their OC using water-cooling (or not).
I'm planning to use this block from Alphacool that I already have used for testing TECs and will use for the RAM in the next build:









Alphacool D-RAM Cooler X4 Universal - Acetal Black Nickel


Mit den neuen Alphacool D-RAM Kühlern können nun alle beliebigen Speicherbausteine gekühlt werden. Dieser Kühlblock wird einfach auf die optional erhältlichen Kühlmodule oder auf vorhandene Heatspreader mit einem Lochabstand von 110mm...




www.alphacool.com





I've replaced my G.Skill TridentZ RGB factory heatsinks with the corresponding set of Alphacool:









Alphacool D-RAM Modul (für Alphacool D-RAM Cooler) - Black 2 Stück


Mit den Alphacool D-RAM Modulen lassen sich nun alle Speichersteine einfach und praktisch mit Wasserkühlern bestücken! Der unterschätzten Hitzequelle „Arbeitsspeicher“ wurde mit dem System der Alphacool D-RAM Kühler der Kampf angesagt....




www.alphacool.com





The block is really good, the modules not so exciting but they are probably more than enough for the job.
They are a bit short, barely covers the RAM ICs at the bottom and very light.
The G.Skill heatsinks are definitely bigger and heavier.

Obviously this was a great occasion to compare the factory HS against something else.
It's well known the "thermal pad" from G.Skill is very sticky and thin which raises a lot of questions about the thermal performances.

The answer is yes, there's much more glue than thermal material and the impact on temperature is quite sensible.
The main goal for G.Skill is to glue the HS to the DIMM, not to provide a good thermal conduct to the HS.

Unfortunately their HS can't be used without something that can glue it to the DIMM.
If you want to improve the temperature, without WC, you need to use the above modules from Alphacool or hopefully something better.
You need to use a good thermal pad to improve thermally, so a locking mechanism is mandatory.

Removing the HS was quite easy; better to heat the DIMMs with some testing before shutting down and starting the job.
But the glue was quite painful; took almost an hour to clean properly the 2 DR DIMMs.
There's really a lot of glue and it's terribly sticky.

Initially I was planning to use the Minus Pad 8 from Thermal Grizzly.
But @Pedros told me about the Gelid GP Extreme pads... 12 W/Mk.
Much better than the 8 W/Mk from the Minus Pad 8.
Couldn't find them on Amazon so I bought the GP Ultimate pads which are rated 15 W/Mk.

Considering these specs are more similar to thermal paste performance, the good ones, you'll wonder now: how?
Well to be honest it's not a "classic" thermal pad; it's more solid thermal paste.
Meaning it doesn't stick at all and it's extremely fragile. Shreds into tiny pieces with too much pressure at the wrong angle.
It was quite painful to cut and place and the 0.5mm package must have been mishandled and one sheet was partially messed up.
It's not easy but it can be done; I got away with 2 sheets 90x50mm.






Gelid Solutions GP-Ultimate - Thermal Pad 90x50x0.5mm .: Amazon.de: Computer & Zubehör


Gelid Solutions GP-Ultimate - Thermal Pad 90x50x0.5mm (2pcs). Ausgezeichnete Wärmeleitung, Idealer Lückenfüller. Einfache Installation Wärmeleitfähigkeit 15W - Kostenloser Versand ab 29€. Jetzt bei Amazon.de bestellen!



www.amazon.de





The result is that now in idle the DIMMs temperature improved about 1c.

The delta between the 2 DIMMs was about 0.8-1c, now it's 1-1.5c.

Stress under TM5 over 1h:30m before was 56.4c now it's 53.1c.

Doesn't look like much but, considering the HS itself is definitely much less capable, over 3c under stress it's a lot.
Means reaching stability when it's just out of reach or another notch down in timings.

Of course running them with the WB under the loop is going to be a whole different story 
But if you don't have this option it's still a way to bring down the temp; rather expensive of course.
I'll also mention that the Alphacool modules will hide the RGB LEDs, if you care about them.

If you wonder how I don't get errors in TM5 at over 56c it's because it's a good kit and I have an MSI B550 Unify-X.
Same kit on the GB X570 Aorus Master Rel 1.0 starts erroring at 51c.


----------



## TimeDrapery

Veii said:


> Spoiler
> 
> 
> 
> AMD's main menu settings are translation links directed to AMD CBS & PBS
> AMD CBS runs of HEX and is a low firmware level
> Some brands do not translate everything into user decimal values to avoid bugs. (procODT, RTTs)
> 
> AMD OVERCLOCKING is a newer implemented "direct call" method.
> It sends out "SMU calls" (easy formulated). But it does send "ovverrides"
> 
> Because AMD CBS & PBS are low firmware level, an extended override will "override" them.
> A boot failure on AMD OVERCLOCKING will continue to be loaded until CMOS reset, but AMD OVERCLOCKING settings will not stick into Bios profiles.
> 
> AMD CBS is again "low-level firmware". Technically and stupidly both are "direct calls", but in comparison ~ they stick.
> CBS settings have the highest priority unless they are overwritten by the similar/same command by "another method".
> Main menu settings, even when they are direct links from CBS - can often bug out and not change CBS settings. CBS again has the highest priority unless priority on specific point get's overwritten before/on post.
> 
> A fully unlocked CBS, is all people need.
> Consumers & sadly enthusiasts see at best 12-13% of the whole CBS & usable options.
> AMD "OVERCLOCKING" is a 1 step backwards, 2 steps forwards thing.
> CBS gets locked down further and further & the consumer is given a tiny crumble of the cookie as an "allowed to use" menu - to keep a bit of access & make him adjust to the bakers recipe.
> The real meal you have to cook yourself "free"
> 
> Ryzen Master does neither stay in CBS nor in AMD OVERCLOCKING.
> Like AMD OVERCLOCKING, it does push NVRAM "request-tasks". Soo they stay permanent till CMOS reset
> But are also wiped upon CMOS reset & will need a CMOS reset (mostly) to restore the board to Optimal Defaults



@Veii 

Thanks so much for all the wonderfully clarifying information!

Where can I read more on this topic? BKDGs?


----------



## TimeDrapery

ManniX-ITA said:


> Spoiler
> 
> 
> 
> My understanding is CLDO_VDDP, or just VDDP, is the DDR4 PHY on the cIOD SouthBound Interface; the one facing the physical DIMM sockets.
> There is another set of DDR4 PHY in the cIOD but on the NorthBound Interface; they encapsulate DDR4 data over the IF and communicate with a DDR4 PHY which is on each CCD (max 2 on Ryzen, more on TR and EPYC).
> Those DDR4 PHY VDDP can be adjusted by CPU_VDDP.
> 
> Now something for those interested in more stability for their OC using water-cooling (or not).
> I'm planning to use this block from Alphacool that I already have used for testing TECs and will use for the RAM in the next build:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Alphacool D-RAM Cooler X4 Universal - Acetal Black Nickel
> 
> 
> Mit den neuen Alphacool D-RAM Kühlern können nun alle beliebigen Speicherbausteine gekühlt werden. Dieser Kühlblock wird einfach auf die optional erhältlichen Kühlmodule oder auf vorhandene Heatspreader mit einem Lochabstand von 110mm...
> 
> 
> 
> 
> www.alphacool.com
> 
> 
> 
> 
> 
> I've replaced my G.Skill TridentZ RGB factory heatsinks with the corresponding set of Alphacool:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Alphacool D-RAM Modul (für Alphacool D-RAM Cooler) - Black 2 Stück
> 
> 
> Mit den Alphacool D-RAM Modulen lassen sich nun alle Speichersteine einfach und praktisch mit Wasserkühlern bestücken! Der unterschätzten Hitzequelle „Arbeitsspeicher“ wurde mit dem System der Alphacool D-RAM Kühler der Kampf angesagt....
> 
> 
> 
> 
> www.alphacool.com
> 
> 
> 
> 
> 
> The block is really good, the modules not so exciting but they are probably more than enough for the job.
> They are a bit short, barely covers the RAM ICs at the bottom and very light.
> The G.Skill heatsinks are definitely bigger and heavier.
> 
> Obviously this was a great occasion to compare the factory HS against something else.
> It's well known the "thermal pad" from G.Skill is very sticky and thin which raises a lot of questions about the thermal performances.
> 
> The answer is yes, there's much more glue than thermal material and the impact on temperature is quite sensible.
> The main goal for G.Skill is to glue the HS to the DIMM, not to provide a good thermal conduct to the HS.
> 
> Unfortunately their HS can't be used without something that can glue it to the DIMM.
> If you want to improve the temperature, without WC, you need to use the above modules from Alphacool or hopefully something better.
> You need to use a good thermal pad to improve thermally, so a locking mechanism is mandatory.
> 
> Removing the HS was quite easy; better to heat the DIMMs with some testing before shutting down and starting the job.
> But the glue was quite painful; took almost an hour to clean properly the 2 DR DIMMs.
> There's really a lot of glue and it's terribly sticky.
> 
> Initially I was planning to use the Minus Pad 8 from Thermal Grizzly.
> But @Pedros told me about the Gelid GP Extreme pads... 12 W/Mk.
> Much better than the 8 W/Mk from the Minus Pad 8.
> Couldn't find them on Amazon so I bought the GP Ultimate pads which are rated 15 W/Mk.
> 
> Considering these specs are more similar to thermal paste performance, the good ones, you'll wonder now: how?
> Well to be honest it's not a "classic" thermal pad; it's more solid thermal paste.
> Meaning it doesn't stick at all and it's extremely fragile. Shreds into tiny pieces with too much pressure at the wrong angle.
> It was quite painful to cut and place and the 0.5mm package must have been mishandled and one sheet was partially messed up.
> It's not easy but it can be done; I got away with 2 sheets 90x50mm.
> 
> 
> 
> 
> 
> 
> Gelid Solutions GP-Ultimate - Thermal Pad 90x50x0.5mm .: Amazon.de: Computer & Zubehör
> 
> 
> Gelid Solutions GP-Ultimate - Thermal Pad 90x50x0.5mm (2pcs). Ausgezeichnete Wärmeleitung, Idealer Lückenfüller. Einfache Installation Wärmeleitfähigkeit 15W - Kostenloser Versand ab 29€. Jetzt bei Amazon.de bestellen!
> 
> 
> 
> www.amazon.de
> 
> 
> 
> 
> 
> The result is that now in idle the DIMMs temperature improved about 1c.
> 
> The delta between the 2 DIMMs was about 0.8-1c, now it's 1-1.5c.
> 
> Stress under TM5 over 1h:30m before was 56.4c now it's 53.1c.
> 
> Doesn't look like much but, considering the HS itself is definitely much less capable, over 3c under stress it's a lot.
> Means reaching stability when it's just out of reach or another notch down in timings.
> 
> Of course running them with the WB under the loop is going to be a whole different story
> But if you don't have this option it's still a way to bring down the temp; rather expensive of course.
> I'll also mention that the Alphacool modules will hide the RGB LEDs, if you care about them.
> 
> If you wonder how I don't get errors in TM5 at over 56c it's because it's a good kit and I have an MSI B550 Unify-X.
> Same kit on the GB X570 Aorus Master Rel 1.0 starts erroring at 51c.



This is awesome, I'm piecing together a loop and the memory cooling is something I've been wondering how best to approach

Thanks a ton for sharing!

*Off topic:*


Spoiler



How is your work on OS power plans progressing? I'm using your "Snappy" plan and I'm enjoying it immensely


----------



## jomama22

ManniX-ITA said:


> My understanding is CLDO_VDDP, or just VDDP, is the DDR4 PHY on the cIOD SouthBound Interface; the one facing the physical DIMM sockets.
> There is another set of DDR4 PHY in the cIOD but on the NorthBound Interface; they encapsulate DDR4 data over the IF and communicate with a DDR4 PHY which is on each CCD (max 2 on Ryzen, more on TR and EPYC).
> Those DDR4 PHY VDDP can be adjusted by CPU_VDDP.
> 
> Now something for those interested in more stability for their OC using water-cooling (or not).
> I'm planning to use this block from Alphacool that I already have used for testing TECs and will use for the RAM in the next build:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Alphacool D-RAM Cooler X4 Universal - Acetal Black Nickel
> 
> 
> Mit den neuen Alphacool D-RAM Kühlern können nun alle beliebigen Speicherbausteine gekühlt werden. Dieser Kühlblock wird einfach auf die optional erhältlichen Kühlmodule oder auf vorhandene Heatspreader mit einem Lochabstand von 110mm...
> 
> 
> 
> 
> www.alphacool.com
> 
> 
> 
> 
> 
> I've replaced my G.Skill TridentZ RGB factory heatsinks with the corresponding set of Alphacool:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Alphacool D-RAM Modul (für Alphacool D-RAM Cooler) - Black 2 Stück
> 
> 
> Mit den Alphacool D-RAM Modulen lassen sich nun alle Speichersteine einfach und praktisch mit Wasserkühlern bestücken! Der unterschätzten Hitzequelle „Arbeitsspeicher“ wurde mit dem System der Alphacool D-RAM Kühler der Kampf angesagt....
> 
> 
> 
> 
> www.alphacool.com
> 
> 
> 
> 
> 
> The block is really good, the modules not so exciting but they are probably more than enough for the job.
> They are a bit short, barely covers the RAM ICs at the bottom and very light.
> The G.Skill heatsinks are definitely bigger and heavier.
> 
> Obviously this was a great occasion to compare the factory HS against something else.
> It's well known the "thermal pad" from G.Skill is very sticky and thin which raises a lot of questions about the thermal performances.
> 
> The answer is yes, there's much more glue than thermal material and the impact on temperature is quite sensible.
> The main goal for G.Skill is to glue the HS to the DIMM, not to provide a good thermal conduct to the HS.
> 
> Unfortunately their HS can't be used without something that can glue it to the DIMM.
> If you want to improve the temperature, without WC, you need to use the above modules from Alphacool or hopefully something better.
> You need to use a good thermal pad to improve thermally, so a locking mechanism is mandatory.
> 
> Removing the HS was quite easy; better to heat the DIMMs with some testing before shutting down and starting the job.
> But the glue was quite painful; took almost an hour to clean properly the 2 DR DIMMs.
> There's really a lot of glue and it's terribly sticky.
> 
> Initially I was planning to use the Minus Pad 8 from Thermal Grizzly.
> But @Pedros told me about the Gelid GP Extreme pads... 12 W/Mk.
> Much better than the 8 W/Mk from the Minus Pad 8.
> Couldn't find them on Amazon so I bought the GP Ultimate pads which are rated 15 W/Mk.
> 
> Considering these specs are more similar to thermal paste performance, the good ones, you'll wonder now: how?
> Well to be honest it's not a "classic" thermal pad; it's more solid thermal paste.
> Meaning it doesn't stick at all and it's extremely fragile. Shreds into tiny pieces with too much pressure at the wrong angle.
> It was quite painful to cut and place and the 0.5mm package must have been mishandled and one sheet was partially messed up.
> It's not easy but it can be done; I got away with 2 sheets 90x50mm.
> 
> 
> 
> 
> 
> 
> Gelid Solutions GP-Ultimate - Thermal Pad 90x50x0.5mm .: Amazon.de: Computer & Zubehör
> 
> 
> Gelid Solutions GP-Ultimate - Thermal Pad 90x50x0.5mm (2pcs). Ausgezeichnete Wärmeleitung, Idealer Lückenfüller. Einfache Installation Wärmeleitfähigkeit 15W - Kostenloser Versand ab 29€. Jetzt bei Amazon.de bestellen!
> 
> 
> 
> www.amazon.de
> 
> 
> 
> 
> 
> The result is that now in idle the DIMMs temperature improved about 1c.
> 
> The delta between the 2 DIMMs was about 0.8-1c, now it's 1-1.5c.
> 
> Stress under TM5 over 1h:30m before was 56.4c now it's 53.1c.
> 
> Doesn't look like much but, considering the HS itself is definitely much less capable, over 3c under stress it's a lot.
> Means reaching stability when it's just out of reach or another notch down in timings.
> 
> Of course running them with the WB under the loop is going to be a whole different story
> But if you don't have this option it's still a way to bring down the temp; rather expensive of course.
> I'll also mention that the Alphacool modules will hide the RGB LEDs, if you care about them.
> 
> If you wonder how I don't get errors in TM5 at over 56c it's because it's a good kit and I have an MSI B550 Unify-X.
> Same kit on the GB X570 Aorus Master Rel 1.0 starts erroring at 51c.


Actually putting water through it will keep the dimms well below 30c under any stress. 

Running TM5 for hours on end keep my 2x16 @ 1.5v below 26C with ambiant of 22C.

The trick to getting of the heatsinks is to just use a hair dryer/heat gun. EzPz. The glue comes right off with some rubbing alcohol. Havnt had any issues doing many kits this way. 

This is just using whatever thermal pads came with my bykski block. Which is much cheaper than the others and performs the same (it's a ram block after all).

The biggest tip is to actually use thermal paste between the ram block and ram covers. That alone with drop 2 degrees from using thermal pads/nothing at all.









Ram Blocks


Bykski US | Quality Water Cooling | Cutting Edge Designs




www.bykski.us


----------



## ManniX-ITA

jomama22 said:


> Actually putting water through it will keep the dimms well below 30c under any stress.
> 
> Running TM5 for hours on end keep my 2x16 @ 1.5v below 26C with ambiant of 22C.
> 
> The trick to getting of the heatsinks is to just use a hair dryer/heat gun. EzPz. The glue comes right off with some rubbing alcohol. Havnt had any issues doing many kits this way.
> 
> This is just using whatever thermal pads came with my bykski block. Which is much cheaper than the others and performs the same (it's a ram block after all).
> 
> The biggest tip is to actually use thermal paste between the ram block and ram covers. That alone with drop 2 degrees from using thermal pads/nothing at all.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Ram Blocks
> 
> 
> Bykski US | Quality Water Cooling | Cutting Edge Designs
> 
> 
> 
> 
> www.bykski.us


I'll have to wait a bit to run them under water, still need to do quite a lot to finish the build.
The bykski is nice but the Alphacool block is nickel plated copper, it's an excellent performer.
But indeed it's just a RAM block so the difference is probably negligible.
It's more that I already had it in inventory.

I don't recommend using an hair dryer anymore cause last time I did a friend managed to do some damage...
At least in my case was more than enough that the DIMMs were just warm.

Not sure the Alphacool modules heatsink can work with the thermal paste; there's an almost 0.5mm gap on each side.
Didn't try but maybe with the thermal paste the heatsink couldn't make enough grip on the DIMM.
Anyway wasn't really the best option for me cause the GP Ultimate pad is in theory better than the Kryonaut.
Which is the best thermal paste I have.
Theoretically is even better than the Kryonaut Extreme.


----------



## ManniX-ITA

TimeDrapery said:


> How is your work on OS power plans progressing? I'm using your "Snappy" plan and I'm enjoying it immensely


I'm pretty happy with it as it is.
Not doing more research; planning to add some stuff in the OC tool.
If you have some request or suggestion feel free to post in the thread!


----------



## jomama22

ManniX-ITA said:


> I'll have to wait a bit to run them under water, still need to do quite a lot to finish the build.
> The bykski is nice but the Alphacool block is nickel plated copper, it's an excellent performer.
> But indeed it's just a RAM block so the difference is probably negligible.
> It's more that I already had it in inventory.
> 
> I don't recommend using an hair dryer anymore cause last time I did a friend managed to do some damage...
> At least in my case was more than enough that the DIMMs were just warm.
> 
> Not sure the Alphacool modules heatsink can work with the thermal paste; there's an almost 0.5mm gap on each side.
> Didn't try but maybe with the thermal paste the heatsink couldn't make enough grip on the DIMM.
> Anyway wasn't really the best option for me cause the GP Ultimate pad is in theory better than the Kryonaut.
> Which is the best thermal paste I have.
> Theoretically is even better than the Kryonaut Extreme.


Bykski's are nickle copper, same thing.

And by where to put paste, I mean literally between the physical water block and the ram cover, not between the cover and the chips. So like between the top of the covers and the block.


----------



## ManniX-ITA

jomama22 said:


> Bykski's are nickle copper, same thing.
> 
> And by where to put paste, I mean literally between the physical water block and the ram cover, not between the cover and the chips. So like between the top of the covers and the block.


Nice to know, I did look around and only found references to aluminum.
Unfortunately doesn't seem a brand widely available in Europe.

Got it now; indeed between the block and the heatsinks I'm planning to use the thermal paste.


----------



## Pedros

We can also put some thermal pads between the block and the heatshield ... lets see when I do mines how it goes ... first, building the waterbox  then I'll try to cool down my xtreem's 4500s


----------



## skinnyq

Hey guys, I have a 5600x + Gigabyte b550i Aorus Pro AX mobo. I was testing for FCLK stability first and found I can get 1866 with no WHEA errors. 1900 will not boot and 1933 has WHEA errors. At 1866, it passed 1 hour of OCCT AVX2 large test.
So with this in mind I tried to overclock my 16x2 Ballistix 3200 CL16 kit. Here are the timings and voltages:








These passed an OCCT SSE memtest for 30 mins but failed OCCT AVX2 memtest with 3 errors.
Please anything you would do before dropping frequency even further?


----------



## ManniX-ITA

skinnyq said:


> These passed an OCCT SSE memtest for 30 mins but failed OCCT AVX2 memtest with 3 errors.
> Please anything you would do before dropping frequency even further?


What IC they have? Micron E-die?
Maybe post a Taiphoon burner summary.
I would first start testing with TM5 1usmus config.
If you use OCCT you could mix problems between CPU and memory stability.


----------



## Katana1074

Finally managed to get under 64ns not bad for a 3950X.....


----------



## craxton

TimeDrapery said:


> How is your work on OS power plans progressing? I'm using your "Snappy" plan and I'm enjoying it immensely


this a win 10 power plan? im currently having a "major bug" where my power plan 
vanishes, yes vanishes, and my CPU pings 100% usage every few seconds
yet its not actually doing anything and no task in task man or process explorer 
state anything's using the cpu. only happens when power plan is gone within win 10 
power plan section. 

so, might i ask where one might get this power plan you speak of??


----------



## ManniX-ITA

craxton said:


> this a win 10 power plan? im currently having a "major bug" where my power plan
> vanishes, yes vanishes, and my CPU pings 100% usage every few seconds
> yet its not actually doing anything and no task in task man or process explorer
> state anything's using the cpu. only happens when power plan is gone within win 10
> power plan section.
> 
> so, might i ask where one might get this power plan you speak of??


I doubt changing the Power Plan could be helpful, but you can try.
Are you sure there's no utility running in background or scheduled task that manipulates it?

This is the thread:








Ryzen Custom Power Plans for Windows 10/11 (Snappy...


CPUDoc now features a custom dynamic power plan with ultra low power in standby: https://github.com/mann1x/CPUDoc/releases/latest These are the custom power plans I've made for my 5950x. I have tested them as well on a 3800X and 5600G (not very thoroughly). They should not interfere with PBO...




www.overclock.net


----------



## Pictus

skinnyq said:


> Hey guys, I have a 5600x + Gigabyte b550i Aorus Pro AX mobo. I was testing for FCLK stability first and found I can get 1866 with no WHEA errors. 1900 will not boot and 1933 has WHEA errors. At 1866, it passed 1 hour of OCCT AVX2 large test.
> So with this in mind I tried to overclock my 16x2 Ballistix 3200 CL16 kit. Here are the timings and voltages:
> 
> 
> 
> 
> 
> 
> 
> 
> These passed an OCCT SSE memtest for 30 mins but failed OCCT AVX2 memtest with 3 errors.
> Please anything you would do before dropping frequency even further?


What I use with my Crucial Ballistix 2x16 3200MHz Micron 8Gbit E-Die
Verify if it is the same RAM with Thaiphoon Burner - Official Support Website








Download Thaiphoon Burner 16.7.0.4 Build 0509 Shareware / 16.7.0.3 Build 0109 Freeware


Download Thaiphoon Burner - This application displays multiple information about Serial Presence Detect and allows you to modify the firmware of SPD EEPROM devices




www.softpedia.com


----------



## skinnyq

Pictus said:


> What I use with my Crucial Ballistix 2x16 3200MHz Micron 8Gbit E-Die
> Verify if it is the same RAM with Thaiphoon Burner - Official Support Website
> 
> 
> 
> 
> 
> 
> 
> 
> Download Thaiphoon Burner 16.7.0.4 Build 0509 Shareware / 16.7.0.3 Build 0109 Freeware
> 
> 
> Download Thaiphoon Burner - This application displays multiple information about Serial Presence Detect and allows you to modify the firmware of SPD EEPROM devices
> 
> 
> 
> 
> www.softpedia.com












I will try your settings, is there a more time efficient memory benchmark than running TM5 for 3 hours?


----------



## Pictus

skinnyq said:


> I will try your settings, is there a more time efficient memory benchmark than running TM5 for 3 hours?


Y-chrucher y-cruncher - A Multi-Threaded Pi Program
Press 1 - 8 - 14 - 0
Test #14 is RAM, test #12 is CPU and the others are a mix CPU/RAM.


----------



## lmfodor

Hi everybody! I tell you that reading a year ago the great recommendations of @Veii, I was surprised by the amount of explanations and advice that helped me to take a small step. I managed to lower the tRCDRD to 15 and I hope to be able to lower it to 14 and flat since I have two references that are working well, at least they managed to do it. I know it is difficult but we are going to test if the PCB and the hardware support it. I actually found out that my PCB is A0, which I think is good. Well what I discovered reading is that the big mistake I was making was to follow the advice that I had to use a voltage range between 1.54 or 1.56 even to sustain a lower tWR, it was not so. In fact, these memories come with an XMP profile with 1.5V base, which suggests that from there it would be good. But the cases where I saw that they achieved 3800-14-14-14 were with 1.5V and the voltages at Auto. So I decided to follow the master´s advice and letting 1.5V for VDIMM, lower the vSOC to 1 .1V, IOD near 1V, CCD 0.94 and VDDP 0.88. In addition, another important tip was, lower the ProctODT as much as possible to achieve a better signal quality, and use stronger CADBUS to compensate in case of requiring higher voltage. With just that, but starting with 1T and GDM enabled I managed to follow suit, a great little step.









I must clarify that with these times above I already ran 3 times 25 cycles of TM5 1 Usmus, OOCT SSE and AVX Extreme, and y-cruncher all test 4 iterations a couple of times. So its quite stable and also I had a little improvment in the writea and copy speed since my last profile with tRCDRD 16.

I also tried to get 2T, but I started with errors 2 and 12 in TM5, so I suspect that GMD is helping me with to cover some mistake. So reading again, I see I should improve the following:

Set TRC to 42 that works almost perfect with TCL 14 and it needs tRFC of 294-215-134​
Set tRAS to 28. Just to math the rule set,​
Fix the CADBUS to 60-20-20--24, and could be 40-20-20-24 because I read it works fine with X570 boards.​
The issue I think would be the tRRDs/tWRDs, I think at first sight I could try lower the tWRTL o 8, but I know this is a common error that need to be align with the tRDWR and also the tRFCs, and also with the SCL that are tight but seems fine​
The tRDWR think is fine since these memories are Dual Rank, so +2 and 9/3 with I think would be fine. I don´t know if trying to lower the tWRRD to 2 would be better.​
Am I fine with the rationale? Now I could work better since I know that just 1.5 and the vSOC of 1.1 are fine and I don´t get errors 6, 10, 12, 0 in a few secconds..

What would be the error that GMD are masking?

This is a first step.. I´m still learning, reading a lot, and next stop will be the most difficult that is lowering *tCDRD to 14*, because only modifiying this value I start with the error 6 about 100 errors per miunute..! But I will not try flat...
Thanks for your advises!


----------



## ManniX-ITA

lmfodor said:


> What would be the error that GMD are masking?


I'd start from the CADBUS and Setup Timings.
The 6-3-3 as suggested by @Veii was meant to run with 40-20-20-20 or 60-20-20-20 and then fine-tuned with timings; I'm using 3-3-15.


----------



## lmfodor

ManniX-ITA said:


> I'd start from the CADBUS and Setup Timings.
> The 6-3-3 as suggested by @Veii was meant to run with 40-20-20-20 or 60-20-20-20 and then fine-tuned with timings; I'm using 3-3-15.


Yes, at first I thought to set the CAD BUS setup that is 3-3-15 for 3800.. I just have to set 20 flat for the 3 remaining values after ClkDrvStt, but at the time I read the Veii’s recommendation he didn’t mention to configure setup, just the following xx-20-20-24 being xx 40 or 60..b

But yes, definitely I will try it! Do you think that would be conflicting to disable GMD and set 2T? 
Thanks


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

lmfodor said:


> But yes, definitely I will try it! Do you think that would be conflicting to disable GMD and set 2T?


No conflict, that's how I'm running it


----------



## lmfodor

Another question, what are the values that I should pay attention to when trying to lower the TRCDRD to 14? I mean, should I rebuild my RTTs? Is there any advice for that? because I saw several configurations but I want to understand the rational one? I know from Veii he always mentions that to lower the primaries it is convenient to loose the TRDD / TWRD, or rather, loose some subs ... because in my current configuration if I only lower tRDCRD to 14, the 6 errors appear in burst mode! So it's seems something related to voltages or impedances not working right ... I did this many times just to test, but I want to know what to pay attention to: What confuses me when re-building RTTs is that although each one has its impedance RZQ 240ohm / x. That gives a partial value, but isn't it that I should rebuild if I increase the voltage? it would make more sense, to be all in sync. for example, to lower tRCDRD from 15 to 14, should you increase the vSOC?
Thanks 


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

lmfodor said:


> Another question, what are the values that I should pay attention to when trying to lower the TRCDRD to 14? I mean, should I rebuild my RTTs? Is there any advice for that? because I saw several configurations but I want to understand the rational one? I know from Veii he always mentions that to lower the primaries it is convenient to loose the TRDD / TWRD, or rather, loose some subs ... because in my current configuration if I only lower tRDCRD to 14, the 6 errors appear in burst mode! So it's seems something related to voltages or impedances not working right ... I did this many times just to test, but I want to know what to pay attention to: What confuses me when re-building RTTs is that although each one has its impedance RZQ 240ohm / x. That gives a partial value, but isn't it that I should rebuild if I increase the voltage? it would make more sense, to be all in sync. for example, to lower tRCDRD from 15 to 14, should you increase the vSOC?
> Thanks
> 
> 
> Sent from my iPhone using Tapatalk Pro


First, you need to consider that right now with GDM you are running tRCDRD at 16 since it's being autocorrected to an even value.
These BUS settings if I remember correctly are more reliable up to a certain voltage, around 1.5V and something.
You'll probably need to raise a lot the VDIMM to lower tRCDRD.
Not sure if at some point you need to adjust it.
Then yes, it's very likely you'll have to adjust tRDWR/tWRRD and maybe also raise SCL.
BTW I'd set tRTP half of tWR, plus try tWR at 12; works for me.

It's very hard to get tRCDRD at 14 with a Dual Rank kit; I couldn't get mine to run error free.
Also, after all the alterations to allow it I got worse performances.
But your kit is probably the best for this attempt at 3800MHz, give it a try.


----------



## lmfodor

ManniX-ITA said:


> First, you need to consider that right now with GDM you are running tRCDRD at 16 since it's being autocorrected to an even value.
> These BUS settings if I remember correctly are more reliable up to a certain voltage, around 1.5V and something.
> You'll probably need to raise a lot the VDIMM to lower tRCDRD.
> Not sure if at some point you need to adjust it.
> Then yes, it's very likely you'll have to adjust tRDWR/tWRRD and maybe also raise SCL.
> BTW I'd set tRTP half of tWR, plus try tWR at 12; works for me.
> 
> It's very hard to get tRCDRD at 14 with a Dual Rank kit; I couldn't get mine to run error free.
> Also, after all the alterations to allow it I got worse performances.
> But your kit is probably the best for this attempt at 3800MHz, give it a try.


Very good info! can you share me your timings with tRCDRD 15? And also your VDIMM, so I will use it as reference. Thanks!!


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

lmfodor said:


> Very good info! can you share me your timings with tRCDRD 15? And also your VDIMM, so I will use it as reference. Thanks!!
> 
> 
> Sent from my iPhone using Tapatalk Pro


Sorry, I didn't save any screenshot as it ended up in a failure 
I remember I had to raise tWTRS/L to get it more stable and SCL to 4 or 5.
About VDIMM it was over 1.55V for sure, maybe 1.57V.
You need to start worrying about temperature at these settings, goes too high and TM5 will drop hundreds of random errors.


----------



## lmfodor

Oh, no worries I have an big fan running at full speed above the memories. Running TM5 it reach a max of 40 degrees .. but almost near 39 degrees. Very good temps.. regarding your values, well when you have it please send it to me. Meanwhile I’m gonna making this changes and try.. thanks! 


Sent from my iPhone using Tapatalk Pro


----------



## GribblyStick

In case anybody else is using GSKILL F4-4000C15-8GTZR, Thaiphoon indicates them as A1, but taking them apart, it looks like they are actually A2:


----------



## craxton

ManniX-ITA said:


> I doubt changing the Power Plan could be helpful, but you can try.
> Are you sure there's no utility running in background or scheduled task that manipulates it?
> 
> This is the thread:
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Custom Power Plans for Windows 10/11 (Snappy...
> 
> 
> CPUDoc now features a custom dynamic power plan with ultra low power in standby: https://github.com/mann1x/CPUDoc/releases/latest These are the custom power plans I've made for my 5950x. I have tested them as well on a 3800X and 5600G (not very thoroughly). They should not interfere with PBO...
> 
> 
> 
> 
> www.overclock.net


no im 100% sure nothing is killing it that ive installed or downloaded/running
and theres no background task causing this either.

when i installed win 10 insider stable build this all started ive since reverted back, and reinstalled
or repaired windows with the installation media but no change. i can sign out and back in
after boot and all is well. but

while the power plan






here is gone or missing

the one that takes place inside the old style win 10 will auto swap between what ever the last
power plan i had selected and balanced profiles without me touching anything as if im
switching between the two.

i also ran a few commands to reinstall the old win 7 style power plan features for balanced and ultimate but
no change there either.

so hopefully this will help somehow.
if only i was getting some kinda WHEA or actual error stating hey somethings crashing,
id be fine with instability but, nothing....unless i raise CO and give less offset to positive voltage
thats the only time i WHEA (bsod) or have any LOG inside whea kernel logger.

thank you tho, going to try this out now.

this is what im talking about, perhaps its something to do with task manager
as process explorer says im good..










(EDIT) ive also tried reverting back to only two dimms with what i used for several months as
stable but still no change.

(EDIT 2) well ran the command with V5 power plan and no change.
wont even stay set.

have had task man running for a min now and this is what im actually seeing, 
(no actual cpu ping to 100% while checking process exp, and hwinfo) 
but yea here it is...never had this before (until 3 weeks ago)


----------



## thigobr

I was able to stabilize 3800MHz 2T 1.33V. Or it seemed stable but it always give me cold boot issues... I tried to play with RTTs, Drive strength, VDIMM and SOC voltages but no way to make it boot after turning off the computer. It will only cold boot with 1T GDM on.

Curiously 1T GDM disabled also seemed to work with ClkDrvStr at 120ohm as I got far longer TM5 and gaming sessions without errors. But cold boot issues were still present and when I tried to boot my Linux install: kernel panic! So it was certainly not stable.









If anybody has experience with high density Dual Rank DIMMs any help is welcome!


----------



## craxton

@ManniX-ITA not that its something i need to say,
but i figured out what my problem was, now my power profile stays to what i selected.

was windows management service being disabled. 
still, thanks for the power plan tho.


----------



## ManniX-ITA

craxton said:


> @ManniX-ITA not that its something i need to say,
> but i figured out what my problem was, now my power profile stays to what i selected.
> 
> was windows management service being disabled.
> still, thanks for the power plan tho.


Wow, wouldn't have thought about something like this.
Thanks for reporting it.

Did it fix also the CPU usage?
I see in your screenshots Precision X1 consuming 8%, doesn't look right.


----------



## Veii

GribblyStick said:


> In case anybody else is using GSKILL F4-4000C15-8GTZR, Thaiphoon indicates them as A1, but taking them apart, it looks like they are actually A2:
> View attachment 2488174


These are custom A2's + RGB traces
They have short traces like A1's , but the curves at the pinout, indicate A2
























=================
Double compare your results with the powerplans
There can be up to 150Mhz difference on stock








Balanced & Powersaver are broken with CTR - and cause idle-switch crashes
Usual DF-States issue that is enforced/enabled again, when running CTR

Got reports in 1202 seems to rework PBO again & "apparently" doesn't cause DF-States issues anymore
both 1201 and 1202 where on SMU 56.50
only some boards got 56.74? , something 56.70+


----------



## lmfodor

Hi Veii! You were missed around here! As always great contribution, I finally think I have an A1 PCB. I've been reading a lot about your notes last year, to write a book, but learning a lot. Still trying to lower my tRCDRD to 15 with GDM disable and then to 14 which seems like a big challenge in double rank and 14 flat (or nor flat). Also in parallel on another profile testing 4000-16-16-16.. a little harder for now! Share my progress in the previous posts, but you should have 1000 questions!!








PS: Taiphoon report B1, but for the pictures and the Gskill code it seems to be A1 for the 1st picture and on the side I was doubted with an A2 by the slot, but it looks more like the A1. The 04213X8810B code was supposed to identify the type of PBC, but I see that with the same code many say they have A1, A2 or B1.. Strange

Thanks! Martin


----------



## Veii

lmfodor said:


> I finally think I have an A1 PCB


For A2 (B2) they miss the cap at the bottom
For A1 (B1) they miss a placeholder for the ECC chip

Don't think it's either of them, but i miss A3 shematics
Traces have more A1 than A2 on them ~ but it's neither of both

Soo should be unique as for scaling behavior, and for RTTs (powering)


lmfodor said:


> Share my progress in the previous posts, but you should have 1000 questions!!


I quit as tech/community supporter & overclocker 
Just jump here and there back, to clear up unclear misunderstandings


----------



## lmfodor

Veii said:


> For A2 (B2) they miss the cap at the bottom
> For A1 (B1) they miss a placeholder for the ECC chip
> 
> Don't think it's either of them, but i miss A3 shematics
> Traces have more A1 than A2 on them ~ but it's neither of both
> 
> Soo should be unique as for scaling behavior, and for RTTs (powering)
> 
> I quit as tech/community supporter & overclocker
> Just jump here and there back, to clear up unclear misunderstandings


Thanks Veii, I don't want a post my advances again. Believe me, I'm reading your post of more than a year and taking notes of your advise and I because of that I have a good advances. You really make a difference!


----------



## ManniX-ITA

Veii said:


> I quit as tech/community supporter & overclocker


Oh no, so sad... 

@lmfodor 
You can find some good profiles in the spreadsheet:









Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com





Seems the king of DR kits that can go down to 14 with tRCDRD is the F4-3200C14-16GTZSK.
Pity I can't run these settings on my kit.
I can probably go higher with frequency but will be worthwhile only if and when AMD will fix higher than 1900 FCLK.
Take a look at it, maybe works on your kit.


----------



## rissie

I have been able to run Dual rank 16GB x 2 at 3800 with 1T and GDM off. That said, this only works with Windows 10 2004. I have random reboots when I update to 20H2 update -- so if you're having instabilities maybe check there? 

I got flat 14 primaries as well on this very low binned corsair 3200 cl 16 ram at 1.52V -- on the Aorus Master ver 1.0


----------



## mongoled

ManniX-ITA said:


> Oh no, so sad...


Its sad that we loose Veii input, but I am happy for him in that he can move and spend his time on more valuable things!

@Veii, I dont know how you held out so long, I know from experience its very draining when many many people want a piece of you while forgetting there is a thing called 'life' and that there is only so much one person can do, such a thankless task assisting countless people.

Wishing you all the best in your endevours and hopefully some "new blood" will appear and continue from the huge base of knowledge you have given us


----------



## mongoled

rissie said:


> I have been able to run Dual rank 16GB x 2 at 3800 with 1T and GDM off. That said, this only works with Windows 10 2004. I have random reboots when I update to 20H2 update -- so if you're having instabilities maybe check there?
> 
> I got flat 14 primaries as well on this very low binned corsair 3200 cl 16 ram at 1.52V -- on the Aorus Master ver 1.0
> 
> View attachment 2488203


Congratulation on those magic modules!

That is extremely rare to have flat 14's with 1T to the extent that I find it hard to believe !!!

Your hardware is aligned with stars

 

I wonder if your super low tFAW is tricking something somehere.....

Can you provide some AIDA64/Sandra screenshots at those settings ??


----------



## lmfodor

ManniX-ITA said:


> Oh no, so sad...
> 
> @lmfodor
> You can find some good profiles in the spreadsheet:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> Seems the king of DR kits that can go down to 14 with tRCDRD is the F4-3200C14-16GTZSK.
> Pity I can't run these settings on my kit.
> I can probably go higher with frequency but will be worthwhile only if and when AMD will fix higher than 1900 FCLK.
> Take a look at it, maybe works on your kit.


Hi! That is the spreadsheet I was looking for! I saw it once but hadn't bookmarked it. I see that you are on the table with excellent results running on 4133/2067. And with amazing bandwidth! Why do you say that you cannot raise the 1900FCLK? These are your current values? 

I'm going to try to copy them. If only it was as easy as copying values, but I'll try again. Every time I try to raise the FCLK above 1900, I get a lot of WHEAs, even with fewer errors in TM5. I don't even know why ... thanks for the link


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

I can run WHEA free only on the super slim benchmarking Windows install which is v1909.
Can't use these settings for the every day install running v20H2.
AGESA from AMD is bugged and despite they promised to fix it for mid-December they clearly failed to deliver...


----------



## lmfodor

ManniX-ITA said:


> I can run WHEA free only on the super slim benchmarking Windows install which is v1909.
> Can't use these settings for the every day install running v20H2.
> AGESA from AMD is bugged and despite they promised to fix it for mid-December they clearly failed to deliver...


Oh, I've got it. Well, I will keep working on the 3800 setup. I wonder who many members go up 4000MHz without WHEAs... I see a lot of them. Meybe as you said with a reduce Windows for benchmarking.

In the meantime, these are my best stable results. again, with 1T GMD enabled. If I have 2T I only have 2 errors.. I'm close. (I'm still using 1.5VDIMM)
I'll try this benchmark in safe mode. I'd like to lower the latencies, but just touch timings, not Windows.. I had read a Veii's post that said how to lower latencies, said to lower the tRFCs and other values that I don't remember now, I'm going to look for that post again


----------



## lmfodor

rissie said:


> I have been able to run Dual rank 16GB x 2 at 3800 with 1T and GDM off. That said, this only works with Windows 10 2004. I have random reboots when I update to 20H2 update -- so if you're having instabilities maybe check there?
> 
> I got flat 14 primaries as well on this very low binned corsair 3200 cl 16 ram at 1.52V -- on the Aorus Master ver 1.0
> 
> View attachment 2488203


Hi Rissie , I tried your values. One think that surprised me is the tFAW, I only see it at that value when use it for the exploit of TRC = tRAS + 1.. amazing But I couldn’t get post for the low number of the tRDWR below 9, with a dual rank seems a little hard to achieve! How you get to that timing. Pretty amazing. and the tWRRD in 4 also surprises me. 

I should have bought 2x8 SR .. I use it only for gaming, bad choice 


Sent from my iPhone using Tapatalk Pro


----------



## wuttman

lmfodor said:


> What would be the error that GMD are masking?
> I think the culprit is that your rcd can't do lower than 16, so gdm rounds it up back.


----------



## rissie

mongoled said:


> Congratulation on those magic modules!
> 
> That is extremely rare to have flat 14's with 1T to the extent that I find it hard to believe !!!
> 
> Your hardware is aligned with stars
> 
> 
> 
> I wonder if your super low tFAW is tricking something somehere.....
> 
> Can you provide some AIDA64/Sandra screenshots at those settings ??


I have aida on file but I do think it's influenced by clockspeed too much. I have included below (although different bios version but this should only be a minor difference).

At 4.5GHz core 0 (my best core on my 3900x is actually core 1)


Spoiler















At daily settings of 4.425GHz + 4.25GHz


Spoiler















And finally the Hynix DJRs GSKill Neos that I'm quite a fan of. You can see it's really not far behind the B die (0.7ns). I was just in an unusual position to pay much less for my lowbin B die (I came out ahead selling away the 3600 NEOs)



Spoiler


----------



## rissie

lmfodor said:


> Hi Rissie , I tried your values. One think that surprised me is the tFAW, I only see it at that value when use it for the exploit of TRC = tRAS + 1.. amazing But I couldn’t get post for the low number of the tRDWR below 9, with a dual rank seems a little hard to achieve! How you get to that timing. Pretty amazing. and the tWRRD in 4 also surprises me.
> 
> I should have bought 2x8 SR .. I use it only for gaming, bad choice
> 
> 
> Sent from my iPhone using Tapatalk Pro


From my experience, tRDWR needs to be balanced with tWRRD. Only one of it can be low (pretty sure Veii mentioned it quite awhile back, I just can't reference the post because it's been so long). Also note that I could not get 1T running before until I chanced upon some random user entry into the database with the bus settings of 56 56 56 (Veii has been sharing some 3 3 15; 4 4 18 settings). This was the only one that worked for me. 

Either way it's stable and I only notice very very slight differences when gaming when I first got the modules. i.e. I don't think it's worth pushing for it (considering how lengthy the stability tests are!) if you're already 2T GDM off stable.


----------



## lmfodor

rissie said:


> From my experience, tRDWR needs to be balanced with tWRRD. Only one of it can be low (pretty sure Veii mentioned it quite awhile back, I just can't reference the post because it's been so long). Also note that I could not get 1T running before until I chanced upon some random user entry into the database with the bus settings of 56 56 56 (Veii has been sharing some 3 3 15; 4 4 18 settings). This was the only one that worked for me.
> 
> Either way it's stable and I only notice very very slight differences when gaming when I first got the modules. i.e. I don't think it's worth pushing for it (considering how lengthy the stability tests are!) if you're already 2T GDM off stable.


Yes, I read that Veii post, that confused me a bit because it mentions higher than usual values like 18 and then divides them by two. I remember that only one should be lower and the other not, that's why I guess I couldn't boot, I don't know if I raised the tWRRD to 5 or more and instead of using tRDWR in 9 lower it to 6, but this is definitely a post refusal . I know there is a math behind it. I'm going to look for that post to understand the rational one. Regarding the 56 56 56 CADBUS configuration that I have never seen before. I know 3-3-15 works for 3800 and 4-4-18 for 4000 ..

But with my mobo I can't get POST. What mobo are you using? I'm tempted to buy the B550 Unify X because it has only two DIMM slots and it has better VRMs too. It came from the coils and these kinds of problems don't bother me. I read that BIOS is getting worse by some user on Unify Thread. I don't know if it has more options than the asus. The asus is very limited with so many options that I see here, and that Asus doesn't have them. Then maybe I will make the change. I can't quite understand why the same memories that I have with mobos with better VRMs achieve better values. That makes me suppose that I have a hardware limitation. I know that my benchmarks are excellent, but since I got into this topic and I am interested in learning, I first want to study the relationships between the values well but also with the sharpness of the hardware. The natural way would be to go to the Dark Hero, but I would like to leave asus at least on the motherboard, although the only thing I like is its BIOS


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

lmfodor said:


> I'm tempted to buy the B550 Unify X because it has only two DIMM slots and it has better VRMs too. It came from the coils and these kinds of problems don't bother me. I read that BIOS is getting worse by some user on Unify Thread


I'm the one complaining about the BIOS.
Some important options are missing, like CPU_VDDP.
The AMD CBS menu is missing as well, but sometimes we are graced with an XOC version which has it.
There are bugs with profiles management which makes quite difficult to test settings.
But in general I love the board, lots of good stuff and top notch memory OC.


----------



## skinnyq

@Pictus 
And others.

These settings are stable for me but where do I go from here?
Can't boot 1900 Mhz FCLK and 1933 Mhz has WHEA errors, so its about tightening timings and voltages now.
Suggestions?


----------



## Veii

skinnyq said:


> @Pictus
> And others.
> 
> These settings are stable for me but where do I go from here?
> Can't boot 1900 Mhz FCLK and 1933 Mhz has WHEA errors, so its about tightening timings and voltages now.
> Suggestions?
> 
> View attachment 2488262


SCL 4, tWRRD 4
tRRD_S 5, tRRD_L 7
tRP 18, tRAS 40, tRC 58
(calculate tRFC from the calculator for 16 gb dimms ~ B-2 mode. 580 tRFC)
Last, try tWR 10 , tRTP 8. Maybe even tRTP 5 @ 1.46v

Example by cm87








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


You can use this set to stabilize voltages & push FCLK & BLCK Runs at




www.overclock.net


----------



## PJVol

1.2.0.2 feels much snappier at mouse movement.


----------



## KedarWolf

This is what is WHEA free and stable on my Neo 3600 CL16 2x16GB.

If I run 6-3-3, 3-3-15 I get random reboots benchmarking etc.

So, if it also isn't working for you, you might try this. The run is so long because I changed it from 100% to 300%.

Also, for my Core Curve I run my CPU at a .0625 negative voltage offset. It reduces temps by 15C in OCCT and raised my R20 multicore almost 100 points.


----------



## lmfodor

KedarWolf said:


> This is what is WHEA free and stable on my Neo 3600 CL16 2x16GB.
> 
> If I run 6-3-3, 3-3-15 I get random reboots benchmarking etc.
> 
> So, if it also isn't working for you, you might try this. The run is so long because I changed it from 100% to 300%.
> 
> Also, for my Core Curve I run my CPU at a .0625 negative voltage offset. It reduces temps by 15C in OCCT and raised my R20 multicore almost 100 points.
> 
> View attachment 2488277
> 
> 
> View attachment 2488275
> 
> 
> View attachment 2488276


Hi @KedarWolf, It seems we have almost the same Kit, mine is 3800CL14 2x16 DR.. now I’m working to disable GDM and then try to lower tRCDRD to 14










How to do reach to a tRAS of 21? I mean the rule.. an also TRP of 19? Just to understand the calc.. thanks 


Sent from my iPhone using Tapatalk Pro


----------



## lmfodor

I’d need some advise to understand two things, why If I run this extact configuration but enabling 2T (GDM off) if got a few errors, some 2 and 10.. I know the meaning of the errors but I followed the principle due to I’m using a low VDIMM for this kit that is 1.5V, I use the lower proctOCT and just to compensate the voltage a stronger CtrDrvStr.. about the RTT I would run 7-3-3 or 6-3-3 or event RTTPark 1.. and also I keep lower SOC of 1.1 to be in line with the lower proctODT. So, what should I consider to enable 2T GDM off without errors?

Then the second challenge is to lower tRCDRD to 14, and I thing I should loose more both TWRD and TRDD, maybe 6-8-24-5-15 and then lower to 5-7-20-4-12, then raise SCL to 4 and maybe I should rise TWR but I don’t know how much and tRFC/2 instead the lowest what I’m using right now.. am I good with this setting? No matter what I try, I also got a huge amounts of error 6.. 100 by minute  and then a think. Should I also rise a bit VSOC, or leave it in 1.1 would be fine? If I rise it I should increase ProctODT to 40 right? Or 43 and perhaps RTT Nom disabled, WR at 3 and Park at 1.. this steps I already did and I can’t stop the bust or error 6… then 12..the 2 and some 10 If I should rise the voltage should be VDIMM and also VSOC? And rise a little IOD, but keeping Low VDDP? I have set SOC Uncore, so I would be hit in the right voltage .. what should I try to avoid this bunch of errors?









Thanks!


Sent from my iPhone using Tapatalk Pro


----------



## KedarWolf

lmfodor said:


> I’d need some advise to understand two things, why If I run this extact configuration but enabling 2T (GDM off) if got a few errors, some 2 and 10.. I know the meaning of the errors but I followed the principle due to I’m using a low VDIMM for this kit that is 1.5V, I use the lower proctOCT and just to compensate the voltage a stronger CtrDrvStr.. about the RTT I would run 7-3-3 or 6-3-3 or event RTTPark 1.. and also I keep lower SOC of 1.1 to be in line with the lower proctODT. So, what should I consider to enable 2T GDM off without errors?
> 
> Then the second challenge is to lower tRCDRD to 14, and I thing I should loose more both TWRD and TRDD, maybe 6-8-24-5-15 and then lower to 5-7-20-4-12, then raise SCL to 4 and maybe I should rise TWR but I don’t know how much and tRFC/2 instead the lowest what I’m using right now.. am I good with this setting? No matter what I try, I also got a huge amounts of error 6.. 100 by minute  and then a think. Should I also rise a bit VSOC, or leave it in 1.1 would be fine? If I rise it I should increase ProctODT to 40 right? Or 43 and perhaps RTT Nom disabled, WR at 3 and Park at 1.. this steps I already did and I can’t stop the bust or error 6… then 12..the 2 and some 10 If I should rise the voltage should be VDIMM and also VSOC? And rise a little IOD, but keeping Low VDDP? I have set SOC Uncore, so I would be hit in the right voltage .. what should I try to avoid this bunch of errors?
> View attachment 2488288
> 
> 
> Thanks!
> 
> 
> Sent from my iPhone using Tapatalk Pro


To get 2T GDM disabled try tRCDRD at 16 (GDM enabled it's running at 16 anyways) and maybe SCLs at 4.


----------



## Ethelneth

Hi all, here is what my daily setup looks like with 4x16GB single rank Crucial Ballistix 3600. These are 16Gb B-die Micron ICs (taiphoon reports them as C9BLH part number):










AIDA 64 measured bandwith: read ~55000 MB/s, copy ~53500 MB/s, write ~30399 MB/s, latency ~56.6 ns.
I've tried various tRRDS tRRDL tFAW tWTRS tWTRL tRDWR tWRRD combinations but improvements were marginal (~200MB/s read ~200-300MB/s copy at most) so I left them more or less stock. Most of the gains came from lowering tRFC to about 295ns and tRDRDDD, tWRWRDD from 5, 7 default to 4, 6. Unfortunately I couldn't get tWRRD below 2 since I'm running 4 sticks and tRTP below 11. Lowest bootable tRFC at 1900MHz fclk was 554.
I think these could easily hit 2000MHz but unfortunately my imc would start complaining with some bus interconnect errors at 1967 fclk and a lot at 2000 fclk.
I'd appreciate any suggestions on how to squeeze a bit more bandwidth out of these sticks


----------



## PJVol

Decided to give agesa 1.2.0.2 a go...


----------



## craxton

(edit) IGNORE THIS was meant as a message 
to someone needing help.....


----------



## The Pook

might play with the timings some more but really wish Asrock allowed higher DRAM voltage than 1.35v, I can't get 3600 even at ridiculous timings


----------



## rissie

lmfodor said:


> Yes, I read that Veii post, that confused me a bit because it mentions higher than usual values like 18 and then divides them by two. I remember that only one should be lower and the other not, that's why I guess I couldn't boot, I don't know if I raised the tWRRD to 5 or more and instead of using tRDWR in 9 lower it to 6, but this is definitely a post refusal . I know there is a math behind it. I'm going to look for that post to understand the rational one. Regarding the 56 56 56 CADBUS configuration that I have never seen before. I know 3-3-15 works for 3800 and 4-4-18 for 4000 ..
> 
> But with my mobo I can't get POST. What mobo are you using? I'm tempted to buy the B550 Unify X because it has only two DIMM slots and it has better VRMs too. It came from the coils and these kinds of problems don't bother me. I read that BIOS is getting worse by some user on Unify Thread. I don't know if it has more options than the asus. The asus is very limited with so many options that I see here, and that Asus doesn't have them. Then maybe I will make the change. I can't quite understand why the same memories that I have with mobos with better VRMs achieve better values. That makes me suppose that I have a hardware limitation. I know that my benchmarks are excellent, but since I got into this topic and I am interested in learning, I first want to study the relationships between the values well but also with the sharpness of the hardware. The natural way would be to go to the Dark Hero, but I would like to leave asus at least on the motherboard, although the only thing I like is its BIOS
> 
> 
> Sent from my iPhone using Tapatalk Pro


It's in the screenshots and post. Gigabyte X570 Aorus Master and the old version 1.0.


----------



## Iarwa1N

Iarwa1N said:


> Thanks for the help guys.
> 
> 
> 
> I tried your suggestion on both Agesa 1.1.9.0 and on latest 1.2.0.2 but it didn't even post on 3600. It did boot up on 3600 when I increased vDimm to 1.75v, but nothing below 1.75v works.
> 
> 
> 
> It didn't worked with the timings I posted below at 3600, only worked if I increased vDimm to 1.75v as I said below.
> 
> 
> 
> Your timings with trfc 288 didn't boot at 3600 unless I increased the vDimm to 1.75v, then it boots.
> 
> 
> 
> I tried 15 but didn't work as well, even if I try 18-20-20-20-40-60 as I said above it doesn't boot even at 3600 unless I increase vDimm to 1.75, then it boots.
> 
> 
> 
> Thanks for the help. It didn't boot at 3600 with this timings and I tried tRFC 288, 352, 440, all on auto, tRCDRD 15. It did boot with your exact timings at 3600 with 1.75v on dimms.
> 
> View attachment 2487319


I finally managed to run this dual rank b-die sticks at 3666 mhz without insane vdimm at 1.75v. It worked with procODT 53.3 and vdimm 1.55v but I couldn't manage to go any further than 3666mhz. I tried to try every combination of resistance settings but no luck, any suggestions?


----------



## danakin

Hello everyone,

pretty new to ram overclocking. im using a x570 unify, 5950x, 4*singlerank 8gb bdies (F4-3600C16Q-32GTZKK)

those are my timings and overall stats.

those temps are worrying me a bit. dimm0 is so much lower. also i get some wheas while testing. TM5 seems stable so far.

do you guys have any recommandations ?

best regards,

pete


----------



## BIaze

Hi, is it already possible to run 2000FCLK on 5900/5950X with current AGESA version? I'm on a 5900x and seemed to top out at 1966


----------



## GribblyStick

Possible? Yes! Likely? Not so much.


----------



## BIaze

what's a safe SOC/VDDP/VDDG voltages to use if you wanna try pushing for stable 2000FCLK?


----------



## PJVol

Add vdd18/pll to the "usual suspects" list


----------



## BIaze

don't seem to have that option available in my MB


----------



## ManniX-ITA

BIaze said:


> what's a safe SOC/VDDP/VDDG voltages to use if you wanna try pushing for stable 2000FCLK?





danakin said:


> pretty new to ram overclocking. im using a x570 unify, 5950x, 4*singlerank 8gb bdies (F4-3600C16Q-32GTZKK)
> 
> those are my timings and overall stats.
> 
> those temps are worrying me a bit. dimm0 is so much lower. also i get some wheas while testing. TM5 seems stable so far.


I would recommend:

VSOC => 1.125V 
VDDG IOD 1060mV
VDDG CCD 1000mV

Possible reason for WHEA, voltages too low and not enough distance between VDDG and VSOC
One DIMM is probably facing a fan, the outmost, that's why the temp is lower


----------



## wuttman

Welp, everything was rock stable in tests, until I used some cpu+gpu combined load to get whea's in my face.


----------



## BIaze

ManniX-ITA said:


> I would recommend:
> 
> VSOC => 1.125V
> VDDG IOD 1060mV
> VDDG CCD 1000mV
> 
> Possible reason for WHEA, voltages too low and not enough distance between VDDG and VSOC
> One DIMM is probably facing a fan, the outmost, that's why the temp is lower


thanks, i'll give that a shot

currently at
VSOC 1.15
VDDG IOD/CCD at 1.05v each

3933CL18(stock timing)/1966FCLK


----------



## ManniX-ITA

BIaze said:


> thanks, i'll give that a shot
> 
> currently at
> VSOC 1.15
> VDDG IOD/CCD at 1.05v each
> 
> 3933CL18(stock timing)/1966FCLK


I'm using VSOC 1.16V - to support memory OC
VDDG CCD at 1020mV - in theory 1000 is enough but since it's a 5950x a bit more juice
VDDG IOD at 1080mV - sweet spot would be 1060 but I need +20mV to support a USB M.2 10Gbps SSD which otherwise stops randomly


----------



## BIaze

ManniX-ITA said:


> I'm using VSOC 1.16V - to support memory OC
> VDDG CCD at 1020mV - in theory 1000 is enough but since it's a 5950x a bit more juice
> VDDG IOD at 1080mV - sweet spot would be 1060 but I need +20mV to support a USB M.2 10Gbps SSD which otherwise stops randomly


So if i can just use slightly lower voltages due to not having said usb m.2 and being on a 5900x?


----------



## BIaze

Oh i forgot, what about CLDO VDDP? Currently at 1


----------



## ManniX-ITA

BIaze said:


> So if i can just use slightly lower voltages due to not having said usb m.2 and being on a 5900x?


Indeed, at least for CCD and IOD.
VSOC being FCLK 1966 wouldn't go below 1.15V


----------



## ManniX-ITA

BIaze said:


> Oh i forgot, what about CLDO VDDP? Currently at 1


Unless there's a specific reason for, always better 900mV


----------



## BIaze

I assume you’re currently running 2000FCLK?


it seems i simply hit a wall trying to hit 2000 FCLK


----------



## wuttman

https://uploads.disquscdn.com/images/e5366bd20badcc447ae302e7e7ddcc7980c0b14e527de0452fc4a951d9a4deed.jpg


Hello, here's the puzzle. I thought it's stable, although I had to bump proc and vdd to fix whea's in occt. Accidentally I figured that combined cpu+gpu load (p95 large + gpu computing for example) throws whea's within minutes if not seconds. But 3800 is alright. Tried to change proc and add more voltage on cpu, soc and vdd, but no luck. Any thoughts? 

Another thing I would like tRCD at 16, what should I tweak to achieve it?


----------



## ManniX-ITA

BIaze said:


> I assume you’re currently running 2000FCLK?
> 
> 
> it seems i simply hit a wall trying to hit 2000 FCLK


Normally I run FCLK 1900, above that WHEA errors.


----------



## PJVol

BIaze said:


> don't seem to have that option available in my


----------



## ManniX-ITA

rissie said:


> I got flat 14 primaries as well on this very low binned corsair 3200 cl 16 ram at 1.52V -- on the Aorus Master ver 1.0


Thanks for sharing it, 56 is the magic number for the Unify-X and my kit as well.
On the Master 1.0 it was 61.
But I couldn't make it work with 6-3-3 or 7-3-3, only Off-3-1.
After being fed up by the atrocious bugs in the Unify-X BIOS, gave up on testing tRCDRD 15 at 2T/1T.
Was working briefly with 2T, no hope with 1T.
Then I had to recreate the profile from scratch and my 2T settings doesn't work anymore...

Now I'm testing the 1T profile below but it gets pretty hot, had to increase VDIMM to 1.54V and VTT to 1.50V.
Lost a 0.1ns in latency compared to 2T but gained some peanuts in bandwidth.

@lmfodor
Maybe you can try to push tRCDRD to 15 starting from this one
(But fixing the tRTP to 7, not sure how it ended up set to 14...)


----------



## Iarwa1N

ManniX-ITA said:


> Thanks for sharing it, 56 is the magic number for the Unify-X and my kit as well.
> On the Master 1.0 it was 61.
> But I couldn't make it work with 6-3-3 or 7-3-3, only Off-3-1.
> After being fed up by the atrocious bugs in the Unify-X BIOS, gave up on testing tRCDRD 15 at 2T/1T.
> Was working briefly with 2T, no hope with 1T.
> Then I had to recreate the profile from scratch and my 2T settings doesn't work anymore...
> 
> Now I'm testing the 1T profile below but it gets pretty hot, had to increase VDIMM to 1.54V and VTT to 1.50V.
> Lost a 0.1ns in latency compared to 2T but gained some peanuts in bandwidth.
> 
> @lmfodor
> Maybe you can try to push tRCDRD to 15 starting from this one
> (But fixing the tRTP to 7, not sure how it ended up set to 14...)
> 
> 
> View attachment 2488410
> 
> 
> View attachment 2488411


When should we use the VTT and which values is suitable?

I finally managed to run my kit at 3600 mhz with the following settings, I didn't try change VTT, maybe it could help to achieve more than 3600mhz. Don't mind the VSOC, I was just trying something.


----------



## ManniX-ITA

Iarwa1N said:


> When should we use the VTT and which values is suitable?


I always use it; lowers the required VDIMM and the need for higher impendence on RTT, fixes a lot instabilities.
In general I use 40-50mV negative offset from VDIMM.
Only once had a beneficial effect over 50 with FCLK above 2033; over 100mV offset it's counter productive.


----------



## lmfodor

ManniX-ITA said:


> Thanks for sharing it, 56 is the magic number for the Unify-X and my kit as well.
> On the Master 1.0 it was 61.
> But I couldn't make it work with 6-3-3 or 7-3-3, only Off-3-1.
> After being fed up by the atrocious bugs in the Unify-X BIOS, gave up on testing tRCDRD 15 at 2T/1T.
> Was working briefly with 2T, no hope with 1T.
> Then I had to recreate the profile from scratch and my 2T settings doesn't work anymore...
> 
> Now I'm testing the 1T profile below but it gets pretty hot, had to increase VDIMM to 1.54V and VTT to 1.50V.
> Lost a 0.1ns in latency compared to 2T but gained some peanuts in bandwidth.
> 
> @lmfodor
> Maybe you can try to push tRCDRD to 15 starting from this one
> (But fixing the tRTP to 7, not sure how it ended up set to 14...)
> 
> 
> View attachment 2488410
> 
> 
> View attachment 2488411


Hi Mannix! I will try this values this night. Increíble that you could enable 1T GDM off with Dual Rank 2x16 as mine. But my goal is to lower tRCDRD to 14.. with a middle step of 15.. I’m running fine with tRCDRD 16.. I want to see how to lower to 14…

About your values, Why TRP is 14 instead of TWR/2? and tWTR wouldn’t be 4 12? Did you try to lower tRCDRD to 14? I’m still wonder how you enabled 1T GDM off!!


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

lmfodor said:


> Hi Mannix! I will try this values this night. Increíble that you could enable 1T GDM off with Dual Rank 2x16 as mine. But my goal is to lower tRCDRD to 14.. with a middle step of 15.. I’m running fine with tRCDRD 16.. I want to see how to lower to 14…
> 
> About your values, Why TRP is 14 instead of TWR/2? and tWTR wouldn’t be 4 12? Did you try to lower tRCDRD to 14? I’m still wonder how you enabled 1T GDM off!!
> 
> 
> Sent from my iPhone using Tapatalk Pro


That was a typo, I had to input again all the timings.










This is the right one.

I can run 1T with the RTT above, 36.9 Ohm at Off-3-1; straight 20 Ohm for the CAD and 56-56-56 on setup timings.
No way to make it stable with different RTT.

I also need tRDWR/tWRRD at 8/3 and SCL at 3.
Lower than that I need to clear CMOS.

Your kit and mainboard are different so it couldn't work for you. On the Aorus Master the same kit needed 61-61-61.

You an try to go lower tRCDRD, I could make it run stable at 15 with 2T.
If your kit is better than mine maybe it's possible to run it at 14 with 2T.
I wouldn't focus too much on 1T, just a bit faster but needs more voltage and the DIMMs are running hot, peaking 56c now.

I've tested with 1 CCD only and could reach 52.8ns in latency.
For single CCD CPUs maybe it makes sense the effort but for dual not really much.


----------



## Pictus

Veii said:


> (calculate tRFC from the calculator for 16 gb dimms ~ B-2 mode. 580 tRFC)


Thank you!
I changed the tRFC_2 to B2









I do not want to use higher voltages, so I will stay with 3733MHz 1.38V tRFC=600


----------



## lmfodor

ManniX-ITA said:


> That was a typo, I had to input again all the timings.
> 
> View attachment 2488425
> 
> 
> This is the right one.
> 
> I can run 1T with the RTT above, 36.9 Ohm at Off-3-1; straight 20 Ohm for the CAD and 56-56-56 on setup timings.
> No way to make it stable with different RTT.
> 
> I also need tRDWR/tWRRD at 8/3 and SCL at 3.
> Lower than that I need to clear CMOS.
> 
> Your kit and mainboard are different so it couldn't work for you. On the Aorus Master the same kit needed 61-61-61.
> 
> You an try to go lower tRCDRD, I could make it run stable at 15 with 2T.
> If your kit is better than mine maybe it's possible to run it at 14 with 2T.
> I wouldn't focus too much on 1T, just a bit faster but needs more voltage and the DIMMs are running hot, peaking 56c now.
> 
> I've tested with 1 CCD only and could reach 52.8ns in latency.
> For single CCD CPUs maybe it makes sense the effort but for dual not really much.


Yes, what I make me some noise maybe it’s because I’m trying to follow the rule set.., for instance, you have a high value of VSOC with lower ProctODT and weaker CADBUS, at least the first one. Maybe 60-20-20-20 with setup of 3-3-15 would be more stable? And you can lower VDIMM and stay at 1.1 of VSoc. But I think that 40 ProcODT or 43 would fit better and maybe 40-20-20-20.. (for your voltages) and then the TRP and TWR.. should be equal, again by the rules..and twrtr_l = tRRD_L x 2
But I’m running fine with tRDCRD at 16.. the challenge is to lower to 15 and 14.. that’s when the errors comes 
Thanks!




Sent from my iPhone using Tapatalk Pro


----------



## Veii

Pictus said:


> Thank you!
> I changed the tRFC_2 to B2
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I do not want to use higher voltages, so I will stay with 3733MHz 1.38V tRFC=600


The timings are pretty much identical to the post i quoted ~ you quoted
Only tWRRD here is correct
tWR could go down a bit , tRP can go down to 18 and so tRC too (with tRFC)
tFAW is too high, 4* tRRD_S , always !
Only exceptions are exploits on tRAS+1=tRC (dual rank +2) but that needs a bump on tRDWR, and a high bump on tRRD, soo also bump on tFAW & 5-14 tWTR
Meaning, always stay at tFAW = tRRD_S , till you find methods to lower it further without choking it. Lower can run but most of the times performs worse because of "cycle sync"
Memory never does "only read" or "only write" multiple things happen ~ soo alignment is key. The only time it does only one thing, is by waiting for tRC to elapse, before anything else can happen 


T884G63 said:


> @Veii what LLC / power settings have you been
> testing with?
> 
> 1.8 PLL for 1900-2000+?
> 
> I was just able to boot 1966 in sync with auto LLC /
> power settings with just your voltages but auto
> ram timings.
> 
> Gonna try my 3800C14 profile LLC / power settings
> but with your voltage settings on auto timings and
> see if I can finally get boot 2000


I never answered that, oops

Renesas 90A where working well under 500khz switching freq with loadline 2 under flat (Lv 3/5) & SOC at Lv 2/5 - switching freq 500Khz
The only time i really changed much was when running CTR, that is then Lv 1 flat with 500khz
Else on default lv 5 (lowest) with 600khz works well

SOC strangely overshoots on LLC 1 flat even at 400khz
Vcore sometimes was at 600khz sometimes at 500, depends how i feel about negative CO and positive vcore offset
Optimals keep changing, when AMD keeps changing the boosting table 

About 1.8 PLL, i've tried it higher like PJVol suggested,
But it only result in instability ~ could be my PSU here too unsure
1.83 is constantly supplied, 1.86 didn't bring anything. 1.9 rarely but still booted, 1.93 didn't post at all anymore

CPU VDDP is read out correctly, and adjusted read out correctly
With "higher" VDDGs compared to my initial 930mV VDDG CCD one, there are no issues jumping between 860mV-900mV
Still don't like the 930mV that are supplied on stock for ASRock boards, but 900mV is currently just as fine as 860mV was
The 870mV and 890mV holes i had, are now gone.
Either because dLDO functions on SMU 56.44+ or because VDDG voltages for 2100 FCLK are now "a bit better"

2133 is still unrunnable without autocorrection
stable , likely but performs horrible (not lower than 50ns, while it should be 48 or lower ~ when 2100C15 is 48.5)
Oh good luck on 4000C14-14, it's as hard as 4200C15-14


----------



## ManniX-ITA

lmfodor said:


> Yes, what I make me some noise maybe it’s because I’m trying to follow the rule set.., for instance, you have a high value of VSOC with lower ProctODT and weaker CADBUS, at least the first one. Maybe 60-20-20-20 with setup of 3-3-15 would be more stable? And you can lower VDIMM and stay at 1.1 of VSoc. But I think that 40 ProcODT or 43 would fit better and maybe 40-20-20-20.. (for your voltages) and then the TRP and TWR.. should be equal, again by the rules..and twrtr_l = tRRD_L x 2
> But I’m running fine with tRDCRD at 16.. the challenge is to lower to 15 and 14.. that’s when the errors comes
> Thanks!
> 
> 
> 
> 
> Sent from my iPhone using Tapatalk Pro


The beauty with B-die is to break the rules 
Voltages and RTT are not a wish but a need.
You can't set what you'd like without thinking about the timings.

Voltage is needed to support tight timings, otherwise you need to relax them.
And that's the opposite of what we want to achieve 
As well too much can have a negative effect; for 1T tRCDRD 15 my sweet spot was 1.56V at 32 Ohm ProcODT.
Then it's all a matter of fine-tuning.

VSOC as well is part of it; I ended up with a couple of error 6, 2 and 10.
Was able to fix the error 6 only with VSOC from 1.16V to 1.175V.
Higher VSOC means better performances and also more stability.



lmfodor said:


> Maybe 60-20-20-20 with setup of 3-3-15 would be more stable?


For me to run 1T the setup timings must be 56-56-56.
Works stable only with RTT Off-3-1 for me.
Probably the same for you; 6-3-3 with 3-3-15 seems more suited for 2T and GDM.
Still have to play with ClkDrvStr and ProcODT.
Maybe I can raise the first and lower the latter.

But don't be surprised by the flat 20; the Unify-X with 2 slots just loves low impedance.
Which is great cause it's less signal noise, you can pump a bit more voltage without getting in trouble and with lower temps.

For the "rules" take as a reference the good scores in the Zen spreadsheet.
You'll learn the amazing things that can be done abusing them.
Not all tricks works the same on all kits, they have different PCBs, different motherboard, BIOS, AGESA, etc
I still can't find a way to exploit 1xtFAW.


----------



## ManniX-ITA

Veii said:


> About 1.8 PLL, i've tried it higher like PJVol suggested,
> But it only result in instability ~ could be my PSU here too unsure
> 1.83 is constantly supplied, 1.86 didn't bring anything. 1.9 rarely but still booted, 1.93 didn't post at all anymore


Tried as well; I don't get instability with the Unify-X but it doesn't help at all with WHEA.
Gets unstable going lower than 1.8V


----------



## PJVol

ManniX-ITA said:


> it doesn't help at all with WHEA


Why it should...


----------



## ManniX-ITA

PJVol said:


> Why it should...


Did I misunderstand? 
Thought it was helpful to alleviate WHEA errors with FCLK above 1900


----------



## PJVol

ManniX-ITA said:


> Did I misunderstand?
> Thought it was helpful to alleviate WHEA errors with FCLK above 1900


I dont have such experience unfortunatlely, what I have found is it somehow helped to reduce package throttling (in my case) with fclk 1933+.
Surely it would be nice to see someone else's experience on this topic.

PS: I'd like to clarify that me personally don't give a damn thing about these whea's untill they mean something's really bad. I'm talking now exclusively about GMI error MCE
Had I so powerfull VRM/PWM loadline in my board as You and Veii have , I wouldnt care about that damn thing at all ))


----------



## ManniX-ITA

PJVol said:


> I dont have such experience unfortunatlely, what I have found is it somehow helped to reduce package throttling (in my case) with fclk 1933+.


Got it now, can't help in this case... I get WHEA but no package throttling.


----------



## Pictus

Veii said:


> tWR could go down a bit , tRP can go down to 18 and so tRC too (with tRFC)
> tFAW is too high, 4* tRRD_S , always !
> Only exceptions are exploits on tRAS+1=tRC (dual rank +2) but that needs a bump on tRDWR, and a high bump on tRRD, soo also bump on tFAW & 5-14 tWTR
> Meaning, always stay at tFAW = tRRD_S , till you find methods to lower it further without choking it. Lower can run but most of the times performs worse because of "cycle sync"
> Memory never does "only read" or "only write" multiple things happen ~ soo alignment is key. The only time it does only one thing, is by waiting for tRC to elapse, before anything else can happen


Thank you!
Changed the tRW/tFAW/tRDWR/tRP/tRC/tRFC
tRFC 580 is working ok.


----------



## Iarwa1N

Pictus said:


>


Can you share the link to this spreadsheet?


----------



## Pictus

Iarwa1N said:


> Can you share the link to this spreadsheet?


Here Ryzen Google Calculator v0.7.x 🔥


----------



## BIaze

PJVol said:


> View attachment 2488409


ah thanks for the pointer, i'll keep that in mind


----------



## craxton

HMMM regarding SOC voltage for 5600x processors running 4000mhz 2000fclk
4x8 2t config, does one absolutely need 1.2V thru SOC voltage ?

have seen several others on the spread sheet posting way lower soc voltages 
currently running at 1.17 instead of 1.21, nothing out the ordinary yet. 
OCCT ran fine, AIDA ran fine (concurrent anyhow) 

Does it simply depend on ones chip/luck?


----------



## ManniX-ITA

craxton said:


> Does it simply depend on ones chip/luck?


Not only, depends also on the BIOS/AGESA.
First releases for Unify-X my 5950x needed crazy SOC voltages over 1.2V to POST over FCLK 2000.
Now it can POST with 1.1V but I need around 1.18V to get good performances.


----------



## lmfodor

Hi! I've been working with the timings to try to get tRCDRD at 15 with 2T GDM Off. Among some timings that I took as a reference I found this one that at first seemed to work well, at least not WHEA or TM5 error, but then in another cycle of TM5 tests 1usmus gave me an error 10 and also tested y-cruncher all the tests and did not pass the VST . In fact, beyond copying the values, I tried to fix the values to match some ruleset, for example I don't understand why the tRAS is so low (23), nor do the tRFC values coincide with those of a tCL 14 and tRC 43 (should be 258-192-118). Then the tWR in 14 with the tRTP 8 either and I see very high the tRDWR ratio at 10 vs the tWRRD at 1. (I have DR kit, so I guess 10-3 would be better). That's what I dont understand, however again this was the best settings to lower tRCDRD to 15 with my kit so far.

Regarding the error 10, RAM overheating is not, I was running at 37 degrees. CADBUS not optimal could be. With my 1T I was using a lower ProcODT of 36 and a CADBUS stronger with 60-20-24-24. however, my standar XMP profile and other test that I saw with my memory kit are the same, I mean, ProctODT of 43, RTTNom disable, RttWR 3 and RTTPark at 1, with VDIMM 1.5. tRFCs to slow I don't beleive it, because my with the tRFC calc with TCL 14 and tRC 43 it gave me 258, 142, 118 instead of 266-148-122, pretty close. and I would try VDIMM 1.5, I set 1.51.. maybe I could lower it to 1.5. Regarding tFAW it's seems to be right and tRAS, is a number to slow that I don't understand how they got to it









The bandwidth values are below my stable configuration with 1T with GDM on, and the latency is similar. I'm a little closer, but beyond the rules, obviously these times worked for someone and they do not seem so far from to fix it from where I am now

What I tested over that baseline (the second timinig with 2T Config below) was:

Set tRAS to 30, tRC leaves to 42, but it should be 44)
Set TWR to 16 to keep tRTP to 8 and inverse, lower tRTP to 7 to 14
I also try to loose tRRRD to 2 and 3.. and also tRRDs from 4 4 to 4 6 and the tWTRs to 4 12..
All of this changes, gave different errors, so maybe there's something I'm missing.

So, this configuration I tested was the one with less errors that I tried, just a a 10, and I feel I'm a little close to lower tRCDRD to 15 with 2T and keep improving.

Would you help me with some advises to try? Thanks!!!


----------



## heavyrain

lmfodor said:


> Hi! I've been working with the timings to try to get tRCDRD at 15 with 2T GDM Off. Among some timings that I took as a reference I found this one that at first seemed to work well, at least not WHEA or TM5 error, but then in another cycle of TM5 tests 1usmus gave me an error 10 and also tested y-cruncher all the tests and did not pass the VST . In fact, beyond copying the values, I tried to fix the values to match some ruleset, for example I don't understand why the tRAS is so low (23), nor do the tRFC values coincide with those of a tCL 14 and tRC 43 (should be 258-192-118). Then the tWR in 14 with the tRTP 8 either and I see very high the tRDWR ratio at 10 vs the tWRRD at 1. (I have DR kit, so I guess 10-3 would be better). That's what I dont understand, however again this was the best settings to lower tRCDRD to 15 with my kit so far.
> 
> Regarding the error 10, RAM overheating is not, I was running at 37 degrees. CADBUS not optimal could be. With my 1T I was using a lower ProcODT of 36 and a CADBUS stronger with 60-20-24-24. however, my standar XMP profile and other test that I saw with my memory kit are the same, I mean, ProctODT of 43, RTTNom disable, RttWR 3 and RTTPark at 1, with VDIMM 1.5. tRFCs to slow I don't beleive it, because my with the tRFC calc with TCL 14 and tRC 43 it gave me 258, 142, 118 instead of 266-148-122, pretty close. and I would try VDIMM 1.5, I set 1.51.. maybe I could lower it to 1.5. Regarding tFAW it's seems to be right and tRAS, is a number to slow that I don't understand how they got to it
> View attachment 2488498
> 
> 
> The bandwidth values are below my stable configuration with 1T with GDM on, and the latency is similar. I'm a little closer, but beyond the rules, obviously these times worked for someone and they do not seem so far from to fix it from where I am now
> 
> What I tested over that baseline (the second timinig with 2T Config below) was:
> 
> Set tRAS to 30, tRC leaves to 42, but it should be 44)
> Set TWR to 16 to keep tRTP to 8 and inverse, lower tRTP to 7 to 14
> I also try to loose tRRRD to 2 and 3.. and also tRRDs from 4 4 to 4 6 and the tWTRs to 4 12..
> All of this changes, gave different errors, so maybe there's something I'm missing.
> 
> So, this configuration I tested was the one with less errors that I tried, just a a 10, and I feel I'm a little close to lower tRCDRD to 15 with 2T and keep improving.
> 
> Would you help me with some advises to try? Thanks!!!
> 
> View attachment 2488497


Your GDM 1T and 2T have different ProcODT, RTT, CAD_BUS; 
so ,dose these timings depend on command rate？Don't exist general setting? (Suppose other variable are same，the only difference is command rate)


----------



## lmfodor

heavyrain said:


> Your GDM 1T and 2T have different ProcODT, RTT, CAD_BUS;
> so ,dose these timings depend on command rate？Don't exist general setting? (Suppose other variable are same，the only difference is command rate)


Hello! Yes, that's right, because I copied the exact timings I found as an aca reference in the forum, I tried using my stables but it seems to have nothing to do with these values. So I'm going to have to go back to the base ones and see that I might be making the few errors. I back to the original values that are equals that the timings I found here. So, there is somethings that more than the impdence seems to be related to timings.. right? The strange thing is that I run 15 cycles without errors.. same settings..


----------



## wuttman

@imfodor
Excuse me, why is your tRTP at 8? And with these tRAS, tRRDL, tWTRL, tCWL, tWRRD and tRFC you don't seem like really trying to stabilize tRCDRD.


----------



## TimeDrapery

Here's an update on my progress with this "1T CR / GDM set to Disabled" timing set (flashed the latest Gigabyte beta BIOS with 1.2.0.2 so I started over from scratch with the set)



Spoiler: Screenshots























































I'm currently conducting stability testing on the timing set as depicted in the second screenshot and I'll update with my results as I've got them

Any advice? Please share your thoughts!

*Edit*: "_The testing is completed, of errors is not detected._" 😁😁😁😁😁


----------



## ManniX-ITA

Should have finished messing with the 1T profile, testing with real world usage now.
Despite passing 1h:30m of TM5, Chrome was crashing with tRFC 238. Had to go back to tRFC 252.

Even at 1.52V the temperatures did not change much; now I'm at 1.53V, reach 56.1c tops 56.6c.
Running at 1T it gets really hot and very quickly compared to 2T.

No way to lower tRRD below 4/6 or tWTR 4/10, crashing at test 0 or 15. 
Maybe with higher VDIMM, I'll have to see with water cooling.

Latency is down to 54.4ns which is lowest I can do with dual CCD.
Bandwidth is quite good, top notch for 3800MHz, over 59GB/s for R/W and 57GB/s for Copy.
Can't complain but not much more than could be achieved with 2T with lower temps.




















Spoiler: Voltages















Then a couples of tips for MSI boards



Spoiler: How to run L3 full speed, thanks Veii. Caution it can introduce instability

















Spoiler: How to abuse telemetry to bump single core boosting


----------



## lmfodor

lmfodor said:


> Hello! Yes, that's right, because I copied the exact timings I found as an aca reference in the forum, I tried using my stables but it seems to have nothing to do with these values. So I'm going to have to go back to the base ones and see that I might be making the few errors
> 
> View attachment 2488500
> 
> 
> 
> 
> wuttman said:
> 
> 
> 
> @imfodor
> Excuse me, why is your tRTP at 8? And with these tRAS, tRRDL, tWTRL, tCWL, tWRRD and tRFC you don't seem like really trying to stabilize tRCDRD.
> 
> 
> 
> Yes, maybe I was not so clear with the screenshots. Currently my stable configuration is this, which is with 1T and GDM enabled, and my first goal is to lower the tRCDRD to 15, and being GDM enabled I understand that it rounds 15 to 16. That is why I want to activate 2T. As when doing it I have several errors, what I did instead of optimizing my current values, was to take other configurations that I saw here in the thread and test if any of them work well. And I found this one, that I take it as a reference because it is also a 2x16 and dual rank kit. So I decided to try and at first I had no errors, however now they appeared.
> 
> This is my stable configuration with 1.5T
> 
> 
> 
> 
> 
> 
> 
> 
> 
> And this is the one that I take as a model, that I copy from another member, and now it is giving me these errors:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Thanks!
Click to expand...


----------



## wuttman

@Imfodor I'm a noob, but I think that even if copies of messed up timings will give you stability, it would be due to out of sync and auto correction throttling. I'm currently trying to put rcd in line with other primaries myself, but I think the only chance to make it happen is through correct proc, rtt and cad bus settings.


----------



## ManniX-ITA

The 1T profile shows the muscles in Sandra and by a big margin.
Between 100-150 GB/s improvement in transfers with data chunks between 16x 4kB and 4x 1024kB.

@Veii look at this beautiful graph, this is with min processor state 100%











Spoiler: Aggregated results

















Spoiler: Bench results






Code:


SiSoftware Sandra

Benchmark Results
Inter-Core Bandwidth : 168.48GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Inter-Core Latency : 44.1ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Inter-Core Bandwidth : 5.26GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Speed
Inter-Core Bandwidth : 50.74MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Inter-Core Latency : 0.13ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-U2 Data Latency : 24.8ns
U0-U4 Data Latency : 26.3ns
U0-U6 Data Latency : 24.6ns
U0-U8 Data Latency : 26.0ns
U0-U10 Data Latency : 24.9ns
U0-U12 Data Latency : 26.0ns
U0-U14 Data Latency : 25.4ns
U0-U16 Data Latency : 61.7ns
U0-U18 Data Latency : 61.1ns
U0-U20 Data Latency : 62.6ns
U0-U22 Data Latency : 62.1ns
U0-U24 Data Latency : 61.6ns
U0-U26 Data Latency : 60.9ns
U0-U28 Data Latency : 61.6ns
U0-U30 Data Latency : 61.2ns
U0-U1 Data Latency : 12.8ns
U0-U3 Data Latency : 24.9ns
U0-U5 Data Latency : 26.1ns
U0-U7 Data Latency : 24.6ns
U0-U9 Data Latency : 26.0ns
U0-U11 Data Latency : 25.0ns
U0-U13 Data Latency : 26.1ns
U0-U15 Data Latency : 25.4ns
U0-U17 Data Latency : 61.6ns
U0-U19 Data Latency : 61.0ns
U0-U21 Data Latency : 62.3ns
U0-U23 Data Latency : 61.4ns
U0-U25 Data Latency : 61.3ns
U0-U27 Data Latency : 61.4ns
U0-U29 Data Latency : 61.5ns
U0-U31 Data Latency : 61.4ns
U2-U4 Data Latency : 24.8ns
U2-U6 Data Latency : 24.4ns
U2-U8 Data Latency : 27.5ns
U2-U10 Data Latency : 25.5ns
U2-U12 Data Latency : 25.0ns
U2-U14 Data Latency : 26.6ns
U2-U16 Data Latency : 60.2ns
U2-U18 Data Latency : 60.8ns
U2-U20 Data Latency : 61.7ns
U2-U22 Data Latency : 61.0ns
U2-U24 Data Latency : 60.8ns
U2-U26 Data Latency : 60.7ns
U2-U28 Data Latency : 61.5ns
U2-U30 Data Latency : 61.4ns
U2-U1 Data Latency : 24.9ns
U2-U3 Data Latency : 12.6ns
U2-U5 Data Latency : 24.6ns
U2-U7 Data Latency : 24.1ns
U2-U9 Data Latency : 24.9ns
U2-U11 Data Latency : 25.8ns
U2-U13 Data Latency : 24.8ns
U2-U15 Data Latency : 26.8ns
U2-U17 Data Latency : 61.0ns
U2-U19 Data Latency : 60.8ns
U2-U21 Data Latency : 61.6ns
U2-U23 Data Latency : 61.2ns
U2-U25 Data Latency : 61.1ns
U2-U27 Data Latency : 61.4ns
U2-U29 Data Latency : 61.9ns
U2-U31 Data Latency : 61.5ns
U4-U6 Data Latency : 24.9ns
U4-U8 Data Latency : 26.1ns
U4-U10 Data Latency : 25.4ns
U4-U12 Data Latency : 26.5ns
U4-U14 Data Latency : 26.7ns
U4-U16 Data Latency : 62.5ns
U4-U18 Data Latency : 61.9ns
U4-U20 Data Latency : 62.7ns
U4-U22 Data Latency : 61.1ns
U4-U24 Data Latency : 61.6ns
U4-U26 Data Latency : 62.0ns
U4-U28 Data Latency : 62.6ns
U4-U30 Data Latency : 62.5ns
U4-U1 Data Latency : 26.6ns
U4-U3 Data Latency : 24.6ns
U4-U5 Data Latency : 13.1ns
U4-U7 Data Latency : 24.8ns
U4-U9 Data Latency : 25.8ns
U4-U11 Data Latency : 25.3ns
U4-U13 Data Latency : 26.4ns
U4-U15 Data Latency : 26.5ns
U4-U17 Data Latency : 62.0ns
U4-U19 Data Latency : 61.7ns
U4-U21 Data Latency : 62.3ns
U4-U23 Data Latency : 62.1ns
U4-U25 Data Latency : 62.8ns
U4-U27 Data Latency : 62.5ns
U4-U29 Data Latency : 62.2ns
U4-U31 Data Latency : 62.1ns
U6-U8 Data Latency : 25.2ns
U6-U10 Data Latency : 26.8ns
U6-U12 Data Latency : 26.4ns
U6-U14 Data Latency : 27.7ns
U6-U16 Data Latency : 60.7ns
U6-U18 Data Latency : 61.2ns
U6-U20 Data Latency : 62.5ns
U6-U22 Data Latency : 62.1ns
U6-U24 Data Latency : 62.0ns
U6-U26 Data Latency : 62.4ns
U6-U28 Data Latency : 62.6ns
U6-U30 Data Latency : 62.4ns
U6-U1 Data Latency : 24.8ns
U6-U3 Data Latency : 24.3ns
U6-U5 Data Latency : 24.6ns
U6-U7 Data Latency : 12.8ns
U6-U9 Data Latency : 24.9ns
U6-U11 Data Latency : 26.5ns
U6-U13 Data Latency : 26.4ns
U6-U15 Data Latency : 27.6ns
U6-U17 Data Latency : 61.6ns
U6-U19 Data Latency : 61.1ns
U6-U21 Data Latency : 62.5ns
U6-U23 Data Latency : 61.9ns
U6-U25 Data Latency : 61.9ns
U6-U27 Data Latency : 62.3ns
U6-U29 Data Latency : 62.8ns
U6-U31 Data Latency : 62.2ns
U8-U10 Data Latency : 26.5ns
U8-U12 Data Latency : 26.9ns
U8-U14 Data Latency : 27.6ns
U8-U16 Data Latency : 61.4ns
U8-U18 Data Latency : 60.9ns
U8-U20 Data Latency : 61.9ns
U8-U22 Data Latency : 61.5ns
U8-U24 Data Latency : 61.6ns
U8-U26 Data Latency : 61.9ns
U8-U28 Data Latency : 63.2ns
U8-U30 Data Latency : 62.2ns
U8-U1 Data Latency : 26.0ns
U8-U3 Data Latency : 23.9ns
U8-U5 Data Latency : 26.1ns
U8-U7 Data Latency : 25.1ns
U8-U9 Data Latency : 12.5ns
U8-U11 Data Latency : 26.0ns
U8-U13 Data Latency : 26.9ns
U8-U15 Data Latency : 27.7ns
U8-U17 Data Latency : 61.6ns
U8-U19 Data Latency : 60.7ns
U8-U21 Data Latency : 62.4ns
U8-U23 Data Latency : 61.9ns
U8-U25 Data Latency : 61.2ns
U8-U27 Data Latency : 61.4ns
U8-U29 Data Latency : 61.4ns
U8-U31 Data Latency : 62.7ns
U10-U12 Data Latency : 27.4ns
U10-U14 Data Latency : 28.0ns
U10-U16 Data Latency : 61.3ns
U10-U18 Data Latency : 61.0ns
U10-U20 Data Latency : 61.9ns
U10-U22 Data Latency : 63.3ns
U10-U24 Data Latency : 61.7ns
U10-U26 Data Latency : 60.6ns
U10-U28 Data Latency : 62.6ns
U10-U30 Data Latency : 62.0ns
U10-U1 Data Latency : 24.5ns
U10-U3 Data Latency : 26.6ns
U10-U5 Data Latency : 25.2ns
U10-U7 Data Latency : 27.5ns
U10-U9 Data Latency : 26.1ns
U10-U11 Data Latency : 13.0ns
U10-U13 Data Latency : 27.1ns
U10-U15 Data Latency : 27.8ns
U10-U17 Data Latency : 60.8ns
U10-U19 Data Latency : 61.0ns
U10-U21 Data Latency : 62.4ns
U10-U23 Data Latency : 61.8ns
U10-U25 Data Latency : 61.2ns
U10-U27 Data Latency : 62.6ns
U10-U29 Data Latency : 62.7ns
U10-U31 Data Latency : 63.1ns
U12-U14 Data Latency : 28.9ns
U12-U16 Data Latency : 61.2ns
U12-U18 Data Latency : 61.1ns
U12-U20 Data Latency : 61.9ns
U12-U22 Data Latency : 61.6ns
U12-U24 Data Latency : 61.8ns
U12-U26 Data Latency : 62.8ns
U12-U28 Data Latency : 61.6ns
U12-U30 Data Latency : 62.2ns
U12-U1 Data Latency : 25.8ns
U12-U3 Data Latency : 24.9ns
U12-U5 Data Latency : 26.2ns
U12-U7 Data Latency : 26.0ns
U12-U9 Data Latency : 27.6ns
U12-U11 Data Latency : 27.7ns
U12-U13 Data Latency : 12.9ns
U12-U15 Data Latency : 28.6ns
U12-U17 Data Latency : 61.4ns
U12-U19 Data Latency : 61.8ns
U12-U21 Data Latency : 61.4ns
U12-U23 Data Latency : 62.6ns
U12-U25 Data Latency : 62.4ns
U12-U27 Data Latency : 63.0ns
U12-U29 Data Latency : 63.2ns
U12-U31 Data Latency : 62.5ns
U14-U16 Data Latency : 60.4ns
U14-U18 Data Latency : 60.7ns
U14-U20 Data Latency : 60.6ns
U14-U22 Data Latency : 61.7ns
U14-U24 Data Latency : 61.5ns
U14-U26 Data Latency : 61.9ns
U14-U28 Data Latency : 62.8ns
U14-U30 Data Latency : 62.3ns
U14-U1 Data Latency : 25.5ns
U14-U3 Data Latency : 25.4ns
U14-U5 Data Latency : 25.5ns
U14-U7 Data Latency : 26.3ns
U14-U9 Data Latency : 26.2ns
U14-U11 Data Latency : 28.4ns
U14-U13 Data Latency : 28.7ns
U14-U15 Data Latency : 13.0ns
U14-U17 Data Latency : 60.0ns
U14-U19 Data Latency : 60.8ns
U14-U21 Data Latency : 62.3ns
U14-U23 Data Latency : 62.3ns
U14-U25 Data Latency : 63.0ns
U14-U27 Data Latency : 62.3ns
U14-U29 Data Latency : 62.2ns
U14-U31 Data Latency : 64.0ns
U16-U18 Data Latency : 24.8ns
U16-U20 Data Latency : 26.0ns
U16-U22 Data Latency : 24.2ns
U16-U24 Data Latency : 25.2ns
U16-U26 Data Latency : 25.0ns
U16-U28 Data Latency : 26.6ns
U16-U30 Data Latency : 26.4ns
U16-U1 Data Latency : 62.9ns
U16-U3 Data Latency : 61.4ns
U16-U5 Data Latency : 61.8ns
U16-U7 Data Latency : 61.0ns
U16-U9 Data Latency : 59.1ns
U16-U11 Data Latency : 60.1ns
U16-U13 Data Latency : 60.9ns
U16-U15 Data Latency : 60.9ns
U16-U17 Data Latency : 13.2ns
U16-U19 Data Latency : 24.4ns
U16-U21 Data Latency : 25.0ns
U16-U23 Data Latency : 24.9ns
U16-U25 Data Latency : 24.6ns
U16-U27 Data Latency : 25.6ns
U16-U29 Data Latency : 26.2ns
U16-U31 Data Latency : 25.9ns
U18-U20 Data Latency : 25.3ns
U18-U22 Data Latency : 25.5ns
U18-U24 Data Latency : 25.0ns
U18-U26 Data Latency : 27.1ns
U18-U28 Data Latency : 25.7ns
U18-U30 Data Latency : 25.8ns
U18-U1 Data Latency : 61.2ns
U18-U3 Data Latency : 60.0ns
U18-U5 Data Latency : 61.2ns
U18-U7 Data Latency : 61.3ns
U18-U9 Data Latency : 58.6ns
U18-U11 Data Latency : 61.1ns
U18-U13 Data Latency : 60.4ns
U18-U15 Data Latency : 59.7ns
U18-U17 Data Latency : 23.7ns
U18-U19 Data Latency : 12.8ns
U18-U21 Data Latency : 25.3ns
U18-U23 Data Latency : 24.8ns
U18-U25 Data Latency : 25.2ns
U18-U27 Data Latency : 26.0ns
U18-U29 Data Latency : 25.7ns
U18-U31 Data Latency : 27.0ns
U20-U22 Data Latency : 25.6ns
U20-U24 Data Latency : 25.8ns
U20-U26 Data Latency : 25.7ns
U20-U28 Data Latency : 27.3ns
U20-U30 Data Latency : 26.8ns
U20-U1 Data Latency : 59.1ns
U20-U3 Data Latency : 62.3ns
U20-U5 Data Latency : 62.5ns
U20-U7 Data Latency : 60.9ns
U20-U9 Data Latency : 62.2ns
U20-U11 Data Latency : 59.9ns
U20-U13 Data Latency : 62.5ns
U20-U15 Data Latency : 62.4ns
U20-U17 Data Latency : 26.0ns
U20-U19 Data Latency : 24.1ns
U20-U21 Data Latency : 13.4ns
U20-U23 Data Latency : 25.5ns
U20-U25 Data Latency : 26.5ns
U20-U27 Data Latency : 25.8ns
U20-U29 Data Latency : 26.8ns
U20-U31 Data Latency : 27.2ns
U22-U24 Data Latency : 25.9ns
U22-U26 Data Latency : 27.3ns
U22-U28 Data Latency : 26.9ns
U22-U30 Data Latency : 28.2ns
U22-U1 Data Latency : 62.0ns
U22-U3 Data Latency : 62.0ns
U22-U5 Data Latency : 60.4ns
U22-U7 Data Latency : 62.0ns
U22-U9 Data Latency : 61.5ns
U22-U11 Data Latency : 62.6ns
U22-U13 Data Latency : 62.4ns
U22-U15 Data Latency : 61.9ns
U22-U17 Data Latency : 24.3ns
U22-U19 Data Latency : 26.9ns
U22-U21 Data Latency : 25.3ns
U22-U23 Data Latency : 13.4ns
U22-U25 Data Latency : 25.4ns
U22-U27 Data Latency : 26.0ns
U22-U29 Data Latency : 26.6ns
U22-U31 Data Latency : 27.3ns
U24-U26 Data Latency : 27.7ns
U24-U28 Data Latency : 29.3ns
U24-U30 Data Latency : 26.9ns
U24-U1 Data Latency : 59.4ns
U24-U3 Data Latency : 62.3ns
U24-U5 Data Latency : 61.3ns
U24-U7 Data Latency : 60.8ns
U24-U9 Data Latency : 59.8ns
U24-U11 Data Latency : 59.8ns
U24-U13 Data Latency : 61.0ns
U24-U15 Data Latency : 62.2ns
U24-U17 Data Latency : 26.6ns
U24-U19 Data Latency : 25.2ns
U24-U21 Data Latency : 26.3ns
U24-U23 Data Latency : 25.7ns
U24-U25 Data Latency : 13.1ns
U24-U27 Data Latency : 27.0ns
U24-U29 Data Latency : 27.7ns
U24-U31 Data Latency : 28.5ns
U26-U28 Data Latency : 28.5ns
U26-U30 Data Latency : 29.4ns
U26-U1 Data Latency : 62.5ns
U26-U3 Data Latency : 62.2ns
U26-U5 Data Latency : 61.7ns
U26-U7 Data Latency : 61.7ns
U26-U9 Data Latency : 61.9ns
U26-U11 Data Latency : 61.3ns
U26-U13 Data Latency : 62.9ns
U26-U15 Data Latency : 62.7ns
U26-U17 Data Latency : 25.1ns
U26-U19 Data Latency : 25.8ns
U26-U21 Data Latency : 25.6ns
U26-U23 Data Latency : 27.6ns
U26-U25 Data Latency : 27.5ns
U26-U27 Data Latency : 13.4ns
U26-U29 Data Latency : 28.1ns
U26-U31 Data Latency : 27.5ns
U28-U30 Data Latency : 29.8ns
U28-U1 Data Latency : 62.4ns
U28-U3 Data Latency : 61.3ns
U28-U5 Data Latency : 62.4ns
U28-U7 Data Latency : 62.2ns
U28-U9 Data Latency : 62.2ns
U28-U11 Data Latency : 63.0ns
U28-U13 Data Latency : 63.7ns
U28-U15 Data Latency : 62.2ns
U28-U17 Data Latency : 26.1ns
U28-U19 Data Latency : 26.0ns
U28-U21 Data Latency : 28.4ns
U28-U23 Data Latency : 27.3ns
U28-U25 Data Latency : 26.7ns
U28-U27 Data Latency : 26.7ns
U28-U29 Data Latency : 13.4ns
U28-U31 Data Latency : 29.7ns
U30-U1 Data Latency : 60.6ns
U30-U3 Data Latency : 61.8ns
U30-U5 Data Latency : 62.4ns
U30-U7 Data Latency : 62.3ns
U30-U9 Data Latency : 61.5ns
U30-U11 Data Latency : 61.8ns
U30-U13 Data Latency : 63.7ns
U30-U15 Data Latency : 62.6ns
U30-U17 Data Latency : 26.1ns
U30-U19 Data Latency : 27.1ns
U30-U21 Data Latency : 26.8ns
U30-U23 Data Latency : 27.4ns
U30-U25 Data Latency : 28.1ns
U30-U27 Data Latency : 29.5ns
U30-U29 Data Latency : 29.2ns
U30-U31 Data Latency : 13.4ns
U1-U3 Data Latency : 23.1ns
U1-U5 Data Latency : 25.0ns
U1-U7 Data Latency : 24.8ns
U1-U9 Data Latency : 25.8ns
U1-U11 Data Latency : 25.1ns
U1-U13 Data Latency : 24.5ns
U1-U15 Data Latency : 26.0ns
U1-U17 Data Latency : 60.8ns
U1-U19 Data Latency : 61.4ns
U1-U21 Data Latency : 62.2ns
U1-U23 Data Latency : 61.5ns
U1-U25 Data Latency : 58.9ns
U1-U27 Data Latency : 62.0ns
U1-U29 Data Latency : 61.0ns
U1-U31 Data Latency : 62.5ns
U3-U5 Data Latency : 24.1ns
U3-U7 Data Latency : 26.1ns
U3-U9 Data Latency : 24.0ns
U3-U11 Data Latency : 26.4ns
U3-U13 Data Latency : 24.8ns
U3-U15 Data Latency : 25.8ns
U3-U17 Data Latency : 62.5ns
U3-U19 Data Latency : 57.2ns
U3-U21 Data Latency : 60.1ns
U3-U23 Data Latency : 62.3ns
U3-U25 Data Latency : 60.5ns
U3-U27 Data Latency : 61.8ns
U3-U29 Data Latency : 61.2ns
U3-U31 Data Latency : 62.3ns
U5-U7 Data Latency : 24.3ns
U5-U9 Data Latency : 27.1ns
U5-U11 Data Latency : 25.3ns
U5-U13 Data Latency : 27.7ns
U5-U15 Data Latency : 25.8ns
U5-U17 Data Latency : 58.9ns
U5-U19 Data Latency : 59.9ns
U5-U21 Data Latency : 62.8ns
U5-U23 Data Latency : 60.3ns
U5-U25 Data Latency : 60.0ns
U5-U27 Data Latency : 61.7ns
U5-U29 Data Latency : 61.7ns
U5-U31 Data Latency : 62.3ns
U7-U9 Data Latency : 25.0ns
U7-U11 Data Latency : 27.1ns
U7-U13 Data Latency : 26.3ns
U7-U15 Data Latency : 28.0ns
U7-U17 Data Latency : 59.8ns
U7-U19 Data Latency : 61.1ns
U7-U21 Data Latency : 60.5ns
U7-U23 Data Latency : 62.2ns
U7-U25 Data Latency : 61.9ns
U7-U27 Data Latency : 63.4ns
U7-U29 Data Latency : 61.3ns
U7-U31 Data Latency : 62.0ns
U9-U11 Data Latency : 26.1ns
U9-U13 Data Latency : 26.0ns
U9-U15 Data Latency : 26.3ns
U9-U17 Data Latency : 61.2ns
U9-U19 Data Latency : 60.8ns
U9-U21 Data Latency : 61.5ns
U9-U23 Data Latency : 62.9ns
U9-U25 Data Latency : 62.1ns
U9-U27 Data Latency : 62.7ns
U9-U29 Data Latency : 63.3ns
U9-U31 Data Latency : 60.4ns
U11-U13 Data Latency : 28.5ns
U11-U15 Data Latency : 28.9ns
U11-U17 Data Latency : 60.7ns
U11-U19 Data Latency : 62.1ns
U11-U21 Data Latency : 63.7ns
U11-U23 Data Latency : 60.4ns
U11-U25 Data Latency : 61.4ns
U11-U27 Data Latency : 62.3ns
U11-U29 Data Latency : 62.7ns
U11-U31 Data Latency : 63.5ns
U13-U15 Data Latency : 27.0ns
U13-U17 Data Latency : 61.0ns
U13-U19 Data Latency : 63.4ns
U13-U21 Data Latency : 62.2ns
U13-U23 Data Latency : 62.0ns
U13-U25 Data Latency : 62.1ns
U13-U27 Data Latency : 62.0ns
U13-U29 Data Latency : 62.1ns
U13-U31 Data Latency : 63.0ns
U15-U17 Data Latency : 62.1ns
U15-U19 Data Latency : 61.3ns
U15-U21 Data Latency : 63.2ns
U15-U23 Data Latency : 63.2ns
U15-U25 Data Latency : 62.2ns
U15-U27 Data Latency : 61.7ns
U15-U29 Data Latency : 62.8ns
U15-U31 Data Latency : 61.9ns
U17-U19 Data Latency : 23.9ns
U17-U21 Data Latency : 25.6ns
U17-U23 Data Latency : 24.8ns
U17-U25 Data Latency : 26.3ns
U17-U27 Data Latency : 25.4ns
U17-U29 Data Latency : 26.8ns
U17-U31 Data Latency : 25.7ns
U19-U21 Data Latency : 25.9ns
U19-U23 Data Latency : 25.5ns
U19-U25 Data Latency : 24.9ns
U19-U27 Data Latency : 29.2ns
U19-U29 Data Latency : 25.8ns
U19-U31 Data Latency : 26.4ns
U21-U23 Data Latency : 25.0ns
U21-U25 Data Latency : 27.5ns
U21-U27 Data Latency : 25.8ns
U21-U29 Data Latency : 27.3ns
U21-U31 Data Latency : 27.2ns
U23-U25 Data Latency : 25.8ns
U23-U27 Data Latency : 27.6ns
U23-U29 Data Latency : 26.6ns
U23-U31 Data Latency : 27.5ns
U25-U27 Data Latency : 27.0ns
U25-U29 Data Latency : 27.0ns
U25-U31 Data Latency : 28.6ns
U27-U29 Data Latency : 28.9ns
U27-U31 Data Latency : 27.6ns
U29-U31 Data Latency : 29.8ns
1x 64bytes Blocks Bandwidth : 25.15GB/s
4x 64bytes Blocks Bandwidth : 22.74GB/s
4x 256bytes Blocks Bandwidth : 96.64GB/s
4x 1024bytes Blocks Bandwidth : 290GB/s
4x 4kB Blocks Bandwidth : 440.15GB/s
16x 4kB Blocks Bandwidth : 588.34GB/s
4x 64kB Blocks Bandwidth : 809.62GB/s
16x 64kB Blocks Bandwidth : 576.7GB/s
8x 256kB Blocks Bandwidth : 572.08GB/s
4x 1024kB Blocks Bandwidth : 581.87GB/s
8x 1024kB Blocks Bandwidth : 40.93GB/s
8x 4MB Blocks Bandwidth : 19.82GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (16C 32T 3.4GHz, 16x 512kB L2, 2x 32MB L3)
Microcode
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
Buffering Used : No
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
Speed : 3.4GHz
Cores per Processor : 16 Unit(s)
Cores per Compute Unit : 2 Unit(s)
Front Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)


----------



## wuttman

I find prime avx large together with some gpu load to be best at catching IF related whea's (they pop in hwinfo). Running occt ram test previously showed nothing.


----------



## Blameless

CPU mining Monero with XMRig allowed me to diagnose and address corrected bus/interconnect errors (on my 3900X at 1866MHz fabric clock) that were showing up in the event logs as warnings, rather than errors. Was seeing them extremely intermittently with other tests but could reliably induce one about every 20-60 hours of XMRig. A bump to SoC and VDDG voltage solved them entirely and haven't seen so much as a single warning/correctable error in months.


----------



## RonLazer

I would actually advise against buying the Unify-X for memory overclocking. Mine died a few days ago during a BIOS flash, and is totally bricked. I'm refunding it and will use my Dark Hero as my overclocking experiment board, with a B550 Vision DP as my daily board.

If you check HWBot - very few of the top Ryzen results are with the Unify-X. Top Ryzen Geekbench 3 result is on the Dark Hero, top Ryzen frequency validation is on the B550-I Strix, the top SuperPi 32M result is on the MSI MPG B550I...

Despite being nominally designed as an XOC board - it doesn't have a Safe Boot button, or a Retry button, or a dual-BIOS switch, or really anything special except a solid memory topology and 2-dimm slots. The VRM design is good, but even the newer revisions are extremely susceptible to coil whine, they already had to issue 2 revisions due to cheaping out on inductors, but even after swapping their suppliers most boards still have some coil whine - which doesn't fill me with confidence over how much actual testing went into the VRM design. And my issue with the BIOS chip failing is far from unique, and doesn't even seem to be a Unify-X specific issue, it's something across all MSI boards if you google it.

Even if the hardware was better - you need a modified BIOS just to access the AMD CBS menu, and even the fully unlocked BIOS don't offer anywhere near the extra settings Asus include in their BIOS. Here is a list of the issues I found:

1. CPU VDDP seems to be entirely impossible to control, and even unlocked BIOS don't fix that.
2. DRAM voltage is always exactly 0.1V higher than you set, and this isn't even a sensor read error because MSI Command Center will show +0.1V over what you typed in - which means the BIOS deliberately adds the extra, possibly to make it seem better at memory overclocking than it is? Oh and the stock BIOS limits you to 2V on DRAM voltage, which is fine for daily but super-low for an XOC board. Buildzoid mentioned that the memory OC behavior actually got worse over 2V, so it might be a memory VRM problem they masked with a BIOS limit?
3. PLL voltage (or 1P8 as MSI insist on referring to it as) is overvolted by 0.4V relative to whatever you set - but then it caps out at 2.1V on the stock BIOS. Modified BIOS allow it to go up to 3V, so again - why was this restriction added on an XOC board?
4. PBO settings are reset between CMOS clears.
5. VTTDDR control is missing on the stock BIOS, and while the unlocked BIOS does have it, it doesn't actually change in the Windows sensor readout, and while you can cause a boot failure with some truly stupid VTTDDR settings, it still boots with settings I know would fail on other boards, so I have no idea what it's actually doing with VTT and to be honest, I can't be bothered messing around with a multimeter to find out. 
6. No favorites menu, and since half the advanced settings are only accessible via the convoluted AMD CBS menu (if you have the aforementioned unlocked BIOS), which is ALSO not indexed in the search feature - you will be spending a lot of time digging in menus. 
7. Memory overclocking recovery is TERRIBLE, I had a single successful recovery the entire time I used it, whereas you have to really mess up hard on the Dark Hero to require a CMOS clear. This isn't a Unify-X issue, my other MSI board has the same issue.

If you want 1DPC at any cost then Crosshair Impact is better (shorter trace lengths due to DTX form factor too), but since the Unify-X has had its cost slashed to £200 in the UK and the Impact is £350 - I suppose its the cheapest high layer-count 1DPC board - so long as you don't plan on flashing the BIOS more than a half-dozen times or you risk bricking it. That said I'm not really convinced 2DPC boards are even that bad given there isn't a single B550/X570 board with T-topology, and Daisy-Chain (despite how much unreasonable hatred it gets) is a really good topology for running 2-dimms on a 4-slot board. The extra space between dimms is also great for air-cooling.

So unless you need the best possible board for doing high-frequency validations on AMD specifically, but you don't need anything beyond basic voltage controls, don't care about OC recovery, AND need to save £150 over the Crosshair Impact - I can't see why you'd buy the Unify-X currently?


----------



## RonLazer

@PJVol @Veii I see people keep referencing 6/3/3 with specific CAD Bus setups and tCKE, but having delved deep into the jedec spec and manufacturer timing sheets, it's very unclear to me why for 2xSR setups you would even want to use dynamic-ODT? Using 0/0/X with X=5 as default allows you to basically ignore tCKE since its only usage would be during self-refresh, and I'm not clear on why adjusting the CKE transition window would be desirable for refresh operations?

Even if you want to exploit dynamic-ODT, there's zero reason to assume that the same setting could be applicable to all possible channel/rank configurations. That's why the defaults are 0/0/5 for 2xSR, 7/3/1 for 4xSR, and 0/3/1 for 2xDR on daisy-chain topology boards.

As for setup times, if you're going over 31 on any of them then aren't you functionally running a slower command rate, since you end up needing to include additive latency on ACT to ensure the memory controller is able to setup the relevant pins before the next CK_t/CK_s crossover. I'm not 100% clear on how setup times operate to be honest so if anyone is able to offer clarity then I'd love to learn more.

I've also seen some discussion about what suitable tRDWR timings are, so here is a mini calculator for the actual minimum (no guarantee of stability): tRDWR calculator

Going below the "Fast" timing will fail to POST under any circumstances and probably require a CMOS clear. I've imposed a *Ceiling[tCL/2]* minimum since in my experience going below this causes problems under high-bandwidth loads (probably saturating the memory controller command register limit?)


----------



## ManniX-ITA

@RonLazer 
Thanks for the interesting feedback, appreciated.



RonLazer said:


> I would actually advise against buying the Unify-X for memory overclocking. Mine died a few days ago during a BIOS flash, and is totally bricked. I'm refunding it and will use my Dark Hero as my overclocking experiment board, with a B550 Vision DP as my daily board.


I still like it, despite the weaknesses. 
Had as well some troubles with the BIOS, M-Flash would not start.
Indeed flash problems seems to be a common issue with MSI boards...
But it's also the first time that I hear someone praising the Dark Hero.
So far I've only seen not enthusiastic comments, especially about memory OC.



RonLazer said:


> If you check HWBot - very few of the top Ryzen results are with the Unify-X. Top Ryzen Geekbench 3 result is on the Dark Hero, top Ryzen frequency validation is on the B550-I Strix, the top SuperPi 32M result is on the MSI MPG B550I...


For sure the DH is more popular. Plus the coil whine issue is pushing away a lot of people.
I'm not sure it's a good metric but indeed it's something to keep into consideration.



RonLazer said:


> Despite being nominally designed as an XOC board - it doesn't have a Safe Boot button, or a Retry button, or a dual-BIOS switch, or really anything special except a solid memory topology and 2-dimm slots. The VRM design is good, but even the newer revisions are extremely susceptible to coil whine, they already had to issue 2 revisions due to cheaping out on inductors, but even after swapping their suppliers most boards still have some coil whine - which doesn't fill me with confidence over how much actual testing went into the VRM design. And my issue with the BIOS chip failing is far from unique, and doesn't even seem to be a Unify-X specific issue, it's something across all MSI boards if you google it.


I agree, the features set for a board which should be oriented to XOC is disappointing.
They did way too many sacrifices to reduce the costs. It was much better a bit more beefy and expensive.
I wouldn't miss that much the Dual BIOS if it wasn't that latest BIOS versions when you rollback don't recognize the saved profiles... ugly.
But a Safe/Retry button was a must considering it needs constantly a clear CMOS.
The VRM seems solid to me; the board AFAIK has only one revision, 2.1.
Maybe an earlier one only available in China?



RonLazer said:


> Even if the hardware was better - you need a modified BIOS just to access the AMD CBS menu, and even the fully unlocked BIOS don't offer anywhere near the extra settings Asus include in their BIOS


Yes, lots of missing options and XOC BIOS only on request, maybe. Should be released public by default.



RonLazer said:


> 1. CPU VDDP seems to be entirely impossible to control, and even unlocked BIOS don't fix that.


MSI engineers.. how to put it? They either are dumb or play dumb.
The CPU VDDP in the BIOS is just VDDP; but for the monolithic CPU, the APU.
Seems there's no way to have them understand what is CPU VDDP.



RonLazer said:


> 2. DRAM voltage is always exactly 0.1V higher than you set, and this isn't even a sensor read error because MSI Command Center will show +0.1V over what you typed in - which means the BIOS deliberately adds the extra, possibly to make it seem better at memory overclocking than it is? Oh and the stock BIOS limits you to 2V on DRAM voltage, which is fine for daily but super-low for an XOC board. Buildzoid mentioned that the memory OC behavior actually got worse over 2V, so it might be a memory VRM problem they masked with a BIOS limit?


GigaByte does the same; it's actually 0.01V.
Not sure why would be a problem if you know it.
Never went above 2V...



RonLazer said:


> 3. PLL voltage (or 1P8 as MSI insist on referring to it as) is overvolted by 0.4V relative to whatever you set - but then it caps out at 2.1V on the stock BIOS. Modified BIOS allow it to go up to 3V, so again - why was this restriction added on an XOC board?


Didn't notice the XOC allows up to 3V, interesting.
I think on A22 BIOS is limited to 1.95V.
Maybe there's some randomness in these choices...



RonLazer said:


> 4. PBO settings are reset between CMOS clears.


I had this in the first BIOS releases.
Then it got worse, much worse.
It's my biggest complaint and makes testing any setting that could trigger the, very frequent, need to clear CMOS a total nightmare.
I have to touch, +/-, almost every setting when I restore a profile.
Plus the Alt+Fx which doesn't work and needs another clear CMOS.



RonLazer said:


> 5. VTTDDR control is missing on the stock BIOS, and while the unlocked BIOS does have it, it doesn't actually change in the Windows sensor readout, and while you can cause a boot failure with some truly stupid VTTDDR settings, it still boots with settings I know would fail on other boards, so I have no idea what it's actually doing with VTT and to be honest, I can't be bothered messing around with a multimeter to find out.


VTT is present in the stock BIOS and works properly.
There's no sensor to read it in Windows that I know of.
In theory Zentimings should read it from SMU but it doesn't.
Same as with GigaByte; I didn't notice any different behavior. 



RonLazer said:


> 6. No favorites menu, and since half the advanced settings are only accessible via the convoluted AMD CBS menu (if you have the aforementioned unlocked BIOS), which is ALSO not indexed in the search feature - you will be spending a lot of time digging in menus.


There is Favorites (F2/F3).
It's quite basic and ugly... 
But honestly I never use it.
The layout is quite good and almost all the options are quickly accessible.
I could set favorites shortcut to the CBS menu in Advanced which was the only one less accessible.
Search function I've never used it, have to check it out 



RonLazer said:


> 7. Memory overclocking recovery is TERRIBLE, I had a single successful recovery the entire time I used it, whereas you have to really mess up hard on the Dark Hero to require a CMOS clear. This isn't a Unify-X issue, my other MSI board has the same issue.


Gigabyte is even worse.
Indeed I have an ASUS B550 TUF Gaming and is way better.
That the Dark Hero doesn't need so many clear CMOS is really tempting...



RonLazer said:


> So unless you need the best possible board for doing high-frequency validations on AMD specifically, but you don't need anything beyond basic voltage controls, don't care about OC recovery, AND need to save £150 over the Crosshair Impact - I can't see why you'd buy the Unify-X currently?


As you said there are no alternatives for an ATX board.
If you don't need/want to do crazy things, memory OC is very easy with 2 DIMMs only and CPU OC is decent.
There's for sure a lot of room for improvement but I'm, still, not considering to replace it.


----------



## PJVol

RonLazer said:


> DRAM voltage is always exactly 0.1V higher


I have mine increased ~50mv as well. Just thought, what might be the reason for that. The only answer i have, vendors raised it to run safe against value stored in xmp profile when one try to apply it at boot.


----------



## RonLazer

ManniX-ITA said:


> @RonLazer
> Thanks for the interesting feedback, appreciated.
> 
> 
> 
> I still like it, despite the weaknesses.
> Had as well some troubles with the BIOS, M-Flash would not start.
> Indeed flash problems seems to be a common issue with MSI boards...
> But it's also the first time that I hear someone praising the Dark Hero.
> So far I've only seen not enthusiastic comments, especially about memory OC.
> 
> 
> 
> For sure the DH is more popular. Plus the coil whine issue is pushing away a lot of people.
> I'm not sure it's a good metric but indeed it's something to keep into consideration.
> 
> 
> 
> I agree, the features set for a board which should be oriented to XOC is disappointing.
> They did way too many sacrifices to reduce the costs. It was much better a bit more beefy and expensive.
> I wouldn't miss that much the Dual BIOS if it wasn't that latest BIOS versions when you rollback don't recognize the saved profiles... ugly.
> But a Safe/Retry button was a must considering it needs constantly a clear CMOS.
> The VRM seems solid to me; the board AFAIK has only one revision, 2.1.
> Maybe an earlier one only available in China?
> 
> 
> 
> Yes, lots of missing options and XOC BIOS only on request, maybe. Should be released public by default.
> 
> 
> 
> MSI engineers.. how to put it? They either are dumb or play dumb.
> The CPU VDDP in the BIOS is just VDDP; but for the monolithic CPU, the APU.
> Seems there's no way to have them understand what is CPU VDDP.
> 
> 
> 
> GigaByte does the same; it's actually 0.01V.
> Not sure why would be a problem if you know it.
> Never went above 2V...
> 
> 
> 
> Didn't notice the XOC allows up to 3V, interesting.
> I think on A22 BIOS is limited to 1.95V.
> Maybe there's some randomness in these choices...
> 
> 
> 
> I had this in the first BIOS releases.
> Then it got worse, much worse.
> It's my biggest complaint and makes testing any setting that could trigger the, very frequent, need to clear CMOS a total nightmare.
> I have to touch, +/-, almost every setting when I restore a profile.
> Plus the Alt+Fx which doesn't work and needs another clear CMOS.
> 
> 
> 
> VTT is present in the stock BIOS and works properly.
> There's no sensor to read it in Windows that I know of.
> In theory Zentimings should read it from SMU but it doesn't.
> Same as with GigaByte; I didn't notice any different behavior.
> 
> 
> 
> There is Favorites (F2/F3).
> It's quite basic and ugly...
> But honestly I never use it.
> The layout is quite good and almost all the options are quickly accessible.
> I could set favorites shortcut to the CBS menu in Advanced which was the only one less accessible.
> Search function I've never used it, have to check it out
> 
> 
> 
> Gigabyte is even worse.
> Indeed I have an ASUS B550 TUF Gaming and is way better.
> That the Dark Hero doesn't need so many clear CMOS is really tempting...
> 
> 
> 
> As you said there are no alternatives for an ATX board.
> If you don't need/want to do crazy things, memory OC is very easy with 2 DIMMs only and CPU OC is decent.
> There's for sure a lot of room for improvement but I'm, still, not considering to replace it.


On MSI and CPU VDDP:

I checked the BIOS file in AMIBCP - CPU VDDP is already enabled in the stock BIOS, it just doesn't show up. Someone (I think it was in this thread even) said that MSI don't actually have any hardware-level ability to control CPU VDDP, and honestly I wouldn't be surprised if that was yet another corner they cut.

On the Dark Hero:

I have no idea who said it was bad for memory OC but I am deeply skeptical. It's the board used in many many HWBot world records on Ryzen, it's the ONLY board I'm aware of (possibly also the Strix B550-XE) that has sensible default VDDG values, and its easily the best board I've tried - and mostly on-par feature-wise with anything more expensive like the Godlike. The Unify-X (and previous MSI boards I tested) have some really weird fallback settings where if a memory config doesn't train properly then it just yeets ProcODT to 60ohm and CLDO_VDDP to 1.1V/1.2V - which works sometimes, but the Dark Hero just resets and tries again with sensible settings and that works most of the time. 

I think ultimately this is just a case-study in why making an XOC board isn't as simple as attaching a powerful VRM to an 8-layer board with 1DPC and calling it a day. Asus have in-house professional overclockers who extensively test their high-end and point out issues before release, and it shows.


----------



## lmfodor

Hi, thank you, your comments , it´s very useful since I was about to change a ChrosHair Hero VIII Wifi for a Unify-x. The B550 XE I discarded it simply because it doesnt have a Clear CMOS button, at this point there are things that were left in the 90s. The retry and safe buttons dont usually work very well. At Intel it sure does. I´d to change this CH8 Wifi but I'm going to see how much I can achieve.


----------



## ManniX-ITA

RonLazer said:


> On MSI and CPU VDDP:
> 
> I checked the BIOS file in AMIBCP - CPU VDDP is already enabled in the stock BIOS, it just doesn't show up. Someone (I think it was in this thread even) said that MSI don't actually have any hardware-level ability to control CPU VDDP, and honestly I wouldn't be surprised if that was yet another corner they cut.


That CPU VDDP is the CLDO VDDP for APU.
It was actually MSI support that said this thing about not having hardware level support.
They don't have a clue, probably much less than the MSI engineer from Taiwan that told them something they didn't understand 



RonLazer said:


> I have no idea who said it was bad for memory OC but I am deeply skeptical. It's the board used in many many HWBot world records on Ryzen, it's the ONLY board I'm aware of (possibly also the Strix B550-XE) that has sensible default VDDG values, and its easily the best board I've tried - and mostly on-par feature-wise with anything more expensive like the Godlike. The Unify-X (and previous MSI boards I tested) have some really weird fallback settings where if a memory config doesn't train properly then it just yeets ProcODT to 60ohm and CLDO_VDDP to 1.1V/1.2V - which works sometimes, but the Dark Hero just resets and tries again with sensible settings and that works most of the time.


I think it was Veii that mentioned problems with the Dark Hero.
And I've read a lot of complaints; maybe till some time ago there were BIOS maturity issues?
I remember someone fed up cause there weren't any reliable release or beta BIOS and he was not alone.



RonLazer said:


> I think ultimately this is just a case-study in why making an XOC board isn't as simple as attaching a powerful VRM to an 8-layer board with 1DPC and calling it a day. Asus have in-house professional overclockers who extensively test their high-end and point out issues before release, and it shows.


I don't have such a high esteem of ASUS; they did more or less the same BS than other manufacturers.
They are doing a bit better now but till last year almost all their boards were problematic on something.
Bad designs, cheap and defective components, everything.
I really don't like the BIOS layout and a lot of the stupid "custom options" a la DOCP or even less the virus software suites.
But considering how miserable are all the others, it doesn't take much to lead the pack.
And of course the ridiculous ASUS price premium.
But I don't want to have prejudices.


----------



## RonLazer

I have a Gigabyte B550 Vision DP on the way, so I'm curious to find out what particular way Gigabyte **** up their motherboards. Sadly no CMOS clear button (yes this is the core issue with the B550-XE as well @lmfodor) but I have a stash of 2-pin jumpers with bare wire that I run to JBAT1 and hook up my ludicrously extra toggle switch screwed onto my testbench:


----------



## lmfodor

ManniX-ITA said:


> Should have finished messing with the 1T profile, testing with real world usage now.
> Despite passing 1h:30m of TM5, Chrome was crashing with tRFC 238. Had to go back to tRFC 252.
> 
> Even at 1.52V the temperatures did not change much; now I'm at 1.53V, reach 56.1c tops 56.6c.
> Running at 1T it gets really hot and very quickly compared to 2T.
> 
> No way to lower tRRD below 4/6 or tWTR 4/10, crashing at test 0 or 15.
> Maybe with higher VDIMM, I'll have to see with water cooling.
> 
> Latency is down to 54.4ns which is lowest I can do with dual CCD.
> Bandwidth is quite good, top notch for 3800MHz, over 59GB/s for R/W and 57GB/s for Copy.
> Can't complain but not much more than could be achieved with 2T with lower temps.
> 
> View attachment 2488507
> View attachment 2488506


Wow, impressive numbers! I just noticed that we both share almost the same timings with the exception of CAD BUS Setup and that you could go to much lower with ProcODT. I can go up to 36 and below have no POST.
Again, having you a pretty similar memory kit, I mean, should be the same BDIE, and Dual Rank, I can´t believe how yoy can enable 1T GDM disabled. Amaizing.
Regarding Latency, I didn´t know that 54.4ns would be the lowest value for 2 CCD, what is that, I see a lot of members with lowest lacenty, all of them have one CCD?




> Spoiler: Voltages
> 
> 
> 
> 
> View attachment 2488509
> 
> 
> 
> 
> Well, 1.53 with RTT Park 1 would not be the best option, why not 3??
> 
> Then a couples of tips for MSI boards
> 
> 
> 
> Spoiler: How to run L3 full speed, thanks Veii. Caution it can introduce instability
> 
> 
> 
> 
> View attachment 2488510


I never set that value, I see a cTDC option, but not that one. 1000W? Maybe we could try with 300/400. In fact my PCO is set to 300/235/400, reaching the fuse limit of 200A on EDC.


> Spoiler: How to abuse telemetry to bump single core boosting
> 
> 
> 
> 
> View attachment 2488512
> 
> 
> 
> I never see that, so if I enable telemetry and put those settings would improve SC performance?


----------



## RonLazer

ManniX-ITA said:


> I think it was Veii that mentioned problems with the Dark Hero.
> And I've read a lot of complaints; maybe till some time ago there were BIOS maturity issues?
> I remember someone fed up cause there weren't any reliable release or beta BIOS and he was not alone.
> 
> I don't have such a high esteem of ASUS; they did more or less the same BS than other manufacturers.
> They are doing a bit better now but till last year almost all their boards were problematic on something.
> Bad designs, cheap and defective components, everything.
> I really don't like the BIOS layout and a lot of the stupid "custom options" a la DOCP or even less the virus software suites.


Yes, the BIOS default of installing the Asus Update Service is infuriating, but you don't actually have to install any of their software, and they didn't lock their RGB or fan control behind any hardware encryption, so you can just use free open-source, low-bloat, 3rd party softwares like OpenRGB or FanControl and get full control over your board.


----------



## RonLazer

lmfodor said:


> Wow, impressive numbers! I just noticed that we both share almost the same timings with the exception of CAD BUS Setup and that you could go to much lower with ProcODT. I can go up to 36 and below have no POST.
> Again, having you a pretty similar memory kit, I mean, should be the same BDIE, and Dual Rank, I can´t believe how yoy can enable 1T GDM disabled. Amaizing.
> Regarding Latency, I didn´t know that 54.4ns would be the lowest value for 2 CCD, what is that, I see a lot of members with lowest lacenty, all of them have one CCD?
> 
> 
> 
> I never set that value, I see a cTDC option, but not that one. 1000W? Maybe we could try with 300/400. In fact my PCO is set to 300/235/400, reaching the fuse limit of 200A on EDC.


Not gonna make any definitive claims (every dimm is different) but I suspect the following is sub-optimal:

ProcODT too low for DR dimms, I suspect you'll need 36.9ohm minimum. Remember this is an impedance setting, going lower isn't better, you just want the output impedance to match the transmission line impedance. 
SCLs should be 4, you have CAS strobes synchronized on the rising edge during training, then you expect them to flip during operation and still align?
Just run tRCDs at 15/15 - who cares about write latency anyway
tWR/tRTP at 16/8 very likely won't make a noticeable different to stability but will give you a ton more breathing space during high bandwidth loads
tRFC is too low unless you have hella cooling
Raise CKE drive strength to 24ohm
Raise Chip select drive strength to 24ohm, maybe even 30ohm?
SOC voltage is very high from my testing, I don't think you'd need more than 1.15V SET - but this is admittedly more of a silicon lottery than usual.


----------



## lmfodor

Hi @ManniX-ITA , this is the first time I use SISandra. Where did you find the options of Bench Results? I´m attaching the SiSandra complete report. How am I supposed to interpret all these values, I mean the ones that are related to the IC, which ones should it read and what parameters should it have?

Thanks!


----------



## RonLazer

Oh and since people were chatting about PLL 1.8V voltage (or whatever your motherboard calls it: 1P8, CPU VDD, CPU VTT whatever) I thought I'd share my data:









To be clear - this is not Aida64 latency, it's a custom 256mb memory load injected at idle with random access patterns to exclude the influence of the L1/L2 prefetchers. However as far as I can tell the Aida64 latency will follow very similar patterns.


----------



## lmfodor

RonLazer said:


> Not gonna make any definitive claims (every dimm is different) but I suspect the following is sub-optimal:
> 
> ProcODT too low for DR dimms, I suspect you'll need 36.9ohm minimum. Remember this is an impedance setting, going lower isn't better, you just want the output impedance to match the transmission line impedance.
> SCLs should be 4, you have CAS strobes synchronized on the rising edge during training, then you expect them to flip during operation and still align?
> Just run tRCDs at 15/15 - who cares about write latency anyway
> tWR/tRTP at 16/8 very likely won't make a noticeable different to stability but will give you a ton more breathing space during high bandwidth loads
> tRFC is too low unless you have hella cooling
> Raise CKE drive strength to 24ohm
> Raise Chip select drive strength to 24ohm, maybe even 30ohm?
> SOC voltage is very high from my testing, I don't think you'd need more than 1.15V SET - but this is admittedly more of a silicon lottery than usual.


Hi @RonLanzer, thanks for your guidance. Indeed Im still expiriences some errors in TM5. My goal is to try 14 flat, but I know if hard to get. Meanwhile I´m trying to stabilize tRCDRD 15. Ok, so

I will rise ProctODT to 40 or 43. I know there is a correlation between voltage and higher ProcODT, but the RRT also plays here, I know that for DR a 6/3/3 would be fine or RTTNum Disabled, WR, 3 and Park 1 but witha limit of 1.52 for 240ohms or would kill some dies.. and ProcODT will improve singal integrity, but it shold be in line with lower vSOC, low vDDP.. and aldo ClkDvr high hellps to lower procODT.. that´s whay I am using a lower one.
I will try again 15-15 for tRCDs..
and is good the advise of 16/8.. I noticed that a lot of member have this both setting without any rule..
Regarding tRFCs, yes, now Im running a TM5 with a very lower tems, I have an active cooling.. working very well











Raise CKE drive strength to 24ohm
Raise Chip select drive strength to 24ohm, maybe even 30ohm?
What is this value? It should be 40-24-30-24? I see old @Veii post where he recomend an structure of xx-20-20-24, when XX could be 40 or 60.. but with care about the voltages. Then, what I did is to set 40-20-20-20 and the setup for 3800 3-3-15, is that right?
SOC voltage is very high from my testing, I don't think you'd need more than 1.15V SET - but this is admittedly more of a silicon lottery than usual.
Yes, I think so, I really don´t know how to calculate it, I started with 1.1. and it was fine. The a tight some subs and I rise a bit, 1.12, then 1.14 as you can see in the current stress test that I´m running right now.
Besides, I have some other questions:

Even having reading a lot of Veiis post of past years, I should put all in a word to make some bible of OC.. I´m still confusing how we play the tRRDs, tWTRs and the tRDWR and tWRD. I know the rules, but what I don´t know if If a loose for instance tRRD_L and the +1 or +2, should have an impact on tRDWR or tWRRD, or this are more linked with the SCL? I need to understand how we play all togheter to know what value to loose and wha to tight.
What determines the read / write speed? I mean, I have the false perception that if I loose tRRDs and tWTRs, the R/W Speed will increase.
And maybe the most important question is when I tried to lower the tRCDRD to 14, at any combination, I always have a bunch of errors 6 in TM5, then 12, 2, 0,.. and son on.. So, I read I have to loose tRRDs and tWRTs, and also increase +1 or +2 SCL, but what happen with the voltage, should I increase? VDIMM or VSOC? Its a play of try and try untile the error 6 goes away? that´s it´s really frustrastring, becuase there are some many variables that I don´t know how to twak in an ordererd way.
At last, there are some many options in BIOS that I don´t know if has some negative influence in memory OC, for instance, I have a very tight PBO Curve.. not all core, but per core.. would it conflict with mem OC? should I set for instance all core -15, PBO Limits Motherboard? Then other settings, the standard like CPPC Enabled, Preferred Cores, PStates, but also there are other more specifics, like memory clear, memory interleaving, which I don´t know if should be set to 256 or 512, I have PHY Memory Controller, DFE, PMU, PME all enabled, with a PMU Pattenr A. Then the SocUncore enabled. DFStates Disables, Cstates in my case also disable to preven reboots.. I also have set APBDIS in 1 with SOC PState to 0, then DPM LCL both states 2-1-1-1-2-1-1-1 and Power Package Limit to 400W. Also Broad Spetrcrum enable, but some tells that should be disabled..
And last, what would be the procedure to lower tRCDRD? that´s the big question, which parameters should be change and in what order.. at least to try, because copying values is not worh it.. 
Thanks!


----------



## wuttman

lmfodor said:


> I was about to change a ChrosHair Hero VIII Wifi for a Unify-x.


Because you're not happy how your ram clocks? You have pretty poor bin, there is [email protected] kit on newegg, I think it would be better investment.


----------



## wuttman

RonLazer said:


> Oh and since people were chatting about PLL 1.8V voltage (or whatever your motherboard calls it: 1P8, CPU VDD, CPU VTT whatever) I thought I'd share my data:


Nice free performance lol. But how safe is to bump it? Mobo highlighting it red at 1.9+


----------



## TimeDrapery

wuttman said:


> Spoiler
> 
> 
> 
> Because you're not happy how your ram clocks? You have pretty poor bin, there is [email protected] kit on newegg, I think it would be better investment.



@wuttman

3800MT/s CL14 is a better bin than 4000MT/s CL16... 7.368421ns versus 8ns

"_latency (ns) = clock cycle time (ns) × number of clock cycles_"

You could also calculate it thusly,

"_tCL × 2000 ÷ memory speed (for example, '3800')_"


----------



## hazium233

RonLazer said:


> I've also seen some discussion about what suitable tRDWR timings are, so here is a mini calculator for the actual minimum (no guarantee of stability): tRDWR calculator
> 
> Going below the "Fast" timing will fail to POST under any circumstances and probably require a CMOS clear. I've imposed a *Ceiling[tCL/2]* minimum since in my experience going below this causes problems under high-bandwidth loads (probably saturating the memory controller command register limit?)


Thanks for making this, I have a question about the formula. I thought WPRE was 1 or 2 clocks (or rather 0.9 or 1.8 clocks). The Micron 8Gb sheet anyway has it listed in the bin tables as units CK.

I ask because it looks like it is being divided by 2000/speed as if converting ns to clocks.

Coincidentally, CL 14 CWL 14 calculation with WPRE = 2ck and BL=8 equals 7 which is CL/2.


----------



## wuttman

TimeDrapery said:


> 3800MT/s CL14 is a better bin


Isn't it 14-16-16, so more like 15.33 vs 16 and asking 1.5v instead of 1.4?


----------



## TimeDrapery

wuttman said:


> Spoiler
> 
> 
> 
> Isn't it 14-16-16, so more like 15.33 vs 16 and asking 1.5v instead of 1.4?



@wuttman 

No

Neverminding the marketing aspect of what numbers are displayed to the prospective memory buyer, it takes a higher binned kit to run tCL 14 at 3800MT/s than it does to run tCL 16 at 4000MT/s

You can see evidence of this by converting the 3800 CL14 kit's "latency" from ns back to clocks at 4000MT/s

"_7.368421… × 4000 ÷ 2000 = 14.736842_", round this up and you're seeing tCL 15 at 4000MT/s

Now convert the other bub to run the other kit's 3800MT/s...

"_16 × 2000 ÷ 4000 = 8_"

"_8 × 3800 ÷ 2000 = 15.2_", again we're gonna round up (even if we did test and tune to drop down to tCL 15 instead of bump it up to tCL 16... It's still a lesser bin) and, as you can see, the 4000MT/s kit wants tCL 16 at 3800MT/s


----------



## craxton

RonLazer said:


> said that MSI don't actually have any hardware-level ability to control CPU VDDP


to put it (exactly how MSI put it) in an email to me, and one other person.


*Content:*

Dear Ryan (and my last name)

Thanks for contacting MSI technical support.

Regarding your concern, do you mean the CPU VDDP Voltage option? We are really sorry, this option only appear when you use the CPU which has iGPU.

Thanks for your cooperation in advance!

Best Regards,

MSI Technical Support Team


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> to put it (exactly how MSI put it) in an email to me, and one other person.
> 
> 
> *Content:*
> 
> Dear Ryan (and my last name)
> 
> Thanks for contacting MSI technical support.
> 
> Regarding your concern, do you mean the CPU VDDP Voltage option? We are really sorry, this option only appear when you use the CPU which has iGPU.
> 
> Thanks for your cooperation in advance!
> 
> Best Regards,
> 
> MSI Technical Support Team



At least they're relatively polite when telling you they don't care to answer your questions 😂😂😂😂😂

One exchange between myself and a Gigabyte rep ended when the rep told me that in order to learn more about how something related to voltages worked (specifically on their product...) I should go sign up for computer science courses at my local college 😂😂😂😂😂


----------



## craxton

TimeDrapery said:


> I should go sign up for computer science courses at my local college


i swear, to be tech support they ABSOLUTLY should know the mfn tech that they support
or give support for.

as for what MSI said to me, if i hadnt been late to checking my email at the time, i would have told them
it an APU not a cpu with iGPU its just called APU ffs lol



Spoiler



they told mogoled the exact same thing...



if i hade one of AMDs APUs however, id know for sure if CPU_VDDP option 
unhides itself inside MSI b550 bios. 



Spoiler



really need to get the flasher out and use the bios Veii said the option was unlocked in
just didnt quite understand what i was supposed to do with it. 
used the flasher on GPUs before but, no software was mentioned, 
at the time, im unsure if all i needed to do was flash the BIOS file or what
as it was mentioned that it would have some kind of write protection against it
as it wasnt signed or something along those lines..


----------



## ManniX-ITA

lmfodor said:


> Wow, impressive numbers! I just noticed that we both share almost the same timings with the exception of CAD BUS Setup and that you could go to much lower with ProcODT. I can go up to 36 and below have no POST.
> Again, having you a pretty similar memory kit, I mean, should be the same BDIE, and Dual Rank, I can´t believe how yoy can enable 1T GDM disabled. Amaizing.
> Regarding Latency, I didn´t know that 54.4ns would be the lowest value for 2 CCD, what is that, I see a lot of members with lowest lacenty, all of them have one CCD?


The ProcODT works like this on the Unify-X, better much lower than the usual.
Below with ClkDrvStr 40/60 is usually the best.
Veii told me it should be at least 36.9 Ohm but I guess needs to be adjusted to the shorter traces.
Here works up to 36.9 Ohm then starts erroring.
For this 1T profile with setup timings at 56 it gets a bit weird.

On the Aorus Master is the same, minimum 36.9 or it will start struggling POST.
Couldn't do anything similar on the Master with 1T (but it's Rel 1.0).
The Unify-X for non extreme stuff is a very welcoming board, that's one of the main reasons why I like it.

The very low latencies results on the spreadsheet are all one CCD, I could go down to 52.4ns with one CCD.
For me the barrier with dual CCD is 54.4ns.
Guess at that point the kit makes a big difference.
It can go even lower, down to 53.3ns with an SR kit.
But for DR kit I don't see anything below 54.1ns.



lmfodor said:


> Hi @ManniX-ITA , this is the first time I use SISandra. Where did you find the options of Bench Results? I´m attaching the SiSandra complete report. How am I supposed to interpret all these values, I mean the ones that are related to the IC, which ones should it read and what parameters should it have?


You should focus on the Processor Multi-Core Efficiency test and compare with your previous results.
You can run just this test and save the results in the clipboard with Ctrl+C or the second icon from the left on the bottom bar.
Since a higher number of cores results in higher bandwidth, check the shape of the graph.


----------



## ManniX-ITA

RonLazer said:


> Oh and since people were chatting about PLL 1.8V voltage (or whatever your motherboard calls it: 1P8, CPU VDD, CPU VTT whatever) I thought I'd share my data:


Sigh, I had big hopes but it doesn't help me with latency... something else that should be set in tandem?

Tested with AIDA and Sandra but there's no difference at all.
A slight decrease in Geekbench 5:



Micro-Star International Co., Ltd. MS-7D13 vs Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser



Thought it would increase the temps but actually running at 1.95V the CCDs tops a few degrees less running GB5.


----------



## lmfodor

RonLazer said:


> Not gonna make any definitive claims (every dimm is different) but I suspect the following is sub-optimal:
> 
> ProcODT too low for DR dimms, I suspect you'll need 36.9ohm minimum. Remember this is an impedance setting, going lower isn't better, you just want the output impedance to match the transmission line impedance.
> SCLs should be 4, you have CAS strobes synchronized on the rising edge during training, then you expect them to flip during operation and still align?
> Just run tRCDs at 15/15 - who cares about write latency anyway
> tWR/tRTP at 16/8 very likely won't make a noticeable different to stability but will give you a ton more breathing space during high bandwidth loads
> tRFC is too low unless you have hella cooling
> Raise CKE drive strength to 24ohm
> Raise Chip select drive strength to 24ohm, maybe even 30ohm?
> SOC voltage is very high from my testing, I don't think you'd need more than 1.15V SET - but this is admittedly more of a silicon lottery than usual.


Hi @RonLazer 
I took your suggestions and let TM5 run 25 cycles in an open case just to avoid temperature issues, also in a closed case I never run above 42 .. 

















Considering I ran 25 cycles and had only one n error. 10 and two no. 2 and n. 12 which are the same in their description, I think my problem would be the voltage or maybe the CADBUS. I am using 1.52V from VDIMM. So would this be a VDIMM bug or a vSOC, vDDP, IOD, and CCD bug? Because regarding vSOC I understand that for 3800 1.1 should be more than enough. I will try again with 1.1V or 1.12 maybe. But again, how should I proceed to fix these very common errors? I almost always get recommendations to increase VDIMMs, maybe due to the lower tRCDRD, but I also know people who run these same memories with 1.5V, 3800-14-14-14 and the same ProcODT, RTT and CADBUS that I am running now, which in fact they are the default values of the XPM profile or if I leave it to Auto. I read a lot to keep VDDP lower, between 0.9 ~ 0.85, CCD, 0.95 or a little lower, and IOD 0.75 below vSOC, but if I'm not mistaken, it corrects automatically. So I'll rerun the same setup with 1.1V VSOC and 1.02 IOD and lower the CCD to 0.95 to see if it improves, leaving VDIMM 1.52. Regarding bug # 10, I read Veii's description many times that TWR is slow, in fact now it has a higher value at 16, and tRTP at 8 seems to be fine. But again I am confused by the relationship between tRDWR and tWRRDs and tRCDs. I will try tRDWR at 10 to follow the +2 rule set for DR, and RD will keep at 3. I know this is an easy question for most members, I read the old Veii and he calculates very well where the problems were, but that is not written. By the way I am reading your previous posts a lot. 
Here's the AIDA DRAM Timings where shows the default vs actual values.


Spoiler: AIDA DRAM Timings


----------



## lmfodor

@RonLazer you did it! Of cuurse I need to run more test, but the big issue I guess was the TWR to slow. Reading Veii's post for last year I found that tWR is 8ns and to calculate it we should use freq * 8/2000, so 3800*8/2000 is 15.2 but should be an even number. so 16 did the work. And tRFC / tWR, 252/16 is 15.75ns.

However the write speed is not so good as before when I ran 1.5T. I guess I should have to adjust tRDWR more but I'm a little confuse with my Dual Rrank Mems, because the math should be tRDWR x2 <= tRCDRD, so I should lower to. 7 but it won't work, I mean I wouldn't get the POST. So maybe, I think, I should set at 9 and regarding tWRRD maybe I should set to 4, because it x SCL (4)=16, in fact 15/4=3.75. So I think 9-4 would be better, am I thinking right? Again, the Dual Rank confused me a bit since I have to add +2 to tRDWR. This is what could be affecting the low write times?

The big challenge is to lower tRCDRD to 14, because I think I should increase tWR and also tRTP, and sync with a higher tRFC and maybe rising SCL to 15. Below in the spoiler I leave a member that could reach 3800-14-14-14 and 3800-14-8-14 with my same mems and also the same mobo (he has the Dark Hero). I did the test of copying all of his settings but I doesn't work. 
So I prefer to reason rather than copy values to find the alignment in ns and try a configuration that does not give me errors 6 and 12 in burst mode!










Spoiler: 3800-14-8-14-14 Same mem, almost same mobo














And also the famous Igor's Lab review (Review) that I don't know how with those values I achieved 14 flat, but I see that I use very high TWR values as well as high tRFC values too, which makes sense. What is wrong is its tFAW, I do not know where I get those values and also the voltages .. they are in Auto, but very high both VDDP and CCD 
Thanks for your help!


----------



## wuttman

lmfodor said:


> The big challenge is to lower tRCDRD to 14


You will probably have to bring gdm back


----------



## ManniX-ITA

lmfodor said:


> The big challenge is to lower tRCDRD to 14, because I think I should increase tWR and also tRTP, and sync with a higher tRFC and maybe rising SCL to 15. Below in the spoiler I leave a member that could reach 3800-14-14-14 and 3800-14-8-14 with my same mems and also the same mobo (he has the Dark Hero). I did the test of copying all of his settings but I doesn't work.


The big question is: does it run faster?
If it's for the sake of seeing tRCDRD at 14 and that's all ok.
But at the end if it's performing worse I don't see the point...


----------



## lmfodor

wuttman said:


> You will probably have to bring gdm back


Yes sure! I’m not considering reach 14 flat with GDM off. But I’m still far away from that. I need to do the math and understand why I’m failing to reach it. 


Sent from my iPhone using Tapatalk Pro


----------



## lmfodor

ManniX-ITA said:


> The big question is: does it run faster?
> If it's for the sake of seeing tRCDRD at 14 and that's all ok.
> But at the end if it's performing worse I don't see the point...


Well, my old stable configuración with 1T GDM enabled was the best bandwidth results and also the lowest latency also. So I just want to try.. I know it’s not easy. But reading and with some little helps perhaps I would achieve it!


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

lmfodor said:


> Well, my old stable configuración with 1T GDM enabled was the best bandwidth results and also the lowest latency also. So I just want to try.. I know it’s not easy. But reading and with some little helps perhaps I would achieve it!


I agree it's a nice challenge!
Please let us know how it goes and provide benchmarks at the end


----------



## Redwoodz

ManniX-ITA said:


> The big question is: does it run faster?
> If it's for the sake of seeing tRCDRD at 14 and that's all ok.
> But at the end if it's performing worse I don't see the point...


 I wonder if you are not already limiting your bandwith with those timings


----------



## lmfodor

Redwoodz said:


> I wonder if you are not already limiting your bandwith with those timings


Yes, according to what Veii mentioned more than once, he always insisted on achieving flat values, even though it is difficult for many PCBs to achieve that. More in Dual Rank, but if some exploit could be used, perhaps that of TRC = tRAS +1, perhaps the values are better. I really don't know, since we are near to the maximum limits of 3800.


----------



## ManniX-ITA

Redwoodz said:


> I wonder if you are not already limiting your bandwith with those timings


Do you mean those from @gabian or from @lmfodor?
I guess the achievement would be to get tRCDRD working at 14 without making too many sacrifices or compromises.
Otherwise would be too easy


----------



## lmfodor

Hi, does anyone know why y-cruncher is giving me errors with the 18-VST test? I pass all the TM5, OOCT tests, but this one fails








Thanks!


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> i swear, to be tech support they ABSOLUTLY should know the mfn tech that they support
> or give support for.
> 
> as for what MSI said to me, if i hadnt been late to checking my email at the time, i would have told them
> it an APU not a cpu with iGPU its just called APU ffs lol
> 
> 
> 
> Spoiler
> 
> 
> 
> they told mogoled the exact same thing...
> 
> 
> 
> if i hade one of AMDs APUs however, id know for sure if CPU_VDDP option
> unhides itself inside MSI b550 bios.
> 
> 
> 
> Spoiler
> 
> 
> 
> really need to get the flasher out and use the bios Veii said the option was unlocked in
> just didnt quite understand what i was supposed to do with it.
> used the flasher on GPUs before but, no software was mentioned,
> at the time, im unsure if all i needed to do was flash the BIOS file or what
> as it was mentioned that it would have some kind of write protection against it
> as it wasnt signed or something along those lines..



@craxton 

I agree with you 110%... I guess they're cutting costs as much as they can get away with, what a shame

No joke, they'd have probably directed you to exit the chat had you responded that way 😂😂😂😂😂

I tell you what, if I had me one of them new APUs with the Zen 3 cores I'd be telling everyone about it, they're looking pretty fancy!

Dude, BIOS modding and flashing is something I'd really, really like to learn more of and I'm working my way towards doing so but... Good God, so many NDAs stand in the way of clarity! I've been reading whatever I can get my hands on trying to gain some ground


----------



## craxton

TimeDrapery said:


> so many NDAs stand in the way of clarity!


i believe thats why Veii didnt respond so much to my questions.
as to what software i needed or how to use it etc.
then again sometimes its plain and simple considering i was directed to the
proper post on how to use the tool. but just didnt know if i needed the chaflasher or not.


----------



## wuttman

lmfodor said:


> Hi, does anyone know why y-cruncher is giving me errors with the 18-VST test?


I don't but try to bump IOD voltage a little?


----------



## TimeDrapery

lmfodor said:


> Spoiler
> 
> 
> 
> Hi, does anyone know why y-cruncher is giving me errors with the 18-VST test? I pass all the TM5, OOCT tests, but this one fails
> View attachment 2488664
> 
> Thanks!



@lmfodor 

You running offsets via Core Optimizer? I'd look at that first...


----------



## craxton

So close to that 50 ns threshold....

6 months ago i could have cared less, so long as it worked fine, ran youtube/netlflix,
COD, CP2077, you know games and the normies use cases....



Spoiler



but now..... well, i got away from an actual addiction problem to become addicted 
to numbers and benchmark scores...smh lol


----------



## craxton

TimeDrapery said:


> @lmfodor
> 
> You running offsets via Core Optimizer? I'd look at that first...


from what i could gather here the error (if im not mistaken)
is something to do with a drive.....

ctrl f the page and search VST

(im probably wrong) but it could be windows not allowing 
ycruncher folder access at this part of the test...


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> from what i could gather here the error (if im not mistaken)
> is something to do with a drive.....
> 
> ctrl f the page and search VST
> 
> (im probably wrong) but it could be windows not allowing
> ycruncher folder access at this part of the test...



Oh, good look dude! I'm gonna bookmark that page... Thanks!

Maybe page file sizing?

*Edit*: Nope, not page file sizing 😂😂😂😂😂


----------



## lmfodor

craxton said:


> from what i could gather here the error (if im not mistaken)
> is something to do with a drive.....
> 
> ctrl f the page and search VST
> 
> (im probably wrong) but it could be windows not allowing
> ycruncher folder access at this part of the test...


Hi! for some reason when I ran y-cruncher all test, frequently crash on this test.. Now I went back to my stable timings 1.5T and the error disappeared


----------



## Antiarch

thismock said:


> In my limited experience, high FCLK seems to be very dependent on the silicon lottery of your motherboard (in addition to getting lucky with your RAM and CPU).
> 
> I have a set of single rank Rev. E (3600c16) that I can run stable, WHEA-free at 4267c16, 2133 FCLK on an Asrock B450 Fatal1ty Gaming-ITX/AC motherboard.
> 
> Using the exact same components and just switching out the motherboard to an ASUS Crosshair VIII Impact (X570), the highest I could get stable was 3867c16, 1933 FCLK. No matter how much voltage tweaking and BIOS manipulation I tried (and the ASUS x570 board has wayyy more options than the Asrock B450), I was unable to get the system to post at 3933:1967 or higher. Which is bananas because the ASUS is a much more expensive, and supposedly higher quality, motherboard.
> 
> I suspect I was unlucky with my ASUS board, since there are others running the Crosshair VIII Impact at 2000+ FCLK stable, WHEA-free — and I know my CPU and memory can perform at that level. You may also have an unlucky board, since Veii (and I think some others?) are running 2000+ FCLK on the Asrock B550 Phantom Gaming ITX.


Yeah, I transplanted and tried everything in an ASUS ROG STRIX B550-I Gaming. It was about the same and just depended on what I plugged into the various main drivers of FCLK. I get it.  Maybe I'll try my other set of the same RAM in my B550 Phantom Gaming ITX.


----------



## wuttman

thismock said:


> In my limited experience, high FCLK seems to be very dependent on the silicon lottery of your motherboard (in addition to getting lucky with your RAM and CPU)


Could it be coming down to different approaches to treat instability for different boards and agesa? After trying to get at least 1933 IF on my cpu (it works, but instant whea's at prime avx large plus gpu compute load), I don't believe there are samples around that can do rock stable 2000mhz. xD


----------



## Danny.ns

Spent a bit of time finding a lower tRFC - my PC wouldnt POST at 230 (it posted at 235). I set it to 245 for some "headroom" and stresstested with memtest (2500mb*12, ~400%) and it seemed stable enough. Aida64 down to 55.2ns. I know my primaries arent that impressive but I tried 15-16-16 with GDM off/T2 and still would get errors after a while in memtest - for this i had secondary and tertierary on auto (so, very loose). I haven't tried higher than 1.5Vdimm tho. I also have not tried 16-15-15 or 16-14-14 or some weird thing like that (not sure its practical??).


----------



## ManniX-ITA

I'm disappointed with my F4-4000C16-32GTZR kit.
Not only tRCDRD struggles below 16 but it crashes above 1.95V and it's impossible to get 3800CL12 stable.

Just ordered a F4-3200C14D-32GTZSK kit.
Hopefully it's a good bin like Infrared got, 4000CL12 at 2.0V:


Spoiler: 4000CL12


----------



## wuttman

Danny.ns said:


> I know my primaries arent that impressive


Bandwidth is pretty impressive for these clocks


----------



## wuttman

Why rcdrd refuses to work at 16?


----------



## hazium233

lmfodor said:


> Hi! for some reason when I ran y-cruncher all test, frequently crash on this test.. Now I went back to my stable timings 1.5T and the error disappeared


VST error can be from VDDG apparently.

Or on Zen+ I think it can be more generally fabric stability, but I don't think I actually got that one with much frequency on the 2700X.


----------



## lmfodor

hazium233 said:


> VST error can be from VDDG apparently.
> 
> Or on Zen+ I think it can be more generally fabric stability, but I don't think I actually got that one with much frequency on the 2700X.


Yes, every time I change my timings , in addition to running TM5, I run Y-C all test ... and if for some reason there is an error, it appears in that test. So now instead of running all the tests I try the VST first and if it works then I run all the tests. But I didn't know it was related to VDDG. I'm going to investigate a little more. Thanks!


Sent from my iPhone using Tapatalk Pro


----------



## RonLazer

wuttman said:


> Why rcdrd refuses to work at 16?
> View attachment 2488751


I think your tRDWR is probably 1 tick too low. Maybe try letting tRDRDSD/tRDRDDD/tWRWRSD/tWRWRDD go on auto too?


----------



## wuttman

RonLazer said:


> I think your tRDWR is probably 1 tick too low. Maybe try letting tRDRDSD/tRDRDDD/tWRWRSD/tWRWRDD go on auto too?


No luck


----------



## craxton

ManniX-ITA said:


> I'm disappointed with my F4-4000C16-32GTZR kit.
> Not only tRCDRD struggles below 16 but it crashes above 1.95V and it's impossible to get 3800CL12 stable.
> 
> Just ordered a F4-3200C14D-32GTZSK kit.
> Hopefully it's a good bin like Infrared got, 4000CL12 at 2.0V:
> 
> 
> Spoiler: 4000CL12
> 
> 
> 
> 
> View attachment 2488741


question to you...

how do you know when you have "such a good bin"
does tRAS come into play, would you think (image below)
would be a "good enough" bin to achieve this?

yes, depending on PCB which is A0 says TB but, 
i have not taken the heat spreader off to check, and teamgroup
cant say what it is other than R2 spec which they claim they 
dont use a standard normal PCB or some B.S. like that in an email i recieved when i asked about it.


----------



## ManniX-ITA

craxton said:


> question to you...
> 
> how do you know when you have "such a good bin"
> does tRAS come into play, would you think (image below)
> would be a "good enough" bin to achieve this?
> 
> yes, depending on PCB which is A0 says TB but,
> i have not taken the heat spreader off to check, and teamgroup
> cant say what it is other than R2 spec which they claim they
> dont use a standard normal PCB or some B.S. like that in an email i recieved when i asked about it.


The XMP profile doesn't really tell much about the binning.
You need to test it in order to see what it can really do.

I think the old 3200C14 kits were good binning and A0/B0 PCB (or at least based on it).
From the spreadsheets and the HWBot submissions those are the best kits for low timings.
In theory A0/B0 should start struggling above 3600/3800 MHz but I see a lot having fantastic results at 4000 and above.
Going to do see very soon, this week I should get the kit delivered.

Yes most manufacturers don't use standard PCBs.
They slightly modify them or mix some parts.
Especially when they integrated RGB LEDs.
That's what I understood lurking here.


----------



## Veii

wuttman said:


> Why rcdrd refuses to work at 16?
> View attachment 2488751


SD, DDs are wrong and voltage high in combination with procODT
1-5-5-1-7-7 and sub procODT 40 , else disable RTT_NOM (voltage too low for /7)
But for sure lower procODT

You should increase RRD_ to 5-7-20 or change RTTs or lower VDIMM & disable RTT_NOM
Pick one of the 3 options


ManniX-ITA said:


> In theory A0/B0 should start struggling above 3600/3800 MHz but I see a lot having fantastic results at 4000 and above.
> Going to do see very soon, this week I should get the kit delivered


A0's usually "should" fail beyond 4133 (4000 in reality) which is why many board partners beyond 4000 swap PCBs or make a custom design
* A1 should be similar 4133+ is A2 zone
Except for when you adjust RTTs
Please remember to adapt RTTs beyond 1.51v/1.52v, for the health of thekits



thismock said:


> I suspect I was unlucky with my ASUS board, since there are others running the Crosshair VIII Impact at 2000+ FCLK stable, WHEA-free — and I know my CPU and memory can perform at that level. You may also have an unlucky board, since Veii (and I think some others?) are running 2000+ FCLK on the Asrock B550 Phantom Gaming ITX.


It's the I/O's fault & X570 PCIe + XHCI that causes WHEA issues
Sillicon lottery starts to be a thing beyond 2000 FCLK
All Vermeer have to run 2000+ on single rank

Boards PCBs even between Daisy-Chain & T-Topology start to matter beyond 4266MT/s
For up to 4 dimms and dual rank
As for my mention, 2133 is runnable and visually stable
But internally it throttles back 2ns
2100 is the optimal for now
2167 was not bootable but should be possible on Vermeer, as seen with Rev.E kits
2000 @ 14-14-14 seems to be the optimal between easy to run and reasable with PCB
4200 C15-15-15 is nearly identical but far harder to daily 
Maybe 3800C13-13 could be an option, but th FCLK bump is worth it
2100 is complicated, you cut too deep into to boosting powerbudget
Likely fine in a 5900X but not so easy on a 5600X
120(122A) EDC cap is just too low for 2100 SOC requirements


----------



## weleh

If 1900 fCLK works straight out of the box, why would one need extra tweaking for > 1900? 
Makes no sense. It does look like silicon lottery and agesa limitation.


----------



## weleh

I did an experiment on my own 5800X and Unify X running SR 2*8GB bdie.

1900 works out of the box no adjusments to VSOC, VDDGs, etc.

1900 scales positively with reduction to VDDG IOD, namely, below 1V it keeps scaling positively until it stops booting at <0.9V. Higher than 1V makes it go from 1 WHEA per 5 min to 1 WHEA per second.

Increasing VSOC past 1.1V also brings no noticeable improvement and so doesn't reducing procODT as far as I could measure.

This scaling is observed until 2000 fCLK. After 2000 fCLK, you start to see strange behaviours from the throttling mentioned here I guess, cpu boost gets lower and latency higher.
I am able to boot at until 2200 synced. Haven't tried higher with newer AGESA/BIOs.

MSI doesn't expose PLL voltage although I think it's 1P8 voltage but not sure. Also, I've used LN2 mode in Zen 2 era to boot and stabilize 1 tick higher fCLK however on Zen 3 on this board, enabling LN2 actually fails post/boot.


----------



## PJVol

Veii said:


> Likely fine in a 5900X but not so easy on a 5600X
> 120(122A) EDC cap is just too low for 2100 SOC requirements


Yeah, exactly what I experienced when tested mine @2100. All scales well up to (and icluding) 2066 (with a few caveats). At 2100 AIDA latency is fine, but something' starts to eat up power too much

98-ish vs 95-ish seconds (2100 vs 2033) with easy preset in membench, and throttling a lot according to GB5 multicore.


----------



## TimeDrapery

I made another attempt to pull 14s flat and here are my results... They're... Not flat 😂😂😂😂😂

I'm so confused on how to move forward I just tried silly stuff... Dunno if setup timings work (or tCKE) for Matisse or if my profile is just me setting future me up for when I finally get around to obtaining a 5800X



Spoiler: Screenshots












This just spewed errors #0, #12, and #6 within a minute of starting TM5











































*Edit*: I just now purchased another F4-3200C14-8GTZR (8GB, SR) kit so I'll be adding two more DIMMs on the 5th of May... If I hate it I'll prolly just pull em and use em in another system until I'm upgraded to Zen 3 and I've completed assembly of the watercooling loop...

@Veii
If you're not too busy traveling and making music would you mind taking a look at the screenshots I've got posted above and tell me what I should do to improve the efficacy of my efforts here? Please and thank you always


----------



## ManniX-ITA

Veii said:


> A0's usually "should" fail beyond 4133 (4000 in reality) which is why many board partners beyond 4000 swap PCBs or make a custom design
> * A1 should be similar 4133+ is A2 zone
> Except for when you adjust RTTs
> Please remember to adapt RTTs beyond 1.51v/1.52v, for the health of thekits


I'll take a shot of the PCB when I put on the heatsinks for the waterblock.
Probably going to be rude with this kit 
But I'll keep in mind your advice about the RTT.

What do you think about running ClkDrvStr at 120 Ohm?

I managed to run my DR kit at 1T without setup timings.
Only using this crazy high ClkDrvStr; but the RTT and ProcODT is very mild.

It's just a tad better in latency than with setup timings.
But maybe for CPUs with a single CCD that can go very low in latency it makes a big difference.


----------



## jomama22

weleh said:


> I did an experiment on my own 5800X and Unify X running SR 2*8GB bdie.
> 
> 1900 works out of the box no adjusments to VSOC, VDDGs, etc.
> 
> 1900 scales positively with reduction to VDDG IOD, namely, below 1V it keeps scaling positively until it stops booting at <0.9V. Higher than 1V makes it go from 1 WHEA per 5 min to 1 WHEA per second.
> 
> Increasing VSOC past 1.1V also brings no noticeable improvement and so doesn't reducing procODT as far as I could measure.
> 
> This scaling is observed until 2000 fCLK. After 2000 fCLK, you start to see strange behaviours from the throttling mentioned here I guess, cpu boost gets lower and latency higher.
> I am able to boot at until 2200 synced. Haven't tried higher with newer AGESA/BIOs.
> 
> MSI doesn't expose PLL voltage although I think it's 1P8 voltage but not sure. Also, I've used LN2 mode in Zen 2 era to boot and stabilize 1 tick higher fCLK however on Zen 3 on this board, enabling LN2 actually fails post/boot.


What do you mean by "scaling" when lowering iod? You mean like latency benefits or somthing else?


----------



## wuttman

Veii said:


> You should increase RRD_ to 5-7-20


This have completely ruined performance, +5 seconds in membench 1.7.3 Rtt_nom off just doesn't boot, I have 4x8 sticks and I thought 7/3/1 is default for that? So I'm left with lowering vdimm and proc, I guess, but no luck so far.


----------



## KedarWolf

Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 176GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.9ns (9.5ns - 61.4ns)
Inter-Thread (same Core) Latency : 9.8ns
Inter-Core (same Module) Latency : 21.0ns
Inter-Module (same Package) Latency : 58.4ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.5GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1716.17MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.80ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 36.22MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 22.2ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.6ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.1ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.4ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.8ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.5ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 56.9ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 56.6ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.9ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.0ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.5ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.1ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.1ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.5ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.0ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.8ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.5ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.8ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.5ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.9ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.4ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.9ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.0ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.5ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.1ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.1ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.2ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.8ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.7ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.4ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 21.0ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.8ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.0ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.1ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 60.9ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 61.0ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 60.8ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 60.5ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 60.3ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 22.2ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 21.9ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 23.0ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 22.3ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.6ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 21.8ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 61.4ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 61.1ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 61.2ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 60.9ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 61.1ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 60.8ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 60.5ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 60.3ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 21.3ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.6ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 19.9ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 19.8ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 60.3ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 60.7ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 60.2ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 60.6ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.7ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 60.4ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.6ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 60.0ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 22.0ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 22.2ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 21.2ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.6ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.5ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 19.9ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 19.8ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 60.4ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 60.8ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 60.1ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 60.5ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.7ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 60.4ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.6ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 60.1ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.7ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 19.9ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.1ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 61.1ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 60.9ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 60.9ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 60.4ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 60.4ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 60.5ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 60.2ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 60.1ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 21.9ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 23.2ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 21.4ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.7ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 19.9ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.2ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.0ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.0ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.3ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.0ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.2ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.6ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.3ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.0ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.8ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.7ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.2ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.0ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.8ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.6ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.4ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.9ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.8ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.7ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.9ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 21.8ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.0ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.9ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.7ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.7ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.2ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.9ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.8ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.6ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.4ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.8ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.7ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.7ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.7ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 57.4ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.1ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 57.6ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.8ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.4ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.3ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.9ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.2ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.3ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.9ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.5ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.8ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.7ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.7ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.4ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.2ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 57.6ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.6ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.4ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.8ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.3ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 22.4ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.4ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 57.8ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.5ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.7ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.1ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.0ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.7ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.8ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.6ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.9ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.8ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.9ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 22.5ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.4ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.0ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.5ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.6ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.1ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.0ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.7ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.7ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.0ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.6ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.1ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.1ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.1ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.6ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.6ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.8ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.3ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.4ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.7ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.9ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 22.3ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 57.9ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.5ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.1ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.2ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.0ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.5ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.5ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.2ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 20.0ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.7ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.9ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.3ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.5ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.1ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.9ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.0ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.4ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.6ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.6ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.2ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.0ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.2ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 20.1ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.7ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.9ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.3ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.9ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.9ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.7ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.5ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.5ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.4ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 56.1ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 56.8ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 56.9ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.0ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.1ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 57.7ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.3ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.2ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 18.9ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.9ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.7ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.5ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.4ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.4ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.6ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.4ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.0ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.1ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.1ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.7ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.4ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.6ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.7ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.3ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.2ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 20.1ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.6ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.4ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.0ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.1ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.4ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.3ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.0ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.9ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.0ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.7ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.4ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.7ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.6ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.9ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.1ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.6ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.0ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.4ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.8ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.4ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.3ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.9ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.2ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.9ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.9ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.3ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.1ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.3ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.7ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.3ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.1ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 21.1ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.8ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.7ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.5ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.3ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.9ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.6ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.7ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.4ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.2ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 57.9ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.2ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.2ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.3ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.9ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.7ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.3ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.3ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.6ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.7ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 22.3ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.4ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.8ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.9ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 59.2ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.6ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.5ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 21.1ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 23.0ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.7ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 22.3ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.0ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.4ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.4ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.7ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.6ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.5ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.2ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.6ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.6ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.1ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.2ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.9ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.0ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 22.2ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.4ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.2ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.9ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.6ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.2ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.5ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.5ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 56.9ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 56.3ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.0ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.9ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.6ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.3ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.9ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.4ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.3ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.8ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.8ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.7ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.0ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 56.8ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.2ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.2ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 57.8ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.7ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.7ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.1ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.7ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.3ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.3ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 57.3ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.2ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.4ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.2ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.3ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.6ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.6ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.3ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.2ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.0ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.1ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.1ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 57.9ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.1ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.7ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.2ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 21.0ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.9ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.7ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.7ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.3ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.0ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.8ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.6ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.4ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.9ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.9ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.7ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.7ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.4ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.3ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.6ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.8ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.5ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.4ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.9ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.4ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 22.9ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.4ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.9ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.6ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.0ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.0ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.7ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.8ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 57.9ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.6ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.1ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.2ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.0ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.6ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.5ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.2ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.2ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 20.0ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.7ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.9ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.4ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 18.9ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.9ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.7ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.5ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.4ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.4ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.6ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.4ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.0ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.1ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.4ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.3ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.0ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.0ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.9ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.6ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.7ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.2ns
1x 64bytes Blocks Bandwidth : 26GB/s
4x 64bytes Blocks Bandwidth : 28.76GB/s
4x 256bytes Blocks Bandwidth : 96.46GB/s
4x 1kB Blocks Bandwidth : 321.1GB/s
4x 4kB Blocks Bandwidth : 507GB/s
16x 4kB Blocks Bandwidth : 726.56GB/s
4x 64kB Blocks Bandwidth : 995.61GB/s
16x 64kB Blocks Bandwidth : 598.29GB/s
8x 256kB Blocks Bandwidth : 602.17GB/s
4x 1MB Blocks Bandwidth : 608.9GB/s
16x 1MB Blocks Bandwidth : 24.7GB/s
8x 4MB Blocks Bandwidth : 19.17GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 5GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## lmfodor

KedarWolf said:


> View attachment 2489013
> 
> 
> View attachment 2489011
> 
> 
> 
> 
> Code:
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 176GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Average Inter-Thread Latency : 39.9ns (9.5ns - 61.4ns)
> Inter-Thread (same Core) Latency : 9.8ns
> Inter-Core (same Module) Latency : 21.0ns
> Inter-Module (same Package) Latency : 58.4ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5.5GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1716.17MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 3.80ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 707.05kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 36.22MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 0.08ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-M0C0T0 <> U2-M0C1T0 Data Latency : 22.2ns
> U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.6ns
> U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.1ns
> U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
> U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.4ns
> U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.8ns
> U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.5ns
> U0-M0C0T0 <> U16-M1C0T0 Data Latency : 56.9ns
> U0-M0C0T0 <> U18-M1C1T0 Data Latency : 56.6ns
> U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.9ns
> U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
> U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.0ns
> U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.5ns
> U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.1ns
> U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.1ns
> U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
> U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
> U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.5ns
> U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.0ns
> U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.8ns
> U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.5ns
> U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.8ns
> U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.5ns
> U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.9ns
> U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.4ns
> U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.9ns
> U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
> U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.0ns
> U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.5ns
> U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.1ns
> U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.1ns
> U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.2ns
> U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.8ns
> U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.7ns
> U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.4ns
> U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
> U2-M0C1T0 <> U14-M0C7T0 Data Latency : 21.0ns
> U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.8ns
> U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.0ns
> U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.1ns
> U2-M0C1T0 <> U22-M1C3T0 Data Latency : 60.9ns
> U2-M0C1T0 <> U24-M1C4T0 Data Latency : 61.0ns
> U2-M0C1T0 <> U26-M1C5T0 Data Latency : 60.8ns
> U2-M0C1T0 <> U28-M1C6T0 Data Latency : 60.5ns
> U2-M0C1T0 <> U30-M1C7T0 Data Latency : 60.3ns
> U2-M0C1T0 <> U1-M0C0T1 Data Latency : 22.2ns
> U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
> U2-M0C1T0 <> U5-M0C2T1 Data Latency : 21.9ns
> U2-M0C1T0 <> U7-M0C3T1 Data Latency : 23.0ns
> U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
> U2-M0C1T0 <> U11-M0C5T1 Data Latency : 22.3ns
> U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.6ns
> U2-M0C1T0 <> U15-M0C7T1 Data Latency : 21.8ns
> U2-M0C1T0 <> U17-M1C0T1 Data Latency : 61.4ns
> U2-M0C1T0 <> U19-M1C1T1 Data Latency : 61.1ns
> U2-M0C1T0 <> U21-M1C2T1 Data Latency : 61.2ns
> U2-M0C1T0 <> U23-M1C3T1 Data Latency : 60.9ns
> U2-M0C1T0 <> U25-M1C4T1 Data Latency : 61.1ns
> U2-M0C1T0 <> U27-M1C5T1 Data Latency : 60.8ns
> U2-M0C1T0 <> U29-M1C6T1 Data Latency : 60.5ns
> U2-M0C1T0 <> U31-M1C7T1 Data Latency : 60.3ns
> U4-M0C2T0 <> U6-M0C3T0 Data Latency : 21.3ns
> U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.6ns
> U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
> U4-M0C2T0 <> U12-M0C6T0 Data Latency : 19.9ns
> U4-M0C2T0 <> U14-M0C7T0 Data Latency : 19.8ns
> U4-M0C2T0 <> U16-M1C0T0 Data Latency : 60.3ns
> U4-M0C2T0 <> U18-M1C1T0 Data Latency : 60.7ns
> U4-M0C2T0 <> U20-M1C2T0 Data Latency : 60.2ns
> U4-M0C2T0 <> U22-M1C3T0 Data Latency : 60.6ns
> U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.7ns
> U4-M0C2T0 <> U26-M1C5T0 Data Latency : 60.4ns
> U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.6ns
> U4-M0C2T0 <> U30-M1C7T0 Data Latency : 60.0ns
> U4-M0C2T0 <> U1-M0C0T1 Data Latency : 22.0ns
> U4-M0C2T0 <> U3-M0C1T1 Data Latency : 22.2ns
> U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
> U4-M0C2T0 <> U7-M0C3T1 Data Latency : 21.2ns
> U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.6ns
> U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.5ns
> U4-M0C2T0 <> U13-M0C6T1 Data Latency : 19.9ns
> U4-M0C2T0 <> U15-M0C7T1 Data Latency : 19.8ns
> U4-M0C2T0 <> U17-M1C0T1 Data Latency : 60.4ns
> U4-M0C2T0 <> U19-M1C1T1 Data Latency : 60.8ns
> U4-M0C2T0 <> U21-M1C2T1 Data Latency : 60.1ns
> U4-M0C2T0 <> U23-M1C3T1 Data Latency : 60.5ns
> U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.7ns
> U4-M0C2T0 <> U27-M1C5T1 Data Latency : 60.4ns
> U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.6ns
> U4-M0C2T0 <> U31-M1C7T1 Data Latency : 60.1ns
> U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
> U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.7ns
> U6-M0C3T0 <> U12-M0C6T0 Data Latency : 19.9ns
> U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.1ns
> U6-M0C3T0 <> U16-M1C0T0 Data Latency : 61.1ns
> U6-M0C3T0 <> U18-M1C1T0 Data Latency : 60.9ns
> U6-M0C3T0 <> U20-M1C2T0 Data Latency : 60.9ns
> U6-M0C3T0 <> U22-M1C3T0 Data Latency : 60.4ns
> U6-M0C3T0 <> U24-M1C4T0 Data Latency : 60.4ns
> U6-M0C3T0 <> U26-M1C5T0 Data Latency : 60.5ns
> U6-M0C3T0 <> U28-M1C6T0 Data Latency : 60.2ns
> U6-M0C3T0 <> U30-M1C7T0 Data Latency : 60.1ns
> U6-M0C3T0 <> U1-M0C0T1 Data Latency : 21.9ns
> U6-M0C3T0 <> U3-M0C1T1 Data Latency : 23.2ns
> U6-M0C3T0 <> U5-M0C2T1 Data Latency : 21.4ns
> U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
> U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
> U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.7ns
> U6-M0C3T0 <> U13-M0C6T1 Data Latency : 19.9ns
> U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.2ns
> U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.0ns
> U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.0ns
> U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.3ns
> U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
> U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.0ns
> U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.2ns
> U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.6ns
> U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.3ns
> U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.0ns
> U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.8ns
> U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.7ns
> U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
> U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.2ns
> U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.0ns
> U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.8ns
> U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.6ns
> U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.4ns
> U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.9ns
> U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.8ns
> U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.7ns
> U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.9ns
> U8-M0C4T0 <> U5-M0C2T1 Data Latency : 21.8ns
> U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
> U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
> U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.0ns
> U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.9ns
> U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.7ns
> U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.7ns
> U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.2ns
> U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.9ns
> U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.8ns
> U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.6ns
> U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.4ns
> U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.8ns
> U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.7ns
> U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.7ns
> U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.7ns
> U10-M0C5T0 <> U16-M1C0T0 Data Latency : 57.4ns
> U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.1ns
> U10-M0C5T0 <> U20-M1C2T0 Data Latency : 57.6ns
> U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.8ns
> U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.4ns
> U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.3ns
> U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.9ns
> U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.2ns
> U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.3ns
> U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.9ns
> U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
> U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.5ns
> U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
> U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.8ns
> U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.7ns
> U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.7ns
> U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.4ns
> U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.2ns
> U10-M0C5T0 <> U21-M1C2T1 Data Latency : 57.6ns
> U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.6ns
> U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.4ns
> U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
> U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.8ns
> U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.3ns
> U12-M0C6T0 <> U14-M0C7T0 Data Latency : 22.4ns
> U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.4ns
> U12-M0C6T0 <> U18-M1C1T0 Data Latency : 57.8ns
> U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.5ns
> U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.7ns
> U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.1ns
> U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.0ns
> U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.7ns
> U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.8ns
> U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.6ns
> U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
> U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
> U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.9ns
> U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.8ns
> U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.9ns
> U12-M0C6T0 <> U15-M0C7T1 Data Latency : 22.5ns
> U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.4ns
> U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.0ns
> U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.5ns
> U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.6ns
> U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.1ns
> U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.0ns
> U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.7ns
> U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.7ns
> U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.0ns
> U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.6ns
> U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.1ns
> U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.1ns
> U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.1ns
> U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
> U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.6ns
> U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
> U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.6ns
> U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.8ns
> U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.3ns
> U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.4ns
> U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.7ns
> U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.9ns
> U14-M0C7T0 <> U13-M0C6T1 Data Latency : 22.3ns
> U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
> U14-M0C7T0 <> U17-M1C0T1 Data Latency : 57.9ns
> U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.5ns
> U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.1ns
> U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.2ns
> U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.0ns
> U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.5ns
> U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.5ns
> U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
> U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.2ns
> U16-M1C0T0 <> U20-M1C2T0 Data Latency : 20.0ns
> U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.7ns
> U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.9ns
> U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.3ns
> U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
> U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.5ns
> U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.1ns
> U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.9ns
> U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.0ns
> U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.4ns
> U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.6ns
> U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.6ns
> U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.2ns
> U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.0ns
> U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
> U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.2ns
> U16-M1C0T0 <> U21-M1C2T1 Data Latency : 20.1ns
> U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.7ns
> U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.9ns
> U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.3ns
> U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
> U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
> U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.9ns
> U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.9ns
> U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.7ns
> U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.5ns
> U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.5ns
> U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.4ns
> U18-M1C1T0 <> U1-M0C0T1 Data Latency : 56.1ns
> U18-M1C1T0 <> U3-M0C1T1 Data Latency : 56.8ns
> U18-M1C1T0 <> U5-M0C2T1 Data Latency : 56.9ns
> U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
> U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.0ns
> U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.1ns
> U18-M1C1T0 <> U13-M0C6T1 Data Latency : 57.7ns
> U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.3ns
> U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.2ns
> U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
> U18-M1C1T0 <> U21-M1C2T1 Data Latency : 18.9ns
> U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.9ns
> U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.7ns
> U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.5ns
> U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.4ns
> U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.4ns
> U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
> U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.6ns
> U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.4ns
> U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.0ns
> U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.1ns
> U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.1ns
> U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.7ns
> U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.4ns
> U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.6ns
> U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.7ns
> U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
> U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.3ns
> U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.2ns
> U20-M1C2T0 <> U17-M1C0T1 Data Latency : 20.1ns
> U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
> U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
> U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
> U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.6ns
> U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.4ns
> U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.0ns
> U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.1ns
> U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.4ns
> U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.3ns
> U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.0ns
> U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.9ns
> U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.0ns
> U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.7ns
> U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.4ns
> U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.7ns
> U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.6ns
> U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.9ns
> U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
> U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.1ns
> U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.6ns
> U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.0ns
> U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.4ns
> U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.8ns
> U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.4ns
> U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.3ns
> U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
> U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.9ns
> U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.2ns
> U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
> U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.9ns
> U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.9ns
> U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.3ns
> U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.1ns
> U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.3ns
> U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
> U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.3ns
> U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.1ns
> U24-M1C4T0 <> U17-M1C0T1 Data Latency : 21.1ns
> U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.8ns
> U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.7ns
> U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.5ns
> U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
> U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.3ns
> U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
> U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.9ns
> U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.6ns
> U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.7ns
> U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.4ns
> U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U5-M0C2T1 Data Latency : 57.9ns
> U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.3ns
> U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.9ns
> U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.7ns
> U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.3ns
> U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
> U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.3ns
> U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
> U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
> U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.6ns
> U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.7ns
> U28-M1C6T0 <> U30-M1C7T0 Data Latency : 22.3ns
> U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.4ns
> U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
> U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.8ns
> U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
> U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.9ns
> U28-M1C6T0 <> U11-M0C5T1 Data Latency : 59.2ns
> U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.6ns
> U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.5ns
> U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
> U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
> U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
> U28-M1C6T0 <> U23-M1C3T1 Data Latency : 21.1ns
> U28-M1C6T0 <> U25-M1C4T1 Data Latency : 23.0ns
> U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.7ns
> U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
> U28-M1C6T0 <> U31-M1C7T1 Data Latency : 22.3ns
> U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.0ns
> U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.4ns
> U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.4ns
> U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
> U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.6ns
> U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.5ns
> U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.2ns
> U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.6ns
> U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.6ns
> U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.1ns
> U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.2ns
> U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.9ns
> U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.0ns
> U30-M1C7T0 <> U29-M1C6T1 Data Latency : 22.2ns
> U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
> U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.4ns
> U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.2ns
> U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.9ns
> U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.6ns
> U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.2ns
> U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.5ns
> U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.5ns
> U1-M0C0T1 <> U17-M1C0T1 Data Latency : 56.9ns
> U1-M0C0T1 <> U19-M1C1T1 Data Latency : 56.3ns
> U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.0ns
> U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
> U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.9ns
> U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.6ns
> U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.3ns
> U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.9ns
> U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.4ns
> U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.3ns
> U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
> U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.8ns
> U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.8ns
> U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.7ns
> U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.0ns
> U3-M0C1T1 <> U19-M1C1T1 Data Latency : 56.8ns
> U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.2ns
> U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.2ns
> U3-M0C1T1 <> U25-M1C4T1 Data Latency : 57.8ns
> U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.7ns
> U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.7ns
> U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.1ns
> U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
> U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.7ns
> U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
> U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.3ns
> U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.3ns
> U5-M0C2T1 <> U17-M1C0T1 Data Latency : 57.3ns
> U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.2ns
> U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.4ns
> U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
> U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.2ns
> U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.3ns
> U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
> U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.6ns
> U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
> U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.6ns
> U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.3ns
> U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.2ns
> U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.0ns
> U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.1ns
> U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.1ns
> U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
> U7-M0C3T1 <> U25-M1C4T1 Data Latency : 57.9ns
> U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.1ns
> U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.7ns
> U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.2ns
> U9-M0C4T1 <> U11-M0C5T1 Data Latency : 21.0ns
> U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.9ns
> U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.7ns
> U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.7ns
> U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.3ns
> U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.0ns
> U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.8ns
> U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.6ns
> U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.9ns
> U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.9ns
> U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.7ns
> U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.7ns
> U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.4ns
> U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.3ns
> U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.6ns
> U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.8ns
> U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.5ns
> U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.9ns
> U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.4ns
> U13-M0C6T1 <> U15-M0C7T1 Data Latency : 22.9ns
> U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.9ns
> U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
> U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.6ns
> U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.0ns
> U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.0ns
> U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.7ns
> U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.8ns
> U15-M0C7T1 <> U17-M1C0T1 Data Latency : 57.9ns
> U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.6ns
> U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.1ns
> U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.2ns
> U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.0ns
> U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.6ns
> U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.5ns
> U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.2ns
> U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.2ns
> U17-M1C0T1 <> U21-M1C2T1 Data Latency : 20.0ns
> U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.7ns
> U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.9ns
> U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.4ns
> U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
> U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
> U19-M1C1T1 <> U21-M1C2T1 Data Latency : 18.9ns
> U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.9ns
> U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.7ns
> U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.5ns
> U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.4ns
> U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.4ns
> U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
> U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.6ns
> U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.4ns
> U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.0ns
> U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.1ns
> U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.4ns
> U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.3ns
> U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.0ns
> U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.0ns
> U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
> U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
> U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.9ns
> U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.6ns
> U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.7ns
> U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.2ns
> 1x 64bytes Blocks Bandwidth : 26GB/s
> 4x 64bytes Blocks Bandwidth : 28.76GB/s
> 4x 256bytes Blocks Bandwidth : 96.46GB/s
> 4x 1kB Blocks Bandwidth : 321.1GB/s
> 4x 4kB Blocks Bandwidth : 507GB/s
> 16x 4kB Blocks Bandwidth : 726.56GB/s
> 4x 64kB Blocks Bandwidth : 995.61GB/s
> 16x 64kB Blocks Bandwidth : 598.29GB/s
> 8x 256kB Blocks Bandwidth : 602.17GB/s
> 4x 1MB Blocks Bandwidth : 608.9GB/s
> 16x 1MB Blocks Bandwidth : 24.7GB/s
> 8x 4MB Blocks Bandwidth : 19.17GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : A20F10-1009
> Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
> Platform Compliance : x64
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> URL : https://www.amd.com
> Speed : 5GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 8 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : A20F10-1009
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


Hi @KedarWolf, I´d like your timings. I just testing it with my 3800CL14, that seems to be the same memory type (Mine shows A2: F4-3800CL14-16TGNZ (16GB, DR). I´m a liitle tired to try tRCDRD in 15. A quick question, how did you calculate your TRP to 19 and tRAS 21? Then the tWR at 10 and tRTP 6? Shouln´t be tWRT 12? I should have to think outside the rulesets 

At last, I am new using SiSandra, its a powerful tool, however no s intuitive yet, how did you export the text output below your graph? I tried to make some report.. also the export options but only allos to export to XML, CSV....

I let you know how my test with your timings results.

Thanks!


----------



## lmfodor

Hi , I would like to know if any of you are using any High Performance Plan by BIOS. I´m actually using SMU 56.45 and I want to lower some version to try above 4000 Freq without WHEAs. I read from Veii that Patch B, not C, would perform well abobe 4000 Freq. Some time ago I read a post from 1Usmus that recommended certain parameters in the BIOS and since I am optimizing my memory overclocking I would like to know if any of these parameters could help or perhaps thet are complicating my OC . Among them I had set these options:


*Global C-state Control = Enabled* (Advanced\AMD CBS). I set ti to disable to prevent Reboots under idle. However I was reading that rising IOD Voltage above 1.05V would prevent reboots. Is that right?
*DF CStates = Disabled* (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\DF Cstates = Disabled)
This setting does not allow for Infinity Fabric to go to a low-power state when the processor has entered Cx states..
*PPC Adjustment = PState 0*. Two settings below:
(Advanced\AMD CBS\NBIO Common Options\SMU Common Options\*APBDIS = 1
AND*
(Advanced\AMD CBS\NBIO Common Options\SMU Common Options\*Fixed SOC Pstate = P0*)
4. *CPPC = Enabled* (Advanced\AMD CBS\NBIO Common Options\SMU Common Options)
5. C*PPC Preferred Cores = Enabled* (Advanced\AMD CBS\NBIO Common Options\SMU Common Options)
6. P*ower Supply Idle Control = Low Current Idle* (Advanced\AMD CBS\CPU Common Options) Here I had set it to "Typical Power Idle" however it suggest Low Current, do you know what would be better?
PBO: *Enable Precision Boost Overdrive* in UEFI BIOS. Allow it to run from the BIOS/Motherboard control. This is much easier than setting in AMD Ryzen Master manually in Windows; just enable these BIOS Options and don't mess with Ryzen Master in Windows except to experiment. PBO: Ai Tweaker or Extreme Tweaker on Asus mobo's\Precision Boost Overdrive, Accept\Precision Boost Overdrive = Enabled; Advanced\AMD Overclocking, Accept\Precision Boost Overdrive = Enabled, . PBO: Advanced\AMD CBS\NBIO Common Options, Accept\XFR Enhancement, Accept\ Precision Boost Overdrive = Enabled. Does it necessary to enable in all of the BIOS options? I only set it on Advanced Overclokng. All the rest values I leave in AUTO
*PBO FMax Enhancer:* Ai Tweaker or Extreme Tweaker on Asus mobo's\Precision Boost Overdrive, Accept\PBO Fmax Enhancer = Enabled ****Many people report they get better results with this option set it to DISABLED. Try it both ways to see which gives the better score It appears to not be needed (set to Disable) on Ryzen 5000/Zen 3 CPU's and effects scores negatively.. (I set to Disable)*
And also enable to improve L3 Cache, but it is not improving it much, it should be above 650GB / s flat with 10.4 sec latency

"SOC Uncore = Enable"
cTDP = 400
Package Power Liimit 400 (CBS-SMU)
Then DPM LCLK to 2-1-1-1-2-1-1-1
And also Enabled PMU Training until Phy Configuration (CBS\DDR4 Common Options); DFE, FFE both enabled ad PMU Pattern Bits Control to "A"
And also disable SB Clock Spread Spectrum, and set VTTDDR Voltage = VDIMM /2 . What I dont know what is VPP_MEM, anybody knows?

All of this to have a @high performance power plan. Maybe some settings would be an overkill.

And I take the opportunity to validate if my External DIGI + Power Control (on ASUS..but it´s LLC config) are fine, I set it to:

Voltage Monitor = Die Sense
CPU LLC Auto (I know Level 3 woud be better, but If I leave to Auto I got a better CB Score, maybe it rise automatically to Level 4
CPU Current Capabiliy to 120%
CPU VRM Switching Freq to Manual and I set 500 KHz
CPU Power Duty Control = T. Probe
CPU: Pwer Phase Control to Optimizd
CPU Power thermal Control to 120
VDDSOC LLC = Level 4
VDDSCO Switching Freq to 500 also
VDDSOC: Power Phase Response and Manual Adjustment to FAST and
DRAM Current Capability 110%
DRAM Power Phase Control = Leave it as Extreme
DRAM Switching Freq Manual Fix it to 300.
Would it be right for MEM OC?

Could my PBO Settings + Curve Optimizer impact in Mem OC? I also set to default, just enable it, and other test was to set only PBO Limits to motherboard.. and then I left with my best tight value that is *300/235/400* with CO* -28 -26 -26 -28 -25* (my best 1st core), *-24 *(my 2nd best core), then CCD2, *-28, -25- 24 -28 - 30 -30* with +100 Boost Clock Override.. I´m not using scalar. I read that it might degrade the CPU with some spikes.. and Platform Thermal Throttle Limit to 85. I think I would try set to All Core negative to -24 that is my lowest curve value, maybe the PBO algorithm perform better that setting per core values, and perhaps I should add a little + VCore Offset. My default CPU Core Voltage is around 1.425~1457. I see it a little bit low, because if I remember correctly, it was 1.5..very high. Por some reason the reading now is a little low, even If I clear CMOS and start over from scratch,

I hope you can advise me if these values are you using , if some would be overkill or I should adjust some of them, and if you have any other recommendation about the values of my PBO, maybe I could try All Cores but my question is how much the Offset value would be. I know that much voltage is not good.

Thanks!


----------



## Veii

wuttman said:


> This have completely ruined performance, +5 seconds in membench 1.7.3 Rtt_nom off just doesn't boot, I have 4x8 sticks and I thought 7/3/1 is default for that? So I'm left with lowering vdimm and proc, I guess, but no luck so far.


Isnt the goal to get it stable in the first place
They are slower, but its not that extreme ~ as i run them at 7-9-28
Maybe the instability got worse, but they play together with SD-DDs

Depends what you've tried
Would RTT_NOM disabled post if you increase RTT_PARK to /2 with at least 40 or higher ClkDrvStr (CAD_BUS first value)

The RTT values that where shared for Matisse as easy to run options, are not optimal anymore
Vermeer works a bit different that Matisse
Since the recent 1201 and 1202 update, my settings fully bricked
Was initially running 6/3/6 , but i had to go down to 5/3/7 or even 6/3/0 worked

Something changed with the IMC, and i'm still testing around
Compared to 1200 , but IPC increased nicely
5-23% according to geekbench
Just it spills random 2's out for some random reason


TimeDrapery said:


> @Veii
> If you're not too busy traveling and making music would you mind taking a look at the screenshots I've got posted above and tell me what I should do to improve the efficacy of my efforts here? Please and thank you always
> 
> 
> TimeDrapery said:
> 
> 
> 
> This just spewed errors #0, #12, and #6 within a minute of starting TM5
Click to expand...

Is this TM5 profile based upon 1usmus_v3 ?
Because for example Anta's profile , the error numbers differ fully and mean something completely different
CsOdtDrvStr got a bump between 30-40ohm , in order to work against the broken memory training since AGESA 1.1.0.0*A*
After Patch C , it got worse and worse / this was about the correct option, to get it towards a useable setting
It's not fitting for Matisse.
There the hard work of 1usmus from the DRAM calculator works blindly

ClkDrvStr bump still is a good method to help lowering procODT and getting GDM off
Which btw is too high for you
in combination with high ClkDrvStr, it might be too much for the PCB and you can "PCB Crash" - IF the errors mean the same which they do on Yuri's preset

Matisse's procODT range was:
28-32ohm for 2x8GB SR
34-36ohm for Dual Rank or 4x8Gb
34~ for Rev.E or Micron B-Die
30-32 for Hynix-MFR or AFR (CJR should be fine within 30)
Overall it's too high.

The minimum & optimal value at 900-950-1050 (1900FCLK) on Matisse was 28ohm with B-dies, and anything else a tad higher.
But not 3 steps higher like you do run atm.
It also needed the UncoreOC flag inside AMD OVERCLOCKING enabled, else FIT was autocorrecting the voltage you set and ignore it fully
(a long story with buggy Dynamic FCLK & Dynamic SOC)

Another thing is that you run tRAS+2.
If you want to move inside JEDEC's range, you need to use +4 for SR ~ or don' follow it and run tRCD+tRCD (28)
tRC "technically optimally" would remain that 32+tRP.
That under *8 multiplier from my anchor's would be 368-273-168, with tWR 16 (8.421111....to the infinite)

But JEDEC up to which revision out of the 30+ , you refer to - doesn't always define what has to work.
It's not recommend to follow it like a holy book. Especially when this holy book had over 30 revisions 

I'm also a bit conflicted with your tWRRD & tWTR set
4-12 should run, but i can't recommend stuff blindly without double-testing SD,DD relationship here.
Try to get it stable under SLC 4-4 , with your current setting and bump up tRRD & tWTR (5-14) , till you have something that passes at least 20 cycles TM5
(or anything that takes longer than 1h to test ~ soo you hit thermal equilibrium & still have a full cycle to test)

RTT 7/0/6 is a bit special
Combine it please with tCKE 9
It does work also for Matisse, but CAD_BUS SETUP timings could missmatch
I think what you surely want, is to drop VDDG IOD a bit near that 1v range or even 950mV with procODT max 32ohm
32ohm shouldn't allow you to run VDDG IOD to 950mV but 28ohm will !
ClkDrvStr doesn't care about it, you can keep running 40 or 60ohm there ~ just have in your backhead, that it is a (A) multiplier , soo if you want to increase RTT_PARK strengthness for example /6 or /5, lower it down to 40ohm instead of 60 (for single rank) . Or lower VDIMM down 

About Matisse,
24-20-20-24 is what works , similar for Zen 1
24-20-24-24 should be used on lower quality PCBs to prevent cold boot issues, but higher than 24 is not needed on any board for Matisse and lower
30-20-20-24 is fine, same as 40-20-20-24 is fine
60-20-20-24 is a bit conflicting but can work out , it's just a bit harsh . You may need 60-20-20-20, but you'll figure it out

SOC beyond 1.1v here has bad effects and increases procODT requirements.
Up till 1.15v is usually the range after when negative scaling begins
But i want to remind, that 1900 FCLK on Matisse was hard and it still suffered from bad signal integrity ranges
Soo lower procODT = higher FCLK (1900 lock, but 1900 didn't run on every CPU)
Focus on that 28ohm range, and stay at 900mV cLDO_VDDP
950mV is not fine with 28ohm proc, same as beyond 1.1v is not fine with it.
1900 FCLK bruteforce settings are 32ohm proc, 950-1050-1100-1150 (cLDO_VDDP, VDDG CCD , VDDG IOD, VSOC [GET])
* stepping on Matisse was 50mV on stock or 75mV on extreme bruteforce settings
More about it here:








OC'ing T-Force 4133 cl18


I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...




www.overclock.net




Buttom part of the message
AMDs minimum limits are 42-43mV (ty The Stilt) , but you want to have at least 48mV difference between the GET settings between VDDP, VDDG and VSOC


lmfodor said:


> @RonLazer you did it! Of cuurse I need to run more test, but the big issue I guess was the TWR to slow. Reading Veii's post for last year I found that tWR is 8ns and to calculate it we should use freq * 8/2000, so 3800*8/2000 is 15.2 but should be an even number. so 16 did the work. And tRFC / tWR, 252/16 is 15.75ns.


I have a bit of an issue with anytype of "fixed real world timed" values
There was a ruleset out there spreading on the Intel MemOC thread, about tWR being a 8ns value as absolute minimum
This can not work. Memory is logarithmic and works on integers
No real world timed value is correct - as it scales up and down depending on set MCLK and the Command Rate state (PowerDown and GDM rounding included)

This is not optimal, and i strongly try to skip math that considers any type of fixed ns value. This can not work and won't work.
Rounding decimal numbers is also not optimal, same as focusing on fixed ns tRFC value is strongly not considerable
Been through this, and one of the reasons that tRFC mini module exists

Technically tRAS + XYZ (4,8) or tRC+1,2,4,8
used as integer values of tRC as a whole (half cycle, 1/8th of a cycle and so on) - was an option for stability and matching up things.
But it's also not optimal to do math that way
No XYZ + fixed ns value , is optimal
It works when you use added "memory timing" value, as it will turn at the end still to a .xxxxxxx (11 decimals) value
But if we speak about ns math, that's not a good method
Every little rounding stacks ~ beginning with board manufactures and IMC firmware developer rounding 3733.33333333337 MT/s, values
The math breaks, the more you round and tRFC 2 and 4 do fully break if you do it with the /1.346 & /2.1875 math
* reason why tRFC mini module exists, against Yuri's DRAM Calculator method, it always got tRFC2 & 4 wrong but it wasn't his fault but the user who inputs the wrong ns value
Even the windows calculator doesn't function beyond 11 decimals, while google docs ends at 13 decimals

I need to sit with you and write a book about everything that's wrong with how we scale MCLK and boards predict values
But trust me that a lot of thought went into "tRFC Mini" , and the way that it functions at version v2.31. It had undergone many revisions since v0.1 & yet is not perfect, because i can not generate tSTAG out of thin air, to match it better & have no statistic range for temperature to ns delay failure.

We'll talk someday about the reason i abandoned fully anything JEDEC related.
Because this holy book did not follow reality
A fantastic description was this post by an older dram engineer








How to calculate tRC timing in cycles?


Hi. I was looking for some additional ram for my aging desktop PC and tried to find modules that match the timings perfectly. At first I thought I found a perfect match with some Kingston modules, but on a closer look things are a bit weird. Wikipedia, among other sources states that tRC =...




www.overclock.net




137,438,953,472 memory cells won't always follow perfect tRC (tRAS+tRP) math, it's not possible to follow it blindly
But it's still a good indicator if the "transition" is "clean" or not, on a users set ~ or it needs work somewhere else, as tRC added delay does mask issues 
* need to answer Ron too, but it requires another big wall of text, soo someday later 


ManniX-ITA said:


> What do you think about running ClkDrvStr at 120 Ohm?


Not such a good idea
I mean it runs, but this combined with high voltage beyond 1.6 - i don't know what to think about it

Like mentioned a bit further up on the post,
AMD did something to their IMC firmware since 1201 and 1202.
I move between RTT_PARK /7 and /Disabled right now ~ instead of 6/3/6
But still face issues. They 100% did something with RZQ , but i can not achieve stability yet
Soo i can not say much more right now. I think some hidden CBS value changed, considering over 5% IPC bump & if i load my old profiles - it disables 4 of my USB 3.0 ports
Also considering something adds 0.5ns to it (L3 cache stayed the same no change there, but Geekbench reports 5-23% improvement ~ single and multi)

Overall if you use high ClkDrvStr
Lower RTT_PARK and RTT_NOM,
CKE high & CKE low will move differently and be more bursty
Any impedance value acts as a current multiplier , even if it's used as termination impedance (acts as resistance)

VDIMM, ClkDrvStr, procODT, and RTT_PARK go hand in hand
They need balancing
tCKE and SETUP timings are just control options, but i couldn't find something usable at 4200MT/s yet. It doesn't work well with DynamicODT (RTT_WR)
But tCKE does still work well, soo that's a plus point 


ManniX-ITA said:


> I managed to run my DR kit at 1T without setup timings.
> Only using this crazy high ClkDrvStr; but the RTT and ProcODT is very mild.


Dual Rank dimms can run 60-120, that's fine
but it's not soo fine for 8gb single rank


----------



## Veii

lmfodor said:


> Hi , I would like to know if any of you are using any High Performance Plan by BIOS. I´m actually using SMU 56.45 and I want to lower some version to try above 4000 Freq without WHEAs. I read from Veii that Patch B, not C, would perform well abobe 4000 Freq. Some time ago I read a post from 1Usmus that recommended certain parameters in the BIOS and since I am optimizing my memory overclocking I would like to know if any of these parameters could help or perhaps thet are complicating my OC . Among them I had set these options:
> 
> 
> *Global C-state Control = Enabled* (Advanced\AMD CBS). I set ti to disable to prevent Reboots under idle. However I was reading that rising IOD Voltage above 1.05V would prevent reboots. Is that right?
> *DF CStates = Disabled* (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\DF Cstates = Disabled)
> This setting does not allow for Infinity Fabric to go to a low-power state when the processor has entered Cx states..
> *PPC Adjustment = PState 0*. Two settings below:
> (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\*APBDIS = 1
> AND*
> (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\*Fixed SOC Pstate = P0*)


Please don't take it as rude, if i give a bit of critique too this writeup 
All 3 options are strange and first two misunderstood

*Global C-States*, does allow the per-core c-states to function and dLDO to function (speedstep , nothing to do with suspended cores)
This means, it allows the cpu to go down to 550Mhz P3/P4 state
This is important to have it enabled.
In combination with CPPC , it allows windows to lower frequency on worse cores and accept dLDO_injector , to smooth the voltage differentiation between cores ~ where each of the little core modules


Spoiler: Single CCD Illustration












Credits for the shot to Fritzchen's Fritz AMD/Zen3/Ryzen/Vermeer | Flickr


It needs to be enabled, soo cores can adjust and Vermeer can adjust inside the powerbudget

*DF-States* are controlling the suspension and also the wake-up from hibernation , triggers the overboosting bug , which causes an "idle to wake-up" crash by badly designed powerplans from AMD & Microsoft, without Peak frequency boosts
This has to be disabled till it get's fixed on 1202 or 1202ABCD 
* i need to test if it's still an issue on 1202 , after figuring out what the hello kitty is wrong with RZQ and why IMC behaviour is now completely exotic and wrong/broken
~ after the PMTable rewrite & 3 new activated sensors inside FIT


Spoiler: Overboost issue illustration with DF-States












Whole Source








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Veii, what's the formula for correct tCKE? And what would be the optimal RTT values for 4 sticks of 8GB SR ? It's frequency dependent Each 200MT/s = +2 tCKE 3600 = 6/7 3800 = 9 4000 = 11 4200 = 13 Stock 3600 = 6, but 7 say my findings probably it goes in stepping's of 3 like CkeSetup Timing




www.overclock.net










lmfodor said:


> *PPC Adjustment = PState 0*. Two settings below:
> (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\*APBDIS = 1
> AND*
> (Advanced\AMD CBS\NBIO Common Options\SMU Common Options\*Fixed SOC Pstate = P0*)


This is what you described as Infinity Fabric Scaling "disabled"
It's on FW level disabled & does nothing from the surface viewpoint (maybe does something internally if you keep it functioning at misson-mode = 0)
and if you ask any engineer about Dynamic FCLK and variable SOC - they will cut the contact with you
I think this topic is under NDA , 4 engineers refused to answer and cut the chat after asking more about ABPDIS and why Dynamic FCLK is disabled internally

You can keep it at 0 mission mode
it won't function except for Renoir & Cezanne, which have STAMP control and are build upon this. Same for ryzen U & G series notebooks ~ there it functions
For Matisse and Vermeer it's disabled since mid of the lifespan of Matisse & Matisse has an 1900 FCLK lock - like Vermeer was attempted to get after Patch C, gladly this nonsense was stopped after Patch D


lmfodor said:


> Then DPM LCLK to 2-1-1-1-2-1-1-1


Before 1200 , soo 1191/1181 and lower, you can run this
1202 seems to set internally X-X-X-2-X-X-X-2
SMU debug shows on 1200 and lower that 2-1-X-X-2-1-X-X is used
One 600mhz link with one 300mhz one. Level 2 and Level 3 where not readable , but 2-2-1 was not accepted by SMU
Currently i test 2-1-1-2/2-1-1-2, as Level3/4 (the last link) is set at 600mhz and used (by FW alone, i had them at auto)
probably 2-1-1-2 could be good, but we'll see, test in progress AGESA 1.2.0.2 is awkward & did a lot of changes

The rest is fine
You can include opening PBO EDC to 400A
It still allows cache to boost till it gets internally limited
and should be reflective on SiSandra MCE , as also on Aida64
But lifting the EDC limit will need a limit on TDC , else it adds to much voltage for allcore and the CPU throttles back
This can be fixed by nearly maxed out negative CO with "lower" but positive vcore offset or just more droopy CPU LLC


----------



## Veii

KedarWolf said:


> View attachment 2489013
> 
> 
> View attachment 2489011
> 
> 
> 
> 
> Code:
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 176GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Average Inter-Thread Latency : 39.9ns (9.5ns - 61.4ns)
> Inter-Thread (same Core) Latency : 9.8ns
> Inter-Core (same Module) Latency : 21.0ns
> Inter-Module (same Package) Latency : 58.4ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5.5GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1716.17MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 3.80ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 707.05kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 36.22MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 0.08ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-M0C0T0 <> U2-M0C1T0 Data Latency : 22.2ns
> U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.6ns
> U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.1ns
> U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
> U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.4ns
> U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.8ns
> U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.5ns
> U0-M0C0T0 <> U16-M1C0T0 Data Latency : 56.9ns
> U0-M0C0T0 <> U18-M1C1T0 Data Latency : 56.6ns
> U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.9ns
> U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
> U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.0ns
> U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.5ns
> U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.1ns
> U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.1ns
> U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
> U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
> U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.5ns
> U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.0ns
> U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.8ns
> U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.5ns
> U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.8ns
> U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.5ns
> U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.9ns
> U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.4ns
> U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.9ns
> U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
> U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.0ns
> U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.5ns
> U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.1ns
> U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.1ns
> U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.2ns
> U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.8ns
> U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.7ns
> U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.4ns
> U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
> U2-M0C1T0 <> U14-M0C7T0 Data Latency : 21.0ns
> U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.8ns
> U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.0ns
> U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.1ns
> U2-M0C1T0 <> U22-M1C3T0 Data Latency : 60.9ns
> U2-M0C1T0 <> U24-M1C4T0 Data Latency : 61.0ns
> U2-M0C1T0 <> U26-M1C5T0 Data Latency : 60.8ns
> U2-M0C1T0 <> U28-M1C6T0 Data Latency : 60.5ns
> U2-M0C1T0 <> U30-M1C7T0 Data Latency : 60.3ns
> U2-M0C1T0 <> U1-M0C0T1 Data Latency : 22.2ns
> U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
> U2-M0C1T0 <> U5-M0C2T1 Data Latency : 21.9ns
> U2-M0C1T0 <> U7-M0C3T1 Data Latency : 23.0ns
> U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
> U2-M0C1T0 <> U11-M0C5T1 Data Latency : 22.3ns
> U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.6ns
> U2-M0C1T0 <> U15-M0C7T1 Data Latency : 21.8ns
> U2-M0C1T0 <> U17-M1C0T1 Data Latency : 61.4ns
> U2-M0C1T0 <> U19-M1C1T1 Data Latency : 61.1ns
> U2-M0C1T0 <> U21-M1C2T1 Data Latency : 61.2ns
> U2-M0C1T0 <> U23-M1C3T1 Data Latency : 60.9ns
> U2-M0C1T0 <> U25-M1C4T1 Data Latency : 61.1ns
> U2-M0C1T0 <> U27-M1C5T1 Data Latency : 60.8ns
> U2-M0C1T0 <> U29-M1C6T1 Data Latency : 60.5ns
> U2-M0C1T0 <> U31-M1C7T1 Data Latency : 60.3ns
> U4-M0C2T0 <> U6-M0C3T0 Data Latency : 21.3ns
> U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.6ns
> U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
> U4-M0C2T0 <> U12-M0C6T0 Data Latency : 19.9ns
> U4-M0C2T0 <> U14-M0C7T0 Data Latency : 19.8ns
> U4-M0C2T0 <> U16-M1C0T0 Data Latency : 60.3ns
> U4-M0C2T0 <> U18-M1C1T0 Data Latency : 60.7ns
> U4-M0C2T0 <> U20-M1C2T0 Data Latency : 60.2ns
> U4-M0C2T0 <> U22-M1C3T0 Data Latency : 60.6ns
> U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.7ns
> U4-M0C2T0 <> U26-M1C5T0 Data Latency : 60.4ns
> U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.6ns
> U4-M0C2T0 <> U30-M1C7T0 Data Latency : 60.0ns
> U4-M0C2T0 <> U1-M0C0T1 Data Latency : 22.0ns
> U4-M0C2T0 <> U3-M0C1T1 Data Latency : 22.2ns
> U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
> U4-M0C2T0 <> U7-M0C3T1 Data Latency : 21.2ns
> U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.6ns
> U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.5ns
> U4-M0C2T0 <> U13-M0C6T1 Data Latency : 19.9ns
> U4-M0C2T0 <> U15-M0C7T1 Data Latency : 19.8ns
> U4-M0C2T0 <> U17-M1C0T1 Data Latency : 60.4ns
> U4-M0C2T0 <> U19-M1C1T1 Data Latency : 60.8ns
> U4-M0C2T0 <> U21-M1C2T1 Data Latency : 60.1ns
> U4-M0C2T0 <> U23-M1C3T1 Data Latency : 60.5ns
> U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.7ns
> U4-M0C2T0 <> U27-M1C5T1 Data Latency : 60.4ns
> U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.6ns
> U4-M0C2T0 <> U31-M1C7T1 Data Latency : 60.1ns
> U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
> U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.7ns
> U6-M0C3T0 <> U12-M0C6T0 Data Latency : 19.9ns
> U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.1ns
> U6-M0C3T0 <> U16-M1C0T0 Data Latency : 61.1ns
> U6-M0C3T0 <> U18-M1C1T0 Data Latency : 60.9ns
> U6-M0C3T0 <> U20-M1C2T0 Data Latency : 60.9ns
> U6-M0C3T0 <> U22-M1C3T0 Data Latency : 60.4ns
> U6-M0C3T0 <> U24-M1C4T0 Data Latency : 60.4ns
> U6-M0C3T0 <> U26-M1C5T0 Data Latency : 60.5ns
> U6-M0C3T0 <> U28-M1C6T0 Data Latency : 60.2ns
> U6-M0C3T0 <> U30-M1C7T0 Data Latency : 60.1ns
> U6-M0C3T0 <> U1-M0C0T1 Data Latency : 21.9ns
> U6-M0C3T0 <> U3-M0C1T1 Data Latency : 23.2ns
> U6-M0C3T0 <> U5-M0C2T1 Data Latency : 21.4ns
> U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
> U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
> U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.7ns
> U6-M0C3T0 <> U13-M0C6T1 Data Latency : 19.9ns
> U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.2ns
> U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.0ns
> U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.0ns
> U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.3ns
> U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
> U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.0ns
> U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.2ns
> U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.6ns
> U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.3ns
> U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.0ns
> U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.8ns
> U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.7ns
> U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
> U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.2ns
> U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.0ns
> U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.8ns
> U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.6ns
> U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.4ns
> U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.9ns
> U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.8ns
> U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.7ns
> U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.9ns
> U8-M0C4T0 <> U5-M0C2T1 Data Latency : 21.8ns
> U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
> U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
> U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.0ns
> U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.9ns
> U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.7ns
> U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.7ns
> U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.2ns
> U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.9ns
> U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.8ns
> U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.6ns
> U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.4ns
> U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.8ns
> U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.7ns
> U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.7ns
> U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.7ns
> U10-M0C5T0 <> U16-M1C0T0 Data Latency : 57.4ns
> U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.1ns
> U10-M0C5T0 <> U20-M1C2T0 Data Latency : 57.6ns
> U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.8ns
> U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.4ns
> U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.3ns
> U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.9ns
> U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.2ns
> U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.3ns
> U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.9ns
> U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
> U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.5ns
> U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
> U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.8ns
> U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.7ns
> U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.7ns
> U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.4ns
> U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.2ns
> U10-M0C5T0 <> U21-M1C2T1 Data Latency : 57.6ns
> U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.6ns
> U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.4ns
> U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
> U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.8ns
> U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.3ns
> U12-M0C6T0 <> U14-M0C7T0 Data Latency : 22.4ns
> U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.4ns
> U12-M0C6T0 <> U18-M1C1T0 Data Latency : 57.8ns
> U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.5ns
> U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.7ns
> U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.1ns
> U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.0ns
> U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.7ns
> U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.8ns
> U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.6ns
> U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
> U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
> U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.9ns
> U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.8ns
> U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.9ns
> U12-M0C6T0 <> U15-M0C7T1 Data Latency : 22.5ns
> U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.4ns
> U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.0ns
> U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.5ns
> U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.6ns
> U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.1ns
> U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.0ns
> U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.7ns
> U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.7ns
> U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.0ns
> U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.6ns
> U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.1ns
> U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.1ns
> U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.1ns
> U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
> U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.6ns
> U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
> U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.6ns
> U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.8ns
> U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.3ns
> U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.4ns
> U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.7ns
> U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.9ns
> U14-M0C7T0 <> U13-M0C6T1 Data Latency : 22.3ns
> U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
> U14-M0C7T0 <> U17-M1C0T1 Data Latency : 57.9ns
> U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.5ns
> U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.1ns
> U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.2ns
> U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.0ns
> U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.5ns
> U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.5ns
> U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
> U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.2ns
> U16-M1C0T0 <> U20-M1C2T0 Data Latency : 20.0ns
> U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.7ns
> U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.9ns
> U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.3ns
> U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
> U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.5ns
> U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.1ns
> U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.9ns
> U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.0ns
> U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.4ns
> U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.6ns
> U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.6ns
> U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.2ns
> U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.0ns
> U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
> U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.2ns
> U16-M1C0T0 <> U21-M1C2T1 Data Latency : 20.1ns
> U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.7ns
> U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.9ns
> U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.3ns
> U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
> U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
> U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.9ns
> U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.9ns
> U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.7ns
> U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.5ns
> U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.5ns
> U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.4ns
> U18-M1C1T0 <> U1-M0C0T1 Data Latency : 56.1ns
> U18-M1C1T0 <> U3-M0C1T1 Data Latency : 56.8ns
> U18-M1C1T0 <> U5-M0C2T1 Data Latency : 56.9ns
> U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
> U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.0ns
> U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.1ns
> U18-M1C1T0 <> U13-M0C6T1 Data Latency : 57.7ns
> U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.3ns
> U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.2ns
> U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
> U18-M1C1T0 <> U21-M1C2T1 Data Latency : 18.9ns
> U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.9ns
> U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.7ns
> U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.5ns
> U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.4ns
> U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.4ns
> U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
> U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.6ns
> U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.4ns
> U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.0ns
> U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.1ns
> U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.1ns
> U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.7ns
> U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.4ns
> U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.6ns
> U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.7ns
> U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
> U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.3ns
> U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.2ns
> U20-M1C2T0 <> U17-M1C0T1 Data Latency : 20.1ns
> U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
> U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
> U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
> U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.6ns
> U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.4ns
> U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.0ns
> U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.1ns
> U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.4ns
> U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.3ns
> U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.0ns
> U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.9ns
> U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.0ns
> U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.7ns
> U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.4ns
> U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.7ns
> U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.6ns
> U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.9ns
> U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
> U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.1ns
> U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.6ns
> U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.0ns
> U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.4ns
> U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.8ns
> U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.4ns
> U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.3ns
> U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
> U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.9ns
> U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.2ns
> U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
> U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.9ns
> U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.9ns
> U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.3ns
> U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.1ns
> U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.3ns
> U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
> U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.3ns
> U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.1ns
> U24-M1C4T0 <> U17-M1C0T1 Data Latency : 21.1ns
> U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.8ns
> U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.7ns
> U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.5ns
> U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
> U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.3ns
> U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
> U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.9ns
> U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.6ns
> U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.7ns
> U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.4ns
> U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U5-M0C2T1 Data Latency : 57.9ns
> U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.3ns
> U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.9ns
> U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.7ns
> U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.3ns
> U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
> U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.3ns
> U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
> U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
> U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.6ns
> U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.7ns
> U28-M1C6T0 <> U30-M1C7T0 Data Latency : 22.3ns
> U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.4ns
> U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
> U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.8ns
> U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
> U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.9ns
> U28-M1C6T0 <> U11-M0C5T1 Data Latency : 59.2ns
> U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.6ns
> U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.5ns
> U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
> U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
> U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
> U28-M1C6T0 <> U23-M1C3T1 Data Latency : 21.1ns
> U28-M1C6T0 <> U25-M1C4T1 Data Latency : 23.0ns
> U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.7ns
> U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
> U28-M1C6T0 <> U31-M1C7T1 Data Latency : 22.3ns
> U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.0ns
> U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.4ns
> U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.4ns
> U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
> U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.6ns
> U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.5ns
> U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.2ns
> U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.6ns
> U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.6ns
> U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.1ns
> U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.2ns
> U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.9ns
> U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.0ns
> U30-M1C7T0 <> U29-M1C6T1 Data Latency : 22.2ns
> U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
> U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.4ns
> U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.2ns
> U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.9ns
> U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.6ns
> U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.2ns
> U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.5ns
> U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.5ns
> U1-M0C0T1 <> U17-M1C0T1 Data Latency : 56.9ns
> U1-M0C0T1 <> U19-M1C1T1 Data Latency : 56.3ns
> U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.0ns
> U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
> U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.9ns
> U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.6ns
> U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.3ns
> U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.9ns
> U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.4ns
> U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.3ns
> U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
> U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.8ns
> U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.8ns
> U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.7ns
> U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.0ns
> U3-M0C1T1 <> U19-M1C1T1 Data Latency : 56.8ns
> U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.2ns
> U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.2ns
> U3-M0C1T1 <> U25-M1C4T1 Data Latency : 57.8ns
> U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.7ns
> U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.7ns
> U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.1ns
> U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
> U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.7ns
> U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
> U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.3ns
> U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.3ns
> U5-M0C2T1 <> U17-M1C0T1 Data Latency : 57.3ns
> U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.2ns
> U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.4ns
> U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
> U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.2ns
> U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.3ns
> U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
> U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.6ns
> U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
> U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.6ns
> U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.3ns
> U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.2ns
> U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.0ns
> U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.1ns
> U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.1ns
> U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
> U7-M0C3T1 <> U25-M1C4T1 Data Latency : 57.9ns
> U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.1ns
> U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.7ns
> U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.2ns
> U9-M0C4T1 <> U11-M0C5T1 Data Latency : 21.0ns
> U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.9ns
> U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.7ns
> U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.7ns
> U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.3ns
> U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.0ns
> U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.8ns
> U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.6ns
> U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.9ns
> U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.9ns
> U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.7ns
> U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.7ns
> U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.4ns
> U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.3ns
> U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.6ns
> U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.8ns
> U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.5ns
> U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.9ns
> U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.4ns
> U13-M0C6T1 <> U15-M0C7T1 Data Latency : 22.9ns
> U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.9ns
> U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
> U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.6ns
> U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.0ns
> U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.0ns
> U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.7ns
> U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.8ns
> U15-M0C7T1 <> U17-M1C0T1 Data Latency : 57.9ns
> U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.6ns
> U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.1ns
> U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.2ns
> U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.0ns
> U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.6ns
> U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.5ns
> U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.2ns
> U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.2ns
> U17-M1C0T1 <> U21-M1C2T1 Data Latency : 20.0ns
> U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.7ns
> U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.9ns
> U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.4ns
> U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
> U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
> U19-M1C1T1 <> U21-M1C2T1 Data Latency : 18.9ns
> U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.9ns
> U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.7ns
> U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.5ns
> U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.4ns
> U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.4ns
> U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
> U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.6ns
> U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.4ns
> U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.0ns
> U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.1ns
> U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.4ns
> U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.3ns
> U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.0ns
> U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.0ns
> U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
> U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
> U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.9ns
> U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.6ns
> U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.7ns
> U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.2ns
> 1x 64bytes Blocks Bandwidth : 26GB/s
> 4x 64bytes Blocks Bandwidth : 28.76GB/s
> 4x 256bytes Blocks Bandwidth : 96.46GB/s
> 4x 1kB Blocks Bandwidth : 321.1GB/s
> 4x 4kB Blocks Bandwidth : 507GB/s
> 16x 4kB Blocks Bandwidth : 726.56GB/s
> 4x 64kB Blocks Bandwidth : 995.61GB/s
> 16x 64kB Blocks Bandwidth : 598.29GB/s
> 8x 256kB Blocks Bandwidth : 602.17GB/s
> 4x 1MB Blocks Bandwidth : 608.9GB/s
> 16x 1MB Blocks Bandwidth : 24.7GB/s
> 8x 4MB Blocks Bandwidth : 19.17GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : A20F10-1009
> Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
> Platform Compliance : x64
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> URL : https://www.amd.com
> Speed : 5GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 8 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : A20F10-1009
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


I wish the links to the 2nd CCD wouldn't be that low - AMD likely can bump them up
But 9.8ns Inter-Thread Latency is quite awesome 









Just if they would finally unlock PBO Override beyond 200mhz :/
* test was between Windows 10 ProWorkstation Ultimate-Perf Powerplan & Balanced AMD with the slider to the right
** lost my own Plan but the red line is the balanced, which shows improvement on cache-boost ~ when you have more boosting reserves, as other cores slow down by c-state generation
Result could be way better if DF-States where not broken 

I do feel like you can unleash the EDC limiter
Cache seems to throttle a bit for you
Also thanks to your MDL Optimize Offline guide @KedarWolf
Combined with GitHub - DrEmpiricism/ConvertTo-PfW: Windows 10 Home to Windows 10 Pro for Workstations converter.
It works quite well 
* just need to use NTLite (free) for iso creation, as .esd encrypts and the old decrypter - has disabled servers 
Was playing with 21H1, but maan you have 100+ windows autorun services added to it ~ it's really bad
But without them (autoruns.exe) it wasn't even bad ~ tho ProWorkstation seems to have a subtle better thread scheduler


----------



## lmfodor

KedarWolf said:


> View attachment 2489013
> 
> 
> View attachment 2489011
> 
> 
> 
> 
> Code:
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 176GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Average Inter-Thread Latency : 39.9ns (9.5ns - 61.4ns)
> Inter-Thread (same Core) Latency : 9.8ns
> Inter-Core (same Module) Latency : 21.0ns
> Inter-Module (same Package) Latency : 58.4ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5.5GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1716.17MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 3.80ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 707.05kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 36.22MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 0.08ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-M0C0T0 <> U2-M0C1T0 Data Latency : 22.2ns
> U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.6ns
> U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.1ns
> U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
> U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.4ns
> U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.8ns
> U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.5ns
> U0-M0C0T0 <> U16-M1C0T0 Data Latency : 56.9ns
> U0-M0C0T0 <> U18-M1C1T0 Data Latency : 56.6ns
> U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.9ns
> U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
> U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.0ns
> U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.5ns
> U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.1ns
> U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.1ns
> U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
> U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
> U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.5ns
> U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.0ns
> U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.8ns
> U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.5ns
> U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.8ns
> U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.5ns
> U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.9ns
> U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.4ns
> U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.9ns
> U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
> U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.0ns
> U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.5ns
> U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.1ns
> U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.1ns
> U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.2ns
> U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.8ns
> U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.7ns
> U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.4ns
> U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
> U2-M0C1T0 <> U14-M0C7T0 Data Latency : 21.0ns
> U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.8ns
> U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.0ns
> U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.1ns
> U2-M0C1T0 <> U22-M1C3T0 Data Latency : 60.9ns
> U2-M0C1T0 <> U24-M1C4T0 Data Latency : 61.0ns
> U2-M0C1T0 <> U26-M1C5T0 Data Latency : 60.8ns
> U2-M0C1T0 <> U28-M1C6T0 Data Latency : 60.5ns
> U2-M0C1T0 <> U30-M1C7T0 Data Latency : 60.3ns
> U2-M0C1T0 <> U1-M0C0T1 Data Latency : 22.2ns
> U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
> U2-M0C1T0 <> U5-M0C2T1 Data Latency : 21.9ns
> U2-M0C1T0 <> U7-M0C3T1 Data Latency : 23.0ns
> U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
> U2-M0C1T0 <> U11-M0C5T1 Data Latency : 22.3ns
> U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.6ns
> U2-M0C1T0 <> U15-M0C7T1 Data Latency : 21.8ns
> U2-M0C1T0 <> U17-M1C0T1 Data Latency : 61.4ns
> U2-M0C1T0 <> U19-M1C1T1 Data Latency : 61.1ns
> U2-M0C1T0 <> U21-M1C2T1 Data Latency : 61.2ns
> U2-M0C1T0 <> U23-M1C3T1 Data Latency : 60.9ns
> U2-M0C1T0 <> U25-M1C4T1 Data Latency : 61.1ns
> U2-M0C1T0 <> U27-M1C5T1 Data Latency : 60.8ns
> U2-M0C1T0 <> U29-M1C6T1 Data Latency : 60.5ns
> U2-M0C1T0 <> U31-M1C7T1 Data Latency : 60.3ns
> U4-M0C2T0 <> U6-M0C3T0 Data Latency : 21.3ns
> U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.6ns
> U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
> U4-M0C2T0 <> U12-M0C6T0 Data Latency : 19.9ns
> U4-M0C2T0 <> U14-M0C7T0 Data Latency : 19.8ns
> U4-M0C2T0 <> U16-M1C0T0 Data Latency : 60.3ns
> U4-M0C2T0 <> U18-M1C1T0 Data Latency : 60.7ns
> U4-M0C2T0 <> U20-M1C2T0 Data Latency : 60.2ns
> U4-M0C2T0 <> U22-M1C3T0 Data Latency : 60.6ns
> U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.7ns
> U4-M0C2T0 <> U26-M1C5T0 Data Latency : 60.4ns
> U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.6ns
> U4-M0C2T0 <> U30-M1C7T0 Data Latency : 60.0ns
> U4-M0C2T0 <> U1-M0C0T1 Data Latency : 22.0ns
> U4-M0C2T0 <> U3-M0C1T1 Data Latency : 22.2ns
> U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
> U4-M0C2T0 <> U7-M0C3T1 Data Latency : 21.2ns
> U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.6ns
> U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.5ns
> U4-M0C2T0 <> U13-M0C6T1 Data Latency : 19.9ns
> U4-M0C2T0 <> U15-M0C7T1 Data Latency : 19.8ns
> U4-M0C2T0 <> U17-M1C0T1 Data Latency : 60.4ns
> U4-M0C2T0 <> U19-M1C1T1 Data Latency : 60.8ns
> U4-M0C2T0 <> U21-M1C2T1 Data Latency : 60.1ns
> U4-M0C2T0 <> U23-M1C3T1 Data Latency : 60.5ns
> U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.7ns
> U4-M0C2T0 <> U27-M1C5T1 Data Latency : 60.4ns
> U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.6ns
> U4-M0C2T0 <> U31-M1C7T1 Data Latency : 60.1ns
> U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
> U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.7ns
> U6-M0C3T0 <> U12-M0C6T0 Data Latency : 19.9ns
> U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.1ns
> U6-M0C3T0 <> U16-M1C0T0 Data Latency : 61.1ns
> U6-M0C3T0 <> U18-M1C1T0 Data Latency : 60.9ns
> U6-M0C3T0 <> U20-M1C2T0 Data Latency : 60.9ns
> U6-M0C3T0 <> U22-M1C3T0 Data Latency : 60.4ns
> U6-M0C3T0 <> U24-M1C4T0 Data Latency : 60.4ns
> U6-M0C3T0 <> U26-M1C5T0 Data Latency : 60.5ns
> U6-M0C3T0 <> U28-M1C6T0 Data Latency : 60.2ns
> U6-M0C3T0 <> U30-M1C7T0 Data Latency : 60.1ns
> U6-M0C3T0 <> U1-M0C0T1 Data Latency : 21.9ns
> U6-M0C3T0 <> U3-M0C1T1 Data Latency : 23.2ns
> U6-M0C3T0 <> U5-M0C2T1 Data Latency : 21.4ns
> U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
> U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
> U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.7ns
> U6-M0C3T0 <> U13-M0C6T1 Data Latency : 19.9ns
> U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.2ns
> U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.0ns
> U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.0ns
> U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.3ns
> U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
> U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.0ns
> U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.2ns
> U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.6ns
> U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.3ns
> U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.0ns
> U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.8ns
> U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.7ns
> U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
> U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.2ns
> U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.0ns
> U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.8ns
> U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.6ns
> U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.4ns
> U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.9ns
> U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.8ns
> U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.7ns
> U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.9ns
> U8-M0C4T0 <> U5-M0C2T1 Data Latency : 21.8ns
> U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
> U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
> U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.0ns
> U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.9ns
> U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.7ns
> U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.7ns
> U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.2ns
> U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.9ns
> U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.8ns
> U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.6ns
> U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.4ns
> U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.8ns
> U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.7ns
> U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.7ns
> U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.7ns
> U10-M0C5T0 <> U16-M1C0T0 Data Latency : 57.4ns
> U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.1ns
> U10-M0C5T0 <> U20-M1C2T0 Data Latency : 57.6ns
> U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.8ns
> U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.4ns
> U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.3ns
> U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.9ns
> U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.2ns
> U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.3ns
> U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.9ns
> U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
> U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.5ns
> U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
> U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.8ns
> U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.7ns
> U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.7ns
> U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.4ns
> U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.2ns
> U10-M0C5T0 <> U21-M1C2T1 Data Latency : 57.6ns
> U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.6ns
> U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.4ns
> U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
> U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.8ns
> U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.3ns
> U12-M0C6T0 <> U14-M0C7T0 Data Latency : 22.4ns
> U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.4ns
> U12-M0C6T0 <> U18-M1C1T0 Data Latency : 57.8ns
> U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.5ns
> U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.7ns
> U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.1ns
> U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.0ns
> U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.7ns
> U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.8ns
> U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.6ns
> U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
> U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
> U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.9ns
> U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.8ns
> U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.9ns
> U12-M0C6T0 <> U15-M0C7T1 Data Latency : 22.5ns
> U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.4ns
> U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.0ns
> U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.5ns
> U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.6ns
> U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.1ns
> U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.0ns
> U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.7ns
> U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.7ns
> U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.0ns
> U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.6ns
> U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.1ns
> U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.1ns
> U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.1ns
> U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
> U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.6ns
> U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
> U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.6ns
> U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.8ns
> U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.3ns
> U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.4ns
> U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.7ns
> U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.9ns
> U14-M0C7T0 <> U13-M0C6T1 Data Latency : 22.3ns
> U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
> U14-M0C7T0 <> U17-M1C0T1 Data Latency : 57.9ns
> U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.5ns
> U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.1ns
> U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.2ns
> U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.0ns
> U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.5ns
> U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.5ns
> U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
> U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.2ns
> U16-M1C0T0 <> U20-M1C2T0 Data Latency : 20.0ns
> U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.7ns
> U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.9ns
> U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.3ns
> U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
> U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.5ns
> U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.1ns
> U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.9ns
> U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.0ns
> U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.4ns
> U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.6ns
> U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.6ns
> U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.2ns
> U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.0ns
> U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
> U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.2ns
> U16-M1C0T0 <> U21-M1C2T1 Data Latency : 20.1ns
> U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.7ns
> U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.9ns
> U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.3ns
> U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
> U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
> U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.9ns
> U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.9ns
> U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.7ns
> U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.5ns
> U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.5ns
> U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.4ns
> U18-M1C1T0 <> U1-M0C0T1 Data Latency : 56.1ns
> U18-M1C1T0 <> U3-M0C1T1 Data Latency : 56.8ns
> U18-M1C1T0 <> U5-M0C2T1 Data Latency : 56.9ns
> U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
> U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.0ns
> U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.1ns
> U18-M1C1T0 <> U13-M0C6T1 Data Latency : 57.7ns
> U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.3ns
> U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.2ns
> U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
> U18-M1C1T0 <> U21-M1C2T1 Data Latency : 18.9ns
> U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.9ns
> U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.7ns
> U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.5ns
> U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.4ns
> U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.4ns
> U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
> U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.6ns
> U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.4ns
> U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.0ns
> U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.1ns
> U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.1ns
> U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.7ns
> U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.4ns
> U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.6ns
> U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.7ns
> U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
> U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.3ns
> U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.2ns
> U20-M1C2T0 <> U17-M1C0T1 Data Latency : 20.1ns
> U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
> U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
> U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
> U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.6ns
> U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.4ns
> U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.0ns
> U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.1ns
> U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.4ns
> U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.3ns
> U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.0ns
> U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.9ns
> U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.0ns
> U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.7ns
> U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.4ns
> U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.7ns
> U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.6ns
> U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.9ns
> U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
> U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.1ns
> U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.6ns
> U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.0ns
> U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.4ns
> U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.8ns
> U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.4ns
> U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.3ns
> U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
> U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.9ns
> U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.2ns
> U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
> U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.9ns
> U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.9ns
> U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.3ns
> U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.1ns
> U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.3ns
> U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
> U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.3ns
> U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.1ns
> U24-M1C4T0 <> U17-M1C0T1 Data Latency : 21.1ns
> U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.8ns
> U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.7ns
> U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.5ns
> U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
> U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.3ns
> U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
> U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.9ns
> U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.6ns
> U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.7ns
> U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.4ns
> U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U5-M0C2T1 Data Latency : 57.9ns
> U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.3ns
> U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.9ns
> U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.7ns
> U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.3ns
> U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
> U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.3ns
> U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
> U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
> U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.6ns
> U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.7ns
> U28-M1C6T0 <> U30-M1C7T0 Data Latency : 22.3ns
> U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.4ns
> U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
> U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.8ns
> U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
> U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.9ns
> U28-M1C6T0 <> U11-M0C5T1 Data Latency : 59.2ns
> U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.6ns
> U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.5ns
> U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
> U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
> U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
> U28-M1C6T0 <> U23-M1C3T1 Data Latency : 21.1ns
> U28-M1C6T0 <> U25-M1C4T1 Data Latency : 23.0ns
> U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.7ns
> U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
> U28-M1C6T0 <> U31-M1C7T1 Data Latency : 22.3ns
> U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.0ns
> U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.4ns
> U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.4ns
> U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
> U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.6ns
> U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.5ns
> U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.2ns
> U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.6ns
> U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.6ns
> U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.1ns
> U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.2ns
> U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.9ns
> U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.0ns
> U30-M1C7T0 <> U29-M1C6T1 Data Latency : 22.2ns
> U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
> U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.4ns
> U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.2ns
> U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.9ns
> U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.6ns
> U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.2ns
> U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.5ns
> U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.5ns
> U1-M0C0T1 <> U17-M1C0T1 Data Latency : 56.9ns
> U1-M0C0T1 <> U19-M1C1T1 Data Latency : 56.3ns
> U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.0ns
> U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
> U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.9ns
> U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.6ns
> U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.3ns
> U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.9ns
> U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.4ns
> U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.3ns
> U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
> U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.8ns
> U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.8ns
> U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.7ns
> U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.0ns
> U3-M0C1T1 <> U19-M1C1T1 Data Latency : 56.8ns
> U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.2ns
> U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.2ns
> U3-M0C1T1 <> U25-M1C4T1 Data Latency : 57.8ns
> U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.7ns
> U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.7ns
> U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.1ns
> U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
> U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.7ns
> U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
> U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.3ns
> U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.3ns
> U5-M0C2T1 <> U17-M1C0T1 Data Latency : 57.3ns
> U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.2ns
> U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.4ns
> U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
> U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.2ns
> U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.3ns
> U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
> U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.6ns
> U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
> U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.6ns
> U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.3ns
> U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.2ns
> U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.0ns
> U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.1ns
> U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.1ns
> U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
> U7-M0C3T1 <> U25-M1C4T1 Data Latency : 57.9ns
> U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.1ns
> U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.7ns
> U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.2ns
> U9-M0C4T1 <> U11-M0C5T1 Data Latency : 21.0ns
> U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.9ns
> U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.7ns
> U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.7ns
> U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.3ns
> U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.0ns
> U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.8ns
> U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.6ns
> U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.9ns
> U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.9ns
> U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.7ns
> U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.7ns
> U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.4ns
> U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.3ns
> U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.6ns
> U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.8ns
> U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.5ns
> U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.9ns
> U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.4ns
> U13-M0C6T1 <> U15-M0C7T1 Data Latency : 22.9ns
> U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.9ns
> U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
> U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.6ns
> U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.0ns
> U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.0ns
> U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.7ns
> U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.8ns
> U15-M0C7T1 <> U17-M1C0T1 Data Latency : 57.9ns
> U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.6ns
> U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.1ns
> U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.2ns
> U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.0ns
> U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.6ns
> U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.5ns
> U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.2ns
> U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.2ns
> U17-M1C0T1 <> U21-M1C2T1 Data Latency : 20.0ns
> U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.7ns
> U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.9ns
> U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.4ns
> U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
> U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
> U19-M1C1T1 <> U21-M1C2T1 Data Latency : 18.9ns
> U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.9ns
> U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.7ns
> U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.5ns
> U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.4ns
> U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.4ns
> U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
> U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.6ns
> U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.4ns
> U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.0ns
> U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.1ns
> U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.4ns
> U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.3ns
> U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.0ns
> U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.0ns
> U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
> U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
> U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.9ns
> U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.6ns
> U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.7ns
> U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.2ns
> 1x 64bytes Blocks Bandwidth : 26GB/s
> 4x 64bytes Blocks Bandwidth : 28.76GB/s
> 4x 256bytes Blocks Bandwidth : 96.46GB/s
> 4x 1kB Blocks Bandwidth : 321.1GB/s
> 4x 4kB Blocks Bandwidth : 507GB/s
> 16x 4kB Blocks Bandwidth : 726.56GB/s
> 4x 64kB Blocks Bandwidth : 995.61GB/s
> 16x 64kB Blocks Bandwidth : 598.29GB/s
> 8x 256kB Blocks Bandwidth : 602.17GB/s
> 4x 1MB Blocks Bandwidth : 608.9GB/s
> 16x 1MB Blocks Bandwidth : 24.7GB/s
> 8x 4MB Blocks Bandwidth : 19.17GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : A20F10-1009
> Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
> Platform Compliance : x64
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> URL : https://www.amd.com
> Speed : 5GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 8 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : A20F10-1009
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.












Hi! I took it seriously the stress test, 41 cycles.. The truth is I was running an strange version of TM5 and I noticed that it only run 11 test, instead of the 15. So, even if I set 25 cycles, for some reason it continue to testing. No bad. But I will try again after a power off, capacitors discharge.. and try again.. Pretty stable.. And I think the best performance. The latency can go lower, I'm still running above 100 windows process after the last Sophia version.
Well, if you can and help to understand how you came to these values (tRAS, tRP, tWR and tRTP not aligned, an also why with soy low voltage (1.49) do you need so high ProcODT and high CklDvrStr). And last question, I read once time in a Yuri's Post where he talk about CTR, that mention that high vSOC and CPU LLC could cause degradation. It's safe to run so high vSOC for 3800 fcql? Thanks a lot! And also for sharing you vales. Works perfect for me.


----------



## KedarWolf

lmfodor said:


> View attachment 2489043
> 
> 
> Hi! I took it seriously the stress test, 41 cycles.. The truth is I was running an strange version of TM5 and I noticed that it only run 11 test, instead of the 15. So, even if I set 25 cycles, for some reason it continue to testing. No bad. But I will try again after a power off, capacitors discharge.. and try again.. Pretty stable.. And I think the best performance. The latency can go lower, I'm still running above 100 windows process after the last Sophia version.
> Well, if you can and help to understand how you came to these values (tRAS, tRP, tWR and tRTP not aligned, an also why with soy low voltage (1.49) do you need so high ProcODT and high CklDvrStr). And last question, I read once time in a Yuri's Post where he talk about CTR, that mention that high vSOC and CPU LLC could cause degradation. It's safe to run so high vSOC for 3800 fcql? Thanks a lot! And also for sharing you vales. Works perfect for me.


The 19-21 was suggested to me by someone and I find it a bit easier to get stable and a bit better in benchmarks. Technically it should be 21-21 but I find 19-21 benches a bit better. I changed the SCLs to 4 and lowered the ProODT to 40 and the ClkDrStr to 40, this passes TM5, SCLs at 2 doesn't. 1.2v on SoC is the highest I'll go but I've seen people running as high as 1.25v.

From what I understand 5000 series chips have good tolerance for higher voltages, it's 3000 series you want to keep lower.

Edit: I actually get a better score on AIDA64 and Sandra multi-core efficiency with SCLs at 4 instead of 2.


----------



## ManniX-ITA

KedarWolf said:


> The 19-21 was suggested to me by someone and I find it a bit easier to get stable and a bit better in benchmarks. Technically it should be 21-21 but I find 19-21 benches a bit better. I changed the SCLs to 4 and lowered the ProODT to 40 and the ClkDrStr to 40, this passes TM5, SCLs at 2 doesn't. 1.2v on SoC is the highest I'll go but I've seen people running as high as 1.25v.


I'm checking out but 19/21/42 doesn't work well with my kit, the latency gets errathic.
With a little bump in VDIMM works find with SCL at 2.

But my bandwidth in Sandra is way lower; did you do anything special? I'm on A22 instead of A21O.


----------



## KedarWolf

ManniX-ITA said:


> I'm checking out but 19/21/42 doesn't work well with my kit, the latency gets errathic.
> With a little bump in VDIMM works find with SCL at 2.
> 
> But my bandwidth in Sandra is way lower; did you do anything special? I'm on A22 instead of A21O.
> 
> View attachment 2489073


I'll test traditional instead of 19-21 for latency, but yeah, I change a lot of hidden things you can with A210. I won't be home from work for 8 hours or so though to test. 

Edit: I'll share my BIOS settings when I get home.


----------



## lmfodor

KedarWolf said:


> The 19-21 was suggested to me by someone and I find it a bit easier to get stable and a bit better in benchmarks. Technically it should be 21-21 but I find 19-21 benches a bit better. I changed the SCLs to 4 and lowered the ProODT to 40 and the ClkDrStr to 40, this passes TM5, SCLs at 2 doesn't. 1.2v on SoC is the highest I'll go but I've seen people running as high as 1.25v.
> 
> From what I understand 5000 series chips have good tolerance for higher voltages, it's 3000 series you want to keep lower.
> 
> Edit: I actually get a better score on AIDA64 and Sandra multi-core efficiency with SCLs at 4 instead of 2.


Yes, it really surprised me that works perfect for me. I think we both share the same PCB, it´s the same model, both Dual Rank. And the score are really good. I don´t think I could improve it so much at 3800. Have you tried 4000-15-15-15? I think this would be my next step. 

Regarding the timings, it´s something that I try to understand, reading a lot, but there are some values that ar far away from the rulesets, that really consfused me. Becuase, I know there are a lot of PCB and electrical specific parameters to have in consideration, but as a newbie, that one day I will stop being, I read a lot and in my head I try to think about relationships more than values and rules, so hundreds or thousands of times Veii enlightened us with his advice, because I don´t hink that is everything trial and error, but there must be a relationship, some values with voltages, others with nano seconds and frequencies. I´d love to have an excel but not for calculation, but to understand the relationship between those ns and how they should be related. I think it would be a good way to ask less, or to be more specific, and also to understand better. I see many times that @Veii tell us when a value is not stable, but not by rules, but by his understanding how it works, for example I read a lot about the relationships of tRDWR and tWRRD, which is used as latency, and these related to the TWR, and the SCL, and with the tRFC, everything has to be in tune. So if we talk about recommended values, it is trial and error, but if we talk about relationships, and since everything is related, it can better find a way to test. For example, lowering the tRCDRD, which seems to be the most difficult of all values, implies that you have to make several changes, I can understand some of them, how to loose some times to achieve a stable configuration with less performance and then adjust. But how do I determine the voltage increase? How do I know if 1.5 is enought? Or do I have to go to 1.55 or 1.6? I mean, because this configuration that we are both running now, in my case I´m at 1.5v and you are at 1.49V. However, I always received recommendations not to lower than 1.55! So I always had errors due to overvoltage, not due to lack of it. There is the problem, which is what I would like to understand. The relationships. Some are in ns, related to clock cycles, if some transfer does not start, if another does not finish well, others related to voltage, and others related to resistances or impedances, which obviously have to do with voltage. Following the rules is not so easy, because there are thousands of recommendations, and not all of them coincide. I think that would be a great step to improve a configuration. For example, I will have spent a month trying to lower the tRCDRD to 15 and not to mention 14, but following some assumptions. And I have no way to "hit" without a good calculation. The rayzen Calculator DRAM is very good, but it was outdated, not only does it not go higher than 1800MHz (or MT / s) but if one wants to look for even tighter values, it never takes them. Perhaps there is a calculator that is more self explanatory. I have many doubts left but I keep reading, writing down. I have a Word Document with Veii's recommendations, they are the best! That is why my question about how you got to such a low tRAS, or such a low tRTP, must have a reason, in fact, see how well it worked for me, but like that, I did not learn anything! I take it as a hobby, I have three memory kits, three different mobos, I can try several OC, but I lack that knowledge that I will gradually learn. I confess that it costs me because I am new, but I am 45 years old and I started at 13 with my first online service back in the early 90's, then I was an Engineer in the old Compaq, then HP, Solution Architect, and had all HW certifications and SW. I worked a lot with circuits from a very young age, so I can say that in my life I always did troubleshooting, now I am dedicated to the sales of Software in one of the main German companies, but I am passionate about this and I want to continue learning. I would lack a better guide than values!



KedarWolf said:


> The 19-21 was suggested to me by someone and I find it a bit easier to get stable and a bit better in benchmarks. Technically it should be 21-21 but I find 19-21 benches a bit better. I changed the SCLs to 4 and lowered the ProODT to 40 and the ClkDrStr to 40, this passes TM5, SCLs at 2 doesn't. 1.2v on SoC is the highest I'll go but I've seen people running as high as 1.25v.


So you did´t pass TM5 with SCL 2 and ProcODT of 48? Does it perform better with SCL 4 and lower ProcODT of 40? Againt, in mi mind, I higher ClkDrStr would help to compensate high voltages, like ProcODT to be lower and also vSOC. I am really impress that your first configuration pass almows 50 cycles of TM5, but I don'´t thing it´s enought. Let´s see if it pass Y-Cuncher All test.. ANTA777.. and also the HCI Memtest, I have the deliuve version.. 

Thanks for your tips!


----------



## KedarWolf

lmfodor said:


> Yes, it really surprised me that works perfect for me. I think we both share the same PCB, it´s the same model, both Dual Rank. And the score are really good. I don´t think I could improve it so much at 3800. Have you tried 4000-15-15-15? I think this would be my next step.
> 
> Regarding the timings, it´s something that I try to understand, reading a lot, but there are some values that ar far away from the rulesets, that really consfused me. Becuase, I know there are a lot of PCB and electrical specific parameters to have in consideration, but as a newbie, that one day I will stop being, I read a lot and in my head I try to think about relationships more than values and rules, so hundreds or thousands of times Veii enlightened us with his advice, because I don´t hink that is everything trial and error, but there must be a relationship, some values with voltages, others with nano seconds and frequencies. I´d love to have an excel but not for calculation, but to understand the relationship between those ns and how they should be related. I think it would be a good way to ask less, or to be more specific, and also to understand better. I see many times that @Veii tell us when a value is not stable, but not by rules, but by his understanding how it works, for example I read a lot about the relationships of tRDWR and tWRRD, which is used as latency, and these related to the TWR, and the SCL, and with the tRFC, everything has to be in tune. So if we talk about recommended values, it is trial and error, but if we talk about relationships, and since everything is related, it can better find a way to test. For example, lowering the tRCDRD, which seems to be the most difficult of all values, implies that you have to make several changes, I can understand some of them, how to loose some times to achieve a stable configuration with less performance and then adjust. But how do I determine the voltage increase? How do I know if 1.5 is enought? Or do I have to go to 1.55 or 1.6? I mean, because this configuration that we are both running now, in my case I´m at 1.5v and you are at 1.49V. However, I always received recommendations not to lower than 1.55! So I always had errors due to overvoltage, not due to lack of it. There is the problem, which is what I would like to understand. The relationships. Some are in ns, related to clock cycles, if some transfer does not start, if another does not finish well, others related to voltage, and others related to resistances or impedances, which obviously have to do with voltage. Following the rules is not so easy, because there are thousands of recommendations, and not all of them coincide. I think that would be a great step to improve a configuration. For example, I will have spent a month trying to lower the tRCDRD to 15 and not to mention 14, but following some assumptions. And I have no way to "hit" without a good calculation. The rayzen Calculator DRAM is very good, but it was outdated, not only does it not go higher than 1800MHz (or MT / s) but if one wants to look for even tighter values, it never takes them. Perhaps there is a calculator that is more self explanatory. I have many doubts left but I keep reading, writing down. I have a Word Document with Veii's recommendations, they are the best! That is why my question about how you got to such a low tRAS, or such a low tRTP, must have a reason, in fact, see how well it worked for me, but like that, I did not learn anything! I take it as a hobby, I have three memory kits, three different mobos, I can try several OC, but I lack that knowledge that I will gradually learn. I confess that it costs me because I am new, but I am 45 years old and I started at 13 with my first online service back in the early 90's, then I was an Engineer in the old Compaq, then HP, Solution Architect, and had all HW certifications and SW. I worked a lot with circuits from a very young age, so I can say that in my life I always did troubleshooting, now I am dedicated to the sales of Software in one of the main German companies, but I am passionate about this and I want to continue learning. I would lack a better guide than values!
> 
> 
> 
> So you did´t pass TM5 with SCL 2 and ProcODT of 48? Does it perform better with SCL 4 and lower ProcODT of 40? Againt, in mi mind, I higher ClkDrStr would help to compensate high voltages, like ProcODT to be lower and also vSOC. I am really impress that your first configuration pass almows 50 cycles of TM5, but I don'´t thing it´s enought. Let´s see if it pass Y-Cuncher All test.. ANTA777.. and also the HCI Memtest, I have the deliuve version..
> 
> Thanks for your tips!


Anything above 3800 I get a lot of WHEA errors but I think it's just a limitation of my IMC. Your results may be different.


----------



## Pictus

lmfodor said:


> 6. P*ower Supply Idle Control = Low Current Idle* (Advanced\AMD CBS\CPU Common Options) Here I had set it to "Typical Power Idle" however it suggest Low Current, do you know what would be better?


It depends on the PSU/BIOS/ETC, keep it "Typical Power Idle" and it is one less thing to worry...


----------



## lmfodor

Veii said:


> Please don't take it as rude, if i give a bit of critique too this writeup
> All 3 options are strange and first two misunderstood
> 
> *Global C-States*, does allow the per-core c-states to function and dLDO to function (speedstep , nothing to do with suspended cores)
> This means, it allows the cpu to go down to 550Mhz P3/P4 state
> This is important to have it enabled.
> In combination with CPPC , it allows windows to lower frequency on worse cores and accept dLDO_injector , to smooth the voltage differentiation between cores ~ where each of the little core modules
> 
> 
> Spoiler: Single CCD Illustration
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Credits for the shot to Fritzchen's Fritz AMD/Zen3/Ryzen/Vermeer | Flickr
> 
> 
> It needs to be enabled, soo cores can adjust and Vermeer can adjust inside the powerbudget
> 
> *DF-States* are controlling the suspension and also the wake-up from hibernation , triggers the overboosting bug , which causes an "idle to wake-up" crash by badly designed powerplans from AMD & Microsoft, without Peak frequency boosts
> This has to be disabled till it get's fixed on 1202 or 1202ABCD
> * i need to test if it's still an issue on 1202 , after figuring out what the hello kitty is wrong with RZQ and why IMC behaviour is now completely exotic and wrong/broken
> ~ after the PMTable rewrite & 3 new activated sensors inside FIT
> 
> 
> Spoiler: Overboost issue illustration with DF-States
> 
> 
> 
> 
> View attachment 2489039
> 
> Whole Source
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Veii, what's the formula for correct tCKE? And what would be the optimal RTT values for 4 sticks of 8GB SR ? It's frequency dependent Each 200MT/s = +2 tCKE 3600 = 6/7 3800 = 9 4000 = 11 4200 = 13 Stock 3600 = 6, but 7 say my findings probably it goes in stepping's of 3 like CkeSetup Timing
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> 
> 
> 
> This is what you described as Infinity Fabric Scaling "disabled"
> It's on FW level disabled & does nothing from the surface viewpoint (maybe does something internally if you keep it functioning at misson-mode = 0)
> and if you ask any engineer about Dynamic FCLK and variable SOC - they will cut the contact with you
> I think this topic is under NDA , 4 engineers refused to answer and cut the chat after asking more about ABPDIS and why Dynamic FCLK is disabled internally
> 
> You can keep it at 0 mission mode
> it won't function except for Renoir & Cezanne, which have STAMP control and are build upon this. Same for ryzen U & G series notebooks ~ there it functions
> For Matisse and Vermeer it's disabled since mid of the lifespan of Matisse & Matisse has an 1900 FCLK lock - like Vermeer was attempted to get after Patch C, gladly this nonsense was stopped after Patch D
> 
> Before 1200 , soo 1191/1181 and lower, you can run this
> 1202 seems to set internally X-X-X-2-X-X-X-2
> SMU debug shows on 1200 and lower that 2-1-X-X-2-1-X-X is used
> One 600mhz link with one 300mhz one. Level 2 and Level 3 where not readable , but 2-2-1 was not accepted by SMU
> Currently i test 2-1-1-2/2-1-1-2, as Level3/4 (the last link) is set at 600mhz and used (by FW alone, i had them at auto)
> probably 2-1-1-2 could be good, but we'll see, test in progress AGESA 1.2.0.2 is awkward & did a lot of changes
> 
> The rest is fine
> You can include opening PBO EDC to 400A
> It still allows cache to boost till it gets internally limited
> and should be reflective on SiSandra MCE , as also on Aida64
> But lifting the EDC limit will need a limit on TDC , else it adds to much voltage for allcore and the CPU throttles back
> This can be fixed by nearly maxed out negative CO with "lower" but positive vcore offset or just more droopy CPU LLC


Veii! How do you think it might sound a bit rude coming from you? It is an honor to have you here and have an advice or explanation from you. I regret not having entered a while ago to be able to take advantage of more of the time when you were more active, but that's life!



Veii said:


> *DF-States* are controlling the suspension and also the wake-up from hibernation , triggers the overboosting bug , which causes an "idle to wake-up" crash by badly designed powerplans from AMD & Microsoft, without Peak frequency boosts
> This has to be disabled till it get's fixed on 1202 or 1202ABCD
> * i need to test if it's still an issue on 1202 , after figuring out what the hello kitty is wrong with RZQ and why IMC behaviour is now completely exotic and wrong/broken
> ~ after the PMTable rewrite & 3 new activated sensors inside FIT


Well, impressive explanation! and great picture!! and also the graph. You know why I am disabled it (C-states), because is a "best practice" to avoid the common reboot on iddle, but is not the sotution neigher a workaround. Perhaps going to a less aggressive curve, not per core. all cores -20 or -25, and a little positive Vcore Offset would help to avoid the idle reboot. But one think make me doubt, I´m running SMU 56.45 (and thinking of installing two older versions, before Patch D .. to test if an OC above 4000 or 4000 works better, since today I receive WHEAS constants). I also disabled the DF States, so maybe it help with the Idle reboot, not the C-States.. I will enable it to see if I have some reboots. Do you recommend me to change to an older BIOS than my actual 56.45? I will loose REBAR but I prefer to have a 4000-x-x-x without WHEAs



Veii said:


> This is what you described as Infinity Fabric Scaling "disabled"
> It's on FW level disabled & does nothing from the surface viewpoint (maybe does something internally if you keep it functioning at misson-mode = 0)
> and if you ask any engineer about Dynamic FCLK and variable SOC - they will cut the contact with you
> I think this topic is under NDA , 4 engineers refused to answer and cut the chat after asking more about ABPDIS and why Dynamic FCLK is disabled internally
> 
> You can keep it at 0 mission mode
> it won't function except for Renoir & Cezanne, which have STAMP control and are build upon this. Same for ryzen U & G series notebooks ~ there it functions
> For Matisse and Vermeer it's disabled since mid of the lifespan of Matisse & Matisse has an 1900 FCLK lock - like Vermeer was attempted to get after Patch C, gladly this nonsense was stopped after Patch D


Ok, so I´m gonna disable it. 4 engineered refused to unswer you. Wow!



Veii said:


> Before 1200 , soo 1191/1181 and lower, you can run this
> 1202 seems to set internally X-X-X-2-X-X-X-2
> SMU debug shows on 1200 and lower that 2-1-X-X-2-1-X-X is used
> One 600mhz link with one 300mhz one. Level 2 and Level 3 where not readable , but 2-2-1 was not accepted by SMU
> Currently i test 2-1-1-2/2-1-1-2, as Level3/4 (the last link) is set at 600mhz and used (by FW alone, i had them at auto)
> probably 2-1-1-2 could be good, but we'll see, test in progress AGESA 1.2.0.2 is awkward & did a lot of changes


Ok, I´m on 1200,right now so I don´t need it, but I would like to try 56.30, I think it´s one the better version to try 4000 Freq, right? So If I´m not wrong should be AGESA 1.9.0.x , and in that case I should use 2-1-1-1/2-1-1-1, To understand, what exacttly do that? I just google it to find the AGESA version and I found you in Reddit . I always wanted to know, when you refer as Boost in memory, what it is? I never found any Boost on my Asus. I will try your suggestion of maxed out CO to -30 and maybe apply +40mV right? And also LL2? or one of them?

Thanks!!


----------



## KedarWolf

KedarWolf said:


> I'll test traditional instead of 19-21 for latency, but yeah, I change a lot of hidden things you can with A210. I won't be home from work for 8 hours or so though to test.
> 
> Edit: I'll share my BIOS settings when I get home.























Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 178.51GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 40.1ns (9.5ns - 61.9ns)
Inter-Thread (same Core) Latency : 9.7ns
Inter-Core (same Module) Latency : 20.8ns
Inter-Module (same Package) Latency : 58.8ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.58GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1740.91MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.82ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 37.12MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 22.1ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 21.9ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 21.8ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 20.8ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.8ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.5ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 60.3ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 60.7ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 60.4ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 60.6ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 59.7ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 60.3ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 59.3ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 59.9ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 22.2ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.9ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 21.8ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 20.8ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.8ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.5ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.2ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 60.5ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 60.6ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 60.4ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 60.6ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 59.8ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 60.3ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 59.4ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 59.9ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 21.7ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 22.9ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 21.1ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 22.1ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.4ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.9ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.7ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 56.5ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.0ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.4ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 57.8ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 57.9ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.3ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.0ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.4ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 19.1ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 20.7ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 19.8ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 21.3ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.4ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.9ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 61.4ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 61.0ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.5ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.6ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 59.4ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 58.6ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.9ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 60.3ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 21.1ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 21.9ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.4ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 21.4ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 20.8ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 60.3ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.5ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 59.9ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.8ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 58.5ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 57.8ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.2ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.7ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 19.4ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.2ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.9ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.7ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.4ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.4ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 21.3ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 21.1ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 57.8ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 59.4ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 59.9ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 60.0ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.6ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 59.2ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 58.4ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 59.2ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.4ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 22.0ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.1ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 22.3ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.4ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 60.7ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 57.8ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.0ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.7ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 59.1ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 58.6ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 58.7ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.0ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 21.0ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.7ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.4ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.9ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 21.1ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.5ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.8ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 59.4ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.2ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.1ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 60.4ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 59.6ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.6ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.4ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.0ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 21.4ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.1ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 58.2ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 58.1ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 57.1ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.8ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 59.6ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.3ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.3ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 59.2ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.4ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 20.7ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.5ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.4ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 19.3ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 21.8ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 20.8ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 56.8ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.0ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.1ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.8ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 57.9ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.6ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.6ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.7ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.6ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 20.0ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 59.3ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.0ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.1ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 59.6ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.1ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.5ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.0ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 57.8ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.5ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.3ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.4ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.8ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 21.0ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.7ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.6ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 20.6ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.4ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.8ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.1ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 58.7ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.2ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 57.9ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.0ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.8ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 19.9ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 59.2ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 59.7ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.9ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 59.0ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.2ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.1ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.4ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.2ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 20.7ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 21.3ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 21.4ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.1ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 19.1ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.7ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.9ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.1ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 59.4ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 59.1ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 59.2ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.0ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.0ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 58.6ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.4ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 59.7ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.8ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 59.0ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.7ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 58.9ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.8ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 58.8ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.0ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.4ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 21.0ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.0ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.4ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.1ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 20.7ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.5ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.7ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.3ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 59.3ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.8ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.5ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 59.2ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 58.5ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.2ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 21.8ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 21.0ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 22.2ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 21.0ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.6ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 59.4ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.4ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.0ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 58.8ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 58.1ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 59.3ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.9ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 59.6ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 22.3ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 20.4ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.7ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 22.4ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.5ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.4ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.8ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 20.4ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 20.6ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.7ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.2ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.7ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 59.7ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 59.2ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 58.5ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.8ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 58.2ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 58.2ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.3ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.2ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 21.1ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.7ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 21.7ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 20.4ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 20.9ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 21.1ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.3ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.3ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.4ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 20.6ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.1ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 19.6ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.8ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 56.7ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.3ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 58.3ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 59.5ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.3ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.5ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.6ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 59.6ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 21.7ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 18.8ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.7ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 20.6ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.1ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 21.9ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.5ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.3ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 20.5ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 19.4ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.9ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 56.6ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 58.8ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.5ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 59.7ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.3ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 59.2ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 59.0ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.2ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 18.9ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 21.7ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 21.0ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.7ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.3ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.8ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 19.5ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 20.2ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 21.9ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.4ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.1ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 57.6ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 59.7ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.5ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 59.7ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.2ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 58.5ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.6ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 19.8ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 21.2ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 20.6ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.4ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.8ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.1ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 21.6ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.0ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 20.2ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.8ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 59.2ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 59.2ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 60.6ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.9ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.4ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 59.0ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.8ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.5ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.4ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.5ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.3ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 20.2ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.5ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 22.4ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 21.5ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.9ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 60.6ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.2ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 58.9ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.5ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.4ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.3ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.3ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.4ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 19.6ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 21.5ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 20.2ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.7ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 21.9ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 59.6ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 60.8ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.6ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 60.1ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.8ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.6ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.1ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.4ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.3ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.5ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.5ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.3ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 19.7ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.9ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 20.4ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.6ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 22.7ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 22.0ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.9ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 19.4ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.8ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 20.7ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.3ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 59.1ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 58.5ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 56.9ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 58.0ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 58.3ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.8ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.9ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.5ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.9ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 21.2ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 21.4ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.5ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 21.0ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 61.9ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 61.1ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.0ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 56.8ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 61.4ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.5ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 59.3ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.6ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 21.3ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.9ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.4ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 21.1ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 20.8ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.7ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.6ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 60.4ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 59.0ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.3ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 57.9ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.3ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 60.1ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.9ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.2ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.5ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.5ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.3ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.5ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 59.0ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 59.5ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.8ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.7ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.4ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 19.4ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 21.8ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.5ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 60.3ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 59.7ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 57.1ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 59.8ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.7ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.2ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.6ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.7ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 20.3ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 22.4ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 56.9ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 58.1ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 59.1ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 58.2ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.4ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 59.6ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.9ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 59.0ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 19.1ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.1ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.7ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.6ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.3ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.4ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.0ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.4ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 59.2ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.1ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.6ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.4ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 58.5ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 59.6ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.3ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.0ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 20.9ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 22.8ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 21.9ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 21.2ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 19.6ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.4ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 21.6ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 22.9ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 20.5ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 21.2ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.7ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.8ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 21.1ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 20.7ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.3ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 20.9ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.8ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.4ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.7ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.5ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 22.1ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.1ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 21.9ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 20.4ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.5ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.9ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 21.8ns
1x 64bytes Blocks Bandwidth : 26.26GB/s
4x 64bytes Blocks Bandwidth : 28.6GB/s
4x 256bytes Blocks Bandwidth : 102GB/s
4x 1kB Blocks Bandwidth : 328GB/s
4x 4kB Blocks Bandwidth : 517.23GB/s
16x 4kB Blocks Bandwidth : 728.6GB/s
4x 64kB Blocks Bandwidth : 1001.46GB/s
16x 64kB Blocks Bandwidth : 606.71GB/s
8x 256kB Blocks Bandwidth : 616.7GB/s
4x 1MB Blocks Bandwidth : 606.11GB/s
16x 1MB Blocks Bandwidth : 25.43GB/s
8x 4MB Blocks Bandwidth : 19.15GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.92GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 4.92GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.92GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.























Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-ThSiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 175.35GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.9ns (9.5ns - 59.7ns)
Inter-Thread (same Core) Latency : 9.7ns
Inter-Core (same Module) Latency : 20.9ns
Inter-Module (same Package) Latency : 58.5ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.48GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1710.09MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.80ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 36.46MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.5ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 21.7ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 19.6ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 22.0ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.0ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 21.4ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 57.9ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 57.8ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 57.8ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.1ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.7ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.9ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.5ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.6ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.5ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.6ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.7ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 19.6ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 22.0ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 19.9ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 21.4ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.3ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 57.9ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 57.7ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 58.0ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.1ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.8ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.9ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.6ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.4ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 20.6ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.0ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 21.2ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.5ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.3ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 58.1ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.8ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 58.4ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.2ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 59.0ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 57.9ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.9ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.6ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.5ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 20.6ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 20.1ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.5ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.5ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.4ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 58.1ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 58.0ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.3ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.3ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 59.0ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 57.9ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 59.1ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.3ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.8ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 22.9ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.3ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 22.4ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 21.1ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 58.1ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.0ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 58.4ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.7ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.2ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.3ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.7ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.7ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 21.6ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.7ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.7ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 22.9ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.4ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 22.4ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 21.1ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 58.0ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 58.0ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 58.4ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 57.7ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.2ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.3ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 58.7ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.6ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 20.8ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.2ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 20.8ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.0ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 57.7ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 58.2ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 57.5ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.8ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.2ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 58.8ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 58.5ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.9ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 20.3ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.9ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.8ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 20.7ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 20.7ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 20.8ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.0ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.6ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 58.2ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.9ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.3ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.9ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.5ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.8ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.7ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.4ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 58.4ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 58.2ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 59.0ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.1ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 59.6ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.7ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 59.2ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 59.0ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 21.7ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 21.2ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 23.1ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.4ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.8ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.8ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.4ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 58.4ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 58.2ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.9ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.1ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 59.7ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.7ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 59.2ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 59.0ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.0ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.2ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.5ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.1ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.5ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.6ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.4ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.2ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.1ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.5ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.2ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.7ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.6ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.7ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.7ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.0ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.2ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.4ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 58.1ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.6ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.5ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 59.4ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.2ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.5ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 21.0ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.6ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.4ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.7ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 57.9ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.4ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 58.8ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.4ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.4ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.4ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.5ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.7ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 20.9ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.0ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.6ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.5ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.6ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.0ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.5ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 58.9ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.4ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.4ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.9ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.2ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.9ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 57.7ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.5ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.7ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.2ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.4ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.2ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 20.6ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.6ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.2ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.1ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.6ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.9ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.2ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.9ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 57.7ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.5ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.4ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.6ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.4ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 21.4ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.4ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 22.4ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.1ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.4ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.3ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 58.3ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 58.1ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 58.4ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.7ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 58.7ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.1ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.8ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.6ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.7ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.4ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 21.4ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.4ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 22.4ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.1ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.4ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.3ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 20.4ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.8ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 21.1ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.4ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.3ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.3ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.9ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 58.0ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 58.4ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 58.7ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.4ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.6ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.1ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.4ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.7ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 20.4ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.8ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 21.1ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.4ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.3ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.2ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 22.8ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.1ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.2ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.9ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 58.0ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 58.5ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 58.5ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 58.0ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 58.6ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.7ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.6ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 21.4ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 20.3ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.7ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 22.8ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.1ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.1ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.9ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.6ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 20.5ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 20.5ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.6ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.6ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 58.0ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 58.2ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.2ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.6ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.5ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 57.9ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.7ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 19.8ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.7ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.7ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.6ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 20.5ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 20.7ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.6ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.1ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.6ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.7ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 59.5ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 59.0ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.6ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 59.4ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.5ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.4ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 22.1ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 21.1ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 23.0ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.4ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.8ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.1ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.6ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 20.9ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.3ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 58.2ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.6ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.8ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.0ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 59.2ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.0ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 59.0ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.5ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.2ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.4ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.4ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.5ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.7ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 20.9ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.3ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 20.9ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.9ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 59.1ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 59.2ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 58.5ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 59.3ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.7ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.5ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.3ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.4ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.3ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.2ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 22.9ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 20.9ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 20.9ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.5ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.7ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 59.0ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.0ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 59.5ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.3ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.4ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.9ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.2ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.3ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.0ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.4ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.8ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.2ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 21.1ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.6ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 21.6ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.6ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 22.0ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.0ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.4ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.2ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 57.9ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 57.7ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.8ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.3ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 58.8ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.9ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.6ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.5ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.8ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.1ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 21.3ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.6ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.6ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.6ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 58.4ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 58.4ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.8ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.7ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 59.3ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.6ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 59.3ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 59.0ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 22.9ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.4ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.4ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.1ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.0ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.0ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 58.3ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 59.1ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.4ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.8ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.7ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.7ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.8ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.9ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.8ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.0ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.7ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 58.3ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.8ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.4ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.8ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.5ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.8ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.8ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.4ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 58.4ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 58.2ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.9ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 58.1ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 59.7ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.6ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 59.3ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 59.0ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.0ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.2ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 58.4ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 58.1ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 58.6ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.5ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 59.3ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.2ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 59.1ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.5ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 21.0ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.6ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 58.4ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.7ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.1ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.4ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 58.7ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.4ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.4ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.9ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.2ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.8ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 57.7ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.7ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.5ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.6ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.1ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.4ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 21.4ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.5ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 22.3ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.1ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.4ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.3ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 20.3ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.7ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 21.1ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.4ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.3ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.2ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 22.8ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.1ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.1ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.9ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.6ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 20.5ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.6ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 20.6ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.1ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 22.9ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.6ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 20.9ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.3ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 20.9ns
1x 64bytes Blocks Bandwidth : 26.57GB/s
4x 64bytes Blocks Bandwidth : 29.2GB/s
4x 256bytes Blocks Bandwidth : 103.48GB/s
4x 1kB Blocks Bandwidth : 324GB/s
4x 4kB Blocks Bandwidth : 522GB/s
16x 4kB Blocks Bandwidth : 669.66GB/s
4x 64kB Blocks Bandwidth : 1001.73GB/s
16x 64kB Blocks Bandwidth : 612.24GB/s
8x 256kB Blocks Bandwidth : 600.25GB/s
4x 1MB Blocks Bandwidth : 608.21GB/s
16x 1MB Blocks Bandwidth : 22.37GB/s
8x 4MB Blocks Bandwidth : 18.56GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.92GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 4.92GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.92GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.
read Bandwidth : 175.35GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.9ns (9.5ns - 59.7ns)
Inter-Thread (same Core) Latency : 9.7ns
Inter-Core (same Module) Latency : 20.9ns
Inter-Module (same Package) Latency : 58.5ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.48GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1710.09MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.80ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 36.46MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.5ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 21.7ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 19.6ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 22.0ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.0ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 21.4ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 57.9ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 57.8ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 57.8ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.1ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.7ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.9ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.5ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.6ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.5ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.6ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.7ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 19.6ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 22.0ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 19.9ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 21.4ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.3ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 57.9ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 57.7ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 58.0ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.1ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.8ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.9ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.6ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.4ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 20.6ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.0ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 21.2ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.5ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.3ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 58.1ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.8ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 58.4ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.2ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 59.0ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 57.9ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.9ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.6ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.5ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 20.6ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 20.1ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.5ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.5ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.4ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 58.1ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 58.0ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.3ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.3ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 59.0ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 57.9ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 59.1ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.3ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.8ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 22.9ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.3ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 22.4ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 21.1ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 58.1ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.0ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 58.4ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.7ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.2ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.3ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.7ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.7ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 21.6ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.7ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.7ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 22.9ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.4ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 22.4ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 21.1ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 58.0ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 58.0ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 58.4ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 57.7ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.2ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.3ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 58.7ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.6ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 20.8ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.2ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 20.8ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.0ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 57.7ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 58.2ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 57.5ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.8ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.2ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 58.8ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 58.5ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.9ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 20.3ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.9ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.8ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 20.7ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 20.7ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 20.8ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.0ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.6ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 58.2ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.9ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.3ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.9ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.5ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.8ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.7ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.4ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 58.4ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 58.2ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 59.0ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.1ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 59.6ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.7ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 59.2ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 59.0ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 21.7ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 21.2ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 23.1ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.4ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.8ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.8ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.4ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 58.4ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 58.2ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.9ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.1ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 59.7ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.7ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 59.2ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 59.0ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.0ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.2ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.5ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.1ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.5ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.6ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.4ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.2ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.1ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.5ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.2ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.7ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.6ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.7ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.7ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.0ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.2ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.4ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 58.1ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.6ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.5ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 59.4ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.2ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.5ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 21.0ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.6ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.4ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.7ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 57.9ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.4ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 58.8ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.4ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.4ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.4ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.5ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.7ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 20.9ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.0ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.6ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.5ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.6ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.0ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.5ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 58.9ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.4ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.4ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.9ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.2ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.9ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 57.7ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.5ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.7ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.2ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.4ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.2ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 20.6ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.6ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.2ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.1ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.6ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.9ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.2ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.9ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 57.7ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.5ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.4ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.6ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.4ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 21.4ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.4ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 22.4ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.1ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.4ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.3ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 58.3ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 58.1ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 58.4ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.7ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 58.7ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.1ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.8ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.6ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.7ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.4ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 21.4ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.4ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 22.4ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.1ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.4ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.3ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 20.4ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.8ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 21.1ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.4ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.3ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.3ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.9ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 58.0ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 58.4ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 58.7ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.4ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.6ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.1ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.4ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.7ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 20.4ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.8ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 21.1ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.4ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.3ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.2ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 22.8ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.1ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.2ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.9ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 58.0ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 58.5ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 58.5ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 58.0ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 58.6ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.7ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.6ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 21.4ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 20.3ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.7ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 22.8ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.1ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.1ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.9ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.6ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 20.5ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 20.5ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.6ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.6ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 58.0ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 58.2ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.2ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.6ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.5ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 57.9ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.7ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 19.8ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.7ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.7ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.6ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 20.5ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 20.7ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.6ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.1ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.6ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.7ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 59.5ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 59.0ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.6ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 59.4ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.5ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.4ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 22.1ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 21.1ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 23.0ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.4ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.8ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.1ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.6ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 20.9ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.3ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 58.2ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.6ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.8ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.0ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 59.2ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.0ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 59.0ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.5ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.2ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.4ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.4ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.5ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.7ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 20.9ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.3ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 20.9ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.9ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 59.1ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 59.2ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 58.5ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 59.3ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.7ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.5ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.3ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.4ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.3ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.2ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 22.9ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 20.9ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 20.9ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.5ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.7ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 59.0ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.0ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 59.5ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.3ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.4ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.9ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.2ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.3ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.0ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.4ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.8ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.2ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 21.1ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.6ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 21.6ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.6ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 22.0ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.0ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.4ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.2ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 57.9ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 57.7ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.8ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.3ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 58.8ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.9ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.6ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.5ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.8ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.1ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 21.3ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.6ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.6ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.6ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 58.4ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 58.4ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.8ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.7ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 59.3ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.6ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 59.3ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 59.0ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 22.9ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.4ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.4ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.1ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.0ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.0ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 58.3ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 59.1ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.4ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.8ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.7ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.7ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.8ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.9ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.8ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.0ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.7ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 58.3ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.8ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.4ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.8ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.5ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.8ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.8ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.4ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 58.4ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 58.2ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.9ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 58.1ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 59.7ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.6ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 59.3ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 59.0ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.0ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.2ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 58.4ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 58.1ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 58.6ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.5ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 59.3ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.2ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 59.1ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.5ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 21.0ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.6ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 58.4ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.7ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.1ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.4ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 58.7ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.4ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.4ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.9ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.2ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.8ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 57.7ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.7ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.5ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.6ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.1ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.4ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 21.4ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.5ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 22.3ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.1ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.4ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.3ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 20.3ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.7ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 21.1ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.4ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.3ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.2ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 22.8ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.1ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.1ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.9ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.6ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 20.5ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.6ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 20.6ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.1ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 22.9ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.6ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 20.9ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.3ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 20.9ns
1x 64bytes Blocks Bandwidth : 26.57GB/s
4x 64bytes Blocks Bandwidth : 29.2GB/s
4x 256bytes Blocks Bandwidth : 103.48GB/s
4x 1kB Blocks Bandwidth : 324GB/s
4x 4kB Blocks Bandwidth : 522GB/s
16x 4kB Blocks Bandwidth : 669.66GB/s
4x 64kB Blocks Bandwidth : 1001.73GB/s
16x 64kB Blocks Bandwidth : 612.24GB/s
8x 256kB Blocks Bandwidth : 600.25GB/s
4x 1MB Blocks Bandwidth : 608.21GB/s
16x 1MB Blocks Bandwidth : 22.37GB/s
8x 4MB Blocks Bandwidth : 18.56GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.92GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 4.92GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.92GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## KedarWolf

This link will show all my BIOS settings for the Unify-X A210 BIOS, the last unlocked one we got as far as I know.



http://imgur.com/a/r44xPOt


----------



## TimeDrapery

Veii said:


> Spoiler
> 
> 
> 
> this TM5 profile based upon 1usmus_v3 ?
> Because for example Anta's profile , the error numbers differ fully and mean something completely different
> CsOdtDrvStr got a bump between 30-40ohm , in order to work against the broken memory training since AGESA 1.1.0.0*A*
> After Patch C , it got worse and worse / this was about the correct option, to get it towards a useable setting
> It's not fitting for Matisse.
> There the hard work of 1usmus from the DRAM calculator works blindly
> 
> ClkDrvStr bump still is a good method to help lowering procODT and getting GDM off
> Which btw is too high for you
> in combination with high ClkDrvStr, it might be too much for the PCB and you can "PCB Crash" - IF the errors mean the same which they do on Yuri's preset
> 
> Matisse's procODT range was:
> 28-32ohm for 2x8GB SR
> 34-36ohm for Dual Rank or 4x8Gb
> 34~ for Rev.E or Micron B-Die
> 30-32 for Hynix-MFR or AFR (CJR should be fine within 30)
> Overall it's too high.
> 
> The minimum & optimal value at 900-950-1050 (1900FCLK) on Matisse was 28ohm with B-dies, and anything else a tad higher.
> But not 3 steps higher like you do run atm.
> It also needed the UncoreOC flag inside AMD OVERCLOCKING enabled, else FIT was autocorrecting the voltage you set and ignore it fully
> (a long story with buggy Dynamic FCLK & Dynamic SOC)
> 
> Another thing is that you run tRAS+2.
> If you want to move inside JEDEC's range, you need to use +4 for SR ~ or don' follow it and run tRCD+tRCD (28)
> tRC "technically optimally" would remain that 32+tRP.
> That under *8 multiplier from my anchor's would be 368-273-168, with tWR 16 (8.421111....to the infinite)
> 
> But JEDEC up to which revision out of the 30+ , you refer to - doesn't always define what has to work.
> It's not recommend to follow it like a holy book. Especially when this holy book had over 30 revisions
> 
> I'm also a bit conflicted with your tWRRD & tWTR set
> 4-12 should run, but i can't recommend stuff blindly without double-testing SD,DD relationship here.
> Try to get it stable under SLC 4-4 , with your current setting and bump up tRRD & tWTR (5-14) , till you have something that passes at least 20 cycles TM5
> (or anything that takes longer than 1h to test ~ soo you hit thermal equilibrium & still have a full cycle to test)
> 
> RTT 7/0/6 is a bit special
> Combine it please with tCKE 9
> It does work also for Matisse, but CAD_BUS SETUP timings could missmatch
> I think what you surely want, is to drop VDDG IOD a bit near that 1v range or even 950mV with procODT max 32ohm
> 32ohm shouldn't allow you to run VDDG IOD to 950mV but 28ohm will !
> ClkDrvStr doesn't care about it, you can keep running 40 or 60ohm there ~ just have in your backhead, that it is a (A) multiplier , soo if you want to increase RTT_PARK strengthness for example /6 or /5, lower it down to 40ohm instead of 60 (for single rank) . Or lower VDIMM down
> 
> About Matisse,
> 24-20-20-24 is what works , similar for Zen 1
> 24-20-24-24 should be used on lower quality PCBs to prevent cold boot issues, but higher than 24 is not needed on any board for Matisse and lower
> 30-20-20-24 is fine, same as 40-20-20-24 is fine
> 60-20-20-24 is a bit conflicting but can work out , it's just a bit harsh . You may need 60-20-20-20, but you'll figure it out
> 
> SOC beyond 1.1v here has bad effects and increases procODT requirements.
> Up till 1.15v is usually the range after when negative scaling begins
> But i want to remind, that 1900 FCLK on Matisse was hard and it still suffered from bad signal integrity ranges
> Soo lower procODT = higher FCLK (1900 lock, but 1900 didn't run on every CPU)
> Focus on that 28ohm range, and stay at 900mV cLDO_VDDP
> 950mV is not fine with 28ohm proc, same as beyond 1.1v is not fine with it.
> 1900 FCLK bruteforce settings are 32ohm proc, 950-1050-1100-1150 (cLDO_VDDP, VDDG CCD , VDDG IOD, VSOC [GET])
> * stepping on Matisse was 50mV on stock or 75mV on extreme bruteforce settings
> More about it here:
> 
> 
> 
> 
> 
> 
> 
> 
> OC'ing T-Force 4133 cl18
> 
> 
> I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> Buttom part of the message
> AMDs minimum limits are 42-43mV (ty The Stilt) , but you want to have at least 48mV difference between the GET settings between VDDP, VDDG and VSOC
> 
> I have a bit of an issue with anytype of "fixed real world timed" values
> There was a ruleset out there spreading on the Intel MemOC thread, about tWR being a 8ns value as absolute minimum
> This can not work. Memory is logarithmic and works on integers
> No real world timed value is correct - as it scales up and down depending on set MCLK and the Command Rate state (PowerDown and GDM rounding included)
> 
> This is not optimal, and i strongly try to skip math that considers any type of fixed ns value. This can not work and won't work.
> Rounding decimal numbers is also not optimal, same as focusing on fixed ns tRFC value is strongly not considerable
> Been through this, and one of the reasons that tRFC mini module exists
> 
> Technically tRAS + XYZ (4,8) or tRC+1,2,4,8
> used as integer values of tRC as a whole (half cycle, 1/8th of a cycle and so on) - was an option for stability and matching up things.
> But it's also not optimal to do math that way
> No XYZ + fixed ns value , is optimal
> It works when you use added "memory timing" value, as it will turn at the end still to a .xxxxxxx (11 decimals) value
> But if we speak about ns math, that's not a good method
> Every little rounding stacks ~ beginning with board manufactures and IMC firmware developer rounding 3733.33333333337 MT/s, values
> The math breaks, the more you round and tRFC 2 and 4 do fully break if you do it with the /1.346 & /2.1875 math
> * reason why tRFC mini module exists, against Yuri's DRAM Calculator method, it always got tRFC2 & 4 wrong but it wasn't his fault but the user who inputs the wrong ns value
> Even the windows calculator doesn't function beyond 11 decimals, while google docs ends at 13 decimals
> 
> I need to sit with you and write a book about everything that's wrong with how we scale MCLK and boards predict values
> But trust me that a lot of thought went into "tRFC Mini" , and the way that it functions at version v2.31. It had undergone many revisions since v0.1 & yet is not perfect, because i can not generate tSTAG out of thin air, to match it better & have no statistic range for temperature to ns delay failure.
> 
> We'll talk someday about the reason i abandoned fully anything JEDEC related.
> Because this holy book did not follow reality
> A fantastic description was this post by an older dram engineer
> 
> 
> 
> 
> 
> 
> 
> 
> How to calculate tRC timing in cycles?
> 
> 
> Hi. I was looking for some additional ram for my aging desktop PC and tried to find modules that match the timings perfectly. At first I thought I found a perfect match with some Kingston modules, but on a closer look things are a bit weird. Wikipedia, among other sources states that tRC =...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 137,438,953,472 memory cells won't always follow perfect tRC (tRAS+tRP) math, it's not possible to follow it blindly
> But it's still a good indicator if the "transition" is "clean" or not, on a users set ~ or it needs work somewhere else, as tRC added delay does mask issues
> * need to answer Ron too, but it requires another big wall of text, soo someday later


@Veii

Dude, thank you so much for taking your time to help me (and all others reading your posts) to learn more and more with each logon

Yes, the TM5 config is the "1usmus default" config file

I changed the number of cycles and I rename them to display where I obtained the files from so I'll more easily recognize what config I'm using while testing... Sorry for any confusion!

I'm still caught up with my day-to-day right now but I wanted to reply here to thank you and let you know that I'll reply more thoroughly ASAP

Here's a screenshot of my current work-in-progress that reflects the changes I've made in accordance with your guidance...










Take care! Again... *Thank you!!!*


----------



## ManniX-ITA

KedarWolf said:


> This link will show all my BIOS settings for the Unify-X A210 BIOS, the last unlocked one we got as far as I know.
> 
> 
> 
> http://imgur.com/a/r44xPOt


Thanks a lot!
Very interesting indeed, you gained a lot of bandwidth but lost latency; I score around 54.4-54.5ns on both profiles.
But with the low tRAS version frequently drops to 54.7-55.x, like something didn't finish in time and got a retry.
Curious to see what makes the difference, maybe the memory interleave size at 512 bytes.

Yes A21O is the latest. Was waiting for something new but it's not coming out.
I regretted moving to A22, I thought it wouldn't take that much to get a new one.
But I'm lazy and I don't want to re-create all the profile, it's so annoying...


----------



## lmfodor

KedarWolf said:


> The 19-21 was suggested to me by someone and I find it a bit easier to get stable and a bit better in benchmarks. Technically it should be 21-21 but I find 19-21 benches a bit better. I changed the SCLs to 4 and lowered the ProODT to 40 and the ClkDrStr to 40, this passes TM5, SCLs at 2 doesn't. 1.2v on SoC is the highest I'll go but I've seen people running as high as 1.25v.
> 
> From what I understand 5000 series chips have good tolerance for higher voltages, it's 3000 series you want to keep lower.
> 
> Edit: I actually get a better score on AIDA64 and Sandra multi-core efficiency with SCLs at 4 instead of 2.


Hi! I’m just trying with your new values.. and yes, I notice an increase in the read speed. Now I’m testing with y-cruncher all test.. then I’ll run TM5 again. Pretty good! 

Reading your BIOS config, what I like in comparison to the Asus because MSI have more options, I’d like to know some of your settings, why you apply an undervolt to the CPU? Your curve seems very tight. 

The other question is about the LLC, I saw that you have CPU and VSoc at level 2, and also a the CPU VRM and VDDSOC switching frequency set to 1000. In my case I leave CPU LLC to Auto, knowing that many of us are running at level 3, and the CPU VRM and VVDSoc VRM Sw Freq both set to 500. So the question is, it’s better to have the LLC at level 2 and increase the SW Freq to 1000? never saw this on an Asus Mobo. 

My concern and the reason why I’m asking this to you is because as we are using a high VSOC value I guess should have a low LLC, I read this from Yuri. And he also recommend the SW Freq to 500 on his Dark Hero. Should I lower both LLC to 2?
And also about the CPU core negative offset with a good curve as you have.. don’t go to lower on idle? I though that I should have use a positive offset to compensate the curve.. 

Thanks!




Sent from my iPhone using Tapatalk Pro


----------



## DemonAk

Hello guys, need advice
on my b550 taichi + ryzen 5950x + 4x32gb F4-3200C16Q-128GVK (hynix MJR) i can get stable overclock memory at 3533Mhz (dram v1.422, vsoc 1.12 llc1, vddg's auto) maximum, all what above (3600,3666,3733) not stable. played with cad bus, proc's, increased voltages dram to 1.462, soc to 1.2, vddg's to 1.15, vppm to 2.7, vdd to 1.9 but nothing, not stable. I Can pass karhu 1h (even 3 hours) or tm5 (1usmus config) but after reboot errors in tests almost immediately. maybe this is limit board or IMC and i need some special settings or timinngs =\























3533 stable
3666 training and boot ok with procodt 48om, rtt 7/2/1 or 7/3/1 and cad bus 40-20-24-24
3733 problem with memory training and cold boot


----------



## lmfodor

KedarWolf said:


> View attachment 2489115
> 
> 
> View attachment 2489116
> 
> 
> 
> 
> Code:
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 178.51GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Average Inter-Thread Latency : 40.1ns (9.5ns - 61.9ns)
> Inter-Thread (same Core) Latency : 9.7ns
> Inter-Core (same Module) Latency : 20.8ns
> Inter-Module (same Package) Latency : 58.8ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5.58GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1740.91MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 3.82ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 707.05kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 37.12MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 0.08ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-M0C0T0 <> U2-M0C1T0 Data Latency : 22.1ns
> U0-M0C0T0 <> U4-M0C2T0 Data Latency : 21.9ns
> U0-M0C0T0 <> U6-M0C3T0 Data Latency : 21.8ns
> U0-M0C0T0 <> U8-M0C4T0 Data Latency : 20.8ns
> U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.8ns
> U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.5ns
> U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
> U0-M0C0T0 <> U16-M1C0T0 Data Latency : 60.3ns
> U0-M0C0T0 <> U18-M1C1T0 Data Latency : 60.7ns
> U0-M0C0T0 <> U20-M1C2T0 Data Latency : 60.4ns
> U0-M0C0T0 <> U22-M1C3T0 Data Latency : 60.6ns
> U0-M0C0T0 <> U24-M1C4T0 Data Latency : 59.7ns
> U0-M0C0T0 <> U26-M1C5T0 Data Latency : 60.3ns
> U0-M0C0T0 <> U28-M1C6T0 Data Latency : 59.3ns
> U0-M0C0T0 <> U30-M1C7T0 Data Latency : 59.9ns
> U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
> U0-M0C0T0 <> U3-M0C1T1 Data Latency : 22.2ns
> U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.9ns
> U0-M0C0T0 <> U7-M0C3T1 Data Latency : 21.8ns
> U0-M0C0T0 <> U9-M0C4T1 Data Latency : 20.8ns
> U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.8ns
> U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.5ns
> U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.2ns
> U0-M0C0T0 <> U17-M1C0T1 Data Latency : 60.5ns
> U0-M0C0T0 <> U19-M1C1T1 Data Latency : 60.6ns
> U0-M0C0T0 <> U21-M1C2T1 Data Latency : 60.4ns
> U0-M0C0T0 <> U23-M1C3T1 Data Latency : 60.6ns
> U0-M0C0T0 <> U25-M1C4T1 Data Latency : 59.8ns
> U0-M0C0T0 <> U27-M1C5T1 Data Latency : 60.3ns
> U0-M0C0T0 <> U29-M1C6T1 Data Latency : 59.4ns
> U0-M0C0T0 <> U31-M1C7T1 Data Latency : 59.9ns
> U2-M0C1T0 <> U4-M0C2T0 Data Latency : 21.7ns
> U2-M0C1T0 <> U6-M0C3T0 Data Latency : 22.9ns
> U2-M0C1T0 <> U8-M0C4T0 Data Latency : 21.1ns
> U2-M0C1T0 <> U10-M0C5T0 Data Latency : 22.1ns
> U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.4ns
> U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.9ns
> U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.7ns
> U2-M0C1T0 <> U18-M1C1T0 Data Latency : 56.5ns
> U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.0ns
> U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.4ns
> U2-M0C1T0 <> U24-M1C4T0 Data Latency : 57.8ns
> U2-M0C1T0 <> U26-M1C5T0 Data Latency : 57.9ns
> U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.3ns
> U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.0ns
> U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.4ns
> U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
> U2-M0C1T0 <> U5-M0C2T1 Data Latency : 19.1ns
> U2-M0C1T0 <> U7-M0C3T1 Data Latency : 20.7ns
> U2-M0C1T0 <> U9-M0C4T1 Data Latency : 19.8ns
> U2-M0C1T0 <> U11-M0C5T1 Data Latency : 21.3ns
> U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.4ns
> U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.9ns
> U2-M0C1T0 <> U17-M1C0T1 Data Latency : 61.4ns
> U2-M0C1T0 <> U19-M1C1T1 Data Latency : 61.0ns
> U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.5ns
> U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.6ns
> U2-M0C1T0 <> U25-M1C4T1 Data Latency : 59.4ns
> U2-M0C1T0 <> U27-M1C5T1 Data Latency : 58.6ns
> U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.9ns
> U2-M0C1T0 <> U31-M1C7T1 Data Latency : 60.3ns
> U4-M0C2T0 <> U6-M0C3T0 Data Latency : 21.1ns
> U4-M0C2T0 <> U8-M0C4T0 Data Latency : 21.9ns
> U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.4ns
> U4-M0C2T0 <> U12-M0C6T0 Data Latency : 21.4ns
> U4-M0C2T0 <> U14-M0C7T0 Data Latency : 20.8ns
> U4-M0C2T0 <> U16-M1C0T0 Data Latency : 60.3ns
> U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.5ns
> U4-M0C2T0 <> U20-M1C2T0 Data Latency : 59.9ns
> U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.8ns
> U4-M0C2T0 <> U24-M1C4T0 Data Latency : 58.5ns
> U4-M0C2T0 <> U26-M1C5T0 Data Latency : 57.8ns
> U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.2ns
> U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.7ns
> U4-M0C2T0 <> U1-M0C0T1 Data Latency : 19.4ns
> U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.2ns
> U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.9ns
> U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.7ns
> U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.4ns
> U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.4ns
> U4-M0C2T0 <> U13-M0C6T1 Data Latency : 21.3ns
> U4-M0C2T0 <> U15-M0C7T1 Data Latency : 21.1ns
> U4-M0C2T0 <> U17-M1C0T1 Data Latency : 57.8ns
> U4-M0C2T0 <> U19-M1C1T1 Data Latency : 59.4ns
> U4-M0C2T0 <> U21-M1C2T1 Data Latency : 59.9ns
> U4-M0C2T0 <> U23-M1C3T1 Data Latency : 60.0ns
> U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.6ns
> U4-M0C2T0 <> U27-M1C5T1 Data Latency : 59.2ns
> U4-M0C2T0 <> U29-M1C6T1 Data Latency : 58.4ns
> U4-M0C2T0 <> U31-M1C7T1 Data Latency : 59.2ns
> U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.4ns
> U6-M0C3T0 <> U10-M0C5T0 Data Latency : 22.0ns
> U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.1ns
> U6-M0C3T0 <> U14-M0C7T0 Data Latency : 22.3ns
> U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.4ns
> U6-M0C3T0 <> U18-M1C1T0 Data Latency : 60.7ns
> U6-M0C3T0 <> U20-M1C2T0 Data Latency : 57.8ns
> U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.0ns
> U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.7ns
> U6-M0C3T0 <> U26-M1C5T0 Data Latency : 59.1ns
> U6-M0C3T0 <> U28-M1C6T0 Data Latency : 58.6ns
> U6-M0C3T0 <> U30-M1C7T0 Data Latency : 58.7ns
> U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.0ns
> U6-M0C3T0 <> U3-M0C1T1 Data Latency : 21.0ns
> U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.7ns
> U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
> U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.4ns
> U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.9ns
> U6-M0C3T0 <> U13-M0C6T1 Data Latency : 21.1ns
> U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.5ns
> U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.8ns
> U6-M0C3T0 <> U19-M1C1T1 Data Latency : 59.4ns
> U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.2ns
> U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.1ns
> U6-M0C3T0 <> U25-M1C4T1 Data Latency : 60.4ns
> U6-M0C3T0 <> U27-M1C5T1 Data Latency : 59.6ns
> U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.6ns
> U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.4ns
> U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.0ns
> U8-M0C4T0 <> U12-M0C6T0 Data Latency : 21.4ns
> U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.1ns
> U8-M0C4T0 <> U16-M1C0T0 Data Latency : 58.2ns
> U8-M0C4T0 <> U18-M1C1T0 Data Latency : 58.1ns
> U8-M0C4T0 <> U20-M1C2T0 Data Latency : 57.1ns
> U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.8ns
> U8-M0C4T0 <> U24-M1C4T0 Data Latency : 59.6ns
> U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.3ns
> U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.3ns
> U8-M0C4T0 <> U30-M1C7T0 Data Latency : 59.2ns
> U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.4ns
> U8-M0C4T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.5ns
> U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.4ns
> U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
> U8-M0C4T0 <> U11-M0C5T1 Data Latency : 19.3ns
> U8-M0C4T0 <> U13-M0C6T1 Data Latency : 21.8ns
> U8-M0C4T0 <> U15-M0C7T1 Data Latency : 20.8ns
> U8-M0C4T0 <> U17-M1C0T1 Data Latency : 56.8ns
> U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.0ns
> U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.1ns
> U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.8ns
> U8-M0C4T0 <> U25-M1C4T1 Data Latency : 57.9ns
> U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.6ns
> U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.6ns
> U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.7ns
> U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.6ns
> U10-M0C5T0 <> U14-M0C7T0 Data Latency : 20.0ns
> U10-M0C5T0 <> U16-M1C0T0 Data Latency : 59.3ns
> U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.0ns
> U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.1ns
> U10-M0C5T0 <> U22-M1C3T0 Data Latency : 59.6ns
> U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.1ns
> U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.5ns
> U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.0ns
> U10-M0C5T0 <> U30-M1C7T0 Data Latency : 57.8ns
> U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.5ns
> U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.3ns
> U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.4ns
> U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.8ns
> U10-M0C5T0 <> U9-M0C4T1 Data Latency : 21.0ns
> U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.7ns
> U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.6ns
> U10-M0C5T0 <> U15-M0C7T1 Data Latency : 20.6ns
> U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.4ns
> U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.8ns
> U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.1ns
> U10-M0C5T0 <> U23-M1C3T1 Data Latency : 58.7ns
> U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.2ns
> U10-M0C5T0 <> U27-M1C5T1 Data Latency : 57.9ns
> U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.0ns
> U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.8ns
> U12-M0C6T0 <> U14-M0C7T0 Data Latency : 19.9ns
> U12-M0C6T0 <> U16-M1C0T0 Data Latency : 59.2ns
> U12-M0C6T0 <> U18-M1C1T0 Data Latency : 59.7ns
> U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.9ns
> U12-M0C6T0 <> U22-M1C3T0 Data Latency : 59.0ns
> U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.2ns
> U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.1ns
> U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.4ns
> U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.2ns
> U12-M0C6T0 <> U1-M0C0T1 Data Latency : 20.7ns
> U12-M0C6T0 <> U3-M0C1T1 Data Latency : 21.3ns
> U12-M0C6T0 <> U5-M0C2T1 Data Latency : 21.4ns
> U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.1ns
> U12-M0C6T0 <> U9-M0C4T1 Data Latency : 19.1ns
> U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.7ns
> U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
> U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.9ns
> U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.1ns
> U12-M0C6T0 <> U19-M1C1T1 Data Latency : 59.4ns
> U12-M0C6T0 <> U21-M1C2T1 Data Latency : 59.1ns
> U12-M0C6T0 <> U23-M1C3T1 Data Latency : 59.2ns
> U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.0ns
> U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.0ns
> U12-M0C6T0 <> U29-M1C6T1 Data Latency : 58.6ns
> U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.4ns
> U14-M0C7T0 <> U16-M1C0T0 Data Latency : 59.7ns
> U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.8ns
> U14-M0C7T0 <> U20-M1C2T0 Data Latency : 59.0ns
> U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.7ns
> U14-M0C7T0 <> U24-M1C4T0 Data Latency : 58.9ns
> U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.8ns
> U14-M0C7T0 <> U28-M1C6T0 Data Latency : 58.8ns
> U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.0ns
> U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.4ns
> U14-M0C7T0 <> U3-M0C1T1 Data Latency : 21.0ns
> U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.0ns
> U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.4ns
> U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.1ns
> U14-M0C7T0 <> U11-M0C5T1 Data Latency : 20.7ns
> U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.5ns
> U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
> U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.7ns
> U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.3ns
> U14-M0C7T0 <> U21-M1C2T1 Data Latency : 59.3ns
> U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.8ns
> U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.5ns
> U14-M0C7T0 <> U27-M1C5T1 Data Latency : 59.2ns
> U14-M0C7T0 <> U29-M1C6T1 Data Latency : 58.5ns
> U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
> U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.2ns
> U16-M1C0T0 <> U20-M1C2T0 Data Latency : 21.8ns
> U16-M1C0T0 <> U22-M1C3T0 Data Latency : 21.0ns
> U16-M1C0T0 <> U24-M1C4T0 Data Latency : 22.2ns
> U16-M1C0T0 <> U26-M1C5T0 Data Latency : 21.0ns
> U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
> U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.6ns
> U16-M1C0T0 <> U1-M0C0T1 Data Latency : 59.4ns
> U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.4ns
> U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.0ns
> U16-M1C0T0 <> U7-M0C3T1 Data Latency : 58.8ns
> U16-M1C0T0 <> U9-M0C4T1 Data Latency : 58.1ns
> U16-M1C0T0 <> U11-M0C5T1 Data Latency : 59.3ns
> U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.9ns
> U16-M1C0T0 <> U15-M0C7T1 Data Latency : 59.6ns
> U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
> U16-M1C0T0 <> U19-M1C1T1 Data Latency : 22.3ns
> U16-M1C0T0 <> U21-M1C2T1 Data Latency : 20.4ns
> U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.7ns
> U16-M1C0T0 <> U25-M1C4T1 Data Latency : 22.4ns
> U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.5ns
> U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
> U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.4ns
> U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.8ns
> U18-M1C1T0 <> U22-M1C3T0 Data Latency : 20.4ns
> U18-M1C1T0 <> U24-M1C4T0 Data Latency : 20.6ns
> U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.7ns
> U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.2ns
> U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.7ns
> U18-M1C1T0 <> U1-M0C0T1 Data Latency : 59.7ns
> U18-M1C1T0 <> U3-M0C1T1 Data Latency : 59.2ns
> U18-M1C1T0 <> U5-M0C2T1 Data Latency : 58.5ns
> U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.8ns
> U18-M1C1T0 <> U9-M0C4T1 Data Latency : 58.2ns
> U18-M1C1T0 <> U11-M0C5T1 Data Latency : 58.2ns
> U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.3ns
> U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.2ns
> U18-M1C1T0 <> U17-M1C0T1 Data Latency : 21.1ns
> U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.7ns
> U18-M1C1T0 <> U21-M1C2T1 Data Latency : 21.7ns
> U18-M1C1T0 <> U23-M1C3T1 Data Latency : 20.4ns
> U18-M1C1T0 <> U25-M1C4T1 Data Latency : 20.9ns
> U18-M1C1T0 <> U27-M1C5T1 Data Latency : 21.1ns
> U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.3ns
> U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.3ns
> U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.4ns
> U20-M1C2T0 <> U24-M1C4T0 Data Latency : 20.6ns
> U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.1ns
> U20-M1C2T0 <> U28-M1C6T0 Data Latency : 19.6ns
> U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.8ns
> U20-M1C2T0 <> U1-M0C0T1 Data Latency : 56.7ns
> U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.3ns
> U20-M1C2T0 <> U5-M0C2T1 Data Latency : 58.3ns
> U20-M1C2T0 <> U7-M0C3T1 Data Latency : 59.5ns
> U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.3ns
> U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.5ns
> U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.6ns
> U20-M1C2T0 <> U15-M0C7T1 Data Latency : 59.6ns
> U20-M1C2T0 <> U17-M1C0T1 Data Latency : 21.7ns
> U20-M1C2T0 <> U19-M1C1T1 Data Latency : 18.8ns
> U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.7ns
> U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
> U20-M1C2T0 <> U25-M1C4T1 Data Latency : 20.6ns
> U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.1ns
> U20-M1C2T0 <> U29-M1C6T1 Data Latency : 21.9ns
> U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.5ns
> U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.3ns
> U22-M1C3T0 <> U26-M1C5T0 Data Latency : 20.5ns
> U22-M1C3T0 <> U28-M1C6T0 Data Latency : 19.4ns
> U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.9ns
> U22-M1C3T0 <> U1-M0C0T1 Data Latency : 56.6ns
> U22-M1C3T0 <> U3-M0C1T1 Data Latency : 58.8ns
> U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.5ns
> U22-M1C3T0 <> U7-M0C3T1 Data Latency : 59.7ns
> U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.3ns
> U22-M1C3T0 <> U11-M0C5T1 Data Latency : 59.2ns
> U22-M1C3T0 <> U13-M0C6T1 Data Latency : 59.0ns
> U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.2ns
> U22-M1C3T0 <> U17-M1C0T1 Data Latency : 18.9ns
> U22-M1C3T0 <> U19-M1C1T1 Data Latency : 21.7ns
> U22-M1C3T0 <> U21-M1C2T1 Data Latency : 21.0ns
> U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.7ns
> U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.3ns
> U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.8ns
> U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
> U22-M1C3T0 <> U31-M1C7T1 Data Latency : 19.5ns
> U24-M1C4T0 <> U26-M1C5T0 Data Latency : 20.2ns
> U24-M1C4T0 <> U28-M1C6T0 Data Latency : 21.9ns
> U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.4ns
> U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.1ns
> U24-M1C4T0 <> U3-M0C1T1 Data Latency : 57.6ns
> U24-M1C4T0 <> U5-M0C2T1 Data Latency : 59.7ns
> U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.5ns
> U24-M1C4T0 <> U9-M0C4T1 Data Latency : 59.7ns
> U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.2ns
> U24-M1C4T0 <> U13-M0C6T1 Data Latency : 58.5ns
> U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.6ns
> U24-M1C4T0 <> U17-M1C0T1 Data Latency : 19.8ns
> U24-M1C4T0 <> U19-M1C1T1 Data Latency : 21.2ns
> U24-M1C4T0 <> U21-M1C2T1 Data Latency : 20.6ns
> U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.4ns
> U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.8ns
> U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.1ns
> U24-M1C4T0 <> U29-M1C6T1 Data Latency : 21.6ns
> U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.0ns
> U26-M1C5T0 <> U28-M1C6T0 Data Latency : 20.2ns
> U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.8ns
> U26-M1C5T0 <> U1-M0C0T1 Data Latency : 59.2ns
> U26-M1C5T0 <> U3-M0C1T1 Data Latency : 59.2ns
> U26-M1C5T0 <> U5-M0C2T1 Data Latency : 60.6ns
> U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.9ns
> U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.4ns
> U26-M1C5T0 <> U11-M0C5T1 Data Latency : 59.0ns
> U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.8ns
> U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.5ns
> U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.4ns
> U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.5ns
> U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.3ns
> U26-M1C5T0 <> U25-M1C4T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
> U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.5ns
> U26-M1C5T0 <> U31-M1C7T1 Data Latency : 22.4ns
> U28-M1C6T0 <> U30-M1C7T0 Data Latency : 21.5ns
> U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.9ns
> U28-M1C6T0 <> U3-M0C1T1 Data Latency : 60.6ns
> U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.2ns
> U28-M1C6T0 <> U7-M0C3T1 Data Latency : 58.9ns
> U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.5ns
> U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.4ns
> U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.3ns
> U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.3ns
> U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.4ns
> U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
> U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
> U28-M1C6T0 <> U23-M1C3T1 Data Latency : 19.6ns
> U28-M1C6T0 <> U25-M1C4T1 Data Latency : 21.5ns
> U28-M1C6T0 <> U27-M1C5T1 Data Latency : 20.2ns
> U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.7ns
> U28-M1C6T0 <> U31-M1C7T1 Data Latency : 21.9ns
> U30-M1C7T0 <> U1-M0C0T1 Data Latency : 59.6ns
> U30-M1C7T0 <> U3-M0C1T1 Data Latency : 60.8ns
> U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.6ns
> U30-M1C7T0 <> U7-M0C3T1 Data Latency : 60.1ns
> U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.8ns
> U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.6ns
> U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.1ns
> U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.4ns
> U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.3ns
> U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.5ns
> U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.5ns
> U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.3ns
> U30-M1C7T0 <> U25-M1C4T1 Data Latency : 19.7ns
> U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.9ns
> U30-M1C7T0 <> U29-M1C6T1 Data Latency : 20.4ns
> U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.6ns
> U1-M0C0T1 <> U3-M0C1T1 Data Latency : 22.7ns
> U1-M0C0T1 <> U5-M0C2T1 Data Latency : 22.0ns
> U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.9ns
> U1-M0C0T1 <> U9-M0C4T1 Data Latency : 19.4ns
> U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.8ns
> U1-M0C0T1 <> U13-M0C6T1 Data Latency : 20.7ns
> U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.3ns
> U1-M0C0T1 <> U17-M1C0T1 Data Latency : 59.1ns
> U1-M0C0T1 <> U19-M1C1T1 Data Latency : 58.5ns
> U1-M0C0T1 <> U21-M1C2T1 Data Latency : 56.9ns
> U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
> U1-M0C0T1 <> U25-M1C4T1 Data Latency : 58.0ns
> U1-M0C0T1 <> U27-M1C5T1 Data Latency : 58.3ns
> U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.8ns
> U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.9ns
> U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.5ns
> U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.9ns
> U3-M0C1T1 <> U9-M0C4T1 Data Latency : 21.2ns
> U3-M0C1T1 <> U11-M0C5T1 Data Latency : 21.4ns
> U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.5ns
> U3-M0C1T1 <> U15-M0C7T1 Data Latency : 21.0ns
> U3-M0C1T1 <> U17-M1C0T1 Data Latency : 61.9ns
> U3-M0C1T1 <> U19-M1C1T1 Data Latency : 61.1ns
> U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.0ns
> U3-M0C1T1 <> U23-M1C3T1 Data Latency : 56.8ns
> U3-M0C1T1 <> U25-M1C4T1 Data Latency : 61.4ns
> U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.5ns
> U3-M0C1T1 <> U29-M1C6T1 Data Latency : 59.3ns
> U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.6ns
> U5-M0C2T1 <> U7-M0C3T1 Data Latency : 21.3ns
> U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.9ns
> U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.4ns
> U5-M0C2T1 <> U13-M0C6T1 Data Latency : 21.1ns
> U5-M0C2T1 <> U15-M0C7T1 Data Latency : 20.8ns
> U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.7ns
> U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.6ns
> U5-M0C2T1 <> U21-M1C2T1 Data Latency : 60.4ns
> U5-M0C2T1 <> U23-M1C3T1 Data Latency : 59.0ns
> U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.3ns
> U5-M0C2T1 <> U27-M1C5T1 Data Latency : 57.9ns
> U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.3ns
> U5-M0C2T1 <> U31-M1C7T1 Data Latency : 60.1ns
> U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
> U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.9ns
> U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.2ns
> U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.5ns
> U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.5ns
> U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.3ns
> U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.5ns
> U7-M0C3T1 <> U23-M1C3T1 Data Latency : 59.0ns
> U7-M0C3T1 <> U25-M1C4T1 Data Latency : 59.5ns
> U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.8ns
> U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.7ns
> U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.4ns
> U9-M0C4T1 <> U11-M0C5T1 Data Latency : 19.4ns
> U9-M0C4T1 <> U13-M0C6T1 Data Latency : 21.8ns
> U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.5ns
> U9-M0C4T1 <> U17-M1C0T1 Data Latency : 60.3ns
> U9-M0C4T1 <> U19-M1C1T1 Data Latency : 59.7ns
> U9-M0C4T1 <> U21-M1C2T1 Data Latency : 57.1ns
> U9-M0C4T1 <> U23-M1C3T1 Data Latency : 59.8ns
> U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.7ns
> U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.2ns
> U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.6ns
> U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.7ns
> U11-M0C5T1 <> U13-M0C6T1 Data Latency : 20.3ns
> U11-M0C5T1 <> U15-M0C7T1 Data Latency : 22.4ns
> U11-M0C5T1 <> U17-M1C0T1 Data Latency : 56.9ns
> U11-M0C5T1 <> U19-M1C1T1 Data Latency : 58.1ns
> U11-M0C5T1 <> U21-M1C2T1 Data Latency : 59.1ns
> U11-M0C5T1 <> U23-M1C3T1 Data Latency : 58.2ns
> U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.4ns
> U11-M0C5T1 <> U27-M1C5T1 Data Latency : 59.6ns
> U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.9ns
> U11-M0C5T1 <> U31-M1C7T1 Data Latency : 59.0ns
> U13-M0C6T1 <> U15-M0C7T1 Data Latency : 19.1ns
> U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.1ns
> U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.7ns
> U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
> U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.6ns
> U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.3ns
> U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.4ns
> U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.0ns
> U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.4ns
> U15-M0C7T1 <> U17-M1C0T1 Data Latency : 59.2ns
> U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.1ns
> U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.6ns
> U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.4ns
> U15-M0C7T1 <> U25-M1C4T1 Data Latency : 58.5ns
> U15-M0C7T1 <> U27-M1C5T1 Data Latency : 59.6ns
> U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.3ns
> U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.0ns
> U17-M1C0T1 <> U19-M1C1T1 Data Latency : 20.9ns
> U17-M1C0T1 <> U21-M1C2T1 Data Latency : 22.8ns
> U17-M1C0T1 <> U23-M1C3T1 Data Latency : 21.9ns
> U17-M1C0T1 <> U25-M1C4T1 Data Latency : 21.2ns
> U17-M1C0T1 <> U27-M1C5T1 Data Latency : 19.6ns
> U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
> U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.4ns
> U19-M1C1T1 <> U21-M1C2T1 Data Latency : 21.6ns
> U19-M1C1T1 <> U23-M1C3T1 Data Latency : 22.9ns
> U19-M1C1T1 <> U25-M1C4T1 Data Latency : 20.5ns
> U19-M1C1T1 <> U27-M1C5T1 Data Latency : 21.2ns
> U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.7ns
> U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.8ns
> U21-M1C2T1 <> U23-M1C3T1 Data Latency : 21.1ns
> U21-M1C2T1 <> U25-M1C4T1 Data Latency : 20.7ns
> U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.3ns
> U21-M1C2T1 <> U29-M1C6T1 Data Latency : 20.9ns
> U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.8ns
> U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.4ns
> U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.7ns
> U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.5ns
> U23-M1C3T1 <> U31-M1C7T1 Data Latency : 22.1ns
> U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.1ns
> U25-M1C4T1 <> U29-M1C6T1 Data Latency : 21.9ns
> U25-M1C4T1 <> U31-M1C7T1 Data Latency : 20.4ns
> U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.5ns
> U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.9ns
> U29-M1C6T1 <> U31-M1C7T1 Data Latency : 21.8ns
> 1x 64bytes Blocks Bandwidth : 26.26GB/s
> 4x 64bytes Blocks Bandwidth : 28.6GB/s
> 4x 256bytes Blocks Bandwidth : 102GB/s
> 4x 1kB Blocks Bandwidth : 328GB/s
> 4x 4kB Blocks Bandwidth : 517.23GB/s
> 16x 4kB Blocks Bandwidth : 728.6GB/s
> 4x 64kB Blocks Bandwidth : 1001.46GB/s
> 16x 64kB Blocks Bandwidth : 606.71GB/s
> 8x 256kB Blocks Bandwidth : 616.7GB/s
> 4x 1MB Blocks Bandwidth : 606.11GB/s
> 16x 1MB Blocks Bandwidth : 25.43GB/s
> 8x 4MB Blocks Bandwidth : 19.15GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.92GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : A20F10-1009
> Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
> Platform Compliance : x64
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> URL : https://www.amd.com
> Speed : 4.92GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.92GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 8 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : A20F10-1009
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.
> 
> 
> View attachment 2489117
> 
> 
> View attachment 2489118
> 
> 
> 
> 
> 
> Code:
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-ThSiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 175.35GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Average Inter-Thread Latency : 39.9ns (9.5ns - 59.7ns)
> Inter-Thread (same Core) Latency : 9.7ns
> Inter-Core (same Module) Latency : 20.9ns
> Inter-Module (same Package) Latency : 58.5ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5.48GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1710.09MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 3.80ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 707.05kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 36.46MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 0.08ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.5ns
> U0-M0C0T0 <> U4-M0C2T0 Data Latency : 21.7ns
> U0-M0C0T0 <> U6-M0C3T0 Data Latency : 19.6ns
> U0-M0C0T0 <> U8-M0C4T0 Data Latency : 22.0ns
> U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.0ns
> U0-M0C0T0 <> U12-M0C6T0 Data Latency : 21.4ns
> U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
> U0-M0C0T0 <> U16-M1C0T0 Data Latency : 57.9ns
> U0-M0C0T0 <> U18-M1C1T0 Data Latency : 57.8ns
> U0-M0C0T0 <> U20-M1C2T0 Data Latency : 57.8ns
> U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.1ns
> U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.7ns
> U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.9ns
> U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.5ns
> U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.6ns
> U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.5ns
> U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.6ns
> U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.7ns
> U0-M0C0T0 <> U7-M0C3T1 Data Latency : 19.6ns
> U0-M0C0T0 <> U9-M0C4T1 Data Latency : 22.0ns
> U0-M0C0T0 <> U11-M0C5T1 Data Latency : 19.9ns
> U0-M0C0T0 <> U13-M0C6T1 Data Latency : 21.4ns
> U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.3ns
> U0-M0C0T0 <> U17-M1C0T1 Data Latency : 57.9ns
> U0-M0C0T0 <> U19-M1C1T1 Data Latency : 57.7ns
> U0-M0C0T0 <> U21-M1C2T1 Data Latency : 58.0ns
> U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.1ns
> U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.8ns
> U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.9ns
> U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.6ns
> U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.4ns
> U2-M0C1T0 <> U4-M0C2T0 Data Latency : 20.6ns
> U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.0ns
> U2-M0C1T0 <> U8-M0C4T0 Data Latency : 21.2ns
> U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.5ns
> U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
> U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.3ns
> U2-M0C1T0 <> U16-M1C0T0 Data Latency : 58.1ns
> U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.8ns
> U2-M0C1T0 <> U20-M1C2T0 Data Latency : 58.4ns
> U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.2ns
> U2-M0C1T0 <> U24-M1C4T0 Data Latency : 59.0ns
> U2-M0C1T0 <> U26-M1C5T0 Data Latency : 57.9ns
> U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.9ns
> U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.6ns
> U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.5ns
> U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
> U2-M0C1T0 <> U5-M0C2T1 Data Latency : 20.6ns
> U2-M0C1T0 <> U7-M0C3T1 Data Latency : 20.1ns
> U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
> U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.5ns
> U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.5ns
> U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.4ns
> U2-M0C1T0 <> U17-M1C0T1 Data Latency : 58.1ns
> U2-M0C1T0 <> U19-M1C1T1 Data Latency : 58.0ns
> U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.3ns
> U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.3ns
> U2-M0C1T0 <> U25-M1C4T1 Data Latency : 59.0ns
> U2-M0C1T0 <> U27-M1C5T1 Data Latency : 57.9ns
> U2-M0C1T0 <> U29-M1C6T1 Data Latency : 59.1ns
> U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.3ns
> U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.8ns
> U4-M0C2T0 <> U8-M0C4T0 Data Latency : 22.9ns
> U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.3ns
> U4-M0C2T0 <> U12-M0C6T0 Data Latency : 22.4ns
> U4-M0C2T0 <> U14-M0C7T0 Data Latency : 21.1ns
> U4-M0C2T0 <> U16-M1C0T0 Data Latency : 58.1ns
> U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.0ns
> U4-M0C2T0 <> U20-M1C2T0 Data Latency : 58.4ns
> U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.7ns
> U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.2ns
> U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.3ns
> U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.7ns
> U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.7ns
> U4-M0C2T0 <> U1-M0C0T1 Data Latency : 21.6ns
> U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
> U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.7ns
> U4-M0C2T0 <> U9-M0C4T1 Data Latency : 22.9ns
> U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.4ns
> U4-M0C2T0 <> U13-M0C6T1 Data Latency : 22.4ns
> U4-M0C2T0 <> U15-M0C7T1 Data Latency : 21.1ns
> U4-M0C2T0 <> U17-M1C0T1 Data Latency : 58.0ns
> U4-M0C2T0 <> U19-M1C1T1 Data Latency : 58.0ns
> U4-M0C2T0 <> U21-M1C2T1 Data Latency : 58.4ns
> U4-M0C2T0 <> U23-M1C3T1 Data Latency : 57.7ns
> U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.2ns
> U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.3ns
> U4-M0C2T0 <> U29-M1C6T1 Data Latency : 58.7ns
> U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.6ns
> U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
> U6-M0C3T0 <> U10-M0C5T0 Data Latency : 20.8ns
> U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.2ns
> U6-M0C3T0 <> U14-M0C7T0 Data Latency : 20.8ns
> U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.0ns
> U6-M0C3T0 <> U18-M1C1T0 Data Latency : 57.7ns
> U6-M0C3T0 <> U20-M1C2T0 Data Latency : 58.2ns
> U6-M0C3T0 <> U22-M1C3T0 Data Latency : 57.5ns
> U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.8ns
> U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.2ns
> U6-M0C3T0 <> U28-M1C6T0 Data Latency : 58.8ns
> U6-M0C3T0 <> U30-M1C7T0 Data Latency : 58.5ns
> U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.9ns
> U6-M0C3T0 <> U3-M0C1T1 Data Latency : 20.3ns
> U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.9ns
> U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.8ns
> U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
> U6-M0C3T0 <> U11-M0C5T1 Data Latency : 20.7ns
> U6-M0C3T0 <> U13-M0C6T1 Data Latency : 20.7ns
> U6-M0C3T0 <> U15-M0C7T1 Data Latency : 20.8ns
> U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.0ns
> U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.6ns
> U6-M0C3T0 <> U21-M1C2T1 Data Latency : 58.2ns
> U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
> U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.9ns
> U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.3ns
> U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.9ns
> U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.5ns
> U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.8ns
> U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.7ns
> U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.4ns
> U8-M0C4T0 <> U16-M1C0T0 Data Latency : 58.4ns
> U8-M0C4T0 <> U18-M1C1T0 Data Latency : 58.2ns
> U8-M0C4T0 <> U20-M1C2T0 Data Latency : 59.0ns
> U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.1ns
> U8-M0C4T0 <> U24-M1C4T0 Data Latency : 59.6ns
> U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.7ns
> U8-M0C4T0 <> U28-M1C6T0 Data Latency : 59.2ns
> U8-M0C4T0 <> U30-M1C7T0 Data Latency : 59.0ns
> U8-M0C4T0 <> U1-M0C0T1 Data Latency : 21.7ns
> U8-M0C4T0 <> U3-M0C1T1 Data Latency : 21.2ns
> U8-M0C4T0 <> U5-M0C2T1 Data Latency : 23.1ns
> U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.4ns
> U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
> U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.8ns
> U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.8ns
> U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.4ns
> U8-M0C4T0 <> U17-M1C0T1 Data Latency : 58.4ns
> U8-M0C4T0 <> U19-M1C1T1 Data Latency : 58.2ns
> U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.9ns
> U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.1ns
> U8-M0C4T0 <> U25-M1C4T1 Data Latency : 59.7ns
> U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.7ns
> U8-M0C4T0 <> U29-M1C6T1 Data Latency : 59.2ns
> U8-M0C4T0 <> U31-M1C7T1 Data Latency : 59.0ns
> U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.0ns
> U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.2ns
> U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.5ns
> U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.1ns
> U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.5ns
> U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.6ns
> U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.4ns
> U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.2ns
> U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.1ns
> U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.5ns
> U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.2ns
> U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.6ns
> U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.7ns
> U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
> U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.7ns
> U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.0ns
> U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.2ns
> U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.4ns
> U10-M0C5T0 <> U19-M1C1T1 Data Latency : 58.1ns
> U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.6ns
> U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.5ns
> U10-M0C5T0 <> U25-M1C4T1 Data Latency : 59.4ns
> U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
> U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.2ns
> U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.5ns
> U12-M0C6T0 <> U14-M0C7T0 Data Latency : 21.0ns
> U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.6ns
> U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.4ns
> U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.7ns
> U12-M0C6T0 <> U22-M1C3T0 Data Latency : 57.9ns
> U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.4ns
> U12-M0C6T0 <> U26-M1C5T0 Data Latency : 58.8ns
> U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.4ns
> U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.4ns
> U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.4ns
> U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
> U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.5ns
> U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.7ns
> U12-M0C6T0 <> U11-M0C5T1 Data Latency : 20.9ns
> U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
> U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.0ns
> U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.6ns
> U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.5ns
> U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.6ns
> U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.0ns
> U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.5ns
> U12-M0C6T0 <> U27-M1C5T1 Data Latency : 58.9ns
> U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.4ns
> U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.4ns
> U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.9ns
> U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.2ns
> U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.9ns
> U14-M0C7T0 <> U22-M1C3T0 Data Latency : 57.7ns
> U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.5ns
> U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
> U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.7ns
> U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
> U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.2ns
> U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.4ns
> U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.2ns
> U14-M0C7T0 <> U7-M0C3T1 Data Latency : 20.6ns
> U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.6ns
> U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.2ns
> U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.1ns
> U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.6ns
> U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.9ns
> U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.2ns
> U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.9ns
> U14-M0C7T0 <> U23-M1C3T1 Data Latency : 57.7ns
> U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.5ns
> U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.4ns
> U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.6ns
> U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
> U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.4ns
> U16-M1C0T0 <> U20-M1C2T0 Data Latency : 21.4ns
> U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.4ns
> U16-M1C0T0 <> U24-M1C4T0 Data Latency : 22.4ns
> U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.1ns
> U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.4ns
> U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.3ns
> U16-M1C0T0 <> U1-M0C0T1 Data Latency : 58.3ns
> U16-M1C0T0 <> U3-M0C1T1 Data Latency : 58.1ns
> U16-M1C0T0 <> U5-M0C2T1 Data Latency : 58.4ns
> U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.7ns
> U16-M1C0T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.1ns
> U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.8ns
> U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.6ns
> U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.7ns
> U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.4ns
> U16-M1C0T0 <> U21-M1C2T1 Data Latency : 21.4ns
> U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.4ns
> U16-M1C0T0 <> U25-M1C4T1 Data Latency : 22.4ns
> U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.1ns
> U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.4ns
> U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.3ns
> U18-M1C1T0 <> U20-M1C2T0 Data Latency : 20.4ns
> U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.8ns
> U18-M1C1T0 <> U24-M1C4T0 Data Latency : 21.1ns
> U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.4ns
> U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.3ns
> U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.3ns
> U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.9ns
> U18-M1C1T0 <> U3-M0C1T1 Data Latency : 58.0ns
> U18-M1C1T0 <> U5-M0C2T1 Data Latency : 58.4ns
> U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
> U18-M1C1T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.4ns
> U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.6ns
> U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.1ns
> U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.4ns
> U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.7ns
> U18-M1C1T0 <> U21-M1C2T1 Data Latency : 20.4ns
> U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.8ns
> U18-M1C1T0 <> U25-M1C4T1 Data Latency : 21.1ns
> U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.4ns
> U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.3ns
> U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.2ns
> U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
> U20-M1C2T0 <> U24-M1C4T0 Data Latency : 22.8ns
> U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.1ns
> U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.2ns
> U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.9ns
> U20-M1C2T0 <> U1-M0C0T1 Data Latency : 58.0ns
> U20-M1C2T0 <> U3-M0C1T1 Data Latency : 58.5ns
> U20-M1C2T0 <> U5-M0C2T1 Data Latency : 58.5ns
> U20-M1C2T0 <> U7-M0C3T1 Data Latency : 58.0ns
> U20-M1C2T0 <> U9-M0C4T1 Data Latency : 58.6ns
> U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
> U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.7ns
> U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.6ns
> U20-M1C2T0 <> U17-M1C0T1 Data Latency : 21.4ns
> U20-M1C2T0 <> U19-M1C1T1 Data Latency : 20.3ns
> U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.7ns
> U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
> U20-M1C2T0 <> U25-M1C4T1 Data Latency : 22.8ns
> U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.1ns
> U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.1ns
> U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.9ns
> U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.6ns
> U22-M1C3T0 <> U26-M1C5T0 Data Latency : 20.5ns
> U22-M1C3T0 <> U28-M1C6T0 Data Latency : 20.5ns
> U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.6ns
> U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.6ns
> U22-M1C3T0 <> U3-M0C1T1 Data Latency : 58.0ns
> U22-M1C3T0 <> U5-M0C2T1 Data Latency : 58.2ns
> U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.2ns
> U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.6ns
> U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.5ns
> U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
> U22-M1C3T0 <> U15-M0C7T1 Data Latency : 57.9ns
> U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.7ns
> U22-M1C3T0 <> U19-M1C1T1 Data Latency : 19.8ns
> U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.7ns
> U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.7ns
> U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.6ns
> U22-M1C3T0 <> U27-M1C5T1 Data Latency : 20.5ns
> U22-M1C3T0 <> U29-M1C6T1 Data Latency : 20.7ns
> U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.6ns
> U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.1ns
> U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
> U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.6ns
> U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.7ns
> U24-M1C4T0 <> U3-M0C1T1 Data Latency : 59.5ns
> U24-M1C4T0 <> U5-M0C2T1 Data Latency : 59.0ns
> U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.6ns
> U24-M1C4T0 <> U9-M0C4T1 Data Latency : 59.4ns
> U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
> U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.5ns
> U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.4ns
> U24-M1C4T0 <> U17-M1C0T1 Data Latency : 22.1ns
> U24-M1C4T0 <> U19-M1C1T1 Data Latency : 21.1ns
> U24-M1C4T0 <> U21-M1C2T1 Data Latency : 23.0ns
> U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.4ns
> U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.8ns
> U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.1ns
> U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
> U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.6ns
> U26-M1C5T0 <> U28-M1C6T0 Data Latency : 20.9ns
> U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.3ns
> U26-M1C5T0 <> U1-M0C0T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.6ns
> U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.8ns
> U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.0ns
> U26-M1C5T0 <> U9-M0C4T1 Data Latency : 59.2ns
> U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.0ns
> U26-M1C5T0 <> U13-M0C6T1 Data Latency : 59.0ns
> U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.5ns
> U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.4ns
> U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.4ns
> U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.5ns
> U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
> U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.7ns
> U26-M1C5T0 <> U29-M1C6T1 Data Latency : 20.9ns
> U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.3ns
> U28-M1C6T0 <> U30-M1C7T0 Data Latency : 20.9ns
> U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.9ns
> U28-M1C6T0 <> U3-M0C1T1 Data Latency : 59.1ns
> U28-M1C6T0 <> U5-M0C2T1 Data Latency : 59.2ns
> U28-M1C6T0 <> U7-M0C3T1 Data Latency : 58.5ns
> U28-M1C6T0 <> U9-M0C4T1 Data Latency : 59.3ns
> U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.7ns
> U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.5ns
> U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.3ns
> U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.4ns
> U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.3ns
> U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
> U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.2ns
> U28-M1C6T0 <> U25-M1C4T1 Data Latency : 22.9ns
> U28-M1C6T0 <> U27-M1C5T1 Data Latency : 20.9ns
> U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
> U28-M1C6T0 <> U31-M1C7T1 Data Latency : 20.9ns
> U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.5ns
> U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.7ns
> U30-M1C7T0 <> U5-M0C2T1 Data Latency : 59.0ns
> U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.0ns
> U30-M1C7T0 <> U9-M0C4T1 Data Latency : 59.5ns
> U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.3ns
> U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.4ns
> U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.9ns
> U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.2ns
> U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.3ns
> U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.0ns
> U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.4ns
> U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.8ns
> U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.2ns
> U30-M1C7T0 <> U29-M1C6T1 Data Latency : 21.1ns
> U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
> U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.6ns
> U1-M0C0T1 <> U5-M0C2T1 Data Latency : 21.6ns
> U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.6ns
> U1-M0C0T1 <> U9-M0C4T1 Data Latency : 22.0ns
> U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.0ns
> U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.4ns
> U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.2ns
> U1-M0C0T1 <> U17-M1C0T1 Data Latency : 57.9ns
> U1-M0C0T1 <> U19-M1C1T1 Data Latency : 57.7ns
> U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.8ns
> U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.3ns
> U1-M0C0T1 <> U25-M1C4T1 Data Latency : 58.8ns
> U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.9ns
> U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.6ns
> U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.5ns
> U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.8ns
> U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.1ns
> U3-M0C1T1 <> U9-M0C4T1 Data Latency : 21.3ns
> U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.6ns
> U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.6ns
> U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.6ns
> U3-M0C1T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U3-M0C1T1 <> U19-M1C1T1 Data Latency : 58.4ns
> U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.8ns
> U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.7ns
> U3-M0C1T1 <> U25-M1C4T1 Data Latency : 59.3ns
> U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.6ns
> U3-M0C1T1 <> U29-M1C6T1 Data Latency : 59.3ns
> U3-M0C1T1 <> U31-M1C7T1 Data Latency : 59.0ns
> U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
> U5-M0C2T1 <> U9-M0C4T1 Data Latency : 22.9ns
> U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.4ns
> U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.4ns
> U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.1ns
> U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.0ns
> U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.0ns
> U5-M0C2T1 <> U21-M1C2T1 Data Latency : 58.3ns
> U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
> U5-M0C2T1 <> U25-M1C4T1 Data Latency : 59.1ns
> U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.8ns
> U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.7ns
> U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.7ns
> U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.8ns
> U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.9ns
> U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.8ns
> U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.0ns
> U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.7ns
> U7-M0C3T1 <> U21-M1C2T1 Data Latency : 58.3ns
> U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
> U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.8ns
> U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.8ns
> U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.5ns
> U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.8ns
> U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.8ns
> U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.4ns
> U9-M0C4T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U9-M0C4T1 <> U19-M1C1T1 Data Latency : 58.2ns
> U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.9ns
> U9-M0C4T1 <> U23-M1C3T1 Data Latency : 58.1ns
> U9-M0C4T1 <> U25-M1C4T1 Data Latency : 59.7ns
> U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.6ns
> U9-M0C4T1 <> U29-M1C6T1 Data Latency : 59.3ns
> U9-M0C4T1 <> U31-M1C7T1 Data Latency : 59.0ns
> U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.0ns
> U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.2ns
> U11-M0C5T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U11-M0C5T1 <> U19-M1C1T1 Data Latency : 58.1ns
> U11-M0C5T1 <> U21-M1C2T1 Data Latency : 58.6ns
> U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.5ns
> U11-M0C5T1 <> U25-M1C4T1 Data Latency : 59.3ns
> U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.2ns
> U11-M0C5T1 <> U29-M1C6T1 Data Latency : 59.1ns
> U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.5ns
> U13-M0C6T1 <> U15-M0C7T1 Data Latency : 21.0ns
> U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.6ns
> U13-M0C6T1 <> U19-M1C1T1 Data Latency : 58.4ns
> U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.7ns
> U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.1ns
> U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.4ns
> U13-M0C6T1 <> U27-M1C5T1 Data Latency : 58.7ns
> U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.4ns
> U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.4ns
> U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.9ns
> U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.2ns
> U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.8ns
> U15-M0C7T1 <> U23-M1C3T1 Data Latency : 57.7ns
> U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.7ns
> U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.5ns
> U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.6ns
> U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.1ns
> U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.4ns
> U17-M1C0T1 <> U21-M1C2T1 Data Latency : 21.4ns
> U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.5ns
> U17-M1C0T1 <> U25-M1C4T1 Data Latency : 22.3ns
> U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.1ns
> U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.4ns
> U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.3ns
> U19-M1C1T1 <> U21-M1C2T1 Data Latency : 20.3ns
> U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.7ns
> U19-M1C1T1 <> U25-M1C4T1 Data Latency : 21.1ns
> U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.4ns
> U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.3ns
> U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.2ns
> U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
> U21-M1C2T1 <> U25-M1C4T1 Data Latency : 22.8ns
> U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.1ns
> U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.1ns
> U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.9ns
> U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.6ns
> U23-M1C3T1 <> U27-M1C5T1 Data Latency : 20.5ns
> U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.6ns
> U23-M1C3T1 <> U31-M1C7T1 Data Latency : 20.6ns
> U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.1ns
> U25-M1C4T1 <> U29-M1C6T1 Data Latency : 22.9ns
> U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.6ns
> U27-M1C5T1 <> U29-M1C6T1 Data Latency : 20.9ns
> U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.3ns
> U29-M1C6T1 <> U31-M1C7T1 Data Latency : 20.9ns
> 1x 64bytes Blocks Bandwidth : 26.57GB/s
> 4x 64bytes Blocks Bandwidth : 29.2GB/s
> 4x 256bytes Blocks Bandwidth : 103.48GB/s
> 4x 1kB Blocks Bandwidth : 324GB/s
> 4x 4kB Blocks Bandwidth : 522GB/s
> 16x 4kB Blocks Bandwidth : 669.66GB/s
> 4x 64kB Blocks Bandwidth : 1001.73GB/s
> 16x 64kB Blocks Bandwidth : 612.24GB/s
> 8x 256kB Blocks Bandwidth : 600.25GB/s
> 4x 1MB Blocks Bandwidth : 608.21GB/s
> 16x 1MB Blocks Bandwidth : 22.37GB/s
> 8x 4MB Blocks Bandwidth : 18.56GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.92GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : A20F10-1009
> Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
> Platform Compliance : x64
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> URL : https://www.amd.com
> Speed : 4.92GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.92GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 8 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : A20F10-1009
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.
> read Bandwidth : 175.35GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Average Inter-Thread Latency : 39.9ns (9.5ns - 59.7ns)
> Inter-Thread (same Core) Latency : 9.7ns
> Inter-Core (same Module) Latency : 20.9ns
> Inter-Module (same Package) Latency : 58.5ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5.48GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1710.09MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 3.80ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 707.05kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 36.46MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 0.08ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.5ns
> U0-M0C0T0 <> U4-M0C2T0 Data Latency : 21.7ns
> U0-M0C0T0 <> U6-M0C3T0 Data Latency : 19.6ns
> U0-M0C0T0 <> U8-M0C4T0 Data Latency : 22.0ns
> U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.0ns
> U0-M0C0T0 <> U12-M0C6T0 Data Latency : 21.4ns
> U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
> U0-M0C0T0 <> U16-M1C0T0 Data Latency : 57.9ns
> U0-M0C0T0 <> U18-M1C1T0 Data Latency : 57.8ns
> U0-M0C0T0 <> U20-M1C2T0 Data Latency : 57.8ns
> U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.1ns
> U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.7ns
> U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.9ns
> U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.5ns
> U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.6ns
> U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.5ns
> U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.6ns
> U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.7ns
> U0-M0C0T0 <> U7-M0C3T1 Data Latency : 19.6ns
> U0-M0C0T0 <> U9-M0C4T1 Data Latency : 22.0ns
> U0-M0C0T0 <> U11-M0C5T1 Data Latency : 19.9ns
> U0-M0C0T0 <> U13-M0C6T1 Data Latency : 21.4ns
> U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.3ns
> U0-M0C0T0 <> U17-M1C0T1 Data Latency : 57.9ns
> U0-M0C0T0 <> U19-M1C1T1 Data Latency : 57.7ns
> U0-M0C0T0 <> U21-M1C2T1 Data Latency : 58.0ns
> U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.1ns
> U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.8ns
> U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.9ns
> U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.6ns
> U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.4ns
> U2-M0C1T0 <> U4-M0C2T0 Data Latency : 20.6ns
> U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.0ns
> U2-M0C1T0 <> U8-M0C4T0 Data Latency : 21.2ns
> U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.5ns
> U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
> U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.3ns
> U2-M0C1T0 <> U16-M1C0T0 Data Latency : 58.1ns
> U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.8ns
> U2-M0C1T0 <> U20-M1C2T0 Data Latency : 58.4ns
> U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.2ns
> U2-M0C1T0 <> U24-M1C4T0 Data Latency : 59.0ns
> U2-M0C1T0 <> U26-M1C5T0 Data Latency : 57.9ns
> U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.9ns
> U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.6ns
> U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.5ns
> U2-M0C1T0 <> U3-M0C1T1 Data Latency : 10.0ns
> U2-M0C1T0 <> U5-M0C2T1 Data Latency : 20.6ns
> U2-M0C1T0 <> U7-M0C3T1 Data Latency : 20.1ns
> U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.1ns
> U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.5ns
> U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.5ns
> U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.4ns
> U2-M0C1T0 <> U17-M1C0T1 Data Latency : 58.1ns
> U2-M0C1T0 <> U19-M1C1T1 Data Latency : 58.0ns
> U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.3ns
> U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.3ns
> U2-M0C1T0 <> U25-M1C4T1 Data Latency : 59.0ns
> U2-M0C1T0 <> U27-M1C5T1 Data Latency : 57.9ns
> U2-M0C1T0 <> U29-M1C6T1 Data Latency : 59.1ns
> U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.3ns
> U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.8ns
> U4-M0C2T0 <> U8-M0C4T0 Data Latency : 22.9ns
> U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.3ns
> U4-M0C2T0 <> U12-M0C6T0 Data Latency : 22.4ns
> U4-M0C2T0 <> U14-M0C7T0 Data Latency : 21.1ns
> U4-M0C2T0 <> U16-M1C0T0 Data Latency : 58.1ns
> U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.0ns
> U4-M0C2T0 <> U20-M1C2T0 Data Latency : 58.4ns
> U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.7ns
> U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.2ns
> U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.3ns
> U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.7ns
> U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.7ns
> U4-M0C2T0 <> U1-M0C0T1 Data Latency : 21.6ns
> U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
> U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.7ns
> U4-M0C2T0 <> U9-M0C4T1 Data Latency : 22.9ns
> U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.4ns
> U4-M0C2T0 <> U13-M0C6T1 Data Latency : 22.4ns
> U4-M0C2T0 <> U15-M0C7T1 Data Latency : 21.1ns
> U4-M0C2T0 <> U17-M1C0T1 Data Latency : 58.0ns
> U4-M0C2T0 <> U19-M1C1T1 Data Latency : 58.0ns
> U4-M0C2T0 <> U21-M1C2T1 Data Latency : 58.4ns
> U4-M0C2T0 <> U23-M1C3T1 Data Latency : 57.7ns
> U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.2ns
> U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.3ns
> U4-M0C2T0 <> U29-M1C6T1 Data Latency : 58.7ns
> U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.6ns
> U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
> U6-M0C3T0 <> U10-M0C5T0 Data Latency : 20.8ns
> U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.2ns
> U6-M0C3T0 <> U14-M0C7T0 Data Latency : 20.8ns
> U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.0ns
> U6-M0C3T0 <> U18-M1C1T0 Data Latency : 57.7ns
> U6-M0C3T0 <> U20-M1C2T0 Data Latency : 58.2ns
> U6-M0C3T0 <> U22-M1C3T0 Data Latency : 57.5ns
> U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.8ns
> U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.2ns
> U6-M0C3T0 <> U28-M1C6T0 Data Latency : 58.8ns
> U6-M0C3T0 <> U30-M1C7T0 Data Latency : 58.5ns
> U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.9ns
> U6-M0C3T0 <> U3-M0C1T1 Data Latency : 20.3ns
> U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.9ns
> U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.8ns
> U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.7ns
> U6-M0C3T0 <> U11-M0C5T1 Data Latency : 20.7ns
> U6-M0C3T0 <> U13-M0C6T1 Data Latency : 20.7ns
> U6-M0C3T0 <> U15-M0C7T1 Data Latency : 20.8ns
> U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.0ns
> U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.6ns
> U6-M0C3T0 <> U21-M1C2T1 Data Latency : 58.2ns
> U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.5ns
> U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.9ns
> U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.3ns
> U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.9ns
> U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.5ns
> U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.8ns
> U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.7ns
> U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.4ns
> U8-M0C4T0 <> U16-M1C0T0 Data Latency : 58.4ns
> U8-M0C4T0 <> U18-M1C1T0 Data Latency : 58.2ns
> U8-M0C4T0 <> U20-M1C2T0 Data Latency : 59.0ns
> U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.1ns
> U8-M0C4T0 <> U24-M1C4T0 Data Latency : 59.6ns
> U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.7ns
> U8-M0C4T0 <> U28-M1C6T0 Data Latency : 59.2ns
> U8-M0C4T0 <> U30-M1C7T0 Data Latency : 59.0ns
> U8-M0C4T0 <> U1-M0C0T1 Data Latency : 21.7ns
> U8-M0C4T0 <> U3-M0C1T1 Data Latency : 21.2ns
> U8-M0C4T0 <> U5-M0C2T1 Data Latency : 23.1ns
> U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.4ns
> U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
> U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.8ns
> U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.8ns
> U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.4ns
> U8-M0C4T0 <> U17-M1C0T1 Data Latency : 58.4ns
> U8-M0C4T0 <> U19-M1C1T1 Data Latency : 58.2ns
> U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.9ns
> U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.1ns
> U8-M0C4T0 <> U25-M1C4T1 Data Latency : 59.7ns
> U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.7ns
> U8-M0C4T0 <> U29-M1C6T1 Data Latency : 59.2ns
> U8-M0C4T0 <> U31-M1C7T1 Data Latency : 59.0ns
> U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.0ns
> U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.2ns
> U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.5ns
> U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.1ns
> U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.5ns
> U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.6ns
> U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.4ns
> U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.2ns
> U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.1ns
> U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.5ns
> U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.2ns
> U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.6ns
> U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.7ns
> U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
> U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.7ns
> U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.0ns
> U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.2ns
> U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.4ns
> U10-M0C5T0 <> U19-M1C1T1 Data Latency : 58.1ns
> U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.6ns
> U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.5ns
> U10-M0C5T0 <> U25-M1C4T1 Data Latency : 59.4ns
> U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.3ns
> U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.2ns
> U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.5ns
> U12-M0C6T0 <> U14-M0C7T0 Data Latency : 21.0ns
> U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.6ns
> U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.4ns
> U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.7ns
> U12-M0C6T0 <> U22-M1C3T0 Data Latency : 57.9ns
> U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.4ns
> U12-M0C6T0 <> U26-M1C5T0 Data Latency : 58.8ns
> U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.4ns
> U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.4ns
> U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.4ns
> U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
> U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.5ns
> U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.7ns
> U12-M0C6T0 <> U11-M0C5T1 Data Latency : 20.9ns
> U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
> U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.0ns
> U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.6ns
> U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.5ns
> U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.6ns
> U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.0ns
> U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.5ns
> U12-M0C6T0 <> U27-M1C5T1 Data Latency : 58.9ns
> U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.4ns
> U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.4ns
> U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.9ns
> U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.2ns
> U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.9ns
> U14-M0C7T0 <> U22-M1C3T0 Data Latency : 57.7ns
> U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.5ns
> U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.5ns
> U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.7ns
> U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.1ns
> U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.2ns
> U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.4ns
> U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.2ns
> U14-M0C7T0 <> U7-M0C3T1 Data Latency : 20.6ns
> U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.6ns
> U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.2ns
> U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.1ns
> U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.6ns
> U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.9ns
> U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.2ns
> U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.9ns
> U14-M0C7T0 <> U23-M1C3T1 Data Latency : 57.7ns
> U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.5ns
> U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.4ns
> U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.6ns
> U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.1ns
> U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.4ns
> U16-M1C0T0 <> U20-M1C2T0 Data Latency : 21.4ns
> U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.4ns
> U16-M1C0T0 <> U24-M1C4T0 Data Latency : 22.4ns
> U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.1ns
> U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.4ns
> U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.3ns
> U16-M1C0T0 <> U1-M0C0T1 Data Latency : 58.3ns
> U16-M1C0T0 <> U3-M0C1T1 Data Latency : 58.1ns
> U16-M1C0T0 <> U5-M0C2T1 Data Latency : 58.4ns
> U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.7ns
> U16-M1C0T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.1ns
> U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.8ns
> U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.6ns
> U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.7ns
> U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.4ns
> U16-M1C0T0 <> U21-M1C2T1 Data Latency : 21.4ns
> U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.4ns
> U16-M1C0T0 <> U25-M1C4T1 Data Latency : 22.4ns
> U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.1ns
> U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.4ns
> U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.3ns
> U18-M1C1T0 <> U20-M1C2T0 Data Latency : 20.4ns
> U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.8ns
> U18-M1C1T0 <> U24-M1C4T0 Data Latency : 21.1ns
> U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.4ns
> U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.3ns
> U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.3ns
> U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.9ns
> U18-M1C1T0 <> U3-M0C1T1 Data Latency : 58.0ns
> U18-M1C1T0 <> U5-M0C2T1 Data Latency : 58.4ns
> U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.1ns
> U18-M1C1T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.4ns
> U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.6ns
> U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.1ns
> U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.4ns
> U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.7ns
> U18-M1C1T0 <> U21-M1C2T1 Data Latency : 20.4ns
> U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.8ns
> U18-M1C1T0 <> U25-M1C4T1 Data Latency : 21.1ns
> U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.4ns
> U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.3ns
> U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.2ns
> U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
> U20-M1C2T0 <> U24-M1C4T0 Data Latency : 22.8ns
> U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.1ns
> U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.2ns
> U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.9ns
> U20-M1C2T0 <> U1-M0C0T1 Data Latency : 58.0ns
> U20-M1C2T0 <> U3-M0C1T1 Data Latency : 58.5ns
> U20-M1C2T0 <> U5-M0C2T1 Data Latency : 58.5ns
> U20-M1C2T0 <> U7-M0C3T1 Data Latency : 58.0ns
> U20-M1C2T0 <> U9-M0C4T1 Data Latency : 58.6ns
> U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.2ns
> U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.7ns
> U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.6ns
> U20-M1C2T0 <> U17-M1C0T1 Data Latency : 21.4ns
> U20-M1C2T0 <> U19-M1C1T1 Data Latency : 20.3ns
> U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.7ns
> U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
> U20-M1C2T0 <> U25-M1C4T1 Data Latency : 22.8ns
> U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.1ns
> U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.1ns
> U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.9ns
> U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.6ns
> U22-M1C3T0 <> U26-M1C5T0 Data Latency : 20.5ns
> U22-M1C3T0 <> U28-M1C6T0 Data Latency : 20.5ns
> U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.6ns
> U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.6ns
> U22-M1C3T0 <> U3-M0C1T1 Data Latency : 58.0ns
> U22-M1C3T0 <> U5-M0C2T1 Data Latency : 58.2ns
> U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.2ns
> U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.6ns
> U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.5ns
> U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
> U22-M1C3T0 <> U15-M0C7T1 Data Latency : 57.9ns
> U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.7ns
> U22-M1C3T0 <> U19-M1C1T1 Data Latency : 19.8ns
> U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.7ns
> U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.7ns
> U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.6ns
> U22-M1C3T0 <> U27-M1C5T1 Data Latency : 20.5ns
> U22-M1C3T0 <> U29-M1C6T1 Data Latency : 20.7ns
> U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.6ns
> U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.1ns
> U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
> U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.6ns
> U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.7ns
> U24-M1C4T0 <> U3-M0C1T1 Data Latency : 59.5ns
> U24-M1C4T0 <> U5-M0C2T1 Data Latency : 59.0ns
> U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.6ns
> U24-M1C4T0 <> U9-M0C4T1 Data Latency : 59.4ns
> U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.9ns
> U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.5ns
> U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.4ns
> U24-M1C4T0 <> U17-M1C0T1 Data Latency : 22.1ns
> U24-M1C4T0 <> U19-M1C1T1 Data Latency : 21.1ns
> U24-M1C4T0 <> U21-M1C2T1 Data Latency : 23.0ns
> U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.4ns
> U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.8ns
> U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.1ns
> U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
> U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.6ns
> U26-M1C5T0 <> U28-M1C6T0 Data Latency : 20.9ns
> U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.3ns
> U26-M1C5T0 <> U1-M0C0T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.6ns
> U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.8ns
> U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.0ns
> U26-M1C5T0 <> U9-M0C4T1 Data Latency : 59.2ns
> U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.0ns
> U26-M1C5T0 <> U13-M0C6T1 Data Latency : 59.0ns
> U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.5ns
> U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.4ns
> U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.4ns
> U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.5ns
> U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
> U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.7ns
> U26-M1C5T0 <> U29-M1C6T1 Data Latency : 20.9ns
> U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.3ns
> U28-M1C6T0 <> U30-M1C7T0 Data Latency : 20.9ns
> U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.9ns
> U28-M1C6T0 <> U3-M0C1T1 Data Latency : 59.1ns
> U28-M1C6T0 <> U5-M0C2T1 Data Latency : 59.2ns
> U28-M1C6T0 <> U7-M0C3T1 Data Latency : 58.5ns
> U28-M1C6T0 <> U9-M0C4T1 Data Latency : 59.3ns
> U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.7ns
> U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.5ns
> U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.3ns
> U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.4ns
> U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.3ns
> U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.2ns
> U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.2ns
> U28-M1C6T0 <> U25-M1C4T1 Data Latency : 22.9ns
> U28-M1C6T0 <> U27-M1C5T1 Data Latency : 20.9ns
> U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
> U28-M1C6T0 <> U31-M1C7T1 Data Latency : 20.9ns
> U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.5ns
> U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.7ns
> U30-M1C7T0 <> U5-M0C2T1 Data Latency : 59.0ns
> U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.0ns
> U30-M1C7T0 <> U9-M0C4T1 Data Latency : 59.5ns
> U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.3ns
> U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.4ns
> U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.9ns
> U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.2ns
> U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.3ns
> U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.0ns
> U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.4ns
> U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.8ns
> U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.2ns
> U30-M1C7T0 <> U29-M1C6T1 Data Latency : 21.1ns
> U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
> U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.6ns
> U1-M0C0T1 <> U5-M0C2T1 Data Latency : 21.6ns
> U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.6ns
> U1-M0C0T1 <> U9-M0C4T1 Data Latency : 22.0ns
> U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.0ns
> U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.4ns
> U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.2ns
> U1-M0C0T1 <> U17-M1C0T1 Data Latency : 57.9ns
> U1-M0C0T1 <> U19-M1C1T1 Data Latency : 57.7ns
> U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.8ns
> U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.3ns
> U1-M0C0T1 <> U25-M1C4T1 Data Latency : 58.8ns
> U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.9ns
> U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.6ns
> U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.5ns
> U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.8ns
> U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.1ns
> U3-M0C1T1 <> U9-M0C4T1 Data Latency : 21.3ns
> U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.6ns
> U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.6ns
> U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.6ns
> U3-M0C1T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U3-M0C1T1 <> U19-M1C1T1 Data Latency : 58.4ns
> U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.8ns
> U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.7ns
> U3-M0C1T1 <> U25-M1C4T1 Data Latency : 59.3ns
> U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.6ns
> U3-M0C1T1 <> U29-M1C6T1 Data Latency : 59.3ns
> U3-M0C1T1 <> U31-M1C7T1 Data Latency : 59.0ns
> U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
> U5-M0C2T1 <> U9-M0C4T1 Data Latency : 22.9ns
> U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.4ns
> U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.4ns
> U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.1ns
> U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.0ns
> U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.0ns
> U5-M0C2T1 <> U21-M1C2T1 Data Latency : 58.3ns
> U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
> U5-M0C2T1 <> U25-M1C4T1 Data Latency : 59.1ns
> U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.8ns
> U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.7ns
> U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.7ns
> U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.8ns
> U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.9ns
> U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.8ns
> U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.0ns
> U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.7ns
> U7-M0C3T1 <> U21-M1C2T1 Data Latency : 58.3ns
> U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
> U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.8ns
> U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.8ns
> U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.5ns
> U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.8ns
> U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.8ns
> U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.4ns
> U9-M0C4T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U9-M0C4T1 <> U19-M1C1T1 Data Latency : 58.2ns
> U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.9ns
> U9-M0C4T1 <> U23-M1C3T1 Data Latency : 58.1ns
> U9-M0C4T1 <> U25-M1C4T1 Data Latency : 59.7ns
> U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.6ns
> U9-M0C4T1 <> U29-M1C6T1 Data Latency : 59.3ns
> U9-M0C4T1 <> U31-M1C7T1 Data Latency : 59.0ns
> U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.0ns
> U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.2ns
> U11-M0C5T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U11-M0C5T1 <> U19-M1C1T1 Data Latency : 58.1ns
> U11-M0C5T1 <> U21-M1C2T1 Data Latency : 58.6ns
> U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.5ns
> U11-M0C5T1 <> U25-M1C4T1 Data Latency : 59.3ns
> U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.2ns
> U11-M0C5T1 <> U29-M1C6T1 Data Latency : 59.1ns
> U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.5ns
> U13-M0C6T1 <> U15-M0C7T1 Data Latency : 21.0ns
> U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.6ns
> U13-M0C6T1 <> U19-M1C1T1 Data Latency : 58.4ns
> U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.7ns
> U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.1ns
> U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.4ns
> U13-M0C6T1 <> U27-M1C5T1 Data Latency : 58.7ns
> U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.4ns
> U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.4ns
> U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.9ns
> U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.2ns
> U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.8ns
> U15-M0C7T1 <> U23-M1C3T1 Data Latency : 57.7ns
> U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.7ns
> U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.5ns
> U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.6ns
> U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.1ns
> U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.4ns
> U17-M1C0T1 <> U21-M1C2T1 Data Latency : 21.4ns
> U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.5ns
> U17-M1C0T1 <> U25-M1C4T1 Data Latency : 22.3ns
> U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.1ns
> U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.4ns
> U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.3ns
> U19-M1C1T1 <> U21-M1C2T1 Data Latency : 20.3ns
> U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.7ns
> U19-M1C1T1 <> U25-M1C4T1 Data Latency : 21.1ns
> U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.4ns
> U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.3ns
> U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.2ns
> U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
> U21-M1C2T1 <> U25-M1C4T1 Data Latency : 22.8ns
> U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.1ns
> U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.1ns
> U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.9ns
> U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.6ns
> U23-M1C3T1 <> U27-M1C5T1 Data Latency : 20.5ns
> U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.6ns
> U23-M1C3T1 <> U31-M1C7T1 Data Latency : 20.6ns
> U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.1ns
> U25-M1C4T1 <> U29-M1C6T1 Data Latency : 22.9ns
> U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.6ns
> U27-M1C5T1 <> U29-M1C6T1 Data Latency : 20.9ns
> U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.3ns
> U29-M1C6T1 <> U31-M1C7T1 Data Latency : 20.9ns
> 1x 64bytes Blocks Bandwidth : 26.57GB/s
> 4x 64bytes Blocks Bandwidth : 29.2GB/s
> 4x 256bytes Blocks Bandwidth : 103.48GB/s
> 4x 1kB Blocks Bandwidth : 324GB/s
> 4x 4kB Blocks Bandwidth : 522GB/s
> 16x 4kB Blocks Bandwidth : 669.66GB/s
> 4x 64kB Blocks Bandwidth : 1001.73GB/s
> 16x 64kB Blocks Bandwidth : 612.24GB/s
> 8x 256kB Blocks Bandwidth : 600.25GB/s
> 4x 1MB Blocks Bandwidth : 608.21GB/s
> 16x 1MB Blocks Bandwidth : 22.37GB/s
> 8x 4MB Blocks Bandwidth : 18.56GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.92GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : A20F10-1009
> Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
> Platform Compliance : x64
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> URL : https://www.amd.com
> Speed : 4.92GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.92GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 8 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : A20F10-1009
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


Hi @KedarWolf. I just finish to testing.. I will continue tomorrow with more cycles, gaming, realbench, OOCT and I guess I'm done with 3800. Pretty similar results between two timings (SCL 2 or 4, ProcODT 48 to 40). SCL 2 will give me more write speed, SCL 4 more read speed. I should see the SiSandra Intercore and Inter-Thread Latency, but I don't know how to export it!! (yet) 

Loot at your timings with my memories. I would say, *Awesome! *










Thanks for your help!


----------



## Kitsune2431

Hey. I managed to stabilize my ram oc, but i have a weird issue(?). I was testing on external ssd with windows to go installed, some essential overclocking tools and few games. It passed every test i gave it for 16h+. Tm5 1usmus/tm5 anta extreme/small fft per thread and all threads/large fft all threads/y cruncher. Everything was fine on external ssd windows.

The issue appeared when i tried to do 2 last tm5 tests again, but on my main windows instead of external windows. Tm5 doesn't give errors, but just stops testing randomly. The timer is still going, but testing just stops. I think it happens when 1 cycle ends and ram gets freed, but new cycle doesn't start. Happens at random cycles (3,9,25,69)., but it doesn't stop if i disable ethernet (read thread with same issue on reddit, but there was no conclusion). With ethernet disabled it passes the tests and doesn't stop. Do you guys know if this is a sign of instability or just windows shenanigans? Tried turning off all programs and test, but it still happens. I think the only big difference between my windows installs is that my main windows has eset antivirus and external ssd just windows defender.

So, should i be worried and try to pinpoint the issue if my main windows passes the tests with ethernet disabled? Haven't encountered any other issues. No whea, no game crashes. Just tm5 stopping randomly with no errors.


----------



## Redwoodz

DemonAk said:


> Hello guys, need advice
> on my b550 taichi + ryzen 5950x + 4x32gb F4-3200C16Q-128GVK (hynix MJR) i can get stable overclock memory at 3533Mhz (dram v1.422, vsoc 1.12 llc1, vddg's auto) maximum, all what above (3600,3666,3733) not stable. played with cad bus, proc's, increased voltages dram to 1.462, soc to 1.2, vddg's to 1.15, vppm to 2.7, vdd to 1.9 but nothing, not stable. I Can pass karhu 1h (even 3 hours) or tm5 (1usmus config) but after reboot errors in tests almost immediately. maybe this is limit board or IMC and i need some special settings or timinngs =\
> View attachment 2489140
> View attachment 2489141
> View attachment 2489142
> 
> 
> 3533 stable
> 3666 training and boot ok with procodt 48om, rtt 7/2/1 or 7/3/1 and cad bus 40-20-24-24
> 3733 problem with memory training and cold boot


 4 DR sticks..... seems pretty fast to me but I have limitied experience trying to overclock 128 GB's of RAM. I think I would focus on lowering voltages and latency.


----------



## ivanchin99

Veii said:


> SCL 4, tWRRD 4
> tRRD_S 5, tRRD_L 7
> tRP 18, tRAS 40, tRC 58
> (calculate tRFC from the calculator for 16 gb dimms ~ B-2 mode. 580 tRFC)
> Last, try tWR 10 , tRTP 8. Maybe even tRTP 5 @ 1.46v
> 
> Example by cm87
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> You can use this set to stabilize voltages & push FCLK & BLCK Runs at
> 
> 
> 
> 
> www.overclock.net





Veii said:


> SCL 4, tWRRD 4
> tRRD_S 5, tRRD_L 7
> tRP 18, tRAS 40, tRC 58
> (calculate tRFC from the calculator for 16 gb dimms ~ B-2 mode. 580 tRFC)
> Last, try tWR 10 , tRTP 8. Maybe even tRTP 5 @ 1.46v
> 
> Example by cm87
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> You can use this set to stabilize voltages & push FCLK & BLCK Runs at
> 
> 
> 
> 
> www.overclock.net


Hi Veii, I was using the cm87 timings posted and had good results. VDIMM 1.5v
One difference is I couldn't get tRCDRD to go lower than 19 without a BSOD at windows startup. The other difference is drive strengths I use 60-20-30-20 instead which seems to work well for me.

1900 FCLK wont POST, anything above that I can post but will get a ton of WHEA error. 5800x is silver sample according to CTR. Hence my only is to tighten 1867 FCLK

With 2T GDM disable, I was able to complete TM5 1usmus 5 cycle test with no error, would need longer hours/cycles to confirm though.
However for 1T GDM disable, that's another story as I am seemingly 1 TM5 error from 100% stability... 
Any tips to reach that? Thank you in advance


----------



## madweazl

Doing some memory testing and received a "voltage cutoff choke" in TM5. Anyone know what that means and more importantly, how do to go about correcting it?


----------



## Senniha

Hi,i need some help to have stable memory setup with my taichi x370.I have 4 dimms 3333cl16 LPX corsair and are not identical.I m running with latest beta leaked bios P6.62 with 5900x.My goal is to set as high as i can without WHEA errors which occur above 3200/IF 1600 with this agesa 1.1.0.0.I dont know how to start with ryzen Calculator as my Hynix memory are my limit.I have manage to run them 3600cl16 but i got whea errors.When i start tuning with Ryzen Calculator recommadations noticed that i reduce WHEA errors but CINE20 test droped 700 points and while the test was running i heard coil wine from the mobo.This is happenig only above 3200/if 1600.Here my best tuned in 3200 without WHEA errors.

Any old friend from taichi @Veii ?Can you help?


----------



## RonLazer

Senniha said:


> Hi,i need some help to have stable memory setup with my taichi x370.I have 4 dimms 3333cl16 LPX corsair and are not identical.I m running with latest beta leaked bios P6.62 with 5900x.My goal is to set as high as i can without WHEA errors which occur above 3200/IF 1600 with this agesa 1.1.0.0.I dont know how to start with ryzen Calculator as my Hynix memory are my limit.I have manage to run them 3600cl16 but i got whea errors.When i start tuning with Ryzen Calculator recommadations noticed that i reduce WHEA errors but CINE20 test droped 700 points and while the test was running i heard coil wine from the mobo.This is happenig only above 3200/if 1600.Here my best tuned in 3200 without WHEA errors.
> 
> Any old friend from taichi @Veii ?Can you help?
> View attachment 2489206
> View attachment 2489207
> View attachment 2489208


I think your first step is to update your BIOS, AGESA 1.1.0 is ancient!


----------



## Pictus

DemonAk said:


> Hello guys, need advice
> on my b550 taichi + ryzen 5950x + 4x32gb F4-3200C16Q-128GVK (hynix MJR)


I know nothing about Hynix MJR, but your voltages are not good, check








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




Try:

VSOC = 1.1
CLDO VDDP = 0.900
VDDG CCD = 0.940
VDDG IDO = 1.020

My reference is








NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking...


AMD Ryzen Memory Tweaking & Overclocking Guide AMD Ryzen Memory Tweaking & Overclocking Guide MEMbench 0.6 README https://www.overclock.net/forum/27960952-post4412.html HOW USE MEMTEST in MEMbench https://www.overclock.net/forum/28069030-post5047.html DRAM Calculator for Ryzen™ 1.7.3 +...




www.overclock.net




and this








Ryzen Google Calculator!


Ryzen Google Calculator! https://docs.google.com/spreadsheets/d/1cJmhO62WHPLNKGBtsJV3BjdL-dcfJJeyhdSAoJmuzJE_ Created from "Google Sheets" For mobile users, you need the Google Sheets app. Made for me to learn about timings I'd appreciate it if anyone tell me any advice or improvements...




www.overclock.net


----------



## ManniX-ITA

Gave up trying to stabilize the 1T profile without the setup timings; while ClkDrvStr at 120Ohm helps the RTT fails after one hour no matter what.
Tried everything else possible but couldn't make it.

I've decided to focus on optimizing the 1T profile with setup timings.
Got it almost where I'd like to.

















I could reach even better scores with different timings but this one is better.
Because its *consistency in latency* is almost perfect.
This kit running at 1T with setup timings seems to be a little more erratic than the usual.

I'm probably just too much obsessed on it; latency jumping up and down every now and then without a reason hurts me 
I does happen also with GDM and 2T profiles when the timings are very tight; randomly the AIDA latency test goes off the chart.
If you run only the latency test, it can be very often correlated to a drop in CPU Clock frequency.
Sometimes there's a clock drop even if the latency is fine. It's big, down to 4.7 to 4.9 GHz.
And I noticed that if it happens at some point the latency will show an inconsistency, if you repeat again and again the test.

I think the CPU Clock reported by AIDA can be a spotter of slight misalignment in timings.
AIDA runs a small routine at bench start to detect the "top speed" of the CPU (Core 0).
It's probably not exactly the highest clock that can reach but the highest it can reach with that workload.
BoostTester and also Geekbench are not affected by memory timings.
They give the same result unless something is really wrong.
AIDA seems to use a very special routine.

Which is good cause it can be used as a reference and is somewhat consistent.
I guess that it makes PBO to struggle to boost the clock if there's something wrong with timings.
If the CPU Clock crashes down, that's very likely a sign that something is wrong. 
Or that Windows decided to run something on Core 0 just at that moment...

So my dogma now is: get the reported* CPU Clock* at the right frequency *AND *the* latency* in the range of +/- 0.1ns repeatedly.
Only this makes me confident the timings are right.
With this profile I could get endless runs with latency between +/- 0.1ns from 54.5ns and CPU Clock at 5100, sometimes 5075 MHz.
Other timings would give me better scores but would "ruin the experience" every now and then.

About the profile settings. I had to forget a lot of rules as always:

VDIMM 1.52V and VTT at 750mV, tested for 1h:30m with TM5, 53.1c temp
ProcODT and RTT; found the best as 34.3 Ohm 60-24-20-20. It has a huge impact on consistency, most of the time wasted to get it right
tRP-tRAS-tRC; 19-21-41/19-21-42 were performing worse than 14-28-42. Got good results with 13-27-41, especially in Write and Copy bandwidth and more stable
tRRDS/L; worse for consistency 4/4, set to 4/6
tCWL; no option, no POST at 12
tWTRS/L and tRTP/tWR; that's the combo where I had to focus a lot to get consistency. tRTP at 10 with tWTRS/L at 5/10 seems to do the magic. tWR below 14 would improve scores but mess consistency, higher just worse.
I have set back the previous "regular" timings; more Copy bandwidth and 0.1ns less in latency.
But CPU Clock crashes often to 5 GHz, almost always the Clock is around 5075 instead of 5100 MHz and repeating the test at some point the latency drops to 55ns.

You need a precise methodology to test latency with CPU Clock, prerequisites and timings are essential.
I had quite some fun with it but that's cause I'm Ab Normal as Igor would say 
Took some notes for myself to not forget but I have then adapted to a guide, if you have time to waste.



Spoiler: Guide to testing AIDA latency and CPU Clock



*Prerequisites:*

Clean Windows install
Either a dedicated benching install or you need to close every background app and stop every possible windows service
Better a dedicated install as you'll have to repeat everything every time you change a timing

AIDA64
You can use the free version but it'll take much much longer

PBO
This method does not work with static OC, you really need PBO
A very aggressive PBO setting; you need enough margin between a low boost and high boost to determine if something is wrong or not.
Example given with my 5950x:
Base boost clock (fmax): 5050 MHz
Boost clock Max: 125 MHz = 5175 MHz
AIDA CPU Clock reported speed:
Not acceptable: below 5000 MHz
Acceptable: 5000 MHz and beyond (low boost but still boost)
First full benchmark: 5100-5125 MHz
Latency test after 15 seconds of idle: 5100-5075 MHz




How much time Windows need after booting to begin idling
Windows is doing always some stuff for a while after the Desktop is available
You need to determine how many minutes it needs to settle, for me is 2-3 minutes
I have the CPU temperature displayed on the Debug Code LED screen on the Unify-X
If you don't have an external sensor, use HWInfo; open it and keep track of how much time is needed for the CPU Temperature to settle flat
DO NOT use HWInfo while normally testing with AIDA, only to gather the right timings; even on background will affect latency


How much time for the Core 0 to settle after a latency test and get a good boost
Latency test runs on Core 0; if it's still too hot from the previous the CPU Clock will be low
You need to find the sweet spot that gives you a repeatable high clock (if the timings are not right from start it'll be a bit though, you need to try many times)
My sweet spot is 15 seconds to get a repeatable 5100 MHz, sometimes 5075 MHz
Below 15 seconds could be 5025/5050 MHz, not high enough to test consistency. CPU could fail to boost, latency could be impacted
Longer wait will just consume too much time


*Methodology:*

Your goal is to verify the boost is working as expected and at the same time you get reproducible latency within 0.1ns from the average
First run at boot is a full benchmark, subsequent are only latency tests
Expected result from full benchmark
Read Bandwidth: almost top speed, I assume you start already from a good profile, mostly a matter of primaries
Write Bandwidth: doesn't matter if top speed, can be sacrificed for latency consistency (I did it). For single CCD doesn't matter as it's limited to around 30.4 GB/s
Copy Bandwidth: as above, doesn't matter if top speed, can be sacrificed for latency consistency.
But it's more interesting as it can be a spotter for bad timings; if it drops too low check for inconsistencies
Heavily impacted by tertiary timings, ideal to spot problems there

CPU Clock: should be the max boost clock that can be triggered by the AIDA workload; for me 5100-5125 MHz
Literally anything can cause a drop in reported frequency, a scheduled task, a background process, a butterfly on the other side of the planet, solar wind, a storm of Higgs bosons, Bill lurking on your intimate pictures... it's Windows
If it's not reporting the CPU Clock you expect, it could be a bad omen but also nothing, wait for the latency test consistency. If you have a doubt repeat
Sometimes despite there are no constraints like load or temperature the CPU will not boost as usual. No other option than repeat
If you have big inconsistencies at the first benchmark after boot it could be an issue with ProcODT, RTT, CAD BUS, VDIMM.
Big ones like dropping below 5 GHz are usually also evident during consistency checks with frequent latency drops Eg +1-2ns

If you are in doubt the current settings are limiting PBO boost close and re-open the Cache & Memory Benchmark window, run only the latency. And again a few times with 15-30 seconds apart to cool the Core 0
The bench windows seems static but it's not; if the benchmark ran at least once some refresh timer will run in background, it'll be very hard for the subsequent runs to detect again a clock that high as the first
Eg. First run when window is open I get 5100-5125 MHz clock, subsequent even with minutes idle from 5100-5075 MHz. Only a couple of times got a 5125 MHz.
Closing and reopening the window I get a very constant 5100-5125 MHz clock




Latency: if in the first test the latency is in the 0.1ns tolerance it's a good sign. But it's run after the Copy test, the CPU is hot. As above can be influenced by a whisper

Expected result from latency test
Repeat the test for at least 10-15 times; at this point you know already if you are good or not
Keep track of how many successful tests you can run consecutively; 4-5 times is not good, at least 10-12 you made it, endless is perfect
Some random hiccups in CPU Clock or latency can happen. It's Windows. But if they are too frequent, means something is bad
CPU Clock: should be the average to max boost clock, for me 5100-5075 MHz stable (more frequent 5100)
It can crash down sometimes; if it's still in the acceptable range, for me above 5000 MHz, and the latency is right then I count it successful.
Perfection is the king, first benchmark it can happen but you need to aim to zero occurrences in the latency only test

If it's an hard crash, for me below 5000 MHz, not good. Can still happen sometimes but must be really rare and not reproduceable

Latency: 
Only count successful if latency is in 0.1ns margin
Results in 0.2-0.4ns are fine but don't count them as successful for the consecutive series for consistency, suspect something is wrong if too frequent
+1-2ns means bad timings unless it's really a rare event. It's Windows!
Perfect is perfect; aim to an endless run after the first benchmark with latency and clock always in check



*Steps:*

Boot Windows and don't run anything else
If it's not a clean/benching install, close everything
Maybe prepare a batch file that kills and stops

Open AIDA64 and launch the Cache & Memory Benchmark
Move the mouse cursor over the Start Benchmark button
Wait enough time to have Windows settle Eg. 2 minutes
Click on the Start button (or press Alt+B)
Be careful not to move the mouse cursor, it will impact the CPU Clock routine

Check the results
Move the mouse cursor over the "ns" in the Latency box
Wait enough time for the CPU to settle in temperature, Eg. 30 seconds
Double click on "ns"
Be careful not to move the mouse cursor, it will impact the CPU Clock routine

Count the first run as successful if it meets the criteria, not to be worried if it's not as expected
Wait enough time for the CPU to settle in temperature to get a good boost, Eg. 15 seconds
Check the results
Repeat until you get at least 10-12 consecutive consistent results in a series
Perfect is endless run, you give up cause you are tired

If too many unacceptable results, reboot, change timings, repeat from start


----------



## Senniha

RonLazer said:


> I think your first step is to update your BIOS, AGESA 1.1.0 is ancient!


AMD blocked x370 so it will be this I'm afraid.Hope for mod version in the future.


----------



## jomama22

ManniX-ITA said:


> Gave up trying to stabilize the 1T profile without the setup timings; while ClkDrvStr at 120Ohm helps the RTT fails after one hour no matter what.
> Tried everything else possible but couldn't make it.
> 
> I've decided to focus on optimizing the 1T profile with setup timings.
> Got it almost where I'd like to.
> 
> View attachment 2489198
> View attachment 2489213
> 
> 
> I could reach even better scores with different timings but this one is better.
> Because its *consistency in latency* is almost perfect.
> This kit running at 1T with setup timings seems to be a little more erratic than the usual.
> 
> I'm probably just too much obsessed on it; latency jumping up and down every now and then without a reason hurts me
> I does happen also with GDM and 2T profiles when the timings are very tight; randomly the AIDA latency test goes off the chart.
> If you run only the latency test, it can be very often correlated to a drop in CPU Clock frequency.
> Sometimes there's a clock drop even if the latency is fine. It's big, down to 4.7 to 4.9 GHz.
> And I noticed that if it happens at some point the latency will show an inconsistency, if you repeat again and again the test.
> 
> I think the CPU Clock reported by AIDA can be a spotter of slight misalignment in timings.
> AIDA runs a small routine at bench start to detect the "top speed" of the CPU (Core 0).
> It's probably not exactly the highest clock that can reach but the highest it can reach with that workload.
> BoostTester and also Geekbench are not affected by memory timings.
> They give the same result unless something is really wrong.
> AIDA seems to use a very special routine.
> 
> Which is good cause it can be used as a reference and is somewhat consistent.
> I guess that it makes PBO to struggle to boost the clock if there's something wrong with timings.
> If the CPU Clock crashes down, that's very likely a sign that something is wrong.
> Or that Windows decided to run something on Core 0 just at that moment...
> 
> So my dogma now is: get the reported* CPU Clock* at the right frequency *AND *the* latency* in the range of +/- 0.1ns repeatedly.
> Only this makes me confident the timings are right.
> With this profile I could get endless runs with latency between +/- 0.1ns from 54.5ns and CPU Clock at 5100, sometimes 5075 MHz.
> Other timings would give me better scores but would "ruin the experience" every now and then.
> 
> About the profile settings. I had to forget a lot of rules as always:
> 
> VDIMM 1.52V and VTT at 750mV, tested for 1h:30m with TM5, 53.1c temp
> ProcODT and RTT; found the best as 34.3 Ohm 60-24-20-20. It has a huge impact on consistency, most of the time wasted to get it right
> tRP-tRAS-tRC; 19-21-41/19-21-42 were performing worse than 14-28-42. Got good results with 13-27-41, especially in Write and Copy bandwidth and more stable
> tRRDS/L; worse for consistency 4/4, set to 4/6
> tCWL; no option, no POST at 12
> tWTRS/L and tRTP/tWR; that's the combo where I had to focus a lot to get consistency. tRTP at 10 with tWTRS/L at 5/10 seems to do the magic. tWR below 14 would improve scores but mess consistency, higher just worse.
> I have set back the previous "regular" timings; more Copy bandwidth and 0.1ns less in latency.
> But CPU Clock crashes often to 5 GHz, almost always the Clock is around 5075 instead of 5100 MHz and repeating the test at some point the latency drops to 55ns.
> 
> You need a precise methodology to test latency with CPU Clock, prerequisites and timings are essential.
> I had quite some fun with it but that's cause I'm Ab Normal as Igor would say
> Took some notes for myself to not forget but I have then adapted to a guide, if you have time to waste.
> 
> 
> 
> Spoiler: Guide to testing AIDA latency and CPU Clock
> 
> 
> 
> *Prerequisites:*
> 
> Clean Windows install
> Either a dedicated benching install or you need to close every background app and stop every possible windows service
> Better a dedicated install as you'll have to repeat everything every time you change a timing
> 
> AIDA64
> You can use the free version but it'll take much much longer
> 
> PBO
> This method does not work with static OC, you really need PBO
> A very aggressive PBO setting; you need enough margin between a low boost and high boost to determine if something is wrong or not.
> Example given with my 5950x:
> Base boost clock (fmax): 5050 MHz
> Boost clock Max: 125 MHz = 5175 MHz
> AIDA CPU Clock reported speed:
> Not acceptable: below 5000 MHz
> Acceptable: 5000 MHz and beyond (low boost but still boost)
> First full benchmark: 5100-5125 MHz
> Latency test after 15 seconds of idle: 5100-5075 MHz
> 
> 
> 
> 
> How much time Windows need after booting to begin idling
> Windows is doing always some stuff for a while after the Desktop is available
> You need to determine how many minutes it needs to settle, for me is 2-3 minutes
> I have the CPU temperature displayed on the Debug Code LED screen on the Unify-X
> If you don't have an external sensor, use HWInfo; open it and keep track of how much time is needed for the CPU Temperature to settle flat
> DO NOT use HWInfo while normally testing with AIDA, only to gather the right timings; even on background will affect latency
> 
> 
> How much time for the Core 0 to settle after a latency test and get a good boost
> Latency test runs on Core 0; if it's still too hot from the previous the CPU Clock will be low
> You need to find the sweet spot that gives you a repeatable high clock (if the timings are not right from start it'll be a bit though, you need to try many times)
> My sweet spot is 15 seconds to get a repeatable 5100 MHz, sometimes 5075 MHz
> Below 15 seconds could be 5025/5050 MHz, not high enough to test consistency. CPU could fail to boost, latency could be impacted
> Longer wait will just consume too much time
> 
> 
> *Methodology:*
> 
> Your goal is to verify the boost is working as expected and at the same time you get reproducible latency within 0.1ns from the average
> First run at boot is a full benchmark, subsequent are only latency tests
> Expected result from full benchmark
> Read Bandwidth: almost top speed, I assume you start already from a good profile, mostly a matter of primaries
> Write Bandwidth: doesn't matter if top speed, can be sacrificed for latency consistency (I did it). For single CCD doesn't matter as it's limited to around 30.4 GB/s
> Copy Bandwidth: as above, doesn't matter if top speed, can be sacrificed for latency consistency.
> But it's more interesting as it can be a spotter for bad timings; if it drops too low check for inconsistencies
> Heavily impacted by tertiary timings, ideal to spot problems there
> 
> CPU Clock: should be the max boost clock that can be triggered by the AIDA workload; for me 5100-5125 MHz
> Literally anything can cause a drop in reported frequency, a scheduled task, a background process, a butterfly on the other side of the planet, solar wind, a storm of Higgs bosons, Bill lurking on your intimate pictures... it's Windows
> If it's not reporting the CPU Clock you expect, it could be a bad omen but also nothing, wait for the latency test consistency. If you have a doubt repeat
> Sometimes despite there are no constraints like load or temperature the CPU will not boost as usual. No other option than repeat
> If you have big inconsistencies at the first benchmark after boot it could be an issue with ProcODT, RTT, CAD BUS, VDIMM.
> Big ones like dropping below 5 GHz are usually also evident during consistency checks with frequent latency drops Eg +1-2ns
> 
> If you are in doubt the current settings are limiting PBO boost close and re-open the Cache & Memory Benchmark window, run only the latency. And again a few times with 15-30 seconds apart to cool the Core 0
> The bench windows seems static but it's not; if the benchmark ran at least once some refresh timer will run in background, it'll be very hard for the subsequent runs to detect again a clock that high as the first
> Eg. First run when window is open I get 5100-5125 MHz clock, subsequent even with minutes idle from 5100-5075 MHz. Only a couple of times got a 5125 MHz.
> Closing and reopening the window I get a very constant 5100-5125 MHz clock
> 
> 
> 
> 
> Latency: if in the first test the latency is in the 0.1ns tolerance it's a good sign. But it's run after the Copy test, the CPU is hot. As above can be influenced by a whisper
> 
> Expected result from latency test
> Repeat the test for at least 10-15 times; at this point you know already if you are good or not
> Keep track of how many successful tests you can run consecutively; 4-5 times is not good, at least 10-12 you made it, endless is perfect
> Some random hiccups in CPU Clock or latency can happen. It's Windows. But if they are too frequent, means something is bad
> CPU Clock: should be the average to max boost clock, for me 5100-5075 MHz stable (more frequent 5100)
> It can crash down sometimes; if it's still in the acceptable range, for me above 5000 MHz, and the latency is right then I count it successful.
> Perfection is the king, first benchmark it can happen but you need to aim to zero occurrences in the latency only test
> 
> If it's an hard crash, for me below 5000 MHz, not good. Can still happen sometimes but must be really rare and not reproduceable
> 
> Latency:
> Only count successful if latency is in 0.1ns margin
> Results in 0.2-0.4ns are fine but don't count them as successful for the consecutive series for consistency, suspect something is wrong if too frequent
> +1-2ns means bad timings unless it's really a rare event. It's Windows!
> Perfect is perfect; aim to an endless run after the first benchmark with latency and clock always in check
> 
> 
> 
> *Steps:*
> 
> Boot Windows and don't run anything else
> If it's not a clean/benching install, close everything
> Maybe prepare a batch file that kills and stops
> 
> Open AIDA64 and launch the Cache & Memory Benchmark
> Move the mouse cursor over the Start Benchmark button
> Wait enough time to have Windows settle Eg. 2 minutes
> Click on the Start button (or press Alt+B)
> Be careful not to move the mouse cursor, it will impact the CPU Clock routine
> 
> Check the results
> Move the mouse cursor over the "ns" in the Latency box
> Wait enough time for the CPU to settle in temperature, Eg. 30 seconds
> Double click on "ns"
> Be careful not to move the mouse cursor, it will impact the CPU Clock routine
> 
> Count the first run as successful if it meets the criteria, not to be worried if it's not as expected
> Wait enough time for the CPU to settle in temperature to get a good boost, Eg. 15 seconds
> Check the results
> Repeat until you get at least 10-12 consecutive consistent results in a series
> Perfect is endless run, you give up cause you are tired
> 
> If too many unacceptable results, reboot, change timings, repeat from start


I mean, you should just tighten timings with a static overclock then?

If be more concerned as to why L3 latency is at 10.3ns as opposed to the 9.9/10.0 it should be at for 5075/5100.


----------



## craxton

hey @Veii when you mentioned, using TM5 and C/O
with HWinfo while holding 4.85 all core/threads with 50mv offset
did you mean -50mv offset?

as it stands today, ive not updated bios, but i upped my C/O from 15,11,11,11,15,15 with 60mv pos offset????

to 17,13,13,15,18,18 with (amd voltage option) inside MSI bios
and to my surprise im stable in y-cruncher *didnt limit PBO just set to motherboard so its insanely high
and was HOT on my chip, but

none the less, voltages did NOT pass above 1.41 max but stayed around 1.37/39
to where as before would hit, around 1.49 peak but stayed around 1.42/45

(edit)--->(all cores and threads stayed within 4.85/4.82 so im fine with that at least)---<(edit)

did i miss or perhaps missunderstand what you said?

-50mv offset or positive 50mv offset to core???

yes im sorry to ask this, but im super confused and went back WAYYYY in the forum
but couldnt find where this was spoke about.



Spoiler



thought i had it bookmarked but i didnt. as i have 20 pages or so bookmarked that
youve noted for all to use...


----------



## craxton

weleh said:


> enabling LN2 actually fails post/boot.


same thing on both MSI boards i have, the x570 and B550 gaming edge wifi boards 
do the same thing with LN2 mode on (NO POST) on stable settings.



TimeDrapery said:


> Yes, the TM5 config is the "1usmus default" config file


would you mind uploading this 1usmus default config file?
yes, its on the net and i searched for HOURS and couldnt find it. 
found some in another language to which i couldn't understand at ALL 



DemonAk said:


> 4x32gb


ill have to agree with Time, 4x32 is ALOT of ram to get stable at any frequency really....
4x8 is hard enough (with agesa being changed so much internally)
while some have yet to do 2x8 or 2x16.
if your stable at 3533, then tighten timings and lower voltages
while adjusting CO. unless you can afford to drop 32gb?



Spoiler



whats stable on todays bios may not be stable on tomorrows release (figuratively speaking as seen with this latest 1.2.0.2 agesa release)


----------



## lmfodor

ManniX-ITA said:


> Gave up trying to stabilize the 1T profile without the setup timings; while ClkDrvStr at 120Ohm helps the RTT fails after one hour no matter what.
> Tried everything else possible but couldn't make it.
> 
> I've decided to focus on optimizing the 1T profile with setup timings.
> Got it almost where I'd like to.
> 
> View attachment 2489198
> View attachment 2489213
> 
> 
> 
> I could reach even better scores with different timings but this one is better.
> Because its *consistency in latency* is almost perfect.
> This kit running at 1T with setup timings seems to be a little more erratic than the usual.
> 
> I'm probably just too much obsessed on it; latency jumping up and down every now and then without a reason hurts me
> I does happen also with GDM and 2T profiles when the timings are very tight; randomly the AIDA latency test goes off the chart.
> If you run only the latency test, it can be very often correlated to a drop in CPU Clock frequency.
> Sometimes there's a clock drop even if the latency is fine. It's big, down to 4.7 to 4.9 GHz.
> And I noticed that if it happens at some point the latency will show an inconsistency, if you repeat again and again the test.
> 
> I think the CPU Clock reported by AIDA can be a spotter of slight misalignment in timings.
> AIDA runs a small routine at bench start to detect the "top speed" of the CPU (Core 0).
> It's probably not exactly the highest clock that can reach but the highest it can reach with that workload.
> BoostTester and also Geekbench are not affected by memory timings.
> They give the same result unless something is really wrong.
> AIDA seems to use a very special routine.
> 
> Which is good cause it can be used as a reference and is somewhat consistent.
> I guess that it makes PBO to struggle to boost the clock if there's something wrong with timings.
> If the CPU Clock crashes down, that's very likely a sign that something is wrong.
> Or that Windows decided to run something on Core 0 just at that moment...
> 
> So my dogma now is: get the reported* CPU Clock* at the right frequency *AND *the* latency* in the range of +/- 0.1ns repeatedly.
> Only this makes me confident the timings are right.
> With this profile I could get endless runs with latency between +/- 0.1ns from 54.5ns and CPU Clock at 5100, sometimes 5075 MHz.
> Other timings would give me better scores but would "ruin the experience" every now and then.
> 
> About the profile settings. I had to forget a lot of rules as always:
> 
> VDIMM 1.52V and VTT at 750mV, tested for 1h:30m with TM5, 53.1c temp
> ProcODT and RTT; found the best as 34.3 Ohm 60-24-20-20. It has a huge impact on consistency, most of the time wasted to get it right
> tRP-tRAS-tRC; 19-21-41/19-21-42 were performing worse than 14-28-42. Got good results with 13-27-41, especially in Write and Copy bandwidth and more stable
> tRRDS/L; worse for consistency 4/4, set to 4/6
> tCWL; no option, no POST at 12
> tWTRS/L and tRTP/tWR; that's the combo where I had to focus a lot to get consistency. tRTP at 10 with tWTRS/L at 5/10 seems to do the magic. tWR below 14 would improve scores but mess consistency, higher just worse.
> I have set back the previous "regular" timings; more Copy bandwidth and 0.1ns less in latency.
> But CPU Clock crashes often to 5 GHz, almost always the Clock is around 5075 instead of 5100 MHz and repeating the test at some point the latency drops to 55ns.
> 
> You need a precise methodology to test latency with CPU Clock, prerequisites and timings are essential.
> I had quite some fun with it but that's cause I'm Ab Normal as Igor would say
> Took some notes for myself to not forget but I have then adapted to a guide, if you have time to waste.
> 
> 
> 
> Spoiler: Guide to testing AIDA latency and CPU Clock
> 
> 
> 
> *Prerequisites:*
> 
> Clean Windows install
> Either a dedicated benching install or you need to close every background app and stop every possible windows service
> Better a dedicated install as you'll have to repeat everything every time you change a timing
> 
> AIDA64
> You can use the free version but it'll take much much longer
> 
> PBO
> This method does not work with static OC, you really need PBO
> A very aggressive PBO setting; you need enough margin between a low boost and high boost to determine if something is wrong or not.
> Example given with my 5950x:
> Base boost clock (fmax): 5050 MHz
> Boost clock Max: 125 MHz = 5175 MHz
> AIDA CPU Clock reported speed:
> Not acceptable: below 5000 MHz
> Acceptable: 5000 MHz and beyond (low boost but still boost)
> First full benchmark: 5100-5125 MHz
> Latency test after 15 seconds of idle: 5100-5075 MHz
> 
> 
> 
> 
> How much time Windows need after booting to begin idling
> Windows is doing always some stuff for a while after the Desktop is available
> You need to determine how many minutes it needs to settle, for me is 2-3 minutes
> I have the CPU temperature displayed on the Debug Code LED screen on the Unify-X
> If you don't have an external sensor, use HWInfo; open it and keep track of how much time is needed for the CPU Temperature to settle flat
> DO NOT use HWInfo while normally testing with AIDA, only to gather the right timings; even on background will affect latency
> 
> 
> How much time for the Core 0 to settle after a latency test and get a good boost
> Latency test runs on Core 0; if it's still too hot from the previous the CPU Clock will be low
> You need to find the sweet spot that gives you a repeatable high clock (if the timings are not right from start it'll be a bit though, you need to try many times)
> My sweet spot is 15 seconds to get a repeatable 5100 MHz, sometimes 5075 MHz
> Below 15 seconds could be 5025/5050 MHz, not high enough to test consistency. CPU could fail to boost, latency could be impacted
> Longer wait will just consume too much time
> 
> 
> *Methodology:*
> 
> Your goal is to verify the boost is working as expected and at the same time you get reproducible latency within 0.1ns from the average
> First run at boot is a full benchmark, subsequent are only latency tests
> Expected result from full benchmark
> Read Bandwidth: almost top speed, I assume you start already from a good profile, mostly a matter of primaries
> Write Bandwidth: doesn't matter if top speed, can be sacrificed for latency consistency (I did it). For single CCD doesn't matter as it's limited to around 30.4 GB/s
> Copy Bandwidth: as above, doesn't matter if top speed, can be sacrificed for latency consistency.
> But it's more interesting as it can be a spotter for bad timings; if it drops too low check for inconsistencies
> Heavily impacted by tertiary timings, ideal to spot problems there
> 
> CPU Clock: should be the max boost clock that can be triggered by the AIDA workload; for me 5100-5125 MHz
> Literally anything can cause a drop in reported frequency, a scheduled task, a background process, a butterfly on the other side of the planet, solar wind, a storm of Higgs bosons, Bill lurking on your intimate pictures... it's Windows
> If it's not reporting the CPU Clock you expect, it could be a bad omen but also nothing, wait for the latency test consistency. If you have a doubt repeat
> Sometimes despite there are no constraints like load or temperature the CPU will not boost as usual. No other option than repeat
> If you have big inconsistencies at the first benchmark after boot it could be an issue with ProcODT, RTT, CAD BUS, VDIMM.
> Big ones like dropping below 5 GHz are usually also evident during consistency checks with frequent latency drops Eg +1-2ns
> 
> If you are in doubt the current settings are limiting PBO boost close and re-open the Cache & Memory Benchmark window, run only the latency. And again a few times with 15-30 seconds apart to cool the Core 0
> The bench windows seems static but it's not; if the benchmark ran at least once some refresh timer will run in background, it'll be very hard for the subsequent runs to detect again a clock that high as the first
> Eg. First run when window is open I get 5100-5125 MHz clock, subsequent even with minutes idle from 5100-5075 MHz. Only a couple of times got a 5125 MHz.
> Closing and reopening the window I get a very constant 5100-5125 MHz clock
> 
> 
> 
> 
> Latency: if in the first test the latency is in the 0.1ns tolerance it's a good sign. But it's run after the Copy test, the CPU is hot. As above can be influenced by a whisper
> 
> Expected result from latency test
> Repeat the test for at least 10-15 times; at this point you know already if you are good or not
> Keep track of how many successful tests you can run consecutively; 4-5 times is not good, at least 10-12 you made it, endless is perfect
> Some random hiccups in CPU Clock or latency can happen. It's Windows. But if they are too frequent, means something is bad
> CPU Clock: should be the average to max boost clock, for me 5100-5075 MHz stable (more frequent 5100)
> It can crash down sometimes; if it's still in the acceptable range, for me above 5000 MHz, and the latency is right then I count it successful.
> Perfection is the king, first benchmark it can happen but you need to aim to zero occurrences in the latency only test
> 
> If it's an hard crash, for me below 5000 MHz, not good. Can still happen sometimes but must be really rare and not reproduceable
> 
> Latency:
> Only count successful if latency is in 0.1ns margin
> Results in 0.2-0.4ns are fine but don't count them as successful for the consecutive series for consistency, suspect something is wrong if too frequent
> +1-2ns means bad timings unless it's really a rare event. It's Windows!
> Perfect is perfect; aim to an endless run after the first benchmark with latency and clock always in check
> 
> 
> 
> *Steps:*
> 
> Boot Windows and don't run anything else
> If it's not a clean/benching install, close everything
> Maybe prepare a batch file that kills and stops
> 
> Open AIDA64 and launch the Cache & Memory Benchmark
> Move the mouse cursor over the Start Benchmark button
> Wait enough time to have Windows settle Eg. 2 minutes
> Click on the Start button (or press Alt+B)
> Be careful not to move the mouse cursor, it will impact the CPU Clock routine
> 
> Check the results
> Move the mouse cursor over the "ns" in the Latency box
> Wait enough time for the CPU to settle in temperature, Eg. 30 seconds
> Double click on "ns"
> Be careful not to move the mouse cursor, it will impact the CPU Clock routine
> 
> Count the first run as successful if it meets the criteria, not to be worried if it's not as expected
> Wait enough time for the CPU to settle in temperature to get a good boost, Eg. 15 seconds
> Check the results
> Repeat until you get at least 10-12 consecutive consistent results in a series
> Perfect is endless run, you give up cause you are tired
> 
> If too many unacceptable results, reboot, change timings, repeat from start


Hi Mannix.

The first thing I can tell you is that without a doubt you should have the best combined results between bandwidth and latency for 3800. I have a healthy envy about how your memory achieves 1T GDM disabled. I still blame myself for having paid so much for my memories that they claim to be so good but I could have researched a little more and saved a lot of USD! So you can't complain.

Regarding AIDA, the same thing happens to all of us, it is a ritual to try, in fact I always executed HWInfo, or sometimes I had ZenTimmings open. Wouldn't it be better to try Safe Mode instead of doing all that? I just asked KedarWolf to share his BenchOS image with me to build a dual boot and test from Windows just for Benchs. Because killing all the services on a Gamings PC sometimes gets annoying. For now I have 110 services (I lowered it from 250), I have practically nothing installed, but every time I want to play I need to enable XBOX and Gaming Services, EA Services for EA Desktop and so on. Better a dual boot, old windows, debloated and ready.

I go back to what I told you at the beginning, you have the best bandwidth bench and the best latency at 3800, I don't know if someone has surpassed it with 2 CCDs, what you can try is by deactivating the CCD2 and see how it turns out. You would have a 5800x. And in my case, I still think that my mother or perhaps repeated and copied VRMs configuration is not correct. Otherwise, I buy either the dark Hero, which I know doesn't fail, although it doesn't give me anything new, or the Unify-X, which doesn't have Daisy Chain, and for me it has a better VRM controller from what I saw in Buildzoid and also a lot of settings that I don't have in Asus. For me, that only have an RTX 3808 and 3TB in two NVME would be more than enough. I will miss the safe boot button, but lucky it has the clear CMOS! But the real goal is to run at 4000MT/s, and it doesn't depend on motherboards, just AMD BIOS I guess.


----------



## GribblyStick

One thing that is not clear to me is the pbo limits. I have seen gamernexus set these to motherboard limits, which are way beyond what the FUSE limits are. Assuming Fuse limits are indeed a thing, then why are people talking about different settings for TDP,PPT,EDC? You could set set everything to max and the chip would still not be at risk? Might thermal throttle at worst, but then you could lower TDP until it stop, that would still not damage the CPU


----------



## ManniX-ITA

jomama22 said:


> I mean, you should just tighten timings with a static overclock then?
> 
> If be more concerned as to why L3 latency is at 10.3ns as opposed to the 9.9/10.0 it should be at for 5075/5100.


That would literally hiding the dust under the carpet 
You wouldn't see PBO crashing but still something under the hood wouldn't be optimal.
Didn't try it but I guess the latency would be randomly erratic.

Never managed to get the L3 latency below 10ns, why you link it to the frequency?
So far I managed to manipulate it only with the cTDP and EDC limits.
But it's very dependent on the AGESA, I can't get it much better with this BIOS.
If I raise the EDC the performances will suffer a lot.
Except the nice values in AIDA never had better scores in anything with a speedier L3.



craxton said:


> would you mind uploading this 1usmus default config file?
> yes, its on the net and i searched for HOURS and couldnt find it.
> found some in another language to which i couldn't understand at ALL







__





TM5 - Google Drive







drive.google.com





For this GINYF 
He published it here, advanced search filtered for 1usmus, term: v3 config 



lmfodor said:


> The first thing I can tell you is that without a doubt you should have the best combined results between bandwidth and latency for 3800. I have a healthy envy about how your memory achieves 1T GDM disabled. I still blame myself for having paid so much for my memories that they claim to be so good but I could have researched a little more and saved a lot of USD! So you can't complain.


I almost bought your kit, it could become a good one if AMD fixes high FCLK... 
Yes I achieve true 1T but it's more a "prize" than anything else.
Except a bit better write and copy bandwidth it's not better than a 2T profile and needs a lot more voltage!



lmfodor said:


> Regarding AIDA, the same thing happens to all of us, it is a ritual to try, in fact I always executed HWInfo, or sometimes I had ZenTimmings open. Wouldn't it be better to try Safe Mode instead of doing all that? I just asked KedarWolf to share his BenchOS image with me to build a dual boot and test from Windows just for Benchs. Because killing all the services on a Gamings PC sometimes gets annoying. For now I have 110 services (I lowered it from 250), I have practically nothing installed, but every time I want to play I need to enable XBOX and Gaming Services, EA Services for EA Desktop and so on. Better a dual boot, old windows, debloated and ready.


Much better a benching install.
Buy a cheap USB SSD and use it only for the benching install.
You can set offline the M.2/SATA drives and avoid any kind of corruption on the important stuff.
Plus Windows booting from USB is super sturdy, it doesn't get corrupted by BSOD and the most terrible things you can do.
I have only once corrupted TM5 config, that's all.
There are free tools to create the WinToGo install:





Create Windows 11/10/8/8.1/7 Bootable USB with AOMEI Partition Assistant


Windows To Go Creator can help you make a bootable USB from Windows 11/10/8/8.1/7 ISO/ESD file. Then, you can boot Windows 10/8/8.1/7 from it anywhere and anytime.



www.diskpart.com







lmfodor said:


> I go back to what I told you at the beginning, you have the best bandwidth bench and the best latency at 3800, I don't know if someone has surpassed it with 2 CCDs, what you can try is by deactivating the CCD2 and see how it turns out. You would have a 5800x. And in my case, I still think that my mother or perhaps repeated and copied VRMs configuration is not correct. Otherwise, I buy either the dark Hero, which I know doesn't fail, although it doesn't give me anything new, or the Unify-X, which doesn't have Daisy Chain, and for me it has a better VRM controller from what I saw in Buildzoid and also a lot of settings that I don't have in Asus. For me, that only have an RTX 3808 and 3TB in two NVME would be more than enough. I will miss the safe boot button, but lucky it has the clear CMOS! But the real goal is to run at 4000MT/s, and it doesn't depend on motherboards, just AMD BIOS I guess.


A dual CCD in single CCD mode is not the same as a true 1CCD.
I could achieve down to 52.4ns, there's a 1ns penalty sadly.
The Unify-X is very annoying due to the BIOS bugs and the lack of some features but it's very solid and a great performer.
In the running SuperPI Zen Low Clock competition Top 10, aimed at the best RAM OC, the Unify-X is in position 3,4,7, the Dark Hero in position 6,8,10
All good results but seems for crazy stuff it does have the lead.
If/when AMD fixes the FCLK then the real fun will start.


----------



## ManniX-ITA

GribblyStick said:


> One thing that is not clear to me is the pbo limits. I have seen gamernexus set these to motherboard limits, which are way beyond what the FUSE limits are. Assuming Fuse limits are indeed a thing, then why are people talking about different settings for TDP,PPT,EDC? You could set set everything to max and the chip would still not be at risk? Might thermal throttle at worst, but then you could lower TDP until it stop, that would still not damage the CPU


The limits will not only limit but also shape the PBO boost curve.
They are factors PBO will use to take decisions.
How they influence it depends on the CPU sample but most importantly on the cooling as the thermal factor can vary a lot depending on it.

You should try different limits and run a suite of benchmarks to see how it works for you.


----------



## Veii

lmfodor said:


> r. I see many times that @Veii tell us when a value is not stable, but not by rules, but by his understanding how it works, for example
> 
> 
> lmfodor said:
> 
> 
> 
> So if we talk about recommended values, it is trial and error, but if we talk about relationships, and since everything is related, it can better find a way to test. For example, lowering the tRCDRD
> 
> 
> lmfodor said:
> 
> 
> 
> But how do I determine the voltage increase? How do I know if 1.5 is enought? Or do I have to go to 1.55 or 1.6? I mean, because this configuration that we are both running now, in my case I´m at 1.5v and you are at 1.49V. However, I always received recommendations not to lower than 1.55! So I always had errors due to overvoltage, not due to lack of it. There is the problem, which is what I would like to understand. The relationships.
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

When it comes to minimum required voltage for 3800C14-14-14, it depends on:

The PCB quality (layers = fixed amount of leakage & heat = variable amount of leakage)
A general rule of understanding how tRP 14 behaves by frequency
And the RTT's.

RTT_NOM should be increased if you increase voltage (lower divider, stronger value)
RTT_WR is dynamic ODT and a whole layer ontop of the current ODT & powerdown signal path (dynamic)
RTT_PARK depends on the PCB quality and will increase heat if you increase it. Requirements depend on the IMC's FW and preconfigured RZQ values (more to it later)

3800 MT/s can need between 1.5-1.6v , usually it's 1.5v and above
But 1.5 flat is only at 731 (DR) or 005 (SR) ~ where after 1.51-1.52 you start to see instability , till you use 705 then 1.54v is your instability range
Higher voltage either doesn't work because of heat or start to give you fully dropped channels at 1.54-1.55. If this happens, 1..56+ would kill the PCB.
It depends

Take a look at this current set








RTT_PARK got lowered to /7, RTT_NOM got increased to /5 . Initially 6/3/6 where running @ 1.66v
Now it's 1.65v, as NOM seems to just cover the voltage requirements of the one step "lower" PARK

Also take a look at:


Spoiler: this old GDM comparison














It needed 1.6v to finally reach stable 14-14-14
Not because the set would require it (i mean also), but because RTT_PARK was weaker
(706 instead of 005 ~ didn't want to run 1.55+ on my A0's at 005 or even 705. I like this memory ~ but VDIMM requirements increased with weaker PARK)
Soo more VDIMM was needed ~ but it absolutely doesn't mean, that it causes more heat. Voltage on it's own doesn't translate to heat.
It's the Amperage that arrives ~ depending on resistance and impedances throughout the chain.
Except that timings love more voltage, soo it can be beneficial to take this route instead of the easier 005 / 731 route
============================================================
But there is a caveat, that bothers me the last 3 days (comparing my current set above)
IMC FW changed, and some scaling changed. 200% sure on that a this point 
Compare these two results:








Why does one fail but one passes at "perfect" tFAW math ?
Because it's not how it works anymore. AMD changed something with AGESA 1.2.0.1 and 1.2.0.2
RZQ behaviour is different ~again~ !
And generally tFAW behaviour is different


Spoiler: My initial set which was rock stable














At this point, isn't stable at all. Not even remotely
VDDG needed a remake with voltages, and RTT's where messed up
This tFAW obscureness above, was randomly found ~ after beating my head against a wall of #2's for the last days
AMD changed something !

Is 2* tFAW recommendable ?
Unsure, it's performance is still here-and-there funky
But 4* tFAW at least on my set doesn't work at all. Some new implemented BURST read option , breaks stability fully
It likely is this option that @KedarWolf saw:


Spoiler














900-1020-1100 + tad higher SOC
is currently the new norm for me
Y-Cruncher was rebooting on "too low" SOC & crashing on "too high IOD" (was 1120mV before)

Hope this helps someone who struggles with stability on 1.2.0.1+ AGESA
RZQ is higher, it doesn't behave like 240ohm. Maybe DQS is finally at 480ohm instead of 240 , like "hidden" half a year ago in their bios changes
Anywho:
- lower IOD, and weaker RTT's are required for 1.2.0.1 / 1.2.0.2 to sustain stability 


lmfodor said:


> That is why my question about how you got to such a low tRAS, or such a low tRTP, must have a reason, in fact, see how well it worked for me, but like that, I did not learn anything!


KedarWolf's set was an experiment 
Testing of tRP. The opposite on "instead of lowering it to gain room in order to lower tRC"
Increasing it, as it's one of the timings like tRC, which has to elapse and is not breakable
tRAS was tried to be pushed at the lowest possible value
I think it was
tRCDavg + tCL + (tBL - (tCL-1)) - 1
14+14+ (-6) = 22 (8-13-1)
tBL used as 8 here instead of 4

The formula above tho was found by 1usmus 😇
Overall many little experiments happen along Matisse lifespan, when we where 1900 FCLK locked and bored


Spoiler: This is what i can find from the old data:





































Many many little shenanigans and snippets ~ where most of the things are deprecated and have changed. But just so you know behind the scenes 
Want to remind everyone who judges on tRFC mini - that it took a loong time to build, it's not that random 

I can barely remember, but i think the goal for KedarWolf's set was to either use minimum tRAS or match tRC, just in order to match some abstract tRCD_WR ruleset
Soo tRP was one of the values which can scale down, but also can scale up to lower voltage requirements - as more time to (p)recharge will exist.
A voltage leakage experiment, with from todays perspective, looks a bit off on tRC. Just what works well, works well


lmfodor said:


> I worked a lot with circuits from a very young age, so I can say that in my life I always did troubleshooting, now I am dedicated to the sales of Software in one of the main German companies, but I am passionate about this and I want to continue learning. I would lack a better guide than values!


Please write or correct it next time with linebreaks, that's about all


----------



## RonLazer

ManniX-ITA said:


> That would literally hiding the dust under the carpet
> You wouldn't see PBO crashing but still something under the hood wouldn't be optimal.
> Didn't try it but I guess the latency would be randomly erratic.
> 
> Never managed to get the L3 latency below 10ns, why you link it to the frequency?
> So far I managed to manipulate it only with the cTDP and EDC limits.
> But it's very dependent on the AGESA, I can't get it much better with this BIOS.
> If I raise the EDC the performances will suffer a lot.
> Except the nice values in AIDA never had better scores in anything with a speedier L3.
> 
> 
> 
> 
> 
> 
> 
> __
> 
> 
> 
> 
> 
> TM5 - Google Drive
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> 
> For this GINYF
> He published it here, advanced search filtered for 1usmus, term: v3 config
> 
> 
> 
> I almost bought your kit, it could become a good one if AMD fixes high FCLK...
> Yes I achieve true 1T but it's more a "prize" than anything else.
> Except a bit better write and copy bandwidth it's not better than a 2T profile and needs a lot more voltage!
> 
> 
> 
> Much better a benching install.
> Buy a cheap USB SSD and use it only for the benching install.
> You can set offline the M.2/SATA drives and avoid any kind of corruption on the important stuff.
> Plus Windows booting from USB is super sturdy, it doesn't get corrupted by BSOD and the most terrible things you can do.
> I have only once corrupted TM5 config, that's all.
> There are free tools to create the WinToGo install:
> 
> 
> 
> 
> 
> Create Windows 11/10/8/8.1/7 Bootable USB with AOMEI Partition Assistant
> 
> 
> Windows To Go Creator can help you make a bootable USB from Windows 11/10/8/8.1/7 ISO/ESD file. Then, you can boot Windows 10/8/8.1/7 from it anywhere and anytime.
> 
> 
> 
> www.diskpart.com
> 
> 
> 
> 
> 
> 
> 
> A dual CCD in single CCD mode is not the same as a true 1CCD.
> I could achieve down to 52.4ns, there's a 1ns penalty sadly.
> The Unify-X is very annoying due to the BIOS bugs and the lack of some features but it's very solid and a great performer.
> In the running SuperPI Zen Low Clock competition Top 10, aimed at the best RAM OC, the Unify-X is in position 3,4,7, the Dark Hero in position 6,8,10
> All good results but seems for crazy stuff it does have the lead.
> If/when AMD fixes the FCLK then the real fun will start.


Dark Hero will take a higher position soon when I upload my latest personal best 😏


----------



## Veii

Kitsune2431 said:


> The issue appeared when i tried to do 2 last tm5 tests again, but on my main windows instead of external windows. Tm5 doesn't give errors, but just stops testing randomly. The timer is still going, but testing just stops. I think it happens when 1 cycle ends and ram gets freed, but new cycle doesn't start. Happens at random cycles (3,9,25,69)., but it doesn't stop if i disable ethernet (read thread with same issue on reddit, but there was no conclusion). With ethernet disabled it passes the tests and doesn't stop. Do you guys know if this is a sign of instability or just windows shenanigans? Tried turning off all programs and test, but it still happens. I think the only big difference between my windows installs is that my main windows has eset antivirus and external ssd just windows defender.
> 
> So, should i be worried and try to pinpoint the issue if my main windows passes the tests with ethernet disabled? Haven't encountered any other issues. No whea, no game crashes. Just tm5 stopping randomly with no errors.


This has to be coincidence
When TM5 freezes, it means that one thread/worker crashed
This means that one core/thread crashed

Doublecheck stability with y-cruncher (1/7/0) for 4 loops (54min , >3*18min) and if that passes, then something else happened
Up to what system you run, and up to the bios - it could be either a WHEA triggered by Realtek NIC, or USB issues
I remember MSI had 2-3 months ago SATA storage dropout issues too
Around the debugging period of our USB issues
Really depends what you run and what you have . It can be for example buggy AGESA 1.2.0.1 or strange 1202 with new RTT requirements and lower IOD requirements
Depends 


Senniha said:


> I have 4 dimms 3333cl16 LPX corsair and are not identical
> Any old friend from taichi @Veii ?Can you help


CJR & Micron , fun

If Zentimings is right, then you overvolt cLDO_VDDP and VDDG CCD by a lot
Maybe you haven't seen this post








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net





RTT_WR /2 , i don't think any of the sets would require this.
RTT_PARK of /1 is too low, increase it please to at least /2 or even /3
Wasn't there a P6.63 out there finally ? i remember it was buggy before

Yea no RTT_PARK /2 should be better, but don't run /1
ClkDrvStr you want to push at 60
CsOdtDrvStr at 40
60-20-40-20 CAD_BUS, try this 
Maybe will need 120-20-30-24 on T-Topology, but first try couple of things
On a flat timings set, don't use Odd primaries and GDM on

RTT_NOM, depends
You should be passing just fine with /7,
But what you can also try is test booting without RTT_WR (disabled)
Soo something along the lines of 6/0/3 or 7/0/2
Just don't run /1 on the poor hynix 
Micron dimms would expect DynamicODT (RTT_WR) but your combination is strange

As for the order
Micron, Hynix, Micron, Hynix
try this if you haven't already

Can't help you with one answer only, it's too exotic and needs a lot of trial and error
Autocorrection from Vermeer, is throttling - get the voltages down first
procODT you want to move sub 40, likely 36-39ohm till 3600. Globally sub 40ohm


craxton said:


> hey @Veii when you mentioned, using TM5 and C/O
> with HWinfo while holding 4.85 all core/threads with 50mv offset
> did you mean -50mv offset?


Positive vCore offset and maxed out negative CO (or in the range of 25+)
at 3800 and higher
(if you are a CTR user, don't use any positive vcore offset bellow RC04)
Positive vcore offset comes with strong vdroop LLC
It's only there to increase input current, as negative CO does take a cut on it


----------



## Veii

ManniX-ITA said:


> I could reach even better scores with different timings but this one is better.
> Because its *consistency in latency* is almost perfect.
> This kit running at 1T with setup timings seems to be a little more erratic than the usual.
> 
> I'm probably just too much obsessed on it; latency jumping up and down every now and then without a reason hurts me
> I does happen also with GDM and 2T profiles when the timings are very tight; randomly the AIDA latency test goes off the chart.
> If you run only the latency test, it can be very often correlated to a drop in CPU Clock frequency.
> Sometimes there's a clock drop even if the latency is fine. It's big, down to 4.7 to 4.9 GHz.
> And I noticed that if it happens at some point the latency will show an inconsistency, if you repeat again and again the test.
> 
> I think the CPU Clock reported by AIDA can be a spotter of slight misalignment in timings.
> AIDA runs a small routine at bench start to detect the "top speed" of the CPU (Core 0).
> It's probably not exactly the highest clock that can reach but the highest it can reach with that workload.
> BoostTester and also Geekbench are not affected by memory timings.
> They give the same result unless something is really wrong.
> AIDA seems to use a very special routine.
> 
> Which is good cause it can be used as a reference and is somewhat consistent.
> I guess that it makes PBO to struggle to boost the clock if there's something wrong with timings.
> If the CPU Clock crashes down, that's very likely a sign that something is wrong.
> Or that Windows decided to run something on Core 0 just at that moment...
> 
> So my dogma now is: get the reported* CPU Clock* at the right frequency *AND *the* latency* in the range of +/- 0.1ns repeatedly.
> Only this makes me confident the timings are right.
> With this profile I could get endless runs with latency between +/- 0.1ns from 54.5ns and CPU Clock at 5100, sometimes 5075 MHz.
> Other timings would give me better scores but would "ruin the experience" every now and then.


You might be "obsessed" yes haha
But certainly not crazy 


Veii said:


> Often 3 options will work, but only 2 will perform without variance
> 0.3ns variance in Aida64 cache/memory test ~ means instability
> The CPU is very capable of autocorrecting and slowing itself down to maintain stability


0.1ns is fine, 0.2 maaybe if your OS is bloaty
The first Aida64 test you mostly can trow away
The CPU needs some load, before it starts to accept idle states and slow down correspondingly
SiSoftware Sandra (processor inter-core lateny) test is an equally valuable resource for such

You will get people who judge you that it's "impossible" to have perfectly consistent latency on a "random" latency test
Be aware 


ManniX-ITA said:


> A dual CCD in single CCD mode is not the same as a true 1CCD.
> I could achieve down to 52.4ns, there's a 1ns penalty sadly.
> The Unify-X is very annoying due to the BIOS bugs and the lack of some features but it's very solid and a great performer.
> In the running SuperPI Zen Low Clock competition Top 10, aimed at the best RAM OC, the Unify-X is in position 3,4,7, the Dark Hero in position 6,8,10
> All good results but seems for crazy stuff it does have the lead.
> If/when AMD fixes the FCLK then the real fun will start.


Makes me wonder about my penalty 
Do i have it, don't i have it
Heh, one step wrong procODT and you have this 1ns penalty 
Oh give one step lower proc and weaker PARK a try
SMU 56.50 is awkward - but only 1202 SMU 56.50 , not 1200 SMU 56.50


----------



## RonLazer

Why are we still using Aida64 for latency by the way? I could write a script that uses xmem or mlc and runs longer, more varied, and different sizes of memory loads and spits out a set of latency scores, or perhaps introduce some scoring system. Is there any interest in that or do people just like having the simplicity of a single universal test that they can compare to others?


----------



## Veii

RonLazer said:


> Why are we still using Aida64 for latency by the way? I could write a script that uses xmem or mlc and runs longer, more varied, and different sizes of memory loads and spits out a set of latency scores, or perhaps introduce some scoring system. Is there any interest in that or do people just like having the simplicity of a single universal test that they can compare to others?


Probably because it's behaviour is known and unlike maxmem, a bit more accurate

Cache functionality is often used & we could rely on the Dev to update the testing methodology for each of the CPUs (epyc included)
Likely also as it does work with CPU-Z together to identify the unit and if somebody is "cheating" or not

It would be great to have a replacement for Aida64 and SiSoftware Sandra
1usmus worked on it too with the latency curve, but it was a niece attempt for a niece request (it lacks the cache part and a better UI)
Passmark has a good instructionset to bandwidth test ~ with a curve, for memory access time and overall effficiency

It's probably too much work to cover 3 established brands, into one product.
Then including the testing & learning of this new product.

Fully nothing against it - but it's h*ck load of work
As the latency result mostly is for personal comparisons and only a tiny bit of the reason is that most of us run nearly similar versions
But for pure comparisons, it's not perfect ~ for such SiSandra is way better , just SiSandra's UX is really bad and doesn't give an option to compare with others., except their leaderboards at all 

It's really a sh*tton of work to cover the core functionality of 3 tools
But we would need of one unified testing tool - that at least includes a "different dataset size" generated curve with ns access time values
EDIT:
For example something like this combined with SiSoftware Sandra functionality:















Such curves at U0 U1 U2 , per thread
Pretty much what SiSandra Processor Inter-Core latency , test does
but with better user experience
It doesn't exist, as it's too much work


----------



## mongoled

@Veii 😂😂 couldn't keep away, happy you are posting 😊😊

56-56-56 makes 1T stable with no performance regression, well, at least when tested with AIDA. 

Currently running TM5 into 10th cycle so far, with 3-3-15 would have bluescreen just entering Windows 

😊😊


----------



## ManniX-ITA

Veii said:


> You will get people who judge you that it's "impossible" to have perfectly consistent latency on a "random" latency test
> Be aware


I'll be damned for sure!! 



Veii said:


> Heh, one step wrong procODT and you have this 1ns penalty
> Oh give one step lower proc and weaker PARK a try


I'll try maybe with AORUS Master, tomorrow I should get the new kit... unless of course something is wrong and I decide to send it back.
Want to use the Master as a bench test but I need to finish the build to free some space.
Planning to buy a 57xxG to play with high FCLK.



RonLazer said:


> Why are we still using Aida64 for latency by the way? I could write a script that uses xmem or mlc and runs longer, more varied, and different sizes of memory loads and spits out a set of latency scores, or perhaps introduce some scoring system. Is there any interest in that or do people just like having the simplicity of a single universal test that they can compare to others?


I'd say universal test.
If you really can, would be amazing.
But as Veii said it's a massive amount of work...
TBH best of the best would be as a module/extension in Zentimings, @infraredbg is here.
Yummy, one screenshot rulez all


----------



## Veii

mongoled said:


> @Veii 😂😂 couldn't keep away, happy you are posting 😊😊





mongoled said:


> 56-56-56 makes 1T stable with no performance regression, well, at least when tested with AIDA.


Interesting, it should be far slower tho beyond i think it was value 33 after when it switches to post, or 2T mode
Need to find the bbs.naver links that visualize the range of SETUP timings (korean)


RonLazer said:


> Why are we still using Aida64 for latency by the way? I could write a script that uses xmem or mlc and runs longer, more varied, and different sizes of memory loads and spits out a set of latency scores, or perhaps introduce some scoring system. Is there any interest in that or do people just like having the simplicity of a single universal test that they can compare to others?
> 
> 
> ManniX-ITA said:
> 
> 
> 
> TBH best of the best would be as a module/extension in Zentimings, @infraredbg is here.
> Yummy, one screenshot rulez all
Click to expand...

If Ron wants to do all the work soo the community has something useful aside from intels and Aida's option ~ usable for example with a 5$ license (+48h trial) instead Aida64's 30$ or passmarks expensive one (14 days trial only)
3D Mark works too but also is for 12-20$

all in one tool for testing that has a better UI than SiSoftware Sandra
Would be very beneficial. Just it needs to make 10 things right which is a lot of work
Contribution with infrared for timings & voltage readout, would be valuable too ~ on it. Soo it doesn't have to rely on anything CPU-Z or HWInfo related

But again, sh*tton of work ~ and we know our programs , they are just split. A unified option of course would be far better
Yuri is more than enough busy with CTR, soo DRAM Calculator will remain how it was before
Surely useful , but our demand increased ~ to find hidden autocorrection instabilities

A friend is obsessed with LatencyMon, and finds that way random autocorrection DPC calls + optimal SOC / VDDG voltage


Spoiler






















I for example stick on my "trow AVX2 tests on it till it fails ~ y-cruncher methodology & see when Aida64 starts to misbehave 
Everyone has their own , but having a big testing and compare tool ~ would be very useful !


ManniX-ITA said:


> I'll try maybe with AORUS Master, tomorrow I should get the new kit... unless of course something is wrong and I decide to send it back.
> Want to use the Master as a bench test but I need to finish the build to free some space.
> Planning to buy a 57xxG to play with high FCLK.


I was planning on getting one, but might jump on it when it's out.
The research time would contribute more people, than only the hard to find OEM options

Went for now with an Asus B550 ProArt (finally found it for 269€)
But it has Vishay 50A stages on a 4+4+4 Phase setup. They've cheapen out on the PWM controller too, as it can only peak to 6 not 7 phases,
soo 12+1 , worked only as (4+4+4)+1 & not 6+6+1
It apparently seems to hit 80c on a 5800X @ 1.35v fixed voltage ~ but it should be fine with some cooling
Was fine with a 105c holding B350 Tomahawk back then 

Got it to have fun with Thunderbolt 4/USB4.0, and maybe play around with the internal flashback utility
Aside from needing TB for UAD DSP's under macOS


----------



## ManniX-ITA

Veii said:


> Interesting, it should be far slower tho beyond i think it was value 33 after when it switches to post, or 2T mode
> Need to find the bbs.naver links that visualize the range of SETUP timings (korean)


You mean this link?








쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네


출처:https://blog.asset-intertech.com/test_data_out/2014/11/memory-training-testing-and-margining.ht



coolenjoy.net





I don't see the added latency but @Dar|{cyde could see it with his 1CCD CPU.

BTW You also posted another link from bbs about B-die tweaking but I've lost it and couldn't find your post again... do you recall/have it?

Thanks a lot for these precious pills of course


----------



## Veii

ManniX-ITA said:


> You mean this link?
> 
> 
> 
> 
> 
> 
> 
> 
> 쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네
> 
> 
> 출처:https://blog.asset-intertech.com/test_data_out/2014/11/memory-training-testing-and-margining.ht
> 
> 
> 
> coolenjoy.net
> 
> 
> 
> 
> 
> I don't see the added latency but @Dar|{cyde could see it with his 1CCD CPU.
> 
> BTW You also posted another link from bbs about B-die tweaking but I've lost it and couldn't find your post again... do you recall/have it?
> 
> Thanks a lot for these precious pills of course


쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네 yep , lecture C has deconstructed SETUP times and CKE behaviour when you scroll down
Else Chitos found this precious one
DRAM - 메모리 시스템 구조 > 오버클러킹 | 퀘이사존 (quasarzone.com)
I learned from chiphell a bit, Translators struggle with korean
But that quasar article is well designed ~ need to sit someday and revisit the technical side of things


----------



## kompira

@Veii I can confirm this, after changing Rtt from 736 to 637, I lowered VDIMM from 1.46 to 1.45V. 
tFAW = 2* tRRDS also works.
AGESA 1.2.0.1 PatchA, Zen1
testing now ... it looks very good


----------



## jomama22

ManniX-ITA said:


> That would literally hiding the dust under the carpet
> You wouldn't see PBO crashing but still something under the hood wouldn't be optimal.
> Didn't try it but I guess the latency would be randomly erratic.
> 
> Never managed to get the L3 latency below 10ns, why you link it to the frequency?
> So far I managed to manipulate it only with the cTDP and EDC limits.
> But it's very dependent on the AGESA, I can't get it much better with this BIOS.
> If I raise the EDC the performances will suffer a lot.
> Except the nice values in AIDA never had better scores in anything with a speedier L3.
> 
> 
> 
> 
> 
> 
> 
> __
> 
> 
> 
> 
> 
> TM5 - Google Drive
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> 
> For this GINYF
> He published it here, advanced search filtered for 1usmus, term: v3 config
> 
> 
> 
> I almost bought your kit, it could become a good one if AMD fixes high FCLK...
> Yes I achieve true 1T but it's more a "prize" than anything else.
> Except a bit better write and copy bandwidth it's not better than a 2T profile and needs a lot more voltage!
> 
> 
> 
> Much better a benching install.
> Buy a cheap USB SSD and use it only for the benching install.
> You can set offline the M.2/SATA drives and avoid any kind of corruption on the important stuff.
> Plus Windows booting from USB is super sturdy, it doesn't get corrupted by BSOD and the most terrible things you can do.
> I have only once corrupted TM5 config, that's all.
> There are free tools to create the WinToGo install:
> 
> 
> 
> 
> 
> Create Windows 11/10/8/8.1/7 Bootable USB with AOMEI Partition Assistant
> 
> 
> Windows To Go Creator can help you make a bootable USB from Windows 11/10/8/8.1/7 ISO/ESD file. Then, you can boot Windows 10/8/8.1/7 from it anywhere and anytime.
> 
> 
> 
> www.diskpart.com
> 
> 
> 
> 
> 
> 
> 
> A dual CCD in single CCD mode is not the same as a true 1CCD.
> I could achieve down to 52.4ns, there's a 1ns penalty sadly.
> The Unify-X is very annoying due to the BIOS bugs and the lack of some features but it's very solid and a great performer.
> In the running SuperPI Zen Low Clock competition Top 10, aimed at the best RAM OC, the Unify-X is in position 3,4,7, the Dark Hero in position 6,8,10
> All good results but seems for crazy stuff it does have the lead.
> If/when AMD fixes the FCLK then the real fun will start.


L3 latency is directly tied to clockspeed. Vaii has mentioned numerous times. If you have a higher latency, it's most likely you are actually clock stretching at those boost speeds and not actually hitting them. 

The only reason I am mentioning it is because you are very much concerned about aida's memory latency and it seems you are trying to attack two problems at them same time as opposed to isolating each one individually. If you were to isolate one variable, solve whatever issues you are having, then attack the other after fixing the first, it will most likely go much smoother and quicker with better end results.


----------



## ManniX-ITA

RonLazer said:


> Dark Hero will take a higher position soon when I upload my latest personal best 😏


Ah that's great, let's rock


----------



## ManniX-ITA

jomama22 said:


> L3 latency is directly tied to clockspeed. Vaii has mentioned numerous times. If you have a higher latency, it's most likely you are actually clock stretching at those boost speeds and not actually hitting them.
> 
> The only reason I am mentioning it is because you are very much concerned about aida's memory latency and it seems you are trying to attack two problems at them same time as opposed to isolating each one individually. If you were to isolate one variable, solve whatever issues you are having, then attack the other after fixing the first, it will most likely go much smoother and quicker with better end results.


I didn't consider L3 latency an issue to take care of 
L3 latency at 10.2-10.3 is normal that I know of... in the spreadsheet Veii's 48.5ns latency profile has an L3 latency of 10.4ns.
Just like 99% of the others which are above 10ns, only a couple of people are running it below.
What is the criteria to say it's higher? I'm confused...

@Veii
Should I be worried about the impact of L3 speed on latency?


----------



## jomama22

ManniX-ITA said:


> I didn't consider L3 latency an issue to take care of
> L3 latency at 10.2-10.3 is normal that I know of... in the spreadsheet Veii's 48.5ns latency profile has an L3 latency of 10.4ns.
> Just like 99% of the others which are above 10ns, only a couple of people are running it below.
> What is the criteria to say it's higher? I'm confused...
> 
> @Veii
> Should I be worried about the impact of L3 speed on latency?


When I say clock speed, I am referring to core clock speed.

For instance, my 5100 pbo boost hits 9.9ns constant for L3, which is right where it would be expected. Others with 5150-5175 hit 9.8.

Doing a 4.8 all-core oc nets 10.5 ns L3.

This is consistent across all bios versions in my experience.

Whether clock stretching is directly related to memory latency, I wouldn't not know. I only brought it up since you were comparing core clock speed to the memory latency you were getting in aida. I would not think core clock frequency would have any effect on memory latency as the memory latency measurement would most likely take into account the time needed for instruction execution.


----------



## ManniX-ITA

jomama22 said:


> This is consistent across all bios versions in my experience.


I only had an improvement with high EDC limit but I could not go below 10ns.
What are your limits?
AMD released in AGESA 1.2.x.x, don't remember which one, a fix for L3 speed in AIDA test and that affected my L3 latency (got worse).
But then I could fix it unlocking the cTDP to 1000W as suggested by Veii.


----------



## jomama22

ManniX-ITA said:


> I only had an improvement with high EDC limit but I could not go below 10ns.
> What are your limits?
> AMD released in AGESA 1.2.x.x, don't remember which one, a fix for L3 speed in AIDA test and that affected my L3 latency (got worse).
> But then I could fix it unlocking the cTDP to 1000W as suggested by Veii.


Using a dark hero, I have 300-235-245. This is without adjusting cTDP in the CBS submenu.

I should add that this is more adjusted to top end PBO (up to 6 cores in r20) as I have dynamic OC switcher in this board, so at 85 amps, my cpu automatically locks to 4.8 ghz all core.

PBO/CO has been nurfed since 1.1.9.0/1.1.0.0 patch D. Not sure exactly what all changed, whether it's the algo or the scaling on the CO values, but as an example, any agesa newer than 1.1.8.0 allows everyone to have much lower CO values while either maintaining performance (those who couldn't get low CO values in the earlier agesas) or lowering PBO performance (those who could get very low CO values, like myself, on earlier agesas).

1.1.0.0 patch C was the best agesa for maximizing pbo/co (this is the version where values could be set below -30. Whether these lower-than-30 values helped or not, I am not sure/do not believe so). But it is clear that this agesas CO was more aggressive in it's undervolting and/or pbo was more aggressive in reaching for higher clock speeds.


----------



## jomama22

I want to add that agesa 1.1.8.0 and earlier (1.1.0.0 patch C was the previous version) allow for a reduction in aida latency by around .7-.8ns at the same timings/voltages/w.e. compared to newer agesa versions as well.

If you are going to stick to pbo/co and 1900 fclock, these, in my option, are the best agesa versions to use.


----------



## Veii

ManniX-ITA said:


> @Veii
> Should I be worried about the impact of L3 speed on latency?


@yomama22 is right
10.9ns is 4.65GHz allcore burst
L3 latency test is a short allcore burst test
4.85ghz is 10.4ns
4.75 was 10.6/10.7ns

Soo 10ns would be 5050mhz or 9.9ns would be 5100Mhz

The whole boosting algorithm changed once with a new ABL at 1100D - well it got "unlocked"
Then 1180/1181/1191 tried to "fix" cache speedup, without having to lift the EDC limit
It kind of helped, but it still was 20% slower than fully opening it by yourself
Since 1100D you can run 400A EDC (dual CCD better use 500A) to allow cache to boost till it's internally throttled

Apparantly 1200 should have fixed this, but there is no change between 1191 and 1200
I think we should start to talk in SMU versions instead of big packages
Patch C sadly had an enforced 1900 FCLK lock, as preparation for the EDC burst boost at Patch D
Gladly D lifted this limit again
1201 and 1202 = SMU 56.50 still have cache boost issues and DF hibernation issues (overboost spikes) 
but the EDC lifting still works - soo i hit 680GB/s on read , 660ish on Copy and 670ish on Write

But as exchange for their attempt to lift couple of limits or "extend them" (from 330 to 450GB/s) the L3 access time increased up to 11.2 on stock , instead of 10.9 for me @ the same frequency
Now 1202 with a new branch prediction algorithm (sadly spectre v5 is an issue on it) ~ it did gave another 5-23% IPC boost comparable via geekbench
But both 1201 and 1202 changed memory controllers firmware again , and fully messed up procODT range + VDDG IOD range (lower is needed)

Also either DQS range changed or RZQ is higher (either 320ohm or 480ohm now)
Soo RTTs need to be "weakened" and procODT one step down to something weaker


kompira said:


> @Veii I can confirm this, after changing Rtt from 736 to 637, I lowered VDIMM from 1.46 to 1.45V.
> tFAW = 2* tRRDS also works.
> AGESA 1.2.0.1 PatchA, Zen1
> testing now ... it looks very good
> View attachment 2489289


Didn't expect that Zen1 benefits from it
But fantastic tRDWR  
You should Aida64 test if tFAW 8 vs 16 shows any type of benefits for you 
It's a good set of timings, good job ! 

If it works how i think it should, then you can run procODT 48ohm
But i haven't noticed many changes for Zen1
Although there are couple of new AMD microcodes out , didn't track it much
Try 48ohm proc )


----------



## ManniX-ITA

jomama22 said:


> Using a dark hero, I have 300-235-245. This is without adjusting cTDP in the CBS submenu.
> 
> PBO/CO has been nurfed since 1.1.9.0/1.1.0.0 patch D. Not sure exactly what all changed, whether it's the algo or the scaling on the CO values, but as an example, any agesa newer than 1.1.8.0 allows everyone to have much lower CO values while either maintaining performance (those who couldn't get low CO values in the earlier agesas) or lowering PBO performance (those who could get very low CO values, like myself, on earlier agesas).
> 
> 1.1.0.0 patch C was the best agesa for maximizing pbo/co (this is the version where values could be set below -30. Whether these lower-than-30 values helped or not, I am not sure/do not believe so). But it is clear that this agesas CO was more aggressive in it's undervolting and/or pbo was more aggressive in reaching for higher clock speeds.


Which AGESA version are you running?
On the Unify-X this BIOS is 1.2.0.1; doesn't go below 10.2nx even with PBO motherboard limits and cTDP at 1000W.
I had the first releases on the Master with CO where I could go down to 45-48 CO, not sure.
It was much better, I've lost quite a bit. Both on the Master and the Unify-X despite the boost clock is same or better the performances are a tad lower.


----------



## ManniX-ITA

Veii said:


> 10.9ns is 4.65GHz allcore burst
> L3 latency test is a short allcore burst test
> 4.85ghz is 10.4ns
> 4.75 was 10.6/10.7ns
> 
> Soo 10ns would be 5050mhz or 9.9ns would be 5100Mhz


But I though this was valid for static OC, not PBO...
So I should get at least 9.9ns with PBO boosting to 5100?
Oh damn, what do I have to fix


----------



## ManniX-ITA

Veii said:


> L3 latency test is a short allcore burst test


Are you sure?
I have just run it and is using only Core 0.


----------



## ManniX-ITA

Of course 🤦‍♂️
Didn't factor that my cooling sucks.
The CPU Clock can't be used as a reference for the L3 latency test.
Cause it's a sustained workload and my Core 0 can't run it at 5100-5125 MHz (my cooling sucks).
It runs at 4.9-5.0GHz and hence the latency 10.2ns at best.


----------



## jomama22

Veii said:


> @yomama22 is right
> 10.9ns is 4.65GHz allcore burst
> L3 latency test is a short allcore burst test
> 4.85ghz is 10.4ns
> 4.75 was 10.6/10.7ns
> 
> Soo 10ns would be 5050mhz or 9.9ns would be 5100Mhz
> 
> The whole boosting algorithm changed once with a new ABL at 1100D - well it got "unlocked"
> Then 1180/1181/1191 tried to "fix" cache speedup, without having to lift the EDC limit
> It kind of helped, but it still was 20% slower than fully opening it by yourself
> Since 1100D you can run 400A EDC (dual CCD better use 500A) to allow cache to boost till it's internally throttled
> 
> Apparantly 1200 should have fixed this, but there is no change between 1191 and 1200
> I think we should start to talk in SMU versions instead of big packages
> Patch C sadly had an enforced 1900 FCLK lock, as preparation for the EDC burst boost at Patch D
> Gladly D lifted this limit again
> 1201 and 1202 = SMU 56.50 still have cache boost issues and DF hibernation issues (overboost spikes)
> but the EDC lifting still works - soo i hit 680GB/s on read , 660ish on Copy and 670ish on Write
> 
> But as exchange for their attempt to lift couple of limits or "extend them" (from 330 to 450GB/s) the L3 access time increased up to 11.2 on stock , instead of 10.9 for me @ the same frequency
> Now 1202 with a new branch prediction algorithm (sadly spectre v5 is an issue on it) ~ it did gave another 5-23% IPC boost comparable via geekbench
> But both 1201 and 1202 changed memory controllers firmware again , and fully messed up procODT range + VDDG IOD range (lower is needed)
> 
> Also either DQS range changed or RZQ is higher (either 320ohm or 480ohm now)
> Soo RTTs need to be "weakened" and procODT one step down to something weaker
> 
> Didn't expect that Zen1 benefits from it
> But fantastic tRDWR
> You should Aida64 test if tFAW 8 vs 16 shows any type of benefits for you
> It's a good set of timings, good job !
> 
> If it works how i think it should, then you can run procODT 48ohm
> But i haven't noticed many changes for Zen1
> Although there are couple of new AMD microcodes out , didn't track it much
> Try 48ohm proc )


I believe 1.8.0.0 was released before 1.1.0.0 D as far as I can tell. SMU on 1.8.0.0 is 56.37.0. Hard to find the smu for 1.1.0.0 D, but it looks as though its 56.40.


----------



## Veii

ManniX-ITA said:


> But I though this was valid for static OC, not PBO...
> So I should get at least 9.9ns with PBO boosting to 5100?
> Oh damn, what do I have to fix


at least 10ns, 9.9 if you get it perfectly - maybe even 9.8
Static overclock seems to lose 0.1ns there and cache seems to be lower on it - for whatever reason AMD limited it there

cTDP up to 400W, Package Throttle limit up to 400W
Negative CO further down (more of it)
and if negative CO causes you issues, a bit of positive vcore offset
This tricks FIT and it thinks it doesn't pull that much EDC (A) soo allows cores to boost higher

You can fully lift EDC limit, but by doing so, you let it take more global vcore
One way is like many do with global negative offset
But this doesn't trick again the hardlocked EDC Fuse limit








CoreCycler - tool for testing Curve Optimizer settings


Here's v0.8.0.0 RC4, only use it if you're willing to beta test. 👆 https://github.com/sp00n/corecycler/releases/tag/v0.8.0.0-RC4 @Theo164 It's interesting, I've never been able to have Y-Cruncher actually fail a stress test. It's either passing for me or rebooting the whole system. 🤷‍♂️ And...




www.overclock.net




I still miss 5900X results 

Soo what i figured is better,
Maxed out "allcore" negative CO - soo internal Curves by AMD don't change, but only their magnitude
And then positive vcore offset, to compensate for it
Maxed negative CO is around 120mV droop, soo you should compensate on it.
(i used 50mV on subtle loadline droop, but changed now to 60mV with stronger loadline droop)
Optimally TM5 holds the boost frequency on all-cores , soo 5100 on all cores
Scalar around X6 to X8, higher increases peak voltage

5ghz can run at 1.36ish V-TEL
1.4v V-TEL already limits it down to 4.8-4.9
1.425 V-TEL limits it down to 4.75
soo you can imagine why it is bad to have a higher scalar which also increases supplied voltage
Example








This was not PBO but similar,
Sadly AMD did indeed limit it to +200 , soo i'm on 4.85
CTR while work in progress to becoming very useful, so far is not beating my PBO - not in SC and not in Multi ~ buut it's getting there


ManniX-ITA said:


> Are you sure?
> I have just run it and is using only Core 0.


Yes, Aida64 runs on kernel realtime, it for short time hangs
It's not only a peak boost test but a short burst of allcore - where EDC limit does make a difference
In this case mem-peak is also both
a short term per core tested and a burst allcore


----------



## jomama22

ManniX-ITA said:


> Which AGESA version are you running?
> On the Unify-X this BIOS is 1.2.0.1; doesn't go below 10.2nx even with PBO motherboard limits and cTDP at 1000W.
> I had the first releases on the Master with CO where I could go down to 45-48 CO, not sure.
> It was much better, I've lost quite a bit. Both on the Master and the Unify-X despite the boost clock is same or better the performances are a tad lower.


I am running 1.1.8.0 atm. Reasons why are what I listed above. Here is my aida and zen timings (on semi bloated win install, safe mode lowers memory latency to 53.4). 1.1.8.0 does allow you to try fclk up to 2000 but is locked beyond that (I get wheas above 1900)









also want to note that 1.1.9.0 and greater did allow higher than 2000 fclk, it also massively reduced the amount of whea errors I would get, but they would still pop up.


----------



## Veii

jomama22 said:


> I believe 1.8.0.0 was released before 1.1.0.0 D as far as I can tell. SMU on 1.8.0.0 is 56.37.0. Hard to find the smu for 1.1.0.0 D, but it looks as though its 56.40.











PatchD, the Cache boost was first found supplied by Stasio ~ which AMD refused to let him release as Patch-D
It was pushed on 56.34 Patch C - the newer ABL
He wasn't allowed to release 56.40+
Likely as there where no EDC limits and because AMD knew about the overboost issue - yet hid it as a toggle through the chipset drivers , to disable core hibernation and yet no word on it why DF-States are now disabled instead of enabled on Auto


----------



## jomama22

Veii said:


> PatchD, the Cache boost was first found supplied by Stasio ~ which AMD refused to let him release as Patch-D
> It was pushed on 56.34 Patch C - the newer ABL
> He wasn't allowed to release 56.40+
> Likely as there where no EDC limits and because AMD knew about the overboost issue - yet hid it as a toggle through the chipset drivers , to disable core hibernation and yet no word on it why DF-States are now disabled instead of enabled on Auto


See my zentimings shot above. It's very possible initial 1.1.8.0 agesa releases have 56.37, which is some odd quasi smu work going on. I'm pretty sure only asus actually released a final version on 1.1.8.0 to the masses. Looking at reports most MB makers pulled their 1.1.8.0 releases for stability issues(though I don't have any on the DH with this agesa/smu)

Also, what toggle are you speaking of in reference to the overboost issue?


----------



## Veii

jomama22 said:


> See my zentimings shot above. It's very possible initial 1.1.8.0 agesa releases have 56.37, which is some odd quasi smu work going on. I'm pretty sure only asus actually released a final version on 1.1.8.0 to the masses. Looking at reports most MB makers pulled their 1.1.8.0 releases for stability issues(though I don't have any on the DH with this agesa/smu)
> 
> Also, what toggle are you speaking of in reference to the overboost issue?


DF-States, AMD CBS - NBIO - SMU , DF-States ~ has to be disabled in order to prevent, sleep to wake up overboost


Spoiler: Old example














Global C-State generation needs to be enabled

SMU versions most boards don't get
The whole ASUS lineup missed the SMU 56.30, but got 56.34, which has an FCLK lock ~ soo i got nearly nowhere with the Dark Hero, as it shipped with SMU 56.34 and with an FCLK lock on it
56.30 has non, but 56.26 is buggy and misses BAR mode & Curve Optimizer

Negative CO & BAR mode exist since 56.30 - just marketing pushed users to update to patch C which "apparently should have this"
Or patch D and up which "apparently unlocked 2000 FCLK or have negative CO ~ so called PBO 2.0 marketing nonsense"

Patch D could be 56.36 or 37
but SMU mosttly changes the boosting behaviour and V/F scale
The ABL (AGESA Bootloader) defines FCLK limits, WHEA behaviour and fMAX frequency limits
So should also define PBO Boost limits and negative CO limits


----------



## ManniX-ITA

If there's an all-core burst during L3 latency test in AIDA it must be a matter of ms 
I have the CPU temperature displayed in the Unify-X Debug LED and it doesn't flinch.
With my 5950x any all-core burst would usually bump up substantially the temperature.
Anyway I think what actually defines the L3 latency is the sustained on Core 0 and mine runs below 5.0GHz.
Hence the slow L3 latency...



Veii said:


> soo you can imagine why it is bad to have a higher scalar which also increases supplied voltage


You know I'm a big fan of high scalar 
Higher scalar is not only higher voltage.
Otherwise performances would not improve going higher.
From what I see it's adding voltage and at the same time acting as a base magnitude modifier for the curve.
It's for sure adding more stress and thermal load but if the system can handle means more IPC.
Makes also easier for the good cores not to crash under load with high frequency cause the voltage is higher.
Just more voltage via an offset will not alter the curve and the boost frequency goes down.



Veii said:


> Maxed out "allcore" negative CO - soo internal Curves by AMD don't change, but only their magnitude
> And then positive vcore offset, to compensate for it


Tried your method but I couldn't get much out of it.
Maybe cause my cooling is limited for the 5950x.
Except higher clocks during very light workloads like TM5, it's a disaster for everything else.
Low single threaded and multi threaded scores.
I'll try again with the new build.


----------



## jomama22

Veii said:


> DF-States, AMD CBS - NBIO - SMU , DF-States ~ has to be disabled in order to prevent, sleep to wake up overboost
> 
> 
> Spoiler: Old example
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Global C-State generation needs to be enabled
> 
> SMU versions most boards don't get
> The whole ASUS lineup missed the SMU 56.30, but got 56.34, which has an FCLK lock ~ soo i got nearly nowhere with the Dark Hero, as it shipped with SMU 56.34 and with an FCLK lock on it
> 56.30 has non, but 56.26 is buggy and misses BAR mode & Curve Optimizer
> 
> Negative CO & BAR mode exist since 56.30 - just marketing pushed users to update to patch C which "apparently should have this"
> Or patch D and up which "apparently unlocked 2000 FCLK or have negative CO ~ so called PBO 2.0 marketing nonsense"
> 
> Patch D could be 56.36 or 37
> but SMU mosttly changes the boosting behaviour and V/F scale
> The ABL (AGESA Bootloader) defines FCLK limits, WHEA behaviour and fMAX frequency limits
> So should also define PBO Boost limits and negative CO limits


As far as the DH is concerned, patch D I believe was 3101-3104 bios version. My current bios (3003) with the agesa/smu listed above does allow for fclk up to 2000. I would imagine anyone who can run 2000 on any newer bios should be able to with this as well since it is indeed unlocked.

And yes, totally agree with the marketing nonsense. Made it difficult to know what a bios actually does without just loading it up yourself, really quite annoying.

As far as the df-states, I assume having c-states disabled along side df states disabled would more or less remove these overboost from occuring?


----------



## jomama22

ManniX-ITA said:


> If there's an all-core burst during L3 latency test in AIDA it must be a matter of ms
> I have the CPU temperature displayed in the Unify-X Debug LED and it doesn't flinch.
> With my 5950x any all-core burst would usually bump up substantially the temperature.
> Anyway I think what actually defines the L3 latency is the sustained on Core 0 and mine runs below 5.0GHz.
> Hence the slow L3 latency...
> 
> 
> 
> You know I'm a big fan of high scalar
> Higher scalar is not only higher voltage.
> Otherwise performances would not improve going higher.
> From what I see it's adding voltage and at the same time acting as a base magnitude modifier for the curve.
> It's for sure adding more stress and thermal load but if the system can handle means more IPC.
> Makes also easier for the good cores not to crash under load with high frequency cause the voltage is higher.
> Just more voltage via an offset will not alter the curve and the boost frequency goes down.
> 
> 
> 
> Tried your method but I couldn't get much out of it.
> Maybe cause my cooling is limited for the 5950x.
> Except higher clocks during very light workloads like TM5, it's a disaster for everything else.
> Low single threaded and multi threaded scores.
> I'll try again with the new build.


I have tried this method in the past with my very good cooling setup (2x360 rads with the cpu in its own waterloop) and found the same results as you.

It may stabilize and increase quick/light threaded workloads, but anything like r20 or extended cpu benchmark will be decimated.

Also, the scaler works similarly to using a positive voltage offset, except you don't get the large penalty in those intensive cpu workloads, but you do lose just a hair, sometimes.


----------



## Veii

jomama22 said:


> As far as the df-states, I assume having c-states disabled along side df states disabled would more or less remove these overboost from occuring?


C-States generation is needed but doesn't affect the overboost outcome
as it only happens when cores fully hibernate
C-State generation is needed to shuffle load and manage the powerbudget.
It's needed so cores can lower frequency down to 550mhz - although default powerplans are not designed well & won't lower frequency
Lowering freq doesn't have to be negative neither for access latency, nor for DPC calls - but the powerplans are just not designed for it

Disabling both would keep the CPU between 3.7ghz (P0, or for some 3.8Ghz) and the boost
Yet cores would consume at 0.9v P0 state resources, which could be assigned to other cores
difference example on a 5950X between the highperf powerplan and my take on it:








So there is surely something to gain 75-125mhz on loower powerdraw for the 1st CCD

It generally didn't boost high, it had no PBO fixes or anything
but that's been his setup, with boost-tester under cinebench R20


----------



## jomama22

Veii said:


> C-States generation is needed but doesn't affect the overboost outcome
> as it only happens when cores fully hibernate
> C-State generation is needed to shuffle load and manage the powerbudget.
> It's needed so cores can lower frequency down to 550mhz - although default powerplans are not designed well & won't lower frequency
> Lowering freq doesn't have to be negative neither for access latency, nor for DPC calls - but the powerplans are just not designed for it
> 
> Disabling both would keep the CPU between 3.7ghz (P0, or for some 3.8Ghz) and the boost
> Yet cores would consume at 0.9v P0 state resources, which could be assigned to other cores
> difference example on a 5950X between the highperf powerplan and my take on it:
> 
> 
> 
> 
> 
> 
> 
> 
> So there is surely something to gain 75-125mhz on loower powerdraw for the 1st CCD
> 
> It generally didn't boost high, it had no PBO fixes or anything
> but that's been his setup, with boost-tester under cinebench R20


Gotcha. From my testing with c-states enabled vs disabled, I actually find no difference in boosting behavior for r20 runs when thread count is 2 or greater, which is counter to what I would have guessed would happen. I was hoping the power savings from doing so would allow for greater multicore speeds and scores, but it's just not the case. There just isn't enough power savings to go around I am assuming. Single core boost does infact increase though.

Those individual core boosting tests mask this behavior. You can try this for yourself and see.


----------



## mongoled

Well here is a 1T GDM off 32GB completed TM5

Its was done on my work OS so will do some direct performance comparisons with my 2T setting on the benchmark OS tomorrow

The time that TM5 took to complete is around 4 to 5 mins faster and preliminary AIDA64 shows an increase in read bandwidth of around 300 MB/s (2T 57000, 1T 57300)


----------



## jomama22

I'll also add that disabling c-states does help my latencymon results quite a bit while only reducing r20 single core runs by about 2-3 points, which is really just a wash.


----------



## Dar|{cyde

Veii said:


> 900-1020-1100 + tad higher SOC
> is currently the new norm for me
> Y-Cruncher was rebooting on "too low" SOC & crashing on "too high IOD" (was 1120mV before)
> 
> Hope this helps someone who struggles with stability on 1.2.0.1+ AGESA
> RZQ is higher, it doesn't behave like 240ohm. Maybe DQS is finally at 480ohm instead of 240 , like "hidden" half a year ago in their bios changes
> Anywho:
> - lower IOD, and weaker RTT's are required for 1.2.0.1 / 1.2.0.2 to sustain stability


I've been struggling with y-cruncher reboots. 5600x on Unify-X, I thought it was my CO too low. It throws WHEA 18 on a seemingly random core each time. I've been raising my CO to compensate, but maybe it has nothing (or little) to do with the curve. 

What CPU are you feeding those 900-1020-1100 values? Here's my current setup, TM5 error free.
vDDP 0.900
CCD 0.940
IOD 1.060
vSOC 1.100
I'll try some higher CCD/IOD, see if it helps.


----------



## Danny.ns

I was "stuck" at 16-16-16 with 1.5Vdimm, but a minor increase to 1.515Vdimm has given me this (at 1.5Vdimm even 14-16-16 errors out after ~20%). I tried 14-14-14 at 1.52V and it errored out quickly - so I would probably need quite a bit more for a flat 14;


----------



## weleh

Dar|{cyde said:


> I've been struggling with y-cruncher reboots. 5600x on Unify-X, I thought it was my CO too low. It throws WHEA 18 on a seemingly random core each time. I've been raising my CO to compensate, but maybe it has nothing (or little) to do with the curve.
> 
> What CPU are you feeding those 900-1020-1100 values? Here's my current setup, TM5 error free.
> vDDP 0.900
> CCD 0.940
> IOD 1.060
> vSOC 1.100
> I'll try some higher CCD/IOD, see if it helps.
> 
> View attachment 2489301


Which core APIC ID is crashing?
You can check this on Event viewer under the WHEA error that occured.
It tells you the thread that crashed so you can move the curve accordingly.

WHEA 18 is 100% Curve Optimizer settings not ram or any derivative voltages related.


----------



## ManniX-ITA

mongoled said:


> Well here is a 1T GDM off 32GB completed TM5


Nice!
Please also run the Sandra Inter-Thread Efficiency test.
I can complete a single run of TM5 1usmus config in 6m:20s

This latency optimized profile absolutely destroyed the previous one, I wonder if it's the profile or I've changed something else in the BIOS settings... almost 980 GB/s top speed is a first.











Spoiler: Sandra Detailed






Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 174.52GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 40.1ns (9.3ns - 60.2ns)
Inter-Thread (same Core) Latency : 9.7ns
Inter-Core (same Module) Latency : 20.8ns
Inter-Module (same Package) Latency : 58.8ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.45GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1701.96MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.82ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 36.85MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 18.7ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 21.2ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 19.2ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 21.9ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.0ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 21.1ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.1ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 57.8ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 57.5ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 58.4ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.3ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 58.7ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.7ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 59.0ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.5ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.0ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.1ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 19.1ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 22.0ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.0ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 21.0ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.1ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 57.7ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 57.5ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 58.4ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.3ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 58.8ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.7ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 59.0ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 20.3ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 19.6ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 20.3ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.3ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 19.9ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.0ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 57.6ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.2ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 58.5ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.1ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 58.4ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 58.5ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.8ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.8ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.1ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.3ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 20.1ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 19.4ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 20.4ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.3ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 19.8ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.0ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 57.6ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 57.1ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.4ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.1ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 58.5ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 58.6ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.9ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 59.0ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.6ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 22.5ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 22.1ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 20.8ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 58.4ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.2ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 59.7ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 58.1ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.3ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 59.4ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.3ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 59.6ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 21.3ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.2ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.7ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.4ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 22.4ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.3ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 22.0ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 20.8ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 58.4ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 58.1ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 59.2ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 58.3ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 59.4ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 59.3ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.4ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 60.0ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.2ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 20.6ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 20.9ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 20.5ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.6ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 58.1ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 59.1ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.1ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 59.3ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 59.3ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 59.5ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 59.6ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.6ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 19.9ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.5ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.6ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.1ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 20.5ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 20.3ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 20.5ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.6ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 58.1ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 59.1ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.0ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 59.4ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 59.7ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 59.9ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 59.5ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.9ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.3ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.3ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 58.4ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 58.3ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 59.8ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.5ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 59.7ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 59.6ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 59.4ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 59.7ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 21.6ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 20.3ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 22.6ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.0ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.3ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.6ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.1ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.3ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 58.5ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 58.2ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 59.8ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.5ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 59.6ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 59.6ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 59.4ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 59.7ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 20.9ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.2ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.2ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.0ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 59.1ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 58.0ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.1ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 59.0ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.7ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 59.7ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.1ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.3ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.4ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.4ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.6ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 20.6ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 20.9ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.3ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.9ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 59.0ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 58.0ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 59.2ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 59.0ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.4ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 59.8ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 20.8ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.6ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.4ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 59.3ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.2ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.3ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.3ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.7ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 60.1ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.0ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 19.9ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.2ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.0ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.1ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 20.8ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.5ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 20.8ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.6ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.4ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 59.3ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.2ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.2ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.7ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.6ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.8ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.5ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.1ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 59.6ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.1ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.2ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 59.2ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 60.0ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.9ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.0ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.0ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.0ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 20.2ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.5ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.1ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.0ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.7ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.1ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.9ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 59.4ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.1ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.2ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 59.2ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.9ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.8ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.6ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 21.8ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.6ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 22.4ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.4ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.6ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.8ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.8ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 57.6ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 58.4ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.6ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 58.7ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.0ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.5ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.4ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.3ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 21.5ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.6ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 22.3ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.4ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.6ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.6ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 20.8ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 20.1ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 21.2ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.7ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.6ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.6ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.5ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 57.2ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 58.5ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.3ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 58.6ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.9ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.4ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.3ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.5ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.7ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 20.6ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 20.0ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 21.1ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.7ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.5ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.6ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.9ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 23.2ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.6ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.7ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.3ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 58.5ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 58.4ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 59.1ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 58.4ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 59.3ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 59.0ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 59.5ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 59.2ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 21.8ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 20.7ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.7ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 22.8ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.6ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.7ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.3ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.8ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.0ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 20.7ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.0ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.7ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.4ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 58.6ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 57.5ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.8ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 58.1ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.5ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.2ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 20.0ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.2ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 20.1ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.8ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.5ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 20.8ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 20.9ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 21.0ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.4ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 23.1ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 22.0ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.3ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.3ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 59.0ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.3ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 59.4ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.7ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.1ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 58.9ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 22.1ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 21.0ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 23.1ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.5ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.7ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.1ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 23.2ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.9ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.4ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.8ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 59.0ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.6ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 59.5ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.7ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 60.0ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 59.3ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 59.6ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 59.6ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.6ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.8ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.8ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.9ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.5ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.9ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.3ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.6ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 21.2ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 59.0ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 59.8ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 59.8ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 59.2ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.9ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.7ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.8ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.8ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.6ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 23.2ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.3ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 21.2ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.8ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.9ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 60.1ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.7ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 60.2ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 59.2ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 60.0ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.7ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.6ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.6ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.7ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.9ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 22.1ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.7ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 21.5ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.9ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.0ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 21.3ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.1ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 21.9ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 19.9ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.0ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.1ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 57.6ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 57.5ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 58.3ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.4ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 58.5ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 58.8ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.6ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 59.1ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.3ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 19.5ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 20.4ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.3ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 19.9ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.1ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.7ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 57.3ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.6ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.1ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 58.5ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.6ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 59.0ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.7ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.4ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 22.4ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.1ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.1ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 20.8ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.4ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.2ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 59.5ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 58.0ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 59.3ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 59.3ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 59.2ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 59.9ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.3ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.6ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.3ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.4ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.8ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.5ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 58.5ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.7ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.8ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 59.4ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 59.0ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.9ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.3ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.3ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 58.4ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 58.5ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 59.7ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 58.4ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 59.6ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 59.9ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 59.8ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 59.8ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 20.9ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.3ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 58.4ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 58.1ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 59.1ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 58.0ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 59.1ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 59.2ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 59.6ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 59.8ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 20.8ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.8ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 58.4ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 59.4ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.3ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.2ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.7ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.8ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 60.0ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.5ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.2ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 59.3ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.1ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.2ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 59.4ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 60.1ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.9ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.6ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 21.8ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.7ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 22.4ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.4ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.6ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.8ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 20.8ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 20.1ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 21.2ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.8ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.6ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.7ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.9ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 23.2ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.7ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.7ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.4ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.8ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.0ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.7ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.0ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.4ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.1ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 22.0ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.5ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.8ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 21.5ns
1x 64bytes Blocks Bandwidth : 26GB/s
4x 64bytes Blocks Bandwidth : 25.29GB/s
4x 256bytes Blocks Bandwidth : 99.81GB/s
4x 1kB Blocks Bandwidth : 333.17GB/s
4x 4kB Blocks Bandwidth : 507.61GB/s
16x 4kB Blocks Bandwidth : 703GB/s
4x 64kB Blocks Bandwidth : 979.09GB/s
16x 64kB Blocks Bandwidth : 603.52GB/s
8x 256kB Blocks Bandwidth : 593.52GB/s
4x 1MB Blocks Bandwidth : 603.66GB/s
16x 1MB Blocks Bandwidth : 25.11GB/s
8x 4MB Blocks Bandwidth : 19.28GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.85GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 4.85GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.85GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## Kitsune2431

Veii said:


> This has to be coincidence
> When TM5 freezes, it means that one thread/worker crashed
> This means that one core/thread crashed
> 
> Doublecheck stability with y-cruncher (1/7/0) for 4 loops (46min , 4*18min) and if that passes, then something else happened
> Up to what system you run, and up to the bios - it could be either a WHEA triggered by Realtek NIC, or USB issues
> I remember MSI had 2-3 months ago SATA storage dropout issues too
> Around the debugging period of our USB issues
> Really depends what you run and what you have . It can be for example buggy AGESA 1.2.0.1 or strange 1202 with new RTT requirements and lower IOD requirements
> Depends


I'm on 1.2.0.0 agesa. Tried going external windows again and it's fine. Tried going xmp and turning off curve optimizer on main windows (nvme) and it still stops randomly. Really don't know what to think. I'm gonna try your test with oc and if it passes, then i'll check basic 2133. If it still stops, then i have no idea.


----------



## ManniX-ITA

weleh said:


> WHEA 18 is 100% Curve Optimizer settings not ram or any derivative voltages related.


In some cases can be also VDDG CCD too low or LLC/PWM Frequency too weak


----------



## ManniX-ITA

Kitsune2431 said:


> I'm on 1.2.0.0 agesa. Tried going external windows again and it's fine.


I'd raise VSOC to 1.1V and VDDG to 1000mV, full Windows install is needy.


----------



## lmfodor

Delete


----------



## Dar|{cyde

ManniX-ITA said:


> In some cases can be also VDDG CCD too low or LLC/PWM Frequency too weak


I upped voltage to 900/1000/1050/1125. I still got a reboot, but no WHEA this time. So it wasn't just the curve, but now I still have reboots, and no indication why. Lol, back to testing.

At least OCing these things is never boring


----------



## jomama22

Dar|{cyde said:


> I upped voltage to 900/1000/1050/1125. I still got a reboot, but no WHEA this time. So it wasn't just the curve, but now I still have reboots, and no indication why. Lol, back to testing.
> 
> At least OCing these things is never boring


Just fyi, you can still have a voltage issue(or, too low of curve) if no whea appears. It's not always going to catch the big check or whea during a crash.


----------



## Veii

jomama22 said:


> Gotcha. From my testing with c-states enabled vs disabled, I actually find no difference in boosting behavior for r20 runs when thread count is 2 or greater, which is counter to what I would have guessed would happen. I was hoping the power savings from doing so would allow for greater multicore speeds and scores, but it's just not the case. There just isn't enough power savings to go around I am assuming. Single core boost does infact increase though.
> 
> Those individual core boosting tests mask this behavior. You can try this for yourself and see.
> 
> 
> jomama22 said:
> 
> 
> 
> I'll also add that disabling c-states does help my latencymon results quite a bit while only reducing r20 single core runs by about 2-3 points, which is really just a wash.
Click to expand...

This his how usually the stock powerplans behave








Here you won't see a difference, 100% ACPI means P0 state - soo 3.7ghz with subtle boost peaks to 130 (4.85 for me)
There are still here and there little boost spikes, but it's the nature of the mess they created & being dynamic
~ but yet it doesn't boost down and takes all cores up to waste power & limit maximum sillicon freq








This is how it could look , if C-States started to function and it was CPPC aware
(PowerSaver Powerplan @ 4% minimum state)








Sadly, the "powersaver" is simply too slow - and ramps too slow, also it functions on per core base and takes the thread with it up ~ even without the thread even needing to boost up as it gets no load
But again, doesn't take it up in unison, keeps all cores at P2 state near 1100Mhz , and rarely once a blue moon suspends some "bad" cores
= bad powerplan ~ also does rarely spike boost and is not fine (spikes can cause random shutdowns or fit safety throttling)

This is how a "bit too aggressive by intention" powerplan looks (my little mess)








By the nature of the dLDO design, it has to keep some cores up and running at P0 while boosting others up
And by intention of PatchD+ , there are tiny but existing overboost spikes - well "tiny" = 400mhz speedstep jumps 
But what you also can see, is that anything that isn't "requested" is lowering itself to Sleep State as Parked, but not hibernated core
This allows me to free up as much from the EDC limit as possible ~ soo allowing it to reach peak boost while suspending unused cores
It is CPPC aware too - where the little spikes on the right side, are OCN refreshing itself ~ especially the adds on the right 

Having "no difference" , means that your powerplan does nothing
I'd recommend to check out @ManniX-ITA work here:
(3) Ryzen Custom Power Plans for Windows 10 (Balanced and Ultimate) | Overclock.net
My mess might be useful and intentionally abuses overboost - but it's a bit messy now that dLDO_injection does leverage C-States per cores
It's just a bit too aggressive and causes random reboots on systems with not well balanced chiplet quality
(as the voltage differenciation is too big and FIT crashes , while dLDO tries to smooth out supplied voltage)
Well aswell with CTR ~ bit buggy, just the Cinebench Boost Tester on the 5950X doesn't lie 
* soo i need more time, to redesign it with being not soo aggressive, yet abusing overboost with a peak limiter


----------



## ManniX-ITA

Dar|{cyde said:


> I upped voltage to 900/1000/1050/1125. I still got a reboot, but no WHEA this time. So it wasn't just the curve, but now I still have reboots, and no indication why. Lol, back to testing.
> 
> At least OCing these things is never boring


Did you try lowering the max boost clock or reducing EDC?
I get reboots at 150 MHz with 215A that can be fixed at 205A.
Normally I use 125 MHz with 215A.
It's more beneficial a higher EDC than a higher boost clock unless the Core can really sustain it.
Single core sustained, even with a super light workload, I don't go over 5150 MHz.
Having the max boost clock at 150MHz = 5200 MHz it's really not useful.


----------



## Dar|{cyde

I'm on a lowly 5600, under a custom water loop.

The most I've been able to push is 80C at 145W. I want that +300 boost clock back, single thread speed is my focus for sims. I do have a lot of testing to try with the CPU though. Corecycler hasn't been able to find much. I haven't tried reducing the boost clock.. but I want every mhz I can get. Will see how it goes. I'm not too concerned about synthetic stable either, long as games and VR can handle it. 

Has anyone run past the WHEA point (like 2000 FCLK) and just ignored the warnings? I mean if MT5 passes, and other tests are fine, do we really care about a few _warnings_? If my windows blows up... meh. This is a fresh install for me, and its already probably corrupted by the memOC shenanigans.


----------



## ManniX-ITA

Dar|{cyde said:


> I'm on a lowly 5600, under a custom water loop.
> 
> The most I've been able to push is 80C at 145W. I want that +300 boost clock back, single thread speed is my focus for sims. I do have a lot of testing to try with the CPU though. Corecycler hasn't been able to find much. I haven't tried reducing the boost clock.. but I want every mhz I can get. Will see how it goes. I'm not too concerned about synthetic stable either, long as games and VR can handle it.
> 
> Has anyone run past the WHEA point (like 2000 FCLK) and just ignored the warnings? I mean if MT5 passes, and other tests are fine, do we really care about a few _warnings_? If my windows blows up... meh. This is a fresh install for me, and its already probably corrupted by the memOC shenanigans.


Understandable, try anyway to see if it goes away.
At least you know where to look.

Yes you can just disregard the WHEA if you don't have performance regression.
Found the best to show improvements/regressions for FCLK is 3DMark TimeSpy CPU score.


----------



## madweazl

I'm working on tightening up some RAM timings but haven't been able to disable GDM. With GDM enabled, the settings in the attached image are fine through a few passes of MT5 (1usmus config) but if I enter everything manually in BIOS and disable GDM with 1t it will throw errors instantly. 

What is GDM doing behind the scenes that I'm not seeing?


----------



## ManniX-ITA

madweazl said:


> I'm working on tightening up some RAM timings but haven't been able to disable GDM. With GDM enabled, the settings in the attached image are fine through a few passes of MT5 (1usmus config) but if I enter everything manually in BIOS and disable GDM with 1t it will throw errors instantly.
> 
> What is GDM doing behind the scenes that I'm not seeing?


Is doing a lot of stuff 









integralfx/MemTestHelper


C# WPF to automate HCI MemTest. Contribute to integralfx/MemTestHelper development by creating an account on GitHub.




github.com





My guess is you need much more VDIMM, at least 1.45V.


----------



## madweazl

ManniX-ITA said:


> Is doing a lot of stuff
> 
> 
> 
> 
> 
> 
> 
> 
> 
> integralfx/MemTestHelper
> 
> 
> C# WPF to automate HCI MemTest. Contribute to integralfx/MemTestHelper development by creating an account on GitHub.
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> My guess is you need much more VDIMM, at least 1.45V.


If it's stable at that voltage with GDM on, why would it need to be increased with it disabled? I'm not opposed to increasing it, just trying to understand the reason for the increase. 

Edit: And thanks for the link; I was actually working my way through that but hadn't gotten to the setup times which seem to have done the trick.


----------



## ManniX-ITA

madweazl said:


> If it's stable at that voltage with GDM on, why would it need to be increased with it disabled? I'm not opposed to increasing it, just trying to understand the reason for the increase.


Cause GDM Enabled is slower than 1T, more than a 2T profile well configured.
Thus needs much less voltage to operate.









What is DDR4 Memory Gear-Down Mode? | FuturePlus Systems


A Reliability, Availability and Serviceability (aka RAS) feature more clearly documented in the new JEDEC DDR4 Rev B spec, Gear-down mode, allows the DRAM Address/Command and Control bus to use every other rising clock of the DDR4 Memory bus clock. The Memory Controller indicates that it wants ...




www.futureplus.com


----------



## Veii

ManniX-ITA said:


> Cause GDM Enabled is slower than 1T, more than a 2T profile well configured.
> Thus needs much less voltage to operate.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> What is DDR4 Memory Gear-Down Mode? | FuturePlus Systems
> 
> 
> A Reliability, Availability and Serviceability (aka RAS) feature more clearly documented in the new JEDEC DDR4 Rev B spec, Gear-down mode, allows the DRAM Address/Command and Control bus to use every other rising clock of the DDR4 Memory bus clock. The Memory Controller indicates that it wants ...
> 
> 
> 
> 
> www.futureplus.com


They describe it well as 2N, but don't mention that MUX chips and Sensing I/O runs at half speed too
soo it's more than 2N , and why it was stupidly called 2.5 not 1.5(N or T)
Them running at half speed , aside from rounding also allows lower tRFC to run than on pure 2T - while the difference between both 2T and GDM is only powering related and doesn't need any voltage increase
Not to forget that 2T has quite an access latency benefit & allows the user to utilize all timings "cleanly" - soo allows a benefit over GDM without any voltage increase
1T is another world


----------



## jomama22

Veii said:


> This his how usually the stock powerplans behave
> 
> 
> 
> 
> 
> 
> 
> 
> Here you won't see a difference, 100% ACPI means P0 state - soo 3.7ghz with subtle boost peaks to 130 (4.85 for me)
> There are still here and there little boost spikes, but it's the nature of the mess they created & being dynamic
> ~ but yet it doesn't boost down and takes all cores up to waste power & limit maximum sillicon freq
> 
> 
> 
> 
> 
> 
> 
> 
> This is how it could look , if C-States started to function and it was CPPC aware
> (PowerSaver Powerplan @ 4% minimum state)
> 
> 
> 
> 
> 
> 
> 
> 
> Sadly, the "powersaver" is simply too slow - and ramps too slow, also it functions on per core base and takes the thread with it up ~ even without the thread even needing to boost up as it gets no load
> But again, doesn't take it up in unison, keeps all cores at P2 state near 1100Mhz , and rarely once a blue moon suspends some "bad" cores
> = bad powerplan ~ also does rarely spike boost and is not fine (spikes can cause random shutdowns or fit safety throttling)
> 
> This is how a "bit too aggressive by intention" powerplan looks (my little mess)
> View attachment 2489314
> 
> By the nature of the dLDO design, it has to keep some cores up and running at P0 while boosting others up
> And by intention of PatchD+ , there are tiny but existing overboost spikes - well "tiny" = 400mhz speedstep jumps
> But what you also can see, is that anything that isn't "requested" is lowering itself to Sleep State as Parked, but not hibernated core
> This allows me to free up as much from the EDC limit as possible ~ soo allowing it to reach peak boost while suspending unused cores
> It is CPPC aware too - where the little spikes on the right side, are OCN refreshing itself ~ especially the adds on the right
> 
> Having "no difference" , means that your powerplan does nothing
> I'd recommend to check out @ManniX-ITA work here:
> (3) Ryzen Custom Power Plans for Windows 10 (Balanced and Ultimate) | Overclock.net
> My mess might be useful and intentionally abuses overboost - but it's a bit messy now that dLDO_injection does leverage C-States per cores
> It's just a bit too aggressive and causes random reboots on systems with not well balanced chiplet quality
> (as the voltage differenciation is too big and FIT crashes , while dLDO tries to smooth out supplied voltage)
> Well aswell with CTR ~ bit buggy, just the Cinebench Boost Tester on the 5950X doesn't lie
> * soo i need more time, to redesign it with being not soo aggressive, yet abusing overboost with a peak limiter


Yeah, I have read your other posts on the matter. Personally, until it's possible to have c-states enabled allow for quantifiable gains at anything beyond single thread boosting behavior, the trade off in dpc latency just isn't worth it to me. Idle temperatures aren't any worry for me either so it makes the decision to keep c-states off a bit easier.


----------



## Veii

jomama22 said:


> Yeah, I have read your other posts on the matter. Personally, until it's possible to have c-states enabled allow for quantifiable gains at anything beyond single thread boosting behavior, the trade off in dpc latency just isn't worth it to me. Idle temperatures aren't any worry for me either so it makes the decision to keep c-states off a bit easier.


Oh in this sense/goal, disable CPPC too 
that has a big gain on DPC latency

Same as you don't need virtualisation


Spoiler: Snippet


----------



## jomama22

Veii said:


> Oh in this sense/goal, disable CPPC too
> that has a big gain on DPC latency
> 
> Same as you don't need virtualisation
> 
> 
> Spoiler: Snippet


I actually do that when I decide to just run an all core OC. CPPC does come in handy when I'm just playing lighter threaded games or doing work, but for any highly threaded game, I usually just stick to the all-core.

Disabling c-states and leaving PBO enabled is just a jack of all trades, master of none. PBO will beat out a 4.8 all-core up to 10 threads in r20 for example, so it makes sense in use cases where I'll be allover the place in what work/play I'm doing to just keep it on with the dynamic oc switcher (that, and when I'm too lazy to go into the bios and just set the all-core lol).


----------



## FleischmannTV

When you talk about disabling CPPC, do you mean entirely or just Preferred Cores?


----------



## lmfodor

Hi Veii, how good it is to have you here again 



Veii said:


> When it comes to minimum required voltage for 3800C14-14-14, it depends on:
> 
> The PCB quality (layers = fixed amount of leakage & heat = variable amount of leakage)
> A general rule of understanding how tRP 14 behaves by frequency
> And the RTT's.
> RTT_NOM should be increased if you increase voltage (lower divider, stronger value)
> RTT_WR is dynamic ODT and a whole layer ontop of the current ODT & powerdown signal path (dynamic)
> RTT_PARK depends on the PCB quality and will increase heat if you increase it. Requirements depend on the IMC's FW and preconfigured RZQ values (more to it later)
> 
> 3800 MT/s can need between 1.5-1.6v , usually it's 1.5v and above
> But 1.5 flat is only at 731 (DR) or 005 (SR) ~ where after 1.51-1.52 you start to see instability , till you use 705 then 1.54v is your instability range
> Higher voltage either doesn't work because of heat or start to give you fully dropped channels at 1.54-1.55. If this happens, 1..56+ would kill the PCB.
> It depends
> 
> Take a look at this current set


This is my little obsession, to achieve 3800 flat 14, even though many times a lot of member told me to give up, but every time I read you I think it is possible, more so than I have seen it with a member and ad Igor that both could ahieved it without errors and almost most values in AUTO. I can suspect that maybe the latency or bandwithd is not that good, but I need to see it, unless try to lowering the tRCDRD to 14 and doesn´t have that endless amount of errors 6s and 12. What I learned from our friend Kendarwolf and his timings, beyond the rule of so low tRAS is that we are running with only 1.5V or even it with 1.49 or 1.48 adjusted values with 2T disabled. So there comes my first big question, as you say, how to stabilize not the voltage, but precisely the amperage and the resistances, more considering that we do not need as much voltage as is usually said, is it because our mems are dual Rank? Will these -*GTZN *PCBs model support tighter values with lower voltages? I saw it in every case, even the ones they achieved 3800-14 flat.

I must confess that I don´t know what tBL is so googling it I found the 1Usmus message posted here 4 years ago!


Spoiler: 1Usmus Explanation



Timing rules of a successful system on 3200

1) tRRDS 6 tRRDL 8(9) tFAW 32 or tFAW 34 (the minimum time between the activation of the rows of different banks. Architectually open a row in another bank can be immediately after the opening of the line in the first bank. The restriction is purely electrical - the activation takes a lot of energy, and therefore with frequent line activations, the electrical load on the circuit is very high. To reduce it, this delay was introduced. Do not make them low, you will not get any boost other than beautiful numbers)

2) tRDWR 6 (or 7 or 8) + tWRRD 3 (Read-to-write and write-to-read latency, or the time that must elapse between issuing sequential read/write or write/read commands.)

3) tRCDRD = tCL or tRCDRD = tCL + 1 (or 2) ( the time required to activate the bank line, or the minimum time between the RAS # signal and the column selection signal (CAS #). It's a bottleneck in the memory controller Ryzen )

4) tRTP 12 or 8 (the minimum interval between the command to read before the command for the preliminary charge)

5) In almost all my experiments, tCKE + power down enable caused errors. My suggestion is tCKE 1 + power down disable ( tCKE is the minimum number of cycles that must pass before a clock can go from an active state to a low state )

6) Memory interleaving size , more size = better

7) In conclusion of this part, devoted to the delays in accessing data, we will consider the main relationships between the most important timings parameters for the example of simpler data reading operations. As we discussed above, in the simplest and most general case, for the batch reading of a given amount of data (2, 4 or 8 elements), the following operations must be performed:

1. activate the row in the memory bank using the ACTIVATE command;

2. issue a command to read READ data;

3. read data coming to the external data bus of the chip;

4. close the line using the PRECHARGE row recharging command (as an option, this is done automatically if you use the "RD + AP" command in the second step).

The time interval between the first and second operations is the "delay between RAS # and CAS #" (tRCD), between the second and third - "CAS # delay" (tCL). The time interval between the third and fourth operations depends on the length of the transmitted packet. Strictly speaking, in memory bus cycles, it is equal to the length of the transmitted packet (2, 4 or 8) divided by the number of data elements transmitted on the external bus in one clock cycle - 1 for SDR type devices, 2 for DDR devices. Conditionally, we call this value "tBL" ( tBL for DDR4 = 8 )

It is important to note that the SDRAM chips allow the third and fourth operations to be performed in a sense "in parallel". To be precise, the PRECHARGE command can be used for a number of measures x before the moment at which the last data element of the requested packet occurs, without fear of the occurrence of an "interruption" of the transmitted packet (the latter occurs if the PRECHARGE command is submitted after commands READ with a time interval, less than x). Without going into details, we note that this time interval is equal to the value of the delay of the signal CAS # minus one (x = tCL - 1).

Finally, the time interval between the fourth operation and the subsequent repetition of the first operation of the cycle is the "recharge time of the line" (tRP).

At the same time, the minimum activity time of the line (from the ACTIVATE command to the PRECHARGE command, tRAS), by its definition, exactly corresponds to the time interval between the start of the first and the beginning of the fourth operation. This implies the first important relationship between memory timings:

tRAS, min = tRCD + tCL + (tBL - (tCL-1)) - 1,
where tRCD is the execution time of the first operation, tCL is the second, (tBL - (tCL-1)) is the third; finally, the subtraction of the unit is due to the fact that the tRAS period does not include the clock on which the PRECHARGE command is given. Reducing this expression, we get:
tRAS, min = tRCD + tBL.

The rather amazing conclusion resulting from the detailed consideration of the data access scheme contained in SDRAM memory is that the minimum value of tRAS does not depend (!) On the delay value CAS #, tCL. The dependence of the former on the latter is a fairly common misconception, quite often encountered in various manuals on RAM.


Continuing with your analysis of how to achive 14-Flat, I guess the PCB Quality have to be good, I know, the price does´t tell anything about the quality, maybe it´s just marketing, but in terms of layears, anf fixed amount of leakage and head.. is not something I could estimate.. just keep trying.

_The PCB quality (layers = fixed amount of leakage & heat = variable amount of leakage)_
_A general rule of understanding how tRP 14 behaves by frequency_
_And the RTT's._
What is interesting is what you tell about the RTTs, a topic where there is not so much information but there are several "rules" such as 6-3-3 or 7-3-1, or 0-0-5 for SR. Despite everything, I continue to see in the charts of the best timings, many that run 240ohm in RTTPark with 1.5V and a little higher, something totally not recommended. In my case, with the Kedarwolf values I have (we have) an excellent bandwitdh, low latency and we are almost at the maximum limits of 3800. Perhaps as you told me many times, being 14-flat it should be much faster, but think than we still haven't managed to lower the tRCDRD to 15 in 2T. There is always something that goes out of sync and logically the voltage should be increased and consequently the impedances. So yes, if it does not exceed 1.52V, it would continue with 7-3-1 (in reality we are using 0-3-1) and in case of requiring 1.54 7-0-5 for Dual Rank

Something that also surprised me about the Kedarwolf configuration is the high vSOC, which I always worry about because in my opinion, we have to be careful with LLCs, right? It was one of the questions I asked him. Because it is actually running LLC2 while I am 3 for CPU and 4 for VDDSOC. 1.2x worries me a bit, but I must confess that it is the most stable configuration that passed all the tests, more than 75 cycles of TM5 1usmus, Y-cruncher for hours, TM5 Anta777 .. More than enough.

Now the challenge is, starting from these values as "Baseline", how to try to unify the 14-flats in a thoughtful way. I would love to, as you did, put together the current values that I have in an excel, and simulate what the scenario of 3800-14-14-14 would be, theoretical, at least to know which variables to adjust.



Veii said:


> At this point, isn't stable at all. Not even remotely
> VDDG needed a remake with voltages, and RTT's where messed up
> This tFAW obscureness above, was randomly found ~ after beating my head against a wall of #2's for the last days
> AMD changed something !
> 
> Is 2* tFAW recommendable ?
> Unsure, it's performance is still here-and-there funky
> But 4* tFAW at least on my set doesn't work at all. Some new implemented BURST read option , breaks stability fully
> It likely is this option that @KedarWolf saw:
> 
> Spoiler
> 
> 900-1020-1100 + tad higher SOC
> is currently the new norm for me
> Y-Cruncher was rebooting on "too low" SOC & crashing on "too high IOD" (was 1120mV before)
> 
> Hope this helps someone who struggles with stability on 1.2.0.1+ AGESA
> RZQ is higher, it doesn't behave like 240ohm. Maybe DQS is finally at 480ohm instead of 240 , like "hidden" half a year ago in their bios changes
> Anywho:
> - lower IOD, and weaker RTT's are required for 1.2.0.1 / 1.2.0.2 to sustain stability


Two things that come up about this that you comment, 1) I see that you updated to the SMU 56.50, it surprised me, you always recommended that it be in an older one because the IMC was all broken. It is true, I do not know if ASUS has the correct SMU, it happened to me that they skipped several that are in MSI for example. And even more, something that I always wanted to know is that it is the famous BURST that you always put in your notes, now I see the Screenshot of MSI's KendarWolf and I see that there is the option. It makes me want to switch to Unify-X instead of Dark Hero! There are many more options on MSI.

On the other hand, I understand the tFAW, actually from what I see in your screenshot, in one scenario tFAW 24 passes the tests, and the x4 rule is met, but in the other it fails and you raise the vSOC a little. I will take as a rule to increase the IOD and VSOC a bit when I change versions (900-1020-1100 + tad higher SOC)



Veii said:


> lmfodor said:
> 
> That is why my question about how you got to such a low tRAS, or such a low tRTP, must have a reason, in fact, see how well it worked for me, but like that, I did not learn anything!
> 
> KedarWolf's set was an experiment
> Testing of tRP. The opposite on "instead of lowering it to gain room in order to lower tRC"
> Increasing it, as it's one of the timings like tRC, which has to elapse and is not breakable
> tRAS was tried to be pushed at the lowest possible value
> I think it was
> tRCDavg + tCL + (tBL - (tCL-1)) - 1
> 14+14+ (-6) = 22 (8-13-1)
> tBL used as 8 here instead of 4
> 
> The formula above tho was found by 1usmus 😇
> Overall many little experiments happen along Matisse lifespan, when we where 1900 FCLK locked and bored
> 
> Spoiler: This is what i can find from the old data:
> 
> Many many little shenanigans and snippets ~ where most of the things are deprecated and have changed. But just so you know behind the scenes
> Want to remind everyone who judges on tRFC mini - that it took a loong time to build, it's not that random
> 
> I can barely remember, but i think the goal for KedarWolf's set was to either use minimum tRAS or match tRC, just in order to match some abstract tRCD_WR ruleset
> Soo tRP was one of the values which can scale down, but also can scale up to lower voltage requirements - as more time to (p)recharge will exist.
> A voltage leakage experiment, with from todays perspective, looks a bit off on tRC. Just what works well, works well


I love that spreadsheet you have, in fact I always use the tRFC Mini a lot, but I see that your spreadsheet has many fields, is it something public or yours, can it be shared? What I love is what you did to go from a scenario A to B, for example I see that from the original scenario to the one with the formula of 1Usmus you go from tCL 15 to 13, low the tRCDRD which is what costs us the most, from 15 to 14 and the tRP / tRAS with the 1Usmus formula, which I honestly did not understand well what the tBL is, and then the tRTP and the tWR without complying with the rule, which I see which is a constant. Actually, these relationships are what I would like to know, in short everything is related, by preload, delays, cycles. There should be some form that is not only for the calculation, but that maintains the relationships and explains it, I think it would help us a lot to understand that things should be related either in ns, in delays, in voltages and and impedances, right? Can you share your spreadsheet? 

Lasty, about *Curve Optimzer and Offset*, I have a question that you can surely guide me

I started like many with a configuration like defining by core the maximum value of negative curve in -30 and then as they were failing with Core Cycler I reached a "well adjusted" and stable curve. However, the other day I tried taking the minimum value, which is -24 and I put it in all All Core, following your advice a bit that All Core maintains the AMD vs Per Core algorithm, and that everything is solved with a small offset positive. But he also asks Kendarwolf because he, with a tight curve, puts a negative offset, and as I mentioned before a lower LLCs for VRMs, both CPU and VDDSCO, in my case I have 3 and 4, and he 2 and 2. Which I am concerned in the face of a high vSOC above 1.2v. What would be the recommendation? In addition to the PPT / TDC / EDC values, I have exaggerated values, 300, 235 and 400. I know that I reached the fuse limit in 200A, so I don't understand why to put values higher than 200, right? I saw that you use 175-145-400A , like i do. With lifted cTDP and Package Power Limits of 400W (CBS, SMU), this would be better instead of a higher PPT and even higher TDC? The Packaged Power Limit is type of override of PPT?

What do you recommend? There is no uniform information on how to work the curves well and also, take care of the processor, at least protect it from amperage spikes



Veii said:


> C-States generation is needed but doesn't affect the overboost outcome
> as it only happens when cores fully hibernate
> C-State generation is needed to shuffle load and manage the powerbudget.
> It's needed so cores can lower frequency down to 550mhz - although default powerplans are not designed well & won't lower frequency
> Lowering freq doesn't have to be negative neither for access latency, nor for DPC calls - but the powerplans are just not designed for it
> 
> Disabling both would keep the CPU between 3.7ghz (P0, or for some 3.8Ghz) and the boost
> Yet cores would consume at 0.9v P0 state resources, which could be assigned to other cores
> difference example on a 5950X between the highperf powerplan and my take on it:
> 
> 
> 
> 
> 
> 
> 
> 
> So there is surely something to gain 75-125mhz on loower powerdraw for the 1st CCD
> 
> It generally didn't boost high, it had no PBO fixes or anything
> but that's been his setup, with boost-tester under cinebench R20


I don’t have the option to activate the *C-States, *I don't know if it will be any version of SMU in particular, but so far in all as soon as I activate it, I have reboots both in idle and in load. For example, I run TM5, Y-Cruncher or some game and it reboots. I read everywhere about deactivating C-States, but maybe there is some other basic error that is not allowing to activate it[/QUOTE]

Thanks as always for your great support!!!
I think you should offer some kind of course for those of us who want to learn a little more, I know that you do not help with a commercial purpose, which speaks of your passion and desire to teach or help, because there are many people with knowledge, but not with so eager to help so many people on an issue that is not so easy. If not, you have to write a book!


----------



## RonLazer

lmfodor said:


> Hi Veii, how good it is to have you here again
> 
> 
> This is my little obsession, to achieve 3800 flat 14, even though many times a lot of member told me to give up, but every time I read you I think it is possible, more so than I have seen it with a member and ad Igor that both could ahieved it without errors and almost most values in AUTO. I can suspect that maybe the latency or bandwithd is not that good, but I need to see it, unless try to lowering the tRCDRD to 14 and doesn´t have that endless amount of errors 6s and 12. What I learned from our friend Kendarwolf and his timings, beyond the rule of so low tRAS is that we are running with only 1.5V or even it with 1.49 or 1.48 adjusted values with 2T disabled. So there comes my first big question, as you say, how to stabilize not the voltage, but precisely the amperage and the resistances, more considering that we do not need as much voltage as is usually said, is it because our mems are dual Rank? Will these -*GTZN *PCBs model support tighter values with lower voltages? I saw it in every case, even the ones they achieved 3800-14 flat.
> 
> I must confess that I don´t know what tBL is so googling it I found the 1Usmus message posted here 4 years ago!
> 
> 
> Spoiler: 1Usmus Explanation
> 
> 
> 
> Timing rules of a successful system on 3200
> 
> 1) tRRDS 6 tRRDL 8(9) tFAW 32 or tFAW 34 (the minimum time between the activation of the rows of different banks. Architectually open a row in another bank can be immediately after the opening of the line in the first bank. The restriction is purely electrical - the activation takes a lot of energy, and therefore with frequent line activations, the electrical load on the circuit is very high. To reduce it, this delay was introduced. Do not make them low, you will not get any boost other than beautiful numbers)
> 
> 2) tRDWR 6 (or 7 or 8) + tWRRD 3 (Read-to-write and write-to-read latency, or the time that must elapse between issuing sequential read/write or write/read commands.)
> 
> 3) tRCDRD = tCL or tRCDRD = tCL + 1 (or 2) ( the time required to activate the bank line, or the minimum time between the RAS # signal and the column selection signal (CAS #). It's a bottleneck in the memory controller Ryzen )
> 
> 4) tRTP 12 or 8 (the minimum interval between the command to read before the command for the preliminary charge)
> 
> 5) In almost all my experiments, tCKE + power down enable caused errors. My suggestion is tCKE 1 + power down disable ( tCKE is the minimum number of cycles that must pass before a clock can go from an active state to a low state )
> 
> 6) Memory interleaving size , more size = better
> 
> 7) In conclusion of this part, devoted to the delays in accessing data, we will consider the main relationships between the most important timings parameters for the example of simpler data reading operations. As we discussed above, in the simplest and most general case, for the batch reading of a given amount of data (2, 4 or 8 elements), the following operations must be performed:
> 
> 1. activate the row in the memory bank using the ACTIVATE command;
> 
> 2. issue a command to read READ data;
> 
> 3. read data coming to the external data bus of the chip;
> 
> 4. close the line using the PRECHARGE row recharging command (as an option, this is done automatically if you use the "RD + AP" command in the second step).
> 
> The time interval between the first and second operations is the "delay between RAS # and CAS #" (tRCD), between the second and third - "CAS # delay" (tCL). The time interval between the third and fourth operations depends on the length of the transmitted packet. Strictly speaking, in memory bus cycles, it is equal to the length of the transmitted packet (2, 4 or 8) divided by the number of data elements transmitted on the external bus in one clock cycle - 1 for SDR type devices, 2 for DDR devices. Conditionally, we call this value "tBL" ( tBL for DDR4 = 8 )
> 
> It is important to note that the SDRAM chips allow the third and fourth operations to be performed in a sense "in parallel". To be precise, the PRECHARGE command can be used for a number of measures x before the moment at which the last data element of the requested packet occurs, without fear of the occurrence of an "interruption" of the transmitted packet (the latter occurs if the PRECHARGE command is submitted after commands READ with a time interval, less than x). Without going into details, we note that this time interval is equal to the value of the delay of the signal CAS # minus one (x = tCL - 1).
> 
> Finally, the time interval between the fourth operation and the subsequent repetition of the first operation of the cycle is the "recharge time of the line" (tRP).
> 
> At the same time, the minimum activity time of the line (from the ACTIVATE command to the PRECHARGE command, tRAS), by its definition, exactly corresponds to the time interval between the start of the first and the beginning of the fourth operation. This implies the first important relationship between memory timings:
> 
> tRAS, min = tRCD + tCL + (tBL - (tCL-1)) - 1,
> where tRCD is the execution time of the first operation, tCL is the second, (tBL - (tCL-1)) is the third; finally, the subtraction of the unit is due to the fact that the tRAS period does not include the clock on which the PRECHARGE command is given. Reducing this expression, we get:
> tRAS, min = tRCD + tBL.
> 
> The rather amazing conclusion resulting from the detailed consideration of the data access scheme contained in SDRAM memory is that the minimum value of tRAS does not depend (!) On the delay value CAS #, tCL. The dependence of the former on the latter is a fairly common misconception, quite often encountered in various manuals on RAM.
> 
> 
> Continuing with your analys of how to achive 14-Flat, I guess the PCB Quality have to be good, I know, the price does´t tell anything about the quality, maybe it´s just marketing, but in terms of layears, anf fixed amount of leakage and head.. is not something I could estimate.. just keep trying.
> 
> The PCB quality (layers = fixed amount of leakage & heat = variable amount of leakage)
> A general rule of understanding how tRP 14 behaves by frequency
> And the RTT's.
> What is interesting is what you tell about the RTTs, a topic where there is not so much information but there are several "rules" such as 6-3-3 or 7-3-1, or 0-0-5 for SR. Despite everything, I continue to see in the charts of the best timings, many that run 240ohm in RTTPark with 1.5V and a little higher, something totally not recommended. In my case, with the Kedarwolf values I have (we have) an excellent bandwitdh, low latency and we are almost at the maximum limits of 3800. Perhaps as you told me many times, being 14-flat it should be much faster, but think than we still haven't managed to lower the tRCDRD to 15 in 2T. There is always something that goes out of sync and logically the voltage should be increased and consequently the impedances. So yes, if it does not exceed 1.52V, it would continue with 7-3-1 (in reality we are using 0-3-1) and in case of requiring 1.54 7-0-5 for Dual Rank
> 
> Something that also surprised me about the Kedarwolf configuration is the high vSOC, which I always worry about because in my opinion, we have to be careful with LLCs, right? It was one of the questions I asked him. Because it is actually running LLC2 while I am 3 for CPU and 4 for VDDSOC. 1.2x worries me a bit, but I must confess that it is the most stable configuration that passed all the tests, more than 75 cycles of TM5 1usmus, Y-cruncher for hours, TM5 Anta777 .. More than enough.
> 
> Now the challenge is, starting from these values as "Baseline", how to try to unify the 14-flats in a thoughtful way. I would love to, as you did, put together the current values that I have in an excel, and simulate what the scenario of 3800-14-14-14 would be, theoretical, at least to know which variables to adjust.
> 
> 
> Two things that come up about this that you comment, 1) I see that you updated to the SMU 56.50, it surprised me, you always recommended that it be in an older one because the IMC was all broken. It is true, I do not know if ASUS has the correct SMU, it happened to me that they skipped several that are in MSI for example. And even more, something that I always wanted to know is that it is the famous BURST that you always put in your notes, now I see the Screenshot of MSI's KendarWolf and I see that there is the option. It makes me want to switch to Unify-X instead of Dark Hero! There are many more options on MSI.
> 
> On the other hand, I understand the tFAW, actually from what I see in your screenshot, in one scenario tFAW 24 passes the tests, and the x4 rule is met, but in the other it fails and you raise the vSOC a little. I will take as a rule to increase the IOD and VSOC a bit when I change versions (900-1020-1100 + tad higher SOC)


I went through a process of testing tRCDRD 14 @3800MHz and I really do think it's impossible with the Zen3 IMC in the way you're thinking of. There is a maximum capacity for incoming data that any memory controller can handle at once, and past a certain set of timings you can overflow it. The Zen3 IMC seems to cap out at 7.5ns tRCDRD no matter what voltages, impedances, PCBs, or other timings you try - and it's consistent across the entire frequency range. 3733MHz tRCD 14 works just fine with no adjustments needed, tRCD 15 works all the way up to 4000MHz, and breaks again at 4066MHz when real tRCD timing falls back below 7.5ns.

What you will find is that overflowing the memory controller is not triggered reliably by synthetic stress tests, and if you loosen timings like tRRDS/tRRDL/tFAW/tRDRDSD etc. you can space out the errors more and more, potentially even not hitting one in a 4 hour stress test. You'll notice that Veii uses much looser tRRDS/tRRDL than most users on here, which is a hit to bandwidth but will limit the frequency of these sorts of errors in synthetic tests. But real workloads are far more chaotic, less repetitive, and it's not worth the risk that you're rolling the dice on the right workload tripping up the IMC and crashing/corrupting data. I managed to pass a full Anta77 Extreme1 config run once, and then I ran my quantum simulation code which is built on Fortran and uses older instruction sets - and the very first FFT was totally corrupted.

If it's just an aesthetic desire to have even numbers then you'll have to settle for 3733MHz, or 3600MHz. If you just want minimum possible latency, then just run tRCD 15 or 16 and accept that you're chasing fractions of a % of performance anyway. If you don't care and just want 3800MHz tRCDRD 14 at any costs, then loosen up your memory-controller subtimings (basically everything in the right-hand column of Zentimings except tRTP and tCWL, and tRRDS/tRRDL/tWTRS/tWTRL) until the errors become infrequent, but understanding you're rolling the dice on stability.


----------



## Dar|{cyde

I can do 14-flat 3866Mhz no problem. Just needs enough voltage (and hours of testing all the right settings lol). Maybe it's easier for a single CCD chip? It's definitely possible.


----------



## RonLazer

@Veii I know this is the "daily stability" thread, but there isn't a thread for FCLK XOC so I hope the admins don't mind, but if my goal is just pure FCLK performance, while running a static 5GHz OC, with zero regards for stability provided it can survive a single-threaded benchmark - what is the best SMU version and what CBS settings do you recommend? I managed to boot 2100MHz FCLK on AGESA 1.1.9 (SMU 56.43 I believe?) but the memory performance totally falls apart in any benchmark and cranking up SOC/IOD/PLL voltages only helps up to a point, which is still much slower than 2000MHz at the same timings. What's weird is I can trick the FCLK into running the same frequency with a BCLK overclock and with enough PLL performance goes back to the expected value, so it does seem to be a hardcoded lock in the ABL related to the link-equalisation/CRC but I have no idea how to bypass it.


----------



## RonLazer

Dar|{cyde said:


> I can do 14-flat 3866Mhz no problem. Just needs enough voltage (and hours of testing all the right settings lol). Maybe it's easier for a single CCD chip? It's definitely possible.


Single CCD chip _shouldn't _matter, they have full read bandwidth. Like I said, it's not a question of being able to pass a stress test as a one-off, it's a question of if it can pass multiple stress tests with multiple instruction sets. If you can pass:

1. OCCT CPU large dataset SSE3 - 1hr
2. OCCT CPU large dataset AVX2 - 1hr
3. OCCT memory SSE3 -30mins
4. OCCT memory AVX2 - 30mins
5. tm5 Anta777 Extreme1

Then I'd be very curious to see what configuration you used. I guess the single CCD chips don't tend to run as fast or have as many threads, so they might simply not hit the IOD with enough read ACT commands in a short enough window to flood it? I stand by my core point though - it's just not worth the risk if you're actually interested in daily stability, we're really talking margin of error performance improvements.


----------



## lmfodor

jomama22 said:


> I actually do that when I decide to just run an all core OC. CPPC does come in handy when I'm just playing lighter threaded games or doing work, but for any highly threaded game, I usually just stick to the all-core.
> 
> Disabling c-states and leaving PBO enabled is just a jack of all trades, master of none. PBO will beat out a 4.8 all-core up to 10 threads in r20 for example, so it makes sense in use cases where I'll be allover the place in what work/play I'm doing to just keep it on with the dynamic oc switcher (that, and when I'm too lazy to go into the bios and just set the all-core lol).


This is a good point, I had not noticed it, but for example when I run CB20 I notice that Windows moves between the three best cores, I did not imagine that was why. Are those values that recommend enabling, but then, should we disable preferred cores or both? Thanks!


----------



## TimeDrapery

@Veii

Alright, I'm free to reply more thoroughly

Regarding the timing set in my last post, let's disregard it... A second set of the same 2 × 8Gb F4-3200C14-GTZR arrived for me today and I've installed them and started exploring



Spoiler



I started by making ready for the new with a CMOS clear and a re-flashing of both BIOS with the latest from Gigabyte (F13j / 1.2.0.2)

After configuring and whatnot I set my voltages (I never enable XMP, I dunno if this hampers me in some way [I doubt it unless Gigabyte is doing sneaky things with behind-the-scenes changes when XMP is enabled... Now that I think about that I feel I should look into it further as I'll bet they are] but I hate that the changes made when toggling XMP on or XMP Support Level aren't explicitly described) and started walking the now 4 × 8GB (SR) "kit" up and up in memory speed, keeping the fabric with it

I was especially interested in how the Auto rules would handle powering the memory... RTTs, CAD BUS, all that

I let the mobo drive on all timings as I was interested to see what it did there too... With XMP disabled it appears to me as if it did what it could to scale JEDEC timings all the way up to 3800MT/s










I ran about with the Auto rules' decisions on powering for a bit, with the exception of the CAD BUS and ProcODT... I realize now, after re-reading your reply, the ProcODT is too low for the now 4 × 8GB set










Here's the baseline I'm working from, shown above...

I'll have to check when I'm at the computer to see how TM5 is coming along but I'm pretty sure I've set 34.3Ω for ProcODT currently with 24.0Ω-20.0Ω-20.0Ω-24.0Ω CAD BUS and 6/3/6 for RTTs as the errors I've seen so far point to powering...



Ah, dinner time... I'll be back

When you talk about straight primary timing sets often running faster than those with tRCDWR bottomed out and tRCDRD one to two above tCL, would tCL being one value higher than what follows (for example, 15-14-14-28 or 32) be more effective? I've seen XMP profiles like this on B-die kits often... My TeamGroup 4000MT/s kit wants to run 18-20-20-40 on XMP but, being B-die, they're "supposed" to run flat primaries, right? Is this relevant?

Lemme go see what TM5 is doing...


----------



## lmfodor

Hi, here's my SiSandra Multicore results, what do you thing about my scores and the Inter-Thread Latency and Inter-Core (same Module) Latency? Are good for 5900x? what should I consider about all this information?










Spoiler: SiSandra Multicore Results



SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 129.54GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Aggregate Inter-Thread Latency : 44.1ns (12.5ns - 63.7ns)
Inter-Thread (same Core) Latency : 12.8ns
Inter-Core (same Module) Latency : 25.5ns
Inter-Module (same Package) Latency : 62.2ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.4GB/s
No. Threads : 24
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 35.85MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Aggregate Inter-Thread Latency : 0.12ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 
U0-U2 Data Latency : 24.8ns
U0-U4 Data Latency : 25.7ns
U0-U6 Data Latency : 24.0ns
U0-U8 Data Latency : 25.4ns
U0-U10 Data Latency : 24.3ns
U0-U12 Data Latency : 62.8ns
U0-U14 Data Latency : 62.4ns
U0-U16 Data Latency : 62.9ns
U0-U18 Data Latency : 62.0ns
U0-U20 Data Latency : 62.2ns
U0-U22 Data Latency : 62.4ns
U0-U1 Data Latency : 12.6ns
U0-U3 Data Latency : 24.8ns
U0-U5 Data Latency : 25.7ns
U0-U7 Data Latency : 23.9ns
U0-U9 Data Latency : 25.4ns
U0-U11 Data Latency : 24.4ns
U0-U13 Data Latency : 62.0ns
U0-U15 Data Latency : 62.3ns
U0-U17 Data Latency : 62.2ns
U0-U19 Data Latency : 62.0ns
U0-U21 Data Latency : 62.7ns
U0-U23 Data Latency : 62.4ns
U2-U4 Data Latency : 24.6ns
U2-U6 Data Latency : 24.8ns
U2-U8 Data Latency : 24.4ns
U2-U10 Data Latency : 25.4ns
U2-U12 Data Latency : 61.8ns
U2-U14 Data Latency : 61.7ns
U2-U16 Data Latency : 62.7ns
U2-U18 Data Latency : 62.0ns
U2-U20 Data Latency : 62.1ns
U2-U22 Data Latency : 62.3ns
U2-U1 Data Latency : 24.7ns
U2-U3 Data Latency : 12.6ns
U2-U5 Data Latency : 24.6ns
U2-U7 Data Latency : 24.8ns
U2-U9 Data Latency : 24.4ns
U2-U11 Data Latency : 25.4ns
U2-U13 Data Latency : 62.6ns
U2-U15 Data Latency : 62.5ns
U2-U17 Data Latency : 63.2ns
U2-U19 Data Latency : 62.1ns
U2-U21 Data Latency : 61.9ns
U2-U23 Data Latency : 62.2ns
U4-U6 Data Latency : 24.0ns
U4-U8 Data Latency : 26.9ns
U4-U10 Data Latency : 25.6ns
U4-U12 Data Latency : 62.8ns
U4-U14 Data Latency : 62.8ns
U4-U16 Data Latency : 62.6ns
U4-U18 Data Latency : 61.3ns
U4-U20 Data Latency : 62.4ns
U4-U22 Data Latency : 62.9ns
U4-U1 Data Latency : 25.8ns
U4-U3 Data Latency : 24.8ns
U4-U5 Data Latency : 12.7ns
U4-U7 Data Latency : 24.1ns
U4-U9 Data Latency : 27.0ns
U4-U11 Data Latency : 25.5ns
U4-U13 Data Latency : 62.2ns
U4-U15 Data Latency : 62.2ns
U4-U17 Data Latency : 62.0ns
U4-U19 Data Latency : 62.6ns
U4-U21 Data Latency : 62.8ns
U4-U23 Data Latency : 63.3ns
U6-U8 Data Latency : 25.6ns
U6-U10 Data Latency : 26.3ns
U6-U12 Data Latency : 61.3ns
U6-U14 Data Latency : 62.1ns
U6-U16 Data Latency : 61.7ns
U6-U18 Data Latency : 61.8ns
U6-U20 Data Latency : 62.5ns
U6-U22 Data Latency : 62.7ns
U6-U1 Data Latency : 24.3ns
U6-U3 Data Latency : 25.3ns
U6-U5 Data Latency : 24.2ns
U6-U7 Data Latency : 12.7ns
U6-U9 Data Latency : 25.6ns
U6-U11 Data Latency : 26.3ns
U6-U13 Data Latency : 62.1ns
U6-U15 Data Latency : 62.5ns
U6-U17 Data Latency : 62.6ns
U6-U19 Data Latency : 61.9ns
U6-U21 Data Latency : 62.3ns
U6-U23 Data Latency : 62.3ns
U8-U10 Data Latency : 28.0ns
U8-U12 Data Latency : 62.5ns
U8-U14 Data Latency : 62.1ns
U8-U16 Data Latency : 63.7ns
U8-U18 Data Latency : 62.0ns
U8-U20 Data Latency : 63.4ns
U8-U22 Data Latency : 62.9ns
U8-U1 Data Latency : 25.8ns
U8-U3 Data Latency : 24.9ns
U8-U5 Data Latency : 26.8ns
U8-U7 Data Latency : 26.2ns
U8-U9 Data Latency : 12.6ns
U8-U11 Data Latency : 28.0ns
U8-U13 Data Latency : 62.4ns
U8-U15 Data Latency : 61.9ns
U8-U17 Data Latency : 62.9ns
U8-U19 Data Latency : 61.8ns
U8-U21 Data Latency : 63.1ns
U8-U23 Data Latency : 63.3ns
U10-U12 Data Latency : 62.1ns
U10-U14 Data Latency : 62.4ns
U10-U16 Data Latency : 62.9ns
U10-U18 Data Latency : 62.2ns
U10-U20 Data Latency : 62.6ns
U10-U22 Data Latency : 62.7ns
U10-U1 Data Latency : 24.8ns
U10-U3 Data Latency : 25.8ns
U10-U5 Data Latency : 25.5ns
U10-U7 Data Latency : 26.4ns
U10-U9 Data Latency : 27.9ns
U10-U11 Data Latency : 12.5ns
U10-U13 Data Latency : 62.2ns
U10-U15 Data Latency : 61.7ns
U10-U17 Data Latency : 62.3ns
U10-U19 Data Latency : 62.2ns
U10-U21 Data Latency : 62.9ns
U10-U23 Data Latency : 62.9ns
U12-U14 Data Latency : 25.1ns
U12-U16 Data Latency : 26.1ns
U12-U18 Data Latency : 24.3ns
U12-U20 Data Latency : 25.9ns
U12-U22 Data Latency : 24.7ns
U12-U1 Data Latency : 61.9ns
U12-U3 Data Latency : 61.8ns
U12-U5 Data Latency : 61.2ns
U12-U7 Data Latency : 62.1ns
U12-U9 Data Latency : 62.4ns
U12-U11 Data Latency : 62.5ns
U12-U13 Data Latency : 13.0ns
U12-U15 Data Latency : 25.2ns
U12-U17 Data Latency : 26.1ns
U12-U19 Data Latency : 24.3ns
U12-U21 Data Latency : 26.0ns
U12-U23 Data Latency : 24.8ns
U14-U16 Data Latency : 25.0ns
U14-U18 Data Latency : 25.1ns
U14-U20 Data Latency : 24.8ns
U14-U22 Data Latency : 25.9ns
U14-U1 Data Latency : 62.2ns
U14-U3 Data Latency : 61.2ns
U14-U5 Data Latency : 61.5ns
U14-U7 Data Latency : 59.7ns
U14-U9 Data Latency : 61.7ns
U14-U11 Data Latency : 62.2ns
U14-U13 Data Latency : 24.9ns
U14-U15 Data Latency : 12.9ns
U14-U17 Data Latency : 24.5ns
U14-U19 Data Latency : 23.9ns
U14-U21 Data Latency : 24.6ns
U14-U23 Data Latency : 25.9ns
U16-U18 Data Latency : 24.3ns
U16-U20 Data Latency : 26.3ns
U16-U22 Data Latency : 25.7ns
U16-U1 Data Latency : 61.5ns
U16-U3 Data Latency : 62.1ns
U16-U5 Data Latency : 62.6ns
U16-U7 Data Latency : 61.9ns
U16-U9 Data Latency : 62.4ns
U16-U11 Data Latency : 62.6ns
U16-U13 Data Latency : 26.6ns
U16-U15 Data Latency : 24.3ns
U16-U17 Data Latency : 13.1ns
U16-U19 Data Latency : 24.1ns
U16-U21 Data Latency : 26.3ns
U16-U23 Data Latency : 25.7ns
U18-U20 Data Latency : 25.8ns
U18-U22 Data Latency : 27.1ns
U18-U1 Data Latency : 61.5ns
U18-U3 Data Latency : 61.4ns
U18-U5 Data Latency : 61.5ns
U18-U7 Data Latency : 62.4ns
U18-U9 Data Latency : 62.4ns
U18-U11 Data Latency : 62.5ns
U18-U13 Data Latency : 24.5ns
U18-U15 Data Latency : 23.6ns
U18-U17 Data Latency : 24.3ns
U18-U19 Data Latency : 12.9ns
U18-U21 Data Latency : 25.8ns
U18-U23 Data Latency : 27.1ns
U20-U22 Data Latency : 28.2ns
U20-U1 Data Latency : 62.2ns
U20-U3 Data Latency : 62.4ns
U20-U5 Data Latency : 62.4ns
U20-U7 Data Latency : 62.5ns
U20-U9 Data Latency : 61.4ns
U20-U11 Data Latency : 63.5ns
U20-U13 Data Latency : 26.1ns
U20-U15 Data Latency : 24.9ns
U20-U17 Data Latency : 26.5ns
U20-U19 Data Latency : 25.9ns
U20-U21 Data Latency : 13.0ns
U20-U23 Data Latency : 28.3ns
U22-U1 Data Latency : 62.0ns
U22-U3 Data Latency : 62.0ns
U22-U5 Data Latency : 62.3ns
U22-U7 Data Latency : 62.2ns
U22-U9 Data Latency : 63.5ns
U22-U11 Data Latency : 63.1ns
U22-U13 Data Latency : 25.2ns
U22-U15 Data Latency : 26.2ns
U22-U17 Data Latency : 26.1ns
U22-U19 Data Latency : 27.2ns
U22-U21 Data Latency : 28.3ns
U22-U23 Data Latency : 12.9ns
U1-U3 Data Latency : 24.7ns
U1-U5 Data Latency : 26.3ns
U1-U7 Data Latency : 23.5ns
U1-U9 Data Latency : 25.6ns
U1-U11 Data Latency : 24.2ns
U1-U13 Data Latency : 62.7ns
U1-U15 Data Latency : 61.5ns
U1-U17 Data Latency : 62.4ns
U1-U19 Data Latency : 61.0ns
U1-U21 Data Latency : 61.5ns
U1-U23 Data Latency : 61.3ns
U3-U5 Data Latency : 24.1ns
U3-U7 Data Latency : 23.6ns
U3-U9 Data Latency : 24.2ns
U3-U11 Data Latency : 25.6ns
U3-U13 Data Latency : 62.3ns
U3-U15 Data Latency : 60.9ns
U3-U17 Data Latency : 62.3ns
U3-U19 Data Latency : 61.5ns
U3-U21 Data Latency : 62.0ns
U3-U23 Data Latency : 62.0ns
U5-U7 Data Latency : 23.9ns
U5-U9 Data Latency : 25.9ns
U5-U11 Data Latency : 25.3ns
U5-U13 Data Latency : 62.8ns
U5-U15 Data Latency : 61.3ns
U5-U17 Data Latency : 62.5ns
U5-U19 Data Latency : 61.5ns
U5-U21 Data Latency : 62.2ns
U5-U23 Data Latency : 62.0ns
U7-U9 Data Latency : 25.3ns
U7-U11 Data Latency : 26.7ns
U7-U13 Data Latency : 61.9ns
U7-U15 Data Latency : 61.1ns
U7-U17 Data Latency : 62.4ns
U7-U19 Data Latency : 62.2ns
U7-U21 Data Latency : 62.5ns
U7-U23 Data Latency : 62.2ns
U9-U11 Data Latency : 27.2ns
U9-U13 Data Latency : 62.2ns
U9-U15 Data Latency : 62.2ns
U9-U17 Data Latency : 62.5ns
U9-U19 Data Latency : 62.3ns
U9-U21 Data Latency : 63.4ns
U9-U23 Data Latency : 63.0ns
U11-U13 Data Latency : 62.4ns
U11-U15 Data Latency : 61.9ns
U11-U17 Data Latency : 61.9ns
U11-U19 Data Latency : 62.1ns
U11-U21 Data Latency : 63.3ns
U11-U23 Data Latency : 62.9ns
U13-U15 Data Latency : 25.0ns
U13-U17 Data Latency : 26.8ns
U13-U19 Data Latency : 24.5ns
U13-U21 Data Latency : 26.1ns
U13-U23 Data Latency : 24.7ns
U15-U17 Data Latency : 24.5ns
U15-U19 Data Latency : 23.9ns
U15-U21 Data Latency : 24.6ns
U15-U23 Data Latency : 25.9ns
U17-U19 Data Latency : 24.3ns
U17-U21 Data Latency : 26.3ns
U17-U23 Data Latency : 25.7ns
U19-U21 Data Latency : 25.8ns
U19-U23 Data Latency : 27.1ns
U21-U23 Data Latency : 28.2ns
1x 64bytes Blocks Bandwidth : 14.72GB/s
4x 64bytes Blocks Bandwidth : 23GB/s
4x 256bytes Blocks Bandwidth : 87GB/s
4x 1kB Blocks Bandwidth : 260.08GB/s
4x 4kB Blocks Bandwidth : 355GB/s
16x 4kB Blocks Bandwidth : 471.34GB/s
4x 64kB Blocks Bandwidth : 640.32GB/s
16x 64kB Blocks Bandwidth : 311.6GB/s
8x 256kB Blocks Bandwidth : 315GB/s
4x 1MB Blocks Bandwidth : 309.69GB/s
8x 1MB Blocks Bandwidth : 47.73GB/s
8x 4MB Blocks Bandwidth : 18.75GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5900X 12-Core Processor (2M 12C 24T 3.7GHz, 12x 512kB L2, 2x 32MB L3)
Microcode
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
Platform Compliance : x64
Buffer Memory Accesses : No
No. Threads : 24
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5900X 12-Core Processor
URL : https://www.amd.com
Speed : 3.7GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 6 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
L1D (1st Level) Data Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 12x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)

Memory Controller


Thanks!


----------



## mongoled

Veii said:


> Interesting, it should be far slower tho beyond i think it was value 33 after when it switches to post, or 2T mode
> Need to find the bbs.naver links that visualize the range of SETUP timings (korean)


Obviously this is based on AMD following certain guidelines/specs with regards to DRAM access, though the results do not show that i.e. lesser performance



ManniX-ITA said:


> I can complete a single run of TM5 1usmus config in 6m:20s


FYI, the time it takes to complete the 1st TM5 run is not the same as the time it takes to complete the 25th TM5 run.

On each consecutive loop there is a small increase in the time it takes to complete the loop.

Results below are identical accept for the following

2T 3-3-15









1T 56-56-56









Using 1T 56-56-56 tPHYRDL value is auto adjusted to 28
Using 2T 3-3-15 tPHYRDL value is auto adjusted to 26


----------



## weleh

Yea I can run tRCD at 14 on my 3800 setup easy. Did the same for tRCD 13 at 3733.
This is at 4/4 RRDS/L and 16 tFAW and tRDRDSD 2.

This is straight 20 cycles of Anta's Extreme profile stable, hours and hours of AVX2 / SSE testing and obviously, gaming which is the primary stressor since that's all I do.

No idea where this flat 14's myth comes from but I've done it on 100€ boards and on more expensive boards with the same kit and difference CPUs (3600X and 5800X).

All of this at true 1T.


----------



## ManniX-ITA

The F4-3200C14D-32GTZSK kit was a sad failure... 
G.Skill updated the PCB; works same as my F4-4000C16.
From the visual inspection of the PCB around the heatsink seems it's indeed the same stuff less RGB.
Going to send it back...
Tried the same settings as Neody in the spreadsheet, he uses a Unify-X as well, and total failure.
Have to check on eBay for 2nd hand stuff...



weleh said:


> Yea I can run tRCD at 14 on my 3800 setup easy. Did the same for tRCD 13 at 3733.
> This is at 4/4 RRDS/L and 16 tFAW and tRDRDSD 2.


Interesting I'll check it out. Are you talking about a Dual Rank kit right?
But there are old Dual Rank kits like the above which doesn't need any special settings to run tRCDRD at 14.
Same settings doesn't work for the new ones.

Can you post a Zentimings screenshot?



lmfodor said:


> Are good for 5900x? what should I consider about all this information?


You should compare against another 5900x or just against your own previous results.
I think what seems off is the 12.8ns same core latency. I could go down to 9.3ns, seems strange.

Found out I left the cTDP/PPT value at 1000W in the BIOS settings fir the last Sandra result.
Seems all the mid data sizes are cached in L3 while the lower and higher not.



mongoled said:


> FYI, the time it takes to complete the 1st TM5 run is not the same as the time it takes to complete the 25th TM5 run.
> 
> On each consecutive loop there is a small increase in the time it takes to complete the loop.


Thanks, didn't noticed!
Always made a straight math 



mongoled said:


> Using 1T 56-56-56 tPHYRDL value is auto adjusted to 28
> Using 2T 3-3-15 tPHYRDL value is auto adjusted to 26


Interesting, seems to be a tad faster than 2T.
But I guess the 2T can be optimized much more than the 1T.


----------



## jomama22

ManniX-ITA said:


> The F4-3200C14D-32GTZSK kit was a sad failure...
> G.Skill updated the PCB; works same as my F4-4000C16.
> From the visual inspection of the PCB around the heatsink seems it's indeed the same stuff less RGB.
> Going to send it back...
> Tried the same settings as Neody in the spreadsheet, he uses a Unify-X as well, and total failure.
> Have to check on eBay for 2nd hand stuff...
> 
> 
> 
> Interesting I'll check it out. Are you talking about a Dual Rank kit right?
> But there are old Dual Rank kits like the above which doesn't need any special settings to run tRCDRD at 14.
> Same settings doesn't work for the new ones.
> 
> Can you post a Zentimings screenshot?
> 
> 
> 
> You should compare against another 5900x or just against your own previous results.
> I think what seems off is the 12.8ns same core latency. I could go down to 9.3ns, seems strange.
> 
> Found out I left the cTDP/PPT value at 1000W in the BIOS settings fir the last Sandra result.
> Seems all the mid data sizes are cached in L3 while the lower and higher not.
> 
> 
> 
> Thanks, didn't noticed!
> Always made a straight math
> 
> 
> 
> Interesting, seems to be a tad faster than 2T.
> But I guess the 2T can be optimized much more than the 1T.


I imagine you are using your powerplan for the Sandra runs? The ultimate performance one?


----------



## lmfodor

ManniX-ITA said:


> You should compare against another 5900x or just against your own previous results.
> I think what seems off is the 12.8ns same core latency. I could go down to 9.3ns, seems strange.
> 
> Found out I left the cTDP/PPT value at 1000W in the BIOS settings fir the last Sandra result.
> Seems all the mid data sizes are cached in L3 while the lower and higher not.


Yes, I see there’s much difference with the 5950 in terms of ns.. I have set the cTDP and Power Package Limit to 400, and my actual PBO manual settings are 220/175/300. Should I increase cTDP and PPL to 1000? Maybe the 5900 isn’t so good in comparison with the 5950x or the silicon lottery 

Thanks Mannix



Sent from my iPhone using Tapatalk Pro


----------



## jomama22

ManniX-ITA said:


> The 1T profile shows the muscles in Sandra and by a big margin.
> Between 100-150 GB/s improvement in transfers with data chunks between 16x 4kB and 4x 1024kB.
> 
> @Veii look at this beautiful graph, this is with min processor state 100%
> 
> View attachment 2488526
> 
> 
> 
> Spoiler: Aggregated results
> 
> 
> 
> 
> View attachment 2488527
> 
> 
> 
> 
> 
> 
> Spoiler: Bench results
> 
> 
> 
> 
> 
> 
> Code:
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Inter-Core Bandwidth : 168.48GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Inter-Core Latency : 44.1ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Inter-Core Bandwidth : 5.26GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Speed
> Inter-Core Bandwidth : 50.74MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Inter-Core Latency : 0.13ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-U2 Data Latency : 24.8ns
> U0-U4 Data Latency : 26.3ns
> U0-U6 Data Latency : 24.6ns
> U0-U8 Data Latency : 26.0ns
> U0-U10 Data Latency : 24.9ns
> U0-U12 Data Latency : 26.0ns
> U0-U14 Data Latency : 25.4ns
> U0-U16 Data Latency : 61.7ns
> U0-U18 Data Latency : 61.1ns
> U0-U20 Data Latency : 62.6ns
> U0-U22 Data Latency : 62.1ns
> U0-U24 Data Latency : 61.6ns
> U0-U26 Data Latency : 60.9ns
> U0-U28 Data Latency : 61.6ns
> U0-U30 Data Latency : 61.2ns
> U0-U1 Data Latency : 12.8ns
> U0-U3 Data Latency : 24.9ns
> U0-U5 Data Latency : 26.1ns
> U0-U7 Data Latency : 24.6ns
> U0-U9 Data Latency : 26.0ns
> U0-U11 Data Latency : 25.0ns
> U0-U13 Data Latency : 26.1ns
> U0-U15 Data Latency : 25.4ns
> U0-U17 Data Latency : 61.6ns
> U0-U19 Data Latency : 61.0ns
> U0-U21 Data Latency : 62.3ns
> U0-U23 Data Latency : 61.4ns
> U0-U25 Data Latency : 61.3ns
> U0-U27 Data Latency : 61.4ns
> U0-U29 Data Latency : 61.5ns
> U0-U31 Data Latency : 61.4ns
> U2-U4 Data Latency : 24.8ns
> U2-U6 Data Latency : 24.4ns
> U2-U8 Data Latency : 27.5ns
> U2-U10 Data Latency : 25.5ns
> U2-U12 Data Latency : 25.0ns
> U2-U14 Data Latency : 26.6ns
> U2-U16 Data Latency : 60.2ns
> U2-U18 Data Latency : 60.8ns
> U2-U20 Data Latency : 61.7ns
> U2-U22 Data Latency : 61.0ns
> U2-U24 Data Latency : 60.8ns
> U2-U26 Data Latency : 60.7ns
> U2-U28 Data Latency : 61.5ns
> U2-U30 Data Latency : 61.4ns
> U2-U1 Data Latency : 24.9ns
> U2-U3 Data Latency : 12.6ns
> U2-U5 Data Latency : 24.6ns
> U2-U7 Data Latency : 24.1ns
> U2-U9 Data Latency : 24.9ns
> U2-U11 Data Latency : 25.8ns
> U2-U13 Data Latency : 24.8ns
> U2-U15 Data Latency : 26.8ns
> U2-U17 Data Latency : 61.0ns
> U2-U19 Data Latency : 60.8ns
> U2-U21 Data Latency : 61.6ns
> U2-U23 Data Latency : 61.2ns
> U2-U25 Data Latency : 61.1ns
> U2-U27 Data Latency : 61.4ns
> U2-U29 Data Latency : 61.9ns
> U2-U31 Data Latency : 61.5ns
> U4-U6 Data Latency : 24.9ns
> U4-U8 Data Latency : 26.1ns
> U4-U10 Data Latency : 25.4ns
> U4-U12 Data Latency : 26.5ns
> U4-U14 Data Latency : 26.7ns
> U4-U16 Data Latency : 62.5ns
> U4-U18 Data Latency : 61.9ns
> U4-U20 Data Latency : 62.7ns
> U4-U22 Data Latency : 61.1ns
> U4-U24 Data Latency : 61.6ns
> U4-U26 Data Latency : 62.0ns
> U4-U28 Data Latency : 62.6ns
> U4-U30 Data Latency : 62.5ns
> U4-U1 Data Latency : 26.6ns
> U4-U3 Data Latency : 24.6ns
> U4-U5 Data Latency : 13.1ns
> U4-U7 Data Latency : 24.8ns
> U4-U9 Data Latency : 25.8ns
> U4-U11 Data Latency : 25.3ns
> U4-U13 Data Latency : 26.4ns
> U4-U15 Data Latency : 26.5ns
> U4-U17 Data Latency : 62.0ns
> U4-U19 Data Latency : 61.7ns
> U4-U21 Data Latency : 62.3ns
> U4-U23 Data Latency : 62.1ns
> U4-U25 Data Latency : 62.8ns
> U4-U27 Data Latency : 62.5ns
> U4-U29 Data Latency : 62.2ns
> U4-U31 Data Latency : 62.1ns
> U6-U8 Data Latency : 25.2ns
> U6-U10 Data Latency : 26.8ns
> U6-U12 Data Latency : 26.4ns
> U6-U14 Data Latency : 27.7ns
> U6-U16 Data Latency : 60.7ns
> U6-U18 Data Latency : 61.2ns
> U6-U20 Data Latency : 62.5ns
> U6-U22 Data Latency : 62.1ns
> U6-U24 Data Latency : 62.0ns
> U6-U26 Data Latency : 62.4ns
> U6-U28 Data Latency : 62.6ns
> U6-U30 Data Latency : 62.4ns
> U6-U1 Data Latency : 24.8ns
> U6-U3 Data Latency : 24.3ns
> U6-U5 Data Latency : 24.6ns
> U6-U7 Data Latency : 12.8ns
> U6-U9 Data Latency : 24.9ns
> U6-U11 Data Latency : 26.5ns
> U6-U13 Data Latency : 26.4ns
> U6-U15 Data Latency : 27.6ns
> U6-U17 Data Latency : 61.6ns
> U6-U19 Data Latency : 61.1ns
> U6-U21 Data Latency : 62.5ns
> U6-U23 Data Latency : 61.9ns
> U6-U25 Data Latency : 61.9ns
> U6-U27 Data Latency : 62.3ns
> U6-U29 Data Latency : 62.8ns
> U6-U31 Data Latency : 62.2ns
> U8-U10 Data Latency : 26.5ns
> U8-U12 Data Latency : 26.9ns
> U8-U14 Data Latency : 27.6ns
> U8-U16 Data Latency : 61.4ns
> U8-U18 Data Latency : 60.9ns
> U8-U20 Data Latency : 61.9ns
> U8-U22 Data Latency : 61.5ns
> U8-U24 Data Latency : 61.6ns
> U8-U26 Data Latency : 61.9ns
> U8-U28 Data Latency : 63.2ns
> U8-U30 Data Latency : 62.2ns
> U8-U1 Data Latency : 26.0ns
> U8-U3 Data Latency : 23.9ns
> U8-U5 Data Latency : 26.1ns
> U8-U7 Data Latency : 25.1ns
> U8-U9 Data Latency : 12.5ns
> U8-U11 Data Latency : 26.0ns
> U8-U13 Data Latency : 26.9ns
> U8-U15 Data Latency : 27.7ns
> U8-U17 Data Latency : 61.6ns
> U8-U19 Data Latency : 60.7ns
> U8-U21 Data Latency : 62.4ns
> U8-U23 Data Latency : 61.9ns
> U8-U25 Data Latency : 61.2ns
> U8-U27 Data Latency : 61.4ns
> U8-U29 Data Latency : 61.4ns
> U8-U31 Data Latency : 62.7ns
> U10-U12 Data Latency : 27.4ns
> U10-U14 Data Latency : 28.0ns
> U10-U16 Data Latency : 61.3ns
> U10-U18 Data Latency : 61.0ns
> U10-U20 Data Latency : 61.9ns
> U10-U22 Data Latency : 63.3ns
> U10-U24 Data Latency : 61.7ns
> U10-U26 Data Latency : 60.6ns
> U10-U28 Data Latency : 62.6ns
> U10-U30 Data Latency : 62.0ns
> U10-U1 Data Latency : 24.5ns
> U10-U3 Data Latency : 26.6ns
> U10-U5 Data Latency : 25.2ns
> U10-U7 Data Latency : 27.5ns
> U10-U9 Data Latency : 26.1ns
> U10-U11 Data Latency : 13.0ns
> U10-U13 Data Latency : 27.1ns
> U10-U15 Data Latency : 27.8ns
> U10-U17 Data Latency : 60.8ns
> U10-U19 Data Latency : 61.0ns
> U10-U21 Data Latency : 62.4ns
> U10-U23 Data Latency : 61.8ns
> U10-U25 Data Latency : 61.2ns
> U10-U27 Data Latency : 62.6ns
> U10-U29 Data Latency : 62.7ns
> U10-U31 Data Latency : 63.1ns
> U12-U14 Data Latency : 28.9ns
> U12-U16 Data Latency : 61.2ns
> U12-U18 Data Latency : 61.1ns
> U12-U20 Data Latency : 61.9ns
> U12-U22 Data Latency : 61.6ns
> U12-U24 Data Latency : 61.8ns
> U12-U26 Data Latency : 62.8ns
> U12-U28 Data Latency : 61.6ns
> U12-U30 Data Latency : 62.2ns
> U12-U1 Data Latency : 25.8ns
> U12-U3 Data Latency : 24.9ns
> U12-U5 Data Latency : 26.2ns
> U12-U7 Data Latency : 26.0ns
> U12-U9 Data Latency : 27.6ns
> U12-U11 Data Latency : 27.7ns
> U12-U13 Data Latency : 12.9ns
> U12-U15 Data Latency : 28.6ns
> U12-U17 Data Latency : 61.4ns
> U12-U19 Data Latency : 61.8ns
> U12-U21 Data Latency : 61.4ns
> U12-U23 Data Latency : 62.6ns
> U12-U25 Data Latency : 62.4ns
> U12-U27 Data Latency : 63.0ns
> U12-U29 Data Latency : 63.2ns
> U12-U31 Data Latency : 62.5ns
> U14-U16 Data Latency : 60.4ns
> U14-U18 Data Latency : 60.7ns
> U14-U20 Data Latency : 60.6ns
> U14-U22 Data Latency : 61.7ns
> U14-U24 Data Latency : 61.5ns
> U14-U26 Data Latency : 61.9ns
> U14-U28 Data Latency : 62.8ns
> U14-U30 Data Latency : 62.3ns
> U14-U1 Data Latency : 25.5ns
> U14-U3 Data Latency : 25.4ns
> U14-U5 Data Latency : 25.5ns
> U14-U7 Data Latency : 26.3ns
> U14-U9 Data Latency : 26.2ns
> U14-U11 Data Latency : 28.4ns
> U14-U13 Data Latency : 28.7ns
> U14-U15 Data Latency : 13.0ns
> U14-U17 Data Latency : 60.0ns
> U14-U19 Data Latency : 60.8ns
> U14-U21 Data Latency : 62.3ns
> U14-U23 Data Latency : 62.3ns
> U14-U25 Data Latency : 63.0ns
> U14-U27 Data Latency : 62.3ns
> U14-U29 Data Latency : 62.2ns
> U14-U31 Data Latency : 64.0ns
> U16-U18 Data Latency : 24.8ns
> U16-U20 Data Latency : 26.0ns
> U16-U22 Data Latency : 24.2ns
> U16-U24 Data Latency : 25.2ns
> U16-U26 Data Latency : 25.0ns
> U16-U28 Data Latency : 26.6ns
> U16-U30 Data Latency : 26.4ns
> U16-U1 Data Latency : 62.9ns
> U16-U3 Data Latency : 61.4ns
> U16-U5 Data Latency : 61.8ns
> U16-U7 Data Latency : 61.0ns
> U16-U9 Data Latency : 59.1ns
> U16-U11 Data Latency : 60.1ns
> U16-U13 Data Latency : 60.9ns
> U16-U15 Data Latency : 60.9ns
> U16-U17 Data Latency : 13.2ns
> U16-U19 Data Latency : 24.4ns
> U16-U21 Data Latency : 25.0ns
> U16-U23 Data Latency : 24.9ns
> U16-U25 Data Latency : 24.6ns
> U16-U27 Data Latency : 25.6ns
> U16-U29 Data Latency : 26.2ns
> U16-U31 Data Latency : 25.9ns
> U18-U20 Data Latency : 25.3ns
> U18-U22 Data Latency : 25.5ns
> U18-U24 Data Latency : 25.0ns
> U18-U26 Data Latency : 27.1ns
> U18-U28 Data Latency : 25.7ns
> U18-U30 Data Latency : 25.8ns
> U18-U1 Data Latency : 61.2ns
> U18-U3 Data Latency : 60.0ns
> U18-U5 Data Latency : 61.2ns
> U18-U7 Data Latency : 61.3ns
> U18-U9 Data Latency : 58.6ns
> U18-U11 Data Latency : 61.1ns
> U18-U13 Data Latency : 60.4ns
> U18-U15 Data Latency : 59.7ns
> U18-U17 Data Latency : 23.7ns
> U18-U19 Data Latency : 12.8ns
> U18-U21 Data Latency : 25.3ns
> U18-U23 Data Latency : 24.8ns
> U18-U25 Data Latency : 25.2ns
> U18-U27 Data Latency : 26.0ns
> U18-U29 Data Latency : 25.7ns
> U18-U31 Data Latency : 27.0ns
> U20-U22 Data Latency : 25.6ns
> U20-U24 Data Latency : 25.8ns
> U20-U26 Data Latency : 25.7ns
> U20-U28 Data Latency : 27.3ns
> U20-U30 Data Latency : 26.8ns
> U20-U1 Data Latency : 59.1ns
> U20-U3 Data Latency : 62.3ns
> U20-U5 Data Latency : 62.5ns
> U20-U7 Data Latency : 60.9ns
> U20-U9 Data Latency : 62.2ns
> U20-U11 Data Latency : 59.9ns
> U20-U13 Data Latency : 62.5ns
> U20-U15 Data Latency : 62.4ns
> U20-U17 Data Latency : 26.0ns
> U20-U19 Data Latency : 24.1ns
> U20-U21 Data Latency : 13.4ns
> U20-U23 Data Latency : 25.5ns
> U20-U25 Data Latency : 26.5ns
> U20-U27 Data Latency : 25.8ns
> U20-U29 Data Latency : 26.8ns
> U20-U31 Data Latency : 27.2ns
> U22-U24 Data Latency : 25.9ns
> U22-U26 Data Latency : 27.3ns
> U22-U28 Data Latency : 26.9ns
> U22-U30 Data Latency : 28.2ns
> U22-U1 Data Latency : 62.0ns
> U22-U3 Data Latency : 62.0ns
> U22-U5 Data Latency : 60.4ns
> U22-U7 Data Latency : 62.0ns
> U22-U9 Data Latency : 61.5ns
> U22-U11 Data Latency : 62.6ns
> U22-U13 Data Latency : 62.4ns
> U22-U15 Data Latency : 61.9ns
> U22-U17 Data Latency : 24.3ns
> U22-U19 Data Latency : 26.9ns
> U22-U21 Data Latency : 25.3ns
> U22-U23 Data Latency : 13.4ns
> U22-U25 Data Latency : 25.4ns
> U22-U27 Data Latency : 26.0ns
> U22-U29 Data Latency : 26.6ns
> U22-U31 Data Latency : 27.3ns
> U24-U26 Data Latency : 27.7ns
> U24-U28 Data Latency : 29.3ns
> U24-U30 Data Latency : 26.9ns
> U24-U1 Data Latency : 59.4ns
> U24-U3 Data Latency : 62.3ns
> U24-U5 Data Latency : 61.3ns
> U24-U7 Data Latency : 60.8ns
> U24-U9 Data Latency : 59.8ns
> U24-U11 Data Latency : 59.8ns
> U24-U13 Data Latency : 61.0ns
> U24-U15 Data Latency : 62.2ns
> U24-U17 Data Latency : 26.6ns
> U24-U19 Data Latency : 25.2ns
> U24-U21 Data Latency : 26.3ns
> U24-U23 Data Latency : 25.7ns
> U24-U25 Data Latency : 13.1ns
> U24-U27 Data Latency : 27.0ns
> U24-U29 Data Latency : 27.7ns
> U24-U31 Data Latency : 28.5ns
> U26-U28 Data Latency : 28.5ns
> U26-U30 Data Latency : 29.4ns
> U26-U1 Data Latency : 62.5ns
> U26-U3 Data Latency : 62.2ns
> U26-U5 Data Latency : 61.7ns
> U26-U7 Data Latency : 61.7ns
> U26-U9 Data Latency : 61.9ns
> U26-U11 Data Latency : 61.3ns
> U26-U13 Data Latency : 62.9ns
> U26-U15 Data Latency : 62.7ns
> U26-U17 Data Latency : 25.1ns
> U26-U19 Data Latency : 25.8ns
> U26-U21 Data Latency : 25.6ns
> U26-U23 Data Latency : 27.6ns
> U26-U25 Data Latency : 27.5ns
> U26-U27 Data Latency : 13.4ns
> U26-U29 Data Latency : 28.1ns
> U26-U31 Data Latency : 27.5ns
> U28-U30 Data Latency : 29.8ns
> U28-U1 Data Latency : 62.4ns
> U28-U3 Data Latency : 61.3ns
> U28-U5 Data Latency : 62.4ns
> U28-U7 Data Latency : 62.2ns
> U28-U9 Data Latency : 62.2ns
> U28-U11 Data Latency : 63.0ns
> U28-U13 Data Latency : 63.7ns
> U28-U15 Data Latency : 62.2ns
> U28-U17 Data Latency : 26.1ns
> U28-U19 Data Latency : 26.0ns
> U28-U21 Data Latency : 28.4ns
> U28-U23 Data Latency : 27.3ns
> U28-U25 Data Latency : 26.7ns
> U28-U27 Data Latency : 26.7ns
> U28-U29 Data Latency : 13.4ns
> U28-U31 Data Latency : 29.7ns
> U30-U1 Data Latency : 60.6ns
> U30-U3 Data Latency : 61.8ns
> U30-U5 Data Latency : 62.4ns
> U30-U7 Data Latency : 62.3ns
> U30-U9 Data Latency : 61.5ns
> U30-U11 Data Latency : 61.8ns
> U30-U13 Data Latency : 63.7ns
> U30-U15 Data Latency : 62.6ns
> U30-U17 Data Latency : 26.1ns
> U30-U19 Data Latency : 27.1ns
> U30-U21 Data Latency : 26.8ns
> U30-U23 Data Latency : 27.4ns
> U30-U25 Data Latency : 28.1ns
> U30-U27 Data Latency : 29.5ns
> U30-U29 Data Latency : 29.2ns
> U30-U31 Data Latency : 13.4ns
> U1-U3 Data Latency : 23.1ns
> U1-U5 Data Latency : 25.0ns
> U1-U7 Data Latency : 24.8ns
> U1-U9 Data Latency : 25.8ns
> U1-U11 Data Latency : 25.1ns
> U1-U13 Data Latency : 24.5ns
> U1-U15 Data Latency : 26.0ns
> U1-U17 Data Latency : 60.8ns
> U1-U19 Data Latency : 61.4ns
> U1-U21 Data Latency : 62.2ns
> U1-U23 Data Latency : 61.5ns
> U1-U25 Data Latency : 58.9ns
> U1-U27 Data Latency : 62.0ns
> U1-U29 Data Latency : 61.0ns
> U1-U31 Data Latency : 62.5ns
> U3-U5 Data Latency : 24.1ns
> U3-U7 Data Latency : 26.1ns
> U3-U9 Data Latency : 24.0ns
> U3-U11 Data Latency : 26.4ns
> U3-U13 Data Latency : 24.8ns
> U3-U15 Data Latency : 25.8ns
> U3-U17 Data Latency : 62.5ns
> U3-U19 Data Latency : 57.2ns
> U3-U21 Data Latency : 60.1ns
> U3-U23 Data Latency : 62.3ns
> U3-U25 Data Latency : 60.5ns
> U3-U27 Data Latency : 61.8ns
> U3-U29 Data Latency : 61.2ns
> U3-U31 Data Latency : 62.3ns
> U5-U7 Data Latency : 24.3ns
> U5-U9 Data Latency : 27.1ns
> U5-U11 Data Latency : 25.3ns
> U5-U13 Data Latency : 27.7ns
> U5-U15 Data Latency : 25.8ns
> U5-U17 Data Latency : 58.9ns
> U5-U19 Data Latency : 59.9ns
> U5-U21 Data Latency : 62.8ns
> U5-U23 Data Latency : 60.3ns
> U5-U25 Data Latency : 60.0ns
> U5-U27 Data Latency : 61.7ns
> U5-U29 Data Latency : 61.7ns
> U5-U31 Data Latency : 62.3ns
> U7-U9 Data Latency : 25.0ns
> U7-U11 Data Latency : 27.1ns
> U7-U13 Data Latency : 26.3ns
> U7-U15 Data Latency : 28.0ns
> U7-U17 Data Latency : 59.8ns
> U7-U19 Data Latency : 61.1ns
> U7-U21 Data Latency : 60.5ns
> U7-U23 Data Latency : 62.2ns
> U7-U25 Data Latency : 61.9ns
> U7-U27 Data Latency : 63.4ns
> U7-U29 Data Latency : 61.3ns
> U7-U31 Data Latency : 62.0ns
> U9-U11 Data Latency : 26.1ns
> U9-U13 Data Latency : 26.0ns
> U9-U15 Data Latency : 26.3ns
> U9-U17 Data Latency : 61.2ns
> U9-U19 Data Latency : 60.8ns
> U9-U21 Data Latency : 61.5ns
> U9-U23 Data Latency : 62.9ns
> U9-U25 Data Latency : 62.1ns
> U9-U27 Data Latency : 62.7ns
> U9-U29 Data Latency : 63.3ns
> U9-U31 Data Latency : 60.4ns
> U11-U13 Data Latency : 28.5ns
> U11-U15 Data Latency : 28.9ns
> U11-U17 Data Latency : 60.7ns
> U11-U19 Data Latency : 62.1ns
> U11-U21 Data Latency : 63.7ns
> U11-U23 Data Latency : 60.4ns
> U11-U25 Data Latency : 61.4ns
> U11-U27 Data Latency : 62.3ns
> U11-U29 Data Latency : 62.7ns
> U11-U31 Data Latency : 63.5ns
> U13-U15 Data Latency : 27.0ns
> U13-U17 Data Latency : 61.0ns
> U13-U19 Data Latency : 63.4ns
> U13-U21 Data Latency : 62.2ns
> U13-U23 Data Latency : 62.0ns
> U13-U25 Data Latency : 62.1ns
> U13-U27 Data Latency : 62.0ns
> U13-U29 Data Latency : 62.1ns
> U13-U31 Data Latency : 63.0ns
> U15-U17 Data Latency : 62.1ns
> U15-U19 Data Latency : 61.3ns
> U15-U21 Data Latency : 63.2ns
> U15-U23 Data Latency : 63.2ns
> U15-U25 Data Latency : 62.2ns
> U15-U27 Data Latency : 61.7ns
> U15-U29 Data Latency : 62.8ns
> U15-U31 Data Latency : 61.9ns
> U17-U19 Data Latency : 23.9ns
> U17-U21 Data Latency : 25.6ns
> U17-U23 Data Latency : 24.8ns
> U17-U25 Data Latency : 26.3ns
> U17-U27 Data Latency : 25.4ns
> U17-U29 Data Latency : 26.8ns
> U17-U31 Data Latency : 25.7ns
> U19-U21 Data Latency : 25.9ns
> U19-U23 Data Latency : 25.5ns
> U19-U25 Data Latency : 24.9ns
> U19-U27 Data Latency : 29.2ns
> U19-U29 Data Latency : 25.8ns
> U19-U31 Data Latency : 26.4ns
> U21-U23 Data Latency : 25.0ns
> U21-U25 Data Latency : 27.5ns
> U21-U27 Data Latency : 25.8ns
> U21-U29 Data Latency : 27.3ns
> U21-U31 Data Latency : 27.2ns
> U23-U25 Data Latency : 25.8ns
> U23-U27 Data Latency : 27.6ns
> U23-U29 Data Latency : 26.6ns
> U23-U31 Data Latency : 27.5ns
> U25-U27 Data Latency : 27.0ns
> U25-U29 Data Latency : 27.0ns
> U25-U31 Data Latency : 28.6ns
> U27-U29 Data Latency : 28.9ns
> U27-U31 Data Latency : 27.6ns
> U29-U31 Data Latency : 29.8ns
> 1x 64bytes Blocks Bandwidth : 25.15GB/s
> 4x 64bytes Blocks Bandwidth : 22.74GB/s
> 4x 256bytes Blocks Bandwidth : 96.64GB/s
> 4x 1024bytes Blocks Bandwidth : 290GB/s
> 4x 4kB Blocks Bandwidth : 440.15GB/s
> 16x 4kB Blocks Bandwidth : 588.34GB/s
> 4x 64kB Blocks Bandwidth : 809.62GB/s
> 16x 64kB Blocks Bandwidth : 576.7GB/s
> 8x 256kB Blocks Bandwidth : 572.08GB/s
> 4x 1024kB Blocks Bandwidth : 581.87GB/s
> 8x 1024kB Blocks Bandwidth : 40.93GB/s
> 8x 4MB Blocks Bandwidth : 19.82GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (16C 32T 3.4GHz, 16x 512kB L2, 2x 32MB L3)
> Microcode
> Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
> Platform Compliance : x64
> Buffering Used : No
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> Speed : 3.4GHz
> Cores per Processor : 16 Unit(s)
> Cores per Compute Unit : 2 Unit(s)
> Front Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)


Looking at your post here from a week ago, you have the same core to core latency as @lmfodor so I would be curious as to what exactly is different between the two runs.

Looking at your other Sandra benches seems to show the same, a 12.x ns core to core with average overall of 43-44ns.

So whatever settings you changed to achieve as much would be interesting to know. Wonder if you could repeat the result as well.


----------



## weleh

I already posted my setup either here or on Unify X thread.


----------



## craxton

Ive noticed that on the Zen3 ram sheet, that other users are
(5600X) using under 1.2 SocV with 2x8 4x8 sticks. to where as well, im still running 1.2v SOC

if i lower this to 1.8v SOC i notice instability.

is the SOC limit based solely on the limits of ones chip or "lottery" luck of the draw?
is there a way one can lower SOC voltage?



Spoiler



my chip in CTR is a platinum overclocker and platinum undervolter "says the program"
but i myself dont use it as well, im quite unsure how its supposed to used properly.

and im still yet figuring out what PPT, EDC, TDC limits are best for my chip while
maintaining my CO offset, and allowing PBO to boost to 4.85 all core/threads.


----------



## jomama22

craxton said:


> Ive noticed that on the Zen3 ram sheet, that other users are
> (5600X) using under 1.2 SocV with 2x8 4x8 sticks. to where as well, im still running 1.2v SOC
> 
> if i lower this to 1.8v SOC i notice instability.
> 
> is the SOC limit based solely on the limits of ones chip or "lottery" luck of the draw?
> is there a way one can lower SOC voltage?
> 
> 
> 
> Spoiler
> 
> 
> 
> my chip in CTR is a platinum overclocker and platinum undervolter "says the program"
> but i myself dont use it as well, im quite unsure how its supposed to used properly.
> 
> and im still yet figuring out what PPT, EDC, TDC limits are best for my chip while
> maintaining my CO offset, and allowing PBO to boost to 4.85 all core/threads.


Just ignore whatever ctr says your chip is, It's genuinely unimportant. Also, that has no say as to the quality of your I/o die anyway.

And yes, soc voltage boils down to a mix of I/o die lottery and what stress you're putting it under (fclk, memory timings/clk etc).


----------



## craxton

jomama22 said:


> what stress you're putting it under

















this about sums it up lol....4x8 SR with (moddest timings id say) scores say enough i suspect

CO/PBO -25 all core, +75mv offset...

was stated sometime ago, that 1.2 was safe enough to not degrade "to fast"
hope that still stands at this time.



Spoiler



NOTE tRDWR 10 makes instability/stutters, where as 11 shows no issues thats why
the ruleset isnt so much applied here.



appreciate the response tho. but, i must say, i can (no co) undervolt my chip to -7xxxmv


----------



## jomama22

craxton said:


> View attachment 2489394
> View attachment 2489395
> 
> 
> this about sums it up lol....4x8 SR with (moddest timings id say) scores say enough i suspect
> 
> CO/PBO -25 all core, +75mv offset...
> 
> was stated sometime ago, that 1.2 was safe enough to not degrade "to fast"
> hope that still stands at this time.
> 
> 
> 
> Spoiler
> 
> 
> 
> NOTE tRDWR 10 makes instability/stutters, where as 11 shows no issues thats why
> the ruleset isnt so much applied here.
> 
> 
> 
> appreciate the response tho. but, i must say, i can (no co) undervolt my chip to -7xxxmv


Are you talking about just offset negative voltage with pbo and not using CO? Just fyi, you will induce clock stretching doing this and probably have reduced performance. It's better to use CO if you are trying to undervolt.

Also, 1.2v is fine. The issue comes in with reduced PBO performance from doing so.

Edit: sorry, just put the top and bottom of your post together.

Do a test for yourself, try and run without that positive voltage offset doing any r20 test that is 2 threads or larger. Would be interesting to see what happens. You probably get a single thread boost from the positive offset but am interested in how it affects your multi core scores.


----------



## weleh

Adding any kind of positive offset destroys PBO performance for me. 
And yea, higher VSOC = less boosting.


----------



## craxton

jomama22 said:


> Are you talking about just offset negative voltage with pbo and not using CO? Just fyi, you will induce clock stretching doing this and probably have reduced performance. It's better to use CO if you are trying to undervolt.
> 
> Also, 1.2v is fine. The issue comes in with reduced PBO performance from doing so.
> 
> Edit: sorry, just put the top and bottom of your post together.
> 
> Do a test for yourself, try and run without that positive voltage offset doing any r20 test that is 2 threads or larger. Would be interesting to see what happens. You probably get a single thread boost from the positive offset but am interested in how it affects your multi core scores.


yes thats what im talking about, and nope didnt have any stretching actually.... actually scored what i should on cb23 and 20 
with just a simple offset to voltage.


----------



## jomama22

craxton said:


> yes thats what im talking about, and nope didnt have any stretching actually.... actually scored what i should on cb23 and 20
> with just a simple offset to voltage.


I am wondering if your positive offset with CO and negative offset without CO are what's actually scoring the same. What about if you just do CO, no offset and compare that to the others? I can see how on air cooling they would all be kinda similar though, not sure what you're using.

Don't test single thread. Just do all core only.


----------



## ManniX-ITA

jomama22 said:


> I imagine you are using your powerplan for the Sandra runs? The ultimate performance one?


Yes indeed



jomama22 said:


> Looking at your post here from a week ago, you have the same core to core latency as @lmfodor so I would be curious as to what exactly is different between the two runs.
> 
> Looking at your other Sandra benches seems to show the same, a 12.x ns core to core with average overall of 43-44ns.
> 
> So whatever settings you changed to achieve as much would be interesting to know. Wonder if you could repeat the result as well.


Let me check my posts 
The bandwidth for sure is the PPT/cTDP in CBS menu, not sure the latency.



weleh said:


> I already posted my setup either here or on Unify X thread.


Sorry, I thought it was a new one!



craxton said:


> if i lower this to 1.8v SOC i notice instability.
> 
> is the SOC limit based solely on the limits of ones chip or "lottery" luck of the draw?
> is there a way one can lower SOC voltage?


I can only think about stronger LLC and PWM Switching Frequency.
If you want to stress PBO and CO you need to support both for the CPU and SOC with generous settings.
I have Level 3 and 1000 kHz on both with the Unify-X.
Lower than that either is unstable or the motherboard shuts off when loading Windows.
But that's because it's a 5950x, the 5600x should be less needy.



jomama22 said:


> Just ignore whatever ctr says your chip is, It's genuinely unimportant


It's a "formula" that uses the lowest voltage that was achievable and the ACPI CPPC quality tags.
A wild guess, plus both are variable. So yes it's quite unimportant


----------



## ManniX-ITA

jomama22 said:


> Looking at your other Sandra benches seems to show the same, a 12.x ns core to core with average overall of 43-44ns.


From my posts I see only one using the new Sandra version.
The others you have seen are probably with the older version with the Multicore Efficiency test, this one is "new" and called Processor Inter-Thread Efficiency...


----------



## jomama22

ManniX-ITA said:


> From my posts I see only one using the new Sandra version.
> The others you have seen are probably with the older version with the Multicore Efficiency test, this one is "new" and called Processor Inter-Thread Efficiency...


It's still the same benchmark, tests and results. The results have just been relabeled to better show their differences. So the results still stand for both.

So just rerun the test and see the results. Just curious as to what may have changed or if it was just a fluke.

This much is said in their release notes. You can even compare the actual core latencies output to tell as much.

"Inter thread" in this case just refers to, for example, U0-U1. "Inter core" refers to U0-U2, "inter module" refers to U0-U16 (going between ccx's).


----------



## craxton

ManniX-ITA said:


> I have Level 3 and 1000 kHz on both with the Unify-X.


yeah, i kinda have around similar things...
although ive now (since the screenshots) switched to 800khz soc switching freq as well

and i no longer use llc3 for SOC im now using llc5 as 3/4 both push near 1.25/1.28 at max
which id prefer not to happen.....this is the MSI b550 Gaming Edge board btw.

















now one last question, WHICH of these CPU NB SOC or SoC (SVI2) voltages do i follow for whats ACTUALLY being pushed thru SOC???


----------



## KedarWolf

jomama22 said:


> Are you talking about just offset negative voltage with pbo and not using CO? Just fyi, you will induce clock stretching doing this and probably have reduced performance. It's better to use CO if you are trying to undervolt.
> 
> Also, 1.2v is fine. The issue comes in with reduced PBO performance from doing so.
> 
> Edit: sorry, just put the top and bottom of your post together.
> 
> Do a test for yourself, try and run without that positive voltage offset doing any r20 test that is 2 threads or larger. Would be interesting to see what happens. You probably get a single thread boost from the positive offset but am interested in how it affects your multi core scores.


I scored 100 points higher on R20 multicore with a -.0625 offset on CPU voltage and it still passes OCCT Extreme preset, TM5 and Core Cycler.


----------



## ManniX-ITA

jomama22 said:


> It's still the same benchmark, tests and results. The results have just been relabeled to better show their differences. So the results still stand for both.
> 
> So just rerun the test and see the results. Just curious as to what may have changed or if it was just a fluke.
> 
> This much is said in their release notes. You can even compare the actual core latencies output to tell as much.
> 
> "Inter thread" in this case just refers to, for example, U0-U1. "Inter core" refers to U0-U2, "inter module" refers to U0-U16 (going between ccx's).


That's total BS, I wonder if they know what they are doing 
As you can see all my previous results have been ditched, if they were comparable they'll be there.

I recall now crystal clear; saw Kedar result with that low latency.
Run on mine, much higher latency.
Checked the detailed results and noticed the labels were different, noticed the name of the test was different.
Installed the new version, rebooted, completely different results.
Low latency similar to Kerdar's.
Also the bandwidth can't be compared 1:1.

I'll run again the test later or tomorrow, I have to reboot to the bench install.


----------



## craxton

KedarWolf said:


> I scored 100 points higher on R20 multicore with a -.0625 offset on CPU voltage


i scored around 270 more in R20 than with just plain auto voltage. my offset was one step higher than yours tho.



KedarWolf said:


> passes OCCT Extreme preset, TM5 and Core Cycler.


i as well passed all stress tests, as i was running this offset when i first started testing my 
ram being stable.


----------



## GribblyStick

So finally started looking into CO and of course I have clock stretching, but I noticed something weird. HWINFO reported a max EDC of 220.
That has to be a bug then right? I did get values all throughout that were slightly higher too, like 201 and change.


Spoiler: 220 EDC + settings



reading from a run of R23










and the settings on google drive
in short :
5900x on custom water loop, Crosshair 8 hero wifi
PPT/TDC/EDC: 175/145/400
CO all core NEGATIVE 30
cTDP/Packlacge power limit : 400
Boost override:150
vcore offset: 0,050 POSITIVE

BIOS 3302 / SMU 56.46.0

note that I didn't "arrive" at these values, I simply picked that as an arbitrary starting point from various replies/threads.


----------



## craxton

First one is with CO -26 with .6xxmv offset









this ones with -75mv no CO. (scores still suggest no clock stretching, as my scores still beat most ive seen on reddit.)
usually around 4490 but, i couldnt get a few services to stay down. and im not disabling those anymore
since my last encounter with power plans COMPLETLY bugging out to where they didnt stay set, swapped back and fourth
and cpu usage pegged at 100% although nothing showing usage...


----------



## jomama22

ManniX-ITA said:


> That's total BS, I wonder if they know what they are doing
> As you can see all my previous results have been ditched, if they were comparable they'll be there.
> 
> I recall now crystal clear; saw Kedar result with that low latency.
> Run on mine, much higher latency.
> Checked the detailed results and noticed the labels were different, noticed the name of the test was different.
> Installed the new version, rebooted, completely different results.
> Low latency similar to Kerdar's.
> Also the bandwidth can't be compared 1:1.
> 
> I'll run again the test later or tomorrow, I have to reboot to the bench install.


I see now! Thought the march 4th update was the newest where they had mentioned those changes. 

So that's the issue here. The march 4th update includes the new naming within the benchmark but hasn't updated the actual bench yet. The April 13th update actually includes the new one.

Thanks sisoft


----------



## jomama22

craxton said:


> First one is with CO -26 with .6xxmv offset
> View attachment 2489423
> 
> 
> this ones with -75mv no CO. (scores still suggest no clock stretching, as my scores still beat most ive seen on reddit.)
> usually around 4490 but, i couldnt get a few services to stay down. and im not disabling those anymore
> since my last encounter with power plans COMPLETLY bugging out to where they didnt stay set, swapped back and fourth
> and cpu usage pegged at 100% although nothing showing usage...
> View attachment 2489424


Yeah I would expect the CO + v offset to beat out a plain v offset. 

Was more curious what just a plain CO would do for you. Should be able to just max it out at -30 considering the stability of CO + v offset working.

Curious what you have your llc set to.


----------



## jomama22

ManniX-ITA said:


> That's total BS, I wonder if they know what they are doing
> As you can see all my previous results have been ditched, if they were comparable they'll be there.
> 
> I recall now crystal clear; saw Kedar result with that low latency.
> Run on mine, much higher latency.
> Checked the detailed results and noticed the labels were different, noticed the name of the test was different.
> Installed the new version, rebooted, completely different results.
> Low latency similar to Kerdar's.
> Also the bandwidth can't be compared 1:1.
> 
> I'll run again the test later or tomorrow, I have to reboot to the bench install.


Here are my results first run with the april 14th version:










Spoiler: results



SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 192.83GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.5ns (9.2ns - 59.4ns)
Inter-Thread (same Core) Latency : 9.5ns
Inter-Core (same Module) Latency : 20.1ns
Inter-Module (same Package) Latency : 58.5ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 6GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1880.50MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.76ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 38.91MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31 
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.7ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 20.0ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.7ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 20.1ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 21.2ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.5ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.4ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 55.6ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 55.4ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 55.8ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 58.8ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.1ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 58.2ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.6ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.8ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.3ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 20.2ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.0ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.7ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 20.3ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 19.9ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 19.5ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 19.4ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 58.3ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 58.4ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 58.8ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 58.9ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.1ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 58.3ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.6ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.8ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 20.8ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 21.3ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.9ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.6ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 19.6ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 19.9ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 58.8ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 58.5ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 58.8ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 58.4ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 58.1ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 58.3ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.8ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.4ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 20.2ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.5ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 20.6ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 21.3ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 19.9ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.6ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 19.6ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 19.9ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 58.9ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 58.6ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.9ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 58.4ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 58.1ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 58.2ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.9ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.4ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 20.7ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 21.0ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 19.9ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 20.5ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 19.8ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 59.1ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.7ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 59.2ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 59.3ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 58.7ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 59.1ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.2ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 59.1ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 21.2ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.7ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.5ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 20.6ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 21.0ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 19.8ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 20.5ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 19.9ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 59.0ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 58.8ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 59.4ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 59.4ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 58.7ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 59.1ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.0ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 59.4ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 19.8ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.2ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 20.0ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 20.6ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.5ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 58.4ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 59.3ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.8ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.8ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.5ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 59.1ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 58.7ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 20.7ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 21.3ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 20.5ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.6ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 19.9ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.2ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 20.0ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 20.7ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.6ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 58.4ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 59.2ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.7ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.8ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.4ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 59.1ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.7ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 18.9ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 19.6ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 19.0ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.9ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.8ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.4ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.4ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 57.6ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.3ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.4ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.0ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.3ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.9ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.9ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 19.8ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.4ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 18.9ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 19.6ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 19.1ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.9ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.8ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.5ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.3ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 57.7ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.2ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.5ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 57.9ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 19.7ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 19.8ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.2ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.0ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 59.0ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 58.0ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.0ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.0ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.5ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.2ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.0ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.5ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 19.7ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.2ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 18.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.5ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 19.2ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 20.0ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.1ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 58.0ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 59.0ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 58.0ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 57.9ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.1ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.5ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.2ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 18.8ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.2ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.2ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.6ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.5ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 58.0ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 58.3ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 58.5ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 58.4ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 19.5ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 19.6ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 20.3ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.0ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 19.6ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 19.3ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.2ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 18.9ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.2ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.2ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.6ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.5ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 58.0ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 58.3ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 58.6ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 58.4ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.2ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.1ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.9ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.2ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 58.2ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.1ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 58.8ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 58.3ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 19.5ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 19.9ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 19.7ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 20.7ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 19.1ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 19.8ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 18.8ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.4ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.4ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.3ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.8ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.2ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 58.3ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.1ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 58.7ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 58.3ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 20.0ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 21.3ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 20.4ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.6ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.0ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 20.0ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 19.4ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 58.5ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 58.8ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 58.4ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 58.6ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.9ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.1ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.1ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.3ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.4ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 20.0ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 21.4ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 20.4ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.6ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.0ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 20.0ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 19.4ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 20.6ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 21.0ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.9ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.6ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 19.7ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 19.7ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 58.7ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 58.7ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 58.3ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 58.3ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.8ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 58.0ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.3ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.1ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 20.0ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.4ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 20.6ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 21.0ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.9ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.6ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 19.7ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 19.7ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 20.4ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.3ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 19.8ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 20.7ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.0ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 58.8ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 58.9ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 58.8ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 59.3ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 58.6ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 59.1ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.6ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.8ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 21.3ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 20.7ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.6ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 20.4ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.2ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 19.8ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 20.7ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.0ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 19.7ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.2ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 19.9ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.4ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 58.8ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 58.5ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 59.0ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 58.7ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.4ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 58.0ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.5ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.2ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 20.4ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 21.0ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 20.6ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.4ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 19.7ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.2ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 19.9ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.5ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 19.1ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 20.0ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 19.3ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.1ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.2ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.2ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.6ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 57.7ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.2ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 58.0ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 58.3ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 20.6ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 20.0ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.2ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 19.8ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.5ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 19.1ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 20.0ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 19.3ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 19.8ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 20.0ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 58.3ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.1ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.6ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.5ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.2ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.0ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.3ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.1ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.0ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 19.8ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.2ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 19.1ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.5ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 19.5ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 20.0ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 19.1ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.7ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.9ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.9ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.6ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.4ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 58.4ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 58.7ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 20.1ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 19.7ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 20.7ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.0ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 20.0ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 19.4ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.6ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 19.5ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.9ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.4ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.9ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.0ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.1ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 58.3ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.2ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 19.4ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 19.7ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.0ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.4ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 19.2ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 20.0ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 19.0ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.4ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 20.2ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.9ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 20.7ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.3ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 19.9ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 19.5ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 19.4ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 58.4ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 58.5ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 58.9ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 58.8ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 58.0ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 58.2ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.6ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.7ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.6ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 21.3ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.6ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 19.6ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 19.9ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 58.8ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 58.5ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.9ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 58.4ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 58.1ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.2ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.9ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.5ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 20.5ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 20.9ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 19.7ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 20.3ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 19.7ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.5ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.2ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 58.7ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 58.8ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.2ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.5ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.7ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 19.9ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.2ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.0ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.6ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.5ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 58.4ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 59.2ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 58.8ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.7ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.4ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 59.0ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.8ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 18.9ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 19.6ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 19.1ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.9ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.9ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.4ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 58.3ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 57.7ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.2ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.6ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 57.9ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 19.8ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 19.8ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 58.1ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.9ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 58.9ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 58.0ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.0ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.0ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.4ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.2ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 18.8ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.1ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 58.1ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.6ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.5ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 58.0ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 58.3ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 58.5ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 58.6ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.3ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.2ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.9ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.1ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 58.2ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.0ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 58.9ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 58.3ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 20.0ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 21.3ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 20.4ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.6ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.0ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 20.0ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 19.4ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 20.7ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 21.0ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.9ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.6ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 19.7ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 19.7ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 20.4ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.2ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 19.8ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 20.7ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.0ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 19.7ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.2ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 19.9ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 20.4ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 19.1ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 20.0ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 19.3ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 20.0ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 20.2ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 19.1ns
1x 64bytes Blocks Bandwidth : 27.3GB/s
4x 64bytes Blocks Bandwidth : 27.15GB/s
4x 256bytes Blocks Bandwidth : 109GB/s
4x 1kB Blocks Bandwidth : 348.55GB/s
4x 4kB Blocks Bandwidth : 533.68GB/s
16x 4kB Blocks Bandwidth : 728GB/s
4x 64kB Blocks Bandwidth : 1TB/s
16x 64kB Blocks Bandwidth : 787.8GB/s
8x 256kB Blocks Bandwidth : 751GB/s
4x 1MB Blocks Bandwidth : 749.12GB/s
16x 1MB Blocks Bandwidth : 24.88GB/s
8x 4MB Blocks Bandwidth : 20.66GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5.08GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII DARK HERO)
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 5.08GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5.08GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## craxton

jomama22 said:


> Curious what you have your llc set to.


i shared my LLC settings a moment ago to manna i believe it was in the thread here.



jomama22 said:


> plain CO would do for you


i whished it would. but it doesnt, itll run, but if i persay, open ALL launchers ffor games that i have
would crash the pc. (thats epic, steam, GOG, ubisoft etc.)



jomama22 said:


> max it out at -30 considering the stability of CO + v offset working


-26 is as high as i can go. although i have a percore conig with (amd voltage control) no offset
that works dam good too.


----------



## ManniX-ITA

craxton said:


> now one last question, WHICH of these CPU NB SOC or SoC (SVI2) voltages do i follow for whats ACTUALLY being pushed thru SOC???


The SVI2 is what is running inside the IOD, the CPU NB SOC is what the motherboard is feeding



craxton said:


> and i no longer use llc3 for SOC im now using llc5 as 3/4 both push near 1.25/1.28 at max
> which id prefer not to happen.....this is the MSI b550 Gaming Edge board btw.


You sure you can't set the voltage lower and raise the LLC higher?
In my experience is the best for stability.
You have Auto for CPU, maybe that's the cause for your instability.
I'd try fixed at 3 or 4 and lower VSOC

Ghost CPU usage in Windows should be fixed with this update:


Microsoft Update Catalog



You can try my custom power plan:








Ryzen Custom Power Plans for Windows 10/11 (Snappy...


CPUDoc now features a custom dynamic power plan with ultra low power in standby: https://github.com/mann1x/CPUDoc/releases/latest These are the custom power plans I've made for my 5950x. I have tested them as well on a 3800X and 5600G (not very thoroughly). They should not interfere with PBO...




www.overclock.net







jomama22 said:


> Here are my results first run with the april 14th version:


Gorgeous


----------



## craxton

@jomama22









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


what stress you're putting it under this about sums it up lol....4x8 SR with (moddest timings id say) scores say enough i suspect CO/PBO -25 all core, +75mv offset... was stated sometime ago, that 1.2 was safe enough to not degrade "to fast" hope that still stands at this time...




www.overclock.net





scroll up a tad...
also, (edit) i cant run CO with anything above 12 all core without offset to core voltage and not crash.
may run CB fine, but eventually will WHEA BSOD out and restart. 



ManniX-ITA said:


> You sure you can't set the voltage lower and raise the LLC higher


havent tried honestly, but since its being spoke of ill give it a shot tonight as work resumes tomorrow.



ManniX-ITA said:


> You have Auto for CPU, maybe that's the cause for your instability.
> I'd try fixed at 3 or 4 and lower VSOC


yes, ive ran auto LLC on cpu since the start unless manual cpu overclocking. didnt know i could run LLC
properly with AUTO/PBO/CO with LLC modes on the CPU side of things and it not create problems.

i ran llc3 on SoC since day 1 of getting stable. since then i was able to drop -1 (one click down with + or - that is)
dont know the proper stepping off hand. while running llc3 with what my SoC is now, i get spikes within ranges of
1.28V on SOC voltage.... this is why i dropped to 4 to allow a slight droop instead of flat. or raising when under load.



ManniX-ITA said:


> The SVI2 is what is running inside the IOD, the CPU NB SOC is what the motherboard is feeding


thank you, now i know which is actually going thru the chip.


----------



## kompira

mongoled said:


> ...
> Using 1T 56-56-56 tPHYRDL value is auto adjusted to 28
> Using 2T 3-3-15 tPHYRDL value is auto adjusted to 26


In theory AddrCmdSetup should arrive after CsOdtSetup/CkeSetup, therefore the last two may remain 0 and only AddrCmdSetup between 50 and 63. You can try Setup 56-0-0 with CAD BUS X-20-24-24. My observations show that this is better:







For example, most Asus boards lock AddrCmdSetup at 61 when we have Zen1 / +, ie. setup times are 61-0-0. For comparison Gigabyte puts 11 by default, but I can change it.
Higher AddrCmdSetup helps for lower ProcODT/ClkDrvStr. But we need to find the right settings with which we have no loss of performance.


----------



## TimeDrapery

In an attempt to DTRT I read through and followed the guide on determining appropriate resistances found a page or two back (How to do Stable DDR4 Tuning on Ryzen: Finding the Appropriate Values of the Termination Resistance (Rev. 2))

Here are my results for ProcODT... What are your thoughts?


----------



## craxton

@ManniX-ITA thank you for those suggestions on LLC for CPU and NB

i managed to lower to 1.17 SOC voltage while keeping stability (52.3ns) since i reenabled most services etc.
and since enabling windows "insider" build latency has went up from 51.9 to 52.3
killing other services etc yields 51.9 but thats alot of services to kill when theyre needed for windows not to 
throw a fit on me and scream warnings etc. (not whea)

if one boots in "safe boot" mode if WHEA (other than ID 20 when one crashes) were actually present
they would theoretically show themselves would they not??

the only way i get ANY WHEA at all, is when messing with CO and i crash the system....
so im yet again curious to if somethings actually not quite right with my OS
even if i DID reinstall on an entire new drive as well as new partitions and boot sectors etc.


----------



## ManniX-ITA

craxton said:


> if one boots in "safe boot" mode if WHEA (other than ID 20 when one crashes) were actually present
> they would theoretically show themselves would they not??


Not sure, I think WHEAs are not reported in safe mode
There's a possibility that the CPU doesn't get registered to send WHEA
But also that it's not sending them or that is not affected
Observing the system behavior and benchmark scores is the only way to tell
If at high FCLK you have moments of "loss of smoothness", like the mouse lagging, windows opening with latency, that's tons of WHEA in background
Hard to tell if they are rare
But then I guess if you don't see and don't observe it, you are enough free from it


----------



## Dar|{cyde

TimeDrapery said:


> In an attempt to DTRT I read through and followed the guide on determining appropriate resistances found a page or two back (How to do Stable DDR4 Tuning on Ryzen: Finding the Appropriate Values of the Termination Resistance (Rev. 2))


I spent a bit playing with this. Looks to me like you weren't quite unstable enough to tell any difference. (/edit Well OK at 1.29V you were plenty unstable, but the data still doesnt look that clear) The amount of errors can vary quite a bit, especially on the first loop. For some reason (probably temp) it fires a lot more errors on the 2nd loop. But it's not very consistent either, so you either need to average multiple runs, or only pay attention to large differences.

I was getting 0-12 on the first cycle, and 25-48 after 2 cycles. This is at 4000C14 at 1.56V. In the end, ProcODT 40 was the best for me, but not by a very large margin. I went up to 60 and couldn't tell much difference. 40 seemed the closest to what you might call a sweet spot.

Does your memtest86 take forever to load? Mine takes about 1:35 from selecting the USB in BIOS. I dunno what takes that thing so long to boot, it should load in about 1ms by the looks of things. I do prefer doing unstable memtests outside of windows, it would be nicer if it loaded quicker.


----------



## mongoled

kompira said:


> In theory AddrCmdSetup should arrive after CsOdtSetup/CkeSetup, therefore the last two may remain 0 and only AddrCmdSetup between 50 and 63. You can try Setup 56-0-0 with CAD BUS X-20-24-24. My observations show that this is better:
> View attachment 2489428
> 
> For example, most Asus boards lock AddrCmdSetup at 61 when we have Zen1 / +, ie. setup times are 61-0-0. For comparison Gigabyte puts 11 by default, but I can change it.
> Higher AddrCmdSetup helps for lower ProcODT/ClkDrvStr. But we need to find the right settings with which we have no loss of performance.


Thank you for this new information, I will have a look at this to see if there are any noticable performance differences


----------



## mongoled

weleh said:


> Yea I can run tRCD at 14 on my 3800 setup easy. Did the same for tRCD 13 at 3733.
> This is at 4/4 RRDS/L and 16 tFAW and tRDRDSD 2.
> 
> This is straight 20 cycles of Anta's Extreme profile stable, hours and hours of AVX2 / SSE testing and obviously, gaming which is the primary stressor since that's all I do.
> 
> No idea where this flat 14's myth comes from but I've done it on 100€ boards and on more expensive boards with the same kit and difference CPUs (3600X and 5800X).
> 
> All of this at true 1T.


You post has erked me!

At best its naive.

There is no "myth" regards flat 14s, there is only statistical data.

The statistical data we have seen shows that flat 14s at 3800/1900 is not a commonly achievable result.

Statistical data in this context is posts on the Internet at various forums, Reddit and other resources that clearly show this.

Be it 2 x 16GB, 2 x 8GB or 4 x 8GB, the number of people able to get stable flat 14s are very few, that you happen to have some modules that can do it does not mean all module can do this!

So your "no idea" where the myth comes from is just ugh.


----------



## Dar|{cyde

mongoled said:


> You post has erked me!
> 
> At best its naive.
> 
> There is no "myth" regards flat 14s, there is only statistical data.
> 
> The statistical data we have seen shows that flat 14s at 3800/1900 is not a commonly achievable result.
> 
> Statistical data in this context is posts on the Internet at various forums, Reddit and other resources that clearly show this.
> 
> Be it 2 x 16GB, 2 x 8GB or 4 x 8GB, the number of people able to get stable flat 14s are very few, that you happen to have some modules that can do it does not mean all module can do this!
> 
> So your "no idea" where the myth comes from is just ugh.


I can run 3800 flat-14 no problem (32gb DR). Maybe its the Unify-X that helps. In fact, that's my fallback stable clock now, while I work on faster ones.


----------



## mongoled

Dar|{cyde said:


> I can run 3800 flat-14 no problem (32gb DR). Maybe its the Unify-X that helps. In fact, that's my fallback stable clock now, while I work on faster ones.


As I said, its far from common, obviously some people have managed to achieve this.

4 x 8GB is more difficult due to being in a position to find 4 modules that can handle the flat 14s, 2 x 16GB and 2 x 8GB are the most prevalent.

Ive been hoping that a "magic" setting combo will appear to allow more peeps to run flat 14s, as has happened with 1T/2T with the 56-56-56 discovery


----------



## ManniX-ITA

kompira said:


> In theory AddrCmdSetup should arrive after CsOdtSetup/CkeSetup, therefore the last two may remain 0 and only AddrCmdSetup between 50 and 63. You can try Setup 56-0-0 with CAD BUS X-20-24-24. My observations show that this is better:


Thanks, I'll check and report back.


----------



## ManniX-ITA

Dar|{cyde said:


> I can run 3800 flat-14 no problem (32gb DR). Maybe its the Unify-X that helps. In fact, that's my fallback stable clock now, while I work on faster ones.


What kit do you have?
Do you have pictures of the PCB?


----------



## weleh

mongoled said:


> You post has erked me!
> 
> At best its naive.
> 
> There is no "myth" regards flat 14s, there is only statistical data.
> 
> The statistical data we have seen shows that flat 14s at 3800/1900 is not a commonly achievable result.
> 
> Statistical data in this context is posts on the Internet at various forums, Reddit and other resources that clearly show this.
> 
> Be it 2 x 16GB, 2 x 8GB or 4 x 8GB, the number of people able to get stable flat 14s are very few, that you happen to have some modules that can do it does not mean all module can do this!
> 
> So your "no idea" where the myth comes from is just ugh.


I have my own statistical data.

Hundreds of people on oc discord that I've helped, hundreds of people from ones that I helped to others that helped me.
I have never seen anyone complain their kit can't do 14 RD, ever.

Now I don't want to discredit anyone's work here but I see too much theory being handed out and too few actually overclocking. 
People posting insane rules or exploits I've never ever heard about. Just look at the VSOC and VDDGs most people here run for 1900... My own values are good up to my boards/cpu max fCLK which is around 2200 synced. No need to go bajillion VSOC or VDDGs, absolutely 0 need.

My own rule is simple. When it comes to RAM timings, lower = better and the lower you can get everything the better. 

Sounds pretty simple. 4x8 or 2x16 makes it no different. Board is just an excuse too. Again I've done it on 100€ boards and 500€ boards. Same behaviour.


----------



## weleh

ManniX-ITA said:


> Not sure, I think WHEAs are not reported in safe mode
> There's a possibility that the CPU doesn't get registered to send WHEA
> But also that it's not sending them or that is not affected
> Observing the system behavior and benchmark scores is the only way to tell
> If at high FCLK you have moments of "loss of smoothness", like the mouse lagging, windows opening with latency, that's tons of WHEA in background
> Hard to tell if they are rare
> But then I guess if you don't see and don't observe it, you are enough free from it


It's more like the service that reports them isn't loaded.


----------



## ManniX-ITA

weleh said:


> It's more like the service that reports them isn't loaded.


WHEA is part of the kernel:








Components of the Windows Hardware Error Architecture - Windows drivers


Components of the Windows Hardware Error Architecture



docs.microsoft.com





There's a generic MS PSHED plugin which is reading from ACPI tables the CPU error sources.
Sometimes it doesn't read the tables properly and it doesn't register the source.
If it's not registered in the WHEA logs you'll see only 4 sources instead of 5; if that's the case the WHEA could happen and not being reported.
The sources can be registered/de-registered via WMI calls.



weleh said:


> I have my own statistical data.
> 
> Hundreds of people on oc discord that I've helped, hundreds of people from ones that I helped to others that helped me.
> I have never seen anyone complain their kit can't do 14 RD, ever.


Interesting to know but here the statistical data tells something different 
I'm one of the many that can't run tRCDRD at 14. Maybe it's possible scarifying other timings but that's not the goal.
From the community spreadsheet results it's clear only a few can run it that low with DR kits while most can with SR kits.
I bought the same kit 3200C14 and I have the same motherboard as Neody in the spreadsheet.
But mine can't run his settings, not even close.
I think cause the PCB has been updated and it behaves exactly like my 4000C16 kit.
Pity, I'll send it back.
Maybe older kits can run it easy and newer ones not, your experience may not include the new ones.



weleh said:


> People posting insane rules or exploits I've never ever heard about. Just look at the VSOC and VDDGs most people here run for 1900... My own values are good up to my boards/cpu max fCLK which is around 2200 synced. No need to go bajillion VSOC or VDDGs, absolutely 0 need.


I don't agree, it depends on the sample and also on what you do.
I could run low voltages on the 3800x and also on the 5950x, no problem.
Benchmark scores? Pitiful low.
Gaming? From lagging like hell to crashes.
If your goal is to browse the internet sure, there's no need 



weleh said:


> My own rule is simple. When it comes to RAM timings, lower = better and the lower you can get everything the better.


As demonstrated many times, look at the scores from @Veii in the spreadsheet, lower is not necessarily better.
Balanced timings can do same or better than all low.



weleh said:


> Sounds pretty simple. 4x8 or 2x16 makes it no different. Board is just an excuse too. Again I've done it on 100€ boards and 500€ boards. Same behaviour.


I don't agree the board matters.
My 380€ Aorus Master was a tragedy with RAM OC, the 280€ Unify-X is brilliant.
Maybe price doesn't matter but the board yes indeed!


----------



## weleh

RD is also VERY IMC dependent not just sticks.

It also scales with voltage so obviously it will also depend on what people are confortable dailying.

On my SR kit I can't run RD 14 at 1.5V at 3800 obviously but 100% my IMC can do it. There's a good prediction spreadsheet for tCL and RD on most bdie kits. Pretty useful and for me, it's been kind of consistent eventhough silicon luck matters too from ICs to IMC.

Regarding voltages again, for 1900 fCLK? On latest bios? One shouldn't even need to touch anything, it should be guaranteed. If you have to mess too much either you got shafted on your CPU or your board is absolutely dog... I had a B450 (130€) and a B550 Bazooka (100€) from MSI, it ran exactly the same settings as my Unify X on both my 3600X and 5800X. 1 in a 1000000 if it's actually coincidence.

Again my kit is not even special, it's a 3600 c16 bin, kind of average if I compare with most looser kits I've seen that can do lower tRFC for instance no problem.

I can't imagine a single scenario where 1.3VSOC is going to be needed, or 1.15VDGG IOD/CCD unless you're doing GB3 for records. In fact, from my own testing, doing crazy voltages just degrade integrity and performance. And 100% of the times they will result in instant WHEAs at high fCLK.

About Veii's results as I said, no discredit but I haven't even seen them and I bet you on extremely memory sensitive tasks, lower is better, 100%.
Besides, I hardly take what people post online too serious, people will do anything to look good regarding benchmarks and performance. For instance I don't have a bench OS, everything done on my daily OS. Yet some people will run safe mode or bench OS and claim "this is my result with CAM, Asus suite, hwinfo64 and a game running on the background"... 

Posting on a spreadsheet you can do 4500 synced WHEA free with some screenshots of benchmarks has it's own value but it shouldn't be taken as a fact. This is hipothetically speaking and not directed at anyone else.


----------



## mongoled

weleh said:


> On my SR kit I can't run RD 14 at 1.5V at 3800 obviously but 100% my IMC can do it.


Communication breakdown ?

Just to be clear, I myself am talking about straight 14s when running 3800 mhz, as I think are other people here who are talking about flat 14s.

You were saying you can run flat 14s and above you say that you cant run flat 14s at 3800 mhz.

Maybe this is the issue.

I can run flat 14s at 3733 mhz no problem, just not at 3800 mhz, which is where most of us "get stuck"

And this is not a new thing, this has been investigated by many people and over a number of years!

Thats why when you come here and use words such as "myth" and "easy" and that you have helped "hundreds on discord", there must be a communication breakdown ....


----------



## weleh

I'm talking flat 14's.
And I run 13 RD at 3733.

I used the word myth because clearly, it's possible. It's not a Zen IMC hard limitation like some thing.
Old screen that I already posted here.


----------



## weleh

More recent image here...


----------



## mongoled

You do realise that many of the issues peeps have is that by raising voltages over 1.55v we move into other factors effecting the overclockability of the dimms that is not to do with the actual memory modules but to do with the PCBs.

To be perfectly honest, if you had assisted so many hundreds of people in achieving flat 14s @ 3800 mhz, we would have heard about it, it would have broken the Internet

😂 😂

Its one thing getting your own modules to run flat 14s at 3800 with greater than 1.58v and another to get other hundreds of people to be willing to put such voltage through their memory modules!

And whats with the super low tRDRDSD-DD/tWRWRSD-DDs ? Are these a hack to get flat 14s stable ??


----------



## TimeDrapery

Dar|{cyde said:


> Spoiler
> 
> 
> 
> I spent a bit playing with this. Looks to me like you weren't quite unstable enough to tell any difference. (/edit Well OK at 1.29V you were plenty unstable, but the data still doesnt look that clear) The amount of errors can vary quite a bit, especially on the first loop. For some reason (probably temp) it fires a lot more errors on the 2nd loop. But it's not very consistent either, so you either need to average multiple runs, or only pay attention to large differences.
> 
> I was getting 0-12 on the first cycle, and 25-48 after 2 cycles. This is at 4000C14 at 1.56V. In the end, ProcODT 40 was the best for me, but not by a very large margin. I went up to 60 and couldn't tell much difference. 40 seemed the closest to what you might call a sweet spot.
> 
> Does your memtest86 take forever to load? Mine takes about 1:35 from selecting the USB in BIOS. I dunno what takes that thing so long to boot, it should load in about 1ms by the looks of things. I do prefer doing unstable memtests outside of windows, it would be nicer if it loaded quicker.



@Dar|{cyde 

That's what I was thinking as well

Yeah, it takes forever to load, lags badly, and is often unresponsive to input 😂😂😂😂😂

Not the easiest to work with but there's definitely a positive to not running tests in the OS

I collected a few PCB crashes during my last bit of overnight testing with TM5 so I'm looking to give it another go with different RTTs

The addition of the second 2 × 8GB kit looks like good stuff and I'm sure I'll have a better time once I get the hang of finding where it's stable


----------



## TimeDrapery

mongoled said:


> Spoiler
> 
> 
> 
> You do realise that many of the issues peeps have is that by raising voltages over 1.55v we move into other factors effecting the overclockability of the dimms that is not to do with the actual memory modules but to do with the PCBs.
> 
> To be perfectly honest, if you had assisted so many hundreds of people in achieving flat 14s @ 3800 mhz, we would have heard about it, it would have broken the Internet
> 
> 😂 😂
> 
> Its one thing getting your own modules to run flat 14s at 3800 with greater than 1.58v and another to get other hundreds of people to be willing to put such voltage through their memory modules!
> 
> And whats with the super low tRDRDSD-DD/tWRWRSD-DDs ? Are these a hack to get flat 14s stable ??



@mongoled

It's obvious he's a full-grown baby genius

You haven't heard of his great successes because he's NDA'd everyone he's helped on Discord

The super low tertiaries are a hack to let everyone know you've got no idea what you're talking about whilst claiming you know what you're talking about

Discord is a myth

*Edit*: I just realized he's got his own _statistical_ data... @weleh you should post this data so as to share it with the community and help everyone out


----------



## ManniX-ITA

@mongoled @TimeDrapery 
Let's keep mutual respect plz
Strong opinions and arguing are welcome but childish mocking it's not polite...

@Waleh 
What you posted is all about Single Rank DIMMs... 
We are speaking about Dual Rank having these issues (and not all)
The magic sauce for DR it's what we are going after


----------



## mongoled

ManniX-ITA said:


> @mongoled @TimeDrapery
> Let's keep mutual respect plz
> Strong opinions and arguing are welcome but childish mocking it's not polite...
> 
> @Waleh
> What you posted is all about Single Rank DIMMs...
> We are speaking about Dual Rank having these issues (and not all)
> The magic sauce for DR it's what we are going after


No mocking on my behalf, just gentle banter (my post history shows I've never mocked anyone) 

😊


----------



## ManniX-ITA

mongoled said:


> No mocking on my behalf, just gentle banter (my post history shows I've never mocked anyone)


You are the instigator, you broke my internet


----------



## mongoled

ManniX-ITA said:


> You are the instigator, you broke my internet


😄 😄 😄


----------



## TimeDrapery

ManniX-ITA said:


> Spoiler
> 
> 
> 
> @mongoled @TimeDrapery
> Let's keep mutual respect plz
> Strong opinions and arguing are welcome but childish mocking it's not polite...
> 
> @Waleh
> What you posted is all about Single Rank DIMMs...
> We are speaking about Dual Rank having these issues (and not all)
> The magic sauce for DR it's what we are going after



You're right, good looking out

Thanks for your help


----------



## Dar|{cyde

ManniX-ITA said:


> What kit do you have?
> Do you have pictures of the PCB?











I don't have pics of the board, Thaiphoon says they are B1, but general consensus seems to be that the LED boards are all B2 despite what thiaphoon says. It's just fast, expensive B-die, like everyone else is running.

Weleh is running SR, and seems to gloss over the difference with DR dimms. I'm not surprised that SR dimms have no issues with 1T, or tight timings. Driving DR is much harder, same as 4xSR sticks. The SR guys are forgetting (or they're pissed) that their sweet overclock doesn't enjoy the interleaving performance benefits that DR provides.

What I can't figure out, is why 1T can't give me lower AIDA latency than 2T. It gives a boost in bandwidth, but why would latency drop? Perhaps something to do with dual rank.


----------



## weleh

The fact that you guys are questioning about low terts just proves you really do not understand what they do to SR and DR kits.

In fact, I bet you aren't getting flat 14's because you're actually unstable somewhere else rather than your KIT/IMC not being able to do flat 14's.

And then, there's people claiming Ryzen IMC can't do lower than 7.5ns RD.

To finish my participation on this thread, resorting to insults hidden as "banter" just further proves why I never bothered to post on this thread at all.

👏


----------



## ManniX-ITA

Dar|{cyde said:


> What I can't figure out, is why 1T can't give me lower AIDA latency than 2T. It gives a boost in bandwidth, but why would latency drop? Perhaps something to do with dual rank.


Thanks, I'll check if I can replicate with my F4-4000C16 but I tried something very similar and it failed even with tRCDRD 15.
If it fails I'll try the Ripjaws F4-3600C14D-32GVK, similar but without the damn LEDs.
If those fails as well I'll try with your kit...


----------



## mongoled

Maybe something to do with the Teamgroup PCB that Weleh uses..?

I'm pretty sure my "good" set of Vipers will do flat 14s, but that would give me a total of 16GB.

And yup, 2 sticks of single rank easier than 2 sticks of dual rank or 4 single rank sticks is probably the hardest as you need to have 2 good kits to have any chance of tightening down.

Did not try these on B550 chipset, next time I have a build to make with B550 will give the 4xVipers a go

😊


----------



## ManniX-ITA

Dar|{cyde said:


> What I can't figure out, is why 1T can't give me lower AIDA latency than 2T. It gives a boost in bandwidth, but why would latency drop? Perhaps something to do with dual rank.


Same here but I thought it was because mine is 2CCD... my guess as well it has something to do with DR


----------



## mongoled

weleh said:


> The fact that you guys are questioning about low terts just proves you really do not understand what they do to SR and DR kits.
> 
> In fact, I bet you aren't getting flat 14's because you're actually unstable somewhere else rather than your KIT/IMC not being able to do flat 14's.
> 
> And then, there's people claiming Ryzen IMC can't do lower than 7.5ns RD.
> 
> To finish my participation on this thread, resorting to insults hidden as "banter" just further proves why I never bothered to post on this thread at all.
> 
> 👏


See there you go again. We are all here to help each other, alot of peeps have been tweaking mem modules for years, so to come here and tell people they don't know what they are doing, people who have given hours upon hours to this community, well of course you are not going to get a nice response

Then you go on to tell us about all the people you have helped etc etc without any real evidence. 

What did you expect? 

All info posted here is public anyone can go beck and see it. 

What's that famous quote? "Extraordinary results need extraordinary evidence" (sure someone can tell me the proper quote ) 

😁😁


----------



## Veii

mongoled said:


> @Veii 😂😂 couldn't keep away, happy you are posting 😊😊
> 
> 
> lmfodor said:
> 
> 
> 
> Hi Veii, how good it is to have you here again
Click to expand...

Don't get used to this 


jomama22 said:


> Also, what toggle are you speaking of in reference to the overboost issue?


Hidden by chipset drivers core suspension.
Forcefully by the bios C-States generation being disabled if you attempt to enable DF-States
Auto DF-States from Enabled , being disabled and an inner-core link speed "slowdown" to smooth boosting out (slower less snappy)
RyzenMaster pushing a telemetry fix + Core Remap for my/our frankenstein units and remapping the boosting Table via RSMU#
Couple of attempts to enforce disabled core hibernation to prevent overboosting , while they could've just put a hard-frequency limit on the powerplans & no one would notice or have random idle crashes


Dar|{cyde said:


> I've been struggling with y-cruncher reboots. 5600x on Unify-X, I thought it was my CO too low. It throws WHEA 18 on a seemingly random core each time. I've been raising my CO to compensate, but maybe it has nothing (or little) to do with the curve.
> 
> What CPU are you feeding those 900-1020-1100 values? Here's my current setup, TM5 error free.
> vDDP 0.900
> CCD 0.940
> IOD 1.060
> vSOC 1.100
> I'll try some higher CCD/IOD, see if it helps.


The same as yours, but maybe not fully the same
Go on ZenTimings on Debug and verify you have 1CCD and not by any chance two
I've seen 5800X users with 2 CCDs, two of them
They couldn't sustain normal OS stability, as the V/F curve was from a 5950X and the poor little CCD just crashed on it
Positive vcore offset and slightly backing down CO , fixed it
Poor little thing overvolted itself but on the lower frequency range "undervolted" and kept crashing

WHEA #18 to my and MSIs knowledge, is a lack of vcore. +5mV "should" fix it (on stock)
+15mV has no negative effects on stock, +20 already can cause clock stretching or jumping/falling to another frequency strap & losing perf
If you push IOD, push SOC up - 40mV stepping as the absolute minimum between VDDG and SOC
Between VDDP and VDDG CCD there doesn't have to be any difference, but it can be helpful to have at least somee , there
Between IOD and SOC, there must be one


FleischmannTV said:


> When you talk about disabling CPPC, do you mean entirely or just Preferred Cores?


He disabled the entire one, i think only preferred cores needs an adjustment, but it's strange that this is even a potential issue
Well it's DPC latency nitpicking at this point


lmfodor said:


> o there comes my first big question, as you say, how to stabilize not the voltage, but precisely the amperage and the resistances, more considering that we do not need as much voltage as is usually said, is it because our mems are dual Rank?


I'm sorry, i don't understand the issue
RTTs would be different between PCB layers or design of them
But the logic remains the same. Maaybe the need RTT_WR of /2 , but this one likes very strong RTT_PARK to function
And strong RTT_PARK is contra-productive
Haven't found a away to utilize it positive at /2 so far ~ /3 works equally well for both types of DIMMs. DR & SR

Min/Max try them - likely go with MIN first and see how much is at least required to keep up stability
Then adjust voltage up and see if you have to increase RTT_NOM
(likely no, only 1.56+ ~ rather 1.58+ need /6 instead of /7)
As you lower RTT_PARK, increase ClkDrvStr and try to lower procODT
procODT will be autocorrected, soo that's quite a few latency tests to do ~ in order to check for consistent results
You an continue to take this path indefinately, and increase voltage + lower/weaken RTT_PARK
Someday you'll hit enough voltage and then it's just a balance of tRRD + tWTR + tRDWR & SD,DDs
all of them increased and low primaries still have a big benefit , over lower teritiaries

tRCDRD always gives a big performance uplift, nevertheless how slow you have to make the rest
The tradeoff is worth it, but it takes a lot of time to get that one stable
Again 4200C15-15-15 = 3800C13-13-13 
If i can do it, everyone can with their better PCB


RonLazer said:


> I went through a process of testing tRCDRD 14 @3800MHz and I really do think it's impossible with the Zen3 IMC in the way you're thinking of. There is a maximum capacity for incoming data that any memory controller can handle at once, and past a certain set of timings you can overflow it. The Zen3 IMC seems to cap out at 7.5ns tRCDRD no matter what voltages, impedances, PCBs, or other timings you try - and it's consistent across the entire frequency range.


tRCD 15 on 4200 is 7.1429~~~
tRCD 14 on 4000 is 7ns flat
tRCD 13(.5) on 3800 is 6.8421~~~

I could run tRCD a flat 12-12-12 set on 3733 (6.4291...ns)
There is no IMC limit for me here
i do think the range is lower, but i take the fully stable approatch, not the suicide run approach
The lowest latency on Zen3 was 46.1ns @ 4000C14-14-14 flat with low tertiariers @ 5.1ghz


RonLazer said:


> ou'll notice that Veii uses much looser tRRDS/tRRDL than most users on here, which is a hit to bandwidth but will limit the frequency of these sorts of errors in synthetic tests. But real workloads are far more chaotic, less repetitive, and it's not worth the risk that you're rolling the dice on the right workload tripping up the IMC and crashing/corrupting data.


Which workload is more extreme than OCCT Extreme AVX2 , different y-cruncher AVX2 simulations, as well as P95 small FFT similar non AVX workloads

There is no place to doubtness on the results, they are stable and stay stable 
The reason tRRD got weaker, is to tame tRCD14 at this speed
Tested, they scall up till 4367MT/s, without voltage increase
It's a balancing issue - and only went higher on them to balance anything slower than my easy to run 16-16-16 set at 1.48v

The change on them also enforced a change on SD, DDs and they kept following my pattern of "what runs, don't touch"
Soo they where used also for tFAW 6-7 attempts
Please don't forget that i run an A0 PCB on a kit that cost me 80-90€
My PCB is the issue here, it's not the ICs on it
tRRD and tWTR are "post trasfer" timings, they nearly have nothing to do with the ICs and are mostly PCB related

It makes no sense for me to push them lower and increase strain + lose my low primaries as exchange
it makes sense to work them down after the stepup from 4133 to 4200 or from 16-16-16 flat to 15 flat
But that's a long ongoing procedur. These kits are being worken on each month since at least 12+ months , little by little every month
Last stepup was even reaching 4200MT/s on them and taming the near death of them at 1.55v
This has nothing to do with the ICs or the IMC, why the settings are set
It just doesn't run lower without this PCB giving up. But it can run lower if i find a good SD,DD combination that doesn't have to waste latency on tRDWR

I don't bench settings for benching, everything i use is what i daily & right now i can daily 1.66v (1.65v now) without problems
If it's not stable or performing badly, i won't bother with it
Please remember this. Beating my head against a wall till it works - no benchmark or save mode shenanigans
No benchmark OS, maybe slimmed down, but it remains my daily OS and daily system (single OS) + Game OS
I have nothing and waste my time / or would do it for personal fake enjoyment - to run XOC no one can replicate and no one has any benefit from it
Soo daily stable and nothing else, is what you get from me.
Unless stated that the shared picture is just experimental fooling around 
Anything else, again is a waste of my time and doesn't teach anyone anything ~ just wishful thinking & dreaming


RonLazer said:


> what is the best SMU version and what CBS settings do you recommend? I managed to boot 2100MHz FCLK on AGESA 1.1.9 (SMU 56.43 I believe?) but the memory performance totally falls apart in any benchmark and cranking up SOC/IOD/PLL voltages only helps up to a point, which is still much slower than 2000MHz at the same timings


Best for FCLK performance, AGESA 1.1.0.0 Patch A (SMU 56.30 - there you get a fully functional CO and ReBar)
Next best is 1.1.0.0 Patch D, where you get one cache limit lifted and a big boost, at the cost of increased (slowed down) GMI Link speed internally
Also slower access time and changed boosting curve because of the "activation" of dLDO_injector
(digital low dropout regulator and per-c state VID smoother)

I think SMU 56.44 was top (AGESA 1.2.0.0), except the usb issues if you connect something USB 2 and USB 3 on one set of USB3.0 ports
Which btw still has dropout issues on 1202 zZZ , but it's a fake 1202, it's just 56.50 which is 1201+
When i plug my mouse and my usb mic on the same XHCI connector, my mouse starts to stutter and droup out
I can use the Type-C port for the mic, and no other USB3.0 devices are affected that way


RonLazer said:


> but the memory performance totally falls apart in any benchmark and cranking up SOC/IOD/PLL voltages only helps up to a point, which is still much slower than 2000MHz at the same timings. What's weird is I can trick the FCLK into running the same frequency with a BCLK overclock and with enough PLL performance goes back to the expected value, so it does seem to be a hardcoded lock in the ABL related to the link-equalisation/CRC but I have no idea how to bypass it.


2133 is what does the same for me , 2200 is not bootable at all so far
but at least 2100 is stable and performing as stable
before 2100 was stable , but 2067 + BLCK OC made it "bypass" the performance loss and autocorrection

Working on VDDG and SOC was required. Also only one procODT out of 3 which post, will be beneficial and fine
2133 i still lose 1-2ns on it. Need to find another magical combination for it , but at least it doesn't throttle up to 60+ns
Just stays at 49.5 now, sometimes 50ns
Just it's not worth the strain and throttling, even when every test will pass, because build in autocorrection is fantastic at doing it's job 
48ns is what should be hit, but lower than 48.5 is not possible
Heh, it took a loong time - more than 6 weeks to bypass the 50ns wall (16 flat), which was also an EDC FUSE limit wall

Keep working on it, is all i can say
At least 50.1ns should be "easily" hittable on single CCD units @ 4200 16-16-16
And 16-16-16 "only" requires 1.48-1.49v max. At least the tWR 16 set i pushed once as "undervolt" set


TimeDrapery said:


> I realize now, after re-reading your reply, the ProcODT is too low for the now 4 × 8GB set


3 procODT ranges will work and perform nearly identical just with continues random spikes
only one of these 3 will be the correct consistent one
And you will need to figure it out again, if you change SOC voltage or change ClkDrvStr


TimeDrapery said:


> , would tCL being one value higher than what follows (for example, 15-14-14-28 or 32) be more effective? I've seen XMP profiles like this on B-die kits often... My TeamGroup 4000MT/s kit wants to run 18-20-20-40 on XMP but, being B-die, they're "supposed" to run flat primaries, right? Is this relevant?


Low tCL is a pure marketing term. Given more voltage, everything can run lower tCL, even HynixMFR can run CL14-19-x-x-x
G.Skill mostly does such thing, and it's more marketing behavior than anything else
Sure there is a scaled/timed benefit. But it's mostly marketing

As for "more effective", tCL will first fail if the supplied "minimum voltage" is too low
the voltage that is needed for tCL , should be also fine for tRCD - IF the set is fine and each of the 1 million cells can operate at this access time 
There comes IC quality into place, but stuff like tWR, tFAW, tRTP, tRRD & tWTR + tRDWR
are all "post" timings. They can help and you can balance stuff , but they mostly are PCB density, rank and revision related 
====================================
Now that i think about Ron's post
The only person that beats me memory stability wise (CPU Stability is very questionable , but hey 0c ambient - heh)
Is a 3800 tRCD 12 set, which is also a transfer-time of 6.3158ns
I purely out of results, can not relate to the mentioned 7.5ns value
Same as i do have couple of tRDWR 6, sets which break Ron's predicted/calculated -2 value as
"the minimum that can potentially boot or even be stable"
I break these rules, but he is over 80% accurate with the shared sheet.
Just wish that we would stop hiding under locked algorithms ~ this doesn't teach anyone anything and can even fool yourself when somebody like me, randomly breaks your calculated results with stable results 
It just hides the potential for issue finding, doing anything locked or close source. Sadly NDAs are a thing and it's the death for a teaching overclocker to sign these


----------



## Veii

GribblyStick said:


> So finally started looking into CO and of course I have clock stretching, but I noticed something weird. HWINFO reported a max EDC of 220.
> That has to be a bug then right? I did get values all throughout that were slightly higher too, like 201 and change.
> 
> 
> Spoiler: 220 EDC + settings
> 
> 
> 
> reading from a run of R23
> 
> View attachment 2489417
> 
> 
> and the settings on google drive
> in short :
> 5900x on custom water loop, Crosshair 8 hero wifi
> PPT/TDC/EDC: 175/145/400
> CO all core NEGATIVE 30
> cTDP/Packlacge power limit : 400
> Boost override:150
> vcore offset: 0,050 POSITIVE
> 
> BIOS 3302 / SMU 56.46.0
> 
> note that I didn't "arrive" at these values, I simply picked that as an arbitrary starting point from various replies/threads.


EDC FUSE Limit 
220 is an improvement, probably the board telemetry fakes
It was before 210, but it has to be 200A
Scroll couple of pages back, for the fuse limit writeup

Yet setting 400A does internally allow cache speed to be ramped up higher, but the allcore limit remains at the fuse limit
On which SOC and FCLK do take a cut out of the whole boosting powerbudget
Nothing except CTR can bypass this
Or maxing out the negative allcore-CO and compensating a bit with positive vcore offset

Negative offset doesn't bypass the Fuse limit as CO is a high value
Positive vcore does bypass it, as it takes CO into account - yet also takes SOC into account


craxton said:


> if one boots in "safe boot" mode if WHEA (other than ID 20 when one crashes) were actually present
> they would theoretically show themselves would they not??


Safe-mode misses WMI functionality, boosting and powerbudgeting functionality
Ethernet drivers (unless enabled), sound drivers, GPU drivers 
It's labled cheating for a a good reason, it won't report WHEA, shouldn't 
Half of the CPU functionality including CPPC doesn't function


----------



## TimeDrapery

Spoiler






weleh said:


> The fact that you guys are questioning about low terts just proves you really do not understand what they do to SR and DR kits.
> 
> In fact, I bet you aren't getting flat 14's because you're actually unstable somewhere else rather than your KIT/IMC not being able to do flat 14's.
> 
> And then, there's people claiming Ryzen IMC can't do lower than 7.5ns RD.
> 
> To finish my participation on this thread, resorting to insults hidden as "banter" just further proves why I never bothered to post on this thread at all.
> 
> 👏






@weleh 

Nobody is questioning how "terts" work there little dude, people are questioning how you think they work because yours are goofy... if it's SR, bottom em out at 1... if they're not SR then you're likely losing performance in doing so

I was not resorting to insults hidden as "banter", I was insulting you and I didn't continue insulting you because the gentleman @ManniX-ITA said to keep things civil and he's a knowledgeable, contributing member of this forum whom I appreciate

I don't like the way you talk... you're a know-it-all and, like many know-it-alls, you're unwilling to share what you think you actually do know because you're scared to have someone find out that you've ever been wrong about _anything ever_

Please do finish your participation in this thread (_now_) claphandsclaphandsclaphands


----------



## Senniha

CJR & Micron , fun

If Zentimings is right, then you overvolt cLDO_VDDP and VDDG CCD by a lot
Maybe you haven't seen this post








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net





RTT_WR /2 , i don't think any of the sets would require this.
RTT_PARK of /1 is too low, increase it please to at least /2 or even /3
Wasn't there a P6.63 out there finally ? i remember it was buggy before

Yea no RTT_PARK /2 should be better, but don't run /1
ClkDrvStr you want to push at 60
CsOdtDrvStr at 40
60-20-40-20 CAD_BUS, try this 
Maybe will need 120-20-30-24 on T-Topology, but first try couple of things
On a flat timings set, don't use Odd primaries and GDM on

RTT_NOM, depends
You should be passing just fine with /7,
But what you can also try is test booting without RTT_WR (disabled)
Soo something along the lines of 6/0/3 or 7/0/2
Just don't run /1 on the poor hynix 
Micron dimms would expect DynamicODT (RTT_WR) but your combination is strange

As for the order
Micron, Hynix, Micron, Hynix
try this if you haven't already

Can't help you with one answer only, it's too exotic and needs a lot of trial and error
Autocorrection from Vermeer, is throttling - get the voltages down first
procODT you want to move sub 40, likely 36-39ohm till 3600. Globally sub 40ohm

Positive vCore offset and maxed out negative CO (or in the range of 25+)
at 3800 and higher
(if you are a CTR user, don't use any positive vcore offset bellow RC04)
Positive vcore offset comes with strong vdroop LLC
It's only there to increase input current, as negative CO does take a cut on it
[/QUOTE]
@Veii its really pain to get even 3333 without WHEA i tried everything.on 3466 i got blues screens with your settings .Please check now in this phase what i can do?


----------



## danakin

hello everyone.

managed to get this:


















does someone know how i can decrease latency ? i tried 1TM but it makes latency 55,x

best regards and thanks for help,

pete


----------



## Dar|{cyde

danakin said:


> does someone know how i can decrease latency ? i tried 1TM but it makes latency 55,x
> 
> best regards and thanks for help,
> 
> pete


You could try dropping RFC a bit. Use the manual calculation on the spreadsheet, and drop RFC in increments of tRTP. I can run mine down to 123ns or so... any time I tried below that it was time to clear CMOS. So make sure your profile is saved. It runs pretty warm, a fan on the DIMMs helps.

If you are stable there at 1T, try switching to 2T. Leave everything else the same. Mine is faster on 2T. However you will lose a bit of bandwidth. You win some, you lose some.


----------



## craxton

ManniX-ITA said:


> The SVI2 is what is running inside the IOD, the CPU NB SOC is what the motherboard is feeding


ok, so the boards feeding now, 1.18 but the cpu is actually getting 1.15/16....LLC3 btw MSI LLC that is..



ManniX-ITA said:


> But then I guess if you don't see and don't observe it, you are enough free from it


if only i could accept this....last time i seen an actual WHEA error (other than forcing one out by messing with CO/Voltage/OC)
was in December (by this i mean errors other than id 20) to which i was running my 3600xt)



ManniX-ITA said:


> There's a generic MS PSHED plugin which is reading from ACPI tables the CPU error sources.
> Sometimes it doesn't read the tables properly and it doesn't register the source.


Is the plugin you mentioned a sure fire way to make WHEA 100% sure to work?

as stated, i have a few WHEA logs, but ALL are ID 20 as it happens only when 
my CO isnt stable and the pc crashes. not bsod persay just hardcrashes...



ManniX-ITA said:


> If it's not registered in the WHEA logs you'll see only 4 sources instead of 5


Something like this (being 5 sources?) inside operations???










ManniX-ITA said:


> The sources can be registered/de-registered via WMI calls.


By this i believe you simply mean restarting WMI services???
as WMI was the issue with my CPU 100% usage while nothing was showing
the cpu actually being used, and was the culprit making my power profile to hot swap 
by itself....

Reinstalling windows and EFI system partitions should (in theory) make (if any) WHEA pop about correct?
as thats what ive done to still not have any pop up, using Prime, OCCT, y-cruncher, HCI, TM5, geek bench, nothing makes one pop up.
except the mentioned above like ten times....


----------



## craxton

Veii said:


> Safe-mode misses WMI functionality, boosting and powerbudgeting functionality
> Ethernet drivers (unless enabled), sound drivers, GPU drivers
> It's labeled cheating for a a good reason, it won't report WHEA, shouldn't
> Half of the CPU functionality including CPPC doesn't function


thanks, hard noted and wont forget it this time around, as one other mentioned similar things 
a moment ago.

@weleh if you can do 3800 c14 FLAT with 4x8 then PLEASE 
POST? 
don't just make claims, and not show anything at all. we all share what we find. (some don't find anything)
just simply observe and use (these magic rulesets) which 100% work for the most part
to get the most from DR/4x8 SR kits. 

you simply cant just put "random" lower numbers in for your timings and they just <work>
i mean, yeah you might get lucky with 2x8 and make it happen. but considering most of what's shared here 
is proven data by DAYS/WEEKS/MONTHS of testing and learning the code AMD uses for AGESA with what's 
available inside the bios. (ABL) if you will, perhaps im not quite right on what its called, but someone will correct me.

Again, if you provide some data to show your claims, others may actually be able to use this and improve elsewhere.
(FYI) nobody here puts magical IOD, VDDG, CCD voltage in and gets somewhere. its called trial and error. 

In my near year of being here, If Veii has posted with it, then you can bet it to be 90% accurate, the other 10% is where chip limits and 
board limitations fall inline.


----------



## ManniX-ITA

craxton said:


> ok, so the boards feeding now, 1.18 but the cpu is actually getting 1.15/16....LLC3 btw MSI LLC that is..


I usually run it like this or a notch below.
Since you have an MSI you can cheat with telemetry:










The CPU VDD options have a much greater impact than I thought.
Much higher MT scores. Forgot at the time but that's how the Unify-X can compete with the Master.
Gigabyte is probably doing the same but under the hood; you will get a constant ghost EDC 50A consumption.
SOC Current at 1A will set your SOC power consumption at 0.2A something.
Unfortunately it doesn't mean you recover 20A from the power budget; Vermeer can't be cheated so easily.
But it's enough as a deception measure  You can recover 2A from the power budget which is not that bad, 60-90 points in CPU-z MT.



craxton said:


> Is the plugin you mentioned a sure fire way to make WHEA 100% sure to work?


It's part of the kernel that as well in my understanding
You can't be sure till you actually see them reported
Did you try setting Enabled the LN2 mode in AMD OC?
That's a sure way for me to trigger a flooding of WHEA 19 at any FCLK
Left it one once and got crazy 



craxton said:


> Something like this (being 5 sources?) inside operations???


Yes exactly, you know it's registered. If they were 4 then it wasn't



craxton said:


> By this i believe you simply mean restarting WMI services???
> as WMI was the issue with my CPU 100% usage while nothing was showing
> the cpu actually being used, and was the culprit making my power profile to hot swap
> by itself....


No with WMI queries, not restarting the service.
I don't think it's connected but can't be sure.


----------



## mongoled

Veii said:


> Don't get used to this


As long as you occasionally pop in and blast wall of text/knowledge I will stay happy


----------



## kim nk

Hi! I wrote an eagle to thank the teacher who always gives useful information and to advise the timing of the veii and the timing of the cl13.
The motion of 1x tfaw was tested with the advice that it should be tras+1= trc.
In the case of tcke-9 and RTT 7/0/6 3-3-15, the error occurred and it was tested without giving it the value.



CPU : AMD RYZEN 5800x 47.75clock / Vcore Voltage 1.38v / LLC4 130%
CPU Cooling: ARCTIC Liquid Freezer II 420
M/B : ASUS ROG CROSSHAIR VIII DARK HERO
RAM : G.SKILL DDR4-3800 CL14 TRIDENT Z NEO package 16GB(8Gx2)
3800 CL 13-14-8-11-22 / 1.58v / soc 1.175v / real 1T / Power Down Mode: Disable
RAM Cooling: Noctua 60mm x 2ea
G/C : SAPPHIRE RX 6700 XT NITRO+ OC D6 12GB Tri-X

Due to the characteristics of the dark hero board, Trdwr could not be reduced to 7 under 8.











Real 1T










Real 2T









2.5T










I tightened the timing and blck.

3800 cl13









3828 cl13









The cl13-8-14-11-22-37 passed over 25 Tm5 adv5 cycles.

Please advise if there is anything that needs to be fixed at the timing of CL13-8-14-11-22-37 in the bottom photo.


----------



## Danny.ns

I did some testing with 1T GDM on (2.5T) and true 2T (my stuff cant do 1T on XMP speeds even) and while latency is the same, 2.5T ("1T with GDM enabled") always give better Read speeds of around ~400MB/s more than pure 2T. I ran Aida64 3 times on each setting and the results were pretty consistent for me. kim nk seems to get the same thing I noticed.


----------



## Veii

Senniha said:


> @Veii its really pain to get even 3333 without WHEA i tried everything.on 3466 i got blues screens with your settings .Please check now in this phase what i can do?


These are not my settings. DRAM calculator is not fine for 5xxx
It's different, it can work, but it's different
And since 1201and 1202, it's again fully different

60-20-30-20, or 60-20-40-20 CAD_BUS
RTT_PARK /5 is a high impedance 2x 8GB option , for single rank
it's a wonder that it can even post at it for 4 dimms
usually you need it stronger (lower) for 4 dimms


danakin said:


> does someone know how i can decrease latency ? i tried 1TM but it makes latency 55,x


What was the reason for using tRRD_L as 10+
You would usually move in the 5-8 region there

Start with 2T , GDM off
1T is a big jump
Use CAD_BUS 60-20-30-20
ProcODT lower than 40
Drop RTT_NOM to /6 , if you feel like staying at over 1.5v
Also tRFC2/4 is wrong










kim nk said:


> Please advise if there is anything that needs to be fixed at the timing of CL13-8-14-11-22-37 in the bottom photo.
> 
> 
> Danny.ns said:
> 
> 
> 
> I did some testing with 1T GDM on (2.5T) and true 2T (my stuff cant do 1T on XMP speeds even) and while latency is the same, 2.5T ("1T with GDM enabled") always give better Read speeds of around ~400MB/s more than pure 2T. I ran Aida64 3 times on each setting and the results were pretty consistent for me. kim nk seems to get the same thing I noticed.
Click to expand...

Good work 
This was my take as comparison
It's really interesting

GDM does give a tiiny bit of benefit - but the random access latency shows a big difference
And 2T showed if the set is powered well. Then once this is done - getting to 1T is easier.
Getting GDM away is hard , but 2T does not need any voltage changes - just fixing RTTs & CAD_BUS, which the board misspredict
I think the work is worth it - nevertheless what type of set you use.








MSI B550 Unify / Unify-X Overclocking & Discussions...


Command center allows to change vdimm? Never knew..




www.overclock.net












But then in comparison to 1T








On avg 0.6-1ns better ~ if you do the work
The difference gets smaller and smaller, the lower you go with the timings
Inconsistency between tests on Write (1 CCD) will show that your FCLK is not stable - neither the CPU is. If variation is bigger than 1-2 MB/s there
But it can be also bloated windows or buggy powerplans


----------



## RonLazer

> The only person that beats me memory stability wise (CPU Stability is very questionable , but hey 0c ambient - heh)
> Is a 3800 tRCD 12 set, which is also a transfer-time of 6.3158ns


They have 2Gb of system memory enabled and its a 46 minute stress test, if that counts as a stable result then I'll submit some of my 45-46ns setups on 2gb limited windows and top the list 



> I purely out of results, can not relate to the mentioned 7.5ns value


I did extensive testing on this, but am happy to be proven wrong, I've just not seen any evidence of it. Lots of things I tried were able to limit the error rate, I did manage to get it to the point I could run 3 cycles of [email protected] (took 2.5 hours) but it then failed 25mins into OCCT SSE3 CPU large dataset test. The difficulty seems to arise in some combination of bank group access patterns. I will note that I did my testing on 4x8gb so maybe I should revisit it with single-ranked configs. But I did test with multiple CPUs, motherboards (including the Unify-X) and 2 different kits of B-die (G.Skill Trident Z and Teamgroup 8Pack Xtreem), maybe the really high bins of B-die violate this, but it's bizarre that so many users hit the limitation of their B-die at exactly 7.5ns, when it can definitely run lower and the same dimms often do run <7.5ns on Intel CPUs. 



> Same as i do have couple of tRDWR 6, sets which break Ron's predicted/calculated -2 value as
> "the minimum that can potentially boot or even be stable"
> I break these rules, but he is over 80% accurate with the shared sheet.
> Just wish that we would stop hiding under locked algorithms ~ this doesn't teach anyone anything and can even fool yourself when somebody like me, randomly breaks your calculated results with stable results
> It just hides the potential for issue finding, doing anything locked or close source. Sadly NDAs are a thing and it's the death for a teaching overclocker to sign these


I displayed the algorithms right there in the sheet! I wasn't hiding anything! I will note that I was unsure how to deal with tBL, I was unsure if you could have purely Burst-Chop operation combined with tWPRE 1, but actually, if you ignore the CEILING[tCL/2 ] limit then the absolute minimum is indeed tRDWR 6. I updated the sheet to include all 3 combinations (tWPRE 1CK/2CK) and tBL 4/8, and a safe result that uses the tCL/2 limit. 

But if you consider it a challenge, I'd love to hear if you can boot tRDWR 5 in any configuration, since I am very unclear how its actually possible for a memory controller to conduct a read-to-write in less than 5 cycles, but if you can show me how that would be awesome!


----------



## TimeDrapery

@Veii @RonLazer 

Were you referring to this gentleman's spreadsheet?









unlockedDDR4TimingsforAMDZEN.xlsx


Shared with Dropbox




www.dropbox.com


----------



## Veii

RonLazer said:


> I displayed the algorithms right there in the sheet! I wasn't hiding anything! I will note that I was unsure how to deal with tBL, I was unsure if you could have purely Burst-Chop operation combined with tWPRE 1, but actually, if you ignore the CEILING[tCL/2 ] limit then the absolute minimum is indeed tRDWR 6. I updated the sheet to include all 3 combinations (tWPRE 1CK/2CK) and tBL 4/8, and a safe result that uses the tCL/2 limit.
> 
> But if you consider it a challenge, I'd love to hear if you can boot tRDWR 5 in any configuration, since I am very unclear how its actually possible for a memory controller to conduct a read-to-write in less than 5 cycles, but if you can show me how that would be awesome!


The first time i checked, it was going to another invincible Data-Sheet
The rulesets remain Datasheet column with another assigned column value
Nothing was readable for me, only usable
There have to be more sheets on it, but anyone except you can only see 1 - the main one

Could be now different, i haven't checked
Mmm, sometimes i abuse this
1604.08041.pdf (arxiv.org)
"Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity" ~ by Donghyuk Lee
as tBL 2
Overall a very inspirational research, based upon many JEDEC revisions 
After which i decided to ignore JEDEC ~ as every good researcher & micron, trows current research away and re-defines another "chapter" of JEDEC from scratch
(each of them vary completely)

But i'll test
Haven't ever gotten flat 11-11-11 to post
Soo flat 10-10 would be fun to try
12-8-12-10-22-32 was runnable tho

Wanted to answer you before with a collective set of tRDWR 6's , but i didn't manage to find all the old results
~ soo postponed the answer on your initial ping


Spoiler: This was one of them ~ 2019


----------



## ManniX-ITA

TimeDrapery said:


> Were you referring to this gentleman's spreadsheet?


I think this from @RonLazer?









tRDWR calculator


Sheet1 Frequency,3734,tRDWR tCL,18,Safe,9 tCWL,18,Fast,8 Minimum,6 Calculation details: The safe result is the higher of the rounded up value of tCL/2 or the JEDEC formula with tWPRE 2 Fast uses tWPRE 1 and the full burst length of 8 (tBL=8) Minimum is the timing that is achievable with tWPRE 1...




docs.google.com







RonLazer said:


> I've also seen some discussion about what suitable tRDWR timings are, so here is a mini calculator for the actual minimum (no guarantee of stability): tRDWR calculator


I can see the formula for the calculation BTW


----------



## lmfodor

Veii said:


> The first time i checked, it was going to another invincible Data-Sheet
> The rulesets remain Datasheet column with another assigned column value
> Nothing was readable for me, only usable
> There have to be more sheets on it, but anyone except you can only see 1 - the main one
> 
> Could be now different, i haven't checked
> Mmm, sometimes i abuse this
> 1604.08041.pdf (arxiv.org)
> "Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity" ~ by Donghyuk Lee
> as tBL 2
> Overall a very inspirational research, based upon many JEDEC revisions
> After which i decided to ignore JEDEC ~ as every good researcher & micron, trows current research away and re-defines another "chapter" of JEDEC from scratch
> (each of them vary completely)



Hi Veii, thanks for sharing this document, I guess I will finally understand how to download tRCDRD, at least the theory. I want to cut with the errors 6 that under any attempt to download it appear in burst mode! Do you have a spreadsheet to simulate the transition from configuration A to B? I mean now I have a stable setting at 3800 (with KedarWolf timings) and I would like to try a 4000 / x / -xx setting so maybe I could use a spreadsheet, I tried it with Google Ryzen Calc but it is missing information to me ..

Besides, I am trying to understand two scenarios, the first one starts with the last values that Kedarwolf shared with us, with SCL 4 and in my case a ProcODT reduction of 36 instead of 40 as the only difference. The second scenario below are the original values of him, with SCL 2 and even a higher ProctODT (48), but I left it at 36 since with both scenarios I had no problems and I understand that a lower value favors a better signal, am I right ?. I'm trying to understand why SCLs influence read / write speed, keeping tRDWR and tWRRD / constant. I also noticed that I can reduce the vSOC value from 1.2V to 1.16V without errors, maybe it's because I have a stronger LLC VSOC level at 4 and I think he has it at 2.


----------



## TimeDrapery

ManniX-ITA said:


> Spoiler
> 
> 
> 
> I think this from @RonLazer?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRDWR calculator
> 
> 
> Sheet1 Frequency,3734,tRDWR tCL,18,Safe,9 tCWL,18,Fast,8 Minimum,6 Calculation details: The safe result is the higher of the rounded up value of tCL/2 or the JEDEC formula with tWPRE 2 Fast uses tWPRE 1 and the full burst length of 8 (tBL=8) Minimum is the timing that is achievable with tWPRE 1...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> 
> 
> I can see the formula for the calculation BTW



@ManniX-ITA 

Aha! That makes sense! Thanks for keying me in

To add to the pile, I am also able to view the formula...

Okay, I've been working to understand how best to proceed after adding a second kit (so now I'm running 4 × 8GB of SR g.Skill B-die)

I started off with 2T and GDM disabled so I can get the hang of powering them

Mobo wants to set RTTs to 7/3/1, CAD BUS to 24-20-24-24, and ProcODT to 60Ω when I set 1.5V VDIMM... I've found that (so far) 6/3/3, 24-20-24-24, and 36.9Ω ProcODT seems to tame the beasts whereas I encountered many "4s" in TM5 with Auto rules running the show

Here's what I'll use as a baseline from here forward so long as it continues behaving:










Here's my current timing set, I did change up my config file to the 1usmus_v3 file... Apparently I was running his v2 file...? 😂😂😂😂😂










Here's an example of the errors I'd encountered running mobo Auto rules...










All of you that've done this dance before, what are your thoughts on where I'm at? Got any tips for me going forward?


----------



## craxton

ManniX-ITA said:


> Did you try setting Enabled the LN2 mode in AMD OC


last few times i tried i couldnt get a post AT ALL while LN2 mode was on...



ManniX-ITA said:


> cheat with telemetry:


What values does one try with a 5600x?
first ive seen of this...(have seen this setting in the bios, just never attempted to mess with it)
didnt know it had many gains.



ManniX-ITA said:


> Yes exactly, you know it's registered


so, to be clear registered does not mean its working tho...



ManniX-ITA said:


> No with WMI queries,


again, im unsure what that means lol...i read LOADS on the link you shared about WHEA thru microsot etc. 
but im inexperienced when it comes to C++ anything at all.... 
let alone knowing what a queries actually are.



ManniX-ITA said:


> I think this from @RonLazer?


how many more spreadsheets like this are there????
Google does NOTHING when trying to search (ryzen, ram, spreadsheet)....


----------



## ManniX-ITA

craxton said:


> last few times i tried i couldnt get a post AT ALL while LN2 mode was on...


That's a pity... I don't know any other method to trigger WHEA voluntarily.



craxton said:


> What values does one try with a 5600x?
> first ive seen of this...(have seen this setting in the bios, just never attempted to mess with it)
> didnt know it had many gains.


Good question... I had to run a lot of benchmarks to find the right one for the 5950x.
The biggest delta for me is on Geekbench5 MT.
You have to try and see what's the best value for you.
Consider I have EDC at 215A and with 50 offset creates a ghost 50A of usage.
If those values doesn't work for you try to scale the offset to just below a 4th of your current EDC limit.



craxton said:


> so, to be clear registered does not mean its working tho...


Yes, if it's not registered for sure doesn't work but not vice versa



craxton said:


> again, im unsure what that means lol...i read LOADS on the link you shared about WHEA thru microsot etc.
> but im inexperienced when it comes to C++ anything at all....
> let alone knowing what a queries actually are.


WMI is like an internal database; you can create a query, like a command, and read and set stuff.
It's just an info, you can forget it



craxton said:


> how many more spreadsheets like this are there????
> Google does NOTHING when trying to search (ryzen, ram, spreadsheet)....


Sometimes they are indexed but they need to be referenced many times...
In general you need to catch them in some posts.


----------



## TimeDrapery

Ack! In the last little bit too... 😂😂😂😂😂










It's the one n only too...










Sooooo... PCB crash... Considering ClkDrvStr is set to 24.0Ω I imagine it's likely the RTTs and one or more are too strong

Anybody with experience running 4 × 8GB SR DIMMs have some insight on RTTs that they'd be willing to impart upon me? @craxton @ManniX-ITA @RonLazer @Veii ?


----------



## GribblyStick

Well I can't recommend anything but I am running 4x8 SR so here's what I have:











READ/WRITE and latencies have slowed since trying to overclock CPU but L3 performance has improved so I have that going going for me I guess.
not shown is VDIMM 1,5 and vddp CPU o 0,840 IIRC t, that or 0,860


----------



## craxton

ManniX-ITA said:


> That's a pity... I don't know any other method to trigger WHEA voluntarily.


well, about that....when LN2 mode is on using AMDs overclocking section, i get SUPER STRANGE 
stuff happening like, Display cutout, no wifi or driver shown, bt not working, mouse bt not showing, and again,
the display like turns off and on every 30 seconds.....BUT NO MFN WHEA SHOWN....
so, now im rather worried that i have in fact a major issue somewhere.
but sfc/scannow says im good, and the few other commands that call for restarting the pc say im good too..
so idk...



ManniX-ITA said:


> Yes, if it's not registered for sure doesn't work but not vice versa


noted, registered doesnt mean working, ive looked EVERYWHERE to try to find out how to know if
error reporting is doing its job correctly. sure i have errors, warnings, info pop up...but no WHEA (besides the mentioned CO fiddling)



ManniX-ITA said:


> Consider I have EDC at 215A and with 50 offset creates a ghost 50A of usage.
> If those values doesn't work for you try to scale the offset to just below a 4th of your current EDC limit.


ill do some research on it then start testing. 
i for sure cant afford to fry my cpu...which i have the 3600xt and 1600af but....well, this the only 5000 in my house atm lol



ManniX-ITA said:


> WMI is like an internal database; you can create a query, like a command, and read and set stuff.
> It's just an info, you can forget it


already forgotten...



TimeDrapery said:


> 4 × 8GB SR DIMMs have some insight on RTTs that they'd be willing to impart upon me?


are you sure RTT is the way to go? 
have you tried slightly less VDimm???

my tCKE has to be 11 otherwise i crash out or, error.
im unsure if it relates to 3000 chips, as 5000 is slightly different. but
i assume it should be pretty similar. 



Spoiler



im not the best suited to be asked honestly RTT is my main struggle
but, before changing id try Vdimm, and give tCKE 11 a shot.


----------



## DeletedMember558271

1.45v, 4x8GB, 3733, 53.3ns.














Since 1900 FCLK is never going to post and 1933+ is always going to have WHEA and there is apparently nothing I can do about either I figured it was finally time to ditch my old barely any effort settings I was using while hoping for either of these to get fixed before putting any more effort in.

On top of those issues I have a 3080 and play demanding games for long periods at a time at uncapped FPS, at some point over 1.5v it tends to overheat into errors even with a fan on the RAM with a hot 3080 exhausting right onto it, so I wanted to limit myself to 1.45v max.

With all the talk in more recent months of 2T > GDM On "2.5T" I figured that was worthwhile trying too, I can probably still get tRCDWR much lower along with tRP, tRAS, and tRC a little bit. The only things I know cannot go lower right now at these settings are the SCL's @ 3 will cause errors after some time, tRFC @ tRC * 6 is not stable so it's tCL/2-1 unless I end up changing my tRC lower, I unfortunately cannot get tRDWR to 8 or tWRRD to 1, so no 10&1 or 8&3. tCL @ 14 fails to boot, as does tCWL lower than 14. The rest I haven't tried pushing further.

ProcODT, RTT's, CAD_BUS, I still barely understand if they're optimal but hey it seems to be working, along with voltages VDDP, CCD, IOD, I still don't know where lowering them starts to hurt performance, people are all over the place with these from 0.9 to 1.1 still.

Anyways here are all the other 4x8GB's under 54ns with their vDIMM's on the far right:








I'm still the fastest somehow that can't post 3800/1900, that 52.7ns is an old result of mine, which could be better. And now I have the lowest voltage under 54ns by a good bit and am still the only one under 1900... I don't even know if it's worth submitting this with how much of a joke that sheet has become though, still saying "WHEA free" with all the results they allow on there... that 51.2ns 2033 FCLK literally admitted they have WHEA but it's still up there and that's like 1 of 30 or more on there like that. The 51.5ns 2000 FCLK put a comment on their name saying they have WHEA too... "WHEA free" sheet btw  moderators of it are blind I guess. Oh well


----------



## TimeDrapery

I think reducing the strength of RttPark from RZQ/1 to RZQ/4 cas well as increasing the strength of RttNom from RZQ/7 to RZQ/6 appears to have helped out


















Thanks to everyone that gave their input and suggestions!

Oh, JK 😂😂😂😂😂










I'm gonna try RttPark at RZQ/5










I'm loving the jump in performance I'm seeing, I'm excited to see where they go when I work out the powering


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> well, about that....when LN2 mode is on using AMDs overclocking section, i get SUPER STRANGE
> stuff happening like, Display cutout, no wifi or driver shown, bt not working, mouse bt not showing, and again,
> the display like turns off and on every 30 seconds.....BUT NO MFN WHEA SHOWN....
> so, now im rather worried that i have in fact a major issue somewhere.
> but sfc/scannow says im good, and the few other commands that call for restarting the pc say im good too..
> so idk...
> 
> 
> noted, registered doesnt mean working, ive looked EVERYWHERE to try to find out how to know if
> error reporting is doing its job correctly. sure i have errors, warnings, info pop up...but no WHEA (besides the mentioned CO fiddling)
> 
> 
> ill do some research on it then start testing.
> i for sure cant afford to fry my cpu...which i have the 3600xt and 1600af but....well, this the only 5000 in my house atm lol
> 
> 
> already forgotten...
> 
> 
> 
> are you sure RTT is the way to go?
> have you tried slightly less VDimm???
> 
> my tCKE has to be 11 otherwise i crash out or, error.
> im unsure if it relates to 3000 chips, as 5000 is slightly different. but
> i assume it should be pretty similar.
> 
> 
> 
> Spoiler
> 
> 
> 
> im not the best suited to be asked honestly RTT is my main struggle
> but, before changing id try Vdimm, and give tCKE 11 a shot.



@craxton 

No I'm not sure 😂😂😂😂😂

I'd like to get the powering and termination going at this level, my thinking is this will help later when I'd want to increase it to move towards lesser timings... but I dunno if that's overthinking it

I got another (free, yippie!) of the same kit arriving tomorrow and if I've the time I'm gonna go through and bin all the DIMMs

I've got another kit from TeamGroup that I'm tuning on a R3 3100... This has been really fun during the last year plus whatever with the pandemic learning all of this

I want to try and get these 4 × 8GB sticks to a 14-15-15-30 set as I think I'll see good results if it works out how I'm imagining it to 😂😂😂😂😂

The latest beta from Gigabyte for the Pro-P board my 3100 is on caps me at 1A TDC 😂😂😂😂😂, I had to downgrade to F12 but... No 28.2Ω ProcODT!... Probably not the end of the world as I obviously didn't use it last time I ran these sticks

The 3100 is a 3950X with a bunch of cores chopped?!? Debug on ZenTimings says so but I have no idea what that means as far as what I should expect of the CPU

I remember running it above 4.4GHz (far above the boost clock advertised) without issue but that was a while ago


----------



## jomama22

Dreamic said:


> 1.45v, 4x8GB, 3733, 53.3ns.
> View attachment 2489681
> View attachment 2489682
> 
> Since 1900 FCLK is never going to post and 1933+ is always going to have WHEA and there is apparently nothing I can do about either I figured it was finally time to ditch my old barely any effort settings I was using while hoping for either of these to get fixed before putting any more effort in.
> 
> On top of those issues I have a 3080 and play demanding games for long periods at a time at uncapped FPS, at some point over 1.5v it tends to overheat into errors even with a fan on the RAM with a hot 3080 exhausting right onto it, so I wanted to limit myself to 1.45v max.
> 
> With all the talk in more recent months of 2T > GDM On "2.5T" I figured that was worthwhile trying too, I can probably still get tRCDWR much lower along with tRP, tRAS, and tRC a little bit. The only things I know cannot go lower right now at these settings are the SCL's @ 3 will cause errors after some time, tRFC @ tRC * 6 is not stable so it's tCL/2-1 unless I end up changing my tRC lower, I unfortunately cannot get tRDWR to 8 or tWRRD to 1, so no 10&1 or 8&3. tCL @ 14 fails to boot, as does tCWL lower than 14. The rest I haven't tried pushing further.
> 
> ProcODT, RTT's, CAD_BUS, I still barely understand if they're optimal but hey it seems to be working, along with voltages VDDP, CCD, IOD, I still don't know where lowering them starts to hurt performance, people are all over the place with these from 0.9 to 1.1 still.
> 
> Anyways here are all the other 4x8GB's under 54ns with their vDIMM's on the far right:
> View attachment 2489684
> 
> I'm still the fastest somehow that can't post 3800/1900, that 52.7ns is an old result of mine, which could be better. And now I have the lowest voltage under 54ns by a good bit and am still the only one under 1900... I don't even know if it's worth submitting this with how much of a joke that sheet has become though, still saying "WHEA free" with all the results they allow on there... that 51.2ns 2033 FCLK literally admitted they have WHEA but it's still up there and that's like 1 of 30 or more on there like that. The 51.5ns 2000 FCLK put a comment on their name saying they have WHEA too... "WHEA free" sheet btw  moderators of it are blind I guess. Oh well


Just to throw it out there but you will have to compare your results to other single ccd chips as that will grant you about 1.0-1.4ns over somthing like a 5900/5950. That 5950x with 51.2 is with 1 ccd disabled.

As an example, my 5950x @ 3800cl14 under safe mode will run a 52.5...and that's also a kicker. Everyone running safe mode lol.


----------



## TimeDrapery

Regarding what I'd said about this 3100


----------



## Hale59

TimeDrapery said:


> Regarding what I'd said about this 3100


Yes, different from mine. What is AMD up to?


----------



## ManniX-ITA

AFAIK the 3100 is the "recycle bin" for failed CCDs 
It does exist in every possible configuration; 2CCD 1CCX 2 Cores, 2CCD 2CCX 1 Core, 1CCD 2CCX 2 Cores, 1CCD 1CCX 4 Cores


----------



## Hale59

ManniX-ITA said:


> AFAIK the 3100 is the "recycle bin" for failed CCDs
> It does exist in every possible configuration; 2CCD 1CCX 2 Cores, 2CCD 2CCX 1 Core, 1CCD 2CCX 2 Cores, 1CCD 1CCX 4 Cores


It might be so, but at least I can bench mine @4900MHz easy. No much luck with my previous 6 and 12 core CPUs.


----------



## TimeDrapery

ManniX-ITA said:


> Spoiler
> 
> 
> 
> AFAIK the 3100 is the "recycle bin" for failed CCDs
> It does exist in every possible configuration; 2CCD 1CCX 2 Cores, 2CCD 2CCX 1 Core, 1CCD 2CCX 2 Cores, 1CCD 1CCX 4 Cores



That's my thought as well! Pretty interesting!!!


----------



## ManniX-ITA

Hale59 said:


> It might be so, but at least I can bench mine @4900MHz easy. No much luck with my previous 6 and 12 core CPUs.


Yes they OC very well, the bad cores are disabled.
Maybe not the best bin but that's a matter of luck.
And if it's a win if it's a 1CCD but usually those ends in a 3300.


----------



## TimeDrapery

ManniX-ITA said:


> Spoiler
> 
> 
> 
> Yes they OC very well, the bad cores are disabled.
> Maybe not the best bin but that's a matter of luck.
> And if it's a win if it's a 1CCD but usually those ends in a 3300.



I'm gonna lap it, as well as the cold plate on this cooler, and see what it do 😁😁😁😁😁


























I'm trying different resistances to see if it throws a different error, if it does I'll let tRTP out to 8 and tWR out to 16 and see if the error presents again

Aha, Error #4... Back to the old resistances and time to loosen tRTP/tWR


----------



## Hale59

TimeDrapery said:


> I'm gonna lap it, as well as the cold plate on this cooler, and see what it do 😁😁😁😁😁
> 
> I'm trying different resistances to see if it throws a different error, if it does I'll let tRTP out to 8 and tWR out to 16 and see if the error presents again


Looks like we have the same Single Rank memory. I will look for it and will post.
I cannot remember the full timings, but here is CL14, between 1.5 and 1.53v.
With CL14, I'm the top rank @HWBOT - 4x Geekbench5 - Multi Core...look at the CPU voltage applied...and no breaking a sweat.









**EDIT*: Increasing the Bus Speed helps a lot.


----------



## DeletedMember558271

jomama22 said:


> Just to throw it out there but you will have to compare your results to other single ccd chips as that will grant you about 1.0-1.4ns over somthing like a 5900/5950. That 5950x with 51.2 is with 1 ccd disabled.
> 
> As an example, my 5950x @ 3800cl14 under safe mode will run a 52.5...and that's also a kicker. Everyone running safe mode lol.


Yes, also safe mode is basically the same as a fresh Windows install if I'm not mistaken or if your Windows was perfectly clean with no added personal bloat. If people aren't doing that we're in a way benchmarking the personal cleanliness of everyones Windows installation as a factor, instead of just what the overclock can do in as close to the same environment as possible.
Otherwise it's really just a how clean is your Windows competition, have a worse overclock but cleaner Windows? You can win


----------



## Veii

There are 3100, 3300 ~ same as 5600X & 5800X which have both CCDs on them
And all of these can be unlocked _~in an unnoted near future~_


----------



## jomama22

Dreamic said:


> Yes, also safe mode is basically the same as a fresh Windows install if I'm not mistaken or if your Windows was perfectly clean with no added personal bloat. If people aren't doing that we're in a way benchmarking the personal cleanliness of everyones Windows installation as a factor, instead of just what the overclock can do in as close to the same environment as possible.
> Otherwise it's really just a how clean is your Windows competition, have a worse overclock but cleaner Windows? You can win


Safe mode is much leaner than a clean install. With only 40 some process running vs 100+.

And I agree, the problem is, no one states whether it's safemode or not. It's inevitable that people will look at that sheet or w.e others post and just compare it to their normal windows install and just immediately think somthing is wrong.


----------



## Veii

jomama22 said:


> And I agree, the problem is, no one states whether it's safemode or not. It's inevitable that people will look at that sheet or w.e others post and just compare it to their normal windows install and just immediately think somthing is wrong.


Anything that has no CPU-Z readout through Aida64, on the cache benchmark - is always safemode
Also doesn't help people, who only test latency
The system won't reach peak boost if you only tap one field - compared to pressing "start test" and letting everything run


Dreamic said:


> I don't even know if it's worth submitting this with how much of a joke that sheet has become though, still saying "WHEA free" with all the results they allow on there... that 51.2ns 2033 FCLK literally admitted they have WHEA but it's still up there and that's like 1 of 30 or more on there like that. The 51.5ns 2000 FCLK put a comment on their name saying they have WHEA too... "WHEA free" sheet btw  moderators of it are blind I guess. Oh well


There is no moderation team
There is only one main sheet maker who does check it every week
Probably he didn't expect the amount of work it takes, maintaining a frequency used sheet

The only way to communicate with him - is writing a "note" soo "opening an issue" 
Which he most of the times receives and takes a look in less than a day
Either it's getting resolved or it stays active
But at least it's acknowledged that way


----------



## ManniX-ITA

Dreamic said:


> Yes, also safe mode is basically the same as a fresh Windows install if I'm not mistaken or if your Windows was perfectly clean with no added personal bloat. If people aren't doing that we're in a way benchmarking the personal cleanliness of everyones Windows installation as a factor, instead of just what the overclock can do in as close to the same environment as possible.
> Otherwise it's really just a how clean is your Windows competition, have a worse overclock but cleaner Windows? You can win


I think you can gain more with safe mode.
I can't use my main install; it's seriously bloated.
There is a lot of software that I keep or have to keep running that makes it impossible.
Not only for scores but also for repeatable results.

I wholeheartedly recommend to use a Windows To Go benching install via USB.
Not only to get better scores but for safety.
You don't mess your own main install with failed overclocks and risk to lose data.
And the most important thing is that a WinToGo install is basically indestructible.
You mess with the wrong OC and you need to reinstall Windows.
The WinToGo install is insanely robust, I didn't even had to repair it once.
I have spent countless hours in the past reinstalling Windows & Co, never again.
You can also set offline your main install disks and avoid any kind of corruption with BCLK OC.
It's a life saver.


----------



## DeletedMember558271

jomama22 said:


> Safe mode is much leaner than a clean install. With only 40 some process running vs 100+.
> 
> And I agree, the problem is, no one states whether it's safemode or not. It's inevitable that people will look at that sheet or w.e others post and just compare it to their normal windows install and just immediately think somthing is wrong.


Maybe it's just coincidence in my situation then but I remember comparing safe mode latency to my normal Windows latency and they would be the same if I just disabled the few extra programs and services I usually have running, I already try to have as few non-Microsoft/Windows things running as possible.


----------



## GribblyStick

i gained like 3+ ns by using safe mode and they were more stable to boot.
in normal windows to even get an idea of my latency I need to run aida at least 10 times.At any given time it can vary up to like 4 ns.


----------



## Veii

Dreamic said:


> Maybe it's just coincidence in my situation then but I remember comparing safe mode latency to my normal Windows latency and they would be the same if I just disabled the few extra programs and services I usually have running, I already try to have as few non-Microsoft/Windows things running as possible.


Same herre
It was even worse tbh ,because powerrmanagement didn't work


----------



## jomama22

Veii said:


> Anything that has no CPU-Z readout through Aida64, on the cache benchmark - is always safemode
> Also doesn't help people, who only test latency
> The system won't reach peak boost if you only tap one field - compared to pressing "start test" and letting everything run


Again, it is easy for us to understand that as it's somthing we deal with and know. But for those who don't mess with this stuff often, I can easily see it being overlooked.

I personally havn't had the issue of aida not boosting fully when running individual tests as opposed to running the whole suite. Just today when messing around with 1ccd and letting boost hit 5200, I was able to get 51.2ns @ 3800/1900 14-14-14-28-39 32gb/DR and a L3 latency of 9.7ns. I clicked each box individually for this. The L3 bandwidth is low because of me setting 140 for EDC (was set for when I use dynamic OC switcher, and being on agesa 1.1.8.0).









This may come down to the whole 'aida using core 0' thing as core 0 is my best core.

Also a fun fact: I have discovered that All-core oc's affect 1 CCD chips (at least 5690/5800's with 1 actual CCD) differently than 2 CCD chips interms of memory latency.

On the 2CCD variants, an all-core OC will ALWAYS produce lower memory latencies than PBO.

Meanwhile, on 1CCD variants, the reverse is true. It seems that 1CCD variants will infact rely on PBO boost clocks to determine some part of the memory latency.

My evidence for this is as follows:
Memory 3800cl14-14-14-28-39 32GB/DR
1CCD:
All-core @4.8ghz: 51.9-52.0ns
[email protected] boost: 51.2ns
2CCD:
All-core @4.8: 51.9-52.0ns
[email protected] boost: 52.5ns

So somthing is definitely going on between 1CCD and 2CCD chips in this case.

I should note the results are the same with c-states/d states enabled or disabled. Also, smt disabled will make all-core scores worse, I did not test this with pbo.

Also want to add these were at 2T rate. Also, 2T was much more difficult for me to run on a full 16 cores (2 ccd's) than 8 cores (1 ccd).


----------



## jomama22

Dreamic said:


> Maybe it's just coincidence in my situation then but I remember comparing safe mode latency to my normal Windows latency and they would be the same if I just disabled the few extra programs and services I usually have running, I already try to have as few non-Microsoft/Windows things running as possible.


Once we start talking about services and process you remove, it's no longer just a clean windows install. It a windows install you have altered that allows lower latencies.

Personally, I only see about a .2ns-.3ns difference between the two but it's still there.

I'm speaking here for the lowest common denominator here btw. I.E. someone who doesn't do overclocking much, doesn't understand the INS and outs of memory latency and is just firing up their PC that has steam, afterburner, etc. autostarting when they get into windows.

Assuming everyone should just know is always a way to create confusion.


----------



## GribblyStick

FYI, that 220 EDC spike was not a fluke by the looks. I let tm5 run a few mins and it sat consistently around 220:










Also, @Veii , I didn't mean to say I was surprised by seeing 200 when I set 400, but by seeing 220. Which I understood to be higher than the agreed upon fuse limit.


----------



## jomama22

GribblyStick said:


> FYI, that 220 EDC spike was not a fluke by the looks. I let tm5 run a few mins and it sat consistently around 220:
> 
> View attachment 2489802
> 
> 
> Also, @Veii , I didn't mean to say I was surprised by seeing 200 when I set 400, but by seeing 220. Which I understood to be higher than the agreed upon fuse limit.


This is just caused by setting edc limits high, that's it. 

here's mine when I decide to set 1000 for edc:









basically the same as yours (which I would expect since the 5900x and 5950x have the same limit).

Really, ignore the fuse limit as you cant change it. Rather, you need to mess with the ppt/tdc/edc and find what gives you the most performance. Its slightly different for everyone but there is a sweetspot to be found.


----------



## ManniX-ITA

jomama22 said:


> basically the same as yours (which I would expect since the 5900x and 5950x have the same limit).
> 
> Really, ignore the fuse limit as you cant change it. Rather, you need to mess with the ppt/tdc/edc and find what gives you the most performance. Its slightly different for everyone but there is a sweetspot to be found.


How do you check what's the fuse limit?

I can pull up to 252A with Cinebench setting EDC at 300A.
When i first got the 5859x, don't remember using what, I pulled up to 400A using motherboard limits.
At least that's what is reported by HWInfo, I'm not sure if it's real or not.
But I have the power consumption monitored with 400A the draw was astronomical.
Obviously without almost any gain in performance, it's worse than EDC at 215A..
Hits almost immediately the thermal throttle limit at 90c and I assumed also FUSE limit.
But I'm surprised you can actually see the limit in HWInfo.

TM5 can hit 246A, almost as Cinebench but hits as well 90c.
Falling asleep... I had left Prime95 open in the background.
Realized 90c for TM5 was really odd 










TM5 can pull the most 268A.


----------



## jomama22

ManniX-ITA said:


> How do you check what's the fuse limit?
> 
> I can pull up to 252A with Cinebench setting EDC at 300A.
> When i first got the 5859x, don't remember using what, I pulled up to 400A using motherboard limits.
> At least that's what is reported by HWInfo, I'm not sure if it's real or not.
> But I have the power consumption monitored with 400A the draw was astronomical.
> Obviously without almost any gain in performance, it's worse than EDC at 215A..
> Hits almost immediately the thermal throttle limit at 90c and I assumed also FUSE limit.
> But I'm surprised you can actually see the limit in HWInfo.
> 
> TM5 can hit 246A, almost as Cinebench but hits as well 90c.
> Falling asleep... I had left Prime95 open in the background.
> Realized 90c for TM5 was really odd
> 
> View attachment 2489812
> 
> 
> TM5 can pull the most 268A.
> 
> View attachment 2489813


Yeah, playing with edc will get you different maximums. On my msi ace, 210 was the best value for both single and all core. On the dark hero, it's around 245.

But I think msi is either messing with telemetry slightly to get a bit more all core boost tbh, but it actually runs cooler than the dark hero, so who knows lol.


----------



## craxton

jomama22 said:


> Everyone running safe mode lol


Any and ALL aida shots or Latency screenshots ive posted (ever) on this site,
have been running windows normally.... i didnt know about (safemode) being a thing until just the other day
when trying to figure out what was up with power plans on my pc...


----------



## craxton

Question, to you peeps with (debug/ryzen knowledge about 5000 chips.)

anything special about my 5600x on an obvious note???|


----------



## Sleepycat

craxton said:


> Question, to you peeps with (debug/ryzen knowledge about 5000 chips.)
> 
> anything special about my 5600x on an obvious note???|
> 
> View attachment 2489828


You need to update to a newer version of Zentimings so that it can read your CCX count.


----------



## jomama22

craxton said:


> Any and ALL aida shots or Latency screenshots ive posted (ever) on this site,
> have been running windows normally.... i didnt know about (safemode) being a thing until just the other day
> when trying to figure out what was up with power plans on my pc...


Hence all my posts about people not being aware haha.


----------



## PJVol

ManniX-ITA said:


> But I have the power consumption monitored with 400A the draw was astronomical


What Power Reporting Deviation was shown in HWINFO when running CB R20 MT ? And did you adjust vddcr cpu full_scale_current ? (in PBS)
I have adjusted it from default 245 to 220, and now HWInfo reporting actual power consumed with PRD showed as 100% +/- 1%. Not sure though, if this affects reported EDC/TDC values.


jomama22 said:


> Meanwhile, on 1CCD variants, the reverse is true. It seems that 1CCD variants will infact rely on PBO boost clocks to determine some part of the memory latency.


I don't see why it should be different on 1 and 2 CCD cpus. End result will depend on max frequency achievable during test. The only thing seem abnormal is latency test affinity to core 0. Allcore gives higher latency as well, until 4850.


----------



## ManniX-ITA

PJVol said:


> What Power Reporting Deviation was shown in HWINFO when running CB R20 MT ? And did you adjust vddcr cpu full_scale_current ? (in PBS)
> I have adjusted it from default 245 to 220, and now HWInfo reporting actual power consumed with PRD showed as 100% +/- 1%. Not sure though, if this affects reported EDC/TDC values.


Didn't notice it but as you can see from the screenshots during Prime95 was 67% and TM5 90%.
Yes I use custom telemetry, what do you mean for PBS? AMD PBS menu?
I don't think I've seen telemetry options there.
The telemetry affects EDC reporting, as you can see mine is minimum 50A.

These are the options I use under OC\Advanced CPU:


----------



## Veii

jomama22 said:


> On the 2CCD variants, an all-core OC will ALWAYS produce lower memory latencies than PBO.
> 
> Meanwhile, on 1CCD variants, the reverse is true. It seems that 1CCD variants will infact rely on PBO boost clocks to determine some part of the memory latency.


I've noticed on my abstract dual CCD 5600X, that an allcore (aside from dying fully after a certain range ~ because of the 2nd bad CCD) *
* soo on an allcore @ 1st CCD @ only the "free" cores and not the "not so great disabled 2 cores on the first CCD"
An allcore, lead to worse L3 access time (by 0.1ns) and around 30-40GB/s less maximum L3 cache
Often it was more than that, but fixing only the correct cores ~ got it down to around 5? %

This is important when we talk about CTR usage & why i don't use the 5ghz allcore option from CTR - but still prefer my 4.85 PBO


jomama22 said:


> Once we start talking about services and process you remove, it's no longer just a clean windows install. It a windows install you have altered that allows lower latencies.
> 
> Personally, I only see about a .2ns-.3ns difference between the two but it's still there.


This is a paradox
Grab Autoruns for Windows - Windows Sysinternals and admin-open the 64.exe
Pre & = 20H2 (pre final H2 update) ~ there where around 30 active services & autostart + shedule task "services"
Now if we upgrade to finally 20H2 or even 21H1 (which usually runs great if you don't upgrade but clean install)
The list changes, you have "access" to everything (except that on some things you fully lose all permissions as Administrator)
but the options change from 30 , to 100+ autostart services ~ split option by option by option. For every little tiny thing

Now if we compare a stock enterprise, vs a stock home, vs a re-modded Home → ProWorkstation








GitHub - DrEmpiricism/ConvertTo-PfW: Windows 10 Home to Windows 10 Pro for Workstations converter.


Windows 10 Home to Windows 10 Pro for Workstations converter. - GitHub - DrEmpiricism/ConvertTo-PfW: Windows 10 Home to Windows 10 Pro for Workstations converter.




github.com




With it's slightly different task sheduler
The "stock" OS changes again. As a Pay-to-be-spy-free, Microsoft DLC (199$ i think was the "Pro for Workstation" DLC)

We can't compare this. But we can't also judge Home vs Enterprise vs ProWorkstation DLC
I don't think we should focus our blame in the users wallet size & which OS they run.

But for example not accepting SafeMode results, is something we maybe could do
It would be even better, if we set a standart & registry fix that not only disables the "correct" services without affecting any daily usage (no benchOS)
And likely also start to fill out another thread for which of these 120+ new autoruns should be disabled for every "gamer" & "PC user"
Agreeing on this would resolve this paradox - or we ignore the paradox & accept that everyone will abuse it to their extend of knowledge 


Spoiler: Illustration & Comparison [TaskManager] 



21H1 "fixed" yet still bad / RAM usage is higher








69 Processes ~ 620ish Threads are the goal
I lost the picture, seems like 
- but here is an illustration how "bad" it can look
That "amount" exists at least 4* more.
Over 100+ active ones













GribblyStick said:


> Also, @Veii , I didn't mean to say I was surprised by seeing 200 when I set 400, but by seeing 220. Which I understood to be higher than the agreed upon fuse limit.
> 
> 
> jomama22 said:
> 
> 
> 
> Really, ignore the fuse limit as you cant change it. Rather, you need to mess with the ppt/tdc/edc and find what gives you the most performance. I
Click to expand...

Unsure if the big linked answer was red , but it lists maximum EDC boost limits & lists the current artifical FUSE limit at this date
The only way to bypass it, is to support one of the 3? developers who rework the boosting system with their WIP OC-Tools
I think it's Mannix-ITA, 1usmus & maybe IrusanovBG

The problem falls back to an NDA
Either they have or don't have the needed information
If they _requested _it, then talking about this topic is prohibited ~ even mentioning or answering about it
Telemetry faking is what couple of boards already do. Some with public settings, others on Auto Settings ~ 3rd ones without even listing them as options
It's good that the 5950X finally gets an uplift over the 200A one they shared with the 5900X.
The only reason to extend PBO limits - is to lift some internal limiters.
The major internal limiters will remain active and limit it ~ or even package throttle it on overcurrent (loss of perf)

But potential package throttle, is better than intentional throttle by a lack of remain power-budget.
I wish i could telemetry fake it a bit
FCLK & SOC take a too strong hit on my powerbudget. 1/3rd of it
* or figure out how to reprogram the OPN number
==================
Oh something to add 
I've started to fail & fixed y-cruncher again on AGESA 1.2.0.2
It crashed on my 2nd best core (last one, 10/11)
It was running +60mV, LLC 3/5 (5=most droop) @ -28 CO
The reason for the crash on N32/N64/VST ~ was overvoltage & package throttle
Lowering CO, to -30 fixed it

Soo it can also crash because of overvoltage & not only "lack of voltage"


----------



## Veii

ManniX-ITA said:


> How do you check what's the fuse limit?


It's the limit which you will max out at y-crunche and stay at the same peak EDC % , under snapshot pooling mode (HWInfo)
OC_Mode bypasses this limit.
After a certain point SMU won't read any limit higher
That's the FUSE limit.Telemetry faking allows to work against this
CO does work internally against it (shift it down), but the limit is a programmed hard limit


----------



## GribblyStick

How are you guys getting up to 4,85?
I tried pushing positive offset with an all core negative co of -30 and just pure pbo, but I'm closest I could get was 4700 in tm5.
Tried from from 0,5 to 0,85 but I couldn't really see any improvement, if anything I got lower performance.
Next things I was going to try is to do a per core CO and then I guess, just trying various mixes of PPT/TPC/EDC

I haven't had any stability issues so far, and temps are in control, but I feel like the system isn't being pushed as much as it could.
I see manny gets to the 90ties. PBO increased my temps into the 70is with similar performance albeit a bit worse than an allcore -30.
Auto instead of offset got me Voltages in the 1,1 range with lower tempos but also lower frequencies.
Adding additional offset only seemed to make things hotter with no observed gain.
Currently I've seen clock boost to 5150 but near as I can tell effective was nowhere near that.
It does seem to give me the most bench scores however.


----------



## ManniX-ITA

Veii said:


> But for example not accepting SafeMode results, is something we maybe could do


I agree but is there an easy safe way how to check if it's running in safe mode?



Veii said:


> It would be even better, if we set a standart & registry fix that not only disables the "correct" services without affecting any daily usage (no benchOS)


Absolutely a good idea the script.
But as said I can't use my daily 
Just Kaspersky AV, True Image, Aqua service, Hyper-V are costing me 2-3ns of latency and 50 MHz of CPU clock.
Full featured, all running, it's 5ns latency and 100-150 MHz clock.
There's no way for me to go back to a normal state without uninstalling crucial stuff.

I have nothing against a BenchOS, quite the contrary; I think it's fair to "race" on a track and not on "city streets".
If your daily is clean as a BenchOS even better but I can't do the same 
BTW my BenchOS is not slimmed down to the bones.
It is full featured, except no AV running (but I didn't eradicate the MS antimalware).
Full drivers installed and the same I use in the daily.
I'd feel uncomfortable to use something less that that, it'd be like cheating with safe mode.

It's not only about scores, which is fun; I use it to validate the OC that I'm going to use for the daily.
Being too much slimmed down works against this concept.
Already like this it's borderline acceptable as sometimes I don't see instabilities till I boot into the main.

But anyway, as always in this kind of initiative, how do you detect "cheating" of the rules?
That I know of only Benchmate can do it. Not sure how reliable and strong it is.
Should we allow validation only if TM5 is launched through BM?
I think we can ask to add support for it 



Veii said:


> The only way to bypass it, is to support one of the 3? developers who rework the boosting system with their WIP OC-Tools
> I think it's Mannix-ITA, 1usmus & maybe IrusanovBG


Yes, dynamic switching to static OC is the best way to handle it.



Veii said:


> The problem falls back to an NDA
> Either they have or don't have the needed information
> If they _requested _it, then talking about this topic is prohibited ~ even mentioning or answering about it


Luckily, AMD bounced me with goto person A, goto B, goto A.... 
I'm not going to sign any NDA with them.
They are barely professional.
And while I obviously understand the need for NDAs, I personally hate the concept.
Just like patents are more a mean to stifle innovation than anything else.



Veii said:


> Telemetry faking is what couple of boards already do. Some with public settings, others on Auto Settings ~ 3rd ones without even listing them as options


Indeed. My AORUS Master with Auto adds its "magic sprinkles" and can reach GB5 MT 1900 out of the box.
The Unify-X needs telemetry to do the same; I wouldn't call it a coincidence 
I preferer to have it under my control.



Veii said:


> Oh something to add
> I've started to fail & fixed y-cruncher again on AGESA 1.2.0.2
> It crashed on my 2nd best core (last one, 10/11)
> It was running +60mV, LLC 3/5 (5=most droop) @ -28 CO
> The reason for the crash on N32/N64/VST ~ was overvoltage & package throttle
> Lowering CO, to -30 fixed it
> 
> Soo it can also crash because of overvoltage & not only "lack of voltage"


I had a lot of problems with CO in 1.2.0.1 
My quite safe counts config started failing also on OCCT.
Indeed some cores can also crash for overvolting, usually above 1.4V.
It's more rare than crash for undervolting.
Also cause when you relax the count the frequency goes down and the voltage at some point settle to a max value.

But seems to me this latest AGESA, maybe it's the dLDO injection, is acting quite differently.
There's less "intelligence" and it acts in a quite bizarre way sometimes.
I don't remember I've seen previously a decrease in voltage reducing the negative count before; now it happens quite frequently.

This is just one of the examples but it did happen a lot of times:

# Core EffC VID CO
# 8 4893 *1.393* *24* < _23_ 4849 _1.385_ < 22 4867 1.382

Reducing CO pushed to core VID from about 1.380V to about 1.400V.
Also the dependency from other counts has increased and while before had a more huge impact on frequency now also on voltage.
It can be in excess of 20mV which is 4 to 6 counts.



Veii said:


> It's the limit which you will max out at y-crunche and stay at the same peak EDC % , under snapshot pooling mode (HWInfo)
> OC_Mode bypasses this limit.
> After a certain point SMU won't read any limit higher
> That's the FUSE limit.Telemetry faking allows to work against this
> CO does work internally against it (shift it down), but the limit is a hard limit


Thanks, I'll check with y-cruncher.
From my testing, but it was a lot of time ago, I can go over 220A. Without OC Mode of course.
Which means nothing cause actually the performances are throttled at around 220A.
Hard to say till I move to water cooling, I hit thermal throttling first with anything all core.
y-cruncher sadly hits the limit for me just hovering the icon 

For testing telemetry I've used CPU-z in a range between 14 to 18 threads.
It's the threshold were it hits the EDC limit and I can see if there's a powerbudget change.
Faking SOC from 20A to 0.2A only lead to about 2A of increase in the powerbudget.
Not much but everything is welcome...


----------



## mongoled

Re safe mode.

Its a quick and easy way to get consistent results when testing changes in settings.

As others have mentioned ideally we would like eveyone to be upfront if they used safe mode, but as Veii said there are tell tale signs that safe mode is being used, but many people dont know this, so without safe mode being indicated as being used, peeps who are not aware of the benefits will think there is something wrong with their systems.

As with ManniX-ITA, I also run Kaspersky AV with other services on my "WorkOS" and these services do eat into the L1 latency result, hence the reason many of us use other OSs for comparative results when tweaking just so we can get as consistent results as possible.

Now when benching its a different story as there is always a competitive side to it (yes, some of us are not so much "fulfilled" by this, but others are) hence the reason for peeps looking for some sort of baseline for AIDA64 results of how they are run etc etc so we are all running at the same base lines.

@TimeDrapery
After bumping by 24/7 settings to 1T I am also getting the odd "error 4" error when running TM5, along with an even rarer "error 10".

I first played with RttPark and vDIMM but could not "shake it off" then moved to ProcODT, again no help, now ive moved to vSOC. After adjusting vSOC the error has moved to "Error 14" so looks like there is going to be a combination of settings that need changing.

Y-Cruncher has run happily for over 8 hours without changing anything other than going from 2T to 1T.

Hopefully one us will be able to pinpoint the combination of settings that need changing to get TM5 to play nice



** EDIT **
OK, just seen the new info re "Error 14",
references error 4 and 0 and looks to be all about the changes I made to 3-3-15 to 56-56-56 as the errors seem to be indicating "overall badly timed powerdown"

So onto trying different AddrCmdSetup/CsOdtSetup/CkeSetup first and then possibly different tCKE AddrCmdDrvStr/CsOdtDrvStr/CkeCrvStr values


----------



## ManniX-ITA

Dar|{cyde said:


> I don't have pics of the board, Thaiphoon says they are B1, but general consensus seems to be that the LED boards are all B2 despite what thiaphoon says. It's just fast, expensive B-die, like everyone else is running.


It is definitely a PCB difference.
We have the same board so it can be excluded.
Like everything else I've tested it drops a furious amount of error 0,6.
tRCDRD at 15 drops random errors, mostly 10 and 2 at start, at 16 works perfectly.
Same pattern with any other kind of timings and voltages at CL14.


----------



## danakin

thanks @Veii

semms flat 14s is unstable for me.

im running this at the moment:










and again the question: where can go from here ?

55,1 latency is meeh 🙃 

also i run my 5950x at stock no PBO. (does latency go down if i enable pbo?

best regards,

pete


----------



## RonLazer

danakin said:


> thanks @Veii
> 
> semms flat 14s is unstable for me.
> 
> im running this at the moment:
> 
> View attachment 2489848
> 
> 
> and again the question: where can go from here ?
> 
> 55,1 latency is meeh 🙃
> 
> also i run my 5950x at stock no PBO. (does latency go down if i enable pbo?
> 
> best regards,
> 
> pete


You need to drop your CCD voltage to 0.95, IOD to 1.05, VDDP to 0.9.

tWTRL can be run at 8 instead, that usually boosts latency. I'm also quite surprised you can't run tCL at 14 with that much voltage. 

Otherwise 55ns is perfectly fine, you won't be memory bottlenecked in any game or application and unless you're just hunting for better scores that's the goal isn't it?


----------



## Veii

danakin said:


> and again the question: where can go from here ?


Google for an aida64 key, if you can not afford it right now. But pay up to them if you plan to use it more frequently 
You misstyped tRFC 4
















ClkDrvStr 40 or 60ohm (first CAD_BUS value)

Don't enable PBO yet
You need full L3 cache readouts and latency readouts & a lot of work with CurveOptimizer. Don't touch it yet
SOC has to be GET 1.1v
I misstyped and remade the Picture
You want to set SOC in the bios generally a bit higher - soo with a loadline it drops to 1.1v flat while running TM5
a GET value
cLDO_VDDP & VDDG are SET values in the bios
RTTs are surprisingly decent ~ only RTT_NOM /7 needs a bit higher starting voltage - beyond 1.48, but you can lower VDIMM later too after you know 15-15 flat , runs
With lower than 1.48vDIMM, it's better to disable RTT_NOM fully
RTT_WR does all the "balancing" job already ~ it needs only one , PARK or NOM ~ unless higher than 1.48v is supplied (well higher than 1.51v)


----------



## ManniX-ITA

RonLazer said:


> You need to drop your CCD voltage to 0.95, IOD to 1.05, VDDP to 0.9.


VDDG IOD at 1050 is too high for that VSOC with weak LLC.
In theory the delta should be 50mV but I had stability issues with such a razor thin margin.
Keeping it at 60mV at least is bulletproof.
Due to LLC VSOC runs in idle at 1.08V and 30mV split creates instability.
Which means system lagging, USB issues, audio crackling and in some cases random reboots when a single core is boosting from idle.

The 5950x needs more CCD voltage usually, depends on the sample.
Mine works perfectly fine at 950mV but it's slow with some workloads.
Best way to detect the right voltage for me is Geekbench5.
The single thread tests will show some big drops if CCD voltage is not enough.
For me run at 1000 means more than 500 points in AES-XTS.



RonLazer said:


> tWTRL can be run at 8 instead, that usually boosts latency.


Didn't know that, to which other timing(s) is related?


----------



## Veii

ManniX-ITA said:


> In theory the delta should be 50mV


40mV 
50mV is Matisse
VDDG CCD needs no delta to cLDO_VDDP. It can be the same value - but that's a Vermeer only thing
IOD and SOC scale from procODT and FCLK


----------



## ManniX-ITA

Veii said:


> IOD and SOC scale from procODT and FCLK


From ProcODT how?
Guess higher needs higher VSOC?



Veii said:


> 40mV
> 50mV is Matisse


Ops I must have missed that 
I have tested with the 5950x and it needs 60mV delta for stability.
Tried to "cheat" to keep VSOC at 1.1V to reduce WHEA errors and at 50mV got still some random stability issues.


----------



## ManniX-ITA

Also you need high VSOC if you want to maximize CO counts.
CoreCycler SSE fails on good cores boosting high on my Unify-X
I either need 1.2V LLC3 or 1.175V LLC2 (which is what I'm running now).


----------



## jomama22

Veii said:


> I've noticed on my abstract dual CCD 5600X, that an allcore (aside from dying fully after a certain range ~ because of the 2nd bad CCD) *
> * soo on an allcore @ 1st CCD @ only the "free" cores and not the "not so great disabled 2 cores on the first CCD"
> An allcore, lead to worse L3 access time (by 0.1ns) and around 30-40GB/s less maximum L3 cache
> Often it was more than that, but fixing only the correct cores ~ got it down to around 5? %
> 
> This is important when we talk about CTR usage & why i don't use the 5ghz allcore option from CTR - but still prefer my 4.85 PBO
> 
> This is a paradox
> Grab Autoruns for Windows - Windows Sysinternals and admin-open the 64.exe
> Pre & = 20H2 (pre final H2 update) ~ there where around 30 active services & autostart + shedule task "services"
> Now if we upgrade to finally 20H2 or even 21H1 (which usually runs great if you don't upgrade but clean install)
> The list changes, you have "access" to everything (except that on some things you fully lose all permissions as Administrator)
> but the options change from 30 , to 100+ autostart services ~ split option by option by option. For every little tiny thing
> 
> Now if we compare a stock enterprise, vs a stock home, vs a re-modded Home → ProWorkstation
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - DrEmpiricism/ConvertTo-PfW: Windows 10 Home to Windows 10 Pro for Workstations converter.
> 
> 
> Windows 10 Home to Windows 10 Pro for Workstations converter. - GitHub - DrEmpiricism/ConvertTo-PfW: Windows 10 Home to Windows 10 Pro for Workstations converter.
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> With it's slightly different task sheduler
> The "stock" OS changes again. As a Pay-to-be-spy-free, Microsoft DLC (199$ i think was the "Pro for Workstation" DLC)
> 
> We can't compare this. But we can't also judge Home vs Enterprise vs ProWorkstation DLC
> I don't think we should focus our blame in the users wallet size & which OS they run.
> 
> But for example not accepting SafeMode results, is something we maybe could do
> It would be even better, if we set a standart & registry fix that not only disables the "correct" services without affecting any daily usage (no benchOS)
> And likely also start to fill out another thread for which of these 120+ new autoruns should be disabled for every "gamer" & "PC user"
> Agreeing on this would resolve this paradox - or we ignore the paradox & accept that everyone will abuse it to their extend of knowledge
> 
> 
> Spoiler: Illustration & Comparison [TaskManager]
> 
> 
> 
> 21H1 "fixed" yet still bad / RAM usage is higher
> 
> 
> 
> 
> 
> 
> 
> 
> 69 Processes ~ 620ish Threads are the goal
> I lost the picture, seems like
> - but here is an illustration how "bad" it can look
> That "amount" exists at least 4* more.
> Over 100+ active ones
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Unsure if the big linked answer was red , but it lists maximum EDC boost limits & lists the current artifical FUSE limit at this date
> The only way to bypass it, is to support one of the 3? developers who rework the boosting system with their WIP OC-Tools
> I think it's Mannix-ITA, 1usmus & maybe IrusanovBG
> 
> The problem falls back to an NDA
> Either they have or don't have the needed information
> If they _requested _it, then talking about this topic is prohibited ~ even mentioning or answering about it
> Telemetry faking is what couple of boards already do. Some with public settings, others on Auto Settings ~ 3rd ones without even listing them as options
> It's good that the 5950X finally gets an uplift over the 200A one they shared with the 5900X.
> The only reason to extend PBO limits - is to lift some internal limiters.
> The major internal limiters will remain active and limit it ~ or even package throttle it on overcurrent (loss of perf)
> 
> But potential package throttle, is better than intentional throttle by a lack of remain power-budget.
> I wish i could telemetry fake it a bit
> FCLK & SOC take a too strong hit on my powerbudget. 1/3rd of it
> * or figure out how to reprogram the OPN number
> ==================
> Oh something to add
> I've started to fail & fixed y-cruncher again on AGESA 1.2.0.2
> It crashed on my 2nd best core (last one, 10/11)
> It was running +60mV, LLC 3/5 (5=most droop) @ -28 CO
> The reason for the crash on N32/N64/VST ~ was overvoltage & package throttle
> Lowering CO, to -30 fixed it
> 
> Soo it can also crash because of overvoltage & not only "lack of voltage"


I think you misunderstood me. 

I am for using safemode, just that it probably should be denoted in that spreadsheet. Wasn't trying to make a kerfuffle out of it lol.


----------



## danakin

Veii said:


> Google for an aida64 key, if you can not afford it right now. But pay up to them if you plan to use it more frequently
> You misstyped tRFC 4
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ClkDrvStr 40 or 60ohm (first CAD_BUS value)
> 
> Don't enable PBO yet
> You need full L3 cache readouts and latency readouts & a lot of work with CurveOptimizer. Don't touch it yet
> SOC has to be GET 1.1v
> I misstyped and remade the Picture
> You want to set SOC in the bios generally a bit higher - soo with a loadline it drops to 1.1v flat while running TM5
> a GET value
> cLDO_VDDP & VDDG are SET values in the bios
> RTTs are surprisingly decent ~ only RTT_NOM /7 needs a bit higher starting voltage - beyond 1.48, but you can lower VDIMM later too after you know 15-15 flat , runs
> With lower than 1.48vDIMM, it's better to disable RTT_NOM fully
> RTT_WR does all the "balancing" job already ~ it needs only one , PARK or NOM ~ unless higher than 1.48v is supplied (well higher than 1.51v)


thanks buddy i will try that when i am at home


----------



## Veii

ManniX-ITA said:


> From ProcODT how?
> Guess higher needs higher VSOC?


Only low SOC allows low procODT to work
and high procODT requires high SOC
they have min and max ranges (SOC) up to procODT state

procODT state depends then on dimm amount and ClkDrvStr


----------



## domdtxdissar

Well in my 51.2ns entry i clearly write its done in safemode under the "proof" tab.


http://imgur.com/a/PNZBEGD


And i did just get a 0.2ns difference between safemode and my everyday bloated windows.

Would say very few people takes the time to make a "bench-only" OS install, and for all others safemode is the best option.. If Veii cant cherry-pick the numbers in each tab by running them one-by-one that is just tough luck. (yes i know i have attitude about this, but that is because a certain someone was campaign for my results to get removed from the spreadsheet)


----------



## Yviena

@Veii Do you know what's the recommend RTT settings now for 4x8 SR on 1201+ AGESA?


----------



## ManniX-ITA

domdtxdissar said:


> And i did just get a 0.2ns difference between safemode and my everyday bloated windows.


I'd really like to know how you can go below 54ns 
I tried but not matter what at 3800 MHz it doesn't...

Don't see any change in latency in Safe Mode.



Veii said:


> Only low SOC allows low procODT to work


Thanks for the info, I didn't see that.


----------



## domdtxdissar

ManniX-ITA said:


> I'd really like to know how you can go below 54ns
> I tried but not matter what at 3800 MHz it doesn't...
> 
> Don't see any change in latency in Safe Mode.


Bios 3003 for Asus (agesa 1.1.8.0)
Its ~0.8ns lower latency compared to the newer agesa's)

*jomama22 *is getting same results..
(do notice our L3 latency numbers = effective singlecore speed at or above 5.2ghz)



jomama22 said:


> Again, it is easy for us to understand that as it's somthing we deal with and know. But for those who don't mess with this stuff often, I can easily see it being overlooked.
> 
> I personally havn't had the issue of aida not boosting fully when running individual tests as opposed to running the whole suite. Just today when messing around with 1ccd and letting boost hit 5200, I was able to get 51.2ns @ 3800/1900 14-14-14-28-39 32gb/DR and a L3 latency of 9.7ns. I clicked each box individually for this. The L3 bandwidth is low because of me setting 140 for EDC (was set for when I use dynamic OC switcher, and being on agesa 1.1.8.0).
> View attachment 2489810
> 
> 
> This may come down to the whole 'aida using core 0' thing as core 0 is my best core.
> 
> Also a fun fact: I have discovered that All-core oc's affect 1 CCD chips (at least 5690/5800's with 1 actual CCD) differently than 2 CCD chips interms of memory latency.
> 
> On the 2CCD variants, an all-core OC will ALWAYS produce lower memory latencies than PBO.
> 
> Meanwhile, on 1CCD variants, the reverse is true. It seems that 1CCD variants will infact rely on PBO boost clocks to determine some part of the memory latency.
> 
> My evidence for this is as follows:
> Memory 3800cl14-14-14-28-39 32GB/DR
> 1CCD:
> All-core @4.8ghz: 51.9-52.0ns
> [email protected] boost: 51.2ns
> 2CCD:
> All-core @4.8: 51.9-52.0ns
> [email protected] boost: 52.5ns
> 
> So somthing is definitely going on between 1CCD and 2CCD chips in this case.
> 
> I should note the results are the same with c-states/d states enabled or disabled. Also, smt disabled will make all-core scores worse, I did not test this with pbo.
> 
> Also want to add these were at 2T rate. Also, 2T was much more difficult for me to run on a full 16 cores (2 ccd's) than 8 cores (1 ccd).


----------



## PJVol

Veii said:


> That's the FUSE limit.Telemetry faking allows to work against this
> CO does work internally against it (shift it down), but the limit is a programmed hard limit


You know what? Just fiddled with "CPU telemetry Current scale" and tried to find out if pbo limits affects power reporting accuracy (turned out not)
But accidentally discovered that AIDA memory latency is affected. Just tested with 140 and 350 amps EDC.
The later gives me my usual 52.0 - 52.1 ns, but no way in hell I can get below 52.3 - 52.4 with the 140A EDC.
Before that, I thought it just worsen the L3 cache b/w and latency in the same test and thats it.
Found it strange, given that both tested edc values well beyond "fused" aka "hidden hardcoded" one.


----------



## jomama22

PJVol said:


> You know what? Just fiddled with telemetry Current scale and tried to find if pbo limits affects power reporting accuracy (turned out not)
> But accidentally find out that EDC limit affects AIDA memory latency. Just tested with 140 and 350 amps.
> The later gives me my usual 52.0 - 52.1 ns, but no way in hell I can get below 52.3 - 52.4 with the 140A EDC.
> Before that, I thought its only affect the L3 cache b/w and latency in the same test, given that both edc values well beyond "fused" aka "hidden hardcoded" one.


I didn't run into this issue personally in my testing yesterday when running the 5950x in single ccd mode, had same latency whether it was 140 or 245. Boosting behavior definitely affects memory latency though on single ccd chips. 

It's possible that, as others have said, aida favors core 0 (thread 0 and 1) and if that's not your primary boost core (and you're running in safemode so cppc isn't doing its thing) you will be getting less boost with the lower edc.

My #1 core on my 5950x is core 0, so possibly why I don't see any difference.


----------



## Veii

PJVol said:


> Found it strange, given that both tested edc values well beyond "fused" aka "hidden hardcoded" one.


Thought it was understood and clear :/
Glad you figured it out yourself too

CPU will package throttle internally anyways down to the fuse limit
but Cache will thank you and a suspending powerplan will thank you with how far they can stretch before being stopped internally
Aida does a tiny allcore spike - but it also tests each core individually (on the mem latency test)
Soo 5950X take around 40? sec , 5600X takes about 12-15sec to complete. The difference is quite noticable with dual active CCDs

There is a fuse limit and other dynamic boost limits
And why again, i do recommend to max out EDC - and control the excessive voltage you get, with negative CO
just enabling PBO - does push "a lot more" vcore ~ and not having EDC as the allcore limiter, doesn't help the whole situation


Spoiler: Offtopic ~ just arrived & it has telemetry faking and fMAX












If dual Intel 2.5gbit doesn't WHEA (hopefully also TB4 doesn't), i might switch boards lol ~ we'll see
Has flashback, soo i can finally experiment a bit more - without having to deal with miniSPI 1.28mm headers





domdtxdissar said:


> . If @Veii cant cherry-pick the numbers in each tab by running them one-by-one that is just tough luck. (yes i know i have attitude about this, but that is because a certain someone was campaign for my results to get removed from the spreadsheet)


Not that cherry picked, first Aida64 result you can trow away
2nd has functioning powermanagement and soo also suspended cores
I only "wait" a bit, before testing and run it twice
If i "cherry pick" each option alone , it won't reach peak boost and be slower (the ramp up time is slower, than pressing "start tests" and you lose 0.2-0.3ns that way)
Don't use the shared BenchOS here either

I'm just playing fair to the old rules on the sheet, before it blew up
There is no one that is pinpoint targeted 
The opposite !
I'm really happy that people finally come & beat the 3800MT/s score and generally the average successive result, moves in the 50.1ns region
Meaning, my intention of pushing limits further up and (teaching) the community as a whole ~ is succesfull
There is no other intention, except mocking people a bit who do halfhearted work or give up too fast
And setting a high baseline + pushing up again a bit further ~ was within good intention.
I don't like XOC at all & it doesn't bring neither me, nor the community anything

At the end, the whole OC community improved & we showed AMD that it's a bad idea to FCLK lock it again at 1900Mhz ~ and that's all that matters. 
Bringing the Zen community forward


----------



## PJVol

Veii said:


> If dual Intel 2.5gbit doesn't WHEA


Do you mean those WHEA ID 20's which spits in Windows > Kernel-WHEA log in hundreds as if they were thresholded in MCA_MISCxx ?
btw, what IC's asus use in proarts' VRM implementation ?


----------



## ManniX-ITA

Veii said:


> Aida does a tiny allcore spike - but it also tests each core individually (on the mem latency test)
> Soo 5950X take around 40? sec , 5600X takes about 12-15sec to complete. The difference is quite noticable with dual active CCDs


I don't see that on my 5950x... bandwidth test has an increasing CPU/cores utilization, hacksaw style, up to 100%.
It does indeed run in half the time when I'm in single CCD mode.
The latency test runs steady for 10 seconds on Core 0 (AIDA doesn't care about CPPC priorities).
I there's an all-core test must be very brief, matters of milliseconds or less.
Or maybe it's not being seen cause of the kernel driver but seems weird to me.



domdtxdissar said:


> Bios 3003 for Asus (agesa 1.1.8.0)
> Its ~0.8ns lower latency compared to the newer agesa's)


Think I have a Unify-X BIOS with AGESA 1.1.8.0 and no wonders on latency.
So sad


----------



## jomama22

ManniX-ITA said:


> I don't see that on my 5950x... bandwidth test has an increasing CPU/cores utilization, hacksaw style, up to 100%.
> It does indeed run in half the time when I'm in single CCD mode.
> The latency test runs steady for 10 seconds on Core 0 (AIDA doesn't care about CPPC priorities).
> I there's an all-core test must be very brief, matters of milliseconds or less.
> Or maybe it's not being seen cause of the kernel driver but seems weird to me.
> 
> 
> 
> Think I have a Unify-X BIOS with AGESA 1.1.8.0 and no wonders on latency.
> So sad


You may want to try a patch C variant then. 

On the DH, anything beyond 1.1.8.0 gets around a .7-.8ns latency penalty. 

Should also note that the msi ace I have would run around .3ns slower than the DH with the exact same ram settings.


----------



## ManniX-ITA

jomama22 said:


> You may want to try a patch C variant then.
> 
> On the DH, anything beyond 1.1.8.0 gets around a .7-.8ns latency penalty.
> 
> Should also note that the msi ace I have would run around .3ns slower than the DH with the exact same ram settings.


There's not much choice of decent BIOS releases on the Unify-X.
The bugs makes highly uncomfortable to switch release.

I had all sorts of different combination on the AORUS Master but even there no one that can decrease the latency more than 0.1ns.
Thanks for the info!


----------



## craxton

Sleepycat said:


> You need to update to a newer version of Zentimings so that it can read your CCX count.


Will do later today had not checked for an update in sometime


----------



## danakin

@Veii









forgot to enable BGS, what is it for ?
vsoc is at flat 1.100 when TM5 is running.
why does the MB say vdimm is at 1,52x volt, when i enter 1,5v ?

im pretty happy with that result, but again, where can i go from here ?
14s with the same trfc ? maybe voltage was not enough before.
im a little afraid when i enter 1,51 volts (thats why its at 1,50), since the number turns red than... 🙃
best regards and thanks for help everybody!


edit: for some reason zentimings shows BGS as disabled even when i enable it (?)

regards,

pete


----------



## Dar|{cyde

danakin said:


> forgot to enable BGS, what is it for ?


You can only have BGS or BGS Alt, not both.





__





Sign In to AMD Community - AMD Community


Join AMD Community, a forum for members to discuss the hottest AMD topics or stop by to read the latest blogs & news about all things AMD. Check it out!




community.amd.com





I haven't seen much info on BGS Alt, but supposedly it's good for both benches (Aida) and gaming.


----------



## TimeDrapery

@ManniX-ITA 

Now I'm getting somewhere... For me, the errors appeared to resolve when I adjusted my RTTs so I'm imagining this is a powering issue pertaining primarily to resistances

You find anything new for you and your progress?


----------



## domdtxdissar

mongoled said:


> You post has erked me!
> 
> At best its naive.
> 
> There is no "myth" regards flat 14s, there is only statistical data.
> 
> The statistical data we have seen shows that flat 14s at 3800/1900 is not a commonly achievable result.
> 
> Statistical data in this context is posts on the Internet at various forums, Reddit and other resources that clearly show this.
> 
> Be it 2 x 16GB, 2 x 8GB or 4 x 8GB, the number of people able to get stable flat 14s are very few, that you happen to have some modules that can do it does not mean all module can do this!
> 
> So your "no idea" where the myth comes from is just ugh.


i'm working on it and trying to stabilize 
dual CCD 5950x with 4x8gigs sticks

tRCDRD 14 was only possible after i binned my memory sticks..


----------



## DeletedMember558271

domdtxdissar said:


> Well in my 51.2ns entry i clearly write its done in safemode under the "proof" tab.
> 
> 
> http://imgur.com/a/PNZBEGD
> 
> 
> And i did just get a 0.2ns difference between safemode and my everyday bloated windows.
> 
> Would say very few people takes the time to make a "bench-only" OS install, and for all others safemode is the best option.. If Veii cant cherry-pick the numbers in each tab by running them one-by-one that is just tough luck. (yes i know i have attitude about this, but that is because a certain someone was campaign for my results to get removed from the spreadsheet)


I was wondering why since you're only at 1900 when there's plenty of WHEA filled bullshit on the sheet, but maybe there should be an asterisk + note or something on your best result where it says 5950x since you're running only 1 CCD. I know it's in the image but people don't see that right away when they're just quickly sorting and comparing.

Otherwise idk what the problem is, you may as well have just slotted in a temporary 5800x if you had one that's basically all you did


----------



## domdtxdissar

Dreamic said:


> I was wondering why since you're only at 1900 when there's plenty of WHEA filled bullshit on the sheet, but maybe there should be an asterisk + note or something on your best result where it says 5950x since you're running only 1 CCD. I know it's in the image but people don't see that right away when they're just quickly sorting and comparing.
> 
> Otherwise idk what the problem is, you may as well have just slotted in a temporary 5800x if you had one that's basically all you did


Dont think i can change my entry on that document after the owner have "locked it".
My dual rank flat 14 is still going strong after one hour 








This is how i tested and binned my 4 memory sticks in the different channels:
1-2-3-4
2-1-4-3
3-1-4-2
4-2-1-3
1-3-2-4
2-1-3-4
It took some time to test all these combinations, but in the end the "1-3-2-4" setup was the best layout which allowed me to run these new timings

*edit
failed after 1hour and 15 min 
single error 2

*edit2
quick memtest in dram calc is easy







Back to 25 cycle TM 1umus..


----------



## KedarWolf

*The CL16 4000 almost $100 cheaper and only 1.4v vs 1.5v for the CL14 3800, so the 4000 might be higher binned I'm thinking.*

Edit: Both are b-die.









G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4000 (PC4 32000) Desktop Memory Model F4-4000C16D-32GTZNA - Newegg.com


Buy G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4000 (PC4 32000) Desktop Memory Model F4-4000C16D-32GTZNA with fast shipping and top-rated customer service. Once you know, you Newegg!




www.newegg.ca





*G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 4000 (PC4 32000) Intel XMP 2.0 Desktop Memory Model F4-4000C16D-32GTZNA *

_DDR4 4000 (PC4 32000)_
_Timing 16-16-16-36_
_CAS Latency 16_
_Voltage 1.40V_



_*or*_









G.SKILL Trident Z Neo Series 32GB (2 x 16GB) DDR4 3800 (PC4 30400) Desktop Memory Model F4-3800C14D-32GTZN - Newegg.com


Buy G.SKILL Trident Z Neo Series 32GB (2 x 16GB) DDR4 3800 (PC4 30400) Desktop Memory Model F4-3800C14D-32GTZN with fast shipping and top-rated customer service. Once you know, you Newegg!




www.newegg.ca





_*G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 3800 (PC4 30400) Desktop Memory Model F4-3800C14D-32GTZN*_


_DDR4 3800 (PC4 30400)_
_Timing 14-16-16-36_
_CAS Latency 14_
_Voltage 1.50V_


----------



## ManniX-ITA

TimeDrapery said:


> Now I'm getting somewhere... For me, the errors appeared to resolve when I adjusted my RTTs so I'm imagining this is a powering issue pertaining primarily to resistances


I'm slowly trying to make a 2T profile that runs almost the same as the 1T with setup timings now.

But I'm wasting most of my time calibrating the CO counts right now...
Found out Scalar above 6x with this new AGESA has an impact on how negative you can go with the count, exactly 2 counts.
But at 10x with higher counts is a bit faster; I'm still in the middle of the testing session


----------



## KedarWolf

ManniX-ITA said:


> I'm slowly trying to make a 2T profile that runs almost the same as the 1T with setup timings now.
> 
> But I'm wasting most of my time calibrating the CO counts right now...
> Found out Scalar above 6x with this new AGESA has an impact on how negative you can go with the count, exactly 2 counts.
> But at 10x with higher counts is a bit faster; I'm still in the middle of the testing session


Edit: I did better in multicore* R23* with 150 boost vs 200 boost, running Scaler 10, by 100 points too.


----------



## ManniX-ITA

KedarWolf said:


> Edit: I did better in multicore* R23* with 150 boost vs 200 boost, running Scaler 10, by 100 points too.


Since my cooling is a bit undersized, I use 125 MHz boost.
Works better but I have to check with the new CO counts.

Maybe you could test as well if with Scalar 6x you can drop a couple of counts more on CO.
I got more or less same results with CB R23 and Geekbench5 but 150 points more in CB R21.
Not sure yet how reliable are the scores though.
My best core in CPU-z scores 702 with Scalar 10x and 699 with Scalar 6x and 2 counts less.
It's really head to head, have to run more benchmarks.

In the meantime I've ordered the Ripjaws, should come before Saturday in theory.


----------



## TimeDrapery

ManniX-ITA said:


> Spoiler
> 
> 
> 
> I'm slowly trying to make a 2T profile that runs almost the same as the 1T with setup timings now.
> 
> But I'm wasting most of my time calibrating the CO counts right now...
> Found out Scalar above 6x with this new AGESA has an impact on how negative you can go with the count, exactly 2 counts.
> But at 10x with higher counts is a bit faster; I'm still in the middle of the testing session


Righteous! What are you seeing performance-wise, relative to your 1T set with setup timings, so far?








As you can see, my latest efforts produced another lone... ERRRRRORRRRR #4 😂😂😂😂😂

Oh well, try, try, try again...
















That's very interesting about the CO/scalar behavior changing up with the latest and greatest AGESA release... What do you think that says about how the FIT/SMU has changed with this AGESA? How's throttling compared to prior versions?


----------



## ManniX-ITA

TimeDrapery said:


> Righteous! What are you seeing performance-wise, relative to your 1T set with setup timings, so far?












Need a bit more write bandwidth to feel in peace. Not that is really that useful but...
Latency is extremely stable and RTT mild.
I want to check if I can go a bit lower with tRFC with same or higher VDIMM.
Or if I can keep it as it is and go lower.













TimeDrapery said:


> As you can see, my latest efforts produced another lone... ERRRRRORRRRR #4


It's becoming a regular 



TimeDrapery said:


> That's very interesting about the CO/scalar behavior changing up with the latest and greatest AGESA release... What do you think that says about how the FIT/SMU has changed with this AGESA? How's throttling compared to prior versions?


I'd say there's less throttling which makes it better if you have good cooling.
But also less throttling on its own and hence more difficult if you don't.
It's not really about FIT/SMU but more about the how PBO boosts with single threaded workload.


----------



## KedarWolf

ManniX-ITA said:


> Since my cooling is a bit undersized, I use 125 MHz boost.
> Works better but I have to check with the new CO counts.
> 
> Maybe you could test as well if with Scalar 6x you can drop a couple of counts more on CO.
> I got more or less same results with CB R23 and Geekbench5 but 150 points more in CB R21.
> Not sure yet how reliable are the scores though.
> My best core in CPU-z scores 702 with Scalar 10x and 699 with Scalar 6x and 2 counts less.
> It's really head to head, have to run more benchmarks.
> 
> In the meantime I've ordered the Ripjaws, should come before Saturday in theory.


Oh, I'm still on A210 BIOS, I found the A24 hurt me performance-wise and I like all the unlocked options on A210.


----------



## ManniX-ITA

KedarWolf said:


> Oh, I'm still on A210 BIOS, I found the A24 hurt me performance-wise and I like all the unlocked options on A210.


Same for me, stayed on the A22 for a while but it doesn't help with USB randomness.
And I missed too much the XOC options.


----------



## jomama22

ManniX-ITA said:


> I'm slowly trying to make a 2T profile that runs almost the same as the 1T with setup timings now.
> 
> But I'm wasting most of my time calibrating the CO counts right now...
> Found out Scalar above 6x with this new AGESA has an impact on how negative you can go with the count, exactly 2 counts.
> But at 10x with higher counts is a bit faster; I'm still in the middle of the testing session


Scaler just shifts what voltage values upwards along the vfcurve during boost. If you don't have good cooling, 10x will end up hurting you because of the increased heat. There is also the increase in power consumption to deal with when doing that as well, so you're pbo budget will be eatin' into.

The different co values people are seeing with different scaler values most likely has to do with the voltages pbo is using depending on what the scalar value is. What inevitably ends up happening is with the lower scaler values, you aren't reaching the higher v/f points on the curve, so you can be more aggressive with the CO value (more negative) since it is much easier to undervolt the lower the voltage you go (which is exactly how the CO curve works, for this reason).

With the higher scalar values, you will have in increase CO values (less negative) as you are now using higher voltage bins which will be way more sensitive to undervolting.

It also explains why some may be able to use higher fmax settings with lower scalar values as pbo won't be reaching to those boost clocks nearly as much except for quick, lightweight loads.


----------



## domdtxdissar

Wish me luck 
Dual CCD running 4x memory sticks at 1900fclock *T1 gdm disabled* with flat CL14 timings + tRFC 240








Never had that high memory read numbers @ 1900:3800..
Going to bed now, wonder how many red errors i will see after 25 cycle tomorrow =7


----------



## TimeDrapery

ManniX-ITA said:


> Spoiler
> 
> 
> 
> 
> View attachment 2489936
> 
> 
> Need a bit more write bandwidth to feel in peace. Not that is really that useful but...
> Latency is extremely stable and RTT mild.
> I want to check if I can go a bit lower with tRFC with same or higher VDIMM.
> Or if I can keep it as it is and go lower.
> 
> View attachment 2489937
> 
> 
> 
> 
> 
> It's becoming a regular
> 
> 
> 
> I'd say there's less throttling which makes it better if you have good cooling.
> But also less throttling on its own and hence more difficult if you don't.
> It's not really about FIT/SMU but more about the how PBO boosts with single threaded workload.


Dude, the performance you get from your setup is awesome... Not too much longer until I'll go to Zen 3 now, I'm really looking forward to the switch! I'm also looking forward to see further results from you!

It is becoming a regular, this go-round I've made it past the duration tested where it appeared during the last iteration... Happy enough with that so long as I didn't simply delay its arrival 😂😂😂😂😂








Aha, I see... It's good to hear that AGESA development is actively bring driven forward by AMD rather than languishing as it seemed to in times past (even though there was plenty to work on/with)!


----------



## lmfodor

KedarWolf said:


> *The CL16 4000 almost $100 cheaper and only 1.4v vs 1.5v for the CL14 3800, so the 4000 might be higher binned I'm thinking.*
> 
> Edit: Both are b-die.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4000 (PC4 32000) Desktop Memory Model F4-4000C16D-32GTZNA - Newegg.com
> 
> 
> Buy G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4000 (PC4 32000) Desktop Memory Model F4-4000C16D-32GTZNA with fast shipping and top-rated customer service. Once you know, you Newegg!
> 
> 
> 
> 
> www.newegg.ca
> 
> 
> 
> 
> 
> *G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 4000 (PC4 32000) Intel XMP 2.0 Desktop Memory Model F4-4000C16D-32GTZNA *
> 
> _DDR4 4000 (PC4 32000)_
> _Timing 16-16-16-36_
> _CAS Latency 16_
> _Voltage 1.40V_
> 
> 
> 
> _*or*_
> 
> 
> 
> 
> 
> 
> 
> 
> 
> G.SKILL Trident Z Neo Series 32GB (2 x 16GB) DDR4 3800 (PC4 30400) Desktop Memory Model F4-3800C14D-32GTZN - Newegg.com
> 
> 
> Buy G.SKILL Trident Z Neo Series 32GB (2 x 16GB) DDR4 3800 (PC4 30400) Desktop Memory Model F4-3800C14D-32GTZN with fast shipping and top-rated customer service. Once you know, you Newegg!
> 
> 
> 
> 
> www.newegg.ca
> 
> 
> 
> 
> 
> _*G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 3800 (PC4 30400) Desktop Memory Model F4-3800C14D-32GTZN*_
> 
> 
> _DDR4 3800 (PC4 30400)_
> _Timing 14-16-16-36_
> _CAS Latency 14_
> _Voltage 1.50V_


Hello @KedarWolf, the second model is the one I have and they are working very well with your times. I'm trying to get 1T, when I could, I got a significant increase in bandwidth and lower latency, but at some point some BSOD came along. But I still haven't tried the "magic" CadBus Setup values 56-56-56? Have you tried it? 

Why would the 4000 be better binned? For the performance I saw here, I don't recommend this model for its price/performance . I would choose a 3600CL14 and save a few bucks or even the same model 3800CL14 but single rank with a lot of headroom for OC


Sent from my iPhone using Tapatalk Pro


----------



## lmfodor

Well, the "Vodoo" thing works  @ManniX-ITA plase tell us how to reach to this setup, I never heard or read about it before.. But now, I'm working with 1T without Wheas nor BSOD.. I will continue testing.. but, pretty amazing. There's some place to read about this CADBUS Setup values? I didn't find anything googling it. what is the rational??

I will match tCWL to TCL so I can lower one CK tRDWR and see if read write performance increase..


----------



## DeletedMember558271

So I think these are my final 1.450v 4x8GB 3733 53.5ns settings, tRCDRD 14 could literally last 3 hours apparently before failing so just bumping up to 1.460v could probably be enough to stabilize it but I don't really want to.















It's always going to bug me that I can't boot 1900 FCLK but unless I buy a new 5800x or motherboard I think it's impossible and I don't know if it's possible to get rid of the 1933+ WHEA either. I don't even know if anyone else with a MSI B550 Tomahawk has 1900 FCLK, I'm sure someone does but it's like nobody owns this motherboard but me, no others with 1900 working to try to copy, assuming they found some magic setting or combination to get it working on this motherboard/BIOS. I feel like I just haven't found the secret but maybe there actually isn't one guess I'll never know


----------



## Yviena

Interesting.... after I updated to 1202 I seem to get 600-630mbps in speed tests, downgrading and I'm back to 510 again.


----------



## mongoled

domdtxdissar said:


> i'm working on it and trying to stabilize
> dual CCD 5950x with 4x8gigs sticks
> 
> tRCDRD 14 was only possible after i binned my memory sticks..
> 
> View attachment 2489922
> 
> View attachment 2489924
> 
> View attachment 2489925


Yup, as mentioned before, to be in with a chance to run 4 x 8GB with [email protected] you need to be fortunate enough to have 4 "good" sticks otherwise you need to go start binning sticks to find the combination that can do it!

Wish you luck in getting there, ive found that if you can get past the first few cycles without throwing an error 0, 10 you have a good chance of getting them stable, the difficulty is finding the right combination of setting to power the DIMMs correctly, simply increasing voltage in this scenario often proves counter productive.

Those settings in your later posts sure look familiar

 



Yviena said:


> Interesting.... after I updated to 1202 I seem to get 600-630mbps in speed tests, downgrading and I'm back to 510 again.


Interesting ....



@ManniX-ITA
How come youve dropped tRDRDSCL/tWRWRSCL to 2 while running 32GB ??

Have you found a way to stop the drop in read bandwidth when compared to 4/5 rather then 2/3 ??


----------



## Danny.ns

Dreamic said:


> It's always going to bug me that I can't boot 1900 FCLK but unless I buy a new 5800x or motherboard I think it's impossible and I don't know if it's possible to get rid of the 1933+ WHEA either. I don't even know if anyone else with a MSI B550 Tomahawk has 1900 FCLK, I'm sure someone does but it's like nobody owns this motherboard but me, no others with 1900 working to try to copy, assuming they found some magic setting or combination to get it working on this motherboard/BIOS. I feel like I just haven't found the secret but maybe there actually isn't one guess I'll never know


It isn't your motherboard. There are plenty of us that can not POST at FCLK 1900, but have no problem POSTing at FCLK 1933, 1966, 2000 etc. Obviously anything 1933+ will spam the event viewer with WHEAs.

I have tried everything, the board (Dark Hero+5900x) will not even try to POST at 1900. 1.4vSOC, 1.3 VDD/VDDG, tried low voltages, LN2 mode. Doesn't matter, it simply refuses to even try.

It is just one of the perks of owning AMD hardware, you get one random surprise bug that will stick with you until you upgrade back to Intel. I should've stuck with my ivy bridge until Intel came out with something decent.


----------



## Veii

danakin said:


> @Veii
> View attachment 2489896
> 
> 
> forgot to enable BGS, what is it for ?
> vsoc is at flat 1.100 when TM5 is running.
> why does the MB say vdimm is at 1,52x volt, when i enter 1,5v ?
> 
> im pretty happy with that result, but again, where can i go from here ?
> 14s with the same trfc ? maybe voltage was not enough before.
> im a little afraid when i enter 1,51 volts (thats why its at 1,50), since the number turns red than... 🙃
> best regards and thanks for help everybody!
> 
> 
> edit: for some reason zentimings shows BGS as disabled even when i enable it (?)
> 
> regards,
> 
> pete


Good job, it's 0.2 down - and you prepared the dimms to run on GDM off
But i am sorry to tell you ~ that TM5's result is only 15-18% worth something
It shows that you don't have a catastrophic failure and likely games would be fine with it
But it doesn't show that you won't thermal throttle, and it doesn't show that predicted tREFI + tRFC range is correct

Knowing you used tRFC mini (well i did for you)








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com




Means, tRFC won't fail after a time
But there is a difference between techical theory and real world results

Soo please either edit the MT.cfg config (inside the /Bin folder) to 25 cycles
Or grab this old reuploaded one, which has 20 cycles preconfigured

In order to actually proof thermal stability, we need to be sure the dimms remain stable @ their highest thermal peak
Which means, either running furmark while TM5 runs (soo the GPU heats it up)
Or letting a TM5 test run beyond 1h
Around 45min is required for dimms to reach Thermal Equilibrium, and around 6 cycles are required to notice and tRFC1 failure
19 cycles are required to notice any tREFI and tCKE failure ~ powerdown and a whole refresh cycle.

Soo because memory can and did often fail the last test of cycle 19, the absolute minimum is 20 cycles
Which is 1:30h for 16gb , or 3h for 32gb sets
Please retest 
Also when using Aida64
Put yourself to High-Performance powerplan, push display poweroff to 2h, system hibernation to disabled & disable USB suspension (advanced powerplan settings, above minimum % powerstate)
This will prevent random DPC calls while TM5 runs and while Aida64 runs
Another advice,
Run Aida64 as soon as possible while the OS loads ,then let it finish
By the time it finishes, the OS will have loaded all their useless services & you can run another one (before TM5 !)
Doing so (after the first Aida64 run which loads it's own Kernel Drivers) ~ it will allow the CPU to start using it's powerstates
Soo the CPU will hibernate fully (if enabled) and the test results will be consistent and peaking up to CPUs capability & settings

If you take the first load, the thread sheduler will pioritize Microsoft "delayed" services and your result will be wrong (L3 especially)
If you run Aida64 after TM5 or with ZenTimings, the ZT kernel and both ZT & TM5's random refresh will do random DPC calls
This eats around 400-600MB/s bandwidth, slows cache down and increases tested latency
Soo to make this as correct and consistent as possible:

run Aida64 asap on OS start
wait a bit , like 10sec ~ the test takes long enough soo useless services will be suspended by the thread scheduler as Aida64's kernel enforces Realtime mode
after the first realtime load, the CPU will forcefully suspend itself (if supported) soo what you test is idle to high perf lantency
Last point might appear slower , but it's as close to reality as possible. The rest are peak boost tests and do not match to normal day-to-day usage. Also can randomly track microsoft service triggers and give a slower or unrealistic unstable result 
OC'ing T-Force 4133 cl18
Post with TM5 20cycles , or edit it yourself


PJVol said:


> btw, what IC's asus use in proarts' VRM implementation ?


It's really "bad" ones from my personal viewpoint.
12+2 Vishay SiC639 , 50A
on a ASP1106-PWM-Controller (rebranded RT3667BE) which only supports 4+2 phase mode

They cheaped out on the PWM controller and had too tripple it up
Soo it's in reality:
4 Phase vCore * 3
1 Phase SOC, one DRAM
They should've used a Renesas one which at least supports 7+1 phases to make this a dual 6 phase board, instead a 4 phase one
VRMs according to 5800X test heat up to 80c ~ but the board has full switching frequency control & phase control + loadline modeling

Potentially i am less inteligent than the ASUS engineers, and their 4 phase option has better ripple ~ but somehow i doubt this
Anywho , i think it's fine ~ but i'd be worried with a 5950X on it.
210A on 100% usage is kiinda peaking the specs-sheet (160A vcore + 50A SOC)
A 5900X stock should be fine, a 5800X stock should also be just borderline fine (5800X OCs itself stronger than a 5900X)
But we'll see how it behaves on my take & if fMAX override does anything to the 5600X 
If it's WHEA hell, then i'll just put a 1200AF or 1700X on it ~ although i'd be worried with a 180A 1700X, haha
(eh it was fine with a B350 Toma peaking 105c ~ this shouldn't be thaat bad 😅)
EDIT:
As we know, peaking the specs sheet doesn't help Ripple at all
a doubled 6 phase potentially would be better (with the option to switch it to full phase , which we can with ASUS's ext volt controller)
~ well not using Vishay 50A stages at all and going rather with 70A or 90A Renesas Mosfets on a 300$ board, would be even better
But hey, i'm neither EVGA engineer, nor have ASUS connections to judge them for this ~ maaybe it's fine. I'll hold back critique till i can verify it myself 
A B350 Tomahawk with a mini 55mm blowimatron, was fine with over 200A load ~ this should not be even close as catastrophic as my 1700X set
Yet the B350 Toma sustained my 3467MT/s C14-14 set ~ soo thermal peaking VRMs don't always have to result in unsable ripple 😋
I'll give it a chance and see how bad it really is, have definately worked with worse things


----------



## kompira

Finally stable ProcODT 48 with [email protected]/s.
CAD BUS Setup format X-0-0 = lower ClkDrvStr/ProcODT/VSOC


Spoiler: [email protected]/s ProcODT48


----------



## Veii

KedarWolf said:


> G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 4000 (PC4 32000) Intel XMP 2.0 Desktop Memory Model F4-4000C16D-32GTZNA


Take the 1.4v one, this one has more potential 


kompira said:


> Finally stable ProcODT 48 with [email protected]/s.
> CAD BUS Setup format X-0-0 = lower ClkDrvStr/ProcODT/VSOC
> 
> 
> Spoiler: [email protected]/s ProcODT48
> 
> 
> 
> 
> View attachment 2489976


Eyy, good job ! 🥳
Use Performance Enhancers on first gen Ryzen
it does help intercore latency and thread sheduling a bit

I think GeekBench/Cine R20 mode was the best one, i need to check my old pics
Anywho - Bravo !


Spoiler: Want to give these timings a test ?



Ignore CAD_BUS & procODT ~ that's IMC firmware related & we know something odd happened and it changed


http://imgur.com/a/YFJRjom

 ~ Gallery Link


I think i have now a target to beat again for the 1700X 🙃
Motivation is certainly there ~ but i have other work to finish ~ F
_Soon maybe~_


----------



## Veii

TimeDrapery said:


> Righteous! What are you seeing performance-wise, relative to your 1T set with setup timings, so far?
> View attachment 2489933
> 
> As you can see, my latest efforts produced another lone... ERRRRRORRRRR #4 😂😂😂😂😂
> 
> Oh well, try, try, try again...
> View attachment 2489934
> 
> View attachment 2489935
> 
> That's very interesting about the CO/scalar behavior changing up with the latest and greatest AGESA release... What do you think that says about how the FIT/SMU has changed with this AGESA? How's throttling compared to prior versions?


Is this SMU on AGESA 1202 (1201++) ?
Error #4 here would be tFAW issues, but i am not very sure what exactly is going on ~ i have that nonsense too since 1201
try tFAW 12 or tFAW 10
It's a bit slower, as it times out - but something along the lines of "newly implemented Burst mode" causes crashes on 4* tFAW ~ for whatever reason
2* tFAW keeps stability up, but it is slightly slower


ManniX-ITA said:


> I want to check if I can go a bit lower with tRFC with same or higher VDIMM.


Want to bother wasting time and get tRP 12 stable ?
Testing if you can run tRP 13 and then down to 12
Logically also adjusting tRC with it


----------



## ManniX-ITA

jomama22 said:


> Scaler just shifts what voltage values upwards along the vfcurve during boost. If you don't have good cooling, 10x will end up hurting you because of the increased heat. There is also the increase in power consumption to deal with when doing that as well, so you're pbo budget will be eatin' into.
> 
> The different co values people are seeing with different scaler values most likely has to do with the voltages pbo is using depending on what the scalar value is. What inevitably ends up happening is with the lower scaler values, you aren't reaching the higher v/f points on the curve, so you can be more aggressive with the CO value (more negative) since it is much easier to undervolt the lower the voltage you go (which is exactly how the CO curve works, for this reason).
> 
> With the higher scalar values, you will have in increase CO values (less negative) as you are now using higher voltage bins which will be way more sensitive to undervolting.
> 
> It also explains why some may be able to use higher fmax settings with lower scalar values as pbo won't be reaching to those boost clocks nearly as much except for quick, lightweight loads.


I have to petition WWF to get the Scalar in the list of endangered species 

That's not what I've experienced with my testing both with the 3800x and the 5950x.
The Scalar is definitely not just a base linear factor for voltage; it's a magnitude factor for the curve.
On the 5950x it has a multiplier factor on the number of loaded cores that brings it down to almost zero with a single core.
With the 3800x had more impact also on single threaded and in all-core workloads.

It does not impact negatively the powerbudget, it's extending it.
Yes it works a bit against the CO negative count but I don't see the issue there.
At least on my 5950x the good cores count is between 13 and 22. The +2 doesn't change anything.
The medium quality cores can run at between 28 and 30 and there too it doesn't change at all.
As you can see from the benchmarks below Scalar 6x versus Scalar 10x with +2 counts are almost equivalent.

Raising the Scalar it's not much about raising the voltage.
A +2 count with Scalar 10x will give you more or less the exact same VID and frequency than Scalar 6x +0 in single thread boost.
The difference is minimal at best and often below the margin of error.
There's a quite substantial, still half what did on the 3000, positive offset of 60-75mV in all-core.
And intuitively you could conclude that this has a negative impact on the powerbudget due to the increased power consumption.
It's a wrong assumption; you need to factor in that to compensate this voltage increase the max temperature allowed before throttling is massively expanded.
That's why, despite the increased power consumption and the fight against undervolting, the Scalar effect wins big time.

Yes there's a huge temperature increase with a high Scalar.
But this is not detrimental to performances, quite the opposite.
You want to get a higher temperature, means the throttling is delayed.

I can score the advantages with my silent air cooler Dark Rock Pro 4; it's probably the worst for a 5950x if you look for performances.
Can only imagine how much bigger is the impact with a decent custom loop.
I'm literally dying to complete my build and compare these results with water cooling at ambient and sub-ambient 

My guess on why the Scalar has a big impact on the 3800x also on ST and MT is because the temperatures are lower (and the architecture quite different).
I'd love to see similar testing on a 5600x/5800x.
Due to my limited cooling I can't see higher performances with single threaded or all-core workloads, it's approaching too fast the thermal limits.

Consider the results below were taken very early this morning starting from 1x.
During the session the ambient temperature went up quite substantially.
When you see a score slightly lower with 10x than 6x consider that is in reality slightly above.










The third column is Scalar 10x at the same counts of 1x and 6x.
Which is not stable with my cooling but you get an idea
The ambient temp was already much higher, 10x can score better with a few degrees less.

Consider that if I would have tried a couple of times CB R23 at 6x I could have get 29300 and over.
With a much lower ambient temp and more aggressive CO counts with 10x Scalar I could top about 29900 in CB R23.
It's a lot for a silent air cooler!

As you can see there's a temp delta of 5-6c from 1x to 6x and 6-9c to 10x.
The ST and MT benchmarks are almost not interesting.
I'm 100% thermally constrained at ST and MT, only a better ambient temp can give me a bump up.

Now the more interesting part, the CPU-z bench with different number of threads.

Running between 8 and 24 threads there's a steady increase in scores.
Whatever it's running below or above the EDC limit at 215A there's always an increase almost linear with Scalar (except some temp issues with 10x, like Tr8).
This means the powerbudget has increased and it's delaying the throttling thanks to a higher thermal constraint point.
It's significant that despite the mediocre cooling I get up to 150 points more in CPU-z.

I'm really surprised that who's running excellent cooling solutions is not a dogmatic enthusiastic fanboy of the high Scalar.
I can only assume nobody is running benchmarks with light to medium threaded workloads.
It's a huge mistake!
If you consider real world usage, that's 99% of your use cases.
Unless you run primarily odds sims or encoding or some other 24h all-core workloads, that's where and when you need more performances.

If you have excellent cooling, give it a go for a 10x Scalar if you think the temperature increase is acceptable.
In any other cases I'd highly recommend 6x; the temp increase is manageable in any case and the performance uplift is not negligible.

Unfortunately the latest AGESA 1.2.x.x made the Scalar less safe to use than before, the cores are crashing earlier.
In single thread boost they get too excited and tend to crash much earlier...
But there's still a wide performance increase gap that can be exploited.



mongoled said:


> @ManniX-ITA
> How come youve dropped tRDRDSCL/tWRWRSCL to 2 while running 32GB ??
> 
> Have you found a way to stop the drop in read bandwidth when compared to 4/5 rather then 2/3 ??


I can run SCL at 2 easily with tRDWR/tWRRD at 10/1.
But this is the first time I can POST with 8/3.
My guess is the right combination of ProcODT/RTT/CAD/VDIMM.
Do note that I'm still working on this profile so it's not TM5 tested for more than 3 rounds!
It could very well be that it's not stable at SCL 2.



domdtxdissar said:


> Dual CCD running 4x memory sticks at 1900fclock *T1 gdm disabled* with flat CL14 timings + tRFC 240


Good luck, it's awesome 



TimeDrapery said:


> Dude, the performance you get from your setup is awesome... Not too much longer until I'll go to Zen 3 now, I'm really looking forward to the switch! I'm also looking forward to see further results from you!


Considering how much I'm illiterate on the topic it's indeed surprising 
Hope you go for a single CCD to minimize latency!



lmfodor said:


> Why would the 4000 be better binned? For the performance I saw here, I don't recommend this model for its price/performance . I would choose a 3600CL14 and save a few bucks or even the same model 3800CL14 but single rank with a lot of headroom for OC


Yes that was better binned for the 1.4V was my assumption as well and I was wrong.
And that the 3800C14 was better binned due to the C14 at 3800 MHz proved wrong as well. It's just more expensive.
From our test results they are virtually identical except the XMP profile.
SR is hardly an option for the Unify-X unless you want to live constrained to 16GB 



lmfodor said:


> Well, the "Vodoo" thing works  @ManniX-ITA plase tell us how to reach to this setup, I never heard or read about before.. But now, I'm working with 1T without Wheas nor BSOD.. I will continue testing.. but, pretty amazing. There's some place to read about this CADBUS Setup values? I didn't find anything googling it. what is the rational??


Sacrilege... where else could be if not in the sacred scrolls?
Columns AA to AC in the Zen 2 Spreadsheet.

Plus I saw a BZ stream with the Unify-X were he tried OC on some kits.
As he says incessantly over the stream, he's not very good in memory OC and doesn't like it.
But the people in the chat literally screamed to him for 1 hour to use setup timings.
He didn't listen to them... but caught my attention.

You can find more technical info in the coolenjoy series tome C:









쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네


출처:https://blog.asset-intertech.com/test_data_out/2014/11/memory-training-testing-and-margining.ht



coolenjoy.net


----------



## kompira

Veii said:


> Eyy, good job ! 🥳
> Use Performance Enhancers on first gen Ryzen
> it does help intercore latency and thread sheduling a bit
> 
> I think GeekBench/Cine R20 mode was the best one, i need to check my old pics
> Anywho - Bravo !
> 
> 
> Spoiler: Want to give these timings a test ?
> 
> 
> 
> Ignore CAD_BUS & procODT ~ that's IMC firmware related & we know something odd happened and it changed
> 
> 
> http://imgur.com/a/YFJRjom
> 
> ~ Gallery Link
> 
> 
> I think i have now a target to beat again for the 1700X 🙃
> Motivation is certainly there ~ but i have other work to finish ~ F
> _Soon maybe~_


Thanks ! Need more work, but when I have time.
I want 1T + ProcODT48 + Setup 1-1-1 (or 1-0-0), hmm will see. With ProcODT 53.3 everything is fine, maybe I should stay with it, but it depends on whether it gives a lower and stable latency.
2T is easy...
By the way, I'm also stable at 3667MT/s GDM or 2T I think this should be the next goal for conquest.


----------



## mongoled

ManniX-ITA said:


> I can run SCL at 2 easily with tRDWR/tWRRD at 10/1.
> But this is the first time I can POST with 8/3.
> My guess is the right combination of ProcODT/RTT/CAD/VDIMM.
> Do note that I'm still working on this profile so it's not TM5 tested for more than 3 rounds!
> It could very well be that it's not stable at SCL 2.


I was refering to the loss in read bandwidth when running SCL 2/3 instead of SCL 4/5, not stability, performance

SCL 2/3 is worse then SCL 4/5 when running 32GB on B-die, was wondering if you found something diffferent .....


----------



## ManniX-ITA

Veii said:


> Want to bother wasting time and get tRP 12 stable ?
> Testing if you can run tRP 13 and then down to 12
> Logically also adjusting tRC with it


Part of testing 
Works fine with tRP at 12, used tRAS at 26.
Not sure but I think I've tested with tRC 40 or 42.

But it was quite unstable with latency and the read bw dropped.
I decided first to look for stable RTT.

What do you suggest to look for tRC?


----------



## ManniX-ITA

mongoled said:


> SCL 2/3 is worse then SCL 4/5 when running 32GB on B-die, was wondering if you found something diffferent .....


Didn't make direct comparison but I can check it out.
So far mostly increase using SCL at 2, no drops.


----------



## mongoled

ManniX-ITA said:


> Didn't make direct comparison but I can check it out.
> So far mostly increase using SCL at 2, no drops.


With 4x8GB, 5600x, using SCL 2/3 instead of 4/5 results in loss of read bandwith around 300-400 MB/s

With 2 x 8GB, the results is reveresed


----------



## Veii

ManniX-ITA said:


> Part of testing
> Works fine with tRP at 12, used tRAS at 26.
> Not sure but I think I've tested with tRC 40 or 42.
> 
> But it was quite unstable with latency and the read bw dropped.
> I decided first to look for stable RTT.
> 
> What do you suggest to look for tRC?
> 
> View attachment 2489989


Same thing, RAS keep identical (tRCD *2 ? or tCL + tRCD + tRCD /3) and tRC remains tRP+tRAS
it can be something else too, but it should be at least tRP+tRAS to follow basic cycling.
Same "basic" like 4* tRRD_S = tFAW has to be basic functioning.

The "basic functioning" changed as it seems ~ or "basic AMD JEDEC" has now different behaviour
But according to JEDEC, this is how it has to function
Even when maaybe all of the 1.3 million cells might not hold that "JEDEC Timing"

Result looks like it lost 200MB/s Read ?
First test & soo testing tolerance, or ?


----------



## RonLazer

I think a lot of the testing of timing changes people do here fails to account for the substantial boot to boot variation in memory performance due to subtle deviations in training parameters during boot.

I can see up to 500mb/s and 0.4ns of variation between boots with identical timings and voltages. Some settings combinations can bring this down somewhat, but ultimately you can't adjust a single timing, compare 2 boots, and draw conclusions about it's effect. You also shouldn't rely on a single benchmark, since some timings will be more impactful in different memory access patterns.

If you really want to know what a timing does then you need to use an aggregated benchmark like Geekbench3 and average 3 runs per boot over 3-4 reboots. Cold-booting from PSU off, booting from shutdown, and software level rebooting will also all significantly alter training behaviour.


----------



## ManniX-ITA

mongoled said:


> With 4x8GB, 5600x, using SCL 2/3 instead of 4/5 results in loss of read bandwith around 300-400 MB/s
> 
> With 2 x 8GB, the results is reveresed


Will test and report, have to first validate the counts cause I got a reboot in idle 
In general you can go from Scalar 10x to 6x and gain two counts but it's a rule of thumb; my worst Core 9 can't, it's either -1 or 0



Veii said:


> Result looks like it lost 200MB/s Read ?
> First test & soo testing tolerance, or ?


Looks like but it was unstable, first test and only ran once 
Once I've verified the counts I'll keep digging


----------



## ManniX-ITA

RonLazer said:


> If you really want to know what a timing does then you need to use an aggregated benchmark like Geekbench3 and average 3 runs per boot over 3-4 reboots. Cold-booting from PSU off, booting from shutdown, and software level rebooting will also all significantly alter training behaviour.


Agree, sometimes I thought the profile was crystal perfect and instead found out after a power cycle that it was just as the one before...
But only reading your list I get an headache 
Guess it's where the experience comes in handy and then you know when it's time to focus the effort on such a big testing cycle.
I'm not even close to that point.


----------



## jomama22

ManniX-ITA said:


> I have to petition WWF to get the Scalar in the list of endangered species
> 
> That's not what I've experienced with my testing both with the 3800x and the 5950x.
> The Scalar is definitely not just a base linear factor for voltage; it's a magnitude factor for the curve.
> On the 5950x it has a multiplier factor on the number of loaded cores that brings it down to almost zero with a single core.
> With the 3800x had more impact also on single threaded and in all-core workloads.
> 
> It does not impact negatively the powerbudget, it's extending it.
> Yes it works a bit against the CO negative count but I don't see the issue there.
> At least on my 5950x the good cores count is between 13 and 22. The +2 doesn't change anything.
> The medium quality cores can run at between 28 and 30 and there too it doesn't change at all.
> As you can see from the benchmarks below Scalar 6x versus Scalar 10x with +2 counts are almost equivalent.
> 
> Raising the Scalar it's not much about raising the voltage.
> A +2 count with Scalar 10x will give you more or less the exact same VID and frequency than Scalar 6x +0 in single thread boost.
> The difference is minimal at best and often below the margin of error.
> There's a quite substantial, still half what did on the 3000, positive offset of 60-75mV in all-core.
> And intuitively you could conclude that this has a negative impact on the powerbudget due to the increased power consumption.
> It's a wrong assumption; you need to factor in that to compensate this voltage increase the max temperature allowed before throttling is massively expanded.
> That's why, despite the increased power consumption and the fight against undervolting, the Scalar effect wins big time.
> 
> Yes there's a huge temperature increase with a high Scalar.
> But this is not detrimental to performances, quite the opposite.
> You want to get a higher temperature, means the throttling is delayed.
> 
> I can score the advantages with my silent air cooler Dark Rock Pro 4; it's probably the worst for a 5950x if you look for performances.
> Can only imagine how much bigger is the impact with a decent custom loop.
> I'm literally dying to complete my build and compare these results with water cooling at ambient and sub-ambient
> 
> My guess on why the Scalar has a big impact on the 3800x also on ST and MT is because the temperatures are lower (and the architecture quite different).
> I'd love to see similar testing on a 5600x/5800x.
> Due to my limited cooling I can't see higher performances with single threaded or all-core workloads, it's approaching too fast the thermal limits.
> 
> Consider the results below were taken very early this morning starting from 1x.
> During the session the ambient temperature went up quite substantially.
> When you see a score slightly lower with 10x than 6x consider that is in reality slightly above.
> 
> View attachment 2489981
> 
> 
> The third column is Scalar 10x at the same counts of 1x and 6x.
> Which is not stable with my cooling but you get an idea
> The ambient temp was already much higher, 10x can score better with a few degrees less.
> 
> Consider that if I would have tried a couple of times CB R23 at 6x I could have get 29300 and over.
> With a much lower ambient temp and more aggressive CO counts with 10x Scalar I could top about 29900 in CB R23.
> It's a lot for a silent air cooler!
> 
> As you can see there's a temp delta of 5-6c from 1x to 6x and 6-9c to 10x.
> The ST and MT benchmarks are almost not interesting.
> I'm 100% thermally constrained at ST and MT, only a better ambient temp can give me a bump up.
> 
> Now the more interesting part, the CPU-z bench with different number of threads.
> 
> Running between 8 and 24 threads there's a steady increase in scores.
> Whatever it's running below or above the EDC limit at 215A there's always an increase almost linear with Scalar (except some temp issues with 10x, like Tr8).
> This means the powerbudget has increased and it's delaying the throttling thanks to a higher thermal constraint point.
> It's significant that despite the mediocre cooling I get up to 150 points more in CPU-z.
> 
> I'm really surprised that who's running excellent cooling solutions is not a dogmatic enthusiastic fanboy of the high Scalar.
> I can only assume nobody is running benchmarks with light to medium threaded workloads.
> It's a huge mistake!
> If you consider real world usage, that's 99% of your use cases.
> Unless you run primarily odds sims or encoding or some other 24h all-core workloads, that's where and when you need more performances.
> 
> If you have excellent cooling, give it a go for a 10x Scalar if you think the temperature increase is acceptable.
> In any other cases I'd highly recommend 6x; the temp increase is manageable in any case and the performance uplift is not negligible.
> 
> Unfortunately the latest AGESA 1.2.x.x made the Scalar less safe to use than before, the cores are crashing earlier.
> In single thread boost they get too excited and tend to crash much earlier...
> But there's still a wide performance increase gap that can be exploited.
> 
> 
> 
> I can run SCL at 2 easily with tRDWR/tWRRD at 10/1.
> But this is the first time I can POST with 8/3.
> My guess is the right combination of ProcODT/RTT/CAD/VDIMM.
> Do note that I'm still working on this profile so it's not TM5 tested for more than 3 rounds!
> It could very well be that it's not stable at SCL 2.
> 
> 
> 
> Good luck, it's awesome
> 
> 
> 
> Considering how much I'm illiterate on the topic it's indeed surprising
> Hope you go for a single CCD to minimize latency!
> 
> 
> 
> Yes that was better binned for the 1.4V was my assumption as well and I was wrong.
> And that the 3800C14 was better binned due to the C14 at 3800 MHz proved wrong as well. It's just more expensive.
> From our test results they are virtually identical except the XMP profile.
> SR is hardly an option for the Unify-X unless you want to live constrained to 16GB
> 
> 
> 
> Sacrilege... where else could be if not in the sacred scrolls?
> Columns AA to AC in the Zen 2 Spreadsheet.
> 
> Plus I saw a BZ stream with the Unify-X were he tried OC on some kits.
> As he says incessantly over the stream, he's not very good in memory OC and doesn't like it.
> But the people in the chat literally screamed to him for 1 hour to use setup timings.
> He didn't listen to them... but caught my attention.
> 
> You can find more technical info in the coolenjoy series tome C:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네
> 
> 
> 출처:https://blog.asset-intertech.com/test_data_out/2014/11/memory-training-testing-and-margining.ht
> 
> 
> 
> coolenjoy.net


Never said there wasn't a benefit to running higher scaler values nor that any specific value was better then the other. That would all depend on your use case, cooling and core quality.

Also never said anything about there being performance loss for different CO values when pertains to scaler, just as to why it is such a thing.

The scaler is just part of the overall pbo algorithm, it is still bound to the power and temperature limits imposed as such. As defined many times, it will stay at higher voltage bins for longer (so long as power and temperature are still within the pbo limits). It's purpose is to essentially trick the pbo algorithm into thinking a cores quality is high than it actually is. In doing so, pbo will go after higher voltages since it believes it can do so within it's temperature and power budget.

I suggest you watch this video by skatterbencher, specific from the 10:10 mark, to see how scaler affects the voltages used by pbo:





I stand by what I said as I never said one way or the other which is better or not, just the affects of using scalers of different values.

To add to this, pbo is much more complex than "I have x temp limit and y power limit, let's just go full throttle until we hit it". It's constantly varying no matter the cooling. PBO has already taken into account the great cooling at 1x scaler, so the baseline performance from such is just raised across ever scaler value. There isn't going to be some dramatic difference between 1x and 10x just because you have good cooling since it's already be taken into account by PBO.

You have to realize that PBO will boost higher and higher on its own the lower temperature you give it. If you put a chiller on a 5950x, for example, it will happily and automatically boost higher no matter the workload.

You still end up with a game of finding the best scalar value for your setup to take advantage of the pbo algorithm.


----------



## craxton

EDIT> if its logging ANY WHEA AT ALL then its working would one not think???
messing with curve caused this....but still nothing shows while in LN2 mode and display cuts out,
wifi doesnt work, mouse in and out....









finally after installing a new OS, while unhooking EVERY drive i had to check for WHEA errors,
i still come up empty...LN2 mode same thing, although errors about my display are reported in error reporting...

anyhow, now, do i have some kind of special "5600x" updated zen timings finally...


----------



## ManniX-ITA

jomama22 said:


> I stand by what I said as I never said one way or the other which is better or not, just the affects of using scalers of different values.





jomama22 said:


> Scaler just shifts what voltage values upwards along the vfcurve during boost. If you don't have good cooling, 10x will end up hurting you because of the increased heat. There is also the increase in power consumption to deal with when doing that as well, so you're pbo budget will be eatin' into.


Maybe I'm not reading it properly, sorry.
In the quote above you say it just shifts voltages, will end up hurting at 10x because of the increased heat and eating in the powerbudget.
I don't agree with that and just provided some data to back it.
Just my opinion here which very few share 



jomama22 said:


> I suggest you watch this video by skatterbencher, specific from the 10:10 mark, to see how scaler affects the voltages used by pbo:


I didn't really enjoy it, lots of "marketing stuff" and not much raw meat...
About Scalar only says it's shifting up voltages, not much info at all.
He's good in explaining stuff and is using a good format but that's it.


----------



## Veii

craxton said:


> anyhow, now, do i have some kind of special "5600x" updated zen timings finally...


CCD 1, CCX1
Didn't win a buggy unit

Unsure about 2 Fused away cores - up to Core Layout and Chip (CTR can figure this out)
But no, you likely don't have any frankenstein unit


----------



## jomama22

ManniX-ITA said:


> Maybe I'm not reading it properly, sorry.
> In the quote above you say it just shifts voltages, will end up hurting at 10x because of the increased heat and eating in the powerbudget.
> I don't agree with that and just provided some data to back it.
> Just my opinion here which very few share
> 
> 
> 
> I didn't really enjoy it, lots of "marketing stuff" and not much raw meat...
> About Scalar only says it's shifting up voltages, not much info at all.
> He's good in explaining stuff and is using a good format but that's it.


The video is aimed at just teaching people what pbo is and does, nothing more than that. I liked that specific part because he had chatted the differences in voltages used. 

Looking at your own results, the only advantage you obtained was when dealing with short bench durations (I.e., cpu-z) and reduced core counts. Every other bench was a wash. 

In your own examples, there are arguments to be made for 1x as well, so the coin could easily be flipped.


----------



## craxton

Veii said:


> you likely don't have any frankenstein unit


yea this makes me sad...got this when launch happened from a "semi" scalper,
to be fair, i paid 220 since i sold a free 3600xt for 200 and this one was 420 shipped...so
i still won somewhere....



Veii said:


> Unsure about 2 Fused away cores


i thought thats what it meant....isnt this normal for all 5600x chips?


----------



## domdtxdissar

Close but no sigar (yet) 









BIOS 3501 with AGESA V2 PI 1.2.0.2
dual CCD 5950x
4x8GB gskill 3600 CL16
1900:3800 @ flat CL14 + 240 tRFC + true T1
Single error2 in TM 1umus 25 cycle


> Is a timeout issue, somewhere something ends too quickly
> or you lack voltage and cells are not recharged in time,
> a sync issue with other words,
> which's first culprit is voltage somewhere
> or resistance somewhere


*Anyone got suggestions other than upping the voltage ? (testing 1.57 vdimm now)*

I'm actually pretty happy with these results as they are already far more than only "gaming stable" and they can only get better.. 
But its pretty hard to boot these settings, have to change the settings in a specific order for it to work.

_edit_
got single error10 with 1.57vdimm after ~22min 
error12 with 1.58vdimm after ~3 min
Gonna try work my way down in voltage instead
error13 with 1.56vdim after ~60min (maxtemp is 36 degrees on dimms)


----------



## ManniX-ITA

Veii said:


> Same thing, RAS keep identical (tRCD *2 ? or tCL + tRCD + tRCD /3) and tRC remains tRP+tRAS
> it can be something else too, but it should be at least tRP+tRAS to follow basic cycling.


Tried some combinations but got mixed results with random 55-56ns latency.
Best combination is tRP-tRAS-tRC 12-16-38.

Problem is... absolutely nothing better than 14-28-42.

Should I try to push VDIMM a little bit higher?



Spoiler: tRP12




















*







*





mongoled said:


> With 4x8GB, 5600x, using SCL 2/3 instead of 4/5 results in loss of read bandwith around 300-400 MB/s
> 
> With 2 x 8GB, the results is reveresed


Of course now I remember, I'm old... 
Yes there's a little bump, around 200-250 MB/s.

SCL2:










SCL4:


----------



## ManniX-ITA

jomama22 said:


> The video is aimed at just teaching people what pbo is and does, nothing more than that. I liked that specific part because he had chatted the differences in voltages used.


The detailed results were looking more interesting but he went over them too quickly 



jomama22 said:


> Looking at your own results, the only advantage you obtained was when dealing with short bench durations (I.e., cpu-z) and reduced core counts. Every other bench was a wash.


Yes that's the point, reduced core counts.
Almost anybody runs most of the times a single threaded or all core threaded workload.
So where it matters, in terms of performances, Scalar is better.
Short bench duration cause I didn't have time and anyway it would be unfair to take my Dark Rock Pro 4 as a reference 
But I'm pretty sure it would keep the lead even on the long term.
The other benchmarks ST & MT, as stated, are thermally constrained for me.
It's only as evidence that despite the much higher temperature there's no degradation.
And if I can make it with a silent air cooler, should be much better with an AIO or a custom loop.
I'd love to see similar comparisons with a better cooling but seems to be an interesting topic only for me.



jomama22 said:


> In your own examples, there are arguments to be made for 1x as well, so the coin could easily be flipped.


Absolutely possible.
My guess is only with extreme cooling, where the CPU doesn't get anywhere near a thermal constraint.
Therefore the added advantage of a throttling point higher could be nullified and the negative count be more relevant.
But at the same time I wonder if the increase in the powerbudget can be exploited by CO to pump up more frequency and less voltage...
Hard to say without some testing.


----------



## Veii

craxton said:


> i thought thats what it meant....isnt this normal for all 5600x chips?


Yes and no. This will be decided by CTR then ~ up to how the boosting-table defines the layout & the order of such
(Under diagnose & boost tester - CTR 2.1 RC05+)
Any other potential theory except for public known stuff, can not leave my lips 


domdtxdissar said:


> Close but no sigar (yet)
> View attachment 2490003
> 
> 
> BIOS 3501 with AGESA V2 PI 1.2.0.2
> dual CCD 5950x
> 4x8GB gskill 3600 CL16
> 1900:3800 @ flat CL14 + 240 tRFC + true T1
> Single error2 in TM 1umus 25 cycle
> 
> *Anyone got suggestions other than upping the voltage ? (testing 1.57 vdimm now)*
> 
> I'm actually pretty happy with these results as they are already far more than only "gaming stable" and they can only get better..
> But its pretty hard to boot these settings, have to change the settings in a specific order for it to work.
> 
> _edit_
> got single error10 with 1.57vdimm


Welcome to my suffering world with this SMU and IMC FW rewrite 
Try to lower RTT_PARK (RZQ/2)
your procODT is fine
===================================================
Right as we speak i try to finetune another voltage set
This is my current result, but it's WIP - FFT crashes all my cores
Also @PJVol CPU VDD 1.8 up to 1.93v now finally works and makes a difference - after pushing IOD to VSOC as close as possible
40mV it is, the minimum distance
42mV just works - 38mV insta crashes - even if loadline or switching freq is wrong

But i need to fix VDDG CCD as FTT crashes 4 out of 6 cores 
Figuring out what the supportive thing is to make it work
But the EDC budget 10A more and the tight voltage scale, is noticable
Also yes, CPU_VPP 1.8v can do positive, but only for latency and only if SOC is "constrained" and not much is "wasted" (or applied too much)
Thats very likely the fix for the SOC latency scaling - and every board has VPP 1.8v as an option








also example of a "clean idle" which everyone can do
Not even close to my old 69 services only - but Aida, ZT, TaskManager and shareX run + wifi
Soo likely it's near 75-78 Processes right now. Still bloaty but i need wifi access 

* timings and voltages are WIP. i just play around and show this SOC to VDDG IOD scaling
** bellow 1.2vSOC 2100 FCLK is absolutely not bootable
*** procODT 30ohm now posts here and there but only 32 is rock stable
*** VDDG and VDDP need changes, as FFT crashes - but TM5 doesn't bluescreen anymore by a voltage choke = 40mV doubleconfirmed is the absolute minimum even for strange 1202 AGESA
**** mem is still not stable, soo i contiue to beat my head against a wall why it doesn't behave anymore ~ decyphering errors 

Last EDIT:
The reason i know the voltages are finally fine, is that i finally hit peak Write 33599MB/s (half peak FCLK)
Write bandwidth on 1 CCD units after a point - doesn't depend on MEM at all, it only depends on FCLK and voltage stability
Soo also boosting behavior & Curve Optimizer
I was at 335 98 sometimes 33 587 consistent. if something is little bit off it's 33 570 or lower. A clear notice when it's autocorrecting or subtle autocorrecting
Soo this means clearly, that VDDG IOD is correct and SOC + procODT finally is at the place it has to be
VDDG CCD and VDDP are the ones to play with now and maybe some other remain voltages ~ to gain back FFT test stability
(CCD just dies fully and all cores crash one after another) 😅


----------



## KedarWolf

Anyone who wants to disable all auto driver updates in Windows with Windows 2004 or higher, save this code as update.reg in Notepad++ and click on it.

Then Windows won't install crap like the AMD drivers that crashed peeps. I always install all my drivers manually on a clean Windows install or integrate them into my Windows ISO install.wim and boot.wim for auto-installs when installing Windows. 




Code:


Windows Registry Editor Version 5.00

[HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Windows\CurrentVersion\Device Metadata]
"PreventDeviceMetadataFromNetwork"=dword:00000001

[HKEY_LOCAL_MACHINE\SOFTWARE\Policies\Microsoft\Windows\DriverSearching]
"DriverUpdateWizardWuSearchEnabled"=dword:00000000
"SearchOrderConfig"=dword:00000000

[HKEY_LOCAL_MACHINE\SOFTWARE\Policies\Microsoft\Windows\WindowsUpdate]
"ExcludeWUDriversInQualityUpdate"=dword:00000001

[HKEY_LOCAL_MACHINE\Software\Policies\Microsoft\Windows\CloudContent]
"DisableWindowsConsumerFeatures"=dword:00000001


----------



## DeletedMember558271

Here's the overnight TM5 for these settings















53.5ns could probably be even better with some further PBO & other tweaking.
Anyways haven't seen anyone else with around 1.45v~ or a 1900 FCLK no-boot handicap and dual rank do better and don't know if I will, had to do this all myself cause no one else was doing the homework to copy. All the 1867 boys just be giving up and posting no results, and almost everyone else is slamming their RAM with 1.5v+ which I could do too if I didn't ever play video games with a 3080.

A lot of people just aren't optimizing their RAM very well at all, I know I have 1 CCD but still looking around so many people are not making the most of their extra vDIMM and FCLK at all. Everyone that has 1.5v+ 1900+ should be a ways ahead of me.
And anyone who is still not dual rank, you're doing it wrong. Who cares about single rank anymore
Also just 16GB alone is becoming pretty outdated even if you could get that in dual rank


----------



## jomama22

Dreamic said:


> Here's the overnight TM5 for these settings
> View attachment 2490047
> View attachment 2490048
> 
> 53.5ns could probably be even better with some further PBO & other tweaking.
> Anyways haven't seen anyone else with around 1.45v~ or a 1900 FCLK no-boot handicap and dual rank do better and don't know if I will, had to do this all myself cause no one else was doing the homework to copy. All the 1867 boys just be giving up and posting no results, and almost everyone else is slamming their RAM with 1.5v+ which I could do too if I didn't ever play video games with a 3080.
> 
> A lot of people just aren't optimizing their RAM very well at all, I know I have 1 CCD but still looking around so many people are not making the most of their extra vDIMM and FCLK at all. Everyone that has 1.5v+ 1900+ should be a ways ahead of me.
> And anyone who is still not dual rank, you're doing it wrong. Who cares about single rank anymore
> Also just 16GB alone is becoming pretty outdated even if you could get that in dual rank


Lol, yes, chastise people because they run a higher vdimm voltage than you, that's logical.

Not sure where you think that just adding more volts unlocks all this heaps of performance. It doesn't work like that. Some setups need it, some don't, that's really the long and short of it.

Also, yes, your setup falls in line with what I would expect a 1ccd chip would do at 3733cl15. You realize you are one step from 3890/1900 right? There aren't gobs of performance to be had there.

I already showed you what a 1ccd 3800cl14 flat can do (51.2), tuning that down to 3800 14-15-14 pulls a 51.9. Dare I say that if I pull that down to match yours, it will be faster than yours by around .5ns. 

Really don't understand where you come off acting like that. Your setup isn't special nor magical, it falls into the expected.

If all you have to add to this thread is crap like that, you don't need to post.


----------



## DeletedMember558271

jomama22 said:


> Lol, yes, chastise people because they run a higher vdimm voltage than you, that's logical.
> 
> Not sure where you think that just adding more volts unlocks all this heaps of performance. It doesn't work like that. Some setups need it, some don't, that's really the long and short of it.
> 
> Also, yes, your setup falls in line with what I would expect a 1ccd chip would do at 3733cl15. You realize you are one step from 3890/1900 right? There aren't gobs of performance to be had there.
> 
> I already showed you what a 1ccd 3800cl14 flat can do (51.2), tuning that down to 3800 14-15-14 pulls a 51.9. Dare I say that if I pull that down to match yours, it will be faster than yours by around .5ns.
> 
> Really don't understand where you come off acting like that. Your setup isn't special nor magical, it falls into the expected.
> 
> If all you have to add to this thread is crap like that, you don't need to post.


I'm not chastising anyone for running high vDIMM, I'm chastising all the people I see running like 1.5-1.55v+ and don't even have better latency or barely do, not better enough to warrant running so much more and having higher temps to not perform much better if at all, or lots of people with around 1.45v but performing worse, some of these even on just 2x8GB.
The Zen Sheet is full of jokes, I'm sorry if you can't see that?

I would be curious to see what you can do with 1.45v 3733 though please if you're offering, maybe I could learn something and improve mine.
Again, I can as you say actually add more volts and unlock heaps performance matching you, not sure what this acting like more voltage doesn't allow you to run better performance is. Just lower yours to 1.45v then if it doesn't do anything, as if you'll even boot or not have 1000's errors.

I'll say again, anyone running 0.05v or more than me should perform better... not worse, or you're doing something wrong or have **** RAM.
Not sure why any of this is controversial to you
Bye


----------



## Pegasuss

Hey guys,

New here, I just wanted to share my timings and know your thoughts on what I can improve? dram voltage is 1.51v, not sure why its showing 1.52v.

Tried to do flat 14's with 1T GDM off but it will not work unless you use setup timings, another option is to use 120 clkstrdrv like what @ManniX-ITA said in the B550 unify-x forum. It give less error but seems to be asking for more voltage even when pushing 1.56v+ when I tested them, if I remember correctly.











Also, SCL gives better read bandwidth if set to 4 like what @mongoled said. 2 and 3 gives less read bandwidth. I do not know why?

tRP and tRAS set to 14/28 is better than 13/22(lowest i can go), and 13/27.

Ran 3 runs on each settings, and I got this:
13/27 - 56676, 56736, 56705
13/22 - 56693, 56710, 56740
14/28 - 56882, 56867, 56874


----------



## jomama22

Dreamic said:


> I'm not chastising anyone for running high vDIMM...
> 
> I'll say again, anyone running 0.05v or more than me should perform better... not worse, or you're doing something wrong or have **** RAM.


 Lmao. And yeah, my daily is 3800cl14-15-11-28-39 @1.44v. so yeah, I know it's doing better than yours at the same or less volts.

When I'm home I'll post up my settings.


----------



## DeletedMember558271

Pegasuss said:


> Hey guys,
> 
> New here, also new to ram OC. I just wanted to share my timings and know your thoughts on what I can improve?
> 
> Tried to do flat 14's with 1T GDM off but it will not work unless you use setup timings, another option is to use 120 clkstrdrv like what @ManniX-ITA said in the B550 unify-x forum. It give less error but seems to be asking for more voltage even when pushing 1.56v+ when I tested them, if I remember correctly.
> 
> View attachment 2490077
> 
> 
> 
> Also, tRDRDSCL/tWRWRSCL gives better read bandwidth if set to 4 like what @mongoled said. 2 and 3 gives less read bandwidth. I do not know why?
> 
> tRP and tRAS set to 14/28 gave the best read bandwidth. I tested 13/22, 13/27.
> 
> Ran 3 runs on each settings, and I got this:
> 13/27 - 56676, 56736, 56705
> 13/22 - 56693, 56710, 56740
> 14/28 - 56882, 56867, 56874


With that extra 0.07v you got over me should be able to lower tRCDRD to 14, and tRC, tWR, tRTP to match me or better, along with tRP 13/12 and tRAS 21 though not if that doesn't perform better for you I guess. Otherwise not sure if your sticks need that much more just for the better tCL and tRFC but maybe, they are demanding.



jomama22 said:


> Lmao. And yeah, my daily is 3800cl14-15-11-28-39 @1.44v. so yeah, I know it's doing better than yours at the same or less volts.
> 
> When I'm home I'll post up my settings.


Cool so what are you having trouble understanding? You prove my point even more, so many people running way higher voltage than you with way worse results. I don't think a lot of people are doing a good job of min/maxing before finishing and sharing their final result.
My sticks can't post tCL 14 that low at least with GDM Off 2T, yours are better. None of my primaries can go a digit lower currently without failing a 12 hour stress test, same with SCL's if I wanted them lower, and tRDWR/tWRRD I wish could be better, tCWL won't go to 12. tRFC was falling apart around 135ns at least and maybe does even higher idk, so if I can push that any lower it's not by very much.

I don't believe my sticks are that amazing, not sure if you think yours are, but that's again also part of the reason why I think I should be seeing more people doing better at the voltage they're at. If I thought I had better sticks than everyone that would be an unrealistic and unfair expectation, but I don't think they're too special compared to what you can buy now. Better bins out there


----------



## jomama22

Dreamic said:


> With that extra 0.07v you got over me should be able to lower tRCDRD to 14, and tRC, tWR, tRTP to match me or better, along with tRP 13/12 and tRAS 21 though not if that doesn't perform better for you I guess. Otherwise not sure if your sticks need that much more just for the better tCL and tRFC but maybe, they are demanding.
> 
> 
> Cool so what are you having trouble understanding? You prove my point even more, so many people running way higher voltage than you with way worse results. I don't think a lot of people are doing a good job of min/maxing before finishing and sharing their final result.
> My sticks can't post tCL 14 that low at least with GDM Off 2T, yours are better. None of my primaries can go a digit lower currently without failing a 12 hour stress test, same with SCL's if I wanted them lower, and tRDWR/tWRRD I wish could be better, tCWL won't go to 12. tRFC was falling apart around 135ns at least and maybe does even higher idk, so if I can push that any lower it's not by very much.
> 
> I don't believe my sticks are that amazing, not sure if you think yours are, but that's again also part of the reason why I think I should be seeing more people doing better at the voltage they're at. If I thought I had better sticks than everyone that would be an unrealistic and unfair expectation, but I don't think they're too special compared to what you can buy now. Better bins out there


Right, and I don't sit here saying the stuff you are because it literally doesn't matter what anyone uses for voltage to get their performance. 

And no, I don't. There are plenty of users here who know how to get more out of their memory than me. What vdimm they use doesn't even matter to do so lol.


----------



## RHBH

I'm trying to get my ram to 1T and GDM off. Any tips?

Also, after changing my RAM sticks to different slots, my ProcODT (Auto) changed from 43.6 to 36.9, is this kind of behavior normal?


----------



## DeletedMember558271

jomama22 said:


> Right, and I don't sit here saying the stuff you are because it literally doesn't matter what anyone uses for voltage to get their performance.
> 
> And no, I don't. There are plenty of users here who know how to get more out of their memory than me. What vdimm they use doesn't even matter to do so lol.


I don't know why you're being stupid but I'm done with it, there's clearly people using too much voltage or not getting as much out of their voltage as they could. And what voltage people use does have an impact on how much they can get out of their memory, I don't know what world you live in where voltage can't be a limiting factor, where you never need to raise it to get more. If you think Veii is a magical wizard that can just turn performance out of thin air like RAM jesus or something without more voltage... even they will tell you lack of it can be a limiting factor. It's like half of the TM5 error explanations, "you need more voltage, or lower performance/timings". Crazy I'm even explaining something this basic on a forum like this, all because you're a little confused over RTT's & CAD_BUS and how those can change voltage requirements a bit you go completely dense and extreme with it. "vOLtAgE doEsNt mEAn anYThiNg."


----------



## jomama22

Dreamic said:


> I don't know why you're being stupid but I'm done with it, there's clearly people using too much voltage or not getting as much out of their voltage as they could. And what voltage people use does have an impact on how much they can get out of their memory, I don't know what world you live in where voltage can't be a limiting factor, where you never need to raise it to get more. If you think Veii is a magical wizard that can just turn performance out of thin air like RAM jesus or something without more voltage... even they will tell you lack of it can be a limiting factor. It's like half of the TM5 error explanations, "you need more voltage, or lower performance/timings". Crazy I'm even explaining something this basic on a forum like this, all because you're a little confused over RTT's & CAD_BUS and how those can change voltage requirements a bit you go completely dense and extreme with it. "vOLtAgE doEsNt mEAn anYThiNg."


The point is so far over your head I'm not going to keep repeating myself.

You are just acting like a child at this point. How about you up your voltage and see how much more performance you can get there bud?

Like put up or shut up. Iv showed how much better I can do than you. Keep trying to talk crap to me lmao.


----------



## DeletedMember558271

jomama22 said:


> The point is so far over your head I'm not going to keep repeating myself.
> 
> You are just acting like a child at this point. How about you up your voltage and see how much more performance you can get there bud?
> 
> Like put up or shut up. Iv showed how much better I can do than you. Keep trying to talk crap to me lmao.


The last time I bothered with higher voltage I copied I think Craxtons settings for a minute and got 51.5ns.
I don't know why you're actually so dumb you don't think raising voltage to 1.50v-1.55v makes it possible to do things you just can't do with 1.40v-1.45v.
You're actually delusional thinking voltage doesn't help you accomplish more anything whatsoever you must be trolling me good one dude you got me you can't actually be this dumb


----------



## DeletedMember558271

I cannot even tell you how many times I've seen Veii post here saying "X" timing requires around "X" voltage at "X" frequency, making minimum voltage recommendations for things like tCL 14 or tRCDRD 14 at 3800 for example, how much you probably need for it to work, maybe you should listen to him.

"X" needs this much voltage to work is like one of the things I've seen him say the most


----------



## jomama22

Dreamic said:


> The last time I bothered with higher voltage I copied I think Craxtons settings for a minute and got 51.5ns.
> I don't know why you're actually so dumb you don't think raising voltage to 1.50v-1.55v makes it possible to do things you just can't do with 1.40v-1.45v.
> You're actually delusional thinking voltage doesn't help you accomplish more anything whatsoever you must be trolling me good one dude you got me you can't actually be this dumb


I never even said more voltage doesn't help. Those words literally never came out. All I said was why would I care if someone else used more voltage to get more performance? I also said why would you think upping the voltage gives you heaps of performance? Let's consider this, even my 51.2ns compared to your 53.5 is only 4.5% improvement. I don't consider 4.5% heaps of performance. It is literally somthing you would most like never actually perceive in daily usage.

The only reason I even said that was because of you chastising people about what volts they use and the performance they get. If someone needs to use 1.55v to get the performance they want, even if it's worse than yours, WHAT DOES IT MATTER TO YOU? 

They are clearly here trying to get more performance, whether that's with more or less voltage. 

You have said nothing other then "Hey guys! Look what I can do! Why can't you do that! Wow, you must suck at tuning, I'm not even trying!"

Again, you're acting like a child and no one needs it nor cares to deal with it.

So you choose to run at 3766/1866 even though you can get more performance with more voltage. You choose to do this while making a stink about voltages. You realize how oxymoronic that is right? Or is it you really just can't get them stable so you have to be down in that voltage range?


----------



## Pegasuss

Dreamic said:


> With that extra 0.07v you got over me should be able to lower tRCDRD to 14, and tRC, tWR, tRTP to match me or better, along with tRP 13/12 and tRAS 21 though not if that doesn't perform better for you I guess. Otherwise not sure if your sticks need that much more just for the better tCL and tRFC but maybe, they are demanding.


Testing tWR at 10 right now, looking stable but will wait for testmem5 extreme1 to finish. I can do tRP at 13, tRAS 22-27, and tRC at 35-40 but read bandwidth decreases, which I have no idea why, guess lower isnt always better. I'll try to do tRCDRD 14 again, and see if I can make it work but last time I did a quick check it didnt.


----------



## DeletedMember558271

jomama22 said:


> I never even said more voltage doesn't help. Those words literally never came out. All I said was why would I care if someone else used more voltage to get more performance? I also said why would you think upping the voltage gives you heaps of performance? Let's consider this, even my 51.2ns compared to your 53.5 is only 4.5% improvement. I don't consider 4.5% heaps of performance. It is literally somthing you would most like never actually perceive in daily usage.
> 
> The only reason I even said that was because of you chastising people about what volts they use and the performance they get. If someone needs to use 1.55v to get the performance they want, even if it's worse than yours, WHAT DOES IT MATTER TO YOU?
> 
> They are clearly here trying to get more performance, whether that's with more or less voltage.
> 
> You have said nothing other then "Hey guys! Look what I can do! Why can't you do that! Wow, you must suck at tuning, I'm not even trying!"
> 
> Again, you're acting like a child and no one needs it nor cares to deal with it.


Because I look at the Zen Sheet, and there is objectively many people doing it wrong. If you think all the results on there are perfectly done min/maxing squeezed every last drop of performance, you are dumb. That's all I was saying, that's all my point was, and it's true. I'm so sorry reality bothers you so much jesus christ. There's a lot of inefficiency on the Zen Sheet, I'm sorry.

I want to live in your Utopia where everyone does everything perfectly or close to it


----------



## jomama22

Dreamic said:


> Because I look at the Zen Sheet, and there is objectively many people doing it wrong. If you think all the results on there are perfectly done min/maxing squeezed every last drop of performance, you are dumb. That's all I was saying, that's all my point was, and it's true. I'm so sorry reality bothers you so much jesus christ. There's a lot of inefficieny on the Zen Sheet, I'm sorry.
> 
> I want to live in your Utopia where everyone does everything perfectly or close to it


Has nothing to do with perfection. I just think your approach to the whole matter is tone deaf and childish. I personally viewed that sheet for the first time when you brought it up a few days ago so I genuinely don't even know what's on there nor really care.

I tune my memory, read, seek help, tune some more, etc. That's it.


----------



## craxton

Veii said:


> Any other potential theory except for public known stuff, can not leave my lips


in order for one to get this version one must be a patron i do believe?

thank you, ill not ask further then on that note. 



Spoiler: WHEA



had a WHEA-LOGGER error in "summery section" show up as id 18

but not under kernel WHEA logger....

cant find this WHEA-LOGGER anywhere inside event viewer....is this not shown?
debug is on as well

(edit) i made a custom view for WHEA-LOGGER so now if one is to happen (not a simple bsod from trying to 
get more curve ill know)


----------



## DeletedMember558271

jomama22 said:


> Has nothing to do with perfection. I just think your approach to the whole matter is tone deaf and childish. I personally viewed that sheet for the first time when you brought it up a few days ago so I genuinely don't even know what's on there nor really care.
> 
> I tune my memory, read, seek help, tune some more, etc. That's it.


Ok well thank you so much for sharing your opinion on my approach with me, I will be conducting my future approaches differently because I care so much about what jomama22 thinks of them.


----------



## Veii

Dreamic said:


> I don't know what world you live in where voltage can't be a limiting factor, where you never need to raise it to get more. If you think Veii is a magical wizard that can just turn performance out of thin air like RAM jesus or something without more voltage


My first months of testing, was making a good 16-16-16 testset
It was for research and still is public as "undervolt" preset. it's goal was to extend the A0 PCBs maximum frequency as far as possible and at the same time aside from IC quality, fighting with PCB quality on places it should not be (nobody uses A0 on anything beyond 4133MT/s ~ too many issues and potential for pcb death)


Spoiler: This 16-16-16 set














Was working with 1.35v on 3800MT/s and 1.46v at 4000
Even 1.48v was fine for 4133MT/s. But it started to reach several limits

RTT_PARK was too strong, going up in voltage for higher and higher MT/s made it reach dangerous levels for it
~ 1.52 was barely ever consistently stable, it was overvolting itself
~ on 1.54v i started to lose a whole channel , and gladly realizing the clear nonsense i've been doing , before the die
Soo it was redo time, i figured how to soften and dampen voltage ~ learned / explored what does what on the RTTs ... 706 came into life and 607 too
~ both worked but both with different voltage scales
Soo it continued that trend. Learned about tCKE behavior and that pushed maximum limits even further utilizing powerdowns now to tame higher input volttage
learned about SETUP times aligning them with CKE, from couple of chiphell chinese threads
learned further about dynamic ODT instead fixed current , and to this day didn't get RTT_WR to work with SETUP timing cuts to extend the limit further
Then yes, it was memory latency pushing and pushing and pushing
4.85Mhz, beyond was not possible ~ got that CPU maxed out on PBO. All cores hold it perfectly... Got bored again
Soo from 16-16-16 easy to run, with learned voltage taming experience, it was the path to push it further and find the upper limits of VDIMM to RTT's
This upper limits along the older undervolt limits (for health prevention) ~ allowed to run lower timings at virtual high voltage numbers ~ yet without really heat issues
(again 900rpm dc fan from who knows when 2008 maybe)
~ still maxed out at 50.1ns @ 4200MT/s , could not hit my sub 50ns goal. Soo CL15 something, it had to be

Yes, voltages do not create heat & voltages controlled are not dangerous ~ if you know how to balance it
Current that arrives (ampere) is what creates heat & is dangerous ~ not voltages on their own by themself

The re-shared picture above should be near December.
Yes GDM off also wasn't really a topic to talk about, nor tCKE was researched or RTTs where even considered ~ except following the hard work of 1usmus
Please, mind your sarcastic words next time you judge upon a topic without investigating why people continue to up voltages

Of course you can just push 1.8v onto mem with 1/4th of the allowed capacity and go for records
But this will never be your daily.
My limits extended , currently C15 flat up to 4267 without going beyond 1.66v (except FCLK yet isn't stable at 2133) 
~ and i'm very happy with what i can daily and worked on dailying (A0 4000C19-19 100 bucks dimms mind you)
This board, it's memory & CPU throttling behavior is known to me for around 7-8 months already, and it's been promised to invest time into Vermeer after skipping Matisse
Next time when you judge someone or the community as a whole _~to phrase it how you did~ "JuSt PuShEs VoLtAgEs" _, try to at least check their working history on this topic 

Also no, 2x DR is not superior above 4x SR
Neither is the higher bandwidth at lower MT/s, compared to higher peak MT/s at lower timings
They average out being similar within their peaks, it is not a topic to argue about ~ else yes DualRank is faster at given MT/s & costs more & is newer
Soo please stop looking down on people,
who A.) can not afford it
& B.) didn't build a PC or buy RAM in 2020

I don't need to be any type of wizzard, nothing on the results came with magic. 🙄
It was 100+ hours memory testing on one single board with one single kit for many months & logically other non memOC work on it
Likely less than the lifetime of some new bought sets here


----------



## DeletedMember558271

Veii said:


> Please, mind your sarcastic words next time you judge upon a topic without investigating why people continue to up voltages


I'm not talking about people that know what they're doing as well as you, I'm talking about people that don't and are ineffecient and get poor results.



Veii said:


> Next time when you judge someone or the community as a whole _~to phrase it how you did~ "JuSt PuShEs VoLtAgEs" _, try to at least check their working history on this topic


There's nothing wrong with judging the peoples results I'm judging.



Veii said:


> Also no, 2x DR is not superior above 4x SR


When I was saying dual rank, I was talking about 2x16GB DR or 4x8GB, since either are effectively dual rank and better than 2x8GB, and 16GB total system memory is just on the way out.
I don't even have 2x16GB DR I'm 4x8GB.

You assume everyone I'm talking about knows what they're doing as well as you, you can't tell me you don't see mistakes and big ineffeciency constantly.
All I'm saying is there's some results that are really ineffecient and it's like everyones minds melt like such a thing is impossible


----------



## RHBH

So far these are my results with 1.50v, maybe can I lower the voltage? 1.45v?


----------



## DeletedMember558271

RHBH said:


> So far these are my results with 1.50v, maybe can I lower the voltage? 1.45v?
> 
> View attachment 2490110


I'm on 3733 but I run all my timings the same or tighter on 1.45v so should be able to get a good bit lower yea maybe 1.46v or at least 1.47v I'd hope, might want to change RTT's to maybe 6/3/3.
If 1.45v works, then continuing to run 1.50v would almost be... inefficient? If you're sticks aren't terrible it should be pretty easily possible I'd think, 1.50v here for just 56.2ns doesn't look like a very good result to me but maybe @jomama22 would say it's perfect


----------



## RHBH

Dreamic said:


> I'm on 3733 but I run all my timings the same or tighter on 1.45v so should be able to get a good bit lower yea maybe 1.46v or at least 1.47v I'd hope, might want to change RTT's to maybe 6/3/3.
> If 1.45v works, then continuing to run 1.50v would almost be... inefficient? If you're sticks aren't terrible it should be pretty easily possible I'd think, 1.50v here for just 56.2ns doesn't look like a very good result to me but maybe @jomama22 would say it's perfect


Yea I was also expecting something like 54ns or less....

I think these results can improve at least 1ns if I manage to get 1T GDM off.

I can't POST with 1T GDM off (F9 error code).

Even if I throw something like 3600 CL22 1.45v it won't POST with 1T GDM off.

I can post with true 1T and 3200C14 (XMP) tho...


----------



## DeletedMember558271

RHBH said:


> Yea I was also expecting something like 54ns or less....
> 
> I think these results can improve at least 1ns if I manage to get 1T GDM off.
> 
> I can't POST with 1T GDM off (F9 error code).
> 
> Even if I throw something like 3600 CL22 1.45v it won't POST with 1T GDM off.
> 
> I can post with true 1T and 3200C14 (XMP) tho...


You could try seeing what latency AIDA gives you in safe mode to see how much of it is your Windows cleanliness, also dual CCD so that doesn't help latency but could still be better.
If you stay at 1.50v you should be able to get, well, a good number of things I'd have to type tighter.

I haven't tried 4x8GB GDM Off 1T yet really and barely seen anyone running that yet


----------



## lmfodor

Veii said:


> Yes and no. This will be decided by CTR then ~ up to how the boosting-table defines the layout & the order of such
> (Under diagnose & boost tester - CTR 2.1 RC05+)
> Any other potential theory except for public known stuff, can not leave my lips
> 
> Welcome to my suffering world with this SMU and IMC FW rewrite
> Try to lower RTT_PARK (RZQ/2)
> your procODT is fine
> ===================================================
> Right as we speak i try to finetune another voltage set
> This is my current result, but it's WIP - FFT crashes all my cores
> Also @PJVol CPU VDD 1.8 up to 1.93v now finally works and makes a difference - after pushing IOD to VSOC as close as possible
> 40mV it is, the minimum distance
> 42mV just works - 38mV insta crashes - even if loadline or switching freq is wrong
> 
> But i need to fix VDDG CCD as FTT crashes 4 out of 6 cores
> Figuring out what the supportive thing is to make it work
> But the EDC budget 10A more and the tight voltage scale, is noticable
> Also yes, CPU_VPP 1.8v can do positive, but only for latency and only if SOC is "constrained" and not much is "wasted" (or applied too much)
> Thats very likely the fix for the SOC latency scaling - and every board has VPP 1.8v as an option
> View attachment 2490043
> 
> also example of a "clean idle" which everyone can do
> Not even close to my old 69 services only - but Aida, ZT, TaskManager and shareX run + wifi
> Soo likely it's near 75-78 Processes right now. Still bloaty but i need wifi access
> 
> * timings and voltages are WIP. i just play around and show this SOC to VDDG IOD scaling
> ** bellow 1.2vSOC 2100 FCLK is absolutely not bootable
> *** procODT 30ohm now posts here and there but only 32 is rock stable
> *** VDDG and VDDP need changes, as FFT crashes - but TM5 doesn't bluescreen anymore by a voltage choke = 40mV doubleconfirmed is the absolute minimum even for strange 1202 AGESA
> **** mem is still not stable, soo i contiue to beat my head against a wall why it doesn't behave anymore ~ decyphering errors
> 
> Last EDIT:
> The reason i know the voltages are finally fine, is that i finally hit peak Write 33599MB/s (half peak FCLK)
> Write bandwidth on 1 CCD units after a point - doesn't depend on MEM at all, it only depends on FCLK and voltage stability
> Soo also boosting behavior & Curve Optimizer
> I was at 335 98 sometimes 33 587 consistent. if something is little bit off it's 33 570 or lower. A clear notice when it's autocorrecting or subtle autocorrecting
> Soo this means clearly, that VDDG IOD is correct and SOC + procODT finally is at the place it has to be
> VDDG CCD and VDDP are the ones to play with now and maybe some other remain voltages ~ to gain back FFT test stability
> (CCD just dies fully and all cores crash one after another) 😅


Hi Veii, I repeat that again, what good is to have you here. At least to teach us a little more that I think it is a great quality that you have and that the vast majority of us value.

Now that you are testing the "broken" version of SMU 56.50 I want to ask you two basic questions,

1) how do you run frequencies above 2000Mhz with FCLK 1: 1 and not have WHEAs? I have tried 4000/2000 with the big help of @craxton but have always had errors. Today for example I tested 3966/1933 and although I had no errors in TM5, the WHEAs were there as always full of them.

2) The second and more specific question is precisely about the voltages debate. I ended up discovering that with these 3800CL14 DR Mems, which come from the factory at 1.5V, in reality I never need more than that value to achieve something stable with tight timings but with the great challenge of lowering the tRCDRD which is still at 16. I'm using the timings that @KedarWolf shared with us and they work perfect for me, thanks Kedarwolf for sharing them! What if I discovered that for example he uses 1.20V from vSOC, and I began to try to lower it to understand if it had some kind of limitation, but no, it worked perfect in 1.12V keeping the values that you have recommended and read for example from Coolenjoy. This is my actual timmings, with 1.5V VDIMM and a lower vSOC








The question is, beyond trying to keep lowering the VDIMM to 1.48V or even more, for example I know that to sustain the tWR at 12 it should have a good voltage, however I'm at 10. It may be that my limitation to get the tRCDRD14 is precisely that? Because the TM5 errors 6, 12, 2 that I immediately receive when I go to 14 make me think of a voltage combination, which until now has always led me to try values close to 1.55V but there is something else. Actually I used Google Rayzen Calculator, I tried in different ways but I'm not managing to at least get past the errors 6 12 2 0 and so on. Everything that at first I couldn't, I was able to achieve with the help of a lot and of course great help from you. The values that I have now for 3800MT/s are excellent, something that we share with @ManniX-ITA , and I think that the great challenge, as you have told us many times, is to lower the tRCDRD at least just to test and learn, because I know I'm near the top theoretical value of 3800, so what would be the benefit, right? The question is, what can I do differently. I already tried to relax the tRRDs / tWRDs, increase the SCL to 4 or 5. Raise the tWR to high values and consequently the tRTP to half and begin to lower it. And then I also read the recommendations of tRDWR against tRCDRD, / 2 +2 if tCWL = tCL, and tWRRD x 4 taking into account the SCLs as latency and being aligned with the tRCDWR. Then the RRTs, given this voltage of 1.5V, in RTT 0-3-1 or 0-3-3 or even more loose 0-2-5 (for a higher one) or 6-3-3, considering a Proctodt low at 36 or 40, plus a ClkDvrStr strong of 40 that sustains a "low voltage" (?). I think I considered all variables. I want to take that step and maybe you can give me some guidance. My feeling is that perhaps these DR memories do not require as much voltage perhaps as the same version in SR that I have seen cases where they run at 1.7V. They seem to be very different. Finally, with the great advice from @ManniX-ITA , I managed to activate 1T with the CADBUS Setup of 56-56-56 with an excellent performance. This obsession with tRCDRD at 14 or all flat, you think it's possible?, or not flat, because I know that memories can do it, maybe not just mine, or maybe my 5900 IMC is not so good or the mobo is not accompanying me, so I want to buy a Unify-X to test. Any advise for an a step up?

Final words about the debate, I do not think this is the place to judge anyone, on the contrary, I believe in this forum many have been formed, with the help of many people and it is not precisely a matter of capabilities, or of being the better engineer from AMD or Samsung or whatever, it is about people who have the ability to help constantly, which is not easy because it requires time and passion, to treat cordially without getting into discussions, I think that is value, at least me. Here there is not a matter of egos in who achieves a better result, but in learning, in improving, and of course giving back in some way all this knowledge to other people. So thank you Veii for so much dedication.


----------



## RHBH

Dreamic said:


> You could try seeing what latency AIDA gives you in safe mode to see how much of it is your Windows cleanliness, also dual CCD so that doesn't help latency but could still be better.
> If you stay at 1.50v you should be able to get, well, a good number of things I'd have to type tighter.
> 
> I haven't tried 4x8GB GDM Off 1T yet really and barely seen anyone running that yet


I've seen some ppl saying 60ohm ClkDrvStr allows true 1T, but this didn't work for me.

Also it seems my system is accepting ProcODT 36, 40 and 43, does it matter? I've read higher ProcODT = Less vdimm required.


----------



## lmfodor

RHBH said:


> I've seen some ppl saying 60ohm ClkDrvStr allows true 1T, but this didn't work for me.
> 
> Also it seems my system is accepting ProcODT 36, 40 and 43, does it matter? I've read higher ProcODT = Less vdimm required.


I don’t know if you have a dual rank mems, but for me that works was to set the CADBUS setup to 56-56-56. See my timings above. I always received BSOD when trying to activate 1T, and with those values it works perfect. 


Sent from my iPhone using Tapatalk Pro


----------



## RHBH

lmfodor said:


> I don’t know if you have a dual rank mems, but for me that works was to set the CADBUS setup to 56-56-56. See my timings above. I always received BSOD when trying to activate 1T, and with those values it works perfect.
> 
> 
> Sent from my iPhone using Tapatalk Pro


I will try that, thanks.

I have 4x8GB (SR).


----------



## danakin

Veii said:


> Good job, it's 0.2 down - and you prepared the dimms to run on GDM off
> But i am sorry to tell you ~ that TM5's result is only 15-18% worth something
> It shows that you don't have a catastrophic failure and likely games would be fine with it
> But it doesn't show that you won't thermal throttle, and it doesn't show that predicted tREFI + tRFC range is correct
> 
> Knowing you used tRFC mini (well i did for you)
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Means, tRFC won't fail after a time
> But there is a difference between techical theory and real world results
> 
> Soo please either edit the MT.cfg config (inside the /Bin folder) to 25 cycles
> Or grab this old reuploaded one, which has 20 cycles preconfigured
> 
> In order to actually proof thermal stability, we need to be sure the dimms remain stable @ their highest thermal peak
> Which means, either running furmark while TM5 runs (soo the GPU heats it up)
> Or letting a TM5 test run beyond 1h
> Around 45min is required for dimms to reach Thermal Equilibrium, and around 6 cycles are required to notice and tRFC1 failure
> 19 cycles are required to notice any tREFI and tCKE failure ~ powerdown and a whole refresh cycle.
> 
> Soo because memory can and did often fail the last test of cycle 19, the absolute minimum is 20 cycles
> Which is 1:30h for 16gb , or 3h for 32gb sets
> Please retest
> Also when using Aida64
> Put yourself to High-Performance powerplan, push display poweroff to 2h, system hibernation to disabled & disable USB suspension (advanced powerplan settings, above minimum % powerstate)
> This will prevent random DPC calls while TM5 runs and while Aida64 runs
> Another advice,
> Run Aida64 as soon as possible while the OS loads ,then let it finish
> By the time it finishes, the OS will have loaded all their useless services & you can run another one (before TM5 !)
> Doing so (after the first Aida64 run which loads it's own Kernel Drivers) ~ it will allow the CPU to start using it's powerstates
> Soo the CPU will hibernate fully (if enabled) and the test results will be consistent and peaking up to CPUs capability & settings
> 
> If you take the first load, the thread sheduler will pioritize Microsoft "delayed" services and your result will be wrong (L3 especially)
> If you run Aida64 after TM5 or with ZenTimings, the ZT kernel and both ZT & TM5's random refresh will do random DPC calls
> This eats around 400-600MB/s bandwidth, slows cache down and increases tested latency
> Soo to make this as correct and consistent as possible:
> 
> run Aida64 asap on OS start
> wait a bit , like 10sec ~ the test takes long enough soo useless services will be suspended by the thread scheduler as Aida64's kernel enforces Realtime mode
> after the first realtime load, the CPU will forcefully suspend itself (if supported) soo what you test is idle to high perf lantency
> Last point might appear slower , but it's as close to reality as possible. The rest are peak boost tests and do not match to normal day-to-day usage. Also can randomly track microsoft service triggers and give a slower or unrealistic unstable result
> OC'ing T-Force 4133 cl18
> Post with TM5 20cycles , or edit it yourself
> 
> It's really "bad" ones from my personal viewpoint.
> 12+2 Vishay SiC639 , 50A
> on a ASP1106-PWM-Controller (rebranded RT3667BE) which only supports 4+2 phase mode
> 
> They cheaped out on the PWM controller and had too tripple it up
> Soo it's in reality:
> 4 Phase vCore * 3
> 1 Phase SOC, one DRAM
> They should've used a Renesas one which at least supports 7+1 phases to make this a dual 6 phase board, instead a 4 phase one
> VRMs according to 5800X test heat up to 80c ~ but the board has full switching frequency control & phase control + loadline modeling
> 
> Potentially i am less inteligent than the ASUS engineers, and their 4 phase option has better ripple ~ but somehow i doubt this
> Anywho , i think it's fine ~ but i'd be worried with a 5950X on it.
> 210A on 100% usage is kiinda peaking the specs-sheet (160A vcore + 50A SOC)
> A 5900X stock should be fine, a 5800X stock should also be just borderline fine (5800X OCs itself stronger than a 5900X)
> But we'll see how it behaves on my take & if fMAX override does anything to the 5600X
> If it's WHEA hell, then i'll just put a 1200AF or 1700X on it ~ although i'd be worried with a 180A 1700X, haha
> (eh it was fine with a B350 Toma peaking 105c ~ this shouldn't be thaat bad 😅)
> EDIT:
> As we know, peaking the specs sheet doesn't help Ripple at all
> a doubled 6 phase potentially would be better (with the option to switch it to full phase , which we can with ASUS's ext volt controller)
> ~ well not using Vishay 50A stages at all and going rather with 70A or 90A Renesas Mosfets on a 300$ board, would be even better
> But hey, i'm neither EVGA engineer, nor have ASUS connections to judge them for this ~ maaybe it's fine. I'll hold back critique till i can verify it myself
> A B350 Tomahawk with a mini 55mm blowimatron, was fine with over 200A load ~ this should not be even close as catastrophic as my 1700X set
> Yet the B350 Toma sustained my 3467MT/s C14-14 set ~ soo thermal peaking VRMs don't always have to result in unsable ripple 😋
> I'll give it a chance and see how bad it really is, have definately worked with worse things












i hope thats stable now. =)

what would be the next step ? try flat 14s ? or go 1T ? =)

best regards, 

pete


----------



## domdtxdissar

danakin said:


> View attachment 2490116
> 
> 
> i hope thats stable now. =)
> 
> what would be the next step ? try flat 14s ? or go 1T ? =)
> 
> best regards,
> 
> pete











TM5 need to be run in admin mode.. Right click on icon and run in admin-mode next time you test settings
Also set 25 cycles in the cfg as some problems only manifest above 20 cycles in my experience.

50 degrees on memory is also alittle on the highside.. Maybe consider putting a fan on the sticks ?

Happy tuning


----------



## mongoled

Pegasuss said:


> Testing tWR at 10 right now, looking stable but will wait for testmem5 extreme1 to finish. I can do tRP at 13, tRAS 22-27, and tRC at 35-40 but read bandwidth decreases, which I have no idea why, guess lower isnt always better. I'll try to do tRCDRD 14 again, and see if I can make it work but last time I did a quick check it didnt.


The recently discovered trick for 1T GDM disabled using 32GB is to set AddrCmdSetup/CsODTSetup/CkeSetup to 56-56-56

For me tWR @10 was stable for 2T GDM disabled but not for 1T GDM disabled, I had to move tWR to 12 for TM5 stability.

The mantra should change, lower is not always better, but getting timings in sync is the new mantra

"Get Timings In Sync"

 

@Dreamic,

dude take a chill pill! I understand your POV, but I dont understand the manner you are putting it across !

Dont see the reason you are getting uptight about what voltages people push through their dimms (well thats a lie, I do have an inkling ...), the dimms belong to them and as long as they are not impeding the way you live your life then you should not be letting your ego govern your head.

I totally agree that many of us are pushing more voltages for small gains, but thats what some of us like doing, living on the edge while being as stable as we can, there is nothing more to it.

What peeps do with things they own should not get you all worked up.

Forget about the "sheets" out there where people can put what ever results they like in them, you should do better in not allowing such things to effect the way you feel and thus act.

Most of us are here to have fun and share our experiences, hopefully we can get back on track


----------



## RHBH

lmfodor said:


> I don’t know if you have a dual rank mems, but for me that works was to set the CADBUS setup to 56-56-56. See my timings above. I always received BSOD when trying to activate 1T, and with those values it works perfect.
> 
> 
> Sent from my iPhone using Tapatalk Pro


It didn't work here 

Maybe need more try and error in the other CAD Bus settings.


----------



## TimeDrapery

Well...!








Pretty sure my dick just got hard 😂😂😂😂😂



mongoled said:


> Spoiler
> 
> 
> 
> The recently discovered trick for 1T GDM disabled using 32GB is to set AddrCmdSetup/CsODTSetup/CkeSetup to 56-56-56
> 
> For me tWR @10 was stable for 2T GDM disabled but not for 1T GDM disabled, I had to move tWR to 12 for TM5 stability.
> 
> The mantra should change, lower is not always better, but getting timings in sync is the new mantra
> 
> "Get Timings In Sync"
> 
> 
> 
> @Dreamic,
> 
> dude take a chill pill! I understand your POV, but I dont understand the manner you are putting it across !
> 
> Dont see the reason you are getting uptight about what voltages people push through their dimms (well thats a lie, I do have an inkling ...), the dimms belong to them and as long as they are not impeding the way you live your life then you should not be letting your ego govern your head.
> 
> I totally agree that many of us are pushing more voltages for small gains, but thats what some of us like doing, living on the edge while being as stable as we can, there is nothing more to it.
> 
> What peeps do with things they own should not get you all worked up.
> 
> Forget about the "sheets" out there where people can put what ever results they like in them, you should do better in not allowing such things to effect the way you feel and thus act.
> 
> Most of us are here to have fun and share our experiences, hopefully we can get back on track


DUDE!!! You're some kinda full-grown baby genius or something... 56 56 56 is the ticket to the dog show for sure!


----------



## mongoled

TimeDrapery said:


> Well...!
> View attachment 2490121
> 
> Pretty sure my dick just got hard 😂😂😂😂😂
> 
> 
> 
> DUDE!!! You're some kinda full-grown baby genius or something... 56 56 56 is the ticket to the dog show for sure!


Credit is not mine!

Unsure who, 

please put hands up who is responsible


----------



## TimeDrapery

mongoled said:


> Credit is not mine!
> 
> Unsure who,
> 
> please put hands up who is responsible


Man, that's wild... I've been reading and reading those posts on the Korean forum and trying to find a better translator for the ChipHell pages and I've yet to do so

So, from what I've gathered, these setup timings are AL but for the commands themselves? That's so cool 😎😎😎😎😎


----------



## mongoled

RHBH said:


> It didn't work here
> 
> Maybe need more try and error in the other CAD Bus settings.


Post a ZenTimings screenshot see if we can spot anything ..


----------



## DeletedMember558271

mongoled said:


> Credit is not mine!
> 
> Unsure who,
> 
> please put hands up who is responsible


We need to find the person responsible and task them with finding a solution for the 1900 FCLK no post issue so many people are having, so I can have 3800/1900 and love them forever lol.
This 56-56-56 is working for me now too, without changing anything from my previous ZenTimings screenshots except bumping vDIMM to 1.50v temporarily and its been 20 minutes stable in TM5, so definitely workable if it throws out an error at some point. Then it's just what do I have to do/raise to be able to go back down to 1.450v, no way that's stable from 2T without changing anything when 1.440v would error.

This is cool though, and it seems like all my time just working on going to 2T isn't completely wasted, it's probably pretty close to what my 1T will be, raising a few timings here and there. These new findings almost make me feel better about not being able to run 3800/1900, almost makes up for it, better than 3733/1867 GDM On forever anyway for sure. It's not as bad anymore but even if it doesn't matter much 3800/1900 is just such a nicer looking round number lol... I want it.

Maybe someday a discovery will come out for that, an AMD miracle it would be and whoever finds it will be a hero


----------



## Danny.ns

I will try this 56-56-56 tip and report back. Normally when I enable 1T (even with just XMP loaded) I can not even reach Windows, PC hard crash after windows loading bar and I have to reset BIOS/CMOS 2-4 times before I can even get back to Windows.

I will never stop being annoyed at the no POST 3800/1900 bug. I would be happy if 1933, 1966 and 2000 didnt POST - at least it would make sense and I can accept that I simply have a trash IMC. But when so many have the same random "anything BUT fclk1900 can POST" it just becomes this annoying random **** bug that you are stuck with despite spending on expensive hardware. Or if 1900 would POST and throw WHEAs like 1933, that would be fine too. It is the fact that it simply refuses to even try that annoys the hell out of me.


----------



## Pegasuss

mongoled said:


> The recently discovered trick for 1T GDM disabled using 32GB is to set AddrCmdSetup/CsODTSetup/CkeSetup to 56-56-56
> 
> For me tWR @10 was stable for 2T GDM disabled but not for 1T GDM disabled, I had to move tWR to 12 for TM5 stability.


Setup timings 56-56-56 allows 1T gdm off to work but in term of latency a tuned 2T performs the same? Not sure what it does but read bandwidth increases with it. 

Also, I think I saw a post somewhere where 56-0-0 might be better since CsOdtSetup and CkeSetup goes before AddrCmdSetup? I dont know if it makes a difference though.


----------



## DeletedMember558271

Ok uh maybe I actually barely have to do anything to go from 2T to 1T, it's not erroring like crazy even though the only changes I've made are 56-56-56 and 1T. I maxed 2T and 1.450v to its limits and switching to 1T it's just working, ZenTimings shows 1.460v but it's actually reported as 1.448v-1.452v, same as I had before with 2T.
Pleasant surprise this isn't demanding any more power or relaxing of any timings or anything, literally free performance completely happy with everything I had set up before it seems, or it's not going to take too much work if there is an error I think, it's close to stable IMO if it's not already.












Danny.ns said:


> I will try this 56-56-56 tip and report back. Normally when I enable 1T (even with just XMP loaded) I can not even reach Windows, PC hard crash after windows loading bar and I have to reset BIOS/CMOS 2-4 times before I can even get back to Windows.
> 
> I will never stop being annoyed at the no POST 3800/1900 bug. I would be happy if 1933, 1966 and 2000 didnt POST - at least it would make sense and I can accept that I simply have a trash IMC. But when so many have the same random "anything BUT fclk1900 can POST" it just becomes this annoying random **** bug that you are stuck with despite spending on expensive hardware. Or if 1900 would POST and throw WHEAs like 1933, that would be fine too. It is the fact that it simply refuses to even try that annoys the hell out of me.


Yea, I'm always going to wonder if it's actually impossible or if there's just a secret like this I'll never find... never going to be happy looking at 3733/1867, just feels like compromise, subpar.
I'm not as much of a believer of 1933+ WHEA-free, but I know I could be 1900 WHEA-free, if I could have 1900... almost seems like a more realistic wish to have. Most people get 1900 and nobody really has WHEA there

EDIT: 40 minutes stable now, about to run overnight


----------



## mongoled

Pegasuss said:


> Also, I think I saw a post somewhere where 56-0-0 might be better since CsOdtSetup and CkeSetup goes before AddrCmdSetup? I dont know if it makes a difference though.


Need to retest those, as when I tested that I was getting errors in TM5, but I now know those errors are to do with tWR...



Dreamic said:


> Ok uh maybe I actually barely have to do anything to go from 2T to 1T, it's not erroring like crazy even though the only changes I've made are 56-56-56 and 1T. I maxed 2T and 1.450v to its limits and switching to 1T it's just working, ZenTimings shows 1.460v but it's actually reported as 1.448v-1.452v, same as I had before with 2T.


Yes, no voltage changes were necessary using 56-56-56


----------



## DeletedMember558271

mongoled said:


> Yes, no voltage changes were necessary using 56-56-56


I was just expecting to have to do some amount of work lol, there's like no reason for anyone to be running 2T anymore


----------



## ManniX-ITA

mongoled said:


> Credit is not mine!
> 
> Unsure who,
> 
> please put hands up who is responsible


Credit goes to @rissie if I'm not wrong?

I had stability issues with 56-0-0 but I'm not 100% sure it was that, have to test better

Mind that I was using 61-61-61 on the AORUS Master. It may also depends on the DIMM PCB type.
If it's not working try every value between 54 and 62 they are the most likely winners.
With 56 I couldn't POST with the Master.
Working from 59 to 62 but only 61 was stable.



Dreamic said:


> Ok uh maybe I actually barely have to do anything to go from 2T to 1T, it's not erroring like crazy even though the only changes I've made are 56-56-56 and 1T. I maxed 2T and 1.450v to its limits and switching to 1T it's just working, ZenTimings shows 1.460v but it's actually reported as 1.448v-1.452v, same as I had before with 2T.


With Setup timings is not real 1T, the performances are in between; it makes sense that it doesn't ask much more in voltage, same for me.

Zentimings always reports a +0.1V on top (info from the author)


----------



## RHBH

mongoled said:


> Post a ZenTimings screenshot see if we can spot anything ..


Any tips for 1T?

I got 2hrs without errors using 1.42v, maybe I can lower the voltage some more with this settings.


----------



## lmfodor

ManniX-ITA said:


> Credit goes to @rissie if I'm not wrong?
> 
> With Setup timings is not real 1T, the performances are in between; it makes sense that it doesn't ask much more in voltage, same for)


Hi Mannix, why with the new setup timings is not real 1T? For what I read it seems it add a delay and it would align the command rate. I thought it was a resistance like the CADBUS but it’s not, just a delay. So It make sense that it allow us to enable 1T. Did you understand the same?


Sent from my iPhone using Tapatalk Pro


----------



## domdtxdissar

What tests should be run for a 30min stability check of dram and soc ?
And how many seconds per test ?


----------



## RonLazer

Zentimings and MSI software both report DRAM voltage 1 tick higher on the unify-x, I'm fairly sure it's just a trick to make the board seem better at memory overclocking by shoving in more voltage.

As for how to get 2000MHz FCLK with no WHEAs? Run Windows 1909. It's not a real hardware limitation, the AMD bootloader isn't programmed for proper link calibration over 1900 it seems. After doing more voltage testing I think it's because you need quite a bit more SOC and PLL voltage to not see some performance regression, and AMD probably didn't want people buying 4000MHz XMP kits and then running 1.2V SOC and 2.0V PLL daily while gaming or video encoding or whatever.

Unless some new AGESA changes something drastically, I suspect that 1900MHz will remain the highest daily usable FCLK on Zen3.


----------



## lmfodor

domdtxdissar said:


> What tests should be run for a 30min stability check of dram and soc ?
> And how many seconds per test ?
> View attachment 2490173


Hi! try all test 1-7-0, at least four iteration. Is the best way to find any kind of error


----------



## mongoled

RHBH said:


> Any tips for 1T?
> 
> I got 2hrs without errors using 1.42v, maybe I can lower the voltage some more with this settings.
> 
> View attachment 2490142


When Imfodor explained to you to use 56-56-56, you posted back to say "it didnt work"

What exactly does "it didnt work" mean, could you not post, were you getting bluescreens or simply errors in TM5 ???

Your timings seem to be OK accept tWR which you have set @12, as you have tRTP set @8 you should set tWR to 16.


----------



## lmfodor

RonLazer said:


> Zentimings and MSI software both report DRAM voltage 1 tick higher on the unify-x, I'm fairly sure it's just a trick to make the board seem better at memory overclocking by shoving in more voltage.
> 
> As for how to get 2000MHz FCLK with no WHEAs? Run Windows 1909. It's not a real hardware limitation, the AMD bootloader isn't programmed for proper link calibration over 1900 it seems. After doing more voltage testing I think it's because you need quite a bit more SOC and PLL voltage to not see some performance regression, and AMD probably didn't want people buying 4000MHz XMP kits and then running 1.2V SOC and 2.0V PLL daily while gaming or video encoding or whatever.
> 
> Unless some new AGESA changes something drastically, I suspect that 1900MHz will remain the highest daily usable FCLK on Zen3.
> 
> I'll post my graphs in a minute to show what I mean.


Hi RonLazer, yes, I just asked Veii how so many user are running above 4000 without any WHEA. Yesterday I tried 3966/1833, and even passing al TM5 test, I had a lot of WHEAs. I really don´t know how they run it without any error..


----------



## mongoled

lmfodor said:


> Hi RonLazer, yes, I just asked Veii how so many user are running above 4000 without any WHEA. Yesterday I tried 3966/1833, and even passing al TM5 test, I had a lot of WHEAs. I really don´t know how they run it without any error..


Sorry, but I dont see many people running above 4000 without WHEA!

I only see a handful of people and some of those people may be running 1909 which does not have WHEA warning messages appearing in the event log.

On a side note I can now stop trying for tRCDRD @14 !

I tested each dimm seperatly, 3 of the 4 dimms can run my 24/7 settings with tRDCRD @14, but for one of them it is not possible has to be set @15.

So unless I buy another set and roll the dice, tRCDRD @14 for all for dimm modules will not be possible


----------



## lmfodor

mongoled said:


> When Imfodor explained to you to use 56-56-56, you posted back to say "it didnt work"
> 
> What exactly does "it didnt work" mean, could you not post, were you getting bluescreens or simply errors in TM5 ???
> 
> Your timings seem to be OK accept tWR which you have set @12, as you have tRTP set @8 you should set tWR to 16.


Yes, I also noticed that TWCL should be 15 instead of 14, it is not strictly necessary with GDM disabled, but if the value of tWCL is lower than the tCL, it should increase +1 tRDWR to be in sync considering it has a single rank. I would also add a bit more voltage, testing +1 VDIMM to see if it can actually work.


----------



## lmfodor

mongoled said:


> Sorry, but I dont see many people running above 4000 without WHEA!
> 
> I only see a handful of people and some of those people may be running 1909 which does not have WHEA warning messages appearing in the event log.
> 
> On a side note I can now stop trying for tRCDRD @14 !
> 
> I tested each dimm seperatly, 3 of the 4 dimms can run my 24/7 settings with tRDCRD @14, but for one of them it is not possible has to be set @15.
> 
> So unless I buy another set and roll the dice, tRCDRD @14 for all for dimm modules will not be possible


Yes, I think the same. That's why yesterday I asked Veii why he is one of the TOP in the ranking (the spreadsheet with the best values) and it is assumed that any value that is published there should not have any WHEA errors. Hope AMD fixes it ASAP. The increase in bandwitdh is quite impressive.

As for tRCDRD at 14, yes, another obsession, I mean, just to try, or keep trying. I know it is difficult and more for dual range memories, but I am trying to figure out the voltage timing. I'm reading a lot from different sources about how the timings work and I also know that being close to the theoretical maximum of 60MB/s, so I don't know how much improvement it has to lower the tRCDRD in 3800. But if in 4000, there it makes sense, at least to try 14-14-15-14 or similar.


----------



## PJVol

lmfodor said:


> it is assumed that any value that is published there should not have any WHEA errors


Wondering, why there's no requirement for the GPU being 3dmark TimeSpy Mega-ultra-extreme stable, as well as fully illuminated rgb led and so on...


----------



## ManniX-ITA

lmfodor said:


> Hi Mannix, why with the new setup timings is not real 1T? For what I read it seems it add a delay and it would align the command rate. I thought it was a resistance like the CADBUS but it’s not, just a delay. So It make sense that it allow us to enable 1T. Did you understand the same?


Yes it's a delay; the bandwidth is greater but the latency isn't better than 2T.
I can't stabilize it with latency, there's always a 0.1-0.2ns on top and some random 0.5ns.


----------



## TimeDrapery

It seems pretty "real" to me!!!


----------



## lmfodor

ManniX-ITA said:


> Yes it's a delay; the bandwidth is greater but the latency isn't better than 2T.
> I can't stabilize it with latency, there's always a 0.1-0.2ns on top and some random 0.5ns.


Yes, the same thing happens to me, with an additional latency of 0.1 or 0.2ns. But the bandwidth is much better with 1T. I'm still playing around with the voltage and then I'll fix some timings. I would try a tCL tWCL the same, then I will try a lot of tRDWR at 9 and maybe the highest tWRRD, but for that I will need tRCDRD at 15 ... let's see how it goes 

Also, I updated to the latest version of SMU, so inter-core latency is worse ... but I was able to run 3966 with 53.x ns, great, but with a lot or WHEA.


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

RonLazer said:


> Zentimings and MSI software both report DRAM voltage 1 tick higher on the unify-x, I'm fairly sure it's just a trick to make the board seem better at memory overclocking by shoving in more voltage.


I don't think so, it's the same on Gigabyte.
Infrared, who's Zentmings author, said that he's aware of it.
My guess is how the motherboard is writing this information maybe it's not right.
A rounding error and then when it's read from SMU goes a tick above.
Did you check with the ASUS?



PJVol said:


> Wondering, why there was no requirement for the gpu being 3dmark TimeSpy Mega-ultra-extreme stable, as well as fully illuminated rgb led and so on...


LoL, I'm in. Let's add proof of purchase of a barbecue grill as well


----------



## nexxusty

TimeDrapery said:


> It seems pretty "real" to me!!!
> View attachment 2490179


Your latency is very high for those speeds/timings.


----------



## mongoled

nexxusty said:


> Your latency is very high for those speeds/timings.


He is using a 3000 series CPU so its actually very very good


----------



## lmfodor

PJVol said:


> Wondering, why there's no requirement for the GPU being 3dmark TimeSpy Mega-ultra-extreme stable, as well as fully illuminated rgb led and so on...


Hi PJVol, There is no need for so much sarcasm. Why are people so defensive? Just knowing if what is published is stable, as it says in red, that there should be no WHEAs, which is a problem that seems to affect almost all of us, is just that. It is not a question of breaking benchmarks but of seeking to be stable, or am I wrong? maybe I was misinterpret the spreadsheet, which is very good for reference by the way [emoji6]


Sent from my iPhone using Tapatalk Pro


----------



## mongoled

ManniX-ITA said:


> LoL, I'm in. Let's add proof of purchase of a barbecue grill as well


You will cook "Souvlakia" for us all


----------



## nexxusty

mongoled said:


> He is using a 3000 series CPU so its actually very very good


That's what I get for commenting after just waking up and not being able to see.

Lol. Absolutely.


----------



## Danny.ns

As promised I tested 56-56-56 and indeed, for the first time ever I can reach Windows and even run Aida64 with 1T (GDM Disabled).

However, I am not seeing any benefits. My read bandwidth is ~300mb/s slower - consistenly 58000 vs 58300 with GDM enabled. My latency is exactly the same at 55.0 - 55.2.


----------



## Veii

56/56/56 is really interesting
It should not be pure 2T as thats 61/61/61 or i think it was 63/63/63
The korean bbs sheet shows the cutting times

The Problem i have with this, is that tCKE should not be different
And i wonder if such high value prohibts RTT_WR from working completely
~ somebody can test if RTT_WR disabled would destabilize it then
Seeing that any old SETUP Timings can not work anymore with RTT_WR
It makes me really wonder if this is skipped

You should probably also run X-20-20-20 when you fully rely on SETUP timings
Bad 3rd value ahould show well with memory training issues and cold boot issues
Honestly don't think you need it that high
Somebody could also try if 27/27/56 could work out, or a pure 27/27/27
Just seeing dynamicODT causes issues with it, you probably wont have a good time with it enabled

Test it 
Or if 26/26/26 or 27/27/27 works, it wont have the 2T penalty and actually behave similar to lower than 16 tCKE
56/56/56 sounds to me reversed, hard to explain
Anyways X-20-20-20 it is, if you're going to use SETUP Timings
Although really look into CKE and RTT_WR with it. Syncing all 3 did not work yet for me
Either CKE+SETUP or RTT_WR+CKE
Alone usage of RTT_WR didn't really need CKE, but i like the powerdown feature with it
Setting it will ignore PDM flag in the bios, it bypasses it
CKE-1 is constantly on
CKE 9-16 is constantly on till its not needed anymore
tCKE 17-32 is sleeping with wake up spikes

Soo maaybe 25 could work out for 3800MT/s , if you see stability with SETUP timings
Or 26 for 3734MT/s . likely also
The only thing i'm not entirely sure is the range after CKE 16
Is it again 36 - something for freq
Or is it 17+ something for freq 🤔
It would make sense to be reversed, like SETUP timings are

Should be enough options to test out
Probably the key thing is, what of the 3 values is needed to be delayed and cut after specific uptime value
And at which range RTT_WR does influence it
Something honestly i have to test too (as my setup times are broken too) but SMU 56.50 has far bigger problems like a completely different behaving IMC FW. Getting this finally stable with less cpu voltages , has priority 

@lmfodor WHEA 19s are mostly IO related
To proof this i need to get this ProArt running als0 2066+ FCLK. We'll see on that topic
It has to do with the IO die and board IO. Same as with PCIe 4.0 which was known to crash above 2000 FCLK
(See the 8 lanes cut on Renoir mobile, or 1900 FCLK enforced lock on Matisse)
Same thing was tried to be done here
SOC FUSE limit is not factoring any SOC increase beyond 1.2v and is not factoring edc cut by anything higher than 1900 FCLK
Soo package throttle (instability) or EDC throttle (budget throttle) are common issues you'll face exceeding 1933
If AMD is really annoying, they could mark WHEA reports also on package throttling. I dont know as it doesnt report them
I get #18s if i'm doing really stupid things, but no 19's
It's either hidden throttle, or obvious insta crashes and reboots.
While i mentioned very far ago, that Vermeer is fantastic at auto correction. It's really quite an annoying CPU to OC "cleanly" 

You should check if enabling [AER CAP & then ACS with it] ~ CBS->NBIO
and also SRIS (helps PCIe devices with BCLK changes or overall variance)
Does anything to your WHEA situation

I do think Ron is right with the calibration part
But i never had to touch CPU VDD beyond 1.83v (stock here)
Nor VPPM beyond 2.53 or changes to the 2.5v rail (although it does push itself on stock to 2.55, 2.50 manually works equally well)
Soc is predicted at 1.25v after i exceed 2000 FCLK
Else mostly its 50mV higher than it has to be (if i go with the offset scale)
1900 keeps it at 1.1, soo the old posted minimum SOC voltage scale, still applies
High SOC does cover up some mistakes as it seems, but VDDG for example has its mind on their own and does autocorrect anyways. Only by getting it as close as possible to IOD, 1.8v VDD line started to show and make any changes. With enough SOC any increase on VDD caused crashes or fully no post
Havent tired undervolting that one tho
Hmm no other significant change here.

Soo if ProArt is stable too, then my suspicion remains IO & especially Realtek buggy NUC
Only both ITX lineups have no WHEA 19s, but do strongly autocorrect when issues are there, or hardcrash
We mostly hardcrash , autocorrelation only happens with VDDG and SOC, mostly EDC throttle or VDDG stability related
Nothing else really
Soo we'll see
X570 did no change to maximum FCLK except that EDC throttle was annoying and VDDG values generally where different between both chipsets


----------



## RHBH

mongoled said:


> When Imfodor explained to you to use 56-56-56, you posted back to say "it didnt work"
> 
> What exactly does "it didnt work" mean, could you not post, were you getting bluescreens or simply errors in TM5 ???
> 
> Your timings seem to be OK accept tWR which you have set @12, as you have tRTP set @8 you should set tWR to 16.


I meant that I had the same result, F9 error code (no POST).

I will change tWR to 16.

Does tWR always need to be tRP x 2?
What about tWR @12 and tRP @6?

Also, sometimes I have cold boot issues (memory train 1 or 2 times before post), should I change some CAD Bus value?


----------



## TimeDrapery

lmfodor said:


> Spoiler
> 
> 
> 
> Hi PJVol, There is no need for so much sarcasm. Why are people so defensive? Just knowing if what is published is stable, as it says in red, that there should be no WHEAs, which is a problem that seems to affect almost all of us, is just that. It is not a question of breaking benchmarks but of seeking to be stable, or am I wrong? maybe I was misinterpret the spreadsheet, which is very good for reference by the way [emoji6]
> 
> 
> Sent from my iPhone using Tapatalk Pro


@lmfodor 

Oh I think he's just giving ya grief, not likely to be anything personal

The Google Sheets doc is a great reference but it seems, to me, there's a fundamental misunderstanding regarding what that document is and how it's maintained

The results contained within it are excellent indicators of what's possible when you're running similar hardware and you're equipped with (at least) a working knowledge of how to best configure said hardware to take advantage of its positive characteristics while minimizing the impact of the setup's negative characteristics

Considering it wasn't all that long ago that competitive overclocks started talking about binning motherboards in order to attain better memory OC results I'm gonna guess that there are likely some results posted there that truly do not produce WHEA errors while in use and there are some that do, as well as some that do (and the poster conceals them or isn't aware of their existence)

When I look at a pile of (relatively) randomly collected data like that I don't bother trying to find a single line that contains the closest setup to mine and then copy it, I look at averages and outliers and then attempt to see the differences between the configurations and search further to see if I can identify trends that might lead me on the right path to attaining the goals I set out to attain

Think of it like a dictionary attack, it doesn't help me to have a list of "known good" passwords (I mean, it does, but that's an altogether different situation as I'm talking about the method here and not the result) that work the first time I attempt to access an account... It helps to have a _large_ list of passwords that _could_ be good as evidenced by the fact that someone used them in an attempt to secure something at some point in the past

I'm not going to bother sifting through my list to find only passwords that work first time, I'm going to use my really big list to find a password that suits my needs now by allowing my system(s) to do its thing with that big wordlist so I can focus on the finer details

While I'm doing that, the system will mutate the list if necessary in order to expand it, changing things like the amount of special characters or some other such variable to better accommodate different password rules

I'm a way this is similar to how I use something like those Sheets documents... You can't pay too much attention to the fine details there as, even if they were error free, they're not likely to be PnP for your exact setup... Especially when there's a known issue like the WHEA business prevalent "in the wild", but it can get you in the ballpark

There's another part of those Sheets docs that's helpful... The usernames... Search them... Read what they've got to say at various spots around the 'net as it's _entirely_ possible they're geniuses

It's also entirely possible (in an infinite universe) for a quadrillion apes banging away on typewriters to _eventually_ reproduce the complete works of Shakespeare


----------



## TimeDrapery

Veii said:


> Spoiler
> 
> 
> 
> 56/56/56 is really interesting
> It should not be pure 2T as thats 61/61/61 or i think it was 63/63/63
> The korean bbs sheet shows the cutting times
> 
> The Problem i have with this, is that tCKE should not be different
> And i wonder if such high value prohibts RTT_WR from working completely
> ~ somebody can test if RTT_WR disabled would destabilize it then
> Seeing that any old SETUP Timings can not work anymore with RTT_WR
> It makes me really wonder if this is skipped
> 
> You should probably also run X-20-20-20 when you fully rely on SETUP timings
> Bad 3rd value ahould show well with memory training issues and cold boot issues
> Honestly don't think you need it that high
> Somebody could also try if 27/27/56 could work out, or a pure 27/27/27
> Just seeing dynamicODT causes issues with it, you probably wont have a good time with it enabled
> 
> Test it
> Or if 26/26/26 or 27/27/27 works, it wont have the 2T penalty and actually behave similar to lower than 16 tCKE
> 56/56/56 sounds to me reversed, hard to explain
> Anyways X-20-20-20 it is, if you're going to use SETUP Timings
> Although really look into CKE and RTT_WR with it. Syncing all 3 did not work yet for me
> Either CKE+SETUP or RTT_WR+CKE
> Alone usage of RTT_WR didn't really need CKE, but i like the powerdown feature with it
> Setting it will ignore PDM flag in the bios, it bypasses it
> CKE-1 is constantly on
> CKE 9-16 is constantly on till its not needed anymore
> tCKE 17-32 is sleeping with wake up spikes
> 
> Soo maaybe 25 could work out for 3800MT/s , if you see stability with SETUP timings
> Or 26 for 3734MT/s . likely also
> The only thing i'm not entirely sure is the range after CKE 16
> Is it again 36 - something for freq
> Or is it 17+ something for freq 🤔
> It would make sense to be reversed, like SETUP timings are
> 
> Should be enough options to test out
> Probably the key thing is, what of the 3 values is needed to be delayed and cut after specific uptime value
> And at which range RTT_WR does influence it
> Something honestly i have to test too (as my setup times are broken too) but SMU 56.50 has far bigger problems like a completely different behaving IMC FW. Getting this finally stable with less cpu voltages , has priority
> 
> @lmfodor WHEA 19s are mostly IO related
> To proof this i need to get this ProArt running als0 2066+ FCLK. We'll see on that topic
> It has to do with the IO die and board IO. Same as with PCIe 4.0 which was known to crash above 2000 FCLK
> (See the 8 lanes cut on Renoir mobile, or 1900 FCLK enforced lock on Matisse)
> Same thing was tried to be done here
> SOC FUSE limit is not factoring any SOC increase beyond 1.2v and is not factoring edc cut by anything higher than 1900 FCLK
> Soo package throttle (instability) or EDC throttle (budget throttle) are common issues you'll face exceeding 1933
> If AMD is really annoying, they could mark WHEA reports also on package throttling. I dont know as it doesnt report them
> I get #18s if i'm doing really stupid things, but no 19's
> It's either hidden throttle, or obvious insta crashes and reboots.
> While i mentioned very far ago, that Vermeer is fantastic at auto correction. It's really quite an annoying CPU to OC "cleanly"
> 
> You should check if enabling [AER CAP & then ACS with it] ~ CBS->NBIO
> and also SRIS (helps PCIe devices with BCLK changes or overall variance)
> Does anything to your WHEA situation
> 
> I do think Ron is right with the calibration part
> But i never had to touch CPU VDD beyond 1.83v (stock here)
> Nor VPPM beyond 2.53 or changes to the 2.5v rail (although it does push itself on stock to 2.55, 2.50 manually works equally well)
> Soc is predicted at 1.25v after i exceed 2000 FCLK
> Else mostly its 50mV higher than it has to be (if i go with the offset scale)
> 1900 keeps it at 1.1, soo the old posted minimum SOC voltage scale, still applies
> High SOC does cover up some mistakes as it seems, but VDDG for example has its mind on their own and does autocorrect anyways. Only by getting it as close as possible to IOD, 1.8v VDD line started to show and make any changes. With enough SOC any increase on VDD caused crashes or fully no post
> Havent tired undervolting that one tho
> Hmm no other significant change here.
> 
> Soo if ProArt is stable too, then my suspicion remains IO & especially Realtek buggy NUC
> Only both ITX lineups have no WHEA 19s, but do strongly autocorrect when issues are there, or hardcrash
> We mostly hardcrash , autocorrelation only happens with VDDG and SOC, mostly EDC throttle or VDDG stability related
> Nothing else really
> Soo we'll see
> X570 did no change to maximum FCLK except that EDC throttle was annoying and VDDG values generally where different between both chipsets





Veii said:


> Honestly don't think you need it that high
> 
> Somebody could also try if 27/27/56 could work out, or a pure 27/27/27


@Veii 

This is what I was thinking to try next... I thought 28 though, why 27?


----------



## Veii

RHBH said:


> I meant that I had the same result, F9 error code (no POST).
> 
> I will change tWR to 16.
> 
> Does tWR always need to be tRP x 2?
> What about tWR @12 and tRP @6?
> 
> Also, sometimes I have cold boot issues (memory train 1 or 2 times before post), should I change some CAD Bus value?


I do have another method for it, but even it it looks stable, it sometimes can not be
Use tRFC mini or do the TRFCns math yourself
Turn that random timing value to ns
See if it divides down to 1 decimal or at worst a .25 value
If it does, it's gonna work. If it doesn't its going to time out soon or later

I use the manual mode , the value to ns converter
Often to my advantage for such ~ as the sheet has the potential rounding fixed by working with integers only and no real-world values

Turn your for example 6 to ns
Make a little formula on the right side or where you can edit
Take the turned ns values from the colour box bellow and divide them by the result you get on the right side of the sheet
Now just change that manual value from 5-12 and see which values remain clean dividers and which are half sync or 1/4th , these you can still use without breaking stability
But performance can suffer, soo the most basic and easiest method is either to match tRFC * something = tRTP 
Or to match half of tWR 
Logically for odd values on tWR and tRTP you need GDM off

Well or find that OCN Community calculator, which has tRTP calculations in there
Surely there is a more scientific method, but these are the esoteric ones i know that remain stable


----------



## Veii

TimeDrapery said:


> @Veii
> 
> This is what I was thinking to try next... I thought 28 though, why 27?


CKE & Setup times depend on the MT/s
I wasnt sure if its for 3734 or 3800
Thinking more about it, it makes sense why i run CkeSetupTime as 15 before
It's hard to explain because i forgot the range of these things
1-1-1 was helpful back on Zen1/2 days
56-56-56 was a 3467MT/s thing mostly

I forgot the maximum scale of it, to do the math
Forgot the listed ranges and when it changes behavior, where the half cut is
On CKE it's 16 and the board for me also predicts 16 if i auto CKE

But RTT, CKE, SETUP Timings work ~ goes back to my post for "taming voltage and PCB stability"
If we want to take that route for everyone
Then A.) It needs calculated research for each MT/s step
And B.) We all should accept pushing more voltage and skipping the mindset about the "high and dangerous" part of voltages

It can happen that someone of us messes up and fries their PCB or even others
Soo unless everyone is fine with this and accepts the warning
I don't think it's a good idea to explore termination impedances and change "stock" powerdown behavior
This is advanced stuff, as cheesy as it is to say ~ and requires a rock stable flat set without any variance. 

I've let by accident one A0 die and nearly my own too ~ soo the warning is here for a reason
It was not the voltage that killed it but the RTTs in combination with the "beyond average" high voltage
Soo if you want to take that route, be sure to know it can deal damage and it often is save to push higher voltage, as the end result is not dangerously high (A)


----------



## domdtxdissar

The deed is done, have gotten this fully stable 

BIOS 3501 with AGESA V2 PI 1.2.0.2
dual CCD 5950x
4x8GB gskill 3600 CL16
1900:3800 @ flat CL14 + T1 GDM-OFF
Screenshot of TM 1umus 25 cycle + Memtest 20000% stable (do notice this is my old bloaty windows install with lots of stuff running in background)










Newest OCCT 8.1.3 1 hour large dataset extreme + 4 iteration in y-cruncher with all tests (same boot as above)









Some performance number:
The SiSoftSandra v2021.31.12 (from Mar 5th, 2021). Not sure this is a good match with CTR..
Intel latency checker










> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 157.9GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Aggregate Inter-Thread Latency : 44.5ns (12.2ns - 69.5ns)
> Inter-Thread (same Core) Latency : 12.7ns
> Inter-Core (same Module) Latency : 25.7ns
> Inter-Module (same Package) Latency : 63.0ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1539.86MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Aggregate Inter-Thread Latency : 4.24ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 707.05kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 47.55MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Aggregate Inter-Thread Latency : 0.13ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-U2 Data Latency : 26.1ns
> U0-U4 Data Latency : 25.5ns
> U0-U6 Data Latency : 26.0ns
> U0-U8 Data Latency : 23.6ns
> U0-U10 Data Latency : 25.9ns
> U0-U12 Data Latency : 27.0ns
> U0-U14 Data Latency : 26.3ns
> U0-U16 Data Latency : 64.4ns
> U0-U18 Data Latency : 65.7ns
> U0-U20 Data Latency : 67.9ns
> U0-U22 Data Latency : 67.2ns
> U0-U24 Data Latency : 66.9ns
> U0-U26 Data Latency : 66.8ns
> U0-U28 Data Latency : 65.7ns
> U0-U30 Data Latency : 66.6ns
> U0-U1 Data Latency : 12.2ns
> U0-U3 Data Latency : 25.0ns
> U0-U5 Data Latency : 27.0ns
> U0-U7 Data Latency : 26.4ns
> U0-U9 Data Latency : 23.8ns
> U0-U11 Data Latency : 25.7ns
> U0-U13 Data Latency : 26.6ns
> U0-U15 Data Latency : 26.6ns
> U0-U17 Data Latency : 66.1ns
> U0-U19 Data Latency : 66.2ns
> U0-U21 Data Latency : 68.5ns
> U0-U23 Data Latency : 66.3ns
> U0-U25 Data Latency : 67.1ns
> U0-U27 Data Latency : 66.6ns
> U0-U29 Data Latency : 67.0ns
> U0-U31 Data Latency : 66.1ns
> U2-U4 Data Latency : 24.4ns
> U2-U6 Data Latency : 25.6ns
> U2-U8 Data Latency : 28.2ns
> U2-U10 Data Latency : 26.9ns
> U2-U12 Data Latency : 24.6ns
> U2-U14 Data Latency : 25.2ns
> U2-U16 Data Latency : 62.6ns
> U2-U18 Data Latency : 60.1ns
> U2-U20 Data Latency : 59.4ns
> U2-U22 Data Latency : 61.1ns
> U2-U24 Data Latency : 61.2ns
> U2-U26 Data Latency : 60.3ns
> U2-U28 Data Latency : 61.3ns
> U2-U30 Data Latency : 62.1ns
> U2-U1 Data Latency : 25.5ns
> U2-U3 Data Latency : 13.3ns
> U2-U5 Data Latency : 26.4ns
> U2-U7 Data Latency : 24.3ns
> U2-U9 Data Latency : 25.0ns
> U2-U11 Data Latency : 26.9ns
> U2-U13 Data Latency : 24.4ns
> U2-U15 Data Latency : 23.9ns
> U2-U17 Data Latency : 61.1ns
> U2-U19 Data Latency : 59.4ns
> U2-U21 Data Latency : 58.8ns
> U2-U23 Data Latency : 61.1ns
> U2-U25 Data Latency : 61.5ns
> U2-U27 Data Latency : 61.1ns
> U2-U29 Data Latency : 61.5ns
> U2-U31 Data Latency : 61.0ns
> U4-U6 Data Latency : 23.6ns
> U4-U8 Data Latency : 27.0ns
> U4-U10 Data Latency : 25.6ns
> U4-U12 Data Latency : 27.0ns
> U4-U14 Data Latency : 25.2ns
> U4-U16 Data Latency : 63.2ns
> U4-U18 Data Latency : 62.3ns
> U4-U20 Data Latency : 62.6ns
> U4-U22 Data Latency : 60.5ns
> U4-U24 Data Latency : 62.5ns
> U4-U26 Data Latency : 62.2ns
> U4-U28 Data Latency : 62.8ns
> U4-U30 Data Latency : 62.6ns
> U4-U1 Data Latency : 25.7ns
> U4-U3 Data Latency : 25.8ns
> U4-U5 Data Latency : 12.8ns
> U4-U7 Data Latency : 23.8ns
> U4-U9 Data Latency : 26.6ns
> U4-U11 Data Latency : 25.7ns
> U4-U13 Data Latency : 25.5ns
> U4-U15 Data Latency : 25.1ns
> U4-U17 Data Latency : 59.1ns
> U4-U19 Data Latency : 61.5ns
> U4-U21 Data Latency : 61.7ns
> U4-U23 Data Latency : 60.4ns
> U4-U25 Data Latency : 63.2ns
> U4-U27 Data Latency : 61.2ns
> U4-U29 Data Latency : 63.4ns
> U4-U31 Data Latency : 62.1ns
> U6-U8 Data Latency : 25.1ns
> U6-U10 Data Latency : 26.2ns
> U6-U12 Data Latency : 25.7ns
> U6-U14 Data Latency : 25.8ns
> U6-U16 Data Latency : 61.0ns
> U6-U18 Data Latency : 59.6ns
> U6-U20 Data Latency : 62.6ns
> U6-U22 Data Latency : 60.9ns
> U6-U24 Data Latency : 61.4ns
> U6-U26 Data Latency : 61.8ns
> U6-U28 Data Latency : 62.2ns
> U6-U30 Data Latency : 62.2ns
> U6-U1 Data Latency : 24.8ns
> U6-U3 Data Latency : 25.7ns
> U6-U5 Data Latency : 24.0ns
> U6-U7 Data Latency : 12.5ns
> U6-U9 Data Latency : 25.6ns
> U6-U11 Data Latency : 28.0ns
> U6-U13 Data Latency : 25.4ns
> U6-U15 Data Latency : 26.1ns
> U6-U17 Data Latency : 61.7ns
> U6-U19 Data Latency : 60.1ns
> U6-U21 Data Latency : 61.3ns
> U6-U23 Data Latency : 60.8ns
> U6-U25 Data Latency : 62.3ns
> U6-U27 Data Latency : 61.9ns
> U6-U29 Data Latency : 62.3ns
> U6-U31 Data Latency : 62.7ns
> U8-U10 Data Latency : 29.6ns
> U8-U12 Data Latency : 29.3ns
> U8-U14 Data Latency : 28.0ns
> U8-U16 Data Latency : 65.4ns
> U8-U18 Data Latency : 69.0ns
> U8-U20 Data Latency : 66.9ns
> U8-U22 Data Latency : 65.9ns
> U8-U24 Data Latency : 68.2ns
> U8-U26 Data Latency : 67.1ns
> U8-U28 Data Latency : 67.3ns
> U8-U30 Data Latency : 66.8ns
> U8-U1 Data Latency : 23.8ns
> U8-U3 Data Latency : 26.2ns
> U8-U5 Data Latency : 28.8ns
> U8-U7 Data Latency : 27.2ns
> U8-U9 Data Latency : 12.3ns
> U8-U11 Data Latency : 27.8ns
> U8-U13 Data Latency : 29.0ns
> U8-U15 Data Latency : 29.0ns
> U8-U17 Data Latency : 66.9ns
> U8-U19 Data Latency : 65.7ns
> U8-U21 Data Latency : 69.3ns
> U8-U23 Data Latency : 67.7ns
> U8-U25 Data Latency : 66.7ns
> U8-U27 Data Latency : 67.1ns
> U8-U29 Data Latency : 67.5ns
> U8-U31 Data Latency : 66.7ns
> U10-U12 Data Latency : 26.6ns
> U10-U14 Data Latency : 27.6ns
> U10-U16 Data Latency : 63.0ns
> U10-U18 Data Latency : 61.9ns
> U10-U20 Data Latency : 60.7ns
> U10-U22 Data Latency : 62.5ns
> U10-U24 Data Latency : 61.1ns
> U10-U26 Data Latency : 62.3ns
> U10-U28 Data Latency : 63.0ns
> U10-U30 Data Latency : 62.3ns
> U10-U1 Data Latency : 25.2ns
> U10-U3 Data Latency : 25.1ns
> U10-U5 Data Latency : 24.6ns
> U10-U7 Data Latency : 24.9ns
> U10-U9 Data Latency : 26.8ns
> U10-U11 Data Latency : 13.1ns
> U10-U13 Data Latency : 27.7ns
> U10-U15 Data Latency : 27.3ns
> U10-U17 Data Latency : 61.2ns
> U10-U19 Data Latency : 59.9ns
> U10-U21 Data Latency : 60.4ns
> U10-U23 Data Latency : 62.0ns
> U10-U25 Data Latency : 61.7ns
> U10-U27 Data Latency : 61.4ns
> U10-U29 Data Latency : 63.0ns
> U10-U31 Data Latency : 62.9ns
> U12-U14 Data Latency : 27.9ns
> U12-U16 Data Latency : 60.9ns
> U12-U18 Data Latency : 60.6ns
> U12-U20 Data Latency : 61.1ns
> U12-U22 Data Latency : 62.1ns
> U12-U24 Data Latency : 62.6ns
> U12-U26 Data Latency : 61.9ns
> U12-U28 Data Latency : 62.8ns
> U12-U30 Data Latency : 62.7ns
> U12-U1 Data Latency : 26.1ns
> U12-U3 Data Latency : 25.4ns
> U12-U5 Data Latency : 25.7ns
> U12-U7 Data Latency : 25.6ns
> U12-U9 Data Latency : 27.6ns
> U12-U11 Data Latency : 26.7ns
> U12-U13 Data Latency : 12.7ns
> U12-U15 Data Latency : 28.0ns
> U12-U17 Data Latency : 62.4ns
> U12-U19 Data Latency : 61.5ns
> U12-U21 Data Latency : 62.2ns
> U12-U23 Data Latency : 61.3ns
> U12-U25 Data Latency : 62.4ns
> U12-U27 Data Latency : 61.8ns
> U12-U29 Data Latency : 63.0ns
> U12-U31 Data Latency : 62.7ns
> U14-U16 Data Latency : 60.2ns
> U14-U18 Data Latency : 60.8ns
> U14-U20 Data Latency : 60.9ns
> U14-U22 Data Latency : 62.1ns
> U14-U24 Data Latency : 61.3ns
> U14-U26 Data Latency : 63.0ns
> U14-U28 Data Latency : 62.7ns
> U14-U30 Data Latency : 63.2ns
> U14-U1 Data Latency : 25.3ns
> U14-U3 Data Latency : 26.7ns
> U14-U5 Data Latency : 26.3ns
> U14-U7 Data Latency : 25.8ns
> U14-U9 Data Latency : 26.7ns
> U14-U11 Data Latency : 28.2ns
> U14-U13 Data Latency : 28.5ns
> U14-U15 Data Latency : 12.4ns
> U14-U17 Data Latency : 61.2ns
> U14-U19 Data Latency : 62.4ns
> U14-U21 Data Latency : 60.6ns
> U14-U23 Data Latency : 62.7ns
> U14-U25 Data Latency : 62.3ns
> U14-U27 Data Latency : 62.6ns
> U14-U29 Data Latency : 63.0ns
> U14-U31 Data Latency : 63.3ns
> U16-U18 Data Latency : 22.8ns
> U16-U20 Data Latency : 25.5ns
> U16-U22 Data Latency : 24.1ns
> U16-U24 Data Latency : 24.8ns
> U16-U26 Data Latency : 24.1ns
> U16-U28 Data Latency : 25.8ns
> U16-U30 Data Latency : 24.4ns
> U16-U1 Data Latency : 60.7ns
> U16-U3 Data Latency : 59.8ns
> U16-U5 Data Latency : 61.2ns
> U16-U7 Data Latency : 61.3ns
> U16-U9 Data Latency : 63.5ns
> U16-U11 Data Latency : 61.2ns
> U16-U13 Data Latency : 62.3ns
> U16-U15 Data Latency : 60.4ns
> U16-U17 Data Latency : 12.7ns
> U16-U19 Data Latency : 25.6ns
> U16-U21 Data Latency : 26.6ns
> U16-U23 Data Latency : 24.7ns
> U16-U25 Data Latency : 24.1ns
> U16-U27 Data Latency : 24.0ns
> U16-U29 Data Latency : 24.2ns
> U16-U31 Data Latency : 24.3ns
> U18-U20 Data Latency : 24.7ns
> U18-U22 Data Latency : 23.5ns
> U18-U24 Data Latency : 23.9ns
> U18-U26 Data Latency : 25.1ns
> U18-U28 Data Latency : 24.4ns
> U18-U30 Data Latency : 25.6ns
> U18-U1 Data Latency : 65.9ns
> U18-U3 Data Latency : 63.3ns
> U18-U5 Data Latency : 59.2ns
> U18-U7 Data Latency : 61.3ns
> U18-U9 Data Latency : 65.5ns
> U18-U11 Data Latency : 64.1ns
> U18-U13 Data Latency : 63.1ns
> U18-U15 Data Latency : 61.9ns
> U18-U17 Data Latency : 22.8ns
> U18-U19 Data Latency : 12.7ns
> U18-U21 Data Latency : 23.4ns
> U18-U23 Data Latency : 24.6ns
> U18-U25 Data Latency : 24.1ns
> U18-U27 Data Latency : 24.2ns
> U18-U29 Data Latency : 24.3ns
> U18-U31 Data Latency : 24.7ns
> U20-U22 Data Latency : 24.1ns
> U20-U24 Data Latency : 25.6ns
> U20-U26 Data Latency : 24.5ns
> U20-U28 Data Latency : 27.0ns
> U20-U30 Data Latency : 25.4ns
> U20-U1 Data Latency : 64.6ns
> U20-U3 Data Latency : 64.3ns
> U20-U5 Data Latency : 61.0ns
> U20-U7 Data Latency : 59.3ns
> U20-U9 Data Latency : 64.7ns
> U20-U11 Data Latency : 65.5ns
> U20-U13 Data Latency : 62.5ns
> U20-U15 Data Latency : 62.2ns
> U20-U17 Data Latency : 23.6ns
> U20-U19 Data Latency : 24.7ns
> U20-U21 Data Latency : 12.5ns
> U20-U23 Data Latency : 24.1ns
> U20-U25 Data Latency : 25.5ns
> U20-U27 Data Latency : 24.4ns
> U20-U29 Data Latency : 26.8ns
> U20-U31 Data Latency : 25.3ns
> U22-U24 Data Latency : 24.3ns
> U22-U26 Data Latency : 26.3ns
> U22-U28 Data Latency : 25.7ns
> U22-U30 Data Latency : 25.6ns
> U22-U1 Data Latency : 63.4ns
> U22-U3 Data Latency : 64.5ns
> U22-U5 Data Latency : 60.4ns
> U22-U7 Data Latency : 60.5ns
> U22-U9 Data Latency : 64.7ns
> U22-U11 Data Latency : 63.4ns
> U22-U13 Data Latency : 63.2ns
> U22-U15 Data Latency : 62.5ns
> U22-U17 Data Latency : 24.1ns
> U22-U19 Data Latency : 23.7ns
> U22-U21 Data Latency : 24.2ns
> U22-U23 Data Latency : 12.7ns
> U22-U25 Data Latency : 24.7ns
> U22-U27 Data Latency : 24.2ns
> U22-U29 Data Latency : 24.9ns
> U22-U31 Data Latency : 26.9ns
> U24-U26 Data Latency : 26.0ns
> U24-U28 Data Latency : 27.8ns
> U24-U30 Data Latency : 26.0ns
> U24-U1 Data Latency : 65.2ns
> U24-U3 Data Latency : 63.1ns
> U24-U5 Data Latency : 62.7ns
> U24-U7 Data Latency : 60.5ns
> U24-U9 Data Latency : 65.3ns
> U24-U11 Data Latency : 63.9ns
> U24-U13 Data Latency : 63.5ns
> U24-U15 Data Latency : 63.1ns
> U24-U17 Data Latency : 24.3ns
> U24-U19 Data Latency : 23.7ns
> U24-U21 Data Latency : 25.6ns
> U24-U23 Data Latency : 24.3ns
> U24-U25 Data Latency : 12.7ns
> U24-U27 Data Latency : 25.0ns
> U24-U29 Data Latency : 27.1ns
> U24-U31 Data Latency : 27.7ns
> U26-U28 Data Latency : 26.7ns
> U26-U30 Data Latency : 27.9ns
> U26-U1 Data Latency : 64.8ns
> U26-U3 Data Latency : 62.3ns
> U26-U5 Data Latency : 63.8ns
> U26-U7 Data Latency : 62.4ns
> U26-U9 Data Latency : 65.3ns
> U26-U11 Data Latency : 64.9ns
> U26-U13 Data Latency : 63.1ns
> U26-U15 Data Latency : 62.5ns
> U26-U17 Data Latency : 24.2ns
> U26-U19 Data Latency : 25.4ns
> U26-U21 Data Latency : 24.6ns
> U26-U23 Data Latency : 27.0ns
> U26-U25 Data Latency : 26.1ns
> U26-U27 Data Latency : 12.8ns
> U26-U29 Data Latency : 27.9ns
> U26-U31 Data Latency : 27.9ns
> U28-U30 Data Latency : 27.5ns
> U28-U1 Data Latency : 65.4ns
> U28-U3 Data Latency : 64.1ns
> U28-U5 Data Latency : 64.1ns
> U28-U7 Data Latency : 61.6ns
> U28-U9 Data Latency : 64.1ns
> U28-U11 Data Latency : 63.4ns
> U28-U13 Data Latency : 65.1ns
> U28-U15 Data Latency : 63.0ns
> U28-U17 Data Latency : 24.3ns
> U28-U19 Data Latency : 24.7ns
> U28-U21 Data Latency : 24.7ns
> U28-U23 Data Latency : 25.7ns
> U28-U25 Data Latency : 27.8ns
> U28-U27 Data Latency : 27.8ns
> U28-U29 Data Latency : 12.7ns
> U28-U31 Data Latency : 28.7ns
> U30-U1 Data Latency : 64.0ns
> U30-U3 Data Latency : 61.9ns
> U30-U5 Data Latency : 62.1ns
> U30-U7 Data Latency : 62.0ns
> U30-U9 Data Latency : 64.6ns
> U30-U11 Data Latency : 63.4ns
> U30-U13 Data Latency : 63.1ns
> U30-U15 Data Latency : 62.6ns
> U30-U17 Data Latency : 24.5ns
> U30-U19 Data Latency : 25.0ns
> U30-U21 Data Latency : 26.2ns
> U30-U23 Data Latency : 27.0ns
> U30-U25 Data Latency : 27.6ns
> U30-U27 Data Latency : 27.8ns
> U30-U29 Data Latency : 28.7ns
> U30-U31 Data Latency : 12.7ns
> U1-U3 Data Latency : 25.1ns
> U1-U5 Data Latency : 26.5ns
> U1-U7 Data Latency : 25.7ns
> U1-U9 Data Latency : 24.5ns
> U1-U11 Data Latency : 26.2ns
> U1-U13 Data Latency : 27.6ns
> U1-U15 Data Latency : 26.1ns
> U1-U17 Data Latency : 65.9ns
> U1-U19 Data Latency : 69.5ns
> U1-U21 Data Latency : 69.1ns
> U1-U23 Data Latency : 67.9ns
> U1-U25 Data Latency : 66.8ns
> U1-U27 Data Latency : 65.6ns
> U1-U29 Data Latency : 67.0ns
> U1-U31 Data Latency : 66.6ns
> U3-U5 Data Latency : 24.3ns
> U3-U7 Data Latency : 26.7ns
> U3-U9 Data Latency : 24.9ns
> U3-U11 Data Latency : 25.9ns
> U3-U13 Data Latency : 24.6ns
> U3-U15 Data Latency : 24.3ns
> U3-U17 Data Latency : 59.5ns
> U3-U19 Data Latency : 58.5ns
> U3-U21 Data Latency : 60.9ns
> U3-U23 Data Latency : 59.1ns
> U3-U25 Data Latency : 61.0ns
> U3-U27 Data Latency : 62.4ns
> U3-U29 Data Latency : 61.3ns
> U3-U31 Data Latency : 61.5ns
> U5-U7 Data Latency : 23.1ns
> U5-U9 Data Latency : 26.6ns
> U5-U11 Data Latency : 25.3ns
> U5-U13 Data Latency : 26.6ns
> U5-U15 Data Latency : 24.4ns
> U5-U17 Data Latency : 64.0ns
> U5-U19 Data Latency : 59.2ns
> U5-U21 Data Latency : 62.4ns
> U5-U23 Data Latency : 60.7ns
> U5-U25 Data Latency : 62.3ns
> U5-U27 Data Latency : 60.4ns
> U5-U29 Data Latency : 61.6ns
> U5-U31 Data Latency : 62.2ns
> U7-U9 Data Latency : 25.2ns
> U7-U11 Data Latency : 27.2ns
> U7-U13 Data Latency : 25.0ns
> U7-U15 Data Latency : 26.3ns
> U7-U17 Data Latency : 61.4ns
> U7-U19 Data Latency : 60.6ns
> U7-U21 Data Latency : 60.6ns
> U7-U23 Data Latency : 61.6ns
> U7-U25 Data Latency : 62.7ns
> U7-U27 Data Latency : 61.3ns
> U7-U29 Data Latency : 62.5ns
> U7-U31 Data Latency : 62.3ns
> U9-U11 Data Latency : 27.0ns
> U9-U13 Data Latency : 29.3ns
> U9-U15 Data Latency : 28.7ns
> U9-U17 Data Latency : 65.0ns
> U9-U19 Data Latency : 65.2ns
> U9-U21 Data Latency : 67.7ns
> U9-U23 Data Latency : 66.4ns
> U9-U25 Data Latency : 69.2ns
> U9-U27 Data Latency : 65.8ns
> U9-U29 Data Latency : 67.6ns
> U9-U31 Data Latency : 67.2ns
> U11-U13 Data Latency : 26.5ns
> U11-U15 Data Latency : 27.6ns
> U11-U17 Data Latency : 62.2ns
> U11-U19 Data Latency : 60.1ns
> U11-U21 Data Latency : 61.7ns
> U11-U23 Data Latency : 60.7ns
> U11-U25 Data Latency : 61.8ns
> U11-U27 Data Latency : 62.9ns
> U11-U29 Data Latency : 62.4ns
> U11-U31 Data Latency : 62.6ns
> U13-U15 Data Latency : 27.9ns
> U13-U17 Data Latency : 63.7ns
> U13-U19 Data Latency : 62.1ns
> U13-U21 Data Latency : 62.2ns
> U13-U23 Data Latency : 61.5ns
> U13-U25 Data Latency : 62.5ns
> U13-U27 Data Latency : 63.2ns
> U13-U29 Data Latency : 63.2ns
> U13-U31 Data Latency : 63.1ns
> U15-U17 Data Latency : 61.0ns
> U15-U19 Data Latency : 62.2ns
> U15-U21 Data Latency : 63.2ns
> U15-U23 Data Latency : 63.1ns
> U15-U25 Data Latency : 62.5ns
> U15-U27 Data Latency : 62.6ns
> U15-U29 Data Latency : 62.6ns
> U15-U31 Data Latency : 62.4ns
> U17-U19 Data Latency : 22.8ns
> U17-U21 Data Latency : 23.5ns
> U17-U23 Data Latency : 23.1ns
> U17-U25 Data Latency : 24.4ns
> U17-U27 Data Latency : 24.0ns
> U17-U29 Data Latency : 25.6ns
> U17-U31 Data Latency : 24.7ns
> U19-U21 Data Latency : 24.6ns
> U19-U23 Data Latency : 23.5ns
> U19-U25 Data Latency : 23.8ns
> U19-U27 Data Latency : 24.1ns
> U19-U29 Data Latency : 24.4ns
> U19-U31 Data Latency : 25.1ns
> U21-U23 Data Latency : 23.9ns
> U21-U25 Data Latency : 26.2ns
> U21-U27 Data Latency : 24.4ns
> U21-U29 Data Latency : 25.9ns
> U21-U31 Data Latency : 25.9ns
> U23-U25 Data Latency : 24.2ns
> U23-U27 Data Latency : 27.0ns
> U23-U29 Data Latency : 25.5ns
> U23-U31 Data Latency : 24.8ns
> U25-U27 Data Latency : 25.0ns
> U25-U29 Data Latency : 26.6ns
> U25-U31 Data Latency : 25.4ns
> U27-U29 Data Latency : 25.4ns
> U27-U31 Data Latency : 28.0ns
> U29-U31 Data Latency : 27.4ns
> 1x 64bytes Blocks Bandwidth : 18.56GB/s
> 4x 64bytes Blocks Bandwidth : 29.2GB/s
> 4x 256bytes Blocks Bandwidth : 110.8GB/s
> 4x 1kB Blocks Bandwidth : 339.8GB/s
> 4x 4kB Blocks Bandwidth : 474.1GB/s
> 16x 4kB Blocks Bandwidth : 648GB/s
> 4x 64kB Blocks Bandwidth : 903.6GB/s
> 16x 64kB Blocks Bandwidth : 539GB/s
> 8x 256kB Blocks Bandwidth : 354GB/s
> 4x 1MB Blocks Bandwidth : 346.46GB/s
> 8x 1MB Blocks Bandwidth : 35.17GB/s
> 8x 4MB Blocks Bandwidth : 18.23GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 3.4GHz/5.08GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : MUAF210009
> Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
> Platform Compliance : x64
> Buffer Memory Accesses : No
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> URL : https://www.amd.com
> Speed : 3.4GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5.08GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 8 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : MUAF210009
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Tip 223 : CPU speed, under load, lower than rated speed. Check power management settings.
> Notice 241 : Dynamic OverClocking/Turbo enabled. Performance may vary when engaged.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


Next we have dram calc easy + normal bench together with cinebench r23









And lastly we have SotTR @ 1080p lowest as a gamebench running on my new 24/7 settings =288 CPU average fps









Very happy with these results and my new 24/7 settings 
Maybe i will try to push for higher fclk now 😎

Feel free to leave any comments or questions


----------



## ManniX-ITA

lmfodor said:


> Hi PJVol, There is no need for so much sarcasm. Why are people so defensive?


Don't worry, more or less everyone appreciate the spreadsheet for one reason or another 
There's an endless discussion about it that sometimes ends up in argumentation and dissertation.
It's not bad to chill out with some sarcasm every now and then.

BTW my 4133 MHz result was posted long before the WHEA rule was introduced, like many others.
I think that they all have a value, especially since we still hope AMD can keep the promise and fix it.
WHEA is not dependent on the memory or its settings, it's a pure platform issue.
I don't really mind, guess should be the spreadsheet maintainer to have the last word in these silly questions


----------



## ManniX-ITA

The G.Skill Ripjaws 3600C14 kit attempt failed as well...
Different PCB, minus the LEDs, but they behave exactly the same as the 4000C16 kit.

Well, since I had to return them why not torturing a bit?

Let me present you the first, only, genuine, certified, true 1T profile for memory that needs setup timings to run at 1T (but without setup timings).
This beast is highly un-optimized (no wonders) and marvelously inefficient.
Of course can pass, whoop whoop, a full complete single cycle of TM5 1usmus.

















Et voila, the latency is more or less the same as with setup timings and behave erratically in the same manner; from 54.5ns to 54.7ns with sporadic 54.9ns.

So the bad latency with these kits it's not due to the setup timings but cause they just can't run at 1T properly.

@Veii
I'm thinking about the last PDF you kindly shared about memory latency.
When it's talking about the gap in progress between bandwidth and latency.
And he said that the manufacturers keeps improving bandwidth instead not because it's impossible but cause it's a matter of costs.
Low latency memory is very expensive.

I have the feeling that Samsung is improving the profit and reducing the costs of B-die ICs.
Which should have been End of Life since years but they keep being very remunerative...
I bet the current production has been "nerfed" and only a few kits using old stocks can do properly 1T and low tRCDRD.


----------



## lmfodor

ManniX-ITA said:


> The G.Skill Ripjaws 3600C14 kit attempt failed as well...
> Different PCB, minus the LEDs, but they behave exactly the same as the 4000C16 kit.
> 
> Well, since I had to return them why not torturing a bit?
> 
> Let me present you the first, only, genuine, certified, true 1T profile for memory that needs setup timings to run at 1T (but without setup timings).
> This beast is highly un-optimized (no wonders) and marvelously inefficient.
> Of course can pass, whoop whoop, a full complete single cycle of TM5 1usmus.
> 
> View attachment 2490213
> View attachment 2490214
> 
> 
> Et voila, the latency is more or less the same as with setup timings and behave erratically in the same manner; from 54.5ns to 54.7ns with sporadic 54.9ns.
> 
> So the bad latency with these kits it's not due to the setup timings but cause they just can't run at 1T properly.
> 
> @Veii
> I'm thinking about the last PDF you kindly shared about memory latency.
> When it's talking about the gap in progress between bandwidth and latency.
> And he said that the manufacturers keeps improving bandwidth instead not because it's impossible but cause it's a matter of costs.
> Low latency memory is very expensive.
> 
> I have the feeling that Samsung is improving the profit and reducing the costs of B-die ICs.
> Which should have been End of Life since years but they keep being very remunerative...
> I bet the current production has been "nerfed" and only a few kits using old stocks can do properly 1T and low tRCDRD.


Hi @ ManniX-ITA, I had high expectations for this RipJaws! The results are not bad at all, why do you say that 1T does not work well? Do you measure it in terms of latency and bandwidth or are you comparing it to 2T? What did you expect to improve compared to the ones you had? From what I saw, in a post above, the 3600-CL16 8GTZN 4x8SR gets better bandwith than us, 14 Flat, 1T enabled, right?

PS: another questions, why are you running 1.56V with RTT 1? Just to torture them  and why so strong ClkDvrStr with a High Voltage and even a very hight ProcODT. Wouldn't they work better with 1.5V, ProctODT 36 or 40, a ClkDvrStr of 40? I mean, your setup doesn't have such tight timing with loose tRRD and tWRD, high SCLs, right?


----------



## lmfodor

domdtxdissar said:


> The deed is done, have gotten this fully stable
> 
> BIOS 3501 with AGESA V2 PI 1.2.0.2
> dual CCD 5950x
> 4x8GB gskill 3600 CL16
> 1900:3800 @ flat CL14 + T1 GDM-OFF
> Screenshot of TM 1umus 25 cycle + Memtest 20000% stable (do notice this is my old bloaty windows install with lots of stuff running in background)
> View attachment 2490191
> 
> 
> 
> Newest OCCT 8.1.3 1 hour large dataset extreme + 4 iteration in y-cruncher with all tests (same boot as above)
> View attachment 2490192
> 
> 
> Some performance number:
> The SiSoftSandra v2021.31.12 (from Mar 5th, 2021). Not sure this is a good match with CTR..
> Intel latency checker
> View attachment 2490194
> 
> 
> 
> Next we have dram calc easy + normal bench together with cinebench r23
> View attachment 2490195
> 
> 
> And lastly we have SotTR @ 1080p lowest as a gamebench running on my new 24/7 settings =288 CPU average fps
> View attachment 2490196
> 
> 
> Very happy with these results and my new 24/7 settings
> Maybe i will try to push for higher fclk now 😎
> 
> Feel free to leave any comments or questions


Really excellent results, congratulations!  What voltage are you using (VDIMM?)


----------



## DeletedMember558271

Not sure why some people are having worse or same results on 1T, my latency went from 53.5ns to 52.8ns and my read speed went up like 1000MB/s at its peak, but read always goes down a bit as I run AIDA back to back to back, always seems to be the first few runs that are best for read, but not necessarily latency. My write is up at least 400MB/s as well.
These results were on 56-56-56 but I'm testing 52-0-0 right now (10 minutes), 50-0-0 gave an error within a minute.

Things suggested like 27-27-27 or 28-28-28 don't even boot, even though 0-0-0 does but with lots of fast TM5 errors so.

Never thought I'd be sub-53ns with 1.450v 4x8GB 1867/3733


----------



## ManniX-ITA

lmfodor said:


> Hi @ ManniX-ITA, I had high expectations for this RipJaws! The results are not bad at all, why do you say that 1T does not work well? Do you measure it in terms of latency and bandwidth or are you comparing it to 2T? What did you expect to improve compared to the ones you had? From what I saw, in a post above, the 3600-CL16 8GTZN 4x8SR gets better bandwith than us, 14 Flat, 1T enabled, right?
> 
> PS: another questions, why are you running 1.56V with RTT 1? Just to torture them  and why so strong ClkDvrStr with a High Voltage and even a very hight ProcODT. Wouldn't they work better with 1.5V, ProctODT 36 or 40, a ClkDvrStr of 40? I mean, your setup doesn't have such tight timing with loose tRRD and tWRD, high SCLs, right?


1T should work with lower voltage and not crazy ProcODT/ClkDrvStr, that's the problem 
Otherwise works with the setup timings.

Yes the profile from dom is better and I guess it's cause he can do flat 14 which we can't...


----------



## ManniX-ITA

Veii said:


> And i wonder if such high value prohibts RTT_WR from working completely
> ~ somebody can test if RTT_WR disabled would destabilize it then


I will check about RTT_WR, tried all possible combinations below 31 without success.
Above 6 it doesn't POST or gets really unstable.



Veii said:


> Although really look into CKE and RTT_WR with it. Syncing all 3 did not work yet for me
> Either CKE+SETUP or RTT_WR+CKE
> Alone usage of RTT_WR didn't really need CKE, but i like the powerdown feature with it
> Setting it will ignore PDM flag in the bios, it bypasses it
> CKE-1 is constantly on
> CKE 9-16 is constantly on till its not needed anymore
> tCKE 17-32 is sleeping with wake up spikes
> 
> Soo maaybe 25 could work out for 3800MT/s , if you see stability with SETUP timings
> Or 26 for 3734MT/s . likely also
> The only thing i'm not entirely sure is the range after CKE 16
> Is it again 36 - something for freq
> Or is it 17+ something for freq 🤔
> It would make sense to be reversed, like SETUP timings are


I'm lost


----------



## lmfodor

ManniX-ITA said:


> 1T should work with lower voltage and not crazy ProcODT/ClkDrvStr, that's the problem
> Otherwise works with the setup timings.
> 
> Yes the profile from dom is better and I guess it's cause he can do flat 14 which we can't...


For me, the Dom´s memory seems to be the best. In order to get a good write speed it should be 4 DIMMs right? with only 2 sticks the Write speed will be reduce to 3xMB/s right? Unfortunately I can't sell mine in my country, with taxes above I don't think anyone will buy them. I loved Dom's results. This new sales pitch from Gskill with the low latency, pure marketing, just more voltage and a lot of margin.


----------



## DeletedMember558271

So 1hr stable now 52-0-0 when 50-0-0 failed in less than a minute, maybe 51-0-0 is stable too, doubt it matters that much. Don't know if I'll be getting any of these stable or even bootable with like 26's, 27's, or 28's, maybe if I see others do and it's possible somehow. Again 0-0-0 boots even though 28-28-28 doesn't, but lots of errors
















If there was an improvement from 56-56-56 to 52-0-0, it's pretty unnoticeable at least in AIDA.


----------



## domdtxdissar

lmfodor said:


> For me, the Dom´s memory seems to be the best. In order to get a good write speed it should be 4 DIMMs right? with only 2 sticks the Write speed will be reduce to 3xMB/s right?


I'm not sure i understand you, but i have high writespeed because i have a dual CCD cpu, if i had a 5600x or 5800x the memory write bandwidth would be almost half.. (with around ~30k MB/sec)
Like this:


http://imgur.com/a/PNZBEGD

(asus bios 3003 with agesa 1.1.8.0 have ~ 0.8 ns lower latency in aida than asus bios 3501 with 1.2.0.2 )

*You should have same performance with 4x8GB or 2x16GB if everything else stay the same*

A big reason for my higher numbers is also because i also run at a much higher clockspeeds than you guys, look at l3 latency in aida for example, or the ST score in Cinebench23/CPU-Z. Its only jomama22 that ether comes close or beat me in cpu performance with hes setup.. dont think anyone else comes close.



> Threadscaling in Cinebench r20
> 
> CTR 2.1 RC5 v18.
> Latest bios 3501 for these runs, which i did all back-to-back (could gain a few points with restarts between runs)
> 
> 1 thread = 662 points
> 2 threads = 1309 points
> 4 threads = 2544 points
> 6 threads = 3796 points
> 8 threads = 4991 points
> 10 threads = 6083 points
> 12 threads = 7212 points
> 14 threads = 8139 points
> 16 threads = 8708 points
> 20 threads = 9400 points
> 24 threads = 10183 points
> 28 threads = 11123 points
> 32 threads = 12158 points
> LLC4 = upto 2% vdroop
> 
> PX high = from 1 to 2 threads @ 5025mhz
> PX mid = from 3 to 4 threads @ 4900mhz
> PX low = from 5 to 9 threads @ 4825mhz
> P2 = from 10 to 24 threads @ 4800/4675mhz
> P1 = from 25 to 32 threads @ 4750/4625mhz
> 
> PBO CO benchmode: (ambient ~ 20 degrees)
> Bios 3003, which have the best PBO CO boosting behavior of all asus bioses
> 
> 1 thread = 662 points
> 2 threads = 1303 points
> 4 threads = 2444 points
> 6 threads = 3706 points
> 8 threads = 4887 points
> 10 threads = 5974 points
> 12 threads = 7022 points
> 14 threads = 7906 points
> 16 threads = 8645 points
> 20 threads = 9583 points
> ...seems like i didn't save 24 thread screenshot, but 105xx score
> 32 threads = 12238 points
> CTR 2.04 hotfix: (ambient ~ 24 degrees)
> Bios 3003, but dont matter since using CTR
> 
> 1 thread = 652 points
> 2 threads = 1295 points
> 4 threads = 2525 points
> 6 threads = 3752 points
> 8 threads = 4979 points
> 10 threads = 6016 points
> 12 threads = 7171 points
> 14 threads = 8287 points
> 16 threads = 8831 points
> 20 threads = 9539 points
> 24 threads = 10217 points
> 28 threads = 11117 points
> 32 threads = 12032 points
> Results from CTR 2.1 RC5
> Latest bios 3501 for these runs, which i did all back-to-back (could gain a few points with restarts between runs)
> 
> 1 thread = 668 points
> 2 threads = 1302 points
> 4 threads = 2528 points
> 6 threads = 3800 points
> 8 threads = 4999 points
> 10 threads = 6081 points
> 12 threads = 7187 points
> 14 threads = 8185 points
> 16 threads = 8963 points
> 20 threads = 9540 points
> 24 threads = 10031 points
> 28 threads = 11044 points
> 32 threads = 12064 points
> 
> Screenshots @
> 
> 
> http://imgur.com/a/rIDGapf


Quote above taken from here: ASUS ROG X570 Crosshair VIII Overclocking &amp...

Also, have highlighted the vdimm voltage in hwinfo, in the first screenshot. (1.65v in bios)

Lastly, with the newest 1.2.0.2 agesa alot of the settings changed for me..
Before the lowest i could boot was with procODT 37 (but had coldboot problems), now i can boot all the way down to 30, but 34 is the most stable for me.
Before i was using RTT 6-3-3, now these settings wont boot/work anymore.. Its like veii said, it seems they have changed the RTT resistance (doubled it?) in the latest agesa, that's why I'm running 7-3-1 atm


----------



## craxton

lmfodor said:


> run frequencies above 2000Mhz with FCLK 1: 1 and not have WHEAs?


PSSSSTTTT...turn off whea logger, and wham...NOMORE whea errors lol...
kidding, ive read ALOT on other forums where people have simply returned their chips
and got a replacement and that fixed their errors ENTIRLY to the extent that 

well, it supposedly narrowed down to chips simply being defective from the start...


----------



## craxton

domdtxdissar said:


> if i had a 5600x or 5800x the bandwidth would be half


not quite true, i mean? (edit)<im speaking on memory alone, not L3/2/1 cache speeds>) (4x8) BUT here is also my 2x8 (same kit just two less dimms)









i do believe i wasnt 100% stable here, as i recall i ended up with 1.40Vdimm and better copy speeds...

this is just ALL both shots, PBO btw the top being with CO/PBO bottom just PBO with -mv offset to cpu core
voltage.


----------



## craxton

Dreamic said:


> Ok uh maybe I actually barely have to do anything to go from 2T to 1T


is this 2xDR or 4XSR?????????

if either really gonna give this a shot and see what
i can confirm for myself on my 5600x..


----------



## jomama22

craxton said:


> not quite true, i mean? (edit)<im speaking on memory alone, not L3/2/1 cache speeds>) (4x8) BUT here is also my 2x8 (same kit just two less dimms)
> 
> View attachment 2490237
> 
> i do believe i wasnt 100% stable here, as i recall i ended up with 1.40Vdimm and better copy speeds...
> 
> this is just ALL both shots, PBO btw the top being with CO/PBO bottom just PBO with -mv offset to cpu core
> voltage.
> 
> View attachment 2490238


Well yes, but then you are comparing 3800 vs 4000, which gives around a 2500MB boost more or less.


----------



## craxton

jomama22 said:


> comparing 3800 vs 4000, which gives around a 2500MB boost


None the less tho, wouldnt a 5600x perform way less?


----------



## Flash1228

Tried 1T 56-56-56 and I see no real difference between that and 2T.


----------



## DeletedMember558271

craxton said:


> is this 2xDR or 4XSR?????????
> 
> if either really gonna give this a shot and see what
> i can confirm for myself on my 5600x..


4xSR, 4400C19 Viper Patriots.
I'm actually really glad I only have 1 CCD, and the best/biggest one you can get. Seeing people with like 1.560v but still 1.5ns more latency, I wouldn't trade. At least for gaming there's like barely any games care about more than 8 cores anyway and if they do care it's usually not too beneficial, yet.


----------



## domdtxdissar

Dreamic said:


> 4xSR, 4400C19 Viper Patriots.
> I'm actually really glad I only have 1 CCD, and the best/biggest one you can get. Seeing people with like 1.560v but still 1.5ns more latency, I wouldn't trade. At least for gaming there's like barely any games care about more than 8 cores anyway and if they do care it's usually not too beneficial, yet.


lol
Try a bench in SotTB with those 8 cores / 16 threads 
If you have a dual CCD cpu, you can simply disable one if you wish for a 5600x or 5800x with *much better binning *which can clock higher and/or use less voltage at same speed, if so desired 

Typical 5800x cores: (1 average CCD)









vs 5950x cores (1 good and 1 average CCD)


----------



## craxton

Dreamic said:


> Seeing people with like 1.560v but still 1.5ns more latency, I wouldn't trade


agree with you 100% there, i just tried the 56-56-56 (while changing to x20-20-20 
from 20-24-24 i think or what ever the pic showed before.

but my aida score went up, latency in safe mode stayed the same (without disabling services) 
as i would usually do

here it is,


----------



## DeletedMember558271

Flash1228 said:


> Tried 1T 56-56-56 and I see no real difference between that and 2T.
> 
> View attachment 2490245


I don't understand because I get massive improvements to read, copy, and latency, all I really look at. Maybe some sticks just hating 1T or not fully optimized/stable for 1T? Doesn't make sense.
Like +800MB/s~ to read, +500MB/s~ to copy, and 0.7ns less latency for me.


domdtxdissar said:


> lol
> Try a bench in SotTB with those 8 cores / 16 threads
> If you have a dual CCD cpu, you can simply disable one if you wish for a 5600x or 5800x with *much better binning *which can clock higher with faster clocks and/or use less voltage at same speed, if so desired
> 
> Typical 5800x cores: (1 average CCD)
> View attachment 2490246
> 
> 
> vs 5950x cores (1 good and 1 average CCD)
> View attachment 2490247


Ok but what kinda madman buys a 5950x to turn it into a binned 5800x? And here's the benchmarks I found, you still have realize this one of the few games that cares about more than 8 cores, though I know that's becoming popular lately obviously, that's how things progress. But typically since most games are also on consoles, that's what they design the engine to run around and function on, so I don't expect to be seeing significant improvements from having more than 8 cores until the PS6 and Xbox X 2 or whatever come out, with exception being developers that decide to go above and beyond on their PC port or PC exclusives like Star Citizen. Most devs are just going to optimize for PS5's 8 cores and throw it onto PC instead of reworking everything to perfectly take advantage of more cores and scale well. They've always been lazy like that.

















So if you buy a 3090, or 3080 (that's like 5% worse basically), and only play at 1080p you will see a difference? And this is a 2018 game, future games are only going to be more GPU limited and demanding, so maybe you won't be able to see this difference at just 1080p in some of them. If we're already having to drop to 1080p with a 3090 in a 2018 game to see a CPU difference

I'm not convinced
Also its 4.7% difference, at 1080p with a 3090 in a 2018 game that's not going to be nearly as GPU limiting and demanding as future games will be at 1080p on a 3090, 166 to 174, will only shrink or completely disappear like at 1440p


----------



## lmfodor

Veii said:


> 56/56/56 is really interesting
> It should not be pure 2T as thats 61/61/61 or i think it was 63/63/63
> The korean bbs sheet shows the cutting times
> 
> The Problem i have with this, is that tCKE should not be different
> And i wonder if such high value prohibts RTT_WR from working completely
> ~ somebody can test if RTT_WR disabled would destabilize it then
> Seeing that any old SETUP Timings can not work anymore with RTT_WR
> It makes me really wonder if this is skipped
> 
> You should probably also run X-20-20-20 when you fully rely on SETUP timings
> Bad 3rd value ahould show well with memory training issues and cold boot issues
> Honestly don't think you need it that high
> Somebody could also try if 27/27/56 could work out, or a pure 27/27/27
> Just seeing dynamicODT causes issues with it, you probably wont have a good time with it enabled
> 
> Test it
> Or if 26/26/26 or 27/27/27 works, it wont have the 2T penalty and actually behave similar to lower than 16 tCKE
> 56/56/56 sounds to me reversed, hard to explain
> Anyways X-20-20-20 it is, if you're going to use SETUP Timings
> Although really look into CKE and RTT_WR with it. Syncing all 3 did not work yet for me
> Either CKE+SETUP or RTT_WR+CKE
> Alone usage of RTT_WR didn't really need CKE, but i like the powerdown feature with it
> Setting it will ignore PDM flag in the bios, it bypasses it
> CKE-1 is constantly on
> CKE 9-16 is constantly on till its not needed anymore
> tCKE 17-32 is sleeping with wake up spikes
> 
> Soo maaybe 25 could work out for 3800MT/s , if you see stability with SETUP timings
> Or 26 for 3734MT/s . likely also
> The only thing i'm not entirely sure is the range after CKE 16
> Is it again 36 - something for freq
> Or is it 17+ something for freq 🤔
> It would make sense to be reversed, like SETUP timings are
> 
> Should be enough options to test out
> Probably the key thing is, what of the 3 values is needed to be delayed and cut after specific uptime value
> And at which range RTT_WR does influence it
> Something honestly i have to test too (as my setup times are broken too) but SMU 56.50 has far bigger problems like a completely different behaving IMC FW. Getting this finally stable with less cpu voltages , has priority


Hi Veii, I will try RTT 0-0-5 to see if it works... or 7-0-1 for 1.5V
What I don´t know is the x-20-20-20 is necessary to activate setup times because I see it a lot of us running x-20-24-24 or other combination with the setup times 3-3-15 or 4-4-18.
The other test would be keeping for instance RTTWR to 3 and setup times 27-27-27 to see if it works right?

Regarding CKE + Setup, do you mean to enable tCKE from low to high and try? I mean, tCKE shouldn´t be in 1 to work with Setup or should it work? Acctually I´m running tCKE 1, CadBus 40-20-24-24 and Setup 56-56-56, so CKE or tCKE 1 is constantly on until 9, so what would be the relation with the Setup for instance 27-27-27 and RTT-WR in 3? 
I´m trying to follow you



Spoiler: CKE Definition



I like this CKE definition that I found in one forum:
CKE (clock enable) is a signal/line going from the memory controller to the memory. It's a way to tell the memory to enable internal clock signals, input buffers and output drivers (to work like a memory). Or to disable those things and enter idle mode (low power/self-refresh). CKE goes from LOW to HIGH when the memory controller needs to access the memory, telling the memory to exit power down mode. TCKE is the time interval the memory controller is waiting between enabling some reference voltages and then raising CKE to high. TCKE too short may cause data corruption due to those voltages not being at the right potential yet. TCKE too long hurts memory response after it's been sleeping.
Power down mode is a power saving feature of DDR4 memory, designed mainly for battery-operated devices. If you're overclocking then you most probably don't need it so just disable it. When you disable it, tCKE becomes irrelevant because during normal operation CKE doesn't change states and remains high.


----------



## domdtxdissar

What games you wanna bench with that 1 CCD 1.5ns supremacy then ? 
I see you have linked SoTB 1080p and 1440p highest above, it happens i have already benched exactly that 













I will throw in a 1080p lowest for good measure








Maybe some F1 2020 1080p and 1440p ?














Horizen zero down ?






(100%res scale)






(50% res scale)


FarCry 5 ?








Let me know if you get close to any of these with your eco setup  (these are all games with cpu benchmarks where you can use those 1.5ns)
Yesterday you wanted to fight with jomama22 because your ego got hurt and today me ? If you have problems with your memory overheating and cant run above 3733 its not our fault.

Stop trying to talk others down, or atleast step-up when you get called out on it.


----------



## DeletedMember558271

domdtxdissar said:


> What games you wanna bench with that 1 CCD 1.5ns supremacy then ?
> I see you have linked SoTB 1080p and 1440p highest above, it happens i have already benched exactly that
> View attachment 2490252
> View attachment 2490253
> 
> I will throw in a 1080p lowest for good measure
> View attachment 2490254
> 
> 
> Maybe some F1 2020 1080p and 1440p ?
> View attachment 2490256
> View attachment 2490257
> 
> 
> Horizen zero down ?
> View attachment 2490258
> (100%res scale)
> View attachment 2490259
> (50% res scale)
> 
> 
> FarCry 5 ?
> View attachment 2490261
> 
> 
> Let me know if you get close to any of these with your eco setup
> Yesterday you wanted to fight with jomama22 because your ego got hurt and today me ? If you have problems with your memory overheating and cant run above 3733 its not our fault. Stop trying to talk others down.


What exactly do you think it is you're proving here? That every other professional reviewer in the industry is wrong with their results? Or just Hardware Unboxed?
Nobody cares what you get with your 5950x and 3090 at different resolutions, as if this is some newfound knowledge and no other professional outlets have benchmarked the same hardware in signficanctly more games against other hardware under the same conditions, you're not even using close to the same drivers in these images.
I also don't have the game.
Stop being stupid please, thank you. I'm not going to waste my time with another idiot, who is going to ignore everything out there benching 5950x vs 5800x.
Go to LinusTechTips forums or something


----------



## jomama22

craxton said:


> None the less tho, wouldnt a 5600x perform way less?


Not sure what you mean? You're read/write bandwidth fall in line with the boost 3800 vs 4000mhz gives.


----------



## lmfodor

craxton said:


> PSSSSTTTT...turn off whea logger, and wham...NOMORE whea errors lol...
> kidding, ive read ALOT on other forums where people have simply returned their chips
> and got a replacement and that fixed their errors ENTIRLY to the extent that
> well, it supposedly narrowed down to chips simply being defective from the start...


No pls, tell me that I don´t need to change the processor. Do you mean that all of us who have WHEA errors are due to faulty processors? For me is something related to some parameter in BIOS or something not yet fixed. I hope so!


----------



## jomama22

Dreamic said:


> What exactly do you think it is you're proving here? That every other professional reviewer in the industry is wrong with their results? Or just Hardware Unboxed?
> Nobody cares what you get with your 5950x and 3090 at different resolutions, as if this is some newfound knowledge and no other professional outlets have benchmarked the same hardware in signficanctly more games against other hardware under the same conditions, you're not even using close to the same drivers in these images.
> I also don't have the game.
> Stop being stupid please, thank you. I'm not going to waste my time with another idiot, who is going to ignore everything out there benching 5950x vs 5800x.
> Go to LinusTechTips forums or something


You realize how much of a child it makes you look like calling people idiots, stupid, mocking them and just overall being rude right? Your credibility is basically 0 because of it.


----------



## TimeDrapery

Uhoh... Performance drop, initial stability test results are favorable though...


----------



## Pegasuss

The setup timings is also working for me, I don't think there is any improvement to be made now? Also, 27 setup timings does not boot on my end.


----------



## KedarWolf

Can those running 1T run Sisoft Sandra.

Can't get 1T working at all, tried a bunch of stuff you guys have.

My 2T stable at much lower voltages though with 56-56-56. 59.4 highest latency. 





















Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 175.27GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.7ns (9.5ns - 59.4ns)
Inter-Thread (same Core) Latency : 9.7ns
Inter-Core (same Module) Latency : 20.7ns
Inter-Module (same Package) Latency : 58.1ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.48GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1709.31MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.78ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 35.90MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.3ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 20.0ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.4ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.7ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.1ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 57.0ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 57.2ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.8ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 57.6ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.9ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 57.7ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.1ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.5ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 20.1ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.6ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.9ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.7ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.1ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.2ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 57.1ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 57.2ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.9ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 57.6ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.9ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 57.7ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.2ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.8ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 21.6ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 20.2ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.9ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.2ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 21.3ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 57.9ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.7ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.4ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.8ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 58.0ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 58.3ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.4ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.8ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.4ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.9ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 19.8ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 21.5ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 20.2ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 21.9ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.2ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 21.3ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 57.8ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 57.9ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 57.4ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.9ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 58.1ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 58.4ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.4ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.8ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.6ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.6ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.3ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 20.4ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 20.3ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 56.8ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 57.3ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 56.9ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.4ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 57.6ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.1ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 57.6ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.2ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 19.8ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 19.6ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.6ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.6ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.3ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 20.4ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 20.2ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 56.8ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 57.4ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 56.9ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 57.4ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 57.7ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.1ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 57.6ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.2ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.5ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 22.8ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.2ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 22.4ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.1ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 58.2ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 57.9ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.2ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.5ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.8ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 58.8ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 59.0ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 20.5ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 21.7ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.8ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.8ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.6ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 22.8ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 21.2ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 22.4ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.0ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 58.2ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.8ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.3ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.5ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.8ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.8ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.9ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.6ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 21.1ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 20.7ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.1ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.2ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 57.1ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.6ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.0ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.3ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 57.7ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.2ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 19.9ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 20.1ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.6ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.3ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.6ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 21.1ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 20.7ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.1ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.2ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.0ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.6ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.0ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.2ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 57.7ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.3ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.6ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 22.5ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.5ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.4ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.1ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 58.5ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.0ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 59.0ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.4ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.9ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.8ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 22.3ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 22.8ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.8ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.7ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.6ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 22.5ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.4ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 58.4ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.2ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 58.5ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.9ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 59.1ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.4ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.9ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 20.8ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 57.9ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.3ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 57.6ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.3ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 58.3ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.1ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 58.7ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.1ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 20.4ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.3ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 20.6ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.0ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 21.2ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.4ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 20.9ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.0ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.2ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 57.6ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.4ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 58.3ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.2ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 58.7ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.1ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.4ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.4ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 57.9ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.2ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 58.8ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.9ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.2ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.2ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.1ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 21.5ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 20.8ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 22.3ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 20.8ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 22.6ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.0ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.7ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.4ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.4ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 57.9ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.3ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 58.7ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.8ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.1ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.2ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.1ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 19.7ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 20.1ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.3ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.7ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 20.0ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.2ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.1ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 57.8ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.4ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.7ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.7ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.0ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.0ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.1ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.7ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.2ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 19.7ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 20.2ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.4ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.7ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 20.0ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.2ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 19.4ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 21.1ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 20.1ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 21.7ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.0ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 21.1ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.5ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 57.9ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 57.7ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.8ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.8ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 58.0ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.4ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.1ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.2ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.6ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 19.4ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 21.1ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 20.1ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 21.7ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.0ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 21.1ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.3ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 20.5ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.0ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 20.1ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.0ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 56.6ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.3ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.1ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.5ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.1ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 57.8ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 57.4ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 57.6ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 19.6ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.1ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.6ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.3ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 20.5ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.0ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 20.1ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 19.9ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.3ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 22.4ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 20.7ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.9ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.5ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.9ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.7ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 58.1ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.0ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 58.7ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.6ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.4ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 20.1ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 21.1ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.4ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.6ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.3ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 22.5ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 20.7ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 21.9ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 20.8ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 21.2ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 20.8ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.6ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.1ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 57.9ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.1ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.2ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.6ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 58.3ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 58.6ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 20.3ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 20.0ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 20.5ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.1ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.7ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 20.9ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 21.2ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 20.8ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.4ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 22.4ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.9ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.6ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.6ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.9ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.7ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 59.1ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 59.1ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 59.1ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.7ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 21.9ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 22.4ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 20.9ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.6ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.4ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 22.4ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 20.6ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 57.7ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.0ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 58.4ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.0ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.7ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 58.8ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 58.9ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 20.0ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.0ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 20.3ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.6ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 21.2ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.2ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.6ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 20.7ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.1ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.9ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.4ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.5ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.5ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.9ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.4ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.0ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.1ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 21.1ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.3ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.9ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 20.9ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.4ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 20.7ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.7ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.5ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.0ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 20.5ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 19.9ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.7ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 20.1ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.2ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 57.0ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 57.3ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 56.8ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.3ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.5ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.9ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 57.6ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.1ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.9ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 21.7ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 20.3ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 22.1ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.3ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 21.4ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 58.1ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 58.1ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.7ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 58.1ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 58.4ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.5ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.6ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 59.1ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.7ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 20.6ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.3ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 20.5ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 20.3ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 56.9ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.4ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.0ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.5ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 57.7ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.2ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 57.6ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.2ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.6ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 22.8ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.2ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 22.4ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.2ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 58.2ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.8ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 58.3ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.6ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.8ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.8ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 59.0ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.6ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 21.1ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 20.7ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.1ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.2ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 57.0ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.6ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 57.9ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.2ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 57.7ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.1ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.6ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 22.5ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 58.4ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 58.3ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 58.1ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 58.5ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 59.0ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 59.0ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 59.3ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.9ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 20.8ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 57.9ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 58.3ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 57.7ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.4ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 58.3ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.1ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 58.8ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.1ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.4ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.5ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.0ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.3ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 58.8ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.9ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.2ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.3ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.2ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 19.8ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 20.3ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.4ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.8ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 20.0ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.2ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 19.4ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 21.1ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 20.1ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 21.7ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.0ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 21.1ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.3ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 20.5ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 19.9ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 20.1ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 19.9ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.3ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 22.4ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.8ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 22.0ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 20.9ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 21.2ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 20.8ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.4ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 22.4ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 20.6ns
1x 64bytes Blocks Bandwidth : 26GB/s
4x 64bytes Blocks Bandwidth : 27.76GB/s
4x 256bytes Blocks Bandwidth : 89.25GB/s
4x 1kB Blocks Bandwidth : 316.09GB/s
4x 4kB Blocks Bandwidth : 511.67GB/s
16x 4kB Blocks Bandwidth : 709.49GB/s
4x 64kB Blocks Bandwidth : 977.57GB/s
16x 64kB Blocks Bandwidth : 595.3GB/s
8x 256kB Blocks Bandwidth : 602.35GB/s
4x 1MB Blocks Bandwidth : 590GB/s
16x 1MB Blocks Bandwidth : 26.41GB/s
8x 4MB Blocks Bandwidth : 20.86GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 5GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## craxton

Dreamic said:


> I also don't have the game.





Spoiler



You can have the game, pretty much ANY game you so
desire.... IGG-GAMES. moc (fix that last bit yourself) or you can use GITFIRL (fix that yourself too)



i may get banned for even mentioning those here, or warned...but for the sake of anyone claiming to not
have "a game" i cant stand idle by.

even tho your right and thats GPU limiting the cpu that 5600x does as good as the highest sku,
those overclocks on RAM is really one thing we dont see or hear ANY benchmark/youtuber do.

like squeezing the LAST BIT out their setups.

but here is a link showing that near NO cpu has an advantages while using SAID gpu's
again, i dont see mentions of overclocking the ever loving **** out their ram/IMC being shown either.

to which extent, i play several games, where i get better FPS with my ram tuned, and 
PBO/CO tuned right as well...running 4000mhz as i never tried anything lower since day one 
of receiving this 5600x..


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> 
> 
> 
> Spoiler
> 
> 
> 
> You can have the game, pretty much ANY game you so
> desire.... IGG-GAMES. moc (fix that last bit yourself) or you can use GITFIRL (fix that yourself too)
> 
> 
> 
> i may get banned for even mentioning those here, or warned...but for the sake of anyone claiming to not
> have "a game" i cant stand idle by.


I'M WARNING YOU

_Never_ talk about games, EVER

They require too much _voltage_, they're _inefficient_, and I *hate* _electricity_ *overall* because I can't figure out how to run high juice without losing my patience and setting my **** back to 3734 MT/s _plus_ I don't have _any_ games and it's *impossible* for me to get any even though everyone else on the games spreadsheet has games but that's because they're inefficient too

**** everybody with games but **** all electricity too


----------



## KedarWolf

Talking about fake news, my cat will meow for food when her dish is still half full.

Yes, I'm tired of all the fake mews.


----------



## KedarWolf

For those people running 56-56-56 change this part of your 1usmus_v3 .cfg to the below.

I don't get errors in the quick test at 100% but do in a prolonged test of 1000%.

It takes a bit less than an hour to run on a 5950x with 32GB of RAM, but I find it more effective finding errors than the regular settings. 



Code:


Memory Test config file v0.02
Copyrights to the program belong to me.
Serj
testmem.tz.ru
[email protected]

[Main Section]
Config Name=1000%
Config Author=1usmus_v3
Cores=0
Tests=16
Time (%)=1000
Cycles=1
Language=0
Test Sequence=6,12,2,10,5,1,4,3,0,13,9,14,7,8,1,11,15

[Global Memory Setup]
Channels=2
Interleave Type=1
Single DIMM width, bits=64
Operation Block, byts=64
Testing Window Size (Mb)=880
Lock Memory Granularity (Mb)=16
Reserved Memory for Windows (Mb)=1024
Capable=0x0
Debug Level=7


----------



## TimeDrapery

KedarWolf said:


> Spoiler
> 
> 
> 
> For those people running 56-56-56 change this part of your 1usmus_v3 .cfg to the below.
> 
> I don't get errors in the quick test at 100% but do in a prolonged test of 1000%.
> 
> It takes a bit less than an hour to run on a 5950x with 32GB of RAM, but I find it more effective finding errors than the regular settings.
> 
> 
> 
> Code:
> 
> 
> Memory Test config file v0.02
> Copyrights to the program belong to me.
> Serj
> testmem.tz.ru
> [email protected]
> 
> [Main Section]
> Config Name=1000%
> Config Author=1usmus_v3
> Cores=0
> Tests=16
> Time (%)=1000
> Cycles=1
> Language=0
> Test Sequence=6,12,2,10,5,1,4,3,0,13,9,14,7,8,1,11,15
> 
> [Global Memory Setup]
> Channels=2
> Interleave Type=1
> Single DIMM width, bits=64
> Operation Block, byts=64
> Testing Window Size (Mb)=880
> Lock Memory Granularity (Mb)=16
> Reserved Memory for Windows (Mb)=1024
> Capable=0x0
> Debug Level=7


Oooooh-la-la, I like your style... What errors are you seeing?


----------



## KedarWolf

TimeDrapery said:


> Oooooh-la-la, I like your style... What errors are you seeing?


Oh, I don't recall, a bunch of them, test 10, test 5, test 8 I think.

This just passed though. Raised VOC from 1.1375 to 1.15.

RAM voltage in BIOS is 1.52, it always reports higher.


----------



## Dar|{cyde

@ManniX-ITA Since you got 1T stable, try swap it back to 2T using the same timings, and compare scores.

I don't think you're torturing them at all. This is OCN, not Dell support forums. I'm comfortable with 1.6V if there are XMP sticks that require 1.5V. I just keep them cool, nothing to worry about.


----------



## DeletedMember558271

jomama22 said:


> We all understand that but that's not the point we are trying to make to you. This isn't a GPU comparison, it's a CPU comparison, just using gaming benchmarks to do so in this case. We're using these types of benchmarks as it provides a context as to what differences there are between a maxed out 5800x and 5950x, completely independent of the gpu.
> 
> If you notice, in Dom's benchmarks there are cpu game and rendering fps. This is completely separate from overall/gpu fps as it is the speed and rate at which the cpu can render and pass frames to the gpu. That is what the comparison is, since we are comparing CPUs.
> 
> That's it. This has literally nothing to do with anything else. No need for justification as to why you have a 5800x, why the comparison is dumb with 3090s, literally nothing to do with any of that. It is purely comparing CPUs.
> 
> It's the same way in which we sit here and compare aida latency and don't just compare game fps. You know why? Because this is the result:
> View attachment 2490278
> 
> Fractions of a fps.


Ok, but back to what I originally said, which was I'm glad I only have 1 CCD, because I get better latency than I would otherwise, and there's really not much of a difference in having dual CCD/more cores right now, unless you're putting it to use in applications other than gaming. That's all I was saying, that's all I care about. And the latency is more important right now, and there are specific games that value it and Dual Rank > Single Rank more than others, regarding that benchmark. Sort of like Resizable BAR, it varies from game to game as well, some really liking it. The latency is what kept 3000 series behind Intel in gaming, not the lack of cores, outperformed Intel in basically everything but gaming.

I don't really care about just CPU performance and was never talking about just CPU performance, I was talking about gaming performance and you can't play a *video *game with just a CPU.
I know he can run CineBench faster, I don't really care about that though.
What you're talking is not what I was ever talking about


----------



## DeletedMember558271

And even when not GPU-limited, it's not like most games care about the extra cores and scale well with them like you would hope they would, and with the consoles only having 8 cores and that being what 99% of developers will care to optimize for, I don't see that changing much anytime soon, until we have consoles with more cores, with developers building games from the ground up to make the most use of all of them.

This isn't anything new, used to be back in the day having an 6 or 8 core was kinda pointless over a 4 core, cause games and developers just didn't care to make as much use of them as they should if any, you'd look at your CPU usage on your 8 core and it would only be using like the first 4.
Dreaming if hoping for games to properly utilize all 16 cores anytime soon to come even close to being anything but a pretty rare thing


----------



## jomama22

KedarWolf said:


> Can those running 1T run Sisoft Sandra.
> 
> Can't get 1T working at all, tried a bunch of stuff you guys have.
> 
> My 2T stable at much lower voltages though with 56-56-56. 59.4 highest latency.
> 
> View attachment 2490271
> 
> 
> View attachment 2490270
> 
> 
> 
> 
> Code:
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 175.27GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Average Inter-Thread Latency : 39.7ns (9.5ns - 59.4ns)
> Inter-Thread (same Core) Latency : 9.7ns
> Inter-Core (same Module) Latency : 20.7ns
> Inter-Module (same Package) Latency : 58.1ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5.48GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1709.31MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 3.78ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 707.05kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 35.90MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 0.08ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.3ns
> U0-M0C0T0 <> U4-M0C2T0 Data Latency : 20.0ns
> U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.4ns
> U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
> U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.7ns
> U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.1ns
> U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
> U0-M0C0T0 <> U16-M1C0T0 Data Latency : 57.0ns
> U0-M0C0T0 <> U18-M1C1T0 Data Latency : 57.2ns
> U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.8ns
> U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.3ns
> U0-M0C0T0 <> U24-M1C4T0 Data Latency : 57.6ns
> U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.9ns
> U0-M0C0T0 <> U28-M1C6T0 Data Latency : 57.7ns
> U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.1ns
> U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.5ns
> U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
> U0-M0C0T0 <> U5-M0C2T1 Data Latency : 20.1ns
> U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.6ns
> U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.9ns
> U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.7ns
> U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.1ns
> U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.2ns
> U0-M0C0T0 <> U17-M1C0T1 Data Latency : 57.1ns
> U0-M0C0T0 <> U19-M1C1T1 Data Latency : 57.2ns
> U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.9ns
> U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.3ns
> U0-M0C0T0 <> U25-M1C4T1 Data Latency : 57.6ns
> U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.9ns
> U0-M0C0T0 <> U29-M1C6T1 Data Latency : 57.7ns
> U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.2ns
> U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.8ns
> U2-M0C1T0 <> U6-M0C3T0 Data Latency : 21.6ns
> U2-M0C1T0 <> U8-M0C4T0 Data Latency : 20.2ns
> U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.9ns
> U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.2ns
> U2-M0C1T0 <> U14-M0C7T0 Data Latency : 21.3ns
> U2-M0C1T0 <> U16-M1C0T0 Data Latency : 57.9ns
> U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.7ns
> U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.4ns
> U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.8ns
> U2-M0C1T0 <> U24-M1C4T0 Data Latency : 58.0ns
> U2-M0C1T0 <> U26-M1C5T0 Data Latency : 58.3ns
> U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.4ns
> U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.8ns
> U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.4ns
> U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.9ns
> U2-M0C1T0 <> U5-M0C2T1 Data Latency : 19.8ns
> U2-M0C1T0 <> U7-M0C3T1 Data Latency : 21.5ns
> U2-M0C1T0 <> U9-M0C4T1 Data Latency : 20.2ns
> U2-M0C1T0 <> U11-M0C5T1 Data Latency : 21.9ns
> U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.2ns
> U2-M0C1T0 <> U15-M0C7T1 Data Latency : 21.3ns
> U2-M0C1T0 <> U17-M1C0T1 Data Latency : 57.8ns
> U2-M0C1T0 <> U19-M1C1T1 Data Latency : 57.9ns
> U2-M0C1T0 <> U21-M1C2T1 Data Latency : 57.4ns
> U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.9ns
> U2-M0C1T0 <> U25-M1C4T1 Data Latency : 58.1ns
> U2-M0C1T0 <> U27-M1C5T1 Data Latency : 58.4ns
> U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.4ns
> U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.8ns
> U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.6ns
> U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.6ns
> U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.3ns
> U4-M0C2T0 <> U12-M0C6T0 Data Latency : 20.4ns
> U4-M0C2T0 <> U14-M0C7T0 Data Latency : 20.3ns
> U4-M0C2T0 <> U16-M1C0T0 Data Latency : 56.8ns
> U4-M0C2T0 <> U18-M1C1T0 Data Latency : 57.3ns
> U4-M0C2T0 <> U20-M1C2T0 Data Latency : 56.9ns
> U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.4ns
> U4-M0C2T0 <> U24-M1C4T0 Data Latency : 57.6ns
> U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.1ns
> U4-M0C2T0 <> U28-M1C6T0 Data Latency : 57.6ns
> U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.2ns
> U4-M0C2T0 <> U1-M0C0T1 Data Latency : 19.8ns
> U4-M0C2T0 <> U3-M0C1T1 Data Latency : 19.6ns
> U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
> U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.6ns
> U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.6ns
> U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.3ns
> U4-M0C2T0 <> U13-M0C6T1 Data Latency : 20.4ns
> U4-M0C2T0 <> U15-M0C7T1 Data Latency : 20.2ns
> U4-M0C2T0 <> U17-M1C0T1 Data Latency : 56.8ns
> U4-M0C2T0 <> U19-M1C1T1 Data Latency : 57.4ns
> U4-M0C2T0 <> U21-M1C2T1 Data Latency : 56.9ns
> U4-M0C2T0 <> U23-M1C3T1 Data Latency : 57.4ns
> U4-M0C2T0 <> U25-M1C4T1 Data Latency : 57.7ns
> U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.1ns
> U4-M0C2T0 <> U29-M1C6T1 Data Latency : 57.6ns
> U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.2ns
> U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.5ns
> U6-M0C3T0 <> U10-M0C5T0 Data Latency : 22.8ns
> U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.2ns
> U6-M0C3T0 <> U14-M0C7T0 Data Latency : 22.4ns
> U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.1ns
> U6-M0C3T0 <> U18-M1C1T0 Data Latency : 58.2ns
> U6-M0C3T0 <> U20-M1C2T0 Data Latency : 57.9ns
> U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.2ns
> U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.5ns
> U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.8ns
> U6-M0C3T0 <> U28-M1C6T0 Data Latency : 58.8ns
> U6-M0C3T0 <> U30-M1C7T0 Data Latency : 59.0ns
> U6-M0C3T0 <> U1-M0C0T1 Data Latency : 20.5ns
> U6-M0C3T0 <> U3-M0C1T1 Data Latency : 21.7ns
> U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.8ns
> U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.8ns
> U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.6ns
> U6-M0C3T0 <> U11-M0C5T1 Data Latency : 22.8ns
> U6-M0C3T0 <> U13-M0C6T1 Data Latency : 21.2ns
> U6-M0C3T0 <> U15-M0C7T1 Data Latency : 22.4ns
> U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.0ns
> U6-M0C3T0 <> U19-M1C1T1 Data Latency : 58.2ns
> U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.8ns
> U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.3ns
> U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.5ns
> U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.8ns
> U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.8ns
> U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.9ns
> U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.6ns
> U8-M0C4T0 <> U12-M0C6T0 Data Latency : 21.1ns
> U8-M0C4T0 <> U14-M0C7T0 Data Latency : 20.7ns
> U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.1ns
> U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.2ns
> U8-M0C4T0 <> U20-M1C2T0 Data Latency : 57.1ns
> U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.6ns
> U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.0ns
> U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.3ns
> U8-M0C4T0 <> U28-M1C6T0 Data Latency : 57.7ns
> U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.2ns
> U8-M0C4T0 <> U1-M0C0T1 Data Latency : 19.9ns
> U8-M0C4T0 <> U3-M0C1T1 Data Latency : 20.1ns
> U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.6ns
> U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.3ns
> U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
> U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.6ns
> U8-M0C4T0 <> U13-M0C6T1 Data Latency : 21.1ns
> U8-M0C4T0 <> U15-M0C7T1 Data Latency : 20.7ns
> U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.1ns
> U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.2ns
> U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.0ns
> U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.6ns
> U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.0ns
> U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.2ns
> U8-M0C4T0 <> U29-M1C6T1 Data Latency : 57.7ns
> U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.3ns
> U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.6ns
> U10-M0C5T0 <> U14-M0C7T0 Data Latency : 22.5ns
> U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.5ns
> U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.4ns
> U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.1ns
> U10-M0C5T0 <> U22-M1C3T0 Data Latency : 58.5ns
> U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.0ns
> U10-M0C5T0 <> U26-M1C5T0 Data Latency : 59.0ns
> U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.4ns
> U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.9ns
> U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.8ns
> U10-M0C5T0 <> U3-M0C1T1 Data Latency : 22.3ns
> U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
> U10-M0C5T0 <> U7-M0C3T1 Data Latency : 22.8ns
> U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.8ns
> U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.7ns
> U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.6ns
> U10-M0C5T0 <> U15-M0C7T1 Data Latency : 22.5ns
> U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.4ns
> U10-M0C5T0 <> U19-M1C1T1 Data Latency : 58.4ns
> U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.2ns
> U10-M0C5T0 <> U23-M1C3T1 Data Latency : 58.5ns
> U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.9ns
> U10-M0C5T0 <> U27-M1C5T1 Data Latency : 59.1ns
> U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.4ns
> U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.9ns
> U12-M0C6T0 <> U14-M0C7T0 Data Latency : 20.8ns
> U12-M0C6T0 <> U16-M1C0T0 Data Latency : 57.9ns
> U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.3ns
> U12-M0C6T0 <> U20-M1C2T0 Data Latency : 57.6ns
> U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.3ns
> U12-M0C6T0 <> U24-M1C4T0 Data Latency : 58.3ns
> U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.1ns
> U12-M0C6T0 <> U28-M1C6T0 Data Latency : 58.7ns
> U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.1ns
> U12-M0C6T0 <> U1-M0C0T1 Data Latency : 20.4ns
> U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.3ns
> U12-M0C6T0 <> U5-M0C2T1 Data Latency : 20.6ns
> U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.0ns
> U12-M0C6T0 <> U9-M0C4T1 Data Latency : 21.2ns
> U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.4ns
> U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
> U12-M0C6T0 <> U15-M0C7T1 Data Latency : 20.9ns
> U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.0ns
> U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.2ns
> U12-M0C6T0 <> U21-M1C2T1 Data Latency : 57.6ns
> U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.4ns
> U12-M0C6T0 <> U25-M1C4T1 Data Latency : 58.3ns
> U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.2ns
> U12-M0C6T0 <> U29-M1C6T1 Data Latency : 58.7ns
> U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.1ns
> U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.4ns
> U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.4ns
> U14-M0C7T0 <> U20-M1C2T0 Data Latency : 57.9ns
> U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.2ns
> U14-M0C7T0 <> U24-M1C4T0 Data Latency : 58.8ns
> U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.9ns
> U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.2ns
> U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.2ns
> U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.1ns
> U14-M0C7T0 <> U3-M0C1T1 Data Latency : 21.5ns
> U14-M0C7T0 <> U5-M0C2T1 Data Latency : 20.8ns
> U14-M0C7T0 <> U7-M0C3T1 Data Latency : 22.3ns
> U14-M0C7T0 <> U9-M0C4T1 Data Latency : 20.8ns
> U14-M0C7T0 <> U11-M0C5T1 Data Latency : 22.6ns
> U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.0ns
> U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.7ns
> U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.4ns
> U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.4ns
> U14-M0C7T0 <> U21-M1C2T1 Data Latency : 57.9ns
> U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.3ns
> U14-M0C7T0 <> U25-M1C4T1 Data Latency : 58.7ns
> U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.8ns
> U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.1ns
> U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.2ns
> U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.1ns
> U16-M1C0T0 <> U20-M1C2T0 Data Latency : 19.7ns
> U16-M1C0T0 <> U22-M1C3T0 Data Latency : 20.1ns
> U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.3ns
> U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.7ns
> U16-M1C0T0 <> U28-M1C6T0 Data Latency : 20.0ns
> U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.2ns
> U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.1ns
> U16-M1C0T0 <> U3-M0C1T1 Data Latency : 57.8ns
> U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.4ns
> U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.7ns
> U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.7ns
> U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.0ns
> U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.0ns
> U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.1ns
> U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.7ns
> U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.2ns
> U16-M1C0T0 <> U21-M1C2T1 Data Latency : 19.7ns
> U16-M1C0T0 <> U23-M1C3T1 Data Latency : 20.2ns
> U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.4ns
> U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.7ns
> U16-M1C0T0 <> U29-M1C6T1 Data Latency : 20.0ns
> U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.2ns
> U18-M1C1T0 <> U20-M1C2T0 Data Latency : 19.4ns
> U18-M1C1T0 <> U22-M1C3T0 Data Latency : 21.1ns
> U18-M1C1T0 <> U24-M1C4T0 Data Latency : 20.1ns
> U18-M1C1T0 <> U26-M1C5T0 Data Latency : 21.7ns
> U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.0ns
> U18-M1C1T0 <> U30-M1C7T0 Data Latency : 21.1ns
> U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.5ns
> U18-M1C1T0 <> U3-M0C1T1 Data Latency : 57.9ns
> U18-M1C1T0 <> U5-M0C2T1 Data Latency : 57.7ns
> U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.8ns
> U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.8ns
> U18-M1C1T0 <> U11-M0C5T1 Data Latency : 58.0ns
> U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.4ns
> U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.1ns
> U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.2ns
> U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.6ns
> U18-M1C1T0 <> U21-M1C2T1 Data Latency : 19.4ns
> U18-M1C1T0 <> U23-M1C3T1 Data Latency : 21.1ns
> U18-M1C1T0 <> U25-M1C4T1 Data Latency : 20.1ns
> U18-M1C1T0 <> U27-M1C5T1 Data Latency : 21.7ns
> U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.0ns
> U18-M1C1T0 <> U31-M1C7T1 Data Latency : 21.1ns
> U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.3ns
> U20-M1C2T0 <> U24-M1C4T0 Data Latency : 20.5ns
> U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.0ns
> U20-M1C2T0 <> U28-M1C6T0 Data Latency : 20.1ns
> U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.0ns
> U20-M1C2T0 <> U1-M0C0T1 Data Latency : 56.6ns
> U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.3ns
> U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.1ns
> U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.5ns
> U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.1ns
> U20-M1C2T0 <> U11-M0C5T1 Data Latency : 57.8ns
> U20-M1C2T0 <> U13-M0C6T1 Data Latency : 57.4ns
> U20-M1C2T0 <> U15-M0C7T1 Data Latency : 57.6ns
> U20-M1C2T0 <> U17-M1C0T1 Data Latency : 19.6ns
> U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.1ns
> U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.6ns
> U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.3ns
> U20-M1C2T0 <> U25-M1C4T1 Data Latency : 20.5ns
> U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.0ns
> U20-M1C2T0 <> U29-M1C6T1 Data Latency : 20.1ns
> U20-M1C2T0 <> U31-M1C7T1 Data Latency : 19.9ns
> U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.3ns
> U22-M1C3T0 <> U26-M1C5T0 Data Latency : 22.4ns
> U22-M1C3T0 <> U28-M1C6T0 Data Latency : 20.7ns
> U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.9ns
> U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.5ns
> U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.9ns
> U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.7ns
> U22-M1C3T0 <> U7-M0C3T1 Data Latency : 58.1ns
> U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.0ns
> U22-M1C3T0 <> U11-M0C5T1 Data Latency : 58.7ns
> U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.6ns
> U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.4ns
> U22-M1C3T0 <> U17-M1C0T1 Data Latency : 20.1ns
> U22-M1C3T0 <> U19-M1C1T1 Data Latency : 21.1ns
> U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.4ns
> U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.6ns
> U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.3ns
> U22-M1C3T0 <> U27-M1C5T1 Data Latency : 22.5ns
> U22-M1C3T0 <> U29-M1C6T1 Data Latency : 20.7ns
> U22-M1C3T0 <> U31-M1C7T1 Data Latency : 21.9ns
> U24-M1C4T0 <> U26-M1C5T0 Data Latency : 20.8ns
> U24-M1C4T0 <> U28-M1C6T0 Data Latency : 21.2ns
> U24-M1C4T0 <> U30-M1C7T0 Data Latency : 20.8ns
> U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.6ns
> U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.1ns
> U24-M1C4T0 <> U5-M0C2T1 Data Latency : 57.9ns
> U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.1ns
> U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.2ns
> U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.6ns
> U24-M1C4T0 <> U13-M0C6T1 Data Latency : 58.3ns
> U24-M1C4T0 <> U15-M0C7T1 Data Latency : 58.6ns
> U24-M1C4T0 <> U17-M1C0T1 Data Latency : 20.3ns
> U24-M1C4T0 <> U19-M1C1T1 Data Latency : 20.0ns
> U24-M1C4T0 <> U21-M1C2T1 Data Latency : 20.5ns
> U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.1ns
> U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.7ns
> U24-M1C4T0 <> U27-M1C5T1 Data Latency : 20.9ns
> U24-M1C4T0 <> U29-M1C6T1 Data Latency : 21.2ns
> U24-M1C4T0 <> U31-M1C7T1 Data Latency : 20.8ns
> U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.4ns
> U26-M1C5T0 <> U30-M1C7T0 Data Latency : 22.4ns
> U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.9ns
> U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.6ns
> U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.6ns
> U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.9ns
> U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.7ns
> U26-M1C5T0 <> U11-M0C5T1 Data Latency : 59.1ns
> U26-M1C5T0 <> U13-M0C6T1 Data Latency : 59.1ns
> U26-M1C5T0 <> U15-M0C7T1 Data Latency : 59.1ns
> U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.7ns
> U26-M1C5T0 <> U19-M1C1T1 Data Latency : 21.9ns
> U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U23-M1C3T1 Data Latency : 22.4ns
> U26-M1C5T0 <> U25-M1C4T1 Data Latency : 20.9ns
> U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.6ns
> U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.4ns
> U26-M1C5T0 <> U31-M1C7T1 Data Latency : 22.4ns
> U28-M1C6T0 <> U30-M1C7T0 Data Latency : 20.6ns
> U28-M1C6T0 <> U1-M0C0T1 Data Latency : 57.7ns
> U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.7ns
> U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.0ns
> U28-M1C6T0 <> U7-M0C3T1 Data Latency : 58.4ns
> U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.0ns
> U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.7ns
> U28-M1C6T0 <> U13-M0C6T1 Data Latency : 58.8ns
> U28-M1C6T0 <> U15-M0C7T1 Data Latency : 58.9ns
> U28-M1C6T0 <> U17-M1C0T1 Data Latency : 20.0ns
> U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.0ns
> U28-M1C6T0 <> U21-M1C2T1 Data Latency : 20.3ns
> U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.6ns
> U28-M1C6T0 <> U25-M1C4T1 Data Latency : 21.2ns
> U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.2ns
> U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.6ns
> U28-M1C6T0 <> U31-M1C7T1 Data Latency : 20.7ns
> U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.1ns
> U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.9ns
> U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.4ns
> U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.5ns
> U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.5ns
> U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.9ns
> U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.4ns
> U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.0ns
> U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.1ns
> U30-M1C7T0 <> U19-M1C1T1 Data Latency : 21.1ns
> U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.3ns
> U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.9ns
> U30-M1C7T0 <> U25-M1C4T1 Data Latency : 20.9ns
> U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.4ns
> U30-M1C7T0 <> U29-M1C6T1 Data Latency : 20.7ns
> U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.7ns
> U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.5ns
> U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.0ns
> U1-M0C0T1 <> U7-M0C3T1 Data Latency : 20.5ns
> U1-M0C0T1 <> U9-M0C4T1 Data Latency : 19.9ns
> U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.7ns
> U1-M0C0T1 <> U13-M0C6T1 Data Latency : 20.1ns
> U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.2ns
> U1-M0C0T1 <> U17-M1C0T1 Data Latency : 57.0ns
> U1-M0C0T1 <> U19-M1C1T1 Data Latency : 57.3ns
> U1-M0C0T1 <> U21-M1C2T1 Data Latency : 56.8ns
> U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.3ns
> U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.5ns
> U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.9ns
> U1-M0C0T1 <> U29-M1C6T1 Data Latency : 57.6ns
> U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.1ns
> U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.9ns
> U3-M0C1T1 <> U7-M0C3T1 Data Latency : 21.7ns
> U3-M0C1T1 <> U9-M0C4T1 Data Latency : 20.3ns
> U3-M0C1T1 <> U11-M0C5T1 Data Latency : 22.1ns
> U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.3ns
> U3-M0C1T1 <> U15-M0C7T1 Data Latency : 21.4ns
> U3-M0C1T1 <> U17-M1C0T1 Data Latency : 58.1ns
> U3-M0C1T1 <> U19-M1C1T1 Data Latency : 58.1ns
> U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.7ns
> U3-M0C1T1 <> U23-M1C3T1 Data Latency : 58.1ns
> U3-M0C1T1 <> U25-M1C4T1 Data Latency : 58.4ns
> U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.5ns
> U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.6ns
> U3-M0C1T1 <> U31-M1C7T1 Data Latency : 59.1ns
> U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.7ns
> U5-M0C2T1 <> U9-M0C4T1 Data Latency : 20.6ns
> U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.3ns
> U5-M0C2T1 <> U13-M0C6T1 Data Latency : 20.5ns
> U5-M0C2T1 <> U15-M0C7T1 Data Latency : 20.3ns
> U5-M0C2T1 <> U17-M1C0T1 Data Latency : 56.9ns
> U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.4ns
> U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.0ns
> U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.5ns
> U5-M0C2T1 <> U25-M1C4T1 Data Latency : 57.7ns
> U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.2ns
> U5-M0C2T1 <> U29-M1C6T1 Data Latency : 57.6ns
> U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.2ns
> U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.6ns
> U7-M0C3T1 <> U11-M0C5T1 Data Latency : 22.8ns
> U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.2ns
> U7-M0C3T1 <> U15-M0C7T1 Data Latency : 22.4ns
> U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.2ns
> U7-M0C3T1 <> U19-M1C1T1 Data Latency : 58.2ns
> U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.8ns
> U7-M0C3T1 <> U23-M1C3T1 Data Latency : 58.3ns
> U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.6ns
> U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.8ns
> U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.8ns
> U7-M0C3T1 <> U31-M1C7T1 Data Latency : 59.0ns
> U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.6ns
> U9-M0C4T1 <> U13-M0C6T1 Data Latency : 21.1ns
> U9-M0C4T1 <> U15-M0C7T1 Data Latency : 20.7ns
> U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.1ns
> U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.2ns
> U9-M0C4T1 <> U21-M1C2T1 Data Latency : 57.0ns
> U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.6ns
> U9-M0C4T1 <> U25-M1C4T1 Data Latency : 57.9ns
> U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.2ns
> U9-M0C4T1 <> U29-M1C6T1 Data Latency : 57.7ns
> U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.1ns
> U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.6ns
> U11-M0C5T1 <> U15-M0C7T1 Data Latency : 22.5ns
> U11-M0C5T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U11-M0C5T1 <> U19-M1C1T1 Data Latency : 58.3ns
> U11-M0C5T1 <> U21-M1C2T1 Data Latency : 58.1ns
> U11-M0C5T1 <> U23-M1C3T1 Data Latency : 58.5ns
> U11-M0C5T1 <> U25-M1C4T1 Data Latency : 59.0ns
> U11-M0C5T1 <> U27-M1C5T1 Data Latency : 59.0ns
> U11-M0C5T1 <> U29-M1C6T1 Data Latency : 59.3ns
> U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.9ns
> U13-M0C6T1 <> U15-M0C7T1 Data Latency : 20.8ns
> U13-M0C6T1 <> U17-M1C0T1 Data Latency : 57.9ns
> U13-M0C6T1 <> U19-M1C1T1 Data Latency : 58.3ns
> U13-M0C6T1 <> U21-M1C2T1 Data Latency : 57.7ns
> U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.4ns
> U13-M0C6T1 <> U25-M1C4T1 Data Latency : 58.3ns
> U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.1ns
> U13-M0C6T1 <> U29-M1C6T1 Data Latency : 58.8ns
> U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.1ns
> U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.4ns
> U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.5ns
> U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.0ns
> U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.3ns
> U15-M0C7T1 <> U25-M1C4T1 Data Latency : 58.8ns
> U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.9ns
> U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.2ns
> U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.3ns
> U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.2ns
> U17-M1C0T1 <> U21-M1C2T1 Data Latency : 19.8ns
> U17-M1C0T1 <> U23-M1C3T1 Data Latency : 20.3ns
> U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.4ns
> U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.8ns
> U17-M1C0T1 <> U29-M1C6T1 Data Latency : 20.0ns
> U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.2ns
> U19-M1C1T1 <> U21-M1C2T1 Data Latency : 19.4ns
> U19-M1C1T1 <> U23-M1C3T1 Data Latency : 21.1ns
> U19-M1C1T1 <> U25-M1C4T1 Data Latency : 20.1ns
> U19-M1C1T1 <> U27-M1C5T1 Data Latency : 21.7ns
> U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.0ns
> U19-M1C1T1 <> U31-M1C7T1 Data Latency : 21.1ns
> U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.3ns
> U21-M1C2T1 <> U25-M1C4T1 Data Latency : 20.5ns
> U21-M1C2T1 <> U27-M1C5T1 Data Latency : 19.9ns
> U21-M1C2T1 <> U29-M1C6T1 Data Latency : 20.1ns
> U21-M1C2T1 <> U31-M1C7T1 Data Latency : 19.9ns
> U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.3ns
> U23-M1C3T1 <> U27-M1C5T1 Data Latency : 22.4ns
> U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.8ns
> U23-M1C3T1 <> U31-M1C7T1 Data Latency : 22.0ns
> U25-M1C4T1 <> U27-M1C5T1 Data Latency : 20.9ns
> U25-M1C4T1 <> U29-M1C6T1 Data Latency : 21.2ns
> U25-M1C4T1 <> U31-M1C7T1 Data Latency : 20.8ns
> U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.4ns
> U27-M1C5T1 <> U31-M1C7T1 Data Latency : 22.4ns
> U29-M1C6T1 <> U31-M1C7T1 Data Latency : 20.6ns
> 1x 64bytes Blocks Bandwidth : 26GB/s
> 4x 64bytes Blocks Bandwidth : 27.76GB/s
> 4x 256bytes Blocks Bandwidth : 89.25GB/s
> 4x 1kB Blocks Bandwidth : 316.09GB/s
> 4x 4kB Blocks Bandwidth : 511.67GB/s
> 16x 4kB Blocks Bandwidth : 709.49GB/s
> 4x 64kB Blocks Bandwidth : 977.57GB/s
> 16x 64kB Blocks Bandwidth : 595.3GB/s
> 8x 256kB Blocks Bandwidth : 602.35GB/s
> 4x 1MB Blocks Bandwidth : 590GB/s
> 16x 1MB Blocks Bandwidth : 26.41GB/s
> 8x 4MB Blocks Bandwidth : 20.86GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : A20F10-1009
> Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
> Platform Compliance : x64
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> URL : https://www.amd.com
> Speed : 5GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 8 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : A20F10-1009
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


Not 1T, actually gdm enabled 1T, but two comparisons for you:
New, slightly tightened tRFC, tRAS and tRC with some slightly weird rtt's and drivestrengths. What got me stable for the normal 20 cycle run (haven't tried your 1000%). vDIMM is 1.51v here:


















Spoiler: Results



SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 199.62GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.1ns (9.2ns - 58.8ns)
Inter-Thread (same Core) Latency : 9.5ns
Inter-Core (same Module) Latency : 20.0ns
Inter-Module (same Package) Latency : 57.5ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 6.24GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1946.76MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.72ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 40.28MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 18.5ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 18.7ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 19.3ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 18.9ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 19.8ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 19.5ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 19.4ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 55.8ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 55.6ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.4ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 56.4ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 56.6ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.0ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 57.2ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 57.0ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.2ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 18.5ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 18.6ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 19.3ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 18.9ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 19.8ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 19.5ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 19.4ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 55.8ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 55.5ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.3ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 56.4ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 56.6ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.0ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 57.3ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 57.0ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 18.6ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 19.9ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.1ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.5ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 19.7ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.1ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.0ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 55.7ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 56.5ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 56.8ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 57.2ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 57.3ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 57.5ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 57.3ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 18.5ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.5ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 18.4ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 19.9ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 19.1ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.4ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 19.7ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.1ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 56.0ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 55.7ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 56.6ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 56.9ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 57.1ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 57.1ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 57.4ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 57.3ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.3ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 19.7ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 19.8ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 20.5ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 20.1ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 56.7ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 56.3ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 56.7ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.0ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 57.3ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 57.7ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 57.9ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.2ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 18.6ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 18.5ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.5ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.3ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 19.7ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 19.8ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 20.5ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 20.1ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 56.7ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 56.6ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 56.7ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 57.3ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 57.4ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 57.9ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 57.9ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.2ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 19.8ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.2ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 20.5ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 20.8ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 56.8ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 56.5ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 56.9ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 57.3ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 57.5ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 57.6ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 57.9ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 58.0ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.3ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 19.9ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.2ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.6ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 19.8ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.3ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 20.5ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 20.8ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 56.7ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 56.6ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.0ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.4ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 57.7ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 57.6ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 57.9ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.1ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.2ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 20.9ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 20.3ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.1ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 56.3ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 56.5ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.3ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 57.3ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 57.7ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.0ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 57.9ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 19.0ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.0ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 19.5ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 19.8ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.4ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.2ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 20.9ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 20.3ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.1ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 56.3ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 56.5ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.2ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 57.4ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 57.8ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.0ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 57.9ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 20.9ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.2ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 56.9ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 56.6ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 57.3ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.4ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 57.7ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 57.9ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.6ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.0ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 19.8ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.4ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 19.7ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.3ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.3ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.5ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.0ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.2ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 56.9ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 56.8ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 57.3ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.4ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 57.7ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 57.8ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.5ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.0ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 20.9ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 57.4ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 56.9ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 57.1ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 57.7ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 57.9ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 58.6ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 58.4ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 58.7ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 19.5ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 19.6ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 20.3ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.4ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 20.9ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 20.9ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.2ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 20.9ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 57.4ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 56.9ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 57.1ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 57.6ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 57.9ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 58.6ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 58.4ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 58.6ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 57.2ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 56.8ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 57.2ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 57.5ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 57.9ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.4ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 58.6ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 58.5ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 19.4ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.1ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 19.9ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 20.9ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 20.4ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.3ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.0ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.4ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 57.3ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 56.8ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 57.3ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 57.6ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 57.9ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.4ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 58.7ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 58.5ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 18.3ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 18.8ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.0ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 19.2ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 19.9ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 20.0ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 19.4ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 55.8ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 55.9ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 56.1ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 56.9ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 56.9ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.0ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 57.7ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 57.3ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.4ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 18.4ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 18.8ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.0ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 19.2ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 21.4ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 20.1ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 19.4ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 19.8ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 20.9ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.8ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.6ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 19.7ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 19.8ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.3ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 57.3ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 57.6ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 58.0ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.2ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.6ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 57.6ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.4ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.7ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.4ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 19.7ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 20.9ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.8ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.6ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 19.7ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 19.8ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.9ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.2ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 19.8ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 20.6ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.0ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.9ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.8ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.8ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 58.4ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.7ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 57.9ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 57.9ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.4ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 20.1ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.8ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.6ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 20.0ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.2ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 19.8ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 20.7ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.0ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 19.7ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.2ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 19.9ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.5ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.3ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.4ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.3ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 58.2ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.3ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.6ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 57.8ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 57.9ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 20.1ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.9ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.9ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.5ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 19.8ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.2ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 19.9ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.4ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 19.9ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 21.2ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 20.3ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.6ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 57.8ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 57.4ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 57.8ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 57.7ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.0ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 57.6ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 58.0ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 20.5ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.9ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.2ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.2ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.5ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 19.9ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 21.2ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 20.4ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 19.8ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 20.1ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.8ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 57.4ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.4ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.1ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.1ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 57.8ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.1ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.0ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.0ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 19.8ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.2ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 19.9ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.6ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 19.8ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 20.1ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 20.0ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.1ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.4ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.1ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 58.2ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 57.7ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.3ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 58.0ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 58.7ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 20.1ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 19.8ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 20.7ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.0ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 21.2ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 19.8ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.6ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 20.1ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.3ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.1ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.2ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.2ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 57.9ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.0ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 58.4ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.4ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 19.4ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 19.8ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.0ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.4ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 20.2ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 20.1ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 20.0ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.4ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.8ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 19.8ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 20.4ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.1ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 19.8ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 19.6ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 19.4ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 57.9ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 57.1ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 58.1ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.3ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.4ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.9ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.1ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.1ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.6ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 21.2ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.5ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 19.7ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.0ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.3ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 57.5ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.0ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.6ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 58.1ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.6ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.1ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 57.8ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 20.0ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 20.8ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 19.6ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 20.3ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 19.8ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.1ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.5ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.8ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.4ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 57.6ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.1ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.2ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.6ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 19.9ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.2ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.0ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.7ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.0ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 58.1ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 58.0ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 58.8ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 57.8ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.2ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.1ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.3ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 19.8ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 20.8ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 20.0ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.8ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.3ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 57.6ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.3ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 57.4ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.2ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 57.7ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 57.8ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 19.7ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 20.0ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.5ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.6ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.9ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.8ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 57.9ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 57.8ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.5ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.1ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 19.8ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.0ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.4ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 57.9ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 57.8ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 57.6ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 58.4ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 58.0ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 58.4ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 57.8ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.4ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.3ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 57.8ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 58.1ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.3ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 58.7ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 58.5ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.6ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 20.1ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 20.1ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.5ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.0ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 20.1ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 19.4ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 19.8ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 20.9ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.8ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.6ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 19.7ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 19.8ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.9ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.2ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 19.8ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 20.7ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.0ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 19.8ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.2ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 19.9ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 20.5ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 19.9ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 21.2ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 20.3ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 19.8ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 20.3ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 20.0ns
1x 64bytes Blocks Bandwidth : 27GB/s
4x 64bytes Blocks Bandwidth : 29.16GB/s
4x 256bytes Blocks Bandwidth : 106.21GB/s
4x 1kB Blocks Bandwidth : 374GB/s
4x 4kB Blocks Bandwidth : 541.87GB/s
16x 4kB Blocks Bandwidth : 816GB/s
4x 64kB Blocks Bandwidth : 1TB/s
16x 64kB Blocks Bandwidth : 787GB/s
8x 256kB Blocks Bandwidth : 749.87GB/s
4x 1MB Blocks Bandwidth : 749.07GB/s
16x 1MB Blocks Bandwidth : 30.57GB/s
8x 4MB Blocks Bandwidth : 20.2GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5.08GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII DARK HERO)
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 5.08GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5.08GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.



Compared to my previous, vDIMM at 1.44v (excuse the paint drawling, lol, don't have a previous screenshot of zentimings):
















Results


Spoiler: Results



SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 192.83GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.5ns (9.2ns - 59.4ns)
Inter-Thread (same Core) Latency : 9.5ns
Inter-Core (same Module) Latency : 20.1ns
Inter-Module (same Package) Latency : 58.5ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 6GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1880.50MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.76ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 38.91MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.7ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 20.0ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.7ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 20.1ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 21.2ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.5ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.4ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 55.6ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 55.4ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 55.8ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 58.8ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.1ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 58.2ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.6ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.8ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.3ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 20.2ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.0ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.7ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 20.3ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 19.9ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 19.5ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 19.4ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 58.3ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 58.4ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 58.8ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 58.9ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.1ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 58.3ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.6ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.8ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 20.8ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 21.3ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.9ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.6ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 19.6ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 19.9ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 58.8ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 58.5ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 58.8ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 58.4ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 58.1ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 58.3ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.8ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.4ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 20.2ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.5ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 20.6ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 21.3ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 19.9ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.6ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 19.6ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 19.9ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 58.9ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 58.6ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.9ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 58.4ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 58.1ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 58.2ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.9ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.4ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 20.7ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 21.0ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 19.9ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 20.5ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 19.8ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 59.1ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.7ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 59.2ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 59.3ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 58.7ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 59.1ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.2ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 59.1ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 21.2ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.7ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.5ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 20.6ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 21.0ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 19.8ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 20.5ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 19.9ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 59.0ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 58.8ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 59.4ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 59.4ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 58.7ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 59.1ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.0ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 59.4ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 19.8ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 21.2ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 20.0ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 20.6ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.5ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 58.4ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 59.3ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.8ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.8ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.5ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 59.1ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 58.7ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 20.7ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 21.3ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 20.5ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.6ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 19.9ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 21.2ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 20.0ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 20.7ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.6ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 58.4ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 59.2ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.7ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.8ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.4ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 59.1ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.7ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 18.9ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 19.6ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 19.0ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.9ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.8ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.4ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.4ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 57.6ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.3ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.4ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.0ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.3ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.9ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.9ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 19.8ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.4ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 18.9ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 19.6ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 19.1ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.9ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.8ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.5ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.3ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 57.7ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.2ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.5ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 57.9ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 19.7ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 19.8ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.2ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.0ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 59.0ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 58.0ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.0ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.0ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.5ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.2ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.0ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.5ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 19.7ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 21.2ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 18.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.5ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 19.2ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 20.0ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.1ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 58.0ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 59.0ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 58.0ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 57.9ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.1ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.5ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.2ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 18.8ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.2ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.2ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.6ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.5ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 58.0ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 58.3ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 58.5ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 58.4ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 19.5ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 19.6ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 20.3ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.0ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 19.6ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 19.3ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.2ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 18.9ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.2ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.2ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.6ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.5ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 58.0ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 58.3ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 58.6ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 58.4ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.2ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.1ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.9ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.2ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 58.2ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.1ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 58.8ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 58.3ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 19.5ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 19.9ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 19.7ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 20.7ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 19.1ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 19.8ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 18.8ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.4ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.4ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.3ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.8ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.2ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 58.3ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.1ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 58.7ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 58.3ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 20.0ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 21.3ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 20.4ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.6ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.0ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 20.0ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 19.4ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 58.5ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 58.8ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 58.4ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 58.6ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.9ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.1ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.1ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.3ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.4ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 20.0ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 21.4ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 20.4ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.6ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.0ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 20.0ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 19.4ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 20.6ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 21.0ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.9ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.6ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 19.7ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 19.7ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 58.7ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 58.7ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 58.3ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 58.3ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.8ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 58.0ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.3ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.1ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 20.0ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.4ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 20.6ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 21.0ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.9ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.6ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 19.7ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 19.7ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 20.4ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.3ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 19.8ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 20.7ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.0ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 58.8ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 58.9ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 58.8ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 59.3ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 58.6ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 59.1ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.6ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.8ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 21.3ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 20.7ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.6ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 20.4ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.2ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 19.8ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 20.7ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.0ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 19.7ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.2ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 19.9ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.4ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 58.8ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 58.5ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 59.0ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 58.7ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.4ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 58.0ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.5ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.2ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 20.4ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 21.0ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 20.6ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.4ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 19.7ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.2ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 19.9ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.5ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 19.1ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 20.0ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 19.3ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.1ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.2ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.2ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.6ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 57.7ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.2ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 58.0ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 58.3ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 20.6ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 20.0ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.2ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 19.8ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.5ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 19.1ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 20.0ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 19.3ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 19.8ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 20.0ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 58.3ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.1ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.6ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 58.5ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.2ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.0ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.3ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.1ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.0ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.6ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 19.8ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.2ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 19.1ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.5ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 19.5ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 20.0ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 19.1ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.7ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.9ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.9ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.1ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.6ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.4ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 58.4ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 58.7ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 20.1ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 19.7ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 20.7ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.0ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 20.0ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 19.4ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.6ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 19.5ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.9ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.4ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.9ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.0ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.1ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 58.3ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.2ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 19.4ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 19.7ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.0ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.4ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 19.2ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 20.0ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 19.0ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.4ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 20.2ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 20.9ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 20.7ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.3ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 19.9ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 19.5ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 19.4ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 58.4ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 58.5ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 58.9ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 58.8ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 58.0ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 58.2ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.6ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.7ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.6ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 21.3ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.9ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.6ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 19.6ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 19.9ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 58.8ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 58.5ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.9ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 58.4ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 58.1ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.2ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.9ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.5ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 20.5ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 20.9ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 19.7ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 20.3ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 19.7ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.5ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.2ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 58.7ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 58.8ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.2ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.5ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.7ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 19.9ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 21.2ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.0ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.6ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.5ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 58.4ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 59.2ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 58.8ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.7ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.4ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 59.0ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.8ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 18.9ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 19.6ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 19.1ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.9ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.9ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.4ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 58.3ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 57.7ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.2ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.6ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 57.9ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 19.8ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 19.8ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 58.1ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.9ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 58.9ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 58.0ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.0ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.0ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.4ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.2ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 18.8ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.1ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 58.1ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.6ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.5ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 58.0ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 58.3ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 58.5ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 58.6ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.3ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.2ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.9ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.1ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 58.2ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.0ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 58.9ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 58.3ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 20.0ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 21.3ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 20.4ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.6ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.0ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 20.0ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 19.4ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 20.7ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 21.0ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.9ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.6ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 19.7ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 19.7ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 20.4ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.2ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 19.8ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 20.7ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.0ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 19.7ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.2ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 19.9ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 20.4ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 19.1ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 20.0ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 19.3ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 20.0ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 20.2ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 19.1ns
1x 64bytes Blocks Bandwidth : 27.3GB/s
4x 64bytes Blocks Bandwidth : 27.15GB/s
4x 256bytes Blocks Bandwidth : 109GB/s
4x 1kB Blocks Bandwidth : 348.55GB/s
4x 4kB Blocks Bandwidth : 533.68GB/s
16x 4kB Blocks Bandwidth : 728GB/s
4x 64kB Blocks Bandwidth : 1TB/s
16x 64kB Blocks Bandwidth : 787.8GB/s
8x 256kB Blocks Bandwidth : 751GB/s
4x 1MB Blocks Bandwidth : 749.12GB/s
16x 1MB Blocks Bandwidth : 24.88GB/s
8x 4MB Blocks Bandwidth : 20.66GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 5.08GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII DARK HERO)
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 5.08GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 5.08GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.



Overlay of both (Red is updated timings):


----------



## ManniX-ITA

@Veii 
RTT_WR ends up in no POST with 3 beeps and debug code "dE-aD".
Guess yes very unstable 



domdtxdissar said:


> If you have a dual CCD cpu, you can simply disable one if you wish for a 5600x or 5800x with *much better binning *which can clock higher and/or use less voltage at same speed, if so desired


Indeed better binning.
But don't take as a reference the quality tags, they are relative values and only pertinent to a single CPU.
The Dual CCDs goes higher cause there are more cores.

I did some quick test with a single CCD but I can't get down to the latency of single CCD.
Think couldn't go less than 52.4ns which is more or less 1ns above what should be achievable.
How far could you go?



Dreamic said:


> Ok but what kinda madman buys a 5950x to turn it into a binned 5800x?


You couldn't image how many 

Actually since AMD forbid board vendors to allow more than 200 MHz on PBO the 5900x/5950x got more attractive.

I'm lazy eheh can't be bothered to kill or close anything when I start playing.
Often I play with Chrome with about 400 tabs open in the background (have to close some, yes).
With ProcessLasso basically I play the game with the 1st CCD and run everything else on the 2nd.
Pretty convenient!

Games are much more likely to be and become more CPU dependent than memory latency dependent.
Actually about memory it'll become more urgent in the near future to have more size than speed or latency.



domdtxdissar said:


> Yesterday you wanted to fight with jomama22 because your ego got hurt and today me ? If you have problems with your memory overheating and cant run above 3733 its not our fault.
> 
> Stop trying to talk others down, or atleast step-up when you get called out on it.


Doesn't look to me like he was talking you down, more asking and looking for comments.
You're all on the edge, chill out 

Thanks for the benchmarks really appreciated!



lmfodor said:


> No pls, tell me that I don´t need to change the processor. Do you mean that all of us who have WHEA errors are due to faulty processors? For me is something related to some parameter in BIOS or something not yet fixed. I hope so!


Of course there's a chance.
But while some got back WHEA free CPU, many more didn't.
Especially dual CCDs...



Dreamic said:


> It is beneficial for gaming... the improved latency is the biggest improvement AMD made for fps gains from the 3000 series... it's what put them ahead of Intel finally, was pretty big news...


You are really getting too nervous 
The 10ns latency improvement from 3000s, which is part of the general better efficiency on memory, did the difference.
A 2ns difference between a single and dual CCD doesn't.
100% is much more beneficial, as you can see in GN's benchmarks, the 1% and 0.1% low fps percentile.
That's what makes more enjoyable to play games on a 5950x, more consistent frame rates.










If I was only interested in memory OC wouldn't trade as well that 1.5ns for anything else but I'm not so... 



Dar|{cyde said:


> @ManniX-ITA Since you got 1T stable, try swap it back to 2T using the same timings, and compare scores.
> 
> I don't think you're torturing them at all. This is OCN, not Dell support forums. I'm comfortable with 1.6V if there are XMP sticks that require 1.5V. I just keep them cool, nothing to worry about.


I will, fell asleep yesterday...
Was not talking about voltage or temperature but ProcODT at 70 Ohm!


----------



## DeletedMember558271

ManniX-ITA said:


> The 10ns latency improvement from 3000s, which is part of the general better efficiency on memory, did the difference.
> A 2ns difference between a single and dual CCD doesn't.
> 100% is much more beneficial, as you can see in GN's benchmarks, the 1% and 0.1% low fps percentile.
> That's what makes more enjoyable to play games on a 5950x, more consistent frame rates.
> View attachment 2490297
> 
> 
> If I was only interested in memory OC wouldn't trade as well that 1.5ns for anything else but I'm not so...


If you look at this: https://www.techspot.com/review/2197-zen-3-cpu-gpu-scaling-benchmark/
The 1% lows they had are often no worse or probably unnoticeably worse, maybe depends on personal config or got improved at some point since GN's review?
For the same game at the same 1080p/medium settings:








I'm not too hurt about it.
And I'm not saying 2ns is a world of difference either, but lower latency does help performance we can agree, and it helps more than extra cores a game isn't even going to use, depending on the game, which I'd say it's currently the exception that a game uses more than 8 cores, definitely not close to the norm yet, and probably won't be for years, at which point I'll probably just upgrade to something even better than what we all have now that has more cores when it's actually relevant for gaming.


----------



## mongoled

lmfodor said:


> No pls, tell me that I don´t need to change the processor. Do you mean that all of us who have WHEA errors are due to faulty processors? For me is something related to some parameter in BIOS or something not yet fixed. I hope so!


Unfortunately you may have to bin a number of CPUs to get one that works without WHEA at the frequencies you desire, but as had been explained some people WHEA warnings are not because of the CPU, so the reality is until you try a number of different CPUs you will not be able to tell.

Also, I do not agree with people calling CPUs that dont meet their personal evaluation of what FCLK is achievable without WHEA warnings and frequency it will post at as "faulty", they are not faulty, overclocking is not guranteed and anything above 1600 mhz is considered being run out of spec.



KedarWolf said:


> Can those running 1T run Sisoft Sandra.
> 
> Can't get 1T working at all, tried a bunch of stuff you guys have.
> 
> My 2T stable at much lower voltages though with 56-56-56. 59.4 highest latency.


I hope you are not assuming that your 2T settings can be directly transfered over to your 1T settings without any changes (im not saying they cant, just you cant just assume that!) ??

I mentioned earlier that to run the 1T settings I had to adjust tWR to 12 from 10 otherwise I was getting the odd 0, 4, 5, 10 error, once I made the change everything returned to what I expected.

Also those of you that are running "hacks" and not seeing any performance benefits from going to 1T 56-56-56, I think you peeps need to find a stable baseline with 2T without those hacks, then from that baseline switch to 1T 56-56-56 to see if you are still not getting any performance boosts.

As ive noted 2 people so far who are saying they are not seeing benefits and they are both using the low tRAS trick ....


----------



## lmfodor

Veii said:


> 56/56/56 is really interesting
> It should not be pure 2T as thats 61/61/61 or i think it was 63/63/63
> The korean bbs sheet shows the cutting times
> 
> The Problem i have with this, is that tCKE should not be different
> And i wonder if such high value prohibts RTT_WR from working completely
> ~ somebody can test if RTT_WR disabled would destabilize it then
> Seeing that any old SETUP Timings can not work anymore with RTT_WR
> It makes me really wonder if this is skipped
> 
> You should probably also run X-20-20-20 when you fully rely on SETUP timings
> Bad 3rd value ahould show well with memory training issues and cold boot issues
> Honestly don't think you need it that high
> Somebody could also try if 27/27/56 could work out, or a pure 27/27/27
> Just seeing dynamicODT causes issues with it, you probably wont have a good time with it enabled
> 
> Test it
> Or if 26/26/26 or 27/27/27 works, it wont have the 2T penalty and actually behave similar to lower than 16 tCKE
> 56/56/56 sounds to me reversed, hard to explain
> Anyways X-20-20-20 it is, if you're going to use SETUP Timings
> Although really look into CKE and RTT_WR with it. Syncing all 3 did not work yet for me
> Either CKE+SETUP or RTT_WR+CKE
> Alone usage of RTT_WR didn't really need CKE, but i like the powerdown feature with it
> Setting it will ignore PDM flag in the bios, it bypasses it
> CKE-1 is constantly on
> CKE 9-16 is constantly on till its not needed anymore
> tCKE 17-32 is sleeping with wake up spikes
> 
> Soo maaybe 25 could work out for 3800MT/s , if you see stability with SETUP timings
> Or 26 for 3734MT/s . likely also
> The only thing i'm not entirely sure is the range after CKE 16
> Is it again 36 - something for freq
> Or is it 17+ something for freq [emoji848]
> It would make sense to be reversed, like SETUP timings are
> 
> Should be enough options to test out
> Probably the key thing is, what of the 3 values is needed to be delayed and cut after specific uptime value
> And at which range RTT_WR does influence it
> Something honestly i have to test too (as my setup times are broken too) but SMU 56.50 has far bigger problems like a completely different behaving IMC FW. Getting this finally stable with less cpu voltages , has priority


Hi @Veii, I tried your suggestions about CADBUS Setup. I could disable RTTWR with 6-0-3 for 1.51VDIMM but I couldn't get post with 27-27-27. 27-27-56 nor 26-26-26 or 25-25-25. I did the math I think based in the Korean Site,

56 = 111000
5-bit value = 1 = coatse delay activation = 1 MCLK delay = molecule 1 = 1/?
You can calculate the fine delay by subtracting 32.
56 - 32 = 24
Delay = 24*1/32 = 24/32 = 3/4 MCLK, 24 Sf 24 = ?/24
That is, 56 = 1/24.
The actual delay will be = 1+3/4 = 1.75 MCLK
But according to the CAD Delay table, 56 would be the same as 25, and I guess 1.8M / T should be 58 or 26 or 27 as you suggested. So, you should try 25 .. It should work, right? I also played with tCKE 9 or 16, but couldn't get the post. 


Spoiler: CAD Delay Table














This is the final comparison between the two times. I managed to lower the tRCDRD to 15 by changing tRDWR to 8 and tWRRD to 3, but did not notice a big improvement, and I lowered the vSOC to 1.12, IOD and CCD in line with this value, and also lowered ProcODT to 36 and set a stronger ClkDvrStr at 60, with this setting I could stop errors 6 and 0 and from what I read this would give a better signal and not so much strain to the IMC, right? .. The performance difference between 1T and 2T is noticeable in bandwidth and maybe the RTTWR turned off could equal the latency with 56-56-56. I will keep trying








This is the SiSandra results for a 5900x 1T vs 2T


Spoiler: SiSandra MultiCore 1T



SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 144.77GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Aggregate Inter-Thread Latency : 43.4ns (12.4ns - 64.6ns)
Inter-Thread (same Core) Latency : 12.7ns
Inter-Core (same Module) Latency : 25.1ns
Inter-Module (same Package) Latency : 61.3ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 6GB/s
No. Threads : 24
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1411.86MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Aggregate Inter-Thread Latency : 4.13ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 686.32kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 30.10MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Aggregate Inter-Thread Latency : 0.09ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23
U0-U2 Data Latency : 22.7ns
U0-U4 Data Latency : 24.7ns
U0-U6 Data Latency : 23.2ns
U0-U8 Data Latency : 24.8ns
U0-U10 Data Latency : 24.0ns
U0-U12 Data Latency : 59.3ns
U0-U14 Data Latency : 59.1ns
U0-U16 Data Latency : 59.9ns
U0-U18 Data Latency : 60.0ns
U0-U20 Data Latency : 61.4ns
U0-U22 Data Latency : 61.3ns
U0-U1 Data Latency : 12.6ns
U0-U3 Data Latency : 22.4ns
U0-U5 Data Latency : 24.0ns
U0-U7 Data Latency : 23.1ns
U0-U9 Data Latency : 28.5ns
U0-U11 Data Latency : 24.1ns
U0-U13 Data Latency : 59.6ns
U0-U15 Data Latency : 59.4ns
U0-U17 Data Latency : 60.2ns
U0-U19 Data Latency : 59.8ns
U0-U21 Data Latency : 61.7ns
U0-U23 Data Latency : 61.2ns
U2-U4 Data Latency : 23.2ns
U2-U6 Data Latency : 25.0ns
U2-U8 Data Latency : 24.3ns
U2-U10 Data Latency : 25.5ns
U2-U12 Data Latency : 59.5ns
U2-U14 Data Latency : 59.7ns
U2-U16 Data Latency : 60.3ns
U2-U18 Data Latency : 60.3ns
U2-U20 Data Latency : 62.4ns
U2-U22 Data Latency : 61.9ns
U2-U1 Data Latency : 22.4ns
U2-U3 Data Latency : 12.6ns
U2-U5 Data Latency : 22.7ns
U2-U7 Data Latency : 25.0ns
U2-U9 Data Latency : 24.3ns
U2-U11 Data Latency : 25.5ns
U2-U13 Data Latency : 59.7ns
U2-U15 Data Latency : 59.4ns
U2-U17 Data Latency : 60.2ns
U2-U19 Data Latency : 60.4ns
U2-U21 Data Latency : 62.2ns
U2-U23 Data Latency : 61.6ns
U4-U6 Data Latency : 23.9ns
U4-U8 Data Latency : 26.6ns
U4-U10 Data Latency : 25.5ns
U4-U12 Data Latency : 60.1ns
U4-U14 Data Latency : 59.5ns
U4-U16 Data Latency : 60.6ns
U4-U18 Data Latency : 60.3ns
U4-U20 Data Latency : 62.4ns
U4-U22 Data Latency : 61.7ns
U4-U1 Data Latency : 24.1ns
U4-U3 Data Latency : 23.0ns
U4-U5 Data Latency : 12.6ns
U4-U7 Data Latency : 23.7ns
U4-U9 Data Latency : 26.6ns
U4-U11 Data Latency : 25.6ns
U4-U13 Data Latency : 59.3ns
U4-U15 Data Latency : 59.2ns
U4-U17 Data Latency : 60.7ns
U4-U19 Data Latency : 59.6ns
U4-U21 Data Latency : 62.3ns
U4-U23 Data Latency : 62.0ns
U6-U8 Data Latency : 28.8ns
U6-U10 Data Latency : 26.1ns
U6-U12 Data Latency : 60.5ns
U6-U14 Data Latency : 60.3ns
U6-U16 Data Latency : 61.4ns
U6-U18 Data Latency : 61.0ns
U6-U20 Data Latency : 62.9ns
U6-U22 Data Latency : 62.1ns
U6-U1 Data Latency : 22.8ns
U6-U3 Data Latency : 25.0ns
U6-U5 Data Latency : 23.8ns
U6-U7 Data Latency : 12.6ns
U6-U9 Data Latency : 24.8ns
U6-U11 Data Latency : 26.1ns
U6-U13 Data Latency : 60.4ns
U6-U15 Data Latency : 60.3ns
U6-U17 Data Latency : 61.2ns
U6-U19 Data Latency : 61.3ns
U6-U21 Data Latency : 62.7ns
U6-U23 Data Latency : 62.3ns
U8-U10 Data Latency : 26.5ns
U8-U12 Data Latency : 61.3ns
U8-U14 Data Latency : 61.0ns
U8-U16 Data Latency : 61.6ns
U8-U18 Data Latency : 61.5ns
U8-U20 Data Latency : 63.9ns
U8-U22 Data Latency : 63.2ns
U8-U1 Data Latency : 25.4ns
U8-U3 Data Latency : 24.4ns
U8-U5 Data Latency : 26.9ns
U8-U7 Data Latency : 24.9ns
U8-U9 Data Latency : 12.4ns
U8-U11 Data Latency : 26.4ns
U8-U13 Data Latency : 61.7ns
U8-U15 Data Latency : 61.1ns
U8-U17 Data Latency : 62.4ns
U8-U19 Data Latency : 61.7ns
U8-U21 Data Latency : 63.8ns
U8-U23 Data Latency : 64.0ns
U10-U12 Data Latency : 61.3ns
U10-U14 Data Latency : 60.9ns
U10-U16 Data Latency : 62.0ns
U10-U18 Data Latency : 61.2ns
U10-U20 Data Latency : 63.3ns
U10-U22 Data Latency : 63.3ns
U10-U1 Data Latency : 24.0ns
U10-U3 Data Latency : 25.6ns
U10-U5 Data Latency : 25.5ns
U10-U7 Data Latency : 26.0ns
U10-U9 Data Latency : 26.3ns
U10-U11 Data Latency : 12.4ns
U10-U13 Data Latency : 61.5ns
U10-U15 Data Latency : 60.9ns
U10-U17 Data Latency : 62.5ns
U10-U19 Data Latency : 61.6ns
U10-U21 Data Latency : 64.2ns
U10-U23 Data Latency : 63.5ns
U12-U14 Data Latency : 22.9ns
U12-U16 Data Latency : 24.5ns
U12-U18 Data Latency : 23.5ns
U12-U20 Data Latency : 26.0ns
U12-U22 Data Latency : 24.6ns
U12-U1 Data Latency : 59.5ns
U12-U3 Data Latency : 59.3ns
U12-U5 Data Latency : 60.7ns
U12-U7 Data Latency : 60.0ns
U12-U9 Data Latency : 61.8ns
U12-U11 Data Latency : 61.6ns
U12-U13 Data Latency : 12.8ns
U12-U15 Data Latency : 22.9ns
U12-U17 Data Latency : 24.5ns
U12-U19 Data Latency : 23.5ns
U12-U21 Data Latency : 25.9ns
U12-U23 Data Latency : 24.7ns
U14-U16 Data Latency : 23.7ns
U14-U18 Data Latency : 25.5ns
U14-U20 Data Latency : 24.8ns
U14-U22 Data Latency : 26.0ns
U14-U1 Data Latency : 59.9ns
U14-U3 Data Latency : 59.6ns
U14-U5 Data Latency : 60.3ns
U14-U7 Data Latency : 60.4ns
U14-U9 Data Latency : 61.7ns
U14-U11 Data Latency : 61.8ns
U14-U13 Data Latency : 22.9ns
U14-U15 Data Latency : 12.8ns
U14-U17 Data Latency : 23.4ns
U14-U19 Data Latency : 25.3ns
U14-U21 Data Latency : 24.8ns
U14-U23 Data Latency : 26.0ns
U16-U18 Data Latency : 24.3ns
U16-U20 Data Latency : 27.4ns
U16-U22 Data Latency : 26.2ns
U16-U1 Data Latency : 59.8ns
U16-U3 Data Latency : 59.1ns
U16-U5 Data Latency : 61.3ns
U16-U7 Data Latency : 60.3ns
U16-U9 Data Latency : 61.8ns
U16-U11 Data Latency : 62.1ns
U16-U13 Data Latency : 24.6ns
U16-U15 Data Latency : 23.4ns
U16-U17 Data Latency : 12.9ns
U16-U19 Data Latency : 27.0ns
U16-U21 Data Latency : 27.4ns
U16-U23 Data Latency : 26.1ns
U18-U20 Data Latency : 25.7ns
U18-U22 Data Latency : 26.6ns
U18-U1 Data Latency : 59.6ns
U18-U3 Data Latency : 60.0ns
U18-U5 Data Latency : 60.9ns
U18-U7 Data Latency : 60.4ns
U18-U9 Data Latency : 62.0ns
U18-U11 Data Latency : 62.0ns
U18-U13 Data Latency : 23.4ns
U18-U15 Data Latency : 25.3ns
U18-U17 Data Latency : 24.2ns
U18-U19 Data Latency : 12.7ns
U18-U21 Data Latency : 25.3ns
U18-U23 Data Latency : 26.5ns
U20-U22 Data Latency : 31.0ns
U20-U1 Data Latency : 62.2ns
U20-U3 Data Latency : 61.7ns
U20-U5 Data Latency : 62.8ns
U20-U7 Data Latency : 62.3ns
U20-U9 Data Latency : 64.5ns
U20-U11 Data Latency : 64.0ns
U20-U13 Data Latency : 26.1ns
U20-U15 Data Latency : 25.1ns
U20-U17 Data Latency : 27.5ns
U20-U19 Data Latency : 25.4ns
U20-U21 Data Latency : 13.0ns
U20-U23 Data Latency : 27.7ns
U22-U1 Data Latency : 61.5ns
U22-U3 Data Latency : 61.9ns
U22-U5 Data Latency : 62.6ns
U22-U7 Data Latency : 62.3ns
U22-U9 Data Latency : 64.6ns
U22-U11 Data Latency : 64.0ns
U22-U13 Data Latency : 24.8ns
U22-U15 Data Latency : 26.4ns
U22-U17 Data Latency : 26.5ns
U22-U19 Data Latency : 27.0ns
U22-U21 Data Latency : 27.4ns
U22-U23 Data Latency : 12.9ns
U1-U3 Data Latency : 22.5ns
U1-U5 Data Latency : 24.1ns
U1-U7 Data Latency : 23.1ns
U1-U9 Data Latency : 25.3ns
U1-U11 Data Latency : 24.1ns
U1-U13 Data Latency : 59.7ns
U1-U15 Data Latency : 59.0ns
U1-U17 Data Latency : 60.6ns
U1-U19 Data Latency : 60.0ns
U1-U21 Data Latency : 62.1ns
U1-U23 Data Latency : 61.7ns
U3-U5 Data Latency : 23.2ns
U3-U7 Data Latency : 25.0ns
U3-U9 Data Latency : 24.2ns
U3-U11 Data Latency : 25.6ns
U3-U13 Data Latency : 59.7ns
U3-U15 Data Latency : 59.3ns
U3-U17 Data Latency : 60.2ns
U3-U19 Data Latency : 59.8ns
U3-U21 Data Latency : 62.4ns
U3-U23 Data Latency : 61.4ns
U5-U7 Data Latency : 23.9ns
U5-U9 Data Latency : 26.6ns
U5-U11 Data Latency : 25.5ns
U5-U13 Data Latency : 59.8ns
U5-U15 Data Latency : 59.7ns
U5-U17 Data Latency : 60.4ns
U5-U19 Data Latency : 60.2ns
U5-U21 Data Latency : 62.2ns
U5-U23 Data Latency : 61.9ns
U7-U9 Data Latency : 25.0ns
U7-U11 Data Latency : 26.1ns
U7-U13 Data Latency : 60.3ns
U7-U15 Data Latency : 60.1ns
U7-U17 Data Latency : 60.9ns
U7-U19 Data Latency : 60.4ns
U7-U21 Data Latency : 62.6ns
U7-U23 Data Latency : 62.3ns
U9-U11 Data Latency : 26.5ns
U9-U13 Data Latency : 61.7ns
U9-U15 Data Latency : 60.9ns
U9-U17 Data Latency : 62.2ns
U9-U19 Data Latency : 61.7ns
U9-U21 Data Latency : 64.1ns
U9-U23 Data Latency : 63.6ns
U11-U13 Data Latency : 61.3ns
U11-U15 Data Latency : 61.1ns
U11-U17 Data Latency : 62.0ns
U11-U19 Data Latency : 61.9ns
U11-U21 Data Latency : 63.5ns
U11-U23 Data Latency : 63.4ns
U13-U15 Data Latency : 23.0ns
U13-U17 Data Latency : 24.5ns
U13-U19 Data Latency : 23.6ns
U13-U21 Data Latency : 26.0ns
U13-U23 Data Latency : 24.6ns
U15-U17 Data Latency : 23.7ns
U15-U19 Data Latency : 25.4ns
U15-U21 Data Latency : 24.8ns
U15-U23 Data Latency : 26.0ns
U17-U19 Data Latency : 27.0ns
U17-U21 Data Latency : 27.4ns
U17-U23 Data Latency : 26.1ns
U19-U21 Data Latency : 25.4ns
U19-U23 Data Latency : 26.7ns
U21-U23 Data Latency : 27.4ns
1x 64bytes Blocks Bandwidth : 14.61GB/s
4x 64bytes Blocks Bandwidth : 23.89GB/s
4x 256bytes Blocks Bandwidth : 79.26GB/s
4x 1kB Blocks Bandwidth : 248.32GB/s
4x 4kB Blocks Bandwidth : 348.41GB/s
16x 4kB Blocks Bandwidth : 464.3GB/s
4x 64kB Blocks Bandwidth : 635.87GB/s
16x 64kB Blocks Bandwidth : 501.68GB/s
8x 256kB Blocks Bandwidth : 500.62GB/s
4x 1MB Blocks Bandwidth : 507.7GB/s
8x 1MB Blocks Bandwidth : 48.55GB/s
8x 4MB Blocks Bandwidth : 19.37GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5900X 12-Core Processor (2M 12C 24T 4.92GHz, 1.9GHz IMC, 12x 512kB L2, 2x 32MB L3)
Microcode : MUAF210009
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
Platform Compliance : x64
Buffer Memory Accesses : No
No. Threads : 24
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5900X 12-Core Processor
URL : https://www.amd.com
Speed : 4.92GHz
Min/Max/Turbo Speed : 2.2GHz - 3.7GHz - 4.92GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 6 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : MUAF210009
L1D (1st Level) Data Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 12x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.





Spoiler: SiSandra MultiCore 2T



SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 134.38GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Aggregate Inter-Thread Latency : 44.2ns (12.4ns - 65.2ns)
Inter-Thread (same Core) Latency : 12.7ns
Inter-Core (same Module) Latency : 25.4ns
Inter-Module (same Package) Latency : 63.2ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.6GB/s
No. Threads : 24
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1310.48MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Aggregate Inter-Thread Latency : 4.21ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 686.32kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 27.94MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Aggregate Inter-Thread Latency : 0.09ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23
U0-U2 Data Latency : 23.3ns
U0-U4 Data Latency : 24.3ns
U0-U6 Data Latency : 23.8ns
U0-U8 Data Latency : 25.4ns
U0-U10 Data Latency : 24.2ns
U0-U12 Data Latency : 61.0ns
U0-U14 Data Latency : 61.5ns
U0-U16 Data Latency : 61.9ns
U0-U18 Data Latency : 61.7ns
U0-U20 Data Latency : 62.8ns
U0-U22 Data Latency : 62.7ns
U0-U1 Data Latency : 12.6ns
U0-U3 Data Latency : 23.3ns
U0-U5 Data Latency : 24.3ns
U0-U7 Data Latency : 23.9ns
U0-U9 Data Latency : 25.3ns
U0-U11 Data Latency : 24.3ns
U0-U13 Data Latency : 62.5ns
U0-U15 Data Latency : 61.3ns
U0-U17 Data Latency : 61.6ns
U0-U19 Data Latency : 61.6ns
U0-U21 Data Latency : 63.4ns
U0-U23 Data Latency : 62.4ns
U2-U4 Data Latency : 23.6ns
U2-U6 Data Latency : 26.0ns
U2-U8 Data Latency : 24.2ns
U2-U10 Data Latency : 25.4ns
U2-U12 Data Latency : 60.7ns
U2-U14 Data Latency : 60.9ns
U2-U16 Data Latency : 61.9ns
U2-U18 Data Latency : 62.0ns
U2-U20 Data Latency : 62.7ns
U2-U22 Data Latency : 62.1ns
U2-U1 Data Latency : 23.4ns
U2-U3 Data Latency : 12.6ns
U2-U5 Data Latency : 23.4ns
U2-U7 Data Latency : 25.9ns
U2-U9 Data Latency : 24.3ns
U2-U11 Data Latency : 25.4ns
U2-U13 Data Latency : 60.4ns
U2-U15 Data Latency : 61.3ns
U2-U17 Data Latency : 61.4ns
U2-U19 Data Latency : 62.1ns
U2-U21 Data Latency : 62.5ns
U2-U23 Data Latency : 62.3ns
U4-U6 Data Latency : 24.0ns
U4-U8 Data Latency : 26.7ns
U4-U10 Data Latency : 25.3ns
U4-U12 Data Latency : 60.4ns
U4-U14 Data Latency : 60.9ns
U4-U16 Data Latency : 62.0ns
U4-U18 Data Latency : 61.0ns
U4-U20 Data Latency : 63.2ns
U4-U22 Data Latency : 64.3ns
U4-U1 Data Latency : 24.7ns
U4-U3 Data Latency : 24.6ns
U4-U5 Data Latency : 12.6ns
U4-U7 Data Latency : 24.1ns
U4-U9 Data Latency : 25.6ns
U4-U11 Data Latency : 25.6ns
U4-U13 Data Latency : 64.1ns
U4-U15 Data Latency : 62.6ns
U4-U17 Data Latency : 63.8ns
U4-U19 Data Latency : 63.4ns
U4-U21 Data Latency : 63.4ns
U4-U23 Data Latency : 64.1ns
U6-U8 Data Latency : 25.8ns
U6-U10 Data Latency : 25.6ns
U6-U12 Data Latency : 64.2ns
U6-U14 Data Latency : 63.9ns
U6-U16 Data Latency : 64.0ns
U6-U18 Data Latency : 63.5ns
U6-U20 Data Latency : 64.0ns
U6-U22 Data Latency : 63.8ns
U6-U1 Data Latency : 24.3ns
U6-U3 Data Latency : 24.7ns
U6-U5 Data Latency : 24.1ns
U6-U7 Data Latency : 12.6ns
U6-U9 Data Latency : 25.6ns
U6-U11 Data Latency : 25.6ns
U6-U13 Data Latency : 64.1ns
U6-U15 Data Latency : 63.4ns
U6-U17 Data Latency : 64.4ns
U6-U19 Data Latency : 63.8ns
U6-U21 Data Latency : 63.7ns
U6-U23 Data Latency : 63.8ns
U8-U10 Data Latency : 28.1ns
U8-U12 Data Latency : 63.2ns
U8-U14 Data Latency : 63.7ns
U8-U16 Data Latency : 63.1ns
U8-U18 Data Latency : 63.3ns
U8-U20 Data Latency : 65.2ns
U8-U22 Data Latency : 63.4ns
U8-U1 Data Latency : 24.7ns
U8-U3 Data Latency : 24.8ns
U8-U5 Data Latency : 26.1ns
U8-U7 Data Latency : 26.0ns
U8-U9 Data Latency : 12.4ns
U8-U11 Data Latency : 27.9ns
U8-U13 Data Latency : 63.7ns
U8-U15 Data Latency : 63.6ns
U8-U17 Data Latency : 63.5ns
U8-U19 Data Latency : 63.2ns
U8-U21 Data Latency : 63.9ns
U8-U23 Data Latency : 63.7ns
U10-U12 Data Latency : 63.5ns
U10-U14 Data Latency : 63.6ns
U10-U16 Data Latency : 63.2ns
U10-U18 Data Latency : 63.7ns
U10-U20 Data Latency : 63.9ns
U10-U22 Data Latency : 64.1ns
U10-U1 Data Latency : 24.6ns
U10-U3 Data Latency : 24.8ns
U10-U5 Data Latency : 26.1ns
U10-U7 Data Latency : 26.0ns
U10-U9 Data Latency : 27.9ns
U10-U11 Data Latency : 12.4ns
U10-U13 Data Latency : 63.8ns
U10-U15 Data Latency : 63.7ns
U10-U17 Data Latency : 63.4ns
U10-U19 Data Latency : 63.0ns
U10-U21 Data Latency : 64.0ns
U10-U23 Data Latency : 64.2ns
U12-U14 Data Latency : 25.7ns
U12-U16 Data Latency : 25.4ns
U12-U18 Data Latency : 24.9ns
U12-U20 Data Latency : 24.9ns
U12-U22 Data Latency : 24.7ns
U12-U1 Data Latency : 63.7ns
U12-U3 Data Latency : 63.2ns
U12-U5 Data Latency : 62.9ns
U12-U7 Data Latency : 62.8ns
U12-U9 Data Latency : 62.6ns
U12-U11 Data Latency : 63.1ns
U12-U13 Data Latency : 12.9ns
U12-U15 Data Latency : 25.5ns
U12-U17 Data Latency : 25.1ns
U12-U19 Data Latency : 24.9ns
U12-U21 Data Latency : 24.9ns
U12-U23 Data Latency : 24.7ns
U14-U16 Data Latency : 25.1ns
U14-U18 Data Latency : 25.0ns
U14-U20 Data Latency : 24.9ns
U14-U22 Data Latency : 24.7ns
U14-U1 Data Latency : 63.5ns
U14-U3 Data Latency : 63.6ns
U14-U5 Data Latency : 62.9ns
U14-U7 Data Latency : 62.9ns
U14-U9 Data Latency : 62.8ns
U14-U11 Data Latency : 62.5ns
U14-U13 Data Latency : 25.6ns
U14-U15 Data Latency : 12.8ns
U14-U17 Data Latency : 25.0ns
U14-U19 Data Latency : 24.8ns
U14-U21 Data Latency : 25.0ns
U14-U23 Data Latency : 24.7ns
U16-U18 Data Latency : 24.6ns
U16-U20 Data Latency : 26.5ns
U16-U22 Data Latency : 26.3ns
U16-U1 Data Latency : 63.4ns
U16-U3 Data Latency : 63.6ns
U16-U5 Data Latency : 62.5ns
U16-U7 Data Latency : 63.2ns
U16-U9 Data Latency : 62.9ns
U16-U11 Data Latency : 62.7ns
U16-U13 Data Latency : 25.2ns
U16-U15 Data Latency : 25.0ns
U16-U17 Data Latency : 12.9ns
U16-U19 Data Latency : 24.5ns
U16-U21 Data Latency : 26.5ns
U16-U23 Data Latency : 26.3ns
U18-U20 Data Latency : 26.5ns
U18-U22 Data Latency : 26.1ns
U18-U1 Data Latency : 62.5ns
U18-U3 Data Latency : 63.2ns
U18-U5 Data Latency : 62.8ns
U18-U7 Data Latency : 63.1ns
U18-U9 Data Latency : 63.2ns
U18-U11 Data Latency : 62.4ns
U18-U13 Data Latency : 24.9ns
U18-U15 Data Latency : 25.0ns
U18-U17 Data Latency : 24.6ns
U18-U19 Data Latency : 12.7ns
U18-U21 Data Latency : 26.1ns
U18-U23 Data Latency : 26.0ns
U20-U22 Data Latency : 29.2ns
U20-U1 Data Latency : 63.9ns
U20-U3 Data Latency : 63.8ns
U20-U5 Data Latency : 63.7ns
U20-U7 Data Latency : 63.6ns
U20-U9 Data Latency : 63.8ns
U20-U11 Data Latency : 64.2ns
U20-U13 Data Latency : 25.4ns
U20-U15 Data Latency : 25.3ns
U20-U17 Data Latency : 27.0ns
U20-U19 Data Latency : 26.8ns
U20-U21 Data Latency : 13.0ns
U20-U23 Data Latency : 29.3ns
U22-U1 Data Latency : 63.3ns
U22-U3 Data Latency : 64.1ns
U22-U5 Data Latency : 63.9ns
U22-U7 Data Latency : 63.8ns
U22-U9 Data Latency : 64.3ns
U22-U11 Data Latency : 64.3ns
U22-U13 Data Latency : 25.4ns
U22-U15 Data Latency : 25.5ns
U22-U17 Data Latency : 26.4ns
U22-U19 Data Latency : 26.3ns
U22-U21 Data Latency : 28.1ns
U22-U23 Data Latency : 12.9ns
U1-U3 Data Latency : 22.8ns
U1-U5 Data Latency : 23.5ns
U1-U7 Data Latency : 23.3ns
U1-U9 Data Latency : 24.3ns
U1-U11 Data Latency : 24.2ns
U1-U13 Data Latency : 59.7ns
U1-U15 Data Latency : 60.1ns
U1-U17 Data Latency : 60.8ns
U1-U19 Data Latency : 60.2ns
U1-U21 Data Latency : 61.8ns
U1-U23 Data Latency : 61.8ns
U3-U5 Data Latency : 23.4ns
U3-U7 Data Latency : 23.5ns
U3-U9 Data Latency : 24.3ns
U3-U11 Data Latency : 24.2ns
U3-U13 Data Latency : 60.4ns
U3-U15 Data Latency : 59.8ns
U3-U17 Data Latency : 60.8ns
U3-U19 Data Latency : 60.6ns
U3-U21 Data Latency : 62.1ns
U3-U23 Data Latency : 62.8ns
U5-U7 Data Latency : 24.0ns
U5-U9 Data Latency : 25.4ns
U5-U11 Data Latency : 25.7ns
U5-U13 Data Latency : 60.4ns
U5-U15 Data Latency : 59.9ns
U5-U17 Data Latency : 60.5ns
U5-U19 Data Latency : 60.2ns
U5-U21 Data Latency : 62.5ns
U5-U23 Data Latency : 62.0ns
U7-U9 Data Latency : 25.8ns
U7-U11 Data Latency : 25.6ns
U7-U13 Data Latency : 60.6ns
U7-U15 Data Latency : 60.2ns
U7-U17 Data Latency : 60.7ns
U7-U19 Data Latency : 61.3ns
U7-U21 Data Latency : 62.1ns
U7-U23 Data Latency : 63.0ns
U9-U11 Data Latency : 27.1ns
U9-U13 Data Latency : 61.2ns
U9-U15 Data Latency : 61.3ns
U9-U17 Data Latency : 62.2ns
U9-U19 Data Latency : 61.4ns
U9-U21 Data Latency : 63.5ns
U9-U23 Data Latency : 63.3ns
U11-U13 Data Latency : 61.0ns
U11-U15 Data Latency : 61.7ns
U11-U17 Data Latency : 61.5ns
U11-U19 Data Latency : 61.8ns
U11-U21 Data Latency : 63.9ns
U11-U23 Data Latency : 63.4ns
U13-U15 Data Latency : 23.2ns
U13-U17 Data Latency : 23.9ns
U13-U19 Data Latency : 23.6ns
U13-U21 Data Latency : 24.7ns
U13-U23 Data Latency : 24.9ns
U15-U17 Data Latency : 23.9ns
U15-U19 Data Latency : 23.8ns
U15-U21 Data Latency : 24.8ns
U15-U23 Data Latency : 24.6ns
U17-U19 Data Latency : 24.4ns
U17-U21 Data Latency : 26.3ns
U17-U23 Data Latency : 26.2ns
U19-U21 Data Latency : 26.2ns
U19-U23 Data Latency : 26.1ns
U21-U23 Data Latency : 28.0ns
1x 64bytes Blocks Bandwidth : 14.88GB/s
4x 64bytes Blocks Bandwidth : 14.26GB/s
4x 256bytes Blocks Bandwidth : 74.7GB/s
4x 1kB Blocks Bandwidth : 230.23GB/s
4x 4kB Blocks Bandwidth : 344.82GB/s
16x 4kB Blocks Bandwidth : 452.25GB/s
4x 64kB Blocks Bandwidth : 636GB/s
16x 64kB Blocks Bandwidth : 502GB/s
8x 256kB Blocks Bandwidth : 499GB/s
4x 1MB Blocks Bandwidth : 504.56GB/s
8x 1MB Blocks Bandwidth : 40.51GB/s
8x 4MB Blocks Bandwidth : 18.7GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5900X 12-Core Processor (2M 12C 24T 4.92GHz, 1.9GHz IMC, 12x 512kB L2, 2x 32MB L3)
Microcode : MUAF210009
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
Platform Compliance : x64
Buffer Memory Accesses : No
No. Threads : 24
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5900X 12-Core Processor
URL : https://www.amd.com
Speed : 4.92GHz
Min/Max/Turbo Speed : 2.2GHz - 3.7GHz - 4.92GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 6 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : MUAF210009
L1D (1st Level) Data Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 12x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## mongoled

domdtxdissar said:


> The deed is done, have gotten this fully stable
> 
> BIOS 3501 with AGESA V2 PI 1.2.0.2
> dual CCD 5950x
> 4x8GB gskill 3600 CL16
> 1900:3800 @ flat CL14 + T1 GDM-OFF
> Screenshot of TM 1umus 25 cycle + Memtest 20000% stable (do notice this is my old bloaty windows install with lots of stuff running in background)
> View attachment 2490191
> 
> 
> 
> Newest OCCT 8.1.3 1 hour large dataset extreme + 4 iteration in y-cruncher with all tests (same boot as above)
> View attachment 2490192
> 
> 
> Some performance number:
> The SiSoftSandra v2021.31.12 (from Mar 5th, 2021). Not sure this is a good match with CTR..
> Intel latency checker
> View attachment 2490194
> 
> 
> 
> Next we have dram calc easy + normal bench together with cinebench r23
> View attachment 2490195
> 
> 
> And lastly we have SotTR @ 1080p lowest as a gamebench running on my new 24/7 settings =288 CPU average fps
> View attachment 2490196
> 
> 
> Very happy with these results and my new 24/7 settings
> Maybe i will try to push for higher fclk now 😎
> 
> Feel free to leave any comments or questions


Darn you!

Its a sickness of the mind

😂😂😂

Well done

 

Now I thought I had managed to re-calibrate my mind as to not "needing" flat 14s, unfortunately I didnt do a good enough job as I am considering buying one more set of Viper Steels 4400 mhz modules as I really want the flat 14s. Its quite stupid really, as its not going to make any "real" difference if running tRCDRD @15 but it just bugs me that one of the four sticks cant do it .....


----------



## kompira

lmfodor said:


> Hi @Veii, I tried your suggestions about CADBUS Setup. I could disable RTTWR with 6-0-3 for 1.51VDIMM but I couldn't get post with 27-27-27. 27-27-56 nor 26-26-26 or 25-25-25. I did the math I think based in the Korean Site,
> 
> 56 = 111000
> 5-bit value = 1 = coatse delay activation = 1 MCLK delay = molecule 1 = 1/?
> You can calculate the fine delay by subtracting 32.
> 56 - 32 = 24
> Delay = 24*1/32 = 24/32 = 3/4 MCLK, 24 Sf 24 = ?/24
> That is, 56 = 1/24.
> The actual delay will be = 1+3/4 = 1.75 MCLK
> But according to the CAD Delay table, 56 would be the same as 25, and I guess 1.8M / T should be 58 or 26 or 27 as you suggested. So, you should try 25 .. It should work, right? I also played with tCKE 9 or 16, but couldn't get the post.
> 
> 
> Spoiler: CAD Delay Table
> 
> 
> 
> 
> View attachment 2490303
> 
> 
> 
> This is the final comparison between the two times. I managed to lower the tRCDRD to 15 by changing tRDWR to 8 and tWRRD to 3, but did not notice a big improvement, and I lowered the vSOC to 1.2, IOD and CCD in line with this value, and also lowered ProcODT to 36 and set a stronger ClkDvrStr at 60, with this setting I could stop errors 6 and 0 and from what I read this would give a better signal and not so much strain to the IMC, right? .. The performance difference between 1T and 2T is noticeable in bandwidth and maybe the RTTWR turned off could equal the latency with 56-56-56. I will keep trying
> View attachment 2490307
> 
> This is the SiSandra results for a 5900x 1T vs 2T
> 
> 
> Spoiler: SiSandra MultiCore 1T
> 
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 144.77GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Aggregate Inter-Thread Latency : 43.4ns (12.4ns - 64.6ns)
> Inter-Thread (same Core) Latency : 12.7ns
> Inter-Core (same Module) Latency : 25.1ns
> Inter-Module (same Package) Latency : 61.3ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 6GB/s
> No. Threads : 24
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1411.86MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Aggregate Inter-Thread Latency : 4.13ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 686.32kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 30.10MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Aggregate Inter-Thread Latency : 0.09ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23
> U0-U2 Data Latency : 22.7ns
> U0-U4 Data Latency : 24.7ns
> U0-U6 Data Latency : 23.2ns
> U0-U8 Data Latency : 24.8ns
> U0-U10 Data Latency : 24.0ns
> U0-U12 Data Latency : 59.3ns
> U0-U14 Data Latency : 59.1ns
> U0-U16 Data Latency : 59.9ns
> U0-U18 Data Latency : 60.0ns
> U0-U20 Data Latency : 61.4ns
> U0-U22 Data Latency : 61.3ns
> U0-U1 Data Latency : 12.6ns
> U0-U3 Data Latency : 22.4ns
> U0-U5 Data Latency : 24.0ns
> U0-U7 Data Latency : 23.1ns
> U0-U9 Data Latency : 28.5ns
> U0-U11 Data Latency : 24.1ns
> U0-U13 Data Latency : 59.6ns
> U0-U15 Data Latency : 59.4ns
> U0-U17 Data Latency : 60.2ns
> U0-U19 Data Latency : 59.8ns
> U0-U21 Data Latency : 61.7ns
> U0-U23 Data Latency : 61.2ns
> U2-U4 Data Latency : 23.2ns
> U2-U6 Data Latency : 25.0ns
> U2-U8 Data Latency : 24.3ns
> U2-U10 Data Latency : 25.5ns
> U2-U12 Data Latency : 59.5ns
> U2-U14 Data Latency : 59.7ns
> U2-U16 Data Latency : 60.3ns
> U2-U18 Data Latency : 60.3ns
> U2-U20 Data Latency : 62.4ns
> U2-U22 Data Latency : 61.9ns
> U2-U1 Data Latency : 22.4ns
> U2-U3 Data Latency : 12.6ns
> U2-U5 Data Latency : 22.7ns
> U2-U7 Data Latency : 25.0ns
> U2-U9 Data Latency : 24.3ns
> U2-U11 Data Latency : 25.5ns
> U2-U13 Data Latency : 59.7ns
> U2-U15 Data Latency : 59.4ns
> U2-U17 Data Latency : 60.2ns
> U2-U19 Data Latency : 60.4ns
> U2-U21 Data Latency : 62.2ns
> U2-U23 Data Latency : 61.6ns
> U4-U6 Data Latency : 23.9ns
> U4-U8 Data Latency : 26.6ns
> U4-U10 Data Latency : 25.5ns
> U4-U12 Data Latency : 60.1ns
> U4-U14 Data Latency : 59.5ns
> U4-U16 Data Latency : 60.6ns
> U4-U18 Data Latency : 60.3ns
> U4-U20 Data Latency : 62.4ns
> U4-U22 Data Latency : 61.7ns
> U4-U1 Data Latency : 24.1ns
> U4-U3 Data Latency : 23.0ns
> U4-U5 Data Latency : 12.6ns
> U4-U7 Data Latency : 23.7ns
> U4-U9 Data Latency : 26.6ns
> U4-U11 Data Latency : 25.6ns
> U4-U13 Data Latency : 59.3ns
> U4-U15 Data Latency : 59.2ns
> U4-U17 Data Latency : 60.7ns
> U4-U19 Data Latency : 59.6ns
> U4-U21 Data Latency : 62.3ns
> U4-U23 Data Latency : 62.0ns
> U6-U8 Data Latency : 28.8ns
> U6-U10 Data Latency : 26.1ns
> U6-U12 Data Latency : 60.5ns
> U6-U14 Data Latency : 60.3ns
> U6-U16 Data Latency : 61.4ns
> U6-U18 Data Latency : 61.0ns
> U6-U20 Data Latency : 62.9ns
> U6-U22 Data Latency : 62.1ns
> U6-U1 Data Latency : 22.8ns
> U6-U3 Data Latency : 25.0ns
> U6-U5 Data Latency : 23.8ns
> U6-U7 Data Latency : 12.6ns
> U6-U9 Data Latency : 24.8ns
> U6-U11 Data Latency : 26.1ns
> U6-U13 Data Latency : 60.4ns
> U6-U15 Data Latency : 60.3ns
> U6-U17 Data Latency : 61.2ns
> U6-U19 Data Latency : 61.3ns
> U6-U21 Data Latency : 62.7ns
> U6-U23 Data Latency : 62.3ns
> U8-U10 Data Latency : 26.5ns
> U8-U12 Data Latency : 61.3ns
> U8-U14 Data Latency : 61.0ns
> U8-U16 Data Latency : 61.6ns
> U8-U18 Data Latency : 61.5ns
> U8-U20 Data Latency : 63.9ns
> U8-U22 Data Latency : 63.2ns
> U8-U1 Data Latency : 25.4ns
> U8-U3 Data Latency : 24.4ns
> U8-U5 Data Latency : 26.9ns
> U8-U7 Data Latency : 24.9ns
> U8-U9 Data Latency : 12.4ns
> U8-U11 Data Latency : 26.4ns
> U8-U13 Data Latency : 61.7ns
> U8-U15 Data Latency : 61.1ns
> U8-U17 Data Latency : 62.4ns
> U8-U19 Data Latency : 61.7ns
> U8-U21 Data Latency : 63.8ns
> U8-U23 Data Latency : 64.0ns
> U10-U12 Data Latency : 61.3ns
> U10-U14 Data Latency : 60.9ns
> U10-U16 Data Latency : 62.0ns
> U10-U18 Data Latency : 61.2ns
> U10-U20 Data Latency : 63.3ns
> U10-U22 Data Latency : 63.3ns
> U10-U1 Data Latency : 24.0ns
> U10-U3 Data Latency : 25.6ns
> U10-U5 Data Latency : 25.5ns
> U10-U7 Data Latency : 26.0ns
> U10-U9 Data Latency : 26.3ns
> U10-U11 Data Latency : 12.4ns
> U10-U13 Data Latency : 61.5ns
> U10-U15 Data Latency : 60.9ns
> U10-U17 Data Latency : 62.5ns
> U10-U19 Data Latency : 61.6ns
> U10-U21 Data Latency : 64.2ns
> U10-U23 Data Latency : 63.5ns
> U12-U14 Data Latency : 22.9ns
> U12-U16 Data Latency : 24.5ns
> U12-U18 Data Latency : 23.5ns
> U12-U20 Data Latency : 26.0ns
> U12-U22 Data Latency : 24.6ns
> U12-U1 Data Latency : 59.5ns
> U12-U3 Data Latency : 59.3ns
> U12-U5 Data Latency : 60.7ns
> U12-U7 Data Latency : 60.0ns
> U12-U9 Data Latency : 61.8ns
> U12-U11 Data Latency : 61.6ns
> U12-U13 Data Latency : 12.8ns
> U12-U15 Data Latency : 22.9ns
> U12-U17 Data Latency : 24.5ns
> U12-U19 Data Latency : 23.5ns
> U12-U21 Data Latency : 25.9ns
> U12-U23 Data Latency : 24.7ns
> U14-U16 Data Latency : 23.7ns
> U14-U18 Data Latency : 25.5ns
> U14-U20 Data Latency : 24.8ns
> U14-U22 Data Latency : 26.0ns
> U14-U1 Data Latency : 59.9ns
> U14-U3 Data Latency : 59.6ns
> U14-U5 Data Latency : 60.3ns
> U14-U7 Data Latency : 60.4ns
> U14-U9 Data Latency : 61.7ns
> U14-U11 Data Latency : 61.8ns
> U14-U13 Data Latency : 22.9ns
> U14-U15 Data Latency : 12.8ns
> U14-U17 Data Latency : 23.4ns
> U14-U19 Data Latency : 25.3ns
> U14-U21 Data Latency : 24.8ns
> U14-U23 Data Latency : 26.0ns
> U16-U18 Data Latency : 24.3ns
> U16-U20 Data Latency : 27.4ns
> U16-U22 Data Latency : 26.2ns
> U16-U1 Data Latency : 59.8ns
> U16-U3 Data Latency : 59.1ns
> U16-U5 Data Latency : 61.3ns
> U16-U7 Data Latency : 60.3ns
> U16-U9 Data Latency : 61.8ns
> U16-U11 Data Latency : 62.1ns
> U16-U13 Data Latency : 24.6ns
> U16-U15 Data Latency : 23.4ns
> U16-U17 Data Latency : 12.9ns
> U16-U19 Data Latency : 27.0ns
> U16-U21 Data Latency : 27.4ns
> U16-U23 Data Latency : 26.1ns
> U18-U20 Data Latency : 25.7ns
> U18-U22 Data Latency : 26.6ns
> U18-U1 Data Latency : 59.6ns
> U18-U3 Data Latency : 60.0ns
> U18-U5 Data Latency : 60.9ns
> U18-U7 Data Latency : 60.4ns
> U18-U9 Data Latency : 62.0ns
> U18-U11 Data Latency : 62.0ns
> U18-U13 Data Latency : 23.4ns
> U18-U15 Data Latency : 25.3ns
> U18-U17 Data Latency : 24.2ns
> U18-U19 Data Latency : 12.7ns
> U18-U21 Data Latency : 25.3ns
> U18-U23 Data Latency : 26.5ns
> U20-U22 Data Latency : 31.0ns
> U20-U1 Data Latency : 62.2ns
> U20-U3 Data Latency : 61.7ns
> U20-U5 Data Latency : 62.8ns
> U20-U7 Data Latency : 62.3ns
> U20-U9 Data Latency : 64.5ns
> U20-U11 Data Latency : 64.0ns
> U20-U13 Data Latency : 26.1ns
> U20-U15 Data Latency : 25.1ns
> U20-U17 Data Latency : 27.5ns
> U20-U19 Data Latency : 25.4ns
> U20-U21 Data Latency : 13.0ns
> U20-U23 Data Latency : 27.7ns
> U22-U1 Data Latency : 61.5ns
> U22-U3 Data Latency : 61.9ns
> U22-U5 Data Latency : 62.6ns
> U22-U7 Data Latency : 62.3ns
> U22-U9 Data Latency : 64.6ns
> U22-U11 Data Latency : 64.0ns
> U22-U13 Data Latency : 24.8ns
> U22-U15 Data Latency : 26.4ns
> U22-U17 Data Latency : 26.5ns
> U22-U19 Data Latency : 27.0ns
> U22-U21 Data Latency : 27.4ns
> U22-U23 Data Latency : 12.9ns
> U1-U3 Data Latency : 22.5ns
> U1-U5 Data Latency : 24.1ns
> U1-U7 Data Latency : 23.1ns
> U1-U9 Data Latency : 25.3ns
> U1-U11 Data Latency : 24.1ns
> U1-U13 Data Latency : 59.7ns
> U1-U15 Data Latency : 59.0ns
> U1-U17 Data Latency : 60.6ns
> U1-U19 Data Latency : 60.0ns
> U1-U21 Data Latency : 62.1ns
> U1-U23 Data Latency : 61.7ns
> U3-U5 Data Latency : 23.2ns
> U3-U7 Data Latency : 25.0ns
> U3-U9 Data Latency : 24.2ns
> U3-U11 Data Latency : 25.6ns
> U3-U13 Data Latency : 59.7ns
> U3-U15 Data Latency : 59.3ns
> U3-U17 Data Latency : 60.2ns
> U3-U19 Data Latency : 59.8ns
> U3-U21 Data Latency : 62.4ns
> U3-U23 Data Latency : 61.4ns
> U5-U7 Data Latency : 23.9ns
> U5-U9 Data Latency : 26.6ns
> U5-U11 Data Latency : 25.5ns
> U5-U13 Data Latency : 59.8ns
> U5-U15 Data Latency : 59.7ns
> U5-U17 Data Latency : 60.4ns
> U5-U19 Data Latency : 60.2ns
> U5-U21 Data Latency : 62.2ns
> U5-U23 Data Latency : 61.9ns
> U7-U9 Data Latency : 25.0ns
> U7-U11 Data Latency : 26.1ns
> U7-U13 Data Latency : 60.3ns
> U7-U15 Data Latency : 60.1ns
> U7-U17 Data Latency : 60.9ns
> U7-U19 Data Latency : 60.4ns
> U7-U21 Data Latency : 62.6ns
> U7-U23 Data Latency : 62.3ns
> U9-U11 Data Latency : 26.5ns
> U9-U13 Data Latency : 61.7ns
> U9-U15 Data Latency : 60.9ns
> U9-U17 Data Latency : 62.2ns
> U9-U19 Data Latency : 61.7ns
> U9-U21 Data Latency : 64.1ns
> U9-U23 Data Latency : 63.6ns
> U11-U13 Data Latency : 61.3ns
> U11-U15 Data Latency : 61.1ns
> U11-U17 Data Latency : 62.0ns
> U11-U19 Data Latency : 61.9ns
> U11-U21 Data Latency : 63.5ns
> U11-U23 Data Latency : 63.4ns
> U13-U15 Data Latency : 23.0ns
> U13-U17 Data Latency : 24.5ns
> U13-U19 Data Latency : 23.6ns
> U13-U21 Data Latency : 26.0ns
> U13-U23 Data Latency : 24.6ns
> U15-U17 Data Latency : 23.7ns
> U15-U19 Data Latency : 25.4ns
> U15-U21 Data Latency : 24.8ns
> U15-U23 Data Latency : 26.0ns
> U17-U19 Data Latency : 27.0ns
> U17-U21 Data Latency : 27.4ns
> U17-U23 Data Latency : 26.1ns
> U19-U21 Data Latency : 25.4ns
> U19-U23 Data Latency : 26.7ns
> U21-U23 Data Latency : 27.4ns
> 1x 64bytes Blocks Bandwidth : 14.61GB/s
> 4x 64bytes Blocks Bandwidth : 23.89GB/s
> 4x 256bytes Blocks Bandwidth : 79.26GB/s
> 4x 1kB Blocks Bandwidth : 248.32GB/s
> 4x 4kB Blocks Bandwidth : 348.41GB/s
> 16x 4kB Blocks Bandwidth : 464.3GB/s
> 4x 64kB Blocks Bandwidth : 635.87GB/s
> 16x 64kB Blocks Bandwidth : 501.68GB/s
> 8x 256kB Blocks Bandwidth : 500.62GB/s
> 4x 1MB Blocks Bandwidth : 507.7GB/s
> 8x 1MB Blocks Bandwidth : 48.55GB/s
> 8x 4MB Blocks Bandwidth : 19.37GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5900X 12-Core Processor (2M 12C 24T 4.92GHz, 1.9GHz IMC, 12x 512kB L2, 2x 32MB L3)
> Microcode : MUAF210009
> Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
> Platform Compliance : x64
> Buffer Memory Accesses : No
> No. Threads : 24
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5900X 12-Core Processor
> URL : https://www.amd.com
> Speed : 4.92GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.7GHz - 4.92GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 6 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : MUAF210009
> L1D (1st Level) Data Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 12x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.
> 
> 
> 
> 
> 
> Spoiler: SiSandra MultiCore 2T
> 
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 134.38GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Aggregate Inter-Thread Latency : 44.2ns (12.4ns - 65.2ns)
> Inter-Thread (same Core) Latency : 12.7ns
> Inter-Core (same Module) Latency : 25.4ns
> Inter-Module (same Package) Latency : 63.2ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5.6GB/s
> No. Threads : 24
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1310.48MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Aggregate Inter-Thread Latency : 4.21ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 686.32kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 27.94MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Aggregate Inter-Thread Latency : 0.09ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23
> U0-U2 Data Latency : 23.3ns
> U0-U4 Data Latency : 24.3ns
> U0-U6 Data Latency : 23.8ns
> U0-U8 Data Latency : 25.4ns
> U0-U10 Data Latency : 24.2ns
> U0-U12 Data Latency : 61.0ns
> U0-U14 Data Latency : 61.5ns
> U0-U16 Data Latency : 61.9ns
> U0-U18 Data Latency : 61.7ns
> U0-U20 Data Latency : 62.8ns
> U0-U22 Data Latency : 62.7ns
> U0-U1 Data Latency : 12.6ns
> U0-U3 Data Latency : 23.3ns
> U0-U5 Data Latency : 24.3ns
> U0-U7 Data Latency : 23.9ns
> U0-U9 Data Latency : 25.3ns
> U0-U11 Data Latency : 24.3ns
> U0-U13 Data Latency : 62.5ns
> U0-U15 Data Latency : 61.3ns
> U0-U17 Data Latency : 61.6ns
> U0-U19 Data Latency : 61.6ns
> U0-U21 Data Latency : 63.4ns
> U0-U23 Data Latency : 62.4ns
> U2-U4 Data Latency : 23.6ns
> U2-U6 Data Latency : 26.0ns
> U2-U8 Data Latency : 24.2ns
> U2-U10 Data Latency : 25.4ns
> U2-U12 Data Latency : 60.7ns
> U2-U14 Data Latency : 60.9ns
> U2-U16 Data Latency : 61.9ns
> U2-U18 Data Latency : 62.0ns
> U2-U20 Data Latency : 62.7ns
> U2-U22 Data Latency : 62.1ns
> U2-U1 Data Latency : 23.4ns
> U2-U3 Data Latency : 12.6ns
> U2-U5 Data Latency : 23.4ns
> U2-U7 Data Latency : 25.9ns
> U2-U9 Data Latency : 24.3ns
> U2-U11 Data Latency : 25.4ns
> U2-U13 Data Latency : 60.4ns
> U2-U15 Data Latency : 61.3ns
> U2-U17 Data Latency : 61.4ns
> U2-U19 Data Latency : 62.1ns
> U2-U21 Data Latency : 62.5ns
> U2-U23 Data Latency : 62.3ns
> U4-U6 Data Latency : 24.0ns
> U4-U8 Data Latency : 26.7ns
> U4-U10 Data Latency : 25.3ns
> U4-U12 Data Latency : 60.4ns
> U4-U14 Data Latency : 60.9ns
> U4-U16 Data Latency : 62.0ns
> U4-U18 Data Latency : 61.0ns
> U4-U20 Data Latency : 63.2ns
> U4-U22 Data Latency : 64.3ns
> U4-U1 Data Latency : 24.7ns
> U4-U3 Data Latency : 24.6ns
> U4-U5 Data Latency : 12.6ns
> U4-U7 Data Latency : 24.1ns
> U4-U9 Data Latency : 25.6ns
> U4-U11 Data Latency : 25.6ns
> U4-U13 Data Latency : 64.1ns
> U4-U15 Data Latency : 62.6ns
> U4-U17 Data Latency : 63.8ns
> U4-U19 Data Latency : 63.4ns
> U4-U21 Data Latency : 63.4ns
> U4-U23 Data Latency : 64.1ns
> U6-U8 Data Latency : 25.8ns
> U6-U10 Data Latency : 25.6ns
> U6-U12 Data Latency : 64.2ns
> U6-U14 Data Latency : 63.9ns
> U6-U16 Data Latency : 64.0ns
> U6-U18 Data Latency : 63.5ns
> U6-U20 Data Latency : 64.0ns
> U6-U22 Data Latency : 63.8ns
> U6-U1 Data Latency : 24.3ns
> U6-U3 Data Latency : 24.7ns
> U6-U5 Data Latency : 24.1ns
> U6-U7 Data Latency : 12.6ns
> U6-U9 Data Latency : 25.6ns
> U6-U11 Data Latency : 25.6ns
> U6-U13 Data Latency : 64.1ns
> U6-U15 Data Latency : 63.4ns
> U6-U17 Data Latency : 64.4ns
> U6-U19 Data Latency : 63.8ns
> U6-U21 Data Latency : 63.7ns
> U6-U23 Data Latency : 63.8ns
> U8-U10 Data Latency : 28.1ns
> U8-U12 Data Latency : 63.2ns
> U8-U14 Data Latency : 63.7ns
> U8-U16 Data Latency : 63.1ns
> U8-U18 Data Latency : 63.3ns
> U8-U20 Data Latency : 65.2ns
> U8-U22 Data Latency : 63.4ns
> U8-U1 Data Latency : 24.7ns
> U8-U3 Data Latency : 24.8ns
> U8-U5 Data Latency : 26.1ns
> U8-U7 Data Latency : 26.0ns
> U8-U9 Data Latency : 12.4ns
> U8-U11 Data Latency : 27.9ns
> U8-U13 Data Latency : 63.7ns
> U8-U15 Data Latency : 63.6ns
> U8-U17 Data Latency : 63.5ns
> U8-U19 Data Latency : 63.2ns
> U8-U21 Data Latency : 63.9ns
> U8-U23 Data Latency : 63.7ns
> U10-U12 Data Latency : 63.5ns
> U10-U14 Data Latency : 63.6ns
> U10-U16 Data Latency : 63.2ns
> U10-U18 Data Latency : 63.7ns
> U10-U20 Data Latency : 63.9ns
> U10-U22 Data Latency : 64.1ns
> U10-U1 Data Latency : 24.6ns
> U10-U3 Data Latency : 24.8ns
> U10-U5 Data Latency : 26.1ns
> U10-U7 Data Latency : 26.0ns
> U10-U9 Data Latency : 27.9ns
> U10-U11 Data Latency : 12.4ns
> U10-U13 Data Latency : 63.8ns
> U10-U15 Data Latency : 63.7ns
> U10-U17 Data Latency : 63.4ns
> U10-U19 Data Latency : 63.0ns
> U10-U21 Data Latency : 64.0ns
> U10-U23 Data Latency : 64.2ns
> U12-U14 Data Latency : 25.7ns
> U12-U16 Data Latency : 25.4ns
> U12-U18 Data Latency : 24.9ns
> U12-U20 Data Latency : 24.9ns
> U12-U22 Data Latency : 24.7ns
> U12-U1 Data Latency : 63.7ns
> U12-U3 Data Latency : 63.2ns
> U12-U5 Data Latency : 62.9ns
> U12-U7 Data Latency : 62.8ns
> U12-U9 Data Latency : 62.6ns
> U12-U11 Data Latency : 63.1ns
> U12-U13 Data Latency : 12.9ns
> U12-U15 Data Latency : 25.5ns
> U12-U17 Data Latency : 25.1ns
> U12-U19 Data Latency : 24.9ns
> U12-U21 Data Latency : 24.9ns
> U12-U23 Data Latency : 24.7ns
> U14-U16 Data Latency : 25.1ns
> U14-U18 Data Latency : 25.0ns
> U14-U20 Data Latency : 24.9ns
> U14-U22 Data Latency : 24.7ns
> U14-U1 Data Latency : 63.5ns
> U14-U3 Data Latency : 63.6ns
> U14-U5 Data Latency : 62.9ns
> U14-U7 Data Latency : 62.9ns
> U14-U9 Data Latency : 62.8ns
> U14-U11 Data Latency : 62.5ns
> U14-U13 Data Latency : 25.6ns
> U14-U15 Data Latency : 12.8ns
> U14-U17 Data Latency : 25.0ns
> U14-U19 Data Latency : 24.8ns
> U14-U21 Data Latency : 25.0ns
> U14-U23 Data Latency : 24.7ns
> U16-U18 Data Latency : 24.6ns
> U16-U20 Data Latency : 26.5ns
> U16-U22 Data Latency : 26.3ns
> U16-U1 Data Latency : 63.4ns
> U16-U3 Data Latency : 63.6ns
> U16-U5 Data Latency : 62.5ns
> U16-U7 Data Latency : 63.2ns
> U16-U9 Data Latency : 62.9ns
> U16-U11 Data Latency : 62.7ns
> U16-U13 Data Latency : 25.2ns
> U16-U15 Data Latency : 25.0ns
> U16-U17 Data Latency : 12.9ns
> U16-U19 Data Latency : 24.5ns
> U16-U21 Data Latency : 26.5ns
> U16-U23 Data Latency : 26.3ns
> U18-U20 Data Latency : 26.5ns
> U18-U22 Data Latency : 26.1ns
> U18-U1 Data Latency : 62.5ns
> U18-U3 Data Latency : 63.2ns
> U18-U5 Data Latency : 62.8ns
> U18-U7 Data Latency : 63.1ns
> U18-U9 Data Latency : 63.2ns
> U18-U11 Data Latency : 62.4ns
> U18-U13 Data Latency : 24.9ns
> U18-U15 Data Latency : 25.0ns
> U18-U17 Data Latency : 24.6ns
> U18-U19 Data Latency : 12.7ns
> U18-U21 Data Latency : 26.1ns
> U18-U23 Data Latency : 26.0ns
> U20-U22 Data Latency : 29.2ns
> U20-U1 Data Latency : 63.9ns
> U20-U3 Data Latency : 63.8ns
> U20-U5 Data Latency : 63.7ns
> U20-U7 Data Latency : 63.6ns
> U20-U9 Data Latency : 63.8ns
> U20-U11 Data Latency : 64.2ns
> U20-U13 Data Latency : 25.4ns
> U20-U15 Data Latency : 25.3ns
> U20-U17 Data Latency : 27.0ns
> U20-U19 Data Latency : 26.8ns
> U20-U21 Data Latency : 13.0ns
> U20-U23 Data Latency : 29.3ns
> U22-U1 Data Latency : 63.3ns
> U22-U3 Data Latency : 64.1ns
> U22-U5 Data Latency : 63.9ns
> U22-U7 Data Latency : 63.8ns
> U22-U9 Data Latency : 64.3ns
> U22-U11 Data Latency : 64.3ns
> U22-U13 Data Latency : 25.4ns
> U22-U15 Data Latency : 25.5ns
> U22-U17 Data Latency : 26.4ns
> U22-U19 Data Latency : 26.3ns
> U22-U21 Data Latency : 28.1ns
> U22-U23 Data Latency : 12.9ns
> U1-U3 Data Latency : 22.8ns
> U1-U5 Data Latency : 23.5ns
> U1-U7 Data Latency : 23.3ns
> U1-U9 Data Latency : 24.3ns
> U1-U11 Data Latency : 24.2ns
> U1-U13 Data Latency : 59.7ns
> U1-U15 Data Latency : 60.1ns
> U1-U17 Data Latency : 60.8ns
> U1-U19 Data Latency : 60.2ns
> U1-U21 Data Latency : 61.8ns
> U1-U23 Data Latency : 61.8ns
> U3-U5 Data Latency : 23.4ns
> U3-U7 Data Latency : 23.5ns
> U3-U9 Data Latency : 24.3ns
> U3-U11 Data Latency : 24.2ns
> U3-U13 Data Latency : 60.4ns
> U3-U15 Data Latency : 59.8ns
> U3-U17 Data Latency : 60.8ns
> U3-U19 Data Latency : 60.6ns
> U3-U21 Data Latency : 62.1ns
> U3-U23 Data Latency : 62.8ns
> U5-U7 Data Latency : 24.0ns
> U5-U9 Data Latency : 25.4ns
> U5-U11 Data Latency : 25.7ns
> U5-U13 Data Latency : 60.4ns
> U5-U15 Data Latency : 59.9ns
> U5-U17 Data Latency : 60.5ns
> U5-U19 Data Latency : 60.2ns
> U5-U21 Data Latency : 62.5ns
> U5-U23 Data Latency : 62.0ns
> U7-U9 Data Latency : 25.8ns
> U7-U11 Data Latency : 25.6ns
> U7-U13 Data Latency : 60.6ns
> U7-U15 Data Latency : 60.2ns
> U7-U17 Data Latency : 60.7ns
> U7-U19 Data Latency : 61.3ns
> U7-U21 Data Latency : 62.1ns
> U7-U23 Data Latency : 63.0ns
> U9-U11 Data Latency : 27.1ns
> U9-U13 Data Latency : 61.2ns
> U9-U15 Data Latency : 61.3ns
> U9-U17 Data Latency : 62.2ns
> U9-U19 Data Latency : 61.4ns
> U9-U21 Data Latency : 63.5ns
> U9-U23 Data Latency : 63.3ns
> U11-U13 Data Latency : 61.0ns
> U11-U15 Data Latency : 61.7ns
> U11-U17 Data Latency : 61.5ns
> U11-U19 Data Latency : 61.8ns
> U11-U21 Data Latency : 63.9ns
> U11-U23 Data Latency : 63.4ns
> U13-U15 Data Latency : 23.2ns
> U13-U17 Data Latency : 23.9ns
> U13-U19 Data Latency : 23.6ns
> U13-U21 Data Latency : 24.7ns
> U13-U23 Data Latency : 24.9ns
> U15-U17 Data Latency : 23.9ns
> U15-U19 Data Latency : 23.8ns
> U15-U21 Data Latency : 24.8ns
> U15-U23 Data Latency : 24.6ns
> U17-U19 Data Latency : 24.4ns
> U17-U21 Data Latency : 26.3ns
> U17-U23 Data Latency : 26.2ns
> U19-U21 Data Latency : 26.2ns
> U19-U23 Data Latency : 26.1ns
> U21-U23 Data Latency : 28.0ns
> 1x 64bytes Blocks Bandwidth : 14.88GB/s
> 4x 64bytes Blocks Bandwidth : 14.26GB/s
> 4x 256bytes Blocks Bandwidth : 74.7GB/s
> 4x 1kB Blocks Bandwidth : 230.23GB/s
> 4x 4kB Blocks Bandwidth : 344.82GB/s
> 16x 4kB Blocks Bandwidth : 452.25GB/s
> 4x 64kB Blocks Bandwidth : 636GB/s
> 16x 64kB Blocks Bandwidth : 502GB/s
> 8x 256kB Blocks Bandwidth : 499GB/s
> 4x 1MB Blocks Bandwidth : 504.56GB/s
> 8x 1MB Blocks Bandwidth : 40.51GB/s
> 8x 4MB Blocks Bandwidth : 18.7GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5900X 12-Core Processor (2M 12C 24T 4.92GHz, 1.9GHz IMC, 12x 512kB L2, 2x 32MB L3)
> Microcode : MUAF210009
> Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
> Platform Compliance : x64
> Buffer Memory Accesses : No
> No. Threads : 24
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5900X 12-Core Processor
> URL : https://www.amd.com
> Speed : 4.92GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.7GHz - 4.92GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 6 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : MUAF210009
> L1D (1st Level) Data Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 12x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 12x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


I compared my last two stable sets: Setup 1-1-1 vs. 51-0-0 and as we can see there is not much difference in the numbers:


Spoiler: comparison



Setup 1-1-1








Setup 51-0-0










I prefer the second one because it has a lower ProcODT, VDIMM.


----------



## DeletedMember558271

kompira said:


> I compared my last two stable sets: Setup 1-1-1 vs. 51-0-0 and as we can see there is not much difference in the numbers:
> 
> 
> Spoiler: comparison
> 
> 
> 
> Setup 1-1-1
> View attachment 2490308
> 
> Setup 51-0-0
> View attachment 2490309
> 
> 
> 
> I prefer the second one because it has a lower ProcODT, VDIMM.


Yea I was wondering if there's anything to be gained from this or if we should just go as low as we can, I've been running 52-0-0 for like 8 hours TM5 stable, seems fine


----------



## ManniX-ITA

Dreamic said:


> And I'm not saying 2ns is a world of difference either, but lower latency does help performance we can agree, and it helps more than extra cores a game isn't even going to use, depending on the game, which I'd say it's currently the exception that a game uses more than 8 cores, definitely not close to the norm yet, and probably won't be for years, at which point I'll probably just upgrade to something even better than what we all have now that has more cores when it's actually relevant for gaming.


They both don't make a world of difference, agree 
But there are very few games that can gain from better memory settings and it must be a difference in orders of magnitude, not just a few ms in latency.
While I have really a lot of games that can benefit from high threading; yes mostly are optimized up to 8 cores but if they find more there's always some gain.
Sometimes I open the task manager to see how the game is threading and I get a lot of nice surprises.
A lot of recent ports from consoles are happily using 12 threads.
But the game fps is usually limited by the 3-4 cores that are running the main threads and define the rendering pipeline.
That's why I try to optimize my OC for this kind of workload, pure ST and full MT is nice only for benchmark scores.
Having a lot of cores free makes gaming smoother, not only cause it's less likely some child thread is going to compete and slow down.
There's ample space for Windows to do its nasty unrequested and unwanted stuff in background.

I'm not sure SOTR is a good example to compare Low FPS between a 5800x and a 5950x.
Yes there have been a lot of improvements but there are many games more threaded than SOTR that should still show a substantial gain.
Still, doesn't make a world of difference...



mongoled said:


> lso those of you that are running "hacks" and not seeing any performance benefits from going to 1T 56-56-56, I think you peeps need to find a stable baseline with 2T without those hacks, then from that baseline switch to 1T 56-56-56 to see if you are still not getting any performance boosts.


It is definitely an issue with tCKE.
I'm testing with 20 iterations of AIDA latency.










Have to run many more but tCKE at 16 looks like a good start.
I was able to get a 54.3ns and many 54.4ns with CkeSetup at 18 but a second round proven it to be weaker than I hoped.
Then I started to record stuff.

CkeSetup at 12 seems promising, almost stable 54.5ns.
But looks like is impacting PBO boost more than the others.
Have to find a stable 54.4ns setting to be satisfied


----------



## lmfodor

ManniX-ITA said:


> They both don't make a world of difference, agree
> But there are very few games that can gain from better memory settings and it must be a difference in orders of magnitude, not just a few ms in latency.
> While I have really a lot of games that can benefit from high threading; yes mostly are optimized up to 8 cores but if they find more there's always some gain.
> Sometimes I open the task manager to see how the game is threading and I get a lot of nice surprises.
> A lot of recent ports from consoles are happily using 12 threads.
> But the game fps is usually limited by the 3-4 cores that are running the main threads and define the rendering pipeline.
> That's why I try to optimize my OC for this kind of workload, pure ST and full MT is nice only for benchmark scores.
> Having a lot of cores free makes gaming smoother, not only cause it's less likely some child thread is going to compete and slow down.
> There's ample space for Windows to do its nasty unrequested and unwanted stuff in background.
> 
> I'm not sure SOTR is a good example to compare Low FPS between a 5800x and a 5950x.
> Yes there have been a lot of improvements but there are many games more threaded than SOTR that should still show a substantial gain.
> Still, doesn't make a world of difference...
> 
> 
> 
> It is definitely an issue with tCKE.
> I'm testing with 20 iterations of AIDA latency.
> 
> View attachment 2490316
> 
> 
> Have to run many more but tCKE at 16 looks like a good start.
> I was able to get a 54.3ns and many 54.4ns with CkeSetup at 18 but a second round proven it to be weaker than I hoped.
> Then I started to record stuff.
> 
> CkeSetup at 12 seems promising, almost stable 54.5ns.
> But looks like is impacting PBO boost more than the others.
> Have to find a stable 54.4ns setting to be satisfied
> 
> View attachment 2490317


Hi Mannix! So CKEsetup 12 works better for you? I mean as the screenshot 56-0-12?

How it plays with the tCKE at 16? I’m a little confuse with the tCKE and the CADBUS Setup. Thanks!


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

lmfodor said:


> Hi Mannix! So CKEsetup 12 works better for you? I mean as the screenshot 56-0-12?
> 
> How it plays with the tCKE at 16? I’m a little confuse with the tCKE and the CADBUS Setup. Thanks!


tCKE at 16 and CkeSetup at 12 as in the screenshot.
So far it's the best with 54.5ns average.
But I'm convinced the profile can definitely do 54.4ns as average.
I think it's a matter of fine tuning.
I'm going to check tCKE 6 now.


----------



## Blameless

Does tCKE even do anything for a system that doesn't have power down enabled, doesn't get put into sleep/suspend, and isn't using SoC c-states?



Flash1228 said:


> Tried 1T 56-56-56 and I see no real difference between that and 2T.
> 
> View attachment 2490245


That's mostly what I'd expect to see from inserting a setup delay that's almost a full clock cycle long.


----------



## lmfodor

Blameless said:


> Does tCKE even do anything for a system that doesn't have power down enabled, doesn't get put into sleep/suspend, and isn't using SoC c-states?
> 
> That's mostly what I'd expect to see from inserting a setup delay that's almost a full clock cycle long.


This is one of my doubts, because it will be that by adding a delay of up to almost 1 clock cycle, we enable 1T with GDM off, which executes everything in one clock cycle and not in two like 2T. That is, it allows to enable the command rate by adding a dealy, it is correct? it´s a consusing


----------



## Veii

I'm gonna chees you a bit, but i figured the root cause of WHEA #19 
Let me finish testing , and see how to put phone ethernet sharing on my ProArt
Kind of wish now that my twitter wasn't suspended, as that would make big news for the tech reviewers

Eh whatever, today i'll push out the news and a tiny little review. Very happy with this board, having a great time with it
Sadly my experience with the Dark Hero was one of the least fulfullig one. Likely the WHEA hardware design issue

Which speaking of, unless i figure out the root flaw and fix it, there is no way to fix it, except to refund your board ~ of anyone who WHEA's at 1933Mhz or higher FCLK
Really sorry to say that, but for the next unannounced months, you are a lost cause 
Until later 🤗

Current ProArt is rock stable at 4000Mhz XMP 1:1
Same as 4200Mhz 1:1, with subtle dimm voltage increase to 1.4v
CPU VDDP = VDDP Standby Voltage. At 900mV its comfy

The ProArt is not "special" except that the whole AMD CBS is unlocked
Which is the way to go ASUS, fantastic job
But no, this should have been the user experience since the start
2100 FCLK can run perfectly with stock values on AGESA 1200 and higher on every board that doesnt have the HW issus
Neither ASRock nor ASUS are special here. Neither B550 nor X570 are special either

Edit:
Up till 2133 works well on auto predicted values
2167 is a hardwall for me. There my lottery luck ends
But 2000 FCLK again is runnable on every Vermeer chip
Higher is silicon lottery related


----------



## craxton

TimeDrapery said:


> **** all electricity too


**** the ******* charging my left nut on the electric bill i know that lol



Dreamic said:


> congratulated on OCN apparently


if anyone's to be congratulated, its not me bud. i agree with both, when you overclock
these chips those baseline factors go out the window. and i mean straight out the window.
if you can manage 4000mhz youll see what im saying, (cod cold war _zombies_) i gained 20 fps
just by tuning the ram... hard to believe but none the less when it wasnt crashing (due to the games coding)
i was seeing DRASTIC improvements. my link for those other chips is simply to show baseline.
not overclocking..



KedarWolf said:


> 56-56-56 change this part of your 1usmus_v3 .cfg to the below.


i IMMEDITLY see error 2 (had to switch cad_bus strengths back to x-20-20-20 which is what i had before
otherwise i seen error 1 straight out the gate. now within 5 min i see error 2.
im stable and happy at 2t gdm off. but like all others here, love to mess with whats not broken
to possibly achieve/experiment something better.


----------



## craxton

mongoled said:


> I really want the flat 14s. Its quite stupid really


this cant be done on 3200 c14 sticks???

i retract my question... not stress tested yet... nor have i tried 1t but none the less...


----------



## craxton

lmfodor said:


> No pls, tell me that I don´t need to change the processor. Do you mean that all of us who have WHEA errors are due to faulty processors? For me is something related to some parameter in BIOS or something not yet fixed. I hope so!


I'm not saying that at all, I'm saying that I've seen on other places where people was being ate alive upon 3200mhz etc ram of with WHEA out the roof. And they returned their chips to which, they had nomore WHEA errors.


----------



## lmfodor

Veii said:


> I'm gonna chees you a bit, but i figured the root cause of WHEA #19
> Let me finish testing , and see how to put phone ethernet sharing on my ProArt
> Kind of wish now that my twitter wasn't suspended, as that would make big news for the tech reviewers
> 
> Eh whatever, today i'll push out the news and a tiny little review. Very happy with this board, having a great time with it
> Sadly my experience with the Dark Hero was one of the least fulfullig one. Likely the WHEA hardware design issue
> 
> Which speaking of, unless i figure out the root flaw and fix it, there is no way to fix it, except to refund your board ~ of anyone who WHEA's at 1933Mhz or higher FCLK
> Really sorry to say that, but for the next unannounced months, you are a lost cause
> Until later [emoji847]
> 
> Current ProArt is rock stable at 4000Mhz XMP 1:1
> Same as 4200Mhz 1:1, with subtle dimm voltage increase to 1.4v
> CPU VDDP = VDDP Standby Voltage. At 900mV its comfy
> 
> The ProArt is not "special" except that the whole AMD CBS is unlocked
> Which is the way to go ASUS, fantastic job
> But no, this should have been the user experience since the start
> 2100 FCLK can run perfectly with stock values on AGESA 1200 and higher on every board that doesnt have the HW issus
> Neither ASRock nor ASUS are special here. Neither B550 nor X570 are special either
> 
> Edit:
> Up till 2133 works well on auto predicted values
> 2167 is a hardwall for me. There my lottery luck ends
> But 2000 FCLK again is runnable on every Vermeer chip
> Higher is silicon lottery related


Hi @Veii! You are a genius. Most of us thinking to RMA the processor and I don’t really want to
Yesterday I try with a little step up to 1933/3866 and even if I didn’t get any error in the 25 cycles of TM5 I got a lot or WHEA 19

I tried with your settings AER CAP & then ACS with it] ~ CBS->NBIO and also SRIS, but one of them I could find it in my asus BIOS. I think it was the AER CAP. AES and SRIR i could enable but it doesn’t stopped the WHEA

If it has to be with the mobo, I’m changing my Crosshair hero Wifi for an Unify-X. So you have bad experience with the dark? I supposed that it’s one of the best x570..

Looking forward for your great news [emoji3]


Sent from my iPhone using Tapatalk Pro


----------



## craxton

Veii said:


> I'm gonna chees you a bit, but i figured the root cause of WHEA #19
> Let me finish testing , and see how to put phone ethernet sharing on my ProArt
> Kind of wish now that my twitter wasn't suspended, as that would make big news for the tech reviewers
> 
> Eh whatever, today i'll push out the news and a tiny little review. Very happy with this board, having a great time with it
> Sadly my experience with the Dark Hero was one of the least fulfullig one. Likely the WHEA hardware design issue
> 
> Which speaking of, unless i figure out the root flaw and fix it, there is no way to fix it, except to refund your board ~ of anyone who WHEA's at 1933Mhz or higher FCLK
> Really sorry to say that, but for the next unannounced months, you are a lost cause
> Until later 🤗
> 
> Current ProArt is rock stable at 4000Mhz XMP 1:1
> Same as 4200Mhz 1:1, with subtle dimm voltage increase to 1.4v
> CPU VDDP = VDDP Standby Voltage. At 900mV its comfy
> 
> The ProArt is not "special" except that the whole AMD CBS is unlocked
> Which is the way to go ASUS, fantastic job
> But no, this should have been the user experience since the start
> 2100 FCLK can run perfectly with stock values on AGESA 1200 and higher on every board that doesnt have the HW issus
> Neither ASRock nor ASUS are special here. Neither B550 nor X570 are special either
> 
> Edit:
> Up till 2133 works well on auto predicted values
> 2167 is a hardwall for me. There my lottery luck ends
> But 2000 FCLK again is runnable on every Vermeer chip
> Higher is silicon lottery related


good god thats a nice lookin board.... to bad since posting this, all the 
(off known sellers upped their prices lol) 
will be looking into getting a new board, so that i have a second one in my stock as the rest are
sold to those in need.

so this board really should be named B550 WHEA FREE? 😀
thanks for sharing this, although im not needing away from whea just glad to see some 
insight on this. (thanks for sharing) adding to my cart now.


----------



## Veii

craxton said:


> good god thats a nice lookin board.... to bad since posting this, all the
> (off known sellers upped their prices lol)
> will be looking into getting a new board, so that i have a second one in my stock as the rest are
> sold to those in need.
> 
> so this board really should be named B550 WHEA FREE? 😀
> thanks for sharing this, although im not needing away from whea just glad to see some
> insight on this. (thanks for sharing) adding to my cart now.


The board makes a lot of fun, the led indicators are colour coded and noticable what error is what
The VRMs are really warm
It was around 60-70c while running y-cruncher 120A load. Felt that way, couldn't measure it. Hardwareluxx states 80c on a 5800X. Wouldn't run a 5950X on it
Dual intel 2.5gbit is useful and can be chained together as single 5gbit out
Coolers are a high quality, memory training is fine , CBS is fully opened so that's a big plus
I lack the dynamic OC feature but it has an own perf enhancer and the stilt's fmax enchance feature
Couldn't bypass yet the 120A fuse limit, but it has vcore and soc telemetry faking from 1000mA to 80 000mA.
BIOS is a bit sluggish but thats fine, its unlocked and this is all that matters
Usb 4.0 ports have no dropouts with my usb 3.0 mouse and focusrite usb 2.0 (switching issue on the ITX board)

It has a a WSON-8 chip and a new proprietary 14pin TPM header for SPI flash. Its not 9-0 anymore (10pin)
On the back are two tiny SOIC-8 romchips for both ethernet outs
M.2 Mount is screwless
No board led's except strip Aura Sync controll
My-Asus and Armoury Crate software are enabled by default but the option is easily visible to disable it before the first windows boot (soo noo .dll is injected into windows)
Turbo-Vcore works but the voltage access is little. Good enough its useful for CPU and RamOC

As for cpuOC again, the Mosfets are Weak and its a 4 phase board ~ but trippled
Switching freq moves between 150-350Khz, 5 loadlines and Asus Optomized+Manual Phase control mode
Current extenders go up till 140% but its just a bit underbuild with Vishay SIC 50A stages.
MemOC makes fun tho and should be just fine for a 5900X. 5950X needs heatsink modding or current limiting.
I would give it 210A max, 160A + 50A SOC & FCLK
=========================================
*Whea #19 is a hardware design issue, and has nothing to with the CPUs*
I'm sorry but everyone who has it, needs to refund their board ~ or wait 3+ months till PCB designers notice my post (later) and fix this
I am not capable to fix EFI modules and the chance to fix it is low.
It very likely needs a whole new revision of the affected boards | 40+ boards
And if it still is possible to rescue affected boards, it will take at absolute minimum 3+ months.
I expect half a year for it, till they rewrite and repair specific firmware parts of the board
Yet again, no guarantee as this is a design flaw 

While you wait or try:
AMD CBS - NBIO - SMU Common Options,
DPM LCLK has to be at 2-1-1-2-2-1-1-2 or 2-1-1-1-2-1-1-1 & DF-States as of 1200 & 1202 still need to be disabled
Thats it, best of luck that your board is not affected
2100 1:1:1 is able to run on stock predicted values @ 36.9ohm proc or lower
2000 FCLK has to work for everyone without touching anything !

If 1933 FCLK WHEA #19, then you are out of luck
WHEA #18 is CPU Vcore related and needs a tiny 10mV positive *vcore-offset* bump 

Full review of the board and explanation/thread about WHEA #19
Later today or at worst if memory missbehaves ~ tomorrow 👍

There are many board which are WHEA 19 free
But this is one of them, which doesn't have the design flaw
Although i really wish they would use a better PWM controller
Making it a 6+1 phase board / doubled
Instead a 4+4+4/+1+1 (12+2 tripled) board


----------



## Veii

lmfodor said:


> If it has to be with the mobo, I’m changing my Crosshair hero Wifi for an Unify-X. So you have bad experience with the dark? I supposed that it’s one of the best x570..


Unify Lineup is affected, same as the Dark Hero lineup
I think the Impact too, but i dont want to spill the beans yet
It deserves a proper post and not a phone writing with typos 

Also want to share proofing pictures and auto predicted voltage patterns
You dont need to touch much for 2100 1:1:1 to be stable on XMP 
(For example 19-19-19 XMP)
And dont need to touch anything for 2000 FCLK to be stable and WHEA free

I just got lucky with this board, being able to confirm my research
Every other unaffected board will behave the same after AGESA 1.2.0.0 and will not WHEA #19 fail
No exotic or specific settings needed, except enforce GMI/DPM link speeds | in-case the bios messes it up by wrong ACPI prediction/readout

This is how the release experience should have been
Sadly >80% of the 500 series boards, have an "unintentional" design flaw


----------



## ManniX-ITA

Veii said:


> If 1933 FCLK WHEA #19, then you are out of luck


Nooooo 
Waiting patiently updates...


----------



## domdtxdissar

Veii said:


> If 1933 FCLK WHEA #19, then you are out of luck
> WHEA #18 is CPU Vcore related and needs a tiny 10mV positive *vcore-offset* bump


I'm out of luck it seems 😂


----------



## Veii

ManniX-ITA said:


> Nooooo
> Waiting patiently updates...


I mean, you can ignore it
It will not affect the CPU performance, except continuously logged error's ~ soo contineous DPC calls on anything that has access to the CPUs cache
Soo pretty much every game and likely also audio work
I'm not sure how worse these DPC calls are when it comes to stutter, but if you can disable only this error, then go for it

As long as it passes several rounds of the y-cruncher FFT test
You are perfectly fine. Well and OCCT AVX2 Extreme Large Dataset
You can take 10cycles pure FFT only loop ~ as "good enough"
It mostly crashes when it warms up (3 single test loops = 9min)~ if SOC or VDDG are the issue why high FCLK doesnt work
But then, you really dont need to do ~anything~ to have 2000 1:1:1 rock stable on AGESA 1.2.0.0 (SMU 56.45+)
Not even 2100 1:1:1 ~ heh
The predictiond except for cLDO_VDDP are already solid, on this SMU and higher

My Frankenstein sample had 9 WHEA #18s at the very start on stock
10mV vcore bump fixed it, and since then there are neither warnings nor errors in the whole systemlog with 1000+ entries 
This board tracks 9 WHEA entries/categories, according to the guidance on Kernel-WHEA shared couple of pages ago

EDIT:
Oh WHEA #18 can alsol be CurveOptimizer related, but thats also just "a lack of vcore issue" 

@domdtxdissar its such a cooperate stupid business mistake
It's unbelievable, sadly i don't know if the affected boards can be fixed on firmware level, without a PCB redesign or by hand soldering


----------



## ManniX-ITA

Veii said:


> It's unbelievable, sadly i don't know if the affected boards can be fixed on firmware level, without a PCB redesign or by hand soldering


I should insulate for condensation the Unify-X but then there's no RMA...
Now I don't what to do


----------



## Kitsune2431

Veii said:


> This has to be coincidence
> When TM5 freezes, it means that one thread/worker crashed
> This means that one core/thread crashed
> 
> Doublecheck stability with y-cruncher (1/7/0) for 4 loops (54min , >3*18min) and if that passes, then something else happened
> Up to what system you run, and up to the bios - it could be either a WHEA triggered by Realtek NIC, or USB issues
> I remember MSI had 2-3 months ago SATA storage dropout issues too
> Around the debugging period of our USB issues
> Really depends what you run and what you have . It can be for example buggy AGESA 1.2.0.1 or strange 1202 with new RTT requirements and lower IOD requirements
> Depends


Hey. Update regarding my issue of tm5 stopping randomly on main windows and being fine on external windows. Turns out there were 2 issues.

First issue was just curve optimizer not being stable on full windows, so backing up curve solved it. Took a long time to solve it, because i drew a lot of wrong conclusions thanks to 2nd issue.

2nd issue is that it always crashes randomly if i turn off my monitor. That's what i always did on external windows and it was fine, but on main windows it always crashes. Tried upping voltages/turning off c states/positive curve/xmp/stock ram. Nothing helps. If i set turn off display after xx min in windows (which gives the same effect as turned off monitor), then it's fine, but monitor has to be turned on.

Any ideas on how to stabilize 2nd issue? I'm willing to do some more tests, but i guess i'll just ignore it since it also happens on stock.


----------



## KedarWolf

ManniX-ITA said:


> The G.Skill Ripjaws 3600C14 kit attempt failed as well...
> Different PCB, minus the LEDs, but they behave exactly the same as the 4000C16 kit.
> 
> Well, since I had to return them why not torturing a bit?
> 
> Let me present you the first, only, genuine, certified, true 1T profile for memory that needs setup timings to run at 1T (but without setup timings).
> This beast is highly un-optimized (no wonders) and marvelously inefficient.
> Of course can pass, whoop whoop, a full complete single cycle of TM5 1usmus.
> 
> View attachment 2490213
> View attachment 2490214
> 
> 
> Et voila, the latency is more or less the same as with setup timings and behave erratically in the same manner; from 54.5ns to 54.7ns with sporadic 54.9ns.
> 
> So the bad latency with these kits it's not due to the setup timings but cause they just can't run at 1T properly.
> 
> @Veii
> I'm thinking about the last PDF you kindly shared about memory latency.
> When it's talking about the gap in progress between bandwidth and latency.
> And he said that the manufacturers keeps improving bandwidth instead not because it's impossible but cause it's a matter of costs.
> Low latency memory is very expensive.
> 
> I have the feeling that Samsung is improving the profit and reducing the costs of B-die ICs.
> Which should have been End of Life since years but they keep being very remunerative...
> I bet the current production has been "nerfed" and only a few kits using old stocks can do properly 1T and low tRCDRD.


Someone in the Intel thread bought 16-16-16-36 4000 Royal RAM and it has the same production date, April 15th, 2021 as the CL16 Neo.

It performed much worse than the CL17 4000 RAM they already had.

I'm still going to try the CL16 4000 Neo though, I'll refund it if it's crap compared to my Cl16 3600 Neo I already own.


----------



## ManniX-ITA

KedarWolf said:


> I'm still going to try the CL16 4000 Neo though, I'll refund it if it's crap compared to my Cl16 3600 Neo I already own.


I think it's the way, lotto time... only a matter of luck.


----------



## ManniX-ITA

Kitsune2431 said:


> Any ideas on how to stabilize 2nd issue? I'm willing to do some more tests, but i guess i'll just ignore it since it also happens on stock.


Is the monitor connected via a DisplayPort cable?
If so, try to use an HDMI, could be the cable defective.


----------



## diggiddi

Teamgroup T-Force vulcan Z 64Gb(2x32) 16-18-18-38 micon( not sure the spec)
TeamGroup T-FORCE VULCAN Z 64GB (2 x 32GB) DDR4-3200 PC4-25600 CL16 Dual Channel Desktop Memory Kit - Gray - Micro Center 

These should be able to hit 3600 cl18 right? I'm trying to overclock in Ubuntu 20.04 what's the best and quickest way to go for a ryzen noob? thx


----------



## KedarWolf

diggiddi said:


> Teamgroup T-Force vulcan Z 64Gb(2x32) 16-18-18-38 micon( not sure the spec)
> TeamGroup T-FORCE VULCAN Z 64GB (2 x 32GB) DDR4-3200 PC4-25600 CL16 Dual Channel Desktop Memory Kit - Gray - Micro Center
> 
> These should be able to hit 3600 cl18 right? I'm trying to overclock in Ubuntu 20.04 what's the best and quickest way to go for a ryzen noob? thx


Check the b-die finder website. b-die 2x32GB surely the best way to go.


----------



## lmfodor

Veii said:


> Unify Lineup is affected, same as the Dark Hero lineup
> I think the Impact too, but i dont want to spill the beans yet
> It deserves a proper post and not a phone writing with typos
> 
> Also want to share proofing pictures and auto predicted voltage patterns
> You dont need to touch much for 2100 1:1:1 to be stable on XMP
> (For example 19-19-19 XMP)
> And dont need to touch anything for 2000 FCLK to be stable and WHEA free
> 
> I just got lucky with this board, being able to confirm my research
> Every other unaffected board will behave the same after AGESA 1.2.0.0 and will not WHEA #19 fail
> No exotic or specific settings needed, except enforce GMI/DPM link speeds | in-case the bios messes it up by wrong ACPI prediction/readout
> 
> This is how the release experience should have been
> Sadly >80% of the 500 series boards, have an "unintentional" design flaw


Wow, can’t believe it! All mothebosrds design? Where I can disable specific DF-States, I only have on option … I have WHEA 19 without touching DPM or DF, should I try or if WHEA 19 appear in 1933 I’m part or the bad batch? It is better to downgrade to SMU 55.4x? Or with the last version and the DPM and DF states should work?

These are the DF options …










Sent from my iPhone using Tapatalk Pro


----------



## DeletedMember558271

Veii said:


> While you wait or try:
> AMD CBS - NBIO - SMU Common Options,
> *DPM LCLK has to be at 2-1-1-2-2-1-1-2 or 2-1-1-1-2-1-1-1* & DF-States as of 1200 & 1202 still need to be disabled
> Thats it, best of luck that your board is not affected
> 2100 1:1:1 is able to run on stock predicted values @ 36.9ohm proc or lower
> 2000 FCLK has to work for everyone without touching anything !
> 
> If 1933 FCLK WHEA #19, then you are out of luck


Of course my B550 Tomahawk doesn't have the option to set DPM LCLK like this, not that it would probably even matter, if I got an unlocked BIOS or something with the option.
You or someone should maybe make a Google Sheet or something of like verified/confirmed WHEA-free boards to buy, would definitely be useful information.
This is all so stupid, and still doesn't explain the 1900 FCLK issue either does it? I actually don't remember if I've only seen people with WHEA have the 1900 FCLK issue, or if there are people who are WHEA-free 1933+ who still can't post 1900 specifically, if these are somehow related. I'm still just curious why 1900 is cursed, if that's a CPU issue or also part of this board problem. Just a weird little anomaly


----------



## danakin

Dreamic said:


> Of course my B550 Tomahawk doesn't have the option to set DPM LCLK like this, not that it would probably even matter, if I got an unlocked BIOS or something with the option.
> You or someone should maybe make a Google Sheet or something of like verified/confirmed WHEA-free boards to buy, would definitely be useful information.
> This is all so stupid, and still doesn't explain the 1900 FCLK issue either does it? I actually don't remember if I've only seen people with WHEA have the 1900 FCLK issue, or if there are people who are WHEA-free 1933+ who still can't post 1900 specifically, if these are somehow related. I'm still just curious why 1900 is cursed, if that's a CPU issue or also part of this board problem. Just a weird little anomaly


well i got my 5950x/unify x570 for arround 2 weeks now. i sent my first 5950x back and ordered another one. the first cpu couldnt post 1900 fclk and also had whea errors at 1933+.

the second cpu can post 1900fclk but got the same whea errors at 1933 and above.

i think the 1900 fclk no post thing is cpu related.


----------



## DeletedMember558271

danakin said:


> well i got my 5950x/unify x570 for arround 2 weeks now. i sent my first 5950x back and ordered another one. the first cpu couldnt post 1900 fclk and also had whea errors at 1933+.
> 
> the second cpu can post 1900fclk but got the same whea errors at 1933 and above.
> 
> i think the 1900 fclk no post thing is cpu related.


That's so weird, but apparently if your board was fine that old 5950x that couldn't 1900 would be fine and WHEA-free 1933+.
Just doesn't make sense to me, why some CPU's hate 1900 specifically but will be fine at like 2000 or more still.
Bugged CPU's, bugged motherboards...


----------



## diggiddi

KedarWolf said:


> Check the b-die finder website. b-die 2x32GB surely the best way to go.


 I already have this set and was wondering how to overclock it


----------



## Kitsune2431

ManniX-ITA said:


> Is the monitor connected via a DisplayPort cable?
> If so, try to use an HDMI, could be the cable defective.


Yes, it's DP, but external windows is fine with turned off monitor, so pretty sure cable should be fine. Don't have any HDMI cable lying around, so not gonna buy one, since i only turn off monitor while stress testing.


----------



## ManniX-ITA

Kitsune2431 said:


> Yes, it's DP, but external windows is fine with turned off monitor, so pretty sure cable should be fine. Don't have any HDMI cable lying around, so not gonna buy one, since i only turn off monitor while stress testing.


Just be careful, if the cable is not certified and is doing weird things could have a manufacturing defect (extremely frequent) that can create this and more obscure issues till killing parts or the whole PC.
Certification detects it immediately but most of the cables aren't and most of the big brands they sell cheap stuff.


Spoiler: DP Cable 





__
https://www.reddit.com/r/buildapc/comments/agcv46


----------



## Blameless

Too much B-die in this thread, so here is some cheap ($124 for the 2x16GiB kit when I bought it about six months ago) Hynix CJR:










Not safe mode, TM5 stable, 1.29 vDIMM. Was in my 3900X setup until last week, still tuning it on the 5800X.



Veii said:


> DPM LCLK has to be at 2-1-1-2-2-1-1-2 or 2-1-1-1-2-1-1-1 & DF-States as of 1200 & 1202 still need to be disabled
> Thats it, best of luck that your board is not affected


Interesting. Have always disabled DF C-states, given the negligible impact on power/heat, but haven't messed with DPM LCLK yet. Will have to see see if that lets me get over 1900FCLK error free.


----------



## craxton

Veii said:


> While you wait or try:
> AMD CBS - NBIO - SMU Common Options,
> DPM LCLK has to be at 2-1-1-2-2-1-1-2 or 2-1-1-1-2-1-1-1 & DF-States as of 1200 & 1202 still need to be disabled


this isnt something ive seen inside MSI bios, unless its with the newest SMU? as im still on agesa 1.2.0.1 as .0.2 wouldnt post 
with my stable config so i didnt even bother..



Veii said:


> The board makes a lot of fun, the led indicators are colour coded and noticable what error is what


thats something i believe ALL BOARDS with EZ DEBUG led should do... most the time 
cant even tell without a flashlight unless one knows the order anyhow.



Veii said:


> The VRMs are really warm
> It was around 60-70c while running y-cruncher 120A load. Felt that way, couldn't measure it.


a 200$ board for a 600chip is not so common i do believe...unless it is lol, then again, 2000$ gpus are a thing it would seem now days



Veii said:


> CBS is fully opened so that's a big plus


if only MSI could do this instead of claiming its only gonna help APU's 


Veii said:


> it has vcore and soc telemetry faking from 1000mA to 80 000mA.


still something i personally have yet to experiment with, but it is unlocked inside the bios 
unsure how well it works on my particular board.



Veii said:


> BIOS is a bit sluggish but thats fine,


Again, MSI being a cuplrit this bios is as well, a little sluggish (at times) 



Veii said:


> Switching freq moves between 150-350Khz, 5 loadlines and Asus Optomized+Manual Phase control mode
> Current extenders go up till 140% but its just a bit underbuild with Vishay SIC 50A stages.
> MemOC makes fun tho and should be just fine for a 5900X. 5950X needs heatsink modding or current limiting.


all these settings would perhaps make it easier to overclock in general, but none the less STILL FIGHTING MSI 
to unlock CPU VDDP....it hasnt been said time limit yet the closed BOTH my tickets for the emails ive sent both with the same 
responses...
perhaps ASUS would simply be the (fix for all) at this point... but i myself have only used MSI bios
(minues HP having used a few prebuilts to which, i figured out how to unlock advanced features that werent visible otherwise.)

if, i snag this board and hit checkout ill probably become headless as my ol lady despises computers since i 
began chasing that dragon...(NO NOT MSI's dragon) that overclock dragon..might just well enough be worth it.


----------



## Kitsune2431

ManniX-ITA said:


> Just be careful, if the cable is not certified and is doing weird things could have a manufacturing defect (extremely frequent) that can create this and more obscure issues till killing parts or the whole PC.
> Certification detects it immediately but most of the cables aren't and most of the big brands they sell cheap stuff.
> 
> 
> Spoiler: DP Cable
> 
> 
> 
> 
> 
> __
> https://www.reddit.com/r/buildapc/comments/agcv46


Huh, i'll think about new cable then.


----------



## DeletedMember558271

craxton said:


> this isnt something ive seen inside MSI bios, unless its with the newest SMU? as im still on agesa 1.2.0.1 as .0.2 wouldnt post


Yea it's not in the latest BIOS for my MSI B550 Tomahawk, 1.2.0.2, 56.50.0


----------



## craxton

diggiddi said:


> These should be able to hit 3600 cl18 right?


i can tell you what set WILL post 3800 C14.... if you care to spend a little on them like 90-120 per 16gb SR kit
which im running two sets as they come in sets of two running 4000 myself stable c16 flat 2T tho.



Dreamic said:


> who still can't post 1900 specifically


i have no issues posting all the way from one step above 4000mhz all the way down to 3200mhz tied.
unsure about stability etc as i mentioned earlier, ive ran 4000mhz straight OFF THE RIP...day 0 of initial install.



Dreamic said:


> Yea it's not in the latest BIOS for my MSI B550 Tomahawk, 1.2.0.2, 56.50.0


i do know there is something about FCLK or LCLK or something like that in 1.2.0.2 either
inside AMD section thru advanced sub menu, or CBS i cant recall...almost will to update to test as i 
still have 1.2.0.1 downloaded since its been removed from the download page by MSI for whatever reason....


----------



## craxton

Blameless said:


> Hynix CJR:


Team has a CJR kit 3800 or 3600mhz tforce darkZa i cant recall if its 36 or 3800mhz
and they have the WAY more expensive 4000mhz C/DJR kit as well. but they tighten up pretty nice.

i sold all 4 sticks of the 4000mhz i had to recoup some cost on the B-DIE i have now....also from team lol


----------



## DeletedMember558271

craxton said:


> i do know there is something about FCLK or LCLK or something like that in 1.2.0.2 either
> inside AMD section thru advanced sub menu, or CBS i cant recall...almost will to update to test as i
> still have 1.2.0.1 downloaded since its been removed from the download page by MSI for whatever reason....


Yea there's just this, someone elses image


----------



## Blameless

craxton said:


> Team has a CJR kit 3800 or 3600mhz tforce darkZa i cant recall if its 36 or 3800mhz
> and they have the WAY more expensive 4000mhz C/DJR kit as well. but they tighten up pretty nice.
> 
> i sold all 4 sticks of the 4000mhz i had to recoup some cost on the B-DIE i have now....also from team lol


This Timetec stuff has primaries that do not tighten well at all, but it scales well in frequency with relatively low voltage, and the subtimings tighten fine.

No heatspreaders either, which I consider a plus (if I need more cooling, I can add more functional ones than any OEM would include for ~20 bucks).

Might have to check out what other options there are currently, but at this point I'm mostly done acquiring DDR4. Need to save some money for a DDR5 platform.


----------



## jomama22

craxton said:


> i can tell you what set WILL post 3800 C14.... if you care to spend a little on them like 90-120 per 16gb SR kit
> which im running two sets as they come in sets of two running 4000 myself stable c16 flat 2T tho.
> 
> 
> i have no issues posting all the way from one step above 4000mhz all the way down to 3200mhz tied.
> unsure about stability etc as i mentioned earlier, ive ran 4000mhz straight OFF THE RIP...day 0 of initial install.
> 
> 
> i do know there is something about FCLK or LCLK or something like that in 1.2.0.2 either
> inside AMD section thru advanced sub menu, or CBS i cant recall...almost will to update to test as i
> still have 1.2.0.1 downloaded since its been removed from the download page by MSI for whatever reason....


What I do find interesting is that most boards that people can get 4000 to work with whea are on the lowe-end/mid-teir end of the spectrum. Nothing to do with quality or w.e. but my guess would be that they lack a lot of the extra components (USB chips, networking chips, etc.) The higher end boards add on as frills. 

Just speculation fueled by vaii's comments. 

The only this I will say is that I haven't seen anyone with a chip who can hit 4000 whea-free throw it into a board and not be able to hit it. So it does still leave open the possibility that it's not only a board issue.


----------



## Pegasuss

For those that tried to run 2x16 dual rank 3800cl14 with tRCDRD 14, do you remember what type of errors you get on TM5?


----------



## TimeDrapery

Here's where I've ended up so far... Currently Karhu ... ing 😁😁😁😁😁


















































Veii said:


> Spoiler
> 
> 
> 
> While you wait or try:
> AMD CBS - NBIO - SMU Common Options,
> DPM LCLK has to be at 2-1-1-2-2-1-1-2 or 2-1-1-1-2-1-1-1 & DF-States as of 1200 & 1202 still need to be disabled


@Veii








This is a pretty cool idea regardless of PCI-E GEN 3/4 or BAR/SAM being available/disabled/enabled... What positive impact(s) have you witnessed when configured as you described? What negative impact(s)? Thanks so much for sharing with us all... Again 😁😁😁😁😁


----------



## ManniX-ITA

Pegasuss said:


> For those that tried to run 2x16 dual rank 3800cl14 with tRCDRD 14, do you remember what type of errors you get on TM5?


Almost everything at some point but with a preference of 0,6,4 and, same when trying to stabilize tRCDRD 15, the 2,10


----------



## Blameless

Adjusting the SMU DPM settings significantly reduced the rate of WHEA #19 errors past 1900 FCLK, but didn't eliminate them, and didn't make FCLK 1966 or higher any more usable. It almost, in conjunction with a bit of vSoC tuning, made 1933 viable on my ASRock B550 Phantom Gaming-ITX/AX setup, but there were still a few errors.

I can still POST at 2033 FCLK, but 1966 and 2000 are super flaky no matter what I do and constantly produce error 19s while dropping USB devices at random.



jomama22 said:


> What I do find interesting is that most boards that people can get 4000 to work with whea are on the lowe-end/mid-teir end of the spectrum. Nothing to do with quality or w.e. but my guess would be that they lack a lot of the extra components (USB chips, networking chips, etc.) The higher end boards add on as frills.


I'm sure there is a board/FW component to the FLCK issue, but I'm not convinced most 5000 series CPUs will do 2000, even in an ideal board. The SMU and fabric hardware don't leave the CPU package on AM4 setups. 

The DPM tweak having an effect makes sense, as that controls the frequency of the control fabric the SMU uses to poll and manage the CCDs and IOD, but barring firmware or power delivery issues, it doesn't make a whole lot of sense for FCLK potential to be determined by the board or the fluff on it.


----------



## Pegasuss

ManniX-ITA said:


> Almost everything at some point but with a preference of 0,6,4 and, same when trying to stabilize tRCDRD 15, the 2,10


I only get errors on test 10, I'm guessing there's nothing I can do about that?

Also, do you happen to know if its better to have tCWL at 14 with tRDWR 8 and tWRRD 3 than tCWL 12 with tRDWR 10, tWRRD 1? Just wondering because, I am seeing people with both setups but it probably does not make a difference?


----------



## ManniX-ITA

Pegasuss said:


> I only get errors on test 10, I'm guessing there's nothing I can do about that?
> 
> Also, do you happen to know if its better to have tCWL at 14 with tRDWR 8 and tWRRD 3 than tCWL 12 with tRDWR 10, tWRRD 1? Just wondering because, I am seeing people with both setups but it probably does not make a difference?


Well if you only get error #10 you can try to fix it.
But last time I gave up as the price of fixing tRCDRD 15 was higher than keeping it at 16.

It does make a difference but I'm not sure which one is better.
10/1 allows SCL at 2 but is worse than SCL 4 on read bandwidth.
I usually try some combinations to see what works and how it changes.
Very often there's no choice.


----------



## TimeDrapery

Pegasuss said:


> Spoiler
> 
> 
> 
> I only get errors on test 10, I'm guessing there's nothing I can do about that?
> 
> Also, do you happen to know if its better to have tCWL at 14 with tRDWR 8 and tWRRD 3 than tCWL 12 with tRDWR 10, tWRRD 1? Just wondering because, I am seeing people with both setups but it probably does not make a difference?


@Pegasuss 

My board autos tRDWR to 9 and tWRRD to 2 with tCL 14 and tCWL 12

I remember somewhere it says...

_tCWL_ - _tCL_ + _tRDWR_ ≤ 8

I imagine it will work for you too


----------



## KedarWolf

G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4000 (PC4 32000) Desktop Memory Model F4-4000C16D-32GTZNA - Newegg.com


Buy G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4000 (PC4 32000) Desktop Memory Model F4-4000C16D-32GTZNA with fast shipping and top-rated customer service. Once you know, you Newegg!




www.newegg.com






DDR4 4000 (PC4 32000)
Timing 16-16-16-36
CAS Latency 16
Voltage 1.40V


Just bought this and only $2.01 more for rush shipping. 

From newegg.ca though, but I link .com for you peeps as not too many of us are from Kanuckistan.


----------



## mongoled

For the record, tested several 5600x CPUs and all of them had different max post FCLK and different FCLK "holes"

The modified BIOSs we are using, although they unhide the features, are those features actually applied when we set them ???

I have tried the settings that are available in Eder modified A85 BIOS for the X570 Unify, they made no difference to how FCLK is acting.

In the past I have also tried disabling all peripherals in BIOS that could be disabled such as LAN, wLAN, Audio etc etc as well as droppig PCIe to 2x etc etc, non of these made any changes to WHEA 19 warnings


----------



## lmfodor

Hi @ManniX-ITA ,


ManniX-ITA said:


> They both don't make a world of difference, agree
> But there are very few games that can gain from better memory settings and it must be a difference in orders of magnitude, not just a few ms in latency.
> While I have really a lot of games that can benefit from high threading; yes mostly are optimized up to 8 cores but if they find more there's always some gain.
> Sometimes I open the task manager to see how the game is threading and I get a lot of nice surprises.
> A lot of recent ports from consoles are happily using 12 threads.
> But the game fps is usually limited by the 3-4 cores that are running the main threads and define the rendering pipeline.
> That's why I try to optimize my OC for this kind of workload, pure ST and full MT is nice only for benchmark scores.
> Having a lot of cores free makes gaming smoother, not only cause it's less likely some child thread is going to compete and slow down.
> There's ample space for Windows to do its nasty unrequested and unwanted stuff in background.
> 
> I'm not sure SOTR is a good example to compare Low FPS between a 5800x and a 5950x.
> Yes there have been a lot of improvements but there are many games more threaded than SOTR that should still show a substantial gain.
> Still, doesn't make a world of difference...
> 
> 
> 
> It is definitely an issue with tCKE.
> I'm testing with 20 iterations of AIDA latency.
> 
> View attachment 2490316
> 
> 
> Have to run many more but tCKE at 16 looks like a good start.
> I was able to get a 54.3ns and many 54.4ns with CkeSetup at 18 but a second round proven it to be weaker than I hoped.
> Then I started to record stuff.
> 
> CkeSetup at 12 seems promising, almost stable 54.5ns.
> But looks like is impacting PBO boost more than the others.
> Have to find a stable 54.4ns setting to be satisfied
> 
> View attachment 2490317


How did you test so many tCKE values in the spreadsheet? What tool are you using? Maybe I should work with some Software that modifify the BIOS instead of rebooting and enter in the BIOS setup. I tried with the AsRock and event with the Asus V


Veii said:


> The board makes a lot of fun, the led indicators are colour coded and noticable what error is what
> The VRMs are really warm
> It was around 60-70c while running y-cruncher 120A load. Felt that way, couldn't measure it. Hardwareluxx states 80c on a 5800X. Wouldn't run a 5950X on it
> Dual intel 2.5gbit is useful and can be chained together as single 5gbit out
> Coolers are a high quality, memory training is fine , CBS is fully opened so that's a big plus
> I lack the dynamic OC feature but it has an own perf enhancer and the stilt's fmax enchance feature
> Couldn't bypass yet the 120A fuse limit, but it has vcore and soc telemetry faking from 1000mA to 80 000mA.
> BIOS is a bit sluggish but thats fine, its unlocked and this is all that matters
> Usb 4.0 ports have no dropouts with my usb 3.0 mouse and focusrite usb 2.0 (switching issue on the ITX board)
> 
> It has a a WSON-8 chip and a new proprietary 14pin TPM header for SPI flash. Its not 9-0 anymore (10pin)
> On the back are two tiny SOIC-8 romchips for both ethernet outs
> M.2 Mount is screwless
> No board led's except strip Aura Sync controll
> My-Asus and Armoury Crate software are enabled by default but the option is easily visible to disable it before the first windows boot (soo noo .dll is injected into windows)
> Turbo-Vcore works but the voltage access is little. Good enough its useful for CPU and RamOC
> 
> As for cpuOC again, the Mosfets are Weak and its a 4 phase board ~ but trippled
> Switching freq moves between 150-350Khz, 5 loadlines and Asus Optomized+Manual Phase control mode
> Current extenders go up till 140% but its just a bit underbuild with Vishay SIC 50A stages.
> MemOC makes fun tho and should be just fine for a 5900X. 5950X needs heatsink modding or current limiting.
> I would give it 210A max, 160A + 50A SOC & FCLK
> =========================================
> *Whea #19 is a hardware design issue, and has nothing to with the CPUs*
> I'm sorry but everyone who has it, needs to refund their board ~ or wait 3+ months till PCB designers notice my post (later) and fix this
> I am not capable to fix EFI modules and the chance to fix it is low.
> It very likely needs a whole new revision of the affected boards | 40+ boards
> And if it still is possible to rescue affected boards, it will take at absolute minimum 3+ months.
> I expect half a year for it, till they rewrite and repair specific firmware parts of the board
> Yet again, no guarantee as this is a design flaw
> 
> While you wait or try:
> AMD CBS - NBIO - SMU Common Options,
> DPM LCLK has to be at 2-1-1-2-2-1-1-2 or 2-1-1-1-2-1-1-1 & DF-States as of 1200 & 1202 still need to be disabled
> Thats it, best of luck that your board is not affected
> 2100 1:1:1 is able to run on stock predicted values @ 36.9ohm proc or lower
> 2000 FCLK has to work for everyone without touching anything !
> 
> If 1933 FCLK WHEA #19, then you are out of luck
> WHEA #18 is CPU Vcore related and needs a tiny 10mV positive *vcore-offset* bump
> 
> Full review of the board and explanation/thread about WHEA #19
> Later today or at worst if memory missbehaves ~ tomorrow 👍
> 
> There are many board which are WHEA 19 free
> But this is one of them, which doesn't have the design flaw
> Although i really wish they would use a better PWM controller
> Making it a 6+1 phase board / doubled
> Instead a 4+4+4/+1+1 (12+2 tripled) board


Hi Veii, first of all I tried everything, DPM with your values 2-1-1-1-2-1-1-1 or 2-1-1-2-2-1-1-2 but it didn't work. Probe with DPM LCLK Enabled, there were two DPM options and I enabled them. Then I tried matching with the vSOC values. I think I should try lowering the LLC for a lower SOC amperage. But I had no luck, any combination with 1933 gives me an exaggerated amount of WHEA 19, so I am not among the lucky ones.

Now, rethinking what you said that the error is in the motherboards and that maybe they even have to make modifications in the circuits, and that almost all motherboards are bad, I think, all these motherboards came out before the 5000 series, so, AMD When launching this last line I announced the compatibility updating the firmware, but, then it is not the motherboards, or I mean, they were never prepared to support the high performance that the new line, so, or the firmware could fix the IF problem, or they should release new motherboards that effectively support what was announced by AMD in 2020. That will surely come out when they launch the new Rayzen 5000 "NextGen" It seems to me that this is where the problem comes from, let's say that admitting this it doesn't sell too much, better to say that 4000MHz is recommended and good, if it works better else try with Windows 1909 and there is no more WHEA .. Sorry for being simplistic. I had to repair server circuits that back in the late 90's cost 150k usd, yes, I worked on the old Compaq with the famous Proliant, and lived everything with motherboards and those pentiums from the first generations, but never on a large scale like this, they were specific corrections that Compaq and Intel engineers sent us via VHS, yes, VHS !! But this seems to me that it is an inconsistency of the processors with the mobos, and hopefully, let's continue waiting for the AMD engineers to achieve the long-awaited firmware, but the wait is long and if we continue arguing that the USB does not work, that is clearly by some communication channel of the famous IF, then how do we pretend that the memories work WHEA free knowing that error 19 is from I/O. Let's say that we are looking for high performance almost as a hobby, already in the values that we have , we are playing in the first leagues.

Well, it seems I'm not gonna buy the Unify X, in fact I have a B550 ASRock Phantom Gaiming, with a 3700x that I used just one month. Perhaps I should try with this board.. maybe it works better that the CH8 Wifi with so many stuff. I'm going to rest a bit so I stop the frustration of continuing to try WHEA free .. at least I have the battle to lower the blessed tRCDRD without the burst of errors 6 and the PCB Crash .. I will find a way at least for those errors 6 .or change this Kit for the 3600CL16 4x8 that work much better than these.


----------



## lmfodor

ManniX-ITA said:


> Have to run many more but tCKE at 16 looks like a good start.
> I was able to get a 54.3ns and many 54.4ns with CkeSetup at 18 but a second round proven it to be weaker than I hoped.
> Then I started to record stuff.
> 
> CkeSetup at 12 seems promising, almost stable 54.5ns.
> But looks like is impacting PBO boost more than the others.
> Have to find a stable 54.4ns setting to be satisfied


Hi @ManniX-ITA , Help me with a piece of information, how do you do these tests? Do you modify the values from Windows with some BIOS software, or do you reboot and record the values? I would love to try this just like you do. In fact I am looking for some software that modifies the BIOS values from Windows, the ones I tested did not work for me. I know there is one from ASRock and another old one from Asus 

Thanks!


----------



## ManniX-ITA

lmfodor said:


> Hi @ManniX-ITA , Help me with a piece of information, how do you do these tests? Do you modify the values from Windows with some BIOS software, or do you reboot and record the values? I would love to try this just like you do. In fact I am looking for some software that modifies the BIOS values from Windows, the ones I tested did not work for me. I know there is one from ASRock and another old one from Asus


Change in BIOS and boot every time in Windows...
I wouldn't trust a memory setting change via Windows.


----------



## lmfodor

ManniX-ITA said:


> Change in BIOS and boot every time in Windows...
> I wouldn't trust a memory setting change via Windows.


Hi Mannix!

And how did you finish with the latency tests? 56-0-12 and tCKE 16 seem to be the most stable, right? I am adjusting my voltage values. Everything contrasted with the above, with everything adjusted as you can see in my timings - less tRCDRD - that it is in 16, I am in 1.48V of VDIMM, 1.1 of vSOC, and the other values in relation. Then ProcODT low for a better signal, Cadbus 40-20-20-20 and tCKE 1 .. the latency varies a lot, but I'm going to run the test alone and do the same exercise to see how it works. I'm still amazed by the voltage values. everyone recommended me to go up to 1.55 easy and I'm at 1.48 .. passing all the y-cruncher tests, OCCT Extreme Large all SSR, AVX and AVX2 and TM5 almost for a day. more nights of HCI memtest .. 

I think that if we can lower the tRCDRD looking for some way to avoid the PCB Crash (errors 6, 12, 0), we can lower it and increase the bandwidth It's steadfast, but at 15 I got a much better reading so at 14 it should be much better. But precisely the alignment of the VDIMM and vSOC + the ProcODT and the RTTs are the key. There must be some calculation of voltages and impedances, I say, it is the least developed, but RQZ 240 + ProcODT + cadbus all in ohms against the current, VSOC and VDIMM should line up. I didn't find much of this. Always only from timings. but little related to voltages and resistances


Sent from my iPhone using Tapatalk Pro


----------



## PJVol

Veii said:


> DPM LCLK has to be at 2-1-1-2-2-1-1-2 or 2-1-1-1-2-1-1-1 & DF-States as of 1200 & 1202 still need to be disabled


Hey!
Tried it just for curiosity's sake...
...so they literally do nothing on my board/cpu, and according to metrics, LCLK3 max freq. always stays at 592Mhz and LCLK3 eff. freq. dropped as low as ~290 in idle, regardless of CBS settings including DF C-states and APB (though couple of ~ weeks ago had seen both lclk's at 302Mhz) - tested with GPU-Z built-in render test, which stresses PCIe. And IIRC LCLK not much dependent on DF power saving, being separate clock domain, though not sure, may be wrong here.
Anyway, I personally still I think that WHEA 19 issue is on both sides, cpu and mb, so I'm really looking forward to your story 

The only thing I can't understand is what all this fuss about these WHEA per se. Whoever I ask what impact they have on performance or stability, I still can't get a definitive answer.
I admit if it would be a case like mine, when performance degrades unless bruteforced with VDD18, then its clearly dissapointment, given that max. allowed vdd18 on my board - 2.1V - barely enough to stabilize 2033-2066 max.
IDK, what people are complain about


----------



## RonLazer

It's a good point, I think people worry about WHEAs because it's a sign that the hardware is unhappy, but if they are infrequent enough that they don't degrade performance then really they're just a feature of the data-fabric error-correction mechanism working as intended. Provided the voltages used to run the infinity fabric at that speed aren't excessive then there's no risk of damage. The GloFo 12nm process is typically more sensitive to voltage than current, not that 1900MHz vs 2000MHz is a significant amount of extra current anyway.


----------



## Dar|{cyde

I'm starting to think I'll just ignore WHEA 19's. If my rig can pass MT5, y-cruncher, p95, and OCCT, what do I care if it puts _warnings_ in the event log? Honestly I haven't found that stability point yet... but I'm probably just pushing the timings too hard.


----------



## craxton

question for anyone that can answer,

ive ran TM5 25 cycles for over 10 hours now, but its still not finished and
its not using any ram at all on my system at this time...

is it possible to be bugged due to hibernating last night?????
been on cycle 24 since 8 hour mark...


----------



## Veii

@PJVol like you mentioned the readouts are correct
The reason for setting DPM LCLK state not PCIe one is only to enforce AMDs default behavior
At least how it should behave
LV3 since dLDO injection "unlock" should stay at 600mhz, not at 300
It was 2-1-1-1 bellow 1200 and probably SMU 56.44 is a middle step, as it was also used on 1191 and 1180/1181
SMU 56.45 should have been the standard 1.2.0.0 although its arguable if its 1200A(AB) or 1201
SMU 56.50 is 1202 but not every board has a pure 1202, some again are 1200++ or 1201A
Depending on the applied state of usb fix patch
(Which created the issued for me on the ITX between Type C and USB 3.0)
And some have the IMC FW rewrite on 56.45 others like on asrock only got everything new on 1202
Although i can say that 1201 behaved abnormal when it comes to my timings

Ignoring now the changes which first gen and 2nd gen users see

The WHEA #19 issue relates to a chip on the boards, a component handled by the chipset
And communication towards the chipset from the I/O die is an issue
It belongs to the usb issues, but they are an endproduct or "sideeffect" of the issue
EDIT:
Same as unstable PCIe 4.0 on FCLK @ and beyond 2000Mhz, is an "sideeffect" of the issue
I continue to drive the route that every Vermeer chip can reach 2000 FCLK ~ IF PCIe 4.0 doesn't dropout till then, but 1967 is 110% possible

The reason why 1909 behaves probably better ~ although no changes for unaffected boards up to 21H2
Is that the driver loaded with the numerous patches that where tried to be applied publicly and in the hidden between couple board manufactures
I suspect that every board manufacture "now" knows the issue, but either because of
A.) Brand Ashaming (semiconductor ?)
B.) NDA with the faith to resolve it in 3+ months
remains silent.
Maybe X570S will ring a bell too 

One of both, but i suspect the problem maker enforced an NDA in exchange to potentially fix the issue and rewrite the FW ~ soo they wont lose margin because of the refunds, when the issue is public
As, as stupid as it sounds, neither of the board partners can much against the FW issue ~ when they followed their schematics accurately

Maybe at this point of the story, the issue rings to someone who followed it couple of bios revisions ago
I think I can talk about it, but its not something that will be liked ~ being heard
And also because i respect the semiconductors work (except this nonsense here) , i need to be cautious how i form words not to brand shame them

Overall, it is an IO issue
DPM advice above was to fix something that is inconsistent and can be part of the communication problem with the IO-Die to the chipset

I want to re-mention that the chipset does not matter here nor the series
(if 300 series would have support and didn't use this semiconductor part ~ they also would be WHEA 19 free)
I think (again), affected users can ignore this error fully
But it will cause continuous DPC calls, soo unless logging can be disabled for this specific issue ~ it will oppose a performance and latency penalty & variation

Sadly disabling all IO does not resolve the issue
Maybe erasing the module from the bios could be a fix 🤔
But people would lose I/O functionality ~ although that is resolvable through Type-C adapters 🙄🤔

Edit 2:
The problem with this actually 'little" issue,
Aside from brand misstrust ~ which will stay for a long time now
Or the lost of jobs & salary it brings with it. Not to forget each of the board partners who lose a big cut
Is that it affects more than 80% of the boards
The number is likely even higher
And the wealth and payment of all these workers depend on this one semiconductor, who messed up and was problematic to talk with before the usb issues where public

Soo it's really a fragile topic to talk about, even when the issue is soo simple and little. The tail of issues, on the problem maker is long and will have trust sideeffects for the next year at least, in the pc component market 😐
Eh at least their product functions ~ its an enthusiast complain, soo maybe it can be fine for cheaper devices 🤔


----------



## Veii

craxton said:


> thats something i believe ALL BOARDS with EZ DEBUG led should do... most the time
> cant even tell without a flashlight unless one knows the order anyhow.


Basic colour and brightness change
Helps you see the issue from 1m away
Strongly appreciate this little change ~ even when debug codes sequences could be more accurate 


craxton said:


> all these settings would perhaps make it easier to overclock in general, but none the less STILL FIGHTING MSI
> to unlock CPU VDDP....it hasnt been said time limit yet the closed BOTH my tickets for the emails ive sent both with the same
> responses...
> perhaps ASUS would simply be the (fix for all) at this point... but i myself have only used MSI bios


Ask them about Standby VDDP voltage access, which should be between 900-930mV
Sadly the board doesn't allow to go lower than that, but at least it's 900mV already



Dreamic said:


> Of course my B550 Tomahawk doesn't have the option to set DPM LCLK like this, not that it would probably even matter, if I got an unlocked BIOS or something with the option.
> You or someone should maybe make a Google Sheet or something of like verified/confirmed WHEA-free boards to buy, would definitely be useful information.


A list will happen 
Tho last time i made a huge list here it was removed because either
A.) The bot didn't like the length of the big list (in a spoiler)
Or B.) The affected board partner didn't like the results digging on their RGB drivers and why they cant hold consistency there haha

(WHEA 19 is not an RGB issue) 🙈
Don't worry too much about DPM CLCK
it was an advice how it has to function for better cache and interconnect performance, but not a requirement to be WHEA free
New bioses after SMU 56.44 do set it correctly ~ just not always
Soo a consistency advice there if you have access

Collected till today a list of serval examples for voltage scaling and timinga from CL9-9-9 , CL12-12-12 to my current set, between FCLKs and auto XMP predictions
(As XMP predictions finally function)
I want to review this board at the same time as making the issue public
It needs preparation and i needed more time testing the quirks of this bios, with access to all the options 
Soo probably in a new thread or two
Will still reveal it in less than 24h


----------



## mirzet1976

craxton said:


> question for anyone that can answer,
> 
> ive ran TM5 25 cycles for over 10 hours now, but its still not finished and
> its not using any ram at all on my system at this time...
> 
> is it possible to be bugged due to hibernating last night?????
> been on cycle 24 since 8 hour mark...
> View attachment 2490431


There is something similar, the PC was turned on for 3 days and then I did the Aida64 benchmark 3 runs and the result is ...


----------



## mongoled

@mirzet1976 

What voodoo magic is that 3800/1900 with latency under 50 ns ??


----------



## Veii

Blameless said:


> Adjusting the SMU DPM settings significantly reduced the rate of WHEA #19 errors past 1900 FCLK, but didn't eliminate them, and didn't make FCLK 1966 or higher any more usable. It almost, in conjunction with a bit of vSoC tuning, made 1933 viable on my ASRock B550 Phantom Gaming-ITX/AX setup, but there were still a few errors.
> 
> I can still POST at 2033 FCLK, but 1966 and 2000 are super flaky no matter what I do and constantly produce error 19s while dropping USB devices at random.


Your board should be WHEA 19 free
Maybe not WHEA 18

It probably also could be that i nail the settings every time, but i really doubt ~ as i will demonstrate stock XMP being stable till 2067FCLK on the ProArt. 2100 then only needed either a bit of IOD or a bit of SOC bump
2100 for me needed a long time on this itx board and it was a combination of CKE and RTT issues
Well and VDDG CCD being too high or procODT being very wrong + VDDP being beyond 900mV

If you want, i still have some black-copy, full spi rom exported fallback bioses
In case amd does anything stupid, AGESA changes drastically, well or PSP-Firmware updates
They are signed and have all my old FCLK experiments and profiles till 2067 FCLK
You could then restore it and use the profiles as a test
~ first downgrade to non 1200 AGESA and then use flashrom to override the flash chip

Then you can update higher in case you see a benefit, and it will keep the profiles
Till 1200 you have no problems, after 1202 it rewrites a lot and this pretty much disables the USB ports within windows
I dont have a current copy of the board's bios with profiles (yet) as i switched to the other one
(Maybe if i resolder the probes, i could export it again with the EVC2)
But you absolutely shouldn't have any WHEA across the whole FCLK range
It either is stable or randomly crashes, well or package throttles, but there are no WHEA 19s there 
It's only possible if ASRock pushed a new revision of the ITX/AX

Edit:
Can i ask if you use any NVMe as a main boot device
Just for research, as you really shouldn't be WHEA 19 error'ing on this board, unless they re-released another revision of it


----------



## jomama22

mongoled said:


> @mirzet1976
> 
> What voodoo magic is that 3800/1900 with latency under 50 ns ??


Maybe an odd hpet sync issue from the uptime would be my guess.


----------



## lmfodor

Veii said:


> Your board should be WHEA 19 free
> Maybe not WHEA 18
> 
> It probably also could be that i nail the settings every time, but i really doubt ~ as i will demonstrate stock XMP being stable till 2067FCLK on the ProArt. 2100 then only needed either a bit of IOD or a bit of SOC bump
> 2100 for me needed a long time on this itx board and it was a combination of CKE and RTT issues
> Well and VDDG CCD being too high or procODT being very wrong + VDDP being beyond 900mV
> 
> If you want, i still have some black-copy, full spi rom exported fallback bioses
> In case amd does anything stupid, AGESA changes drastically, well or PSP-Firmware updates
> They are signed and have all my old FCLK experiments and profiles till 2067 FCLK
> You could then restore it and use the profiles as a test
> ~ first downgrade to non 1200 AGESA and then use flashrom to override the flash chip
> 
> Then you can update higher in case you see a benefit, and it will keep the profiles
> Till 1200 you have no problems, after 1202 it rewrites a lot and this pretty much disables the USB ports within windows
> I dont have a current copy of the board's bios with profiles (yet) as i switched to the other one
> (Maybe if i resolder the probes, i could export it again with the EVC2)
> But you absolutely shouldn't have any WHEA across the whole FCLK range
> It either is stable or randomly crashes, well or package throttles, but there are no WHEA 19s there
> It's only possible if ASRock pushed a new revision of the ITX/AX
> 
> Edit:
> Can i ask if you use any NVMe as a main boot device
> Just for research, as you really shouldn't be WHEA 19 error'ing on this board, unless they re-released another revision of it


@Veii, very interesting what you found out about the boards. I had no luck with my CrossHair Hero 8. In fact, I was about to order a B550 Unify X instead of the Dark Hero. and now, I'm thinking of using my Phantom Gaming B550. Do you think it will work better? Maybe I don't need VRMs as strong as you thought. What is the best BIOS version for B550 Phantom Gaining? I used it for a couple of weeks and changed it for the asus. 

BIOS update didn't seem so simple and intuitive, not even where to download it from. It seems I have to play with my old ASRock again. Any other suggestions for the 5900 and the asrock? I mean VRM or other settings. Tomorrow I start to take everything apart to see how it works. I swear I was about to buy the UnifyX, and for very little on the Dark Hero ... something incredible this. I agree with you, that they turn off the module. Let's lose USB C. I hope they solve it soon .. I was left with the desire for a board with better OC capacity for the memories

Thanks!


Sent from my iPhone using Tapatalk Pro


----------



## Dar|{cyde

mirzet1976 said:


> There is something similar, the PC was turned on for 3 days and then I did the Aida64 benchmark 3 runs and the result is ...
> 
> View attachment 2490441
> View attachment 2490442
> 
> View attachment 2490443


How are you getting 4900 MHz on a 5600X? I'm guessing older AGESA?


----------



## RonLazer

It's pretty easy to run a static OC at 4.9GHz on a 5600X actually.


----------



## PJVol

RonLazer said:


> It's pretty easy to run a static OC at 4.9GHz on a 5600X actually.


It's much easier just to run PBO with boost override +250 on 56.43.0. Enough for good results in AIDA



Veii said:


> Can i ask if you use any NVMe as a main boot device


The exact same question (actually, the reverse, cause I do have nvme pcie x4 as data/game storage with windows pagefile on it) haunts me since whea19 battle, and every time it hits me, tempts to swap it with system-boot m.2 sata III ))
Do you have any SATA m.2 in your current rig?


----------



## Blameless

Veii said:


> Your board should be WHEA 19 free
> Maybe not WHEA 18


Most of my AM4 setups have seen correctable WHEA 19 errors long before any WHEA 18s or most other apparent problems. Usually takes at least 100MHz of FCLK after the 19s show up for crashes featuring 18s to occur. Even 2000 FCLK doesn't crash outright on this ASRock + 5800X, it just spits out hundreds of WHEA 19s per minute while dropping USB devices. The system will actually pass benchmarks and quick stress tests...if I can get them started with intermittent access to input devices.

On my 3700X and 3900X, WHEA 19s are the very first sign I've pushed FCLK too far and are a real chore to eliminate at the edge of stability. At 1866 FCLK on the 3900X (also previously on the ASRock) , the only signs of potential instability I saw were one error 19 every 50-70 hours, and it took a large bump (~50mV) in vSoC and VDDG to eliminate that.



Veii said:


> It probably also could be that i nail the settings every time, but i really doubt ~ as i will demonstrate stock XMP being stable till 2067FCLK on the ProArt. 2100 then only needed either a bit of IOD or a bit of SOC bump
> 2100 for me needed a long time on this itx board and it was a combination of CKE and RTT issues
> Well and VDDG CCD being too high or procODT being very wrong + VDDP being beyond 900mV


Might have to play with settings some more, but I've never seen CKE do anything to any of my boards (Auto is 1 and I can plug in any number without any apparent effect), and some of my CPUs have needed high VDDG CCD to eliminate error 19s.



Veii said:


> If you want, i still have some black-copy, full spi rom exported fallback bioses
> In case amd does anything stupid, AGESA changes drastically, well or PSP-Firmware updates
> They are signed and have all my old FCLK experiments and profiles till 2067 FCLK
> You could then restore it and use the profiles as a test
> ~ first downgrade to non 1200 AGESA and then use flashrom to override the flash chip
> 
> Then you can update higher in case you see a benefit, and it will keep the profiles
> Till 1200 you have no problems, after 1202 it rewrites a lot and this pretty much disables the USB ports within windows
> I dont have a current copy of the board's bios with profiles (yet) as i switched to the other one
> (Maybe if i resolder the probes, i could export it again with the EVC2)
> But you absolutely shouldn't have any WHEA across the whole FCLK range
> It either is stable or randomly crashes, well or package throttles, but there are no WHEA 19s there
> It's only possible if ASRock pushed a new revision of the ITX/AX


Might take you up on the offer, though, ideally I'd like to retain 1202 or 1201.



Veii said:


> Can i ask if you use any NVMe as a main boot device
> Just for research, as you really shouldn't be WHEA 19 error'ing on this board, unless they re-released another revision of it


Main boot device on the ASRock is a PCI-E 4.0 NVMe SSD attached to the CPU and there is a PCI-E 3.0 SSD attached to the chipset. Most of my AM4 setups look something like this. There are two Sabrent Rocket 4.0s and four Sk Hynix P31s between my two B550s and one X570 board. Oddly enough, my ASRock ITX is the only one that has any SATA devices attached.

I don't think this is a new revision of the ITX/ax. I didn't buy it that long after it became available.


----------



## Nizzen

mirzet1976 said:


> There is something similar, the PC was turned on for 3 days and then I did the Aida64 benchmark 3 runs and the result is ...
> 
> View attachment 2490441
> View attachment 2490442
> 
> View attachment 2490443


Show us some performance in games, to see if the performance really is there 

Start with Tombraider


----------



## KedarWolf

KedarWolf said:


> G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4000 (PC4 32000) Desktop Memory Model F4-4000C16D-32GTZNA - Newegg.com
> 
> 
> Buy G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4000 (PC4 32000) Desktop Memory Model F4-4000C16D-32GTZNA with fast shipping and top-rated customer service. Once you know, you Newegg!
> 
> 
> 
> 
> www.newegg.com
> 
> 
> 
> 
> 
> 
> DDR4 4000 (PC4 32000)
> Timing 16-16-16-36
> CAS Latency 16
> Voltage 1.40V
> 
> 
> Just bought this and only $2.01 more for rush shipping.
> 
> From newegg.ca though, but I link .com for you peeps as not too many of us are from Kanuckistan.


Strange this is advertised for Ryzen 5000 series but the QVL only has Z390, Z490 and Z590 motherboards.









F4-4000C16D-32GTZNA - QVL - G.SKILL International Enterprise Co., Ltd.


Check to see if your motherboard model is on the QVL for F4-4000C16D-32GTZNA. Trident Z Neo DDR4-4000 CL16-16-16-36 1.40V 32GB (2x16GB).




www.gskill.com


----------



## GribblyStick

@Veii
Was able to push EDC higher still. Up to 238 effective for sustained periods.

This was from an R23 run:









Can't say I'm getting better performance for it though.
Best Score on R23 was still with stock limit oddly enough.


----------



## DeletedMember558271

Alright I think we might stable








Now if I'm bored I'm a bit curious just how much more voltage I'd need for tCL & tRCDRD @ 14, tRCDRD 14 is already stable for hours sometimes so might just need 1.460v, tCL 14 doesn't even post though. And would probably be able to lower tRP, tRC, and tRFC a bit too, maybe tCWL to 12 if lucky. Might be able to get tRDWR & tWRRD to 10/1 or 8/3 as well, I don't actually know how much more preferable those are over 9/2 but I see way more people running them, they won't post for me with these settings currently though.

Not much else I can do I think, SCL's might be able to go lower too but it's not even beneficial apparently.
Looks like the end of the road


----------



## Ramad

WHEA errors are related to system instability, mainly IMC, and in case of users trying to run higher than FCLK=1900 then I think it's clear that the IMC as a hardware has reached it's physical limit and can't perform correctly beyond this frequency. Most of the users are hitting the wall at FCLK=1900+, so this is very clear sign of end of the line for IMC capability. I think that any user should accept this hardware limitation and be happy with this result, which is not a bad result. 

Suggesting that this is a motherboard or a motherboard design issue is incorrect, because all motherboards (X570 and B550) are, more or less, performing equally in this regard. Moreover, if you have a 3rd. or 5th. gen Ryzen, and run your system at FCLK/2 the you will be able to hit higher memory frequencies than 3800MT/s which indicates good memory-IMC traces, so the limitation is the IMC itself. 

In every platform or a CPU architecture, you will find disparity in quality, so when it's clear, to me at least, that nothing is wrong with these CPUs/IMCs when 99.9% of them are performing in the same way. 

You will never use your system for the reason you have bought and build your system for, unless you accept and live with the physical limitations of your hardware, if you don't accept these clear limits then you will only end up with chasing fairy tells.


On another note, TM5 is a junk program that should never be used to confirm stability. There are good programs that will reveal actual instabilities, such as y-cruncher and prime95 for CPU+IMC, OCCT and LinX for Ryzen for CPU, Real bench and Blender for over all system stability.

You want to know how good/bad your settings are then use LinX using 80% of your RAM and see how many GFLOPS you are getting compared to other settings, programs that spits results in a few seconds are not reliable.


----------



## PJVol

Ramad said:


> in case of users trying to run higher than FCLK=1900 then I think it's clear that the IMC as a hardware has reached it's physical limit and can't perform correctly beyond this frequency.


Care to elaborate, what makes it so clear for you?


----------



## TimeDrapery

Ramad said:


> Spoiler
> 
> 
> 
> WHEA errors are related to system instability, mainly IMC, and in case of users trying to run higher than FCLK=1900 then I think it's clear that the IMC as a hardware has reached it's physical limit and can't perform correctly beyond this frequency. Most of the users are hitting the wall at FCLK=1900+, so this is very clear sign of end of the line for IMC capability. I think that any user should accept this hardware limitation and be happy with this result, which is not a bad result.
> 
> Suggesting that this is a motherboard or a motherboard design issue is incorrect, because all motherboards (X570 and B550) are, more or less, performing equally in this regard. Moreover, if you have a 3rd. or 5th. gen Ryzen, and run your system at FCLK/2 the you will be able to hit higher memory frequencies than 3800MT/s which indicates good memory-IMC traces, so the limitation is the IMC itself.
> 
> In every platform or a CPU architecture, you will find disparity in quality, so when it's clear, to me at least, that nothing is wrong with these CPUs/IMCs when 99.9% of them are performing in the same way.
> 
> You will never use your system for the reason you have bought and build your system for, unless you accept and live with the physical limitations of your hardware, if you don't accept these clear limits then you will only end up with chasing fairy tells.
> 
> 
> On another note, TM5 is a junk program that should never be used to confirm stability. There are good programs that will reveal actual instabilities, such as y-cruncher and prime95 for CPU+IMC, OCCT and LinX for Ryzen for CPU, Real bench and Blender for over all system stability.
> 
> You want to know how good/bad your settings are then use LinX using 80% of your RAM and see how many GFLOPS you are getting compared to other settings, programs that spits results in a few seconds are not reliable.


@Ramad 

Dude, this is the second time you've showed up to "school everyone" without _actually_ contributing to the knowledge base that is this long-running thread...

I understand that you harbor different beliefs and this, necessarily, sets your expectations regarding interactions with the individuals participating in this thread... Askew

If TM5 is, in your own words, "a junk program"... Tell us *why* you believe it's a junk program

If the other programs you mentioned are, in your eyes, better options... Again, tell us *why*

Without the why it's near impossible to take you seriously because, as far as I can see, you've demonstrated (and/or provided) 0.000 reasons that support your authoritative claims regarding memory overclocking, stability testing, or the _proximate_ cause of high FCLK WHEAs... All you've done is act like some know-it-all that dislikes any information not directly propogated by some organization making money through the standardization of industrial practices and the licensing of said standards to manufacturers and vendors

Thanks for sharing your spreadsheet, no thanks for causing me to spend the additional minute to run a stupid macro against the sheet and unlock it

If you are looking to have people agree with you blindly regarding your assertions... This likely isn't the place for you, you'll have to find another site wherein the participants don't care much for independent thinking and exploration on/of their hobbies/livelihoods and will simply acquiesce to you once you harsh your "tone"

*TLDR*; You sound like a **** and you're sounding cuntier and cuntier with each and every post... **** off or cool out and truly contribute through sharing your knowledge, not your opinions


----------



## Veii

Ramad said:


> Suggesting that this is a motherboard or a motherboard design issue is incorrect, because all motherboards (X570 and B550) are, more or less, performing equally in this regard.


I wish i could share & live your reality, trust me i really wish.
Sadly my reality shows something different - on the same CPU within both X570 & B550 tested boards
The pattern is very clear and i'm very confident on the issue.

My really shows a big messup from one semiconductor and a huge amount of money that is into play.
Not only from AMDs side, but from every boardpartner which's margin is in line when "all" their for example B550 boards have this fundamental issue ~ and still are dependent on semiconductors willpower and happiness, to provide a FW fix (somedayTM)

My reality showed very well where NDAs where made and the attempts to carve/sweep the issue under the carpet, soo nobody notices.
I really wish i could agree and live with this viewpoint that everything is fine 
Life would be soo much easier ~ than hunting enforced lockdowns and holding the community for dumb for a whole CPU generation (Matisse).
Sorry but i can not relate to this, well you have an easier life with the viewpoint.
Very glad that you are happy with your hardware and the brand's business practices. Less problems in life that way



Ramad said:


> On another note, TM5 is a junk program that should never be used to confirm stability. There are good programs that will reveal actual instabilities,


Unclear wide spectrum of attack ~ against a program which does justify and do it's work for a sole single operation & does do this work very accurately, up to users configuration.
TM5 by the Russian developer on it's own does "nothing" without the loaded userconfig
Which up to config maintainer, will test different spectrums of the memory compared with different verified datasets

I've expected more from you , than comparing it with any CPU test ~ or not noticing how it performs
I'm sorry ,but this part of the message is purely wrong.
There are cpu intensive memory tests like you mentioned. Same OOCT has a normal linpack which is good on it's own
But the "medium dataset" same as IBT both are useful

As for your specific complain,
Karhu, GSAT, HCI are all very good tests (up to testing size) , but they do test two factors at once and don't report the error
GSAT is an exception
Your point is valid as a personal point - but your attack against the huge testing spectrum you expect from a program that's sole focus is to test "timings" and nothing more , with the least amount of system stress
Is hitting a point of "ashaming to write"
I don't want to be thaat harsh, soo maybe you had bad experience or got taught wrong
Oor have a personal emotional issue with the developers 
But the tool by itself "TM5" does do it's sole and core job very well
"Test memory timings,up to users configured method and hash-compare the result"
This is it's pure sole work, and nothing else. You the config maker are responsible for it testing the correct location with "testing methods".
It is neither an AVX test, nor will it verify your GPU or anything other FCLK related.


Blameless said:


> Oddly enough, my ASRock ITX is the only one that has any SATA devices attached.


Yes i was only focusing on the ITX
Also the B550 Taichi is free from this issue

Unless they changed & remade the PCB plus got other IO supliers
It should be fully WHEA free
I was asking about the M.2 part, as AMI updated the current NVMe module ~ and there is a bit of conflicting information out there when it comes to board partners bios compilation
But no, you should not have any issues with the ITX/AX
the ITX/AC has issues and the remain Phantom Gaming has issues (b550)
X570 around half of them have issues, B550 90% of them have issues


----------



## lmfodor

Veii said:


> Yes i was only focusing on the ITX
> Also the B550 Taichi is free from this issue
> 
> Unless they changed & remade the PCB plus got other IO supliers
> It should be fully WHEA free


@Veii, can you confirm if the Taichi B550 doesn´t have the IF issue? I am just about to buy another mobo to change my CH8. I also see the GB Aorus Master B550 which looks good and has dual BIOS, but I don't know if it has the problem. I quite liked the VRM setup of the Taichi.

I currently have an ASROCK B550 PHANTOM GAMING 4 & 4 / ac. Tomorrow I will test if you have this issue..

Thanks!


----------



## Blameless

Veii said:


> But no, you should not have any issues with the ITX/AX


The errors I'm getting are corrected (19) bus/interconnect errors. Any they happen in this board over 1866FCLK on my 3900X and over 1900FCLK with my 5800X. No permutation of settings seems to fully eliminate them past these speeds and they don't seem to have anything to do with memory at all, just FCLK.

Haven't tried it without the NVMe drive.


----------



## Ramad

PJVol said:


> Care to elaborate, what makes it so clear for you?


If 100+ pages of posts contains "I'm stable at 3800MT/s but I get WEHA errors at anything higher than that" does not make it clear, then I don't know what else makes it clear.



TimeDrapery said:


> @Ramad
> 
> Dude, this is the second time you've showed up to "school everyone" without _actually_ contributing to the knowledge base that is this long-running thread...
> 
> I understand that you harbor different beliefs and this, necessarily, sets your expectations regarding interactions with the individuals participating in this thread... Askew
> 
> If TM5 is, in your own words, "a junk program"... Tell us *why* you believe it's a junk program
> 
> If the other programs you mentioned are, in your eyes, better options... Again, tell us *why*
> 
> Without the why it's near impossible to take you seriously because, as far as I can see, you've demonstrated (and/or provided) 0.000 reasons that support your authoritative claims regarding memory overclocking, stability testing, or the _proximate_ cause of high FCLK WHEAs... All you've done is act like some know-it-all that dislikes any information not directly propogated by some organization making money through the standardization of industrial practices and the licensing of said standards to manufacturers and vendors
> 
> Thanks for sharing your spreadsheet, no thanks for causing me to spend the additional minute to run a stupid macro against the sheet and unlock it
> 
> If you are looking to have people agree with you blindly regarding your assertions... This likely isn't the place for you, you'll have to find another site wherein the participants don't care much for independent thinking and exploration on/of their hobbies/livelihoods and will simply acquiesce to you once you harsh your "tone"
> 
> *TLDR*; You sound like a *** and you're sounding cuntier and cuntier with each and every post... *** off or cool out and truly contribute through sharing your knowledge, not your opinions


TM5 is junk, use it and when you are stable, run prime95 or y-cruncher and see if your system is really stable. Go back a few posts back and see for your self how bugged it is.

Why other programs are better ? I don't know, years of testing that proved them reliable maybe?

"_*you've demonstrated (and/or provided) 0.000 reasons that support your authoritative claims regarding memory overclocking, stability testing, or the proximate cause of high FCLK WHEAs*_" Hmm...read a few 100s posts back and use your logic.

"*Thanks for sharing your spreadsheet, no thanks for causing me to spend the additional minute to run a stupid macro against the sheet and unlock it*"
You are welcome, it's my pleasure. You could have sent me a PM and I would have given you the password, I decided not to share the password at the last moment, because I don't have time to deal with complains.

"*TLDR*; *You sound like a ** and you're sounding cuntier and cuntier with each and every post... ** off or cool out and truly contribute through sharing your knowledge, not your opinions*" I'm not going to answer this, I guess our manners are different. I wish you good luck.


@Veii

"_*I wish i could share & live your reality, trust me i really wish.*_"

My reality is simple.

I respect the physical limitation of systems hardware and tune my system as good as it' can be done, run a stability test for 2 hours as minimum and post them here or any other thread, my results are backed up by screenshots proving that my system is running stable at the shown settings. I don't post unstable settings, never have and never will, show off screenshots are not my thing, if a setting screenshot is not backed up by a stress test then it's worthless for me, and there are tons of them here at this thread, which is named "*AMD Ryzen DDR4 24/7 Memory Stability Thread*". 

I hope you are right about a motherboard that does better, but what are you going to do if members here buy this motherboard that you are recommending and still hit the same wall as the rest of motherboards? Compensate them for their losses when they have 2 motherboards that perform identically, if not the latter is worse than the old one?

I hope that you have thought this through.


----------



## Veii

Ramad said:


> I respect the physical limitation of system's hardware and tune my system as good as it' can be done, run a stability test for 2 hours as minimum and post them here or any other thread, my results are backed up by screenshots proving that my system is running stable at the shown settings. I don't post unstable settings, never have and never will, show off screenshots are not my thing, if a setting screenshot is not backed up by a stress test then it's worthless for me, and there are tons of them here at this thread, which is named "*AMD Ryzen DDR4 24/7 Memory Stability Thread*".
> 
> I hope you are right about a motherboard that does better, but what are you going to do if members here buy this motherboard that you are recommending and still hit the same wall as the rest of motherboards? Compensate them for their losses when they have 2 motherboards that perform identically, if not the latter is worse than the old one?
> 
> I hope that you have thought this through.


Yes i do know that TM5 is not "only" enough - and it's why i always provide y-cruncher with it
Unless i know or have supplied that these specific changes (voltages and procODT + freq changes) are rock stable already
TM5 really only tests timings, soo i prefer it over Karhu and HCI
It won't show if they are better (maybe if the stresstest takes less time to complete)
But compared to Karhu & HCI , which both will fail if the CPU cores are unstable ~ TM5 barely to never fails for such
Only Error 6 sometimes can mean external issues away from the memory by itself

That's what i think everyone of us knows, TM5 by itself is not enough
But the work it does for itself, is enough in most cases ~ when the rest is stable
It is complicated to phrase ~ but i do think that we all know this here
A single TM5 is not enough, that should be known already ~ and the first post of this thread even mentions to use HCI or Karhu
GSAT i would put on the list like TM5, purely timings related but nothing else

About the motherboard part,
I take my time and don't just spil the beans, because the issue is big
There is too much business deals around this what appears "little" issue
To spill a bit - "MSI & Gigabyte" have not even one B550 board which is free from this Whea #19 trigger issue even 1mhz beyond 1900

WHEA #19 on it's own is IO related, and usually lies between the IO-Die and the Chipset
The problem is, i am already very confident it's FW related ~ of something that is build in the boards
Half of ASUS B550 boards are affected & 90% of the B550 ASRock ones are
X570 at least the "damage" looks less extreme, and old X370 & X470 boards (the flagships) appear to be fine

I'm still thinking how to phrase it and collect email data that proofs my point where X semiconductor keeps fooling and messing with the boardpartners
Although i do think that every of the board partners knows this issue and AMD does know it very well
Just money is into play, and the suppliance deal they made ~ is a far bigger number than we "enthusiasts" who have the issue "only on higher FCLK"
Where the issue can also be pushed as "PCIe 4.0 crashes beyond 2000 FCLK ~ an architectural limit"

All these USB fixes where only a sideproduct to fix a bad behaving design, which sadly is build in close to every mainboard
I played with the dark hero , and had nothing but WHEA 19 problems
Autocorrection and other little annoying Vermeer things exist, but this is a bigger issue ~ soo i really take my time to gather enough information , before making such "brand-shaming" post
Notebooks can also be affected , as this issue even 3 months after discovery by board-partners, is yet not fixed in the hidden
We all (well most) still suffer from "a 1900FCLK limit" ~ one that has neither FCLK instability nor MCLK instability or CPU Core instability as a base
It shows as random unknown kernel error apparently by the IO
My ProArt purchase just confirmed my long going theory ~ and it makes now more sense
But because of all the hate that can come out of this post, i still take my time to make it more analytical without putting any random semiconductor into target/fire 

I know what you want to tell me, but there are really many issues that can cause WHEA #19
Sadly one of these is a major board design problem users can do nothing about it except refund or bios mod & erase the module fully
Deactivating it does nothing at all, it still is loaded and triggers WHEA's
Keeping it hidden will never resolve the issue, and putting it easily out there will brand-misstrust a major player in the supply chain + also push the fire back to me for whatever excuses/talking out ~ points they find


----------



## craxton

Blameless said:


> Might have to check out what other options there are currently


depending on what your aiming to spend honestly lol..but seeing how 
many posts you have, this aint your first rodeo 



Blameless said:


> Need to save some money for a DDR5 platform.


wouldnt one be able to assume that since DDR5 comes, that 
an entire new platform/chip etc would be envolved?



jomama22 said:


> (USB chips, networking chips, etc.)


hmmm, idk how CHEAP they went on the X570 version of this b550 gaming
edge wifi board i use now. but it didnt have WHEA errors that i seen while running the 3600xt 
at 3800mhz even when i ran 4x8 with it..



Blameless said:


> dropping USB devices at random


gotta admit, only usb dropout i have now, is when my razer mouse goes to sleep 
from power save being set to 1 minute inside synapse software (HATE btw..the software)



KedarWolf said:


> Just bought this and only $2.01 more for rush shipping


......thats more than my board alone in US currency...do let us know how these sticks fair out 
for that price...one should expect HIGH THINGS..



Veii said:


> Basic colour and brightness change
> Helps you see the issue from 1m away
> Strongly appreciate this little change


ABSOLUTLY, cant see them on this b550 at all...when they decide to work.
usually when i attempt to adjust something that wont work, i just HARD lock
and have to reset the bios. but then again, they have gotten the ram overclock failed
issue way better than it used to be as now itll revert old settings so long as i use + and - per value in
throughout the bios



Veii said:


> debug codes sequences could be more accurate


unsure you can ever count on that being a thing.. 
unusual for one to have a post code and ezdebug tho?



Veii said:


> Ask them about Standby VDDP voltage access


will email shortly, the website was having issues yesterday 
all the way back till tuesday. this morning one still could not download AB 
thru the site...



mirzet1976 said:


> There is something similar, the PC was turned on for 3 days and then I did the Aida64 benchmark 3 runs and the result is


i dont quite understand what you mean....i se no difference in your aida benchs? 
you saying it took 3 days to run TM5?????


----------



## Veii

craxton said:


> hmmm, idk how CHEAP they went on the X570 version of this b550 gaming
> edge wifi board i use now. but it didnt have WHEA errors that i seen while running the 3600xt
> at 3800mhz even when i ran 4x8 with it..


If the whole supply of them is to blame, then you should get WHEA 19's on 1933 FCLK
If you won't, then i'm happy that it's not thaat catastrophic and it's only one batch, not everything affecting soo many boards
On the MSI X570 Gaming Edge (wifi)

EDIT:,
i think i missunderstood you & you do run the B550 version not X570
But if my theory is right and it's as worse as i think
the X570 Gaming edge, should also be affected at 1933+
With a bios that doesn't have any artificial FCLK limits ,SMU 56.43 and higher


----------



## craxton

mongoled said:


> What voodoo magic is that 3800/1900 with latency under 50 ns ??


wouldnt the static oc have an impact on that?
or would it not be near as much as 1.x ns? as im thinking.



Veii said:


> B550 90% of them have issues


this B550 problem, have the gaming edge included?
as stated, had ID20, and ID 18 (18 when i had WAY TO LOW voltage on the chip with CO/30 running)
and 20 when i simply...well same thing actually just not quite as low needed one bump more...



Ramad said:


> 100+ pages of posts contains "I'm stable at 3800MT/s but I get WEHA errors at anything higher than that" does not make it clear, then I don't know what else makes it clear


if i cant run TM5 then i cant run any of the other tests to start, let alone pass HCI or OCCT?
one starts with RAM testing usually and then focuses on cpu



Ramad said:


> TM5 is junk, use it and when you are stable, run prime95 or y-cruncher and see if your system is really stable


again, i pass TM5 and run PRIME and crash this doesnt mean ram is at fault? can
be Cpu CORE, etc.
90% of "most" vets here wont come and claim stable with simply posting TM5 passing.
but, if they dont pass TM5 then they AUTO know theyre NOT passing y or prime. let alone occt.
you claim to post proof of your findings and claims. but im here LITERALLY everyday....



Spoiler



wheres your pics??? we all would like to see lol
let alone be shown this "statistical" data proving your claims?





Ramad said:


> Go back a few posts back and see for your self how bugged it is


if you mean me, and having been bugged out, well thats my own error which ill
not explain as its not really needed.

after all, i can just make "that claim" and thats all i need?



Spoiler



honestly i dont get why your [tilted] so much about this thread.
if you dont agree with whats being done or said here, its just as easy
to leave, or share discord ( 80% sure twas you who said it last time you give help in discord? )
to where others will follow with all the knowledge you share here?


----------



## craxton

Veii said:


> B550 version not X570


yes you got me right, running only the b550 now.
didnt run the 5600x in my x570 board as the VRM temps we hitting 60c on
a 3600xt. so i didnt believe it to be wise to push a "better" chip
on such a cheap made board, it was one of the earlier made in that note tho.

i got the b550 used-good on amazon still sealed in the static bag with all goodies sealed to for
130.00 usd after tax. (and registered on MSI on that note)

i never pushed the x570 passed 3800/1900 as the 3600xt (maybe the boards doing)
wouldnt go past 1900.....

EDIT<my question is only for the B550 gaming edge wifi> 
my uncle has the x570 board now, and doesnt care about overclocking at all...


----------



## TimeDrapery

Ramad said:


> Spoiler
> 
> 
> 
> TM5 is junk, use it and when you are stable, run prime95 or y-cruncher and see if your system is really stable. Go back a few posts back and see for your self how bugged it is.
> 
> Why other programs are better ? I don't know, years of testing that proved them reliable maybe?
> 
> "_*you've demonstrated (and/or provided) 0.000 reasons that support your authoritative claims regarding memory overclocking, stability testing, or the proximate cause of high FCLK WHEAs*_" Hmm...read a few 100s posts back and use your logic.
> 
> "*Thanks for sharing your spreadsheet, no thanks for causing me to spend the additional minute to run a stupid macro against the sheet and unlock it*"
> You are welcome, it's my pleasure. You could have sent me a PM and I would have given you the password, I decided not to share the password at the last moment, because I don't have time to deal with complains.
> 
> "*TLDR*; *You sound like a ** and you're sounding cuntier and cuntier with each and every post... ** off or cool out and truly contribute through sharing your knowledge, not your opinions*" I'm not going to answer this, I guess our manners are different. I wish you good luck.


I'm not asking you why other programs are better, I'm asking you to share why TM5 is junk... Excellent diversion tactic normally intended to save face when one doesn't have an answer for a question one's asked though



Spoiler















I don't think I need to read back "100s" of pages when your post history goes back two months... Link me to what you're talking about and I'll read it

I've tried considering an alternative meaning to your statement and the only one I've arrived at would be that the last 100s of pages are sufficient evidence of WHEAs' presence... *Yet again*, that's not what I'm asking you to show me... I'm asking you to show me definitive proof of _*your *_statement regarding their p_roximate _c_ause_, you go so far as to state individuals are encountering a _physical limitation_... If anything, the last "100s" pages indicate it's _not_ a physical limitation unless that limitation can be overcome through different combinations of hardware and software as well as their configurations (as @Veii *is* indicating)

This bit about the spreadsheet is actually very kind and I do apologize for poking at you for password protecting it and assuming you'd be a prick were I to PM you regarding the unlocking of the sheet... That was very nice of you to share it as you did

See? I'm not a _*complete*_ piece of ****

Also, I apologize for calling you a **** and saying that your replies sound cuntier and cuntier... That's uncalled for and I'll do my best to better control my emotionally charged responses so as to avoid insulting you while attempting to get you to share with the group all the little nuggets of knowledge you've managed to accumulate over the years... Now that I type it out I see that tactic is likely very counter-productive

Yes, our manners are _very_ obviously _very_ different, doesn't mean we can't be friends... I wish you the best of luck as well


----------



## Veii

craxton said:


> this B550 problem, have the gaming edge included?
> as stated, had ID20,


ID 20 on the datase log like Mannix-ITA shared , or inside the system kernel logger where all the WHEA's come
ID 20 in the database has nothing attached to it - and doesn't end up as an error
Error (actual error ID18 is vcore related) - lack of vcore , and restated the same by an msi bios dev

B550 , i haven't seen one MSI board which doesn't have this hardware issue
I don't think there is one 1933 FCLK record out there ?
I will go through that zen ram OC list and recheck, but i don't think there is even one who managed to get 1933 running without WHEA #19 on it

What surprises me still, is that it triggers just at beyond 1900 FCLK
It's too accurate to trigger perfectly every time after this higher bandwidth increase
Can make you think that Infinity fabric is an issue or some SMD element on the CPU itself
If you wouldn't know what crashes

It remains bizarre, but i'm very confident that it's majorly a board design issue than anything else
as FCLK doesn't really crash before 2067ish
Some can boot higher than 2167 , i can't sadly ~ beyond 2000 i see it as sillicon lottery
but WHEA #19 has nothing to do with FCLK, but always triggers with FCLK beyond a 1933
This is the bizarre thing i don't fully get yet

What link speed increase does trigger a component level crash and why does it have to do anything with GMI generally anything with the IO-Die & FCLK
Ifi only knew, then maaybe affected boards could be fixable with a different setting
but considering this issue remains a reality ~ i do think that it's not thaat easily fixable and all rely on the semiconductor to fix their Firmware
(which's email response, is to blame board design partners for not following their shematics
~ turning this issue in a loop of "nobody is to blame, we have nothing to fix") 

We got a whole inter-connect rewrite, a powermanagement rewrite, an usb rewrite, pcie link speed and chipset sleep/powerstate rewrite
and this issue still exists
H*ck, most of AMDs attempts to fix the chipset related IO after SMU 56.30
(Patch A & Patch C as enforced 1900FCLK lock to hide the issue under a carpet)
- rather caused more issues than really "fix" anything
* this issue exists since 5 months

All because a major semiconductor, where every board-partner invested a sh*ton of money for supply, messed big times up
How can i ignore this rather obvious issue. Very confident that everyone who works with it knows the issue but does nothing to it
Preventing lost sales, preventing brand-shaming, not caring about us ~ as the chunk of money invested for supply is far bigger than us & will disappear with X570S boards (hopefully)


----------



## DeletedMember558271

As a quick and probably final update to my last post,








With these settings, to change only tCL from 15 to 14, it requires going from 1.450v to at least 1.520v... no thanks. Probably 1.530v or maybe even 1.540v if I do a long stability test.
Also required changing tRDWR & tWRRD as 9&2 was unbootable with tCL 14, so made it 8&3, which is unbootable for me with tCL 15. No other changes were needed for tCL 14.

Just going to get too hot with 1.520v+ and error, even with a fan on the RAM, when 3080 comes in to play 
I still can't be too mad at 52.8ns, all things considered. 3 factors against me, 4x8GB (not that I would ever ditch Dual Rank or 32GB for less, 2x16GB DR would be preferable though), 1900 FCLK no post and any higher = WHEA, 3080 hairdryer heater nuclear reactor exhausting on my RAM. Thankful for 2T and now "1T" to make the most of everything despite everything


----------



## Blameless

craxton said:


> wouldnt one be able to assume that since DDR5 comes, that
> an entire new platform/chip etc would be envolved?


Yes. I've got a good selection of DDR4 and though I'd be inclined to play around with some new kits, they aren't a priority.

I'm already planning out an Alder Lake and/or a Rembrandt setup and can't justify spending any more on extra DDR4 that will either be immediately resold or put to pasture in the near future.



craxton said:


> gotta admit, only usb dropout i have now, is when my razer mouse goes to sleep
> from power save being set to 1 minute inside synapse software (HATE btw..the software)


I haven't had any USB issues at stable settings on any of my AM4 setups, but when the FCLK or SoC is unstable, USB seems to be one of the first things to go.


----------



## Blameless

Veii said:


> but WHEA #19 has nothing to do with FCLK, but always triggers with FCLK beyond a 1933
> This is the bizarre thing i don't fully get yet


I know correlation doesn't imply causation, but how are you so sure of this?

Bus/interconnect errors sound they could easily be directly related to FCLK, since that's the major function of infinity fabric...the interconnect between the IOD (which is itself a collection of buses/interconnects and their controllers) and CCDs.

I don't have enough Vermeer and board samples to come to any real conclusions myself, but I am using a board that supposedly doesn't have this issue where I clearly have issues past 1900MHz FCLK and that suggests, to me, that the CPU itself is a major contributor....more especially since all of the CPUs I have on hand have different FCLK limits on the same board.

If it's not the FCLK itself, it has to be something attached to it, which is functionally the same thing, until there is a reliable workaround.



Veii said:


> (which's email response, is to blame board design partners for not following their shematics
> ~ turning this issue in a loop of "nobody is to blame, we have nothing to fix")


Strictly speaking, they don't.

Anything over 1600FCLK is overclocking and AMD isn't compelled to make sure their parts work far beyond spec, even if they suggest much more in their disclaimer-laden marketing material.


----------



## Veii

@Dreamic
While playing with AMD CBS a bit more
I think i redesigned the Memory Training algorithm to be a bit more efficient


Spoiler: Do you have access to:














I've played a bit more with getting Data-Eye mode to function fully & there is a wonderful option which 2D prints the whole Data-Eye + DQs & RTTs behavior into the ABL
But i haven't figured out how to take out that log and make it usable
Overall AMD has an option hidden that actually can visualize how RTTs behave, instead of having to Simulate it with PCB trace-data
Getting access to this ABL exported path, could open the opportunity to design a fully automated memOC & calibration tool
It's beyond my power, as i can not code - but i just want to share a bit of fancy information 
Maybe someday everyone will have access to a fully open AMD CBS

There is also a mode that puts each core from one CCD into a numa node - and a 2nd option which then does interleaving between each numa node in IOMMU
stating from NPS0
(interleaving across all Numa Nodes)
NPS1 interleaving across symmetrical (if i understood it correctly ~ the nearby ones)
NPS2, between a pair of 2 on each side
NPS4 between 4 on each of the sides with a cache in the middle (how our Vermeer units are build - except that this is symmetrical interleaving)

Another fancy thing i remember, is that there is an option in GMI link ~ for "CAKE"
That can modify after which % penalty autocorrection starts to trigger, and another one that controls memory write autocorrection (attempts & amount) plus defines the range it can trigger and by how much it will autocorrect

Probably the most fancy & interesting one is the flag in
DDR4 Common Options > Dram Controller Configuration > DRAM Power Options
"Disable Burst & Postpone Refresh"
Programming SubUrgRef bounds - with Urgent-Reference-Limit and UrgRef-LowerBound
"Specifies the stored refresh limit to require entering sub-urgend refresh mode & urgent-refresh mode"
~ pretty much being the undocumented flag before that can trigger a burst refresh and the amount of postponed refreshes
Value 1-5 (to 6)
** very likely the main thing that broke my 4* tFAW set on 1201+ & core thing that makes 1* tFAW & burst tRC work positively

And this:
DRAM tMAW & tMAC control








I want to explore that "untested MAC" mode along with what you guys calculated for tMAW.tMAC = tRC_Page
"tRC_Page controls the average postponed refresh-cycle"
~ above controls the upper and lower boundaries of such
=============================================
I've played further with a better Data-Eye based memory training *
but it takes 40-50sec to train for no appeared success ~ nothing worth the 1min wait to post
Soo i need to explore and play with that part more
But the shared method, takes 2sec to post, loop through all 10x pattern tests and does test simultaneous
Played with more Aggressor Channels and further shaping them ~ but my knowledge there is a bit lacking and time too
Overall had a lot of fun the last two days with it ~ and why my posts are delayed
* i should stop giving fixed ETA times i can not hold ~ really need to learn this

Played around with a flat CL9-9 set and CL8-8


Spoiler












I think @domdtxdissar was asking about proofing/testing tRDWR 5 on Vermeer










There are still couple of straps issues between FCLK's , where low numbers simply refuse to boot
Bios issues that should be resolved by ASUS and overall AMD's Memory Controller FW 
CL11-11 & CL13-13 have nonsense boundry limits on it
CL12-12 and CL14-14 are perfectly fine
CL8-8 is funny but there the freq straps are the limiting factor

A0 PCB is fun , but the Ballistix MAX 4000C18-19 will arrive in a week
Either Micron Rev.B 2020 edition or B-die ~ on A3 custom PCB

Oh here are also some XMP "boots" verifying that predictions at this date are already usable and i didn't need to tinker with anything, except for 2100 FLCK


Spoiler





































This is how it looks when voltages are predicted wrong and "all cores randomly crash - although it's FCLK related








And when i slightly adjust voltages










All above is because i promised some results after (2x) 24h timeframe & a review ~ but not on the quality i usually share (which takes 6h each to run all stability tests)
Still exploring the big CBS menu and the possibilities & effects ~ soo bear with me please
been working my *** off but enjoy it as the board makes fun, with an open bios ~ should've been standard on ASRock. 
Sad that they stopped carrying or their engineer left

Overall the ITX board was not special in any way - and this here has "far worse" PWM & Mosfets
Yet even XMP can run 2067+ FCLK stable
Yes it can be sample based - but then i wouldn't dislike the X570 Dark Hero soo much , and really have a lot of fun with this "cheap" little board
(which in theory should have crashing thunderbolt 4 and so on ~ yet nothing , it behaves how it has to)
Glad i didn't went Biostar as i wanted (because of the Renesas 90A stages) ~ but hey PWM on a 4 phase board, really doesn't matter for FCLK success 


Blameless said:


> I know correlation doesn't imply causation, but how are you so sure of this?
> 
> Bus/interconnect errors sound they could easily be directly related to FCLK, since that's the major function of infinity fabric...the interconnect between the IOD (which is itself a collection of buses/interconnects and their controllers) and CCDs.
> 
> I don't have enough Vermeer and board samples to come to any real conclusions myself, but I am using a board that supposedly doesn't have this issue where I clearly have issues past 1900MHz FCLK and that suggests, to me, that the CPU itself is a major contributor....more especially since all of the CPUs I have on hand have different FCLK limits on the same board.
> 
> If it's not the FCLK itself, it has to be something attached to it, which is functionally the same thing, until there is a reliable workaround.


Testing and watching Vermeer since November
Working on a dual CCD & fused core unlock
Played so far with:
Normal Unify, 2 Dark Hero's, one CH8, an X570i Aorus Pro ITX (should be free from this issue, i will verify and post a 1933 score it has to be possible),
normal X570 Auros Pro (apparantly unaffected, soo i'll test too ~ 5950X),X570 Auros Elite (unaffected? but can't verify , lost contact the person), and couple of affected B450 MSI boards

I am looking into this issue since quite some time and follow the Board-Maker's "PR & Bios update Team"
Many of the things they share, gets removed, and a lot of it is under NDA
Soo at this point i'm very sure that every bios engineer is aware of this issue & they are either under NDA or remain silent to prevent sales loss

Guess i need to proof that the two Aorus Boards i have access too (5900X & 5950X) can easily run 1933 FCLK without any WHEA 19 , to strengthen the claim
As i don't have locally boards which cause me issues, although neither of them are affected too
Problematic


----------



## lmfodor

Veii said:


> @Dreamic
> While playing with AMD CBS a bit more
> I think i redesigned the Memory Training algorithm to be a bit more efficient
> 
> 
> Spoiler: Do you have access to:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I've played a bit more with getting Data-Eye mode to function fully & there is a wonderful option which 2D prints the whole Data-Eye + DQs & RTTs behavior into the ABL
> But i haven't figured out how to take out that log and make it usable
> Overall AMD has an option hidden that actually can visualize how RTTs behave, instead of having to Simulate it with PCB trace-data
> Getting access to this ABL exported path, could open the opportunity to design a fully automated memOC & calibration tool
> It's beyond my power, as i can not code - but i just want to share a bit of fancy information
> Maybe someday everyone will have access to a fully open AMD CBS
> 
> There is also a mode that puts each core from one CCD into a numa node - and a 2nd option which then does interleaving between each numa node in IOMMU
> stating from NPS0
> (interleaving across all Numa Nodes)
> NPS1 interleaving across symmetrical (if i understood it correctly ~ the nearby ones)
> NPS2, between a pair of 2 on each side
> NPS4 between 4 on each of the sides with a cache in the middle (how our Vermeer units are build - except that this is symmetrical interleaving)
> 
> Another fancy thing i remember, is that there is an option in GMI link ~ for "CAKE"
> That can modify after which % penalty autocorrection starts to trigger, and another one that controls memory write autocorrection (attempts & amount) plus defines the range it can trigger and by how much it will autocorrect
> 
> Probably the most fancy & interesting one is the flag in
> DDR4 Common Options > Dram Controller Configuration > DRAM Power Options
> "Disable Burst & Postpone Refresh"
> Programming SubUrgRef bounds - with Urgent-Reference-Limit and UrgRef-LowerBound
> "Specifies the stored refresh limit to require entering sub-urgend refresh mode & urgent-refresh mode"
> ~ pretty much being the undocumented flag before that can trigger a burst refresh and the amount of postponed refreshes
> Value 1-5 (to 6)
> ** very likely the main thing that broke my 4* tFAW set on 1201+ & core thing that makes 1* tFAW & burst tRC work positively
> 
> And this:
> DRAM tMAW & tMAC control
> 
> 
> 
> 
> 
> 
> 
> 
> I want to explore that "untested MAC" mode along with what you guys calculated for tMAW.tMAC = tRC_Page
> "tRC_Page controls the average postponed refresh-cycle"
> ~ above controls the upper and lower boundaries of such
> =============================================
> I've played further with a better Data-Eye based memory training *
> but it takes 40-50sec to train for no appeared success ~ nothing worth the 1min wait to post
> Soo i need to explore and play with that part more
> But the shared method, takes 2sec to post, loop through all 10x pattern tests and does test simultaneous
> Played with more Aggressor Channels and further shaping them ~ but my knowledge there is a bit lacking and time too
> Overall had a lot of fun the last two days with it ~ and why my posts are delayed
> * i should stop giving fixed ETA times i can not hold ~ really need to learn this
> 
> Played around with a flat CL9-9 set and CL8-8
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2490484
> 
> I think @domdtxdissar was asking about proofing/testing tRDWR 5 on Vermeer
> View attachment 2490485
> 
> 
> 
> There are still couple of straps issues between FCLK's , where low numbers simply refuse to boot
> Bios issues that should be resolved by ASUS and overall AMD's Memory Controller FW
> CL11-11 & CL13-13 have nonsense boundry limits on it
> CL12-12 and CL14-14 are perfectly fine
> CL8-8 is funny but there the freq straps are the limiting factor
> 
> A0 PCB is fun , but the Ballistix MAX 4000C18-19 will arrive in a week
> Either Micron Rev.B 2020 edition or B-die ~ on A3 custom PCB
> 
> Oh here are also some XMP "boots" verifying that predictions at this date are already usable and i didn't need to tinker with anything, except for 2100 FLCK
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2490486
> 
> View attachment 2490488
> 
> 
> 
> 
> 
> 
> 
> 
> 
> View attachment 2490487
> 
> 
> This is how it looks when voltages are predicted wrong and "all cores randomly crash - although it's FCLK related
> View attachment 2490489
> 
> And when i slightly adjust voltages
> View attachment 2490490
> 
> 
> 
> All above is because i promised some results after (2x) 24h timeframe & a review ~ but not on the quality i usually share (which takes 6h each to run all stability tests)
> Still exploring the big CBS menu and the possibilities & effects ~ soo bear with me please
> been working my *** off but enjoy it as the board makes fun, with an open bios ~ should've been standard on ASRock.
> Sad that they stopped carrying or their engineer left
> 
> Overall the ITX board was not special in any way - and this here has "far worse" PWM & Mosfets
> Yet even XMP can run 2067+ FCLK stable
> Yes it can be sample based - but then i wouldn't dislike the X570 Dark Hero soo much , and really have a lot of fun with this "cheap" little board
> (which in theory should have crashing thunderbolt 4 and so on ~ yet nothing , it behaves how it has to)
> Glad i didn't went Biostar as i wanted (because of the Renesas 90A stages) ~ but hey PWM on a 4 phase board, really doesn't matter for FCLK success
> 
> Testing and watching Vermeer since November
> Working on a dual CCD & fused core unlock
> Played so far with:
> Normal Unify, 2 Dark Hero's, one CH8, an X570i Aorus Pro ITX (should be free from this issue, i will verify and post a 1933 score it has to be possible),
> normal X570 Auros Pro (apparantly unaffected, soo i'll test too ~ 5950X),X570 Auros Elite (unaffected? but can't verify , lost contact the person), and couple of affected B450 MSI boards
> 
> I am looking into this issue since quite some time and follow the Board-Maker's "PR & Bios update Team"
> Many of the things they share, gets removed, and a lot of it is under NDA
> Soo at this point i'm very sure that every bios engineer is aware of this issue & they are either under NDA or remain silent to prevent sales loss
> 
> Guess i need to proof that the two Aorus Boards i have access too (5900X & 5950X) can easily run 1933 FCLK without any WHEA 19 , to strengthen the claim
> As i don't have locally boards which cause me issues, although neither of them are affected too
> Problematic


Veii, today playing a game with my "Stable configuration", several OOCTs, TM5 20 hours continues.. Extreme and 1usmus.. P95.. I had a reboot. I thoght it was a thermal issue.. maybe my little OC of my 3080.. so I left the y-cruncher for a while, more than the usual 4 iterations.. and.. I happened.. Will it be because of the OC All Cores that I am using at -24 (the lowest value stable with Core Cycler) or will it be something from the Mem OC ? I even also left 800% coverage in HCI Memtest Deluxe .. What could I test? Back to 2T, rise the VSOC.. I pass all TM5.. I wonder what could it be...


----------



## Veii

lmfodor said:


> Will it be because of the OC All Cores that I am using at -24 (the lowest value stable with Core Cycler) or will it be something from the Mem OC ? I even also left 800% coverage in HCI Memtest Deluxe .. What could I test? Back to 2T, rise the VSOC.. I pass all TM5.. I wonder what could it be...


Never really failed on thaat test , but it is CPU related
Probably Loadlines related & Powerdraw/installation related

If you where just at the limit , Mosfets heat up too much , efficiency dropped, ripple increased & you crashed
Stronger switching frequency or lower vdroop (oor subtle positive vcore and more vdroop ~ soo more headroom)
Should resolve your issue 

If you had normal voltage issues, you wouldn't pass more than 2 cycles.
Reaching thermal equilibrium takes around 30-40min, reaching heat soaking thermal equilibrium
Soo the rest could be a fridge which turned on - or switching from daylight to night-power
Just a tiny voltage drop ~ but it also can be the heat that increased ripple

Focus on this part first
If you can not resolve it, it can be problems with tREFI (tRFC) , but usually TM5 will report this with 20 cycles
25 for sure will find tREFI issues ~ soo i strongly think it's a loadline+heat issue 

EDIT:
If you want to be very sure it's not Heat+FCLK (powersuply ripple related by external source)
Loop FFT+N64 for 10 loops = 20min
that should destabilize the memory controller within 10-15min , soo 5+ loops should make it crash
If it doesn't , then VDDG voltages are fine and it was just a heat+mosfets ~ loadline, issue


----------



## Blameless

Veii said:


> Guess i need to proof that the two Aorus Boards i have access too (5900X & 5950X) can easily run 1933 FCLK without any WHEA 19 , to strengthen the claim


The claim that your samples can run 1933+ without issue isn't in doubt. I absolutely believe they do.

It's the claim that _my_ samples should run 1933+ without issues that I find dubious.

If international shipping wasn't such a chore I'd loan you this 5800X to see if you could get an entirely error free at 1933+.



lmfodor said:


> Will it be because of the OC All Cores that I am using at -24 (the lowest value stable with Core Cycler)


Core Cycler, and pretty much every stress test I've tried, will pass with flying colors at a negative offset that will cause AIDA64's cachemem benchmark to hard lock or reboot in after 3-10 back to back runs. It's my main CO test right now, because it fails faster than anything else I've found.


----------



## Nizzen

KedarWolf said:


> Strange this is advertised for Ryzen 5000 series but the QVL only has Z390, Z490 and Z590 motherboards.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> F4-4000C16D-32GTZNA - QVL - G.SKILL International Enterprise Co., Ltd.
> 
> 
> Check to see if your motherboard model is on the QVL for F4-4000C16D-32GTZNA. Trident Z Neo DDR4-4000 CL16-16-16-36 1.40V 32GB (2x16GB).
> 
> 
> 
> 
> www.gskill.com


G.skill thought Amd could fix "AGESA" to run 4000 without errors, but they failed.

You can't have a MB on the qvl list, when only a few random cpu's can run 4000 1:1

Just think about all the rage from people don't know it's the memorycontroller and the cpu' fault, that 4000 isn't working.

Smart move fram MB manufactory's to dodge the problem


----------



## DeletedMember558271

Veii said:


> @Dreamic
> While playing with AMD CBS a bit more
> I think i redesigned the Memory Training algorithm to be a bit more efficient
> 
> 
> Spoiler: Do you have access to:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I've played a bit more with getting Data-Eye mode to function fully & there is a wonderful option which 2D prints the whole Data-Eye + DQs & RTTs behavior into the ABL
> But i haven't figured out how to take out that log and make it usable
> Overall AMD has an option hidden that actually can visualize how RTTs behave, instead of having to Simulate it with PCB trace-data
> Getting access to this ABL exported path, could open the opportunity to design a fully automated memOC & calibration tool
> It's beyond my power, as i can not code - but i just want to share a bit of fancy information
> Maybe someday everyone will have access to a fully open AMD CBS
> 
> There is also a mode that puts each core from one CCD into a numa node - and a 2nd option which then does interleaving between each numa node in IOMMU
> stating from NPS0
> (interleaving across all Numa Nodes)
> NPS1 interleaving across symmetrical (if i understood it correctly ~ the nearby ones)
> NPS2, between a pair of 2 on each side
> NPS4 between 4 on each of the sides with a cache in the middle (how our Vermeer units are build - except that this is symmetrical interleaving)
> 
> Another fancy thing i remember, is that there is an option in GMI link ~ for "CAKE"
> That can modify after which % penalty autocorrection starts to trigger, and another one that controls memory write autocorrection (attempts & amount) plus defines the range it can trigger and by how much it will autocorrect
> 
> Probably the most fancy & interesting one is the flag in
> DDR4 Common Options > Dram Controller Configuration > DRAM Power Options
> "Disable Burst & Postpone Refresh"
> Programming SubUrgRef bounds - with Urgent-Reference-Limit and UrgRef-LowerBound
> "Specifies the stored refresh limit to require entering sub-urgend refresh mode & urgent-refresh mode"
> ~ pretty much being the undocumented flag before that can trigger a burst refresh and the amount of postponed refreshes
> Value 1-5 (to 6)
> ** very likely the main thing that broke my 4* tFAW set on 1201+ & core thing that makes 1* tFAW & burst tRC work positively
> 
> And this:
> DRAM tMAW & tMAC control
> 
> 
> 
> 
> 
> 
> 
> 
> I want to explore that "untested MAC" mode along with what you guys calculated for tMAW.tMAC = tRC_Page
> "tRC_Page controls the average postponed refresh-cycle"
> ~ above controls the upper and lower boundaries of such
> =============================================
> I've played further with a better Data-Eye based memory training *
> but it takes 40-50sec to train for no appeared success ~ nothing worth the 1min wait to post
> Soo i need to explore and play with that part more
> But the shared method, takes 2sec to post, loop through all 10x pattern tests and does test simultaneous
> Played with more Aggressor Channels and further shaping them ~ but my knowledge there is a bit lacking and time too
> Overall had a lot of fun the last two days with it ~ and why my posts are delayed
> * i should stop giving fixed ETA times i can not hold ~ really need to learn this
> 
> Played around with a flat CL9-9 set and CL8-8
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2490484
> 
> I think @domdtxdissar was asking about proofing/testing tRDWR 5 on Vermeer
> View attachment 2490485
> 
> 
> 
> There are still couple of straps issues between FCLK's , where low numbers simply refuse to boot
> Bios issues that should be resolved by ASUS and overall AMD's Memory Controller FW
> CL11-11 & CL13-13 have nonsense boundry limits on it
> CL12-12 and CL14-14 are perfectly fine
> CL8-8 is funny but there the freq straps are the limiting factor
> 
> A0 PCB is fun , but the Ballistix MAX 4000C18-19 will arrive in a week
> Either Micron Rev.B 2020 edition or B-die ~ on A3 custom PCB
> 
> Oh here are also some XMP "boots" verifying that predictions at this date are already usable and i didn't need to tinker with anything, except for 2100 FLCK
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2490486
> 
> View attachment 2490488
> 
> 
> 
> 
> 
> 
> 
> 
> 
> View attachment 2490487
> 
> 
> This is how it looks when voltages are predicted wrong and "all cores randomly crash - although it's FCLK related
> View attachment 2490489
> 
> And when i slightly adjust voltages
> View attachment 2490490
> 
> 
> 
> All above is because i promised some results after (2x) 24h timeframe & a review ~ but not on the quality i usually share (which takes 6h each to run all stability tests)
> Still exploring the big CBS menu and the possibilities & effects ~ soo bear with me please
> been working my *** off but enjoy it as the board makes fun, with an open bios ~ should've been standard on ASRock.
> Sad that they stopped carrying or their engineer left
> 
> Overall the ITX board was not special in any way - and this here has "far worse" PWM & Mosfets
> Yet even XMP can run 2067+ FCLK stable
> Yes it can be sample based - but then i wouldn't dislike the X570 Dark Hero soo much , and really have a lot of fun with this "cheap" little board
> (which in theory should have crashing thunderbolt 4 and so on ~ yet nothing , it behaves how it has to)
> Glad i didn't went Biostar as i wanted (because of the Renesas 90A stages) ~ but hey PWM on a 4 phase board, really doesn't matter for FCLK success
> 
> Testing and watching Vermeer since November
> Working on a dual CCD & fused core unlock
> Played so far with:
> Normal Unify, 2 Dark Hero's, one CH8, an X570i Aorus Pro ITX (should be free from this issue, i will verify and post a 1933 score it has to be possible),
> normal X570 Auros Pro (apparantly unaffected, soo i'll test too ~ 5950X),X570 Auros Elite (unaffected? but can't verify , lost contact the person), and couple of affected B450 MSI boards
> 
> I am looking into this issue since quite some time and follow the Board-Maker's "PR & Bios update Team"
> Many of the things they share, gets removed, and a lot of it is under NDA
> Soo at this point i'm very sure that every bios engineer is aware of this issue & they are either under NDA or remain silent to prevent sales loss
> 
> Guess i need to proof that the two Aorus Boards i have access too (5900X & 5950X) can easily run 1933 FCLK without any WHEA 19 , to strengthen the claim
> As i don't have locally boards which cause me issues, although neither of them are affected too
> Problematic


No I don't think I have like 95% of these options, only a couple from the PMU Training section look familiar


----------



## Nizzen

Veii said:


> Yes i do know that TM5 is not "only" enough - and it's why i always provide y-cruncher with it
> Unless i know or have supplied that these specific changes (voltages and procODT + freq changes) are rock stable already
> TM5 really only tests timings, soo i prefer it over Karhu and HCI
> It won't show if they are better (maybe if the stresstest takes less time to complete)
> But compared to Karhu & HCI , which both will fail if the CPU cores are unstable ~ TM5 barely to never fails for such
> Only Error 6 sometimes can mean external issues away from the memory by itself
> 
> That's what i think everyone of us knows, TM5 by itself is not enough
> But the work it does for itself, is enough in most cases ~ when the rest is stable
> It is complicated to phrase ~ but i do think that we all know this here
> A single TM5 is not enough, that should be known already ~ and the first post of this thread even mentions to use HCI or Karhu
> GSAT i would put on the list like TM5, purely timings related but nothing else
> 
> About the motherboard part,
> I take my time and don't just spil the beans, because the issue is big
> There is too much business deals around this what appears "little" issue
> To spill a bit - "MSI & Gigabyte" have not even one B550 board which is free from this Whea #19 trigger issue even 1mhz beyond 1900
> 
> WHEA #19 on it's own is IO related, and usually lies between the IO-Die and the Chipset
> The problem is, i am already very confident it's FW related ~ of something that is build in the boards
> Half of ASUS B550 boards are affected & 90% of the B550 ASRock ones are
> X570 at least the "damage" looks less extreme, and old X370 & X470 boards (the flagships) appear to be fine
> 
> I'm still thinking how to phrase it and collect email data that proofs my point where X semiconductor keeps fooling and messing with the boardpartners
> Although i do think that every of the board partners knows this issue and AMD does know it very well
> Just money is into play, and the suppliance deal they made ~ is a far bigger number than we "enthusiasts" who have the issue "only on higher FCLK"
> Where the issue can also be pushed as "PCIe 4.0 crashes beyond 2000 FCLK ~ an architectural limit"
> 
> All these USB fixes where only a sideproduct to fix a bad behaving design, which sadly is build in close to every mainboard
> I played with the dark hero , and had nothing but WHEA 19 problems
> Autocorrection and other little annoying Vermeer things exist, but this is a bigger issue ~ soo i really take my time to gather enough information , before making such "brand-shaming" post
> Notebooks can also be affected , as this issue even 3 months after discovery by board-partners, is yet not fixed in the hidden
> We all (well most) still suffer from "a 1900FCLK limit" ~ one that has neither FCLK instability nor MCLK instability or CPU Core instability as a base
> It shows as random unknown kernel error apparently by the IO
> My ProArt purchase just confirmed my long going theory ~ and it makes now more sense
> But because of all the hate that can come out of this post, i still take my time to make it more analytical without putting any random semiconductor into target/fire
> 
> I know what you want to tell me, but there are really many issues that can cause WHEA #19
> Sadly one of these is a major board design problem users can do nothing about it except refund or bios mod & erase the module fully
> Deactivating it does nothing at all, it still is loaded and triggers WHEA's
> Keeping it hidden will never resolve the issue, and putting it easily out there will brand-misstrust a major player in the supply chain + also push the fire back to me for whatever excuses/talking out ~ points they find


Is there any source of this hardware problem, that people can read more about it?

Or is this problem "silenced" from all MB manufactorys and AMD?

I'd love to read more about it


----------



## lmfodor

Veii said:


> f you want to be very sure it's not Heat+FCLK (powersuply ripple related by external source)
> Loop FFT+N64 for 10 loops = 20min
> that should destabilize the memory controller within 10-15min , soo 5+ loops should make it crash
> If it doesn't , then VDDG voltages are fine and it was just a heat+mosfets ~ loadline, issue


Yes, maybe I have to much swtiching frecuency for the vSOC and the memories.. I'm using LLC4.. Ultra Fast response instead of FAST. I will fix that first and the I will try that loop of FFT+N64 when a new TM5 1usmus (30 cycles) finished!

Thanks!!!!


----------



## DeletedMember558271

Blameless said:


> Core Cycler, and pretty much every stress test I've tried, will pass with flying colors at a negative offset that will cause AIDA64's cachemem benchmark to hard lock or reboot in after 3-10 back to back runs. It's my main CO test right now, because it fails faster than anything else I've found.


I wish it was that simple for me, my only indication of instability is my PC is on 24/7 and I might get a idle reboot overnight every month and a half with event viewer pointing to an APIC ID for me to lower...
If I ever have a rare game crash, I have to wonder if it was just the game or my system instability, no good or fast way to actually test Curve Optimizer stability at least for me as far as I know.
Just kinda accepted it might be unstable and if it ever makes itself obvious enough, I'll lower it.
All I did with my good old 4690k was ran overnight stress tests at a static frequency and vcore and if didn't BSOD you were good forever, simpler times. Can't really test these new CPU's that are super dymamic with voltages and frequency, benchmarks and stress tests are limited in the range they can test. It's like oh if you're stable at this load, at this frequency, with this voltage, at these temps, that this test is doing right this second, yea you're stable for that specifically.. pretty useless.

Nvidia has a little automated thing that tries to stress each point on its curve, OC Scanner or whatever, probably doesn't work very well but this reminds of that. We need like significantly better versions of things like that.
Imagine trying to stress test RAM if everything was dynamic boosting, frequency and voltage, what nightmare

And then AMD is always possibly changing and improving like they did before with Curve Optimizer big time, makes me always wonder if it's maybe been tuned more and I can squeeze more out of it every time there's a new AGESA. Then can go literally a month and a half of being on 24/7 before a reboot happens from being too low...


----------



## Blameless

Could definitely use some better tools for validating modern CPUs. Even after getting what I feel is a pretty good methodology down, I'm spending days or weeks to wind up with something a few percent better than stock.


----------



## DeletedMember558271

Blameless said:


> Could definitely use some better tools for validating modern CPUs. Even after getting what I feel is a pretty good methodology down, I'm spending days or weeks to wind up with something a few percent better than stock.


Arguably a good thing though, I think. Unless it's just your specific sample, means AMD is doing a good job of pushing things to the limit already.
There's just too many variables to test with something that doesn't have static frequency and voltage, idk how you test every frequency and voltage combination possible, every condition and scenario accounted for


----------



## Taraquin

I have a 5600X, Gigabyte B550m S2H, I used 1.2.0.1A for a month, now on 1.2.0.2 for 2 weeks. I have never had a whea error and I have run 4000/2000 all the time, 4066/2033 also works without wheas, but requires quite a bit more soc and iod voltage with minimal gains. Currently running 1.1v soc, 1.02v iod, 860mv vddp and ccd. B-die at 16-16-15-32-47, 282 tRFC, 2T, rest tuned tight, 1.44V ram. 

If this issue should be present on all Gigabyte B550 running above 3800/1900, why have I seen no whea for 6 weeks?


----------



## mongoled

Taraquin said:


> I have a 5600X, Gigabyte B550m S2H, I used 1.2.0.1A for a month, now on 1.2.0.2 for 2 weeks. I have never had a whea error and I have run 4000/2000 all the time, 4066/2033 also works without wheas, but requires quite a bit more soc and iod voltage with minimal gains. Currently running 1.1v soc, 1.02v iod, 860mv vddp and ccd. B-die at 16-16-15-32-47, 282 tRFC, 2T, rest tuned tight, 1.44V ram.
> 
> If this issue should be present on all Gigabyte B550 running above 3800/1900, why have I seen no whea for 6 weeks?


If you are on a Windows version 1909 or lower, you have your answer.

Otherwise be very happy you won the silicon lottery

 

Just to be clear, peeps here are talking about WHEA warning which has error number 19 in the event logs


----------



## Blameless

Dreamic said:


> Arguably a good thing though, I think. Unless it's just your specific sample, means AMD is doing a good job of pushing things to the limit already.


Oh, my sample has some oddities (one exceptionally bad core that cannot take any negative offset at all and needs a positive one with any use of scalar or clock increase), but AMD has certainly minimized the available margins.



Dreamic said:


> There's just too many variables to test with something that doesn't have static frequency and voltage, idk how you test every frequency and voltage combination possible, every condition and scenario accounted for


Don't need to test everything, just the extremes...the odds of a middling load in the mid part of any curve having issues when idle, heavy, and rapid transient tests all pass seems rather remote and I've yet to see anything suggestive of problems near the middle of any curve (though I can't categorically rule out the possibility). Heavy loads are easy enough, it's the rapidly shifting transient ones that are tricky. One of the reasons Cachemem is so handy is because it will hit the cores individually and together with a light load that maxes out the frequency of the cores. It's not perfect, but it really helps isolate issues with too much negative offset.


----------



## Taraquin

mongoled said:


> If you are on a Windows version 1909 or lower, you have your answer.
> 
> Otherwise be very happy you won the silicon lottery
> 
> 
> 
> Just to be clear, peeps here are talking about WHEA warning which has error number 19 in the event logs


I'm on 20H2.


----------



## Nizzen

Taraquin said:


> I have a 5600X, Gigabyte B550m S2H, I used 1.2.0.1A for a month, now on 1.2.0.2 for 2 weeks. I have never had a whea error and I have run 4000/2000 all the time, 4066/2033 also works without wheas, but requires quite a bit more soc and iod voltage with minimal gains. Currently running 1.1v soc, 1.02v iod, 860mv vddp and ccd. B-die at 16-16-15-32-47, 282 tRFC, 2T, rest tuned tight, 1.44V ram.
> 
> If this issue should be present on all Gigabyte B550 running above 3800/1900, why have I seen no whea for 6 weeks?


Do you have some performance numbers in like Aida?

My old 5900x can't go over 3600mhz without WHEA errors. My new 5950x can run 3866 without errors. Over 3866 it's throwing WHEA errors.
Using Dark hero.

There is no doubt that the cpu's has different bins on the memorycontroller


----------



## Taraquin

Nizzen said:


> Do you have some performance numbers in like Aida?
> 
> My old 5900x can't go over 3600mhz without WHEA errors. My new 5950x can run 3866 without errors. Over 3866 it's throwing WHEA errors.
> Using Dark hero.
> 
> There is no doubt that the cpu's has different bins on the memorycontroller











This is my best score with all core 4.8GHz.


----------



## Blameless

Have been progressively raising SoC and VDDG IOD while reducing VDDG CCD and, in conjunction with the SMU DPM tweak, I'm now down to 1-2 WHEA 19 corrected interconnect errors on boot at 1933 FCLK. Last few errors are proving problematic though as I'm at the lower limit of stability for VDDG CDD.

Edit: Three error free boot cycles in a row. Ended up having to bump VDDG CCD back up to 0.9v. Also running 0.86v CLOD VDDP, 1.04v VDDG IOD, 1.1v SOC, and 1.88v CPU VDD 1.8.

Edit2: memory benchmarks cause tons of error 19s and repeatedly reset my USB ports.

Edit3: able to keep boot error free if I maintain at least a 150mV differential between CCD and IOD, but I cannot get anything resembling a load to stop throwing craptons of errors or stop causing USB issues, even with vSOC up to 1.2v, which is as far as I am willing to go for 1933.


----------



## jomama22

Blameless said:


> Have been progressively raising SoC and VDDG IOD while reducing VDDG CCD and, in conjunction with the SMU DPM tweak, I'm now down to 1-2 WHEA 19 corrected interconnect errors on boot at 1933 FCLK. Last few errors are proving problematic though as I'm at the lower limit of stability for VDDG CDD.
> 
> Edit: Three error free boot cycles in a row. Ended up having to bump VDDG CCD back up to 0.9v. Also running 0.86v CLOD VDDP, 1.04v VDDG IOD, 1.1v SOC, and 1.88v CPU VDD 1.8.
> 
> Edit2: memory benchmarks cause tons of error 19s and repeatedly reset my USB ports.
> 
> Edit3: able to keep boot error free if I maintain at least a 150mV differential between CCD and IOD, but I cannot get anything resembling a load to stop throwing craptons of errors or stop causing USB issues, even with vSOC up to 1.2v, which is as far as I am willing to go for 1933.


Personally never had any issues with USB dropouts or stability issues with hundreds of wheas at 2000fclk. All benchmarks improve as well. 

Literally just pesky whea 19s. 

Back in the day, some bios's had a setting to actually disable all whea error reporting. Would be fun if that was still around lol.


----------



## craxton

Veii said:


> ID 20 in the database has nothing attached to it


yea i know its not got anything attached, its just a BSOD to which,
the ONLY time ive had it is when my CO was off by a small (offset in core voltage)
once i upped it a tad, i had nomore BSOD or id20..
thus why i made claim about it being voltage related



Veii said:


> B550 , i haven't seen one MSI board which doesn't have this hardware issue


hmmm maybe i got the "golden board from MSI" lol



Veii said:


> but i don't think there is even one who managed to get 1933 running without WHEA #19 on it


share me some timings that work for 1933 4x8 and ill let ya know 
but from the fact i think itll not have issues ill give it a shot anyhow.



Taraquin said:


> If this issue should be present on all Gigabyte B550 running above 3800/1900, why have I seen no whea for 6 weeks


have you disabled alot of windows services? or deleted folders etc and changed ownership of said folders?


----------



## craxton

hmm, id have to say this makes me happy considering without CO
or even a neg offset its 300 lower...
{EDIT}<this is running 1933 3866 btw>{EDIT}









will run single core test and update....to impatient not to share. (NOT A CTR USER)
EDIT SINGLE CORE


----------



## Taraquin

craxton said:


> yea i know its not got anything attached, its just a BSOD to which,
> the ONLY time ive had it is when my CO was off by a small (offset in core voltage)
> once i upped it a tad, i had nomore BSOD or id20..
> thus why i made claim about it being voltage related
> 
> 
> hmmm maybe i got the "golden board from MSI" lol
> 
> 
> share me some timings that work for 1933 4x8 and ill let ya know
> but from the fact i think itll not have issues ill give it a shot anyhow.
> 
> 
> have you disabled alot of windows services? or deleted folders etc and changed ownership of said folders?


No, haven't done any of that.


----------



## craxton

Taraquin said:


> No, haven't done any of that.


hmm, i had to which i thought i had messed around to where 
my WHEA errors wouldnt log to which extent i completely remade an entire new drive 
from scratch and well, lost all the stuff i had before, but i still dont have WHEA error...

even running 1933/3866 as i am now...?


----------



## Taraquin

I ran 3800\1900 the first week on agesa 1.1.0.0, no wheas, after upgradding to 1.2.0.1A I ran 3866\1933 for a while, then 3933\1966 for a while, no wheas then either.


----------



## PJVol

jomama22 said:


> Back in the day, some bios's had a setting to actually disable all whea error reporting. Would be fun if that was still around lol.


Don't see why it can't be done just writing directly to MCA_CTL_PIE and MCG_CTL from kernel space


----------



## craxton

Taraquin said:


> This is my best score with all core 4.8GHz.


looks more like 4.9/4875 lol
i suppose i could test a 4.9ghz all core and see if my numbers match close to where you lay
then again, im running 4x8 SR to where you seem to be 2x8... why 2T btw? 
should be easy enough to get 1t stable GDM off...what voltage are you running for
this all core OC?



jomama22 said:


> Back in the day, some bios's had a setting to actually disable all whea error reporting. Would be fun if that was still around lol.


i mean, couldnt one just change ownership, of the folder where WHEA is at?

or simply change ownership and delete the logger all together? yes, im aware that sfc/ scannow 
might repair it at somepoint, but i dont think it would fix ownership privs....


----------



## jomama22

PJVol said:


> Don't see why it can't be done just writing directly to MCA_CTL_PIE and MCG_CTL from kernel space





craxton said:


> looks more like 4.9/4875 lol
> 
> i suppose i could test a 4.9ghz all core and see if my numbers match close to where you lay
> 
> then again, im running 4x8 SR to where you seem to be 2x8... why 2T btw?
> 
> should be easy enough to get 1t stable GDM off...what voltage are you running for
> 
> this all core OC?
> 
> 
> 
> 
> 
> i mean, couldnt one just change ownership, of the folder where WHEA is at?
> 
> 
> 
> or simply change ownership and delete the logger all together? yes, im aware that sfc/ scannow
> 
> might repair it at somepoint, but i dont think it would fix ownership privs....
> 
> 2490556



If this method would prevent the mobo/cpu from sending an interrupt I'd be for it. But so long as it's blasting an interrupt, I'd be hesitant as to what difference there would be compared to having it flood with errors.


----------



## Blameless

jomama22 said:


> Personally never had any issues with USB dropouts or stability issues with hundreds of wheas at 2000fclk. All benchmarks improve as well.
> 
> Literally just pesky whea 19s.
> 
> Back in the day, some bios's had a setting to actually disable all whea error reporting. Would be fun if that was still around lol.


This specific CPU is the first time I've seen USB issues anything like this. It's like the USB controller on the SoC or the UMI link to the chipset is the first part of the chip to be affected. There are no memory errors at all and no loss of CPU or memory performance. Even the GPU and main NVMe slot are unaffected...but anything attached via USB or the chipset gets super flaky.

Anyway, if there are errors being reported by the CPU, even correctable ones, I'd like to know about it (and resolve them, if possible), as they could have stability implications. If it was a false alarm or something I wanted to filter out for testing purposes, I can do that in event viewer, or disable logging at the OS level.


----------



## PJVol

craxton said:


> looks more like 4.9/4875 lol


I think it indeed is, just 4800 with 101,875 bus clock )) or more like 4850 / 100.8


----------



## ManniX-ITA

Works for me, hope it works for you too...

Alpha version, no warranties, use at your own risk blah blah blah

It's a system service, will start at boot (or can be manually started) and will disable WHEA error reporting.
Non intrusive and non destructive.
You will loose WHEA error reporting for probably more than just WHEA 19.

I'm testing now my precious main install at FCLK 2000.
Got a reboot in idle at FCLK 2066 sigh sob...

DPC Latency with Latencymon is quite awesome.

Download:





WHEAService_1.0_alpha.zip







drive.google.com





There's both a "portable" version that can be installed/uninstalled via a batch file and a classic installation package.

Will publish tomorrow on Github if someone is confirming that works on other systems too.



lmfodor said:


> And how did you finish with the latency tests?


Sorry was busy and focusing on FCLK 2000+


----------



## Taraquin

craxton said:


> looks more like 4.9/4875 lol
> i suppose i could test a 4.9ghz all core and see if my numbers match close to where you lay
> then again, im running 4x8 SR to where you seem to be 2x8... why 2T btw?
> should be easy enough to get 1t stable GDM off...what voltage are you running for
> this all core OC?
> 
> 
> i mean, couldnt one just change ownership, of the folder where WHEA is at?
> 
> or simply change ownership and delete the logger all together? yes, im aware that sfc/ scannow
> might repair it at somepoint, but i dont think it would fix ownership privs....
> View attachment 2490556


It was set at [email protected], dunno why aida reads wrong sometimes. My ram is a ****ty bin, and the gpu blows hot ait through fan no 2 straight at the ram so anything above 1.45V spits out errors, but getting a new 3060ti or 3070 at a okay price is impossible atm.


----------



## ManniX-ITA

craxton said:


> but this is something that im sure ALOT will thank, and hate about as
> well, no need to explain but some cant let go that they have errors period.
> (Id be one of those if i were seeing WHEA out the arse)


I trust Veii analysis that these errors have nothing to do with a fault in the CPU
That's why I released it and risking my main install as well 
Error reporting is beautiful and should be always taken into consideration. When it works.
If it's just messing with my system, I can live with it disabled
Loads of y-cruncher cycles and you know if something is wrong or not....


----------



## Blameless

ManniX-ITA said:


> I trust Veii analysis that these errors have nothing to do with a fault in the CPU
> That's why I released it and risking my main install as well
> Error reporting is beautiful and should be always taken into consideration. When it works.
> If it's just messing with my system, I can live with it disabled
> Loads of y-cruncher cycles and you know if something is wrong or not....


If the errors weren't representative of something, they wouldn't cease to appear below a certain FCLK.

I'm also completely y-cruncher stable in a CPU that is so bad I think it may be legitimately defective.


----------



## craxton

ManniX-ITA said:


> Loads of y-cruncher cycles and you know if something is wrong or not..


ill admit when i came here, i had NO IDEA what y-cruncher was, or where 
to even begin tuning ram, let alone (MSI easy overclocking working out sometimes 
to which, the ram oc section usually working fine so i just always went with it) 
ive not had any crashes since lowering to 50mv core voltage and running -20 CO all core
to which voltage doesnt exceed 1.43 in ANY hardcore tests. (still just running motherboard PBO values
with X4 scaler, and LLC 2 tho ( which is what i needed ) still have vdroop but from the looks of things, 
its perfectly stable...until i go messing again?



ManniX-ITA said:


> I trust Veii analysis that these errors have nothing to do with a fault in the CPU


100% agree, but im still wondering if somehow my WHEA logger only records BSOD crashes?
or -19 as 20 and 19 are the ONLY two ive had EVER and 19 only 1 time 
which was before setting LLC 2 and getting CO tuned correctly. 
20 was around the same issue, would BSOD while not having enough voltage
but cant say 100% sure, just not had another since getting CO 100% stable.

(i did drop CLDO_VDDP to 900 from 910 since then as well, so that may have helped?)



ManniX-ITA said:


> Error reporting is beautiful


.... its sure colorful when you task kill thats for sure lol


----------



## ManniX-ITA

Blameless said:


> If the errors weren't representative of something, they wouldn't cease to appear below a certain FCLK.


For sure are representative of something; but is this something meaningful?
I'm running at FCLK 2000 on my main install and I've benched it and stressed it on the benching install.
No performance degradation, no stability issues. So far at least, the main install is a terrible test bench 

The only drawback is loosing the legitimate WHEA errors.
But that's a problem that AMD has to solve not me.
AMD keeps being lazy and underperforming which is a shame cause these are great processors.
You are willing to risk this is the price to pay.
The reward is higher FCLK which can be a nice uplift in performances in specific scenarios.
And you can run your precious B-die kits at amazing speeds


----------



## lmfodor

Nizzen said:


> Do you have some performance numbers in like Aida?
> 
> My old 5900x can't go over 3600mhz without WHEA errors. My new 5950x can run 3866 without errors. Over 3866 it's throwing WHEA errors.
> Using Dark hero.
> 
> There is no doubt that the cpu's has different bins on the memorycontroller


Hi Nizzen, what a strange thing, I have a 5900x with a CrossHair Hero Wifi, and I bought a month ago a new set of memories 3800CL14 2x16 Dual Rank, and with the XMP profile or overclocking it. I never had WHEA error 19 but if I increase the FCLK to 1933 Immediately triggers WHEA 19, so I think that is something relates to hardware (I/O) that AMD will fix it. I hope so! 

Ps: I tried literally all BIOS available. Even the older version without curve optimizer. 


Sent from my iPhone using Tapatalk Pro


----------



## Yuke

ManniX-ITA said:


> I trust Veii analysis that these errors have nothing to do with a fault in the CPU
> That's why I released it and risking my main install as well
> Error reporting is beautiful and should be always taken into consideration. When it works.
> If it's just messing with my system, I can live with it disabled
> Loads of y-cruncher cycles and you know if something is wrong or not....


Any specific test that you loop im y cruncher?


----------



## lmfodor

Veii said:


> Never really failed on thaat test , but it is CPU related
> Probably Loadlines related & Powerdraw/installation related
> 
> If you where just at the limit , Mosfets heat up too much , efficiency dropped, ripple increased & you crashed
> Stronger switching frequency or lower vdroop (oor subtle positive vcore and more vdroop ~ soo more headroom)
> Should resolve your issue
> 
> If you had normal voltage issues, you wouldn't pass more than 2 cycles.
> Reaching thermal equilibrium takes around 30-40min, reaching heat soaking thermal equilibrium
> Soo the rest could be a fridge which turned on - or switching from daylight to night-power
> Just a tiny voltage drop ~ but it also can be the heat that increased ripple
> 
> Focus on this part first
> If you can not resolve it, it can be problems with tREFI (tRFC) , but usually TM5 will report this with 20 cycles
> 25 for sure will find tREFI issues ~ soo i strongly think it's a loadline+heat issue
> 
> EDIT:
> If you want to be very sure it's not Heat+FCLK (powersuply ripple related by external source)
> Loop FFT+N64 for 10 loops = 20min
> that should destabilize the memory controller within 10-15min , soo 5+ loops should make it crash
> If it doesn't , then VDDG voltages are fine and it was just a heat+mosfets ~ loadline, issue


Today the same thing happened to me playing a game with my son, it seems to be overheating, because at 3 hours we received a BSOD 41 and then he started it again at 15 minutes another, which I think is what Veii said about some Mosfet overheating or a bad LLC calibration I still can't figure out what it could be, but in the memory controller seems to tolerate all the load because I let Y-cruncher test 14 and 16 run for 3 hours and no errors, which is what he recommended me to do. I also ran OOCT Extreme Large, TM5 1usmus for 4 hours to re-validate if some timings might be wrong, but nothing. I don’t think it is CPU because with the AIO the temperature in games does not rise much, but there is something that causes me the BSOD error 41 

How should I configure the LLCs, both of the CPU and the vSOC so that it does not have vdroop? for example I always had the LLC of the CPU in car, perhaps there is the error. Should it be 3, with a switching frequency of 500? I have the VSoc in 500, LLC 4 and then the memories in extreme and the switching frequency of 400

My PBO is all core -24 and now I lowered to -20.. Could you give me some advises to try? For instance, a little positive Vcore offset would help, -+ 0,03/0,06V? Or should I try LLC 2 for both CPU and VSOC and leave sw frequency to 500?

I would appreciate your guidance [emoji4]



Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

Yuke said:


> Any specific test that you loop im y cruncher?


I think Veii mentioned at least VST in loop 4-5 times.
But I always select 6 for "Enable All Tests".
4-5 cycles is rock solid, 12 cycles should be safe as Fort Knox


----------



## Blameless

ManniX-ITA said:


> For sure are representative of something; but is this something meaningful?


That depends on use case, but in general, I think so. These errors generally show up before obvious problems are present, but not always, and I've rarely had a setup that had even a single corrected bus/interconnect error reported where I couldn't find some problem with it that couldn't be resolved by reducing FCLK or adjusting voltages. The sole exception has been a very borderline case where the errors were extremely intermittent, and I'm glad I got the WHEA errors so I knew to back off before something went wrong.



ManniX-ITA said:


> I'm running at FCLK 2000 on my main install and I've benched it and stressed it on the benching install.
> No performance degradation, no stability issues. So far at least, the main install is a terrible test bench


Have you specifically tried to test for idle/transient errors? Used the system for protracted periods of general use? Tested all available I/O to it's limits?

I certainly believe there are systems that will do 2000+ FCLK stable, but I'm extremely doubtful that there are systems reporting a significant numbers of bus/interconnect errors, even correctable ones, where I couldn't eventually find a problem that manifests elsewhere. And I _want_ to see these errors, so I know to look for their underlying cause...because there is one, because these are legitimate errors.



ManniX-ITA said:


> You are willing to risk this is the price to pay.
> The reward is higher FCLK which can be a nice uplift in performances in specific scenarios.
> And you can run your precious B-die kits at amazing speeds


A trade off that's surely worth it for some, but there is a big difference between errors not being important for a benching or gaming setup, and errors not being legitimate or not actually existing. My systems do work and handle data that I am not willing risk for a measly few percent of performance.


----------



## lmfodor

ManniX-ITA said:


> For sure are representative of something; but is this something meaningful?
> I'm running at FCLK 2000 on my main install and I've benched it and stressed it on the benching install.
> No performance degradation, no stability issues. So far at least, the main install is a terrible test bench
> 
> The only drawback is loosing the legitimate WHEA errors.
> But that's a problem that AMD has to solve not me.
> AMD keeps being lazy and underperforming which is a shame cause these are great processors.
> You are willing to risk this is the price to pay.
> The reward is higher FCLK which can be a nice uplift in performances in specific scenarios.
> And you can run your precious B-die kits at amazing speeds


Hi Mannix, I gave up with the FCLK 1933 or above. I think that Veii is right. There’s something in the I/O that need to be fixed. Maybe we can lower some errores with the DPM tweak, buy in my case the WHEA 19 is still there.. so I’ll wait for some new firmware or I’ll wait for the X570s. A friend is going to give me a dark hero that he doesn’t use, so I will test more than anything if I can achieve a better OC in 3800/1900 and see if the VRMs help, at least to test. The mobos are the same, but I remove the doubt of the VRMs .. I have no expectation that this can be solved by us, only AMD and the manufacturers. 

And what happens to me now with a game pays me back to before, sometimes having a bad OC, in my case with LLCs or overheating of mosfets shows that for benchs everything works very well but to play, with GPU temperature , something is affecting him. I think it's more of an LLC issue, because I have good cooling, maybe I can put some thermal pads on the mosfets, right? I must have amgun vdroop .. could it be the PSU? 850 should be enough for a 3080 TUF and the OC of my 5900 not? Thank you!


Sent from my iPhone using Tapatalk Pro


----------



## lmfodor

ManniX-ITA said:


> I think Veii mentioned at least VST in loop 4-5 times.
> But I always select 6 for "Enable All Tests".
> 4-5 cycles is rock solid, 12 cycles should be safe as Fort Knox


Yes! See my yesterday post. After 8 iterations one test failed. But I did it for the BDOD 41 while gaming.. 



Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

Blameless said:


> That depends on use case, but in general, I think so. These errors generally show up before obvious problems are present, but not always, and I've rarely had a setup that had even a single corrected bus/interconnect error reported where I couldn't find some problem with it that couldn't be resolved by reducing FCLK or adjusting voltages. The sole exception has been a very borderline case where the errors were extremely intermittent, and I'm glad I got the WHEA error before something went wrong


In general I agree as well in general; this case is peculiar.
I wouldn't definitely recommend this workaround to anyone doing vital stuff with its PC, only overclockers willing to risk.
The performance uplift is not that much to justify a costly remediation.



Blameless said:


> Have you specifically tried to test for idle/transient errors? Used the system for protracted periods of general use? Tested all available I/O to it's limits?


Absolutely not as I said 
Going to find out now using my main daily install.
FCLK 2067 MHz was stable for benching and proven unstable on the main.



Blameless said:


> I certainly believe there are systems that will do 2000+ FCLK stable, but I'm extremely doubtful that there are systems reporting a significant numbers of bus/interconnect errors, even correctable ones, where I couldn't eventually find a problem that manifests elsewhere. And I _want_ to see these errors, so I know to look for their underlying cause...because there is one, because these are legitimate errors.


Me as well, when I was tuning the other day the CO counts got some WHEA 18 and understood something was wrong.
But there are also other tools like y-cruncher and OCCT to check stability.



Blameless said:


> A trade off that's surely worth it for some, but there is a big difference between errors not being important for a benching or gaming setup, and errors not being legitimate or not actually existing. My systems do work and handle data that I am not willing risk for a measly few percent of performance.


It's indeed a matter or risk; if you do important stuff with your data, definitely it's not for you.


----------



## Blameless

ManniX-ITA said:


> But there are also other tools like y-cruncher and OCCT to check stability.


These have their limits, especially when instabilities often show up at lower loads, rather than higher ones. And while programs like these are great memory and memory controller tests, and pretty good CPU core/cache tests, not every issue with FCLK or bus/interconnect errors presents as a problem with these subsystems.

Finding tools or procedures for these tools that that can adequately test other subsystems, or test low/transient loads, is much trickier.


----------



## ManniX-ITA

Blameless said:


> Finding tools or procedures for these tools that that can adequately test other subsystems, or test low/transient loads, is much trickier.


Yes, very often despite all the testing and stressing the only way to uncover instabilities is a long gaming and watching Youtube with Chrome


----------



## Veii

Good Job @ManniX-ITA , thank you for making it 
Maybe attach it to your signature , soo it's easier findable - i'll give it a shot on boards/users systems i know that fail

2067 is not thaat hard, but maybe if my older message was viewed (the picture spam in the spoiler section)
it needs exquisite voltages and low procODT - also a big difference between CCD and IOD
High FCLK tends to mess with the CCDs, while high SOC might make the whole substrate very sensitive and will put FIT triggerhappy to autocorrect and slow down things (if something little is off)
But higher SOC generally helped a lot - where VDDG then auto adjusted and load balanced it ~ nevertheless what you put in (as long as uncoreOC is disabled)

The "way" to get high FCLK to work, is on one hand to lower every voltage possible - this includes procODT too
on the other hand supply enough to the IO-Die and then slowly bring up everything higher with SOC
a high CCD freq will require more SOC , but tooo much SOC and high FCLK interconnect speeds will destabilize and crash the cores in the CCD
Soo you need as low CCD as possible

Low CCD made it look like it triggers sound crackling and usb issues, but that is because VDDG keeps load balancing between CCD and IOD
IO issues continue to relate to procODT and IOD - they have nothing to do with the CCD voltages. Suure the CPU controls somewhere the "cleanness and consistency" of the audio decoding
Aside from the D/A chip on the board ~ but this goes back then to the "Signal Integrity" Topic , which is purely procODT related
Soo lower CCD , you will notice when it's too low ~ then uplift everything with subtle more SOC voltage
Also keep Standby voltage low

About the 1.8v Line
This continues to be a semi mystery
It is helpful when you SOC and IOD have a perfect 40mV *GET* distance, and nomatter of the load, this distance doesn't drop to 38mV
But if it jumps to 42mV it can "desync" and destabilize
Also if you max out switching frequency and loadlines, the ripple will get too worse and SOC won't be clean anymore, at all ~ a balance thing, i like to use loadlines here

CPU voltage, is up to users sillicon
You can drive it with as little loadline as possible, or as much loadline as possible
Signal Integrity is king here ~ soo give your best to lower ripple/increase signal integrity as best as you can
This means, go lower with procODT (use all methods possible with CAD_BUS and RTT to help you for such)
Go the lowest on cLDO_VDDP you can run (900mV is fine, but i've seen people at 2000 run 840 and lower)
Go with the lowest VDDP Standby Voltage or CPU VDDP as possible ~ whatever is exposed and whattever it is named

VDD 1.8v line, usually holding it at 1.83v was beneficial to a little degree
1.8V is fine, lower had no benefits to this date ~ higher did only destabilize if you went with the "low current, high input SOC" path
If you go with the "IOD to SOC = perfect 40mV" - then 1.8v line does help till 1.9v, somewhere along 1.84-1.86 is the sweetspot , higher can already create instability

Y-cruncher will crash, it is still able to destabilize Vermeer very well after some time ~ but give it time, as Vermeer does autocorrect and adapt to errors + adjust internal GMI link speeds to keep stability up
OCCT Extreme AVX2, 1h ~ remains a good benchmark
However it differs from y-cruncher, it is able to freeze Vermeer's Autocorrection . Whatever it does, Vermeer is not able to autocorrect that well for it
But OCCT will also crash on any little FCLK or MCLK issue ~ as it is a Linpack Type of test after all. Soo be sure the whole y-cruncher test suite is stable for 3+ cycles. Make it 4 

EDIT:
If you see FCLK crashing because of "too much IOD or too much CCD"
Bring it down - and compensate with higher input voltage on SOC
That should make it stable, as it mostly crashes on "overcurrent" by bad signal integrity - just that the colour substrate change can need more SOC overall
This should make it stable ~ but generally, the lower SOC the better , as it strongly eats into the powerbudget (EDC) which you can notice on one of the pictures after 1933Mhz 
EDIT 2:
Keep in mind procODT has upper and lower bonds of SOC stable'ness
It can be that you either need to decrease or increase procODT - on SOC increase (decrease on SOC decrease)

@Nizzen about the issue, sadly i'm the single person aside from board makes who noticed it. Very sure every board-partner & AMD is aware of the issue with Realtek & surely know their big stock-up amount & investment + trust
Yes, i'll spill the beans but decided to take another route


Spoiler



I could, brandshame them if i make a big announcement and focus on putting them into target on several places ~ including Reddit and for bigger media outlets
~ but i have personal issues not to think that they deserve it
Don't get me wrong, they treated each of the boardpartners like ****, they absolutely deserve the brandshame and target-fire for whoever took that wrong direction, with this big flaw
And alone that they refuse to fix it ~ but every boardpartner and AMD have to bent down to them just so they won't lose a huge amount of sales.
It's a long going fight and the only "source" for this are email exchanges between PCB engineers and the Realtek RND department. The stupid excuses that are given and the lack of work that is provided, having AMD to force in redoing & applying soo many unstable patches ~ just to deal with their stubborn refusal to assist and fix their own design flaw.
I'm mad about them. Respect them alot the last 6-8 years for how they behaved in the wireless and linux driver market.
Respected them with the lower prices made and helped notebooks and PCBs in general costing less. Respected them a lot again for their Unix/Linux driver support staying opensource (kinda) and assisting + helping the Arch Linux community have more stable drivers.

But this here is a disaster








B550 VRM DB sheet


시트1 Feedback : [email protected] Don't requst permission / You can leave comment :) Product,Price,Config,Phase Type,VRM Type,MOSFET (Vcore),PWM Controller,LAN,Wireless LAN,Audio ASUS ROG STRIX B550-XE Gaming WiFi,$ 330,14+2,Dual-Output,DrMOS,TI X95410RR 90A,ASP1405i (7+1),Intel I225-V (2.5...




docs.google.com




Take a look here, tell me how many I225-V boards exist . . .
Madness shouldn't rule over my public relationship with them, and i haven't received any bribe to refuse to talk.
But i'm disappointed who in their department rules this nonsense. Why do you treat board partners like **** when they multiple times try to talk with you and fix it for everyone
Is money that much more important than the huge userbase who uses "by your made mistake" all these buggy boards.
At least they went out of their way after 3 months back and forth blaming - to fix some of the issues where each of their ports was force restarting attached Lan-Splitters and Routers.
Probably just to ensure themself to be somewhat sue-free, and push a damage prevention math.

All these usb fix agesa and of course hidden ethernet fixes, driver rewrites (10+)
Windows enforced update pushes and FW injections.
Shady work, but nobody would notice anything ~ and probably for the brandstatus of this semiconductor ~ "shouldn't notice anything"
But it reached hilarious levels already, and nothing changes
Surely board partners are under NDA, in hope that nice Realtek guy finally fixes their broken mess of a FW
And the saddest thing ~ you can't even skip the issue. It still causes problems if nothing is plugged in or even "ACPI disabled". it still triggers crashes and kernel "reboot reports"
It still causes SATA drive crashes, by the experimental Chipset interconnect patches, that where supplied. And all for what ~ because dear semiconductor sits on their cooperate stool , stating that nobody held their given Schematics and they are not in fault for unstable controllers ~ and surely not in fault for letting close to everything reboot or crash by simply connecting it with it. . . .


But yes, nobody wants to hear that and thinking about it for more ~ it's not the path to take
Suure it would help and wake up some of these stubborn people in the industry, but it would put me on target and is kind of shameful having to take such path.
Also would be against all of the Board-Partners who at least "try" to do something , in comparison to Semiconductor who doesn't even bother to cooperate.

Yes AMD tries too, sure many of it is loss-of-sales prevention & damage prevention, but at least "they try" ~something~
And this "trying" is more appreciable - weighting out the damage and childish nonsense that has been going on between them in the hidden.
Soo i should appreciate this "trying" of resolving something and not take the madman path not only damaging semiconductors reputation, but putting every boardpartner also in fire
It is a bad idea to take that path ~ as again, the person to blame in the industry is someone that are not the board partners (not fully)
And i can see from each of them on the new board releases, that they at least try to go around the problem (which is not public) and sale boards with only Intel-Lan , no combo options anymore
I appreciate this, and should not continue to fuel the already burning down underground communication "fire" that is burning and burning in the dark. 
====================================================================
Soo yes, the reason i share it is that i've changed my mind a bit
Instead of complaining and crying about how stupid all this nonsense is
Let's work to maybe resolve it

Stability should be kept up, if the module is fully wiped from the bios, then it can not be loaded
Another way to "break" it , is by accident erasing the SOIC-8 chip which belongs only to the ethernet ports (each one has one)
I've done it by accident on the ITX (has I225-V) , sooo i know this fully renders ethernet inactive and no driver can even load + no entry in the ACPI table, soo no crashing FW can be loaded

Desoldering and swapping is hard
You'd need not only the corresponding Port, but also it's corresponding FW chip. And this means, destroying a board fully to "fix" another affected one.
Not a good option, but wiping the bios module with UefiTools and flashing it - should be easiest way to prevent the FW ever being loaded.

WHEA #19 overall covers a lot of IO, but this is the major issue one
the Dark hero , sadly was very problematic too me ~ but at that ttime i didn't know what's up
And it certainly is not even remotely an Substrate instability limit, as everything passed the usual test suite of y-cruncher , OCCT, P95, Cinebench , IBT and so on
It was a bad time with a 5900X & two swapped 5950X on the same board.

I've let you decide what to do with the information and the moderation team this time hopefully not censoring me
But i decided to take the least damage making route ~for now~ , try to actually resolve this issue somehow instead of complaining
And let you guys in this thread & not a big targeting post know ~ what's up , and why this can be problematic
Thank you for the trust & thanks again to @ManniX-ITA for the supplied workaround patch
Only filtering WHEA #19 would be useful, to prevent random DPC calls but at least this is something against the neverending fight with the semiconductor
I don't think AMD has the power to fix it really, it's them alone to supply not only "driver fixes" but actually update the FW in it ~ to stop crashing devices or itself . . . 
_let's see how long this post will last, hopefully it gets hidden under dozens of other messages, soo we can quote it ~ but hey i might get censored again_


----------



## T[]RK

Veii said:


> the Dark hero , sadly was very problematic too me ~ but at that ttime i didn't know what's up
> And it certainly is not even remotely an Substrate instability limit, as everything passed the usual test suite of y-cruncher , OCCT, P95, Cinebench , IBT and so on
> It was a bad time with a 5900X & two swapped 5950X on the same board.


It's really sad to read that Dark Hero is affected. I got it still in the box, never installed. @shamino1978 from time to time release "beta" BIOS for Crosshair motherboards, maybe he do something about it? Do you talk with him about problem with Dark Hero?

Also, untill there is no list of affected\non affected motherboards it impossible to switch board. Sell yeah, but no info about which to buy...


----------



## ManniX-ITA

Veii said:


> Maybe attach it to your signature , soo it's easier findable - i'll give it a shot on boards/users systems i know that fail


You are right, didn't think about it.
Will do tomorrow when it's on GitHub, will also create a thread.



Veii said:


> The "way" to get high FCLK to work, is on one hand to lower every voltage possible - this includes procODT too
> on the other hand supply enough to the IO-Die and then slowly bring up everything higher with SOC
> a high CCD freq will require more SOC , but tooo much SOC and high FCLK interconnect speeds will destabilize and crash the cores in the CCD
> Soo you need as low CCD as possible


I need to experiment a lot.
The latest releases for the Unify-X are much more troubling for memory above 3800.
Making it stable for my daily will be for sure challenging...
My old profiles doesn't work anymore and know I have to find out if I can stabilize tRCDRD 16 at 4000 MHz 



Veii said:


> Soo yes, the reason i share it is that i've changed my mind a bit
> Instead of complaining and crying about how stupid all this nonsense is
> Let's work to maybe resolve it


Agree, we can only hope in damage control now...
Obviously with this silicon crisis with 1 year lead time nobody is willing to pick up a fight with them.



Veii said:


> Thank you for the trust & thanks again to @ManniX-ITA for the supplied workaround patch


You are the man, you did the real stuff  
Me just a small bit. 
It's a risky path but until there's a better solution...


----------



## Veii

T[]RK said:


> Also, untill there is no list of affected\non affected motherboards it impossible to switch board. Sell yeah, but no info about which to buy...


I find some of the results on the Zen DRAM Sheet a bit suspicious
There are users with the Realtek RTL8111H ~ who have no WHEAs
It makes me wonder if HWInfo even tracks the #19's or only #18s which are "real issues" or only 2.5gbit ones are fully affected
(Combo unit boards are affected, but it's unsure if you can do anything there, if disabling the realtek jack actually disables anything there or it still causes crashes and WHEAs)

RTL8125B guaranteed does crash itself without anything plugging in, but the amount got less and less
It's been a long debate and mostly readable in the gigabyte beta bios thread
But i'm sure it wasn't only gigabyte, as stasio mentioned indirectly that more board partners where complaining to them and all they got is "you didn't follow our schematics correctly"
I really doubt that everyone is wrong and they are correct ~ considering it's "for the first time ?" , that i've heard, plugging anything into your RJ45 port can make the plugged device crash. lol

Unless some can rewrite the firmware of this thing , the only way is to exclude the module fully from the DXE UEFI table
Then if it still causes problems, erasing it's rom chip will "destroy" it enough so that it can not crash anymore.
Sadly restoring a by accident wiped ethernet rom chip is a pure pain, haha
Soo don't really do that, as you might not get the software & firmware from realtek to repair & reflash it :')
Getting it from intel was already hard enough ~ finding something "usable", had to dig into some Asus bios releases and then figure out which software it is to even reprogram that thing, as it didn't notice it exists anymore , once it's wiped 

Yea no, all can hope that dear semiconductor does something
Meanwhile 1200 and 1201 "USB Patches", caused USB droupouts on the ITX/AX ~ boards with usb 3.0 and type C only controllers
and if you restore a pre-1200 profile into it. These usb ports fully stop working ~ because XHCI and EHCI flags differ now and port layout differs after 1200 @Blameless

@ManniX-ITA 1201 and 1202 are painful for ramOC ^^
Good job to dom who got it stable finally 
But if you compare the geekbench results between 1200 and 1202, there is a 5-23% performance bump ~ with the same open EDC cache boost "fixes"
It certainly is worth it, but i'd suggest to stay on 1200 for now (SMU 56.43/44 , unsure about 56.45 as it has that burst refresh option in there ~ soo it probably ? already has the updated IMC FW)
1181-1201 are kind of a mystery at this point, what you get
Nobody really has the same bios out there with the same amount of applied or skipped patches


----------



## DeletedMember558271

So if we just buy boards without Realtek LAN we should be good then?
How ironic since I was probably going to buy an Asus B550-A originally, but specifically avoid Intel LAN for the issues I-225V was having, which are supposed to be fixed now in the B3 Stepping if you can get it. Have to hope you're not buying from somewhere with old stock.
With my luck I would go through all that now and get an old B2 I-225V or still have WHEA 1933+ somehow for some other reason, probably still have 1900 specifically unbootable still too.
If I knew 100% I could do like 2000/4000 WHEA-free though, it's tempting...
If everyone on these boards was having such success though, I think people would have noticed this was much more obvious sooner, I don't think everyone with Asus ROG Strix B550's are having 1933+ success or am I wrong?
I even see one on the Zen Sheet at just 1867/3733 on a Asus B550-F Gaming WiFi, with B-Die.


----------



## ManniX-ITA

Veii said:


> @ManniX-ITA 1201 and 1202 are painful for ramOC ^^


Of course I'm on 1.2.0.1 with SMU 56.45...
Can't go back cause the previous XOC BIOS doesn't have CO.
I can live with it running at 4000 MHz.



Veii said:


> I find some of the results on the Zen DRAM Sheet a bit suspicious
> There are users with the Realtek RTL8111H ~ who have no WHEAs
> It makes me wonder if HWInfo even tracks the #19's or only #18s which are "real issues"


Tracks also the #19, guaranteed.
There are many ways to remove the WHEA error sources my guess is they removed it or got lost due to some Windows bugs.

I wonder @craxton; which board do you have?


----------



## DeletedMember558271

Veii said:


> I find some of the results on the Zen DRAM Sheet a bit suspicious
> There are users with the Realtek RTL8111H ~ who have no WHEAs
> It makes me wonder if HWInfo even tracks the #19's or only #18s which are "real issues" or only 2.5gbit ones are fully affected
> (Combo unit boards are affected, but it's unsure if you can do anything there, if disabling the realtek jack actually disables anything there or it still causes crashes and WHEAs)
> 
> RTL8125B guaranteed does crash itself without anything plugging in, but the amount got less and less
> It's been a long debate and mostly readable in the gigabyte beta bios thread
> But i'm sure it wasn't only gigabyte, as stasio mentioned indirectly that more board partners where complaining to them and all they got is "you didn't follow our schematics correctly"
> I really doubt that everyone is wrong and they are correct ~ considering it's "for the first time ?" , that i've heard, plugging anything into your RJ45 port can make the plugged device crash. lol
> 
> Unless some can rewrite the firmware of this thing , the only way is to exclude the module fully from the DXE UEFI table
> Then if it still causes problems, erasing it's rom chip will "destroy" it enough so that it can not crash anymore.
> Sadly restoring a by accident wiped ethernet rom chip is a pure pain, haha
> Soo don't really do that, as you might not get the software & firmware from realtek to repair & reflash it :')
> Getting it from intel was already hard enough ~ finding something "usable", had to dig into some Asus bios releases and then figure out which software it is to even reprogram that thing, as it didn't notice it exists anymore , once it's wiped


Hmm... and here I am with my MSI B550 Tomahawk, "1x Realtek® RTL8125B 2.5G LAN + 1x Realtek® RTL8111H 1G LAN"...


----------



## Veii

Dreamic said:


> So if we just buy boards without Realtek LAN we should be good then?


It won't eliminate remain WHEA potential caused by other factors "from the chipset ongoing" ~ which includes SATA dismount and crashes (usually also RTL NIC related)
Soo i am still suspicious about the rewritten AMI NVMe module that came recently ~ as i'm purely on SATA and never had dropping out ports
But all these interconnect patches AMD pushes - do either break things or fix things (stupid i know)

The root cause was the NIC, although from the start till now, at least 20 patches have been pushed
Via drivers, microsoft FW injections and AGESAs
Soo it might not be as catastrophic anymore , when AMD felt that they can lift the Patch-C applied 1900 FCLK limit
But considering people still have issues while simple SMU 56.30 could reach and hold 2133 FCLK "stable" ~ although with a huge amount of autocorrection and package throttle : ')
(before all these interconnect and usb patches ~ thanks RTL)
Things might not look that bad. Overall it is bad to begin with , and i haven't seen really a response from the semiconductor ~ only unattended pushed patches without real namings what they do

Oh ProArt , procODT finally goes up to 480 Ohm
RZQ surely has changed and DQS range has changed
Funnily SMU 56.45 (1200 final) should not have the patches of 56.50 (1202), but CBS shows the options in there
Unsure what i have and what i miss, still haven't updatet to 1202 on it. Wanted first to port and adjust over the stable set from the ITX
(see how RTTs behave here) before i "potentially ?" , maybe trow away the unlocked bios
Depending if ASUS wants to be favorable with this fully unlocked bios , or again AMD bending ~ with 20% of them left 


ManniX-ITA said:


> Of course I'm on 1.2.0.1 with SMU 56.45...
> Can't go back cause the previous XOC BIOS doesn't have CO.
> I can live with it running at 4000 MHz.


Might trying my Memory training Rewrite on the unlocked bios ?
See if it's faster for you , if you find the options in CBS - DDR4 Common options (MBIST)


----------



## ManniX-ITA

Veii said:


> Might trying my Memory training Rewrite ?
> See if it's faster for you , if you find the options in CBS - DDR4 Common options (MBIST)


Sure, what I have to do


----------



## Veii

ManniX-ITA said:


> Sure, what I have to do


[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread this post
First spoiler 
2nd Spoiler has pictures i've taken the last two days while wanting to review the board - but you know i've given time-frames, soo at least some information to hold my words

Maxing out memory training amount to A or 10
then changing MBIST patterns to both methods, with 6 patterns on one single Aggressor

Was playing a bit more with pure data-eye predicted mode, which is accurate
but even at 3 PMU loops , it took 45-50sec to post / IF it posts the low CL settings

This shared method is faster, and takes 2 sec ~ yet is better than the stock memory training mode
If you enable Data Eye MBIST mode tho, it will take nearly a minute to post
It will eventuelly train, it's not frozen or broken like we thought, but it optimally needs redefined boundries for the aggressor channels
I lack the knowledge on it for now, soo this little change there, is the best that works for now 

Someday i'll get DATA-EYE mode training to be fast. I have faith ~ haha
Currently it's just unpractical , very accurate, but 1min post time is unpractical


----------



## Yuke

ManniX-ITA said:


> I think Veii mentioned at least VST in loop 4-5 times.
> But I always select 6 for "Enable All Tests".
> 4-5 cycles is rock solid, 12 cycles should be safe as Fort Knox


this is so funny...had so many WHEA errors when trying those settings before...but they are 7x Y-Cruncher and 3000% Karhu stable? Wth does that ignored Whea error even report?


----------



## KedarWolf

Got this earlier today.


----------



## Veii

ManniX-ITA said:


> Works for me, hope it works for you too...
> 
> Alpha version, no warranties, use at your own risk blah blah blah
> 
> It's a system service, will start at boot (or can be manually started) and will disable WHEA error reporting.
> Non intrusive and non destructive.
> You will loose WHEA error reporting for probably more than just WHEA 19.
> 
> I'm testing now my precious main install at FCLK 2000.
> Got a reboot in idle at FCLK 2066 sigh sob...
> 
> DPC Latency with Latencymon is quite awesome.
> 
> Download:
> 
> 
> 
> 
> 
> WHEAService_1.0_alpha.zip
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> 
> There's both a "portable" version that can be installed/uninstalled via a batch file and a classic installation package.
> Will publish tomorrow on Github if someone is confirming that works on other systems too.
> 
> Sorry was busy and focusing on FCLK 2000+


Works on one X570 ITX/AX
But with a bit of a workaround

















Something else, please test MSI Dragon Ball
It should work on some selected ASUS boards too
it won't install a .DLL like MemTweakIt
Which speaking of
This is the latest from shamino - works well on ASUS boards, but no write access

It does read out what i want it to read out tho - soo i can work with tMAW & UrgRefLimits + SubUrgRefLimits
tCKE is 1, so PDM is disabled
Here couple pictures ~ still fooling around















Very interesting, especially the Burst Mode that functions and remain IMC configs
will play with this and report back little advices and other shenanigans
~ sadly i get no write access on/with it

MSI Dragon Ball ~ universal ?





 MSI Dragon Ball.zip







drive.google.com




ASUS MemTweakIT ~ shamino edit [Needs the .dll ~ ASUS only]








MemTweakIt.rar


Shared with Dropbox




www.dropbox.com






Spoiler: EDIT



Urgend and SubUrgend Refresh Mode - function
Not just an "EPYC only Flag" in CBS








Wonder if i can fix that way my 1202 issues with buggy 4x tFAW mode 

Exploring if there is any way to modify predicted tREFI ~ tMAC changes apply but i can not see much of actual changes
tRC_PAGE is 214 on this set, tRC_PAGE limit 1023
Wonder if @infraredbg can figure out how to still read out tRC_PAGE , which is not Zero as it makes it believe

We really need to sit together and push an unlocked bios for all boards out there and push AMD a-bit to "allow" leaving these options publicly visible
There is soo much to adjust and soo little access, when you compare Z470/Z590 vs X570 / B550
Kind of sad to be on the wrong preferred & supported enthusiast tail

Still missing access to these things ~ MSI has access to & adapts with their "low latency" mode


----------



## craxton

Veii said:


> Good Job @ManniX-ITA , thank you for making it
> Maybe attach it to your signature , soo it's easier findable - i'll give it a shot on boards/users systems i know that fail
> 
> 2067 is not thaat hard, but maybe if my older message was viewed (the picture spam in the spoiler section)
> it needs exquisite voltages and low procODT - also a big difference between CCD and IOD
> High FCLK tends to mess with the CCDs, while high SOC might make the whole substrate very sensitive and will put FIT triggerhappy to autocorrect and slow down things (if something little is off)
> But higher SOC generally helped a lot - where VDDG then auto adjusted and load balanced it ~ nevertheless what you put in (as long as uncoreOC is disabled)
> 
> The "way" to get high FCLK to work, is on one hand to lower every voltage possible - this includes procODT too
> on the other hand supply enough to the IO-Die and then slowly bring up everything higher with SOC
> a high CCD freq will require more SOC , but tooo much SOC and high FCLK interconnect speeds will destabilize and crash the cores in the CCD
> Soo you need as low CCD as possible
> 
> Low CCD made it look like it triggers sound crackling and usb issues, but that is because VDDG keeps load balancing between CCD and IOD
> IO issues continue to relate to procODT and IOD - they have nothing to do with the CCD voltages. Suure the CPU controls somewhere the "cleanness and consistency" of the audio decoding
> Aside from the D/A chip on the board ~ but this goes back then to the "Signal Integrity" Topic , which is purely procODT related
> Soo lower CCD , you will notice when it's too low ~ then uplift everything with subtle more SOC voltage
> Also keep Standby voltage low
> 
> About the 1.8v Line
> This continues to be a semi mystery
> It is helpful when you SOC and IOD have a perfect 40mV *GET* distance, and nomatter of the load, this distance doesn't drop to 38mV
> But if it jumps to 42mV it can "desync" and destabilize
> Also if you max out switching frequency and loadlines, the ripple will get too worse and SOC won't be clean anymore, at all ~ a balance thing, i like to use loadlines here
> 
> CPU voltage, is up to users sillicon
> You can drive it with as little loadline as possible, or as much loadline as possible
> Signal Integrity is king here ~ soo give your best to lower ripple/increase signal integrity as best as you can
> This means, go lower with procODT (use all methods possible with CAD_BUS and RTT to help you for such)
> Go the lowest on cLDO_VDDP you can run (900mV is fine, but i've seen people at 2000 run 840 and lower)
> Go with the lowest VDDP Standby Voltage or CPU VDDP as possible ~ whatever is exposed and whattever it is named
> 
> VDD 1.8v line, usually holding it at 1.83v was beneficial to a little degree
> 1.8V is fine, lower had no benefits to this date ~ higher did only destabilize if you went with the "low current, high input SOC" path
> If you go with the "IOD to SOC = perfect 40mV" - then 1.8v line does help till 1.9v, somewhere along 1.84-1.86 is the sweetspot , higher can already create instability
> 
> Y-cruncher will crash, it is still able to destabilize Vermeer very well after some time ~ but give it time, as Vermeer does autocorrect and adapt to errors + adjust internal GMI link speeds to keep stability up
> OCCT Extreme AVX2, 1h ~ remains a good benchmark
> However it differs from y-cruncher, it is able to freeze Vermeer's Autocorrection . Whatever it does, Vermeer is not able to autocorrect that well for it
> But OCCT will also crash on any little FCLK or MCLK issue ~ as it is a Linpack Type of test after all. Soo be sure the whole y-cruncher test suite is stable for 3+ cycles. Make it 4
> 
> EDIT:
> If you see FCLK crashing because of "too much IOD or too much CCD"
> Bring it down - and compensate with higher input voltage on SOC
> That should make it stable, as it mostly crashes on "overcurrent" by bad signal integrity - just that the colour substrate change can need more SOC overall
> This should make it stable ~ but generally, the lower SOC the better , as it strongly eats into the powerbudget (EDC) which you can notice on one of the pictures after 1933Mhz
> EDIT 2:
> Keep in mind procODT has upper and lower bonds of SOC stable'ness
> It can be that you either need to decrease or increase procODT - on SOC increase (decrease on SOC decrease)
> 
> @Nizzen about the issue, sadly i'm the single person aside from board makes who noticed it. Very sure every board-partner & AMD is aware of the issue with Realtek & surely know their big stock-up amount & investment + trust
> Yes, i'll spill the beans but decided to take another route
> 
> 
> Spoiler
> 
> 
> 
> I could, brandshame them if i make a big announcement and focus on putting them into target on several places ~ including Reddit and for bigger media outlets
> ~ but i have personal issues not to think that they deserve it
> Don't get me wrong, they treated each of the boardpartners like ****, they absolutely deserve the brandshame and target-fire for whoever took that wrong direction, with this big flaw
> And alone that they refuse to fix it ~ but every boardpartner and AMD have to bent down to them just so they won't lose a huge amount of sales.
> It's a long going fight and the only "source" for this are email exchanges between PCB engineers and the Realtek RND department. The stupid excuses that are given and the lack of work that is provided, having AMD to force in redoing & applying soo many unstable patches ~ just to deal with their stubborn refusal to assist and fix their own design flaw.
> I'm mad about them. Respect them alot the last 6-8 years for how they behaved in the wireless and linux driver market.
> Respected them with the lower prices made and helped notebooks and PCBs in general costing less. Respected them a lot again for their Unix/Linux driver support staying opensource (kinda) and assisting + helping the Arch Linux community have more stable drivers.
> 
> But this here is a disaster
> 
> 
> 
> 
> 
> 
> 
> 
> B550 VRM DB sheet
> 
> 
> 시트1 Feedback : [email protected] Don't requst permission / You can leave comment :) Product,Price,Config,Phase Type,VRM Type,MOSFET (Vcore),PWM Controller,LAN,Wireless LAN,Audio ASUS ROG STRIX B550-XE Gaming WiFi,$ 330,14+2,Dual-Output,DrMOS,TI X95410RR 90A,ASP1405i (7+1),Intel I225-V (2.5...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Take a look here, tell me how many I225-V boards exist . . .
> Madness shouldn't rule over my public relationship with them, and i haven't received any bribe to refuse to talk.
> But i'm disappointed who in their department rules this nonsense. Why do you treat board partners like **** when they multiple times try to talk with you and fix it for everyone
> Is money that much more important than the huge userbase who uses "by your made mistake" all these buggy boards.
> At least they went out of their way after 3 months back and forth blaming - to fix some of the issues where each of their ports was force restarting attached Lan-Splitters and Routers.
> Probably just to ensure themself to be somewhat sue-free, and push a damage prevention math.
> 
> All these usb fix agesa and of course hidden ethernet fixes, driver rewrites (10+)
> Windows enforced update pushes and FW injections.
> Shady work, but nobody would notice anything ~ and probably for the brandstatus of this semiconductor ~ "shouldn't notice anything"
> But it reached hilarious levels already, and nothing changes
> Surely board partners are under NDA, in hope that nice Realtek guy finally fixes their broken mess of a FW
> And the saddest thing ~ you can't even skip the issue. It still causes problems if nothing is plugged in or even "ACPI disabled". it still triggers crashes and kernel "reboot reports"
> It still causes SATA drive crashes, by the experimental Chipset interconnect patches, that where supplied. And all for what ~ because dear semiconductor sits on their cooperate stool , stating that nobody held their given Schematics and they are not in fault for unstable controllers ~ and surely not in fault for letting close to everything reboot or crash by simply connecting it with it. . . .
> 
> 
> But yes, nobody wants to hear that and thinking about it for more ~ it's not the path to take
> Suure it would help and wake up some of these stubborn people in the industry, but it would put me on target and is kind of shameful having to take such path.
> Also would be against all of the Board-Partners who at least "try" to do something , in comparison to Semiconductor who doesn't even bother to cooperate.
> 
> Yes AMD tries too, sure many of it is loss-of-sales prevention & damage prevention, but at least "they try" ~something~
> And this "trying" is more appreciable - weighting out the damage and childish nonsense that has been going on between them in the hidden.
> Soo i should appreciate this "trying" of resolving something and not take the madman path not only damaging semiconductors reputation, but putting every boardpartner also in fire
> It is a bad idea to take that path ~ as again, the person to blame in the industry is someone that are not the board partners (not fully)
> And i can see from each of them on the new board releases, that they at least try to go around the problem (which is not public) and sale boards with only Intel-Lan , no combo options anymore
> I appreciate this, and should not continue to fuel the already burning down underground communication "fire" that is burning and burning in the dark.
> ====================================================================
> Soo yes, the reason i share it is that i've changed my mind a bit
> Instead of complaining and crying about how stupid all this nonsense is
> Let's work to maybe resolve it
> 
> Stability should be kept up, if the module is fully wiped from the bios, then it can not be loaded
> Another way to "break" it , is by accident erasing the SOIC-8 chip which belongs only to the ethernet ports (each one has one)
> I've done it by accident on the ITX (has I225-V) , sooo i know this fully renders ethernet inactive and no driver can even load + no entry in the ACPI table, soo no crashing FW can be loaded
> 
> Desoldering and swapping is hard
> You'd need not only the corresponding Port, but also it's corresponding FW chip. And this means, destroying a board fully to "fix" another affected one.
> Not a good option, but wiping the bios module with UefiTools and flashing it - should be easiest way to prevent the FW ever being loaded.
> 
> WHEA #19 overall covers a lot of IO, but this is the major issue one
> the Dark hero , sadly was very problematic too me ~ but at that ttime i didn't know what's up
> And it certainly is not even remotely an Substrate instability limit, as everything passed the usual test suite of y-cruncher , OCCT, P95, Cinebench , IBT and so on
> It was a bad time with a 5900X & two swapped 5950X on the same board.
> 
> I've let you decide what to do with the information and the moderation team this time hopefully not censoring me
> But i decided to take the least damage making route ~for now~ , try to actually resolve this issue somehow instead of complaining
> And let you guys in this thread & not a big targeting post know ~ what's up , and why this can be problematic
> Thank you for the trust & thanks again to @ManniX-ITA for the supplied workaround patch
> Only filtering WHEA #19 would be useful, to prevent random DPC calls but at least this is something against the neverending fight with the semiconductor
> I don't think AMD has the power to fix it really, it's them alone to supply not only "driver fixes" but actually update the FW in it ~ to stop crashing devices or itself . . .
> _let's see how long this post will last, hopefully it gets hidden under dozens of other messages, soo we can quote it ~ but hey i might get censored again_


this MASTERPIECE just got bookmarked, thank you VERY MUCH
for this OVERLOAD on info thats gonna improve my (personal knowledge already  )
i myself am one that was able to lower my offset voltage and increased LLC to 2 (msi) 
and 800khz cpu, 1000khz soc. 150mv overvoltage protection (*im not sure what it actually is, 
but i do believe its semi to do with how much is allowed to overshoot on core voltage?) 

anyhow thank you, ive not read it all. but will for sure over time.


----------



## Yuke

What is a "low procODT"? I have it at 40 and i had to increase my VSOC from 1.185 to 1.2V because i had idle reboot @2000Mhz IF clock with 1.185VSOC. I dont think that i can go lower with procODT with my dual rank kit if it means that "you have to compensate with more VSOC" when im already at 1.2V flat.


----------



## Eder

​Replaced my 3700x with a 5900x yesterday and after a good read of 30 pages I took the first step in raising FCLK. First lowered ProcODT and VSOC and currently testing. Let's see if 2000 is possible


----------



## Veii

Yuke said:


> What is a "low procODT"? I have it at 40 and i had to increase my VSOC from 1.185 to 1.2V because i had idle reboot @2000Mhz IF clock with 1.185VSOC.


*Too high*:
2x 8Gb SR
- 48Ω
4x 8GB SR & 2x 16GB
- 53.3Ω
4x 16GB DR / 2x 32GB
- 60Ω

*Just enough*
2x 8Gb SR
- 40Ω
4x 8GB SR / 2x 16GB
- 43.6Ω
4x 16GB DR / 2x 32GB
- 48Ω

*Optimal / Low procODT*
2x 8Gb SR
- 30-34.3Ω
4x 8GB SR & 2x 16GB
- 32-36.9Ω
4x 16GB DR / 2x 32GB
- 34.3-40Ω

*Too Low / Issues*
2x 8Gb SR
- 28.2Ω
4x 8GB SR & 2x 16GB
- 30Ω
4x 16GB DR / 2x 32GB
- 32-34.3Ω

"Too Low" ~ can be made possible when cLDO_VDDP is bellow 900mV
But then one step up makes more sense as you will be package throttling


Yuke said:


> I dont think that i can go lower with procODT with my dual rank kit if it means that "you have to compensate with more VSOC" when im already at 1.2V flat.[
> 
> 
> Veii said:
> 
> 
> 
> 
> CCDs have positive scaling with low voltage and low VDDP (CPU VDDP)
> IMC remains to have positive scaling with low voltage and so better signal integrity
> VDDG IOD remains to have the same scaling like Matisse, while it feels comfortable near 980-1080mV
> VDDG CCD has negative scaling beyond 950-980mV. It has positive scaling sub 940mV. Down to 850mV
> SOC has a big range 980-1280mV
Click to expand...

SOC's range is higher because of the substrate colour change
The quote will lead you to a big post about "AMD Maximum Voltage - Vermeer Edition"
920-1300mV is the SOC range of this generation
Higher than 1.3v is bad, higher than 1.25v barely brings any benefits
920mV SOC expects 840mV cLDO_VDDP, 840mV VDDG CCD, 880mV VDDG IOD, 920mV *GET *vSOC
GET = applied, factoring switching frequency and loadline droop

Same post also has a "minimum required SOC to run X FCLK"


----------



## TimeDrapery

@Veii 

Is your conclusion regarding the WHEAs present at high FCLK also likely the reason why Gigabyte (and others I'm sure) started capping PBO limits relative to what was available at release (or, at least, before Zen 3's release)...?

For example, my B550 AORUS MASTER came out of the box setting mobo limits to 1260 PPT/700 TDC/840 EDC whereas F13j sets 1260 PPT/700 TDC/215 EDC

When I noticed this I couldn't discern if it was the AGESA update that capped it or a mobo cap implemented by Gigabyte


----------



## craxton

@ManniX-ITA about the (operations being 5 error sources active we spoke on the other day)
i cleared the log, bc i (cant let anything be and accept that i just may be WHEA free even running 1933)
but i seem to have 4 operations logs, one which defines there are 5 error sources active to which, im
asking for a better answer (providing my questioning is better)

that im actually running WHEA logger as its supposed to be, or is something missing here? 
upon every reboot the same 4 come about again. 

if someone with WHEAs wouldnt mind clearing their operations logger for me, and rebooting to show 
if they too only have 4 information viewers shown with one being 5 error sources active id be 
content that i have a unicorn motherboard and CPU..........

bc nothing ive done will trigger (any WHEA errors other than messing with core voltage to where its 
WAY TO LOW to even run properly to begin with. 

anyhow, if someone can check this for me ill be greatful.


----------



## jomama22

Veii said:


> *Too high*:
> 2x 8Gb SR
> - 48Ω
> 4x 8GB SR & 2x 16GB
> - 53.3Ω
> 4x 16GB DR / 2x 32GB
> - 60Ω
> 
> *Just enough*
> 2x 8Gb SR
> - 40Ω
> 4x 8GB SR / 2x 16GB
> - 43.6Ω
> 4x 16GB DR / 2x 32GB
> - 48Ω
> 
> *Optimal / Low procODT*
> 2x 8Gb SR
> - 30-34.3Ω
> 4x 8GB SR & 2x 16GB
> - 32-36.9Ω
> 4x 16GB DR / 2x 32GB
> - 34.3-40Ω
> 
> *Too Low / Issues*
> 2x 8Gb SR
> - 28.2Ω
> 4x 8GB SR & 2x 16GB
> - 30Ω
> 4x 16GB DR / 2x 32GB
> - 32-34.3Ω
> 
> "Too Low" ~ can be made possible when cLDO_VDDP is bellow 900mV
> But then one step up makes more sense as you will be package throttling
> 
> SOC's range is higher because of the substrate colour change
> The quote will lead you to a big post about "AMD Maximum Voltage - Vermeer Edition"
> 920-1300mV is the SOC range of this generation
> Higher than 1.3v is bad, higher than 1.25v barely brings any benefits
> 920mV SOC expects 840mV cLDO_VDDP, 840mV VDDG CCD, 880mV VDDG IOD, 920mV *GET *vSOC
> GET = applied, factoring switching frequency and loadline droop
> 
> Same post also has a "minimum required SOC to run X FCLK"


I think a big misconception here as well is that as much as a lot of this is standard practice, it's not written in stone. Chips will be chips and vary. Just because you're stable doesn't mean you're getting the most performance out of any given set of timings.

My 5950x hates clod_vddp or ccd below .95 and gives me the best benchmarks and results at 1.0. IOD hates anything above 1.05 and runs best at 1.0 as well. So I have these odd ball voltages of flat 1v for vddg and Clod_vddp and 1.056v soc (get) for my current setup. Raising soc results again in worse performance. This is specific to my 1900/3800 set ups.

All the while, many different combinations of these voltages will be perfectly stable through tm5, y-cruncher, occt, w.e. 

Same goes for the rtt's and drive strengths. Again, have a real weird set of 7/3/2 and 20-24-24-24 with procODT of 43.6.

When I say better performance, I'm not really talking about aida latency and such as really, that won't much, if at all, once your stable. But doing render times, cpu game benchmarks, etc, can expose these odd behaviors.

Vdimm below is 1.51. The rtt's changed to 7/3/2 as stated as I found it game me better and more consistent performance.


----------



## drnilly007

So Im not sure what to do now after reading the last few pages. I have the dark hero and a 5900x that died in that board going to rma. THe ASUS qcode was 07 which refers to memory but the chip wouldnt even get to bios. I tried other working sets of ram. I think the memory controller or IF died.

Either Im selling the rma 5900x and going intel or is there a good known motherboard that can support the 5900x properly and also dual rank b die ram. I have a 5600x in the Dark hero now and docp 3200 b die causes crashes and instability.

Im starting to hate AMD because of all of this, never had a dead intel cpu in 2 months.


----------



## Veii

TimeDrapery said:


> @Veii
> 
> Is your conclusion regarding the WHEAs present at high FCLK also likely the reason why Gigabyte (and others I'm sure) started capping PBO limits relative to what was available at release (or, at least, before Zen 3's release)...?
> 
> For example, my B550 AORUS MASTER came out of the box setting mobo limits to 1260 PPT/700 TDC/840 EDC whereas F13j sets 1260 PPT/700 TDC/215 EDC
> 
> When I noticed this I couldn't discern if it was the AGESA update that capped it or a mobo cap implemented by Gigabyte


It was to fight the overboost [Bug] issue, not the CTR 2.1 Overboost [Feature] thing

By opening EDC, internally more than one Flag changes
There is a specific limit for cache boost and cache burst limit
1usmus mentioned 3 of them on his post 2 monts ago
Its been "there" since the ABL change/unlock on AGESA 1.1.0.0D
It co-exists with dLDO-Regulator loadbalancing, but was a triggerable flag before

L3 interleaved cache speedup , will boost a bit higher than what you'll get when you run the same frequency on all cores
Vermeer on PBO is able to overdrive itself a bit further than normal frequency shows, within the peak frequency limits. Its a snowballing interleaving algorithm with set GMI CAKE (the cake is fake)  performance degradation penalty watchdogs.
Soo this means not only that it watches and adapts to clean signal integrity + adjusts and smooths dropouts with dLDO_injection ~ soo throttles interconnect lines if required to keep up stability
But also overdrive or overboosts itself, when the "Health/Quality" is enough
I'm unclear how much logging is left on the public CTR 2.1 , but it illustrates it very well
Overboost CTRs feature ~ does rely the foundations of functional dLDO , soo the requirements are AGESA 1.2.0.0 or 46.43 SMU (preferably over 56.37)

The limits you see and set "nearly" do nothing
Its just throttling in the first stage and can control the supplied voltage before it arrives to FIT & dLDO_injector

You might remember the 5ghz allcore TM5 i postet at 1.375v dynamic
This was overboost in play, but not the crashing but overboost
Or maybe some remember the "overboost bugs" that spread on twitter and here
Reaching 50ghz peaks or the reason i/we fully focused on powerplan work abusing idle states
As idle states have a higher boost hysteria than normal frequency curve straps
Also far stronger boost hysteria than going from P1 to P0 or boost to P0 (being 3.7 or 3.8ghz up to cpu)
Using suspend to boost states, skipping the P-states and skipping P0 fully, leads to a snapshot boost
Or burst boost, which can peak far beyond the silicons capability and far beyond 1.75v (if allowed) before FIT throttles it back and then slowly the more time passes , dLDO averages and smooths out everything

About this topic and the OB abusing powerplan
I'm still not done, was waiting for 1202 boost scheme rewrite and CTR finishing 2.1
Currently and still it's similar to the first Alpha i've dropped here
Its usable, but it's too extreme
And once you enable DF-CStates (hibernation states) generation, the aggressiveness of it is too strong and the duration of the 200% APCI spike (limited but it stil spikes that high = 3.7*1.5= 5500Mhz) leads to crashes and idle reboots

I've seen and noted several 48Ghz spikes on it, up to 55Ghz and they where kept stable
But it is too risky and unstable, even if there is a nice boost benefit ~ sop DF-states are disabled in the bios by default
AMD knows about this, but their stock powerplans have no peak limits, soo it can spike too high
And my powerplan which abuses this within limits, is still too spiky and aggressive on many CPUs
Its fine for balanced units, but dLDO is not able to fully correct and smooth it out.
I'll keep a copy of the aggressive one, but need to weaken it, as the boosting system still can not handle it and crashes the CPU on too many voltage variation's 

Else when it works on a 5950X, there are 120-150Mhz boosts per core
Simply as more boosting budget remains left 😊
Well it's still "broken" from my perspective and CTR crashes it, haha
Soo i need to finish it someday ~ hopefully soon

Edit:
TL;DR.; 
Keep EDC high, limit a bit with TDC and keep PPT to your cooling capabilities and power supply capabilities 
Lifting the first-stage EDC limits, allows overdive to happen and cache to dynamically adapt to CPUs capabiltiy limits 
It won't crash because of this, but can overvolt itself a bit too much
Soo increase negative CO, to lower general input current (V) helping FIT having to throttle less & noting less "uaed current"
Meaning "more free potential left and soo more allowed boosting busget"


----------



## craxton

ManniX-ITA said:


> I wonder @craxton; which board do you have?


my apologies didn't see i was mentioned,
i have the MSI MPG B550 Gaming EDGE WIFI rev 1.0
1.2.0.1 agesa, (thats not posted on MSI website since the latest released agesa for whatever reason)

would seem the other very few on zen timings sheet that use this board
are as well on this agesa or older as 4000mhz wont post with extremely loose timings
let alone just 2x8 instead of the 4x8 i run now.

and aout HWiNFO tracking WHEA errors, it ALWAYS shows 0 even when i clearly have 2 20s and 2 19s or was it 18?
yea was 2 ID20 and 2 ID18's but still, HWiNFO64 never shows any being logged.

i cleared the ID20 codes, and left the ID18's (ran ctr just to check and it says 2 WHEA records as well)

if these have been recorded then the rest would be recorded as well, wouldn't they?


Spoiler



whys this something i cant leave be


----------



## jomama22

craxton said:


> my apologies didn't see i was mentioned,
> i have the MSI MPG B550 Gaming EDGE WIFI rev 1.0
> 1.2.0.1 agesa, (thats not posted on MSI website since the latest released agesa for whatever reason)
> 
> would seem the other very few on zen timings sheet that use this board
> are as well on this agesa or older as 4000mhz wont post with extremely loose timings
> let alone just 2x8 instead of the 4x8 i run now.
> 
> and aout HWiNFO tracking WHEA errors, it ALWAYS shows 0 even when i clearly have 2 20s and 2 19s or was it 18?
> yea was 2 ID20 and 2 ID18's but still, HWiNFO64 never shows any being logged.
> 
> i cleared the ID20 codes, and left the ID18's (ran ctr just to check and it says 2 WHEA records as well)
> 
> if these have been recorded then the rest would be recorded as well, wouldn't they?
> 
> 
> Spoiler
> 
> 
> 
> whys this something i cant leave be


Don't think hwinfo picks up on the 18s as that usually ends in a crash. Iv personally never experienced a 20 lol. Hwinfo will track the 19s as they happen though.


----------



## craxton

lmfodor said:


> -+ 0,03/0,06V? Or should I try LLC 2 for both CPU and VSOC and leave sw frequency to 500?


it comes down to CPU honestly, LLC2 with what you have set (at the time you crashed) 
should possibly do the trick, just (MONITOR) how far core voltage overshoots 
Veii stated 1.5V on one core in certain workloads is fine for a short period of time.
and sustained 1.35 i believe is fine under heavy loads, so long as you can keep the chip cool...
he stated ALOT in the post he made on this, sadly i didnt think to bookmark it tho.

as now i book mark ANYTHING over 5 sentences with labels that i know what to look for, 
so i can link others in lower places back to that post for guidance...

llc2 did the trick for me and i lowered my offset in voltage, while keeping 800khz cpu switching frequency, 
1000khz on SOC llc3 and lowered WAY DOWN from 1.21SOC to 1.15SOC (remember 4x8 not 2x8)
can run 2x8 at 1.1soc just fine...(for those reading) 



jomama22 said:


> Don't think hwinfo picks up on the 18s as that usually ends in a crash.


yea sounds about right, prob why i never have had ANYTHING show inside HWiNFO
at all....since just those two are all ive ever had and thats been within the last 7 days....

still wouldnt mind to know whats in (other peoples) operations log.
each restart shows 4 (same info loggers) on my end, just wondering if im missing one...

already stated in the post up above, but my curiousity is getting the best of me, as not to much 
info is (EASY TO UNDERSTAND) on whats supposed to be inside operations log underneath kernel whea folder...


----------



## TimeDrapery

Veii said:


> Spoiler
> 
> 
> 
> It was to fight the overboost [Bug] issue, not the CTR 2.1 Overboost [Feature] thing
> 
> By opening EDC, internally more than one Flag changes
> There is a specific limit for cache boost and cache burst limit
> 1usmus mentioned 3 of them on his post 2 monts ago
> Its been "there" since the ABL change/unlock on AGESA 1.1.0.0D
> It co-exists with dLDO-Regulator loadbalancing, but was a triggerable flag before
> 
> L3 interleaved cache speedup , will boost a bit higher than what you'll get when you run the same frequency on all cores
> Vermeer on PBO is able to overdrive itself a bit further than normal frequency shows, within the peak frequency limits. Its a snowballing interleaving algorithm with set GMI CAKE (the cake is fake)  performance degradation penalty watchdogs.
> Soo this means not only that it watches and adapts to clean signal integrity + adjusts and smooths dropouts with dLDO_injection ~ soo throttles interconnect lines if required to keep up stability
> But also overdrive or overboosts itself, when the "Health/Quality" is enough
> I'm unclear how much logging is left on the public CTR 2.1 , but it illustrates it very well
> Overboost CTRs feature ~ does rely the foundations of functional dLDO , soo the requirements are AGESA 1.2.0.0 or 46.43 SMU (preferably over 56.37)
> 
> The limits you see and set "nearly" do nothing
> Its just throttling in the first stage and can control the supplied voltage before it arrives to FIT & dLDO_injector
> 
> You might remember the 5ghz allcore TM5 i postet at 1.375v dynamic
> This was overboost in play, but not the crashing but overboost
> Or maybe some remember the "overboost bugs" that spread on twitter and here
> Reaching 50ghz peaks or the reason i/we fully focused on powerplan work abusing idle states
> As idle states have a higher boost hysteria than normal frequency curve straps
> Also far stronger boost hysteria than going from P1 to P0 or boost to P0 (being 3.7 or 3.8ghz up to cpu)
> Using suspend to boost states, skipping the P-states and skipping P0 fully, leads to a snapshot boost
> Or burst boost, which can peak far beyond the silicons capability and far beyond 1.75v (if allowed) before FIT throttles it back and then slowly the more time passes , dLDO averages and smooths out everything
> 
> About this topic and the OB abusing powerplan
> I'm still not done, was waiting for 1202 boost scheme rewrite and CTR finishing 2.1
> Currently and still it's similar to the first Alpha i've dropped here
> Its usable, but it's too extreme
> And once you enable DF-CStates (hibernation states) generation, the aggressiveness of it is too strong and the duration of the 200% APCI spike (limited but it stil spikes that high = 3.7*1.5= 5500Mhz) leads to crashes and idle reboots
> 
> I've seen and noted several 48Ghz spikes on it, up to 55Ghz and they where kept stable
> But it is too risky and unstable, even if there is a nice boost benefit ~ sop DF-states are disabled in the bios by default
> AMD knows about this, but their stock powerplans have no peak limits, soo it can spike too high
> And my powerplan which abuses this within limits, is still too spiky and aggressive on many CPUs
> Its fine for balanced units, but dLDO is not able to fully correct and smooth it out.
> I'll keep a copy of the aggressive one, but need to weaken it, as the boosting system still can not handle it and crashes the CPU on too many voltage variation's
> 
> Else when it works on a 5950X, there are 120-150Mhz boosts per core
> Simply as more boosting budget remains left 😊
> Well it's still "broken" from my perspective and CTR crashes it, haha
> Soo i need to finish it someday ~ hopefully soon
> 
> Edit:
> TL;DR.;
> Keep EDC high, limit a bit with TDC and keep PPT to your cooling capabilities and power supply capabilities
> Lifting the first-stage EDC limits, allows overdive to happen and cache to dynamically adapt to CPUs capabiltiy limits
> It won't crash because of this, but can overvolt itself a bit too much
> Soo increase negative CO, to lower general input current (V) helping FIT having to throttle less & noting less "uaed current"
> Meaning "more free potential left and soo more allowed boosting busget"


@craxton 

I think this is one of those posts to bookmark, right? 😂😂😂😂😂

@Veii 

Thanks so much for taking your time to share all this information, that's righteous... I'm back to read through it again now


----------



## craxton

TimeDrapery said:


> I think this is one of those posts to bookmark, right?


ABSOLUTLY, infact already have lol, and a few others...









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


but this is something that im sure ALOT will thank, and hate about as well, no need to explain but some cant let go that they have errors period. (Id be one of those if i were seeing WHEA out the arse) I trust Veii analysis that these errors have nothing to do with a fault in the CPU That's...




www.overclock.net













CoreCycler - tool for testing Curve Optimizer settings


Here's v0.8.0.0 RC4, only use it if you're willing to beta test. 👆 https://github.com/sp00n/corecycler/releases/tag/v0.8.0.0-RC4 @Theo164 It's interesting, I've never been able to have Y-Cruncher actually fail a stress test. It's either passing for me or rebooting the whole system. 🤷‍♂️ And...




www.overclock.net













[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Opposite. The cooler pressures in the center only. AUROS retweet back then about LGA and PGA But the actual illustration fits The center and the sides where bent higher when they where send to the factory The heat and pressure clamps then went strongly into the layers The center was pushed...




www.overclock.net













[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


craxton Thank you for your recommendation. I did Prime95 for 7.4 hours and there is no errors. Do I need to test it longer? you see, thats Veii one of the two i mentioned...as you can see he said ALOT of things in which will be hard to understand as i dont understand some of what was said...




www.overclock.net





the other few i have are just stuff i thought id use eventually, and some are
just comparisons lol...but none the less, others should mark these pages too...


----------



## jomama22

Veii said:


> It was to fight the overboost [Bug] issue, not the CTR 2.1 Overboost [Feature] thing
> 
> By opening EDC, internally more than one Flag changes
> There is a specific limit for cache boost and cache burst limit
> 1usmus mentioned 3 of them on his post 2 monts ago
> Its been "there" since the ABL change/unlock on AGESA 1.1.0.0D
> It co-exists with dLDO-Regulator loadbalancing, but was a triggerable flag before
> 
> L3 interleaved cache speedup , will boost a bit higher than what you'll get when you run the same frequency on all cores
> Vermeer on PBO is able to overdrive itself a bit further than normal frequency shows, within the peak frequency limits. Its a snowballing interleaving algorithm with set GMI CAKE (the cake is fake)  performance degradation penalty watchdogs.
> Soo this means not only that it watches and adapts to clean signal integrity + adjusts and smooths dropouts with dLDO_injection ~ soo throttles interconnect lines if required to keep up stability
> But also overdrive or overboosts itself, when the "Health/Quality" is enough
> I'm unclear how much logging is left on the public CTR 2.1 , but it illustrates it very well
> Overboost CTRs feature ~ does rely the foundations of functional dLDO , soo the requirements are AGESA 1.2.0.0 or 46.43 SMU (preferably over 56.37)
> 
> The limits you see and set "nearly" do nothing
> Its just throttling in the first stage and can control the supplied voltage before it arrives to FIT & dLDO_injector
> 
> You might remember the 5ghz allcore TM5 i postet at 1.375v dynamic
> This was overboost in play, but not the crashing but overboost
> Or maybe some remember the "overboost bugs" that spread on twitter and here
> Reaching 50ghz peaks or the reason i/we fully focused on powerplan work abusing idle states
> As idle states have a higher boost hysteria than normal frequency curve straps
> Also far stronger boost hysteria than going from P1 to P0 or boost to P0 (being 3.7 or 3.8ghz up to cpu)
> Using suspend to boost states, skipping the P-states and skipping P0 fully, leads to a snapshot boost
> Or burst boost, which can peak far beyond the silicons capability and far beyond 1.75v (if allowed) before FIT throttles it back and then slowly the more time passes , dLDO averages and smooths out everything
> 
> About this topic and the OB abusing powerplan
> I'm still not done, was waiting for 1202 boost scheme rewrite and CTR finishing 2.1
> Currently and still it's similar to the first Alpha i've dropped here
> Its usable, but it's too extreme
> And once you enable DF-CStates (hibernation states) generation, the aggressiveness of it is too strong and the duration of the 200% APCI spike (limited but it stil spikes that high = 3.7*1.5= 5500Mhz) leads to crashes and idle reboots
> 
> I've seen and noted several 48Ghz spikes on it, up to 55Ghz and they where kept stable
> But it is too risky and unstable, even if there is a nice boost benefit ~ sop DF-states are disabled in the bios by default
> AMD knows about this, but their stock powerplans have no peak limits, soo it can spike too high
> And my powerplan which abuses this within limits, is still too spiky and aggressive on many CPUs
> Its fine for balanced units, but dLDO is not able to fully correct and smooth it out.
> I'll keep a copy of the aggressive one, but need to weaken it, as the boosting system still can not handle it and crashes the CPU on too many voltage variation's
> 
> Else when it works on a 5950X, there are 120-150Mhz boosts per core
> Simply as more boosting budget remains left 😊
> Well it's still "broken" from my perspective and CTR crashes it, haha
> Soo i need to finish it someday ~ hopefully soon
> 
> Edit:
> TL;DR.;
> Keep EDC high, limit a bit with TDC and keep PPT to your cooling capabilities and power supply capabilities
> Lifting the first-stage EDC limits, allows overdive to happen and cache to dynamically adapt to CPUs capabiltiy limits
> It won't crash because of this, but can overvolt itself a bit too much
> Soo increase negative CO, to lower general input current (V) helping FIT having to throttle less & noting less "uaed current"
> Meaning "more free potential left and soo more allowed boosting busget"


Talking about tm5 and overboost lol:


----------



## Veii

TimeDrapery said:


> @Veii
> 
> Thanks so much for taking your time to share all this information, that's righteous... I'm back to read through it again now


It was written on my phone, sadly the Alpha powerplan with 4% idle atates & 5150Mhz limit, i dont have on my phone. Currently outside
Its somewhere lost on this Thread
"Vermeer_LowPower-Alpha"
Bookmark the NIC complain if you haven't, first half of it is rather educational

Figured something extremely interesting before going out
This older picture showing tMAW addressing
Has a very interesting behavior

On tRFC 218, 200K is 546 tRC_Page
900K goes down to as low as 115 RC_PAGE
Unlimited and & untested do "nothing*
But these actually do some changes ti RC_PAGE and i think it depends on tRFC range what works there
Either tSTAG or tRFC

The interesting part of all this is, that there is a range and we can take this and use it for calculation
I forgot who had tRC_Page (tMaw.tMac) in their sheets if it was Ron or Dom
But we'd need this information. Can better up timings with it and control it better

As for AMD for MBIST menu,
Pattern A & Aggressor 5 are even better than 9 & 1
I mistook hex with decimal, it's range is 3-9 and A-C = 3-12 value
Bettered it up and this made memory training even better, soo currently (today) jumped from 3333 to 3400CL12-12-12 @ 55ns 
Quite low for such a low MT/s 😊
3400 is tCKE 4, 5 doesn't want to work
Its on full powerdown mode, not just Aggressive Powerdown without nornal powerdown togglr

@craxton for me its 9 different types of WHEA's
I forgot on the ITX probably around 5-6
WHEA 20 I really think means nothing
Haven't had 18s , gladly


----------



## craxton

Veii said:


> for me its 9 different types of WHEA's


you get 9 different WHEA errors in kernel-whea?
or inside the operations logger????

as stated the two 18s i had was on the same day, 7 days ago, well now
8 days ago since midnights passed...


----------



## Dar|{cyde

@craxton My event log looks the same. I get 4 events on each boot. Three ID 42's and an ID 5. That one says "5 error sources are active." I'm on a Unify-X if that makes any difference.

Regarding the Realtek LAN causing issues, I'm not very surprised. You always want to avoid RTL Lan if you have a choice, intel was always better. It's been like that for at least 20 yrs. It did shock me that so many vendors went with realtek instead of Intel this generation.

I just found something cool that might interest you peeps.

I was messing with rEFInd boot loader, and I managed to copy over the boot file for memtest86. The boot manager detects it automatically. The big deal part is memtest loads orders of magnitude faster (than a crappy old USB stick that I used before.) There are instructions on the rEFInd site. Copying the file requires mounting the EFI partition of your memtest86 stick. It shouldn't be too hard to figure out using mountvol. If anyone needs instructions I could probably write some up, but you guys are sharp.

TL;DR Run memtest86 from EFI, it's super fast.


----------



## craxton

Dar|{cyde said:


> TL;DR Run memtest86 from EFI, it's super fast.


many here swade away from memtest85...
HCI is what most will suggest, as well, ill let someone who knows the reason best
that can explain easy....but i do know i was told to use anything BUT memtest 86...
windows memory diag (is what they suggested over memtest lol???) 
i used it forever, but i did have it pass several times over, to which my OS corrupt due to bad ram timings etc...
i never went back after that..

do not take that as some kind of insult, i dont care what people use, i just spread what i know/experience.
it is safer tho to run from a bootable since its not running inside the OS. 
but OCCT, PRIME95, HCI, TM5, y-cruncher, and kuhra? idk what its called for that last one, i dont use it.
but thats what most here speak of. 




Dar|{cyde said:


> My event log looks the same. I get 4 events on each boot. Three ID 42's and an ID 5. That one says "5 error sources are active." I'm on a Unify-X if that makes any difference.


THANK YOU VERY MUCH!!!

matters not what board your on. (you get WHEA errors? by chance)?


----------



## DeletedMember558271

Dar|{cyde said:


> Regarding the Realtek LAN causing issues, I'm not very surprised. You always want to avoid RTL Lan if you have a choice, intel was always better. It's been like that for at least 20 yrs. It did shock me that so many vendors went with realtek instead of Intel this generation.


You act like Intel didn't also ship out faulty unfixable avoid at all costs I225-V's as the only alternative, until they fixed it in a new B3 Stepping.
Realtek was the only option at the time for everyone who was paying attention because of this, and now we're finding out that's ****ed too.
So now that you can actually get Intel LAN that works properly, looks like that's the only option now...
Except still not even guaranteed 1933+ WHEA-free I guess, I don't want to make a switch and do all that for the same result idk...
Imagine if everything just didn't suck, that would be nice


----------



## DeletedMember558271

Also good luck to anyone trying to get a B3 Stepping from Intel as it seems there are still plenty of faulty B2's out in the wild sitting on warehouse shelves waiting to be shipped to you just from the first Reddit thread I looked at on this and the comments within just the past month and days


__
https://www.reddit.com/r/ASUS/comments/kppyoi


----------



## Dar|{cyde

I didn't know I225-V was having issues as well. Huh.

@craxton I'm running stable 3800 right now. I can easily push into WHEA territory, I've just been working on other stuff lately.

I know memtest isn't the greatest one (and I've used it since we booted from floppies and timings looked like 2-2-2-5). It definitely isn't as sensitive to errors as TM5. It does come in handy to test your system though, especially when its destabilized to throw errors on purpose. That RTT testing method posted a few days back used it. I prefer to stay out of my windows when I'm actively throwing memory errors. As you experienced, it only takes one error to corrupt your registry.


----------



## lmfodor

Dreamic said:


> Also good luck to anyone trying to get a B3 Stepping from Intel as it seems there are still plenty of faulty B2's out in the wild sitting on warehouse shelves waiting to be shipped to you just from the first Reddit thread I looked at on this and the comments within just the past month and days
> 
> 
> __
> https://www.reddit.com/r/ASUS/comments/kppyoi


What good information, then, if we do not want to choose a Mobo without realtek, we just had these with Intel Ethernet cards. Too bad they filled the Realtek 2.5GB mobos, I don't know how many use it.


----------



## ManniX-ITA

craxton said:


> each restart shows 4 (same info loggers) on my end, just wondering if im missing one...


Yes that´s it, the missing one should be the DeviceDriver source.
Some of the WHEA are spawned from that source and, seems logical, all those related to the Realtek/FCLK issue.




jomama22 said:


> My 5950x hates clod_vddp or ccd below .95 and gives me the best benchmarks and results at 1.0. IOD hates anything above 1.05 and runs best at 1.0 as well. So I have these odd ball voltages of flat 1v for vddg and Clod_vddp and 1.056v soc (get) for my current setup. Raising soc results again in worse performance.


Some for my 5950x except higher VSOC doesn't hurt.
How's that kit? 
It's the next in my list... did you try tRCDRD at 16 at 4066+?
My 4000C16 can do tRCDRd up to 4000, at 4066+ needs 17.



craxton said:


> @ManniX-ITA about the (operations being 5 error sources active we spoke on the other day)
> i cleared the log, bc i (cant let anything be and accept that i just may be WHEA free even running 1933)
> but i seem to have 4 operations logs, one which defines there are 5 error sources active to which, im
> asking for a better answer (providing my questioning is better)


I'm not sure I understand your question 
Are you counting the event messages?
You need to check content of the message with Event ID 5.

Which is something like:
*
WHEA successfully initialized.
6 error sources are active
Error record format version is 10.*

If the active error sources are less than 5 then that's probably why you don't get them.
But I think you already posted a screenshot and they were 5.

Which BIOS version are you running?
I don't see an AGESA 1.2.0.1 in the support page.

It's interesting since you should have WHEA since the LAN is Realtek.
Wonder if there's something special in the UNDI EFI (the Realtek firmware) in that specific BIOS.



Veii said:


> Currently and still it's similar to the first Alpha i've dropped here
> Its usable, but it's too extreme


I have missed it 
Can you repost?


----------



## Veii

craxton said:


> you get 9 different WHEA errors in kernel-whea?
> or inside the operations logger????
> 
> as stated the two 18s i had was on the same day, 7 days ago, well now
> 8 days ago since midnights passed...


Inside the operation logger, the way ManniX teached it 
9 different potential operations
On the ITX it was 6
But i get 0 WHEAs

At the very first start without 6.25mV positive vcore offset, i got plenty of 18s
8-9 at least
There is some interesting bug
If i let it auto-predict, the SOC range is lower and accurate ~ same for IOD
But if i push it as an offset, its 50-60mV higher and starts from 1.2v and higher for over 2000 FCLK
Usually it was 1.25+ but here it's 1.2+
Soo the offset, even 10mV in this applies after the 1.2v range

I can see that Asus has internally an own predefined range
Soo i'm not sure if the sample #18 at the start because ASUS range is too tight, or because the CPU has a 5950X V/F table inside, soo it struggles a bit without work
I've for example seen this on other 5800X dual CCD units, which where completely unstable on stock without 2-3 positive CO on it


----------



## DeletedMember558271

lmfodor said:


> What good information, then, if we do not want to choose a Mobo without realtek, we just had these with Intel Ethernet cards. Too bad they filled the Realtek 2.5GB mobos, I don't know how many use it.


I don't really understand what you just said, but yea, if not wanting Realtek there's Intel, and it's a gamble as to whether you'll get a B2 stepping, which are all physically defective, or a new B3. Board choices are more limited.
Fun times


----------



## ManniX-ITA

Veii said:


> Pattern A & Aggressor 5 are even better than 9 & 1


So Pattern length(VMR) in DataEye set to 5 with 1 Aggressor Channel and PMU Pattern A?


----------



## lmfodor

In the middle of this news of trying to test +1933 without WHEAs, I gave up as I am among those affected with my Asus Crosshair.

So for now, I want to stabilize my configuration at least to play a game for hours as before, I had no WHEA 41 nor BSOD errors for a long time. So now, I realize that from playing with values so much, I was wrong about something, and I know that it is simple for many of you. First I took care of validating my memory configuration, which seems to be stable at least for so many TM5 tests and even leaving HCI Memtest deluxed (I know it is an old program, but one more to test) overnight with almost 600% coverage without errors. Also both TM5 without any errors and I'm already passing 30 cycles, both 1usmus or the Anta777 Extreme.

The last thing I modified was to enable the 1T GDM Disabled and with the "miraculous" 56-56-56 that then leads to -56-0-12 with tCKE 16 to achieve better latency, which in fact thanks to @ManniX-ITA tests with AIDA64 achieves the same, 54.4ns almost always. Excellent Mannix! Now I have the easiest but the least I understand, which are *voltage drops and LLC.* I don't know if my problem here is the CPU or the vSOC. But I saw many configurations, and they are all similar. In fact, in ASUS, unlike other boards, you cannot put switching frequencies as high as in the MSI that I see more than 1000. So all this boils down to something that maybe can help me so I try, and also for my son to play Need for Speed Heat , which I feel quite guilty about so much tuning with excellent benchmarks but I can't play a basic game. I clarify that a long time ago I dismissed the OC to my RTX 3080 TUF OC, it never worked for me since I always had a crash in several basic games such as Forza Horizon 4, or CyberPunk 2077 (which supported a little more OC) and the COD Coldwar . Even playing Crysis Rematered everything on Ultra and RTX, with the non-OC settings it worked very well for me.

This are my current memory timings, 1.5VDIMM. I could try to increase the procODT to 36ohm, but the voltages in term of the memory OC seems pretty normal, I mean 1.1 vSOC, 0.9 VDDP, 1.05 IOD and the CCD I have my doubts if it would be 0.95 or a little bit up as I have it now in 0.98V. Y-Cruncher stil fail, but not with the memory test 14 and 15, always on VST on other like this. Even after 4 hours running. One thing I test is to move the mouse while testing and if forced the crash. I saw it in Buildzoid..









And these my BIOS Values



Spoiler: DIGI Power Settings












































An All Core -24.. That's it


So I would ask for your help, 🙏I know it is not the "fashionable" issue since I am also interested in overcoming the 1933 FCLK, but now I want to at least be able to play. So, if you can help me with some advice, I would really appreciate it (and my son  ). Excuse me again for being so basic. But I always had the best help here!


----------



## Veii

ManniX-ITA said:


> So Pattern length(VMR) in DataEye set to 5 with 1 Aggressor Channel and PMU Pattern A?


PMU patterns always set to A
There the range is 1-9 , A-C

Aggressor from 1 change it to 5 , (1,5,7, is the range)
The rest is like the picture
Test mode is "both"
Pattern length the range is 3-12, there 3 means hex 1
Soo we want also A there which in this case is range 9 out of 12

That should work better , takes 3 instead 2 sec but successfully trains it
The bios can then potentially still freeze, but at least the board posts and trains better
A CMOS reset is worse and wipes CBS on failsafe post 

PMU vref part i still need to learn
Probably we can gain a better training out of it too


----------



## ManniX-ITA

Veii said:


> PMU patterns always set to A
> There the range is 1-9 , A-C


Made a simple test and had to clear CMOS 
PMU pattern is 1-10 on MSI... I've set it at 10=A

Have to check MBIST part.

Opened a thread for WHEAService and put it in the signature 

@lmfodor 
Try with WHEAService if you can run FCLK 1933+
Of course at your own risk but you seem a brave one 



lmfodor said:


> The last thing I modified was to enable the 1T GDM Disabled and with the "miraculous" 56-56-56 that then leads to -56-0-12 with tCKE 16 to achieve better latency, which in fact thanks to @ManniX-ITA tests with AIDA64 achieves the same, 54.4ns almost always. Excellent Mannix!


Nice!


----------



## ManniX-ITA

I've set this one nice little 4066 MHz puppy as my daily:

















Still living the dream!
Tested only for 5 TM5 cycles.


----------



## Veii

ManniX-ITA said:


> I've set this one nice little 4066 MHz puppy as my daily:
> 
> View attachment 2490638
> View attachment 2490639
> 
> 
> Still living the dream!
> Tested only for 5 TM5 cycles.


Glad we develope and push further
Somebody (the mass) has to show AMD that their 1900 FCLK lock attempt was a mistake and should never be a thing again

I wonder if 1202 finally lifts it for Matisse
These things should be capable of running 1966 while ours are capable of 2067 XMP 1:1
If values are predicted well and EDC Fuse limit increases a bit

Thats how it has to be, not sub 1900 for nearly 3 generations 😐
Even a 2700X could reach 1900, with a lot of work, but there the hardwall was at 1867
Here the hardwall is at 2167, 2133 being very hard to get stable

Still have an 1200AF untested
Would love some 1900 FCLK on 12nm :^)
Apparently this rewrite should give 2 FCLK steps more, soo i belive it only when i see it

Still have a fight with them for two things

AmiSetupVar locking us out on system SPI flashes ("for security reasons")
Forbidding every boardpartner to revive X370 for Vermeer, Cezanne & Warhol 😐

It really needs another big library and collection of fully opened bios updates, down to the X370 line

@ManniX-ITA i wanted to ask you
Dont you have a Type-C port
Wouldnt you like to UEFI module disable the problematic NIC and run a Type-C adapter as for WHEA #19 wipe, confirmation ?
Could make you the rom edit

Better than wiping it's flashchip after all ^^"


----------



## ManniX-ITA

Veii said:


> Glad we develope and push further
> Somebody (the mass) has to show AMD that their 1900 FCLK lock attempt was a mistake and should never be a thing again


Absolutely idiotic...
Pretty sure my 3800x could do 1967 MHz without problems.



Veii said:


> I wonder if 1202 finally lifts it for Matisse


Don't think so, didn't see anyone reporting success on the AORUS thread
Pretty sure, not 100%, I tried 1.2.0.2 on the 3800x with the Master and no change
Maybe this delayed 1.2.0.3 will bring some improvement? Hard to say


----------



## ManniX-ITA

Veii said:


> @ManniX-ITA i wanted to ask you
> Dont you have a Type-C port
> Wouldnt you like to UEFI module disable the problematic NIC and run a Type-C adapter as for WHEA #19 wipe, confirmation ?
> Could make you the rom edit
> 
> Better than wiping it's flashchip after all ^^"


Sure I have, using it for the USB SSD but it can run also on any other port.
Do I really need a Type-C NIC?
Have plenty of USB Type-A 5 GBps Gigabit adapters. Realtek of course...

Always ready to make dangerous stuff 
The BIOS is A21O for the Unify-X:





MEG B550 UNIFY-XA21O.zip







drive.google.com





Is it just removing the EFI UNDI from the package?


----------



## T[]RK

Veii said:


> MSI Dragon Ball ~ universal ?


Nope. Tested it on my GIGABYTE B450M DS3H v2 and got error: "Do not support this platform". MSI no like GIGABYTE. =)


----------



## adversary

I posted some time ago (and already posted first picture, but I post it again for compare) my so far stable overclock on 5600X on 3800/1900.

Note - at first picture L3 actually get better score than it was average for whatever reason, speeds was lower and latency was usually 11+
However at this latest tuning, L3 is always 10.7 and speeds are about same (have slight variance, but it is always 600+)

In first one RAM latenc was 52.3-52.4, at second and latest on it is 51.9-52.0, there is no more variance ever besides that 0.1. No Safe Mode. Win10 20H2.

This is still on Agesa 1.2.0.1 Patch A

Changes I did :
1 - CAD BUS set 60-20-20-20 instaed of 60-20-30-20, but started to use CAD timings of 3-3-15. Seems like latency is slightly worse in this case, but stability is increased. Now it tolerate RAM temperature of 37C under stress (in my previous post I explained very detailed how temperature played big role on this B-Die memory, and RAM is watercooled), and it can operate at 1.57V instead of 1.6V

2 - tested to put manual PBO limits as 175-145-400 (EDC is 400 so). boosted L3 in Aida64 pretty good, and seems to improved latency just slightly

3 - started using Curve Optimizer. Helped also L3 and RAM latency. Maybe biggest impact of all which I did. And this CPU is pretty bad bin in my opinion (from what I tested before, how much voltage it require to run fixed speed - it was just test, I do not run fixed speed all core overclock - compared to another users speeds and voltage requirements this one is crap), good watercooling however helps it to overcome that partially


Again this is tested very intensive with Y-Cruncher, Prime95 LargeFFT, SuperPI 1.5, and this time TM5 with 25 cycles 1usmus, and AntaExtreme for some cycles, 0 errors.
After all tests I usually run game at lowest details, lower resolution, remove fps cap - 0 problems, no stutters, no crackling sound

I did, just for test, try to return Tcke to Auto (which end as 1). It freeze even during Aida64 test. At Tcke 9 all seems super stable all around. Interesting.


I mentioned previously water chiller is planned. Now, unit is bought and it is on my friend adress, soon it should be with me. It will help to maintain this setup setting during summer (and during colder period, it would be possible to go even more aggressive with Curve Optimizer). Because ambient temperatures will still arise in next period, so it is questionable would this setting be still stable as for B-Die every degree can play a role. With chiller, even in worst summer, there is no worry I will have to pull down any settings, same settings as now will be possible.

However, because temperature is so important for RAM and Curve Optimizer, while waiting for chiller to arrive, I tested so far with mobile aircondition unit, simply by pointing it at watercooling radiator, hugely lowering temperatures.

Clock speeds go further up, Curve Optimizer is possible to go also more aggressive resulting in even more clock speed, but latency do not go below 51.9ns

Lowering any of primary timinigs, additionally cooled or not, do not produce better result also, interesting.

Seems like I reached some limit with this settings. However, I do not object, performance for me is more than enough, all is stable, I try it mostly for sake of experimenting and overclocking.

For my motherboard, AGESA 1.2.0.2 is still in Beta, so I will not do any upgrade until there is Stable version.

@Veii mentioned some IPC improvements with 1.2.0.2 ? Also different RZQ values for RTT ? I now run 6/3/3, I guess I would have to go for higher divider, but again who know how it will overall behave once BIOS get updated

I read all time this thread and discussion why 3800/1900 is not stable or error free in number of users. I also can't go more than 3800/1900, 3866/1933 can post sometimes if all timings are totally relaxed, but no matter timings, voltages, or whatever, it throw number of different errors all time. Is that due to motherboard, bad cpu bin, current BIOS, 20H2 Windows10, is beyong my knoweledge.

All I could get is to try to get most of 3800/1900. Once soon chiller arrives, I also have 15 W/mK new thermal pads which I will use on RAM instead of EKWB 2.5 W/mK, should help at least some.
Also, EKWB RAM Monarch is not nearly perfectly flat with RAM thermal heatsink adapters. Instructions say to use thermal paste there and I used best one I have Thermal Grizzly Kyronaut, but gaps are huge - it have to be machined to make it flat and that is what I will do.

Going direct flat aluminium to aluminium sure will be better than filling such gaps with thermal paste (but I will still apply paste of course).
This could also be reason why at moment there is about 0.7C difference between RAM sticks.

Stay tuned <3


----------



## Ezalor

Hello! First post, been following this thread for a long time, trying to learn and become better at understanding memory settings in order to dial in a decent memory overclock.

The knowledge among all who contributes here is truly fantastic.

I have been semi-sucsessful with my own attemts, although i was very close to make a post here to see if i could get some tips to have my modest clocking attemt 100% stable, wich it isn't. (Running 3800/1900 16-16-16)

Just yesterday i discovered that i might have a big problem with my system: (5950X, Gigabyte X570, 4x8 B-die), that prompts me to having to reach out to you guys for help.

Aida64 reports write speeds that are indicatory of a 1 CCD cpu. 
Read 59200, Write 29000, Latency 55.7

Read and latency is fine, but write is quite clearly messed up.

I have been countless times going through Bios to try to find something wrong, but the only thing that should be able to affect this is the setting for disableing one CCD, but that is not done of course.

Anyone with any idea what this could be? I am fearing that the cpu might be faulty in some way.


----------



## lmfodor

ManniX-ITA said:


> Made a simple test and had to clear CMOS
> PMU pattern is 1-10 on MSI... I've set it at 10=A
> 
> Have to check MBIST part.
> 
> Opened a thread for WHEAService and put it in the signature
> 
> @lmfodor
> Try with WHEAService if you can run FCLK 1933+
> Of course at your own risk but you seem a brave one
> 
> 
> 
> Nice!


Hi Manix! Yes of course I will try it . I’m fact I downloaded the WHEA Service, installed it and then.. I don know what to do. I see the service lowered but when I try to start it up I won’t. How should I use it? It some kind of WHEA blocker??  

Great job Mannix. I’m following you! Sadly I have this issue with the LLC and voltages.. I’m able to play games but.. after a couple of hour I had a BSOD with error 41. For me it some kind of current spike or vdroop. Something basic. I hope I could fix it to continue testing+1933. 

Thanks!!


Sent from my iPhone using Tapatalk Pro


----------



## lmfodor

ManniX-ITA said:


> I've set this one nice little 4066 MHz puppy as my daily:
> 
> View attachment 2490638
> View attachment 2490639
> 
> 
> Still living the dream!
> Tested only for 5 TM5 cycles.


Wow! Congrats! Tell me, how you handle the WHEA errors 19, I mean reduced it? I will try it later! My mobo has the Realtek, when I increase the FCLK to 1933 I got a lots of WHEA..


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

lmfodor said:


> Hi Manix! Yes of course I will try it . I’m fact I downloaded the WHEA Service, installed it and then.. I don know what to do. I see the service lowered but when I try to start it up I won’t. How should I use it? It some kind of WHEA blocker??


Don't do anything, just reboot and set an higher FCLK 

But indeed if you are facing other issues it's better not to mix.
Actually until you solve it would be better to uninstall WHEAService to get the errors logged, just in case.
Once you are sure it's fine you can try going up.



lmfodor said:


> Wow! Congrats! Tell me, how you handle the WHEA errors 19, I mean reduced it? I will try it later! My mobo has the Realtek, when I increase the FCLK to 1933 I got a lots of WHEA..


They are "silenced", Windows will not process them and therefore will not get clogged and unresponsive.
Maybe give it a try but solve first the other issue.


----------



## Taraquin

ManniX-ITA said:


> Absolutely idiotic...
> Pretty sure my 3800x could do 1967 MHz without problems.
> 
> 
> 
> Don't think so, didn't see anyone reporting success on the AORUS thread
> Pretty sure, not 100%, I tried 1.2.0.2 on the 3800x with the Master and no change
> Maybe this delayed 1.2.0.3 will bring some improvement? Hard to say


I think I've seen a guy who had his 3800X running at 3866/1933 stable on a beta bios, but nobody above that. On my 3600 I could run 3733/1866 with soc at 1.06v and iod/ccd 825mv, 775mv vddp. 3800/1900 was a bit unstable (random reboot at idle once or twice a day) at 1.15v soc, 1.1v iod and ccd/vddp at 950mv and 900mv. Anything below that soc/iod would crash instantly or not boot, going higher didn't improve stability. On my 5600X I can run 3800/1900 stable at 1.02V soc, 980mv iod, 860 ccd and vddp. Going up to 4000/2000 requires 0.08V soc and 0.04V iod. If I set it below everything is stable, but I get higher latency. Seems AMD build in some sort of protection mechanism that makes it rock stable, but reduce perf if voltage is too low. This should be possible to do on Zen 2 aswell if AMD wants as I/O-die is basically the same unless there is some major HW differences on the chiplets which works diffently with voltage-scaling etc between Zen 2 and 3. Veii might know more?


----------



## ManniX-ITA

adversary said:


> 2 - tested to put manual PBO limits as 175-145-400 (EDC is 400 so). boosted L3 in Aida64 pretty good, and seems to improved latency just slightly


Are you running static OC?
Cause the L3 latency is dictated by the max single core boost on Core 0.
If it's a static 4850 MHz then 10.8ns is just right.
But if you are using PBO could be it can be improved, I don't remember which is the fMAX frequency.

If you have the "cTDP" control in the BIOS you can set it to 400W and it will boost L3 speed as well on top of higher EDC.


----------



## lmfodor

ManniX-ITA said:


> Don't do anything, just reboot and set an higher FCLK
> 
> But indeed if you are facing other issues it's better not to mix.
> Actually until you solve it would be better to uninstall WHEAService to get the errors logged, just in case.
> Once you are sure it's fine you can try going up.
> 
> 
> 
> They are "silenced", Windows will not process them and therefore will not get clogged and unresponsive.
> Maybe give it a try but solve first the other issue.


Wow! Amazing. I wonder why the service doesn’t start when I boot up.. I installed but I didn’t know that to do. It is supposed that it will start only? I have a profile saved it with an stable 4000/2000 config. I will try it! 

Thanks 


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

Taraquin said:


> I think I've seen a guy who had his 3800X running at 3866/1933 stable on a beta bios, but nobody above that. On my 3600 I could run 3733/1866 with soc at 1.06v and iod/ccd 825mv, 775mv vddp. 3800/1900 was a bit unstable (random reboot at idle once or twice a day) at 1.15v soc, 1.1v iod and ccd/vddp at 950mv and 900mv. Anything below that soc/iod would crash instantly or not boot, going higher didn't improve stability. On my 5600X I can run 3800/1900 stable at 1.02V soc, 980mv iod, 860 ccd and vddp. Going up to 4000/2000 requires 0.08V soc and 0.04V iod. If I set it below everything is stable, but I get higher latency. Seems AMD build in some sort of protection mechanism that makes it rock stable, but reduce perf if voltage is too low. This should be possible to do on Zen 2 aswell if AMD wants as I/O-die is basically the same unless there is some major HW differences on the chiplets which works diffently with voltage-scaling etc between Zen 2 and 3. Veii might know more?


I can run 1967 MHz with my 3800x but with WHEA errors.
Have more issues running at 1933.
Not sure, maybe it's Realtek there too 
I have a Master with both Intel and Realtek maybe I should zap the RTL.


----------



## ManniX-ITA

lmfodor said:


> Wow! Amazing. I wonder why the service doesn’t start when I boot up.. I installed but I didn’t know that to do. It is supposed that it will start only? I have a profile saved it with an stable 4000/2000 config. I will try it!
> 
> Thanks
> 
> 
> Sent from my iPhone using Tapatalk Pro


Again, you don't have to do anything!
The service is starting and stopping itself.
It's not meant to keep running, there's no need.
I'm not Microsoft or nVidia doing stuff just to gather telemetry 
It will disable the sources in a few seconds and it's done.


----------



## Taraquin

ManniX-ITA said:


> I can run 1967 MHz with my 3800x but with WHEA errors.
> Have more issues running at 1933.
> Not sure, maybe it's Realtek there too
> I have a Master with both Intel and Realtek maybe I should zap the RTL.


Interesting! No instability? Only wheas? Maybe the latest agesas must have implemented the stability protections for Zen 2 aswell then?


----------



## PJVol

ManniX-ITA said:


> The service is starting and stopping itself.


Hi!
Cant start that daemon unfortunately )) install.log says System.Security.SecurityException. It can't get access to Security and State logs.
I have made two runs of Membench with LatencyMon with vdd18 auto (presumably 1.8) and 2.05(proved kinda stable  ).
Can you or anyone else familiar with those ISR's and DPC's point to where to look for abnormal behavior in these screens ?
I don't know how the good results should look like, because I am not sure my Windows's fine at all those latency tests.


----------



## ManniX-ITA

Taraquin said:


> Interesting! No instability? Only wheas? Maybe the latest agesas must have implemented the stability protections for Zen 2 aswell then?


Quite stable but lots of WHEA, it was like that since the beginning not a new thing.
The difference with the latest AGESA was that I could randomly run 1933 MHz, before it was an 100% POST failure.
But still some random WHEA even if much less than 1967.


----------



## Veii

Taraquin said:


> This should be possible to do on Zen 2 aswell if AMD wants as I/O-die is basically the same unless there is some major HW differences on the chiplets which works diffently with voltage-scaling etc between Zen 2 and 3. Veii might know more?


Its not being confirmed, i think ?
That K19.2 is unique to Vermeer and not Matisse

I've been telling fairytales multiple times and also 1usmus did mention artificial limits to begin with
Matisse is 1900 FCLK hardlocked
Was since the beginning and maybe still ? is

They hardlocked it to make PCIe 4.0 run and push the industry forward
1933 and maybe 1966 should be just as fine for it
But going beyond 1.15v has negative scaling and beyond 1.2v is dangerous, there

Vermeer has borrowed many characteristic's but is more like a 2700X here
Matisse was a powersaving unit to begin with
It utilized many of Vermeers boosting methods, but the silicon was too weak to utlize them well
Sadly i'm not sure about dLDO functionality on it
Would be awesome if it was a hidden Ace card on it and it actually exists

Vermeer has 30+ monitorings
And 20+ sensors. It is more than fantastic at autocorrection and frequency balancing
Aside from having "hardware ecc" support

Currently it runs at 60-65% of its capability
After 1202 around 70%. They can do more
But users would be scared to see 1.75v bursts
Probably a Warhol thing then , depending if it will be N6 or N5 substrate 🤔🤐
Part of the boosting algorithm that can be told in fairy tales and esoteric theories, is up yo 1.95-2v
But 1.75v bursts are more mythological than 1.95v fairy tailes
More likely to ever happen in some history line 🙈

@ManniX-ITA dont forget that 2000+ FCLK and PCIe 4.0 are no good friends 

@adversary tCKE 9, 6-3-3 (6-3-6) , x-20-20-20, 3-3-15 (4-4-18) is really great, isnt it 😊
Now with the new changes you can weaken RZQ to something weaker (higher divider)
And drop prcoODT one more down ~ towards 34ohm


----------



## lmfodor

[


> USER=538195]@ManniX-ITA[/USER] i wanted to ask you
> Dont you have a Type-C port
> Wouldnt you like to UEFI module disable the problematic NIC and run a Type-C adapter as for WHEA #19 wipe, confirmation ?
> Could make you the rom edit
> 
> Better than wiping it's flashchip after all ^^"


Hi @Veii! I’m interested to modify the ROM to try to disable the NIC, if you can do it for an asus cross hair Hero Wifi, I will test it! What about the type-C connector, for what it is needed? 

Count on me! New mobos are comings  so I would like to test with the CH8.. I would be great 

Thanks 


Sent from my iPhone using Tapatalk Pro


----------



## ManniX-ITA

PJVol said:


> Cant start that daemon unfortunately )) install.log says System.Security.SecurityException. It can't get access to Security and State logs.


Permissions?
Did you use the MSI installer?



Veii said:


> @ManniX-ITA dont forget that 2000+ FCLK and PCIe 4.0 are no good friends


Actually I did 
But it's not a problem since nVidia doesn't want to sell me a new GPU, they have a thing with miners.

BTW didn't try much but at 2T my kit could run 4000CL14... it's another interesting option if I have to scale down the FCLK for PCIe 4


----------



## adversary

ManniX-ITA said:


> Are you running static OC?
> Cause the L3 latency is dictated by the max single core boost on Core 0.
> If it's a static 4850 MHz then 10.8ns is just right.
> But if you are using PBO could be it can be improved, I don't remember which is the fMAX frequency.
> 
> If you have the "cTDP" control in the BIOS you can set it to 400W and it will boost L3 speed as well on top of higher EDC.



No, as explained, I run PBO. I mentioned all core overclock (static) just as very short test when I bought and started CPU, just to see how capable it is (and its pretty bad).

Interesting thing is this. If I run Curve Optimizer and PBO from Advanced Options (AMD Overclocking), it do not do "EDC boost".

Have to set PBO limits from AI Tweaker, at same time, and than "EDC boost" works. Is that normal?

For me it runs 10.7ns latency L3. As mentioned, with airconditioner test and lower temps, Curve Optimizer can be pushed forward stable (and anyway CPU boost higher because of lower temps), but L3 is still 10.7, no any core goes above 4850 Mhz ever. Lower temps plus (or) more aggressive Curve Optimizer, just run average of all cores boost higher, but still caps at 4850 max.

Pardon me for my limited knoweledge, but where could I find cTDP ? Roughtly if you have some hint.


----------



## ManniX-ITA

adversary said:


> Pardon me for my limited knoweledge, but where could I find cTDP ? Roughtly if you have some hint.


It's an option in AMD CBS menu.
I bought a B550 TUF Gaming Plus for my niece and I think I've seen the CBS menu somewhere.

Check in HWInfo under Main:










Maybe the Fmax for the 5600x is 4650 MHz, I'm not sure.
If it's higher you should be able to boost more.


----------



## adversary

Veii said:


> @adversary tCKE 9, 6-3-3 (6-3-6) , x-20-20-20, 3-3-15 (4-4-18) is really great, isnt it 😊
> Now with the new changes you can weaken RZQ to something weaker (higher divider)
> And drop prcoODT one more down ~ towards 34ohm



indeed it is 
seems like, for a small latency penality, provide very solid gain on stability when you push some settings towards extreme

I will test with RTTs and ProcODT as you say

However, I remember very well that weaker/higher divider from 3 on RttPark do not post at all, going from 6/3/3
If RttWr is set to 2, than RttPark 5 is possible (6 still not working)
but I will test more combinations including ProcODT and see what is possible and what isn't, and if there is any gains

wonder what 1.2.0.2 will bring. it is already for one month available for my motherboard but only in Beta


----------



## PJVol

ManniX-ITA said:


> Permissions?
> Did you use the MSI installer?


Yea, installer seem to work. Does this look like the service doing right ?


----------



## adversary

@ManniX-ITA 














I will check now in BIOS for setting you mentioned, and test it if I find itm, tnx


----------



## ManniX-ITA

adversary said:


> I will check now in BIOS for setting you mentioned, and test it if I find itm, tnx


What a pity, I thought it could go up at least another 100 MHz.
Unfortunately the greedy AMD sales department blocked the board manufacturers trick to set the PBO boost clock over 200...


----------



## ManniX-ITA

PJVol said:


> Yea, installer seem to work. Does this look like the service doing right ?


Yes indeed, some sources will fail to disable but that's normal.


----------



## adversary

@ManniX-ITA

I found it under Advanced > CBS > NBIO Common > SMU Common

set from Auto to Manual and set 400W

however, seems that is changes nothing, I'm testing over and over again for some time

in HWInfo it still state TDP limit as 65W

mind you, setting EDC to 400, trick do not work if it is set from Advanced > AMD Overclocking > and whatever leads to PBO there
it have to be set from AI Tweaker to 400 to work

Speaking of max CPU Mhz, in Curve Optimizer PBO options in Advanced > AMD Overclocking, +200Mhz is max possible you can set
in AI Tweaker PBO options you can set way higher but it do nothing it seems. I think it is set at moment there to +350

should I leave cTDP to 400W anyway or?


----------



## ManniX-ITA

adversary said:


> should I leave cTDP to 400W anyway or?


Use Sandra Inter-Thread efficiency processor test to see the higher bandwdith.
Compare with and without, you should see a sizeable difference.

I think you can still sett more than 200, like in MSI bios, but it doesn't work anymore.


----------



## Requiem4u

Ezalor said:


> Hello! First post, been following this thread for a long time, trying to learn and become better at understanding memory settings in order to dial in a decent memory overclock.
> 
> The knowledge among all who contributes here is truly fantastic.
> 
> I have been semi-sucsessful with my own attemts, although i was very close to make a post here to see if i could get some tips to have my modest clocking attemt 100% stable, wich it isn't. (Running 3800/1900 16-16-16)
> 
> Just yesterday i discovered that i might have a big problem with my system: (5950X, Gigabyte X570, 4x8 B-die), that prompts me to having to reach out to you guys for help.
> 
> Aida64 reports write speeds that are indicatory of a 1 CCD cpu.
> Read 59200, Write 29000, Latency 55.7
> 
> Read and latency is fine, but write is quite clearly messed up.
> 
> I have been countless times going through Bios to try to find something wrong, but the only thing that should be able to affect this is the setting for disableing one CCD, but that is not done of course.
> 
> Anyone with any idea what this could be? I am fearing that the cpu might be faulty in some way.


How To Enable All Cores in Windows
Check this.


----------



## domdtxdissar

Regarding the disabling of windows WHEA-error reporting.
In my testing there is a reason why they are there above 1900 for my setup.

When i turn the reporting off and run 1933 only the bandwidth scale, not latency (it gets worse compared to 1900)















Rest of the numbers also look funky.. Auto correction in action it seems, and not 100% stable
Back to my tested 1900 t1 flat cl14 for me..

_edit_
Compared to my 1900 settings:


----------



## mirzet1976

adversary said:


> @ManniX-ITA
> 
> I found it under Advanced > CBS > NBIO Common > SMU Common
> 
> set from Auto to Manual and set 400W
> 
> however, seems that is changes nothing, I'm testing over and over again for some time
> 
> in HWInfo it still state TDP limit as 65W
> 
> mind you, setting EDC to 400, trick do not work if it is set from Advanced > AMD Overclocking > and whatever leads to PBO there
> it have to be set from AI Tweaker to 400 to work
> 
> Speaking of max CPU Mhz, in Curve Optimizer PBO options in Advanced > AMD Overclocking, +200Mhz is max possible you can set
> in AI Tweaker PBO options you can set way higher but it do nothing it seems. I think it is set at moment there to +350
> 
> should I leave cTDP to 400W anyway or?


Or you can go to the previous version of BIOS with agesa 1.1.9 where there is no such restriction with CPU override, I'm still on agesa 1.1.9.0 with no USB dropout and I've never even had this problem with this board.


----------



## adversary

@mirzet1976

your picture also show 65W for TDP

I can bypass TDC, EDC, PPT

maybe best thing, like ManniX-ITA suggested, is to first run Sandra Inter-Thread efficiency processor test to see if there are changes or not

EDIT - or you mean to override max +200 CPU Mhz overclocking offset?


----------



## adversary

@Veii 

did some tests with RTTs and ProcODT, but nothing special seems to be possible

RttNom can go higher to 7, but nothing changes with it
RttPart can't post at 4 or any higher divider, unless RttWr is set to 2
setting different ProcODT did not change this
I set ProcODT to 34 now, did number of Aida64 tests, but latency is same

how to exactly determine which value is perfect for current settings, I don't know

I did not have much time, but did some Y-Cruncher tests, than Y-Cruncher with just FFT + N64 for 30 minutes (as you suggested to someone, that 10-15 minutes should already reveal instability if there is any), and have about 6 cycles of TM5. Did not have time for more now. Nothing changes compared to 36.X ProcODT, 34 seems also full stable


----------



## TimeDrapery

Veii said:


> Spoiler
> 
> 
> 
> It was written on my phone, sadly the Alpha powerplan with 4% idle atates & 5150Mhz limit, i dont have on my phone. Currently outside
> Its somewhere lost on this Thread
> "Vermeer_LowPower-Alpha"
> Bookmark the NIC complain if you haven't, first half of it is rather educational
> 
> Figured something extremely interesting before going out
> This older picture showing tMAW addressing
> Has a very interesting behavior
> 
> On tRFC 218, 200K is 546 tRC_Page
> 900K goes down to as low as 115 RC_PAGE
> Unlimited and & untested do "nothing*
> But these actually do some changes ti RC_PAGE and i think it depends on tRFC range what works there
> Either tSTAG or tRFC
> 
> The interesting part of all this is, that there is a range and we can take this and use it for calculation
> I forgot who had tRC_Page (tMaw.tMac) in their sheets if it was Ron or Dom
> But we'd need this information. Can better up timings with it and control it better
> 
> As for AMD for MBIST menu,
> Pattern A & Aggressor 5 are even better than 9 & 1
> I mistook hex with decimal, it's range is 3-9 and A-C = 3-12 value
> Bettered it up and this made memory training even better, soo currently (today) jumped from 3333 to 3400CL12-12-12 @ 55ns
> Quite low for such a low MT/s 😊
> 3400 is tCKE 4, 5 doesn't want to work
> Its on full powerdown mode, not just Aggressive Powerdown without nornal powerdown togglr
> 
> @craxton for me its 9 different types of WHEA's
> I forgot on the ITX probably around 5-6
> WHEA 20 I really think means nothing
> Haven't had 18s , gladly


@Veii

The calculator sheet that @Ramad shared contains two tRCPAGE formulas, one based on die density and one "generic"

Another footnote on his sheet states that acceptable values for MAC are as follows:



> 200K, 300K, 400K, 500K, 600K, and 700K


The formulas multiply MAC by 1000 because it's entered as a value of 200, 300, 400, etc. on his calculator sheet (so 200 × 1000 = 200000, for example)

Assuming that tMAW is a product of the following:



> tMAW = 8192 × tREFI


The formula based on die density looks like:



> tRCPAGE = ((tMAW *[in ns]* - tRFC *[in ns]* × (tMAW *[in ns]* ÷ tREFI *[in ns]*)) ÷ (MAC × 1000)) ÷ (2 × 1000 ÷ memory speed *[in MT/s]*)


The "generic" formula looks like:



> tRCPAGE = (tMAW *[in ns]* ÷ (MAC × 1000)) ÷ (2 × 1000 ÷ memory speed *[in MT/s]*)


The footnotes in his sheet state that both formulas were sourced from AMD but, unfortunately, no links or further info is provided... @Ramad, would you happen to have the URLs for your source material? If so, would you please share it if you've the time?

I'll check on FCLK unlock on AGESA 1.2.0.2 for Matisse when I'm back at the house

Hope this helps! Even if it just rules out two possibilities that's progress 😁😁😁😁😁



craxton said:


> Spoiler
> 
> 
> 
> ABSOLUTLY, infact already have lol, and a few others...
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> but this is something that im sure ALOT will thank, and hate about as well, no need to explain but some cant let go that they have errors period. (Id be one of those if i were seeing WHEA out the arse) I trust Veii analysis that these errors have nothing to do with a fault in the CPU That's...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> CoreCycler - tool for testing Curve Optimizer settings
> 
> 
> Here's v0.8.0.0 RC4, only use it if you're willing to beta test. 👆 https://github.com/sp00n/corecycler/releases/tag/v0.8.0.0-RC4 @Theo164 It's interesting, I've never been able to have Y-Cruncher actually fail a stress test. It's either passing for me or rebooting the whole system. 🤷‍♂️ And...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Opposite. The cooler pressures in the center only. AUROS retweet back then about LGA and PGA But the actual illustration fits The center and the sides where bent higher when they where send to the factory The heat and pressure clamps then went strongly into the layers The center was pushed...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> craxton Thank you for your recommendation. I did Prime95 for 7.4 hours and there is no errors. Do I need to test it longer? you see, thats Veii one of the two i mentioned...as you can see he said ALOT of things in which will be hard to understand as i dont understand some of what was said...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> the other few i have are just stuff i thought id use eventually, and some are just comparisons lol...but none the less, others should mark these pages too...


@craxton

DONE AND DONE! Good look!


----------



## Speede

Bought a new kit F4-3600C14D-16GTZNB dated March 2021. Was able to set up 2 options with and without gdm. Without gdm, I can’t pick up resistances on 3800.


----------



## ManniX-ITA

domdtxdissar said:


> Rest of the numbers also look funky.. Auto correction in action it seems, and not 100% stable


You probably need to adjust the voltages.
But could also be it's not stable.
I'm still fiddling with it cause I had a big drop in performances, except memory.
Now I'm at the same level but I know it can go better cause with AGESA 1.x it was scaling up.
It's not easy peasy.


----------



## Ramad

TimeDrapery said:


> The footnotes in his sheet state that both formulas were sourced from AMD but, unfortunately, no links or further info is provided... @Ramad, would you happen to have the URLs for your source material? If so, would you please share it if you've the time?


I don't have a direct URL to AMD's patent but have the document itself, you can search for *Patent No.: US 9.281,046 B2 *dated *Mar. 8, 2016 *or download my copy from this link : 








US9281046


MediaFire is a simple to use free service that lets you put all your photos, documents, music, and video in a single place so you can access them anywhere and share them everywhere.



www.mediafire.com





It's a good read, but the information you are looking for is at *page 12* which reads:


Spoiler
















MAC is not detailed in every die data sheet, depending on manufacturer, but Micron does in their data sheets and it reads:


Spoiler















tRC_PAGE = 0 in the BIOS is the meaning of *Unlimited* in the data sheet.

See page 133, Link: https://www.micron.com/-/media/clie...ducts/data-sheet/dram/ddr4/8gb_ddr4_sdram.pdf


----------



## TimeDrapery

Ramad said:


> Spoiler
> 
> 
> 
> I don't have a direct URL to AMD's patent but have the document itself, you can search for *Patent No.: US 9.281,046 B2 *dated *Mar. 8, 2016 *or download my copy from this link :
> 
> 
> 
> 
> 
> 
> 
> 
> US9281046
> 
> 
> MediaFire is a simple to use free service that lets you put all your photos, documents, music, and video in a single place so you can access them anywhere and share them everywhere.
> 
> 
> 
> www.mediafire.com
> 
> 
> 
> 
> 
> It's a good read, but the information you are looking for is at *page 12* which reads:
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2490709
> 
> 
> 
> 
> 
> MAC is not detailed in every die data sheet, depending on manufacturer, but Micron does in their data sheets and it reads:
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2490712
> 
> 
> 
> 
> tRC_PAGE = 0 in the BIOS is the meaning of *Unlimited* in the data sheet.
> 
> See page 133, Link: https://www.micron.com/-/media/clie...ducts/data-sheet/dram/ddr4/8gb_ddr4_sdram.pdf


@Ramad 

You rock, dude! Thanks for sharing the patent doc and all the info (I was cruising Google Patents and reading a Samsung doc looking for info on tRCPAGE when I'd noticed your post 😂😂😂😂😂)!

Now I'm off to read the doc you shared! Thanks again!!!


----------



## DeletedMember558271

Veii said:


> @ManniX-ITA i wanted to ask you
> Dont you have a Type-C port
> Wouldnt you like to UEFI module disable the problematic NIC and run a Type-C adapter as for WHEA #19 wipe, confirmation ?
> Could make you the rom edit
> 
> Better than wiping it's flashchip after all ^^"


Really curious about this more than anything.
Will be an interesting future, if everyone is running modified .roms and ethernet adapters.
I'm curious how hard it is to personally modify a .rom to disable it, gonna need a tutorial or something, since it's something that will have to be done every new BIOS release.
Also I'll have to find out what a good ethernet adapter is, my luck buy some **** one with problems. Idk anything about ethernet adapters, never needed one, I'm sure there's lots of trash.

Also for boards such as mine, is it possible to just disable the RTL8125B 2.5G and not the RTL8111H 1G? And the issues will be gone potentially?
That would be optimal if I'm not needing more than 1G, then I don't even need an adapter.


----------



## Ezalor

Requiem4u said:


> How To Enable All Cores in Windows
> Check this.


Thanks for replying.

I do not think that is it, all cores have always been visible in task manager, and my general performance is on par of an average binned 5950x, 10000 points in CB20 stock, 11000 with motherboard limits for instance. If cores would be missing, i would not reach those numbers.


----------



## Eder

Ok on the Unify X570 got all the WHEA 19 crap when going above 1900FCKL with a 5900X.


----------



## TimeDrapery

@Veii 

No dice on booting 1967MHz / 3934MT/s on (my) Matisse CPU (3700X)... Failure to train and eventual kick to the backup BIOS

I'll play with it more and get legit debug codes and whatnot tonight when I'm home again


----------



## DeletedMember558271

Does anyone know the Neody guy on the Zen Sheet? Apparently they were at 1867 FCLK but then 1900 FCLK, I'm curious what made that possible for them.


Spoiler: 1867 ZenTimings

















Spoiler: 1900 ZenTimings














Nothing in the entire right side column changes, all power and voltages everything the same. Idk if they actually just switched 5800X's or never had a problem with 1900 but started on 1867 first for some reason? Motherboard the same too, new BIOS though.
@Neody ? Never posted here


----------



## TimeDrapery

Dreamic said:


> Spoiler
> 
> 
> 
> Does anyone know the Neody guy on the Zen Sheet? Apparently they were at 1867 FCLK but then 1900 FCLK, I'm curious what made that possible for them.
> 
> 
> Spoiler: 1867 ZenTimings
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Spoiler: 1900 ZenTimings
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Nothing in the entire right side column changes, all power and voltages everything the same. Idk if they actually just switched 5800X's or never had a problem with 1900 but started on 1867 first for some reason? Motherboard the same too, new BIOS though.
> @Neody ? Never posted here


Looks like they updated their BIOS on their X470 and then... Voìla


----------



## DeletedMember558271

TimeDrapery said:


> Looks like they updated their BIOS on their X470 and then... Voìla


Maybe but don't thinking updating BIOS has helped anyone else with this issue, and that's not really something I can try since I've updated to every BIOS as they've come out and no voila.
Could be some of the many options in the BIOS not displayed by ZenTimings too they changed, only they would know


----------



## TimeDrapery

Dreamic said:


> Spoiler
> 
> 
> 
> Maybe but don't thinking updating BIOS has helped anyone else with this issue, and that's not really something I can try since I've updated to every BIOS as they've come out and no voila.
> Could be some of the many options in the BIOS not displayed by ZenTimings too they changed, only they would know



😂😂😂😂😂

No, not maybe... His settings remained the same and his BIOS changed... On an X470 it would certainly help to update BIOS...

It doesn't matter what you've tried, that's what the screenshots you posted show

Maybe he increased VDIMM...?


----------



## DeletedMember558271

TimeDrapery said:


> 😂😂😂😂😂
> 
> No, not maybe... His settings remained the same and his BIOS changed... On an X470 it would certainly help to update BIOS...
> 
> It doesn't matter what you've tried, that's what the screenshots you posted show
> 
> Maybe he increased VDIMM...?


😂😂😂😂😂 (what are you a 12 year old tiktok user?)

Yes, yes maybe. You're acting like ZenTimings encompasses all important BIOS settings, not even close. Weird for someone who apparently reads a lot here, you've never seen settings outside of what it displays being talked about here?
BIOS updates haven't helped anyone else with this issue, and it hasn't helped me, not something I can try since I already have.
vDIMM has nothing to do with FCLK.

You're annoying


----------



## TimeDrapery

Dreamic said:


> Spoiler
> 
> 
> 
> 😂😂😂😂😂 (what are you a 12 year old tiktok user?)
> 
> Yes, yes maybe. You're acting like ZenTimings encompasses all important BIOS settings, not even close. Weird for someone who apparently reads a lot here, you've never seen settings outside of what it displays being talked about here?
> BIOS updates haven't helped anyone else with this issue, and it hasn't helped me, not something I can try since I already have.
> vDIMM has nothing to do with FCLK.
> 
> You're annoying


😂😂😂😂😂

Yes, I'm a 12-year-old TikTok user... with higher F/MEMCLKs than you... On last gen componentry...

Why don't you send me your 5800X and I'll send you back my 3700X? That way I can get proper use out of the CPU you're squandering and you can stop crying about your FCLK being oh so impossible to increase any higher

Guess what, dude? If your CPU is jacked... *RMA IT*

If you agree to the sweet, sweet deal I proposed above and ship that lil bub my way it's exactly what I'm gonna do if I find out that you're not wrong and your sample is truly limited to 1867MHz FCLK *no matter what* like you have said _over and over and over_ again and again

No, ZenTimings doesn't contain all important BIOS settings 😂😂😂😂😂... The updated BIOS that dude flashed his (listen closely to this next bit you B550 chipset mobo owner) *X470* mobo with *does* contains all important BIOS settings 😂😂😂😂😂

For someone that finds me so annoying you sure have a hard time not sending me PMs that I don't read... It's ok, secretly... I like me too 😂😂😂😂😂


----------



## Veii

TimeDrapery said:


> Looks like they updated their BIOS on their X470 and then... Voìla
> 
> 
> Dreamic said:
> 
> 
> 
> Maybe but don't thinking updating BIOS has helped anyone else with this issue, and that's not really something I can try since I've updated to every BIOS as they've come out and no voila.
> Could be some of the many options in the BIOS not displayed by ZenTimings too they changed, only they would know
Click to expand...

Could be no change except that newer SMU should have resolved that strange 1900 FCLK hole people seem to have
Although the only indication of anything wrong with it , i could find far back near Patch-C
Is that 1900 strap had completely messed up memory training. One out of 12 reboot attempts started , posted and funnily remain rock stable
2067 at that time was a rather 4/6 restart success with the same outcome

Will get to the remain pings in about 'n hour

I see nothing wrong with his/her score.
bios updates do change quite a bit, but "what is changed & how many of the patches are pushed" - between 56.43 and 56.50
is different between boardpartners and apparently also bioses/boards

Maybe changes don't do anything positive, soo very likely it breaks 3 things while fixing one (yes,quite likely)
But exactly this 4-5 SMU version (43,44,45,46,50) are a complete mess when it comes to consistency tracking
Every boardpartner does or doesn't apply couple of patches, up to users/boards need

Please don't fight over something unclear
even the same SMU version can have 3-4 patches difference and so perform by board, different 
Let's not bring up SMU 56.34 the apparent (yes FCLK lock, no FCLK, yes boost rewrite, No cache rewrite, Patch A,B, AB, C, D) ~ mess that existed 
ABL is a good indicator to see if anything "on the bare surface" changed ~ but reading it out needs access to AMD PBS
ZT only reads out the patch-table, yet not the ABL version injected

While ABL can control from allowed FCLK,
to memory training, secure boot patches, usb assignment, acpi table changes, zen rebrands, and even can push in the hidden a non downgradable PSP Firmware update
~ which nevertheless on which bios version you are, the cpu freq scaling and voltage behaviour will be kept persistent. . . soo also their bugs they introduce (IF)
Oh i should not forget another inconsistency, which is the boosting table ~ that is rewriteable or rewritten by CTR and Ryzen Master ~ or other shady windows update pushed patches

This one also stays consistent between bios updates and even between chipset updates 
Exmpl, CTR 2.0 RC03 & lower, fiasko for frankenstein units ~ which got fixed on RC04


----------



## DeletedMember558271

TimeDrapery said:


> 😂😂😂😂😂
> 
> Yes, I'm a 12-year-old TikTok user... with higher F/MEMCLKs than you... On last gen componentry...
> 
> Why don't you send me your 5800X and I'll send you back my 3700X? That way I can get proper use out of the CPU you're squandering and you can stop crying about your FCLK being oh so impossible to increase any higher
> 
> Guess what, dude? If your CPU is jacked... *RMA IT*
> 
> If you agree to the sweet, sweet deal I proposed above and ship that lil bub my way it's exactly what I'm gonna do if I find out that you're not wrong and your sample is truly limited to 1867MHz FCLK *no matter what* like you have said _over and over and over_ again and again
> 
> No, ZenTimings doesn't contain all important BIOS settings 😂😂😂😂😂... The updated BIOS that dude flashed his (listen closely to this next bit you B550 chipset mobo owner) *X470* mobo with *does* contains all important BIOS settings 😂😂😂😂😂
> 
> For someone that finds me so annoying you sure have a hard time not sending me PMs that I don't read... It's ok, secretly... I like me too 😂😂😂😂😂


Holy you are braindead lol, how did you find your way off LTT forums? You are so lost.
If you're not aware of the 1867 FCLK issue that's ok, no need to be dumb, @ManniX-ITA or @mongoled had it too, the people here who have had multiple samples have noticed different FCLK holes, many people way smarter than you (not that you seem to set the bar very high), and haven't been able to do anything about it. If you were informed you would know, but you're not so you don't.
It's not a personal accomplishment that you got luckier with a silicon lottery, don't confuse it. Also, show me how much you get on 1900 (because you'll probably be WHEA-limited as well) when you stop being poor with your 3700X and 5500XT and get Zen 3. If I had a trash tier poor persons GPU like you I could bump to 1.530v and be 51ns at 3733/1866, but I like playing video games with my 3080 and it gets too hot, suffering from success.

I could try RMAing it though but it's such a hassle


----------



## TimeDrapery

Veii said:


> Spoiler
> 
> 
> 
> Please don't't fight over something unclear
> even the same SMU version can have 3-4 patches difference and so perform by board, different
> Let's not bring up SMU 56.34 the apparent (yes FCLK lock, no FCLK, yes boost rewrite, No cache rewrite, Patch A,B, AB, C, D) ~ mess that existed



@Veii

You're right, I'll stop



Dreamic said:


> Spoiler
> 
> 
> 
> 😂😂😂😂😂😂😂😂😂😂


@Dreamic 

Have fun dude! Please take care and enjoy your journey!


----------



## Veii

Dreamic said:


> when you stop being poor with your 3700X and 5500XT and get Zen 3. If I had a trash tier poor persons GPU like you I could bump to 1.530v and be 51ns at 3733/1866, but I like playing video games with my 3080 and it gets too hot, suffering from success.


Hello i'm _"trash-tier gpu guy"_ 
~ with a GTX 650, who used mostly an intel HD4000 while their 560ti, 770, 980ti died
My type of games & work don't need gpu rendering, only VFX do maybe go back to it


----------



## DeletedMember558271

@TimeDrapery you're also braindead if you think my result is bad, is it a failure that I'm only 1ns behind the other best Dual Rank 3800/1900 results while they're all using 1.550v or more? You wouldn't be able to do better.








And that other result from me is old low effort unoptimized inefficient trash on bloated Windows too so its latency is a lot higher than it should be, I don't even want it on there anymore


----------



## TimeDrapery

Dreamic said:


> Spoiler
> 
> 
> 
> @TimeDrapery you're also braindead if you think my result is bad, is it a failure that I'm only 1ns behind the other best Dual Rank 3800/1900 results while using when they're all using 1.550v or more? You wouldn't be able to do better.
> View attachment 2490744
> 
> And that other result from me is old low effort unoptimized inefficient trash on bloated Windows too so its latency is a lot higher than it should be, I don't even want it on there anymore



Dude! That's great! You're doing such a good job and I'm so proud of you, you keep on going and you're gonna do such great things!!! I can't believe that the mean person maintaining that Sheets doc won't remove the other result you submitted! How inconsiderate!


----------



## DeletedMember558271

TimeDrapery said:


> Dude! That's great! You're doing such a good job and I'm so proud of you, you keep on going and you're gonna do such great things!!! I can't believe that the mean person maintaining that Sheets doc won't remove the other result you submitted! How inconsiderate!


You were the one talking about how good of a job you would do and what great things you've done, ******.
Beat me when you stop being poor and post it
And if you can do it anywhere near 1.450v 3800/1900 Dual Rank, congratulations


----------



## craxton

Dar|{cyde said:


> I'm running stable 3800 right now. I can easily push into WHEA territory, I've just been working on other stuff lately.


so, to be clear, you have had WHEA errors on this board running this setup, with slightly 
different clock speeds on ram?



ManniX-ITA said:


> Yes that´s it, the missing one should be the DeviceDriver source.


i only have the ones i showed...



ManniX-ITA said:


> You need to check content of the message with Event ID 5.


it states 5 error sources are active, error record format is 10...
the rest i didnt note down...



ManniX-ITA said:


> If the active error sources are less than 5 then that's probably why you don't get them.
> But I think you already posted a screenshot and they were 5.


yes, several times actually lol...










ManniX-ITA said:


> Which BIOS version are you running?
> I don't see an AGESA 1.2.0.1 in the support page.


you wont see 1.2.0.1 in the support page at all, since they released 1.2.0.2. update 
they removed it????????

im running tho (E7C91AMS.161) 
which is well, the best yet ive noticed....but all ffrom here before it i 
could run 4000mhz without WHEA, unless (*even with a new install without ANY drives being hooked up)
its still not logging the other events and just 18 and 20.


ManniX-ITA said:


> It's interesting since you should have WHEA since the LAN is Realtek.
> Wonder if there's something special in the UNDI EFI (the Realtek firmware) in that specific BIOS.


unsure, here is a download link for anyone who knows what theyre doing to 
look into what may be different? 
it doesnt have the TXT file but it flashes without issue none the less...



Veii said:


> Inside the operation logger, the way ManniX teached it
> 9 different potential operations
> On the ITX it was 6
> But i get 0 WHEAs


so its almost like all board venders are different?
or is it perboard persay?


Veii said:


> Still have an 1200AF untested


1600af?
i have one which 3800mhz wasnt an issue on......
4100 all core 1.33v stable.


----------



## TimeDrapery

Dreamic said:


> Spoiler
> 
> 
> 
> You were the one talking about how good of a job you would do and what great things you've done, ****.



Oh totally! Then you posted that screen of the publicly available Sheets doc showing your amazing results and I immediately knew I had barked up the wrong tree!!!


----------



## craxton

TimeDrapery said:


> you sure have a hard time not sending me PMs that I don't read


(PSSST) im special  so far only one person, who hasnt responded to a message
from me  but id ignore pm too if i were them.

anyhow, im poor you asshats, with my 2070S (from BEFORE the GREAT 2020-2023 shortages)
with my bargain find NVME adata 8200sx 2tb drives, i work for


Spoiler



walmart packing groceries to your cars


 fellas LMAO
so stop making me feel attacked 



Spoiler



(13.00 an hour here tho, is like 25 an hour other places)


----------



## DeletedMember558271

TimeDrapery said:


> Oh totally! Then you posted that screen of the publicly available Sheets doc showing your amazing results and I immediately knew I had barked up the wrong tree!!!


It's only 1 good result and good you should know that, because if you look at what's around it and think it's a poor result when it's only 1.450v and the slight penalty from not being 1900/3800, you're just dumb, which is obvious. Beat it with the same conditions when you stop being poor and can afford it


----------



## Veii

ManniX-ITA said:


> You need to check content of the message with Event ID 5.
> 
> Which is something like:
> 
> *WHEA successfully initialized.
> 6 error sources are active
> Error record format version is 10.*
> 
> If the active error sources are less than 5 then that's probably why you don't get them.
> But I think you already posted a screenshot and they were 5.
> 
> 
> 
> craxton said:
> 
> 
> 
> yes, several times actually lol...
Click to expand...

This is how it looks for me
9 potential tracking outcomes















No WHEA since quite some time
Also doesn't WHEA when y-cruncher FFT or HNT Errors
The only thing i get if i majory hardcrash (FCLK crash with green-lines)








Strongly unsure if WHEA 20 means anything at all ~ doesn't even have a description
I don't get it, but no idea what i've been running that made it appear
But i've been getting it also on the ITX, rarely
Awkward ~ dual I225-V board , right now at 2100 FCLK ~ but it's silent


----------



## craxton

...something i was thinking about earlier, (THOSE WITH NVIDIA GPU's)

that have usb-c on the back etc, do you guys install the driver for that b.s.?

i dont, only phyx software, and sometimes gforce now.... (would this be something to do 
with those who have issues with USB b.s.???? uninstall it and see if something changes,
yes dead asx serious....you never know...


----------



## TimeDrapery

Dreamic said:


> Spoiler
> 
> 
> 
> It's only 1 good result and good you should know that, because if you look at what's around it and think it's a poor result when it's only 1.450v and the slight penalty from not being 1900/3800, you're just dumb, which is obvious. Beat it with the same conditions when you stop being poor and can afford it



@Dreamic 

😂😂😂😂😂



Spoiler



😂😂😂😂😂



Take care, dude!


----------



## craxton

Veii said:


> but it's silent


hmmm, i really dont wanna unhook my drives again, and create an entire new drive
but i do belive ill do just that this week (tuesday as thats my only day off)
each time ive done so tho, it still only shows the 4 with one being 5 sources are active...

what windows version might you be running?
im currently up-to-date on windows entirely minus preview builds as
well, task man starts doing stupid crap when i use insider builds etc.


Veii said:


> Strongly unsure if WHEA 20 means anything at all


it possibly doesnt, but a hard crash (no BSOD) just straight crashing 
is the only time i get one period. 

i can force 18 and 20 now....these being logged would mean 
WHEA-logger is working.....i would LOVE to believe ...but as manna stated
one might be missing and thats the key logger thats plaguing everyone else?


----------



## Veii

craxton said:


> ...something i was thinking about earlier, (THOSE WITH NVIDIA GPU's)
> 
> that have usb-c on the back etc, do you guys install the driver for that b.s.?
> 
> i dont, only phyx software, and sometimes gforce now.... (would this be something to do
> with those who have issues with USB b.s.???? uninstall it and see if something changes,
> yes dead asx serious....you never know...


Haven't seen USB issues cause any WHEAs
They came after AMDs PMTable rewrite and experimental patches
But only when i mix USB 2.0 and USB 3.0 on a 3.1 port

For example a 2ndary usb mic and my mouse
Or my soundcard and my mouse
High input devices , then it crashes

If i load pre PM-Table rewrite profile , it fully disabled the usb ports
soo making it from scratch on the new bios - made it resolve itself, well kinda
Just don't need to mix down usb devices as there seems to be either a lack of bandwidth to the chipset , or an issue with the XHCI chip (both likely)

And no 
PhysX, and even disabling the nvidia controll pannel DLL + service to "manual trigger"
Nvidia telemetry is usually wiped with NVClean-Installer, or directly packaged by the Guru3D community








527.56 - Clean Version


[IMG] Description: Geforce Clean Version GTX/RTX drivers are cleaned from all the unnecessary bloat NVIDIA has added as of late. Only the core...




forums.guru3d.com




Jumped back to 466.11 because of CUDA, else was running a long time 470 Dev driver
_~ not that it made any difference at all ~_



craxton said:


> hmmm, i really dont wanna unhook my drives again, and create an entire new drive
> but i do belive ill do just that this week (tuesday as thats my only day off)
> each time ive done so tho, it still only shows the 4 with one being 5 sources are active...


The only other thing is suspect for #19, are the new AMI NVMe modules (which have a fix ~ but are supplied afterwards)
I don't suspect usb issues to have anything to do with #19 at all
They are a crashing sideproduct of the attempts to rewrite the PMTable and redesign the GMI routing / interconnect accelerations together with dLDO
Also an attempt to maybe deal with the self-crashing RTL issues

You might be missing one, but hey, good for you 
Less potential issues that will spam DPC calls *
Just need to be more picky about hidden autocorrection
Which will continue to be a thing and is not trackable except by benchmark inconsistency and bad scores
Just bad scores on anything beyond 1933 can also just mean "hitting EDC Fuse limit or first stage EDC limit"
Soo unless you are sure that you have power headroom ~ it can just also be throttling because of "lack of power"

One of the reasons "for now" i'm back at 4.65 with CO
Just to rule that option out of the equation when working towards 2133 daily & then updating to 1202 and redoing everything again 🌝
* i have 9 watchdogs, and am error free ~ less makes the life easier haha


----------



## craxton

Dreamic said:


> Kraft Dinner isn't healthy for you


if you think thats bad, then you aint heard of bread and ketchup.......


----------



## craxton

Veii said:


> You might be missing one, but hey, good for you


if only i could just accept that tho lol, 
ive looked thru c/win/sys32/winev at the log apps itself,
but only the two i see in event viewer for (KERNEL WHEA) is there, 
(no there is LOADS there of other log sources, just those two in general)



Veii said:


> Haven't seen USB issues cause any WHEAs
> They came after AMDs PMTable rewrite and experimental patches
> But only when i mix USB 2.0 and USB 3.0 on a 3.1 port


so an example of this would be, like having my mouse hooked thru usb 2.0 front panel, 
and having my "spare nvme/enclosure" hooked thru usb-c to where it connects and disconnects
but never shows inside partition man, nor inside explorer AT ALL with any usb-c cable 
with speeds over (i think? 480mbs?) thunderbolt cables or whatever theyre called i have 
several brandnew, several from amazon, and several from other places to which work perfectly with my phone etc


i kinda just suspect it to be that ssk sent me the wrong enclosure to which its not really capable of usb-c speeds 
(not long enough to finish any data drive benchmarks anyhow) gets HOOOOTTTT 
just by being hooked up...



Veii said:


> Which will continue to be a thing and is not trackable except by benchmark inconsistency and bad scores
> Just bad scores on anything beyond 1933 can also just mean "hitting EDC Fuse limit or first stage EDC limit


so far, ive not noticed any issues, if im in safe mode scores (ns) is ALWAYS the same. 
if im inside windows normally, it depends on if/what tasks/services i stop at that time and 
not allow restart for the moment. (record myself disabling these so its not the root problem)
if i have one of WHEA not being logged other than 18 and 20...


----------



## glnn_23

Grabbed a different 4650g the other day and have it in a Asus Crosshair Impact.

4533c16 1:1 IF seems to be the sweet spot.

Using custom water it has to be the coolest running Ryzen chip I’ve tested


----------



## Veii

glnn_23 said:


> Grabbed a different 4650g the other day and have it in a Asus Crosshair Impact.
> 
> 4533c16 1:1 IF seems to be the sweet spot.
> 
> Using custom water it has to be the coolest running Ryzen chip I’ve tested
> 
> View attachment 2490752


Good Job !
Can you please check if MSI Dragon Ball, will work for you ?
(They seem to have Asus support, but not every board 🤔)
Else just a free opportunity to grab the latest MemTweakIT
Maybe we can learn something from the powering settings or IMC settings of it (timings aside)








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


I find some of the results on the Zen DRAM Sheet a bit suspicious There are users with the Realtek RTL8111H ~ who have no WHEAs It makes me wonder if HWInfo even tracks the #19's or only #18s which are "real issues" or only 2.5gbit ones are fully affected (Combo unit boards are affected, but...




www.overclock.net





Which version is your TurboV ?
I atm have 1.01.15


craxton said:


> so an example of this would be, like having my mouse hooked thru usb 2.0 front panel,
> and having my "spare nvme/enclosure" hooked thru usb-c to where it connects and disconnects


Type C doesn't have any dropout issues funnily
USB 2.0 Pure , doesn't have any either
It where these 3.0 & 3.1 combo jacks - somehow still randomly having bandwidth share issues

USB 4.0 down to USB 2.0 (device) has no issues at all
Haven't seen any TB4 issues either ~ but i'm still desperately looking for a Thunderbolt Audio interface deal
(nothing TB2 as the TB3 to 2 adapter, seems to cause BSODs on TB4 ~ somebody understand why)


----------



## Speede

Please help stabilize at 3800 without gdm. With gdm it works stably, and with the same timings without gdm it works at 3600 in 2t mode


----------



## Veii

Speede said:


> Please help stabilize at 3800 without gdm. With gdm it works stably, and with the same timings without gdm it works at 3600 in 2t mode


Up your transition timings a bit (tRRD, tWTR, SCL)
Single Rank wants SD,DD's as 1-5-5-1-7-7
with 1-4-4-1-6-6 you leave performance on the table ~ soo it can be pushed masking something else that's maybe not in sync








Green = Change, with altenative options if you CMOS Reset
Orange = Frequency scaled
Red = Faster, but currently used VDIMM was not written ~ soo "success" may need more voltage


----------



## DeletedMember558271

@Veii @ManniX-ITA
Any updates on the modified BIOS to disable Realtek and possibly 1933+ WHEA? Also for dual LAN boards such as mine are we able to disable just the RTL8125B 2.5G if the RTL8111H 1G is possibly fine?
If this works it's huge because we can probably save everyone with modified BIOS they just need an adapter.
We're going to need a tutorial how to mod it ourselves, unless some people are going to do it for all these boards and all the new BIOS that come out for them for everyone


----------



## Veii

Pegasuss said:


> The setup timings is also working for me, I don't think there is any improvement to be made now? Also, 27 setup timings does not boot on my end.
> 
> View attachment 2490267


Increase VDIMM till this posts
Might even be able to lower procODT to 34 afterwards - depends on ClkDrvStr & Mem-Training consistency








Your goal tho should be 14-14-14 flat


----------



## Veii

Dreamic said:


> @Veii @ManniX-ITA
> Any updates on the modified BIOS to disable Realtek and possibly 1933+ WHEA? Also for dual LAN boards such as mine are we able to disable just the RTL8125B 2.5G if the RTL8111H 1G is possibly fine?
> If this works it's huge because we can probably save everyone with modified BIOS they just need an adapter.
> We're going to need a tutorial how to mod it ourselves, unless some people are going to do it for all these boards and all the new BIOS that come out for them


Woke up early, haven't focused on it since yesterdays request
It's not only the simple DXE module that has to be gone, but also to find it's GUID and scan all modules for it
Replace that anchor either wit FF FF FF
Or zero purely the RTL 2.5gbit module (FF, or 00 depending if zero is accepted or some empty data is needed)

Key-Goal is to make it have no association with the bios at all, soo it doesn't matter how often it crashes on itself and reboots
Best practice would be to wipe every anchor that leads to this GUID module - soo it's purely excluded
Only erasing the module, will leave open chains to it which will make the bios sluggish, keep spamming other errors or at worst not even post & fail CRC check


----------



## Speede

Veii said:


> Up your transition timings a bit (tRRD, tWTR, SCL)
> Single Rank wants SD,DD's as 1-5-5-1-7-7
> with 1-4-4-1-6-6 you leave performance on the table ~ soo it can be pushed masking something else that's maybe not in sync
> View attachment 2490755
> 
> Green = Change, with altenative options if you CMOS Reset
> Orange = Frequency scaled
> Red = Faster, but currently used VDIMM was not written ~ soo "success" may need more voltage


tRDWR 7 tWRRD 3 no boot
witch GDM Enable 1.49V
to test GDM Disable 1.53v


----------



## Veii

Speede said:


> tRDWR 7 tWRRD 3 no boot
> witch GDM Enable 1.49V
> to test GDM Disable 1.53v
> View attachment 2490757
> View attachment 2490758
> View attachment 2490759
> View attachment 2490760


I see you test each options individually ?
RTT + SETUP timings + tCKE + CAD_BUS ~ are one block
You still get too many 6 = PCB crash or voltage issue / soo something with the RTTs here is not liked (IF you changed the whole block & not just one option)

Only changing SCL without changing tWRRD will make you issues
only changing CAD_BUS, will overvolt the dimms and crash

tRDWR not functioning means something else overlaps with it still 
SD, DD's work is that part
only they go alone - in theory but if you need to tighten them (increase) then it can be that something else also bothers them

Overall nothing here goes alone

EDIT:
tRFC can go alone, but would still need tWR & tRTP changed
tRTP won't be able to go an odd value with GDM off

The only thing i can see are strange 13 & 11's
11's are either RTT_NOM or tRRD / tWTR issues
Probably GDM off on it's own makes issues because the timings are too low & can't run when internal MUX "chips" run at fullspeed
GDM pushes them at half speed, soo strain is nearly half - and will explain why some timings "look low" ~ but in practice would never run without GDM
Same goes for tRFC

EDIT2:
Soo this as a whole posts ?
Really trying anything "solo" - won't just work 








What is it's error log & what voltage did you end up at ?
* i think we have other things to fix to make GDM off work , GDM on is just cheating and hiding bad powering or bad bad timings

EDIT3:
GDM on , is nice handy and dandy
But if you ever want to go further ~ it's just burden
Usually it doesn't need any voltage increase to get GDM away, but it very well will show issues with your set ~ once you disable that
Soo any work that you did on GDM on, is nearly worthless when you get it away ~ as you'll have to fiddle again with your tertiaries to make it stable 
(real stable not half-time speed stable)


----------



## paih85

Hi @Veii 

This timing can improve more? let say i want to stay this vdimm max @1.45v. 😅


----------



## Taraquin

Taraquin said:


> View attachment 2490515
> 
> This is my best score with all core 4.8GHz.
> View attachment 2490516


Veii or others that knows much more about ramtuning than me: Got any further tips for tweaking, can go max 0.01-0.02V higher on ram volt before overheat. That was not enough for lowering tCL, tRCDRD, tRP or tCWL. Should tRAS always be tCL+tRCDRD, tRC alwas be tRAS+tRP and tRFC=tRCx6 on B-die? Any tweaks on ProcODT, Rtts, drv-strength I might try to lower voltage reqs for primaries?


----------



## DeletedMember558271

paih85 said:


> Hi @Veii
> 
> This timing can improve more? let say i want to stay this vdimm max @1.45v. 😅
> 
> 
> View attachment 2490764


Go for 3800/1900 15-15-15-15-30-45 or 3733/1867 if you can't boot 1900 and 1933+ has WHEA for you.
Should be an easy place to start, probably only need to raise/relax tRFC if anything has major issues I'd bet.
If have issues could check 1.460v or 1.470v temporarily even if you don't want to stick with it, just to see if it is lack of voltage related or something else.
Might need to raise vsoc, ccd, and iod as well


----------



## Speede

Veii said:


> I see you test each options individually ?
> RTT + SETUP timings + tCKE + CAD_BUS ~ are one block
> You still get too many 6 = PCB crash or voltage issue / soo something with the RTTs here is not liked (IF you changed the whole block & not just one option)
> 
> Only changing SCL without changing tWRRD will make you issues
> only changing CAD_BUS, will overvolt the dimms and crash
> 
> tRDWR not functioning means something else overlaps with it still
> SD, DD's work is that part
> only they go alone - in theory but if you need to tighten them (increase) then it can be that something else also bothers them
> 
> Overall nothing here goes alone
> 
> EDIT:
> tRFC can go alone, but would still need tWR & tRTP changed
> tRTP won't be able to go an odd value with GDM off
> 
> The only thing i can see are strange 13 & 11's
> 11's are either RTT_NOM or tRRD / tWTR issues
> Probably GDM off on it's own makes issues because the timings are too low & can't run when internal MUX "chips" run at fullspeed
> GDM pushes them at half speed, soo strain is nearly half - and will explain why some timings "look low" ~ but in practice would never run without GDM
> Same goes for tRFC
> 
> EDIT2:
> Soo this as a whole posts ?
> Really trying anything "solo" - won't just work
> View attachment 2490763
> 
> What is it's error log & what voltage did you end up at ?
> * i think we have other things to fix to make GDM off work , GDM on is just cheating and hiding bad powering or bad bad timings
> 
> EDIT3:
> GDM on , is nice handy and dandy
> But if you ever want to go further ~ it's just burden
> Usually it doesn't need any voltage increase to get GDM away, but it very well will show issues with your set ~ once you disable that
> Soo any work that you did on GDM on, is nearly worthless when you get it away ~ as you'll have to fiddle again with your tertiaries to make it stable
> (real stable not half-time speed stable)


















VDIMM 1.495V


----------



## paih85

Dreamic said:


> Go for 3800/1900 15-15-15-15-30-45 or 3733/1867 if you can't boot 1900 and 1933+ has WHEA for you.
> Should be an easy place to start, probably only need to raise/relax tRFC if anything has major issues I'd bet.
> If have issues could check 1.460v or 1.470v temporarily even if you don't want to stick with it, just to see if it is lack of voltage related or something else.
> Might need to raise vsoc, ccd, and iod as well
> View attachment 2490765


ok. i will try your timing. thanks


----------



## DeletedMember558271

Taraquin said:


> Veii or others that knows much more about ramtuning than me: Got any further tips for tweaking, can go max 0.01-0.02V higher on ram volt before overheat. That was not enough for lowering tCL, tRCDRD, tRP or tCWL. Should tRAS always be tCL+tRCDRD, tRC alwas be tRAS+tRP and tRFC=tRCx6 on B-die? Any tweaks on ProcODT, Rtts, drv-strength I might try to lower voltage reqs for primaries?


And your actual reported vDIMM is 0.01v lower than ZenTimings reports yes? So you started overheating into errors at just 1.460v actual then? If ZT is saying 1.440v right now +0.03v = overheat.
Maybe these 4400C19 Patriot Viper are just the worst heatsinks known to man? Practically overheating at XMP vDIMM. You only even have 2 sticks as well, so gaps for airflow compared to 4. Making me wonder how much better my temps would be with different sticks...
Also you don't have WHEA at 2000 FCLK or just ignoring?


----------



## Taraquin

Dreamic said:


> And your actual reported vDIMM is 0.01v lower than ZenTimings reports yes? So you started overheating into errors at just 1.460v actual then? If ZT is saying 1.440v right now +0.03v = overheat.
> Maybe these 4400C19 Patriot Viper are just the worst heatsinks known to man? Practically overheating at XMP vDIMM. You only even have 2 sticks as well, so gaps for airflow compared to 4. Making me wonder how much better my temps would be with different sticks...
> Also you don't have WHEA at 2000 FCLK or just ignoring?


Actual voltage is 1.45-1.46V. I set 1.44V in bios so Zentimings reads correctly from what I set. If actual voltage rises to 1.48-1.49V I get the overheat error in TM5 after 3-4 cycles if GPU is loaded at same time (hot air from fan 2 on GPU). I have a 2-dimm MB so little space between. I have seen 5 wheas 18 since building the computer 2 months ago, but 3 of them were on agesa 1.1.0.0 above 3800\1900 and 2 on beta 1.2.0.1 when I tried 4133\2066. No wheas for 4 weeks since on 1.2.0.2


----------



## DeletedMember558271

Taraquin said:


> Actual voltage is 1.45-1.46V. If actual voltage rises to 1.48-1.49V I get the overheat error in TM5 after 3-4 cycles if GPU is loaded at same time (hot air from fan 2 on GPU). I have a 2-dimm MB so little space between. I have seen 5 wheas 18 since building the computer 2 months ago, but 3 of them were on agesa 1.1.0.0 above 3800\1900 and 2 on beta 1.2.0.1 when I tried 4133\2066. No wheas for 4 weeks since on 1.2.0.2


Yea my GPU overheats mine too if it's too high, same RAM as you but 4x8GB, my bad assuming you had 4 DIMM slots.
Interesting you have no WHEA, @Veii








Gigabyte being real specific with model numbers and all... obviously not RTL8125B 2.5G though.
I really hope a modded BIOS can fix WHEA for me so my board can perform like yours, it doesn't sound easy to do though or like 1 tutorial will work for all boards/BIOS from what Veii said earlier.
It's that or buy a new motherboard though I guess, for a lot of people


----------



## Taraquin

Dreamic said:


> Yea my GPU overheats mine too if it's too high, same RAM as you but 4x8GB, my bad assuming you had 4 DIMM slots.
> Interesting you have no WHEA, @Veii
> View attachment 2490774
> 
> Gigabyte being real specific with model numbers and all... obviously not RTL8125B 2.5G though.
> I really hope a modded BIOS can fix WHEA for me so my board can perform like yours, it doesn't sound easy to do though or like 1 tutorial will work for all boards/BIOS from what Veii said earlier.
> It's that or buy a new motherboard though I guess, for a lot of people


So buying a budget board might be the whea-savior and ensure running fast ram? That must be a first. What timings\voltages etc do you currently use?


----------



## mongoled

Veii said:


> snip.........................The "way" to get high FCLK to work, is on one hand to lower every voltage possible - this includes procODT too
> on the other hand supply enough to the IO-Die and then slowly bring up everything higher with SOC
> a high CCD freq will require more SOC , but tooo much SOC and high FCLK interconnect speeds will destabilize and crash the cores in the CCD
> Soo you need as low CCD as possible
> 
> Low CCD made it look like it triggers sound crackling and usb issues, but that is because VDDG keeps load balancing between CCD and IOD
> IO issues continue to relate to procODT and IOD - they have nothing to do with the CCD voltages. Suure the CPU controls somewhere the "cleanness and consistency" of the audio decoding
> Aside from the D/A chip on the board ~ but this goes back then to the "Signal Integrity" Topic , which is purely procODT related
> Soo lower CCD , you will notice when it's too low ~ then uplift everything with subtle more SOC voltage
> Also keep Standby voltage low
> 
> About the 1.8v Line
> This continues to be a semi mystery
> It is helpful when you SOC and IOD have a perfect 40mV *GET* distance, and nomatter of the load, this distance doesn't drop to 38mV
> But if it jumps to 42mV it can "desync" and destabilize
> Also if you max out switching frequency and loadlines, the ripple will get too worse and SOC won't be clean anymore, at all ~ a balance thing, i like to use loadlines here
> 
> CPU voltage, is up to users sillicon
> You can drive it with as little loadline as possible, or as much loadline as possible
> Signal Integrity is king here ~ soo give your best to lower ripple/increase signal integrity as best as you can
> This means, go lower with procODT (use all methods possible with CAD_BUS and RTT to help you for such)
> Go the lowest on cLDO_VDDP you can run (900mV is fine, but i've seen people at 2000 run 840 and lower)
> Go with the lowest VDDP Standby Voltage or CPU VDDP as possible ~ whatever is exposed and whattever it is named
> 
> VDD 1.8v line, usually holding it at 1.83v was beneficial to a little degree
> 1.8V is fine, lower had no benefits to this date ~ higher did only destabilize if you went with the "low current, high input SOC" path
> If you go with the "IOD to SOC = perfect 40mV" - then 1.8v line does help till 1.9v, somewhere along 1.84-1.86 is the sweetspot , higher can already create instability
> 
> Y-cruncher will crash, it is still able to destabilize Vermeer very well after some time ~ but give it time, as Vermeer does autocorrect and adapt to errors + adjust internal GMI link speeds to keep stability up
> OCCT Extreme AVX2, 1h ~ remains a good benchmark
> However it differs from y-cruncher, it is able to freeze Vermeer's Autocorrection . Whatever it does, Vermeer is not able to autocorrect that well for it
> But OCCT will also crash on any little FCLK or MCLK issue ~ as it is a Linpack Type of test after all. Soo be sure the whole y-cruncher test suite is stable for 3+ cycles. Make it 4
> 
> EDIT:
> If you see FCLK crashing because of "too much IOD or too much CCD"
> Bring it down - and compensate with higher input voltage on SOC
> That should make it stable, as it mostly crashes on "overcurrent" by bad signal integrity - just that the colour substrate change can need more SOC overall
> This should make it stable ~ but generally, the lower SOC the better , as it strongly eats into the powerbudget (EDC) which you can notice on one of the pictures after 1933Mhz
> EDIT 2:
> Keep in mind procODT has upper and lower bonds of SOC stable'ness
> It can be that you either need to decrease or increase procODT - on SOC increase (decrease on SOC decrease)
> 
> @Nizzen about the issue, sadly i'm the single person aside from board makes who noticed it. Very sure every board-partner & AMD is aware of the issue with Realtek & surely know their big stock-up amount & investment + trust
> Yes, i'll spill the beans but decided to take another route
> 
> 
> Spoiler
> 
> 
> 
> I could, brandshame them if i make a big announcement and focus on putting them into target on several places ~ including Reddit and for bigger media outlets
> ~ but i have personal issues not to think that they deserve it
> Don't get me wrong, they treated each of the boardpartners like ****, they absolutely deserve the brandshame and target-fire for whoever took that wrong direction, with this big flaw
> And alone that they refuse to fix it ~ but every boardpartner and AMD have to bent down to them just so they won't lose a huge amount of sales.
> It's a long going fight and the only "source" for this are email exchanges between PCB engineers and the Realtek RND department. The stupid excuses that are given and the lack of work that is provided, having AMD to force in redoing & applying soo many unstable patches ~ just to deal with their stubborn refusal to assist and fix their own design flaw.
> I'm mad about them. Respect them alot the last 6-8 years for how they behaved in the wireless and linux driver market.
> Respected them with the lower prices made and helped notebooks and PCBs in general costing less. Respected them a lot again for their Unix/Linux driver support staying opensource (kinda) and assisting + helping the Arch Linux community have more stable drivers.
> 
> But this here is a disaster
> 
> 
> 
> 
> 
> 
> 
> 
> B550 VRM DB sheet
> 
> 
> 시트1 Feedback : [email protected] Don't requst permission / You can leave comment :) Product,Price,Config,Phase Type,VRM Type,MOSFET (Vcore),PWM Controller,LAN,Wireless LAN,Audio ASUS ROG STRIX B550-XE Gaming WiFi,$ 330,14+2,Dual-Output,DrMOS,TI X95410RR 90A,ASP1405i (7+1),Intel I225-V (2.5...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Take a look here, tell me how many I225-V boards exist . . .
> Madness shouldn't rule over my public relationship with them, and i haven't received any bribe to refuse to talk.
> But i'm disappointed who in their department rules this nonsense. Why do you treat board partners like **** when they multiple times try to talk with you and fix it for everyone
> Is money that much more important than the huge userbase who uses "by your made mistake" all these buggy boards.
> At least they went out of their way after 3 months back and forth blaming - to fix some of the issues where each of their ports was force restarting attached Lan-Splitters and Routers.
> Probably just to ensure themself to be somewhat sue-free, and push a damage prevention math.
> 
> All these usb fix agesa and of course hidden ethernet fixes, driver rewrites (10+)
> Windows enforced update pushes and FW injections.
> Shady work, but nobody would notice anything ~ and probably for the brandstatus of this semiconductor ~ "shouldn't notice anything"
> But it reached hilarious levels already, and nothing changes
> Surely board partners are under NDA, in hope that nice Realtek guy finally fixes their broken mess of a FW
> And the saddest thing ~ you can't even skip the issue. It still causes problems if nothing is plugged in or even "ACPI disabled". it still triggers crashes and kernel "reboot reports"
> It still causes SATA drive crashes, by the experimental Chipset interconnect patches, that where supplied. And all for what ~ because dear semiconductor sits on their cooperate stool , stating that nobody held their given Schematics and they are not in fault for unstable controllers ~ and surely not in fault for letting close to everything reboot or crash by simply connecting it with it. . . .
> 
> 
> But yes, nobody wants to hear that and thinking about it for more ~ it's not the path to take
> Suure it would help and wake up some of these stubborn people in the industry, but it would put me on target and is kind of shameful having to take such path.
> Also would be against all of the Board-Partners who at least "try" to do something , in comparison to Semiconductor who doesn't even bother to cooperate.
> 
> Yes AMD tries too, sure many of it is loss-of-sales prevention & damage prevention, but at least "they try" ~something~
> And this "trying" is more appreciable - weighting out the damage and childish nonsense that has been going on between them in the hidden.
> Soo i should appreciate this "trying" of resolving something and not take the madman path not only damaging semiconductors reputation, but putting every boardpartner also in fire
> It is a bad idea to take that path ~ as again, the person to blame in the industry is someone that are not the board partners (not fully)
> And i can see from each of them on the new board releases, that they at least try to go around the problem (which is not public) and sale boards with only Intel-Lan , no combo options anymore
> I appreciate this, and should not continue to fuel the already burning down underground communication "fire" that is burning and burning in the dark.
> ====================================================================
> Soo yes, the reason i share it is that i've changed my mind a bit
> Instead of complaining and crying about how stupid all this nonsense is
> Let's work to maybe resolve it
> 
> Stability should be kept up, if the module is fully wiped from the bios, then it can not be loaded
> Another way to "break" it , is by accident erasing the SOIC-8 chip which belongs only to the ethernet ports (each one has one)
> I've done it by accident on the ITX (has I225-V) , sooo i know this fully renders ethernet inactive and no driver can even load + no entry in the ACPI table, soo no crashing FW can be loaded
> 
> Desoldering and swapping is hard
> You'd need not only the corresponding Port, but also it's corresponding FW chip. And this means, destroying a board fully to "fix" another affected one.
> Not a good option, but wiping the bios module with UefiTools and flashing it - should be easiest way to prevent the FW ever being loaded.
> 
> WHEA #19 overall covers a lot of IO, but this is the major issue one
> the Dark hero , sadly was very problematic too me ~ but at that ttime i didn't know what's up
> And it certainly is not even remotely an Substrate instability limit, as everything passed the usual test suite of y-cruncher , OCCT, P95, Cinebench , IBT and so on
> It was a bad time with a 5900X & two swapped 5950X on the same board.
> 
> I've let you decide what to do with the information and the moderation team this time hopefully not censoring me
> But i decided to take the least damage making route ~for now~ , try to actually resolve this issue somehow instead of complaining
> And let you guys in this thread & not a big targeting post know ~ what's up , and why this can be problematic
> Thank you for the trust & thanks again to @ManniX-ITA for the supplied workaround patch
> Only filtering WHEA #19 would be useful, to prevent random DPC calls but at least this is something against the neverending fight with the semiconductor
> I don't think AMD has the power to fix it really, it's them alone to supply not only "driver fixes" but actually update the FW in it ~ to stop crashing devices or itself . . .
> _let's see how long this post will last, hopefully it gets hidden under dozens of other messages, soo we can quote it ~ but hey i might get censored again_





Veii said:


> *Too high*:
> 2x 8Gb SR
> - 48Ω
> 4x 8GB SR & 2x 16GB
> - 53.3Ω
> 4x 16GB DR / 2x 32GB
> - 60Ω
> 
> *Just enough*
> 2x 8Gb SR
> - 40Ω
> 4x 8GB SR / 2x 16GB
> - 43.6Ω
> 4x 16GB DR / 2x 32GB
> - 48Ω
> 
> *Optimal / Low procODT*
> 2x 8Gb SR
> - 30-34.3Ω
> 4x 8GB SR & 2x 16GB
> - 32-36.9Ω
> 4x 16GB DR / 2x 32GB
> - 34.3-40Ω
> 
> *Too Low / Issues*
> 2x 8Gb SR
> - 28.2Ω
> 4x 8GB SR & 2x 16GB
> - 30Ω
> 4x 16GB DR / 2x 32GB
> - 32-34.3Ω
> 
> "Too Low" ~ can be made possible when cLDO_VDDP is bellow 900mV
> But then one step up makes more sense as you will be package throttling
> 
> SOC's range is higher because of the substrate colour change
> The quote will lead you to a big post about "AMD Maximum Voltage - Vermeer Edition"
> 920-1300mV is the SOC range of this generation
> Higher than 1.3v is bad, higher than 1.25v barely brings any benefits
> 920mV SOC expects 840mV cLDO_VDDP, 840mV VDDG CCD, 880mV VDDG IOD, 920mV *GET *vSOC
> GET = applied, factoring switching frequency and loadline droop
> 
> Same post also has a "minimum required SOC to run X FCLK"


Regarding both the above posts.

Testing the theory against reality.

This is on X570 Unify with latest BIOS A93, such low vDDG/vDDP were not possible on A85.

TLDR, applying the methodologies above made absolutely no difference to WHEA warnings.

I started from scratch profile with the following pre-requisites.

*DPM LCLK tried both 2-1-1-1-2-1-1-1 and 2-1-1-2-2-1-1-2
DF-States: Disabled
ProcODT: 28.2 ohms and 34.3 ohms
Curve Optimizer: Disabled
CPU LLC: 4
NB LLC: 2
CPU/NB Switching Frequency: 800khz
CPU/NB: Enhanced
vSOC: lower than 1.0v and higher than 1.2v (i used combination of different ProcODT with different vSOC ranges)
PBO: PPT/TDC/EDC set at 140/90/142
vDDP: 0.780v
vDDG CCD: 0.780v
vDDG IOD: 0.945v
vSOC: 0.9875v*

All other settings apart from those used for vDDG CCD/IOD, vDDP are on AUTO

Below will be two images, one using my 24/7 settings which are tuned on A85 and are WHEA free, while the other uses the pre-requisites set above but default memory timings

The 24/7 setting also uses PBO Boost Override set @200 mhz

*Check items*
Difference between vSOC and VDDG IOD is around 0.04v - Checked
vDDG CCD set to low value (tried different low ranges from 0.760v to 0.900v) - Checked
vDDP set to low value (tried different low ranges from 0.760v to 0.900v) - Checked
ProcODT/vSOC used "too low" and "optimal" - Checked

*Unknowns*
How can we check that the DPM LCLK and DF-States settings are actually being applied ??
How can we check that the voltages ive applied are not being auto corrected ??

*Notes*
Going from 3800/1900 to 3866/1933 results in thousands of WHEA warnings, no combination of settings had any effect
Using the lower voltages on A93 set at 3800/1900 results in a few WHEA warnings which were not occurring with my 24/7 settings on A85 (which uses "normal" voltages)
Apart from WHEA warning 3933/1933 looks to be stable on these super low voltages, have not been higher

3800/1900 "24/7 settings"









3866/1933 "Pre-requisites"


----------



## DeletedMember558271

Taraquin said:


> So buying a budget board might be the whea-savior and ensure running fast ram? That must be a first. What timings\voltages etc do you currently use?





Spoiler: This is what I use














But yes Realtek RTL8125B 2.5G is apparently the issue, if you don't have that should be good unless there's something else wrong it's looking like. Kinda waiting to see what happens when ManniX-ITA gets his modded BIOS that disables it.
I can't boot 1900 specifically unfortunately and obviously I have WHEA 1933+ and with the high temp errors like you I just decided to stick around 1.450v, I'm not sure how much higher I could push it but I don't want to be on the edge and have a too warm day give me anxiety lol, I know just around 1.520v at least with GPU hammering it starts causing issues so the lower the safer I feel, and these sticks shouldn't be having problems at or barely above XMP vDIMM or Patriot is a joke. Would help a lot if these sticks had temp sensors


----------



## ManniX-ITA

Veii said:


> Strongly unsure if WHEA 20 means anything at all ~ doesn't even have a description


I got it as well a few times, I don't remember exactly what was triggering it 
Could may be insufficient VSOC and/or VDDG and/or VRM LLC/PWM


----------



## Veii

ManniX-ITA said:


> I have missed it
> Can you repost?


It's alpha, too aggressive, crashes with CTR because the wake up spikes are too frequent ~ cpu hickups on voltage if the unit is slow/badly binned,
it's not really much better than the high-perf option in memlatency, except that it powersaves & lat-results remain consistent (made one that had a 0.3ns improvement but it's gone by accident while designing this one)
Yea that's about it. At least it's CPPC aware, and manages the powerbudget well. Maybe too well, as the cpu can sometimes choke on not enough voltage

Keep it at 4% idle state, DF will function when it's usable. Else without DF there is only a tiny overboost
Keep in mind it should have a 5150mhz freq limiter in there. If you want to extend it (i mean you know how)
Grab QuickCPU , or just unhide both maximum frequency limits with this winraid community tool








PowerSettingsExplorer


MediaFire is a simple to use free service that lets you put all your photos, documents, music, and video in a single place so you can access them anywhere and share them everywhere.



www.mediafire.com





I'm atm lazy to stop being busy, but i'll finish it up someday
Either it's usable and runs very well, or it's fully broken and idle crashes the CPU
Doublecheck minimum idle state, it could be predefined as 100%
Critically judged ~ it needs work & i motivation to fix it up, soo CTR 2.1 OB doesn't insta crash the unit by "too well" powershuffle
And someday AMD finally has to fix their DF-CStates, soo this thing can actually show what it was designed for ~ and not run in slow legacy mode without correct core hibernation zZZ
Speaking of "zZZ" , until later 🛌

The only good thing that i can confidently say about it
is that the core leverage mode and CPPC awareness functions on the rocket mode
Good stepup from the broken AMD delivered options ~ IF it functions, so to speak, if the unit survives with it and doesn't hardcrash


----------



## glnn_23

Veii said:


> Good Job !
> Can you please check if MSI Dragon Ball, will work for you ?
> (They seem to have Asus support, but not every board 🤔)
> Else just a free opportunity to grab the latest MemTweakIT
> Maybe we can learn something from the powering settings or IMC settings of it (timings aside)
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> I find some of the results on the Zen DRAM Sheet a bit suspicious There are users with the Realtek RTL8111H ~ who have no WHEAs It makes me wonder if HWInfo even tracks the #19's or only #18s which are "real issues" or only 2.5gbit ones are fully affected (Combo unit boards are affected, but...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> Which version is your TurboV ?
> I atm have 1.01.15


Hi Veii thanks again for all the info you are putting out there.

Unfortunately I have been unable to get MSI Dragon Ball or MemTweakIT running on my system so far.

The version of TurboV I have is 1.05.03_beta.


----------



## rossi594

Veii said:


> Good Job @ManniX-ITA , thank you for making it
> Maybe attach it to your signature , soo it's easier findable - i'll give it a shot on boards/users systems i know that fail
> 
> 2067 is not thaat hard, but maybe if my older message was viewed (the picture spam in the spoiler section)
> it needs exquisite voltages and low procODT - also a big difference between CCD and IOD
> High FCLK tends to mess with the CCDs, while high SOC might make the whole substrate very sensitive and will put FIT triggerhappy to autocorrect and slow down things (if something little is off)
> But higher SOC generally helped a lot - where VDDG then auto adjusted and load balanced it ~ nevertheless what you put in (as long as uncoreOC is disabled)
> 
> The "way" to get high FCLK to work, is on one hand to lower every voltage possible - this includes procODT too
> on the other hand supply enough to the IO-Die and then slowly bring up everything higher with SOC
> a high CCD freq will require more SOC , but tooo much SOC and high FCLK interconnect speeds will destabilize and crash the cores in the CCD
> Soo you need as low CCD as possible
> 
> Low CCD made it look like it triggers sound crackling and usb issues, but that is because VDDG keeps load balancing between CCD and IOD
> IO issues continue to relate to procODT and IOD - they have nothing to do with the CCD voltages. Suure the CPU controls somewhere the "cleanness and consistency" of the audio decoding
> Aside from the D/A chip on the board ~ but this goes back then to the "Signal Integrity" Topic , which is purely procODT related
> Soo lower CCD , you will notice when it's too low ~ then uplift everything with subtle more SOC voltage
> Also keep Standby voltage low
> 
> About the 1.8v Line
> This continues to be a semi mystery
> It is helpful when you SOC and IOD have a perfect 40mV *GET* distance, and nomatter of the load, this distance doesn't drop to 38mV
> But if it jumps to 42mV it can "desync" and destabilize
> Also if you max out switching frequency and loadlines, the ripple will get too worse and SOC won't be clean anymore, at all ~ a balance thing, i like to use loadlines here
> 
> CPU voltage, is up to users sillicon
> You can drive it with as little loadline as possible, or as much loadline as possible
> Signal Integrity is king here ~ soo give your best to lower ripple/increase signal integrity as best as you can
> This means, go lower with procODT (use all methods possible with CAD_BUS and RTT to help you for such)
> Go the lowest on cLDO_VDDP you can run (900mV is fine, but i've seen people at 2000 run 840 and lower)
> Go with the lowest VDDP Standby Voltage or CPU VDDP as possible ~ whatever is exposed and whattever it is named
> 
> VDD 1.8v line, usually holding it at 1.83v was beneficial to a little degree
> 1.8V is fine, lower had no benefits to this date ~ higher did only destabilize if you went with the "low current, high input SOC" path
> If you go with the "IOD to SOC = perfect 40mV" - then 1.8v line does help till 1.9v, somewhere along 1.84-1.86 is the sweetspot , higher can already create instability
> 
> Y-cruncher will crash, it is still able to destabilize Vermeer very well after some time ~ but give it time, as Vermeer does autocorrect and adapt to errors + adjust internal GMI link speeds to keep stability up
> OCCT Extreme AVX2, 1h ~ remains a good benchmark
> However it differs from y-cruncher, it is able to freeze Vermeer's Autocorrection . Whatever it does, Vermeer is not able to autocorrect that well for it
> But OCCT will also crash on any little FCLK or MCLK issue ~ as it is a Linpack Type of test after all. Soo be sure the whole y-cruncher test suite is stable for 3+ cycles. Make it 4
> 
> EDIT:
> If you see FCLK crashing because of "too much IOD or too much CCD"
> Bring it down - and compensate with higher input voltage on SOC
> That should make it stable, as it mostly crashes on "overcurrent" by bad signal integrity - just that the colour substrate change can need more SOC overall
> This should make it stable ~ but generally, the lower SOC the better , as it strongly eats into the powerbudget (EDC) which you can notice on one of the pictures after 1933Mhz
> EDIT 2:
> Keep in mind procODT has upper and lower bonds of SOC stable'ness
> It can be that you either need to decrease or increase procODT - on SOC increase (decrease on SOC decrease)
> 
> @Nizzen about the issue, sadly i'm the single person aside from board makes who noticed it. Very sure every board-partner & AMD is aware of the issue with Realtek & surely know their big stock-up amount & investment + trust
> Yes, i'll spill the beans but decided to take another route
> 
> 
> Spoiler
> 
> 
> 
> I could, brandshame them if i make a big announcement and focus on putting them into target on several places ~ including Reddit and for bigger media outlets
> ~ but i have personal issues not to think that they deserve it
> Don't get me wrong, they treated each of the boardpartners like ****, they absolutely deserve the brandshame and target-fire for whoever took that wrong direction, with this big flaw
> And alone that they refuse to fix it ~ but every boardpartner and AMD have to bent down to them just so they won't lose a huge amount of sales.
> It's a long going fight and the only "source" for this are email exchanges between PCB engineers and the Realtek RND department. The stupid excuses that are given and the lack of work that is provided, having AMD to force in redoing & applying soo many unstable patches ~ just to deal with their stubborn refusal to assist and fix their own design flaw.
> I'm mad about them. Respect them alot the last 6-8 years for how they behaved in the wireless and linux driver market.
> Respected them with the lower prices made and helped notebooks and PCBs in general costing less. Respected them a lot again for their Unix/Linux driver support staying opensource (kinda) and assisting + helping the Arch Linux community have more stable drivers.
> 
> But this here is a disaster
> 
> 
> 
> 
> 
> 
> 
> 
> B550 VRM DB sheet
> 
> 
> 시트1 Feedback : [email protected] Don't requst permission / You can leave comment :) Product,Price,Config,Phase Type,VRM Type,MOSFET (Vcore),PWM Controller,LAN,Wireless LAN,Audio ASUS ROG STRIX B550-XE Gaming WiFi,$ 330,14+2,Dual-Output,DrMOS,TI X95410RR 90A,ASP1405i (7+1),Intel I225-V (2.5...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Take a look here, tell me how many I225-V boards exist . . .
> Madness shouldn't rule over my public relationship with them, and i haven't received any bribe to refuse to talk.
> But i'm disappointed who in their department rules this nonsense. Why do you treat board partners like **** when they multiple times try to talk with you and fix it for everyone
> Is money that much more important than the huge userbase who uses "by your made mistake" all these buggy boards.
> At least they went out of their way after 3 months back and forth blaming - to fix some of the issues where each of their ports was force restarting attached Lan-Splitters and Routers.
> Probably just to ensure themself to be somewhat sue-free, and push a damage prevention math.
> 
> All these usb fix agesa and of course hidden ethernet fixes, driver rewrites (10+)
> Windows enforced update pushes and FW injections.
> Shady work, but nobody would notice anything ~ and probably for the brandstatus of this semiconductor ~ "shouldn't notice anything"
> But it reached hilarious levels already, and nothing changes
> Surely board partners are under NDA, in hope that nice Realtek guy finally fixes their broken mess of a FW
> And the saddest thing ~ you can't even skip the issue. It still causes problems if nothing is plugged in or even "ACPI disabled". it still triggers crashes and kernel "reboot reports"
> It still causes SATA drive crashes, by the experimental Chipset interconnect patches, that where supplied. And all for what ~ because dear semiconductor sits on their cooperate stool , stating that nobody held their given Schematics and they are not in fault for unstable controllers ~ and surely not in fault for letting close to everything reboot or crash by simply connecting it with it. . . .
> 
> 
> But yes, nobody wants to hear that and thinking about it for more ~ it's not the path to take
> Suure it would help and wake up some of these stubborn people in the industry, but it would put me on target and is kind of shameful having to take such path.
> Also would be against all of the Board-Partners who at least "try" to do something , in comparison to Semiconductor who doesn't even bother to cooperate.
> 
> Yes AMD tries too, sure many of it is loss-of-sales prevention & damage prevention, but at least "they try" ~something~
> And this "trying" is more appreciable - weighting out the damage and childish nonsense that has been going on between them in the hidden.
> Soo i should appreciate this "trying" of resolving something and not take the madman path not only damaging semiconductors reputation, but putting every boardpartner also in fire
> It is a bad idea to take that path ~ as again, the person to blame in the industry is someone that are not the board partners (not fully)
> And i can see from each of them on the new board releases, that they at least try to go around the problem (which is not public) and sale boards with only Intel-Lan , no combo options anymore
> I appreciate this, and should not continue to fuel the already burning down underground communication "fire" that is burning and burning in the dark.
> ====================================================================
> Soo yes, the reason i share it is that i've changed my mind a bit
> Instead of complaining and crying about how stupid all this nonsense is
> Let's work to maybe resolve it
> 
> Stability should be kept up, if the module is fully wiped from the bios, then it can not be loaded
> Another way to "break" it , is by accident erasing the SOIC-8 chip which belongs only to the ethernet ports (each one has one)
> I've done it by accident on the ITX (has I225-V) , sooo i know this fully renders ethernet inactive and no driver can even load + no entry in the ACPI table, soo no crashing FW can be loaded
> 
> Desoldering and swapping is hard
> You'd need not only the corresponding Port, but also it's corresponding FW chip. And this means, destroying a board fully to "fix" another affected one.
> Not a good option, but wiping the bios module with UefiTools and flashing it - should be easiest way to prevent the FW ever being loaded.
> 
> WHEA #19 overall covers a lot of IO, but this is the major issue one
> the Dark hero , sadly was very problematic too me ~ but at that ttime i didn't know what's up
> And it certainly is not even remotely an Substrate instability limit, as everything passed the usual test suite of y-cruncher , OCCT, P95, Cinebench , IBT and so on
> It was a bad time with a 5900X & two swapped 5950X on the same board.
> 
> I've let you decide what to do with the information and the moderation team this time hopefully not censoring me
> But i decided to take the least damage making route ~for now~ , try to actually resolve this issue somehow instead of complaining
> And let you guys in this thread & not a big targeting post know ~ what's up , and why this can be problematic
> Thank you for the trust & thanks again to @ManniX-ITA for the supplied workaround patch
> Only filtering WHEA #19 would be useful, to prevent random DPC calls but at least this is something against the neverending fight with the semiconductor
> I don't think AMD has the power to fix it really, it's them alone to supply not only "driver fixes" but actually update the FW in it ~ to stop crashing devices or itself . . .
> _let's see how long this post will last, hopefully it gets hidden under dozens of other messages, soo we can quote it ~ but hey i might get censored again_


Wow thanks mate. Does every voltage include the voltages for the core chiplet? Or only soc? How do I lower ProcODT? Do I apply Ohms law and lower the resistance?


----------



## adversary

Veii said:


>




May I know reason why you sugested exactly this tRFC2 and 4 for him? Is there some general different rule for dual rank, or this is specific for his case?


----------



## craxton

Veii said:


> Type C doesn't have any dropout issues funnily
> USB 2.0 Pure , doesn't have any either
> It where these 3.0 & 3.1 combo jacks - somehow still randomly having bandwidth share issues
> 
> USB 4.0 down to USB 2.0 (device) has no issues at all
> Haven't seen any TB4 issues either ~ but i'm still desperately looking for a Thunderbolt Audio interface deal
> (nothing TB2 as the TB3 to 2 adapter, seems to cause BSODs on TB4 ~ somebody understand why)


so it would indeed seem that, its the SSK enclosure im using none the less.

suppose ill give one more shot to SSK and buy the "same one" only this time
pay attention to which one i receive as well, what was ordered and received were different but
its been way to long to mention to amazon now.

usb 2.0/ usb 3.1 A to usb-c works fine on this device enclosure, but type c-c thats when it 
randomly connects and disconnects (doesnt matter whats hooked to the pc (tested)


----------



## craxton

ManniX-ITA said:


> Could may be insufficient VSOC and/or VDDG and/or VRM LLC/PWM


thats what was causing my crashes for sure.
but if it was just barely low it was 18 instead with a bsod. 

20 was straight out crashing with a restart with me pressing "DEL" 
until i hit the bios....

why is it called msi dragon ball, if it doesnt work for msi board? 
or at least not the board im running lol....


----------



## TimeDrapery

Taraquin said:


> Spoiler
> 
> 
> 
> Veii or others that knows much more about ramtuning than me: Got any further tips for tweaking, can go max 0.01-0.02V higher on ram volt before overheat. That was not enough for lowering tCL, tRCDRD, tRP or tCWL. Should tRAS always be tCL+tRCDRD, tRC alwas be tRAS+tRP and tRFC=tRCx6 on B-die? Any tweaks on ProcODT, Rtts, drv-strength I might try to lower voltage reqs for primaries?


@Taraquin

For me, these have always worked out really well...

tRAS = tRCDRD × 2
tRC = tRAS + tRP
tRTP = tWR ÷ 2
tRFC = tRC (in ns) × tRTP

Anchoring tRFC to tRTP like this really does seem to help immense amounts



mongoled said:


> Spoiler
> 
> 
> 
> Regarding both the above posts.
> 
> Testing the theory against reality.
> 
> This is on X570 Unify with latest BIOS A93, such low vDDG/vDDP were not possible on A85.
> 
> TLDR, applying the methodologies above made absolutely no difference to WHEA warnings.
> 
> I started from scratch profile with the following pre-requisites.
> 
> *DPM LCLK tried both 2-1-1-1-2-1-1-1 and 2-1-1-2-2-1-1-2
> DF-States: Disabled
> ProcODT: 28.2 ohms and 34.3 ohms
> Curve Optimizer: Disabled
> CPU LLC: 4
> NB LLC: 2
> CPU/NB Switching Frequency: 800khz
> CPU/NB: Enhanced
> vSOC: lower than 1.0v and higher than 1.2v (i used combination of different ProcODT with different vSOC ranges)
> PBO: PPT/TDC/EDC set at 140/90/142
> vDDP: 0.780v
> vDDG CCD: 0.780v
> vDDG IOD: 0.945v
> vSOC: 0.9875v*
> 
> All other settings apart from those used for vDDG CCD/IOD, vDDP are on AUTO
> 
> Below will be two images, one using my 24/7 settings which are tuned on A85 and are WHEA free, while the other uses the pre-requisites set above but default memory timings
> 
> The 24/7 setting also uses PBO Boost Override set @200 mhz
> 
> *Check items*
> Difference between vSOC and VDDG IOD is around 0.04v - Checked
> vDDG CCD set to low value (tried different low ranges from 0.760v to 0.900v) - Checked
> vDDP set to low value (tried different low ranges from 0.760v to 0.900v) - Checked
> ProcODT/vSOC used "too low" and "optimal" - Checked
> 
> *Unknowns*
> How can we check that the DPM LCLK and DF-States settings are actually being applied ??
> How can we check that the voltages ive applied are not being auto corrected ??
> 
> *Notes*
> Going from 3800/1900 to 3866/1933 results in thousands of WHEA warnings, no combination of settings had any effect
> Using the lower voltages on A93 set at 3800/1900 results in a few WHEA warnings which were not occurring with my 24/7 settings on A85 (which uses "normal" voltages)
> Apart from WHEA warning 3933/1933 looks to be stable on these super low voltages, have not been higher
> 
> 3800/1900 "24/7 settings"
> View attachment 2490776
> 
> 
> 3866/1933 "Pre-requisites"
> View attachment 2490777


@mongoled

Would the "Debug" tool in ZenTimings suffice to see if your voltages are actually applied after setting them in BIOS?



Veii said:


> Spoiler
> 
> 
> 
> It's alpha, too aggressive, crashes with CTR because the wake up spikes are too frequent ~ cpu hickups on voltage if the unit is slow/badly binned,
> it's not really much better than the high-perf option in memlatency, except that it powersaves & lat-results remain consistent (made one that had a 0.3ns improvement but it's gone by accident while designing this one)
> Yea that's about it. At least it's CPPC aware, and manages the powerbudget well. Maybe too well, as the cpu can sometimes choke on not enough voltage
> 
> Keep it at 4% idle state, DF will function when it's usable. Else without DF there is only a tiny overboost
> Keep in mind it should have a 5150mhz freq limiter in there. If you want to extend it (i mean you know how)
> Grab QuickCPU , or just unhide both maximum frequency limits with this winraid community tool
> 
> 
> 
> 
> 
> 
> 
> 
> PowerSettingsExplorer
> 
> 
> MediaFire is a simple to use free service that lets you put all your photos, documents, music, and video in a single place so you can access them anywhere and share them everywhere.
> 
> 
> 
> www.mediafire.com
> 
> 
> 
> 
> 
> I'm atm lazy to stop being busy, but i'll finish it up someday
> Either it's usable and runs very well, or it's fully broken and idle crashes the CPU
> Doublecheck minimum idle state, it could be predefined as 100%
> Critically judged ~ it needs work & i motivation to fix it up, soo CTR 2.1 OB doesn't insta crash the unit by "too well" powershuffle
> And someday AMD finally has to fix their DF-CStates, soo this thing can actually show what it was designed for ~ and not run in slow legacy mode without correct core hibernation zZZ
> Speaking of "zZZ" , until later 🛌
> 
> The only good thing that i can confidently say about it
> is that the core leverage mode and CPPC awareness functions on the rocket mode
> Good stepup from the broken AMD delivered options ~ IF it functions, so to speak, if the unit survives with it and doesn't hardcrash


@Veii 

Oh you shared your OS power plan! Thanks! I'm gonna compare it to the others I've got so I can learn more about this side of the house!


----------



## Dar|{cyde

I tried MSI Dragon Ball on a Unify-X as well. No joy, it says platform unsupported. All the screenshots show it on a Z490 platform, perhaps it only works there.


----------



## craxton

Taraquin said:


> when I tried 4133\2066. No wheas for 4 weeks since on 1.2.0.2


...your running 1.2.0.2 with 4133/2066 ?
I can't get **** timings to post on 1.2.0.2....


----------



## craxton

Dar|{cyde said:


> I tried MSI Dragon Ball on a Unify-X as well. No joy, it says platform unsupported. All the screenshots show it on a Z490 platform, perhaps it only works there.


Yea from my b550 gaming edge looking in, it's unsupported as well lol... Still don't know the name for it being MSI dragon ball... Perhaps Intel is what it's for but works on Asus boards for amd?


----------



## Taraquin

craxton said:


> ...your running 1.2.0.2 with 4133/2066 ?
> I can't get **** timings to post on 1.2.0.2....


Sorry, I meant 4066/2033. I haven't been able to boot 4133/2033, but I only tried with same timings I use now and a bit higher voltage.


----------



## Yuke

With WHEA-hider but Y-Cruncher, Karhu, Gaming and Idle stable. Had to loosen CO values a bit since i went from 3800Mhz to 4000Mhz but whatever.

Couldnt boot with 4066/2033 but may try it out with stupid voltages at some point just to be sub 53ns for once. CL14 also didnt boot even at 1.55V, may have to try out 2T with GDM off and a stupid amount of ClkDrvStr. 40 ProcODT was the lowest i could go, 36 already had booting issues (50% chance).


----------



## KedarWolf

KedarWolf said:


> Got this earlier today.
> 
> View attachment 2490611


Improved my score by a decent margin.


----------



## Yuke

Yuke said:


> With WHEA-hider but Y-Cruncher, Karhu, Gaming and Idle stable. Had to loosen CO values a bit since i went from 3800Mhz to 4000Mhz but whatever.
> 
> Couldnt boot with 4066/2033 but may try it out with stupid voltages at some point just to be sub 53ns for once. CL14 also didnt boot even at 1.55V, may have to try out 2T with GDM off and a stupid amount of ClkDrvStr. 40 ProcODT was the lowest i could go, 36 already had booting issues (50% chance).
> 
> View attachment 2511277
> View attachment 2511279


Meh, my personal brickwall it seems
























Also, i had weird buzzing and humming sounds coming from my RAM/CPU/VRMs (not sure) when benching AIDA lol, better return to my 4000Mhz settings.


----------



## ManniX-ITA

Yuke said:


> Couldnt boot with 4066/2033 but may try it out with stupid voltages at some point just to be sub 53ns for once. CL14 also didnt boot even at 1.55V, may have to try out 2T with GDM off and a stupid amount of ClkDrvStr. 40 ProcODT was the lowest i could go, 36 already had booting issues (50% chance).


I need stupid voltages and PLL at 1.95V.
Weak CPU LLC for whatever reason.
But I can go down 2-3 counts more than 3800.
Will try tomorrow a 4000 profile.
2T with ClkDrvStr at 60 could go down to ProcODT 32.

SCL at 5 gave me more bandwidth than 4.
tRTP/tWR sey at 8/16 cause doesn't change anything below, same as tRRD set at 8/11.
tWTR 3/8 big gains.


----------



## ManniX-ITA

Yuke said:


> Also, i had weird buzzing and humming sounds coming from my RAM/CPU/VRMs (not sure) when benching AIDA lol, better return to my 4000Mhz settings.


That's coil whine from the VRM, is normal running AIDA. Lots of load and high PWM frequency.
Maybe you didn't really notice till today cause the settings where not so stressing.


----------



## Yuke

ManniX-ITA said:


> That's coil whine from the VRM, is normal running AIDA. Lots of load and high PWM frequency.
> Maybe you didn't really notice till today cause the settings where not so stressing.


Ah, ok, makes sense i guess


----------



## Veii

Yuke said:


> Meh, my personal brickwall it seems
> 
> View attachment 2511289
> View attachment 2511290
> View attachment 2511291
> 
> 
> Also, i had weird buzzing and humming sounds coming from my RAM/CPU/VRMs (not sure) when benching AIDA lol, better return to my 4000Mhz settings.


Is this 4x 8Gb ?
I want to be honest with you. Lower your expectation 🤗
Transition timings (tRRD and tWTR) - transition timings between primaries, are very low
To illustrate:
3800MT/s
tRRD_L (same bank) 6 = 3.1579~ ns
tFAW 16, the time window for 4 ACTIV(ates) = 8.4211 ns (having to push 4 of them through it)

4067MT/s
tRRD_L 4 = 1.9671ns
tFAW 16 = 7.8682ns
this is nearly twice as fast/harsh compared to "what people usually run @ 3800MT/s"
And this "usually" also is faster than JEDEC , which defines it as 8 and higher, not 6 and absolutely not 4 

Increase both tWTR and tRRD to have any chance of going higher
Primaries you still can lower further and further.
4100 16-16-16 should require not more than 1.48v (worst), while for 3800C16-16-16 it runs at 1.36v and lower
Here is a repost of the "easy to run" set ~ i've been working with , in order to explore and stabilize FCLK








This has been so far 4 months old and on another board ~ but the logic remains identical
tRRD bump, does a lot ~ stability wise, and lower primaries even with something for example like this currently benching thing


http://imgur.com/I3bUAx5

 ~ Cloudflare PhotoDNA blocks ?!? this, soo no preview, i'm sorry
Continues to lead a performance benefit over "just tight tertiaries"
Lowering primaries should be your first goal, after you are confident that this FCLK is rockstable
Lowering primaries will require continues rework on RTTs and shifting delays to something "less valuable" , like the transition timings ~ in order to keep up stability

Your tRDWR is also already 1 "too low", 9 or even 10 would be required
10 for DR, 9 for 4x8 - both with tWRRD delay

The only thing you should really change here are the SD,DDs to 1-4-4-1-6-6 (reverse in the bios)
Or 1-5-4-1-7-6 (if it isn't dual rank)
And logically also skip powering settings, as this is 2x8

Another thing to keep in mind, is that SMU 56.50 guaranteed has a changed RZQ & DQs range
Lower RTT_PARK to at least /2, /1 is too strong
For me right now /6 is causing PCB crashes and i'm up to /7
But interestingly RTT_WR /2 works ~ boots i mean, "works" rather not so far. Nothing positive came out of of it


----------



## craxton

well, unhooked ALL DRIVES even my adata 2tb nvme for games this time.
reinstalled windows, and well....STILL

EDIT<(the time change is something that happened after the reboot when installing amd drivers etc.
so overlook the time change as its only a ffew seconds (30 for full shutdown and reboot tops)>










so perhaps, im one ina million who can run ANY FCLK ANY FREQUENCY on RAM...without WHEA errors...
showing task man, (it had installed drivers ffor the board, mouse software, logitech software etc.... but
nothing more as it would or should WHEA straight away...
(THE SECOND DRIVE, wasnt hooked up when installing....
backed up this registry to import it to my actual install.

as i did something to power plans that i couldnt undo..
Veii always sharing stuff and me always using without knowing what im doing before hand lol
but, anyhow
WHEA FREE FCLK from ANY-4066 as thats as far as ive tested thus far, 5600x
4x8 SR (b550 gaming edge wifi rev 1.0 bios 1.2.0.1(version is in another post possible a page or two back
shared link for those using this board and wishing to use it)
first launch 5600x) scalper sold)
dont use ethernet only wifi, dont use nothing but display port,
have gen 3 set on all inside bios that i can possibly set it to.

(use-c does some strange stuff while having ANY usb 2.0-up to type ANY A usb device hooked up
where it connects (rather just keeps giving the disconnect sound, on ONE DEVICE)
but my phones, and other things etc doesnt do this....

2070S FTW 3 ultra+, no mods to bios, no mods to registry/power plans straight 4000/2000 with
CO..... scratching my head as to how im either lucky to be WHEA FREE? or im unlucky enough to get
some kind of issue where it doesnt even start the service for the other whea loggers????

thankyou to all whos helped me up to this point. unsure if i honestly believe windows to be true to this (WHEA FREE EVENT LOG)
although its clear ? sigh, others screaming leave it be...the back of my head saying
somethings not right somewhere? idk...sorry fellas, maybe another board when it comes in
ill know if the chips (a one ina mill) sample or not?


----------



## hazium233

craxton said:


> ...
> 
> so perhaps, im one ina million who can run ANY FCLK ANY FREQUENCY on RAM...without WHEA errors...
> .
> 4x8 SR (b550 gaming edge wifi rev 1.0 bios 1.2.0.1(version is in another post possible a page or two back
> shared link for those using this board and wishing to use it)
> ..


I have been really lazy since getting my 5600X on the 17th of last month. But as soon as I installed it I went to 1.63 beta which was the one out.

The other day I had 2x8GB Flare X 3200C14 installed, and before going to bed I had just tried to boot 1900 FCLK then 2000. 1900 seemed ok for the few minutes in Windows, but trying my random voltages for 2000 ended up with ~200 WHEA 19 in the few minutes I was in Win. I was running async, and hadn't manually set PCI gen, but I only have Gen 3 gpu and NVME anyway. I do have 4xSATA drives connected (2xSSD, 2xHDD)

Maybe I will need to try the older version, or maybe just live with pedestrian FCLK. Either way, I need to get back into the swing because I have too much ram that I want to test.

edit: I also don't use the LAN, and it is enabled. Actually now that I think about it, not sure what driver is installed either.


----------



## DeletedMember558271

craxton said:


> well, unhooked ALL DRIVES even my adata 2tb nvme for games this time.
> reinstalled windows, and well....STILL
> 
> EDIT<(the time change is something that happened after the reboot when installing amd drivers etc.
> so overlook the time change as its only a ffew seconds (30 for full shutdown and reboot tops)>
> 
> View attachment 2511300
> 
> 
> so perhaps, im one ina million who can run ANY FCLK ANY FREQUENCY on RAM...without WHEA errors...
> showing task man, (it had installed drivers ffor the board, mouse software, logitech software etc.... but
> nothing more as it would or should WHEA straight away...
> (THE SECOND DRIVE, wasnt hooked up when installing....
> backed up this registry to import it to my actual install.
> 
> as i did something to power plans that i couldnt undo..
> Veii always sharing stuff and me always using without knowing what im doing before hand lol
> but, anyhow
> WHEA FREE FCLK from ANY-4066 as thats as far as ive tested thus far, 5600x
> 4x8 SR (b550 gaming edge wifi rev 1.0 bios 1.2.0.1(version is in another post possible a page or two back
> shared link for those using this board and wishing to use it)
> first launch 5600x) scalper sold)
> dont use ethernet only wifi, dont use nothing but display port,
> have gen 3 set on all inside bios that i can possibly set it to.
> 
> (use-c does some strange stuff while having ANY usb 2.0-up to type ANY A usb device hooked up
> where it connects (rather just keeps giving the disconnect sound, on ONE DEVICE)
> but my phones, and other things etc doesnt do this....
> 
> 2070S FTW 3 ultra+, no mods to bios, no mods to registry/power plans straight 4000/2000 with
> CO..... scratching my head as to how im either lucky to be WHEA FREE? or im unlucky enough to get
> some kind of issue where it doesnt even start the service for the other whea loggers????
> 
> thankyou to all whos helped me up to this point. unsure if i honestly believe windows to be true to this (WHEA FREE EVENT LOG)
> although its clear ? sigh, others screaming leave it be...the back of my head saying
> somethings not right somewhere? idk...sorry fellas, maybe another board when it comes in
> ill know if the chips (a one ina mill) sample or not?
> 
> 
> View attachment 2511302


And you have Realtek RTL8125B 2.5G. And others without it are still having WHEA 1933+, like @Blameless, with his ASRock B550 Phantom Gaming-ITX/ax, Intel I225-V 2.5G.
So still no clear indication of what's wrong or anything anyone can do or buy, no single board everyone is WHEA-free on.
I wonder what would happen if you and Hazium were able to trade boards, if he would lose WHEAs and you would gain them? If it's really just the board being magically different and nothing to do with other parts or personal configuration somehow. It just doesn't make sense


----------



## mongoled

mongoled said:


> *Unknowns*
> How can we check that the DPM LCLK and DF-States settings are actually being applied ??
> How can we check that the voltages ive applied are not being auto corrected ??


Nobody??


----------



## lmfodor

Veii said:


> Never really failed on thaat test , but it is CPU related
> Probably Loadlines related & Powerdraw/installation related
> 
> If you where just at the limit , Mosfets heat up too much , efficiency dropped, ripple increased & you crashed
> Stronger switching frequency or lower vdroop (oor subtle positive vcore and more vdroop ~ soo more headroom)
> Should resolve your issue
> 
> If you had normal voltage issues, you wouldn't pass more than 2 cycles.
> Reaching thermal equilibrium takes around 30-40min, reaching heat soaking thermal equilibrium
> Soo the rest could be a fridge which turned on - or switching from daylight to night-power
> Just a tiny voltage drop ~ but it also can be the heat that increased ripple
> 
> Focus on this part first
> If you can not resolve it, it can be problems with tREFI (tRFC) , but usually TM5 will report this with 20 cycles
> 25 for sure will find tREFI issues ~ soo i strongly think it's a loadline+heat issue
> 
> EDIT:
> If you want to be very sure it's not Heat+FCLK (powersuply ripple related by external source)
> Loop FFT+N64 for 10 loops = 20min
> that should destabilize the memory controller within 10-15min , soo 5+ loops should make it crash
> If it doesn't , then VDDG voltages are fine and it was just a heat+mosfets ~ loadline, issue


Hi everybody! I'm stuck here unable to advance. Yesterday I left y-cruncher for the whole night, however after 3 and a half hours I had an error. It is a difficult test, but beyond that I still have BSOD 41. As you can see, the errors are from recently (two weeks) The last changes I made was
1) Upgrade to BIOS 56.50
2) On the Kedarwolf values, which were super stable, I tried to lower the VSOC from 1.2 to 1.12 and 1.10. At TM5 level I had no problems, but that was a change that maybe is hurting me.
2) Set the CadBUS Setup to 56-56-56 to enable 1T

And what I did to try to modify something and test if the error is resolved:
1) Set the LLC of the CPU to Level 3, leaving the SW Freq at 500 and taking the CPU Power Phased Control to Extreme, because I read in the CTR 2.0 guide that this makes the OC more stable
2) Lower the PBO from -24 to -20. then to -15
3) Lower the values of PPT, TDC and EDC, before it had 300/245/400 and now lower values. In the SMU menu, just leave Power Package (PPT) at 400, the rest DF and CStates Disabled, and CPPC and Preferred cores enabled.

This is new, maybe it is the 1T with the 56-56-56, even passing all the OOCT tests with AVX, AVX2 and SSE, all in Extreme and Large, cycling and not cycling cores. Also 1Usmus for 30 cycles and Anta777 for 30 cycles, several times. It would seem that it is not the memory, however my last similar problem yesterday in January of this year with some HyperX Predator 4000CL19 travels drove me crazy until I had to change them. Therefore, despite passing all the tests that does not seem like a memory OC error, it brings that memory back to me.

What seems most is an error of overheating or mosfets or VRMs, I do not know how to compensate and test
The teacher @Veii suggested that I adjust to increase the Switching Freq, but I am at maximum or lower the vdroop (would it be to put the LLC in 2?) Or else put a vCore with positive offstet and increase the LLC so that there is more headroom, or see if I have problems with the tRFi TRFC, although the TM5 in 25 cycles should show it and if not try Loop FFT + N64 for 10 loops = 20min that should destabilize the memory controller within 10-15min, soo 5+ loops should make it crash If it doesn't, then VDDG voltages are fine and it was just a heat + mosfets ~ loadline, issue. Here I can run it without problems and I have no errors ..








So I'm lost, what other test can I take? This is new, I don't know whether to revert to a 56.45 BIOS. Or go down to 2T, look here when I take the Kedarwolf values, leave it 45 cyclos. in 2T and with 1.2V vSOC, then I lowered it to 1.1, maybe the VSOC should be higher.


Spoiler: Kedarwolf Timings Test



41 Cycles!
[/SPOI







LER]


I'm really lost, what would they do or try? I want to get out of this situation, I no longer know what to think about what it could be.
Thank you!

I'm really lost, what would they do or try? I want to get out of this situation, I no longer know what to think about what it could be.

Thank you!


----------



## ManniX-ITA

lmfodor said:


> I'm really lost, what would they do or try? I want to get out of this situation, I no longer know what to think about what it could be.


Your 5900x is exceptional 
My 5950x wouldn't even finish the first y-cruncher test without rebooting with these settings.
Especially with that 1T profile which is twice demanding than the 2T.

You may be super lucky but if you want to push RAM overclock you need more VSOC; I wouldn't go below 1.12V, better 1.14V.
Only scale down if you are 100% sure y-cruncher it's not failing and/or you don't loose performances.
Lower VSOC means also lower performances in some tests.
Use CPU-z and Geekbench 5 to test if/how these settings are impacting the perf.

The there's also the VDDG CCD; dual CCDs are more needy, you may be lucky but test with Geekbench 5.
Raise the CCD to 1000mV and run again Geekbench 5. If you see an increase in some benchmarks, CCD was too low.

There's also the VRM settings that could crash y-cruncher.
PWM switching frequency and LLC could be borderline enough and needs a bump.

Plus there's CO counts; did you test with CoreCycler?
Could be very well -20 is too much for Core 9 or other cores and you need to fix it.

You have a lot of work to do before giving up


----------



## lmfodor

ManniX-ITA said:


> Your 5900x is exceptional
> My 5950x wouldn't even finish the first y-cruncher test without rebooting with these settings.
> Especially with that 1T profile which is twice demanding than the 2T.
> 
> You may be super lucky but if you want to push RAM overclock you need more VSOC; I wouldn't go below 1.12V, better 1.14V.
> Only scale down if you are 100% sure y-cruncher it's not failing and/or you don't loose performances.
> Lower VSOC means also lower performances in some tests.
> Use CPU-z and Geekbench 5 to test if/how these settings are impacting the perf.
> 
> The there's also the VDDG CCD; dual CCDs are more needy, you may be lucky but test with Geekbench 5.
> Raise the CCD to 1000mV and run again Geekbench 5. If you see an increase in some benchmarks, CCD was too low.
> 
> There's also the VRM settings that could crash y-cruncher.
> PWM switching frequency and LLC could be borderline enough and needs a bump.
> 
> Plus there's CO counts; did you test with CoreCycler?
> Could be very well -20 is too much for Core 9 or other cores and you need to fix it.
> 
> You have a lot of work to do before giving up


Hi @ManniX-ITA !! How good it is to have you here and thank you for always helping us! 

I did not know that the vSOC value for 1T influenced, I was always guided by the minimums for a certain frequency, that's why I started to go down, in fact Kedarwolf had 1.2 of vSOC for 2T and it worked perfect for me, only it made me noisy to have so high vSOC for 3800MHz. 

But I can run 1.14 with 1.5V VDIMM without problems right? I don't have as many possibilities of high switching frequencies as in the MSI boards, I have up to 500 maximum of CPU VRMs and 600 maximum of VSOC, with LLC 3 for the CPU and LLC4 for the VSOC VRM. I didn't apply any offset to my vCORE and it could lower my All core to -15. The truth is, I have a super tested curve for weeks with Core Cycler, but I thought that this could be causing the crash, so instead of having cores at -30 -28 and so, I decided to choose the lowest value and run all of them at -24 . But I can get back to the tight curve. I thought that by loosing the curve and lowering the undervolt I could stabilize the problem. I have a confusion with the voltages. And these BSODs make me think that it is some voltage issue. I will try the following 

1) Go back to my fitted curve 
2) Raise the vSOC to 1.14, the CCD to 1 and the IOD to 1.09 to keep a distance of 0.05V 
3) About my LLCs, is that okay? Thanks again! 

1 hour running test FFT and N64.. to destabilize the memory controller. and keep running


----------



## craxton

hazium233 said:


> I do have 4xSATA drives connected (2xSSD, 2xHDD)


i as well, (wait) ive 3 drives thru sata on port 1, 5,6
my 2 wd blue 500gb ssd's and my 1tb wdblue hdd which is years old by now but
its where backups go from time to time...



hazium233 said:


> But as soon as I installed it I went to 1.63 beta which was the one out.


so, your literally running 4000 on 1.63/1.2.0.2???????? 
no post anything over 1966 for me....4000 is either locked, or
what was stable is nomore....and that new setting (posted one time with 4000mhz on
current timings all the same settings,) but that new setting inside the bios 
in amd section does something strange and messes with performance 
or something so i went back after failing to boot 9 times ina row

each time needing clear cmos.



hazium233 said:


> Actually now that I think about it, not sure what driver is installed either.


im pretty sure, mine are up-to-date for the most part...
never use ethernet tho...EVER


Dreamic said:


> And you have Realtek RTL8125B 2.5G


yes, only wifi..which i think runs thru intel?
maybe if LAN isnt used its not thrown???
assumptions here, but if your using it, disable?



Dreamic said:


> no single board everyone is WHEA-free on.


some may be free on yada board, but yada board might give yoda errors.
and vise versa....are you guys running 2 NVME drives as well????



Dreamic said:


> , if he would lose WHEAs and you would gain them?


i was wondering the same thing if i were to either BUY another board (the same)
or another vender perhaps and check to see whats logged there....

maybe im not getting WHEA due to the fact its not checking for them? UNSURE???
manna stated that i may be missing one...but since i reinstalled windows with 
NO DRIVES other than a CLEAN one, im unsure if im missing one rather 
windows just installs whats needed per board? (CURRENT WINDOWS BTW)
downloaded tonight !


----------



## craxton

Oh, BTW that power thing Veii shared earlier, USE IT WISELY otherwise
you might tell windows your CPU runs at 0mhz FFS like i did not paying attention 
then restarting windows and it just staying on boot the hole time...

unless trying to copy the registry from another install screwed something up?
dunno never tried it before but im back to the start with getting rid of windows bloat ware b.s.

but, that tool is nice, my only thing is needing to know/understand what most of the processor stuff is for etc.
use wisely lol


----------



## lmfodor

ManniX-ITA said:


> Your 5900x is exceptional
> My 5950x wouldn't even finish the first y-cruncher test without rebooting with these settings.
> Especially with that 1T profile which is twice demanding than the 2T.
> 
> You may be super lucky but if you want to push RAM overclock you need more VSOC; I wouldn't go below 1.12V, better 1.14V.
> Only scale down if you are 100% sure y-cruncher it's not failing and/or you don't loose performances.
> Lower VSOC means also lower performances in some tests.
> Use CPU-z and Geekbench 5 to test if/how these settings are impacting the perf.
> 
> The there's also the VDDG CCD; dual CCDs are more needy, you may be lucky but test with Geekbench 5.
> Raise the CCD to 1000mV and run again Geekbench 5. If you see an increase in some benchmarks, CCD was too low.
> 
> There's also the VRM settings that could crash y-cruncher.
> PWM switching frequency and LLC could be borderline enough and needs a bump.
> 
> Plus there's CO counts; did you test with CoreCycler?
> Could be very well -20 is too much for Core 9 or other cores and you need to fix it.
> 
> You have a lot of work to do before giving up


HI Mannix, I rise vSOC to 1.14, CCD to 1 and IOD 1.09V. I went back to my previous tight timings teste with Curve Optimizer, so they are tight, without scalar and only 125Mhz of Boost Override.

Regarding VRM and PWM Switching, cosidering my asus values, what should I use? I mean, LLC 3 for CPU and LLC 4 for vSOC? the SW Freq is capped to 500 for CPU and 600 for vSOC. This is how I'm running now:








And this my Geekbench, I never used it, the first was with the 1.1 vSOC and 0.95 IOD, the second 1.14vSOC and 1 CCD and the third one the same but with the tight curve, going from -30 to -24
Are they good values?








Thanks!!


----------



## Taraquin

Yuke said:


> Meh, my personal brickwall it seems
> 
> View attachment 2511289
> View attachment 2511290
> View attachment 2511291
> 
> 
> Also, i had weird buzzing and humming sounds coming from my RAM/CPU/VRMs (not sure) when benching AIDA lol, better return to my 4000Mhz settings.


Do you really need 1.54V on ram to run 4066cl16? I have a poorly binned B-die and can run about the same settings as you with 1.47V, 4000cl15 works fine at 1.5V (but my ram overheats after a while above 1.45V so can only use it for a few minutes in stresstesting.


----------



## mongoled

Taraquin said:


> Do you really need 1.54V on ram to run 4066cl16? I have a poorly binned B-die and can run about the same settings as you with 1.47V, 4000cl15 works fine at 1.5V (but my ram overheats after a while above 1.45V so can only use it for a few minutes in stresstesting.


4 x 8GB bdie need no more than 1.48v running at 4133 mhz flat 16s


----------



## DeletedMember558271

craxton said:


> yes, only wifi..which i think runs thru intel?
> maybe if LAN isnt used its not thrown???
> assumptions here, but if your using it, disable?
> 
> 
> some may be free on yada board, but yada board might give yoda errors.
> and vise versa....are you guys running 2 NVME drives as well????
> 
> 
> i was wondering the same thing if i were to either BUY another board (the same)
> or another vender perhaps and check to see whats logged there....
> 
> maybe im not getting WHEA due to the fact its not checking for them? UNSURE???
> manna stated that i may be missing one...but since i reinstalled windows with
> NO DRIVES other than a CLEAN one, im unsure if im missing one rather
> windows just installs whats needed per board? (CURRENT WINDOWS BTW)
> downloaded tonight !


Doesn't matter if I unplug and disable LAN in BIOS and uninstall in device manager, still WHEAs.
I have 1 NVMe, 980 Pro.
Temporary clean install of Windows changes nothing either, even with LAN and as many things disabled in BIOS and unplugged as possible and with no internet during install so no background downloading, and no ability to detect anything disabled/unplugged to install Microsoft basic drivers.
I'd be curious what happens if you ever get another board or CPU.
I don't know why you're fine and I'm not, our boards are almost the same if not identical in most ways, and Haziums is the same as yours obviously but WHEAs.
I don't like that the only solution appears to be start buying motherboards until you find one that works, or find someone that already has found such a magical motherboard and offer to buy it lol.
And then what if I somehow still have 1933+ WHEA with it... cause who ****ing knows


----------



## mongoled

Why dont we coordinate an influx into the AMD official forums with all our findings with regards to the WHEA warning "19" issue.

If we keep posting information over there, surely there will come a time that someone higher up in AMD are going to have to make some sort of statement as it would be quite an embarassing for them that this is aired in their own public forum.

See what other peeps think ...


----------



## RonLazer

Does anyone else have their WHEA 19s spread exactly at 60s intervals? I get 1 WHEA event a minute, always exactly one minute from when the first appears too. It's happened on multiple CPUs and OS builds, so I'm guessing it's a Windows configuration issue?


----------



## Speede

Stable 3800 GDM OFF 1T VDIMM 1.5V *F4-3600C14D-16GTZNB *tested in TM5 and OCCT


----------



## GamingWiidesire

RonLazer said:


> Does anyone else have their WHEA 19s spread exactly at 60s intervals? I get 1 WHEA event a minute, always exactly one minute from when the first appears too.


Yes, same for me with IF 1866 to 1933. Interestingly enough I switched mainboards and with the old one (ASRock X470 Taichi Ultimate) IF 1866 was possible without WHEA ID 19, now with a MSI B550 Gaming Carbon WiFi only IF 1833 is possible without WHEA errors.


----------



## ManniX-ITA

RonLazer said:


> Does anyone else have their WHEA 19s spread exactly at 60s intervals? I get 1 WHEA event a minute, always exactly one minute from when the first appears too. It's happened on multiple CPUs and OS builds, so I'm guessing it's a Windows configuration issue?


Did you check with HWInfo?
Cause could be Windows is throttling the flow.
HWInfo usually reports all of them.


----------



## ManniX-ITA

mongoled said:


> Nobody??


I think only with indirect observation.
If it has an effect, good or bad, then it works.
Voltages can be tricky to detect with a scope on the measuring points...


----------



## mongoled

ManniX-ITA said:


> I think only with indirect observation.
> If it has an effect, good or bad, then it works.
> Voltages can be tricky to detect with a scope on the measuring points...


Then unfortunately we are all in the dark regarding if these unhidden options actually do anything, this is a huge barrier in being able to troubleshoot the issue as indirect observation is not a good means to do this.

Regards measuring points, we need to be aware if autocorrection also effect the measuring points on boards that have them, this could be an easy test for those who have boards that have measuring points.

The Unify I have does not have such measureing points, at least from what I know ..


----------



## Yuke

Taraquin said:


> Do you really need 1.54V on ram to run 4066cl16? I have a poorly binned B-die and can run about the same settings as you with 1.47V, 4000cl15 works fine at 1.5V (but my ram overheats after a while above 1.45V so can only use it for a few minutes in stresstesting.


well according to Vei its because of too tight sub-timings, but yes i needed the bump in voltage with those sub-timings


i can do 2000/4000Mhz at 1.49V (as posted before) but yes...if i switch to 4066 with the same subtimings i needed 1.54V for a error free karhu pass.

gonna test out what Vei suggested and reduce RRD's to 6/12 and tRTP/tRDWR to 8/10

in my experience reduction of tCL and tRFC is the only one that let me reduce voltage *significantly*, tho. Next best to change was always tRP/tRAS/tRC combo regarding voltages.


----------



## ManniX-ITA

mongoled said:


> Then unfortunately we are all in the dark regarding if these unhidden options actually do anything, this is a huge barrier in being able to troubleshoot the issue as indirect observation is not a good means to do this.


It's not the best but it's what we do most of the times and it works.
Run a lot of benchmarks and stability tests, take HWInfo screenshots and CSV loggings and you'll be able to find out most of the times.
Problem is since it's not an efficient method it takes a lot of times, sometimes weeks to validate a single change.


----------



## RonLazer

@ManniX-ITA HWInfo is the same.


----------



## ManniX-ITA

Yuke said:


> gonna test out what Vei suggested and reduce RRD's to 6/12 and tRTP/tRDWR to 8/10


I'm still experimenting but indeed all that he said holds true.
I'd try to keep very low tWTR cause that's a big bump in performances.
Lowering tRRD and tRTP/tWR didn't have any noticeable effect.


----------



## ManniX-ITA

RonLazer said:


> @ManniX-ITA HWInfo is the same.


I think once with a specific BIOS and settings I was able to reduce it to something like this, one WHEA very regular.
Not sure it was once 1 minute.
I did set 1.1V VSOC straight. Was almost WHEA free but performances were poor.


----------



## mongoled

Currently testing 4133/2067 flat 16s 1T on the A93 Unify X570 BIOS.

Earlier run finished with one error 6 and one error 3 in 2hrs 45 mins.

I changed only RttNom from 6 to 7, hopefully will get a pass then onto testing other applications.

Have been here before 4133/2067 TM5 stable on the A85 BIOS, but with that BIOS games would hardlock, hoping the A93 BIOS does not have the same issues


----------



## PJVol

mongoled said:


> *Unknowns*
> How can we check that the DPM LCLK and DF-States settings are actually being applied ??
> How can we check that the voltages ive applied are not being auto corrected ??
> Nobody??


You can check perf/effective LCLK clocks at 0x01D0h and 0x01D8 offsets (valid If your CPU is "single-CCD"), as for voltages, if you mean vdd... , as @Veii said, there are only getter seem to exist.


----------



## mongoled

PJVol said:


> You can check perf/effective LCLK clocks at 0x01D0h and 0x01D8 offsets (valid If your CPU is "single-CCD"), as for voltages, if you mean vdd... , as @Veii said, there are only getter seem to exist.


What are you using to read the offsets ?


----------



## domdtxdissar

domdtxdissar said:


> The deed is done, have gotten this fully stable
> 
> BIOS 3501 with AGESA V2 PI 1.2.0.2
> dual CCD 5950x
> 4x8GB gskill 3600 CL16
> 1900:3800 @ flat CL14 + T1 GDM-OFF
> Screenshot of TM 1umus 25 cycle + Memtest 20000% stable (do notice this is my old bloaty windows install with lots of stuff running in background)
> View attachment 2490191
> 
> 
> 
> Newest OCCT 8.1.3 1 hour large dataset extreme + 4 iteration in y-cruncher with all tests (same boot as above)
> View attachment 2490192
> 
> 
> Some performance number:
> The SiSoftSandra v2021.31.12 (from Mar 5th, 2021). Not sure this is a good match with CTR..
> Intel latency checker
> View attachment 2490194
> 
> 
> 
> Next we have dram calc easy + normal bench together with cinebench r23
> View attachment 2490195
> 
> 
> And lastly we have SotTR @ 1080p lowest as a gamebench running on my new 24/7 settings =288 CPU average fps
> View attachment 2490196
> 
> 
> Very happy with these results and my new 24/7 settings
> Maybe i will try to push for higher fclk now 😎
> 
> Feel free to leave any comments or questions


So i have been playing around with this further.. managed to squeeze out tRFC 240 while lowering vdimm to 1.54 volts (which is the lowest i can run for these settings)
(-2 tRAS timing compared to previous settings)


----------



## PJVol

mongoled said:


> What are you using to read the offsets ?


Sorry, was in hurry when answering 
I mean debug tool in ZenTimings, scroll down to SMU power metrics table. Search for those offsets. On clicking "debug" button you can see their current value as soon as pm table refreshes.


----------



## KedarWolf

My 16-16-16-36 4000MHz RAM came today, but I won't be home from work until about eight hours from now to play with it.


----------



## jomama22

KedarWolf said:


> Improved my score by a decent margin.
> 
> View attachment 2511287


How did you set up/what drivers are needed for the 3090 to do floating point? Get "GPGPU call failed" when testing.


----------



## Blameless

mongoled said:


> How can we check that the DPM LCLK and DF-States settings are actually being applied ??
> How can we check that the voltages ive applied are not being auto corrected ??


No idea on DPM LCLK, other than observing changes in behavior over a statistically relevant period.

DF C-states are pretty easy. SoC voltage and current draw will remain relatively elevated (no voltage reduction, 15-20A SoC current), even at idle, with them disabled.

Without physical measurements, you can't be 100% sure about voltages, so it's down to looking at any software-polled sensors available and paying attention to system behavior.



mongoled said:


> Going from 3800/1900 to 3866/1933 results in thousands of WHEA warnings, no combination of settings had any effect


I was never able to fully eliminate WHEA 19s at 1933 on my 5800X sample, but several settings made a statistically significant difference in rate at which they occurred. Biggest thing by far was SoC and VDDG IOD, which I needed to raise significantly...only after 1.15v SoC and 1.08v DDG IOD did things stop improving (and rapidly became less stable as I approached 1.2v SoC). CPU PLL (1.8v) increases and DPM LCLK settings also helped, up to about 1.88v.



Dreamic said:


> And you have Realtek RTL8125B 2.5G. And others without it are still having WHEA 1933+, like @Blameless, with his ASRock B550 Phantom Gaming-ITX/ax, Intel I225-V 2.5G.
> So still no clear indication of what's wrong or anything anyone can do or buy, no single board everyone is WHEA-free on.
> I wonder what would happen if you and Hazium were able to trade boards, if he would lose WHEAs and you would gain them? If it's really just the board being magically different and nothing to do with other parts or personal configuration somehow. It just doesn't make sense


Board/firmware can definitely make a large difference.

I've been swapping around CPUs between my B550 Phantom Gaming ITX/ax and my Arorus X570 Elite Wifi and noticed some interesting oddities.

My 5800X reaches about the same FCLK on the newest firmware of both boards...haven't been able to full stabilize 1933 on either, but might be able to on the Aorus, if I spend more time with it.

My 3900X can do a full 133MHz FCLK more on the Gigabyte than on my ASRock...it's bench stable at 2000 FCLK. Still throws WHEAs, but it's usable to at least 1967, which is pretty impressive for a Matisse. After swapping the CPU back to my ASRock B550, I realized (via Zen Timings) what the issue was...the ASRock board ignores my vDDG CCD setting and just applies the vDDG IOD to both, which makes CCD way too high for the upper FCLK range. It doesn't have this problem with Vermeer.

Anyway, I think one would need a known good board/firmware combo for a given line of chips, and then a crapton of CPU samples to really get a meaningful idea of what the range of CPU limitations actually were. No matter how honest or competent individual enthusiasts are there are too many variables to take into account, and few of us have enough CPU samples to go through to really come to any firm conclusions.

_Edit_: I may have been mistaken about this B550 ITX/ax not taking CLO VDDG CCD settings...I am getting intermittent WHEAs on my 3900X again with CCD voltage set lower than what I was using before. I think this CPU just needs a ton of VDDG CCD to be completely stable in this board.


----------



## hazium233

craxton said:


> so, your literally running 4000 on 1.63/1.2.0.2????????


No, I was only seeing what FCLK I could boot, and that was asynchronous. Ram was just at XMP 3200.

The voltage settings were likely crap, but 2000 FCLK booted easily. It was just that it had so many WHEA 19 I was annoyed and went to sleep. SOC 1.175, VDDP 0.900, CCD 0.950, IOD 1.050 so maybe that combo is just bad for me.

I haven't tested the Flares except to make sure they worked at XMP. Similarly, I had picked up 2x16GB dual rank Rev E 3200C16 and tested them for function at XMP and those are in the machine right now.

I can try the ram at 4000MT/s tonight although I was mostly planning on just trying to hammer out "simple" 3600 - 3800C16 or so and at least get ram settings somewhat accurate to then see about what voltages I need for fabric.


----------



## hazium233

I don't know if I have forgotten this, or if I am just ignorant but:

Can I not actually force UCLK==MCLK when fabric is not synchronized? Setting in Overclocking Settings seems to do nothing. Eg FCLK on Auto resulting in 1800MHz, memory set to 4000MT/s (2000MHz), any setting results in 1000MHz UCLK.

I couldn't see another way to change the divisor mode.


----------



## jomama22

KedarWolf said:


> Improved my score by a decent margin.
> 
> View attachment 2511287











My results after getting the gpu thing squared away. Broke the 12's!


----------



## ManniX-ITA

hazium233 said:


> Can I not actually force UCLK==MCLK when fabric is not synchronized?


Not sure I understand... the DIV1 mode UCLK==MCLK means fabric in sync.


----------



## PJVol

Blameless said:


> DF C-states are pretty easy. SoC voltage and current draw will remain relatively elevated


Just disabling them doesn't make any noticeable difference to me, except lowering memory bandwidth according to aida64.


hazium233 said:


> I couldn't see another way to change the divisor mode.


You wont, unless manually set fclk:mclk 1:1


----------



## Yviena

This is my baseline stable 3733mhz i finally managed to make it stable by setting TRTP to 9, and TWR to 18.

I'm gonna try to see if upping it to 3800Cl16 soon. i've downgraded to 1.2.0.0 AGESA though maybe 1.2.0.3 that should release in a month or two will be better.


----------



## KedarWolf

jomama22 said:


> View attachment 2511386
> 
> My results after getting the gpu thing squared away. Broke the 12's!


What GPU do you have?

I have a Strix OC 3090 but can only do 2205 core, +1077 memory without it erroring out in the benchmark.


----------



## jomama22

KedarWolf said:


> What GPU do you have?
> 
> I have a Strix OC 3090 but can only do 2205 core, +1077 memory without it erroring out in the benchmark.


Same gpu. You can look at the different results on the leaderboard and compare them. I just have an old rusty pcie 4.0 name, not the new fangled ones with 7000+ reads lol.

It's actually funny, not sure how they calculate the final kpt but the drive benchmark must be worth a ton lmao.


----------



## KedarWolf

jomama22 said:


> Same gpu. You can look at the different results on the leaderboard and compare them. I just have an old rusty pcie 4.0 name, not the new fangled ones with 7000+ reads lol.
> 
> It's actually funny, not sure how they calculate the final kpt but the drive benchmark must be worth a ton lmao.


I have an M.2 that does nearly 7000 MB/sec read, 6500 MB/sec write. 

But I don't see your score on the leaderboards, I just checked. Either it never updated yet, or there is some kind of problem with your score.

What clocks on core and memory did you run your GPU at?


----------



## jomama22

KedarWolf said:


> I have an M.2 that does nearly 7000 MB/sec read, 6500 MB/sec write.
> 
> But I don't see your score on the leaderboards, I just checked. Either it never updated yet, or there is some kind of problem with your score.
> 
> What clocks on core and memory did you run your GPU at?


Just do the individual results. Up there now. They don't seem the believe most of results as it falls out of their expected deviation lol









Top Overall Score (2K21-2018) Ranks







ranker.sisoftware.co.uk





Gpu was set at 2190/+1225. Get is probably 2145 or so I would imagine during some of the gpu benches.

The anonymous score is also mine. Didn't know how to actually create an account until later so I guess it just put them both there lol

All the anonymous results with the dark hero and 5950x from today or yesterday are mine, that's about all I know lmao.


----------



## hazium233

ManniX-ITA said:


> Not sure I understand... the DIV1 mode UCLK==MCLK means fabric in sync.


FCLK should be a separate domain from UCLK-MCLK, so what I was trying to do was run lower FCLK but higher UCLK=MCLK. Apparently that isn't allowed, which I suppose is not a big deal.

On the other hand, if FCLK > MCLK then you can use UCLK=MCLK, which was the supposed trick if you were somehow stuck on low ram speed to gain some performance on single CCD at least.



Spoiler


----------



## craxton

Dreamic said:


> Doesn't matter if I unplug and disable LAN in BIOS and uninstall in device manager, still WHEAs.


hmm, im actually blind to why im fine then.... ive currently disabled NOTHING on my install
as i (JUST AS OF TEN MINUTES AGO) reinstalled again, since something happened to 
ryzen master and it wouldnt install, all fixes lead to the same thing 
tried revo uninstaller but RM wasnt installed to actually remove registry files anyhow...
the SDK was present, but none the less, a new install is what it took.

i believe when i was installing chipset drivers and RM at the same time as well as
all C++ files at the SAME TIMN it created something that wasnt supposed to happen
and while one thing was still installing or such the board restarted 
(I did quite a few things within that little moment of mayhem)



Dreamic said:


> Temporary clean install of Windows


as do i now, still no sign of WHEA, although i was blue screening 
while not having chipset drivers installed.

and having loads of chrome tabs open, while pagefile was full...
changed the page file and havent had a BSOD since 

no (whea log tho) just page file is all it states under errors....(not whea again)



Dreamic said:


> I'd be curious what happens if you ever get another board or CPU.


its coming, perhaps next month ill checkout whats in my cart, 
ill possibly not buy another CPU, but instead 
(3000) series has WHEA errors as well? i have a near brand new 3600xt
to which (my ol install WHEA logs were from while it was installed) 
so, (ON THIS BOARD) id say i can swap my 5600x into the new board/ test stable settings
and see, while installing the 3600xt into this one and again check whea for logs 



Dreamic said:


> I don't know why you're fine and I'm not, our boards are almost the same if not identical in most ways, and Haziums is the same as yours obviously but WHEAs.


i honestly couldnt tell you, i also updated to what ever version windows released sometime today
which so far no issues arose as of yet...



mongoled said:


> Why dont we coordinate an influx into the AMD official forums with all our findings with regards to the WHEA warning "19" issue.


Every post ive EVER posted in AMD help/support has ALWAYS 
been removed or some b.s. 
dont know if im just posting in the wrong spot or not, but none the less
always find my posts removed...



mongoled said:


> If we keep posting information over there, surely there will come a time that someone higher up in AMD are going to have to make some sort of statement as it would be quite an embarassing for them that this is aired in their own public forum


made 12 posts and all but two have been removed, i dont think itll matter...
but, if you know where i should post on it, link it to me
so i know im in the right spot....


----------



## craxton

hazium233 said:


> No, I was only seeing what FCLK I could boot, and that was asynchronous. Ram was just at XMP 3200.
> 
> The voltage settings were likely crap, but 2000 FCLK booted easily. It was just that it had so many WHEA 19 I was annoyed and went to sleep. SOC 1.175, VDDP 0.900, CCD 0.950, IOD 1.050 so maybe that combo is just bad for me.
> 
> I haven't tested the Flares except to make sure they worked at XMP. Similarly, I had picked up 2x16GB dual rank Rev E 3200C16 and tested them for function at XMP and those are in the machine right now.
> 
> I can try the ram at 4000MT/s tonight although I was mostly planning on just trying to hammer out "simple" 3600 - 3800C16 or so and at least get ram settings somewhat accurate to then see about what voltages I need for fabric.


ahh, (are you running a b550 gaming wifi edge board) ?
if so (if i havent done so) ill link you the bios im on

(ITS MY GDRIVE) trust or not, its where ill download it from once an updates made, 
to where it to is locked and i have to go back lol...

i had horrible luck with E die myself (samsung i believe?) 
was supposed to be b die but none the less never did get stable..
memtest said i was good, but windows needing rebuilt stated otherwise, 
this was before i started actually reading and coming here, or right around the same time 
actually....buildzoid was who stated what they were in a live stream....might have been C die? idfk...

anyhow, good luck, i currently got rid of most my ram....


----------



## hazium233

craxton said:


> ahh, (are you running a b550 gaming wifi edge board) ?
> if so (if i havent done so) ill link you the bios im on
> 
> (ITS MY GDRIVE) trust or not, its where ill download it from once an updates made,
> to where it to is locked and i have to go back lol...
> 
> i had horrible luck with E die myself (samsung i believe?)
> was supposed to be b die but none the less never did get stable..
> memtest said i was good, but windows needing rebuilt stated otherwise,
> this was before i started actually reading and coming here, or right around the same time
> actually....buildzoid was who stated what they were in a live stream....might have been C die? idfk...
> 
> anyhow, good luck, i currently got rid of most my ram....


Thanks. Yes, this is B550 Gaming Edge Wifi, it was produced in Sept of last year.

No this isn't Samsung E-die, it is dual rank Micron 8Gb Rev E in the 3200 16-18-18 bin. Obviously I haven't put in the work yet, but usually it should do any frequency, just the timings won't be amazing.

On the desk are 2x8 Micron 8Gb Rev D, 2x8 Micron 8Gb Rev E, and then the four Samsung 8Gb B-die sticks. Really I always intended to just run the B-die, but I saw this open box 2x16GB Rev E and bought it, heh.

If I can't get 4x8 mixed B-die to work I will just fall back on the E. Both the Trident Z and Flare X are A0 for whatever that is worth for me.


----------



## Blameless

hazium233 said:


> Can I not actually force UCLK==MCLK when fabric is not synchronized?


As observed, everything is either 1:1:1 in sync, or UCLK is half memclock.



PJVol said:


> Just disabling them doesn't make any noticeable difference to me, except lowering memory bandwidth according to aida64.


I can get the SoC below ~20w or so, even completely idle with SoC C-states disabled.

What sort of memory bandwidth differential are you seeing?


----------



## jomama22

mongoled said:


> Why dont we coordinate an influx into the AMD official forums with all our findings with regards to the WHEA warning "19" issue.
> 
> If we keep posting information over there, surely there will come a time that someone higher up in AMD are going to have to make some sort of statement as it would be quite an embarassing for them that this is aired in their own public forum.
> 
> See what other peeps think ...


What findings exactly? I appreciate veii's work thus far but until we have someone who 1) Has no wheas then changes motherboards and gets wheas at 1933+ 2) Has wheas at 1933+, changes boards, then doesn't have them.

We have 0 people like that.

The only reports we have of people over 1933 with no wheas have never had them.

Until we have further proof, I have to believe the cpu plays a roll in this.

Amd never guaranteed anything btw. So to just bombard a forum about not getting 2000 fclk is questionable at best.


----------



## Veii

jomama22 said:


> What findings exactly? I appreciate veii's work thus far but until we have someone who 1) Has no wheas then changes motherboards and gets wheas at 1933+ 2) Has wheas at 1933+, changes boards, then doesn't have them.


Soo welcome to the WHEA #19 club
It's not a tracking issue for sure

The only thing that could've happened yesterday, was a bios reset while experimenting with CO (see WHEA 18)
And i've plugged a PCIe CC (3.0) on a x4 port connected to the chipset
Never had issues plugging in in the CPU m.2 slot one (either m.2 or x4 ~ you know)
Soo i didn't consider it even as a potential issue

The problem to all this:
A.) either i continue to nail specific CBS settings (as these are wiped on fail-boot or cmos reset) and thatt's why i don't WHEA
B.) WHEA 19 remains to be a big chunk of potential issues, while having most of them sorted so far

I think it's more B.)
Currently Ethernet is plugged in and the CC didn't change position
No WHEA 19 on Aida64 or y-cruncher. Things are bizarre

Still continue the path of blaming IO from the Chipset for it
it was one strange 19 without anything associated to it (couldn't track anything, needs a closer look)

Audio in didn't change
USB order didn't change
FLCK didn't change
Nor have i installed new or random drivers 

I've jumped back to ultimate perf, as my powerplan continues to idle shut it down on y-cruncher
On anything else it's fine, but to eliminate potential new issues while playing with CO








Oh, KB5003173 update installed itself yesterday - although windows update and their services where disabled


Spoiler














Same as a strange .Net update
Soo that's +1 on the "bizarre" part 

Currently running








But i remember while testing 21H2 that i didn't have issues either 🤷‍♂️
Problem on this whole bizarreness is, that they don't come back ~ these 19s
"Operational" Mode - only has 20's but old 20's not current one.
2 things are strange. WHEA #19 is an "information" not an "error" aand it's not on the main "operation log" listed

Didn't have ethernet plugged in yesterday (2 days ago)
As i was waiting for a long CAT 8 cable, and kept using phone ethernet usb-drivers 
@mongoled Yes , was waiting for PJVol to write it down, he told/teached me this ~ the levels i figured myself out on Board swaps and external information

DF_C-States only gather the hibernation states
Sadly hibernation and suspended state are two different things with the same ACPI readout
You only know that pure DF states are used, if you have overboost issues / spikes (big spikes not little 180% spikes)
Global C & DF state generation, covers the generation of powerstates down to P3 which is 550mhz


Spoiler: Example






















The pictures where ment for another writeup, soo let's chain the posts together while i'm at it & as an answer is kind of expected, to the phrasing i can read the couple of pages


TimeDrapery said:


> @Veii
> Oh you shared your OS power plan! Thanks! I'm gonna compare it to the others I've got so I can learn more about this side of the house!


The "Alpha" was shared soo that @ManniX-ITA can take a look at the concept of it, learn it and maybe better something up on his own work
This are the positive & couple of issue ~ points i wanted to share later on another writeup


Spoiler












The P0 state should be ACPI 100% or with CO , it's around 105-110% ~ soo it's between 3700-3800Mhz, up to CPU
The reason it spikes that way, is that usually you aren't able to push unused cores to the sleep state while running P0
It is possible, kind off - as you can see, where the Rocket Algorithm (which will push only the needed core up) bumps up the best core & it's SMT thread
The problem with the Rocket algorithm is, that the CPUs aren't able to only push one core higher and only supply it voltage, while keep the rest "individually functioning"
Sure PerCore-C State generation should be functioning according to Hex-Bios "flags". But you where normally never able to break the issue of all other cores being pushed to their corresponding "minimum state" while an "peak boost" runs

One of the things that took 1usmus a long time to "fix" / "explore" / "exploit"
Same as for me, but a bit different
Sadly the Powerplan needs more work ~ now that dLDO functions "finally"








This bottom one was captured while Aida64 run and benchmarked
You can see on some "longer/extended" spikes - that more than one core goes to parked state and free's up powering resources = powerbudget & lowers on it's own silicon strain








on the more right side, is a P2 state held with it's up and down variances or "sleeping" attempts

Usually the plan was designed to utilize exactly this, just that it's a bit too trigger happy on the current state 
This is right now after the mysterious windows update, and i surely have to fix my services again
Something randomly triggers DPC calls, wakes up the cores and the P-Plan can not reach 550mhz low idle state








Soo i'll come back here once i fix my mess and figure out the reason for these random WHEAs


Overall , it's not finished
I hope you understand the only reason i shared it is for ManniX and everyone else to learn
But it's unstable as h*ck and causes random reboots ~ because transitions are not perfect yet. dLDO just gets confused and crashes. Spikes have a too big magnitude difference and the cpu crashes on lack of voltage 
With DF it functions, but that's completely messed up and broken, soo i can only recommend for everyone to keep it disabled for now


craxton said:


> Oh, BTW that power thing Veii shared earlier, USE IT WISELY otherwise
> you might tell windows your CPU runs at 0mhz FFS like i did not paying attention
> then restarting windows and it just staying on boot the hole time...
> 
> unless trying to copy the registry from another install screwed something up?


Haha, you messed up big times 
QuickCPU , the tool you mean - has a button that pushes everything to 550mhz state
Yea you need to hover over some buttons and read what they do - before you enforce a low power state with it

It's useful to edit powerplans, but it can do far more things
Else no, 0 FSB should have been a bug, never made such a "mistake" 
Shared PP is on .txt, to bypass the reasonless restrictions on file uploads ~ which OCN still hasn't fixed, in comparison to HardwareLuxx or Computerbase ~ which both are on Xenforo
Lazyness. . .
========================================
RTL 2.5Gbit will crash itself without having anything plugged into it 
I don't have a board that WHEAs , except maybe "both". lol
Seems like it is indeed tracked, but hey something i always make right and something else fishy that breaks ~ is going on
It will be figured out , so far i don't own any NVMe to figure that part out


----------



## Veii

double-post bug, please ignore


----------



## ManniX-ITA

Veii said:


> RTL 2.5Gbit will crash itself without having anything plugged into it


Did you try the latest EFI UNDI from beginning of May?


----------



## mongoled

PJVol said:


> Sorry, was in hurry when answering
> I mean debug tool in ZenTimings, scroll down to SMU power metrics table. Search for those offsets. On clicking "debug" button you can see their current value as soon as pm table refreshes.


Thanks ever so much, will look into this and see what I get





Blameless said:


> No idea on DPM LCLK, other than observing changes in behavior over a statistically relevant period.
> 
> DF C-states are pretty easy. SoC voltage and current draw will remain relatively elevated (no voltage reduction, 15-20A SoC current), even at idle, with them disabled.
> 
> Without physical measurements, you can't be 100% sure about voltages, so it's down to looking at any software-polled sensors available and paying attention to system behavior.
> 
> I was never able to fully eliminate WHEA 19s at 1933 on my 5800X sample, but several settings made a statistically significant difference in rate at which they occurred. Biggest thing by far was SoC and VDDG IOD, which I needed to raise significantly...only after 1.15v SoC and 1.08v DDG IOD did things stop improving (and rapidly became less stable as I approached 1.2v SoC). CPU PLL (1.8v) increases and DPM LCLK settings also helped, up to about 1.88v.
> 
> Board/firmware can definitely make a large difference.
> 
> I've been swapping around CPUs between my B550 Phantom Gaming ITX/ax and my Arorus X570 Elite Wifi and noticed some interesting oddities.
> 
> My 5800X reaches about the same FCLK on the newest firmware of both boards...haven't been able to full stabilize 1933 on either, but might be able to on the Aorus, if I spend more time with it.
> 
> My 3900X can do a full 133MHz FCLK more on the Gigabyte than on my ASRock...it's bench stable at 2000 FCLK. Still throws WHEAs, but it's usable to at least 1967, which is pretty impressive for a Matisse. After swapping the CPU back to my ASRock B550, I realized (via Zen Timings) what the issue was...the ASRock board ignores my vDDG CCD setting and just applies the vDDG IOD to both, which makes CCD way too high for the upper FCLK range. It doesn't have this problem with Vermeer.
> 
> Anyway, I think one would need a known good board/firmware combo for a given line of chips, and then a crapton of CPU samples to really get a meaningful idea of what the range of CPU limitations actually were. No matter how honest or competent individual enthusiasts are there are too many variables to take into account, and few of us have enough CPU samples to go through to really come to any firm conclusions.
> 
> _Edit_: I may have been mistaken about this B550 ITX/ax not taking CLO VDDG CCD settings...I am getting intermittent WHEAs on my 3900X again with CCD voltage set lower than what I was using before. I think this CPU just needs a ton of VDDG CCD to be completely stable in this board.


Fully under your sentiments and means of studying behavioural changes and as you and others have asserted, its time consuming and its based on peeps interpreting these changes correctly which in itself is not an easy task to keep track of every little known change, never mind the unknown gremlins that creep in from time to time, hence the reason for asking if there is a more "reliable" way to track what's occurring with the changes we make in settings.

As with others, have also spent copious amount of hours making small changes here and there, but when I think ive seen pattern a subsequent reboot will "break" the pattern, so back to step one again ....



craxton said:


> Every post ive EVER posted in AMD help/support has ALWAYS
> been removed or some b.s.
> dont know if im just posting in the wrong spot or not, but none the less
> always find my posts removed...
> 
> made 12 posts and all but two have been removed, i dont think itll matter...
> but, if you know where i should post on it, link it to me
> so i know im in the right spot....


Damn, was never aware they moderated their forums in such a way!

That is not what I would have expected, provided the information was being put across in a constructive non volatile manner.



jomama22 said:


> Amd never guaranteed anything btw. So to just bombard a forum about not getting 2000 fclk is questionable at best.


I totally agree, its all overclocking, but the hope would be that there enough people posting respectfully and constructively about the issue in the hope of getting greater attention.

It would have to be a structured post, emphasizing a specific subset of questions, I would not jump in to 2000 mhz territory, best to stay closer to what most peeps are seeing and that is from 1866-1900 WHEA 19 warning are for most peeps non existent, then the next postable hop results in 1000s of WHEA 19s while the system shows to be stable.

This is what I I believe such a post should concentrate on.

Once you get peeps chiming in "crying" why they cant have 2200 mhz running WHEA 19 free then the discussion looses its value...



Veii said:


> Yes , was waiting for PJVol to write it down, he told/teached me this ~ the levels i figured myself out on Board swaps and external information


----------



## Veii

ManniX-ITA said:


> Did you try the latest EFI UNDI from beginning of May?


Not sure, haven't tracked the issue further on the dark hero. Its been some time, probably till update 1200
Didnt know what to track at that point of time
Only got "mad" as Realtek Team continued to drive that path of barely doing anything ~ according to close source communication between board manufactures and them
While as it's been linked here, Intel resolved it decently fast

When i think about it
The x570 gigabyte Pro Rev1.0 has an I225-V
It was soo strange and "useless" to make two more revisions, just to include a simple thunderbolt 5-pin power header on it

Need to read through that reddit page and see where you can read out what revisions of I225-V you have

@craxton that scalper cpu
I wish you'd have that CPU SCU number noted down
Revision and fab number
If it is BG 20xx or 21xx, overall the batch number
But dont tell the middle part of the serial number, only the last part of it

If anybody would know how to rewrite the OPN number
It would be helpful to finally rebrand this 5600X
Except the OPN number and maybe something inside RSMU written,
There is nothing that tells the microcode the difference between a 5600X or 5800X 

Sadly that's about all I know so far
Unless i gather RSMU to program the unit. I only can question how to rebrand it, while it's work in progress from another sources


----------



## rossi594

I did what I seem to do every day lately I get up and try to dial in my voltages to make the whea 19s go away. 

I tryed to run the aida64 benchmark and see where the errors appear and adjust the voltages acordingly (errors everywhere = vsoc errors in mem latency = vddg iod errors in cache = vddg ccd).
Then later I did not run the test because the mail came and I still had the errors. They appear in a repetetive pattern and it's time / clockcycle based. I think it has something to do with power management. I did not do anything with the system.


----------



## rossi594

I managed to reduce the ones appearing early with more vsoc and vddg iod.


----------



## Blameless

jomama22 said:


> What findings exactly? I appreciate veii's work thus far but until we have someone who 1) Has no wheas then changes motherboards and gets wheas at 1933+ 2) Has wheas at 1933+, changes boards, then doesn't have them.
> 
> We have 0 people like that.


The behavior of my 3900X between my ASRock B550 and Gigabyte X570 is like that. Huge WHEAs at 1900, no POST at 1933 on the former. No WHEAs at 1900, maybe even 1933 (if I had bothered to test and tune further), bench stable all the way to 2000 on the latter.

My 5800X didn't show anywhere near as much of a difference and I'm not sure if I could have made it WHEA free on one setup at the same FCLK where WHEA's were prevalent on the other, assuming equal effort given to both.

Main issue is how long testing for WHEAs takes when near the edge of stability. I can clearly see a different in rate of WHEAs between boards, but claiming they are absent, with anything approaching confidence, takes a lot of work and even more time.

Anyway, it seems fairly clear to me that the issue is bigger than any single component, but that any single relevant component can be the weakest link in the chain. It will take _a lot_ of data to convince me that a crappy board can run a good CPU up to the CPU's maximum free WHEA limit (especially since I'm staring a counter example in the face), _or_ that Vermeer CPUs with CPU dependent WHEA free limits well below 2000MHz are rare (I have access to no where near enough Vermeer parts to make such a claim). So, yeah, I _don't_ have the data yet to be confident one way or another, but this is far and away the safest assumption based on what I can gather, past experience, and the resulting balance of probabilities.



mongoled said:


> As with others, have also spent copious amount of hours making small changes here and there, but when I think ive seen pattern a subsequent reboot will "break" the pattern, so back to step one again ....


Having to do everything serially is the issue. Just no way to iterate tests and collect data fast enough with only a handful of parts at a time. Small sample size will always make results of dubious applicability to other cases as well.

If I had a hundred boards and a thousand CPUs...well, it wouldn't really be any easier, but it would certainly be faster.

I wish someone like Silicon Lottery was binning for FCLK.


----------



## Ezalor

Veii said:


> This has been so far 4 months old and on another board ~ but the logic remains identical
> tRRD bump, does a lot ~ stability wise, and lower primaries even with something for example like this currently benching thing


----------



## Ezalor

I have no idea why the page wont allow me to post the text that is to be in the post above, but here it is:



Hello Veii

Just wanted you to know that your screenshot above helped me solve a big problem.

I wrote in this tread a couple of days asking for help regarding that my 5950x only produced half of expected memory write speed, (29000 instead of 58000), and i was worried that my 5950x was faulty.

But then i saw your screenshot above and noticed that it is the same memory that i have, FlareX, (although i run 4x8), so i copied all your timings exept for voltages, RTT and DrvStr, and voila, *i now have full writespeed again*.

Something in my own timings was hence bad enough to get the processor to act like it was totally broken.

I will sooner or later proudce a zentimings of my old settings side by side with yours and post here, it would be really interesting to know what was so wrong with it.
Thanks again!


----------



## adversary

Veii said:


> double-post bug, please ignore



I have alert, 4 hours ago, that you quoted my post in this thread, but I can't find it. Did you deleted your post by mistake?


----------



## craxton

hazium233 said:


> The voltage settings were likely crap,





mongoled said:


> Damn, was never aware they moderated their forums in such a way!
> 
> That is not what I would have expected, provided the information was being put across in a constructive non volatile manner.


yea, idk i never state anything out the way, or even link to anywhere..
mostly ask a question to which im told HEY OP your posts been deleted.

i may be in the wrong place posting in r/AMD or whatever but none the less, 
they never send me to the right spot to post.



Veii said:


> that scalper cpu
> I wish you'd have that CPU SCU number noted down
> Revision and fab number
> If it is BG 20xx or 21xx, overall the batch number
> But dont tell the middle part of the serial number, only the last part of it


i have the box in the closet, would this info but listed on there???
if my pics had been backed up......wait, i think i sent pics to the seller,
for a "in case situation" where i needed to send it back, since they live 
about 30 minutes from me anyhow


HMMM so i ran prime last night, and this is the log file, 
to which i woke with a HARD LOCKED pc, and WHEA 20
im assuming one core is to blame but, if it truly took prime to make it happen, 
then idk if ill even be using the machine harder than this.

anyhow here is the log
can someone clarify, prime doesnt end on its own????
i changed a little bit of curve to such i thought i could get away with it....

i suppose not. just have to swap back i suppose...sigh -20 all core +one step above 50mv
grr.... (MSI STEPPING)



Spoiler



[Wed May 19 00:52:53 2021]
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## craxton

hazium233 said:


> Thanks. Yes, this is B550 Gaming Edge Wifi, it was produced in Sept of last year.
> 
> No this isn't Samsung E-die, it is dual rank Micron 8Gb Rev E in the 3200 16-18-18 bin. Obviously I haven't put in the work yet, but usually it should do any frequency, just the timings won't be amazing.
> 
> On the desk are 2x8 Micron 8Gb Rev D, 2x8 Micron 8Gb Rev E, and then the four Samsung 8Gb B-die sticks. Really I always intended to just run the B-die, but I saw this open box 2x16GB Rev E and bought it, heh.
> 
> If I can't get 4x8 mixed B-die to work I will just fall back on the E. Both the Trident Z and Flare X are A0 for whatever that is worth for me.


im to lazy to pull my box out the closet to check the date it was made, 
not that im aware its on there let alone


Spoiler



im up only to play Days gone on pc for the first time
downloaded a cracked version from igg.... worked fine so far...



anyhow .161 bios for b550 gaming edge wifi, stated already that the TXT file is missing, 
mine has one from the latest bios to which, .161 flashed just fine. 
(comments are open so that if someone downloads and magically some kinda 
virus or b.s. happened to get inside they can state just that) but
theres not lmao

im running 4 bdie sticks are well. all are the same manu, and model, only one 2x8 set was
made earlier bought earlier, and the other well obviously later timed. tRFC, and two other timings are different 
says aida, and a few other ram readers...but none the less i got em working together nicely enough...


----------



## craxton

Veii said:


> Haha, you messed up big times


yes, i sure did, so much in fact it took two installs for me not to mess up again..
(will setting 5000mhz allow the machine to boost that much higher?) 
or will it still only limit to what pbo tells it too by default? 



Veii said:


> QuickCPU , the tool you mean - has a button that pushes everything to 550mhz state


yes, about to redownload now and run on another install im willing to test with 
as well, before i even looked i was like HEY A BUTTON....typical man syndrome am i right ???
im unsure i used the 550mhz button tho, just the unhide all with apply while looking at the power 
options inside windows come to life like i had never knew existed. 

(to those reading, export your stuff first (somewhere safe on another drive to the cloud lol)



Veii said:


> Yea you need to hover over some buttons and read what they do


one doesn't actually have to hover, if you click it tells you near the bottom what it is and does
thats when i started putting 5000mhz in and noticed no change then i erased it
and rebooted, and it was either that or where i tried to import a different registry
from a new install that did the trick. 
it failed, but im fairly certain it was removing 5000mhz hitting apply and rebooting....
you state OCN is where this was obtained from, this site has LOADS OF GOODIES 
that one just doesn't know about, until someone mentions it...




Veii said:


> It will be figured out , so far i don't own any NVMe to figure that part out


i dont doubt you at all, if i could, id but a 250gb and have it shipped to you 


Spoiler



may contact within a few days for a shipping po box of some sort? wont be anything 
expensive but, will be an NVME none the less.





Veii said:


> RTL 2.5Gbit will crash itself without having anything plugged into it


ive yet to notice or see where it states any crashing. 90% of what windows screams about is DCOM 
DCOM HEY DCOM IS blah blah...


----------



## hazium233

I didn't get a lot accomplished, and wasted some time trying to see if tRCDRD 18t worked at 3600, which had a low probability anyway. Although maybe with cheating tRC and tFAW high.

I made an edit of 1usmus v3 with 200% and only 5cycle and assumed I would switch to either 400% or 10cycle, or just run anta extreme afterwords but fell asleep. Ran y cruncher "memtest" edited config for an hour because I thought timings were probably ok and I wanted to see voltage. AIDA had one anomaly, and one maybe. With hwinfo going, latency deviation was 0.3ns over four or five runs. With it off though it was only 0.1ns But on the last run with it off, Write changed (cache?). All of the ones with hwinfo going were also 28799.




Spoiler















The TM5 error with tRCDRD 18t was 6 spam at the beginning, but that is the first test anyway.

I skipped my normal routine of finding out which dimm is the best, I might try that today so they can go in the correct slots.

I am more interested in seeing what voltages I really need for 1800+ fabric. Is it wise to test PBO off, then adjust curve later, or will that result in wrong SOC, VDDP, VDDG?


----------



## hazium233

Blameless said:


> As observed, everything is either 1:1:1 in sync, or UCLK is half memclock.


You can do FCLK > MCLK==UCLK, just not the other way around where FCLK is lower. I had taken a screenshot of FCLK 1900 with MCLK=UCLK= 1600 in this post. If you are on single CCD and have really low ram speed, doing this can be beneficial, I think 3200MT/s is about a wash with typical max FCLK.




craxton said:


> anyhow .161 bios for b550 gaming edge wifi, stated already that the TXT file is missing,
> mine has one from the latest bios to which, .161 flashed just fine.


Thanks for posting, I just noticed I must have downloaded 1.61 while it was up on the website since it is already in my bioses folder. 

I am going to see if I can make some more progress on 1.63 before flashing back.


----------



## craxton

hazium233 said:


> I must have downloaded 1.61 while it was up on the website since it is already in my bioses folder.


best hold onto it then lol, i may try again to get 4000 working later today...
but that new setting inside the bios, well it did some auto things last time that made 
the mouse feel slow, while the desktop seemed fine, was like link speeds were super slow...


----------



## craxton

Veii said:


> If it is BG 20xx or 21xx, overall the batch number


as it stands i dont have this info backed up, not even on ebay to the seller.
but when im off work later, ill tear down and find out.
least i can do is find out, maybe this will tell a little better info
on "possible better" chips or not...

(Edit<BG 20XX>) 
Found my backups for Google photos.. glad I have that subscription now...


----------



## mongoled

PJVol said:


> 0x01D0h and 0x01D8





PJVol said:


> Sorry, was in hurry when answering
> I mean debug tool in ZenTimings, scroll down to SMU power metrics table. Search for those offsets. On clicking "debug" button you can see their current value as soon as pm table refreshes.


Dont see these offsets in the "SMU Power Table"

Would that mean that "DF States" do not exist in the BIOS even though the option has been unhidden ?



Spoiler






Code:


ZenTimings 1.2.3.201 Debug Report

######################################################
System Info
######################################################
OS: Microsoft Windows 10 Pro
CpuName: AMD Ryzen 5 5600X 6-Core Processor
CodeName: Vermeer
CpuId: 00A20F10
Model: 33
ExtendedModel: 32
PackageType: 2
FusedCoreCount: 6
PhysicalCoreCount: 8
NodesPerProcessor: 1
Threads: 12
SMT: True
CCDCount: 1
CCXCount: 1
NumCoresInCCX: 6
MbVendor: Micro-Star International Co., Ltd.
MbName: MEG X570 UNIFY (MS-7C35)
BiosVersion: A.93
SmuVersion: 56.50.0
SmuTableVersion: 00380905
PatchLevel: 0A201009

######################################################
Memory Modules
######################################################
P0 CHANNEL A | DIMM 0
-- Slot: A1
-- Single Rank
-- DCT Offset: 0x0
-- Manufacturer: Unknown
-- 4400 C19 Series 8GB 4133MHz

P0 CHANNEL A | DIMM 1
-- Slot: A2
-- Single Rank
-- DCT Offset: 0x0
-- Manufacturer: Unknown
-- 4400 C19 Series 8GB 4133MHz

P0 CHANNEL B | DIMM 0
-- Slot: B1
-- Single Rank
-- DCT Offset: 0x1
-- Manufacturer: Unknown
-- 4400 C19 Series 8GB 4133MHz

P0 CHANNEL B | DIMM 1
-- Slot: B2
-- Single Rank
-- DCT Offset: 0x1
-- Manufacturer: Unknown
-- 4400 C19 Series 8GB 4133MHz

######################################################
Memory Channels Info
######################################################
Channel0: True
-- UMC Registers
   0x00050000: 0x00000001
   0x00050004: 0x00000000
   0x00050008: 0x00000201
   0x0005000C: 0x00000000
   0x00050010: 0x00000000
   0x00050014: 0x00000000
   0x00050018: 0x00000000
   0x0005001C: 0x00000000
   0x00050020: 0x03FFFDFE
   0x00050024: 0x03FFFDFE
   0x00050028: 0x00000000
   0x0005002C: 0x00000000
   0x00050030: 0x00150608
   0x00050034: 0x00150608
   0x00050038: 0x00000000
   0x0005003C: 0x00000000
   0x00050040: 0x060C98BA
   0x00050044: 0x060C98BA
   0x00050048: 0x00000000
   0x0005004C: 0x00000000
   0x00050050: 0x87654321
   0x00050054: 0xA9876543
   0x00050058: 0x87654321
   0x0005005C: 0xA9876543
   0x00050060: 0x00000000
   0x00050064: 0x00000000
   0x00050068: 0x00000000
   0x0005006C: 0x00000000
   0x00050070: 0x00000000
   0x00050074: 0x00000000
   0x00050078: 0x00000000
   0x0005007C: 0x00000000
   0x00050080: 0x00000000
   0x00050084: 0x00000000
   0x00050088: 0x00000000
   0x0005008C: 0x00000000
   0x00050090: 0x00000000
   0x00050094: 0x00000000
   0x00050098: 0x00000000
   0x0005009C: 0x00000000
   0x000500A0: 0x36163616
   0x000500A4: 0x36163616
   0x000500A8: 0x36163616
   0x000500AC: 0x36163616
   0x000500B0: 0x00000000
   0x000500B4: 0x36163616
   0x000500B8: 0x36163616
   0x000500BC: 0x36163616
   0x000500C0: 0x36163616
   0x000500C4: 0x00000000
   0x000500C8: 0x04444001
   0x000500CC: 0x08888001
   0x000500D0: 0x111107F1
   0x000500D4: 0x22220001
   0x000500D8: 0x00000000
   0x000500DC: 0x00000000
   0x000500E0: 0x00000000
   0x000500E4: 0x00000000
   0x000500E8: 0x03FFFC00
   0x000500EC: 0x03FFFC01
   0x000500F0: 0x00000401
   0x000500F4: 0x00040001
   0x000500F8: 0x00000000
   0x000500FC: 0x00000000
   0x00050100: 0x80000200
   0x00050104: 0xB040808B
   0x00050108: 0xC4403F61
   0x0005010C: 0x040000D8
   0x00050110: 0x00D09820
   0x00050114: 0x20013000
   0x00050118: 0x00000047
   0x0005011C: 0x00000000
   0x00050120: 0x00000000
   0x00050124: 0xA100480A
   0x00050128: 0x00000000
   0x0005012C: 0x01100468
   0x00050130: 0x10000000
   0x00050134: 0x00000000
   0x00050138: 0x0740C0C0
   0x0005013C: 0x00000000
   0x00050140: 0x00000000
   0x00050144: 0x000F1101
   0x00050148: 0xDA7A5C11
   0x0005014C: 0x00000000
   0x00050150: 0x02000F00
   0x00050154: 0x00280081
   0x00050158: 0x60108000
   0x0005015C: 0x00000000
   0x00050160: 0xC00A0000
   0x00050164: 0x00000000
   0x00050168: 0x00002100
   0x0005016C: 0x00000000
   0x00050170: 0x00000000
   0x00050174: 0x00000000
   0x00050178: 0x00000000
   0x0005017C: 0x00000000
   0x00050180: 0x00000000
   0x00050184: 0x00000000
   0x00050188: 0x00000000
   0x0005018C: 0x00000000
   0x00050190: 0x00000000
   0x00050194: 0x00000000
   0x00050198: 0x00000000
   0x0005019C: 0x00000000
   0x000501A0: 0x00000000
   0x000501A4: 0x00000000
   0x000501A8: 0x00000000
   0x000501AC: 0x00000000
   0x000501B0: 0x00000202
   0x000501B4: 0x00000000
   0x000501B8: 0x00000101
   0x000501BC: 0x00000000
   0x000501C0: 0x00000000
   0x000501C4: 0x00000000
   0x000501C8: 0x00000000
   0x000501CC: 0x00000000
   0x000501D0: 0x00000000
   0x000501D4: 0x00000000
   0x000501D8: 0x00000000
   0x000501DC: 0x00000000
   0x000501E0: 0x00000117
   0x000501E4: 0x00000000
   0x000501E8: 0x00000000
   0x000501EC: 0x00000000
   0x000501F0: 0x00000000
   0x000501F4: 0x00000000
   0x000501F8: 0x00000000
   0x000501FC: 0x00000000
   0x00050200: 0x0000153E
   0x00050204: 0x10102010
   0x00050208: 0x00100030
   0x0005020C: 0x06000804
   0x00050210: 0x00000010
   0x00050214: 0x000E0410
   0x00050218: 0x0000000C
   0x0005021C: 0x00000000
   0x00050220: 0x45010404
   0x00050224: 0x45010606
   0x00050228: 0x00000B03
   0x0005022C: 0x0FD20080
   0x00050230: 0x00003EF4
   0x00050234: 0x1F151F08
   0x00050238: 0x040002E8
   0x0005023C: 0x24002024
   0x00050240: 0x00000000
   0x00050244: 0x7FFE0010
   0x00050248: 0x00000000
   0x0005024C: 0x00000000
   0x00050250: 0x00F20000
   0x00050254: 0x0B04000D
   0x00050258: 0x021A0B0B
   0x0005025C: 0x22002A2A
   0x00050260: 0x2106B120
   0x00050264: 0x2106B120
   0x00050268: 0x00000000
   0x0005026C: 0x00000000
   0x00050270: 0x00000000
   0x00050274: 0x00000000
   0x00050278: 0x80000000
   0x0005027C: 0x80000000
   0x00050280: 0x00007070
   0x00050284: 0x00000120
   0x00050288: 0x00000552
   0x0005028C: 0x18002980
   0x00050290: 0x00000000
   0x00050294: 0x00000000
   0x00050298: 0x00000000
   0x0005029C: 0x00000000
   0x000502A0: 0x00000000
   0x000502A4: 0x00000000
   0x000502A8: 0x00000000
   0x000502AC: 0x00000000
   0x000502B0: 0x00000000
   0x000502B4: 0x00000000
   0x000502B8: 0x00000000
   0x000502BC: 0x00000000
   0x000502C0: 0x00000000
   0x000502C4: 0x00000000
   0x000502C8: 0x00000000
   0x000502CC: 0x00000000
   0x000502D0: 0x00000000
   0x000502D4: 0x00000000
   0x000502D8: 0x00000000
   0x000502DC: 0x00000000
   0x000502E0: 0x00000000
   0x000502E4: 0x00000000
   0x000502E8: 0x00000000
   0x000502EC: 0x00000000
   0x000502F0: 0x00000000
   0x000502F4: 0x00000000
   0x000502F8: 0x00000000
   0x000502FC: 0x00000000
   0x00050300: 0x00000100
Channel1: True
-- UMC Registers
   0x00150000: 0x00000001
   0x00150004: 0x00000000
   0x00150008: 0x00000201
   0x0015000C: 0x00000000
   0x00150010: 0x00000000
   0x00150014: 0x00000000
   0x00150018: 0x00000000
   0x0015001C: 0x00000000
   0x00150020: 0x03FFFDFE
   0x00150024: 0x03FFFDFE
   0x00150028: 0x00000000
   0x0015002C: 0x00000000
   0x00150030: 0x00150608
   0x00150034: 0x00150608
   0x00150038: 0x00000000
   0x0015003C: 0x00000000
   0x00150040: 0x060C98BA
   0x00150044: 0x060C98BA
   0x00150048: 0x00000000
   0x0015004C: 0x00000000
   0x00150050: 0x87654321
   0x00150054: 0xA9876543
   0x00150058: 0x87654321
   0x0015005C: 0xA9876543
   0x00150060: 0x00000000
   0x00150064: 0x00000000
   0x00150068: 0x00000000
   0x0015006C: 0x00000000
   0x00150070: 0x00000000
   0x00150074: 0x00000000
   0x00150078: 0x00000000
   0x0015007C: 0x00000000
   0x00150080: 0x00000000
   0x00150084: 0x00000000
   0x00150088: 0x00000000
   0x0015008C: 0x00000000
   0x00150090: 0x00000000
   0x00150094: 0x00000000
   0x00150098: 0x00000000
   0x0015009C: 0x00000000
   0x001500A0: 0x36163616
   0x001500A4: 0x36163616
   0x001500A8: 0x36163616
   0x001500AC: 0x36163616
   0x001500B0: 0x00000000
   0x001500B4: 0x36163616
   0x001500B8: 0x36163616
   0x001500BC: 0x36163616
   0x001500C0: 0x36163616
   0x001500C4: 0x00000000
   0x001500C8: 0x04444001
   0x001500CC: 0x08888001
   0x001500D0: 0x111107F1
   0x001500D4: 0x22220001
   0x001500D8: 0x00000000
   0x001500DC: 0x00000000
   0x001500E0: 0x00000000
   0x001500E4: 0x00000000
   0x001500E8: 0x03FFFC00
   0x001500EC: 0x03FFFC01
   0x001500F0: 0x00000401
   0x001500F4: 0x00040001
   0x001500F8: 0x00000000
   0x001500FC: 0x00000000
   0x00150100: 0x80000200
   0x00150104: 0xB040808B
   0x00150108: 0xC4403F61
   0x0015010C: 0x040000D8
   0x00150110: 0x00D09820
   0x00150114: 0x20013000
   0x00150118: 0x00000047
   0x0015011C: 0x00000000
   0x00150120: 0x00000000
   0x00150124: 0xA100480A
   0x00150128: 0x00000000
   0x0015012C: 0x01100468
   0x00150130: 0x10000000
   0x00150134: 0x00000000
   0x00150138: 0x0740C0C0
   0x0015013C: 0x00000000
   0x00150140: 0x00000000
   0x00150144: 0x000F1101
   0x00150148: 0xDA7A5C11
   0x0015014C: 0x00000000
   0x00150150: 0x02000F00
   0x00150154: 0x00280081
   0x00150158: 0x60108000
   0x0015015C: 0x00000000
   0x00150160: 0xC00A0000
   0x00150164: 0x00000000
   0x00150168: 0x00002100
   0x0015016C: 0x00000000
   0x00150170: 0x00000000
   0x00150174: 0x00000000
   0x00150178: 0x00000000
   0x0015017C: 0x00000000
   0x00150180: 0x00000000
   0x00150184: 0x00000000
   0x00150188: 0x00000000
   0x0015018C: 0x00000000
   0x00150190: 0x00000000
   0x00150194: 0x00000000
   0x00150198: 0x00000000
   0x0015019C: 0x00000000
   0x001501A0: 0x00000000
   0x001501A4: 0x00000000
   0x001501A8: 0x00000000
   0x001501AC: 0x00000000
   0x001501B0: 0x00000202
   0x001501B4: 0x00000000
   0x001501B8: 0x00000101
   0x001501BC: 0x00000000
   0x001501C0: 0x00000000
   0x001501C4: 0x00000000
   0x001501C8: 0x00000000
   0x001501CC: 0x00000000
   0x001501D0: 0x00000000
   0x001501D4: 0x00000000
   0x001501D8: 0x00000000
   0x001501DC: 0x00000000
   0x001501E0: 0x00000117
   0x001501E4: 0x00000000
   0x001501E8: 0x00000000
   0x001501EC: 0x00000000
   0x001501F0: 0x00000000
   0x001501F4: 0x00000000
   0x001501F8: 0x00000000
   0x001501FC: 0x00000000
   0x00150200: 0x0000153E
   0x00150204: 0x10102010
   0x00150208: 0x00100030
   0x0015020C: 0x06000804
   0x00150210: 0x00000010
   0x00150214: 0x000E0410
   0x00150218: 0x0000000C
   0x0015021C: 0x00000000
   0x00150220: 0x45010404
   0x00150224: 0x45010606
   0x00150228: 0x00000B03
   0x0015022C: 0x0FD20080
   0x00150230: 0x00003EF4
   0x00150234: 0x1F151F08
   0x00150238: 0x040002E8
   0x0015023C: 0x24002024
   0x00150240: 0x00000000
   0x00150244: 0x7FFE0010
   0x00150248: 0x00000000
   0x0015024C: 0x00000000
   0x00150250: 0x00F20000
   0x00150254: 0x0B04000D
   0x00150258: 0x021A0B0B
   0x0015025C: 0x22002A2A
   0x00150260: 0x2106B120
   0x00150264: 0x2106B120
   0x00150268: 0x00000000
   0x0015026C: 0x00000000
   0x00150270: 0x00000000
   0x00150274: 0x00000000
   0x00150278: 0x80000000
   0x0015027C: 0x80000000
   0x00150280: 0x00007070
   0x00150284: 0x00000120
   0x00150288: 0x00000552
   0x0015028C: 0x18002980
   0x00150290: 0x00000000
   0x00150294: 0x00000000
   0x00150298: 0x00000000
   0x0015029C: 0x00000000
   0x001502A0: 0x00000000
   0x001502A4: 0x00000000
   0x001502A8: 0x00000000
   0x001502AC: 0x00000000
   0x001502B0: 0x00000000
   0x001502B4: 0x00000000
   0x001502B8: 0x00000000
   0x001502BC: 0x00000000
   0x001502C0: 0x00000000
   0x001502C4: 0x00000000
   0x001502C8: 0x00000000
   0x001502CC: 0x00000000
   0x001502D0: 0x00000000
   0x001502D4: 0x00000000
   0x001502D8: 0x00000000
   0x001502DC: 0x00000000
   0x001502E0: 0x00000000
   0x001502E4: 0x00000000
   0x001502E8: 0x00000000
   0x001502EC: 0x00000000
   0x001502F0: 0x00000000
   0x001502F4: 0x00000000
   0x001502F8: 0x00000000
   0x001502FC: 0x00000000
   0x00150300: 0x00000100
Channel2: False
Channel3: False
Channel4: False
Channel5: False
Channel6: False
Channel7: False

######################################################
Memory Config
######################################################
Frequency: 4133.333
Ratio: 20.66667
TotalCapacity: 32GB
BGS: Disabled
BGSAlt: Enabled
GDM: Disabled
PowerDown: Disabled
Cmd2T: 2T
CL: 16
RCDWR: 16
RCDRD: 16
RP: 16
RAS: 32
RC: 48
RRDS: 4
RRDL: 8
FAW: 16
WTRS: 4
WTRL: 14
WR: 12
RDRDSCL: 5
WRWRSCL: 5
CWL: 16
RTP: 6
RDWR: 11
WRRD: 3
RDRDSC: 1
RDRDSD: 4
RDRDDD: 4
WRWRSC: 1
WRWRSD: 6
WRWRDD: 6
TRCPAGE: 0
CKE: 11
STAG: 242
MOD: 31
MODPDA: 31
MRD: 8
MRDPDA: 21
RFC: 288
RFCns: 139.3548
RFC2: 214
RFC4: 132
REFI: 16116
REFIns: 7798.065
XP: 13
PHYWRD: 2
PHYWRL: 11
PHYRDL: 26

######################################################
BIOS: Memory Controller Config
######################################################
Index 000: 00 (0)
Index 001: 00 (0)
Index 002: 00 (0)
Index 003: 00 (0)
Index 004: 00 (0)
Index 005: 00 (0)
Index 006: 01 (1)
Index 007: 01 (1)
Index 008: 00 (0)
Index 009: 00 (0)
Index 010: 00 (0)
Index 011: 00 (0)
Index 012: 00 (0)
Index 013: 00 (0)
Index 014: 00 (0)
Index 015: 00 (0)
Index 016: 00 (0)
Index 017: 00 (0)
Index 018: 00 (0)
Index 019: 00 (0)
Index 020: 13 (19)
Index 021: 08 (8)
Index 022: 10 (16)
Index 023: 10 (16)
Index 024: 10 (16)
Index 025: 20 (32)
Index 026: 10 (16)
Index 027: C8 (200)
Index 028: 05 (5)
Index 029: E4 (228)
Index 030: 02 (2)
Index 031: 00 (0)
Index 032: 00 (0)
Index 033: 3B (59)
Index 034: 00 (0)
Index 035: 00 (0)
Index 036: 00 (0)
Index 037: 30 (48)
Index 038: 20 (32)
Index 039: 01 (1)
Index 040: D6 (214)
Index 041: 00 (0)
Index 042: 84 (132)
Index 043: 00 (0)
Index 044: 10 (16)
Index 045: 04 (4)
Index 046: 08 (8)
Index 047: 0C (12)
Index 048: 04 (4)
Index 049: 0E (14)
Index 050: 0B (11)
Index 051: 10 (16)
Index 052: 06 (6)
Index 053: 01 (1)
Index 054: 05 (5)
Index 055: 04 (4)
Index 056: 04 (4)
Index 057: 01 (1)
Index 058: 05 (5)
Index 059: 06 (6)
Index 060: 06 (6)
Index 061: 0B (11)
Index 062: 03 (3)
Index 063: 00 (0)
Index 064: 01 (1)
Index 065: 07 (7)
Index 066: 04 (4)
Index 067: 01 (1)
Index 068: 00 (0)
Index 069: 00 (0)
Index 070: 0E (14)
Index 071: 06 (6)
Index 072: 00 (0)
Index 073: 00 (0)
Index 074: 00 (0)
Index 075: 00 (0)
Index 076: 00 (0)
Index 077: 00 (0)
Index 078: 01 (1)
Index 079: 00 (0)
Index 080: 00 (0)
Index 081: 00 (0)
Index 082: 00 (0)
Index 083: 00 (0)
Index 084: 06 (6)
Index 085: 00 (0)
Index 086: 04 (4)
Index 087: 04 (4)
Index 088: 12 (18)
Index 089: 0F (15)
Index 090: 1F (31)
Index 091: 1F (31)
Index 092: 1F (31)
Index 093: 00 (0)
Index 094: 00 (0)
Index 095: 00 (0)
Index 096: 01 (1)
Index 097: 00 (0)
Index 098: 00 (0)
Index 099: 00 (0)
Index 100: 01 (1)
Index 101: 00 (0)
Index 102: 00 (0)
Index 103: 00 (0)
Index 104: 00 (0)
Index 105: 01 (1)
Index 106: 00 (0)
Index 107: 00 (0)
Index 108: 8E (142)
Index 109: 00 (0)
Index 110: 00 (0)
Index 111: 00 (0)
Index 112: 5F (95)
Index 113: 00 (0)
Index 114: 00 (0)
Index 115: 00 (0)
Index 116: 8C (140)
Index 117: 00 (0)
Index 118: 00 (0)
Index 119: 00 (0)
Index 120: 00 (0)
Index 121: 00 (0)
Index 122: 00 (0)
Index 123: 00 (0)
Index 124: 02 (2)
Index 125: 02 (2)
Index 126: 00 (0)
Index 127: 00 (0)
Index 128: 00 (0)
Index 129: 00 (0)
Index 130: 00 (0)
Index 131: 00 (0)
Index 132: 00 (0)
Index 133: 00 (0)
Index 134: 00 (0)
Index 135: 00 (0)
Index 136: 00 (0)
Index 137: 00 (0)
Index 138: 00 (0)
Index 139: 00 (0)
Index 140: 00 (0)
Index 141: 00 (0)
Index 142: 00 (0)
Index 143: 00 (0)
Index 144: 00 (0)
Index 145: 00 (0)
Index 146: 00 (0)
Index 147: 00 (0)
Index 148: 00 (0)
Index 149: 00 (0)
Index 150: 00 (0)
Index 151: 00 (0)
Index 152: 00 (0)
Index 153: 00 (0)
Index 154: 00 (0)
Index 155: 00 (0)
Index 156: 00 (0)
Index 157: 00 (0)
Index 158: 00 (0)
Index 159: 00 (0)
Index 160: 00 (0)
Index 161: 00 (0)
Index 162: 00 (0)
Index 163: 00 (0)
Index 164: 00 (0)
Index 165: 00 (0)
Index 166: 00 (0)
Index 167: 0E (14)
Index 168: 06 (6)
Index 169: 00 (0)
Index 170: 00 (0)
Index 171: 00 (0)
Index 172: 00 (0)
Index 173: 00 (0)
Index 174: 00 (0)
Index 175: 00 (0)
Index 176: 00 (0)
Index 177: 00 (0)
Index 178: 00 (0)
Index 179: 00 (0)
Index 180: 00 (0)
Index 181: 00 (0)
Index 182: 00 (0)
Index 183: 00 (0)
Index 184: 00 (0)
Index 185: 00 (0)
Index 186: 00 (0)
Index 187: 00 (0)
Index 188: 00 (0)
Index 189: 00 (0)
Index 190: 00 (0)
Index 191: 00 (0)
Index 192: 00 (0)
Index 193: 00 (0)
Index 194: 00 (0)
Index 195: 00 (0)
Index 196: 00 (0)
Index 197: 00 (0)
Index 198: 00 (0)
Index 199: 00 (0)

######################################################
SMU: Power Table
######################################################
Offset 000: 142.00000000
Offset 004: 62.46069000
Offset 008: 95.00000000
Offset 00C: 22.58803000
Offset 010: 95.00000000
Offset 014: 51.18944000
Offset 018: 648.47680000
Offset 01C: 567.55500000
Offset 020: 140.00000000
Offset 024: 122.39570000
Offset 028: 1.44508400
Offset 02C: 1.42820000
Offset 030: 3.52042200
Offset 034: 62.45097000
Offset 038: 0.00000000
Offset 03C: 21.26184000
Offset 040: 0.00000000
Offset 044: 51.18891000
Offset 048: 0.00000000
Offset 04C: 576.22460000
Offset 050: 0.00000000
Offset 054: 122.39570000
Offset 058: 0.00000000
Offset 05C: 1.42820000
Offset 060: 31.95447000
Offset 064: 18.16309000
Offset 068: 10.38764000
Offset 06C: 0.94545940
Offset 070: 1.00000000
Offset 074: 62.45097000
Offset 078: 4.82569400
Offset 07C: 4.84999800
Offset 080: 4.84999800
Offset 084: 4.84999800
Offset 088: 4.84999800
Offset 08C: 4.84999800
Offset 090: 4.82569400
Offset 094: 4.84999800
Offset 098: 1.44508600
Offset 09C: 1.44994000
Offset 0A0: 1.42820000
Offset 0A4: 1.41540900
Offset 0A8: 22.58177000
Offset 0AC: 31.95447000
Offset 0B0: 1.28750600
Offset 0B4: 1.28750600
Offset 0B8: 14.10718000
Offset 0BC: 18.16309000
Offset 0C0: 2067.00000000
Offset 0C4: 2066.68500000
Offset 0C8: 2067.00000000
Offset 0CC: 2067.00000000
Offset 0D0: 0.00000000
Offset 0D4: 0.42396570
Offset 0D8: 0.00000000
Offset 0DC: 1.15810200
Offset 0E0: 0.00000000
Offset 0E4: 0.00720449
Offset 0E8: 0.00000000
Offset 0EC: 0.00000000
Offset 0F0: 3.88605000
Offset 0F4: 0.00000000
Offset 0F8: 0.00000000
Offset 0FC: 0.00000000
Offset 100: 0.23933890
Offset 104: 0.24329270
Offset 108: 0.00476843
Offset 10C: 0.00476843
Offset 110: 0.22521350
Offset 114: 0.05516799
Offset 118: 100.00000000
Offset 11C: 0.00000000
Offset 120: 0.00000000
Offset 124: 0.00000000
Offset 128: 2067.00000000
Offset 12C: 0.00000000
Offset 130: 0.00000000
Offset 134: 0.00000000
Offset 138: 2067.00000000
Offset 13C: 0.00000000
Offset 140: 0.00000000
Offset 144: 0.00000000
Offset 148: 2067.00000000
Offset 14C: 0.00000000
Offset 150: 0.00000000
Offset 154: 0.00000000
Offset 158: 0.00000000
Offset 15C: 0.00000000
Offset 160: 0.00000000
Offset 164: 0.00000000
Offset 168: 1.00000000
Offset 16C: 0.00000000
Offset 170: 0.00000000
Offset 174: 0.00000000
Offset 178: 592.59260000
Offset 17C: 301.88680000
Offset 180: 31.25000000
Offset 184: 31.81939000
Offset 188: 1.00000000
Offset 18C: 0.00000000
Offset 190: 0.00000000
Offset 194: 0.00000000
Offset 198: 592.59260000
Offset 19C: 301.88680000
Offset 1A0: 0.00000000
Offset 1A4: 0.00000000
Offset 1A8: 1.00000000
Offset 1AC: 0.00000000
Offset 1B0: 0.00000000
Offset 1B4: 0.00000000
Offset 1B8: 592.59260000
Offset 1BC: 301.88680000
Offset 1C0: 0.00000000
Offset 1C4: 0.00000000
Offset 1C8: 1.00000000
Offset 1CC: 0.00749625
Offset 1D0: 301.88140000
Offset 1D4: 284.66360000
Offset 1D8: 592.59260000
Offset 1DC: 301.88680000
Offset 1E0: 31.25000000
Offset 1E4: 31.81939000
Offset 1E8: 10.00000000
Offset 1EC: 0.00000000
Offset 1F0: 0.00000000
Offset 1F4: 0.00000000
Offset 1F8: 0.00000000
Offset 1FC: 33.88243000
Offset 200: 6.16554000
Offset 204: 0.00000000
Offset 208: 4.87617300
Offset 20C: 0.00000000
Offset 210: 1.95142800
Offset 214: 0.94545940
Offset 218: 65.00000000
Offset 21C: 0.00000000
Offset 220: 0.95038550
Offset 224: 0.94448490
Offset 228: 1.04774500
Offset 22C: 1.03889400
Offset 230: 63.00000000
Offset 234: 1.45000000
Offset 238: 4.85000000
Offset 23C: 1.43750000
Offset 240: 37.64706000
Offset 244: 53.17647000
Offset 248: 1.81609500
Offset 24C: 4.82569400
Offset 250: 1.31581900
Offset 254: 0.00000000
Offset 258: 62.76868000
Offset 25C: 0.01378953
Offset 260: 0.00000000
Offset 264: 1.59567200
Offset 268: 0.00000000
Offset 26C: 0.00000000
Offset 270: 0.00000000
Offset 274: 5.49466500
Offset 278: 500.00000000
Offset 27C: 500.00000000
Offset 280: 500.00000000
Offset 284: 500.00000000
Offset 288: 457.14290000
Offset 28C: 457.13860000
Offset 290: 457.14290000
Offset 294: 137.82150000
Offset 298: 400.00000000
Offset 29C: 400.00000000
Offset 2A0: 0.00000000
Offset 2A4: 31.68117000
Offset 2A8: 27.51045000
Offset 2AC: 99.00000000
Offset 2B0: 3.32679800
Offset 2B4: 3.25394200
Offset 2B8: 3.06844600
Offset 2BC: 7.76701800
Offset 2C0: 0.00000000
Offset 2C4: 4.18310300
Offset 2C8: 5.61592200
Offset 2CC: 0.00000000
Offset 2D0: 1.05787800
Offset 2D4: 1.02372500
Offset 2D8: 1.08759600
Offset 2DC: 1.29951900
Offset 2E0: 0.00000000
Offset 2E4: 1.08953000
Offset 2E8: 1.30009400
Offset 2EC: 0.00000000
Offset 2F0: 38.72089000
Offset 2F4: 40.79810000
Offset 2F8: 37.98938000
Offset 2FC: 48.79335000
Offset 300: 35.09545000
Offset 304: 42.99076000
Offset 308: 43.87581000
Offset 30C: 33.61519000
Offset 310: 37.85322000
Offset 314: 45.87835000
Offset 318: 36.18983000
Offset 31C: 95.22465000
Offset 320: 0.00000000
Offset 324: 54.02625000
Offset 328: 63.77968000
Offset 32C: 0.00000000
Offset 330: 14.38626000
Offset 334: 13.94706000
Offset 338: 14.48774000
Offset 33C: 16.54154000
Offset 340: 0.00000000
Offset 344: 14.73814000
Offset 348: 16.47588000
Offset 34C: 0.00000000
Offset 350: 4.21527900
Offset 354: 4.06421500
Offset 358: 4.24965600
Offset 35C: 4.80439800
Offset 360: 0.00000000
Offset 364: 4.29283000
Offset 368: 4.82230000
Offset 36C: 0.00000000
Offset 370: 0.68956180
Offset 374: 0.54116350
Offset 378: 0.51853880
Offset 37C: 3.30652400
Offset 380: 0.00000000
Offset 384: 1.23515700
Offset 388: 2.34170200
Offset 38C: 0.00000000
Offset 390: 15.15615000
Offset 394: 12.07786000
Offset 398: 11.47926000
Offset 39C: 67.95313000
Offset 3A0: 0.00000000
Offset 3A4: 26.38848000
Offset 3A8: 48.55457000
Offset 3AC: 0.00000000
Offset 3B0: 83.14960000
Offset 3B4: 85.75970000
Offset 3B8: 85.86052000
Offset 3BC: 32.04689000
Offset 3C0: 0.00000000
Offset 3C4: 66.05212000
Offset 3C8: 51.44542000
Offset 3CC: 0.00000000
Offset 3D0: 1.69428300
Offset 3D4: 2.16244400
Offset 3D8: 2.66025500
Offset 3DC: 0.00000000
Offset 3E0: 100.00000000
Offset 3E4: 7.55937100
Offset 3E8: 0.00000000
Offset 3EC: 100.00000000
Offset 3F0: 0.00000000
Offset 3F4: 0.00000000
Offset 3F8: 0.00000000
Offset 3FC: 0.00000000
Offset 400: 0.00000000
Offset 404: 0.00000000
Offset 408: 0.00000000
Offset 40C: 0.00000000
Offset 410: 0.00000000
Offset 414: 0.00000000
Offset 418: 0.00000000
Offset 41C: 0.00000000
Offset 420: 0.00000000
Offset 424: 0.00000000
Offset 428: 0.00000000
Offset 42C: 0.00000000
Offset 430: 95.29250000
Offset 434: 95.31579000
Offset 438: 95.45224000
Offset 43C: 100.00000000
Offset 440: 0.00000000
Offset 444: 92.12400000
Offset 448: 100.00000000
Offset 44C: 0.00000000
Offset 450: 0.00000000
Offset 454: 0.00000000
Offset 458: 0.00000000
Offset 45C: 0.00000000
Offset 460: 0.00000000
Offset 464: 0.00000000
Offset 468: 0.00000000
Offset 46C: 0.00000000
Offset 470: 4.84999800
Offset 474: 4.84999800
Offset 478: 4.84999800
Offset 47C: 4.84999800
Offset 480: 4.84999800
Offset 484: 4.84999800
Offset 488: 4.84999800
Offset 48C: 4.84999800
Offset 490: 3.68126200
Offset 494: 3.68126200
Offset 498: 3.68126200
Offset 49C: 3.68126200
Offset 4A0: 0.54999540
Offset 4A4: 3.68126200
Offset 4A8: 3.68126200
Offset 4AC: 0.54999540
Offset 4B0: 0.00000000
Offset 4B4: 0.00000000
Offset 4B8: 0.00000000
Offset 4BC: 0.00000000
Offset 4C0: 0.00000000
Offset 4C4: 0.00000000
Offset 4C8: 0.00000000
Offset 4CC: 0.00000000
Offset 4D0: 36.35033000
Offset 4D4: 36.75812000
Offset 4D8: 35.87207000
Offset 4DC: 45.57172000
Offset 4E0: 254.00000000
Offset 4E4: 38.52074000
Offset 4E8: 37.74563000
Offset 4EC: 254.00000000
Offset 4F0: 0.89555230
Offset 4F4: 0.83258370
Offset 4F8: 0.53223390
Offset 4FC: 4.87906100
Offset 500: 0.00000000
Offset 504: 2.08145900
Offset 508: 4.10394800
Offset 50C: 0.00000000
Offset 510: 0.00000000
Offset 514: 0.00000000
Offset 518: 0.00000000
Offset 51C: 0.00000000
Offset 520: 0.00000000
Offset 524: 0.00000000
Offset 528: 0.00000000
Offset 52C: 0.00000000
Offset 530: 1.42827400
Offset 534: 1.78082300
Offset 538: 1.58289300
Offset 53C: 2.13307000
Offset 540: 0.00000000
Offset 544: 1.97999900
Offset 548: 2.14613800
Offset 54C: 0.00000000
Offset 550: 707.37610000
Offset 554: 621.27900000
Offset 558: 454.93460000
Offset 55C: 3828.23900000
Offset 560: 0.00000000
Offset 564: 1790.12900000
Offset 568: 3169.51300000
Offset 56C: 0.00000000
Offset 570: 257.98100000
Offset 574: 179.66070000
Offset 578: 178.25140000
Offset 57C: 194.03300000
Offset 580: 0.00000000
Offset 584: 186.49230000
Offset 588: 216.58570000
Offset 58C: 0.00000000
Offset 590: 2.86994100
Offset 594: 0.43799270
Offset 598: 36.06934000
Offset 59C: 243.27240000
Offset 5A0: 32.42197000
Offset 5A4: 4.82569400
Offset 5A8: 4.82569700
Offset 5AC: 0.00000000
Offset 5B0: 2047.00000000
Offset 5B4: 13.67166000
Offset 5B8: 0.00000000
Offset 5BC: 15.00000000
Offset 5C0: 0.34682660
Offset 5C4: 0.00000000
Offset 5C8: 0.99121090
Offset 5CC: 28.93275000
Offset 5D0: 0.00000000
Offset 5D4: 0.00000000
Offset 5D8: 0.00000000
Offset 5DC: 0.00000000
Offset 5E0: 0.00000000
Offset 5E4: 0.00000000
Offset 5E8: 0.00000000
Offset 5EC: 0.00000000
Offset 5F0: 0.00000000
Offset 5F4: 0.00000000
Offset 5F8: 0.00000000
Offset 5FC: 0.00000000
Offset 600: 0.00000000
Offset 604: 0.00000000
Offset 608: 0.00000000
Offset 60C: 0.00000000
Offset 610: 0.00000000
Offset 614: 0.00000000
Offset 618: 0.00000000
Offset 61C: 0.00000000
Offset 620: 0.00000000
Offset 624: 0.00000000
Offset 628: 0.00000000
Offset 62C: 0.00000000
Offset 630: 0.00000000
Offset 634: 0.00000000
Offset 638: 0.00000000
Offset 63C: 0.00000000
Offset 640: 0.00000000
Offset 644: 0.00000000
Offset 648: 0.00000000
Offset 64C: 0.00000000
Offset 650: 0.00000000
Offset 654: 0.00000000
Offset 658: 0.00000000
Offset 65C: 0.00000000
Offset 660: 0.00000000
Offset 664: 0.00000000
Offset 668: 0.00000000
Offset 66C: 0.00000000
Offset 670: 0.00000000
Offset 674: 0.00000000
Offset 678: 0.00000000
Offset 67C: 0.00000000
Offset 680: 0.00000000
Offset 684: 0.00000000
Offset 688: 0.00000000
Offset 68C: 0.00000000
Offset 690: 0.00000000
Offset 694: 0.00000000
Offset 698: 0.00000000
Offset 69C: 0.00000000
Offset 6A0: 0.00000000
Offset 6A4: 0.00000000
Offset 6A8: 0.00000000
Offset 6AC: 0.00000000
Offset 6B0: 0.00000000
Offset 6B4: 0.00000000
Offset 6B8: 0.00000000
Offset 6BC: 0.00000000
Offset 6C0: 0.00000000
Offset 6C4: 0.00000000
Offset 6C8: 0.00000000
Offset 6CC: 0.00000000
Offset 6D0: 0.00000000
Offset 6D4: 0.00000000
Offset 6D8: 0.00000000
Offset 6DC: 0.00000000
Offset 6E0: 0.00000000
Offset 6E4: 0.00000000
Offset 6E8: 0.00000000
Offset 6EC: 0.00000000
Offset 6F0: 0.00000000
Offset 6F4: 0.00000000
Offset 6F8: 0.00000000
Offset 6FC: 0.00000000
Offset 700: 0.00000000
Offset 704: 0.00000000
Offset 708: 0.00000000
Offset 70C: 0.00000000
Offset 710: 0.00000000
Offset 714: 0.00000000
Offset 718: 0.00000000
Offset 71C: 0.00000000
Offset 720: 0.00000000
Offset 724: 0.00000000
Offset 728: 0.00000000
Offset 72C: 0.00000000
Offset 730: 0.00000000
Offset 734: 0.00000000
Offset 738: 0.00000000
Offset 73C: 0.00000000
Offset 740: 0.00000000
Offset 744: 0.00000000
Offset 748: 0.00000000
Offset 74C: 0.00000000
Offset 750: 0.00000000
Offset 754: 0.00000000
Offset 758: 0.00000000
Offset 75C: 0.00000000
Offset 760: 0.00000000
Offset 764: 0.00000000
Offset 768: 0.00000000
Offset 76C: 0.00000000
Offset 770: 0.00000000
Offset 774: 0.00000000
Offset 778: 0.00000000
Offset 77C: 0.00000000
Offset 780: 0.00000000
Offset 784: 0.00000000
Offset 788: 0.00000000
Offset 78C: 0.00000000
Offset 790: 0.00000000
Offset 794: 0.00000000
Offset 798: 0.00000000
Offset 79C: 0.00000000
Offset 7A0: 0.00000000
Offset 7A4: 0.00000000
Offset 7A8: 0.00000000
Offset 7AC: 0.00000000
Offset 7B0: 0.00000000
Offset 7B4: 0.00000000
Offset 7B8: 0.00000000
Offset 7BC: 0.00000000
Offset 7C0: 0.00000000
Offset 7C4: 0.00000000
Offset 7C8: 0.00000000
Offset 7CC: 0.00000000
Offset 7D0: 0.00000000
Offset 7D4: 0.00000000
Offset 7D8: 0.00000000
Offset 7DC: 0.00000000
Offset 7E0: 0.00000000

######################################################
SMU: Power Table Detected Values
######################################################
SmuType: TYPE_CPU3
TableVersion: 00380905
ConfiguredClockSpeed: 4133.333
MemRatio: 20.66667
FCLK: 2067
MCLK: 2067
UCLK: 2067
VDDCR_SOC: 1.287506
CLDO_VDDP: 0.9444849
CLDO_VDDG_IOD: 1.047745
CLDO_VDDG_CCD: 1.038894

######################################################
WMI: AMD_ACPI
######################################################
OK

######################################################
WMI: Instance Name
######################################################
ACPI\PNP0C14\AOD_0

######################################################
WMI: Bios Functions 1
######################################################
Get APCB Config: 00010001
Get memory voltages: 00010002
Set memory clock frequency: 00020001
Set Tcl: 00020002
Set Trcdrd: 00020003
Set Trcdwr: 00020004
Set Tras: 00020005
Set Trp: 00020006
Set ProcODT: 00020007
Set Trcpage: 00020008
Set Trc: 00020009
Set Trfc: 0002000A
Set Trfc2: 0002000B
Set Trfc4: 0002000C
Set Tfaw: 0002000D
Set TrrdS: 0002000E
Set TrrdL: 0002000F
Set Twr: 00020010
Set TwtrS: 00020011
Set TwtrL: 00020012
Set TCke: 00020013
Set Tcwl: 00020014
Set Trtp: 00020015
Set TrdrdSc: 00020016
Set TrdrdScL: 00020017
Set TrdrdSd: 00020018
Set TrdrdDd: 00020019
Set TwrwrSc: 0002001A
Set TwrwrScL: 0002001B
Set TwrwrSd: 0002001C
Set TwrwrDd: 0002001D
Set Trdwr: 0002001E
Set Twrrd: 0002001F
Set GearDownEn: 00020020
Set Cmd2t: 00020021
Set RttNom: 00020022
Set RttWR: 00020023
Set RttPark: 00020024
Set PowerDownEn: 00020025
Set SMT EN: 00020026
Software Downcore Config: 00020027
Set EDC Throttler Control: 00020028
Set AddrCmdSetup: 00020029
Set CsOdtSetup: 0002002A
Set CkeSetup: 0002002B
Set CadBusClkDrvStren: 0002002C
Set CadBusAddrCmdDrvStren: 0002002D
Set CadBusCsOdtCmdDrvStren: 0002002E
Set CadBusCkeDrvStren: 0002002F
Set CLDO_VDDP: 00020030
Set Interleave Mode: 00020031
Set Interleave Size: 00020032
Set FCLK OC Mode: 00020033
Set SOC VID: 00020034
Set FCLK Frequency: 00020035
Set CCLK Fmax: 00020036
Set GFXCLK Fmax: 00020037
Set CLDO_VDDG: 00020038
Get ECO Mode: 00020039
Set ECO Mode: 0002003A
Set VDDIO: 00030001
Set VTT: 00030002
Command Buffer Start: 00040001
Command Buffer End: 00040002

######################################################
WMI: Bios Functions 2
######################################################
Set PPT Limit: 00050001
Set TDC Limit: 00050002
Set EDC Limit: 00050003
Set Scalar: 00050004
Set DRAM Map Inversion: 00050005
Set Curve Optimizer: 0005000A
Set IOD VDDG: 0005000B
Set Soc TDC Limit: 0005000C
Set Soc EDC Limit: 0005000D
Set Dram Latency Enhance: 0005000E
Get Dram Latency Enhance: 0005000F

######################################################
SVI2: PCI Range
######################################################
0x0005A000: 0x00000006
0x0005A004: 0x00000026
0x0005A008: 0x00000002
0x0005A00C: 0x012A0024
0x0005A010: 0x0117001F
0x0005A014: 0x00000000
0x0005A018: 0x00000000
0x0005A01C: 0x0000E00E
0x0005A020: 0x00000002
0x0005A024: 0x00000000
0x0005A028: 0xEB800000
0x0005A02C: 0x00000000
0x0005A030: 0x00140000
0x0005A034: 0x00000000
0x0005A038: 0x00000000
0x0005A03C: 0x00000000
0x0005A040: 0x00000000
0x0005A044: 0x00000000
0x0005A048: 0x00000000
0x0005A04C: 0x00000000
0x0005A050: 0x14000000
0x0005A054: 0x68000000
0x0005A058: 0x2A000000
0x0005A05C: 0x68000000
0x0005A060: 0x00000000
0x0005A064: 0x00000F0A
0x0005A068: 0x00000006
0x0005A06C: 0x00000000
0x0005A070: 0x80000002
0x0005A074: 0x80000002
0x0005A078: 0x80000041
0x0005A07C: 0x80000042
0x0005A080: 0x80000042
0x0005A084: 0x00000041
0x0005A088: 0x00000000
0x0005A08C: 0x00000008
0x0005A090: 0x00000000
0x0005A094: 0x00000000
0x0005A098: 0x00000000
0x0005A09C: 0x00000000
0x0005A0A0: 0x00000000
0x0005A0A4: 0x00000000
0x0005A0A8: 0x00000000
0x0005A0AC: 0x01FF00FF
0x0005A0B0: 0x00000000
0x0005A0B4: 0x00000000
0x0005A0B8: 0x00000000
0x0005A0BC: 0x00000000
0x0005A0C0: 0x01FF00FF
0x0005A0C4: 0x00000000
0x0005A0C8: 0x00000000
0x0005A0CC: 0x00000000
0x0005A0D0: 0x00000000
0x0005A0D4: 0x01FF00FF
0x0005A0D8: 0x00000000
0x0005A0DC: 0x00000000
0x0005A0E0: 0x00000000
0x0005A0E4: 0x00000000
0x0005A0E8: 0x01FF00FF
0x0005A0EC: 0x00000000
0x0005A0F0: 0x00000001
0x0005A0F4: 0x00000001
0x0005A0F8: 0x00000000
0x0005A0FC: 0x00000000


----------



## adversary

Now, running chiller, we got it down to 51.2ns, from 51.9ns.
Difference is exactly what chiller allowed me, to push tRCDRD from 14 to 13 without any errors, and to push core clocks more aggressive, both things contibuted.
Lowering any other primary timings provide almost no change (0.1ns at best), so I did not want to bother with it.
Did not have much time today, but did also Prime95 LargeFFT and Y-Cruncher for some time, 0 error or warnings.
This is not in Safe mode. In Safe mode, latency is better by 0.1ns exactly.
Average temperature during TM5 was 22.xxC.
This further proves how much BDies likes low temps.
Thermal pads still are not replaced, and heatsink plates are not machined (because they are not nearly flat, clearly visible by eye).
In next days when I get time, EKWB 2.5 W/mK thermal pads will be replaced with 15 W/mK ones, and plates will be machined to get flat surface (and that may be reason for difference between Dimms temperature). This will also help further a little bit.

From my expirience not long ago, I have no doubt it will pass 25 cycles, as long as temperature is under control, and in case of this settings it is - below 25C (13 tRCDRD will produce errors above that, but at same voltage, 14 tRCDRD is going to be stable up to 36-37C).

And voltage used is 1.57V.

This is not settings just for short show, this is what I'm going to use. It will be possible always, except in middle of hottest summer days, in that case, I can't set chiller target temperature this low, DEW point is going to be different. Even today was solid warm day, but not as summer tend to be at place I live (meaning, for example at night time, or winter, or any time when ambient temperatures tend to be lower, chiller could even push temperatures further down without risk of condensation - but not really needed, as this settings are stable).

I should apply to be added for Zen3 latency results 

This extreme cooling may be some kind of "cheating"  . But, I planned it and invested into it, and it is ready for normal daily use, hence I consider result as fully legit. But definitely, this would not be possible without this cooling.
On the other side, this CPU bin is pretty bad, and motherboard with this BIOS do not allow me to push more than +200Mhz. Should I have another, or same CPU model, but better binned or higher clocked, with more than +200Mhz possible, some combination of these, I belive result would be even slightly better.


----------



## Veii

craxton said:


> as it stands i dont have this info backed up, not even on ebay to the seller.
> but when im off work later, ill tear down and find out.
> least i can do is find out, maybe this will tell a little better info
> on "possible better" chips or not...
> 
> (Edit<BG 20XX>)
> Found my backups for Google photos.. glad I have that subscription now...


Please run Debug on Zentimings, you might have a dual CCD lottery unit
Depends but the chance is likely ~ over 70% likely


mongoled said:


> Dont see these offsets in the "SMU Power Table"
> 
> Would that mean that "DF States" do not exist in the BIOS even though the option has been unhidden ?


If i remember correctly - up to how many cores you have, the table changes
For me it's fully different than usual 5600X , it's longer
Soo the "offset position" changes ~ which makes thing a bit problematic 🤔 🤔 

DF-CStates is only in AMD CBS
it's above CPPC, inside NBIO, SMU common options
Yea somewhere along these lines 
===============================
Ballistix MAX 18-19-19 1.35v arrived
32gb dimms are 2020 version of Rev.B ~ single rank
16gb seem to be something else, curious 
The box and the PCBs are "heavy" , like actually 300g heavy  

Will see how they behave, probably till tomorrow


----------



## jomama22

adversary said:


> View attachment 2511491
> 
> 
> 
> 
> 
> Now, running chiller, we got it down to 51.2ns, from 51.9ns.
> Difference is exactly what chiller allowed me, to push tRCDRD from 14 to 13 without any errors, and to push core clocks more aggressive, both things contibuted.
> Lowering any other primary timings provide almost no change (0.1ns at best), so I did not want to bother with it.
> Did not have much time today, but did also Prime95 LargeFFT and Y-Cruncher for some time, 0 error or warnings.
> This is not in Safe mode. In Safe mode, latency is better by 0.1ns exactly.
> Average temperature during TM5 was 22.xxC.
> This further proves how much BDies likes low temps.
> Thermal pads still are not replaced, and heatsink plates are not machined (because they are not nearly flat, clearly visible by eye).
> In next days when I get time, EKWB 2.5 W/mK thermal pads will be replaced with 15 W/mK ones, and plates will be machined to get flat surface (and that may be reason for difference between Dimms temperature). This will also help further a little bit.
> 
> From my expirience not long ago, I have no doubt it will pass 25 cycles, as long as temperature is under control, and in case of this settings it is - below 25C (13 tRCDRD will produce errors above that, but at same voltage, 14 tRCDRD is going to be stable up to 36-37C).
> 
> And voltage used is 1.57V.
> 
> This is not settings just for short show, this is what I'm going to use. It will be possible always, except in middle of hottest summer days, in that case, I can't set chiller target temperature this low, DEW point is going to be different. Even today was solid warm day, but not as summer tend to be at place I live (meaning, for example at night time, or winter, or any time when ambient temperatures tend to be lower, chiller could even push temperatures further down without risk of condensation - but not really needed, as this settings are stable).
> 
> I should apply to be added for Zen3 latency results
> 
> This extreme cooling may be some kind of "cheating"  . But, I planned it and invested into it, and it is ready for normal daily use, hence I consider result as fully legit. But definitely, this would not be possible without this cooling.
> On the other side, this CPU bin is pretty bad, and motherboard with this BIOS do not allow me to push more than +200Mhz. Should I have another, or same CPU model, but better binned or higher clocked, with more than +200Mhz possible, some combination of these, I belive result would be even slightly better.


On those single ccd chips, you will actually get better latency from PBO unless you can get your all-core oc above 5-5.1ghz. 380014-14-14-14 was giving me 51.2 when doing testing using 1ccd on the 5950x and those settings w/PBO. All-core was stuck at 51.9 as you showed.


----------



## mongoled

Veii said:


> DF-CStates is only in AMD CBS
> it's above CPPC, inside NBIO, SMU common options
> Yea somewhere along these lines


No problem finding them as per your detailed instructions on page 407





Veii said:


> Ballistix MAX 18-19-19 1.35v arrived
> 32gb dimms are 2020 version of Rev.B ~ single rank
> 16gb seem to be something else, curious
> The box and the PCBs are "heavy" , like actually 300g heavy
> 
> Will see how they behave, probably till tomorrow


Look forward to seeing how those get on!


----------



## Veii

mongoled said:


> Look forward to seeing how those get on!


Rev.E 19mm
But i don't recognize that part "die density = part number"
Z11B 
Same RTTs as B-Dies, A2 PCB but i doubt it's really A2 (it should've been A3)















But surely same powering characteristics
tFAW is 6* , like SubUrgent refresh usually enforces ~ unless manually changed
Interesting indeed
Getting tRFC 200ns would be already an achievement
Booted easily 2000 FCLK, if you enforce voltages and dont let it predict nonsense
RTT & proc + CAD where auto , same as the rest after tRC

EDIT:
Honestly would be more happy with 2020 Rev.B, but maybe these could be fun nevertheless


----------



## adversary

jomama22 said:


> On those single ccd chips, you will actually get better latency from PBO unless you can get your all-core oc above 5-5.1ghz. 380014-14-14-14 was giving me 51.2 when doing testing using 1ccd on the 5950x and those settings w/PBO. All-core was stuck at 51.9 as you showed.



At 51.9 I also used PBO.
Don't like all core fixed overclock for number of reasons.
With cooling, CPU also get very good boost as well.
I did 51.1ns with 13-13-12, but did not want to even bother for just 0.1ns so I did not test that, instead I opted for this 14-13-12.


----------



## jomama22

adversary said:


> At 51.9 I also used PBO.
> Don't like all core fixed overclock for number of reasons.
> With cooling, CPU also get very good boost as well.
> I did 51.1ns with 13-13-12, but did not want to even bother for just 0.1ns so I did not test that, instead I opted for this 14-13-12.


Yeah, my guess is since you're on the 5600x, it's not really letting you boost fmax all that high. That testing was at 5150-5.2 when I was doing it.


----------



## adversary

jomama22 said:


> Yeah, my guess is since you're on the 5600x, it's not really letting you boost fmax all that high. That testing was at 5150-5.2 when I was doing it.



Yes, I already mentioned at post where I put picture, that CPU and motherboard is limit in this case. But I compensated for it using more aggressive timings compared to you, hence similar result.

tRCDRD of 13 provided very good improvement, but other primary timings do not. Maybe it is some kind od limit.

But now it is too late to be sorry for CPU and motherboard choice. Sure 5800X (and most probably better binned, as this sample I have is crap) with Unify-X would get better result.

However I'm going to stay with this CPU and board for at least a year. Once we get Zen3+ or some refresh, and once we are sure product matures, I would than go for it as long term plan PC. That was my plan from beginning, to first get into AMD at all, learn something, so 5600X and this board is indeed good choice for that decision, as they are temporary solution, always easy to sell.

When upgrade day comes, as solution intended to last for years, I will do my best to pick CPU (if binned happened to be offered, I would be interested) and motherboard. There are rumors of X570S already and MSI Unify-X are mentioned as one of these. We need to keep eye on tech  . I will however need more cores for future CPU, for obvious reasons.
Should I keep this RAM still, probably, but we will see again about that when upgrade time comes.

On other hand, this Zen3 proven so much more powerful than my old Intel CPU, than I simply have all performance I need in next year. I can attempt further tunings with new BIOS(es), or whatever we discover in meantime. But I can wait for best CPU choice relaxed and with no rush. I would not ever buy CPU moment it was released (I do not prefer that for any product) if I did not have exact this plan. So far so good.


----------



## craxton

Veii said:


> Please run Debug on Zentimings, you might have a dual CCD lottery unit
> Depends but the chance is likely ~ over 70% likely











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Finally stable ProcODT 48 with [email protected]/s. CAD BUS Setup format X-0-0 = lower ClkDrvStr/ProcODT/VSOC




www.overclock.net





Don't believe so 😶

Unless I need to post more?


----------



## PJVol

mongoled said:


> Dont see these offsets in the "SMU Power Table





> Offset 1D0: 301.88140000
> Offset 1D4: 284.66360000
> Offset 1D8: 592.59260000
> Offset 1DC: 301.88680000


From your log.
301.88 mhz curr. perf. clock
284.66 mhz curr. eff. clock
592.59 max DPM for lclk3
301.88 min DPM for lclk3

PS: I've mistaken, 0x01d4 is effective clock, 1d8 and 1dc are max/min dpm state's clocks, sorry about that

I could PM you my (actually not mine initially, but I slightly revised it) estimated lables for that table, when i get to my home PC (if you want, of course)


----------



## Taraquin

Veii said:


> Rev.E 19mm
> But i don't recognize that part "die density = part number"
> Z11B
> Same RTTs as B-Dies, A2 PCB but i doubt it's really A2 (it should've been A3)
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But surely same powering characteristics
> tFAW is 6* , like SubUrgent refresh usually enforces ~ unless manually changed
> Interesting indeed
> Getting tRFC 200ns would be already an achievement
> Booted easily 2000 FCLK, if you enforce voltages and dont let it predict nonsense
> RTT & proc + CAD where auto , same as the rest after tRC
> 
> EDIT:
> Honestly would be more happy with 2020 Rev.B, but maybe these could be fun nevertheless


I have done a lot of rev E tuning and except for tRCDRD, tRC and tRFC they can run many timings very tight. Comparing my good binned rev E vs B-die at 3733cl15 I could run tRP 11, twtrs 3 and twtrl 6 on rev E vs tRP 14 and twtrs 4, twtrl 10 8n B-die, 1T gdm off was also much easier on rev E. But I could run tRCDRD 15 vs 20, tRC 34 vs 56, tRFC 260 vs 525 on B-die.


----------



## Flash1228

Veii said:


> Rev.E 19mm
> But i don't recognize that part "die density = part number"
> Z11B
> Same RTTs as B-Dies, A2 PCB but i doubt it's really A2 (it should've been A3)
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But surely same powering characteristics
> tFAW is 6* , like SubUrgent refresh usually enforces ~ unless manually changed
> Interesting indeed
> Getting tRFC 200ns would be already an achievement
> Booted easily 2000 FCLK, if you enforce voltages and dont let it predict nonsense
> RTT & proc + CAD where auto , same as the rest after tRC
> 
> EDIT:
> Honestly would be more happy with 2020 Rev.B, but maybe these could be fun nevertheless


Looks pretty close to my Ballistix Elite. The 3800 is what I normally use, but I've gotten both through 20 rounds of TM5 and no issues with y-cruncher. 4000 does give WHEA 19 unless I change CPU 1.8 to 2


----------



## DeletedMember558271

ManniX-ITA said:


> Did you try the latest EFI UNDI from beginning of May?


Yea does anyone already familiar with BIOS modding want to try this so I don't have to figure it out to find out it does nothing?


Veii said:


> Only got "mad" as Realtek Team continued to drive that path of barely doing anything ~ according to close source communication between board manufactures and them
> While as it's been linked here, Intel resolved it decently fast


Except people with Intel are still suffering from basically identical WHEA issues above 1900 FCLK, and there are people with Realtek who are not.

Not sure how long it takes to mod a BIOS to disable Realtek cause I'm not familiar with BIOS modding but still waiting on the results from that, if it turns out to do nothing we're not going to just not hear anything are we?
This was the big news big reveal most exciting/interesting thing to find out right now, if it actually does anything


----------



## hazium233

Veii said:


> Rev.E 19mm
> But i don't recognize that part "die density = part number"
> Z11B


The Micron code for the actual die for 8Gb Rev E. I think these I have collected are accurate:

4Gb

Z80A Rev A
Z90B Rev B
Z00B Rev E
Z10B Rev F
Z20A Rev G

8Gb

Z91B Rev A
Z01A Rev B
Z01B Rev D
Z11B Rev E
Z01C Rev G
Z11C Rev H
Z21C Rev J
Z21E Rev N -> half capacity 16Gb, not on 8Gb sheet
Z31A Rev P -> suspect half capacity 16Gb, not on 8Gb
Z??? Rev R

16Gb

Z12A Rev A
Z22A Rev B
Z32D Rev E



> Same RTTs as B-Dies, A2 PCB but i doubt it's really A2 (it should've been A3)


I don't think Micron / Crucial programs PCB revision.


----------



## craxton

Whose reporting posts?? 
Or does the site send a noti to admins 
When stuff is linked outside the site 
Like crack stuff (in spoilers) 
Just curious, not an issue for the warning to me but am curious to how 
Their flags work....


----------



## ManniX-ITA

PJVol said:


> I could PM you my (actually not mine initially, but I slightly revised it) estimated lables for that table, when i get to my home PC (if you want, of course)


I'd like too! Thanks


----------



## ManniX-ITA

BTW found out the reason why I could push 2-4 CO counts lower at FCLK 2000 is VDDG IOD and VSOC.
Just going from IOD 1100 to 1120 and VSOC 1.17 to 1.18 made this difference.



Dreamic said:


> Yea does anyone already familiar with BIOS modding want to try this so I don't have to figure it out to find out it does nothing?


I did already, doesn't change anything for me.


----------



## craxton

Veii said:


> Unsure about 2 Fused away cores - up to Core Layout and Chip (CTR can figure this out)


you mention this around 8 days ago,
how does CTR go about telling this information?

do i just run it and let it finish, then itll tell me if to cores are "inactive"
or...

im unsure if the post i linked gave all the info needed or not.
but here is a full debug report to which im pretty sure, 
its one CCD..




Spoiler






Code:


ZenTimings 1.2.3.201 Debug Report

######################################################
System Info
######################################################
OS: Microsoft Windows 10 Home
CpuName: AMD Ryzen 5 5600X 6-Core Processor
CodeName: Vermeer
CpuId: 00A20F10
Model: 33
ExtendedModel: 32
PackageType: 2
FusedCoreCount: 6
PhysicalCoreCount: 8
NodesPerProcessor: 1
Threads: 12
SMT: True
CCDCount: 1
CCXCount: 1
NumCoresInCCX: 6
MbVendor: Micro-Star International Co., Ltd.
MbName: MPG B550 GAMING EDGE WIFI (MS-7C91)
BiosVersion: 1.61
SmuVersion: 56.46.0
SmuTableVersion: 00380904
PatchLevel: 0A201009

######################################################
Memory Modules
######################################################
P0 CHANNEL A | DIMM 0
-- Slot: A1
-- Single Rank
-- DCT Offset: 0x0
-- Manufacturer: Unknown
-- TEAMGROUP-UD4-3200 8GB 4000MHz

P0 CHANNEL A | DIMM 1
-- Slot: A2
-- Single Rank
-- DCT Offset: 0x0
-- Manufacturer: Unknown
-- TEAMGROUP-UD4-3200 8GB 4000MHz

P0 CHANNEL B | DIMM 0
-- Slot: B1
-- Single Rank
-- DCT Offset: 0x1
-- Manufacturer: Unknown
-- TEAMGROUP-UD4-3200 8GB 4000MHz

P0 CHANNEL B | DIMM 1
-- Slot: B2
-- Single Rank
-- DCT Offset: 0x1
-- Manufacturer: Unknown
-- TEAMGROUP-UD4-3200 8GB 4000MHz

######################################################
Memory Channels Info
######################################################
Channel0: True
-- UMC Registers
   0x00050000: 0x00000001
   0x00050004: 0x00000000
   0x00050008: 0x00000201
   0x0005000C: 0x00000000
   0x00050010: 0x00000000
   0x00050014: 0x00000000
   0x00050018: 0x00000000
   0x0005001C: 0x00000000
   0x00050020: 0x03FFFDFE
   0x00050024: 0x03FFFDFE
   0x00050028: 0x00000000
   0x0005002C: 0x00000000
   0x00050030: 0x00150608
   0x00050034: 0x00150608
   0x00050038: 0x00000000
   0x0005003C: 0x00000000
   0x00050040: 0x060C98BA
   0x00050044: 0x060C98BA
   0x00050048: 0x00000000
   0x0005004C: 0x00000000
   0x00050050: 0x87654321
   0x00050054: 0xA9876543
   0x00050058: 0x87654321
   0x0005005C: 0xA9876543
   0x00050060: 0x00000000
   0x00050064: 0x00000000
   0x00050068: 0x00000000
   0x0005006C: 0x00000000
   0x00050070: 0x00000000
   0x00050074: 0x00000000
   0x00050078: 0x00000000
   0x0005007C: 0x00000000
   0x00050080: 0x00000000
   0x00050084: 0x00000000
   0x00050088: 0x00000000
   0x0005008C: 0x00000000
   0x00050090: 0x00000000
   0x00050094: 0x00000000
   0x00050098: 0x00000000
   0x0005009C: 0x00000000
   0x000500A0: 0x36163616
   0x000500A4: 0x36163616
   0x000500A8: 0x36163616
   0x000500AC: 0x36163616
   0x000500B0: 0x00000000
   0x000500B4: 0x36163616
   0x000500B8: 0x36163616
   0x000500BC: 0x36163616
   0x000500C0: 0x36163616
   0x000500C4: 0x00000000
   0x000500C8: 0x04444001
   0x000500CC: 0x08888001
   0x000500D0: 0x111107F1
   0x000500D4: 0x22220001
   0x000500D8: 0x00000000
   0x000500DC: 0x00000000
   0x000500E0: 0x00000000
   0x000500E4: 0x00000000
   0x000500E8: 0x03FFFC00
   0x000500EC: 0x03FFFC01
   0x000500F0: 0x00000401
   0x000500F4: 0x00040001
   0x000500F8: 0x00000000
   0x000500FC: 0x00000000
   0x00050100: 0x80000200
   0x00050104: 0xB040808B
   0x00050108: 0xC4403F61
   0x0005010C: 0x040000F8
   0x00050110: 0x00D09820
   0x00050114: 0x20013000
   0x00050118: 0x00000047
   0x0005011C: 0x00000000
   0x00050120: 0x00000000
   0x00050124: 0xA100480A
   0x00050128: 0x00000000
   0x0005012C: 0x01100468
   0x00050130: 0x10000000
   0x00050134: 0x00000000
   0x00050138: 0x0740C0C0
   0x0005013C: 0x00000000
   0x00050140: 0x00000000
   0x00050144: 0x000F1101
   0x00050148: 0xDA7A5C11
   0x0005014C: 0x00000000
   0x00050150: 0x02000F00
   0x00050154: 0x00280081
   0x00050158: 0x60108000
   0x0005015C: 0x00000000
   0x00050160: 0xC00A0000
   0x00050164: 0x00000000
   0x00050168: 0x00002100
   0x0005016C: 0x00000000
   0x00050170: 0x00000000
   0x00050174: 0x00000000
   0x00050178: 0x00000000
   0x0005017C: 0x00000000
   0x00050180: 0x00000000
   0x00050184: 0x00000000
   0x00050188: 0x00000000
   0x0005018C: 0x00000000
   0x00050190: 0x00000000
   0x00050194: 0x00000000
   0x00050198: 0x00000000
   0x0005019C: 0x00000000
   0x000501A0: 0x00000000
   0x000501A4: 0x00000000
   0x000501A8: 0x00000000
   0x000501AC: 0x00000000
   0x000501B0: 0x00000202
   0x000501B4: 0x00000000
   0x000501B8: 0x00000101
   0x000501BC: 0x00000000
   0x000501C0: 0x00000000
   0x000501C4: 0x00000000
   0x000501C8: 0x00000000
   0x000501CC: 0x00000000
   0x000501D0: 0x00000000
   0x000501D4: 0x00000000
   0x000501D8: 0x00000000
   0x000501DC: 0x00000000
   0x000501E0: 0x00000116
   0x000501E4: 0x00000000
   0x000501E8: 0x00000000
   0x000501EC: 0x00000000
   0x000501F0: 0x00000000
   0x000501F4: 0x00000000
   0x000501F8: 0x00000000
   0x000501FC: 0x00000000
   0x00050200: 0x0000153C
   0x00050204: 0x10102010
   0x00050208: 0x00100030
   0x0005020C: 0x06000804
   0x00050210: 0x00000010
   0x00050214: 0x000E040E
   0x00050218: 0x0000000C
   0x0005021C: 0x00000000
   0x00050220: 0x45010404
   0x00050224: 0x45010606
   0x00050228: 0x00000A04
   0x0005022C: 0x0F420080
   0x00050230: 0x00003CF0
   0x00050234: 0x1E141E08
   0x00050238: 0x040002D0
   0x0005023C: 0x24002024
   0x00050240: 0x00000000
   0x00050244: 0x7FFE0010
   0x00050248: 0x00000000
   0x0005024C: 0x00000000
   0x00050250: 0x00EA0000
   0x00050254: 0x0B04000C
   0x00050258: 0x021A090B
   0x0005025C: 0x22002A2A
   0x00050260: 0x2106B120
   0x00050264: 0x2106B120
   0x00050268: 0x00000000
   0x0005026C: 0x00000000
   0x00050270: 0x00000000
   0x00050274: 0x00000000
   0x00050278: 0x80000000
   0x0005027C: 0x80000000
   0x00050280: 0x00007072
   0x00050284: 0x00000120
   0x00050288: 0x00000552
   0x0005028C: 0x18002980
   0x00050290: 0x00000000
   0x00050294: 0x00000000
   0x00050298: 0x00000000
   0x0005029C: 0x00000000
   0x000502A0: 0x00000000
   0x000502A4: 0x00000000
   0x000502A8: 0x00000000
   0x000502AC: 0x00000000
   0x000502B0: 0x00000000
   0x000502B4: 0x00000000
   0x000502B8: 0x00000000
   0x000502BC: 0x00000000
   0x000502C0: 0x00000000
   0x000502C4: 0x00000000
   0x000502C8: 0x00000000
   0x000502CC: 0x00000000
   0x000502D0: 0x00000000
   0x000502D4: 0x00000000
   0x000502D8: 0x00000000
   0x000502DC: 0x00000000
   0x000502E0: 0x00000000
   0x000502E4: 0x00000000
   0x000502E8: 0x00000000
   0x000502EC: 0x00000000
   0x000502F0: 0x00000000
   0x000502F4: 0x00000000
   0x000502F8: 0x00000000
   0x000502FC: 0x00000000
   0x00050300: 0x00000100
Channel1: True
-- UMC Registers
   0x00150000: 0x00000001
   0x00150004: 0x00000000
   0x00150008: 0x00000201
   0x0015000C: 0x00000000
   0x00150010: 0x00000000
   0x00150014: 0x00000000
   0x00150018: 0x00000000
   0x0015001C: 0x00000000
   0x00150020: 0x03FFFDFE
   0x00150024: 0x03FFFDFE
   0x00150028: 0x00000000
   0x0015002C: 0x00000000
   0x00150030: 0x00150608
   0x00150034: 0x00150608
   0x00150038: 0x00000000
   0x0015003C: 0x00000000
   0x00150040: 0x060C98BA
   0x00150044: 0x060C98BA
   0x00150048: 0x00000000
   0x0015004C: 0x00000000
   0x00150050: 0x87654321
   0x00150054: 0xA9876543
   0x00150058: 0x87654321
   0x0015005C: 0xA9876543
   0x00150060: 0x00000000
   0x00150064: 0x00000000
   0x00150068: 0x00000000
   0x0015006C: 0x00000000
   0x00150070: 0x00000000
   0x00150074: 0x00000000
   0x00150078: 0x00000000
   0x0015007C: 0x00000000
   0x00150080: 0x00000000
   0x00150084: 0x00000000
   0x00150088: 0x00000000
   0x0015008C: 0x00000000
   0x00150090: 0x00000000
   0x00150094: 0x00000000
   0x00150098: 0x00000000
   0x0015009C: 0x00000000
   0x001500A0: 0x36163616
   0x001500A4: 0x36163616
   0x001500A8: 0x36163616
   0x001500AC: 0x36163616
   0x001500B0: 0x00000000
   0x001500B4: 0x36163616
   0x001500B8: 0x36163616
   0x001500BC: 0x36163616
   0x001500C0: 0x36163616
   0x001500C4: 0x00000000
   0x001500C8: 0x04444001
   0x001500CC: 0x08888001
   0x001500D0: 0x111107F1
   0x001500D4: 0x22220001
   0x001500D8: 0x00000000
   0x001500DC: 0x00000000
   0x001500E0: 0x00000000
   0x001500E4: 0x00000000
   0x001500E8: 0x03FFFC00
   0x001500EC: 0x03FFFC01
   0x001500F0: 0x00000401
   0x001500F4: 0x00040001
   0x001500F8: 0x00000000
   0x001500FC: 0x00000000
   0x00150100: 0x80000200
   0x00150104: 0xB040808B
   0x00150108: 0xC4403F61
   0x0015010C: 0x040000F8
   0x00150110: 0x00D09820
   0x00150114: 0x20013000
   0x00150118: 0x00000047
   0x0015011C: 0x00000000
   0x00150120: 0x00000000
   0x00150124: 0xA100480A
   0x00150128: 0x00000000
   0x0015012C: 0x01100468
   0x00150130: 0x10000000
   0x00150134: 0x00000000
   0x00150138: 0x0740C0C0
   0x0015013C: 0x00000000
   0x00150140: 0x00000000
   0x00150144: 0x000F1101
   0x00150148: 0xDA7A5C11
   0x0015014C: 0x00000000
   0x00150150: 0x02000F00
   0x00150154: 0x00280081
   0x00150158: 0x60108000
   0x0015015C: 0x00000000
   0x00150160: 0xF00A0000
   0x00150164: 0x00000000
   0x00150168: 0x00002100
   0x0015016C: 0x00000000
   0x00150170: 0x00000000
   0x00150174: 0x00000000
   0x00150178: 0x00000000
   0x0015017C: 0x00000000
   0x00150180: 0x00000000
   0x00150184: 0x00000000
   0x00150188: 0x00000000
   0x0015018C: 0x00000000
   0x00150190: 0x00000000
   0x00150194: 0x00000000
   0x00150198: 0x00000000
   0x0015019C: 0x00000000
   0x001501A0: 0x00000000
   0x001501A4: 0x00000000
   0x001501A8: 0x00000000
   0x001501AC: 0x00000000
   0x001501B0: 0x00000202
   0x001501B4: 0x00000000
   0x001501B8: 0x00000101
   0x001501BC: 0x00000000
   0x001501C0: 0x00000000
   0x001501C4: 0x00000000
   0x001501C8: 0x00000000
   0x001501CC: 0x00000000
   0x001501D0: 0x00000000
   0x001501D4: 0x00000000
   0x001501D8: 0x00000000
   0x001501DC: 0x00000000
   0x001501E0: 0x00000116
   0x001501E4: 0x00000000
   0x001501E8: 0x00000000
   0x001501EC: 0x00000000
   0x001501F0: 0x00000000
   0x001501F4: 0x00000000
   0x001501F8: 0x00000000
   0x001501FC: 0x00000000
   0x00150200: 0x0000153C
   0x00150204: 0x10102010
   0x00150208: 0x00100030
   0x0015020C: 0x06000804
   0x00150210: 0x00000010
   0x00150214: 0x000E040E
   0x00150218: 0x0000000C
   0x0015021C: 0x00000000
   0x00150220: 0x45010404
   0x00150224: 0x45010606
   0x00150228: 0x00000A04
   0x0015022C: 0x0F420080
   0x00150230: 0x00003CF0
   0x00150234: 0x1E141E08
   0x00150238: 0x040002D0
   0x0015023C: 0x24002024
   0x00150240: 0x00000000
   0x00150244: 0x7FFE0010
   0x00150248: 0x00000000
   0x0015024C: 0x00000000
   0x00150250: 0x00EA0000
   0x00150254: 0x0B04000C
   0x00150258: 0x021A090B
   0x0015025C: 0x22002A2A
   0x00150260: 0x2106B120
   0x00150264: 0x2106B120
   0x00150268: 0x00000000
   0x0015026C: 0x00000000
   0x00150270: 0x00000000
   0x00150274: 0x00000000
   0x00150278: 0x80000000
   0x0015027C: 0x80000000
   0x00150280: 0x00007072
   0x00150284: 0x00000120
   0x00150288: 0x00000552
   0x0015028C: 0x18002980
   0x00150290: 0x00000000
   0x00150294: 0x00000000
   0x00150298: 0x00000000
   0x0015029C: 0x00000000
   0x001502A0: 0x00000000
   0x001502A4: 0x00000000
   0x001502A8: 0x00000000
   0x001502AC: 0x00000000
   0x001502B0: 0x00000000
   0x001502B4: 0x00000000
   0x001502B8: 0x00000000
   0x001502BC: 0x00000000
   0x001502C0: 0x00000000
   0x001502C4: 0x00000000
   0x001502C8: 0x00000000
   0x001502CC: 0x00000000
   0x001502D0: 0x00000000
   0x001502D4: 0x00000000
   0x001502D8: 0x00000000
   0x001502DC: 0x00000000
   0x001502E0: 0x00000000
   0x001502E4: 0x00000000
   0x001502E8: 0x00000000
   0x001502EC: 0x00000000
   0x001502F0: 0x00000000
   0x001502F4: 0x00000000
   0x001502F8: 0x00000000
   0x001502FC: 0x00000000
   0x00150300: 0x00000100
Channel2: False
Channel3: False
Channel4: False
Channel5: False
Channel6: False
Channel7: False

######################################################
Memory Config
######################################################
Frequency: 4000
Ratio: 20
TotalCapacity: 32GB
BGS: Disabled
BGSAlt: Enabled
GDM: Disabled
PowerDown: Disabled
Cmd2T: 2T
CL: 16
RCDWR: 16
RCDRD: 16
RP: 16
RAS: 32
RC: 48
RRDS: 4
RRDL: 8
FAW: 16
WTRS: 4
WTRL: 14
WR: 12
RDRDSCL: 5
WRWRSCL: 5
CWL: 14
RTP: 6
RDWR: 10
WRRD: 4
RDRDSC: 1
RDRDSD: 4
RDRDDD: 4
WRWRSC: 1
WRWRSD: 6
WRWRDD: 6
TRCPAGE: 0
CKE: 11
STAG: 234
MOD: 30
MODPDA: 30
MRD: 8
MRDPDA: 20
RFC: 288
RFCns: 144
RFC2: 214
RFC4: 132
REFI: 15600
REFIns: 7800
XP: 12
PHYWRD: 2
PHYWRL: 9
PHYRDL: 26

######################################################
BIOS: Memory Controller Config
######################################################
Index 000: 00 (0)
Index 001: 00 (0)
Index 002: 00 (0)
Index 003: 00 (0)
Index 004: 00 (0)
Index 005: 00 (0)
Index 006: 1F (31)
Index 007: 1F (31)
Index 008: 00 (0)
Index 009: 00 (0)
Index 010: 00 (0)
Index 011: 00 (0)
Index 012: 00 (0)
Index 013: 00 (0)
Index 014: 00 (0)
Index 015: 00 (0)
Index 016: 00 (0)
Index 017: 00 (0)
Index 018: 00 (0)
Index 019: 00 (0)
Index 020: D0 (208)
Index 021: 07 (7)
Index 022: 10 (16)
Index 023: 10 (16)
Index 024: 10 (16)
Index 025: 20 (32)
Index 026: 10 (16)
Index 027: C8 (200)
Index 028: 05 (5)
Index 029: E4 (228)
Index 030: 02 (2)
Index 031: 00 (0)
Index 032: 00 (0)
Index 033: 38 (56)
Index 034: 00 (0)
Index 035: 00 (0)
Index 036: 00 (0)
Index 037: 30 (48)
Index 038: 20 (32)
Index 039: 01 (1)
Index 040: D6 (214)
Index 041: 00 (0)
Index 042: 84 (132)
Index 043: 00 (0)
Index 044: 10 (16)
Index 045: 04 (4)
Index 046: 08 (8)
Index 047: 0C (12)
Index 048: 04 (4)
Index 049: 0E (14)
Index 050: 0B (11)
Index 051: 0E (14)
Index 052: 06 (6)
Index 053: 01 (1)
Index 054: 05 (5)
Index 055: 04 (4)
Index 056: 04 (4)
Index 057: 01 (1)
Index 058: 05 (5)
Index 059: 06 (6)
Index 060: 06 (6)
Index 061: 0A (10)
Index 062: 04 (4)
Index 063: 00 (0)
Index 064: 01 (1)
Index 065: 03 (3)
Index 066: 04 (4)
Index 067: 06 (6)
Index 068: 00 (0)
Index 069: 00 (0)
Index 070: 0E (14)
Index 071: 06 (6)
Index 072: 00 (0)
Index 073: 00 (0)
Index 074: 00 (0)
Index 075: 00 (0)
Index 076: 00 (0)
Index 077: 00 (0)
Index 078: 01 (1)
Index 079: 00 (0)
Index 080: 00 (0)
Index 081: 00 (0)
Index 082: 00 (0)
Index 083: 00 (0)
Index 084: 06 (6)
Index 085: 00 (0)
Index 086: 04 (4)
Index 087: 04 (4)
Index 088: 12 (18)
Index 089: 03 (3)
Index 090: 1F (31)
Index 091: 0F (15)
Index 092: 0F (15)
Index 093: 00 (0)
Index 094: 00 (0)
Index 095: 00 (0)
Index 096: 01 (1)
Index 097: 00 (0)
Index 098: 00 (0)
Index 099: 00 (0)
Index 100: 01 (1)
Index 101: 00 (0)
Index 102: 00 (0)
Index 103: 00 (0)
Index 104: 00 (0)
Index 105: 01 (1)
Index 106: 00 (0)
Index 107: 00 (0)
Index 108: F4 (244)
Index 109: 01 (1)
Index 110: 00 (0)
Index 111: 00 (0)
Index 112: C8 (200)
Index 113: 00 (0)
Index 114: 00 (0)
Index 115: 00 (0)
Index 116: DC (220)
Index 117: 00 (0)
Index 118: 00 (0)
Index 119: 00 (0)
Index 120: 00 (0)
Index 121: 00 (0)
Index 122: 00 (0)
Index 123: 00 (0)
Index 124: 02 (2)
Index 125: 02 (2)
Index 126: 00 (0)
Index 127: 00 (0)
Index 128: 00 (0)
Index 129: 00 (0)
Index 130: 00 (0)
Index 131: 00 (0)
Index 132: 01 (1)
Index 133: 00 (0)
Index 134: 00 (0)
Index 135: 00 (0)
Index 136: 00 (0)
Index 137: 00 (0)
Index 138: 00 (0)
Index 139: 00 (0)
Index 140: 00 (0)
Index 141: 00 (0)
Index 142: 00 (0)
Index 143: 00 (0)
Index 144: 00 (0)
Index 145: 00 (0)
Index 146: 00 (0)
Index 147: 00 (0)
Index 148: 00 (0)
Index 149: 00 (0)
Index 150: 00 (0)
Index 151: 00 (0)
Index 152: 00 (0)
Index 153: 00 (0)
Index 154: 00 (0)
Index 155: 00 (0)
Index 156: 00 (0)
Index 157: 00 (0)
Index 158: 00 (0)
Index 159: 00 (0)
Index 160: 00 (0)
Index 161: 00 (0)
Index 162: 00 (0)
Index 163: 00 (0)
Index 164: 00 (0)
Index 165: 00 (0)
Index 166: 00 (0)
Index 167: 0E (14)
Index 168: 06 (6)
Index 169: 00 (0)
Index 170: 00 (0)
Index 171: 00 (0)
Index 172: 00 (0)
Index 173: 00 (0)
Index 174: 00 (0)
Index 175: 00 (0)
Index 176: 00 (0)
Index 177: 00 (0)
Index 178: 00 (0)
Index 179: 00 (0)
Index 180: 00 (0)
Index 181: 00 (0)
Index 182: 00 (0)
Index 183: 00 (0)
Index 184: 00 (0)
Index 185: 00 (0)
Index 186: 00 (0)
Index 187: 00 (0)
Index 188: 00 (0)
Index 189: 00 (0)
Index 190: 00 (0)
Index 191: 00 (0)
Index 192: 00 (0)
Index 193: 00 (0)
Index 194: 00 (0)
Index 195: 00 (0)
Index 196: 00 (0)
Index 197: 00 (0)
Index 198: 00 (0)
Index 199: 00 (0)

######################################################
SMU: Power Table
######################################################
Offset 000: 1000.00000000
Offset 004: 36.61806000
Offset 008: 200.00000000
Offset 00C: 8.76048200
Offset 010: 90.00000000
Offset 014: 30.26676000
Offset 018: 6471.90000000
Offset 01C: 17.60346000
Offset 020: 220.00000000
Offset 024: 65.15617000
Offset 028: 1.44997600
Offset 02C: 1.04953000
Offset 030: 3.58166000
Offset 034: 36.62670000
Offset 038: 0.00000000
Offset 03C: 5.95990600
Offset 040: 0.00000000
Offset 044: 30.26677000
Offset 048: 0.00000000
Offset 04C: 17.35543000
Offset 050: 0.00000000
Offset 054: 65.15617000
Offset 058: 0.00000000
Offset 05C: 1.04953000
Offset 060: 10.67371000
Offset 064: 14.39281000
Offset 068: 9.64134000
Offset 06C: 0.91885670
Offset 070: 1.00000000
Offset 074: 36.62670000
Offset 078: 4.85006800
Offset 07C: 4.85006800
Offset 080: 4.85006800
Offset 084: 4.85006800
Offset 088: 4.85006800
Offset 08C: 4.85006800
Offset 090: 4.85006800
Offset 094: 4.85006800
Offset 098: 1.44997600
Offset 09C: 1.44997600
Offset 0A0: 1.04953000
Offset 0A4: 1.12548200
Offset 0A8: 8.76615300
Offset 0AC: 10.67371000
Offset 0B0: 1.17501800
Offset 0B4: 1.16866700
Offset 0B8: 12.31539000
Offset 0BC: 14.39281000
Offset 0C0: 2000.00000000
Offset 0C4: 2000.01700000
Offset 0C8: 2000.00000000
Offset 0CC: 2000.00000000
Offset 0D0: 0.00000000
Offset 0D4: 0.35708040
Offset 0D8: 0.00000000
Offset 0DC: 0.30217520
Offset 0E0: 0.00000000
Offset 0E4: 0.02409245
Offset 0E8: 0.00000000
Offset 0EC: 0.00000000
Offset 0F0: 3.88605000
Offset 0F4: 0.00000000
Offset 0F8: 0.00000000
Offset 0FC: 0.00000000
Offset 100: 0.16747450
Offset 104: 0.10481350
Offset 108: 0.01542111
Offset 10C: 0.01542111
Offset 110: 0.17378340
Offset 114: 0.05332982
Offset 118: 100.00000000
Offset 11C: 0.00000000
Offset 120: 0.00000000
Offset 124: 0.00000000
Offset 128: 2000.00000000
Offset 12C: 0.00000000
Offset 130: 0.00000000
Offset 134: 0.00000000
Offset 138: 2000.00000000
Offset 13C: 0.00000000
Offset 140: 0.00000000
Offset 144: 0.00000000
Offset 148: 2000.00000000
Offset 14C: 0.00000000
Offset 150: 0.00000000
Offset 154: 0.00000000
Offset 158: 0.00000000
Offset 15C: 0.00000000
Offset 160: 0.00000000
Offset 164: 0.00000000
Offset 168: 5.00000000
Offset 16C: 0.00000000
Offset 170: 0.00000000
Offset 174: 0.00000000
Offset 178: 592.59260000
Offset 17C: 301.88680000
Offset 180: 31.25000000
Offset 184: 32.07527000
Offset 188: 5.00000000
Offset 18C: 0.00000000
Offset 190: 0.00000000
Offset 194: 0.00000000
Offset 198: 592.59260000
Offset 19C: 301.88680000
Offset 1A0: 0.00000000
Offset 1A4: 0.00000000
Offset 1A8: 5.00000000
Offset 1AC: 0.00000000
Offset 1B0: 0.00000000
Offset 1B4: 0.00000000
Offset 1B8: 592.59260000
Offset 1BC: 301.88680000
Offset 1C0: 0.00000000
Offset 1C4: 0.00000000
Offset 1C8: 5.00000000
Offset 1CC: 0.00430769
Offset 1D0: 301.88280000
Offset 1D4: 301.88770000
Offset 1D8: 592.59260000
Offset 1DC: 301.88680000
Offset 1E0: 31.25000000
Offset 1E4: 32.07527000
Offset 1E8: 10.00000000
Offset 1EC: 0.00000000
Offset 1F0: 0.00000000
Offset 1F4: 0.00000000
Offset 1F8: 0.00000000
Offset 1FC: 27.52708000
Offset 200: 5.66273100
Offset 204: 0.00000000
Offset 208: 4.99021700
Offset 20C: 0.00000000
Offset 210: 1.59455600
Offset 214: 0.91885670
Offset 218: 65.00000000
Offset 21C: 0.00000000
Offset 220: 0.95038550
Offset 224: 0.90908150
Offset 228: 1.07429800
Offset 22C: 0.98873930
Offset 230: 48.25000000
Offset 234: 1.34375000
Offset 238: 4.85000000
Offset 23C: 0.42913800
Offset 240: 4.85006800
Offset 244: 0.99425160
Offset 248: 0.00000000
Offset 24C: 36.69051000
Offset 250: 0.00000000
Offset 254: 0.00000000
Offset 258: 15.62068000
Offset 25C: 0.00000000
Offset 260: 0.00000000
Offset 264: 0.00000000
Offset 268: 3.66191900
Offset 26C: 500.00000000
Offset 270: 500.00000000
Offset 274: 500.00000000
Offset 278: 500.00000000
Offset 27C: 457.14290000
Offset 280: 457.14180000
Offset 284: 457.14290000
Offset 288: 140.54830000
Offset 28C: 400.00000000
Offset 290: 400.00000000
Offset 294: 0.00000000
Offset 298: 33.47221000
Offset 29C: 29.17568000
Offset 2A0: 31.00000000
Offset 2A4: 0.00000000
Offset 2A8: 0.98537330
Offset 2AC: 0.00000000
Offset 2B0: 1.00362900
Offset 2B4: 0.77991380
Offset 2B8: 0.70248780
Offset 2BC: 1.58328500
Offset 2C0: 0.90840390
Offset 2C4: 0.00000000
Offset 2C8: 0.89809010
Offset 2CC: 0.00000000
Offset 2D0: 0.90995950
Offset 2D4: 0.88619920
Offset 2D8: 0.88139090
Offset 2DC: 0.97746210
Offset 2E0: 0.89033590
Offset 2E4: 25.94938000
Offset 2E8: 28.21523000
Offset 2EC: 26.30354000
Offset 2F0: 28.45338000
Offset 2F4: 27.83200000
Offset 2F8: 27.93000000
Offset 2FC: 29.70323000
Offset 300: 28.17354000
Offset 304: 0.00000000
Offset 308: 1.33192000
Offset 30C: 0.00000000
Offset 310: 1.46064100
Offset 314: 1.26288000
Offset 318: 1.16655100
Offset 31C: 2.20375200
Offset 320: 1.40198300
Offset 324: 0.00000000
Offset 328: 8.08327400
Offset 32C: 0.00000000
Offset 330: 8.16330400
Offset 334: 7.92822200
Offset 338: 7.94326600
Offset 33C: 8.71011100
Offset 340: 8.01717400
Offset 344: 0.00000000
Offset 348: 3.80633900
Offset 34C: 0.00000000
Offset 350: 3.83678200
Offset 354: 3.74723200
Offset 358: 3.75260600
Offset 35C: 4.03976600
Offset 360: 3.77947200
Offset 364: 0.00000000
Offset 368: 0.26721020
Offset 36C: 0.00000000
Offset 370: 0.28637240
Offset 374: 0.15408240
Offset 378: 0.15007720
Offset 37C: 0.72368940
Offset 380: 0.24712060
Offset 384: 0.00000000
Offset 388: 6.42892200
Offset 38C: 0.00000000
Offset 390: 6.94841800
Offset 394: 3.66901100
Offset 398: 3.51007400
Offset 39C: 16.57923000
Offset 3A0: 5.77815400
Offset 3A4: 0.00000000
Offset 3A8: 93.45130000
Offset 3AC: 0.00000000
Offset 3B0: 81.02544000
Offset 3B4: 71.98666000
Offset 3B8: 64.65768000
Offset 3BC: 83.42073000
Offset 3C0: 70.95082000
Offset 3C4: 100.00000000
Offset 3C8: 0.11974150
Offset 3CC: 100.00000000
Offset 3D0: 12.02617000
Offset 3D4: 24.34449000
Offset 3D8: 31.83249000
Offset 3DC: 0.00000000
Offset 3E0: 23.27130000
Offset 3E4: 0.00000000
Offset 3E8: 0.00000000
Offset 3EC: 0.00000000
Offset 3F0: 0.00000000
Offset 3F4: 0.00000000
Offset 3F8: 0.00000000
Offset 3FC: 0.00000000
Offset 400: 0.00000000
Offset 404: 0.00000000
Offset 408: 0.00000000
Offset 40C: 0.00000000
Offset 410: 0.00000000
Offset 414: 0.00000000
Offset 418: 0.00000000
Offset 41C: 0.00000000
Offset 420: 0.00000000
Offset 424: 0.00000000
Offset 428: 95.22049000
Offset 42C: 0.00000000
Offset 430: 81.00928000
Offset 434: 73.40327000
Offset 438: 66.00623000
Offset 43C: 99.30675000
Offset 440: 75.83192000
Offset 444: 0.00000000
Offset 448: 0.00000000
Offset 44C: 0.00000000
Offset 450: 0.00000000
Offset 454: 0.00000000
Offset 458: 0.00000000
Offset 45C: 0.00000000
Offset 460: 0.00000000
Offset 464: 4.85006800
Offset 468: 4.85006800
Offset 46C: 4.85006800
Offset 470: 4.85006800
Offset 474: 4.85006800
Offset 478: 4.85006800
Offset 47C: 4.85006800
Offset 480: 4.85006800
Offset 484: 0.54999190
Offset 488: 1.78866900
Offset 48C: 0.54999190
Offset 490: 1.78866900
Offset 494: 1.78866900
Offset 498: 1.78866900
Offset 49C: 1.78866900
Offset 4A0: 1.78866900
Offset 4A4: 254.00000000
Offset 4A8: 125.14580000
Offset 4AC: 254.00000000
Offset 4B0: 125.22650000
Offset 4B4: 125.04310000
Offset 4B8: 125.20800000
Offset 4BC: 126.34710000
Offset 4C0: 125.42770000
Offset 4C4: 0.00000000
Offset 4C8: 0.61292310
Offset 4CC: 0.00000000
Offset 4D0: 0.86769230
Offset 4D4: 0.17784610
Offset 4D8: 0.24738460
Offset 4DC: 2.74707700
Offset 4E0: 0.49600000
Offset 4E4: 0.00000000
Offset 4E8: 0.00000000
Offset 4EC: 0.00000000
Offset 4F0: 0.00000000
Offset 4F4: 0.00000000
Offset 4F8: 0.00000000
Offset 4FC: 0.00000000
Offset 500: 0.00000000
Offset 504: 0.00000000
Offset 508: 1.26830200
Offset 50C: 0.00000000
Offset 510: 1.52297600
Offset 514: 1.06811300
Offset 518: 1.17144800
Offset 51C: 1.69550000
Offset 520: 1.22628600
Offset 524: 0.00000000
Offset 528: 197.95450000
Offset 52C: 0.00000000
Offset 530: 249.64100000
Offset 534: 105.60260000
Offset 538: 123.90650000
Offset 53C: 698.64010000
Offset 540: 210.37270000
Offset 544: 0.00000000
Offset 548: 240.92370000
Offset 54C: 0.00000000
Offset 550: 175.01290000
Offset 554: 146.10710000
Offset 558: 144.67940000
Offset 55C: 220.38580000
Offset 560: 155.67080000
Offset 564: 1.36661000
Offset 568: 0.39879780
Offset 56C: 27.75692000
Offset 570: 8.52770900
Offset 574: 19.00353000
Offset 578: 4.10006300
Offset 57C: 4.07952500
Offset 580: 0.00000000
Offset 584: 2047.00000000
Offset 588: 5.31753800
Offset 58C: 0.00000000
Offset 590: 26.03508000
Offset 594: 0.16861540
Offset 598: 0.00000000
Offset 59C: 0.99117230
Offset 5A0: 29.28314000
Offset 5A4: 0.00000000
Offset 5A8: 0.00000000
Offset 5AC: 0.00000000
Offset 5B0: 0.00000000
Offset 5B4: 0.00000000
Offset 5B8: 0.00000000
Offset 5BC: 0.00000000
Offset 5C0: 0.00000000
Offset 5C4: 0.00000000
Offset 5C8: 0.00000000
Offset 5CC: 0.00000000
Offset 5D0: 0.00000000
Offset 5D4: 0.00000000
Offset 5D8: 0.00000000
Offset 5DC: 0.00000000
Offset 5E0: 0.00000000
Offset 5E4: 0.00000000
Offset 5E8: 0.00000000
Offset 5EC: 0.00000000
Offset 5F0: 0.00000000
Offset 5F4: 0.00000000
Offset 5F8: 0.00000000
Offset 5FC: 0.00000000
Offset 600: 0.00000000
Offset 604: 0.00000000
Offset 608: 0.00000000
Offset 60C: 0.00000000
Offset 610: 0.00000000
Offset 614: 0.00000000
Offset 618: 0.00000000
Offset 61C: 0.00000000
Offset 620: 0.00000000
Offset 624: 0.00000000
Offset 628: 0.00000000
Offset 62C: 0.00000000
Offset 630: 0.00000000
Offset 634: 0.00000000
Offset 638: 0.00000000
Offset 63C: 0.00000000
Offset 640: 0.00000000
Offset 644: 0.00000000
Offset 648: 0.00000000
Offset 64C: 0.00000000
Offset 650: 0.00000000
Offset 654: 0.00000000
Offset 658: 0.00000000
Offset 65C: 0.00000000
Offset 660: 0.00000000
Offset 664: 0.00000000
Offset 668: 0.00000000
Offset 66C: 0.00000000
Offset 670: 0.00000000
Offset 674: 0.00000000
Offset 678: 0.00000000
Offset 67C: 0.00000000
Offset 680: 0.00000000
Offset 684: 0.00000000
Offset 688: 0.00000000
Offset 68C: 0.00000000
Offset 690: 0.00000000
Offset 694: 0.00000000
Offset 698: 0.00000000
Offset 69C: 0.00000000
Offset 6A0: 0.00000000
Offset 6A4: 0.00000000
Offset 6A8: 0.00000000
Offset 6AC: 0.00000000
Offset 6B0: 0.00000000
Offset 6B4: 0.00000000
Offset 6B8: 0.00000000
Offset 6BC: 0.00000000
Offset 6C0: 0.00000000
Offset 6C4: 0.00000000
Offset 6C8: 0.00000000
Offset 6CC: 0.00000000
Offset 6D0: 0.00000000
Offset 6D4: 0.00000000
Offset 6D8: 0.00000000
Offset 6DC: 0.00000000
Offset 6E0: 0.00000000
Offset 6E4: 0.00000000
Offset 6E8: 0.00000000
Offset 6EC: 0.00000000
Offset 6F0: 0.00000000
Offset 6F4: 0.00000000
Offset 6F8: 0.00000000
Offset 6FC: 0.00000000
Offset 700: 0.00000000
Offset 704: 0.00000000
Offset 708: 0.00000000
Offset 70C: 0.00000000
Offset 710: 0.00000000
Offset 714: 0.00000000
Offset 718: 0.00000000
Offset 71C: 0.00000000
Offset 720: 0.00000000
Offset 724: 0.00000000
Offset 728: 0.00000000
Offset 72C: 0.00000000
Offset 730: 0.00000000
Offset 734: 0.00000000
Offset 738: 0.00000000
Offset 73C: 0.00000000
Offset 740: 0.00000000
Offset 744: 0.00000000
Offset 748: 0.00000000
Offset 74C: 0.00000000
Offset 750: 0.00000000
Offset 754: 0.00000000
Offset 758: 0.00000000
Offset 75C: 0.00000000
Offset 760: 0.00000000
Offset 764: 0.00000000
Offset 768: 0.00000000
Offset 76C: 0.00000000
Offset 770: 0.00000000
Offset 774: 0.00000000
Offset 778: 0.00000000
Offset 77C: 0.00000000
Offset 780: 0.00000000
Offset 784: 0.00000000
Offset 788: 0.00000000
Offset 78C: 0.00000000
Offset 790: 0.00000000
Offset 794: 0.00000000
Offset 798: 0.00000000
Offset 79C: 0.00000000
Offset 7A0: 0.00000000
Offset 7A4: 0.00000000
Offset 7A8: 0.00000000
Offset 7AC: 0.00000000
Offset 7B0: 0.00000000
Offset 7B4: 0.00000000
Offset 7B8: 0.00000000
Offset 7BC: 0.00000000
Offset 7C0: 0.00000000
Offset 7C4: 0.00000000
Offset 7C8: 0.00000000
Offset 7CC: 0.00000000
Offset 7D0: 0.00000000
Offset 7D4: 0.00000000
Offset 7D8: 0.00000000
Offset 7DC: 0.00000000
Offset 7E0: 0.00000000

######################################################
SMU: Power Table Detected Values
######################################################
SmuType: TYPE_CPU3
TableVersion: 00380904
ConfiguredClockSpeed: 4000
MemRatio: 20
FCLK: 2000
MCLK: 2000
UCLK: 2000
VDDCR_SOC: 1.168667
CLDO_VDDP: 0.9090815
CLDO_VDDG_IOD: 1.074298
CLDO_VDDG_CCD: 0.9887393

######################################################
WMI: AMD_ACPI
######################################################
OK

######################################################
WMI: Instance Name
######################################################
ACPI\PNP0C14\AOD_0

######################################################
WMI: Bios Functions 1
######################################################
Get APCB Config: 00010001
Get memory voltages: 00010002
Set memory clock frequency: 00020001
Set Tcl: 00020002
Set Trcdrd: 00020003
Set Trcdwr: 00020004
Set Tras: 00020005
Set Trp: 00020006
Set ProcODT: 00020007
Set Trcpage: 00020008
Set Trc: 00020009
Set Trfc: 0002000A
Set Trfc2: 0002000B
Set Trfc4: 0002000C
Set Tfaw: 0002000D
Set TrrdS: 0002000E
Set TrrdL: 0002000F
Set Twr: 00020010
Set TwtrS: 00020011
Set TwtrL: 00020012
Set TCke: 00020013
Set Tcwl: 00020014
Set Trtp: 00020015
Set TrdrdSc: 00020016
Set TrdrdScL: 00020017
Set TrdrdSd: 00020018
Set TrdrdDd: 00020019
Set TwrwrSc: 0002001A
Set TwrwrScL: 0002001B
Set TwrwrSd: 0002001C
Set TwrwrDd: 0002001D
Set Trdwr: 0002001E
Set Twrrd: 0002001F
Set GearDownEn: 00020020
Set Cmd2t: 00020021
Set RttNom: 00020022
Set RttWR: 00020023
Set RttPark: 00020024
Set PowerDownEn: 00020025
Set SMT EN: 00020026
Software Downcore Config: 00020027
Set EDC Throttler Control: 00020028
Set AddrCmdSetup: 00020029
Set CsOdtSetup: 0002002A
Set CkeSetup: 0002002B
Set CadBusClkDrvStren: 0002002C
Set CadBusAddrCmdDrvStren: 0002002D
Set CadBusCsOdtCmdDrvStren: 0002002E
Set CadBusCkeDrvStren: 0002002F
Set CLDO_VDDP: 00020030
Set Interleave Mode: 00020031
Set Interleave Size: 00020032
Set FCLK OC Mode: 00020033
Set SOC VID: 00020034
Set FCLK Frequency: 00020035
Set CCLK Fmax: 00020036
Set GFXCLK Fmax: 00020037
Set CLDO_VDDG: 00020038
Get ECO Mode: 00020039
Set ECO Mode: 0002003A
Command Buffer Start: 00030001
Command Buffer End: 00030002
Set VDDIO: 00040001
Set VTT: 00040002

######################################################
WMI: Bios Functions 2
######################################################
Set PPT Limit: 00050001
Set TDC Limit: 00050002
Set EDC Limit: 00050003
Set Scalar: 00050004
Set DRAM Map Inversion: 00050005
Set Curve Optimizer: 0005000A
Set IOD VDDG: 0005000B
Set Soc TDC Limit: 0005000C
Set Soc EDC Limit: 0005000D
Set Dram Latency Enhance: 0005000E
Get Dram Latency Enhance: 0005000F

######################################################
SVI2: PCI Range
######################################################
0x0005A000: 0x00000006
0x0005A004: 0x00000026
0x0005A008: 0x00000002
0x0005A00C: 0x013E0023
0x0005A010: 0x011A0022
0x0005A014: 0x00000000
0x0005A018: 0x00000000
0x0005A01C: 0x0000E00E
0x0005A020: 0x00000002
0x0005A024: 0x00000000
0x0005A028: 0xEB800000
0x0005A02C: 0x00000000
0x0005A030: 0x00260000
0x0005A034: 0x00000000
0x0005A038: 0x00000000
0x0005A03C: 0x00000000
0x0005A040: 0x00000000
0x0005A044: 0x00000000
0x0005A048: 0x00000000
0x0005A04C: 0x00000000
0x0005A050: 0x26000000
0x0005A054: 0x68000000
0x0005A058: 0x3C000000
0x0005A05C: 0x68000000
0x0005A060: 0x00000000
0x0005A064: 0x00000F0A
0x0005A068: 0x00000006
0x0005A06C: 0x00000000
0x0005A070: 0x80000002
0x0005A074: 0x80000002
0x0005A078: 0x80000041
0x0005A07C: 0x80000042
0x0005A080: 0x80000042
0x0005A084: 0x00000041
0x0005A088: 0x00000000
0x0005A08C: 0x00000008
0x0005A090: 0x00000000
0x0005A094: 0x00000000
0x0005A098: 0x00000000
0x0005A09C: 0x00000000
0x0005A0A0: 0x00000000
0x0005A0A4: 0x00000000
0x0005A0A8: 0x00000000
0x0005A0AC: 0x01FF00FF
0x0005A0B0: 0x00000000
0x0005A0B4: 0x00000000
0x0005A0B8: 0x00000000
0x0005A0BC: 0x00000000
0x0005A0C0: 0x01FF00FF
0x0005A0C4: 0x00000000
0x0005A0C8: 0x00000000
0x0005A0CC: 0x00000000
0x0005A0D0: 0x00000000
0x0005A0D4: 0x01FF00FF
0x0005A0D8: 0x00000000
0x0005A0DC: 0x00000000
0x0005A0E0: 0x00000000
0x0005A0E4: 0x00000000
0x0005A0E8: 0x01FF00FF
0x0005A0EC: 0x00000000
0x0005A0F0: 0x00000001
0x0005A0F4: 0x00000001
0x0005A0F8: 0x00000000
0x0005A0FC: 0x00000000


----------



## Takla

I'm using this:
My question: Why does VDDG go to 1100mV when my SOC is set to 1050mV?


----------



## RonLazer

Takla said:


> I'm using this:
> My question: Why does VDDG go to 1100mV when my SOC is set to 1050mV?


BIOS programmers do daft stuff sometimes. See for example trying to push 1.1V VDDG_CCD on every board I've tried except the Dark Hero as soon as you go above 3733MHz.

Open question to all those tweaking their VDDGs to minimize WHEAs - have you actually checked its helping performance? From my own testing some of the voltages you guys are using are so low they would tank performance relative to the "sweet spot" voltages, so it's probably not you actually reducing WHEA incidents, just slowing down GMI link performance to the point they trigger less often?

I'll also note that even though I can tweak various input voltages at FCLK >2000MHz to recover the expected Aida64 latency - but it's a mirage, I've yet to find a way to run >2000MHz without performance falling off a cliff in any latency-bound benchmarks. It might just be that the 5600X I use to experiment sucks, but using BCLK to push the FCLK to 2033MHz for example retains performance, while directly setting the clock doesn't. 

There's a few instances of people on HWBot showing actual scaling past 2000MHz so there must be a way to trick the AGESA into not throttling performance under load at higher frequencies, but I cannot figure out how and I've exhausted the settings in CBS menu (unless some specific creative combination of settings is the key).


----------



## ManniX-ITA

RonLazer said:


> I'll also note that even though I can tweak various input voltages at FCLK >2000MHz to recover the expected Aida64 latency - but it's a mirage, I've yet to find a way to run >2000MHz without performance falling off a cliff in any latency-bound benchmarks. It might just be that the 5600X I use to experiment sucks, but using BCLK to push the FCLK to 2033MHz for example retains performance, while directly setting the clock doesn't.


Odd, I don't have any issue with memory or latency at 2033 and 2067.
AIDA benchmark and anything related to memory like GB3 scores are the most stable.
I have problems in consistency with CPU benchmarks and at 2067 in general throttling at all-core.
It's clear in GB5 where some tests sometimes drops 2.5% to 25%.
Couldn't find yet a magic voltages combo, there's always something that falls off; didn't try yet PLL above 1.96V
Some GB5 test like the Gaussian can gain up to 20% but I'm not sure how reliable it is.


----------



## KedarWolf

ManniX-ITA said:


> Odd, I don't have any issue with memory or latency at 2033 and 2067.
> AIDA benchmark and anything related to memory like GB3 scores are the most stable.
> I have problems in consistency with CPU benchmarks and at 2067 in general throttling at all-core.
> It's clear in GB5 where some tests sometimes drops 2.5% to 25%.
> Couldn't find yet a magic voltages combo, there's always something that falls off; didn't try yet PLL above 1.96V
> Some GB5 test like the Gaussian can gain up to 20% but I'm not sure how reliable it is.


Can you post your Zen Timings screenshots for 2033 and 2067?


----------



## PJVol

ManniX-ITA said:


> I'd like too! Thanks


I've pm'ed you my version, but mind you, its for single ccd cpus ("normal" 5600 & 5800). Yours most likely is 0x380804(or 5) and you can find it in this project (with a couple of my commits), in file *pm_tables.c *: (They are mostly identical, except per-core groups of 8 and 16 elements, and L3 block at the end, with groups of 1 and 2 elements respectively)








GitHub - hattedsquirrel/ryzen_monitor: Monitor power information of Ryzen processors via the PM table of the SMU


Monitor power information of Ryzen processors via the PM table of the SMU - GitHub - hattedsquirrel/ryzen_monitor: Monitor power information of Ryzen processors via the PM table of the SMU




github.com


----------



## ManniX-ITA

@Veii

AMD fixed power consumption reporting with uProf 3.4.
You can monitor power consumption live per core at 100ms interval.
Quite handy. P-State report seems to be a bit weird and it's missing C-State.
But still quite valid.
Thanks for the Power Plan, I'm learning 
Still can't find a good balance with latency and multi core which sinks.
But Core Parking has a very nice effect that I didn't see.
It's parking Core 0 and forcing single thread to Core 4 which is my best.
I'll try to find a way to use it without drawbacks.



Spoiler: uProf

















KedarWolf said:


> Can you post your Zen Timings screenshots for 2033 and 2067?


As Veii reminded, be careful with your Gen4 SSDs. Above 2000 can mess up them.

Only have one for 2033:










Was doing some testing so it's not a good one.
Especially the memory profile.
I didn't even thought I could still boot 2067.
Tried up to 1150 IOD and 1.27 VSOC but it's really unstable.

This is the one I'm using now and it's crystal perfect:













PJVol said:


> I've pm'ed you my version, but mind you, its for single ccd cpus ("normal" 5600 & 5800). Yours most likely 0x380804(or 5) and you can find it in this project (with a couple of my commits), in file *pm_tables.c *: (They are mostly identical, except per-core groups of 8 and 16 elements, and L3 block at the end, with groups of 1 and 2 elements respectively)
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - hattedsquirrel/ryzen_monitor: Monitor power information of Ryzen processors via the PM table of the SMU
> 
> 
> Monitor power information of Ryzen processors via the PM table of the SMU - GitHub - hattedsquirrel/ryzen_monitor: Monitor power information of Ryzen processors via the PM table of the SMU
> 
> 
> 
> 
> github.com


Amazing, thanks a lot.
I want to modify a bit more BoostTester so it can report the max and sustained boost clock.


----------



## PJVol

ManniX-ITA said:


> I want to modify a bit more BoostTester so it can report the max and sustained boost clock


That would be nice, though if I was making a pull request )), I'd suggest to report VID eff, Vcore(SVI2) and may be per-core power and temps (along with Tctl) as well.


----------



## Taraquin

RonLazer said:


> BIOS programmers do daft stuff sometimes. See for example trying to push 1.1V VDDG_CCD on every board I've tried except the Dark Hero as soon as you go above 3733MHz.
> 
> Open question to all those tweaking their VDDGs to minimize WHEAs - have you actually checked its helping performance? From my own testing some of the voltages you guys are using are so low they would tank performance relative to the "sweet spot" voltages, so it's probably not you actually reducing WHEA incidents, just slowing down GMI link performance to the point they trigger less often?
> 
> I'll also note that even though I can tweak various input voltages at FCLK >2000MHz to recover the expected Aida64 latency - but it's a mirage, I've yet to find a way to run >2000MHz without performance falling off a cliff in any latency-bound benchmarks. It might just be that the 5600X I use to experiment sucks, but using BCLK to push the FCLK to 2033MHz for example retains performance, while directly setting the clock doesn't.
> 
> There's a few instances of people on HWBot showing actual scaling past 2000MHz so there must be a way to trick the AGESA into not throttling performance under load at higher frequencies, but I cannot figure out how and I've exhausted the settings in CBS menu (unless some specific creative combination of settings is the key).


On my setup I've found some cliffs at 4000/2000. Anything below 1.1V soc and 1.02V iod gives me significant latency penalty. For instance trying 1.1V and 1.01V gave me 2ns higher in aida. 1.08V and 1.0V gave me 4ns. No wheas or stability issues, just perf degredation.


----------



## ManniX-ITA

PJVol said:


> That would be nice, though if I was making a pull request )), I'd suggest to report VID eff, Vcore(SVI2) and may be per-core power and temps (along with Tctl) as well.


Indeed! Thought the same.
In my version I'm doing a first quick workload to trigger max boost clock and then a longer for sustained.
Want to report the effective clock and the percentage delta against core clock to check if there's clock stretching.


----------



## PJVol

craxton said:


> im unsure if the post i linked gave all the info needed or not.
> but here is a full debug report to which im pretty sure,
> its one CCD..


As for your cores layout, I'm pretty sure it may look like this (based on debug log):
| ----- | L3 | Core0 |
| ----- | L3 | Core1 |
| Core2 | L3 | Core3 |
| Core4 | L3 | Core5 |

Don't know what can you really learn from it, but mine gave me some food for thoughts.

| Core0 | L3 | ----- |
| ----- | L3 | Core1 |
| Core2 | L3 | Core3 |
| Core4 | L3 | Core5 |

I've estimated the actual core positioning by running CBR20 single core test and cycling its affinity for each core and observing per-core temps.
Throughout the test, cores on either side of L3 block always "heat up" adjacent cores (up to 4°) , so in my case, thermally interacting cores are 2-4, 1-3 and 3-5 with Core0 sitting far enough from others to live on its own. This behavior actually helped me to understand some weirdness, regarding Curve Optimizier tuning, but thats another story...


----------



## Veii

Flash1228 said:


> Looks pretty close to my Ballistix Elite. The 3800 is what I normally use, but I've gotten both through 20 rounds of TM5 and no issues with y-cruncher. 4000 does give WHEA 19 unless I change CPU 1.8 to 2
> 
> View attachment 2511521
> View attachment 2511522
> 
> View attachment 2511523


What latency results are you getting out of this ?








Still playing and exploring
But i don't like them

They post close to everything i trow at them
And always post - but once you run TM5, the first 10sec it either passes and is stable
or you get a spam of 6-6-6-6-6 error's , someday also 0's

i feel they are slow
But this 15-15-18 set, reminds me cm87's result from CmputerBase
Looks like many people got similar results

tCWL 12 is fine on my side, but the effects are tiny
tCL 13, tCWL 12 is fine too, but i'm not justified
Going down to CL12 if i can make it
then going up to 4200

It's behaving very strange, the tRCD_RD one
as if a fixed delay is programmed to fail , while down&up-scaling is perfect for it
For any other timing it barely cares and just takes it ~ but i still dislike them. They are annoying
We'll see once i reach 53ns, then i'll consider them as a replacement ~ so far they cost the same as my b-dies, have a temp sensor, a good heatsink and a better PCB.
Sadly not interesting ICs, but at least take my RTTs well

If i could, i'd rebrand them Rev.A for "annoying" instead of Rev.E 
"Annoying" as they don't complain & take everything stupid as long as you keep CCD_L 7 in mind
Same for tFAW *7 works better than *4 on these, and tBL 7 also leads to better scores
~ but always post, nevertheless how broken your settings are. . .


Spoiler: Still testing and having fun, nothing fixed yet














* voltages where for 2100 , don't wonder
just too lazy to verify y-cruncher for lower than 2100 FCLK speeds ~ wastes too much time


----------



## craxton

PJVol said:


> As for your cores layout, I'm pretty sure it may look like this (based on debug log):
> | ----- | L3 | Core0 |
> | ----- | L3 | Core1 |
> | Core2 | L3 | Core3 |
> | Core4 | L3 | Core5 |
> 
> Don't know what can you really learn from it, but mine gave me some food for thoughts.
> 
> | Core0 | L3 | ----- |
> | ----- | L3 | Core1 |
> | Core2 | L3 | Core3 |
> | Core4 | L3 | Core5 |
> 
> I've estimated the actual core positioning by running CBR20 single core test and cycling its affinity for each core and observing per-core temps.
> Throughout the test, cores on either side of L3 block always "heat up" adjacent cores (up to 4°) , so in my case, thermally interacting cores are 2-4, 1-3 and 3-5 with Core0 sitting far enough from others to live on its own. This behavior actually helped me to understand some weirdness, regarding Curve Optimizier tuning, but thats another story...


Wow, this is super interesting, 
Perhaps now it'll get me to run core cycler.

Not only have I not, but I to have some 
Strange things with co 
Happening. Can run fine for a month no 
Issues, then poof crash WHEA 20 and 18 
When 20 hits 18 does too. 

I'm not nowhere near as full in knowledge as you fellas here. But with this info, 
There may be two cores in there just turned off.

(Running these tests, what's one thing I 
Need to watch out for?) 
Have the next two days off. So it's a good time to test.


----------



## mongoled

PJVol said:


> From your log.
> 301.88 mhz curr. perf. clock
> 284.66 mhz curr. eff. clock
> 592.59 max DPM for lclk3
> 301.88 min DPM for lclk3
> 
> PS: I've mistaken, 0x01d4 is effective clock, 1d8 and 1dc are max/min dpm state's clocks, sorry about that
> 
> I could PM you my (actually not mine initially, but I slightly revised it) estimated lables for that table, when i get to my home PC (if you want, of course)


Man thats very strange!

I copied the debug into notepad and then searched for the strings and nothing came up.

Though what I posted in the thread was a second debug which I didnt search.

Regards PM, yeah send me, not sure will do anything with it, maybe just wait out till Agesa 1.2.0.3 is released to test again.

To the topic of lowered performance when going over 2000 FCLK, sure would be helpful if we had access to AMD algorithms in making heads/tails of whats going on!

So many different results occuring depending on what is tweaked.

Example, as with yourself, PLL voltage has an effect with Agesa 1.2.0.2, i did not see the following happening on ageasa below 1.2.x.x

Running 3800/1900 using 200mhz boost clock with no CO results in around 12000 points
Running 4133/2067 using 200mhz boost clock with no CO results in around 11700 points

Now if I up PLL to my motherboard maximum (1.95v) when running 4133/2067 with no CO the score now reaches 11900 points

Running 4133/2067 using 200mhz boost clock with tuned CO and default PLL results in around 11900 points, if I then up the PLL, guess what happens, the score stays the same, no increase when using increased PLL voltage with tuned CO.

I may have got a stable 4133/2067 system that does not puke when gaming, those who remember, I already have a 25 cycle 4133/2067 TM5 stable set, but was getting games lock up with audio still playing, think ive got passed that but needs more thorough testing, currently putting it through Realbench test then some Y-Cruncher, hopefully it holds up to scrutiny.

But I cant get CB23 over 12000 with whatever tweaks I do apart from using BCLK, but that is obviously putting the system into more unknown territory.

I really wish they would bring back the option of greater boost clock override as my CPU can reach 5000 mhz as it was running with BIOS A85 (prior to agesa 1.2.x.x) ...........


----------



## Flash1228

Veii said:


> What latency results are you getting out of this ?
> View attachment 2511608
> 
> Still playing and exploring
> But i don't like them
> 
> They post close to everything i trow at them
> And always post - but once you run TM5, the first 10sec it either passes and is stable
> or you get a spam of 6-6-6-6-6 error's , someday also 0's
> 
> i feel they are slow
> But this 15-15-18 set, reminds me cm87's result from CmputerBase
> Looks like many people got similar results
> 
> tCWL 12 is fine on my side, but the effects are tiny
> tCL 13, tCWL 12 is fine too, but i'm not justified
> Going down to CL12 if i can make it
> then going up to 4200
> 
> It's behaving very strange, the tRCD_RD one
> as if a fixed delay is programmed to fail , while down&up-scaling is perfect for it
> For any other timing it barely cares and just takes it ~ but i still dislike them. They are annoying
> We'll see once i reach 53ns, then i'll consider them as a replacement ~ so far they cost the same as my b-dies, have a temp sensor, a good heatsink and a better PCB.
> Sadly not interesting ICs, but at least take my RTTs well
> 
> If i could, i'd rebrand them Rev.A for "annoying" instead of Rev.E
> "Annoying" as they don't complain & take everything stupid as long as you keep CCD_L 7 in mind
> Same for tFAW *7 works better than *4 on these, and tBL 7 also leads to better scores
> ~ but always post, nevertheless how broken your settings are. . .
> 
> 
> Spoiler: Still testing and having fun, nothing fixed yet
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> * voltages where for 2100 , don't wonder
> just too lazy to verify y-cruncher for lower than 2100 FCLK speeds ~ wastes too much time


The spam of 6s is something I'm all to familiar with lol. I've come across a lot of odds things that don't seem to abide by the 'normal' rules, like TRTP less than 12 I have errors but TWR higher than 16 is too slow which gives errors. I've always chalked a lot of it up to running 4x8GB on a daisy chain board combined with my less than expert understanding of how it all works. I can't think of any off the top of my head, but I know whilst I was trying to get 3800CL15 stable I would run into errors in TM5 that the description on the tRFC mini doc would say point to one thing and turned out to be something totally different which again I've just assumed was due to my lack of understanding something.

I can boot 2100 FCLK with a massive amount of WHEA 19s and reboots during TM5. I haven't done a lot of testing into that though as it was more of a test to see if it would even boot.


----------



## PJVol

mongoled said:


> Though what I posted in the thread was a second debug which I didnt search


My initial goal actually was to integrate it to Ivan's project, and although having little to no experience with C#, I think I could do it (when coding in classic C++, working with Qt framework in linux mostly, and at the same time with Javascript for some client-side projects, got a very strange feeling with that language  ). I've made a changes needed to one of his project files, so that debug will output labels for pm_table entries as well.
The problem is I just don't wanna ruin my windows setup by installing Visual Studio  - its huge. If someone have it, it would be an easy effort to build it with a more informative debug feature, at least for those who interested.
Posted him my changes and asked for build, but not sure he will got time to fiddle with it.
PS: pm'ed


----------



## Veii

Flash1228 said:


> The spam of 6s is something I'm all to familiar with lol. I've come across a lot of odds things that don't seem to abide by the 'normal' rules, like TRTP less than 12 I have errors but TWR higher than 16 is too slow which gives errors. I've always chalked a lot of it up to running 4x8GB on a daisy chain board combined with my less than expert understanding of how it all works. I can't think of any off the top of my head, but I know whilst I was trying to get 3800CL15 stable I would run into errors in TM5 that the description on the tRFC mini doc would say point to one thing and turned out to be something totally different which again I've just assumed was due to my lack of understanding something.
> 
> I can boot 2100 FCLK with a massive amount of WHEA 19s and reboots during TM5. I haven't done a lot of testing into that though as it was more of a test to see if it would even boot.
> 
> View attachment 2511614


I see 
I went up a bit, to fix bandwidth
Seems like hit some strange CBS option which cut me 500mb/s read and added 2ns latency more (unclear what it was, probably dimm hashing or datascramble)
Rebalanced it and it's now usable again

Goal is CL12 
I am not sure if you can somehow, but try to figure out tCCD_L
And try to use tBL 7 for everything on them
They are funny, if i hold 3 little rules, everything i trow at them is stable








I hovered by a mistake over something, but it's ok ~ only a temp save for review
Now i'll target again sub tCL 13
tCWL 12 was oke'ish , but i'm not sure what to think about it
Only tCL on this makes a good latency bump
tRAS & tRC , i mean tRC is barely really mattering on it

I started to get 800MB/s cuts when i tried to increase tRRD_S or lower tRRD_L
tFAW feels the most comfortable at 7* tRRD_S
and tRAS never broke if i use tBL 7 on it

We'll see,
So far it's a love-hate relationship with them
Soo i'm titling them as Rev.VA (Very Annoying) ^^

Also RTTs are lovely 
005 @ 1.35v with 42-43c, or 727 at 1.6v+ @ the same temp
I think i'll pick the high voltage because of lower timings
Not that tRCD would show any change whatsoever

EDIT:
You might want to fix your L3 cache or work with voltage/curve optimizer a bit
You hit 10.7 L3, while it should be 10.4
10.6ns is 4.75Ghz, unless that's CTR ~ then 10.7 is kind of alright
Still , a correct 4.85 PBO should be at 10.4ns L3
EDIT2:
Asus fMax enchancer does increase L3 cache by 0.3ns and doesn't do much to cache , nothing really positive
run 450A EDC and you have the same effect 
No need to change any scalar


----------



## Flash1228

Veii said:


> I see
> I went up a bit, to fix bandwidth
> Seems like hit some strange CBS option which cut me 500mb/s read and added 2ns latency more (unclear what it was, probably dimm hashing or datascramble)
> Rebalanced it and it's now usable again
> 
> Goal is CL12
> I am not sure if you can somehow, but try to figure out tCCD_L
> And try to use tBL 7 for everything on them
> They are funny, if i hold 3 little rules, everything i trow at them is stable
> 
> 
> 
> 
> 
> 
> 
> 
> I hovered by a mistake over something, but it's ok ~ only a temp save for review
> Now i'll target again sub tCL 13
> tCWL 12 was oke'ish , but i'm not sure what to think about it
> Only tCL on this makes a good latency bump
> tRAS & tRC , i mean tRC is barely really mattering on it
> 
> I started to get 800MB/s cuts when i tried to increase tRRD_S or lower tRRD_L
> tFAW feels the most comfortable at 7* tRRD_S
> and tRAS never broke if i use tBL 7 on it
> 
> We'll see,
> So far it's a love-hate relationship with them
> Soo i'm titling them as Rev.VA (Very Annoying) ^^
> 
> Also RTTs are lovely
> 005 @ 1.35v with 42-43c, or 727 at 1.6v+ @ the same temp
> I think i'll pick the high voltage because of lower timings
> Not that tRCD would show any change whatsoever
> 
> EDIT:
> You might want to fix your L3 cache or work with voltage/curve optimizer a bit
> You hit 10.7 L3, while it should be 10.4
> 10.6ns is 4.75Ghz, unless that's CTR ~ then 10.7 is kind of alright
> Still , a correct 4.85 PBO should be at 10.4ns L3
> EDIT2:
> Asus fMax enchancer does increase L3 cache by 0.3ns and doesn't do much to cache , nothing really positive
> run 450A EDC and you have the same effect
> No need to change any scalar


I'll change the EDC to 450 and see how that goes. I've got fmax off and CO I've done per core as low I can pass core cycler and y-cruncher without errors. 

I'm not sure what tCCD_L and tBL are as I don't see them in zentiminings. Unless I'm missing something?


----------



## Veii

Flash1228 said:


> I'll change the EDC to 450 and see how that goes. I've got fmax off and CO I've done per core as low I can pass core cycler and y-cruncher without errors.
> 
> I'm not sure what tCCD_L and tBL are as I don't see them in zentiminings. Unless I'm missing something?


ASUS SPD Info , in the bios should report it - and usually all other SPD reading softwares
Zentimings misses this
tBL is something that is not reported sadly


----------



## Flash1228

Veii said:


> ASUS SPD Info , in the bios should report it - and usually all other SPD reading softwares
> Zentimings misses this
> tBL is something that is not reported sadly


Changing EDC to 450 makes no difference in L3 latency and tCCD_L is 7 for JEDEC and shows nothing under XMP.

You're seeing better results with tFAW=tRRDS*7?


----------



## RonLazer

Taraquin said:


> On my setup I've found some cliffs at 4000/2000. Anything below 1.1V soc and 1.02V iod gives me significant latency penalty. For instance trying 1.1V and 1.01V gave me 2ns higher in aida. 1.08V and 1.0V gave me 4ns. No wheas or stability issues, just perf degredation.


Aida64 is not a real benchmark though, it's a few seconds of synthetic memory buffering with no accompanying core load. You'd need a real workload like Linpack Extreme, HWBot x265, or game benchmarks, to see if it's actually improving anything. 

I've been pushing my 5600X well into unstable territory for the HWBot SuperPi 32M low-clock challenge, and what settings perform best in highly synthetic, single-threaded, low memory usage applications is absolutely not correlated with what performs best in "real" workloads. If this thread is just "how low can we get Aida64 latency while passing tm5" then sure that's fine, but I can't see any value to that for 24/7 applications. 

Perhaps it would be useful to collect up the immense amount of valuable technical information scattered through this thread and start a separate "Ryzen Memory Overclocking Theory" thread? Mixing highly technical discussions that serve little to no useful purpose for the average user, with people trying to get help stabilizing very basic overclocks stable seems counter-productive?


----------



## Eder

new realtek lan drivers on tweaktown forum. Not shur it helps with whea19


----------



## RonLazer

Eder said:


> new realtek lan drivers on tweaktown forum. Not shur it helps with whea19


Actually that reminds me,@Veii is the problematic chip you identified connected via the chipset? Because my motherboard has the possibility to entirely disable the chipset link, so if I got an NVMe SSD I could test this theory by not using any chipset devices.


----------



## Veii

RonLazer said:


> Actually that reminds me,@Veii is the problematic chip you identified connected via the chipset? Because my motherboard has the possibility to entirely disable the chipset link, so if I got an NVMe SSD I could test this theory by not using any chipset devices.


It is, chipset links where the issue and the main reason for the whole rewrites and balancing 
you can try 

Same strange issue here, got my first WHEA 19 without really a reason
but the only holding points i have was a random windows update & an elgato pcie x4 capture card plugged into the bottom link slot
Probably an AMD CBS thing - but i haven't had anything since then 

It's questionable at best, what really triggers it
Just knowing i got one randomly too - means there is an active issue about it
Just WHEA 19 can be many things, not only one ~ but IO it's for sure


----------



## ManniX-ITA

RonLazer said:


> I've been pushing my 5600X well into unstable territory for the HWBot SuperPi 32M low-clock challenge, and what settings perform best in highly synthetic, single-threaded, low memory usage applications is absolutely not correlated with what performs best in "real" workloads. If this thread is just "how low can we get Aida64 latency while passing tm5" then sure that's fine, but I can't see any value to that for 24/7 applications.


For sure that's a bit of competition spirit in posting the AIDA benchmarks.
But mostly it's because there's not much alternative as a quick check.
If you have a better solution to propose feel free 
As a small side-project I'll make a better boosttester but about benchmarks I wouldn't know where to start.
There's some free code on Github that could be partially reused but I would end up doing mostly random stuff.


----------



## lmfodor

ManniX-ITA said:


> @Veii
> 
> AMD fixed power consumption reporting with uProf 3.4.
> You can monitor power consumption live per core at 100ms interval.
> Quite handy. P-State report seems to be a bit weird and it's missing C-State.
> But still quite valid.
> Thanks for the Power Plan, I'm learning
> Still can't find a good balance with latency and multi core which sinks.
> But Core Parking has a very nice effect that I didn't see.
> It's parking Core 0 and forcing single thread to Core 4 which is my best.
> I'll try to find a way to use it without drawbacks.
> 
> 
> 
> Spoiler: uProf
> 
> 
> 
> 
> View attachment 2511567
> 
> 
> 
> 
> 
> 
> As Veii reminded, be careful with your Gen4 SSDs. Above 2000 can mess up them.
> 
> Only have one for 2033:
> 
> View attachment 2511569
> 
> 
> Was doing some testing so it's not a good one.
> Especially the memory profile.
> I didn't even thought I could still boot 2067.
> Tried up to 1150 IOD and 1.27 VSOC but it's really unstable.
> 
> This is the one I'm using now and it's crystal perfect:
> 
> View attachment 2511570
> 
> 
> 
> 
> 
> Amazing, thanks a lot.
> I want to modify a bit more BoostTester so it can report the max and sustained boost clock.


Hi @ManniX-ITA!!!

It seems that the cause of my BSOD was the riser cable 4.0 from linkup. Because already tired of so many BSODs, which occurred just playing, I ended up thinking that it was something from the GPU, since I don't use OC with the 3080, I deactivated PBO and put the memories in XMP, the BSOD happened again, so I immediately thought that is the cable. I had not other option. Now my son is in a game marathon to see if he is stable. I hope that's it! On the other hand, I was just going to buy another mobo without the realtek NIC, but I'd rather wait to see if they do something to fix it. With a friend I did the I change the mobo for a Dark Hero that he didn’t use it, so now I am with this new one that the truth is very different how it behaves with the memory OC. It's like the training was more permissive and something that surprised me a lot is that the retry button works excellently, in the Wi-Fi version it almost never retried, it was like a reset. Now it shuts down, try once, twice and three times, and then goes to BIOS. And the Safe boot too, I enter Windows without problems or BIOS .. I'm going to try modifying the memory training that was optimized by Veii 

About your new secure timings in 4000/2000, I am going to test them. My only doubt is the RTT Park in 1 with 1.56v. Is that safe? For DR the best combination of RTTs that I saw is 0/3/1, but I don't know if for higher voltage a 0/3/3 would be better .. 

if one modifies the RTT values in ohms, one should adjust the difference with the Cad Bus or ProcODT? I mean, if one has a stable configuration with a voltage and x ohms composed by the RTTs plus the proctODT plus the cad bus, the sum of all these should accompany the voltage rise, right? It is always the part that is most difficult for me to accommodate 

Finally, the Dark Hero came with the SMU 56.37, well, should I stay in such an old version because of the L3 cache or to go to 4000/2000 is the last one better? asus has not yet released the final of 1.2.0.2 .. continue with the beta version of April 

Thanks [emoji4] 


Sent from my iPhone using Tapatalk Pro


----------



## Yviena

Setting edc on my x570 tomahawk for 1000gb/s L3 eems to break boosting.


----------



## jomama22

Yviena said:


> Setting edc on my x570 tomahawk for 1000gb/s L3 eems to break boosting.


I don't recommend super high edc as it ruins your boost. Don't think it's worth sacrificing just for more l3 bandwidth.



Veii said:


> I see
> I went up a bit, to fix bandwidth
> Seems like hit some strange CBS option which cut me 500mb/s read and added 2ns latency more (unclear what it was, probably dimm hashing or datascramble)
> Rebalanced it and it's now usable again
> 
> Goal is CL12
> I am not sure if you can somehow, but try to figure out tCCD_L
> And try to use tBL 7 for everything on them
> They are funny, if i hold 3 little rules, everything i trow at them is stable
> 
> 
> 
> 
> 
> 
> 
> 
> I hovered by a mistake over something, but it's ok ~ only a temp save for review
> Now i'll target again sub tCL 13
> tCWL 12 was oke'ish , but i'm not sure what to think about it
> Only tCL on this makes a good latency bump
> tRAS & tRC , i mean tRC is barely really mattering on it
> 
> I started to get 800MB/s cuts when i tried to increase tRRD_S or lower tRRD_L
> tFAW feels the most comfortable at 7* tRRD_S
> and tRAS never broke if i use tBL 7 on it
> 
> We'll see,
> So far it's a love-hate relationship with them
> Soo i'm titling them as Rev.VA (Very Annoying) ^^
> 
> Also RTTs are lovely
> 005 @ 1.35v with 42-43c, or 727 at 1.6v+ @ the same temp
> I think i'll pick the high voltage because of lower timings
> Not that tRCD would show any change whatsoever
> 
> EDIT:
> You might want to fix your L3 cache or work with voltage/curve optimizer a bit
> You hit 10.7 L3, while it should be 10.4
> 10.6ns is 4.75Ghz, unless that's CTR ~ then 10.7 is kind of alright
> Still , a correct 4.85 PBO should be at 10.4ns L3
> EDIT2:
> Asus fMax enchancer does increase L3 cache by 0.3ns and doesn't do much to cache , nothing really positive
> run 450A EDC and you have the same effect
> No need to change any scalar


Personally have had 0 change in l3 latency with fmax enhancer (stays at 9.9ns @ 5100) but bandwidth is much higher during pbo usage (1500+ on my 5950x) and this is with 1.8.0.0, before the cache boost of later agesa's.


----------



## Veii

jomama22 said:


> nd this is with 1.8.0.0, before the cache boost of later agesa's.


"Cache Boost" exists since the ABL on 1.1.0.0 patch D
which was ported to Pattch-C before it got public
Patch-D needed time to be released

EDC boost only ruins your boost if you overvoltage
Alone enabling PBO does overvolt it a bit, lifting the limits does it more


----------



## DeletedMember558271

RonLazer said:


> Actually that reminds me,@Veii is the problematic chip you identified connected via the chipset? Because my motherboard has the possibility to entirely disable the chipset link, so if I got an NVMe SSD I could test this theory by not using any chipset devices.


What board do you have that has this feature? Kinda interesting


----------



## jomama22

Veii said:


> "Cache Boost" exists since the ABL on 1.1.0.0 patch D
> which was ported to Pattch-C before it got public
> Patch-D needed time to be released
> 
> EDC boost only ruins your boost if you overvoltage
> Alone enabling PBO does overvolt it a bit, lifting the limits does it more


Right, and I know the DH 1.1.8.0 (3003) does not have cache boost/pbo l3 aida fix for pbo implemented in it. If you are referring to the boost for allcore OCs of 5900/5950x's, that is indeed in there.

Bit confused what you're saying in that last bit. If you use PBO and set edc too high, you will lose performance, mostly on heavy multicore workloads. Single core and light loads aren't affected as much but you will see the affects in cpu benchmarks.

It's a balancing act of sorts but I don't think it makes a ton of sense to forgo cpu performance for aida l3 bandwidth readings.

Btw, if you have a DH, or know someone who uses one and pbo, I highly suggest using DOS with fmax enhancer enabled. It actually opens PBO up and essentially does an edc 0 bug just like the 3000 series. It does not work in this way without DOS enabled so you can't compare the two. You can set the crossover limit to 250A to basically only even use PBO (except in extreme circumstances). Doing this will fully ignore edc values all together while still allowing CO to be effective, actually even more so.


----------



## Yviena

Veii said:


> "Cache Boost" exists since the ABL on 1.1.0.0 patch D
> which was ported to Pattch-C before it got public
> Patch-D needed time to be released
> 
> EDC boost only ruins your boost if you overvoltage
> Alone enabling PBO does overvolt it a bit, lifting the limits does it more


My behavior seems to be different just changing EDC to 500-1000 to get 1000gb/s L3 cache seems to cap R23 mutli thread to around 3900mhz and voltage around 1.15-1.20.


----------



## RonLazer

Dreamic said:


> What board do you have that has this feature? Kinda interesting


Dark Hero! Although its called "Promontory Presence" for some reason, I can never fathom why BIOS programmers refuse to give anything a useful name.

@Veii I don't think your theory about WHEAs being caused by the Realtek chip holds water (open to evidence to prove otherwise though!). I was just looking at the WHEA 19 Events and I noticed the Memory Hierarchy Level is "3", which according to the Windows hierarchy map is the L3 cache. WHEA 18s (caused by undervolting, usually curve-optimiser being too low) usually report level 0 which is the CPU registers, and sometimes level 1 (instruction cache), which is exactly what you'd expect if the error was occurring in the CPU cores. An L3 cache error implies it was caught by the GMI bus ECC mechanism before passing through the CPU cores or the L1/L2 cache. Now this could well be faulty data from a malfunctioning chip, but the CBS settings indicate that the MCA uses error thresholding and the default is set to 10, although I'm not sure how often it triggers, but you can increase it up to 4094 I think. A high memory intensity workload would be flooding the L3 cache with data, and if some of it was getting corrupted in the transfer (due to unstable link speeds) then that would exceed the MCA error threshold and trigger a PIE event which is reported to the OS. The AMD documentation points suggests this is the error:










So yeh, this might be a case of Occams Razer. The simplest explanation is the infinity fabric is clocked too high and data sent along the bus is getting corrupted. It's likely happening in normal operation, but rarely enough to stay below the MCA error threshold so it doesn't get reported. 

I maintain that the root of the problem is due to the link-equalisation mechanism, where AMD/Hypertransport developed a protocol for synchronising the IF-PHY bridge interface up to 1900MHz (which appears to have been its maximum design spec), slapped together something functional but imperfect for 1900-2000MHz range in time for Zen3, but ultimately couldn't even get it to reliably synchronize until AGESA 1.1.8, decided it wasn't worth sinking extra effort into trying to push the link-equalisation past 2000MHz and so any higher frequencies re-use the protocol for 2000MHz. Maybe some chips have a remarkably stable interconnect and can function outside the specified range, but there's no hope of finding the hidden settings that will unlock performance outside this range. Maybe they will update the AGESA at some point to improve the IF-PHY training algorithm, but I wouldn't hold my breath.


----------



## Toddimus

RonLazer said:


> Dark Hero! Although its called "Promontory Presence" for some reason, I can never fathom why BIOS programmers refuse to give anything a useful name.
> 
> @Veii I don't think your theory about WHEAs being caused by the Realtek chip holds water (open to evidence to prove otherwise though!). I was just looking at the WHEA 19 Events and I noticed the Memory Hierarchy Level is "3", which according to the Windows hierarchy map is the L3 cache. WHEA 18s (caused by undervolting, usually curve-optimiser being too low) usually report level 0 which is the CPU registers, and sometimes level 1 (instruction cache), which is exactly what you'd expect if the error was occurring in the CPU cores. An L3 cache error implies it was caught by the GMI bus ECC mechanism before passing through the CPU cores or the L1/L2 cache. Now this could well be faulty data from a malfunctioning chip, but the CBS settings indicate that the MCA uses error thresholding and the default is set to 10, although I'm not sure how often it triggers, but you can increase it up to 4094 I think. A high memory intensity workload would be flooding the L3 cache with data, and if some of it was getting corrupted in the transfer (due to unstable link speeds) then that would exceed the MCA error threshold and trigger a PIE event which is reported to the OS. The AMD documentation points suggests this is the error:
> 
> View attachment 2511661
> 
> 
> So yeh, this might be a case of Occams Razer. The simplest explanation is the infinity fabric is clocked too high and data sent along the bus is getting corrupted. It's likely happening in normal operation, but rarely enough to stay below the MCA error threshold so it doesn't get reported.
> 
> I maintain that the root of the problem is due to the link-equalisation mechanism, where AMD/Hypertransport developed a protocol for synchronising the IF-PHY bridge interface up to 1900MHz (which appears to have been its maximum design spec), slapped together something functional but imperfect for 1900-2000MHz range in time for Zen3, but ultimately couldn't even get it to reliably synchronize until AGESA 1.1.8, decided it wasn't worth sinking extra effort into trying to push the link-equalisation past 2000MHz and so any higher frequencies re-use the protocol for 2000MHz. Maybe some chips have a remarkably stable interconnect and can function outside the specified range, but there's no hope of finding the hidden settings that will unlock performance outside this range. Maybe they will update the AGESA at some point to improve the IF-PHY training algorithm, but I wouldn't hold my breath.


Good analysis. It does sound plausible and even probable. Having said that, so does @Veii;’s explanation. I don’t necessarily think they are mutually exclusive and in fact could be synergistic. 

I’m just shooting from the hip though. I only know enough about this stuff to be dangerous. [emoji851]


Sent from my iPhone using Tapatalk


----------



## ManniX-ITA

jomama22 said:


> Bit confused what you're saying in that last bit. If you use PBO and set edc too high, you will lose performance, mostly on heavy multicore workloads. Single core and light loads aren't affected as much but you will see the affects in cpu benchmarks.
> 
> It's a balancing act of sorts but I don't think it makes a ton of sense to forgo cpu performance for aida l3 bandwidth readings.


I also start loosing performances with high EDC, at best I don't get nothing.
What is really killing my multi-core is high TDC.
The slight under-volting like many are doing it's causing a massive clock stretching.
Reducing EDC to 180A has a very positive effect on gaming with my 5950x but it's killing multi-core.

In-game benchmarks are all showing zero gain with high L3 speed, have still to run some other real workload but I don't hold my breath.
It's nice on Sandra and AIDA for now, that's all.



RonLazer said:


> I was just looking at the WHEA 19 Events and I noticed the Memory Hierarchy Level is "3", which according to the Windows hierarchy map is the L3 cache.


@Veii can be wrong or right but also partially right. We just don't know until proven.
My feeling is there are many concurrent reasons but the Realtek issue could be the n.1 for severity or lead to the root cause.

I think you are just wrong with your analysis, good try but flawed for these reasons:

You trust the error and the information inside, which is a wrong assumption
You trust the WHEA error reporting reliability
You didn't check the Error Source type
The theory, which is proven by empirical testing with performance and stress tests, is these errors are all or most of them just bogus.
If they are not, you will get crashes, reboots, performances sinking.
It's not that hard to verify; those a bit old here did it for years before WHEA was a thing.
*Who's not brave enough to overclock, that doesn't feel to be a tough guy, should not attempt such a perilous road.

Considering there's empirical evidence that these WHEA are not right, why you trust the information inside?*
There's no evidence that says it's right, more that it's not.
Very often alarms can be misleading as they are not reported correctly or are completely fake.
It's the biggest risk in implementing a sophisticated error reporting capability in a complex system.
I felt the pain very often in my professional life with geographical disaster procedures kicking in because of nothing...
One wrong comma somewhere and a whole platform switching data centers.

If I disable the WHEA Source for the high data rate flow of Error 19, I still get some spurious errors from other sources.
I can't map them to anything as I usually can when something is wrong.
*My conclusion is that when this high flow data rate starts bogging the system the whole WHEA error reporting system starts failing.*
It's my theory but again is proven by empirical evidence.

*You can make some reverse empirical testing and try to force a real instability to watch the behavior.*
Try undervolting like a boss VDDG and SOC and start Prime95 Small FFT.
At some point you'll get to the point where it will start dropping Error 19.
More down you go and more frequent the WHEA 19, maybe some 18.
If you get to the right point it will start dropping frequent 19.
After a steady stream of Error 19, those from a real CPU instability, the system will reboot.
That's the behavior I do expect from a steady flow of just 1-2 per second WHEA 19.
And it doesn't match with the behavior of hundreds per seconds I see going over FCLK 1900.

*The main reason why I released WHEAService relies in the Error Source type of these WHEA 19.*
The high flow data rate is very likely not coming from the CPU.

This is the Error Source types mapping on my machine, it's not the same on all but the first sources are often the same:

*WHEA Error Sources details:

ErrorSourceId: 0 Type: WheaErrSrcTypeDeviceDriver = 0x10, Device Driver Error Source
ErrorSourceId: 1 Type: WheaErrSrcTypeMCE = 0x00, Machine Check Exception
ErrorSourceId: 2 Type: WheaErrSrcTypeCMC = 0x01, Corrected Machine Check
ErrorSourceId: 3 Type: WheaErrSrcTypeNMI = 0x03, Non-Maskable Interrupt
ErrorSourceId: 4 Type: WheaErrSrcTypeBOOT = 0x07, BOOT Error Source*

The high flow data rate is not coming from the Error Source 1,2,3 like it should if it was from the CPU.

This is a legitimate Error 18:










Error source is 3, *Non-Maskable Interrupt*.

This is a WHEA Error 19 from the high data rate flow:










Error source is 0, *Device Driver Error Source*.

*The Device Driver error source can be literally anything.*
You can compile a driver with the NDK which has the sole function of just outputting WHEA Error 19 for that source with random info inside 

These errors can come from the IO die, the Realtek NIC, whatever has a driver, also the CPU.

Unfortunately WHEA, as many of the Microsoft stuff, sucks badly.
I couldn't find how to really understand *who sent the error*.

*I don't trust this error reliability and the whole WHEA error reporting system in any form once it's triggered by high FCLK.*

What I trust more is my old method of testing which is telling me otherwise; my system is running fine.

And my eyes, since it's been a week (I want to cry 5 minutes in a corner for this) that *I don't see a single USB issue for the first time.*
I've been plagued with USB issues since the first day I bought the 3800x.

_*Instead of observing a system borderline stable I'm seeing a system more reliable than at FCLK 1900.*_
*It doesn't fit at all to what the WHEA error reporting is telling me.*

Plus of course months of testing and benching on my the Win2GO USB install.
Zero issues.
I do get performance degradation over FCLK 2000 while it was over 2033 with older AGESA.
That's all.

Everyone has the freedom to test it on its own skin now, no complaints if it doesn't work.


----------



## mongoled

lmfodor said:


> I was just going to buy another mobo without the realtek NIC, but I'd rather wait to see if they do something to fix it


Dont get fixated on the Realtek "issue" as you will most likely be disappointed once you invest in a motherboard without Realtek to only find you still have the same WHEA warnings.



RonLazer said:


> I maintain that the root of the problem is due to the link-equalisation mechanism, where AMD/Hypertransport developed a protocol for synchronising the IF-PHY bridge interface up to 1900MHz (which appears to have been its maximum design spec), slapped together something functional but imperfect for 1900-2000MHz range in time for Zen3, but ultimately couldn't even get it to reliably synchronize until AGESA 1.1.8, decided it wasn't worth sinking extra effort into trying to push the link-equalisation past 2000MHz and so any higher frequencies re-use the protocol for 2000MHz. Maybe some chips have a remarkably stable interconnect and can function outside the specified range, but there's no hope of finding the hidden settings that will unlock performance outside this range. Maybe they will update the AGESA at some point to improve the IF-PHY training algorithm, but I wouldn't hold my breath.


This is also my general consensus, makes logical thinking and follows how things are done in the industry which we can see from following historical trends.

@ManniX-ITA 
Although your points are valid, you should also point out what is "right" about what RonLazer has said and primarily the key point is what frequency AMD designed the fabric to function to. This frequency has been confirmed by AMD.

Its all well and good saying



> You trust the error and the information inside, which is a wrong assumption
> You trust the WHEA error reporting reliability
> You didn't check the Error Source type




But we need to have some sort of baseline information to work from and that baseline information comes from the tools that have been designed by those people who are responsible for bringing these technologies to us.

Your third point above is a paradox as you say we cant trust number 1 and 2 so what point is there in checking the "Error Source Type" if 1 and 2 above are "invalid" ?


----------



## ManniX-ITA

mongoled said:


> Although your points are valid, you should also point out what is "right" about what RonLazer has said and primarily the key point is what frequency AMD designed the fabric to function to. This frequency has been confirmed by AMD.


It's another theory, he could be right or not.
Only AMD could confirm or not, knows really what is the success rate of Zen 3 going over FCLK 1900.

It is the most obvious explanation also for me.
But there are 2 points that should be considered.
First is that AMD brazenly declared that FCLK 2000 would be the new reference for Zen 3, just like FCLK 1900 was for Zen 2.
If you are familiar with silicon vendors that's quite exceptional.
They never declare they can go over the specs without a massive validation data behind to back it.
Second is that my 5950x works fine at FCLK 2000, even better.
Which makes me think they were right in their statement but something else is broken.



mongoled said:


> Your third point above is a paradox as you say we cant trust number 1 and 2 so what point is there in checking the "Error Source Type" if 1 and 2 above are "invalid" ?


No, it's not a paradox.

The Error Source is telling you from where the error is coming from.
The fact that these constant Error 19 are coming from the Device Driver source is relevant and it's the only reliable information.

Point 2 is that what you get after that could be unreliable as well; I can't map it to real issues.

Point 1 is that considering Point 2, you can't guarantee the information is correct or relevant.
Plus since the source could be very well not the CPU, the L3 mapping or any other decoding could be a wrong assumption.
The L3 cache hierarchy could be pertaining the Realtek NIC SoC architecture, the motherboard chipset, really anything.


----------



## mongoled

ManniX-ITA said:


> First is that AMD brazenly declared that FCLK 2000 would be the new reference for Zen 3, just like FCLK 1900 was for Zen 2.


Could you link where this was said?

What I remember is Robert Hallock saying that some samples would be able to run 2000 mhz, just as they said with the previous 1900 mhz ceiling. Myself personally, I would not quantify neither the 1900 mhz nor the 2000 mhz a baseline that is achievable for most people and this is backed by the number of people who struggle to hit 1900 mhz just as those of us who stuggle to hit 2000 mhz ...



ManniX-ITA said:


> No, it's not a paradox.
> 
> The Error Source is telling you from where the error is coming from.
> The fact that these constant Error 19 are coming from the Device Driver source is relevant and it's the only reliable information.


I am not wanting to be counter arguing, I just want you to apply the same logic you applied when breaking down RonLazer post, you are making an assumption just as RonLazer made (which is perfectly fine if that is what you want to truly believe) the assumption that the driver source is relevant, but who to say this is "fact" ??


----------



## ManniX-ITA

mongoled said:


> Could you link where this was said?
> 
> What I remember is Robert Hallock saying that some samples would be able to run 2000 mhz, just as they said with the previous 1900 mhz ceiling.


I don't remember where it was.
It's that quote from Robert Hallock, I think he said most not some samples.
He defined it as the new ceiling for Zen 3 just like 1900 was for Zen 2.
The exact number is not relevant, it's relevant he said it.
He could have very well shut up or said it's going to be same as Zen 2 the ceiling, 1900.



mongoled said:


> I am not wanting to be counter arguing, I just want you to apply the same logic you applied when breaking down RonLazer post, you are making an assumption just as RonLazer made (which is perfectly fine if that is what you want to truly believe) the assumption that the driver source is relevant, but who to say this is "fact" ??


Of course my theory and I may be wrong, I'm making a lot of assumptions as well 
The fact is that the error source is a driver and not those which are only used to report CPU errors.
I mean WHEA could be so messed up to mix up the error sources as well but I think that's extremely unlikely...

The main point is empirical testing; how the system is behaving?
Just like when a doctor is getting a patient with a psychosomatic illness.
Is there really a stomach issue or it's just his mind imagining it?
You have to deduct from observation or you will end up doing worst trying to fix something which is well.

All this struggling diagnosing these errors could be a waste of time and opportunities.
If you are brave enough, test it and if it works use it, otherwise don't 

Don't get me wrong, I like that Ron is digging into it and you are counter arguing.
How boring would be without it...
It's the main reason we are here and enjoy the discussions.
Otherwise I would just have disabled WHEA for myself and not care about anyone else.


----------



## mongoled

ManniX-ITA said:


> I don't remember where it was.
> It's that quote from Robert Hallock, I think he said most not some samples.
> He defined it as the new ceiling for Zen 3 just like 1900 was for Zen 2.
> The exact number is not relevant, it's relevant he said it.
> He could have very well shut up or said it's going to be same as Zen 2 the ceiling, 1900.
> 
> 
> 
> Of course my theory and I may be wrong, I'm making a lot of assumptions as well
> The fact is that the error source is a driver and not those which are only used to report CPU errors.
> I mean WHEA could be so messed up to mix up the error sources as well but I think that's extremely unlikely...
> 
> The main point is empirical testing; how the system is behaving?
> Just like when a doctor is getting a patient with a psychosomatic illness.
> Is there really a stomach issue or it's just his mind imagining it?
> You have to deduct from observation or you will end up doing worst trying to fix something which is well.
> 
> All this struggling diagnosing these errors could be a waste of time and opportunities.
> If you are brave enough, test it and if it works use it, otherwise don't
> 
> Don't get me wrong, I like that Ron is digging into it and you are counter arguing.
> How boring would be without it...
> It's the main reason we are here and enjoy the discussions.
> Otherwise I would just have disabled WHEA for myself and not care about anyone else.


Its great that there are many of us here who are of the same mindset, specifically this point you made



> Don't get me wrong, I like that Ron is digging into it and you are counter arguing.
> How boring would be without it...
> It's the main reason we are here and enjoy the discussions


 

I also diagnose like a "doctor" my diagnosis is more matching RonLazer previous statement.

For me, its as if we are having to balance several different voltages to get stable results across a broad range of applications, where one set of voltage combinations work for a TM5 workload, that same set of combinations does not work with another work load such as Realbench etc.

I tweak the most when the system is at the edge of stability, as this way its easier to see the effects of any changes made.

Have been tweaking 4133/2067 for the past two days and still cannot get a "handle" on what settings to use to be stable across all applications.

So far I have one set of settings that are fine for memory intensive applications and another set of settings for gaming applications, I am so far unable to balance both out.

Its looking I am going to have to back off to 4066/2033 and start tweaking from there, 4000/2000 is non postable (07 error) on my sample...


----------



## Takla

ManniX-ITA said:


> First is that AMD brazenly declared that FCLK 2000 would be the new reference for Zen 3, just like FCLK 1900 was for Zen 2.


IIRC, they said 2000 fclk on zen 3 would be what 1900 fclk on zen 2 was. That is, with luck you might get it. And I think they only ever commented on this as an "icing on the cake" type of thing, to get people that care about this sort of niche min/maxing hyped.


----------



## ManniX-ITA

mongoled said:


> Its looking I am going to have to back off to 4066/2033 and start tweaking from there, 4000/2000 is non postable (07 error) on my sample...


Wow, first time I heard.
Did you check if works with memory in de-sync?
Could be also an issue with timings in my experience, although quite rare.



Takla said:


> IIRC, they said 2000 fclk on zen 3 would be what 1900 fclk on zen 2 was. That is, with luck you might get it. And I think they only ever commented on this as an "icing on the cake" type of thing, to get people that care about this sort of niche min/maxing hyped.


Indeed, what's valuable to me is that they commented on it.
Like all the silicon vendors the answer is usually: no comment.

Just like their answer on the B2 stepping.
A real classic.
Got the same answer from another silicon vendor about a SoC new cut.
I'm still angry.
6 months later I found out there were functional differences, bug fixes and an overclock.
But of course after 6 months there was no way to change the SoC in the project.
When there's such a bold statement it's very likely behind they have run a massive validation and still being pessimistic.


----------



## mongoled

ManniX-ITA said:


> Wow, first time I heard.
> Did you check if works with memory in de-sync?
> Could be also an issue with timings in my experience, although quite rare.


Tested extensivly,

my current CPU sample regards to FCLK is as follows

1900 mhz perfect, error free, post everytime, no issues
1933 mhz, posts 50% of the time, thousands of WHEA 19s, stable whatever I throw at it
1966/2000 mhz, no post 07 error, nothing can get past these holes
2033 mhz, posts 70% of the time, thousands of WHEA 19s, not played with this FCLK
2066 mhz, posts 90% of the time, thousands of WHEA 19s, not got to 100% stability ..

I have also tested four other 5600x, each one had different FLCK holes.

In total 5 5600x, four from the same batch.


----------



## Taraquin

Finding out if this is a MB and/or CPU/IO-die issue shouldn't be to hard. If you get wheas on one MB, test with 1 or 2 more CPUs and still get problems, the CPU is most likely to blame. If you swap MB and issues with same CPU disappears it's likely the MB. I know some of you have done this, and it seems like there in some cases is a combo of both. 

Technically, even if this is a MB or CPU-problem there isn't much you can demand as AMD only guarantees 3200/1600 and it seems like viritually none has wheas below 3600/1800. It's an entusiast only issue. Annoying? Yes and if fixable with a new bios the AMD should do it asap, but specwise they never promised 3800/1900+ for all. On my 3600 I could do 1866 fclk easy, but 1900 was impossible and I could live with that.


----------



## craxton

ManniX-ITA said:


> I also start loosing performances with high EDC, at best I don't get nothing.
> What is really killing my multi-core is high TDC.
> The slight under-volting like many are doing it's causing a massive clock stretching.
> Reducing EDC to 180A has a very positive effect on gaming with my 5950x but it's killing multi-core.
> 
> In-game benchmarks are all showing zero gain with high L3 speed, have still to run some other real workload but I don't hold my breath.
> It's nice on Sandra and AIDA for now, that's all.
> 
> 
> 
> @Veii can be wrong or right but also partially right. We just don't know until proven.
> My feeling is there are many concurrent reasons but the Realtek issue could be the n.1 for severity or lead to the root cause.
> 
> I think you are just wrong with your analysis, good try but flawed for these reasons:
> 
> You trust the error and the information inside, which is a wrong assumption
> You trust the WHEA error reporting reliability
> You didn't check the Error Source type
> The theory, which is proven by empirical testing with performance and stress tests, is these errors are all or most of them just bogus.
> If they are not, you will get crashes, reboots, performances sinking.
> It's not that hard to verify; those a bit old here did it for years before WHEA was a thing.
> *Who's not brave enough to overclock, that doesn't feel to be a tough guy, should not attempt such a perilous road.
> 
> Considering there's empirical evidence that these WHEA are not right, why you trust the information inside?*
> There's no evidence that says it's right, more that it's not.
> Very often alarms can be misleading as they are not reported correctly or are completely fake.
> It's the biggest risk in implementing a sophisticated error reporting capability in a complex system.
> I felt the pain very often in my professional life with geographical disaster procedures kicking in because of nothing...
> One wrong comma somewhere and a whole platform switching data centers.
> 
> If I disable the WHEA Source for the high data rate flow of Error 19, I still get some spurious errors from other sources.
> I can't map them to anything as I usually can when something is wrong.
> *My conclusion is that when this high flow data rate starts bogging the system the whole WHEA error reporting system starts failing.*
> It's my theory but again is proven by empirical evidence.
> 
> *You can make some reverse empirical testing and try to force a real instability to watch the behavior.*
> Try undervolting like a boss VDDG and SOC and start Prime95 Small FFT.
> At some point you'll get to the point where it will start dropping Error 19.
> More down you go and more frequent the WHEA 19, maybe some 18.
> If you get to the right point it will start dropping frequent 19.
> After a steady stream of Error 19, those from a real CPU instability, the system will reboot.
> That's the behavior I do expect from a steady flow of just 1-2 per second WHEA 19.
> And it doesn't match with the behavior of hundreds per seconds I see going over FCLK 1900.
> 
> *The main reason why I released WHEAService relies in the Error Source type of these WHEA 19.*
> The high flow data rate is very likely not coming from the CPU.
> 
> This is the Error Source types mapping on my machine, it's not the same on all but the first sources are often the same:
> 
> *WHEA Error Sources details:
> 
> ErrorSourceId: 0 Type: WheaErrSrcTypeDeviceDriver = 0x10, Device Driver Error Source
> ErrorSourceId: 1 Type: WheaErrSrcTypeMCE = 0x00, Machine Check Exception
> ErrorSourceId: 2 Type: WheaErrSrcTypeCMC = 0x01, Corrected Machine Check
> ErrorSourceId: 3 Type: WheaErrSrcTypeNMI = 0x03, Non-Maskable Interrupt
> ErrorSourceId: 4 Type: WheaErrSrcTypeBOOT = 0x07, BOOT Error Source*
> 
> The high flow data rate is not coming from the Error Source 1,2,3 like it should if it was from the CPU.
> 
> This is a legitimate Error 18:
> 
> View attachment 2511689
> 
> 
> Error source is 3, *Non-Maskable Interrupt*.
> 
> This is a WHEA Error 19 from the high data rate flow:
> 
> View attachment 2511690
> 
> 
> Error source is 0, *Device Driver Error Source*.
> 
> *The Device Driver error source can be literally anything.*
> You can compile a driver with the NDK which has the sole function of just outputting WHEA Error 19 for that source with random info inside
> 
> These errors can come from the IO die, the Realtek NIC, whatever has a driver, also the CPU.
> 
> Unfortunately WHEA, as many of the Microsoft stuff, sucks badly.
> I couldn't find how to really understand *who sent the error*.
> 
> *I don't trust this error reliability and the whole WHEA error reporting system in any form once it's triggered by high FCLK.*
> 
> What I trust more is my old method of testing which is telling me otherwise; my system is running fine.
> 
> And my eyes, since it's been a week (I want to cry 5 minutes in a corner for this) that *I don't see a single USB issue for the first time.*
> I've been plagued with USB issues since the first day I bought the 3800x.
> 
> _*Instead of observing a system borderline stable I'm seeing a system more reliable than at FCLK 1900.*_
> *It doesn't fit at all to what the WHEA error reporting is telling me.*
> 
> Plus of course months of testing and benching on my the Win2GO USB install.
> Zero issues.
> I do get performance degradation over FCLK 2000 while it was over 2033 with older AGESA.
> That's all.
> 
> Everyone has the freedom to test it on its own skin now, no complaints if it doesn't work.


....sorry to chime in, but i literally have only well heres a look to show,
but ive got very little in event data...is there a script one can get,
or task i can run to show more info?

or is it simply bc its ID20 and theres nothing on it??


----------



## RonLazer

craxton said:


> ....sorry to chime in, but i literally have only well heres a look to show,
> but ive got very little in event data...is there a script one can get,
> or task i can run to show more info?
> 
> or is it simply bc its ID20 and theres nothing on it??
> View attachment 2511709


Level 4 is your DRAM, I think those are just normal error correction in routine DRAM operation. DDR4 has many inbuilt error correction processes which don't even qualify as ECC.

Level 256 would be the general address space associated with non CPU/DRAM devices.

Anyway, I have an NVMe drive on the way, but I might just try booting Windows off a USB with the chipset disconnected (there are USB ports that connect directly to the CPU in the X570 block diagram) and then we'll see if the fault is on the GMI link or a board SMD.


----------



## T[]RK

craxton said:


> Whose reporting posts?


It was me.



craxton said:


> When stuff is linked outside the site
> Like crack stuff (in spoilers)


No, there was serial numbers on AIDA64 in you post. Under "spolier", but in you post. You post in this topic on OCN forum. This topic is too valuble (mostly because of huge Veii input) to be shut down because someone posted something not belong to him and make owners of AIDA64 mad. There are more then enought ways to share things.



craxton said:


> Their flags work.


Sure it is. There was a potential problem. I explained admins what it is and how it may end. They reacted exactly as expected - eliminated problem before it become a real problem for THEM (not for user). That's why you can keep posting here comments and read answers instead of get "Error 404".

P.S.OCN admins surprisingly polite and don't ban users for such behaviour. On RU HW forums you may get instant ban for such things.


----------



## hazium233

Here is how much progress I made on FCLK 2000 and 1966:










Usually the way it went was a little after Windows load +1 interconnect. Then at 2000 with probably too low voltages, +100 every once and a while. Tried some at 1966 starting at 0.900, 0.940, 1.060, 1.125V.

LCLK states to Disabled didn't seem to affect the big stuff. SOC to 1.1825 cut them way down. I did some minor changes on CCD and IOD, but since it had become like a ticking clock, I did some PLL checks to look at rate with fixed CLDOs and SOC

1.8 - 4.5 / min
1.81 - 4.5 / min
1.82 - 1.5 / min
1.83 - 1 / min
1.84 - 1 in 30 minutes
1.85 - 1 in 3 minutes

Stopped there for the time being since 1.85 seemed worse, but I guess I will check through 1.9 or so later.

---

The WHEA 19 logs were basically one of three things, Unknown the most common. In spoiler:



Spoiler



Machine Check Exception - rare



> A corrected hardware error has occurred.
> 
> Reported by component: Processor Core
> Error Source: Machine Check Exception
> Error Type: Bus/Interconnect Error
> Processor APIC ID: 0












Then the "Corrected Machine Check" - somewhat rare

Seemed to come in pairs logged 59s apart. eg 9:15:01, next would be 9:16:00



> A corrected hardware error has occurred.
> 
> Reported by component: Processor Core
> Error Source: Corrected Machine Check
> Error Type: Bus/Interconnect Error
> Processor APIC ID: 0












The by far most common "Unknown Error Source"



> A corrected hardware error has occurred.
> 
> Reported by component: Processor Core
> Error Source: Unknown Error Source
> Error Type: Bus/Interconnect Error
> Processor APIC ID: 0














I didn't validate this timings but the next spoiler is when trying 2000 first:



Spoiler



Guess I should have started >> 1.12 SOC


----------



## PJVol

I wonder, has anyone ever heard from any AMD official rep (i.e. Hallock-like) of the reasons for these WHEA at high FCLK ?

...meanwhile ))


----------



## ChillyRide

Cant lower tRDWR. What timing have effect on tRDWR? may be SCL rise to 3-3? Everything after RDWR auto.


----------



## Robostyle

I've read last couple of pages about this WHEA thing...this is what you've been talking about?









It is completely stable, HCI 200%, etc. Can go stable even at RAM 4000: FCLK 2000, but I get sound issues then. 
So, this is BIOS/software problem, not the hardware, right?

Interesting fact - I've started getting these errors after I reinstalled Win10 for my fresh am4 build. Before I've ran my old Win left from 8700K platform - had zero issues.


----------



## Takla

Robostyle said:


> I've read last couple of pages about this WHEA thing...this is what you've been talking about?
> View attachment 2511738
> 
> 
> It is completely stable, HCI 200%, etc. Can go stable even at RAM 4000: FCLK 2000, but I get sound issues then.
> So, this is BIOS/software problem, not the hardware, right?
> 
> Interesting fact - I've started getting these errors after I reinstalled Win10 for my fresh am4 build. Before I've ran my old Win left from 8700K platform - had zero issues.


That is fclk instability. You can try playing around with vddp/vddg & soc voltage. I found I get errors quicker when there is a gpu load too, so I used Aida64 stress test.


----------



## jomama22

Robostyle said:


> I've read last couple of pages about this WHEA thing...this is what you've been talking about?
> View attachment 2511738
> 
> 
> It is completely stable, HCI 200%, etc. Can go stable even at RAM 4000: FCLK 2000, but I get sound issues then.
> So, this is BIOS/software problem, not the hardware, right?
> 
> Interesting fact - I've started getting these errors after I reinstalled Win10 for my fresh am4 build. Before I've ran my old Win left from 8700K platform - had zero issues.


Were you on 1909 by chance on the old windows?


----------



## VinnieM

ChillyRide said:


> Cant lower tRDWR. What timing have effect on tRDWR? may be SCL rise to 3-3? Everything after RDWR auto.


You probably need to lower tWRRD as well. I can run tWRRD at 2 and tRDWR at 10, maybe even 9. Still testing this memory speed.
Key for memory stability was upping the ClkDrvStr from 40 to 60 Ohm. WHEA errors are still there, but greatly reduced after upping the CPU VDD18 from 1.8 to about 1.96v.
Funny is that especially the AIDA memory benchmark seems to trigger these, while running TM5 does almost nothing.


----------



## craxton

T[]RK said:


> That's why you can keep posting here comments and read answers instead of get "Error 404".


im almost sure i can keep posting due to three strike rule?

i checked the DCMA FAQ, i know the rules (after post) 
id much rather you have just sent me a PM and stated this before hand, 
so that piece of the comment could have been resolved. instead the entire comment being removed.



T[]RK said:


> P.S.OCN admins surprisingly polite and don't ban users for such behavior


yea considering this site is the only one i really use
i know how they are. have had to use the admins for profile issues.



Spoiler



and "the users" tend to be polite 













T[]RK said:


> It was me.


respect you came forward but perhaps due to this site ill keep my unmentionable thought(s)
to myself (little tip tho, real world scenes dont tell on yourself, or anyone else)
again, respect you stated it was you, but if at some point ive posted something
you "dont agree with" simply send me a pm, not one to ignore a message.



T[]RK said:


> No, there was serial numbers on AIDA64 in you post.


i know what was posted for me to be warned lol...only thing ive actually posted 
to be warned about. 
other than in the post linking gig games (scrambled for a reason)
for so (dont try googling gig) for the sake of those claiming
they cant get or dont own games. but never the less 
you seemed to have missed that one i suppose? unless it doesnt go against
policy, i would think it does, as its not much different than serial keys..?? unsure honestly
(future posts, wont link or have stuff the compromise's this site)
or this thread in particular. 



T[]RK said:


> That's why you can keep posting here comments and read answers instead of get "Error 404"


my account may get banned, but ive got another just bc...
not because of something like this.. simply due to my profile being locked 
to where nothing was able to be added or changed or signatures being modified...

none the less, let this be for the sake of me trying to be polite... 
rather stay polite... feel free to PM your response if you wish.


----------



## craxton

RonLazer said:


> Level 4 is your DRAM,


so, even tho i had no errors in HCI, memtest pro, y-cruncher, occt and prime
somethings not quite right with my timings???

only time ive got this id20 is when voltage/co was off to make a hard crash....


----------



## RonLazer

craxton said:


> so, even tho i had no errors in HCI, memtest pro, y-cruncher, occt and prime
> somethings not quite right with my timings???
> 
> only time ive got this id20 is when voltage/co was off to make a hard crash....


If the inbuilt error-correction mechanisms catch it then no, the memory testing software won't register an error. Memory testing software works by creating a segment of data with a known checksum, writing it to DRAM, possibly performing some further operations on it, then reading it back and verifying the checksum. If the checksum is invalid then its' deemed to have failed that test. Since in this case the error was detected and corrected at the hardware level - the data is uncorrupted and the checksum is valid.


----------



## craxton

RonLazer said:


> If the inbuilt error-correction mechanisms catch it then no


so whats happening is the built in error correction?
meaning, something somewhere is to tight or slightly off?
this just started happening after i reinstalled windows 

and i played with curve, perhaps ill check to see if the timings are as they should be.

or do you mean windows memory diagnostics test?


----------



## Robostyle

Takla said:


> That is fclk instability. You can try playing around with vddp/vddg & soc voltage. I found I get errors quicker when there is a gpu load too, so I used Aida64 stress test.


Yea, there is some kind of edge when raising SOC voltages decrease the amount of these errors from hundreds to tens, but thats it, I still get’em no matter what voltages I set. Solid stable at 3733:1866 with SOC 1.1V, while numerous WHEAs at 3800:1900 with SOC even 1.2V and above.



jomama22 said:


> Were you on 1909 by chance on the old windows?


Might be - actually, I remember my old windows was stubborn on updates, it did not get 2004 update for long, whereas my laptop was runing 2004 for almost a year.


----------



## jomama22

Robostyle said:


> Yea, there is some kind of edge when raising SOC voltages decrease the amount of these errors from hundreds to tens, but thats it, I still get’em no matter what voltages I set. Solid stable at 3733:1866 with SOC 1.1V, while numerous WHEAs at 3800:1900 with SOC even 1.2V and above.
> 
> 
> Might be - actually, I remember my old windows was stubborn on updates, it did not get 2004 update for long, whereas my laptop was runing 2004 for almost a year.


Yeah, only reason I ask is because 1909 doesn't produce the whea 19s on zen 3. Why this is exactly I'm not sure, could just be a lack of reporting, but it's a known effect.


----------



## DeletedMember558271

RonLazer said:


> Anyway, I have an NVMe drive on the way, but I might just try booting Windows off a USB with the chipset disconnected (there are USB ports that connect directly to the CPU in the X570 block diagram) and then we'll see if the fault is on the GMI link or a board SMD.


If it does anything I wish my board had this feature, I'm basically only using CPU USB and NVMe or can be, have a SATA drive for backups that isn't important/needing to always be hooked up.
I don't think it'd be hiding under any stupid disguised name for me as well, but maybe.
I feel like I'm gonna be surprised if it works, and if it does what, I have to buy a Dark Hero or try to find boards with this feature? Which I don't know how I'm going to find that


----------



## RonLazer

Dreamic said:


> If it does anything I wish my board had this feature, I'm basically only using CPU USB and NVMe or can be, have a SATA drive for backups that isn't important/needing to always be hooked up.
> I don't think it'd be hiding under any stupid disguised name for me as well, but maybe.
> I feel like I'm gonna be surprised if it works, and if it does what, I have to buy a Dark Hero or try to find boards with this feature? Which I don't know how I'm going to find that


I think any Crosshair Board would have this feature. Asus really do put effort into their boards XOC features compared to MSI and Gigabyte (though Z590 suggests they're back in the game).


----------



## craxton

@RonLazer 
this is a screen shot of my event viewer
per shots of 18 and 20 (times are identical) i can make 20 happen by lowering voltage
and stressing the system...

yes i got (what you said) that theres an error somewhere....
but i dont fully understand if you mean windows sent something 
and the data was sent back curropt in the process? or
none the less, when i make a ID20 happen 18 comes out with it....


----------



## MattKelly

So I know the verdict is still out on what exactly might be causing WHEA #19... but is there a general accepted trend for which ITX boards are able to push FCLK the farthest, without much issue? I currently have an unopened Asus X570-I Strix, and was thinking of returning it for the ASRock B550 Phantom ITX board (but am interested in what other ITX boards might also be worth considering).

@Veii, would you be able to shine a light on which boards make your okay-list (specifically for ITX?). What would you buy today, knowing what you know right now?


----------



## RonLazer

craxton said:


> @RonLazer
> this is a screen shot of my event viewer
> per shots of 18 and 20 (times are identical) i can make 20 happen by lowering voltage
> and stressing the system...
> 
> yes i got (what you said) that theres an error somewhere....
> but i dont fully understand if you mean windows sent something
> and the data was sent back curropt in the process? or
> none the less, when i make a ID20 happen 18 comes out with it....
> View attachment 2511771


Can you send the full logs of both? I need the MCA/MCI data to interpret them properly.


----------



## RonLazer

Just some testing I did with Aida64 latency (its just the most consistent measure of memory performance, even though its only vaguely correlated with "real" benchmarks) and you can clearly see the effect of different "fclk domains" with respect to memory training:










X570 Dark Hero, AGESA 1.1.19, SMU 56.43.00, 5600X was static 4.8GHz, DRAM timings were like 12-12-12-24-48 + 100ns of tRFC + tight subs. I didn't tune the SOC/IOD/CCD/PLL/DRAM voltages for each frequency, just used the ones for 2000MHz across the full range. I did try tuning for 2033MHz but the lowest I could get the latency was like 49.5ns at 2003MHz so it was pointless.

Up till 1867Mhz it scales linearly, at 1900MHz the link-training switches to something else which is about 0.4ns slower but then continues to scale linearly down to 2000MHz, then the latency spikes and needs excessively high voltages to retrieve some of the lost latency.

Linpack scales to about 1900Mhz, then takes a big hit at 1933MHz, and totally bottoms out at 2000MHz. Performance is crap at 2033MHz regardless of voltages.

SuperPi 32M scales the entire range to 200MHz, but also falls apart at 2033MHz.


----------



## hazium233

RonLazer said:


> Just some testing I did with Aida64 latency (its just the most consistent measure of memory performance, even though its only vaguely correlated with "real" benchmarks) and you can clearly see the effect of different "fclk domains" with respect to memory training:
> 
> View attachment 2511773
> 
> 
> X570 Dark Hero, AGESA 1.1.19, SMU 56.43.00, 5600X was static 4.8GHz, DRAM timings were like 12-12-12-24-48 + 100ns of tRFC + tight subs. I didn't tune the SOC/IOD/CCD/PLL/DRAM voltages for each frequency, just used the ones for 2000MHz across the full range. I did try tuning for 2000MHz but the lowest I could get the latency was like 49.5ns at 2003MHz so it was pointless.
> 
> Up till 1867Mhz it scales linearly, at 1900MHz the link-training switches to something else which is about 0.4ns slower but then continues to scale linearly down to 2000MHz, then the latency spikes and needs excessively high voltages to retrieve some of the lost latency.
> 
> Linpack scales to about 1900Mhz, then takes a big hit at 1933MHz, and totally bottoms out at 2000MHz. Performance is crap at 2033MHz regardless of voltages.
> 
> SuperPi 32M scales the entire range to 200MHz, but also falls apart at 2033MHz.


Hmmm so should 56.50.00 be expected to behave similarly?


----------



## RonLazer

hazium233 said:


> Hmmm so should 56.50.00 be expected to behave similarly?


Most likely yes, but give it a shot!


----------



## NDS322

Last night I change the memory bus from 4066 to 4000 MHz and update the driver Realtek Lan driver 10.50.511.2021 from some guy in the Gigabyte forum
then I have not been notified of WHEA 19 again since 2 AM.

*update* it still has problem again on 9.34/9.43 AM today


----------



## NDS322

Try it here

Realtek RTL8125 10.050 WHQL as promised - https://www.dropbox.com/s/sz8e5a5jus...82021.zip?dl=0
As before, source is Realtek.

From user AMD718 tweaktownforum


----------



## hazium233

RonLazer said:


> Most likely yes, but give it a shot!


I think I need to take out my 5600X and drop it on the ground like craxton before I will be able to get 2000 FCLK to work without WHEA out the Wazzoo.

I will try to fall into the local nadir at 1866.


----------



## ManniX-ITA

Robostyle said:


> It is completely stable, HCI 200%, etc. Can go stable even at RAM 4000: FCLK 2000, but I get sound issues then.
> So, this is BIOS/software problem, not the hardware, right?


If you get sound issues you probably need to raise VDDG IOD and VSOC.

No it could be also an hardware problem.
Or a BIOS/Firmware issue. Or a combination of multiple issues.
We don't know for sure.
But if you are confident it can run it reliably and you get too many errors, which will slow down the system, you can silence them.


----------



## craxton

RonLazer said:


> Can you send the full logs of both?


and i do this how exactly?

*!!!DISCLAIMER!!!
My pc name is exactly what it is,
please NOONE take offense!
ill not hear no nonesense about the name of a 
machine! if you possibly get upset over nothing
then do not look at the PC NAME!*


if its as simple as copy paste, then well see below.
(copied entire log folder as detailed view...unsure if this is what you meant or not...
but i didnt see export only import.




Code:


Log Name:      Microsoft-Windows-Kernel-WHEA/Errors
Source:        Microsoft-Windows-Kernel-WHEA
Date:          5/21/2021 12:26:46 PM
Event ID:      20
Task Category: None
Level:         Information
Keywords:      WHEA Error Events
User:          SYSTEM
Computer:      BLACK-BOSS
Description:
WHEA Event
Event Xml:
<Event xmlns="http://schemas.microsoft.com/win/2004/08/events/event">
  <System>
    <Provider Name="Microsoft-Windows-Kernel-WHEA" Guid="{7b563579-53c8-44e7-8236-0f87b9fe6594}" />
    <EventID>20</EventID>
    <Version>0</Version>
    <Level>4</Level>
    <Task>0</Task>
    <Opcode>0</Opcode>
    <Keywords>0x4000000000000800</Keywords>
    <TimeCreated SystemTime="2021-05-21T16:26:46.1147675Z" />
    <EventRecordID>4</EventRecordID>
    <Correlation />
    <Execution ProcessID="4" ThreadID="168" />
    <Channel>Microsoft-Windows-Kernel-WHEA/Errors</Channel>
    <Computer>BLACK-BOSS</Computer>
    <Security UserID="S-1-5-18" />
  </System>
  <EventData>
    <Data Name="Length">936</Data>
    <Data Name="RawData">435045521002FFFFFFFF03000100000002000000A80300002E1A1000150515140000000000000000000000000000000000000000000000000000000000000000BDC407CF89B7184EB3C41F732CB57131FE6FF5E89C91C54CBA8865ABE14913BBEECCA3155E4ED70102000000000000000000000000000000000000000000000058010000C00000000003000001000000ADCC7698B447DB4BB65E16F193C4F3DB0000000000000000000000000000000001000000000000000000000000000000000000000000000018020000800000000003000000000000B0A03EDC44A19747B95B53FA242B6E1D0000000000000000000000000000000001000000000000000000000000000000000000000000000098020000100100000003000000000000011D1E8AF94257459C33565E5CC3F7E8000000000000000000000000000000000100000000000000000000000000000000000000000000007F010000000000000002010300000000100FA2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000007000000000000000600000000000000100FA20000080C060B32D87EFFFB8B170000000000000000000000000000000000000000000000000000000000000000F50157A5EFE3DE43AC72249B573FAD2C01000000000000009F0014060000000000000000000000000000000000000000000000000000000000000000000000000200000002000000D056A0175E4ED701060000000000000000000000000000000000000005000000500103000000A0BA000000000000000000000000FE0F1AD0000000000600000000000000B00005000200004D00000000F9010000230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</Data>
  </EventData>
</Event>

LOG#2

Log Name:      Microsoft-Windows-Kernel-WHEA/Errors
Source:        Microsoft-Windows-Kernel-WHEA
Date:          5/19/2021 8:13:16 AM
Event ID:      20
Task Category: None
Level:         Information
Keywords:      WHEA Error Events
User:          SYSTEM
Computer:      BLACK-BOSS
Description:
WHEA Event
Event Xml:
<Event xmlns="http://schemas.microsoft.com/win/2004/08/events/event">
  <System>
    <Provider Name="Microsoft-Windows-Kernel-WHEA" Guid="{7b563579-53c8-44e7-8236-0f87b9fe6594}" />
    <EventID>20</EventID>
    <Version>0</Version>
    <Level>4</Level>
    <Task>0</Task>
    <Opcode>0</Opcode>
    <Keywords>0x4000000000000800</Keywords>
    <TimeCreated SystemTime="2021-05-19T12:13:16.3141847Z" />
    <EventRecordID>3</EventRecordID>
    <Correlation />
    <Execution ProcessID="4" ThreadID="168" />
    <Channel>Microsoft-Windows-Kernel-WHEA/Errors</Channel>
    <Computer>BLACK-BOSS</Computer>
    <Security UserID="S-1-5-18" />
  </System>
  <EventData>
    <Data Name="Length">936</Data>
    <Data Name="RawData">435045521002FFFFFFFF03000100000002000000A8030000100D0C00130515140000000000000000000000000000000000000000000000000000000000000000BDC407CF89B7184EB3C41F732CB57131FE6FF5E89C91C54CBA8865ABE14913BBDA16F056A84CD70102000000000000000000000000000000000000000000000058010000C00000000003000001000000ADCC7698B447DB4BB65E16F193C4F3DB0000000000000000000000000000000001000000000000000000000000000000000000000000000018020000800000000003000000000000B0A03EDC44A19747B95B53FA242B6E1D0000000000000000000000000000000001000000000000000000000000000000000000000000000098020000100100000003000000000000011D1E8AF94257459C33565E5CC3F7E8000000000000000000000000000000000100000000000000000000000000000000000000000000007F010000000000000002010300000000100FA2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000007000000000000000600000000000000100FA20000080C060B32D87EFFFB8B170000000000000000000000000000000000000000000000000000000000000000F50157A5EFE3DE43AC72249B573FAD2C01000000000000009F0014060000000000000000000000000000000000000000000000000000000000000000000000000200000002000000E5DE0E59A84CD701060000000000000000000000000000000000000005000000500103000000A0BA000000000000000000000000FE0F1AD0000000000600000000000000B00005000200004D00000000F9010000230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</Data>
  </EventData>
</Event>


LOG#3

Log Name:      Microsoft-Windows-Kernel-WHEA/Errors
Source:        Microsoft-Windows-Kernel-WHEA
Date:          5/19/2021 8:06:15 AM
Event ID:      20
Task Category: None
Level:         Information
Keywords:      WHEA Error Events
User:          SYSTEM
Computer:      BLACK-BOSS
Description:
WHEA Event
Event Xml:
<Event xmlns="http://schemas.microsoft.com/win/2004/08/events/event">
  <System>
    <Provider Name="Microsoft-Windows-Kernel-WHEA" Guid="{7b563579-53c8-44e7-8236-0f87b9fe6594}" />
    <EventID>20</EventID>
    <Version>0</Version>
    <Level>4</Level>
    <Task>0</Task>
    <Opcode>0</Opcode>
    <Keywords>0x4000000000000800</Keywords>
    <TimeCreated SystemTime="2021-05-19T12:06:15.8899820Z" />
    <EventRecordID>2</EventRecordID>
    <Correlation />
    <Execution ProcessID="4" ThreadID="476" />
    <Channel>Microsoft-Windows-Kernel-WHEA/Errors</Channel>
    <Computer>BLACK-BOSS</Computer>
    <Security UserID="S-1-5-18" />
  </System>
  <EventData>
    <Data Name="Length">936</Data>
    <Data Name="RawData">435045521002FFFFFFFF03000100000002000000A80300000F060C00130515140000000000000000000000000000000000000000000000000000000000000000BDC407CF89B7184EB3C41F732CB57131FE6FF5E89C91C54CBA8865ABE14913BB0F939B5CA74CD70102000000000000000000000000000000000000000000000058010000C00000000003000001000000ADCC7698B447DB4BB65E16F193C4F3DB0000000000000000000000000000000001000000000000000000000000000000000000000000000018020000800000000003000000000000B0A03EDC44A19747B95B53FA242B6E1D0000000000000000000000000000000001000000000000000000000000000000000000000000000098020000100100000003000000000000011D1E8AF94257459C33565E5CC3F7E8000000000000000000000000000000000100000000000000000000000000000000000000000000007F010000000000000002010300000000100FA2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000007000000000000000600000000000000100FA20000080C060B32D87EFFFB8B170000000000000000000000000000000000000000000000000000000000000000F50157A5EFE3DE43AC72249B573FAD2C01000000000000009F00140600000000000000000000000000000000000000000000000000000000000000000000000002000000020000004D80775EA74CD701060000000000000000000000000000000000000005000000500103000000A0BA000000000000000000000000FE0F1AD0000000000600000000000000B00005000200004D00000000F9010000230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</Data>
  </EventData>
</Event>

LOG#4

Log Name:      Microsoft-Windows-Kernel-WHEA/Errors
Source:        Microsoft-Windows-Kernel-WHEA
Date:          5/18/2021 8:25:31 PM
Event ID:      20
Task Category: None
Level:         Information
Keywords:      WHEA Error Events
User:          SYSTEM
Computer:      BLACK-BOSS
Description:
WHEA Event
Event Xml:
<Event xmlns="http://schemas.microsoft.com/win/2004/08/events/event">
  <System>
    <Provider Name="Microsoft-Windows-Kernel-WHEA" Guid="{7b563579-53c8-44e7-8236-0f87b9fe6594}" />
    <EventID>20</EventID>
    <Version>0</Version>
    <Level>4</Level>
    <Task>0</Task>
    <Opcode>0</Opcode>
    <Keywords>0x4000000000000800</Keywords>
    <TimeCreated SystemTime="2021-05-19T00:25:31.9773000Z" />
    <EventRecordID>1</EventRecordID>
    <Correlation />
    <Execution ProcessID="4" ThreadID="456" />
    <Channel>Microsoft-Windows-Kernel-WHEA/Errors</Channel>
    <Computer>BLACK-BOSS</Computer>
    <Security UserID="S-1-5-18" />
  </System>
  <EventData>
    <Data Name="Length">936</Data>
    <Data Name="RawData">435045521002FFFFFFFF03000100000002000000A80300001F190000130515140000000000000000000000000000000000000000000000000000000000000000BDC407CF89B7184EB3C41F732CB57131FE6FF5E89C91C54CBA8865ABE14913BB83F16B78454CD70102000000000000000000000000000000000000000000000058010000C00000000003000001000000ADCC7698B447DB4BB65E16F193C4F3DB0000000000000000000000000000000001000000000000000000000000000000000000000000000018020000800000000003000000000000B0A03EDC44A19747B95B53FA242B6E1D0000000000000000000000000000000001000000000000000000000000000000000000000000000098020000100100000003000000000000011D1E8AF94257459C33565E5CC3F7E8000000000000000000000000000000000100000000000000000000000000000000000000000000007F010000000000000002010300000000100FA2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000007000000000000000600000000000000100FA20000080C060B32D87EFFFB8B170000000000000000000000000000000000000000000000000000000000000000F50157A5EFE3DE43AC72249B573FAD2C01000000000000009F00140600000000000000000000000000000000000000000000000000000000000000000000000002000000020000005079567A454CD701060000000000000000000000000000000000000005000000500103000000A0BA000000000000000000000000FE0F1AD0000000000600000000000000B00005000200004D00000000F9010000230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</Data>
  </EventData>
</Event>


EVENT 18 LOGS




Code:


Log Name:      System
Source:        Microsoft-Windows-WHEA-Logger
Date:          5/21/2021 12:26:53 PM
Event ID:      18
Task Category: None
Level:         Error
Keywords:  
User:          LOCAL SERVICE
Computer:      BLACK-BOSS
Description:
A fatal hardware error has occurred.

Reported by component: Processor Core
Error Source: Machine Check Exception
Error Type: Cache Hierarchy Error
Processor APIC ID: 6

The details view of this entry contains further information.
Event Xml:
<Event xmlns="http://schemas.microsoft.com/win/2004/08/events/event">
  <System>
    <Provider Name="Microsoft-Windows-WHEA-Logger" Guid="{c26c4f3c-3f66-4e99-8f8a-39405cfed220}" />
    <EventID>18</EventID>
    <Version>0</Version>
    <Level>2</Level>
    <Task>0</Task>
    <Opcode>0</Opcode>
    <Keywords>0x8000000000000000</Keywords>
    <TimeCreated SystemTime="2021-05-21T16:26:53.6127640Z" />
    <EventRecordID>11586</EventRecordID>
    <Correlation ActivityID="{289b93dd-bf01-4db8-83f9-4ec0af3a692b}" />
    <Execution ProcessID="3916" ThreadID="4984" />
    <Channel>System</Channel>
    <Computer>BLACK-BOSS</Computer>
    <Security UserID="S-1-5-19" />
  </System>
  <EventData>
    <Data Name="ErrorSource">3</Data>
    <Data Name="ApicId">6</Data>
    <Data Name="MCABank">5</Data>
    <Data Name="MciStat">0xbaa0000000030150</Data>
    <Data Name="MciAddr">0x0</Data>
    <Data Name="MciMisc">0xd01a0ffe00000000</Data>
    <Data Name="ErrorType">9</Data>
    <Data Name="TransactionType">0</Data>
    <Data Name="Participation">256</Data>
    <Data Name="RequestType">5</Data>
    <Data Name="MemorIO">256</Data>
    <Data Name="MemHierarchyLvl">0</Data>
    <Data Name="Timeout">256</Data>
    <Data Name="OperationType">256</Data>
    <Data Name="Channel">256</Data>
    <Data Name="Length">936</Data>
    <Data Name="RawData">435045521002FFFFFFFF03000100000002000000A80300002E1A1000150515140000000000000000000000000000000000000000000000000000000000000000BDC407CF89B7184EB3C41F732CB57131FE6FF5E89C91C54CBA8865ABE14913BBEECCA3155E4ED70102000000000000000000000000000000000000000000000058010000C00000000003000001000000ADCC7698B447DB4BB65E16F193C4F3DB0000000000000000000000000000000001000000000000000000000000000000000000000000000018020000800000000003000000000000B0A03EDC44A19747B95B53FA242B6E1D0000000000000000000000000000000001000000000000000000000000000000000000000000000098020000100100000003000000000000011D1E8AF94257459C33565E5CC3F7E8000000000000000000000000000000000100000000000000000000000000000000000000000000007F010000000000000002010300000000100FA2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000007000000000000000600000000000000100FA20000080C060B32D87EFFFB8B170000000000000000000000000000000000000000000000000000000000000000F50157A5EFE3DE43AC72249B573FAD2C01000000000000009F0014060000000000000000000000000000000000000000000000000000000000000000000000000200000002000000D056A0175E4ED701060000000000000000000000000000000000000005000000500103000000A0BA000000000000000000000000FE0F1AD0000000000600000000000000B00005000200004D00000000F9010000230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</Data>
  </EventData>
</Event>

(LOG#2)

Log Name:      System
Source:        Microsoft-Windows-WHEA-Logger
Date:          5/19/2021 8:13:23 AM
Event ID:      18
Task Category: None
Level:         Error
Keywords:  
User:          LOCAL SERVICE
Computer:     BLACK-BOSS
Description:
A fatal hardware error has occurred.

Reported by component: Processor Core
Error Source: Machine Check Exception
Error Type: Cache Hierarchy Error
Processor APIC ID: 6

The details view of this entry contains further information.
Event Xml:
<Event xmlns="http://schemas.microsoft.com/win/2004/08/events/event">
  <System>
    <Provider Name="Microsoft-Windows-WHEA-Logger" Guid="{c26c4f3c-3f66-4e99-8f8a-39405cfed220}" />
    <EventID>18</EventID>
    <Version>0</Version>
    <Level>2</Level>
    <Task>0</Task>
    <Opcode>0</Opcode>
    <Keywords>0x8000000000000000</Keywords>
    <TimeCreated SystemTime="2021-05-19T12:13:23.6581092Z" />
    <EventRecordID>3473</EventRecordID>
    <Correlation ActivityID="{19f15701-3847-4db7-82fb-cb887241f37d}" />
    <Execution ProcessID="3880" ThreadID="4408" />
    <Channel>System</Channel>
    <Computer>BLACK-BOSS</Computer>
    <Security UserID="S-1-5-19" />
  </System>
  <EventData>
    <Data Name="ErrorSource">3</Data>
    <Data Name="ApicId">6</Data>
    <Data Name="MCABank">5</Data>
    <Data Name="MciStat">0xbaa0000000030150</Data>
    <Data Name="MciAddr">0x0</Data>
    <Data Name="MciMisc">0xd01a0ffe00000000</Data>
    <Data Name="ErrorType">9</Data>
    <Data Name="TransactionType">0</Data>
    <Data Name="Participation">256</Data>
    <Data Name="RequestType">5</Data>
    <Data Name="MemorIO">256</Data>
    <Data Name="MemHierarchyLvl">0</Data>
    <Data Name="Timeout">256</Data>
    <Data Name="OperationType">256</Data>
    <Data Name="Channel">256</Data>
    <Data Name="Length">936</Data>
    <Data Name="RawData">435045521002FFFFFFFF03000100000002000000A8030000100D0C00130515140000000000000000000000000000000000000000000000000000000000000000BDC407CF89B7184EB3C41F732CB57131FE6FF5E89C91C54CBA8865ABE14913BBDA16F056A84CD70102000000000000000000000000000000000000000000000058010000C00000000003000001000000ADCC7698B447DB4BB65E16F193C4F3DB0000000000000000000000000000000001000000000000000000000000000000000000000000000018020000800000000003000000000000B0A03EDC44A19747B95B53FA242B6E1D0000000000000000000000000000000001000000000000000000000000000000000000000000000098020000100100000003000000000000011D1E8AF94257459C33565E5CC3F7E8000000000000000000000000000000000100000000000000000000000000000000000000000000007F010000000000000002010300000000100FA2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000007000000000000000600000000000000100FA20000080C060B32D87EFFFB8B170000000000000000000000000000000000000000000000000000000000000000F50157A5EFE3DE43AC72249B573FAD2C01000000000000009F0014060000000000000000000000000000000000000000000000000000000000000000000000000200000002000000E5DE0E59A84CD701060000000000000000000000000000000000000005000000500103000000A0BA000000000000000000000000FE0F1AD0000000000600000000000000B00005000200004D00000000F9010000230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</Data>
  </EventData>
</Event>

(LOG#3)

Log Name:      System
Source:        Microsoft-Windows-WHEA-Logger
Date:          5/19/2021 8:06:23 AM
Event ID:      18
Task Category: None
Level:         Error
Keywords:  
User:          LOCAL SERVICE
Computer:      BLACK-BOSS
Description:
A fatal hardware error has occurred.

Reported by component: Processor Core
Error Source: Machine Check Exception
Error Type: Cache Hierarchy Error
Processor APIC ID: 6

The details view of this entry contains further information.
Event Xml:
<Event xmlns="http://schemas.microsoft.com/win/2004/08/events/event">
  <System>
    <Provider Name="Microsoft-Windows-WHEA-Logger" Guid="{c26c4f3c-3f66-4e99-8f8a-39405cfed220}" />
    <EventID>18</EventID>
    <Version>0</Version>
    <Level>2</Level>
    <Task>0</Task>
    <Opcode>0</Opcode>
    <Keywords>0x8000000000000000</Keywords>
    <TimeCreated SystemTime="2021-05-19T12:06:23.0350467Z" />
    <EventRecordID>3346</EventRecordID>
    <Correlation ActivityID="{e021af8a-b23d-48ea-a0de-ea88c247dff4}" />
    <Execution ProcessID="3688" ThreadID="4116" />
    <Channel>System</Channel>
    <Computer>BLACK-BOSS</Computer>
    <Security UserID="S-1-5-19" />
  </System>
  <EventData>
    <Data Name="ErrorSource">3</Data>
    <Data Name="ApicId">6</Data>
    <Data Name="MCABank">5</Data>
    <Data Name="MciStat">0xbaa0000000030150</Data>
    <Data Name="MciAddr">0x0</Data>
    <Data Name="MciMisc">0xd01a0ffe00000000</Data>
    <Data Name="ErrorType">9</Data>
    <Data Name="TransactionType">0</Data>
    <Data Name="Participation">256</Data>
    <Data Name="RequestType">5</Data>
    <Data Name="MemorIO">256</Data>
    <Data Name="MemHierarchyLvl">0</Data>
    <Data Name="Timeout">256</Data>
    <Data Name="OperationType">256</Data>
    <Data Name="Channel">256</Data>
    <Data Name="Length">936</Data>
    <Data Name="RawData">435045521002FFFFFFFF03000100000002000000A80300000F060C00130515140000000000000000000000000000000000000000000000000000000000000000BDC407CF89B7184EB3C41F732CB57131FE6FF5E89C91C54CBA8865ABE14913BB0F939B5CA74CD70102000000000000000000000000000000000000000000000058010000C00000000003000001000000ADCC7698B447DB4BB65E16F193C4F3DB0000000000000000000000000000000001000000000000000000000000000000000000000000000018020000800000000003000000000000B0A03EDC44A19747B95B53FA242B6E1D0000000000000000000000000000000001000000000000000000000000000000000000000000000098020000100100000003000000000000011D1E8AF94257459C33565E5CC3F7E8000000000000000000000000000000000100000000000000000000000000000000000000000000007F010000000000000002010300000000100FA2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000007000000000000000600000000000000100FA20000080C060B32D87EFFFB8B170000000000000000000000000000000000000000000000000000000000000000F50157A5EFE3DE43AC72249B573FAD2C01000000000000009F00140600000000000000000000000000000000000000000000000000000000000000000000000002000000020000004D80775EA74CD701060000000000000000000000000000000000000005000000500103000000A0BA000000000000000000000000FE0F1AD0000000000600000000000000B00005000200004D00000000F9010000230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</Data>
  </EventData>
</Event>

(LOG#4)

Log Name:      System
Source:        Microsoft-Windows-WHEA-Logger
Date:          5/18/2021 8:25:38 PM
Event ID:      18
Task Category: None
Level:         Error
Keywords:  
User:          LOCAL SERVICE
Computer:      BLACK-BOSS
Description:
A fatal hardware error has occurred.

Reported by component: Processor Core
Error Source: Machine Check Exception
Error Type: Cache Hierarchy Error
Processor APIC ID: 6

The details view of this entry contains further information.
Event Xml:
<Event xmlns="http://schemas.microsoft.com/win/2004/08/events/event">
  <System>
    <Provider Name="Microsoft-Windows-WHEA-Logger" Guid="{c26c4f3c-3f66-4e99-8f8a-39405cfed220}" />
    <EventID>18</EventID>
    <Version>0</Version>
    <Level>2</Level>
    <Task>0</Task>
    <Opcode>0</Opcode>
    <Keywords>0x8000000000000000</Keywords>
    <TimeCreated SystemTime="2021-05-19T00:25:38.6061740Z" />
    <EventRecordID>857</EventRecordID>
    <Correlation ActivityID="{71c4255b-4bb8-4c74-b041-d09d4634e656}" />
    <Execution ProcessID="3724" ThreadID="4000" />
    <Channel>System</Channel>
    <Computer>BLACK-BOSS</Computer>
    <Security UserID="S-1-5-19" />
  </System>
  <EventData>
    <Data Name="ErrorSource">3</Data>
    <Data Name="ApicId">6</Data>
    <Data Name="MCABank">5</Data>
    <Data Name="MciStat">0xbaa0000000030150</Data>
    <Data Name="MciAddr">0x0</Data>
    <Data Name="MciMisc">0xd01a0ffe00000000</Data>
    <Data Name="ErrorType">9</Data>
    <Data Name="TransactionType">0</Data>
    <Data Name="Participation">256</Data>
    <Data Name="RequestType">5</Data>
    <Data Name="MemorIO">256</Data>
    <Data Name="MemHierarchyLvl">0</Data>
    <Data Name="Timeout">256</Data>
    <Data Name="OperationType">256</Data>
    <Data Name="Channel">256</Data>
    <Data Name="Length">936</Data>
    <Data Name="RawData">435045521002FFFFFFFF03000100000002000000A80300001F190000130515140000000000000000000000000000000000000000000000000000000000000000BDC407CF89B7184EB3C41F732CB57131FE6FF5E89C91C54CBA8865ABE14913BB83F16B78454CD70102000000000000000000000000000000000000000000000058010000C00000000003000001000000ADCC7698B447DB4BB65E16F193C4F3DB0000000000000000000000000000000001000000000000000000000000000000000000000000000018020000800000000003000000000000B0A03EDC44A19747B95B53FA242B6E1D0000000000000000000000000000000001000000000000000000000000000000000000000000000098020000100100000003000000000000011D1E8AF94257459C33565E5CC3F7E8000000000000000000000000000000000100000000000000000000000000000000000000000000007F010000000000000002010300000000100FA2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000600000000000000000000000000000000000000000000000000000000000000000000000000000007000000000000000600000000000000100FA20000080C060B32D87EFFFB8B170000000000000000000000000000000000000000000000000000000000000000F50157A5EFE3DE43AC72249B573FAD2C01000000000000009F00140600000000000000000000000000000000000000000000000000000000000000000000000002000000020000005079567A454CD701060000000000000000000000000000000000000005000000500103000000A0BA000000000000000000000000FE0F1AD0000000000600000000000000B00005000200004D00000000F9010000230000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</Data>
  </EventData>
</Event>

very much hate taking a keyboard apart due to sticky substances being spilled on it
lucky enough no actual damage done....


----------



## craxton

RonLazer said:


> Just some testing I did with Aida64 latency (its just the most consistent measure of memory performance, even though its only vaguely correlated with "real" benchmarks) and you can clearly see the effect of different "fclk domains" with respect to memory training:
> 
> View attachment 2511773
> 
> 
> X570 Dark Hero, AGESA 1.1.19, SMU 56.43.00, 5600X was static 4.8GHz, DRAM timings were like 12-12-12-24-48 + 100ns of tRFC + tight subs. I didn't tune the SOC/IOD/CCD/PLL/DRAM voltages for each frequency, just used the ones for 2000MHz across the full range. I did try tuning for 2000MHz but the lowest I could get the latency was like 49.5ns at 2003MHz so it was pointless.
> 
> Up till 1867Mhz it scales linearly, at 1900MHz the link-training switches to something else which is about 0.4ns slower but then continues to scale linearly down to 2000MHz, then the latency spikes and needs excessively high voltages to retrieve some of the lost latency.
> 
> Linpack scales to about 1900Mhz, then takes a big hit at 1933MHz, and totally bottoms out at 2000MHz. Performance is crap at 2033MHz regardless of voltages.
> 
> SuperPi 32M scales the entire range to 200MHz, but also falls apart at 2033MHz.


those are some expensive kits, 
how much of a difference with PBO/CO? 

(im pushing sub 51.4 in safe mode) but not on static all core.


----------



## craxton

hazium233 said:


> I think I need to take out my 5600X and drop it on the ground like craxton before I will be able to get 2000 FCLK to work without WHEA out the Wazzoo


no no now,
mine wasnt dropped on the floor....was dropped inside the case and smacked the 2070s ftw3 ultras heatsink lol

(i havent mentioned this in months) but none the less i wondered if it does have anything at all to do 
with any of my WHEA (mostly) free logs.


----------



## RonLazer

craxton said:


> those are some expensive kits,
> how much of a difference with PBO/CO?
> 
> (im pushing sub 51.4 in safe mode) but not on static all core.


Just some 3200 CL14 dimms nothing special. I just wanted to eliminate memory latency as much as possible to see the effect of pure FCLK scaling.


----------



## Robostyle

ManniX-ITA said:


> If you get sound issues you probably need to raise VDDG IOD and VSOC.
> 
> No it could be also an hardware problem.
> Or a BIOS/Firmware issue. Or a combination of multiple issues.
> We don't know for sure.
> But if you are confident it can run it reliably and you get too many errors, which will slow down the system, you can silence them.


Yeah, sound problems are mostly related to IOD - setting VDDG/VDDP voltages to ~1.1V solves the issue, no sound artifacts at least, but I do get performance and latency penalty compared to something liket 3866MHz - dunno, maybe it needs some additional tweaking.
I don't like these voltages though - even if I cool it with velocity fullnickel, CPU temps go around 79-85C all the time because of this amd's boosts with "up to 1.5 vCore"

And no additional voltages helps me to get rid of this Bus errors, starting from 3800:1900 and higher. As well as whea 19 logs.

Other than that, everything looks fine - at least without major problems. No BSODs, no reboots, HCI memtest runs stable up to 200%, general perfomance is at "level" aswell. Only these WHEA errrors and logs. Hope it WILL be solved, cause I have my doubts due to asus 3501 BETA stuck for 2 months already. I really don't want this platform to give me regrets that I didn't go with 10900K


----------



## RonLazer

Robostyle said:


> Yeah, sound problems are mostly related to IOD - setting VDDG/VDDP voltages to ~1.1V solves the issue, no sound artifacts at least, but I do get performance and latency penalty compared to something liket 3866MHz - dunno, maybe it needs some additional tweaking.
> I don't like these voltages though - even if I cool it with velocity fullnickel, CPU temps go around 79-85C all the time because of this amd's boosts with "up to 1.5 vCore"
> 
> And no additional voltages helps me to get rid of this Bus errors, starting from 3800:1900 and higher. As well as whea 19 logs.
> 
> Other than that, everything looks fine - at least without major problems. No BSODs, no reboots, HCI memtest runs stable up to 200%, general perfomance is at "level" aswell. Only these WHEA errrors and logs. Hope it WILL be solved, cause I have my doubts due to asus 3501 BETA stuck for 2 months already. I really don't want this platform to give me regrets that I didn't go with 10900K


If the temperatures or voltages are scaring you then you can just reduce the PPT in the PBO menu, or even just set a lower thermal limit. I don't know why you'd assume AMD/TSMCs semiconductor engineers don't know what they're doing, you'll never see 1.5V under actual loads if you use a proper monitoring software with snapshot polling, and 90C is absolutely fine for heavy loads. Remember that Intel and AMD report temperatures very differently and use entirely different process nodes so what's an unsafe temp/voltage on one is not necessarily unsafe on the other.


----------



## craxton

quick question, the ryzen google calc
has been updated, and these updates no longer allow "manual" options,
i suppose using the recommended selections will be the proper way to go?

found two values that it wants quite a bit lower than mine.....
tRRD_L
and tRDWR
actually quite a few other things thats been updated....

since the values given, and mine (some are on testing only use caution)
i suppose ill give whats given a shot......

(EDIT) UPDATE- hard lock for the values recommended
unsure if it was user error, or the fact that im running 2t (did swtch to 1t GDM off) but none the less,
failed to post)

hmmmmmmmm

(reedit) before it wouldnt allow me to change a few things, telling me i didnt have
rights to do so etc. now its allowing manual values to be added where it wouldnt before.
to which, no error is detected? 
im super confused. 


oh, tRDWR 9 will not post on my 4x8 2t config. 11-10 work but 9-8 will not...
unsure if setup timings 4-4-18 are countering anything here, but cannot go lower than 10
even tho 9 is the correct value to use, (ruleset implies 10)


----------



## lmfodor

craxton said:


> quick question, the ryzen google calc
> has been updated, and these updates no longer allow "manual" options,
> i suppose using the recommended selections will be the proper way to go?
> 
> found two values that it wants quite a bit lower than mine.....
> tRRD_L
> and tRDWR
> actually quite a few other things thats been updated....
> 
> since the values given, and mine (some are on testing only use caution)
> i suppose ill give whats given a shot......
> 
> (EDIT) UPDATE- hard lock for the values recommended
> unsure if it was user error, or the fact that im running 2t (did swtch to 1t GDM off) but none the less,
> failed to post)
> 
> hmmmmmmmm
> 
> (reedit) before it wouldnt allow me to change a few things, telling me i didnt have
> rights to do so etc. now its allowing manual values to be added where it wouldnt before.
> to which, no error is detected?
> im super confused.
> 
> 
> oh, tRDWR 9 will not post on my 4x8 2t config. 11-10 work but 9-8 will not...
> unsure if setup timings 4-4-18 are countering anything here, but cannot go lower than 10
> even tho 9 is the correct value to use, (ruleset implies 10)


Hi Craxton! Did you try 8/4? I had the same issue when trying to lower from 10.. in fact I actually have 10-1.. but can go to 8-4 just to try 


Sent from my iPhone using Tapatalk Pro


----------



## craxton

lmfodor said:


> Hi Craxton! Did you try 8/4? I had the same issue when trying to lower from 10.. in fact I actually have 10-1.. but can go to 8-4 just to try
> 
> 
> Sent from my iPhone using Tapatalk Pro


already running 10-4 so thus 8-4 or 9-4 as ive tried only changing WRRD to before
will not work....


----------



## craxton

@RonLazer any update on those logs, and possibly knowing if it is indeed ram related or just
where i mess with CURVE so much?


----------



## jankaw

RonLazer said:


> you'll never see 1.5V under actual loads if you use a proper monitoring software with snapshot polling


Hi, I'm running a 5600x using HWiNFO to monitor 
running -25 co with 50mv positive offset, 
I see 1.5v on all cores as a "max" voltage range from time to time

Not during YouTube or chrome usage usually and average voltage is 1.3x-1.35 would this
be considered safe?


----------



## craxton

not gonna lie, going crazy wondering why the silence fellas....
(DID I PISS OFF SOMEONE with my post to torq, or was it the name of my PC?)


----------



## hazium233

craxton said:


> already running 10-4 so thus 8-4 or 9-4 as ive tried only changing WRRD to before
> will not work....
> View attachment 2511868


RDWR_min depends in part on the difference between CL and CWL. If you increased CWL by 2, you should be able to 8 on RDWR. But there won't be much point in doing that.

...

As a different question, are you running your GPU or sound drivers via Message Signal Interrupt? I was wondering if maybe WHEA 19 spam could in part relate to that since I set all of mine this way.

Otherwise, maybe I needed to be more aggressive with VRM settings and or voltage. I think I had 800 kHz on SOC when I tested before, haven't really used much other than that. Last strap I sort of tested was just 3733 / 1866 where I left all LLC on Auto and even switching to default.

Also, nobody has happened to mod any of the bioses to fully unlock anything have they? And I think I read you said MSI doesn't seem interested in doing it.


----------



## craxton

hazium233 said:


> Otherwise, maybe I needed to be more aggressive with VRM settings and or voltage


my VRM switching is set to 700khz LLC cpu is llc2 *msi, SOC/northbridge LLC4 1000khz



hazium233 said:


> are you running your GPU or sound drivers via Message Signal Interrupt?


i dont have HDMI audio drivers installed although windows installed them automatically,
i KEEP THEM DISABLED. as for message signal interrupt, im unsure what this means honestly?
if you can explain in simple terms, i use latest nvidia driver, with phyX, and geforce now, bout it for GPU with ALL redist files, installed.



hazium233 said:


> Also, nobody has happened to mod any of the bioses to fully unlock anything have they


Veii i do believe shared a modded MSI b550 gaming edge wifi bios (quite some pages back)
but i wasnt sure if thats what he meant, or how i was to flash it as ive never flashed
a bios to a motherboard without it being verified etc.
have to GPU's using eprom/cha4 flasher-USB

but if he hasnt removed the file from his upload link youll find it a month or so back somewhere around

and no MSI isnt interested in CPU VDDP at all and states its only for APU/cpu's with integrated graphics installed already.

they have said this to several of us here. (i do know that some things even while being unlocked those with these unlocked
features/options etc, cant verify some do anything at all, while some do very little while others just simply show up inside the bios.)

on the B550 gaming edge, CPU-VDDP voltage is shown inside the bios, but its shown CPU-VDDP= N/A
so i dont think itll register to be monitored even if it were unlocked sadly..

oh, Veii is more focusing on music now, he may stop by from time to time. but
without him here, this thread may die out.....even tho its by far one of the greatest things to AMD
to date upon where people can turn to for BOOKS of information.

if you check a few others profiles some have been silent for a few days now.
if i can find the post that was made, about unlocking features yourself ill post it to you in this comment,
look for an underlined edit.

even HWiNFO shows CPU_VDDP voltage but its shown as .1 for a moment then disappears

(EDIT @hazium233 sadly the file Veii had uploaded is no longer valid. i did ping/chime him in, but i fear itll not do much good.)
i searched for quite sometime tho. sorry.


----------



## Sleepycat

jankaw said:


> Hi, I'm running a 5600x using HWiNFO to monitor
> running -25 co with 50mv positive offset,
> I see 1.5v on all cores as a "max" voltage range from time to time
> 
> Not during YouTube or chrome usage usually and average voltage is 1.3x-1.35 would this
> be considered safe?


If you enter a 50mV positive offset, that will naturally push the typical 1.45V max single core voltage up to 1.50V. Personally I used to use PBO with curve optimiser set per core and the positive offset was 0. Nowadays I just use CTR 2.1 to manually set my voltage and clockspeed to each load scenario.


----------



## craxton

Veii said:


> Quite honestly I would use the tool and permanently change it, if there is no way to make "the category" and "the field" visible, after setting it to USER
> 
> Haven't seen any CPU which does behave negatively with 880mV CPU VDDP
> While 900 works and is questionable what is better beyond 2133
> 880mV was certainly needed for 2100 to pass all the y-cruncher torture. Well and tCKE , but that's been my dimms exclusive under 4200C16-16
> 
> Testflash this, and see if you can see all the changes
> E7C91AMS.16(3)
> 
> 
> 
> 
> 
> 
> 
> 
> MyAirBridge.com | Send or share big files up to 20 GiB for free
> 
> 
> We will transfer your files easily, safely and rapidly from one place to another. You can send them directly to an email address or share files using a unique link.
> 
> 
> 
> 
> mab.to
> 
> 
> 
> 
> 1.2.0.1 has interesting Vermeer and Cezanne specific override features
> And seems to feature STAMP mode too + telemetry offset override ~ for tricking the boost system in thinking you have more power reserves
> Usually asus does use this
> 
> You can open and take a look , but not only do you change the window flag inside one category, but also go outside and change the corresponding category to "user"
> A pyramid system of permissions. Even if the little field has user permission, it won't make a change if the higher hierarchy denies it


apologies, if you would resend a valid link, ill GREATLY leave you be....(understand quite a bit better now)
back then was barely able to read correctly let alone speak my own language


----------



## hazium233

craxton said:


> my VRM switching is set to 700khz LLC cpu is llc2 *msi, SOC/northbridge LLC4 1000khz


Interesting. I haven't tested the LLC steps very well with the 5600X, the 2700X on here needed basically either SOC LLC mode 3 or Auto else it would drop sporadic test 12 error somewhere around cycle 18 or higher.



> i dont have HDMI audio drivers installed although windows installed them automatically,
> i KEEP THEM DISABLED. as for message signal interrupt, im unsure what this means honestly?
> if you can explain in simple terms, i use latest nvidia driver, with phyX, and geforce now, bout it for GPU with ALL redist files, installed.


This is the interrupt mode, if you haven't heard of it then nvidia GPU drivers default to legacy for Windows. You have to make a registry edit, or use something like MSI Mode Utility 2.0 to switch. MSI being Message Signal Interrupt, not MicroStar International. 

Generally DPC looks a lot better with everything set to MSI on Ryzen, so I have been doing that since my 1600.



> Veii i do believe shared a modded MSI b550 gaming edge wifi bios (quite some pages back)
> but i wasnt sure if thats what he meant, or how i was to flash it as ive never flashed
> a bios to a motherboard without it being verified etc.


I will be going through the thread more with time. I am getting demotivated when I go through the bios and there are many missing features.

I had downloaded flashrom a long time ago, but only used it to read and backup bioses. Really I have done very little with bios editing and the split bios images seem a lot more troublesome than the old days on B350 or X370 with only Summit and Pinnacle where some simple edits in AMIBCP could be flashed on my Asus boards.

I think 3733 16-18/19-18-38-56 was ok enough, so I think I will take a look at FCLK 1933 tonight and see what happens with it. Need to probably try GDM off 2T as well.

It also seems like there isn't as much on dual rank Rev E for Vermeer as I expected, although there are a few pretty high results.


----------



## craxton

hazium233 said:


> will be going through the thread more with time. I am getting demotivated when I go through the bios and there are many missing features.











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


It is completely stable, HCI 200%, etc. Can go stable even at RAM 4000: FCLK 2000, but I get sound issues then. So, this is BIOS/software problem, not the hardware, right? If you get sound issues you probably need to raise VDDG IOD and VSOC. No it could be also an hardware problem. Or a...




www.overclock.net





i found where he shared it, both sites in fact. but both are gone...unsure what ive said
and have not said, 12 hour work day today and then mowing the dam yard jus now got me weak...none the less tho,
i think there actually is not to far back about REV e kits unsure about DR tho, but 4x8 is nearly the same as 2x16 in most timing instances if
i recall, again, i did find the page where Manna and Veii both stated these are "their" rulesets and what they have found work for most
but not all...im in no way eager to go back and find the page on REV e tho, not atm....

i think i have it saved, ill link EVERY SAVED POST
i ever made, its up to you to look at it tho. (included stuff relevant to anyone, and a few things only i would use, or a select few)


Thread 'AGESA FW stack patched bioses for 3rd gen'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread 'AMD max overclocking voltage'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread 'CoreCycler - tool for testing Curve Optimizer settings'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread 'Ryzen Google Calculator!'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'



*For all who wish to fast travel to KEY PARTS of tuning or seeing what was said, about what feature set/ruleset/LIMITS ram, FCLK, VOLTAGES, EDC/ppt/tdc and LOADS of other stuff, *

_*if someone wishes to take sometime and properly name these (important ones of course, then i did some of the harder work for you which was finding it to begin with) Veii, Manna, Mongol, and ANYONE ELSE who played a part will be in the links, there are also scripts/edits to stop WHEA logs, and windows (certain ones) from running)*_

thank you fellas for the collage course (FREE) lessons. Wont forget it (what i could learn) EVER!

(P.S.) some may be duplicated, im unsure, but DO NOT CLICK A LINK WITHOUT CHECKING THE REST OF THAT PAGE! *INFO IS EVERYWHERE*
and Its commented to just about anyone who asked (properly) theres way more than what i saved. but none the less- maybe if others who saved stuff i didnt see could get 
together we can make some actual data to form something together on all this to share with ALL WHO WISH TO KNOW! (ON SITE AND OFF)


----------



## jomama22

craxton said:


> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> It is completely stable, HCI 200%, etc. Can go stable even at RAM 4000: FCLK 2000, but I get sound issues then. So, this is BIOS/software problem, not the hardware, right? If you get sound issues you probably need to raise VDDG IOD and VSOC. No it could be also an hardware problem. Or a...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> i found where he shared it, both sites in fact. but both are gone...unsure what ive said
> and have not said, 12 hour work day today and then mowing the dam yard jus now got me weak...none the less tho,
> i think there actually is not to far back about REV e kits unsure about DR tho, but 4x8 is nearly the same as 2x16 in most timing instances if
> i recall, again, i did find the page where Manna and Veii both stated these are "their" rulesets and what they have found work for most
> but not all...im in no way eager to go back and find the page on REV e tho, not atm....
> 
> i think i have it saved, ill link EVERY SAVED POST
> i ever made, its up to you to look at it tho. (included stuff relevant to anyone, and a few things only i would use, or a select few)
> 
> 
> Thread 'AGESA FW stack patched bioses for 3rd gen'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread 'AMD max overclocking voltage'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread 'CoreCycler - tool for testing Curve Optimizer settings'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread 'Ryzen Google Calculator!'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> 
> 
> *For all who wish to fast travel to KEY PARTS of tuning or seeing what was said, about what feature set/ruleset/LIMITS ram, FCLK, VOLTAGES, EDC/ppt/tdc and LOADS of other stuff, *
> 
> _*if someone wishes to take sometime and properly name these (important ones of course, then i did some of the harder work for you which was finding it to begin with) Veii, Manna, Mongol, and ANYONE ELSE who played a part will be in the links, there are also scripts/edits to stop WHEA logs, and windows (**certain** ones) from running)*_
> 
> thank you fellas for the collage course (FREE) lessons. Wont forget it (what i could learn) EVER!


I'm glad you are enthusiastic but there is no need for the massive red lettering lol.


----------



## craxton

jomama22 said:


> massive red lettering


you been around since i can remember, so you must not be thinking about the questions that came out
that literally were answered on the same page lol.....thus the big red lettering...i can change the color tho,


----------



## craxton

did anyone else see the "leak" AM5 is LGA1718??????????


----------



## RonLazer

craxton said:


> @RonLazer any update on those logs, and possibly knowing if it is indeed ram related or just
> where i mess with CURVE so much?


If they only show up when you undervolt too much with curve-optimiser then it's safe to assume they're not DRAM related errors.


----------



## RonLazer

For anyone invested in this saga, sadly Asus's "Promontory Presence" doesn't actually do what it says in the BIOS and disable the Southbridge (aka the chipset). I'll email their support and see what's up with that. Sadly no way to test if these WHEA 19s are caused by a motherboard component or the CPU for now. 

If I can find a way to disable the chipset then I should be able to test this as I've checked the Dark Hero block diagram and the 1st PCIE slot, 4 USB ports, and the 1st M.2 slot all connect directly to the CPU, so its very possible to run an OS with most of the motherboard disabled - and there's no way for any LAN components to interact with the CPU without going via the chipset.


----------



## ManniX-ITA

RonLazer said:


> For anyone invested in this saga, sadly Asus's "Promontory Presence" doesn't actually do what it says in the BIOS and disable the Southbridge (aka the chipset). I'll email their support and see what's up with that. Sadly no way to test if these WHEA 19s are caused by a motherboard component or the CPU for now.


Thanks let us know, it'd be really interesting to test

In the meantime I've decoded the WHEA raw values and preparing an app that can show both the MCA/MCI and all the rest parsed and decoded in understandable terms.
Better than windbg kernel mode output. Not sure if it can really help us out but still better than not knowing.
Unfortunately I'm miserable with UI and spent the last 2 days trying to understand how WPF works.
I'm finally somewhere with an ugly event log browser and I'll start working on the decoding this week.


----------



## PJVol

craxton said:


> any update on those logs, and possibly knowing if it is indeed ram related or just
> where i mess with CURVE so much?


Just after a brief look at WHEA 18 logs, bank 5 indicates EX (execution unit) error - "Immediate displacement register file parity error ".

Error code itself says (if I didn't confused byte order):

Transaction type: Instruction
Cache level: Core
Memory transaction type: Instruction fetch
PCC bit is set, so it is unrecoverable and reboot should follow.

From MISC:

Thresholded interrupt type - APIC
LVT offset - 0x1
Threshold value FFF (i.e. 1 error to take interrupt)
Error count 0xFFE / Overflow - 0

As for 20's ... they don't seem like MCE raised, since ETW didn't parse raw data, and in that case one may suggest corrected errors reported via SMI or LVT. Maybe @ManniX-ITA will clarify  , exracting CTL, STATUS and MISC registers data.

PS: In the pre-Family17h times (as per BKDG), the 20 meant uncorrected fatal AMDNB error.


----------



## hazium233

This WHEA saga is about 19 from ErrorSource 0 only, is that correct?

I read through the WHEA Suppressor thread, read through links craxton had posted, and had already used search through this thread earlier for hints. Took away some debug time. But I am missing something.

At which rate or frequency can one say "these can now be ignored"? And if you are trying to test a frequency, do you just go about testing and ignore these specific errors?

I looked a bit at 3866 - 1933 last evening before I had to step away for a while, I could pretty reliably get WHEA 19 when I ran y cruncher FFT + N64, each test 2 minutes for 20 minutes total. N64 seemed to give 5-6 of these per loop the different boots / tests I ran it. Hour of TM5 previously had 50 total.


----------



## ManniX-ITA

PJVol said:


> Maybe @ManniX-ITA will clarify  , exracting CTL, STATUS and MISC registers data.


I'll probably need some help to make it right 



hazium233 said:


> At which rate or frequency can one say "these can now be ignored"? And if you are trying to test a frequency, do you just go about testing and ignore these specific errors?


There's not a specific rate.
If you don't get hundreds and more per minute it'd be better to try to find better settings as the IF could be unstable.
If they are a few definitely better to not suppress them and keep them recorded in the logs.

Those incoming from the DeviceDriver source are the dubious ones.
The others can and usually have a meaning.

In general the best you can do now is to test the performances are right and the system is stable.
I'd make first 25 cycles of TM5.
Test for performances making sure there are no regressions but only improvements.
Then at least 10 y-cruncher stress test iterations and CoreCycler (with y-cruncher not P95) for a whole night.


----------



## PJVol

ManniX-ITA said:


> I'll probably need some help to make it right


What was the WHEA_DEVICE_DRIVER_DESCRIPTOR fileld in those Type 16 errors you've had?


----------



## craxton

PJVol said:


> Just after a brief look at WHEA 18 logs, bank 5 indicates EX (execution unit) error - "Immediate displacement register file parity error ".
> 
> Error code itself says (if I didn't confused byte order):
> 
> Transaction type: Instruction
> Cache level: Core
> Memory transaction type: Instruction fetch
> PCC bit is set, so it is unrecoverable and reboot should follow.
> 
> From MISC:
> 
> Thresholded interrupt type - APIC
> LVT offset - 0x1
> Threshold value FFF (i.e. 1 error to take interrupt)
> Error count 0xFFE / Overflow - 0
> 
> As for 20's ... they don't seem like MCE raised, since ETW didn't parse raw data, and in that case one may suggest corrected errors reported via SMI or LVT. Maybe @ManniX-ITA will clarify  , exracting CTL, STATUS and MISC registers data.
> 
> PS: In the pre-Family17h times (as per BKDG), the 20 meant uncorrected fatal AMDNB error.


thank-you

but as most of what your saying to me is piglatin i still dont understand. so its pointless to explain to me. 

WHEA is by far the biggest language barrier ive came across that i couldn't understand a few "words" in lol

but since its been a few days now, since ive had any errors, crashes, etc from 20 or 18
i think (what i did was allowed 300mv overvoltage protection, which what i believe it does (is allow 
300mv of overvolting?) 

i only think that since when i set it to 150 it wont go over a certain voltage range, bumping to 350 it hits a higher target.
then again, that could be something inside windows pushing voltage up unsure. 

none the less, switching to 700khz cpu, leaving 1000khz soc/nb, and the overvoltage protection overshoot have 
countered the error 18 i was having. as i have not changed any timings....(although i did change IOD, CCD voltages WAY DOWN 
IOD was 1070mv is now .990mv CCD was only -10mv drop or so. but have been clear for a few days while the pc stays on
constantly and ive gammed more these few days than this entire year (while not working) (days gone running pretty good)

i ran integrity checks etc, nothing came back on that either. 

i also ran an hours worth of OCCT, and re-ran y-cruncher in loop for a few hours. 
(only problem i have now is hibernating dont wanna wake up one out of ten times)


----------



## ManniX-ITA

PJVol said:


> What was the WHEA_DEVICE_DRIVER_DESCRIPTOR fileld in those Type 16 errors you've had?


I'm not yet sure that is there as I didn't finish the manual decoding.
In theory should be there, maybe later in the second part of the packet.
There are 3 sections and I stopped at first.

The error record is described in ntddk.h.

Have to decode it via coding as manually is exhausting 



Spoiler: Manual decoding WHEA






Code:


HEADER:

43504552                            WHEA_ERROR_RECORD_SIGNATURE Signature: REPC = CPER
1002                                WHEA_ERROR_RECORD_REVISION  Revision: 0x0210
FFFFFFFF                            WHEA_ERROR_RECORD_SIGNATURE_END SignatureEnd: 0xFFFFFFFF
0300                                SectionCount: 0x003
02000000                            Severity: 0x00000002 (Corrected Error)
02000000                            ValidBits: 0x00000002 (2)
    WHEA_ERROR_RECORD_HEADER_VALIDBITS ValidBits;
    _Field_range_(>=, (sizeof(WHEA_ERROR_RECORD_HEADER)
                       + (SectionCount
                          * sizeof(WHEA_ERROR_RECORD_SECTION_DESCRIPTOR))))
A8030000                            Length: 0x0000038A (8)
22070E0016051514                    Timestamp:
00000000000000000000000000000000    PlatformId:
00000000000000000000000000000000    PartitionId:
BDC407CF89B7184EB3C41F732CB57131    CreatorId:
B248949139377F4BA8F1E0062805C2A3    NotifyType:
49971ECB134FD701                    RecordId:
00000000                            Flags:
0000000000000000                    PersistenceInfo:
0000000000000000                    Reserved

SECTION DESCRIPTION:

58010000                            SectionOffset
C0000000                            SectionLength
0003                                Revision
00                                  ValidBits
00                                  Reserved
01000000                            Flags
ADCC7698B447DB4BB65E16F193C4F3DB    SectionType
00000000000000000000000000000000    FRUId
02000000                            SectionSeverity
00000000000000000000000000000000    FRUtext

WHEA_PROCESSOR_GENERIC_ERROR_SECTION

0000000018020000                ValidBits
8                               ProcessorType   
0                               InstructionSet
0                               ErrorType
0                               Operation
0                               Flags
0                               Level
00                              Reserved
0003000000000000                CPUVersion
B0A03EDC44A19747B95B53FA242B6E1D0000000000000000000000000000000002000000000000000000000000000000000000000000000098020000100100000003000000000000011D1E8AF94257459C33565E5CC3F7E800000000000000000000000000000000020000000000000000000000000000000000000000000000 CPUBrandString
7F01000000000000                ProcessorId
0002040000030000                TargetAddress
100FA20000000000                RequesterId
0000000000000000                ResponderId
0000000000000000                InstructionPointer


----------



## craxton

PSA: ill be buying the board Veii mentioned to be WHEA # free sometime this afternoon, 
it should arrive within a few days hopefully. ill post if i trigger the ones he stated it didnt have
(if someone can refresh what ERROR code it was this board was free from)
if not ill find it im sure. none the less, need more hardware. 

might instead get another 5600x or still get the board, and see if WHEA triggers are present 
on the 3600xt since they was with this board while using the 3600xt (which was only weeks old)


----------



## PJVol

ManniX-ITA said:


> I'm not yet sure that is there as I didn't finish the manual decoding.


In your GetSourceInfo() method, where you reading binary data, the Info variable is basically a union from the structure below, which in case *esType *= *WheaErrSrcTypeDeviceDriver*, is WHEA_DEVICE_DRIVER_DESCRIPTOR type data:



Spoiler: WHEA_ERROR_SOURCE_DESCRIPTOR






C++:


typedef struct _WHEA_ERROR_SOURCE_DESCRIPTOR {
  ULONG                   Length;
  ULONG                   Version;
  WHEA_ERROR_SOURCE_TYPE  Type;
  WHEA_ERROR_SOURCE_STATE State;
  ULONG                   MaxRawDataLength;
  ULONG                   NumRecordsToPreallocate;
  ULONG                   MaxSectionsPerRecord;
  ULONG                   ErrorSourceId;
  ULONG                   PlatformErrorSourceId;
  ULONG                   Flags;
  union {
    WHEA_XPF_MCE_DESCRIPTOR          XpfMceDescriptor;
    WHEA_XPF_CMC_DESCRIPTOR          XpfCmcDescriptor;
    WHEA_XPF_NMI_DESCRIPTOR          XpfNmiDescriptor;
    WHEA_IPF_MCA_DESCRIPTOR          IpfMcaDescriptor;
    WHEA_IPF_CMC_DESCRIPTOR          IpfCmcDescriptor;
    WHEA_IPF_CPE_DESCRIPTOR          IpfCpeDescriptor;
    WHEA_AER_ROOTPORT_DESCRIPTOR     AerRootportDescriptor;
    WHEA_AER_ENDPOINT_DESCRIPTOR     AerEndpointDescriptor;
    WHEA_AER_BRIDGE_DESCRIPTOR       AerBridgeDescriptor;
    WHEA_GENERIC_ERROR_DESCRIPTOR    GenErrDescriptor;
    WHEA_GENERIC_ERROR_DESCRIPTOR_V2 GenErrDescriptorV2;
    WHEA_DEVICE_DRIVER_DESCRIPTOR    DeviceDriverDescriptor;
  } Info;
} *PWHEA_ERROR_SOURCE_DESCRIPTOR, WHEA_ERROR_SOURCE_DESCRIPTOR;







Spoiler: WHEA_DEVICE_DRIVER_DESCRIPTOR






C++:


typedef struct _WHEA_DEVICE_DRIVER_DESCRIPTOR {
  USHORT                             Type;
  BOOLEAN                            Enabled;
  UCHAR                              Reserved;
  GUID                               SourceGuid;
  USHORT                             LogTag;
  USHORT                             Reserved2;
  ULONG                              PacketLength;
  ULONG                              PacketCount;
  PUCHAR                             PacketBuffer;
  WHEA_ERROR_SOURCE_CONFIGURATION_DD Config;
  GUID                               CreatorId;
  GUID                               PartitionId;
  ULONG                              MaxSectionDataLength;
  ULONG                              MaxSectionsPerRecord;
  PUCHAR                             PacketStateBuffer;
  LONG                               OpenHandles;
} WHEA_DEVICE_DRIVER_DESCRIPTOR, *PWHEA_DEVICE_DRIVER_DESCRIPTOR;





What's left is to parse it and see if it has valuable data, i.e. driver uid, etc. 
Or just post the raw *WHEA_ERROR_SOURCE_DESCRIPTOR *data

Wondering, are we looking at the same docs ? 








_WHEA_ERROR_SOURCE_DESCRIPTOR (ntddk.h) - Windows drivers


The WHEA_ERROR_SOURCE_DESCRIPTOR structure describes an error source.



docs.microsoft.com


----------



## ManniX-ITA

PJVol said:


> In your GetSourceInfo() method, where you reading binary data, the Info variable is basically a union from the structure below, and if esType points to DeviceDriver as source, then that Info field contains WHEA_DEVICE_DRIVER_DESCRIPTOR type data:


The GetSourceInfo it's querying the error sources not the actual errors 

From my understanding via WMI you can query and operate on the sources and inject an error, that's all.









WHEA Management Operations - Windows drivers


WHEA Management Operations



docs.microsoft.com





To access the actual errors information you need to read the event log.

What I'm parsing is the RawData in the XML structure:



Code:


435045521002FFFFFFFF03000200000002000000A803000022070E00160515140000000000000000000000000000000000000000000000000000000000000000BDC407CF89B7184EB3C41F732CB57131B248949139377F4BA8F1E0062805C2A349971ECB134FD70100000000000000000000000000000000000000000000000058010000C00000000003000001000000ADCC7698B447DB4BB65E16F193C4F3DB0000000000000000000000000000000002000000000000000000000000000000000000000000000018020000800000000003000000000000B0A03EDC44A19747B95B53FA242B6E1D0000000000000000000000000000000002000000000000000000000000000000000000000000000098020000100100000003000000000000011D1E8AF94257459C33565E5CC3F7E8000000000000000000000000000000000200000000000000000000000000000000000000000000007F010000000000000002040000030000100FA2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007000000000000000000000000000000100FA200000820000B32D87EFFFB8B170000000000000000000000000000000000000000000000000000000000000000B3F8F31CB1C5A249AA595EEF92FFA63C01000000000000009E07C000040000000000000000000000000000000000000000000000000000000000000000000000020000000200000017BD1ED0134FD70100000000000000000000000000000000000000001B0000000B08020000002098000000000000000000000000FE0F1AD00000000000000000000500002E0001000100025A000000007D000000270000000000000000000000000000000000000000000000000010000000000000001000000000000000100000000000000010003B00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

Together with the MCI stuff should be everything that's available from a WHEA error.



PJVol said:


> Wondering, are we looking at the same docs ?


Yes as well 
Mostly I'm following what's inside the ntddk.h, I have the DDK installed.


----------



## PJVol

ManniX-ITA said:


> What I'm parsing is the RawData in the XML structure:


Can you post just *Flags* and *Info* value itself (not its length) in hex, obtained here ?


C++:


                            Flags = reader.ReadInt32();
                            Info = reader.ReadBytes(InfoSeek)


----------



## ManniX-ITA

PJVol said:


> Can you post just *Flags* and *Info* value itself (not its length) in hex, obtained here ?
> 
> 
> C++:
> 
> 
> Flags = reader.ReadInt32();
> Info = reader.ReadBytes(InfoSeek)


You mean from the error source?

Of course you mean it.... 



Code:


ERROR 0 Flags: 0
ERROR 0 Info Length: 932
ERROR 0 Info: 000000003C60C1835215A74887D114D9467D776550530000D80E000001000000100014B383B5FFFFF0180D7406F8FFFF10190D7406F8FFFF6037167006F8FFFF8D7C2157665EFB4480339B74CACEDF5B00000000000000000000000000000000640400000100000010F59FB083B5FFFF00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

But my understanding is the source is generic and doesn't hold the information about the underlying driver source.


----------



## PJVol

I mean what value those two variables have when after your code execution passed those two lines.
ps: yes, from the error source, I want to find them in whea error raw data from event log.


----------



## ManniX-ITA

PJVol said:


> I mean what value those two variables have when after your code passed thosr two lines.


Yes sorry I'm tired...
Added above, that's for the ErrorSourceID 0 Type 16


----------



## hazium233

craxton said:


> PSA: ill be buying the board Veii mentioned to be WHEA # free sometime this afternoon,
> it should arrive within a few days hopefully. ill post if i trigger the ones he stated it didnt have
> (if someone can refresh what ERROR code it was this board was free from)
> if not ill find it im sure. none the less, need more hardware.
> 
> might instead get another 5600x or still get the board, and see if WHEA triggers are present
> on the 3600xt since they was with this board while using the 3600xt (which was only weeks old)


Which motherboard is that?


----------



## ManniX-ITA

PJVol said:


> I mean what value those two variables have when after your code execution passed those two lines.
> ps: yes, from the error source, I want to find them in whea error raw data from event log.


I tried to parse the Info block but something is off...



Spoiler



Made this to parse the Info:



Code:


                           if (Info.Length > 0 && TypeEs == 16)
                            {
                                using (var infoms = new MemoryStream()) {
                                    infoms.Write((byte[])Info, 0, Info.Length);
                                    infoms.Position = 0;
                                    using (BinaryReader inforeader = new System.IO.BinaryReader(infoms))
                                    {
                                        int recs = 1;
                                        while (recs <= NumRecordsToPreallocate) {
                                            long iPosition = infoms.Position;
                                            int iType = inforeader.ReadInt16();
                                            byte iEnabled = inforeader.ReadByte();
                                            int iReserved = inforeader.ReadByte();
                                            Guid iSourceGuid = Guid.Parse(BitConverter.ToString(inforeader.ReadBytes(16)).Replace("-", ""));
                                            int iLogTag = inforeader.ReadInt16();
                                            int iReserved2 = inforeader.ReadInt16();
                                            int iPacketLength = inforeader.ReadInt32();
                                            int iPacketCount = inforeader.ReadInt32();
                                            byte iPacketBuffer = inforeader.ReadByte();
                                            int iConfig = inforeader.ReadInt32();
                                            Guid iCreatorId = Guid.Parse(BitConverter.ToString(inforeader.ReadBytes(16)).Replace("-", ""));
                                            Guid iPartitionId = Guid.Parse(BitConverter.ToString(inforeader.ReadBytes(16)).Replace("-", ""));
                                            int iMaxSectionDataLength = inforeader.ReadInt32();
                                            int iMaxSectionsPerRecord = inforeader.ReadInt32();
                                            byte iPacketStateBuffer = inforeader.ReadByte();
                                            int iOpenHandles = inforeader.ReadInt32();

                                            WHEAservice.WHEAService.EventErr(i + " iPosition: " + iPosition.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iType: " + iType.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iEnabled: " + iEnabled.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iSourceGuid: " + iSourceGuid.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iLogTag: " + iLogTag.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iConfig: " + iConfig.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iCreatorId: " + iCreatorId.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iPartitionId: " + iPartitionId.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iMaxSectionDataLength: " + iMaxSectionDataLength.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iMaxSectionsPerRecord: " + iMaxSectionsPerRecord.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iPacketStateBuffer: " + iPacketStateBuffer.ToString());
                                            WHEAservice.WHEAService.EventErr(i + " iOpenHandles: " + iOpenHandles.ToString());

                                            recs++;
                                        }
                                    }
                                }
                            }

No idea what length should be the Config struct.
The Guid which is read after could be plausible... dunno.
But the MaxSection fields are not.

This is the output.

ERROR 0 Length: 972
ERROR 0 Version: 11
ERROR 0 Type: 16
ERROR 0 State: 1
ERROR 0 MaxRawDataLength: 3372
ERROR 0 NumRecordsToPreallocate: 1
ERROR 0 MaxSectionsPerRecord: 3
ERROR 0 ErrorSourceId: 0
ERROR 0 PlatformErrorSourceId: 0
ERROR 0 Flags: 0
ERROR 0 Info Seek: 932
ERROR 0 Info Length: 932
ERROR 0 Info: 000000003C60C1835215A74887D114D9467D776550530000D80E000001000000100014B383B5FFFFF0180D7406F8FFFF10190D7406F8FFFF6037167006F8FFFF8D7C2157665EFB4480339B74CACEDF5B00000000000000000000000000000000640400000100000010F59FB083B5FFFF00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
ERROR 0 iPosition: 0
ERROR 0 iType: 0
ERROR 0 iEnabled: 0
ERROR 0 iSourceGuid: 3c60c183-5215-a748-87d1-14d9467d7765
ERROR 0 iLogTag: 21328
ERROR 0 iConfig: -2085415936
ERROR 0 iCreatorId: b5fffff0-180d-7406-f8ff-ff10190d7406
ERROR 0 iPartitionId: f8ffff60-3716-7006-f8ff-ff8d7c215766
ERROR 0 iMaxSectionDataLength: -2142962850
ERROR 0 iMaxSectionsPerRecord: -898327757
ERROR 0 iPacketStateBuffer: 206
ERROR 0 iOpenHandles: 23519


----------



## craxton

hazium233 said:


> Which motherboard is that?


B550 proArt









Amazon.com: ASUS ProArt B550-Creator AMD (Ryzen 5000/3000) ATX Content Creator Motherboard (Thunderbolt 4, Dual M.2, PCIe 4.0, Dual 2.5 Gb LAN, DisplayPort/HDMI, USB 3.2 Gen 2 Type-A and Type-C, and RGB headers) : Electronics


Buy ASUS ProArt B550-Creator AMD (Ryzen 5000/3000) ATX Content Creator Motherboard (Thunderbolt 4, Dual M.2, PCIe 4.0, Dual 2.5 Gb LAN, DisplayPort/HDMI, USB 3.2 Gen 2 Type-A and Type-C, and RGB headers): Motherboards - Amazon.com ✓ FREE DELIVERY possible on eligible purchases



www.amazon.com


----------



## hazium233

craxton said:


> B550 proArt


Ah, yeah I saw he was talking about it but I must have missed the WHEA free part.

As far as the motherboard topic goes, I noticed the local Micro Center is accumulating many open box AM4 motherboards these days. Part may be people reserving them to try and get GPU, but I wonder how much is just general AM4 shenanigans. 57 total right now. Here's some on the first page with multiples:

3x Crosshair Impact
4x B550 Aorus Master
5x X570 Aorus Pro
2x X570 Gaming Edge
2x B550 Gaming Carbon
3x B550-i Strix
5x X570 Aorus Elite
7x B550-F Strix Wifi
3x X570 TUF Wifi
3x B550 Tomahawk
2x X570 Elite
3x B550 Aorus Elite v2


----------



## craxton

hazium233 said:


> local Micro Center


please refrain from EVER mentioning micro center to me....as i dont have ANYWAY or am in noway near one at all
nearest ones like 5 hours from me so im a little *itch when it comes to actually buying something for what its supposed to be sold at

i myself have noticed that amazon hasnt had NEAR as many open box boards lately coming to sell...unless im just missing them?
the b550 proart veii mentioned has 0 ratings so i dont think the news is out...



hazium233 said:


> the WHEA free part


i believe its WHEA 18-19 free, one or the other, he stated its not had a single issue while the CPU 
he had in other boards were WHEA prone thus this board and realtek etc is the cause or one of the major issues.

the b550 board we both use (assuming u still use the gaming edge wifi) just released a bios update the other day
that i missed somehow? 
none the less, running my old stable config on it now, so far so good. still no CPU_VDDP option tho.... 
and still dont know what LCLK DPM bs is for but the config im running is working...


----------



## craxton

hazium233 said:


> 2x X570 Gaming Edge


NEVER EVER get this board unless its for a dual core 30 watt processor...VRM is TRASH can confirm as 
it was my daily, does run 4000mhz tho which is odd (2x8) but still 3600xt at PBO or static all core ran the VRM upto 70c 
with my case being a sebray adv with 9 120mm fans, and 4 of which are EK vardars, plus a 140mm out the back, with one of those 120mm 
directly at the VRMs it helped but still....wouldnt recommend this board to ANYONE unless it was 80$ or lower???




hazium233 said:


> 3x X570 TUF Wifi


i also stand firm against this particular board from asus as the ram compatibility is well....(for what the board is)
it should be way better, but way to many ive seen (ON OTHER FORUMS) state its hard to get anything working..

the b550 version different story...still unsure why Asus nor gigabyte neither one updates their QVL hardly at all after a few months upto a year of the board 
being out....


----------



## Takla

Other then primary timings, only trfc, trdwr & twrrd do anything for micron rev e. See my cheat sheet.


----------



## mongoled

Just thinking out load,

Regards to something RonLazer mentioned earlier about WHEA 19s.

There is a possibility that the WHEA 19s that are flagging "device driver issue" is because of a timing issue.

What do I mean, well, obviously there is some algorithm that the driver must feed into as to be able to work out if there is an error or not when running "computations".

Now if that algorithm is geared to a maximum FCLK of around 1900 mhz then the algorithm will be tuned to a certain "delay value" when cross referencing "computations" for possible errors. Of course there will be pre-defined values that if they fall out of the "delay range" will trigger the error checking algorithm to believe there is an issue.

When we push past 1900 mhz, this "delay range" will fall out of whats expected hence the strangeness in the 100s of WHEA 19s ID 0 Type 16s once you go a few mhz past a certain FCLK frequency.


----------



## TimeDrapery

Veii said:


> Spoiler
> 
> 
> 
> Overall , it's not finished
> I hope you understand the only reason i shared it is for ManniX and everyone else to learn
> But it's unstable as h*ck and causes random reboots ~ because transitions are not perfect yet. dLDO just gets confused and crashes. Spikes have a too big magnitude difference and the cpu crashes on lack of voltage
> With DF it functions, but that's completely messed up and broken, soo i can only recommend for everyone to keep it disabled for now


Sounds great! I'm gonna run it on all my most critical 24/7 systems 😂😂😂😂😂

No, I'm kidding, I understand and I'll be sure to try not to break more than I have to... Thanks again for sharing!


----------



## ManniX-ITA

mongoled said:


> There is a possibility that the WHEA 19s that are flagging "device driver issue" is because of a timing issue.


Yes, it's for sure a timing issue related to the IF speed otherwise it would happen as well at 1900 MHz and below 

What he said is all true and correct.
The source and effect of this timing issue is what is under debate.

Matisse had the same issue as Vermeer with IF above 1900 MHz but the effect, at least what I observed, was very much different.
When the WHEA 19 was starting to pop at a moderate rate, eg. usually running y-cruncher, the CPU would reset and reboot the system.
Performance degradation would be evident and it was easy to verify that the system stability was compromised.

Vermeer doesn't show this behavior.
When these errors are popping at an incredibly high rate the only performance degradation (with the right settings to have the IF stable) is due to the processing of the WHEA errors.
System stability is same as IF 1900 (actually for me better at 2000) and can be verified running all sort of stress testing.

This means there's no data corruption, it would end up to a crash at this rate, neither a data corruption which is recovered, at that rate would degrade the performances.

In my opinion and testing, these errors can be ignored and high IF can be used with the right settings to make it stable.
But it would be really helpful to identify the source and ideally a way to avoid them popping up.
Because for sure silencing the sources is possibly hide legitimate errors and thus hiding slight instabilities that could be fixed with a better tuning.


----------



## mongoled

Well thats a completed 4133/2067 TM5 with the new A9 BIOS,

now onto RealBench and finishing with several hours of Y-Cruncher full suite


----------



## craxton

Curious, in HWiNFO64 under the main startup settings, do you guys use 
AMD snapshot polling? or ? (after updating the bios i looked (forgot i set this) and
had a max of 1.2V while boosting to 4.85 and was like..............

then i turned off hardware polling and restarted and well back to hitting 1.4-5V depending on whats going on....


----------



## craxton

ManniX-ITA said:


> If you don't get hundreds and more per minute it'd be better to try to find better settings as the IF could be unstable


so your saying (me being near whea free) i should find a different IF freq????
bc im probably not being recorded???


----------



## ManniX-ITA

craxton said:


> so your saying (me being near whea free) i should find a different IF freq????
> bc im probably not being recorded???


Being near free usually means something needs tweaking
May be VDDG, VSOC, LLC, PWM...
To stabilize first thing I had to do was to find the right VDDG CCD&IOD and VSOC and SOC LLC


----------



## hazium233

craxton said:


> ...
> bios


I missed the 1.6 official too, but it may end up as just being relabeled 1.63 beta. I doubt anything new is unlocked, and who knows about WHEA.


mongoled said:


> When we push past 1900 mhz, this "delay range" will fall out of whats expected hence the strangeness in the 100s of WHEA 19s ID 0 Type 16s once you go a few mhz past a certain FCLK frequency.


This "Type 16" I assume is in the "ErrorType" field when you look at the details in Event Viewer?

I have had the below errors on 3866 and 3933 which are WHEA 19, ErrorSource 0, ErrorType 10, MemHierarchLvl 3. 280 in the 25c TM5 1usmus run last night. (I don't know if people prefer spoiler for image in post, but I will use them in case)



Spoiler















The "Raw Data" changes, but everything above is the same. This was the case at 1966 too.

Earlier I had just tried my loose timings that were tested 1 hr TM5 to try and look at ProcODT and CAD over 8 runs of AIDA for consistency, but only managed to get variation to 0.2ns. But I may need to look again at higher SOC.

I may just need more IOD, or at least better VDDG settings and haven't tested all the steps yet.

The LCLK master setting I have may not do anything for this, although it disables monitoring of some fields in hwinfo.

I haven't tried Global C-States, that will be next. Then more VRM settings.

I maybe incorrectly am running PBO-Disabled (so default power limits) maybe that is a mistake and I will check that too.

Settings I tested initially at 3866 were an 18-20/21-20-40-64 set at 1.4 that passed 1hr TM5. I figured if I was running 25c, I would test a CL 16 profile with "expected" RC and moderate subtimings also at 1.4. I used tRFC 576 with WR 24, RTP 12. This frequency seemed to want RDWR 10 at these voltages anyway.

Need to run Y-cruncher to look for outright fail.


AIDA on this CL 16 set is ~57.4 so far. When I was mentioning Rev E results before, it was because I wanted to compare results to double check my speeds, not so much for timing advice, but I don't mind advice or criticism. Sorting the fabric is my main goal for the next few days though, if possible.

If that fails, these dimms come out and the old Rev D goes in just for the hell of it.


----------



## mongoled

hazium233 said:


> This "Type 16" I assume is in the "ErrorType" field when you look at the details in Event Viewer?


Look at this post









WHEAService, WHEA errors suppressor - unleash Ryzen...


So...... From Manni-ITX excellent work I can diagnose the following from my CPU running at 4133/2067 On most boots I get the following Type: 3 Description: WheaErrSrcTypeNMI = 0x03, Non-Maskable Interrupt - 1 Warning Type: 0 Description: WheaErrSrcTypeMCE = 0x00, Machine Check Exception -...




www.overclock.net


----------



## RonLazer

ManniX-ITA said:


> Yes, it's for sure a timing issue related to the IF speed otherwise it would happen as well at 1900 MHz and below
> 
> What he said is all true and correct.
> The source and effect of this timing issue is what is under debate.
> 
> Matisse had the same issue as Vermeer with IF above 1900 MHz but the effect, at least what I observed, was very much different.
> When the WHEA 19 was starting to pop at a moderate rate, eg. usually running y-cruncher, the CPU would reset and reboot the system.
> Performance degradation would be evident and it was easy to verify that the system stability was compromised.
> 
> Vermeer doesn't show this behavior.
> When these errors are popping at an incredibly high rate the only performance degradation (with the right settings to have the IF stable) is due to the processing of the WHEA errors.
> System stability is same as IF 1900 (actually for me better at 2000) and can be verified running all sort of stress testing.
> 
> This means there's no data corruption, it would end up to a crash at this rate, neither a data corruption which is recovered, at that rate would degrade the performances.
> 
> In my opinion and testing, these errors can be ignored and high IF can be used with the right settings to make it stable.
> But it would be really helpful to identify the source and ideally a way to avoid them popping up.
> Because for sure silencing the sources is possibly hide legitimate errors and thus hiding slight instabilities that could be fixed with a better tuning.


Isn't this just due to CCD topology in the old CCD design? Inter-core communication had to cross the data-fabric and if any corruption happened as data moved between L3 domains there was no way to correct it, so the CPU would shut down to prevent any malfunction. I might be wrong but that was my understanding.


----------



## hazium233

mongoled said:


> Look at this post
> 
> 
> 
> 
> 
> 
> 
> 
> 
> WHEAService, WHEA errors suppressor - unleash Ryzen...
> 
> 
> So...... From Manni-ITX excellent work I can diagnose the following from my CPU running at 4133/2067 On most boots I get the following Type: 3 Description: WheaErrSrcTypeNMI = 0x03, Non-Maskable Interrupt - 1 Warning Type: 0 Description: WheaErrSrcTypeMCE = 0x00, Machine Check Exception -...
> 
> 
> 
> 
> www.overclock.net


Thanks I did see that. Maybe the question is better over there but I was missing where ErrorSource 0 = Type 16 even if in friendly view / XML view it says "ErrorType 10" came from. I didn't know if ManniX's logs showed something different, or if I am looking in the wrong place in Event Viewer. Or if I need to plug the XML into something else. I will read through again at lunch.


----------



## mongoled

Completed 2 hours Realbench, followed by 3 hours Y-Cruncher.

Time to test Doom Eternal


----------



## Dar|{cyde

@mongoled dang man, either those settings really help with the voltage, or your sticks are bloody magic. 1.48v is insane for that speed (does it overvolt like the Unify-x too? So its only 1.47v bios?) How did you tune in your RTTs/ProcODT/ClkDrv? I wish you were running DR so I could copy them, but everything is different when you're 4xSR vs 2xDR.

Funny thing is, I've been tuning 3933 at 50.4ns. So for pure latency, you had to go much farther in mhz to improve.


----------



## mongoled

Dar|{cyde said:


> @mongoled dang man, either those settings really help with the voltage, or your sticks are bloody magic. 1.48v is insane for that speed (does it overvolt like the Unify-x too? So its only 1.47v bios?) How did you tune in your RTTs/ProcODT/ClkDrv? I wish you were running DR so I could copy them, but everything is different when you're 4xSR vs 2xDR.
> 
> Funny thing is, I've been tuning 3933 at 50.4ns. So for pure latency, you had to go much farther in mhz to improve.


Three of the four modules are excellent and can handle 3800 mhz flat 14s no problem, one of the sticks requires tRCDRD to be @15.

With regards to the voltage, yeah, overvolts 0.02v, so I have set in BIOS 1.48v and HWInfo64 reports 1.5v.

As ive not really played with vDIMM while tweaking 4133mhz, they may go down on voltage still.

Re RTTs/ProcODT/ClkDrv, I used values that I had tuned when running 3800 mhz and just modified from there as per using less vDIMM and more vSOC, i.e. was using 1.53v for my 3800 mhz settins as I could reduce vDIMM it allowed me to reduce ClkDrvStr while I had to raise ProcODT due to higher vSOC.

You should be able to copy my settings, you may need to increase ClkDrvStr to 40 ohms, but all other values should work OK.

When I tweaked my 3800 mhz settings, latency was around 51.3 to 51.6, I could never get to sub 51 reliably.

I shall have to retest the settings in my sig as this new BIOS I am using may bring that latency down while at 3800 mhz


----------



## ManniX-ITA

RonLazer said:


> Isn't this just due to CCD topology in the old CCD design? Inter-core communication had to cross the data-fabric and if any corruption happened as data moved between L3 domains there was no way to correct it, so the CPU would shut down to prevent any malfunction. I might be wrong but that was my understanding.


Yes you are right, the CCXs in the same die would talk via the IF.
But my 5950x is a dual CCD so inter-core communication would still pass over the IF between them in my understanding.
So I was expecting a similar degradation behavior at least in all-core tests and visible in Sandra Multi-Core test.


----------



## MattKelly

So is the ASRock B550 Phantom ITX considered the best ITX board in terms of pushing FCLK the farthest? Are there any other ITX boards (X570 or B550) worth considering, as far as WHEAs & FCLK are concerned?


----------



## jomama22

ManniX-ITA said:


> Yes you are right, the CCXs in the same die would talk via the IF.
> But my 5950x is a dual CCD so inter-core communication would still pass over the IF between them in my understanding.
> So I was expecting a similar degradation behavior at least in all-core tests and visible in Sandra Multi-Core test.


Cores to core only use the IF when it's inter module, i.e. 0-7 to 8-15 and vise versa. Anything on the same ccd just goes through the l3 of that ccd.

You can see this latency penalty difference in Sandra.


----------



## Dar|{cyde

mongoled said:


> Three of the four modules are excellent and can handle 3800 mhz flat 14s no problem, one of the sticks requires tRCDRD to be @15.
> 
> With regards to the voltage, yeah, overvolts 0.02v, so I have set in BIOS 1.48v and HWInfo64 reports 1.5v.
> 
> As ive not really played with vDIMM while tweaking 4133mhz, they may go down on voltage still.
> 
> Re RTTs/ProcODT/ClkDrv, I used values that I had tuned when running 3800 mhz and just modified from there as per using less vDIMM and more vSOC, i.e. was using 1.53v for my 3800 mhz settins as I could reduce vDIMM it allowed me to reduce ClkDrvStr while I had to raise ProcODT due to higher vSOC.
> 
> You should be able to copy my settings, you may need to increase ClkDrvStr to 40 ohms, but all other values should work OK.
> 
> When I tweaked my 3800 mhz settings, latency was around 51.3 to 51.6, I could never get to sub 51 reliably.
> 
> I shall have to retest the settings in my sig as this new BIOS I am using may bring that latency down while at 3800 mhz


Not really related to the mem timings, but what tricks are you using for your CPU OC? I've never seen my EDC spike up to 132 like that. Best I've ever done is 122A with unstable CO settings. Are you using telemetry offset? I can work out the PPT/TDC/EDC from the screenshot.


----------



## PJVol

Dar|{cyde said:


> EDC spike up to 132


TDC 87 amps 
Now I see why mine was throttling so hard in similar config...


----------



## craxton

ManniX-ITA said:


> To stabilize first thing I had to do was to find the right VDDG CCD&IOD and VSOC and SOC LLC


yep, finally found the right voltages for my timings/cpu i do believe, no crashes in y-cruncher
prime, or OCCT and (with the new bios) TM5 ran just fine like it did on the bios i was running for my board.









above is what i have now vs what i did have which near dropped .5xx soc, from 1070 iod to 1000
and ccd one step (unsure what MSI stepping is but just used minus for it) 

havent had a crash any this week, did limit to 70ppt while running prime and ycruncher otherwise the 
240mm ek d-rgb cant keep up even while the house is 70f throughout.



ManniX-ITA said:


> Being near free usually means something needs tweaking


by near free i mean (this week ive been free, and have only had 4 WHEA 18 events 
throughout my history with this board while stabilizing curve settings with voltage offset.


----------



## craxton

hazium233 said:


> I missed the 1.6 official too, but it may end up as just being relabeled 1.63 beta. I doubt anything new is unlocked, and who knows about WHEA.
> 
> This "Type 16" I assume is in the "ErrorType" field when you look at the details in Event Viewer?
> 
> I have had the below errors on 3866 and 3933 which are WHEA 19, ErrorSource 0, ErrorType 10, MemHierarchLvl 3. 280 in the 25c TM5 1usmus run last night. (I don't know if people prefer spoiler for image in post, but I will use them in case)
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2512137
> 
> 
> 
> 
> The "Raw Data" changes, but everything above is the same. This was the case at 1966 too.
> 
> Earlier I had just tried my loose timings that were tested 1 hr TM5 to try and look at ProcODT and CAD over 8 runs of AIDA for consistency, but only managed to get variation to 0.2ns. But I may need to look again at higher SOC.
> 
> I may just need more IOD, or at least better VDDG settings and haven't tested all the steps yet.
> 
> The LCLK master setting I have may not do anything for this, although it disables monitoring of some fields in hwinfo.
> 
> I haven't tried Global C-States, that will be next. Then more VRM settings.
> 
> I maybe incorrectly am running PBO-Disabled (so default power limits) maybe that is a mistake and I will check that too.
> 
> Settings I tested initially at 3866 were an 18-20/21-20-40-64 set at 1.4 that passed 1hr TM5. I figured if I was running 25c, I would test a CL 16 profile with "expected" RC and moderate subtimings also at 1.4. I used tRFC 576 with WR 24, RTP 12. This frequency seemed to want RDWR 10 at these voltages anyway.
> 
> Need to run Y-cruncher to look for outright fail.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2512138
> 
> 
> 
> 
> AIDA on this CL 16 set is ~57.4 so far. When I was mentioning Rev E results before, it was because I wanted to compare results to double check my speeds, not so much for timing advice, but I don't mind advice or criticism. Sorting the fabric is my main goal for the next few days though, if possible.
> 
> If that fails, these dimms come out and the old Rev D goes in just for the hell of it.


your running the EXACT board that i am, yet i do NOT see anything about CPU bus/interconnect errors in HWiNFO64...
did you manually add this somehow??????


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> your running the EXACT board that i am, yet i do NOT see anything about CPU bus/interconnect errors in HWiNFO64...
> did you manually add this somehow??????


On my system this line item hides out at the very bottom...


----------



## mongoled

Dar|{cyde said:


> Not really related to the mem timings, but what tricks are you using for your CPU OC? I've never seen my EDC spike up to 132 like that. Best I've ever done is 122A with unstable CO settings. Are you using telemetry offset? I can work out the PPT/TDC/EDC from the screenshot.


PPT/TDC/EDC is set at 142/95/500
CPU LLC @3
CPU SoC LLC @2
Scaler: X4

No telemetry offset


----------



## mongoled

PJVol said:


> TDC 87 amps
> Now I see why mine was throttling so hard in similar config...


How much do you see?


----------



## craxton

TimeDrapery said:


> On my system this line item hides out at the very bottom...


its not on my version of HWiNFO,

what all settings do you guys have ticked????

besides run at startup, hide name and welcome screen/start minimized....


----------



## Dar|{cyde

craxton said:


> its not on my version of HWiNFO,
> 
> what all settings do you guys have ticked????
> 
> besides run at startup, hide name and welcome screen/start minimized....


It appears dynamically when you throw a WHEA. You have to throw an error first. I set an Alert on mine, so now its there permanently.


----------



## TimeDrapery

mongoled said:


> Spoiler
> 
> 
> 
> How much do you see?


@mongoled 

If it's the system in his sig he's referring to then I imagine he saw at least 60A TDC considering the throttling he's describing

I see your EDC limit is lifted _way_ up above the AMD limits for PPT and TDC, why did you elect to go this route rather than lifting PPT on its own or alongside TDC? What behavior(s) did you see during testing that prompted you to go this route?

@PJVol 

What limits are you setting during testing of this sort? What differences have you seen in throttling behavior with regards to which PBO limit gets maxed? For example, you see higher voltages when it throttles due to TDC limit being reached...? Or do you see higher voltages when it's the EDC limit that's reached?


----------



## TimeDrapery

craxton said:


> Spoiler
> 
> 
> 
> its not on my version of HWiNFO,
> 
> what all settings do you guys have ticked????
> 
> besides run at startup, hide name and welcome screen/start minimized....


@craxton 

Ah, good question! I'll check for ya next time I'm home this evening



Dar|{cyde said:


> Spoiler
> 
> 
> 
> It appears dynamically when you throw a WHEA. You have to throw an error first. I set an Alert on mine, so now its there permanently.


@Dar|{cyde 

No ****? I didn't know it did that! Thanks for sharing!


----------



## goondam

craxton said:


> B550 proArt
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Amazon.com: ASUS ProArt B550-Creator AMD (Ryzen 5000/3000) ATX Content Creator Motherboard (Thunderbolt 4, Dual M.2, PCIe 4.0, Dual 2.5 Gb LAN, DisplayPort/HDMI, USB 3.2 Gen 2 Type-A and Type-C, and RGB headers) : Electronics
> 
> 
> Buy ASUS ProArt B550-Creator AMD (Ryzen 5000/3000) ATX Content Creator Motherboard (Thunderbolt 4, Dual M.2, PCIe 4.0, Dual 2.5 Gb LAN, DisplayPort/HDMI, USB 3.2 Gen 2 Type-A and Type-C, and RGB headers): Motherboards - Amazon.com ✓ FREE DELIVERY possible on eligible purchases
> 
> 
> 
> www.amazon.com


careful i have 5950x and i recently upgraded to b550 pro art.
i have a very rare but super annoying issue, not sure if its whea error related 

issue is this sometimes during login or when opening a app/program windows will freeze, both cpu/disk go to 100% usage. pc will then restart after couple minutes as the cpu reaches max temp. this didn't happen on the old board(x470 ch7). happened on both old windows installation(previous mobo) and a new fresh clean install of windows


----------



## PJVol

mongoled said:


> How much do you see?


Depends on the load type (sse, avx, etc)
The highest TDC and PPT was in OCCT small/extreme/steady - 65A (EDC 105A, PPT107W)
The highest EDC in CB23 - 113A (TDC 56A, PPT 97W) , AIDA stress test - 116A (TDC 49A, PPT 93W)

PS: I seem to miss y-cruncher window on your screens. Is it what stress CPU the most? Heard of some extraordinary load it put onto cpu...



TimeDrapery said:


> What limits are you setting during testing of this sort? What differences have you seen in throttling behavior with regards to which PBO limit gets maxed? For example, you see higher voltages when it throttles due to TDC limit being reached...? Or do you see higher voltages when it's the EDC limit that's reached?


Not to mess with answers, I hope you won't mind to look at screens below, that's all there. But to put it simple, I didn't see any of those limits ever reached.

PS: added PBO limits info


----------



## craxton

Dar|{cyde said:


> It appears dynamically when you throw a WHEA.


well i suppose 18 isnt good enough then....lol

or 20 for that matter?



Dar|{cyde said:


> You have to throw an error first. I set an Alert on mine, so now its there permanently.


as mentioned only ID 18 and ID 20 have ever been shown on my board/with this cpu (3600xt however different story)
log was full on my old back ups....



goondam said:


> i have a very rare but super annoying issue, not sure if its whea error related


hmmmmmmm i had this issue, reinstalling windows, and all sorts of other things DID NOTHING...
(do you have some sort of USB dongle for an NVME drive hooked up?)

also, try to restart WMI (windows management instrument)
itll state its going to restart IP helper but click yes, for quite sometime i had 100% cpu usage in task man
and nothing shown in process explorer however rarely did the cpu actually hit anything above normal temps between 30c-46c
i still suggest trying WMI restart, (you could if you have one) remove ALL DRIVES (MAIN MOSTLY) and reinstall windows 
as i did, which solved my issue. (installing MSI dragon center however did for some reason cause this problem to reappear.
but its stopped? unsure how..

@TimeDrapery 

thanks, would like to know if what i have ticked is correct or not...
ticking the option for "snapshot polling" and giving a reboot, shows near 1.2 volts on the cpu while boosting to 4.8x
which i thought HELL YES this new bios is the SHIIIIII but after remembering i ticked this yesterday sometime i turned it back off
then restarted the pc again to find its mostly just idle voltage or something like that.....
i suppose under 1.48V is good enough with -26CO with +6xmv (msi stepping) cant set manual range only + or - 
which gives its own numbers.


----------



## hazium233

craxton said:


> your running the EXACT board that i am, yet i do NOT see anything about CPU bus/interconnect errors in HWiNFO64...
> did you manually add this somehow??????


Well, we were on different bios at some point, I had only used 1.63 beta for testing (and am still on that), you had 1.61 IIRC.

I can boot at least 4000 / 2000 synchronous, but so far at 1933 and 1966 FCLK, I get the WHEA 19 - ErrorSource 0 logged. I didn't do anything special to enable logging, it is 20H2 Windows 10 Pro, the hwinfo version is 7.04-4480.

I asked about Message Signal Interrupt above, but otherwise I was running whatever Realtek Lan driver Windows automatically installed (but some FCLK tests I had lan disabled). Nvidia 457.51 installed for Strix 2060, set to MSI mode via tweak.

Are you now on 1.6 final bios? If I make no progress with settings tonight or tomorrow I may try a flash to a different version. But I may just have a potato 5600X, or am incompetent with settings.


----------



## craxton

the bios i was on, i believe (was a beta) which is why its no longer posted via support page.
the bios im running now is the same SMU your running, but is 1.60 (latest via support page)

-22 CO with AMD voltage setting inside the bios, (used it before per core)
but this time around, prime NO CRASH with it, Y-cruncher NO CRASH WITH IT,
OCCT same no crash....

allowing well attaching ryzen master shots of PPT etc per profile, (gaming is what i actually use to keep from going above 65c
while allowing boost to happen...(if any lower it doesnt?)

this area is one thing i dont know much on no matter what i read, i dont allow my chip hardly ever to hit 80c
if it does i lower ppt REAL QUICK....anyhow

(PJvol just a moment ago shared what hes using Via HWiNFO 
i mostly copied his per what app im using to stress, although he showed nothing about prime, and y-cruncher,
i still set under 90ppt as its easier to manage temps using a limit on ppt rather EDC and TDC

gaming profile tho is possibly limiting the cpu more than it should but still boosts in games, 
doesnt hinder performance AT ALL and keeps temps in check (to my liking)


----------



## craxton

hazium233 said:


> 20H2 Windows 10 Pro


ive got home edition, to which im thinking of updating as i have a new update as of today 









i dont have any windows HELLO bs, no cams, no external harddrives,
(did buy a NVME enclosure tho which hopefully works as the SSK one i have doesnt/does
just not at its rated speed, only 48mbs (NVME drive will do 350mbs easy (cheap hp laptop exchange out nvme dunno name etc)
just know 120gb is to much to throw away when i can use it somewhere lol

i have allowed windows to install most drivers, but after setup (the new setup via windows install this time)
i used dragon center to install drivers etc. which gave no issues this time around...i do NOT like the new 
app theyre working with now....U.I is hard to nav for someone already used to something else...



hazium233 said:


> Message Signal Interrupt


im unsure if i stated, but i still have no idea what that means lol....
i could look it up, but id say its specific to per device??? (i think i did look it up)
i do not have this turned on unless windows did it by default ?

i tried 1.63 (the version that was right before this release now) 
and never could get my stable config to work more than one time...
it may have been where i turned off LCLK or whatever it is inside amd overclocking section, 
as this new bios with this feature turned off i get reboots upon windows PIN sign in...

(do you use TPM and secure boot)? 

all my bios settings are default except overclocking ram and PBO/CO settings, (i did turn off LN2 stuff and spread spectrum)
but other than that just TPM and secure boot have been enabled. no legacy mode or any other settings are on.

you can try my 4000mhz settings (if 4x8 is your set now?) 

2 sticks are better binned 3800c14 FLAT while the other two 3800c15
(not on 3800mhz just stating what i did to figure out which were better, using good/bad good/bad on dimm slots


----------



## hazium233

craxton said:


> the bios i was on, i believe (was a beta) which is why its no longer posted via support page.
> the bios im running now is the same SMU your running, but is 1.60 (latest via support page)


Right, I thought you were on 1.61 beta, I was using 1.63 beta. If you aren't getting the same WHEA then it could just be good luck for you and bad luck for me. I can try flashing official 1.6 at some, probably would be tomorrow. I need to see if ****load more CCD, or maybe more IOD does anything.



> -22 CO with AMD voltage setting inside the bios, (used it before per core)
> but this time around, prime NO CRASH with it, Y-cruncher NO CRASH WITH IT,
> OCCT same no crash....


I am not even using PBO, which at one point I wondered if the default power limits or some shenanigans from that could be related. I originally thought get ram / fabric stable then work on CO. Also I have been logging some benchmarks because I also wanted to look at ram scaling for my system and I though I would keep default limiters for this to make it more pure. This is probably pointless, but I wanted to do it.



> this area is one thing i dont know much on no matter what i read, i dont allow my chip hardly ever to hit 80c
> if it does i lower ppt REAL QUICK....anyhow


I have D15S, and I can't quite recall what the highest temp (CCD1 Tdie) I have seen has been, but really hasn't been that high.

I'm using a Meshify C with 2x140+1x120 up front. Strix 2060 nearly divides the main area in half though as an upper and lower airflow zone. 840 Evo and 850 Evo on back of mobo tray, 500 and 2TB HDD in basement. 1TB Hynix P31 NVME in top slot. Bitfenix Formula Gold 550W PSU.


----------



## hazium233

craxton said:


> i have allowed windows to install most drivers, but after setup (the new setup via windows install this time)
> i used dragon center to install drivers etc. which gave no issues this time around...i do NOT like the new
> app theyre working with now....U.I is hard to nav for someone already used to something else...


I usually don't let Windows manage drivers if I can help it, but I was lazy with the Realtek lan because I haven't used it. But I did install the latest finally that is posted on on the B550 support page.



> im unsure if i stated, but i still have no idea what that means lol....
> i could look it up, but id say its specific to per device??? (i think i did look it up)
> i do not have this turned on unless windows did it by default ?


It is a method for how the PCIe device communicated, if you didn't manually tweak it then nvidia uses the old method as default on Windows (line based interrupts). Similarly, Reaktek Audio defaulted to old method, but I also changed it.

Message Signaled Interrupts



> LCLK or whatever it is inside amd overclocking section,
> as this new bios with this feature turned off i get reboots upon windows PIN sign in...


Yeah the LCLK I think had to go in System tab then AMD CBS then the LCLK state. With it disabled, ZenTimings can't read the power table, and I can't read some things in hwinfo. But rate of WHEA 19 didn't seem to change so far with it disabled or enabled.



> (do you use TPM and secure boot)?


No, definitely not secure boot. TPM I don't think so either.



> you can try my 4000mhz settings (if 4x8 is your set now?)
> 
> 2 sticks are better binned 3800c14 FLAT while the other two 3800c15
> (not on 3800mhz just stating what i did to figure out which were better, using good/bad good/bad on dimm slots


I still have the dual rank Micron E in right now. Really there isn't much to do with it if I can't get FCLK > 3800 stable. I might see what my 2666 Rev D sticks will do for fun, then go B-die. In between verify some 3600 bin Rev E I won on ebay works after it arrives.


----------



## munternet

Just purchased a Crosshair VIII Hero and a 5950x and put in some Gskill 3600c16 2x16GB and a 3080 Tuf OC and a 1TB 980 Pro
I am a fish out of water with AMD but I'm keen to give it a decent go to compare to the Intel system in my sig
Already I can see about 20 extra frames in BFV and I plan to stretch it out more with some help from you guys 
Currently I have a fast and dirty 4.65GHz 1.4v all core with 3600-16-16-16-36 1T on the ram
I have a custom loop with a thicker radiator and EK Monarch plates for the ram on the way from Amazon
I have a bunch of questions but I need to get the hardware finalized first since the ram is already tapping 55°c after long gaming sessions


----------



## mongoled

TimeDrapery said:


> I see your EDC limit is lifted _way_ up above the AMD limits for PPT and TDC, why did you elect to go this route rather than lifting PPT on its own or alongside TDC? What behavior(s) did you see during testing that prompted you to go this route?


Well I aim for "simple" things first then if that doesnt work I move to more exotic methods



Basically I simply decided to use AMD recommended values for the 105W TDP processors, which is PPT/TDC/EDC, 142/95/140

As we saw in earlier BIOSs, there was an issue with peeps comparative AIDA64 L3 cache throughputs and it was discovered that EDC was the "cause", so thats the only thing I changed, to use a over aggressive EDC settings to "fix" that issue.

Understandably in newer BIOSs using the default EDC results in higher throughput than previous BIOS, but not to the levels of when using a high EDC.

Using a high EDC seems to have the added effect of "opening" PPT and TDC.

I have not tested other PBO values as I didnt see the need, if something was amiss, or some performance was left on the table I could re-evaluate this.



PJVol said:


> PS: I seem to miss y-cruncher window on your screens. Is it what stress CPU the most? Heard of some extraordinary load it put onto cpu...


This post









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Which motherboard is that? B550 proArt https://www.amazon.com/ASUS-B550-Creator-Motherboard-Thunderbolt-DisplayPort/dp/B08ZS73B4Y/ref=sr_1_1?dchild=1&keywords=b550+proart&qid=1621972735&sr=8-1




www.overclock.net





On the left side screen, Y-Cruncher ...



No issues when I gamed for about an hour.

Only issue I seem to be having is mouse getting stuck for a microsecond, no sound anomolies in the sense that audio clarity is not distorted. The mouse getting stuck only happened on previous BIOS when stress testing, it happens on new BIOS while not stress testing, but it does not happen often.

Its like an interrupt takes place that halts the OS for that microsecond, as if audio is playing it will also stop for that microsecond ...

** EDIT **
Interrupts may have to do with not fully stable CO settings, just had a WHEA 18 crash, just tweaked that core a little and so far no sticking mouse ...


----------



## mongoled

hazium233 said:


> Thanks I did see that. Maybe the question is better over there but I was missing where ErrorSource 0 = Type 16 even if in friendly view / XML view it says "ErrorType 10" came from. I didn't know if ManniX's logs showed something different, or if I am looking in the wrong place in Event Viewer. Or if I need to plug the XML into something else. I will read through again at lunch.


Here you go,

this is what happens on my system on boot when using 4133/2067.

101 WHEA 19s

First one









Then the other 100


----------



## ManniX-ITA

mongoled said:


> First one


Same for me, first one from ErrorSource 3, it's usually the NMI source with MciStat 0xd02000000002080b.
Sometimes the first doesn't come up.
The others they always have MciStat at 0x982000000002080b and coming from ErrorSource 0 which is the DeviceDriver.
Have seen around other people posting and is always the same.

If you get anything else than this there's something wrong to take care for sure.


----------



## Asutz

Can somebody pls explain how soc/vddp/vddg distorts sound?

changed all of them so often and never got rid of sound pops 100%, no issues if a video is running or music unless pressing stop button or something then it sounds like the click of the mousebutton inside the headphone.
there are posts inside the forum and they are from year 2013 or older and did not found a solution. is it just bad hardware or a combination of both ? is it emi ? bad electricity ? or whats more important.how to fix this, driving me nuts. do those usb fixes in the newest ages help a bit maybe?!

used the jack in back = soundpops here and there
spdif to my amp, was better but also not clean, now usb dac and headphone.
was sitting on a friends pc long time ago, stock amd system and checked the headphone.soundpops.

next problem is it can happen on intel systems aswell.
back in the days on my older systems always installed windows without acpi looks like its not possible anymore and if i remember correctly it was much better overall.thanks in advance


----------



## ManniX-ITA

Asutz said:


> Can somebody pls explain how soc/vddp/vddg distorts sound?


In general a bit more VSOC and IOD will fix it.
But there are so many causes that can corrupt audio, eg EMI, drivers, whatever... that it doesn't always work.
Post a ZenTimings screenshot.


----------



## mongoled

ManniX-ITA said:


> Same for me, first one from ErrorSource 3, it's usually the NMI source with MciStat 0xd02000000002080b.
> Sometimes the first doesn't come up.
> The others they always have MciStat at 0x982000000002080b and coming from ErrorSource 0 which is the DeviceDriver.
> Have seen around other people posting and is always the same.
> 
> If you get anything else than this there's something wrong to take care for sure.


Same here, though its a rarity not to have first WHEA indicator.

Just had another crash

🤣🤣

All CO related, fully stable when stress tested, now I am checking out regular light PC usage and getting the hangs.

Funny thing is its looking like I am going to have the exact same CO settings that I was using with 1.1.9.0 and 1.1.9.0 was using 350 mhz boost overdrive, while its 200 mhz on 1.2.0.2 ...


----------



## ManniX-ITA

use CoreCycler:









GitHub - sp00n/corecycler: Stability test script for PBO & Curve Optimizer stability testing on AMD Ryzen processors


Stability test script for PBO & Curve Optimizer stability testing on AMD Ryzen processors - GitHub - sp00n/corecycler: Stability test script for PBO & Curve Optimizer stability testing on A...




github.com





But I get random results with Prime95, I would switch to y-cruncher to test
You can do so by editing the config.ini


----------



## mongoled

ManniX-ITA said:


> use CoreCycler:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - sp00n/corecycler: Stability test script for PBO & Curve Optimizer stability testing on AMD Ryzen processors
> 
> 
> Stability test script for PBO & Curve Optimizer stability testing on AMD Ryzen processors - GitHub - sp00n/corecycler: Stability test script for PBO & Curve Optimizer stability testing on A...
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> But I get random results with Prime95, I would switch to y-cruncher to test
> You can do so by editing the config.ini


Will try thanks, didnt see any issues while using both corecycler and core_jumping, but maybe I wasnt looking at the right thing, both passed each time I used them


----------



## Asutz

here it is.
having issues with sound since the beginning with 2700x and now 5600x, cant remember old r3 1200 was ok i think.
boards b450 pro carbon and now ch7.

vsoc ive tried range 1.05 - 1.1 and auto settings, auto over 1.1v
cldo vddp tried ~855 - 950 and auto.
Auto overall is too high, also sound pops.

my ch7 is weird, no option to disable synchronous vddg iod / cdd voltages even if i set them both with the 50mv difference.bios 4301.


----------



## mongoled

Asutz said:


> here it is.
> having issues with sound since the beginning with 2700x and now 5600x, cant remember old r3 1200 was ok i think.
> boards b450 pro carbon and now ch7.
> 
> vsoc ive tried range 1.05 - 1.1 and auto settings, auto over 1.1v
> cldo vddp tried ~855 - 950 and auto.
> Auto overall is too high, also sound pops.
> 
> my ch7 is weird, no option to disable synchronous vddg iod / cdd voltages even if i set them both with the 50mv difference.bios 4301.
> 
> View attachment 2512240


Set
vDDP @ 0.880v
vDDG IOD @ 1.040v
vDDG CCD @ 1.000v

Report back



Ahhh, just saw you cant set asynchronous

Its important that CCD to IOD has a 0.04v difference


----------



## ManniX-ITA

mongoled said:


> Set
> vDDP @ 0.880v
> vDDG IOD @ 1.040v
> vDDG CCD @ 1.000v


I would not venture below 900mV VDDP yet.
Maybe in a second step.
It can cause instabilities.
Important to set VSOC at 1.1V.
If you still get issues, raise VSOC again to 1.15V.
You should really not need more to fix audio issues, otherwise is something else.


----------



## mongoled

ManniX-ITA said:


> I would not venture below 900mV VDDP yet.
> Maybe in a second step.
> It can cause instabilities.
> Important to set VSOC at 1.1V.
> If you still get issues, raise VSOC again to 1.15V.
> You should really not need more to fix audio issues, otherwise is something else.


Hes only @ 3600/1800

Never ran those settings myself personally, as things seem to scale with frequency I suggested those values as per my experience with 3800/1900


----------



## Asutz

vddg iod 1.040 and 1000 ccd is what i'v set in the bios and zen timer messuring both @0.99xxx like in the pic
maybe another flash and clear cmos would help but its stable except the issues with sound.

same odyssey like 2700x in the past, vsoc never rly helped,latency is fine too, 
energy saving, most or nearly everything is off.

what happed if i deactivate acpi in device manager? can windows boot without?
dont wanna risk too much and not rly like to restore os after that.


----------



## ManniX-ITA

mongoled said:


> Hes only @ 3600/1800
> 
> Never ran those settings myself personally, as things seem to scale with frequency I suggested those values as per my experience with 3800/1900


I had mixed results with 880mV, just better to stick to 900mV if you are looking for stability.
Yes he's only IF 1800 and with sound cracking is already quite weird as a start...

If you input something in BIOS and it's not set there's something wrong with it.
It's a X470 so ASUS probably messed up something adding support for the 3000s.
I'd try a different release till you get the voltages properly set.

Not sure what happens if you deactivate ACPI, I don't think it's a good idea 
You can still create a restore point and try to fix if it's not booting.
But you should not have this issue, ACPI or not.


----------



## Asutz

hm ok, will think about switching the board for the 3rd time if the next bios updates wont help. what is good ? no more asus, gigabyte. faulty bios at the beginning, more whea issues than on other brands.
msi is quick with updates at least on b550 and some newer ones. asrock, i dont know, had a z77pro long ago, was a solid pick but aslong amd's agesas suck, not sure if they are error free manufacturers cant do much in the end.


----------



## ManniX-ITA

I wouldn't know, no one is good in my opinion.
Gigabyte is doing much better lately with BIOS releases.
And the AORUS line has usually all settings exposed without an XOC specific release.
But the limits are normal.

MSI has XOC bios for some boards but they don't release it, which is a shame.
Not everything is exposed and lots of bugs which doesn't get fixed.

ASUS has its own problems but there are XOC bios regularly updated and available on HWBot.
Plus they have Safe boot and Retry buttons which are very helpful.

If I would pick another board after the Unify-X, I'll try the Dark Hero.
Price is high but not like before.


----------



## jomama22

So I will post more once I get my 4000fclk stable, but last week I did a full windows install with the Dark Hero after reflashing bios 3003 (I always do this just for my own weirdness). I Left everything on default except fully disabling Bluetooth, wifi, realtek lan, audio output (I use a sound card) and the asmedia 3.1 ports controller (affects the 4 blue usb's on the rear I/o). Did this all within the fresh bios before installing windows. Basically disabled everything I was given the option too as far as controllers go.

Since then I have received 0 whea 19s in event viewer when using fclk 2000. When looking at kernel-whea dir in event viewer, error sources are 5. In the error report there, I only see ID 20 which is directly affected by the soc/iod voltage I use (have so far been able to reduce it to just a few or none, depending on what tests/bench)

See performance gains and such in every bench I've tried this far.

I (believe) I had done this installation before with the exception of disabling the asmedia USB 3.0 controller (as1825 I think it is?) and still received whea 19s at anything over 1900.

Just food for thought. If there is somewhere someone would like me to look, just lmk and I can provide some pics or somthing.


----------



## ManniX-ITA

jomama22 said:


> Just food for thought. If there is somewhere someone would like me to look, just lmk and I can provide some pics or somthing.


Thanks, very good description 

You did the install and left everything disabled or later you re-enabled all/some of the devices?


----------



## jomama22

ManniX-ITA said:


> Thanks, very good description
> 
> You did the install and left everything disabled or later you re-enabled all/some of the devices?


Left everything disabled as I genuinely don't have a need for any of it lol. Didn't install any drivers manually, just let MS do its thing.

Nothing I disabled shows in device manager so windows cant see them either.


----------



## ManniX-ITA

jomama22 said:


> Left everything disabled as I genuinely don't have a need for any of it lol. Didn't install any drivers manually, just let MS do its thing.


So if my understanding is correct, previously you had the high flow of WHEA 19 running at 2000, right?

Would be nice if you could check how many error sources are initialized at boot.



Spoiler: WHEA Sources















I know it's a lot to ask...
But it could be great if you could check what happens re-enabling one by one the devices, if the error sources are 5.
You could save a restore point or make a backup to revert to a clean state.
It's annoying so if you don't have time no problem.


----------



## jomama22

ManniX-ITA said:


> So if my understanding is correct, previously you had the high flow of WHEA 19 running at 2000, right?
> 
> Would be nice if you could check how many error sources are initialized at boot.
> 
> 
> 
> Spoiler: WHEA Sources
> 
> 
> 
> 
> View attachment 2512250
> 
> 
> 
> 
> I know it's a lot to ask...
> But it could be great if you could check what happens re-enabling one by one the devices, if the error sources are 5.
> You could save a restore point or make a backup to revert to a clean state.
> It's annoying so if you don't have time no problem.


Yeah, error sources are 5 as I said previously. I unfortunately did not see what they were prior to reinstall.

Personally, don't reallllly want to go re-enabling stuff for fear of just getting lucky lmao. I'll consider it once I get this 4000 setup stable and such.

What I can do is just create a new windows install on a separate ssd I have and see what happens. Will be a bit before I can do that, just busy this week.

At the very least I would kinda guess it' may be related to that asmedia USB controller that goes through the chipset.

I have my soundcard, an nvme, a SSD and HDD all connected through the chipset as well just for info.

















Edit: yeah, had whea 19s at anything above 1900 prior.


----------



## ManniX-ITA

jomama22 said:


> Yeah, error sources are 5 as I said previously. I unfortunately did not see what they were prior to reinstall.


Sorry, I missed it 



jomama22 said:


> What I can do is just create a new windows install on a separate ssd I have and see what happens. Will be a bit before I can do that, just busy this week.


Would be nice, no problem.
We have plenty of time...

I'll try this route too, will make a fresh Win2Go install with everything disabled.
But could be also this new BIOS has some magic sprinkle inside...


----------



## jomama22

ManniX-ITA said:


> Sorry, I missed it
> 
> 
> 
> Would be nice, no problem.
> We have plenty of time...
> 
> I'll try this route too, will make a fresh Win2Go install with everything disabled.
> But could be also this new BIOS has some magic sprinkle inside...


The bios I'm using is 3003, so way back in early December. Agesa 1.1.8.0/smu 56.37.


----------



## ManniX-ITA

jomama22 said:


> The bios I'm using is 3003, so way back in early December. Agesa 1.1.8.0/smu 56.37.


Pretty old stuff... not sure about the SMU but I think I've tested 1.1.8.0 for both the Aorus Master and the Unify-X and they were dropping the same massive WHEA 19.


----------



## jomama22

ManniX-ITA said:


> Pretty old stuff... not sure about the SMU but I think I've tested 1.1.8.0 for both the Aorus Master and the Unify-X and they were dropping the same massive WHEA 19.


Yeah, this version is actually much worse then the newer ones interms of whea. Had tested 1.2.0.0 before and was able to knock down the whea's quite a bit, though still there. With this version, no matter the soc/vddg changes you make it makes no difference. Why I'm pretty happy to just have them not here lmao.


----------



## hazium233

mongoled said:


> Here you go,
> this is what happens on my system on boot when using 4133/2067.
> 101 WHEA 19s ...
> Then the other 100..





ManniX-ITA said:


> Same for me, first one from ErrorSource 3, it's usually the NMI source with MciStat 0xd02000000002080b.
> Sometimes the first doesn't come up.
> The others they always have MciStat at 0x982000000002080b and coming from ErrorSource 0 which is the DeviceDriver.
> Have seen around other people posting and is always the same.
> 
> If you get anything else than this there's something wrong to take care for sure.


Thanks to both.

The ErrorSource 3 with MCIStat 0xd02000000002080b I did see at 2000.










But not at 1933 or 1966 so far. At 2000 I had many of the ErrorSource 0 that could increment +100 at a time in hwinfo64, but they seem to come in slower at 1933 or 1966.

ErrorSource 0 with MciStat 0x982000000002080b










I think the motherboard is using ~1.84 PLL by default, but labeled as VTT in hwinfo for some reason.

I still need to do more work to see if I can maybe get rid of them at 1933.

Windows > Kernel-WHEA > Operational has "5 error sources are active" for me, for whatever that is worth.

The new posts on Windows install are interesting.


----------



## RonLazer

jomama22 said:


> Yeah, error sources are 5 as I said previously. I unfortunately did not see what they were prior to reinstall.
> 
> Personally, don't reallllly want to go re-enabling stuff for fear of just getting lucky lmao. I'll consider it once I get this 4000 setup stable and such.
> 
> What I can do is just create a new windows install on a separate ssd I have and see what happens. Will be a bit before I can do that, just busy this week.
> 
> At the very least I would kinda guess it' may be related to that asmedia USB controller that goes through the chipset.
> 
> I have my soundcard, an nvme, a SSD and HDD all connected through the chipset as well just for info.
> View attachment 2512252
> 
> View attachment 2512253
> 
> 
> Edit: yeah, had whea 19s at anything above 1900 prior.


These aren't even errors. It literally just says "information".

Just so everyone is clear, the WHEAs that you should be concerned with have a yellow triangle and are labelled "Error". If they are ID 18 then they are due to too much undervolting, probably from curve-optimiser. If they are ID 19 then they are due to infinity fabric instability. 

I've not seen any other ID numbers pop up with any regularity, would be curious if they have, but I now realise a lot of the discussion in this thread might have simply been about Kernel events.


----------



## jomama22

RonLazer said:


> These aren't even errors. It literally just says "information".
> 
> Just so everyone is clear, the WHEAs that you should be concerned with have a yellow triangle and are labelled "Error". If they are ID 18 then they are due to too much undervolting, probably from curve-optimiser. If they are ID 19 then they are due to infinity fabric instability.
> 
> I've not seen any other ID numbers pop up with any regularity, would be curious if they have, but I now realise a lot of the discussion in this thread might have simply been about Kernel events.


Yeah, I know where/what whea errors classify for whea 19. Whether I set a custom view for wheas, look at administrative events, or just check system events in general, whea 19 (were 99% bus/interconnect machine checks) no longer shows up. Hwinfo no longer reports bus/interconnect issues either.


----------



## ManniX-ITA

RonLazer said:


> I've not seen any other ID numbers pop up with any regularity, would be curious if they have, but I now realise a lot of the discussion in this thread might have simply been about Kernel events.


I've never seen myself these empty WHEA 20 but more than a few posted about them.
I remember got some running y-cruncher with the 3800x with not enough voltages or at IF over 1900.
But they were filled with data and marked as Error.

What I'm trying to track is the WHEA 19 coming at high rate.
They always have the same MCI data on all systems.


----------



## hazium233

I don't know if this is of interest, but above I said I had not yet seen WHEA 19 with Error Source 1 at 1933.

I was testing steps of CCD, and it seems that 0.925 and higher made Source 1 error "Corrected Machine Check" start to appear during OCCT Large AVX 2. These could appear as a pair 1 min apart.

Source 3 I had appear once at boot with 0.925 CCD combined with PLL 1.84 set (shows 1.87 "vtt" in hwinfo).

Otherwise I have made about as much progress with this as I have with my lead to gold alchemy project.


----------



## ManniX-ITA

hazium233 said:


> I was testing steps of CCD, and it seems that 0.925 and higher made Source 1 error "Corrected Machine Check" start to appear during OCCT Large AVX 2. These could appear as a pair 1 min apart.
> 
> Source 3 I had appear once at boot with 0.925 CCD combined with PLL 1.84 set (shows 1.87 "vtt" in hwinfo).


Thanks, it's interesting.
Low CCD and SOC at 1.1V seems to be beneficial to fix WHEA errors.
The problem usually is that, especially with 2 CCDs, there's a big impact on performances.


----------



## lmfodor

I just installed the new beta BIOS for ASUS Dark Hero, Agesa 1.2.0.3 PatchA. (SMU 56.53) The first thing that surprised me was that no WHEA 19 was activated when Windows boot up. I started with the TM5 test and the WHEA 19 errors began to appear very little by little. I can tell that less frequently than before. Let me clarify that I keep the same timings that I have in my 3800/1900 configuration, just go to 3866/1933. I do not notice performance degradation. Then I canceled TM5..take one screenshot and continued with another TTM5 execution, however the WHEA 19 stopped appearing. Pretty weird right? Before, immediately when booting with Windows, an endless amount of WHEA 19 appeared. Something seems to have been modified.

I will continue with Y-Cruncer. Do you think that with an increase in the IOD or CCD or even VDDP I can reduce it? The error 15 ACPI also calls my attention. I am tempted to disable the Realtek from the BIOS. What test would you do with this new BIOS? I clarify that it is not yet public, it is one that was shared by the Asus CH8 group










This is the ACPI error









Still running TM5 withot any other WHEA 19 yet,,


----------



## mongoled

Heads up regards high FCLK.

Seems that high FCLK is impacting CPU stability in which WHEA 18s are being triggered even though CO is tuned "correctly".

The random WHEA 18s and USB issues I was having stopped as soon as I dropped to 4067/2033.

I didnt change the CO settings, just dropped FCLK.

Disabling DF-CStates did not make any difference to stopping the random 19s, ive just tweaked NBIO to see if thats going to make a difference...

** EDIT **
No difference in tweaking NBIO either.

Relaxing CPU NB LLC seems to have helped, though its too early to come to any conclusion, I wish to not have to "drop" to 4066/2033

😄😄


----------



## Denvys5

[email protected] 1.1v---BIOS 7901---HCI---450%---BL32G36C16U4B.M16FB1








16gbit Micron Rev. B FTW

low priority threads coz I was using that PC, does not affect the result in my particular case


----------



## Asutz

little succes maybe, not sure, still testing still weird, most of the time the board wont change voltages
vddg iod too high or "safe" ?
vddg cdd too low ? 

other vddp's are on auto


----------



## mongoled

Asutz said:


> little succes maybe, not sure, still testing still weird, most of the time the board wont change voltages
> vddg iod too high or "safe" ?
> vddg cdd too low ?
> 
> other vddp's are on auto
> 
> View attachment 2512327


Can you take out the CPU, inspect it for any dirt, dust, possible corrosion ?

Once you take out the CPU, take out the CMOS battery.

You have a strange issue that you cannot change voltages which is the source of your issues

Do you still have audio issues with the above voltages?


----------



## Asutz

undusted this weak,cpu isnt old, 2 months but good point

its now a latency issue i think, win is new, acpi.sys latency spiking. most energy savings in win 10 are disabled, drivers etc is everything updated.


----------



## mongoled

Asutz said:


> undusted this weak,cpu isnt old, 2 months but good point
> 
> its now a latency issue i think, win is new, acpi.sys latency spiking. most energy savings in win 10 are disabled, drivers etc is everything updated.


Have you tried to run those with XMP settings ?

Im not finding what your exact modules are

Are they these ?


----------



## Asutz

2x 16gb crucial dr
xmp and or stock with stock/auto voltages tested no difference at all


----------



## mongoled

Asutz said:


> 2x 16gb crucial dr
> xmp and or stock with stock/auto voltages tested no difference at all


Thats not helpful

Please find a link to what you purchased so we can see what the modules are as I dont have any experience with those modules


----------



## Asutz

your link is correct mongoled, those are the sticks
they differ that much, mine are dual ranked, flashed older bios. trying that now


----------



## mongoled

Asutz said:


> your link is correct mongoled, those are the sticks
> they differ that much, mine are dual ranked, flashed older bios. trying that now


Was this RAM used on both the b450 pro carbon and ch7 ?


----------



## mongoled

I am guessing you have seen this link as its in your native language

[User-Review] - Crucial Ballistix DDR4-3600 32GB (2x16GB) [BL2K16G36C16U4R] Review | Hardwareluxx 

If not I would advise to go through that thread to see if anybody had issues running these on Ryzen platform


----------



## mongoled

mongoled said:


> Heads up regards high FCLK.
> 
> Seems that high FCLK is impacting CPU stability in which WHEA 18s are being triggered even though CO is tuned "correctly".
> 
> The random WHEA 18s and USB issues I was having stopped as soon as I dropped to 4067/2033.
> 
> I didnt change the CO settings, just dropped FCLK.
> 
> Disabling DF-CStates did not make any difference to stopping the random 19s, ive just tweaked NBIO to see if thats going to make a difference...
> 
> ** EDIT **
> No difference in tweaking NBIO either.
> 
> Relaxing CPU NB LLC seems to have helped, though its too early to come to any conclusion, I wish to not have to "drop" to 4066/2033
> 
> 😄😄


Has anybody here ran 1.3v CPU vSOC on Vermeer for extended periods of stress testing ?

My issues are clearly to do with vSOC, I am wondering if 1.3v is past the safe level for these CPUs.

I am using LLC of 6 with 1.3v and this seems to resolve the WHEA 18s and USB issues, just unsure on the longevity of using such vSOC ...


----------



## RonLazer

mongoled said:


> Has anybody here ran 1.3v CPU vSOC on Vermeer for extended periods of stress testing ?
> 
> My issues are clearly to do with vSOC, I am wondering if 1.3v is past the safe level for these CPUs.
> 
> I am using LLC of 6 with 1.3v and this seems to resolve the WHEA 18s and USB issues, just unsure on the longevity of using such vSOC ...


WHEA 18s have been confirmed to be from Vcore, are you running any Curve Offset?


----------



## mongoled

RonLazer said:


> WHEA 18s have been confirmed to be from Vcore, are you running any Curve Offset?


I had already explained above,

yes I am using CO

Same CO settings when utilized with FCLK below 2033 results in no WHEA 18s.

Once FCLK is increased to 2067 WHEA 18s are occuring.

Attempts to re-tweak CO results in no reliable result and no logical pattern.

I found that vSOC effects the stability, but ive yet to find a completly stable config, hence asking if anybody else here had used vSOC a 1.3v on vermeer ....


----------



## Asutz

quick 3800 profile
this is what i got, bios settings: ccd voltage 940, iod voltage 990 both typed in in amd overclocking section and the tweaker section zen timing showing both around 940
if i leave iod voltage and put in on auto it jumps to 1.047 iod, auto ccd voltage is around 0.900. it still looks like the ch7 makes them synchronous unless its on auto then it makes the 50mv automatic or synchron.dark hero feature only ?! and no function to set it asynchronous

there is pss support enable/disable/auto has something to do with acpi, that maybe is the troublemaker for acpi.sys latency spikes. disabled it but not sure if it was off before win10 install. what do you recommend?


----------



## ManniX-ITA

Asutz said:


> if i leave iod voltage and put in on auto it jumps to 1.047 iod, auto ccd voltage is around 0.900. it still looks like the ch7 makes them synchronous unless its on auto then it makes the 50mv automatic or synchron.dark hero feature only ?! and no function to set it asynchronous


Yes seems that's a problem with the CH7:









ROG Crosshair VII overclocking thread


New version of chipset drivers is up sadly need to reboot NOOOOOO ;) There u can see temps of my 3080 under water with max temps on mem when minimg. Thats before new pumop thats next to me and before liquid metal and pads upgrade.




www.overclock.net


----------



## jomama22

mongoled said:


> I had already explained above,
> 
> yes I am using CO
> 
> Same CO settings when utilized with FCLK below 2033 results in no WHEA 18s.
> 
> Once FCLK is increased to 2067 WHEA 18s are occuring.
> 
> Attempts to re-tweak CO results in no reliable result and no logical pattern.
> 
> I found that vSOC effects the stability, but ive yet to find a completly stable config, hence asking if anybody else here had used vSOC a 1.3v on vermeer ....


Yeah, I would imagine the increase in soc consumption is messing with you. My best guess is that you are stressing different points of the volt/freq curve now, because of the increase in soc power consumption, which may be less stable than the points used as lower soc power consumption.

Also, I would honestly guess that at the soc power consumption you have, you are probably near the point, or past it, of actually hurting your core clock enough to be worse off compared to a lower memory clock with lower soc power. 

From my testing on the 5950x and observing clock speed during tm5 testing, you loose about 25mhz for every +.05v of vsoc.


----------



## RonLazer

mongoled said:


> I had already explained above,
> 
> yes I am using CO
> 
> Same CO settings when utilized with FCLK below 2033 results in no WHEA 18s.
> 
> Once FCLK is increased to 2067 WHEA 18s are occuring.
> 
> Attempts to re-tweak CO results in no reliable result and no logical pattern.
> 
> I found that vSOC effects the stability, but ive yet to find a completly stable config, hence asking if anybody else here had used vSOC a 1.3v on vermeer ....


Well yes, 1.3V is well above the safe specified voltage. I guess I'm just confused why you are testing this,just scientific curiosity or do you actually want to run these settings daily?


----------



## Asutz

thx for the link to the ch7 thread. looks like im not the only one, not really confident that they fix it , bug or no bug possible that it is intended to buy their x570's, still no 1202b agesa.looking at other bios screens its possible to switch between synch/ansync so in theory not that hard to implement. which is also possible, amd deniying that feature it in there x470 agesa, which would suck, a good 470 with decent vrm dont have problems, vrms here on full load barely hit 40°c.


----------



## mongoled

jomama22 said:


> Yeah, I would imagine the increase in soc consumption is messing with you. My best guess is that you are stressing different points of the volt/freq curve now, because of the increase in soc power consumption, which may be less stable than the points used as lower soc power consumption.
> 
> Also, I would honestly guess that at the soc power consumption you have, you are probably near the point, or past it, of actually hurting your core clock enough to be worse off compared to a lower memory clock with lower soc power.
> 
> From my testing on the 5950x and observing clock speed during tm5 testing, you loose about 25mhz for every +.05v of vsoc.


Yes, this is one of the possible scenarios that I have already envisioned



RonLazer said:


> Well yes, 1.3V is well above the safe specified voltage. I guess I'm just confused why you are testing this,just scientific curiosity or do you actually want to run these settings daily?


Research and a want to be able to run it 24/7



As its looking I am probably going to have to drop down to 4066/2033, I want to avoid that as its very often a non post scenario with error code 07, where as 4133/2067 will post 95% of the time.

Will return to my previous BCLK overclocking to push the 4066/2033 into reliable posting territory and with an added benefit of clawing back the 150 mhz boost override that they removed from the previous possible 350 mhz boost override


----------



## mongoled

@jomama22
I did a new Windows install with as many peripherals as possible disabled to see if I could achieve the WHEA free result you saw.

On my setup it made no difference, was a pain in the arse doing this all through just a PS2 keyboard

😂 😂


----------



## RonLazer

mongoled said:


> Yes, this is one of the possible scenarios that I have already envisioned
> 
> 
> Research and a want to be able to run it 24/7
> 
> 
> 
> As its looking I am probably going to have to drop down to 4066/2033, I want to avoid that as its very often a non post scenario with error code 07, where as 4133/2067 will post 95% of the time.
> 
> Will return to my previous BCLK overclocking to push the 4066/2033 into reliable posting territory and with an added benefit of clawing back the 150 mhz boost override that they removed from the previous possible 350 mhz boost override


This is all stuff I've done for XOC purposes, but it's totally impractical for daily usage. Without dangerously high voltages you're going to see some serious performance degradation going over 1900MHz, let alone 2000MHz. There are diminishing returns on infinity fabric performance with frequency even without link-equalization shenanigans. 

Have you actually validated that your memory system performance is improving with these higher speeds in real mixed memory/CPU workloads like Linpack Extreme?


----------



## mongoled

Will do a comparisson for you with Linpack Extreme between 3800/1900 and 4133/2067.

If you like make a prediction



Per AIDA64, SiSoft Sandra and DRAM Calc membench test I am not seeing any noticable degradation same goes for CB23 performance

** EDIT **
1st result in - 3800-1900









2nd result in - 4133-2067









May as well do 4066/2033

brb



3rd result in - 4033/2033 (note: this is not a tweaked set, hence the drop in GFs)


----------



## RonLazer

mongoled said:


> Will do a comparisson for you with Linpack Extreme between 3800/1900 and 4133/2067.
> 
> If you like make a prediction
> 
> 
> 
> Per AIDA64, SiSoft Sandra and DRAM Calc membench test I am not seeing any noticable degradation same goes for CB23 performance
> 
> ** EDIT **
> 1st result in
> View attachment 2512338
> 
> 
> Rebooting.....


I'm tempted to try to replicate this since I also have a 5600X and a 4-dimm board. Only issue is we'd probably just end up comparing the strength of cooling solutions due to PBO, so if you're willing to try a static OC afterwards (let's say 4.5GHz all-core) and we can compare our 3800/4000 results with identical timings - would be interesting to see how impactful fclk silicon-quality reallly is!


----------



## mongoled

RonLazer said:


> I'm tempted to try to replicate this since I also have a 5600X and a 4-dimm board. Only issue is we'd probably just end up comparing the strength of cooling solutions due to PBO, so if you're willing to try a static OC afterwards (let's say 4.5GHz all-core) and we can compare our 3800/4000 results with identical timings - would be interesting to see how impactful fclk silicon-quality reallly is!


Good idea!

If you get your done today I will post mine tomorrow.

See results above



Though I cant post 2000 mhz, my post range is 1900/1933/2033/2066/2100


----------



## craxton

mongoled said:


> just tweaked that core a little and so far no sticking mouse


how do you know which core to adjust?

having the same minor issue (once ina great while)


----------



## RonLazer

mongoled said:


> Will do a comparisson for you with Linpack Extreme between 3800/1900 and 4133/2067.
> 
> If you like make a prediction
> 
> 
> 
> Per AIDA64, SiSoft Sandra and DRAM Calc membench test I am not seeing any noticable degradation same goes for CB23 performance
> 
> ** EDIT **
> 1st result in - 3800-1900
> View attachment 2512338
> 
> 
> 2nd result in - 4133-2067
> View attachment 2512343
> 
> 
> May as well do 4066/2033
> 
> brb
> 
> 
> 
> 3rd result in - 4033/2033 (note: this is not a tweaked set, hence the drop in GFs)
> View attachment 2512345


Can you repeat the 3800 results with the same timings? It's impossible to compare since you've changed multiple variables.


----------



## mongoled

RonLazer said:


> Can you repeat the 3800 results with the same timings? It's impossible to compare since you've changed multiple variables.


Will be tomorrow.

Was simply using tweaked sets that have been thoroughly tested.

I am guessing you want me to run the exact same timings for 3800 vs 4133 ?

Is Linpack not sensitive to dram timings ?


----------



## mongoled

craxton said:


> how do you know which core to adjust?
> 
> having the same minor issue (once ina great while)


If you are lucky when a crash comes it will record the crash in the event log (WHEA 18) and the ID of the core that crashed


----------



## craxton

@PJVol
the other day you stated you figured out how to get your Curve settings configured by
monitoring temps (as example) 1 would heat up 3 and 4 would heat up 6 etc

how did you monitor this???
i seen you mentioning a few tools but they were linux based and i wasnt sure if thats what they were for
if theres something out there than can monitor temps like this can you mention it at me?

currently running tests and passing core 0, core 4, failing 1, 5 with my curve settings when 0 and 4 have the highest curve applied...
scratch that,

passed 0, 1, 4, 2 the other two failed. 3, 6
...which have the lowest curve applied.......

it may have been @RonLazer who was speaking about this to me,

when the discussion of debug for zen timings was discussed.*


----------



## craxton

mongoled said:


> the ID of the core that crashed


well, each time mine has crashed its been core 6 so....now i know whats the issue. THANK YOU
well 3 and 6 as core cycler just failed on 3 and 6 both.

(would it be apcid ? its always been 6 but it would seem one has 11)


----------



## jomama22

craxton said:


> well, each time mine has crashed its been core 6 so....now i know whats the issue. THANK YOU
> well 3 and 6 as core cycler just failed on 3 and 6 both.
> 
> (would it be apcid ? its always been 6 but it would seem one has 11)
> View attachment 2512354
> 
> 
> View attachment 2512353


Id 6 would be core 3 (if we are starting at 0). Id#s are threads.

I'd 11 would be core 5 (again, if starting at 0)

Can confirm this by using cpuz and outputting an html report under 'tools' at the bottom pulldown menu there.


----------



## jomama22

mongoled said:


> Will do a comparisson for you with Linpack Extreme between 3800/1900 and 4133/2067.
> 
> If you like make a prediction
> 
> 
> 
> Per AIDA64, SiSoft Sandra and DRAM Calc membench test I am not seeing any noticable degradation same goes for CB23 performance
> 
> ** EDIT **
> 1st result in - 3800-1900
> View attachment 2512338
> 
> 
> 2nd result in - 4133-2067
> View attachment 2512343
> 
> 
> May as well do 4066/2033
> 
> brb
> 
> 
> 
> 3rd result in - 4033/2033 (note: this is not a tweaked set, hence the drop in GFs)
> View attachment 2512345


Wait, if I'm reading this right, 3800/1900 produced the best results for you yeah?


----------



## PJVol

mongoled said:


> I am guessing you want me to run the exact same timings for 3800 vs 4133 ?


It may be platform specific, but I found that gb3 has a couple of tests that show biggest performance impact on high-fclk config for me. Can you look into gb3 results as well, when comparing?
They are in the last tab - "memory performance", these *Stream* *Add Multicore* and *Stream Triad* used to drop noticeably at 2000+.










One more quick test is aida's FP64 Ray-Trace. On a 24/7 [email protected] config - it reaches 7800-7900, and still can't beat it with 1933+.


----------



## PJVol

craxton said:


> how did you monitor this???


When you click "debug" in zentimings, it updates smu pm table, and you may see current values for certain metrics. (I use ZenTimings, that Ivan kindly build for me with labeled offsets in pm_table in-app dump - many thanks for him)
Your per-core temps are here:


Code:


Offset 2E4: 25.94938000
Offset 2E8: 28.21523000  core0
Offset 2EC: 26.30354000 
Offset 2F0: 28.45338000  core1
Offset 2F4: 27.83200000  core2
Offset 2F8: 27.93000000  core3
Offset 2FC: 29.70323000  core4
Offset 300: 28.17354000  core5

Take note of "dummy cores" at 2e4 and 2ec.

Anyway, what I was trying to tell then, is knowing actual cores layout may help to see the whole picture of boosting behavior in real load, taking into account core's interaction.
It's not something that help you tuning CO - bad cores are bad cores, so you just have to decrease their bmagnitude, and thats it.


----------



## Eder

All new MSI 1.2.0.3a beta bios modded with unlocked PBS+CBS menu. Use at your own risk.


----------



## hazium233

I had a little time and just dropped the 3866 timings down a notch to 3800 to look at 1900 FCLK. I am not sure from the old posts if it is most desirable for only IOD to be 40mV under SOC, or if VDDP to CCD to IOD to SOC are all different steps of 40, or if VDDP to VDDG-Avg is multiple of 40... but I did 900 -> 905 -> 975 -> 1.075 with auto / droop. Then tried testing some other voltage steps and looking at Proc and ClkDrvStr AIDA tests to see what was consistent.

I am not entirely sure if boosting SOC to 1.1V was really more consistent than at 1.075 (where I reran 10c TM5), but I was going out for a bit and set Y-cruncher to run for four loops:



I need to check some more benchmarks. Also I hadn't tested all that many steps of IOD yet at 1933+... and those that I did were all 1.040+.


----------



## hazium233

Eder said:


> All new MSI 1.2.0.3a beta bios modded with unlocked PBS+CBS menu. Use at your own risk.


@craxton and I cry in B550 GEW


----------



## Eder

hazium233 said:


> @craxton and I cry in B550 GEW


No beta yet but I can unlock the latest release if you need it. Flashing beta right now on the x570 Unify.

Btw only placing these posts here because of the FCLK instability we experience lately.

They changed the PCI subsystem menu you can only choose chipset generation, option to change generation on PCI lanes is gone in my case.


----------



## craxton

Eder said:


> No beta yet but I can unlock the latest release if you need it. Flashing beta right now on the x570 Unify.
> 
> Btw only placing these posts here because of the FCLK instability we experience lately.
> 
> They changed the PCI subsystem menu you can only choose chipset generation, option to change generation on PCI lanes is gone in my case.


as Hazium said, both him and i are pouting bc you mentioned this lol...

im unsure how well itll do anything for our boards. 
(whea free on my end (minus 18 here and there still dialing in curve offset as of today)

if you would that would be GRRRRREAAATTTTTTTT 
it flashes normally thru MSI flash? or do i need to use a CH4a flasher ?
crossing fingers its just using MSI flash option inside the bios....
at this time, the bios they released for this board has been better than the others. but
i havent really used the bios as much lately.
i do wish it would stop going to my TV on the wall when its not on while going to the bios 
having to unhook the HDMI cable just to see the bios (to lazy to turn the tv on) is annoying....


----------



## craxton

PJVol said:


> When you click "debug" in zentimings, it updates smu pm table, and you may see current values for certain metrics. (I use ZenTimings, that Ivan kindly build for me with labeled offsets in pm_table in-app dump - many thanks for him)
> Your per-core temps are here:
> 
> 
> Code:
> 
> 
> Offset 2E4: 25.94938000
> Offset 2E8: 28.21523000  core0
> Offset 2EC: 26.30354000
> Offset 2F0: 28.45338000  core1
> Offset 2F4: 27.83200000  core2
> Offset 2F8: 27.93000000  core3
> Offset 2FC: 29.70323000  core4
> Offset 300: 28.17354000  core5
> 
> Take note of "dummy cores" at 2e4 and 2ec.
> 
> Anyway, what I was trying to tell then, is knowing actual cores layout may help to see the whole picture of boosting behavior in real load, taking into account core's interaction.
> It's not something that help you tuning CO - bad cores are bad cores, so you just have to decrease their bmagnitude, and thats it.




HMMMMMMMMMMMMM
wouldnt it go from 2E4 all the way down to 30C ? as my two "dummy cores" 
show near nothing in heat.... 

can you make sense of whats being shown?


----------



## craxton

better yet @PJVol whats it say down from 304 to 30C on your debug?
or does yours say 0.9xxxxx or something like this???

im unsure who ivan is, and me knowing this info im not sure would help me much.
but IT WOULD HELP knowing if those cores are INDEED still active just "off" 
which might be why my chip likes more voltage than the rest of you (or i believe?)
7xxx offset for 26 CO with LLC2 (this board UNDERvolts ram even with llc1-2 still undervolts so i set 1.48 bios
get 1.47 hwinfo....


----------



## craxton

jomama22 said:


> Id 6 would be core 3 (if we are starting at 0). Id#s are threads.
> 
> I'd 11 would be core 5 (again, if starting at 0)
> 
> Can confirm this by using cpuz and outputting an html report under 'tools' at the bottom pulldown menu there.


thank you, i suppose this confirms what the tool stated to be
(off in prime) highly noted. ran tests earlier and didnt fail but.....not having -30 curve like most the others
is a splinter under my fingernail thats buggin me to death...

id almost trade whea 19s for a chip that ran -30 curve easy....


----------



## Eder

craxton said:


> as Hazium said, both him and i are pouting bc you mentioned this lol...
> 
> im unsure how well itll do anything for our boards.
> (whea free on my end (minus 18 here and there still dialing in curve offset as of today)
> 
> if you would that would be GRRRRREAAATTTTTTTT
> it flashes normally thru MSI flash? or do i need to use a CH4a flasher ?
> crossing fingers its just using MSI flash option inside the bios....
> at this time, the bios they released for this board has been better than the others. but
> i havent really used the bios as much lately.
> i do wish it would stop going to my TV on the wall when its not on while going to the bios
> having to unhook the HDMI cable just to see the bios (to lazy to turn the tv on) is annoying....


I see your board has bios flashback so I added B550 Gaming Edge Wifi to the mod list. You can flash it with the MSI flash option in bios. I always have a stick with flashback bios in case something goes wrong but never had any issues since I began a year ago. 

Now back on topic. I still got whea-19 errors with latest beta bios. Haven't got time to test a lot of values for vddg's and soc so I'll test some more tomorrow. The second test produced 1 error every minute. These are the best results I had in a long while


----------



## craxton

even tho i sent a PM i wouldnt respond to it either...

but this is what my cores are

core 2-offset 300 (2f8? 45c (core 4 near)

core 1 offset 2FC <core 0? near core 5>
and core 3??

core 5 offset 30C <core 3>

core 4 offset 308 <core 2>

core 3 offset 304

core 0 offset 2F4 <core 1>

take a note that 2F8 while running core cycler is never hit only warms up while 
core 2 is being hit around 74c (worst core is core 3 it would seem) so thats where ill adjust. 
was trying to figure out where the cores where located etc...
i do know that my Debug looks way different almost like all cores are there...
just turned off.


----------



## craxton

Eder said:


> I see your board has bios flashback so I added B550 Gaming Edge Wifi to the mod list. You can flash it with the MSI flash option in bios. I always have a stick with flashback bios in case something goes wrong but never had any issues since I began a year ago.
> 
> Now back on topic. I still got whea-19 errors with latest beta bios. Haven't got time to test a lot of values for vddg's and soc so I'll test some more tomorrow. The second test produced 1 error every minute. These are the best results I had in a long while


thank you...ill download this now and safe keep it.
ill be off work for a few days come monday thats when ill play and tinker the most.

(161,160,163 i have all backed up.)
161 was the best i used uptill now....
what all options have you unlocked ??


----------



## KedarWolf

Eder said:


> All new MSI 1.2.0.3a beta bios modded with unlocked PBS+CBS menu. Use at your own risk.


Anyone test them? I had an issue where UBU Tool bricked my Unify-X on the previous BIOS and I see these are UBU modded as well I think.

There are UBU unmodded versions available I can use until I'm sure. :/


----------



## craxton

KedarWolf said:


> Anyone test them? I had an issue where UBU Tool bricked my Unify-X on the previous BIOS and I see these are UBU modded as well I think.
> 
> There are UBU unmodded versions available I can use until I'm sure. :/


....im unsure what UBU means, but now im not sure i wanna test 
as you know what your doing as i well...flash manufacture made bios..

(offtopic as always)
to anyone with the answer,
Veii before going out and making music stated CTR would know
if my chip had some sort of (unique thing)

what do i look for?
would this be one of those unique things?

setting negative 20 to all cores using curve but core 3 which needs positive 1
seems well....idk...

does CTR always state CCX#1 and CCX#2
like this,








(EDIT) 

fogured out what cores are what....


----------



## PJVol

craxton said:


> can you make sense of whats being shown?


That temp block offset was taken from the debug log you've posted some pages ago, likely it was from older smu pm_table version (older bios), as they may differ.

Indeed, on your screen, temps block starts at 2F0 ( - 30C) - as in 380905. dummy cores are @2f0 and @2f8










PS: Ivan Rusanov, @infraredbg (developer of this useful utility)


----------



## ManniX-ITA

RonLazer said:


> Have you actually validated that your memory system performance is improving with these higher speeds in real mixed memory/CPU workloads like Linpack Extreme?


Thanks, I had actually forgot about it despite being in evidence on my desktop the whole time.
Much better and easier to fine tune the right CCD and PLL voltage than Geekbench 5.

PLL above 1.810V for me is only worsening performances and I get a reboot at 2.0V with P95 and Linpack



Spoiler: IF 1900

















Spoiler: IF 2000 CCD 1070mV

















Spoiler: IF 2000 CCD 1080mV PLL Auto

















Spoiler: IF 2000 CCD 1080mV PLL 1.810v

















Spoiler: IF 2033, couldn't get it above 603 with additional tweaking


----------



## Veii

goondam said:


> careful i have 5950x and i recently upgraded to b550 pro art.
> i have a very rare but super annoying issue, not sure if its whea error related
> 
> issue is this sometimes during login or when opening a app/program windows will freeze, both cpu/disk go to 100% usage. pc will then restart after couple minutes as the cpu reaches max temp. this didn't happen on the old board(x470 ch7). happened on both old windows installation(previous mobo) and a new fresh clean install of windows


Can the proArt even fuel this chip ? The VRM is weak, i wouldn't pull more than 210A from it
Strangely never have this, but being sure that i everytime disbale MyAsus and Asus Crate
Both spyware dlls, which inject into system32 after you let it pass the bootloader

I should call it malware, but it's used for communication with useful programs
Soo it's just spyware at its best, or bloatware at it's nicest | as they take resources


hazium233 said:


> I am not even using PBO, which at one point I wondered if the default power limits or some shenanigans from that could be related. I originally thought get ram / fabric stable then work on CO. Also I have been logging some benchmarks because I also wanted to look at ram scaling for my system and I though I would keep default limiters for this to make it more pure. This is probably pointless, but I wanted to do it.


Stock with open PBO limits or finetuned soo the latency result is as stable as possible
You will get a lot of variance, and it can be everything from lack of vcore, not enough soc, hitting power limits because of the high FCLK and SOC powerdraw
Its recommend to finetune the cpu first and be sure its y-cruncher stable at any FCLK you move forward

Using core cycler is nice and very handy , but can not justify the time required redoing them every fclk step
Y-cruncher is good enough for it. "Only" takes 6h to get TM5+OCCT Extreme+X-cruncher stable
And if something fails, like OCCT mid run, you could redo TM5 [to skip people questioning your high FCLK]
Run Aida64 before you give TM5 a go. A finished TM5 eats still resources, same with ZT, later only.


MattKelly said:


> So is the ASRock B550 Phantom ITX considered the best ITX board in terms of pushing FCLK the farthest? Are there any other ITX boards (X570 or B550) worth considering, as far as WHEAs & FCLK are concerned?


Im not sure, i dislike close to all 5xx series boards at this point
Unsure what to recommend at all. Even on the ProArt i do have a little Problem with Asus Bios team and Thunderbolt 4 (hidden settings)
Which UAD makes more than enough issues on their own with WDM drivers. Both companies are not excusable 

I saw you PMd me also on Discord, but been doing the last 2 weeks OC work on an e-sport pc managing team
Just a bit freelancer work, to be able to pay my rent. But barely took time for myself or the Rev.E here. Only up to 4000C14-10-18-14
Really dont know what ti recommend so far
AGESAs are still problematic and 1203A sounds without changes at all. Nothing that shouldnt be there since SMU 56.30, including SOC EDC, TDC and STAMP control the "leakers" found for the APUs


mongoled said:


> Has anybody here ran 1.3v CPU vSOC on Vermeer for extended periods of stress testing ?
> 
> My issues are clearly to do with vSOC, I am wondering if 1.3v is past the safe level for these CPUs.
> 
> I am using LLC of 6 with 1.3v and this seems to resolve the WHEA 18s and USB issues, just unsure on the longevity of using such vSOC ...


"Anybody" here~
1.25v is preapplied after 2100 FCLK, around 1.1875-1.2 is required for it
Up to 1.3v is usable, but thr amount it cuts into the powerbudget, makes it more and more a bad decision

It might have been even you who pushed me to redo my voltages
Been running before 1.26ish
But that was with lower IOD

I figured after time, that it masks issues
Even masks low procODT
Overall, welcome to my world of struggle at and past 2033, you and @ManniX-ITA
I think you can orient to everyrhing i posted 4 months ago
Including the AMD Maximum Voltage thread

Everything including high 1.8 VDD issues should apply to you ~ up to 1.82v is fine, someday 1.83v depends
===================
Ron's writeup on throttling is on many parts correct. But the foundation is wrongly assigned
Neither WHEA 19s nor the low performance on high FCLK have to with xGMI and xCAKE
CAKE which defines the throttle range

Throttling that happens internally, will always happen. Thats how cache settles down after beinf dynamic
On 1 CCD units its easier to spot, when Write bandwidth doesnt reach perfect half max MCLK bandwidth
It appears it having to do with a bad mem-timings set
But unlike Matisse its not the case here
It's range depends on FCLK but dual CCDs have unknown to me peak limits

On 1 CCD the value depends on the stability of FCLK and Curve Optimizer
But not on the memory, even when it sounde contraproductive for a memory test result

There is an exploration going on how these CAKE throttle ranges (64 being stock) affect boosting and stabilty
But it neither does influence WHEA appearence nor throttling appearence
Throttling will always be active.
Just for me its full been hardcrashes, while some report WHEAs
Yet i do get #19 too, just it doesnt need to appear. Nothing triggers it, but as its happened, it can happen
I'm no exception to anyone else, my sample isnt special either. Its strange but not with FCLK behavior


----------



## Veii

Any throttling you get mostly is lack of powerbudget, if instability is pushed away as potential option
You can fix the CPU at 1.15v @ 4.2Ghz (4ghz for dual CCDs) and FCLK will continue to scale linearly from 3600 upwards

Testing it with one fixed voltage can work, but trusting on auto is not a good idea
There are different predefined interconnect speeds between FCLK, but its not "after 3600 or after 3800"
There is no fixed inentional throttling range

There was one and i've complained about it, but this topic is long time gone
How you should test, is by adjusting voltages till every FCLK has perfect non variable results.
(It can not magically get better unless it didnt reach it beforehand. Adjust till you get the lowest latency, then continue testing)
On a dual CCD again, i can see how this can be hard finding any holding point

There are many Sensors in there, and many Options you can throttle
No whea is reported because of throttling. The OS has no control over SMU or FIT
Dont mix it up please, these are not the same things and the cpu is based upon overdrive, throttleback and autocorrection.
And on these parts, it does a fantastic job.

Aida64 reports i dont use as comparisons with anyone.
What only matters is what you get out now and got before
Its sensitive and SiSandra is equally very sensitive.
If both dont show any positive change, then it doesnt matter what games or TM5 report
You need constant improvement, as tiny as it be ~ to figure out all the little autocorrection locations that can happen
And VDDG in this case is dynamic too, unless you enable UncoreOC mode.
I wouldnt enable it, but everyone with their own tricks 

Just dont missjudge bad performance by reaching artificial AMD EDC Fuse limits,
with bad performance because of your own fault
There is no throttling on FLCK till 2100, when you have correct settings
2133 is still unstable, and 2167 is unusable yet

"Throttling on FCLK" looks different. It appears on L3 and on memory latency
Its not 0.3 ns and not 1 or 2 ns , i've read here
It's 20ns and higher, sometimes 100ns
This is what CAKE really does once you reach their preconfigured threshold
0.3ns difference is unstableness, but not what has been described here as "throttling"
Its just slight unstableness and autocorrection


----------



## hazium233

I guess I need to take a break from the ram then and figure out my core situation. Wasted some more time today on some stuff. 

On a whim the other day after I was done with banging my head on WHEA 19, I ran CTR diagnostic the first time - "Golden Sample." I think 1usmus is just trying to make people feel happy about their chips. 

Otherwise I didn't make any more headway WHEA 19 - Source 0 at 3866 with my little tests, except that it also seemed IOD at 0.980 might have slowed them down. With increase core VRM switching, they slowed to 60 in 5 minutes of OCCT large. AIDA latency had gone down to ~57.1ns. Global C-State disabled lowered to 47 per 5minutes with above, but latency was worse.

Reverted C-states, did PBO-Enabled, 1x, motherboard limits. That did about +100 errors in the first couple seconds, then slowed down a little. I canceled it early with 202 at 2:44 mark. Two Source 1 errors showed up in there, just like before they were together in a pair. Ah well.

I had also run TM5 for 25cycles at the 3800 / 1900 speed just to do it. That boot had 58ns latency, I probably should have worked more on the timings. It is hard to compare to the sheet with many higher core clock results, but these seem to lose to a 3733 result (that one didn't hit Write limit though).

I would have liked to try all 19's, but they don't seem to want to do 19t tRCDRD anyway (same as they didn't want to do 18t at 3600). I think I am pulling these sticks in a little while to make sure the 3600C16 2x8GB set I ended up with at least are functional so farewell dual rank E for the time being.


----------



## craxton

KedarWolf said:


> Anyone test them? I had an issue where UBU Tool bricked my Unify-X on the previous BIOS and I see these are UBU modded as well I think.
> 
> There are UBU unmodded versions available I can use until I'm sure. :/


can confirm the B550 gaming edge wifi bios works...

dont much change the fact i have NO IDEA what all that extra stuff is..
but theres a WHOLE HEAP of stuff shown now after flashing.


----------



## craxton

hmmm, is this what you see @mongoled and stated it does nothing to change VDDP values?
i dont even see it listed anywhere inside HWiNFO (did a few times but value was always .01 greyed out,
to which would disappear etc...bios just says N/A..


(NOTES TO CONSIDER) i changed NOTHING INSIDE ANY OPTIONS 
if others wish, i can post what is default to see if somethings different (on their board than mine)
to maybe perhaps see if something inside this unlocked bios is whats triggering your flooded whea's


----------



## ZenMasterRam

Hello, I want my RAMs to run at 4000 MHz with an Fclk value of 2000.
I managed to get to Dram 3966 MHz with Fclk 2000.
I've already posted that I need help here and don't know what I can do to be able to run safely on the desired value. The link to my post here.









Trying to get Ram speed 4000Mhz on 5900x pls help


Hi Guys, First of all, my english is very bad so i'm sorry, please don't judge me 😅. I need expert help. I've never done Ram OC before, it's my first try. For days I try to bring my RAM OC, the Fclk 2000 and Ram 4000 MHz to find out whether my CPU can do that. I've built my new setup...




www.overclock.net





I ask for help did not want to post everything in here again, I would be happy if you are interested.

Kind regards


----------



## rossi594

ZenMasterRam said:


> Hello, I want my RAMs to run at 4000 MHz with an Fclk value of 2000.
> I managed to get to Dram 3966 MHz with Fclk 2000.
> I've already posted that I need help here and don't know what I can do to be able to run safely on the desired value. The link to my post here.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Trying to get Ram speed 4000Mhz on 5900x pls help
> 
> 
> Hi Guys, First of all, my english is very bad so i'm sorry, please don't judge me 😅. I need expert help. I've never done Ram OC before, it's my first try. For days I try to bring my RAM OC, the Fclk 2000 and Ram 4000 MHz to find out whether my CPU can do that. I've built my new setup...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> I ask for help did not want to post everything in here again, I would be happy if you are interested.
> 
> Kind regards


Did you check the event viewer for Whea errors?

Start -> Event Viewer -> Custom Views -> create custom view -> by source -> WHEA-Logger

If you running into anything but WHEA 19 warnings your system will most likely be unstable. 18s for example cause Bluescreens.


----------



## rossi594

Is anyone here running 3667 MT/s on CL14-14-14-28? I usually end up with a few errors an hour into testing ... 

My chip has a hole / hates 3800 and 4000 runs stable at cl 16 but troughs WHEA 19s.


----------



## munternet

Complete noob here with the AMD ram tuning
Where is the best tutorial and what should I be aiming for?
This is an Aida shot of my current setup
Cheers


----------



## PJVol

Mind to update AIDA to latest version, since results used to differ noticeably between verions and hard to compare, except latency. 
Regarding the latter, it looks fine for [email protected] and ram [email protected]


----------



## YoungChris

Eder said:


> All new MSI 1.2.0.3a beta bios modded with unlocked PBS+CBS menu. Use at your own risk.


How about unlocked voltage limits? I want vdimm >2!


----------



## Veii

Eder said:


> All new MSI 1.2.0.3a beta bios modded with unlocked PBS+CBS menu. Use at your own risk.


God job 
Was playing with the X570 Tomahawk Wifi (.150) , around 3 days ago
Haven't tried higher FCLK, the 5900X user awaits new rams

Jumping back'n'forth between 4000C16-16-16 sets @ 1.4 or 3600C14-15-15 @ 1.45 (32gb)
First one appears superior, but the 2nd TeamGroup set is known to have it easier with CL12-12
Anywho, thank you for the continuous effort on the bios mods 

@craxton this VDDP here is starting from 1050mV higher - still not the one we are looking for
I do think that MSI mistook it ~ it's more closer to what ASUS specifies as Standby VDDP voltage
Sadly ASUS didn't think that it can drop to 800mV and put a 900mV lock on it.
You mostly are fine with what runs. Only if it's buggy, 930mV or more would be set. It should be fixed at 900mV on the newer bioses. One could expect it at this point of time

For MSI users, save this G-Drive link
MSI - Google Drive
And do you maybe want to give MSI Dragon-Power , AMD version a shot ?
Dragon Ball, even the last 3 versions do not work on AM4 ~ but MemTweakIt & Dragon Ball do work across multiple Z490 & Z590 Boards, even if they are not Asus or MSI branded

Maybe we'll get a Dragon-Ball utility for AM4 someday upon request ~ but try how much Dragon-Power on AM4 can read out
Maaybe you get lucky with access to some more voltages 

EDIT:
I forgot to add,
AMIFlash (AfuWin) does finally allow flashing bios-mods
I know it's a win utility and technically more unsafe - but not licensed bioses pass through with it (temporary replacement for flashrom)
~ and as it flashes in blobs, i feel it a bit more safe, than bios's own CRC checking utilities


----------



## T[]RK

I returned back just to share some results with memory overclock. I sold previous RAM module - Team Group T-Force Dark Pro "8Pack" Edition [email protected] It was nice, but i don't really need that much RAM (~48Gb in total). Now i use Team Group T-Force Xtreme [email protected] as [email protected] It's still on cheapest B450M DS3H v2!

Here is screenshot from ZenTimings:








It pass 25 cycles of TM5 with 1usmus_v3 config. Also i didn't saw any WHEA errors so far (i didn't saw them in event viewer). There was problem with HDD, but i fixed it i guess.

At the same time, i think latency in AIDA64 is a bit high - +\- 58ns. I guess some timings are high, but which? tRFC? I can use tRFC calculator (mini) to play with it a bit - no problem, but how to calculate tWTRS and tWTRL?


----------



## Veii

T[]RK said:


> I returned back just to share some results with memory overclock.


Please try this 








Shouldn't be performing much slower, it's a preparation set for future 1T work
The used tRFC is not a clean divider , neither from tRTP nor tWR








It will run, but eat away performance or be even skipped if you are unlucky
tRFC mini multiplier = tRTP
tWR is then double this

tRTP and tWR combination doesn't always have to match up, as long as the results on both are less than 2 decimals.
Else it desync's and tRFC is postponed , or something else is postponed
Just increases latency for nearly no reason

For something near your result, it was 336-250-154 (for the 16-16-16-16-32-48 set)
Would look slower but i bet it performs better than 304
160ns do look better as a number than 176.842105263158ns
but that 176~ number is more accurate 
It's something old that i fight against.
"You can not use world clock numbers with memory where everything runs in integers.
Each of the timings are placeholders for long 11-18 decimal numbers.
And rounding issues are causing degraded performance"


T[]RK said:


> At the same time, i think latency in AIDA64 is a bit high - +\- 58ns.


Slightly high, 16-16-16 3800 is not hard to run or fast. Around 56-58ns is expected ~ up to boost
Faster than XMP but not that fast compared to most of the results in the sheet








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com






T[]RK said:


> but how to calculate tWTRS and tWTRL?


tRRD_ and tWTR_ are "transfer timings". "mid section"
Between reads and between writes
Lowering them , makes memory more snappy between "done executions"
But it increases strain on it by quite a bit.
It's more worth to push them up and lower primaries further down

They have a combination with SD, DD's timings on the right and a combination between both
_L can be many things as "rulesets"
sometimes it's double of _S , sometimes tWTR_L is only double of tRRD_L
There are many possible options, but keep the sheme up
tRRD_, +2 in between
tWTR_ 2x or 3x _S value
=============================================
I forgot, push 1.42v with it
tRFC could be a bit "too low" but i think it can run with the given set
Just 20mV more


----------



## T[]RK

Veii said:


> Slightly high, 16-16-16 3800 is not hard to run or fast. Around 56-58ns is expected ~ up to boost
> Faster than XMP but not that fast compared to most of the results in the sheet


I'm a FOOL - i installed RAM in slot 1 and 3 instead 2 and 4. That's why it's slower... I have NO IDEA how it's happened, I swear! %))


Spoiler: EPiC_FAiL photo












P.S. Unused DIMM slots have got silicone covers on it. I added them to protect from dust.


Thanks for you respond @Veii! I read everything, a lot work to do and test it. Will return with results.


----------



## Veii

T[]RK said:


> Spoiler: EPiC_FAiL photo


Haha 
Which TeamGroup ram did you have, before selling it off ?
The ARGB ?

Still looking for some 32gb set, but i wasn't happy with KedarWolf's result (on the 16-16 set) ~ kind of
Might want to grab some can of compressed air or WD40 Oil-Free contact cleaner (there are two WD40, a green one which is for PCBs & an oily one)
Too "undust" the DIMM slots and maybe even "fix soon happening" corrosion inside 4xx series sockets
3xx where due for it last year (3 years lifetime) ~ after some time the pins started to show signs of corrosion and didn't make a good contact (did affect nearly all 3xx boards)


----------



## T[]RK

Veii said:


> Which TeamGroup ram did you have, before selling it off ? The ARGB ?


Nope, i got allergy on ARGB.  I sold Team Group T-Force Dark Pro "8Pack" Edition [email protected] (Single Rank, Samsung B-die). I still got report from Thaiphoon if you need it. It was good memory, but i got too much RAM in general (2x8 GB Dark Pro and 4x8 GB Xtreme). It's good RAM, but i don't really need it. And i no longer can get similar Dark Pro kit, so... 

Also, i saw for sale nice G.Skill Trident Z set with Samsung B-die chips rated 4266 MHz (19-19-19-39, 1.4V, A1 PCB). One person got abnormal low latency (at 3800 [email protected] below 50ns) with similar set and i wonder... maybe get it too? And yeah, G.Skill got temp sensor.


----------



## 1s1mple

Any settings i can adjust for better timings etc?

Hynix C die kit

I tried 3800 no luck with 1.4v, cant post.


----------



## ManniX-ITA

Veii said:


> Any throttling you get mostly is lack of powerbudget, if instability is pushed away as potential option
> You can fix the CPU at 1.15v @ 4.2Ghz (4ghz for dual CCDs) and FCLK will continue to scale linearly from 3600 upwards


Thanks, it's indeed a good tip to test with static OC 

Made some very good progress today.
What you say it's true and it's an important factor but it's not the root cause of my performance degradation
More likely what @RonLazer said about the mode switch above 2000 MHz but the degradation is not on the GMI links.
The GMI links works properly and at full speed; otherwise it'll be evident in AIDA and Sandra synthetic bandwidth and latency tests.

I think the SoC quality and maybe also the CCDs (the common part) quality plays a role.

*Good news is that I've found the option that (mostly) fixes the performance degradation at 2033*
It's also improving a bit 2067 for me but not much.



Spoiler: I'll put the rest in a spoiler as it's very long...



But of course there are also bad news.
First; it's an option in AMD PBS menu. So you need it unlocked to test it.










Not sure what it does but seems to fix what looks a "clock sync" issue.
It helps me up to a point.
Perfect till 12 cores but at 16 cores still can't recover all the loss.
Definitely related to the bandwidth.

_Don't use it at FCLK 2000 or below, it only degrades for me._

At FCLK 2067 had good results in stabilizing a bit but with this AGESA for me is unusable.

You are right @Veii that the SOC dips into the power budget.
But what would be the solution? I don't have many options.
Maybe you have an amazing IOD but mine needs loads of volts even to POST 

To get the most out of FCLK 2000, the voltages have to be very specific for me.
Made a lot of tests with Linpack with static OC at 4.0 and 4.25 GHz.

I need a bit more VDDG IOD & CCD at FCLK 2033 but it only scales up in performances with VSOC.
And it scales up to 1.3V; at 1.131V can't boot in Windows.

Setting CLKREQ# enabled at 2033 is fixing the loss but needs 1.3V:










But at that point at 1.3V the SOC is eating too much from the power budget, this is FCLK 2000 at 1.3V:










Almost same result... at the end no different from FCLK 1900.

But I've made a lot tests using a set of non optimal but good enough for both 2000 and 2033 with different number of cores.

If you have a 6/8 cores is easy, even 12 cores is already a stroll.
But for my 5950x with all cores enabled is though.
I see the degradation kicking in with 16 cores at 2033.
At 2067 it's already a mess with 8 cores and is not stable even with 6.

This is 8 cores FCLK 2000:










This is the same at FCLK 2033, here there's already a small degradation costing a few GFlops:










And here with CLKREQ# enabled, a little better than FCLK 2000 instead that a little worse:










12 cores is where Linpack starts enjoying higher FCLK.
FCLK 2000:










FCLK 2033:









FCLK 2033 with CLKREQ#:










It's not much but is repeatable; whenever is enabled it's a bit more faster and at some point instead of crashing down holds up.
Guess it means that is more stable than without.

Up to some point which is not enough for my 5950x to loose something.
Maybe there's also a thermal factor and someone with a better cooling will have better luck.

It doesn't have a negative impact on memory scores, almost sub 50ns damn... 2067:










2033:


----------



## jomama22

ManniX-ITA said:


> Thanks, it's indeed a good tip to test with static OC
> 
> Made some very good progress today.
> What you say it's true and it's an important factor but it's not the root cause of my performance degradation
> More likely what @RonLazer said about the mode switch above 2000 MHz but the degradation is not on the GMI links.
> The GMI links works properly and at full speed; otherwise it'll be evident in AIDA and Sandra synthetic bandwidth and latency tests.
> 
> I think the SoC quality and maybe also the CCDs (the common part) quality plays a role.
> 
> *Good news is that I've found the option that (mostly) fixes the performance degradation at 2033*
> It's also improving a bit 2067 for me but not much.
> 
> 
> 
> Spoiler: I'll put the rest in a spoiler as it's very long...
> 
> 
> 
> But of course there are also bad news.
> First; it's an option in AMD PBS menu. So you need it unlocked to test it.
> 
> View attachment 2512547
> 
> 
> Not sure what it does but seems to fix what looks a "clock sync" issue.
> It helps me up to a point.
> Perfect till 12 cores but at 16 cores still can't recover all the loss.
> Definitely related to the bandwidth.
> 
> _Don't use it at FCLK 2000 or below, it only degrades for me._
> 
> At FCLK 2067 had good results in stabilizing a bit but with this AGESA for me is unusable.
> 
> You are right @Veii that the SOC dips into the power budget.
> But what would be the solution? I don't have many options.
> Maybe you have an amazing IOD but mine needs loads of volts even to POST
> 
> To get the most out of FCLK 2000, the voltages have to be very specific for me.
> Made a lot of tests with Linpack with static OC at 4.0 and 4.25 GHz.
> 
> I need a bit more VDDG IOD & CCD at FCLK 2033 but it only scales up in performances with VSOC.
> And it scales up to 1.3V; at 1.131V can't boot in Windows.
> 
> Setting CLKREQ# enabled at 2033 is fixing the loss but needs 1.3V:
> 
> View attachment 2512571
> 
> 
> But at that point at 1.3V the SOC is eating too much from the power budget, this is FCLK 2000 at 1.3V:
> 
> View attachment 2512572
> 
> 
> Almost same result... at the end no different from FCLK 1900.
> 
> But I've made a lot tests using a set of non optimal but good enough for both 2000 and 2033 with different number of cores.
> 
> If you have a 6/8 cores is easy, even 12 cores is already a stroll.
> But for my 5950x with all cores enabled is though.
> I see the degradation kicking in with 16 cores at 2033.
> At 2067 it's already a mess with 8 cores and is not stable even with 6.
> 
> This is 8 cores FCLK 2000:
> 
> View attachment 2512573
> 
> 
> This is the same at FCLK 2033, here there's already a small degradation costing a few GFlops:
> 
> View attachment 2512574
> 
> 
> And here with CLKREQ# enabled, a little better than FCLK 2000 instead that a little worse:
> 
> View attachment 2512575
> 
> 
> 12 cores is where Linpack starts enjoying higher FCLK.
> FCLK 2000:
> 
> View attachment 2512576
> 
> 
> FCLK 2033:
> View attachment 2512577
> 
> 
> FCLK 2033 with CLKREQ#:
> View attachment 2512578
> 
> 
> 
> It's not much but is repeatable; whenever is enabled it's a bit more faster and at some point instead of crashing down holds up.
> Guess it means that is more stable than without.
> 
> Up to some point which is not enough for my 5950x to loose something.
> Maybe there's also a thermal factor and someone with a better cooling will have better luck.
> 
> It doesn't have a negative impact on memory scores, almost sub 50ns damn... 2067:
> 
> View attachment 2512580
> 
> 
> 2033:
> 
> View attachment 2512581


Just so you know, you can't compare those last two aida shots you posted in the spoiler. Your first one is using only 8 cores with pbo vs all 16 with pbo. You cant do this and expect to get any comparable results.

As I have shown in the past, single ccd pbo will be the best case scenario for aida latency with the exact same timings. We are talking upwards of 1.5ns advantages here. My testing showed a 1ccd (8cores) pbo @ 5200 fmax achieving 51.9ns compared to full 2ccd fmax 5200 achieving 53.4ns with the exact same memory speed and timings.

1ccd and 2ccd setups act opposite each other interms of aida latency. 1ccd benefits from pbo and will lower aida latency the higher the fmax will go. It also suffers when using a static allcore oc. 2ccd setups are the opposite, with allcore OCs beating any pbo results by about .7-.8ns.

So don't go and fool yourself and come to incorrect conclusions.

This is why trying to compare someone's timings/latency between 1ccd and 2ccd chips is null and void.


----------



## Veii

ManniX-ITA said:


> You are right @Veii that the SOC dips into the power budget.
> But what would be the solution? I don't have many options.


Telemetry Fake it 
This works - else adjust VDDG higher till there is only 40mV difference to between IOD and SOC 
You'll need this 1.2v+ , there is no way around it
But you can lower 12-13A from SOC, without FIT noticing

1.25V =30A , also no way around it except by faking it
Maybe adjusting IOD and CCD ~ re'adjusting like i did afterwards

Mostly you go down to 18A, but it's still a big cut
And for my sample with only 12(2)A EDC Fuse ~ where the 2nd CCD takes another 20A at least on 550mhz
It's annoying, but nothing you can do about it.

Just don't overdo telemetry faking, as results will reverse. FIT notices that, soo only a little range works for both VCore and SOC


----------



## craxton

@Veii a while back 
You mentioned a whole heap, 
Of stuff like DF, CSTATES, and we'll LOADS MORE 
That I now have access too. 

Is this something you have saved? Not being able to run curve on 3 cores at all is..
Well what I'm asking might not help, 
But I've bookmarked alot of info sadly this isn't one of those things 
I bookmarked. 

On my phone, forgive if it looks odd.


----------



## jomama22

craxton said:


> @Veii a while back
> You mentioned a whole heap,
> Of stuff like DF, CSTATES, and we'll LOADS MORE
> That I now have access too.
> 
> Is this something you have saved? Not being able to run curve on 3 cores at all is..
> Well what I'm asking might not help,
> But I've bookmarked alot of info sadly this isn't one of those things
> I bookmarked.
> 
> On my phone, forgive if it looks odd.


Turning off cstates isn't going to help with core boosting behavior. It may let you have lower CO values, but it's fake and will not allow better performance. It will also decrease single core boosting behavior. 

It will help dpc latency, increase idle temperatures, and may provide benefit to aida latency (I am not sure how it behaves on single ccd chips).

You should of had the c-states toggle already. If it wasn't under amd cbs it should have been under cpu options.


----------



## craxton

jomama22 said:


> c-states toggle already.


c states are there, but DF is not.
or wasnt its under this modded bios in another section as well as cstates being right below it.
im actually 200 pages back now or so and found quite a bit on it.
where pjvol posted it decreased his bandwidth 1000 or so with it off while on increased....

ive gotta good IMC but i be dammed if my chip is horrible at overclocking (or running anywhere near stable)
with curve settings lol ill eventually get it tuned. (scores were impressive) with the curve i was running in R23 and R20
way better than most ive seen here and other places....

still have yet to spot relaxed EDC throttling anywhere tho....
it was actually page 353 where he mentioned this, but none the less ive been back to 201 an noticed
i somehow was going forward...so i split some windows into fours
saved a few more things leaving DF back to how it was for now.

(EDIT)

no change on my aida runs (without killing tasks or running in safe mode other than latency being higher)
copy, write, L1 round the same, and L2 and L3 speeds are actually quite a bit higher....?
as well as idle temps (with chrome running NOW WITH 23 tabs open and 4 windows while
a few other programs go at it (idle temps while room is 80c temps are 34c range) usually idle temps alone without
anything running its 30-46c depending....

Another edit*
it would seem that the main page
Being set to auto
Override what I had set other places...
WHY !
ARE THERE FOUR PLACES to control each setting..

(also i know DF-Cstates are the same thing...idk *** i was writting at that moment...as stated
to pj im not knowladged a most of you fellas are. and not understanding how im free from WHEA 19 
as others are flooded to where others are whea 18 free to where im well 1 a day with anything over 20 curve 
without offset 6xx voltage to core. 

id trade 3800mhz stable to hit 25 CO stable


----------



## RonLazer

Sorry for the delay, had some real work to do, but I finished my testing, I'll explain my methodology a bit first though.

*OS:* Windows 20H2 x64. It's my Bench OS so it's quite lightweight. I used @ManniX-ITA High-Performance Power plan.
*CPU:* 5600X [email protected] SET (LLC 1, droops to 1.2V) - SMT enabled.
*BIOS:* Spread Spectrum: disabled, Global C-States: enabled, PLL/1P8 Voltage locked to 2V, DFE/FFE training enabled.
*Memory:* See Zentimings in screenshot, had to adjust the DRAM and SOC voltages as I increased frequency.
*Benchmark:* Linpack Extreme 1.1.5, with the standard 3Gb test run 5 times.








*Why Linpack?*
It's as close to a "real-world" memory test as any benchmark gets, it will hammer the memory controller AND the CPU so the CCD portion of the infinity-fabric gets hot, uses fairly representative memory in it's "Standard" benchmark (3Gb of heavy IO is about typical for most games/computational-software) and is multi-threaded. The problem with Aida64 bandwidth and latency tests is they put absolutely zero strain on the memory controller, Geekbench is too short and too synthetic, and y-cruncher is a fair substitute but is far heavier than any real-world use-case and so only really useful for scoring HWBot points or really proving a point about stability.

*Why a static Overclock?*
It stops thermal variation affecting PBO, and allows comparison across different silicon-quality CPUs. Linpack is a very heavy memory benchmark, but still mostly scales with CPU and so without locking the CPU core ratio we'd just be comparing who has the best-binned 5600X. It also isolates the impact of higher SOC power pulling from the PBO power/current budget.

*Why GearDownMode?*
This means we're not fiddling with CAD setups etc. to stabilize our respective overclocks - which will impact performance. Feel free to adjust drive-strengths/ProcODT/RTTs to match your boards/dimms impedances, they won't dramatically affect the results. I can't even run CR 1T at 3800 with my 4x8gb kit, and Linpack doesn't particularly care about latency in isolation anyway.

*What about the SOC-derived voltages?*
Feel free to tune SOC/CCD/IOD/VDDP/PLL to match your CPU, I just didn't want to get bogged down in fine-tuning these to squeeze out the last few % when the goal is to show and compare qualitative trends. I just used ballpark values I know have worked in the past. The timings are not very tight at all, because I didn't want this to be a comparison of memory controllers, but instead of the infinity fabric link itself.

As both the memory/CPU overclock are quite mild, in theory anyone can try and replicate this, including those with 5900X or 5950X's by disabling the 2nd CCD and limiting the number of active cores in the BIOS.

Here is the full graph from 1800MHz to 2033MHz:








The drop-off is obviously distorting the scale so let's remove 2033MHz:








Not quite sure what happened at 1933MHz, it even failed to POST a few times so I think I have a weak "FCLK hole" at that frequency on my CPU. The overall trend seems to basically show what I claimed initially - that FCLK equalization mechanism stops functioning properly after 1900MHz. The actual memory performance under load is barely increasing beyond 1900MHz, despite the fact that the timings are constant so we should see a rise in throughput solely on the memory side, the infinity fabric link is clearly bottlenecking the memory performance. As far as I've been able to tell, speeds over 1900MHz are basically just for show, or very very light workloads. I've observed this same behavior in multiple benchmarks before, this is the first time I've properly collected the data on it.

Here is my screenshot for the 2033MHz run:








You can literally see the performance dropping off as the CPU gets further into the benchmark, and the data-fabric and IOD get hotter, and hence less stable. This is why brief "bursty" benchmarks like Aida64 are insufficient, they don't actually push the CPU at all so instability doesn't kick in hard enough to manifest as performance degradation.

I'd like to see some people try and replicate these tests (should be pretty easy for anyone with 4 sticks of B-die) and a Zen3 CPU. This will allow us to compare and see if the performance stagnation kicks in at 1933MHz for everyone, and if the sharp drop-off at 2033MHz is also a universal feature. A few tips to improve reproducibility:

1. Start with a single 2gb run first to "wake up the CPU". If you don't then the first loop will be slower than the others. I assume this is due to scheduler behaviour, could also be core parking.
2. Close all background processes, ideally run in Windows 10 Diagnostic Mode.
3. If a run is anomalously low, reboot and try again. Memory training is super variable and boot-to-boot variation can sometimes be larger than changes in timings/frequency/voltages.

*Working Conclusion?*
I'd like to see more results, but I strongly suspect the optimal fclk frequency for pragmatic daily usage really is 1900Mhz and no amount of fiddling is going to fix this. If there was a magic setting in the CBS that fixed all the issues and unlocked the full potential of higher clocked memory with no risks or downsides - why haven't AMD just turned it on for us?

Also if there was, someone would have found it by now. I've tried almost all of them, some of them help a little, nothing actually changes this overall trend. You can definitely hack together a BIOS config that will spit out excitingly low latency numbers, but as soon as your CPU gets hot it will probably crumple, and even if it doesn't - are the gains really worth the extra strain you're putting on your CPU with the higher SOC voltages? Probably not.


----------



## RonLazer

@Veii I'm interested in doing some scientific testing on the effect of the tCKE + RTT combinations you've found through your experiments. Can you summarise the hypothesis involved, I've not been following this thread for that long so I'm not 100% clear on what exact role they serve or how one would know if they're "working"?


----------



## hazium233

jomama22 said:


> and may provide benefit to aida latency (I am not sure how it behaves on single ccd chips).


I only tried Global C-State - Disabled once to see if it would help WHEA 19 - Source 0 (helped slow a little), but it seemed to make latency a lot worse for my 5600X. But this was in WHEA hell, so I don't know how valid.



hazium233 said:


> to make sure the 3600C16 2x8GB set I ended up with at least are functional so farewell dual rank E for the time being.


It's a good thing I jinxed myself with this post, one of the dimms I can't get to even load into Windows at 3200C16. The other one seemed to do XMP (more or less, since I tested it second I didn't care that tRC did not get loaded).


----------



## craxton

Veii said:


> God job
> Was playing with the X570 Tomahawk Wifi (.150) , around 3 days ago
> Haven't tried higher FCLK, the 5900X user awaits new rams
> 
> Jumping back'n'forth between 4000C16-16-16 sets @ 1.4 or 3600C14-15-15 @ 1.45 (32gb)
> First one appears superior, but the 2nd TeamGroup set is known to have it easier with CL12-12
> Anywho, thank you for the continuous effort on the bios mods
> 
> @craxton this VDDP here is starting from 1050mV higher - still not the one we are looking for
> I do think that MSI mistook it ~ it's more closer to what ASUS specifies as Standby VDDP voltage
> Sadly ASUS didn't think that it can drop to 800mV and put a 900mV lock on it.
> You mostly are fine with what runs. Only if it's buggy, 930mV or more would be set. It should be fixed at 900mV on the newer bioses. One could expect it at this point of time
> 
> For MSI users, save this G-Drive link
> MSI - Google Drive
> And do you maybe want to give MSI Dragon-Power , AMD version a shot ?
> Dragon Ball, even the last 3 versions do not work on AM4 ~ but MemTweakIt & Dragon Ball do work across multiple Z490 & Z590 Boards, even if they are not Asus or MSI branded
> 
> Maybe we'll get a Dragon-Ball utility for AM4 someday upon request ~ but try how much Dragon-Power on AM4 can read out
> Maaybe you get lucky with access to some more voltages
> 
> EDIT:
> I forgot to add,
> AMIFlash (AfuWin) does finally allow flashing bios-mods
> I know it's a win utility and technically more unsafe - but not licensed bioses pass through with it (temporary replacement for flashrom)
> ~ and as it flashes in blobs, i feel it a bit more safe, than bios's own CRC checking utilities


version 1.0.0.05 can read CPU_VDDP but as for changing it im unsure...
as for the later version listed, it can not read it...unless im blind but im 99% sure its not there...

(EDIT) after trying version 1.0.0.05 CPU_VDDP idk HOW MANY TIMES
it would pop up in hwinfo for whatever reason under WHEA errors
not as an error just as its labeled. 

but was .2xx while anything under 1.05xx was applied however, while 1.0500 
(default) was applied it would stop showing and be greyed out with the last value it showed while 
still being visible.

none the less, ryzen master showed it wasnt changing the value. to which.
was set already (as you stated 900mv well close to it with minor droop)
the tool would raise SOC voltage but couldnt lower it back to where it was previously. 
didnt try the updated version....


----------



## jomama22

RonLazer said:


> Sorry for the delay, had some real work to do, but I finished my testing, I'll explain my methodology a bit first though.
> 
> *OS:* Windows 20H2 x64. It's my Bench OS so it's quite lightweight. I used @ManniX-ITA High-Performance Power plan.
> *CPU:* 5600X [email protected] SET (LLC 1, droops to 1.2V) - SMT enabled.
> *BIOS:* Spread Spectrum: disabled, Global C-States: enabled, PLL/1P8 Voltage locked to 2V, DFE/FFE training enabled.
> *Memory:* See Zentimings in screenshot, had to adjust the DRAM and SOC voltages as I increased frequency.
> *Benchmark:* Linpack Extreme 1.1.5, with the standard 3Gb test run 5 times.
> View attachment 2512597
> 
> *Why Linpack?*
> It's as close to a "real-world" memory test as any benchmark gets, it will hammer the memory controller AND the CPU so the CCD portion of the infinity-fabric gets hot, uses fairly representative memory in it's "Standard" benchmark (3Gb of heavy IO is about typical for most games/computational-software) and is multi-threaded. The problem with Aida64 bandwidth and latency tests is they put absolutely zero strain on the memory controller, Geekbench is too short and too synthetic, and y-cruncher is a fair substitute but is far heavier than any real-world use-case and so only really useful for scoring HWBot points or really proving a point about stability.
> 
> *Why a static Overclock?*
> It stops thermal variation affecting PBO, and allows comparison across different silicon-quality CPUs. Linpack is a very heavy memory benchmark, but still mostly scales with CPU and so without locking the CPU core ratio we'd just be comparing who has the best-binned 5600X. It also isolates the impact of higher SOC power pulling from the PBO power/current budget.
> 
> *Why GearDownMode?*
> This means we're not fiddling with CAD setups etc. to stabilize our respective overclocks - which will impact performance. Feel free to adjust drive-strengths/ProcODT/RTTs to match your boards/dimms impedances, they won't dramatically affect the results. I can't even run CR 1T at 3800 with my 4x8gb kit, and Linpack doesn't particularly care about latency in isolation anyway.
> 
> *What about the SOC-derived voltages?*
> Feel free to tune SOC/CCD/IOD/VDDP/PLL to match your CPU, I just didn't want to get bogged down in fine-tuning these to squeeze out the last few % when the goal is to show and compare qualitative trends. I just used ballpark values I know have worked in the past. The timings are not very tight at all, because I didn't want this to be a comparison of memory controllers, but instead of the infinity fabric link itself.
> 
> As both the memory/CPU overclock are quite mild, in theory anyone can try and replicate this, including those with 5900X or 5950X's by disabling the 2nd CCD and limiting the number of active cores in the BIOS.
> 
> Here is the full graph from 1800MHz to 2033MHz:
> View attachment 2512596
> 
> The drop-off is obviously distorting the scale so let's remove 2033MHz:
> View attachment 2512598
> 
> Not quite sure what happened at 1933MHz, it even failed to POST a few times so I think I have a weak "FCLK hole" at that frequency on my CPU. The overall trend seems to basically show what I claimed initially - that FCLK equalization mechanism stops functioning properly after 1900MHz. The actual memory performance under load is barely increasing beyond 1900MHz, despite the fact that the timings are constant so we should see a rise in throughput solely on the memory side, the infinity fabric link is clearly bottlenecking the memory performance. As far as I've been able to tell, speeds over 1900MHz are basically just for show, or very very light workloads. I've observed this same behavior in multiple benchmarks before, this is the first time I've properly collected the data on it.
> 
> Here is my screenshot for the 2033MHz run:
> View attachment 2512599
> 
> You can literally see the performance dropping off as the CPU gets further into the benchmark, and the data-fabric and IOD get hotter, and hence less stable. This is why brief "bursty" benchmarks like Aida64 are insufficient, they don't actually push the CPU at all so instability doesn't kick in hard enough to manifest as performance degradation.
> 
> I'd like to see some people try and replicate these tests (should be pretty easy for anyone with 4 sticks of B-die) and a Zen3 CPU. This will allow us to compare and see if the performance stagnation kicks in at 1933MHz for everyone, and if the sharp drop-off at 2033MHz is also a universal feature. A few tips to improve reproducibility:
> 
> 1. Start with a single 2gb run first to "wake up the CPU". If you don't then the first loop will be slower than the others. I assume this is due to scheduler behaviour, could also be core parking.
> 2. Close all background processes, ideally run in Windows 10 Diagnostic Mode.
> 3. If a run is anomalously low, reboot and try again. Memory training is super variable and boot-to-boot variation can sometimes be larger than changes in timings/frequency/voltages.
> 
> *Working Conclusion?*
> I'd like to see more results, but I strongly suspect the optimal fclk frequency for pragmatic daily usage really is 1900Mhz and no amount of fiddling is going to fix this. If there was a magic setting in the CBS that fixed all the issues and unlocked the full potential of higher clocked memory with no risks or downsides - why haven't AMD just turned it on for us?
> 
> Also if there was, someone would have found it by now. I've tried almost all of them, some of them help a little, nothing actually changes this overall trend. You can definitely hack together a BIOS config that will spit out excitingly low latency numbers, but as soon as your CPU gets hot it will probably crumple, and even if it doesn't - are the gains really worth the extra strain you're putting on your CPU with the higher SOC voltages? Probably not.


I will throw this in there just as somthing to add to the conversation.

Here are sottr (shadow of the tomb raider) benchmarks I have thrown together comparing identical timings at 3800 and 4000 (still working out getting 4000 fully stable, 1 stupid error in 25 tm5 cycle). I will note, fclk 2000 is stable for me at 1.125v soc, so its possible I don't suffer nearly as much from soc heat (I also have a the 5950x on its own loop with 2x360 rads).
What we care about here are the 'cpu game's results.
3800 max:









4000:









The results are consistent interms of the range of scores they can achieve relative to their differences above and both are the max I have been able to achieve with either.

Now, they aren't some massive variances (1-3% or so) but there are tangible differences.

Only sharing this as a somewhat real world example of what differences may be achievable. Not saying what is worth it or not one way or another

The timings:


----------



## ManniX-ITA

@RonLazer

Very nice initiative!

But I can't reproduce your results.
Give a try to CLKREQ# to fix FCLK 2033.
Seems to be the same issue I have.
But it's weird that is hitting you with 6 cores, for me works almost fine till 12.

Did you use always the same SOC voltage?
Cause maybe that's why you don't see scaling up.
I need to set a specific VSOC going above FCLK 1900 or the gains are being eaten up.

Eg. FCLK 1900 at VSOC 1.16V 618 GFlops, FCLK 2000 at VSOC 1.2V 590 GFlops, 1.23V 630 GFlops, 1.3V 618 GFlops



RonLazer said:


> The actual memory performance under load is barely increasing beyond 1900MHz, despite the fact that the timings are constant so we should see a rise in throughput solely on the memory side, the infinity fabric link is clearly bottlenecking the memory performance. As far as I've been able to tell, speeds over 1900MHz are basically just for show, or very very light workloads. I've observed this same behavior in multiple benchmarks before, this is the first time I've properly collected the data on it.


I see scaling up till FCLK 2000 but maybe you need more cores to see it.
Running 3 cores the difference between 2000 and 2033 is 143.25 GFlops to 144 GFlops. 0.25 per core.
But using 12 cores goes from 486.7 to 491.8, starts to be noticeable. 0.425 per core.
As per the results above with 16 cores the gap gets wider, 12 GFlops. 0.75 per core.
Not sure Linpack is the best way to show the gain with higher FCLK; good to test for stability but not FCLK performances.
Something more latency oriented maybe.
Still the max theoretical gain is no more than 5%... you need something really tailored.



RonLazer said:


> 1. Start with a single 2gb run first to "wake up the CPU". If you don't then the first loop will be slower than the others. I assume this is due to scheduler behaviour, could also be core parking.


I don't see this behavior, never. The first run is always the faster one.
My power plan also doesn't use core parking.
I suspect something off with the settings.

Of course with 16 cores my runs gets slower and slower.
With only 3 cores are super steady 
But I've noticed during the tests that they also fall down due to LLC and PWM settings.
Unfortunately anything than Auto LLC on MSI has detrimental effects.
The next runs in the benchmarks can be stabilized using high PWM switching frequency and OVP/OCP to 400mV and Enhanced in MSI BIOS.
These settings are exposed also in the Gigabyte BIOS but I think they are not in the Dark Hero.
Still an indication where to look to fix consistency.

@jomama22

Thanks amazing SOTR results!
I'm very far from that but I can replicate the same FCLK results as well.
Still 60% GPU bound at 800x600


----------



## PJVol

@RonLazer
Ok, CPU [email protected] 
vdd18/vsoc: @2000 2.0/1.15, @2033 2.05/1.15 @2066 2.1/1.175 @2100 2.1/1.200
vddp 0.93, ccd 1.000 iod 1.080

all results (except PBO) : 263-264Gflops
a couple results with PBO
3800 CL16 w/tighter timings and vdd/vsoc - auto/1.1
----------------------------------------------------------------------------
*Conclusion )) *
Basically, no scaling at all within a 1900-2100 FCLK range.
I suspect your "2033 drop-off" is due to not enough pll. If I keep vdd18 at 2.0 going above 2000, it may drop similarly (or may not, depending on voltage training).


----------



## Asutz

runnin 3600c14 
are the numbers correct more or less?


----------



## MadGoat

1s1mple said:


> Any settings i can adjust for better timings etc?
> 
> Hynix C die kit
> 
> I tried 3800 no luck with 1.4v, cant post.
> 
> View attachment 2512579


Looks good! It seems that Micron E-die and Hynix C-die respond similarly.


----------



## domdtxdissar

RonLazer said:


> Sorry for the delay, had some real work to do, but I finished my testing, I'll explain my methodology a bit first though.
> 
> *OS:* Windows 20H2 x64. It's my Bench OS so it's quite lightweight. I used @ManniX-ITA High-Performance Power plan.
> *CPU:* 5600X [email protected] SET (LLC 1, droops to 1.2V) - SMT enabled.
> *BIOS:* Spread Spectrum: disabled, Global C-States: enabled, PLL/1P8 Voltage locked to 2V, DFE/FFE training enabled.
> *Memory:* See Zentimings in screenshot, had to adjust the DRAM and SOC voltages as I increased frequency.
> *Benchmark:* Linpack Extreme 1.1.5, with the standard 3Gb test run 5 times.
> View attachment 2512597
> 
> *Why Linpack?*
> It's as close to a "real-world" memory test as any benchmark gets, it will hammer the memory controller AND the CPU so the CCD portion of the infinity-fabric gets hot, uses fairly representative memory in it's "Standard" benchmark (3Gb of heavy IO is about typical for most games/computational-software) and is multi-threaded. The problem with Aida64 bandwidth and latency tests is they put absolutely zero strain on the memory controller, Geekbench is too short and too synthetic, and y-cruncher is a fair substitute but is far heavier than any real-world use-case and so only really useful for scoring HWBot points or really proving a point about stability.
> 
> *Why a static Overclock?*
> It stops thermal variation affecting PBO, and allows comparison across different silicon-quality CPUs. Linpack is a very heavy memory benchmark, but still mostly scales with CPU and so without locking the CPU core ratio we'd just be comparing who has the best-binned 5600X. It also isolates the impact of higher SOC power pulling from the PBO power/current budget.
> 
> *Why GearDownMode?*
> This means we're not fiddling with CAD setups etc. to stabilize our respective overclocks - which will impact performance. Feel free to adjust drive-strengths/ProcODT/RTTs to match your boards/dimms impedances, they won't dramatically affect the results. I can't even run CR 1T at 3800 with my 4x8gb kit, and Linpack doesn't particularly care about latency in isolation anyway.
> 
> *What about the SOC-derived voltages?*
> Feel free to tune SOC/CCD/IOD/VDDP/PLL to match your CPU, I just didn't want to get bogged down in fine-tuning these to squeeze out the last few % when the goal is to show and compare qualitative trends. I just used ballpark values I know have worked in the past. The timings are not very tight at all, because I didn't want this to be a comparison of memory controllers, but instead of the infinity fabric link itself.
> 
> As both the memory/CPU overclock are quite mild, in theory anyone can try and replicate this, including those with 5900X or 5950X's by disabling the 2nd CCD and limiting the number of active cores in the BIOS.
> 
> Here is the full graph from 1800MHz to 2033MHz:
> View attachment 2512596
> 
> The drop-off is obviously distorting the scale so let's remove 2033MHz:
> View attachment 2512598
> 
> Not quite sure what happened at 1933MHz, it even failed to POST a few times so I think I have a weak "FCLK hole" at that frequency on my CPU. The overall trend seems to basically show what I claimed initially - that FCLK equalization mechanism stops functioning properly after 1900MHz. The actual memory performance under load is barely increasing beyond 1900MHz, despite the fact that the timings are constant so we should see a rise in throughput solely on the memory side, the infinity fabric link is clearly bottlenecking the memory performance. As far as I've been able to tell, speeds over 1900MHz are basically just for show, or very very light workloads. I've observed this same behavior in multiple benchmarks before, this is the first time I've properly collected the data on it.
> 
> Here is my screenshot for the 2033MHz run:
> View attachment 2512599
> 
> You can literally see the performance dropping off as the CPU gets further into the benchmark, and the data-fabric and IOD get hotter, and hence less stable. This is why brief "bursty" benchmarks like Aida64 are insufficient, they don't actually push the CPU at all so instability doesn't kick in hard enough to manifest as performance degradation.
> 
> I'd like to see some people try and replicate these tests (should be pretty easy for anyone with 4 sticks of B-die) and a Zen3 CPU. This will allow us to compare and see if the performance stagnation kicks in at 1933MHz for everyone, and if the sharp drop-off at 2033MHz is also a universal feature. A few tips to improve reproducibility:
> 
> 1. Start with a single 2gb run first to "wake up the CPU". If you don't then the first loop will be slower than the others. I assume this is due to scheduler behaviour, could also be core parking.
> 2. Close all background processes, ideally run in Windows 10 Diagnostic Mode.
> 3. If a run is anomalously low, reboot and try again. Memory training is super variable and boot-to-boot variation can sometimes be larger than changes in timings/frequency/voltages.
> 
> *Working Conclusion?*
> I'd like to see more results, but I strongly suspect the optimal fclk frequency for pragmatic daily usage really is 1900Mhz and no amount of fiddling is going to fix this. If there was a magic setting in the CBS that fixed all the issues and unlocked the full potential of higher clocked memory with no risks or downsides - why haven't AMD just turned it on for us?
> 
> Also if there was, someone would have found it by now. I've tried almost all of them, some of them help a little, nothing actually changes this overall trend. You can definitely hack together a BIOS config that will spit out excitingly low latency numbers, but as soon as your CPU gets hot it will probably crumple, and even if it doesn't - are the gains really worth the extra strain you're putting on your CPU with the higher SOC voltages? Probably not.


5950x @ static 4.5ghz
1900:3800 CL14 flat T1 GDM-off
4*8GB memory
Bloaty Windows

Getting pretty stable 633 Gflops before i opened hwinfo
632 flops after when running hwinfo at the same time.









stable 631 @ 1866:3733








Nevermind the vcore/temp/watt as this was just a quick and easy testrun in CTR. (can run with lower vcore for this speed)

Can only boot 1933:3866 @ 880mv/880mv/1050mv/1125mv for the IO die, but then i also need higher procODT which mean i cant run with T1 GDM-off. But it dont matter since i get much worse performance even in Aida64 with those settings...

@ *jomama22*
Welcome in the 300 CPU game SotTR club


----------



## PJVol

Asutz said:


> runnin 3600c14
> are the numbers correct more or less?


It would make sense when "gpu bound" is 0% or close to. Otherwise, you may not see the effect the RAM performance has.


----------



## Asutz

720p lowest settings, rx 580 is ok for gaming but still very weak, oc*ed a bit but not rly helpful,


----------



## MadGoat

domdtxdissar said:


> 5950x @ static 4.5ghz
> 1900:3800 CL14 flat T1
> 4*8GB memory
> Bloaty Windows
> 
> Getting pretty stable 633 Gflops before i opened hwinfo
> 632 flops after when running hwinfo at the same time.
> View attachment 2512653
> 
> 
> stable 631 @ 1866:3733
> View attachment 2512656
> 
> Nevermind the vcore/temp/watt as this was just a quick and easy testrun in CTR. (can run with lower vcore for this speed)
> 
> @ *jomama22*
> Welcome in the 300 CPU game SotTR club


Those timings must do wonders


----------



## KedarWolf

I'm sending the 16-16-16-36 4000MHz G.Skill Neo RAM back, it performs worse than my CL16 3600 Neo.

Newegg will honour the refund because it won't even boot at XMP settings and will with higher voltages but I get tons of WHEA errors and they are made for our platform.

That's not why I'm sending it back though, it needs more voltage to be stable at the same timings at 3800. I knew I'd likely still get WHEA errors at 4000.

Someone on overclock.net got tons of flack from another member here for saying the FLCK WHEA issues are CPU dependent but I really think they are too.

Some CPUs will do 4000 no WHEA errors, but they are few and far between. Some CPUs won't even boot at 3800 but a new CPU has fixed that for some.

And I have a two DIMM Unify-X motherboard, so if 4000 wasn't CPU dependent, I'd likely have no issues with it.

My 5950x CPU does really great with the CO Curve though. 150 Boost, Scaler 6, 17-17-21-21-23-23-25-25-25-25-30-30-30-30-30-30 which isn't half bad.

Core Cycler, TM5 and Linpack XTreme stable as well.


----------



## Veii

RonLazer said:


> @Veii I'm interested in doing some scientific testing on the effect of the tCKE + RTT combinations you've found through your experiments.
> how one would know if they're "working"?


I'm not sure, i understand your request at all
"working" ? 🤯

RTTs are always active, the changes are also always permanent and differ by capacity, voltage and memory PCB
I can not understand the "working" part.

RTTs will also change by procODT influence
And procODT changes up up SOC, ClkDrvStr, PCB quality (mainboard) , and target FCLK ~ oh also VDIMM

VDIMM influences RTT, ClkDrvStr, procODT.
VDIMM doesn't degrade much the S/N ration and signal integrity, but procODT does
Different CAD_BUS values change the magnitude of degradation ~ impedances are always multipliers, even when termination impedances are working as resistance and not pure impedance (like the ohm's law)

tCKE "working" ?
Does it need a scientific method to proof obvious behaviour ?
Change it to something random - jump from 3 to 11 to 32 and you will see a change. It also "is working"
According to MemTweakIt , it does influence AggressivePowerdown , which is an own thing aside from the normal PowerDownMode
(but this technical term, came far later after seeing any change)

If you ment, "explain it in scientific manner, to reproduce in scientific tests"
Then i'm sorry, but i'm the wrong person for such. I don't read manuals, it's learning by doing
At the very end i might take a look when i'm stuck on something or to manifest experience ~ but sorry , that's not how i do "anything". In Tech and in Life
Theories remain theories ~ practical observation is what i watch. I can not help you except link you to technical paper threads.
Then if these papers still apply with the current IMC firmware, is another theory on it's own 

If you mean something completely different, then please let me know
But on both potential understandings ~ i still don't understand what you ask me to do 🙇‍♂️
Of course they are functional and do something, else there would be no variance nevertheless what you set

EDIT:
If you maybe mean specifically the combination with tCKE and RTT. Purely the patterns
Then maybe i can give you a list
But this is matching 3 different states ~ with SETUP times we end up to 4.
I believe it's possible to make a calculator based on the technical delay information out there for both tCKE and SETUP timings range
But it's outside of what i usually do.
It surely makes sense somehow on the technical term ~ but i can't know.
I observe if they work together , all 3 or 4 ~ and figure out what breaks of the 4 and why. But not "why it's offsync" in the technical term.

Probably takes me at least 5x as long that way, bruteforcing potential combinations, but that's how i work
Efficiency increased, soo "with success" i guess 
But i don't know how to teach "efficient brute-forcing" to anybody ~ except give results i've tested on couple of systems & the OCN log here
~ Maybe you mean this part of the question 🤔


----------



## ManniX-ITA

jomama22 said:


> Just so you know, you can't compare those last two aida shots you posted in the spoiler. Your first one is using only 8 cores with pbo vs all 16 with pbo. You cant do this and expect to get any comparable results.


You got it wrong, I just took some random AIDA bench to check there was no impact in memory performances with CLKREQ# enabled.
Casually went down to 50.2ns at 4133MHz but couldn't go lower, it was just for the personal pleasure to see a result below 50 



jomama22 said:


> 1ccd and 2ccd setups act opposite each other interms of aida latency. 1ccd benefits from pbo and will lower aida latency the higher the fmax will go. It also suffers when using a static allcore oc. 2ccd setups are the opposite, with allcore OCs beating any pbo results by about .7-.8ns.


Yes I noticed the gap with the 1CCD but I could not see that big gap between static OC and PBO.
Maybe cause I can't go that much high with static OC.
Limiting PBO to what I can achieve with static OC just brings a 0.1-0.2ns gain, below the margin of error.


----------



## RonLazer

Veii said:


> I'm not sure, i understand your request at all
> "working" ? 🤯
> 
> RTTs are always active, the changes are also always permanent and differ by capacity, voltage and memory PCB
> I can not understand the "working" part.
> 
> RTTs will also change by procODT influence
> And procODT changes up up SOC, ClkDrvStr, PCB quality (mainboard) , and target FCLK ~ oh also VDIMM
> 
> VDIMM influences RTT, ClkDrvStr, procODT.
> VDIMM doesn't degrade much the S/N ration and signal integrity, but procODT does
> Different CAD_BUS values change the magnitude of degradation ~ impedances are always multipliers, even when termination impedances are working as resistance and not pure impedance (like the ohm's law)
> 
> tCKE "working" ?
> Does it need a scientific method to proof obvious behaviour ?
> Change it to something random - jump from 3 to 11 to 32 and you will see a change. It also "is working"
> According to MemTweakIt , it does influence AggressivePowerdown , which is an own thing aside from the normal PowerDownMode
> (but this technical term, came far later after seeing any change)
> 
> If you ment, "explain it in scientific manner, to reproduce in scientific tests"
> Then i'm sorry, but i'm the wrong person for such. I don't read manuals, it's learning by doing
> At the very end i might take a look when i'm stuck on something or to manifest experience ~ but sorry , that's not how i do "anything". In Tech and in Life
> Theories remain theories ~ practical observation is what i watch. I can not help you except link you to technical paper threads.
> Then if these papers still apply with the current IMC firmware, is another theory on it's own
> 
> If you mean something completely different, then please let me know
> But on both potential understandings ~ i still don't understand what you ask me to do 🙇‍♂️
> Of course they are functional and do something, else there would be no variance nevertheless what you set
> 
> EDIT:
> If you maybe mean specifically the combination with tCKE and RTT. Purely the patterns
> Then maybe i can give you a list
> But this is matching 3 different states ~ with SETUP times we end up to 4.
> I believe it's possible to make a calculator based on the technical delay information out there for both tCKE and SETUP timings range
> But it's outside of what i usually do.
> It surely makes sense somehow on the technical term ~ but i can't know.
> I observe if they work together , all 3 or 4 ~ and figure out what breaks of the 4 and why. But not "why it's offsync" in the technical term.
> 
> Probably takes me at least 5x as long that way, bruteforcing potential combinations, but that's how i work
> Efficiency increased, soo "with success" i guess
> But i don't know how to teach "efficient brute-forcing" to anybody ~ except give results i've tested on couple of systems & the OCN log here
> ~ Maybe you mean this part of the question 🤔


Sorry I wasn't very clear. What I mean is when you suggest people use specific combinations of tCKE, CAD setups, and RTTs - what is it supposed to achieve? Better stability? Lower voltage requirements? Lower latency? Higher bandwidth? 

If you could give me the combinations you've found already then I can try doing A/B comparisons on the performance criteria you're aiming for and try and learn more about the behaviour and role of each parameter. I've tried using a battery of tests for tCKE alone in the past and not seen any change, but that was with 0 setups and 0/0/5 on RTTs. 

For example I think that at 2000MHz CR 2T you suggest people use tCKE=11, 4-4-18 setups and 6/3/6 RTTs, is this for 2xSR, 2xDR, 4xSR or will it work on all of them? What differences should I be looking for compared to tCKE=1, 0-0-0 setups, RTTs on 0/0/5?


----------



## mongoled

craxton said:


> well, each time mine has crashed its been core 6 so....now i know whats the issue. THANK YOU
> well 3 and 6 as core cycler just failed on 3 and 6 both.
> 
> (would it be apcid ? its always been 6 but it would seem one has 11)
> View attachment 2512354
> 
> 
> View attachment 2512353


Your welcome, glad it was helpful





jomama22 said:


> Wait, if I'm reading this right, 3800/1900 produced the best results for you yeah?


Yup, best results using Linpack is at 3800/1900



PJVol said:


> It may be platform specific, but I found that gb3 has a couple of tests that show biggest performance impact on high-fclk config for me. Can you look into gb3 results as well, when comparing?
> They are in the last tab - "memory performance", these *Stream* *Add Multicore* and *Stream Triad* used to drop noticeably at 2000+.
> 
> View attachment 2512449
> 
> 
> One more quick test is aida's FP64 Ray-Trace. On a 24/7 [email protected] config - it reaches 7800-7900, and still can't beat it with 1933+.


Hopefully will have a look at this request tomorrow



Veii said:


> "Anybody" here~
> 1.25v is preapplied after 2100 FCLK, around 1.1875-1.2 is required for it
> Up to 1.3v is usable, but thr amount it cuts into the powerbudget, makes it more and more a bad decision
> 
> It might have been even you who pushed me to redo my voltages
> Been running before 1.26ish
> But that was with lower IOD
> 
> I figured after time, that it masks issues
> Even masks low procODT
> Overall, welcome to my world of struggle at and past 2033, you and @ManniX-ITA
> I think you can orient to everyrhing i posted 4 months ago
> Including the AMD Maximum Voltage thread
> 
> Everything including high 1.8 VDD issues should apply to you ~ up to 1.82v is fine, someday 1.83v depends


Thanks for the feedback, not really made progress from when I asked this post, but not because I have not been able to reduce the vSOC voltage, biggest "obstacle" is finding that using identical settings with identical BIOS act differently having flashed to a different version then flashing back.

Throws a spanner in the works as things you believed you had "worked out" are thrown out the window!

I am seeing this not only in stability testing but also in power consumption numbers.

Going to reflash with a few different methods to see if things start behaving again.

Regarding vSOC being over 1.3v, I managed to reduce it considerably and am avoiding the USB "getting stuck" issue and games locking up but with audio playing @ 2066 FCLK, but I dint really know the reasons why!

And tomorrow will add my Linpack Extreme results, they pretty much mirror @PJVol results, unsure why @RonLazer results fall off a cliff after 2000 mhz.

I dont see that at all, quick summary from the top of my head

1867 mhz - 266 gflops
1900 mhz - 267 gflops
1933 mhz - 262 gflops
2033 mhz - 263 gflops
2066 mhz - 263 gflops

Most I could get 2066 mhz to was 264/265 gflops, had to raise vDDG IOD and vDDP slightly, raising them too much brought the results down, also PLL voltage lower than 1.82v gives me worse results, increasing up to 2v did not give me any increase in score so I leave it on AUTO which gives me 1.84/5 volts according to HWInfo64.


----------



## ManniX-ITA

mongoled said:


> Most I could get 2066 mhz to was 264/265 gflops, had to raise vDDG IOD and vDDP slightly, raising them too much brought the results down, also PLL voltage lower than 1.82v gives me worse results, increasing up to 2v did not give me any increase in score so I leave it on AUTO which gives me 1.84/5 volts according to HWInfo64.


Linpack is good to test CPU performances and voltages but not much for the FCLK specifically.
You can see when something is wrong but not necessarily the scaling up.

Still for me the best is CPU-z to really see the FCLK gain.
Compared 1:1 to a lower FCLK there's always an improvement.
There's a catch of course.
Like Linpack, it's a CPU test; below 12 cores/threads you will not see any gain.
There's more than enough bandwidth at FCLK 1900 already.
The few GB/s more in bandwidth and less ns in latency better they get lost in the margin of error.
Then with more threads you enter in thermal and EDC limits territory and it gets lost again.

But to me is pretty clear the most gain for FCLK higher than 1900 is for 5900/5950x.
Below gets very marginal unless it's a workload very memory dependent.
But even there with lower CAS and timings, except maybe AIDA, is very often better FCLK 1900.

Not sure at this point what could be used, so far only with SOTR benchmark I can see a linear scaling.
I'm looking if there's something else more suited for this specific task.
I'll check as suggested by @PJVol the Stream Triad and Add Multicore in GB3.
But GB3 is only 32bit as freeware so it's not a good general way to compare..


----------



## RonLazer

ManniX-ITA said:


> Linpack is good to test CPU performances and voltages but not much for the FCLK specifically.
> You can see when something is wrong but not necessarily the scaling up.
> 
> Still for me the best is CPU-z to really see the FCLK gain.
> Compared 1:1 to a lower FCLK there's always an improvement.
> There's a catch of course.
> Like Linpack, it's a CPU test; below 12 cores/threads you will not see any gain.
> There's more than enough bandwidth at FCLK 1900 already.
> The few GB/s more in bandwidth and less ns in latency better they get lost in the margin of error.
> Then with more threads you enter in thermal and EDC limits territory and it gets lost again.
> 
> But to me is pretty clear the most gain for FCLK higher than 1900 is for 5900/5950x.
> Below gets very marginal unless it's a workload very memory dependent.
> But even there with lower CAS and timings, except maybe AIDA, is very often better FCLK 1900.
> 
> Not sure at this point what could be used, so far only with SOTR benchmark I can see a linear scaling.
> I'm looking if there's something else more suited for this specific task.
> I'll check as suggested by @PJVol the Stream Triad and Add Multicore in GB3.
> But GB3 is only 32bit as freeware so it's not a good general way to compare..


I see scaling from FCLK up to 2000MHz with SuperPi 32M, but that's a single-threaded workload and very light so it doesn't really tax the GMI link. I disagree that Linpack is not a good FCLK test, if the entire point is to test "real world" performance of your overclock then it needs to be a combined CPU+Memory test, and if you experiment a bit with Linpack you'll see that it is _extremely _sensitive to memory performance. Geekbench3 is a nice all-round memory performance test for sure, but its so short that there isn't any time for instability to show up. If we could configure it to run each test multiple times then maybe it would work. 

I'm going to play around with XMem soon and try and code a more aggressive latency test that loads multiple cores and generates a "score", but I'm still not clear how we can get the CPU hot without giving it some real maths to solve, which brings us back to Linpack...

I wish I could upload some of my quantum simulation codes for you all, as they offer a really fantastic mixture of memory usage behaviour, but sadly they aren't free for general use.


----------



## mongoled

RonLazer said:


> I see scaling from FCLK up to 2000MHz with SuperPi 32M, but that's a single-threaded workload and very light so it doesn't really tax the GMI link. I disagree that Linpack is not a good FCLK test, if the entire point is to test "real world" performance of your overclock then it needs to be a combined CPU+Memory test, and if you experiment a bit with Linpack you'll see that it is _extremely _sensitive to memory performance. Geekbench3 is a nice all-round memory performance test for sure, but its so short that there isn't any time for instability to show up. If we could configure it to run each test multiple times then maybe it would work.
> 
> I'm going to play around with XMem soon and try and code a more aggressive latency test that loads multiple cores and generates a "score", but I'm still not clear how we can get the CPU hot without giving it some real maths to solve, which brings us back to Linpack...
> 
> I wish I could upload some of my quantum simulation codes for you all, as they offer a really fantastic mixture of memory usage behaviour, but sadly they aren't free for general use.


I see no difference in Linpack when using 3800/1900 flat 16s compared to flat 14s, both scored 266/267 gflops


----------



## Taraquin

1s1mple said:


> Any settings i can adjust for better timings etc?
> 
> Hynix C die kit
> 
> I tried 3800 no luck with 1.4v, cant post.
> 
> View attachment 2512579


Tried tRCDRD 18 or tRP 20 or 19? tWR 10 might work, tRTP 6 or 5 might work. Tried lower tRFC? If your ram is a good bin you might get to 450 or below. Set tRFC 2 at auto.


----------



## ManniX-ITA

RonLazer said:


> I see scaling from FCLK up to 2000MHz with SuperPi 32M, but that's a single-threaded workload and very light so it doesn't really tax the GMI link. I disagree that Linpack is not a good FCLK test, if the entire point is to test "real world" performance of your overclock then it needs to be a combined CPU+Memory test, and if you experiment a bit with Linpack you'll see that it is _extremely _sensitive to memory performance. Geekbench3 is a nice all-round memory performance test for sure, but its so short that there isn't any time for instability to show up. If we could configure it to run each test multiple times then maybe it would work.


You are testing with a 5600x, you probably can't even see the issue.
Whatever you put in (I've test with 1CCD and 6 cores) as voltages and settings you'll always get almost the same result.
If you test with a 5900x or a 5950x it's not that easy.

Linpack is extreme already by itself and that's the eXtreme version. It puts a lot of stress on the CPU, which we don't really need to measure the FCLK.
With 12 or 16 cores a small change in VDDG, VDDP, VSOC, LLC, PLL can change the GFlops by a minimum of 30 to 100.
It's too much CPU dependent; it's stressing the FPU which is not a good thing for this test.
Yes it's memory dependent but much more on latency than bandwidth; CL14 at 3600 can be faster than CL16 at 4000.

Using 16 cores at 4.35 GHz static OC my CPU goes over 100c. It's good as a torture test, not as a speed benchmark for the FCLK.
With PBO is limiting to 90c but then it's throttling already and the FCLK benefit is masked by whatever PBO decides to do.
Ideally should be something with much less math, that puts much less strain on the CPU but that can gain advantage by first the memory bandwidth and second the latency.
The Standard test is not enough to measure the FCLK, it just can't use enough available bandwidth with 16 cores.
For me it's topping around 608 GFlops at FCLK 1900 and doesn't scale up going higher.
The Extreme test is the only one that can show, at least till FCLK 2000, the gain but it's already too extreme at that point.


----------



## 1s1mple

Taraquin said:


> Tried tRCDRD 18 or tRP 20 or 19? tWR 10 might work, tRTP 6 or 5 might work. Tried lower tRFC? If your ram is a good bin you might get to 450 or below. Set tRFC 2 at auto.


I have not, i use these settings (Minus the termination Block and CAD) that it gave me in the DRAM Calculator.


----------



## Insidious Supra

4x8gb cl16/3600 kit. This is bascially auto/default for my hynix CJR @ 3800. I can run 3933 with different settings, but have a hard time keeping the sticks cool enough. I've tried tightening these to no avail. Will have a new set of 4x8gb cl19 4400 b-die this week


----------



## Taraquin

1s1mple said:


> I have not, i use these settings (Minus the termination Block and CAD) that it gave me in the DRAM Calculator.
> 
> View attachment 2512691


Try the tips I gave you, you can also try 35 tRAS and tRC=tRAS+tRP.


----------



## domdtxdissar

So have been testing some more with different core amounts in Linpack Extreme 1.1.5 if anyone want to compare settings.

5950x @ static 4.5ghz
1900:3800 CL14 flat T1 GDM-off
4*8GB memory
Bloaty Windows

6 cores = stable 266 Gflops









8 cores = stable 349 Gflops









12 cores = around 500 Gflops "semi-stable", maybe because data is jumping in L3 cache between the CCD's (?)









16 cores = stable 634 Gflops









Did also a 16 cores extended 8GB run with HWinfo open while running to check temp etc (~1.188v vcore under load)









Not sure if these are good or bad scores, but they seem stable atleast


----------



## 1s1mple

Taraquin said:


> Try the tips I gave you, you can also try 35 tRAS and tRC=tRAS+tRP.


Thanks for the quick replies.

Do I have to try the settings one by one?
Eg: tRCDRD 18 then play with TRP etc etc


----------



## craxton

so, the strangest thing...

maybe i didnt set something quite right, but how ever
OCCT core cycler passes with extreme 

am i suppose to run it 1 core 1 hour???? 
unsure if its configured correctly considering core cycler fails on 1 core now
usually 3rd iteration (auto) allowing all FFT sizes to run....

so can someone tell me what the correct configuration is:


----------



## craxton

KedarWolf said:


> Some CPUs will do 4000 no WHEA errors, but they are few and far between


im one of those lucky ones that can run (any FCLK) without WHEA 
but its a dud on overclocking the CPU unless im just that bad at it...even following guides left here
still core cycler screams at me on core 3-5 always..... unless i use positive curve???


----------



## 1s1mple

Taraquin said:


> Tried tRCDRD 18 or tRP 20 or 19? tWR 10 might work, tRTP 6 or 5 might work. Tried lower tRFC? If your ram is a good bin you might get to 450 or below. Set tRFC 2 at auto.


Tried TRCRD 18, system booted. Ran testmem5 got errors with 5 mins.

Tried lowering the TRFC to 450, system wouldn’t boot.

Tried both settings with 1.37v and SOC 1.1v


----------



## Taraquin

1s1mple said:


> Tried TRCRD 18, system booted. Ran testmem5 got errors with 5 mins.
> 
> Tried lowering the TRFC to 450, system wouldn’t boot.
> 
> Tried both settings with 1.37v and SOC 1.1v


Try them one by one, tWR 10, tRTP 6/5 and tRP 20/19 is probably easiest to lower. Try tRFC 480, if that works, 470 etc.


----------



## craxton

1s1mple said:


> Tried TRCRD 18, system booted. Ran testmem5 got errors with 5 mins.
> 
> Tried lowering the TRFC to 450, system wouldn’t boot.
> 
> Tried both settings with 1.37v and SOC 1.1v


one really shouldnt use dram calc anymore for 5000 series to gather timings
but if your going to use it, then you need thaiphoon burner 
download it if you havent,

then open, hit read, hit report, scroll all the way to the bottom,
then hit show delays in nano seconds, after that itll take you back to the top
then hit export (complete HTML report) save as whatever whereever youll be able to find
and reconize.

once thats done open dram calc, select board, speed, how many sticks, and memory type.
then hit compare, (reselect proper speed your wanting 3800 (max is 3866 for dram calc)
then hit calculate
should look something like (below) 
ignore mine saying 4000 and any red flavored text. 
(this is how to properly use dram calc) running it just by entering bdie, speed, board, stick, hitting calculate
never one time worked for me...


----------



## mongoled

craxton said:


> im one of those lucky ones that can run (any FCLK) without WHEA
> but its a dud on overclocking the CPU unless im just that bad at it...even following guides left here
> still core cycler screams at me on core 3-5 always..... unless i use positive curve???


I think you are looking far too deep into this. On my 6 core CPU both my best cores need positive offset for the settings I'm pushing. 

Obviously it's not binned as well as the 59xx but it's not effecting anything


----------



## craxton

mongoled said:


> I think you are looking far too deep into this. On my 6 core CPU both my best cores need positive offset for the settings I'm pushing.
> 
> Obviously it's not binned as well as the 59xx but it's not effecting anything


maybe i am, but my "best cores says windows, ryzen master both anyhow 
needs less curve than that of any other core in the system, perhaps fastest isnt best in some ways lol
none the less i think ive finally found the "spot" 
which is near nothing and needs offset in voltage "no telemetry scaling" 
just PBO, CO, like -17, and under 10 for the rest as 0 is my best overclocker...with some voltage offset.


----------



## ManniX-ITA

craxton said:


> still core cycler screams at me on core 3-5 always..... unless i use positive curve???



My Core 1 is the best core and needs a -10.
But it's much faster than the Core 0 at -18, bit slower than the 2nd best Core 4 at -20 and trillion times faster than Core 15 at -29.

So it's relative to the starting point, you need to check how fast really is and how it compares to the others.
Higher count has sadly a bit of negative impact on all-core performances, it's the weird AMD design for CO.
But on single core performance a positive core doesn't mean necessarily that is bad.
Especially on a 5600x with very low thermal constraints; for a 5900x and up can be more of a problem.

Check what is the actual speed of your cores.

Use BenchMate:





BenchMate







benchmate.org





Set affinity as below and launch CPU-z, measure every core (test only one thread per core).










Set the Threads to 1 as below:










And click on Bench CPU.
Close it once done, launch it with anew affinity every time.


----------



## mongoled

So........

For the runs I used CPU @4.5Ghz, CPU voltage was 1.275v with vDroop this is 1.2v, PLL on AUTO unless otherwise stated differently.

BIOS A85 Beta, last agesa (1.1.9.0) with boost override not gimped at 200 mhz

The first comparison that is relevant is 3800/1900 "tight" vs 3800/1900 "loose"

*3800/1900 "tight" - AVG: 267.5225*


Spoiler














*3800/1900 "loose" - AVG: 267.2641*


Spoiler















At least for my setup there is no difference between the two results

As memory timings do not play a role as per my setup all following results will use the same timings and relative voltages as show per ZenTimings unless otherwise stated.

*In summary - 1867 vs 1900 vs 1933 vs 2067

3733/1867 - AVG: 266.8223*


Spoiler














*3800/1900 - AVG: 267.2641*


Spoiler














*3866/1933 - AVG: 265.4789*


Spoiler














*4133/2067 - AVG: 262.2465*


Spoiler















Now onto comparative results at what I am aiming for as a 24/7 setup ...

*4133/2067 PBO + IOD/vDDP increase - AVG: 269.7470
CPU LLC: Level 6, CPU NB LLC: Level 2
PPT/TDC/EDC - 142/95/500
Boost Override: 375 mhz
Scaler: Auto*


Spoiler














*4133/2067 4.5Ghz - AVG: 262.2465*


Spoiler














*4133/2067 4.5Ghz IOD/vDDP increase - AVG: 264.7284*


Spoiler














*4133/2067 PLL @ 1.77v/1.80v (set/get) - AVG: 255.2571*


Spoiler















*Conclusion*

Per my setup memory timings do not effect the result.

As long as PLL voltage is not too low I didnt see any gains when increasing FCLK by increasing PLL.

To get back some of the "lost" performance when pushing past 2000 mhz FCLK i needed to raise IOD and vDDP, raising these two too much decreased performance in Y-Cruncher


----------



## ManniX-ITA

mongoled said:


> As memory timings do not play a role as per my setup all following results will use the same timings and relative voltages as show per ZenTimings unless otherwise stated.


You should be able to squeeze more performances with higher FCLK.
For me that VSOC is too low; I have to get at least 1.21V from Zentimings to have it run faster than FCLK 1900.
The sweet spot is 1.23V in BIOS.

For FCLK above 2000 more is needed, 1.25V in BIOS at least.
The PLL/1P8 sweet spot for me is set/get at 1.810/1.840.

Using PBO and 6 cores I can get 274 GFlops at 2000 and 2033.
If you can find a BIOS for the Unify with AMD PBS you can probably fix that small drop going over 1900 with CLKREQ# enabled.


----------



## mongoled

ManniX-ITA said:


> You should be able to squeeze more performances with higher FCLK.
> For me that VSOC is too low; I have to get at least 1.21V from Zentimings to have it run faster than FCLK 1900.
> The sweet spot is 1.23V in BIOS.
> 
> For FCLK above 2000 more is needed, 1.25V in BIOS at least.
> The PLL/1P8 sweet spot for me is set/get at 1.810/1.840.
> 
> Using PBO and 6 cores I can get 274 GFlops at 2000 and 2033.
> If you can find a BIOS for the Unify with AMD PBS you can probably fix that small drop going over 1900 with CLKREQ# enabled.


If you had noted my previous posts I am "fighting" with unpredictable vSOC level and resulting performance, bugs etc.

For Y-Cruncher using higher vSOC did not result in any further scaling, I also was able to play Doom Eternal for over an hour with no issues.

Will be re-putting the system through my stress test "suite" to see if I can finally tie down 4133/2067

Here is a AIDA64 ran with my PBO settings, performance is exactly where I would expect it to be ....









Forgot to say, this CPU sample cannot post at 1966, 2000 .......while 2033 cannot reliably post, hence the reason for aiming for 2067 ...

And...... I am confident that a better binned CPU such as 59xx series will have more performance at same clock speed as lesser binned CPU when using PBO even when you mimick same CPU/Thread count, what I am doing my best to say is that your increased performance in Linpack is not because of FCLK


----------



## ManniX-ITA

mongoled said:


> If you had noted my previous posts I am "fighting" with unpredictable vSOC level and resulting performance, bugs etc.


Following it of course 
So did you test with a bit higher VSOC and is worse?
I wonder if/how this is directly connected to the IOD quality or not.

About performances I mean Linpack.
Can see a linear consistency with Geekbench 5 MT results.
But if you go overboard with VSOC then Linpack and GB5 scores keeps going up but single core, GB5 SC, starts falling down.

Memory is more or less where it should be but I can do as well 50.4ns easy with a 2CCD, went down to 50.2ns the other day testing with CLKREQ#.
In theory you should be able to go even lower than me.
My profile is very similar, even a bit worse in theory.

Did you try the latest AGESA 1.2.0.3 modded BIOS that was shared here?
Maybe it has CLKREQ# unhid.
But then maybe you miss the unlocked boost clock and that's a problem...


----------



## mongoled

ManniX-ITA said:


> Following it of course
> So did you test with a bit higher VSOC and is worse?
> I wonder if/how this is directly connected to the IOD quality or not.
> 
> About performances I mean Linpack.
> Can see a linear consistency with Geekbench 5 MT results.
> But if you go overboard with VSOC then Linpack and GB5 scores keeps going up but single core, GB5 SC, starts falling down.
> 
> Memory is more or less where it should be but I can do as well 50.4ns easy with a 2CCD, went down to 50.2ns the other day testing with CLKREQ#.
> In theory you should be able to go even lower than me.
> My profile is very similar, even a bit worse in theory.
> 
> Did you try the latest AGESA 1.2.0.3 modded BIOS that was shared here?
> Maybe it has CLKREQ# unhid.
> But then maybe you miss the unlocked boost clock and that's a problem...


Thanks to @Eder work even A85 has this option, does not make a difference on my CPU sample when using it.

I tried the latest modded BIOS, only benefit I saw from this BIOS (have not tested extensively) was that this BIOS can post 1933 FCLK with no WHEA, but still have same memory holes and still "gimped" boost ovveride.

When using a "good" 5600X CPU sample with good cooling this is not a nice thing to have missing as the only option to "get back" higher single thread performance is to use BCLK and that opens a whole new world of uncertainties

😄 😄

I will get round to Geek Bench testing later, have work to do

🤣🤣


----------



## ManniX-ITA

mongoled said:


> Thanks to @Eder work even A85 has this option, does not make a difference on my CPU sample when using it.


Nice to know!
Do you remember if it has AMD PBS menu?


----------



## mongoled

ManniX-ITA said:


> Nice to know!
> Do you remember if it has AMD PBS menu?


Yes, its all available



Forgot to answer your question, adding vSOC brought no benefits to performance.

Also re L1 latency, 50.4. 50.2 is variance of runs, that core0 is my best core often results in it being awaken by other processes so really only in safe mode will it drop below 50 ns and the OS I am using is a fresh 21H1 but with no tweaks except for disabling "Windows Security" and using default "Balanced" profile


----------



## danakin

mongoled said:


> I tried the latest modded BIOS, only benefit I saw from this BIOS (have not tested extensively) was that this BIOS can post 1933 FCLK with no WHEA, but still have same memory holes and still "gimped" boost ovveride.


your able to post it whea free on the new agesa, but not on older ones? i have to give it a shot than...


----------



## mongoled

danakin said:


> your able to post it whea free on the new agesa, but not on older ones? i have to give it a shot than...


Yes thats right, on all older agesa posting FCLK 1933 resulted in WHEA warnings, although this is now WHEA warning free (i posted several times) I am still not able to find a solution to the "07" codes that sometime occur when either rebooting or booting from cold state ....

Also I did not do any extensive testing so WHEA 19s may arrise eventually ..


----------



## TimeDrapery

RonLazer said:


> Spoiler
> 
> 
> 
> Sorry I wasn't very clear. What I mean is when you suggest people use specific combinations of tCKE, CAD setups, and RTTs - what is it supposed to achieve? Better stability? Lower voltage requirements? Lower latency? Higher bandwidth?
> 
> If you could give me the combinations you've found already then I can try doing A/B comparisons on the performance criteria you're aiming for and try and learn more about the behaviour and role of each parameter. I've tried using a battery of tests for tCKE alone in the past and not seen any change, but that was with 0 setups and 0/0/5 on RTTs.
> 
> For example I think that at 2000MHz CR 2T you suggest people use tCKE=11, 4-4-18 setups and 6/3/6 RTTs, is this for 2xSR, 2xDR, 4xSR or will it work on all of them? What differences should I be looking for compared to tCKE=1, 0-0-0 setups, RTTs on 0/0/5?


@RonLazer

I've been reading and reading and reading in an attempt to gain a greater understanding of how setup timings do what they do and so far I've learned a lot of other things regarding DDR4 memory yet I still lack the depth of knowledge necessary to provide an explanation of their workings

I can tell you that, through my own trial and error experiments with the setup in my signature and another system of minute fitted with a Ryzen 3 3100 and a TeamGroup 2×8GB SR kit, I've found they're seemingly essential (as a "finishing touch") to extracting maximum performance regardless of the DIMMs configuration

Once all else in your timing set is configured to your satisfaction experimenting with setup timings is a must as I've seen effects such as:

• reduced VDIMM requirements which brings along many benefits itself
• disabling GDM and setting 1T CR no longer requires three or four days with of "get home safe" powder so you can disregard sleep and continue clearing CMOS 😂😂😂😂😂
• rather than focusing entirely on the "how low can I make the numbers" games, once you do attain stability you can focus far more heavily on optimally configuring timings so you've got a well synced set that, as far as I've seen, is going to be *far* more performant than any of the run-of-the-mill 1-1-1-2-3 GDM enabled, 1.2V VDIMM, "I set tRFC to 2 but it won't boot, @Veii please help me by retyping your old posts in this very thread that I can't be bothered to search for" timing sets

I feel like the word "skew" may have something to do with the explanation of how and why setup timings do what they do

Lemme know what you find! They're my new DRAM OC obsession so ... Back to reading patent applications I go!


----------



## mongoled

TimeDrapery said:


> Lemme know what you find! They're my new DRAM OC obsession so ... Back to reading patent applications I go!


😍😍


----------



## Sleepycat

craxton said:


> im one of those lucky ones that can run (any FCLK) without WHEA
> but its a dud on overclocking the CPU unless im just that bad at it...even following guides left here
> still core cycler screams at me on core 3-5 always..... unless i use positive curve???


I have the same thing with my 5900X. My best core needs positive 10 to pass core cycler. But putting +10 doesn't seem to make overclocking any worse for that core. Still can hit 4.9GHz.


----------



## RonLazer

TimeDrapery said:


> @RonLazer
> 
> I've been reading and reading and reading in an attempt to gain a greater understanding of how setup timings do what they do and so far I've learned a lot of other things regarding DDR4 memory yet I still lack the depth of knowledge necessary to provide an explanation of their workings
> 
> I can tell you that, through my own trial and error experiments with the setup in my signature and another system of minute fitted with a Ryzen 3 3100 and a TeamGroup 2×8GB SR kit, I've found they're seemingly essential (as a "finishing touch") to extracting maximum performance regardless of the DIMMs configuration
> 
> Once all else in your timing set is configured to your satisfaction experimenting with setup timings is a must as I've seen effects such as:
> 
> • reduced VDIMM requirements which brings along many benefits itself
> • disabling GDM and setting 1T CR no longer requires three or four days with of "get home safe" powder so you can disregard sleep and continue clearing CMOS 😂😂😂😂😂
> • rather than focusing entirely on the "how low can I make the numbers" games, once you do attain stability you can focus far more heavily on optimally configuring timings so you've got a well synced set that, as far as I've seen, is going to be *far* more performant than any of the run-of-the-mill 1-1-1-2-3 GDM enabled, 1.2V VDIMM, "I set tRFC to 2 but it won't boot, @Veii please help me by retyping your old posts in this very thread that I can't be bothered to search for" timing sets
> 
> I feel like the word "skew" may have something to do with the explanation of how and why setup timings do what they do
> 
> Lemme know what you find! They're my new DRAM OC obsession so ... Back to reading patent applications I go!


Oh I know what they do, and it would make sense that they could improve performance, but I can't understand what connection they have to tCKE or termination resistor values.


----------



## 1s1mple

craxton said:


> one really shouldnt use dram calc anymore for 5000 series to gather timings
> but if your going to use it, then you need thaiphoon burner
> download it if you havent,
> 
> then open, hit read, hit report, scroll all the way to the bottom,
> then hit show delays in nano seconds, after that itll take you back to the top
> then hit export (complete HTML report) save as whatever whereever youll be able to find
> and reconize.
> 
> once thats done open dram calc, select board, speed, how many sticks, and memory type.
> then hit compare, (reselect proper speed your wanting 3800 (max is 3866 for dram calc)
> then hit calculate
> should look something like (below)
> ignore mine saying 4000 and any red flavored text.
> (this is how to properly use dram calc) running it just by entering bdie, speed, board, stick, hitting calculate
> never one time worked for me...
> View attachment 2512763
> 
> 
> View attachment 2512762


I have done that if you read my post in [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## craxton

1s1mple said:


> I have done that if you read my post in [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


thats not what you did when you set A3,A2,B2 pcb revisions tho. it auto change it. leave what the import sets 
only set your frequency 
when using dram calc importing your ram into it is the easiest way to use it. 

as well as not changing PCB revision it resets it on my side when i do this. 
manual is what it should set? i could be wrong. but you have NO TIMINGS in the bottom left corner
so therefore dram calc doesnt see your import in nanoseconds to properly set your timings according 
to your ram sticks.

so again, try what i said but dont change anything but the frequency.


----------



## 1s1mple

craxton said:


> thats not what you did when you set A3,A2,B2 pcb revisions tho. it auto change it. leave what the import sets
> only set your frequency
> when using dram calc importing your ram into it is the easiest way to use it.
> 
> as well as not changing PCB revision it resets it on my side when i do this.
> manual is what it should set? i could be wrong. but you have NO TIMINGS in the bottom left corner
> so therefore dram calc doesnt see your import in nanoseconds to properly set your timings according
> to your ram sticks.
> 
> so again, try what i said but dont change anything but the frequency.


Okay i just did that way you mentioned but i highly doubt i can do CL 14


----------



## ManniX-ITA

1s1mple said:


> Okay i just did that way you mentioned but i highly doubt i can do CL 14


Seems to be very similar to the DJR, you can try these:









NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking...


Hey guys, what can I continue to do to improve my memory clocks. Here are my Zen timings. I have tried multiple things but it seems I am unable to go above 3733. Also I really don't know which timing to further tighten. As an addition, I am also adding my screenshots of DRAM calculator. Is...




www.overclock.net


----------



## 1s1mple

ManniX-ITA said:


> Seems to be very similar to the DJR, you can try these:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking...
> 
> 
> Hey guys, what can I continue to do to improve my memory clocks. Here are my Zen timings. I have tried multiple things but it seems I am unable to go above 3733. Also I really don't know which timing to further tighten. As an addition, I am also adding my screenshots of DRAM calculator. Is...
> 
> 
> 
> 
> www.overclock.net


Thanks, will test those settings as well


----------



## TimeDrapery

RonLazer said:


> Spoiler
> 
> 
> 
> Oh I know what they do, and it would make sense that they could improve performance, but I can't understand what connection they have to tCKE or termination resistor values.



@RonLazer

WONDERFUL! Please, share with the class what setup timings are and how they function to bring about the results that they do... Like I'd said, I don't possess the knowledge necessary to provide an accurate description

Okay, I know you're not a novice here in this arena

You're not understanding what connection the setup timings have with tCKE or RTT settings? Your statement has got me thinking that I certainly do not understand what the connection is here or how they do what they do... Just when I thought I was out 😂😂😂😂😂

These three combo'd up help us to "manipulate"/"move" the "shape" and "positioning" of the signals as represented by the data eye, do they not? Necessarily, all three work synergistically to help improve signal integrity through course and fine manipulations of the memory controller as well as on-die termination on the DIMMs, right?

Regardless, if I've got free chicken, everybody eats... Share your chicken, friend!


----------



## craxton

ManniX-ITA said:


> My Core 1 is the best core and needs a -10.
> But it's much faster than the Core 0 at -18, bit slower than the 2nd best Core 4 at -20 and trillion times faster than Core 15 at -29.
> 
> So it's relative to the starting point, you need to check how fast really is and how it compares to the others.
> Higher count has sadly a bit of negative impact on all-core performances, it's the weird AMD design for CO.
> But on single core performance a positive core doesn't mean necessarily that is bad.
> Especially on a 5600x with very low thermal constraints; for a 5900x and up can be more of a problem.
> 
> Check what is the actual speed of your cores.
> 
> Use BenchMate:
> 
> 
> 
> 
> 
> BenchMate
> 
> 
> 
> 
> 
> 
> 
> benchmate.org
> 
> 
> 
> 
> 
> Set affinity as below and launch CPU-z, measure every core (test only one thread per core).
> 
> View attachment 2512771
> 
> 
> Set the Threads to 1 as below:
> 
> View attachment 2512772
> 
> 
> And click on Bench CPU.
> Close it once done, launch it with anew affinity every time.


ok, so i only close CPUz correct?
if so then i believe core 3 and 4 (4,846 not quite 4850)
will be close enough i suppose TM5 pushes all to 4850.

however if im suppose to close benchmate down then i didnt run it right.
and im suppose to use HWiNFO to monitor speeds on core to core runs?

(EDIT) seems core 4 and 3 (both threads as well) dont hit over 4845.....
might need to adjust curve a little more but thank you for this tool manna.


----------



## ManniX-ITA

craxton said:


> ok, so i only close CPUz correct?
> if so then i believe core 3 and 4 (4,846 not quite 4850)
> will be close enough i suppose TM5 pushes all to 4850.
> 
> however if im suppose to close benchmate down then i didnt run it right.
> and im suppose to use HWiNFO to monitor speeds on core to core runs?
> 
> (EDIT) seems core 4 and 3 (both threads as well) dont hit over 4845.....
> might need to adjust curve a little more but thank you for this tool manna.


No you are only supposed to close CPU-z, otherwise will not be launched with the new affinity
HWIinfo will impact scores, make a first run to record the scores
If you want to see the clocks make a second run


----------



## craxton

ManniX-ITA said:


> HWIinfo will impact scores,


yes as it impacts all scores for every test ive ever ran....
i wasnt even thinking about scores... smh



ManniX-ITA said:


> make a first run to record the scores


record the scores myself in notes somewhere? 
or does the software record them? 
yes i know its simple, but nothings (as many have already seen) is simple with me..
so i do apologize as i almost always have a question to every answer given.
as overthinking is something ive yet to solve and put an end to..


----------



## ManniX-ITA

craxton said:


> record the scores myself in notes somewhere?


Yes 
Best if you record for each core the score, the frequency it runs on the 2nd run and the vid.
Will be easier to understand how a new BIOS or new settings are impacting the cores
let's say a new agesa with your old CO is unstable, you can tell maybe it's cause it's pushing too high in frequency or low in vid the cores


----------



## Takla

Can anyone tell me why I always get 67.2ns latency in AIDA64 on cold boot, but 66.6ns after a restart?


----------



## ManniX-ITA

Takla said:


> Can anyone tell me why I always get 67.2ns latency in AIDA64 on cold boot, but 66.6ns after a restart?


Probably the VSOC below VDDG, set it at least to 1.1V or a bit higher


----------



## Takla

ManniX-ITA said:


> Probably the VSOC below VDDG, set it at least to 1.1V or a bit higher


SOC is set to 1.05, and IOD+CCD is set to 1.05 too. Its just vdroop that shows it as lower. Tried with LLC3 which has soc at ~1.04v but still the same results.

Edit: Yikes. Tried setting every single memory timing/setting manually, tried different types of memory training settings in amd cbs, still nothing...


----------



## craxton

on an updated note


ManniX-ITA said:


> Yes
> Best if you record for each core the score, the frequency it runs on the 2nd run and the vid.
> Will be easier to understand how a new BIOS or new settings are impacting the cores
> let's say a new agesa with your old CO is unstable, you can tell maybe it's cause it's pushing too high in frequency or low in vid the cores


ok, gotcha and im done with testing...no hwinfo and with hwinfo..
(if anyone is curious to what software this is, well its (notes on a Xiaomi mi 11)
then swapped to "create mind map" 
anyhow here it is....not much differences but it looks like HWiNFO might make scores a bit better???????
had snapshot polling on for the third run which is what i recorded. seen a response you had made to another user in 
core-cycler thread about this program (literally telling them the same thing) i hadnt seen it until after you told me 
how-to otherwise i wouldnt have asked...

core 0 and core 5 both have the lowest core VID of all the other cores where "other cores" will use
1.3x VID where as 0 and 5 would be 1.21..... (my curve for core 0 is the strongest but it passed core-cycler and OCCT 5 hours (all cores did on occt) 
but 3-5 failed core cycler until i changed it again to positive on core 3 and lowered to under 10 on 5 (all but core 0 are under -10 now besides core 3 which is +10)

my findings is that *this is a headache and each restart can cause something different *
meaning, i can restart and not change anything and get only core 3 to fail (before changing to present settings)
or i could get core 5 to fail and would run for 13 hours until it skipped 5 so many times i turned off skip core
and would cause a crash (says the logs was indeed core 5) but would run on core 5 for almost the entire test iteration started at 2 a.m.
crashed at 7 pm yesterday.... 
anyhow, im crossing my fingers ive gotten somewhere stable (might go back to the older bios) 
since id rather see higher curve offset numbers (strange how humans work) higher curve numbers but voltage usage was
a little higher 

anyhow, ill keep looking at posts to see what else i can use to further advance my system 
as of right now, going to test my CO settings against my pure offset.... and see where the performance might lay.


----------



## RonLazer

@craxton there isn't an explanation that is directly transferable to overclocking usefulness, unfortunately. Each setup time is measured in fractions of a clock cycle, I believe 32 at 1T would be equivalent to running 2T, but I forget the exact crossover mechanism. It functions as a phase offset for that signal line, e.g. if you used a setup time of 16 on the Address Command bus then it would begin latching the address 1/2 cycle before the signal for an ACT command occurred.

This is useful to correct the "skew" that is characteristic of of the response profile of transistors, which improves DQ-calibration accuracy, which in turn causes the PHY to train a set of faster performing timings, or at least increases accuracy in signalling. 

Problem is the Zen2/3 memory controller seems to be pretty damn good at calibrating without adjustment, and there's certainly no way of predicting what the setups ought be that I can tell.


----------



## jomama22

RonLazer said:


> @craxton there isn't an explanation that is directly transferable to overclocking usefulness, unfortunately. Each setup time is measured in fractions of a clock cycle, I believe 32 at 1T would be equivalent to running 2T, but I forget the exact crossover mechanism. It functions as a phase offset for that signal line, e.g. if you used a setup time of 16 on the Address Command bus then it would begin latching the address 1/2 cycle before the signal for an ACT command occurred.
> 
> This is useful to correct the "skew" that is characteristic of of the response profile of transistors, which improves DQ-calibration accuracy, which in turn causes the PHY to train a set of faster performing timings, or at least increases accuracy in signalling.
> 
> Problem is the Zen2/3 memory controller seems to be pretty damn good at calibrating without adjustment, and there's certainly no way of predicting what the setups ought be that I can tell.
> 
> View attachment 2512842


Want to add say here that the cad bus timings available only kinda relate to the second part of that skew image. The setup timings are exactly as they sound, the increase the time given for the rise or fall of a waveform to reach its "1 or 0", to allow the data to be "setup" before being accessed. That second image is still misleading as it shows a shortened hold time, which is not affected by setup times (unless the strobe cycle is strict).

They do not phase shift the cycle (doing so would have no affect on performance, as the "pos/neg" images represent). And as you said, that is handled by the imc.

They also do not alter the amplitude (as the accm represents).

They have no direct connection or impact to signal impedance, rather, they only only allow accomodations for such. You are more or less delaying the strobe on a given command, hence increasing the distance/time between each strobe.


----------



## craxton

regarding linpack xtreme,

calling out you 4000/2000 5600x users, 
whats your bench runs look like ??

(do note this is not a contest, its more of a comparison)
3800 and higher join in too.


----------



## craxton

RonLazer said:


> @craxton there isn't an explanation that is directly transferable to overclocking usefulness, unfortunately. Each setup time is measured in fractions of a clock cycle, I believe 32 at 1T would be equivalent to running 2T, but I forget the exact crossover mechanism. It functions as a phase offset for that signal line, e.g. if you used a setup time of 16 on the Address Command bus then it would begin latching the address 1/2 cycle before the signal for an ACT command occurred.
> 
> This is useful to correct the "skew" that is characteristic of of the response profile of transistors, which improves DQ-calibration accuracy, which in turn causes the PHY to train a set of faster performing timings, or at least increases accuracy in signalling.
> 
> Problem is the Zen2/3 memory controller seems to be pretty damn good at calibrating without adjustment, and there's certainly no way of predicting what the setups ought be that I can tell.
> 
> View attachment 2512842


thanks for this, but i might as well be someone who can only see lines and dots
bc i have no clue what this means... i have a small idea
but to translate that and make myself look more foolish ill leave out.

curve doesn't only adjust how voltage hits the processor at a certain point?
the way you guys go at this is....well im one of the "smartest" people turn to around here.
yet this makes me feel dumb  in order to setup my curve settings for "true stability"
i do need to understand what it does and doesnt affect.

but im confused to what DIFF and ACCM are, significant skew would mean someone who
has adjusted relatively hard on curve settings?

also to add, my setup timings can impact how far along i can adjust my curve?
you guys are using far to big and "over compensating" words for my "small" self to understand..
it took me months to properly understand Veii. 
if i know one thing, its that AMD is doing all the right things the wrong way *


----------



## jomama22

craxton said:


> thanks for this, but i might as well be someone who can only see lines and dots
> bc i have no clue what this means... i have a small idea
> but to translate that and make myself look more foolish ill leave out.
> 
> curve doesn't only adjust how voltage hits the processor at a certain point?
> the way you guys go at this is....well im one of the "smartest" people turn to around here.
> yet this makes me feel dumb  in order to setup my curve settings for "true stability"
> i do need to understand what it does and doesnt affect.
> 
> but im confused to what DIFF and ACCM are, significant skew would mean someone who
> has adjusted relatively hard on curve settings?


They do not relate to CO at all. I'm not sure why he quoted you with his response (probably a mistake).

CO merely undervolts non-linearly across the frequency curve to allow additional power budget for a given workload and hence, higher clocks achieved within the same power limit.


----------



## RonLazer

@jomama22 you're right, I just couldn't find a good image of the classic signal skew, but this conveys it better:








I understand its not exactly a phase-offset, but it functions somewhat similarly and I couldn't think of a way to express it better. And in principle there's no direct impact on performance, but there's numerous timings that are set during training that we can't define, and they can have a pretty severe effect. Tuning the memory-training _can _in some cases improve the training accuracy which means the PHY will adopt tighter timings which does affect performance, though marginally. 

@craxton I'm not sure what you mean by voltage curves? Are you referring to Curve-Optimiser? These are different concepts, I was replying to your earlier comment asking me to explain what the CAD Setup Times do, this is solely a memory related effect.


----------



## jomama22

RonLazer said:


> @jomama22 you're right, I just couldn't find a good image of the classic signal skew, but this conveys it better:
> View attachment 2512845
> 
> I understand its not exactly a phase-offset, but it functions somewhat similarly and I couldn't think of a way to express it better. And in principle there's no direct impact on performance, but there's numerous timings that are set during training that we can't define, and they can have a pretty severe effect. Tuning the memory-training _can _in some cases improve the training accuracy which means the PHY will adopt tighter timings which does affect performance, though marginally.
> 
> @craxton I'm not sure what you mean by voltage curves? Are you referring to Curve-Optimiser? These are different concepts, I was replying to your earlier comment asking me to explain what the CAD Setup Times do, this is solely a memory related effect.


I suppose it's possible to view setup timings as providing a potential benefit to underlining timings of the whole memory system, but it would really only be advantageous if negative setup times were available.

They are also so specific to command and address bus lines that their only use in this form is for stabilities sake at the expense of delayed readings of those busses.

Those underlining timings could make the data eye more optimized around that now delayed point, but you are still dealing with delay at the end of the day.

If it allows slightly tighter timings then therein lies it's direct benefit, but that only matters if the delay is overcome by those tighter timings.

Unfortunately, no one has really showed any example of no setup timing vs setup timings with the tightest stable timings of both. I personally don't have the time or patience lmao.

I think what's also difficult here is even if there was a comparison, using aida to show the .1 or .2ns shaved would be the extent of the comparison made lol.

Do want to add that the image you put is also a bit misleading in the sense that it still shows no performance degradation caused by the setup time extension. It still only shows the skew/phase shift of a 1/2 cycle to better align with the widened data eye. I think the best way to think of it taking the signal and stretching it at both ends. The reason the higher the timings the closer you reach 2t (if we are using them for 1t timings for instance) is because we are stretching out the time each half cycle will take. This further you stretch then, the closer you get to the time 2t takes for each command. You are making one 1t cycle take up to the time one 2t cycle takes. So instead of 2t where you are sending two duplicate commands right after each other, you are just using one extended command.


----------



## TimeDrapery

RonLazer said:


> Spoiler
> 
> 
> 
> @craxton there isn't an explanation that is directly transferable to overclocking usefulness, unfortunately. Each setup time is measured in fractions of a clock cycle, I believe 32 at 1T would be equivalent to running 2T, but I forget the exact crossover mechanism. It functions as a phase offset for that signal line, e.g. if you used a setup time of 16 on the Address Command bus then it would begin latching the address 1/2 cycle before the signal for an ACT command occurred.
> 
> This is useful to correct the "skew" that is characteristic of of the response profile of transistors, which improves DQ-calibration accuracy, which in turn causes the PHY to train a set of faster performing timings, or at least increases accuracy in signalling.
> 
> Problem is the Zen2/3 memory controller seems to be pretty damn good at calibrating without adjustment, and there's certainly no way of predicting what the setups ought be that I can tell.
> 
> View attachment 2512842



@RonLazer

I think you were intending to address me, not @craxton

Firstly, THANK YOU A WHOLE TON (_*no*_ sarcasm) for taking your time to deliver me that explanation... that's righteous of you

Secondly, what are some good references you'd recommend I read in order to gain a greater understanding of these concepts and functions?



jomama22 said:


> Spoiler
> 
> 
> 
> ...
> 
> They are also so specific to command and address bus lines that their only use in this form is for stabilities sake at the expense of delayed readings of those busses.
> 
> ...
> 
> If it allows slightly tighter timings then Theron lies it's direct benefit, but that only matters if the delay is overcome by those tighter timings.
> 
> ...


@jomama22

Yup, this is the benefit I'm seeing... Lower values for exposed timings and greater stability

As I understand it, these timing values correspond with latency in picoseconds, not nanoseconds... Does this jive with what you know? If yes why don't you think these could have larger impacts on performance?


----------



## RonLazer

Sorry I've lost track of who is who. Hopefully anyone who cares enough is reading the posts and will catch it either way 


I agree with @jomama22 the differences we're talking about are really really small. Boot-to-boot memory training variation is larger than the differences I'd expect to see from the PHY training. That's why I was hoping @Veii can point me in the right direction on what to look for since they have already done all the trial and error the old-fashioned way.


----------



## jomama22

RonLazer said:


> Sorry I've lost track of who is who. Hopefully anyone who cares enough is reading the posts and will catch it either way
> 
> 
> I agree with @jomama22 the differences we're talking about are really really small. Boot-to-boot memory training variation is larger than the differences I'd expect to see from the PHY training. That's why I was hoping @Veii can point me in the right direction on what to look for since they have already done all the trial and error the old-fashioned way.


Wasn't trying to be pedantic about the pics lol. So my bad for that. If I was at the house I'd just draw it.



TimeDrapery said:


> @RonLazer
> 
> I think you were intending to address me, not @craxton
> 
> Firstly, THANK YOU A WHOLE TON (_*no*_ sarcasm) for taking your time to deliver me that explanation... that's righteous of you
> 
> Secondly, what are some good references you'd recommend I read in order to gain a greater understanding of these concepts and functions?
> 
> 
> 
> @jomama22
> 
> Yup, this is the benefit I'm seeing... Lower values for exposed timings and greater stability
> 
> As I understand it, these timing values correspond with latency in picoseconds, not nanoseconds... Does this jive with what you know? If yes why don't you think these could have larger impacts on performance?


Just read about anything related to signal integrity for anything honestly. Doesn't have to be related to memory. But there are plenty of papers specifically related to memory. 

I don't know the fractions each setup time interval represents but yes, you would be dealing with picoseconds. Important to remember this is accumulative over each cycle though.


----------



## Dollar

Takla said:


> Can anyone tell me why I always get 67.2ns latency in AIDA64 on cold boot, but 66.6ns after a restart?


I can reproduce this, it gave me cancer trying to dial in voltages. Thats an ASUS crosshair VI bug that never got fixed. For more fun try sleeping and then waking your system and then go check your vddg/vddp voltages in zentimings to see they have reset to stock values.


----------



## TimeDrapery

jomama22 said:


> Spoiler
> 
> 
> 
> Wasn't trying to be pedantic about the pics lol. So my bad for that. If I was at the house I'd just draw it.
> 
> 
> Just read about anything related to signal integrity for anything honestly. Doesn't have to be related to memory. But there are plenty of papers specifically related to memory.
> 
> I don't know the fractions each setup time interval represents but yes, you would be dealing with picoseconds. Important to remember this is accumulative over each cycle though.



That makes a lot of sense to me, thanks so much for educating the masses!!!

So... Considering their impact on stability and that they're cumulative does this mean that after however long of them stacking throughout cycles you'll eventually toss errors and there's nothing to be done about this?

For example... Here's a flat 15 set below, it's stable through 25× cycles of 1usmus_v3... If I remove the setup timings should it remain stable as configured? If I run Karhu overnight would you think it would remain stable?










Here's the only reference I've found to values <---> picoseconds...


----------



## Veii

RonLazer said:


> That's why I was hoping @Veii can point me in the right direction on what to look for since they have already done all the trial and error the old-fashioned way.


Will do, give me a bit of time 
I can add, test FCLK performance with monero mining
Specifically Releases · fireice-uk/xmr-stak
I absolutely dislike the marketing side of it, and more than anything would like to avoid advertising any random crypto. As that's how they grow and we can later deal with the problems their growth caused
(looking at the chia nonsense ~ sorry for the harsh words to any dev who made it)

Just remembering it from TechTechPotato's (Ian) Random snippets on Twitter
And remembering how people praised the big jump 2100 FCLK gave, although my core OC is noobish at best (considering i was always +200mhz locked at max)

Test it with this, scaling is perfectly linear. Powerbudget differences are shown and timing differences are shown
Like you mentioned, using Scientific Dataset-Compilation shows very well how FLCK behaves as accelerated interposer

ROI on it with a 5600X strongly OCd was around 1 year ~ soo i feel confident sharing it as benchmark without fearing CPU prices could skyrocket again
(it made 1€ a day + electricity factored in , but 24h heat + noise was a nonsense to even bother with it. just a good benchmark like early on Nimiq was for Threadripper Farms)
the FCLK bump was about 2000H/s , which equals to around 15% bump
Geekbench did show 20% uplift too ~ but this can be because of reaching a lower latency wall or because of low timings

I shouldn't forget that 14nm had a 70ns (Aida64) or 60ns (SiSandra) Inter-Core latency wall
If fabric thanks to mem behaved slower - any instruction set between chiplets was throttled & it made no difference if you run 3.80ghz or 4.1 on the 1700X and similar APUs
===========================================
This is the poop i deal right now with ~ even after being able to Translate ASIO 64 , to ASIO32 to WDM
Simply bending down to the lack of Elgato's PCIe Support on Unix and macOS ~ and dealing with the same nonsense for Universal Audio and lack of Windows WDM drivers.
Anything thunderbolt 40gb/s steals lanes from the X16 CPU based slot ~ and causes huge GPU spikes


Spoiler: Spoiler of Fighting against 4 Fronts [ASUS, UAD, AMD, Intel TB4]




































I've noticed something interesting.
Well this is a tiny advice about FPS boosts and Frame-Inconsistency
Message-Interrupt Mode is very valuable ~ even MSIX
Push important stuff over towards it ~ especially Nvidia GPUs / Quadro's and AMD RX are by default on MSI mode

The interesting thing:
Any Realtek device i've seen, so far pushes Interrupt Process priority to the Highest State
Ignoring takin priority over the GPU, over Sound drivers or any USB IO
Nearly all USB controllers suspend randomly into a powerstate, but remain on LineBased communication mode
This will mean that random DPC latency chokes will happen, and the NIC will guarantee that these not only happen, but hang in a pipeline.
This stacks and after time you have crashes

Been digging strongly through why Universal Audio was/is unwilling to bother with Windows Customers and why Ryzen 5xxx has a specific issue , which Matisse didn't have
This above is a screenshot for a client - but take a look by yourself
It's very offtopic, but i think every memOCer will benefit putting it that way ~ and doublechecking + lowering absurd priority settings Realtek drivers and some USB Controll-chip "manufactures" set on driver level

I still have to deal with consistent powermanagement issues and buggy powerplans
And also want to deal with the AMD "end of support" part they enforce to BoardPartners
But this remains as open end.


Will answer with more tricks and a bit more information ~ when i can [No ETA, i can't hold to ETA's]
You'll get a list that is voltage , frequency, and capacity based for RTTs.
Still have to deal with the Rev.E's. Deal with Intel & Asus together for the Thunderbolt/USB 4.0 issues
All aside dealing with macOS/Unix ~ writing a compatible APCI DSDT Map for Thunderbolt 4 on this board.
Take a look on X370 and Vermeer (want). Finally fix Universal Audio's issues
And at the same time do part-time OC work with an E-Sports Technical Marketing Team (doing every night finetune work to get enough just being able to pay my rent)

I'm sorry, i'll get back to you ~ but right now it's a lot sitting on backtrack
Soo i nearly fully do ignore PMs too ~ it's just too much open-END things
Very proud of AMD tho with the Computex Keynote ~ aside all the harsh critique and issues that exist. A big technological leap ! 😇


----------



## RonLazer

Sorry @Veii didn't mean to hassle you!


----------



## craxton

jomama22 said:


> They do not relate to CO at all. I'm not sure why he quoted you with his response (probably a mistake).


lol yea must have been, since i had no idea what that was for nor context where it came from
as i was merly speaking about CO and cpu overclocking being harder to achieve consistent than that
of a 4000mhz stable config....


RonLazer said:


> explain what the CAD Setup Times do, this is solely a memory related effect.


i understand now why you posted it, but im still blank. 
"you can write books of knowledge" have people read it, and they still
have no idea what the book was about. (thats me on some forms of the stuff you guys state here)
none the less, appreciate posting it. as im sure someone/others will appreciate it


----------



## Veii

TimeDrapery said:


> Here's the only reference I've found to values <---> picoseconds...
> 
> 
> craxton said:
> 
> 
> 
> i understand now why you posted it, but im still blank.
> "you can write books of knowledge" have people read it, and they still
> have no idea what the book was about. (thats me on some forms of the stuff you guys state here)
> none the less, appreciate posting it. as im sure someone/others will appreciate it
Click to expand...

Check this, but it's in Korean ~ Thread *C*
Just scroll down








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


One thing that is not clear to me is the pbo limits. I have seen gamernexus set these to motherboard limits, which are way beyond what the FUSE limits are. Assuming Fuse limits are indeed a thing, then why are people talking about different settings for TDP,PPT,EDC? You could set set everything...




www.overclock.net




Google Translate is not soo good with korean


----------



## Veii

GribblyStick said:


> One thing that is not clear to me is the pbo limits. I have seen gamernexus set these to motherboard limits, which are way beyond what the FUSE limits are. Assuming Fuse limits are indeed a thing, then why are people talking about different settings for TDP,PPT,EDC? You could set set everything to max and the chip would still not be at risk? Might thermal throttle at worst, but then you could lower TDP until it stop, that would still not damage the CPU


Actually never answered
Fuse Limits are artificial limits by AMD
Real limits are different
CoreCycler - tool for testing Curve Optimizer settings check this post
Need to finally fill out the 5900X ~ hmm
This is public CTR information, soo we can speak a bit about it

The reason we set PBO limits higher, is to lift one of the stages of throttle back
There are many of them, this is to "trick" one part of the sensors

Usually the best Performance, you get out if you limit supplied allcore voltage ~ which is by limiting EDC
Else the best single core perf you get by voltage limit on TDC
Currently cache is dynamic (good) soo the EDC limit needs to be lifted (not soo good) ~ in order to reach peak cache boost
Which also requires the user to have as much power-reserves as possible = core parking, deep sleep causes overboost (DF-States) but sleep/parking is fine (global C-State generation)

PPT is purely a powersuply limit, and max TDP limit
It has priority over anything and will be held.
Lift it 
TDC is what we can limit so far, for performance

Vermeer is dynamic, Matisse was too but PBO added 75-125mV more allcore voltage
Soo limiting EDC was one of the best things to do on Matisse
the EDC bug bugged out the throttle state (reversed it) and also disabled FIT.
EDC BUG works still , but it's more than just bad to use ~ soo better forget it

Yes limit TDC, unlock EDC to it's full protential
Keep in mind, by enabling PBO and also changing the Scalar, you introduce a magnitude of more voltage (allcore and peak)
Work with curve optimizer against it ~ be it just an allcore negative CO or per core

But max out EDC to lift one stage of the throttling
They marketed it as "fixed" but it's at best at 70% of it's potential speedup
But it's also tied to clockspeed 
Write is purely focusing on FCLK , and not memory frequency


----------



## mirzet1976

craxton said:


> regarding linpack xtreme,
> 
> calling out you 4000/2000 5600x users,
> whats your bench runs look like ??
> 
> (do note this is not a contest, its more of a comparison)
> 3800 and higher join in too.
> 
> View attachment 2512844


Here


----------



## KedarWolf

mirzet1976 said:


> Here
> 
> View attachment 2512883


----------



## mongoled

Veii said:


> Yes limit TDC


Thanks for this tidbit, will test it later, was not aware that limiting TDC could get more performance benefits





KedarWolf said:


> View attachment 2512885


@craxton specifically requested 5600x running at 4000/2000, which is the result @mirzet1976 provided


----------



## iraff1

Can any of you memory experts give me any ideas how to tweak my Ballistix Max 4x16GB BLM16G40C18U4B.M8FB1.
I currently run these in 3800mhz 17-18-18-36 timings, TRFC is 666 which seems high? 

These modules are rated for 4000mhz but my system won't boot at 2000mhz, but i haven't done any tweaks to any voltages. Do you guys have any suggestions what i could try to get these to boot at 2000? My guess is that i have to increase voltages to something in order to even have a shot at 2000mhz, then hope my cpu mem controller can handle it?

Where shoudl i begin, what voltages are safe for long term overclock use? 

I run these on a gigabyte x570 xtreme with a 5950x cpu.


----------



## mongoled

Posting at difference FCLK frequencies is dependant on your CPU sample.

If your CPU sample has a FCLK hole at 2000 mhz, nothing you change will make a difference.

FYI, my current CPU can boot the following FCLK

1866/1900/1933/2033/2067

Note that I have a memory hole at 1966/2000

So you need to first find out where your memory holes are then see what is the highest FCLK you can post reliably and work from there ....


----------



## iraff1

mongoled said:


> Posting at difference FCLK frequencies is dependant on your CPU sample.
> 
> If your CPU sample has a FCLK hole at 2000 mhz, nothing you change will make a difference.
> 
> FYI, my current CPU can boot the following FCLK
> 
> 1866/1900/1933/2033/2067
> 
> Note that I have a memory hole at 1966/2000
> 
> So you need to first find out where your memory holes are then see what is the highest FCLK you can post reliably and work from there ....


Wow that is interesting, i have to test other speeds then because i have only attempted at 2000mhz.

Do any of you know any limits regarding Ballistix Max Micron memories? I am mostly looking for:
1. what is the maximum safe operating temprature of these memory modules?
2. what is the maximum safe voltage for long term use for these memory modules?

I see some people using 1.5v on their samsung b die, question is can i do the same for my micron modules?


----------



## mongoled

iraff1 said:


> Wow that is interesting, i have to test other speeds then because i have only attempted at 2000mhz.
> 
> Is it not possible to increase some voltage values to be able to post at certain speeds as well or does that have nothing to do with it?


I have literally spent hour upon hour trying to post at my FCLK holes, maybe once in every 100 or so attempts it will pass "07" error, nothing, absolutely nothing I have tried has made any difference ...


----------



## Veii

iraff1 said:


> Wow that is interesting, i have to test other speeds then because i have only attempted at 2000mhz.
> 
> Do any of you know any limits regarding Ballistix Max Micron memories? I am mostly looking for:
> 1. what is the maximum safe operating temprature of these memory modules?
> 2. what is the maximum safe voltage for long term use for these memory modules?
> 
> I see some people using 1.5v on their samsung b die, question is can i do the same for my micron modules?


Try this , just drop RTT_PARK 2x then it should boot with 4 dimms
Adjustt RTT_PARK to a stronger value till it posts
8gb Ballistix MAX are Rev.E, 16gb are 2020 version of Rev.B
I run them at 1.6v for now, they can run at 1.72v but it makes no sense ~ CL12 @ 3800 or 4000 is impossible, but CL13 , tCWL 12 runs. Worse Perf tho


Spoiler




















After 4000 it needs tRCD 19
17 will not work - no way 
But 2T or 1T , forget GDM


RTTs define reaching Amperage at the dimms, voltage means nearly nothing ~ just lowers timings well
You probably are looking at RTT_PARK /5 for them (4 dimms) @ 34ohm proc (sub 36.9) @ these voltages 
Maaybe /6 could work for 4 dimms ~ but i doubt, it needs lower proc

Also this is SMU 56.50 / AGESA 1.2.0.2
it will not work on 56.46 or lower ~ uh maybe 56.46, but surely not 56.45 or lower 

Yea try it, i think it's fine
Beyond 1.56 VDIMM please
Also take my 1-4-4-1-6-6 SD, DD's for "many dimm" setups
and add +1 on tRDWR because of "many dimms"

EDIT:
Soo to recap,
+1 for many dimms on procODT and +1 on tRDWR because of many dimms
Then another +1 on both ~ because these "dimms" are double the capacity and dual rank !
Missed the point that they are 4x dual rank
Target procODT would be then 36.9 to 40 max , lower is better
RTT_PART you have to check , higher divider ~ weaker setting is better, but you need to drop it at least -2 from what i run soo /5 or /4
WR & NOM are fine for higher voltage
ClkDrvStr could need +1 on them 40 instead 30, 120 instead of 60 or 60 instead of 40
Good luck !


----------



## ManniX-ITA

mongoled said:


> @craxton specifically requested 5600x running at 4000/2000, which is the result @mirzet1976 provided


Let us 5950x owners have some fun as well 



Veii said:


> I can add, test FCLK performance with monero mining
> Specifically Releases · fireice-uk/xmr-stak


Will test it, thx!


----------



## mongoled

ManniX-ITA said:


> Let us 5950x owners have some fun as well
> 
> 
> 
> Will test it, thx!


Yes we call all have fun, just pointing out that its not what craxton asked for

😍


----------



## ManniX-ITA

mongoled said:


> Yes we call all have fun, just pointing out that its not what craxton asked for
> 
> 😍


Let me than do as well a call out for 5950x owners to provide their PBO results 

This is the profile I was using yesterday:


http://imgur.com/a/58BP537


Now I'm running with A31 and I'm reworking it.
Too much VDDG CCD voltage made me lost at least 5 counts on Core 1.
Which is my best core... not acceptable. Lost 12 points in CPU-z.
I'm trying to find a good voltage combo to keep it at least between -15 and -18.
Then I'll have to find a way to compensate for the lower CCD voltage.


----------



## Veii

ManniX-ITA said:


> Then I'll have to find a way to compensate for the lower CCD voltage.


DF_States doesn't cause overboost issues for you on 1203A ?
You can increase the VR 12VIN OCP expander 
Enable PMU training
Maybe enable MSI latency enchance to change tPHYWRL and tPHYWRD

Lowering CCD increasing IOD, balances things out - if UncoreOC mode is disabled and SOC-OC mode is disabled


----------



## mongoled

Guess what guys/gals, obviously we have seen this before but it's not been widely reported, but I've seen it for myself, really should have tested this before hand! 

The WHEA 19s FCLK issue is not just motherboard or cpu related it's also graphics card related. 

As I was due to do some maintenance on my loop decided it was time to unplug everything such as sata, nvme, pci addon cards etc and see if I could determine if some other piece of hardware or bus where it is sitting is the cause. 

After playing around for a while with these devices I came to the conclusion that these were not effecting the WHEA 19s, that's when I decided to try with a different GFX card and yup you guessed it, WHEA has changed! 

With GT710 it was unstable posting 1900 FCLK! I tried my 2133 FCLK settings and after numerous failed booting attempts I managed to get into Windows, when I finally was able to get into event log there were thousands upon thousands of WHEA 19s, was then greeted with a reboot. 

So it's becoming clearer why AMD are not really interested on commenting on this "issue" as they probably understand that all pieces of hardware need to "behave" and work on tandem to be and to push FCLK further without having WHEA 19s


----------



## mongoled

Now I've tried with an X1650 Pro (yeah, yeah I know    ) and it's better than the GT710 and it's acting like the GTX960 I am currently using, though it's struggling posting at 2133 FCLK

Now to try the GTX960 in the PCIe chipset slot...


----------



## domdtxdissar

mirzet1976 said:


> Here
> 
> View attachment 2512883





KedarWolf said:


> View attachment 2512885


Running extended 8GB while others run 3 GB ?

I'm getting this scaling between these two modes


----------



## Taraquin

iraff1 said:


> Can any of you memory experts give me any ideas how to tweak my Ballistix Max 4x16GB BLM16G40C18U4B.M8FB1.
> I currently run these in 3800mhz 17-18-18-36 timings, TRFC is 666 which seems high?
> 
> These modules are rated for 4000mhz but my system won't boot at 2000mhz, but i haven't done any tweaks to any voltages. Do you guys have any suggestions what i could try to get these to boot at 2000? My guess is that i have to increase voltages to something in order to even have a shot at 2000mhz, then hope my cpu mem controller can handle it?
> 
> Where shoudl i begin, what voltages are safe for long term overclock use?
> 
> I run these on a gigabyte x570 xtreme with a 5950x cpu.


Are they rev E or rev B? What is default voltage? You must probably run tRCDRD a bit higher at 4000, and it scales negatively with more volt on rev E/B. Try 16-19-16-35 and 60 tRC, tRFC 600, that might work. Copy other timings from rev E 3800 dram calc like trrds, tfaw, twr etc.


----------



## domdtxdissar

ManniX-ITA said:


> Let me than do as well a call out for 5950x owners to provide their PBO results


These are my 24/7 CTR settings after ~42 hours uptime in bloaty Windows install..
Very warm weather here also today which dont help matters. (above 26 degrees ambient)








Around 646 Gflops in normal 3GB mode without closing anything.

Guess i can get close to 655 or above 660 in 3GB if i wanted to "maxbench" this.


----------



## ManniX-ITA

domdtxdissar said:


> I'm getting this scaling between these two modes


Is this with PBO?


----------



## domdtxdissar

ManniX-ITA said:


> Is this with PBO?


That screen was from static 4500 mhz
Full post with numbers from static 4500mhz @ 6, 8, 12 and 16 cores here:

Iam talking about difference between benchmode 3GB and extended 8GB.
8GB scores higher


----------



## ManniX-ITA

Veii said:


> DF_States doesn't cause overboost issues for you on 1203A ?
> You can increase the VR 12VIN OCP expander
> Enable PMU training
> Maybe enable MSI latency enchance to change tPHYWRL and tPHYWRD
> 
> Lowering CCD increasing IOD, balances things out - if UncoreOC mode is disabled and SOC-OC mode is disabled


Gosh, I've already rolled back to A21O with AGESA 1.2.0.1.
Literally killed my 5950x in stability and performances 
Terrible scores in everything, Linpack choking like hell.
GB5 MT 200 points less almost, 200-300 less in CB R23, CPU-z scores inconsistent.
Perfect CO setup failing in CoreCycler... too much.
No improvement with FCLK 2033, even worse.

I'll try again with A21O but I have repeated again CPU-z when I rolled back.
Core 1 compared to Core 4 lost only 8 points... not sure it's worth the hassle.

Didn't check DF C-State on 1.2.0.3; but on 1.2.0.1 if it's Disabled it's unstable.
Got a couple of reboots while testing with GB5 and Prime.

The VR 12VIN OCP expander it's killing the scores, at least with AGESA 1.2.x
Used it before and didn't notice issues, something changed.

Yes I have to still mess with PMU training and MSI latency enhance.
Maybe now it's the right time 



domdtxdissar said:


> That screen was from static 4500 mhz
> Full post with numbers from static 4500mhz @ 6, 8, 12 and 16 cores here:
> 
> Iam talking about difference between benchmode 3GB and extended 8GB.
> 8GB scores higher


Yes and I've also seen it, sorry 
I was interested in what PBO could give with better cooling.
Can't run it at 4.5 GHz static, too much heat for me....


----------



## ManniX-ITA

mongoled said:


> Now to try the GTX960 in the PCIe chipset slot...


Yes, I couldn't test it but seems running PCIe 4 GPUs above 1900 is increasingly hard and impossible over 2000.
Have only a GTX 1070 and a GTX 960 here, no changes in this regard.

Let us know!


----------



## domdtxdissar

ManniX-ITA said:


> I was interested in what PBO could give with better cooling.
> Can't run it at 4.5 GHz static, too much heat for me....


Quick and dirty PBO CO -30 allcore









Only 627 Gflops but its too hot bench here now..


----------



## ManniX-ITA

domdtxdissar said:


> Only 627 Gflops but its too hot bench here now..


Thanks same result!
Too hot here as well...


----------



## mongoled

Lolz at the two last posts ^^^

In that case its always too hot where I am 

😂😂


----------



## Taraquin

ManniX-ITA said:


> Yes, I couldn't test it but seems running PCIe 4 GPUs above 1900 is increasingly hard and impossible over 2000.
> Have only a GTX 1070 and a GTX 960 here, no changes in this regard.
> 
> Let us know!


Hmm, my 3060ti runs fine both at pcie 3.0 and 4.0 even at 4066/2033.


----------



## mongoled

Taraquin said:


> Hmm, my 3060ti runs fine both at pcie 3.0 and 4.0 even at 4066/2033.


We know you have a magic motherboard, it does not count


----------



## ManniX-ITA

Taraquin said:


> Hmm, my 3060ti runs fine both at pcie 3.0 and 4.0 even at 4066/2033.


Nice to know, thanks!
Hopefully one day I'll be able to test myself...


----------



## craxton

Veii said:


> Check this, but it's in Korean ~ Thread *C*
> Just scroll down
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> One thing that is not clear to me is the pbo limits. I have seen gamernexus set these to motherboard limits, which are way beyond what the FUSE limits are. Assuming Fuse limits are indeed a thing, then why are people talking about different settings for TDP,PPT,EDC? You could set set everything...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> Google Translate is not soo good with korean


google translate actually worked really well on the page.
unless i have no idea that its getting so many words wrong but making them sound right...

thank you i ened up passing out on this at 9am this morning and now its noon lol 
will continue in on this,


----------



## craxton

mirzet1976 said:


> Here
> 
> View attachment 2512883


are these dual rank? 
why are you running a tad faster than i?

did you have all sorts of tasks killing???? 
thankyou for posting now i regret it bc i should NOT be slower than you


----------



## craxton

KedarWolf said:


> View attachment 2512885


PFFT showing off lol
im in the 6 class range- not having issues hanging to my knees lmao...

i can only imagine the hair pulling this has given you....


----------



## Taraquin

mongoled said:


> We know you have a magic motherboard, it does not count


It's dirt cheap, maybe the lack of features that can interfere is the key


----------



## Taraquin

ManniX-ITA said:


> Nice to know, thanks!
> Hopefully one day I'll be able to test myself...


Luck + cheap MB with very few features might be the reason? Few things that can go wrong if you have few things, haha. I got a ****ty binned ram and gpu so that makes up for good 5600X sample and MB with great ram oc.


----------



## Takla

Dollar said:


> I can reproduce this, it gave me cancer trying to dial in voltages. Thats an ASUS crosshair VI bug that never got fixed. For more fun try sleeping and then waking your system and then go check your vddg/vddp voltages in zentimings to see they have reset to stock values.


Oh well. It only seems to affect AIDA64 anyways. The latency test in Ryzen DRAM Calc always results in ~65.5ns of custom latency, and ~70ns of random latency, no matter if it is a cold boot or a restart.

Edit: These are my stats with SiSoftware Sandra, Processor Inter-Thread Efficiency


Code:


Average Inter-Thread Latency : 53.6ns (7.7ns - 66.0ns)
Inter-Thread (same Core) Latency : 8.0ns
Inter-Core (same Module) Latency : 24.7ns
Inter-Module (same Package) Latency : 62.8ns


----------



## craxton

mirzet1976 said:


> Here
> 
> View attachment 2512883


hmmh hmmmm...nvm i figured out why your so much higher...
\raising SOC IOD or any voltage AT ALL drastically lowered my score...(yes since you posted this ive been trying to 
compensate as thats just what men do) 
and well....this is with the "daily ran" -26 curve i was running (when i was asking why) 
my voltages were so much higher than that of others.... its due to the absurd amount of offset needed to make this remotely windows stable...
gonna check and see if the -7xx offset i ran without curve is any count since i ran that from the start....

(what curve settings are you running?)
it shows hard what curve can do. 
currently trying to decide on a new 5600x or a 4650G possibly 5xxxG chip 
(granted i find one not scalped in price)


----------



## PJVol

mongoled said:


> it's also graphics card related


Back in the agesa 1.2.0.0 days), the first thing i tried was to swap my 5700xt to rx 570 4gb from my office PC (which, if you remember, haven't had any whea running 5600X, at least up to fclk 2000), thinking mostly the same path as you.
Unfortunately, with RX 570 installed, nothing has changed.


----------



## craxton

on this "GPU/WHEA" subject you fellas are speaking on, 
are any of you running a riser cable?
i got a phanteks vertical GPU mount kit sometime ago, 
and have used this riser cable since (if im correct) 
this is the GPU bracket (dont buy this its a nightmare to work with)
unless its directly compatible to your case, which then again,
its universal (modification might happen) my case is huge to which 
its impossible to work in and i dread taking out the GPU more than anything else
considering how it had to be mounted.

anyhow curious to know "IF" this could relate somehow?
as G/N has already shown riser cables can make some differences....
(2070S) is what i run gen switch is auto. id assume its gen 3 as this is what GPU/z says.


----------



## domdtxdissar

domdtxdissar said:


> So have been testing some more with different core amounts in Linpack Extreme 1.1.5 if anyone want to compare settings.
> 
> 5950x @ static 4.5ghz
> 1900:3800 CL14 flat T1 GDM-off
> 4*8GB memory
> Bloaty Windows
> 
> 6 cores = stable 266 Gflops
> View attachment 2512706
> 
> 
> 8 cores = stable 349 Gflops
> View attachment 2512707
> 
> 
> 12 cores = around 500 Gflops "semi-stable", maybe because data is jumping in L3 cache between the CCD's (?)
> View attachment 2512708
> 
> 
> 16 cores = stable 634 Gflops
> View attachment 2512709
> 
> 
> Did also a 16 cores extended 8GB run with HWinfo open while running to check temp etc (~1.188v vcore under load)
> View attachment 2512710
> 
> 
> Not sure if these are good or bad scores, but they seem stable atleast


So i have done a comparison with PBO CO @ ManniX-ITA 

5950x @ PBO CO -30 allcore with LLC auto which is the weakest loadline = highest performance. (asus bios 3003 boosts even better)
1900:3800 CL14 flat T1 GDM-off
4*8GB memory
Bloaty Windows

6 core = 281 Gflops









8 cores = 363 Gflops









12 cores = ~506 Gflops









16 cores = 641 Gflops









----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Did also do some max bench runs.. 

*6 cores = 286 Gflops*









*16 cores = 654 Gflops*









All specified Gflops numbers are for the 3GB benchmark, but i also have included the 8GB benchmark numbers for those who previous did not compare apples to apples numbers..


----------



## mirzet1976

craxton said:


> hmmh hmmmm...nvm i figured out why your so much higher...
> \raising SOC IOD or any voltage AT ALL drastically lowered my score...(yes since you posted this ive been trying to
> compensate as thats just what men do)
> and well....this is with the "daily ran" -26 curve i was running (when i was asking why)
> my voltages were so much higher than that of others.... its due to the absurd amount of offset needed to make this remotely windows stable...
> gonna check and see if the -7xx offset i ran without curve is any count since i ran that from the start....
> 
> (what curve settings are you running?)
> it shows hard what curve can do.
> currently trying to decide on a new 5600x or a 4650G possibly 5xxxG chip
> (granted i find one not scalped in price)
> 
> View attachment 2512931


Bench was on my daily settings, Curve is -26 and for the two best cores -6 and I also had Opera minimized when I run bench. Voltage offset +682


----------



## jomama22

ManniX-ITA said:


> Let me than do as well a call out for 5950x owners to provide their PBO results
> 
> This is the profile I was using yesterday:
> 
> 
> http://imgur.com/a/58BP537
> 
> 
> Now I'm running with A31 and I'm reworking it.
> Too much VDDG CCD voltage made me lost at least 5 counts on Core 1.
> Which is my best core... not acceptable. Lost 12 points in CPU-z.
> I'm trying to find a good voltage combo to keep it at least between -15 and -18.
> Then I'll have to find a way to compensate for the lower CCD voltage.


Here's r20:









And that previous sottr bench was pbo as well.

and linpack:









This is with 3800/1900. Running 4000/2000 shows a significant drop to the same levels you have at 630 or so. So there is definitely a reduction in bandwidth for 2000 fclk (atleast for smu 56.37). How applicable that is to other things like games is questionable. Case being my sottr benchmarks comparing the same memory frequencies.

I imagine that peak throughput is what is being throttled at 4000+ fclk so you will not see a negative effect, rather a beneficial one, when you aren't utilizing a that type of bandwidth (which I can't imagine any game does). 

I would also gander that single ccd chips (5600x/5800x) wouldn't see such a large drop off if only because they don't rely on the IF for core to core communication, which linpack does quite a lot of.

I think, as we kinda already discussed previously. If you are going to be utilizing all cores on a 2ccd cpu for anything heavily reliant on full bandwidth, 3800/1900 makes the most sense. 

For anything else, 2000/4000 is probably the way to go, though that is heavily reliant on whether you can get both the timings tight enough to be clearly advantageous to 3800 and you don't eat away at your pbo boost in the process (aka any soc more that .1v extra you need for 2000 vs 1900).


----------



## craxton

mirzet1976 said:


> Bench was on my daily settings, Curve is -26 and for the two best cores -6 and I also had Opera minimized when I run bench. Voltage offset +682


"best" two cores lol
same goes for me, but one can handle -8 and the other well....+10

right now however, 3 cores are handling -26 while the other 3 (one being -14) the other two
-8 and +10 (short i just applied -26 to the ones that passed core cycler)

while running no offset just allowing amd voltage option inside MSI settings.


----------



## craxton

did you fellas see amd is "selling" 5000 series APU processors 
for DYI instead to prebuilders????

5600G


----------



## CarnageBT

Hi,

Was wondering if someone could PLEASE help me reach stability. 

On membench I can get to 2400% or 100% / thread, no errors. 

Then I moved onto TestMem5 and keep getting errors 2, 12, and 0 all related to voltage. 

I'm new to this but have put in well over 20 hours at this point blindly testing near every iteration I can imagine but can't seem to find the right combo. 
Once I passed 20 cycles on testmem using 1usmus cfg but when I tried it again later, it failed after only 6 cycles. 
*I modified the cycle so it would only test 0, 2, and 12 so I could test voltage quicker. 

Here are my details:
x570 mobo, daisy chain layout
4 dimms of 3600mhz, cl14, samsung b die, 
Trying for stability at 3733 mhz, 1867 fclk, uclk = memclk

Any help is IMMENSELY appreciated. I gave up on 3800 earlier due to single membench errors b/w 300-1000%. I just want to get 3733 stable now. 

Below are pictures with all my details as well as an excel table of the 40 or so itterations of soc, vddp, vddg ccd, cddg iod, and dram voltage I tried. At the end it shows how many cycles were successfully completed before producing the first error.


----------



## ManniX-ITA

jomama22 said:


> This is with 3800/1900. Running 4000/2000 shows a significant drop to the same levels you have at 630 or so. So there is definitely a reduction in bandwidth for 2000 fclk (atleast for smu 56.37). How applicable that is to other things like games is questionable. Case being my sottr benchmarks comparing the same memory frequencies.


Thanks for testing 

I don't think it's a reduction in bandwidth. From 677 GFlops to 630 Gflops is a delta of 47. It's a full core missing.
Reduction in bandwidth would mean either only a bit higher or a bit lower than 677.

I score 618 at 1900 and 627 at 2000; that's the gap i would expect by pure increase or decrease in bandwidth.
Switching to 2033 then I have a drop to 610 GFlops.

This massive negative delta is not reproducible for me in anything else.
Did you try CB R20/R23 or GB5 at FCLK 2000?
You should see same or higher scores than FCLK 1900.

My theory is that at higher FCLK the thermal throttling threshold is lower.
The whole CPU gets throttled more than at lower FCLK, maybe to protect the IF substrate.
That's why I don't think testing FCLK with Linpack is a good method.
It's evidencing a very real problem running at high FCLK but it's not a good way to tell if it works and how good it works.

If you have CLKREQ# in AMD PBS give it a try; works only at 2033 for me but maybe in your case could work at 2000 as well.


----------



## mongoled

CarnageBT said:


> Hi,
> 
> Was wondering if someone could PLEASE help me reach stability.
> 
> On membench I can get to 2400% or 100% / thread, no errors.
> 
> Then I moved onto TestMem5 and keep getting errors 2, 12, and 0 all related to voltage.
> 
> I'm new to this but have put in well over 20 hours at this point blindly testing near every iteration I can imagine but can't seem to find the right combo.
> Once I passed 20 cycles on testmem using 1usmus cfg but when I tried it again later, it failed after only 6 cycles.
> *I modified the cycle so it would only test 0, 2, and 12 so I could test voltage quicker.
> 
> Here are my details:
> x570 mobo, daisy chain layout
> 4 dimms of 3600mhz, cl14, samsung b die,
> Trying for stability at 3733 mhz, 1867 fclk, uclk = memclk
> 
> Any help is IMMENSELY appreciated. I gave up on 3800 earlier due to single membench errors b/w 300-1000%. I just want to get 3733 stable now.
> 
> Below are pictures with all my details as well as an excel table of the 40 or so itterations of soc, vddp, vddg ccd, cddg iod, and dram voltage I tried. At the end it shows how many cycles were successfully completed before producing the first error.
> 
> View attachment 2512987


Nice to hear you have put the work in before coming to ask for help



Firstly, you need to find a set that is stable with GDM disabled and using 2T, that is the first move.

Looking at your current settings these are the things that I would change, they may not work as with GDM enabled it masks all sorts of possible issues.

So I would change the following

vDIMM needs to be raised since you are running CL14, you have it set at 1.46v whats does that give you, ideally for CL14 3733 you want to start with at least 1.52v (get) then work your way down once you have a stable set
Keep flat primaries until you get a stable set so set tRDCRD and tRP to 14
tRC to 42
tRFC/tRFC1/tRFC2 to 294/218/134
tRDRDSC/tRDRDDD to 4
tWRWRSC/tWRWRDD to 6
I would leave tRDWR/tWRRD on AUTO just to see if you can post ok, then see what auto values are set

Let us know if you can post with the above changes


----------



## ManniX-ITA

CarnageBT said:


> I'm new to this but have put in well over 20 hours at this point blindly testing near every iteration I can imagine but can't seem to find the right combo.
> Once I passed 20 cycles on testmem using 1usmus cfg but when I tried it again later, it failed after only 6 cycles.
> *I modified the cycle so it would only test 0, 2, and 12 so I could test voltage quicker.


You could try this:








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


ok, so the boards feeding now, 1.18 but the cpu is actually getting 1.15/16....LLC3 btw MSI LLC that is.. I usually run it like this or a notch below. Since you have an MSI you can cheat with telemetry: The CPU VDD options have a much greater impact than I thought. Much higher MT scores...




www.overclock.net





Not an expert on 4xSR but a bit of advice.
Ditch GDM and use 2T, it's faster and it's not masking errors, you will get more consistent results changing timings. 
GDM is easy but if something is wrong drives you mad.
Avoid Auto setting as much as possible; set everything you can manually.
Especially RTT, ProcODT, CAD, etc
CL14 probably needs a bit more VDIMM than what you tested.


----------



## mongoled

domdtxdissar said:


> All specified Gflops numbers are for the 3GB benchmark, but i also have included the 8GB benchmark numbers for those who previous did not compare apples to apples numbers..


Well its only a few pages back but "we" started to use Linpack Xtreme on @RonLazer suggestions to get baselines for FCLK comparisons not to post our best scores

In this context it was not relevant which test was chosen, just that we use the same one to do our own comparison.

Ive discovered something while tweaking my CO settings which has had a direct effect on increasing the GFlops, here is a new one with exact same settings as the one I previously posted only this time I have gained 4 GFlops.









Basically as I was getting oddities with WHEA 18s while idling and it was happening on the same cores irrespective of the values I was changing, changing the CO values only seemed to make the instability jump between the 3 same cores, if I remember correctly this is the same thing @craxton and @Manni-ITX have been experiencing also.

I remembered something @Veii mentioned about AIDA64 benchmark and that balancing all the cores to the same frequency using boost tester helped to get more consistent results, so thats what I set about doing.

Basically I have slightly tweaked all the cores to hit just over 5000 mhz using boost tested, this resulted in the increase in GFlops and also a similar increase in score is seen across other CPU-Z (both tests) and CB23.

Before normalising the cores 3 of the 6 cores were between 20-40 mhz below the 5000 mhz threshold, I dont believe this frequency difference is enough to explain the increase in scores.

Obviously I have not tested for stability, but I know so far that with the non-normalised core frequencies I was able to trigger WHEA 18s quite easily with boost tester, since normalizing the cores ive had no WHEA 18s but this was a very short test.....


----------



## ManniX-ITA

mongoled said:


> I remembered something @Veii mentioned about AIDA64 benchmark and that balancing all the cores to the same frequency using boost tester helped to get more consistent results, so thats what I set about doing.


Have to try as well someday but with 16 cores.... it's going to be long and equalizing on the worst cores doesn't look good.
But indeed why not giving a chance.

I think Veii suggested to look at the VIDs running TM5; still a light workload but maxing out EDC.


----------



## domdtxdissar

mongoled said:


> Well its only a few pages back but "we" started to use Linpack Xtreme on @RonLazer suggestions to get baselines for FCLK comparisons not to post our best scores
> 
> In this context it was not relevant which test was chosen, just that we use the same one to do our own comparison.


Hmm



RonLazer said:


> *Benchmark:* Linpack Extreme 1.1.5, *with the standard 3Gb test run 5 times*.
> *CPU:* 5600X *4.5GHz*@1.25V SET (LLC 1, droops to 1.2V) - SMT enabled.
> 
> *Why Linpack?*
> It's as close to a "real-world" memory test as any benchmark gets, it will hammer the memory controller AND the CPU so the CCD portion of the infinity-fabric gets hot, *uses fairly representative memory in it's "Standard" benchmark (3Gb of heavy IO is about typical for most games/computational-software) and is multi-threaded*. The problem with Aida64 bandwidth and latency tests is they put absolutely zero strain on the memory controller, Geekbench is too short and too synthetic, and y-cruncher is a fair substitute but is far heavier than any real-world use-case and so only really useful for scoring HWBot points or really proving a point about stability.
> 
> *Why a static Overclock?*
> It stops thermal variation affecting PBO, and allows comparison across different silicon-quality CPUs. Linpack is a very heavy memory benchmark, but still mostly scales with CPU and so without locking the CPU core ratio we'd just be comparing who has the best-binned 5600X. It also isolates the impact of higher SOC power pulling from the PBO power/current budget.


Anyway, i have included both 3GB and 8GB numbers so people can compare what they want.
Have done both Static 4.5ghz OC and PBO CO as requested @ 6, 8, 12 and 16 cores for _my cpu_, and as a bonus ive done a maxbench at the end also.


----------



## mongoled

domdtxdissar said:


> Hmm
> 
> 
> Anyway, i have included both 3GB and 8GB numbers so people can compare what they want.
> Have done both Static 4.5ghz OC and PBO CO as requested @ 6, 8, 12 and 16 cores for _my cpu_, and as a bonus ive done a maxbench at the end also.


I will check to see if there is a difference between 3GB and 8GB on my setup


----------



## domdtxdissar

mongoled said:


> I will check to see if there is a difference between 3GB and 8GB on my setup


There is.. Or atleast there should be


----------



## mongoled

domdtxdissar said:


> There is.. Or atleast there should be


Sorry I should have been more specific, I am not talking about changes in the score but changes in the way different FCLK effects the score.

As I explained prior post it was not about posting the highest scores, that came after by certain peeps

😄 😄


----------



## mongoled

PJVol said:


> Back in the agesa 1.2.0.0 days), the first thing i tried was to swap my 5700xt to rx 570 4gb from my office PC (which, if you remember, haven't had any whea running 5600X, at least up to fclk 2000), thinking mostly the same path as you.
> Unfortunately, with RX 570 installed, nothing has changed.


Yes, many many variables in play.

Moving the GTX960 to the PCIe slot running off the chipset was slightly worse with regards to posting at FCLK 2067, WHEA 19s were the same ..


----------



## Veii

craxton said:


> did you fellas see amd is "selling" 5000 series APU processors
> for DYI instead to prebuilders????
> 
> 5600G


I have my eyes on it since a bit 
Might end up as a gaming CPU at the end
We'll see where they drop, as i would like one


----------



## ManniX-ITA

Veii said:


> I have my eyes on it since a bit
> Might end up as a gaming CPU at the end
> We'll see where they drop, as i would like one


I'm also looking for it...


----------



## mongoled

PJVol said:


> It may be platform specific, but I found that gb3 has a couple of tests that show biggest performance impact on high-fclk config for me. Can you look into gb3 results as well, when comparing?
> They are in the last tab - "memory performance", these *Stream* *Add Multicore* and *Stream Triad* used to drop noticeably at 2000+.
> 
> View attachment 2512449
> 
> 
> One more quick test is aida's FP64 Ray-Trace. On a 24/7 [email protected] config - it reaches 7800-7900, and still can't beat it with 1933+.


Here you go 4133/2067 tweaked PBO (32bit)

Micro-Star International Co., Ltd. MS-7C35 - Geekbench Browser 

Also AIDA64 FP64 Ray-Trace

Have not tested at 3800/1900


----------



## CarnageBT

mongoled said:


> Nice to hear you have put the work in before coming to ask for help
> 
> 
> 
> Firstly, you need to find a set that is stable with GDM disabled and using 2T, that is the first move.
> 
> Looking at your current settings these are the things that I would change, they may not work as with GDM enabled it masks all sorts of possible issues.
> 
> So I would change the following
> 
> vDIMM needs to be raised since you are running CL14, you have it set at 1.46v whats does that give you, ideally for CL14 3733 you want to start with at least 1.52v (get) then work your way down once you have a stable set
> Keep flat primaries until you get a stable set so set tRDCRD and tRP to 14
> tRC to 42
> tRFC/tRFC1/tRFC2 to 294/218/134
> tRDRDSC/tRDRDDD to 4
> tWRWRSC/tWRWRDD to 6
> I would leave tRDWR/tWRRD on AUTO just to see if you can post ok, then see what auto values are set
> 
> Let us know if you can post with the above changes



Thank you for the advice. I've made all the changes you mentioned with the exception, I tried 1T, and have successfully posted. To be clear, I tested a ton, but am a complete novice, and don't' know what I'm doing. Good news, is when I tried for 1T previously, I couldn't get into windows and now I have. AMAZING!

What is the next step? Try for 3800? 4000? lol. I would like the fastest stable OC I can achieve, but gave up on anything above 3733 because I'm so novice and didn't want to be testing for eternity without knowledge of what to try.

edit: got a little too excited there and tried 3800/1900/1:1 with up to 1.57v dram and still couldn't boot. I've reverted to 3733

also forgot to answer your question about the auto settings for tRDWR 9 and tWRRD 4


----------



## RonLazer

ManniX-ITA said:


> Thanks for testing
> 
> I don't think it's a reduction in bandwidth. From 677 GFlops to 630 Gflops is a delta of 47. It's a full core missing.
> Reduction in bandwidth would mean either only a bit higher or a bit lower than 677.
> 
> I score 618 at 1900 and 627 at 2000; that's the gap i would expect by pure increase or decrease in bandwidth.
> Switching to 2033 then I have a drop to 610 GFlops.
> 
> This massive negative delta is not reproducible for me in anything else.
> Did you try CB R20/R23 or GB5 at FCLK 2000?
> You should see same or higher scores than FCLK 1900.
> 
> My theory is that at higher FCLK the thermal throttling threshold is lower.
> The whole CPU gets throttled more than at lower FCLK, maybe to protect the IF substrate.
> That's why I don't think testing FCLK with Linpack is a good method.
> It's evidencing a very real problem running at high FCLK but it's not a good way to tell if it works and how good it works.
> 
> If you have CLKREQ# in AMD PBS give it a try; works only at 2033 for me but maybe in your case could work at 2000 as well.


There's no mechanism for this, and if you check the current for the SOC/CPU you'll see it doesn't change (so no throttling is occuring). What seems to be happening is numerous errors on the GMI link are cropping up, each of which requires correction. How this is done is unclear to me, but I know a guy who is more experienced in CPU architecture who I'll ask. The point is this error correction is extremely wasteful and crushes performance.


----------



## RonLazer

Veii said:


> I have my eyes on it since a bit
> Might end up as a gaming CPU at the end
> We'll see where they drop, as i would like one


Sadly the APUs have 1/2 the L3 cache, which means they lose big time, even clock-for-clock, to their non-APU counterparts. Making things worse still, they don't clock as high no matter how much you tweak them. I think its a result of the thermal concentration from the monolithic die and smaller L3 cache meaning the cores are closer together, soaking heat from the iGPU, and bleeding heat into the IOD as well - so without extreme cooling they can't hit the 4.85-5.05GHz we're used to seeing on Ryzen. 

Sadly as far as I can tell their FCLK scaling isn't quite as dramatic as hoped for either, I've seen 2200MHz but it's not daily-stable as far as I gather, and you'd need to be running 4400MHz with stupidly tight timings only accessible with a solid motherboard and expensive dimms just to get close to a 5600X/5800X - at which point you could just buy the non-APU and some Crucial Ballistix 3600 cl16 and still get better gaming results.


----------



## craxton

Veii said:


> I have my eyes on it since a bit
> Might end up as a gaming CPU at the end
> We'll see where they drop, as i would like one


I found a few on ebay but double retail of course... Engineering samples from what I could figure.


----------



## RonLazer

CarnageBT said:


> Thank you for the advice. I've made all the changes you mentioned with the exception, I tried 1T, and have successfully posted. To be clear, I tested a ton, but am a complete novice, and don't' know what I'm doing. Good news, is when I tried for 1T previously, I couldn't get into windows and now I have. AMAZING!
> 
> What is the next step? Try for 3800? 4000? lol. I would like the fastest stable OC I can achieve, but gave up on anything above 3733 because I'm so novice and didn't want to be testing for eternity without knowledge of what to try.
> 
> edit: got a little too excited there and tried 3800/1900/1:1 with up to 1.57v dram and still couldn't boot. I've reverted to 3733
> 
> also forgot to answer your question about the auto settings for tRDWR 9 and tWRRD 4





CarnageBT said:


> Thank you for the advice. I've made all the changes you mentioned with the exception, I tried 1T, and have successfully posted. To be clear, I tested a ton, but am a complete novice, and don't' know what I'm doing. Good news, is when I tried for 1T previously, I couldn't get into windows and now I have. AMAZING!
> 
> What is the next step? Try for 3800? 4000? lol. I would like the fastest stable OC I can achieve, but gave up on anything above 3733 because I'm so novice and didn't want to be testing for eternity without knowledge of what to try.
> 
> edit: got a little too excited there and tried 3800/1900/1:1 with up to 1.57v dram and still couldn't boot. I've reverted to 3733
> 
> also forgot to answer your question about the auto settings for tRDWR 9 and tWRRD 4


This looks like a very good overclock to me (minus a few minor details), if you go up to 3800MHz you'd likely need to loosen tRCDRD which probably isn't worth the extra 33MHz. You still have some slack though:

tRRDS/tRRDL/tFAW can definitely be set to 4/6/24 or 4/6/16 and you'll see a big boost in bandwidth. 

tWTRL 14 is very loose, you can definitely run 8 on that one. 

Raise tWR to 16, its usually best to keep it at 2x tRTP.

tWRRD should go down to 3 or even 2. 

The tRDRDSC and tWRWRSC timings can be set at 1, I've never seen anyone run them higher than this so I don't even know what effect they have, but I think its would serve as a latency penalty for repeated reads/writes in the same channel so should have some effect. 

I'm impressed your board+dimms do CR 1T without any tweaking of drive strengths. However it might be worth trying to raise ClkDrvStr to 30 or 40 and see if that lets you bring down the DRAM voltage needed to be stable.


----------



## craxton

(curve, -20, -16, -8, +10, -7, - 15) and a negative 25mv with "amd over clocking" been running core-cycler, but fails without the offset......??? On 2 cores (4, 6)


----------



## RonLazer

domdtxdissar said:


> Hmm
> 
> 
> Anyway, i have included both 3GB and 8GB numbers so people can compare what they want.
> Have done both Static 4.5ghz OC and PBO CO as requested @ 6, 8, 12 and 16 cores for _my cpu_, and as a bonus ive done a maxbench at the end also.


Did you duplicate the memory timings too? Because we would expect 263-265 GFlops at 1900 with the timings I used, and you're getting 281 at 4.5GHz which is abnormally high.


----------



## RonLazer

craxton said:


> (curve, -20, -16, -8, +10, -7, - 15) and a negative 25mv with "amd over clocking" been running core-cycler, but fails without the offset......??? On 2 cores (4, 6)


Do you mean it fails without the -25mV offset? It might be because that functionality causes clock-stretching which means you're not actually hitting the peak frequencies you were without it so the cores aren't getting into their unstable voltage:frequency region.

It's important people understand the difference between Curve-Optimiser and Vcore offsets. CO actually modifies the VID tables for each core, so it's targeting a lower voltage at every point on the frequency curve, and it does so in some curve (we don't know if its linear or fitted to the expected response profile) so that each 1 point of offset removes -5mV of Vcore at idle, and -3mV at 100% load. This matches the typical scaling of transistors, they can tolerate slightly higher undervolts for low current workloads (which are more cache heavy typically) than for high current workloads (which utilize the FPUs more). 

Vcore offsets do no such thing, they just instruct the VRM to deliver less voltage than requested. That means that the SMU will simply downclock the PLL-clockgen on each CCX to match the supplied voltage. If the voltage was already excessive then that drop will be small (which is why Zen2 undervolting could produce some benefits in highly threaded workloads) but if you're using curve-optimiser then that drop will be quite large. So combining the 2, you're just pulling down the peak frequency. This might be desirable, and I wish AMD allowed us to set a negative boost override (I don't want or need single core boosts to 5.05GHz, it just overheats instantly and clocks back down more aggressively, limiting the boost behaviour would be desirable here) - but I suspect that's not your goal?


----------



## jomama22

RonLazer said:


> Did you duplicate the memory timings too? Because we would expect 263-265 GFlops at 1900 with the timings I used, and you're getting 281 at 4.5GHz which is abnormally high.


He disabled smt and is using 4750/4600 for that run. Got the same running the same clocks.

Interesting to note that changing ccd2 between 4600 and 4750 (so it was 4750 all core) made no change in the score at all. Seems linpack is very dependent on the speed of a primary thread.


----------



## mongoled

CarnageBT said:


> Thank you for the advice. I've made all the changes you mentioned with the exception, I tried 1T, and have successfully posted. To be clear, I tested a ton, but am a complete novice, and don't' know what I'm doing. Good news, is when I tried for 1T previously, I couldn't get into windows and now I have. AMAZING!
> 
> What is the next step? Try for 3800? 4000? lol. I would like the fastest stable OC I can achieve, but gave up on anything above 3733 because I'm so novice and didn't want to be testing for eternity without knowledge of what to try.
> 
> edit: got a little too excited there and tried 3800/1900/1:1 with up to 1.57v dram and still couldn't boot. I've reverted to 3733
> 
> also forgot to answer your question about the auto settings for tRDWR 9 and tWRRD 4


Im glad you are happy, though it would be better that you follow the advice as its given then rather do your own thing, that is, if you are wanting advice!

Otherwise, fire away and do what ever you want



So....... if you want to follow you need to be careful to do exactly whats asked and not change things that did not need to be changed.

RonLazer already pointed out one of those changes you made which was not requested.

I missed that you had tRP set to 8, change this to 7.

Also, it was not by chance that I requested you run 2T, if you want to corrupt your OS/data keep using 1T, the whole point of giving you guidance is to assist you to find a baseline for a stable set.

That is going to take a while to work out, just posting and getting into Windows does not mean it is a stable set.

So I urge you to go back to your first request for help, look at the TM5 you showed us and look at the things you changed that were not requested.

You also have not change the tRFC/tRFC2/tRFC4 settings ....

The choice is yours


----------



## PJVol

mongoled said:


> Also AIDA64 FP64 Ray-Trace


Thanks, although without comparing they're not of much use. Wondering, why it shows 4700Mhz clock in FP64 test ... or were you running it with fixed clock?


----------



## mongoled

PJVol said:


> Thanks, although without comparing they're not of much use. Wondering, why it showed 4700Mhz clock in FP64 test ... or you were running it with fixed clock?


I think I know whats going on with that AIDA64 FPU test, each time I run it the frequency it runs at is different hence the difference in score!

I am using PBO, when it shows 4850 mhz on a run it scores just over 7800, obviously anything lower and the score tanks.

Not a reliable way to test with PBO enabled!


----------



## ManniX-ITA

RonLazer said:


> There's no mechanism for this, and if you check the current for the SOC/CPU you'll see it doesn't change (so no throttling is occuring). What seems to be happening is numerous errors on the GMI link are cropping up, each of which requires correction. How this is done is unclear to me, but I know a guy who is more experienced in CPU architecture who I'll ask. The point is this error correction is extremely wasteful and crushes performance.


I'm not convinced at all, it's not a valid metric IMHO on Ryzen. Maybe on the Intel CPU.
If you remove limits on a 5950x it can consume over 300W PPT, 400A EDC and draw an astonishing amount of AC power but deliver miserable performances; because it's throttling internally.
Set with the limits at half what was consuming unlimited will draw half the AC power and scores much better.
Same thing with the 3800x had before; you can't understand if it's throttling looking at the power metrics and you can't predict the IPC throughput.


----------



## RonLazer

ManniX-ITA said:


> I'm not convinced at all, it's not a valid metric IMHO on Ryzen. Maybe on the Intel CPU.
> If you remove limits on a 5950x it can consume over 300W PPT, 400A EDC and draw an astonishing amount of AC power but deliver miserable performances; because it's throttling internally.
> Set with the limits at half what was consuming unlimited will draw half the AC power and scores much better.
> Same thing with the 3800x had before; you can't understand if it's throttling looking at the power metrics and you can't predict the IPC throughput.


I've never seen a 5950X hit 300W PPT except on LN2. You can set those values in BIOS sure, but if you look at the VRM telemetry it's not actually the power draw being used. And I've checked this with socket power measurement devices. 

I'm really unclear how a CPU could be pulling more current but clocking lower, where is the current going? I'm not saying you're wrong on this, I'm just extremely confused because it seems to violate some fundamentals of electrical theory.


----------



## ManniX-ITA

RonLazer said:


> I'm really unclear how a CPU could be pulling more current but clocking lower, where is the current going? I'm not saying you're wrong on this, I'm just extremely confused because it seems to violate some fundamentals of electrical theory.


Don't ask me, ask AMD 
When I got the 5950x did some tests to find good limits with AORUS Master and I managed to pull 416A EDC and around 300W PPT, not sure exactly how much.
But that's why I started using 280W as my PPT value so it was around there.
Still with that obscene amount of power draw, I think around 600W AC, the scores were abysmal; just a bit better than the TDP 105W settings.
I would have thought the metrics were fake, sometimes they are, but the staggering AC power draw can't be faked.


----------



## jomama22

RonLazer said:


> I've never seen a 5950X hit 300W PPT except on LN2. You can set those values in BIOS sure, but if you look at the VRM telemetry it's not actually the power draw being used. And I've checked this with socket power measurement devices.
> 
> I'm really unclear how a CPU could be pulling more current but clocking lower, where is the current going? I'm not saying you're wrong on this, I'm just extremely confused because it seems to violate some fundamentals of electrical theory.


Different instruction sets utilize different parts of a core more or less effectively depending on the branching used by zen 3. You can absolutely utilize more resources of a core, which inturn uses more power, generates more heat, and cause clock speeds (specifically pbo) to drop. Pbo is definitely hooked into branch and instruction prediction done by the pipeline to determine clockspeed and voltage. Avx and fma are purpose built to maximize core utilization (so long as the branch prediction and instruction sets of the cpu allow for it).

Probably easier to look at it like comparing graphics api's for gpus. Think of dtm style (like mantle was) compared to direct3d (though it's getting better) where using a dtm allows a wider utilization of each sp if both were used for the same game.

That all goes out the window anyhow if you just slap an all-core on it with higher voltage and have the capacity to cool it. You can easily get over 300w if you wanted.


----------



## RonLazer

ManniX-ITA said:


> Don't ask me, ask AMD
> When I got the 5950x did some tests to find good limits with AORUS Master and I managed to pull 416A EDC and around 300W PPT, not sure exactly how much.
> But that's why I started using 280W as my PPT value so it was around there.
> Still with that obscene amount of power draw, I think around 600W AC, the scores were abysmal; just a bit better than the TDP 105W settings.
> I would have thought the metrics were fake, sometimes they are, but the staggering AC power draw can't be faked.


Jesus Christ, that's insane. 

OK I have to be do my due diligence, extraordinary claims require extraordinary evidence after all! Can you show me a HWInfo shot with the SVI2 Power measurement hitting these high values? I don't want this to come across like me interrogating you, I just cannot wrap my head around a Ryzen CPU using that much power without throttling on anything bar LN2/Dice!


----------



## RonLazer

jomama22 said:


> Different instruction sets utilize different parts of a core more or less effectively depending on the branching used by zen 3. You can absolutely utilize more resources of a core, which inturn uses more power, generates more heat, and cause clock speeds (specifically pbo) to drop. Pbo is definitely hooked into branch and instruction prediction done by the pipeline to determine clockspeed and voltage. Avx and fma are purpose built to maximize core utilization (so long as the branch prediction and instruction sets of the cpu allow for it).
> 
> Probably easier to look at it like comparing graphics api's for gpus. Think of dtm style (like mantle was) compared to direct3d (though it's getting better) where using a dtm allows a wider utilization of each sp if both were used for the same game.
> 
> That all goes out the window anyhow if you just slap an all-core on it with higher voltage and have the capacity to cool it. You can easily get over 300w if you wanted.


Yes I'm aware there are native AVX offsets and clock-targeting based on branch-prediction, but if we're comparing identical workloads (Linpack Extreme 1.1.5 which has been optimised for AMD) in this case, which uses AVX2, and we're seeing near-identical current draw at two different FCLK settings, then it can't be SMU throttling since that would result in lower load, and hence lower VRM current output. 

And yeh, an all-core overclock disables all SMU power management features, which is how I do my FCLK testing anyway, so we know for a fact it can't be throttling behaviour and has to be a different mechanism. I know people are saying that benchmarks like Cinebench and Tomb Raider don't see the latency penalty, probably because they don't actually use much bandwidth and results of calculations don't overflow L3, so even if an error is detected correcting it is simple, the data is just retrieved from L3 again with a minor performance hit which is overcome by the higher link speed. It's when the CPU is being hit with memory-intensive workloads that we'd see L3 overflow and hence corrupted data would have to be totally recalculated from scratch. That chain of events is huge, hence why performance craters.


----------



## PJVol

mongoled said:


> I am using PBO, when it shows 4850 mhz on a run it scores just over 7800, obviously anything lower and the score tanks.


It's something beyond my understanding )) Never have seen anythinig like that. Here is a couple of my results - with PBO Boost +200 its always 4850 shown, whether it membench or some other test:


----------



## jomama22

RonLazer said:


> Yes I'm aware there are native AVX offsets and clock-targeting based on branch-prediction, but if we're comparing identical workloads (Linpack Extreme 1.1.5 which has been optimised for AMD) in this case, which uses AVX2, and we're seeing near-identical current draw at two different FCLK settings, then it can't be SMU throttling since that would result in lower load, and hence lower VRM current output.
> 
> And yeh, an all-core overclock disables all SMU power management features, which is how I do my FCLK testing anyway, so we know for a fact it can't be throttling behaviour and has to be a different mechanism. I know people are saying that benchmarks like Cinebench and Tomb Raider don't see the latency penalty, probably because they don't actually use much bandwidth and results of calculations don't overflow L3, so even if an error is detected correcting it is simple, the data is just retrieved from L3 again with a minor performance hit which is overcome by the higher link speed. It's when the CPU is being hit with memory-intensive workloads that we'd see L3 overflow and hence corrupted data would have to be totally recalculated from scratch. That chain of events is huge, hence why performance craters.


Very possible, referring to the latter part. But that's just where I suggested it depends on what workload you are using for what fclk makes sense to use. 

Identifying the throttling would be difficult to detect unless we were able to look at microsecond power intervals of the smu itself. I imagine the algos used for such operate so quickly that somthing like hwinfo isn't going to pickup on. But again, this was merely a suggestion that may be happening.


----------



## Taraquin

RonLazer said:


> Sorry for the delay, had some real work to do, but I finished my testing, I'll explain my methodology a bit first though.
> 
> *OS:* Windows 20H2 x64. It's my Bench OS so it's quite lightweight. I used @ManniX-ITA High-Performance Power plan.
> *CPU:* 5600X [email protected] SET (LLC 1, droops to 1.2V) - SMT enabled.
> *BIOS:* Spread Spectrum: disabled, Global C-States: enabled, PLL/1P8 Voltage locked to 2V, DFE/FFE training enabled.
> *Memory:* See Zentimings in screenshot, had to adjust the DRAM and SOC voltages as I increased frequency.
> *Benchmark:* Linpack Extreme 1.1.5, with the standard 3Gb test run 5 times.
> View attachment 2512597
> 
> *Why Linpack?*
> It's as close to a "real-world" memory test as any benchmark gets, it will hammer the memory controller AND the CPU so the CCD portion of the infinity-fabric gets hot, uses fairly representative memory in it's "Standard" benchmark (3Gb of heavy IO is about typical for most games/computational-software) and is multi-threaded. The problem with Aida64 bandwidth and latency tests is they put absolutely zero strain on the memory controller, Geekbench is too short and too synthetic, and y-cruncher is a fair substitute but is far heavier than any real-world use-case and so only really useful for scoring HWBot points or really proving a point about stability.
> 
> *Why a static Overclock?*
> It stops thermal variation affecting PBO, and allows comparison across different silicon-quality CPUs. Linpack is a very heavy memory benchmark, but still mostly scales with CPU and so without locking the CPU core ratio we'd just be comparing who has the best-binned 5600X. It also isolates the impact of higher SOC power pulling from the PBO power/current budget.
> 
> *Why GearDownMode?*
> This means we're not fiddling with CAD setups etc. to stabilize our respective overclocks - which will impact performance. Feel free to adjust drive-strengths/ProcODT/RTTs to match your boards/dimms impedances, they won't dramatically affect the results. I can't even run CR 1T at 3800 with my 4x8gb kit, and Linpack doesn't particularly care about latency in isolation anyway.
> 
> *What about the SOC-derived voltages?*
> Feel free to tune SOC/CCD/IOD/VDDP/PLL to match your CPU, I just didn't want to get bogged down in fine-tuning these to squeeze out the last few % when the goal is to show and compare qualitative trends. I just used ballpark values I know have worked in the past. The timings are not very tight at all, because I didn't want this to be a comparison of memory controllers, but instead of the infinity fabric link itself.
> 
> As both the memory/CPU overclock are quite mild, in theory anyone can try and replicate this, including those with 5900X or 5950X's by disabling the 2nd CCD and limiting the number of active cores in the BIOS.
> 
> Here is the full graph from 1800MHz to 2033MHz:
> View attachment 2512596
> 
> The drop-off is obviously distorting the scale so let's remove 2033MHz:
> View attachment 2512598
> 
> Not quite sure what happened at 1933MHz, it even failed to POST a few times so I think I have a weak "FCLK hole" at that frequency on my CPU. The overall trend seems to basically show what I claimed initially - that FCLK equalization mechanism stops functioning properly after 1900MHz. The actual memory performance under load is barely increasing beyond 1900MHz, despite the fact that the timings are constant so we should see a rise in throughput solely on the memory side, the infinity fabric link is clearly bottlenecking the memory performance. As far as I've been able to tell, speeds over 1900MHz are basically just for show, or very very light workloads. I've observed this same behavior in multiple benchmarks before, this is the first time I've properly collected the data on it.
> 
> Here is my screenshot for the 2033MHz run:
> View attachment 2512599
> 
> You can literally see the performance dropping off as the CPU gets further into the benchmark, and the data-fabric and IOD get hotter, and hence less stable. This is why brief "bursty" benchmarks like Aida64 are insufficient, they don't actually push the CPU at all so instability doesn't kick in hard enough to manifest as performance degradation.
> 
> I'd like to see some people try and replicate these tests (should be pretty easy for anyone with 4 sticks of B-die) and a Zen3 CPU. This will allow us to compare and see if the performance stagnation kicks in at 1933MHz for everyone, and if the sharp drop-off at 2033MHz is also a universal feature. A few tips to improve reproducibility:
> 
> 1. Start with a single 2gb run first to "wake up the CPU". If you don't then the first loop will be slower than the others. I assume this is due to scheduler behaviour, could also be core parking.
> 2. Close all background processes, ideally run in Windows 10 Diagnostic Mode.
> 3. If a run is anomalously low, reboot and try again. Memory training is super variable and boot-to-boot variation can sometimes be larger than changes in timings/frequency/voltages.
> 
> *Working Conclusion?*
> I'd like to see more results, but I strongly suspect the optimal fclk frequency for pragmatic daily usage really is 1900Mhz and no amount of fiddling is going to fix this. If there was a magic setting in the CBS that fixed all the issues and unlocked the full potential of higher clocked memory with no risks or downsides - why haven't AMD just turned it on for us?
> 
> Also if there was, someone would have found it by now. I've tried almost all of them, some of them help a little, nothing actually changes this overall trend. You can definitely hack together a BIOS config that will spit out excitingly low latency numbers, but as soon as your CPU gets hot it will probably crumple, and even if it doesn't - are the gains really worth the extra strain you're putting on your CPU with the higher SOC voltages? Probably not.


Marginal perf-regression with 4000cl16 vs 3800cl16 (2%), CPU at [email protected] But I get 2.3% higher fps in shadow of the tomb raider with 4000cl16 vs 3800cl15 so I keep 4000cl16.


----------



## jomama22

Taraquin said:


> Marginal perf-regression with 4000cl16 vs 3800cl16 (2%), CPU at [email protected] But I get 2.3% higher fps in shadow of the tomb raider with 4000cl16 vs 3800cl15 so I keep 4000cl16.
> View attachment 2513022
> View attachment 2513023


Don't think the regression really shows itself much on the 1ccd chips. Seems to be 2ccd is necessary for the larger drops.


----------



## ManniX-ITA

RonLazer said:


> OK I have to be do my due diligence, extraordinary claims require extraordinary evidence after all! Can you show me a HWInfo shot with the SVI2 Power measurement hitting these high values? I don't want this to come across like me interrogating you, I just cannot wrap my head around a Ryzen CPU using that much power without throttling on anything bar LN2/Dice!


Unfortunately I didn't take a screenshot at the time.

But I think this was the AC peak:










I only have an HWInfo screenshot from 2 days later were you can see how easy is to peak 230W PPT with 245A EDC.
Reaching around 300W with 400A EDC was quite easy especially at the beginning with the first AGESA releases, there were much less protections:


----------



## CarnageBT

mongoled said:


> Im glad you are happy, though it would be better that you follow the advice as its given then rather do your own thing, that is, if you are wanting advice!
> 
> Otherwise, fire away and do what ever you want
> 
> 
> 
> So....... if you want to follow you need to be careful to do exactly whats asked and not change things that did not need to be changed.
> 
> RonLazer already pointed out one of those changes you made which was not requested.
> 
> I missed that you had tRP set to 8, change this to 7.
> 
> Also, it was not by chance that I requested you run 2T, if you want to corrupt your OS/data keep using 1T, the whole point of giving you guidance is to assist you to find a baseline for a stable set.
> 
> That is going to take a while to work out, just posting and getting into Windows does not mean it is a stable set.
> 
> So I urge you to go back to your first request for help, look at the TM5 you showed us and look at the things you changed that were not requested.
> 
> You also have not change the tRFC/tRFC2/tRFC4 settings ....
> 
> The choice is yours


Sorry, I can get a bit carried away. I really appreciate the help and understand the methods and steps need to be followed in a certain order as they will inform an experienced person what has gone wrong along the way.

I changed tRTP to 7 (that's what you meant right? not tRP which is currently at 14)
set 2T mode
Set tRFC to 294 (missed this earlier, unintentional). I don't know how to set tRFC1/2/4, they are greyed out, just lets me modify a single value for tRFC1/2/4

Unsure of what you mean by the TM5 changes vs those shown in my first post; it was written as a did it, chronologically, so the testing was done after the top summary. sorry, it was not clear. my current settings will all be shown in the attached screenshot. If you'd like me to change anything, let me know and I'll do so.

Otherwise, what is the next step?


----------



## CarnageBT

RonLazer said:


> This looks like a very good overclock to me (minus a few minor details), if you go up to 3800MHz you'd likely need to loosen tRCDRD which probably isn't worth the extra 33MHz. You still have some slack though:
> 
> tRRDS/tRRDL/tFAW can definitely be set to 4/6/24 or 4/6/16 and you'll see a big boost in bandwidth.
> 
> tWTRL 14 is very loose, you can definitely run 8 on that one.
> 
> Raise tWR to 16, its usually best to keep it at 2x tRTP.
> 
> tWRRD should go down to 3 or even 2.
> 
> The tRDRDSC and tWRWRSC timings can be set at 1, I've never seen anyone run them higher than this so I don't even know what effect they have, but I think its would serve as a latency penalty for repeated reads/writes in the same channel so should have some effect.
> 
> I'm impressed your board+dimms do CR 1T without any tweaking of drive strengths. However it might be worth trying to raise ClkDrvStr to 30 or 40 and see if that lets you bring down the DRAM voltage needed to be stable.


Thanks very much for the advice. I'll keep these in mind as I systematically go through the changes mongoled suggests


----------



## RonLazer

ManniX-ITA said:


> Unfortunately I didn't take a screenshot at the time.
> 
> But I think this was the AC peak:
> 
> View attachment 2513025
> 
> 
> I only have an HWInfo screenshot from 2 days later were you can see how easy is to peak 230W PPT with 245A EDC.
> Reaching around 300W with 400A EDC was quite easy especially at the beginning with the first AGESA releases, there were much less protections:
> 
> View attachment 2513026


Yeh 230W is about what I've managed to get with maxed out settings, and it was already hitting 90C then, same as yours. If it was possible to hit 300W then it would for sure trigger over-thermal protections. I've actually managed to do that before on just PBO with Linpack Extreme 8Gb test, and I had HWinfo logging which showed it going to 242W as the last sensor reading before it shut down. This is with a water loop and 280mm radiator, so decent cooling. I'm not sure how to explain your AC reading, did you have a power-hungry GPU plugged in that might have triggered some brief load? I ask because I used a GT 710 with power limits on when testing just to prevent this scenario. 

This discussion is interesting as a separate point, but returning to the core issue of performance degradation with higher FCLK values, I still want to be clear that the evidence simply isn't there for a CPU throttling mechanism being applied for higher FCLK values, even if you could prove that there exists some way to create a load that draws higher current despite throttling (reason is that the VRM needs a load for electrons to pass through the power stage, you can't just create a current out of thin air) - it still doesn't have any technical basis. Remember my tests were with a static overclock, the SMU's ability to throttle cores is disabled in this mode since the PLL-clockgen is set to a static frequency. I have some AMD whitepapers on the topic that I'd love to share but sadly they're not publicly available so the best I can do (since I didn't sign an NDA to get them) is explain how Zen cores modulate their respective clocks from a circuit-design perspective - if you're still not persuaded.


----------



## domdtxdissar

RonLazer said:


> Did you duplicate the memory timings too? Because we would expect 263-265 GFlops at 1900 with the timings I used, and you're getting 281 at 4.5GHz which is abnormally high.


I'm getting 266 Gflops at 4.5ghz static with 6 cores enabled

Same memory settings for every run.









3GB numbers
6 cores at 4.5ghz static OC = 266 Gflops
6 cores at PBO CO -30 = 281 Gflops
6 cores maxed (static 4.85ghz) = 286 Gflops

8GB extended numbers
6 cores at PBO CO -30 = 283 Gflops
6 cores maxed (static 4.85ghz) = 287 Gflops



jomama22 said:


> He disabled smt and is using 4750/4600 for that run. Got the same running the same clocks.


No all runs was with HT enabled, and i think he is talking about the 6 cores numbers which was run at settings above.



jomama22 said:


> Interesting to note that changing ccd2 between 4600 and 4750 (so it was 4750 all core) made no change in the score at all. Seems linpack is very dependent on the speed of a primary thread.


Found exactly the same.. Score is highly depended on main CCD clock speed.
Could run 16 cores @ 4800/4625 in the 3GB bench which wound give me ~655-658 Gflops numbers but not stable in 8GB benchmark. (crash or invalid result)



RonLazer said:


> I've never seen a 5950X hit 300W PPT except on LN2. You can set those values in BIOS sure, but if you look at the VRM telemetry it's not actually the power draw being used. And I've checked this with socket power measurement devices.
> 
> I'm really unclear how a CPU could be pulling more current but clocking lower, where is the current going? I'm not saying you're wrong on this, I'm just extremely confused because it seems to violate some fundamentals of electrical theory.


This is one of my old runs from january this year when i was using bios 3003 and PBO CO, 1 hour sustained ~300watt workload on my everyday waterloop setup









Look at uptime in HWinfo and average numbers..
68mins @ average PPT 268 watt
Had PPT 300watt limit set in bios, without i would had way higher spikes.

Below we have *suicide run* with waterloop radiator hanging out the window (*i live north of the arctic circle *)


----------



## ManniX-ITA

RonLazer said:


> I'm not sure how to explain your AC reading, did you have a power-hungry GPU plugged in that might have triggered some brief load?


It's a GTX 1070 and it was in idle at the time.
Was using the benching install so nothing in background.



RonLazer said:


> Remember my tests were with a static overclock, the SMU's ability to throttle cores is disabled in this mode since the PLL-clockgen is set to a static frequency.


Why do you think only the SMU can throttle the CPU?
From my understanding about the, rather scarce, AMD explanations about how advanced is Ryzen in measuring and controlling those thousands of in-die sensors it's only one of the possibilities.
Probably Hallock, in one one of the QA sessions, bragged about how complex all this was and that it's not all centralized.
He referred specifically to the latency of gathering and computing all this data.
It could be too late in some cases to wait for a central directive, therefore some parts of the die can take emergency decisions, eg. throttling, independently.
It maybe not directly throttling the Core but something else which is feeding it with the same result.


----------



## mongoled

CarnageBT said:


> Sorry, I can get a bit carried away. I really appreciate the help and understand the methods and steps need to be followed in a certain order as they will inform an experienced person what has gone wrong along the way.
> 
> I changed tRTP to 7 (that's what you meant right? not tRP which is currently at 14)
> set 2T mode
> Set tRFC to 294 (missed this earlier, unintentional). I don't know how to set tRFC1/2/4, they are greyed out, just lets me modify a single value for tRFC1/2/4
> 
> Unsure of what you mean by the TM5 changes vs those shown in my first post; it was written as a did it, chronologically, so the testing was done after the top summary. sorry, it was not clear. my current settings will all be shown in the attached screenshot. If you'd like me to change anything, let me know and I'll do so.
> 
> Otherwise, what is the next step?
> 
> View attachment 2513034


Apologies, you correctly amended tRP to tRTP and what I meant to say was compare your ZenTimings screenshots to see what you accidentally changed.

Regards tRFC settings, I'm not familiar with your motherboard, is there not a setting to take tFRC off auto?

On my motherboard I can input all three separately, but if I accidentally type the tRFC value into the first box then I won't be able to input the other two timings. Maybe that's what you are doing incorrectly.

tRDRDSC/tWRWRSC should be set to 1.

Everything else is good.

Report back re tRFC

😊


----------



## CarnageBT

mongoled said:


> Apologies, you correctly amended tRP to tRTP and what I meant to say was compare your ZenTimings screenshots to see what you accidentally changed.
> 
> Regards tRFC settings, I'm not familiar with your motherboard, is there not a setting to take tFRC off auto?
> 
> On my motherboard I can input all three separately, but if I accidentally type the tRFC value into the first box then I won't be able to input the other two timings. Maybe that's what you are doing incorrectly.
> 
> tRDRDSC/tWRWRSC should be set to 1.
> 
> Everything else is good.
> 
> Report back re tRFC
> 
> 😊


Thanks for clarifying how to set tRFC settings. Got everything set. What's next?

*The auto settings for tRDWR and tWRRD are 9 and 4 respectively (those are changed from my original zentimings picture)


----------



## jomama22

mongoled said:


> Apologies, you correctly amended tRP to tRTP and what I meant to say was compare your ZenTimings screenshots to see what you accidentally changed.
> 
> Regards tRFC settings, I'm not familiar with your motherboard, is there not a setting to take tFRC off auto?
> 
> On my motherboard I can input all three separately, but if I accidentally type the tRFC value into the first box then I won't be able to input the other two timings. Maybe that's what you are doing incorrectly.
> 
> tRDRDSC/tWRWRSC should be set to 1.
> 
> Everything else is good.
> 
> Report back re tRFC
> 
> 😊


That was the most annoying thing about the msi ace I had lol


----------



## domdtxdissar

Nevermind, better to gather everything in one post above


----------



## KedarWolf

Shouldn't this be quite highly binned. Is b-die. 2x16GB.

G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 4266 (PC4 34100) Intel XMP 2.0 Desktop Memory Model F4-4266C17D-32GTRGB










G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4266 (PC4 34100) Desktop Memory Model F4-4266C17D-32GTRGB - Newegg.com


Buy G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4266 (PC4 34100) Desktop Memory Model F4-4266C17D-32GTRGB with fast shipping and top-rated customer service. Once you know, you Newegg!




www.newegg.ca





DDR4 4266 (PC4 34100)
Timing 17-18-18-38
CAS Latency 17
Voltage 1.50V
Edit: Saw some on the Intel forums that said it'll only do 3733 on a Z590 board which is terrible.


----------



## ManniX-ITA

I'm running with the Royal Z version now, should send it back tomorrow.
Exactly the same as the 4000C16 kit. Except many more LEDs.


----------



## KedarWolf

ManniX-ITA said:


> I'm running with the Royal Z version now, should send it back tomorrow.
> Exactly the same as the 4000C16 kit. Except many more LEDs.


The CL16 4000 kit I had was worse than the CL16 3600 kit I already had. I sent the 4000 kit back.


----------



## ManniX-ITA

KedarWolf said:


> The CL16 4000 kit I had was worse than the CL16 3600 kit I already had. I sent the 4000 kit back


I know... wish I had the same CL16 3600 kit 
Tried a new one and it's not like the older versions... keep it with care.
Same for the 3200 CL14 kit.
They are all like the 4000C16 kit but with a different XMP.


----------



## jomama22

KedarWolf said:


> Shouldn't this be quite highly binned. Is b-die. 2x16GB.
> 
> G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 4266 (PC4 34100) Intel XMP 2.0 Desktop Memory Model F4-4266C17D-32GTRGB
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4266 (PC4 34100) Desktop Memory Model F4-4266C17D-32GTRGB - Newegg.com
> 
> 
> Buy G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 4266 (PC4 34100) Desktop Memory Model F4-4266C17D-32GTRGB with fast shipping and top-rated customer service. Once you know, you Newegg!
> 
> 
> 
> 
> www.newegg.ca
> 
> 
> 
> 
> 
> DDR4 4266 (PC4 34100)
> Timing 17-18-18-38
> CAS Latency 17
> Voltage 1.50V
> Edit: Saw some on the Intel forums that said it'll only do 3733 on a Z590 board which is terrible.


They are most likely referring to gear 1, and that is more heavily dependent on imc and mobo for getting over that hump.

I have the ripjaw version of that same kit (was lucky and picked it up in September for $250). You can look at the timings I get with that as an example of what it can do for us.


----------



## craxton

RonLazer said:


> Sadly the APUs have 1/2 the L3 cache, which means they lose big time, even clock-for-clock, to their non-APU counterparts. Making things worse still, they don't clock as high no matter how much you tweak them. I think its a result of the thermal concentration from the monolithic die and smaller L3 cache meaning the cores are closer together, soaking heat from the iGPU, and bleeding heat into the IOD as well - so without extreme cooling they can't hit the 4.85-5.05GHz we're used to seeing on Ryzen.
> 
> Sadly as far as I can tell their FCLK scaling isn't quite as dramatic as hoped for either, I've seen 2200MHz but it's not daily-stable as far as I gather, and you'd need to be running 4400MHz with stupidly tight timings only accessible with a solid motherboard and expensive dimms just to get close to a 5600X/5800X - at which point you could just buy the non-APU and some Crucial Ballistix 3600 cl16 and still get better gaming results.


How is it these can do "less" than that of 46/4750G on memory clocking? 
I'm not so much "looking" for 4.8/5ghz CPU core oc .. mostly just looking to play around with it myself and maybe use for a secondary rig for the home. As I don't need to buy a dgpu


----------



## craxton

RonLazer said:


> Do you mean it fails without the -25mV offset? It might be because that functionality causes clock-stretching which means you're not actually hitting the peak frequencies you were without it so the cores aren't getting into their unstable voltage:frequency region.
> 
> It's important people understand the difference between Curve-Optimiser and Vcore offsets. CO actually modifies the VID tables for each core, so it's targeting a lower voltage at every point on the frequency curve, and it does so in some curve (we don't know if its linear or fitted to the expected response profile) so that each 1 point of offset removes -5mV of Vcore at idle, and -3mV at 100% load. This matches the typical scaling of transistors, they can tolerate slightly higher undervolts for low current workloads (which are more cache heavy typically) than for high current workloads (which utilize the FPUs more).
> 
> Vcore offsets do no such thing, they just instruct the VRM to deliver less voltage than requested. That means that the SMU will simply downclock the PLL-clockgen on each CCX to match the supplied voltage. If the voltage was already excessive then that drop will be small (which is why Zen2 undervolting could produce some benefits in highly threaded workloads) but if you're using curve-optimiser then that drop will be quite large. So combining the 2, you're just pulling down the peak frequency. This might be desirable, and I wish AMD allowed us to set a negative boost override (I don't want or need single core boosts to 5.05GHz, it just overheats instantly and clocks back down more aggressively, limiting the boost behaviour would be desirable here) - but I suspect that's not your goal?


I tested with what I was told to test with, using benchmate and cpuz setting affinity to _per thread_ and setting threads in cpuz to 1 and running the bench. Both core and thread was hitting 4.85ghz (clock stretching) means one shows x frequency while the other would show higher? Example, (I think you was the one who posted a hwinfo shot of it sometime back) but I've not had this happen. If the core shows 4850, the corresponding thread shows the same frequency upon max load. 
I didn't allow cycler to finish but 15 minutes of the test it ran usually the start it yells at me. Only max frequency was 4750 1ghz less than 4850 (on those two cores) that crashes in the testing.


----------



## RonLazer

craxton said:


> How is it these can do "less" than that of 46/4750G on memory clocking?
> I'm not so much "looking" for 4.8/5ghz CPU core oc .. mostly just looking to play around with it myself and maybe use for a secondary rig for the home. As I don't need to buy a dgpu


Oh they can clock MUCH higher than that, but their FCLK limit isn't much higher than regular chips.


----------



## glnn_23

RonLazer said:


> Oh they can clock MUCH higher than that, but their FCLK limit isn't much higher than regular chips.


My 4650g FCLK was pretty stable at 2266. 
When not running 1:1 the default FCLK was 2200 when pushing high mem clk.
Hoping the 5600g might do better.


----------



## RonLazer

glnn_23 said:


> My 4650g FCLK was pretty stable at 2266.
> When not running 1:1 the default FCLK was 2200 when pushing high mem clk.
> Hoping the 5600g might do better.


Unlikely without good binning luck. The 4600G and 5600G are different only in the single CCX unification of the L3 cache, but both are monolithic dies and have no physical interconnect like the non-APU SKUs


----------



## Veii

RonLazer said:


> Sadly the APUs have 1/2 the L3 cache, which means they lose big time, even clock-for-clock, to their non-APU counterparts. Making things worse still, they don't clock as high no matter how much you tweak them. I think its a result of the thermal concentration from the monolithic die and smaller L3 cache meaning the cores are closer together, soaking heat from the iGPU, and bleeding heat into the IOD as well - so without extreme cooling they can't hit the 4.85-5.05GHz we're used to seeing on Ryzen.
> 
> Sadly as far as I can tell their FCLK scaling isn't quite as dramatic as hoped for either, I've seen 2200MHz but it's not daily-stable as far as I gather, and you'd need to be running 4400MHz with stupidly tight timings only accessible with a solid motherboard and expensive dimms just to get close to a 5600X/5800X - at which point you could just buy the non-APU and some Crucial Ballistix 3600 cl16 and still get better gaming results.


Had anybody played with it to figure out the fabric limits ?
I'm interested in functional APBDIS and functional STAMP ~ for them
This will lower powerdraw quite a bit ~ soo boosting budget should be there where it's at.
I'd be curious if 4.6 is the peak, or they underpromise.
Also still have my eyes on removing this 200Mhz override lock, if AMD doesn't do first ~ as it's a temporary limitation without much value for it's existence, except internal scale-testing
If they don't, CTR 2.1/2 is a valid option for overriding any telemetry locks

An 8 core version should be already cheaper than the 320€ i paid for the 48-50th ryzen retail sample and i expect pretty much equal results (although cache is lower per core, that's true)
They like to pull rabbits out of their hat's, soo maybe Write won't be 16bit limited ~ if this is by any chance the case, then i will outperform the 5600X

We'll see
Sadly the APU is not doing well for KVMs ~ soo i can not use it as a macOS only "optimus" load switching option
Not till that Unix community figures out the patches to rebrand it running on Intel Iris drivers
Soo it very likely will be a low-gaming unit or dual GPU windows setup, lifting render strain from the gaming GPU. Unsure yet

Thunderbolt and Ryzen 5th series have issues which i don't think anybody would resolve at least for the next 6-8 months
Soo my fallback is a 1200AF and a 1700X as an X264/X265 render machine + Audio mixer under UNIX

Unclear yet, but as always ~ these are just toys to explore, learn and publish supportive data.
Have Ballisttix MAX and b-dies here + 3 boards with display out. Haven't decided yet what to use ~ but i need to build the 2nd pc. Procrastinating here
Might push that ProArt as 12nm holding unit, just to deliver me proper Thunderbolt 4 support under win ~ or ignore win and turn it into a hackintosh machine just without pcie CC support 


craxton said:


> (curve, -20, -16, -8, +10, -7, - 15) and a negative 25mv with "amd over clocking" been running core-cycler, but fails without the offset......??? On 2 cores (4, 6)
> 
> 
> 
> RonLazer said:
> 
> 
> 
> It's important people understand the difference between Curve-Optimiser and Vcore offsets. CO actually modifies the VID tables for each core, so it's targeting a lower voltage at every point on the frequency curve, and it does so in some curve (we don't know if its linear or fitted to the expected response profile) so that each 1 point of offset removes -5mV of Vcore at idle, and -3mV at 100% load. This matches the typical scaling of transistors, they can tolerate slightly higher undervolts for low current workloads (which are more cache heavy typically) than for high current workloads (which utilize the FPUs more).
> 
> Vcore offsets do no such thing, they just instruct the VRM to deliver less voltage than requested. That means that the SMU will simply downclock the PLL-clockgen on each CCX to match the supplied voltage.
Click to expand...

Pretty much nails it.
Clock stretching 

One CO is a value of 5mV under idle ~ just sadly it's more into the 4mV range
3mV at full load, is accurate too

20 CO values are already 80mV dropped
Vermeer has a predefined V/F curve, which then is adjusted according to FIT & core Q values
But it will apply a slower Strap, or crash.
I see people heard my "use -30 allcore CO" , and recommend it to random people as "tweaks".
Yet the spread message lost the real meaning, that you have to ! add a bit of positive vcore

Vermeer if it detects a lower frequency strap , will load this - clock will be supplied a different one , a higher one as it thinks it has more boost reserves
Internally IPC to Value Frequency will be screwed by this method. It is on it's core Telemetry faking, but rather internal

IPC real world, to lower clock - does increase that way ~ and programms like CTR will try to apply for example a 5ghz load, instead a 4.85 ghz peak strap ~ reported by SMU. Just crash because it lacks the supplied voltage to run that
Safety limits will be screwed, but it's "negative-clock stretching" , if you do it that way. It's not the positive one where IPC to Set Clock, matches the same number and it just fakes a value "because it misses frequency to run it"

I have to add that relative clock - on CPU Snapshot pooling, is accurate clock
The first read out set clocks will be fake, the moment you start working with CO.
 @craxton i think it was you, this was the "advice" for running TM5 and CPU-Z or Aida - to performance/frequency match it. All-Cores need to run the same highest boost frequency. Else clock stretching is occurring. The natural or the unnatural way thanks to user input
It will indicate which strap it tries to load ~ but IPC vise, they are fake. Either positive or negative fake.

Quoted it to also mention that,
While negative voltage offset
~ pushes the CPU thinking it needs to add more voltage to meet the V/F curve / pretty much increasing the chance of hitting the internal FUSE throttle limits

Positive vcore offset,
~ doesn't do this !

CO will lower VID, and yes will screw fully the V/F curve. But because the CPU attempts to correct it upwards (not really supplying more voltage, but tries running a higher strap)
Technically performance can be better. And voltage will be higher ~ because a higher strap = more voltage. But positive vcore isn't the cause of more supplied voltage !
It does need the positive voltage offset in order to run ~ and then you have to check if it doesn't reach V-TEL llimiters/walls, which need to be increased with the scalar

Positive vcore, is added in post - and FIT doesn't detect it
It only detects if
it's stable at given V/F range,
if it has boosting headroom or does reach FUSE limits
if it exceeds predefined 1.4875-1.55v peaks at X given load type (amperage)

Each of these simplified, do work separated and have no connection together
(soo if you increase positive supplied vcore too high, it *will* *detect* it and throttle back. But it does nott change the V/F curve like CO does)
Keep in mind , there are more than 20 active sensors and 1.55v is not the highest wall ~ it's the current silicon defined wall.

TL;DR
Only running negative CO does screw a bit with the V/F curve.
It's mostly done to balance per core tuning, as FIT will push voltage of these up. Lower global required voltage, higher boost overall
But you need to check a lot how your perf remains, because it will drop like a rock, once it shifts to the slower strap 

And once it drops like a rock, you need to check why ~ was it by lack of voltage or because you reached Telemetry limits
V/F strap is confidential information, same as CO behaviour. The information that is public, is what 1usmus figured out and once stuff is public ~ about it is talking allowed. From people who know, and from Developers who stand under the same NDA
CTR 2.1 with OB (bad name, but it says "over-boost") ~ is build on these fundamentals. How, sadly should not be shared for a good relationship


----------



## KedarWolf

Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 165.45GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.6ns (9.5ns - 59.6ns)
Inter-Thread (same Core) Latency : 9.7ns
Inter-Core (same Module) Latency : 20.7ns
Inter-Module (same Package) Latency : 58.1ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.17GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1613.50MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.77ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 34.40MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 18.9ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.3ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 19.9ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.4ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.0ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.3ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 56.7ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 56.2ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.4ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 56.4ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 57.3ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.2ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 57.5ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 57.6ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.5ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.0ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.3ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 19.9ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.4ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.0ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.3ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.2ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.4ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.3ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.4ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 56.4ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 57.2ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.3ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 57.6ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 57.5ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.0ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.7ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.3ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.0ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.1ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.6ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.6ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 56.3ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 56.3ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.0ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 57.4ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 57.6ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 57.7ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 57.6ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.1ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.7ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 19.0ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 20.6ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 19.4ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.9ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.2ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.1ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 57.7ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 57.1ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 57.5ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 56.5ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 58.6ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 57.2ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.3ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 57.8ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.7ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 22.8ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.3ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 22.3ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 21.0ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 58.0ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 57.8ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 58.2ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.3ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 58.9ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.2ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.7ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.4ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 21.5ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.5ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.8ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.7ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 22.8ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.3ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 22.3ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 21.0ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 58.0ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 57.8ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 58.3ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 57.4ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 58.9ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.2ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 58.6ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.4ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 20.6ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 20.5ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 20.7ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 57.7ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 57.5ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 57.9ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 57.4ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.6ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 57.9ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 58.4ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 58.2ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.8ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 20.0ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.8ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.6ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 20.6ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 20.5ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 20.7ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.6ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.4ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.9ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 57.3ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.6ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.0ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.5ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 58.2ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.6ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.5ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.2ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 58.3ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.8ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.6ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.5ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 59.4ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.4ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 59.0ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.8ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 21.5ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 20.8ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 22.8ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.4ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.5ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.5ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.5ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.2ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 58.3ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 58.0ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.7ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.5ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 59.6ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.4ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 59.1ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.5ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 20.7ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.0ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.0ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.7ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.1ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.1ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.1ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 57.9ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.5ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.0ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 19.9ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.3ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.6ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.7ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.6ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 20.7ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.0ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.0ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.7ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.0ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.1ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 59.1ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 57.9ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.9ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.7ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 21.0ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.8ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.4ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.9ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 57.7ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.4ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 58.5ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.3ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 58.9ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.2ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.3ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 22.4ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.3ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.5ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 20.6ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.7ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 20.7ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.5ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 57.9ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.5ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 57.7ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.3ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 58.3ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.2ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 58.9ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.3ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.8ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.4ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 57.0ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.5ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.0ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.2ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 58.5ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.0ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.1ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.1ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 20.5ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.4ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 20.9ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 20.8ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.7ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.4ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.9ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.3ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 57.1ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.6ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.0ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.1ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 58.4ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.3ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 21.3ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.3ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 22.3ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.0ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.3ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.2ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.6ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 57.4ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 58.2ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 57.5ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 58.6ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.7ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.5ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.3ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.7ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.3ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 21.3ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.3ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 22.3ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.0ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.3ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.2ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 20.2ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.6ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 21.0ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 20.2ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.2ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.1ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.4ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 57.2ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 58.0ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 56.9ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 58.2ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.2ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.3ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.8ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.3ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.7ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 20.3ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.6ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 21.0ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 20.2ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.2ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.1ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.4ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 22.8ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.1ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.1ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.7ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.6ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.6ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 58.3ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.7ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 58.5ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.0ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.3ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.3ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 21.3ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 20.2ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.7ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 22.8ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.1ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.0ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.8ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.5ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 20.4ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 20.1ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 20.2ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.0ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.0ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.9ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 56.9ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.0ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.2ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 57.9ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 57.3ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.6ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 19.7ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.5ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.7ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.5ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 20.4ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 20.1ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 20.3ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.0ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.9ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.6ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.5ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.6ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 59.0ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.5ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 59.2ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.8ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.6ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.5ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 22.1ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 21.1ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 22.8ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.3ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.8ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.1ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.9ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.6ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 20.8ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.1ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.8ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 57.5ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.5ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 57.7ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.9ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 57.8ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.6ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.2ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.1ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.3ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.3ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.3ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.1ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.7ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 20.8ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.1ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 20.7ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.2ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.4ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 59.1ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 58.3ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 59.1ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.2ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.4ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 58.9ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.3ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.2ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.1ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 19.9ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 22.8ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 20.9ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.7ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 20.7ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.2ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.0ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.7ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 57.5ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 59.1ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 57.7ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.1ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.3ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.2ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.1ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.9ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.1ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.7ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.1ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 20.8ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.7ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.3ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 21.5ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.5ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 21.7ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 19.7ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.1ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.0ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 57.6ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 57.3ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.5ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 56.6ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 58.5ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.5ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.3ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.1ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.6ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.0ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 20.9ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.2ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.3ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.1ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.7ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 57.5ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.9ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 56.7ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 58.8ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.5ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.6ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.1ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.8ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 22.9ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.3ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.3ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.0ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 58.1ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.8ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 58.2ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.4ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.9ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.2ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.7ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.6ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.6ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.7ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.5ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.7ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.7ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.5ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.9ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 57.5ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.6ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.0ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.4ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.1ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.5ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.5ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.2ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 58.3ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 58.0ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 58.7ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.6ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 59.6ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.4ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.9ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.7ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 20.7ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.0ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.8ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.7ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 58.0ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.1ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 59.1ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 57.9ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.6ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.0ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 20.7ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.5ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 58.1ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.5ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 57.5ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.4ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 58.4ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.4ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 58.9ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.4ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.0ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.3ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 57.2ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.5ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.0ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.2ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 58.6ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.3ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 21.3ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.3ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 22.3ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.0ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.3ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.2ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 20.2ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.6ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 21.1ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 20.2ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.2ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.1ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.4ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 22.8ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.1ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.0ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.9ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.5ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 20.4ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.1ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 20.2ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.0ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 22.9ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.6ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 20.8ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.1ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 20.7ns
1x 64bytes Blocks Bandwidth : 24.91GB/s
4x 64bytes Blocks Bandwidth : 32.5GB/s
4x 256bytes Blocks Bandwidth : 104.34GB/s
4x 1kB Blocks Bandwidth : 348.14GB/s
4x 4kB Blocks Bandwidth : 519.35GB/s
16x 4kB Blocks Bandwidth : 646.59GB/s
4x 64kB Blocks Bandwidth : 1007GB/s
16x 64kB Blocks Bandwidth : 596.82GB/s
8x 256kB Blocks Bandwidth : 619.51GB/s
4x 1MB Blocks Bandwidth : 221.48GB/s
16x 1MB Blocks Bandwidth : 25.15GB/s
8x 4MB Blocks Bandwidth : 20.54GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.92GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1016
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 4kB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 4.92GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.92GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1016
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Warning 5010 : Cannot use Large Memory Pages due to lack of privileges.
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## craxton

Veii said:


> Pretty much nails it.
> Clock stretching


so i was correct ? or you saying it seems i have clock stretching?
as well....if what i stated is correct then,
first is snapshot polling, second is snapshot turned off.
core-cycler has ran its course today while i was away at work and to my surprise
it ran fine...(note that core 4 did not hit over 4.7x ghz while running the test tho)
as im fairly certain its supposed to









(as stated no snapshot polling)










Veii said:


> I see people heard my "use -30 allcore CO" , and recommend it to random people as "tweaks".
> Yet the spread message lost the real meaning, that you have to ! add a bit of positive vcore


i (myself) cant get -30 to post unless i input a positive volatge offset of 1v or more yes
Volt not mv itll run at 8xxmv but is nowhere near stable.

people on the amd thread forums that have the whea 18 crash still dont seem to know
its Core voltage related.... anyhow, i used TM5 as an example as this is what (you Veii) stated to test curve with
to check if all cores were boosting at the same time. i can handle 4850/4859 lol might be i am stretching?
or if i am at the slightest .2mhz difference but i dont think thats what anyone meant with clock stretching.

im personally getting ready to donate to get beta builds of CTR so that (or i hope) itll magically
config my cpu to what it believes is best. (even tho ill probably still not be happy) "hey you can do 4.8ghz at X voltage...
nah give me that .50mhz or else 🤪

i also ran Mannas recomended of benchmate using CPUz (which core 4 hit 4.85ghz) so im unsure what to call it)
however, no other stress tests failed (4 hours) prime 95 small FFT alone while i was "playing" pokogo
y-cruncher 4 passes no issue, OCCT 1 hour no issue. but i failed to snag screenshots. will run tests again tomorrow after work
to provide some backbone to this strange behavior? will edit a shot of my Curve and offset as well, my curve might be wrong im unsure
but its pretty close to what i claimed.

do note that my R23 score did drop from well...12050 to 11831 so around 200/250 points but without benchmate open 
in the background i get around 30/40 more points..give or take...


----------



## Veii

craxton said:


> im personally getting ready to donate to get beta builds of CTR so that (or i hope) itll magically
> config my cpu to what it believes is best. (even tho ill probably still not be happy) "hey you can do 4.8ghz at X voltage...
> nah give me that .50mhz or else 🤪


I'm not 100% happy with Yuri's business model, and CTR was not able to outbeat my 4.85 PBO (yet)
But if you want to overdrive CTR a bit - a slight negative CO of 3 with CTR's Overboost feature ontop + little postive vCore offset ~ can run 5ghz allcore
Just because CTR does only run OC mode.

CTR by itself , speaking 2.1 RC05 and later
Is pretty well designed now. He got a lot of unique people's help/contribution to finetune CO and also a lot of information from friendly engineers, assisting him on his work in redoing the whole boosting system
*But again reminding you - it runs in OC_Mode
OC_Mode does shut down 70% of all sensors* , (% may vary up to AGESA state)
Meaning, if you want to pump 1.55v , you can
If you want to peak beyond 1.7v you also can (has a reason)








Reposting again and again - that it certainly is possible
But it's dangerous to follow this path.
You need to observe and understand many of the limiters , because you can run such thing
And OC_Mode is slower than PBO in the switching way
500ms are slower than 5ms switching time. Although my PowerPlan for example was faster than dLDO could adapt , it still is all experimental and very risky

See this 154A,
Long beyond 122A Fuse limit , but still into the Sillicon limits
CTR has them visible, what sillicon limits are.
I give him good credit and bad credit when it's needed.
RC03 messed up my core layout, RC 04 and 05 got finetuned afterwards
Soo credit is there where it's deserved & don't want to ruin friendship by sharing too much information 

I used CTR for 4 things:
Finetuning Loadline between supplied CPU-VID , and V-TEL
V-TEL is what applies on the chip level. VID is what defines the anchor of FIT for the V/F curve ~ which scales by pre-programmed CO values and by FIT's reported core Q values + sillicon strain limit as EDC-A and TDC-A

I also used it for making my life easier and running per-core cinebench workloads (going back to the realistic and not realistic workload topic)
And i used it to play around with CO beyond AMDs defined artificial limits.

Took around 4-5 weeks research , at the time i was inactive on-here.
But because there is a big split on wealthyness for CTR usage ~ going exactly against "hopefully" also his intention "to improve the whole mass of people and architecture"
I can not be happy and say "oh i contributed for a great programm and great cause"
The tool is very good, very dangerous but very good !
The business model affecting also his status & branding ~ is not soo good. But that's my viewpoint 

Hopefully the nice features soon will be public, and people can utilize OB.
Normal people ~ not people who have a subscription model. . .
He started like everyone else, small unknown with a lot of invested work hours. Yet a lot of support thanks to the community, which such business model does split apart 

@craxton , yes 2mhz are already clock stretching by one magnitude or restrained because of other sensor conditions (thermals, amperage). Ron is right , not 100% by the lack of information, but pretty much on point
Flat frequency is what you are looking for 
CPU Snapshot pooling disabled only shows BCLK changes ~ be it because of Hyper-V or because of Spread Spectrum.
It on, doesn't show such changes.

Aida64 has many purposes, i see the constant fight against it ~ but it's not the ns values you get "as comparisons" that matter
Neither is it thaat broken of a "random" test
Oh btw, don't use maxxmem ~ the last 3 versions i tried all had spyware on it ~ run it through VirusTotal and you'll see
I think the download links are compromised. Couldn't find any version that was spyware free


Veii said:


> Is pretty well designed now. He got a lot of unique people's help/contribution to finetune CO and also a lot of information from friendly engineers, assisting him on his work in redoing the whole boosting system


Oh i should add, for people who donate the big amount to buy personal assistance.
Simping won't work  The big community discord is not the developer discord. If you want to contribute with technical information, no monetary value will help you. Only the value of the research matters ~ in case you want to assist the developement or "are a big fan" 


Veii said:


> Reposting again and again - that it certainly is possible


@craxton
If your core rating is better than mine
You likely have a chance of doing the same overdrive as i do
First CCD was a well binned 5950X trown away CCD
It's not guaranteed that you can reach beyond +200Mhz on any ryzen chip ~ and likely why AMD doesn't want to lift this annoying restriction, yet
~ Just so you consider this too, before investing into the subscription model and expecting the same results ~ which i preset 
_your mileage will vary with the OB feature ~ higher boosting chips on stock, have a potentially higher chance to hold +200 and beyond
* mine can do it, as it's not a low binned 5600X , but a trown away 5950X with now a broken V/F curve _


----------



## craxton

Veii said:


> yes 2mhz are already clock stretching


 you cant let me win huh...i removed the offset and added back the .03xx positive offset i once had
as (cant say for sure) but windows update broke? never had that happen had to manually...well anyhow,
"MY" best core or says ryzen master, and core testing software IE"4" is also my worst core for
overclocking....(what your calling clock stretching on 2mhz i do all the time when i meet new females
 (cant get rid of em afterwards tho)




















Veii said:


> CPU Snapshot pooling disabled only shows BCLK changes ~ be it because of Hyper-V or because of Spread Spectrum.
> It on, doesn't show such changes.


snapshot pooling is "exactly" what the cpu is hitting then?
so i should leave this on all the time instead of turning it on once ina while ?
so in otherwords "snapshot" and "max" voltage while snapshots on is what
is being given to the cpu VID? as in thats what the per/core gets?
spread spectrum is always off.... on (while in the past with 2400g, 1600af, 3600xt all
didnt oc (static) to well with it on.
and most ive seen state to turn it off to get better stability while overclocking the cpu



Veii said:


> for people who donate the big amount to buy personal assistance.
> Simping won't work


Not at all, only giving to the cause so i can use the software instead of the free version, and
im impatient.
a small dono to something that ive seen do good things is better than me setting here waiting
while i have the extra cash to do so.
but for sure not a simp, see those on his twitter all the time
"i paid X amount for this and you dont help at all"
how many people donated? if your problem is just a "you problem"
likely its you who is doing something wrong.

but if its being widespread chances are itll get noticed. (you doesnt mean Veii)
you as in simps.




Veii said:


> If your core rating is better than mine
> You likely have a chance of doing the same overdrive as i do


How does one know "core rating?"
thru testing or will a simple (core tuner test) tell this?
Core 0 143
Core 1 139
Core 2 135
Core 3 147
Core 4 131
Core 5 147
(core cycler is where i got this info from) doesnt seem like core 4 is
that "great" after all.



Veii said:


> Just so you consider this too, before investing into the subscription model and expecting the same results ~ which i preset


Not at all, i dont expect to ever get the same outcome as someone else.
perhaps close in some things but im barely able (possibly just me)
to get 4.85 stable with curve settings, and no amount of "all curve"
will this chip hold. (100% stable in every test) -26 itll run fine without crashes with 6xxmv offset.
undervolts not an issue tho.... i believe its mostly user error related and someone else with this chip
could achieve much better results.




Veii said:


> higher boosting chips on stock, have a potentially higher chance to hold


by stock, you mean without the "200mhz" turned on inside bios, being set to "auto"?
im unsure what you mean by stock.

(edit) if you mean stock by 200mhz only with no voltage or curve inputs and everything "BUT" the 200mhz
option being adjusted (leaving 90c max temp) then i hit 4.75ish with TM5 (benchmate) 4.85 (reset hwinfo to run TM5 to get 
all core load or all cores at the same time reading)
so im unsure if 5ghz is possible but if CTR can get me stable 100% at 4.8/4.85 with the scores in my benchs i have now
ill be fine with that, either way ill still be ok just helping out as ive downloaded the software several times...

(LLC and all other stuff is still at 2, 1000khz switching etc, just the 200mhz option inside the bios is what i changed)


----------



## craxton

...? CONFUSED ?

does this mean its actually gonna do 4.9GHz? lol 
i guess only one way to find out....


----------



## Veii

craxton said:


> you cant let me win huh


I can't lie 


craxton said:


> snapshot pooling is "exactly" what the cpu is hitting then?
> so i should leave this on all the time instead of turning it on once ina while ?


Yes


craxton said:


> and most ive seen state to turn it off to get better stability while overclocking the cpu


finetuned by the manufacture, it's a good thing to have
It keeps signal integrity in check by lightly combating EMI ~ also helps memOC because of such
Snapshot pooling will mask/hide it, soo you won't see it as an issue. Don't worry about leaving it enabled, but Hyper-V kernel support, does behave like SpreadSpectrum


craxton said:


> but if its being widespread chances are itll get noticed. (you doesnt mean Veii)
> you as in simps.


Didn't mean you specific either, just as a neutral comment on the different patreon tiers
The discord you get is the "fan" & support discord. It's a bit special, but surely there are helpful people. I mind such places tho, not really neutral ~ you waste too much time ending fights or dodging ones


craxton said:


> How does one know "core rating?"


ACPI core rating, either by windows's core visualizer (% Performance) or by CTR next to the main fields
Your Sample
143+139+135+147+131+147= 842 / cores = ~140.3333
My Sample
136+140+144+132+128+144= 824 / cores = ~137.3333
On average a better sample. Expect 5050-5100 when you perfectly tune it. Also expect a gold rated sample, when loadlines are fine

Funnily both dual CCD 5600X have the same ranking, perfectly the same just with different spreading
There has to be a minimum "passable" rating for AMD ~ to select scu's while all of them are 5800X or 5950X to begin with


craxton said:


> Not at all, i dont expect to ever get the same outcome as someone else.
> perhaps close in some things but im barely able (possibly just me)


Just generalized, not against you


craxton said:


> by stock, you mean without the "200mhz" turned on inside bios, being set to "auto"?
> im unsure what you mean by stock.


Stock stock, please read the 8 page techpowerup or igors-lab tutorial on how to configure and use CTR "the normal" way
The tool is dangerous, please read the manual


craxton said:


> ..? CONFUSED ?
> 
> does this mean its actually gonna do 4.9GHz? lol
> i guess only one way to find out....


You want to disable every offset , and run your common memOC - then likely let vcore loadlines to auto or to something you know will work
run diagnose, later run tune
You will see how much vdroop you get and how different VID from V-TEL is
Match it, it has to be less than 10mV apart from other.
It will shift on Diagnose between VID's ~ soo 1100mV has a different scaling than 1030mV
But it will report the distance of both ~ watch it, takes around 15-20min to finish diag

Once VID to V-TEL is correct, then you can run OB the feature
I should add, because CTR on RC05 still enables DF-States, you want to run a powerplan with as little as possible variation. High Performance with no Idling is preferred, to combat overboost [bug] spikes
... he really shouldn't have called "a feature" something that is actually "a bug and issue" . Only masks the "issue" & the naming is no coincidence 

No curve optimizer, nothing
Maybe enable motherboard limits on PBO just to lift some sensor restrictions, but no offsets & x2 scalar at worst, better X1
(not an issue anymore with RC05, but it can bug out and run 1.55v with vcore offsets. You've been warned) 


Veii said:


> Expect 5050-5100 when you perfectly tune it. Also expect a gold rated sample, when loadlines are fine


Beyond 4900 only when you overdrive the CTR overdriving 
that is 1325mV VID with +50mV offset and sub -10 CO value , likely sub 5 as OB feature does work in 5,10,15,20,25,30 values.
Could have added 35-40-45-50 for me, but it's fine ~ it was tested well & i like to break AMDs stupid artificial limits 🤭
* You don't need PX to run OB feature ~ soo you can use it on P2 for example


----------



## domdtxdissar

Veii said:


> CTR by itself , speaking 2.1 RC05 and later
> Is pretty well designed now. He got a lot of unique people's help/contribution to finetune CO and also a lot of information from friendly engineers, assisting him on his work in redoing the whole boosting system
> *But again reminding you - it runs in OC_Mode
> OC_Mode does shut down 70% of all sensors* , (% may vary up to AGESA state)
> Meaning, if you want to pump 1.55v , you can
> If you want to peak beyond 1.7v you also can (has a reason)
> 
> 
> 
> 
> 
> 
> 
> 
> Reposting again and again - that it certainly is possible
> But it's dangerous to follow this path.
> You need to observe and understand many of the limiters , because you can run such thing
> And OC_Mode is slower than PBO in the switching way
> 500ms are slower than 5ms switching time. Although my PowerPlan for example was faster than dLDO could adapt , it still is all experimental and very risky


Dont understand why boosting in TestMEM is a talking point, there is pretty much no load on the cpu.. Its pointless to compare boosting in it as there is pretty much no heat/work generated for the cores.







If you want to check if your settings are clockstreeching use something else, not TestMEM 5.. (?)


----------



## mongoled

CarnageBT said:


> Thanks for clarifying how to set tRFC settings. Got everything set. What's next?
> 
> *The auto settings for tRDWR and tWRRD are 9 and 4 respectively (those are changed from my original zentimings picture)
> 
> View attachment 2513044


Now you need to run tests to see if the memory is stable, that is the next test.



Veii said:


> ACPI core rating, either by windows's core visualizer (% Performance) or by CTR next to the main fields
> Your Sample
> 143+139+135+147+131+147= 842 / cores = ~140.3333
> My Sample
> 136+140+144+132+128+144= 824 / cores = ~137.3333
> On average a better sample. Expect 5050-5100 when you perfectly tune it. Also expect a gold rated sample, when loadlines are fine


Are these values effected by using PBO, CO and LLC settings ?

My "tuned" 5600X throws out these

152+148+140+144+152+136 = 842 145.33

Using agesa 1.1.9.0, the most ive seen at light loads such as AIDA64 mem bandwidth test is 5025

Will answer my own question, after disabling CO and setting LLC to auto there was a huge change in values from

152+148+140+144+152+136 = 842 145.33

to

140+137+129+133+140+125 = 679 113.16

With that in mind, those values you both posted are they with CO disabled and LLC on AUTO ?

I am going to put LLC back to my previous values and see if the "Maximal performance precentage" changes ....

LLC does not effect the "Maximal performance precentage" value...

Now to put PBO on disabled...


----------



## munternet

Can anyone tell me why vdimm and Mem VTT is grayed out in zentimings?
DRAM voltage shows in HWinfo64 and changes when I make a change in the BIOS


----------



## RonLazer

munternet said:


> Can anyone tell me why vdimm and Mem VTT is grayed out in zentimings?
> View attachment 2513082


Asus boards have the DRAM voltage read off an embedded controller, so Zentimings can't access it. VTT is usually reported by halving DRAM, so that's not shown either.


----------



## PJVol

RonLazer said:


> Asus boards have the DRAM voltage read off an embedded controller,


Why doesn't it read directly from pwm?



Veii said:


> Beyond 4900 only when you overdrive the CTR overdriving


 Just reminds me of Viznik from Deus ex mankind divided, - "exile from exile..." ))


----------



## ManniX-ITA

Veii said:


> One CO is a value of 5mV under idle ~ just sadly it's more into the 4mV range
> 3mV at full load, is accurate too


I can't confirm this, at all 

Very early CO, when there was not mapping to +/- 30 it was linear like that.
Then it got weird with the mapping, weirder with AGESA 1.2.0.0
But now with AGESA 1.2.0.1 and dLDO really... I don't know.
There must be a logic but I can't find it.

Positive or negative vCore offset has always been negative for me.
But with the latest telemetry settings which are very aggressive a small positive offset is beneficial.
Better scores and no crashing running CoreCycler.

Now I'm trying to optimize it but I'm getting really lost... the positive offset acts as a highly randomizing factor.
Decreasing a negative offset often results in the opposite, reducing the VID under load.
The effect of a count change on another core is even more evident than before.

Consider with a positive offset of 25mv eg. Core 5 at -30 went from 4990 Mhz @ 1.340 Vid to 4935 Mhz @ 1.312 Vid
Trying to fix with -28 and it went to 4880 Mhz @ 1.290 Vid... instead of +10mV got a +22mV

Some cores didn't change at all, others got a +20mV....
Did some changes and Core 7 at the same -28 Count dropped 30mV and is now running 50 MHz slower.

Don't know I'm a bit puzzled... maybe 1CCD is more linear than 2CCD?
Will keep testing...

I'd like to try equalizing all the cores the same.
Can you explain a bit more how did you achieve it?

Balancing the VIDs while they run all at the same frequencies during TM5 would work?
Or bringing them to an equal VID when they boost at single core?
What else?


----------



## CarnageBT

mongoled said:


> Now you need to run tests to see if the memory is stable, that is the next test.


I will begin testing now and report back. 

The two tests I am running are:

Membench Memtest set for task scope 1200% (50%/24 cores) and stop at (task mode) Total
TM5 using 1usmus_v3 for 25 cycles. (is this cfg good? or should I use [email protected]?) 

For quicker testing to get rough results should I be testing to these amounts? 1200% and 25 cycles? Or should I lower the test lengths at first until we nail down what you think are more refined numbers then test for longer times?


----------



## mongoled

CarnageBT said:


> I will begin testing now and report back.
> 
> The two tests I am running are:
> 
> Membench Memtest set for task scope 1200% (50%/24 cores) and stop at (task mode) Total
> TM5 using 1usmus_v3 for 25 cycles. (is this cfg good? or should I use [email protected]?)
> 
> For quicker testing to get rough results should I be testing to these amounts? 1200% and 25 cycles? Or should I lower the test lengths at first until we nail down what you think are more refined numbers then test for longer times?


cfg is fine


----------



## CarnageBT

mongoled said:


> cfg is fine


Within the first 3* cycles TM5 has revealed errors 6, 9, 9, 1, 15, 15, 0, 0, 0, 3, 13, 14, 0. The first errors occurred in cycle 2, most occurred in cycle 3. Stopped recording after 3rd cycle and opened HWinfo to check temps, see picture. DIMM 1 & 2, the middles ones I assume, get quite hot at 1.52v, 48 degrees C.

edit: Membench doesn't seem to tell me much early on. Ran fine to 740%. I think I'll save this for final testing and focus on TM5 as that quickly produced errors.


----------



## ManniX-ITA

CarnageBT said:


> Within the first 3* cycles TM5 has revealed errors 6, 9, 9, 1, 15, 15, 0, 0, 0, 3, 13, 14, 0. The first errors occurred in cycle 2, most occurred in cycle 3. Stopped recording after 3rd cycle and opened HWinfo to check temps, see picture. DIMM 1 & 2, the middles ones I assume, get quite hot at 1.52v, 48 degrees C.


The temp doesn't look excessive...
I'd suspect first not enough VDIMM, try with 1.55V then scale down if it works.
And second use RTT 0/3/1, only when you are sure it's working properly try something different.


----------



## Veii

domdtxdissar said:


> Dont understand why boosting in TestMEM is a talking point, there is pretty much no load on the cpu.. Its pointless to compare boosting in it as there is pretty much no heat/work generated for the cores.
> View attachment 2513081
> 
> If you want to check if your settings are clockstreeching use something else, not TestMEM 5.. (?)


I expected more, but then did i really? It hasn't been your first time ~ spreading chaos on this forum

You show/are:

half a screenshot to hide your voltages
incapable to see the load type which is SSE
running OC_Mode which has no clock stretching to begin with
are, as "experienced" CTR user, just ignoring that CB is a dynamic feature and your frequency changes on workload type and strain

What is the point you are even trying to proof here ?
You should know at this point that TM5 is designed to perform exactly how it does ~ be fast without using many instructions per clock. Same as boosttester-github
Giving it a best case boost scenario to speed it up and not factor anything CPU related into it's CRC generate/checking algorithm
That's not HCI or Karhu which do show cpu errors that can appear

How can you ignore what you know and appear that . . . terrestrial ?
First hate on Aida64 now TM5.
If there is nothing positive to say, sometimes it's better to spare others from the negativity

But one point you do proof quite well,
Vermeer is scaling very well with supplied voltage & 1usmus does good work to improve his tool.
That's all your screenshot shows ~ with some added negativity against some program, purposely as you know how it's designed in order "to dislike" it.
I know you do, else you'd be disliking anything "you don't understand". I'm sure you are very well aware and just like to spread chaos on here


domdtxdissar said:


> If you want to check if your settings are clockstreeching use something else, not TestMEM 5.. (?)


This is generalized from my post, maybe you really didn't understand 🤔
But nowhere it was written that TM5 can proof fully clockstretching - but be part of it. Like every other program focused on one specific instruction set
Neither did your screenshot proof anything either. Maybe it would with PBO ~ then congrats on the well behaving two CCDs 
doubt FIT would allow this voltage @ this frequency under PBO
But it certainly doesn't exist on OC_MODE

EDIT:
If you want to hide the CTR version because it's an alpha build
It still can show the high voltages you run
Maybe at least somebody could learn "something" from it ~ how to run this high dynamic clock
EDIT2:
SSE is often "game-clock". Not every game uses AVX2 ~ and the OB designer is aware of this.
Soo congrats on the high frequency, but except that ~ i don't get what you even want to proof here


----------



## CarnageBT

ManniX-ITA said:


> The temp doesn't look excessive...
> I'd suspect first not enough VDIMM, try with 1.55V then scale down if it works.
> And second use RTT 0/3/1, only when you are sure it's working properly try something different.


Sorry, I'm very new to this. What is RTT 0/3/1? Does that mean to change the cycle tests in the 1usmus config to just cycle tests 0, 3 and 1?


----------



## craxton

Veii said:


> Also expect a gold rated sample, when loadlines are fine


(it is gold rated due to my load lines i have to assume.
(even if the profile says "4900" 1350 and the mid/low as well, 
setting this doesnt make it work, or "boost" all cores to this?
still tuning is needed?

or at least activating "and hoping for magic" did not happen. 



Veii said:


> The discord you get is the "fan" & support discord. It's a bit special, but surely there are helpful people. I mind such places tho, not really neutral ~ you waste too much time ending fights or dodging ones


i tend to steer clear from discord nowdays. 
seen to much of that (to much clock stretching going on)
when you have a group of guys competing and claiming one thing 
vs another claiming something different.



Veii said:


> It keeps signal integrity in check by lightly combating EMI ~ also helps memOC because of such


so, i should turn this back on? tried to find out more information on but 
i suppose now i know at the least.



Veii said:


> Don't worry about leaving it enabled


itll be turned back on for sure. and keep this in mind for future notes.



Veii said:


> 136+140+144+132+128+144= 824 / cores


137+133+129+140+125+140+804 =134
(with loadlines still set(to llc2 cpu and 3 nb), (auto) is HORRIBLE on this board from what ive seen...
thats with chrome and whatever else runs in the back tho...(which didnt seem to notice change when killing everything)
but no CO, no Voffset, no nothing just loadlines thats it...so i suppose not to much worse than you.
(idk where the first set came from, other than it was with curve) and all the other stuff) unless this set here
is due to the profile being active in CTR



Veii said:


> You want to disable every offset , and run your common memOC - then likely let vcore loadlines to auto or to something you know will work
> run diagnose, later run tune
> You will see how much vdroop you get and how different VID from V-TEL is
> Match it, it has to be less than 10mV apart from other.
> It will shift on Diagnose between VID's ~ soo 1100mV has a different scaling than 1030mV
> But it will report the distance of both ~ watch it, takes around 15-20min to finish diag


all offsets off, no curve (always running my mem-oc) only thing i know works is LLC2 cpu, 3-4 on NB,
and 800-1000 khz CPU, and 1000khz NB (note NB frequency was on AUTO for along time) 
ive been working on lowering SOC voltage if anyones noticed this lol went from 1070 IOD 1.2SOC 
to what its at now. still 100% stable (LLC4 still overshoots but dips below what i set under load) 
so 3 has been my go-to.




Veii said:


> but it can bug out and run 1.55v with vcore offsets. You've been warned)


ill keep this in mind. so far ive not seen this happen.



Veii said:


> You don't need PX to run OB feature


this OB feature your speaking of 
is whats built in to CTR to "tweak"? 
i see it alot in the debug table to the right. 
(glad some back context of how this works has been given)
and by someone who isnt guessing. thank-you



Veii said:


> it was tested well & i like to break AMDs stupid artificial limits


not something i believe ill surpass, but if i can "HIT" these limits and get a fine edge 
on this CPU ill call it success 



mongoled said:


> With that in mind, those values you both posted are they with CO disabled and LLC on AUTO ?


all auto minus LoadLines. bout it (minus IOD, CCD) no mods to limits of any kind.
no offsets.

(so if you can see 5.1ghz at all) i think its 100% user error that i cant get 4.85 
100% stable (due to one core) as its by far the worst ive seen posted here 



mongoled said:


> LLC does not effect the "Maximal performance precentage" value...


idk, if i recall my CPU is a "bronze" without LLC active. 
ill check if it the values change just 1 point ill @ you. but i think your right 
but it does change what "sample" you have using CTR.


----------



## CarnageBT

ManniX-ITA said:


> The temp doesn't look excessive...
> I'd suspect first not enough VDIMM, try with 1.55V then scale down if it works.
> And second use RTT 0/3/1, only when you are sure it's working properly try something different.


Increased to 1.55vdimm but had many more errors (and all in cycle 1); error 10, 3, 3, 13, 13, 9, 9, 9, 9, 14, 1, 1, 1, 11, 11, 0, 15, 15 (end of cycle 1)

Edit: Not sure if it's helpful, but I have time and am trying to provide as much detail as I can. Here are my original settings and current with differences highlighted. I didn't test the original settings extensively, although it did go through TM5 for 8 cycles and had returned the following 5 errors: 2, 10, 0, 12, 14


----------



## craxton

So to be clear, turn on enhanced testing, and OB testing in the beta build?
yea i gave in. help or no help gonna let this do its thing while i set here for the next hour 40 and wait 
for my ride to work.


----------



## mongoled

CarnageBT said:


> Within the first 3* cycles TM5 has revealed errors 6, 9, 9, 1, 15, 15, 0, 0, 0, 3, 13, 14, 0. The first errors occurred in cycle 2, most occurred in cycle 3. Stopped recording after 3rd cycle and opened HWinfo to check temps, see picture. DIMM 1 & 2, the middles ones I assume, get quite hot at 1.52v, 48 degrees C.
> 
> edit: Membench doesn't seem to tell me much early on. Ran fine to 740%. I think I'll save this for final testing and focus on TM5 as that quickly produced errors.
> 
> View attachment 2513086
> View attachment 2513087
> View attachment 2513089


Can you set the voltage to 1.48v in BIOS and if it posts let it load Windows and rerun TM5 and see if the volume of errors decrease and a reminded please of the product code of the memory modules you have


----------



## CarnageBT

mongoled said:


> Can you set the voltage to 1.48v in BIOS and if it posts let it load Windows and rerun TM5 and see if the volume of errors decrease


On it. will report back in 5-10 mins


----------



## CarnageBT

mongoled said:


> Can you set the voltage to 1.48v in BIOS and if it posts let it load Windows and rerun TM5 and see if the volume of errors decrease and a reminded please of the product code of the memory modules you have


I have oloy blade dimms, model ND4U0836144BRADE, Are you a human?


----------



## Veii

CarnageBT said:


> I have oloy blade dimms, model ND4U0836144BRADE, Are you a human?
> 
> View attachment 2513094


These are some new dimms, interesting
It looked like C-Die but the timings are lower @ nice XMP voltage
Could be a newer Samsung Revision

But you run an A0 PCB
Be very cautious with the voltages & RTTs you run
Beyond 1.52v the chance to kill a dimm, is very high 

Need to run as weak as possible RTT_PARK


CarnageBT said:


> 6, 9, 9, 1, 15, 15, 0, 0, 0, 3, 13, 14, 0.


Is this description perfectly accurate ?
6 is a PCB crash
Same as #4 & #0

As long as you use 1usmus_v3, we know what they mean
Anta's is unknown so far 
get this thing here & set tCKE 9 for 3800








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com





Be sure to assist us and tell exactly when the errors appear. The first 4-6 are important, the rest will snowball without much meaning to it

EDIT:
Do you have any set which you know is stable ?
I got a decent 15-15-15 set for A0 PCBs
You might want to do it step by step , binning a pair of two and letting the "best kits ~ that require the lowest voltage" on the Slave set of the Mainboard
the main slot need to have the weaker "worse" dimms
Bu it's important that they are about equal in "worse'ness"

It's also important that you take them out once and make a closeup PCB-Trace picture
To verify if these are really A0's or not
A0's are easy to run, but easy to kill too ~ so you should know what you got in your hands
DIMM PCBs are often random. It can happen that you got 3 identical and 1 random ~ which need an RMA.
Be sure to check
OC'ing T-Force 4133 cl18 screenshot examples


----------



## ManniX-ITA

CarnageBT said:


> Sorry, I'm very new to this. What is RTT 0/3/1? Does that mean to change the cycle tests in the 1usmus config to just cycle tests 0, 3 and 1?


Sorry I thought it was a B-die, it's a C-die.
It was about the RTT.
No idea about the behavior...


----------



## CarnageBT

mongoled said:


> Can you set the voltage to 1.48v in BIOS and if it posts let it load Windows and rerun TM5 and see if the volume of errors decrease and a reminded please of the product code of the memory modules you have


Seems much better than 1.55v which gave many errors in cycle 1.
1.52v gave first error (6), during cycle 2, then the errors piled on after that (mostly during cycle 3)
Now, 1.48vonly had error 0 in cycle 1, nothing else. Cycle 2, no errors. Cycle 3, no errors.


----------



## Veii

CarnageBT said:


> Now, 1.48vonly had error 0 in cycle 1, nothing else. Cycle 2, no errors. Cycle 3, no errors.


ZenTimings screenshot please
Error 0 still is a powering issue (RTT or CAD_BUS)
Try setting 30-20-24-20 ~ if we speak about 5xxx

depending on RTTs , it might be a negative change
depends, you maybe will need to run 24-20-20-24 for now, really depends


----------



## CarnageBT

Veii said:


> ZenTimings screenshot please
> Error 0 still is a powering issue (RTT or CAD_BUS)
> Try setting 30-20-24-20 ~ if we speak about 5xxx
> 
> depending on RTTs , it might be a negative change
> depends, you maybe will need to run 24-20-20-24 for now, really depends


Give me 5 mins. I'll photograph them for you now


----------



## mongoled

CarnageBT said:


> Give me 5 mins. I'll photograph them for you now
> 
> View attachment 2513095


Your in good hands with @Veii 

 

If he drops out the running will take the baton


----------



## craxton

@Veii when you stated the other day, that CTR can tell if you have a dual CCD unit.
(where) will it display this info? 
i think im a little off on it but anyhow, OB CCX#1=60, OB CCX #2=1


----------



## mongoled

ManniX-ITA said:


> Sorry I thought it was a B-die, it's a C-die.
> It was about the RTT.
> No idea about the behavior...


No I think they are b-die also


----------



## ManniX-ITA

mongoled said:


> No I think they are b-die also


Too hot today, thought I've read it was G.Skill kit DR doh 
Don't know it seems so but crashing that bad... maybe a low-binned B-die?
Curious indeed.


----------



## Veii

CarnageBT said:


> Give me 5 mins. I'll photograph them for you now
> 
> View attachment 2513095


You really try an aggressive set
Let's go down a bit 
CCD 980, IOD 1060, SOC 1137,5mV
@ 1800/3600

tRRD needs to be higher
It XMPs higher at 6-10
Try to replicate that for now
6-10-60 tFAW is 60
tRAS is 34, tRC 50
Try the *7 node from tRFC mini

tWTR_ 5-14
tWRRD to 3

tCKE 6 , CAD_BUS 40-20-30-20, RTT 6-3-4, procODT 34
Stay at 1.48v

You will need around 1.55 for 3800 CL14-14
But before you exceed 1.52 , for the health of your dimms you have to lower RTT_PARK & get GDM off stable
Be sure to copy tRFC1-2-4 from the mini thing above

Maybe you need to go *8 because of "many dimms" but we'll see


----------



## mongoled

ManniX-ITA said:


> Too hot today, thought I've read it was G.Skill kit DR doh
> Don't know it seems so but crashing that bad... maybe a low-binned B-die?
> Curious indeed.


It is most likely the PCBs that are used, once we get photos all will become clear


----------



## CarnageBT

Veii said:


> ZenTimings screenshot please
> Error 0 still is a powering issue (RTT or CAD_BUS)
> Try setting 30-20-24-20 ~ if we speak about 5xxx
> 
> depending on RTTs , it might be a negative change
> depends, you maybe will need to run 24-20-20-24 for now, really depends


Here are some pictures of the 4 dimms









3 new items by Brian Tanner







photos.app.goo.gl


----------



## CarnageBT

Veii said:


> You really try an aggressive set
> Let's go down a bit
> CCD 980, IOD 1060, SOC 1137,5mV
> @ 1800/3600
> 
> tRRD needs to be higher
> It XMPs higher at 6-10
> Try to replicate that for now
> 6-10-60 tFAW is 60
> tRAS is 34, tRC 50
> Try the *7 node from tRFC mini
> 
> tWTR_ 5-14
> tWRRD to 3
> 
> tCKE 6 , CAD_BUS 40-20-30-20, RTT 6-3-4, procODT 34
> Stay at 1.48v
> 
> You will need around 1.55 for 3800 CL14-14
> But before you exceed 1.52 , for the health of your dimms you have to lower RTT_PARK & get GDM off stable
> Be sure to copy tRFC1-2-4 from the mini thing above
> 
> Maybe you need to go *8 because of "many dimms" but we'll see


Do you want me to do all of the above and 

"ZenTimings screenshot please
Error 0 still is a powering issue (RTT or CAD_BUS)
Try setting 30-20-24-20 ~ if we speak about 5xxx

depending on RTTs , it might be a negative change
depends, you maybe will need to run 24-20-20-24 for now, really depends "

I'll let you see the pictures first then, let me know which you would like me to do.


----------



## Veii

CarnageBT said:


> Here are some pictures of the 4 dimms
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 3 new items by Brian Tanner
> 
> 
> 
> 
> 
> 
> 
> photos.app.goo.gl
> 
> 
> 
> 
> 
> 
> CarnageBT said:
> 
> 
> 
> I'll let you see the pictures first then, let me know which you would like me to do.
Click to expand...

These are either custom A2's or Thaiphoon Burner is drunk
Both likely
Can you make a side picture ?
To see on which height the ICs are
Further down near the end of the heatspreader or far upwards

They surely are not A0's
Maybe A3's but it doesn't look like A3's , the traces have more an A2 vibe

The post from before counts
Increase tRRD_
It's too low , and fix tWTR ,which is strange


----------



## CarnageBT

Here's a link to the full Thaiphoon report on this ram with the timing in ns









Chun Well Holding Ltd. ND4U0836144BRADE.html







drive.google.com


----------



## mongoled

I cant tell what those PCBs are, looks like they are a custom PCB ? ?

I would simply change RttPark to 2 (120 ohms in BIOS) as you are using 1.48v, is it giving you 1.49v or 1.5v in HWInfo64 ?

@Veii, slowly slowly, CarnageBT is a beginner, you will make his head explode


----------



## domdtxdissar

@ Veii
i cant respond to everything you have written, but i can take a few.



Veii said:


> I expected more, but then did i really? It hasn't been your first time ~ spreading chaos on this forum
> 
> You show/are:
> 
> half a screenshot to hide your voltages


You have both -set and -get vcore voltages, what more do you wish to see ?







Have highlighted all the normal ones in red.



Veii said:


> What is the point you are even trying to proof here ?
> You should know at this point that TM5 is designed to perform exactly how it does ~ be fast without using many instructions per clock. Same as boosttester-github
> Giving it a best case boost scenario to speed it up and not factor anything CPU related into it's CRC generate/checking algorithm


I'm trying to show that TestMeM dont generate any heat / real load on the cpu and therefor its a bad option to use if you want to detect clock stretching / performance problems.
And there are few performance indexes in this program which tells you if your system are underperforming or you are getting the numbers you should..

Does anyone experience clock stretching in TestMem ?

Maybe we have some communication problems here (?) When i say clock stretching i mean when your "effective clock" is much lower than your "shown core clock" -> a person think they are running like 4.8ghz but their cpu only perform like its running 4.4ghz in benchmarks. I will come back with a screenshot of this later.

Think about "undervolt zen2" from a few years back, video about it here



Veii said:


> How can you ignore what you know and appear that . . . terrestrial ?
> First hate on Aida64 now TM5.
> If there is nothing positive to say, sometimes it's better to spare others from the negativity


I dont hate anything, but i still think there is a big difference between latency numbers in AIDA and what i would call "realworld performance" (™ Intel)
One of the the fastest and easier ways in my mind to check what settings actually perform best is to do a memtest bench (included in dram calc)

Aida is and have always been useful if you just want to check small changes on your own settings, but the comparison should only be to your own system as the numbers are very easy to be manipulated both by windows, different versions and other "secret tweaks".

TestMEM is a good memory timing checker which should be used together other other stress/benchmark-programs to find stability (one of the best since it have a "manual" on errors)
But i didn't find it particularly helpful when i was trying to find the best curve optimizer settings for maximum performance. And lets just say my PBO CO numbers on asus bios 3003 was pretty "dialed in" in the end..



Veii said:


> That's all your screenshot shows ~ with some added negativity against some program, purposely as you know how it's designed in order "to dislike" it.
> I know you do, else you'd be disliking anything "you don't understand". I'm sure you are very well aware and just like to spread chaos on here


I have lost you here.. Dont understand what chaos you think iam spreading (?)



Veii said:


> If you want to hide the CTR version because it's an alpha build
> It still can show the high voltages you run


Now you are just making thing up as you go..
In the quoted screenshot i cut out CTR to save space as it didn't show anything that HWinfo didn't show.
Dont understand what you think i'm hiding ?? You have -set vcore, -get vcore temp and static OC mhz ++++

*I can post the whole screenshow without cut, but first please tell what information you think you would gain/learn.*

And i didn't use any specials alpha build, i was a regular CTR subscriber running 2.1 RC5 like everyone else on 1usmus patreon

Did you wake up on the wrong side of the bed this morning or something ?


----------



## mongoled

@domdtxdissar
I think @Veii has you mixed up with someone else from Norway



Trying to remember who it was who didnt like TM5 ...


----------



## CarnageBT

Veii said:


> These are either custom A2's or Thaiphoon Burner is drunk
> Both likely
> Can you make a side picture ?
> To see on which height the ICs are
> Further down near the end of the heatspreader or far upwards
> 
> They surely are not A0's
> Maybe A3's but it doesn't look like A3's , the traces have more an A2 vibe
> 
> The post from before counts
> Increase tRRD_
> It's too low , and fix tWTR ,which is strange


photos 









6 new items by Brian Tanner







photos.app.goo.gl


----------



## Veii

domdtxdissar said:


> Does anyone experience clock stretching in TestMem ?


Me, that's why i told to take a look. But it won't matter as CTR's OC_Mode doesn't ever show clock-stretching
TM5 will not show per-core, as it takes all cores down to the lowest one. But it does very well show if you can hit & hold your peaking limit strap or everything else wents down because "something" is stretching.


domdtxdissar said:


> You have both -set and -get vcore voltages, what more do you wish to see ?
> 
> 
> domdtxdissar said:
> 
> 
> 
> I can post the whole screenshow without cut, but first please tell what information you think you would gain/learn.
Click to expand...

CTR OB is interesting. For learning purposes , for example people can check what V-VID and V-TEL is required for the CPU to try and boost that high
And the distance of these two + P2 , will also show if you used positive v-core offset to allow for such a high boost or not
Logically it will go down on stronger workloads
But nobody expected a CTR screenshot. This makes it have "no meaning" as clock stretching can not appear on a fixed frequency.

I could've been too rude here, but i expected you to know this ~ both of the mentions before you judge on TM5
Just it's not the first time that i see this wording of criticism against a programm somebody uses for "maybe unknown to you" information purposes (Aida64)
But because it is quite obvious and you still call it "nonsense" ~ i expect that you are very aware of why you dislike it. Soo the harsh answer was for a reason there



domdtxdissar said:


> And i didn't use any specials alpha build, i was a regular CTR subscriber running 2.1 RC5 like everyone else on 1usmus patreon


I set a theory on behalf that you are aware of the critic towards the tool being "useless or nonsense"
Soo on behalf that you very well know why my words could be nonsense and aware of hiding something.

Been running dev builds, and it sometimes is not a good idea to share which version you run
But you certainly could share what voltage and starting frequency you used to get the frequency you illustrate "as proof for TM5 being nonsense".

All build around your critique against an useful program. And i expected you are well aware that it's just "a lightweight SSE load" & the reason i picked it
Could have picked any random boost tester, with a lightweight load & continue with AVX and AVX2 loads afterwards
Just then it wouldn't be "clock stretching" but "frequency throttle by hitting powerlimits" or "frequency throttle by hitting thermal limits"

Non of this is the so called "nonsense" , and the whole reason for the harsh answer
I think you are trolling & well aware of that ~ that's the reason for the harsh answer.
But maybe you really didn't know. Unsure, but i know that you where criticising something without much reason + calling it nonsense.
Not for the first time on this thread, and similar not for the first time from you.
I'm normally not that harsh ~ i hope
Soo sorry, but i think it was deserved if you where trolling


CarnageBT said:


> Here's a link to the full Thaiphoon report on this ram with the timing in ns
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Chun Well Holding Ltd. ND4U0836144BRADE.html
> 
> 
> 
> 
> 
> 
> 
> drive.google.com


This certainly is some new Samsung-IC Batch.


CarnageBT said:


> photos
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 6 new items by Brian Tanner
> 
> 
> 
> 
> 
> 
> 
> photos.app.goo.gl


And certainly something along the lines of A2-A3
For A3 the lanes have a bit too many curves and are not short-direct

I think custom A2 ~ would need to find the Viper 4400 A2 PCB to check trace alignment
Certainly has a Hall-Of-Fame vibe to it 
* just for "good A2's" they are PCB crashing too early


----------



## CarnageBT

Ok.... I did my best but i'm sure i've missed or made some errors, can you please let me know how I did? I couldn't set tFAW above 54 (max in bios). and I'm very confused on how to set RTT, I've atached pictures of my rtt options









3 new items by Brian Tanner







photos.app.goo.gl





below is the zentimings pic.


----------



## CarnageBT

mongoled said:


> I cant tell what those PCBs are, looks like they are a custom PCB ? ?
> 
> I would simply change RttPark to 2 (120 ohms in BIOS) as you are using 1.48v, is it giving you 1.49v or 1.5v in HWInfo64 ?
> 
> @Veii, slowly slowly, CarnageBT is a beginner, you will make his head explode


set at 1.48 in bios is giving me 1.488 at idle


----------



## Veii

domdtxdissar said:


> I'm trying to show that TestMeM dont generate any heat / real load on the cpu and therefor its a bad option to use if you want to detect clock stretching / performance problems.
> 
> 
> domdtxdissar said:
> 
> 
> 
> Does anyone experience clock stretching in TestMem ?
> 
> 
> Veii said:
> 
> 
> 
> Me, that's why i told to take a look.
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

This viewpoint is to proof throttling, not stretching

Stretching remains under NDA, and any little load you can push is enough to indicate if any stretching appears
If the CPU can not max out at the set Max-Freq strap, then it does stretch 

In order to sort out all the potential other options for throttling (which looks nearly identical to stretching)
You have to test it at each type of workload
AVX2 has a predefined throttle and predefined voltage drop
AVX utilizes the loadlines for voltage drop

Many options appear for why it can throttle ~ and mask clock-stretching
TM5's SSE load is very well "close to real world". 
It's branch prediction is just very optimized at this state and doesn't generate much heat (same for AVX2 ~ far better than it was with 2x128bit combined on Matisse)
If you took a look at EDC, same with for example running AVX2 under y-crunchers FFT based FCLK test (by random it just detects very well if FCLK has issues)
it also barely generates any PPT or TDC values, but a lot of EDC strain 

It's not "weak" , but rather "well optimized".
Take some early gen, and the strain is far higher on it.
Vermeer just adds ontop of everything also a good OnChip ECC , but gladly TM5 still reports errors.

Nevertheless how we shuffle it,
There is a reason for why i recommended it to someone
From your point of view you just tried to judge on the reason , and then don't even provide any valuable evidence
What answer was expected ? Of course it looks like you are purposely trolling and judging on something. Not even judging pretty much saying my opinion is nonsense and the tool is g*rbage
Just with more neutral wordings


----------



## domdtxdissar

Veii said:


> Me, that's why i told to take a look. But it won't matter as CTR's OC_Mode doesn't ever show clock-stretching
> TM5 will not show per-core, as it takes all cores down to the lowest one. But it does very well show if you can hit & hold your peaking limit strap or everything else wents down because "something" is stretching.
> 
> CTR OB is interesting. For learning purposes , for example people can check what V-VID and V-TEL is required for the CPU to try and boost that high
> And the distance of these two + P2 , will also show if you used positive v-core offset to allow for such a high boost or not
> Logically it will go down on stronger workloads
> But nobody expected a CTR screenshot. This makes it have "no meaning" as clock stretching can not appear on a fixed frequency.
> 
> I could've been too rude here, but i expected you to know this ~ both of the mentions before you judge on TM5
> Just it's not the first time that i see this wording of criticism against a programm somebody uses for "maybe unknown to you" information purposes (Aida64)
> But because it is quite obvious and you still call it "nonsense" ~ i expect that you are very aware of why you dislike it. Soo the harsh answer was for a reason there
> 
> 
> I set a theory on behalf that you are aware of the critic towards the tool being "useless or nonsense"
> Soo on behalf that you very well know why my words could be nonsense and aware of hiding something.
> 
> Been running dev builds, and it sometimes is not a good idea to share which version you run
> But you certainly could share what voltage and starting frequency you used to get the frequency you illustrate "as proof for TM5 being nonsense".
> 
> All build around your critique against an useful program. And i expected you are well aware that it's just "a lightweight SSE load" & the reason i picked it
> Could have picked any random boost tester, with a lightweight load & continue with AVX and AVX2 loads afterwards
> Just then it wouldn't be "clock stretching" but "frequency throttle by hitting powerlimits" or "frequency throttle by hitting thermal limits"
> 
> Non of this is the so called "nonsense" , and the whole reason for the harsh answer
> I think you are trolling & well aware of that ~ that's the reason for the harsh answer.
> But maybe you really didn't know. Unsure, but i know that you where criticising something without much reason + calling it nonsense.
> Not for the first time on this thread, and similar not for the first time from you.
> I'm normally not that harsh ~ i hope
> Soo sorry, but i think it was deserved if you where trolling
> 
> This certainly is some new Samsung-IC Batch.
> 
> And certainly something along the lines of A2-A3
> For A3 the lanes have a bit too many curves and are not short-direct
> 
> I think custom A2 ~ would need to find the Viper 4400 A2 PCB to check trace alignment
> Certainly has a Hall-Of-Fame vibe to it
> * just for "good A2's" they are PCB crashing too early


There is no CTR OB information to be learned from a *static OC* in CTR, which was posted in this thread to show TestMEM dont generate any meaningful heat or load on the cores themselves.


> I'm trying to show that TestMeM dont generate any heat / real load on the cpu and therefor its a bad option to use if you want to detect clock stretching / performance problems.
> And there are few performance indexes in this program which tells you if your system are underperforming or you are getting the numbers you should..


I nevermind said or meant that TestMEM is nonsens, but for me i makes no sense to try to finetune your PBO CO settings with it, when there is lots of other programs which does a better job, in my mind atleast.. And the actual word i used was "pointless"



domdtxdissar said:


> Dont understand why boosting in TestMEM is a talking point, there is pretty much no load on the cpu.. Its pointless to compare boosting in it as there is pretty much no heat/work generated for the cores.
> If you want to check if your settings are clockstreeching use something else, not TestMEM 5.. (?)


On the other hand, your latest posts towards me is what i would call nonsens..

Also, with PBO CO + EDC bug enabled = much wow in TestMeM
(nevermind the actual performance sucks in everything)








With whole screenshot this time!


----------



## CarnageBT

@Veii "
* just for "good A2's" they are PCB crashing too early " 

I have a daisychain layout for my mobo with all 4 of my dimms on 1 side. not sure if that info helps or not


----------



## Veii

CarnageBT said:


> I couldn't set tFAW above 54 (max in bios). and I'm very confused on how to set RTT, I've atached pictures of my rtt options
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 3 new items by Brian Tanner
> 
> 
> 
> 
> 
> 
> 
> photos.app.goo.gl


This is awkward
54 will do, it's just *9

RTT should be visible as own option
RTT_NOM,RTT_WR, RTT_Park

CAD_BUS is near it or split into an own CAD_BUS or DRAM Controller option
Should be pretty much nearby , else also findable in AMD CBS
You can often find it on AMD OVERCLOCKING too
Should be quite visible 

tCKE is a timing , and at the bottom of the remain timings
tRRD & tWTR i see was understandable

A "strong" RTT, meaning a low divider , will let more amperage pass to the dimms
Pretty much increasing the effectiveness of the VDIMM you push
And is able to kill PCBs if they are sensitive
We want as less needed RTT as possible
Soo a higher divider on RTT_NOM and RTT_PARK
RTT_WR is special, soo keep it at /3 till you exceed 1.55v and have maxed out both RTT's at /7 already


CarnageBT said:


> I have a daisychain layout for my mobo with all 4 of my dimms on 1 side. not sure if that info helps or not


That's fine 
nearly all 4xx boards and pretty much all 5xx boards are daisy-chain or 2 slot based
4x A2's is painful, but i think we got workable RTTs for it finally

Can you find on the tomahawk in OC menu or Advanced, anywhere an SPD-Info option
Something that reads out the XMP profile, and shows the tCCD_L value ?
Else test it and see if you still error right now
Test it till 6 cycles
Usually you need 45min at least, to reach thermal equilibrium
Getting it stable at lower RTT values (higher divider) would be better
The 7-3-3 was good, maybe make it as 6-3-3 for the start


----------



## CarnageBT

Veii said:


> This is awkward
> 54 will do, it's just *9
> 
> RTT should be visible as own option
> RTT_NOM,RTT_WR, RTT_Park
> 
> CAD_BUS is near it or split into an own CAD_BUS or DRAM Controller option
> Should be pretty much nearby , else also findable in AMD CBS
> You can often find it on AMD OVERCLOCKING too
> Should be quite visible
> 
> tCKE is a timing , and at the bottom of the remain timings
> tRRD & tWTR i see was understandable
> 
> A "strong" RTT, meaning a low divider , will let more amperage pass to the dimms
> Pretty much increasing the effectiveness of the VDIMM you push
> And is able to kill PCBs if they are sensitive
> We want as less needed RTT as possible
> Soo a higher divider on RTT_NOM and RTT_PARK
> RTT_WR is special, soo keep it at /3 till you exceed 1.55v and have maxed out both RTT's at /7 already
> 
> That's fine
> nearly all 4xx boards and pretty much all 5xx boards are daisy-chain or 2 slot based
> 4x A2's is painful, but i think we got workable RTTs for it finally
> 
> Can you find on the tomahawk in OC menu or Advanced, anywhere an SPD-Info option
> Something that reads out the XMP profile, and shows the tCCD_L value ?
> Else test it and see if you still error right now
> Test it till 6 cycles
> Usually you need 45min at least, to reach thermal equilibrium
> Getting it stable at lower RTT values (higher divider) would be better
> The 7-3-3 was good, maybe make it as 6-3-3 for the start


What is RTT 6 equal to in ohms? in my mobo the options are


----------



## mongoled

240/6 = 40
Your on the wrong item


----------



## CarnageBT

Ah HAH. I think i got all the settings. Also click this link to see all the default and XMP SPD-info, incl tCCD_L, which is 7clk or 5ns

Memory z in bios: 2 new photos by Brian Tanner

edit: Here is the complete Thaiphoon report in clock cycle and nanosecond format, includes the tCCD_L and everything else. 
Clock cycles - ND4U0836144BRADE - clock cycles.html
NS - ND4U0836144BRADE - ns.html


----------



## CarnageBT

Ok. Hopefully everything I've changed is good to go, if I have something wrong, let me know and I'll correct. Otherwise, I've begun the standard 1usmus test in TM5 and will let it run for 6 cycles as advised. Will report back with errors, if any, and their order of appearance. 

Really appreciate the help @Veii @mongoled 🙏


----------



## Veii

CarnageBT said:


> Ok. Hopefully everything I've changed is good to go, if I have something wrong, let me know and I'll correct. Otherwise, I've begun the standard 1usmus test in TM5 and will let it run for 6 cycles as advised. Will report back with errors, if any, and their order of appearance.
> 
> Really appreciate the help @Veii @mongoled 🙏


is it fine for now ?
Keep hwinfo open, to log thermals


----------



## CarnageBT

Veii said:


> is it fine for now ?
> Keep hwinfo open, to log thermals


Yep, completed 3 cycles. no errors. temps are better too, max 43 c.
each cycle takes exactly 10 mins for my system

*writing this on my old computer setup right next to the new one. have't fully migrated over yet until I finish the overclocking process.


----------



## Veii

CarnageBT said:


> Yep, completed 3 cycles. no errors. temps are better too, max 43 c.
> each cycle takes exactly 10 mins for my system
> 
> *writing this on my old computer setup right next to the new one. have't fully migrated over yet until I finish the overclocking process.


Ok, bit slow but alright 
Should've been 6 minutes each

Try now 3800/1900 FCLK with 1160 SOC
and change tCKE to 9
Then change VDIMM to 1.52v


----------



## CarnageBT

Veii said:


> Ok, bit slow but alright
> Should've been 6 minutes each
> 
> Try now 3800/1900 FCLK with 1160 SOC
> and change tCKE to 9
> Then change VDIMM to 1.52v


Completed 4 cycles on prev settings. no errors

Starting test on 3800/1900. 1.1625 soc (wouldn't allow 1.6 flat). tCKE 9. VDIMM 1.52


----------



## CarnageBT

Cycle 1 + 3 mins into cycle 2. Error 2, 5, 3, 14, 9, 15, 0, 15, 6, 12, 2, 10, 5, 5, 1
forgot to record max temp.

Stopped the test

While I wait for instructions, trying the test at 1.48v

Cycle 1 & 2 complete. Error 3, 15, 0, 15, 15
max temp 44.5 c

no further testing. awaiting instructions


----------



## Veii

CarnageBT said:


> Cycle 1 + 3 mins into cycle 2. Error 2, 5, 3, 14, 9, 15, 0, 15, 6, 12, 2, 10, 5, 5, 1
> 
> Stopped the test
> 
> While I wait for instructions, trying the test at 1.48v
> 
> Cycle 1 & 2. Error 3, 15, 0


14, and 0 are CAD_BUS issues ~ they can be
"badly timed powerdown also as option"
2,5,3 all are tRDWR or tCKE issues ~ tCKE is a powerdown, RTT's behave similar ***

Pretty much sounds like powerdown is not in sync or Error 2 can be voltage or "too low tRFC"
Try with more, instead of "less" voltage
6 is an issue either with primaries, too strong powering or with VDDG voltages
Can you confirm at 1.52v , with y-cruncher FFT, N32, N64 , VST, C17 test (1, 8 to deselect, or 7 to select all tests, 0 to start)
That FCLK is perfectly fine ?

Repeat that on 3600,3733,3800
Also try tCKE 8 & 16 on your 3800 set
5 also mentions tRDWR, but rather a mirror-move error
Soo when we know it's likely not tRRD_ & tWTR, and it shouldn't be tRDWR
It can be too low SCL or just a lack of voltage issue.

You start without a baseline, without knowing if FCLK is stable & without a good set


https://www.overclock.net/attachments/1620200554431-png.2489274/


This is another baseline you can use, but for many-dimms ~ it can need more tRTP , soo more tWR, and more tRFC
Also +1 more tRDWR and +1 more procODT
RTT's are different too
But on it's foundation, it runs , just need to adapt it for 4 dimms instead of 2
(tWR, tRTP, tRFC, tRDWR, tCKE)
tCKE is frequency based, RTT_PARK is dimm capacity based, procODT is both capacity and frequency based

🛌time
Your goal is to lower RTT_PARK as much as possible, so you can run voltages in the 1.55-1.65 range without much heat creation. (you can need up till 1.6v to run 3800C14-14-14 GDM off 1T)
example: MSI B550 Unify / Unify-X Overclocking & Discussions... @ 1.6v ~ just adapt for "many dimms ~ community can help you"
Beyond 1.48v you will need RTT_NOM /7, beyond 1.56 you will need RTT_NOM /6
Beyond 1.58v you will need RTT_WR /2 , while weaking NOM and PARK

All this depends on ClkDrvStr, 1st CAD_BUS Value and VDIMM
More ClkDrvStr, more strain, better powering - but often too much strain soo PARK & NOM need to be lower/weaker
More VDIMM, higher potential for more strain, need stronger NOM filter (lower divider) or weaker NOM (higher divider) and stronger WR (lower divider)
ClkDrvStr is individual to anything, no association and there to give dimms "a bit more umpf" when you want to run GDM off, or GDM off 1T
You can increase it as much as you need to increase it , till 1T runs. Usually 30-40 is enough to get GDM away and run 2T
Keep in mind that a lot of VDIMM , needs lowering ClkDrvStr ~ else you overvolt (ampere) the PCBs and they crash
A balance thing

It's no silicon, it can not degrade - but it can die quite fast if you do stupid things
Most of the times it just crashes. But once you start to lose memory channels ~ stop immediately, as it's near death for them 

*** NOM is signal ceiling (high pulse) PARK is signal floor (low pulse) ~ a sinewave
WR is dynamicly shifting the sinewave to adjust and match signal traces
For a sine-signal to move, it needs to reflect upwards and bounce back downwards to upwards
You control the ceiling with RTT

Part helpful, but maybe bit too technical. Learning by doing is easier, make your own observations without reading the manual & expecting that written change
Reddit Demystifying MemoryTimings ~ it's bit old, not everything applies


----------



## CarnageBT

Veii said:


> 14, and 0 are CAD_BUS issues ~ they can be
> "badly timed powerdown also as option"
> 2,5,3 all are tRDWR or tCKE issues ~ tCKE is a powerdown
> 
> Pretty much sounds like powerdown is not in sync or Error 2 can be voltage or "too low tRFC"
> Try with more, instead of "less" voltage
> 6 is an issue either with primaries, too strong powering or with VDDG voltages
> Can you confirm at 1.52v , with y-cruncher FFT, N32, N64 , VST, C17 test (1, 8 to deselect, or 7 to select all tests, 0 to start)
> That FCLK is perfectly fine ?
> 
> Repeat that on 3600,3733,3800
> Also try tCKE 8 & 16 on your 3800 set
> 5 also mentions tRDWR, but rather a mirror-move error
> Soo when we know it's likely not tRRD_ & tWTR, and it shouldn't be tRDWR
> It can be too low SCL or just a lack of voltage issue.
> 
> You start without a baseline, without knowing if FCLK is stable & without a good set
> 
> 
> https://www.overclock.net/attachments/1620200554431-png.2489274/
> 
> 
> This is another baseline you can use, but for many-dimms ~ it can need more tRTP , soo more tWR, and more tRFC
> Also +1 more tRDWR and +1 more procODT
> RTT's are different too
> But on it's foundation, it runs , just need to adapt it for 4 dimms instead of 2
> (tWR, tRTP, tRFC, tRDWR, tCKE)
> tCKE is frequency based, RTT_PARK is dimm capacity based, procODT is both capacity and frequency based
> 
> 🛌time
> Your goal is to lower RTT_PARK as much as possible, so you can run voltages in the 1.55-1.65 range without much heat creation. (you can need up till 1.6v to run 14-14-14 GDM off 1T)
> example: MSI B550 Unify / Unify-X Overclocking & Discussions... @ 1.6v
> Beyond 1.48v you will need RTT_NOM /7, beyond 1.56 you will need RTT_NOM /6
> Beyond 1.58v you will need RTT_WR /2 , while weaking NOM and PARK
> 
> All this depends on ClkDrvStr, 1st CAD_BUS Value and VDIMM
> More ClkDrvStr, more strain, better powering - but often too much strain soo PARK & NOM need to be lower/weaker
> More VDIMM, higher potential for more strain, need stronger NOM filter (lower divider) or weaker NOM (higher divider) and stronger WR (lower divider)
> ClkDrvStr is individual to anything, no association and there to give dimms "a bit more umpf" when you want to run GDM off, or GDM off 1T
> You can increase it as much as you need to increase it , till 1T runs. Usually 30-40 is enough to get GDM away and run 2T
> Keep in mind that a lot of VDIMM , needs lowering ClkDrvStr ~ else you overvolt (ampere) the PCBs and they crash
> A balance thing


holy info overload. i had to re read that to find out what the 1st thing you want me to do is. sounds like its y-cruncher. I'll download and run it now. I haven't used it before


----------



## CarnageBT

Running y cruncher @ 1.52v (1.536v as reported by HWinfo) for the tests your requested.


----------



## Veii

CarnageBT said:


> holy info overload. i had to re read that to find out what the 1st thing you want me to do is. sounds like its y-cruncher. I'll download and run it now. I haven't used it before


Most of the information that you should need. Strongly simplified
Check that MSI link for better CAD_BUS information and the easier to run 15-15-15 set
Once RTT's are fine, and powering is correct , you can just increase VDIMM ~ balance RTT's and run lower timings at lower heat overall

Getting powering correct is very crucial for low timings
Don't fear the voltage, check ohm's law
it's the same principle
Just made a bit overcomplicated , as RTT are "termination impedances" , baseline as impedance but working as "termination = resistances"
Soo it's a bit confusing what is low and what is high. Just see them as impedances with the opposite effect
Lower is better 

Allows usage of more VDIMM , allows running lower timings without much heat or lifetime constrains/warnings
I daily 1.6v now ~ no issues at all. Not on Rev.E and not on Samsung B-Die
Different PCBs have different RTT's , different capacity too , but learning this annoying part with a lot of trial and error
Is what will help you the most in memOC
The rest remains beating your head against a wall , with much trial and error + and slowly removing errors
Bookmark that tRFC mini doc ~ it has an error describing sheet


----------



## CarnageBT

To repeat you.

You want me to run y-cruncher to verify the fclk is stable. Here are the settings I'm testing it with. I had a reboot occur just now but wasn't sure if it was on n64/vst/c17 (pased fft/n32), so I'm re-running those 3 tests and watching where it crashes.


----------



## CarnageBT

Crashed during n64 or VST, didn't catch it.

Can I try to keep the current settings and run 3733? I heard and have read that every +200mhz fclk is equal or similar to adding +1 on your timings, so if I can run a cl14 @ 3733, that would be better than cl15 @ 3800

Or you think I should drop to cl15, dial in the 1900 fclk so we have better power, cad_bus, rtt, etc., then push for cl14 again?


----------



## CarnageBT

re running y cruncher, same settings with cad_bus 40-20-40-20. IF fails, will try 60-20-40-20


----------



## Veii

CarnageBT said:


> To repeat you.
> 
> You want me to run y-cruncher to verify the fclk is stable. Here are the settings I'm testing it with. I had a reboot occur just now but wasn't sure if it was on n64/vst/c17 (pased fft/n32), so I'm re-running those 3 tests and watching where it crashes.
> 
> View attachment 2513117


@ManniX-ITA or @mongoled likely will need to help you first fix the voltages
What i gave you should work with the low proc
But at the end you might need to increase SOC
You can fallback to 3600 , tCKE 6 and see if you pass the whole y-cruncher suite

Stability rating is 4 cycles, 2min each test * 9 test
18min*4 
TM5 takes usually 1:30h for 16gb, and about 3h or 2:50 for a fast 32gb set
You also want to find bankgroupswap and enable that one in the bios

Figure out tCCD_L (didn't do the math sorry, i'm tired)
and use that as tFAW muliplier
Either multiplying tRRD_L or tRRD_S times this
Also use the tCCD_L value for the tRAS math
tRCD*2 + X (for safety)
tRC remains tRP+RAS, but tRP = tRCD

Just dropping information here
You'll understand it later, if it isn't now 


CarnageBT said:


> Can I try to keep the current settings and run 3733? I heard and have read that every +200mhz fclk is equal or similar to adding +1 on your timings, so if I can run a cl14 @ 3733, that would be better than cl15 @ 3800
> 
> Or you think I should drop to cl15, dial in the 1900 fclk so we have better power, cad_bus, rtt, etc., then push for cl14 again?


200MT/s +1 tCL , +1 tRCD
Nearly that, it's around 300MT/s, but 300 is less consistent than 200MT/s
100MCLK is more accurate here

You have no way around fixing powering settings, if you want to run GDM off ~ which you should strive for
14-14-14 on 4 dimms is a bit much to expect, even when the things appear well binned. They can "just be" different too, compared to typical b-dies
XMP shows high values on "transition timing" between reads & between writes, which are tRRD_ & tWTR_
tWTR is maxed out, soo tRRD_ and SCL scaling it is
tWR is mostly dimm amount and capacity based, same for tRTP
(half of tWR or the opposite, tWR being double of tRTP)

I feel you start without any baseline - soo pick something to get stable
that 14-14-14 is 14-14-14-34 , it likely should be tCCD_L (28+6)
it's complicated, you usually "don't have to" slow tRAS higher than tRCD*2 , but for stability and JEDEC sake
Same for Micron Rev.E ~ that's the way to do it

Start to figure out why y-cruncher crashes (voltage or procODT likely)
and then pick between constantly updating and fixing your 14-14-14 XMP , or going with a 15-15-15 set till 3800~3900MT/s
I can give you an even easier to run 16-16-16 set which i started with ~ exploring FCLK
but it would be kind of a waste, considering you have such tight XMP to begin with 

Likely powering is just badly predicted for you ~ soo prioritize this & check voltages for each FCLK step from 1800 upwards AMD max overclocking voltage this thread
y-cruncher is your best friend here
for procODT , Aida64 is your best friend but it needs a clean OS
on it 0.3ns test-to-test difference = instability, but +/- 0.1ns is test to test variance
(3 different procODT can boot, but only one is correct for the given frequency ~ lower is better)
You should always ignore the first Aida64 cache result, as the CPU needs time to warm up and go into idle state ~ after some load
G'Night for now~


----------



## CarnageBT

Veii said:


> @ManniX-ITA or @mongoled likely will need to help you first fix the voltages
> What i gave you should work with the low proc
> But at the end you might need to increase SOC
> You can fallback to 3600 , tCKE 6 and see if you pass the whole y-cruncher suite
> 
> Stability rating is 4 cycles, 2min each test * 9 test
> 18min*4
> TM5 takes usually 1:30h for 16gb, and about 3h or 2:50 for a fast 32gb set
> You also want to find bankgroupswap and enable that one in the bios
> 
> Figure out tCCD_L (didn't do the math sorry, i'm tired)
> and use that as tFAW muliplier
> Either multiplying tRRD_L or tRRD_S times this
> Also use the tCCD_L value for the tRAS math
> tRCD*2 + X (for safety)
> tRC remains tRP+RAS, but tRP = tRCD
> 
> Just dropping information here
> You'll understand it later, if it isn't now
> 
> 200MT/s +1 tCL , +1 tRCD
> Nearly that, it's around 300MT/s, but 300 is less consistent than 200MT/s
> 100MCLK is more accurate here
> 
> You have no way around fixing powering settings, if you want to run GDM off ~ which you should strive for
> 14-14-14 on 4 dimms is a bit much to expect, even when the things appear well binned. They can "just be" different too, compared to typical b-dies
> XMP shows high values on "transition timing" between reads & between writes, which are tRRD_ & tWTR_
> tWTR is maxed out, soo tRRD_ and SCL scaling it is
> tWR is mostly dimm amount and capacity based, same for tRTP
> (half of tWR or the opposite, tWR being double of tRTP)
> 
> I feel you start without any baseline - soo pick something to get stable
> that 14-14-14 is 14-14-14-34 , it likely should be tCCD_L (28+6)
> it's complicated, you usually "don't have to" slow tRAS higher than tRCD*2 , but for stability and JEDEC sake
> Same for Micron Rev.E ~ that's the way to do it
> 
> Start to figure out why y-cruncher crashes (voltage or procODT likely)
> and then pick between constantly updating and fixing your 14-14-14 XMP , or going with a 15-15-15 set till 3800~3900MT/s
> I can give you an even easier to run 16-16-16 set which i started with ~ exploring FCLK
> but it would be kind of a waste, considering you have such tight XMP to begin with
> Likely powering is just badly predicted for you


I found the tCCD_L value. it's 7clk or 5ns.

edit: Here is the complete Thaiphoon report in clock cycle and nanosecond format, includes the tCCD_L and everything else.
Clock cycles - ND4U0836144BRADE - clock cycles.html
NS - ND4U0836144BRADE - ns.html


----------



## Taraquin

Veii said:


> I can't lie
> 
> Yes
> 
> finetuned by the manufacture, it's a good thing to have
> It keeps signal integrity in check by lightly combating EMI ~ also helps memOC because of such
> Snapshot pooling will mask/hide it, soo you won't see it as an issue. Don't worry about leaving it enabled, but Hyper-V kernel support, does behave like SpreadSpectrum
> 
> Didn't mean you specific either, just as a neutral comment on the different patreon tiers
> The discord you get is the "fan" & support discord. It's a bit special, but surely there are helpful people. I mind such places tho, not really neutral ~ you waste too much time ending fights or dodging ones
> 
> ACPI core rating, either by windows's core visualizer (% Performance) or by CTR next to the main fields
> Your Sample
> 143+139+135+147+131+147= 842 / cores = ~140.3333
> My Sample
> 136+140+144+132+128+144= 824 / cores = ~137.3333
> On average a better sample. Expect 5050-5100 when you perfectly tune it. Also expect a gold rated sample, when loadlines are fine
> 
> Funnily both dual CCD 5600X have the same ranking, perfectly the same just with different spreading
> There has to be a minimum "passable" rating for AMD ~ to select scu's while all of them are 5800X or 5950X to begin with
> 
> Just generalized, not against you
> 
> Stock stock, please read the 8 page techpowerup or igors-lab tutorial on how to configure and use CTR "the normal" way
> The tool is dangerous, please read the manual
> 
> You want to disable every offset , and run your common memOC - then likely let vcore loadlines to auto or to something you know will work
> run diagnose, later run tune
> You will see how much vdroop you get and how different VID from V-TEL is
> Match it, it has to be less than 10mV apart from other.
> It will shift on Diagnose between VID's ~ soo 1100mV has a different scaling than 1030mV
> But it will report the distance of both ~ watch it, takes around 15-20min to finish diag
> 
> Once VID to V-TEL is correct, then you can run OB the feature
> I should add, because CTR on RC05 still enables DF-States, you want to run a powerplan with as little as possible variation. High Performance with no Idling is preferred, to combat overboost [bug] spikes
> ... he really shouldn't have called "a feature" something that is actually "a bug and issue" . Only masks the "issue" & the naming is no coincidence
> 
> No curve optimizer, nothing
> Maybe enable motherboard limits on PBO just to lift some sensor restrictions, but no offsets & x2 scalar at worst, better X1
> (not an issue anymore with RC05, but it can bug out and run 1.55v with vcore offsets. You've been warned)
> 
> Beyond 4900 only when you overdrive the CTR overdriving
> that is 1325mV VID with +50mV offset and sub -10 CO value , likely sub 5 as OB feature does work in 5,10,15,20,25,30 values.
> Could have added 35-40-45-50 for me, but it's fine ~ it was tested well & i like to break AMDs stupid artificial limits 🤭
> * You don't need PX to run OB feature ~ soo you can use it on P2 for example


The core ratings in CTR is weird and varies between versions:
I got different values at different CTR versions. My 5600X should be garbage tier according to avg values, but [email protected]1.05V and 4.[email protected] seems to be a bit better than the avg 5600X.


----------



## T[]RK

mongoled said:


> With GT710 it was unstable posting 1900 FCLK! I tried my 2133 FCLK settings and after numerous failed booting attempts I managed to get into Windows, when I finally was able to get into event log there were thousands upon thousands of WHEA 19s, was then greeted with a reboot.


On my system 2000 MHz FCLK (1:1) my system was very unstable in Windows (freeze in Windows) and ~200 WHEA #19 warnings... and yeah... NVIDIA driver stops and recover.


----------



## tigerfeast

Hey guys.

Sorry if this is not the best place for this - I'm quite new here and also new to overclocking so excuse my ignorance.

I recently bought some RAM for my new PC - G Skill Trident Z Neo 2x8GB 16-19-19-39 3600 Mhz - I believe they are Hynix. Followed a few guides online and managed to get them to 4200 Mhz (with IF set to 2100) and 18-21-22-33. I tried initially going for 3800Mhz and tightening timings more but got worse results. Currently getting ~60ns latency and ~62gb/s read/write.

I noticed that these - F4-3800C14D-16_G_TZN. Trident Z Neo DDR4-3800Mhz_ CL14_-16-16-36 1.50V 16GB (2x8GB) - are now available in stock and was wondering if it might be worth to buy them since they are at a similar price and I'm still in the return period.

Am I gonna get much better results with those? And am I even going to be able to run them at 3800Mhz? I read a lot of people are having issues running IF at 1900Mhz on Ryzen (I have 5900x), but does the fact that I already managed to get it to run at 2100Mhz mean that I won't have issues with that? Or does CL14 change something in that context?

Also, I'd ideally want to get 32GB and was wondering if 4x8 might be better than 2x16 in this case? I've seen a few benchmarks saying it's slightly better, but I also know that running 4 sticks is harder in general, so not sure performance wise what would be the best end result. Ideally, all else being equal, I'd get the 4x8 just for aesthetic purposes.

Just to clarify, my personal definition of "worth it" in this case is ">1% increase in fps in 1440p gaming in at least 1 game".


----------



## CarnageBT

I was testing y cruncher just now and got this. Currently looking up what it means or what I need to fix to fix it. If anyone knows, lmk. ty


----------



## CarnageBT

Ughh.. I'm so frustrated. Feel like I didn't accomplish anything today. Can't even establish a solid baseline at cl14. Is a 3600/1800 baseline useful? We can likely establish that since my XMP profile defaults to cl14/3600. We started today with 3733 and quickly moved onto 3800.

Do you guys feel like this is good ram and we can eventually get it to work? @Veii @mongoled . Otherwise, I'm entirely open to selling them and buying a new kit that isn't a NEW pcb and the first time you've seen something. I'm happy to buy what you guys recommend as the best overclockable kit and go with something fast, proven, so we can have an idea of what should work, then go from there. I feel like with this kit, it's a bunch of unknowns since it's new and is much more work than choosing a familiar kit that people have worked with a lot in the past and have a good idea of what's possible and what should/shouldn't work with predictable behaviour.

*I didn't mention but I have a decent cpu overclock; 250 ppt / 175 tdc / 185 edc / 1x scalar / +200mhz boost / CPPC & CPPC preferred cores enabled. Curve optimized per core individually with p95 using 84k/128k fft's. 
It's stable (with the default XMP memory settings lol). Can run prime95 small ftt's as well individual per core (single core) 84k and 128k fft's for hours. No clock stretching either, the odd time, ccd0/1 may have 0.1 stretch but for the most part it's perfect 1:1 mhz.


*sigh... I feel slightly defeated and need direction, either continue with these kits, or give up, sell them, and buy something known to be fast and efficient. I bought 4 dimms because I kept seeing that dual rank > single rank. Is this true after tuning? or is 2x16gb tuned > 4x8gb tuned?

Plz help... have a few drinks to ease the sorrow 😓


----------



## KedarWolf

CarnageBT said:


> Ughh.. I'm so frustrated. Feel like I didn't accomplish anything today. Can't even establish a solid baseline at cl14. Is a 3600/1800 baseline useful? We can likely establish that since my XMP profile defaults to cl14/3600. We started today with 3733 and quickly moved onto 3800.
> 
> Do you guys feel like this is good ram and we can eventually get it to work? @Veii @mongoled . Otherwise, I'm entirely open to selling them and buying a new kit that isn't a NEW pcb and the first time you've seen something. I'm happy to buy what you guys recommend as the best overclockable kit and go with something fast, proven, so we can have an idea of what should work, then go from there. I feel like with this kit, it's a bunch of unknowns since it's new and is much more work than choosing a familiar kit that people have worked with a lot in the past and have a good idea of what's possible and what should/shouldn't work with predictable behaviour.
> 
> *I didn't mention but I have a decent cpu overclock; 250 ppt / 175 tdc / 185 edc / 1x scalar / +200mhz boost / CPPC & CPPC preferred cores enabled. Curve optimized per core individually with p95 using 84k/128k fft's.
> It's stable (with the default XMP memory settings lol). Can run prime95 small ftt's as well individual per core (single core) 84k and 128k fft's for hours. No clock stretching either, the odd time, ccd0/1 may have 0.1 stretch but for the most part it's perfect 1:1 mhz.
> 
> 
> *sigh... I feel slightly defeated and need direction, either continue with these kits, or give up, sell them, and buy something known to be fast and efficient. I bought 4 dimms because I kept seeing that dual rank > single rank. Is this true after tuning? or is 2x16gb tuned > 4x8gb tuned?
> 
> Plz help... have a few drinks to ease the sorrow 😓


B550 boards and X570 boards (Most AMD boards actually) are Daisy Chain and 2x16GB Dual Rank DIMMs overclock better than 4x8GB Single Rank DIMMs.


----------



## craxton

Taraquin said:


> The core ratings in CTR is weird and varies between versions:
> I got different values at different CTR versions. My 5600X should be garbage tier according to avg values, but [email protected] and [email protected] seems to be a bit better than the avg 5600X.


agreed, my core score was what i had shown earlier....now its


----------



## Veii

Taraquin said:


> The core ratings in CTR is weird and varies between versions:
> I got different values at different CTR versions. My 5600X should be garbage tier according to avg values, but [email protected] and [email protected] seems to be a bit better than the avg 5600X.
> 
> 
> craxton said:
> 
> 
> 
> agreed, my core score was what i had shown earlier....now its
> View attachment 2513159
Click to expand...

CTR should read what SMU report
But Curve Optimizer will change how FIT defines the rating of each core
The highest and lowest will mostly remain the same.
The highest will always remain the same

What does influence it , are powerplans, chipset drivers and when FIT has a bad day 
No, it's normal ~ but the average values should stay nearly identical and the peak values will stay on the same cores

Loadlines, better powerdraw, different CO values and disabling Board-Manufacture's Cheating
(manually enforcing PBO, manually enforcing loadlines or 12V expanders)
manually enforcing procODT & removing other latency enchancers

All these will change potential highest OC and boosting behavior
It's normal , it's not CTRs fault



CarnageBT said:


> I was testing y cruncher just now and got this. Currently looking up what it means or what I need to fix to fix it. If anyone knows, lmk. ty
> 
> 
> CarnageBT said:
> 
> 
> 
> Ughh.. I'm so frustrated. Feel like I didn't accomplish anything today. Can't even establish a solid baseline at cl14. Is a 3600/1800 baseline useful?
> 
> 
> CarnageBT said:
> 
> 
> 
> *I didn't mention but I have a decent cpu overclock; 250 ppt / 175 tdc / 185 edc / 1x scalar / +200mhz boost / CPPC & CPPC preferred cores enabled. Curve optimized per core individually with p95 using 84k/128k fft's.
> It's stable (with the default XMP memory settings lol). Can run prime95 small ftt's as well individual per core (single core) 84k and 128k fft's for hours. No clock stretching either, the odd time, ccd0/1 may have 0.1 stretch but for the most part it's perfect 1:1 mhz.
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

You did accomplish something. You found a flaw in your potentially stable old set
It's cores that where crashing
But you can let it loop, (one test before and this) - to see if the same core crashes

Very likely your CO values are not soo good
Soo i guess back to ground 0

Try fixing it by checking which cores consistently crash
You can sort y-cruncher to individual cores too
(it loves to crash CTR "stable" results) 😏

My go to test for CPU stability, before finishing it off with OCCT Extreme AVX2 ~ couldn't make p95 ever useful to me
Soo at the end it's either bad CO value or not soo good loadline
Just need to figure out if it's too much vdroop or lack of voltage

If you can't figure it out, drop it to +150
and add +10mV positive vcore offset
that should be about in line with the big next frequency strap jump
10-15mV positive

One thing you should also consider with "offset" voltages
Is that board-partners on stock have different baselines for automatic "offsets"
Once you go to "offset mode" , it does reset back to AMDs specified defaults
It can very often be "too high" or "too low" ~ with a significant difference. Like it's very clearly visible once board-partners where cheating

Soo sometimes what is positive offset for one, might need to be negative offset for the other
(looking at gigabyte and msi with negative required offsets) 
Or ASUS with nearly always required +5-10mV offsets
(on purely stock operation)


----------



## oobymach

I've got A0 b-dies and pushed them as far as I could and here's my results so far, I set the TestMem5 profile myself to run 13 back to back mirror tests (3,4,5,14,15 are mirror tests) along with the regular 1usmus cycle and no errors after 3 cycles means they're pretty much rock solid.

I also increased voltage to 1.5v on the rams and dropped refresh to 140ns which is basically what b-die is rated for, and running vddp 0.850v, ccd 0.900v, iod 1.0v, vsoc 1.1v with a 3600x


----------



## KedarWolf

oobymach said:


> I've got A0 b-dies and basically pushed them as far as I could and here's my results so far, I set the TestMem5 profile myself to run 13 back to back mirror tests (3,4,5,14,15 are mirror tests) along with the regular 1usmus cycle and no errors after 3 cycles means they're pretty much rock solid.
> 
> I also increased voltage to 1.5v on the rams and dropped refresh to 140ns which is basically what b-die is rated for, and running vddp 0.850v, ccd 0.900v, iod 1.0v, vsoc 1.1v with a 3600x
> 
> View attachment 2513174


You need to change the .cfg file and run at least 20 cycles if not 25 cycles. 3 cycles not near enough to test stability.


----------



## Veii

oobymach said:


> along with the regular 1usmus cycle and no errors after 3 cycles means they're pretty much rock solid.


3 cycles anta = 1:30h means it could be stable
1usmus_v3 needs to be 20+, as the minimum baseline for anything near stability
tRFC errors after cycle 19

Reaching Thermal equilibrium takes 45min and longer
Nothing under 45min is worth anything - not y-cruncher, p95, OCCT or TM5 

Also GDM on does round primaries up ~ on the 2nd pass, that tRCD 13 is likely not real
Get it GDM off, 2T stable (increase ClkDrvStr) and be aware that A0's can die near the 1.54-1.56v range if you push too strong RTT_PARK
tRFC also goes down because of GDM on. Tho 140ns is not much ~ soo GDM off should run it easily


KedarWolf said:


> You need to change the .cfg file and run at least 20 cycles if not 25 cycles. 3 cycles not near enough to test stability.


^
* if the dimms are powered correctly, it doesn't need any voltage increase between 2T and GDM
1T then is another topic

EDIT:
Also your tRFC is wrong ~ rounding errors on 2 & 4
But usually it's fully wrong








Upon tripple checking
Are you even sure that these are A0 ?
A0 usually fail at 4133MT/s - which 4400C19's are these
If they are vipers, then it's a custom A2


----------



## oobymach

Yeah it's a viper kit, it reports as A0 in Thaiphoon, also GDM is greyed out in bios, can't change it from auto setting.

Also would higher or lower value for park be better?


----------



## Veii

oobymach said:


> Yeah it's a viper kit, it reports as A0 in Thaiphoon, also GDM is greyed out in bios, can't change it from auto setting.
> 
> Also would higher or lower value for park be better?


PCB in real life is what matters
If you take them out and make close up trace picture - then we can check

RTT Park = RZQ / something
RZQ= 240ohm , although it should now be finally 480ohm since the latest 1201/2 AGESA

You want /6 or higher but take a look here








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com




RTTs work for every Ryzen Gen and also for Z490 and Z590 boards - if you get to figure out what RZQ and DQs is there

RTT 706 is good for the beginning
Later depends on the PCB and how you power them + what VDIMM you like to use


Spoiler: Another WIP example












Got it up to 4.1ghz / 1200AF
14nm + 12nm IO-Die
3800 doesn't post at all so far


----------



## ManniX-ITA

@Veii
Oh man, *thank you again!*

Of course you were right and the monero miner is the *perfect tool to both measure performances and stability at high FCLK*.

I owe you a tray of beers if you come to Frankfurt one day.
You are great and your advice as usual is pure gold.
I know you don't like being incensed... but how to throttle an humble disciple veneration for his messiah? 

Unlike Linpack xtreme, the miner is memory bandwidth dependent and it doesn't kill my CPU at 90c.
At FCLK 2000 the read DRAM bandwidth is about 41 Gbps almost steady while Linkpack is 27 Gbps.
Linpack only jumps to 45 at the end for a brief second when it's checking the results.

*I was right, CLKREQ# is the key to fix high FCLK instabilities.*
Was also wrong cause it doesn't work for 2033, while it works for 2000.
*It's crucial to power cycle when you enable/disable it or the system will become unstable.*
Must have made the mistake of not power cycling when I've tested it with FCLK 2000.

*Also found that CLKREQ# doesn't work at 1967 but it works beautifully at 1933!*
Always been highly unstable at 1933 but with CLKREQ# doesn't hitch.
Another difference is coil whine; at 1933 without CLKREQ# is humming running the miner with 24 threads like with 32 threads.
With CLKREQ# enabled the VRM is almost quiet with 24 threads....

Thanks to the miner running with 24 threads, I've found out I had performance issues at FCLK 2000 without CLKREQ#.
_Nothing else was evidencing the problem!_

Only 12360 H/s without CLKREQ#!



Spoiler: xmr-stak-rx at FCLK2000 without CLKREQ# 24 threads















Back in business with CLKREQ# with 14935 H/s!



Spoiler: xmr-stak-rx at FCLK2000 with CLKREQ# 24 threads















The issue is not evident while running with 32 threads!
But you can say something is wrong cause the average drops below FCLK 1967 and has a massive peak of 19233 H/s.



Spoiler: xmr-stak-rx at FCLK2000 without CLKREQ# 24 threads















And here the results with the scaling:










Seems a 5900x would already benefit the most just going to 1933 while a 5950x scales better at 1967 and up.

5% gain is really something big... *700-900 H/s delta is a almost a full core on top!*
Obviously fixing the performance issue using CLKREQ# had zero impact on the flow of WHEA 19.
Doesn't seem they have any relationship with the FCLK being unstable or not.



Spoiler: This is what happens at FCLK 2033, similarly at 1967 with CLKREQ#:


----------



## oobymach

I ran the test modded again but with 15 back to back mix of the 5 mirror tests then the regular 1usmus cycle and even dropped the refresh a bit more and still no errors. Tried with trfc 234 like you suggested but it gives bsod on my custom test after only a few seconds but trfc 250 looks stable. I left it for an hour and then ran firefox for a bit while it was doing its thing.


----------



## Veii

ManniX-ITA said:


> I owe you a tray of beers if you come to Frankfurt one day.


I don't drink alcohol often, to very rarely
But consider coming back to Germany ~ depends if i can find any work there to pay my rent
At least for a bit of time 
Hehe, glad to see you had success

It was 2000H/s for me between stock & 2100 FCLK 
Big jump 
I sadly haven't seen this option since quite some time. I think the last time was on an MSI board
Probably with bios mods it should appear

Where is it listed, where does it stay ?
244A EDC limit 🤭

You get a lot of rejected shares
Might want to switch the algorithm - and be sure it won't touch the GPU at all



oobymach said:


> I ran the test modded again but with 15 back to back mix of the 5 mirror tests then the regular 1usmus cycle and even dropped the refresh a bit more and still no errors.


It's really great that you chain together own tests
But unless you know the algorithms, chaining random tests together wont make them fail
Every cell needs to be tested and a little IC has over 1.3 million cells , - soo that times 8 or times 16 on dual rank
not every of these lithographic cells will be able to run the tight timings

No way around going with the typical routine
Only looping one test won't test the properties of the dimm


oobymach said:


> but trfc 250 looks stable.











tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com




Whatever you pick , use the above manual mode - else rounding errors stack


----------



## ManniX-ITA

Veii said:


> I don't drink alcohol often, to very rarely
> But consider coming back to Germany ~ depends if i can find any work there to pay my rent
> At least for a bit of time


Best of luck and pass over Frankfurt in case!



Veii said:


> It was 2000H/s for me between stock & 2100 FCLK
> Big jump
> I sadly haven't seen this option since quite some time. I think the last time was on an MSI board


I fall very quickly in a massive thermal constraint eheh
Hopefully someone with a 5950x and better cooling will do the same test.
I'm working a bit on the new build, still missing some tools but hopefully for this summer I'll sport the 1000W TECs power 

The option is in AMD PBS menu:










Not easy to get it unlocked sadly...



Veii said:


> 244A EDC limit


Testing new limits... I'm at the very edge of what is possible with the Dark Rock Pro 4!



Veii said:


> You get a lot of rejected shares
> Might want to switch the algorithm - and be sure it won't touch the GPU at all


LoL, don't really care to be honest eheh
W/h is more expensive here than you can earn mining!
GPU is disabled in config of course, first thing I did
The clever miner immediately found it and started working on it


----------



## ManniX-ITA

And today hopefully DHL will deliver these:









F4-4000C14D-32GVK - G.SKILL International Enterprise Co., Ltd.


Ripjaws V DDR4-4000 CL14-15-15-35 1.55V 32GB (2x16GB) Ripjaws V series DDR4 DRAM memory is designed for sleek aesthetics and performance, making it an ideal choice for building a new PC system or for upgrading your system memory.




gskill.com


----------



## Veii

ManniX-ITA said:


> I fall very quickly in a massive thermal constraint eheh
> Hopefully someone with a 5950x and better cooling will do the same test.
> I'm working a bit on the new build, still missing some tools but hopefully for this summer I'll sport the 1000W TECs power
> 
> The option is in AMD PBS menu:
> 
> 
> ManniX-ITA said:
> 
> 
> 
> Testing new limits... I'm at the very edge of what is possible with the Dark Rock Pro 4!
Click to expand...

This makes sense 
The Thermal Syphon's look interesting - but only for 300W+ loads
They behave very bad on low powerdraw units
Would cool the 5950X & the 5600X pretty identical , around 30c over ambient
The coolermaster TECs are in my eyes/view ~ same as thermal-takes dual CPU + Memory AIO unit

Currently looking/recommending the Corsair CMDAF2 ~ as easy to install/fix option, for people who accept build-tuning/OC (@ 1.6v) 
But sadly there is no information about ThermalTake's new Black CPU+Mem AIO

Yea AMD PBS
I really need to take a look
14nm can load Thuderbolt 4, but misses the PBS menu - unlike Matisse and Vermeer
It struggles with PCIe-Tunneling and PCIe Loophole ~ in order to pass x16 GPU lanes over to TB4
While Vermeer has pops and audio issues, thanks to it's branch prediction ~ even on a fixed allcore. Making only Matisse workable with TB4 
Ignoring the lack of driver support from Asus's own support page


ManniX-ITA said:


> And today hopefully DHL will deliver these:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> F4-4000C14D-32GVK - G.SKILL International Enterprise Co., Ltd.
> 
> 
> Ripjaws V DDR4-4000 CL14-15-15-35 1.55V 32GB (2x16GB) Ripjaws V series DDR4 DRAM memory is designed for sleek aesthetics and performance, making it an ideal choice for building a new PC system or for upgrading your system memory.
> 
> 
> 
> 
> gskill.com


Aah you bought them
Be sure to swap the thermalpad or fully remove the cooler
A half cooled IC is a not cooled IC ~ it likely behaves better without the cooler itself
As the heatsink was designed for A0 PCBs ~ where A1/A2 only hit half of the cooler


Spoiler: Broken Ripjaw's Design



Not my hand, but well noticeable










I saw them, but 1.55v XMP 
Soo still hold my eyes on the 16-16-16 1.4v Ripjaws (16 and 32gb)


----------



## CarnageBT

Veii said:


> CTR should read what SMU report
> But Curve Optimizer will change how FIT defines the rating of each core
> The highest and lowest will mostly remain the same.
> The highest will always remain the same
> 
> What does influence it , are powerplans, chipset drivers and when FIT has a bad day
> No, it's normal ~ but the average values should stay nearly identical and the peak values will stay on the same cores
> 
> Loadlines, better powerdraw, different CO values and disabling Board-Manufacture's Cheating
> (manually enforcing PBO, manually enforcing loadlines or 12V expanders)
> manually enforcing procODT & removing other latency enchancers
> 
> All these will change potential highest OC and boosting behavior
> It's normal , it's not CTRs fault
> 
> 
> You did accomplish something. You found a flaw in your potentially stable old set
> It's cores that where crashing
> But you can let it loop, (one test before and this) - to see if the same core crashes
> 
> Very likely your CO values are not soo good
> Soo i guess back to ground 0
> 
> Try fixing it by checking which cores consistently crash
> You can sort y-cruncher to individual cores too
> (it loves to crash CTR "stable" results) 😏
> 
> My go to test for CPU stability, before finishing it off with OCCT Extreme AVX2 ~ couldn't make p95 ever useful to me
> Soo at the end it's either bad CO value or not soo good loadline
> Just need to figure out if it's too much vdroop or lack of voltage
> 
> If you can't figure it out, drop it to +150
> and add +10mV positive vcore offset
> that should be about in line with the big next frequency strap jump
> 10-15mV positive
> 
> One thing you should also consider with "offset" voltages
> Is that board-partners on stock have different baselines for automatic "offsets"
> Once you go to "offset mode" , it does reset back to AMDs specified defaults
> It can very often be "too high" or "too low" ~ with a significant difference. Like it's very clearly visible once board-partners where cheating
> 
> Soo sometimes what is positive offset for one, might need to be negative offset for the other
> (looking at gigabyte and msi with negative required offsets)
> Or ASUS with nearly always required +5-10mV offsets
> (on purely stock operation)


I'm up. Be on the computer in 5. Need coffee. Badly! Lol


----------



## Veii

CarnageBT said:


> I'm up. Be on the computer in 5. Need coffee. Badly! Lol


Alc and then coffee is a bad idea
Don't drink coffee, unless 2h have passed (after waking up)
OCers life-advice 

Good Morning


----------



## mongoled

CarnageBT said:


> Ughh.. I'm so frustrated. Feel like I didn't accomplish anything today. Can't even establish a solid baseline at cl14. Is a 3600/1800 baseline useful? We can likely establish that since my XMP profile defaults to cl14/3600. We started today with 3733 and quickly moved onto 3800.
> 
> Do you guys feel like this is good ram and we can eventually get it to work? @Veii @mongoled . Otherwise, I'm entirely open to selling them and buying a new kit that isn't a NEW pcb and the first time you've seen something. I'm happy to buy what you guys recommend as the best overclockable kit and go with something fast, proven, so we can have an idea of what should work, then go from there. I feel like with this kit, it's a bunch of unknowns since it's new and is much more work than choosing a familiar kit that people have worked with a lot in the past and have a good idea of what's possible and what should/shouldn't work with predictable behaviour.
> 
> *I didn't mention but I have a decent cpu overclock; 250 ppt / 175 tdc / 185 edc / 1x scalar / +200mhz boost / CPPC & CPPC preferred cores enabled. Curve optimized per core individually with p95 using 84k/128k fft's.
> It's stable (with the default XMP memory settings lol). Can run prime95 small ftt's as well individual per core (single core) 84k and 128k fft's for hours. No clock stretching either, the odd time, ccd0/1 may have 0.1 stretch but for the most part it's perfect 1:1 mhz.
> 
> 
> *sigh... I feel slightly defeated and need direction, either continue with these kits, or give up, sell them, and buy something known to be fast and efficient. I bought 4 dimms because I kept seeing that dual rank > single rank. Is this true after tuning? or is 2x16gb tuned > 4x8gb tuned?
> 
> Plz help... have a few drinks to ease the sorrow 😓


I do my best to apply this golden rule, but sometimes I fail, don't become emotionally attached to success/failures while overclocking

😂😂

Now that's out the way, I don't think that's an option anymore, i.e. finding tried and tested memory as newer versions of the same products are not acting like older products.

Next, overclocking can be a never ending story, or ask depends how far your want to take it!

What is your end game? You need to decide a target frequency your would like and then work to get a baseline. In the search for a baseline you may come across other issues that are not to do with the memory, it's an a fine balancing act.

Personally I test each module independently so I know what each one can do and then match the two best pair together that I will put in the "bad slots", also testing each dimm independently let's you know what the ceiling is when using all four memory sticks.

Of the 4 modules I have 3 can do 3800 flat 14s, where as one needs tRDCRD set to 15, so when running all four together at 3800 tRCDRD had to be set to 15.

You could go to base, i.e. run them at 3600 but work on tightening the timings, once you have a stable baseline move from there.

I use this calculator to give me correctly sync values









Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com





NOTE: Click pencil top right to edit and accept to use app


----------



## ManniX-ITA

Veii said:


> The Thermal Syphon's look interesting - but only for 300W+ loads
> They behave very bad on low powerdraw units


Pity... I had high hopes but indeed news were lacking recently.



Veii said:


> Aah you bought them
> Be sure to swap the thermalpad or fully remove the cooler


I have ready the Alphacool heat spreaders for the WC block 
Already mounted a pair on the 4000C16 kit and they work better than the standard Trident Z RGB heatsinks (without WC block of course)



Veii said:


> Alc and then coffee is a bad idea
> Don't drink coffee, unless 2h have passed (after waking up)


LoL, I'm Italian can't spend 10 minutes after waking up without a coffee or I start freaking out eheh
2 hours wait is between a tragedy and the apocalypse


----------



## CarnageBT

@Veii @mongoled Ok, if it's back to ground 0 (cpu overclock), should I revert all memory settings to stock XMP (aka, auto everything for memory), then check on those cores and adjust the CO until stability has been reached, then from a stable CPU overclock, begin to work on memory OC again?


----------



## Veii

CarnageBT said:


> @Veii @mongoled Ok, if it's back to ground 0 (cpu overclock), should I revert all memory settings to stock XMP (aka, auto everything for memory), then check on those cores and adjust the CO until stability has been reached, then from a stable CPU overclock, begin to work on memory OC again?


Memory and the RTTs should be flawless - at least "usable flawless"
I mean you tested it
Use that as a 3600 baseline and try my advice to either
A.) Drop +200 to +150 and add about a +10mV offset (check the SVI before and after, or do the check with CTR boost tester)
Then repeat y-cruncher and see if you consistently between boots crash the same core

B.) take all your CO values - find the average (get them all together then / by the core amount)
use that as an negative allcore with the same +10mV offset , and see if you can pass it

Later maybe
C.) still wipe it and redo VDDG voltages ~ if it continues to error

I wrote you a big post what to do or how to behave - a mentioned one
Maybe Re-Read it 
====================
Sadness,
No PBS access for 1xxx, 2xxx (remain half of the bios) to fix TB4
At least it's a decent freq-set for 1.356v on 14nm


----------



## CarnageBT

Veii said:


> Memory and the RTTs should be flawless - at least "usable flawless"
> I mean you tested it
> Use that as a 3600 baseline and try my advice to either
> A.) Drop +200 to +150 and add about a +10mV offset (check the SVI before and after, or do the check with CTR boost tester)
> Then repeat y-cruncher and see if you consistently between boots crash the same core
> 
> B.) take all your CO values - find the average (get them all together then / by the core amount)
> use that as an negative allcore with the same +10mV offset , and see if you can pass it
> 
> Later maybe
> C.) still wipe it and redo VDDG voltages ~ if it continues to error
> 
> I wrote you a big post what to do or how to behave - a mentioned one
> Maybe Re-Read it


I'm just wondering if my CPU overclock is the issue, should I revert all memory settings back to stock XMP, then go from there so eliminate memory as a variable.

My CPU overclock is using CPU voltage (auto), Soc LLC max (lvl 1, stays where set, but doesn't overshoot at all), Soc switching frequency 800khz
250 ppt / 175 tdc / 185 edc / 1x scalar / +200mhz boost / CPPC & CPPC preferred cores enabled. Curve optimizer set individual based on running p95 per core which clearly wasn't enough to catch everything given that y cruncher is finding problems. *Is there a good CPU overclock with y cruncher thread I can refer to? to fine tune my CO negative offsets further. *y cruncher is still new to me, just got it yesterday, so I have some learning to do then will run through it to stabilize CPU oc before completing memory.

* SVI are you referring to CPU Core Voltage (SVI2 TFN)? On auto idles around 1.42, min 1.406, max 1.481. Under p95 small fft, runs at 1.131 (1.125-1.138)

edit: 
Used this in the past for setting CO per core using 84k and 128k, Single core Prime95 test script for Zen 3 curve offset...

but it seems it may have missed some possible errors, will now try this and run everything, CoreCycler - tool for testing Curve Optimizer settings


----------



## Veii

CarnageBT said:


> * SVI are you referring to CPU Core Voltage (SVI2 TFN)? On auto idles around 1.42, min 1.406, max 1.481. Under p95 small fft, runs at 1.131 (1.125-1.138)


Ignore prime95 
AVX2 world and mixed AVX workloads are different than common non AVX or purely AVX workloads
P95 is either random or you forgot something along the whole range of FFT ranges ~ to test

Y-cruncher has a nice area of tests, and OCCT can be used for the finish
Check SVI2, because offset mode can often run completely different voltages for the baseline
You have 15mV playroom - soo add +10mV and try option A.)


----------



## mongoled

@CarnageBT 
You want some droop! Take CPU LLC off 1 and put it to 3! (I use 5/6 but that's a different story). Same for CPU NB


----------



## CarnageBT

mongoled said:


> @CarnageBT
> You want some droop! Take CPU LLC off 1 and put it to 3! (I use 5/6 but that's a different story). Same for CPU NB


CPU LLC is auto, I only pinned NB/soc LLC to 1, so it stays at 1.1 (or wherever I've set it). This should be dropped?

CoreCycler - tool for testing Curve Optimizer settings seems like gold. It will do the individual per core testing like the other program I used, but for y cruncher

Edit: this program is able to test only the single thread on each core without splitting the load to the ht, unlink the other program which splits the load.


----------



## CarnageBT

I'm new to y cruncher,


Veii said:


> Ignore prime95
> AVX2 world and mixed AVX workloads are different than common non AVX or purely AVX workloads
> P95 is either random or you forgot something along the whole range of FFT ranges ~ to test
> 
> Y-cruncher has a nice area of tests, and OCCT can be used for the finish
> Check SVI2, because offset mode can often run completely different voltages for the baseline
> You have 15mV playroom - soo add +10mV and try option A.)





Veii said:


> Ignore prime95
> AVX2 world and mixed AVX workloads are different than common non AVX or purely AVX workloads
> P95 is either random or you forgot something along the whole range of FFT ranges ~ to test
> 
> Y-cruncher has a nice area of tests, and OCCT can be used for the finish
> Check SVI2, because offset mode can often run completely different voltages for the baseline
> You have 15mV playroom - soo add +10mV and try option A.)


Added 0.0125v (wouldn't let me add 10mv). Will go through individual core testing with Y cruncher to optimize the curve with the +12.5mv offset

Is there a specific set of tests you recommend for per core testing? I'm still to new to y cruncher to know which is preferred for CPU curve testing

Excerpt from the core cycler settings:
# y-Cruncher specific settings
[yCruncher]

# The test modes for y-Cruncher
# See the \test_programs\y-cruncher\Binaries\Tuning.txt file for a detailed explanation
# "00-x86" - 86/IA-32 since Pentium (BSWAP, CMPXCHG, CPUID, RDTSC, possibly others...)
# "04-P4P" - SSE, SSE2, SSE3
# "05-A64 ~ Kasumi" - x64, SSE, SSE2, SSE3
# "08-NHM ~ Ushio" - x64, SSE, SSE2, SSE3, SSSE3, SSE4.1
# "11-SNB ~ Hina" - x64, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX
# "13-HSW ~ Airi" - x64, ABM, BMI1, BMI2, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, FMA3, AVX2
# "14-BDW ~ Kurumi" - x64, ABM, BMI1, BMI2, ADX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, FMA3, AVX2
# "17-ZN1 ~ Yukina" - x64, ABM, BMI1, BMI2, ADX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, FMA3, AVX2
# "19-ZN2 ~ Kagari" - x64, ABM, BMI1, BMI2, ADX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, FMA3, AVX2
#
# The following settings would be available as well, but they don't run on Ryzen CPUs!
# "11-BD1 ~ Miyu" - x64, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, ABM, FMA4, XOP
# "17-SKX ~ Kotori" - x64, ABM, BMI1, BMI2, ADX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, FMA3, AVX2 AVX512-(F/CD/VL/BW/DQ)
# "18-CNL ~ Shinoa" - x64, ABM, BMI1, BMI2, ADX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, FMA3, AVX2 AVX512-(F/CD/VL/BW/DQ/IFMA/VBMI)
#
# "00-x86" should produce the highest boost clock on most tests
# "19-ZN2 ~ Kagari" is optimized for Zen2/3, but produces more heat and a lower boost clock on most tests
# Default: 00-x86
mode = 00-x86


Edit: 
Running it through the default setting for y cruncher, the tests include bkt, bbp, sft, fft, n32, n64, hnt and vst 
(includes everything @Veii suggested yesterday except for C17 test but I was consistently crashing on n64 and possibly vst, so this should work well to optimize my curve)

After +0.0125v to CPU core voltage, on single core tasks (y cruncher tests on individual cores), I see SVI2 around 1.44, max 1.494. Is that ok? I remember before adding anything to core voltage, so auto, the highest I had seen running p95 single core was 1.5v on auto, so I assume this looks good? Don't want to kill my processor with volts. 
What is the highest "safe" voltage for ryzen 5000 cores for single core?


----------



## Veii

CarnageBT said:


> What is the highest "safe" voltage for ryzen 5000 cores for single core?


I can not give you a concrete answer
1.5 is AMDs public spec
1.55 is an advice but voltage doesn't mean anything








CoreCycler - tool for testing Curve Optimizer settings


Here's v0.8.0.0 RC4, only use it if you're willing to beta test. 👆 https://github.com/sp00n/corecycler/releases/tag/v0.8.0.0-RC4 @Theo164 It's interesting, I've never been able to have Y-Cruncher actually fail a stress test. It's either passing for me or rebooting the whole system. 🤷‍♂️ And...




www.overclock.net




This thread has interesting information
some sensors allow reports beyond 1.7v in specific scenarios
FIT throttles at 1.5v under specific reasons
1.4875 is a good value to hold

but yes, fit can allow 1.5v sometimes ~ and it can allow 1.55v sometimes
do with this random piece of information what you want 

y-cruncher 1 , 1 (allows you to deselect and select threads numbers)
1,7 (will select all tests)
0 to start

You want to run all tests for 4 loops ~ repeating myself for the 4th time now
AMD max overclocking voltage this thread is interesting too


----------



## musician

nvm


----------



## craxton

Veii said:


> Loadlines, better powerdraw, different CO values and disabling Board-Manufacture's Cheating
> (manually enforcing PBO, manually enforcing loadlines or 12V expanders)
> manually enforcing procODT & removing other latency enchancers
> 
> All these will change potential highest OC and boosting behavior
> It's normal , it's not CTRs fault


highly noted, now about this 4900mhz PX profile, this is just one core correct?
starting to understand a little more (the vid or any vid out there in fact) is no help with how its updated now. (vid being video) 

the one thing i cant quite understand is the (dont think its public released yet) but its been
added to the latest update so i dont think itll be hard to understand what im talking about.
(is there a place besides the patron page) to discuss with other users?

ive noticed that P1 profile is all core, PX is one core? and unsure what P2 is for.
(i think) you mentioned that you can overdrive what CTR has already, (thus using CO ?)
i kinda tried but my vdroop went from 0 always to well 1.xx to which the CO i used was mild at best nomore than -8
and positive 0 (does it make a difference) if you set negative 0 vs positive 0? does this change curves behavior?

(yes) i have lots of questions but some im unsure if im at liberty to say until release.
so ill leave those be. (only thing i changed) in bios was auto board limits to motherboard
then manual leaving those all to auto.

thats what i believe changed my core values. (none the less, ill take the better values over the other results)
(turning on dram latency enhance makes me unstable in my memory overclock, or at least makes it worse)
on the 1600AF however it did help.
------------
(this EDC bug, how is this triggered? asked this several times but never got any answers on it)
unsure if its not answered bc someone might see it and say well not letting that happen anymore
and patch it or what, but if someone knows how, they can send me a PM (please)
if its well known, then a reply will do


oobymach said:


> Yeah it's a viper kit, it reports as A0 in Thaiphoon, also GDM is greyed out in bios, can't change it from auto setting.


if your GDM is greyed out on MSI boards, usually its bc (down below) in dram overclocking selection
you have selected 1t (you can go to Advanced, amd overclocking) and go in the ram section, and set it to 1T that way and
itll work) unless your after 2T unsure only seen mention of being greyed out. (if you figured this out already, my apologies)


----------



## Veii

craxton said:


> ive noticed that P1 profile is all core, PX is one core? and unsure what P2 is for.


Read the manual 

P2 is an allcore , and matches the diagnose recommendation
P1 is a game frequency and usualy matches AMDs P0 state = 3.7ghz ~ 80% load
PX is a burst boost frequency with peaks
1 core = high, 2 core medium, 1/4th core (3 or 4) being PX Low
There is a thread here for CTR



craxton said:


> craxton said:
> 
> 
> 
> the one thing i cant quite understand is the (dont think its public released yet) but its been
> added to the latest update so i dont think itll be hard to understand what im talking about.
> 
> 
> 
> and positive 0 (does it make a difference) if you set negative 0 vs positive 0? does this change curves behavior?
Click to expand...

0 = zero, no change
PX is public at this point, but it's not switching fast enough
OB is dynamic which should replace PX
Yet often OB is lower and there to smooth out the boosting curves
P1 and P2 OverBoost [feature] exists to create speedstep-straps
PX = rocket, exists for benchmarks and specific isolated core workloads

If neither PX nor P1,P2 are loaded (PX to work you need to run all 3)
Then it switches to AMD mode ~ back to boosting mode / as replacement and "bettered"up version of the Dynamic All-Core ASUS feature


craxton said:


> (this EDC bug, how is this triggered? asked this several times but never got any answers on it)


EDC Bug,
When you hit EDC limit, the CPU package throttles ~ first voltage later frequency after it passes it's low/high strap value
The bug tells the CPU to always throttle ~ but rather reverses the throttle
idle = throttle and throttle = perf
On matisse this functions, as it breaks FIT and allows "on load" to disable the ceiling and let it "infinitely" pull power (EDC-A)
On Vermeer, there are other package throttle sensors and algorithms and it will slow down to 30ns or higher (L3) . It will slow fabric internally down too - same as the GMI link and interconnect links between cores

Performance on load will be less than performance on 550Mhz
There is also an EDC bug thread here, for Matisse


----------



## jomama22

ManniX-ITA said:


> And today hopefully DHL will deliver these:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> F4-4000C14D-32GVK - G.SKILL International Enterprise Co., Ltd.
> 
> 
> Ripjaws V DDR4-4000 CL14-15-15-35 1.55V 32GB (2x16GB) Ripjaws V series DDR4 DRAM memory is designed for sleek aesthetics and performance, making it an ideal choice for building a new PC system or for upgrading your system memory.
> 
> 
> 
> 
> gskill.com


Personally, at that cost level, you may as well just watercool the cpu first lol. You'll get much more performance out than any amount of tighten timings will get you.


----------



## ManniX-ITA

jomama22 said:


> Personally, at that cost level, you may as well just watercool the cpu first lol. You'll get much more performance out than any amount of tighten timings will get you.


Yes it's insane 
I know... I got addicted. Tried to fend it off but went down the rabbit hole.
Have already spent more than what costs a city car for my next build so don't worry eheh
A few loops and 1000W TECs will do nicely the job...


----------



## 1s1mple

@Veii How come you recommend the 1usmus_v3 config over the Extreme1 Anta777 config in TestMem5?


----------



## ManniX-ITA

1s1mple said:


> How come you recommend the 1usmus_v3 config over the Extreme1 Anta777 config in TestMem5?


Look in the DATA sheet:









Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com





For all errors you get with the 1usmus config there's an hint on what to look.
Anta config is good but if you get an error you are on your own.
Better to first pass the 25 cycles with 1usmus and then go over with the Anta config if you want to be extra safe.


----------



## CarnageBT

@Veii or anyone for that matter. I'm pretty sure this is common knowledge, but it's all too new for me =P

"A "strong" RTT, meaning a low divider , will let more amperage pass to the dimms
Pretty much increasing the effectiveness of the VDIMM you push
And is able to kill PCBs if they are sensitive
We want as less needed RTT as possible
Soo a higher divider on RTT_NOM and RTT_PARK
RTT_WR is special, soo keep it at /3 till you exceed 1.55v and have maxed out both RTT's at /7 already "

When you say this, are you referring to the RTT # (1/2/3/4/5/6/7) or are you referring to the ohms?

Ideally we want the least RTT and a higher divider on NOM / PARK.
Does this mean best would be RTT 1 (240 ohm)? or the RTT 7 (34ohms)?


----------



## mongoled

@CarnageBT
RT Park: RTT 7 (34ohms)

The other end of the scale is danger land

😂


----------



## 1s1mple

ManniX-ITA said:


> Look in the DATA sheet:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> For all errors you get with the 1usmus config there's an hint on what to look.
> Anta config is good but if you get an error you are on your own.
> Better to first pass the 25 cycles with 1usmus and then go over with the Anta config if you want to be extra safe.


Thanks, i wish these made by Veii spreadsheets were included in the OP

Edit: Big props to @chitos123/to whoever made those Google Ryzen Calculator spreadsheets


----------



## mongoled

CarnageBT said:


> When you say this, are you referring to the RTT # (1/2/3/4/5/6/7) or are you referring to the ohms?


The numbers are the dividers, they devide by 240 to give you the ohms, example

240/1 = 240 ohms
240/7 = 34 ohms
Etc etc


----------



## CarnageBT

mongoled said:


> @CarnageBT
> RTT 7 (34ohms)
> 
> The other end of the scale is danger land
> 
> 😂


With all of the increase in voltages for me to "attempt" to run 3800/1900, which also generates a lot more heat, should I not just focus on 3733 1t as a goal. 

Ideally I want high sustained boosts for gaming. Specifically 1080p low settings 240fps target for the 1% lows. Aka. Insane frames lol
*although I understand memory oc is more important for this goal vs 100fps 1440p


----------



## Veii

1s1mple said:


> @Veii How come you recommend the 1usmus_v3 config over the Extreme1 Anta777 config in TestMem5?
> 
> 
> 
> ManniX-ITA said:
> 
> 
> 
> Look in the DATA sheet:
Click to expand...

Worked only with it for the 2-3 years, figured most of it out
Also it's more effective from a personal standpoint - but too effective
Thermal Equilibrium won't be reached ~ meaning you have to increase it to 20 cycles
Different patterns different behavior. i don't know anta's config, and haven't had a good communication with him or people who follow the person
Same is with 1usmus on some parts, if i have to follow public opinion. Personal chat is different

Don't feel like i want to learn the anta config. Wasted too much time learning 1usmus_v3 & it's testing is consistent + still finds errors even with Vermeers autocorrection

That's about it
1usmus_v3 is more effective, but too fast
20-25 cycles is by luck the same length as anta's , and the first i know decently well so far

Also this one is more up-to-date








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com




TM5 page (it shouldn't be invincible)

Stopped supporting the google docs for now
Have a bigger plan in mind for the config, and i want to add more value to the docs i made
Later it can be transferred over to the public docs
Just again "bigger plans" and don't want to let chitos deal with my experiments. Better to deal myself with the editing on the own docs


CarnageBT said:


> Ideally we want the least RTT and a higher divider on NOM / PARK.
> Does this mean best would be RTT 1 (240 ohm)? or the RTT 7 (34ohms)?


Described it twice, overdescribed it even
Low value, less value, low RZQ
High divider low ohm value ~ same thing
MSI has it written out, other board-partners do not ~ because these translation can make bugs from AMD CBS


1s1mple said:


> Thanks, i wish these made by Veii spreadsheets were included in the OP


This is not my spreadsheet
A lot of research, and all these big complicated docs commands belong to @chitos123
All of the credit, as this is hard work

The "bigger" contribution team is halfway known halfway not
Not everyone wants to be known - but maintaining big docs is painful. A lot of cudos go to chitos !

I maintain my own mini sheet which people keep purposely breaking & here and there the Zen Ram OC docs
It's more then enough work. Chitos did a lot
Soo i don't want to be a burden ontop of all, and maintain my little thing till the "bigger reason" is finished ~ somedayTM


mongoled said:


> The numbers are the dividers, they devide by 240 to give you the ohms, example


RZQ and DQs should have changed to 480 now
But the bioses do not reflect these changes
It's unclear what runs really - but lower is better , ignore this ohm value it likely is wrong at this point


----------



## oobymach

Veii said:


> I don't drink alcohol often, to very rarely
> But consider coming back to Germany ~ depends if i can find any work there to pay my rent
> At least for a bit of time
> Hehe, glad to see you had success
> 
> It was 2000H/s for me between stock & 2100 FCLK
> Big jump
> I sadly haven't seen this option since quite some time. I think the last time was on an MSI board
> Probably with bios mods it should appear
> 
> Where is it listed, where does it stay ?
> 244A EDC limit 🤭
> 
> You get a lot of rejected shares
> Might want to switch the algorithm - and be sure it won't touch the GPU at all
> 
> 
> It's really great that you chain together own tests
> But unless you know the algorithms, chaining random tests together wont make them fail
> Every cell needs to be tested and a little IC has over 1.3 million cells , - soo that times 8 or times 16 on dual rank
> not every of these lithographic cells will be able to run the tight timings
> 
> No way around going with the typical routine
> Only looping one test won't test the properties of the dimm
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Whatever you pick , use the above manual mode - else rounding errors stack


Thanks for that tool but idk how it works I just use the one in 1usmus ryzen ram calculator, also wasn't hammering with just one test but all 5 of the mirror tests in the order 3,4,5,14,15,3,4,5,14,15,3,4,5,14,15 put in the profile test sequence line because I noticed on unstable clocks it was the mirror test that would give errors so I set it to run them all back to back figuring if there was any instability it would show quickly and it does, within the first few seconds usually if the timings are off.

Also going to test with 2t timings since you pointed out with gdm 1t can be ignored. Is there any way to disable gdm with high ram speed? Nevermind, it disabled when I set 2t timing.


----------



## mongoled

Veii said:


> This is not my spreadsheet
> A lot of research, and all these big complicated docs commands belong to @chitos123
> All of the credit, as this is hard work


👍👍😊


----------



## Veii

oobymach said:


> Thanks for that tool but idk how it works I just use the one in 1usmus ryzen ram calculator, also wasn't hammering with just one test but all 5 of the mirror tests in the order 3,4,5,14,15,3,4,5,14,15,3,4,5,14,15 put in the profile test sequence line because I noticed on unstable clocks


Yes it's not how it works
To mirror data, data has to exist
Data won't exist if nothing is written

Nothing can be written, if data won't exist
Data can not exist if you keep copying air back and forth - empty data
It can bruteforce the "copy" mirror! algorithm but it will only error if your transitions are bad
It won't show why the transitions are bad and it won't test primaries at all

Pretty much wasting time bruteforcing refresh cycles and back and forth transfers out of thin air
You maybe test the PCB that way well, and maybe it has a reason to fail (i would be worried rather)
Maybe it increases the testing strain and heats them up further
But on it's core and definition it's problematic at best ~ and spilling fake results, at worst

Please abandonee this method, unless you are very well aware how the steps are layed out & can make an own config
The testing order matters a lot ~ don't really change it  


oobymach said:


> Also going to test with 2t timings since you pointed out with gdm 1t can be ignored. Is there any way to disable gdm with high ram speed?


There are many methods
Information is spread across this thread and likely across other threads ~ kind of sad, but it's too much information to write a huge docs , while you still learn every experiment-day something new. Soo no unified guide can be written yet

Increasing ClkDrvStr helps
It shows badly powered dimms, soo RTT focus helps
It runs them at fullspeed how they should be, soo bad timings/issues will be visible
PCB crashes and powerdown requirements (tCKE) will be shown

2T and GDM on , require the same VDIMM to run ~ optimizing it around that is the goal
There is no magical wand that helps ~ maybe just ClkDrvStr helps a lot and low procODT
Haven't seen any ClkDrvStr dependency, except that PCBs can crash on too much of it
So far the only option, which works "alone" i feel like


----------



## CarnageBT

Thanks for explaining the RTT thing to me so many times. I finally get it lol. I was looking too deeply into the meaning of divider, instead of taking it for the literally meaning of the number used to divide. lmao. 

Currently working on getting things stable (fclk in ycruncher) from where Veii left me yesterday. almost there


----------



## Yviena

Hmm seems that 1.46V+ is too much for my sticks with RZQ 7/3/1 reducing the voltage to 1.44v severely increased my stability with these timings., though i still seem seem to get error 3 in TM5 upping the TRWDR to 10 doesn't seem to fix it.


----------



## Veii

Yviena said:


> Hmm seems that 1.46V+ is too much for my sticks with RZQ 7/3/1 reducing the voltage to 1.44v severely increased my stability with these timings., though i still seem seem to get error 3 in TM5 upping the TRWDR to 10 doesn't seem to fix it.
> 
> View attachment 2513246


Try CAD_BUS 40-20-30-20 , drop tRTP to 8
and increase tWTR_ , to 5-15


----------



## ManniX-ITA

This new kit is finally something different 
Ridiculously expensive but at least...

tRDCRD at 16/4000MHz is easy peasy now.
Works fine with tRCDRD 15 as well but with the terrible XMP timings.
Lots of work to do to build a decent profile.

This is the XMP profile:


----------



## Veii

ManniX-ITA said:


> This new kit is finally something different
> Ridiculously expensive but at least...
> 
> tRDCRD at 16/4000MHz is easy peasy now.
> Works fine with tRCDRD 15 as well but with the terrible XMP timings.
> Lots of work to do to build a decent profile.
> 
> This is the XMP profile:
> 
> View attachment 2513251
> View attachment 2513252


Try to figure out what CCD_L is on it , according to the bios readout
633 RTTs will work perfectly on a dual channel board
might even go up to 6-3-4 because of SMU 56.50 (when you want to update away from AGESA 1.2.0.0) - and drop procODT by one 

Grab that CCD_L and use it as tRRD_S multiplier for tFAW
little trick but helps quite a bit
also use it on tRCD*2 + tCCD_L= tRAS
with this, the Rev.E was stable on any speed as long as i keep it's "annoying" tRCD up and the higher required tRAS


----------



## T[]RK

Veii said:


> run diagnose, later run tune
> You will see how much vdroop you get and how different VID from V-TEL is
> Match it, it has to be less than 10mV apart from other.


Long time ago i used CTR 2.0 (RC5) and complete all: Diagnostic, Tune and Stability Check. At the end i got 4425 [email protected] for my Undervolt. But i saw that under load CPU TEL (V) lower (obviously) then CPU VID (V) on 19mV. How to match them? When i manually enter new value (for example 1125mV = 1106mV) there always 19mV gap. It's only possible with LLC? Or I just must set CPU VID (V) always higher on 19mV?

It's worked with vSOC, when i can set value in BIOS, add load and check vSOC under load and correct entered value to find lowest gap between SET and GET (it was 6mV). But i don't think it will work with CPU VID on my motherboard...


----------



## jomama22

Veii said:


> Yes it's not how it works
> To mirror data, data has to exist
> Data won't exist if nothing is written
> 
> Nothing can be written, if data won't exist
> Data can not exist if you keep copying air back and forth - empty data
> It can bruteforce the "copy" mirror! algorithm but it will only error if your transitions are bad
> It won't show why the transitions are bad and it won't test primaries at all
> 
> Pretty much wasting time bruteforcing refresh cycles and back and forth transfers out of thin air
> You maybe test the PCB that way well, and maybe it has a reason to fail (i would be worried rather)
> Maybe it increases the testing strain and heats them up further
> But on it's core and definition it's problematic at best ~ and spilling fake results, at worst
> 
> Please abandonee this method, unless you are very well aware how the steps are layed out & can make an own config
> The testing order matters a lot ~ don't really change it
> 
> There are many methods
> Information is spread across this thread and likely across other threads ~ kind of sad, but it's too much information to write a huge docs , while you still learn every experiment-day something new. Soo no unified guide can be written yet
> 
> Increasing ClkDrvStr helps
> It shows badly powered dimms, soo RTT focus helps
> It runs them at fullspeed how they should be, soo bad timings/issues will be visible
> PCB crashes and powerdown requirements (tCKE) will be shown
> 
> 2T and GDM on , require the same VDIMM to run ~ optimizing it around that is the goal
> There is no magical wand that helps ~ maybe just ClkDrvStr helps a lot and low procODT
> Haven't seen any ClkDrvStr dependency, except that PCBs can crash on too much of it
> So far the only option, which works "alone" i feel like


When you say "pcbs can crash in too much clkdrvstr" do you mean too much as in too much resistance (the ohm value is too high) or do you mean the ohm value is too low?

Reason I ask is because it's quite confusing as clkdrvstr would be "higher" with lower resistance values...


----------



## ManniX-ITA

Veii said:


> Try to figure out what CCD_L is on it , according to the bios readout


According to BIOS readout meaning how? 

I have the Taiphoon Burner report were is reported tCCD_L min:



Spoiler: Report

















Veii said:


> 633 RTTs will work perfectly on a dual channel board
> might even go up to 6-3-4 because of SMU 56.50 (when you want to update away from AGESA 1.2.0.0) - and drop procODT by one
> 
> Grab that CCD_L and use it as tRRD_S multiplier for tFAW
> little trick but helps quite a bit
> also use it on tRCD*2 + tCCD_L= tRAS
> with this, the Rev.E was stable on any speed as long as i keep it's "annoying" tRCD up and the higher required tRAS


Will check it thanks.
The tFAW is quite problematic indeed as tRRD_S/L can't go lower than 5/10.
But I have still to test a lot...

Seems this kit is also much more flexible and doesn't strictly need high ClkDrvStr.


----------



## T[]RK

Veii said:


> Try to figure out what CCD_L is on it


Will it work on Samsung B-die too? I founded this value in Thiaphoon Report for my modules.


----------



## CarnageBT

Was working away at stablizing those settings. Each time y cruncher would throw an error for logical core X, I would turn down the curve on the respective core by 1 tick. Then I got to thinking, I know my memory OC isn't stable, so do I truly know it's the curve or other possible things?

I took myself back to square 1, almost (retained my previous curve), but have reset all memory overclocks to stock XMP, and am running y cruncher on each core for 10 minutes to check for errors. At least this way I'm can be relatively certain any errors presented are from the CO and not other settings. Once I'm certain I have a stable CPU OC, then I can move on to memory.

Aside y cruncher, are there other tests I should perform to verify my cpu oc is stable? I can run per core p95, but @Veii has mentioned he doesn't find it useful. Anything other than y cruncher for cpu stability testing?

Edit: 
Once I have this finished, I'll do the standard y cruncher all test x4, then OCCT Extreme AVX2 to finish it off. I hope that should validate a stable CPU OC.
No need for aida64 for CPU stability right?


----------



## CarnageBT

Does y cruncher create a log anywhere? I hate when I'm testing it I need to stay and pay attention to what it's doing. Otherwise, I walk away and return to my desktop with nothing open and no logs to see where it crashed. I just know it failed and rebooted somewhere along the line lol.


----------



## Yviena

Veii said:


> Try CAD_BUS 40-20-30-20 , drop tRTP to 8
> and increase tWTR_ , to 5-15
> View attachment 2513250


Hmm I seem to get error 14 when it's set to X 20 X 20 motherboard won't allow me to set TWTR_ to 15 max is 14 it seems like.


----------



## PJVol

Yviena said:


> TWTR_ to 15


He supposedly meant twtrs 5 and twtrl 15 ?


----------



## Veii

jomama22 said:


> When you say "pcbs can crash in too much clkdrvstr" do you mean too much as in too much resistance (the ohm value is too high) or do you mean the ohm value is too low?
> 
> Reason I ask is because it's quite confusing as clkdrvstr would be "higher" with lower resistance values...


CAD_BUS are impedances, RTTs are termination impedances
RTT's you want as low of an Ohm value as possible
CAD_BUS usually too, but here ClkDrvStr is different. It behaves exactly like an impedance should do ~ as a strong multiplier
PCB Crashes do not mean deaths, but just hickups and crashes



T[]RK said:


> Long time ago i used CTR 2.0 (RC5) and complete all: Diagnostic, Tune and Stability Check. At the end i got 4425 [email protected] for my Undervolt. But i saw that under load CPU TEL (V) lower (obviously) then CPU VID (V) on 19mV. How to match them? When i manually enter new value (for example 1125mV = 1106mV) there always 19mV gap. It's only possible with LLC? Or I just must set CPU VID (V) always higher on 19mV?


Both
You can try to fix it with LLC, or just add positive v-core offset, to fix it
changing scalar does also do it ~ soo move at X2 or lower


ManniX-ITA said:


> According to BIOS readout meaning how?


Most bioses have an SPD info tool - MSI has it too _~somewhere~_


T[]RK said:


> Will it work on Samsung B-die too? I founded this value in Thiaphoon Report for my modules.


Mostly it's used as tBL 4 for single sided 8 chips
8 for dual sided 16 ICs

But tCCD_L is different by dimms
Mostly JEDEC does use +6 there , sometimes +7 ~ depends
My Rev.E Max are +7
My A0 B-Dies where supposedly +6 ~but +4 works as tBURST option
tBURST 2 , is then a stacking exploit for SR, and 4 for DR as "exploit"

Overall tRAS that way up and tFAW that way up always runs
Urg(ent) Refresh Timing now with 56.50+ is 4
SubUrgRef is 6 "on stock"

I think that's how it scales
Urgent you can get down to 1 but that needs tricks ~ the tRAS+1=tRC, 1x tFAW exploit.
It needs a lot of rebalancing to make it work

But as long as i followed the tCCD_L rule, and usually how bioses predict timings from XMP
it couldn't get unstable. Just tRCD sometimes broke and needed an increase for the freq
It's sttill slower than a clean tRCD*2 = tRAS method
But for this "clean" transition to work ~ you often need to shift timings elsewhere.

The tCCD_L method, although slower, always works
It's how JEDEC and bioses operate with their XMPs
The tFAW trick is just a bonus ~ because it isn't always *4 anymore
Some partners run tRRD_L * tCCD_L to get max tFAW
But then bioses have a tFAW limit , 60 doesn't work for example


Yviena said:


> Hmm I seem to get error 14 when it's set to X 20 X 20 motherboard won't allow me to set TWTR_ to 15 max is 14 it seems like.











mmm it's _ - X - X - X as potential issue
one of the last 3
Or tCKE issue if powerdown flag is enabled while tCKE is at 1

Hmmm, you can try X - 30 - 20 - 24
but check first if tRTP fix, does fix it and see if you can change tWTR_L to 15
I know it can work.
Else you can do it also via HEX inside AMD CBS ~ but once you change it there, the whole profile only accepts HEX values
soo make first another profile before you attempt such things

Another option is 60-20-20-24
But i'm worried that you need the 3rd value over 30 , to fix broken memory training

These 0mb mirror moves, are tiny timeout issues
can be transition timings or powering. mostly a signal choke/cut (loss)
More power or more vdimm will make a noisier but stronger signal & fix it - or just better balanced powering
(or different timed transition timings ~ for example tRRD_, tWTR_, tRDWR, tWRRD, tSCL, SD & DD's)


----------



## musician

If I survieved 3 hours of y-cruncher, is my memory stable enough? I tried to select tests with higher impact on the memory.


----------



## MyUsername

musician said:


> If I survieved 3 hours of y-cruncher, is my memory stable enough? I tried to select tests with higher impact on the memory.


I like to stress the memory with TM5 with an extreme config anta777 or 1usmus_v3 and let it run for a few passes. I use y-cruncher to stress the soc IF with occt after to finish.


----------



## Veii

I have some challenge for you guys
For a client build, location & money doesn't play a role
Can anybody help me import a pack of 4 from
*HOF4RJL4BST4400T19MF162CL*
4x 8GB 4400 C19-19-19 @ 1.4v
@fcchin thinking about you , for someone who can get GALAX dimms 
* for a set of 4, GALAX needs to be contacted directly ~ as they sell mostly only a Set of 2
** only 50 pieces were made and it's not on their webstore yet (news is 2 weeks old)


----------



## Yviena

@Veii seems that tRDWR was somehow reset to 10 putting it to 9 made me reach 15 cycles before a error 2 happened with the same settings I showed a couple posts back that means it's resistance somewhere like procODT, or cadbus that's not totally optimal right?


----------



## Veii

Yviena said:


> @Veii seems that tRDWR was somehow reset to 10 putting it to 9 made me reach 15 cycles before a error 2 happened with the same settings I showed a couple posts back that means it's resistance somewhere like procODT, or cadbus that's not totally optimal right?


This counts in the tRTP change ?

I personally feel that tWR should be ending faster - same for tRTP **
Although tRTP has playroom (as long as it's inside tRFC range), tWR rarely when you run an already bursty tRFC
Could be also just thermal equilibrium (heat) issue or a random fridge at night going on. Oor also just switching from daylight power to cheaper night-savings

If it was with tRTP 8 , then try to drop tWR to 12 and see what happens 
I do think the rest is alright , else it would create issues far sooner than now
After Cycle 9 to 19 it mostly is some offsync that takes a lot of times to appear or "leak" from on IC to another *
* In the sense, on continuous done loops, it could tiny bit shift over ~ till at the end you are met with a place between dimms & then the error can not be masked anymore

But it can also be a typical time effect by heat. Really depends 
Wish you would've let it run for 2 more cycles to at least see what kind of effect will happen.
Will it snowball with errors, or just was a tiny choke.
Heat will snowball, and a house-current (ripple) change would also snowball strongly 

** i personally also feel, that you can either tighten SD,DD's a bit or lower tRDWR once more 
~ probably both when the rest is tight.
Increasing SD, DD's leads to more perf , but can overlap and cause issues.
The stepping between RDRD & WRWR as +2 you can keep up. +3 or further exotic stuff i run, needs a full redoing on tRRD_ and tWTR_
These ones you should touch/tighten at the very end, as they will limit any low primaries. Where low primaries are far more worth than just tighter transition timings


----------



## craxton

Veii said:


> There is a thread here for CTR


ive checked it already, its guide is rather outdated from what i can tell. 
and mostly has to do with the first iteration. (the thread i found) wasnt very long
nowhere near the length of this. i think like 40 pages max or so....



Veii said:


> 0 = zero, no change


so it doesnt matter (inside bios) what you set as negative or positive if you leave it set to 0...
im seeing CTR stated to not use curve but....what if one does, wouldnt this perhaps yeild better results?

(i did test but as my questions show im not equipped enough yet) and Vdroop happened quite a bit. 
OB wasnt on the free public version that i obtained, current version has a PX of 4950-XXXX-XXXX and 
voltage settings....i got 4900 to run all cores, with cpu VID and TEL values staying neck and neck with each other (per you stating they needed to be rather close with each other)
forgot how far apart the tolerance levels were exactly as i can look back three or so pages ive been watching for less than 10mv.
as anything other than that above 4850 seems to not stay running (only using TM5 to hit max clocks that is)
benchmate can hit all cores (one by one) at 4900 
(without anything adjusted in the bios) but its not what CTR said i "could" do. 
4850 all core is what it states. (again, if the manual was up-to-date) id probably 
not bother wondering what was what 
but with what info you shared thats when i was able to get the 4900 all core stable (ish)



Veii said:


> If neither PX nor P1,P2 are loaded (PX to work you need to run all 3)


so, to further question you can adjust what CTR says you can run, but 
how to configure this to where DIAG mode will auto set this 
is what one wants? (im unsure if someone in CTR thread would 
be able to assist as good as you) not to many replies over there in general mostly qustions/complaints
or what one got.



Veii said:


> EDC Bug,
> When you hit EDC limit, the CPU package throttles


i did hit (in CTR) 120 EDC limit as it was yelling EDC limit reached while running 
180-120-240 but you mentioned the bug needs triggered on boot. so im assuming 
i need to adjust PPT, EDC, TDC in bios. (google does not know what it means)
to "trigger" ryzen EDC bug lol anyhow appreciate the response.


----------



## craxton

Veii said:


> But if you want to overdrive CTR a bit - a slight negative CO of 3 with CTR's Overboost feature ontop + little postive vCore offset ~ can run 5ghz allcore
> Just because CTR does only run OC mode.


(nevermind on an answer about using curve and voltage offset) 
you read my mind two days ahead....(your temp limits must be pushing as your overclock is (body wise) is outthere bud)
but none-the less you did give me an answer to which both posts you spoke to me about will now 
be saved and booked marked properly.

(is it possible that if im asked) to share some of this information with others elsewhere? 
Credit where credit is due ALWAYS! (i now know why you use this color blue or think so, (so much easier to read)  
unless its your favorite color or something... anyhow


----------



## munternet

Thanks to @ManniX-ITA for all the help getting me started with AMD memory overclocking and solving my in-game issues


----------



## ManniX-ITA

Veii said:


> Most bioses have an SPD info tool - MSI has it too _~somewhere~_


Oh yes I forgot about that, Memory-Z is called 
Reports same as Taiphoon, 6 tCK for tCCD_L

If I use it for tRAS that would be 38 with tRCDRD at 16.
Now I'm running with 32; is there any exploit possible? 
Lower tRC or tRP?

Found a way finally to use tRRD_S at 4.
This new kit is indeed much better than all the rest.
Can run it lower with tRDWR/tWRRD 11/1 and tCKE 1.
Doesn't like high ClkDrvStr like the 4000C16.

How could I use tCCD_L for tFAW? x2=12 or x4=24?
Could help doing something else crazy?

Right now I'm using this profile that works at least for 5 cycles TM5.
Want to explore a better RTT 7/3/3 or 7/3/4 first, then check tCCD_L experiments.

But it's already pretty good, very stable 52.9-53.0ns with occasional dips to 52.8ns.

















When I'm done, I'll give a check at 1T.
Not sure I can do it with only 1.55V but at least I was able to complete an AIDA benchmark, never been able with the other kits.
Super unstable, the screenshot got corrupted 
Quite impressive results in bandwidth of course.


----------



## T[]RK

Veii said:


> You can try to fix it with LLC, or just add positive v-core offset, to fix it


This cheap board don't have LLC, and i didn't saw exact that name (v-core offset) in GIGABYTE BIOS, but there is menu "Advanced Voltage Settings" and there two options "CPU Vcore" and gray "Dynamic Vcore (DVID)" (there also Dynamic VCORE SOC, but i think it's for APU).

GIGABYTE manual don't tell how to use it exactly (in fact it's not even tell what's inside this menu!). By default "CPU VCore" in "Auto", but i can set it in "Normal". When it's in "Normal" i can edit "Dynamic Vcore" with minimum 0.00625V steps up (+) and down (-). Look's like this is exactly it.

P.S .I never used "offsets" before. I understand that positive offset may give me some additional heat, but negative may give me... no boot, crash during load or even BSOD.  So i better to be sure what it is and what it's exactly do.


----------



## Tomasz91

Hello everyone.
Any ideas to improve? 
Is stable - 30 cycles 1usmus.


----------



## ManniX-ITA

Tomasz91 said:


> Any ideas to improve?


tRTP to 6 (tWR/2) works?
I'd check with SCL to 4 instead of 2 how it goes.


----------



## craxton

ManniX-ITA said:


> I'd check with SCL to 4 instead of 2 how it goes


is it the higher it goes for SCL the better?


----------



## ManniX-ITA

craxton said:


> is it the higher it goes for SCL the better?


I'm not sure always but in general 4/5 gives a boost in bandwidth compared to 2/3


----------



## Redwoodz

Veii said:


> I have some challenge for you guys
> For a client build, location & money doesn't play a role
> Can anybody help me import a pack of 4 from
> *HOF4RJL4BST4400T19MF162CL*
> 4x 8GB 4400 C19-19-19 @ 1.4v
> @fcchin thinking about you , for someone who can get GALAX dimms
> * for a set of 4, GALAX needs to be contacted directly ~ as they sell mostly only a Set of 2
> ** only 50 pieces were made and it's not on their webstore yet (news is 2 weeks old)



Look here Buddy








GALAX HOF OC LAB Water Cooling DDR4-4400 Limited Edition


GALAX HOF OC LAB Water Cooling DDR4-4400 Limited Edition




www.meitem.com


----------



## Yviena

Veii said:


> This counts in the tRTP change ?
> 
> I personally feel that tWR should be ending faster - same for tRTP **
> Although tRTP has playroom (as long as it's inside tRFC range), tWR rarely when you run an already bursty tRFC
> Could be also just thermal equilibrium (heat) issue or a random fridge at night going on. Oor also just switching from daylight power to cheaper night-savings
> 
> If it was with tRTP 8 , then try to drop tWR to 12 and see what happens
> I do think the rest is alright , else it would create issues far sooner than now
> After Cycle 9 to 19 it mostly is some offsync that takes a lot of times to appear or "leak" from on IC to another *
> * In the sense, on continuous done loops, it could tiny bit shift over ~ till at the end you are met with a place between dimms & then the error can not be masked anymore
> 
> But it can also be a typical time effect by heat. Really depends
> Wish you would've let it run for 2 more cycles to at least see what kind of effect will happen.
> Will it snowball with errors, or just was a tiny choke.
> Heat will snowball, and a house-current (ripple) change would also snowball strongly
> 
> ** i personally also feel, that you can either tighten SD,DD's a bit or lower tRDWR once more
> ~ probably both when the rest is tight.
> Increasing SD, DD's leads to more perf , but can overlap and cause issues.
> The stepping between RDRD & WRWR as +2 you can keep up. +3 or further exotic stuff i run, needs a full redoing on tRRD_ and tWTR_
> These ones you should touch/tighten at the very end, as they will limit any low primaries. Where low primaries are far more worth than just tighter transition timings


It was with tRTP 9 I'm gonna try setting TRTP/TWR lower later, I'm using a ram fan so my sticks really quickly reach thermal equilibrium after 20-30mins sensor doesn't move, atm I'm testing if a tick lower ODT would help.

clkdrvstr at 60 decreases stability so I believe maybe 30-40 is correct there, I'm using 4x8 sticks so unsure if I can change.SD/DD., I could also maybe try XX-24-24-24 for cadbus.


----------



## Sleepycat

craxton said:


> so it doesnt matter (inside bios) what you set as negative or positive if you leave it set to 0...
> im seeing CTR stated to not use curve but....what if one does, wouldnt this perhaps yeild better results?


What I found was that in actual use after tuning, CO doesn't matter. However, it does affect results during diagnostics. So if you had previously tuned it perfectly for PBO overclocking, then have the same settings on prior to diagnostics.



craxton said:


> (i did test but as my questions show im not equipped enough yet) and Vdroop happened quite a bit.
> OB wasnt on the free public version that i obtained, current version has a PX of 4950-XXXX-XXXX and
> voltage settings....i got 4900 to run all cores, with cpu VID and TEL values staying neck and neck with each other (per you stating they needed to be rather close with each other)


That's Vdroop, which is larger the heavier the load. You can compensate for the difference by increasing CPU VID (what you set) to ensure that CPU TEL is at the required level (what the CPU receives). Or you could use LLC which reduces Vdroop, but at the risk of voltage overshoot under certain situations.



craxton said:


> forgot how far apart the tolerance levels were exactly as i can look back three or so pages ive been watching for less than 10mv.
> as anything other than that above 4850 seems to not stay running (only using TM5 to hit max clocks that is)
> benchmate can hit all cores (one by one) at 4900
> (without anything adjusted in the bios) but its not what CTR said i "could" do.
> 4850 all core is what it states. (again, if the manual was up-to-date) id probably
> not bother wondering what was what
> but with what info you shared thats when i was able to get the 4900 all core stable (ish)


Personally, I don't worry about the difference, but instead watch for TEL to ensure it does not drop when under full load. If it works fine on full load without errors, then that TEL is sufficient and any lighter loads will be a higher voltage than full load.



craxton said:


> so, to further question you can adjust what CTR says you can run, but
> how to configure this to where DIAG mode will auto set this
> is what one wants? (im unsure if someone in CTR thread would
> be able to assist as good as you) not to many replies over there in general mostly qustions/complaints
> or what one got.


While the new guides say you don't need to use Tune, just Diagnostic, I still use Tune as it gives me even more aggressive values. If you want to use the values recommend during diagnostics, then just type them into the P1, P2 and Px profiles. The software "auto" determines what you can run, but it doesn't always auto-populate the settings. Typing them in, saving and activating works fine.



craxton said:


> i did hit (in CTR) 120 EDC limit as it was yelling EDC limit reached while running
> 180-120-240 but you mentioned the bug needs triggered on boot. so im assuming
> i need to adjust PPT, EDC, TDC in bios. (google does not know what it means)
> to "trigger" ryzen EDC bug lol anyhow appreciate the response.


That is just the setting that you had entered in CTR under advanced, which is like a soft-limiter. It will only stop Cinebench if you exceed the limiter, or just keep throwing silent messages which doesn't really affect other software. So yes, just set PPT, EDC and TDC in your bios, making sure CTR settings for these 3 are also the same or slightly higher than in bios.


----------



## CarnageBT

Veii -
"Try fixing it by checking which cores consistently crash
You can sort y-cruncher to individual cores too
(it loves to crash CTR "stable" results) 😏

My go to test for CPU stability, before finishing it off with OCCT Extreme AVX2 ~ couldn't make p95 ever useful to me "

I've returned to my baseline XMP profile settings for memory to eliminate it as a variable. I've re-run my cpu tests and made a few small tweaks to CO.
core cycler - y cruncher for a few hours
core cycler - p95 for a few hours
passed y cruncher 9 tests x 2 mins x 4 iterations
Currently running OCCT extreme avx2 (set to default, large)

If this passes, should I continue to test the CPU? ie. longer duration for core cycler, p95, y cruncher, OCCT (I am limited to 1 hour per test, I could run avx2 set to small or the Linpack test after)

or should I move onto memory? TM5 the default XMP profile to be sure it works, then move on?

or should I return the processor to all default settings, then work on the memory OC? CPU set to defaults, no OC.


----------



## craxton

Sleepycat said:


> , I still use Tune as it gives me even more aggressive values.


(you cant use tune) on the patreon version doesnt have the option to use it. its completely greyed out now.
(Sorry, unsure what all i can and cant show) but so far ive never had the option to tune at all. always stays greyed out)









(what version of CTR are you running? im on CTR 2.1 RC6 ver.13


Sleepycat said:


> However, it does affect results during diagnostics


ya it did for sure, but at the same time i was running a positive offset to core.
might end up giving my curve settings another shot. 
to that extent it is when CTR said i could do 5050 on PX profile. 


Sleepycat said:


> So if you had previously tuned it perfectly for PBO overclocking, then have the same settings on prior to diagnostics.


since the new version (im using atm) some settings in the bios wont need to be used. 
but i currently can run 4900 for along time on P2 profile but once i stop the the stress test, it crashes the system.



Sleepycat said:


> That's Vdroop, which is larger the heavier the load


only time i get this vdroop is setting offset in bios. otherwise TEL and VID are the same. 
other than that tho, i run LLC2 which i have yet to see overshoot and CPU voltage, however
LLC3 on NB overshoots SOC but setting 1.48 in bios to DRAM sets inside windows as 1.46 idle to 1.47 under load. 
(both CPU and NB at 1000khz) 
(this little b550 gaming edge board is cheaper now and almost worth it) despite how MSI is 
with certain voltage controls and not allowing user controls over these crucial controls.



Sleepycat said:


> So yes, just set PPT, EDC and TDC in your bios, making sure CTR settings for these 3 are also the same or slightly higher than in bios.


(thats what ive done as of last night) but i still dont know the values to trigger the EDC bug...thats what my main concern was. 
to trick the CPU sounds like a better option unless im understanding what the EDC bug does....


----------



## PJVol

Sleepycat said:


> but at the risk of voltage overshoot under certain situations.


Actually, undershoot is more of a problem in these cases, I think.


----------



## ManniX-ITA

I was able to stabilize FCLK 2033, thanks to the xmr-stak-rx miner and Geekbench 5.
You need to find the exact CCD/IOD voltage. And it's a lot of course.
Couldn't find, yet, good enough settings for FCLK 2067.

















Best result so far with GB5, over 150 MT points on top of the best FCLK 2000.


----------



## PJVol

ManniX-ITA said:


> And it's a lot of course.


Is it? Considering board itself set vsoc to 1.28-ish with 2000+ in "auto" ?


----------



## ManniX-ITA

PJVol said:


> Is it? Considering board itself set vsoc to 1.28-ish with 2000+ in "auto" ?


eheh not the VSOC
Same as FCLK 2000 set to 1.23V but with LLC2
CCD to 1090mV, which is just 10mV more than I need for FCLK 2000
But the IOD needs to be 1155mV which is 15mV more and that's really a lot
FCLK 2067 seems to need more around 1170mV but couldn't get it stable and performant under xmr load
And at least 1.25 VSOC, at 1.27V crashes under load


----------



## musician

munternet said:


> Thanks to @ManniX-ITA for all the help getting me started with AMD memory overclocking and solving my in-game issues
> 
> View attachment 2513300


Well, I have to thanks to @ManniX-ITA as well. Because after many crashes and faults with my builds, I just shamelessly coppied this your settings, but with only 3800/1900 speed. My maximal stable FCLK without WHEA errors was 1866/1933, with all of the other settings left on auto, so I decided I should do one step down with tweaked speed.
I have done 1 and half hour of 1usmus v3 TM5, 3 hours of OCCT CPU Large Extreme AVX2 and 3 hours of Y-cruncher. Not a single WHEA or an error.
I coppied all the settings except the frequency as I already said, SOC - I set it to 1,1V and VDIMM to 1,405. Restt of the voltage, Impendance, DrvStr and Setup sections is on auto.
Works great, thank you


----------



## craxton

musician said:


> Well, I have to thanks to @ManniX-ITA as well. Because after many crashes and faults with my builds, I just shamelessly coppied this your settings, but with only 3800/1900 speed. My maximal stable FCLK without WHEA errors was 1866/1933, with all of the other settings left on auto, so I decided I should do one step down with tweaked speed.
> I have done 1 and half hour of 1usmus v3 TM5, 3 hours of OCCT CPU Large Extreme AVX2 and 3 hours of Y-cruncher. Not a single WHEA or an error.
> I coppied all the settings except the frequency as I already said, SOC - I set it to 1,1V and VDIMM to 1,405. Restt of the voltage, Impendance, DrvStr and Setup sections is on auto.
> Works great, thank you


starting to think, i should go with DR sticks instead of these 4x8 sticks...









(have not tested since updating bios) so these AIDA results may be invalid. (stability i have tho)










Spoiler



(updated of course in safe mode)







(second run of 4 all 51.6 51.7 (in windows still 51.9 sadly cant kill enough tasks)







was able to lower IOD, CCD, VSOC down quite some margin (included in ZT screenshot) from where it used to roam tho.

congrats tho... re-run your setup on a hot day, and set 25 cycles for TM5.. a few pages back or so youll see why
its mentioned...
always best to re-check when its hotter outside.

(does anyone elses background go black while running safe mode? mine does to which, it comes up black as such.)


----------



## hazium233

craxton said:


> 137+133+129+140+125+140+804 =134


Interestingly, those numbers are exactly what I got with my 5600X the one time I ran diagnostic in the other day, although assigned to different cores. Nearly anything in bios on Auto (including VRM / LLC), PBO manually disabled. Ram was just at FlareX 3200C14 XMP.



craxton said:


> starting to think, i should go with DR sticks instead of these 4x8 sticks...


What are you trying to do that 2x DR will help you?


----------



## mirzet1976

ManniX-ITA said:


> I was able to stabilize FCLK 2033, thanks to the xmr-stak-rx miner and Geekbench 5.
> You need to find the exact CCD/IOD voltage. And it's a lot of course.
> Couldn't find, yet, good enough settings for FCLK 2067.
> 
> View attachment 2513345
> View attachment 2513346
> 
> 
> Best result so far with GB5, over 150 MT points on top of the best FCLK 2000.
> 
> View attachment 2513347


I have one old run with GB5


----------



## craxton

hazium233 said:


> What are you trying to do that 2x DR will help you?


lower SOC voltage hopefully, and simply have something else to play with as i own 0 DR dimms. 
in fact, i dont own any kits other than my 3200c14 dark pro sticks now (sold all others off for way to cheap)
you ever get to tinker with 4000mhz 1:1:1 mode yet?



hazium233 said:


> Auto (including VRM / LLC)


something i didnt pay attention to while running DIAG was having left my +vcore 
(turning it off) increased my core scores to, 143+139+135+147+131+147=842/6=140.3333
(have not turned LLC down or set to auto, have not changed switching frequency)
core 5 is my worst core, and core 4 being the best* (minding it needs 1.179 (in TM5) to sustain 4.85GHZ) with snapshot polling on.
all im running currently is CO as i gave up with CTR... for the moment... couldnt out due my CO 
no matter what i tried. CTR might be a great tool, but without the know how, its a 
long list of WHEA 18s 

(to anyone who can answer) when running tune, (giving it a few clicks after diag runs hit profile, then swap back you still have a greyed out tune button but you can click it a few times and itll run strangely) 
have not reported the bug, however
WHEA COUNTER 3 
does this mean there are 3 counters active, or is CTR saying i have 3 WHEA errors? 
as i had way more than that. cleared the log yet (only during tune) it still stated WHEA counters-3

(kernel WHEA had just as many (around 40 since using CTR)
(i changed values always, and i finally found the manual and understood somewhat better of what did what
but none-the-less, i still couldnt get CTR to outperform my CO overclock (this time around only needing slight offset to voltage for safe measure)


----------



## Yviena

@Veii managed to reach around 23-25 cycles before error 14/0 now by setting TRTP to 8 and TWR to 12, procodt to 36.9, and cadbus to 24-24-30-24, TWTR_ is still at 4-12, setting it to 5-15 via hex is a pain...as mobo doesn't accept 15.


----------



## hazium233

craxton said:


> lower SOC voltage hopefully, and simply have something else to play with as i own 0 DR dimms.


Ah ok, for fun it makes sense.



> you ever get to tinker with 4000mhz 1:1:1 mode yet?


With the unlock bios? No, not yet.



> something i didnt pay attention to while running DIAG was having left my +vcore
> (turning it off) increased my core scores to, 143+139+135+147+131+147=842/6=140.3333
> (have not turned LLC down or set to auto, have not changed switching frequency)
> core 5 is my worst core, and core 4 being the best* (minding it needs 1.179 (in TM5) to sustain 4.85GHZ) with snapshot polling on.


I do not know which is my true best cores, although I did look at the voltage in single core loads manually with P95 and then core cycler when I first got it. Not surprisingly, the lowest voltage tracked with the two best cores... but without getting through all of CO testing, I do not know if the true quality will end up different.

I only ran the CTR diagnostic with nearly bone stock settings since I did not want to skew the results, and it was just for fun. Although the one set of instructions I think actually recommended Mode 3? LLC for MSI, but it was on Auto when I ran it.

* actually the 2.0 guide said Mode 3, the 2.1 says Mode 4. I don't know


----------



## craxton

hazium233 said:


> Ah ok, for fun it makes sense.


yes, but from my ol ladies perspective its a hammer in hand...... 



hazium233 said:


> With the unlock bios? No, not yet.


honestly i have yet to really do anything with the unlocked bios....
i did note down a few things that was mentioned to others for their timings and etc.
but im unsure if that was just "per" user case with set dimm/board, or in general that one should
disable these things and enable these things. "these" being the stuff i noted down. which is shown inside the bios
but some of or at least 90% is already done default. 



hazium233 said:


> I do not know which is my true best cores


CTR (latest) tells what core, freq, voltage, etc best to worst.
and tells what cores are actually being used. which is how (other that when i consulted with PjVOL using zen timings debug)
i knew as well what cores were turned off/on. skips 1 and 3 ( wished there was a way one could turn these back on ) 
even if it did bring clock speeds down surely 8 cores at 4750 is better than 6 at 4925/4850 lol...



hazium233 said:


> but without getting through all of CO testing


using CO is a nightmare to get down in my opinion especially going in blind...
have been at it (properly) for over a week now, haven't gammed much, but have ran several heavy workloads 
to which knock, knock, knock no crashes. 



hazium233 said:


> the 2.1 says Mode 4. I don't know


from what i just read (a few hours ago) thats what was recommended, or auto/what you know will work.
there is a different beta version as well, with "game" mode on it that people in the discord are speaking about hitting
5ghz from time to time......pffft like its an easy task... 
my chip in the right hands, im sure would be a dandy....but in mine well


----------



## Veii

Redwoodz said:


> Look here Buddy
> 
> 
> 
> 
> 
> 
> 
> 
> GALAX HOF OC LAB Water Cooling DDR4-4400 Limited Edition
> 
> 
> GALAX HOF OC LAB Water Cooling DDR4-4400 Limited Edition
> 
> 
> 
> 
> www.meitem.com


Sadly HOF is located in Taiwan and has REP's in Japan & Hong Kong
I killed my Twitter, in order to redo it ~ but lost contact + my Japanese is not good enough

They don't sell a set of 4 dimms, while the cooler is designed for 4
getting another similar Bitspower cooler is possible (without RGB) but they only sell 2
When you contact GALAX support, they should sell a set of 4 ~ sadly it needs regional contact , because of Language Barriers 
Usually they also should sell 2x16GB OC Lab's but i can not find anything. The set is new and the run is very limimted

Sad this site, and i'm considering it, but i am not sure ~ we need 4x8 at least, as Warzone eats too much RAM


Sleepycat said:


> What I found was that in actual use after tuning, CO doesn't matter. However, it does affect results during diagnostics. So if you had previously tuned it perfectly for PBO overclocking, then have the same settings on prior to diagnostics.


CO does change PX boost and does change OB range
Because internally it pushes you to lower straps , soo you overdrive the overdriving and cheat FIT 
But it's more than dangerous ~ but trowing it out, as a little CO does help a bit . More than 5 needs positive vcore offset ~ which can break CTRs V/F presets and AMDs confidential ones
Buuut it does work 


Yviena said:


> @Veii managed to reach around 23-25 cycles before error 14/0 now by setting TRTP to 8 and TWR to 12, procodt to 36.9, and cadbus to 24-24-30-24, TWTR_ is still at 4-12, setting it to 5-15 via hex is a pain...as mobo doesn't accept 15.


14-0 are CAD_BUS issues now








4 are PCB crashes , 0 usually too but 0 mid testing is a voltage based choke
It's delay based, soo the first potential issue are badly timed SETUP timings, or badly timed tCKE
Unless powerdownmode is strictly enabled ~ the issue lies rather in powering (again)

I think it's CAD_BUS
Never seen that any 5xxx CPU or 5xx board likes 24ohm on CAD_BUS
it's 20 or 30+
Lower on the values is mostly better

What if you redo testing with tWR 12 and tRTP 6 ? will that even pass ?
Currently it's just a slight bit offsync , when you fail that late
* which is why i run 25 cycles 

You'll get there. Eh, we'll get there 


craxton said:


> does this mean there are 3 counters active, or is CTR saying i have 3 WHEA errors?


you had 3 errors, but it will continue or learn (drop voltage)


craxton said:


> but none-the-less, i still couldnt get CTR to outperform my CO overclock (this time around only needing slight offset to voltage for safe measure)


same here, even when CTR boosted higher to 4950-5000
a fixed allcore is slower cache wise and latency wise than PBO - for whatever AMD throttle reasons, it is slightly slower 0.1-0.2ns L3 & around 50GB/s less cache perf


hazium233 said:


> * actually the 2.0 guide said Mode 3, the 2.1 says Mode 4. I don't know


The guide between 2.0 version and 2.1 version got changed slightly 
Same for ASRocks guide too ~ was there
Consider that loadlines are not always identical between PWM controllers ~ even from the same brand


craxton said:


> i knew as well what cores were turned off/on. skips 1 and 3 ( wished there was a way one could turn these back on )
> even if it did bring clock speeds down surely 8 cores at 4750 is better than 6 at 4925/4850 lol...


If they failed verification - it failed because no CO value of -30/+30 was able to run this frequency
I have it on the 2nd CCD which are less than 4.65 stable, it only allows 4.5ghz at any voltage ~ soo it got disabled
Maybe someday somehow from somebody in another castle - said it could be potentially possible.
As a dreaming thought


----------



## mongoled

ManniX-ITA said:


> Of course you were right and the monero miner is the *perfect tool to both measure performances and stability at high FCLK*.


Any quick setup guide for this for those of us who have never dabbled in mining ?

Got as far as understanding I need to have some sort of account setup somewhere to access a "pool"

I created a wallet using "monero"

Thats as far as I got ...

I thought I had understood this correctly though im getting the following error



Code:


[2021-06-07 10:04:19] : SOCKET ERROR - [xmr.bohemianpool.com:7777] Login error: Invalid payment address provided
[2021-06-07 10:04:19] : SOCKET ERROR - [xmr.bohemianpool.com:7777] RECEIVE error: A blocking operation was interrupted by a call to WSACancelBlockingCall.


----------



## Veii

mongoled said:


> hats as far as I got ...
> 
> I thought I had understood this correctly though im getting the following error



















I tried to optimize it for better hash results - but at the end it's not worth it anyways
but a good stresstest for sure 

Be sure that the configs have " " in there, else it won't be read


----------



## mongoled

Veii said:


> View attachment 2513375
> 
> View attachment 2513376
> 
> I tried to optimize it for better hash results - but at the end it's not worth it anyways
> but a good stresstest for sure
> 
> Be sure that the configs have " " in there, else it won't be read


Thanks, I thought my issue was because I did not have a "wallet address" which I think I found from the "Monero Wallet" in "Account" copy "Primary Account" section.

But after entering that value into the "pool.txt" config I get a different error



Code:


[2021-06-07 10:31:55] : Fast-connecting to xmr-eul.nanopool.org:14433 pool ...
[2021-06-07 10:32:16] : SOCKET ERROR - [xmr-eul.nanopool.org:14433] 10044:error:0200274C:system library:connect:reason(1868):crypto\bio\b_sock2.c:110:
10044:error:2008A067:BIO routines:BIO_connect:connect error:crypto\bio\b_sock2.c:111:
10044:error:0200274C:system library:connect:reason(1868):crypto\bio\bss_conn.c:173:hostname=xmr-eul.nanopool.org service=14433
10044:error:20073067:BIO routines:conn_state:connect error:crypto\bio\bss_conn.c:177:

OK, something to do with the pool,

I changed the pool and its working.

PC has become slow as molasses

🤣 🤣


----------



## Taraquin

ManniX-ITA said:


> I was able to stabilize FCLK 2033, thanks to the xmr-stak-rx miner and Geekbench 5.
> You need to find the exact CCD/IOD voltage. And it's a lot of course.
> Couldn't find, yet, good enough settings for FCLK 2067.
> 
> View attachment 2513345
> View attachment 2513346
> 
> 
> Best result so far with GB5, over 150 MT points on top of the best FCLK 2000.
> 
> View attachment 2513347


Nice! But do you really need that much volt on soc, iod and ccd? I got 2033 stable with 1.16V soc, 1.08 iod, 860mv ccd and vddp. I know some who needs a bit more due to DR, but do you get wheas/perf reduction with lower voltage?


----------



## mongoled

ManniX-ITA said:


> Back in business with CLKREQ# with 14935 H/s


So with 12 threads and FCLK @2067mhz im getting 7818.2 H/s CPU frequency is locked at 4637/8 mhz

Its dropped to just under 7700 as the CPU reached thermal equilibrium frequency is now 4634/4635 mhz

Now its back up to 7800, unsure how this miner acts with the hashrate, all new to me



So just dropped to 1900 FCLK with tight timings, score is slightly higher as well as frequency (78xx H/s 4640/x), looks like higher FCLK is simply eating into the power budget, not making a difference in performance, at least for a 12 thread CPU.

These results simply mirror what I see when running Y-Cruncher at different FCLKs ...


----------



## fcchin

Veii said:


> Can anybody help me import a pack of 4 from
> *HOF4RJL4BST4400T19MF162CL*
> 4x 8GB 4400 C19-19-19 @ 1.4v
> @fcchin thinking about you , for someone who can get GALAX dimms
> * for a set of 4, GALAX needs to be contacted directly ~ as they sell mostly only a Set of 2
> ** only 50 pieces were made and it's not on their webstore yet (news is 2 weeks old)


Hi Veii (long time no see), I've sent email to ask a distributor of Galax = GALAX - Felton Distribution

I also sent enquiry to one of the shops listing normal 4400mhz HOF CL-18-22-22, I know is not what you want, but hopes they can help us ask Galax. Galax HOF OC Lab Extreme 皚鑽 RGB DDR4 4400MHz 16GB Kit 價錢、規格及用家意見 - 香港格價網 Price.com.hk


----------



## Veii

mongoled said:


> So just dropped to 1900 FCLK with tight timings, score is slightly higher as well as frequency (78xx H/s 4640/x), looks like higher FCLK is simply eating into the power budget, not making a difference in performance, at least for a 12 thread CPU.
> 
> These results simply mirror what I see when running Y-Cruncher at different FCLKs ...


That's correct 
This is why we need maxed out negative CO and or telemetry faking
this drops the FUSE limit FIT recognizes and powerdraw can increase same as the score


----------



## Veii

fcchin said:


> Hi Veii (long time no see), I've sent email to ask a distributor of Galax = GALAX - Felton Distribution
> 
> I also sent enquiry to one of the shops listing normal 4400mhz HOF CL-18-22-22, I know is not what you want, but hopes they can help us ask Galax. Galax HOF OC Lab Extreme 皚鑽 RGB DDR4 4400MHz 16GB Kit 價錢、規格及用家意見 - 香港格價網 Price.com.hk


Thanks a bunch, knew i could count on you.
Need a set of 4, they have 50 pieces out only
and all of them are labelled, soo they (GALAX) need to put an order out - or the retailer, to save buying twice the MemCooler

Else buying twice and sellling one (maybe even here on OCN), would be the option
Again, thanks 
If needed, i have contacts in Korea ~ but GALAX is HK & JP based 🙊
(Korea has a lot of Kingpin KPx paste, Europe has non) 

Yes, long time no see


----------



## mongoled

I think telemetry faking is broken in AGESA 1.1.9.0
When I attempt to input a value in a field that says it takes a value in "mA" instead of applying it in "mA" it applies it as Amperes!

CPU then gets restricted to 60 mhz per core or 58x mhz all core frequency

  😄

Unsure how we can "trust" the miner as I've noticed when the log shows message that the "difficulty changed" the hashrate is also effected....., second thoughts , its still being effected by whatever is being mined :/ :/

Scub that, once vSOC is dropped below a certain value (its around 1.1875v for my CPU @2067 FCLK) hashrates tank, just brought back up to 1.2v set (gets is 1.95v). so at least Monero mining can be used to tweak vSOC


----------



## Yviena

@Veii any recommendations for 2x DR sticks that are relatively close performance wise to b-die? I've been thinking about building another another pc as I have a spare 3700x.


----------



## kratosatlante

Tomasz91 said:


> View attachment 2513312
> 
> Hello everyone.
> Any ideas to improve?
> Is stable - 30 cycles 1usmus.


go scl 5 5, in my case trp 13 no work with tcwl 12, I need to trp 14 and tras 22, at last you can try test faw 12


----------



## Veii

Yviena said:


> @Veii any recommendations for 2x DR sticks that are relatively close performance wise to b-die? I've been thinking about building another another pc as I have a spare 3700x.


F4-4000C16D-32GVKA are decent, because of the 1.4v rating ~ you can have luck and get something better out of them 
But the cooler was designed for A0 kits and so A1 or A2 PCB (it's A2) only covers half of the ICs
Meaning you either put a fan on them, or fully remove the PCB cooler (likely would be cooled better then)

The Trident-Z Neo's same 16-16-16 binning appear to have a full allumium heatsink & 10 layer instead of 8, but the RGB creates a temp hit on it
i don't like these 1.5 or 1.55v maxed out binnings
4000+ to verify it's no  PCB, but still not a 1.5v binning
You might be often better with 4400C19-19-19 kits @ 1.35v than these high voltage ones
At least it wasn't then pre-tested, soo you can play once with the wheel of IC lottery


mongoled said:


> second thoughts , its still being effected by whatever is being mined :/ :/
> 
> Scub that, once vSOC is dropped below a certain value (its around 1.1875v for my CPU @2067 FCLK) hashrates tank, just brought back up to 1.2v set (gets is 1.95v). so at least Monero mining can be used to tweak vSOC


Oh it can take time till it settles, 5min at least
But also because Ping varies & because CPU hits TDC limits - by thermals
EDC will be maxed out anyways, but TDC limits exist
Consistency i think was fine ~ just need to configure it well & keep the FUSE limits in mind
After a point , it will tank strongly


kratosatlante said:


> go scl 5 5, in my case trp 13 no work with tcwl 12, I need to trp 14 and tras 22, at last you can try test faw 12


8+15 tRCD = 23 /2 = 11.5, 12 is the minimum, but that expects that the rest is perfect
11.5 is not perfect really , soo increasing tRCDWR can be needed , to 9
that's then 13
Odd sets like this mostly perform worse than flat timings
Focus more on getting tRCD 15 away, by increasing tRRD_ & tWTR + tRDWR
and maybe more tRFC too
That in general performs better than an odd set

What you want to probably do, is increase ClkDrvStr , 30+
and weaken RTT_PARK, soo the PCB doesn't crash on high voltage
Also i can see that you aren't hitting 30399 MB/s write, soo FCLK is not rock stable  it still throttles or autocorrects somewhere

L3 cache latency looks fine at 10.4 , that's how it should be
But L3 cache on it's own looks wrong. it misses 50-60GB/s
Soo maybe this is an allcore, because the values look comparable, but still are performing like a 4.65 set , instead a 4.85 (if this really is an allcore)
tRAS should be 19 if you want to go for min-tRAS else 27 or 31 (23+Burst 4 or +Burst 8)
tRC is fine at 38 on this current set

But rather focus on getting flat CL14-14-14 to run 


mongoled said:


> I think telemetry faking is broken in AGESA 1.1.9.0
> When I attempt to input a value in a field that says it takes a value in "mA" instead of applying it in "mA" it applies it as Amperes!


Nono, it's not, what you have is correct
but the change needs to be subtle
mA, soo 3000 a value or 8000 
FIT will detect telemetry faking - soo make smaller mA values


----------



## ManniX-ITA

Taraquin said:


> Nice! But do you really need that much volt on soc, iod and ccd? I got 2033 stable with 1.16V soc, 1.08 iod, 860mv ccd and vddp. I know some who needs a bit more due to DR, but do you get wheas/perf reduction with lower voltage?


At least on my 5950x is critical; otherwise under heavy load, eg the monero miner with 24/32 threads, the performances will drop instead of scaling up.
You can also see the same and different issue with Geekbench 5 and scaling up with Shadow of the Tomb Raider benchmark.



mongoled said:


> So just dropped to 1900 FCLK with tight timings, score is slightly higher as well as frequency (78xx H/s 4640/x), looks like higher FCLK is simply eating into the power budget, not making a difference in performance, at least for a 12 thread CPU.


The miner is more sensitive to bandwidth but also to latency, you should keep the same settings or balance it otherwise the results will be skewed toward FCLK 1900.

But in any case if you don't see a performance uplift something is wrong or you just hit the fuse limit first.
You can try to reduce the number of threads in case of fuse limit.
If something is wrong is either the voltages not right or you need CLKREQ# enabled.


----------



## ManniX-ITA

mongoled said:


> think telemetry faking is broken in AGESA 1.1.9.0
> When I attempt to input a value in a field that says it takes a value in "mA" instead of applying it in "mA" it applies it as Amperes!


What did you use?
On my 5950x works best:
CPU VDD Full Scale Current = bit less than half of EDC limit eg 100A for EDC 215A
CPU VDD Offset = 45 (for a 5600x probably 20-30 range would be better)
CPU SOC Full Scale Current = 1/5/10A (doesn't really change much for me, all works the same till 10A)


----------



## mongoled

Veii said:


> Nono, it's not, what you have is correct
> but the change needs to be subtle
> mA, soo 3000 a value or 8000
> FIT will detect telemetry faking - soo make smaller mA values


This makes absolutely no sense to me (I understood what you wrote but the explanation, will explain more below.....)



ManniX-ITA said:


> What did you use?
> On my 5950x works best:
> CPU VDD Full Scale Current = bit less than half of EDC limit eg 100A for EDC 215A
> CPU VDD Offset = 45 (for a 5600x probably 20-30 range would be better)
> CPU SOC Full Scale Current = 1/5/10A (doesn't really change much for me, all works the same till 10A)


Well, I didnt get to use as I stopped as soon as I saw something that made no sense to me.

What I had planned was to simply study what happens when I changed the values found in the menu below.

Both telemetry offset fields are in mA (1000mA = 1A).

So in my head if I set here 10000mA that is an offset of 10A, but nooooooooo, HWInfo shows me it at 10,000A hence the CPU completely "throttles".

So I do not understand @Veii explanation for this and stopped looking into this further as I assumed it is broken as 10000mA is not equal to 10A when set, but 10,000 amps !


----------



## ManniX-ITA

mongoled said:


> So in my head if I set here 10000mA that is an offset of 10A, but nooooooooo, HWInfo shows me it at 10,000A hence the CPU completely "throttles".


As you said it's an *offset.*

Like the vCore offset, do you expect to set 25mV and see the vCore set to 25mV? 

The Full Scale Current is an absolute value but the offset is applied to something and multiplied.
No idea what is the base factor 
But you can observe the result; EDC will be set to a minimum of offset x 1000.
Hence a 50mV offset will equal to 50A.

Look at the CPU frequency while running OCCT Large on a single core, best one you have.
Do it without and with offset; start low at 10 and go up, look for the value that will give you the highest stable frequency and most boosting.
I can get around 50-75 MHz more stable frequency and much more longer and frequent boosting to 5 GHz and above.
Then check the change with CB23 MT, you should see an increase in score. For the 5950x is up to 400 points.


----------



## Veii

Yea his feature is broken somehow 
it does work for me, but ASUS introduced them as new fields
New made and new renamed

might make sense to dig into the bios check what hex they apply and maybe see how much they differ ~ if they differ


----------



## mongoled

ManniX-ITA said:


> As you said it's an *offset.*
> 
> Like the vCore offset, do you expect to set 25mV and see the vCore set to 25mV?
> 
> The Full Scale Current is an absolute value but the offset is applied to something and multiplied.
> No idea what is the base factor
> But you can observe the result; EDC will be set to a minimum of offset x 1000.
> Hence a 50mV offset will equal to 50A.
> 
> Look at the CPU frequency while running OCCT Large on a single core, best one you have.
> Do it without and with offset; start low at 10 and go up, look for the value that will give you the highest stable frequency and most boosting.
> I can get around 50-75 MHz more stable frequency and much more longer and frequent boosting to 5 GHz and above.
> Then check the change with CB23 MT, you should see an increase in score. For the 5950x is up to 400 points.


I understand your want to give an explanation (and I appreciate that) when using the "offset" but in the notes for the field it says nothing about a "base factor", and it is here that it says its an "offset" nothing to do with me



Re your example, yeah absolutely

If I set a 25mV offset I expect to get an option if the offset is a positive or negative offset and dependent on this I would expect an offset of the amount I entered, so if my voltage is set to 1.025 then I expect a negative offset to reduce the voltage to 1.0v!

As is with current implementation, if I set "CPU VDD Full Scale Current" to 120A, I expect that a "CPU VDD Telemetry Offset" of 10000mA would either reduce this or increase this by 10A, as per the notes for the field that says



> CPU VDD Telemetry Offset Value [mA]. Range:1~10000mA


But no option for + or -

Nevermind that this is far from scientific its far from any sort of logic!

Now, I am not denying what you are suggesting to do does works, but this does not excuse that what is being described in the notes is far far far away from explaining exactly how the telemetry offset works .......

I am going to have to move to a new agesa just to see if this feature still works in the same way ....


----------



## ManniX-ITA

mongoled said:


> Now, I am not denying what you are suggesting to do does works, but this does not excuse that what is being described in the notes is far far far away from explaining exactly how the telemetry offset works .......


Most of these descriptions on the right panel are either poor or plainly wrong 

I was expecting like you something similar at the beginning but clearly MSI engineers they live in their own funny world where things have meanings which we, commoners, can't understand eheh

It's a positive offset only, guess maybe a negative value doesn't make sense. Hard to understand since I have no idea how it works...
But I think it works, test it how I suggested; the behavior you described is the same as mine with AGESA 1.2.0.1.
Have done the same and thought the same as you


----------



## mongoled

ManniX-ITA said:


> Most of these descriptions on the right panel are either poor or plainly wrong
> 
> I was expecting like you something similar at the beginning but clearly MSI engineers they live in their own funny world where things have meanings which we, commoners, can't understand eheh
> 
> It's a positive offset only, guess maybe a negative value doesn't make sense. Hard to understand since I have no idea how it works...
> But I think it works, test it how I suggested; the behavior you described is the same as mine with AGESA 1.2.0.1.
> Have done the same and thought the same as you


Thanks for saving me having to flash to a newer agesa!

Seems like changes, notes and experience is the only way to find out what these settings do, pffft.


----------



## heavyrain

Veii said:


> Isnt the goal to get it stable in the first place
> They are slower, but its not that extreme ~ as i run them at 7-9-28
> Maybe the instability got worse, but they play together with SD-DDs
> 
> Depends what you've tried
> Would RTT_NOM disabled post if you increase RTT_PARK to /2 with at least 40 or higher ClkDrvStr (CAD_BUS first value)
> 
> The RTT values that where shared for Matisse as easy to run options, are not optimal anymore
> Vermeer works a bit different that Matisse
> Since the recent 1201 and 1202 update, my settings fully bricked
> Was initially running 6/3/6 , but i had to go down to 5/3/7 or even 6/3/0 worked
> 
> Something changed with the IMC, and i'm still testing around
> Compared to 1200 , but IPC increased nicely
> 5-23% according to geekbench
> Just it spills random 2's out for some random reason
> 
> Is this TM5 profile based upon 1usmus_v3 ?
> Because for example Anta's profile , the error numbers differ fully and mean something completely different
> CsOdtDrvStr got a bump between 30-40ohm , in order to work against the broken memory training since AGESA 1.1.0.0*A*
> After Patch C , it got worse and worse / this was about the correct option, to get it towards a useable setting
> It's not fitting for Matisse.
> There the hard work of 1usmus from the DRAM calculator works blindly
> 
> ClkDrvStr bump still is a good method to help lowering procODT and getting GDM off
> Which btw is too high for you
> in combination with high ClkDrvStr, it might be too much for the PCB and you can "PCB Crash" - IF the errors mean the same which they do on Yuri's preset
> 
> Matisse's procODT range was:
> 28-32ohm for 2x8GB SR
> 34-36ohm for Dual Rank or 4x8Gb
> 34~ for Rev.E or Micron B-Die
> 30-32 for Hynix-MFR or AFR (CJR should be fine within 30)
> Overall it's too high.
> 
> The minimum & optimal value at 900-950-1050 (1900FCLK) on Matisse was 28ohm with B-dies, and anything else a tad higher.
> But not 3 steps higher like you do run atm.
> It also needed the UncoreOC flag inside AMD OVERCLOCKING enabled, else FIT was autocorrecting the voltage you set and ignore it fully
> (a long story with buggy Dynamic FCLK & Dynamic SOC)
> 
> Another thing is that you run tRAS+2.
> If you want to move inside JEDEC's range, you need to use +4 for SR ~ or don' follow it and run tRCD+tRCD (28)
> tRC "technically optimally" would remain that 32+tRP.
> That under *8 multiplier from my anchor's would be 368-273-168, with tWR 16 (8.421111....to the infinite)
> 
> But JEDEC up to which revision out of the 30+ , you refer to - doesn't always define what has to work.
> It's not recommend to follow it like a holy book. Especially when this holy book had over 30 revisions
> 
> I'm also a bit conflicted with your tWRRD & tWTR set
> 4-12 should run, but i can't recommend stuff blindly without double-testing SD,DD relationship here.
> Try to get it stable under SLC 4-4 , with your current setting and bump up tRRD & tWTR (5-14) , till you have something that passes at least 20 cycles TM5
> (or anything that takes longer than 1h to test ~ soo you hit thermal equilibrium & still have a full cycle to test)
> 
> RTT 7/0/6 is a bit special
> Combine it please with tCKE 9
> It does work also for Matisse, but CAD_BUS SETUP timings could missmatch
> I think what you surely want, is to drop VDDG IOD a bit near that 1v range or even 950mV with procODT max 32ohm
> 32ohm shouldn't allow you to run VDDG IOD to 950mV but 28ohm will !
> ClkDrvStr doesn't care about it, you can keep running 40 or 60ohm there ~ just have in your backhead, that it is a (A) multiplier , soo if you want to increase RTT_PARK strengthness for example /6 or /5, lower it down to 40ohm instead of 60 (for single rank) . Or lower VDIMM down
> 
> About Matisse,
> 24-20-20-24 is what works , similar for Zen 1
> 24-20-24-24 should be used on lower quality PCBs to prevent cold boot issues, but higher than 24 is not needed on any board for Matisse and lower
> 30-20-20-24 is fine, same as 40-20-20-24 is fine
> 60-20-20-24 is a bit conflicting but can work out , it's just a bit harsh . You may need 60-20-20-20, but you'll figure it out
> 
> SOC beyond 1.1v here has bad effects and increases procODT requirements.
> Up till 1.15v is usually the range after when negative scaling begins
> But i want to remind, that 1900 FCLK on Matisse was hard and it still suffered from bad signal integrity ranges
> Soo lower procODT = higher FCLK (1900 lock, but 1900 didn't run on every CPU)
> Focus on that 28ohm range, and stay at 900mV cLDO_VDDP
> 950mV is not fine with 28ohm proc, same as beyond 1.1v is not fine with it.
> 1900 FCLK bruteforce settings are 32ohm proc, 950-1050-1100-1150 (cLDO_VDDP, VDDG CCD , VDDG IOD, VSOC [GET])
> * stepping on Matisse was 50mV on stock or 75mV on extreme bruteforce settings
> More about it here:
> 
> 
> 
> 
> 
> 
> 
> 
> OC'ing T-Force 4133 cl18
> 
> 
> I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> Buttom part of the message
> AMDs minimum limits are 42-43mV (ty The Stilt) , but you want to have at least 48mV difference between the GET settings between VDDP, VDDG and VSOC
> 
> I have a bit of an issue with anytype of "fixed real world timed" values
> There was a ruleset out there spreading on the Intel MemOC thread, about tWR being a 8ns value as absolute minimum
> This can not work. Memory is logarithmic and works on integers
> No real world timed value is correct - as it scales up and down depending on set MCLK and the Command Rate state (PowerDown and GDM rounding included)
> 
> This is not optimal, and i strongly try to skip math that considers any type of fixed ns value. This can not work and won't work.
> Rounding decimal numbers is also not optimal, same as focusing on fixed ns tRFC value is strongly not considerable
> Been through this, and one of the reasons that tRFC mini module exists
> 
> Technically tRAS + XYZ (4,8) or tRC+1,2,4,8
> used as integer values of tRC as a whole (half cycle, 1/8th of a cycle and so on) - was an option for stability and matching up things.
> But it's also not optimal to do math that way
> No XYZ + fixed ns value , is optimal
> It works when you use added "memory timing" value, as it will turn at the end still to a .xxxxxxx (11 decimals) value
> But if we speak about ns math, that's not a good method
> Every little rounding stacks ~ beginning with board manufactures and IMC firmware developer rounding 3733.33333333337 MT/s, values
> The math breaks, the more you round and tRFC 2 and 4 do fully break if you do it with the /1.346 & /2.1875 math
> * reason why tRFC mini module exists, against Yuri's DRAM Calculator method, it always got tRFC2 & 4 wrong but it wasn't his fault but the user who inputs the wrong ns value
> Even the windows calculator doesn't function beyond 11 decimals, while google docs ends at 13 decimals
> 
> I need to sit with you and write a book about everything that's wrong with how we scale MCLK and boards predict values
> But trust me that a lot of thought went into "tRFC Mini" , and the way that it functions at version v2.31. It had undergone many revisions since v0.1 & yet is not perfect, because i can not generate tSTAG out of thin air, to match it better & have no statistic range for temperature to ns delay failure.
> 
> We'll talk someday about the reason i abandoned fully anything JEDEC related.
> Because this holy book did not follow reality
> A fantastic description was this post by an older dram engineer
> 
> 
> 
> 
> 
> 
> 
> 
> How to calculate tRC timing in cycles?
> 
> 
> Hi. I was looking for some additional ram for my aging desktop PC and tried to find modules that match the timings perfectly. At first I thought I found a perfect match with some Kingston modules, but on a closer look things are a bit weird. Wikipedia, among other sources states that tRC =...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 137,438,953,472 memory cells won't always follow perfect tRC (tRAS+tRP) math, it's not possible to follow it blindly
> But it's still a good indicator if the "transition" is "clean" or not, on a users set ~ or it needs work somewhere else, as tRC added delay does mask issues
> * need to answer Ron too, but it requires another big wall of text, soo someday later
> 
> Not such a good idea
> I mean it runs, but this combined with high voltage beyond 1.6 - i don't know what to think about it
> 
> Like mentioned a bit further up on the post,
> AMD did something to their IMC firmware since 1201 and 1202.
> I move between RTT_PARK /7 and /Disabled right now ~ instead of 6/3/6
> But still face issues. They 100% did something with RZQ , but i can not achieve stability yet
> Soo i can not say much more right now. I think some hidden CBS value changed, considering over 5% IPC bump & if i load my old profiles - it disables 4 of my USB 3.0 ports
> Also considering something adds 0.5ns to it (L3 cache stayed the same no change there, but Geekbench reports 5-23% improvement ~ single and multi)
> 
> Overall if you use high ClkDrvStr
> Lower RTT_PARK and RTT_NOM,
> CKE high & CKE low will move differently and be more bursty
> Any impedance value acts as a current multiplier , even if it's used as termination impedance (acts as resistance)
> 
> VDIMM, ClkDrvStr, procODT, and RTT_PARK go hand in hand
> They need balancing
> tCKE and SETUP timings are just control options, but i couldn't find something usable at 4200MT/s yet. It doesn't work well with DynamicODT (RTT_WR)
> But tCKE does still work well, soo that's a plus point
> 
> Dual Rank dimms can run 60-120, that's fine
> but it's not soo fine for 8gb single rank


The RTT value 


Veii said:


> Isnt the goal to get it stable in the first place
> They are slower, but its not that extreme ~ as i run them at 7-9-28
> Maybe the instability got worse, but they play together with SD-DDs
> 
> Depends what you've tried
> Would RTT_NOM disabled post if you increase RTT_PARK to /2 with at least 40 or higher ClkDrvStr (CAD_BUS first value)
> 
> The RTT values that where shared for Matisse as easy to run options, are not optimal anymore
> Vermeer works a bit different that Matisse
> Since the recent 1201 and 1202 update, my settings fully bricked
> Was initially running 6/3/6 , but i had to go down to 5/3/7 or even 6/3/0 worked
> 
> Something changed with the IMC, and i'm still testing around
> Compared to 1200 , but IPC increased nicely
> 5-23% according to geekbench
> Just it spills random 2's out for some random reason
> 
> Is this TM5 profile based upon 1usmus_v3 ?
> Because for example Anta's profile , the error numbers differ fully and mean something completely different
> CsOdtDrvStr got a bump between 30-40ohm , in order to work against the broken memory training since AGESA 1.1.0.0*A*
> After Patch C , it got worse and worse / this was about the correct option, to get it towards a useable setting
> It's not fitting for Matisse.
> There the hard work of 1usmus from the DRAM calculator works blindly
> 
> ClkDrvStr bump still is a good method to help lowering procODT and getting GDM off
> Which btw is too high for you
> in combination with high ClkDrvStr, it might be too much for the PCB and you can "PCB Crash" - IF the errors mean the same which they do on Yuri's preset
> 
> Matisse's procODT range was:
> 28-32ohm for 2x8GB SR
> 34-36ohm for Dual Rank or 4x8Gb
> 34~ for Rev.E or Micron B-Die
> 30-32 for Hynix-MFR or AFR (CJR should be fine within 30)
> Overall it's too high.
> 
> The minimum & optimal value at 900-950-1050 (1900FCLK) on Matisse was 28ohm with B-dies, and anything else a tad higher.
> But not 3 steps higher like you do run atm.
> It also needed the UncoreOC flag inside AMD OVERCLOCKING enabled, else FIT was autocorrecting the voltage you set and ignore it fully
> (a long story with buggy Dynamic FCLK & Dynamic SOC)
> 
> Another thing is that you run tRAS+2.
> If you want to move inside JEDEC's range, you need to use +4 for SR ~ or don' follow it and run tRCD+tRCD (28)
> tRC "technically optimally" would remain that 32+tRP.
> That under *8 multiplier from my anchor's would be 368-273-168, with tWR 16 (8.421111....to the infinite)
> 
> But JEDEC up to which revision out of the 30+ , you refer to - doesn't always define what has to work.
> It's not recommend to follow it like a holy book. Especially when this holy book had over 30 revisions
> 
> I'm also a bit conflicted with your tWRRD & tWTR set
> 4-12 should run, but i can't recommend stuff blindly without double-testing SD,DD relationship here.
> Try to get it stable under SLC 4-4 , with your current setting and bump up tRRD & tWTR (5-14) , till you have something that passes at least 20 cycles TM5
> (or anything that takes longer than 1h to test ~ soo you hit thermal equilibrium & still have a full cycle to test)
> 
> RTT 7/0/6 is a bit special
> Combine it please with tCKE 9
> It does work also for Matisse, but CAD_BUS SETUP timings could missmatch
> I think what you surely want, is to drop VDDG IOD a bit near that 1v range or even 950mV with procODT max 32ohm
> 32ohm shouldn't allow you to run VDDG IOD to 950mV but 28ohm will !
> ClkDrvStr doesn't care about it, you can keep running 40 or 60ohm there ~ just have in your backhead, that it is a (A) multiplier , soo if you want to increase RTT_PARK strengthness for example /6 or /5, lower it down to 40ohm instead of 60 (for single rank) . Or lower VDIMM down
> 
> About Matisse,
> 24-20-20-24 is what works , similar for Zen 1
> 24-20-24-24 should be used on lower quality PCBs to prevent cold boot issues, but higher than 24 is not needed on any board for Matisse and lower
> 30-20-20-24 is fine, same as 40-20-20-24 is fine
> 60-20-20-24 is a bit conflicting but can work out , it's just a bit harsh . You may need 60-20-20-20, but you'll figure it out
> 
> SOC beyond 1.1v here has bad effects and increases procODT requirements.
> Up till 1.15v is usually the range after when negative scaling begins
> But i want to remind, that 1900 FCLK on Matisse was hard and it still suffered from bad signal integrity ranges
> Soo lower procODT = higher FCLK (1900 lock, but 1900 didn't run on every CPU)
> Focus on that 28ohm range, and stay at 900mV cLDO_VDDP
> 950mV is not fine with 28ohm proc, same as beyond 1.1v is not fine with it.
> 1900 FCLK bruteforce settings are 32ohm proc, 950-1050-1100-1150 (cLDO_VDDP, VDDG CCD , VDDG IOD, VSOC [GET])
> * stepping on Matisse was 50mV on stock or 75mV on extreme bruteforce settings
> More about it here:
> 
> 
> 
> 
> 
> 
> 
> 
> OC'ing T-Force 4133 cl18
> 
> 
> I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> Buttom part of the message
> AMDs minimum limits are 42-43mV (ty The Stilt) , but you want to have at least 48mV difference between the GET settings between VDDP, VDDG and VSOC
> 
> I have a bit of an issue with anytype of "fixed real world timed" values
> There was a ruleset out there spreading on the Intel MemOC thread, about tWR being a 8ns value as absolute minimum
> This can not work. Memory is logarithmic and works on integers
> No real world timed value is correct - as it scales up and down depending on set MCLK and the Command Rate state (PowerDown and GDM rounding included)
> 
> This is not optimal, and i strongly try to skip math that considers any type of fixed ns value. This can not work and won't work.
> Rounding decimal numbers is also not optimal, same as focusing on fixed ns tRFC value is strongly not considerable
> Been through this, and one of the reasons that tRFC mini module exists
> 
> Technically tRAS + XYZ (4,8) or tRC+1,2,4,8
> used as integer values of tRC as a whole (half cycle, 1/8th of a cycle and so on) - was an option for stability and matching up things.
> But it's also not optimal to do math that way
> No XYZ + fixed ns value , is optimal
> It works when you use added "memory timing" value, as it will turn at the end still to a .xxxxxxx (11 decimals) value
> But if we speak about ns math, that's not a good method
> Every little rounding stacks ~ beginning with board manufactures and IMC firmware developer rounding 3733.33333333337 MT/s, values
> The math breaks, the more you round and tRFC 2 and 4 do fully break if you do it with the /1.346 & /2.1875 math
> * reason why tRFC mini module exists, against Yuri's DRAM Calculator method, it always got tRFC2 & 4 wrong but it wasn't his fault but the user who inputs the wrong ns value
> Even the windows calculator doesn't function beyond 11 decimals, while google docs ends at 13 decimals
> 
> I need to sit with you and write a book about everything that's wrong with how we scale MCLK and boards predict values
> But trust me that a lot of thought went into "tRFC Mini" , and the way that it functions at version v2.31. It had undergone many revisions since v0.1 & yet is not perfect, because i can not generate tSTAG out of thin air, to match it better & have no statistic range for temperature to ns delay failure.
> 
> We'll talk someday about the reason i abandoned fully anything JEDEC related.
> Because this holy book did not follow reality
> A fantastic description was this post by an older dram engineer
> 
> 
> 
> 
> 
> 
> 
> 
> How to calculate tRC timing in cycles?
> 
> 
> Hi. I was looking for some additional ram for my aging desktop PC and tried to find modules that match the timings perfectly. At first I thought I found a perfect match with some Kingston modules, but on a closer look things are a bit weird. Wikipedia, among other sources states that tRC =...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 137,438,953,472 memory cells won't always follow perfect tRC (tRAS+tRP) math, it's not possible to follow it blindly
> But it's still a good indicator if the "transition" is "clean" or not, on a users set ~ or it needs work somewhere else, as tRC added delay does mask issues
> * need to answer Ron too, but it requires another big wall of text, soo someday later
> 
> Not such a good idea
> I mean it runs, but this combined with high voltage beyond 1.6 - i don't know what to think about it
> 
> Like mentioned a bit further up on the post,
> AMD did something to their IMC firmware since 1201 and 1202.
> I move between RTT_PARK /7 and /Disabled right now ~ instead of 6/3/6
> But still face issues. They 100% did something with RZQ , but i can not achieve stability yet
> Soo i can not say much more right now. I think some hidden CBS value changed, considering over 5% IPC bump & if i load my old profiles - it disables 4 of my USB 3.0 ports
> Also considering something adds 0.5ns to it (L3 cache stayed the same no change there, but Geekbench reports 5-23% improvement ~ single and multi)
> 
> Overall if you use high ClkDrvStr
> Lower RTT_PARK and RTT_NOM,
> CKE high & CKE low will move differently and be more bursty
> Any impedance value acts as a current multiplier , even if it's used as termination impedance (acts as resistance)
> 
> VDIMM, ClkDrvStr, procODT, and RTT_PARK go hand in hand
> They need balancing
> tCKE and SETUP timings are just control options, but i couldn't find something usable at 4200MT/s yet. It doesn't work well with DynamicODT (RTT_WR)
> But tCKE does still work well, soo that's a plus point
> 
> Dual Rank dimms can run 60-120, that's fine
> but it's not soo fine for 8gb single rank


The Renior's proODT or RTT is same as Matisse's?


----------



## PJVol

ManniX-ITA said:


> since I have no idea how it works...


Isn't it just a simple linear function? Sadly i've got no "offest" in current bios, but it's safe to assume something like b in ax + b ?


----------



## ManniX-ITA

PJVol said:


> Isn't it just a simple linear function? Sadly i've got no "offest" in current bios, but it's safe to assume something like b in ax + b ?


Seems linear but I don't know how from mV ends up in A... something is multiplied resulting in the EDC fake telemetry but I don't know what.
There must be a reason why you don't type in directly the Amperes.


----------



## Yviena

Any thoughts about 1.2.0.3 AGESA worth upgrading to or?

Also @Veii think my sticks love lower voltage it's on cycle 24 atm without errors with 1.43v, I wonder if it's because of the RZQ values 7/3/1.


----------



## 1s1mple

Just finished a TM5 1usums.cfg 100 cycle as it seems to be recommended in this thread. Now I know its rock solid😁

G.Skill F4-3600C16D-32GVKC Dual Rank Memory Hynix CJR chips
Stock XMP 3600MHz 16-19-19-39 @ 1.35V
OC'd 3733MHz 16-19-21-36 @ 1.38V

VSOC 1.1v
CLDO VDDP Auto
VDDG CCD Auto
VDDG IOD Auto
ProcODT 43.6
RTTNom Disable
RTTWr RZQ/3
RTTPark RZQ/1

Tried some other recommendations but no luck so far, I guess ill stick with this.


----------



## Yviena

Hurrah managed to pass 30 cycles by lowering VDIMM from 1.44v to 1.43v.


----------



## jomama22

Ignore.


----------



## KedarWolf

ManniX-ITA said:


> As you said it's an *offset.*
> 
> Like the vCore offset, do you expect to set 25mV and see the vCore set to 25mV?
> 
> The Full Scale Current is an absolute value but the offset is applied to something and multiplied.
> No idea what is the base factor
> But you can observe the result; EDC will be set to a minimum of offset x 1000.
> Hence a 50mV offset will equal to 50A.
> 
> Look at the CPU frequency while running OCCT Large on a single core, best one you have.
> Do it without and with offset; start low at 10 and go up, look for the value that will give you the highest stable frequency and most boosting.
> I can get around 50-75 MHz more stable frequency and much more longer and frequent boosting to 5 GHz and above.
> Then check the change with CB23 MT, you should see an increase in score. For the 5950x is up to 400 points.


*Top Contributors this Month*
View All
ManniX-ITA
414 Replies

'gasp'


----------



## ManniX-ITA

KedarWolf said:


> *Top Contributors this Month*
> View All
> ManniX-ITA
> 414 Replies


Still have to get the vaccine, don't go out much


----------



## kratosatlante

Veii said:


> F4-4000C16D-32GVKA are decent, because of the 1.4v rating ~ you can have luck and get something better out of them
> But the cooler was designed for A0 kits and so A1 or A2 PCB (it's A2) only covers half of the ICs
> Meaning you either put a fan on them, or fully remove the PCB cooler (likely would be cooled better then)
> 
> The Trident-Z Neo's same 16-16-16 binning appear to have a full allumium heatsink & 10 layer instead of 8, but the RGB creates a temp hit on it
> i don't like these 1.5 or 1.55v maxed out binnings
> 4000+ to verify it's no  PCB, but still not a 1.5v binning
> You might be often better with 4400C19-19-19 kits @ 1.35v than these high voltage ones
> At least it wasn't then pre-tested, soo you can play once with the wheel of IC lottery
> 
> Oh it can take time till it settles, 5min at least
> But also because Ping varies & because CPU hits TDC limits - by thermals
> EDC will be maxed out anyways, but TDC limits exist
> Consistency i think was fine ~ just need to configure it well & keep the FUSE limits in mind
> After a point , it will tank strongly
> 
> 8+15 tRCD = 23 /2 = 11.5, 12 is the minimum, but that expects that the rest is perfect
> 11.5 is not perfect really , soo increasing tRCDWR can be needed , to 9
> that's then 13
> Odd sets like this mostly perform worse than flat timings
> Focus more on getting tRCD 15 away, by increasing tRRD_ & tWTR + tRDWR
> and maybe more tRFC too
> That in general performs better than an odd set
> 
> What you want to probably do, is increase ClkDrvStr , 30+
> and weaken RTT_PARK, soo the PCB doesn't crash on high voltage
> Also i can see that you aren't hitting 30399 MB/s write, soo FCLK is not rock stable  it still throttles or autocorrects somewhere
> 
> L3 cache latency looks fine at 10.4 , that's how it should be
> But L3 cache on it's own looks wrong. it misses 50-60GB/s
> Soo maybe this is an allcore, because the values look comparable, but still are performing like a 4.65 set , instead a 4.85 (if this really is an allcore)
> tRAS should be 19 if you want to go for min-tRAS else 27 or 31 (23+Burst 4 or +Burst 8)
> tRC is fine at 38 on this current set
> 
> But rather focus on getting flat CL14-14-14 to run
> 
> Nono, it's not, what you have is correct
> but the change needs to be subtle
> mA, soo 3000 a value or 8000
> FIT will detect telemetry faking - soo make smaller mA values


Thanks for the advice, I will try trcd 15, I had tried many times with the ryzen 5 3600, but with the 5600x not much partly because of the ch7wifi bios that do not allow me to play vddp and vddg, it puts the value that you want To the bios version, in later bios I had a higher reading in the L3 cache, but I went back to 4007 just to see 4850+ and test the new gpu with that extra mhz and less latency, every so often, nothing special and see if the configuration It was from bios 4204 it worked
any advice for this? 


only reduce faw 38 to 24 and trfc from 630 to 592 , trfc2 and 4 set auto, set 3800mhz and same timing seems ok, I do not have great experience overcloking micron e die




















have time to bench in the Weekend , the cpu seems gold sample


----------



## KedarWolf

ManniX-ITA said:


> Still have to get the vaccine, don't go out much


I'm a front line mental health worker, got my second shot two weeks ago from last Friday.


----------



## MyUsername

ManniX-ITA said:


> As you said it's an *offset.*
> 
> Like the vCore offset, do you expect to set 25mV and see the vCore set to 25mV?
> 
> The Full Scale Current is an absolute value but the offset is applied to something and multiplied.
> No idea what is the base factor
> But you can observe the result; EDC will be set to a minimum of offset x 1000.
> Hence a 50mV offset will equal to 50A.
> 
> Look at the CPU frequency while running OCCT Large on a single core, best one you have.
> Do it without and with offset; start low at 10 and go up, look for the value that will give you the highest stable frequency and most boosting.
> I can get around 50-75 MHz more stable frequency and much more longer and frequent boosting to 5 GHz and above.
> Then check the change with CB23 MT, you should see an increase in score. For the 5950x is up to 400 points.


The Full Scale Current seems to be an offset, default for my chip is 302-303 Amps, adjusting this up or down skews everything without affecting performance. The Telemetry offset adds Amps to CPU Core Current(SV12 TFN), TDC and EDC, but the CPU is only drawing approx 20 Watts more on idle, it's appears to be a phantom value as is not actually drawing any more than default, I can only use my PSU to gauge. This is boosting the CPU for longer giving a slightly higher/constant score in benchmarks and with about the same current draw from the PSU, it may spike 30 Watts higher at times.
Default Telemetry 








50mA(50 Amps) Telemetry Offset








Telemetry settings


----------



## CarnageBT

Hi Guys,

I haven't given up. I was testing today with the followings settings (see zentimings).










I then recorded the error messages as they came in over the first 2 cycles for each test run. Each change was cumulative (retained previous changes)

Changes madeErrors over 2 complete cyclesPictured settings0, 1, 4, 13, 0, 9, 14, 14, 1, 1,VDIMM 1.5 (from 1.52)12, 2, 10, 0, 14, 14,RttNom 6 (from 7)1, 1, 11, 12, 13, 13, 15VDIMM 1.48 (from 1.5)14, 10 - accidentally closed 1/2 way through 2nd cycletRAS 30, tRC 44, tFAW 42 (tCCD_l 7 x tRRDS)14, 11, 15, 0, 2, 10, 5, 5, 4, 14, 0, 15, 15, 6, 0, 6, 6, 6, 12, 0, 2, 2, 2, 10, 10, 10returned tRAS, tRC, tFAW to prrior valuesNeed to re-test but will be the same settings as the VDIMM 1.48 settings

Currently testing the full y cruncher suite x4.

At 3600 IF I passed everything without any errors.
Now at 3800 I am getting the odd logical core error (and making the necessary adjustments to CO)

Is this behaviour expect? ie. no errors at a specific IF speed, but changing it could reveal new problems?


----------



## craxton

Veii said:


> you had 3 errors,


(I had like well, more than 30 tho lol) (whea 18s while using CTR) and manually messing with what it says 
vs what i thought.....then again, i was able to get 4900 to run, (would run quite a while until stopping the test)
thats when id get a crash..... unstable but was running had 4950 at one point too but again, same thing...
still need more thought on what works and doesnt. 


Veii said:


> it failed because no CO value of -30/+30 was able to run this frequency


youd think, they could have simply made a 5700nonx or 5650 or 5800 8 core chip (all inbetweens since each would possibly boost 
those two dud cores differently) 
ill keep dreaming, unlikely even if someone does manage to turn them on tho, ill be one of those who can 
tune enough to actually get all 8 cores to run...



mongoled said:


> Monero mining can be used to tweak vSOC


have you given "nicehash" a thought? 
its on facebook, i used it for a little bit, just couldnt bare the thought of running my system that hard
all the time....but none the less, nice hash also has a way to tell you what youll make perday, how much power etc.
(unsure if its 100% going to be down to core clocks on CPU or not) but does pretty well about GPU mining for calculation 
(you can use this which is what youd use anyhow to guestamate how much income etc)
although i believe this is mostly to stress the system. itll still hit the CPU pretty dam hard.


----------



## craxton

question, if VID is lower than TEL then this means, im overvolting? or....
does this mean thats what i should be giving the chip? i know VID is whats gave to the chip and TEL
is what it actually gets, but if VID is lower than TEL how is the chip getting more lol?
no answer needed for that last part, just wanting to know how to counter....
please dont response with "test, test, test, tune, crash, test, tune, crash repeat"

considering LLC 2 or LLC3/4 all do around the same.... on CPU im curious to how to counter this..

(never mind, already got it figured out) removed the 250mv offset set llc to 4 
noticed VID was higher this time, jumped LLC to 3 and its right where it should be (give or take .03)
from time to time. possibly as close as ill get it. 

(also looked at a picture i took) of some stuff Veii had mentioned about MEM clear, PMU, TSME, all the other stuff as well
and turning all this off increased my boot time, (mostly how fast all my startup tasks loaded) 
....shuda listed before to when he told this to "someone" and thought it was for "everyone" instead.
to answer my question about "what the CPU thinks it needs" is FIT? 
almost certian, VID is what its given, TEL is what is actually getting, FIT, is what it "claims" is needed 
at "certain point/load/task" which is what most are trying to understand.


----------



## KedarWolf

ManniX-ITA said:


> What did you use?
> On my 5950x works best:
> CPU VDD Full Scale Current = bit less than half of EDC limit eg 100A for EDC 215A
> CPU VDD Offset = 45 (for a 5600x probably 20-30 range would be better)
> CPU SOC Full Scale Current = 1/5/10A (doesn't really change much for me, all works the same till 10A)











G.Skill launches low-latency CL14 Trident Z Royal Elite memory - KitGuru


G.Skill is back with another kit of Trident Z Royal Elite memory. We've seen G.Skill push extreme sp




www.kitguru.net





The latest Trident Z Royal Elite series memory comes in two variants, one running at 4000MHz and CL14-15-15-35 timings and another running at 3600MHz and CL14-14-14-34 timings.


----------



## Iarwa1N

I am really out of ideas with my dual rank 3200 CL14 B-dies. Whatever I did, I couldnt able to boot more than 3400 mhz. Finally I tried one stick at a time and one of them can easily post at 4000, but the other stick wont even post at 3600 with this timings;










I tried procODT 43-48-53, I tried so many RTT and CAD_BUS combinations. I tried 3-4 different bios with different AGESA versions. Is there anything else that I can try? 
I have 5900X and Asus Strix B550-F. These are the sticks I have;










This is one of the sticks posting at 4000;


----------



## CarnageBT

Taking a break from 3800.... seems really difficult for me to nail down.

Setup 3733 with the settings shown below. Ran 6 cycles in TM5 and got 3 errors all in the final 6th cycle. Error 12, 10, 0

Any recommendations as to what I should change? I'm considering adding +0.01 to vDIMM, or changing tRDWR/tWRRD.


----------



## mongoled

CarnageBT said:


> Taking a break from 3800.... seems really difficult for me to nail down.
> 
> Setup 3733 with the settings shown below. Ran 6 cycles in TM5 and got 3 errors all in the final 6th cycle. Error 12, 10, 0
> 
> Any recommendations as to what I should change? I'm considering adding +0.01 to vDIMM, or changing tRDWR/tWRRD.
> 
> View attachment 2513467


real quick and easy, drop tRCDRD to 16, change nothing else, let's see if those errors disappear 
😊


----------



## fcchin

Veii said:


> Thanks a bunch, knew i could count on you.


Hi Veii, the shop seller says not enough buyers in Hong Kong, not meet MoQ minimum order quantity, hence Felton distributor is not able to get stock, because Galax demands from distributor MoQ. 

I've told the shop seller to add me into buyer list if they plan to fulfill the MoQ, and will verify price by future's fluctuation. 

Even this time no price quoted to me, because can't get stock. 

Sorry !!!


----------



## Veii

fcchin said:


> Hi Veii, the shop seller says not enough buyers in Hong Kong, not meet MoQ minimum order quantity, hence Felton distributor is not able to get stock, because Galax demands from distributor MoQ.
> 
> I've told the shop seller to add me into buyer list if they plan to fulfill the MoQ, and will verify price by future's fluctuation.
> 
> Even this time no price quoted to me, because can't get stock.
> 
> Sorry !!!


Don't worry 
Yea the guy just fainted away, scared away
at first he was going for "i want to hold over 300fps in warzone with my 360hz monitor"
We got it up to avg 300+, as at first he had only 30% GPU utilisation (3080) , because his 3600C16-19 ram was bottlenecking the 5900X
Now it's around 98% , but still wanted to replace the ram 
Eh had no enough b*** to do it at the end , was planing something special for him

About the rams, 
it's strange, they have soo many out there & "not being able to fullfill quota" is strange
Maybe because 350 bucks for 16gb was scary. Probably because the waterblock is expensive

Getting two will be interesting for sure
I think we can have usage out of it
But getting 4 is the real target - because 16gb is not enough for Warzone Streamer 
We'll see
You did your best, thank you ! 

I will find a buyer for them, just availability is important first ~ because "limited edition run"


----------



## musician

CarnageBT said:


> Taking a break from 3800.... seems really difficult for me to nail down.
> 
> Setup 3733 with the settings shown below. Ran 6 cycles in TM5 and got 3 errors all in the final 6th cycle. Error 12, 10, 0
> 
> Any recommendations as to what I should change? I'm considering adding +0.01 to vDIMM, or changing tRDWR/tWRRD.
> 
> View attachment 2513467


Since you are running 2t anyway, go for 3800 cl15. Copy my settings, VDIMM depends on your ram, mine is at 1,45V.


----------



## Nighthog

If anyone is interested I got RZQ values of 5/3/3 to boot and be more stable than 6/3/3 that was recommended here.

It has a quirky behaviour though. You can only train it and boot it when the computer is COLD, or has been shutdown for a while. It will not train or boot when the computer is hot or been running for a while.
But as soon as you have it successfully trained it will keep booting without issue. Only if you want to make BIOS changes with 5/3/3 you need to let the system cool down again before it will allow it to train again. But it might then fail quite a few times to train before it succeeds but if it manages to boot you have better stability. 
It's a hassle if you want to change settings but works if you have the patience or capability to make your system cool running with chilled water or better.


----------



## CarnageBT

mongoled said:


> real quick and easy, drop tRCDRD to 16, change nothing else, let's see if those errors disappear
> 😊


I'll try this now, so only tRCDRD to 16, no changes to anything else.


----------



## CarnageBT

musician said:


> Since you are running 2t anyway, go for 3800 cl15. Copy my settings, VDIMM depends on your ram, mine is at 1,45V.


Thanks. I'll keep this in mind if I can't complete the cl14 set with 1T.


----------



## mongoled

CarnageBT said:


> I'll try this now, so only tRCDRD to 16, no changes to anything else.


Yup 👍


----------



## CarnageBT

mongoled said:


> Yup 👍


So far, 6 cycles, no errors. I'll continue to let it run. If I pass 25 without errors, what does this tell you? ie. what should I try next


----------



## mongoled

CarnageBT said:


> So far, 6 cycles, no errors. I'll continue to let it run. If I pass 25 without errors, what does this tell you? ie. what should I try next


Well the next step will be the step that hopefully uncovers whats going on.

I did mention this previously, you are going to have to check each stick one by one on the assumption you get a clean TM5 run.

But you will test with the same settings but return tRCDRD back to 14.

Hopefully some of the sticks will run tRCDRD @14, this will give us a clearer picture of what each stick is capable of so you are not wasting more time with inconsistent results.


----------



## Cavokk

musician said:


> Since you are running 2t anyway, go for 3800 cl15. Copy my settings, VDIMM depends on your ram, mine is at 1,45V.


Hi musician, - are you on 2 16Gb stick or 4 8GB sticks?

Thanks


----------



## musician

Cavokk said:


> Hi musician, - are you on 2 16Gb stick or 4 8GB sticks?
> 
> Thanks


Hi, 2 16GB


----------



## mongoled

musician said:


> Since you are running 2t anyway, go for 3800 cl15. Copy my settings, VDIMM depends on your ram, mine is at 1,45V.


What vDIMM are you running ? 

RTT Park set to 1 is dangerous for A0 PCBs when voltage exceeds 1.5v.

So check to see what PCB's your DIMMS are if you are going over 1.5v or increase RTT Park to 2 (120 ohms) or higher


----------



## CarnageBT

mongoled said:


> Well the next step will be the step that hopefully uncovers whats going on.
> 
> I did mention this previously, you are going to have to check each stick one by one on the assumption you get a clean TM5 run.
> 
> But you will test with the same settings but return tRCDRD back to 14.
> 
> Hopefully some of the sticks will run tRCDRD @14, this will give us a clearer picture of what each stick is capable of so you are not wasting more time with inconsistent results.


I stopped it after 10 cycles, no errors. I really don't want to have to test each stick individually. So I went back to look over the error codes to see if there is something else I can tweak

12/2 - voltage, sync issue, resistance 
10 - tWR too slow, 5 main timings, tRDWR/tWRRD not playing well with main timings
0 - voltage cutoff, tRRD/tWTR, or VDIMM

I'm currently testing if it's the tRDWR/tWRRD not playing well with main timings. Previously was 9/4, trying 8/3 (dram calculator), and next I'll try 7/1 (ryzen google calculator)

If neither help, I'll try increasing vdimm to 1.47 and again to 1.48.

Hopefully one of these changes will work.

@Veii Any thoughts on those errors? Completed 5 cycles with no errors, then in the 6th cycle, error 12, 10, 0


----------



## mongoled

CarnageBT said:


> I stopped it after 10 cycles, no errors. I really don't want to have to test each stick individually. So I went back to look over the error codes to see if there is something else I can tweak
> 
> 12/2 - voltage, sync issue, resistance
> 10 - tWR too slow, 5 main timings, tRDWR/tWRRD not playing well with main timings
> 0 - voltage cutoff, tRRD/tWTR, or VDIMM
> 
> I'm currently testing if it's the tRDWR/tWRRD not playing well with main timings. Previously was 9/4, trying 8/3 (dram calculator), and next I'll try 7/1 (ryzen google calculator)
> 
> If neither help, I'll try increasing vdimm to 1.47 and again to 1.48.
> 
> Hopefully one of these changes will work.
> 
> @Veii Any thoughts on those errors? Completed 5 cycles with no errors, then in the 6th cycle, error 12, 10, 0


Stay in the dark then 

😂

I prefer to know what I'm playing with, knowing what the sticks do individually with save you heaps of time later

I spent hours and hours trying to get flat 14s to run at 3800, it's only once I tested the sticks individually I realised the amount of time I had lost as one of the sticks couldn't do tRCDRD @14


----------



## CarnageBT

mongoled said:


> Stay in the dark then
> 
> 😂
> 
> I prefer to know what I'm playing with, knowing what the sticks do individually with save you heaps of time later
> 
> I spent hours and hours trying to get flat 14s to run at 3800, it's only once I tested the sticks individually I realised the amount of time I had lost


I'm just hoping to dial these in at 3733 cl14. Not interested in pushing them to the max or seeing how far I can get.

You still think I should test individually? What is required? go back to the settings in the most recent zentimings picture and test to see if each stick passes? and If one doesn't do I relax tRDCRD to 15, 16, etc. until it passes?


----------



## musician

mongoled said:


> What vDIMM are you running ?
> 
> RTT Park set to 1 is dangerous for A0 PCBs when voltage exceeds 1.5v.
> 
> So check to see what PCB's your DIMMS are if you are going over 1.5v or increase RTT Park to 2 (120 ohms) or higher


Oh, I have no idea about PCB, there are some pics if you may help me to see please. I always leave the impedance and Setup sections on auto, I don´t understand how those values works at all. I am not much experienced about Ryzen ram oc, I am just a luker who copy some builds and see how it works for me lol, sometimes just trying to change something a bit. Still looking for THE build, however now I just took the CarnageBT posted build, it works for me with 1.465 VDIMM and I have the lowest latency in AIDA ever, 53.0! The best I have had ever, so thank you  I have always been at 55 range.


----------



## PJVol

Nighthog said:


> It has a quirky behaviour though


That applies not only to mem training, but the whole power management. It's the most annoying of all ryzen oddities I've seen so far. Happens all the time when I'm trying to stabilize performance at high FCLK, 1966+. If training was not done "properly", the cpu clocks starts stretching, sometimes up to 150+ mhz delta effective/performance, lowering bench scores. Recently noted the same thing, though its not 100% reproducible, that there's a higher chance of "successful" boot, if one let the PC to settle down a bit in uefi.
Sometimes it takes 3-4 reboots to enter relatively stable config. Really weird.


----------



## mongoled

CarnageBT said:


> I'm just hoping to dial these in at 3733 cl14. Not interested in pushing them to the max or seeing how far I can get.
> 
> You still think I should test individually? What is required? go back to the settings in the most recent zentimings picture and test to see if each stick passes? and If one doesn't do I relax tRDCRD to 15, 16, etc. until it passes?


Use your settings that passed the 10 cycle TM5. Just change tRCDRD to 14.

No other changes.

Use 1 stick at a time. Once a stick errors take it out and use the next stick until you get through the 4 sticks.

Don't play with any settings, you just want to find out if any of the sticks can run the flat 14s...


----------



## CarnageBT

mongoled said:


> Use your settings that passed the 10 cycle TM5. Just change tRCDRD to 14.
> 
> No other changes.
> 
> Use 1 stick at a time. Once a stick errors take it out and use the next stick until you get through the 4 sticks.
> 
> Don't play with any settings, you just want to find out if any of the sticks can run the flat 14s...


does it need a full 25 cycles? or is 10 sufficient for single stick?


----------



## mongoled

CarnageBT said:


> does it need a full 25 cycles? or is 10 sufficient for single stick?


I think you will know before the full 25 cycles

😉

Remember a single stick will take roughly a quarter of the time to cycle through 25 runs


----------



## mongoled

musician said:


> Oh, I have no idea about PCB, there are some pics if you may help me to see please. I always leave the impedance and Setup sections on auto, I don´t understand how those values works at all. I am not much experienced about Ryzen ram oc, I am just a luker who copy some builds and see how it works for me lol, sometimes just trying to change something a bit. Still looking for THE build, however now I just took the CarnageBT posted build, it works for me with 1.465 VDIMM and I have the lowest latency in AIDA ever, 53.0! The best I have had ever, so thank you  I have always been at 55 range.


You are OK then, your voltage is less than 1.5v so no worries 

 

Somone familiar with your RAM with hopefully post to inform what PCB they use


----------



## KedarWolf

CarnageBT said:


> does it need a full 25 cycles? or is 10 sufficient for single stick?


To be 100% sure my RAM is stable, I'll change the .cfg file from 100% to 1000% and 8 cycles and run it overnight.

On my 5950x with 2x16GB of RAM, it'll take a bit less than eight hours. If it passes that, I'm sure my RAM is stable.

I find 1000% rather than the standard 100% will find errors more reliably as the cycles are ten times longer. 🐺


----------



## KedarWolf

ManniX-ITA said:


> What did you use?
> On my 5950x works best:
> CPU VDD Full Scale Current = bit less than half of EDC limit eg 100A for EDC 215A
> CPU VDD Offset = 45 (for a 5600x probably 20-30 range would be better)
> CPU SOC Full Scale Current = 1/5/10A (doesn't really change much for me, all works the same till 10A)


G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 4400 (PC4 35200) Intel XMP 2.0 Desktop Memory Model F4-4400C17D-32GTRS - Newegg.com Maybe? Is b-die.


----------



## chozen-de

When testing for stability at 2000fclk (1:1) with TM5 (1usmus) I get no errors. But my Eventviewer is full of Wheas.
I'm using 1.2 vsoc, 900 vddp, 1060 vddg iod, 1000 vddg ccd.
Any way to fix this? Is my 5950x just not capable?


----------



## KedarWolf

chozen-de said:


> When testing for stability at 2000fclk (1:1) with TM5 (1usmus) I get no errors. But my Eventviewer is full of Wheas.
> I'm using 1.2 vsoc, 900 vddp, 1060 vddg iod, 1000 vddg ccd.
> Any way to fix this? Is my 5950x just not capable?


Most 5950x CPUs will NOT do 4000 1-1 WHEA free. I can only do 3800 on my 2x16GB but with really decent timings.


----------



## ManniX-ITA

KedarWolf said:


> G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 4400 (PC4 35200) Intel XMP 2.0 Desktop Memory Model F4-4400C17D-32GTRS - Newegg.com Maybe? Is b-die.


This one I didn't try 
But I'm very satisfied with the 4000C14, works as expected without #2/10 errors bringing down tRCDRD.


----------



## KedarWolf

ManniX-ITA said:


> This one I didn't try
> But I'm very satisfied with the 4000C14, works as expected without #2/10 errors bringing down tRCDRD.


Where did you buy it?


----------



## ManniX-ITA

KedarWolf said:


> Where did you buy it?





https://www.alternate.de/G-Skill/DIMM-32-GB-DDR4-4000-Kit-Arbeitsspeicher/html/product/1754138



From there; obviously I will replace the shameful Ripjaws heatsink.


----------



## KedarWolf

KedarWolf said:


> Where did you buy it?


Oh, I found them on newegg.ca. Super expensive.


----------



## ManniX-ITA

KedarWolf said:


> Oh, I found them on newegg.ca. Super expensive.


Indeed, very expensive.
But anything less is better to buy the 3200C14 then.
They are cheap and are the same as the 3600C16, 3800C14, 4000C16, etc.


----------



## MyUsername

ManniX-ITA said:


> Indeed, very expensive.
> But anything less is better to buy the 3200C14 then.
> They are cheap and are the same as the 3600C16, 3800C14, 4000C16, etc.


To be honest, I've had my eye on these since you mentioned your memory, remembered reading about them. Finding it hard to justify paying that £466, it's not far what I'm capable of already, mine can do 4000 cl16 1.55v easily, cl14 needs 1.6v but still get a few errors with tm5.


----------



## ManniX-ITA

MyUsername said:


> To be honest, I've had my eye on these since you mentioned your memory, remembered reading about them. Finding it hard to justify paying that £466, it's not far what I'm capable of already, mine can do 4000 cl16 1.55v easily, cl14 needs 1.6v but still get a few errors with tm5.


Yes that's the same I have but with LEDs which I don't want 
Really hard to justify.
My 4000C16 struggles with 16-17-16 at 2000 MHz and doesn't work at 14-17-16.
This one works flawlessly at 16-16-16 and also at 14-16-16.
I'm only struggling to find a good 14-15-15 profile with tight tertiary timings.
Probably also an overheating issue, I have to change the heat spreader.
Have good hopes when they'll be under the water loop...


----------



## MyUsername

ManniX-ITA said:


> Yes that's the same I have but with LEDs which I don't want
> Really hard to justify.
> My 4000C16 struggles with 16-17-16 at 2000 MHz and doesn't work at 14-17-16.
> This one works flawlessly at 16-16-16 and also at 14-16-16.
> I'm only struggling to find a good 14-15-15 profile with tight tertiary timings.
> Probably also an overheating issue, I have to change the heat spreader.
> Have good hopes when they'll be under the water loop...


If they can do this at 1.55-1.6v stable then I'll be more than happy to buy, mine errors.


----------



## Blameless

Have a new 5800X sample that's much better than my old one; still doesn't like over 1900 FCLK in any of my boards, however.

I also noticed some interesting performance oddities with reducing the SMU DPM values. 2-1-1-1-2-1-1-1 cost me ~10GiB/s of PCI-E bandwidth (tested with AIDA64 GPGPU, 3Mark's feature test, and some old PCI-E OCL test program I had), and about 200 points in Time Spy's graphics score vs. the AUTO settings. No wonder it seems to reduce the frequency of bus/interconnect errors...it's cutting performance of a major part of the SoC significantly.


----------



## ManniX-ITA

MyUsername said:


> If they can do this at 1.55-1.6v stable then I'll be more than happy to buy, mine errors.


I think that I was almost there at 1.56V but end up in overheating.
The Ripjaws heat spreader is a joke, this week I should change it and will try again.


----------



## PJVol

Blameless said:


> wonder it seems to reduce the frequency of bus/interconnect errors...it's cutting performance of a major part of the SoC significantly.


It depends on whether lclk run at 770mhz, otherwise i don't get, why setting dpm level capped at 2 ( 593mhz), or they are min DPM's ?


----------



## MyUsername

ManniX-ITA said:


> I think that I was almost there at 1.56V but end up in overheating.
> The Ripjaws heat spreader is a joke, this week I should change it and will try again.


My finger slipped and I accidentally got a set of 2x16 G.Skill 4000 cl14 gtzn, I haven't told the boss yet.


----------



## KedarWolf




----------



## craxton

Blameless said:


> SMU DPM values


and by that you mean??? is this something thats unlocked/unhidden in modded bois (fully unlocked) 
how does one know if this is already done?

perhaps its self explanatory as SMU-DPM might be in plain sight however, not had an unlocked bios very long.


----------



## craxton

MyUsername said:


> 2x16 G.Skill 4000 cl14 gtzn


i couldnt do it, i had a choice between this kit, a 5800x to play with, or 
a 4650G to which (they went up in pricing?) 

but i couldnt, almost got a "cheap" b550 board to test and see if my CPU still shows WHEA 19 free on a different board
but atm, im unsure id live long if i bought any of these items lol as the "boss" wont know until they get here...


----------



## craxton

Hmm, can someone tell what "fast short REP MOVSB-ENABLED and ENHANCED REP MOVSB/STOSB-ENABLED means? (I know enabled means it's on. But the board auto turned this on itself.


----------



## CarnageBT

Did a bunch of testing today. The results don't necessarily mean a lot to me, but may to some of you more experienced guys. You may be able to pick up a trend or pattern than I don't see. Here goes:

3733 Test 1









3733 test 1CyclesErrorSettings as pictured612, 10, 0 (all errors in cyycle 6)tRCDRD 1610 cyclesno errors (pictured settings /w tRCDRD 16)tRCDRD 14, Fix tFAW to 20 (4x tRRDS)- no test. only changed tfaw 21 to 20tRCDRD 16, tFAW 20, tRDWR 8 / tWRRD 335, 14, 9, 14tRCDRD 16, tFAW 20, tRDWR 9 / tWRRD 336, 13, 0, 15Settings as pictured (tFAW 20)33, 5, 9, 0pic, tfaw 20, 1.47 vdimm312, 2, 0, 3, 9pic, tfaw 20, 1.48 vdimm315, 15, 14, 11pic, tfaw 20, 1.45 vdimm211, 2, 4, 4, pic, tfaw 20, 1.45 vdimm, ProcODT 40514, 15, 2, 55, 1, 4, 3, (1st 2 errors in cycle 4, rest cycle 5)

3733 Test 2









3733 test 2CyclesErrorSettings as pictured (procODT to 40)514, 15, 2, 5, 1, 4, 3, (1st 2 errors in cycle 4, rest cycle 5)40 clkdrvstren, 40-20-24-2426, 10, 4, 3, 3, 3, 12, 0, 12, 2+ csodtdrvstren, 40-20-30-2030, 14, 5, 5Settings as pictured, 1.46 VDIMM315, 13, 11, Settings as pictured, 1.44 VDIMM31000's of errors.

3800 Test 1









3800 Test 1cycles2 complete cyclesPictured settings20, 1, 4, 13, 0, 9, 14, 14, 1, 1,VDIMM 1.5212, 2, 10, 0, 14, 14,RttNom 621, 1, 11, 12, 13, 13, 15VDIMM 1.48214, 10 - accidentally closed 1/2 way through 2nd cycletRAS 30, tRC 44, tFAW 42 (tCCD_l 7 x tRRDS)214, 11, 15, 0, 2, 10, 5, 5, 4, 14, 0, 15, 15, 6, 0, 6, 6, 6, 12, 0, 2, 2, 2, 10, 10, 10returned tRAS, tRC, tFAW to prrior valuesdidn't testPic + 1.06 vddg iod, 1.48vdimm, 40 procODT26, 6, 12, 2, 2, 2, 10, 10, 5, 4, 4, 4, 3, 3,RttNOM 6213, 9, 15, 6, 6, 6, 12, 12, 0, 2, 2, 2, 10, 5, 1, 4, 3, 13, 13, 9, 14, 0,RttNOM 7, 1.1 VSOC16, 12, 1.125 vsoc, .9 vddp/vddg ccd,210, 6, 6, 2, 2, 2, 2, 10, 10, 10, 0, 5, 5, 5, 5, 1, 4, 4, 3, 3, 3,

3800 Test 2









*note, cycles are ~9 minutes vs 6 (on 3733 or 3600 IF)7 cycles / 65 mins. Errors: 0, 0, 12, 14No errors until 45 min mark (in cycle 5), then 0, 0, back to backthen nothing until 58 min mark (in cycle 7), then 12 and 14.max dimm temp was 42.8 c


----------



## CarnageBT

Sorry for the testing dump, but I'm hoping the data makes sense to someone.

Is time until the first error useful? ie. if you error in cycle 1, your settings are far off the mark, vs your first error in cycle 10, would that imply your settings are getting closer to where they need to be?

Just curious as the last test I did for 3800 didn't error until the 45 minute mark, but only cycle 5 due to approx 9 minute cycles (i don't know why, it's around 6 on 3733 IF)


Some questions I haven't found answers to yet:

When I run 3600 or 3733 IF, TM5 tests take around 6 minutes as expected but when I run 3800 IF I notice they take around 9 minutes. Does this mean anything to anyone?
I tested my cpu CO settings at 3600 stock xmp (CC, p95, y cruncher all tests x 4, OCCT avx2 extreme small & large, etc...), but noticed that when I go to 3800 IF, some of the cores needed to be brought down further (now I have a curve for 3600 and a different one for 3800), why is that? is that expected and normal?
When testing, I'm sure there is a logical order. I have been dialing in the CPU CO, then moving to memory 2nd. When working with memory, there are so many variables. What is the correct order to dial things in? For example, I am trying 3733 and 3800 IF 2T, but keep producing errors. Should I focus on power first, procODT, then RTT values, CAD_Bus, then timings last?
When Dialing in procODT, do you need to run the full benchmark (discarding the 1st run), to get comparable latency numbers? OR can you simply dbl click the latency field for quicker results?
I don't understand how to dial in RTT values. Kind of a vague statement but, when I change an RTT, say RttPark, what do I do validate whether the change was good, bad, or better or worse? When I change rttPark, is there another variable I should also be changing to balance it? I understand the goal, is to have less RTTNOM/PARK, aka, high divider for both, 7/7, before touching RTTWR 3. As you increase the divider, I assume there is another corresponding value that needs to be increased? Like VDIMM? are there others?
Hopefully, I'm getting close. That final run at 3800 felt like it was getting closer.

@Veii - I just realized tonight, while re-reading the whole thread that I had incorrect tRFC values when we were testing (was using 42 x 7, but you had me change tRC to 50)

edit:
Here's an aida benchmark from the final 3800 settings I tested. I also ran the first 3 tests in y cruncher 4 times without error to test IF stability.


----------



## ManniX-ITA

Blameless said:


> I also noticed some interesting performance oddities with reducing the SMU DPM values. 2-1-1-1-2-1-1-1 cost me ~10GiB/s of PCI-E bandwidth (tested with AIDA64 GPGPU, 3Mark's feature test, and some old PCI-E OCL test program I had), and about 200 points in Time Spy's graphics score vs. the AUTO settings. No wonder it seems to reduce the frequency of bus/interconnect errors...it's cutting performance of a major part of the SoC significantly.


Can't reproduce it.
What is your configuration?
In 3DMark feature test what is the speed you expect and what you get?

I have a GTX 1070 and it doesn't flinch from 13.05 GB/s in 3DMark whatever is the LCLK setting.


----------



## KedarWolf

ManniX-ITA said:


> Can't reproduce it.
> What is your configuration?
> In 3DMark feature test what is the speed you expect and what you get?
> 
> I have a GTX 1070 and it doesn't flinch from 13.05 GB/s in 3DMark whatever is the LCLK setting.


With 2-1-1-2 settings I get 100 points more read/write/copy in AIDA64.


----------



## ManniX-ITA

KedarWolf said:


> With 2-1-1-2 settings I get 100 points more read/write/copy in AIDA64.


Have to try, never noticed a change in AIDA!


----------



## mongoled

PJVol said:


> That applies not only to mem training, but the whole power management. It's the most annoying of all ryzen oddities I've seen so far. Happens all the time when I'm trying to stabilize performance at high FCLK, 1966+. If training was not done "properly", the cpu clocks starts stretching, sometimes up to 150+ mhz delta effective/performance, lowering bench scores. Recently noted the same thing, though its not 100% reproducible, that there's a higher chance of "successful" boot, if one let the PC to settle down a bit in uefi.
> Sometimes it takes 3-4 reboots to enter relatively stable config. Really weird.


I see the same thing,

hopefully we will get an agesa that is able to keep everything sync/trained with higher FCLK.

Looks like I am going to have to let go of 4133/2067, runs stable under load when all cores are loaded, not so much when its light loads.

Throws WHEA 18s that are usually associated with CPU vCore, but after my extensive testing its being effected by the high FCLK.....


----------



## Blameless

ManniX-ITA said:


> Can't reproduce it.
> What is your configuration?
> In 3DMark feature test what is the speed you expect and what you get?
> 
> I have a GTX 1070 and it doesn't flinch from 13.05 GB/s in 3DMark whatever is the LCLK setting.


5800X custom PBO @ 1900 FCLK and an overclocked 6800XT along with a PCI-E 4.0 primary SSD on an ASRock B550 Phantom Gaming-ITX/ax.

I expect 26-28GiB/s, which is what I get on auto, but with the DPM LCLK set to 2-1-1-1-2-1-1-1 I get ~17.

It doesn't appear to be a limiting factor for PCI-E 3.0 devices.



KedarWolf said:


> With 2-1-1-2 settings I get 100 points more read/write/copy in AIDA64.


I'll have to try 2-1-1-2

Is that vs. auto or vs. 2-1-1-1?


----------



## NDS322

Can someone answer me about that AGESA 1.2.0.3 Patch A still get WHEA Error Code 19 with 4000MHz 1:1 of RAM ?


----------



## Blameless

2-1-1-2 seems to allow for full PCI-E speed on my system:









No change in system memory performance, but I wouldn't expect the LCLK to have any bearing on that since it shouldn't touch the memory controller (UCLK).









AMD Ryzen Clock Domains Detailed - Tech Altar


Ryzen's clock domains have been detailed in a diagram from AMD's GDC event. Read here for more information!




thetechaltar.com







PJVol said:


> It depends on whether lclk run at 770mhz, otherwise i don't get, why setting dpm level capped at 2 ( 593mhz), or they are min DPM's ?


The description of the setting in my board's UEFI suggests DPM 2 caps the data launch clock at 600MHz while DPM 1 is 300MHz.



craxton said:


> and by that you mean??? is this something thats unlocked/unhidden in modded bois (fully unlocked)
> how does one know if this is already done?
> 
> perhaps its self explanatory as SMU-DPM might be in plain sight however, not had an unlocked bios very long.


There is an option in the AMD CBS/SMU options that caps the various LCLK speeds. Veii suggested that incorrect settings here could be responsible for trouble at high FCLKs (which did seem to be the case, to some degree, in my testing...both 2-1-1-1 and 2-1-1-2 reduced the number of WHEA bus/interconnect warning I was seeing, but didn't eliminate them). So I've been playing with reduced values. 2-1-1-2 is probably a keeper, but 2-1-1-1 is enough to reduce PCI-E performance on my setup.

Not all boards have this option revealed. My ASRock and MSI B550s do, but my Gigabyte X570 Elite Wifi does not.

Edit: Found the settings in the newest bios for my Gigabyte board.


----------



## ManniX-ITA

KedarWolf said:


> With 2-1-1-2 settings I get 100 points more read/write/copy in AIDA64.


At FCLK 2000 for me it's +150 Write and about 0.2-0.4ns better latency, at 2-1-1-1 the average is 53.2ns with dips to 53.1ns while at 2-1-1-2 gets down to regular 52.9ns:



















Blameless said:


> No change in system memory performance, but I wouldn't expect the LCLK to have any bearing on that since it shouldn't touch the memory controller (UCLK).


I see a difference although not the same as Kedar.



NDS322 said:


> Can someone answer me about that AGESA 1.2.0.3 Patch A still get WHEA Error Code 19 with 4000MHz 1:1 of RAM ?


Doesn't change a thing about WHEA at FCLK 2000. Only worse for me at high FCLK, went back to 1.2.0.1.


----------



## Blameless

ManniX-ITA said:


> I see a difference although not the same as Kedar.


Interesting.

Could be having more of an effect on dual CCD parts.


----------



## mongoled

NDS322 said:


> Can someone answer me about that AGESA 1.2.0.3 Patch A still get WHEA Error Code 19 with 4000MHz 1:1 of RAM ?


Completely normal unless you won the silicon lottery for all your parts!


----------



## ManniX-ITA

Blameless said:


> Interesting.
> 
> Could be having more of an effect on dual CCD parts.


Indeed; the big latency gain was due to a very lucky training at boot seems... now it's at an average of 53.1ns, about 0.1ns better than Auto DPM LCLK..


----------



## mongoled

Trying out 1.2.0.3 again,

so far after several reboots its behaving at 4133/2067.

No stability tests as of yet, audio is great, no USB issues yet, waiting for a WHEA 18

🤣😄

** EDIT **
Back to BCLK I go......


----------



## rossi594

Do you guys believe that the "holes" or whea 19s are ever going away with new agesa / gpu drivers / windows versions? I am running 3600 cl 14 right now I can't run 3666 cl14, 1900 MHz flck is not even posting. 2000 MHz cl 16 runs smooth but troughs whea 19s.

I believe 2000 cl 16 would be my best setup but I don't feel comfy tuning everything with the wheas. I would be fine running 3800 cl 16 if the hole was gone.

Right now it just feels like wasting your time ocing ram if the infinity fabric isn't stable or troughing whea 19s ...


----------



## mongoled

rossi594 said:


> Do you guys believe that the "holes" or whea 19s are ever going away with new agesa / gpu drivers / windows versions? I am running 3600 cl 14 right now I can't run 3666 cl14, 1900 MHz flck is not even posting. 2000 MHz cl 16 runs smooth but troughs whea 19s.
> 
> I believe 2000 cl 16 would be my best setup but I don't feel comfy tuning everything with the wheas. I would be fine running 3800 cl 16 if the hole was gone.
> 
> Right now it just feels like wasting your time ocing ram if the infinity fabric isn't stable or troughing whea 19s ...


I think we are all in the dark!

Each agesa that passes nothing that us overclockers want bear fruition


----------



## PJVol

rossi594 said:


> Do you guys believe that the "holes" or whea 19s are ever going away with new agesa / gpu drivers / windows versions?


I don't. I beleive it's 99% hardware limit of current DF implementation.


----------



## byDenoso

Hello Guys!
Any hints to tune my Hynix DJR Ram?
Especially with CAD-BUS timings and Proc ODT
@Veii Can you save me?


----------



## T[]RK

Veii said:


> DF-States, AMD CBS - NBIO - SMU , DF-States ~ has to be disabled in order to prevent, sleep to wake up overboost


Since GIGABYTE uploaded new BIOS for my motherboard - F61c i can finally try it too. There are so many new options...

Also, i still didn't tested [email protected], sice i was really busy lowering tWTR_L from 12 to 8 (i founded interesting what you told before that _S is just base and later used muliplier x2 or x3). So, i used my [email protected] and just lowered one value:

tWTR_L=8
Errors 5, [email protected] (explosion)

tWTR_L=8 + vDIMM 1.42V
Error [email protected] (at this stage i thinking that it's simply overheat, but now i can say it was wrong)

tWTR_L=8 +vDIMM 1.42V + Fan
Error [email protected] (So, 6 more cycles, but still error, but not 13, so no overheat?)

tWTR_L=8 + tCKE=9
Errors 10, 5 (explosion)

===== Some play with tCKE and Error list
tWTR_L=8 + vDIMM 1.42V + tCKE=9 + tRDWR=8 + tWRRD=1
Error [email protected]

tWTR_L=8 + vDIMM 1.42V + tCKE=9 + tRDWR=8 + tWRRD=2
Error... Can't run ZenTimings in Windows - Error in Kernel.dll in Event viewer

tWTR_L=8 + vDIMM 1.42V + tCKE=9 + tRDWR=8 + tWRRD=3
Error [email protected]

tWTR_L=8 + vDIMM 1.42V + tCKE=9 + tRDWR=9 + tWRRD=1
Error [email protected]

tWTR_L=8 + vDIMM 1.42V + tCKE=9 + tRDWR=9 + tWRRD=2
Error [email protected] (No Kernel error at ZenTimings run)

tWTR_L=8 + vDIMM 1.42V + tCKE=9 + tRDWR=9 + tWRRD=3
Error [email protected]

tWTR_L=8 + vDIMM 1.42V + tCKE=9 + tRDWR=10 + tWRRD=1
Error [email protected]

After that "pattern" look obvious and repeatable. Wrong path.
=====

tWTR_L=8 + vDIMM 1.44V
Error [email protected] So... it was only because of voltage. After i added +0.02V more - it was O.K. No overheat and no Fan used.







So, i play a bit with tRFC lowering and then try CL15. I need that [email protected] for base (default) profile. I want to use something when i not in a mood to play with TM5 and all this "memory stuff" since i can't use XMP-profile with DDR-4133. I have no boot with it.


----------



## oobymach

CarnageBT said:


> Did a bunch of testing today. The results don't necessarily mean a lot to me, but may to some of you more experienced guys. You may be able to pick up a trend or pattern than I don't see. Here goes:
> 
> 3733 Test 1
> View attachment 2513540
> 
> 
> 3733 test 1CyclesErrorSettings as pictured612, 10, 0 (all errors in cyycle 6)tRCDRD 1610 cyclesno errors (pictured settings /w tRCDRD 16)tRCDRD 14, Fix tFAW to 20 (4x tRRDS)-no test. only changed tfaw 21 to 20tRCDRD 16, tFAW 20, tRDWR 8 / tWRRD 335, 14, 9, 14tRCDRD 16, tFAW 20, tRDWR 9 / tWRRD 336, 13, 0, 15Settings as pictured (tFAW 20)33, 5, 9, 0pic, tfaw 20, 1.47 vdimm312, 2, 0, 3, 9pic, tfaw 20, 1.48 vdimm315, 15, 14, 11pic, tfaw 20, 1.45 vdimm211, 2, 4, 4,pic, tfaw 20, 1.45 vdimm, ProcODT 40514, 15, 2, 55, 1, 4, 3, (1st 2 errors in cycle 4, rest cycle 5)
> 
> 3733 Test 2
> View attachment 2513541
> 
> 
> 3733 test 2CyclesErrorSettings as pictured (procODT to 40)514, 15, 2, 5, 1, 4, 3, (1st 2 errors in cycle 4, rest cycle 5)40 clkdrvstren, 40-20-24-2426, 10, 4, 3, 3, 3, 12, 0, 12, 2+ csodtdrvstren, 40-20-30-2030, 14, 5, 5Settings as pictured, 1.46 VDIMM315, 13, 11,Settings as pictured, 1.44 VDIMM31000's of errors.
> 
> 3800 Test 1
> View attachment 2513542
> 
> 
> 3800 Test 1cycles2 complete cyclesPictured settings20, 1, 4, 13, 0, 9, 14, 14, 1, 1,VDIMM 1.5212, 2, 10, 0, 14, 14,RttNom 621, 1, 11, 12, 13, 13, 15VDIMM 1.48214, 10 - accidentally closed 1/2 way through 2nd cycletRAS 30, tRC 44, tFAW 42 (tCCD_l 7 x tRRDS)214, 11, 15, 0, 2, 10, 5, 5, 4, 14, 0, 15, 15, 6, 0, 6, 6, 6, 12, 0, 2, 2, 2, 10, 10, 10returned tRAS, tRC, tFAW to prrior valuesdidn't testPic + 1.06 vddg iod, 1.48vdimm, 40 procODT26, 6, 12, 2, 2, 2, 10, 10, 5, 4, 4, 4, 3, 3,RttNOM 6213, 9, 15, 6, 6, 6, 12, 12, 0, 2, 2, 2, 10, 5, 1, 4, 3, 13, 13, 9, 14, 0,RttNOM 7, 1.1 VSOC16, 12,1.125 vsoc, .9 vddp/vddg ccd,210, 6, 6, 2, 2, 2, 2, 10, 10, 10, 0, 5, 5, 5, 5, 1, 4, 4, 3, 3, 3,
> 
> 3800 Test 2
> View attachment 2513543
> 
> 
> *note, cycles are ~9 minutes vs 6 (on 3733 or 3600 IF)7 cycles / 65 mins. Errors: 0, 0, 12, 14No errors until 45 min mark (in cycle 5), then 0, 0, back to backthen nothing until 58 min mark (in cycle 7), then 12 and 14.max dimm temp was 42.8 c


Change your secondary timings, tRDRDSD and tRDRDDD to 5, tWRWRSD tWRWRDD to 7, I kept getting errors with these at 4 and 6.


Also: I get more fps from my gpu if I run the trfc = trc x8, ram runs a hair slower but the fps boost is real. You can use this handy dandy tool.









tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com





My timings for reference, in this case 42 x 8 = 336


----------



## Blameless

ManniX-ITA said:


> Indeed; the big latency gain was due to a very lucky training at boot seems... now it's at an average of 53.1ns, about 0.1ns better than Auto DPM LCLK..


Training variances make it almost impossible to pin down subtle changes in performance. Since there isn't any technical reason for the LCLK to influence memory performance--unless one's SoC is running into a TDC/EDC limit, or one is running out of memory and paging--the safest assumption is that it doesn't.


----------



## PJVol

Has anyone got B1 revision chip?


----------



## KedarWolf

PJVol said:


> Has anyone got B1 revision chip?


Yes, my 16-16-16-36 3600 B1.


----------



## PJVol

KedarWolf said:


> Yes, my 16-16-16-36 3600 B1


Sorry for being vague, I meant CPU 19h family revision


----------



## jomama22

oobymach said:


> Change your secondary timings, tRDRDSD and tRDRDDD to 5, tWRWRSD tWRWRDD to 7, I kept getting errors with these at 4 and 6.
> 
> 
> Also: I get more fps from my gpu if I run the trfc = trc x8, ram runs a hair slower but the fps boost is real. You can use this handy dandy tool.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> My timings for reference, in this case 42 x 8 = 336
> 
> View attachment 2513602


This genuinely sounds like you are just more stable than you were previously So you don't have auto-correction kicking in as much as opposed to 8 x trc = tRFC being better for games.


----------



## craxton

PJVol said:


> Sorry for being vague, I meant CPU 19h family revision


are you speaking on the second line on the CPU heatspreader?

or would CPUz tell this?
(heat spreader says BG
(B0 but family is 19) 
sorry for responding thought i might have just what you were asking for.


----------



## Iarwa1N

I have a new problem with my rams. My system wont boot up after it has been shut down for a while. Memory error led stays lid and I have to remove the sticks, clear cmos and put them again to be able to boot. This even happens on docp 3200 mhz. I have a strix b550-f, 5900x and 16x2 3200 cl14 samsung b-dies. I tried increasing cl and trcd to 15, tried increasing procodt. Any advice?


Sent from my iPhone using Tapatalk


----------



## oobymach

jomama22 said:


> This genuinely sounds like you are just more stable than you were previously So you don't have auto-correction kicking in as much as opposed to 8 x trc = tRFC being better for games.


Idk why it works, but I went from 315 to 327 fps in furmark with only that change. Now it seems to have taken and works for other speeds.


----------



## wuttman

nvm


----------



## braveblades

Hello everyone, I'm new to this forum. As one of many I have changed from intel to amd. 
I'm still trying to get the most efficient and stable OC, so I looked through most of the pages in this thread.

My current platform is *5900x + ASUS Crosshair VIII Dark Hero + 32GB (2x16) G.Skill F4-3600C16-16GTZN*. 

Voltage: 
DRAM: 1.41
SOC: 1.05 
VDDG CCD: 0.900
VDDG IOD: 1.050
CLDO VDDP: 0.880

Here you can see my results based largely on these community advice - *special thanks to Veii for his advice*

















I'am aware that my settings are on 1T (not 2T). However, on these settings my system is rock-solid (tm5 - 20 cycles, karhu 8000% + working heavily 3D/multi-app over 12-16h per day). 

Looking at the experience of the people on this forum Iam convinced that I could get better results. The most important thing is that *my goal is to get the most efficient but stable configuration that I can work on for up to 12 hours a day* (I don't want to do OC to get the best benchmark results). 

I will be grateful for any hints and advice on what I can do better with my configuration. BTW - of course I also play games sometimes 😉 ..in 1440p.


----------



## braveblades

KedarWolf said:


> Yes, my 16-16-16-36 3600 B1.
> 
> View attachment 2513625


KedarWolf, i try to use your settings, but with no-luck.. i mean no boot...  and have the same dram. could you look at my earlier post about my config and voltage? maybe i doing something wrong... thank you!


----------



## musician

KedarWolf said:


> Yes, my 16-16-16-36 3600 B1.
> 
> View attachment 2513625


Hello, since my ram is B1 too, I shamelessly took your build. Now, I got 1 error in test #6. My TM5 is set as you recommended, changed to 1000%, 8 cycles.
According to @Veii 1usmus errors explanations, one single error in test #6 = "_fix RTT values or give it +1 VDIMM_". I would like to leave increasing VDIMM as the last possible option.
Please, any chance you could see if the RTT values are wrong in my case, or how to fix it?


----------



## Veii

About DPM , LCLK and similar
Let me drop you this little tool
Bios Modding - Google Drive Tool1007.zip (tool.exe)

Have fun with it 
Single CCD can run








To override allcore EDC throttle
You still should set Bios PBO EDC limit higher soo cache can boost up
But this overrides another stage of allcore throttling








This is interesting for you , just the plotting is a bit strange to use
And this is what you surely will like to see









Enjoy experimenting
Each of the 8 "Frequency Limiters" Sensors can be the cause of frequency loss
FIT PPT throttle usually appears because of something else, still searching for the value

DPM doesn't show up correctly and the ASRock ITX misses LCLK optionality to enable it. The Asus board had it
Some values are under a wrong multiplier but there are valuable things to check and read out
Effective Clock is correct for example
Also it shows fully how many CCDs and Cores you have ~ for all these mysterious samples out there









Copyright belongs to the ASUS Forums as XOC tool
I forgot who published it and which team maintains it.
No credit belong to me, just want to make it easier accessible to people 

Waiting for 1.2.0.3A for the ITX board, then i'm gonna check out what can be done for the public
113 Binning value is already good, 118 is fantastic - haven't seen 120+ so far









DPM 2-1-1-2 doesn't show it
testing 2-2-1-1 too ~ but this is intercore stuff. SiSoftware Sandra is your best friend for such
This one is neat, but only ASUS boards let access to RAW VRM controller








Apparently there should be an I²C port on the ITX , but i haven't checked
=========================================
MEM-OC thread, soo here are some valuable RTTs for Rev.E@1.6v or XMP under 56.50















I lack a lot of options on the ASRock bioses - but 1203A update needs to be out, before it has any modding potential or consideration
* on the Drive link above, AMI_FLASH Win can flash unsigned bioses ~ as long as the DeviceID remains identical. It bypasses AMDs SPI lock but is not able to cross-flash bioses
Backups of it are sector based and tiny ~ do no use it for backup purposes, unless you can stitch bioses together (HEX)


----------



## ManniX-ITA

Veii said:


> 113 Binning value is already good, 118 is fantastic - haven't seen 120+ so far


This opens quite some interesting doors 

Now you got a 125... but my silicon quality is not that good, not sure how reliable is this metric eheh










Also see my FIT VID is 1.5V and the Limit is a monstrous 52K:


----------



## Veii

ManniX-ITA said:


> This opens quite some interesting doors
> 
> Now you got a 125... but my silicon quality is not that good, not sure how reliable is this metric eheh
> 
> View attachment 2513669
> 
> 
> Also see my FIT VID is 1.5V and the Limit is a monstrous 52K:
> 
> View attachment 2513672


Speaking of this, i just figured most of the throttling reasons out

CCA will throttle if you hit FIT limit
ProcHot will throttle surely after 70c (can't test it lower & the ranges, my cooling solution can not keep up)

FIT Limit is dynamic and it's peak + low state changes
The way to change it inside OS is that way








X * 1.923416666666667 = FIT assigned value (probably more decimals again)
If you decrease FIT Limit - it decreases the Low limit, that way it will throttle CCA , but not voltage

If you want to throttle Voltage, you need to change EDC, TDC Limit
Values there work was 420 000 (3 digits for mA to A)
What you see here are my motherboard limits and the remain zombie cores ~ while this time only 6 are sleepy and 9 are functioning (OS can only assign load to 6 till i OPN ID rebrand it somehow)
You can go quite low on FIT Limit, till it actually starts to throttle because of FIT limit
Oor you can increase it, till CCA doesn't throttle anymore ~ when it's not EDC that throttles first

THM (Processor max Throttle Temp) Limit is 95c
I think it throttles from 60c upwards, but i can not test it
It surely does throttle allcore loads from 70c onwards
CCA at least we can not "fix/bypass" and so extend FIT Throttling a bit 🤭

* Be sure to check AMD Monitor & Vermeer Monitor , which one works for you & has correct EDC Limit or Relative Freq (values)
If you write a target Freq in the V/F tool , and press "Get Voltage" it will tell you (after Sillicon test) what the required VID is for this Freq ~ for your silicon
Negative CO doesn't change that quality value - but it's +/- 0.5 [Value] Variable
** running it together with HWInfo will crash it after 60-90sec

EDIT:
FIT PRE ~ shows highest possible boost voltage before throttle
Tried experimenting with Scalar values, but there is no visible change on ~anything~
_* maybe it's a multiplier for FIT Peak value, unsure yet ~ i see nothing changing_

EDIT 2:
Bingo , found it
ProcHot - preprogrammed for me is 65c , afterwards it throttles down
soo either every 5c or they got it every 1c
It's a 125mhz cut for 10c 

EDIT 3:
That reminds me, @ManniX-ITA
You likely can lower FIT limit quite low to tame heat - yet lift EDC limit , soo your cache bursts high in the 1600+ range
The Value till CCA throttles "on an allcore" because of FIT Limit, is quite low ~ soo you have headroom
It will first throttle because of EDC Limit (or reaching near it) & lose a lot of L3 Cache perf with the low EDC limit


----------



## Robostyle

2 fruitless months of searching...so I guess I better ask again straight here.
Guys - is there any way to fix this?









I really don't get it - while RAM and system completely stable in all tests (The screenshot shows only 30%, but I've got 200% stable) and no BSoDs, I get these interconnect whea. No additional voltage help in solving this thing either. Even more confusing that I started getting these errors after a fresh Win10 install - if only I didn't reinstall it, I would ran my mem [email protected] happily :/


----------



## rossi594

Robostyle said:


> 2 fruitless months of searching...so I guess I better ask again straight here.
> Guys - is there any way to fix this?
> View attachment 2513682
> 
> 
> I really don't get it - while RAM and system completely stable in all tests (The screenshot shows only 30%, but I've got 200% stable) and no BSoDs, I get these interconnect whea. No additional voltage help in solving this thing either. Even more confusing that I started getting these errors after a fresh Win10 install - if only I didn't reinstall it, I would ran my mem [email protected] happily :/


You should check the event viewer -> custom view -> source = whea logger. But I would assume these are the whea 19 warnings. I don't know anyone running flck 1900+ that doesn't have any.


----------



## musician

ignore


----------



## Hibbing

Veii said:


> Waiting for 1.2.0.3A for the ITX board, then i'm gonna check out what can be done for the public
> 113 Binning value is already good, 118 is fantastic - haven't seen 120+ so far


----------



## domdtxdissar

Some numbers while running CTR RC6 v20








CTR settings: (cpu gamemode in timespy)








Numbers while benching CPU-Z multicore with CTR enabled:


----------



## KedarWolf

musician said:


> Hello, since my ram is B1 too, I shamelessly took your build. Now, I got 1 error in test #6. My TM5 is set as you recommended, changed to 1000%, 8 cycles.
> According to @Veii 1usmus errors explanations, one single error in test #6 = "_fix RTT values or give it +1 VDIMM_". I would like to leave increasing VDIMM as the last possible option.
> Please, any chance you could see if the RTT values are wrong in my case, or how to fix it?


I run 1.2v VoC, 1.1v and 1.15v VDDGs, 1.48v memory in BIOS.

Those voltages might stop the error.


----------



## KedarWolf

Hibbing said:


> View attachment 2513684


Where do you get the AMD V/F tool. I'd like to check my Sil Quality.


----------



## KedarWolf

braveblades said:


> Hello everyone, I'm new to this forum. As one of many I have changed from intel to amd.
> I'm still trying to get the most efficient and stable OC, so I looked through most of the pages in this thread.
> 
> My current platform is *5900x + ASUS Crosshair VIII Dark Hero + 32GB (2x16) G.Skill F4-3600C16-16GTZN*.
> 
> Voltage:
> DRAM: 1.41
> SOC: 1.05
> VDDG CCD: 0.900
> VDDG IOD: 1.050
> CLDO VDDP: 0.880
> 
> Here you can see my results based largely on these community advice - *special thanks to Veii for his advice*
> 
> View attachment 2513655
> View attachment 2513656
> 
> 
> I'am aware that my settings are on 1T (not 2T). However, on these settings my system is rock-solid (tm5 - 20 cycles, karhu 8000% + working heavily 3D/multi-app over 12-16h per day).
> 
> Looking at the experience of the people on this forum Iam convinced that I could get better results. The most important thing is that *my goal is to get the most efficient but stable configuration that I can work on for up to 12 hours a day* (I don't want to do OC to get the best benchmark results).
> 
> I will be grateful for any hints and advice on what I can do better with my configuration. BTW - of course I also play games sometimes 😉 ..in 1440p.


2T GDM disabled actually better than 1T GDM Enabled. And GDM Enabled some timings like the ones set to 15 will go to 16.


----------



## T[]RK

KedarWolf said:


> Where do you get the AMD V/F tool. I'd lie to check my Sil Quality.


From @Veii post. Tool1007 in archive. You need to run Tool.exe and then select "DB Query" Tab and then "AMD V\F" and "Gel Sil Quality".

My result ~117 with 900-940-980V on VDDP, VDDG CCD\IOD.


----------



## Robostyle

rossi594 said:


> You should check the event viewer -> custom view -> source = whea logger. But I would assume these are the whea 19 warnings. I don't know anyone running flck 1900+ that doesn't have any.


Yes, I see those 19s. 

It's just I saw people in this thread running fclk 2000-2033 without any of these.
I do get some performance drop at 2000 fclk. whea start at 1900fclk:3800mem, 3800-3933 mem without penalty though


----------



## KedarWolf

If it helps anyone, ALL of my BIOS settings.

Unlocked BIOS though, some options you may not have access to.

The only thing different from the screenshots is IP8 voltage at 1.8v and VDIMM voltage at 1.48v.





http://imgur.com/a/ZkrrKj5


Oh, and below at 115/50/10


----------



## jomama22

KedarWolf said:


> 2T GDM disabled actually better than 1T GDM Enabled. And GDM Enabled some timings like the ones set to 15 will go to 16.


I'll be that guy for a moment.

Better for what? Aside from internal mux's being at half speed and some timings needing to be even, what quantifiable benefit does it provide?

I always see this claimed without any sort of actual metric used to show a benefit one way or the other. Timings for both would have to be the exact same as well for it to be a 'fair fight" and it seems most cannot keep their same timings when moving to 2t from gdm.

And I DONT mean aida latency differences lol


----------



## KedarWolf

T[]RK said:


> From @Veii post. Tool1007 in archive. You need to run Tool.exe and then select "DB Query" Tab and then "AMD V\F" and "Gel Sil Quality".
> 
> My result ~117 with 900-940-980V on VDDP, VDDG CCD\IOD.


ty


----------



## CarnageBT

Is this normal? I set 3733 IF and 1867 fclk, 1:1, with auto xmp timings, then played around with voltages.


Testing Voltage Stability @ 3733 /w auto timingsvSOCVDDPCCDIODVDIMM1.10.91.11.11.46MOBO Defaults + 1.46vdimm45 mins, error 4, 2, 10 - pcb crash, voltage, timing1.1250.880.881.061.46my settings from before~ 40 mins, cycle 5, error 2, cycle 7/53 mins, no further errors - timing, voltage,1.1250.90.981.061.46add vddp / ccd45 mins, 13, 12, total time 53m. stop - timing, voltage1.1250.880.881.061.48my settings, add vdimm1h30m, error 6, Total time, 2h53m, no others errors. either +1 vdimm or less vSOC - IMC voltage1.10.880.881.061.48^ same but less vSOC1h58m, cycle 15, error 15. stopped at 2h16m, no other errors - timing1.10.880.880.881.48& same, less vsoc and way low IODerror 12. 3h30m total. unknown when error occured - voltage1.10.880.880.881.47untested yet1.10.880.880.881.49untested yet1.10.880.920.961.4846 mins, cycle 6, error 0 - voltage10.880.920.961.4827 mins, cycle 4, error 2. voltage - IOD or SOC - pretty sure vSOC too low1.10.880.961.04tbduntested yet1.10.90.90.9tbduntested yet1.10.90.940.98tbduntested yet1.10.90.981.06tbduntested yet

I'm still uncertain if longer time before first error implies better, ie. 2hrs before first error vs 1.5h. 

Is it weird that I could run 0.88 on vddp and vddg, both ccd/iod, and the results were only 1 error over a full 25 cycles?

If my VDDP and VDDG CCD like to be matched 1:1, what is the ideal stepping for vddg IOD? 40/80/160mv


----------



## domdtxdissar

jomama22 said:


> I'll be that guy for a moment.
> 
> Better for what? Aside from internal mux's being at half speed and some timings needing to be even, what quantifiable benefit does it provide?
> 
> I always see this claimed without any sort of actual metric used to show a benefit one way or the other. Timings for both would have to be the exact same as well for it to be a 'fair fight" and it seems most cannot keep their same timings when moving to 2t from gdm.
> 
> And I DONT mean aida latency differences lol


I did the testing like 100 pages back, but ever since then, "i hate aida64" according to some.









T2 vs T1 GDM


----------



## CarnageBT

domdtxdissar said:


> I did the testing like 100 pages back, but ever since then, "i hate aida64" according to some.
> 
> View attachment 2513695
> 
> 
> T2 vs T1 GDM


Ahh, read your post from way back when. Good to know. I'm having a hell of a time getting my 4x8 sticks set up with 2T. Gave up and now trying to get them to run 1T with GDM.


----------



## CarnageBT

domdtxdissar said:


> I did the testing like 100 pages back, but ever since then, "i hate aida64" according to some.
> 
> View attachment 2513695
> 
> 
> T2 vs T1 GDM


Why does your VDIMM and VTT MEM show N/A? due to some other settings?


----------



## domdtxdissar

CarnageBT said:


> Why does your VDIMM and VTT MEM show N/A? due to some other settings?


Zentimings cant read those voltages on asus motherboards.. Hwinfo can read vdimm tho. (vtt mem is almost always half vdimm)


----------



## CarnageBT

domdtxdissar said:


> Zentimings cant read those voltages on asus motherboards.. Hwinfo can read vdimm tho. (vtt mem is almost always half vdimm)


What is your VDIMM set at?


----------



## domdtxdissar

CarnageBT said:


> What is your VDIMM set at?


Highlighted in blue (inside hwinfo)







1.54 vdimm in bios

These are newer 4x8GB settings than those i used to benchmark T2 vs GDM T1
Newest settings iam currently using


----------



## Veii

rossi594 said:


> I don't know anyone running flck 1900+ that doesn't have any.


Don't forget me 
I don't use any WHEA suspender
* 2100 FCLK


----------



## Robostyle

Veii said:


> Don't forget me
> I don't use any WHEA suspender
> * 2100 FCLK


So whats the solution?


----------



## musician

Robostyle said:


> So whats the solution?


Win CPU silicon lottery


----------



## jomama22

domdtxdissar said:


> I did the testing like 100 pages back, but ever since then, "i hate aida64" according to some.
> 
> View attachment 2513695
> 
> 
> T2 vs T1 GDM


Yeah, I'm aware of this and meant to include it but I wasn't about to search for it lol.

Beyond this, no one has posted a single thing, just requoting 2t being better than gdm until it became a fact without any real metric basis. 

The crappy part about sottr is it's inconsistencies run to run. I'm genuinely surprised reviewers use it as a comparison outside of having some range to average. Pure maximum result seems to be somewhat ok to use but even then it's a 'stars align' type deal.


----------



## limjh1221

@Veii 

no WHEA is dual ccd related?

this is dual ccd 5800x.

from korea.









other's post









5600x with dual CCD Tuning


Hey everyone, I couldn't find any discussion on the Ryzen 5600x with the dual CCD's: Ryzen 5 5600X and Ryzen 7 5800X with 2 CCDs spotted, can the CPU be unlocked to Ryzen 9? Just wondering how many people out there that have these unique processors and what sort of performance or overclocking...




www.overclock.net


----------



## Robostyle

musician said:


> Win CPU silicon lottery


Soo, I've lost the lottery when reinstalled OS?)


----------



## musician

Robostyle said:


> Soo, I've lost the lottery when reinstalled OS?)


How long did you run without WHEAs before the reinstall?


----------



## Robostyle

musician said:


> How long did you run without WHEAs before the reinstall?


Don't remember exactly, ~3 weeks, just dialed 4000 Mhz, 2000MHz fclk, set the voltages - don't remember about IOD though. And after the assemble and it ran flawlessly.

P.S. Okay so seems like I'm close to figuring it out. Looks like my CPU likes voltages too much, especially VDDP. I'm stable again at 3866 MHz, no WHEA, but I've had to raise SOC to 1.2V and VDDP/VDDG voltages to 1.15V (safe limit is something like 1.05V, right?)


----------



## Veii

limjh1221 said:


> @Veii
> no WHEA is dual ccd related?
> this is dual ccd 5800x.
> 
> from korea.
> View attachment 2513701
> 
> 
> other's post
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 5600x with dual CCD Tuning
> 
> 
> Hey everyone, I couldn't find any discussion on the Ryzen 5600x with the dual CCD's: Ryzen 5 5600X and Ryzen 7 5800X with 2 CCDs spotted, can the CPU be unlocked to Ryzen 9? Just wondering how many people out there that have these unique processors and what sort of performance or overclocking...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> View attachment 2513701


Good overclock 
Yes likely
Can you grab worktool.exe (tool.exe) from this post
And see how much cores are active for you








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Trying out 1.2.0.3 again, so far after several reboots its behaving at 4133/2067. No stability tests as of yet, audio is great, no USB issues yet, waiting for a WHEA 18 🤣😄 ** EDIT ** Back to BCLK I go...... :)




www.overclock.net





For me it jumps between 8-9 cores but AMD locks it down purposely
They randomly wake up
About the question "can it be unlocked"
No information can be given ~ i look for it myself
But i can not comment on it ~ till i find it out myself & information comes from "my own" research. Can not comment on gifted/told information

Microcode reads out the OPN number of the unit, and loads only the APCI values (all cores are awake, just on lowest powerstate)
We need to rewrite OPN number to make it read as 5950X
Both (you and me) are pure 5950X - but some 5600X are 5900X

Only negative issue with Dual CCD 5600/5800X ~ we crash on stock
Voltage to Frequency Curve ~ is borrowed from a 5950X , it misses voltage for X frequency and crashes
It needs positive vcore offset or high Scalar to run stable "on stock"

We also waste 18A EDC and 18A SOC , around 30W waste for nothing ~ cut into the powerbudget
Global C-State generation needs to be enabled, soo other cores idle down and save power. DF-C States needs to be off !
A powerplan with minimum 1-10% state is required to control powerbudget and high EDC limit is too (because we waste a lot of power and lose performance that way)

I see, it's strange but good coincidence
Again, great overclock ! 

We only hard crash, but have no WHEA #19
We can get WHEA #19 rarely and sometimes #18 - but nearly never
(i got WHEA #19 once, and WHEA#18 when i was doing stupid things with CTR)


----------



## KedarWolf

Veii said:


> About DPM , LCLK and similar
> Let me drop you this little tool
> Bios Modding - Google Drive Tool1007.zip (tool.exe)
> 
> Have fun with it
> Single CCD can run
> 
> 
> 
> 
> 
> 
> 
> 
> To override allcore EDC throttle
> You still should set Bios PBO EDC limit higher soo cache can boost up
> But this overrides another stage of allcore throttling
> 
> 
> 
> 
> 
> 
> 
> 
> This is interesting for you , just the plotting is a bit strange to use
> And this is what you surely will like to see
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Enjoy experimenting
> Each of the 8 "Frequency Limiters" Sensors can be the cause of frequency loss
> FIT PPT throttle usually appears because of something else, still searching for the value
> 
> DPM doesn't show up correctly and the ASRock ITX misses LCLK optionality to enable it. The Asus board had it
> Some values are under a wrong multiplier but there are valuable things to check and read out
> Effective Clock is correct for example
> Also it shows fully how many CCDs and Cores you have ~ for all these mysterious samples out there
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Copyright belongs to the ASUS Forums as XOC tool
> I forgot who published it and which team maintains it.
> No credit belong to me, just want to make it easier accessible to people
> 
> Waiting for 1.2.0.3A for the ITX board, then i'm gonna check out what can be done for the public
> 113 Binning value is already good, 118 is fantastic - haven't seen 120+ so far
> 
> 
> 
> 
> 
> 
> 
> 
> 
> DPM 2-1-1-2 doesn't show it
> testing 2-2-1-1 too ~ but this is intercore stuff. SiSoftware Sandra is your best friend for such
> This one is neat, but only ASUS boards let access to RAW VRM controller
> 
> 
> 
> 
> 
> 
> 
> 
> Apparently there should be an I²C port on the ITX , but i haven't checked
> =========================================
> MEM-OC thread, soo here are some valuable RTTs for Rev.E@1.6v or XMP under 56.50
> 
> 
> 
> 
> 
> 
> 
> View attachment 2513725
> 
> I lack a lot of options on the ASRock bioses - but 1203A update needs to be out, before it has any modding potential or consideration
> * on the Drive link above, AMI_FLASH Win can flash unsigned bioses ~ as long as the DeviceID remains identical. It bypasses AMDs SPI lock but is not able to cross-flash bioses
> Backups of it are sector based and tiny ~ do no use it for backup purposes, unless you can stitch bioses together (HEX)


Might be why I can run Curve all 30's except two top cores with 150 Boost and Scaler 6.


----------



## limjh1221

Veii said:


> 좋은 오버 클럭
> 예 가능성이 높습니다.
> 이 게시물에서 .exe(도구.exe)를잡을 수 있습니다.
> 그리고 당신을 위해 얼마나 많은 코어가 활성화되어 있는지 확인하십시오.


Please understand using a translator.


----------



## limjh1221

I ran it on stock.


----------



## 1s1mple

Just posting my Sil Quality like others


----------



## thismock

Veii said:


> MEM-OC thread, soo here are some valuable RTTs for Rev.E@1.6v or XMP under 56.50


@Veii: are you willing to share your AIDA benchmark scores for that tuned Rev.E set?


----------



## PJVol

Veii said:


> DPM doesn't show up correctly and the ASRock ITX misses LCLK optionality to enable it. The Asus board had it
> Some values are under a wrong multiplier but there are valuable things to check and read out
> Effective Clock is correct for example


All monitors are messed with reporting data, I think due to old pm_table version the tool was build with. It just need to be updated for the 380805 and 380905.

As for LCLK DPM's, there's a SetLclkDpmLevelRange command in a first SMN messenger.
The "range" is 24 bit where [24:16] NBIO ID (always 3 for me)
[15-7] - max dpm lvl
[7-0] - min dpm lvl.
Levels are 0-3, though 3 didn't work for me as it corresponds to 770 Mhz (which seem to be not supported in B0, PPR for revision B1), so it stays at max lvl 2 - 593Mhz
1 - 400Mhz
0 - 300Mhz

- Sil quality 117-118 no matter what, so have to agree that metric is suspicious. The result depends on current max boost frequency (may be on fclk a bit) : 112-113 with default setings.

- The AMD tool is interesting nevertheless.

- Sadly SB RMI didn't work for me - hangs application, as well as other "Board functions" (still looking for a way to adjust boost override limit, lol)


----------



## Sleepycat

I still have potato cores though, one of them on CCX1 needs +10 in curve optimiser to pass corecycler.


----------



## CarnageBT

Still hammering away at my testing. Below is where I'm currently at, but I keep getting error 2 / 12. I've been increasing vdimm slowly and re-testing but on my latest run, 1.47vdimm I got error 4. Thoughts?










Vdimm 1.45, tRDWR / tWRRD - 8/3, tWR 105 Cycles, 12, 6, 12, 6 - Low or wrong tWR will cause errors after errors and mostly error on 6&12 for TM5Vdimm 1.45, tWR 114 cycles, 10, 10, 6Vdimm 1.45, tWR 122 cycles, 12, 12, 2,Vdimm 1.46 (settings in picture)3.5 cycles. 12 (best so far, only 1 error)Vdimm 1.472 cycles, 4, 4, 3, 0Vdimm 1.483 cycles, 0, 3, 1, 10, 7, 8Vdimm 1.44testing soonVdimm 1.43testing soonerror 2, voltage - vdimm, vsoc, vddp, vddg ccd / iod. resistance - procODT, rttm DrvStr

If I get more errors on 1.48, it looks like 1.46 was the sweet spot but still had error 12. What do you guys think I should try to change next?


----------



## KedarWolf

Sleepycat said:


> View attachment 2513759
> 
> I still have potato cores though, one of them on CCX1 needs +10 in curve optimiser to pass corecycler.


Two top cores for me, 11-20, rest 30 with 150 Boost, 6 Scaler, passes Core Cycler. My Sil Quality is always above 131 though.

Sorry, meant -11 -20, rest -30.


----------



## Art385

limjh1221 said:


> @Veii
> 
> no WHEA is dual ccd related?
> 
> this is dual ccd 5800x.
> 
> from korea.
> View attachment 2513701
> 
> 
> other's post
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 5600x with dual CCD Tuning
> 
> 
> Hey everyone, I couldn't find any discussion on the Ryzen 5600x with the dual CCD's: Ryzen 5 5600X and Ryzen 7 5800X with 2 CCDs spotted, can the CPU be unlocked to Ryzen 9? Just wondering how many people out there that have these unique processors and what sort of performance or overclocking...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> View attachment 2513701


I doubt it. I can run Tm5 without whea on single ccd 5800x but AIDA64 memory benchmark will generate around 100. Nice overclock


----------



## Dasa

First kit of Patriot 4400c19 did 3771 14-15 1.48v
Second kit needs 1.56v just to boot.
Put the 4x4400c19 sticks together and they wont even post at anything over 2133.
The original 4400c19 worked fine with my 3200c14 except they couldn't run 1T together while 4x8GB of 3200c14 could.
Not what I was expecting.


----------



## Nighthog

Dasa said:


> First kit of Patriot 4400c19 did 3771 14-15 1.48v
> Second kit needs 1.56v just to boot.
> Put the 4x4400c19 sticks together and they wont even post at anything over 2133.
> The original 4400c19 worked fine with my 3200c14 except they couldn't run 1T together while 4x8GB of 3200c14 could.
> Not what I was expecting.


They have the same dram & XMP profiles? Not different manufacturers or different PCB?


----------



## Taraquin

I get a sil-quality of 80 on my semi-golden sample  Seems legit!


----------



## KedarWolf

Art385 said:


> I doubt it. I can run Tm5 without whea on single ccd 5800x but AIDA64 memory benchmark will generate around 100. Nice overclock


I reinstalled Windows about two weeks ago, check my Event Viewer, filtering out for WHEA errors, none at all. Have ran Core Cycler multiple times, AIDA64, 3DMark, even Sisoft Sandra and Linpack Xtreme. Pretty happy with that. 

I've put a ton of work nailing down this memory and CPU overclock.


----------



## Dasa

Nighthog said:


> They have the same dram & XMP profiles? Not different manufacturers or different PCB?


Yep exactly the same just different serial numbers with one kit being 6 months newer.


----------



## mongoled

CarnageBT said:


> Still hammering away at my testing. Below is where I'm currently at, but I keep getting error 2 / 12. I've been increasing vdimm slowly and re-testing but on my latest run, 1.47vdimm I got error 4. Thoughts?
> 
> View attachment 2513762
> 
> 
> Vdimm 1.45, tRDWR / tWRRD - 8/3, tWR 105 Cycles, 12, 6, 12, 6 - Low or wrong tWR will cause errors after errors and mostly error on 6&12 for TM5Vdimm 1.45, tWR 114 cycles, 10, 10, 6Vdimm 1.45, tWR 122 cycles, 12, 12, 2,Vdimm 1.46 (settings in picture)3.5 cycles. 12 (best so far, only 1 error)Vdimm 1.472 cycles, 4, 4, 3, 0Vdimm 1.483 cycles, 0, 3, 1, 10, 7, 8Vdimm 1.44testing soonVdimm 1.43testing soonerror 2, voltage - vdimm, vsoc, vddp, vddg ccd / iod. resistance - procODT, rttm DrvStr
> 
> If I get more errors on 1.48, it looks like 1.46 was the sweet spot but still had error 12. What do you guys think I should try to change next?


Gave you some golden advice as you did not respond to it I can only assume you didnt bother.

Good luck, im out


----------



## mongoled

Dasa said:


> First kit of Patriot 4400c19 did 3771 14-15 1.48v
> Second kit needs 1.56v just to boot.
> Put the 4x4400c19 sticks together and they wont even post at anything over 2133.
> The original 4400c19 worked fine with my 3200c14 except they couldn't run 1T together while 4x8GB of 3200c14 could.
> Not what I was expecting.


So hit and miss, I wonder if the distributors are just recycling people returns .....

Ive tried in total 4 sets of A2s and 2 set of A0s all four sets of A2s were different in what they could do and these were purchased over a year ago.

I really wanted to go for another set to see if I can find another pair that can run the flat 14s but seeing such reports means im not going to bother.



Dasa said:


> Yep exactly the same just different serial numbers with one kit being 6 months newer.


Is the newer kit the bad kit ???


----------



## Taraquin

mongoled said:


> So hit and miss, I wonder if the distributors are just recycling people returns .....
> 
> Ive tried in total 4 sets of A2s and 2 set of A0s all four sets of A2s were different in what they could do and these were purchased over a year ago.
> 
> I really wanted to go for another set to see if I can find another pair that can run the flat 14s but seeing such reports means im not going to bother.
> 
> 
> Is the newer kit the bad kit ???


Dram calc actually has a binning stat if you import profile, seems quite accurate. You can check all your modules and see what % they get? My 4400cl19 got a 94% which is garbage. They can do 3800cl15 2T at 1.45V (1.46-47 actual) and 141ns tRFC. My micron rev E (ballistix 3000cl15) got a score of 102% and they can do 3800cl15 1t gdm off and 535 tRFC (560-600 is more usual) at 1.46V so they are clearly better binned than 4400cl19, but ofcourse a few % slower due to high tRCDRD (20 vs 15), tRC (57 vs 47) and tRFC. 1t, lower tRP (11 vs 15) and tWTRS/L (3/6 vs 4/10) don't make up for that.


----------



## Veii

Taraquin said:


> I get a sil-quality of 80 on my semi-golden sample  Seems legit!


CTR tests under 4375Mhz across an allcore
It tests the voltage response IF the user predefined the loadline and ripple corresponding to "too high switching freq" correctly

My sample started from bronze, to silver ~ which was average, to finally moving in the 1037mV "core crash" range
Gold rating is 1062mV and lower
On one point i learned to adapt to this broken V/F curve chip, but it's also been the powermanagement and generally bios updates ~ which "made it slowly better"
* makes me wonder if silicon burn in is a thing 
EDIT: written nonsense 
But it very likely can be that placed PSP Firmware updates and all the redone attempts to re-balance PM-Table and finetune dLDO
(if finetuning is even possible)
Should surely show some silicon characteristic changes after time/months


On the V/F curve, this are FIT stats
it does run an allcore for a short period of time, but barely to non does push up any Amperage through
It at worst moved +1/-1 value for me ~ doesn't matter if 4.65 "stock" (with fixes), or 4.85 (with -27 or more negative CO [and fixes])
The value remained the same and FIT behaviour unlikely changed at all that drastically.

I'm sorry that you have such a low value, but even when your sample responds well (glad) to undervolting
It might do really bad on peak frequency & why the rating is soo low ~ or loadlines7bios is a mess and you can try to fix it

3xxx samples i saw with the value also drop bellow 100
This here for example is a "to my eyes" very good 14nm unit (1200AF)








4.1 where easy, 4.2 with a bit of overvolting works
Probably need to redo this on my "bad" 1700X which only held 3.8 at worst ~ to see a 60-70ish value
I can trust it, i think i can ~ as it doesn't respond to changes with CO or any boost overrides at all

It does have an interesting feature tho:
@KedarWolf and anyone above 120Q
Can you set 5000Mhz as target & press "get voltage"
This should show you what FIT decided that your sample would need ~ to run this freq on all cores
* Get Max Freq , is then the value to what the sample will drop on an allcore ~ according to FIT rulesets (which you can now override)
Cooler score is foreign to me, and didn't influence the score at all

@PJVol thanks for the LCLK support
It's having a strange pattern that our frankenstein samples have broken LCLK. Either that or a coincidence where we both have locked bioses ^^'
I'll try to override it and see what's up with that. Also continue checking the strange differences between our samples

@limjh1221 Thanks also for the report
Same strange behavior. 9 cores are active, 7 suspended
Zero number core, for you is behaving awkward & always sleeping, maybe a bad core by CPPC rating ?
For our samples, run EDC 400+, and limit heat + voltage by TDC value. 70A looks good, maybe 65A. Lower than 100A
Also run X2 scalar and higher, preferably X6.
X2 scalar with +15mV positive offset (+10mV is fine too) & -3 negative CurveOptimizer ~ works too ,instead of X6

High scalar will increase peak voltage, and it can be that FIT peak voltage throttles back
Utilize Negative "allcore !" CO & optimally run CTR once with high-performance powerplan
CTR will override and remake your core-layout on successful Diagnose.
Strongly recommended now (was buggy before) , to run CTR Diagnose (make it pass) on dual CCD broken/disabled units

CTR changes (core-layout remap) are now permanent changes, but will stick temporary while chipset drivers are installed
Be sure chipset drivers are installed first ~ but use windows high-performance powerplan for the attempt.



thismock said:


> @Veii: are you willing to share your AIDA benchmark scores for that tuned Rev.E set?


Will do when i settle, still fighting with it
Trying to break the tRFC ns wall but first break that tRCDRD 18+ requirement (19+ for 4000)
Consistent Error #4 (PCB Crashes/IC crashes) on 4000MT/s ~ 3800 was easy, 3600 even runs CL13, tCWL 12

Also @PJVol 
Yes, not ready for to the newest SMU
Funnily LCLK also functions on Matisse now with 1203A
The tool.exe has two readouts ~ a global AMD Monitor, and a Vermeer focused monitor
One of both spills correct values ~ both can track the same sensor the same accuracy, just math is wrong and readout sometimes is a messy value

Do not run it with HWInfo or Zentimings open
Too many SMU calls will close the programm in 60-90sec
As standalone it works well.
If it crashes, you can just keep reopening it ~ set values stick till a reboot


----------



## Art385

KedarWolf said:


> I reinstalled Windows about two weeks ago, check my Event Viewer, filtering out for WHEA errors, none at all. Have ran Core Cycler multiple times, AIDA64, 3DMark, even Sisoft Sandra and Linpack Xtreme. Pretty happy with that.
> 
> I've put a ton of work nailing down this memory and CPU overclock.


at IF 2000? That's great. I've managed to cut errors to like 2 on single aida bench test but I was using only 2x8GB not 4x8GB that I use daily. But I'm happy that 1900MHz is working great. 



Dasa said:


> First kit of Patriot 4400c19 did 3771 14-15 1.48v
> Second kit needs 1.56v just to boot.
> Put the 4x4400c19 sticks together and they wont even post at anything over 2133.
> The original 4400c19 worked fine with my 3200c14 except they couldn't run 1T together while 4x8GB of 3200c14 could.
> Not what I was expecting.


It's probably newer set with loose xmp 4266 trc 133 tfaw 40 older was 68/27. This newer set needs active cooling to work with tighter timings in 4x8GB or will overheat even below 1.45v


----------



## Veii

Doublecheck if 4400 are really on A2 PCB
I've seen they push out A0's now , for the remain stock of 4400 units

RTTs will need to match
4 x A2 will be a struggle on Daisy-Chain, nothing can change that ~ and needs 633 RTT to work , likely bit different now since SMU 56.50 / AGESA 1.2.0.0+

A0 PCBs then also require weaker RTT_PARK or they crash/die fully
Voltage as "a value" means nothing to heat 
running RTT_PARK /1 or /5 will result in very low voltage stability ~ only till 1.5v before it changes to negative scalling

All PCB dependent & amount dependent


----------



## Dasa

mongoled said:


> Is the newer kit the bad kit ???


Yes.
The old kits are ~week 6 2021 while the new kit is week 13 2021.



Art385 said:


> It's probably newer set with loose xmp 4266 trc 133 tfaw 40 older was 68/27. This newer set needs active cooling to work with tighter timings in 4x8GB or will overheat even below 1.45v


Actually both are tRC 133 tFAW 40.



Veii said:


> Doublecheck if 4400 are really on A2 PCB
> I've seen they push out A0's now , for the remain stock of 4400 units
> 
> RTTs will need to match
> 4 x A2 will be a struggle on Daisy-Chain, nothing can change that ~ and needs 633 RTT to work , likely bit different now since SMU 56.50 / AGESA 1.2.0.0+
> 
> A0 PCBs then also require weaker RTT_PARK or they crash/die fully
> Voltage as "a value" means nothing to heat
> running RTT_PARK /1 or /5 will result in very low voltage stability ~ only till 1.5v before it changes to negative scalling
> 
> All PCB dependent & amount dependent


Have been running them 34ODT, 633 RTT 40,20,20,20 DrvStr 
Doesn't look like My 3200c14 A1 or like pics of A2 so I guess there all A0?









As for heat room temp is low and airflow is excellent with 1850RPM rad fans blowing up over them and a 2000RPM 90mm fan directly over which was keeping the 3200c14 sticks at ~25-40c.


----------



## Art385

Dasa said:


> Actually both are tRC 133 tFAW 40.
> 
> As for heat room temp is low and airflow is excellent with 1850RPM rad fans blowing up over them and a 2000RPM 90mm fan directly over which was keeping the 3200c14 sticks at ~25-40c.


So they are even worse now  Shame. First kit I bought back in 2019 was great . So I bought another kit last year and it was not so great. Though for the price it's still pretty good deal.


----------



## ManniX-ITA

PJVol said:


> - Sil quality 117-118 no matter what, so have to agree that metric is suspicious. The result depends on current max boost frequency (may be on fclk a bit) : 112-113 with default setings.


Yesterday I have realized that maybe it's just the average for the CPPC tags... isn't it?
Which is indeed an unreliable metric.



Veii said:


> Can you set 5000Mhz as target & press "get voltage"
> This should show you what FIT decided that your sample would need ~ to run this freq on all cores


Seems about right:


----------



## mongoled

Can anyone with 5600x confirm what their VID limit is.

Mine is 1.45v and now it makes sense why I cant do certain things .....


----------



## ManniX-ITA

jomama22 said:


> I'll be that guy for a moment.
> 
> Better for what? Aside from internal mux's being at half speed and some timings needing to be even, what quantifiable benefit does it provide?
> 
> I always see this claimed without any sort of actual metric used to show a benefit one way or the other. Timings for both would have to be the exact same as well for it to be a 'fair fight" and it seems most cannot keep their same timings when moving to 2t from gdm.
> 
> And I DONT mean aida latency differences lol





domdtxdissar said:


> I did the testing like 100 pages back, but ever since then, "i hate aida64" according to some.





jomama22 said:


> Beyond this, no one has posted a single thing, just requoting 2t being better than gdm until it became a fact without any real metric basis.


I think you are wrong; SOTR is not exactly the best thing to show the differences between GDM and 2T.
Just like for FCLK you need to use something which is extremely dependent on memory speed and latency; the monero miner.

The difference is very thin and unless you are really into "get the best from your expensive kit" it's probably not worth to spend all this time to find and stabilize the perfect 2T profile.
But in absolute 2T is faster than GDM and that's why we all look for it here.

GDM will let you forget a lot of problems and get very good performances. But not the best.
@Veii shamed me and many others multiple times with much better 2T profiles with apparently worst timings 

I'm still working on this 2T profile and still half sucks.
What is very good about GDM is that you can use it iteratively to improve the 2T profile.
Unless of course you are aiming for odd timings.
Once you are at or better the AIDA benchmark for GDM then you are close to a better 2T profile.
And it works also for the opposite; GDM is masking issues, when you'll have a better 2T profile that will work as well as a better GDM profile.

*2T*
















*1T GDM*
















GDM still has a very small lead in bandwidth but it's a loser in latency with an average at 53.2ns.
The 2T profile has an edge with a 53.1ns average dropping often to 53.0ns.
But AIDA sucks and you all hate it, so let's see the miner 

You need to run the miner all core to maximize the memory usage.

xmr-stak-rx at 2T, average after 15m: *18550.8 H/s*










xmr-stak-rx at GDM, average after 15m: *18353.5 H/s*










Since today is again very hot and the ambient temperature always rising, I've run it again at 2T.

xmr-stak-rx at 2T, average after 15m: *18532.7 H/s*










The difference is a very sizeable 150-200 H/s.
And that's with an un-optimized 2T profile, someone better than me at it can get better gains.

For a miner is not a small difference, almost 6 billions more hashes per year 

For a gamer probably doesn't matter, ever.
But for an overclocker is climbing the Everest and reaching the peak 



jomama22 said:


> The crappy part about sottr is it's inconsistencies run to run. I'm genuinely surprised reviewers use it as a comparison outside of having some range to average. Pure maximum result seems to be somewhat ok to use but even then it's a 'stars align' type deal.


I don't have inconsistencies with SOTR, at all. It's probably the most repeatable in-game benchmark ever...
It depends a lot on the CPU and GPU temperature (even when not GPU bound) but if there's no change there then the results are consistent.
Max fps are expected to have quite some variance, but all the other metrics are always in 1-4 fps margin for me.
Otherwise something is off with your settings; it did uncover for me in the past issues with too high/too low CCD/IOD/SOC voltages.


----------



## ManniX-ITA

Veii said:


> * Get Max Freq , is then the value to what the sample will drop on an allcore ~ according to FIT rulesets (which you can now override)
> Cooler score is foreign to me, and didn't influence the score at all


Yes it does 
I wonder how to quantify this cooler score...










Maybe 163 is the AMD stock cooler?
We should find out what's the score for an AIO or a custom loop...

Works also for Get Max Freq:


----------



## XPEHOPE3

Hello! Is there a specific guide on how to make overclock of 4 sticks of 16Gb stable? Or maybe a guide which timings to tighten in which order?

I have B-dies which won't test good @ 3800CL14 (F4-3200C14Q-64GVK @ 5600X and B500 Aorus Pro V2)









I test with TestMem5 anta777 extreme, failing tests are 9, 15, 11, 14, 10, 3 (the ones which are SimpleTest with Pattern mode 1 or 2). They fail even when only them are in a test sequence.
Temps while testing are 44-45.8 (Noctua A14 900RPM blowing directly at RAM).
Some other benchmarks pass though (like xmrig benchmark 1M or Linpack Xtreme benchmark 8G).

I could run the memory stable with 3600-14-14-14-14-34 and 3800-16-16-16-16-34. That 3800-16 config passed TM5 anta777 extreme with DRAM temps of 48,53,53,51 even without cooling. Does it mean the 46-ish temps are Ok for tighter timings??

3866-1933 won't get me to Windows (at least with VDIMM 1.5V and ProcODT Auto (48 Ohm)).
3800CL14 will only boot to Windows with 1.52 DIMM if ProcODT is on auto (meaning 48 Ohm). At VDIMM 1.55V Lowering ProcODT to 40 Ohm or 34.3 would lower(!) number of errors. With ProcODT values in between of 34.3-40-48 I can't boot to Windows.


----------



## Veii

ManniX-ITA said:


> GDM will let you forget a lot of problems and get very good performances. But not the best.
> @Veii shamed me and many others multiple times with much better 2T profiles with apparently worst timings


Tiny bit, just mocking ~ with good intention

Working on a GDM on profile, leads to nothing
A waste of time - because also tRFC will be "fake" and lower than in reality the dimms are capable off
Powering will be fake, as it requires less ~ but yes it's fast & i've tested it well between 16-16-16 and 14-14-14 

It took a  lot of time and 1.6v for my DIMMs to run the flat 14-14-14 set under 1T
Double that time to better up RTTs soo 4000 14-14-14 runs ~ probably tripple
Soo we reach 50hours of testing at least. 
And for what ~ only because i focused soo much on GDM ~ to not see how bad powering was to begin with

GDM and 2T need the same VDIMM
This is important !

But 2T will not work if your powering is bad
The gain for all that, is magically subtle more perf ~ without you actually doing anything to better up your timings
I think the payment and "value" you get once to fix your mess & issues ~ is worth enough the hassle
But staying on GDM makes you live and go around potential powering issues ~ which you surely have 
(else you wouldn't stay on GDM after all)

The work to get it to run is worth it,
1, if you ever want to play with odd timings, 
or 2, just so you can keep improving and working towards 1T @ the same timings
* not adjusting timings lower "just to run 1T"
As 1T is not the goal , but your "apparently great timings" under 1T without loops to mask issues


----------



## mongoled

@XPEHOPE3

You have sticks rated for 3200 mhz and you are trying to run them @3800 mhz with the tightest timings and you expect them to work!

You should start your way from a lower frquency get a stable set then move up!

Very very very very (one more) very few people have 32GB running 3800 flat 14s nevermind running 64GB

Where has the common sense gone from this World ....

Take RTT Park off RZQ/1 and move it to RZQ/3 before you end up destroying those modules.

Also ClkDrvStr may well be needed to increase to 120 ohms ..


----------



## XPEHOPE3

mongoled said:


> Very very very very (one more) very few people have 32GB running 3800 flat 14s nevermind running 64GB


That's why I'm asking for a guide! As I OC memory for the first time, I only came across this one, but it lacks info on 16Gb sticks.
Thanks for your response, will test it.

I only go for 3800-14 because there are rare reports of such setup working with Samsung B-dies (even binned 3200CL14 like mine). Also I see it pass some tests so that gave me (unnecessary) hopes


----------



## domdtxdissar

ManniX-ITA said:


> Just like for FCLK you need to use something which is extremely dependent on memory speed and latency; the monero miner.


Is there a guide anywhere how to benchmark with this miner ?
Thought i could try T1 GDM-off vs T1 GDM-on vs T2


----------



## ManniX-ITA

domdtxdissar said:


> Is there a guide anywhere how to benchmark with this miner ?
> Thought i could try T1 GDM-off vs T1 GDM-on vs T2


Can tell you what I did.

Downloaded the Windows binary from:









Releases · fireice-uk/xmr-stak


Free Monero RandomX Miner and unified CryptoNight miner - fireice-uk/xmr-stak




github.com





Not sure if it needs a real monero wallet but I did create one on my phone with Cake Wallet app.

In the pools.txt I have:



Code:


"pool_list" :
[
    {"pool_address" : "xmr-eu1.nanopool.org:14433", "wallet_address" : "aAa6aB1CzZsDXgGRedqiG8FcHcSYzUw8QDaSs2hs48CG2KhaETseL8iGNtc4DjJ1nb1C1QuELn1TUpEkd54RZaoVnGi5,YourRIGname/[email protected]", "rig_id" : "", "pool_password" : "", "use_nicehash" : false, "use_tls" : true, "tls_fingerprint" : "", "pool_weight" : 1 },
],

"currency" : "randomx",

The wallet address is a fake and you should replace YourRIGname and [email protected].
Maybe works also like this not sure.
Testing for 15 minutes at a time doesn't make any money sadly 

If you start it will create the config and also use the GPU but I guess you can directly configure the cpu and nvidia configuration files.

In nvidia.txt just a few lines to disable the GPU:



Code:


"gpu_threads_conf" :
null,

In cpu.txt I have in the comments 3 sets of threads for different tests:



Code:


// generated by xmr-stak-rx/1.0.4-rx/65ade74b9/xmr-stak-rx/win/nvidia-amd-cpu

/*
 * Thread configuration for each thread. Make sure it matches the number above.
 * low_power_mode - This can either be a boolean (true or false), or a number between 1 to 5. When set to true,
 *                  this mode will double the cache usage, and double the single thread performance. It will
 *                  consume much less power (as less cores are working), but will max out at around 80-85% of
 *                  the maximum performance. When set to a number N greater than 1, this mode will increase the
 *                  cache usage and single thread performance by N times.
 *
 * affine_to_cpu  - This can be either false (no affinity), or the CPU core number. Note that on hyperthreading
 *                  systems it is better to assign threads to physical cores. On Windows this usually means selecting
 *                  even or odd numbered cpu numbers. For Linux it will be usually the lower CPU numbers, so for a 4
 *                  physical core CPU you should select cpu numbers 0-3.
 *
 * On the first run the miner will look at your system and suggest a basic configuration that will work,
 * you can try to tweak it from there to get the best performance.
 *
 * A filled out configuration should look like this:
 * "cpu_threads_conf" :
 * [
 *      { "low_power_mode" : false, "affine_to_cpu" : 0 },
 *      { "low_power_mode" : false, "affine_to_cpu" : 1 },
 * ],
 * If you do not wish to mine with your CPU(s) then use:
 * "cpu_threads_conf" :
 * null,

    { "low_power_mode" : false, "affine_to_cpu" : 0 },
    { "low_power_mode" : false, "affine_to_cpu" : 2 },
    { "low_power_mode" : false, "affine_to_cpu" : 4 },
    { "low_power_mode" : false, "affine_to_cpu" : 6 },
    { "low_power_mode" : false, "affine_to_cpu" : 8 },
    { "low_power_mode" : false, "affine_to_cpu" : 10 },
    { "low_power_mode" : false, "affine_to_cpu" : 12 },
    { "low_power_mode" : false, "affine_to_cpu" : 14 },
    { "low_power_mode" : false, "affine_to_cpu" : 1 },
    { "low_power_mode" : false, "affine_to_cpu" : 3 },
    { "low_power_mode" : false, "affine_to_cpu" : 5 },
    { "low_power_mode" : false, "affine_to_cpu" : 7 },
    { "low_power_mode" : false, "affine_to_cpu" : 9 },
    { "low_power_mode" : false, "affine_to_cpu" : 11 },
    { "low_power_mode" : false, "affine_to_cpu" : 13 },
    { "low_power_mode" : false, "affine_to_cpu" : 15 },
    { "low_power_mode" : false, "affine_to_cpu" : 16 },
    { "low_power_mode" : false, "affine_to_cpu" : 18 },
    { "low_power_mode" : false, "affine_to_cpu" : 20 },
    { "low_power_mode" : false, "affine_to_cpu" : 22 },
    { "low_power_mode" : false, "affine_to_cpu" : 24 },
    { "low_power_mode" : false, "affine_to_cpu" : 26 },
    { "low_power_mode" : false, "affine_to_cpu" : 28 },
    { "low_power_mode" : false, "affine_to_cpu" : 30 },
    { "low_power_mode" : false, "affine_to_cpu" : 17 },
    { "low_power_mode" : false, "affine_to_cpu" : 19 },
    { "low_power_mode" : false, "affine_to_cpu" : 21 },
    { "low_power_mode" : false, "affine_to_cpu" : 23 },
    { "low_power_mode" : false, "affine_to_cpu" : 25 },
    { "low_power_mode" : false, "affine_to_cpu" : 27 },
    { "low_power_mode" : false, "affine_to_cpu" : 29 },
    { "low_power_mode" : false, "affine_to_cpu" : 31 },

    { "low_power_mode" : false, "affine_to_cpu" : 2 },
    { "low_power_mode" : false, "affine_to_cpu" : 4 },
    { "low_power_mode" : false, "affine_to_cpu" : 6 },
    { "low_power_mode" : false, "affine_to_cpu" : 8 },
    { "low_power_mode" : false, "affine_to_cpu" : 10 },
    { "low_power_mode" : false, "affine_to_cpu" : 12 },
    { "low_power_mode" : false, "affine_to_cpu" : 3 },
    { "low_power_mode" : false, "affine_to_cpu" : 5 },
    { "low_power_mode" : false, "affine_to_cpu" : 7 },
    { "low_power_mode" : false, "affine_to_cpu" : 9 },
    { "low_power_mode" : false, "affine_to_cpu" : 11 },
    { "low_power_mode" : false, "affine_to_cpu" : 13 },
    { "low_power_mode" : false, "affine_to_cpu" : 16 },
    { "low_power_mode" : false, "affine_to_cpu" : 18 },
    { "low_power_mode" : false, "affine_to_cpu" : 20 },
    { "low_power_mode" : false, "affine_to_cpu" : 22 },
    { "low_power_mode" : false, "affine_to_cpu" : 24 },
    { "low_power_mode" : false, "affine_to_cpu" : 26 },
    { "low_power_mode" : false, "affine_to_cpu" : 17 },
    { "low_power_mode" : false, "affine_to_cpu" : 19 },
    { "low_power_mode" : false, "affine_to_cpu" : 21 },
    { "low_power_mode" : false, "affine_to_cpu" : 23 },
    { "low_power_mode" : false, "affine_to_cpu" : 25 },
    { "low_power_mode" : false, "affine_to_cpu" : 27 },

    { "low_power_mode" : false, "affine_to_cpu" : 2 },
    { "low_power_mode" : false, "affine_to_cpu" : 4 },
    { "low_power_mode" : false, "affine_to_cpu" : 6 },
    { "low_power_mode" : false, "affine_to_cpu" : 8 },
    { "low_power_mode" : false, "affine_to_cpu" : 3 },
    { "low_power_mode" : false, "affine_to_cpu" : 5 },
    { "low_power_mode" : false, "affine_to_cpu" : 7 },
    { "low_power_mode" : false, "affine_to_cpu" : 9 },
    { "low_power_mode" : false, "affine_to_cpu" : 16 },
    { "low_power_mode" : false, "affine_to_cpu" : 18 },
    { "low_power_mode" : false, "affine_to_cpu" : 20 },
    { "low_power_mode" : false, "affine_to_cpu" : 22 },
    { "low_power_mode" : false, "affine_to_cpu" : 17 },
    { "low_power_mode" : false, "affine_to_cpu" : 19 },
    { "low_power_mode" : false, "affine_to_cpu" : 21 },
    { "low_power_mode" : false, "affine_to_cpu" : 23 },


 */

"cpu_threads_conf" :
[
    { "low_power_mode" : false, "affine_to_cpu" : 0 },
    { "low_power_mode" : false, "affine_to_cpu" : 2 },
    { "low_power_mode" : false, "affine_to_cpu" : 4 },
    { "low_power_mode" : false, "affine_to_cpu" : 6 },
    { "low_power_mode" : false, "affine_to_cpu" : 8 },
    { "low_power_mode" : false, "affine_to_cpu" : 10 },
    { "low_power_mode" : false, "affine_to_cpu" : 12 },
    { "low_power_mode" : false, "affine_to_cpu" : 14 },
    { "low_power_mode" : false, "affine_to_cpu" : 1 },
    { "low_power_mode" : false, "affine_to_cpu" : 3 },
    { "low_power_mode" : false, "affine_to_cpu" : 5 },
    { "low_power_mode" : false, "affine_to_cpu" : 7 },
    { "low_power_mode" : false, "affine_to_cpu" : 9 },
    { "low_power_mode" : false, "affine_to_cpu" : 11 },
    { "low_power_mode" : false, "affine_to_cpu" : 13 },
    { "low_power_mode" : false, "affine_to_cpu" : 15 },
    { "low_power_mode" : false, "affine_to_cpu" : 16 },
    { "low_power_mode" : false, "affine_to_cpu" : 18 },
    { "low_power_mode" : false, "affine_to_cpu" : 20 },
    { "low_power_mode" : false, "affine_to_cpu" : 22 },
    { "low_power_mode" : false, "affine_to_cpu" : 24 },
    { "low_power_mode" : false, "affine_to_cpu" : 26 },
    { "low_power_mode" : false, "affine_to_cpu" : 28 },
    { "low_power_mode" : false, "affine_to_cpu" : 30 },
    { "low_power_mode" : false, "affine_to_cpu" : 17 },
    { "low_power_mode" : false, "affine_to_cpu" : 19 },
    { "low_power_mode" : false, "affine_to_cpu" : 21 },
    { "low_power_mode" : false, "affine_to_cpu" : 23 },
    { "low_power_mode" : false, "affine_to_cpu" : 25 },
    { "low_power_mode" : false, "affine_to_cpu" : 27 },
    { "low_power_mode" : false, "affine_to_cpu" : 29 },
    { "low_power_mode" : false, "affine_to_cpu" : 31 },
],


----------



## 1s1mple

mongoled said:


> Can anyone with 5600x confirm what their VID limit is.
> 
> Mine is 1.45v and now it makes sense why I cant do certain things .....


Heres mines


----------



## ManniX-ITA

1s1mple said:


> Heres mines


The VID Limit is in AMD monitor.
I'd like to know what is set for a 5800x....


----------



## 1s1mple

For my 5600x


----------



## domdtxdissar

ManniX-ITA said:


> Can tell you what I did.
> 
> Downloaded the Windows binary from:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Releases · fireice-uk/xmr-stak
> 
> 
> Free Monero RandomX Miner and unified CryptoNight miner - fireice-uk/xmr-stak
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> Not sure if it needs a real monero wallet but I did create one on my phone with Cake Wallet app.
> 
> In the pools.txt I have:
> 
> 
> 
> Code:
> 
> 
> "pool_list" :
> [
> {"pool_address" : "xmr-eu1.nanopool.org:14433", "wallet_address" : "aAa6aB1CzZsDXgGRedqiG8FcHcSYzUw8QDaSs2hs48CG2KhaETseL8iGNtc4DjJ1nb1C1QuELn1TUpEkd54RZaoVnGi5,YourRIGname/[email protected]", "rig_id" : "", "pool_password" : "", "use_nicehash" : false, "use_tls" : true, "tls_fingerprint" : "", "pool_weight" : 1 },
> ],
> 
> "currency" : "randomx",
> 
> The wallet address is a fake and you should replace YourRIGname and [email protected].
> Maybe works also like this not sure.
> Testing for 15 minutes at a time doesn't make any money sadly
> 
> If you start it will create the config and also use the GPU but I guess you can directly configure the cpu and nvidia configuration files.
> 
> In nvidia.txt just a few lines to disable the GPU:
> 
> 
> 
> Code:
> 
> 
> "gpu_threads_conf" :
> null,
> 
> In cpu.txt I have in the comments 3 sets of threads for different tests:
> 
> 
> 
> Code:
> 
> 
> // generated by xmr-stak-rx/1.0.4-rx/65ade74b9/xmr-stak-rx/win/nvidia-amd-cpu
> 
> /*
> * Thread configuration for each thread. Make sure it matches the number above.
> * low_power_mode - This can either be a boolean (true or false), or a number between 1 to 5. When set to true,
> *                  this mode will double the cache usage, and double the single thread performance. It will
> *                  consume much less power (as less cores are working), but will max out at around 80-85% of
> *                  the maximum performance. When set to a number N greater than 1, this mode will increase the
> *                  cache usage and single thread performance by N times.
> *
> * affine_to_cpu  - This can be either false (no affinity), or the CPU core number. Note that on hyperthreading
> *                  systems it is better to assign threads to physical cores. On Windows this usually means selecting
> *                  even or odd numbered cpu numbers. For Linux it will be usually the lower CPU numbers, so for a 4
> *                  physical core CPU you should select cpu numbers 0-3.
> *
> * On the first run the miner will look at your system and suggest a basic configuration that will work,
> * you can try to tweak it from there to get the best performance.
> *
> * A filled out configuration should look like this:
> * "cpu_threads_conf" :
> * [
> *      { "low_power_mode" : false, "affine_to_cpu" : 0 },
> *      { "low_power_mode" : false, "affine_to_cpu" : 1 },
> * ],
> * If you do not wish to mine with your CPU(s) then use:
> * "cpu_threads_conf" :
> * null,
> 
> { "low_power_mode" : false, "affine_to_cpu" : 0 },
> { "low_power_mode" : false, "affine_to_cpu" : 2 },
> { "low_power_mode" : false, "affine_to_cpu" : 4 },
> { "low_power_mode" : false, "affine_to_cpu" : 6 },
> { "low_power_mode" : false, "affine_to_cpu" : 8 },
> { "low_power_mode" : false, "affine_to_cpu" : 10 },
> { "low_power_mode" : false, "affine_to_cpu" : 12 },
> { "low_power_mode" : false, "affine_to_cpu" : 14 },
> { "low_power_mode" : false, "affine_to_cpu" : 1 },
> { "low_power_mode" : false, "affine_to_cpu" : 3 },
> { "low_power_mode" : false, "affine_to_cpu" : 5 },
> { "low_power_mode" : false, "affine_to_cpu" : 7 },
> { "low_power_mode" : false, "affine_to_cpu" : 9 },
> { "low_power_mode" : false, "affine_to_cpu" : 11 },
> { "low_power_mode" : false, "affine_to_cpu" : 13 },
> { "low_power_mode" : false, "affine_to_cpu" : 15 },
> { "low_power_mode" : false, "affine_to_cpu" : 16 },
> { "low_power_mode" : false, "affine_to_cpu" : 18 },
> { "low_power_mode" : false, "affine_to_cpu" : 20 },
> { "low_power_mode" : false, "affine_to_cpu" : 22 },
> { "low_power_mode" : false, "affine_to_cpu" : 24 },
> { "low_power_mode" : false, "affine_to_cpu" : 26 },
> { "low_power_mode" : false, "affine_to_cpu" : 28 },
> { "low_power_mode" : false, "affine_to_cpu" : 30 },
> { "low_power_mode" : false, "affine_to_cpu" : 17 },
> { "low_power_mode" : false, "affine_to_cpu" : 19 },
> { "low_power_mode" : false, "affine_to_cpu" : 21 },
> { "low_power_mode" : false, "affine_to_cpu" : 23 },
> { "low_power_mode" : false, "affine_to_cpu" : 25 },
> { "low_power_mode" : false, "affine_to_cpu" : 27 },
> { "low_power_mode" : false, "affine_to_cpu" : 29 },
> { "low_power_mode" : false, "affine_to_cpu" : 31 },
> 
> { "low_power_mode" : false, "affine_to_cpu" : 2 },
> { "low_power_mode" : false, "affine_to_cpu" : 4 },
> { "low_power_mode" : false, "affine_to_cpu" : 6 },
> { "low_power_mode" : false, "affine_to_cpu" : 8 },
> { "low_power_mode" : false, "affine_to_cpu" : 10 },
> { "low_power_mode" : false, "affine_to_cpu" : 12 },
> { "low_power_mode" : false, "affine_to_cpu" : 3 },
> { "low_power_mode" : false, "affine_to_cpu" : 5 },
> { "low_power_mode" : false, "affine_to_cpu" : 7 },
> { "low_power_mode" : false, "affine_to_cpu" : 9 },
> { "low_power_mode" : false, "affine_to_cpu" : 11 },
> { "low_power_mode" : false, "affine_to_cpu" : 13 },
> { "low_power_mode" : false, "affine_to_cpu" : 16 },
> { "low_power_mode" : false, "affine_to_cpu" : 18 },
> { "low_power_mode" : false, "affine_to_cpu" : 20 },
> { "low_power_mode" : false, "affine_to_cpu" : 22 },
> { "low_power_mode" : false, "affine_to_cpu" : 24 },
> { "low_power_mode" : false, "affine_to_cpu" : 26 },
> { "low_power_mode" : false, "affine_to_cpu" : 17 },
> { "low_power_mode" : false, "affine_to_cpu" : 19 },
> { "low_power_mode" : false, "affine_to_cpu" : 21 },
> { "low_power_mode" : false, "affine_to_cpu" : 23 },
> { "low_power_mode" : false, "affine_to_cpu" : 25 },
> { "low_power_mode" : false, "affine_to_cpu" : 27 },
> 
> { "low_power_mode" : false, "affine_to_cpu" : 2 },
> { "low_power_mode" : false, "affine_to_cpu" : 4 },
> { "low_power_mode" : false, "affine_to_cpu" : 6 },
> { "low_power_mode" : false, "affine_to_cpu" : 8 },
> { "low_power_mode" : false, "affine_to_cpu" : 3 },
> { "low_power_mode" : false, "affine_to_cpu" : 5 },
> { "low_power_mode" : false, "affine_to_cpu" : 7 },
> { "low_power_mode" : false, "affine_to_cpu" : 9 },
> { "low_power_mode" : false, "affine_to_cpu" : 16 },
> { "low_power_mode" : false, "affine_to_cpu" : 18 },
> { "low_power_mode" : false, "affine_to_cpu" : 20 },
> { "low_power_mode" : false, "affine_to_cpu" : 22 },
> { "low_power_mode" : false, "affine_to_cpu" : 17 },
> { "low_power_mode" : false, "affine_to_cpu" : 19 },
> { "low_power_mode" : false, "affine_to_cpu" : 21 },
> { "low_power_mode" : false, "affine_to_cpu" : 23 },
> 
> 
> */
> 
> "cpu_threads_conf" :
> [
> { "low_power_mode" : false, "affine_to_cpu" : 0 },
> { "low_power_mode" : false, "affine_to_cpu" : 2 },
> { "low_power_mode" : false, "affine_to_cpu" : 4 },
> { "low_power_mode" : false, "affine_to_cpu" : 6 },
> { "low_power_mode" : false, "affine_to_cpu" : 8 },
> { "low_power_mode" : false, "affine_to_cpu" : 10 },
> { "low_power_mode" : false, "affine_to_cpu" : 12 },
> { "low_power_mode" : false, "affine_to_cpu" : 14 },
> { "low_power_mode" : false, "affine_to_cpu" : 1 },
> { "low_power_mode" : false, "affine_to_cpu" : 3 },
> { "low_power_mode" : false, "affine_to_cpu" : 5 },
> { "low_power_mode" : false, "affine_to_cpu" : 7 },
> { "low_power_mode" : false, "affine_to_cpu" : 9 },
> { "low_power_mode" : false, "affine_to_cpu" : 11 },
> { "low_power_mode" : false, "affine_to_cpu" : 13 },
> { "low_power_mode" : false, "affine_to_cpu" : 15 },
> { "low_power_mode" : false, "affine_to_cpu" : 16 },
> { "low_power_mode" : false, "affine_to_cpu" : 18 },
> { "low_power_mode" : false, "affine_to_cpu" : 20 },
> { "low_power_mode" : false, "affine_to_cpu" : 22 },
> { "low_power_mode" : false, "affine_to_cpu" : 24 },
> { "low_power_mode" : false, "affine_to_cpu" : 26 },
> { "low_power_mode" : false, "affine_to_cpu" : 28 },
> { "low_power_mode" : false, "affine_to_cpu" : 30 },
> { "low_power_mode" : false, "affine_to_cpu" : 17 },
> { "low_power_mode" : false, "affine_to_cpu" : 19 },
> { "low_power_mode" : false, "affine_to_cpu" : 21 },
> { "low_power_mode" : false, "affine_to_cpu" : 23 },
> { "low_power_mode" : false, "affine_to_cpu" : 25 },
> { "low_power_mode" : false, "affine_to_cpu" : 27 },
> { "low_power_mode" : false, "affine_to_cpu" : 29 },
> { "low_power_mode" : false, "affine_to_cpu" : 31 },
> ],


So far so good, but didnt get any GPU cfg file and no "score output" (?)








_edit_
Nevermind, i just needed to click "H" 
Thanks for the help ManniX-ITA


----------



## mongoled

1s1mple said:


> For my 5600x
> 
> View attachment 2513802


Thanks, also 1.45v ...


----------



## PJVol

ManniX-ITA said:


> We should find out what's the score for an AIO or a custom loop...


You know, the funny thing is your (seeminly randomly choosen) 300 megapoints-cooler value almost perfectly fit my 4800 and 4850 static OC profiles  1.276 and 1.301 (taking Vdroop into account) so you may consider then 300 for the Al-made LC ))


----------



## Veii

ManniX-ITA said:


> I'd like to know what is set for a 5800x....













mongoled said:


> Mine is 1.45v and now it makes sense why I cant do certain things .....
> 
> 
> mongoled said:
> 
> 
> 
> So they are gimping the 5600x even if they are capable of higher frequencies ...
Click to expand...










ProcHot gimping


----------



## mongoled

So they are gimping the 5600x even if they are capable of higher frequencies ...


----------



## T[]RK

Veii said:


> Can you set 5000Mhz as target & press "get voltage"
> This should show you what FIT decided that your sample would need ~ to run this freq on all cores











No-no-no... =)


----------



## mongoled

T[]RK said:


> View attachment 2513806
> 
> No-no-no... =)


🤣😂🤣

You must get silicon quality first


----------



## domdtxdissar

Dont know how useful this rating is as both PBO and CTR together with cooler score affect the given rating.. But here is mine:









Ill try to do the comparison of T1 GDM vs T2 vs T1 later tonight


----------



## mongoled

PJVol said:


> You know, the funny thing is your (seeminly randomly choosen) 300 megapoints-cooler value almost perfectly fit my 4800 and 4850 static OC profiles  1.276 and 1.301 (taking Vdroop into account) so you may consider then 300 for the Al-made LC ))


I know what my CPU requires for 4.6Ghz static all core overclock when using AVX2 and that is 1.313v.

So when I set cooler to 0 guess what I get










😂😂😂


----------



## Veii

Pretty consistent for my run , also shows that you have to use that cooler score
whatever it really means 








zA9aeYyA3b.mp4


Watch "zA9aeYyA3b.mp4" on Streamable.




streamable.com


----------



## CarnageBT

mongoled said:


> Gave you some golden advice as you did not respond to it I can only assume you didnt bother.
> 
> Good luck, im out


Damn it man! Why do you have to always have to be right?

I tested all 4 dimms individually (in dimm slot A2 per mobo instructions for 1 dimm setup).


dimm115 cycles, 49m, no errorsdimm212 cycles, 35m, no errorsdimm317 cycles, 52m, no errorsdimm46 cycles, 18 mins, error 6, 6, 12, 6, 10, 10

Settings used:


----------



## T[]RK

mongoled said:


> You must get silicon quality first


Yeah, that's better. More like "On the edge".


----------



## CarnageBT

@mongoled this dim used to be in slot b2. a2/b2 are preferred to a1/b1 right? So it was already in the slot giving it, it's best chance? or is there a better slot for a weaker dimm? 

@Veii I think mongoled has solved the problem

What is the next step now? Test the best settings for this weakest dimm, then apply that to all?


----------



## ManniX-ITA

PJVol said:


> You know, the funny thing is your (seeminly randomly choosen) 300 megapoints-cooler value almost perfectly fit my 4800 and 4850 static OC profiles  1.276 and 1.301 (taking Vdroop into account) so you may consider then 300 for the Al-made LC ))


ahahah was absolutely random


----------



## PJVol

Veii said:


> also shows that you have to use that cooler score


To be serious, that didn't make much sense. At the default 163, it wants me to set 1.35 VID for the 4800, ... WHAT ? 
It looks more like max FIT voltage for that freq, not the min required. Just curious, what current it needs as well.


----------



## ManniX-ITA

domdtxdissar said:


> Nevermind, i just needed to click "H"
> Thanks for the help ManniX-ITA


Ooops that I forgot 
there's also nice to know, it does say at start, --noTest to skip the test at boot which is useless
Let's see if you can replicate my results, very curious!


----------



## Veii

CarnageBT said:


> @Veii I think mongoled has solved the problem


He is right, i never used this method - as RTTs for single dimms are different than dual dimms
Read your PM - i accept, but been recently busy too with people's system 7-8h, nearly every night one. Farminng to pay my rent for this month

That's currently my Agony 








Same nonsense after 56.50 i had with the B-Dies - the tFAW dillema 
Too low and you have a spam of 0's & 6's,
using tCCD_L as anchor for i, works but this 4 PCB crash is more than annoying

Redid them fully and these bizzare RTTs work well from 1.6-1.65v
But #4 can also be tRRD_ to tWTR
It's majorly annoying ~ tho i remember i bruteforced lower tRCD too on my A0's ~ soo it certainly is possible
What will instantly run is tRCDRD 19 here, but that's not acceptable 
===========================
Soo probably for you as a next step
Bruteforce it with 2 dimms
find the ones which run at the lowest voltage for 14-14-14
Then pair the "bad" one with the next worse one

Work on bruteforcing it with correct RTTs and higher tRRD_ and tWTR_ *
* see profile upload for an example how
Copy that awkward SD,DD 

After you finally got it to run
Leave the worst ones where they are and just put the best ones in
Double tWR , double tRTP 
drop all of the SD, DDs by 1 and they should be stable


----------



## mongoled

CarnageBT said:


> @mongoled this dim used to be in slot b2. a2/b2 are preferred to a1/b1 right? So it was already in the slot giving it, it's best chance? or is there a better slot for a weaker dimm?
> 
> @Veii I think mongoled has solved the problem
> 
> What is the next step now? Test the best settings for this weakest dimm, then apply that to all?


Glad you've come around 

😁

Yeah, get the bad stick stable at the tightest timings, highest frequency possible as that is unfortunately going to be your bottleneck. 

No way around it other then buying more sets and binning them. 

It's not that I'm "always right" it's just that I "suffered" to be in a position to be right more times than I'm wrong

😁


----------



## CarnageBT

mongoled said:


> Glad you've come around
> 
> 😁
> 
> Yeah, get the bad stick stable at the tightest timings, highest frequency possible as that is unfortunately going to be your bottleneck.
> 
> No way around it other then buying more sets and binning them.
> 
> It's not that I'm "always right" it's just that I "suffered" to be in a position to be right more times than I'm wrong
> 
> 😁


Should I just work at 3733? or go for 3800? My goal is 1080p, 240+ fps gaming, so memory & CPU speed matters. I noticed that I had to drop a few of my curve offsets when moving from 3733 to 3800 (but 3733 worked with the same curve as 3600 stock IF), I assume because the IMC and memory are eating into my available voltage. 

Thoughts? Unless you think 3800 will provide a large boost, I think I rather just fix the "easier" 3733 as I've spent far too many hours (its coming on 2 wks now - just memory) on this and my wife will soon disown me... or pour water on the new computer lol.


----------



## Robostyle

I think I figured out SOC voltages for whea-free run. Something like 1.15 for 3800, 1.25 for 3866, and dunno how much for 4000( 
Definitely waaay more than 1.3V...
Don't know what happened to this machine - and why I can't hit 4000 stable after reinstall...silicon degradation in 2 months? 
What's the long run safe limits of vermeers for SOC/VDDP/VDDG?


----------



## Veii

Robostyle said:


> What's the long run safe limits of vermeers for SOC/VDDP/VDDG?


AMD max overclocking voltage still valid
High SOC will mask lack of IOD - and High IOD will mask lack of CCD

40mV is the required distance as GET value
VDDG rebalances itself, but IOD + 40mV = SOC
CCD can be equal to cLDO_VDDP but usually +40mV there is also nice to have

If both VDDGs are equal, the unit will rebalance them internally & SMU can not register these values

1CCD units show bad voltages or bad core behaviour, if you can not hit or hold half maximum FCLK Bandwidth on Write
Be it because of voltages or because of bad overwritten curve optimizer
use y-cruncher for voltage testing, and OCCT extreme to confirm FCLK stability
Aida64 as fast short metric. If it doesn't improve ~ you don't need to waste time stability stresstesting it.
The stability can be autocorrected and maintained, yet in reality be sub-optimal

Aida64 is valuable for a lot of things, if you ignore it being a memory test and work outside of the box with it
* Preferably IOD + 80mV, but if you want it perfect, then you want to have it IOD+40mV = SOC
** 38mV = crash, 42mV = peak , more is not an issue ~ but 40mV is the minimum required distance
*** also preferably start with 1.83v 1.8V-line (it has many names)


----------



## citizenasdf

Hi All,

I'm wondering if anyone can help me with lowering tRCDRD. I tried other suggestions of increasing vddp, trfc, scl, vdimm, and procodt but I still get errors in TM5 when lowering tRCDRD to 19. Would changing Rtt, Cmd2T, GDM, or something else help me tighten or have I hit the limit with this kit?


----------



## Veii

citizenasdf said:


> I'm wondering if anyone can help me with lowering tRCDRD.


RTTs yes, if you know your PCB
tRRD & tWTR, also SCL & tRDWR ~ check the profile post for an example / or the signature
Balance these higher and you can drop primaries (more worth than low transition timings)
Starting with an even set of timings + 20-30hours of TM5 error debugging

Unclear memory kit, could be Rev-C or Rev-A
tRCDRD far to high for B-Die. Maybe "bad b-die"
Questionable timings , but nice latency !

GDM off will be a fight when you got used to such odd set
You can start from scratch pretty much

OCCT Extreme is the go-to stability test (AVX2)
And y-cruncher 4 loops, all tests (for FCLK)

SR kits like
706, 636, 727, 620
RTTs sorted by used VDIMM
Each of these needs tCKE and ClkDrvStr bump
4267 should be about tCKE 14, maaybe 15 but likely 14
Cold boot or training issues are resolved by CsOdtDrvSetup (30+ for Vermeer)

EDIT:
tCDD_L is 7 for you, right ?
if it's 6, tRAS 20 could run ~ bioses are just stupid. But maybe AMD CBS allows overrides sub value 21

EDIT 2:
When you start to load RTT_WR,
you can drop tCKE and can drop SETUP timings
Because DynamicODT will do it's job alone
Stronger DynamicODT will need different high/low's for RTTs
After /2 , you can drop Park completely ~ when you move beyond 1.65v
* 1.65v stays 36-43c for me on ambient open bench, voltage ≠ heat
** if you can balance tCKE & RTT_WR , you get even better thermal results and less strain by the high voltage ~ but it's a fight & different every MCLK


----------



## rossi594

Veii said:


> AMD max overclocking voltage still valid
> High SOC will mask lack of IOD - and High IOD will mask lack of CCD
> 
> 40mV is the required distance as GET value
> VDDG rebalances itself, but IOD + 40mV = SOC
> CCD can be equal to cLDO_VDDP but usually +40mV there is also nice to have
> 
> If both VDDGs are equal, the unit will rebalance them internally & SMU can not register these values
> 
> 1CCD units show bad voltages or bad core behaviour, if you can not hit or hold half maximum FCLK Bandwidth on Write
> Be it because of voltages or because of bad overwritten curve optimizer
> use y-cruncher for voltage testing, and OCCT extreme to confirm FCLK stability
> Aida64 as fast short metric. If it doesn't improve ~ you don't need to waste time stability stresstesting it.
> The stability can be autocorrected and maintained, yet in reality be sub-optimal
> 
> Aida64 is valuable for a lot of things, if you ignore it being a memory test and work outside of the box with it
> * Preferably IOD + 80mV, but if you want it perfect, then you want to have it IOD+40mV = SOC
> ** 38mV = crash, 42mV = peak , more is not an issue ~ but 40mV is the minimum required distance
> *** also preferably start with 1.83v 1.8V-line (it has many names)


Did you imply that they whea 19s can be fixed with a certain process of dialing in the right voltages?

You are so far ahead sometimes I have a hard time drawing conclusions from your info.


----------



## CarnageBT

When trying to correct for TM5 error 2. What variables and in what order would you try them? ie. vdimm, ( vsoc, vddp, vddg ccd / iod -- ?). resistance - procODT, rtt, DrvStr ?

I'm keep getting error 2 but am unsure of what I should be playing with to try to resolve it


----------



## citizenasdf

Thanks for your response. Apologies for many the questions, I'm fairly new to memory overclocking and this thread. Please see my responses * starred below.

RTTs yes, if you know your PCB
tRRD & tWTR, also SCL & tRDWR ~ check the profile post for an example / or the signature
Balance these higher and you can drop primaries (more worth than low transition timings)
Starting with an even set of timings + 20-30hours of TM5 error debugging

**** Unfortunately, I'm not sure how to check PCB. Below is what Taiphoon Burner shows.
**** would do you mean by Profile post? The main post? Your signature?
**** 20-30 hours of TM5 is a long time but I could do this after finding more tighter "stable" timings with short TM5 25 cycle test



ManufacturerSamsungPart NumberK4A8G085WB-BCPBPackageStandard Monolithic 78-ball FBGADie Density / Count8 Gb B-die (Boltzmann / 20 nm) / 1 dieComposition1024Mb x8 (64Mb x8 x 16 banks)

​
JEDEC DIMM Label8GB 1Rx8 PC4-2133-UA1-11


Revision / Raw Card0000h / A1 (10 layers)



Unclear memory kit, could be Rev-C or Rev-A
tRCDRD far to high for B-Die. Maybe "bad b-die"
Questionable timings , but nice latency !

*** Revision 0000h?
*** It might be bad b-die
*** this is with CTR active. HIGHER latency without CTR but around same read/write/copy numbers

GDM off will be a fight when you got used to such odd set
You can start from scratch pretty much
*** maybe it's best to leave it on GDM on for now then

OCCT Extreme is the go-to stability test (AVX2)
And y-cruncher 4 loops, all tests (for FCLK)
*** It passes these but I retest whenever I make changes

SR kits like
706, 636, 727, 620
RTTs sorted by used VDIMM
Each of these needs tCKE and ClkDrvStr bump
4267 should be about tCKE 14, maaybe 15 but likely 14
Cold boot or training issues are resolved by CsOdtDrvSetup (30+ for Vermeer)
**** I'll need to figure out what 706,636,727,620 means
**** ok, I can change tCKE to 14
*** Good to know about CsOdtDrvSetup being over 30+ for Vermeer. This will help with cold boot or training issues.

EDIT:
tCDD_L is 7 for you, right ?
if it's 6, tRAS 20 could run ~ bioses are just stupid. But maybe AMD CBS allows overrides sub value 21
**** sorry, I don't know what tCDD_L is. where can I find this?


EDIT 2:
When you start to load RTT_WR,
you can drop tCKE and can drop SETUP timings
Because DynamicODT will do it's job alone
Stronger DynamicODT will need different high/low's for RTTs
After /2 , you can drop Park completely ~ when you move beyond 1.65v
[* 1.65v stays 36-43c for me on ambient open bench, voltage ≠ heat
[** if you can balance tCKE & RTT_WR , you get even better thermal results and less strain by the high voltage ~ but it's a fight & different every MCLK
**** by "drop tCKE" do you mean put it on auto?
**** At 1.58v I see max temps reaching 46c after hours of memory stress test

Thank you Veii. It seems that I have a lot to learn about this but glad to see that there can be room for improvement


----------



## KedarWolf

1s1mple said:


> Heres mines
> View attachment 2513797


You need to mouse over 'Get Sil Quality' until it actually highlights so that you can click it. 90 is the default, which means you never actually calculated Sil Quality.


----------



## Veii

rossi594 said:


> Did you imply that they whea 19s can be fixed with a certain process of dialing in the right voltages?
> 
> You are so far ahead sometimes I have a hard time drawing conclusions from your info.


Been on this 5 months ago ~ now most can only run it since the WHEA suspender exists, but most of the community still is at that 2033 range. After 2067 the real struggle begins

It's hard to relink to soo many old posts , even more when a lot of the information where on twitter & i wiped them to free the @tag for something bigger
Complicated, i shouldn't be annoyed repeating ~ but it is repeating and repeating.
Never had WHEA #19 issues , got some once but only if i really have to be doing very stupid things

Although as comparison, working with a Dark Hero ~ it was nothing but WHEA#19 even on 1867 , with 1900 FCLK holes
It was painful, soo i can understand the annoyingness by some users
Gladly, i'm free from such ~ but then the Bios as exchange on ASRock is barebones and booring
The Asus ProArt made fun, but the reason i bought it for "Thunderbolt" is buggy on it's current state ~ while loosing the contact to my ASUS Rep
I shouldn't complain, after all was planing to retire

Tech-Support on it's own got frustrating / booring
Exploring new things kept/keeps the motivation up, but bioses got booring too. FCLK got booring - till next year, there isn't much to do. Soo i have my eyes now on Cezanne (5th of August)
We'll see

Aida64 i can only repeat, is your best friend ~ utilize it. For more than just memory tuning
Cache variability is an important thing this gen. Powerbudget management too
Everything everywhere will auto-correct and fight against you. Soo working on reaching an as consistent as possible setup ~ should be your goal

If you don't see even subtle Aida64 improvements on anything ~ then it makes no sense to keep benchmarking this voltages
Friends of mine use LatencyMon to track autocorrection spikes









I meanwhile stability check by crashes, as that's what WHEA means for me ~ freezes and reboots on anything little and tiny (on this cpu)
Y-cruncherr and OCCT for example ~ early the miners , and still consistently Aida64 (as i know how it should perform and behave, latency wise)

Everyone has their own methods to test things,
But it's at a point where saying less, is better. 
Letting you guys just re-read old posts instead of spamming everyone with the same lectures over and over again

If there is new updates, or urgent nice stuff ~ i'll post


CarnageBT said:


> When trying to correct for TM5 error 2. What variables and in what order would you try them? ie. vdimm, ( vsoc, vddp, vddg ccd / iod -- ?). resistance - procODT, rtt, DrvStr ?
> 
> I'm keep getting error 2 but am unsure of what I should be playing with to try to resolve it











This one is complicated
VDDP and VDDG are y-cruncher territory and Aida64 territory. On dual CCD units it's complicated ~ but single active solutions are easier. As Aida64 will instantly tell if something is off via "Write"

Haven't found a defined anchor, else it would have been updated with advices what to change first
It really can be everything
Mostly it goes together with 12's which go together with 0's and 6's
6 means something is big times messed up , 0's can just mean bad tRRD_, tWTR balancing or too low VDIMM.
0 & 12 can be rather RTT focused or CAD_BUS

Once i have the issue (currently do) and have a focused fix ~ the TM5 deciphering docs will be updated
I still have in plan, to put "error patterns" as possible lookup option , but it needs me to have more issues than i currently do
We'll see, everything with it's time. 
If i know something concrete, it will be updated


----------



## Robostyle

Veii said:


> AMD max overclocking voltage still valid


Okay, so with written above in my mind, I somewhat tinkered with voltages. Ended up with successful, fast boot and ~stable system at SOC 1.25V, ccd 980mV, IOD 1.15V and vddp 1.1V







Dropping IOD below 1.05, or might even below 1.1V has negative impact. And seems like this dud won't go 2000 fclk...

Other than that, I don't even have an idea if I'm doing everything right 😂

P.S. Nope, nothing helps to get rid of whea. Tried different voltage configurations, low vs high, from 900 to 1150 mV for both vddg and vddp


----------



## domdtxdissar

ManniX-ITA said:


> Ooops that I forgot
> there's also nice to know, it does say at start, --noTest to skip the test at boot which is useless
> Let's see if you can replicate my results, very curious!


Here we go 


5950x @ 4700/4600 static OC, SMT enabled
4x8GB memory sticks
Hwinfo open for all runs
consecutive runs
Flat CL 14-14-14-14 timings








T1 setup-time
*19723.4 H/S over 15min run*
upto 627 H/S per core








T1 GDM
*19151 H/S over 15min run*
upto 606 H/S per core








T2
*19413 H/S over 15min run*
upto 616 H/S per core

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

19413 / 19151 = T2 is ~1.3% faster than T1 GDM in this benchmark
19723 / 19413 = T1 setup-time is ~1.6% faster than T2 in this benchmark
19723 / 19151 = T1 setup-time is ~2.9% faster than T1 GDM in this benchmark

No time to break down the numbers further, going out 

But it seems like CPU mhz is king in pretty much every benchmark, *dont waste to much of your power budget on SOC if your running PBO CO *as the pure core clocks matters the most in the end...


----------



## 1s1mple

1s1mple said:


> Just posting my Sil Quality like others
> View attachment 2513742





KedarWolf said:


> You need to mouse over 'Get Sil Quality' until it actually highlights so that you can click it. 90 is the default, which means you never actually calculated Sil Quality.


Didnt i do it correctly the first time?








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Zentimings cant read those voltages on asus motherboards.. Hwinfo can read vdimm tho. (vtt mem is almost always half vdimm) What is your VDIMM set at?




www.overclock.net


----------



## KedarWolf

1s1mple said:


> Didnt i do it correctly the first time?
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Zentimings cant read those voltages on asus motherboards.. Hwinfo can read vdimm tho. (vtt mem is almost always half vdimm) What is your VDIMM set at?
> 
> 
> 
> 
> www.overclock.net


The picture in the post I replied to showed 90, look at the attachment on my response.


----------



## KedarWolf

1s1mple said:


> Heres mines


This post I mean for that. I might have replied to the wrong one.


----------



## KedarWolf

Here is mine but to get no errors running Blender or Cinibench I need 1.3125v at 46.5 46. I tried 1.35v at 47/46.5 and Blender would stop responding and sometimes Cinebench would error out.


----------



## KedarWolf

Veii said:


> About DPM , LCLK and similar
> Let me drop you this little tool
> Bios Modding - Google Drive Tool1007.zip (tool.exe)
> 
> Have fun with it
> Single CCD can run
> 
> 
> 
> 
> 
> 
> 
> 
> To override allcore EDC throttle
> You still should set Bios PBO EDC limit higher soo cache can boost up
> But this overrides another stage of allcore throttling
> 
> 
> 
> 
> 
> 
> 
> 
> This is interesting for you , just the plotting is a bit strange to use
> And this is what you surely will like to see
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Enjoy experimenting
> Each of the 8 "Frequency Limiters" Sensors can be the cause of frequency loss
> FIT PPT throttle usually appears because of something else, still searching for the value
> 
> DPM doesn't show up correctly and the ASRock ITX misses LCLK optionality to enable it. The Asus board had it
> Some values are under a wrong multiplier but there are valuable things to check and read out
> Effective Clock is correct for example
> Also it shows fully how many CCDs and Cores you have ~ for all these mysterious samples out there
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Copyright belongs to the ASUS Forums as XOC tool
> I forgot who published it and which team maintains it.
> No credit belong to me, just want to make it easier accessible to people
> 
> Waiting for 1.2.0.3A for the ITX board, then i'm gonna check out what can be done for the public
> 113 Binning value is already good, 118 is fantastic - haven't seen 120+ so far
> 
> 
> 
> 
> 
> 
> 
> 
> 
> DPM 2-1-1-2 doesn't show it
> testing 2-2-1-1 too ~ but this is intercore stuff. SiSoftware Sandra is your best friend for such
> This one is neat, but only ASUS boards let access to RAW VRM controller
> 
> 
> 
> 
> 
> 
> 
> 
> Apparently there should be an I²C port on the ITX , but i haven't checked
> =========================================
> MEM-OC thread, soo here are some valuable RTTs for Rev.E@1.6v or XMP under 56.50
> 
> 
> 
> 
> 
> 
> 
> View attachment 2513725
> 
> I lack a lot of options on the ASRock bioses - but 1203A update needs to be out, before it has any modding potential or consideration
> * on the Drive link above, AMI_FLASH Win can flash unsigned bioses ~ as long as the DeviceID remains identical. It bypasses AMDs SPI lock but is not able to cross-flash bioses
> Backups of it are sector based and tiny ~ do no use it for backup purposes, unless you can stitch bioses together (HEX)


@Veii 

What should I try for my 5950x?


----------



## Insidious Supra

Here's what I've got so far. Primaries of 14, 15, 15 15 do not like 1.53V. This all runs at 1.54. Temps stay below 40C without a cooler, but I am running a pretty efficient cooler now just for good measure.

I was manually setting vcore soc, and accidentally put it on auto. Turns out auto is wayyyy more stable, although it set the same damn voltage I was running before?? IDK

I reduced resistance as much as I could on procodt, but can't go lower than 53.3

These are both patriot 4400 kits (2x 2x8 kits) One pair of dimms was aquired second hand, and it shows a manufacture date of the year 2000. Huh? Other set says 2020 week 50. See attached thumbs... Also have the tiniest bit different timings. Some not reflected in these photos here, but visible in bios.

I decided on 3800 as anything higher seems to give me both higher and lower peak frames. (more inconsistent) I can get this stable at 4000 and 2000 fclk cl15, but like I said, performance is more spastic, though stable.


----------



## oobymach

Just learned this recently, TRC x TRTP = TRFC, do with this as you will but it seems to help.


----------



## rossi594

Veii said:


> Been on this 5 months ago ~ now most can only run it since the WHEA suspender exists, but most of the community still is at that 2033 range. After 2067 the real struggle begins
> 
> It's hard to relink to soo many old posts , even more when a lot of the information where on twitter & i wiped them to free the @tag for something bigger
> Complicated, i shouldn't be annoyed repeating ~ but it is repeating and repeating.
> Never had WHEA #19 issues , got some once but only if i really have to be doing very stupid things
> 
> Although as comparison, working with a Dark Hero ~ it was nothing but WHEA#19 even on 1867 , with 1900 FCLK holes
> It was painful, soo i can understand the annoyingness by some users
> Gladly, i'm free from such ~ but then the Bios as exchange on ASRock is barebones and booring
> The Asus ProArt made fun, but the reason i bought it for "Thunderbolt" is buggy on it's current state ~ while loosing the contact to my ASUS Rep
> I shouldn't complain, after all was planing to retire


Thanks for clarifying. 
I don't want to annoy you. I am just really frustrated. I got my board punched in fairly aggressive settings of another user, lowered voltages and had something nice and stable. Just the whea 19s drive me nuts. (I tryed to fix them with voltages for 10h+, there is just no real pattern. Only thing I noticed is that load doesn't matter - it's time / clockcycle based. Even in idle after a certain time a big pack drops. The time to that drop felt consistent.)
My chip runs 4000MT/s CL16-16-16-32 1:1:1 @ vsoc of 1,040v with only some usb dropouts, so I went to 1,070v and some more ccd_iod and everything is perfectly stable. I just did not want to do everything twice, so I thought I would wait for a fix. But there seems to be none. So I just punched in 3600 cl14. Still waiting for a fix from Gigabyte / AMD that is never coming.

So it seems to depend on the board? I swapped mine for the B550 Vision D, because it has the updated mem. topology. This should be easy. I bought top dimms and one of the boards with the best memory topology. I think I even got lucky on my chip.


----------



## rossi594

oobymach said:


> Just learned this recently, TRC x TRTP = TRFC, do with this as you will but it seems to help.


So does it lower my TRFC without showing? Or can I lower TRTP to get to TRTP x TRC = TRFC?


----------



## oobymach

In the case of b-dies with tCL 14 tRTP should either be 6, 7, or 8. Optimally it should be half or half minus 1 your tCL (ignore this if you have hynix chips). Mine is running ok at 7 and 3666/1833 but 6 needs more voltage I think, 7 is completely stable.

My current timings for comparison, in my case tRC 42 x tRTP 7 = tRFC 294, at 6 tRTP the refresh goes to 137ns at this speed and isn't totally stable. Setting command rate to 2t timing actually reduced my memory latency a hair so props to Veii for that recommendation.










Been using this tool for reference that Veii recommended.









tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com


----------



## rossi594

oobymach said:


> In the case of b-dies with tCL 14 tRTP should either be 6, 7, or 8. Optimally it should be half or half minus 1 your tCL (ignore this if you have hynix chips). Mine is running ok at 7 and 3666/1833 but 6 needs more voltage I think, 7 is completely stable.
> 
> My current timings for comparison, in my case tRC 42 x tRTP 7 = tRFC 294, at 6 tRTP the refresh goes to 137ns at this speed and isn't totally stable. Setting command rate to 2t timing actually reduced my memory latency a hair so props to Veii for that recommendation.
> 
> View attachment 2513922
> 
> 
> Been using this tool for reference that Veii recommended.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com












Are the 67 MT/s more worth going to 2t?

I assume you are running the patriot viper steels as well?


----------



## Taraquin

The V/F program doesn't read my CPU correct at all. It says best all core frequecy at 1037mv is 3300, I run [email protected] 100% stable. Estimated voltage at 5000 is 1909mv, I gan run [email protected] (stable but overheats in avx due to cooler.) My sil rating is 80. I run -30 CO at +50MHz, LLC medium, maybe some of this interferes?


----------



## rossi594

oobymach said:


> In the case of b-dies with tCL 14 tRTP should either be 6, 7, or 8. Optimally it should be half or half minus 1 your tCL (ignore this if you have hynix chips). Mine is running ok at 7 and 3666/1833 but 6 needs more voltage I think, 7 is completely stable.
> 
> My current timings for comparison, in my case tRC 42 x tRTP 7 = tRFC 294, at 6 tRTP the refresh goes to 137ns at this speed and isn't totally stable. Setting command rate to 2t timing actually reduced my memory latency a hair so props to Veii for that recommendation.
> 
> View attachment 2513922
> 
> 
> Been using this tool for reference that Veii recommended.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com


Your settings got me curious. This is what I came up with:










 Had to bend over 3-4 times to reset cmos while I was eating ...

tRTP seems to be affected by gdm. I thought it was only tcl.

Make sure you test well, CL14 3667 always errored super late for me. Like over 1h into memtest.


----------



## oobymach

rossi594 said:


> Your settings got me curious. This is what I came up with:
> 
> View attachment 2513926
> 
> 
> Had to bend over 3-4 times to reset cmos while I was eating ...
> 
> tRTP seems to be affected by gdm. I thought it was only tcl.
> 
> Make sure you test well, CL14 3667 always errored super late for me. Like over 1h into memtest.


Yeah I have the viper kit as well, I'm able to push it to 140ns refresh at 1800 mhz with trfc 252, trfc2 187 and trfc4 115 but I have the 16gb kit, your 32gb kit looks much nicer than mine but idk how low you can go with 32gb.

My poopy 32gb kit.










It was Veii who recommended 2t timings because 1t with gdm enabled can ignore your timings that you set.


----------



## craxton

ManniX-ITA said:


> This opens quite some interesting doors
> 
> Now you got a 125... but my silicon quality is not that good, not sure how reliable is this metric eheh
> 
> View attachment 2513669
> 
> 
> Also see my FIT VID is 1.5V and the Limit is a monstrous 52K:
> 
> View attachment 2513672


you guys are set, im HIT

(am i doing something wrong?)

your using this on a MSI board are you not?










so i have the "worst" CPU here? tf are you guys doing that i missed somewhere lol...


----------



## rossi594

oobymach said:


> Yeah I have the viper kit as well, I'm able to push it to 140ns refresh at 1800 mhz with trfc 252, trfc2 187 and trfc4 115 but I have the 16gb kit, your 32gb kit looks much nicer than mine but idk how low you can go with 32gb.
> 
> My poopy 32gb kit.
> 
> View attachment 2513928
> 
> 
> It was Veii who recommended 2t timings because 1t with gdm enabled can ignore your timings that you set.


I am using 2 16gb kits . But I made sure to get a nice board.
I did not do soo much clocking yet wanted to wait for a whea 19 fix to do all of it on 4000. But I wanted to give you something to punch in.


----------



## PJVol

mongoled said:


> hopefully we will get an agesa that is able to keep everything sync/trained with higher FCLK


Seems to have found the reason for stretching (or not stretching) clocks from boot to boot. Dont know how it exactly works, but after decreasing all CO values (abs) by 3-5, clocks normalized. Can't explain that phenomena atm, other than some static V/F curve formed at boot stage, taking current temps, power limits, etc into account, and used later by some DFS functionality. So when ambient temp rises, given that OC-ed DF cut a decent part off of a CPU total power budget, there's just lack of boosted P-states to met the "trained" conditions at high allcore load for the frequency the "dynamic" algorithm requested . Which condition exactly? I assume its the power, because temps are higher with lower abs. CO values (for obvious reasons), but the perfomance was not degraded at least, despite clocks shown are lower on average.
To put it simple - I see it as the "power clock stretching", similarly to "VID clock stretching" caused by low negative Vcore global offset

PS: Although, I realize that all of the above might turn out complete bulls**t, lol, it would be nice to hear any expert opinion about that ))


----------



## craxton

musician said:


> Win CPU silicon lottery


not so much in my case, since "if" i ran what these fellas were using a few pages back
right then well my cpu lottery is 80...lower than the default score it has...
and im WHEA free now. was getting WHEA 18 (never 19) 
but still.... 18 was due to core and curve adjusting...


----------



## domdtxdissar

domdtxdissar said:


> Here we go
> 
> 
> 5950x @ 4700/4600 static OC, SMT enabled
> 4x8GB memory sticks
> Hwinfo open for all runs
> consecutive runs
> Flat CL 14-14-14-14 timings
> 
> View attachment 2513871
> 
> T1 setup-time
> *19723.4 H/S over 15min run*
> upto 627 H/S per core
> 
> View attachment 2513872
> 
> T1 GDM
> *19151 H/S over 15min run*
> upto 606 H/S per core
> 
> View attachment 2513873
> 
> T2
> *19413 H/S over 15min run*
> upto 616 H/S per core
> 
> ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> 
> 19413 / 19151 = T2 is ~1.3% faster than T1 GDM in this benchmark
> 19723 / 19413 = T1 setup-time is ~1.6% faster than T2 in this benchmark
> 19723 / 19151 = T1 setup-time is ~2.9% faster than T1 GDM in this benchmark
> 
> No time to break down the numbers further, going out
> 
> But it seems like CPU mhz is king in pretty much every benchmark, *dont waste to much of your power budget on SOC if your running PBO CO *as the pure core clocks matters the most in the end...


Have also done some Aida numbers for my fastest T1 setup-time profile with my new CTR 24/7 settings


----------



## sendap

Impressive! 56 56 56 did the trick for 1T?


----------



## domdtxdissar

sendap said:


> Impressive! 56 56 56 did the trick for 1T?


Yes

And when i change over to T1, i change nothing other than the following 3 things in bios:

tCKE 1 -> 9
commandrate T2 -> T1
setup-time 0 ->56 (all 3)

If i change more than these settings it wont boot.. Once its booted and settings are "saved" there is no hassels with restarts and/or cold/warm starts. But everytime i change something in the bios i have to go over this prosses again.

Low ProcODT is also needed for this to work.. So you need to finetune your voltages/settings to run this low ProcODT* with dualrank memory.. singlerank 16GB everyone can run T1 

* = i also needed a bios with ageisa 1.202 to manage these settings


----------



## T[]RK

oobymach said:


> Just learned this recently, tRC x tRTP = tRFC, do with this as you will but it seems to help.


Carefull with this. It will not work for everyone! Good example - my system: [email protected] I can run tRTP as low as... 5 (with tWR=10).  And i have got tRC=48. So it mean that i may run tRFC=240? I tested before tRFC=264 and i can't complete TM5 even 3 cycles and got BSOD: Kernel Security Check. I think i can't even boot with tRFC=240.










Taraquin said:


> Estimated voltage at 5000 is 1909mv





Taraquin said:


> My sil rating is 80


You need to press "Get Sil Quality" first only after that press "Get Volts". Without that data software will use default value in "Sil Quality" window.


----------



## mongoled

T[]RK said:


> I think i can't even boot with tRFC=240


You may just need more vDIMM


----------



## Takla

oobymach said:


> Just learned this recently, TRC x TRTP = TRFC, do with this as you will but it seems to help.


Not applicable for micron e-die.


----------



## Dasa

Insidious Supra said:


> These are both patriot 4400 kits (2x 2x8 kits)


Mind checking the sticks to see how high the chips are on the PCB? Just had a closer look at mine and the chips are right at the bottom so all A2 I guess.
Will give your higher ODT a try but I wonder if you are running A0 and A2 sticks together which could be why I cant post at 2666 with 4 sticks of that RAM and you can get it stable at 4000.


----------



## Insidious Supra

Apparently all of mine are A0



Dasa said:


> Mind checking the sticks to see how high the chips are on the PCB? Just had a closer look at mine and the chips are right at the bottom so all A2 I guess.
> Will give your higher ODT a try but I wonder if you are running A0 and A2 sticks together which could be why I cant post at 2666 with 4 sticks of that RAM and you can get it stable at 4000.


----------



## Art385

Dasa said:


> Mind checking the sticks to see how high the chips are on the PCB? Just had a closer look at mine and the chips are right at the bottom so all A2 I guess.
> Will give your higher ODT a try but I wonder if you are running A0 and A2 sticks together which could be why I cant post at 2666 with 4 sticks of that RAM and you can get it stable at 4000.


Maybe try my timings. TWRRD must be at least 3 to boot on higher frequency with 4x8GB otherwise it will not boot and hang.


----------



## XPEHOPE3

mongoled said:


> Take RTT Park off RZQ/1 and move it to RZQ/3 before you end up destroying those modules.
> 
> Also ClkDrvStr may well be needed to increase to 120 ohms ..


I tried both settings, both separately and together, with all three *Setup settings set to Auto or all three to 30, or to 56 - neither of those configurations would survive to Windows logon.

However I've set my DRAM fan to 100% RPM, lowered voltages and passed 3 cycles of TestMem5 1usmus_v3:


Spoiler: screenshot















However I then cut down 1usmus' config to only Variable and Random tests and set them to Time (%)=500 (from default 100), and got first errors within 7 minutes! And all 6 errors appeared within some 30 minutes.










Why do you guys use 1usmus' config? I believe Time (%) = 100 produces not enough stress even with 25 cycles, because the tests switch too fast from stressing one component to another.
In comparison, anta777's config (with Time (%) = 500) catches catches errors of my setup, both full config and cut-down version.


----------



## Dasa

Insidious Supra said:


> Apparently all of mine are A0


Thaiphoon burner says the same about mine but fairly sure they are not A0.

* Art385 *
Fairly sure I had tWRRD at 3 but I will see how it goes with 4+ thanks.


----------



## Veii

Takla said:


> Not applicable for micron e-die.


Works well for me








Score is bad, i'm incapable to run tCL 12 (me being too stupid) but capable to run tCWL 10, somebody figure (likely bios is too stupid)
Should move in the sub 54 area with it

But something else,
Check the voltage to temperature
The memory is not directly cooled - maybe has a little fan which gives it around 10% focused air

If we change that to 1.65v and RTT: 620 it's even better
I'm still fighting with it to gett tRCD 18 run on 4000 , instead of having to drop to 20 for 4200
But it should show that it certainly is possible


oobymach said:


> Just learned this recently, TRC x TRTP = TRFC, do with this as you will but it seems to help.


This is kind of correct, but i don't want to be the person who betters up people

tWR is double just need to be inside the tRFC range
The same goes for tRTP - without GDM botth can be an odd value and can be the same multiplier i use on tRFC mini
But they can also be lower, as long as they stay less than 2 decimals inside the tRFCns range

You have to do the math in ns , not in virtual value


sendap said:


> Impressive! 56 56 56 did the trick for 1T?
> 
> 
> domdtxdissar said:
> 
> 
> 
> Yes
> 
> And when i change over to T1, i change nothing other than the following 3 things in bios:
> 
> tCKE 1 -> 9
> commandrate T2 -> T1
> setup-time 0 ->56 (all 3)
> 
> If i change more than these settings it wont boot..
Click to expand...

Doing so , does pretty much the same as going on 2T - but it's helpful
Just pushing ClkDrvStr , would do the same but actually changes powering and doesn't add delay 
ClkDrvStr and CsOdtDrvStr (to prevent coldboot issues with strange new memory training FW 30+ for Vermeer)


citizenasdf said:


> would do you mean by Profile post? The main post? Your signature?





Spoiler: This example

















Robostyle said:


> Dropping IOD below 1.05, or might even below 1.1V has negative impact. And seems like this dud won't go 2000 fclk...


You have a very strong Cache Throttle - could be EDC throttle , could be lack of voltage throttle
Y-cruncher should have screamed and cause issues with wrong voltages . Seems like you lack one somewhere


KedarWolf said:


> @Veii
> 
> What should I try for my 5950x?


Use the bottom field not the top one, but you can notice it on AMD Monitor that it will instantly change
400A is about fine - 420 or 460 is also ok
See if 600A applies and is used, or FIT throttles back
"used" in the sense that Cache does boost upwards.
You should limit TDC tho lower, else it overvolts and throttles because of such


XPEHOPE3 said:


> Why do you guys use 1usmus' config? I believe Time (%) = 100 produces not enough stress even with 25 cycles, because the tests switch too fast from stressing one component to another.
> In comparison, anta777's config (with Time (%) = 500) catches catches errors of my setup, both full config and cut-down version.


It will error out, has been proofen well over the time, but it needs time 
Error's are different - anta's error #2 means something else. We'll never know till somebody can understand both configs

25 cycles 1usmus_v3 will catch issues with powerdown & tRFC
Unsure if this 3 cycles are 1000% or where they come from, but they work too (original config at 1000% just takes 8:30h)


Dasa said:


> Fairly sure I had tWRRD at 3 but I will see how it goes with 4+ thanks.


tWRRD is X * SCL = less than tRCDavg or equal,
usually anchored to tRCDWR but it can be awkward and error only after a long time. tRCDavg works better


----------



## XPEHOPE3

Veii said:


> It will error out, has been proofen well over the time, but it needs time
> Error's are different - anta's error #2 means something else. We'll never know till somebody can understand both configs
> 
> 25 cycles 1usmus_v3 will catch issues with powerdown & tRFC
> Unsure if this 3 cycles are 1000% , but they work too


Can you please run attached config on any of your hard pushed B-dies? Preferrably 4 sticks...
I think it runs for <45 minutes and might err even on 25-cycle-stable systems (if e.g. cooling is suboptimal).

While 25 cycles of original 1usmus_v3 would run almost 8 hours for me


----------



## citizenasdf

Veii said:


> RTTs yes, if you know your PCB
> tRRD & tWTR, also SCL & tRDWR ~ check the profile post for an example / or the signature
> Balance these higher and you can drop primaries (more worth than low transition timings)
> Starting with an even set of timings + 20-30hours of TM5 error debugging
> 
> Unclear memory kit, could be Rev-C or Rev-A
> tRCDRD far to high for B-Die. Maybe "bad b-die"
> Questionable timings , but nice latency !
> 
> GDM off will be a fight when you got used to such odd set
> You can start from scratch pretty much
> 
> OCCT Extreme is the go-to stability test (AVX2)
> And y-cruncher 4 loops, all tests (for FCLK)
> 
> SR kits like
> 706, 636, 727, 620
> RTTs sorted by used VDIMM
> Each of these needs tCKE and ClkDrvStr bump
> 4267 should be about tCKE 14, maaybe 15 but likely 14
> Cold boot or training issues are resolved by CsOdtDrvSetup (30+ for Vermeer)
> 
> EDIT:
> tCDD_L is 7 for you, right ?
> if it's 6, tRAS 20 could run ~ bioses are just stupid. But maybe AMD CBS allows overrides sub value 21
> 
> EDIT 2:
> When you start to load RTT_WR,
> you can drop tCKE and can drop SETUP timings
> Because DynamicODT will do it's job alone
> Stronger DynamicODT will need different high/low's for RTTs
> After /2 , you can drop Park completely ~ when you move beyond 1.65v
> * 1.65v stays 36-43c for me on ambient open bench, voltage ≠ heat
> ** if you can balance tCKE & RTT_WR , you get even better thermal results and less strain by the high voltage ~ but it's a fight & different every MCLK


@Veii

Thanks for your response. Apologies for many the questions, I'm fairly new to memory overclocking and this thread. Please see my responses * starred below.

RTTs yes, if you know your PCB
tRRD & tWTR, also SCL & tRDWR ~ check the profile post for an example / or the signature
Balance these higher and you can drop primaries (more worth than low transition timings)
Starting with an even set of timings + 20-30hours of TM5 error debugging

**** Unfortunately, I'm not sure how to check PCB. Below is what Taiphoon Burner shows.
**** would do you mean by Profile post? The main post? Your signature?
**** 20-30 hours of TM5 is a long time but I could do this after finding more tighter "stable" timings with short TM5 25 cycle test



ManufacturerSamsungPart NumberK4A8G085WB-BCPBPackageStandard Monolithic 78-ball FBGADie Density / Count8 Gb B-die (Boltzmann / 20 nm) / 1 dieComposition1024Mb x8 (64Mb x8 x 16 banks)



JEDEC DIMM Label8GB 1Rx8 PC4-2133-UA1-11

Revision / Raw Card0000h / A1 (10 layers)



Unclear memory kit, could be Rev-C or Rev-A
tRCDRD far to high for B-Die. Maybe "bad b-die"
Questionable timings , but nice latency !

*** Revision 0000h?
*** It might be bad b-die
*** this is with CTR active. HIGHER latency without CTR but around same read/write/copy numbers

GDM off will be a fight when you got used to such odd set
You can start from scratch pretty much
*** maybe it's best to leave it on GDM on for now then

OCCT Extreme is the go-to stability test (AVX2)
And y-cruncher 4 loops, all tests (for FCLK)
*** It passes these but I retest whenever I make changes

SR kits like
706, 636, 727, 620
RTTs sorted by used VDIMM
Each of these needs tCKE and ClkDrvStr bump
4267 should be about tCKE 14, maaybe 15 but likely 14
Cold boot or training issues are resolved by CsOdtDrvSetup (30+ for Vermeer)
**** I'll need to figure out what 706,636,727,620 means
**** ok, I can change tCKE to 14
*** Good to know about CsOdtDrvSetup being over 30+ for Vermeer. This will help with cold boot or training issues.

EDIT:
tCDD_L is 7 for you, right ?
if it's 6, tRAS 20 could run ~ bioses are just stupid. But maybe AMD CBS allows overrides sub value 21
**** sorry, I don't know what tCDD_L is. where can I find this?


EDIT 2:
When you start to load RTT_WR,
you can drop tCKE and can drop SETUP timings
Because DynamicODT will do it's job alone
Stronger DynamicODT will need different high/low's for RTTs
After /2 , you can drop Park completely ~ when you move beyond 1.65v
[* 1.65v stays 36-43c for me on ambient open bench, voltage ≠ heat
[** if you can balance tCKE & RTT_WR , you get even better thermal results and less strain by the high voltage ~ but it's a fight & different every MCLK
**** by "drop tCKE" do you mean put it on auto?
**** At 1.58v I see max temps reaching 46c after hours of memory stress test

Thank you Veii. It seems that I have a lot to learn about this but glad to see that there can be room for improvement


----------



## craxton

Taraquin said:


> The V/F program doesn't read my CPU correct at all. It says best all core frequecy at 1037mv is 3300, I run [email protected] 100% stable. Estimated voltage at 5000 is 1909mv, I gan run [email protected] (stable but overheats in avx due to cooler.) My sil rating is 80. I run -30 CO at +50MHz, LLC medium, maybe some of this interferes?


same for me, although mine undervolts pretty well. 
4850 on all cores but one runs fine at 1.35 
(that bad core) doesnt allow me to run over -26 CO with 50mv offset.


----------



## craxton

(did anyone) with a 5600x run the "tool" veii posted and 
have a better score than 80? only seen two posted, unless i missed a few...
if this chips silicon is indeed so bad, how is the IMC so dam good???????
or are these not related at all? 

Veii you posting this caused a whole heap of messes 
this might just push me enough to actually buy that 5600x 
and perhaps sell this one or "keep" for comparisons against each other...

shouldnt be hard to find a 5600x better than the one i have....

@Taraquin i retract what i said about -26 earlier, with this new agesa for whatever 
reason, currently running all core -30 with 50mv offset to core.
(no stress tests) but before i couldnt get thru windows without crashing. let alone run 
tm5 at all, or open HWiNFO/Chrome....


----------



## Dasa

Not sure what changed but they are now posting fine together at 3800

How safe are Patriot Viper 4400c9 A2 at 1.572v with these settings and is there anything else I should change to make it safer.
Thanks.
Probably going to need 1.6v to get c14 vs 1.45v for c15.


----------



## jomama22

craxton said:


> (did anyone) with a 5600x run the "tool" veii posted and
> have a better score than 80? only seen two posted, unless i missed a few...
> if this chips silicon is indeed so bad, how is the IMC so dam good???????
> or are these not related at all?
> 
> Veii you posting this caused a whole heap of messes
> this might just push me enough to actually buy that 5600x
> and perhaps sell this one or "keep" for comparisons against each other...
> 
> shouldnt be hard to find a 5600x better than the one i have....
> 
> @Taraquin i retract what i said about -26 earlier, with this new agesa for whatever
> reason, currently running all core -30 with 50mv offset to core.
> (no stress tests) but before i couldnt get thru windows without crashing. let alone run
> tm5 at all, or open HWiNFO/Chrome....


Highly doubt silicone quality has anything to do with much beyond best core maximum boost on whatever the primary chiplet is. It isn't some all encompassing metric. There is a reason it isn't included in asus' bios (unlike the Intel counterparts) as it doesn't give any real perspective of what the whole chip can do.

It also was never meant to cover anything about the I/O die. It's why it's bundled with voltage/frequency estimations.

Using it for any sort of guesstimation of chip potential is more or less meaningless.


----------



## craxton

jomama22 said:


> Using it for any sort of guesstimation of chip potential is more or less meaningless.


ill take your word on this...but still would like to see others with a 5600x show scores over 80 lol
seems thats all a 5600x gets, someone mentioned in Discord that uri stated that this software 
is built for bulldozer?


----------



## Sleepycat

XPEHOPE3 said:


> Hello! Is there a specific guide on how to make overclock of 4 sticks of 16Gb stable? Or maybe a guide which timings to tighten in which order?
> 
> I have B-dies which won't test good @ 3800CL14 (F4-3200C14Q-64GVK @ 5600X and B500 Aorus Pro V2)
> View attachment 2513795
> 
> 
> I test with TestMem5 anta777 extreme, failing tests are 9, 15, 11, 14, 10, 3 (the ones which are SimpleTest with Pattern mode 1 or 2). They fail even when only them are in a test sequence.
> Temps while testing are 44-45.8 (Noctua A14 900RPM blowing directly at RAM).
> Some other benchmarks pass though (like xmrig benchmark 1M or Linpack Xtreme benchmark 8G).
> 
> I could run the memory stable with 3600-14-14-14-14-34 and 3800-16-16-16-16-34. That 3800-16 config passed TM5 anta777 extreme with DRAM temps of 48,53,53,51 even without cooling. Does it mean the 46-ish temps are Ok for tighter timings??
> 
> 3866-1933 won't get me to Windows (at least with VDIMM 1.5V and ProcODT Auto (48 Ohm)).
> 3800CL14 will only boot to Windows with 1.52 DIMM if ProcODT is on auto (meaning 48 Ohm). At VDIMM 1.55V Lowering ProcODT to 40 Ohm or 34.3 would lower(!) number of errors. With ProcODT values in between of 34.3-40-48 I can't boot to Windows.


Quick test. Set tRCDRD to 15 and re-run TM5, see if those errors go away.


----------



## Sleepycat

Is this the best I can achieve with 4x16GB B-die? Am I limited by the fact that I am running 4 sticks of 16GB DR?

1800 FCLK seems to be the limit with this set up, even pumping vSOC to 1.2V and VDIMM to 1.55V, setting to CL18 does not let me post at 1833 FCLK. It goes higher to 1933 with 2 sticks, even with only a vSOC of 1.1V, but stuck at a 1800 wall with 4 sticks. This setting is WHEA-free, passes TM5 and OCCT large extreme.


----------



## Dasa

Veii said:


> tWRRD is X * SCL = less than tRCDavg or equal,


So if I understand you correctly then with tRCDRD 15 tWRRD 3 I should drop tRCDWR to 9 so that 3x4= the tRCD average of 12 and that tRCDWR10 would also be ok.


----------



## Veii

XPEHOPE3 said:


> While 25 cycles of original 1usmus_v3 would run almost 8 hours for me


You would need to bear with it - but 32gb take 3:38h, to 4h
soo 64gb would take 8h that's correct

"Sadly" short 17min tests mean nothing, as thermal equilibrium takes at least 45min to be reached
But it did not change anything ~ the "normal official" TM5 is already very efficient
20 cycles are set aside from reaching thermal equilibrium - to also find tRFC and tREFI errors
tREFI you can not set ~ but there are many timings which fail on the end of the 19th cycle and some even after 24 cycles

My personal usage is 25 cycles
But 20+ is more than enough










jomama22 said:


> Using it for any sort of guesstimation of chip potential is more or less meaningless.


Is it an estimate or is it actually reading FITs guestimates
If we can not trust FIT - i am not sure
It doesn't run an single core either

In such case we shouldn't trust 1usmus's short P95 allcore load, with as low as possible IPC requests ~ for CTR
As such thing is based on the exact same method & would fully fall apart, if the method is flawed in any way (ignoring the 20+ people who contributed to the project)
The required max voltage and the Freq to Voltage according to FIT's V/F curve , is a bit strange
but considering CO did nothing to that value, i think it's valid .
Cooler score metrics have yet to be seen and understand.


craxton said:


> someone mentioned in Discord that uri stated that this software
> is built for bulldozer?


Bulldozer never had any CCX - the first version for ryzen 1xxx 2 years ago had CCX support
He has to mean something else ~ or is just confused


Dasa said:


> So if I understand you correctly then with tRCDRD 15 tWRRD 3 I should drop tRCDWR to 9 so that 3x4= the tRCD average of 12 and that tRCDWR10 would also be ok.


The tWRRD value can be less than that - but it shouldn't be more than it 
Keeping tRCD flat, as a balance thing most of the times to nearly always ~ results in better perf, than odd timings

Odd timings are very hard to balance
They look faster , random access latency can be lower - but bandwidth is mostly also worse. They are not easy to balance


----------



## Kurt Krampmeier

Hello all!

i already asked my Question on german forums but i got no helpful advice yet.
i know that with the combination of B450 + 4x B-Die aimed at overclocking, this board may be hindering.
but the fun in overclocking has always been to me, getting my results with reasonable budget.
so i got myself this used b450 and 4 sticks of fairly old Gskill 2nd hand and put it
together with my 5900x i got some time ago at the amd online store, when originally aiming at a 6800 
the trial and error took some time but i made it to this










with reasonable stability. Memory is at 1.58v and has 80mm fan above it.
vddg_ccd and iod are reported same voltage but set 1.02 and 1.06 in bios.
the board would not boot with default ODT(60) any higher than 3400mhz. default RTT was 7/2/1, what worked up to 3600.

there was no boot above 3666 with any settings - and i tried timings, voltages, rtt combinations, ODT
(only 43.6 gets to 3666- lower only to 3600 - above 48 no luck) and several cad resistances
from advice on forums, but that made it rather worse.
while reading forums i came across this thread, where the knowledge looks sound.
so does anyone know the trick with getting the B450 to 3733 or 3800mt with 4 Sticks of ram?
i know i could well throw money at the problem and change the board, but then, that's easy.

Thanks in advance for any suggestions.

AMD Ryzen 9 5900X
Asus ROG STRIX B450-F GAMING II Bios 4301
Frequency 1832.9 MHz (DDR4-3666) - Ratio 3:55
Slot #1 Module G.Skill 8192 MB (DDR4-2137) - XMP 2.0 - P/N: F4-3200C14-8GVK
Slot #2 Module G.Skill 8192 MB (DDR4-2400) - XMP 2.0 - P/N: F4-3200C14-8GFX
Slot #3 Module G.Skill 8192 MB (DDR4-2137) - XMP 2.0 - P/N: F4-3200C14-8GVK
Slot #4 Module G.Skill 8192 MB (DDR4-2400) - XMP 2.0 - P/N: F4-3200C14-8GFX


----------



## craxton

Veii said:


> He has to mean something else ~ or is just confused


Uri is he "in discord" which I didn't see 
Him mention this, jus others claiming he did.

I now know that in Aida "all core" stress I get 45xx with pretty open limits, and 200mhz boost. No curve just that....well, per core near all hit 4850 other than my two "worst" cores. However, I do believe this would be considered "defective"? Considering the advertisment is 4650? Or is that not 
An all core workload... My max 4850 with "tool" states 
1675 is needed and 5000ghz is 1.7xx lol
My CPU is for sure fd up... I tried using 0-5 cores but no give went thru all configs no change 😭 

As I got this chip from a scalper I'm pretty sure 
I can't return and get a new one. 
But, I can buy a 5800x here Ina week. 
Since a hole ebay sellers want near 400 for a 4650g now... Due to crypto. 

Anyways, gonna test the 3600xt tomorrow sometime if I'm up to it. And see if I can whea-19.


----------



## mongoled

@craxton, go back a couple of pages (464/465) , there are at least two people showing results with 5600X, one is mine and one post has peeps pointing out to an OP that you need to press the "get sil quality" button!

Mine is around 117....


----------



## rossi594

Dasa said:


> First kit of Patriot 4400c19 did 3771 14-15 1.48v
> Second kit needs 1.56v just to boot.
> Put the 4x4400c19 sticks together and they wont even post at anything over 2133.
> The original 4400c19 worked fine with my 3200c14 except they couldn't run 1T together while 4x8GB of 3200c14 could.
> Not what I was expecting.


I have 4 of those running up to 4000 no problem. I think my soc won't do higher flck. let me try.


----------



## Robostyle

Veii said:


> You have a very strong Cache Throttle - could be EDC throttle , could be lack of voltage throttle
> Y-cruncher should have screamed and cause issues with wrong voltages . Seems like you lack one somewhere


Hm, I haven't touched core yet, cpu is on stock. 
Should. i change something else - PBO, C-states? Frankly, I still have no idea since Im novice to am4...


----------



## Veii

craxton said:


> As I got this chip from a scalper I'm pretty sure
> I can't return and get a new one.
> But, I can buy a 5800x here Ina week.
> Since a hole ebay sellers want near 400 for a 4650g now... Due to crypto.
> 
> Anyways, gonna test the 3600xt tomorrow sometime if I'm up to it. And see if I can whea-19.


Currently Zen3 units are falling in prices, to spread all the collected left stock








60-120€ less on each unit , mostly 10% off
5950X retailed earlier for 850-900€ (over 1 grand usd)

AMD does want to lift all the old stock
I think you might want to deal with what you got and wait till Christmas 
Winter will get interesting again ~ but APUs release on the 5th of August

It might make sense to wait a bit, if the unit is not borked and well usable

About V/F tool
Too many engineers and most from the ASUS team have worked on this tool.exe . Especially the V/F curve part
I do find the requirements for X frequency are a bit strange ~ considering we don't understand the cooler score really

But i do still think that whatever this random rating means, it's valid
Considering it's stable, doesn't change by cores amount and we all get such different results out of it
It's usage on Matisse and lower is questionable, as it rated a 3950X with a lot of near 200 ACPI (FIT) core values ~ very low in the 80's 
Just when it comes to Vermeer, it seems to hold some stand.
Again, whatever this cooler score metric has to mean (which also didn't influence that silicon rating)

I do think however, that it is more of a peak "held" frequency thing
Likely doesn't factor in PBO possibilities & wouldn't mean like on CTR that a "silver or bronze sample" can not reach 4.85ghz allcore PBO 
It only would mean , that it's rather a leaky silicon and needs more current.
After all , not every silicon has to be low power ~ in order to be a good peak freq overclocker
Look on it more neutral ~ don't base your wallet upon this value. It "again" still can perform very well on peak boost (just with far more input voltage) 



Robostyle said:


> Hm, I haven't touched core yet, cpu is on stock.
> Should. i change something else - PBO, C-states? Frankly, I still have no idea since Im novice to am4...


Only disable DF-C States on Vermeer for now. It's still a broken boosting system and will cause overboost bugs upon core wakeup
Global C-States enabled , and CPPC should be enabled.

Apparently disabling CPPC states & running an allcore, gives a big stability boost (lowers also DPC calls by quite a bit)
But i don't feel like, this should be our goal. Going against AMDs boosting System
Global C-States keep always on
It allows the CPU to lower frequency on "bad" or unused cores ~ resulting in generally more boosting reserves for good cores which can reach higher freq


----------



## Robostyle

Veii said:


> Only disable DF-C States on Vermeer for now. It's still a broken boosting system and will cause overboost bugs upon core wakeup
> Global C-States enabled , and CPPC should be enabled.
> 
> Apparently disabling CPPC states & running an allcore, gives a big stability boost (lowers also DPC calls by quite a bit)
> But i don't feel like, this should be our goal. Going against AMDs boosting System
> Global C-States keep always on
> It allows the CPU to lower frequency on "bad" or unused cores ~ resulting in generally more boosting reserves for good cores which can reach higher freq


I see. 
And what about cache throttle - you mean, L1/2/3 Bandwith are abnormal? What else should I try in order to stabilize cache/MC/IF/RAM?
For now, I only touched soc/vddp/vddg and 1.8 rail.


----------



## Veii

Robostyle said:


> I see.
> And what about cache throttle - you mean, L1/2/3 Bandwith are abnormal? What else should I try in order to stabilize cache/MC/IF/RAM?
> For now, I only touched soc/vddp/vddg and 1.8 rail.


Be first sure that you can even pass y-cruncher (all tests , 1-7-0) 
Then override PBO witth Scalar X1 (companies love to cheat there)
and maybe it's just your windows which slows it down
but it's at least 30% slower than stock, soo i think something fishy is going on

Going offset mode and adding the slightest bit of positive vcore should also fix much
Most of the times, boardparners make their own voltage ranges ~ and only offset mode does really reset it to AMDs based scaling 
Soo a tiny offset will wipe whatever cheating was going there (too)

Check this and report back
y-cruncher for stability needs 4 loops = 4*18min , to be anywhere near "stable"


----------



## aditrex

guyz can u imagine not even 3600 profile is stable for me what do u think i have faulty cpu or motherboard


----------



## XPEHOPE3

Sleepycat said:


> Quick test. Set tRCDRD to 15 and re-run TM5, see if those errors go away.


I remember previously testing it with no luck, but with changed ProcODT (rest of changes come from autotraining) now it passed failing tests from the post you quoted:


Spoiler: screenshot














Temps were even greater (48.1 vs 45.5), but they will be lower with full RPM (not half like now).
I will be running fuller tests after I bench this and see if it's good enough to stabilize. (EDIT: ofc I got 3800-16 performance (in AIDA); since I'm on GDM on, doesn't tRCD 15 behave like 16?)

I noticed we have the same kits 
Did you see any perf gains going to GDM off + 2T?
Also we have common "Str" settings (coming from Auto, I guess), but different CAD BUS. Did you set those by yourself or are they auto?


----------



## Yuke

settled down with this for my 3800X










Note: Karhu with Cache stressing enabled
Note2: All Core OC to see actual gain

Hoping to attack GDM = off at some point


----------



## wuttman

@craxton any particular reason you use proc as high as 40 for 4000mhz on 5600x?


----------



## mongoled

aditrex said:


> guyz can u imagine not even 3600 profile is stable for me what do u think i have faulty cpu or motherboard


Please try

tRP @15
tRAS @30
tRC @15
tRDS @4
tRDL @6
tFAW @16
tWTRL @12
tWR @16
tRDRDSCL/tWRWRSCL @3
tRFC @ 360
tRFC2 @267
tRFC4 @165
tWRRD @3

Report back

😊


----------



## T[]RK

I made screenshots from GIGABYTE BIOS about DF Cstates. Hope it will help someone.
1. Peripherals => *AMD CBS* => NBIO Common Options







2.*NBIO Common Options* => SMU Common Options







3. *SMU Common Options* => *DF Cstates* - Disable


----------



## sendap

can not find it in MSI BIOS. Only Global C-State...


----------



## craxton

Veii said:


> Currently Zen3 units are falling in prices, to spread all the collected left stock
> 
> 
> 
> 
> 
> 
> 
> 
> 60-120€ less on each unit , mostly 10% off
> 5950X retailed earlier for 850-900€ (over 1 grand usd)


yea around where im at, there hasnt been anything on a discounted price atm. 








granted i didnt go looking thru sites, but usually google brings up where i check anyhow. 



Veii said:


> I think you might want to deal with what you got and wait till Christmas


waiting could mean better sense, but at the same time i waited to not buy a second 2070S 
to match my ftw 3 ultra+ back when they were 680 us and now i havent seen one in stock
in months lol. 
id have to guess with the release of the APUs in august that pricing will go up as AMD stock price
will increase yet again. (perhaps for a short time) but none the less a spike is always present when 
something new is released and everything gets sold out.
(this time last year a 2700x was 150 usd or less....NEW lol rather strange how that price SKY rocketed the way it did...



Veii said:


> About V/F tool
> Too many engineers and most from the ASUS team have worked on this tool.exe . Especially the V/F curve part
> I do find the requirements for X frequency are a bit strange ~ considering we don't understand the cooler score really
> 
> But i do still think that whatever this random rating means, it's valid
> Considering it's stable, doesn't change by cores amount and we all get such different results out of it
> It's usage on Matisse and lower is questionable, as it rated a 3950X with a lot of near 200 ACPI (FIT) core values ~ very low in the 80's
> Just when it comes to Vermeer, it seems to hold some stand.
> Again, whatever this cooler score metric has to mean (which also didn't influence that silicon rating)


i was wondering where this tool came from, no matter what i changed the cooler score too 
it changed very little. i seen a cooler score somewhere else before but i cant recall what i was looking at that
based AIO coolers on the scale "spot" they were placed. i suppose my memory isnt what it used to be. 
i do know if one places "300" for instance inside cooler score it crashes the software most the time 
even tho thermal throttle or none of the likes happens in HWiNFO. 
i tried LOADS of different things to change the "silicon lottery score" but nothing changed it.
undervolting, overvolting, llc 1 2 3 4 auto, setting complete stock values, nothing (including setting the best cores i could)



Veii said:


> I do think however, that it is more of a peak "held" frequency thing
> Likely doesn't factor in PBO possibilities & wouldn't mean like on CTR that a "silver or bronze sample" can not reach 4.85ghz allcore PBO
> It only would mean , that it's rather a leaky silicon and needs more current.
> After all , not every silicon has to be low power ~ in order to be a good peak freq overclocker
> Look on it more neutral ~ don't base your wallet upon this value. It "again" still can perform very well on peak boost (just with far more input voltage)


on auto, CTR thinks my chips a "golden sample" although it might be in all cores except core 3 being 131 by far 
the worst core needs "extreme" amounts of voltage over the other cores to sustain X frequency.
id have to take a HARD GUESS that when i dropped it (about 5 inches) when i installed it
sometime back, it actually did do a little "unseen" damage to the chips credit tho, everywhere else is 
above par with what most get that ive seen. 
if i turn off PBO thats when i notice it wont boost to the "max" rated clocks under a full load. 
"per core" however does just fine. even setting "core X and core X (0) always" does fine.
still no change in frequency curve graphs shown with TOOL. 
my wallet has no value on trying to fix this chip, have been looking into a new chip for several months now.
only now ive been back to 90+hrs per 2 weeks have i had a little spare change to throw at it. 
i dont game much anymore, mostly in bios tweaking all the time.

im always a more "half full" kinda guy, but since the 3600xt was a "overclocking beast" minus the IMC being sub par
i figured all the chips ive had up-to this point were all great at what i usually do.. this one being the exception. 
(NOTE) ive watched AMD monitor for quite sometime underload and idle, true core 0 and 2 never come alive period. 
so id have to bet theyre indefinitely turned off. 

appreciate the "viewing perspective" to which ill hold and continue tweaking, 
perhaps, turning off this one core might do what i was "seeing" a 5600x do elsewhere. 
"not expecting" at this point, just observing how "a good chip" can be "without" that one "horrific" core.


----------



## craxton

sendap said:


> can not find it in MSI BIOS. Only Global C-State...


if you dont have "unlocked" bios, or Unify X or "godlike" boards
you wont see it.
what board do you have? itll be under advanced and if the option is unhidden in your bios,
itll be where "AMD OVERCLOCKING" will be setting not inside that spot. but on that page either above or below.
































to which itll be inside CBS you wont miss it promise.
if someone has "unlocked/unhidden" your bios then itll be here 
(here being the person who unlocked the B550 gaming edge wifi im running) 
just flash it as if your updating the bios thru MSI FLASH. 
DISCLAIMER! if you mess up a bios flash, your the one pressing "FIRE" youll be responsible noone else.

but, shouldnt have any issue. granted you flash the bios "FOR YOUR BOARD"


----------



## 1s1mple

sendap said:


> can not find it in MSI BIOS. Only Global C-State...


Check in the AMD CBS menu


----------



## craxton

wuttman said:


> any particular reason you use proc as high as 40 for 4000mhz on 5600x?


yep, its daily driven as such for 4 months or so now ?
40 is "MAX" i believe is what was stated for 5000 series on proc.
i could lower it id assume, granted i wanna mess with cad_bus strengths etc.
but i dont. my scores are exactly where they should be for the most part.

im running 2x8 + 2x8 (same sticks however) they were purchased at different times
to which the second set (NEWEGG) (first set amazon) again, second set, has some different timings
like well here... you can see, this is why i stopped when i passed all the tests i had been doing.
minus CO being a nightmare with this chip. as all cores are pretty good minus 1 core being a dud.

(FIRST SET)








(SECOND SET)








at only a 2x8 config, i can run C14 flat at 4000mhz
with 36.x proc but that was on the "BETTER" two sticks.
i didnt really think that TEAM would change anything between sets. but i suppose
when sets are made is quite a big change in certain timings. since the second set wouldnt do c14 (same profile)
at 4000mhz GDM OFF of course. i have no proof of any of this (checking WAY back in this post, will show it somewhere).
lost all my files due to a new install selecting destroy everything,
was trying to figure out if i was "getting" recorded WHEA events, to which i was...

does that answer your question, in short its what "works" lol..


----------



## craxton

mongoled said:


> go back a couple of pages (464/465) , there are at least two people showing results with 5600X, one is mine and one post has peeps pointing out to an OP that you need to press the "get sil quality" button!
> 
> Mine is around 117....


for whatever reason, i thought you was running a higher core count chip, 
and seen PJvol shot after posting this.

to which i pressed "get sil" around 100x or so trying many many different things and its sadly 80.
possibly lower but maybe the tool doesn't go lower than 80 by default. 
gotta great IMC but the OC ability is horrific. which explains why i have such a hard time getting CO dialed in
all cores but one runs fine with -20 +50mv offset.to which that "one" core needs a + value to which will not boost 
to 4.85 past +7 

(off topic of tool) on topic of CO,
have you or anyone else noticed that core cycler, will pass cores running all FFT sizes thru multiple iterations, 
then you go change one core value for "CO" and go test again, and the testing fails what was "stable" for a core 
that was "stable"? 
is that how its supposed to be, or is this positive value impacting another core somewhere?


----------



## T[]RK

sendap said:


> can not find it in MSI BIOS. Only Global C-State...


They hide it. On my GIGABTE board BIOS F61a was pretty simple, but in F61c they unlocked almost everything (i guess). I have got tonns of new menus.


----------



## sendap

craxton said:


> if you dont have "unlocked" bios, or Unify X or "godlike" boards


i am on the latest official BIOS (A9) for the X570 Unify


----------



## hazium233

craxton said:


> to which i pressed "get sil" around 100x or so trying many many different things and its sadly 80.
> possibly lower but maybe the tool doesn't go lower than 80 by default.


Don't know if I ran this correctly (default bios settings), but here is what I got with mine:


----------



## XPEHOPE3

Veii said:


> You would need to bear with it - but 32gb take 3:38h, to 4h
> soo 64gb would take 8h that's correct
> 
> "Sadly" short 17min tests mean nothing, as thermal equilibrium takes at least 45min to be reached
> But it did not change anything ~ the "normal official" TM5 is already very efficient
> 20 cycles are set aside from reaching thermal equilibrium - to also find tRFC and tREFI errors
> tREFI you can not set ~ but there are many timings which fail on the end of the 19th cycle and some even after 24 cycles
> 
> My personal usage is 25 cycles
> But 20+ is more than enough


I started 1usmus_v3 25 cycles, left the PC, came after 3,5 hours and saw everything was Ok after 13 cycles:








Then, wellllll, I just wasted some ~3 hours 
Since I have only one monitor I switched its inputs from PC being tested to my main PC,
and also replugged my keyboard from one PC to another. And TM5 just stopped doing
tests as can be seen from status time in the


Spoiler: screenshot!















I'm tempted to consider it stable now since it also passed 4 iterations of y-cruncher
full tests (1-7-0, as you said).

However performance isn't there, it's on the level of this setup for both AIDA latency (60,85+-0,8)
and read speed (52362+-270):








How can it be that *3800-14-15* performs as bad as *3800-16 flat*?? (I only set voltages, procODT
and first 5 timings, rest comes from training, and difference between training results seem minor to me)


----------



## Iarwa1N

For those who gets SIL Quality 80 from the tool @Veii has posted, try to remove any anticheat you may have and try again. I got 80, and AMD monitor tool couldn't able to read any values, so I uninstalled Faceit anticheat and the tool started working after that.

5900x;









I managed to get my kits running at 3600 mhz but with 1.6 vdimm. I don't know the layout of my kit, can somebody tell me if there is any dangerous RTT settings that I might be using. I don't know what to look for to not damage the memory dimms while setting the RTTs. I am trying all possible combinations to make my kit stable at or above 3600.










The settings in the picture was stable TM5 for 1 hour and I played games like 8 hours yesterday and today it is unstable, I barely make windows, how can this be possible. Even clearing cmos does not works after my windows got stuck and I had to remove sticks and reinsert them to just boot into bios. I am really tired of this kits, nothing I tried works.


----------



## Veii

Iarwa1N said:


> I managed to get my kits running at 3600 mhz but with 1.6 vdimm. I don't know the layout of my kit, can somebody tell me if there is any dangerous RTT settings that I might be using. I don't know what to look for to not damage the memory dimms while setting the RTTs. I am trying all possible combinations to make my kit stable at or above 3600.


A2 (B2) can handle this, in exchange of big instabilities
Other ones should have been dead by now (or maybe are still alive because GDM runs them internally at half speed)

CAD_BUS you want to run as 40-20-30-20 on such voltage
RTT you want to run att least RZQ/7 but rather /6 for 1.6v and higher
RTT_PARK should move in the /3 range
633 if you are on 2x16
732 if you are on 4x8

724 should work beyond 1.65v
but lower procODT to 42 with higher ClkDrvStr
HWinfo you just opened on this picture - this should move around 50c if if was "real" @ this voltage

GDM also rounds your primaries , aside from tWR and tRTP
This powering you show me only looks fake ~ lying to yourself with GDM


----------



## craxton

hazium233 said:


> Don't know if I ran this correctly (default bios settings), but here is what I got with mine:
> 
> View attachment 2514044


are you running you ram overclock? or just all default ?


----------



## craxton

Iarwa1N said:


> For those who gets SIL Quality 80 from the tool @Veii has posted, try to remove any anticheat you may have and try again. I got 80, and AMD monitor tool couldn't able to read any values, so I uninstalled Faceit anticheat and the tool started working after that.
> 
> 5900x;
> View attachment 2513969
> 
> 
> I managed to get my kits running at 3600 mhz but with 1.6 vdimm. I don't know the layout of my kit, can somebody tell me if there is any dangerous RTT settings that I might be using. I don't know what to look for to not damage the memory dimms while setting the RTTs. I am trying all possible combinations to make my kit stable at or above 3600.
> 
> View attachment 2513970
> 
> 
> The settings in the picture was stable TM5 for 1 hour and I played games like 8 hours yesterday and today it is unstable, I barely make windows, how can this be possible. Even clearing cmos does not works after my windows got stuck and I had to remove sticks and reinsert them to just boot into bios. I am really tired of this kits, nothing I tried works.


sadly i searched thru my entire folder (this pc) for "anticheat" although it came up empty, i do have steam, epic, GOG, and UBISOFT all installed.
and LOADS of cracked games. however, still came back with 80 as there was nothing i could find in my pc searching folders, or the entire pc for anticheat battleeye, etc.

on another note, i ran all default settings with 4x8 and hit a whopping 89.3ns delay in aida lol..
at 2400mhz c16 speeds... goodluck with your kit.


----------



## citizenasdf

@Veii Thanks for your help with the x370 taichi suggesting the bios flash tool, i still have it  ... can you respond to the questions I have regarding memory overclock?


----------



## Iarwa1N

Veii said:


> A2 (B2) can handle this, in exchange of big instabilities
> Other ones should have been dead by now (or maybe are still alive because GDM runs them internally at half speed)


If the sticks die, does that mean they won't ever post no matter what or they can post but shows extreme unstability as in my case? Sometimes they work at XMP for days (which is only 3200mhz), and suddenly they become extreme unstable, so far as I had to remove and reinsert the sticks. 



Veii said:


> This powering you show me only looks fake ~ lying to yourself with GDM


I will try again 6/3/3 and lower procODT, I am just wondering are the timings I posted loose enough starter point for 3600 mhz? I need a starter point and I will be glad if somebody with a dual rank 3600mhz cl16 b-die can post a picture of Zentimings at XMP.


----------



## Iarwa1N

craxton said:


> sadly i searched thru my entire folder (this pc) for "anticheat" although it came up empty, i do have steam, epic, GOG, and UBISOFT all installed.
> and LOADS of cracked games. however, still came back with 80 as there was nothing i could find in my pc searching folders, or the entire pc for anticheat battleeye, etc.
> 
> on another note, i ran all default settings with 4x8 and hit a whopping 89.3ns delay in aida lol..
> at 2400mhz c16 speeds... goodluck with your kit.


Are you playing Valorant by a chance? You might need to uninstall Vanguard if that is the case.


----------



## craxton

Iarwa1N said:


> Are you playing Valorant by a chance? You might need to uninstall Vanguard if that is the case.


nope not at all, have ac valhala installed, and rust is too. but other than that...wait, valheim is as well...all 3 of these run an anticheat? or two of the 3
do....but the anti cheat isnt running....at least the service isnt. tried in safe mode, runs fine. but no gains. pretty sure, its just
a bad cpu.
(EDIT) bad core i mean chips a BEAST for undervolting. but that one core is killing it. 
turning off core 3 is something im about to give a whirl in ryzen master.


----------



## Takla

What is the math of trfc value to nanoseconds?

memclk times trfc in ns divided by 2000 equals trfc


----------



## craxton

Realized one thing, looking back at veii posting. 
That not matter what I set using 460000 or any value at all, the edc limit remains the same shown in the amd monitor. 
Perhaps there's something about this board, chip, (me) that did something somewhere that's bricked something. As the "VF" curve is nearly an arrow and says 4850 mhz needs 1.75v to hit it...can confirm I can't all core overclock to 4850 at 1.45v even. But with pbo no offset voltage, and per core adjustments I'm boosting as I should. No crashes at all now, unless I use "px auto oc" with what CTR says I can do. 

I did see 5ghz on 2 cores tho sadly only two times that happened. But still I hit it...


----------



## Taraquin

craxton said:


> nope not at all, have ac valhala installed, and rust is too. but other than that...wait, valheim is as well...all 3 of these run an anticheat? or two of the 3
> do....but the anti cheat isnt running....at least the service isnt. tried in safe mode, runs fine. but no gains. pretty sure, its just
> a bad cpu.
> (EDIT) bad core i mean chips a BEAST for undervolting. but that one core is killing it.
> turning off core 3 is something im about to give a whirl in ryzen master.


I don't think one bad core should turn sil quality to 80. I have 2 avg cores, but no real bad ones, sil quality 80 aswell. I will try stock setting to see if it changes, apex legends has anti-cheat, will try to uninstall. What is your best all core OC within 1.35V? Mine is [email protected] (but can't stress test avx due to overheat, it's stable on SOTTR/aida).


----------



## Sleepycat

XPEHOPE3 said:


> I remember previously testing it with no luck, but with changed ProcODT (rest of changes come from autotraining) now it passed failing tests from the post you quoted:
> 
> 
> Spoiler: screenshot
> 
> 
> 
> 
> View attachment 2514011
> 
> 
> 
> Temps were even greater (48.1 vs 45.5), but they will be lower with full RPM (not half like now).
> I will be running fuller tests after I bench this and see if it's good enough to stabilize. (EDIT: ofc I got 3800-16 performance (in AIDA); since I'm on GDM on, doesn't tRCD 15 behave like 16?)
> 
> Looking at your ZenTimings, it looks like for me to go from 3600 to 3800 will require a significant boost in voltage for VSOC, VDIMM, CLDO VDDP and VDDG IOD. Maybe I won't pursue it if this is the steep cliff that I need to climb for that last 200 MHz at the risk higher voltages.
> I noticed we have the same kits
> Did you see any perf gains going to GDM off + 2T?
> Also we have common "Str" settings (coming from Auto, I guess), but different CAD BUS. Did you set those by yourself or are they auto?


NIce, yes, and trying to push 64GB beyond 3600 is very tough for me. I didn't notice a difference between 1T GDM on and 2T GDM off. I went 2T since it would be more consistent in my mind since the timings would be what I set it to. 

I previously ran ClkDrvStr at 30.0, with 1.45V VDIMM with 3501 (original was 24.0 with 1.46V). The auto settings were 24/20/24/24, but I was trying to lower VDIMM a bit more.

However, with 3601, I started getting a single TM5 error with ClkDrvStr 30.0 and 1.45V. Upping the voltage to 1.46V fixed the error, and further testing showed that I could set ClkDrvStr back to 24.0 and still not have errors. So 24/20/24/24 for those settings are very similar to when you leave them as Auto.


----------



## sendap

Hi,
wonderd what I can do to improve my novice RAM Oc and ended up reading the last 150 pages of this thread. On this journey I learned a lot and tried a lot.
This is where I am right now...












Clearly visible the handwriting of @Veii 

It initially ran on ProcODT 36,9 RTT 6 3 3 but also runs stable on 34,4 6 3 4 (which was suggested to try as of 1.2.0.2). 1.44v Bios, 1.46v HWinfo

Next try was the 1T 56-56-56 hack. This also seems stable and resulted in a nice boost. No voltage adujustments required...










Where would I go from here to improve even further? My Dimms are not actively cooled and hit peak temps of 47C now. I play a bit with 14-15-14-14 up to 1.52v but
it errored out sooner or later. Most probably because not changing the rest of the timings correctly. But i guess it would get too hot anyways. Not sure.


----------



## T[]RK

Veii said:


> Please try this


Nope, got a lot errors in Test 15 and with some 0.







I also tested another timings (more tight) - same result.







And one more - same.


----------



## XPEHOPE3

Veii said:


> 633 if you are on 2x16
> 732 if you are on 4x8


Do you have a recommendation for 4*16?


Sleepycat said:


> So 24/20/24/24 for those settings are very similar to when you leave them as Auto.


I was actually interested in whether your RTTs settings were from Auto or manual, just used wrong term 😅


----------



## Robostyle

Veii said:


> Be first sure that you can even pass y-cruncher (all tests , 1-7-0)
> Then override PBO witth Scalar X1 (companies love to cheat there)
> and maybe it's just your windows which slows it down
> but it's at least 30% slower than stock, soo i think something fishy is going on
> 
> Going offset mode and adding the slightest bit of positive vcore should also fix much
> Most of the times, boardparners make their own voltage ranges ~ and only offset mode does really reset it to AMDs based scaling
> Soo a tiny offset will wipe whatever cheating was going there (too)
> 
> Check this and report back
> y-cruncher for stability needs 4 loops = 4*18min , to be anywhere near "stable"


Here it is - obviously, I had to revert back to 3800mem:1900fclk.


Spoiler: Cruncher















SOC 1.2V, vddp 1.05V, CCD ~0.99V, IOD 1.1V, vDDR 1.45V, PBO scalar x1, vCore +250mV offset.
Going with +0.8V offset changes nothing, judging from HWInfo vCore goes up to 1.54V - if it is actually that much, then its another shady thing from asus, since I have everything related to CPU set on Auto, even LLC.


P.S. By the way, cruncher instantly crushes when I try to push it at 1.1V SOC, whereas I'm completely stable in everything else - the same aida stresstest and scores, HCI memtest 200% stable, no whea errors too

P.S.S. Does low vDDR cause whea interconnect erros aswell? I've just noticed that raising DRAM voltage helps me to get rid of whea at 3800:1900, while memory tests show full stability and no corrupt data at low vDDR


----------



## mongoled

PJVol said:


> Seems to have found the reason for stretching (or not stretching) clocks from boot to boot. Dont know how it exactly works, but after decreasing all CO values (abs) by 3-5, clocks normalized. Can't explain that phenomena atm, other than some static V/F curve formed at boot stage, taking current temps, power limits, etc into account, and used later by some DFS functionality. So when ambient temp rises, given that OC-ed DF cut a decent part off of a CPU total power budget, there's just lack of boosted P-states to met the "trained" conditions at high allcore load for the frequency the "dynamic" algorithm requested . Which condition exactly? I assume its the power, because temps are higher with lower abs. CO values (for obvious reasons), but the perfomance was not degraded at least, despite clocks shown are lower on average.
> To put it simple - I see it as the "power clock stretching", similarly to "VID clock stretching" caused by low negative Vcore global offset
> 
> PS: Although, I realize that all of the above might turn out complete bulls**t, lol, it would be nice to hear any expert opinion about that ))


Gremlins, just Gremlins, actually Ryzen Gremlins, more and more of them, the further you look into Ryzen, the more you prod and probe the more Gremlins appear

😂 😂


----------



## craxton

Taraquin said:


> I don't think one bad core should turn sil quality to 80. I have 2 avg cores, but no real bad ones, sil quality 80 aswell. I will try stock setting to see if it changes, apex legends has anti-cheat, will try to uninstall. What is your best all core OC within 1.35V? Mine is [email protected] (but can't stress test avx due to overheat, it's stable on SOTTR/aida).


i cant get windows to load 48 with 1.4 so you can do the math lol...
my best "cores" are 147 worst is 131 and 134 (with pbo on)
(perhaps where i simply copied and pasted most my "bought" games from steam etc to another drive
the anti cheats are interacting that way. since well, there in there somewhere.

none the less, installing a os on a new drive just to test out and see.
will turn off most other drives to check.
dont know why this "tool" is buggin me... im running a 4x8 set that most others
still cant do.... not the tightest timings granted but still....no whea 19 lol...
18 sure always acpi 6 (core 3) which is exactly what my worst core is.

the only reason i believe something to not be correct is due to the sheer fact i can run 47.50 all core with 1.35
(first agesa release for this board) i was running 4.8 at 1.375 so im unsure if the settings i had before
have degraded somehow) have lowered SOC, IOD, CCD by well, from 1070 iod to 990, its on the overclock sheet.
(i was 100% whea free at that time) never had any CO offsets, nor did i overclock the cores)

EDIT actually running 4800 all core oc now, with 1.35v core....
so im assuming was a setting somewhere i had turned when i was fiddling with the bios.
still the "TOOL" says 80 sil score.


----------



## PJVol

mongoled said:


> Gremlins, just Gremlins, actually Ryzen Gremlins, more and more of them, the further you look into Ryzen, the more you prod and probe the more Gremlins appear


Yeah, kinda...)
And not to deal with'em anymore, I decided to give up finding 24/7 fclk 2000 config. Too much mess and too little officially available info when diving too deep )


----------



## Theo164




----------



## Art385

craxton said:


> for whatever reason, i thought you was running a higher core count chip,
> and seen PJvol shot after posting this.
> 
> to which i pressed "get sil" around 100x or so trying many many different things and its sadly 80.
> possibly lower but maybe the tool doesn't go lower than 80 by default.
> gotta great IMC but the OC ability is horrific. which explains why i have such a hard time getting CO dialed in
> all cores but one runs fine with -20 +50mv offset.to which that "one" core needs a + value to which will not boost
> to 4.85 past +7
> 
> (off topic of tool) on topic of CO,
> have you or anyone else noticed that core cycler, will pass cores running all FFT sizes thru multiple iterations,
> then you go change one core value for "CO" and go test again, and the testing fails what was "stable" for a core
> that was "stable"?
> is that how its supposed to be, or is this positive value impacting another core somewhere?


You don't even have to change CO all it takes is to turn off pc. Turn on PC retest and cores will fail it's like V/F shift at every boot. I even extended test to 12 minutes did 6 iterations super stable. Turn off PC retest and got rounding error lol. Scalar seems to helps as it counters a little voltage drop with +12mv global offset but i think that on failing cores i will just do like -2 offset and call it a day. Best thing that one of the cores that are failing frequently is "150" other "139" and core that is 127 is quite fine all the time xD


----------



## jcpq

HI
I have a 16gb(2x8gb) kit overclocked at [email protected]
I want to buy a 32gb kit (2x16gb) and I would like to know your opinion about a model that is good at overclocking, for something like [email protected]
Any suggestions?


----------



## CarnageBT

I've been testing the 1 bad stick and have beat my head against the wall trying to find stable settings for it at 3733.

This morning I dropped to 3667 and it passed 25 cycles, no errors. From there, I've started following this guide, integralfx/MemTestHelper, on tightening timings.

Surprisingly, everything I've changed, (1 at a time), has passed. It almost seems wrong lol. Is this testing useful (aka, find the lowest possible settings on my weakest stick), or is it somewhat fruitless/waste of time, as once I put all 4 sticks in, many of theses settings that worked on the single stick, may no longer work or be valid.

As of now, I'm following the guide, making single changes and testing along the way with my SINGLE weakest stick.

Appreciate the info, if I should continue, or put the other sticks back in before going forward. Thank you!


----------



## hazium233

craxton said:


> are you running you ram overclock? or just all default ?


That was XMP basically (although I typed FAW in a little lower), with sku limits (PBO - Auto / disabled). Power limits or SOC power affect the result?


----------



## hazium233

I don't think there is a Ryzen Cache Stability thread, so will ask here. I was testing various PBO limits at just XMP to get a handle on what did what, and saw the L3 changes with EDC.

Board has 220 EDC limit, and more or less that gave the largest numbers in AIDA. CB20 runs were showing ~122A effective EDC based on percentage vs set limit, which I suppose jives with other observations for the 5600X.

But which real world workloads benefit from setting EDC high for cache numbers? Something mostly multicore like CB20 seems to prefer riding a little lower EDC than 122 which may in part be due to temperature I suppose. edit: hmm actually I need to test PPT with EDC up and see if that works.


----------



## craxton

@Veii 
curious to know since you state that your VF curve is broken, due to a CTR version
in which (i was using at that time) i just cant recall which one it was. and to lazy to go back and check atm.

here is what mines looking like....(that CTR version you mentioned at the time, was the first and only version 
i had tried uptill a few days ago, to which extent 4800mhz all core at 1.35 should yeild better results than what i get..
sure its irrelevant. but trying to solve whats the cause of this "block" in the readout and rule out all 
outcomes as such.


----------



## Pictus

Veii said:


> GDM also rounds your primaries , aside from tWR and tRTP
> This powering you show me only looks fake ~ lying to yourself with GDM


Interesting, Photoshop likes GDM








Ryzen 5000 RAM Guide: Find The Best RAM For Your Zen 3 CPU


We decipher the best memory frequency and configuration to unleash your Zen 3 processor's full potential.




www.tomshardware.com


----------



## CarnageBT

@mongoled @Veii

I finally got something stable. It passed 5 iterations of the whole y cruncher suite, and passed 25 iterations on TM5 1usmus. *FINALLY!*

I really don't understand the powering options well enough but it was the AddrCmdSetup timing that finally got everything to work. Tried 56-56-56, error after 2 hrs, 56-0-0, success.... finally!

I'll try adding that setup timing on some faster settings later but for now, this is what I finally got stable. Let me know your thoughts, if anything looks to be easily improved, etc.. 

I think my voltage / power settings need some work. I need to look the method and tools used to fine tune them. I've read that certain tests, aida, etc., and certain items within the tests, ie, latency, read / write speeds, allow you to fine tune the voltages. I'm going to look this up. I know my aida latency is no good, moves from 55.6-55.9, so 0.3ns, which I recall reading earlier implied something is off... ProcODT maybe?

Thank you very much for both of your help 🙏


----------



## craxton

hazium233 said:


> That was XMP basically (although I typed FAW in a little lower), with sku limits (PBO - Auto / disabled). Power limits or SOC power affect the result?


I've found nothing to "get higher scores". Unsure about the dpm clock settings. But
Don't believe they were mentioned in a way that made it "test" better. As I'm sure yours are on auto?

I doubt soc affects it, from the looks of Veii SOC voltage he's running 1.2v but, 
I didn't look at the power report it stated either. @Veii @PJVol @mongoled 
(what is you SOC power at a "given" range? or does what im asking not make sense?

I can't much test DPM clock as I have 8 clocks to set, and I'm not to sure what is what.
Only see well less than that mentioned. It almost. 
makes sense, since cores can too, but I wonder if 1.2soc on one chip could have less power draw? 
Vs 1.8x on another?
Turning off 200mhz auto oc and performance boost still gives the same 80 score.
Did lower score per core down tho. 692.5 instead of over 800...Quite the margin....


----------



## ManniX-ITA

Pictus said:


> Interesting, Photoshop likes GDM


I wouldn't trust an article about memory timings that doesn't show in detail the timings that were used to test 

For me that result only show how bad the 1T and 2T profiles were set.
Which makes completely unreliable the whole set of benchmarks presented in the article.



CarnageBT said:


> Let me know your thoughts, if anything looks to be easily improved, etc..


Did you compare it with the same with GDM enabled?

I would test with SCL at 4 instead of 2.
Also RRD at 4/4 not always is better, test 4/6 as well.
Same for WTR; test 3/8 and 4/10. I had better results with those than 4/8.


----------



## mongoled

CarnageBT said:


> @mongoled @Veii
> 
> I finally got something stable. It passed 5 iterations of the whole y cruncher suite, and passed 25 iterations on TM5 1usmus. *FINALLY!*
> 
> I really don't understand the powering options well enough but it was the AddrCmdSetup timing that finally got everything to work. Tried 56-56-56, error after 2 hrs, 56-0-0, success.... finally!
> 
> I'll try adding that setup timing on some faster settings later but for now, this is what I finally got stable. Let me know your thoughts, if anything looks to be easily improved, etc..
> 
> I think my voltage / power settings need some work. I need to look the method and tools used to fine tune them. I've read that certain tests, aida, etc., and certain items within the tests, ie, latency, read / write speeds, allow you to fine tune the voltages. I'm going to look this up. I know my aida latency is no good, moves from 55.6-55.9, so 0.3ns, which I recall reading earlier implied something is off... ProcODT maybe?
> 
> Thank you very much for both of your help 🙏
> 
> View attachment 2514120
> 
> 
> View attachment 2514119


What ManniX-ITA said,

tRDRDSCL/tWRWRSCL should be 4 or 5 when using 32GB, 2 or 3 when using 16GB (this is valid for bdie, for other modules I am unsure ...)

Otherwise good job!

Though why didnt you stick with tRDCRD @16 and work from that?

I am assuming your bad stick was stable using tRCDRD @16.

I would have used that as the lowest donominator and pushed frequency up, im confident its going to be better performing in your use case scenario than 3666 flat14s, as to how much difference you would have to test with your games.

But as you have really fought to get to where you are you could just use your PC for what you built it for and maybe return to tweaking at a later time.

For the record I would have aimed for 3800/1900 14-16-14-14, all your other settings dont need to be changed apart from what ManniX-ITA said then just bump it to 3733/1866 and bump vDIMM to 1.5v, do a quick test, if it fails then fall back to your working set, if it does not fail aim for 3800/1900.


----------



## Insidious Supra

To infinity and beyond. (was showing 118-120 not sure what happened) Lol, working on another setup for these 4400 sticks. My last tune was pretty lackluster

These have been kinda funky. Two different patriot b die 2x8gb kits for 4 stick total on a t-topology board. I'd expect my dimm temps to get higher with these resistances and voltage, but I am only seeing 32C with my semi-custom air cooler. Only about half-way thru with adjustments.


----------



## T[]RK

mongoled said:


> tRDRDSCL/tWRWRSCL should be 4 or 5 when using 32GB, 2 or 3 when using 16GB (this is valid for bdie, for other modules I am unsure ...)


I am unable to run 2-2 or 3-3 on my config (2x 8GB B-die). With 3-3 i got Error in test 4 (PCB crash) at 4th cycle and with 2-2 i got error in test 5 at 11 cycle. 2-2 act better, but i am unsure where to dig. Error description say that it may be tRDWR\tWRRD, but that's combination to try (currently i got 8-1)? Or maybe i can calculate them somehow?


----------



## XPEHOPE3

Does anyone know what this y-cruncher error means? CPU is 5600x PBO with motherboard limits









I was using RDP from my PC to the tested PC at the time (if that matters)

I'm currently tightening timings and lowering voltage for this config:
















TestMem5 1usmus_v3 stopped cycling by itself after 18-th cycle (previously it also stopped after 8 cycles, then after 9 cycles...)
Temps were up to 47.5

BTW with tRRDS/tRRDL/tFAW 6/9/24 and tRDWR 9/8 (different timings on A/B channels) it won't pass 1usmus_v3 with multitude of mostly MirrorMove errors (mostly 3,7, some 0,1,4,etc).



T[]RK said:


> Or maybe i can calculate them somehow?


Through Ryzen Google Calculator maybe?


----------



## mongoled

T[]RK said:


> I am unable to run 2-2 or 3-3 on my config (2x 8GB B-die). With 3-3 i got Error in test 4 (PCB crash) at 4th cycle and with 2-2 i got error in test 5 at 11 cycle. 2-2 act better, but i am unsure where to dig. Error description say that it may be tRDWR\tWRRD, but that's combination to try (currently i got 8-1)? Or maybe i can calculate them somehow?


Ive never experienced boarderline instability when playing with these values, just loss in memory throughput. However I have experienced no post scenario when experimenting with different values back in the day.

So unsure how to advise, are you sure the error are a directly linked to your changing the SCLs ??



XPEHOPE3 said:


> Does anyone know what this y-cruncher error means? CPU is 5600x PBO with motherboard limits
> 
> View attachment 2514132
> 
> I was using RDP from my PC to the tested PC at the time (if that matters)
> 
> I'm currently tightening timings and lowering voltage for this config:
> View attachment 2514133
> View attachment 2514139
> 
> 
> TestMem5 1usmus_v3 stopped cycling by itself after 18-th cycle (previously it also stopped after 8 cycles, then after 9 cycles...)
> Temps were up to 47.5
> 
> BTW with tRRDS/tRRDL/tFAW 6/9/24 and tRDWR 9/8 (different timings on A/B channels) it won't pass 1usmus_v3 with multitude of mostly MirrorMove errors (mostly 3,7, some 0,1,4,etc).
> 
> 
> Through Ryzen Google Calculator maybe?


TM5 stopping cycling is usually caused by one of the cores not getting enough voltage, which could also be the reason you are getting the Y-Cruncher error, re-evaluate you PBO, CO settings using core-cycler and than after verify with Y-Cruncher...


----------



## ManniX-ITA

XPEHOPE3 said:


> TestMem5 1usmus_v3 stopped cycling by itself after 18-th cycle (previously it also stopped after 8 cycles, then after 9 cycles...)


I have no experience with 4xDR, it can be though...
For my kit it dying like that was more an issue with rRRD_S/L and tRDWR/tWRRD.
Wouldn't know what to suggest for 4 sticks.
Don't run y-cruncher till you are 100% sure the memory setting is 100% fine.
Would be best to not use any PBO or CO till you know for sure.



T[]RK said:


> I am unable to run 2-2 or 3-3 on my config (2x 8GB B-die). With 3-3 i got Error in test 4 (PCB crash) at 4th cycle and with 2-2 i got error in test 5 at 11 cycle. 2-2 act better, but i am unsure where to dig. Error description say that it may be tRDWR\tWRRD, but that's combination to try (currently i got 8-1)? Or maybe i can calculate them somehow?


I'd suspect the tRDWR/tWRRD, not sure if it can be calculated.
Did you try with 8/3?


----------



## T[]RK

mongoled said:


> So unsure how to advise, are you sure the error are a directly linked to your changing the SCLs ??


Yes, exatly SCL. I have stable profile (tested it with 25 cycles) and now changed only two SCL values. It's clearly they are cause error.

Here is my last post with stable config:








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Here is mine but to get no errors running Blender or Cinibench I need 1.3125v at 46.5 46. I tried 1.35v at 47/46.5 and Blender would stop responding and sometimes Cinebench would error out. :(




www.overclock.net







ManniX-ITA said:


> I'd suspect the tRDWR/tWRRD, not sure if it can be calculated.
> Did you try with 8/3?


Yes, but didn't remember for which combination 2-2 or 3-3. I saw error in event viewer of dwm.exe and KENRNELBASE.DLL and Dwminit after saw flickered screen, so i didn't even started TM5. System was already unstable.


----------



## XPEHOPE3

ManniX-ITA said:


> Don't run y-cruncher till you are 100% sure the memory setting is 100% fine.


I saw @Veii suggesting somewhere to use y-cruncher to test if FCLK is fine at certain voltages
*before* running 1usmus_v3 test, that's why I ran it in that order.


ManniX-ITA said:


> Would be best to not use any PBO or CO till you know for sure.


And what to use then? All-core OC or none at all? I'm on stock settings CPU-wise
(apart from using motherboard limits). Thought it should be safe. If it's not, why are you sure
no PBO (+no CO) at all would be safe?


mongoled said:


> TM5 stopping cycling is usually caused by one of the cores not getting enough voltage


I searched some more and saw these solutions, arguably more believable since the cycling
ends exactly after the last test when TM5 needs to reallocate memory anyway:

disconnect from internet to prevent updates
stop multitasking on PC being tested
EDIT: (ru) stop background processes, especially GPU monitoring
What would be your and @ManniX-ITA takes on these explanations?


mongoled said:


> one of the cores not getting enough voltage, which could also be the reason you are getting the Y-Cruncher error, re-evaluate you PBO, CO settings using core-cycler


Can it be because my (only) CCD2 becomes 87.3C hot during y-cruncher?
Also I'm not on CO, so I believe I shouldn't use it yet.


----------



## craxton

Insidious Supra said:


> To infinity and beyond. (was showing 118-120 not sure what happened) Lol


lol thats nothing, turn on CTR with some OB ranges of some sort, youll see 
that the test goes -13e0480945860+e


----------



## hazium233

craxton said:


> I've found nothing to "get higher scores". Unsure about the dpm clock settings. But
> Don't believe they were mentioned in a way that made it "test" better. As I'm sure yours are on auto?


Yes, nearly everything on "Auto" except for fan speeds, set XMP, some manual typing for timings to make sure. I think I had even left PBO - Auto, which works correctly as sku limit. VRM all Auto. 

Power states are certainly active, this showed up in the monitor with fabric clock going down when doing nothing. Moving mouse, it would go back to 1600, heh.

I don't know if the tool is testing the VF curve directly, or if that came from fitness values or other values programmed into the chip that are read in the monitor.

I just ran this for another data point if anybody needed it.

*edit SOC on Auto is only 1.000 at this speed, so power from that stays fairly low. < 6 W in hwinfo.


----------



## T[]RK

ManniX-ITA said:


> Did you try with 8/3?


I run test with tRDRD/tWRWR_SCL=2 and tRDWR/tWRRD=8-3
Error in test [email protected] 8 + BSOD after i stopped TM5 with error Internal Power Error. Event viewer got Kernel-power Code 41.


----------



## CarnageBT

ManniX-ITA said:


> I wouldn't trust an article about memory timings that doesn't show in detail the timings that were used to test
> 
> For me that result only show how bad the 1T and 2T profiles were set.
> Which makes completely unreliable the whole set of benchmarks presented in the article.
> 
> 
> 
> Did you compare it with the same with GDM enabled?
> 
> I would test with SCL at 4 instead of 2.
> Also RRD at 4/4 not always is better, test 4/6 as well.
> Same for WTR; test 3/8 and 4/10. I had better results with those than 4/8.


I have changed SCL to 4. I can do some aida testing. Is there a specific type of testing you recommend for trying out those variations? RDD 4/4 vs 4/6 and WTR 3/8 or 4/10 vs 4/8



mongoled said:


> For the record I would have aimed for 3800/1900 14-16-14-14, all your other settings dont need to be changed apart from what ManniX-ITA said then just bump it to 3733/1866 and bump vDIMM to 1.5v, do a quick test, if it fails then fall back to your working set, if it does not fail aim for 3800/1900.


Well... since I'm in testing mode, I'll try this because once I finish, I'm going to be doing a clean install of windows as I'm pretty sure I've messed up the current one lol.
Should I try the single weak stick at 14-15-14-14 first, then if fails, try 14-16-14-14 ?


----------



## craxton

@wuttman
this is that c14 4000 i told you about, (not the 100% stable config) and my voltage was
WAY LOWER and the timings well everything is auto. NOTE not the stable c14 @4000 config i had.
took out two sticks to see if that made any difference within the sil test on tool.exe but nope.










amd this is 4x8, with everything preset, but SOC is on auto....
passes stress tests at that....?


----------



## ManniX-ITA

T[]RK said:


> I run test with tRDRD/tWRWR_SCL=2 and tRDWR/tWRRD=8-3
> Error in test [email protected] 8 + BSOD after i stopped TM5 with error Internal Power Error. Event viewer got Kernel-power Code 41.


You need probably to test more combinations... did you try SCL at 4? What is the difference in AIDA bandwidth?
Not sure maybe @Veii can help.



CarnageBT said:


> I have changed SCL to 4. I can do some aida testing. Is there a specific type of testing you recommend for trying out those variations? RDD 4/4 vs 4/6 and WTR 3/8 or 4/10 vs 4/8


Basic check with AIDA, especially bandwidth.
Then I use SOTR benchmark, DRAM Calc benchmark and Sandra Core Efficiency test.


----------



## T[]RK

ManniX-ITA said:


> You need probably to test more combinations... did you try SCL at 4?


Here is my stable config (without errors) and it's with SCL=4.








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Here is mine but to get no errors running Blender or Cinibench I need 1.3125v at 46.5 46. I tried 1.35v at 47/46.5 and Blender would stop responding and sometimes Cinebench would error out. :(




www.overclock.net





Here is current bandwidth with SCL=4


----------



## ManniX-ITA

XPEHOPE3 said:


> I saw @Veii suggesting somewhere to use y-cruncher to test if FCLK is fine at certain voltages
> *before* running 1usmus_v3 test, that's why I ran it in that order.


y-cruncher is doing calculations, if there's something wrong with the memory it will error
same as Prime95 or OCCT or any other CPU test
if you want to test the FCLK with y-cruncher do it only after you are 100% sure the memory is rock solid
Erroring so late at the 7th cycle points to a memory issue



XPEHOPE3 said:


> And what to use then? All-core OC or none at all? I'm on stock settings CPU-wise
> (apart from using motherboard limits). Thought it should be safe. If it's not, why are you sure
> no PBO (+no CO) at all would be safe?


Just stock settings with PBO and CO disabled
PBO with motherboard limits is definitely not safe, not even in Auto is safe
No static OC of course unless you set a very low frequency
At stock with PBO and CO disabled it's the best way to be sure the memory profile works properly
When you are sure you can factor in also the CPU
But if you still get errors go back to the XMP profile and check again
Cause if you still get errors with all stock and XMP something is off and maybe you need to RMA something



XPEHOPE3 said:


> What would be your and @ManniX-ITA takes on these explanations?


TM5 dying at the end of the cycle for me was almost always as above
It's a bad error, the thread testing the memory just dies
Indeed you should not use the PC while TM5 is running
It's very delicate and if some other program is running and messing with the memory allocation it will crash or die
Usually I just browse with Firefox which I opened before starting TM5 and it doesn't cause issues
But it's risky...



XPEHOPE3 said:


> Can it be because my (only) CCD2 becomes 87.3C hot during y-cruncher?
> Also I'm not on CO, so I believe I shouldn't use it yet.


That's a normal temperature for y-cruncher


----------



## ManniX-ITA

T[]RK said:


> Here is my stable config (without errors) and it's with SCL=4.
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Here is mine but to get no errors running Blender or Cinibench I need 1.3125v at 46.5 46. I tried 1.35v at 47/46.5 and Blender would stop responding and sometimes Cinebench would error out. :(
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> Here is current bandwidth with SCL=4
> View attachment 2514151


Wow it's really really slow for that profile at 3800 and a 5800x... do you get a better result with SCL 2?
Also, did you compare with GDM enabled?
There's something really off; tRTP/tWR are probably too low at 5/10. Try with them at 8/16.
I also suspect you are starving voltage, set SOC at 1.12V and CCD/IOD at 1050mV, check if you get a performance bump.


----------



## sendap

ManniX-ITA said:


> Wow it's really really slow for that profile at 3800 and a 5800x


Read MB/s look ok, Write MB/s definately 1500 or 2000 MB/s too slow.

This is the best i could do on a 5800X


----------



## CarnageBT

mongoled said:


> For the record I would have aimed for 3800/1900 14-16-14-14, all your other settings dont need to be changed apart from what ManniX-ITA said then just bump it to 3733/1866 and bump vDIMM to 1.5v, do a quick test, if it fails then fall back to your working set, if it does not fail aim for 3800/1900.


Thank you for this advice. It seems a little lack luster to have put in the amount of hours I have to walk away with 3666 lol.

Just tried 3800/1900 with my single bad stick using same settings + tRCDRD 15 and 1.5vdimm and passed 25 TM5 cycles!

Now testing with the full 4 dimms back in and running another 25 cycles of TM5. _Fingers crossed_


----------



## craxton

More on this (AUTO SOC) ran TM5 25 cycles while i was way installing 
a timing chain, and fan belt tensioner pully on my ol ladies dads car.

now im back, the tests done, have ran AIDA with "most" services i usually disable manually 
to run benchmarks could have turned off a few more but causes problems sometimes.
(ran aida 4 times, while TM5 was open score was an entire 53.5 while without it, the other 3 runs (without zen timings open) 
are as shown with the other two shots...

i thought others were stating auto soc was 1.2v at 4000mhz. 
none the less, if auto can run at this ill know shortly with y-cruncher. (well, later tonight) 
its way to hot. (have limited to 4.8ghz pbo boost) as its easier to run -30 offset.


----------



## PJVol

sendap said:


> Read MB/s look ok, Write MB/s definately 1500 or 2000 MB/s too slow


He's "MB/s" absolutely ok. Latency is not, lacking ca. 3ns


----------



## CarnageBT

I feel like I'm so close but just missing a tiny detail to achieve stability on 3800/1900. Below are the settings as well as some tests, and results. I seem to be getting error 8 on my best runs (~50m - 1hr before the error).

If anyone has any insight or idea, please share. Thank you











*Tested with single WEAKEST stick*Pictured, 1.48vdimm16 cycles, 42m, error 21.5 vdimmpassed 25 cycles*All 4 DIMMs populated*Picturedcycle 9, ~ 55m, error 81.52 vdimmcycle 5, ~ 25m, error 12Pictured, tWTRL 10 (from 8)cycle 7, ~40 mins, error 0tRRD 4/6 + tWTRL 10 (from 8)cycle 4, ~ 23, error 7, then 11, 12, 1 through 37mPictured, tCKE 9cycle 1, error 8, 8, 8, 8,tCKE 9 + CsOdtSetup CkeSetup 56-56-56cycle 8, ~50m, error 1, ran for 65m, no other errorsPictured, tCKE 1 + CsOdtSetup CkeSetup 56-56-56cycle 11, ~70m, error 7, ran for 80m, no other errors1.51 vdimm2 Cycles, ~20m, error 7, 7, ran for 35m1.49 vdimmtesting nowIDEAS for next testsPictured - tRRD 4/6. didnt' try tRRD alone. only in combo with tWTRL 10Pictured, ClkDrvStr 60considering re-doing tras (tcl+twr=26), and fixing tRFC values OR tRAS = 29 and fix tRFC values up 1vsoc 1.125 // .94 ccd


----------



## KedarWolf

CarnageBT said:


> I feel like I'm so close but just missing a tiny detail to achieve stability on 3800/1900. Below are the settings as well as some tests, and results. I seem to be getting error 8 on my best runs (~50m - 1hr before the error).
> 
> If anyone has any insight or idea, please share. Thank you
> 
> View attachment 2514192
> 
> 
> 
> *Tested with single WEAKEST stick*Pictured, 1.48vdimm16 cycles, 42m, error 2*1.5 vdimm**passed 25 cycles**All 4 DIMMs populated*Pictured*cycle 9, ~ 55m, error 8*1.52 vdimmcycle 5, ~ 25m, error 12Pictured, tWTRL 10 (from 8)cycle 7, ~40 mins, error 0tRRD 4/6 + tWTRL 10 (from 8)cycle 4, ~ 23, error 7, then 11, 12, 1 through 37mPictured, tCKE 9cycle 1, error 8, 8, 8, 8,tCKE 9 + CsOdtSetup CkeSetup 56-56-56*cycle 8, ~50m, error 1, ran for 65m, no other errors*tCKE 1 + CsOdtSetup CkeSetup 56-56-56currently testing


Try tRCDRD at 16.


----------



## CarnageBT

KedarWolf said:


> Try tRCDRD at 16.


It should work at 16. I just don't want to give up the timing lol. In the end I may have to, but hopefully I can figure out the little detail to make this work


----------



## KedarWolf

CarnageBT said:


> I feel like I'm so close but just missing a tiny detail to achieve stability on 3800/1900. Below are the settings as well as some tests, and results. I seem to be getting error 8 on my best runs (~50m - 1hr before the error).
> 
> If anyone has any insight or idea, please share. Thank you
> 
> View attachment 2514192
> 
> 
> 
> *Tested with single WEAKEST stick*Pictured, 1.48vdimm16 cycles, 42m, error 2*1.5 vdimm**passed 25 cycles**All 4 DIMMs populated*Pictured*cycle 9, ~ 55m, error 8*1.52 vdimmcycle 5, ~ 25m, error 12Pictured, tWTRL 10 (from 8)cycle 7, ~40 mins, error 0tRRD 4/6 + tWTRL 10 (from 8)cycle 4, ~ 23, error 7, then 11, 12, 1 through 37mPictured, tCKE 9cycle 1, error 8, 8, 8, 8,tCKE 9 + CsOdtSetup CkeSetup 56-56-56*cycle 8, ~50m, error 1, ran for 65m, no other errors*tCKE 1 + CsOdtSetup CkeSetup 56-56-56currently testing


Try Nom/Wr/Park 0/3/1?

Edit: And it might be a memory temp issue, fan over memory?

See here about fan frame and high end fans. At 3000RPM they are silent, at my 6800 RPM a bit noisy but don't bother me over my headset, is amazing for my RAM stability.









MSI MEG X570 Unify Overclocking & Discussion Thread


Need help, I'm not sure what I have done wrong. In Bios A85 @ IF1900 and RAM3800Mhz I could only get up to PBO 25% and -15 Curve on all cores, any higher resulted in WHEA errors Now on Bios A86 @ IF1900 and RAM3800Mhz I can get PBO 200% and -20 Curve (I have tested for 40mns in OCCT with no...




www.overclock.net


----------



## XPEHOPE3

CarnageBT said:


> If anyone has any insight or idea, please share


Are you sure about tRP? This calculator recommends tRCD Max for it (which is 15 for you). Ofc with consequences for tRAS, tRC, tRFC...
Also did you try to relax tRRD_, tWTR_, tFAW according to this Veii's post? (starting from "Compare these two results")


----------



## CarnageBT

KedarWolf said:


> Try Nom/Wr/Park 0/3/1?
> 
> Edit: And it might be a memory temp issue, fan over memory?
> 
> See here about fan frame and high end fans. At 3000RPM they are silent, at my 6800 RPM a bit noisy but don't bother me over my headset, is amazing for my RAM stability.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> MSI MEG X570 Unify Overclocking & Discussion Thread
> 
> 
> Need help, I'm not sure what I have done wrong. In Bios A85 @ IF1900 and RAM3800Mhz I could only get up to PBO 25% and -15 Curve on all cores, any higher resulted in WHEA errors Now on Bios A86 @ IF1900 and RAM3800Mhz I can get PBO 200% and -20 Curve (I have tested for 40mns in OCCT with no...
> 
> 
> 
> 
> www.overclock.net


Updated my testing chart. I am considering dropping RttPark to 1, 7-3-1, or possibly increasing my ClkDrvStr to 60 from 40. I have theses ideas noted for my future tests at the bottom of the chart. I'm literally just shooting in the dark for the most part.

If I had better knowledge, I would key in on what differs when going from 1 dimm to 4 dimms. As I have identified my weakest dim, and it passed the pictured zentimings settings for 25 cycles, so I know it's not my dimms, but rather the settings that need to be changed to accommodate the change from 1 to 4 dimms; power settings, which I have very weak understanding of, or very basic.


----------



## CarnageBT

XPEHOPE3 said:


> Are you sure about tRP? This calculator recommends tRCD Max for it (which is 15 for you). Ofc with consequences for tRAS, tRC, tRFC...
> Also did you try to relax tRRD_, tWTR_, tFAW according to this Veii's post? (starting from "Compare these two results")



Thanks for the info. I will give it a read. Hope to find good insights


----------



## XPEHOPE3

@CarnageBT 
also you can check timings in ZenTimings for A2 and B1 sticks. There can be differences if you use Auto somewhere. E.g. for my 4*16 B-die I have tRDWR 9 and 8 jumping between chA and chB from one training to another.


----------



## craxton

@ManniX-ITA
quick question, i was checking the EDC bug thread. noticed noone (that i found)


Spoiler



state 5000 chips values and what not.
i seen Veii values the other day with the "tool" monitor for his 5600x.
as i now have most values changed all together than what i did have, i have EDC set to 1
260,420,1 and....nothing is showing signs of it being locked at 1.

would AIDA show this limit?? as bench scores i think in L3 is slower??
(if its been found i wouldnt know) read loads on it but last i seen was people using R20 to test

(hwinfo shows 60amps) BUTTTTT
with me manually setting 260,420,420 in bios
with same settings else where. i get well bottom score is what i manually set (best score id gotten EVER at that time)
(also note that i had NO CHROME RUNNING no razer software, no hwinfo (literally barebones stuff even anti-virus was off for that run)

now the "best score you see on this top shot" is while chromes running, hwinfo...all my normal startup stuff plus chrome running
(hwinfo still shows max 60a) so if i trigger this bug would it not show that in hwinfo being more than 60a?
or would i simply get better scores?

(EDIT) maybe its 90A and im not thinking clearly trying to keep busy with my gpaw leaving...









this is without anything running in the back
(im unclear if itll go over 60A normally.)
all core boosting seen 4.7


----------



## mongoled

CarnageBT said:


> I feel like I'm so close but just missing a tiny detail to achieve stability on 3800/1900. Below are the settings as well as some tests, and results. I seem to be getting error 8 on my best runs (~50m - 1hr before the error).
> 
> If anyone has any insight or idea, please share. Thank you
> 
> View attachment 2514192
> 
> 
> 
> *Tested with single WEAKEST stick*Pictured, 1.48vdimm16 cycles, 42m, error 21.5 vdimmpassed 25 cycles*All 4 DIMMs populated*Picturedcycle 9, ~ 55m, error 81.52 vdimmcycle 5, ~ 25m, error 12Pictured, tWTRL 10 (from 8)cycle 7, ~40 mins, error 0tRRD 4/6 + tWTRL 10 (from 8)cycle 4, ~ 23, error 7, then 11, 12, 1 through 37mPictured, tCKE 9cycle 1, error 8, 8, 8, 8,tCKE 9 + CsOdtSetup CkeSetup 56-56-56cycle 8, ~50m, error 1, ran for 65m, no other errorsPictured, tCKE 1 + CsOdtSetup CkeSetup 56-56-56cycle 11, ~70m, error 7, ran for 80m, no other errors1.51 vdimm2 Cycles, ~20m, error 7, 7, ran for 35m1.49 vdimmtesting nowIDEAS for next testsPictured - tRRD 4/6. didnt' try tRRD alone. only in combo with tWTRL 10Pictured, ClkDrvStr 60considering re-doing tras (tcl+twr=26), and fixing tRFC values OR tRAS = 29 and fix tRFC values up 1vsoc 1.125 // .94 ccd


Has Eder provided a modified BIOS for your motherboard ?






Bios Mods - Google Drive







drive.google.com





If your BIOS is using an agesa higher than 1.1.9.0 you should disable "DF C-States" found in

Advanced --> AMD CBS --> NBIO Common Options --> SMU Common Options

Though as explained its only in modded BIOS

Good job btw, seems like we are in the same position, one weak stick


----------



## ManniX-ITA

@craxton 
If you can I'd really appreciate if you could write more polished and structured...
Apologize but I'm not native in English and I really struggle to understand what you say even reading it multiple times 

So far I've not seen anyone having success with the EDC bug and a 5000.
If you get higher scores and the EDC limit to high percentage (like the 6752.2% in your screenshot) then it's working.
Is that a better score than the usual?
If so what AGESA version are you using?


----------



## ManniX-ITA

mongoled said:


> If your BIOS is using an agesa higher than 1.1.9.0 you should disable "DF C-States" found in
> 
> Advanced --> AMD CBS --> NBIO Common Options --> SMU Common Options


Wasn't disabled by default in 1.2.x AGESA versions? 🤔


----------



## mongoled

ManniX-ITA said:


> Wasn't disabled by default in 1.2.x AGESA versions? 🤔


Im quite confident Veii said to disable this in agesa after 1.1.9.0.

Below is my stable set, rock stable on 1.1.9.0 and now rock stable on 1.2.0.3a

Before setting "DF C-States" to disabled I would sometimes get no errors and then sometimes get errors after test 20 that were not consistent with no pattern, i.e. one run would give me an error 3,4 and another run an error 7/8, after setting "DF C-States" to disabled ive done two runs with the system being powered down for several hours before the second run and its passed both times....


----------



## ManniX-ITA

mongoled said:


> Im quite confident Veii said to disable this in agesa after 1.1.9.0.


Yes indeed, he said that and it's because is causing stability issues in general.
For me at FCLK 2000 is actually more stable than without, dunno...
But my point was that AFAIK it's disabled by default.
That's what Veii said and it's indeed disabled on the Unify-X A21O BIOS and later.
So why looking for the option? Are there cases where it's enabled instead?


----------



## CarnageBT

I'm calling it for the night but I do see my motherboard in those modified bios. Interesting. I'll need to look into that tomorrow.

Here's where I stand









*Tested with single WEAKEST stick*Pictured, 1.48vdimm16 cycles, 42m, error 21.5 vdimmpassed 25 cycles*All 4 DIMMs populated*Picturedcycle 9, ~ 55m, error 81.52 vdimmcycle 5, ~ 25m, error 12Pictured, tWTRL 10 (from 8)cycle 7, ~40 mins, error 0tRRD 4/6 + tWTRL 10 (from 8)cycle 4, ~ 23, error 7, then 11, 12, 1 through 37mPictured, tCKE 9cycle 1, error 8, 8, 8, 8,tCKE 9 + CsOdtSetup CkeSetup 56-56-56cycle 8, ~50m, error 1, ran for 65m, no other errorsPictured, tCKE 1 + CsOdtSetup CkeSetup 56-56-56cycle 11, ~70m, error 7, ran for 80m, no other errors1.51 vdimm2 Cycles, ~20m, error 7, 7, ran for 35m*Pictured + 1.49 vdimm + 56-56-56**Cycle 12, ~75m, error 11, ran for 88m, no other errors*Pictured + 1.49vdimm, tRAS 29, tRC 43, tRFC x6, 56-56-56Cycle 4, ~25m, error, 1, 1Pictured + 1.5vdimm, tRAS 29, tRC 43, tRFC x6, 56-56-56Cycle 1, error 7Pictured + 1.5 VDIMM, tRAS 29, tRC 43, tRFC x6, 56-0-0Cycle 2, error 8Pictured + 1.49 VDIMM, tRAS 29, tRC 43, tRFC x6, 56-0-0Cycle 5, error 1, 0*Pictured, 1.49 vdimm**cycle 10, 60m, error 1*tRDRDSCL/tWRWRSCL - 2/2, 1.49 vdimm 56-0-0 (running out of ideas and this is something I changed from last night when I finally passed 25 cycles at 3667.)currently testing^ same but 56-56-56Pictured - tRRD 4/6. didnt' try tRRD alone. only in combo with tWTRL 10Pictured, ClkDrvStr 60 // or CADBUS settings

I honestly think my power settings need to be re-worked but i haven't gotten a good grasp of how yet.

I'm out for the night. Cheers


----------



## mongoled

ManniX-ITA said:


> Yes indeed, he said that and it's because is causing stability issues in general.
> For me at FCLK 2000 is actually more stable than without, dunno...
> But my point was that AFAIK it's disabled by default.
> That's what Veii said and it's indeed disabled on the Unify-X A21O BIOS and later.
> So why looking for the option? Are there cases where it's enabled instead?


Mine was left on "AUTO" and I had those inconsistent errors after setting to "disable" I have not had an error in TM5 yet, it could be unrelated, time will tell


----------



## ManniX-ITA

@Veii

Tried testing EDC very high but the thermal throttle limit at some point, didn't find where, drops from 90c to 80c...

I've also been voluntarily robbed and bought an MSI 3080ti Suprim X...
Works fine with PCIe Gen4 at FCLK 2000.
Nice card but the massive cooler is just barely enough for stock settings.
Overclocked can pass benchmarks but it's not stable in gaming.
Hope will do better with a water block, considering how expensive it is.

I've also did another check at the telemetry; didn't notice before that CPU VDD Full Scale is the full scale for TDC.
So whatever is set there will be the max reported TDC usage.
Too big delta from the PBO limit will cause instability.



mongoled said:


> Mine was left on "AUTO" and I had those inconsistent errors after setting to "disable" I have not had an error in TM5 yet, it could be unrelated, time will tell


Interesting... you should be able to spot if it's enabled cause the idle temperature will drop a few degrees.


----------



## mongoled

CarnageBT said:


> I'm calling it for the night but I do see my motherboard in those modified bios. Interesting. I'll need to look into that tomorrow.
> 
> Here's where I stand
> View attachment 2514208
> 
> 
> *Tested with single WEAKEST stick*Pictured, 1.48vdimm16 cycles, 42m, error 21.5 vdimmpassed 25 cycles*All 4 DIMMs populated*Picturedcycle 9, ~ 55m, error 81.52 vdimmcycle 5, ~ 25m, error 12Pictured, tWTRL 10 (from 8)cycle 7, ~40 mins, error 0tRRD 4/6 + tWTRL 10 (from 8)cycle 4, ~ 23, error 7, then 11, 12, 1 through 37mPictured, tCKE 9cycle 1, error 8, 8, 8, 8,tCKE 9 + CsOdtSetup CkeSetup 56-56-56cycle 8, ~50m, error 1, ran for 65m, no other errorsPictured, tCKE 1 + CsOdtSetup CkeSetup 56-56-56cycle 11, ~70m, error 7, ran for 80m, no other errors1.51 vdimm2 Cycles, ~20m, error 7, 7, ran for 35m*Pictured + 1.49 vdimm + 56-56-56**Cycle 12, ~75m, error 11, ran for 88m, no other errors*Pictured + 1.49vdimm, tRAS 29, tRC 43, tRFC x6, 56-56-56Cycle 4, ~25m, error, 1, 1Pictured + 1.5vdimm, tRAS 29, tRC 43, tRFC x6, 56-56-56Cycle 1, error 7Pictured + 1.5 VDIMM, tRAS 29, tRC 43, tRFC x6, 56-0-0Cycle 2, error 8Pictured + 1.49 VDIMM, tRAS 29, tRC 43, tRFC x6, 56-0-0Cycle 5, error 1, 0*Pictured, 1.49 vdimm**cycle 10, 60m, error 1*tRDRDSCL/tWRWRSCL - 2/2, 1.49 vdimm 56-0-0 (running out of ideas and this is something I changed from last night when I finally passed 25 cycles at 3667.)currently testing^ same but 56-56-56Pictured - tRRD 4/6. didnt' try tRRD alone. only in combo with tWTRL 10Pictured, ClkDrvStr 60 // or CADBUS settings
> 
> I honestly think my power settings need to be re-worked but i haven't gotten a good grasp of how yet.
> 
> I'm out for the night. Cheers


Counting from left to right

Best pair dimm stick 1 = BP1
Best pair dimm stick 1 = BP2
Worse pair dimm bad stick = WPB
Worse pair dimm good stick = WPG

1 -------- 2 -------- 3 -------- 4
BP1 --- WPB --- BP2 --- WPG

Thats how I have them ordered, may help also...

Night


----------



## mongoled

ManniX-ITA said:


> I've also did another check at the telemetry; didn't notice before that CPU VDD Full Scale is the full scale for TDC.


My investigation only found gremlins

😂 😂

** EDIT **
Actually something crossed my mind, will report back if its the case, maybe the source of this particular gremlin


----------



## kim nk

Bios agesa 1.2.0.3 3601 Version DF C-States - disable issue occurs. The memory voltage should be added 0.01 more, and the ccd value should be raised from 0.940 to 1.0. So I rolled back to 1.20.2 beta version again. There is one question. The timing you're using now. Here, we use bios dream voltage 1.51v at rt0/0/5 and 1.1 llc4 iod 1.0 ccd 1.0 cldo vddp 0.900. Here's a more efficient and correct value advice from timing. I'm looking at your data in translation, and there are many things I don't understand.
bclk 100.5625

agesa 1.2.0.2 3501 ---> agesa 1.2.0.3 a 3601 ----> agesa 1.2.0.2 3501

3501 --> 3601
ccd 0.94--->1.0
dram voltage-->1.50-->1.51
DF C-States-disable ------> auto
clkdrvstr 40-----> 24


----------



## Taraquin

craxton said:


> @wuttman
> this is that c14 4000 i told you about, (not the 100% stable config) and my voltage was
> WAY LOWER and the timings well everything is auto. NOTE not the stable c14 @4000 config i had.
> took out two sticks to see if that made any difference within the sil test on tool.exe but nope.
> 
> View attachment 2514140
> 
> 
> amd this is 4x8, with everything preset, but SOC is on auto....
> passes stress tests at that....?
> View attachment 2514143


Impressive IOD-voltage on 4000cl16. I have to use 1.11V soc and 1.03V IOD on 2x8 with 4000cl16. Seems we got golden I/O-dies and ****ty cores according to sil quality


----------



## mongoled

Taraquin said:


> Impressive IOD-voltage on 4000cl16. I have to use 1.11V soc and 1.03V IOD on 2x8 with 4000cl16. Seems we got golden I/O-dies and ****ty cores according to sil quality


Or because you have "****ty" cores they leave more power budget to the IOD, just another food for thought.... 

😊😊


----------



## mongoled

kim nk said:


> Bios agesa 1.2.0.3 3601 Version DF C-States - disable issue occurs. The memory voltage should be added 0.01 more, and the ccd value should be raised from 0.940 to 1.0. So I rolled back to 1.20.2 beta version again. There is one question. The timing you're using now. Here, we use bios dream voltage 1.51v at rt0/0/5 and 1.1 llc4 iod 1.0 ccd 1.0 cldo vddp 0.900. Here's a more efficient and correct value advice from timing. I'm looking at your data in translation, and there are many things I don't understand.
> bclk 100.5625
> 
> agesa 1.2.0.2 3501 ---> agesa 1.2.0.3 a 3601 ----> agesa 1.2.0.2 3501
> 
> 3501 --> 3601
> ccd 0.94--->1.0
> dram voltage-->1.50-->1.51
> DF C-States-disable ------> auto
> clkdrvstr 40-----> 24
> View attachment 2514220
> 
> 
> 
> 
> 
> View attachment 2514216
> 
> View attachment 2514219
> 
> 
> View attachment 2514221


You must have relatively low ambient temperatures, what exactly are ambient??

125xx 124xx using PBO is not possible with 28C ambient temperature using a rock stable CO curve 😁😁


----------



## kim nk

mongoled said:


> You must have relatively low ambient temperatures, what exactly are ambient??
> 
> 125xx using PBO is not possible with 28C ambient temperature using a rock stable CO curve 😁😁


The weather in Korea is over 30 degrees, so hot that you have to turn on the air conditioner. Cinebench set the air conditioner at 22 degrees and ran it. Maybe the room temperature is 24 degrees or so. Lol, I'm interested in rtt these days. It's too difficult to do rtt depending on the voltage requirement. crying 😭


----------



## mongoled

kim nk said:


> The weather in Korea is over 30 degrees, so hot that you have to turn on the air conditioner. Cinebench set the air conditioner at 22 degrees and ran it. Maybe the room temperature is 24 degrees or so. Lol, I'm interested in rtt these days. It's too difficult to do rtt depending on the voltage requirement. crying 😭


You are blasting AC into the heatsink/fan? That would explain the high score along with the slight CPU increase over the default 200mhz boost override limit while using BCLK increase. Or else there is another trick I am not aware of to get such high CB23 score on a stable CO setup

Re powering, didn't notice a difference for my 4x8GB kit from AGESA 1.1.9.0 to 1.2.0.3a


----------



## MyUsername

ManniX-ITA said:


> @Veii
> I've also did another check at the telemetry; didn't notice before that CPU VDD Full Scale is the full scale for TDC.
> So whatever is set there will be the max reported TDC usage.
> Too big delta from the PBO limit will cause instability.


I have this CPU VDD full scale calibrated the same as EDC 200 and used the offset at 43 to bring the PRD to near 100% full load. I'll investigate this with TDC at 150 later and report my findings. I did notice the lower you go with the CPU VDD scale and higher offset, you can go further with CO.

I had a look at 3070 and 3080ti, I'm just not paying that ridiculous prices.


----------



## kim nk

View attachment 2514224
View attachment 2514225

View attachment 2514226


I'm writing it like the last picture.


----------



## ManniX-ITA

MyUsername said:


> I had a look at 3070 and 3080ti, I'm just not paying that ridiculous prices.


Don't it's a true robbery 
But Intel said this situation will last a few more years... and indeed there's no sign of improvement in delivery dates and availability of components.
Plus the RAM prices are hiking at least 14% in the next months.
Couldn't wait another 6-12 months.


----------



## kim nk

mongoled said:


> You are blasting AC into the heatsink/fan? That would explain the high score along with the slight CPU increase over the default 200mhz boost override limit while using BCLK increase. Or else there is another trick I am not aware of to get such high CB23 score on a stable CO setup
> 
> Re powering, didn't notice a difference for my 4x8GB kit from AGESA 1.1.9.0 to 1.2.0.3a




























The last picture is now in view. 😱


----------



## mongoled

MyUsername said:


> I have this CPU VDD full scale calibrated the same as EDC 200 and used the offset at 43 to bring the PRD to near 100% full load. I'll investigate this with TDC at 150 later and report my findings. I did notice the lower you go with the CPU VDD scale and higher offset, you can go further with CO.
> 
> I had a look at 3070 and 3080ti, I'm just not paying that ridiculous prices.


I have a post here discussing my findings









Guide - Fully optimise your PBO


TLDR Its looking that Ryzen Gremlins are not allowing me to get consistent results, looking like just leave PBO on AUTO and tweak CO .... :oops: Warning, if you want to waste your time read further :D :D...




www.overclock.net


----------



## MyUsername

ManniX-ITA said:


> Don't it's a true robbery
> But Intel said this situation will last a few more years... and indeed there's no sign of improvement in delivery dates and availability of components.
> Plus the RAM prices are hiking at least 14% in the next months.
> Couldn't wait another 6-12 months.


CCL computers have your card at £1850, they can get f**ked I'm paying that


----------



## ManniX-ITA

MyUsername said:


> CCL computers have your card at £1850, they can get f**ked I'm paying that


That's really Ocean 11  
At the end I paid around 1900€
Which is way more than the ridiculous 1200 USD retail price but considering it's Europe and a premium OEM version it's not that high
Just a normal street robbery...


----------



## rossi594

ManniX-ITA said:


> Don't it's a true robbery
> But Intel said this situation will last a few more years... and indeed there's no sign of improvement in delivery dates and availability of components.
> Plus the RAM prices are hiking at least 14% in the next months.
> Couldn't wait another 6-12 months.


Let's see rtx 3080 had 700€ drop in germany within the last week. There is much more listings. Let's see where it goes. But it definitly didn't stay the same. It got slightly less terrible.

With ethereum lower than before, difficulty increasing, proof of stake update this year, nvidia pumping out more cards than ever for the miners and people going out getting drunk after beeing vaccinated. Maybe we find ourself in the lucky situation supply outpaces demand sooner than we think.


----------



## T[]RK

ManniX-ITA said:


> do you get a better result with SCL 2?


Didn't tested, since i do TM5 first and if there are no errors then i test AIDA64. But i can test AIDA64 first since it was stable with a lot cycles. Just to compare.

I tested today tRDRD/tWRRD=10-1. It was BAD - problem with video driver (stopped\recovered), screen freeze, mouse freeze, broken picture on squares.



sendap said:


> Read MB/s look ok, Write MB/s definately 1500 or 2000 MB/s too slow.


You mean "Copy"?  Write always stable at 30399 MB\s. Read close to "realistic" 57000 MB\s (ideal for 3800 MHz would be 60800 MB\s, but it's unreal).



ManniX-ITA said:


> There's something really off; tRTP/tWR are probably too low at 5/10. Try with them at 8/16.


I tested all three options 5-10, 6-12 and 8-16 with 25 cycles. They are stable with SCL=4, but yeah... maybe don't work well with SCL=2.



ManniX-ITA said:


> I also suspect you are starving voltage, set SOC at 1.12V and CCD/IOD at 1050mV, check if you get a performance bump.


Hm... i can try that.


----------



## XPEHOPE3

ManniX-ITA said:


> Wasn't disabled by default in 1.2.x AGESA versions?


On my Gigabyte B550 AORUS PRO V2 with F13h BIOS AGESA ComboV2 1.2.0.2 it wasn't disabled by default


----------



## Veii

kim nk said:


> View attachment 2514224
> View attachment 2514225
> 
> View attachment 2514226
> 
> 
> I'm writing it like the last picture.


Can you redo this post - the pictures are gone from the server  ?


mongoled said:


> You are blasting AC into the heatsink/fan?


Not directly - it's common to have an AC across hot locations
With a difference of over 10c - kim ment that the room is 24c at the moment ~ not direct blast, else idle wouldn't be in the 40s


kim nk said:


> Here, we use bios dram voltage 1.51v at rt0/0/5
> 
> 
> mongoled said:
> 
> 
> 
> Im quite confident Veii said to disable this in agesa after 1.1.9.0.
> 
> 
> 
> ManniX-ITA said:
> 
> 
> 
> Yes indeed, he said that and it's because is causing stability issues in general.
> For me at FCLK 2000 is actually more stable than without, dunno...
> But my point was that AFAIK it's disabled by default.
> That's what Veii said and it's indeed disabled on the Unify-X A21O BIOS and later.
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

DF_C-States are a complicated topic
They cause overboost issues, little overboost spikes sometimes between P-States , but mostly from full suspension
HWInfo isn't able to always track it & considering people told Martin (dev) that this could be a bug ~ i wouldn't wonder if it was tried to be masked and "smoothed out"

APCI Performance Index, under the Performance Tracking setting (% Processor Performance),
Does still track them ~ but you need to click on one little tab to change the range from 100 to 200 

My wording was, that since AGESA 1.1.0.0C/D - Patch D which is 1180/81 == 1191 == 1200+ (annoying beta bios spread)
Several attempts where made to cover that boosting issue.
From the chipset powerplans with disabled hibernation (deep sleep) to Bioses changing the Auto value "meaning" from Enabled , to Disabled

It was always on Auto, soo sometimes it means Enabled, sometimes it means disabled
Now thinking about it, maybe "enabled" with powerplan "disabled" method ~ could result internally in more power reserves
But the fact stays, that they cause overboost issues and idle crash or random reboot units.
Maaybe it's fixable with a bit of DPM tweaks and maybe fixable with different CO
(my powerplan mess, caused abusage of overboost with a frequency limiter ~ soo usage of DF_State only had benefits, as cache could even boost higher that way)

But non the less, it is more than buggy - and i strongly suggest to disable it, till AMD fixes their Boosting Table mess
They tried to rewrite it fully on 1200A/1201 but it still is an issue even at 1203A (not everyone got A ,and no SMU version shows a difference if it's A or nonA)
Overall it's a mess, and you shouldn't trust AUTO on anything
You shouldn't trust chipset drivers to have only the public visible changes, they love to sneak gremlins into it 
While playing with bioses between Patch C and 1200 pure, i usually used a very old Chipset driver ~ because the new ones messed with the powerplans
Today, i just don't install the powerplans at all anymore & use Windows High-Perf for preventing overboost (using powerplan explorer to unhide the two maximum frequency limits & set them bellow 5ghz)

Soo even if through some magic overboost happened - it will be hard capped on a 2nd stage and be cut , without it ever reaching 55ghz and hardcrashing

@kim nk stay cautious with this 1.51v at RTT_PARK /5
If you use 1202 and higher, drop procODT once - and drop RTT_PARK to lower value (a higher divider /6 and more)
Use RTT_NOM /7 once you exceed 1.46v. Range is from 1.48v but 1.46v does count if you ever used more ClkDrvStr (30+)

4 dimms would need RTT_WR , starting with RZQ /3 and lower
Getting /2 to run is a big benefit, but it's mostly only running beyond 1.58v or with very strong Ampere reaching the dimms (low RTT_PARK and strong ClkDrvStr)
Low RTT_PARK (strong ohm value) is not a good idea on it's own , as it increases heat creation too much








This is what it settled for now, but was riding the 620 train before
When you reach 737 RTT , then changing RTT_WR the middle value to /2
If you do so (RZQ/2), then RTT_NOM and RTT_PARK "reset" .
You start with low strong values again like 625 and lower 724. Someday you can reach 727 or 620

RTT_NOM nearly always depends on used voltage. You will notice when you need to increase it
More NOM, is fine ~ it is needed when you run strong voltage
But all is a balance thing.

Balance thing because ClkDrvStr is the "main" powering thing
Too much ClkDrvStr and too much PARK - will make issues
A lot of ClkDrvStr and no PARK, will make less issues
A lot of VDIMM and a lot of PARK , can kill dimm sticks (can kill the PCB)


ManniX-ITA said:


> Don't run y-cruncher till you are 100% sure the memory setting is 100% fine.
> Would be best to not use any PBO or CO till you know for sure.
> 
> 
> XPEHOPE3 said:
> 
> 
> 
> I saw @Veii suggesting somewhere to use y-cruncher to test if FCLK is fine at certain voltages
> *before* running 1usmus_v3 test, that's why I ran it in that order.
> 
> 
> 
> ManniX-ITA said:
> 
> 
> 
> y-cruncher is doing calculations, if there's something wrong with the memory it will error
> same as Prime95 or OCCT or any other CPU test
> if you want to test the FCLK with y-cruncher do it only after you are 100% sure the memory is rock solid
> Erroring so late at the 7th cycle points to a memory issue
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

This is a wording missunderstanding,
ManniX is fully right but a wording missunderstanding

Y-cruncher you should run with XMP on stock , to finetune your procODT/VDDP/VDDG range / and to verify your sample is not defect by the factory
Also to finetune your loadline droop
(more droop is often better with Vermeer - except for CTR usage. Less switching freq is better for lower ripple, find the balance between loadline and "enough" switching frequency)

It is recommended to disable every little manufacture cheating ~ including every performance enchancers, enable PBO with the stock limits and scalar set to X1 (boardpartners love to use X2)
Often it's easier to just change the scalar in AMD CBS - without touching PBO, because PBO will add more vcore.
Soo be sure FCLK and the CPU is stable and extend your XMP profile a bit higher in frequency or lower in frequency (the good thing when you buy 4000+ kits)

Y-cruncher is slightly sensitive to memOC , but FFT test can error because of both
Vermeer is fantastic at autocorrection, don't forget that please. Y-cruncher is a calculated result, but like SuperPi 1.5SX , it's not too harsh on the dimms

TM5 is a purely memory sensitive test, and not even an FCLK sensitive one
Error 6 mostly relates to both (majorly broken primaries & other timings) or (majorly broken voltages and FCLK crashes)
TM5 is able to run with crashing cores - but will trow a thread-exception handler, if one crashes. Then it will stop but the timer will keep running

Two more notes on both topics,
CTR does force-enable DF_C-States.
CTR is made to catch crashing cores in time, but the Overboost issue [boosting bug] will still cause issues
Soo it is strongly recommended to ignore AMDs powerplans (they are a mess because of the DF bug, sorry AMD) and ignore windows ultimate powerplan (it's also a mess)
Use highperf with a frequency limiter (if you have crashes) to catch the boosting spikes & consider that even CTR can randomly cause a crash while running TM5 on it
Soo once CTR crashes, TM5 will also crash ~ keep this in mind (it happened to me)


Spoiler: Something else funny happened to "me":














This has silicon score of 112 [remote system] 
I noticed only later that the setup had -30 on the first CCD and -22 on the 2nd CCD , with +30mV offset and vdroop at lv 5

Soo i learned here that you can utilize another way of running CTR (well overboosting the overboost CTR feature) but more extreme :^
If you use a very strong loadline , and still add an offset ontop. You can get it nearly similar where CPU_TEL is identical to CPU_VID
Here i messed up slightly, but yes 5200 could run

Normal CTR usage only allowed 4850 or 4900
Soo this should trick FIT too (deepest loadline with highest negative CO and positive vcore to compensate for straps jumping/switching)
I need to explore this further, but my current OS (main system) doesn't open public CTR 2.1 (he released the public version to the community because of bigger plans behind the stage)


ManniX-ITA said:


> So far I've not seen anyone having success with the EDC bug and a 5000.


It runs for me, but since 1100A i commented that it is bad on Vermeer
Because it can package throttle on many parts - unlike Matisse, this one results in +30ns L3 and 172ns memory latency

Value 2 works, 3 is accepted as EDC3 = 550mhz constant throttle and laggy bios
1 could be recognized by FIT and stop the nonsense 
==============================================
@ManniX-ITA i saw you got a 3080ti ? 
I've been playing the recent 2-3 days, with 2 3080s and a 3070 (3060 fun misses)
* warzone stability only matches firestrike extreme stability, Timespy and superposition matter for something else

A little advice:
MSI Afterburner, max out the powerlimit, max out the thermal limit (keep in mind some bioses can have 350W some 450W limits)
then change the slider to -200 to -150Mhz on core
Open the Curve editor:

For a 3080, you want to grab 850-881mV strap and move it to 1950mhz , and press L to force the freq + apply
Start that way and verify it's firestrike extreme + unigine superposition (1080p extreme windowed ~ custom) , stable
Then you can go up to 2100 at the same 850mV strap
RTX Ampere scales better with lower voltage and on stock always hit powerlimits (hotspot temp) soo throttles frequency and clock stretches too. lol

On 3090 or likely even 3080ti's , you want to anchor it at 800-850mV
There try to run 1806-1860. They run less frequency, but core is binned for far lower voltage

This will result in 80-100W drop, compared to stock and 10-15c less on the hotspot temp
With nearly no performance regression
Also you can nearly always add +200mem, but start with +100
Lower voltage on the card allows for higher memOC

There is a step 3. to mark the 900-950mV range, by holding shift+drag leftclick, and subtly push it upwards near the 2000-2050 or 2100-2130 range (3080ti or 3090 & 3080 or lower)
then the curve adapts to this little bump, as long as the shift range is selected and marked. But this can make it crash
Be sure to disable L key to let it be dynamic boosting and lowering perf , again 

At the very end, lower the powerlimit till you don't lose any score on superposition (more accurate/consistant than 3D mark i feel)
~ as the board will draw current, without really using it & the normal slider extender doesn't work well. Too many little core throttle options "on stock curve"
Happy Overclocking


----------



## T[]RK

ManniX-ITA said:


> do you get a better result with SCL 2?


Just run with SCL=2. No big diffirence compare to SCL=4.


----------



## kim nk

Veii said:


> Can you redo this post - the pictures are gone from the server  ?
> 
> Not directly - it's common to have an AC across hot locations
> With a difference of over 10c - kim ment that the room is 24c at the moment ~ not direct blast, else idle wouldn't be in the 40s
> 
> DF_C-States are a complicated topic
> They cause overboost issues, little overboost spikes sometimes between P-States , but mostly from full suspension
> HWInfo isn't able to always track it & considering people told Martin (dev) that this could be a bug ~ i wouldn't wonder if it was tried to be masked and "smoothed out"
> 
> APCI Performance Index, under the Performance Tracking setting (% Processor Performance),
> Does still track them ~ but you need to click on one little tab to change the range from 100 to 200
> 
> My wording was, that since AGESA 1.1.0.0C/D - Patch D which is 1180/81 == 1191 == 1200+ (annoying beta bios spread)
> Several attempts where made to cover that boosting issue.
> From the chipset powerplans with disabled hibernation (deep sleep) to Bioses changing the Auto value "meaning" from Enabled , to Disabled
> 
> It was always on Auto, soo sometimes it means Enabled, sometimes it means disabled
> Now thinking about it, maybe "enabled" with powerplan "disabled" method ~ could result internally in more power reserves
> But the fact stays, that they cause overboost issues and idle crash or random reboot units.
> Maaybe it's fixable with a bit of DPM tweaks and maybe fixable with different CO
> (my powerplan mess, caused abusage of overboost with a frequency limiter ~ soo usage of DF_State only had benefits, as cache could even boost higher that way)
> 
> But non the less, it is more than buggy - and i strongly suggest to disable it, till AMD fixes their Boosting Table mess
> They tried to rewrite it fully on 1200A/1201 but it still is an issue even at 1203A (not everyone got A ,and no SMU version shows a difference if it's A or nonA)
> Overall it's a mess, and you shouldn't trust AUTO on anything
> You shouldn't trust chipset drivers to have only the public visible changes, they love to sneak gremlins into it
> While playing with bioses between Patch C and 1200 pure, i usually used a very old Chipset driver ~ because the new ones messed with the powerplans
> Today, i just don't install the powerplans at all anymore & use Windows High-Perf for preventing overboost (using powerplan explorer to unhide the two maximum frequency limits & set them bellow 5ghz)
> 
> Soo even if through some magic overboost happened - it will be hard capped on a 2nd stage and be cut , without it ever reaching 55ghz and hardcrashing
> 
> @kim nk stay cautious with this 1.51v at RTT_PARK /5
> If you use 1202 and higher, drop procODT once - and drop RTT_PARK to lower value (a higher divider /6 and more)
> Use RTT_NOM /7 once you exceed 1.46v. Range is from 1.48v but 1.46v does count if you ever used more ClkDrvStr (30+)
> 
> 4 dimms would need RTT_WR , starting with RZQ /3 and lower
> Getting /2 to run is a big benefit, but it's mostly only running beyond 1.58v or with very strong Ampere reaching the dimms (low RTT_PARK and strong ClkDrvStr)
> Low RTT_PARK (strong ohm value) is not a good idea on it's own , as it increases heat creation too much
> 
> 
> 
> 
> 
> 
> 
> 
> This is what it settled for now, but was riding the 620 train before
> When you reach 737 RTT , then changing RTT_WR the middle value to /2
> If you do so (RZQ/2), then RTT_NOM and RTT_PARK "reset" .
> You start with low strong values again like 625 and lower 724. Someday you can reach 727 or 620
> 
> RTT_NOM nearly always depends on used voltage. You will notice when you need to increase it
> More NOM, is fine ~ it is needed when you run strong voltage
> But all is a balance thing.
> 
> Balance thing because ClkDrvStr is the "main" powering thing
> Too much ClkDrvStr and too much PARK - will make issues
> A lot of ClkDrvStr and no PARK, will make less issues
> A lot of VDIMM and a lot of PARK , can kill dimm sticks (can kill the PCB)
> 
> This is a wording missunderstanding,
> ManniX is fully right but a wording missunderstanding
> 
> Y-cruncher you should run with XMP on stock , to finetune your procODT/VDDP/VDDG range / and to verify your sample is not defect by the factory
> Also to finetune your loadline droop
> (more droop is often better with Vermeer - except for CTR usage. Less switching freq is better for lower ripple, find the balance between loadline and "enough" switching frequency)
> 
> It is recommended to disable every little manufacture cheating ~ including every performance enchancers, enable PBO with the stock limits and scalar set to X1 (boardpartners love to use X2)
> Often it's easier to just change the scalar in AMD CBS - without touching PBO, because PBO will add more vcore.
> Soo be sure FCLK and the CPU is stable and extend your XMP profile a bit higher in frequency or lower in frequency (the good thing when you buy 4000+ kits)
> 
> Y-cruncher is slightly sensitive to memOC , but FFT test can error because of both
> Vermeer is fantastic at autocorrection, don't forget that please. Y-cruncher is a calculated result, but like SuperPi 1.5SX , it's not too harsh on the dimms
> 
> TM5 is a purely memory sensitive test, and not even an FCLK sensitive one
> Error 6 mostly relates to both (majorly broken primaries & other timings) or (majorly broken voltages and FCLK crashes)
> TM5 is able to run with crashing cores - but will trow a thread-exception handler, if one crashes. Then it will stop but the timer will keep running
> 
> Two more notes on both topics,
> CTR does force-enable DF_C-States.
> CTR is made to catch crashing cores in time, but the Overboost issue [boosting bug] will still cause issues
> Soo it is strongly recommended to ignore AMDs powerplans (they are a mess because of the DF bug, sorry AMD) and ignore windows ultimate powerplan (it's also a mess)
> Use highperf with a frequency limiter (if you have crashes) to catch the boosting spikes & consider that even CTR can randomly cause a crash while running TM5 on it
> Soo once CTR crashes, TM5 will also crash ~ keep this in mind (it happened to me)
> 
> 
> Spoiler: Something else funny happened to "me":
> 
> 
> 
> 
> View attachment 2514238
> 
> 
> 
> This has silicon score of 112 [remote system]
> I noticed only later that the setup had -30 on the first CCD and -22 on the 2nd CCD , with +30mV offset and vdroop at lv 5
> 
> Soo i learned here that you can utilize another way of running CTR (well overboosting the overboost CTR feature) but more extreme :^
> If you use a very strong loadline , and still add an offset ontop. You can get it nearly similar where CPU_TEL is identical to CPU_VID
> Here i messed up slightly, but yes 5200 could run
> 
> Normal CTR usage only allowed 4850 or 4900
> Soo this should trick FIT too (deepest loadline with highest negative CO and positive vcore to compensate for straps jumping/switching)
> I need to explore this further, but my current OS (main system) doesn't open public CTR 2.1 (he released the public version to the community because of bigger plans behind the stage)
> 
> It runs for me, but since 1100A i commented that it is bad on Vermeer
> Because it can package throttle on many parts - unlike Matisse, this one results in +30ns L3 and 172ns memory latency
> 
> Value 2 works, 3 is accepted as EDC3 = 550mhz constant throttle and laggy bios
> 1 could be recognized by FIT and stop the nonsense
> ==============================================
> @ManniX-ITA i saw you got a 3080ti ?
> I've been playing the recent 2-3 recently with 2 3080s and a 3070 (3060 fun misses)
> * warzone stability only matches firestrike extreme stability, Timespy and superposition matter for something else
> 
> A little advice:
> MSI Afterburner, max out the powerlimit, max out the thermal limit (keep in mind some bioses can have 350W some 450W limits)
> then change the slider to -200 to -150Mhz on core
> Open the Curve editor:
> 
> For a 3080, you want to grab 850-881mV strap and move it to 1950mhz , and press L to force the freq + apply
> Start that way and verify it's firestrike extreme + unigine superposition (1080p extreme windowed ~ custom) , stable
> Then you can go up to 2100 at the same 850mV strap
> RTX Ampere scales better with lower voltage and on stock always hit powerlimits (hotspot temp) soo throttles frequency and clock stretches too. lol
> 
> On 3090 or likely even 3080ti's , you want to anchor it at 800-850mV
> There try to run 1806-1860. They run less frequency, but core is binned for far lower voltage
> 
> This will result in 80-100W drop, compared to stock and 10-15c less on the hotspot temp
> With nearly no performance regression
> Also you can nearly always add +200mem, but start with +100
> Lower voltage on the card allows for higher memOC
> 
> There is a step 3. to mark the 900-950mV range, by holding shift+drag leftclick, and subtly push it upwards near the 2000-2050 or 2100-2130 range (3080ti or 3090 & 3080 or lower)
> then the curve adapts to this little bump, as long as the shift range is selected and marked. But this can make it crash
> Be sure to disable L key to let it be dynamic boosting and lowering perf , again
> 
> At the very end, lower the powerlimit till you don't lose any score on superposition (more accurate/consistant than 3D mark i feel)
> ~ as the board will draw current, without really using it & the normal slider extender doesn't work well. Too many little core throttle options "on stock curve"
> Happy Overclocking





Veii said:


> Can you redo this post - the pictures are gone from the server  ?
> 
> Not directly - it's common to have an AC across hot locations
> With a difference of over 10c - kim ment that the room is 24c at the moment ~ not direct blast, else idle wouldn't be in the 40s
> 
> DF_C-States are a complicated topic
> They cause overboost issues, little overboost spikes sometimes between P-States , but mostly from full suspension
> HWInfo isn't able to always track it & considering people told Martin (dev) that this could be a bug ~ i wouldn't wonder if it was tried to be masked and "smoothed out"
> 
> APCI Performance Index, under the Performance Tracking setting (% Processor Performance),
> Does still track them ~ but you need to click on one little tab to change the range from 100 to 200
> 
> My wording was, that since AGESA 1.1.0.0C/D - Patch D which is 1180/81 == 1191 == 1200+ (annoying beta bios spread)
> Several attempts where made to cover that boosting issue.
> From the chipset powerplans with disabled hibernation (deep sleep) to Bioses changing the Auto value "meaning" from Enabled , to Disabled
> 
> It was always on Auto, soo sometimes it means Enabled, sometimes it means disabled
> Now thinking about it, maybe "enabled" with powerplan "disabled" method ~ could result internally in more power reserves
> But the fact stays, that they cause overboost issues and idle crash or random reboot units.
> Maaybe it's fixable with a bit of DPM tweaks and maybe fixable with different CO
> (my powerplan mess, caused abusage of overboost with a frequency limiter ~ soo usage of DF_State only had benefits, as cache could even boost higher that way)
> 
> But non the less, it is more than buggy - and i strongly suggest to disable it, till AMD fixes their Boosting Table mess
> They tried to rewrite it fully on 1200A/1201 but it still is an issue even at 1203A (not everyone got A ,and no SMU version shows a difference if it's A or nonA)
> Overall it's a mess, and you shouldn't trust AUTO on anything
> You shouldn't trust chipset drivers to have only the public visible changes, they love to sneak gremlins into it
> While playing with bioses between Patch C and 1200 pure, i usually used a very old Chipset driver ~ because the new ones messed with the powerplans
> Today, i just don't install the powerplans at all anymore & use Windows High-Perf for preventing overboost (using powerplan explorer to unhide the two maximum frequency limits & set them bellow 5ghz)
> 
> Soo even if through some magic overboost happened - it will be hard capped on a 2nd stage and be cut , without it ever reaching 55ghz and hardcrashing
> 
> @kim nk stay cautious with this 1.51v at RTT_PARK /5
> If you use 1202 and higher, drop procODT once - and drop RTT_PARK to lower value (a higher divider /6 and more)
> Use RTT_NOM /7 once you exceed 1.46v. Range is from 1.48v but 1.46v does count if you ever used more ClkDrvStr (30+)
> 
> 4 dimms would need RTT_WR , starting with RZQ /3 and lower
> Getting /2 to run is a big benefit, but it's mostly only running beyond 1.58v or with very strong Ampere reaching the dimms (low RTT_PARK and strong ClkDrvStr)
> Low RTT_PARK (strong ohm value) is not a good idea on it's own , as it increases heat creation too much
> 
> 
> 
> 
> 
> 
> 
> 
> This is what it settled for now, but was riding the 620 train before
> When you reach 737 RTT , then changing RTT_WR the middle value to /2
> If you do so (RZQ/2), then RTT_NOM and RTT_PARK "reset" .
> You start with low strong values again like 625 and lower 724. Someday you can reach 727 or 620
> 
> RTT_NOM nearly always depends on used voltage. You will notice when you need to increase it
> More NOM, is fine ~ it is needed when you run strong voltage
> But all is a balance thing.
> 
> Balance thing because ClkDrvStr is the "main" powering thing
> Too much ClkDrvStr and too much PARK - will make issues
> A lot of ClkDrvStr and no PARK, will make less issues
> A lot of VDIMM and a lot of PARK , can kill dimm sticks (can kill the PCB)
> 
> This is a wording missunderstanding,
> ManniX is fully right but a wording missunderstanding
> 
> Y-cruncher you should run with XMP on stock , to finetune your procODT/VDDP/VDDG range / and to verify your sample is not defect by the factory
> Also to finetune your loadline droop
> (more droop is often better with Vermeer - except for CTR usage. Less switching freq is better for lower ripple, find the balance between loadline and "enough" switching frequency)
> 
> It is recommended to disable every little manufacture cheating ~ including every performance enchancers, enable PBO with the stock limits and scalar set to X1 (boardpartners love to use X2)
> Often it's easier to just change the scalar in AMD CBS - without touching PBO, because PBO will add more vcore.
> Soo be sure FCLK and the CPU is stable and extend your XMP profile a bit higher in frequency or lower in frequency (the good thing when you buy 4000+ kits)
> 
> Y-cruncher is slightly sensitive to memOC , but FFT test can error because of both
> Vermeer is fantastic at autocorrection, don't forget that please. Y-cruncher is a calculated result, but like SuperPi 1.5SX , it's not too harsh on the dimms
> 
> TM5 is a purely memory sensitive test, and not even an FCLK sensitive one
> Error 6 mostly relates to both (majorly broken primaries & other timings) or (majorly broken voltages and FCLK crashes)
> TM5 is able to run with crashing cores - but will trow a thread-exception handler, if one crashes. Then it will stop but the timer will keep running
> 
> Two more notes on both topics,
> CTR does force-enable DF_C-States.
> CTR is made to catch crashing cores in time, but the Overboost issue [boosting bug] will still cause issues
> Soo it is strongly recommended to ignore AMDs powerplans (they are a mess because of the DF bug, sorry AMD) and ignore windows ultimate powerplan (it's also a mess)
> Use highperf with a frequency limiter (if you have crashes) to catch the boosting spikes & consider that even CTR can randomly cause a crash while running TM5 on it
> Soo once CTR crashes, TM5 will also crash ~ keep this in mind (it happened to me)
> 
> 
> Spoiler: Something else funny happened to "me":
> 
> 
> 
> 
> View attachment 2514238
> 
> 
> 
> This has silicon score of 112 [remote system]
> I noticed only later that the setup had -30 on the first CCD and -22 on the 2nd CCD , with +30mV offset and vdroop at lv 5
> 
> Soo i learned here that you can utilize another way of running CTR (well overboosting the overboost CTR feature) but more extreme :^
> If you use a very strong loadline , and still add an offset ontop. You can get it nearly similar where CPU_TEL is identical to CPU_VID
> Here i messed up slightly, but yes 5200 could run
> 
> Normal CTR usage only allowed 4850 or 4900
> Soo this should trick FIT too (deepest loadline with highest negative CO and positive vcore to compensate for straps jumping/switching)
> I need to explore this further, but my current OS (main system) doesn't open public CTR 2.1 (he released the public version to the community because of bigger plans behind the stage)
> 
> It runs for me, but since 1100A i commented that it is bad on Vermeer
> Because it can package throttle on many parts - unlike Matisse, this one results in +30ns L3 and 172ns memory latency
> 
> Value 2 works, 3 is accepted as EDC3 = 550mhz constant throttle and laggy bios
> 1 could be recognized by FIT and stop the nonsense
> ==============================================
> @ManniX-ITA i saw you got a 3080ti ?
> I've been playing the recent 2-3 recently with 2 3080s and a 3070 (3060 fun misses)
> * warzone stability only matches firestrike extreme stability, Timespy and superposition matter for something else
> 
> A little advice:
> MSI Afterburner, max out the powerlimit, max out the thermal limit (keep in mind some bioses can have 350W some 450W limits)
> then change the slider to -200 to -150Mhz on core
> Open the Curve editor:
> 
> For a 3080, you want to grab 850-881mV strap and move it to 1950mhz , and press L to force the freq + apply
> Start that way and verify it's firestrike extreme + unigine superposition (1080p extreme windowed ~ custom) , stable
> Then you can go up to 2100 at the same 850mV strap
> RTX Ampere scales better with lower voltage and on stock always hit powerlimits (hotspot temp) soo throttles frequency and clock stretches too. lol
> 
> On 3090 or likely even 3080ti's , you want to anchor it at 800-850mV
> There try to run 1806-1860. They run less frequency, but core is binned for far lower voltage
> 
> This will result in 80-100W drop, compared to stock and 10-15c less on the hotspot temp
> With nearly no performance regression
> Also you can nearly always add +200mem, but start with +100
> Lower voltage on the card allows for higher memOC
> 
> There is a step 3. to mark the 900-950mV range, by holding shift+drag leftclick, and subtly push it upwards near the 2000-2050 or 2100-2130 range (3080ti or 3090 & 3080 or lower)
> then the curve adapts to this little bump, as long as the shift range is selected and marked. But this can make it crash
> Be sure to disable L key to let it be dynamic boosting and lowering perf , again
> 
> At the very end, lower the powerlimit till you don't lose any score on superposition (more accurate/consistant than 3D mark i feel)
> ~ as the board will draw current, without really using it & the normal slider extender doesn't work well. Too many little core throttle options "on stock curve"
> Happy Overclocking





Veii said:


> Can you redo this post - the pictures are gone from the server  ?
> 
> Not directly - it's common to have an AC across hot locations
> With a difference of over 10c - kim ment that the room is 24c at the moment ~ not direct blast, else idle wouldn't be in the 40s
> 
> DF_C-States are a complicated topic
> They cause overboost issues, little overboost spikes sometimes between P-States , but mostly from full suspension
> HWInfo isn't able to always track it & considering people told Martin (dev) that this could be a bug ~ i wouldn't wonder if it was tried to be masked and "smoothed out"
> 
> APCI Performance Index, under the Performance Tracking setting (% Processor Performance),
> Does still track them ~ but you need to click on one little tab to change the range from 100 to 200
> 
> My wording was, that since AGESA 1.1.0.0C/D - Patch D which is 1180/81 == 1191 == 1200+ (annoying beta bios spread)
> Several attempts where made to cover that boosting issue.
> From the chipset powerplans with disabled hibernation (deep sleep) to Bioses changing the Auto value "meaning" from Enabled , to Disabled
> 
> It was always on Auto, soo sometimes it means Enabled, sometimes it means disabled
> Now thinking about it, maybe "enabled" with powerplan "disabled" method ~ could result internally in more power reserves
> But the fact stays, that they cause overboost issues and idle crash or random reboot units.
> Maaybe it's fixable with a bit of DPM tweaks and maybe fixable with different CO
> (my powerplan mess, caused abusage of overboost with a frequency limiter ~ soo usage of DF_State only had benefits, as cache could even boost higher that way)
> 
> But non the less, it is more than buggy - and i strongly suggest to disable it, till AMD fixes their Boosting Table mess
> They tried to rewrite it fully on 1200A/1201 but it still is an issue even at 1203A (not everyone got A ,and no SMU version shows a difference if it's A or nonA)
> Overall it's a mess, and you shouldn't trust AUTO on anything
> You shouldn't trust chipset drivers to have only the public visible changes, they love to sneak gremlins into it
> While playing with bioses between Patch C and 1200 pure, i usually used a very old Chipset driver ~ because the new ones messed with the powerplans
> Today, i just don't install the powerplans at all anymore & use Windows High-Perf for preventing overboost (using powerplan explorer to unhide the two maximum frequency limits & set them bellow 5ghz)
> 
> Soo even if through some magic overboost happened - it will be hard capped on a 2nd stage and be cut , without it ever reaching 55ghz and hardcrashing
> 
> @kim nk stay cautious with this 1.51v at RTT_PARK /5
> If you use 1202 and higher, drop procODT once - and drop RTT_PARK to lower value (a higher divider /6 and more)
> Use RTT_NOM /7 once you exceed 1.46v. Range is from 1.48v but 1.46v does count if you ever used more ClkDrvStr (30+)
> 
> 4 dimms would need RTT_WR , starting with RZQ /3 and lower
> Getting /2 to run is a big benefit, but it's mostly only running beyond 1.58v or with very strong Ampere reaching the dimms (low RTT_PARK and strong ClkDrvStr)
> Low RTT_PARK (strong ohm value) is not a good idea on it's own , as it increases heat creation too much
> 
> 
> 
> 
> 
> 
> 
> 
> This is what it settled for now, but was riding the 620 train before
> When you reach 737 RTT , then changing RTT_WR the middle value to /2
> If you do so (RZQ/2), then RTT_NOM and RTT_PARK "reset" .
> You start with low strong values again like 625 and lower 724. Someday you can reach 727 or 620
> 
> RTT_NOM nearly always depends on used voltage. You will notice when you need to increase it
> More NOM, is fine ~ it is needed when you run strong voltage
> But all is a balance thing.
> 
> Balance thing because ClkDrvStr is the "main" powering thing
> Too much ClkDrvStr and too much PARK - will make issues
> A lot of ClkDrvStr and no PARK, will make less issues
> A lot of VDIMM and a lot of PARK , can kill dimm sticks (can kill the PCB)
> 
> This is a wording missunderstanding,
> ManniX is fully right but a wording missunderstanding
> 
> Y-cruncher you should run with XMP on stock , to finetune your procODT/VDDP/VDDG range / and to verify your sample is not defect by the factory
> Also to finetune your loadline droop
> (more droop is often better with Vermeer - except for CTR usage. Less switching freq is better for lower ripple, find the balance between loadline and "enough" switching frequency)
> 
> It is recommended to disable every little manufacture cheating ~ including every performance enchancers, enable PBO with the stock limits and scalar set to X1 (boardpartners love to use X2)
> Often it's easier to just change the scalar in AMD CBS - without touching PBO, because PBO will add more vcore.
> Soo be sure FCLK and the CPU is stable and extend your XMP profile a bit higher in frequency or lower in frequency (the good thing when you buy 4000+ kits)
> 
> Y-cruncher is slightly sensitive to memOC , but FFT test can error because of both
> Vermeer is fantastic at autocorrection, don't forget that please. Y-cruncher is a calculated result, but like SuperPi 1.5SX , it's not too harsh on the dimms
> 
> TM5 is a purely memory sensitive test, and not even an FCLK sensitive one
> Error 6 mostly relates to both (majorly broken primaries & other timings) or (majorly broken voltages and FCLK crashes)
> TM5 is able to run with crashing cores - but will trow a thread-exception handler, if one crashes. Then it will stop but the timer will keep running
> 
> Two more notes on both topics,
> CTR does force-enable DF_C-States.
> CTR is made to catch crashing cores in time, but the Overboost issue [boosting bug] will still cause issues
> Soo it is strongly recommended to ignore AMDs powerplans (they are a mess because of the DF bug, sorry AMD) and ignore windows ultimate powerplan (it's also a mess)
> Use highperf with a frequency limiter (if you have crashes) to catch the boosting spikes & consider that even CTR can randomly cause a crash while running TM5 on it
> Soo once CTR crashes, TM5 will also crash ~ keep this in mind (it happened to me)
> 
> 
> Spoiler: Something else funny happened to "me":
> 
> 
> 
> 
> View attachment 2514238
> 
> 
> 
> This has silicon score of 112 [remote system]
> I noticed only later that the setup had -30 on the first CCD and -22 on the 2nd CCD , with +30mV offset and vdroop at lv 5
> 
> Soo i learned here that you can utilize another way of running CTR (well overboosting the overboost CTR feature) but more extreme :^
> If you use a very strong loadline , and still add an offset ontop. You can get it nearly similar where CPU_TEL is identical to CPU_VID
> Here i messed up slightly, but yes 5200 could run
> 
> Normal CTR usage only allowed 4850 or 4900
> Soo this should trick FIT too (deepest loadline with highest negative CO and positive vcore to compensate for straps jumping/switching)
> I need to explore this further, but my current OS (main system) doesn't open public CTR 2.1 (he released the public version to the community because of bigger plans behind the stage)
> 
> It runs for me, but since 1100A i commented that it is bad on Vermeer
> Because it can package throttle on many parts - unlike Matisse, this one results in +30ns L3 and 172ns memory latency
> 
> Value 2 works, 3 is accepted as EDC3 = 550mhz constant throttle and laggy bios
> 1 could be recognized by FIT and stop the nonsense
> ==============================================
> @ManniX-ITA i saw you got a 3080ti ?
> I've been playing the recent 2-3 recently with 2 3080s and a 3070 (3060 fun misses)
> * warzone stability only matches firestrike extreme stability, Timespy and superposition matter for something else
> 
> A little advice:
> MSI Afterburner, max out the powerlimit, max out the thermal limit (keep in mind some bioses can have 350W some 450W limits)
> then change the slider to -200 to -150Mhz on core
> Open the Curve editor:
> 
> For a 3080, you want to grab 850-881mV strap and move it to 1950mhz , and press L to force the freq + apply
> Start that way and verify it's firestrike extreme + unigine superposition (1080p extreme windowed ~ custom) , stable
> Then you can go up to 2100 at the same 850mV strap
> RTX Ampere scales better with lower voltage and on stock always hit powerlimits (hotspot temp) soo throttles frequency and clock stretches too. lol
> 
> On 3090 or likely even 3080ti's , you want to anchor it at 800-850mV
> There try to run 1806-1860. They run less frequency, but core is binned for far lower voltage
> 
> This will result in 80-100W drop, compared to stock and 10-15c less on the hotspot temp
> With nearly no performance regression
> Also you can nearly always add +200mem, but start with +100
> Lower voltage on the card allows for higher memOC
> 
> There is a step 3. to mark the 900-950mV range, by holding shift+drag leftclick, and subtly push it upwards near the 2000-2050 or 2100-2130 range (3080ti or 3090 & 3080 or lower)
> then the curve adapts to this little bump, as long as the shift range is selected and marked. But this can make it crash
> Be sure to disable L key to let it be dynamic boosting and lowering perf , again
> 
> At the very end, lower the powerlimit till you don't lose any score on superposition (more accurate/consistant than 3D mark i feel)
> ~ as the board will draw current, without really using it & the normal slider extender doesn't work well. Too many little core throttle options "on stock curve"
> Happy Overclocking


It's the same picture that was posted in the back. I don't know how to erase it, so I guess it happened.

It took 1.5v to 1.51v to perform trfc 240.

So, what I can try at this value is rttnom/7 rttpark/6 ? The bios memory voltage is 1.51v, but it is 1.53v in hwinfo64. I do not know how to touch the rt part, so I can keep the soc voltage and vddg iod cldo _vddp at the current level at 3800 and change the rtt value? I've always done all the overs while watching your information and always thank you. Mr.veii's words are always the best information for me You are the best!!


----------



## ManniX-ITA

Veii said:


> ManniX is fully right but a wording missunderstanding


Yes, you said it better 



Veii said:


> @ManniX-ITA i saw you got a 3080ti ?
> I've been playing the recent 2-3 recently with 2 3080s and a 3070 (3060 fun misses)
> * warzone stability only matches firestrike extreme stability, Timespy and superposition matter for something else


Ah... I'll probably regret it and tomorrow will cost half but whatever 

I'm using Metro Exodus with custom settings to test, seems to be the only one really uncovering stability issues:










If it's surviving 15 iterations, good to go.
Ray Tracing Ultra is a must to test memory overclock.
If you use something without RT then memory could be unstable.

Did an attempt with the curve like I was with my GTX1070 and got bad results...
Now I've spent a few hours to find at least a baseline:










More than this will crash.
Power limit can go up to 110% but doesn't really matter with temp limit at 83c. Anything more will crash in the long run.
It's also 30c ambient today and side by side with a 5950x on air cooler 

Temperature is the main constraint; this classic tri-fan setup without the hole doesn't seem to be enough.
This card is really set to the limit already.
Could be also bad thermal paste and bad/missing thermal pads.
Anyway, I'll (hopefully) soon replace it with a waterblock.

I will immediately test with your suggestions, thanks a lot it was exactly what I needed 

The card is peaking up to 420W, the BIOS limit is 440W and target 400W.
When it's crashing it's hard. Full system shutdown and the reboot but no POST.
Almost seems a power issue if it wasn't that I have a 1.3kW PSU and the Unify-X has all 3x12V PCI-E power cables connected...

From the reviews seems it's a bad binning but I'm not sure, the ambient temperature is too high to judge.
When it's below 70c the clock jumps easily to 2175 MHz and keeps a 2050 MHz sustained for a little.

There's also a .15 BIOS, I have .13:

MSI RTX 3080 Ti VBIOS 

Not sure it's worth trying as MSI is not publishing it.
Not a different memory IC for sure as it's always Micron.
Too big the risk of bricking to blind test...


----------



## XPEHOPE3

Gigabyte employee: AMD requested to remove all Beta's with 1.2.0.2.

If anyone's interested


----------



## Nighthog

@Veii 

Got any clue what might be the issue with this kit of memory?

I have a HyperX 2x16GB 3600 18-22-22 1.35V kit that is behaving oddly when I increase voltage & frequency. 
It's 16Gbit Micron Rev.E, single rank.

Basically the maximum allowed voltage to have the system work, not freeze or reboot decreases the more you increase the frequency they run at.
You reach a limit ~4200Mhz where you can not use more than ~1.450V for the dims if you put any kind of load on the memory the system will freeze/reboot with more voltage. 
4133Mhz ~1.500V is OK but not much more.
4266Mhz you need less than 1.400V etc.

This kit has behaved the same both on my X570 Xtreme and my cheap B550MH, with both my 3800X/4650G processors. 

Might be a RTT or DrvStr issue?
I've not tested them out much but this issue is crippling the fun and was guessing you might have a clue what it might be with your experience.
Wanted to play with them a little but saw that it had the same issue on my B550MH motherboard putting a stop to more exploration as it is for the moment.


----------



## mongoled

Veii said:


> Not directly - it's common to have an AC across hot locations
> With a difference of over 10c - kim ment that the room is 24c at the moment ~ not direct blast, else idle wouldn't be in the 40s


This does not explain the abnormally high CB23 score using PBO/CO.

That's why I asked if the score he showed was using a stable CO setup.

The highest score I have reached using PBO/CO in 28C ambient is 124xx using -24 on all cores. But as we all know this it far far from being a usable state for a working OS.

So I did some experimentation, even a 4.7 Ghz all core clock without using PBO does not score in the 124xx range.

So would like to know how Kim was able to post a 125xx score

Ughhhh, its a 4.81 fixed clock, that's why, need to look at the pictures more carefully!

4.8 Ghz fixed clock 28C 26C ambient


----------



## mongoled

kim nk said:


> The weather in Korea is over 30 degrees, so hot that you have to turn on the air conditioner. Cinebench set the air conditioner at 22 degrees and ran it. Maybe the room temperature is 24 degrees or so. Lol, I'm interested in rtt these days. It's too difficult to do rtt depending on the voltage requirement. crying 😭


I worked it out, you are not using PBO but a fixed overclock with slight BCLK giving you 4.81 Ghz frequency


----------



## kim nk

mongoled said:


> I worked it out, you are not using PBO but a fixed overclock with slight BCLK giving you 4.81 Ghz frequency


That's right! The ppt tdc edc is free


----------



## sendap

Wondering if can improve anything on this setup. It is stable 
2x16GB Flare X B-Die, partnumber K4A8G085WB-BCPB 

Dimm Temp max 47C during TM5. Agesa 1.2.0.2. Hwinfo 1.46v (Bios 1.44v)


----------



## mongoled

sendap said:


> Wondering if can improve anything on this setup. It is stable
> 2x16GB Flare X B-Die, partnumber K4A8G085WB-BCPB
> 
> Dimm Temp max 47C during TM5. Agesa 1.2.0.2. Hwinfo 1.46v (Bios 1.44v)
> 
> View attachment 2514266


Its already excellent, next step up you need a big jump on vDIMM


----------



## kim nk

[QUOTE = "kim nk, 게시물 : 28827974, 회원 : 641452"]
rt 7/0/6 드럼 전압 1.52v tm5를 19 회 구동하면서 pt tdc edc 값을 확인한 후 이제 자유 로워졌습니다. 바이오스에서 가능 해졌다
View attachment 2514264

[/인용문]


----------



## craxton

ManniX-ITA said:


> If you can I'd really appreciate if you could write more polished and structured...


i suppose on this, id have to go with the fact that i wrote several things.
then stopped, then started again, and all while reading other places.
English is my native, but at the same time is it bc sometimes it doesnt seem to be?
ill admit there is a few hard spots in what i wrote that i had to re-read too 
but if you knew me, youd know structure (in general) isnt very well maintained.
if you have to re-read this, then ill have to start picking up a new language and consider English my secondary.



Spoiler



my grandpaw passed, so im fritzing if its not easy noticed by the sheer spam in my posts the last few days.
only thing to knock the thought is OC'ing.



(EDIT) this is the best R20 score ive "EVER" gotten.
the other runs shown in the last post i made were on the same agesa 
just with wide open EDC limit of 420. 



ManniX-ITA said:


> If you get higher scores and the EDC limit to high percentage (like the 6752.2% in your screenshot) then it's working.
> Is that a better score than the usual?
> If so what AGESA version are you using?


this is by far the highest score ive gotten, all while having less on "150mhz auto oc" as usually its 200mhz
im on 1.2.0.2 latest patch for the b550 board, while noting that im using a modded bois/unlocked-unhidden.
DF states are not turned off, CPPC is on, i think you seen the hwinfo shot wrong. unless im reading it wrong?
it shows 67.252a max on EDC and TDP.

EDC is set to 1 in bios, "tool" shows its set to 1









since system info report in OCCT says EDC is 90A "FUSED" id have to assume
that the "oversized" values inside the bios are simply allowing the chip to hit (close to that) 90a fused limit.
or would it already go over that " 1 " value i manually set? i thought i was reading others state it was simply locking them
to what they had set?












mongoled said:


> Or because you have "****ty" cores they leave more power budget to the IOD, just another food for though


yes my cores are ****ty, but wouldn't that mean its taking more power to run
these cores at the same frequency range others would normally have?

my old IOD and CCD values were 1070iod and 1000 CCD
unless im wrong and more voltage being supplied to the cores since its a "leaky" silicon
would give more headroom for IOD, CCD. 

(on older agesa) i couldnt run at 1.1 SOC but i hadnt lowered IOD nor CCD either.
this agesa might be broken but on this B550 board its been the best one yet since patch C/B


----------



## sendap

mongoled said:


> Its already excellent, next step up you need a big jump on vDIMM


thanks a lot for your input. Waiting for a possibilty to go highter on IF in the future then...


----------



## mongoled

craxton said:


> i suppose on this, id have to go with the fact that i wrote several things.
> then stopped, then started again, and all while reading other places.
> English is my native, but at the same time is it bc sometimes it doesnt seem to be?
> ill admit there is a few hard spots in what i wrote that i had to re-read too
> but if you knew me, youd know structure (in general) isnt very well maintained.
> if you have to re-read this, then ill have to start picking up a new language and consider English my secondary.
> 
> 
> 
> Spoiler
> 
> 
> 
> my grandpaw passed, so im fritzing if its not easy noticed by the sheer spam in my posts the last few days.
> only thing to knock the thought is OC'ing.
> 
> 
> 
> (EDIT) this is the best R20 score ive "EVER" gotten.
> the other runs shown in the last post i made were on the same agesa
> just with wide open EDC limit of 420.
> 
> 
> this is by far the highest score ive gotten, all while having less on "150mhz auto oc" as usually its 200mhz
> im on 1.2.0.2 latest patch for the b550 board, while noting that im using a modded bois/unlocked-unhidden.
> DF states are not turned off, CPPC is on, i think you seen the hwinfo shot wrong. unless im reading it wrong?
> it shows 67.252a max on EDC and TDP.
> 
> EDC is set to 1 in bios, "tool" shows its set to 1
> View attachment 2514263
> 
> 
> since system info report in OCCT says EDC is 90A "FUSED" id have to assume
> that the "oversized" values inside the bios are simply allowing the chip to hit (close to that) 90a fused limit.
> or would it already go over that " 1 " value i manually set? i thought i was reading others state it was simply locking them
> to what they had set?
> 
> View attachment 2514267
> 
> 
> 
> yes my cores are ****ty, but wouldn't that mean its taking more power to run
> these cores at the same frequency range others would normally have?
> 
> my old IOD and CCD values were 1070iod and 1000 CCD
> unless im wrong and more voltage being supplied to the cores since its a "leaky" silicon
> would give more headroom for IOD, CCD.
> 
> (on older agesa) i couldnt run at 1.1 SOC but i hadnt lowered IOD nor CCD either.
> this agesa might be broken but on this B550 board its been the best one yet since patch C/B


To be honest with you I dont like the meaning of "best" cores as defined by AMD

🤣

The reason is simple, most people will automatically think the best core is the one that boosts higher, but this is not really what happens for every single core.

My understanding is the "best" core is given this designation if it is able to run X frequency with less voltage than the other cores on the same CPU and hold that load for a bigger duration.

But as we know the V/F curve changes as we scale up/down voltage and we cant assume that this scaling stays the same for any core!

Example, my "best" cores need positive CO offset, while the others all take negative offset, but when I check to see what they boost to you would assume that the best cores would boost to a higher frequency than the others, but this is not the case all of the time, hence the reason I no longer look at the cores as best or worse, I just do my best to give them what CO they need to run X frequency and not worry about if one needs positive offset and other needs negative


----------



## kim nk

Veii said:


> Can you redo this post - the pictures are gone from the server  ?
> 
> Not directly - it's common to have an AC across hot locations
> With a difference of over 10c - kim ment that the room is 24c at the moment ~ not direct blast, else idle wouldn't be in the 40s
> 
> DF_C-States are a complicated topic
> They cause overboost issues, little overboost spikes sometimes between P-States , but mostly from full suspension
> HWInfo isn't able to always track it & considering people told Martin (dev) that this could be a bug ~ i wouldn't wonder if it was tried to be masked and "smoothed out"
> 
> APCI Performance Index, under the Performance Tracking setting (% Processor Performance),
> Does still track them ~ but you need to click on one little tab to change the range from 100 to 200
> 
> My wording was, that since AGESA 1.1.0.0C/D - Patch D which is 1180/81 == 1191 == 1200+ (annoying beta bios spread)
> Several attempts where made to cover that boosting issue.
> From the chipset powerplans with disabled hibernation (deep sleep) to Bioses changing the Auto value "meaning" from Enabled , to Disabled
> 
> It was always on Auto, soo sometimes it means Enabled, sometimes it means disabled
> Now thinking about it, maybe "enabled" with powerplan "disabled" method ~ could result internally in more power reserves
> But the fact stays, that they cause overboost issues and idle crash or random reboot units.
> Maaybe it's fixable with a bit of DPM tweaks and maybe fixable with different CO
> (my powerplan mess, caused abusage of overboost with a frequency limiter ~ soo usage of DF_State only had benefits, as cache could even boost higher that way)
> 
> But non the less, it is more than buggy - and i strongly suggest to disable it, till AMD fixes their Boosting Table mess
> They tried to rewrite it fully on 1200A/1201 but it still is an issue even at 1203A (not everyone got A ,and no SMU version shows a difference if it's A or nonA)
> Overall it's a mess, and you shouldn't trust AUTO on anything
> You shouldn't trust chipset drivers to have only the public visible changes, they love to sneak gremlins into it
> While playing with bioses between Patch C and 1200 pure, i usually used a very old Chipset driver ~ because the new ones messed with the powerplans
> Today, i just don't install the powerplans at all anymore & use Windows High-Perf for preventing overboost (using powerplan explorer to unhide the two maximum frequency limits & set them bellow 5ghz)
> 
> Soo even if through some magic overboost happened - it will be hard capped on a 2nd stage and be cut , without it ever reaching 55ghz and hardcrashing
> 
> @kim nk stay cautious with this 1.51v at RTT_PARK /5
> If you use 1202 and higher, drop procODT once - and drop RTT_PARK to lower value (a higher divider /6 and more)
> Use RTT_NOM /7 once you exceed 1.46v. Range is from 1.48v but 1.46v does count if you ever used more ClkDrvStr (30+)
> 
> 4 dimms would need RTT_WR , starting with RZQ /3 and lower
> Getting /2 to run is a big benefit, but it's mostly only running beyond 1.58v or with very strong Ampere reaching the dimms (low RTT_PARK and strong ClkDrvStr)
> Low RTT_PARK (strong ohm value) is not a good idea on it's own , as it increases heat creation too much
> 
> 
> 
> 
> 
> 
> 
> 
> This is what it settled for now, but was riding the 620 train before
> When you reach 737 RTT , then changing RTT_WR the middle value to /2
> If you do so (RZQ/2), then RTT_NOM and RTT_PARK "reset" .
> You start with low strong values again like 625 and lower 724. Someday you can reach 727 or 620
> 
> RTT_NOM nearly always depends on used voltage. You will notice when you need to increase it
> More NOM, is fine ~ it is needed when you run strong voltage
> But all is a balance thing.
> 
> Balance thing because ClkDrvStr is the "main" powering thing
> Too much ClkDrvStr and too much PARK - will make issues
> A lot of ClkDrvStr and no PARK, will make less issues
> A lot of VDIMM and a lot of PARK , can kill dimm sticks (can kill the PCB)
> 
> This is a wording missunderstanding,
> ManniX is fully right but a wording missunderstanding
> 
> Y-cruncher you should run with XMP on stock , to finetune your procODT/VDDP/VDDG range / and to verify your sample is not defect by the factory
> Also to finetune your loadline droop
> (more droop is often better with Vermeer - except for CTR usage. Less switching freq is better for lower ripple, find the balance between loadline and "enough" switching frequency)
> 
> It is recommended to disable every little manufacture cheating ~ including every performance enchancers, enable PBO with the stock limits and scalar set to X1 (boardpartners love to use X2)
> Often it's easier to just change the scalar in AMD CBS - without touching PBO, because PBO will add more vcore.
> Soo be sure FCLK and the CPU is stable and extend your XMP profile a bit higher in frequency or lower in frequency (the good thing when you buy 4000+ kits)
> 
> Y-cruncher is slightly sensitive to memOC , but FFT test can error because of both
> Vermeer is fantastic at autocorrection, don't forget that please. Y-cruncher is a calculated result, but like SuperPi 1.5SX , it's not too harsh on the dimms
> 
> TM5 is a purely memory sensitive test, and not even an FCLK sensitive one
> Error 6 mostly relates to both (majorly broken primaries & other timings) or (majorly broken voltages and FCLK crashes)
> TM5 is able to run with crashing cores - but will trow a thread-exception handler, if one crashes. Then it will stop but the timer will keep running
> 
> Two more notes on both topics,
> CTR does force-enable DF_C-States.
> CTR is made to catch crashing cores in time, but the Overboost issue [boosting bug] will still cause issues
> Soo it is strongly recommended to ignore AMDs powerplans (they are a mess because of the DF bug, sorry AMD) and ignore windows ultimate powerplan (it's also a mess)
> Use highperf with a frequency limiter (if you have crashes) to catch the boosting spikes & consider that even CTR can randomly cause a crash while running TM5 on it
> Soo once CTR crashes, TM5 will also crash ~ keep this in mind (it happened to me)
> 
> 
> Spoiler: Something else funny happened to "me":
> 
> 
> 
> 
> View attachment 2514238
> 
> 
> 
> This has silicon score of 112 [remote system]
> I noticed only later that the setup had -30 on the first CCD and -22 on the 2nd CCD , with +30mV offset and vdroop at lv 5
> 
> Soo i learned here that you can utilize another way of running CTR (well overboosting the overboost CTR feature) but more extreme :^
> If you use a very strong loadline , and still add an offset ontop. You can get it nearly similar where CPU_TEL is identical to CPU_VID
> Here i messed up slightly, but yes 5200 could run
> 
> Normal CTR usage only allowed 4850 or 4900
> Soo this should trick FIT too (deepest loadline with highest negative CO and positive vcore to compensate for straps jumping/switching)
> I need to explore this further, but my current OS (main system) doesn't open public CTR 2.1 (he released the public version to the community because of bigger plans behind the stage)
> 
> It runs for me, but since 1100A i commented that it is bad on Vermeer
> Because it can package throttle on many parts - unlike Matisse, this one results in +30ns L3 and 172ns memory latency
> 
> Value 2 works, 3 is accepted as EDC3 = 550mhz constant throttle and laggy bios
> 1 could be recognized by FIT and stop the nonsense
> ==============================================
> @ManniX-ITA i saw you got a 3080ti ?
> I've been playing the recent 2-3 days, with 2 3080s and a 3070 (3060 fun misses)
> * warzone stability only matches firestrike extreme stability, Timespy and superposition matter for something else
> 
> A little advice:
> MSI Afterburner, max out the powerlimit, max out the thermal limit (keep in mind some bioses can have 350W some 450W limits)
> then change the slider to -200 to -150Mhz on core
> Open the Curve editor:
> 
> For a 3080, you want to grab 850-881mV strap and move it to 1950mhz , and press L to force the freq + apply
> Start that way and verify it's firestrike extreme + unigine superposition (1080p extreme windowed ~ custom) , stable
> Then you can go up to 2100 at the same 850mV strap
> RTX Ampere scales better with lower voltage and on stock always hit powerlimits (hotspot temp) soo throttles frequency and clock stretches too. lol
> 
> On 3090 or likely even 3080ti's , you want to anchor it at 800-850mV
> There try to run 1806-1860. They run less frequency, but core is binned for far lower voltage
> 
> This will result in 80-100W drop, compared to stock and 10-15c less on the hotspot temp
> With nearly no performance regression
> Also you can nearly always add +200mem, but start with +100
> Lower voltage on the card allows for higher memOC
> 
> There is a step 3. to mark the 900-950mV range, by holding shift+drag leftclick, and subtly push it upwards near the 2000-2050 or 2100-2130 range (3080ti or 3090 & 3080 or lower)
> then the curve adapts to this little bump, as long as the shift range is selected and marked. But this can make it crash
> Be sure to disable L key to let it be dynamic boosting and lowering perf , again
> 
> At the very end, lower the powerlimit till you don't lose any score on superposition (more accurate/consistant than 3D mark i feel)
> ~ as the board will draw current, without really using it & the normal slider extender doesn't work well. Too many little core throttle options "on stock curve"
> Happy Overclocking


Thank you feedback was received and modified to rt 7/0/6 1.51v-->1.52v vddg cd 1.00 -> vddg cd 0.94 vddg iod 1.05--->1.06 soc 1.1 --> 1.106 llc 4 and passed tm5 20 times. If you tell me the wrong timing or improvement, I will try hard to fix it. Thank you for always giving me good information!


----------



## XPEHOPE3

@kim nk BTW did you use some formula for tRC? tRP+tRAS+something to make it work?


----------



## Taraquin

mongoled said:


> Or because you have "****ty" cores they leave more power budget to the IOD, just another food for thought....
> 
> 😊😊


I wish it was that easy, but my 5600X seems like a quite good bin as I can do CO -30 all core and run PBO +50MHz 100% stable. [email protected] also works so no bad cores, but maybe no golden cores either.


----------



## kim nk

XPEHOPE3 said:


> @kim nk BTW did you use some formula for tRC? tRP+tRAS+something to make it work?


trcdwr 8+trp 13 = tras 21, tras 21 + trp 13 = trc = 34, but trtp x trc = trfc came out too low, so we gave it a free value. 😓


----------



## mongoled

Taraquin said:


> I wish it was that easy, but my 5600X seems like a quite good bin as I can do CO -30 all core and run PBO +50MHz 100% stable. [email protected] also works so no bad cores, but maybe no golden cores either.


I max out it out to +200 and tune each core independantly, obviously its not going to run CO at -30.

Have you validated your results using that -30 setup as you may be loosing performance with "clock shrinking" as opposed to "clock stretching" if the cores are not getting enough voltage ...


----------



## ManniX-ITA

craxton said:


> English is my native, but at the same time is it bc sometimes it doesnt seem to be?
> ill admit there is a few hard spots in what i wrote that i had to re-read too


Yes, always re-read what you wrote before posting 
I do it always and the few times I forget it, I regret it
Sometimes after extensive corrections I come back after 5 minutes and wonder what the frack I meant to say...
Mine is just a wish, don't feel obliged to! Be free
I'd like yo read your posts but as I said I'm really struggling 



Spoiler



Sorry for your loss 





craxton said:


> this is the best R20 score ive "EVER" gotten.
> the other runs shown in the last post i made were on the same agesa


If that's the real best than maybe it's working
On my 5950x the EDC bug works till 5, above and it really tries to enforce it and as said by Veii got 500 MHz cores and sluggish system.
Problem is that it doesn't help like on the 3000, quite the opposite
Cinebench R23 scores are dropping into 28K instead of 29-30K
Which is better than stock settings but worse than good PBO settings



craxton said:


> i think you seen the hwinfo shot wrong. unless im reading it wrong?


You have to look at *CPU EDC Limit, *not at CPU EDC:










If it's overriding the 100% big time then it's "working".
Meaning it's not enforcing the limit but not necessarily giving you a boost.
In my case is overriding as well but I don't get any boost only worse performances.


----------



## CarnageBT

Got it stable! The weird thing is the tRDRDSCL/tWRWRSCL 2/2, was the setting holding it back. Check the bottom of the chart, I've highlighted the 2 identical runs aside from the tRDRDSCL/tWRWRSCL setting. @mongoled











**All settings below referring to pictured are the ZenTimings above ^^*


*All 4 DIMMs populated*Picturedcycle 9, ~ 55m, error 81.52 vdimmcycle 5, ~ 25m, error 12Pictured, tWTRL 10 (from 8)cycle 7, ~40 mins, error 0tRRD 4/6 + tWTRL 10 (from 8)cycle 4, ~ 23, error 7, then 11, 12, 1 through 37mPictured, tCKE 9cycle 1, error 8, 8, 8, 8,tCKE 9 + CsOdtSetup CkeSetup 56-56-56cycle 8, ~50m, error 1, ran for 65m, no other errorsPictured, tCKE 1 + CsOdtSetup CkeSetup 56-56-56cycle 11, ~70m, error 7, ran for 80m, no other errors1.51 vdimm2 Cycles, ~20m, error 7, 7, ran for 35m*Pictured + 1.49 vdimm + 56-56-56**Cycle 12, ~75m, error 11, ran for 88m, no other errors*Pictured + 1.49vdimm, tRAS 29, tRC 43, tRFC x6, 56-56-56Cycle 4, ~25m, error, 1, 1Pictured + 1.5vdimm, tRAS 29, tRC 43, tRFC x6, 56-56-56Cycle 1, error 7Pictured + 1.5 VDIMM, tRAS 29, tRC 43, tRFC x6, 56-0-0Cycle 2, error 8Pictured + 1.49 VDIMM, tRAS 29, tRC 43, tRFC x6, 56-0-0Cycle 5, error 1, 0Pictured, 1.49 vdimmcycle 10, 60m, error 1tRDRDSCL/tWRWRSCL - 2/2, 1.49 vdimm, 56-0-025 cycles, 2h43m, error 1, 1, 1 (62mins in), 0, 4*tRDRDSCL/tWRWRSCL - 2/2, 1.49 vdimm, 56-56-56**25 Cycles. PASSED!*

Final Settings (not the "pictured" settings referred to in the chart above):









I'll attach 3 runs of Aida (discarding the 1st) in thumbnail. Do the results look ok? Are there any variances that are too large implying problems? Sorry, I don't know any of the rules or things to look for aside from latency of greater than 0.1ns difference.


----------



## mongoled

CarnageBT said:


> Got it stable! The weird thing is the tRDRDSCL/tWRWRSCL 2/2, was the setting holding it back. Check the bottom of the chart, I've highlighted the 2 identical runs aside from the tRDRDSCL/tWRWRSCL setting. @mongoled
> 
> 
> *All 4 DIMMs populated*Picturedcycle 9, ~ 55m, error 81.52 vdimmcycle 5, ~ 25m, error 12Pictured, tWTRL 10 (from 8)cycle 7, ~40 mins, error 0tRRD 4/6 + tWTRL 10 (from 8)cycle 4, ~ 23, error 7, then 11, 12, 1 through 37mPictured, tCKE 9cycle 1, error 8, 8, 8, 8,tCKE 9 + CsOdtSetup CkeSetup 56-56-56cycle 8, ~50m, error 1, ran for 65m, no other errorsPictured, tCKE 1 + CsOdtSetup CkeSetup 56-56-56cycle 11, ~70m, error 7, ran for 80m, no other errors1.51 vdimm2 Cycles, ~20m, error 7, 7, ran for 35m*Pictured + 1.49 vdimm + 56-56-56**Cycle 12, ~75m, error 11, ran for 88m, no other errors*Pictured + 1.49vdimm, tRAS 29, tRC 43, tRFC x6, 56-56-56Cycle 4, ~25m, error, 1, 1Pictured + 1.5vdimm, tRAS 29, tRC 43, tRFC x6, 56-56-56Cycle 1, error 7Pictured + 1.5 VDIMM, tRAS 29, tRC 43, tRFC x6, 56-0-0Cycle 2, error 8Pictured + 1.49 VDIMM, tRAS 29, tRC 43, tRFC x6, 56-0-0Cycle 5, error 1, 0Pictured, 1.49 vdimmcycle 10, 60m, error 1tRDRDSCL/tWRWRSCL - 2/2, 1.49 vdimm, 56-0-025 cycles, 2h43m, error 1, 1, 1 (62mins in), 0, 4*tRDRDSCL/tWRWRSCL - 2/2, 1.49 vdimm, 56-56-56**25 Cycles. PASSED!*
> 
> Final Settings:
> View attachment 2514277
> 
> 
> I'll attach 3 runs of Aida (discarding the 1st) in thumbnail. Do the results look ok? Are there any variances that are too large implying problems? Sorry, I don't know any of the rules or things to look for aside from latency of greater than 0.1ns difference.


Great result, just unsure if you misunderstood ManniX-ITA and myself.

We both said to use 4 or 5 for tRDRDSCL/tWRWRSCL when using 32GB.

I have not understood if thats what you tried but had issues ?

Everything else looks where it should be


----------



## ManniX-ITA

Veii said:


> There is a step 3. to mark the 900-950mV range, by holding shift+drag leftclick, and subtly push it upwards near the 2000-2050 or 2100-2130 range (3080ti or 3090 & 3080 or lower)
> then the curve adapts to this little bump, as long as the shift range is selected and marked. But this can make it crash
> Be sure to disable L key to let it be dynamic boosting and lowering perf , again


I don't understand how to achieve the step 3 
Shift+drag LeftClick will remove the curve and just set +n frequency from that point...

Works quite well at 1860 MHz at 850mV. But I'm not ready yet to save power...
The sweet spot for 83c is 950mV at 1935 MHz.

Now I'm trying this profile with 925-975mV strap set for +90/1965MHz for 950mV.
Gives a very stable 1920-1935 MHz clock with few drops under Unigine and almost flat 1935 on FSE and Metro Exodus.
Still allows some substantial boost to 1965 MHz with lighter load.
Have to test more, not sure it's better than the +66 with a small bump at 950mV for 1980 MHz.
More or less produces the same result but with much more boosting toward 2025 MHz with light load.
I see some stuttering with metro Exodus but I'm not sure it's cause the profile or some background mess, have to test on the benching install.


----------



## CarnageBT

mongoled said:


> Great result, just unsure if you misunderstood ManniX-ITA and myself.
> 
> We both said to use 4 or 5 for tRDRDSCL/tWRWRSCL when using 32GB.
> 
> I have not understood if thats what you tried but had issues ?
> 
> Everything else looks where it should be


I've edited my original post to be more clear and included the referenced "pictured" settings from the chart.

But yes. I understood and did all the testing with tRDRDSCL/tWRWRSCL 4/4 but failed. Oddly, when I changed back to 2/2 is when it passed. I highlighted the 2 identical runs I performed with the tRDRDSCL/tWRWRSCL setting being the only difference. I could try 5/5 but should I if 2/2 has passed?


----------



## ManniX-ITA

CarnageBT said:


> But yes. I understood and did all the testing with tRDRDSCL/tWRWRSCL 4/4 but failed. Oddly, when I changed back to 2/2 is when it passed. I highlighted the 2 identical runs I performed with the tRDRDSCL/tWRWRSCL setting being the only difference. I could try 5/5 but should I if 2/2 has passed?


I'd check if something changes in speed with different SCL values.
But otherwise is really good! There's not much room left for improvement already.
Maybe test as it is but with GDM enabled; if something in AIDA is improving then you can still make it better.


----------



## mongoled

CarnageBT said:


> I've edited my original post to be more clear and included the referenced "pictured" settings from the chart.
> 
> But yes. I understood and did all the testing with tRDRDSCL/tWRWRSCL 4/4 but failed. Oddly, when I changed back to 2/2 is when it passed. I highlighted the 2 identical runs I performed with the tRDRDSCL/tWRWRSCL setting being the only difference. I could try 5/5 but should I if 2/2 has passed?


I am unsure if the voltage you are using is enough for running CAS @14 and that the results you are getting are reproducible over several TM5 runs etc.

Anything you decide to do is really up to you, think you have a grasp of what to do now, you learned alot, no need to be afraid

 

Did you compare your throughput results in AIDA64 when using 4/4 compared to 2/2 ?

4/4 gives around 300-400 mbytes/s more bandwidth compared to 2/2 but this may not be the case for all setups !


----------



## CarnageBT

ManniX-ITA said:


> I'd check if something changes in speed with different SCL values.
> But otherwise is really good! There's not much room left for improvement already.
> Maybe test as it is but with GDM enabled; if something in AIDA is improving then you can still make it better.





mongoled said:


> 4/4 gives around 300-400 mbytes/s more bandwidth compared to 2/2 but this may not be the case for all setups !


I did notice approximately 150-200 increase in my read but with a corresponding decrease to my write (At 3667). I'm happy to test it but the problem is I fail TM5 with it set at 4/4

I will test this with GDM enabled to see

When you say voltage may not be enough, I assume you're referring to VDIMM? I will retest it overnight tonight.

@mongoled how did you calculate your tRAS and tRC? I saw @domdtxdissar has the same speeds
I intend on trying that later


----------



## mongoled

CarnageBT said:


> I did notice approximately 150-200 increase in my read but with a corresponding decrease to my write (At 3667). I'm happy to test it but the problem is I fail TM5 with it set at 4/4
> 
> I will test this with GDM enabled to see
> 
> When you say voltage may not be enough, I assume you're referring to VDIMM? I will retest it overnight tonight.
> 
> @mongoled how did you calculate your tRAS and tRC? I saw @domdtxdissar has the same speeds
> I intend on trying that later


Me thinks you have the "tweaking" bug, poor wifey

😀😀

At its simplest tRC = tRP + tRAS so in my case 14 + 26 = 40

But......tRAS is usually tCL + tRCDRD + 2 so in my case 14 + 15 + 2 = 31 but whooooaaaaaaa I have it set to 26

Why 26 ? I just kept forcing it lower and lower while testing, testing, testing, your milage may vary



Yeah vDIMM!


----------



## T[]RK

ManniX-ITA said:


> I also suspect you are starving voltage, set SOC at 1.12V and CCD/IOD at 1050mV, check if you get a performance bump.


Nope. Here is result with vSOC=1,144mV








And result with same vSOC + IOD=1,050mV








No performance bump.  I guiess it's just "weak" board. I don't know where are 2000 MB\s of Copy are lost...


----------



## ManniX-ITA

T[]RK said:


> I don't know where are 2000 MB\s of Copy are lost...


Bad lead 
I have improved the Copy BW with better tWTR/tRTP/tWR/tRDWR/tWRRD combinations.
Lower numbers don't give you better performances.
I'm more worried about the 2ns latency lost somewhere... but I don't really see anything that could cause such a big drop.
Do you have maybe virtualization enabled?


----------



## T[]RK

ManniX-ITA said:


> Bad lead


Maybe. 



ManniX-ITA said:


> Do you have maybe virtualization enabled?


Yes i do (SVM Mode was enabled in BIOS)! Now it's disabled, take a look.







Same result. =) Haha


----------



## XPEHOPE3

Sorry for long post 🤓


Veii said:


> TM5 is able to run with crashing cores - but will trow a thread-exception handler, if one crashes. Then it will stop but the timer will keep running


I haven't seen any messageboxes with such crashes. I manged to watch the process live just now: it started _freeing memory long before_ the last 15 test (cycle 12 error-free), I saw ...,7,8,1,11,15 tests to go with gradually *MORE *available memory from 50GB to 62GB, and with from only 12GB pagefile to 6GB pagefile, while on the start it was less than 1GB available memory and 72+GB page file. Also those tests were running very fast. Very strange..... I decided to run it once more with HWinfo with alert on too much free RAM. Maybe all of those error-free cycles were fake (were run on not all the memory available). Currently it appears that on pre-last test (11) TM5 unexpectedly freed 5GB memory (not all cores were 4650 effective clock during this, but vcore was 1.344 in comparison to 1.344-1.368 usual for TM5 runs, VIN0 dropped from 1.815V to 1.804V, while CPU VDD18 is 1.815 rock solid), then during test 15 it freed all the memory, then reclaimed it back on the next cycle start.


Veii said:


> Less switching freq is better for lower ripple, find the balance between loadline and "enough" switching frequency)


That all sounds Greek to me 😅 😅


Veii said:


> Y-cruncher you should run with XMP on stock , to finetune your procODT/VDDP/VDDG range / and to verify your sample is not defect by the factory
> Also to finetune your loadline droop
> (more droop is often better with Vermeer - except for CTR usage. Less switching freq is better for lower ripple, find the balance between loadline and "enough" switching frequency)
> 
> It is recommended to disable every little manufacture cheating ~ including every performance enchancers, enable PBO with the stock limits and scalar set to X1 (boardpartners love to use X2)
> Often it's easier to just change the scalar in AMD CBS - without touching PBO, because PBO will add more vcore.
> Soo be sure FCLK and the CPU is stable and extend your XMP profile a bit higher in frequency or lower in frequency (the good thing when you buy 4000+ kits)
> 
> Y-cruncher is slightly sensitive to memOC , but FFT test can error because of both
> Vermeer is fantastic at autocorrection, don't forget that please. Y-cruncher is a calculated result, but like SuperPi 1.5SX , it's not too harsh on the dimms
> 
> TM5 is a purely memory sensitive test, and not even an FCLK sensitive one
> Error 6 mostly relates to both (majorly broken primaries & other timings) or (majorly broken voltages and FCLK crashes)


Thank you for all the time you spent answering!! But being a novice I think I wouldn't make it without more detailed directions 🙄
For example, from what you wrote here I gather there is no test to ascertain FCLK stability (not TM5, not y-cruncher, nothing else was mentioned).
Moreover, what's "finetune" here:


Veii said:


> Y-cruncher you should run with XMP on stock , to *finetune* your procODT/VDDP/VDDG range / and to verify your sample is not defect by the factory
> Also to *finetune* your loadline droop
> (more droop is often better with Vermeer - except for CTR usage.


For example, igorslab says for CTR "As an LLC, you should choose a level that achieves between 1 and 3 percent Vdroop at 100% CPU load." That's pretty precise direction, I must say! I only need to know how to measure Vdroop to follow it (Vcore I've set in BIOS minus Vcore from HWInfo, I guess). And then I don't need to change Vcore LLC.
I assume you were talking about Vsoc loadline, not Vcore loadline? Or both?? Do I need to change it after I finetune it for XMP on stock? Yesterday I tried searching your posts on this forum for "vSOC LLC" and got nothing really relevant on what to aim for  Guess I need to also search for "Vsoc loadline", or just "loadline". I also was thinking to use *the same* memory OC for Windows with CTR and Linux with PBO2+CO (since there's no CTR for Linux). That's why I went for memory OC *before* CPU OC (as CTR recommends ensure stable memory first). Guess I have to ditch CTR then if it requires different Vsoc LLC and hence different memory OC.

The other question is about "Y-cruncher you should run with XMP on stock , to *finetune* your procODT/VDDP/VDDG range". What "finetune" means here? Finding lowest y-cruncher-stable those 3 settings? How is changing procODT for XMP timings and voltage would help, if procODT for example depends on voltage, and for higher clocks I would need higher voltage anyway, rendering XMP-voltage-procODT-range knowledge irrelevant?
About VDDP/VDDG: well, ok, I would know the range, but then again I'm going to up VDIMM, powerbudget would change, VDDP/VDDG ranges would change. Not to mention the hell I gonna face upping Vcore  .

Then, do I really need to run exactly XMP on stock with AMD CBS scalar x1? Or it it possible to ensure *any *other CPU+RAM stable overclock before going further? E.g. I can ensure y-cruncher stable profile of PBO+auto scalar+*mobo *limits+3600memOC with timings from XMP (3200-CL14) VDimm 1.45, as it's much closer to what I'll be happy with.


----------



## CarnageBT

mongoled said:


> Yeah vDIMM!


Tried 1.51vdimm, error 14 after approximately 40 minutes. 1.5 may work, will test tonight. 

According to HWinfo, when I set 1.49 = 1.5, 1.5 = 1.51, 1.51 = 1.52

I'm going to see if I can run tRAS 26 lol.


----------



## XPEHOPE3

That rises the question: are there recommendations how to overclock memory (and CPU) to be AGESA-update-stable? I assume one has to not finetune memory but leave some wiggle room for all the settings. That probably means RTTs on Auto, only playing with LLC and voltages (and maybe CAD_BUS), 1900 FCLK max, tRC being higher than tRP+tRAS, tRTP only 8, etc? Can anyone share an example overclock *stable through at least two AGESA updates*? Anyone had the experience of having to _redo GDM ON_ memory OC after an AGESA update? Or are mostly GDM _OFF _overclocks affected?


----------



## sendap

T[]RK said:


> You mean "Copy"?  Write always stable at 30399 MB\s. Read close to "realistic" 57000 MB\s (ideal for 3800 MHz would be 60800 MB\s, but it's unreal).


yeah sorry, that is what i meant. mixed it up...


----------



## CarnageBT

While testing TM5, a BSOD normally means too little vSOC right?


----------



## MyUsername

CarnageBT said:


> While testing TM5, a BSOD normally means too little vSOC right?


Maybe, I usually find too little voltage causes the PC to restart without a bsod while doing nothing, you might be lucky for it to logged in the event log. Stabilize the SoC and IF before you consider stabilizing your memory with TM5, try y-cruncher as that can hammer the cpu, soc, imc and IF and quickly detect something.


----------



## CarnageBT

I'm re-tuning my curve (was originally tuned for 3600), now for 3800.

My question, do my memory power settings like vSOC, cldo VDDP, VDDG CCD/IOD, or VDIMM have a material effect on the CPU?


----------



## Taraquin

mongoled said:


> I max out it out to +200 and tune each core independantly, obviously its not going to run CO at -30.
> 
> Have you validated your results using that -30 setup as you may be loosing performance with "clock shrinking" as opposed to "clock stretching" if the cores are not getting enough voltage ...


Yep, it's works good, allcore runs at 4.6GHz, single at 4.7 with -30 CO, same score in CB20 as 4.6GHz static OC. I see no stretching so far, but if I try +100MHz pbo or more I get random reboots or freezes once or twice a day.


----------



## MyUsername

CarnageBT said:


> I'm re-tuning my curve (was originally tuned for 3600), now for 3800.
> 
> My question, do my memory power settings like vSOC, cldo VDDP, VDDG CCD/IOD, or VDIMM have a material effect on the CPU?


No. Leave the CO on auto for now and dial in the SoC if it bsods, if it's just whea bsod then you know the curve is too high. Be generous at first 1.15-1.2V, IF it's throwing whea's play with the VDDG's, it can be tedious af, as sometimes you think it's stable then a few days it's falling apart. Give the memory power, 1.4-1.45V for 3800 cl16 or 1.5V+ for cl14.


----------



## CarnageBT

MyUsername said:


> No. Leave the CO on auto for now and dial in the SoC if it bsods, if it's just whea bsod then you know the curve is too high. Be generous at first 1.15-1.2V, IF if it's throwing whea's play with the VDDG's, it can be tedious af, as sometimes you think it's stable then a few days it's falling apart. Give the memory power, 1.4-1.45V for 3800 cl16 or 1.5V+ for cl14.


I just finished dialing in my memory OC. Now going back over the CO to adjust for any changes. 

My mem OC is here
View attachment 2514277


Stability and aida results are on the prev page.

* The BSOD questions were because I was trying some crazy tRAS numbers that go against the standard formula


----------



## Veii

kim nk said:


> trcdwr 8+trp 13 = tras 21, tras 21 + trp 13 = trc = 34, but trtp x trc = trfc came out too low, so we gave it a free value. 😓
> 
> 
> kim nk said:
> 
> 
> 
> If you tell me the wrong timing or improvement, I will try hard to fix it. Thank you for always giving me good information!
Click to expand...

I think the set is flawless 
Only tRP would need to be 12 , but this requires more voltage - and more voltage means different RTT

Also it looks like it wants ClkDrvStr a bit ~ but your procODT is far lower than usual
This likely is the reason for low cLDO_VDDP

Test the timings and adjust procODT up and down 28-34ohm , 3 options one of 3 will only have zero variation on Aida64. 0.3ns or more is instability and autocorrection
Formula you used for tRAS is tRCDmax + tCCD_L or tBL


Spoiler














Currently it was used as 14+6=20 (bios issue soo 21)
tRC is tRCDWR+tCWL+tWR+tCCD_L or tBL
8+14+12+6=40

Both are issues because tRP + tRAS does not equal tRC
I think your tCCD_L is 6 here
Try maybe this first
(2T needed 1.54~, 1T needed 1.6v)








Next one is this but with your own RTTs








Looking at it now, it looks amateur 🙊
Too high tRDWR high SD,DD and not even tWR 10. Also ignore GDM, this is a weak preset but timings are ok i think

Buut you can also try to go for tCL 13 :^
Just need to start running tCKE and RTT_WR , in order to utilize voltage beyond 1.6v
Your cooling is far better than mine


----------



## MyUsername

CarnageBT said:


> I just finished dialing in my memory OC. Now going back over the CO to adjust for any changes.
> 
> My mem OC is here
> View attachment 2514277
> 
> 
> Stability and aida results are on the prev page.
> 
> * The BSOD questions were because I was trying some crazy tRAS numbers that go against the standard formula


Bump the SoC to 1.15 and maybe run 2T. 1T is hard and extreme with 4 sticks SR or 2 sticks DR. Your timings are about as good as it gets.


----------



## FleischmannTV

Does a low RTT_WR RZQ divider increase or lower DIMM temperature? From what I've read here, low RTT_Park divider is bad with high voltage, but RTT_WR is recommended with it?


----------



## domdtxdissar

@ *craxton*
Why do you want to run with EDC bug on Zen3 ?
I already wrote that you can get "high boosting" in stuff like TM5, but it is with hidden clockstreeching (effective clock is not real)
(and i have already explained why _i think_ TestMEM is not the best program to test CPU overclocking, but that is a separate issue)







(hwinfo is reading the "edc limit" as straight up removed)

You get worse real performance with "EDC bug" on Zen3, it only worked well on Zen2.


----------



## kim nk

Veii said:


> I think the set is flawless
> Only tRP would need to be 12 , but this requires more voltage - and more voltage means different RTT
> 
> Also it looks like it wants ClkDrvStr a bit ~ but your procODT is far lower than usual
> This likely is the reason for low cLDO_VDDP
> 
> Test the timings and adjust procODT up and down 28-34ohm , 3 options one of 3 will only have zero variation on Aida64. 0.3ns or more is instability and autocorrection
> Formula you used for tRAS is tRCDmax + tCCD_L or tBL
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Currently it was used as 14+6=20 (bios issue soo 21)
> tRC is tRCDWR+tCWL+tWR+tCCD_L or tBL
> 8+14+12+6=40
> 
> Both are issues because tRP + tRAS does not equal tRC
> I think your tCCD_L is 6 here
> Try maybe this first
> (2T needed 1.54~, 1T needed 1.6v)
> 
> 
> 
> 
> 
> 
> 
> 
> Next one is this but with your own RTTs
> 
> 
> 
> 
> 
> 
> 
> 
> Looking at it now, it looks amateur 🙊
> Too high tRDWR high SD,DD and not even tWR 10. Also ignore GDM, this is a weak preset but timings are ok i think
> 
> Buut you can also try to go for tCL 13 :^
> Just need to start running tCKE and RTT_WR , in order to utilize voltage beyond 1.6v
> Your cooling is far better than mine


Yes, I am always trying to refer to the "veii" teacher's old memory overclock formula and trying to understand it one by one with Google translation ~ tRC is tRCDWR + tCWL + tWR + tCCD_L or tBL Thank you very much for telling me 8 + 14 + 12 + 6 = 40 value and tras = tcd max + tccd_l or tbl ~ My cpu stays at cl14 3800. I have replaced it four times, but I have not met cpu without "whea" More than 3800 clocks have a cpu bus error "whea" error. I would like to ask if this error is a memory controller problem and there is no solution. Thank you for teaching rt 7/0/6 this time. It is very difficult to understand because the data of "veii" teacher is still in Korea only in Google translation. I am so grateful for explaining it kindly in this comment. 1xtfaw execution learned to be tras+1=trc last time You need a voltage of about 1.6v! Thank you very much for this information, tras 20, but only 21. Trc33 trtp7 trfc 231 ,trc 34 trp 7 trfc245 trfc 238, trc35 trtp 7 trfc245 trc 36 trtp 7 trfc 252 This method, but the result value is not good, I am using it at the present time. Thank you very much for your help. I'll try the part you taught me!


----------



## Robostyle

Veii said:


> Be first sure that you can even pass y-cruncher (all tests , 1-7-0)
> Then override PBO witth Scalar X1 (companies love to cheat there)
> and maybe it's just your windows which slows it down
> but it's at least 30% slower than stock, soo i think something fishy is going on
> 
> Going offset mode and adding the slightest bit of positive vcore should also fix much
> Most of the times, boardparners make their own voltage ranges ~ and only offset mode does really reset it to AMDs based scaling
> Soo a tiny offset will wipe whatever cheating was going there (too)
> 
> Check this and report back
> y-cruncher for stability needs 4 loops = 4*18min , to be anywhere near "stable"


Reverted back to 3800mem:1900fclk.


Spoiler: cruncher
















y-cruncher is hard to use - instantly crashes all the time after the start, only 1\10 it runs okay and starts testing.
SOC 1.2V, vddp 1.05V, CCD ~0.99V, IOD 1.1V, vDDR 1.45V, PBO scalar x1, vCore +250mV offset.
Going with +0.8V offset changes nothing, judging from HWInfo vCore goes up to 1.54.

Low vDDR by its own causes whea interconnect errors too.


----------



## XPEHOPE3

Veii said:


> Dual Rank and 4 dimms need tWRRD neverless of the timings working method


If this holds 3 months after being posted, can you please rephrase into something concrete? Even assuming "neverless" = "nevertheless", the quote doesn't make sense to me (English also non-native for me).


----------



## craxton

mongoled said:


> To be honest with you I dont like the meaning of "best" cores as defined by AMD
> 
> 🤣
> 
> The reason is simple, most people will automatically think the best core is the one that boosts higher, but this is not really what happens for every single core.
> 
> My understanding is the "best" core is given this designation if it is able to run X frequency with less voltage than the other cores on the same CPU and hold that load for a bigger duration.
> 
> But as we know the V/F curve changes as we scale up/down voltage and we cant assume that this scaling stays the same for any core!
> 
> Example, my "best" cores need positive CO offset, while the others all take negative offset, but when I check to see what they boost to you would assume that the best cores would boost to a higher frequency than the others, but this is not the case all of the time, hence the reason I no longer look at the cores as best or worse, I just do my best to give them what CO they need to run X frequency and not worry about if one needs positive offset and other needs negative


yea ive noticed that my "best" two cores actually need less voltage than the others, but
my highest clocking core which is "the worst" needs way more voltage than the rest.

at this time, ive not had my "half ass" dialed in CO settings, and have been running -20 for over a week now
with 50mv offset even tho its supposed to be 50mv for 25 or higher CO.

@ManniX-ITA

i could use better grammar all together in reality, working on it. but ive been used to
scatter shot sentences half my life. so hense the start of one thing, and ending it with another.

as for EDC limit, assuming this value is indeed inside HWINFO?








does that look about right?
and yes thats my "all time" highest score to date.
manually setting 420 inside bios yields the previous scores, give or take 10-20 points.

i will note that i have NOT tried going higher than 1 with EDC limit. (isnt the EDC fused limit 90 or 60A?) for 5600x


----------



## craxton

domdtxdissar said:


> @ *craxton*
> Why do you want to run with EDC bug on Zen3 ?
> I already wrote that you can get "high boosting" in stuff like TM5, but it is with hidden clockstreeching (effective clock is not real)
> (and i have already explained why _i think_ TestMEM is not the best program to test CPU overclocking, but that is a separate issue)
> View attachment 2514308
> 
> (hwinfo is reading the "edc limit" as straight up removed)
> 
> You get worse real performance with "EDC bug" on Zen3, it only worked well on Zen2.


im unsure your following what ive posted, im not using TM5 to check clock speeds, nor am i using to test clock stretching.
im running OCCT and have way lower temps (while its WAY HOTTER inside today) while having way better benchmark scores. 
all while not limiting PPT, nor TDC at all. as usually i MUST while running OCCT other wise the start of the test session
instantly hits 80c and climbs. (pc stays on 90% of the time) idle is around 30-35c (240mm ek-d-rgb aio 4 vardar push pull top mount
which (btw) top mount seems to cool WAY better than what it was front mounted....(leaving one fan as direct intake towards the VRMs)

im simply doing my own searching. figuring out what works for my chip and doesnt. as if you seen any other stuff i posted
what works for 90% of others on the CPU core side, does NOT AT ALL work for me so well....
now my IMC however, above average from what ive seen. with ****TY timings can hit 1:1 mode all the way to 4200mhz (just didnt try to stabilize)
was simply looking to see where i could get. after that hard lock to bios reset needed. (was still running 4x8 on all this 1:1 checking stuff) didnt 
try using 1 dimm tho.


----------



## Drevi

5600X @ X570 Aorus Elite rev 1.0 with Crucial Ballistix 16GBx2 (Micron Rev-E)

I been running 3800 with kind of thrash timings for the last 3-4 months (and recently learned of the 25 cycle TM5, so I did that 3 times and no errors). My CO settings where dialed in last month using core cycler, and got a pass running two whole nights.
I've tried every bios version to see if anything will allow 2000, but no luck so far (need to reset cmos or wont even boot). So I would like to tune my memory at3800 and just forget about 2000fclk.
Most of the talk is bout B-Die, the only one with Rev-E seems to be @Veii but it's a way better bin, so not sure if I should try to copy his settings. This is as far as I could get reading the thread.



Spoiler: BIOS Settings



Vcore soc 1.112v
Dram 1.4v
CPU LLC auto
Soc LLC high
CO -15 -20 -15 -5 +3 -20
PBO limits motherboard
Scalar auto
+200mhz





Spoiler: Taiphoon Report



​

Module Manufacturer:Micron Semiconductor
Malaysia Sdn. Bhd.Module Part Number:BL16G32C16U4B.M16FEModule Series:BallistixDRAM Manufacturer:Micron TechnologyDRAM Components:D9VPP (MT40A1G8SA-075:E)Component Design ID:Z11BDRAM Die Revision / Process Node:E / 19 nmModule Manufacturing Date:Week 45, 2020Manufacturing Date Decoded:November 2-6, 2020Module Manufacturing Location:Muar, MalaysiaModule Serial Number:E504ECF2hManufacturing Identification Number:421450712Module PCB Revision:00h

PHYSICAL & LOGICAL ATTRIBUTES
​

Fundamental Memory Class:DDR4 SDRAMModule Speed Grade:DDR4-2666VBase Module Type:UDIMM (133,35 mm)Module Capacity:16 GBReference Raw Card:B1 (8 layers)JEDEC Raw Card Designer:Micron TechnologyModule Nominal Height:31 < H <= 32 mmModule Thickness Maximum, Front:1 < T <= 2 mmModule Thickness Maximum, Back:1 < T <= 2 mmNumber of DIMM Ranks:2Address Mapping from Edge Connector to DRAM:MirroredDRAM Device Package:Standard MonolithicDRAM Device Package Type:78-ball FBGADRAM Device Die Count:Single dieSignal Loading:Not specifiedNumber of Column Addresses:10 bitsNumber of Row Addresses:16 bitsNumber of Bank Addresses:2 bits (4 banks)Bank Group Addressing:2 bits (4 groups)DRAM Device Width:8 bitsProgrammed DRAM Density:8 GbCalculated DRAM Density:8 GbNumber of DRAM components:16DRAM Page Size:1 KBPrimary Memory Bus Width:64 bitsMemory Bus Width Extension:0 bitsDRAM Post Package Repair:SupportedSoft Post Package Repair:Supported

DRAM TIMING PARAMETERS
​

Fine Timebase:0,001 nsMedium Timebase:0,125 nsCAS Latencies Supported:10T, 12T, 13T, 14T,
15T, 16T, 17T, 18T,
19T, 20TMinimum Clock Cycle Time (tCK min):0,750 ns (1333,33 MHz)Maximum Clock Cycle Time (tCK max):1,600 ns (625,00 MHz)CAS# Latency Time (tAA min):14,250 nsRAS# to CAS# Delay Time (tRCD min):14,250 nsRow Precharge Delay Time (tRP min):14,250 nsActive to Precharge Delay Time (tRAS min):32,000 nsAct to Act/Refresh Delay Time (tRC min):46,250 nsNormal Refresh Recovery Delay Time (tRFC1 min):350,000 ns2x mode Refresh Recovery Delay Time (tRFC2 min):260,000 ns4x mode Refresh Recovery Delay Time (tRFC4 min):160,000 nsShort Row Active to Row Active Delay (tRRD_S min):3,000 nsLong Row Active to Row Active Delay (tRRD_L min):4,900 nsWrite Recovery Time (tWR min):15,000 nsShort Write to Read Command Delay (tWTR_S min):2,500 nsLong Write to Read Command Delay (tWTR_L min):7,500 nsLong CAS to CAS Delay Time (tCCD_L min):5,000 nsFour Active Windows Delay (tFAW min):21,000 nsMaximum Active Window (tMAW):8192*tREFIMaximum Activate Count (MAC):Unlimited MACDRAM VDD 1,20 V operable/endurant:Yes/Yes

THERMAL PARAMETERS
​

Module Thermal Sensor:Not Incorporated

SPD PROTOCOL
​

SPD Revision:1.1SPD Bytes Total:512SPD Bytes Used:384SPD Checksum (Bytes 00h-7Dh):52F2h (OK)SPD Checksum (Bytes 80h-FDh):DF74h (OK)

PART NUMBER DETAILS
​

JEDEC DIMM Label:16GB 2Rx8 PC4-2666V-UB1-11

​

FrequencyCASRCDRPRASRCRRDSRRDLWRWTRSWTRLFAW1333 MHz20191943624720410281333 MHz19191943624720410281200 MHz1818183956461839261067 MHz1716163550461638231067 MHz161616355046163823933 MHz151414304435143720933 MHz141414304435143720800 MHz131212263734122617800 MHz121212263734122617667 MHz101010223124102514

INTEL EXTREME MEMORY PROFILES
​

XMP PARAMETERPROFILE 1PROFILE 2Profiles Revision: 2.0Profile 1 (Certified) Enables: YesProfile 2 (Extreme) Enables: NoProfile 1 Channel Config: 1 DIMM/channelSpeed Grade:DDR4-3200N/ADRAM Clock Frequency:1600 MHzN/AModule VDD Voltage Level:1,35 VN/AMinimum DRAM Cycle Time (tCK):0,625 nsN/ACAS Latencies Supported:20T,19T,18T,17T,
16T,15T,14T,13T,
12T,11T,10T,9T,
8T,7TN/ACAS Latency Time (tAA):10,000 nsN/ARAS# to CAS# Delay Time (tRCD):11,250 nsN/ARow Precharge Delay Time (tRP):11,250 nsN/AActive to Precharge Delay Time (tRAS):22,500 nsN/AActive to Active/Refresh Delay Time (tRC):45,000 nsN/AFour Activate Window Delay Time (tFAW):21,000 nsN/AShort Activate to Activate Delay Time (tRRD_S):3,000 nsN/ALong Activate to Activate Delay Time (tRRD_L):4,900 nsN/ANormal Refresh Recovery Delay Time (tRFC1):350,000 nsN/A2x mode Refresh Recovery Delay Time (tRFC2):260,000 nsN/A4x mode Refresh Recovery Delay Time (tRFC4):160,000 nsN/A













Edit: wrong sshot, fixed


----------



## dansi

i got unexpected whea reboot by doing a full windows defender scan, around the 8 min mark of scanning with hwinfo opened.

i think you can try it as a stability test. windef uses up to 30% of the 5900x cpu while scanning


----------



## 1s1mple

Delete, Adblocked. _Fixed_


----------



## Drevi

1s1mple said:


> Whats your CO settings look like?


It's inside "BIOS Setttings". Did I do wrong the spoiler tag? I see them fine. 

Anyways: 
Vcore soc 1.112v
Dram 1.4v
CPU LLC auto
Soc LLC high
CO -15 -20 -15 -5 +3 -20
PBO limits motherboard
Scalar auto
+200mhz


----------



## ManniX-ITA

craxton said:


> does that look about right?
> and yes thats my "all time" highest score to date.


Looks right 
Check that you don't have clock stretching
Run CB23 MT and TM5, verify all cores are running at the same clock and effective


----------



## CarnageBT

ManniX-ITA said:


> Looks right
> Check that you don't have clock stretching
> Run CB23 MT and TM5, verify all cores are running at the same clock and effective


I've always wondered about this. When checking for clock stretching I currently just compare the effective clocks across all my cores (usually if EDC is too low, I'll see CCD1 running slightly faster than CCD2). Is that the correct way to check for clock stretching? OR is it that PLUS if there is any difference from the reported core clocks vs the effective clocks?

Was that clear or confusing? Stated another way:

clock stretching = variance in effective clocks

OR

clock stretching = variance b/w reported "core clocks" and effective clocks

Which is correct?


----------



## mongoled

Drevi said:


> It's inside "BIOS Setttings". Did I do wrong the spoiler tag? I see them fine.
> 
> Anyways:
> Vcore soc 1.112v
> Dram 1.4v
> CPU LLC auto
> Soc LLC high
> CO -15 -20 -15 -5 +3 -20
> PBO limits motherboard
> Scalar auto
> +200mhz


Did you test your CO with Y-Cruncher, CoreCycler etc as that would be an extermely good specimin if those CO values are actually stable ?

I dont mean "game" stable but "stable" as in the CPU can run CPU intensive tasks using AVX2, SSE, AVX etc without crashing ..


----------



## mongoled

CarnageBT said:


> I've always wondered about this. When checking for clock stretching I currently just compare the effective clocks across all my cores (usually if EDC is too low, I'll see CCD1 running slightly faster than CCD2). Is that the correct way to check for clock stretching? OR is it that PLUS if there is any difference from the reported core clocks vs the effective clocks?
> 
> Was that clear or confusing? Stated another way:
> 
> clock stretching = variance in effective clocks
> 
> OR
> 
> clock stretching = variance b/w reported "core clocks" and effective clocks
> 
> Which is correct?


Second,

Easiest test is to run with PBO, note the effective clock speed when running CB23.

Close CB23 and re-run after having set its priority to real-time (yes it will look like the system has hung but it hasnt), note the score

Then reboot go into BIOS and set the CPU to a fixed frequency that is the same as the one you noted earlier.

Run CB23 again with priority set to real-time, if you have properly tuned CO then the scores between the PBO run and the fixed clocks run should be close, i.e. no more than 80 points discrepancy

Note: I have not specifically tested the above with an intent to test for clock stretching, but have noted that my PBO scores which run CB23 at 4.6Ghz is on par with those running CB23 with fixed 4.6 Ghz clock ..


----------



## ManniX-ITA

CarnageBT said:


> clock stretching = variance b/w reported "core clocks" and effective clocks


This one.

Effective clock is relative to usage.
You can compare a core effective clock only if that core is under 100% usage.
So don't use anything that is not fully 100% using all cores or you could think there's stretching while there's not.

Then you have to compare the scores.
Even if everything looks right doesn't mean it is working fine.
There are a lot of throttling mechanisms in Zen2/3.
Some can have the hard stop effect of a thermal limit, others a progressive degradation going up with clock like stretching.
But in some cases you don't see it looking at the clocks, only when you check the scores.


----------



## mongoled

Taraquin said:


> Yep, it's works good, allcore runs at 4.6GHz, single at 4.7 with -30 CO, same score in CB20 as 4.6GHz static OC. I see no stretching so far, but if I try +100MHz pbo or more I get random reboots or freezes once or twice a day.


Well yeah, thats where you would re-tweak your CO values, thats if you actually want to increase your single core top frequency.

Im at +200, with +5 | -3 | -7 | -6 | +6 | -9

All core boost 4850, CB23 @4600, Prime95 Small FFTs @ 45xx

If you are really lucky you will get the below

😂 😂


----------



## Drevi

mongoled said:


> Did you test your CO with Y-Cruncher, CoreCycler etc as that would be an extermely good specimin if those CO values are actually stable ?
> 
> I dont mean "game" stable but "stable" as in the CPU can run CPU intensive tasks using AVX2, SSE, AVX etc without crashing ..


Yes, I got to those values using CoreCycler. After I got it dialed in I let it run 2 nights, so around 20hs. This was early april. Ran just fine until last week of may, where I had 3 whea 18 reboots (just browsing/youtube). Two where APIC ID 5 and one APIC ID 4. Assuming threads start at 0, core 3 might need a bit extra v. Ran CoreCycler again after that, but no crash. Neither got any whea 18/reboot and PC is on 24/7. 


I had a whole post explaining this and asking for guidance for further tuning but it's now marked as "waiting for mod aproval" (I guess it didn't like that I edited it 2 times to correct). I might just delete that and post it again.


----------



## mongoled

@CarnageBT

I decided to return to my one bad stick and see if I can get flat 14s running on it, then comparing the performance to 14-15-14-14

So far im loosening, loosening and loosening to find what is the primary cause of issues with this particular stick with tRCDRD @14 and its looking like its tFAW related.

Have finally got a non instant error throwing TM5 running and it needed tRRDS set to 10, pushing tFAW to 40 (tRRDSx4 = tFAW).

I am now going to start tightening other timings to see what the next bottleneck is going to be ....



*** EDIT ***
So I can hold almost exactly the same settings as my 24/7 settings when using tRCDRD @14, but to get the errors down to minimal I have to set tFAW to the biggest value available to me which is 54

Its very strange, the errors I get are now more consistent and they revolve around 10, 13 and 4.

No amount of relaxing other timings makes a difference.

No amount of playing with RTT/vDIMM makes a difference.

No amount of playing with CadBus makes a difference.

I have active fan over the dimm so error 13 being due to overheating does not explain the error 13, ive noticed that even when not using a fan the dimm does not get very hot at all so I am wondering if its something to do with the heatsink and tacky thermal tape that is used.

Once tRCDRD is returned to 15 all is well again.....


----------



## mongoled

Drevi said:


> Yes, I got to those values using CoreCycler. After I got it dialed in I let it run 2 nights, so around 20hs. This was early april. Ran just fine until last week of may, where I had 3 whea 18 reboots (just browsing/youtube). Two where APIC ID 5 and one APIC ID 4. Assuming threads start at 0, core 3 might need a bit extra v. Ran CoreCycler again after that, but no crash. Neither got any whea 18/reboot and PC is on 24/7.
> 
> 
> I had a whole post explaining this and asking for guidance for further tuning but it's now marked as "waiting for mod aproval" (I guess it didn't like that I edited it 2 times to correct). I might just delete that and post it again.


Only CoreCycler ?

CoreCycler for me is just a primer for finding something that looks to be OK, after I found something its then onto Y-Cruncher to see if its stable, if Y-Cruncher crashes on specific tests (N32/N64 are particularly sensitive to CO) I tweak CO on core that crashed then hone in Y-Cruncher just to run on the crashing test.

Once its stopped crashing on the particular core I return to Y-Cruncher full test suite.

After Y-Cruncher is stable I do another CoreCycler, then use the system normally for an extended period of time to possibly catch idle crashes before moving to other types of stress tests


----------



## Drevi

mongoled said:


> Only CoreCycler ?
> 
> CoreCycler for me is just a primer for finding something that looks to be OK, after I found something its then onto Y-Cruncher to see if its stable, if Y-Cruncher crashes on specific tests (N32/N64 are particularly sensitive to CO) I tweak CO on core that crashed then hone in Y-Cruncher just to run on the crashing test.
> 
> Once its stopped crashing on the particular core I return to Y-Cruncher full test suite.
> 
> After Y-Cruncher is stable I do another CoreCycler, then use the system normally for an extended period of time to possibly catch idle crashes before moving to other types of stress tests


I'm not doing anything heavier than gaming currently. CC was good enough for that (or that is my understanding). I might check with Y-Cruncher just to know how stable it is. Any recommendation on config/amount of tests?


----------



## mongoled

Drevi said:


> I'm not doing anything heavier than gaming currently. CC was good enough for that (or that is my understanding). I might check with Y-Cruncher just to know how stable it is. Any recommendation on config/amount of tests?


Default config first (press 1, then 7, then 0). Let it run couple of hours


----------



## ManniX-ITA

mongoled said:


> After Y-Cruncher is stable I do another CoreCycler, then use the system normally for an extended period of time to possibly catch idle crashes before moving to other types of stress tests


Running y-cruncher standalone is not enough if you are using PBO.
It will run on all cores, lower frequency.
To properly test CO you need to check with CoreCycler, one single core at a time.
And also avoid using at all the PC if possible.
Otherwise the core under test will slow down in frequency.

You can also use y-cruncher with CoreCyler.
But it's better to use as well Prime95 with CoreCycler and run all the FFT sizes from 4K to MAX:



Code:


# Smallest:     4K to   21K - Prime95 preset: "tests L1/L2 caches, high power/heat/CPU stress"
# Small:       36K to  248K - Prime95 preset: "tests L1/L2/L3 caches, maximum power/heat/CPU stress"
# Large:      426K to 8192K - Prime95 preset: "stresses memory controller and RAM" (although dedicated memory stress testing is disabled here by default!)
# Huge:      8960K to   MAX - anything beginning at 8960K up to the highest FFT size (32768K for SSE/AVX, 51200K for AVX2)
# All:          4K to   MAX - 4K to up to the highest FFT size (32768K for SSE/AVX, 51200K for AVX2)
# Moderate:  1344K to 4096K - special preset, recommended in the "Curve Optimizer Guide Ryzen 5000"
# Heavy:        4K to 1344K - special preset, recommended in the "Curve Optimizer Guide Ryzen 5000"
# HeavyShort:   4K to  160K - special preset, recommended in the "Curve Optimizer Guide Ryzen 5000"

Of course it takes a huge amount of time.
But running "All" with SSE/AVX/AVX2 is the only way to be 100% all is working fine.

You should run at least 20m cycle per core (thermal equilibirum):



Code:


# - Prime95 "Smallest":     4K to   21K - [SSE] ~3-4 Minutes   <|> [AVX] ~8-9 Minutes    <|> [AVX2] ~8-10 Minutes
# - Prime95 "Small":       36K to  248K - [SSE] ~4-6 Minutes   <|> [AVX] ~14-19 Minutes  <|> [AVX2] ~14-19 Minutes
# - Prime95 "Large":      426K to 8192K - [SSE] ~18-22 Minutes <|> [AVX] ~37-44 Minutes  <|> [AVX2] ~38-51 Minutes
# - Prime95 "Huge":      8960K to   MAX - [SSE] ~13-19 Minutes <|> [AVX] ~27-40 Minutes  <|> [AVX2] ~33-51 Minutes
# - Prime95 "All":          4K to   MAX - [SSE] ~40-65 Minutes <|> [AVX] ~92-131 Minutes <|> [AVX2] ~102-159 Minutes
# - Prime95 "Moderate":  1344K to 4096K - [SSE] ~7-15 Minutes  <|> [AVX] ~17-30 Minutes  <|> [AVX2] ~17-33 Minutes
# - Prime95 "Heavy":        4K to 1344K - [SSE] ~15-28 Minutes <|> [AVX] ~43-68 Minutes  <|> [AVX2] ~47-73 Minutes
# - Prime95 "HeavyShort":   4K to  160K - [SSE] ~6-8 Minutes   <|> [AVX] ~22-24 Minutes  <|> [AVX2] ~23-25 Minutes
# - y-Cruncher: ~10 Minutes
# Default: 6m
runtimePerCore = auto

So use Auto to test all FFT or set it to at least 20 minutes if the cycle will last less, like with Small set.

I gave up after running all FFT in SSE, too much time on a 5950x 
One day I'll test as well AVX and AVX2.

You should also consider CPPC Preferred cores.
In a normal usage only the first best 2-3 cores will ever run at full speed tested with CoreCycler.
Once the scheduler will distribute load and threads to the other cores the total load will be higher and they'll run at a lower frequency.
So if you want to save some time you could take a shortcut and test thoroughly only the best ones.


----------



## XPEHOPE3

Drevi said:


> I had a whole post explaining this and asking for guidance for further tuning but it's now marked as "waiting for mod aproval" (I guess it didn't like that I edited it 2 times to correct). I might just delete that and post it again.


I had the same problem with editing and waiting for approval. Had to search for moderator which was recently online, and ask. He didn't know why the bot marked my post as spam. Then the post got approved, but now I don't see it in my replies in profile


----------



## craxton

ManniX-ITA said:


> Looks right
> Check that you don't have clock stretching
> Run CB23 MT and TM5, verify all cores are running at the same clock and effective


as a matter of fact, works great for "pure" core loads, but threads on the other hand, well they set at 4675mhz
under core cycler loads. anything over 1A edc and nothing moves past 1ghz lol....
had 5x scaler tried 9A which made no core boost, tried 1A 10x scaler, same thing cores boost but threads stuck maxed at 4675.

so perhaps thats what DOM was getting at. (yes i used TM5 to see) as core cycler was pegging the corresponding threads to 4675mhz.
so, unsure how those CB runs (the ones i didnt show) and the one i did were my best.... perhaps due to all cores and threads pegging 4675
instead of fluctuating up and down?

so maybe ona 5600x the "bug" is good for a few things...while in other places maybe not so much.


----------



## ManniX-ITA

craxton said:


> as a matter of fact, works great for "pure" core loads, but threads on the other hand, well they set at 4675mhz
> under core cycler loads. anything over 1A edc and nothing moves past 1ghz lol....


Yes that's one of the weird side effects could arise and Dom was referring to
How did you test with CoreCycler?
The max speed the core can reach depends on the FFT size, Small lowest speed, Huge highest
You can also use y-cruncher with CC and that should boost the core to the max running some tests (not sure which one)


----------



## kim nk

Veii said:


> I think the set is flawless
> Only tRP would need to be 12 , but this requires more voltage - and more voltage means different RTT
> 
> Also it looks like it wants ClkDrvStr a bit ~ but your procODT is far lower than usual
> This likely is the reason for low cLDO_VDDP
> 
> Test the timings and adjust procODT up and down 28-34ohm , 3 options one of 3 will only have zero variation on Aida64. 0.3ns or more is instability and autocorrection
> Formula you used for tRAS is tRCDmax + tCCD_L or tBL
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Currently it was used as 14+6=20 (bios issue soo 21)
> tRC is tRCDWR+tCWL+tWR+tCCD_L or tBL
> 8+14+12+6=40
> 
> Both are issues because tRP + tRAS does not equal tRC
> I think your tCCD_L is 6 here
> Try maybe this first
> (2T needed 1.54~, 1T needed 1.6v)
> 
> 
> 
> 
> 
> 
> 
> 
> Next one is this but with your own RTTs
> 
> 
> 
> 
> 
> 
> 
> 
> Looking at it now, it looks amateur 🙊
> Too high tRDWR high SD,DD and not even tWR 10. Also ignore GDM, this is a weak preset but timings are ok i think
> 
> Buut you can also try to go for tCL 13 :^
> Just need to start running tCKE and RTT_WR , in order to utilize voltage beyond 1.6v
> Your cooling is far better than mine


I think the set is flawless 
Only tRP would need to be 12 , but this requires more voltage - and more voltage means different RTT

Also it looks like it wants ClkDrvStr a bit ~ but your procODT is far lower than usual
This likely is the reason for low cLDO_VDDP

Test the timings and adjust procODT up and down 28-34ohm , 3 options one of 3 will only have zero variation on Aida64. 0.3ns or more is instability and autocorrection
Formula you used for tRAS is tRCDmax + tCCD_L or tBL


Spoiler














Currently it was used as 14+6=20 (bios issue soo 21)
tRC is tRCDWR+tCWL+tWR+tCCD_L or tBL
8+14+12+6=40

Both are issues because tRP + tRAS does not equal tRC
I think your tCCD_L is 6 here
Try maybe this first
(2T needed 1.54~, 1T needed 1.6v)








Next one is this but with your own RTTs








Looking at it now, it looks amateur 🙊
Too high tRDWR high SD,DD and not even tWR 10. Also ignore GDM, this is a weak preset but timings are ok i think

Buut you can also try to go for tCL 13 :^
Just need to start running tCKE and RTT_WR , in order to utilize voltage beyond 1.6v
Your cooling is far better than mine [/QUOTE]

Hello, I tested the value you asked me to try recently. To run the BIOS memory voltage 1.6V 1XTFAW, you asked me to do TRAS + 1 = TRC, and I was wondering here. I wonder what formula TRRDS, TRRDL, TFAW, TWTRS, TWTRL used. And what should we do with the 3800 14-10-14-12-26-38 that you asked me to test at the end, "RTT" 0/0/5, 7/0/6? Do you need to perform a voltage of 1.6V for 1T memory voltage? And I wonder what the most efficient practical use of the CL14 3800 is among the most effective. Thank you so much for always teaching me! 

14-14-14-14-28-29. 1T 1.6V


----------



## CarnageBT

ManniX-ITA said:


> This one.
> 
> Effective clock is relative to usage.
> You can compare a core effective clock only if that core is under 100% usage.
> So don't use anything that is not fully 100% using all cores or you could think there's stretching while there's not.
> 
> Then you have to compare the scores.
> Even if everything looks right doesn't mean it is working fine.
> There are a lot of throttling mechanisms in Zen2/3.
> Some can have the hard stop effect of a thermal limit, others a progressive degradation going up with clock like stretching.
> But in some cases you don't see it looking at the clocks, only when you check the scores.


Did a bit of testing. I never paid much attention to report core clocks before. I notice that while effective are precise, reported core clocks are rounded to the nearest 25mhz.

In my testing:
p95 small FFT reported core = 4400 - 4425 || Effective core = 4410 - 4420 - I assume this is not stretching? The reported core just rounds up or down relative to effective, so often reported says 4400 while my effective is 4410, but once effective passed 4415 or so, then reported will jump up 25mhz to 4425
same patten with r23, reported core = 4600 and effective = 4595 - 4605.

Looks ok?


----------



## ManniX-ITA

CarnageBT said:


> Looks ok?


Yes, looks ok.
Also consider there's a pooling period rate in HWInfo in the sensors configuration.
If you want to really catch almost all the clock variations it should be set to 500ms.
But it will impact the CPu quite heavy so should only be reduced on a spot basis and then set back to default.
And you should select in the main settings Snapshot CPU Pooling to get more accurate results for effective clocks.


----------



## CarnageBT

Yea, I was looking at it with the rate set to 500ms. Haven't tried Snapshot pooling before though.

@mongoled @ManniX-ITA
Horrible news.... I tested again last night before sleep and to my dismay,

Identical settings as prior night 25 cycle pass = cycle 7, error 1.

Next I tried increasing vdimm from 1.49 to 1.5 as suggested and went to bed. Woke up to a competed 25 cycle test, but errors, 7, 14, 0, 11, 1, 7, 14, 1, 8 .

*I did not increase beyond because the other day when you first mentioned it, I tried 1.51 vdimm and got error 14 after 40 minutes.

I think I may have to try a complete re-work. I've been looking at your and dom's settings and think I may need to fiddle with CADBUS setttings. OR completely re work my RTT's, maybe lower park like you both have.

*When I run the TM5 test I have HWinfo open and msi afterburner. shouldn't be a problem though right? afterburners hw monitor is paused. so it doesn't do much of anything

Going to test CAD_BUS variations now. any and all suggestions welcome

Settings tested last night (vdimm was 1.49 for first test, maybe I should allow it to complete a full run with 1.49 to see what other errors arise)









Edit:
Tested:

Pictured, 40-20-24-24Cycle 7, error 11.5 vdimm25 cycles, UNKNOWN when 1st error occured, 7, 14, 0, 11, 1, 7, 14, 1, 81.48 vdimm60-20-24-24cycle 1, error 10*40-20-30-24**cycle 17, 1h45m, error 1 - COULD BE 1.5 VDIMM /w this setting OR 56-0-0**40-20-20-24**Cycle 23, 2h30m, error 1, 1, 1 (back to back), then completed to 25 cycles, no other errors*40-20-20-20cycle 4, 20m, error 10*40-20-30-20**Cycle 20, 2h, error 2, 2, 2, 0*


----------



## 1s1mple

mongoled said:


> Default config first (press 1, then 7, then 0). Let it run couple of hours


If it passes in that, the CO is stable?
I’m testing all cores -10 right now, 0 boost override with a tuned PBO


----------



## PJVol

CarnageBT said:


> I notice that while effective are precise, reported core clocks are rounded to the nearest 25mhz.


Just set "Cpu snapshot polling mode" checkbox in startup hwinfo window's settings. No need to reduce polling interval.
25 mhz is a frequency resolution for the p-states. Its actually the exact frequency, the core run at. What you see in "snapshot mode" (as i see it) is the COF table formed by SMU firmware, where each COF may be for example, dfs prerounded value. Need double check it though.


----------



## ManniX-ITA

PJVol said:


> Just set "Cpu snapshot polling mode" checkbox in startup hwinfo window's settings. No need to reduce polling interval.


You still need to reduce the pooling interval otherwise it could miss peaks and/or smoothen the current.






Effective clock vs instant (discrete) clock


It has become a common practice for several years to report instant (discrete) clock values for CPUs. This method is based on knowledge of the actual bus clock (BCLK) and sampling of core ratios at specific time points. The resulting clock is then a simple result of ratio * BCLK. Such approach...




www.hwinfo.com





The snapshot is a different method to get the data but still relies on the pooling interval.
Instead of being actively queried one by one the counters are written all at once, like dumping the powertable via the SMU.


----------



## CarnageBT

OMG. error on cycle 23, 2h30m into the test, 3x error 1 back to back. Anyone have insights into what the CAD_BUS testing I'm doing may mean? I've included time of 1st error for all except 1 (overnight test). I figure the ones that go so long must have some similarities / differences to others that would imply or mean something to someone with better understanding

* see post above for the most updated results. I am editing that post with results as I get them


----------



## PJVol

ManniX-ITA said:


> You still need to reduce the pooling interval otherwise it could miss peaks and/or smoothen the current.


Why bother with peaks if you evaluating clock stretching this way, over a period of time, in any case?



ManniX-ITA said:


> like dumping the powertable via the SMU


Why "like" ? ))

And Idk, whether high SMU poll rate might adversely affect its functionality, so unless proven otherwise, I wouldn't use other than default 2s.


----------



## KedarWolf

CarnageBT said:


> OMG. error on cycle 23, 2h30m into the test, 3x error 1 back to back. Anyone have insights into what the CAD_BUS testing I'm doing may mean? I've included time of 1st error for all except 1 (overnight test). I figure the ones that go so long must have some similarities / differences to others that would imply or mean something to someone with better understanding
> 
> * see post above for the most updated results. I am editing that post with results as I get them


Did you see my posts about RAM temps and the fans I use etc? Errors late in testing likely due to RAM getting too hot.

My RAM performs really well if I keep it under 40C while stress testing and if you're hitting 50C+, might be a problem. 









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


To infinity and beyond. (was showing 118-120 not sure what happened) Lol lol thats nothing, turn on CTR with some OB ranges of some sort, youll see that the test goes -13e0480945860+e




www.overclock.net


----------



## Drevi

mongoled said:


> Default config first (press 1, then 7, then 0). Let it run couple of hours


Seems good so far, gonna let it run all night when I go to bed.


----------



## CarnageBT

KedarWolf said:


> Did you see my posts about RAM temps and the fans I use etc? Errors late in testing likely due to RAM getting too hot.
> 
> My RAM performs really well if I keep it under 40C while stress testing and if you're hitting 50C+, might be a problem.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> To infinity and beyond. (was showing 118-120 not sure what happened) Lol lol thats nothing, turn on CTR with some OB ranges of some sort, youll see that the test goes -13e0480945860+e
> 
> 
> 
> 
> www.overclock.net


Yea, I saw it, also looked at the fans. Pretty cool. How / Where do you mount those fans?
At the moment my case has quite high airflow, it's a lian li lancool ii mesh, with all fan spaces maxed out, 8 incl. the aio. 

My ram never exceeds 48.5c, during testing, so it stays below 50 where errors typically develop for b die. It's actually only dimm1 that gets to 48.5c during MT5; max temps are - dimm1 44.5c, dimm2 48.5c, dimm3 45c, dimm4 46c.


----------



## 1s1mple

mongoled said:


> Default config first (press 1, then 7, then 0). Let it run couple of hours


Here's almost 6 hours of testing my curve (all cores -10 with PPT 200 TDC 70 EDC 130) with Y Cruncher


----------



## CarnageBT

40-20-24-24Cycle 7, error 11.5 vdimm25 cycles, UNKNOWN when 1st error occured, 7, 14, 0, 11, 1, 7, 14, 1, 81.48 vdimm60-20-24-24cycle 1, error 1040-20-20-20cycle 4, 20m, error 10*40-20-30-24**cycle 17, 1h45m, error 1 - COULD BE 1.5 VDIMM /w this setting OR 56-0-0**40-20-20-24**Cycle 23, 2h30m, error 1, 1, 1 (back to back), then completed to 25 cycles, no other errors**40-20-30-20**Cycle 20, 2h, error 2, 2, 2, 0*

Do these results mean anything to anyone? Not sure what to make of them as I don't have a consistent trend, which makes sense as this is about balance.

I'll test the pictured settings at 1.48vdimm in the mean time, if it's clearly worse, then I'll try testing with 1.5vdimm in combination with some of those CAD_BUS variations.


----------



## XPEHOPE3

CarnageBT said:


> Do these results mean anything to anyone?


Did you look through Veii's error descriptions?
"2,0", "1" all relate to VDIMM.

EDIT: Also keep in mind that to use CAD_BUS setup timings you must use CAD_BUS X-20-20-20, not like in your last 3 tests.


----------



## KedarWolf

CarnageBT said:


> Yea, I saw it, also looked at the fans. Pretty cool. How / Where do you mount those fans?
> At the moment my case has quite high airflow, it's a lian li lancool ii mesh, with all fan spaces maxed out, 8 incl. the aio.
> 
> My ram never exceeds 48.5c, during testing, so it stays below 50 where errors typically develop for b die. It's actually only dimm1 that gets to 48.5c during MT5; max temps are - dimm1 44.5c, dimm2 48.5c, dimm3 45c, dimm4 46c.


On the mount they just screw on with standard fan screws. 48C is still pretty high, might cause errors. Like I said in that post I get errors going over 40C that under I get no errors under 40C using really tight timings for Dual Rank RAM.


----------



## Veii

CarnageBT said:


> View attachment 2514374
> 
> 
> 
> 40-20-24-24Cycle 7, error 11.5 vdimm25 cycles, UNKNOWN when 1st error occured, 7, 14, 0, 11, 1, 7, 14, 1, 81.48 vdimm60-20-24-24cycle 1, error 1040-20-20-20cycle 4, 20m, error 10*40-20-30-24**cycle 17, 1h45m, error 1 - COULD BE 1.5 VDIMM /w this setting OR 56-0-0**40-20-20-24**Cycle 23, 2h30m, error 1, 1, 1 (back to back), then completed to 25 cycles, no other errors**40-20-30-20**Cycle 20, 2h, error 2, 2, 2, 0*
> 
> Do these results mean anything to anyone? Not sure what to make of them as I don't have a consistent trend, which makes sense as this is about balance.
> 
> I'll test the pictured settings at 1.48vdimm in the mean time, if it's clearly worse, then I'll try testing with 1.5vdimm in combination with some of those CAD_BUS variations.
> 
> 
> 
> XPEHOPE3 said:
> 
> 
> 
> Did you look through Veii's error descriptions?
> "2,0", "1" all relate to VDIMM.
> 
> EDIT: Also keep in mind that to use CAD_BUS setup timings you must use CAD_BUS X-20-20-20, not like in your last 3 tests.
Click to expand...

Looks like instability issues between voltage and Memory Training issues (might want to try 40-20-24-20)
Small MB test sizes are refreshes. Be it tRFC refreshes, or mid-transfer timings like tRRD/tWTR , or SCLs

Every timing can be bruteforced, but he has too many error 1 & 0's
1.5v sample was hitting








Likely signal ripple got too worse and RTTs where bad, or rather SETUP timings couldn't cut well, as signal was too noisy
Visible by the remain tests, when voltage dropped ~ signal appeared cleaner

Overall looks like RTTs are not optimal.
I would try to drop RTT_NOM once more and see if you get PCB crashes
When you increase ClkDrvStr , you have to lower/weaken RTT_NOM or lower voltage.
When you lower procODT, you also should lower VDIMM but increase ClkDrvStr or SOC
If SOC is high, generally weaken RTTs and weaken CAD_BUS (all of them) ~ or just weaken VTT_DDR
If SOC is high, weaken the 1.8v rail ~ i feel ASRock's decision with 1.83v on stock, is pretty perfect , replicating the voltage on the ASUS board.
1.82v was fine, but beyond 1.83v i had issues. I didn't have issues if remain voltages where strange or too low (VDDG, SOC)

The Error #0 , refresh stable can also be an issue with powerdown & so also SETUP timings
But can also be overshooting by RTTs
Tho for RTTs, it often is an explosion of errors at the same time , then peace ~ when signal peak is too strong and reflects back, or fully drops out for a sec
RTT_WR is dynamic, it will catch issues and adjust ripple ~ but for it to function either RTT_NOM needs to work or PARK, one of both
Disabled PARK means 0 doesn't mean 240/480ohm. Then RTT_WR takes over

He/She is close, soo keep trying
I still would give tRRD_L a bump at 5
and tWTR_L a bump at 10
Just for good measure
These tRRD's are too low, they will cause issues , not only with 4 dimms not only with "great" PCBs but also on low primaries
They add performance, but primaries mean much more. Pushing them higher can help in stabilizing your lower tRCD_RD


Drevi said:


> Most of the talk is bout B-Die, the only one with Rev-E seems to be @Veii but it's a way better bin, so not sure if I should try to copy his settings. This is as far as I could get reading the thread.


You can copy & adjust frequency till it's not stable anymore 
As long as you follow a tCCD_L rule, everything runs on these micron kits.
I want a bit more playing time with them and finally get this tRCD 18 under 4000 to work ~ before writing tCCD_L rulesets in stone
It simply refuses on everything i try ~ feels like doing medical work on a war-person. Strongly handcapped on tRCD and tRFC ~ the micron Rev.E's
I'm close but yet didn't made it.
Here are some examples and collection of past fun


Spoiler: "Past Fun"












3933 is the furthest i got with tRCDRD 18
And bit more fun
Highest CL12 i got was 3667, voltage did not make any difference - even 1.7 didn't do *💩 *to make it run any higher freq
(maybe had already negative effects, as RTTs likely where not suited for 1.7+)








Yep i'm back on the ITX, thunderbolt 4 only runs well with Matisse . . . annoying
Old slower sets:


















Sure i do have








C9BKV 055M:E vs your D9VPP 075:E

But all rev.E are kind of similar
Just keep in mind, i move from now mostly in the >1.6v range ~ because thermals are no issue when RTTs are set and weaken
Especially taking a look on:








This is 1.64v , 727 was 1.6v (but used 40+ ClkDrvStr)
* i don't really have a directed fan and roomtemp is surely over 26c most of the day (outdoor is 28-30c)


----------



## Drevi

Veii said:


> You can copy & adjust frequency till it's not stable anymore


Does it matter that mine are 16GB dimms?



Veii said:


> As long as you follow a tCCD_L rule, everything runs on these micron kits.


What would that be? 

(sorry to ask, kind of a noob on memory fine tuning)


----------



## Takla

What does it mean if TM5 skips seconds on the timer in the status tab? Is it just a software bug? I didn't get any errors but the timer would look like it skips 1 second every 10 seconds. (For example, 36s to 37s would happen much quicker then a second)

My guess is, it is just desync between gui and the internal timer?


----------



## Insidious Supra

I am farily well mystified by cad bus timings at this point. I could never get anything stable at 0 0 0. And 1 1 1 is waayyyy worse. Anything lower than 46 doesnt seem to post, and anything above 2 doesnt seem to post either 🤷‍♂️. Can anyone shed any light on the cad bus? 













Takla said:


> What does it mean if TM5 skips seconds on the timer in the status tab? Is it just a software bug? I didn't get any errors but the timer would look like it skips 1 second every 10 seconds. (For example, 36s to 37s would happen much quicker then a second)
> 
> My guess is, it is just desync between gui and the internal timer?


System memory use is nearly maxed. Expect some hesitation or delay.


----------



## Takla

Insidious Supra said:


> System memory use is nearly maxed. Expect some hesitation or delay.


Actually, I changed the config file to reserve 1024kb for windows, so the ssd/pagefile is not used. In most tests there is 1.5gb of free memory. Should be enough to still allow background processes.


----------



## Insidious Supra

Might just be a "feature" of the program, then, lol


----------



## CarnageBT

Insidious Supra said:


> I am farily well mystified by cad bus timings at this point. I could never get anything stable at 0 0 0. And 1 1 1 is waayyyy worse. Anything lower than 46 doesnt seem to post, and anything above 2 doesnt seem to post either 🤷‍♂️. Can anyone shed any light on the cad bus?
> 
> View attachment 2514386
> 
> 
> 
> 
> 
> System memory use is nearly maxed. Expect some hesitation or delay.


Here are some notes I saved in my excel file from various authors


AddrCmdSetup value can range from 50 - 63In theory AddrCmdSetup should arrive after CsOdtSetup/CkeSetup, therefore the last two may remain 0 and only AddrCmdSetup between 50 and 63.You can try Setup 56-0-0 with CAD BUS X-20-24-24. My observations show that this is better:For example, most Asus boards lock AddrCmdSetup at 61 when we have Zen1 / +, ie. setup times are 61-0-0. For comparison Gigabyte puts 11 by default, but I can change it.Higher AddrCmdSetup helps for lower ProcODT/ClkDrvStr. But we need to find the right settings with which we have no loss of performance.Ive been hoping that a "magic" setting combo will appear to allow more peeps to run flat 14s, as has happened with 1T/2T with the 56-56-56 discovery


----------



## Insidious Supra

Hmmm ok, I can certainly run "tighter" timings with 56 56 56 but performance was worse than my "loose" setup now. I'm tempted to revisit and run more tests now.....


----------



## ManniX-ITA

PJVol said:


> Why bother with peaks if you evaluating clock stretching this way, over a period of time, in any case?


Just to say as additional info eheh 
That's useful to get the max boost clock with boosttester, for clock stretching is useful the current value
Default 2 seconds is too much and if the core is not steady 100% usage you could get the wrong idea there's stretching



PJVol said:


> Why "like" ? ))
> 
> And Idk, whether high SMU poll rate might adversely affect its functionality, so unless proven otherwise, I wouldn't use other than default 2s.


No idea what exactly HWInfo's snapshot is doing but I strongly suspect is exactly that 
Do you know more?

I can tell about my testing with the 5950x; at 1 second doesn't make any difference, that's my default.
500 ms if the sensors window is not minimized it has a sizeable hit on performances, minimized very thin
Below that is affecting adversely
In general SMU shouldn't be stressed more than once in 40-60ms but the power table dump is an intensive task
It takes 80-120ms to dump it hence it's better to set at least 200ms between requests or the SMU could crash and the CPU reset
Which is indeed the minimum time suggested by AMD for their crappy RM Monitoring SDK


----------



## CarnageBT

Final testing dump info dump as I'm heading to bed. Close but no cigar was the theme of the day; even though the pictured settings passed 25 TM5 cycles the other day 










All tests done with settings as pictured above aside from the mentioned change

1.49 vdimmCycle 7, error 11.5 vdimm25 cycles, UNKNOWN when 1st error occured, 7, 14, 0, 11, 1, 7, 14, 1, 81.5 vdimm (repeat)Cycle 6. 33m. Error 3, then ran for 60m total with error 3, 3, (total errors = 3, 3, 3)1.48 vdimmCycle 6. Error 2, 1, 2, 6, 6, 0, 21.47 vdimmcycle 1. error 2, 10, 10 - too low vdimm60-20-24-24cycle 1, error 1040-20-20-20cycle 4, 20m, error 1040-20-30-24cycle 17, 1h45m, error 1 - COULD BE 1.5 VDIMM /w this setting OR 56-0-040-20-20-24Cycle 23, 2h30m, error 1, 1, 1 (back to back), then completed to 25 cycles, no other errors40-20-30-20Cycle 20, 2h, error 2, 2, 2, 040-20-24-20Cycle 4. 20m. Error 1. ran for another 12m, 32m total, error 1, 4RttNom 6 (40 ohm)Cycle 13. 1h20m. Error 3, 3ProcODT 36.9Cycle 3. 20m. error 3


----------



## CarnageBT

Veii said:


> Overall looks like RTTs are not optimal.
> I would try to drop RTT_NOM once more and see if you get PCB crashes
> When you increase ClkDrvStr , you have to lower/weaken RTT_NOM or lower voltage.
> When you lower procODT, you also should lower VDIMM but increase ClkDrvStr or SOC
> If SOC is high, generally weaken RTTs and weaken CAD_BUS (all of them) ~ or just weaken VTT_DDR
> If SOC is high, weaken the 1.8v rail ~ i feel ASRock's decision with 1.83v on stock, is pretty perfect , replicating the voltage on the ASUS board.
> 1.82v was fine, but beyond 1.83v i had issues. I didn't have issues if remain voltages where strange or too low (VDDG, SOC)
> 
> The Error #0 , refresh stable can also be an issue with powerdown & so also SETUP timings
> But can also be overshooting by RTTs
> Tho for RTTs, it often is an explosion of errors at the same time , then peace ~ when signal peak is too strong and reflects back, or fully drops out for a sec
> RTT_WR is dynamic, it will catch issues and adjust ripple ~ but for it to function either RTT_NOM needs to work or PARK, one of both
> Disabled PARK means 0 doesn't mean 240/480ohm. Then RTT_WR takes over
> 
> He/She is close, soo keep trying
> I still would give tRRD_L a bump at 5
> and tWTR_L a bump at 10
> Just for good measure
> These tRRD's are too low, they will cause issues , not only with 4 dimms not only with "great" PCBs but also on low primaries
> They add performance, but primaries mean much more. Pushing them higher can help in stabilizing your lower tRCD_RD


Thank you for this info. I will begin testing with it tomorrow. The only point I currently debate, is if I'm close, do I just keep pushing till I find stability with the current settings? 
OR do I scrap it all, and re do the procODT, RTTs, etc....


----------



## mongoled

Drevi said:


> Seems good so far, gonna let it run all night when I go to bed.
> 
> View attachment 2514364


Re Y-Cruncher long duration runs, just be aware that Y-Cruncher will tax the CPU hard, some people dont like high temperatures for some reason, just wanted to point that out. I have in the past run over 8 hours Y-Cruncher though through experience if it passes the first 3 hours ive never seen an error after that ....

Can you post your CO and boost override settings for this run ?



CarnageBT said:


> Yea, I saw it, also looked at the fans. Pretty cool. How / Where do you mount those fans?
> At the moment my case has quite high airflow, it's a lian li lancool ii mesh, with all fan spaces maxed out, 8 incl. the aio.
> 
> My ram never exceeds 48.5c, during testing, so it stays below 50 where errors typically develop for b die. It's actually only dimm1 that gets to 48.5c during MT5; max temps are - dimm1 44.5c, dimm2 48.5c, dimm3 45c, dimm4 46c.


You should put some fans just as a troubleshooting tool to rule out that it is heat accumalation that is the cause of the inconsistencies, if you put the fans and there are no changes to the consistency of the errors then you will then know its not heat related.



1s1mple said:


> Here's almost 6 hours of testing my curve (all cores -10 with PPT 200 TDC 70 EDC 130) with Y Cruncher
> 
> 
> View attachment 2514372


Same as explanation to Drevi, you would have better overall system performance/efficiency tuning each core seperatly, but its fine if you go all core CO, you just need to invest more time





CarnageBT said:


> Thank you for this info. I will begin testing with it tomorrow. The only point I currently debate, is if I'm close, do I just keep pushing till I find stability with the current settings?
> OR do I scrap it all, and re do the procODT, RTTs, etc....


Im confident that if you drop tRCDRD to 16 you can call it a day, you are now in the realms of chasing the white rabbit



I spent most of yesterday trying to find a magic combo for my bad stick but did not come up with anything.....


----------



## mongoled

ManniX-ITA said:


> Running y-cruncher standalone is not enough if you are using PBO.
> It will run on all cores, lower frequency.
> To properly test CO you need to check with CoreCycler, one single core at a time.
> And also avoid using at all the PC if possible.
> Otherwise the core under test will slow down in frequency.
> 
> You can also use y-cruncher with CoreCyler.
> But it's better to use as well Prime95 with CoreCycler and run all the FFT sizes from 4K to MAX:
> 
> 
> 
> Code:
> 
> 
> # Smallest:     4K to   21K - Prime95 preset: "tests L1/L2 caches, high power/heat/CPU stress"
> # Small:       36K to  248K - Prime95 preset: "tests L1/L2/L3 caches, maximum power/heat/CPU stress"
> # Large:      426K to 8192K - Prime95 preset: "stresses memory controller and RAM" (although dedicated memory stress testing is disabled here by default!)
> # Huge:      8960K to   MAX - anything beginning at 8960K up to the highest FFT size (32768K for SSE/AVX, 51200K for AVX2)
> # All:          4K to   MAX - 4K to up to the highest FFT size (32768K for SSE/AVX, 51200K for AVX2)
> # Moderate:  1344K to 4096K - special preset, recommended in the "Curve Optimizer Guide Ryzen 5000"
> # Heavy:        4K to 1344K - special preset, recommended in the "Curve Optimizer Guide Ryzen 5000"
> # HeavyShort:   4K to  160K - special preset, recommended in the "Curve Optimizer Guide Ryzen 5000"
> 
> Of course it takes a huge amount of time.
> But running "All" with SSE/AVX/AVX2 is the only way to be 100% all is working fine.
> 
> You should run at least 20m cycle per core (thermal equilibirum):
> 
> 
> 
> Code:
> 
> 
> # - Prime95 "Smallest":     4K to   21K - [SSE] ~3-4 Minutes   <|> [AVX] ~8-9 Minutes    <|> [AVX2] ~8-10 Minutes
> # - Prime95 "Small":       36K to  248K - [SSE] ~4-6 Minutes   <|> [AVX] ~14-19 Minutes  <|> [AVX2] ~14-19 Minutes
> # - Prime95 "Large":      426K to 8192K - [SSE] ~18-22 Minutes <|> [AVX] ~37-44 Minutes  <|> [AVX2] ~38-51 Minutes
> # - Prime95 "Huge":      8960K to   MAX - [SSE] ~13-19 Minutes <|> [AVX] ~27-40 Minutes  <|> [AVX2] ~33-51 Minutes
> # - Prime95 "All":          4K to   MAX - [SSE] ~40-65 Minutes <|> [AVX] ~92-131 Minutes <|> [AVX2] ~102-159 Minutes
> # - Prime95 "Moderate":  1344K to 4096K - [SSE] ~7-15 Minutes  <|> [AVX] ~17-30 Minutes  <|> [AVX2] ~17-33 Minutes
> # - Prime95 "Heavy":        4K to 1344K - [SSE] ~15-28 Minutes <|> [AVX] ~43-68 Minutes  <|> [AVX2] ~47-73 Minutes
> # - Prime95 "HeavyShort":   4K to  160K - [SSE] ~6-8 Minutes   <|> [AVX] ~22-24 Minutes  <|> [AVX2] ~23-25 Minutes
> # - y-Cruncher: ~10 Minutes
> # Default: 6m
> runtimePerCore = auto
> 
> So use Auto to test all FFT or set it to at least 20 minutes if the cycle will last less, like with Small set.
> 
> I gave up after running all FFT in SSE, too much time on a 5950x
> One day I'll test as well AVX and AVX2.
> 
> You should also consider CPPC Preferred cores.
> In a normal usage only the first best 2-3 cores will ever run at full speed tested with CoreCycler.
> Once the scheduler will distribute load and threads to the other cores the total load will be higher and they'll run at a lower frequency.
> So if you want to save some time you could take a shortcut and test thoroughly only the best ones.


Though I fully agree with these sentiments, the key words out of all this for me is the following



> *To properly test* CO you need to check with CoreCycler, one single core at a time.


I do wonder if AMD "properly" test their CPUs in the manner you have described above, i.e. recycling each core through every possible combination of instruction set to see where a crash will be induced. Looking at posting history since Zen's release I highly doubt they do!

So the burden of how to define the word "proper" is down to the end user, obviously the "proper" way is to do what you have said above.

Now, for me personally, I prefer to spread my testing across a plethora of tests, some more lengthy than others, hence the reason I said at the sentance you quoted



> After Y-Cruncher is stable I do another CoreCycler, then use the system normally for an extended period of time to possibly catch idle crashes before moving to other types of stress tests


I do take it upon myself (rightly or wrongly) to "evaluate" the poster and their posting history to determine how much information to feed to that particular poster, as too much information for most people is not a good combination for learning!

If after giving information that may be slightly "sparce" in the eyes of others and seeing that the poster I am giving information is open to receiving more info, its only then that I may go into more detail if I feel it is of benefit to the poster.

Some people may not agree with this methodology, though it has served me well in this journey through life


----------



## ManniX-ITA

mongoled said:


> I do wonder if AMD "properly" test their CPUs in the manner you have described above, i.e. recycling each core through every possible combination of instruction set to see where a crash will be induced. Looking at posting history since Zen's release I highly doubt they do!


I'm not so sure they are so thoroughly.. they probably have some optimized code that works 99% of the times and takes a fraction of that time. Costs 



mongoled said:


> Now, for me personally, I prefer to spread my testing across a plethora of tests, some more lengthy than others, hence the reason I said at the sentance you quoted


Yes, what I mean for proper it's about running a single core at max frequency.
When you change the CO count to negative the VID will be lower and the frequency higher (most of the times).
You have to test load on a single core and not an all-core test like y-cruncher (without CC).
That's also needed but on a final step.

Otherwise, which is what I see happening most of the times, after a few weeks the poster comes back with: I was watching a video on Youtube with Chrome and my PC suddenly rebooted, could be my CO config?

And it's almost always that, cause they never tested this scenario.
Testing with Geekbench 5 is helpful but it can easily miss instabilities with 2nd/3rd best core running the ST benchmark.
CC or OCCT with CoreCycling are really a must to ensure stability with CO.

In general I agree with your methodology 
But in this case I think it's better to be clear that is really needed to test each core, at least the best ones, separately.
Otherwise the risk of random reboots even after weeks is very very high.


----------



## mongoled

ManniX-ITA said:


> I'm not so sure they are so thoroughly.. they probably have some optimized code that works 99% of the times and takes a fraction of that time. Costs
> 
> 
> 
> Yes, what I mean for proper it's about running a single core at max frequency.
> When you change the CO count to negative the VID will be lower and the frequency higher (most of the times).
> You have to test load on a single core and not an all-core test like y-cruncher (without CC).
> That's also needed but on a final step.
> 
> Otherwise, which is what I see happening most of the times, after a few weeks the poster comes back with: I was watching a video on Youtube with Chrome and my PC suddenly rebooted, could be my CO config?
> 
> And it's almost always that, cause they never tested this scenario.
> Testing with Geekbench 5 is helpful but it can easily miss instabilities with 2nd/3rd best core running the ST benchmark.
> CC or OCCT with CoreCycling are really a must to ensure stability with CO.
> 
> In general I agree with your methodology
> But in this case I think it's better to be clear that is really needed to test each core, at least the best ones, separately.
> Otherwise the risk of random reboots even after weeks is very very high.


The only slight concern I have with this is that even if we assign an affinity to a process on a core and hammer that core across various workloads to maximise the peak frequency, this type of simulated testing is not what occurs in most "real World" scenarios.

Its the "idle" boosting that is often an issue with CO, when we use tools such as Prime95 to cycle cores they dont mimick this type of scenario but full single load core scenario.

Maybe using boost tester for several hours is a better test for CO ..........??


----------



## ManniX-ITA

mongoled said:


> Maybe using boost tester for several hours is a better test for CO ..........??


No you really need some workload, like Prime95 or y-cruncher.
It's not like real workload but so far I've never seen an instance where fixing it with CC would not fix also random reboots.
Usually it's even fixed before getting it fully stable with CC...

Unless the issue it's not pure core stability but some Over Boosting issue where the core jumps to crazy high frequencies from idle.
But that should be fixed by other means with different settings (that's wher DF C State disabled can help) or a better power plan.


----------



## Taraquin

mongoled said:


> Well yeah, thats where you would re-tweak your CO values, thats if you actually want to increase your single core top frequency.
> 
> Im at +200, with +5 | -3 | -7 | -6 | +6 | -9
> 
> All core boost 4850, CB23 @4600, Prime95 Small FFTs @ 45xx
> 
> If you are really lucky you will get the below
> 
> 😂 😂
> 
> View attachment 2514337


I could probably do +200 PBO with some adjustments to the CO values, but 4.6MC, 4.7SC is good enough and temps and noise are far better vs +200PBO which I ran for a day with -30 CO before I noticed instability. I also undervolt and underclock my GPU to make it silent. Noise and low temps are more important than a few percept performance


----------



## Taraquin

kim nk said:


> I think the set is flawless
> Only tRP would need to be 12 , but this requires more voltage - and more voltage means different RTT
> 
> Also it looks like it wants ClkDrvStr a bit ~ but your procODT is far lower than usual
> This likely is the reason for low cLDO_VDDP
> 
> Test the timings and adjust procODT up and down 28-34ohm , 3 options one of 3 will only have zero variation on Aida64. 0.3ns or more is instability and autocorrection
> Formula you used for tRAS is tRCDmax + tCCD_L or tBL
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Currently it was used as 14+6=20 (bios issue soo 21)
> tRC is tRCDWR+tCWL+tWR+tCCD_L or tBL
> 8+14+12+6=40
> 
> Both are issues because tRP + tRAS does not equal tRC
> I think your tCCD_L is 6 here
> Try maybe this first
> (2T needed 1.54~, 1T needed 1.6v)
> 
> 
> 
> 
> 
> 
> 
> 
> Next one is this but with your own RTTs
> 
> 
> 
> 
> 
> 
> 
> 
> Looking at it now, it looks amateur 🙊
> Too high tRDWR high SD,DD and not even tWR 10. Also ignore GDM, this is a weak preset but timings are ok i think
> 
> Buut you can also try to go for tCL 13 :^
> Just need to start running tCKE and RTT_WR , in order to utilize voltage beyond 1.6v
> Your cooling is far better than mine


Hello, I tested the value you asked me to try recently. To run the BIOS memory voltage 1.6V 1XTFAW, you asked me to do TRAS + 1 = TRC, and I was wondering here. I wonder what formula TRRDS, TRRDL, TFAW, TWTRS, TWTRL used. And what should we do with the 3800 14-10-14-12-26-38 that you asked me to test at the end, "RTT" 0/0/5, 7/0/6? Do you need to perform a voltage of 1.6V for 1T memory voltage? And I wonder what the most efficient practical use of the CL14 3800 is among the most effective. Thank you so much for always teaching me! 

14-14-14-14-28-29. 1T 1.6V
View attachment 2514342

[/QUOTE]
Do you really need 1.22v soc for 1900 fclk? It eats into the CPU budget. On my setup 1.06V is more than enough for 1900 fclk.


----------



## kim nk

Taraquin said:


> Hello, I tested the value you asked me to try recently. To run the BIOS memory voltage 1.6V 1XTFAW, you asked me to do TRAS + 1 = TRC, and I was wondering here. I wonder what formula TRRDS, TRRDL, TFAW, TWTRS, TWTRL used. And what should we do with the 3800 14-10-14-12-26-38 that you asked me to test at the end, "RTT" 0/0/5, 7/0/6? Do you need to perform a voltage of 1.6V for 1T memory voltage? And I wonder what the most efficient practical use of the CL14 3800 is among the most effective. Thank you so much for always teaching me!
> 
> 14-14-14-14-28-29. 1T 1.6V
> View attachment 2514342


Do you really need 1.22v soc for 1900 fclk? It eats into the CPU budget. On my setup 1.06V is more than enough for 1900 fclk.
[/QUOTE]
In my case, soc voltage is enough to perform 1.1vcl143800. The timing we performed now was the same as teacher "veii"'s. The timing of my actual use is as shown in the picture below.


----------



## Drevi

mongoled said:


> Can you post your CO and boost override settings for this run ?


Vcore soc 1.112v 
Dram 1.4v
CPU LLC auto
Soc LLC high 
CO -15 -20 -15 -5 +3 -20
PBO +200mhz
PPT/EDC/TDC motherboard
Scalar auto


----------



## mongoled

Taraquin said:


> I could probably do +200 PBO with some adjustments to the CO values, but 4.6MC, 4.7SC is good enough and temps and noise are far better vs +200PBO which I ran for a day with -30 CO before I noticed instability. I also undervolt and underclock my GPU to make it silent. Noise and low temps are more important than a few percept performance


Yeah, I dont notice any difference when using 200 mhz or less with regards to noise or temps as its only single core that is going to boost slightly higher and being on water it makes no difference.

So I already have low temps and low noise



Obviously you have chosen whats best for you.





Drevi said:


> Vcore soc 1.112v
> Dram 1.4v
> CPU LLC auto
> Soc LLC high
> CO -15 -20 -15 -5 +3 -20
> PBO +200mhz
> PPT/EDC/TDC motherboard
> Scalar auto


Thats an excellet sample 5600X!

Can you tell me what you score with CB23 ?

Looking at those CO values and settings you posted you should be getting close to 12300 if temps are not an issue for you and everything is tweaked correctly


----------



## CarnageBT

Funny to wake up to see you two, @mongoled and @ManniX-ITA talking about CO and CC. I just ran that test last night to confirm my curve. 

Ran ALL FFT's for 65m/core, so it would complete all FFT's and loop a tad. Still waiting on 2 cores to finish but likely will, everything else has from previous settings.

My settings are, 250 PPT // 175 TDC // 185 EDC // +200mhz boost // Scalar auto (1x)

Core - Logical CoreCurve Offset0 - 0 / 1-191 - 2 / 3-182 - 4 / 5-303 - 6 / 7-124 - 8 / 9-295 - 10 / 11-306 - 12 / 13-187 - 14 / 15-308 - 16 / 17-249 - 18 / 19-3010 - 20 / 21-2811 - 22 / 23-30


----------



## sendap

i do have a question about voltage settings. I stumbled upon this post from @Veii from 7 months ago. Does this ruleset still hold true (40mv stepping) and if so, do i need to apply it for the get or set value of VSOC?

I did not exactly apply those rules to my current setup as i was not aware of it. It is 100% stable though. But for the future (going up with IF) it would be good to know


----------



## craxton

Has anyone else had a CPPC-Preferred core order to
Change in what order cores are chosen?
Mine used to be 4-6-1-2-3-5 now it's 1-2-3-4-5-6
I'm unaware that I've updated any drivers, windows log doesn't show any driver updates, just definition updates. (could it be bc of curve offset?)

(Using occt info to show this info) unsure if it reads correctly or not.
Is this normal, how are these CPPC cores chosen?
(Am now running a per-core offset) so no longer running the all core -30 +50mv offset. (Running amd voltage option inside bios as well. Sil quality is still 80 but no WHEA 18s in quite sometime. Turned off df states, is that a reason CPPC changes?
Edit-Will add pics of new core order, once I'm home-








(EDIT-UPDATE)


----------



## Drevi

mongoled said:


> Thats an excellet sample 5600X!
> 
> Can you tell me what you score with CB23 ?
> 
> Looking at those CO values and settings you posted you should be getting close to 12300 if temps are not an issue for you and everything is tweaked correctly


11950-11970. I have a CLC280, runs CB23 at 80°.


----------



## PJVol

craxton said:


> 1-2-3-4-5-6


It usually means CPPC is disabled in bios or somewhere else.


----------



## hazium233

Drevi said:


> Does it matter that mine are 16GB dimms?
> ---
> What would that be?
> 
> (sorry to ask, kind of a noob on memory fine tuning)


I am not running them right now, and this was really kind of half assed on the timings, but:









I don't know how well PBO really helps or hurts the numbers, but that is default.

I think generally the effect of bin for Rev E is mostly lower tRCD with higher bin. I also need 20t tRCDRD at 3800 for various 3200 sticks, the 3600 bin should always be lower.

I didn't test tWR down at this speed, tWTR_, or fix tWRRD. So those may not be quite right. I leave tRP looser on these, closer to tRC - tRAS rather than try to push them down.


----------



## Drevi

hazium233 said:


> I am not running them right now, and this was really kind of half assed on the timings, but:
> View attachment 2514464
> 
> 
> I don't know how well PBO really helps or hurts the numbers, but that is default.
> 
> I think generally the effect of bin for Rev E is mostly lower tRCD with higher bin. I also need 20t tRCDRD at 3800 for various 3200 sticks, the 3600 bin should always be lower.
> 
> I didn't test tWR down at this speed, tWTR_, or fix tWRRD. So those may not be quite right. I leave tRP looser on these, closer to tRC - tRAS rather than try to push them down.


Pretty similar to what I'm running. Some are the same, some lower, some higher. But I have the same test results, except L3 cache, mine are much higher (560 BG/s) but I think that one depends on PBO. 

Gonna try to copy this and see if I get better results.


----------



## craxton

PJVol said:


> It usually means CPPC is disabled in bios or somewhere else.


thats what i thought too, but its turned on (in all three places) well, on auto for DF-Cstates/CPPC cores,
the one thing thats strange is this tho,










(CTR showing ALL CORES as 131?)
perhaps on my board turning off DF-STATES auto kill CPPC?
"NOTES" running core-cycler has passed 7 iterations now. (all FFT sizes)
my CO is

CORE 1 -15CORE 2 -20CORE 3 -15CORE 4 +5CORE 5 -11CORE 6 -10
(NO offset running this time around) if CPPC was turned off would cores idle down still ?
considering ive ran core-cycler for this long and passed, i suppose i may just LEAVE THIS THE HELL ALONE
since im running better than ever. about to run some benchmarks and test with what i did have before hand.


(EDIT) does anyone else have this many options for C-states, CPPC?


----------



## PJVol

craxton said:


> but its turned on


If so, then acpi seem broken. Try to run CB Rxx single core test and look at the cores, which are under load.


----------



## Veii

CTR turns on DF-C States once you run diagnose , or run the tool/use the tool
ZenStates will report it's off, but CTR turns it on temporary till you press the "Exit" button

EDIT:
This is the old Zenstates 2.0.Alpha
irusanovBG doesn't want to publish it yet, but it's not forbidden to me
Don't blame him for bugs, or complain about the tool please (this was also his request)
PBO stuff doesn't work for example
But the flags do work


https://cdn.discordapp.com/attachments/847219304210366524/855603462288310302/ZenStates_2.0.0_debug_20210120.zip










This has to be off
EDC value will also missreport and the bottom field doesn't function

If bioses lack DF-C States, which this tool on autoruns, you can always disable them to prevent random reboots
@mongoled 8ghz example had DF-C states on, as it overboosted that high
* I publish it, because the lack of bios options from MSI and Gigabyte (closed down AMD CBS) starts to get annoying


----------



## craxton

Veii said:


> CTR turns on DF-C States once you run diagnose , or run the tool/use the tool
> ZenStates will report it's off, but CTR turns it on temporary till you press the "Exit" button
> 
> EDIT:
> This is the old Zenstates 2.0.Alpha
> irusanovBG doesn't want to publish it yet, but it's not forbidden to me
> Don't blame him for bugs, or complain about the tool please (this was also his request)
> PBO stuff doesn't work for example
> But the flags do work
> 
> 
> https://cdn.discordapp.com/attachments/847219304210366524/855603462288310302/ZenStates_2.0.0_debug_20210120.zip
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This has to be off
> EDC value will also missreport and the bottom field doesn't function
> 
> If bioses lack DF-C States, which this tool on autoruns, you can always disable them to prevent random reboots
> @mongoled 8ghz example had DF-C states on, as it overboosted that high
> * I publish it, because the lack of bios options from MSI and Gigabyte (closed down AMD CBS) starts to get annoying


completly reset the bios (not reflashed) 
ctr showed (default values which showed my worst core as 125 and 129 the rest were ALL 131.
(hadnt ran diag on CTR tho, just opened it to see what core scores were)
also used core cycler tuner as well which shows the values listed below.
(the values below are with a new profile but with all my values entered) 
just no turning off CPPC, DF states are off in one area of the bios. the rest are still auto. 
(did try all other areas off) but still the same outcome. CPPC order is 123564??? used to be 461235 lol.
if what you shared doesnt work, ill reflash the bios. (only the none modded version) 
and see if that changes anything.


----------



## craxton

HMMM, now the "active cores" that were NOT ACTIVE EVER using the "tool" monitor feature (just opened it for the first time (TODAY)
shows that core 3 and 7 are no longer active. but before it was core 2 and 4 being turned off....?
...i broke something....


----------



## Veii

craxton said:


> if what you shared doesnt work, ill reflash the bios. (only the none modded version)
> and see if that changes anything.


use AFUWIN, windows flashing utility and override all blocks
else there is a partition aside from AMD CBS, aside from CMOS which brands have no access to
USB dropout issues by "unclean" updates - especially on MSI sit there

It doesn't flash cleanly the normal way
but ignoring that recent 21H1 is buggy with CPPC and 1202 is buggy + AMD took AGESA 1200 down ~ while every boardpartner doesn't have 1203A out

=====================
On CTR RC06
use the Update, CTR thing
There are bugfixes there too, latest version is revision 23
Everything kind of feels broken right now. Still waiting for 1203A for X570 MSI & ASRock boards

CPPC broke for this guy too








AMD Gremlin's , many little gremlin's


----------



## craxton

Veii said:


> use AFUWIN, windows flashing utility and override all blocks
> else there is a partition aside from AMD CBS, aside from CMOS which brands have no access to
> USB dropout issues by "unclean" updates - especially on MSI sit there
> 
> It doesn't flash cleanly the normal way
> but ignoring that recent 21H1 is buggy with CPPC and 1202 is buggy + AMD took AGESA 1200 down ~ while every boardpartner doesn't have 1203A out
> 
> =====================
> On CTR RC06
> use the Update, CTR thing
> There are bugfixes there too, latest version is revision 23
> Everything kind of feels broken right now. Still waiting for 1203A for X570 MSI & ASRock boards
> 
> CPPC broke for this guy too
> 
> 
> 
> 
> 
> 
> 
> 
> AMD Gremlin's , many little gremlin's


i actually figured out what the issue was.
STRANGE ISSUE AT THAT. using the windows power utility (inside your gdrive) the same
power utility editior for unlocking/unhiding windows power stuff that i used that i set 0mhz as my core last time
and made a potato out of my OS,
none the less, i set 5000mhz as max for well pic below.
and thats what was causing this issue?
had already flashed the bios before seeing this reply.
(which did NOT fix this issue, importing my saved power file immediately solved this issue without needing to restart
nor did re-installing chipset drivers "latest version" either)
(i dont have USB dropout issues, which is why i asked if anyone would like to see whats "default"
inside the advanced options tabs, ALL of them a while back.. perhaps something inside the bios on this boards on or off that may affect whea, and USB issues?
(atm default core score (only changing PBO leaving mhz to auto in bios) are
now where they should be, CTR was reading wrong as they were all 131? (before fixing)
now its, 137+133+129+140+125+140
(was never a 131 score period other than my "worst" core with 200mhz auto oc enabled?)
still dont understand why active cores using the "tool" amd Vermeer monitor changed...
i gotta watch myself on programs like power explorer lol else, ill have a case of issues and scratching my head trying to figure out what i changed.
will now attempt to re-run core cycler overnight with DF-STATES off and CPPC ON.

i was smart enough this time around to have made a backup of my power plans using export and saved said backup
to my gdrive. still, setting 5000 should not have affected this should it not?


----------



## Veii

craxton said:


> i was smart enough this time around to have made a backup of my power plans using export and saved said backup
> to my gdrive. still, setting 5000 should not have affected this should it not?


A frequency limit there is helping if DF_C-States enable themself
soo in case of an overboost, there are two more limiters who cut down the spike, preventing a reboot

It does nothing in harm, except hardcap the maximum frequency you can run


----------



## craxton

Veii said:


> A frequency limit there is helping if DF_C-States enable themself
> soo in case of an overboost, there are two more limiters who cut down the spike, preventing a reboot
> 
> It does nothing in harm, except hardcap the maximum frequency you can run


i seen you mentioned this, which is why i set it in the first place. 
but removing that seemed to have restored CPPC-CORES back to 4-6-1-2-3-5 order vs 1-2-3-4-5-6 or whatever it was.
going to try again to set this 5000mhz limit (should i set it for max processor freq, and the option below that as well?)

(when i booted into windows it was showing cores being 1-2-3-4-5-6 or whatever for CPPC 
which was after re-flashing bios, re-installing drivers, re-enabling my RAM profile and CO tune,
but nothing had changed the order. once i removed the 5000mhz limit (only on the one i highlighted is where it was placed)
did CPPC then begin to show 4-6-1-2-3-5 which is what it used to show.) 

perhaps, if your experiencing the same thing im getting, if you changed this, import your saved power file as well.
and see if it changes? (just a thought)


----------



## craxton

CONFIRMED (posted screenshots are on the SAME BOOT meaning i have NOT restarted windows, simply set 5100mhz in power explorer utility 
and checked OCCT which said CPPC cores were 123654 then i imported my saved profile, and closed OCCT reopened it, and CPPC cores were
461235
(CPPC cores before changing any values in power explorer was correctly shown, was only after did it change CPPC cores order.
(yes my EDC value is absurd but, im testing some-things) also take note in 6x scaler, 
so far this has been the go-to value for this chip. 
no overvolting noticed, no crashing, (still need to re-run core-cycler) then y-cruncher or together to see 
but the curve offset inside the bios now is giving me -30 +50mv offset with 1A EDC scores. (+ or - 20 points) 
12111 r23 4663 r20 (2 runs each) 3rd run dropped R23 to 11998) something i killed started back up...

perhaps, its not the 5000mhz thats causing this issue in power explorer, rather another setting ive not changed thats defaulted 
(then again, that doesn't make much sense considering i exported before changing 5000mhz value, changed nothing else only 5000mhz as shown in 
previous post.)

confused to whats going on with this, but @Veii maybe you should revert the change if you made one on power explorer and see if you notice a change as well.
shouldnt need to reboot to see it, i didnt anyhow as mentioned above.

if anyone else can speak on what setting inside power explorer is causing this, lmk. would like to be able to use this without fear...


----------



## Veii

craxton said:


> perhaps, if your experiencing the same thing im getting, if you changed this, import your saved power file as well.
> and see if it changes? (just a thought)


I will test
Figured that ManniX-ITA's powerplans break CPPC on 21H1 somehow
But this did not do anything before - will try


----------



## craxton

Veii said:


> I will test
> Figured that ManniX-ITA's powerplans break CPPC on 21H1 somehow
> But this did not do anything before - will try


im not running any modified power plans. 
i am running 21H1 tho, so the update in windows might be the issue.


----------



## mongoled

Drevi said:


> 11950-11970. I have a CLC280, runs CB23 at 80°.


Thats running CB23 at priority "Realtime" ??

If the above run is "Realtime" can you do another run but with normal priority with HWInfo64 open and note what all core frequency is ?

I would have expected your score to be higher, but it looks like you are thermal limited.

See below pic from my setup of CB23 where CPU temp is at 73-74C while frequency is at 4660 mhz









I wonder if I can somehow simulate an 80C CB23 run to see how much frequency drops by.

My estimate of being close to 123xx for your CPU is based on CB23 not exceeding 75C.



Veii said:


> CTR turns on DF-C States once you run diagnose , or run the tool/use the tool
> ZenStates will report it's off, but CTR turns it on temporary till you press the "Exit" button
> 
> EDIT:
> This is the old Zenstates 2.0.Alpha
> irusanovBG doesn't want to publish it yet, but it's not forbidden to me
> Don't blame him for bugs, or complain about the tool please (this was also his request)
> PBO stuff doesn't work for example
> But the flags do work
> 
> 
> https://cdn.discordapp.com/attachments/847219304210366524/855603462288310302/ZenStates_2.0.0_debug_20210120.zip
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This has to be off
> EDC value will also missreport and the bottom field doesn't function
> 
> If bioses lack DF-C States, which this tool on autoruns, you can always disable them to prevent random reboots
> @mongoled 8ghz example had DF-C states on, as it overboosted that high
> * I publish it, because the lack of bios options from MSI and Gigabyte (closed down AMD CBS) starts to get annoying


Ugghhhh, ughhhhhh and ughhhhhh

"DF-C States" was/is set to disabled in the BIOS



And ive just ran the tool you kindly shared and look whats its showing and yes, its set to disabled in BIOS, no wonder I cant get consistent results when attempting to tweak PBO with telemetry, no consistency across reboots ......












Veii said:


> AMD Gremlin's , many little gremlin's


Yes toooooooo many, I am on Eder modifed A.A1 BIOS that uses agesa 1.2.3.0a, maybe I am going to have to do a flash with a different utility than the default MSI flash tool .........


----------



## mongoled

So I re-flashed with the AfuWin64 tool, "all blocks"

Still no change with setting "DF-CStates" to disabled as per "ZenStates 2.0.0" debug tool.

So looks like @Eder unhidden options are not taking effect ??

:/


----------



## Takla

Veii said:


> https://cdn.discordapp.com/attachments/847219304210366524/855603462288310302/ZenStates_2.0.0_debug_20210120.zip


Mhh interesting. Performance Enhancer Level 1 sets scalar to 10x for me, yet it is not called OC? Sounds like when some intel mainboards straight up ignore the power target.


----------



## PJVol

mongoled said:


> I would have expected your score to be higher


Why all of a sudden? His score is well inline with others.



mongoled said:


> I wonder if I can somehow simulate an 80C CB23 run to see how much frequency drops by


You may expect roughly 100 pts down per 2°C+
Attached my 77°C run for the reference )) and earlier tests summary (winter BIOS).

May I ask you, what makes your cores run @ such high Vcore and ~ 15W / core ?
Is it some +global offset?


----------



## craxton

one last thing, you mentioned that turning off DF-CTATES in bios is best.
no doubt, but you also showed zen-states and a picture showing what to turn off there.
but once i restarted the pc it somehow has it turned back on again.
(as everyone else is showing) 
C6 state is off, but C6 package stays on...


----------



## craxton

PJVol said:


> Why all of a sudden? His score is well inline with others.
> 
> 
> You may expect roughly 100 pts down per 2°C+
> Attached my 77°C run for the reference )) and earlier tests summary (winter BIOS).
> 
> May I ask you, what makes your cores run @ such high Vcore and ~ 15W / core ?
> Is it some +global offset?











almost 20 watts a core for me....?
(edit) i do have to readjust core 4 on the 9th iteration it had a fail (stated core 3 which is on positive offset) gonna try neg offset
but none the less...


----------



## hazium233

Drevi said:


> Pretty similar to what I'm running. Some are the same, some lower, some higher. But I have the same test results, except L3 cache, mine are much higher (560 BG/s) but I think that one depends on PBO.
> 
> Gonna try to copy this and see if I get better results.


Yeah L3 is from my EDC being at default 90 or whatever, vs higher. But also some might be CCD since I was playing with that and the B-die at 3800 and it may get a tiny boost with CCD being tuned more optimally.

* But while I didn't spend a lot of time on the timings, I did spend a while looking at various ProcODT and CAD combos as well as checking SOC and IOD steps to see what gave the best latency and latency consistency.

As for the timings, I don't think 8t tRDWR will boot without more vdimm for me. The tWRRD was an oversight, but since I left tWTR at 4, 12 it may need more than 2, I don't know. I ran tWR at 16t at 3733 so 24t is probably not needed here, but my 3733 set needed a little more voltage which was from that and lower tFAW (16t).

Similarly, I think that 57t tRC should run without too much problem or a lot of voltage. I had 56t at 3733 with the above 1.42. Probably 56t will work here too.

I don't try to tighten tRP way under tRC - tRAS anymore for anything resembling daily. You could try if you want, but I don't think it makes much sense on E really.

** 3733 set was 16-18/19-18-38-56. The 3800 set was a little faster with less voltage and looser timings -> Super Pi, GB3, SotTR... the latter being no difference in GPU fps when GPU limited of course, heh.


----------



## XPEHOPE3

Can anyone please explain why would CPU FSB (BCLK) be reported lower than 100MHz, as in screenshot?









Under those combinations (not everything combination tested, but most of them):
BIOS: PBO off or Enabled (mobo limits), Scalar 1x or Auto, BCLK Auto or 100MHz, DF States disabled or Auto
Windows: both balanced and max performance power plans.
That happens with any load (idle, Aida latency test, TM5 1usmus_v3).

PS: previously there were runs where FSB would report 100MHz, and the rest of frequencies would be normal 4650 and 1600/1800

Effective CPU clock is actually 4650MHz, and AMD monitor shows that CPU freq limits are 4650MHz, not 4593.7:








So the other question is: if effective CPU clock is unaffected, what clock does my RAM run at actually? 1580.6 or 1600?
Due to this I'm unsure if TestMem5 runs are testing what actually matters


----------



## Art385

XPEHOPE3 said:


> Can anyone please explain why would CPU FSB (BCLK) be reported lower than 100MHz, as in screenshot?
> View attachment 2514534
> 
> 
> Under those combinations (not everything combination tested, but most of them):
> BIOS: PBO off or Enabled (mobo limits), Scalar 1x or Auto, BCLK Auto or 100MHz, DF States disabled or Auto
> Windows: both balanced and max performance power plans.
> That happens with any load (idle, Aida latency test, TM5 1usmus_v3).
> 
> PS: previously there were runs where FSB would report 100MHz, and the rest of frequencies would be normal 4650 and 1600/1800
> 
> Effective CPU clock is actually 4650MHz, and AMD monitor shows that CPU freq limits are 4650MHz, not 4593.7:
> View attachment 2514535
> 
> 
> So the other question is: if effective CPU clock is unaffected, what clock does my RAM run at actually? 1580.6 or 1600?
> Due to this I'm unsure if TestMem5 runs are testing what actually matters


Turn off Spread Spectrum


----------



## PJVol

Some boards don't have that option, and actually not a big deal either.


----------



## mongoled

PJVol said:


> Why all of a sudden? His score is well inline with others.
> 
> 
> You may expect roughly 100 pts down per 2°C+
> Attached my 77°C run for the reference )) and earlier tests summary (winter BIOS).
> 
> May I ask you, what makes your cores run @ such high Vcore and ~ 15W / core ?
> Is it some +global offset?


What do you mean by all of a sudden? Taking into account the temperature of the CPU during the CB23 run you are correct his scores are in line with others. 

I was going on the assumption (a bad one) that Drevi CPU could do CB23 at around 75C and gave too much weight to the high negative CO offsets he is able to give to his CPU. 

I wrongly thought that the CO would improve the all core frequency, but the CPUs are thermal limited and even when using such great CO values its not enough to lower the temp when running the benchmark. 

Re the wattage, no idea, im just running AUTO PBO with 200 boost override, CPU/CPU NB LLC on AUTO, Scaler on AUTO, vCORE AUTO, CPU switching frequency 800, SoC switching frequency 600, no telemetry 

It's a substantial difference to your system. 

🤔


----------



## oobymach

> oobymach said:
> 
> 
> 
> Just learned this recently, TRC x TRTP = TRFC, do with this as you will but it seems to help.
Click to expand...




Takla said:


> Not applicable for micron e-die.


Actually it should work for any ram type, tRTP goes up to 14 and it works even on my crap hynix MJR chips, it just runs a lot lower on b-dies.

In my hynix 32gb kit tRC 57 x tRTP 12 = tRFC 684


----------



## craxton

@PJVol 
you asked mongol about having 15 watts per core, is this not normal ? 
i do know that anything less than 13 watts i dont hit 46/4570mhz 
this is R23 running
with CO tuned (minus one core being retested but since its boosting now to where it should
i believe it might be more accurate of where it should be)
auto scaler, manual PBO settings, 200mhz auto, 
DF-Cstates are turned off, but the pic Veii showed states when opening zen-states that its bugged 
and only turns off core-C6-state and leaves on Package C6-state.
(note i did not change it before this test using zen states) but can see while leaving HWiNFO open that C6 residency
is used while package is off, and package is used while C6 state is off. 
both being off uses C1 residency. (actual r23 score (now) is 11968) didnt save it however.


----------



## Art385

mongoled said:


> What do you mean by all of a sudden? Taking into account the temperature of the CPU during the CB23 run you are correct his scores are in line with others.
> 
> I was going on the assumption (a bad one) that Drevi CPU could do CB23 at around 75C and gave too much weight to the high negative CO offsets he is able to give to his CPU.
> 
> I wrongly thought that the CO would improve the all core frequency, but the CPUs are thermal limited and even when using such great CO values its not enough to lower the temp when running the benchmark.
> 
> Re the wattage, no idea, im just running AUTO PBO with 200 boost override, CPU/CPU NB LLC on AUTO, Scaler on AUTO, vCORE AUTO, CPU switching frequency 800, SoC switching frequency 600, no telemetry
> 
> It's a substantial difference to your system.
> 
> 🤔


On my 5800x and MSI B550 Tomahawk bios A71 AGESA 1.2.0.3A if I set negative [email protected] (or positive) for problematic cores (rest are quite great form -22 to -30) it will cap voltage, frequency and power draw to around 120W (limit is 142) in CB20 MT test. Voltage will drop to ~1.25-1.28v. Setting them to -3 will shift whole V/F table up and CPU will push around 1.3-1.33v in CB20 and go all the way to set in bios limits. Frequency will also be higher by 50-75MHz though will heat up to 85c instead of 75c. I'm very happy with this finding as at those settings my CPU is always stable at last in core cycler through all FFT sizes (auto setting). 
After weeks off testing and getting random fails even after reboot on settings that was running stable for like 8h in CC xD 
It's also really easy to set up so I will share as it works - maybe it will save someone some time. You just need to set Scalar to x1 autoOC off then set all the "good" cores that will not randomly fail to max negative offset that is stable (couple of iteration will do). Now you will need to find when "capping" occurs in CB20. To do this set low negative offset on bad/failng cores - good place to start is -1 at least on MSI though it can vary per config curve setting. Now just push negative offset on those cores up to the point where V/F table shifts - don't touch other cores offsets (bump 1 point on Curve at a time to know exactly when it occurs). This will be rock stable setting. 
Now if you want you can fine tune offset. You can go again by one point (more time) or just bump by 5 points. Now this is a little tricky as you will need to test one pass on those ****ty cores (set rest of the cores as ignored in CC config file) If test will pass turn off PC completely and retest. On my system cores will fail on second testing attempt if their are unstable. If cores fails just back down CO offset by 1 on these cores to the point when after every power cycle CC will pass. Done, when you set CO this way bad cores will never boost past stability and randomly fail. Now you can retest all the cores - 6 iteration on auto setting for time per core should be enough.

Sorry for my English


----------



## PJVol

mongoled said:


> It's a substantial difference to your system.


Perhaps I wasn't clear, I refered to your screen below, with edc limit 110A.


mongoled said:


>


So unless you weren't using CO (that would explain quite high Vcore) I don't see our systems do differ much.


----------



## XPEHOPE3

Veii said:


> finetuned by the manufacture, it's a good thing to have
> It keeps signal integrity in check by lightly combating EMI ~ also helps memOC because of such
> Snapshot pooling will mask/hide it, soo you won't see it as an issue. Don't worry about leaving it enabled, but Hyper-V kernel support, does behave like SpreadSpectrum


Sorry to bother you again, but from this I gather you do recommend setting Spread Spectrum for memory OC. However judging from all your screenshots with Aida or with HWInfo I can see CPU FSB at 100 MHz, suggesting Spread Spectrum (together with virtualization) is actually off.
Or is it just because you don't have any EMIs and there is no need for Spread Spectrum to kick in? How did you manage to achieve this?


----------



## Veii

XPEHOPE3 said:


> Sorry to bother you again, but from this I gather you do recommend setting Spread Spectrum for memory OC. However judging from all your screenshots with Aida or with HWInfo I can see CPU FSB at 100 MHz, suggesting Spread Spectrum (together with virtualization) is actually off.
> Or is it just because you don't have any EMIs and there is no need for Spread Spectrum to kick in? How did you manage to achieve this?


Spread Spectrum, Hyper-V and AMD SVM do change this state
Hyper-V and SVM both are off for me,same as TPM 2.0 (for now ~ will set up Windows 11 Pro Workstation today)


But yes, all 3 options influence it ~ and for me it's on. Like on usually every board.
It varries subtle, as you can see on the GDM picture - where the freq is 4650.*3*
Just be sure to fully disable Hyper-V and SVM (if this bothers you)
Although variance is good, it's not thaat bad anymore. Vermeer varries the whole time with their clock-gen. Don't worry too much


----------



## PJVol

craxton said:


> you asked mongol about having 15 watts per core, is this not normal ?


Its not about being "normal" or not. Just trying to figure something out.
In short, with PBO, cpu's boost constantly thermally limited. I mean not by PROCHOT assertion, but in the way current boost frequency depends on temp. sensors data.
These algorithms and boosted P-states are seemingly hidden even at the ACPI level.

As for 15W, mine when running cbr23 @72-73 C draw ~ 13W per core. So maybe yours and @mongoled higher boosting cores were tuned with higher leakage profile.

Don't get, what all that df- and c- states things was about, sorry ))


----------



## domdtxdissar

Maybe not the correct thread, but win11 seems interesting.. Also for us using cpus with cppc core tags.















> The laptop being used has an Intel Core i7-10875H and an NVIDIA GeForce RTX 2070 Super.
Click to expand...




> One test that he ran was Time Spy in 3DMark, which jumped from a score of 6,872 to 7,613. That’s both a bump in CPU and GPU, with the GPU score increasing from 6,927 to 7,426, and the CPU score increasing from 6,573 to 8,886.
Click to expand...




> For Geekbench, the single-core performance increased from 1,138 on Windows 10 to 1,251 on Windows 11, and the multi-core score increased from 6,284 to 7,444, so there are some impressive improvements there too.
Click to expand...

Now here's the cherry on top, this may also be linked to power management:


> It would seem that Microsoft is adding some new power management. The person that did the testing uninstalled any ASUS software that might have been controlling the fans, so everything that happened there was controlled by the OS. *It was notable that the fans ran differently while running the tests, and as we all know, the cooler the CPU and GPU stay, the better the performance is.
> 
> But the temperatures don’t even seem to reflect that. When running 3DMark, the results said that it ran hotter, but the fans were running louder and more consistently.*
Click to expand...










Windows 11 apparently offers big performance improvements over Windows 10


According to a report, Microsoft's upcoming Windows 11 operating system will offer some impressive performance improvements over Windows 10.




www.xda-developers.com


----------



## XPEHOPE3

Veii said:


> Although variance is good, it's not thaat bad anymore. Vermeer varries the whole time with their clock-gen. Don't worry too much


Do you mean 100->98.8 MHz drop which I get from SVM isn't bad?
I don't understand why you don't have any drop at all and I get a drop that big. Lottery loss or some settings / environment?


----------



## craxton

PJVol said:


> Don't get, what all that df- and c- states things was about, sorry


that was mostly just placed there for "other" to see. 
sorry..


PJVol said:


> As for 15W, mine when running cbr23 @72-73 C draw


im running a CO offset which i stated previously already. but other than that just an EK-DRGB aio hitting 79c
while running R23 (its 76c in my room) fans are full tilt atm. 
but im peaking at 80c while (still holding 457x/4650 mhz (above 4575 is where i notice 13watts per core.
any under on my chip is pushing 13 watts but not quite. 

id have to agree that it is partial due to "leaky silicon" but 
im almost certain the chips better than what i previously thought it was anyhow.


(if i were to lower my temps by not running a wide open PBO set values, im sure i could boost higher during R23 runs and 
beat 12000 points instead of getting this consistently 








i do know that i can alter my CO offset on the one positive core i have and itll lower power per-core to 
a max of 12-13 watts. by alter i mean either direction giving more positive co or less positive co. 

(if i limit in bios 1A edc, with 220 PPT, 440 TDC, 1A edc, 4-6X scaler, then i can hit well over 12000 points.
but as i mentioned a few pages back, threads are limited to 4450? while cores are running at 4700mhz?
"clock stretching perhaps"? temps stay 75c or lower...still tho even if clocks are stretching with 1A edc
benchmarks are WAY HIGHER while keeping temps in check (without limiting PPT, TDC) unsure if 4-6 scaler is needed just the two 
ive used. and 10x as well. 

(pics below are 1A EDC) left most my "auto" startup tasks running while running the below shots.














(power per core stays under 13 watts here tho)


----------



## craxton

quick off topic question, ive noticed that BIOS files on MSI website (mostly my board)
have been getting WAY SMALLER in size. is this due to hidden options being removed, or other unhidden options 
being hidden?


----------



## Veii

XPEHOPE3 said:


> Do you mean 100->98.8 MHz drop which I get from SVM isn't bad?
> I don't understand why you don't have any drop at all and I get a drop that big. Lottery loss or some settings / environment?


Nono, i don't have it because of these 3 things
SVM and Hyper-V both are wiped from the windows kernel (later one is a kernel thing)
First one virtualization is a bios thing

All of these 3 do influence it
Yet it's board dependent
But no its not a big thing at all, do not worry about it ~ you can disable Spread Spectrum if you really want
I know ASUS splits it with D.O.C.P in one location

i do think EMI for me is higher than usual
Router is nearby , 5ghz mesh is running , tube amp for the mic is running
But the system is on an open bench. Unsure how that correlates to EMI buildup ,but it's just board dependent & the 2 features above

==========================
About the big power improvements:
Before








After









There is a "turbo" tag on the powerplans, which are all ryzen powerplans since v1903
All of them behave that way, but the cache results are awkward
Copy and Read are both consistently higher
Latency could be just a bloated OS installation difference

Ultimate Powerplan with ProWorkstation sheduler, performs far worse on L3
Something is fishy, but i point to TPM 2.0 , but will need to retest things
The performance jumps look quite acceptable




 following this youtuber

With and without the powerplan, with and without windows being "power aware" - something is certainly different here
But all these performance improvements can correlate to just an updated thread scheduler, better UEFI module integration and newer kernel
Currently it performs horrible on cache and i need to figure out why
Patch 21996.1 - ProWS Activated (keys do convert upwards)

EDIT:
Also there is no "Turbo" powerplan


----------



## XPEHOPE3

Veii said:


> But no its not a big thing at all, do not worry about it ~ you can disable Spread Spectrum if you really want


Well, I did disable both Spread Spectrum and SVM and got 64.5-67.4ns Aida variety in latency.
And when both were enabled I only had 64.7-64.8 variety.
Funny thing is *why* I had SVM enabled. It was required to run WSL 2.0 and Ubuntu inside it, so that I could run GSAT to stress test memory😂 I think GSAT is unsuitable for stressing max possible overclocks if run under WSL then, since with SVM BCLK clocks @98.8, and with only Spread Spectrum - 99.8.


----------



## Veii

XPEHOPE3 said:


> Well, I did disable both Spread Spectrum and SVM and got 64.5-67.4ns Aida variety in latency.
> And when both were enabled I only had 64.7-64.8 variety.
> Funny thing is *why* I had SVM enabled. It was required to run WSL 2.0 and Ubuntu inside it, so that I could run GSAT to stress test memory😂 I think GSAT is unsuitable for stressing max possible overclocks if run under WSL then, since with SVM BCLK clocks @98.8, and with only Spread Spectrum - 99.8.


@KedarWolf runs GSAT and the Windows WSL kernel

The variance shouldn't be "worse" when you run "less" things
But maybe the WSL kernel indeed is better ~ never tested such thing. Alone the theory is absurd, but it could be a thing.
==============================
Investigating more into Win11 21996.1
The thread scheduler is broken and somehow enforces strange things








This should not happen
These dropout spikes, then it overboosts and FIT throttles back
The flat lines near 140 are peak boosts on single core tests
L3 Read i got up, but i think all powerplans are broken , fully broken

Either that or something with AMD's encryption (PSP Firmware) is broken
Ooor both and my special sample somehow throttles back.
Need to wait couple more weeks till ASRock also finishes 1203A agesa and check back
DF-C States keep being off, Zenstates doesn't lie ~ but bios bugs can disable Global-C State generation when you enable DF-C States, and opposite (it's buggy)
Soo most of the times for buggy bioses to make it stick, you actually need to double reboot the settings and manually enable (disable/enable) again Global C-State generation , else DF- States do turn itself on

Something else on the above
Without PSP aware chipset drivers, it's worse. With , the powerplans are broken and overboost
But this behavior looks like, something enforce-tries to override and turn on DF-C States + FIT throttling back
Bizzare, considering TechYES guy didn't have bad performance with his 5950X . Maybe he didn't notice who knows

Will experiment with DF-C States and DPM, also experiment if we can run TPM off windows
Disabling AMD fTPM did give copy cache bandwidth back, but it's still a broken mess
Also will play with CTR RC06 a bit more (now that it finally works again after reinstall) and see what's up with that

Oh also optimize-offline works , if you edit it a bit


Spoiler












Bottom flags need it erased the ELSE disable
and top one needs to get build support for 21996(.1)

Also








DeveloperMode needs to be off


















At the very end, 
There are two TPM modes and 3 AMD fTPM modes
Change it first to fTPM mode, soo trusted devices come alive on a bios reboot
There change it to TPM 2.0 instead TPM 1.3 mode - soo windows 10 and "older", can run

later after it's installed, switch to AMD SPI TPM , to gain back cache performance
Oh also 4G mode must be on & secure boot too


----------



## Takla

oobymach said:


> Actually it should work for any ram type, tRTP goes up to 14 and it works even on my crap hynix MJR chips, it just runs a lot lower on b-dies.
> 
> In my hynix 32gb kit tRC 57 x tRTP 12 = tRFC 684
> 
> View attachment 2514550


What I meant with "not applicable" is, you cannot run, for example, trfc=480 even though trc=60 & trtp=8 works just fine. But you also shouldn't run 10*60 since 300ns is doable with just about any micron e-die and so you'd leave performance on the table.


----------



## Veii

@XPEHOPE3
It's not as stable as you think








ue1LyBC1En.mp4


Watch "ue1LyBC1En.mp4" on Streamable.




streamable.com




But while load is applied, it stays that way ~ consistent 
The 102 spike you saw tho is the kernel and PSP Firmware issue that's currently under investigation ~ it overboosted slightly
Around the end on the recording


----------



## ManniX-ITA

Veii said:


> Figured that ManniX-ITA's powerplans break CPPC on 21H1 somehow


Really, how? 
I'm using them now on 21H1 and I didn't notice anything weird.


----------



## Sleepycat

XPEHOPE3 said:


> Well, I did disable both Spread Spectrum and SVM and got 64.5-67.4ns Aida variety in latency.
> And when both were enabled I only had 64.7-64.8 variety.
> Funny thing is *why* I had SVM enabled. It was required to run WSL 2.0 and Ubuntu inside it, so that I could run GSAT to stress test memory😂 I think GSAT is unsuitable for stressing max possible overclocks if run under WSL then, since with SVM BCLK clocks @98.8, and with only Spread Spectrum - 99.8.


I would leave SVM disabled, and spread spectrum on Auto.

But if you are more worried about your memory latency, I don't think it is caused by SVM. You have a Zentimings screenshot for this config that you are running (3200 CL14)? I thought you were running 3800 CL14 previously?


----------



## kim nk

I don't know what to do with all the chaos right now. First, I post a post and ask for your advice on this matter.

There is no whea error up to 4200 clocks. But it's a very sensitive cpu elsewhere. If "procodt" is not correct, the latency and bandwidth will be destroyed. Eventually, I found the proper range and finished the test, but I didn't touch the cpu Lunar New Year's Day at all, and it's as big as memory overclock.
Also, pbo max or pbo-enabled, setting causes read-write copy bandwidth and latency to decline. And based on some compromise, the city of Latency seems to be higher than the clock. How can I solve this problem...?











pbo -auto












max +200
















Normal latencies of 49 to 50... What settings should I turn off and turn on?
Increasing both the pbo-enable setting and the pbo-max results in a longer bandwidth portion and latency.


----------



## ManniX-ITA

Veii said:


> Figured that ManniX-ITA's powerplans break CPPC on 21H1 somehow


Maybe something else?
I've tested both with 21H1 Build 19043.1052 and CPPC works.
Meaning the threads are scheduled with the correct order on the cores in the priority list.
Let me know


----------



## domdtxdissar

Veii said:


> Also there is no "Turbo" powerplan


What is this then ?









The leaked build that "Tech YES City" tested (your video) is clearly older than the build in the video i posted according to "Ben Anonymous"

Timestamped video below 10min and 58 sec


----------



## PJVol

craxton said:


> i do know that i can alter my CO offset on the one positive core i have and itll lower power per-core to


In essence, this is close to what we want when tuning the curve. Look at this screen and take note of core VIDs









In this VID group (snapshot polling should be turned on), you can see which core mostly impact requested allcore VID.
I've marked this core red, and despite being 2nd best according to fused rating, its the ****tiest of all cores.
Thats because to reach showed frequency (4671Mhz) it need more voltage with CO -15 than Core4 (best) with CO -7. 
So I had to lower its offset as much as possible, up until it crashes in light loads.
Thats the goal - find its optimal offset.
Lowering other core's offset do nothing, since that ****ty core is the one, the boosting is rely upon.

Just setting it to -12 lower clocks by ~100Mhz and the score 75-100pts down. (from ~12150 to ~12060)


----------



## Veii

domdtxdissar said:


> What is this then ?
> View attachment 2514607
> 
> 
> The leaked build that "Tech YES City" tested (your video) is clearly older than the build in the video i posted according to "Ben Anonymous"
> 
> Timestamped video below 10min and 58 sec


Asus specific powerplans, i use it right infront of me
Aside some graphical glitches, this post sums it up








Introducing Windows 11:


I bet their goal with windows 11 will be to have an OS that runs well on mobile devices as well as normal PCs. They canceled windows 10X which was supposed to compete with chrome OS more directly and I suspect that's because they're building that kind of functionality into 11. 10 can run on arm...




www.overclock.net





If you have any specific questions, let me know so i can test
Aside from the glitches, it's quite performant
Posted the last message even a tutorial what you need to erase, to keep it performant and get optimize-offline to run

Powerplans do not dissapear out of nowhere
But ASUS injected DLLs do appear out of nowhere 
Like the ProArt had a "Creator" powerplan, so also does this ROG Zephyrus have own Notebook Powerplans
You confuse them with given powerplans
They have no connection whatsoever

Also once you install it with AMD fTPM mode, you don't need it running 
Yet thread scheduler, CPPC awareness and powerplans are broken.
Gaming Performance is not bad at all tho. I feel an improvement even on a GTX650


----------



## XPEHOPE3

Sleepycat said:


> I would leave SVM disabled, and spread spectrum on Auto.


That's what I did. I'd enable SVM back when I start using Virtual machines for work.


Sleepycat said:


> But if you are more worried about your memory latency, I don't think it is caused by SVM.


I'm worried about CPU FSB and hence resulting memory clock. As soon as I disable SVM, CPU FSB is back to 99.8 from 98.8.


Sleepycat said:


> I thought you were running 3800 CL14 previously?


stasio from Gigabyte dropped AGESA 1.2.0.3 beta BIOS, so I swapped to it and started from scratch (losing all saved BIOS profiles in the process, but my memory and my XLS serve me well yet), since I couldn't get 3800-14-15 stable whatever I did. So I figured I'd start better following advices like that:


Veii said:


> Y-cruncher you should run with XMP on stock , to finetune your procODT/VDDP/VDDG range / and to verify your sample is not defect by the factory
> Also to finetune your loadline droop
> (more droop is often better with Vermeer - except for CTR usage. Less switching freq is better for lower ripple, find the balance between loadline and "enough" switching frequency)
> 
> It is recommended to disable every little manufacture cheating ~ including every performance enchancers, enable PBO with the stock limits and scalar set to X1 (boardpartners love to use X2)
> Often it's easier to just change the scalar in AMD CBS - without touching PBO, because PBO will add more vcore.
> Soo be sure FCLK and the CPU is stable and extend your XMP profile a bit higher in frequency or lower in frequency (the good thing when you buy 4000+ kits)



My board doesn't have frequency switching settings
LLCs on most droop by default, left them there, although @Veii elsewhere recommended vSOC LLC just 1 setting more droop than flat. On XMP settings that doesn't change a thing (vSOC stays 0.994-0.988 on any vSOC LLC), so I'll experiment later
set PBO to disabled (that means it's on stock limits, at least that's what B550 Aorus Pro V2's BIOS help string said, and while testing I saw 4.650 freq, 90A EDC limit, and no overshoot in per-core voltage)
scalar in CBS set to 1x
So now I'm TM5-stable at 3600 with XMP settings with 1.45 VDIMM and 1.2 vSOC (n ot optimal, just set something which worked):









Temps are Ok with active cooling, given it's +30C outside 

Question is, *where to go from here*? In what order?)

Think I'm gonna run y-cruncher. How to tune LLC and vSOC LLC with it? 🙄 Or tune vSOC LLC with TM5? I never saw overshoots in vSOC anyway, so is it tuned enough already on largest-droop-LLC? Do I fiddle with VDDP/VDDG to attempt to crash y-cruncher so that later I know what shouldn't work? I see no way to measure those voltages while running (e.g. ZenTimings shows values which doesn't change even when monitoring is enabled) hence I see no way to measure LLC influence on them.
set FCLK to 1900 and run y-cruncher and TM5 again to isolate FCLK issues
is it worth to lower vSOC/VDIMM/procODT for 3600-14, if I'm going to try 3800-smth anyway? On XMP 3200 procODT was 53-ish, for example. And for 3800-14 I was able to use 40 (but between 40 and 48 won't train).
is it worth lowering secondary/tertiary timings before pushing 3800?
is it time to switch GDM off and go 2T? Or 1T? Never tried that


----------



## Veii

XPEHOPE3 said:


> is it worth lowering secondary/tertiary timings before pushing 3800?


no, i started with a 16-16-16 set


XPEHOPE3 said:


> is it time to switch GDM off and go 2T? Or 1T? Never tried that


Yes, going down to 2T can be a hard entry step, if you are used to low timings on GDM. No voltage change required, only RTT and CAD_BUS & maybe lower procODT


XPEHOPE3 said:


> is it worth to lower vSOC/VDIMM/procODT for 3600-14, if I'm going to try 3800-smth anyway? On XMP 3200 procODT was 53-ish, for example. And for 3800-14 I was able to use 40 (but between 40 and 48 won't train).


You likely will need to lower VDDG CCD and increase IOD after time. SOC is already plenty for 2000 FCLK. Around 1.1875-1.2125 is needed , often even less up to procODT


XPEHOPE3 said:


> How to tune LLC and vSOC LLC with it? 🙄 Or tune vSOC LLC with TM5?


Droopy. Y-Cruncher is mostly AVX2, you want to move on some tests near 1.18-1.2v, some like the first one can often need 1.35v upwards
Droopy & Variable is what you're looking for. Soo i start with it, before anything. 
Seen so far 4 out of 20 Vermeer CPUs which where defective on stock & needed an RMA . Online mentioned failure rate of 3% is starting to increase near the 5% mark and higher

TM5 you rather focus on negative CO values, as long as you are not hitting ProcHot or THM (both thermal throttle limits)
The ipc-load is weak enough to pass as an allcore-hold frequency test. Else BoostTester on CTR is alright to configure & finetune it on the next stage for AVX1 loads
It also will test CurveOptimizer values for you , if you don't want to deal with CoreCycler. (i haven't touched CoreCycler yet)



XPEHOPE3 said:


> Do I fiddle with VDDP/VDDG to attempt to crash y-cruncher so that later I know what shouldn't work?


They will run or crash y-cruncher & OCCT Extreme AVX2 
Use Aida64 as a baseline, till you see the point of catastrophic latency increase or can't hit perfect half of FCLK ~ write bandwidth (1 CCD units only)
They autobalance themself, no loadline or user influence exists. You only need to find the golden middle between CCD and IOD. IOD voltage influences CCD voltage and the opposite


----------



## Dasa

Managed to get 3771c14 stable and it only took 1.572V





Gigabyte Technology Co., Ltd. B550 AORUS PRO - Geekbench Browser


Benchmark results for a Gigabyte Technology Co., Ltd. B550 AORUS PRO with an AMD Ryzen 7 5800X processor.



browser.geekbench.com


----------



## Veii

XPEHOPE3 said:


> In what order?



GDM off first, TM5 stable / later aida64 baseline screenshot
1900FCLK post, checking Aida64 run if it's better than the early screenshot. Adjust VDDG and procODT till it's better / then TM5 stable + y-cruncher afterwards
lower SOC , set 1.8v rail to 1.83v or 1.85v (better 1.83v) and lower SOC + VDDG till you hold the 40mV stepping (can be double 40mV) / that you test y-cruncher stable but first see if you improve in Aida64 (memory latency or write bandwidth loss is unforgiving & a sign of autocorrection)
at the end you finalize verify with OCCT Extreme AVX2 (runs 1h) ~ if it freezes, you can start over = adjust VDDG, adjust SOC, aida64 score verify, y-cruncher stability verify & again OCCT Extreme finalize

After all that is done
You move to 2000 FCLK
Same test pattern, but run ManniX-ITA's WHEA supressor , if you encounter WHEA #19. WHEA #18 are voltage related, which you have to fix first by hand
* 4000CL14-14 will need around 1.65-1.7v, you won't be able to run this, soo better find a good CL16-16 baseline 
** 4000C15-15 is hard too, but in the doable range of 1.52-1.55v , still would recommend learning RTTs on an easier to run set ~ might be able to find some on my posting history (as pictures)
or even easier, find/take some from here Zen RAM Overclocking


----------



## ManniX-ITA

@Veii 

Do you mean the % Processor Performance never going below 100 in Performance Monitor?

If that's the case don't trust the counters; they are bogus.
Don't know how's doing worse if Microsoft or AMD... 21H1 is a new low on this regard.

Check the CPU Core Power (SVI2 TFN) minimum value in HWInfo.
Let the LowPower v8 plan run for a few minutes idling and compare it with Balanced which keeps the % at 105.

Also compare it with LowPower v8 with min processor state at 1% and allow throttle states On.
The clocks goes down to 1.2GHz and the % drops to a minimum of 19 on my 5950x.

They both raise the minimum core power to 45W instead of 37W and a higher CPU Tctl/Tdie temperature.
Plus the system is much more sluggish.

At the end despite what the Performance Monitor says it's better in every aspect; performance and power consumption/temperature.

The High Performance v5 is even better with 34W and 1c degree less in CPU temperature.
And it's blazing fast. But there are more temperature spikes on load compared to LowPower.


----------



## Veii

ManniX-ITA said:


> @Veii
> 
> Do you mean the % Processor Performance never going below 100 in Performance Monitor?
> 
> If that's the case don't trust the counters; they are bogus.
> Don't know how's doing worse if Microsoft or AMD... 21H1 is a new low on this regard.
> 
> Check the CPU Core Power (SVI2 TFN) minimum value in HWInfo.
> Let the LowPower v8 plan run for a few minutes idling and compare it with Balanced which keeps the % at 105.
> 
> Also compare it with LowPower v8 with min processor state at 1% and allow throttle states On.
> The clocks goes down to 1.2GHz and the % drops to a minimum of 19 on my 5950x.
> 
> They both raise the minimum core power to 45W instead of 37W and a higher CPU Tctl/Tdie temperature.
> Plus the system is much more sluggish.
> 
> At the end despite what the Performance Monitor says it's better in every aspect; performance and power consumption/temperature.
> 
> The High Performance v5 is even better with 34W and 1c degree less in CPU temperature.
> And it's blazing fast. But there are more temperature spikes on load compared to LowPower.


mmm~
Nono it's been a combination of bugs from 21H1 onwards which broke CPPC flags, by working against the overboost
By setting any peak frequency limiters on it - breaks CPPC tags

I didn't have this earlier on 20H2 , 21H1 just noticed it with this 1202 AGESA and forward
It was not your powerplan specific but all of them and the AMD ones break it
You are right that 21H1 is buggy, but honestly that's the recent updates.
It even broke login once for me, requesting a specified app to log-in , which didn't exist, soo login was not possible at all after an update

Since people got that temp sensor on their task bar, performance gets worse and worse
https://mab.to/xM9hW6oIV
This link will expire in 2 days, soo nobody can blame me for it. It's not activated either, just pre-made modified with open-source tools
BCD bootloader is different - either you install it ontop and trust in Microsoft for updating it consistently + nvidia fixing the random desktop flickering mess
Or you pick another drive (be sure to unplug your windows OS one first - else the bootloader will jump drives)
Overall gaming perf is on point, good for a 2 system gamingOS ~ you just need to find a cheap Win 10 ProWS key
Speaking of key, this is the installation one which is accepted DXG7C-N36C4-C4HTG-X4T3X-2YV77 (Public information, again no piracy)
You usually have 48h till it pushes itself into demo mode with that installation key

Happy testing


----------



## Audioboxer

Hi guys, picked up a 5950x recently, noticed it could boot 1900FCLK stable whereas my 3900xt couldn't do above 1866 and I decided to pickup some B-die due to my Micron E-die not being binned all that great and needing quite loose timings at 3733.

Here is where I am at with the B-die










Doesn't seem to be a golden set of RAM as I was struggling to do 3800C14. Tried up to 1.5v but could only get it posting, not booting into Windows without crashes.

Then thought about trying to get GDM off and 3800CL15, but that's proving hard as well. GDM off at 3800 isn't posting at all, stuck in bootloops. It posts on slower speeds with GDM off.

Finally, wondered about 3800+C16, as in, FCLK 1933/1966/2000. All of them boot, but getting some WHEA errors. A fair number on 2000, far less on 1933. So, I think I can maybe get 1933~1966 stable and try and pump the memory speed a bit more on C16.

What would you guys aim for next?


----------



## Mach3.2

XPEHOPE3 said:


> Can anyone please explain why would CPU FSB (BCLK) be reported lower than 100MHz, as in screenshot?
> View attachment 2514534


Did you turn on VBS? Specifically HVCI.

If you did, try turning off AMD SVM and see if the BCLK reports as 100MHz.

I suspect it's some form of telemetry reporting bug when you have VBS turned on that resulted in lower BCLK being reported. I haven't tested if there's actually any performance regression.


----------



## Sleepycat

XPEHOPE3 said:


> That's what I did. I'd enable SVM back when I start using Virtual machines for work.
> I'm worried about CPU FSB and hence resulting memory clock. As soon as I disable SVM, CPU FSB is back to 99.8 from 98.8.
> stasio from Gigabyte dropped AGESA 1.2.0.3 beta BIOS, so I swapped to it and started from scratch (losing all saved BIOS profiles in the process, but my memory and my XLS serve me well yet), since I couldn't get 3800-14-15 stable whatever I did. So I figured I'd start better following advices like that:
> 
> 
> My board doesn't have frequency switching settings
> LLCs on most droop by default, left them there, although @Veii elsewhere recommended vSOC LLC just 1 setting more droop than flat. On XMP settings that doesn't change a thing (vSOC stays 0.994-0.988 on any vSOC LLC), so I'll experiment later
> set PBO to disabled (that means it's on stock limits, at least that's what B550 Aorus Pro V2's BIOS help string said, and while testing I saw 4.650 freq, 90A EDC limit, and no overshoot in per-core voltage)
> scalar in CBS set to 1x
> So now I'm TM5-stable at 3600 with XMP settings with 1.45 VDIMM and 1.2 vSOC (n ot optimal, just set something which worked):
> View attachment 2514606
> 
> 
> Temps are Ok with active cooling, given it's +30C outside
> 
> Question is, *where to go from here*? In what order?)
> 
> Think I'm gonna run y-cruncher. How to tune LLC and vSOC LLC with it? 🙄 Or tune vSOC LLC with TM5? I never saw overshoots in vSOC anyway, so is it tuned enough already on largest-droop-LLC? Do I fiddle with VDDP/VDDG to attempt to crash y-cruncher so that later I know what shouldn't work? I see no way to measure those voltages while running (e.g. ZenTimings shows values which doesn't change even when monitoring is enabled) hence I see no way to measure LLC influence on them.
> set FCLK to 1900 and run y-cruncher and TM5 again to isolate FCLK issues
> is it worth to lower vSOC/VDIMM/procODT for 3600-14, if I'm going to try 3800-smth anyway? On XMP 3200 procODT was 53-ish, for example. And for 3800-14 I was able to use 40 (but between 40 and 48 won't train).
> is it worth lowering secondary/tertiary timings before pushing 3800?
> is it time to switch GDM off and go 2T? Or 1T? Never tried that


I'd push for 3800 first, but if the bios is holding your system back, then go for tighter subtimings. What you learnt previously with vSOC, VDIMM and procODT still apply, but I think the settings/values have shifted, and the old settings we used successfully now give us stability or POST issues. However, the pattern remains the same, we just need to find the new baseline.

I run a similar 4x16GB kit to yours @ 1.46V and you can certainly push for tighter subtimings if you want. I don't tune for LLC or vSOC LLC, but instead look for errors which appear with heavy loads but not light loads, and compare the voltages between the two. If the difference is great and is causing errors, then I increase either voltage or LLC (similar approach for CPU and SOC. My CPU is on LLC 3, and vSOC on LLC 2. I do have an issue where I can't POST at 3666 with VSOC at 1.25V and VDIMM at 1.55V even with the older bios versions, so I've left it to 3600 and instead went for tighter subtimings.


----------



## XPEHOPE3

Veii said:


> or even easier, find/take some from here Zen RAM Overclocking


WOW, what a list! You always have such amazing information! Thank you! Strange I haven't seen this list posted here previously.
What I noticed is that the best 4*16Gb is at only 90-th row and it's only 3600MHz. If Aida64 latency isn't that dependent on CPU, it's pretty beatable 💪😈
With this in mind do you really believe setups quoted below would be attainable? I was aiming at 3800-15 at best. Also I have 3200CL14 binned B-die, not 3600-16, as *u/derickso*


Veii said:


> 4000CL14-14 will need around 1.65-1.7v, you won't be able to run this, soo better find a good CL16-16 baseline
> ** 4000C15-15 is hard too, but in the doable range of 1.52-1.55v





Veii said:


> GDM off first, TM5 stable / later aida64 baseline screenshot
> 1900FCLK post, checking Aida64 run if it's better than the early screenshot. Adjust VDDG and procODT till it's better / then TM5 stable + y-cruncher afterwards
> lower SOC , set 1.8v rail to 1.83v or 1.85v (better 1.83v) and lower SOC + VDDG till you hold the 40mV stepping (can be double 40mV) / that you test y-cruncher stable but first see if you improve in Aida64 (memory latency or write bandwidth loss is unforgiving & a sign of autocorrection)
> at the end you finalize verify with OCCT Extreme AVX2 (runs 1h) ~ if it freezes, you can start over = adjust VDDG, adjust SOC, aida64 score verify, y-cruncher stability verify & again OCCT Extreme finalize


Great, thank you!
As you posted above, vCore LLC setup should be before those. But what about vSOC LLC? Also VDD*P *(I think pick 0.9v and forget)? And 2T->1T (I guess only at the very end)?
And main question: when to setup CPU overclock? After I stabilize best RAM setup on stock limits? And then treat all errors as CPU errors, not RAM errors? I would aim for Curve Optimizer, not CTR, I think.


Veii said:


> Droopy. Y-Cruncher is mostly AVX2, you want to move on some tests near 1.18-1.2v, some like the first one can often need 1.35v upwards
> Droopy & Variable is what you're looking for. Soo i start with it, before anything.


Just to reword it, I think you propose to pick vCore LLC in such a way that test1 receives 1.35v vCore or per-core (@ 5600X, on stock limits), and some other tests fall into 1.18-1.20v ballpark.

Regarding "_1.8v rail to 1.83v or 1.85v (better 1.83v)_": I have two "1.8 rails": CPU VDD18 and A_VDD18SS. Both show as 1.800 in BIOS although I've set one of them to 1.820 (and it could only be set in 0.02v increments, the other one can only be set in 0.04v: 1.800 then 1.840). In HWInfo I only see CPU_VDD18 (rock stable at 1.815) and VIN0 (1.804-1.815), and those volts didn't change at all when I changed that volt in BIOS.
I saw your 1.83v advice previously but never saw mentions of what issues it prevents and how. Probably was explained long ago...



Mach3.2 said:


> Did you turn on VBS?


I didn't, at least voluntarily. But disabling SVM, as I previously wrote, helped to reduce BCLK drop.

@Sleepycat 
Interesting how you have those RTTs/procODT. procODT 40 and 48 worked for me for 3800, but 43 won't post. RTT 7/3/1 were stuck in place, only once I booted into 6/3/1, but Aida gained 1ns of latency. 6/3/2, 7/3/2, 7/3/3, 6/3/3 won't post with procODT 48, and some I tested with 40 either. I was pushing 1.52-1.55 VDIMM though. Will see what happens now with a more gradual approach and GDM off.


----------



## craxton

PJVol said:


> In essence, this is close to what we want when tuning the curve. Look at this screen and take note of core VIDs
> 
> View attachment 2514602
> 
> 
> In this VID group (snapshot polling should be turned on), you can see which core mostly impact requested allcore VID.
> I've marked this core red, and despite being 2nd best according to fused rating, its the ****tiest of all cores.
> Thats because to reach showed frequency (4671Mhz) it need more voltage with CO -15 than Core4 (best) with CO -7.
> So I had to lower its offset as much as possible, up until it crashes in light loads.
> Thats the goal - find its optimal offset.
> Lowering other core's offset do nothing, since that ****ty core is the one, the boosting is rely upon.
> 
> Just setting it to -12 lower clocks by ~100Mhz and the score 75-100pts down. (from ~12150 to ~12060)


Granted all things i tried (getting near your PPT, EDC, and TDC limits.
i could not get boosting over 4.5xx anything at all.

however, leaving what i have (what i know my chip needs to run X frequency at max boost)
i can however get what i believe your meaning we should want out of VID per core.
mine is however quite a bit lower than your cores tho, (as of last night figured out i can run a -15 all cores without fail?
no offset this time around with DF-Cstates turned off.

none the less,







core 4 is my "worst" core period, not just what the "fused algo states" it actually is the worst core. 
but still runs up-to -17 CO without issue. (turning of DF-state however, it doesnt.)


----------



## Insidious Supra

Audioboxer said:


> What would you guys aim for next?


Honestly wherever is stable. I can't personally see a reason to run above 3800. I've run up to 3933, and while stable, performance was not as consistent. Higher peaks, lower lows. Same went for even 3866

I think I'd dial in your power and resistances first, then run back over your primaries, and work across the rest of the timings. 

Here's where I'm at with my 4x8gb 4400 cl19 bdie. Passed all stress tests, but for whatever reason would not run ghost recon without bumping vdimm to 1.53 from 1.52. (tried adjusting several other things prior)


----------



## Audioboxer

Insidious Supra said:


> Honestly wherever is stable. I can't personally see a reason to run abover 3800. I've run up to 3933, and while stable, performance was not as consistent. Higher peaks, lower lows. Same went for even 3866
> 
> I think I'd dial in your power and resistances first, then run back over your primaries, and work across the rest of the timings.
> 
> Here's where I'm at with my 4x8gb 4400 cl19 bdie. Passed all stress tests, but for whatever reason would not run ghost recon without bumping vdimm to 1.53 from 1.52. (tried adjusting several other things prior)
> 
> View attachment 2514639


Good advice, I think the hassle of trying to go stable at 1933/1966 probably won't be worth it. 1900 just.. works, and there is no WHEA errors.

I might try for 3800C14 again, but I was struggling at 1.5v. Guessing it might need more and I don't have any active cooling on the RAM other than case airflow.


----------



## Insidious Supra

Audioboxer said:


> Good advice, I think the hassle of trying to go stable at 1933/1966 probably won't be worth it. 1900 just.. works, and there is no WHEA errors.
> 
> I might try for 3800C14 again, but I was struggling at 1.5v. Guessing it might need more and I don't have any active cooling on the RAM other than case airflow.


For increasing voltage, I'd just keep an eye on the temp. I use an IR temp gun to measure on die and back side temps. (bdie has onboard temp sensors too) I feel like on bdie anything under 40C should be stable... but you never know.

People were saying higher resistances would equate to higher temps, which makes sense.... I'm running higher resistances than I see most. But my temps just don't reflect it. I've tried dialing resistance back for on die termination, and cad bus, but cant get mine any lower.

I'm also using 4 sticks where I think most people are using 2. And my board has t-topology where most am4 boards are daisy chain. Meaning my board fares batter with 4 sticks. But not as well as a daisy chain board would fare OC-wise with 2 sticks. I'm sure this plays into how my settings have come about, and why they are a bit different.

I do use active cooling. Consisting of a g.skill fan frame, and gelid 50mm fans. I'm pretty sure I don't need it, but figure why not. I used to actually NEED it for my hynix 4x8gb cl16 3600 kit (ran at 3933 cl16) but had set at 3800, if I got over 35C it would get unstable. From what I've learned with various power and resistance settings tuning my 4400 dimms, I could probably get more stability from my hynix sticks now.


----------



## Dasa

Insidious Supra said:


> Here's where I'm at with my 4x8gb 4400 cl19 bdie. Passed all stress tests, but for whatever reason would not run ghost recon without bumping vdimm to 1.53 from 1.52. (tried adjusting several other things prior)
> 
> View attachment 2514639


And here was me thinking 1T would be impossible with 4xA2 on this board but AddrCmdSetup 48 was the secret ingredient and you DrvStr settings were also needed along with higher ProcODT but for my sticks even more VDIMM is needed.
Still need to dial some things in but until I do I am left wondering if the performance will be better or worse.


----------



## Insidious Supra

@Dasa That's good to hear. And I'd be curious to know if performance does indeed improve. 

It does seem the gigabyte board I use (and apparently you use) requires some different inputs from the asus boards people tend to run. For instance, my cpu operates at pretty low voltage, while my vcore is a bit higher than I see a lot of people use, same for vdimm, and resistances

How did you get your latency so low? I'm running a fully bloated windows install, lol. Any attempt of gutting my OS resulted in botching my microsoft store and also xbox login. Mine tends to hover around 55.5 at best.


----------



## Dasa

If I launch windows in diagnostic mode, disable defender and end task explorer it can get down to 52.7ns at those settings.
If I don't close a heap of processes it ranges from ~53-56ns at the same settings.

Best I have managed although very unstable was 50.9ns but that was probably with 2x8GB A1 at ~4100 when it starts to see WHEA errors at 3800.


----------



## Nighthog

I will be getting a new kit of memory later this week to test out.

Bought some Crucial Ballistix Max 4400 CL19-19-19, for a 4x8GB total. Will replace the older kits with these better binned ones. 
I mess around with OC so much even with the same old kits I have was time to get something better.

They have a reasonable price at the moment, lower than msrp.


----------



## Taraquin

Drevi said:


> 11950-11970. I have a CLC280, runs CB23 at 80°.


At -30 CO +50MHz pbo I get 11660-11690. Amd stock limits. Allcore in CB23 lies at 4550-4580MHz with current settings. 72C temp. Not sure if cooler can handle 12000+ score


----------



## Art385

Dasa said:


> And here was me thinking 1T would be impossible with 4xA2 on this board but AddrCmdSetup 48 was the secret ingredient and you DrvStr settings were also needed along with higher ProcODT but for my sticks even more VDIMM is needed.
> Still need to dial some things in but until I do I am left wondering if the performance will be better or worse.


use 56-0-0 CAD timings for 4x8GB A2 it works pretty great in games and perform quite nice in AIDA bench


----------



## Veii

XPEHOPE3 said:


> WOW, what a list! You always have such amazing information! Thank you! Strange I haven't seen this list posted here previously.


It's a public reddit list, which just grew in popularity recently
We had an own OCN maintained one, but it rather faded away ~ alone by the bigger popularity of this thing


XPEHOPE3 said:


> But what about vSOC LLC? Also VDD*P *(I think pick 0.9v and forget)?


SOC LLC should always be one under flat, to prevent overshooting ~ but it needs special attention for it's switching freq.
What i do, is push more SOC , a more droopy loadline with low switching freq (maintaining lower noise)
Overall focus on "GET" SOC , which is important for the 40mV stepping rule


XPEHOPE3 said:


> Just to reword it, I think you propose to pick vCore LLC in such a way that test1 receives 1.35v vCore or per-core (@ 5600X, on stock limits), and some other tests fall into 1.18-1.20v ballpark.


Not always,
Going from FIT settings, and adjusting near that range
Just noticed and note down my sample behavior without PBO what FIT allows and what not.
After all AVX = Loadline Droop, AVX2 = Loadline droop + fixed voltage droop + fixed frequency drop

Soo some tests there require 1.18v , some can boost up to 1.35 and higher
Meaning, running a fixed allcore, nearly always will make you a bad time with y-cruncher. Even CTR was problematic before the recent RC06 update with boost scaling

Which again means, you want a loadline droop, to have a bigger scale between voltage/frequency
As it will very fast crash on "too much" voltage - or even if you are on OC_MODE , degrade the unit faster.
~ Just as a note



XPEHOPE3 said:


> Regarding "_1.8v rail to 1.83v or 1.85v (better 1.83v)_": I have two "1.8 rails": CPU VDD18 and A_VDD18SS. Both show as 1.800 in BIOS although I've set one of them to 1.820 (and it could only be set in 0.02v increments, the other one can only be set in 0.04v: 1.800 then 1.840). In HWInfo I only see CPU_VDD18 (rock stable at 1.815) and VIN0 (1.804-1.815), and those volts didn't change at all when I changed that volt in BIOS.
> I saw your 1.83v advice previously but never saw mentions of what issues it prevents and how. Probably was explained long ago...


Everything still applies
CPU_VDD 1.8 rail, never seen that A_VDD reail
1.8-1.85, usually more causes crashes
But only causes crashes if SOC is tight
If SOC is high and unused, you can push this up to 1.9 sometimes 2.0v to improve latency scaling
But this is mostly going around a problem
Soo 1.83v or lower, 1.8v can work

cLDO_VDDP seems to stay at 900mV across all the samples i tested
Even is fine on Matisse
but it seems to function also bellow 900mV
"Friends" of mine got it down to 820mV and lower
lower VDDP seems to lower procODT requirements

But i haven't find time to make another testing session for voltages. Current goal is still to improve and finish these Ballistix MAX ~ which are beyond annoying 
At the same time playing with v21996 Windows
* apparently this "leak" turned into a public jebait "again" and it should release in 4 days ?!
** did expect it, considering they "update" a leaked windows ~ pretty much using us again as testing rabbits
*** well yes, the above share then is even more white than gray now. considering it "releases" in 3-4 days. But keep in mind BCD bootloader is different now

Considering, to what i see ~ L3 cache is messed up & the MSI issues publishing a "fake" 1.2.0.3A AGESA and not 1.2.0.3B 
(also the time long silence from boardpartners about 1.2.0.3B)

I do think, there are issues with virtualisation kernels and passthrough SVM based functionality 
Soo i strongly expect a microcode update with 1.2.0.3B ~ when it finally releases


----------



## adversary

@Veii 

what is exactly about 40mV stepping? is it relative to average of CCD & IOD, or just IOD?

I did tune my RAM long ago already, for what I did read about 75mV you write in past. it works nicely regarding performance and stability.


for 1.8V rail, I remember I did try to increase it, but it resulted in slightly worse latency, did not bother afterwards with it, returned to Auto.

I may attempt to do complete new tuning again, but still did not decide, as current settings are super fine for me, and I don't know is it worth to upgrade BIOS still.

on 1.2.0.1 Patch A at moment, SMU 56.50.0

exactly today I did read on mobile when I wake up, news for MSI 1.2.0.3 Patch B

and also did refresh page for my BIOS moments ago (I have Asus board), now 1.2.0.3 Patch A is not longer Beta, and 1.2.0.2 is removed (it was all time in Beta)

I'm trying to understand what you say about 1.2.0.3. as for me it is not urgent, all works fine now, is it worth to upgrade now to 1.2.0.3 Patch A or maybe leave it for some time till newer one?


----------



## Veii

adversary said:


> @Veii
> 
> what is exactly about 40mV stepping? is it relative to average of CCD & IOD, or just IOD?


It's this thread








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net





AMD's early stepping for Matisse (thanks The Stilt) was 50mV , at least enforced 50mV stepping








Strictly technical: Matisse (Not really)


07/08/2019 6:33 PM (GMT) - Update on the bios issue on Crosshair VIII Hero motherboard ("the thing"). Earlier today I received a response to my inquiries from ASUS. The response was rather technical and I cannot go into the specifics of what exactly it involved. However, it confirmed my...




www.overclock.net




But 50 and 75mV worked well
OC'ing T-Force 4133 cl18 (bottom half of the thread)

This generation (Vermeer) it's 40mV as minimum stepping between all of the 3 & 1 higher procODT than Matisse
Only one exception exists, which is that VDDG CCD can be equal to cLDO_VDDP , but it often might be better 40 or 80mV over it 


adversary said:


> I'm trying to understand what you say about 1.2.0.3. as for me it is not urgent, all works fine now, is it worth to upgrade now to 1.2.0.3 Patch A or maybe leave it for some time till newer one?


this post sums it up, with the relinked reddit in the quote
MSI B550 Unify / Unify-X Overclocking & Discussions... credits to weleh
The comments of reddit sum it up
AMD starts to enforce removal of 1200, 1181/1191 and 1201
while these bioses where one of the few without usb dropouts
And yet nearly no one has 1203B out , only 1203A , which did nothing against usb droupouts


----------



## XPEHOPE3

Veii said:


> CPU_VDD 1.8 rail, never seen that A_VDD reail
> 1.8-1.85, usually more causes crashes
> But only causes crashes if SOC is tight
> If SOC is high and unused, you can push this up to 1.9 sometimes 2.0v to improve latency scaling
> But this is mostly going around a problem
> Soo 1.83v or lower, 1.8v can work


So I went to BIOS:
A_VDD18S5 rail can be set in 0.02mV increments (and setting that to 1.82 did nothing)
CPU_VDD -- in 0.04 increments. So I think I'd better stick with 1.8v CPU_VDD to avoid spending too much time.


Veii said:


> Going from FIT settings, and adjusting near that range
> Just noticed and note down my sample behavior without PBO what FIT allows and what not.
> After all AVX = Loadline Droop, AVX2 = Loadline droop + fixed voltage droop + fixed frequency drop
> 
> Soo some tests there require 1.18v , some can boost up to 1.35 and higher


So I've tested some vCore LLCs (with vSOC LLC on Auto meaning furthest from flat). Auto, Normal, Standard are all equal according to graph shown in BIOS. Next is "Low".
y-cruncher tests 1-4 present uniform load while 5-9 have spikes and lows in both vCore and SOC current, so it's unclear what to measure. So I had to measure both at peaks and lows 
Also I took measurements on 4-th iteration (and they were equal to measurements on 2nd iteration, but not on 1st iteration).
I came up with a table (omitting 5-9 tests and 1-3 iterations):


llc autovcore first spikevcore holdbest core Vworst core VvSoc currentvcore diffbest core diffworst core diffvSOC current difftest 1 (integer)1,392​1,248​1,167​1,194​10,283​test 2 (avx2 float)1,08​1,08​1,027​1,032​10,308​test 3 (avx2 float)1,356​1,068​1,022​1,026​10,45​test 4 (FFT, avx2 float)1,332​1,332​1,216​1,251​13,85​llc lowtest 11,248​1,248​1,156​1,182​10,45​0​-0,011​-0,012​0,167​test 21,08​1,08​1,019​1,023​10,44​0​-0,008​-0,009​0,132​test 31,2​1,08​1,017​1,022​10,6​0,012​-0,005​-0,004​0,15​test 41,344​1,218​1,253​14,1​0,012​0,002​0,002​0,25​

So what interests me:

Droop happens not on every test. Happened on 3,4,5,8 tests. For 5 and 8 tests -- LLC made peaks higher (by 0,12*3 and 0,12*9 respectively) and lows deeper (by -0,024 and -0,012)
1,08 for 2nd and 3rd tests is quite far away from 1,18. So it's unlikely I can use those numbers blindly. I'd say my FIT (whatever that is) just doesn't allow as much. I'm not even sure I will crash with volts that low.
vSOC current also changes showing I guess that memory "eats" from the same powerbudget as CPU.


----------



## T[]RK

Veii said:


> * I publish it, because the lack of bios options from MSI and Gigabyte (closed down AMD CBS) starts to get annoying


Hm... my last BIOS (F61c) have got DF Cstate switch, but when i disable it and run ZenState after reboot - Package C6 state still got that check box active. I even disabled CTR autorun, but C6 state is active anyway after reboot.

Also, i notice that if i disable DF Cstates in BIOS i got 1000 MB\s lower result in AIDA64 (Read) and higher latency. BUT, since C6 state still active, then maybe that's why there is problem.

Is it BIOS bug? Checkbox in ZenState do anything with DF Cstates?


----------



## Dasa

Insidious Supra said:


> That's good to hear. And I'd be curious to know if performance does indeed improve.





Art385 said:


> use 56-0-0 CAD timings for 4x8GB A2 it works pretty great in games and perform quite nice in AIDA bench


56-0-0 allowed me to drop ProcODT & DrvStr back down and just helped stability in general even more than 46 and also seems to have helped my WHEA errors at 3800.
Any performance hit seems to be worth it as I am now getting the best Geekbench and TimeSpy benchmarks with AddrCmdSetup 56 and the tighter timings it allows.
Still fine tuning and may have to give up on tRCD15 for stability reasons but this is where it is at now with the 5800X at stock.










GB5 Multi-Core Score 12052
TimeSpy CPU Score 13390

Edit: Oops looks like I missed changing tRC to 44 in that image.


----------



## clackersx

Hey,
Could someone please check my timings to make sure I haven't set something stupid or incorrect? 
Seems stable with 50 TM5 cycles and over 40000% in Karhu.

I am happy with the performance as is. Don't want to push any more vdimm.

5950X Asus Dark Hero
F4-4000C16D-32GTZNA
1.45VDIMM
1.025V SOC
.950 IOD
.900 CCD
.900 VDDP

ProcODT, RttNom, RttWr, RttPark, all DrvStr and setup on auto in bios.
all CPU settings and VRM/power settings on auto in bios.


----------



## Dasa

clackersx said:


> Could someone please check my timings to make sure I haven't set something stupid or incorrect?


I think tWR should be 12 (tRTP x2) and tWRRD x4 should equal less than tRCD## average so 3 for anyhting under tRCD16 16.
Maybe tRDRD## 5, tWRWR## 7.
You could probably lower DIMM temps with RttNom 6, Wr 3, Park 3 and lower ProcODT even if it equiers a notch more VDIMM.

I don't fully understand all this just repeating what others have said and I could be wrong


----------



## Veii

clackersx said:


> Hey,
> Could someone please check my timings to make sure I haven't set something stupid or incorrect?
> Seems stable with 50 TM5 cycles and over 40000% in Karhu.
> 
> I am happy with the performance as is. Don't want to push any more vdimm.
> 
> 5950X Asus Dark Hero
> F4-4000C16D-32GTZNA
> 1.45VDIMM
> 1.025V SOC
> .950 IOD
> .900 CCD
> .900 VDDP
> 
> ProcODT, RttNom, RttWr, RttPark, all DrvStr and setup on auto in bios.
> all CPU settings and VRM/power settings on auto in bios.
> 
> View attachment 2514779
> 
> 
> View attachment 2514780
> View attachment 2514781


More ClkDrvStr , less AddrCmdDrvStr
30-20-30-20, or 40-20-40-20

tRRD 4-4 and tWTR 4-8 might look tight
But takes away your potential ability to ever get 3800C14-14-14 stable
Else they are fine
try this set








Else you want
















Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com


----------



## craxton

keep seeing mention of USB dropout issues, (im not near that limit)
havent been for sometime now. have been jumping up and down with SOC tho for testing to
see how much less voltage i get "per core" but nothing ive noticed.

reguardless however, running 1.2.0.2 still and the only thing i can complain about is my "best" core
being my ****tiest core in my entire system. while all others hold near -10 or near -20 this "best" core needs a minimum of +8
to hold the 4850mhz auto 200mhz boost.

is there a way i can zip the bios i have now and send it to someone who knows what theyre looking at?
i know the next B550 gaming edge board might be the same bios flashed, but "maybe" this board does something "STRANGE"
to which doesnt give WHEA 19s, or USB-dropout issues PERIOD?
ive brought this up several times but not in a manner of such a way that shows what "auto" or "default" does upon boot.


----------



## Dasa

craxton said:


> the only thing i can complain about is my "best" core
> being my ****tiest core in my entire system. while all others hold near -10 or near -20 this "best" core needs a minimum of +8
> to hold the 4850mhz auto 200mhz boost.


Check Snapshot CPU polling in HWiNFO64 and see what the actual V is for each core it may be that your best core has a very low V by default and adding +8 just brings it up in line with the others?


----------



## CarnageBT

mongoled said:


> I decided to return to my one bad stick and see if I can get flat 14s running on it, then comparing the performance to 14-15-14-14


After fighting with my setup for days, getting the odd 25 cycles to pass, then failing later with the same settings, using a huge fan blowing directly in my open case (keeps max dimm temps down about 4 degrees to 44.5), I've given up as well. but am not done "chasing the white rabbit"

Based your your experience, we ruled that I have 1 stick that isn't as good as the others, great call.

I've re-ordered another set of my ram. As long as 1 of the 2 sticks is good, then I will swap it in with my other 3 and hopefully, finally, I will consistently pass the 25 cycles of TM5.

TLDR. I ordered another set of my ram to swap out against my 1 bad stick. Wish me luck. Fingers crossed

What is the best way to benchmark individual sticks to find the best ones? Based on lowest passable timings?


----------



## craxton

Dasa said:


> Check Snapshot CPU polling in HWiNFO64 and see what the actual V is for each core it may be that your best core has a very low V by default and adding +8 just brings it up in line with the others?


if only that was actually the case...
needs way more than the others to run X frequency.


----------



## craxton

CarnageBT said:


> I've re-ordered another set of my ram. As long as 1 of the 2 sticks is good, then I will swap it in with my other 3 and hopefully, finally, I will consistently pass the 25 cycles of TM5.


good luck with that, as i ordered two sticks (2x8) tforce dark pro from amazon lets say oct 2020,
then ordered another 2x8 set from newegg (exact SAME KIT)
in jan 2021, the part number, model number, literally EVERYTHING is the EXACT SAME but
well, here take a look at what they "secretly change" similar to what adata did with the 8200sx pro not to long ago (yes LTT released a vid today)
but lucky enough i already knew this and got one of there best released versions. anyhow,

Notice that TRC, TFAW, TRRD_S, and TRRD_L are different from each other.
two sticks match the top, two sticks match the bottom. just be aware.... (only thing i noticed hard was manufacture date
the better set was made earlier on, vs the "lesser" set being made later i.e. newer)

(edit) i was able however, to get all four sticks to run the same timings, and be 100% stable for me, at 4000mhz 2000fclk without WHEA 19)
so, take this info as you wish. im unsure if that change was made for AMD or, they had issues with keeping the timings that tight? dunno...
(NO) these kits are NOT labeled as AMD ready sticks. on the board i use, only states that 2x8 works at 3200mhz XMP profile) 

*FIRST SET*
















*SECOND SET














*


----------



## Drevi

mongoled said:


> Thats running CB23 at priority "Realtime" ??
> 
> If the above run is "Realtime" can you do another run but with normal priority with HWInfo64 open and note what all core frequency is ?
> 
> I would have expected your score to be higher, but it looks like you are thermal limited.
> 
> See below pic from my setup of CB23 where CPU temp is at 73-74C while frequency is at 4660 mhz
> 
> View attachment 2514503
> 
> 
> I wonder if I can somehow simulate an 80C CB23 run to see how much frequency drops by.
> 
> My estimate of being close to 123xx for your CPU is based on CB23 not exceeding 75C.
> 
> 
> Ugghhhh, ughhhhhh and ughhhhhh
> 
> "DF-C States" was/is set to disabled in the BIOS
> 
> 
> 
> And ive just ran the tool you kindly shared and look whats its showing and yes, its set to disabled in BIOS, no wonder I cant get consistent results when attempting to tweak PBO with telemetry, no consistency across reboots ......
> 
> View attachment 2514504
> 
> 
> 
> Yes toooooooo many, I am on Eder modifed A.A1 BIOS that uses agesa 1.2.3.0a, maybe I am going to have to do a flash with a different utility than the default MSI flash tool .........


Yes, it was realtime. This is what a normal run looks like (finished at 11919):


----------



## Veii

Completely broken Thread Scheduler for AMD on v21996.1








Even with new 470.25 driver


Spoiler: SiSandra Log






Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 46.78GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 19.6ns (9.7ns - 22.4ns)
Inter-Thread (same Core) Latency : 9.8ns
Inter-Core (same Module) Latency : 20.5ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 3.9GB/s
No. Threads : 12
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 65.00W
Aggregate Inter-Thread Bandwidth : 737.03MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.02ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 554.34kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 9.88MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.04ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11
U0-C0T0 <> U2-C1T0 Data Latency : 21.7ns
U0-C0T0 <> U4-C2T0 Data Latency : 22.2ns
U0-C0T0 <> U6-C3T0 Data Latency : 20.5ns
U0-C0T0 <> U8-C4T0 Data Latency : 21.6ns
U0-C0T0 <> U10-C5T0 Data Latency : 20.2ns
U0-C0T0 <> U1-C0T1 Data Latency : 9.8ns
U0-C0T0 <> U3-C1T1 Data Latency : 21.7ns
U0-C0T0 <> U5-C2T1 Data Latency : 22.1ns
U0-C0T0 <> U7-C3T1 Data Latency : 20.6ns
U0-C0T0 <> U9-C4T1 Data Latency : 21.6ns
U0-C0T0 <> U11-C5T1 Data Latency : 20.2ns
U2-C1T0 <> U4-C2T0 Data Latency : 20.9ns
U2-C1T0 <> U6-C3T0 Data Latency : 20.7ns
U2-C1T0 <> U8-C4T0 Data Latency : 20.2ns
U2-C1T0 <> U10-C5T0 Data Latency : 20.3ns
U2-C1T0 <> U1-C0T1 Data Latency : 21.6ns
U2-C1T0 <> U3-C1T1 Data Latency : 9.8ns
U2-C1T0 <> U5-C2T1 Data Latency : 20.9ns
U2-C1T0 <> U7-C3T1 Data Latency : 20.7ns
U2-C1T0 <> U9-C4T1 Data Latency : 20.2ns
U2-C1T0 <> U11-C5T1 Data Latency : 20.3ns
U4-C2T0 <> U6-C3T0 Data Latency : 19.6ns
U4-C2T0 <> U8-C4T0 Data Latency : 21.5ns
U4-C2T0 <> U10-C5T0 Data Latency : 20.3ns
U4-C2T0 <> U1-C0T1 Data Latency : 22.0ns
U4-C2T0 <> U3-C1T1 Data Latency : 21.0ns
U4-C2T0 <> U5-C2T1 Data Latency : 9.7ns
U4-C2T0 <> U7-C3T1 Data Latency : 19.6ns
U4-C2T0 <> U9-C4T1 Data Latency : 21.5ns
U4-C2T0 <> U11-C5T1 Data Latency : 20.3ns
U6-C3T0 <> U8-C4T0 Data Latency : 18.9ns
U6-C3T0 <> U10-C5T0 Data Latency : 19.0ns
U6-C3T0 <> U1-C0T1 Data Latency : 20.4ns
U6-C3T0 <> U3-C1T1 Data Latency : 20.6ns
U6-C3T0 <> U5-C2T1 Data Latency : 19.6ns
U6-C3T0 <> U7-C3T1 Data Latency : 9.8ns
U6-C3T0 <> U9-C4T1 Data Latency : 18.9ns
U6-C3T0 <> U11-C5T1 Data Latency : 19.0ns
U8-C4T0 <> U10-C5T0 Data Latency : 19.6ns
U8-C4T0 <> U1-C0T1 Data Latency : 21.5ns
U8-C4T0 <> U3-C1T1 Data Latency : 20.3ns
U8-C4T0 <> U5-C2T1 Data Latency : 21.5ns
U8-C4T0 <> U7-C3T1 Data Latency : 19.2ns
U8-C4T0 <> U9-C4T1 Data Latency : 9.8ns
U8-C4T0 <> U11-C5T1 Data Latency : 19.8ns
U10-C5T0 <> U1-C0T1 Data Latency : 20.5ns
U10-C5T0 <> U3-C1T1 Data Latency : 20.6ns
U10-C5T0 <> U5-C2T1 Data Latency : 20.4ns
U10-C5T0 <> U7-C3T1 Data Latency : 19.4ns
U10-C5T0 <> U9-C4T1 Data Latency : 19.9ns
U10-C5T0 <> U11-C5T1 Data Latency : 9.8ns
U1-C0T1 <> U3-C1T1 Data Latency : 21.8ns
U1-C0T1 <> U5-C2T1 Data Latency : 22.4ns
U1-C0T1 <> U7-C3T1 Data Latency : 20.6ns
U1-C0T1 <> U9-C4T1 Data Latency : 21.6ns
U1-C0T1 <> U11-C5T1 Data Latency : 20.3ns
U3-C1T1 <> U5-C2T1 Data Latency : 21.0ns
U3-C1T1 <> U7-C3T1 Data Latency : 20.8ns
U3-C1T1 <> U9-C4T1 Data Latency : 20.3ns
U3-C1T1 <> U11-C5T1 Data Latency : 20.4ns
U5-C2T1 <> U7-C3T1 Data Latency : 20.0ns
U5-C2T1 <> U9-C4T1 Data Latency : 21.6ns
U5-C2T1 <> U11-C5T1 Data Latency : 20.4ns
U7-C3T1 <> U9-C4T1 Data Latency : 19.3ns
U7-C3T1 <> U11-C5T1 Data Latency : 19.1ns
U9-C4T1 <> U11-C5T1 Data Latency : 19.7ns
1x 64bytes Blocks Bandwidth : 9.32GB/s
4x 64bytes Blocks Bandwidth : 11.1GB/s
4x 256bytes Blocks Bandwidth : 40.24GB/s
4x 1kB Blocks Bandwidth : 139.25GB/s
4x 4kB Blocks Bandwidth : 204.23GB/s
16x 4kB Blocks Bandwidth : 310.68GB/s
4x 64kB Blocks Bandwidth : 322.86GB/s
16x 64kB Blocks Bandwidth : 57.52GB/s
8x 256kB Blocks Bandwidth : 40.16GB/s
4x 1MB Blocks Bandwidth : 19.32GB/s
16x 1MB Blocks Bandwidth : 15.47GB/s
8x 4MB Blocks Bandwidth : 13.41GB/s

Benchmark Status
Result ID : AMD Ryzen 5 5600X 6-Core Processor (6C 12T 4.85GHz, 1.9GHz IMC, 6x 512kB L2, 32MB L3)
Microcode : A20F10-1009
Computer : Acidanthera iMac20,1 iMac (Acidanthera Mac-CFF7D910A743CAAF)
Platform Compliance : x64
No. Threads : 12
System Timer : 10MHz
Page Size : 4kB

Processor
Model : AMD Ryzen 5 5600X 6-Core Processor
URL : https://www.amd.com
Speed : 4.85GHz
Min/Max/Turbo Speed : 2.2GHz - 3.7GHz - 4.85GHz
Cores per Processor : 6 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
Latest Version : A20F10-1016
L1D (1st Level) Data Cache : 6x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 6x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 6x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 65.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Warning 5010 : Cannot use Large Memory Pages due to lack of privileges.
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 229 : CPU microcode update available. Check for an updated System BIOS with updated microcode.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.




Ignore the CPU ID, it was a test
But apparently there should be a new microcode update higher than A20F10-1009
Curious to check & see

Can agree that game perf tho is better for some reason, soo aida64 doesn't lie that cache is messed up
I want to see how they'll fix such in 2-3 days
When you push load to the CPU , "randomly" cache performance comes back ~ as if something is holding it back


----------



## Mach3.2

I've managed to get tighten the timing on this set of 16GB Micron Rev. B ICs down to 14-17-16-31 1T, passed 25 rounds of default @1usmus_v3 TM5 and 600% of HCI MemTest. No WHEA errors.

Just putting the ZenTiming screenshot here for another set of eyes to look through them to make sure it's kosher.

I'm still planning to tighten tRCD_WR and tRFC further though.

AIDA results are pretty consistent across 6 passes on a clean windows install too.


----------



## sendap

Dasa said:


> 56-0-0 allowed me to drop ProcODT & DrvStr back down and just helped stability in general even more than 46 and also seems to have helped my WHEA errors at 3800.
> Any performance hit seems to be worth it as I am now getting the best Geekbench and TimeSpy benchmarks with AddrCmdSetup 56 and the tighter timings it allows.
> Still fine tuning and may have to give up on tRCD15 for stability reasons but this is where it is at now with the 5800X at stock.
> 
> View attachment 2514771
> 
> 
> GB5 Multi-Core Score 12052
> TimeSpy CPU Score 13390
> 
> Edit: Oops looks like I missed changing tRC to 44 in that image.


i got very similar AIDA Results with Flat 15 1T. Do you have some special CPU cooling solution? I run on a NH-D15 and get a score of 
13050 Time Spy
11900 GB5 
PBO +100 and CO


----------



## Pickclock

Hello fellow Overclockers 
Novice overclocker here. I read many pages back in the thread, and here I am with my attempt. It took me about a week to get it finally stable, however I am concerned about ProcODT + Rtt + DrvStr + Setup values. I left all those settings on Auto. The PC is stable, but I am worried if it may damage either my CPU, board or memory modules, is there something dangerous or is it safe for 24/7 daily?
And next, I have lost about voltage. I read Veii posts about voltage steps, but I could not get it to be stable that way, so I have had to go with try/error route. Set values in BIOS are:
VSOC - 1.08125, VDDG CCD - 0.94, VDDG IOD 1.03, CLDO VDDP 0.9
Is there any visible fault please? Either timings, voltages or just whatever value.
Perhaps, is there a chance to switch to 1T somehow?


----------



## mongoled

Art385 said:


> On my 5800x and MSI B550 Tomahawk bios A71 AGESA 1.2.0.3A if I set negative [email protected] (or positive) for problematic cores (rest are quite great form -22 to -30) it will cap voltage, frequency and power draw to around 120W (limit is 142) in CB20 MT test. Voltage will drop to ~1.25-1.28v. Setting them to -3 will shift whole V/F table up and CPU will push around 1.3-1.33v in CB20 and go all the way to set in bios limits. Frequency will also be higher by 50-75MHz though will heat up to 85c instead of 75c. I'm very happy with this finding as at those settings my CPU is always stable at last in core cycler through all FFT sizes (auto setting).
> After weeks off testing and getting random fails even after reboot on settings that was running stable for like 8h in CC xD
> It's also really easy to set up so I will share as it works - maybe it will save someone some time. You just need to set Scalar to x1 autoOC off then set all the "good" cores that will not randomly fail to max negative offset that is stable (couple of iteration will do). Now you will need to find when "capping" occurs in CB20. To do this set low negative offset on bad/failng cores - good place to start is -1 at least on MSI though it can vary per config curve setting. Now just push negative offset on those cores up to the point where V/F table shifts - don't touch other cores offsets (bump 1 point on Curve at a time to know exactly when it occurs). This will be rock stable setting.
> Now if you want you can fine tune offset. You can go again by one point (more time) or just bump by 5 points. Now this is a little tricky as you will need to test one pass on those ****ty cores (set rest of the cores as ignored in CC config file) If test will pass turn off PC completely and retest. On my system cores will fail on second testing attempt if their are unstable. If cores fails just back down CO offset by 1 on these cores to the point when after every power cycle CC will pass. Done, when you set CO this way bad cores will never boost past stability and randomly fail. Now you can retest all the cores - 6 iteration on auto setting for time per core should be enough.
> 
> Sorry for my English


English is fine



Very good data and very good thought process to follow this line of investigation.

The only "issue" is do you see what you have described above to be consistent across reboots ?

As thats my main gripe after thinking ive got Ryzen 5000 series "worked out" the characteristics are not the same across multiple reboots....

For whats its worth, I thought that pushing my assigned good cores to + CO values was going to have a negative effect on my CB23 scores and it did when I first tested it, but after a reboot the scores were where they should be so I kept my CO values that are tried and tested for the max boost override that can be run on later BIOS, that is 200 mhz ...



PJVol said:


> Perhaps I wasn't clear, I refered to your screen below, with edc limit 110A.
> 
> So unless you weren't using CO (that would explain quite high Vcore) I don't see our systems do differ much.


They dont differ much but the difference in wattage is quite substantial !



PJVol said:


> Its not about being "normal" or not. Just trying to figure something out.
> In short, with PBO, cpu's boost constantly thermally limited. I mean not by PROCHOT assertion, but in the way current boost frequency depends on temp. sensors data.
> These algorithms and boosted P-states are seemingly hidden even at the ACPI level.
> 
> As for 15W, mine when running cbr23 @72-73 C draw ~ 13W per core. So maybe yours and @mongoled higher boosting cores were tuned with higher leakage profile.
> 
> Don't get, what all that df- and c- states things was about, sorry ))


I will look into this and investigate my system to see if I can spot where the difference in wattage is coming from ...



CarnageBT said:


> After fighting with my setup for days, getting the odd 25 cycles to pass, then failing later with the same settings, using a huge fan blowing directly in my open case (keeps max dimm temps down about 4 degrees to 44.5), I've given up as well. but am not done "chasing the white rabbit"
> 
> Based your your experience, we ruled that I have 1 stick that isn't as good as the others, great call.
> 
> I've re-ordered another set of my ram. As long as 1 of the 2 sticks is good, then I will swap it in with my other 3 and hopefully, finally, I will consistently pass the 25 cycles of TM5.
> 
> TLDR. I ordered another set of my ram to swap out against my 1 bad stick. Wish me luck. Fingers crossed
> 
> What is the best way to benchmark individual sticks to find the best ones? Based on lowest passable timings?


Yup, based on the lowest possible, just like you did before, good luck!





Drevi said:


> Yes, it was realtime. This is what a normal run looks like (finished at 11919):
> View attachment 2514812


Thanks for the screenshot, your temps were lower in this run (77C vs 80C) 3C will definatly make a difference on the score


----------



## Takla

Mach3.2 said:


> I've managed to get tighten the timing on this set of 16GB Micron Rev. B ICs down to 14-17-16-31 1T, passed 25 rounds of default @1usmus_v3 TM5 and 600% of HCI MemTest. No WHEA errors.
> 
> Just putting the ZenTiming screenshot here for another set of eyes to look through them to make sure it's kosher.
> 
> I'm still planning to tighten tRCD_WR and tRFC further though.
> 
> AIDA results are pretty consistent across 6 passes on a clean windows install too.


Copy looks low. See my 4x8GB:


----------



## Mach3.2

Takla said:


> Copy looks low. See my 4x8GB:


I'm running 2 single rank sticks, maybe dual rank interleaving had something to do with the higher numbers you're seeing?

Stock XMP profile benched lower too.


----------



## CarnageBT

mongoled said:


> Yup, based on the lowest possible, just like you did before, good luck!


Are there certain settings I should change for single stick vs quad stick testing? Ie. tRDWR/tWRRD ?


----------



## byDenoso

Is my Ram Ok for my R5 3600?

Do i need to tweak something?

I posted here because in games i'm experiencing some stuttering.


----------



## craxton

mongoled said:


> I will look into this and investigate my system to see if I can spot where the difference in wattage is coming from


whats your core 3 look like (the one getting the hightest voltage)
while running core cycler?
i myself, no matter really what core (although my worst/best fused core) sees 16 watts max
the rest fall in line at 15 watts...
max in R23 with "tuned" CO offset without C6 package on, gets well....i suppose i could
lower TDP by some margin and lower over all power but at the same time, this are the exact settings
i ran Core-Cycler for 12 hours without fail.
(i probably could get more out of core 3 and 6 with more negative CO)
but at this time, ive been fighting this "bad" core for weeks. 
(fails with C6 package turned on using zenstates i quickly change this)


----------



## mongoled

CarnageBT said:


> Are there certain settings I should change for single stick vs quad stick testing? Ie. tRDWR/tWRRD ?


Good question! Leave those both on AUTO just incase the values you have set lead to a no post/reset CMOS scenario.

You really only want to get a rough ball park of what each stick can run reliably without too much tweaking.


----------



## mongoled

craxton said:


> whats your core 3 look like (the one getting the hightest voltage)
> while running core cycler?
> i myself, no matter really what core (although my worst/best fused core) sees 16 watts max
> the rest fall in line at 15 watts...
> max in R23 with "tuned" CO offset without C6 package on, gets well....i suppose i could
> lower TDP by some margin and lower over all power but at the same time, this are the exact settings
> i ran Core-Cycler for 12 hours without fail.
> (i probably could get more out of core 3 and 6 with more negative CO)
> but at this time, ive been fighting this "bad" core for weeks.
> (fails with C6 package turned on using zenstates i quickly change this)
> 
> View attachment 2514852
> 
> View attachment 2514851


Hopefully will find the time to test and will let you know tomorrow


----------



## CarnageBT

mongoled said:


> Good question! Leave those both on AUTO just incase the values you have set lead to a no post/reset CMOS scenario.
> 
> You really only want to get a rough ball park of what each stick can run reliably without too much tweaking.


Ok, I'll test each of my 4 sticks with the settings below aside from switching it to flat 14's and tRDWR/tWRRD set to auto. 

If the 3 good sticks I have pass, I'll just have to test the 2 new ones and hopefully will end up with a complete flat 14 set =)


----------



## Takla

Mach3.2 said:


> I'm running 2 single rank sticks, maybe dual rank interleaving had something to do with the higher numbers you're seeing?
> 
> Stock XMP profile benched lower too.


Mhh. If I disable Chipselect Interleaving in AMD CBS I get 2K less Copy, so around what you are getting.
But I'm confused. Shouldn't your 2x16GB be dual rank?


----------



## Mach3.2

Takla said:


> Mhh. If I disable Chipselect Interleaving in AMD CBS I get 2K less Copy, so around what you are getting.
> But I'm confused. Shouldn't your 2x16GB be dual rank?


16GB sticks of Micron Rev. B are single rank.


----------



## Takla

Mach3.2 said:


> 16GB sticks of Micron Rev. B are single rank.


Weird. But thanks for the info.


----------



## CarnageBT

Question regarding CPU/NB SOC. I have my NB/SOC voltage in override mode at 1.1 with 1000khz swittching and CPU NB/SOC LLC at 1 (max). 

I always left it there because I've never once seen overshoot when watching HWinfo. I recently noticed that I've only been watching the processor SoC voltage svi2, which is always perfect, 1.1, no overshoot.

I just noticed there is also the motherboard readout which shows CPU/NB SoC, that one frequently overshoots to 1.12, max 1.135 from my setting at 1.1 

TLDR: does the motherboard cpu nb/soc readout matter? or am I only concerned with the processor soc svi2 readout?


----------



## Takla

Chipselect Interleaving set to disabled inside AMD CBS section under UMC Common Options DRAM Memory Mapping gives me 1ns lower latency at the cost of 2K copy in AIDA64. Thoughts on what is better for fps in games? I'm tending to latency.


----------



## CarnageBT

When validating single stick memory. What values need to be changed coming from a 4 dimm setup?
I left tRDWR/tWRRD on auto and my board left them at 8/3.
Are there some settings that are specific to single vs multi dimms?

I'm asking because I'm getting multiple errors within the first 10 cycles on my single sticks but when I use the exact same settings with all 4 dimms they either pass all 25 cycles or throw a single error between hour 2 and 3 of TM5.

Makes me think, there are some settings I need to change to correctly test individual sticks. @Veii @mongoled










Edit: I believe it was all the power settings needed for 4 dimms at 3800; Setup times 56-56-56, ProcODT 40, Drv strengths.


----------



## Veii

CarnageBT said:


> Makes me think, there are some settings I need to change to correctly test individual sticks. @Veii @mongoled


I've never been binning ram sticks
Just go with what i have - but then also never really been using 4 dimms (for my system)
Soo prettty much never did this

We are different, both mongoled and me
I use bruteforce methods and continue (often for months) till i meet my goal & dig through all kind of possible shenanigans to make it stable on lower tRCD
(soo such abstract methods and values are found ~ researching abstract things keeps the motivation up, repeating the same steps is booring to me)
* reminder that i run 80-90€ A0 b-dies  and they are certainly not "great" binning

But i don't have the money to afford binning dimms - can't help you with such
Pretty sure that timings fully change when only testing one dimm, and so also tRRD and tWTR requirements change, in order to get them running
You can likely do 2 at a time and look for "stable at X lowest voltage" ~ or "can run this harsh timings"
Then the weaker one you put on the main slots and the better ones on the slave slot (daisy chain current split)



CarnageBT said:


> Setup times 56-56-56, ProcODT 40, Drv strengths.


Likely counter intuitive to all the research that has been postet
But SETUP timings continue to be a delay
over the value 32 they are very similar to 2T performance - just slightly better

Between 1T and 2T is often a big voltage difference , but it's not a binning difference (what can run 2T , will run 1T with different powering and voltages)
I feel SETUP timings make your live a bit too easy.
You can use the low ones 1-31 like i did. That works together with powerdownmode (which to some part is also cheating, but working on heatmanagement for the "bad" PCB)
Tho, beyond 32 it changes it's behavior and is rather a command rate similar behavior

I can not fully take 1T with such high SETUP timings, serious - but this is a personal thing
Can very well see that you get performance improvements and "it runs" , soo why not let you enjoy this success 
Tho for you who anyways invests soo much time - try to work without them. They are not needed , only help ~ but it's better without them
And surely do not attempt 1T 14-14-14 out of nowhere, first be sure it's 2T stable


----------



## byDenoso

Should i Run GDM OFF or 2T on Hynix DJR?


----------



## Ethelneth

Mach3.2 said:


> I've managed to get tighten the timing on this set of 16GB Micron Rev. B ICs down to 14-17-16-31 1T, passed 25 rounds of default @1usmus_v3 TM5 and 600% of HCI MemTest. No WHEA errors.
> 
> Just putting the ZenTiming screenshot here for another set of eyes to look through them to make sure it's kosher.
> 
> I'm still planning to tighten tRCD_WR and tRFC further though.
> 
> AIDA results are pretty consistent across 6 passes on a clean windows install too.


Here is how I run 4x of the same SR sticks (sensor reported vdimm is about 1,33V when set to 1,30V in bios):










AIDA average results on 5 consecutive runs:
read: 55402 MB/s
copy: 54225 MB/s
write: 30397 MB/s
latency: 55,0 ns

I can confirm you can get a couple GB/s more on memory copy by running 4 sticks, as I initially went for a single kit and lost the dual rank lottery. Thankfully my second kit was a perfect match (same production week, similar serial numbers).

Minimum bootable tRFC in my case is about 291 ns. tRRDL, tWTRL, tFAW and tWR could be tightened a bit more but at the expense of some stability.
Unfortunately I couldn't get anything above 1900 fclk whea warning free even if 2000 fclk boots and benchmarks just fine.
Note that with just 2 dimms you should be able to run tWRRD=1.


----------



## pipeclock

Takla said:


> Chipselect Interleaving set to disabled inside AMD CBS section under UMC Common Options DRAM Memory Mapping gives me 1ns lower latency at the cost of 2K copy in AIDA64. Thoughts on what is better for fps in games? I'm tending to latency.


-1 ns is huge boost in games, so prefer latency for sure.


----------



## pipeclock

Veii said:


> Tho for you who anyways invests soo much time - try to work without them. They are not needed , only help ~ but it's better without them


Hello, please do you mean it´s better to not use the Setup values at all? Leave it all at 0?


----------



## Veii

pipeclock said:


> Hello, please do you mean it´s better to not use the Setup values at all? Leave it all at 0?


Pretty much yes
They help a lot, but it's undeniable that they do add latency
from the range of 1-31 it's working together with powerdownmode and tCKE (agressive powerdown)

But after 32-63?64, they work similar to how a command rate bump behaves


byDenoso said:


> Should i Run GDM OFF or 2T on Hynix DJR?


Focus your time to get GDM off 2T stable - it makes your time more worth
GDM changes too much things, and will give you a bad illustration that your Dimms could potentially run low timings (it's not a good thing)


----------



## Mach3.2

Ethelneth said:


> Here is how I run 4x of the same SR sticks (sensor reported vdimm is about 1,33V when set to 1,30V in bios):
> 
> View attachment 2514894
> 
> 
> AIDA average results on 5 consecutive runs:
> read: 55402 MB/s
> copy: 54225 MB/s
> write: 30397 MB/s
> latency: 55,0 ns
> 
> I can confirm you can get a couple GB/s more on memory copy by running 4 sticks, as I initially went for a single kit and lost the dual rank lottery. Thankfully my second kit was a perfect match (same production week, similar serial numbers).


Thanks for confirming that higher copy numbers are due to interleaving.




Ethelneth said:


> Minimum bootable tRFC in my case is about 291 ns. tRRDL, tWTRL, tFAW and tWR could be tightened a bit more but at the expense of some stability.
> Unfortunately I couldn't get anything above 1900 fclk whea warning free even if 2000 fclk boots and benchmarks just fine.
> Note that with just 2 dimms you should be able to run tWRRD=1.


General consensus seem to say that tFAW tighter than tRRDS*4 does nothing to improve performance so I'll probably keep it at 16. I'll look into tightening tRFC to around 295ns first, before playing with tRRDL, tWTRL, tWR and tWRRD.

I think I've pretty much lost the IMC silicon lottery despite getting 2 decent CCDs that can do -30 on almost all cores. Even running the IF at 1833MHz generated a few WHEA errors on XMP timing.


----------



## sendap

also running 1T 56-56-56 on 3800 Flat 15. Still better results than same timings on 2T 3-3-15. Have to try 1T 0-0-0 again. Or maybe 1T 3-3-15? Had no success so far...

stable:


----------



## craxton

sendap said:


> also running 1T 56-56-56 on 3800 Flat 15. Still better results than same timings on 2T 3-3-15. Have to try 1T 0-0-0 again. Or maybe 1T 3-3-15? Had no success so far...
> 
> stable:
> View attachment 2514903
> View attachment 2514904


4-4-18 should work....or from what i remember.... 
not running DR myself but 4x8 is similar to DR on a 2x16 scale.


----------



## XPEHOPE3

Anyone knows what is the reason behind Aida64 varying latency between reboots?
I measure in Safe mode without network drivers, but on one reboot I get e.g. 58.6-58.8 ns across 5 runs, on the other reboot I get 59.1-59.5 ns. But there are only those two types of "reboots", that is I never get other values for those settings.


----------



## pipeclock

XPEHOPE3 said:


> Anyone knows what is the reason behind Aida64 varying latency between reboots?
> I measure in Safe mode without network drivers, but on one reboot I get e.g. 58.6-58.8 ns across 5 runs, on the other reboot I get 59.1-59.5 ns. But there are only those two types of "reboots", that is I never get other values for those settings.


Try the Diagnostic mode instead. Search > msconfig > diagnostic mode > restart.


----------



## craxton

XPEHOPE3 said:


> Anyone knows what is the reason behind Aida64 varying latency between reboots?
> I measure in Safe mode without network drivers, but on one reboot I get e.g. 58.6-58.8 ns across 5 runs, on the other reboot I get 59.1-59.5 ns. But there are only those two types of "reboots", that is I never get other values for those settings.


it can be "can be" another service is running while in safe mode. take note on how many process
are running while you get the "lower" score. (im not running in safe mode) 
and have loads of tabs open, auto start programs etc. 
i do recall that some voltages upon boot can differ.


----------



## XPEHOPE3

Time to report some progress on OCing 4*16GB B-dies.


Veii said:


> Droopy. Y-Cruncher is mostly AVX2, you want to move on some tests near 1.18-1.2v, some like the first one can often need 1.35v upwards
> Droopy & Variable is what you're looking for. Soo i start with it, before anything.


I haven't found a single combination of vCore LLC and vSOC LLC to crush y-cruncher within 2-4 iterations yet. I also tried to pick LLCs and 1.8v-rail value based on Aida latency results (measured in safe mode with network drivers, "normal" is default and has the most droop):


Spoiler: table




vCore LLCvSOC LLC1.8v raillatency minlatency maxlowturbo (one lower than flat)1.858.758.9lowturbo1.8458.959highturbo1.8458.959highturbo1.859.960highnormal1.859.659.9highnormal1.8459.559.7lownormal1.8458.959.1lownormal1.859.459.6normalnormal1.8458.860normalnormal1.858.558.8



Based on this I picked (for now) default values for LLCs (most droop) and 1.8 rail.



Veii said:


> GDM off first, TM5 stable / later aida64 baseline screenshot


GDM off 2T done (3600-14):






















Veii said:


> 1900FCLK post, checking Aida64 run if it's better than the early screenshot. Adjust VDDG and procODT till it's better / then TM5 stable + y-cruncher afterwards


This I didn't understand maybe. If I just set FCLK to 1900 and change nothing else in existing 3600-14 setup, how can latency be anywhere near the same? I got 5ns bump in safe mode from 58.6 to 63.6. I assumed then that you meant to enter some surely working setup with FCLK=1900=MEMCLK, so I used 3800-16 flat. And it ran worse than base until I changed procODT from 48 to 43.4. Then fine tuned VDDGs: CCD to 1018mV and IOD to 1100mV (EDIT: was 1020 by error). GET difference is more than 80mV, unlike if CCD set to 1020. I arrived at these results, which are not better than base latency-wise, but no other procODT/VDDGs values were better:














Will see what TM5 would say. It's 28-33C here, hope memory won't burn 😇


----------



## XPEHOPE3

craxton said:


> i do recall that some voltages upon boot can differ.


problem is - in safe mode I can't see them with neither HWInfo nor ZenTimings


----------



## dansi

Mach3.2 said:


> Thanks for confirming that higher copy numbers are due to interleaving.
> 
> 
> 
> General consensus seem to say that tFAW tighter than tRRDS*4 does nothing to improve performance so I'll probably keep it at 16. I'll look into tightening tRFC to around 295ns first, before playing with tRRDL, tWTRL, tWR and tWRRD.
> 
> I think I've pretty much lost the IMC silicon lottery despite getting 2 decent CCDs that can do -30 on almost all cores. Even running the IF at 1833MHz generated a few WHEA errors on XMP timing.


having good CCDs is far better than chasing the FCLK
for every -10, you gain a 3% uplift. 
Try running BCLK at 101 if you want to push ram performance.


----------



## craxton

XPEHOPE3 said:


> problem is - in safe mode I can't see them with neither HWInfo nor ZenTimings


to my knowledge its not possible unless someone knows a way. 
i tried myself to get something working, and AIDA was the only thing to 
show "barely anything at all" 
but none the less, here are 2 runs (5 total but they were all the same pretty much)
(1 run, would seem i didnt screenshot the last of the 5) 4 of 5 were 51.6 and one was 51.7


----------



## Veii

craxton said:


> 4-4-18 should work....or from what i remember....


4-4-18 is for 4000MT/s, 3-3-15 is for 3800MT/s
tCKE 11 is for 4000MT/s, tCKE 9 is for 3800MT/s


XPEHOPE3 said:


> I haven't found a single combination of vCore LLC and vSOC LLC to crush y-cruncher within 2-4 iterations yet.


Crush = crash ?
Crush = crush/beat ?
Crush = y-*crunch'*er ~ run ?



XPEHOPE3 said:


> GDM off 2T done (3600-14):


Perfect half for 3600MT/s (1800FCLK) = 28800MB/s
Take 1mb/s away for the OS kernel, 28799MB/s write ~ is your target
~ only hit once in a blue moon perfect perfect half, but 1 off is good enough 

Write for 1800FCLK needs to be perfect half (-1), else you are autocorrecting & FCLK throttling slightly (bigger in your case)


Veii said:


> 1900FCLK post, checking Aida64 run if it's better than the early screenshot. Adjust VDDG and procODT till it's better / then TM5 stable + y-cruncher afterwards
> 
> 
> XPEHOPE3 said:
> 
> 
> 
> This I didn't understand maybe. If I just set FCLK to 1900 and change nothing else in existing 3600-14 setup, how can latency be anywhere near the same?
Click to expand...

Memory latency will be "the same" or "higher" if the CPU starts to autocorrect FCLK ~ the bump will be strongly noticeable
This is where you adjust SOC & the 1.8v rail to get the lowest result possible
This work is usually what you do for every FCLK , till you are absolutely sure that it can not be lower & verify the "found voltages" with y-cruncher and OCCT extreme

But all this expects a clean OS
Or a least a daily OS with many Microsoft Spyware Services disabled








GitHub - madbomb122/BlackViperScript: Sets Win 10 Services based on Black Viper's Service Configurations


Sets Win 10 Services based on Black Viper's Service Configurations - GitHub - madbomb122/BlackViperScript: Sets Win 10 Services based on Black Viper's Service Configurations




github.com




&








GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11


:zap: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11 - GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-t...




github.com





first sophia script, then black viper then








WPD


Privacy dashboard for Windows




wpd.app




Is pretty much my order on every install
Even on an optimize-offline reworked iso 



XPEHOPE3 said:


> it ran worse than base until I changed procODT from 48 to 43.4.


Maybe you haven't read this whole thread








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




3 ProcODT's pretty much always work, only one of them has less than 0.3ns variance
0.1-0.2ns is test to test variance. 0.3ns = instability or other strangeness (for example buggy enabled DF-C States) or just a bad OS

At the very end you also grab Autoruns for Windows - Windows Sysinternals
Press on Scan - Options - Check with VirusTotal
Disable everything that appears Red with a potential spyware or virus
And disable everything else that appears suspicious or useless

Windows to Go service
Chrome, IE-xplorer, Discord "updater", skype and SysMain services
all of the printer category & most of the anti cheats
. . . and so on 


XPEHOPE3 said:


> I got 5ns bump in safe mode from 58.6 to 63.6.


Stop using Safe-Mode
it's cheating and hiding things
Powermanagement is disabled
WMI links are disabled
CPPC is disabled
Windows Error Reporting is disabled

Makes no sense to run on it
Also it can perform worse than a fixed OS 
my latency on it is worse than inside a booted windows
Stopping windows explorer also does nothing but harm, as on the restart it does start more services with it

* keep in mind with blackviperscript, it does disable WLAN autoconfig (breaks wifi)
And enabled SysMain service (need to disable it)
** also might want to go on it's options and tell it to skip xbox services (for a daily gaming OS)


----------



## craxton

Veii said:


> 4-4-18 is for 4000MT/s, 3-3-15 is for 3800MT/s


so thats why i never could simply lower freq to test...
always had issues. (just remember you mentioning to me to "test" tcke 9
quite a while back when you were still figuring out what worked and didnt.

this rule applies for 2T GDM off, or in general for 4000/2000?


----------



## Veii

craxton said:


> this rule applies for 2T GDM off, or in general for 4000/2000?


Generally 
tCKE & SETUP timings scale & differ by MCLK
* also the reason why i run tCKE 13 on 4200MT/s
==================================
Played yesterday with an X570 Aorus Elite
CPU VDDP exists and scales down "in offsets" (AGESA 1203A)
920ish is stock, because -100mV was 820mV ~ went down to 700mV set
HWInfo could read it out and behaved the same way on Matisse

It is NOT APU bound to what MSI shares, but likely APUs utilize it further
Seems to not only apply to Vermeer
Anywho, it's usable and readable ~ whatever it brings on Matisse 

EDIT:
To give Gigabyte engineers bit of credit,
Bad memory profiles do not reset to a 2nd bios, and boards do finally reset by their own
That was far worse before & finally seems to be "fixed"
Early on you could reflash the bios after unsuccessful memory training
~ now i have to change my mind about their X570 series again. (before they where completely unusable for OC)
At least for now


----------



## dansi

Veii said:


> 4-4-18 is for 4000MT/s, 3-3-15 is for 3800MT/s
> tCKE 11 is for 4000MT/s, tCKE 9 is for 3800MT/s
> 
> Crush = crash ?
> Crush = crush/beat ?
> Crush = y-*crunch'*er ~ run ?
> 
> 
> Perfect half for 3600MT/s (1800FCLK) = 28800MB/s
> Take 1mb/s away for the OS kernel, 28799MB/s write ~ is your target
> ~ only hit once in a blue moon perfect perfect half, but 1 off is good enough
> 
> Write for 1800FCLK needs to be perfect half (-1), else you are autocorrecting & FCLK throttling slightly (bigger in your case)
> 
> Memory latency will be "the same" or "higher" if the CPU starts to autocorrect FCLK ~ the bump will be strongly noticeable
> This is where you adjust SOC & the 1.8v rail to get the lowest result possible
> This work is usually what you do for every FCLK , till you are absolutely sure that it can not be lower & verify the "found voltages" with y-cruncher and OCCT extreme
> 
> But all this expects a clean OS
> Or a least a daily OS with many Microsoft Spyware Services disabled
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - madbomb122/BlackViperScript: Sets Win 10 Services based on Black Viper's Service Configurations
> 
> 
> Sets Win 10 Services based on Black Viper's Service Configurations - GitHub - madbomb122/BlackViperScript: Sets Win 10 Services based on Black Viper's Service Configurations
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> &
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11
> 
> 
> :zap: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11 - GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-t...
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> first sophia script, then black viper then
> 
> 
> 
> 
> 
> 
> 
> 
> WPD
> 
> 
> Privacy dashboard for Windows
> 
> 
> 
> 
> wpd.app
> 
> 
> 
> 
> Is pretty much my order on every install
> Even on an optimize-offline reworked iso
> 
> 
> Maybe you haven't read this whole thread
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 3 ProcODT's pretty much always work, only one of them has less than 0.3ns variance
> 0.1-0.2ns is test to test variance. 0.3ns = instability or other strangeness (for example buggy enabled DF-C States) or just a bad OS
> 
> At the very end you also grab Autoruns for Windows - Windows Sysinternals
> Press on Scan - Options - Check with VirusTotal
> Disable everything that appears Red with a potential spyware or virus
> And disable everything else that appears suspicious or useless
> 
> Windows to Go service
> Chrome, IE-xplorer, Discord "updater", skype and SysMain services
> all of the printer category & most of the anti cheats
> . . . and so on
> 
> Stop using Safe-Mode
> it's cheating and hiding things
> Powermanagement is disabled
> WMI links are disabled
> CPPC is disabled
> Windows Error Reporting is disabled
> 
> Makes no sense to run on it
> Also it can perform worse than a fixed OS
> my latency on it is worse than inside a booted windows
> Stopping windows explorer also does nothing but harm, as on the restart it does start more services with it
> 
> * keep in mind with blackviperscript, it does disable WLAN autoconfig (breaks wifi)
> And enabled SysMain service (need to disable it)
> ** also might want to go on it's options and tell it to skip xbox services (for a daily gaming OS)


you mean the ns latency in aida64 should stay within 0.2ns run to run variance?

anything above means fclk instability from auto-correction?

how do we solve this instability, adjust the procODT first, than the vsoc?


----------



## Veii

dansi said:


> you mean the ns latency in aida64 should stay within 0.2ns run to run variance?
> 
> anything above means fclk instability from auto-correction?


Yes, exactly
But it can also mean windows services
Soo i put the thread scheduler to background services








Everything get's equal priority
And fixed paging size

Usually run-to-run variance is 0.0ns or 0.01ns
You shouldn't move the mouse after pressing "start test"
And if you cherry pick values, it won't reach peak boost in time
Soo "start test" and wait 


dansi said:


> how do we solve this instability, adjust the procODT first, than the vsoc?


Adjusting VDDP, VDDG and SOC
but first find "the working" procODT which gives less to non variance
You can mostly boot 3 different ones, but only one is correct
It does change by voltages (lower voltages lower procODT) , soo focus on lowering voltages first till y-cruncher just dies out 
(FFT, N64,C19 all potential issues) ~ but test all of them 4*18min = 72min for "required stability"
TM5 will also spill error #6 if it's unstable FCLK & not only unstable timings

For 1 CCD users it's easy to just focus on Aida64 Write Bandwidth
For me, if Aida64 doesn't improve ever so slightly, it's not worth my time to test it for 2-3hours + TM5 hours
Soo it really is one of your best friends, if you know what to look for, on it
It's not all about the latency you get ~ but about the little tiny improvements you make across the journey.
It's only a benchmark for you against you ~ hard to compare against everyone else, except when you lower latency further and further.
But Bandwidth matters too 

* (TM5, Aida64, Y-Cruncher, OCCT, CPU-Z, Cinebench, BoostTester, HWInfo, SiSoftware Sandra) ~ is all you need to configure Vermeer
** probably also CoreCycler, but you can do the same work also by hand with y-cruncher & CMD for OCCT,CPU-Z,Cinebench Core Affinity Test ~ or with Processor Lasso


----------



## craxton

Veii said:


> Generally
> tCKE & SETUP timings scale & differ by MCLK
> * also the reason why i run tCKE 13 on 4200MT/s
> ==================================
> Played yesterday with an X570 Aorus Elite
> CPU VDDP exists and scales down "in offsets" (AGESA 1203A)
> 920ish is stock, because -100mV was 820mV ~ went down to 700mV set
> HWInfo could read it out and behaved the same way on Matisse
> 
> It is NOT APU bound to what MSI shares, but likely APUs utilize it further
> Seems to not only apply to Vermeer
> Anywho, it's usable and readable ~ whatever it brings on Matisse
> 
> EDIT:
> To give Gigabyte engineers bit of credit,
> Bad memory profiles do not reset to a 2nd bios, and boards do finally reset by their own
> That was far worse before & finally seems to be "fixed"
> Early on you could reflash the bios after unsuccessful memory training
> ~ now i have to change my mind about their X570 series again. (before they where completely unusable for OC)
> At least for now


i could "run" tCKE 1 and 9 but was never stable at all.

theres still no bios release for my board yet from MSI (none ive seen) checking daily.
been thinking about testing the "stock" bios to which a few versions back to notice how
different "CO" values might affect with what im 100% sure is rock solid at this time-without C6 package on-

i gave up on speaking to MSI at all about CPU_VDDP when they responded a 3rd time claiming its APU dependent and all that
bullsh*t. but, taking a look at ryzen master will show that its been fixed--->







<---

(edit) seems thats CLDO_VDDP) so idk what i was looking at the other day when i thought i seen CPU_VDDP.

so ill just leave it be for the time being. am however waiting for a piece to my pay to hit and will
be purchasing a "higher" core count CPU. not needed, just want "yes crossing fingers its a true gold sample"
but at this point just aiming to play with something else.

i gotta admit when a "bad profile" is loaded when i incorrectly load bad timings up on this MSI board
it does detect 90% of the time and revert back to what it was before hand. (still need to + - each timing) or enter manually again
or maybe not, still always do just to be sure.

the AORUS ELITE was the "other" board i was aiming to get since it had "all" the features i was after. but
after sometime looking at VRMs and temps etc, i landed with this board, since i got it for 130 us new (at that time was 189.99)

are you running a 6 core on that board, if so hows its VRMs handling it? what revision is the board your using??
thats the ONLY thing i didnt agree with on asus boards as one revision could be WAY better in most aspects while the next
be worse and you cant know what one youll get ordering from amazon nor newegg. which needs a fix honestly but 🤷‍♂️


----------



## dansi

Veii said:


> Yes, exactly
> But it can also mean windows services
> Soo i put the thread scheduler to background services
> 
> 
> 
> 
> 
> 
> 
> 
> Everything get's equal priority
> And fixed paging size
> 
> Usually run-to-run variance is 0.0ns or 0.01ns
> You shouldn't move the mouse after pressing "start test"
> And if you cherry pick values, it won't reach peak boost in time
> Soo "start test" and wait
> 
> Adjusting VDDP, VDDG and SOC
> but first find "the working" procODT which gives less to non variance
> You can mostly boot 3 different ones, but only one is correct
> It does change by voltages (lower voltages lower procODT) , soo focus on lowering voltages first till y-cruncher just dies out
> (FFT, N64,C19 all potential issues) ~ but test all of them 4*18min = 72min for "required stability"
> TM5 will also spill error #6 if it's unstable FCLK & not only unstable timings
> 
> For 1 CCD users it's easy to just focus on Aida64 Write Bandwidth
> For me, if Aida64 doesn't improve ever so slightly, it's not worth my time to test it for 2-3hours + TM5 hours
> Soo it really is one of your best friends, if you know what to look for, on it
> It's not all about the latency you get ~ but about the little tiny improvements you make across the journey.
> It's only a benchmark for you against you ~ hard to compare against everyone else, except when you lower latency further and further.
> But Bandwidth matters too
> 
> * (TM5, Aida64, Y-Cruncher, OCCT, CPU-Z, Cinebench, BoostTester, HWInfo, SiSoftware Sandra) ~ is all you need to configure Vermeer
> ** probably also CoreCycler, but you can do the same work also by hand with y-cruncher & CMD for OCCT,CPU-Z,Cinebench Core Affinity Test ~ or with Processor Lasso


i have my work apps opened and in the background, when i run multiple aida latency, it seems to give very stable results.

but if i clean boot into windows, with nothing opened, when i run multiple aida latency, it seems to vary much more. the lowest latency is better than the first scenario though.


----------



## mongoled

Veii said:


> Stop using Safe-Mode
> it's cheating and hiding things
> Powermanagement is disabled
> WMI links are disabled
> CPPC is disabled
> Windows Error Reporting is disabled
> 
> Makes no sense to run on it


No no no,

dont look at it in this way (cheating)

😍

Use it for diagnostic purposes, i.e. to compare latency between subtle changes and thats all.

It can be a very useful tool,

but to post AIDA64 screenshots in safe mode/diagnostic mode for eeeeepeeen, well that is lame


----------



## Veii

craxton said:


> will be purchasing a "higher" core count CPU. not needed, just want "yes crossing fingers its a true gold sample"
> but at this point just aiming to play with something else.


You likely want to wait for December/New Year


craxton said:


> are you running a 6 core on that board, if so hows its VRMs handling it? what revision is the board your using??


It was a 3900X but the VRMs are weak as you thought and i too at the start ~ just got to play with it for a bit
VRMs held 70c on 140A load
This is hard to compare when it was build into a case and it's on night-time always 24-25c
But it was weak. Probably equally weak like the ProArt ~ but "just enough to be fine"
I'd prefer the Aorus Pro, but last year i played with it ~ it got labled as "worthless board for any type of OC"
They used a dual bios, which you could not boot back into. They saved 2$ for the DIP switch and you had to reflash the bios every little bios mistake ~ wiping your profiles with it
The most unfriendly board i could play with ~ but so was also the surprise that the elite now functions well (once you efiflash /DB /C , it fully ~ cleanly)
No dual bios buggy shenanigans or other nonsense that shouldn't be there in the first place

Revision 1.0 i think
I'd love for the Aorus Pro to be good, as it's also on Intel Lan (the opposite opinion of BZ haha)
But can yet not be sure with it
So far the best performer where the Renesas 90A stages on this tiny True Phase ITX/AX (ASRock). ~ 35-42c @ 122A
(out of the boards i could play with. The Dark Hero was worse somehow)

Just it needs an unlocked bios ~ as it's a very booring board on stock. Tho functions and is reasonably priced for it's specs
Just really needs bios mods for it.
The only other "fun" option is the ASUS Impact ~ as comparison & maybe the X570I Aorus Pro (if they managed to get their bios shenanigans/issues together)

Then we come to the Unify-X but it misses as mATX/ITX OC version


mongoled said:


> Use it for diagnostic purposes, i.e. to compare latency between subtle changes and thats all.
> 
> It can be a very useful tool,
> 
> but to post AIDA64 screenshots in safe mode/diagnostic mode for eeeeepeeen, well that is lame


I can't, half of the diagnostic is missing/disabled and it shows unrealistic values
It doesn't utilize anything C-State related. It could look on it stable, yet in reality be completely broken and throttling
It wouldn't show much throttling indications & runs more services than a normal booted "maintained" OS


----------



## mongoled

@craxton

Here you go, corecycler ...










@PJVol next ....

CB23









Your CPU is reporting substantially lower peak CPU VID values.

I know for a fact that my system needs 1.31x volts to be stable Prime95 Small FFTs (AVX2) @ 4600 mhz, it would be impossible for it to be stable with 1.21x volts at 466x mhz.

The information relayed for my setup falls in line with my expectations taking into account what Prime95 Small FFTs require.

No idea why your system relays such low CPU VID, what voltage do you need to run Prime95 Small FFTs with AVX2 stable @ 4600 mhz ???


----------



## Nighthog

Veii said:


> Generally
> tCKE & SETUP timings scale & differ by MCLK
> * also the reason why i run tCKE 13 on 4200MT/s
> ==================================
> Played yesterday with an X570 Aorus Elite
> CPU VDDP exists and scales down "in offsets" (AGESA 1203A)
> 920ish is stock, because -100mV was 820mV ~ went down to 700mV set
> HWInfo could read it out and behaved the same way on Matisse
> 
> It is NOT APU bound to what MSI shares, but likely APUs utilize it further
> Seems to not only apply to Vermeer
> Anywho, it's usable and readable ~ whatever it brings on Matisse
> 
> EDIT:
> To give Gigabyte engineers bit of credit,
> Bad memory profiles do not reset to a 2nd bios, and boards do finally reset by their own
> That was far worse before & finally seems to be "fixed"
> Early on you could reflash the bios after unsuccessful memory training
> ~ now i have to change my mind about their X570 series again. (before they where completely unusable for OC)
> At least for now


CPU_VDDP on Renoir, 4650G has and effect on your PWM fans, they stop functioning if you go lower than stock voltage. Increasing voltage has effects on memory side stability.
Really only really usefull when doing Manual OC as it's often needed to be increased to maintain MEM OC stability as you increase Core Clock @ high MEM OC frequencies.
With PBO it's best left @ stock/AUTO most of the time as the behaviour is often detrimental to stability with PBO to mess with it. Though it can have a good/bad effect adjusting a little if nothing else seems to work.
On Mattise, 3800X you had more room for adjustment up or down. To similiar effect for MEM OC if on high frequency paired with Manual OC for cores. Usually +100-120mv was a good spot with my own testing in general there.
When I had my Biostar X470 GT8, it really liked to have this CPU_VDDP to be overvolted like crazy for any manual OC at all to work back when I was using my Ryzen 7 1700 for that board considered maximum MEM OC.


----------



## Veii

mongoled said:


> CB23
> 
> 
> 
> Your CPU is reporting substantially lower peak CPU VID values.
> 
> I know for a fact that my system needs 1.31x volts to be stable Prime95 Small FFTs (AVX2) @ 4600 mhz, it would be impossible for it to be stable with 1.21x volts at 466x mhz.


You beat me on the score & with 75Mhz more sustained
Can you check Tool.exe , and find your programmed ProcHot value ?

Voltage example, around 1.18-1.21 it needs for 4.6, but it thermal throttles















I feel like thermal throttling after 60c already , 65c is my programmed prochot
Really need to run again 2100 FCLK not stay on 1900. Need to finish this Rev.E research finally, someday, soonTM


----------



## Ezalor

Pickclock said:


> Hello fellow Overclockers
> Novice overclocker here. I read many pages back in the thread, and here I am with my attempt. It took me about a week to get it finally stable, however I am concerned about ProcODT + Rtt + DrvStr + Setup values. I left all those settings on Auto. The PC is stable, but I am worried if it may damage either my CPU, board or memory modules, is there something dangerous or is it safe for 24/7 daily?
> And next, I have lost about voltage. I read Veii posts about voltage steps, but I could not get it to be stable that way, so I have had to go with try/error route. Set values in BIOS are:
> VSOC - 1.08125, VDDG CCD - 0.94, VDDG IOD 1.03, CLDO VDDP 0.9
> Is there any visible fault please? Either timings, voltages or just whatever value.
> Perhaps, is there a chance to switch to 1T somehow?


Hello. I see that you are using 4x8 FlareX as i do, and we have quite similar settings.

My setup is unfortunately not stable, but good enough for daily driving and a few games.

First of all, as you have an Asus board, and Zentimings cannot show vDimm voltage on them, what is your dimm voltage?

If your hwinfo-screenshot is from doing OCCT, i would say that your temperatures are fine. B-die should be kept under 40c.

I only have 2 tips, being a newbie myself. Set tCKE to 9, and change RTT/Park to 2. I was using 6/3/3 the latest 2 months and was thinking it was the best setting for me, but just a few days ago i changed to 7/3/2 and it improved stability without doubt.

Anyway, since you are stable, i do not think there is anything harmful with your current settings, as long as your dimm-voltage is below say 1.52.. RTT/Park 2 is supposed to make higher voltages safer.


----------



## mongoled

Veii said:


> You beat me on the score & with 75Mhz more sustained
> Can you check Tool.exe , and find your programmed ProcHot value ?
> 
> Voltage example, around 1.18-1.21 it needs for 4.6, but it thermal throttles
> View attachment 2514960
> View attachment 2514961
> 
> I feel like thermal throttling after 60c already , 65c is my programmed prochot
> Really need to run again 2100 FCLK not stay on 1900. Need to finish this Rev.E research finally, someday, soonTM


ProcHot is the same as your 65C.

I noted that both yourself and @PJVol are using ASRock motherboards and both of your HWInfo64 are showing substantially lower CPU VID than the MSI's myself and @craxton are using ...

I re-visited my load stable 4133/2067 settings with the "new" 1.2.0.3b BIOS for my motherboard but alas I am still getting WHEA 18s in idle with CO settings that are stable at 3800/1900.....


----------



## Veii

mongoled said:


> I re-visited my load stable 4133/2067 settings with the "new" 1.2.0.3b BIOS for my motherboard but alas I am still getting WHEA 18s in idle with CO settings that are stable at 3800/1900.....


The 1.2.0.3A++ or the real 1.2.0.3B 

I figured out what it was
Been running no CO values as it seems ~ as it barely can hold 4.8








The VIDs are sample exclusive
It can be influenced through boardpartner trickery with PBO and have "less droopy loadlines"
But even this one shows (can remember on CTR dynamic allcore that 1.375v was enough for 5ghz) ~ that it moves near the 1.27v mark

I don't want to give ASRock full credit as their bios is purely barebones, less than AMD even wants to publish ~ as if they remove intentionally features
But it has as close to no trickery in there. All trickery options are missing, CBS is tiny too
No telemetry faking, X1 scalar by default, nothing really ~ booring
But it does run stable, when it runs stable.
This means, when AGESA is not completely messed up , but you pay with 3-4 weeks longer wait-time till it's "good enough" to be released

EDIT:
That "Vcore" sensor never reported anything useful tho 
At least SOC and VCORE VRM (VR-OUT) are very accurate
EDIT2: and seems like i forgot to wipe the positive vcore offset








Then again, no VDIMM readout anywhere


----------



## mongoled

Veii said:


> The 1.2.0.3A++ or the real 1.2.0.3B


Who knows!

Its currently a hot topic 

😍 😍


----------



## Veii

mongoled said:


> Who knows!
> 
> Its currently a hot topic
> 
> 😍 😍


There is a "new" bios update
I have to downgrade in order to flashrom it
ASRock has annoying double license verification algorithms and refuses flashing updated bioses ~ no AMIFlash unless i could get a fake signing to pass (can't)








009 stayed for a long time - this one should be far newer (but just recently in 1203+++ implemented)
My only hope that L3 cache issues are virtualization issues
I really don't have high hopes for microsoft fixing the whole thread scheduler in 1 day (tomorrow is the MS event)

I think pure 1.2.0.3B was SMU 56.72?/74
72-75 somewhere there ~ lack more information
It certainly was a big jump from SMU 56.50 1202
Probably 1203A or non a should move in the 63-67 range, but the Patch B was something along 56.7x

EDIT:
This delayed microcode update, also should "fix" cache performance (already with Patch-C) - but i still think they had issues with PM-Table and "broken" SMU before
Need to play the testing rabbit and lose my bios profiles again, because of ASRocks useless Capsule CRC checks
Gigabyte fully blocks AMI-Flash (AFUWIN) soo they are not really better lol. Only on MSI it works flawlessly how it has to
* at least stasio gave a modified efiflash for downgrades. Yet from ASRock there is nothing. Unfortunate behavior


----------



## Takla

XPEHOPE3 said:


> Anyone knows what is the reason behind Aida64 varying latency between reboots?
> I measure in Safe mode without network drivers, but on one reboot I get e.g. 58.6-58.8 ns across 5 runs, on the other reboot I get 59.1-59.5 ns. But there are only those two types of "reboots", that is I never get other values for those settings.


I get 68.5ns after cold boot / when saving and exiting bios and 67.5ns after restarting. (C6H, 3900x & 3600CL16) I thing it is related to mainboard training. (I literally tried all AMD CBS settings on disabled/enabled, none of them changed this so it must be some hidden thing) I do not think it is a windows process that causes this difference.


----------



## dansi

may i know what is the L3 cache perfomance issues?


----------



## Veii

dansi said:


> may i know what is the L3 cache perfomance issues?











And visible on SiSoftware Sandra [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
Aside from that horrible result, it retains Single & Multicore Performance ~ soo games actually feel an improvement 
Yet it's only the buggy thread scheduler, which does suspend cores while they have load, but doesn't if they don't get load
* i didn't get any random reboot DF_C-State issues at all, soo it has potential

If i push load and then benchmark, my cache results can boost up to their 610+ values
Also this post








Introducing Windows 11:


I bet their goal with windows 11 will be to have an OS that runs well on mobile devices as well as normal PCs. They canceled windows 10X which was supposed to compete with chrome OS more directly and I suspect that's because they're building that kind of functionality into 11. 10 can run on arm...




www.overclock.net




Flickering fixed with "WDDM 3.0" aware drivers 470.25
Soo only the broken thread scheduler is an issue or rather the multi-layer kernel "virtualization" performance loss

Win 11 can run without any TPM or secureboot shenanigans , after you install it and pass microsoft's check
But it's something intentionally throttling Vermeer. Either microsoft is to blame or AMD who has a big bug with PSP Firmware and fTPM mode
The last thing that remains, is the "current" new microcode
Performance is great on it, even more on a cut down version ~ but this L3 throttle issue, is annoying  loses a lot of perf for "no reason"


----------



## PJVol

mongoled said:


> Your CPU is reporting substantially lower peak CPU VID values


You talking about those values, ignoring the temps, which is imho not correct. I cant reproduce your 74° CBR23 load atm, since ambient is ~33 now, and VID dropped even more.









But looking for old screens, I found one with Tctl 74°, VID's were in 1.240-1.260 range.
The issue with my CPU is that Core 3 which is the main "heater" in the whole V/F/T ecosystem )) Even with the curve offset, that will most likely crash in blender, it remains the hottest. But even then it managed not to dip below 12000 thanks to optimal curve preset.

PS: and btw, was your power telemetry always a bit off at 93% ?


----------



## sendap

Veii said:


> 4-4-18 is for 4000MT/s, 3-3-15 is for 3800MT/s
> tCKE 11 is for 4000MT/s, tCKE 9 is for 3800MT/s


3800 3-3-15 2T tCKE 9 stable
3800 56-56-56 1T tCKE 9 -> TM5 shuts down without any error message, stable with tCKE 11

Going to try to get 3-3-15 1T working next

how much more voltage is required switching from 2T to 1T? 1T 56-56-56 works without any voltage change (1.44 set 1.46 get)


----------



## mongoled

PJVol said:


> PS: and btw, was your power telemetry always a bit off at 93% ?


I know about the reading but only paid attention to it when it was first being discussed so cannot tell you if it has changed between different agesa versions or/if its consistent across reboots, changes in BIOS etc ....

Yes I see hot weather across Europe, join our club for hot weather (Cyprus)


----------



## PJVol

mongoled said:


> join our club for hot weather (Cyprus)


Yeah, I know ( the boss just got back from vacation from Cyprus and took the heat with him  ) .

PS: Looking at your screen with corecycler I saw why you've had high VIDs, lol.
Your CO +5 -3 -7 -6 +6 -9 vs. mine -15 -16 -18 -14 -7 -22



mongoled said:


> What voltage do you need to run Prime95 Small FFTs with AVX2 stable @ 4600 mhz ???


You mean fixed one?


----------



## XPEHOPE3

XPEHOPE3 said:


> so I used 3800-16 flat. And it ran worse than base until I changed procODT from 48 to 43.4. Then fine tuned VDDGs: CCD to 1018mV and IOD to 1100mV (EDIT: was 1020 by error). GET difference is more than 80mV, unlike if CCD set to 1020. I arrived at these results, which are not better than base latency-wise, but no other procODT/VDDGs values were better:
> 
> 
> Will see what TM5 would say. It's 28-33C here, hope memory won't burn 😇


Ok, that is TM5 and y-cruncher stable (two screenshots to record DIMM temps):


----------



## mongoled

PJVol said:


> Yeah, I know ( the boss just got back from vacation from Cyprus and took the heat with him  ) .
> 
> PS: Looking at your screen with corecycler I saw why you've had high VIDs, lol.
> Your CO +5 -3 -7 -6 +6 -9 vs. mine -15 -16 -18 -14 -7 -22
> 
> 
> 
> You mean fixed one?


Lucky BOSS

 

So what vCore do you need to run 4.6Ghz all core stable Prime95 FFTs with AVX2 ??

That should tell the real picture regards the differences between our CPUs and any possible manufacturer shinanigans.

Ive tuned my CO to be stable across all applications, would be a complete crash fest if I run such aggressive CO values.

I can run benchmarks with aggressive CO values, but for 24/7 stability the CO values I use are a requirement.


----------



## craxton

mongoled said:


> @craxton
> 
> Here you go, corecycler ...
> 
> View attachment 2514958
> 
> 
> @PJVol next ....
> 
> CB23
> 
> View attachment 2514959
> 
> 
> Your CPU is reporting substantially lower peak CPU VID values.
> 
> I know for a fact that my system needs 1.31x volts to be stable Prime95 Small FFTs (AVX2) @ 4600 mhz, it would be impossible for it to be stable with 1.21x volts at 466x mhz.
> 
> The information relayed for my setup falls in line with my expectations taking into account what Prime95 Small FFTs require.
> 
> No idea why your system relays such low CPU VID, what voltage do you need to run Prime95 Small FFTs with AVX2 stable @ 4600 mhz ???


while my chip uses less VID, i also get a "best" case 12001 score, and worst
119xx since having dialed in CO values.

(EDIT AGAIN) the CO values im running are 100% stable daily, havent had any crashes
even if i dont turn off C6 package i still have no issues just core cycler fails upon the 9th iteration or so on core 3

(youll have to show me what you mean with prime)
atm im unsure what you mean to select.
ill have to get back with this later today as work iis calling but
did you turn off package c6 state? as Veii showed? if i leave this on i dont pass Core-cycler.
i also just tried to run prime 95 with an all core oc i instantly hit 90c as i dont have any limits (none thats keeping temps in check)
for running such a demanding task. ill respond with what it takes later today.

if prime makes a "sound" and shows a core isnt running thats a fail correct? and 12 torture tests is what i should run?
atm running fine and dandy with my "auto" oc with the CO offset i found "stable" with core cycler.
















(this is what i have to set to pass) otherwise (core 3 (4 in bios) fails while all others pass


----------



## mongoled

craxton said:


> while my chip uses less VID, i also get a "best" case 12001 score, and worst
> 119xx since having dialed in CO values.
> 
> (EDIT AGAIN) the CO values im running are 100% stable daily, havent had any crashes
> even if i dont turn off C6 package i still have no issues just core cycler fails upon the 9th iteration or so on core 3
> 
> (youll have to show me what you mean with prime)
> atm im unsure what you mean to select.
> ill have to get back with this later today as work iis calling but
> did you turn off package c6 state? as Veii showed? if i leave this on i dont pass Core-cycler.
> i also just tried to run prime 95 with an all core oc i instantly hit 90c as i dont have any limits (none thats keeping temps in check)
> for running such a demanding task. ill respond with what it takes later today.
> 
> if prime makes a "sound" and shows a core isnt running thats a fail correct? and 12 torture tests is what i should run?
> atm running fine and dandy with my "auto" oc with the CO offset i found "stable" with core cycler.
> View attachment 2514986
> View attachment 2514987
> 
> 
> (this is what i have to set to pass) otherwise (core 3 (4 in bios) fails while all others pass
> View attachment 2514988


Ive got a thread open discussing stuff that is way more relevant than what we are discussing here

Guide - Fully optimise your PBO | Overclock.net

To answer your question, your first screenshot is correct, I dont advise running this for too long unless your cooling can handle it.

I have not disabled any C-states everything is on AUTO.

Yes, sound indicates dropped core.

I was using Prime95 Small FFTs as a baseline to get a frequency/vcore capability, thats all, for my Prime95 Small FFT testing I dont leave much longer than a couple of hours.


----------



## XPEHOPE3

Takla said:


> I get 68.5ns after cold boot / when saving and exiting bios and 67.5ns after restarting.


I haven't found any dependency on whether I get variance from after exiting BIOS or just reboot. But never tested from cold boot.


mongoled said:


> Use it for diagnostic purposes, i.e. to compare latency between subtle changes and thats all.
> ...
> but to post AIDA64 screenshots in safe mode/diagnostic mode for eeeeepeeen, well that is lame


That's what I used Safe mode for. Screens posted only as reference and discussion (also together with screen from normal-booted Windows).


Veii said:


> Crush = crash ?


Meh, another misprint =/
"crash" of course, sorry.



Veii said:


> Stop using Safe-Mode
> it's cheating and hiding things
> Powermanagement is disabled
> WMI links are disabled
> CPPC is disabled


Yeah, I figured it's not the same powering-wise. But I had no other way to lower variance to guide my choices. Also the bump was even higher in normal boot. And setting procODT to 43.4 made bump worse, while on 3800-16 with FCLK 1900 that change made improvements.



Veii said:


> But all this expects a clean OS


Well, all my posts were made regarding my clean install. It only has all updates, NVIDIA drivers, Firefox, Total Commander, benchmarking & stresstesting software (incl. WSL 2 + GSAT), and Steam (for 3D Mark). Nothing of that is in autostart apart from GeForce Experience. OneDrive is also in autostart, but I close it before tests, set Powerplan to Performance and disable background malware detection.
So I'd say my Windows is clean (in tech support meaning of "original with little to no interference with it"). And your Windows is stripped down 😅 So I guess your real claim is that >0.3ns Aida64 variance surely means memory instability on a very stripped down Windows install.



Veii said:


> 0.3ns = instability or other strangeness (for example buggy enabled DF-C States)


I too have that problem with DF states: disabled in BIOS, CPPC both setting enabled in BIOS, yet ZenStates reports all three ticks set. Disabling Package-C6 and clicking Apply, and then exiting ZenStates and rerunning Aida *never* made a difference.


Veii said:


> Soo i put the thread scheduler to background services


Whaaaaat? How is that making Aida run better if it's not a background process? Background processes would only be more likely to interrupt the tests.


Veii said:


> Maybe you haven't read this whole thread


The post you linked I've read for sure, voltage recommendations from there were changed to 900-1020-1100 by you here. The rest of the thread I haven't read yet. Thought it was only about max voltages which I'm not really interested in as I'd try not to push limits to try to be stable across AGESA updates, but no, that thread is also about lots of other things 


Veii said:


> Memory latency will be "the same" or "higher" if the CPU starts to autocorrect FCLK ~ the bump will be strongly noticeable
> _This is where you adjust SOC & the 1.8v rail to get the lowest result possible_


Well, that's not what you wrote originally 


Veii said:


> GDM off first, TM5 stable / later aida64 baseline screenshot
> 1900FCLK post, checking Aida64 run if it's better than the early screenshot. *Adjust VDDG and procODT till it's better* / then TM5 stable + y-cruncher afterwards
> lower SOC , set 1.8v rail to 1.83v or 1.85v (better 1.83v) and lower SOC + VDDG till you hold the 40mV stepping (can be double 40mV) / that you test y-cruncher stable but first see if you improve in Aida64 (memory latency or write bandwidth loss is unforgiving & a sign of autocorrection)


Originally you wrote to use only procODT and VDDG to tame FCLK autocorrection latency bump _completely_. Now I guess I need to combine 2nd and 3rd bullets and aim for as best results as possible with FCLK 1900, MEMCLK 1800. FCLK 2000 I don't think I'll go for because I wasn't able to post with MEMCLK higher than 1933 on previous BIOS. So do you think one needs to tighten the timings only after (s)he hits FCLK(=MEMCLK) wall? I think stability-wise 1900 FCLK is much easier than 1933 for my setup.



Veii said:


> Or a least a daily OS with many Microsoft Spyware Services disabled


Oh, *another *rabbit hole to dive in! Would it be possible to *safely *reenable everything after I'm done OCing? I believe those scripts might cause dreaded issues with OS updates. Or do you just reinstall Windows after you done OCing?
So you set thread scheduler to level field with Aida and background services, but then you just remove most of the background services. Isn't it possible to just set Aida priority to realtime that other processes can't interfere?


----------



## Veii

sendap said:


> how much more voltage is required switching from 2T to 1T? 1T 56-56-56 works without any voltage change


56 is nearly full 2T, no wonder it doesn't require anything 


sendap said:


> 3800 3-3-15 2T tCKE 9 stable
> 3800 56-56-56 1T tCKE 9 -> TM5 shuts down without any error message, stable with tCKE 11


This part is interesting
Haven't seen tCKE difference between 1T and 2T - they both align
but setting setup timings shift it that much to be a full 200MT/s difference, is abstract to say at least
Curious if it would function with 1T

Keep in mind, RTT_WR which is dynamic, and SETUP times, which are fixed frequency based ~ don't go well together
tCKE is "kind of dynamic". It's moving and adjusting independently like RTT_WR is, but triggers at constant set intervals ~ unlike RTT_WR which is fully dynamic
And SETUP times which are fully constant with in/out

tCKE + WR + SETUP, do not work well
i could/can align both , tCKE and SETUP - to simulate "a more accurate" Dynamic ODT (RTT_WR)
but it adds latency
While RTT_WR i haven't seen does any harm ~ never seen negative effects, but fully breaks SETUP Timings

Probably it's again the same A+B thing
only 2 things work together
tCKE which is powerdown but rather aggressive powerdown (enforced)
RTT_WR which is dynamically shifting/moving the signal back and forth to increase Data-Eye size + also can "create/adapt" for one piece of the CKE signal, either dynamic CKE HIGH or dynamic CKE LOW (meaning you disable one RTT (NOM or PARK) if you use WR

But this then means, that you have time it perfectly
tCKE needs to be correct and tFAW will start to play a role ~ also this new BURST REFRESH override AMD implemented
(Urgent & SubUrgent Refresh intervals & kill intervals = tCCD_L or tBURST based to what i figured ~ only that tBURST is now "adaptive"? and user changable)















^ MemTweakIt_12-22.exe maker shamino 
Can maybe read out Aggressive Powerdown and Normal Powerdown + this abstract thing

Anywho, i think this piece of information is important
A+B,

CKE+SETUP
CKE+RTT_WR
Only RTT_WR
Only SETUP & full powerdown (no tCKE = 1)
one of these works
first one is probably the hardest to align
RTT_WR has only 3 stages and tCKE is frequency based (trial and error)
CKE & SETUP both being frequency based, has 2 stages of variables, while one stage has 3 stages of variables and combinations 

=================================

Microcode 0A201016h,

works on SMU 56.50, has no requirement for 56.53+
Is implemented with all 1203A++ to the infinite, bioses
did nothing to powertable or boosting behavior, nothing to DPM or LCLK behavior, can not see any IMC FW issues
(unlike SMU 56.45+ did with randomly added BURST REFRESH override ~ dynamic so to speak)

no changes in cinebench, cpu-z, aida64 (sadly) and no changes in SiSandra (i think, changes are just my CO)
@mongoled back to being "equal" again ~ with my negative CO
You still win , but i need to get 2100 to work on Rev.E
















SiSandra shows an Improvement, but i don't think it has anything to do with the microcode at all
Just happy to share the result. I think it's "alright" as 9.7-



















Spoiler: Result Detailed






Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 83.8GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 19.9ns (9.7ns - 22.1ns)
Inter-Thread (same Core) Latency : 9.8ns
Inter-Core (same Module) Latency : 20.9ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 7GB/s
No. Threads : 12
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 65.00W
Aggregate Inter-Thread Bandwidth : 1320.28MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.06ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 554.34kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 17.69MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.04ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11
U0-C0T0 <> U2-C1T0 Data Latency : 21.8ns
U0-C0T0 <> U4-C2T0 Data Latency : 21.4ns
U0-C0T0 <> U6-C3T0 Data Latency : 20.8ns
U0-C0T0 <> U8-C4T0 Data Latency : 20.8ns
U0-C0T0 <> U10-C5T0 Data Latency : 20.5ns
U0-C0T0 <> U1-C0T1 Data Latency : 9.8ns
U0-C0T0 <> U3-C1T1 Data Latency : 20.7ns
U0-C0T0 <> U5-C2T1 Data Latency : 21.2ns
U0-C0T0 <> U7-C3T1 Data Latency : 20.7ns
U0-C0T0 <> U9-C4T1 Data Latency : 20.9ns
U0-C0T0 <> U11-C5T1 Data Latency : 20.4ns
U2-C1T0 <> U4-C2T0 Data Latency : 21.0ns
U2-C1T0 <> U6-C3T0 Data Latency : 21.4ns
U2-C1T0 <> U8-C4T0 Data Latency : 20.7ns
U2-C1T0 <> U10-C5T0 Data Latency : 20.9ns
U2-C1T0 <> U1-C0T1 Data Latency : 20.7ns
U2-C1T0 <> U3-C1T1 Data Latency : 9.8ns
U2-C1T0 <> U5-C2T1 Data Latency : 20.5ns
U2-C1T0 <> U7-C3T1 Data Latency : 21.4ns
U2-C1T0 <> U9-C4T1 Data Latency : 20.5ns
U2-C1T0 <> U11-C5T1 Data Latency : 20.7ns
U4-C2T0 <> U6-C3T0 Data Latency : 20.7ns
U4-C2T0 <> U8-C4T0 Data Latency : 22.0ns
U4-C2T0 <> U10-C5T0 Data Latency : 21.1ns
U4-C2T0 <> U1-C0T1 Data Latency : 21.3ns
U4-C2T0 <> U3-C1T1 Data Latency : 20.7ns
U4-C2T0 <> U5-C2T1 Data Latency : 9.8ns
U4-C2T0 <> U7-C3T1 Data Latency : 20.7ns
U4-C2T0 <> U9-C4T1 Data Latency : 22.1ns
U4-C2T0 <> U11-C5T1 Data Latency : 21.1ns
U6-C3T0 <> U8-C4T0 Data Latency : 20.9ns
U6-C3T0 <> U10-C5T0 Data Latency : 20.8ns
U6-C3T0 <> U1-C0T1 Data Latency : 20.7ns
U6-C3T0 <> U3-C1T1 Data Latency : 21.3ns
U6-C3T0 <> U5-C2T1 Data Latency : 20.5ns
U6-C3T0 <> U7-C3T1 Data Latency : 9.7ns
U6-C3T0 <> U9-C4T1 Data Latency : 20.5ns
U6-C3T0 <> U11-C5T1 Data Latency : 20.8ns
U8-C4T0 <> U10-C5T0 Data Latency : 20.8ns
U8-C4T0 <> U1-C0T1 Data Latency : 20.9ns
U8-C4T0 <> U3-C1T1 Data Latency : 20.5ns
U8-C4T0 <> U5-C2T1 Data Latency : 21.8ns
U8-C4T0 <> U7-C3T1 Data Latency : 20.4ns
U8-C4T0 <> U9-C4T1 Data Latency : 9.8ns
U8-C4T0 <> U11-C5T1 Data Latency : 20.7ns
U10-C5T0 <> U1-C0T1 Data Latency : 20.5ns
U10-C5T0 <> U3-C1T1 Data Latency : 20.9ns
U10-C5T0 <> U5-C2T1 Data Latency : 21.1ns
U10-C5T0 <> U7-C3T1 Data Latency : 20.9ns
U10-C5T0 <> U9-C4T1 Data Latency : 20.8ns
U10-C5T0 <> U11-C5T1 Data Latency : 9.7ns
U1-C0T1 <> U3-C1T1 Data Latency : 21.0ns
U1-C0T1 <> U5-C2T1 Data Latency : 21.3ns
U1-C0T1 <> U7-C3T1 Data Latency : 20.6ns
U1-C0T1 <> U9-C4T1 Data Latency : 20.9ns
U1-C0T1 <> U11-C5T1 Data Latency : 20.5ns
U3-C1T1 <> U5-C2T1 Data Latency : 21.0ns
U3-C1T1 <> U7-C3T1 Data Latency : 21.3ns
U3-C1T1 <> U9-C4T1 Data Latency : 20.5ns
U3-C1T1 <> U11-C5T1 Data Latency : 20.8ns
U5-C2T1 <> U7-C3T1 Data Latency : 20.6ns
U5-C2T1 <> U9-C4T1 Data Latency : 21.8ns
U5-C2T1 <> U11-C5T1 Data Latency : 21.0ns
U7-C3T1 <> U9-C4T1 Data Latency : 20.8ns
U7-C3T1 <> U11-C5T1 Data Latency : 20.7ns
U9-C4T1 <> U11-C5T1 Data Latency : 20.8ns
1x 64bytes Blocks Bandwidth : 9GB/s
4x 64bytes Blocks Bandwidth : 12.63GB/s
4x 256bytes Blocks Bandwidth : 36.79GB/s
4x 1kB Blocks Bandwidth : 139.87GB/s
4x 4kB Blocks Bandwidth : 202.23GB/s
16x 4kB Blocks Bandwidth : 315.77GB/s
4x 64kB Blocks Bandwidth : 390.78GB/s
16x 64kB Blocks Bandwidth : 332.53GB/s
8x 256kB Blocks Bandwidth : 351.2GB/s
4x 1MB Blocks Bandwidth : 319GB/s
16x 1MB Blocks Bandwidth : 17.4GB/s
8x 4MB Blocks Bandwidth : 12.77GB/s

Benchmark Status
Result ID : AMD Ryzen 5 5600X 6-Core Processor (6C 12T 4.85GHz, 1.9GHz IMC, 6x 512kB L2, 32MB L3)
Microcode : A20F10-1016
Computer : ASRock B550 Phantom Gaming-ITX/ax
Platform Compliance : x64
No. Threads : 12
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 5 5600X 6-Core Processor
URL : https://www.amd.com
Speed : 4.85GHz
Min/Max/Turbo Speed : 2.2GHz - 3.7GHz - 4.85GHz
Cores per Processor : 6 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1016
Latest Version : A20F10-16
L1D (1st Level) Data Cache : 6x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 6x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 6x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 65.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 229 : CPU microcode update available. Check for an updated System BIOS with updated microcode.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.




* i want to get all of them sub 20ns 

The only really interesting thing here is,
There is supposed to be "another microcode" out in the wild.
One that is/hasn't been supplied as A20F10-1016 mid April (1203) update, but yet has been logged into the database
* I'll probably figure it out, so far it did "nothing" visible ~ maybe some new sensors after 1203B


----------



## Veii

xpehope3 said:


> So I'd say my Windows is clean (in tech support meaning of "original with little to no interference with it"). And your Windows is stripped down 😅 So I guess your real claim is that >0.3ns Aida64 variance surely means memory instability on a very stripped down Windows install. So I'd say my Windows is clean (in tech support meaning of "original with little to no interference with it"). And your Windows is stripped down 😅 So I guess your real claim is that >0.3ns Aida64 variance surely means memory instability on a very stripped down Windows install.


Although i can not find your comment anymore (has been filtered ?) still want to answer ~ as i've read the whole post
Do not mistake "cleaned" with "str*pped-down" (word filter?)
And please try to find a line between "disabled unnecessary" vs "wiped to bare minimum function like safe mode"

Both later parts do not apply to me
~ You can remove couple of unnecessary modules, like TabletPC support, Candy Crush, OneDrive, MS Edge, Mobile Data & Language Packs
Such things do not influence the integrity or health of the original iso, but just slimm down it's storage footprint
~ You can disable part of the listed now & listed on the post before, dll's which also run their own updater services ~ to wipe them from the task and service log of windows. This free's idle processes and yet doesn't interrupt any of the OS functionality or integrity

You can do quite a few things to be honest, by the huge amount and size of how Windows 10+ got bloated after Windows 7
Starting from sys32 /drivers / etc/ hosts file edit to block IPs, towards using an organisation profile forbidding windows to override their spying data triggers/buttons (wpd.app or o&o shutup-tool)

It's kind of an art, to clean it ~ by the deep rabbit-hole of mess it became (without breaking anything or filling your error log)
But there is the difference
I daily these things. There is zero interest in XOC and zero interest to show-off if not earned by hard work.
It will teach nobody if the results are fake and only burn the reputation of this "nobody" 
No, i do not stripe down core functionality ~ and what is disabled or put on manual autostart, won't come back or bite me in the back by not functioning
At least to the extend i use currently and phrased on the post as "advice"

Open alone "autoruns64" by microsoft
This list once had 40 entries near 20H1, now it has 200+ and at least 6 of them are flagged by virustotal
Suspicion aside, it's too much bloat
Even licensed ProWorkstation which is cleaner, still has some bloat in there
Same for this Win11 "cleaned" installation. It's online features are functional if i ever need them, but why should i run more resource hogging things 
No need for random MS account synching or a onedrive i don't use
No need for randomly "always running" ms-edge updaters or chrome + skype UWP app updater services
And yet the safe-mode performs worse than the "live running" OS , for me 

You want to get down to 68 processes active, but my current best and since 21H1 , is around the 80-85 mark
Too much split-service bloat came in, that needs to be running for daily OS operation















This is as best as it get's (on the right)
But my mouse.dll, windows update orchester, wifi connectivity, nvidia display containers, screenshot tool, global system FPS cap (RTSS)
All take processes
These 68-69 processes are never reachable again without breaking core functionality
But really it's as best as i can manage it for now

Oh DF_C-States doesn't break apparently on Win11 thread scheduler
Soo we'll see for how long this can keep up without random reboots 
=========
About the Background Tasks focus question,
It's easier that way
Things that have to take resources, do take resources
And show if something is off or runs
Win 11 notifies you on new autorun programms that add themself there & generally i always was doing it this way

Else it slows down tabbed out programs & sometimes i really don't want that 
Just a multi-tasking tweak, with positives and negative effects (if you don't maintain your OS)


----------



## XPEHOPE3

Veii said:


> Adjusting VDDP, VDDG and SOC
> but *first *find "the working" procODT which gives less to non variance
> You can mostly boot 3 different ones, but only one is correct
> It does change by voltages (lower voltages lower procODT) , soo focus on lowering voltages *first *till y-cruncher just dies out



You are saying "first" to both procODT and voltages creating a circle dependency. Can I decipher it to this?

Lower VDIMM/VDDP/VDDG/VSOC first, for 1-CCDs: until write bandwidth stops increasing, check if y-cruncher dies out after 4 full iterations
Search for procODT (+-1 setting from current) to see if there is improvement
Adjust only VDDP, VDDG and SOC for more improvement
Check y-cruncher
Or is that circle dependency meant to be? That is, to overcome variance overclocker has to just fiddle with everything (VDIMM/VDDP/VDDGs/VSOC/procODT) in Brownian fashion 🤣 until write bandwidth/latency stop improving or y-cruncher starts crashing or, more likely, overclocker runs out of time.


----------



## XPEHOPE3

Veii said:


> Although i can not find your comment anymore (has been filtered ?)


yeah, some of my long posts become filtered if I edit them afterwards (not because of word filter). I already told moderator about it...
Thank you for response!


----------



## Veii

XPEHOPE3 said:


> 1. Lower VDIMM/VDDP/VDDG/VSOC first, for 1-CCDs: until write bandwidth stops increasing, check if y-cruncher dies out after 4 full iterations


VDIMM can make dimms crash, testing takes too much time - soo maybe skip this
Remain ones all have a connection, but you do 1. at the start and at the end when everything is stable ~ till results do not improve anymore but only get worse


XPEHOPE3 said:


> 2. Search for procODT (+-1 setting from current) to see if there is improvement


this is also work for 1.) but only after you have something stable. Any random procODT can most of the times work and reach "stability" even with a lot of autocorrection users barely nottice


XPEHOPE3 said:


> 3. Adjust only VDDP, VDDG and SOC for more improvement


3. is mid-work. It's not a required entry. 900mV cLDO_VDDP always works, but you can try to lower CPU_VDDP further and this one, to help with lower procODT
Lower procODT will help in reaching higher FCLK overall


XPEHOPE3 said:


> 4. Check y-cruncher


Only if Aida64 result is favorable and you know that it can not be a timings issue (no timings change on this boot-tests)
After y-cruncher, verify with OCCT Extreme , then when Aida64 doesn't improve, focus on timings or focus on Curve Optimizer ~ till one of both do not improve

Wrote an order at first, how i do it ~ in short
Everyone has own testing methods, there is no "rule"
I just don't want to waste "already taking enough" time, with bruteforce possibilities ~ soo if Aida64 doesn't improve or CPU-Z doesn't improve. Quick fast benchmarks
Then it is not worth my time and i'll change bigger things

If X change doesn't show, it doesn't mean it's not working tho
Revisiting "unknown changes" options, always is a good idea later
1.8v rail differences we [OCN] figured makes a difference only later, but not at the start
I worked without touching it ~ it always was at 1.83, butt did not see at the start differences between 1.9 or 1.8
Same for CPU_VDDP,, no difference only later beyond 2067 FCLK it started to matter a bit
Also same for tCKE. Did not touch it, till PCBs started to crash and i had to so something against it
I can not replicate, explain the order. Everyone has their own methods


Veii said:


> 3. is mid-work. It's not a required entry. 900mV cLDO_VDDP always works, but you can try to lower CPU_VDDP further and this one, to help with lower procODT
> Lower procODT will help in reaching higher FCLK overall


still haven't gone that path,
2167 FCLK is higher in the priority listt , and before that is getting tRCD 18 on 4000 to work on Rev.E , instead of 19 ~ or CL12 stable not 13
Many other things have higher priority ~ like finding a Matisse CPU to get Thunderbolt 4 to work better (2nd pc) or writing ACPI/machine code-table for macOS hackintoshing & get it there setup

At least 10+ work in progress projects ,
This 3.) can wait , there is not much pressure bellow 49ns for now & bios updates are booring


----------



## XPEHOPE3

Veii said:


> Perfect half for 3600MT/s (1800FCLK) = 28800MB/s
> Take 1mb/s away for the OS kernel, 28799MB/s write ~ is your target
> ~ only hit once in a blue moon perfect perfect half, but 1 off is good enough
> 
> Write for 1800FCLK needs to be perfect half (-1), else you are autocorrecting & FCLK throttling slightly (bigger in your case)


I think I know where my write bandwidth comes from! From CPU FSB not being equal to 100. NB frequency 1796,8 means FSB = 1796,8/18 ~ 99,8(2). An expected write bandwidth is 1796,8*16 = 28748,8. Displayed is 28757 because I screenshot only the last of the measurements while NB freq field gets populated only for the first measurement.


----------



## sendap

Veii said:


> This part is interesting
> Haven't seen tCKE difference between 1T and 2T - they both align
> but setting setup timings shift it that much to be a full 200MT/s difference, is abstract to say at least
> Curious if it would function with 1T
> 
> Keep in mind, RTT_WR which is dynamic, and SETUP times, which are fixed frequency based ~ don't go well together
> tCKE is "kind of dynamic". It's moving and adjusting independently like RTT_WR is, but triggers at constant set intervals ~ unlike RTT_WR which is fully dynamic
> And SETUP times which are fully constant with in/out
> 
> tCKE + WR + SETUP, do not work well
> i could/can align both , tCKE and SETUP - to simulate "a more accurate" Dynamic ODT (RTT_WR)
> but it adds latency
> While RTT_WR i haven't seen does any harm ~ never seen negative effects, but fully breaks SETUP Timings
> 
> Probably it's again the same A+B thing
> only 2 things work together
> tCKE which is powerdown but rather aggressive powerdown (enforced)
> RTT_WR which is dynamically shifting/moving the signal back and forth to increase Data-Eye size + also can "create/adapt" for one piece of the CKE signal, either dynamic CKE HIGH or dynamic CKE LOW (meaning you disable one RTT (NOM or PARK) if you use WR


been reading it three times. Great information! Still a bit confused about the last paragraph 

So tried to run 1T without the 56-56-56 trickery and to my surprise I found a TM5 stabel (25 cycles 1UsmusV3) setting. 
Interestingly i see no difference in Bandwith comparing 56-56-56 to 0-0-0. So there might be something still a little off (no clue how to tackle that).
I had the feeling that 0-0-0 also was a bit more jumping around on latency. I tried in diagnostic mode (only 45 instead of 120 background processes). At first a little jumping but then constant results while hitting the Latency Box twenty times in a row (feeling like a monkey) of 52.3 to 52.5ns. Which is subtle improvement of 0.2ns to the 56-56-56 setup


----------



## DeletedMember558271

sendap said:


> been reading it three times. Great information! Still a bit confused about the last paragraph
> 
> So tried to run 1T without the 56-56-56 trickery and to my surprise I found a TM5 stabel (25 cycles 1UsmusV3) setting.
> Interestingly i see no difference in Bandwith comparing 56-56-56 to 0-0-0. So there might be something still a little off (no clue how to tackle that).
> I had the feeling that 0-0-0 also was a bit more jumping around on latency. I tried in diagnostic mode (only 45 instead of 120 background processes). At first a little jumping but then constant results while hitting the Latency Box twenty times in a row (feeling like a monkey) of 52.3 to 52.5ns. Which is subtle improvement of 0.2ns to the 56-56-56 setup
> 
> View attachment 2515017
> View attachment 2515018


Yea you only really need setup timings for 4x8GB, haven't seen anyone running 1T GDM Off without them.
This is the best I mine can do at 1.45v, since 1933+ WHEAs and 1900 doesn't boot.















Been thinking about if it's worth an RMA for one that boots 1900, not sure what I'd even tell AMD is wrong though, as they probably wouldn't accept if I told them that was it.
Definitely only worth if they cross-ship as I'm not going possible weeks without my PC, and with my luck probably get another one that doesn't boot 1900 or is one of those gimped dual CCD 5800x's or one that just overclocks significantly worse.
Still haven't seen anyone manage to solve the FCLK holes.

Also seems to have been quiet with no progress on the WHEAs above 1900, with regards to solving them or finding out what is causing them.
Nobody has gotten a new motherboard that has solved their WHEAs? Or caused them to appear as I thought @craxton was going to do?
Cause supposedly with some motherboards Veii and others have, if all of us with WHEA sent them our CPUs to test on them, they wouldn't have WHEA anymore. But we still don't know that for sure, or maybe at all really. Or if it's CPU related. I want to see the same CPU have WHEA in one motherboard and not in another, and then that motherboard should be good and WHEA free for everyones CPU's if it's just the motherboard that's ever the issue, and that motherboard with WHEA should have WHEA for everyone and every CPU.

Or maybe it's all just some stupid reporting error somehow everyone is overlooking, as in it's just not getting reported for some people for some reason even though the issue is still there. Cause you can just ignore the WHEA/disable it without fixing whatever the issue actually is and get the same performance and results as these people that never got the reports, they don't have any advantage which is strange to me. Until anyone actually knows what is causing it... which doesn't seem like that's ever going to happen here

The cause of WHEAs and FCLK holes and how to fix them will always be a mystery


RonLazer said:


> For anyone invested in this saga, sadly Asus's "Promontory Presence" doesn't actually do what it says in the BIOS and disable the Southbridge (aka the chipset). I'll email their support and see what's up with that. Sadly no way to test if these WHEA 19s are caused by a motherboard component or the CPU for now.
> 
> If I can find a way to disable the chipset then I should be able to test this as I've checked the Dark Hero block diagram and the 1st PCIE slot, 4 USB ports, and the 1st M.2 slot all connect directly to the CPU, so its very possible to run an OS with most of the motherboard disabled - and there's no way for any LAN components to interact with the CPU without going via the chipset.


Real shame this didn't work out to shed some light on anything
And @Veii / @ManniX-ITA never tried/made the modded BIOS to disable Realtek and see if that did anything, and USB ethernet adapters instead.
All investigation is just dead and given up, weird for this forum
But I guess we already know there's people that have Realtek that don't have WHEA and people that don't have Realtek that do have WHEA, so that can't be it.
Still would've been interesting to see if it possibly somehow did anything


----------



## XPEHOPE3

pipeclock said:


> Try the Diagnostic mode instead. Search > msconfig > diagnostic mode > restart.


Did you actually try it yourself on Windows 10 with PIN login?


----------



## pipeclock

XPEHOPE3 said:


> Did you actually try it yourself on Windows 10 win PIN login?


I don´t have set a pin neither password for login, so no.


----------



## Art385

mongoled said:


> English is fine
> 
> 
> 
> Very good data and very good thought process to follow this line of investigation.
> 
> The only "issue" is do you see what you have described above to be consistent across reboots ?
> 
> As thats my main gripe after thinking ive got Ryzen 5000 series "worked out" the characteristics are not the same across multiple reboots....
> 
> For whats its worth, I thought that pushing my assigned good cores to + CO values was going to have a negative effect on my CB23 scores and it did when I first tested it, but after a reboot the scores were where they should be so I kept my CO values that are tried and tested for the max boost override that can be run on later BIOS, that is 200 mhz ...
> 
> 
> They dont differ much but the difference in wattage is quite substantial !
> 
> 
> I will look into this and investigate my system to see if I can spot where the difference in wattage is coming from ...
> 
> 
> Yup, based on the lowest possible, just like you did before, good luck!
> 
> 
> 
> 
> Thanks for the screenshot, your temps were lower in this run (77C vs 80C) 3C will definatly make a difference on the score


Yes it's consistent as it tamed boosting with CO and drops in voltages. CPU was always stable week worth of testing. Funny thing is that after flashing A72 bios with this AGESA 1.2.0.3B that is A patch Curve Optimizer behaves quite different. Before if I set negative offset my voltages would drop lower and lower whereas clock would boost higher and higher. So getting that sweet spot was real pain. On this new beta voltages per core looks like fixed  and took from FIT or somewhere. Now every core use specific voltage range. One will use 1.33-1.35v and other will use 1.41-1.43 and decreasing negative offset will only rise clocks and do nothing to voltages - tested on Scalar x1. This is really great as setting Curve optimizer now is quite straight forward as you don't need to take voltage drop into account though CPU is tad hotter as some cores in ST load will not go below 1.4v but also I've managed to squeeze more performance out of it on ST and MT. So I'm really happy


----------



## XPEHOPE3

pipeclock said:


> I don´t have set a pin neither password for login, so no.


Well you better don't ))
Lost several hours: going for diagnostic login in msconfig when PIN login is set up triggers "Something happened to your PIN" login loophole on Windows 10. Also solution here.


----------



## craxton

Veii said:


> nvidia display containers,


you can kill this in the dropdown arrow in task bar, then kill display container LS
in task man, then the other and shut all Nvidia services off to run benchmarks "ON CORE" side.



Veii said:


> windows update orchester


can shut this off to for benchmark purposes or at least i do.



Veii said:


> screenshot tool,


(use windows built in hitting windows key + print screen


----------



## CarnageBT

Interesting RttPark findings.... What does it mean? @Veii 

Seems multiple values work. 7/3/6, RttPark 6, lasted the longest. If I can make multiple values work, should I try for a weaker RttPark (higher divider), as preferrable?


ProcODT7/3/36 cycles, no errors, had to stop test7/3/37 cycles, 45m, error 13, 13, 13, 13 (lower vdimm?)7/3/3, 1.48 vdimmtesting soon7/3/4cycle 1, 6m, error 17/3/5cycle 4, 24m, error 7 (max dimm temp 47.8)7/3/6Cycle 16, 1h37m, error 6 (RTT values or +1 vdimm) max temp 48c7/3/6, 1.49 vdimmtesting soon7/3/7Cycle 6, 37m, error 1,8 (together)7/3/2Cycle 3, 16m, error 13, Cycle 6, 37m, error 1 (max temp 48c), total time 58m


----------



## Veii

Dreamic said:


> And @Veii / @ManniX-ITA never tried/made the modded BIOS to disable Realtek and see if that did anything, and USB ethernet adapters instead.
> All investigation is just dead and given up, weird for this forum
> But I guess we already know there's people that have Realtek that don't have WHEA and people that don't have Realtek that do have WHEA, so that can't be it.
> Still would've been interesting to see if it possibly somehow did anything


Not dead, and not forgotten
Just lack of knowledge to modify bioses on my side (can't sign them) ~ and lack of skill to resolder 1.2mm SPI probes again , in order to experiment on the ASRock board (mini SPI)
Lack of time, having to focus 95% on building small little systems for broadcasters in order to pay the rent.
And the focus shifted to other priorities, considering this tool exists








WHEAService, WHEA errors suppressor - unleash Ryzen...


Doesn't work with Windows 11 Either it's a bug, I have reported it, or Microsoft decided for you that is better you always get WHEA whatever you like it or not (more likely this one) Due to the high number of WHEA errors clogging the system, running a Ryzen with high FCLK incurs in a...




www.overclock.net




Maybe if i get later a clients CPU here, i can verify it's WHEA free too ~ so far can only verify WHEA free, unless i strongly & intentionally make a mess ~ to get a #19

Buying 2nd hand stock, binning and reselling them here as WHEA-Free packages ~ would also have a sort of scalpers taste to it
But potentially a possibility to think about 😐


Art385 said:


> Yes it's consistent as it tamed boosting with CO and drops in voltages. CPU was always stable week worth of testing. Funny thing is that after flashing A72 bios with this AGESA 1.2.0.3B that is A patch Curve Optimizer behaves quite different. Before if I set negative offset my voltages would drop lower and lower whereas clock would boost higher and higher. So getting that sweet spot was real pain. On this new beta voltages per core looks like fixed  and took from FIT or somewhere. Now every core use specific voltage range. One will use 1.33-1.35v and other will use 1.41-1.43 and decreasing negative offset will only rise clocks and do nothing to voltages - tested on Scalar x1. This is really great as setting Curve optimizer now is quite straight forward as you don't need to take voltage drop into account though CPU is tad hotter as some cores in ST load will not go below 1.4v but also I've managed to squeeze more performance out of it on ST and MT. So I'm really happy


Can you check if your microcode is the new 1016h ?
There where not many updates between 1202 and 1203 (SMU wise, except for the USB focus) and bit of DPM focus (PCIe/IO stability)










CarnageBT said:


> Interesting RttPark findings.... What does it mean? @Veii
> 
> 
> 
> CarnageBT said:
> 
> 
> 
> 7/3/36 cycles, no errors, had to stop test7/3/37 cycles, 45m, error 13, 13, 13, 13 (lower vdimm?)7/3/3, 1.48 vdimmtesting soon
Click to expand...










Makes sense to me 
Sounds like a crash with too high voltage - or too low RTT_NOM
Lowering voltage and increasing ClkDrvStr . Or keeping voltage and decreasing ClkDrvStr
NOM / 6 shouldn't be needed that early, probably around the 1.56v+ range only


CarnageBT said:


> 7/3/4cycle 1, 6m, error 1











would've been good to keep it longer running. Single errors not always show the whole picture


CarnageBT said:


> 7/3/5cycle 4, 24m, error 7 (max dimm temp 47.8)











Looks like it keeps improving.
Soo low RTT_PARK divider, certainly ment PCB crashes. Else higher ones wouldn't be able to post at all (if they where wrong)
Strangely you still have a high temp on them ~ maybe RGB heatup ?
Don't want to think how hot they have been on /2 or /3


CarnageBT said:


> 7/3/6Cycle 16, 1h37m, error 6 (RTT values or +1 vdimm) max temp 48c


This surely was an improvement, but can now be full crashes or FCLK issues too
Stay on /6 i'd say
But likely procODT needs a change now or ClkDrvStr needs a change
You can try if 636 would do anything ~ tho that set was mostly only for 2 dimms


CarnageBT said:


> 7/3/7Cycle 6, 37m, error 1,8 (together)


Like above #7 picture showed , 1-8-8 likely is lack of ClkDrvStr, and it makes sense to me ~ as RTT_PARK is "too low" now for them
Probably stay on /6 , unless you can not get thermal issues fixed


craxton said:


> you can kill this in the dropdown arrow in task bar, then kill display container LS
> in task man, then the other and shut all Nvidia services off to run benchmarks "ON CORE" side.


mmm, i know 
Tho not really want to do that
Already using as less as possible nvidia telemetry ~ and if you disable the autostart dll, the controll-pannel container doesn't start
Haven't found time to test if the GPU then underperforms or not / without nvidias containers or access to settings. (after all profile inspector exists too)


----------



## Veii

sendap said:


> So tried to run 1T without the 56-56-56 trickery and to my surprise I found a TM5 stable (25 cycles 1UsmusV3) setting.
> Interestingly i see no difference in Bandwidth comparing 56-56-56 to 0-0-0. So there might be something still a little off (no clue how to tackle that).
> I had the feeling that 0-0-0 also was a bit more jumping around on latency. I tried in diagnostic mode (only 45 instead of 120 background processes). At first a little jumping but then constant results while hitting the Latency Box twenty times in a row (feeling like a monkey) of 52.3 to 52.5ns.


The first Aida64 result you nearly always can trow away
It is required (as load) before the CPU starts to go into idle mode after getting any load
DF-C_States appear to be fine for now on the latest microcode , good thing i feel like
But not 100% confident they are, just appear to be for the moment of time
(needs some long CTR session, to see if they overboost crash)

Today is the MS Event, let's hope for a windows update 

Only thing i don't like much on your result, is the high L3 latency
4.95 should be in the 10.2-10.3ns range, might want to open up EDC limit a slight bit (6-10A more)


----------



## CarnageBT

Veii said:


> Soo low RTT_PARK divider, certainly ment PCB crashes. Else higher ones wouldn't be able to post at all (if they where wrong)
> Strangely you still have a high temp on them ~ maybe RGB heatup ?
> Don't want to think how hot they have been on /2 or /3


This is what's confusing me. RttPark 2-7, same temps. I just updated the original post with new results for 7/3/2. In all my testing over the past few days (with 7/3/3), I always max around 48c, and today I thought it would change with a weaker rttpark, but seems the same.

It's not RGB heat up, cuz when I leave it at idle, with RGB running, temps are around 28-30c.


Since I seem to be able to run with multiple setups, the ideal one to try to make stable would be 7/3/5? Seemed to be the strongest and rttpark 5 should generate less heat than 3 or 2

Maybe I'll try a test with proc 36.9


----------



## Veii

CarnageBT said:


> This is what's confusing me. RttPark 2-7, same temps. I just updated the original post with new results for 7/3/2. In all my testing over the past few days (with 7/3/3), I always max around 48c, and today I thought it would change with a weaker rttpark, but seems the same.
> 
> It's not RGB heat up, cuz when I leave it at idle, with RGB running, temps are around 28-30c.
> 
> Since I seem to be able to run with multiple setups, the ideal one to try to make stable would be 7/3/5? Seemed to be the strongest and rttpark 5 should generate less heat than 3 or 2
> 
> Maybe I'll try a test with proc 36.9


Mmm strange indeed
Grab the Asus MemTweakIt tool from above (g-drive link) and check how Powerdown, Aggressive Powerdown , BurstRefresh look like















these things 
Up to preconfigured UrgRef-Bound and LowerUrgRef bound ~ tFAW could be the main culprit that's breaking the set
Like it was for me before ~ having to redo the old 48.5ns one "again" on SMU 56.50


----------



## sendap

Veii said:


> Only thing i don't like much on your result, is the high L3 latency
> 4.95 should be in the 10.2-10.3ns range, might want to open up EDC limit a slight bit (6-10A more)


i never see less than 10.5ns. Tried to raise EDC (PPT=142, TDC=95, EDC=*150) *but that has no impact at all...


----------



## Veii

sendap said:


> i never see less than 10.5ns. Tried to raise EDC (PPT=142, TDC=95, EDC=*150) *but that has no impact at all...


Try to run 400A EDC 
and 110A TDC
Just as test

i can not say where it throttles back, but it throttles the allcore test back - soo cache is lower and L3 latency is higher


----------



## sendap

thanks for investigating!!! raising to 400A EDC and 110A EDC results in 700GB/s to 750GB7s bandwith, so around 100GB/s more than before. But Latency stays at 10.5ns


----------



## craxton

Veii said:


> Already using as less as possible nvidia telemetry ~ and if you disable the autostart dll, the controll-pannel container doesn't start
> Haven't found time to test if the GPU then underperforms or not


no no not turning off AUTO start, let MSI or what ever your using load up, APPLY your OC to the card, and KILL
the tool your using, and kill nvidia main two services first then the last few it leaves behind. 
(your overclock will still be set) and im pretty sure the only thing it kills is nvidias container itself.)
i have the container, and geforce experience both so i kill both. but none the less, 

ill check to see if i still get the same score or not "FPS" mostly but im 90% sure it changes nothing on the fact the pc still
knows the GPU is there. as i run games all the time after killing loads of tasks... (*only after benchmarking the CPU)


----------



## craxton

hmm, if snapshot pooling in ON in HWiNFO, while gaming (this is while i have KILLED all gpu tasks etc after running
R23 for tele testing) noticing that (after i started after burner 10 min or so after playing biomutant) that it shows 4850 boosting,
yet HWiNFO shows well.....?
also @Veii this is WITHOUT nvidia display containers running etc. (did NOT kill auto start DLL for the driver)
anyhow.
whatever snapshot pooling is showing is (ACTUALLY) whats being clocked? or is the CPU really boosting to 4850? 
this is a little confusing, and NO hwinfo is not in overlay mode. (maxed out settings and sliders)


----------



## Veii

craxton said:


> hmm, if snapshot pooling in ON in HWiNFO, while gaming (this is while i have KILLED all gpu tasks etc after running
> R23 for tele testing) noticing that (after i started after burner 10 min or so after playing biomutant) that it shows 4850 boosting,
> yet HWiNFO shows well.....?
> also @Veii this is WITHOUT nvidia display containers running etc. (did NOT kill auto start DLL for the driver)
> anyhow.
> whatever snapshot pooling is showing is (ACTUALLY) whats being clocked? or is the CPU really boosting to 4850?
> this is a little confusing, and NO hwinfo is not in overlay mode. (maxed out settings and sliders)
> View attachment 2515077


Effective clock is what you currently run
The top is just the strap it applied in it's V/F curve
they mean nearly nothing - it's just the powerstage it is in
But the real load (effective clock) is what matters ~ and indicates if it's slower because of some throttling reason (power, thermal, voltage, clock stretching)

I thought about nvidia's automatic thread sheduler and texture filtering things (it behaves automatic in warzone, but performs better on enabled ~ more core usage)
Afterburner i never really run (there is nvidia ispector for such) but RTSS is to have a framecap on windows and per game
Often some videos run themself in infinite FPS mode, and create stutter (or some fishy browser sites) ~ this fully prevents it (also advisable for broadcasters)
also RTSS fps limiter is bit more smooth than ingame ~ as it interpolates to the target limit


----------



## XPEHOPE3

sendap said:


> View attachment 2515018


Did you do anything to have such perfect write speed? E.g clean all bs from Windows to improve Aida results?


----------



## craxton

XPEHOPE3 said:


> Did you do anything to have such perfect write speed? E.g clean all bs from Windows to improve Aida results?





http://imgur.com/HImrTqy

 
this is an "older" run but none the less, with tasks killed etc. 
even if i "dont" kill these tasks write speed is still 31999/31998

(running in safe mode "eventho" veii said not to, is a better option to get "consistent" runs while making sure you have the 
same processes running killing runtime brokers while in safemode and windows help thing as well. 
its not the "best" but it is 90% consistent on par with reboots for me. only time its not is when i dont kill the "help" thing microsoft has 
in safe mode (note that the run i shared in imgur is NOT in safe mode.) and was before getting CO dialed in. 
and is now around the same, only latency is more along 51.6 actual in safe mode.


----------



## craxton

considering this score


http://imgur.com/wvYMNep

and what i get now, *** HAS CHANGED? 
is bios revisions killing my chip? is it really that bad "on leaky silicon" 
was i running -25 CO all core with one step above 50mv offset?
.....really curious at this time.
granted i was on an older windows and disabled LOADS of other services that i dont have killed now, but as PJ, and mongol
both have higher scores and mongol having WAY LESS CO offset values than i do both being stable its odd... 
wished i knew better and labeled **** back then....


----------



## Veii

Veii said:


> DF-C_States appear to be fine for now on the latest microcode , good thing i feel like
> But not 100% confident they are, just appear to be for the moment of time


nop, that's been random reboot number 3 
they are still not fine - maaybe on 1203B , maybe never
We'll see when AMD finally fixes core hibernation and powermanagement (APBDIS)


----------



## Robostyle

Regarding CO offset values - anybody knows what do those mean? mV?
Mine is stable without Vcore offset all core CO negative offset of ~25, giving 4.65 sustained - but I don't know how do I dial individual cores with more aggressive CO curve, while maximum CO offset of 30 requires me to push +0.1V Vcore 

P.S. I guess my best cores are the ones that run effective 5GHz when running CB SC? Or it's just random and means nothing?...


----------



## Veii

Robostyle said:


> Regarding CO offset values - anybody knows what do those mean? mV?


Between 3-5mV each
up to load type and droop

Calculate it as 4mV each


----------



## craxton

If u fellas had an option, would A buy another 5600x, or B buy a 5800x? 
(Yes asking bc I'm curious and have enough for one or the other at THIS time. Really aiming to see how the "same" series of chip works on this board. And just bc I like to gather Ryzen chips. Currently having 3 6 cores and 1 4 with igpu.


----------



## Veii

craxton said:


> If u fellas had an option, would A buy another 5600x, or B buy a 5800x?


5800X because of two 3 things
~ it bypasses it's PBO limits
~ is higher binned to begin with
~ it has a prochot limit of 105c compared to 65c 

Else usually a 5900X, because it's even better binned
Normally the 5950X is better binned ~ but the chance to get a lemon, is bigger than with a 5900X (seen so far 3 bronze 5950X)
on a 5900X , lemon cores can be fused away and make the overall chip better "binning"

Tho i would just wait at this point ~ no need to buy an inferior CPU (soon EOL)


----------



## Robostyle

Veii said:


> Between 3-5mV each
> up to load type and droop
> 
> Calculate it as 4mV each


Such a feeling that it changes the "steepness" of V/F curve as well - I see all cores, even the worst ones go stable and easy with -20 CO offset, which is -80mV I believe, 
but then -30 CO offset is unstable even with vCore positive offset of +116mV

Or that's just aggressive CO offset pushes worst and best cores to sustain higher frequencies for a second longer, destabilizing CPU. Or its mediocre cores that fail


----------



## Veii

Robostyle said:


> Such a feeling that it changes the "steepness" of V/F curve as well -


this is what scalar does, and it changes the peak voltage too


Robostyle said:


> but then -30 CO offset is unstable even with vCore positive offset of +116mV


+45 - +60 is enough
too much and it triggers FIT to throttle back as it exceeds peak voltage limits


----------



## mongoled

Just putting this here before I forget

For MSI users

Power Supply Idle Control set to "Low Current" or "AUTO" == Package C6-State Enabled
Power Supply Idle Control set to "Typical Current" == Package C6-State Disabled

Will get back to other posts soon ....


----------



## mongoled

Art385 said:


> Yes it's consistent as it tamed boosting with CO and drops in voltages. CPU was always stable week worth of testing. Funny thing is that after flashing A72 bios with this AGESA 1.2.0.3B that is A patch Curve Optimizer behaves quite different. Before if I set negative offset my voltages would drop lower and lower whereas clock would boost higher and higher. So getting that sweet spot was real pain. On this new beta voltages per core looks like fixed  and took from FIT or somewhere. Now every core use specific voltage range. One will use 1.33-1.35v and other will use 1.41-1.43 and decreasing negative offset will only rise clocks and do nothing to voltages - tested on Scalar x1. This is really great as setting Curve optimizer now is quite straight forward as you don't need to take voltage drop into account though CPU is tad hotter as some cores in ST load will not go below 1.4v but also I've managed to squeeze more performance out of it on ST and MT. So I'm really happy


Great news!

If I remember correctly the change in how CO applies the V/F curve was updated in agesa 1.2.x.x

As you were using a previous agesa it now makes sense with what you described and with what we both now see while using agesa > 1.1.9.x



craxton said:


> considering this score
> 
> 
> http://imgur.com/wvYMNep
> 
> and what i get now, *** HAS CHANGED?
> is bios revisions killing my chip? is it really that bad "on leaky silicon"
> was i running -25 CO all core with one step above 50mv offset?
> .....really curious at this time.
> granted i was on an older windows and disabled LOADS of other services that i dont have killed now, but as PJ, and mongol
> both have higher scores and mongol having WAY LESS CO offset values than i do both being stable its odd...
> wished i knew better and labeled **** back then....
> View attachment 2515086


You always got to keep in mind that CB23 throttles depending on temp!

Myself and PJVol are usually below 75C where as your run is 80C

Also, if you are comparing to your previous results then you need to account for ambient temps.

You score is perfectly in line for the temp your CPU is running at.

Unsure who asked me, yourself or Veii..

My OS for benching is just a fresh 21H1 with only "Windows Defender" disabled, nothing else ...


----------



## mongoled

Veii said:


> Can you check if your microcode is the new 1016h ?
> There where not many updates between 1202 and 1203 (SMU wise, except for the USB focus) and bit of DPM focus (PCIe/IO stability)


My understanding is that @Art385 was on an agesa < 1.2.x.x

The latest agesa released by MSI is using the new 1016h confirmed on my X570 Unify, 0A201016h ...

I am now re-retesting non load scenario while using 4133/2067 with "Package C6-State" set to disabled now that I know what controls it !!

So far after around 30 minutes just browsing, playing music etc no random hard crashes or reboots


----------



## T[]RK

mongoled said:


> For MSI users
> 
> Power Supply Idle Control set to "Low Current" or "AUTO" == Package C6-State Enabled
> Power Supply Idle Control set to "Typical Current" == Package C6-State Disabled


So… DF-Cstate connected to PSU Idle Control?
Are you check ZenStates? I may later check this on my GIGABYTE board. Switching only DF-Cstate in Disable didn’t help, it still was enable in ZenStates.


----------



## sendap

Veii said:


> Try to run 400A EDC
> and 110A TDC
> Just as test
> 
> i can not say where it throttles back, but it throttles the allcore test back - soo cache is lower and L3 latency is higher


better bandwith but same 10.5ns @4950Mhz

edit: could it be that AIDA is running on Core 0 and cannot hold that boost if my Core 0 is not one of the best cores and thus resulting in 10.5ns instead of 10.3ns?


----------



## mongoled

T[]RK said:


> So… DF-Cstate connected to PSU Idle Control?
> Are you check ZenStates? I may later check this on my GIGABYTE board. Switching only DF-Cstate in Disable didn’t help, it still was enable in ZenStates.


I cant answer that as I am not sure if "DF-CStates" is the same as "Package C6-State" as is defined in ZenStates.

If they are the same then yes, on MSI "Power Supply Idle Control" is the switch for "DF-CStates".

No random reboots yet while turning off "DF-CStates" at 4133/2067, after a few more hours will need to reboot to see if its consistent (no crashes) across reboots/shutdowns ..

Yes its checked in ZenStates


----------



## NDS322

It seems more than 1 Hr after I was updated to the new bios AGESA 1.2.0.3 Patch B from MSI.

No more WHEA ERROR 19 with RAM Bus 4000MHz at 1:1 Ratio


----------



## Takla

What is the correct tCKE for 3600? And do I need power down enabled, for matisse?


----------



## FleischmannTV

I believe it's 6 and PowerDown should be disabled by default.


----------



## Robostyle

NDS322 said:


> It seems more than 1 Hr after I was updated to the new bios AGESA 1.2.0.3 Patch B from MSI.
> 
> No more WHEA ERROR 19 with RAM Bus 4000MHz at 1:1 Ratio


You think it was BIOS bug, but not instability that you solved tinkering voltages?


----------



## craxton

Veii said:


> 5800X because of two 3 things
> ~ it bypasses it's PBO limits
> ~ is higher binned to begin with
> ~ it has a prochot limit of 105c compared to 65c
> 
> Else usually a 5900X, because it's even better binned
> Normally the 5950X is better binned ~ but the chance to get a lemon, is bigger than with a 5900X (seen so far 3 bronze 5950X)
> on a 5900X , lemon cores can be fused away and make the overall chip better "binning"
> 
> Tho i would just wait at this point ~ no need to buy an inferior CPU (soon EOL)


ordered one of the "last 3" amazon claims to have until more are shipped in. 422 after tax. comes in saturday.
and yes, i know new sockets coming into play but none the less for the sake of what im "aiming" to do.
i should be ok the purchase. 
hopefully the EK 240mm aio can keep it cool "enough" 

at this time however, quite concerned that my 5600x is degrading. from all the imgur shots i have, 
to what i can/cant run the same now (bios differs i know) but used to i could run 4800mhz at 1.38v and not have issues 
until prime ran for a few hours. but now, cant get into windows for 30 seconds on the same voltage and freq. 
(never ran it over a day on that oc) and since then been PBO. 

but somethings not quite right with the CO values i can use, what the "tool" says 80 sil quality, and that "old" manual oc 
arent stable anymore (none of them)


----------



## craxton

mongoled said:


> Great news!
> 
> If I remember correctly the change in how CO applies the V/F curve was updated in agesa 1.2.x.x
> 
> As you were using a previous agesa it now makes sense with what you described and with what we both now see while using agesa > 1.1.9.x
> 
> 
> You always got to keep in mind that CB23 throttles depending on temp!
> 
> Myself and PJVol are usually below 75C where as your run is 80C
> 
> Also, if you are comparing to your previous results then you need to account for ambient temps.
> 
> You score is perfectly in line for the temp your CPU is running at.
> 
> Unsure who asked me, yourself or Veii..
> 
> My OS for benching is just a fresh 21H1 with only "Windows Defender" disabled, nothing else ...


considering my old temps were roughly the same, but its cooler in my house at this time. 
*(as heats not set to 75c and air is instead on 71c) thats what im concerned about. 
old static OC no longer stable, none of the old ones are. to where now they need more voltage.
maybe due to using 4x8 but when i removed the other 2 last night, still the old profiles i had wouldnt work
(*have pics of these old profiles)


----------



## XPEHOPE3

Veii said:


> VDIMM can make dimms crash, testing takes too much time - soo maybe skip this
> Remain ones all have a connection, but you do 1. at the start and at the end when everything is stable ~ till results do not improve anymore but only get worse
> 
> this is also work for 1.) but only after you have something stable. Any random procODT can most of the times work and reach "stability" even with a lot of autocorrection users barely nottice
> 
> 3. is mid-work. It's not a required entry. 900mV cLDO_VDDP always works, but you can try to lower CPU_VDDP further and this one, to help with lower procODT
> Lower procODT will help in reaching higher FCLK overall
> 
> Only if Aida64 result is favorable and you know that it can not be a timings issue (no timings change on this boot-tests)
> After y-cruncher, verify with OCCT Extreme , then when Aida64 doesn't improve, focus on timings or focus on Curve Optimizer ~ till one of both do not improve
> 
> Wrote an order at first, how i do it ~ in short
> Everyone has own testing methods, there is no "rule"
> I just don't want to waste "already taking enough" time, with bruteforce possibilities ~ soo if Aida64 doesn't improve or CPU-Z doesn't improve. Quick fast benchmarks
> Then it is not worth my time and i'll change bigger things
> 
> If X change doesn't show, it doesn't mean it's not working tho
> Revisiting "unknown changes" options, always is a good idea later
> 1.8v rail differences we [OCN] figured makes a difference only later, but not at the start
> I worked without touching it ~ it always was at 1.83, butt did not see at the start differences between 1.9 or 1.8
> Same for CPU_VDDP,, no difference only later beyond 2067 FCLK it started to matter a bit
> Also same for tCKE. Did not touch it, till PCBs started to crash and i had to so something against it
> I can not replicate, explain the order. Everyone has their own methods
> 
> still haven't gone that path,
> 2167 FCLK is higher in the priority listt , and before that is getting tRCD 18 on 4000 to work on Rev.E , instead of 19 ~ or CL12 stable not 13
> Many other things have higher priority ~ like finding a Matisse CPU to get Thunderbolt 4 to work better (2nd pc) or writing ACPI/machine code-table for macOS hackintoshing & get it there setup
> 
> At least 10+ work in progress projects ,
> This 3.) can wait , there is not much pressure bellow 49ns for now & bios updates are booring


Ok, I tried these directions. TLDR and questions in the end 
I had this 3600-14-fclk1800 stable setup:







And tried to set fclk 1900. Initial results for write bandwidth and latency were (for procODT _48_):
30389 65.6
30388 65.4
30389 65.6
30393 66.1
30389 65.6
I figured the latency bump was so huge and stable that I don't need to "fix" Windows yet to search for settings which would strongly lower latency, were there any such settings.
It appeared that I can boot and test with literally any procODT:

28.2303234.336.94043.6_48_53.36068.630390-3039430385-3039130387-3042330390-3039230388-3039130389-3040130390-30392_30388-30393_30388-3039230391-3039130390-3039165,1-66,665,7-66,665,4-66,265,3-65,965,3-65,865,5-66,265,5-65,8_65,4-66,1_64,5-65,365,2-65,665,2-65,6
Only 53.3 gave measurable improvement in latency, but that procODT was higher than base while for higher FCLK and lower voltages one should aim for lower procODT. Also for 3800-16-1900 setup I found that procODT 43.6 was slightly better than any other.
Then I tried to vary VDDP/VDDG CCD/VDDG IOD, 1.8 rail (values of 1.8v and 1.84v)/VSOC/VSOC LLC to Turbo ("1 below flat"), and even VDIMM (1.42-1.46 and 1.5). VDDP I tested 880, 840, 900 and 902 set values with 53.3 and 36.9 procODTs. VDDP 840 with procODT 36.9 improved to 64.5-65.4 ns when LLC was set to Turbo. The rest -- no better than in the table above.
The best I could achieve was 64.3-64.7ns for 53.3 procODT with 900-1018-1100 VDD*, VSOC 1.2 and Turbo VSOC LLC. Write bandwidth did not improve at all. And transferring those voltages to procODT 43.6 which I kinda aim for, gave 64.3-65, which also is an improvement.

However what struck me is that setting FCLK to *2000 actually gave better latency*: 62.1-62.8ns (31989-31992 write bandwidth).

*TLDR*: (and questions)

Latency bump of 5ns appearing after going from 3600-14-fclk1800 to FCLK 1900 can't be tamed fiddling with procODT/VDD*/VSOC/VSOC LLC/VDIMM/1.8 rail. Why can that be the case? Is it my particular hardware problem (CPU/Motherboard/RAM PCB)? Or is it 4*16Gb-related general issue? Or is that huge bump actually expected to remain?
At best 1ns can be saved, but those settings (e.g. procODT) might not transfer when MEMCLK is upped as well
Going for 2000 FCLK gives lesser bump (< 2ns) than FCLK 1900. Why?  Can it give any clue to the first bump?
Why could I boot and test with that many procODT values?


----------



## NDS322

Robostyle said:


> You think it was BIOS bug, but not instability that you solved tinkering voltages?


Maybe it from bios, My setting and Hardware still the same as Bios AGESA 1.2.0.2 Final before.

It around 3 Hr now, I still don't get WHEA Error 19 anymore.


----------



## Robostyle

Patch B? So its something newer than asus’ 3601 Patch A...


----------



## Nighthog

Maybe Agesa 1.2.0.3b finally fixed the WHEA issues for higher FCLK on 5000 series?

They really took their time with finding the problem? Maybe related to the USB issues? Patch B is the one supposed to finally fix that problem.


----------



## Robostyle

Nighthog said:


> Maybe Agesa 1.2.0.3b finally fixed the WHEA issues for higher FCLK on 5000 series?
> 
> They really took their time with finding the problem? Maybe related to the USB issues? Patch B is the one supposed to finally fix that problem.


I guess, and a lot of other issues as well cause Patch A BIOS might be the worst of asus firmwares I've ever seen - this 3601 could challenge rgb bloatware if you ask me


----------



## domdtxdissar

New "CPU profile benchmark" from UL 3dmark out, dont know if scores are affected by memory speed/latency, but this is my result with ctr 24/7 clocks in a semi warm room: I scored 0 in CPU Profile








_edit_
Normal temp








I scored 0 in CPU Profile


AMD Ryzen 9 5950X, NVIDIA GeForce RTX 3090 x 1, 32768 MB, 64-bit Windows 10}




www.3dmark.com













Download here: 3DMark on Steam


----------



## 1s1mple

With the new 1.2.0.3 Patch A


----------



## Insidious Supra

@craxton Yep, I'd wait and get a 3d v-cache 5800xt? Toward the end of the year. I'll likely swap mine out for the newer variant when it comes out. Though my 5800 is quite nicely binned. (seems a lot of 5800x's are nicely binned)


----------



## Robostyle

What can be a reason for this ycruncher to crash instantly after the start?
All other tests are fine, no errors or sudden crashes...like, immediately.


----------



## Rujaza

Hi all, I came up with this stable configuration:










VDDG CCD: 1,000v

It's a mix of Dram Calculator 1.7.3, all of your posts, some guides I have read and of course tests.
I added a fan over ram slots to keep temperature under control and in real condition they top at 48c° these days where I live. Seems too high for these settings and active cooling or am I missing something?
I have a P600S with plenty of airflow.
Honestly I didn't understand very well how to relate VDIMM, ProcODT, Rtt and DrvStr to try different combinations and why tFAW won't go under 30 despite should be a good B-die A1 bin.
Could someone more experienced explain to me? I'm willing to learn and test more but I feel I need more informations. 

I settled at FCLK1800 because seems that my 3700X need more than 1,125v vsoc to reach 1866/1900FCLK and I have read it's no good ( I can boot easly but it crash randomly). Is it a lost cause or can I push? In which direction?

Thank you in advance!


----------



## craxton

Robostyle said:


> What can be a reason for this ycruncher to crash instantly after the start?
> All other tests are fine, no errors or sudden crashes...like, immediately.


Can be unstable somewhere with ram, or SOC voltage. What are "all other tests" that u run? 
Are u running a CO offset ? If so then turn it off and retest. As from what I recall your running -25 on all or almost all cores. My guess start there and change nothing else and see if that doesn't fail. If it does try a little more SOC voltage. I'd almost bet tho if you look inside event viewer under WHEA errors it'll show an ACPI WITH 1-16 1 and 2 being core 1 or aka 0 and so on and so fourth. If it does that's the core that's crashing during your test and your CO offset isn't as stable as you had thought.


----------



## Robostyle

craxton said:


> Can be unstable somewhere with ram, or SOC voltage. What are "all other tests" that u run?
> Are u running a CO offset ? If so then turn it off and retest. As from what I recall your running -25 on all or almost all cores. My guess start there and change nothing else and see if that doesn't fail. If it does try a little more SOC voltage. I'd almost bet tho if you look inside event viewer under WHEA errors it'll show an ACPI WITH 1-16 1 and 2 being core 1 or aka 0 and so on and so fourth. If it does that's the core that's crashing during your test and your CO offset isn't as stable as you had thought.


Nope, totally stable in AIDA, memtest, HCI, Prime95, GSAT, etc., 5950x-like single-core results in cinebench, no WHEA, no BSoDs, no reboots - nothing! 0 errors in event viewer - don't have even regular application errors for last 24H.
More of that, actually, ycruncher is able to run stable. Once in a while. I don't know what the reason for it, but it can run flawlessly for 2 hours, the whole set - then I stop it, try to run it once more - and it crashes instantly, just after the start in 3 seconds. Like, it can only run stable after cold boot or something.

I run CO offset -20on all cores, -25 and -30 is a little bit tricky, I can't get fully stable with those, getting random reboots, thinking that +125mV offset solves the problem, but it was said earlier too much vCore could cause throttle. Now using ~+50mV offset - but that's just for insure.
SOC is already at 1.2V for just 3800:1900 memclk, and I have tested both CPU and MEM overclock overnight for stability


----------



## craxton

Robostyle said:


> Nope, totally stable in AIDA, memtest, HCI, Prime95, GSAT, etc., 5950x-like single-core results in cinebench, no WHEA, no BSoDs, no reboots - nothing! 0 errors in event viewer - don't have even regular application errors for last 24H.
> More of that, actually, ycruncher is able to run stable. Once in a while. I don't know what the reason for it, but it can run flawlessly for 2 hours, the whole set - then I stop it, try to run it once more - and it crashes instantly, just after the start in 3 seconds. Like, it can only run stable after cold boot or something.
> 
> I run CO offset -20on all cores, -25 and -30 is a little bit tricky, I can't get fully stable with those, getting random reboots, thinking that +125mV offset solves the problem, but it was said earlier too much vCore could cause throttle. Now using ~+50mV offset - but that's just for insure.
> SOC is already at 1.2V for just 3800:1900 memclk, and I have tested both CPU and MEM overclock overnight for stability


have you looked here,
take note that im in event viewer local, then under ERROR, then WHEA-LOGGER.
which is different that WHEA KERNEL
so go there and look unless you did.
mine doesnt show in app and service logs, folder, folder, then kernel whea folder.
i had a crash while trying to run a 4600mhz all core setting but
other than that my CO is tuned per core now.
(what i showed a shot of will show what core if it is thats crashing.)

whats your IOD, CCD, CPU_VDDP voltage?
what LLC are you running?
what switching frequency?
run OCCT like well see the other image.









(edit) this is where i belive your checking for crash WHEA logs, which is not where one needs to look
to find what core it was. at least on my board its not there. only WHEA 20 which means a crash happened.


























i would NOT advise a 150mv offset to voltage in the positive range... if you didnt try turning off the CO OFFSET
then do so before applying more voltage. (its best to NOT NEED) voltage offset while running CO. as CO should make your CPU
use less voltage. so your kind of negating what your doing with CO lol.....

to find CO values its easy to use CORE-CYCLER, which i dont see you mention. if you run that and fail then your not -20 CO stable.


----------



## craxton

seems a bios update for my board came thru as well patch B. 
gonna ask that @Eder unlock this new bios???? b550 gaming edge wifi???
straight to the page.


----------



## Veii

mongoled said:


> My understanding is that @Art385 was on an agesa < 1.2.x.x


Yes, there was a big update coming from 1200 towards 1201+
Tho not all 1201 had all the patches included
1201 onwards had a changed IMC Firmware, soo also changed procODT behaviour


mongoled said:


> So far after around 30 minutes just browsing, playing music etc no random hard crashes or reboots





XPEHOPE3 said:


> And tried to set fclk 1900. Initial results for write bandwidth and latency were (for procODT _48_):
> 30389 65.6
> 30388 65.4
> 30389 65.6
> 30393 66.1
> 30389 65.6


The only halfway reasonable result looks to be 34 ohm
With only sub 0.4ns latency differentiation
Also 60ohm, but this counterproductive

Makes me wonder about the method of testing
You have too much variance and maybe? don't press "start test"
If you do, and are sure that windows update or random printer/fax services at the right moment didn't interfere
Then it comes down to "bad" voltages for this 34ohm set

Usually higher nearly always work. Up to 120ohm
But considering IMC FW surely was changed
ProcODT, DQs, RZQ and couple more (don't have them in my mind right now)
~ got changed, it wouldn't surprise me if procODT peak is different

Overall, your goal is to have as less latency variability as possible with that procODT
The write "peak" bandwidth scales/rather "depends" on voltages and "lost/not wasted" ones

Dont forget enegry can not be diminished or destoryed
It always moved to something
And when voltages are not used or overvolted
FIT will slow the CPU down to "absorb" higher voltages
~ this takes into consideration that frequency can not raise, and silicon limits are reached (Q levels)
Soo when frequency can not raise and FIT clarifies cores as "peak voltage, peak current, peak Q levels
~ the only place "overcurrent" can go, is to be absorbed

Soo what happens, is package throttle 
A slow frequency CPU, won't have that much issues with for example 1.6v
Compared to one on >4.5ghz
This happens for me too now with my 2100 FCLK voltages on 1900FCLK
I know and ignore it, but thats why for example my results right now lack 7-8MB/s peak write
Couldn't be bothered to rerun 6h of stress tests, just for a "memory stability" experiment with low timings 



Nighthog said:


> Maybe Agesa 1.2.0.3b finally fixed the WHEA issues for higher FCLK on 5000 series?


Look them extending it to 2000, but causing issues with 2100+ 


craxton said:


> i know new sockets coming into play


I didn't say this 🤭


----------



## mongoled

craxton said:


> considering my old temps were roughly the same, but its cooler in my house at this time.
> *(as heats not set to 75c and air is instead on 71c) thats what im concerned about.
> old static OC no longer stable, none of the old ones are. to where now they need more voltage.
> maybe due to using 4x8 but when i removed the other 2 last night, still the old profiles i had wouldnt work
> (*have pics of these old profiles)


Did you also downgrade to the BIOS that was used to run those tests ?

I would be looking at redoing the thermal paste and making sure nothing has changed with regards to the cooling capacity of whatever you are using to cool the CPU



Veii said:


> Yes, there was a big update coming from 1200 towards 1201+
> Tho not all 1201 had all the patches included
> 1201 onwards had a changed IMC Firmware, soo also changed procODT behaviour


Thanks for confirmation!


----------



## Robostyle

craxton said:


> whats your IOD, CCD, CPU_VDDP voltage?
> what LLC are you running?
> what switching frequency?
> run OCCT like well see the other image.
> 
> 
> (edit) this is where i belive your checking for crash WHEA logs, which is not where one needs to look
> to find what core it was. at least on my board its not there. only WHEA 20 which means a crash happened.
> 
> i would NOT advise a 150mv offset to voltage in the positive range... if you didnt try turning off the CO OFFSET
> then do so before applying more voltage. (its best to NOT NEED) voltage offset while running CO. as CO should make your CPU
> use less voltage. so your kind of negating what your doing with CO lol.....
> 
> to find CO values its easy to use CORE-CYCLER, which i dont see you mention. if you run that and fail then your not -20 CO stable.


NO, I've never thought about whea kernel at all, always meant for whea logger in the event viewer.
IOD 1.1V, CCD 1V, VDDP 1.05V, LLC3/500kHz

I apply vCore offset purely for core oc and stability at aggressive CO - since good-old oc isn't applicable with zen...

For the starters...occt


----------



## Veii

domdtxdissar said:


> New "CPU profile benchmark" from UL 3dmark out, dont know if scores are affected by memory speed/latency, but this is my result with ctr 24/7 clocks in a semi warm room:


For whatever it tests, for the price of 4 bucks ~ it's recommendable to get the package


----------



## Robostyle

Naah, it's 100% ycruncher fault. 
I've loaded optimized defaults, then followed my usual routine to repeat cruncher error - 10-15 minutes of other stress-tests, ordinary work, etc.
And it crashes again, lol! While PC is on stock.









And it does that again and again and again...sometimes, like 1 of 10 it runs succesfully for hours or crashes at some point.


----------



## Veii

Robostyle said:


> Naah, it's 100% ycruncher fault.
> I've loaded optimized defaults, then followed my usual routine to repeat cruncher error - 10-15 minutes of other stress-tests, ordinary work, etc.
> And it crashes again, lol! While PC is on stock.
> View attachment 2515214
> 
> 
> And it does that again and again and again...sometimes, like 1 of 10 it runs succesfully for hours or crashes at some point.


There are defective CPUs out (seen 4 out of 20) - and buggy bioses
But you can get an older version of y-cruncher too

The chance that it's y-cruncher is too low
Rather blaming a random microsoft update, or .net framework / SMU issues ~ sounds more reasonable

EDIT:
For an algorithm to hardcrash (probably on detection), something has to be majorly broken
If this is the first time you run the program, i'd doublecheck if your CPU is not a dual CCD frankenstein unit by any chance
Else really rather blaming the Bios (SMU) or a random windows update


----------



## Robostyle

Veii said:


> There are defective CPUs out (seen 4 out of 20) - and buggy bioses
> But you can get an older version of y-cruncher too
> 
> The chance that it's y-cruncher is too low
> Rather blaming a random microsoft update, or .net framework / SMU issues ~ sounds more reasonable


5800X+Dark Hero 3401, Win10 20H2 19042.1052
Unfortunately, crashing cruncher won't help me prove local retailer of amd that my system is on fault, especially when other tests work fine - besides, I don't see any negative effects, like loose or corrupt files, system crashing, laggy or "not-so-smooth" system that would indicate any OC issues. 

I'm more interested in going further with even more aggressive CO and 2000FCLK. So would like to ask for advice: how do you guys dial the most potent cores for the most aggressive CO?


----------



## Veii

Robostyle said:


> Unfortunately, crashing cruncher won't help me prove local retailer of amd that my system is on fault,


Sadly,
Crashing AVX2 tests ~ are an issue and RMA'able, but you crash on mixed SSE workloads already (like overcurrent crashes)
Ryzen Master on your Picture looks like it has an OC applied - or was once used with an Win-OC (DDU wiping chipset drivers & running once CTR diagnose could help)

The tool (RM) does save configs in a partition of the bios (not NVRAM) which does not reset upon CMOS wipe
It can be wiped with AFUWIN on Windows or USB Flashback (SPI ~ outside of the bios)
But it looks very near/close to a "i've used Ryzen Master & so it keeps applying the old overclock" ~ kind of issue

Gave you 3 options 

Downgrade the Bios & be sure to disable PBO + slight postive offset (5mV)
Downgrade the Windows update
RMA
Last one, you need to be very sure it's that part
But considering there are quite a few out there with such issues ~ it doesn't feel like the stated 3-4% failure rate anymore
Nevertheless, it shouldn't crash ~ resolve that first, before you get used to going around issues


----------



## ManniX-ITA

Robostyle said:


> And it does that again and again and again...sometimes, like 1 of 10 it runs succesfully for hours or crashes at some point.


How did you exactly test the memory OC?


----------



## CarnageBT

Is it normal that I can boot into windows, run aida, and a few mins of TM5 for a quick check on ALL procODT values from 28 - 40? I kind of expected only 3 or 4 would work, and the others fail.

Other settings were, Rtt 7/3/6, cad_bus 30-20-30-24, 1.1 vsoc, .88 vddp/ccd, .96 iod, 1.5 vdimm.


----------



## Robostyle

Veii said:


> Sadly,


I guess I simply should have checked other versions of ycruncher before making all the fuss 
All crunchers ver. 0.7.7 and below start and run fine without issues.
It's all about 0.7.8, all three of them 9503,9506 and 9507 have problems, every single crash at the start.
They even crash sometimes while creating their own dump file.










ManniX-ITA said:


> How did you exactly test the memory OC?


Starting with light loads just to check if I'm stable at least 95% - chrome, then RAM-heavy games and AIDA, if no bugs or app crashes occurred - HCI memtest for an hour/couple of hours/overnight.


----------



## mongoled

so... was able to use roughly the same settings as previous BIOS for the new agesa 1.2.0.3B on the below 4133/2067 TM5 run.

Additional comments are required for the image below:

vDDP @ 0.9v is too low, ive now raised it to 0.92v as Latency Monitor did not like only 0.9v !

Loss in GFlops in LinpackXtreme due to high FCLK can be kept to a minimal using higher than default PLL voltage, have now set this to 1.88v that returns 1.90x volts get.

Still cannot find a combination of CCD/IOD or something else to help with the slight sound anomolies that happen every so often. If I cant get rid of these sound anomolies there is no point doing any futher stress testing


----------



## mongoled

CarnageBT said:


> Is it normal that I can boot into windows, run aida, and a few mins of TM5 for a quick check on ALL procODT values from 28 - 40? I kind of expected only 3 or 4 would work, and the others fail.
> 
> Other settings were, Rtt 7/3/6, cad_bus 30-20-30-24, 1.1 vsoc, .88 vddp/ccd, .96 iod, 1.5 vdimm.


Yes, perfectly normal


----------



## craxton

Veii said:


> I didn't say this 🤭


Nope, other leaks did. LGA style am5 socket. 
Unsure if I agree with this change. 
But at least I can't bend anymore pins on anymore CPUs by dropping the dam things lol



Robostyle said:


> all about 0.7.8


Probably shuda asked, but it's in the bug fixes that the earlier version were crashin amd Ryzen chips. 

@mongoled 
No, I actually did downgrade to those bios. Would seem upgrading to patch B beta MSI released, costs even MORE performance. And in order to gain it back, I must run -25 co with 3xmv offset. 
Which puts my chip (with auto start b.s. 12090 ish) 

Mfn 5800x dropped 2 dollars in price, and 5600x dropped an entire 10 lol 😆


----------



## Veii

craxton said:


> Nope, other leaks did. LGA style am5 socket.


Yet wasn't talking about end of 2022 🌝


----------



## ManniX-ITA

Robostyle said:


> It's all about 0.7.8, all three of them 9503,9506 and 9507 have problems, every single crash at the start.


Looks like an issue with the CPU.
But I would double check the memory OC running at least 25 cycles TM5 1usmus just to be sure.


----------



## craxton

Veii said:


> Yet wasn't talking about end of 2022


....i suppose i musta missed something somewhere then...
none the less, ill be able to get most of everything i need to build "a new testing" 
system minus a GPU once needed. 

but it would seem i need to check up and see about this "change" in sockets and whatever 
AMD is about to change.


----------



## craxton

@Robostyle
check this uness you have.



y-cruncher - FAQ


unsure if your getting an error with this crash in y-cruncher or not.
"do you have tamper protection and protected folders turned on in windows"
if so turn that off or give an all access pass to y-cruncher...although this should hard crash the system

and TURN OFF CO OFFSET??? state that you set defaults but keep mentioning that your running curve offset...
the link i sent however can tell what error your getting when checking the dump file ycruncher made.
y-cruncher at the latest version isnt having any issue. this is 100% a cpu issue if it continues to crash without curve offset applied.
and do go back after and try a 5mv (0.0005) or it might look like 0.005 unsure as MSI only has set options using + or -
(do this after turning off Curve offset COMPLETLY) and failing.

and again, about "US" finding our Curve offset values, you can use this 
with y-cruncher, as well as you can use OCCT how i showed you only testing 1 core with its thread at a time. 
DO NOT USE THE PC and CLOSE all other tasks that you auto start while running core cycler.
it will take A GOOD WHILE>


----------



## XPEHOPE3

Robostyle said:


>


Left screen *misses 2 cores (#1 and #15)* and allocates 80MBs more memory per core. Also strange is that total memory allocation is just 22-24GB. It's like you have a lot of other things open.


----------



## Veii

craxton said:


> i suppose i musta missed something somewhere then...


The message of "you might want to wait a bit" 🤭
Or "for this year to nearly finish"
It's "a good idea to not rush on cheap looking offers"


craxton said:


> and do go back after and try a 5mv (0.0005) or it might look like 0.005 unsure as MSI only has set options using + or -


+1, as this resets any custom configured voltage curves by the board partners and set's it to AMD's default one


----------



## Nighthog

Having decent success with the new memory kits I've gotten.
Testing on my Biostar B550MH paired with my 3800X.

Doing 5000Mhz 18-23-23-46-120 @ 1.580V stable for the moment it looks like, just need a longer test-run to see everything is fine before more tuning is done.
Here is a screenshot it did 20-23-23 all good. (tCL-tCWL 18-18 worked just as good everything else the same)


----------



## craxton

Veii said:


> The message of "you might want to wait a bit"


as of today, the price drop "just like last time" would indicate that 
somethings about to release which should be the APUs 
but when a price drop happens on AMD side it instantly JUMPS back up over MSRP 
at base price thru most sellers. 
so i didnt wait, and wanted a 5800x anyhow since day one. 

my patience is thin, with 3 kids and a woman behind me i have none to give to amd atm lol
nor my wallet for that matter. but if all goes according to plan ill recoup ALL the cost of this chip. 



Veii said:


> +1, as this resets any custom configured voltage curves by the board partners and set's it to AMD's default one


hmm, i wonder if thats why i use "less" voltage when running stock vs leaving it set to "auto" 
does this apply for using "amd voltage control" as well? i know you cant +1 here. 
but wouldnt it or shouldnt it be what AMD sets by default while running the AMD option?


----------



## craxton

Nighthog said:


> Having decent success with the new memory kits I've gotten.
> Testing on my Biostar B550MH paired with my 3800X.
> 
> Doing 5000Mhz 18-23-23-46-120 @ 1.580V stable for the moment it looks like, just need a longer test-run to see everything is fine before more tuning is done.
> Here is a screenshot it did 20-23-23 all good. (tCL-tCWL 18-18 worked just as good everything else the same)


dang nice, is this board a 2 dim board or 4?? 
has to be 2 slots.. 

this VRM on this boar is enough to handle the 3800x ? or are you running some kind of fan over the VRMs ??


----------



## craxton

Yo @Veii 
hows win 11 turning out?
are you still testing and playing with it?
are "services" that you normally can shut off completely and not have a windows issue arise still doable ??
yes, the "free upgrade" is interesting but ive never been an early adopter. 
so im curious to know how it does now.


----------



## Nighthog

craxton said:


> dang nice, is this board a 2 dim board or 4??
> has to be 2 slots..
> 
> this VRM on this boar is enough to handle the 3800x ? or are you running some kind of fan over the VRMs ??


It was the cheapest 2dimm B550 board around when I bought it, most likely still is. 

Though it can't really handle the 3800X, you need to limit it for 80Watts if you don't want issues with VRM throttling. (though you can disable the limit for thermal runaway if you really want all the performance)
Additional cooling for VRM area is a requirement for anything else than 65watt TDP CPU's/APU's.

I really should be changing the cpu's on my systems, the 4650G to the B550 and the 3800X to the X570 Xtreme.


----------



## Robostyle

ManniX-ITA said:


> Looks like an issue with the CPU.
> But I would double check the memory OC running at least 25 cycles TM5 1usmus just to be sure.


I did TM5 anta777 (heavy), after OCed my mem first time. The last - and the current mem tune was stable ~20cycles.



XPEHOPE3 said:


> Left screen *misses 2 cores (#1 and #15)* and allocates 80MBs more memory per core. Also strange is that total memory allocation is just 22-24GB. It's like you have a lot of other things open.


Seen that. Dunno, why then earlier cruncher detects all cores just right after new failing one?
RAM limits - it's just Win10 caches 7.8Gb for an unknown reason, 4 of them used only.


----------



## Veii

craxton said:


> somethings about to release which should be the APUs


Yes, yes but i mentioned "the APUs release on the 5th of August"


Nighthog said:


> Having decent success with the new memory kits I've gotten.


Better mood than me
I think they are painful , but post everything i trow at them

I wonder, can you replicate ? ~ 1.64v, but above 1.6v "required"
tRCD 18 on 4000 is still a challenge and a half








============
@domdtxdissar
Seems to be a good Curve Optimizer test
Got it crashing 4 times on my old settings ~ soo adjusted loadline and offsets a bit ~ soo it passes now
Seems to also be a very good CTR test ~ surely more harsh than it's P95 presets








Unsure if it tests per core with 2 threads and 1 thread ~ or only one fixed
but that one was crashing couple of times. Now it's fine
They need to make a stresstest version of it
Seems like load is quite aggressive

Also wonder about this "gray" OC potential ~ what it really means
Only makes sense with CTR PX so far
I scored 0 in CPU Profile[/URL]

EDIT:
1T & 2T test seem to not be CPPC aware ~ at least on the current win
The program only tests the first core ~ can just use CPU-Z too
Also redid screenshots, more vcore offset - way stronger vdroop
Frequency "curve" is now more stable ~ might have it's existence reason after all


----------



## XPEHOPE3

Robostyle said:


> anta777 (heavy)


this is less sensitive than anta extreme, which is on par with 1usmus_v3 config: I had situations when one would catch an error while the other wouldn't. It's jsut you need to run 1usmus_v3 way more cycles to catch all errors.


----------



## Iarwa1N

I finally decided to try my dual rank b-die rams on my old Z390 Aorus Master, just to see if I damaged the kits while trying to make it work on my B550 Strix-F board. While on Strix board I couln't even post with 3600 mhz, on z390 the board easily posted at 4000 mhz with CL16. Is it possible to deduct which rtt, drvStr and setup timings the Z390 board uses to try the same values on my Strix-f. Here is the timings (I used loose timings strategy from the bios);


----------



## Nighthog

Veii said:


> Better mood than me
> I think they are painful , but post everything i trow at them
> 
> I wonder, can you replicate ? ~ 1.64v, but above 1.6v "required"
> tRCD 18 on 4000 is still a challenge and a half
> 
> 
> 
> 
> 
> 
> 
> 
> ============


Here you go.
Could do tRCDRD @ 17, 
16 caused a blue screen with those timings. Just a quick test done.


----------



## byDenoso

For a Hynix DJR, is a good latency IMO.


----------



## Robostyle

craxton said:


> and TURN OFF CO OFFSET??? state that you set defaults but keep mentioning that your running curve offset...
> the link i sent however can tell what error your getting when checking the dump file ycruncher made.


Dude, I've made that last screenshot with two crunchers after optimized defaults+CMOS reset.
I've read dump files cruncher created. Nothing special except this:








Problems with accessing RAM rows?
I've tried running it with admin rights, withal killing all the 3rd processes, leaving win native + drivers like nvm, etc.
Besides, 0.7.7 doesn't have problems, even after 0.7.8


----------



## craxton

Robostyle said:


> Dude, I've made that last screenshot with two crunchers after optimized defaults+CMOS reset.
> I've read dump files cruncher created. Nothing special except this:
> View attachment 2515239
> 
> Problems with accessing RAM rows?
> I've tried running it with admin rights, withal killing all the 3rd processes, leaving win native + drivers like nvm, etc.
> Besides, 0.7.7 doesn't have problems, even after 0.7.8


then its your ram config not being 100% stable.

you said you ran loads of ram tests and passed, but manna
mentioned 25 cycles as another feller mentioned (Veii) tRFC rounding errors dont come into play etc until
cycle 20+. so, if you havent done so, run TM5 again with 25 cycles.
(EDIT) you need to run TM5 without using the ANTA777 config file (re-edit) the reason
to use 1usmus default config is the work has been put in to know what these errors/if any
are, i believe the one who put in that work as well, is Veii.-end re-edit,
use 1usmus default. ill
share a link from my Gdrive that has all you need. just be sure to load config and exit, its already
set for 25 cycles, just dont use the machine while its running. (best to do it overnight)

Here is that TM5 link

also, did you check to see if your antivirus has (see pics) turned off?















if its not then turn it off to "try" and see if this helps. sometimes controlled folder access blocks
well it always does even windows stuff that it needs daily to run itll block for some reason and you have
to give it permission to run.

i do see you mentioned killing stuff, but considering how much ram you have, and how much y-cruncher can get to
somethings running in the background that your not noticing....mine with "ALL MY AUTO RUNS"
like razer, aferburner, PX1, (afterburner is used for OSD and PX1 is used for overclocking, dont use ab
as it doesnt have 3 fan controls and has a few issues overclocking my card for some reason)
anyhow with all the autos, and chrome open this is what im setting at (thats with synapse by razer btw open and running
in the back)











when you run y-cruncher are you doing 1-7-0 ?
another fellow had the exact same issue as you have now, his was INDEED ram related!
so thats probably what you got going on. unless the chip does indeed need to be RMA.
Imfodor i believe was his name, havent seen him in quite sometime.


----------



## XPEHOPE3

Veii said:


> The only halfway reasonable result looks to be 34 ohm
> ...
> Then it comes down to "bad" voltages for this 34ohm set
> ...
> You have too much variance and maybe? don't press "start test"


The whole table was created while using 902-1000-1000 VDD* voltages, droopiest VSOC LLC, and clicking RMB on Start Benchmark -> Start Memory Tests Only.
But changing that to 900-1018-1100 & VSOC LLC "1 below flat" improved mean latency *for every procODT I checked* 


Spoiler: for example




for 36.9 Ohm from 65,3-65,8 latency became 64.4-64.8 with two outliers of 65.2 and 65.5
for 34.3 Ohm from 65,3-65,9 latency became 64.4-64.8 with 65.1 and 65.5 ~ outliers



Also variation and value did not depend on how I measured latency (later on I read in this thread from someone that it's possible to just doubleclick Latency field and run the test, which I'm doing from then on).


Spoiler: Regarding outliers



Since I'm not stripping Windows yet, I have to conduct tens of measurements and choose by hand what looks like outlier and what doesn't. If something comes from popup corner, obviously latency goes nuts and that would be an outlier. Also I have to wait some minutes so that no updater uses ethernet anymore which I see from task manager. So given that, if I see 10 values in one ballpark and two values much higher, I declare those outliers. Never I saw one value much *lower *that the usual).





Veii said:


> got changed, it wouldn't surprise me if procODT peak is different


With SMU 56.53.0, microcode update 0A201016 I have these values:










Veii said:


> Soo what happens, is package throttle


I think you were right. I loaded AMD monitor together with Aida write bandwidth test and saw PPT, TDC, FIT PID limiters _being hit temporarily in the start of the test_ (often just PPT limiter is hit). However write bandwidth was not affected by running alongside AMD monitor (it was 30388-30392 just as previously). And during _most of the test_ EDC current value = 90A = EDC limit. No other "current value" is close to its respective limits, so kinda strange other limiters engage.
I wonder if anyone with perfect Aida Write bandwidth can confirm they don't hit limits or limiters in AMD Monitor during that test? @craxton @sendap ?

While I was at it I also ran latency tests. It dropped latency by 4ns to 68+, but it showed no limits being hit. Also it showed that latency test is probably only about read latency, as DRAM writes were near 0 after short spike at the start of the test, while DRAM reads were consistently near 1.5 during the test but near 0 before and after it.


----------



## Veii

Robostyle said:


> Problems with accessing RAM rows?
> I've tried running it with admin rights, withal killing all the 3rd processes, leaving win native + drivers like nvm, etc.
> Besides, 0.7.7 doesn't have problems, even after 0.7.8











If everything really is stable - then it can be an access permission issue
Antivirus or Windows Defender 
If even launching it from an USB doesn't fix it, then it's user error
I strongly hope it's extracted, but if it can not load Kagari algorithm ~ it has to be windows or RAM


----------



## CarnageBT

Got a 4000 set running on 15's now BUT, now I started getting WHEA errors, specifically error 20. I disabled PBO and any CPU OC's and ran the test with otherwise the same settings, still WHEA error 20, they come in groups of 101 at a time lol. Haven't solved it yet, but playing with CCD / IOD voltage seems to help


----------



## Robostyle

What's the fastest way to check DIMMs for integrity nowadays? Is it still memtest86?


----------



## CarnageBT

Robostyle said:


> What's the fastest way to check DIMMs for integrity nowadays? Is it still memtest86?


Wish I knew. I just finished binning 6 dimms. Ran each through TM5, 25 cycles, in slot dimm slot A2. Doesn't take as long as a full setup, around 65m / stick.


----------



## craxton

XPEHOPE3 said:


> with perfect Aida Write bandwidth can confirm they don't hit limits or limiters in AMD Monitor during that test


ill check in just a moment and let you know, usually tho i cant keep AMD monitor using "tool.exe" 
open when running a benchmark. 
almost 100% positive something "besides" my antivirus is blocking parts of the AMD tool from reading 
certian things on my board. 
since i did copy most my old files to a different drive and reflashed windows to the old drive i believe
it might start there. did install a new OS on another drive but did not however remove the other drives to elminate 
any other services "not being shown" in task man/service.msc



CarnageBT said:


> specifically error 20.


check here, 
"event viewer" event viewer local, then hit "error" then hit WHEA-LOGGER 
not the one where you go to apps and service logs. when ive gotten WHEA-20 
it was a core crashing "hard crash" 
if it shows up, then it should tell you what core (if its that) is crashing.


----------



## craxton

Robostyle said:


> memtest86


id steer clear of memtest86 for the most part.
TM5, HCI, prime95 small FFT should be fine, 
TM5 is what youve been told several times now however,
so maybe take that advise? 25 cycles, 1usmus config, dont touch the machine. 
(running your stable or believe to be stable) ram profile.
TURN OFF your antivirus completely if you haven't and try running y-cruncher again. 

its gotta be the culprit. by default tamper protection will be on and im sure thats whats stopping you


----------



## DeletedMember558271

So 1.2.0.3b unsurprisingly doesn't fix FCLK holes or WHEA for me.
It's kinda crazy no one including AMD have figured out or fixed at least FCLK holes. 1867 and 1933 boot effortlessly with everything on auto or what I currently use for 1867, but 1900 is just impossible.
Its got to be some behind the scenes paramater/training issue that is automatically and incorrectly setting itself, when it sees 1900 and says "alright I'm setting X to Y now" which just doesn't work and can't do anything about it or have any control over it. It's so dumb. Doesn't matter if I try to boot it 10 or 20 times, if its training it never figures itself out.

One other thing for WHEA I remember seeing someone say is they disabled their USB Asmedia hub or something in BIOS, I don't have any option to disable any USB in BIOS to try.
Haven't seen any seen another possible solutions for FCLK holes or WHEA to try that I can or haven't already, keep looking here in the hopes someday someone finds something about either.

These are the 2 problems Zen 3 has and after all this time there's still really nothing interesting going on with figuring them out, everyone is still clueless not any closer to figuring out or fixing anything


----------



## craxton

@XPEHOPE3 
if by limit you mean 
then i cant say i hit near 160 lol.
i am running telemetry offset in the bios tho. 
upon the "start" of L2 and L3 tests i seen it quickly "peak out" 125
and stay near 80-100 for most the test. 
L3 was mostly above 100.

if you wish, ill limit EDC to 90. but im rather sure it wont be much difference.










(HERE) is me limiting EDC to 90 while moving PPT up to 130.
(spoiler that it made no difference. keep in mind i did NOT kill any tasks/services during this
run or the last.)


----------



## Robostyle

craxton said:


> youve been told several times now however,
> so maybe take that advise?


try to re-read my last posts. 
I figured 0.7.8 already..


----------



## craxton

Robostyle said:


> What's the fastest way to check DIMMs for integrity nowadays? Is it still memtest86?


Nope, this is your "last post" so...
Good luck figuring out your issue. Unless by 0.7.8 you mean you no longer have issues now, as I stated that the "latest version" of y-cruncher fixed issues for Ryzen crashing in an earlier post (to you)
Then by all mean good job.

But, since your still looking for an answer on "what to use" for ram testing. Well, TM5 1USMUS V3 CONFIG 25 CYCLES, HCI MEMTEST, PRIME 95 SFFT, (HCI first to 1000%, then tm5 (with 1usmus preset config otherwise when you get an error you'll be on your own for not taking the warning that the errors on 1usmus config has been figured out for the most part) and anta777 config well, mostly on your own if you error on a number. As those random "numbers" tell what's giving the issue) then prime95 sff (overnight at the least) limit your ppt tdc, edc values otherwise you'll be able to "fry an egg" same goes for y-cruncher which you wud test last using 1-7-0, might be advisable to use OCCT, cpu-data set large, mode-extreme, load type steady, auto instruction set, and auto cores unless you wish to run them all. (This will check for whea 19 errors and etc.)

Now, re-read your last post and you'll notice it's been a few "questions of the same response" that u mentioned y-cruncher failing. It's not y-cruncher giving you an error. Your miss using y-cruncher lol. Latest version, again 1-7-0 best to let it pass 5-8 cycles. 4 minimum.

If you can't take this response then I'm almost certain nobody else will reply. As everything I just mentioned (maybe in more detail) has been stated alot throughout this thread.


----------



## XPEHOPE3

@craxton 
I meant the following:

Setup your PC like you previously did to ensure you have perfect results of Write bandwidth Aida test (perfect means 16*FCLK - 1 or - 2, in your case 31999 or 31998). I saw you hitting those earlier! 😅
Run AMD Monitor, close other windows from that tool archive (like Per CCX monitor), and focus on "Frequency Limiters" (PPT, TDC) and "Voltage Limiters" (FIT PID) sections.
Start Aida, go to memory tests, double-click on Write bandwidth cell and check if values from 2. drop from max (4.85 in your case) while the test is running.
I expected they wouldn't drop should you score perfectly (and would drop should you not). If you can't spot it, try running several times (monitoring software can't catch every change).
The drop *only for a moment*, so it's very hard to make a screenshot, and _probably _may even be hard to spot with low monitor refresh rate (I have 240Hz).
EDC limit is also interesting, but from your test it's clear you won't hit it


----------



## craxton

@Veii 
what was your CPU profile score?
(without killing all the background tasks and stuff) 
this is mine. I scored 0 in CPU Profile










(anyone else with a 5600x got some scores to share on CPU side)?


----------



## PJVol

Veii said:


> Seems to be a good Curve Optimizer test


Yeah, crashed once as well, but that was purely my mistake.











craxton said:


> anyone else with a 5600x


Yep, currently 6th 2nd (out of 5600's)


----------



## craxton

XPEHOPE3 said:


> @craxton
> I meant the following:
> 
> Setup your PC like you previously did to ensure you have perfect results of Write bandwidth Aida test (perfect means 16*FCLK - 1 or - 2, in your case 31999 or 31998). I saw you hitting those earlier! 😅
> Run AMD Monitor, close other windows from that tool archive (like Per CCX monitor), and focus on "Frequency Limiters" (PPT, TDC) and "Voltage Limiters" (FIT PID) sections.
> Start Aida, go to memory tests, double-click on Write bandwidth cell and check if values from 2. drop from max (4.85 in your case) while the test is running.
> I expected they wouldn't drop should you score perfectly (and would drop should you not). If you can't spot it, try running several times (monitoring software can't catch every change).
> The drop *only for a moment*, so it's very hard to make a screenshot, and _probably _may even be hard to spot with low monitor refresh rate (I have 240Hz).
> EDC limit is also interesting, but from your test it's clear you won't hit it


144hz should be enough lol, but im unsure if your wanting to know if im hitting (what limit on EDC?)
or if im falling under a said limit?
(THIS?) or the second shot?








(dont mind the latency but i think this is what you want? i didtn circle it, but clicking the first cell is where i notice drops on PPTs 4850 and FIT PIDs 4850 
youll see both on what im talking about if thats what your speakin on. as for double tappin the second cell, FIT PID dropped to 4836? something like that.
this is with chrome open and a few other things, but a few other things as well being killed in task man services.
(thats why the latency is high as a mofo. but i dont aim to kill services that for some reason 
upon a reboot wont restart any longer and break windows updates all together, but do make latency around 51.6/51.9 depending on 
if i can keep said services from restarting, in safe mode consistent 51.6 98% of the time. the shot you seen, was a safe mode shot i do believe 
or was when windows didnt need the "added bloatware" it has now to stay running. (still running that tele offset in bios)


----------



## craxton

Veii said:


> Seems to be a good Curve Optimizer tes


idk if i can speak on it being "good" as im running -20 all cores except 4 and 6
with a +1 offset to voltage. but have NOT had any crashes running prime wide open, occt etc....



PJVol said:


> Yeah, crashed once as well, but that was purely my mistake.


no crashes for me, but i didnt kill everything to give more room for the CPU
to stretch its legs...



PJVol said:


> Yep, currently 6th (all 5600x)


congrats, seems as if im 22nd after killing just the normal stuff i usually run at startup.
still tho, noway my CO offsets of -20, and -9 core 4 and -16 core 6 with +1 step offset voltage is stable....
















5th run for me, still no crashing.....ODD VERY ODD maybe the offsets i have now are more inline with what they should be
R23 scores are over 12000 now voltage isnt peaking over 1.45 temps are staying in check....idk


----------



## PJVol

craxton said:


> congrats,


Thanks, actually currently 2nd (out of 5600's) 








Result not found







www.3dmark.com


----------



## craxton

PJVol said:


> Thanks, actually currently 2nd (out of 5600's)
> CPU Profile


NICEEE, well after running some OCCT per core, turns out 4 (0 being 1)
is unstable as usual....... but this is the major thing i noticed....NEVER seen it use this much?
yes its colorful and perhaps that purple is not so easy to see. noen the less hitting 20watts on core 0.
22 watts on core 3


----------



## Veii

craxton said:


> @Veii
> what was your CPU profile score?


Last two posts had 2 different pictures
The leaderboard is strange, it only focuses on the allcore ?
I blame my cooling being sub-optimal, in loosing strongly on all-core tests (should blame my lack of per-core CO tho)

Funnily i beat everyone except one two on 8 threads loads
Single Core everyone seems to be limited at 970/971 = 4.85Ghz
Haven't seen anybody run CTR, but potentially that's a better way to score high

Not happy with the score
Will let you know, once i'm done with 3800 and move upwards
Maybe the issue is just lack of powerbudget , because of high SOC voltage








^ one guy who beats me on 8 threads








Two guys actually
Market score is better but says #34








The wegpage says #36 , no idea what's up with that


Spoiler: Silicon score 116














i'll take care of it once 3800 passes consistently TM5 & i figure the tRAS scaling issue on Rev.E
EDIT:
I think i'll play today with it ~ have the whole day nothing to do


----------



## Nighthog

Veii said:


> i'll take care of it once 3800 passes consistently TM5 & i figure the tRAS scaling issue on Rev.E
> EDIT:
> I think i'll play today with it ~ have the whole day nothing to do


tRAS scaling issue? what do you mean?

The earlier settings you asked me to test on the Rev.E kit, gotta ask. Are they as low as they go for you or can they do better?
Because my kits have all done much better on the sub timings in general. The settings you had were quite relaxed to be said.


----------



## Veii

Nighthog said:


> tRAS scaling issue? what do you mean?
> 
> The earlier settings you asked me to test on the Rev.E kit, gotta ask. Are they as low as they go for you or can they do better?
> Because my kits have all done much better on the sub timings in general. The settings you had were quite relaxed to be said.


I need to use a funky tRAS "rule" else it has stability issues
Either you got very great Rev.E
or maybe on A3 PCB
Mine where on A2 ~ bought them initially, as i was looking for a custom micron PCB (and b-dies, but they ended up Rev.E)
This wasn't it sadly. I never had luck with RAM to begin with ~ all of the ones i own, where mediocre to "bad" binns, even if some scores published look decently good

tCCD_L for me is 7 on them, and there is no access to SubUrg and UrgRefresh mode on this Bios (ASRock B550 ITX/AX)
Soo tFAW has to run as tRRD_L *6 or tRRD_S*7 ruleset
(can not use 1x or 4x modes at all)

Same for timings have to run as tBURST = 7 , 4 doesn't work nor 6
tRAS currently is far higher than it has to be. tCWL goes easily down to 10, but tCL 12 was only 3667 as peak (bad perf on 10 & 12)
tRCDRD 18 on 4000 doesn't work ~ but i want to try and bruteforce it

I'd say, it's as low as it goes right now with the primaries, but i find it fascinating that tRCD 21 scales for you from 4400 till 4800+
For me the 200MT/s = +1 tCL , +1 tRCD, remains applying

Really makes me wonder about your PCB. Or you got some fantastic Rev.E's
We both should run 2018/2019 revisions of them, but likely i got the lower barrel as always 

EDIT:
tRRD and tWTR as always are failsafe till i get that st*pid 18 to run at 4000
Afterwards i'll scale up
Was trying a lot to get tCL 12 to run, but no dime. Soo the focus is 3800 rock stable (has random CAD_BUS issues #1 & #14) and then 4000 tRCD 18 rock stable
~ afterwards i'll move to 4200 and later tamper in the 2:1 territory (as bioses still are booring)

EDIT2:
Actually, my other goal aside 4000 tRCD 18, was to figure out that 300ns tRFC wall ~ what's exactly up with that
But yes, so far kind of running the failsafe path @ 55.6ns


----------



## PJVol

craxton said:


> NICEEE, well after running some OCCT per core, turns out 4 (0 being 1)
> is unstable as usual....... but this is the major thing i noticed....NEVER seen it use this much?


There's HWINFO64 update 7.05-4495, with added per core temps. And pls, get sensor panel back to how ordinary people used to see it, lol
(unless you wanna make it unreadable and sight-damaging).
Looking at what I could barely make out:

Why you have such low power reporting accuracy ? (did you mess with vdd cpu full scale, by a chance)
would you mind to make screen of Core VID's in CBR23 multi (so, that measurement period was within bench run time)? Same as in this post: Guide - Fully optimise your PBO
And better post it there as well.


----------



## Nighthog

Veii said:


> I need to use a funky tRAS "rule" else it has stability issues
> Either you got very great Rev.E
> or maybe on A3 PCB
> Mine where on A2 ~ bought them initially, as i was looking for a custom micron PCB (and b-dies, but they ended up Rev.E)
> This wasn't it sadly. I never had luck with RAM to begin with ~ all of the ones i own, where mediocre to "bad" binns, even if some scores published look decently good
> 
> tCCD_L for me is 7 on them, and there is no access to SubUrg and UrgRefresh mode on this Bios (ASRock B550 ITX/AX)
> Soo tFAW has to run as tRRD_L *6 or tRRD_S*7 ruleset
> (can not use 1x or 4x modes at all)
> 
> Same for timings have to run as tBURST = 7 , 4 doesn't work nor 6
> tRAS currently is far higher than it has to be. tCWL goes easily down to 10, but tCL 12 was only 3667 as peak (bad perf on 10 & 12)
> tRCDRD 18 on 4000 doesn't work ~ but i want to try and bruteforce it
> 
> I'd say, it's as low as it goes right now with the primaries, but i find it fascinating that tRCD 21 scales for you from 4400 till 4800+
> For me the 200MT/s = +1 tCL , +1 tRCD, remains applying
> 
> Really makes me wonder about your PCB. Or you got some fantastic Rev.E's
> We both should run 2018/2019 revisions of them, but likely i got the lower barrel as always
> 
> EDIT:
> tRRD and tWTR as always are failsafe till i get that st*pid 18 to run at 4000
> Afterwards i'll scale up
> Was trying a lot to get tCL 12 to run, but no dime. Soo the focus is 3800 rock stable (has random CAD_BUS issues #1 & #14) and then 4000 tRCD 18 rock stable
> ~ afterwards i'll move to 4200 and later tamper in the 2:1 territory (as bioses still are booring)
> 
> EDIT2:
> Actually, my other goal aside 4000 tRCD 18, was to figure out that 300ns tRFC wall ~ what's exactly up with that
> But yes, so far kind of running the failsafe path @ 55.6ns


I'm guessing it's your motherboard that is more at fault than anything. I've heard about funky behaviour on ITX and specifically ASROCK in general with Memory overall.

@3800MEM 1900FCLK
My kits have all done 4-4-3-8 for tRRDS-tRRDL-tWTRS-tWTRL, tFAW is usually dependent on having correct DrvStr values to do *4 tRRDS. If you can't set them correctly you need to use ~32 tFAW at best before instabilities kick in. The needed DrvStr has been different between all the kits I've tested so you need to experiment around.

AMD AGESA version also plays into it if you can get it stable at all *4 tFAW even with the right DrvStr values.
I've struggled with it often when they didn't want to align. (changes in AGESA always effect this so need to check this every update it's still working)

tRDRDSCL-tWRWRSCL 2-2 should be possible. My kits have no trouble with it if I give them enough voltage. 1.500-1.600V range is enough for it to work on the kits I've tested.

tRFC... depends on the kit quality. bad bins do 300-305ns. While better kits can do 280-290ns I've seen.
Still not tested the new kit how low they go but 288ns was OK which is in parity with my Rev.J has done as best. 
For example my older 2018 Rev.E does ~305ns only.

This new Crucial kit has the better qualities of my both HyperX 2020 Rev.J & 2018 Rev.E kits with extras added on top.


----------



## T[]RK

mongoled said:


> I cant answer that as I am not sure if "DF-CStates" is the same as "Package C6-State" as is defined in ZenStates.


So, i finally was able to test it. Indeed "Power Supply Idle Control" is connected to "Package C6-State" in ZenStates 2.0.0. I also tested "DF-Cstate" with "Power Supply Idle Control". Here is small table:


ZS Package C6-StateEnabledDisabledPower Supply Idle ControlLow CurrentTypical CurrentDF-CstateDisable\EnableAutoDisabled\Enable\Auto


Screenshots:
*Low Current + DF-Cstate* (Auto/Enable/Disable)




















*Typical Current + DF-Cstate* (Auto/Enable/Disable)




















Connected @Veii post:








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Does it matter that mine are 16GB dimms? --- What would that be? (sorry to ask, kind of a noob on memory fine tuning) I am not running them right now, and this was really kind of half assed on the timings, but: I don't know how well PBO really helps or hurts the numbers, but that is...




www.overclock.net


----------



## ManniX-ITA

Robostyle said:


> try to re-read my last posts.
> I figured 0.7.8 already..


y-cruncher doesn't have external dependencies that I know of, 0.7.8 introduced a new compiler and optimizations for Zen2
I'd investigate what's wrong cause it's very likely the CPU is faulty and needs RMA
But first would be better to re-check again the memory
Test with OCCT and also with CoreCycler/P95, SSE/AVX/AVX2 with focus on AVX2


----------



## Veii

Nighthog said:


> AMD AGESA version also plays into it if you can get it stable at all *4 tFAW even with the right DrvStr values.


Yes








It depends what the bios sets publicly and not publicly about UrgRefLimit & SubUrgRef

With modification on them on the ASUS 4 dimm board, it changed tFAW behavior
Since 1201 changed IMC FW across the whole range Ryzen CPUs + Ryzen Microcode updates,
it changed 4* tFAW behavior


Nighthog said:


> I'm guessing it's your motherboard that is more at fault than anything. I've heard about funky behavior on ITX and specifically ASROCK in general with Memory overall.


Being a board issue or dimm issue - wouldn't change it's behavior out of random completely , forcing me to redesign sets, voltages & resistance
The board plays a role on high frequency, but doesn't play a role on low MT/s - low being sub 4600MT/s
It's not a "first time notice", and not a "single kit" issue 

ASRock's bios so far is the most stable out of the 5xx board lineup, but also the most booring one with least added functionality and most removed functionality
Yet it did not do anything positive or negative for MemOC
The 4 dimm daisy chain board made a difference ~ but i wouldn't call it negative. It just changed RTT requirements.

Once/If the ASRock Bioses get unlocked ~ there would be like AMD intentioned from the beginning "no functionality difference between board-manufactures"
Yet i can not judge anything against ASRocks, ASUS, MSI's or Gigabyte's side
Across all the brands, AGESA wise ~ it has negatives and memory training issues you can go around (if the CBS options appear)
But still i can not blame the brand of the board, for the memory behavior. It's pretty much identical when we speak lower or equal to SMU 56.44 (or 56.45 pre new microcode)

I'd like to blame nearly every board-manufacture for disabling valuable features in AMD CBS ~ or copy/moving "broken" links to the main OC menu with "broken" hex-to-decimal translations
But yet can not judge anybody, for their functionality of the HW supplied (aside from old NIC revision issues ~ combined with a big supply contract and multi revision boards)


----------



## Nighthog

I noticed the B550MH with the 3800X can do GDM:disabled 1T @ 5000Mhz on the Crucial 4400 CL19 kit right now.

Quite unexpected to be said it worked at all. I was at first struggling to get above 4866 to even boot but now sitting with quite reliable @5000Mhz 1T.
No luck to get 5100Mhz to boot yet though.

There are still quirks with POST where it fails quite often and need a few retries. Trying to work out the kinks with it and lowering timings as I test slowly checking it's still stable.


----------



## Veii

Nighthog said:


> There are still quirks with POST where it fails quite often and need a few retries. Trying to work out the kinks with it and lowering timings as I test slowly checking it's still stable.


If you have CBS Access to MBIST - you can better up memory training
And if you push CsOdtDrvStr to 30-40 , it fixes memory training issues on Vermeer 
24 was recommendable for Matisse , 30-40 was needed for Vermeer


----------



## Nighthog

Veii said:


> If you have CBS Access to MBIST - you can better up memory training
> And if you push CsOdtDrvStr to 30-40 , it fixes memory training issues on Vermeer
> 24 was recommendable for Matisse , 30-40 was needed for Vermeer


Yeah I have the CBS MBIST settings for training, never figured how they worked so haven't really messed with them other than the pattern bits value to test for "no effect"


----------



## Veii

Nighthog said:


> Yeah I have the CBS MBIST settings for training, never figured how they worked so haven't really messed with them other than the pattern bits value to test for "no effect"


They are also in hex
You want pattern testing to "both"
Pattern bits to A (hex) or to 9
And one down to i think 5 is the next one
1-5-9 or 1-3-9 up to how the bios shows it
The 2nd instead of 1 is what you want to set

This betters up memory training a bit, and takes 2.5-3sec to post
If you enable data-eye training, which is a good thing ~ training will take 50-60sec
And this is too much, soo above settings are a good middle ground


----------



## PJVol

*@Veii*
Recently, while reading *The Stilt '*s post about Zen+, I remembered that 163 "Cooler Score" from your "tool" > AMD V/F, and have an assumption what it might mean.
He wrote that according to AMD, processors' TDP is defined as Tcase.max - Tambient.max / Rtherm (thermal resistance of the cooler), and for the 105W rated 2700X they are 61.8°C, 42°C and Rtherm 0.189°C/W, and AFAIK 2700x cooler beefier than "wraith". So I came to conclusiuon that "cooler score" may actually be its Therm. resistance * 1000.
I.e. wraith may well fit to 163 score. What do you think?


----------



## Robostyle

ManniX-ITA said:


> y-cruncher doesn't have external dependencies that I know of, 0.7.8 introduced a new compiler and optimizations for Zen2
> I'd investigate what's wrong cause it's very likely the CPU is faulty and needs RMA
> But first would be better to re-check again the memory
> Test with OCCT and also with CoreCycler/P95, SSE/AVX/AVX2 with focus on AVX2


Seems like 0.7.8 has conflicts with Win10 or some kind of ram allocation bug.
It was enough to lower the ram pool by a mere ~400MB from what it takes automatically.



Spoiler: st















And it's not a hard limit though - it always needs to manually lower memory limit by a bit from what it allocates, no matter if its 29GB or 13GB.


----------



## XPEHOPE3

craxton said:


> (THIS?) or the second shot?
> 
> 
> 
> 
> 
> 
> 
> 
> (dont mind the latency but i think this is what you want?


Almost there  I circled limits I was initially interested in. They are probably hit during Write Bandwidth test, that is, while "Please wait" is shown where I pointed in screenshot.







Since you hit perfect score now, those limits would probably not be hit (that is - show 4.85 constantly, while EDC current value being less than 240)


----------



## XPEHOPE3

Nighthog said:


> Doing 5000Mhz 18-23-23-46-120 @ 1.580V stable for the moment it looks like, just need a longer test-run to see everything is fine before more tuning is done.
> Here is a screenshot it did 20-23-23 all good. (tCL-tCWL 18-18 worked just as good everything else the same)


Did you try 1933 or 1866 FCLK (with all other settings being the same) to see if Aida latency would improve?


----------



## Nighthog

Nighthog said:


> It was the cheapest 2dimm B550 board around when I bought it, most likely still is.
> 
> Though it can't really handle the 3800X, you need to limit it for 80Watts if you don't want issues with VRM throttling. (though you can disable the limit for thermal runaway if you really want all the performance)
> Additional cooling for VRM area is a requirement for anything else than 65watt TDP CPU's/APU's.
> 
> I really should be changing the cpu's on my systems, the 4650G to the B550 and the 3800X to the X570 Xtreme.


Hey! Good news!

I found a new setting in the BIOS that allows you to set your own VRM temperature limits!

*A.I. TP Control* [Hardware Monitor]
High temperature limit 40-125C
Low temperature limit 40-125C

High temperature sets the limit when throttling shall occur and the processor downclocks to 550Mhz and then when the VRM hit the Low temperature limit it allows normal clocks again.
This is better than setting the LLC setting which disabled the temperature sensor altogether from earlier experience if you want burnt toast.

Cinebench R23 will still kicked the VRM @ 100C after a couple minutes. As a test run I did.
Can set better limits than the stock 84C (79C) that was tripped by cpu-z bench.

Can do some more better benches like this 
Rather than only test stability as the board was a suprise for MEM OC.


----------



## byDenoso

Veii said:


> I need to use a funky tRAS "rule" else it has stability issues
> Either you got very great Rev.E
> or maybe on A3 PCB
> Mine where on A2 ~ bought them initially, as i was looking for a custom micron PCB (and b-dies, but they ended up Rev.E)
> This wasn't it sadly. I never had luck with RAM to begin with ~ all of the ones i own, where mediocre to "bad" binns, even if some scores published look decently good
> 
> tCCD_L for me is 7 on them, and there is no access to SubUrg and UrgRefresh mode on this Bios (ASRock B550 ITX/AX)
> Soo tFAW has to run as tRRD_L *6 or tRRD_S*7 ruleset
> (can not use 1x or 4x modes at all)
> 
> Same for timings have to run as tBURST = 7 , 4 doesn't work nor 6
> tRAS currently is far higher than it has to be. tCWL goes easily down to 10, but tCL 12 was only 3667 as peak (bad perf on 10 & 12)
> tRCDRD 18 on 4000 doesn't work ~ but i want to try and bruteforce it
> 
> I'd say, it's as low as it goes right now with the primaries, but i find it fascinating that tRCD 21 scales for you from 4400 till 4800+
> For me the 200MT/s = +1 tCL , +1 tRCD, remains applying
> 
> Really makes me wonder about your PCB. Or you got some fantastic Rev.E's
> We both should run 2018/2019 revisions of them, but likely i got the lower barrel as always
> 
> EDIT:
> tRRD and tWTR as always are failsafe till i get that st*pid 18 to run at 4000
> Afterwards i'll scale up
> Was trying a lot to get tCL 12 to run, but no dime. Soo the focus is 3800 rock stable (has random CAD_BUS issues #1 & #14) and then 4000 tRCD 18 rock stable
> ~ afterwards i'll move to 4200 and later tamper in the 2:1 territory (as bioses still are booring)
> 
> EDIT2:
> Actually, my other goal aside 4000 tRCD 18, was to figure out that 300ns tRFC wall ~ what's exactly up with that
> But yes, so far kind of running the failsafe path @ 55.6ns


Can you explain me When, How and Why use 1x TFaw mode?


----------



## Veii

Soo, finally 
That was TM5 verified run #5 in a span of last two weeks

Funnily RTT_WR /2 , managed to stay in sync with the SETUP times ~ this time
Rev.E does seem to fail for me consistently only after 1:30-2:00 hours, soo 16-20 loops ~ but it will post close to every timing, just fail after time
This time i got it to work , and funnily it even retained stability + lowered latency ~ with SETUP timings
Guess it was unstable all along @ 55.6ns before
* Ambient = 28c








About Windows 11,
Taking into consideration all the past events and core-layout remap issues before
It makes me really wonder, why AMD decided to use one core with the 2nd CCD ~ and might even be labeled as core #1

I'd want to wait for @KedarWolf 's take on 21996.1 too, to doublecheck how "broken" really the thread schedular is ~ before continuing any fighting against MS or AMD
But something is awkward to say at least
That Win11 misses AMD patches is pretty much a fact ~ tho games do not reflect it
That my sample is strange, is also a fact

But if Windows without CPPC Preferred and with ~ decided to use the 2nd CCD core, it actually might explain this horrible bandwidth & windows 10 could just "bypass" it, or rather go around the issue"

Anywho , stable is stable ~ already known from before screenshots with different CAD_BUS & RTTs
This time just slight bit redone powering 😃

EDIT:
I probably should attach the original screenshots too, so you can check 3 things

How is SOC pulling 70A ? I know 2nd CCD pulls 30A for itself when initialized
Explanation & Illustration for the frequency held / old topic about using TM5 for CO boost checks
Just verification because windows overlap here for cleanness



Spoiler: Original Screenshots [TMP]


----------



## CarnageBT

General question. When working to improve Aida scores, which values are most important? Read vs write vs latency? etc? is there a hierarchy?

Asking because some settings, ie, SCL 2 vs 4, lowers read by around 150mb/s, but increases write by 150mb/s, so its a trade off.


----------



## FleischmannTV

@Veii 

Holy moly, I've never seen such SOC\VDDG voltages for IF1900.


----------



## Robostyle

FleischmannTV said:


> @Veii
> 
> Holy moly, I've never seen such SOC\VDDG voltages for IF1900.


Mine needs 1.2 SOC and 1.1 vddg(not sure) for IF1900...


----------



## byDenoso

Robostyle said:


> Mine needs 1.2 SOC and 1.1 vddg(not sure) for IF1900...


Is 1.25v for SOC safe for a R5 3600 24/7?


----------



## PJVol

Veii said:


> It makes me really wonder, why AMD decided to use one core with the 2nd CCD ~ and might even be labeled as core #1


Where did you get that? And where is it reported of 70A of SOC ?
And...








If I conceptually am not wrong, your layout is
0 x 2 4
1 x 3 5
Even per core temps inline with it, your first two cores 53° and the rest are 55° thanks to "thermal isolation" from two "fused-out" ones 

RE soc power...
Perhaps your telemetry firmware mistakenly count fused-out ccd as part of total power budget, since vrm reported 19 amps correctly.
Dont know why it's not fixed yet...


----------



## Veii

FleischmannTV said:


> @Veii
> 
> Holy moly, I've never seen such SOC\VDDG voltages for IF1900.


Just a placeholder


Veii said:


> Couldn't be bothered to rerun 6h of stress tests, just for a "memory stability" experiment with low timings


 read linked quote 


PJVol said:


> Where did you get that ? And where is it reported of 70A of SOC ?


Last post, Spoiler








I know thanks to CTR that the 2nd CCD pulls ~16A in sleep-idle but not hibernation mode
Also thanks to old CTR core layout readouts , and old bugs - where RC03 broke my first core at 3.7
_before we sit together and work out a resolve + additions_

Checked my current USB's , but the picture from the first broken core is somewhere on OCN far back on my RC03 rant & warning
Tho it had many many rewrites and this is the Default by AMD supplied value (after the core-layout rewrite)








Yet combining clues, it seems like - it seems like either
A.) the Win 11 thread scheduler is beyond broken ~ but nobody is ready to play testing rabbit yet  @KedarWolf hopefully soon
B.) It was just the lack of Win 10 AMD patches, and it does only run one single core for L3 cache ~ which ends up being alone on the whole CCD
Yet again, game perf does not suffer ~ even improved slightly (feeling) but the OS is not CPPC aware as it seems , (i think)

Part 2 bellow:


----------



## Veii

PJVol said:


> And...


Aren't the numbers just the same value but with a different reading
Core 0 or 1st core = the same, no ?








I am not sure about the order of the 4 block, but if FIT values are correct
And knowing core 3 & 5 [0-5] are my best ones

It looks like Core 6 = C06,
but i am very unsure about Core 15 not being C01 = ACPI core 0 for the OS








Even TechYESCity reports good gaming perf on it, like other people
But nobody could give me an Aida64 screenshot. Something is not correct, even SiSandra reports issues
Something aside ACPI values "improved" after time, compared to RC03

So much towards "degradation" with "high" SOC


Spoiler






















Please understand me,
on one side i lost once the OS with old pictures and data/logs
On the other side i can not share every past experience, in order to keep a good friends-relationship up
Don't ask me further upon CTR parts or Dual CCD shenanigans
When i know/figure something new "by myself" out , i'll comment on it further

Currently still investigating it by/on my own
No idea how RSMU access works, no idea how SMU commands are layed out and miss a wide range of knowledge on PSP Firmware
One man army work, soo focus & motivation for focus ~ is shifting. Whenever time allows to stick my nose further into it ~ while currently there are other important projects in maintenance


Nighthog said:


> Maybe Agesa 1.2.0.3b finally fixed the WHEA issues for higher FCLK on 5000 series?
> 
> 
> Veii said:
> 
> 
> 
> Look them extending it to 2000, but causing issues with 2100+
Click to expand...

Knew it !
As always . . . i'm unsurprised and just disappointed by AMD
Before i'll title them something, i'd need to swap dimms and replicate my 48.5ns result on it
Yet Dimms can boot 4200 easily and are testable with








Timings ~ are high, by my dimms are what they are
I can not boot 2100 FCLK with Microcode 0A201016h on the same SMU 56.50 bios with the same ABL . . .
It keeps the settings, keeps the RAM frequency, but resets itself to 2667MT/s JEDEC @ any procODT ~ with voltages that are guaranteed to work on 2100 FCLK
Strongly disappointed 
Latency results in 52.7ns ~ potentially usable @ 2067 but lame to say at least


----------



## PJVol

Veii said:


> Last post, Spoiler


It obviously do misreport


Veii said:


> Aren't the numbers just the same value but with a different reading
> Core 0 or 1st core = the same, no ?


I just wanna show where the correct Core 0 Freq value is (on your tool's screenshot), aside from that, yes, the same.
As for layout, I meant physical cores layout, exactly as what CPU TOPOLOGY say.
I see this monitoring tool messing things up.
Ask Ivan Rusanov for SDT build with 380805 pm_table lables, he is kind guy 

PS: and if you wanna make sure which core is where on your monitoring tool, just run boosttester and watch for core temps.


----------



## Veii

PJVol said:


> It obviously do misreport











Where does 90W then go 


Spoiler: Lowest Idle






















I remember it was less ~ near the 30 range
(30W 2nd CCD, around 17-18A wasted for nothing)
tho i'm running a different microcode now

I didn't change SMU or ABL
For PMTable to break


Spoiler: Excuse me, but the math just works ~ for a missreport ?















EDIT:
According to HWINFO
SOC VRM Controller, pulls 22W under load. No 80W
Strange 

Whatever it is, it triggers too fast a 122A Fuse limit for allcore loads 
3D Mark does judge "peak allcore and 1 thread score" - just checked


----------



## PJVol

Veii said:


> SOC VRM Controller, pulls 22W under load. No 80W
> Strange
> 
> Whatever it is, it triggers too fast a 122A Fuse limit for allcore loads
> 3D Mark does judge "peak allcore and 1 thread score" - just checked


Yep, the voltage is correct, the amps is not. I'd try to adjust VDD soc_full_scale_current to match what VRM reports.
But hardly it would help with heavy loads (avx2) not to bump into other limits (EDC, etc)


----------



## Veii

PJVol said:


> Yep, the voltage is correct, the amps is not. I'd try to adjust VDD soc_full_scale_current to match what VRM reports


Just wanted to respond
Yes it was that one , from AMD PBS
Been driving both a bit too far
Makes me wonder how it affects FIT in reality
Dropped it to 90, it ended up as 15-16A
Pushed it now to 120A which is 23A in reality

Lost before FIT voltage sensors - soo might have found some bug
But i need to check if they do make any differences & if i can fake a lower value (or even negative), without triggering package throttle
2nd CCD will continue to waste energy while DF-C States are broken, but 2100 FCLK i can not boot at all anymore
I'll play a bit more, and likely fall back to the old microcode
Don't think it magically would work again on 1203A/B , but it feels like there is an FCLK lock again on the "latest" microcode ~ "latest" from April

Would be great if FIT PID could be overridden, generally if OPN number could be overridden to rebrand this unit finally
Haven't tried PBO boost override yet. Considering i lack some safety features/are broken ~ it maybe could push through beyond +200

* funnily 2101 FCLK with BLCK 101.5 runs , yet refuses to post 2100


----------



## PJVol

Veii said:


> But i need to check if they do make any differences & if i can fake a lower value (or even negative), without triggering package throttle


I'm afraid not much, I've spent some time looking for possible benefits, but with no avail. What you called "throttle" seem to have little to power management.
TM5 makes CPU reach my manually set 115A EDC limit almost instantly, and RAM is [email protected], let alone 4000+

Btw, forgot to ask  Does your Win 11 build work fine regarding ACPI power management? Does new scheduler has full control over CPU performance ? I mean has it have the access to CPB directly?


----------



## Ultranoc

Guys I am hopeless, I have no idea how to stop all the errors I get... even raised VDIMM to 1.45V, but it did not help 
I am crazy, what I can do? I thought 1900 FCLK is not that high, no?


----------



## KedarWolf

Ultranoc said:


> Guys I am hopeless, I have no idea how to stop all the errors I get... even raised VDIMM to 1.45V, but it did not help
> I am crazy, what I can do? I thought 1900 FCLK is not that high, no?


Try tRCDRD at 16.

The below works for me with 2x16GB dual ranks sticks.


----------



## craxton

PJVol said:


> (did you mess with vdd cpu full scale, by a chance


Yes, I've stated I'm running 10ma tele offset all over the place in my posts, and even mentioned it in the thread you stated posting to in the "quoted" comment below. 



PJVol said:


> would you mind to make screen of Core VID's in CBR23 multi (so, that measurement period was within bench run time)? Same as in this post: Guide - Fully optimise your PBO
> And better post it there as well


Nope won't mind at all, be one of the "last" runs I make since my 5800x came in today. Will know if the "tool.exe" works or not on my board correctly if it reads anything higher than 80 sil quality on the 5800x later this evening. ATM am at work on a 15 min break so itll be later until I post what your asking. 

None the less, my "per core" correct curve offset values score lower with the new bios than previous bios versions. (Version B for my board) where as I can run negative offset on core 3 (4 actual) now as to before I could not. But still failing on iteration 5-9 somewhere in there it'll fail. But all others are passing with what I've set currently. 

Which is what I previously mentioned while running the benchmarks we were comparing where you was number 6 I believe and I was number 22. 

No, I will not set it back to normal. But I will change the purple as it's hard for me to read 😂 as it stands currently Im able to see power draw per core without needing to scroll down at all. As I don't open multi page hwinfo.


----------



## craxton

Robostyle said:


> Mine needs 1.2 SOC and 1.1 vddg(not sure) for IF1900...


I'm running 2000fclk and only need 1.7 (1.6x in bios) with 980mv cc'd, and 950mv iod.... 900 cldo....but then again the overclocking capabilities of this chips TRASH and is showing hard core compared to most others 4650 all core oc with under 1.31v where mine is 1.35v and still failing on prime 95. On a "5600x" anyhow. Hopefully the 5800x I got today in the mail will be better on core and equal on IMC


----------



## PJVol

craxton said:


> since my 5800x came in today


Ok, nvm then


----------



## domdtxdissar

So.. Have been playing around with Windows 11, some results from me:

Forgot to show in screenshot, but this is *51.6 ns with both CCD enabled* and all 32 threads.



















Spoiler: Sandra results



SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 157.91GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 40.7ns (9.9ns - 63.4ns)
Inter-Thread (same Core) Latency : 10.0ns
Inter-Core (same Module) Latency : 20.9ns
Inter-Module (same Package) Latency : 59.6ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1540.01MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.88ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 33.69MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.8ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 22.0ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 19.0ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 19.7ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.6ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.4ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 61.8ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 62.2ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 62.0ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 61.9ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 61.5ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 61.7ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 60.9ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.7ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 10.0ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 18.5ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.4ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 19.1ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 20.1ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 19.7ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.9ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.5ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.6ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.8ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 57.6ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.4ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.0ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 58.1ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.6ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.7ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.1ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 19.4ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.7ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.1ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.9ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.7ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 56.5ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.5ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.5ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 58.1ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 57.9ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.7ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.4ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 18.9ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.9ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 19.1ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 19.4ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 19.7ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.1ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.4ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.9ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 56.5ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 56.5ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 57.5ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.6ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 58.1ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 57.9ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.6ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.5ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.8ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.7ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 21.6ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 21.2ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 57.2ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 57.2ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 58.2ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 58.1ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 58.7ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.6ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.3ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 59.4ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 19.6ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 19.1ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.9ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.8ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.8ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.5ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 21.6ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 21.2ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 57.2ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 58.5ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 58.1ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 58.2ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 58.5ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.7ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.2ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 59.5ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.5ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 20.8ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.2ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.6ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 57.3ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 57.3ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 58.1ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.2ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.9ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.6ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 59.6ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 59.2ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.6ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 19.4ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.8ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.5ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 20.8ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 21.2ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.6ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.2ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.1ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 58.0ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.1ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.7ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.4ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 59.4ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 59.2ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.2ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.2ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.9ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 58.0ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.6ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.7ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 59.1ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 59.3ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 59.7ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 59.9ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.4ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.7ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.7ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.9ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.2ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.2ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.9ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.9ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.9ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.5ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.7ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 59.1ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 59.2ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 59.8ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 59.9ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.9ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 22.2ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.0ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.7ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.8ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 58.6ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.2ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 59.0ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.9ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 59.7ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.4ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.1ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.8ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 21.2ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.9ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.9ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 22.3ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.3ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.9ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 59.0ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 58.8ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 59.4ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 59.1ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.9ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 59.7ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 22.4ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.5ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.8ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 59.4ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 59.5ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 60.0ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 60.0ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 60.5ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 60.4ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.1ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.6ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 20.6ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.8ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 20.6ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.1ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.9ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.7ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 60.2ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 59.7ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 60.2ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 60.2ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 60.0ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 60.4ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 60.5ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 60.3ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 59.9ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 59.5ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 60.1ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 60.4ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 60.3ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 60.5ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 60.7ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 60.1ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.8ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 21.1ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 20.7ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.5ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.2ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 22.0ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.7ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.9ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 60.0ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 59.6ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 60.0ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 60.5ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 60.5ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 60.6ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 60.6ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 60.1ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 22.2ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 22.5ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 21.7ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 22.0ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 21.2ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 21.1ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 61.4ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 60.0ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 60.7ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 59.7ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 60.0ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 59.9ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 60.3ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 60.1ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 10.1ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 22.2ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 22.5ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 21.7ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 22.0ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 21.2ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 21.1ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 21.6ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 21.1ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 21.2ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 21.1ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 21.0ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 21.5ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 60.7ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 59.5ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 59.9ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 59.6ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 59.8ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 59.3ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 59.7ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 59.6ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 22.2ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 10.1ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 21.6ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 21.2ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 21.2ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 21.0ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 21.0ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 21.5ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 21.3ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.4ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 21.0ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 21.0ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.2ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 61.4ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 59.9ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 60.3ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 59.7ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 60.0ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 59.7ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 59.9ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 60.0ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 22.5ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 21.6ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 10.1ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 21.3ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.4ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 21.0ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 21.1ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.2ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.9ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.3ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.3ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.9ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 60.7ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 59.6ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 59.8ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 59.8ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 60.0ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 59.8ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 60.3ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 60.5ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 21.7ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 21.2ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 21.4ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 10.1ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 21.0ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.3ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.1ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 21.3ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 20.9ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 20.9ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.2ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 61.5ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 60.1ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 61.0ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 60.2ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 60.5ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 60.6ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 60.5ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 60.9ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 22.9ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 21.7ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 22.1ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.8ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 10.1ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 20.9ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 21.0ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.2ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.1ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.2ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 61.3ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 60.2ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 60.6ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 59.9ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 60.7ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 60.3ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 60.5ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 60.0ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 21.7ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.7ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.8ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.9ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.0ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 10.1ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.1ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.1ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 21.2ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 61.5ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 60.4ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 60.7ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 60.2ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 60.8ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 60.3ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 60.6ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 60.1ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 22.1ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.9ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 21.3ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.9ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 20.9ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 20.9ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 10.1ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 21.2ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 61.1ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 60.1ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 60.4ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 60.0ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 60.3ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 60.3ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 60.3ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 60.1ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 21.1ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.9ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.8ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.2ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.0ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.1ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 21.2ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 10.1ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 23.0ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 23.4ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 22.4ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 22.8ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 21.6ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 22.2ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 21.0ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 63.4ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 62.3ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 62.9ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 62.3ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 62.7ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 61.8ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 62.1ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 62.0ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 22.2ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.8ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 21.3ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.4ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.6ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.9ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 61.3ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 60.3ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 61.0ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 60.5ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 60.5ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 60.3ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 60.5ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 60.5ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 21.3ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.8ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 21.0ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 20.7ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 61.6ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 60.8ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 61.2ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 61.0ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 61.0ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 60.9ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 60.1ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 60.3ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.9ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.8ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.5ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 59.8ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 59.7ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 59.9ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 59.6ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 59.6ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 60.0ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 60.1ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 60.1ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.8ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 20.6ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.2ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 60.3ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 59.8ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 60.1ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 60.0ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 59.8ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 59.9ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 60.3ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 60.2ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.1ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 22.0ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 59.8ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 59.4ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 59.8ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 59.9ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 60.0ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 60.3ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 60.3ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 60.2ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 21.7ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 60.1ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 59.8ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 61.4ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 60.2ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 60.2ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 60.7ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 60.7ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 60.5ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 60.2ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 59.7ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 60.1ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 60.4ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 60.4ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 60.7ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 60.7ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 60.2ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 22.2ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 22.5ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 21.7ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 22.0ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 21.2ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 21.1ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 21.6ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 21.1ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 21.2ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 21.0ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 21.0ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 21.5ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 21.3ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.4ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 21.0ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 21.0ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.2ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.9ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.4ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.2ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.9ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 21.1ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.7ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.5ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 22.5ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.2ns
1x 64bytes Blocks Bandwidth : 25.88GB/s
4x 64bytes Blocks Bandwidth : 27.09GB/s
4x 256bytes Blocks Bandwidth : 108.12GB/s
4x 1kB Blocks Bandwidth : 328.23GB/s
4x 4kB Blocks Bandwidth : 535.84GB/s
16x 4kB Blocks Bandwidth : 765.65GB/s
4x 64kB Blocks Bandwidth : 1TB/s
16x 64kB Blocks Bandwidth : 744.45GB/s
8x 256kB Blocks Bandwidth : 499.46GB/s
4x 1MB Blocks Bandwidth : 131.74GB/s
16x 1MB Blocks Bandwidth : 24.88GB/s
8x 4MB Blocks Bandwidth : 18.44GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.8GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 4kB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 4.8GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.8GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
Latest Version : A20F10-16
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Warning 5010 : Cannot use Large Memory Pages due to lack of privileges.
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 229 : CPU microcode update available. Check for an updated System BIOS with updated microcode.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.












CTR settings


----------



## craxton

PJVol said:


> Ok, nvm then


no no bud, here is what i think you were asking for. 

this is with what i ran the benchmarks we were talking about you getting 6th
and I 22nd. 

without this "tele offset" i drop HARD on all cores to 4.570ish 
none the less, i reset the colors but core power is under each core where 
its easier to be seen. 

ill have a new board on the way soon and will get a cheap gt710 just for the sake of CPU performance testing 
just to still tinker with th 5600x.


----------



## craxton

Veii said:


> Last two posts had 2 different pictures


mine? i know mine did, was comparing 5600x with 2070S ONLY 
which placed me #6?



Veii said:


> Single Core everyone seems to be limited at 970/971


nope im hitting 972 lol 
probably a gimp somewhere but i was toggling on and off overlay 
"or trying to" but it was LAGGING HARD..so i reran and tested again.



XPEHOPE3 said:


> Since you hit perfect score now, those limits would probably not be hit


well, the first pic i was talking about with my EDC limit the top left circle you mentioned 
i was not hitting over 120/125 while running any of the tests, and just the middle by itself, 1st by itself, and last by itself.



XPEHOPE3 said:


> I circled limits I was initially interested in.


i showed two shots of what dropped and what they dropped to. and what they peaked at. 
46xx something, and 125 ish EDC peak on another. 
but didnt affect score any, only thing ive seen make my "perfect" score drop is letting windows update service run, 
and a few other services as well. HWiNFO makes it slower sometimes too?


----------



## craxton

well, idk boys seems as if the 5600x i have is a GOLD IMC after all and can run WHATEVER 
IF frequency you toss at it...

  but it booted right up?


























(had a crash as SOC was auto, but anyhow here is now since i rebooted making sure all my "old stable" timings were correct
and well.....UGHHHH


----------



## craxton

oh this is WITHOUT adding a 200mhz EVERYTHING on cpu side is auto
besides SOC loadlines, and switching frequency.

(EDIT) UPDATE on those WHEA-19 there are almost 2thousand 500 yep 2500.
none the less, TOOL.EXE wasnt wrong either and worked fine was the 5600x that was hot trash on
sil quality.








(this is with AUTO) LLC on core, no voltage adjustments no 200mhz just PBO (i think PBO is on)
might not be. none the less, gonna run a few rounds of TM5 and see if this old "stable config" is still stable.
and if so gonna use Mannas WHEA suppressor to shut it up.



















(EDIT)
@ManniX-ITA
(whats your) "stock" no CO, no offset voltage, no 200mhz auto boost, just turn on PBO and leave it at that. score in R23??


----------



## craxton

@Veii OR @ManniX-ITA
(ive been able to STOP WHEA 19 for around 30 seconds
by stopping i mean, i UNINSTALL realtek driver COMPLETLY and turn OFF BTOOTH as well.
but i cant keep it from being re-installed. even tho windows updates are paused for 7 days.

i cant confirm that its 100% realtek causing it. but it does stop for a good bit after uninstalling the drivers from device man.
otherwise is 1-2 per second.

so is there a way to stop windows updates (or whatever is updating this driver by itself?)

(EDIT) unsure if this has been read and ignored, BUTTTTT 
ive managed to get some more sucess, it would seem raising IOD,AND CCD voltage (manually setting 1.8p voltage to 1.8
ive gotten WAYYYY LESSSSS WHEA-19. 
so, whoever has the least an hour, try raising your IOD, CCD voltages... i also raised CLDO_VDDG as well


----------



## Pictus

byDenoso said:


> Is 1.25v for SOC safe for a R5 3600 24/7?


Check AMD max overclocking voltage

For _*me*_, it is too much...
Better stay up to 3733MHz and 1.1V
And be careful with the CLDO VDDP, better set it to 0.900V


----------



## ManniX-ITA

craxton said:


> @ManniX-ITA
> (whats your) "stock" no CO, no offset voltage, no 200mhz auto boost, just turn on PBO and leave it at that. score in R23??


Do I really have to do that? 

I have a 5950x not a 5800x...
It's very low, my 5950x without tweaks sucks.
I'm also running at FCLK 2000, do you want to know at FCLK 1900 or 2000?



Dreamic said:


> So all you changed was your CPU and you have WHEA 19 now.
> Yet geniuses here think it's wise to ignore and disable based off nothing other than a *feeling* in their stomach that it's an unimportant motherboard issue, based off of nothing other than they think they're smart so place false confidence in their feelings and guesses and what they want to be true. Real scientific... I wonder why the investigations to possibly find out they are wrong stopped, where the desire for that went. Rather just live blind in willful denial or ignorance cause I want my high FCLK I guess.
> 
> What a stupid waste of time


Guess you are just looking for some attention...
As stated many times already we are still looking into it.
It's not easy and takes a lot of time. Just whining about it is childish.
We geniuses are trying to do something and avoid blabbing.



craxton said:


> i cant confirm that its 100% realtek causing it. but it does stop for a good bit after uninstalling the drivers from device man.
> otherwise is 1-2 per second.
> 
> so is there a way to stop windows updates (or whatever is updating this driver by itself?)


I'm not sure you can avoid it unless you can disable the peripheral in the bios.
But it's known that you'll still get WHEA even if you can disable both.
That's because the EFI firmware will be initialized and loaded during POST.

The rate at which you get the WHEA could be interesting.
What you can try is to forcibly install the wrong driver for those peripherals, like the Intel driver, then disable them.
This should avoid loading the Realtek driver.

I have changed my GTX 1070 for a RTX 3080ti and the high flow WHEA 19 is almost gone.
I still get them but at a much slower rate than before.



craxton said:


> (EDIT) unsure if this has been read and ignored, BUTTTTT
> ive managed to get some more sucess, it would seem raising IOD,AND CCD voltage (manually setting 1.8p voltage to 1.8
> ive gotten WAYYYY LESSSSS WHEA-19.
> so, whoever has the least an hour, try raising your IOD, CCD voltages... i also raised CLDO_VDDG as well


Yes FCLK 2000 for me needs IOD at 1140mV and CCD 1080mV.
Better to run benchmarks like Geekbench 5 and the monero miner to tune it and avoid performance degradation over FCLK 1900.


----------



## Mach3.2

craxton said:


> so is there a way to stop windows updates (or whatever is updating this driver by itself?)


Settings > System > About tab > Advance System Settings > Hardware tab > Device Installation settings > select No and save.


You can also disable this in group policy or registry editor if you want to be really sure Windows Updates isn't downloading drivers.








Automatic driver updates can cause problems — here's how to turn them off


In this guide, we'll show you the steps to disable updates for drivers through Windows Update using Group Policy and Registry.




www.windowscentral.com


----------



## craxton

ManniX-ITA said:


> Do I really have to do that?


nah wasnt thinking. i can disabled ALOT of stuff, i did 
however take pics of EVERY SINGLE SETTING 
that was set for the 5600x BUT auto is auto and we dont know *** auto means so some are uselss.
at 2400mhz stock there are no whea errors, all all cores but 2 i get 4970-4990 mhz so at least theres that (without CO) 
or adjusting anything simply adding 200mhz auto.



ManniX-ITA said:


> The rate at which you get the WHEA could be interesting.
> What you can try is to forcibly install the wrong driver for those peripherals, like the Intel driver, then disable them.
> This should avoid loading the Realtek driver.


will give that a try tomorrow as its near two and i gotta be at work at 8 in the morn lol bout
to hit the sack for the night, 
managed to lower the errors from nearly 5000 an hour (yea 5grand)
to a mear 30-50 so theres that?



ManniX-ITA said:


> Yes FCLK 2000 for me needs IOD at 1140mV and CCD 1080mV.
> Better to run benchmarks like Geekbench 5 and the monero miner to tune it and avoid performance degradation over FCLK 1900.


atm set all mine back to auto, soc, iod, ccd but that was BAD left cad_bus strenghs on auto, and the other one too.
seems to want near what i had preset already, but still SOC voltage is 1.12x and no cut out with the mouse there nor audio issues.
but still running OCCT or (SIMPLY) TM5 causes errors so theres something hard hitting 

ram timings that worked on my 5600x should in theory be 100% copied if im using the EXACT same kits and not moved said kits
to different dimms?


----------



## craxton

Mach3.2 said:


> Settings > System > About tab > Advance System Settings > Hardware tab > Device Installation settings > select No and save.
> 
> 
> You can also disable this in group policy or registry editor if you want to be really sure Windows Updates isn't downloading drivers.
> 
> 
> 
> 
> 
> 
> 
> 
> Automatic driver updates can cause problems — here's how to turn them off
> 
> 
> In this guide, we'll show you the steps to disable updates for drivers through Windows Update using Group Policy and Registry.
> 
> 
> 
> 
> www.windowscentral.com


im not running PRO win 10 just the normal base version for pesants but i got two keys for 20 bucks
(hard keys in a package) but will give this a shot and see the outcome tomorrow. thanks.


----------



## Nighthog

ManniX-ITA said:


> Yes FCLK 2000 for me needs IOD at 1140mV and CCD 1080mV.


I have a thought that the WHEA issue comes from the VDDG_CCD voltage.
My 3800X gets WHEA & AUDIO issues when I raise the VDDG_CCD voltage above 1000mV. Most WHEA are in the 1000-1050mV range. While AUDIO noise takes over above that but no WHEA. PCIE gets stutter (GPU gets FPS & latency spikes also above ~970mv-1100+)
VDDG_CCD voltage maybe causes some kind of crosstalk/interference and the noise drifts to different subsystems depending on the voltage range you use.

I often see people use above 1000mV on their VDDG_CCD and consider the experience I had with my 3800X if they aren't getting similar issues.


----------



## mongoled

WHEA issues are a combination of several pieces of hardware interacting together where the CPU role in this equation has a heavier "weight" than the other pieces of hardware.

If I was to quantify my "weights" it would be as follows

CPU: 70%
Motherboard: 20%
VGA: 8%
Others: 2%

Though most importantly is that all peripherals need to work in tandem to achieve "perfect sync" at chosen FCLK ....

Will join in the 3DMark 5600x fun tomorrow guys


----------



## mongoled

Nighthog said:


> I have a thought that the WHEA issue comes from the VDDG_CCD voltage.
> My 3800X gets WHEA & AUDIO issues when I raise the VDDG_CCD voltage above 1000mV. Most WHEA are in the 1000-1050mV range. While AUDIO noise takes over above that but no WHEA. PCIE gets stutter (GPU gets FPS & latency spikes also above ~970mv-1100+)
> VDDG_CCD voltage maybe causes some kind of crosstalk/interference and the noise drifts to different subsystems depending on the voltage range you use.
> 
> I often see people use above 1000mV on their VDDG_CCD and consider the experience I had with my 3800X if they aren't getting similar issues.


Very relevant and accurate, as is with all hardware the voltage requirement varies, the one thing I have noticed that really sticks out to me is the following.

When pushing high FCLK (2000+), its easy to see the effect vDDG CCD has on performance using LinpackXtreme, once CCD drops below a certain voltage GFlops will tank, problem is that when you run the CCD voltage required to stop performance from tankng you start getting other anomolies such as those you have described.

Using less CCD voltage smooths out these anomolies but at the cost of less performance, so its quite clear that something is getting "noisy" with the increased CCD voltage.

And ofcourse, we cannot just think of CCD by itself with regards to performance/anomolies, its in tandem with vDDG IOD and vSOC, so more pieces to play with in the hope of getting a stable 24/7 settings for high FCLK....


----------



## PJVol

mongoled said:


> voltage required to stop performance from tankng you start getting other anomolies


So true, regarding other voltages, based on my humble experience


----------



## domdtxdissar

domdtxdissar said:


> So.. Have been playing around with Windows 11, some results from me:
> 
> Forgot to show in screenshot, but this is *51.6 ns with both CCD enabled* and all 32 threads.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Spoiler: Sandra results
> 
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 157.91GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Average Inter-Thread Latency : 40.7ns (9.9ns - 63.4ns)
> Inter-Thread (same Core) Latency : 10.0ns
> Inter-Core (same Module) Latency : 20.9ns
> Inter-Module (same Package) Latency : 59.6ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1540.01MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 3.88ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 707.05kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 33.69MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 0.08ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.8ns
> U0-M0C0T0 <> U4-M0C2T0 Data Latency : 22.0ns
> U0-M0C0T0 <> U6-M0C3T0 Data Latency : 19.0ns
> U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.9ns
> U0-M0C0T0 <> U10-M0C5T0 Data Latency : 19.7ns
> U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.6ns
> U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.4ns
> U0-M0C0T0 <> U16-M1C0T0 Data Latency : 61.8ns
> U0-M0C0T0 <> U18-M1C1T0 Data Latency : 62.2ns
> U0-M0C0T0 <> U20-M1C2T0 Data Latency : 62.0ns
> U0-M0C0T0 <> U22-M1C3T0 Data Latency : 61.9ns
> U0-M0C0T0 <> U24-M1C4T0 Data Latency : 61.5ns
> U0-M0C0T0 <> U26-M1C5T0 Data Latency : 61.7ns
> U0-M0C0T0 <> U28-M1C6T0 Data Latency : 60.9ns
> U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.7ns
> U0-M0C0T0 <> U1-M0C0T1 Data Latency : 10.0ns
> U0-M0C0T0 <> U3-M0C1T1 Data Latency : 18.5ns
> U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.4ns
> U0-M0C0T0 <> U7-M0C3T1 Data Latency : 19.1ns
> U0-M0C0T0 <> U9-M0C4T1 Data Latency : 20.1ns
> U0-M0C0T0 <> U11-M0C5T1 Data Latency : 19.7ns
> U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.9ns
> U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.5ns
> U0-M0C0T0 <> U17-M1C0T1 Data Latency : 56.6ns
> U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.8ns
> U0-M0C0T0 <> U21-M1C2T1 Data Latency : 57.6ns
> U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.4ns
> U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.0ns
> U0-M0C0T0 <> U27-M1C5T1 Data Latency : 58.1ns
> U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.6ns
> U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.7ns
> U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.1ns
> U2-M0C1T0 <> U6-M0C3T0 Data Latency : 19.4ns
> U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.7ns
> U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.1ns
> U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.5ns
> U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.9ns
> U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.7ns
> U2-M0C1T0 <> U18-M1C1T0 Data Latency : 56.5ns
> U2-M0C1T0 <> U20-M1C2T0 Data Latency : 57.5ns
> U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.5ns
> U2-M0C1T0 <> U24-M1C4T0 Data Latency : 58.1ns
> U2-M0C1T0 <> U26-M1C5T0 Data Latency : 57.9ns
> U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.7ns
> U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.4ns
> U2-M0C1T0 <> U1-M0C0T1 Data Latency : 18.9ns
> U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.9ns
> U2-M0C1T0 <> U5-M0C2T1 Data Latency : 19.1ns
> U2-M0C1T0 <> U7-M0C3T1 Data Latency : 19.4ns
> U2-M0C1T0 <> U9-M0C4T1 Data Latency : 19.7ns
> U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.1ns
> U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.4ns
> U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.9ns
> U2-M0C1T0 <> U17-M1C0T1 Data Latency : 56.5ns
> U2-M0C1T0 <> U19-M1C1T1 Data Latency : 56.5ns
> U2-M0C1T0 <> U21-M1C2T1 Data Latency : 57.5ns
> U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.6ns
> U2-M0C1T0 <> U25-M1C4T1 Data Latency : 58.1ns
> U2-M0C1T0 <> U27-M1C5T1 Data Latency : 57.9ns
> U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.6ns
> U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.5ns
> U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.8ns
> U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.7ns
> U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
> U4-M0C2T0 <> U12-M0C6T0 Data Latency : 21.6ns
> U4-M0C2T0 <> U14-M0C7T0 Data Latency : 21.2ns
> U4-M0C2T0 <> U16-M1C0T0 Data Latency : 57.2ns
> U4-M0C2T0 <> U18-M1C1T0 Data Latency : 57.2ns
> U4-M0C2T0 <> U20-M1C2T0 Data Latency : 58.2ns
> U4-M0C2T0 <> U22-M1C3T0 Data Latency : 58.1ns
> U4-M0C2T0 <> U24-M1C4T0 Data Latency : 58.7ns
> U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.6ns
> U4-M0C2T0 <> U28-M1C6T0 Data Latency : 59.3ns
> U4-M0C2T0 <> U30-M1C7T0 Data Latency : 59.4ns
> U4-M0C2T0 <> U1-M0C0T1 Data Latency : 19.6ns
> U4-M0C2T0 <> U3-M0C1T1 Data Latency : 19.1ns
> U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.9ns
> U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.8ns
> U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.8ns
> U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.5ns
> U4-M0C2T0 <> U13-M0C6T1 Data Latency : 21.6ns
> U4-M0C2T0 <> U15-M0C7T1 Data Latency : 21.2ns
> U4-M0C2T0 <> U17-M1C0T1 Data Latency : 57.2ns
> U4-M0C2T0 <> U19-M1C1T1 Data Latency : 58.5ns
> U4-M0C2T0 <> U21-M1C2T1 Data Latency : 58.1ns
> U4-M0C2T0 <> U23-M1C3T1 Data Latency : 58.2ns
> U4-M0C2T0 <> U25-M1C4T1 Data Latency : 58.5ns
> U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.7ns
> U4-M0C2T0 <> U29-M1C6T1 Data Latency : 59.2ns
> U4-M0C2T0 <> U31-M1C7T1 Data Latency : 59.5ns
> U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.5ns
> U6-M0C3T0 <> U10-M0C5T0 Data Latency : 20.8ns
> U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.2ns
> U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.6ns
> U6-M0C3T0 <> U16-M1C0T0 Data Latency : 57.3ns
> U6-M0C3T0 <> U18-M1C1T0 Data Latency : 57.3ns
> U6-M0C3T0 <> U20-M1C2T0 Data Latency : 58.1ns
> U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.2ns
> U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.9ns
> U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.6ns
> U6-M0C3T0 <> U28-M1C6T0 Data Latency : 59.6ns
> U6-M0C3T0 <> U30-M1C7T0 Data Latency : 59.2ns
> U6-M0C3T0 <> U1-M0C0T1 Data Latency : 19.6ns
> U6-M0C3T0 <> U3-M0C1T1 Data Latency : 19.4ns
> U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.8ns
> U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
> U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.5ns
> U6-M0C3T0 <> U11-M0C5T1 Data Latency : 20.8ns
> U6-M0C3T0 <> U13-M0C6T1 Data Latency : 21.2ns
> U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.6ns
> U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.2ns
> U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.1ns
> U6-M0C3T0 <> U21-M1C2T1 Data Latency : 58.0ns
> U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.1ns
> U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.7ns
> U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.4ns
> U6-M0C3T0 <> U29-M1C6T1 Data Latency : 59.4ns
> U6-M0C3T0 <> U31-M1C7T1 Data Latency : 59.2ns
> U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.2ns
> U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.2ns
> U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.9ns
> U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
> U8-M0C4T0 <> U18-M1C1T0 Data Latency : 58.0ns
> U8-M0C4T0 <> U20-M1C2T0 Data Latency : 58.6ns
> U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.7ns
> U8-M0C4T0 <> U24-M1C4T0 Data Latency : 59.1ns
> U8-M0C4T0 <> U26-M1C5T0 Data Latency : 59.3ns
> U8-M0C4T0 <> U28-M1C6T0 Data Latency : 59.7ns
> U8-M0C4T0 <> U30-M1C7T0 Data Latency : 59.9ns
> U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.4ns
> U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.7ns
> U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.7ns
> U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
> U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.9ns
> U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.2ns
> U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.2ns
> U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.9ns
> U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.9ns
> U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.9ns
> U8-M0C4T0 <> U21-M1C2T1 Data Latency : 58.5ns
> U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.7ns
> U8-M0C4T0 <> U25-M1C4T1 Data Latency : 59.1ns
> U8-M0C4T0 <> U27-M1C5T1 Data Latency : 59.2ns
> U8-M0C4T0 <> U29-M1C6T1 Data Latency : 59.8ns
> U8-M0C4T0 <> U31-M1C7T1 Data Latency : 59.9ns
> U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.9ns
> U10-M0C5T0 <> U14-M0C7T0 Data Latency : 22.2ns
> U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.0ns
> U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.7ns
> U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.8ns
> U10-M0C5T0 <> U22-M1C3T0 Data Latency : 58.6ns
> U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.2ns
> U10-M0C5T0 <> U26-M1C5T0 Data Latency : 59.0ns
> U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.9ns
> U10-M0C5T0 <> U30-M1C7T0 Data Latency : 59.7ns
> U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.4ns
> U10-M0C5T0 <> U3-M0C1T1 Data Latency : 20.1ns
> U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.5ns
> U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.8ns
> U10-M0C5T0 <> U9-M0C4T1 Data Latency : 21.2ns
> U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.9ns
> U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.9ns
> U10-M0C5T0 <> U15-M0C7T1 Data Latency : 22.3ns
> U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.3ns
> U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.9ns
> U10-M0C5T0 <> U21-M1C2T1 Data Latency : 59.0ns
> U10-M0C5T0 <> U23-M1C3T1 Data Latency : 58.8ns
> U10-M0C5T0 <> U25-M1C4T1 Data Latency : 59.4ns
> U10-M0C5T0 <> U27-M1C5T1 Data Latency : 59.1ns
> U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.9ns
> U10-M0C5T0 <> U31-M1C7T1 Data Latency : 59.7ns
> U12-M0C6T0 <> U14-M0C7T0 Data Latency : 22.4ns
> U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.5ns
> U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.8ns
> U12-M0C6T0 <> U20-M1C2T0 Data Latency : 59.4ns
> U12-M0C6T0 <> U22-M1C3T0 Data Latency : 59.5ns
> U12-M0C6T0 <> U24-M1C4T0 Data Latency : 60.0ns
> U12-M0C6T0 <> U26-M1C5T0 Data Latency : 60.0ns
> U12-M0C6T0 <> U28-M1C6T0 Data Latency : 60.5ns
> U12-M0C6T0 <> U30-M1C7T0 Data Latency : 60.4ns
> U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.1ns
> U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.6ns
> U12-M0C6T0 <> U5-M0C2T1 Data Latency : 20.6ns
> U12-M0C6T0 <> U7-M0C3T1 Data Latency : 20.8ns
> U12-M0C6T0 <> U9-M0C4T1 Data Latency : 20.6ns
> U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.1ns
> U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.9ns
> U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.7ns
> U12-M0C6T0 <> U17-M1C0T1 Data Latency : 60.2ns
> U12-M0C6T0 <> U19-M1C1T1 Data Latency : 59.7ns
> U12-M0C6T0 <> U21-M1C2T1 Data Latency : 60.2ns
> U12-M0C6T0 <> U23-M1C3T1 Data Latency : 60.2ns
> U12-M0C6T0 <> U25-M1C4T1 Data Latency : 60.0ns
> U12-M0C6T0 <> U27-M1C5T1 Data Latency : 60.4ns
> U12-M0C6T0 <> U29-M1C6T1 Data Latency : 60.5ns
> U12-M0C6T0 <> U31-M1C7T1 Data Latency : 60.3ns
> U14-M0C7T0 <> U16-M1C0T0 Data Latency : 59.9ns
> U14-M0C7T0 <> U18-M1C1T0 Data Latency : 59.5ns
> U14-M0C7T0 <> U20-M1C2T0 Data Latency : 60.1ns
> U14-M0C7T0 <> U22-M1C3T0 Data Latency : 60.4ns
> U14-M0C7T0 <> U24-M1C4T0 Data Latency : 60.3ns
> U14-M0C7T0 <> U26-M1C5T0 Data Latency : 60.5ns
> U14-M0C7T0 <> U28-M1C6T0 Data Latency : 60.7ns
> U14-M0C7T0 <> U30-M1C7T0 Data Latency : 60.1ns
> U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.8ns
> U14-M0C7T0 <> U3-M0C1T1 Data Latency : 21.1ns
> U14-M0C7T0 <> U5-M0C2T1 Data Latency : 20.7ns
> U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.5ns
> U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.2ns
> U14-M0C7T0 <> U11-M0C5T1 Data Latency : 22.0ns
> U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.7ns
> U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.9ns
> U14-M0C7T0 <> U17-M1C0T1 Data Latency : 60.0ns
> U14-M0C7T0 <> U19-M1C1T1 Data Latency : 59.6ns
> U14-M0C7T0 <> U21-M1C2T1 Data Latency : 60.0ns
> U14-M0C7T0 <> U23-M1C3T1 Data Latency : 60.5ns
> U14-M0C7T0 <> U25-M1C4T1 Data Latency : 60.5ns
> U14-M0C7T0 <> U27-M1C5T1 Data Latency : 60.6ns
> U14-M0C7T0 <> U29-M1C6T1 Data Latency : 60.6ns
> U14-M0C7T0 <> U31-M1C7T1 Data Latency : 60.1ns
> U16-M1C0T0 <> U18-M1C1T0 Data Latency : 22.2ns
> U16-M1C0T0 <> U20-M1C2T0 Data Latency : 22.5ns
> U16-M1C0T0 <> U22-M1C3T0 Data Latency : 21.7ns
> U16-M1C0T0 <> U24-M1C4T0 Data Latency : 22.0ns
> U16-M1C0T0 <> U26-M1C5T0 Data Latency : 21.2ns
> U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.5ns
> U16-M1C0T0 <> U30-M1C7T0 Data Latency : 21.1ns
> U16-M1C0T0 <> U1-M0C0T1 Data Latency : 61.4ns
> U16-M1C0T0 <> U3-M0C1T1 Data Latency : 60.0ns
> U16-M1C0T0 <> U5-M0C2T1 Data Latency : 60.7ns
> U16-M1C0T0 <> U7-M0C3T1 Data Latency : 59.7ns
> U16-M1C0T0 <> U9-M0C4T1 Data Latency : 60.0ns
> U16-M1C0T0 <> U11-M0C5T1 Data Latency : 59.9ns
> U16-M1C0T0 <> U13-M0C6T1 Data Latency : 60.3ns
> U16-M1C0T0 <> U15-M0C7T1 Data Latency : 60.1ns
> U16-M1C0T0 <> U17-M1C0T1 Data Latency : 10.1ns
> U16-M1C0T0 <> U19-M1C1T1 Data Latency : 22.2ns
> U16-M1C0T0 <> U21-M1C2T1 Data Latency : 22.5ns
> U16-M1C0T0 <> U23-M1C3T1 Data Latency : 21.7ns
> U16-M1C0T0 <> U25-M1C4T1 Data Latency : 22.0ns
> U16-M1C0T0 <> U27-M1C5T1 Data Latency : 21.2ns
> U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.5ns
> U16-M1C0T0 <> U31-M1C7T1 Data Latency : 21.1ns
> U18-M1C1T0 <> U20-M1C2T0 Data Latency : 21.6ns
> U18-M1C1T0 <> U22-M1C3T0 Data Latency : 21.1ns
> U18-M1C1T0 <> U24-M1C4T0 Data Latency : 21.2ns
> U18-M1C1T0 <> U26-M1C5T0 Data Latency : 21.1ns
> U18-M1C1T0 <> U28-M1C6T0 Data Latency : 21.0ns
> U18-M1C1T0 <> U30-M1C7T0 Data Latency : 21.5ns
> U18-M1C1T0 <> U1-M0C0T1 Data Latency : 60.7ns
> U18-M1C1T0 <> U3-M0C1T1 Data Latency : 59.5ns
> U18-M1C1T0 <> U5-M0C2T1 Data Latency : 59.9ns
> U18-M1C1T0 <> U7-M0C3T1 Data Latency : 59.6ns
> U18-M1C1T0 <> U9-M0C4T1 Data Latency : 59.8ns
> U18-M1C1T0 <> U11-M0C5T1 Data Latency : 59.3ns
> U18-M1C1T0 <> U13-M0C6T1 Data Latency : 59.7ns
> U18-M1C1T0 <> U15-M0C7T1 Data Latency : 59.6ns
> U18-M1C1T0 <> U17-M1C0T1 Data Latency : 22.2ns
> U18-M1C1T0 <> U19-M1C1T1 Data Latency : 10.1ns
> U18-M1C1T0 <> U21-M1C2T1 Data Latency : 21.6ns
> U18-M1C1T0 <> U23-M1C3T1 Data Latency : 21.2ns
> U18-M1C1T0 <> U25-M1C4T1 Data Latency : 21.2ns
> U18-M1C1T0 <> U27-M1C5T1 Data Latency : 21.0ns
> U18-M1C1T0 <> U29-M1C6T1 Data Latency : 21.0ns
> U18-M1C1T0 <> U31-M1C7T1 Data Latency : 21.5ns
> U20-M1C2T0 <> U22-M1C3T0 Data Latency : 21.3ns
> U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.4ns
> U20-M1C2T0 <> U26-M1C5T0 Data Latency : 21.0ns
> U20-M1C2T0 <> U28-M1C6T0 Data Latency : 21.0ns
> U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.2ns
> U20-M1C2T0 <> U1-M0C0T1 Data Latency : 61.4ns
> U20-M1C2T0 <> U3-M0C1T1 Data Latency : 59.9ns
> U20-M1C2T0 <> U5-M0C2T1 Data Latency : 60.3ns
> U20-M1C2T0 <> U7-M0C3T1 Data Latency : 59.7ns
> U20-M1C2T0 <> U9-M0C4T1 Data Latency : 60.0ns
> U20-M1C2T0 <> U11-M0C5T1 Data Latency : 59.7ns
> U20-M1C2T0 <> U13-M0C6T1 Data Latency : 59.9ns
> U20-M1C2T0 <> U15-M0C7T1 Data Latency : 60.0ns
> U20-M1C2T0 <> U17-M1C0T1 Data Latency : 22.5ns
> U20-M1C2T0 <> U19-M1C1T1 Data Latency : 21.6ns
> U20-M1C2T0 <> U21-M1C2T1 Data Latency : 10.1ns
> U20-M1C2T0 <> U23-M1C3T1 Data Latency : 21.3ns
> U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.4ns
> U20-M1C2T0 <> U27-M1C5T1 Data Latency : 21.0ns
> U20-M1C2T0 <> U29-M1C6T1 Data Latency : 21.1ns
> U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.2ns
> U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.9ns
> U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.3ns
> U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.3ns
> U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.9ns
> U22-M1C3T0 <> U1-M0C0T1 Data Latency : 60.7ns
> U22-M1C3T0 <> U3-M0C1T1 Data Latency : 59.6ns
> U22-M1C3T0 <> U5-M0C2T1 Data Latency : 59.8ns
> U22-M1C3T0 <> U7-M0C3T1 Data Latency : 59.8ns
> U22-M1C3T0 <> U9-M0C4T1 Data Latency : 60.0ns
> U22-M1C3T0 <> U11-M0C5T1 Data Latency : 59.8ns
> U22-M1C3T0 <> U13-M0C6T1 Data Latency : 60.3ns
> U22-M1C3T0 <> U15-M0C7T1 Data Latency : 60.5ns
> U22-M1C3T0 <> U17-M1C0T1 Data Latency : 21.7ns
> U22-M1C3T0 <> U19-M1C1T1 Data Latency : 21.2ns
> U22-M1C3T0 <> U21-M1C2T1 Data Latency : 21.4ns
> U22-M1C3T0 <> U23-M1C3T1 Data Latency : 10.1ns
> U22-M1C3T0 <> U25-M1C4T1 Data Latency : 21.0ns
> U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.3ns
> U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.1ns
> U22-M1C3T0 <> U31-M1C7T1 Data Latency : 21.3ns
> U24-M1C4T0 <> U26-M1C5T0 Data Latency : 20.9ns
> U24-M1C4T0 <> U28-M1C6T0 Data Latency : 20.9ns
> U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.2ns
> U24-M1C4T0 <> U1-M0C0T1 Data Latency : 61.5ns
> U24-M1C4T0 <> U3-M0C1T1 Data Latency : 60.1ns
> U24-M1C4T0 <> U5-M0C2T1 Data Latency : 61.0ns
> U24-M1C4T0 <> U7-M0C3T1 Data Latency : 60.2ns
> U24-M1C4T0 <> U9-M0C4T1 Data Latency : 60.5ns
> U24-M1C4T0 <> U11-M0C5T1 Data Latency : 60.6ns
> U24-M1C4T0 <> U13-M0C6T1 Data Latency : 60.5ns
> U24-M1C4T0 <> U15-M0C7T1 Data Latency : 60.9ns
> U24-M1C4T0 <> U17-M1C0T1 Data Latency : 22.9ns
> U24-M1C4T0 <> U19-M1C1T1 Data Latency : 21.7ns
> U24-M1C4T0 <> U21-M1C2T1 Data Latency : 22.1ns
> U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.8ns
> U24-M1C4T0 <> U25-M1C4T1 Data Latency : 10.1ns
> U24-M1C4T0 <> U27-M1C5T1 Data Latency : 20.9ns
> U24-M1C4T0 <> U29-M1C6T1 Data Latency : 21.0ns
> U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.2ns
> U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.1ns
> U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.2ns
> U26-M1C5T0 <> U1-M0C0T1 Data Latency : 61.3ns
> U26-M1C5T0 <> U3-M0C1T1 Data Latency : 60.2ns
> U26-M1C5T0 <> U5-M0C2T1 Data Latency : 60.6ns
> U26-M1C5T0 <> U7-M0C3T1 Data Latency : 59.9ns
> U26-M1C5T0 <> U9-M0C4T1 Data Latency : 60.7ns
> U26-M1C5T0 <> U11-M0C5T1 Data Latency : 60.3ns
> U26-M1C5T0 <> U13-M0C6T1 Data Latency : 60.5ns
> U26-M1C5T0 <> U15-M0C7T1 Data Latency : 60.0ns
> U26-M1C5T0 <> U17-M1C0T1 Data Latency : 21.7ns
> U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.7ns
> U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.8ns
> U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.9ns
> U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.0ns
> U26-M1C5T0 <> U27-M1C5T1 Data Latency : 10.1ns
> U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.1ns
> U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.1ns
> U28-M1C6T0 <> U30-M1C7T0 Data Latency : 21.2ns
> U28-M1C6T0 <> U1-M0C0T1 Data Latency : 61.5ns
> U28-M1C6T0 <> U3-M0C1T1 Data Latency : 60.4ns
> U28-M1C6T0 <> U5-M0C2T1 Data Latency : 60.7ns
> U28-M1C6T0 <> U7-M0C3T1 Data Latency : 60.2ns
> U28-M1C6T0 <> U9-M0C4T1 Data Latency : 60.8ns
> U28-M1C6T0 <> U11-M0C5T1 Data Latency : 60.3ns
> U28-M1C6T0 <> U13-M0C6T1 Data Latency : 60.6ns
> U28-M1C6T0 <> U15-M0C7T1 Data Latency : 60.1ns
> U28-M1C6T0 <> U17-M1C0T1 Data Latency : 22.1ns
> U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.9ns
> U28-M1C6T0 <> U21-M1C2T1 Data Latency : 21.3ns
> U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.9ns
> U28-M1C6T0 <> U25-M1C4T1 Data Latency : 20.9ns
> U28-M1C6T0 <> U27-M1C5T1 Data Latency : 20.9ns
> U28-M1C6T0 <> U29-M1C6T1 Data Latency : 10.1ns
> U28-M1C6T0 <> U31-M1C7T1 Data Latency : 21.2ns
> U30-M1C7T0 <> U1-M0C0T1 Data Latency : 61.1ns
> U30-M1C7T0 <> U3-M0C1T1 Data Latency : 60.1ns
> U30-M1C7T0 <> U5-M0C2T1 Data Latency : 60.4ns
> U30-M1C7T0 <> U7-M0C3T1 Data Latency : 60.0ns
> U30-M1C7T0 <> U9-M0C4T1 Data Latency : 60.3ns
> U30-M1C7T0 <> U11-M0C5T1 Data Latency : 60.3ns
> U30-M1C7T0 <> U13-M0C6T1 Data Latency : 60.3ns
> U30-M1C7T0 <> U15-M0C7T1 Data Latency : 60.1ns
> U30-M1C7T0 <> U17-M1C0T1 Data Latency : 21.1ns
> U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.9ns
> U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.8ns
> U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.2ns
> U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.0ns
> U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.1ns
> U30-M1C7T0 <> U29-M1C6T1 Data Latency : 21.2ns
> U30-M1C7T0 <> U31-M1C7T1 Data Latency : 10.1ns
> U1-M0C0T1 <> U3-M0C1T1 Data Latency : 23.0ns
> U1-M0C0T1 <> U5-M0C2T1 Data Latency : 23.4ns
> U1-M0C0T1 <> U7-M0C3T1 Data Latency : 22.4ns
> U1-M0C0T1 <> U9-M0C4T1 Data Latency : 22.8ns
> U1-M0C0T1 <> U11-M0C5T1 Data Latency : 21.6ns
> U1-M0C0T1 <> U13-M0C6T1 Data Latency : 22.2ns
> U1-M0C0T1 <> U15-M0C7T1 Data Latency : 21.0ns
> U1-M0C0T1 <> U17-M1C0T1 Data Latency : 63.4ns
> U1-M0C0T1 <> U19-M1C1T1 Data Latency : 62.3ns
> U1-M0C0T1 <> U21-M1C2T1 Data Latency : 62.9ns
> U1-M0C0T1 <> U23-M1C3T1 Data Latency : 62.3ns
> U1-M0C0T1 <> U25-M1C4T1 Data Latency : 62.7ns
> U1-M0C0T1 <> U27-M1C5T1 Data Latency : 61.8ns
> U1-M0C0T1 <> U29-M1C6T1 Data Latency : 62.1ns
> U1-M0C0T1 <> U31-M1C7T1 Data Latency : 62.0ns
> U3-M0C1T1 <> U5-M0C2T1 Data Latency : 22.2ns
> U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.8ns
> U3-M0C1T1 <> U9-M0C4T1 Data Latency : 21.3ns
> U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.4ns
> U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.6ns
> U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.9ns
> U3-M0C1T1 <> U17-M1C0T1 Data Latency : 61.3ns
> U3-M0C1T1 <> U19-M1C1T1 Data Latency : 60.3ns
> U3-M0C1T1 <> U21-M1C2T1 Data Latency : 61.0ns
> U3-M0C1T1 <> U23-M1C3T1 Data Latency : 60.5ns
> U3-M0C1T1 <> U25-M1C4T1 Data Latency : 60.5ns
> U3-M0C1T1 <> U27-M1C5T1 Data Latency : 60.3ns
> U3-M0C1T1 <> U29-M1C6T1 Data Latency : 60.5ns
> U3-M0C1T1 <> U31-M1C7T1 Data Latency : 60.5ns
> U5-M0C2T1 <> U7-M0C3T1 Data Latency : 21.3ns
> U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.8ns
> U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
> U5-M0C2T1 <> U13-M0C6T1 Data Latency : 21.0ns
> U5-M0C2T1 <> U15-M0C7T1 Data Latency : 20.7ns
> U5-M0C2T1 <> U17-M1C0T1 Data Latency : 61.6ns
> U5-M0C2T1 <> U19-M1C1T1 Data Latency : 60.8ns
> U5-M0C2T1 <> U21-M1C2T1 Data Latency : 61.2ns
> U5-M0C2T1 <> U23-M1C3T1 Data Latency : 61.0ns
> U5-M0C2T1 <> U25-M1C4T1 Data Latency : 61.0ns
> U5-M0C2T1 <> U27-M1C5T1 Data Latency : 60.9ns
> U5-M0C2T1 <> U29-M1C6T1 Data Latency : 60.1ns
> U5-M0C2T1 <> U31-M1C7T1 Data Latency : 60.3ns
> U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.5ns
> U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.9ns
> U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.8ns
> U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.5ns
> U7-M0C3T1 <> U17-M1C0T1 Data Latency : 59.8ns
> U7-M0C3T1 <> U19-M1C1T1 Data Latency : 59.7ns
> U7-M0C3T1 <> U21-M1C2T1 Data Latency : 59.9ns
> U7-M0C3T1 <> U23-M1C3T1 Data Latency : 59.6ns
> U7-M0C3T1 <> U25-M1C4T1 Data Latency : 59.6ns
> U7-M0C3T1 <> U27-M1C5T1 Data Latency : 60.0ns
> U7-M0C3T1 <> U29-M1C6T1 Data Latency : 60.1ns
> U7-M0C3T1 <> U31-M1C7T1 Data Latency : 60.1ns
> U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.8ns
> U9-M0C4T1 <> U13-M0C6T1 Data Latency : 20.6ns
> U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.2ns
> U9-M0C4T1 <> U17-M1C0T1 Data Latency : 60.3ns
> U9-M0C4T1 <> U19-M1C1T1 Data Latency : 59.8ns
> U9-M0C4T1 <> U21-M1C2T1 Data Latency : 60.1ns
> U9-M0C4T1 <> U23-M1C3T1 Data Latency : 60.0ns
> U9-M0C4T1 <> U25-M1C4T1 Data Latency : 59.8ns
> U9-M0C4T1 <> U27-M1C5T1 Data Latency : 59.9ns
> U9-M0C4T1 <> U29-M1C6T1 Data Latency : 60.3ns
> U9-M0C4T1 <> U31-M1C7T1 Data Latency : 60.2ns
> U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.1ns
> U11-M0C5T1 <> U15-M0C7T1 Data Latency : 22.0ns
> U11-M0C5T1 <> U17-M1C0T1 Data Latency : 59.8ns
> U11-M0C5T1 <> U19-M1C1T1 Data Latency : 59.4ns
> U11-M0C5T1 <> U21-M1C2T1 Data Latency : 59.8ns
> U11-M0C5T1 <> U23-M1C3T1 Data Latency : 59.9ns
> U11-M0C5T1 <> U25-M1C4T1 Data Latency : 60.0ns
> U11-M0C5T1 <> U27-M1C5T1 Data Latency : 60.3ns
> U11-M0C5T1 <> U29-M1C6T1 Data Latency : 60.3ns
> U11-M0C5T1 <> U31-M1C7T1 Data Latency : 60.2ns
> U13-M0C6T1 <> U15-M0C7T1 Data Latency : 21.7ns
> U13-M0C6T1 <> U17-M1C0T1 Data Latency : 60.1ns
> U13-M0C6T1 <> U19-M1C1T1 Data Latency : 59.8ns
> U13-M0C6T1 <> U21-M1C2T1 Data Latency : 61.4ns
> U13-M0C6T1 <> U23-M1C3T1 Data Latency : 60.2ns
> U13-M0C6T1 <> U25-M1C4T1 Data Latency : 60.2ns
> U13-M0C6T1 <> U27-M1C5T1 Data Latency : 60.7ns
> U13-M0C6T1 <> U29-M1C6T1 Data Latency : 60.7ns
> U13-M0C6T1 <> U31-M1C7T1 Data Latency : 60.5ns
> U15-M0C7T1 <> U17-M1C0T1 Data Latency : 60.2ns
> U15-M0C7T1 <> U19-M1C1T1 Data Latency : 59.7ns
> U15-M0C7T1 <> U21-M1C2T1 Data Latency : 60.1ns
> U15-M0C7T1 <> U23-M1C3T1 Data Latency : 60.4ns
> U15-M0C7T1 <> U25-M1C4T1 Data Latency : 60.4ns
> U15-M0C7T1 <> U27-M1C5T1 Data Latency : 60.7ns
> U15-M0C7T1 <> U29-M1C6T1 Data Latency : 60.7ns
> U15-M0C7T1 <> U31-M1C7T1 Data Latency : 60.2ns
> U17-M1C0T1 <> U19-M1C1T1 Data Latency : 22.2ns
> U17-M1C0T1 <> U21-M1C2T1 Data Latency : 22.5ns
> U17-M1C0T1 <> U23-M1C3T1 Data Latency : 21.7ns
> U17-M1C0T1 <> U25-M1C4T1 Data Latency : 22.0ns
> U17-M1C0T1 <> U27-M1C5T1 Data Latency : 21.2ns
> U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.5ns
> U17-M1C0T1 <> U31-M1C7T1 Data Latency : 21.1ns
> U19-M1C1T1 <> U21-M1C2T1 Data Latency : 21.6ns
> U19-M1C1T1 <> U23-M1C3T1 Data Latency : 21.1ns
> U19-M1C1T1 <> U25-M1C4T1 Data Latency : 21.2ns
> U19-M1C1T1 <> U27-M1C5T1 Data Latency : 21.0ns
> U19-M1C1T1 <> U29-M1C6T1 Data Latency : 21.0ns
> U19-M1C1T1 <> U31-M1C7T1 Data Latency : 21.5ns
> U21-M1C2T1 <> U23-M1C3T1 Data Latency : 21.3ns
> U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.4ns
> U21-M1C2T1 <> U27-M1C5T1 Data Latency : 21.0ns
> U21-M1C2T1 <> U29-M1C6T1 Data Latency : 21.0ns
> U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.2ns
> U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.9ns
> U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.4ns
> U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.2ns
> U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.9ns
> U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
> U25-M1C4T1 <> U29-M1C6T1 Data Latency : 21.1ns
> U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.7ns
> U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.5ns
> U27-M1C5T1 <> U31-M1C7T1 Data Latency : 22.5ns
> U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.2ns
> 1x 64bytes Blocks Bandwidth : 25.88GB/s
> 4x 64bytes Blocks Bandwidth : 27.09GB/s
> 4x 256bytes Blocks Bandwidth : 108.12GB/s
> 4x 1kB Blocks Bandwidth : 328.23GB/s
> 4x 4kB Blocks Bandwidth : 535.84GB/s
> 16x 4kB Blocks Bandwidth : 765.65GB/s
> 4x 64kB Blocks Bandwidth : 1TB/s
> 16x 64kB Blocks Bandwidth : 744.45GB/s
> 8x 256kB Blocks Bandwidth : 499.46GB/s
> 4x 1MB Blocks Bandwidth : 131.74GB/s
> 16x 1MB Blocks Bandwidth : 24.88GB/s
> 8x 4MB Blocks Bandwidth : 18.44GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.8GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : A20F10-1009
> Computer : ASUS System Product Name (ASUS ROG CROSSHAIR VIII HERO (WI-FI))
> Platform Compliance : x64
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 4kB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> URL : https://www.amd.com
> Speed : 4.8GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.8GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 8 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : A20F10-1009
> Latest Version : A20F10-16
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Warning 5010 : Cannot use Large Memory Pages due to lack of privileges.
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 229 : CPU microcode update available. Check for an updated System BIOS with updated microcode.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.
> 
> 
> 
> View attachment 2515413
> 
> 
> CTR settings
> 
> View attachment 2515414


More Windows 11 testing from me, memory performance seems to be normal or even better then with Windows 10 in pretty everything other Aida64 L3 it seems. But then again, as ive said many times before, Aida64 is a fully synthetic benchmark and should not be given too much weight 
(btw, are the sandra inter thread efficiency benchmark above good for a 5950x (?) i have no idea what's good numbers in this program..)

So over to some new benches from today:








_edit_
Obs, seems i had the wrong P1 and P2 profile enabled in CTR for that cpu profile benchmark run.. Correct numbers should look like this when maxed:












domdtxdissar said:


> Here we go
> 
> 
> 5950x @ 4700/4600 static OC, SMT enabled
> 4x8GB memory sticks
> Hwinfo open for all runs
> consecutive runs
> Flat CL 14-14-14-14 timings
> 
> View attachment 2513871
> 
> T1 setup-time
> *19723.4 H/S over 15min run*
> upto 627 H/S per core
> 
> View attachment 2513872
> 
> T1 GDM
> *19151 H/S over 15min run*
> upto 606 H/S per core
> 
> View attachment 2513873
> 
> T2
> *19413 H/S over 15min run*
> upto 616 H/S per core
> 
> ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> 
> 19413 / 19151 = T2 is ~1.3% faster than T1 GDM in this benchmark
> 19723 / 19413 = T1 setup-time is ~1.6% faster than T2 in this benchmark
> 19723 / 19151 = T1 setup-time is ~2.9% faster than T1 GDM in this benchmark
> 
> No time to break down the numbers further, going out
> 
> But it seems like CPU mhz is king in pretty much every benchmark, *dont waste to much of your power budget on SOC if your running PBO CO *as the pure core clocks matters the most in the end...


Also pretty decent memory performance in the moero miner and the Aida latency aint shabby either 


5950x @ 4700/4600 static OC, SMT enabled
4x8GB memory sticks
Hwinfo open
Windows 11
Flat CL 14-14-14-14 timings










T1 setup-time
*19819.2 H/S over 15min run*
upto 629 H/S per core


----------



## Nighthog

I put in one of the Crucial kits in my X570 Xtreme paired with the Ryzen 5 4650G loaded XMP profile and booted.

XMP is using a little much SoC voltage? 1.350V. [Optimized defaults]


----------



## T[]RK

craxton said:


> but i cant keep it from being re-installed. even tho windows updates are paused for 7 days.





craxton said:


> so is there a way to stop windows updates (or whatever is updating this driver by itself?)





Mach3.2 said:


> You can also disable this in group policy


I did something similar via Group Policy. I have got GTX 650M moddded driver (last version) and sometime Windows Update detected it's modded and installed driver from it's base (very old one). So i have to block it via GPU GUID. That way Windows Update even if detect something - it can't install driver.


----------



## domdtxdissar

Had to turn off "game mode" in windows, but are getting very good results now.
*306 fps CPU game average







*

Even better numbers in dram calc + intel latency tester


----------



## sendap

whats going on with L3 Cache?


----------



## XPEHOPE3

mongoled said:


> Just putting this here before I forget
> 
> For MSI users
> 
> Power Supply Idle Control set to "Low Current" or "AUTO" == Package C6-State Enabled
> Power Supply Idle Control set to "Typical Current" == Package C6-State Disabled
> 
> Will get back to other posts soon ....


*TLDR*: on newest Gigabyte BIOS might not work


For Gigabyte B550 Aorus Pro V2 there are also such settings in *F13j beta* BIOS under Settings/AMD CBS/CPU Common Options/Power Supply Idle Control:







However it doesn't sustain reboots (Global C-State Control above it also resets to Auto). *Anyone knows why can it be that a BIOS setting resets to Auto during normal reboot?* Is it a typical "unimplemented" sign?

There is also another setting seemingly about the same (read description in screenshot): Settings/Platform Power/Power Loading







It's kept between reboots.

However no combination of those settings removed that Package C6-States tick in ZenStates


----------



## XPEHOPE3

Veii said:


> They are also in hex
> You want pattern testing to "both"
> Pattern bits to A (hex) or to 9
> _And one down to i think 5 is the next one
> 1-5-9 or 1-3-9 up to how the bios shows it
> The 2nd instead of 1 is what you want to set_
> 
> This betters up memory training a bit, and takes 2.5-3sec to post
> If you enable data-eye training, which is a good thing ~ training will take 50-60sec
> And this is too much, soo above settings are a good middle ground


Couldn't find italicized settings on B550 Aorus Pro V2. Also there is only one training available (data-eye) although help string suggests there should also be some Interface mode.
I hoped those training would help with my post issues for 1967+ MEM CLK, but they did nothing. Prolonged training was only seen for the same configurations which would boot even without MBIST. Neither Aida latency was improved, nor ZenTimings-observable settings. Those actually varied between reboots and between the same values as without MBIST, e.g. tPHYRDL 26->28 and tRDRDDD 5->6 for one of the channels.

Guess all talks about Gigabyte BIOS was true. Strange that BuildZoid still recommended that very board for memory overclock.


----------



## Nighthog

XPEHOPE3 said:


> Couldn't find italicized settings on B550 Aorus Pro V2. Also there is only one training available (data-eye) although help string suggests there should also be some Interface mode.
> I hoped those training would help with my post issues for 1967+ MEM CLK, but they did nothing. Prolonged training was only seen for the same configurations which would boot even without MBIST. Neither Aida latency was improved, nor ZenTimings-observable settings. Those actually varied between reboots and between the same values as without MBIST, e.g. tPHYRDL 26->28 and tRDRDDD 5->6 for one of the channels.
> 
> Guess all talks about Gigabyte BIOS was true. Strange that BuildZoid still recommended that very board for memory overclock.


He reccomends it because it works even though you might not have all the options available. He gets the best results overall with them.


----------



## Robostyle

Corecycler + ycruncher = is it effective? 

Cause I see when it swaps the core so cores get different algorithm load. Or I have to manually config it to run 10 minutes per core?


----------



## CarnageBT

Robostyle said:


> Corecycler + ycruncher = is it effective?
> 
> Cause I see when it swaps the core so cores get different algorithm load. Or I have to manually config it to run 10 minutes per core?


Yea, it works. I set it to 10 minutes / core so that it completes all the tests on each core, otherwise, at 6m, if will switch before running all tests. Y cruncher through CC runs all the tests except for C17 test, so you might want to test that one directly in y cruncher after the CC version. 

Is there a way to change CC to run all y cruncher tests for 2m, vs the default 1m?


----------



## Veii

craxton said:


> i cant confirm that its 100% realtek causing it. but it does stop for a good bit after uninstalling the drivers from device man.
> otherwise is 1-2 per second.
> 
> so is there a way to stop windows updates (or whatever is updating this driver by itself?)


Give WPD.APP a try
Most of the registry tweaks didn't work to stop windows update
it yet managed to reinstall itself
Also stop the Windows Update Health & Windows Update Medic service



byDenoso said:


> Is 1.25v for SOC safe for a R5 3600 24/7?


Change the question to "too much"
Then kind of yes. Pretty much a yes (it's too much) unless you can keep it sub ambient (ambient being around 30c)
over 1.15v you get negative scaling , over 1.2v it starts to be dangerous
Vermeer is a different substrate - different color. It's range is up to 1.3v, but beyond 1.25v everything is questionable
Matisse was 1.1v beyond 1.15v everything is questionable


----------



## Dasa

Try as I might 3800c14 kept giving 1-4 errors during 20 cycles of TM5 except once but not repeatable and started to get more errors at ~1.6VDIMM.
So a mate pointed me to WHEAService, WHEA errors suppressor where people were disabling the WHEA logger.
Now the settings that would have been 24\7 stable at 3800 were running nicely at 4000 without the logging stutters.
Latency seemed to increase at higher speeds and audio crackling started at 4066.

Very happy with the result thus far but need to test minimum FPS in some games. Know of any that are consistent? most tend to be rather random.
Timespy with CPU at stock CPU Score 13 463 
Geekbench 5 Score SC 1748, MC 12142
Geekbench 4 Score SC 7765 MC 48331

Memory Copy13233
36.7 GB/sec Memory Latency6918
62.6 ns Memory Bandwidth10507
56.1 GB/sec












Any fine tuning left in these settings? other than finding a stable CPU OC to go with it.


----------



## Veii

Ultranoc said:


> Guys I am hopeless, I have no idea how to stop all the errors I get... even raised VDIMM to 1.45V, but it did not help
> I am crazy, what I can do? I thought 1900 FCLK is not that high, no?


What do you mean with "you" are crazy ?
OCCT shows the CPU is unstable, TM5 shows the ram is unstable








Meaning, tWTR to 5-14 or drop tRCDWR to 13
Be sure you are y-cruncher stable & if not - screenshot where you fail

Also try with SD, DD 1-4-4-1-6-6 for now, till you can run 1-5-5-1-7-7
You want to also drop RTT_PARK once, it's too strong on /1


----------



## craxton

Veii said:


> Give WPD.APP a try


will do, as of trying what the other feller said, that immeditly showed to not work.
to which instantly re-installed any driver (including me selecting delete the drivers themselves)
from the PC. 

100% accurate that whoever stated it as the WHEA-19 issue never happened to me up-till-now
that SOC voltage up-to X limit has strange **** happening which i can state thats a 100% fact, 
to which at 1.114-1.122 (auto) i have no audio issues have not stressed the CPU since i got off work-booted since 6pm eastern time. 
is now 6:53pm and i have had 142 WHEA-19 events as shown in my HWiNFO with totaled errors and CPU BUS/INTERCONNECT ERRORS
(testing ram using TM5, HCI etc throws the error reading into a panic mode which starts to raise faster, but not 5000 an hour at IF 2000.

considering the NUMBER of users who have used @ManniX-ITA WHEA suppressor and are still running the "SAME" voltages, and etc
as SIL-quality still shows its strong id bet it would be nothing to worry about. but as im 31 years old and have loads of "GREY" hair already 
not worrying is not anything i can do. 

going to check my saved pages where the user @Veii has posted well more stuff than i well state with hard proof and 100s of other users being able
to confirm what he states, even me on most of it. (some he stated is not a "follow or else" type of deal but rather suggesting that something should be.
but i did not follow. now however, ill be following until i can get down to at least 100 a day. or figure out somehow to get rid of these issues. 

my PCIe is set to "auto" in the bios, maybe i should change this and a few other things. also will note that with -15 all core with +1 offset
that i could not post while DF-Cstates were turned to auto, but turning these off allowed me to post. 
unsure if its due to me (flashing to the unlocked bios 1.60 1.2.0.2) or not but still there's also that. 
Veii dont let this stop you from sharing here. without you, manna, and a few others thats long since not posted in sometime the thread
goes silent and i find myself "posting to noone" to where i respond to myself like a crazy person


Spoiler



(might just be tho)


i could not have responded the way you did, so even tho your younger than I, you do have patience which dealing with Ryzen/AMD 
i suppose thats where it came from. 

now, off to post, look, test, look, reboot, repeat. 
thank you for the 100s of pages of info to look back on for 3000-5000 series chips im sure i speak for others when i state this as well.

(since writing this, cpu/bus errors are now at 168)


----------



## craxton

Oh, with the WHEA-19 being a thing, none the less,
the chip can do 5ghz 








(and clicking SIL quality in "tool.exe" serveral times shows 120.x as silicon quality 
am now going to find and copy veii 3800 settings accounting for 4x8 sets.


----------



## craxton

jomama22 said:


> What findings exactly? I appreciate veii's work thus far but until we have someone who 1) Has no wheas then changes motherboards and gets wheas at 1933+ 2) Has wheas at 1933+, changes boards, then doesn't have them.
> 
> We have 0 people like that.
> 
> The only reports we have of people over 1933 with no wheas have never had them.
> 
> Until we have further proof, I have to believe the cpu plays a roll in this.
> 
> Amd never guaranteed anything btw. So to just bombard a forum about not getting 2000 fclk is questionable at best.


unsure if you seen, but i didnt change boards, however did change my processor, and went from ZERO WHEA-19s
on my 5600x EVER to having thousands within the hour. BUT i managed to lower then greatly by disabling LAN, and nvidias USB driver on my board.
as well as raising IOD, CCD voltages ever so slightly

(came across this while running thru old posts to see what others have tried)

i also turned off the option inside the unlocked bios that states USB on the gpu side will be turned off, and audio.
but that did not help.... my temps however ARE WAY better on this 5800x vs my 5600x.idle on 5800x is 34c around the same on the 
5600x but the 5600x would hit EXTREMLY high temps in the 80s running R23 with lower PBO limits. 
sure different chips but more cores. anyhow just thought id chime ya in. 

working ona board coming in soon enough, may swap the 6 core back in and see if it now too has WHEA 19s


----------



## ManniX-ITA

@Veii 

For me at FCLK 2000 without DF C State enabled the system is unstable.
But I'm not sure the FCLK speed is a factor.
I get random reboots in idle and the yesterday one was logged by WHEA, Error 18 on Core 9.
It's not the worst core but one that needs a less negative count.
Not a single issue if DF C State is enabled.



Nighthog said:


> My 3800X gets WHEA & AUDIO issues when I raise the VDDG_CCD voltage above 1000mV. Most WHEA are in the 1000-1050mV range.


I think there are a number of reasons for WHEA errors.
One of them is the voltages, which have to be all at the right spot.

The story is very different between 3000 & 5000.
The 3000 is near the limit at FCLK 1900 already, the 5000 is near the limit at 2000.

The main voltages are SOC and IOD, those which will drive the Infinity Fabric clock.
But CCD has a very big role as well cause the CCD common parts have to interface with the IF.
And if they can't keep the pace things will go haywire.
Specifically the DDR memory controller, I think it's what is called CCA in Zen2/3.
That is the part which is communicating via the GMI link to the IOD to access the DDR channels.



mongoled said:


> CPU: 70%
> Motherboard: 20%
> VGA: 8%
> Others: 2%


There are 2 "types" of WHEA errors running high FCLK.

One is the high data rate flow which you get constantly and usually raise in speed when you are idling.
The fast pace will bog down the system and changing voltages will not change much the pace.
That's the type I made the WHEA Suppressor for.

I can say in this case the VGA has a very important role.
Since I switched to the 3080ti it doesn't happen anymore, at all.
I would have thought PCIe Gen4 would be more of a problem but maybe since the protocol itself is more resilient it helps instead.
These are what I call the "fake" WHEA errors; they are not related to resources usage at all.

I only have WHEA errors under load right now. Not a single one in idle or low load.
Which is the 2nd type of WHEA errors and for which I wouldn't recommend to use the WHEA suppressor.
Unless you decide that you are fine with it.
If the ratio between the degradation from the corrected errors and the performance uplift is still positive it's risky but could be worth.
Still I wouldn't recommend it at all unless your really know what you are doing and you don't need to save lives with your PC 

It's much more interesting now cause I can finally see what is triggering WHEA and what not and at which pace.
Clearly it's not/not only related to memory/GMI link usage.
Some y-cruncher tests or P95 with CoreCycler doesn't use much of memory bandwidth and triggers a lot of WHEA.
I'll have to compare with water cooling but I have the feeling at least in some cases it's strictly related to thermals.
y-cruncher BBP test doesn't trigger many WHEA if at all, mostly when the temperature is going up.

Anyway the CPU always plays a central role of course.
It depends on FCLK, which is purely a CPU thing, and WHEAs are reported by the CPU.
There are for sure other components involved but the CPU is the main actor here.
If there's also something else not playing along, like the GPU, the chipset, the Realtek NIC, etc surely doesn't help.

Hard to say but I'm very skeptical about the CPUs which doesn't report WHEA.
I have the feeling it's more likely that they don't report correctly instead, as they have their own suppressor inside 
Maybe a lucky combination of low grade CCD and high grade IOD.


----------



## T[]RK

XPEHOPE3 said:


> *Anyone knows why can it be that a BIOS setting resets to Auto during normal reboot?* Is it a typical "unimplemented" sign?


GIGABYTE sometime also have not working BIOS settings. Probably a bug of beta. On my B450M DS3H v2 PBO setting in XFR menu can be set to "Disable" and "Enable". When i set it to "Disable" it allow board to use EDC 140A, but when i set it to "Enable" it limit it to 120A. Ain't it should be diffirent? I did check it in Ryzen Master and HWiNFO64. Description in BIOS say that "Disable" is "stock board values for standard IRM", but "Enable" say "load board limits".

PBO Disable (in XFR)







PBO Enable (in XFR)










XPEHOPE3 said:


> Guess all talks about Gigabyte BIOS was true. Strange that BuildZoid still recommended that very board for memory overclock.


GIGABYTE offer best VRM. Also, don't forget that BZ is XOC. A bit diffirent then usual OC and general user.



Dreamic said:


> I can't even be bothered to read another of your gigantic posts





Dreamic said:


> I'll be happy to read it


Haha.


----------



## XPEHOPE3

T[]RK said:


> Ain't it should be diffirent?


For disabled I have 90A, for enabled I have 120A just as you.

@ManniX-ITA 
since you created WHEA-suppressor... is there a Dreamic-suppressor in the works maybe?


----------



## Takla

You can disable mainboard components in the bios and error reporting in windows all you want, but at the end of the day, you are just masking an unstable overclock. This is called coping.


----------



## mongoled

Dreamic said:


> This is all just based off feelings you have, interesting Veii liked it when he put it 100% on the motherboard, along with ManniX. They were convinced it was Realtek or some stupid thing on the motherboard that can be ignored, definitely not the CPU, but we just saw changing only the CPU makes them appear.
> Yet people here convince themselves and blindly believe it's not their CPU, based on no testing only their feelings, it's definitely some thing on my motherboard that isn't important, CPU: 0%...
> If any of you had the opportunity to present your "findings" to someone knowledgeable at the top level of AMD or wherever who could look into this and maybe fix it, you would be laughed at because you have nothing other than your self-perceived intelligent and true feelings and guesses. There's lots of people smarter than the people who post on OCN, yet nobody anywhere else has been finding any of this.
> 
> Just a case of people who think they're smart and make guesses which they give way too much credence to, which isn't smart. Not scientific or emperical.
> Too much doing nothing and thinking things I think are smart and believing them, too little testing and finding things out and actually knowing them


Man you have issues!

We been through this before, you need to let go of whatever is eating you as its not healthy.

No more to be said from me on this, just hope you can find some peace ..........



ManniX-ITA said:


> @Veii
> 
> For me at FCLK 2000 without DF C State enabled the system is unstable.
> But I'm not sure the FCLK speed is a factor.
> I get random reboots in idle and the yesterday one was logged by WHEA, Error 18 on Core 9.
> It's not the worst core but one that needs a less negative count.
> Not a single issue if DF C State is enabled.
> 
> 
> 
> I think there are a number of reasons for WHEA errors.
> One of them is the voltages, which have to be all at the right spot.
> 
> The story is very different between 3000 & 5000.
> The 3000 is near the limit at FCLK 1900 already, the 5000 is near the limit at 2000.
> 
> The main voltages are SOC and IOD, those which will drive the Infinity Fabric clock.
> But CCD has a very big role as well cause the CCD common parts have to interface with the IF.
> And if they can't keep the pace things will go haywire.
> Specifically the DDR memory controller, I think it's what is called CCA in Zen2/3.
> That is the part which is communicating via the GMI link to the IOD to access the DDR channels.
> 
> 
> 
> There are 2 "types" of WHEA errors running high FCLK.
> 
> One is the high data rate flow which you get constantly and usually raise in speed when you are idling.
> The fast pace will bog down the system and changing voltages will not change much the pace.
> That's the type I made the WHEA Suppressor for.
> 
> I can say in this case the VGA has a very important role.
> Since I switched to the 3080ti it doesn't happen anymore, at all.
> I would have thought PCIe Gen4 would be more of a problem but maybe since the protocol itself is more resilient it helps instead.
> These are what I call the "fake" WHEA errors; they are not related to resources usage at all.
> 
> I only have WHEA errors under load right now. Not a single one in idle or low load.
> Which is the 2nd type of WHEA errors and for which I wouldn't recommend to use the WHEA suppressor.
> Unless you decide that you are fine with it.
> If the ratio between the degradation from the corrected errors and the performance uplift is still positive it's risky but could be worth.
> Still I wouldn't recommend it at all unless your really know what you are doing and you don't need to save lives with your PC
> 
> It's much more interesting now cause I can finally see what is triggering WHEA and what not and at which pace.
> Clearly it's not/not only related to memory/GMI link usage.
> Some y-cruncher tests or P95 with CoreCycler doesn't use much of memory bandwidth and triggers a lot of WHEA.
> I'll have to compare with water cooling but I have the feeling at least in some cases it's strictly related to thermals.
> y-cruncher BBP test doesn't trigger many WHEA if at all, mostly when the temperature is going up.
> 
> Anyway the CPU always plays a central role of course.
> It depends on FCLK, which is purely a CPU thing, and WHEAs are reported by the CPU.
> There are for sure other components involved but the CPU is the main actor here.
> If there's also something else not playing along, like the GPU, the chipset, the Realtek NIC, etc surely doesn't help.
> 
> Hard to say but I'm very skeptical about the CPUs which doesn't report WHEA.
> I have the feeling it's more likely that they don't report correctly instead, as they have their own suppressor inside
> Maybe a lucky combination of low grade CCD and high grade IOD.


Sorry I should have been more specific, I used the word "issues", should have said WHEA 19s.

My estimation of weights has to do with logged event 19 events

Those of you running the 3DMark "CPU Profile" benchmark, are those result you are showing with your 24/7 stable settings or just your attempt to get the highest score ??

My 24/7 stable results are no where near what @PJVol has shared ...

I know if I tweak my CO to different values that I will get near the top ...

** EDIT **
Who is next ??


----------



## Ultranoc

Veii said:


> What do you mean with "you" are crazy ?
> OCCT shows the CPU is unstable, TM5 shows the ram is unstable
> View attachment 2515508
> 
> Meaning, tWTR to 5-14 or drop tRCDWR to 13
> Be sure you are y-cruncher stable & if not - screenshot where you fail
> 
> Also try with SD, DD 1-4-4-1-6-6 for now, till you can run 1-5-5-1-7-7
> You want to also drop RTT_PARK once, it's too strong on /1


Thank you very much, I changed the settings as you said and it works 
Is there anything else I should change now please?


----------



## Veii

Ultranoc said:


> Thank you very much, I changed the settings as you said and it works
> Is there anything else I should change now please?


You have surprisingly low temps for RTT_PARK /2. 
Is your room air-conditioned ? 

Do you want to try one more thing and check if timings improve
Drop tRRD_L to 6
increase SD, DD's to 1-5-5-1-7-7

Then adjust CAD_BUS to 30-20-30-20 & see if this passes
You can also try 30-20-20-24 ~ but you will need to change and redo memory training in CBS, UMC, MBIST, DATA-Eye mode
* Do not enable Data-Eye training mode, else it will take 50-60sec to post. it's good but it takes far to long. Shared things bellow are a bit better ~ and only increase post time to 3sec


Spoiler: These two things:












Just Aggressor to 3 or 5 , instead of 9 & VMR pattern length to A or 9 ~ up to bios, A = 10 = a = HEX value








These to 1-1-1-1-1








And logically this one to extend the normal Training amount


----------



## Veii

PJVol said:


> I'm afraid not much, I've spent some time looking for possible benefits, but with no avail. What you called "throttle" seem to have little to power management.
> TM5 makes CPU reach my manually set 115A EDC limit almost instantly, and RAM is [email protected], let alone 4000+
> 
> Btw, forgot to ask  Does your Win 11 build work fine regarding ACPI power management? Does new scheduler has full control over CPU performance ? I mean has it have the access to CPB directly?


Precision boost seems to function, but something is throttling Ryzen Cache performance
I think to go back to 21H1 clean, as it doesn't mask issues for me (like here with broken cache perf)
Thank you @domdtxdissar ~ soo it's how i thought
Cache access latency looks fine, but the curve has to look something like this:








Yet a bit wider spectrum on the 1kB side and the 1MB side
The 5950X has a similar curve to the Green 3600X ~ well or any dual CCD unit
I can not utilize any dual CCD performance boosts sadly, but this Core 15 (16th) used "single core" is strange
Why does it have to use the 2nd CCD core. But it can be just wrong ACPI readout. I am not sure yet

I am sure tho that even when latency looks similar,
Performance for it suffers, bandwidth & Microsoft stopped updating the dev build

Game performance is fine on it for some reason , and the 64kB spike is bigger
Funny how sharp it is on your side ~ but i get similar results
Soo only Microsoft is to blame. The new microcode which will be enforced to everyone soon ~ has only issues. Couldn't find anything positive on it yet.

Probably will downgrade tomorrow back
It was fun and i liked it but cache doesn't better up even with CTR or any allcore.
There is some kernel issue or enforced throttling

But speaking about throttling,
You guys know that PROCHOT is 65c on the 5600X lable
well it seems to throttle for me at exactly 75c on X8 scalar
I need to doublecheck how much load it put, if it just randomly hold 75c and rather hit the 122A fuse limit
But i noticed it thermal throttling again.

Oh @domdtxdissar
You might want to redo your PX and OB settings with A-Normal mode
Affinity unaware normal mode. It should perform better for benchmarks, tho CPPC aware PX will run higher frequency
Affinity "unaware" mode (A mode) is better for programms like 3D mark, some games and Aida64
* have to also get something runnable out of it. It's hard to beat 4.85 PBO on -30 CO, but thermal throttle bothers me now too much
** sadly miss the "custom" Patreon specific boost-config. No reserves to support Yuri for now ~ sadly


http://imgur.com/9tFmYWl


----------



## ManniX-ITA

@Veii

Thought limiting the frequency via the power plan would avoid the overboost issue but it's not working 100%...
I'll have to disable DF C States and fix the negative counts.

The CPUMark bench works tremendously well for spotting the overboost peaks, especially the 4 threads run:

















I'm very surprised it doesn't random reboot at all but I'm not confident running it like that


----------



## PJVol

Veii said:


> I can not utilize any dual CCD performance boosts sadly, but this Core 15 (16th) used "single core" is strange
> Why does it have to use the 2nd CCD core. But it can be just wrong ACPI readout. I am not sure yet


I don't know, why you still believe that core being from CCD1, since your pm_table data says its not.
Here are C6 residency of all 16 cores in your CPU (from Core0 to Core15):


> Offset 4E4: 100,00000000
> Offset 4E8: 100,00000000
> Offset 4EC: 100,00000000
> Offset 4F0: 100,00000000
> Offset 4F4: 100,00000000
> Offset 4F8: 100,00000000
> Offset 4FC: 100,00000000
> Offset 500: 100,00000000
> Offset 504: 0,00000000
> Offset 508: 0,00000000
> Offset 50C: 100,00000000
> Offset 510: 100,00000000
> Offset 514: 0,00000000
> Offset 518: 0,00000000
> Offset 51C: 0,00000000
> Offset 520: 0,00000000


Just wanna save your precious time for the more valuable explorations, so as we, the community members, surely would appreciate it 



Veii said:


> You guys know that PROCHOT is 65c on the 5600X lable


I may be wrong with the exact numbers, but AFAIK prochot is 95° for 5600x and 105° for the rest.
HWInfo64 has "sensor" that should have trigerred on prochot assertion.


----------



## Nighthog

XPEHOPE3 said:


> Did you try 1933 or 1866 FCLK (with all other settings being the same) to see if Aida latency would improve?


I'm still tweaking and testing but here is a result for 5000Mhz 17-23-17-46-100 1T GDM:disabled.

Getting ~61ns in 2:1 FCLK:MCLK Mode with the 4650G @ 2266FCLK.
Mostly stable as I'm tightening it down and figuring out what can run.

I was trying 5100Mhz way too long, nothing could make it stable but it booted so I really wanted to make it run but nothing had effect on stability.

So I have two systems doing 5000Mhz with these kits, stable.
X570 Xtreme has no issues booting 5100Mhz but nothing is allowing it to run with any kind of stability that I could see. Tested practically everything.


----------



## Veii

ManniX-ITA said:


> 'll have to disable DF C States and fix the negative counts.
> 
> The CPUMark bench works tremendously well for spotting the overboost peaks, especially the 4 threads run:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I'm very surprised it doesn't random reboot at all but I'm not confident running it like that


Ehm

That temp spike worries me much more

Ok, SMU likely hang up, FIT likely broke
But this is actually really bad ~ if FIT froze

I sadly can not find right now my old 45Ghz peak overboost's 
but figured, over ACPI value 200, it usually crashes ~ near 230-250, which is around 8-9ghz
Usually before when we had peak limiters on the powerplan, CPPC turned into another method and used








2-1-1-3-4-1, or with better CO 1-1-1-3-4-1
Currently or rather since dLDO Injector came through, things got buggy and we can have less fun
This was 1100A SMU 56.30




Spoiler: Oh this is how real package throttle & autocorrection looks like



















These pictures are from 26th of November, 2020 
And let me "who doesn't contribute anything"
Also repost some of the "easy to run 1.46v timings " for figuring out high FCLK








I am not sure if these low voltages still work, now that dLDO bothers and more autocorrection happens
(Date 11th of December, 2020)
But yes ~ i've played through Vermeer already
There is not much "new" to post except repeating myself and that way "spamming" the thread
This was also before CTR 2.0 exist 

I hope next time people try to judge me, they have a better argument & foundation / reason
Spend 4-5 months on Vermeer, fulltime ~ before now taking a pause out of everything, as money for food alone is lacking ~ nor to think about rent
I can not justify sticking my nose on something that fully lacks any information and everything is under NDA and hidden. Sorry but WHEA research continues when it coninues
Don't be a b*tch about it (generally speaking, ManniX behaves very polite) and maybe motivation to spend day & night on it, will come back
So far, it's a "rather not" ~ as i don't get issues with everything i learned & shared , soo why bother wasting life-time instead of educating myself on different hobbies

New year will be interesting, but for now it's booring and no positive updates or bioses come out
nothing from asrock, nothing from AMD ~ it's booring / only annoying rev.E is entertaining


PJVol said:


> I don't know, why you keep insisting on that core being from another CCD, but it's obviously not the case, based on your pm_table data.


I don't know, things changed and i noticed it just now
This was with the new microcode
Wouldn't expect core 15-16 to be on the first CCD & trusted 1usmus that the core layout is fixed and rewritten after several attempts 🤭😙
Soo such "bugs" shouldn't be happening in the first place, no ?

Wouldn't PM_Table data be wrong , if ACPI assigns them random values based on the microcode recognition ?
Attached current PM_Table back from 0009 Microcode


PJVol said:


> I may be wrong with the exact numbers, but AFAIK prochot is 95° for 5600x and 105° for the rest.
> HWInfo64 has "sensor" that trigerred when prochot assertion is "true".


I noticed thermal throttle earlier, and Tool.exe reports 65c for it
Noticed throttle on CCA which was not only EDC based & THM limits did not limit it ~ if they really are accepted.


----------



## PJVol

Veii said:


> Attached current PM_Table back from 0009 Microcode


Nah... not much changed from 380804, aside from several entries were added and all per core data have been shifted 3 dwords forth.

Core temps:


> Offset 330: 41,89286000
> Offset 334: 45,64286000
> Offset 338: 42,07143000
> Offset 33C: 46,14286000
> Offset 340: 41,71429000
> Offset 344: 46,25000000
> Offset 348: 42,10714000
> Offset 34C: 46,00000000
> Offset 350: 58,75000000 core 0
> Offset 354: 54,28572000 core 1
> Offset 358: 49,25000000
> Offset 35C: 48,64286000
> Offset 360: 58,14286000 core 2
> Offset 364: 58,00000000 core 3
> Offset 368: 69,14286000 core 4
> Offset 36C: 68,75000000 core 5





Veii said:


> Wouldn't PM_Table data be wrong , if ACPI assigns them random values based on the microcode recognition ?


What ACPI has to do with pm_table generation by SMU firmware?
Afaik, acpi may assign whatever ID's it wants to the virtual cores, but not sure it may change what smu responses.


----------



## Veii

PJVol said:


> What ACPI has to do with pm_table generation by SMU firmware?
> Afaik, acpi may assign whatever ID's it wants to the virtual cores, but not sure it may change what smu responses.


I question 
Because SMU ABL readout can share more or less data, up to what i set it up in the bios








Sadly i am not sure where it stores the data-eye logs
It says (on the ASUS board) that it is in a temporary partition of ABL
Yet haven't found anything

Using them, could potentially visualize how RTTs behave , and make memory OC easier / or give the ability to write a software for such

I question PM_Table, as 2nd CCD flicker-wakes up (which is normal)
But get's suspended/killed again

I would love to understand or own a bit more tools on this topic, but sadly do not know or have anything
1rusanovBG SMU_DEBUG tool is yet not compiled for Vermeer, but got the patches 2 weeks ago
Like once mentioned, one man army ~ i'm on my own & was on my own the whole time for Vermeer
* if OPN number could be rebranded, i could lift this AMD lock and probably let the microcode recognize it as 5950X
** as the cores are not locked, and if they where before, aren't anymore  There is no PSP Firmware lock on my sample.
*** Microcode just doesn't load 5950X modules, soo ACPI can not give sleepy cores work. They only sit and are bored + waste power from AMD's tiny enforced 122A fuse limit
**** Sadly i'm too dumb to write an ACPI patch for OSX, but it does recognize all 0-31 threads, just microcode doesn't share correct ACPI ID, so no load can be assigned either


----------



## Corhone

CarnageBT said:


> Yea, it works. I set it to 10 minutes / core so that it completes all the tests on each core, otherwise, at 6m, if will switch before running all tests. Y cruncher through CC runs all the tests except for C17 test, so you might want to test that one directly in y cruncher after the CC version.
> 
> Is there a way to change CC to run all y cruncher tests for 2m, vs the default 1m?


You can by editing "script-corecycler.ps1" (line 2939). And you can also add C17 if you want to.


----------



## PJVol

@Veii
You may look at the acpi id's for your cores as welk and check if all of them share the same L3 block (ID), cause
L3SharedId = ApicId >> log2(NumSharingCache + 1)

The formula is suggested by AMD to determine, whether certain cores shared the same l3, or in other words are in the same CCX (or CCD in zen3)


----------



## Veii

PJVol said:


> @Veii
> You may look at the acpi id's for your cores as welk and check if all of them share the same L3 block (ID), cause
> L3SharedId = ApicId >> log2(NumSharingCache + 1)
> 
> The formula is suggested by AMD to determine, whether certain cores shared the same l3, or in other words are in the same CCX (or CCD in zen3)


Uhm, how would i do that ? 😅


----------



## ManniX-ITA

Veii said:


> Ehm
> 
> That temp spike worries me much more


That's what worries me of course 
Usually 3Dmark it's catching spikes at 6GHz and something at about 105-110c
Which is already enough worrying... I guess there's more which is just too fast to be catch

Anyway I've found out that disabling DF C State is not enough to avoid the overboost peaks.
Same thing happens, albeit a bit less frequently, with manual DPM LCK.
I was using 2-1-1-2 and I've tested also 2-1-1-1. They both triggers spikes.
Only way to avoid is to set also DPM LCLK to Auto. At least so far I wasn't able to reproduce it with multiple runs.


----------



## adversary

Veii said:


> It's this thread
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> AMD's early stepping for Matisse (thanks The Stilt) was 50mV , at least enforced 50mV stepping
> 
> 
> 
> 
> 
> 
> 
> 
> Strictly technical: Matisse (Not really)
> 
> 
> 07/08/2019 6:33 PM (GMT) - Update on the bios issue on Crosshair VIII Hero motherboard ("the thing"). Earlier today I received a response to my inquiries from ASUS. The response was rather technical and I cannot go into the specifics of what exactly it involved. However, it confirmed my...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> But 50 and 75mV worked well
> OC'ing T-Force 4133 cl18 (bottom half of the thread)
> 
> This generation (Vermeer) it's 40mV as minimum stepping between all of the 3 & 1 higher procODT than Matisse
> Only one exception exists, which is that VDDG CCD can be equal to cLDO_VDDP , but it often might be better 40 or 80mV over it
> 
> this post sums it up, with the relinked reddit in the quote
> MSI B550 Unify / Unify-X Overclocking & Discussions... credits to weleh
> The comments of reddit sum it up
> AMD starts to enforce removal of 1200, 1181/1191 and 1201
> while these bioses where one of the few without usb dropouts
> And yet nearly no one has 1203B out , only 1203A , which did nothing against usb droupouts




Pardon me for replying too late and bringing up posts old for some days (and you have more advanced topics at moment being discussed). At moment situation are here specific, I don't have access to PC all time (but soon it will end as we are near end of competetive play). On top of that, global temperatures are insane this year, forcing me to leave my city for some days from time to time. Hope it will normalise at least to usual summer temps 
I however read this thread and document all time from mobile, all stuff I find it useful.

Now for this motherboard 1203A is released as stable, and 1203B as Beta. there is no rush, guess I will wait until get 1203B stable while collecting info about it.

Now on 1201A all works fine, old problems are gone for months after last tuning. Zero issues or problems.
on 3800/1900, dual-rank, I made 51.9ns (chiller off, radiator fans on)
on 3800/1900, same RAM, I made 51.2ns (chiller on, radiator fans off), but lowering tRCDRD from 14 to 13 (as 13 is stable and full error free only below certain RAM temperature point).
Tested with number of tests, including usmus TM5 25 cycle, and AntaExtreme for some time. no errors, and no variance in Aida64 repeated runs.
(result is in Google Datasheet)

However, how my twaking is really proper or good, I put in question, it may be that I "bruteforced" stability with very low RAM temps (it is also under chiller cooling). Hence I would try to do complete new tweaking once I do BIOS update and get more time. So I'm trying to catch all info in meantime.

Back to direct topic - my voltages used for this, running now, are :
(what ZenTimings 1.2.3 read)

CLDO VDDP - 0.8973V
CDDG CCD - 0.9032V
CDDG IOD - 0.9710V
VSOC - 1.0875V (set in BIOS 1.1V)


I did read all you linked. However, some users, and also you mentioned something, that running CCD voltage above 940mV caused another issues?

Could I try to run CLDO VDDP for example 0.88V, while using stepping of 40mV or more to separate it from CLDO VDDP, and to try to still have CCD not above 940mV, ?

I'm looking now in proper direction? Maybe another voltages, with your advice that it is still better to have stepping between CLDO VDDP and CDDG CCD, could be better solution? If needed, I can link my ZenTimings picture.


----------



## ManniX-ITA

Nope it still happens, just less frequently...


----------



## ENTERPRISE

Closed for cleaning.


----------



## ENTERPRISE

Re-opened.


----------



## KedarWolf

If you really want to clean this thread up, try the command,



Code:


/delete KedarWolf


----------



## Veii

KedarWolf said:


> If you really want to clean this thread up, try the command,
> 
> 
> 
> Code:
> 
> 
> /delete KedarWolf


Probably 1800 from me too haha
Good to be back in our lovely thread 🤭








Nothing special changed either
Buggy Thread Scheduler still remains buggy on Win 11
It also is sometimes called Windows 10 21H2, sometimes Windows 11
L1 and L2 cache at least seem on point latency wise, but L3 remains bad

SETUP Timings seem to work out after all with RTT_WR /2 & WR/2 seems to work out for 2x8GB too, when you exceed +1.62v
Not much new to say yet.. ASRock still takes their time with 1.2.0.3B and ignores their ITX lineup, as usual

Anybody tried Project Hydra (CTR 3.0) yet ?
v0.01 should've been released yesterday

@Netarangi , i think you wheren't done with XMP and asking for help with Samsung-C die the other day
Hop over here in the correct thread


----------



## domdtxdissar

Veii said:


> Anybody tried Project Hydra (CTR 3.0) yet ?
> v0.01 should've been released yesterday


Tentative release date for early access is the end of July. Public release will not be until September at the earliest. Demonstration of the graphical shell will take place at the end of June.

--------------------------------------------------------------------------------------------------------------------

Like i wrote in the other thread, have done some benching in windows11 and in my testing win11 is atleast as fast, or even faster then win10 in everything other then AIDA L3 bench.
Some memory and cpu performance testing screenshots: (more in link above)










































































_edit_
Forgot to link Geenbench runs









Geekbench 3









Geekbench 4
Min rekord geekbench 4 ifra januar i år (8215/74733 points)









Geekbench 5
Min rekord geekbench 5 ifra januar i år (1844/20054 points)

In my view, the "problem" lies with aida64, not windows11 in regards to strange L3 readings with zen3 in aida.


----------



## Veii

domdtxdissar said:


> Like i wrote in the other thread, have done some benching in windows11 and in my testing win11 is atleast as fast, or even faster then win10 in everything other then AIDA L3 bench.
> Some memory and cpu performance testing screenshots: (more in link above)


It is performant 
Ryzen should be able to function without any chipset drivers or powerplans
Yet it still is buggy and has to be better

Nice 51.5ns for 3800MT/s 
This fully doesn't run ?








tRFC 2 and 4 should've been another value, if these are 2x16Gb ~ nevertheless if tWR 10 runs or not


----------



## domdtxdissar

Veii said:


> tRFC 2 and 4 should've been another value, if these are 2x16Gb ~ nevertheless if


I'm running 4*8 GB 








@ 1.54 vdimm in bios










Have been pretty happy the the results lately, haven't tried to tweak anything in a while..


----------



## Veii

domdtxdissar said:


> I'm running 4*8 GB


Oh then ignore tRFC, but you should be able to run tWR 10, tRTP 5 , tRRD_L 5
I hope 

Personally think it can lead to more perf, but you have to test what makes more sense
This set in BGS mode, or tRTP 5 in BGS 2+2 mode (alternative) instead of 1+1+1+1 mode

From my old 1700X testing, i saw tRRD_L higher, giving better perf ~ even when both are rock stable. Probably a sync "issue"

EDIT:
There seems to be a thing "to match tRRD_L with tRTP" , but i haven't verified it actually doing anything reasonable
I feel like matching tRTPns inside tRFC range, makes more sense ~ perf wise


----------



## domdtxdissar

Veii said:


> Oh then ignore tRFC, but you should be able to run tWR 10, tRTP 5 , tRRD_L 5
> I hope
> 
> Personally think it can lead to more perf, but you have to test what makes more sense
> This set in BGS mode, or tRTP 5 in BGS 2+2 mode (alternative) instead of 1+1+1+1 mode
> 
> From my old 1700X testing, i saw tRRD_L higher, giving better perf ~ even when both are rock stable. Probably a sync "issue"


Around ~100mb/s higher copy and 51.4ns on first try.. Wil try to run some stability testing 








I have also tried pure t1 without addcmdsetup 56 all the way up to 1.62 vdimm, could not even complete aida64 bench without bluescreen, so 56 setup timing is needed my for 4*8gb setup


----------



## Veii

domdtxdissar said:


> Around ~100mb/s higher copy and 51.4ns on first try.. Wil try to run some stability testing
> View attachment 2516130


tWR gives a perf boost, and i think it's more worth than the ones tRRD_ give
but tRTP 5 is not easy to run


----------



## Veii

domdtxdissar said:


>


Can you check what tCCD_L is on your side ?
if it's 6, you can run tRC 38
But i am not sure about that low tRAS


----------



## byDenoso

Is 1.5v safe to use on a Hynix DJR 17nm on 24/7?


----------



## domdtxdissar

Veii said:


> Can you check what tCCD_L is on your side ?
> if it's 6, you can run tRC 38
> But i am not sure about that low tRAS


Where do i find "tCCD_L" ? (nothing comes up when i search for tCCD in bios)
Is it this ?









Anyway, im running some stability testing with your suggested settings now: (lower then normal ctr settings for extra stability)


----------



## Takla

4x8GB Micron E-die (19nm from 2019)

Set Voltages:
1.10v SoC
0.90v VDDP
0.95v VDDG
1.35v DRAM

I left tRFC2 & 4 on auto in the tm5 image because they didn't change anything.
Changed tertiary to 1-5-5-1-7-7 (from 1-4-4-1-6-6) *thoughts on this?* I think 5-7 might perform better.

Also, thoughts on tCKE greater then 1? I measured with an infrared thermometer on the dram heatsink (since no temp sensor) tCKE 1 or 6 made no difference after 25min karhu each. I heard earlier agesas do not allow tcke without power down, is that true?

SCL on 3 gave errors after 10min karhu. tWR on 12 gave errors after 5min karhu. tRTP can be set to its lowest possible, 5, pretty comically. It doesn't do anything for performance though.

I might give tRRD_L at 6 a try, I doubt its gonna changes anything though.


----------



## Veii

domdtxdissar said:


> Where do i find "tCCD_L" ? (nothing comes up when i search for tCCD in bios)
> Is it this ?


Inside SPD-Z, it can only be generated from the XMP profile
On this window you want to set testing pattterns to both. Pattern length to A or 9 
And aggressors to 3 or 5 instead of 9
That's memory training , slightly modified 

For your current set i'd even put tRP 13 on it
My suggestions where for 14-14-14 
tRC suggestion was for 14-8-14, but i think this won't be that fine
Math wise it's not soo good


----------



## XPEHOPE3

Veii said:


> Inside SPD-Z, it can only be generated from the XMP profile


I saw people mentioning that tCCD_L thing from time to time, but only saw Taiphoon Burner to be able to read it. Unfortunately it's banned for Russian users. But from that comment I probably was able to google for a "replacement" tool: PassMark's RAMMon.

However it reports tCCD_L*min*, and in *ns* (for unspecified clock! JEDEC or XMP or what?), not in cycles:














Can anyone please check if it reports the same tCCD_L as Taiphoon Burner or ASUS BIOS? For that it's needed to convert tCCD_Lmin from RAMMon to cycles using either JEDEC or XMP clocks and compare it to Taiphoon Burner (or ASUS BIOS on some mobos).

In my case values are:
tCCD_Lmin = 5.625ns
JEDEC clock = 2133MHz = 0.938ns for 1 cycle
XMP clock = 3200MHZ = 0.625ns for 1 cycle
So tCCD_L min is either 5.625/0.938 ~ 6 cycles, or 5.626/0.625 = 9 cycles.


----------



## adversary

domdtxdissar said:


> So.. Have been playing around with Windows 11, some results from me:
> 
> Forgot to show in screenshot, but this is *51.6 ns with both CCD enabled* and all 32 threads.
> View attachment 2515411



I was about to ask for this but this thread was closed for few days.
This is (at least from what I seen for 2 CCD Zen3 CPUs) impressive low latency.

Usually 2 CCD units have about 2ns more. I wonder how you get 51.6 on 1900.

Is trick something with Win11? 
or with 1T with setup timings 56-56-56? 

Did you compare what you get if you run 2T without 56-56-56?

I would like to hear more, in future I may upgrade to 2 CCD Zen3 refresh so it additionally interest me.


----------



## Veii

XPEHOPE3 said:


> However it reports tCCD_L*min*, and in *ns* (for unspecified clock! JEDEC or XMP or what?), not in cycles:


tCCD_L will be different between JEDEC and XMP 
Both are still "predictions" , but it can be used for calculation - as replacement for tBL math
XMP mostly are based on it 

Bioses report it
Close to every board has a feature that reports the XMP profile in the bios
You can also use tRFC mini Value-Ns calculator, if you aren't sure about the math


----------



## domdtxdissar

XPEHOPE3 said:


> I saw people mentioning that tCCD_L thing from time to time, but only saw Taiphoon Burner to be able to read it. Unfortunately it's banned for Russian users. But from that comment I probably was able to google for a "replacement" tool: PassMark's RAMMon.
> 
> However it reports tCCD_L*min*, and in *ns* (for unspecified clock! JEDEC or XMP or what?), not in cycles:
> View attachment 2516160
> View attachment 2516161
> 
> 
> Can anyone please check if it reports the same tCCD_L as Taiphoon Burner or ASUS BIOS? For that it's needed to convert tCCD_Lmin from RAMMon to cycles using either JEDEC or XMP clocks and compare it to Taiphoon Burner (or ASUS BIOS on some mobos).
> 
> In my case values are:
> tCCD_Lmin = 5.625ns
> JEDEC clock = 2133MHz = 0.938ns for 1 cycle
> XMP clock = 3200MHZ = 0.625ns for 1 cycle
> So tCCD_L min is either 5.625/0.938 ~ 6 cycles, or 5.626/0.625 = 9 cycles.


They both read the same 5.625ns



















Veii said:


> For your current set i'd even put tRP 13 on it
> My suggestions where for 14-14-14
> tRC suggestion was for 14-8-14, but i think this won't be that fine
> Math wise it's not soo good


So if i understand you correctly, these are the settings you think are optimal ?


----------



## i9forever

byDenoso said:


> Is 1.5v safe to use on a Hynix DJR 17nm on 24/7?


Yes it is.
If not A0 modules - I stand corrected thanks to Veii.


----------



## domdtxdissar

adversary said:


> I was about to ask for this but this thread was closed for few days.
> This is (at least from what I seen for 2 CCD Zen3 CPUs) impressive low latency.
> 
> Usually 2 CCD units have about 2ns more. I wonder how you get 51.6 on 1900.
> 
> Is trick something with Win11?
> or with 1T with setup timings 56-56-56?
> 
> Did you compare what you get if you run 2T without 56-56-56?
> 
> I would like to hear more, in future I may upgrade to 2 CCD Zen3 refresh so it additionally interest me.


Its down to CTR trickery.. without it enabled i have normal dual ccd latency (~53.5-54ns @ 1900 IF)


----------



## XPEHOPE3

domdtxdissar said:


> They both read the same 5.625ns


Ty.
Strange, maybe I saw screenshots from some old version then, which reported it in cycles. Or I think you can change that "Show delays in nanoseconds" thing in the end (by pressing it or in menu) and then it will report in cycles


----------



## craxton

well, i QUICKLY (after almost a week trying) to get 1.53v 3800c14 stable on my 
SIL quailty 133.xx 5800x stable. and now have something SUPER STRANGE to where
HWiNFO while running SNAPSHOT pooling makes VID, and Clocks dissapear....tried revo uninstaller,
tried CCLEANER, removed ALL registry files i could (that win 10/11 layover) would allow.
yet none seemed to work....removed anything releated to hwinfo from the entire system and 
used a 4 day old restore point and that still didnt help...so, i cant run snapshot pooling.

i do know 1.2.0.3 (a/b either or) breaks snapshot pooling for ryzen but theres already been a released fix for it.
to which im clueless...
does ANY of you fellas have any tools that removes files that windows wont allow normally and one can CTRL+F and find what it 
is i wish to remove? or know a way WITHOUT reinstalling the entire OS ? pretty sure while tryin to get 3800c14 working (which got me 51.6ns max realistic bandwith etc)
i corrupted something there...so, if one or several know a way to possibly get this back working im all ears! 

as i kinda need that working. pic for making others jealous  to bad anything over 1900 still has WHEAs but i can
slow them WAY down on boot up-to 1966.


Spoiler


----------



## Veii

domdtxdissar said:


> In my view, the "problem" lies with aida64, not windows11 in regards to strange L3 readings with zen3 in aida.


This would exclude SiSandra behavior
SiSandra does remain buggy for me too
it's good that Vermeer can at least function without much OS support
Maybe ProWorkstation is even less finished than normal Pro ?


byDenoso said:


> Is 1.5v safe to use on a Hynix DJR 17nm on 24/7?


All depends on the PCB if A0 or not A0
1.48v is easily fine - depends on RTT_PARK too
Voltage doesn't do much on it's own


Takla said:


> I might give tRRD_L at 6 a try, I doubt its gonna changes anything though.


It's not always 6
My Rev.E's are tCCD_L 7 on their PCB
My B-dies where 6, but they can work even as tBURST 2 instead of 4 or 6
Not everything is on 6


domdtxdissar said:


> So if i understand you correctly, these are the settings you think are optimal ?


I dont like your tRAS, but when it runs well, it runs well 
Most of the times, flat timings perform better after all
But if you're really bored, you can take my path of bruteforcing primaries
13-13-13-13 🤭
With bump on tRRD, tWTR,, and tWR
Later you can lower them


craxton said:


> VID, and Clocks dissapear


Cores dissapear ?
I've seen on MSi boards cores fully disappear or take a long time at the start to come on
But that looked like an HWInfo tthing


craxton said:


> does ANY of you fellas have any tools that removes files that windows wont allow normally and one can CTRL+F and find what it
> is i wish to remove? or know a way WITHOUT reinstalling the entire OS ? pretty sure while tryin to get 3800c14 working (which got me 51.6ns max realistic bandwith etc)
> i corrupted something there...so, if one or several know a way to possibly get this back working im all ears!


Remove files , ,yet not corrupt anything ?
Can you rephrase ?

Usually Sophia Script and NT-Lite are decent for such , depends on the request
Take Ownership reg file helps too if permissions are an issue
Windows10Manager.7z this windows 10 manager has a lot of useful tools too
Unsure what the request is


----------



## craxton

Veii said:


> Remove files , ,yet not corrupt anything ?
> Can you rephrase ?


(i mean) when i was trying to get 3800c14 stable i "corrupted my win11 OS?
or perhaps i need to "re-flash" the bios? idk...



Veii said:


> But that looked like an HWInfo tthing


its for sure something with HWiNFO, but it was working fine until
i was playing with "whats not broken at 3800c16"



Veii said:


> Windows10Manager.7z


was thinking of it, but when i tried to run a few things last time it
just "hung" and didnt do nothing. maybe was due to it being on the win 10 drive
and me just copy pasting it to the win 11 location.

(edit)
(yes its 32bit hwinfo, but it matters not which
i select to use. hwinfo 64 and hwinfo 32 both do the 
same thing.


----------



## craxton

was a bios issue, or that win 10 registry tool fixed it..... but reflashing the bios made it work again.
(EDIT) scratch that, was SOME SETTING inside the bios that was loading with my "saved" almost stable
c14 3800 profile. to which i reset defaults, then manually set the stuff i was trying to get.
"ALSO" to whomever is on the zen overclocking ram table sheet, i apologize for changing your config.

when i notice it being changed from what im inputting, i switch to another profile. but some of the tables are broken

were broken... to which, these 4x8 SR sticks, will NOT do tRDWR 8 nor tWRRD 3 or 1.


----------



## Takla

tCKE=6 has lower performance then tCKE=1? Working as intended?


----------



## byDenoso

@Veii 
Its a A2 PCB, so is fine to run it 1,5v?


----------



## craxton

hmm, error #10 in around cycle 2 12 min or so, 
so @Veii havent asked for timing suggestions at all. 
but this is something im struggling with, any suggestions?

prefer c14-14 but i suppose i could adjust.


----------



## craxton

byDenoso said:


> @Veii
> Its a A2 PCB, so is fine to run it 1,5v?


running up-to 1.53 in bios, reported in HWiNFO is 1.516 with LLC4 and droop to 1.512 with "max no load" up-to 1.520
tforce dark pro 3200c14 (different sets but the same sticks if that makes since?) no fan on dimms, trying to go 
with my AIO fans being enough as my dimms dont get hot to touch or the heat sinks dont.


----------



## XPEHOPE3

I was close to start pushing for 3867-16 as I've stability tested all previous configs and got e.g. 3800-16-1933fclk stable at 1.2.0.3A AGESA:














But then Gigabyte release 1.2.0.3B AGESA beta BIOS for my board which I flashed and got unstable (1,3,4,1,4):








Even at lower temperatures. Moreover, sometimes TM5 threads just died in the middle of cycle, for example on test 13 (and that didn't show up as error, just memory got freed and the rest of tests in cycle went very fast).

The only differences between those tests were:

Cooler ambient conditions
RAM cooling was a bit different. Before I ran 100% RPM fan against RAM, and now I used this setup. That could matter because shoving temperature sensor between RAM sticks made one of them less perpendicular to motherboard than it was previously. *Anyone encountered problems due to that?*
I also used different training as described here


Veii said:


> On this window you want to set testing pattterns to both. Pattern length to A or 9
> And aggressors to 3 or 5 instead of 9
> That's memory training , slightly modified


Aggressors set to 3, I only had 1,3,7 choices, pattern set to A, but anyway -- no ZenTimings-observable differences in timings.
1.2.0.3B BIOS instead of 1.2.0.3A.
Should I be sure it is definitely due to BIOS update? Do I really need to retest *all *my previously stable configs? Did anyone else encounter the same problems? After all, I didn't even fiddle with RTTs, CAD_BUS, setup timings, yet the RAM settings wouldn't survive BIOS update as it seems...


----------



## Nighthog

Yeah Gigabyte F34a was a little better for memory stability than F34c. [1.2.0.3a vs 1.2.0.3b]

I noticed the change on my X570 Xtreme running 5000Mhz MEM. Became a little harder to get stable for the settings I had. But it was really only a slight adjustment of DrvStr seems to have fixed it.
[20,20,20,20]-->[20,20,24,24]
But the difference was minimal and the DrvStr change made it better than F34a did with [20,20,20,20] that I could discern for now with F34c.


----------



## Veii

Takla said:


> tCKE=6 has lower performance then tCKE=1? Working as intended?


The GPU also shows variance between 1-5 points. I think it's test by test variance
In order to verify it functioning, you need to verify it causing issues
for example tCKE 3 likely won't run - or 13 shouldn't run anywhere between 3733-3800MT/s
I haven't seen tCKE changes anything around it on Matisse. First time noticed it on 2100 FCLK where any little option off, was causing crashes and reboots (unstable memory)
But for Matisse, everyone who tells you it doesn't do anything - likely is even right. Vermeer is different, but Matisse depends on the IMC FW & AGESA


byDenoso said:


> @Veii
> Its a A2 PCB, so is fine to run it 1,5v?


Yes and no (i can't guarantee your ICs will like it on the current preset)
Voltage doesn't matter, it's the RTT combination with it
RZQ/1 on RTT_PARK is too strong. It's suited for 1.25-1.42v, maybe 1.46 - but likely beyond 1.42v you get negative scaling
It's not suited for it

1.48+ too 1.51v, should run RTT_NOM /7 as minimum 








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


That's probably already the lowest you can go , maaybe tRTP 6 could run Why can't you increase IOD a bit - for 3800MT/s ? Maybe also tRDWR 11, tCWL 14 could run (maaybe if you have a tiny bit of reserves left) But it could need tWR 16 - you have to try I've tested with tRTP 6 and so far so...




www.overclock.net




this post finally fits as answer
Weaken RTT_PARK, use RTT_WR /2 if you manage to get it stable else /3 and decide between 
RTT_WR+CAD_BUS
tCKE + SETUP TImings
CKE+RTT_WR

it's not easy to manage 3 types of powerdowns in sync
only two work most of the times
Either you go down to X-20-20-20 CAD_BUS and use setup times with it 
or you run the typical X-20-24-20 or X-20-20-24 (for Matisse) and you common RTTs
Voltage alone does nothing, all depends on the strength of ClkDrvStr (CAD_BUS) and strength of RTT's , till it's really dangerous and a bad idea
I daily 1.64v currently barely exceeding 44c at worst ~ in a hot 32-34c day . Idle/Gaming it's mostly 6-7c above ambient

Voltage does barely anyhting to heat 
Google Ohm's law , how amperage changes


----------



## Veii

XPEHOPE3 said:


> But then Gigabyte release 1.2.0.3B AGESA beta BIOS for my board which I flashed and got unstable (1,3,4,1,4):


1,3 1,4's (i only had 4's)
Where mostly tFAW related
I had this by going from 56.44 to 56.50 & had to redesign my set
The IMC FW change , also changed the "stock" behaviour on couple of options
You mostly want to try using tFAW calculation as tRRD_S * tCCD_L now
Of find that BURST Refresh Mode override flag, inside AMD CBS , near UMC or DF options - near the DDR4 menu's
Urg & SubUrgRef are different, soo tFAW "math" breaks (UrgRefLimit needs to match tCCD_L, SubUrgRef can be *4 ~ well it's a tRRD _S and _L thing)

You can notice it is wrong by going * tCCD_L and then lowering it by 2
If this is stable but * tCCD_L is not, then you have to change the flag in AMD CBS or redesign your test a bit








If they updated DQs, RZQ & procODT behavior again
You likely need to drop procODT by one value (weaker) and/or drop RTT_PARK by one value weaker (higher / divider or lower ohm value ~ up to bios translation)


XPEHOPE3 said:


> Aggressors set to 3, I only had 1,3,7 choices, pattern set to A, but anyway -- no ZenTimings-observable differences in timings.
> 1.2.0.3B BIOS instead of 1.2.0.3A.


And pattern testing to both 
It affects the way memory training behaves -doesn't change any timings


----------



## XPEHOPE3

Nighthog said:


> Became a little harder to get stable for the settings I had. But it was really only a slight adjustment of DrvStr seems to have fixed it.
> [20,20,20,20]-->[20,20,24,24]





Veii said:


> If they updated DQs, RZQ & procODT behavior again
> You likely need to drop procODT by one value (weaker) and/or drop RTT_PARK by one value weaker (higher / divider or lower ohm value ~ up to bios translation)


Be it for new BIOS or for @Veii RAM training suggestions, I can now boot with RTTPark RZQ/2 for the first time ever  (previously it wouldn't post)
I think that's the right lead (in comparison to 'timings' lead). Decided to test it and see where it fails. Then maybe CAD_BUS test since 1 & 4 point to it as well. The original plan was to stick to the same timings (apart from main), change voltages/procODT/RTTs only, and fiddle with timings only when frequency wall was hit. From timings I only changed SD/DD for now to be able to post 3867 later on.


Veii said:


> also changed the "stock" behaviour on couple of options


I checked stock RAM timings (under CBS there's another menu for timings where some are set even when they are on Auto in the main menu, e.g. tWRRD 5 for me) -- they were the same, incl. tFAW of 39. For tCCD_L again I don't know for sure if it's 6 or 9. And since you are saying it's different for JEDEC and XMP clocks, it must also be different for any other clock. Assuming tCCD_L=6, tFAW would be 36. How a higher than required tFAW would break anything?


----------



## Nighthog

Veii said:


> 1,3 1,4's (i only had 4's)
> Where mostly tFAW related
> I had this by going from 56.44 to 56.50 & had to redesign my set
> The IMC FW change , also changed the "stock" behaviour on couple of options
> You mostly want to try using tFAW calculation as tRRD_S * tCCD_L now
> Of find that BURST Refresh Mode override flag, inside AMD CBS , near UMC or DF options - near the DDR4 menu's
> Urg & SubUrgRef are different, soo tFAW "math" breaks (UrgRefLimit needs to match tCCD_L, SubUrgRef can be *4 ~ well it's a tRRD _S and _L thing)
> 
> You can notice it is wrong by going * tCCD_L and then lowering it by 2
> If this is stable but * tCCD_L is not, then you have to change the flag in AMD CBS or redesign your test a bit
> 
> 
> 
> 
> 
> 
> 
> 
> If they updated DQs, RZQ & procODT behavior again
> You likely need to drop procODT by one value (weaker) and/or drop RTT_PARK by one value weaker (higher / divider or lower ohm value ~ up to bios translation)
> 
> And pattern testing to both
> It affects the way memory training behaves -doesn't change any timings


Been seeing error 7 & error 4 depending on tFAW & other settings at the moment @ 5000Mhz on my Crucial Ballistix Max. 
Not been able to fix it entirely, best I've done is around 1hour stable for TM5 1usmus_v3 profile.

About Urg & SubUrgRef, how would I need to set them manually? I want to play with the setting but been clueless what it does or what values should be used.
You seem to have some clues with the above mention.


----------



## Veii

XPEHOPE3 said:


> I checked stock RAM timings (under CBS there's another menu for timings where some are set even when they are on Auto in the main menu, e.g. tWRRD 5 for me) -- they were the same, incl. tFAW of 39. For tCCD_L again I don't know for sure if it's 6 or 9. And since you are saying it's different for JEDEC and XMP clocks, it must also be different for any other clock. Assuming tCCD_L=6, tFAW would be 36. How a higher than required tFAW would break anything?


It's the bizarreness i noticed, while dom could continue with the ns lead 
I had to redo my whole set "again" , because quite a few things changed since SMU 56.50 (yet not every board runs equal patches - wouldn't wonder me if you just now notice a difference)

Speaking about differences,
Can you run both of the old and current bios through SMU Checker








Ryzen-SMU-Checker-1208.zip


Shared with Dropbox




www.dropbox.com




And see if the older one had a 0009 microcode, or both where on the one from April

On the current one i do have a 2100 FCLK lock
maybe requirements are different - but there is no way how i can post 2100+ at all, not to think about 2133 and higher

tFAW for me was acting bizarre till i discovered this Ref and SurUrgRef setting on the ASUS board
tCCD_L the bios uses for XMP "translation"
I am not sure by how much or after when it changes , was always curious on this value, back with Matisse
But Bios SPD-Z or Memory-Z (names differ by brand)
Do display it

Funnily 1-2 lower than the math on tFAW remained rock stable, but correct tFAW math then seemed to time out and break
That's usually how you notice something is off, soo the advice to test it that way if stability "out of nowhere changes drastically"


Nighthog said:


> About Urg & SubUrgRef, how would I need to set them manually? I want to play with the setting but been clueless what it does or what values should be used.
> You seem to have some clues with the above mention.


I think you can use them 2 ways (need bit more research with them)
For 1x tFAW mode you want to set SubUrgent to the typical 4* value how JEDEC defines it.
Urgent is when it has to close the ACTIVE window , and refuses to accept any commands. This allows for BURST refreshes and so 1x tFAW to function (if you enforce it on 1)

Or the other way around,
Urgent can be used for fixing when an "urgent refresh" has to happen. This is then tCCD_L optimally or whatever you selected for tFAW








And SubUrg can be then used as how JEDEC defines it for 4*
Oh i repeat myself
But this is how i utilized it (picture = stock currently)

You can enforce Urgent to be 1 and subUrg to keep the 4x limit up, or you can swap them and enforce Urgent to be up to X times 4 or 6
And suburgent to allow burst refreshes when they are needed inside the UrgLimit

Haven't decided what makes more sense now, but 1x tFAW trick to work, it needs a change here
And generally noticed that tFAW broke because of these introduced "stock" changes.
Afterwards started to use tCCD_L as math instead of tBL and Rev.E remained stable on everything i trow at them
* i still have random issues with tRC - can't get it lower for some reason, yet tRAS goes down to 2x tRCDmax without any additions to it. Something is off on my side still


Nighthog said:


> Been seeing error 7 & error 4 depending on tFAW & other settings at the moment @ 5000Mhz on my Crucial Ballistix Max.
> Not been able to fix it entirely, best I've done is around 1hour stable for TM5 1usmus_v3 profile.


Rev.E breaks stability for me around 1-1:30h for what appears to be stable at first
Error 7 would mostly point to CAD_BUS, and Error 4 remain PCB crashes
It's complicated

Nice 288ns 
I can only point you to experiment with RTT's
And maybe give this tRRD_L = tRTP wording a try ~ which i gathered from the Intel thread (never used it to judge how much sense it makes)
But error #4 needs to be resolved first


Veii said:


> And SubUrg can be then used as how JEDEC defines it for 4*


Reading my post, it's complicated
Urgent keep as the multiplier you use for tRRD_S to tFAW , probably as tCCD_L for stability
and SubUrgent you can fix it being JEDEC based, as 4x tRRD_S = tFAW ~ to allow BURST Refreshes as a limit of 4*

There is likely a better more accurate method utilizing tRRD_L for limits,
But i need more time to play with it


----------



## XPEHOPE3

Veii said:


> Can you run both of the old and current bios through SMU Checker


Left is first beta from which I started long ago.
Middle is the one which worked 3800-16-1933, but won't post win RTTPark /2
Right is the current (failed 3800-16-1933, but booted with RTTPark /2)









I see chipset version downgrade, don't see microcode info and don't see any difference between mid and right apart from file name (file contents is binary different).
ZenTimings debug shows PatchLevel: 0A201016 just as on previous BIOS (which is at mid screen)


----------



## byDenoso

Veii said:


> All depends on the PCB if A0 or not A0
> 1.48v is easily fine - depends on RTT_PARK too
> Voltage doesn't do much on it's own
> 
> It's not always 6
> My Rev.E's are tCCD_L 7 on their PCB
> My B-dies where 6, but they can work even as tBURST 2 instead of 4 or 6
> Not everything is on 6
> 
> I dont like your tRAS, but when it runs well, it runs well
> Most of the times, flat timings perform better after all
> But if you're really bored, you can take my path of bruteforcing primaries
> 13-13-13-13 🤭
> With bump on tRRD, tWTR,, and tWR
> Later you can lower them
> 
> Cores dissapear ?
> I've seen on MSi boards cores fully disappear or take a long time at the start to come on
> But that looked like an HWInfo tthing
> 
> Remove files , ,yet not corrupt anything ?
> Can you rephrase ?
> 
> Usually Sophia Script and NT-Lite are decent for such , depends on the request
> Take Ownership reg file helps too if permissions are an issue
> Windows10Manager.7z this windows 10 manager has a lot of useful tools too
> Unsure what the request is





Veii said:


> The GPU also shows variance between 1-5 points. I think it's test by test variance
> In order to verify it functioning, you need to verify it causing issues
> for example tCKE 3 likely won't run - or 13 shouldn't run anywhere between 3733-3800MT/s
> I haven't seen tCKE changes anything around it on Matisse. First time noticed it on 2100 FCLK where any little option off, was causing crashes and reboots (unstable memory)
> But for Matisse, everyone who tells you it doesn't do anything - likely is even right. Vermeer is different, but Matisse depends on the IMC FW & AGESA
> 
> Yes and no (i can't guarantee your ICs will like it on the current preset)
> Voltage doesn't matter, it's the RTT combination with it
> RZQ/1 on RTT_PARK is too strong. It's suited for 1.25-1.42v, maybe 1.46 - but likely beyond 1.42v you get negative scaling
> It's not suited for it
> 
> 1.48+ too 1.51v, should run RTT_NOM /7 as minimum
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> That's probably already the lowest you can go , maaybe tRTP 6 could run Why can't you increase IOD a bit - for 3800MT/s ? Maybe also tRDWR 11, tCWL 14 could run (maaybe if you have a tiny bit of reserves left) But it could need tWR 16 - you have to try I've tested with tRTP 6 and so far so...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> this post finally fits as answer
> Weaken RTT_PARK, use RTT_WR /2 if you manage to get it stable else /3 and decide between
> RTT_WR+CAD_BUS
> tCKE + SETUP TImings
> CKE+RTT_WR
> 
> it's not easy to manage 3 types of powerdowns in sync
> only two work most of the times
> Either you go down to X-20-20-20 CAD_BUS and use setup times with it
> or you run the typical X-20-24-20 or X-20-20-24 (for Matisse) and you common RTTs
> Voltage alone does nothing, all depends on the strength of ClkDrvStr (CAD_BUS) and strength of RTT's , till it's really dangerous and a bad idea
> I daily 1.64v currently barely exceeding 44c at worst ~ in a hot 32-34c day . Idle/Gaming it's mostly 6-7c above ambient
> 
> Voltage does barely anyhting to heat
> Google Ohm's law , how amperage changes


This is what i'm using now, no errors since then, should i tweak something?


----------



## Veii

byDenoso said:


> This is what i'm using now, no errors since then, should i tweak something?


Everything 
i found 6 issues 

Start with fixing tRFC 








You "waste" latency on tRP, while running tRCDWR low for "no reason" , nearly no reason ~ can't see a mathematical reason for it
You run very low tWTR and tRRD_ , yet your primaries are very high ~ this shows that tRP is delaying everything and make it look stable
tFAW is 9* ? 
tRP should be on your preset 15, if you up tRCDWR to 9 
tRC should be 49 on your example, or 45 if you fix tRP~ but i doubt it would run it unless you redo a lot of thigs. Another possible math is 8(9)+14+10+4 = 36 , but i don't think tRC 36 would "just run"

These are so far 6 issues
There are couple more but the most critical ones:
Re-do your primaries, up tRRD & tWTR till tRCDRD 20 runs
Don't just drop tRCDWR bellow half of tRCDRD, it won't "just work"
Be sure both tRCD's add together to an even value, so you can divide it well ~ the result of it = tRP
tRAS is fishy, usually it's tRCDavg *2, or tRCDmax *2 . Doing math together with tCL kind of works, but is not recommendable. In reality the value is tRCDavg+tBURST as lowest possible 

Nevertheless how i shuffle it around, i can't get it make sense
Just redo ~everything~


----------



## Veii

XPEHOPE3 said:


> I see chipset version downgrade, don't see microcode info and don't see any difference between mid and right apart from file name (file contents is binary different).
> ZenTimings debug shows PatchLevel: 0A201016 just as on previous BIOS (which is at mid screen)


Ah sorry i am stupid
ZenTimings would show it, aida64 would show it and UBU updater shows it ~ but UBU needs Python support with "add as PATH variable" , on the installer





[Tool Guide+News] "UEFI BIOS Updater" (UBU)


@ all users, who are searching for an easy way to get any OROM or EFI module of their AMI UEFI BIOS updated: It was our member eierfrucht, who gave me in Se




www.win-raid.com




Hmm maybe i can reupload mine, let me try some host which won't get DMCA'd from AMI








MyAirBridge.com | Send or share big files up to 20 GiB for free


We will transfer your files easily, safely and rapidly from one place to another. You can send them directly to an email address or share files using a unique link.




mab.to




You still will need to install couple of things by python (pip3) but i will tell you everything
Once you open the .bat and it loads a bios, it will make a temporary bios.rom file & always re'load it on start
If you want to check multiple things, you'd need to erase the bios.rom from the folder


----------



## byDenoso

Veii said:


> Everything
> i found 6 issues
> 
> Start with fixing tRFC
> 
> 
> 
> 
> 
> 
> 
> 
> You "waste" latency on tRP, while running tRCDWR low for "no reason" , nearly no reason ~ can't see a mathematical reason for it
> You run very low tWTR and tRRD_ , yet your primaries are very high ~ this shows that tRP is delaying everything and make it look stable
> tFAW is 9* ?
> tRP should be on your preset 15, if you up tRCDWR to 9
> tRC should be 49 on your example, or 45 if you fix tRP~ but i doubt it would run it unless you redo a lot of thigs. Another possible math is 8(9)+14+10+4 = 36 , but i don't think tRC 36 would "just run"
> 
> These are so far 6 issues
> There are couple more but the most critical ones:
> Re-do your primaries, up tRRD & tWTR till tRCDRD 20 runs
> Don't just drop tRCDWR bellow half of tRCDRD, it won't "just work"
> Be sure both tRCD's add together to an even value, so you can divide it well ~ the result of it = tRP
> tRAS is fishy, usually it's tRCDavg *2, or tRCDmax *2 . Doing math together with tCL kind of works, but is not recommendable. In reality the value is tRCDavg+tBURST as lowest possible
> 
> Nevertheless how i shuffle it around, i can't get it make sense
> Just redo ~everything~


Got it!!
So i'll have to increase tRP because it wont boot lower than that, even if you loosening the other timings.

I know then Hynix RCD don't scale with voltage, so how can i lower primaries?


----------



## Nighthog

Veii said:


> tFAW for me was acting bizarre till i discovered this Ref and SurUrgRef setting on the ASUS board
> tCCD_L the bios uses for XMP "translation"
> I am not sure by how much or after when it changes , was always curious on this value, back with Matisse
> But Bios SPD-Z or Memory-Z (names differ by brand)
> Do display it
> 
> Funnily 1-2 lower than the math on tFAW remained rock stable, but correct tFAW math then seemed to time out and break
> That's usually how you notice something is off, soo the advice to test it that way if stability "out of nowhere changes drastically"
> 
> I think you can use them 2 ways (need bit more research with them)
> For 1x tFAW mode you want to set SubUrgent to the typical 4* value how JEDEC defines it.
> Urgent is when it has to close the ACTIVE window , and refuses to accept any commands. This allows for BURST refreshes and so 1x tFAW to function (if you enforce it on 1)
> 
> Or the other way around,
> Urgent can be used for fixing when an "urgent refresh" has to happen. This is then tCCD_L optimally or whatever you selected for tFAW
> 
> 
> 
> 
> 
> 
> 
> 
> And SubUrg can be then used as how JEDEC defines it for 4*
> Oh i repeat myself
> But this is how i utilized it (picture = stock currently)
> 
> You can enforce Urgent to be 1 and subUrg to keep the 4x limit up, or you can swap them and enforce Urgent to be up to X times 4 or 6
> And suburgent to allow burst refreshes when they are needed inside the UrgLimit
> 
> Haven't decided what makes more sense now, but 1x tFAW trick to work, it needs a change here
> And generally noticed that tFAW broke because of these introduced "stock" changes.
> Afterwards started to use tCCD_L as math instead of tBL and Rev.E remained stable on everything i trow at them
> * i still have random issues with tRC - can't get it lower for some reason, yet tRAS goes down to 2x tRCDmax without any additions to it. Something is off on my side still
> 
> Rev.E breaks stability for me around 1-1:30h for what appears to be stable at first
> Error 7 would mostly point to CAD_BUS, and Error 4 remain PCB crashes
> It's complicated
> 
> Nice 288ns
> I can only point you to experiment with RTT's
> And maybe give this tRRD_L = tRTP wording a try ~ which i gathered from the Intel thread (never used it to judge how much sense it makes)
> But error #4 needs to be resolved first
> 
> Reading my post, it's complicated
> Urgent keep as the multiplier you use for tRRD_S to tFAW , probably as tCCD_L for stability
> and SubUrgent you can fix it being JEDEC based, as 4x tRRD_S = tFAW ~ to allow BURST Refreshes as a limit of 4*
> 
> There is likely a better more accurate method utilizing tRRD_L for limits,
> But i need more time to play with it


I tried the Urgent & SubUrgent settings but nothing really helped with running it @ tRRDS-tRRDL 4-4 tFAW 16
6-6-6 is more stable.... Other than using something like 4-4 32.
Noted tFAW 16 was more unstable now with 1.2.0.3b than with 1.2.0.3a even without touching Urgent/SubUrgent setting.


----------



## Veii

byDenoso said:


> I know then Hynix RCD don't scale with voltage, so how can i lower primaries?


No brand's tRCD scales with voltage, or rather every brand does
But you have to increase tRRD, tWTR, tWR, tRDWR - to allow it
It's bruteforcing, but currently the set looks rather broken than anything


Nighthog said:


> Noted tFAW 16 was more unstable now


Can you rephrase,please ?
I know only unstable and stable
More errors in TM5 doesn't mean worse - depends on the error type


----------



## byDenoso

Veii said:


> Everything
> i found 6 issues
> 
> Start with fixing tRFC
> 
> 
> 
> 
> 
> 
> 
> 
> You "waste" latency on tRP, while running tRCDWR low for "no reason" , nearly no reason ~ can't see a mathematical reason for it
> You run very low tWTR and tRRD_ , yet your primaries are very high ~ this shows that tRP is delaying everything and make it look stable
> tFAW is 9* ?
> tRP should be on your preset 15, if you up tRCDWR to 9
> tRC should be 49 on your example, or 45 if you fix tRP~ but i doubt it would run it unless you redo a lot of thigs. Another possible math is 8(9)+14+10+4 = 36 , but i don't think tRC 36 would "just run"
> 
> These are so far 6 issues
> There are couple more but the most critical ones:
> Re-do your primaries, up tRRD & tWTR till tRCDRD 20 runs
> Don't just drop tRCDWR bellow half of tRCDRD, it won't "just work"
> Be sure both tRCD's add together to an even value, so you can divide it well ~ the result of it = tRP
> tRAS is fishy, usually it's tRCDavg *2, or tRCDmax *2 . Doing math together with tCL kind of works, but is not recommendable. In reality the value is tRCDavg+tBURST as lowest possible
> 
> Nevertheless how i shuffle it around, i can't get it make sense
> Just redo ~everything~


Testing with corrected primaries now, if passes, what should i do next?


----------



## Veii

byDenoso said:


> Testing with corrected primaries now, if passes, what should i do next?


I don't think it will pass, as tWTR_S is low
but i wish you only the best
tRTP should've been the half of tWR
which is (tRTP) a clean divider of tRFCns

Aida64 you can test, and SiSoftware Sandra you can download 
We work blind, based on experience & not based on results
Test it, we need a baseline to work with

Might also consider this post








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Chipselect Interleaving set to disabled inside AMD CBS section under UMC Common Options DRAM Memory Mapping gives me 1ns lower latency at the cost of 2K copy in AIDA64. Thoughts on what is better for fps in games? I'm tending to latency.




www.overclock.net





EDIT:
Also use 1usmus_v3 to test memory stability @byDenoso
Anta's config is not bad, but nobody knows what the errors mean . 








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com




Soo pretty much useless as helping utility. For memtests you could just use GSAT
1usmus_v3 to find errors and know what to do with it


https://www.overclock.net/attachments/tm5-zip.341254/



Might want to open the cfg (remove read only)
Change language to 1, change cycles to 25, save and put read-only back on it
TM5 always run with admin permissions


----------



## Nighthog

Veii said:


> No brand's tRCD scales with voltage, or rather every brand does
> But you have to increase tRRD, tWTR, tWR, tRDWR - to allow it
> It's bruteforcing, but currently the set looks rather broken than anything
> 
> Can you rephrase,please ?
> I know only unstable and stable
> More errors in TM5 doesn't mean worse - depends on the error type


Basically spewing errors like mad after the first cycle, various errors, like the memory were overheating but actually isn't looking at the temperature reading they provide.
Before I could do a few cycles before a first error now it's in the second cycle, error 7, 3, 2, 4, 0, 5, 13 etc. 
Doesn't like tFAW 16 at all. Though tFAW 32 is mostly fine, similar to 6-6-6 I tried earlier. (~1 error per hour, mostly error 0, 7 or a 4 on occasion)
Might have selected bat Urgent/SubUrgent values but I tested a few and saw no better results from AUTO @ 16 tFAW. Didn't have that much trouble with the F34a 1.2.0.3a BIOS but it wasn't flawless either and would get worse the longer it ran, it's just more fast now to show the issue.


----------



## byDenoso

Veii said:


> I don't think it will pass, as tWTR_S is low
> but i wish you only the best
> tRTP should've been the half of tWR
> which is (tRTP) a clean divider of tRFCns
> 
> Aida64 you can test, and SiSoftware Sandra you can download
> We work blind, based on experience & not based on results
> Test it, we need a baseline to work with
> 
> Might also consider this post
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Chipselect Interleaving set to disabled inside AMD CBS section under UMC Common Options DRAM Memory Mapping gives me 1ns lower latency at the cost of 2K copy in AIDA64. Thoughts on what is better for fps in games? I'm tending to latency.
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> EDIT:
> Also use 1usmus_v3 to test memory stability @byDenoso
> Anta's config is not bad, but nobody knows what the errors mean .
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> Soo pretty much useless as helping utility. For memtests you could just use GSAT
> 1usmus_v3 to find errors and know what to do with it
> 
> 
> https://www.overclock.net/attachments/tm5-zip.341254/
> 
> 
> 
> Might want to open the cfg (remove read only)
> Change language to 1, change cycles to 25, save and put read-only back on it
> TM5 always run with admin permissions


So should i increase TWR to 12 to mantain tRTP on 6
Or adjust tRFC to it? (450 on tRFC1)?
I'll test the 1usmus profile, then i'll post here the results later.


----------



## Veii

byDenoso said:


> So should i increase TWR to 12 to mantain tRTP on 6
> Or adjust tRFC to it? (450 on tRFC1)?
> I'll test the 1usmus profile, then i'll post here the results later.











These are the values which 100% work & won't be suspended ~ for your preset (100% nearly always, except when the PCB or IC doesn't allow it for some architectural reason)
You maybe have read that tRFC can be postponed up till 9 times (8) inside tREFI range
tREFI on AMD tho is generated from tRFC
tMAW , tMAC, tMRD behavior and generation depends on correct tRFC 2 and tRFC4 values
Correctness of tRFC depends on tRFC2 value ~ even when they are not directly used

It's generally a good practice to get them perfect, because boards are stupid and the whole Rabbit Hole with MCLK to MT/s conversion introduces Rounding issues, which stack
You don't want to stack more and more rounding issues ~ soo this is important to follow
You don't "have to" follow tRFC mini, it's my own proof of concept and still is not perfect
But the ns value calculation (tRFC 2 and 4) are perfect (16 dimms have different values)
Soo i can't recommend it enough as assisting tool.

It makes no sense to fix tRFC to any world clock value (120ns, 200ns, 300ns) because memory moves within 11-18 decimal values. Accuracy there is key ~ soo everything works as integers only and virtual placeholder values
Autocorrection is imminent/it's not preventable  But you should at least try to assist it a bit. Boards are stupid enough already and not IC or PCB aware. They only can use tCCD_L to convert Intel XMP to AMD's Memory Profile


byDenoso said:


> So should i increase TWR to 12 to mantain tRTP on 6


Inside your selected 440 tRFC Values (5,8,10,11,16,20,22) work
Tho all of these show slight rounding issues, pretty much no value works out for it .
Probably because 3733,3333333333336MT/s is a rounding issue on it's own  
I can't get "clean" values out of it - but tRFC mini should be fine with it's predictions. I tried to skip using any world clock values , soo math should be clean 
Try to use what it suggests


----------



## Takla

Veii said:


> Don't just drop tRCDWR bellow half of tRCDRD, it won't "*just work*"


Why you gotta do me dirty like that.
Most timings are bottlenecked by another, so why not drop it as low as possible as long as it is stable?
Plus, you did the same?


----------



## Veii

Takla said:


> Why you gotta do me dirty like that.
> Most timings are bottlenecked by another, so why not drop it as low as possible as long as it is stable?
> Plus, you did the same?


"it won't just work"
Meaning it will need a lot of shuffling around to make it work. Same as 1x tFAW with tRAS+1 = tRC "won't just work"
I use tRC as tRCDWR+tCWL+tWR+tBURST or tCCD_L
8+12+22 = 44 + something
usually 48 should work for me, if i go by tBURST or 51 if i go by tCCD_L

Guess who has issues dropping tRC lower 🤭
Soo the only reason i use it, because tCL 13, tRP 13 work for me ~ soo i use it only as tRCDavg lowerer
Rev.E is special on their own, there is no way how i can drop tRCD further (yet)

But yes, it makes issues ~ and i do have plenty of them 
if i ever get tRC 48 to work i'll let you know ~ then "it works, but also doesn't _just work_ without a lot of effort invesed"
Down to half of tRCD works, but lower makes issues ~ and i have plenty of them
It's stable and all, but it's no where near "fine"


Veii said:


> Guess who has issues dropping tRC lower 🤭
> Soo the only reason i use it, because tCL 13, tRP 13 work for me ~ soo i use it only as tRCDavg lowerer


If i ever get to lower tRAS to 30 or 34 how it has to be, then i can say "it was a positive change"
So far i just borrow it for something else ~ but it's really not recommendable ^^'

One of the reasons why i procastinate it fixing it atm. It works and is stable, but Rev.E's are annoying to work with (for me) ~ soo i really don't want to touch it yet.
But i should fix my tRC someday


Takla said:


> so why not drop it as low as possible as long as it is stable?


Because unless you can proof it actually increases performance - lower is not always better & will be autocorrected "at worst". Or throttles the ability to lower primaries "at best"


----------



## Takla

Veii said:


> Because unless you can proof it actually increases performance - lower is not always better & will be autocorrected "at worst". Or throttles the ability to lower primaries "at best"


I agree. A lot of my timings do nothing for performance even though they are set really low (except for tRCDWR which gives me ~500 more read at 8 then at 16 or 20, thus, it "just works").

Like I said, there are always some timings that are bottlenecked by another. But for me, everything is stable and does not degrade performance.
Having timings set as low as they can still boot, and stable, is more a psychological thing for me.

Good old brute forcing works just fine here. There simply isn't some magical equation that lets you easily find the most optimal timing (I wish there were).


----------



## XPEHOPE3

XPEHOPE3 said:


> Be it for new BIOS or for @Veii RAM training suggestions, I can now boot with RTTPark RZQ/2 for the first time ever  (previously it wouldn't post)
> I think that's the right lead (in comparison to 'timings' lead). Decided to test it and see where it fails.


Yep, it was the right choice, as TM5 is now stable after I went for RTTPark from /1 to /2:









Veii said:


> You still will need to install couple of things by python (pip3) but i will tell you everything
> Once you open the .bat and it loads a bios, it will make a temporary bios.rom file & always re'load it on start
> If you want to check multiple things, you'd need to erase the bios.rom from the folder


I don't see what for is it needed yet  Can you elaborate? I thought you only needed microcode number, and I reported it from ZenTimings.


----------



## Veii

XPEHOPE3 said:


> Yep, it was the right choice, as TM5 is now stable after I went for RTTPark from /1 to /2:
> View attachment 2516264
> 
> 
> I don't see what for is it needed yet  Can you elaborate? I thought you only needed microcode number, and I reported it from ZenTimings.


În order to read microcode numbers out, these tools need to have specific libraries.
Unless you want to flash every bios again and check with Zentimings - UBU method is easier 


XPEHOPE3 said:


> Yep, it was the right choice, as TM5 is now stable after I went for RTTPark from /1 to /2:


Soo you're mentioning that "the better memory training" is your resolve ?
Hmm, it should help to post with the timings, but don't really give a superior advantage upon them
Unless memory training was consistently broken ~ but even such would only show posting issues & not "better memory stability"

Or do you maybe mean the weakening of RTT ?


----------



## Mach3.2

Just dropping back in again, I think I did pretty much all that I can to stay below 1.41V VDIMM, my RAM seem to run hot on 1.42V VDIMM.










I can't get tRP to 15 without setting 1.42V VDIMM, and even then TM5 throws an error 13 on the 2nd pass, which according to Veii's notes, points to the memory overheating..

The timings in the ZenTiming screenshot passed 25 passes of [email protected]_v3 and at least 710% of HCI MemTest.

tCL 13 can't seem to train properly too, my PC boots up to default JEDEC speed of 2666MHz whenever I try to set tCL to 13.

Anyway I was also trying to tighten tRAS and tRC using the following guidelines: _tRAS = tRCD_RD + tRTP_ and _tRC = tRP +tRAS_, but I can't POST with anything tighter than tRAS: 30 and tRC: 46. tRAS:30 and tRC: 46 isn't stable too, throw lots of error in TM5 and eventually end in a BSOD.


----------



## Veii

Mach3.2 said:


> _tRAS = tRCD_RD + tRTP_


Where did you read this ?
It's either tCL (which is a bad idea) or only tRCD
tRP is after tRCD, for tRAS
It has no known to me connection with tRCD at all. it comes after not before ~ even when it says "pre" charge

You use such tight tRRD & tWTR and wonder about bad primaries 
This is Rev.B , it has different scaling than Rev.E
Also your powering settings are kind of bad
24-20-20-24 since Matisse upwards
20-20-24-24 as exception
Too high CAD_BUS degrades the signal

SCL is too tight too
tWR is at minimum
There is no wonder at all, that you struggle, everything except primaries is with minimum delay
Yet non of them are worth more than lower primaries 

If this is stable, good job for running 1T GDM off
But tCL 13 won't boot with tCWL 14, and tCWL 12 needs +2 on tRDWR
Rather try such experiments on lower MT/s first. 3600 CL12 is not easy ~ yet 1.42v is nothing
Well it might be something with these RTT's
for Single Rank /5 s strong , /6 and upwards

3800 upwards might also utilize stronger procODT , something near 34.3 level
Generally not well balanced. Your kit is not in fault of refusing to run such settings
Considering the #13 description says "timeout while transferring big data" ~ it can be "a timeout", also considering your secondaries and tertiaries are bursty ~ it really has nobody to wonder why it crashes "mid-transfer"

Rev.E/Rev.B have a thermal sensor, utilize it before you trust my guide blindly
And maybe let it running to collect more errors. Their meaning wastly depends on when they appear and what they come with
A single solo error can mean many things, like just bad timings sync overall (example #15)

EDIT:
I expect you to run 1.52+ for tCL13 


Spoiler: These could be helpful for you






























In order to utilize these RTT's
You need beyond 1.58v as minimum, probably beyond 1.62v 
Yet thermals remain








* picture was taken mid test
With barely any focused airflow
EDIT 2:
Still have a goal to get that tCL 12 example to run @ 3800MT/s , but we'll see
EDIT 3:
Your board would also not be the fault, because the ProArt has weaker Powering and is 4 dimms Daisy-Chain, compared to my main ITX


----------



## XPEHOPE3

Veii said:


> Or do you maybe mean the weakening of RTT ?


This. Although I cba to check TM5 with RTTPark /1 and default training.


Veii said:


> Unless you want to flash every bios again and check with Zentimings


I think I'll just update to every new BIOS without looking at microcode beforehand  I want to stick to latest version possible, if it's stable at moderate OC.


----------



## T[]RK

Got strange monitoring results when play GTA V. I left HWiNFO64 on background and i got similar "spikes" on CPU Die sensor (100+°C). Also, Global Frequency limit go as high as 9,7 GHz, but no Thermal Throttling. Some kind of a bug?








Software runned:
GTA V
CTR 2.1 RC5
MSI Afterburner
RIVA Tuner
HWiNFO64


----------



## Veii

T[]RK said:


> Got strange monitoring results when play GTA V. I left HWiNFO64 on background and i got similar "spikes" on CPU Die sensor (100+°C). Also, Global Frequency limit go as high as 9,7 GHz, but no Thermal Throttling. Some kind of a bug?
> View attachment 2516285
> 
> 
> Software runned:
> GTA V
> CTR 2.1 RC5
> MSI Afterburner
> RIVA Tuner
> HWiNFO64


Just overboost issue, because CTR enforces DF-C States on
But CTR will failsafe trigger, if there is an issue
I think RC06 should be public already Strange it isn't
While Patreon RC06 still has advantages compared to public RC06
Maybe ask him on twitter, if he has any information on making RC06 public, to remind him
I think Yuri just forgot

Even has a version updater, soo likely he just forgot to share it ~ he's too busy


----------



## craxton

Does this mean "error 5" or ? because its not showing that it errored on #5 like it would on error #12....








(EDIT) also would this be the "biggest" issue im getting with ANY c14 flat ? 
again, all 4 sticks are tforce dark pro 3200c14 just one bought at amazon a few months prior,
the other newegg and few months later, the (worse looking is neweggs) 
manufacturing dates are, week 43 2020 (october 19-23 2020) for the "better set)
and the second set week 12 2020 (march 16-20 2020) 
surely it being the second set was made before the other having "looser" timings, wouldn make a difference?
and that TEAM just figured hey, we can tighten these up some more???


----------



## byDenoso

@Veii i changed some secondaries because it has nos passed with the earlier settings, testing now...no errors.

What other tweaks should i do?


----------



## Veii

craxton said:


> Does this mean "error 5" or ? because its not showing that it errored on #5 like it would on error #12....
> View attachment 2516288


Hm ?
#5 is red marked and windows doesn't support russian font
But the error is #5
In this case very likely too high tWRRD


----------



## Veii

byDenoso said:


> @Veii i changed some secondaries because it has nos passed with the earlier settings, testing now...no errors.


I can not see any proof of such
How long did you test ?
And where is the Aida64 cache-performance screenshot, for a baseline ?


----------



## Mach3.2

Veii said:


> Where did you read this ?
> It's either tCL (which is a bad idea) or only tRCD
> tRP is after tRCD, for tRAS
> It has no known to me connection with tRCD at all. it comes after not before ~ even when it says "pre" charge


It's my first time fiddling around with RAM timings and this guide I found on Github seem somewhat legit weeks ago so I just went with it.


Spoiler: Screenshot


















Veii said:


> You use such tight tRRD & tWTR and wonder about bad primaries
> This is Rev.B , it has different scaling than Rev.E
> Also your powering settings are kind of bad
> 24-20-20-24 since Matisse upwards
> 20-20-24-24 as exception
> Too high CAD_BUS degrades the signal
> 
> SCL is too tight too
> tWR is at minimum
> There is no wonder at all, that you struggle, everything except primaries is with minimum delay
> Yet non of them are worth more than lower primaries
> 
> If this is stable, good job for running 1T GDM off
> But tCL 13 won't boot with tCWL 14, and tCWL 12 needs +2 on tRDWR
> Rather try such experiments on lower MT/s first. 3600 CL12 is not easy ~ yet 1.42v is nothing
> Well it might be something with these RTT's
> *for Single Rank /5 s strong , /6 and upwards*


Just to clarify, you meant setting *RttPark* to RZQ/6 or higher?

I suppose I will leave RttNom and RttWr to disabled and off for now? I don't quite understand what those knobs control, so I left those power settings on auto while trying to tighten the timings.

Another question that I have is, does tRP scale with vDIMM?

When I was trying to tighten tRP from 16 to 15, going from 1.41V to 1.42V vDIMM, the amount of errors in TM5 was cut down significantly to just a single error 13 on the 2nd pass. I stopped the test right after getting an error 13 and loosen tRP back to 16 so I had no idea whether it will continue to throw more errors on subsequent passes.

I think I'll focus on trying to tighten tRP to 15 or 14 before I move on to tightening tCL to below 14.

Just for completeness sake, these are the timings I was running while attempting to tighten tRP to 15.


Spoiler: Screenshot

















Veii said:


> 3800 upwards might also utilize stronger procODT , something near 34.3 level
> Generally not well balanced. Your kit is not in fault of refusing to run such settings
> Considering the #13 description says "timeout while transferring big data" ~ it can be "a timeout", also considering your secondaries and tertiaries are bursty ~ it really has nobody to wonder why it crashes "mid-transfer"


My chip had a FCLK hole at 1900MHz, and is pretty unstable at 1833MHz and 1867MHz. Could be the bad power settings too, so I'll give those 2 FLCK another try with your power setting suggestions.



Veii said:


> Rev.E/Rev.B have a thermal sensor, utilize it before you trust my guide blindly
> And maybe let it running to collect more errors. Their meaning wastly depends on when they appear and what they come with
> A single solo error can mean many things, like just bad timings sync overall (example #15)


Unfortunately my kit doesn't come with a temperature sensor, and I don't have a thermo probe lying around that I can take advantage of. 



Veii said:


> EDIT:
> I expect you to run 1.52+ for tCL13
> 
> 
> Spoiler: These could be helpful for you
> 
> 
> 
> 
> View attachment 2516271
> 
> View attachment 2516272
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> In order to utilize these RTT's
> You need beyond 1.58v as minimum, probably beyond 1.62v
> Yet thermals remain
> View attachment 2516273
> 
> * picture was taken mid test
> With barely any focused airflow
> EDIT2:
> Still have a goal to get that tCL 12 example to run @ 3800MT/s , but we'll see
> EDIT 3:
> Your board would also not be the fault, because the ProArt has weaker Powering and is 4 dimms Daisy-Chain, compared to my main ITX


Thanks for those sets of timings, I'll take a look and see what I can do with those.


----------



## craxton

Veii said:


> Hm ?
> #5 is red marked and windows doesn't support russian font
> But the error is #5
> In this case very likely too high tWRRD


so i should go +1 4+1=5? or -1 to make it 4-1=3 higher doesnt always mean +1 ?

is it 1 or 0 in the config file for english? (my math was off somehow, so i edited)

(EDIT)


Spoiler



am able to run c16 t2 at 1.37v (bios) without issues?
but can NOT get c14 with true proper timings to run stable???
noticed i was having boot issues as well, which happened while using the 5600x while restarting.
would have to hit restart again to get it to boot, changing from 40-20-24-24 to 40-20-20-20 
and 6-3-3- to 6-2-3 seems to have solved this issue. still cant wrap why c14-14 1900/3800 isnt doable
without adding a fan as closest ive gotten was 1.53 in bios would state tm5 overheating issues.

so therefor looking to sell the 5600x to buy some ram  the spoiler about the CPU wasnt a joke...


----------



## Veii

craxton said:


> so i should go +1 4+1=5? or -1 to make it 4-1=3 higher doesnt always mean +1 ?


tWRRD = equal or lower than tRCDavg. usually focused on tRCDWR
SCL * X = equal or lower than tRCDWR
6 * 2 = 12 = lower than 14
4 * 3 = 12 = lower than 14


Mach3.2 said:


> Just for completeness sake, these are the timings I was running while attempting to tighten tRP to 15.


tRP needs to cover tRCD, else not enough charge will be left for it. Unless you overvolt
soo 17 on this example


Mach3.2 said:


> It's my first time fiddling around with RAM timings and this guide I found on Github seem somewhat legit weeks ago so I just went with it.


Aah you wrote tRTP right ?
I didn't just read tRP ?
Then i'm sorry, i read tRP which has no connection 
If this is correct, then it makes things even easier ~ but memory is not "one way". Not "one guide" fits
I'll test it


Mach3.2 said:


> Just to clarify, you meant setting *RttPark* to RZQ/6 or higher?


Yes


----------



## domdtxdissar

domdtxdissar said:


> Here we go
> 
> 
> 5950x @ 4700/4600 static OC, SMT enabled
> 4x8GB memory sticks
> Hwinfo open for all runs
> consecutive runs
> Flat CL 14-14-14-14 timings
> 
> View attachment 2513871
> 
> T1 setup-time
> *19723.4 H/S over 15min run*
> upto 627 H/S per core
> 
> View attachment 2513872
> 
> T1 GDM
> *19151 H/S over 15min run*
> upto 606 H/S per core
> 
> View attachment 2513873
> 
> T2
> *19413 H/S over 15min run*
> upto 616 H/S per core
> 
> ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> 
> 19413 / 19151 = T2 is ~1.3% faster than T1 GDM in this benchmark
> 19723 / 19413 = T1 setup-time is ~1.6% faster than T2 in this benchmark
> 19723 / 19151 = T1 setup-time is ~2.9% faster than T1 GDM in this benchmark
> 
> No time to break down the numbers further, going out
> 
> But it seems like CPU mhz is king in pretty much every benchmark, *dont waste to much of your power budget on SOC if your running PBO CO *as the pure core clocks matters the most in the end...


So i decided to also test this in windows11... Pretty much same settings as above.

5950x @ 4700/4600 static OC, SMT enabled
4x8GB memory sticks








1800:3600 T1 setup-time + CL14-14-14-14
*19107.4 H/S over 15min run*
upto 605 H/S per core








1900:3800 T1 setup-time + CL14-14-14-14 and the tweaks i got suggested a few pages back (tRRDL=5, tWR=10 and tRTP=5)
*19769 H/S over 15min run*
upto 625 H/S per core








1900:3800 T1 setup-time + CL14-14-14-14
*19855.7 H/S over 15min run*
upto 632 H/S per core

A few thoughts on the runs above:

Scaling between 1800:3600 and 1900:3800 seems pretty good. Theoretical max scaling should be 5.5%. (1900/1800)
Iam seeing upwards to ~4% improved real-performance (19769/19107) with the only change being fclk 1800 vs 1900.


tRRDL=5, tWR=10 and tRTP=5 setup performed alittle worse then my regular "flat cl 14" setup

For fun i also tried a setup with tighter timings then the flat cl14-14-14-14 baseline.. To my big surprise it performed even better 
In theory (math) it should not perform better, but i cant argue with the numbers im seeing:








1900:3800 T1 setup-time + CL14-8-14-12-24-36
*20038.6 H/S over 15min run*
upto 638 H/S per core

*Can any of you guys make heads or tails of this ? *
Seems like i found me some new daily 24/7 settings by just playing around.


----------



## hazium233

Mach3.2 said:


> _tRAS = tRCD_RD + tRTP_


This is minimum logical, as otherwise tRTP expiration will govern when precharge can be issued.

tRAS covers activate, sense array, and restore array. tRCD is time for activate and sense. + X for the time to restore depends on the characteristics of the array and the set voltage.


----------



## hazium233

I picked up a set of F4-3466C16D-32GTZ on ebay and have only messed around with them a little bit. They were from 2016, so I figured they pretty much had to be B-die (and they are) just based on the fact there wasn't much else in 8Gb IC that could do that back then. The XMP is not great:










First thing I tried was just basically Stilt's "safe" 3200 14 flat profile with 256 tRFC which ran with 1.35. That was nice.

Having trouble getting tRCDRD 16t at 3800 with them though. tRCDRD 17t worked easily enough, and 16t seems like it works at 3733. There are still a couple things I need to try, but I wonder if that is really the limit for them. I know they aren't as well binned as my 3200C14 or 3600C15 SR sticks.


----------



## craxton

hazium233 said:


> I picked up a set of F4-3466C16D-32GTZ on ebay and have only messed around with them a little bit. They were from 2016, so I figured they pretty much had to be B-die (and they are) just based on the fact there wasn't much else in 8Gb IC that could do that back then. The XMP is not great:
> 
> View attachment 2516298
> 
> 
> First thing I tried was just basically Stilt's "safe" 3200 14 flat profile with 256 tRFC which ran with 1.35. That was nice.
> 
> Having trouble getting tRCDRD 16t at 3800 with them though. tRCDRD 17t worked easily enough, and 16t seems like it works at 3733. There are still a couple things I need to try, but I wonder if that is really the limit for them. I know they aren't as well binned as my 3200C14 or 3600C15 SR sticks.


(find) the 4000/2000 c16 profile i have, and try those values to a T (adding NO drive strength/set up timings tho.)
the 4000mhz c16 flat profile i had worked fine on 3800/1900 for this 5800x with 3-3-15 @2t GDM OFF


----------



## craxton

Spoiler: Not a joke...



If anyone's interest Ina 5600x, with an IMC 
that will do WHATEVER (upto 4066 is as 
far as my ram would boot which was at 
1.6v past that I wouldn't try) whea 19s 
free, but with a not-so-good core 
overclocking capability hit me up Ina pm. 

(Yes, I was wasteful with the MX4 and got a nidge on a pin, will clean it) no bent pins or missing. 

Was dropped at one point, but I think that only knocked the WHEA spider webs out. (minus 18s your on your own with CO) less what I had will work on your board too. 




































(In case you wanna verify my finger print)


----------



## byDenoso

Veii said:


> I can not see any proof of such
> How long did you test ?
> And where is the Aida64 cache-performance screenshot, for a baseline ?






















Sry be late, i had to change CL 15 to CL 16 or it would just error all out.
What's the next step?

Some SMU tweaks?


----------



## Kurt Krampmeier

Hello!

i was asking my question several days ago but while the (my first) posting was awaiting approval, it failed any attention.

the Setup is in the quote. 

i am currently set as shown in screenshot. 
the setup is hitting a wall at 3667 (which is not stable at the time of writing)
i have tried voltage- and rtt combinations up to commonly considered dangerous settings.
voltages shown in zentimings are all back to bios auto. vdimm is 1.48v. i have tried them up and down to no success.
there is no boot above 3667. 










Kurt Krampmeier said:


> Hello all!
> 
> i already asked my Question on german forums but i got no helpful advice yet.
> i know that with the combination of B450 + 4x B-Die aimed at overclocking, this board may be hindering.
> but the fun in overclocking has always been to me, getting my results with reasonable budget.
> so i got myself this used b450 and 4 sticks of fairly old Gskill 2nd hand and put it
> together with my 5900x i got some time ago at the amd online store, when originally aiming at a 6800
> the trial and error took some time but i made it to this
> 
> View attachment 2513975
> 
> 
> with reasonable stability. Memory is at 1.58v and has 80mm fan above it.
> vddg_ccd and iod are reported same voltage but set 1.02 and 1.06 in bios.
> the board would not boot with BIOS default ODT(60) any higher than 3400mhz. BIOS default RTT was 7/2/1, what worked up to 3600.
> 
> there was no boot above 3666 with any settings - and i tried timings, voltages, rtt combinations, ODT
> (only 43.6 gets to 3666- lower only to 3600 - above 48 no luck) and several cad resistances
> from advice on forums, but that made it rather worse.
> while reading forums i came across this thread, where the knowledge looks sound.
> so does anyone know the trick with getting the B450 to 3733 or 3800mt with 4 Sticks of ram?
> i know i could well throw money at the problem and change the board, but then, that's easy.
> 
> Thanks in advance for any suggestions.
> 
> AMD Ryzen 9 5900X
> Asus ROG STRIX B450-F GAMING II Bios 4301
> Frequency 1832.9 MHz (DDR4-3666) - Ratio 3:55
> Slot #1 Module G.Skill 8192 MB (DDR4-2137) - XMP 2.0 - P/N: F4-3200C14-8GVK
> Slot #2 Module G.Skill 8192 MB (DDR4-2400) - XMP 2.0 - P/N: F4-3200C14-8GFX
> Slot #3 Module G.Skill 8192 MB (DDR4-2137) - XMP 2.0 - P/N: F4-3200C14-8GVK
> Slot #4 Module G.Skill 8192 MB (DDR4-2400) - XMP 2.0 - P/N: F4-3200C14-8GFX


----------



## Akex

Kurt Krampmeier said:


> Hello!
> 
> i was asking my question several days ago but while the (my first) posting was awaiting approval, it failed any attention.
> 
> the Setup is in the quote.
> 
> i am currently set as shown in screenshot.
> the setup is hitting a wall at 3667 (which is not stable at the time of writing)
> i have tried voltage- and rtt combinations up to commonly considered dangerous settings.
> voltages shown in zentimings are all back to bios auto. vdimm is 1.48v. i have tried them up and down to no success.
> there is no boot above 3667.
> View attachment 2516329


Hi, I don't know if I will be able to help you, because all the combos behave differently, however, like you, I struggled at the beginning to pass the 3533+ milestone in my case, and I found the solution in RTT / CAD and especially ClkdrvStr which allowed me to be stable GDM OFF 2T. I am on 1.65 vdiim, the temperature of my RAM in burn over 24 hours does not exceed 48 °. Maybe you can try my setup? Leave aside the timings of course.


----------



## T[]RK

Veii said:


> Just overboost issue, because CTR enforces DF-C States on


Even when DF-Cstate is on?



Veii said:


> Maybe ask him on twitter, if he has any information on making RC06 public, to remind him
> I think Yuri just forgot. Even has a version updater, soo likely he just forgot to share it ~ he's too busy


I think it's better just to wait for new programm from him (Hydra).


----------



## Kurt Krampmeier

Akex said:


> Hi, I don't know if I will be able to help you, because all the combos behave differently, however, like you, I struggled at the beginning to pass the 3533+ milestone in my case, and I found the solution in RTT / CAD and especially ClkdrvStr which allowed me to be stable GDM OFF 2T. I am on 1.65 vdiim, the temperature of my RAM in burn over 24 hours does not exceed 48 °. Maybe you can try my setup? Leave aside the timings of course.


thank you for sharing. i have not been over 1.60 vdimm. will try.


----------



## Nighthog

byDenoso said:


> Sry be late, i had to change CL 15 to CL 16 or it would just error all out.
> What's the next step?
> 
> Some SMU tweaks?


Disable TSME for better latency.


----------



## XPEHOPE3

Kurt Krampmeier said:


> the setup is hitting a wall at 3667 (*which is not stable at the time of writing*)
> i have tried voltage- and rtt combinations up to commonly considered dangerous settings.
> voltages shown in zentimings are all back to bios auto. vdimm is 1.48v. i have tried them up and down to no success.
> *there is no boot above 3667*.
> View attachment 2516329





Kurt Krampmeier said:


> Slot #1 Module G.Skill 8192 MB (*DDR4-2137*) - XMP 2.0 - P/N: F4-3200C14-8GVK
> Slot #2 Module G.Skill 8192 MB (*DDR4-2400*) - XMP 2.0 - P/N: F4-3200C14-8GFX
> Slot #3 Module G.Skill 8192 MB (DDR4-2137) - XMP 2.0 - P/N: F4-3200C14-8GVK
> Slot #4 Module G.Skill 8192 MB (DDR4-2400) - XMP 2.0 - P/N: F4-3200C14-8GFX



Only run TestMem5 with admin rights, never without. Also no reason to only run for 1 cycle.
Since you have two *different *pairs of sticks, you may as well post two screenshots of timings from ZenTimings (for example, A1 and B1 even for 4-stick package may be different if something set on Auto in BIOS timings). Also the better sticks should be set up into the worse slots: A2B2 are usually the best slots and should have 2137 sticks in them. Or you can "bin" sticks yourself (just leave only one pair, push its timings/voltages to max performance which is stable, then replace that pair with another and repeat, then from obtained numbers you''ll see what pair of sticks is better "binned" (gets higher results at lower voltages) and that would go into A1B1 slots. Anyway, _two pairs of sticks is harder to get posting/booting/stable at tighter settings, than 4-stick package_.
You seem to have tightened timings before you tried to push for higher clocks. That's generally won't necessarily work. E.g. I can only push for 3867 with SD/DD timings set to 1/4/4/1/6/6 instead of your 1/5/5/1/7/7 (those timings are tighter when higher). Same goes for tRRD_/tFAW 4/6/16 is tighter than might be needed (those 3 are tight when low). With *SCL of 3 I can't post at least above 3800, and you already have it on 2.


----------



## T[]RK

Veii said:


> Of find that BURST Refresh Mode override flag, inside AMD CBS , near UMC or DF options - near the DDR4 menu's


I made pictures for GIGABYTE BIOS. Damn, it's hard to find it.

AMD CBS => UMC Common Options => DDR4 Common Options => DRAM Controller Configuration => DRAM Power Options

































*Disable Burst/Postponed Refresh* = *Enable*
After that you will see two options:
*SubUrgRefLowerBound
UrgRefLimit*

Also, there is *DRAM Maximum Activate Count*. It's set on "Auto", but in Thaiphoon Burner i saw that my memory kit have got "Unlimited MAC". Should i set it, or better to leave it to "Auto"?


----------



## Kurt Krampmeier

XPEHOPE3 said:


> Only run TestMem5 with admin rights, never without. Also no reason to only run for 1 cycle.
> Since you have two *different *pairs of sticks, you may as well post two screenshots of timings from ZenTimings (for example, A1 and B1 even for 4-stick package may be different if something set on Auto in BIOS timings). Also the better sticks should be set up into the worse slots: A2B2 are usually the best slots and should have 2137 sticks in them. Or you can "bin" sticks yourself (just leave only one pair, push its timings/voltages to max performance which is stable, then replace that pair with another and repeat, then from obtained numbers you''ll see what pair of sticks is better "binned" (gets higher results at lower voltages) and that would go into A1B1 slots. Anyway, _two pairs of sticks is harder to get posting/booting/stable at tighter settings, than 4-stick package_.
> You seem to have tightened timings before you tried to push for higher clocks. That's generally won't necessarily work. E.g. I can only push for 3867 with SD/DD timings set to 1/4/4/1/6/6 instead of your 1/5/5/1/7/7 (those timings are tighter when higher). Same goes for tRRD_/tFAW 4/6/16 is tighter than might be needed (those 3 are tight when low). With *SCL of 3 I can't post at least above 3800, and you already have it on 2.


Hello!

the cut 1usmus config runs relevant tests at 500% and generates high temperatures very fast. so it works for me to get a quick impression on stability. shown settings run anta777 extreme also.

those 2 kits are more or less equal. difference is intel v. amd branding. i did quite some reseating and cycling and behavior was identical at given speed and timing. i assume that they are of reasonable quality. i have not seen many 3200c14 running the timings shown at 1.48v 4sticks.

the tight timings are result of settling with 3600/3667 as anything at any speed above did not work. so i began tightening what was able to boot. i could set cl18 trrds/l8/12 tfaw36 tcwl18 scl5 1/4/4/1/6/6 you name it, but not get to boot at 3733 with 1.6v - so its not that i tried something... 

2 sticks will run 4066 c16

i suspect a possible solution in odt, cad or setup timing but it is nearly impossible to find any example of my setup anywhere running more than 3600mhz with 4 sticks. 
knowing that crosshair or other flagship boards run 4 sticks at 3800-4000 does little help with my cheapo b450 gaming2


----------



## XPEHOPE3

Veii said:


> And pattern testing to both


Yes, I did that, just didn't write it here.


XPEHOPE3 said:


> Yep, it was the right choice, as TM5 is now stable after I went for RTTPark from /1 to /2:


This also appeared y-cruncher stable for 10 iterations.



Veii said:


> If they updated DQs, RZQ & procODT behavior again
> You likely need to drop procODT by one value (weaker) and/or drop RTT_PARK by one value weaker


Unfortunately I wasn't able to post reliably to 3867-16-1933-procODT36.9 setup anymore. The only time I succeeded was with MBIST 7 aggressors setting, I booted and tested Aida latency: 58.9+-0.3, while before BIOS update it was 58.2+-0.1 at the same settings (but with RTTPark /1 and without training changes). Reboot was fine but after I tried lowering procODT to 34.3 (no dice, VDDP lowering to 840 also didn't help, or should I just *set RTTPark back to /1 and try to vary only procODT?*) it stopped posting even for 36.9 (for any training method, even for 1.55 VDIMM). 40 procODT also won't post. However all those procODTs would post as soon as I drop from 3867 to 3800 (keeping other settings, incl. FCLK at 1933).
Previous timings:







AGESA 1.2.0.3b timings:







The only difference is tPHYRDL (which I can't set) and RTTPark. On other sets of timings tPHYRDL 28 performed worse than 26.

I feel like I have to redo at least Aida testing for all the previous setups (32-xmp, 36-14, 38-16, 38-15).

Funny how there's no entries with 1.2.0.3b in the Zen RAM Overclocking list


----------



## domdtxdissar

XPEHOPE3 said:


> Yep, it was the right choice, as TM5 is now stable after I went for RTTPark from /1 to /2:
> View attachment 2516264











Intended ?


----------



## XPEHOPE3

domdtxdissar said:


> Intended ?


Yes, per Veii's advice to first setup VDD* voltages and procODT, then check FCLK stability, before pushing corresponding MEMCLK.
Every setup lower than that was already TM5+y-cruncher stable (32-xmp, 36-14, 38-16, 38-15) albeit at another BIOS.


----------



## byDenoso

Nighthog said:


> Disable TSME for better latency.


TSME Off




























I've tested again and it survived with no errors.


----------



## BarrettDotFifty

How do I get tRCDRD down to 14 to be stable for a flat 14-14-14 setup? No matter what I try, random errors would just pop as soon as tRCDRD gets set to 14. VDIMM sits at 1.46V.


----------



## Veii

Kurt Krampmeier said:


> i was asking my question several days ago but while the (my first) posting was awaiting approval, it failed any attention.




















T[]RK said:


> Even when DF-Cstate is on?


DF_C-States are the cause of overboost
Package C6


T[]RK said:


> I think it's better just to wait for new programm from him (Hydra).


The update changes core affinity awareness and load awareness
I think he forgot to push it public. Testting time should've been over already


T[]RK said:


> Also, there is *DRAM Maximum Activate Count*. It's set on "Auto", but in Thaiphoon Burner i saw that my memory kit have got "Unlimited MAC". Should i set it, or better to leave it to "Auto"?


Auto
Unlimited and "disabled" behave nearly identical
You can experiment with them at the very end


XPEHOPE3 said:


> Should I just *set RTTPark back to /1 and try to vary only procODT?*)


If you change CsOdtDrvStr to 30+ like advertised many times for Vermeer - it fixes memory training issues 


BarrettDotFifty said:


> No matter what I try, random errors would just pop as soon as tRCDRD gets set to 14. VDIMM sits at 1.46V


Use:
Ryzen Google Calculator! with B-2 mode on tRFC 2 for dual rank kits
Likely also start with 2T till you are sure primaries are fine
it will need at absolute minimum 1.48v, likely more till the 1.56v range ~ which will overheat with strong RTT_PARK /1

Your SOC is lower than your IOD , lower your IOD or increase your SOC (40mV as minimum distance)
AMD max overclocking voltage thread
Your ProcODT is also too high


XPEHOPE3 said:


> Funny how there's no entries with 1.2.0.3b in the Zen RAM Overclocking list


Barely anyone has it , i still wait


domdtxdissar said:


> View attachment 2516340
> 
> Intended ?
> 
> 
> XPEHOPE3 said:
> 
> 
> 
> Yes, per Veii's advice to first setup VDD* voltages and procODT, then check FCLK stability, before pushing corresponding MEMCLK.
Click to expand...

I've never done this, as it usually doesn't work running fabric higher than MCLK
My advice was to run a weak set 16-16-16 to figure out FCLK range
if it works, why not looks fine ~ but never worked for me


----------



## BarrettDotFifty

Veii said:


> Use:
> Ryzen Google Calculator! with B-2 mode on tRFC 2 for dual rank kits


Thanks. Can you please explain though what the different multipliers mean?

Also for me 2T is very unstable. Like, to the point where the even the BIOS freezes and I almost corrupted my OS. 
Do you think a flat 14-14-14 3600 with GDM off @ 1T setup would require more than 1.48V VDIMM?


----------



## XPEHOPE3

Veii said:


> My advice was to run a weak set 16-16-16 to figure out FCLK range


Not only FCLK, but also procODT/VDD*/VSOC to use with each FCLK in a stable way, and then push memclk to match fclk.
Unless ofc you wan't to retract your previous messages 
Ofc I'm not going to daily 3800-16-1933, it's temporary before pushing memclk.


Veii said:


> If you change CsOdtDrvStr to 30+ like advertised many times for Vermeer - it fixes memory training issues


IIRC it never fixed anything for me on previous BIOS with 1.2.0.2 AGESA. But maybe on 1.2.0.3b it will be different. I remember I need to set CAD_BUS to X-20-30+-20. But what do I set for tCKE (which also interferes with CAD_BUS IIRC)?

Meanwhile it appeared I'm able to boot 3866-16-1933 with RTTPark /1 and higher procODTs (40,43.4,48,53.3), not lower, as you suggested.
Also crucial for Aida latency score is tPHYRDL timing for A and B channels (they differ). For 26/26 I get generally better scores than for 28/26, 26/28, 28/28, 26/34, 34/26, unless there's evident autocorrection. But I'm yet to figure out what those tPHYRDL depend on apart from training session. For the same procODT I can get both 28/26 and 34/26 pair depending on training, which gives either 59.3-59.7 or 60.1-60.3 Aida latency.


----------



## craxton

Akex said:


> Hi, I don't know if I will be able to help you, because all the combos behave differently, however, like you, I struggled at the beginning to pass the 3533+ milestone in my case, and I found the solution in RTT / CAD and especially ClkdrvStr which allowed me to be stable GDM OFF 2T. I am on 1.65 vdiim, the temperature of my RAM in burn over 24 hours does not exceed 48 °. Maybe you can try my setup? Leave aside the timings of course.


whats your latency like with this? (in safe mode in win 10 not windows 11/10.5)
have tried 56-56-56 and 3-3-15 as well as all the others but couldnt run c14-3800 1.53v or less since dimms overheat.
can do 16-16 at 3800 1.38v however no issue.


----------



## craxton

XPEHOPE3 said:


> Only run TestMem5 with admin rights, never without. Also no reason to only run for 1 cycle.
> Since you have two *different *pairs of sticks, you may as well post two screenshots of timings from ZenTimings (for example, A1 and B1 even for 4-stick package may be different if something set on Auto in BIOS timings). Also the better sticks should be set up into the worse slots: A2B2 are usually the best slots and should have 2137 sticks in them. Or you can "bin" sticks yourself (just leave only one pair, push its timings/voltages to max performance which is stable, then replace that pair with another and repeat, then from obtained numbers you''ll see what pair of sticks is better "binned" (gets higher results at lower voltages) and that would go into A1B1 slots. Anyway, _two pairs of sticks is harder to get posting/booting/stable at tighter settings, than 4-stick package_.
> You seem to have tightened timings before you tried to push for higher clocks. That's generally won't necessarily work. E.g. I can only push for 3867 with SD/DD timings set to 1/4/4/1/6/6 instead of your 1/5/5/1/7/7 (those timings are tighter when higher). Same goes for tRRD_/tFAW 4/6/16 is tighter than might be needed (those 3 are tight when low). With *SCL of 3 I can't post at least above 3800, and you already have it on 2.


thank you for this, now i see my MAIN problem...
not different boots, same boot same same same... makes more sense now...
2 stick are 10-tRDWR the other 2 are at 11-tRDWR. 
these sticks are not "different like his" but are different sets in general. 
all four are tforce dark pro 3200-c14 to which different times being made and bought. 
i suspect this might be whats giving me grief getting 14-14 dialed in. 
(did not have this issue on the 5600x)
but it did 2000fclk and higher no issues, this 5800x over 1900 is a flooded nightmare.


----------



## Veii

XPEHOPE3 said:


> Not only FCLK, but also procODT/VDD*/VSOC to use with each FCLK in a stable way, and then push memclk to match fclk.


You have many variables. But that's the way
procODT needs to change by FCLK
IOD & CCD need to change by FCLK
CAD_BUS ClkDrvStr needs to be adjusted "lower" on higher procODT
tCKE needs to be adjusted by MCLK
SETUP times need to be adjusted by MCLK (if used)

and all of this always has to be stable on y-cruncher , show "better" results on Aida64 (no L3 throttle, no write throttle) and still be stable on TM5
Above 5 variables are ones you control and change by FCLK or MCLK change (simultaneously) ~ it is normal
Experience you gather by testing around


XPEHOPE3 said:


> IIRC it never fixed anything for me on previous BIOS with 1.2.0.2 AGESA.


You really shouldn't trust Auto values for anything.


XPEHOPE3 said:


> Also crucial for Aida latency score is tPHYRDL timing for A and B channels (they differ). For 26/26 I get generally better scores than for 28/26, 26/28, 28/28, 26/34, 34/26, unless there's evident autocorrection.


I do think you make yourself too much headache for such. Never looked on them. They differ, but they are predicted only.
If as close to nothing is on Auto, as close to nothing will have variance
No variance, no randomness.
You can't change them, only on MSI boards they give you the option to work and modify them ~ or by running "MSI Latency" mode

If you have that much difference on training, i'd start to fix everything that's on Auto.
Even if the board magically get's things right, you won't understand the magic. Fix everything you can fix except vcore. Then there is no random variance
You fight atm against an invisible enemy, against yourself, against the bios


BarrettDotFifty said:


> Thanks. Can you please explain though what the different multipliers mean?


Multipliers ?
RTT, tRFC ?
Both topics require 6000-10 000 letters or two pages
I don't think i can.
쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네 this A, B, C , D thread has everything about DRAM
Sadly OCN broke the links, soo maybe annoy Enterprise (Moderator) again to fix them ~ they worked , then broke, then worked again and now are again broken


----------



## XPEHOPE3

Veii said:


> I do think you make yourself too much headache for such. Never looked on them. They differ, but they are predicted only.
> If as close to nothing is on Auto, as close to nothing will have variance
> No variance, no randomness.


What do I set to not-Auto? RAM-related settings only? But from ZenTimings I see no difference apart from tPHYRDL anyway.
Other settings? There are too many. And some of them I can't even set to "Enabled" or "Disabled", as they *stick to Auto after reboot*. And to move smth off Auto I need to know default setting, which I don't. Also I've disabled PBO and CO long ago, vcore on auto.

Problem is there will always be variance because memory training seems to involve randomness.


Veii said:


> They differ, but they are predicted only.


Do you mean they are different for you even from training to training? Or only for A and B channels?

I can reproduce nearly always:

Make some setup, which is quite hard to post, to post and boot
Save that profile in BIOS
Run ZenTimings to record everything for *both channels*
Run Aida latency test several times
Change something in BIOS so that it doesn't boot with correct RAM frequency, boot PC, reboot into BIOS
Load saved profile, "Save and exit BIOS", make it boot.
Repeat 3 & 4. Whatever timings, volts, Ohms were on Auto in BIOS, would appear the same in ZenTimings as in 3.
I believe even on your setup there will be variance (between values recorded in 3, 4 and 7) in both tPHYRDL for A/B channels, and in Aida latency.
If not, then you have tight timings (while I don't, again, I think per your maybe misunderstood recommendation to first pursue memclk+fclk, then tighten anything) and hidden timings can only be trained "one way". That is, even if I set all timings to not-Auto, but *relaxed*, I presume hidden timings can still be trained with variation.


----------



## byDenoso

Veii said:


> You have many variables. But that's the way
> procODT needs to change by FCLK
> IOD & CCD need to change by FCLK
> CAD_BUS ClkDrvStr needs to be adjusted "lower" on higher procODT
> tCKE needs to be adjusted by MCLK
> SETUP times need to be adjusted by MCLK (if used)


 How VDDG and VDDP voltages work on Matisse?


----------



## Robostyle

Extreme tweaker vs advanced tabs within crosshair series when OCeing RAM - is there any difference?


----------



## byDenoso

What's the tCKE timing? does it increase latency even with power down off?


----------



## T[]RK

Veii said:


> The update changes core affinity awareness and load awareness
> I think he forgot to push it public. Testting time should've been over already


Here is respond from 1usmus on my HWiNFO64 screenshot:

__ https://twitter.com/i/web/status/1411620683226955779


----------



## Hale59

byDenoso said:


> How VDDG and VDDP voltages work on Matisse?


by @Veii:

Ryzen 3000 valtage stepping:

as long as you keep the 50mV or 75mV stepping up, you can scale up

if you use 50mV stepping
VDDP 900mV
VDDG 950
vSOC either 1000 or 1050 works (50mV or 50*2 mV = 100mV stepping)

Example of 75mV stepping
VDDP 900mV
vDDG 975mV
vSOC 1050mV or 1125mV (75mV or 75*2 mV stepping)

As long as it follows this pattern it won't have issues
Another example:
VDDP 1000
VDDG 1075
VSOC 1150 (for XOC & LN2 preset and maybe 2000FCLK)

or another one:
VDDP 1100
VDDG 1150
vSOC 1200 (for LN2 or 5000MT/s memory)

Although VDDP over 1000mV goes already into absurd not needed territory
Max Consumer "reasonable" would be:
VDDP 1050
vDDG 1100
vSOC 1150 (1.15v as max without causing negative effects for maximum FCLK OC)

I would not suggest to use 75mV stepping if you need to go already over 1.1v VSOC
50mV stepping is how it behaves according to AMDs tuning, 75mV stepping should be used for very bad leaky silicon
Leaky silicon = X series cpus which are rated to boost near 4.7/4.8 while using absurd voltages

EDIT:
One exception that exists with a bit different scaling:
50mV *2
VDDP 900mV
VDDG 1000mV
vSOC 1100mV

same as:
75mV *2
VDDP 900mV
VDDG 1050mV
vSOC 1200mV
both of them still work as exceptions, but it would be a bit stupid
They only make sense if you break them down in:
50mV *2
VDDP 900mV
VDDG IOD 950
VDDG CCD 1000
VSOC 1100mV

75mV *2
VDDP 900mV
VDDG IOD 975
VDDG CCD 1050
vSOC 1200mV


----------



## XPEHOPE3

Robostyle said:


> Extreme tweaker vs advanced tabs within crosshair series when OCeing RAM - is there any difference?


There is. For example, if you load default BIOS settings, load XMP profile, go to Tweaker->RAM timings, set for example only tCL to what's expected by XMP (rest on Auto), but then go to Advanced tab/AMD CBS/UMC common/DDR4 common/DRAM timing/... you can see that there are some default timings already set, even which were not in XMP. For example, I have tWRRD set to 5 there, tRRD_ to 6 and 8.


----------



## byDenoso

I Got a bump in the latency (at the cost of bandwidth) only changing tRC and tCKE setting


----------



## byDenoso

Hale59 said:


> by @Veii:
> 
> Ryzen 3000 valtage stepping:
> 
> as long as you keep the 50mV or 75mV stepping up, you can scale up
> 
> if you use 50mV stepping
> VDDP 900mV
> VDDG 950
> vSOC either 1000 or 1050 works (50mV or 50*2 mV = 100mV stepping)
> 
> Example of 75mV stepping
> VDDP 900mV
> vDDG 975mV
> vSOC 1050mV or 1125mV (75mV or 75*2 mV stepping)
> 
> As long as it follows this pattern it won't have issues
> Another example:
> VDDP 1000
> VDDG 1075
> VSOC 1150 (for XOC & LN2 preset and maybe 2000FCLK)
> 
> or another one:
> VDDP 1100
> VDDG 1150
> vSOC 1200 (for LN2 or 5000MT/s memory)
> 
> Although VDDP over 1000mV goes already into absurd not needed territory
> Max Consumer "reasonable" would be:
> VDDP 1050
> vDDG 1100
> vSOC 1150 (1.15v as max without causing negative effects for maximum FCLK OC)
> 
> I would not suggest to use 75mV stepping if you need to go already over 1.1v VSOC
> 50mV stepping is how it behaves according to AMDs tuning, 75mV stepping should be used for very bad leaky silicon
> Leaky silicon = X series cpus which are rated to boost near 4.7/4.8 while using absurd voltages
> 
> EDIT:
> One exception that exists with a bit different scaling:
> 50mV *2
> VDDP 900mV
> VDDG 1000mV
> vSOC 1100mV
> 
> same as:
> 75mV *2
> VDDP 900mV
> VDDG 1050mV
> vSOC 1200mV
> both of them still work as exceptions, but it would be a bit stupid
> They only make sense if you break them down in:
> 50mV *2
> VDDP 900mV
> VDDG IOD 950
> VDDG CCD 1000
> VSOC 1100mV
> 
> 75mV *2
> VDDP 900mV
> VDDG IOD 975
> VDDG CCD 1050
> vSOC 1200mV


Thanks!


----------



## FleischmannTV

byDenoso said:


> Thanks!


He mixed up VDDG CCD and IOD in that misquotation.


----------



## craxton

byDenoso said:


> What's the tCKE timing? does it increase latency even with power down off?


(the first one will help your question.)
ive got to many bookmarked to which some i know how to use,
some i didnt know the website at that time to know what i was saving.
so, ram, CO, stretching, DF-Cstates, all kinds of stuff. (99.9% will be
bookmarks from Veii)

do keep in mind that while most these "rule-sets" work most the time,
in some cases ram will still need a +1/2 here and there depending on
binning.
Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'


(EDIT) this one here be a good one to 
check as well.
Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'


Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread 'AMD max overclocking voltage'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'

Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'


----------



## craxton

Veii said:


> It needed 1.6v to finally reach stable 14-14-14
> Not because the set would require it (i mean also), but because RTT_PARK was weaker
> (706 instead of 005 ~ didn't want to run 1.55+ on my A0's at 005 or even 705. I like this memory ~ but VDIMM requirements increased with weaker PARK)
> Soo more VDIMM was needed ~ but it absolutely doesn't mean, that it causes more heat. Voltage on it's own doesn't translate to heat.
> It's the Amperage that arrives ~ depending on resistance and impedances throughout the chain.
> Except that timings love more voltage, soo it can be beneficial to take this route instead of the easier 005 / 731 route
> 
> RTT_PARK got lowered to /7, RTT_NOM got increased to /5 . Initially 6/3/6 where running @ 1.66v
> Now it's 1.65v, as NOM seems to just cover the voltage requirements of the one step "lower" PARK
> 
> RTT_NOM should be increased if you increase voltage (lower divider, stronger value)
> RTT_WR is dynamic ODT and a whole layer ontop of the current ODT & powerdown signal path (dynamic)
> RTT_PARK depends on the PCB quality and will increase heat if you increase it. Requirements depend on the IMC's FW and preconfigured RZQ values (more to it later)
> 
> 3800 MT/s can need between 1.5-1.6v , usually it's 1.5v and above
> But 1.5 flat is only at 731 (DR) or 005 (SR) ~ where after 1.51-1.52 you start to see instability , till you use 705 then 1.54v is your instability range
> Higher voltage either doesn't work because of heat or start to give you fully dropped channels at 1.54-1.55. If this happens, 1..56+ would kill the PCB.
> It depends


Does this still apply the same with latest 1.2.0.3 bios releases?
if so perhaps i went wrong in my "test/fail/test/fail" trials on 14-14 3800 set


----------



## byDenoso

craxton said:


> (the first one will help your question.)
> ive got to many bookmarked to which some i know how to use,
> some i didnt know the website at that time to know what i was saving.
> so, ram, CO, stretching, DF-Cstates, all kinds of stuff. (99.9% will be
> bookmarks from Veii)
> 
> do keep in mind that while most these "rule-sets" work most the time,
> in some cases ram will still need a +1/2 here and there depending on
> binning.
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> 
> (EDIT) this one here be a good one to
> check as well.
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread 'AMD max overclocking voltage'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'
> 
> Post in thread '[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread'


Thanks mate!
I'm reading it all now.


----------



## adversary

adversary said:


> Pardon me for replying too late and bringing up posts old for some days (and you have more advanced topics at moment being discussed). At moment situation are here specific, I don't have access to PC all time (but soon it will end as we are near end of competetive play). On top of that, global temperatures are insane this year, forcing me to leave my city for some days from time to time. Hope it will normalise at least to usual summer temps
> I however read this thread and document all time from mobile, all stuff I find it useful.
> 
> Now for this motherboard 1203A is released as stable, and 1203B as Beta. there is no rush, guess I will wait until get 1203B stable while collecting info about it.
> 
> Now on 1201A all works fine, old problems are gone for months after last tuning. Zero issues or problems.
> on 3800/1900, dual-rank, I made 51.9ns (chiller off, radiator fans on)
> on 3800/1900, same RAM, I made 51.2ns (chiller on, radiator fans off), but lowering tRCDRD from 14 to 13 (as 13 is stable and full error free only below certain RAM temperature point).
> Tested with number of tests, including usmus TM5 25 cycle, and AntaExtreme for some time. no errors, and no variance in Aida64 repeated runs.
> (result is in Google Datasheet)
> 
> However, how my twaking is really proper or good, I put in question, it may be that I "bruteforced" stability with very low RAM temps (it is also under chiller cooling). Hence I would try to do complete new tweaking once I do BIOS update and get more time. So I'm trying to catch all info in meantime.
> 
> Back to direct topic - my voltages used for this, running now, are :
> (what ZenTimings 1.2.3 read)
> 
> CLDO VDDP - 0.8973V
> CDDG CCD - 0.9032V
> CDDG IOD - 0.9710V
> VSOC - 1.0875V (set in BIOS 1.1V)
> 
> 
> I did read all you linked. However, some users, and also you mentioned something, that running CCD voltage above 940mV caused another issues?
> 
> Could I try to run CLDO VDDP for example 0.88V, while using stepping of 40mV or more to separate it from CLDO VDDP, and to try to still have CCD not above 940mV, ?
> 
> I'm looking now in proper direction? Maybe another voltages, with your advice that it is still better to have stepping between CLDO VDDP and CDDG CCD, could be better solution? If needed, I can link my ZenTimings picture.



@Veii I quote myself to make my post visible again. we was discussing mostly about voltages and proper steppings, however when I responded to you, thread get locked and it was locked for few days, probably you did not see it for that reason.

I will have to manually copy below what you said (so my quote of myself was response to that) :


It's this thread








*AMD max overclocking voltage*
Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...







www.overclock.net

AMD's early stepping for Matisse (thanks The Stilt) was 50mV , at least enforced 50mV stepping








*Strictly technical: Matisse (Not really)*
07/08/2019 6:33 PM (GMT) - Update on the bios issue on Crosshair VIII Hero motherboard ("the thing"). Earlier today I received a response to my inquiries from ASUS. The response was rather technical and I cannot go into the specifics of what exactly it involved. However, it confirmed my...







www.overclock.net
But 50 and 75mV worked well
OC'ing T-Force 4133 cl18 (bottom half of the thread)

This generation (Vermeer) it's 40mV as minimum stepping between all of the 3 & 1 higher procODT than Matisse
Only one exception exists, which is that VDDG CCD can be equal to cLDO_VDDP , but it often might be better 40 or 80mV over it 

this post sums it up, with the relinked reddit in the quote
MSI B550 Unify / Unify-X Overclocking & Discussions... credits to weleh
The comments of reddit sum it up
AMD starts to enforce removal of 1200, 1181/1191 and 1201
while these bioses where one of the few without usb dropouts
And yet nearly no one has 1203B out , only 1203A , which did nothing against usb droupouts


----------



## clackersx

Thanks to @Dasa and @Veii for advice on my previous post a while back (3800 C15)

Turns out while gaming the ram got too hot, so i added a fan to the ram and due to adding the fan I couldn't help myself and started messing with CL14.

3866 or higher was too hard with heaps of WHEAs, i am happy with 3800, max BCLK i could get was 100.4, i am not sure if i will keep that or set it back to 100.00.

Is there anything i have set wrong/suggestions or am i good timing wise?
I am happy with the performance.


----------



## spajdr

Hello people,
If I get WHEA errors above 1900 FCLK is it a lost cause or I can do something about it?
I noticed that changing voltages (CLDO VDDP,CCD,IOD,SVI2) change frequency how fast WHEA errors are reported.
But I didn't find the pattern when it's report by 1-2 errors or 20-40 errors at once.


----------



## XPEHOPE3

Finally I've got something interesting stable:






















I'm tempted to tighten timings instead of pushing 3933 which I couldn't post with on any previous BIOS.
From this setup RTTPark /1 -> /2 and/or ClkDrvStr 30 -> 40 won't post. 36.9 procODT gave worse Aida latency (but then again I might be able to bruteforce training the same way).
Also to post setup from screenshot I often need *to first post it with 3800MHz, and then push 3867*, since 3867 won't post "by itself".

What does one need to push *4* sticks of *dual-rank* B-dies to *3933+*MHz? I'm yet to see a screenshot of this. Well, I think I never saw 3867MHz B-dies pushed that far yet too...
Are there any recommendations in what order to tighten timings to minimize time one has to run TestMem5 and other stability testers?



Veii said:


> If you change CsOdtDrvStr to 30+ like advertised many times for Vermeer - it fixes memory training issues


This helped, I think. Only two training sessions needed to have tPHYRDL=26 on both channels, which gave 58.3+-0.3 Aida latency (within one boot it varies less - 58.4-58.6 on this boot, and 57.9-58.3 on previous boot).


----------



## Kurt Krampmeier

Veii said:


>


Thanks for the input. those settings fail to boot above 3400MT
It seems to me, that my b450 Board does not work well with low proc ODT.
Higher vddp/ccd voltage and clkdrv resistance where also no help.
I also did some testing lately with GDM off 1 and 2T - with copying your suggestions to similar setups - no success even at low speeds.
For the 3600MT in screenshot it would not fully stabilize at 40Ohm (TM5 Errors out at 25min in A777-ext) - at 43.6 it works fine. 
I did however correct the TRDWR and TWRRD timing; they where left over from trial and error and had no penalty, so i did not change them.
I have my eye on an old crosshair vii or b550-f on ebay for reference testing (i only buy cheap) - i am at a point where it seems unmistakably that the b450 Board does not have any headroom above 3667MT with 4 sticks, although its a rather new SKU

edit:
for the full picture. i find those not too shabby:


----------



## byDenoso

Finally Managed to get 1T stable.


----------



## Nighthog

For those interested I did try out the suggested RTT 0/0/6 rather than the standard 0/0/5 combination.

RZQ/6 for RttPark. I tried 7/0/6 but 0/0/6 was more stable that I could tell.

For my system/memory to have it work compared to RZQ/5 I had to increase ProcODT from 34.6 -> 40.0 Ohm and also change my ClkDrvStr from 20->32 Ohm
Voltage for the dimms was not needed to change and as far as I could tell liked it to be the same after those changes.

But still more work needed to get it stable.
Y-cruncher in particular shows the instability quickly @ 5000Mhz if I don't want to wait around for TM5. I was trying this out if it would help but don't know if it's better or not in general.


----------



## ManniX-ITA

@Veii

Trying the profile you suggested; it's ok but a bit weak on write and copy in AIDA.
Have to reduce the temperature with this hot weather...

Couldn't make it work flat 14s; tRCDRD 14 at 3800MHz doesn't work either with this kit.
tRFC 240 is as well too much; had to go down in VDIMM so picked 260.
Any suggestion?


----------



## byDenoso

Nighthog said:


> For those interested I did try out the suggested RTT 0/0/6 rather than the standard 0/0/5 combination.
> 
> RZQ/6 for RttPark. I tried 7/0/6 but 0/0/6 was more stable that I could tell.
> 
> For my system/memory to have it work compared to RZQ/5 I had to increase ProcODT from 34.6 -> 40.0 Ohm and also change my ClkDrvStr from 20->32 Ohm
> Voltage for the dimms was not needed to change and as far as I could tell liked it to be the same after those changes.
> 
> But still more work needed to get it stable.
> Y-cruncher in particular shows the instability quickly @ 5000Mhz if I don't want to wait around for TM5. I was trying this out if it would help but don't know if it's better or not in general.


It works with Matisse too?


----------



## Veii

ManniX-ITA said:


> @Veii
> 
> Trying the profile you suggested; it's ok but a bit weak on write and copy in AIDA.


Mm i don't like this profile either. tRCD 15 is just weak & strange. Rather messes things up.
136ns tRFC hmmm
If you just even out tRP to 15 and increase tRC +2
I remember 14-13-15-14 run well, with tRAS 27
But still not a big fan of uneven timings 




ManniX-ITA said:


> Have to reduce the temperature with this hot weather...


Join the RTT rabbit hole 
A lot of trial and error with instability fun included
Yet results aren't bad once you succeed 
1.64v tRP 13 , 44c peak , the other dimm is on 42ish


----------



## Nighthog

byDenoso said:


> It works with Matisse too?


Haven't tested, no idea. But generally it seems fine, or just as fine if slightly better with Renoir at least. But RZQ/5 is much easier to do with more leeway with the settings allowed.

EDIT: Tried it out on the 3800X B550MH but didn't manage to boot with RZQ/6 at all.. Only done so with RZQ/5 or RZQ/4 etc.
Most likely because the system refuses to start with other than [20,20,20,20] DrvStr values @ 5000Mhz with the other kit of memory of same type.


----------



## ManniX-ITA

Veii said:


> 1.64v tRP 13 , 44c peak , the other dimm is on 42ish


Mines are peaking 63c over TM5


----------



## Veii

Nighthog said:


> For my system/memory to have it work compared to RZQ/5 I had to increase ProcODT from 34.6 -> 40.0 Ohm and also change my ClkDrvStr from 20->32 Ohm
> Voltage for the dimms was not needed to change and as far as I could tell liked it to be the same after those changes.


I am not sure if you've used RTT_WR
But RTTs need always a helping hand
CKE low Park, and CKE high Nom, need to be supplied if dynamic is not used

If you skip nom, you can run off park to some extend but only for low voltage
High voltage will overshoot and reflect back

DynamicODT can be used to generate NOM or to generate PARK , if you drop one of both
But its needed for such to work
If you have issue's with 706 or 636 then you need high vdimm beyond 1.5
If you run WR /2, you need vdimm beyond 1.6

If you have to increase procODT that much, it means that ClkDrvStr is far to weak
Usually rev.e didn't show positive scaling with 60+
But i remember early on, they needed 60 for GDM off
There is no need to decrease signal integrity in the chip with a such strong signal
Just shift it over yo ClkDrvStr. It has to work


----------



## byDenoso

A New bench using some fancy math of @Veii "Shenanigans". it has improved latency by a lot (almost 1ns).
Now i want to tighter the "SD,DD" timings, tRDWR and tWRRD.


----------



## XPEHOPE3

Anyone knows *why BCLK can throttle* as soon as one *sets tRC+tRFC lower than Auto*?
Examples of me trying tRFC=8*tRC on different BIOS:

tRC 49 causes 98.7 droop with DRAM 3752MHz instead of 3800MHz







tRC 45 causes less droop (99.2), DRAM is 3769MHz instead of 3800







My Auto tRC + Auto tRFC are way high, but cause no BCLK droop:

FreqtRCtRC ns46.75*Freq/2000tRFCtRFC nstRFC ns / 46.753200 (XMP)7546.87574.85603507.48663101636008547.2222222284.156303507.48663101638008946.8421052688.825666350.52631587.49788910838679147.064908290.391125677350.14222917.48967335

From this data I gather my board BIOSes like to keep tRFC/tRC multiplier as 7.5. And to keep tRFC at 350 ns or higher. 46.75ns is actually 350/7.5=46.(6) but rounded to closest multiple of 0.25. So for some reason my BIOS likes to compute in nanoseconds instead of cycles. And it sets tRC on Auto to near 46.75ns although my XMP profile asks for 30ns.
I still don't get why for 3800 I get tRFC 666, as tRFC 665 is perfect 350ns.


----------



## aditrex

@Veli friend u dont mind looking into my Drvstren settings whats the best i could use in my situation dont forget i run weird ass timings becouse either my cpu is such a trash lottery or i just have some hard reason to get it fully stable under BFV multiplayer the game i struggle most becouse uses AVX instructions and it does crash to desktop with no msg.


----------



## aditrex

settings


----------



## Veii

Kurt Krampmeier said:


> Thanks for the input. those settings fail to boot above 3400MT
> It seems to me, that my b450 Board does not work well with low proc ODT.


Please try again with tWRRD 3
I made a mistake and forgot that you run 4 dimms ~ i'm sorry
Also use then 36.9 (which has to work) ~ proc was correct for 4 dimms but forgot that many dimms need some kind of tWRRD delay 2 to 4

If you have errors ~ report them.
"I have errors" doesn't work sadly.
i need to know what, when & which one follow after your first error

If you have post issues, retry 4 times
Often memory training is broken and 1 out of 5 boots may succeed ~ yet be fully stable

@XPEHOPE3 & @byDenoso google for Aida64 keys if you can't want to support the developer. There are System Integrator keys out there.
The whole readout is interesting to spot any random throttle. Else you have to use SiSandra to spot curve differences/bandwidth differences as throttle
Both yet require a clean OS - soo consider to run Sophia-Script first



aditrex said:


> dont forget i run weird ass timings becouse either my cpu is such a trash lottery or i just have some hard reason to get it fully stable under BFV multiplayer the game


3 Questions:

Who gave you this abstract tRFC ?
Who told you to run tRAS lower than double tRCD ?
Are voltages also on auto, because SOC is lower than IOD. SOC needs to at absolute minimum 40mV higher than IOD. In your case IOD is too high for this low frequency. Same for procODT. 30-32ohm max sub 3800MT/s

Oh also is this even stable ?
If it's XMP predicted, it still can be unstable.
Can you confirm your CPU or your memory is stable at all in the first place ?

@ManniX-ITA , still no AGESA 1.2.0.3 A/B - nothing 
It's . . . frustrating. I can't test anything on it 
Neither ProArt nor ITX get them. Feels like board partners do it intentional. Guess if i get a Unify-X , it will also stop receiving updates 😅


----------



## Veii

ManniX-ITA said:


> Mines are peaking 63c over TM5


I question if Alphacool D-RAM Modul , would be any useful ~ compared to the Vipers "heatsink"
Also more, to make them low profile
RGB on Trident Z seems to cause +3c increase. Yet wonder if it wouldn't keep stacking, if the heatsinks are rather heat-traps


T[]RK said:


> Here is respond from 1usmus on my HWiNFO64 screenshot:
> 
> __ https://twitter.com/i/web/status/1411620683226955779


I wonder if he even understood you
ты можешь спросить его по русски ~ if he PMs you

He is on some point right, HWInfo does SMU calls, CTR does SMU calls via PCI MUTEX
Both together do make issues. Same as tool.exe and HWInfo together make issues

My intention was, with RC06 ~ because it has an Overboost prevention mechanism.
As RC05 does rely on DF_C-States and so can cause overboost. (it's normal)

As much as i want, i can not share RC06 updater
It would be time for him to publish it publicly ~ but he'll know better
Maybe some Patreon user can do you a favour 
Or somebody from OC.ru has it too.
Idk, but if you want to track temps - stay with CTR . Either / or , not both
See if you can get on PX high anything beyond 4.9Ghz to run @ 1.4v , with PX mid at 1.35v 
If you can , maybe support him on Patreon. If you don't , just stay with PBO


----------



## ManniX-ITA

Veii said:


> I question if Alphacool D-RAM Modul , would be any useful ~ compared to the Vipers "heatsink"


Oh I'm pretty sure about it, made a big difference compared to the Trident RGB HS
Also I'll use Gelid Extreme pads
Anyway I'm trying to speed up the new rig so they'll go un der water soon
In the meantime it's going to be even worse as I decided to ditch the 3080ti for a 3090... should arrive tomorrow


----------



## byDenoso

Veii said:


> @XPEHOPE3 & @byDenoso google for Aida64 keys if you can't want to support the developer. There are System Integrator keys out there.
> The whole readout is interesting to spot any random throttle.



@Veii


----------



## aditrex

Veii the problem is at this point im trying everything just so i have game free crash i copy pasted someone profile i know it is weird but just desperate test o corrected to this now but still wonder whats safest Drevstren settings overall


----------



## XPEHOPE3

Veii said:


> @XPEHOPE3 & @byDenoso google for Aida64 keys if you can't want to support the developer. There are System Integrator keys out there.
> The whole readout is interesting to spot any random throttle.


I already bought it (as one can see from my other screenshots), it's just these screenshots that were made before it 😅 .

Also I walked through your tRFC calculator...

Why don't you ever use ROUNDUP function, only ROUND? For 3867-15-45 setup currently on Copy sheet, for tRC / (tCL / 2), tRFC4 appears 154 instead of 155.
Have you considered fixed point arithmetic for this? Or maybe Q-notation or B-notation? That is, if BIOS needs to store ns of one cycle for 3800 setup and it only has 4 decimal digits, it stores 0.5263, and then on Auto uses it to compute tRFC targeting 350 ns like this: ROUND(350/0.5263)=ROUND(665.0199)=666 instead of mathematically correct 665 (like in my post above). But then since BIOS is likely to use the same thing for hidden timings, non-Auto values have to account for this, that is continue to use the same arithmetic, not infinite precision.


----------



## Veii

XPEHOPE3 said:


> Why don't you ever use ROUNDUP function, only ROUND? For 3867-15-45 setup currently on Copy sheet, for tRC / (tCL / 2), tRFC4 appears 154 instead of 155.


Roundup, was not always the best choice
Been crosstesting it, as MT/s convertion is one of the core issues ~ soo i can not rely on any transfer time values
This means, that i can not technically rely on the timings-ns convertion

Soo i do couple more checks, which makes setting any speed pretty irrelevant
The same goes for the manual part
I keep it still, soo it shows a visual indication ~ but i should've eliminated that potential issue with rounding errors



XPEHOPE3 said:


> Have you considered fixed point arithmetic for this? Or maybe Q-notation or B-notation?


Was never good in math to begin with , i am not sure if i understand Q-Notation but it looks for a way to fight against the high decimal rounding issues
tRFC appears to be point 5 ~ soo we don't use this step & just skip to the one that is a clean divider.








The NS values are for anchoring own math or just visualization. I think i've resolved the rounding problem.
If you round down or up, the result will be wrong.
But if you round up twice (as MT/s is round up already) the result will be twice as bad
Round up and round down together made it more accurate.

There was some change between old methods and current methods. But this current method seems to be more accurate
1usmus's tool had a stacking round down issue.


XPEHOPE3 said:


> That is, if BIOS needs to store ns of one cycle for 3800 setup and it only has 4 decimal digits, it stores 0.5263,


The bios doesn't compute 4 digits. But there is the critical problem ~ it's a design issue from the multiplier to the MCLK to the MT/s conversion
The rounding happens internally already several times
Even when mini looks like it uses fixed world clock values, it doesn't anymore. That was old method but it showed flaws ~ see shenanigans (test) sheet
Any type of world clock value as divider if not procentual or integer, will only increase the stack of rounding issues

I shouldn't use / 1.346 & / 2.1875
But compared to online found methods who take tRFC as a base
I don't. I reverse check it soo there is only one stage of rounding at the very end. It does not stack and multiply rounding.
Soo using one rounding is equally to what bioses will use as one rounding.
Rounding will happen anyways, and the flag for it , just does already what the bios will do anyways ~ yet the ns math should be accurate.
I try not to rely on any world clock values, soo i can not have rounding issues 
And ones that end up to tRFC flat value, won't have rounding issues stacking
Others who already end up as decimals, will have one rounding in there. Soo i decided to put it at the end stage and not stack rounding issues

Probably my biggest issue with all, is that i have no accurate source of feeding the calculator in ~ no accurate real clock value
I can not relay on any world clock values and i can not create tSTAG out of thin air ~ to fully skip any usage of MCLK sync. I already don't , but this was the best i got up with , after several iterations

tRFC is not an issue if it overshoots, but it is a big issue if it undershoots 
Yet even tools accuracy is based on the users correct input . And that is tRAS+tRP = tRC
if tRC is messed up, the math will be messed up
The results always work if the IC & PCB supports it, they are on time without getting skipped.
But i can not rely on the same methods 1usmus used for his DRAM Calculator.
He can do it, on tested sets ~ i can not do it, because there is no input to read from 

Please let me know if you have other accuracy methods that i can implement,
But i can not use any world-clock value. Only integers which are not aligned with MT/s whatsoever. 
Hey maybe you know how to compute tSTAG out of thin air.
The initial plan was to use a whole calculator with timing delays and then get tRFC out of it. But i missed couple of modules for it, so it never was done
And without correct input, there is no way how i can work with made up decimal values. Soo end-stage rounding + boards work, i decided was the closest to it. Yet it's only 99% fine, it can be lower by 1/8th + 1/4th + 1/2th of the result ~ for *5 (well 5.8725 , but accuracy of such needs tSTAG calculated out of thin air)

EDIT:
Technically, if i should be even more accurate,
I would need to take ns value out and use tRFC 2 , to make tRFC
The way it is supposed to be done
But then we have another problem of DOCs or calculators rounding after the 18th decimal by their own
i do use reverse checks & used couple more - to check if the result really was accurate
But i can not use world clock values. Can not rely on the bios to get it accurate (which it doesn't) and can not recreate the whole memory delay chain, to "create" input out of thin air.
Soo skipping any world-clock value, was the best thing to do & just round if it needs to round. Same thing the bios will do anyways
But if i do it, at least it's technically bad, but "fixed bad", i won't have to trust the bios to do it correctly ~ as who knows how many decimals it even supports 

What i ended up deciding for:
Was instead of Board 3x Rounding (Multiplier, MCLK, MT/s) + Transfer time ns + divider world clock + tRFC to tRFC 2
I just skipped these steps and only once at the very end round up. Less stacking rounding ~ but surely there is a better method if you know one
I can not eliminate board rounding internally, soo rather just do it myself once & fix tRFC 2 & 4, soo it won't continue to predict a mess


----------



## Dasa

clackersx said:


> Thanks to @Dasa and @Veii for advice on my previous post a while back (3800 C15)
> 
> Turns out while gaming the ram got too hot, so i added a fan to the ram and due to adding the fan I couldn't help myself and started messing with CL14.
> 
> 3866 or higher was too hard with heaps of WHEAs, i am happy with 3800, max BCLK i could get was 100.4, i am not sure if i will keep that or set it back to 100.00.
> 
> Is there anything i have set wrong/suggestions or am i good timing wise?
> I am happy with the performance.
> 
> 
> View attachment 2516450
> 
> View attachment 2516451


Changing RTT to 633 and lowering ProcODT should help lower temps but may need a little more juice to keep it stable.
AddrCmdSetup 56 may allow for 1T and tCKE 9 may also help while at ~3800.


----------



## XPEHOPE3

Veii said:


> tRFC is not an issue if it overshoots, but it is a big issue if it undershoots


That's why I ask why don't you use ROUNDUP. That way it would never undershoot for sure  Also "as MT/s is round up already" is only correct for DRAM/FSB=(3k+1)/3 or (3k+2)/3. For example, for DRAM 3800 you only round down. Anyway, if you say that any of your Micron stick instabilities surely don't come from tRFC miscalculation being 1 clk down, I believe 


Veii said:


> i won't have to trust the bios to do it correctly ~ as *who knows how many decimals* it even supports


I think I (or anyone for that matter) can compute it from what BIOS shows for Auto values of tRFC based on MEMCLK. BIOS will try to force certain ns, which incur rounding errors, but those would come from exactly one position of decimal point. Varying MEMCLK one can find such a point. If you say tRFC uses 5 decimals, then BIOS uses 5 decimals. Or higher, but in the end rounded to only 5.


Veii said:


> The bios doesn't compute 4 digits.


Yeah, hardware doesn't need to divide up until the end. Memclk can be represented as in Aida DRAM/FSB field, that is via integer number (let's call it D) which would be divided by 3 to represent memclk scale. For 3800 it's 57: 57/3=19=38/2. For 3867 it's 58: 58/3=19.(3)≈38.66/2. D = round(MEMCLK*3/200). So 1 clock in nanoseconds would become 2000/MEMCLK=2000/(D*200/3)=30/D. So all the ns computations are in integer apart from the one last division.


----------



## craxton

clackersx said:


> /suggestions or am i good timing wise


100 cycles of TM5 lol? 
-suggestion, Y-cruncher 1-7-0 (5 runs minimum) and do leave your "PBO" wide open 
otherwise your gonna hit 90c and throttle/do a little damage somewhere while letting it run like that.
HCI memtest let it at least do 1000%, and Prime 95 SFF (i just let it run over night) but it was stated how long)
if you pass those then your solid. i dont suggest changing anything if your "satisfied" but then again, if that were 
truly so youd not be here asking 🧐



spajdr said:


> is it a lost cause or I can do something about it?


it depends on "how" your going to look at it, are you getting "dropout" issues with USB stuff?
random audio crackles at higher than X fclk? if no, then your "!CAN!" use 
this only on "win 10" atm, to shut it up. if your ok with that. you can remove it as well. 
as ive used it recently on my 5800x as it doesnt like over 1900fclk, to which, unsure if it was voltages
or what but i had MAJOR issues with fclk above X limit with "display cutouts, mouse/USB drives dropping out, speakers crackling etc"

so lost cause to "fix" for now seems so, lost cause to "IGNORE" not entirely


----------



## Kurt Krampmeier

Veii said:


> Please try again with tWRRD 3
> I made a mistake and forgot that you run 4 dimms ~ i'm sorry
> Also use then 36.9 (which has to work) ~ proc was correct for 4 dimms but forgot that many dimms need some kind of tWRRD delay 2 to 4
> 
> If you have errors ~ report them.
> "I have errors" doesn't work sadly.
> i need to know what, when & which one follow after your first error
> 
> If you have post issues, retry 4 times
> Often memory training is broken and 1 out of 5 boots may succeed ~ yet be fully stable


me again.
i can confirm, that MBIST tends to disable after a failed ram OC. 
when the board falls back to 2133MT it can be observed that MBIST switches to disabled and needs to manually enable in amd cbs; at least on my Board.
my Results are as follows. i set the values as advised and let every other thing on auto and went from 2400MT upwards. vdimm was 1.50v
The 3600MT were the highest i got with GDM off 2T at given values. GDM off 1T did not boot at any speed over 2666MT (that should tell something on signal quality with that board).
setting ccd, iod, vddp voltages manual would not help - training failed at 3667. clkdrv 60Ohm did not help.
Timings are all Result of Memory training with auto timings. 
i assume CL25 is the worst possible setting. at 3200MT it was already at CL21.
when i tried to set CL18-18-18-40-60 - MBIST broke and reset to 2133. setting mem OC fail counter to 5 did also not help;
i will try again with another board to rule out my incompetence. 
i would stand to my assumption that 3600MT is a bit low as a ceiling for 4 dimms sr with Zen3.


----------



## XPEHOPE3

Kurt Krampmeier said:


> i can confirm, that MBIST tends to disable after a failed ram OC.
> when the board falls back to 2133MT it can be observed that MBIST switches to disabled and needs to manually enable in amd cbs; at least on my Board.


That's common. Also for example PBO settings reset. For me PBO enables itself, and PBO scalar becomes Auto (while I set it manually to 1x).
That's why one has to save BIOS profile every now and then, so that it can be loaded immediately after PC posts into JEDEC config instead of what's configured in BIOS. With that said one is better off saving actually working profiles, loading them and then reapplying values currently being tested.


----------



## Veii

Kurt Krampmeier said:


> i can confirm, that MBIST tends to disable after a failed ram OC.


Every AMD CBS setting will reset upon NVRAM Clear
Every AMD OVERCLOCKING setting will reset on CMOS clear

Board settings "recover!" mostly is an nvram reset while keeping primaries. (soo load your bios profiles, as settings will be missing)
Board 3-4 reboots reset, is a cmos reset and it won't keep main OC settings there

Reset is a reset.
The same way not every "type" of OC profiles keep AMD CBS
The same way not every type of bios reset is a cmos reset.

Boards down to a B350 Tomahawk can run 4133MT/s
4 dimms run on B350 Tomahawk at 3600. B450 is easier
Boards are not your fault, neither is 12nm or 7nm IMC
Neither was 14nm first gen IMC with correct voltages

I think you trust too much on auto settings
Boards are not IC or PCB aware. They are preconfigured presets aware which are cycled through (bruteforced) as what AGESA has preconfigured
Boards are tCCD_L aware, and use this to recalculate Intel XMP , yet are not IC nor PCB aware
Unless boardpartners add "presets" in post , it will behave how AGESA tells it
AGESA == AGESA = Memory Training
Every Board running X AGESA behaves identical to Y board running X AGESA ~ unless manually added "preferences" in post
Unlike Intel where every board behaves different ~ AMD doesn't allow it. Every AGESA is identical , if supplied and used (patches) Identical

When you stop trusting too much AUTO settings - every board you gather will behave nearly identical
PCB Layers do matter later and for more extreme scenario's ~ but not much sub 4067-4133MT/s
Yet if you trust something PCB nor IC aware to predict correct values, you trust more on the issue disappearing, than try to work on the issue


----------



## XPEHOPE3

XPEHOPE3 said:


> And it sets tRC on Auto to near 46.75ns although my XMP profile asks for 30ns.


I found out why!! Via Samsung search I found Samsung datasheet for my exact memory module. And on page 36 it does say tRC is min 46.75 ns for some DDR4-2133 modules. So that's BIOS just forcing my kit to JEDEC even when XMP enabled.


----------



## Veii

XPEHOPE3 said:


> on page 36 it does say tRC is min 46.75 ns for some DDR4-2133 modules. So that's BIOS just forcing my kit to JEDEC even when XMP enabled.


Bioses are not IC or PCB aware 🤭
tRFC 2 & 4 , never will be correct if you let it do it's thing
It will calculate tREFI by tRFC accuracy. And so tMAW.tMAC (tRC_PAGE) can potentially "now" be calculated
But they remain DIMM unaware & Intel XMP barely supplies any helpful information.
Intel Boards where Manufacture (overclocker) tuned. AMD Boards barely to never.

They can have preferences in post, but are not allowed to touch precompiled AGESA
ASUS is just doing their own things
But MSI and ASUS both have to work with AMD & maybe can add own "preferences" yet not "modifying" AMDs AGESA behaviour
Each of them also have to bent down to the Daisy Chain decision for 500 series, or ignore it and bring out dual dimm boards.

EVGA might be here an exception near AM4 EOL, yet even they bring out a rotated 2 dimm X570 board out (two)
* i'd like to ask get a board with a new non Vermeer CPU 🔥

EDIT:
Speaking about getting things,
@ManniX-ITA did you have any success on getting XOC Bioses for AM4 & Z590 ?
I've tried communicating with MSI JP Representatives, but it was generally a complicated talk.
I don't understand MSI's policy with supplying XOC modified bioses
Are they that modified, soo exchange needs to happen behind closed doors.


----------



## XPEHOPE3

Veii said:


> Bioses are not IC or PCB aware 🤭


How do you explain then why my BIOS auto chooses exactly such a value for tRC? (tRC, not tRFC! in case your misread)
That value is not universal: for example, for Micron 2133-15-15-15 it would be 46.5 ns (page 340).
EDIT: that doc provides lots of interesting Micron formulae, for example at page 357 for tRRD_L and tFAW


----------



## Kurt Krampmeier

Veii said:


> I think you trust too much on auto settings
> Boards are not IC or PCB aware. They are preconfigured presets aware which are cycled through (bruteforced) as what AGESA has preconfigured
> Boards are tCCD_L aware, and use this to recalculate Intel XMP , yet are not IC nor PCB aware
> Unless boardpartners add "presets" in post , it will behave how AGESA tells it
> AGESA == AGESA = Memory Training
> Every Board running X AGESA behaves identical to Y board running X AGESA ~ unless manually added "preferences" in post
> Unlike Intel where every board behaves different ~ AMD doesn't allow it. Every AGESA is identical , if supplied and used (patches) Identical


i understand your point.
knowing that ryzen is soc with some wires to the dimm slots (very simplified) is the reason i am still trying.
In my understanding, Memclk just hast to work up to when the IMC bows out.
that nvram rest you describe is what happens on my b450.
problem is, that this reset happens at kind of a wall at 3667MT, nearly regardless of settings.
I did have timings reloaded from my profiles as i observed earlier what you just said (primaries stood, everything else went auto, CBS gone)
I am just running out of variables to change. the failing GDM off 2T, which i think should work, is what concerns me.
when its not working at cl18 with procodt 36,9 - 40 and clkdrv 60 at 1.5v - vddp 0.950v etc. it shifts my suspicion towards the board itself.
an impression of signaling quality would possibly help. but what would be a practical way to do so? 
i did measure latency consistency with aida and it is stable at 3600MT with 55.1 at the time of writing on a clean win10. but this is more or less reading coffee grounds imho.


----------



## byDenoso

Did i have to change any AMD CBS settings to achieve lower latency?
On my bios i have a lot of options (UMC Common, NBIO...)


----------



## XPEHOPE3

@Veii 
Also both Micron (page 377) and Samsung (page 67) documents have nearly the same paragraphs about how to convert time to clocks. DDR4 SDRAM requires >=picosecond precision, so nanoseconds are rounded for 3 digits past decimal point. And there are correction factors none of the tRFC calculators use.


----------



## Veii

XPEHOPE3 said:


> And there are correction factors none of the tRFC calculators use.


Likely. It would be good if one single person knew everything
I don't follow JEDEC since a very long time.



XPEHOPE3 said:


> , for Micron 2133-15-15-15 it would be 46.5 ns


Will need to find mine, downconvert to SMU 56.30 and make this experiment ~ before the FW change on 56.50 which added new functionality
Would need to test this automatic value on JEDEC (2667) and just run 3200 and see if it gets it right.
Loading XMP does calculations, the whole extend i can't know on a signed proprietary blob, but i can check if it does behave this way
=======================================
Anybody with a 5600X wants to be my testing rabbit ?
I think i'm onto something (CO) 🤭

Unsure if i'd make it correctly with 16 cores, but i can try
Just share me your ACPI quality values from CTR & the maximum boost you can hit (should hit) 


Spoiler: Stock vs Overdriven CTR


----------



## ManniX-ITA

Veii said:


> I don't understand MSI's policy with supplying XOC modified bioses
> Are they that modified, soo exchange needs to happen behind closed doors.


No way to get them directly, stupid policies.
You have to ask @Eder or @YoungChris 
ASUS is definitely much better for this aspect


----------



## Veii

ManniX-ITA said:


> No way to get them directly, stupid policies.
> You have to ask @Eder or @YoungChris
> ASUS is definitely much better for this aspect


Yes, my thought too
Strange policies
They could just share Alpha custom builds, like they usually do

You got your CO settings dialed in already right ?
What Peak boost can your best CCD hold ? (boost tester or Cinebench R20 CTR boost test ~ AVX)
Good morning


----------



## ManniX-ITA

Veii said:


> Good morning


Morning 

This was my last saved run at FCLK2000:


----------



## Veii

ManniX-ITA said:


> Morning
> 
> This was my last saved run at FCLK2000:
> 
> View attachment 2516557


Do you want to be my 16 core testing rabbit ?  🤭
If you can give me the ACPI quality value (CTR) from every core
Without telling me the CO value, i'd like to test some math 

Learned how to work with positive and negative CO
Learned how to read ACPI to frequency values and CTR's algorithm that Yuri used on RC06 & soon Hydra
(Hydra is a bit more powerful with half CCX split voltage control, 3+3 or 4+4)

Would like to test if i can match all of them to 5ghz, or at least improve ~something~
But don't tell me what you run, just note it or remember it


Spoiler



Well optimally you'd run one round of Overboost calculation ~ but it takes too long (to have a 0 CO baseline)
Usually i'd need the first test then i'm fine (AMD programmed)








But i might manage it without any readouts (just need core quality values)
AVX hold and SSE hold
















Overall would like to verify research, unsure if i can frequency match it * For other 5600X i should be able to tho 
* before making a guide how to overdrive CTR


----------



## ManniX-ITA

Veii said:


> Do you want to be my 16 core testing rabbit ?  🤭
> If you can give me the ACPI quality value (CTR) from every core
> Without telling me the CO value, i'd like to test some math


Sure 
Where do I see in CTR the ACPI quality?
Is it ok the values from the ACPI tags in the event log?
Should I keep CO enabled?
I did set to disabled the CO and run the Boost Tester and diagnostic



Spoiler






Code:


***ClockTuner for Ryzen 2.1 RC5(ver.23) by 1usmus***
AMD Ryzen 9 5950X 16-Core Processor
MSI MEG B550 UNIFY-X (MS-7D13)
BIOS ver. A.21O SMU ver. 56.46.00
TABLE ver. 3672068
DRAM speed 3800 MHz
07/06/2021 07:21:39


P1
P1 PROFILE has been restored!
P2
P2 PROFILE has been restored!
PX
PX PROFILE has been restored!




07:22:03: Boost testing started!
07:23:40: Boost testing finished!
07:23:40: Cinebench stopped!


CTR BOOST TESTER RESULTS (test version)
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4728    V 1.386    W 11.21    T 58.74
C02    F 4560    V 1.474    W 13.2    T 65.75
C03    F 4629    V 1.419    W 12    T 59.98
C04    F 4730    V 1.358    W 10.88    T 56.12
C05    F 4884    V 1.436    W 13.32    T 61.58
C06    F 4682    V 1.36    W 10.7    T 55.64
C07    F 4753    V 1.366    W 11.01    T 57.54
C08    F 4690    V 1.364    W 11.18    T 57.5
C09    F 4630    V 1.457    W 11.71    T 61.76
C10    F 4632    V 1.466    W 11.89    T 60.85
C11    F 4605    V 1.456    W 11.79    T 59.99
C12    F 4504    V 1.488    W 12.26    T 62.78
C13    F 4534    V 1.48    W 11.92    T 62.4
C14    F 4578    V 1.453    W 11.68    T 59.46
C15    F 4604    V 1.456    W 11.79    T 61.84
C16    F 4554    V 1.445    W 11.55    T 61.44


CPU TOPOLOGY (ENABLED CORES)
CCX#1    C01
CCX#1    C02
CCX#1    C03
CCX#1    C04
CCX#1    C05
CCX#1    C06
CCX#1    C07
CCX#1    C08
CCX#2    C09
CCX#2    C10
CCX#2    C11
CCX#2    C12
CCX#2    C13
CCX#2    C14
CCX#2    C15
CCX#2    C16
Phoenix ready!
Cinebench R20 started
Cinebench R20 finished with result: 10952
Voltage: 1.34 V  PPT: 133.1 W  Temperature: 80°
07:27:42: Test 1 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP / DEBUG
C01    153    F 28    V 1.439    W 0.12    T 39.31    L 0.954
C02    153    F 4786    V 1.439    W 13.23    T 64.96    L 1.326
C03    153    F 38    V 1.439    W 0.21    T 42.56    L 0.964
C04    153    F 22    V 1.439    W 0.22    T 42.74    L 0.958
C05    153    F 4788    V 1.439    W 12.9    T 62.97    L 1.335
C06    153    F 12    V 1.439    W 0.12    T 39.05    L 0.966
C07    153    F 10    V 1.439    W 0.12    T 42.01    L 0.956
C08    153    F 4    V 1.439    W 0.11    T 37.83    L 0.96
C09    153    F 3    V 1.439    W 0.11    T 40.72    L 0.92
C10    153    F 6    V 1.439    W 0.11    T 37.83    L 0.919
C11    153    F 0    V 1.439    W 0.1    T 39.94    L 0.924
C12    153    F 0    V 1.439    W 0.01    T 37.82    L 0.921
C13    153    F 8    V 1.439    W 0.11    T 39.12    L 0.917
C14    153    F 0    V 1.439    W 0.08    T 38.13    L 0.925
C15    153    F 0    V 1.439    W 0.01    T 38.53    L 0.922
C16    152    F 98    V 1.439    W 1.23    T 39.75    L 0.948
Vdroop:    1.38%
07:28:06: Cinebench stopped!
PX HIGH sub-profile
CPU usage(min):    6.2%
CPU usage(avg):    6.42%
CPU usage(max):    9.8%
SAFE:    4700MHz
FAST:    4750MHz
07:28:06: Test 1 finished!
07:28:06: Test 2 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP / DEBUG
C01    153    F 4526    V 1.424    W 11.46    T 64.02    L 1.207
C02    153    F 4604    V 1.424    W 11.66    T 62.76    L 1.197
C03    153    F 49    V 1.424    W 0.22    T 48.9    L 0.936
C04    153    F 110    V 1.424    W 2.02    T 46.45    L 0.935
C05    153    F 4613    V 1.424    W 12.16    T 68.68    L 1.212
C06    153    F 10    V 1.424    W 0.12    T 40.16    L 0.928
C07    153    F 4613    V 1.424    W 12.04    T 69.25    L 1.227
C08    153    F 6    V 1.424    W 0.14    T 38.38    L 0.925
C09    153    F 26    V 1.424    W 0.12    T 40.85    L 0.923
C10    153    F 14    V 1.424    W 0.08    T 37.42    L 0.92
C11    153    F 10    V 1.424    W 0.14    T 40.14    L 0.927
C12    153    F 1    V 1.424    W 0.02    T 37.38    L 0.921
C13    153    F 2    V 1.424    W 0.04    T 39.26    L 0.917
C14    153    F 9    V 1.424    W 0.05    T 37.6    L 0.926
C15    153    F 8    V 1.424    W 0.04    T 38.61    L 0.922
C16    152    F 90    V 1.424    W 1.09    T 38.97    L 0.946
Vdroop:    1.89%
4600 - PASSED
4625 - PASSED
4650 - PASSED
4675 - PASSED
07:28:32: Cinebench stopped!
PX MID sub-profile
CPU usage(min):    12.5%
CPU usage(avg):    12.5%
CPU usage(max):    17%
SAFE:    4675MHz
FAST:    4725MHz
Max CPU usage for PX MID:    15%
07:28:32: Test 2 finished!
07:28:32: Test 3 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP / DEBUG
C01    153    F 4298    V 1.397    W 10.47    T 68.22    L 1.152
C02    153    F 4476    V 1.397    W 10.77    T 69.06    L 1.158
C03    153    F 4418    V 1.397    W 11.04    T 71.91    L 1.182
C04    153    F 4484    V 1.397    W 11.34    T 72.86    L 1.178
C05    153    F 4484    V 1.397    W 10.97    T 71.68    L 1.164
C06    153    F 4268    V 1.397    W 10.82    T 72.35    L 1.188
C07    153    F 4484    V 1.397    W 11    T 69.66    L 1.164
C08    153    F 4482    V 1.397    W 10.8    T 70.06    L 1.189
C09    153    F 21    V 1.397    W 0.13    T 44.84    L 0.923
C10    153    F 15    V 1.397    W 0.12    T 38.72    L 0.919
C11    153    F 28    V 1.397    W 0.11    T 45.53    L 0.926
C12    153    F 90    V 1.397    W 0.24    T 38.92    L 0.924
C13    153    F 218    V 1.397    W 0.82    T 46.76    L 0.938
C14    153    F 0    V 1.397    W 0    T 38.81    L 0.925
C15    153    F 0    V 1.397    W 0.02    T 44.11    L 0.925
C16    152    F 109    V 1.397    W 1.04    T 40.06    L 0.944
Vdroop:    3.33%
4500 - PASSED
4525 - PASSED
4550 - PASSED
4575 - PASSED
4600 - PASSED
4625 - PASSED
07:28:59: Cinebench stopped!
PX LOW sub-profile
CPU usage(min):    24.8%
CPU usage(avg):    25.02%
CPU usage(max):    29.2%
SAFE:    4625MHz
FAST:    4700MHz
Max CPU usage for PX LOW:    28%
07:28:59: Test 3 finished!
07:28:59: Test 4 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP / DEBUG
C01    153    F 4394    V 1.431    W 7.74    T 61.16    L 1.116
C02    153    F 4394    V 1.431    W 8.55    T 67.98    L 1.124
C03    153    F 4394    V 1.431    W 8.18    T 64.26    L 1.135
C04    153    F 4394    V 1.431    W 8.72    T 70.89    L 1.139
C05    153    F 4394    V 1.431    W 8.26    T 64.46    L 1.12
C06    153    F 4394    V 1.431    W 9.07    T 71.53    L 1.156
C07    153    F 4394    V 1.431    W 8.16    T 62.72    L 1.12
C08    153    F 4394    V 1.431    W 8.68    T 68.19    L 1.147
C09    153    F 4394    V 1.431    W 7.5    T 68.51    L 1.188
C10    153    F 4394    V 1.431    W 7.08    T 61.87    L 1.181
C11    153    F 4394    V 1.431    W 7.6    T 71.32    L 1.227
C12    153    F 4394    V 1.431    W 7.3    T 64.5    L 1.202
C13    153    F 4394    V 1.431    W 7.73    T 70.9    L 1.182
C14    153    F 4394    V 1.431    W 7.24    T 64.36    L 1.23
C15    153    F 4394    V 1.431    W 7.5    T 68.04    L 1.214
C16    152    F 4394    V 1.431    W 7.2    T 63.72    L 1.236
07:29:08: Stress test stopped.
Start VID    1150
Start FREQ CCX#1    3975
Start FREQ CCX#2    3825
Vdroop:    4.35%
4000 / 3850 - PASSED
4025 / 3875 - PASSED
4050 / 3900 - PASSED
4075 / 3925 - PASSED
4100 / 3950 - PASSED
4125 / 3975 - PASSED
4150 / 4000 - PASSED
4175 / 4025 - PASSED
4200 / 4050 - PASSED
4225 / 4075 - PASSED
4250 / 4100 - PASSED
4275 / 4125 - PASSED
4300 / 4150 - PASSED
4325 / 4175 - PASSED
4325 / 4200 - PASSED
P2 PROFILE
VID:    1150mV
CCX#1:    4325MHz
CCX#2:    4200MHz
07:29:17: Stress test stopped.
07:29:17: Test 4 finished!
07:29:17: Test 5 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP / DEBUG
C01    153    F 4394    V 1.434    W 8.04    T 62.56    L 1.118
C02    153    F 4394    V 1.434    W 8.53    T 68.23    L 1.125
C03    153    F 4394    V 1.434    W 8.35    T 65.53    L 1.137
C04    153    F 4394    V 1.434    W 8.86    T 71.56    L 1.14
C05    153    F 4394    V 1.434    W 8.32    T 65.12    L 1.121
C06    153    F 4394    V 1.434    W 8.74    T 70.68    L 1.155
C07    153    F 4394    V 1.434    W 8.35    T 63.96    L 1.122
C08    153    F 4394    V 1.434    W 8.69    T 68.4    L 1.147
C09    153    F 4394    V 1.434    W 7.46    T 68.71    L 1.188
C10    153    F 4394    V 1.434    W 7.25    T 62.96    L 1.183
C11    153    F 4394    V 1.434    W 7.59    T 71.45    L 1.228
C12    153    F 4394    V 1.434    W 7.54    T 66.13    L 1.205
C13    153    F 4394    V 1.434    W 7.5    T 70.69    L 1.182
C14    153    F 4394    V 1.434    W 7.64    T 66.48    L 1.237
C15    153    F 4394    V 1.434    W 7.65    T 68.91    L 1.216
C16    152    F 4394    V 1.434    W 7.2    T 64.05    L 1.238
Start VID    1050
Start FREQ CCX#1    3800
Start FREQ CCX#2    3625
Vdroop:    4.29%
3825 / 3650 - PASSED
3850 / 3675 - PASSED
3875 / 3700 - PASSED
3900 / 3725 - PASSED
3925 / 3750 - PASSED
3950 / 3775 - PASSED
3975 / 3800 - PASSED
4000 / 3825 - PASSED
4025 / 3850 - PASSED
4025 / 3875 - PASSED
4025 / 3900 - PASSED
P1 PROFILE
VID:    1050mV
CCX#1:    4025MHz
CCX#2:    3900MHz
07:29:38: Stress test stopped.
Cinebench R20 started
Cinebench R20 finished with result: 10354
Voltage: 1.05 V  PPT: 90.2 W  Temperature: 57.9°
07:30:15: Test 5 finished!


CORES ORDER (from the best to the worst)
###    CPPC    VID    FIT
1    C15    С01    С04
2    C14    С05    C11
3    C13    С07    C13
4    C12    С02    С06
5    C11    С03    C15
6    C10    С04    С09
7    С09    С08    С08
8    С08    С06    С02
9    С07    C13    C14
10    С06    C10    C12
11    С05    С09    С03
12    С04    C12    С05
13    С03    C15    C16
14    С02    C11    С07
15    С01    C14    C10
16    C16    C16    С01




AVX light mode
Cycle time: 60000 ms
Reference frequency: 4375MHz
Reference voltage: 1187 mV
Voltage step: 6 mV


Manual overclocking mode enabled
07:30:22: Saving temporary settings...
07:30:27: CCX1 (153): 4375 MHz, 1187 mV
07:30:27: CCX2 (152): 4375 MHz, 1187 mV
07:30:27: Step# 1. Diagnostic VID: 1187 mV
07:30:27: Stress test 1 started...
07:31:02: Stress test stopped.
07:31:03: Stress test 2 started...
07:31:07: Thread# 16 fall down!
07:31:07: Stress test stopped.
07:31:10: Step# 2. Diagnostic VID: 1146 mV


DIAGNOSTIC RESULTS
AMD Ryzen 9 5950X 16-Core Processor
CPU VID: 1146
CPU TEL: 1090
Max temperature: 71,56°
Energy efficient: 4,01
Your CPU is SILVER SAMPLE
Recomended CCX delta: 125
Theoretical maximum CCX delta: 150
Recomended values for overclocking (P1 profile):
Reference voltage: 1050 mV
Reference frequency: 4075 MHz
Recomended values for overclocking (P2 profile):
Reference voltage: 1250 mV
Reference frequency: 4425 MHz
Recomended values for undervolting:
Reference voltage: 1000 mV
Reference frequency: 3975 MHz

Phoenix deactivated!


----------



## Veii

ManniX-ITA said:


> Where do I see in CTR the ACPI quality?


Ty 
Hmm soo RC05 doesn't have an Overboost test button ?
Well the little right rating value, FIT ACPI rating thingy
These ones








I see a huge difference between VID and supplied Telemetry voltage tho
4-5% vdroop
around 50-55mV droop 
Exemplary example








Or:
* if we have too much vdroop (or lack 100mhz of switching freq)








** Sadly Platinum is sub 980mV i think


----------



## ManniX-ITA

Veii said:


> Hmm soo RC05 doesn't have an Overboost test button ?
> Well the little right rating value, FIT ACPI rating thingy


Nope, it's there but disabled

These are the ACPI tags:

00 211
01 216
02 198
03 202
04 216
05 188
06 207
07 193
08 179
09 175
10 161
11 170
12 184
13 156
14 166
15 152


----------



## ManniX-ITA

Veii said:


> I see a huge difference between VID and supplied Telemetry voltage tho
> 4-5% vdroop


Well I have the fake telemetry enabled 

Pretty sure it's messed up in the readings, same as in the logs.


----------



## Veii

ManniX-ITA said:


> Nope, it's there but disabled
> 
> These are the ACPI tags:
> 00 211
> 01 216
> 02 198
> 03 202
> 04 216
> 05 188
> 06 207
> 07 193
> 08 179
> 09 175
> 10 161
> 11 170
> 12 184
> 13 156
> 14 166
> 15 152


Ok 16 cores are really a lot of work
4.85Ghz should be


Code:


00 211 / +20
01 216 / +22 (maybe +23)
02 198 / +13 (maybe +14)
03 202 / +15 (maybe +16)
04 216 / +22 (maybe +23)
05 188 / +8 (maybe +9)
06 207 / +18
07 193 / +11
~unsure how 150mhz CCX delta affects CO values~
08 179 / +4
09 175 / +2
10 161 / -5
11 170 / -1 (maybe 0)
12 184 / +6 (maybe +7)
13 156 / -8 (maybe -7)
14 166 / -3 (maybe -2)
15 152 / -10 (maybe -9)

* Maybe = it lies stupidly in between. Could run, but could also crash, weaker value provided first has to run, but might not hit frequency target
4.95 stock are the same but take away 8 from every value


Code:


00 211 / +12
01 216 / +14 (maybe +15)
02 198 / +5 (maybe +6)
03 202 / +7 (maybe +8)
04 216 / +14 (maybe +15)
05 188 / +0 (maybe +1)
06 207 / +10
07 193 / +3

08 179 / -4
09 175 / -6
10 161 / -13
11 170 / -9 (maybe -8)
12 184 / -3 (maybe -2)
13 156 / -16 (maybe -15)
14 166 / -11 (maybe -10)
15 152 / -18 (maybe -17)

Every 25Mhz more it's -2 CO (negative value gets bigger) = same VID voltage
** this was harder to calculate than i thought. Soo many cores
*** i likely have a little calculation issue of +/- 1 value. Need more samples to build a correct pattern. Depends what is "correct" even or uneven 
**** more VID doesn't mean higher frequency, for me the hardcap is 1.4v VID (for FIT), slightly peaking over it , it throttles back 75mhz ~ else it holds it


----------



## Veii

ManniX-ITA said:


> Well I have the fake telemetry enabled


The ACPI tags where from CTR right ?
A frequency limit will also bug it out - just use HighPerf for a moment and wipe CO values
Set it to scalar X10 just for the readout
Also put Boost Override to 0mhz, so it has to hit 4.95 on all the cores with the values above
No positive or negative offset. Depends how boards fake it. Might need +10 to +15mV to match VID with TEL voltage (on load not on idle)
Depends on the loadline
=================
@XPEHOPE3 i think you are a very replicable testing rabbit with a 5600X 🤭
Please drop some CTR Core Readout (top sensor values without Curve optimizer used) and i want to try giving you a set
Unsure about non 5600X units, but this surely works on your unit. I'm confident on the math


----------



## ManniX-ITA

Veii said:


> A frequency limit will also bug it out - just use HighPerf for a moment and wipe CO values


Yeah forgot that, I have a freq limit on the plan



Veii said:


> Also put Boost Override to 0mhz, so it has to hit 4.95 on all the cores with the values above


Base boost clock is 5.05 for the 5950x
Should I take away another 8 from the counts above?


----------



## Veii

ManniX-ITA said:


> Base boost clock is 5.05 for the 5950x


Are you sure about that ?
Not that 100mhz boost override happens in the hidden








For me it was 4.6, they run 4.65
For the 5800X it is 4.7, they run 4.75 on 0mhz

I think your board is faking 100mhz. It should be 4.95 on stock
The 5900X should boost to 4.85 (rated as 4.8)
Just set Scalar to X10 and Boost override enforce to 0mhz
I really think the boards cheat. ASUS likes to do it too or Gigabyte


ManniX-ITA said:


> Should I take away another 8 from the counts above?


The worst thing that will happen, is FIT throttling back frequency, because CO value is "too high" & VID will be too high = frequency throttle back
If i didn't do any calculation mistake, this target for 4.95 should be correct 


ManniX-ITA said:


> Yeah forgot that, I have a freq limit on the plan


Please doublecheck if the told values match up what CTR reports (without HWInfo, Zentimings or Tool.exe open)
Else i need to redo the values


----------



## ManniX-ITA

Veii said:


> Are you sure about that ?


Fmax is 5050 MHz:












Veii said:


> Please doublecheck if the told values match up what CTR reports (without HWInfo, Zentimings or Tool.exe open)


How to double check what CTR reports? You mean frequency or VIDs?



Veii said:


> The worst thing that will happen, is FIT throttling back frequency, because CO value is "too high" & VID will be too high = frequency throttle back
> If i didn't do any calculation mistake, this target for 4.95 should be correct


I'm testing both, now it's with +8 for 5050MHz.

The ACPI tags got -3/-4 less, not sure what changed it.

The math seems to work.












Code:


09:20:21: Boost testing started!
09:21:59: Boost testing finished!
09:21:59: Cinebench stopped!


CTR BOOST TESTER RESULTS (test version)
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4754    V 1.414    W 11.89    T 58.96
C02    F 4824    V 1.438    W 12.94    T 61.72
C03    F 4746    V 1.404    W 11.84    T 58.04
C04    F 4748    V 1.402    W 11.73    T 58.49
C05    F 4820    V 1.444    W 13.16    T 61.21
C06    F 4741    V 1.39    W 11.41    T 57.12
C07    F 4759    V 1.404    W 12    T 59.49
C08    F 4620    V 1.454    W 12.56    T 62.56
C09    F 4682    V 1.446    W 11.72    T 62.07
C10    F 4698    V 1.454    W 11.88    T 60.71
C11    F 4713    V 1.44    W 11.65    T 59.77
C12    F 4686    V 1.443    W 11.9    T 60.99
C13    F 4696    V 1.453    W 11.9    T 60.5
C14    F 4710    V 1.444    W 11.66    T 59.83
C15    F 4688    V 1.44    W 11.68    T 61.2
C16    F 4700    V 1.44    W 11.68    T 61.7




Spoiler: Co counts 5050


----------



## ManniX-ITA

This is Boost tester with 4.95 GHz values.
In general higher VIDs, as expected, and less boost clock even at same VID



Code:


CTR BOOST TESTER RESULTS (test version)
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4676    V 1.437    W 12.53    T 60.76
C02    F 4728    V 1.462    W 13.48    T 62.56
C03    F 4586    V 1.474    W 13.22    T 62.94
C04    F 4692    V 1.411    W 12.04    T 58.94
C05    F 4756    V 1.458    W 13.51    T 62.1
C06    F 4690    V 1.398    W 11.71    T 57.6
C07    F 4710    V 1.414    W 12.16    T 59.89
C08    F 4682    V 1.402    W 11.75    T 59.4
C09    F 4632    V 1.448    W 11.7    T 61.64
C10    F 4647    V 1.457    W 11.88    T 60.46
C11    F 4656    V 1.441    W 11.68    T 59.56
C12    F 4618    V 1.449    W 11.84    T 61.37
C13    F 4650    V 1.454    W 11.86    T 60.3
C14    F 4660    V 1.445    W 11.71    T 59.56
C15    F 4628    V 1.449    W 11.86    T 61.5
C16    F 4650    V 1.442    W 11.62    T 61.66


----------



## Veii

ManniX-ITA said:


> Fmax is 5050 MHz:


Yes as the bios does trickery. It should be 4950 
Let me remake the 4.95 set & then maybe make another 5.05
But i am not sure how the 2nd CCD affects the result ~ because CCX Delta is a thing & i just frequency match
Currently i can see that the values nearly exceed 1.45v

At least V-TEL to VID is fine, 5mV difference ~ unsure about load


ManniX-ITA said:


> In general higher VIDs, as expected, and less boost clock even at same VID


Compare it to this
4.95 Set


Spoiler: 4.95Ghz Target_Stock






Code:


00 208 / +18 (maybe +19)
01 212 / +20 (maybe +21)
02 194 / +11 (maybe +22)
03 199 / +14
04 212 / +20 (maybe +21)
05 185 / +7
06 203 / +16
07 190 / +9 (maybe +10)

08 176 / +2 (maybe +3)
09 172 / 0 (maybe +1)
10 158 / -7 (maybe -8)
11 167 / -2
12 181 / +5
13 154 / -9 (maybe -8)
14 163 / -4
15 149 / -11







Spoiler: 5.05Ghz Target






Code:


00 208 / +10 (maybe +11)
01 212 / +12 (maybe +13)
02 194 / +3 (maybe +4)
03 199 / +6
04 212 / +12 (maybe +13)
05 185 / -1
06 203 / +8
07 190 / +1 (maybe +2)

08 176 / -4 (maybe -3)
09 172 / -8 (maybe -7)
10 158 / -15 (maybe -14)
11 167 / -10
12 181 / -3
13 154 / -17 (maybe -16)
14 163 / -12
15 149 / -19


----------



## ManniX-ITA

This is Boost Tester with new 4.95 GHz values.

Of course I have wrongly set negative count for C05.
Are you sure we shouldn't target the opposite magnitude?



Code:


CTR BOOST TESTER RESULTS (test version)
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4628    V 1.442    W 12.3    T 61.08
C02    F 4543    V 1.48    W 13.42    T 64.78
C03    F 4658    V 1.416    W 12.09    T 59.23
C04    F 4652    V 1.416    W 12.08    T 59.37
C05    F 4976    V 1.457    W 14    T 62.96
C06    F 4652    V 1.404    W 11.64    T 57.94
C07    F 4664    V 1.428    W 12.26    T 60.74
C08    F 4640    V 1.416    W 12.06    T 59.76
C09    F 4592    V 1.45    W 11.38    T 61.29
C10    F 4605    V 1.451    W 11.66    T 60.51
C11    F 4622    V 1.449    W 11.68    T 59.78
C12    F 4600    V 1.452    W 11.82    T 60.61
C13    F 4511    V 1.476    W 11.61    T 61.42
C14    F 4481    V 1.481    W 11.71    T 62.32
C15    F 4600    V 1.445    W 11.6    T 61.15
C16    F 4550    V 1.458    W 11.8    T 62.02

This is the fixed version (with an error, c16 was set at -1 instead of -11):



Code:


CTR BOOST TESTER RESULTS (test version)
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4645    V 1.436    W 12.38    T 60.9
C02    F 4700    V 1.466    W 13.55    T 64.11
C03    F 4656    V 1.416    W 12.18    T 59.36
C04    F 4658    V 1.416    W 12.2    T 58.67
C05    F 4712    V 1.468    W 13.92    T 62.94
C06    F 4644    V 1.412    W 11.78    T 58.4
C07    F 4673    V 1.426    W 12.33    T 60.6
C08    F 4649    V 1.413    W 12.1    T 59.7
C09    F 4594    V 1.45    W 11.46    T 61.18
C10    F 4606    V 1.45    W 11.66    T 60.47
C11    F 4508    V 1.486    W 12.18    T 61.95
C12    F 4499    V 1.478    W 11.99    T 61.05
C13    F 4582    V 1.454    W 11.72    T 60.95
C14    F 4616    V 1.447    W 11.62    T 58.73
C15    F 4600    V 1.446    W 11.78    T 61
C16    F 4550    V 1.458    W 11.78    T 61.97


----------



## Veii

Yes, it totally VID throttles back, by being too high 
Well, you know what to do
Scale it up, all of them -2 and then again -2 and again -2 , till it's unstable and cores crash by undervoltage

Technically and easier would be to somewhere gather RC06 and just run a baseline run
That will give you a good baseline to copy


Spoiler: Example Here [Once you copy the scaling]






Code:


23:20:53: Test#1
23:21:52: Test#2

23:22:54: Step: 7
CCX1 FREQ 4200MHz
PX HIGH OB: -13
PX MID OB: -13
PX LOW OB: -12
P2 CCX1 OB: -2
P1 CCX1 OB: -2

Curve Optimizer
C01    3
C02    3
C03    3
C04    3
C05    3
C06    3

23:23:03: Test#1
23:24:01: Test#2

23:25:04: Step: 8
CCX1 FREQ 4225MHz
PX HIGH OB: -7
PX MID OB: -7
PX LOW OB: -7
P2 CCX1 OB: 3
P1 CCX1 OB: 3

Curve Optimizer
C01    1
C02    1
C03    1
C04    1
C05    1
C06    1

23:25:12: Test#1
23:26:12: Test#2

23:27:14: Step: 9
CCX1 FREQ 4250MHz
PX HIGH OB: -3
PX MID OB: -2
PX LOW OB: -1
P2 CCX1 OB: 9
P1 CCX1 OB: 9

Curve Optimizer
C01    0
C02    0
C03    0
C04    0
C05    -1
C06    0

23:27:23: Test#1
23:28:21: Test#2

23:29:25: Step: 10
CCX1 FREQ 4275MHz
PX HIGH OB: 3
PX MID OB: 4
PX LOW OB: 5
P2 CCX1 OB: 15
P1 CCX1 OB: 15

Curve Optimizer
C01    -2
C02    -2
C03    -1
C04    -2
C05    -2
C06    -1

23:29:33: Test#1
23:30:33: Test#2
23:31:23: CCX1 instability detected!

I had a bit of variance between cores at first, as you can see ~ but figured it out
No CoreCycler required or positive offset shenanigans 


It will keep going downwards and downwards
The overboost mechanism i nearly got nailed down too
But the CO values, only thing that i question ~ is how dual CCDs scale
The stepping & ruleset remains per CCD, but two CCDs have a delta between them. Between 125-175Mhz
Soo it can be, that CO value baseline changes ~ because the frequency baseline changes

I think tho it is overthinking,
Because CO is frequency and quality based ~ soo when the target frequency is the same target
The CO will be the same ~ just needs to be tested after when cores can't make it

Here is the little "cheat-sheet"
I'll head to bed now ~ been a long night 🛌
Let me know how far you can scale them
Craxton is right that "bad cores, need a different magnitude in the opposite direction"


Spoiler: Enjoy :)


----------



## ManniX-ITA

This is with the 5.05GHz set:



Code:


CTR BOOST TESTER RESULTS (test version)
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4699    V 1.425    W 12.1    T 60.64
C02    F 4722    V 1.457    W 13.23    T 64.16
C03    F 4694    V 1.412    W 11.94    T 59.17
C04    F 4698    V 1.404    W 11.77    T 59.36
C05    F 4772    V 1.456    W 13.83    T 62.34
C06    F 4698    V 1.399    W 11.5    T 57.66
C07    F 4724    V 1.414    W 12.07    T 60.33
C08    F 4690    V 1.4    W 11.96    T 59.41
C09    F 4614    V 1.453    W 11.52    T 61.64
C10    F 4656    V 1.45    W 11.78    T 60.88
C11    F 4669    V 1.446    W 11.72    T 60.22
C12    F 4644    V 1.452    W 11.82    T 60.83
C13    F 4572    V 1.479    W 11.98    T 61.05
C14    F 4551    V 1.479    W 11.94    T 62.27
C15    F 4638    V 1.446    W 11.68    T 61.7
C16    F 4654    V 1.443    W 11.65    T 61.98


----------



## Veii

ManniX-ITA said:


> This is with the 5.05GHz set:
> 
> 
> 
> Code:
> 
> 
> CTR BOOST TESTER RESULTS (test version)
> CORE / FREQUENCY / VID / POWER / TEMP
> C01    F 4699    V 1.425    W 12.1    T 60.64
> C02    F 4722    V 1.457    W 13.23    T 64.16
> C03    F 4694    V 1.412    W 11.94    T 59.17
> C04    F 4698    V 1.404    W 11.77    T 59.36
> C05    F 4772    V 1.456    W 13.83    T 62.34
> C06    F 4698    V 1.399    W 11.5    T 57.66
> C07    F 4724    V 1.414    W 12.07    T 60.33
> C08    F 4690    V 1.4    W 11.96    T 59.41
> C09    F 4614    V 1.453    W 11.52    T 61.64
> C10    F 4656    V 1.45    W 11.78    T 60.88
> C11    F 4669    V 1.446    W 11.72    T 60.22
> C12    F 4644    V 1.452    W 11.82    T 60.83
> C13    F 4572    V 1.479    W 11.98    T 61.05
> C14    F 4551    V 1.479    W 11.94    T 62.27
> C15    F 4638    V 1.446    W 11.68    T 61.7
> C16    F 4654    V 1.443    W 11.65    T 61.98


Keep scaling 
I think you have to hold between 1.3785-1.4v
I remember 1.3875v-VID allowed for 5ghz to be held
Less VID, higher potential allowed Freq

Try to use the same pattern you got from me and see when you start to crash 
Might not use personal powerplans for such , but idk ~ you'll see
On Freq they look nearly identical, except little exceptions on C14,C09,C13 - which all seem to throttle
C08 looks ok, but it might also be throttling
Yes, keep upscaling - and later once you are beyond 5ghz, check the "maybe" part. They just sit in between, i can't say +/- 1 value what is correct, soo i picked the "will lkeep stability" value


----------



## spajdr

craxton said:


> it depends on "how" your going to look at it, are you getting "dropout" issues with USB stuff?
> random audio crackles at higher than X fclk? if no, then your "!CAN!" use
> this only on "win 10" atm, to shut it up. if your ok with that. you can remove it as well.
> as ive used it recently on my 5800x as it doesnt like over 1900fclk, to which, unsure if it was voltages
> or what but i had MAJOR issues with fclk above X limit with "display cutouts, mouse/USB drives dropping out, speakers crackling etc"
> 
> so lost cause to "fix" for now seems so, lost cause to "IGNORE" not entirely


Thanks a lot for the reply.
Thing is I would keep FCLK 1900, but I seem to lost a noticeable boost in some benchmarks/games when I had FCLK 2000
(FFXIV benchmark at 1080P MAX settings 27400 points, now I can't get more than 24000 points at 1900FLCK)
But I'm not sure if that's the main reason or something I have set with RAM settings did this.
As for the USB issues during WHEA errors, I noticed really sluggish mouse movement sometimes.


----------



## Kurt Krampmeier

Veii said:


> I had a bit of variance between cores at first, as you can see ~ but figured it out
> No CoreCycler required or positive offset shenanigans [/SPOILER]It will keep going downwards and downwards
> The overboost mechanism i nearly got nailed down too
> But the CO values, only thing that i question ~ is how dual CCDs scale
> The stepping & ruleset remains per CCD, but two CCDs have a delta between them. Between 125-175Mhz
> Soo it can be, that CO value baseline changes ~ because the frequency baseline changes





Spoiler: RC6 Diag



*ClockTuner for Ryzen 2.1 RC6(ver.24) by 1usmus*
PUBLIC EDITION
AMD Ryzen 9 5900X 12-Core Processor
ASUS ROG STRIX B450-F GAMING II
BIOS ver. 4402 SMU ver. 56.53.00
TABLE ver. 3672069
DRAM speed 3600 MHz
07/06/2021 08:31:46


P1
FREQ CCX1# 4525MHz
FREQ CCX2# 4375MHz
VID# 1175mV
Usage trigger# 81%
OB CCX1# -33
OB CCX2# -87
P2
FREQ CCX1# 4650MHz
FREQ CCX2# 4475MHz
VID# 1275mV
Usage trigger# 29%
OB CCX1# -33
OB CCX2# -87
PX
FREQ HIGH# 4875MHz
FREQ MID# 4750MHz
FREQ LOW# 4700MHz
VID HIGH# 1400mV
VID MID# 1375mV
VID LOW# 1350mV
OB HIGH# -50
OB MID# -46
OB LOW# -43
Usage trigger# 12%
PX OB LIMIT# 100MHz


HYBRID OC enabled!
P1 PROFILE successfully activated!
P2 PROFILE successfully activated!
PX PROFILE successfully activated!
Recommended to use the manual CPU LLC!
ASUS - Level 3
MSI - Mode 4
Gigabyte - High
Asrock - Level 2
Phoenix ready!
Cinebench R20 started
Cinebench R20 finished with result: 7778
Voltage: 1.182 V PPT: 141.6 W Temperature: 65.8°
08:33:25: Test 1 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP
C01 174 F 4738 V 1.414 W 15.23 T 65.53
C02 170 F 54 V 1.414 W 2.77 T 44.62
C03 162 F 46 V 1.414 W 2.92 T 46.94
C04 174 F 4738 V 1.414 W 15.6 T 69.24
C05 158 F 55 V 1.414 W 2.61 T 42.49
C06 166 F 60 V 1.414 W 3.14 T 50.55
C07 141 F 104 V 1.414 W 0.91 T 36.83
C08 150 F 120 V 1.414 W 0.9 T 34.34
C09 137 F 58 V 1.414 W 0.9 T 38.45
C10 154 F 100 V 1.414 W 0.84 T 34.78
C11 133 F 216 V 1.414 W 1.14 T 38.86
C12 145 F 110 V 1.414 W 0.91 T 34.77
Vdroop: 0%
4700 - PASSED 1.239
4725 - PASSED 1.255
4750 - PASSED 1.272
4775 - PASSED 1.287
4800 - PASSED 1.307
4825 - PASSED 1.325
4850 - PASSED 1.346
4875 - PASSED 1.367
08:33:51: Cinebench stopped!
PX HIGH sub-profile
CPU usage(min): 8.3%
CPU usage(avg): 8.71%
CPU usage(max): 11.3%
SAFE: 4875MHz
FAST: 4925MHz
08:33:51: Test 1 finished!
08:33:51: Test 2 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP
C01 174 F 4644 V 1.396 W 14.24 T 63.72
C02 170 F 4644 V 1.396 W 14.7 T 69.28
C03 162 F 56 V 1.396 W 2.86 T 47.3
C04 174 F 4644 V 1.396 W 15.58 T 74.84
C05 158 F 86 V 1.396 W 2.66 T 43.26
C06 166 F 4638 V 1.396 W 15.53 T 76.13
C07 141 F 170 V 1.396 W 1.08 T 39.94
C08 150 F 134 V 1.396 W 0.91 T 34.82
C09 137 F 60 V 1.396 W 0.92 T 41.62
C10 154 F 103 V 1.396 W 0.9 T 35.22
C11 133 F 290 V 1.396 W 1.32 T 42.3
C12 145 F 260 V 1.396 W 1.12 T 35.51
Vdroop: 0%
4600 - PASSED 1.21
4625 - PASSED 1.228
4650 - PASSED 1.245
4675 - PASSED 1.269
4700 - PASSED 1.295
4725 - PASSED 1.319
4750 - PASSED 1.343
08:34:16: Cinebench stopped!
PX MID sub-profile
CPU usage(min): 16.7%
CPU usage(avg): 17.17%
CPU usage(max): 19%
SAFE: 4750MHz
FAST: 4825MHz
Max CPU usage for PX MID: 20%
08:34:16: Test 2 finished!
08:34:16: Test 3 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP
C01 174 F 4606 V 1.37 W 14.1 T 68.26
C02 170 F 4606 V 1.37 W 14.54 T 68.79
C03 162 F 4606 V 1.37 W 13.94 T 69.66
C04 174 F 4606 V 1.37 W 14.9 T 75.57
C05 158 F 4606 V 1.37 W 14.32 T 69.46
C06 166 F 4606 V 1.37 W 15.37 T 77.06
C07 141 F 98 V 1.37 W 0.9 T 39.79
C08 150 F 133 V 1.37 W 0.85 T 34.48
C09 137 F 63 V 1.37 W 0.9 T 41.68
C10 154 F 95 V 1.37 W 0.79 T 34.83
C11 133 F 253 V 1.37 W 1.12 T 42.18
C12 145 F 124 V 1.37 W 0.86 T 34.83
Vdroop: 0%
4550 - PASSED 1.182
4575 - PASSED 1.198
4600 - PASSED 1.217
4625 - PASSED 1.233
4650 - PASSED 1.249
4675 - PASSED 1.273
4700 - PASSED 1.293
4725 - PASSED 1.316
08:34:41: Cinebench stopped!
PX LOW sub-profile
CPU usage(min): 25%
CPU usage(avg): 25.18%
CPU usage(max): 28.6%
SAFE: 4725MHz
FAST: 4800MHz
Max CPU usage for PX LOW: 29%
08:34:41: Test 3 finished!
08:34:41: Test 4 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP
C01 174 F 4078 V 1.178 W 10.4 T 58.83
C02 170 F 4078 V 1.178 W 10.56 T 60.32
C03 162 F 4078 V 1.178 W 10.44 T 59.72
C04 174 F 4078 V 1.178 W 10.8 T 65.03
C05 158 F 4078 V 1.178 W 10.41 T 57.58
C06 166 F 4078 V 1.178 W 10.82 T 65.16
C07 141 F 4078 V 1.178 W 7.71 T 52.88
C08 150 F 4078 V 1.178 W 7.82 T 53.74
C09 137 F 4078 V 1.178 W 7.96 T 57.89
C10 154 F 4078 V 1.178 W 7.89 T 56.32
C11 133 F 4078 V 1.178 W 7.91 T 57.88
C12 145 F 4078 V 1.178 W 7.88 T 55.58
Start VID 1275
Start FREQ CCX#1 4350
Start FREQ CCX#2 4275
Vdroop: 0%
4375 / 4300 - PASSED
4400 / 4325 - PASSED
4425 / 4350 - PASSED
4450 / 4375 - PASSED
4475 / 4400 - PASSED
4500 / 4425 - PASSED
4525 / 4450 - PASSED
4550 / 4475 - PASSED
4575 / 4475 - PASSED
4600 / 4475 - PASSED
4625 / 4475 - PASSED
4650 / 4475 - PASSED
4625 / 4475 - PASSED
P2 PROFILE
VID: 1275mV
CCX#1: 4625MHz
CCX#2: 4475MHz
08:35:01: Cinebench stopped!
08:35:01: Test 4 finished!
08:35:01: Test 5 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP
C01 174 F 4102 V 1.186 W 10.49 T 58.86
C02 170 F 4102 V 1.186 W 10.79 T 60.68
C03 162 F 4102 V 1.186 W 10.58 T 59.51
C04 174 F 4102 V 1.186 W 11.08 T 65.03
C05 158 F 4102 V 1.186 W 10.55 T 58.12
C06 166 F 4102 V 1.186 W 11.18 T 65.82
C07 141 F 4102 V 1.186 W 7.7 T 53.18
C08 150 F 4102 V 1.186 W 8.06 T 54.5
C09 137 F 4102 V 1.186 W 7.95 T 57.51
C10 154 F 4102 V 1.186 W 8.02 T 56.85
C11 133 F 4102 V 1.186 W 7.98 T 58.36
C12 145 F 4102 V 1.186 W 7.99 T 56.2
Start VID 1175
Start FREQ CCX#1 4150
Start FREQ CCX#2 4075
Vdroop: 0%
4175 / 4100 - PASSED
4200 / 4125 - PASSED
4225 / 4150 - PASSED
4250 / 4175 - PASSED
4275 / 4200 - PASSED
4300 / 4225 - PASSED
4325 / 4250 - PASSED
4350 / 4275 - PASSED
4375 / 4300 - PASSED
4400 / 4325 - PASSED
4425 / 4350 - PASSED
4450 / 4375 - PASSED
4475 / 4375 - PASSED
4500 / 4375 - PASSED
4525 / 4375 - PASSED
4525 / 4375 - PASSED
P1 PROFILE
VID: 1175mV
CCX#1: 4525MHz
CCX#2: 4375MHz
08:35:22: Cinebench stopped!
Cinebench R20 started
Cinebench R20 finished with result: 8418
Voltage: 1.175 V PPT: 147.8 W Temperature: 68.6°
08:36:05: Test 5 finished!


08:36:08: OB test started!
This test can reboot the system!
There is no need to worry, it's safe.
The testing process may take some time.


08:36:11: Step: 1
CCX1 FREQ 4075MHz
CCX2 FREQ 3975MHz
PX HIGH OB: -78
PX MID OB: -75
PX LOW OB: -73
P2 CCX1 OB: -63
P2 CCX2 OB: -59
P1 CCX1 OB: -63
P1 CCX2 OB: -59


Curve Optimizer
C01 20 C07 17
C02 19 C08 19
C03 18 C09 17
C04 19 C10 19
C05 18 C11 20
C06 18 C12 21


08:36:16: Test#1
08:37:16: Test#2


08:38:20: Step: 2
CCX1 FREQ 4100MHz
CCX2 FREQ 4000MHz
PX HIGH OB: -71
PX MID OB: -67
PX LOW OB: -67
P2 CCX1 OB: -56
P2 CCX2 OB: -52
P1 CCX1 OB: -56
P1 CCX2 OB: -52


Curve Optimizer
C01 18 C07 15
C02 17 C08 17
C03 16 C09 15
C04 17 C10 18
C05 16 C11 18
C06 16 C12 20


08:38:28: Test#1
08:39:28: Test#2


08:40:32: Step: 3
CCX1 FREQ 4125MHz
CCX2 FREQ 4025MHz
PX HIGH OB: -65
PX MID OB: -59
PX LOW OB: -59
P2 CCX1 OB: -49
P2 CCX2 OB: -43
P1 CCX1 OB: -49
P1 CCX2 OB: -43


Curve Optimizer
C01 17 C07 13
C02 15 C08 15
C03 15 C09 13
C04 16 C10 16
C05 14 C11 16
C06 15 C12 18


08:40:40: Test#1
08:41:40: Test#2


08:42:44: Step: 4
CCX1 FREQ 4150MHz
CCX2 FREQ 4050MHz
PX HIGH OB: -57
PX MID OB: -53
PX LOW OB: -51
P2 CCX1 OB: -41
P2 CCX2 OB: -36
P1 CCX1 OB: -41
P1 CCX2 OB: -36


Curve Optimizer
C01 15 C07 11
C02 14 C08 14
C03 13 C09 11
C04 14 C10 14
C05 12 C11 14
C06 13 C12 16


08:42:52: Test#1
08:43:51: Test#2


08:44:56: Step: 5
CCX1 FREQ 4175MHz
CCX2 FREQ 4075MHz
PX HIGH OB: -50
PX MID OB: -45
PX LOW OB: -43
P2 CCX1 OB: -33
P2 CCX2 OB: -29
P1 CCX1 OB: -33
P1 CCX2 OB: -29


Curve Optimizer
C01 13 C07 9
C02 12 C08 12
C03 11 C09 9
C04 12 C10 12
C05 10 C11 12
C06 11 C12 14


08:45:04: Test#1
08:46:04: Test#2


08:47:08: Step: 6
CCX1 FREQ 4200MHz
CCX2 FREQ 4100MHz
PX HIGH OB: -42
PX MID OB: -38
PX LOW OB: -36
P2 CCX1 OB: -26
P2 CCX2 OB: -20
P1 CCX1 OB: -26
P1 CCX2 OB: -20


Curve Optimizer
C01 11 C07 8
C02 10 C08 10
C03 9 C09 7
C04 10 C10 10
C05 9 C11 10
C06 9 C12 13


08:47:16: Test#1
08:48:16: Test#2


08:49:20: Step: 7
CCX1 FREQ 4225MHz
CCX2 FREQ 4125MHz
PX HIGH OB: -35
PX MID OB: -30
PX LOW OB: -29
P2 CCX1 OB: -19
P2 CCX2 OB: -11
P1 CCX1 OB: -19
P1 CCX2 OB: -11


Curve Optimizer
C01 9 C07 5
C02 8 C08 8
C03 7 C09 5
C04 8 C10 8
C05 7 C11 8
C06 7 C12 11


08:49:28: Test#1
08:49:48: CCX2 instability detected!
08:49:48: Thread# 12 dropped!
08:49:48: Stress test stopped.
CCX1 FREQ 4225MHz
CCX2 FREQ 4100MHz


PX HIGH OB: -35
PX MID OB: -30
PX LOW OB: -29
P2 CCX1 OB: -19
P2 CCX2 OB: -20
P1 CCX1 OB: -19
P1 CCX2 OB: -20


Curve Optimizer
C01 9 C07 7
C02 8 C08 10
C03 7 C09 7
C04 8 C10 10
C05 7 C11 10
C06 7 C12 13


08:49:57: Test#1
08:50:56: Test#2


08:52:01: Step: 8
CCX1 FREQ 4250MHz
CCX2 FREQ 4100MHz
PX HIGH OB: -28
PX MID OB: -23
PX LOW OB: -21
P2 CCX1 OB: -11
P2 CCX2 OB: -20
P1 CCX1 OB: -11
P1 CCX2 OB: -20


Curve Optimizer
C01 8 C07 7
C02 6 C08 10
C03 5 C09 7
C04 7 C10 10
C05 5 C11 10
C06 5 C12 12


08:52:09: Test#1
08:53:08: Test#2


08:54:12: Step: 9
CCX1 FREQ 4275MHz
CCX2 FREQ 4100MHz
PX HIGH OB: -21
PX MID OB: -15
PX LOW OB: -14
P2 CCX1 OB: -4
P2 CCX2 OB: -20
P1 CCX1 OB: -4
P1 CCX2 OB: -20


Curve Optimizer
C01 5 C07 7
C02 4 C08 10
C03 3 C09 7
C04 5 C10 10
C05 3 C11 10
C06 3 C12 13


08:54:21: Test#1
08:55:20: Test#2


08:56:24: Step: 10
CCX1 FREQ 4300MHz
CCX2 FREQ 4100MHz
PX HIGH OB: -13
PX MID OB: -8
PX LOW OB: -7
P2 CCX1 OB: 3
P2 CCX2 OB: -20
P1 CCX1 OB: 3
P1 CCX2 OB: -20


Curve Optimizer
C01 4 C07 8
C02 3 C08 10
C03 1 C09 7
C04 3 C10 10
C05 1 C11 10
C06 1 C12 13


08:56:33: Test#1
08:57:32: Test#2


08:58:36: Step: 11
CCX1 FREQ 4325MHz
CCX2 FREQ 4100MHz
PX HIGH OB: -6
PX MID OB: -1
PX LOW OB: 1
P2 CCX1 OB: 11
P2 CCX2 OB: -20
P1 CCX1 OB: 11
P1 CCX2 OB: -20


Curve Optimizer
C01 2 C07 7
C02 1 C08 10
C03 0 C09 7
C04 1 C10 10
C05 -1 C11 10
C06 0 C12 13


08:58:45: Test#1
08:59:44: Test#2


09:00:48: Step: 12
CCX1 FREQ 4350MHz
CCX2 FREQ 4100MHz
PX HIGH OB: 1
PX MID OB: 7
PX LOW OB: 9
P2 CCX1 OB: 19
P2 CCX2 OB: -20
P1 CCX1 OB: 19
P1 CCX2 OB: -20


Curve Optimizer
C01 0 C07 7
C02 -1 C08 10
C03 -2 C09 7
C04 -1 C10 10
C05 -3 C11 10
C06 -2 C12 13


09:00:57: Test#1
09:01:56: Test#2


09:03:00: Step: 13
CCX1 FREQ 4375MHz
CCX2 FREQ 4100MHz
PX HIGH OB: 9
PX MID OB: 15
PX LOW OB: 17
P2 CCX1 OB: 27
P2 CCX2 OB: -20
P1 CCX1 OB: 27
P1 CCX2 OB: -20


Curve Optimizer
C01 -2 C07 7
C02 -3 C08 10
C03 -4 C09 7
C04 -3 C10 10
C05 -5 C11 10
C06 -4 C12 13


09:03:08: Test#1
09:04:08: Test#2


09:05:12: Step: 14
CCX1 FREQ 4400MHz
CCX2 FREQ 4100MHz
PX HIGH OB: 17
PX MID OB: 23
PX LOW OB: 25
P2 CCX1 OB: 35
P2 CCX2 OB: -20
P1 CCX1 OB: 35
P1 CCX2 OB: -20


Curve Optimizer
C01 -3 C07 7
C02 -5 C08 10
C03 -6 C09 7
C04 -5  C10 10
C05 -7 C11 10
C06 -6 C12 13


09:05:21: Test#1
09:05:55: CCX1 instability detected!
09:05:55: Thread# 3 dropped!
09:05:55: Stress test stopped.
CCX1 FREQ 4375MHz
CCX2 FREQ 4100MHz


PX HIGH OB: 9
PX MID OB: 14
PX LOW OB: 17
P2 CCX1 OB: 27
P2 CCX2 OB: -20
P1 CCX1 OB: 27
P1 CCX2 OB: -20


Curve Optimizer
C01 -2 C07 7
C02 -3 C08 10
C03 -4 C09 7
C04 -3 C10 10
C05 -5 C11 11
C06 -4 C12 13


09:06:03: Test#1
09:07:03: Test#2


Results OB testing
PX HIGH OB: 9
PX MID OB: 14
PX LOW OB: 17
P2 CCX1 OB: 27
P2 CCX2 OB: -20
P1 CCX1 OB: 27
P1 CCX2 OB: -20






CORES ORDER (from the best to the worst)
### CPPC VID FIT
1 С04 С01 С06
2 С01 С02 С04
3 С02 С04 С02
4 С06 С03 С03
5 С03 С05 С01
6 С05 С06 C11
7 C10 C12 С05
8 С08 C11 С09
9 C12 C10 C10
10 С07 С08 C12
11 С09 С07 С08
12 C11 С09 С07




AVX light mode
Cycle time: 60000 ms
Reference frequency: 4375MHz
Reference voltage: 1187 mV
Voltage step: 6 mV


Manual overclocking mode enabled
09:08:12: Saving temporary settings...
09:08:17: CCX1 (158): 4375 MHz, 1187 mV
09:08:17: CCX2 (133): 4375 MHz, 1187 mV
09:08:17: Step# 1. Diagnostic VID: 1187 mV
09:08:17: Stress test 1 started...



maybe you find something useful in there.


----------



## ManniX-ITA

Sleep well 

Problem with 2 CCDs is indeed the delta but also the concurrent usage.
If you flatten you have to go down a lot.
My CCDs in all-core can't keep up more than 4.7/4.6 due to thermals.
First CCD could easy go to 4.85 but any usage on the 2nd and would crash.
TM5 is usually starting at 4.6 and going down to 4.55/4.58 in all core.


----------



## PJVol

Veii said:


> Here is the little "cheat-sheet"


Is this CO test thingy in a publicly unrealeased CTR version or it's there in the latest available one?


----------



## ManniX-ITA

PJVol said:


> Is this CO test is a publicly unrealeased CTR version thing or it's there in the latest available version?


Only in the RC6 for Patreon


----------



## Veii

Kurt Krampmeier said:


> maybe you find something useful in there.





Spoiler: Results Demystified






Code:


Krapmeier's 5900X

CCX1
FREQ 4100MHz

C01 18
C02 17
C03 16
C04 17
C05 16
C06 16

FREQ 4125MHz

C01 17
C02 15
C03 15
C04 16
C05 14
C06 15

FREQ 4150Mhz

C01 15
C02 14
C03 13
C04 14
C05 12
C06 13

FREQ 4200MHz

C01 11
C02 10
C03 9
C04 10
C05 9
C06 9

FREQ 4300MHz (+100Mhz , -8 CO)

C01 4
C02 3 (should've been 2)
C03 1
C04 3
C05 1
C06 1

FREQ 4400MHz

C01 -3
C02 -5 (error ~ should've been -6)
C03 -6 (usually also -7)
C04 -5
C05 -7
C06 -6

Fallback to
FREQ 4375MHz (-25mhz, 2 CO ontop again)

C01 -2
C02 -3
C03 -4
C04 -3
C05 -5
C06 -4
=================================
CCX2
FREQ 4000MHz
C07 15
C08 17
C09 15
C10 18
C11 18
C12 20

FREQ 4025MHz
C07 13
C08 15
C09 13
C10 16
C11 16
C12 18

FREQ 4050MHz
C07 11
C08 14
C09 11
C10 14
C11 14
C12 16

FREQ 4100MHz (+50mhz, -4 CO)
C07 8
C08 10
C09 7
C10 10
C11 10
C12 13

FREQ 4125MHz
C07 5 crash (should've been a +6 not a +5)
C08 8
C09 5
C10 8
C11 8
C12 11

Fallback to
REQ 4100MHz (-25mhz, 2 CO ontop again)
C07 7
C08 10
C09 7
C10 10
C11 10
C12 12







Spoiler: Math






Code:


RESULT:
CCX1 FREQ 4375MHz
CCX2 FREQ 4100MHz

C01 -2 / C07 +7
C02 -3 / C08 +10
C03 -4 / C09 +7
C04 -3 / C10 +10
C05 -5 / C11 +10
C06 -4 / C12 +12

Requirement for CCX2 to reach 4375 = -24 CO
Soo Result would be:
C01 -2 / C07 -7
C02 -3 / C08 -14
C03 -4 / C09 -17
C04 -3 / C10 -14
C05 -5 / C11 -14
C06 -4 / C12 -12

Then you just scale up
-13 negative CO remaining as max = -12 = +100Mhz & +25mhz
= Peak result for CCX 2 = 4.5Ghz allcore freq @
C07 -20
C08 -27
C09 -30
C10 -27
C11 -27
C12 -25

-12 for CCX 1 to reach 4.5 =
C01 -14
C02 -16
C03 -15
C04 -16
C05 -18
C06 -17







Code:


RESULT:

C01 -14 / C07 -20
C02 -16 / C08 -27
C03 -15 / C09 -30
C04 -16 / C10 -27
C05 -18 / C11 -27
C06 -17 / C12 -25

as input for the BIOS to Overdrive CTR 
* +/- 1 value of the threads that where crashing. But math remains identical
Hope Yuri hurries up with Hydra , soo we don't have to do it by hand
Tho overdriving Hydra surely (w)could work 
** if you've shared the Core ACPI values, you can then match quality to it too
~ CTR can't get it perfect without extended testing
X = 4 ACPI higher = +2 CO
X = 4 ACPI values weaker = -2 CO
According to:


Veii said:


> Spoiler: Enjoy :)


----------



## ManniX-ITA

This is the Boost Tester with my usual CO:



Code:


CTR BOOST TESTER RESULTS (test version)
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4870    V 1.384    W 11.53    T 58.86
C02    F 4956    V 1.429    W 13.11    T 62.88
C03    F 4852    V 1.371    W 11.26    T 57.04
C04    F 4890    V 1.37    W 11.31    T 57.82
C05    F 4986    V 1.448    W 13.59    T 61.72
C06    F 4858    V 1.358    W 10.81    T 56.09
C07    F 4952    V 1.392    W 12.32    T 60.18
C08    F 4856    V 1.359    W 10.98    T 57.82
C09    F 4768    V 1.429    W 11.52    T 61.32
C10    F 4684    V 1.438    W 11.55    T 59.08
C11    F 4755    V 1.426    W 11.94    T 61.1
C12    F 4690    V 1.439    W 11.59    T 60.44
C13    F 4798    V 1.43    W 11.54    T 59.06
C14    F 4734    V 1.432    W 11.52    T 59.66
C15    F 4762    V 1.426    W 11.63    T 61.54
C16    F 4718    V 1.428    W 11.48    T 61.24

The problem I see in creating an algorithm/strategy is the effect of the count can't be determined in advance.
The ACPI quality tag is just an indicator and can't be used linearly.

If you see my best cores C02/C05 they have same 216 quality index.
But they behave very differently.
C02 is at -10 while C05 is at -20.
Despite that C02 runs at a lower VID, lower power draw and temperature and 50 MHz less boost.
That's because every core, even with the same quality index, as a different zero point.
And also a different count below which is unstable.

Same goes for the bad cores; they need maybe a positive count to work reliably.
But higher is the count and worse will be the frequency boost.
C03 and C06 are the worse in CCD1.
But going to a lower negative/positive count and pushing the VID up will not help at all.
They will still throttle with almost the same power draw and temperature.
But the frequency will go down, from 4860 to 4800 and below.

So you really need to test one by one starting form zero and see the effect.
Plus also make continuosly sweeps all over again to see how the change affected the other cores.


----------



## Veii

ManniX-ITA said:


> If you see my best cores C02/C05 they have same 216 quality index.
> But they behave very differently.
> C02 is at -10 while C05 is at -20.
> Despite that C02 runs at a lower VID, lower power draw and temperature and 50 MHz less boost.


Because a better core needs less negative CO
A worse core needs more Negative CO

There is a 20mV distance between both on your example
Likely other cores in the same CCX pull it it globally down too = CCX requests too high VID = FIT throttles frequency to lower VID request
But generally, a weaker core needs more negative CO ~ to have lower VID, to be able to request more VID , to boost higher

IF both are sub 1.4v and surely not voltage/strain limited by FIT
It's just the imbalance that doesn't allow to reach peak boost.

You can use FIT ACPI rating for core to core balance & CO Distance.
You don't have to, if you have a tool that does the math for you and tests down stability
But the same thing you can also do , just by testing "what does it need to boost higher"
Most of the times it doesn't need anything & already gets far too much
Which is why PX High (single core) is fixed at 1.4v or lower & how also overboost works with negative mV additives
And why i mentioned that 1.3875v-TEL & V-VID is plenty to hold 5ghz allcore. You just need to "undervolt" in a reverse manner

^ Disclaimer:
Above is information researched by me
No confidential information i got to know, was shared as such
Result is out of my replicated-research, from open available tools


----------



## domdtxdissar

Kurt Krampmeier said:


> Spoiler: RC6 Diag
> 
> 
> 
> *ClockTuner for Ryzen 2.1 RC6(ver.24) by 1usmus*
> PUBLIC EDITION
> AMD Ryzen 9 5900X 12-Core Processor
> ASUS ROG STRIX B450-F GAMING II
> BIOS ver. 4402 SMU ver. 56.53.00
> TABLE ver. 3672069
> DRAM speed 3600 MHz
> 07/06/2021 08:31:46
> 
> 
> P1
> FREQ CCX1# 4525MHz
> FREQ CCX2# 4375MHz
> VID# 1175mV
> Usage trigger# 81%
> OB CCX1# -33
> OB CCX2# -87
> P2
> FREQ CCX1# 4650MHz
> FREQ CCX2# 4475MHz
> VID# 1275mV
> Usage trigger# 29%
> OB CCX1# -33
> OB CCX2# -87
> PX
> FREQ HIGH# 4875MHz
> FREQ MID# 4750MHz
> FREQ LOW# 4700MHz
> VID HIGH# 1400mV
> VID MID# 1375mV
> VID LOW# 1350mV
> OB HIGH# -50
> OB MID# -46
> OB LOW# -43
> Usage trigger# 12%
> PX OB LIMIT# 100MHz
> 
> 
> HYBRID OC enabled!
> P1 PROFILE successfully activated!
> P2 PROFILE successfully activated!
> PX PROFILE successfully activated!
> Recommended to use the manual CPU LLC!
> ASUS - Level 3
> MSI - Mode 4
> Gigabyte - High
> Asrock - Level 2
> Phoenix ready!
> Cinebench R20 started
> Cinebench R20 finished with result: 7778
> Voltage: 1.182 V PPT: 141.6 W Temperature: 65.8°
> 08:33:25: Test 1 started!
> Basic statistics
> CORE / CPPC / FREQUENCY / VID / POWER / TEMP
> C01 174 F 4738 V 1.414 W 15.23 T 65.53
> C02 170 F 54 V 1.414 W 2.77 T 44.62
> C03 162 F 46 V 1.414 W 2.92 T 46.94
> C04 174 F 4738 V 1.414 W 15.6 T 69.24
> C05 158 F 55 V 1.414 W 2.61 T 42.49
> C06 166 F 60 V 1.414 W 3.14 T 50.55
> C07 141 F 104 V 1.414 W 0.91 T 36.83
> C08 150 F 120 V 1.414 W 0.9 T 34.34
> C09 137 F 58 V 1.414 W 0.9 T 38.45
> C10 154 F 100 V 1.414 W 0.84 T 34.78
> C11 133 F 216 V 1.414 W 1.14 T 38.86
> C12 145 F 110 V 1.414 W 0.91 T 34.77
> Vdroop: 0%
> 4700 - PASSED 1.239
> 4725 - PASSED 1.255
> 4750 - PASSED 1.272
> 4775 - PASSED 1.287
> 4800 - PASSED 1.307
> 4825 - PASSED 1.325
> 4850 - PASSED 1.346
> 4875 - PASSED 1.367
> 08:33:51: Cinebench stopped!
> PX HIGH sub-profile
> CPU usage(min): 8.3%
> CPU usage(avg): 8.71%
> CPU usage(max): 11.3%
> SAFE: 4875MHz
> FAST: 4925MHz
> 08:33:51: Test 1 finished!
> 08:33:51: Test 2 started!
> Basic statistics
> CORE / CPPC / FREQUENCY / VID / POWER / TEMP
> C01 174 F 4644 V 1.396 W 14.24 T 63.72
> C02 170 F 4644 V 1.396 W 14.7 T 69.28
> C03 162 F 56 V 1.396 W 2.86 T 47.3
> C04 174 F 4644 V 1.396 W 15.58 T 74.84
> C05 158 F 86 V 1.396 W 2.66 T 43.26
> C06 166 F 4638 V 1.396 W 15.53 T 76.13
> C07 141 F 170 V 1.396 W 1.08 T 39.94
> C08 150 F 134 V 1.396 W 0.91 T 34.82
> C09 137 F 60 V 1.396 W 0.92 T 41.62
> C10 154 F 103 V 1.396 W 0.9 T 35.22
> C11 133 F 290 V 1.396 W 1.32 T 42.3
> C12 145 F 260 V 1.396 W 1.12 T 35.51
> Vdroop: 0%
> 4600 - PASSED 1.21
> 4625 - PASSED 1.228
> 4650 - PASSED 1.245
> 4675 - PASSED 1.269
> 4700 - PASSED 1.295
> 4725 - PASSED 1.319
> 4750 - PASSED 1.343
> 08:34:16: Cinebench stopped!
> PX MID sub-profile
> CPU usage(min): 16.7%
> CPU usage(avg): 17.17%
> CPU usage(max): 19%
> SAFE: 4750MHz
> FAST: 4825MHz
> Max CPU usage for PX MID: 20%
> 08:34:16: Test 2 finished!
> 08:34:16: Test 3 started!
> Basic statistics
> CORE / CPPC / FREQUENCY / VID / POWER / TEMP
> C01 174 F 4606 V 1.37 W 14.1 T 68.26
> C02 170 F 4606 V 1.37 W 14.54 T 68.79
> C03 162 F 4606 V 1.37 W 13.94 T 69.66
> C04 174 F 4606 V 1.37 W 14.9 T 75.57
> C05 158 F 4606 V 1.37 W 14.32 T 69.46
> C06 166 F 4606 V 1.37 W 15.37 T 77.06
> C07 141 F 98 V 1.37 W 0.9 T 39.79
> C08 150 F 133 V 1.37 W 0.85 T 34.48
> C09 137 F 63 V 1.37 W 0.9 T 41.68
> C10 154 F 95 V 1.37 W 0.79 T 34.83
> C11 133 F 253 V 1.37 W 1.12 T 42.18
> C12 145 F 124 V 1.37 W 0.86 T 34.83
> Vdroop: 0%
> 4550 - PASSED 1.182
> 4575 - PASSED 1.198
> 4600 - PASSED 1.217
> 4625 - PASSED 1.233
> 4650 - PASSED 1.249
> 4675 - PASSED 1.273
> 4700 - PASSED 1.293
> 4725 - PASSED 1.316
> 08:34:41: Cinebench stopped!
> PX LOW sub-profile
> CPU usage(min): 25%
> CPU usage(avg): 25.18%
> CPU usage(max): 28.6%
> SAFE: 4725MHz
> FAST: 4800MHz
> Max CPU usage for PX LOW: 29%
> 08:34:41: Test 3 finished!
> 08:34:41: Test 4 started!
> Basic statistics
> CORE / CPPC / FREQUENCY / VID / POWER / TEMP
> C01 174 F 4078 V 1.178 W 10.4 T 58.83
> C02 170 F 4078 V 1.178 W 10.56 T 60.32
> C03 162 F 4078 V 1.178 W 10.44 T 59.72
> C04 174 F 4078 V 1.178 W 10.8 T 65.03
> C05 158 F 4078 V 1.178 W 10.41 T 57.58
> C06 166 F 4078 V 1.178 W 10.82 T 65.16
> C07 141 F 4078 V 1.178 W 7.71 T 52.88
> C08 150 F 4078 V 1.178 W 7.82 T 53.74
> C09 137 F 4078 V 1.178 W 7.96 T 57.89
> C10 154 F 4078 V 1.178 W 7.89 T 56.32
> C11 133 F 4078 V 1.178 W 7.91 T 57.88
> C12 145 F 4078 V 1.178 W 7.88 T 55.58
> Start VID 1275
> Start FREQ CCX#1 4350
> Start FREQ CCX#2 4275
> Vdroop: 0%
> 4375 / 4300 - PASSED
> 4400 / 4325 - PASSED
> 4425 / 4350 - PASSED
> 4450 / 4375 - PASSED
> 4475 / 4400 - PASSED
> 4500 / 4425 - PASSED
> 4525 / 4450 - PASSED
> 4550 / 4475 - PASSED
> 4575 / 4475 - PASSED
> 4600 / 4475 - PASSED
> 4625 / 4475 - PASSED
> 4650 / 4475 - PASSED
> 4625 / 4475 - PASSED
> P2 PROFILE
> VID: 1275mV
> CCX#1: 4625MHz
> CCX#2: 4475MHz
> 08:35:01: Cinebench stopped!
> 08:35:01: Test 4 finished!
> 08:35:01: Test 5 started!
> Basic statistics
> CORE / CPPC / FREQUENCY / VID / POWER / TEMP
> C01 174 F 4102 V 1.186 W 10.49 T 58.86
> C02 170 F 4102 V 1.186 W 10.79 T 60.68
> C03 162 F 4102 V 1.186 W 10.58 T 59.51
> C04 174 F 4102 V 1.186 W 11.08 T 65.03
> C05 158 F 4102 V 1.186 W 10.55 T 58.12
> C06 166 F 4102 V 1.186 W 11.18 T 65.82
> C07 141 F 4102 V 1.186 W 7.7 T 53.18
> C08 150 F 4102 V 1.186 W 8.06 T 54.5
> C09 137 F 4102 V 1.186 W 7.95 T 57.51
> C10 154 F 4102 V 1.186 W 8.02 T 56.85
> C11 133 F 4102 V 1.186 W 7.98 T 58.36
> C12 145 F 4102 V 1.186 W 7.99 T 56.2
> Start VID 1175
> Start FREQ CCX#1 4150
> Start FREQ CCX#2 4075
> Vdroop: 0%
> 4175 / 4100 - PASSED
> 4200 / 4125 - PASSED
> 4225 / 4150 - PASSED
> 4250 / 4175 - PASSED
> 4275 / 4200 - PASSED
> 4300 / 4225 - PASSED
> 4325 / 4250 - PASSED
> 4350 / 4275 - PASSED
> 4375 / 4300 - PASSED
> 4400 / 4325 - PASSED
> 4425 / 4350 - PASSED
> 4450 / 4375 - PASSED
> 4475 / 4375 - PASSED
> 4500 / 4375 - PASSED
> 4525 / 4375 - PASSED
> 4525 / 4375 - PASSED
> P1 PROFILE
> VID: 1175mV
> CCX#1: 4525MHz
> CCX#2: 4375MHz
> 08:35:22: Cinebench stopped!
> Cinebench R20 started
> Cinebench R20 finished with result: 8418
> Voltage: 1.175 V PPT: 147.8 W Temperature: 68.6°
> 08:36:05: Test 5 finished!
> 
> 
> 08:36:08: OB test started!
> This test can reboot the system!
> There is no need to worry, it's safe.
> The testing process may take some time.
> 
> 
> 08:36:11: Step: 1
> CCX1 FREQ 4075MHz
> CCX2 FREQ 3975MHz
> PX HIGH OB: -78
> PX MID OB: -75
> PX LOW OB: -73
> P2 CCX1 OB: -63
> P2 CCX2 OB: -59
> P1 CCX1 OB: -63
> P1 CCX2 OB: -59
> 
> 
> Curve Optimizer
> C01 20 C07 17
> C02 19 C08 19
> C03 18 C09 17
> C04 19 C10 19
> C05 18 C11 20
> C06 18 C12 21
> 
> 
> 08:36:16: Test#1
> 08:37:16: Test#2
> 
> 
> 08:38:20: Step: 2
> CCX1 FREQ 4100MHz
> CCX2 FREQ 4000MHz
> PX HIGH OB: -71
> PX MID OB: -67
> PX LOW OB: -67
> P2 CCX1 OB: -56
> P2 CCX2 OB: -52
> P1 CCX1 OB: -56
> P1 CCX2 OB: -52
> 
> 
> Curve Optimizer
> C01 18 C07 15
> C02 17 C08 17
> C03 16 C09 15
> C04 17 C10 18
> C05 16 C11 18
> C06 16 C12 20
> 
> 
> 08:38:28: Test#1
> 08:39:28: Test#2
> 
> 
> 08:40:32: Step: 3
> CCX1 FREQ 4125MHz
> CCX2 FREQ 4025MHz
> PX HIGH OB: -65
> PX MID OB: -59
> PX LOW OB: -59
> P2 CCX1 OB: -49
> P2 CCX2 OB: -43
> P1 CCX1 OB: -49
> P1 CCX2 OB: -43
> 
> 
> Curve Optimizer
> C01 17 C07 13
> C02 15 C08 15
> C03 15 C09 13
> C04 16 C10 16
> C05 14 C11 16
> C06 15 C12 18
> 
> 
> 08:40:40: Test#1
> 08:41:40: Test#2
> 
> 
> 08:42:44: Step: 4
> CCX1 FREQ 4150MHz
> CCX2 FREQ 4050MHz
> PX HIGH OB: -57
> PX MID OB: -53
> PX LOW OB: -51
> P2 CCX1 OB: -41
> P2 CCX2 OB: -36
> P1 CCX1 OB: -41
> P1 CCX2 OB: -36
> 
> 
> Curve Optimizer
> C01 15 C07 11
> C02 14 C08 14
> C03 13 C09 11
> C04 14 C10 14
> C05 12 C11 14
> C06 13 C12 16
> 
> 
> 08:42:52: Test#1
> 08:43:51: Test#2
> 
> 
> 08:44:56: Step: 5
> CCX1 FREQ 4175MHz
> CCX2 FREQ 4075MHz
> PX HIGH OB: -50
> PX MID OB: -45
> PX LOW OB: -43
> P2 CCX1 OB: -33
> P2 CCX2 OB: -29
> P1 CCX1 OB: -33
> P1 CCX2 OB: -29
> 
> 
> Curve Optimizer
> C01 13 C07 9
> C02 12 C08 12
> C03 11 C09 9
> C04 12 C10 12
> C05 10 C11 12
> C06 11 C12 14
> 
> 
> 08:45:04: Test#1
> 08:46:04: Test#2
> 
> 
> 08:47:08: Step: 6
> CCX1 FREQ 4200MHz
> CCX2 FREQ 4100MHz
> PX HIGH OB: -42
> PX MID OB: -38
> PX LOW OB: -36
> P2 CCX1 OB: -26
> P2 CCX2 OB: -20
> P1 CCX1 OB: -26
> P1 CCX2 OB: -20
> 
> 
> Curve Optimizer
> C01 11 C07 8
> C02 10 C08 10
> C03 9 C09 7
> C04 10 C10 10
> C05 9 C11 10
> C06 9 C12 13
> 
> 
> 08:47:16: Test#1
> 08:48:16: Test#2
> 
> 
> 08:49:20: Step: 7
> CCX1 FREQ 4225MHz
> CCX2 FREQ 4125MHz
> PX HIGH OB: -35
> PX MID OB: -30
> PX LOW OB: -29
> P2 CCX1 OB: -19
> P2 CCX2 OB: -11
> P1 CCX1 OB: -19
> P1 CCX2 OB: -11
> 
> 
> Curve Optimizer
> C01 9 C07 5
> C02 8 C08 8
> C03 7 C09 5
> C04 8 C10 8
> C05 7 C11 8
> C06 7 C12 11
> 
> 
> 08:49:28: Test#1
> 08:49:48: CCX2 instability detected!
> 08:49:48: Thread# 12 dropped!
> 08:49:48: Stress test stopped.
> CCX1 FREQ 4225MHz
> CCX2 FREQ 4100MHz
> 
> 
> PX HIGH OB: -35
> PX MID OB: -30
> PX LOW OB: -29
> P2 CCX1 OB: -19
> P2 CCX2 OB: -20
> P1 CCX1 OB: -19
> P1 CCX2 OB: -20
> 
> 
> Curve Optimizer
> C01 9 C07 7
> C02 8 C08 10
> C03 7 C09 7
> C04 8 C10 10
> C05 7 C11 10
> C06 7 C12 13
> 
> 
> 08:49:57: Test#1
> 08:50:56: Test#2
> 
> 
> 08:52:01: Step: 8
> CCX1 FREQ 4250MHz
> CCX2 FREQ 4100MHz
> PX HIGH OB: -28
> PX MID OB: -23
> PX LOW OB: -21
> P2 CCX1 OB: -11
> P2 CCX2 OB: -20
> P1 CCX1 OB: -11
> P1 CCX2 OB: -20
> 
> 
> Curve Optimizer
> C01 8 C07 7
> C02 6 C08 10
> C03 5 C09 7
> C04 7 C10 10
> C05 5 C11 10
> C06 5 C12 12
> 
> 
> 08:52:09: Test#1
> 08:53:08: Test#2
> 
> 
> 08:54:12: Step: 9
> CCX1 FREQ 4275MHz
> CCX2 FREQ 4100MHz
> PX HIGH OB: -21
> PX MID OB: -15
> PX LOW OB: -14
> P2 CCX1 OB: -4
> P2 CCX2 OB: -20
> P1 CCX1 OB: -4
> P1 CCX2 OB: -20
> 
> 
> Curve Optimizer
> C01 5 C07 7
> C02 4 C08 10
> C03 3 C09 7
> C04 5 C10 10
> C05 3 C11 10
> C06 3 C12 13
> 
> 
> 08:54:21: Test#1
> 08:55:20: Test#2
> 
> 
> 08:56:24: Step: 10
> CCX1 FREQ 4300MHz
> CCX2 FREQ 4100MHz
> PX HIGH OB: -13
> PX MID OB: -8
> PX LOW OB: -7
> P2 CCX1 OB: 3
> P2 CCX2 OB: -20
> P1 CCX1 OB: 3
> P1 CCX2 OB: -20
> 
> 
> Curve Optimizer
> C01 4 C07 8
> C02 3 C08 10
> C03 1 C09 7
> C04 3 C10 10
> C05 1 C11 10
> C06 1 C12 13
> 
> 
> 08:56:33: Test#1
> 08:57:32: Test#2
> 
> 
> 08:58:36: Step: 11
> CCX1 FREQ 4325MHz
> CCX2 FREQ 4100MHz
> PX HIGH OB: -6
> PX MID OB: -1
> PX LOW OB: 1
> P2 CCX1 OB: 11
> P2 CCX2 OB: -20
> P1 CCX1 OB: 11
> P1 CCX2 OB: -20
> 
> 
> Curve Optimizer
> C01 2 C07 7
> C02 1 C08 10
> C03 0 C09 7
> C04 1 C10 10
> C05 -1 C11 10
> C06 0 C12 13
> 
> 
> 08:58:45: Test#1
> 08:59:44: Test#2
> 
> 
> 09:00:48: Step: 12
> CCX1 FREQ 4350MHz
> CCX2 FREQ 4100MHz
> PX HIGH OB: 1
> PX MID OB: 7
> PX LOW OB: 9
> P2 CCX1 OB: 19
> P2 CCX2 OB: -20
> P1 CCX1 OB: 19
> P1 CCX2 OB: -20
> 
> 
> Curve Optimizer
> C01 0 C07 7
> C02 -1 C08 10
> C03 -2 C09 7
> C04 -1 C10 10
> C05 -3 C11 10
> C06 -2 C12 13
> 
> 
> 09:00:57: Test#1
> 09:01:56: Test#2
> 
> 
> 09:03:00: Step: 13
> CCX1 FREQ 4375MHz
> CCX2 FREQ 4100MHz
> PX HIGH OB: 9
> PX MID OB: 15
> PX LOW OB: 17
> P2 CCX1 OB: 27
> P2 CCX2 OB: -20
> P1 CCX1 OB: 27
> P1 CCX2 OB: -20
> 
> 
> Curve Optimizer
> C01 -2 C07 7
> C02 -3 C08 10
> C03 -4 C09 7
> C04 -3 C10 10
> C05 -5 C11 10
> C06 -4 C12 13
> 
> 
> 09:03:08: Test#1
> 09:04:08: Test#2
> 
> 
> 09:05:12: Step: 14
> CCX1 FREQ 4400MHz
> CCX2 FREQ 4100MHz
> PX HIGH OB: 17
> PX MID OB: 23
> PX LOW OB: 25
> P2 CCX1 OB: 35
> P2 CCX2 OB: -20
> P1 CCX1 OB: 35
> P1 CCX2 OB: -20
> 
> 
> Curve Optimizer
> C01 -3 C07 7
> C02 -5 C08 10
> C03 -6 C09 7
> C04 -5 C10 10
> C05 -7 C11 10
> C06 -6 C12 13
> 
> 
> 09:05:21: Test#1
> 09:05:55: CCX1 instability detected!
> 09:05:55: Thread# 3 dropped!
> 09:05:55: Stress test stopped.
> CCX1 FREQ 4375MHz
> CCX2 FREQ 4100MHz
> 
> 
> PX HIGH OB: 9
> PX MID OB: 14
> PX LOW OB: 17
> P2 CCX1 OB: 27
> P2 CCX2 OB: -20
> P1 CCX1 OB: 27
> P1 CCX2 OB: -20
> 
> 
> Curve Optimizer
> C01 -2 C07 7
> C02 -3 C08 10
> C03 -4 C09 7
> C04 -3 C10 10
> C05 -5 C11 11
> C06 -4 C12 13
> 
> 
> 09:06:03: Test#1
> 09:07:03: Test#2
> 
> 
> Results OB testing
> PX HIGH OB: 9
> PX MID OB: 14
> PX LOW OB: 17
> P2 CCX1 OB: 27
> P2 CCX2 OB: -20
> P1 CCX1 OB: 27
> P1 CCX2 OB: -20
> 
> 
> 
> 
> 
> 
> CORES ORDER (from the best to the worst)
> ### CPPC VID FIT
> 1 С04 С01 С06
> 2 С01 С02 С04
> 3 С02 С04 С02
> 4 С06 С03 С03
> 5 С03 С05 С01
> 6 С05 С06 C11
> 7 C10 C12 С05
> 8 С08 C11 С09
> 9 C12 C10 C10
> 10 С07 С08 C12
> 11 С09 С07 С08
> 12 C11 С09 С07
> 
> 
> 
> 
> AVX light mode
> Cycle time: 60000 ms
> Reference frequency: 4375MHz
> Reference voltage: 1187 mV
> Voltage step: 6 mV
> 
> 
> Manual overclocking mode enabled
> 09:08:12: Saving temporary settings...
> 09:08:17: CCX1 (158): 4375 MHz, 1187 mV
> 09:08:17: CCX2 (133): 4375 MHz, 1187 mV
> 09:08:17: Step# 1. Diagnostic VID: 1187 mV
> 09:08:17: Stress test 1 started...
> 
> 
> 
> maybe you find something useful in there.


Looks to me you are running way to strong LLC as you have 0% vdroop even with an allcore load.
This also very much affect the CO / OB numbers CTR gives you.

More vdroop = Lower CO / Higher OB numbers you get in CTR (at the cost of lower "baseclock" (P1,P2 and to a lesser extent PX))
CTR is a OC sandbox, but many things are not explained well enough and ppl are using it with missing information/knowledge how it actually work..


----------



## ManniX-ITA

Veii said:


> Because a better core needs less negative CO
> A worse core needs more Negative CO


My best is C05 not C02, the one with more negative CO 

C05 is constantly ahead, 5-10 points in CPU-z even with CO equalized.
I think there's a difference in how they have been "serialized" during mass production.

I don't think it's a matter of "need", it's more a matter of "how".
How it works at -10? How it works at -20?
The ACPI index can be used as a starting point but then it's all about "how" it reacts to the count.

I have also some cores that can work with lower counts on CCD2 but they don't go faster but slower.
But if I set the count higher then the all-core performance is impacted.
That's another variable that should be considered when fine tuning per single core.


----------



## Kurt Krampmeier

Kurt Krampmeier said:


> С07 С08 C1





domdtxdissar said:


> Looks to me you are running way to strong LLC as you have 0% vdroop even with an allcore load.
> This also very much affect the CO / OB numbers CTR gives you.
> 
> More vdroop = Lower CO / Higher OB numbers you get in CTR (at the cost of lower "baseclock" (P1,P2 and to a lesser extent PX))
> CTR is a OC sandbox, but many things are not explained well enough and ppl are using it with missing information/knowledge how it actually work..


thanks for the input. i am aware that 0% vdroop is not preferable. the board however does only offer 4 settings, auto, regular, medium, high. where high overshoots. i am at medium and vdroop is in the 0.0x range. have not really tested regular setting as 1usmus suggests rather small vdroop and high vsoc. i started with that in rc5 and kept it. will observe "regular" behavior when i dial in veiis CO values and test them


----------



## XPEHOPE3

Veii said:


> @XPEHOPE3 i think you are a very replicable testing rabbit with a 5600X 🤭
> Please drop some CTR Core Readout (top sensor values without Curve optimizer used) and i want to try giving you a set
> Unsure about non 5600X units, but this surely works on your unit. I'm confident on the math











These are you talking about?
I have 2-CCD 5600x, no access to RC6, "OB testing" greyed out in CTR, in BIOS no CO, PBO disabled @ 1x, vCore LLC normal (not High as recommended for Gigabyte per CTR log from Kurt)

EDIT:


Spoiler: boost tester and diagnostic log



*ClockTuner for Ryzen 2.1 RC5(ver.23) by 1usmus*
AMD Ryzen 5 5600X 6-Core Processor
GIGABYTE B550 AORUS PRO V2
BIOS ver. F13k SMU ver. 56.53.00
TABLE ver. 3672069
DRAM speed 3866 MHz
07/06/2021 14:43:31


P1
FREQ CCX1# 0MHz
VID# 1150mV
Usage trigger# 81%
OB CCX1# 1
OB CCX2# 1
P2
FREQ CCX1# 0MHz
VID# 1250mV
Usage trigger# 58%
OB CCX1# 1
OB CCX2# 1
PX
FREQ HIGH# 0MHz
FREQ MID# 0MHz
FREQ LOW# 0MHz
VID HIGH# 1375mV
VID MID# 1375mV
VID LOW# 1350mV
OB HIGH# 1
OB MID# 1
OB LOW# 1
Usage trigger# 24%
PX OB LIMIT# 75MHz


You have unique processor, 2 CCD's!


14:54:20: Boost testing started!
14:54:58: Boost testing finished!
14:54:58: Cinebench stopped!


CTR BOOST TESTER RESULTS (test version)
CORE / FREQUENCY / VID / POWER / TEMP
C01 F 4650 V 1.34 W 11.17 T 54.44
C02 F 4650 V 1.301 W 10.27 T 52.04
C03 F 4649 V 1.312 W 10.75 T 52.8
C04 F 4650 V 1.33 W 10.84 T 53.36
C05 F 4650 V 1.366 W 12.19 T 57.28
C06 F 4650 V 1.355 W 12.12 T 57.72


CPU TOPOLOGY (ENABLED CORES)
CCX#1 C01
CCX#1 C02
CCX#1 C03
CCX#1 C04
CCX#1 C07
CCX#1 C08
Phoenix ready!
Cinebench R20 started
Cinebench R20 finished with result: 4437
Voltage: 1.224 V PPT: 76 W Temperature: 60.3°
15:00:58: Test 1 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP / DEBUG
C01 133 F 62 V 1.321 W 0.29 T 38.68 L 0.936
C02 140 F 4455 V 1.321 W 10.19 T 53.02 L 1.224
C03 140 F 4650 V 1.321 W 10.78 T 54.26 L 1.249
C04 137 F 30 V 1.321 W 0.12 T 37.14 L 0.933
C05 125 F 112 V 1.321 W 1.17 T 36.47 L 0.942
C06 129 F 62 V 1.321 W 0.19 T 34.2 L 0.938
Vdroop: 0.8%
4625 - PASSED
4650 - PASSED
4675 - PASSED
4700 - PASSED
4725 - PASSED
4750 - PASSED
4775 - PASSED
4800 - PASSED
15:01:26: Cinebench stopped!
PX HIGH sub-profile
CPU usage(min): 16.7%
CPU usage(avg): 16.82%
CPU usage(max): 30.6%
SAFE: 4800MHz
FAST: 4825MHz
15:01:26: Test 1 finished!
15:01:26: Test 2 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP / DEBUG
C01 133 F 4479 V 1.382 W 11.52 T 62.48 L 1.286
C02 140 F 4650 V 1.382 W 11.95 T 62.74 L 1.266
C03 140 F 4632 V 1.382 W 12.08 T 63 L 1.277
C04 137 F 4650 V 1.382 W 12.03 T 62.69 L 1.293
C05 125 F 156 V 1.382 W 1.44 T 39.38 L 0.946
C06 129 F 97 V 1.382 W 0.82 T 38.48 L 0.946
Vdroop: 1.38%
4575 - PASSED
4600 - PASSED
4625 - PASSED
4650 - PASSED
4675 - PASSED
4700 - PASSED
4725 - PASSED
15:01:54: Cinebench stopped!
PX MID sub-profile
CPU usage(min): 33.2%
CPU usage(avg): 33.3%
CPU usage(max): 42.7%
SAFE: 4725MHz
FAST: 4750MHz
Max CPU usage for PX MID: 41%
15:01:54: Test 2 finished!
15:01:54: Test 3 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP / DEBUG
C01 133 F 4606 V 1.381 W 14.01 T 68.67 L 1.295
C02 140 F 4619 V 1.381 W 15.21 T 70.04 L 1.268
C03 140 F 4598 V 1.381 W 12.88 T 66.5 L 1.267
C04 137 F 4619 V 1.381 W 13.09 T 68.28 L 1.289
C05 125 F 310 V 1.381  W 1.82 T 41.88 L 0.958
C06 129 F 2021 V 1.381 W 5.97 T 55.03 L 1.094
Vdroop: 1.85%
4525 - PASSED
4550 - PASSED
4575 - PASSED
4600 - PASSED
4625 - PASSED
4650 - PASSED
4675 - PASSED
4700 - PASSED
15:02:22: Cinebench stopped!
PX LOW sub-profile
CPU usage(min): 50%
CPU usage(avg): 50.2%
CPU usage(max): 58.3%
SAFE: 4700MHz
FAST: 4725MHz
Max CPU usage for PX LOW: 58%
15:02:22: Test 3 finished!
15:02:22: Test 4 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP / DEBUG
C01 133 F 4206 V 1.16 W 9.82 T 59.13 L 1.078
C02 140 F 4206 V 1.16 W 10.05 T 60.02 L 1.074
C03 140 F 4206 V 1.16 W 9.49 T 57.96 L 1.074
C04 137 F 4206 V 1.16 W 10.06 T 59.41 L 1.076
C05 125 F 4206 V 1.16 W 9.28 T 55.94 L 1.078
C06 129 F 4206 V 1.16 W 9.82 T 58.34 L 1.077
15:02:32: Stress test stopped.
Start VID 1250
Start FREQ CCX#1 4375
Vdroop: 2.56%
4400 - PASSED
4425 - PASSED
4450 - PASSED
4475 - PASSED
4500 - PASSED
4525 - PASSED
P2 PROFILE
VID: 1250mV
CCX#1: 4525MHz
15:02:37: Stress test stopped.
15:02:37: Test 4 finished!
15:02:37: Test 5 started!
Basic statistics
CORE / CPPC / FREQUENCY / VID / POWER / TEMP / DEBUG
C01 133 F 4180 V 1.152 W 9.57 T 59.01 L 1.071
C02 140 F 4180 V 1.152 W 9.48 T 59.08 L 1.066
C03 140 F 4180 V 1.152 W 9.68 T 58.06 L 1.068
C04 137 F 4180 V 1.152 W 9.88 T 58.85 L 1.069
C05 125 F 4180 V 1.152 W 9.49 T 56.12 L 1.071
C06 129 F 4180 V 1.152 W 9.38 T 57.7 L 1.07
Start VID 1150
Start FREQ CCX#1 4175
Vdroop: 2.61%
4200 - PASSED
4225 - PASSED
4250 - PASSED
4275 - PASSED
4300 - PASSED
4325 - PASSED
4350 - PASSED
4375 - PASSED
4400 - PASSED
P1 PROFILE
VID: 1150mV
CCX#1: 4400MHz
15:02:55: Stress test stopped.
Cinebench R20 started
Cinebench R20 finished with result: 4386
Voltage: 1.15 V PPT: 68.9 W Temperature: 57°
15:04:11: Test 5 finished!


CORES ORDER (from the best to the worst)
### CPPC VID FIT
1 С03 С02 С02
2 С02 С03 С01
3 С04 С04 С04
4 С01 С06 С03
5 С06 С01 С06
6 С05 С05 С05




AVX light mode
Cycle time: 120000 ms
Reference frequency: 4375MHz
Reference voltage: 1187 mV
Voltage step: 6 mV


Manual overclocking mode enabled
15:04:18: Saving temporary settings...
15:04:23: CCX1 (125): 4375 MHz, 1187 mV
15:04:23: Step# 1. Diagnostic VID: 1187 mV
15:04:23: Stress test 1 started...
15:05:28: Stress test stopped.
15:05:29: Stress test 2 started...
15:06:34: Stress test stopped.
15:06:35: Step# 2. Diagnostic VID: 1112 mV
15:06:35: Stress test 1 started...
15:07:41: Stress test stopped.
15:07:41: Stress test 2 started...
15:08:47: Stress test stopped.
15:08:47: Step# 3. Diagnostic VID: 1106 mV
15:08:47: Stress test 1 started...
15:09:53: Stress test stopped.
15:09:54: Stress test 2 started...
15:10:59: Stress test stopped.
15:11:00: Step# 4. Diagnostic VID: 1100 mV
15:11:00: Stress test 1 started...
15:12:05: Stress test stopped.
15:12:06: Stress test 2 started...
15:13:11: Stress test stopped.
15:13:12: Step# 5. Diagnostic VID: 1094 mV
15:13:12: Stress test 1 started...
15:14:17: Stress test stopped.
15:14:18: Stress test 2 started...
15:15:24: Stress test stopped.
15:15:24: Step# 6. Diagnostic VID: 1088 mV
15:15:24: Stress test 1 started...
15:15:49: Thread# 7 fall down!
15:15:49: Stress test stopped.
15:15:50: Step# 7. Diagnostic VID: 1094 mV


DIAGNOSTIC RESULTS
AMD Ryzen 5 5600X 6-Core Processor
CPU VID: 1094
CPU TEL: 1059
Max temperature: 59,08°
Energy efficient: 4,13
Your CPU is GOLDEN SAMPLE
Recomended values for overclocking (P1 profile):
Reference voltage: 1150 mV
Reference frequency: 4375 MHz
Recomended values for overclocking (P2 profile):
Reference voltage: 1300 mV
Reference frequency: 4625 MHz
Recomended values for undervolting:
Reference voltage: 1025 mV
Reference frequency: 4125 MHz

Phoenix deactivated!


----------



## Mach3.2

Veii said:


> Spoiler: Results Demystified
> 
> 
> 
> 
> 
> 
> Code:
> 
> 
> Krapmeier's 5900X
> 
> CCX1
> FREQ 4100MHz
> 
> C01 18
> C02 17
> C03 16
> C04 17
> C05 16
> C06 16
> 
> FREQ 4125MHz
> 
> C01 17
> C02 15
> C03 15
> C04 16
> C05 14
> C06 15
> 
> FREQ 4150Mhz
> 
> C01 15
> C02 14
> C03 13
> C04 14
> C05 12
> C06 13
> 
> FREQ 4200MHz
> 
> C01 11
> C02 10
> C03 9
> C04 10
> C05 9
> C06 9
> 
> FREQ 4300MHz (+100Mhz , -8 CO)
> 
> C01 4
> C02 3 (should've been 2)
> C03 1
> C04 3
> C05 1
> C06 1
> 
> FREQ 4400MHz
> 
> C01 -3
> C02 -5 (error ~ should've been -6)
> C03 -6 (usually also -7)
> C04 -5
> C05 -7
> C06 -6
> 
> Fallback to
> FREQ 4375MHz (-25mhz, 2 CO ontop again)
> 
> C01 -2
> C02 -3
> C03 -4
> C04 -3
> C05 -5
> C06 -4
> =================================
> CCX2
> FREQ 4000MHz
> C07 15
> C08 17
> C09 15
> C10 18
> C11 18
> C12 20
> 
> FREQ 4025MHz
> C07 13
> C08 15
> C09 13
> C10 16
> C11 16
> C12 18
> 
> FREQ 4050MHz
> C07 11
> C08 14
> C09 11
> C10 14
> C11 14
> C12 16
> 
> FREQ 4100MHz (+50mhz, -4 CO)
> C07 8
> C08 10
> C09 7
> C10 10
> C11 10
> C12 13
> 
> FREQ 4125MHz
> C07 5 crash (should've been a +6 not a +5)
> C08 8
> C09 5
> C10 8
> C11 8
> C12 11
> 
> Fallback to
> REQ 4100MHz (-25mhz, 2 CO ontop again)
> C07 7
> C08 10
> C09 7
> C10 10
> C11 10
> C12 12
> 
> 
> 
> 
> 
> 
> 
> Spoiler: Math
> 
> 
> 
> 
> 
> 
> Code:
> 
> 
> RESULT:
> CCX1 FREQ 4375MHz
> CCX2 FREQ 4100MHz
> 
> C01 -2 / C07 +7
> C02 -3 / C08 +10
> C03 -4 / C09 +7
> C04 -3 / C10 +10
> C05 -5 / C11 +10
> C06 -4 / C12 +12
> 
> Requirement for CCX2 to reach 4375 = -24 CO
> Soo Result would be:
> C01 -2 / C07 -7
> C02 -3 / C08 -14
> C03 -4 / C09 -17
> C04 -3 / C10 -14
> C05 -5 / C11 -14
> C06 -4 / C12 -12
> 
> Then you just scale up
> -13 negative CO remaining as max = -12 = +100Mhz & +25mhz
> = Peak result for CCX 2 = 4.5Ghz allcore freq @
> C07 -20
> C08 -27
> C09 -30
> C10 -27
> C11 -27
> C12 -25
> 
> -12 for CCX 1 to reach 4.5 =
> C01 -14
> C02 -16
> C03 -15
> C04 -16
> C05 -18
> C06 -17
> 
> 
> 
> 
> 
> 
> 
> Code:
> 
> 
> RESULT:
> 
> C01 -14 / C07 -20
> C02 -16 / C08 -27
> C03 -15 / C09 -30
> C04 -16 / C10 -27
> C05 -18 / C11 -27
> C06 -17 / C12 -25
> 
> as input for the BIOS to Overdrive CTR
> * +/- 1 value of the threads that where crashing. But math remains identical
> Hope Yuri hurries up with Hydra , soo we don't have to do it by hand
> Tho overdriving Hydra surely (w)could work
> ** if you've shared the Core ACPI values, you can then match quality to it too
> ~ CTR can't get it perfect without extended testing
> X = 4 ACPI higher = +2 CO
> X = 4 ACPI values weaker = -2 CO
> According to:


Hold up, so the higher the ACPI values, the more positive curve optimiser value you can throw at the core?

I've been running all my cores at -30 except for one of my best cores which is at -20.



Spoiler



DEFAULT CURVE COEFFICIENTS
CORE#1 0 CPPC 170
CORE#2 46 CPPC 166
CORE#3 18 CPPC 178
CORE#4 932 CPPC 161
CORE#5 927 CPPC 178
CORE#6 935 CPPC 174
CORE#7 925 CPPC 141
CORE#8 934 CPPC 153
CORE#9 933 CPPC 157
CORE#10 912 CPPC 145
CORE#11 909 CPPC 149
CORE#12 924 CPPC 137


*ClockTuner for Ryzen 2.1 RC5(ver.23) by 1usmus*
AMD Ryzen 9 5900X 12-Core Processor
MSI MAG X570 TOMAHAWK WIFI (MS-7C84)
BIOS ver. 1.72 SMU ver. 56.53.00
TABLE ver. 3672069
DRAM speed 3600 MHz
07/06/2021 19:21:01


P1
P1 PROFILE has been restored!
P2
P2 PROFILE has been restored!
PX
PX PROFILE has been restored!




19:36:08: Boost testing started!
19:37:21: Boost testing finished!
19:37:21: Cinebench stopped!


CTR BOOST TESTER RESULTS (test version)
CORE / FREQUENCY / VID / POWER / TEMP
C01 F 4840 V 1.446 W 14.51 T 69.64
C02 F 4874 V 1.444 W 14.85 T 69.6
C03 F 4904 V 1.43 W 14.55 T 68.57
C04 F 4852 V 1.44 W 14.55 T 68.38
C05 F 4923 V 1.429 W 15.05 T 69.27
C06 F 4888 V 1.414 W 14.2 T 68.97
C07 F 4758 V 1.435 W 12.78 T 65.28
C08 F 4752 V 1.438 W 13.04 T 65.57
C09 F 4864 V 1.445 W 13.1 T 66.87
C10 F 4791 V 1.422 W 12.62 T 65.87
C11 F 4809 V 1.432 W 12.9 T 65.66
C12 F 4720 V 1.422 W 12.74 T 68.14


CPU TOPOLOGY (ENABLED CORES)
CCX#1 C01
CCX#1 C02
CCX#1 C03
CCX#1 C04
CCX#1 C06
CCX#1 C07
CCX#2 C09
CCX#2 C10
CCX#2 C12
CCX#2 C14
CCX#2 C15
CCX#2 C16


----------



## byDenoso

I've managed to improve my latency by changing RDDS/RDDL, ProcODT and CAD BUS.
But i cant get RCD 19 stable, no matter what i try.


----------



## mongoled

Me thinks you should all be talking about CO in a different thread, it needs its own discussion and that should not be here !


----------



## Iarwa1N

I’m thinking of changing my Strix B550-F board. Which is the best board for overclocking dual rank samsung b-die kits? My research pointing in MSI Unify-X direction. Also i saw there are new x570s series boards incoming, should I wait for them?


Sent from my iPhone using Tapatalk


----------



## byDenoso

I'll Keep tightening secondaries until error, since i get so many errors tightening primaries


----------



## adversary

Iarwa1N said:


> I’m thinking of changing my Strix B550-F board. Which is the best board for overclocking dual rank samsung b-die kits? My research pointing in MSI Unify-X direction. Also i saw there are new x570s series boards incoming, should I wait for them?
> 
> 
> Sent from my iPhone using Tapatalk




I belive going with 2 DIMMs type can't be wrong regarding that

I have some screenshoot in phone where MSI mentions there will be UNIFY-X with X570S chipset

now how exactly will X570S behave and what other will discover about it, I'm waiting to see. I'm also interested for that model. but of course best it to never rush and check all specs once it is out as well as to see if it is going to have any problem (at least for overclockers)
if all goes as I hope could be great choice


----------



## byDenoso

Margin of error result in latency after tweaking tCWL


----------



## PJVol

Veii said:


> Here is the little "cheat-sheet"


Funnily enough, the resulting "cheat-sheet-based" CO setting is very similar to the one I currently have set
-16 -14 -18 -12 -12 -20 (from cheat-sheet values)
-*12* -15 -18 -12 -*7* -20 (my current settings, obtained by a method I provide in a @mongoled PBO thread)
with the exception of Core0 ("special core") and Core4 values:

Core0 I set lower, since its kinda "thermally isolated" and so is able to hit required frequencies at much lower temp than others (but that may onlt be specific for 6 and 12 core CPUs, due to having fused-out cores in ccd's)
Core4 (best core) unfortunately crashes below -7 in 3DMark CPU Profile and Blender 'Koro' scene.
And Core1 is one notch down (and sometimes core5 down to -21 as well), because cores 1,3,5 are in the same "thermal envelope", so it seemed practical to tune down those adjacent to 3rd ("bad") cores if possible.
So nothing new here, sorry


----------



## Robostyle

Dunno why everyone before, even usmus with his dram calculator stated that cldo vddp should be low, lowest of each, way below 1V. Ive had to raise it up to 1.05V so my dualrank kit can be stable without whea at 3800MHz.
Moreover, it needs to be higher than both vddg, and even on auto mb sets vddp to 1.1V, whereas vddgs are fine staying at 950-1000mV
Is thats me doing smth wrong, or is it sil lottery much?


----------



## PJVol

Robostyle said:


> Dunno why everyone before, even usmus with his dram calculator stated that cldo vddp should be low


May be that was the case with zen/zen+, as to zen2/zen3 - i haven't seen any "official" (or semi-official) recommedation for that, except that its VDDIO_MEM rail derived and so can't be lower than VDIMM.
Hope someone more knowledgeable could make it clear, what is the allowable voltage range for the DDR encoding and signaling physical layer's supplied power.


----------



## Veii

PJVol said:


> Hope someone more knowledgeable could make it clear, what is the allowable voltage range


The only thing i know about it is

It behaved like on Intel's VCC_SA
lower allows lower procODT to run
Zen 1 had a signal "matchup" issue, soo it had to be perfectly accurate within 2-3mV else the FCLK wouldn't post
higher voltage made issues with memory signal integrity
950mV where consumer "normal" , 1050mV would be "the maximum limit" , yet 900mV has better signal integrity than 950mV

Only this. Heard here and there that it could make issues with high VDIMM as warnings that "it could kill my IMC" running both high with 1.6v+ and so on
But i heard it rather as roomers and nothing to it

Zen1 at the very first was at 900mV, but that make issues with 14nm IMC
Then it was defaulted to 750mV but that created memory boot holes with 3200MT/s - only 3400+ or 3133sub run
Soo lower was always better

Matisse run better on 700mV with 950mV CCD and 1000mV IOD (or 950/950). Soo SOC beyond 1025-1050+ run well for 12nm IMC with 28ohm procODT on high FCLK
It was common knowledge that lower procODT = higher potential FCLK . Soo lower cLDO_VDDP = lower procODT required
But more than this i've never seen anywhere mentioned, throughout these 3-4 years since Zen 1

But to add,
Since recent AGESA, Matisse only likes 900mV and higher like Vermeer ~ soo its range depends surely on something else
EDIT:


Robostyle said:


> and even on auto mb sets vddp to 1.1V


Oh and also that XMP bugs and other BIOS bugs after 1800 FCLK sometimes set 60ohm procODT with 1.1v cLDO_VDDP
Soo SOC up to architecture only could be 1.3v and was autocorrected
There where couple of buggy bioses, which even defined 1.15v cLDO_VDDP which result in insta dead units (dead IMC) ~ while Vermeer Bioses where buggy

It's complicated
But i would never run it beyond 1v, maaybe 1050mV on XOC - soo 1.3v can be pumped into it
Beyond 1.2v vSOC on Matisse tho is a bad idea
VDDG unless overritten with the UncoreOC flag (on Matisse) will be autocorrected and autoscaled
VDDG generally is complicated

"Do not trust Auto values"
Sometimes really is a good mentality & wording


----------



## byDenoso

Veii said:


> Matisse run better on 700mV with 950mV CCD and 1000mV IOD (or 950/950). Soo SOC beyond 1025-1050+ run well for 12nm IMC with 28ohm procODT on high FCLK
> It was common knowledge that lower procODT = higher potential FCLK . Soo lower cLDO_VDDP = lower procODT required
> But more than this i've never seen anywhere mentioned, throughout these 3-4 years since Zen 1


Is that true with the newer bioses? (like AGESA 1.2.0.2)
My Matisse get audio crackling and random reboots with VDDG_IOD anything lower than 1090mv.


----------



## Robostyle

Veii said:


> EDIT:
> 
> Oh and also that XMP bugs and other BIOS bugs after 1800 FCLK sometimes set 60ohm procODT with 1.1v cLDO_VDDP
> Soo SOC up to architecture only could be 1.3v and was autocorrected
> There where couple of buggy bioses, which even defined 1.15v cLDO_VDDP which result in insta dead units (dead IMC) ~ while Vermeer Bioses where buggy
> 
> It's complicated
> But i would never run it beyond 1v, maaybe 1050mV on XOC - soo 1.3v can be pumped into it
> Beyond 1.2v vSOC on Matisse tho is a bad idea
> VDDG unless overritten with the UncoreOC flag (on Matisse) will be autocorrected and autoscaled
> VDDG generally is complicated
> 
> "Do not trust Auto values"
> Sometimes really is a good mentality & wording


Yes, and thats exactly why I was asking, cause I never trusted auto figures on Intel, not even talking about amd’s agesas. 
I guess I should check PHY voltages and procODT once again - now I get stable 20 1usmus preset cycles, soc/vddg/ddr phy 1.15/1.05/1 volts, after I set RTT and CADs to auto. MB auto-set all CADBUS to 24, procODT 43 Ohm.

Might be the reason I cant reach 3866 and 4000 without wheas anymore - cause me changing settings prior to old guides, that apply no more to recent agesa.


----------



## garf333

Hello friends.

I'd like to ask as to what the consensus baseline we can expect with Micron Rev. B 16GB dies.

I have a set of Crucial Ballistix 3600 32GB (16GBx2), which are single rank Micron Rev. Bs

I've done a little bit of memory overclocking with Zen2 (3200 AFRs to 3600, 16-19-19-40 with tightened secondary timings, which is probably the first time I've hit the silicon lottery) but there doesn't seem to be much online 'documentation' of what the newer Rev B 16GBs can do apart from anecdotal evidence that these have the potential to overclock 'well'.

Would anyone have any good idea of what I should realistically be aiming for, and which secondary timings to pay attention to?

I usually just do:
Primary timings, TFAW, TRAS, the two SCLs and TRFC, and try for 1T without Gear Down.

Currently am testing this with a 5900X and an X570 Hero.

Thank you! :]


----------



## aditrex

mongoled said:


> Me thinks you should all be talking about CO in a different thread, it needs its own discussion and that should not be here !


Totally agree or I have better solution get in discord and chat there 😉


----------



## Robostyle

Okay, so that's what I'm talking about:


Spoiler: not stable

















Spoiler: Stable















And the only difference here is cldo vddp

950mV is just a bit different - instead of numerous thread crashes, testmem pops one single error at a random test.


----------



## Veii

aditrex said:


> Totally agree or I have better solution get in discord and chat there 😉


Put everyone of us in one discord, when once every 2 digit days there has to be a fight about viewpoint, experience and moral


Robostyle said:


> And the only difference here is cldo vddp


When TM5 keeps crashing cores, you have a more serious problem.
* TM5's SSE load is tiny, yet SOC load very big. Cores nearly never crash on TM5

Verify your voltages with y-cruncher all tests (4+ loops)
Same goes for procODT
Lower leads to better results. Excessive SOC does mostly harm than positive
Same goes for CPU OC, which looks rather as the issue
We can start with using +5mV positive offset, and PBO disabled , scalar X1 instead of predefined X2
~ both to wipe as much Brand-Based cheating as possible
fMAX enhancer disabled, Latency enhancer disabled, Dynamic Clock (ASUS Hero half PBO, half fixed ~ freq trick)

If you build your foundation on high values, only high values will be stable


byDenoso said:


> Is that true


?
The quote is big
SMU 56.45+ changed a lot of things
56.50 onwards changed a lot. Yet 1201,1202+ get erased by AMD
Can not judge about a timespan where ever boardpartner picked their own handful of USB, IO & PCH patches
Your bios experience will vary between every board in this timeframe. AGESA 1.1.0.0 and lower (SMU 56.30 and lower) remain consistent.








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com




&








AMD RAM overclocking


ZEN 2 - Matisse (7nm TSMC) s name,latency,FCLK,MT/s,timings,DIMMS,IC-type,part number,read,write,copy,VSOC,VDDG,VDIMM,VDDP,ProcODT,RTT,stability test,CPU,mainboard Reous,57,5 ns,1900 Mhz,3800 Mhz,<a href="https://abload.de/image.php?img=380014-14-13-1310000kzbkdb.png">14-13-14-13-30-44-247</a>...




docs.google.com




Matisse Sheets, speak for themselves
** i had bad experience with this board, lowest findable Bios was 1.1.0.0 Patch C (SMU 56.34) ~ which is common for newer boards


----------



## Kurt Krampmeier

Veii said:


> Spoiler: Results Demystified
> 
> 
> 
> 
> 
> 
> Code:
> 
> 
> Krapmeier's 5900X
> 
> CCX1
> FREQ 4100MHz
> 
> C01 18
> C02 17
> C03 16
> C04 17
> C05 16
> C06 16
> 
> FREQ 4125MHz
> 
> C01 17
> C02 15
> C03 15
> C04 16
> C05 14
> C06 15
> 
> FREQ 4150Mhz
> 
> C01 15
> C02 14
> C03 13
> C04 14
> C05 12
> C06 13
> 
> FREQ 4200MHz
> 
> C01 11
> C02 10
> C03 9
> C04 10
> C05 9
> C06 9
> 
> FREQ 4300MHz (+100Mhz , -8 CO)
> 
> C01 4
> C02 3 (should've been 2)
> C03 1
> C04 3
> C05 1
> C06 1
> 
> FREQ 4400MHz
> 
> C01 -3
> C02 -5 (error ~ should've been -6)
> C03 -6 (usually also -7)
> C04 -5
> C05 -7
> C06 -6
> 
> Fallback to
> FREQ 4375MHz (-25mhz, 2 CO ontop again)
> 
> C01 -2
> C02 -3
> C03 -4
> C04 -3
> C05 -5
> C06 -4
> =================================
> CCX2
> FREQ 4000MHz
> C07 15
> C08 17
> C09 15
> C10 18
> C11 18
> C12 20
> 
> FREQ 4025MHz
> C07 13
> C08 15
> C09 13
> C10 16
> C11 16
> C12 18
> 
> FREQ 4050MHz
> C07 11
> C08 14
> C09 11
> C10 14
> C11 14
> C12 16
> 
> FREQ 4100MHz (+50mhz, -4 CO)
> C07 8
> C08 10
> C09 7
> C10 10
> C11 10
> C12 13
> 
> FREQ 4125MHz
> C07 5 crash (should've been a +6 not a +5)
> C08 8
> C09 5
> C10 8
> C11 8
> C12 11
> 
> Fallback to
> REQ 4100MHz (-25mhz, 2 CO ontop again)
> C07 7
> C08 10
> C09 7
> C10 10
> C11 10
> C12 12
> 
> 
> 
> 
> 
> 
> 
> Spoiler: Math
> 
> 
> 
> 
> 
> 
> Code:
> 
> 
> RESULT:
> CCX1 FREQ 4375MHz
> CCX2 FREQ 4100MHz
> 
> C01 -2 / C07 +7
> C02 -3 / C08 +10
> C03 -4 / C09 +7
> C04 -3 / C10 +10
> C05 -5 / C11 +10
> C06 -4 / C12 +12
> 
> Requirement for CCX2 to reach 4375 = -24 CO
> Soo Result would be:
> C01 -2 / C07 -7
> C02 -3 / C08 -14
> C03 -4 / C09 -17
> C04 -3 / C10 -14
> C05 -5 / C11 -14
> C06 -4 / C12 -12
> 
> Then you just scale up
> -13 negative CO remaining as max = -12 = +100Mhz & +25mhz
> = Peak result for CCX 2 = 4.5Ghz allcore freq @
> C07 -20
> C08 -27
> C09 -30
> C10 -27
> C11 -27
> C12 -25
> 
> -12 for CCX 1 to reach 4.5 =
> C01 -14
> C02 -16
> C03 -15
> C04 -16
> C05 -18
> C06 -17
> 
> 
> 
> 
> 
> 
> 
> Code:
> 
> 
> RESULT:
> 
> C01 -14 / C07 -20
> C02 -16 / C08 -27
> C03 -15 / C09 -30
> C04 -16 / C10 -27
> C05 -18 / C11 -27
> C06 -17 / C12 -25
> 
> as input for the BIOS to Overdrive CTR
> * +/- 1 value of the threads that where crashing. But math remains identical
> Hope Yuri hurries up with Hydra , soo we don't have to do it by hand
> Tho overdriving Hydra surely (w)could work
> ** if you've shared the Core ACPI values, you can then match quality to it too
> ~ CTR can't get it perfect without extended testing
> X = 4 ACPI higher = +2 CO
> X = 4 ACPI values weaker = -2 CO
> According to:


me again. i have tested CO values with ctr2.1R06 v24 and it started promising but ended in fiasco. values work for step 1-4 - meaning they work with rather high VID only. settings managed to pull P2 setting up to 4750/4625 at default 1275mv. PX Profiles are up about 50Mhz each. below 1260mv nothing works anymore. i lowered the CO offsets and identified the cores that failed first. system crashed in CTR Step 5 profiling P1 with WHEA and APIC ID matching the worst CPPC cores. weak cores on my CPU seem to behave non predictable at lower voltages. when i dialed the CO values back (to approx 1/3) , it managed to get stable through OB calculation at least 8 steps. it always failed with low cppc cores (thread fail, no WHEA) on ccx2 and later interestingly with core0 that has highest cppc. i could however observe that ctr is aware of BIOS CO values respectively the resulting core voltage as it lowered CO values for those cores i dialed up in BIOS CO at about the same delta. 
Is CTR indeed able to change CO values per core?
as a result of that there is no additional stability at full load respectively more performance to be gained. OB results in CTR were significantly negative and performance from higher base clock per profile went gone. the only way this game has a point in my opinion is to level out the cores per ccx with bios CO and run CTR without OB.

to remain on topic: 

my 4 sticks of RAM still suck above 3600MT


----------



## Nighthog

garf333 said:


> Hello friends.
> 
> I'd like to ask as to what the consensus baseline we can expect with Micron Rev. B 16GB dies.
> 
> I have a set of Crucial Ballistix 3600 32GB (16GBx2), which are single rank Micron Rev. Bs
> 
> I've done a little bit of memory overclocking with Zen2 (3200 AFRs to 3600, 16-19-19-40 with tightened secondary timings, which is probably the first time I've hit the silicon lottery) but there doesn't seem to be much online 'documentation' of what the newer Rev B 16GBs can do apart from anecdotal evidence that these have the potential to overclock 'well'.
> 
> Would anyone have any good idea of what I should realistically be aiming for, and which secondary timings to pay attention to?
> 
> I usually just do:
> Primary timings, TFAW, TRAS, the two SCLs and TRFC, and try for 1T without Gear Down.
> 
> Currently am testing this with a 5900X and an X570 Hero.
> 
> Thank you! :]


Very similar results as good Micron 8Gbit Rev.E, if not overall better usually. They do quite great considering they are 16Gbit in comparison.
Just be aware there are 16Gbit Micron Rev.E which is horrible in comparison. Behaves like garbage 8Gbit Rev.E with a frequency wall ~4000Mhz. Where Rev.B can do 5000+ for the better expensive kits.
I don't know how well the cheaper kits do though but can't believe they are as bad as the 16Gbit Rev.E, not even close.



byDenoso said:


> Is that true with the newer bioses? (like AGESA 1.2.0.2)
> My Matisse get audio crackling and random reboots with VDDG_IOD anything lower than 1090mv.


Sample, silicon variance. Every sample have a different voltage tolerances. Yours isn't of the better quality that I've seen. You needing more than usual that I've seen reported.


----------



## garf333

Nighthog said:


> Very similar results as good Micron 8Gbit Rev.E, if not overall better usually. They do quite great considering they are 16Gbit in comparison.
> Just be aware there are 16Gbit Micron Rev.E which is horrible in comparison. Behaves like garbage 8Gbit Rev.E with a frequency wall ~4000Mhz. Where Rev.B can do 5000+ for the better expensive kits.
> I don't know how well the cheaper kits do though but can't believe they are as bad as the 16Gbit Rev.E, not even close.


Thanks! I guess I'll try using the DRAM settings from people with Rev E and start from there.

Was hoping to not have to try for every mhz, primary and secondary timing since there is so few info on 16GB Rev Bs on the 'net.

Cheers!


----------



## Nighthog

garf333 said:


> Thanks! I guess I'll try using the DRAM settings from people with Rev E and start from there.
> 
> Was hoping to not have to try for every mhz, primary and secondary timing since there is so few info on 16GB Rev Bs on the 'net.
> 
> Cheers!


Yeah, I was trying to get a Rev.B kit but ended up with the crap that was 16Gbit Rev.E... that kit is no good for anything else than XMP profile really. *3600 CL 18-22-22*... those are sold everywhere from third parties. *DO NOT BUY THOSE KITS!* They do no OC worth a damn from stock settings really.
Not when you can get Rev.B from Crucial directly!


----------



## Robostyle

Veii said:


> Put everyone of us in one discord, when once every 2 digit days there has to be a fight about viewpoint, experience and moral
> 
> When TM5 keeps crashing cores, you have a more serious problem.
> * TM5's SSE load is tiny, yet SOC load very big. Cores nearly never crash on TM5
> 
> Verify your voltages with y-cruncher all tests (4+ loops)
> Same goes for procODT
> Lower leads to better results. Excessive SOC does mostly harm than positive
> Same goes for CPU OC, which looks rather as the issue
> We can start with using +5mV positive offset, and PBO disabled , scalar X1 instead of predefined X2
> ~ both to wipe as much Brand-Based cheating as possible
> fMAX enhancer disabled, Latency enhancer disabled, Dynamic Clock (ASUS Hero half PBO, half fixed ~ freq trick)
> 
> If you build your foundation on high values, only high values will be stable
> 
> ?


I’ve tested my CO overclock with corecycler+cruncher overnight. Besides, with vddp at 950 mV cores don't crash, and 1V makes tm5 completely stable, no?


----------



## Nighthog

Robostyle said:


> I’ve tested my CO overclock with corecycler+cruncher overnight. Besides, with vddp at 950 mV cores don't crash, and 1V makes tm5 completely stable, no?


I've seen the higher frequency you go the need for more VDDP increases. You can not use 900-950mv @ 4800-5000Mhz. Will not even POST.
And Y-cruncher Prime95 Blend usually likes to eat even more than TM5 stability requires.


----------



## garf333

Nighthog said:


> Yeah, I was trying to get a Rev.B kit but ended up with the crap that was 16Gbit Rev.E... that kit is no good for anything else than XMP profile really. *3600 CL 18-22-22*... those are sold everywhere from third parties. *DO NOT BUY THOSE KITS!* They do no OC worth a damn from stock settings really.
> Not when you can get Rev.B from Crucial directly!


3600 CL18-22-22 should be from the Corsair LPX kits I guess?

Picked up my Crucial Ballistix kit from another country actually due to crazy prices here, and was just hoping I'd get something that ran properly.

Pleasantly surprising then that this should do decently on average :]

On to 3800 and tightened timings! :]


----------



## Robostyle

Nighthog said:


> I've seen the higher frequency you go the need for more VDDP increases. You can not use 900-950mv @ 4800-5000Mhz. Will not even POST.
> And Y-cruncher Prime95 Blend usually likes to eat even more than TM5 stability requires.


You mean cores freq, not memory within 1:2?


----------



## Nighthog

garf333 said:


> 3600 CL18-22-22 should be from the Corsair LPX kits I guess?


ALl vendors have these kits now!
I bought Kingston HyperX...
You can get G.skill & PNY, but also Team Group!

They are a favourite in the 16GB kits now! Single rank 16Gbit Rev.E... Garbage, must be cheap for Micron to manufacture.



Robostyle said:


> You mean cores freq, not memory within 1:2?


Memory frequency in 2:1 mode. It's kinda worth it to run 2:1 @5000Mhz but really you want to go above that I've noted now that I've used 5000Mhz for a little bit.
But Memory get temperature limit around here in this range.


----------



## garf333

Nighthog said:


> ALl vendors have these kits now!
> I bought Kingston HyperX...
> You can get G.skill & PNY, but also Team Group!
> 
> They are a favourite in the 16GB kits now! Single rank 16Gbit Rev.E... Garbage, must be cheap for Micron to manufacture.


Interesting. I always thought GSkill used Hynix CJR/DJRs and Samsung B Dies.

The others... the local price was too high for me to consider -- never did my research. I guess I should really be happy with these :]


----------



## Nighthog

garf333 said:


> Interesting. I always thought GSkill used Hynix CJR/DJRs and Samsung B Dies.
> 
> The others... the local price was too high for me to consider -- never did my research. I guess I should really be happy with these :]


CJR, DJR & Samsung B-die are all 8Gbit...

Crucial is the only one I know to actually use the Micron 16Gbit Rev.B on their kits.
16Gbit Rev.E isn't capable of doing 16-18-18 @ 3600Mhz.
You can get dual-rank 8Gbit Rev.E though in the 16GB kits (3600 16-18-18) though but that was before they had Micron 16Gbit Rev.B to use.


----------



## XPEHOPE3

Nighthog said:


> Very similar results as good Micron 8Gbit Rev.E, if not overall better usually


Why then Rev. B rarely if ever occurs in these lists?


Veii said:


> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> AMD RAM overclocking
> 
> 
> ZEN 2 - Matisse (7nm TSMC) s name,latency,FCLK,MT/s,timings,DIMMS,IC-type,part number,read,write,copy,VSOC,VDDG,VDIMM,VDDP,ProcODT,RTT,stability test,CPU,mainboard Reous,57,5 ns,1900 Mhz,3800 Mhz,<a href="https://abload.de/image.php?img=380014-14-13-1310000kzbkdb.png">14-13-14-13-30-44-247</a>...
> 
> 
> 
> 
> docs.google.com


----------



## Nighthog

XPEHOPE3 said:


> Why then Rev. B rarely if ever occurs in these lists?


Because no one buys the Expensive kits they are sold in from Crucial.
You want to buy 4000Mhz CL18-19-18 Crucial Ballistix max 2x16GB? or the more expensive 4400Mhz CL-19-19-19 2x16GB Ballistix MAX?
Or even the top binned Crucial Ballistix MAX 5100Mhz 2x8GB kits for 700-1000$ USD?

Not until recently that were the only kits you got them in.
Now if you are lucky you might get them in the 3600 16-18-18 2x16 (32GB) kits. But some do still get Dual-rank Micron 8Gbit Rev.E in those.

A better bet to get 16Gbit Rev.B would be 2x32GB (64GB) 3600 16-18-18. Nothing else does manage the timings from Crucial, but they are dual-rank so no idea on what they might do.


----------



## BarrettDotFifty

Can someone please explain how to read and use the different tRFC multipliers from the tRFC calculator?








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com


----------



## Mach3.2

Nighthog said:


> Not until recently that were the only kits you got them in.
> Now if you are lucky you might get them in the 3600 16-18-18 2x16 (32GB) kits. But some do still get Dual-rank Micron 8Gbit Rev.E in those.


I think newly manufactured 2*16GB 3600 16-18-18-38 kits are all single rank 16GB Rev. B ICs. I know mine is.


----------



## Nighthog

Mach3.2 said:


> I think newly manufactured 2*16GB 3600 16-18-18-38 kits are all single rank 16GB Rev. B ICs. I know mine is.


Yeah, there is still older stock around though so you need to know you might not get them. Or if you buy second-hand you might get dual-rank.


----------



## byDenoso

i've found a Hard Wall in my Kit, my RCD can't go lower than 20 and tRC from 58.Still i managed to get the most out of it.


----------



## craxton

@ ANY-OF-YOU
does any of you fellas know of some good B-die sticks (DR) only, thatll do 3800 c14 without issues????
decently priced at that???
if so @ me please, or reply to this. looking to get "away" from this 4x8 config to give DR a try and get a few more toys to play with.


----------



## Veii

craxton said:


> @ ANY-OF-YOU
> does any of you fellas know of some good B-die sticks (DR) only, thatll do 3800 c14 without issues????
> decently priced at that???
> if so @ me please, or reply to this. looking to get "away" from this 4x8 config to give DR a try and get a few more toys to play with.


4000 C16-16-16 @ 1.4v should do it easily 
But the 4000-14-15-15 @ 1.55v might not (tho math says it could work)

Ripjaws appear to have a bad heatsink (half coverage) and RGB TridentZ's have RGB that heats dimms up ~ but a 10 layer PCB instead of 8
Both are A2
For the Ripjaws, something like the Corsair CMDAF2 , or the Alphacool D-Ram ~ cooler, should do it
It remains IC lottery
Another good set seems to be TeamGroup T-Force Xtreem ARGB [TF10D432G3600HC14CDC01] which are also rated @ 1.45v (underrated ones)
But both Trident & Teamgroup's are RGB , which is annoying 

* I personally would mind high voltage XMP kits. These are mostly binned and there is no headroom left
something sub 1.5v has headroom. At least one step.
Something at 1.35v can have over 3 tRCD's headroom , sometimes 4 ~ depends on your luck
** I'd also prefer 4000 over 3600 kits, to rule out PCB luck ~ but you still have IC lottery there

EDIT:
Thermaltake seems also to have some heatsinks aside from Alphacool, Byksi & GALAX (same mounting mechanism)








But basic Ripjaws where designed for A0 layout, and the heatsink + thermal pad only covers half of the IC for A1 & A2 PCB
They stay cool, i mean it functions ~ but in this case you can just remove it and put a ram cooler ontop (fan or passive)


----------



## thigobr

Talking about Micron 16Gbit B... This is what I have so far on the Crucial 3600MHz 16-18-18 2x32GB kit. I tried CL15 but it's a no go at least until 1.46V. I think it's a good result nevertheless and being Dual Rank the performance is great. They can get hot though under stress. My case have good air flow but still they get up to 60°C when running TM5 with only 1.33V VDIMM.


----------



## kim nk

Hello We share ROG CROSSHAIR VIII DARK HERO 3701 BETA BIOS. ComboPIv2_1203_PatchA version like 3601 BIOS. The guitar bug has been fixed.

I got it from the website I go to often.









쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네


안녕하세요ROG CROSSHAIR VIII DARK HERO 3701 BETA 바이오스 공유해 드립니다3601 바이오스와 같은 ComboPIv2_1203_PatchA 버전입니다기타



coolenjoy.net










ROG-CROSSHAIR-VIII-DARK-HERO-ASUS-3701.7z







drive.google.com






This Giskill Neo cl14 4000 (xmp 14-15-15-35 1.55v) test showed that if the cl14 Real1t gives a voltage of 1.55v or higher, it will cause a silent error, but on the contrary, the voltage will be lowered to 1.52v, and all the errors will disappear... I knew that 4000 clock cl14 would normally take more than 1.55v, but on the other hand, the voltage was lowered and the timing was lowered to 1.52v even though it was about trp 12 trfc 246. First of all, trcdrd 14 failed and it was 15.










Currently rtt auto, but rtt will try later with 7/0/6.

I didn't know the Giskill Neo cl14 4000 (xmp) memory voltage should be this low to avoid errors, but it's strange that it's been solved by lowering the voltage.

Memory timing will be newly adjusted. There were so many wrong timing that it was amazing that only the memory voltage part turned out to be this low. Hah!


----------



## Deonzy

Yo guys! I recently moved from Intel to Amd and got myself a 5950x. Completely new to how overclocking on ryzen works.

I got 4x8 G.skill 4400 mhz cl 16-19-19-39 1.5v
F4-4400C16-8GTZR

It boots 3800/1900 cl 14-14-14 1.5v but no matter what I do, or voltages, it keeps spitting error 6 in tm5 1usmus. is there anyone here that got time to help a newbie like me?

Edit: 3800 / 1900 cl 16-19-19-39 works perfectly fine at 1.4v lmao, prolly even lower dram voltage


----------



## ManniX-ITA

Deonzy said:


> It boots 3800/1900 cl 14-14-14 1.5v but no matter what I do, or voltages, it keeps spitting error 6 in tm5 1usmus.


Start posting a Zentimings screenshot


----------



## Robostyle

Getting really tired of this cherry-picking voltages between soc, phy, etc.



Veii said:


> Same goes for procODT
> Lower leads to better results. Excessive SOC does mostly harm than positive
> We can start with using +5mV positive offset, and PBO disabled , scalar X1 instead of predefined X2
> ~ both to wipe as much Brand-Based cheating as possible


BTW, I've already asked about offset - is it safe to utilize offsets? I saw Vcore spikes going above amd spec 1.55V when idle, light load, or load shifts (transient response issue?) with +50 mV offset, even! with PBO and other "enhancements" forced off, at stock. Under load Vcore remained unchanged.


----------



## Veii

New voltages, new stable shenanigans
But i'm not sure what to think about it
4033 posts always, 4067 posts rarely , 4133 doesn't . . .
2100 FCLK posts consistently & holds peak write, 2133 barely but can potentially work (throttles a slight bit)


Spoiler






















Appears to me that cLDO_VDDP manages MCLK and has nothing to do with FCLK
But then 1.8v rail has direct effect preventing fabric package throttle, soo both theories are questionable to say the least
Some other resistance is preventing it, if procODT that low has benefits & you'd need near 2v on a 1.8v rail 

And little experiment,
SCL vs tWRRD cut








Mostly it should showcase that tRAS = tRCD+tRTP & tRRD_L = tRTP
Function well together ~ might've found a method to override tRAS min (21) and tWR min (10)

Voltages to utilize 28.2ohm,
CPU VDD 1.8v = 1.93v
CPU VDDP / Standby VDDP = 860mV
cLDO_VDDP 820mV
VDDG CCD 980mV
VDDG IOD 1120mV
VSOC 1.26 (120mV lift ~ well it was for 2133, but 2100 works well till 1.2125vSOC)

Positive:
ClkDrvStr 120 is no issue

Big negative:
Broken memory training even with 120-20-60-20 & 1.7v
Nothing you can do to bruteforce it
And RTT_WR /2 seems to not work, yet 120ClkDrvStr functions easily

* Probably fixable with MBIST fix , but RU Tool on AMD CBS [3A997502-647A-4C82-998E-52EF9486A247]
Doesn't do anything, somehow settings applied do not stick (they stick but nothing happens)
Still waiting for new AGESA soo just fooling around
tRAS trick functions well 
** If i get to fix somehow broken memory training, then this voltage method is better than 900mV+
It does show 1.8v rail scaling beyond 1.83v up till 2,030mV ~ together with procODT, but i don't know what to think about this


Veii said:


> Big negative:
> Broken memory training even with 120-20-60-20 & 1.7v


1/6 reboots posts and is rock stable
Big mess. Considerable, but still fooling around with HEX. Need to fix memory training mess
Only sharing proof of concept


----------



## Yviena

I dunno if i like how the new CO works in 1.2.0.2+ agesa i would rather have both lower voltages/heat/higher frequencies and just find the highest undervolt that works stability wise than the cores having a set voltage with the new agesa.


----------



## adversary

@Veii 

is 1.8V rail needed to play with for 1900 FCLK (I run 1.57V RAM voltage and low and aggressive timings), or it is fine to leave it on Auto? dual-rank 32GB, RTT 6/3/3, 34.3 ProcODT, 60-20-20-20 (3-3-15 setup timings).

and wait wait.. is Standby VDDP actually CPU VDDP you mentioned already long ago? I have Asus board, and there is Standby VDDP. did not ever touch it (1201A AGESA now) and it shows 0.900V.

some days ago I set different CLDO VDDP, CCD and IOD voltage, and tested - all stable, 0 errors anywhere.
now it is :
CLDO VDDP - 0.88V
CCD - 0.93V
IOD - 0.98V
SOC - Auto - which is set in BIOS as 1.1V, but in ZenTimings it is 1.0875V (and under some load it may fall to 1.0813V I think)


----------



## PJVol

Veii said:


> Appears to me that cLDO_VDDP manages MCLK and has nothing to do with FCLK


Can't understand quite a while, why people believe it has to.
But, tbh, can't see it manage MCLK either ))


----------



## ManniX-ITA

PJVol said:


> Can't understand quite a while, why people believe it has to.
> But, tbh, can't see it manage MCLK either ))


Sorry, what is exactly the meaning of "manage" here?


----------



## Robostyle

@Veii
How does this thing determine sil quality?









Do other functions - get freq, get volt, curve scales work as intended?


----------



## domdtxdissar

domdtxdissar said:


> So i decided to also test this in windows11... Pretty much same settings as above.
> 
> 5950x @ 4700/4600 static OC, SMT enabled
> 4x8GB memory sticks
> 
> 
> 
> 
> 
> 
> 
> 
> 1800:3600 T1 setup-time + CL14-14-14-14
> *19107.4 H/S over 15min run*
> upto 605 H/S per core
> 
> 
> 
> 
> 
> 
> 
> 
> 1900:3800 T1 setup-time + CL14-14-14-14 and the tweaks i got suggested a few pages back (tRRDL=5, tWR=10 and tRTP=5)
> *19769 H/S over 15min run*
> upto 625 H/S per core
> 
> 
> 
> 
> 
> 
> 
> 
> 1900:3800 T1 setup-time + CL14-14-14-14
> *19855.7 H/S over 15min run*
> upto 632 H/S per core
> 
> A few thoughts on the runs above:
> 
> Scaling between 1800:3600 and 1900:3800 seems pretty good. Theoretical max scaling should be 5.5%. (1900/1800)
> Iam seeing upwards to ~4% improved real-performance (19769/19107) with the only change being fclk 1800 vs 1900.
> 
> 
> tRRDL=5, tWR=10 and tRTP=5 setup performed alittle worse then my regular "flat cl 14" setup
> 
> For fun i also tried a setup with tighter timings then the flat cl14-14-14-14 baseline.. To my big surprise it performed even better
> In theory (math) it should not perform better, but i cant argue with the numbers im seeing:
> 
> 
> 
> 
> 
> 
> 
> 
> 1900:3800 T1 setup-time + CL14-8-14-12-24-36
> *20038.6 H/S over 15min run*
> upto 638 H/S per core
> 
> *Can any of you guys make heads or tails of this ? *
> Seems like i found me some new daily 24/7 settings by just playing around.


So i have been stability testing my new 24/7 settings, pretty happy with the results 
*51.1ns* with both CCD enabled + 4 memory sticks @ 1.54vdimm:








Full stresstesting:
20 cycles TESTmem 1usmns cfg
3000% in Karhu RAM Test
y-cruncher all stresstests, 4 iterations (SFT is a 300 watt load with current settings)








Like *kim nk *said a few posts back, i also had to lower vdimm to complete testmem without errors.. With older agesa's i could not dream about running these settings at only 1.54 vdimm in bios, but setting it higher gives error 2-5-6 and 12 in TESTmem on this SMU version 56.50.0


----------



## PJVol

ManniX-ITA said:


> Sorry, what is exactly the meaning of "manage" here?


Can't say for sure, but hardly "power supply" was meant. Probably more like "affecting", as long as it ensures data encoding and signalling integrity...?


----------



## dante`afk

Used house moving to change my motherboard and stock up on more RAM. on the right side as comparison with previous 32gb.











any tips for optimizations?


----------



## Veii

adversary said:


> @Veii
> 
> is 1.8V rail needed to play with for 1900 FCLK (I run 1.57V RAM voltage and low and aggressive timings), or it is fine to leave it on Auto? dual-rank 32GB, RTT 6/3/3, 34.3 ProcODT, 60-20-20-20 (3-3-15 setup timings).


Not at all. Nobody should have problems posting till 2000 FCLK

For me on stock it always was 30mV higher @ 1.83v
I have to remember and doublecheck, but VPPM i think was it, is from 2.5v to 2.55v lifted
I've run both 2.5v rails at 2.5v as they didnt show obvious changes 

There is still improvement up to 1.93v instead of 1.8(3)v 
But this also seems to depend on procODT
The lower the procODT (requires low cLDO_VDDP) the higher the required 1.8v for preventing throttle
If procODT is too high (which requires higher cLDO_VDDP) then it can actually cause instabilities
I feel if SOC is high and excessive, it also requires higher 1.8v rail
But 1.83v shouldn't be "preventing" FCLK from posting
Higher ranges depend fully on signal integrity and low procODT.
Got it down from 20+ ns autocorrection, to only +4
It stillt throttles , soo its unusable so far




adversary said:


> and wait wait.. is Standby VDDP actually CPU VDDP you mentioned already long ago? I have Asus board, and there is Standby VDDP. did not ever touch it (1201A AGESA now) and it shows 0.900V.


That's the only 2nd VDDP on ASUS Boards
But it never went bellow 900mV for me
In both cases it wasn't useful 


Robostyle said:


> @Veii
> How does this thing determine sil quality?
> View attachment 2516970
> 
> 
> Do other functions - get freq, get volt, curve scales work as intended?


Only ASUS engineers know
It utilises FIT readings, but also does a short allcore test
Its unclear, as CO does not affect it strongly -/+ 1 value
Thermals do tho


PJVol said:


> Can't understand quite a while, why people believe it has to.
> But, tbh, can't see it manage MCLK either ))


Yes as written "both have to be nonsense"
But it surely affects Memory Training success, together with used procODT


----------



## PJVol

Veii said:


> But it surely affects Memory Training success, together with used procODT


Btw, do you know by a chance, what voltages hwinfo report in superIO tab as VIN3 and VIN9 on ASRock boards? I suspect one of it might be cpu vddp.
VIN3 almost constantly 0.920V and VIN9 in 0.848-0.856 range


----------



## Robostyle

I figured out why I got occasional test crashes while being "stable". Again, it's SOC mostly and seems like I'm way off understanding how to OC ryzens.
I have single wheas popping off even at 1900 fclk


Spoiler: 1















Already mentioned before, I have a feeling it's all about balancing between vDIMM, vSOC, and VDDP - but maybe I'm losing something - so, again - what is required to make zen 3 stable at 1900-2000 fclk?


----------



## Veii

PJVol said:


> Btw, do you know by a chance, what voltages hwinfo report in superIO tab as VIN3 and VIN9 on ASRock boards? I suspect one of it might be cpu vddp.
> VIN3 almost constantly 0.920V and VIN9 in 0.848-0.856 range


I don't think we can compare that








Our PWM Controller (setup) is identical (nearly), soo a crossflash can function
But out Mosfets are too different








VIN3 appears to be something different
VIN2 appears to be CPU 1.8v Rail , but i am not sure. Wonder about VTT
Nah ours are too different - BUT , you can dig a bit
I've tested yesterday 1203A Beta on our boards, and with AMIBCP you can change the flags ~ then CTRL+S & still keep up integrity


Spoiler





















Maybe give it a try, so you can dig with RU Tool or other setup_var tools ~ easier than HEX modifying the bios and downconverting
If you only change this, it won't break the signature


dante`afk said:


> any tips for optimizations?


Enable Bank Group Swap and disable the BGS Alt one
You miss a lot of Write Bandwidth


----------



## Deonzy

@Veii what would you say is max soc voltage for daily use? on a 5950x


----------



## Veii

Deonzy said:


> @Veii what would you say is max soc voltage for daily use? on a 5950x











AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




1.25 till 1.275 ~ 1.3v is unreasonable, but within limit
1.2125 [GET] is plenty for 2100 FCLK ~ 21W cut into powerdraw
< 1.25v is alright

SOC voltage won't be your limit. Thermals & EDC FUSE Limit will be


----------



## craxton

Veii said:


> 4000 C16-16-16


well considering around the "only ones i found were, RGB i find some 4000c19 1.35v
(solid black ones)
but then again?


Veii said:


> TridentZ's have RGB that heats dimms up


much rather prefer to stay away from more rgb stuff lol but there is this 
to which not many reviews on it? 
(does anyone here have this, know someone who uses it?) or know if its "worth
while"?
then again, i prefer not to swap out the AIO i have now, as its keeping the 5800x pretty cool


Spoiler



(issue on the 5600x being "hot" was 100% to much thermal paste.)





Veii said:


> I'd also prefer 4000 over 3600


how about the 3866 18-19-19-39 1.35?
same kit as the 4000 19-19-19-39 1.35
newegg  i did however add a "90"mm fan blowing "towards the dimms, 
but with recent events with me getting "covid19" found out today, ive not felt to 
great to tinker with nearly anything which is why the delayed response. 

id have to suspect both these kits would be the "same" since both have the same timings etc? but neither have RGB.....


----------



## Veii

craxton said:


> well considering around the "only ones i found were, RGB i find some 4000c19 1.35v


4000 C19-19-19 is a too "low" bin
My A0's are such, but on them i know at least they are b-dies
The 4000 18-19-19 are Rev.E , but could be also Rev.B for 16Gb Dimms
~ generally bad idea, unless you know for certain, that it is b-die



craxton said:


> but there is this
> to which not many reviews on it?


They should've pushed a newer version out, still waiting for it
Looks interesting but i am not sure
It's just the same principle like every other one















Just that here you'd actually heat up the dimms by the CPU loop
But idk, air is enough. Only the heatsinks are appealing.
You can't hold your loop sub ambient. And air-resolves are just around 4-5c over ambient (for me) with peaks at 12c over ambient.
Hard to keep a whole loop only 5c over ambient on max load 


craxton said:


> was 100% to much thermal paste.


thermal isolation paste ? 
What did you even use ?


craxton said:


> how about the 3866 18-19-19-39 1.35?


I think it could be Micron, too low bin for b-die

Non RGB i ment these [F4-4000C16D-32GVKA]
But the heatspreader needs a swap & trident's apparently are 10 layer while these are supposed to be 8


----------



## craxton

Veii said:


> generally bad idea, unless you know for certain, that it is b-die


thats just it tho, i used B-die finder thru google search lol and somehow google sent me
the wrong stuff anyhow.



Veii said:


> What did you even use


MX-4 (2019) gotta 20gram tube of it settin here. 
but i suppose when installing it while having a dispute with my ol lady
i somehow overshot it not realizing it while spreading it out. 



Veii said:


> The 4000 18-19-19 are Rev.E , but could be also Rev.B for 16Gb Dimms


thats something ill steer away from if i can. (any dimms on amazon) 
even if "model" numbers match it wont matter somehow amazon sends 1 number/letter off and you get some 
horrid samsung die that wont do 3800mhz cl19 or for me thats what happened anyhow.... 



Veii said:


> Just that here you'd actually heat up the dimms by the CPU loop


if one was two get a "pump" and simply void their warranty and remove the cpu cooler pump. 
that might work out, but a little more work than it might be worth..to bad i didnt have my old aio to jus test this on..
dont however have many options for galax options period here in the us.
in fact little to none... unless paying an up-scaled price. (talking about adding a water cooling block/240rad to the 4 dimms i have now...




Veii said:


> F4-4000C16D-32GVKA


shew, and here i thought a 5800x at discount prices was still kinda high..
but i suppose thats the price one pays for such a bin.


----------



## byDenoso

i've found then i get better scores (Both in cinebench and AIDA64) with the CPPC and CPPC Preferred Cores disabled.
is there any explanation for that?


----------



## Veii

craxton said:


> dont however have many options for galax options period here in the us.


Galax is just another company who does use the nearly identical design ~ is what i wanted to say
Bykski, Alphacool, EK ~ all are close to identical
I'd try to get alphacool's , but then you really don't have to try such absurd thing
Probably a 120/140mm rad is enough for memory only , but i still feel it's overkill
Plain fans on a thick heatspreader  
Just without the waterblock


----------



## ManniX-ITA

craxton said:


> in fact little to none... unless paying an up-scaled price.


problem I see with that solution is that if something breaks you have to trash everything

for sure more expensive but:








Alphacool Eisbaer Pro Aurora 360 CPU AIO


The Alphacool Eisbaer Pro Aurora CPU AIO water cooler is a special development for processors with particularly large CPU dies. These include the AMD Threadripper and Epyc processors and the Intel CPUs for the LGA 3647 and LGA 4189...




www.aquatuning.us





plus:









Alphacool D-RAM Cooler X4 Universal - Acetal Black Nickel


With the new D-RAM coolers all desired memory chips can be cooled. This cooling block is screwed onto the optional cooling modules or existing heatspreader with a hole spacing of 110mm (like the Corsair Dominator). Due to its black...




www.aquatuning.us





x2:








Alphacool D-RAM module (for Alphacool D-RAM cooler) - black 2 pieces


Due to the new Alphacool D-RAM modules all memory blocks can easily and quickly be equipped with water coolers! A fight against the underrated heat source "memory" has been announced with the new system of the Alphacool D-RAM coolers ....




www.aquatuning.us













Alphacool Eisbaer TPV Extension Set 90° (tubes and fittings)


The Alphacool Eisbaer TPV Extension Set 90° offers the easiest way to connect the expandable AIO systems from Alphacool with other components. The Extension Set is compatible with all Alphacool AIO systems for processors and graphics...




www.aquatuning.us





should be definitely more performant and if something breaks you can replace the single parts and even slowly upgrade to a real custom loop
the RAM block is excellent
just the fans are not that good
but over time you can replace them with 3 x Corsair ML120 that are awesome


----------



## Robostyle

Wont it break the warranty from gskill if you replace their heatsink plastic with waterblock?


----------



## mongoled

Darn you guys, im close to purchasing RAM blocks

🤣🤣😂


----------



## Veii

mongoled said:


> Darn you guys, im close to purchasing RAM blocks
> 
> 🤣🤣😂


Riding the same boat.
It's "just" 20 bucks, but "is it worth it" 🤭


----------



## mongoled

Veii said:


> Riding the same boat.
> It's "just" 20 bucks, but "is it worth it" 🤭


More like over 100€ 

2 x Alphacool D-RAM module (for Alphacool D-RAM cooler) - black 2 pieces - 42.38€
1 x Alphacool D-RAM Cooler X4 Universal - Acryl Black Nickel - 49.79€
1 x Shipping - 17.00€


----------



## Veii

mongoled said:


> More like over 100€
> 
> 2 x Alphacool D-RAM module (for Alphacool D-RAM cooler) - black 2 pieces - 42.38€
> 1 x Alphacool D-RAM Cooler X4 Universal - Acryl Black Nickel - 49.79€
> 1 x Shipping - 17.00€


Hmm you want to go deep
On that topic ~ the D-Ram blocks where "redone"
If you buy them from external sources, the screws where rather ring like and round (bit bulky).
Soo some people reported "bented looking" RAMs on the slot on the old batches
They swapped it to flat screws now (probably since a year?), soo the issue should be gone (i think we have an alphacool rep over here)

But then, is it really worth to go liquid ~ can you hold a delta of sub 5c over ambient, on load
I hesitate for the basic blocks alone, because it won't make them that much better * ~ as they don't heat up anyways near the 1.6v range
Don't really plan to daily 1.7 too ~ sooo i don't know about the reason
But they look sleek & have a small footprint 
* it won't magically resolve my issues with ram either, that's just on me & not the heat
EDIT:


mongoled said:


> 2 x Alphacool D-RAM module (for Alphacool D-RAM cooler) - black 2 pieces - 42.38€
> 
> 
> Veii said:
> 
> 
> 
> Hmm you want to go deep
Click to expand...

Include a 1mm thermal pad, for single rank kits (four)
If we're talking 4x8Gb here


----------



## Sleepycat

I run 4 sticks of B-die and hit 59ºC at only 3600 MHz due to poor airflow with the 4 sticks under the NH-U12A. I got this cheap piece of crap for $15, which is noisy at high RPM. Temps dropped to 43 ºC under load, so I'm happy. Just needed to limit the RAM cooler's fan RPM to 2500 rpm and it is silent.


----------



## mongoled

Veii said:


> Hmm you want to go deep
> On that topic ~ the D-Ram blocks where "redone"
> If you buy them from external sources, the screws where rather ring like and round (bit bulky).
> Soo some people reported "bented looking" RAMs on the slot on the old batches
> They swapped it to flat screws now (probably since a year?), soo the issue should be gone (i think we have an alphacool rep over here)
> 
> But then, is it really worth to go liquid
> I hesitate for the basic blocks alone, because it won't make them that much better ~ as they don't heat up anyways near the 1.6v range
> Don't really plan to daily 1.7 too ~ sooo i don't know about the reason
> But they look sleek & have a small footprint


I was not aware of the issue with prior blocks, know the name of the rep ?

Well, as I have a loop and considering I am using a fan to cool the 4 sticks I may as well watercool the RAM as you have said it makes them sleek 



The main things that is stopping me is ease of swapping sticks.


----------



## XPEHOPE3

@Sleepycat @mongoled @ManniX-ITA 
If anyone's interested, I recently posted about my RAM cooling solution
Currently at 31C ambient and TM5 1usmus_v3 load I get 44C at 3867MHz


----------



## PJVol

Veii said:


> If you only change this, it won't break the signature


Did you mean just flags or anything in bios setup menu as well, though every entry there showed in amibcp as kinda enabled (not at my pc atm, sorry).
Can you double check which are safe to modify and which aren't?

PS: I haven't got "usb flashback" feature on x4, if something goes wrong


----------



## ManniX-ITA

Veii said:


> It's "just" 20 bucks, but "is it worth it"


I've already replaced the original HS on the Trident Z RGB kit 4000C16 with gelid Extreme thermal pads (which are very expensive).
I think the difference was 3c-5c.
It's something but it's worth it only if you plan to move to water cooling.
Otherwise just keep the original HS, buy something like posted by @Sleepycat and replace the fans with a couple of Noctua.
Much more effective, probably cheaper, no need to spend one hour to remove the original HS.



Robostyle said:


> Wont it break the warranty from gskill if you replace their heatsink plastic with waterblock?


Maybe. In theory. You can buy a cheap thermal bi-adhesive an re-mount them.
Unlikely anybody would notice it


----------



## Veii

PJVol said:


> Did you mean just flags or anything in bios setup menu as well, though every entry there showed in amibcp as kinda enabled (not at my pc atm, sorry).
> Can you double check which are safe to modify and which aren't?
> 
> PS: I haven't got "usb flashback" feature on x4, if something goes wrong


mmm, i neither
Nono, just the two flags for setup variable
Every other change from AMIBCP does break the signature capsule ~ soo the tool alone was not that useful on ASRock bioses
This here works, no need to even split the bios ~ just open , disable both , CTRL+S and flash with amidos
Latest AMIFLASH with GAN is 5.06.00 , but our bioses are too new
Latest one without is 5.11.01.1745 ~ or the one on the screenshot.
For real edits , you need to break the capsule ~ two of them AMDs and ASRocks.

This change here only allows tools like RU or similar, to do UEFI HEX modifications in realtime. Else there was lock #3
This is the easier metthod, with AMIBCP. It still seems to pass secure flash check


ManniX-ITA said:


> I've already replaced the original HS on the Trident Z RGB kit 4000C16 with gelid Extreme thermal pads (which are very expensive).
> I think the difference was 3c-5c.
> It's something but it's worth it only if you plan to move to water cooling.


mmm,
They look appealing for low profile "actual heatsinks"
Question is between "no heatsink" or "better heatsink" ~ just that i'm not thermally constrained with weak RTT's


----------



## Blameless

New AGESA 1.2.0.3b hasn't done anything to improve the FCLK range on my ASRock B550 Phantom Gaming ITX/AX. No errors, even at conservative voltages for 1900FLCK, but gobs at 1933.

Haven't tried some of the more radical/innovative settings mentioned recently, and I'm a bit hesitant to get too adventurous with this board as there is no good way to fixed badly corrupted firmware...single BIOS, no flashback feature, etc.



Veii said:


> But then 1.8v rail has direct effect preventing fabric package throttle


Isn't the 1.8v rail on this platform essentially CPU PLL/VCO voltage?



PJVol said:


> Can't say for sure, but hardly "power supply" was meant. Probably more like "affecting", as long as it ensures data encoding and signalling integrity...?


I'm pretty sure both cLOD_VDDP and (CPU) VDDP are explicitly related to the memory PHY and could well be what powers it. Regardless, I definitely encounter memory issues first if either are outside a certain range.

Of course, anything related to memory clock probably has _some_ influence on FCLK stabilty and vice versa as the clocks are either outright linked or at the very least memory traffic still has to go through the Fabric to reach the memory controller.


----------



## spajdr

After reading some mention of 1.8V, which might do something about getting a higher FCLK than 1900+, I wanted to try increasing it, but realized that in the bios I can only set it to 1.8 or 1.85V, nothing more, even though the description lists steps of 0.05V.


----------



## FleischmannTV

@Veii 

Why is getting RttWr=RZQ/2 to run a big benefit in your opinion?


----------



## PJVol

Blameless said:


> I'm pretty sure both cLOD_VDDP and (CPU) VDDP are explicitly related to the memory PHY


I wouldn't be so sure regarding the latter, cause it has it's own power rail on am4 socket, whereas the former derived from VCCR_MEMIO

@ManniX-ITA
Forza Italia!


----------



## ManniX-ITA

PJVol said:


> Forza Italia!


Oh man, suffering since the 2nd minute 
But it's coming Rome!


----------



## Blameless

PJVol said:


> I wouldn't be so sure regarding the latter, cause it has it's own power rail on am4 socket, wheras the former derived from VCCR_MEMIO


Why would that be a contraindication of it being related to the memory PHY? The only descriptions I can find of CPU VDDP on AM4 is "the voltage for the transistor that sets memory contents", which part of what a memory PHY does. The memory PHY is part of the I/O-die, which is part of the CPU. Any DRAM PHY is almost certain to have multiple input voltages. I don't know exactly what 'CPU VDDP' is doing on AM4, but if where doing something unrelated to the vague definition commonly cited, I'd expect to see some mention of it somewhere and wouldn't be able to influence memory stability by manipulating it.


----------



## PJVol

Blameless said:


> Why would that be a contraindication of it being related to the memory PHY? The only descriptions I can find of CPU VDDP on AM4 is "the voltage for the transistor that sets memory contents", which part of what a memory PHY does. The memory PHY is part of the I/O-die, which is part of the CPU. Any DRAM PHY is almost certain to have multiple input voltages. I don't know exactly what 'CPU VDDP' is doing on AM4, but if where doing something unrelated to the vague definition commonly cited, I'd expect to see some mention of it somewhere and wouldn't be able to influence memory stability by manipulating it.


All of the above (and below) are just a guesswork based on what I currently have known.
1. Yes, the term "CPU_VDDP" suggests (but of course, not limited to) something more CPU centric.
2. AFAIK memory cirquits (dram itself) and MEM PHY IO are powered by PHY VRM (Vdimm)
3. MEM PHY core logic (UMC itself) most likely powered by SOC VRM, though not confident enough here
4. In all those rare documents where I came across the term VDDP, it was referred to as "bias or reference voltage", i.e. not for providing of actual power. For example, it was mentioned in the recent AMD patent on memory subsystem, although not called vddp (it was, in some VRM controllers datasheets I've seen):


Spoiler: US 20210200297A1



In the described embodiments, the particular regulated voltage for electrical power provided by each of the voltage regulators is set using circuit elements in that voltage regulator. The circuit elements that are used for controlling the output of each voltage regulator depend on the type of that voltage regulator—and thus the circuit elements present therein. For example, in some embodiments, a *bias or reference voltage* supplied to circuit elements of a given voltage regulator can be set to specified values to cause those circuit elements to commence providing electrical power at a respective voltages


5. The patent itself is quite interesting to read. There was a switch introduced to MEM PHY, that is dynamically select the VRM controller for powering PHY core logic (i.e. UMC, I suppose)


@Veii
There's a bunch of AMD assigned patents published, some will surely interest you if you haven't read them yet
The technologies described therein definitely will turn memory OC-ing to a nightmare (or rather make it useless) in the nearest future 
Here is the list from Underfox, if anyone is interested


Spoiler: Patents





__ https://twitter.com/i/web/status/1412502324644298756


----------



## craxton

ManniX-ITA said:


> problem I see with that solution is that if something breaks you have to trash everything
> 
> for sure more expensive but:
> 
> 
> 
> 
> 
> 
> 
> 
> Alphacool Eisbaer Pro Aurora 360 CPU AIO
> 
> 
> The Alphacool Eisbaer Pro Aurora CPU AIO water cooler is a special development for processors with particularly large CPU dies. These include the AMD Threadripper and Epyc processors and the Intel CPUs for the LGA 3647 and LGA 4189...
> 
> 
> 
> 
> www.aquatuning.us
> 
> 
> 
> 
> 
> plus:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Alphacool D-RAM Cooler X4 Universal - Acetal Black Nickel
> 
> 
> With the new D-RAM coolers all desired memory chips can be cooled. This cooling block is screwed onto the optional cooling modules or existing heatspreader with a hole spacing of 110mm (like the Corsair Dominator). Due to its black...
> 
> 
> 
> 
> www.aquatuning.us
> 
> 
> 
> 
> 
> x2:
> 
> 
> 
> 
> 
> 
> 
> 
> Alphacool D-RAM module (for Alphacool D-RAM cooler) - black 2 pieces
> 
> 
> Due to the new Alphacool D-RAM modules all memory blocks can easily and quickly be equipped with water coolers! A fight against the underrated heat source "memory" has been announced with the new system of the Alphacool D-RAM coolers ....
> 
> 
> 
> 
> www.aquatuning.us
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Alphacool Eisbaer TPV Extension Set 90° (tubes and fittings)
> 
> 
> The Alphacool Eisbaer TPV Extension Set 90° offers the easiest way to connect the expandable AIO systems from Alphacool with other components. The Extension Set is compatible with all Alphacool AIO systems for processors and graphics...
> 
> 
> 
> 
> www.aquatuning.us
> 
> 
> 
> 
> 
> should be definitely more performant and if something breaks you can replace the single parts and even slowly upgrade to a real custom loop
> the RAM block is excellent
> just the fans are not that good
> but over time you can replace them with 3 x Corsair ML120 that are awesome


for that universal aio you shared which is 100% what i would have gotten if i had seen it. instead of the EK-240-D-RGB
which performs great, but isnt modular in anyway....
thanks for both these i have some vardars at this time which work better than
any fan i have currently.
so i may stick with those if i go this route.



Veii said:


> Bykski


had never heard of such until now...quick google search shows an entire heaven for water cooling an such.. THANK YOU!!!!



ManniX-ITA said:


> for sure more expensive but:


I mean, it would 100% have been cheaper
For me to have gotten that
Aio considering I bought the ek I mentioned and the cooler master ml240L
(Ml240l is as well a great cooler especially granted it's cheap price.)

But at this moment I'm a little over an hour into TM5 with that 90mm fan I may, or may not have mentioned idk. Had this reply typed several times and


Spoiler



covid got to me as such I slept for a good while)


But, if this passes granted I'm running
43.6 proc, 6/3/4 1.54v bios (unsure reported) 40-20-24-24 still seems to be the sweet spot for whatever reason)
with that fan full tilt is as loud as my system on full tilt. So it's actually not to bad. The big fan in the background drowns it out so...dimms are cool to the touch now. Wished they had a thermo sensor built in.

It's hot inside ATM however, unless I'm just hot idk. But if this passes (and other stressings pass), I won't immediately seek a new method to cool, but I will be gathering enough for those sticks Veii mentioned, and adding those to the aio u mentioned. As I was looking at some "EK-KITS" when I had enough funding on hand it was out of stock. And ebay wanted way to much.

(Edit) ignore the bios reset wire danglin out front... Not "mounted" just rests there for testing. As the aio block in/outlets are kind of in the way I'm
Unsure if I'll be able to mount properly.
Or "half ass better" than what it is now.
!disclaimer!


Spoiler



I do not take responsibility for any triggers regarding that cable management you'll notice I gave up on. 12 RGB fans to each their own is a mofo to manage. Would place two more fans near those ssd mounting spots but the GPU is so big I had to "bend" the mounts to get the GPU in as is (normal mounted) so there's no room for more fans in that spot.



(Edit) 3 hours for 25 passes tm5? 2:43 min so far on pass 24.. no errors but dam seems slower than 16-16 3800...









Update, passed tm5, so all I needed was some airflow. 
Now for more hours of testing. And try lowering the rpm some, gotta crank the GPU open as well to get more heat in the system and rerun. But it all starts here.


----------



## 1devomer

@Veii

I'm still waiting an answer on what you posted in another thread.
Again, can you please expand your thought about this post, what does it mean?



Veii said:


> * I mention this, as many people contributed to HWInfo
> And some of the many people also have access to official AMD API , which should never belong to the public
> Martin is again not to judge for such, but not everything he uses for sensoring, is based upon his own research


----------



## craxton

1devomer said:


> @Veii
> 
> I'm still waiting an answer on what you posted in another thread.
> Again, can you please expand your thought about this post, what doest it means?


Pretty sure he means that you can't just blame martin, as he has help in other places, and sources he doesn't mention to "protect" such people from AMD hammer/slammer lawsuit type stuff. 
The way you wrote this question tho is a little "demanding" as such. Veii has more mentions than anyone on OCN I'm aware of. (Excluding the admins) chances are he didn't see it. Or seen it and thought the response was good enough. Not speaking for him persay. 
But I'd have to bet that's roughly what it means, unless I missed the part your looking for an answer to?


----------



## 1devomer

craxton said:


> Pretty sure he means that you can't just blame martin, as he has help in other places, and sources he doesn't mention to "protect" such people from AMD hammer/slammer lawsuit type stuff.


Why i would, and/or i should, blame HWInfo developers team?!
I didn't get the point at the time of the post, i still didn't get the point now, hence my question.

And i still didn't get the point about people having access to AMD API, and the fact that these should not belong to the public?

Simple curiosity.


----------



## Veii

1devomer said:


> @Veii
> 
> I'm still waiting an answer on what you posted in another thread.
> Again, can you please expand your thought about this post, what does it mean?


We talked back and forth between HWInfo Accuracy, Information Sharing and NDA type of sttuff
The person in charge quoted a quote from Martin upon his personal question. All was about readout accuracy & type of SMU readout/Injection. 1usmus also often mentions that HWInfo doesn't use a proper mapping or a "different" compared to CTR

It's a big discussion topic and somehow everyone wants to be right
I mentioned that for Martin to get accurate readouts, it needed more than just personal reverse engineering or using open source code
I mentioned briefly that not every code is open source and some is borrowed , while some is "given".
Not every code should be out in the public and not every part of it should even leave the Development Lab (no information to Board Partners or Engineers)

This is all i wanted to mention about, from the side
Yet Martin is not to judge for information he get's (which he shouldn't know) . Same as other people who got here and there pieces of information without signing NDA's ~ which also includes myself by some extend
But i don't want to put on fire trustworthy friends in the tech industry. Which also (them) got information snippets either by own research or by handed snippets of research

There is not more to speak about this topic.
What the public should rather know, is that all this secretive (personal opinion) is annoying and hinders community developed progress.
AGESA 1.2.0.3A/B is more broken than 1200 which is more broken than 1100A.
AMD keeps improving and focuses ~with success so to say~ on specific topics. But it's overwhelming how much is not "fixed".
They can not manage it alone. They need us ~ yet treat us like law breakers and traitors. At least the behaviour from the industry let's you feel such.

Matisse was strongly locked, but they went the powersaving path. Fine for me
Vermeer is very dynamic with very high limiters & possibilities. But i feel the silicon is still in active change & optimize procedure.
It's sad that important information is censored or prohibited & active issues are silenced rather than admitting that they are broken.
An NDA for a "teaching Overclocker" is strongly damaging. But that's what you have to trade for, if you want to actively develope something [A: for AMD, B: For Ryzen Prosumer]
Nothing can get out of this methodic. Either you damage your reputation, or you skip questions and behave badly ~ with such NDA's
I don't want to talk more about this topic, but the industry needs to change. I think we the community too. Not trying to be "the one person" with all the information, but share snippets to brainstorm together.
Currently it's rather a fight, who has more information and who is risking more damaging his reputation.


----------



## Blameless

PJVol said:


> 1. Yes, the term "CPU_VDDP" suggests (but of course, not limited to) something more CPU centric.


The memory PHY is wholly contained on the CPU package and the nomenclature difference between cLDO_VDDP and CPU VDDP only really imply the source of the voltage; the former being derived internally via an LDO attached to some other rail, and the later being sent directly to CPU pins from some external (probably switching) voltage regulator.



PJVol said:


> 2. AFAIK memory cirquits (dram itself) and MEM PHY IO are powered by PHY VRM (Vdimm)
> 3. MEM PHY core logic (UMC itself) most likely powered by SOC VRM, though not confident enough here


Entirely possible, though in other DDR4 PHY implementations I've read about, I tend to see voltages closer to AM4's VDDP used than to AM4's SoC voltage, though there are outliers.



PJVol said:


> In all those rare documents where I came across the term VDDP, it was referred to as "bias or reference voltage", i.e. not for providing of actual power.


This is also not implied by the terminology and it's not hard to find alternate uses for 'VDDP', if one searches for pre-Ryzen sources to filter out popular repetitions of the same vague use.

A couple of examples:


https://www.infineon.com/dgdl/APP_XMC4000_PCB_Design_Guidelines_v1_0.pdf?fileId=db3a3043427ac3e201427b9be8b11f13





https://www.microsemi.com/document-portal/doc_view/129831-ac188-in-system-programming-proasic-devices-app-note



After brushing up on how LDOs work and looking at the description for 'CPU VDDP', as vague as it is with regard to AM4, I do acknowledge that it could be suggestive of the idea that CPU VDDP is being used as a reference voltage for the error amplifier in the LDO regulator responsible for cLDO_VDDP. However, some doubts remain...namely why would a pure reference voltage need nine pins (more than twice as many as CPU 1.8v) on AM4? It's also possible that they are simply supplies for different domains within the PHY.


----------



## ManniX-ITA

PJVol said:


> All of the above (and below) are just a guesswork based on what I currently have known.


My understanding is different, based on what I've read about the original Zen architecture and what I could find about Zen 2/2, EPYC and the Infinity Fabric interposer.










The cIOD does not access the DDR4 memory, it doesn't need to and would conflict with the cores.
The UMC acts as a proxy handling the shared access from the CCDs and controlling the DDR4 PHY.

The GMI2 links does not have a protocol, they are simple SerDes; they don't "speak" any language but are just tunneling what is coming through, it's a transport layer.

So either they are passing PCIe to access the I/O connected to the Hub controller or DDR4.

This means the CCD has to "speak" the DDR4 protocol.
I rule out any conversion cause otherwise it would have a huge impact in latency and bandwidth.

In the monolithic Zen architecture that was done per CCX via the CCM.
In Zen2/3 my guess is the CCA which is in the common/L3 part serving all the cores.
The CCA should contain a full DDR4 memory controller die (logically more or less 1 and 2 in the picture), like the UMC, minus the PHY part as that's the IFOP (GMI2 SerDes).

I think the CPU VDDP is the voltage supplied to the memory controller in the CCD.


----------



## PJVol

ManniX-ITA said:


> The cIOD does not access the DDR4 memory, it doesn't need to and would conflict with the cores.
> The UMC acts as a proxy handling the shared access from the CCDs and controlling the DDR4 PHY


You may missed context of my post as it was solely DDR PHY abstract level.


ManniX-ITA said:


> I think the CPU VDDP is the voltage supplied to the memory controller in the CCD


Sorry, still don't get what "memory controller in the CCD" means.


----------



## ManniX-ITA

PJVol said:


> You may missed context of my post as it was solely DDR PHY abstract level.


I'm talking about CPU VDDP voltage.



PJVol said:


> Sorry, still don't get what "memory controller in the CCD" means.


The memory controller is the IC with the logic.
For all physical interfaces you have an IC and a PHY (DDR, HDMI, ETH, etc)


----------



## PJVol

Blameless said:


> After brushing up on how LDOs work and looking at the description for 'CPU VDDP', as vague as it is with regard to AM4


Have to agree regarding vagueness, and with @Veii too, when he called it annoying 



ManniX-ITA said:


> The memory controller is the IC with the logic.
> For all physical interfaces you have an IC and a PHY (DDR, HDMI, ETH, etc)


I mean "in the CCD" part, i.e. are you talking about UMC or something else that is in the CCD?


----------



## 1devomer

Veii said:


> We talked back and forth between HWInfo Accuracy, Information Sharing and NDA type of sttuff....
> ....Currently it's rather a fight, who has more information and who is risking more damaging his reputation.


Thank you for expanding about the matter.

At this point, i strongly regret taking a defensive stance toward the HWInfo developers and maintainers team.
Especially when people were trashing HWInfo usage, because of the WHEA occurrence, when paired with a RX6k gpu and Ryzen 5K cpu.
From what i got, HWInfo team was complaining alongside other dev team, especially on Linux, about AMD not releasing development toolkits.
So the next time, i will be more careful defending and/or supporting HWInfo development team!!!

Second point, i would generally agree with you, but.
If you and others are protecting secrets without having a NDA signed, that allow 3rd parties to make money, on top of basic consumers.
All these people are ethically reprehensible, by duping less knowledgable people, on top of hindering the community development and well-being.
Which is an annoying trend, that is growing fast when dealing with AMD products, and/or AMD development software.

Now i understand much better what you meant.
Maybe this stuff will come out one day, alongside the full EUV development story.
That said, i'm out!



Spoiler: I Was There



"I was there Gandalf, 3000 years ago, when on this same forum, we trashed Intel for the X299 VRM debacle"


----------



## Veii

mongoled said:


> I was not aware of the issue with prior blocks, know the name of the rep ?
> 
> Well, as I have a loop and considering I am using a fan to cool the 4 sticks I may as well watercool the RAM as you have said it makes them sleek


I will have to look today.
But the "sleek" part rather goes to the low footprint heatsink
Watercooling them, might even make them warmer


FleischmannTV said:


> @Veii
> 
> Why is getting RttWr=RZQ/2 to run a big benefit in your opinion?


I haven't compared it from the technical side of things if it matches my gotten out results
But _WR is triggering dynamic On-DieTermination. Adjustable by shifting "phase" left and right

The positive part of it:

it does shift misaligned reflections, which means the signal is more unlikely to reflect back and so lowers ripple and noise | research micron technology
it is capable to make up and set own borders, floor and top ~ if one of both is only provided. This helps point 1 even more
generally it's work is to figure minimum required ceiling and adjust it dynamically
Part of of this is very beneficial working together with MCLK timed powerdown 

The reason why /2 is better, to my testing 
Is because generally its stronger, but it doesnt mean more heat
I am not confident if it only changes +/- range (increases control range) or purely the strengthness similar to RTT_PARK
I only check results later with technical documents, to prevent influencing a neutral viewpoint and have so no expectation's of the outcome

So far it showed me that heat was lower, and yet helps power dimms better than lower PARK (well they are similar, just WR is more controlling than X floor (park) or Y ceiling (nom) ~ WR maintenances both)

WR /2 generally is hard to get running single rank
It took me down to /7 PARK, before i could disable it (which moves in the >1.66v range)
Only afterwards WR was even taken as /2

But each WR has their own range of NOM and PARK ceiling
/6 PARK on /3 WR is different Ampere outcome than /5 PARK /2 WR (first being higher and so worse)

I am not sure how to explain it fully. Still miss more data for its floor range. (After which voltage and when it starts to work
But generally getting it to run is better. When you "can" get it to run


----------



## Blameless

ManniX-ITA said:


> This means the CCD has to "speak" the DDR4 protocol.


Frankly, I would be flatly astounded if this were the case. There is almost no conceivable way for the CCDs to be doing this, or any reason for there to be a memory controller/PHY on the I/O-die if this what was happening.



ManniX-ITA said:


> I rule out any conversion cause otherwise it would have a huge impact in latency and bandwidth.


Simply having to reach across Fabric to another die on the same package is responsible for a lot of latency, which is why even with a very robust memory controller, fast fabric interconnect, and huge caches to mask latency, main memory latency is still in the toilet compared to good on-die memory controllers/monolithic architectures.

The location of the memory controller shouldn't make one whit of difference if the PHY is on the IOD and the memory pins connect to the IOD. Putting the controller on the CCD only to have to send it to a middleman before reaching the memory isn't going to reduce latency.

I don't believe there is a DR4 memory controller in the CCD. There is no evidence for one being there, no reason for it to be there, and plenty of evidence to the contrary.


----------



## ManniX-ITA

Blameless said:


> I don't believe there is a DR4 memory controller in the CCD.


I may be wrong but I think there is.
In one of the documents I've read there's written the cIOD does not issue DDR4 commands at all.
The UMC to my understanding is there to proxy the DDR4 commands coming from the CCDs and handle the PHY.



Blameless said:


> There is almost no conceivable way for the CCDs to be doing this, or any reason for there to be a memory controller/PHY on the I/O-die if this what was happening.


Why not? It's just on-die space. Not a PHY (it's not connected to a physical DDR4 channel), only a memory controller.
It's the core, more exactly the shared die logic, handling access to RAM; can't be otherwise.
The same die part must also handle the L2/L3 to handle the cache; hitting the cache instead of doing requests for data which is already hit in the cache.


----------



## Blameless

ManniX-ITA said:


> Why not? It's just on-die space. Not a PHY (it's not connected to a physical DDR4 channel), only a memory controller.


That's the answer right there.

Putting the memory controller on the CCD would be a redunant waste of die area on a more expensive process and would do nothing to reduce latency because memory traffic would still need to cross the Fabric to the IOD and the PHY. Having the memory controller on the CCD makes no sense if the PHY is on the IOD.

There is also no evidence of a DDR4 memory controller on the CCD die shots, but parts that could almost certainly only be DDR4 memory controllers on the IODs.



ManniX-ITA said:


> It's the core, more exactly the shared die logic, handling access to RAM; can't be otherwise.
> The same die part must also handle the L2/L3 to handle the cache; hitting the cache instead of doing requests for data which is already hit in the cache.


That's what the MMU does, but an MMU is not a memory controller, not in this sense. Nothing on the CCD/CCX needs to know anything about the main memory interface, that's what the memory controller is for. Indeed, this is one of the very intentional strengths of the chiplet topology. You don't have redunant parts and can drop CCDs onto any platform/package. It's why we can have AM4, TR4, and TRX4 that can all use the same CCDs.


----------



## ManniX-ITA

Blameless said:


> That's the answer right there.
> 
> Putting the memory controller on the CCD would be a redunant waste of die area on a more expensive process and would do nothing to reduce latency because memory traffic would still need to cross the Fabric to the IOD and the PHY. Having the memory controller on the CCD makes no sense if the PHY is on the IOD.
> 
> There is also no evidence of a DDR4 memory controller on the CCD die shots, but parts that could almost certainly only be DDR4 memory controllers on the IODs.
> 
> 
> 
> That's what the MMU does, but an MMU is not a memory controller, not in this sense. Nothing on the CCD/CCX needs to know anything about the main memory interface, that's what the memory controller is for. Indeed, this is one of the very intentional strengths of the chiplet topology. You don't have redunant parts and can drop CCDs onto any platform/package. It's why we can have AM4, TR4, and TRX4 that can all use the same CCDs.


It's not a redundant waste. You say it's transparent. Ok, then what is this "transparent"?
Because it's how data is moved through the GMI2 links. What protocol would be used for that?
Having a memory controller in the CCD makes sense cause otherwise some protocol for the payload had to be implemented, GMI2 links are purely a transport layer, and that conversion would cause a big, additional, latency and bandwidth hit.
There's already a small hit coming from the SerDes, that would be on top.

Not sure what should be the MMU... 
If you look for one of the answers from AMD about Zen3 supporting both DDR4 and DDR5 you'll see it was that it would require a re-design of core and a waste of die space.
Not a re-design of the cIOD, the core part, the CCD.
The CCDs can be re-used because they all speak DDR4.
And they'll not be re-used on AM5 cause they can't speak DDR5.

Again I may be wrong but this makes perfectly sense for me


----------



## Veii

@Blameless @ManniX-ITA , wouldn't it be generally contra productive for each mCCX to mCCX (let me call them that for now, mini CCX or CoreCapsules) ~ 4 left , cache, 4 right (well 2+2+cache+2+2)
to proxy to L1/L2 cache while at the same do such towards memcontroller and back to mCCX
There is a fixed +8ns latency, which to what i can see only changes (lowers) by FCLK increasement
(delay between send instruction set, error checked and send back before exception inside same mCCX)
And read, incl copy/duplicate lanes run on double the linkspeed as one way write

For what was dLDO per core needed, including per core c-states (i really don't want to call them "cores" but mCCX sounds wrong to you)
For what would per core error correction be needed & what is the reason for doubling copy and read bandwidth + for what reason is OpCache such a big security issue and does per-name.exe acceleration

I do think that AMD did not "only" split L1 & L2 apart from L3 ~ for monolithic cost reasons
I can not think they gave up Numa acceleration, yet link CoreCapsules (core+L1+L2) with an mCCX in post together
It makes no sense to me that CBS (split from SP3 fully as own repo/tree) keeps on utilizing virtual numa acceleration and CCX acceleration ~ when low latency is important
It makes also no sense why each core has to run through ECC towards the IO-Die, instead of staying inside
(unless it does, there is a bigger chip on the substate which has no explanation what it really does)
But then also it makes from a business perspective not much sense why they would link CoreCapsules/CorePackages in post on the substrate ~ yet leave 12 & 16 core units sometimes / instead of destroying the links

What also doesn't make much sense to me, is why all 1CCD units where not dual CCDs with hollow Capsules (what we call cores) - in order to utilize cache acceleration and gain another 30+ % in cache perf uplift (like Matisse, consumers anyways pay the 2nd CCD tax nevertheless if it's used or not)
Tho i think they probably did focus on exactly such with Zen3D.
It absolutely makes no sense why they would leave any duplication acceleration algorithms & stacking algorithms (numa and similar) ~ when it has no belonging to AM-X Consumer lineup

EDIT:


Veii said:


> What also doesn't make much sense to me, is why all 1CCD units where not dual CCDs with hollow Capsules (what we call cores) - in order to utilize cache acceleration and gain another 30+ % in cache perf uplift (like Matisse, consumers anyways pay the 2nd CCD tax nevertheless if it's used or not)


It likely was done in order to support pure AVX256. Likely there was a design reason for such (to give up such big stacking acceleration boost).
We'll see with Zen3D if AVX512 support will come and how CCD layout will look 
============================
I noticed at the very beginning something funny
Cache acceleration depends not only on the frequency of each core & not only on the avg frequency of each package left & right of the cache inside a CCD
But it does increase and decrease in speed to meet a specific throughput target (anti choke target) ~ and why overboost sometimes happened, or you actually get better cache performance from slower powerplans not faster
If a powerplan does slow down frequency spikes and link speeds overdrive/overshoot fully - FIT is not really detecting any reason to throttle. Yet it does detect a reason to throttle on spiky fast powerplans where peak cache bandwidth is reached instantly (which results in worse perf)

I don't think that any of the GMI links are fixed speed and don't think that DPM doesn't play a role
I can not see why the consumer limits are set as low as they are now ~ except that the substrate is not mature enough
Here and there i overshoot 32B/Cycle ~ while apparently connections to the 2nd CCD should be blocked
Yet it does keep accelerating from it ~ without any load or anything being offloaded there. Neither cache nor anything
Mystery after Mystery 🤭

On twitter, i had some good chat with an early Zen 1/2 technical engineer (need to find him again, i think you guys could have some questions for him)
Part of the things he was able to talk with me, about the reason why FCLK @ X frequency only results in half bandwidth - and don't bother or touch MCLK to UCLK performance
Yet there was as always a communication breaker (NDA) when i mentioned and asked about variable FCLK and APBDIS ~ why it's disabled/absent & cuts soo deep into the powerbudget because of their decision
* if you want to break an active conversation with an engineer - just ask about variable SOC and APBDIS for consumer (not mobile ryzen) ~ where it went 🤭


----------



## Blameless

ManniX-ITA said:


> Ok, then what is this "transparent"?


The CCD should work wether or not it's connected to an IOD with a DDR4 controller, an HBM controller, or a giant brick of SRAM, because the CCD/cores should not need to know or care about the main memory, excepting the physical addresses



ManniX-ITA said:


> Because it's how data is moved through the GMI2 links. What protocol would be used for that?
> Having a memory controller in the CCD makes sense cause otherwise some protocol for the payload had to be implemented, GMI2 links are purely a transport layer, and that conversion would cause a big, additional, latency and bandwidth hit.


I'd presume whatever protocol all the IF traffic uses.

There has to be some way to differentiate memory from other IF traffic, so I'm not seeing where there would be any additional overhead from having the memory controller on the IOD. The CCD to IOD Fabric cannot be 'speaking DDR4' because it carries a lot of information that is not going to the system memory.

The memory controllers, or PHY (if they were separated), should only be routed memory traffic and there would need to be a protocol to do this.



ManniX-ITA said:


> Not sure what should be the MMU...


The memory management unit is the part of the CPU core that translates virtual addresses to physical addresses.



ManniX-ITA said:


> If you look for one of the answers from AMD about Zen3 supporting both DDR4 and DDR5 you'll see it was that it would require a re-design of core and a waste of die space.
> Not a re-design of the cIOD, the core part, the CCD.
> The CCDs can be re-used because they all speak DDR4.
> And they'll not be re-used on AM5 cause they can't speak DDR5.


Do you have a reference for that?

Zen 3 is design that's used in a lot of parts, many of them monolithic. I do not believe that a Vermeer or Matisse CCD would have any trouble at all working with DDR5 (or _any_ arbitrary memory standard) if connected to an I/O-die that had DDR5 controllers and PHYs, and it would take an extremely unambiguous statement to convince me otherwise.


----------



## Veii

Blameless said:


> The CCD should work wether or not it's connected to an IOD with a DDR4 controller, an HBM controller, or a giant brick of SRAM,


Consumer Ryzen does speak DDR4, LPDDR4 and HBM
Unsure about DDR5, if it isn't "just a FW thing"


Blameless said:


> ecause the CCD/cores should not need to know or care about the main memory, excepting the physical addresses


But i am not sure what type L1 and L2 cache are and if L3 is a different type ~ soo unsure if CoreCapsule (Core) does even need to speak DDR/HBM
Yet latency is too high from the core to cache to same core, for it to not leave it's "House"
House/Capsule =








EDIT 2:
Because these links are placed/connected in post.
(focus towards mention about hollow "cache only" vessel, for 2nd CCD (inter-CCX acceleration ~ option)


----------



## ManniX-ITA

Veii said:


> Consumer Ryzen does speak DDR4, LPDDR4 and HBM
> Unsure about DDR5, if it isn't "just a FW thing"


Yes cause they are all the same more or less; HBM being a "dialect" of DDR4.



Veii said:


> But i am not sure what type L1 and L2 cache are and if L3 is a different type ~ soo unsure if CoreCapsule (Core) does even need to speak DDR/HBM


Not the Core itself, should be the common part which is handling L2 (L3 is a subsystem of L2); that part on Zen was using a discrete part called CCM (Cache Coherent Master) for communication with the UMC.
In the chiplet design it's part of the CCD common part and I think it's called CCA (Cache Coherent A..? Architecture?).



Blameless said:


> The CCD should work wether or not it's connected to an IOD with a DDR4 controller, an HBM controller, or a giant brick of SRAM, because the CCD/cores should not need to know or care about the main memory, excepting the physical addresses


Then we would see them re-used on AM5 for costs reasons but it's not going to happen according to AMD cause it would require a re-design.
That's why I think there is a memory controller inside.



Blameless said:


> I'd presume whatever protocol all the IF traffic uses.


There is no protocol. It's a transport layer, it's only encapsulating data.



Blameless said:


> There has to be some way to differentiate memory from other IF traffic, so I'm not seeing where there would be any additional overhead from having the memory controller on the IOD. The CCD to IOD Fabric cannot be 'speaking DDR4' because it carries a lot of information that is not going to the system memory.


There is a control plane for DF where all the other data is going through which is not payload.
The other payload is PCIe.



Blameless said:


> Do you have a reference for that?


Sorry I'm not maniac enough to keep an organized reference of whatever I read sadly


----------



## Veii

ManniX-ITA said:


> Then we would see them re-used on AM5 for costs reasons but it's not going to happen according to AMD cause it would require a re-design.


Old codename Warhol could have come to AM4 - it was technically possible & dual DDR4/5 accepting boards where also a possibility
But Warhol right now is another project.
The cache stacking gain , the typical fabric stacking & interleaving performance "trick" ~ lead to over +20 % , soo old Warhol was not needed to exist
I look forward to "extreme corecount" units with 8 mCCX per side & cache in the middle  (not AM4/5)
We need another thread for [Zen Technical (Speculation)] ~ now that Q4 is soon arriving
EDIT:


Spoiler: Drawing on ShareX is hard :')



Speculative Links/Connections Idea








Would be happily surprised if they can efficiently pull a pyramid schematic off for AVX512 acceleration (top row 3 bottom row 3)
But they'd need to put another batch in contract to redesign L1/L2 cache position ~ in order to mirror them like it's so far done
Idk if AMD can manage (effectively) such snowballing method ~ but i'd be happy to see a proof of concept for AVX512 acceleration on a pyramid schematic


----------



## Blameless

Veii said:


> Consumer Ryzen does speak DDR4, LPDDR4 and HBM
> Unsure about DDR5, if it isn't "just a FW thing"


While interesting, that just says that they have controllers and PHYs capable of attaching to any of those memory standards, not where the controller is.



Veii said:


> But i am not sure what type L1 and L2 cache are and if L3 is a different type ~ soo unsure if CoreCapsule (Core) does even need to speak DDR/HBM
> Yet latency is too high from the core to cache to same core, for it to not leave it's "House"
> House/Capsule =


The L1 and L2 are inclusive and the L3 is an exclusive/victim cache.

Regardless, I'd _expect_ the MMU to kick anything with a physical address that didn't fall within local cache out over the Fabric, to be routed to the memory controller on the IOD...not for the cores or CCD to have direct access to the memory PHYs.



ManniX-ITA said:


> Then we would see them re-used on AM5 for costs reasons but it's not going to happen according to AMD cause it would require a re-design.


Even assuming zero compatibility issues I doubt they'd use last gen CCDs on a new IOD and package, nor am I convinced it would be economical to do so, unless there was a serious shortage of new CCDs.

There are also numerous possible compatibility issues that would not imply a memory controller on the CCD. Changes to the physical Fabric layer, electrical considerations, or simply a desire to streamline validation by not having to test new gen IODs with last gen CCDs or vice versa.



ManniX-ITA said:


> There is no protocol. It's a transport layer, it's only encapsulating data.


I can think of plenty of transport layer protocols. How do you encapsulate/decapsulate data without a protocol?

Regardless, I'm still not seeing how or or where you think having the memory controller on the IOD would add any latency. Either a memory controller on a CCD converts it to something the PHY can send directly to the to the memory, or a memory controller on the IOD converts it to something the PHY can send to the memory. Either way the distance is the same and same steps need to be performed.

You're essentially arguing that it takes less time to put a LEGO castle on your coffee table if you assemble the castle on your kitchen counter and then carry it to the coffee table than if you take the parts to the coffee table and assemble it there.


----------



## ManniX-ITA

Blameless said:


> I can think of plenty of transport layer protocols. How do you encapsulate/decapsulate data without a protocol?


I meant that it's transparent; the data itself is packaged in SDF requests and then encoded/decoded serially via the CAKE.
Those SDF requests I suppose are HyperTransport protocol, which is sort of a subset/extension of PCI.

You can read a lot about it in this article about Zen:









ISSCC 2018: AMD's Zeppelin; Multi-chip routing and packaging


A look at AMD's Zeppelin SoC and the Infinity Fabric, a multi-chip architecture used by AMD to scale their SoC design from the mainstream PC market all the way to the server market.




fuse.wikichip.org





The point which lead me to think there is a memory controller in the CCD is that the UMC in the cIOD does not issue DDR commands.
Can't find the reference but it was pretty reliable.
Could be either the UMC is directly connected via HT but then it would conflict with the statement above.
And it would mean the CCD would not need a re-design to support DDR5 which is what AMD said, unless I've misinterpreted their statements.

It's a pity there's not enough material shared as for Zen. 



Blameless said:


> Regardless, I'm still not seeing how or or where you think having the memory controller on the IOD would add any latency. Either a memory controller on a CCD converts it to something the PHY can send directly to the to the memory, or a memory controller on the IOD converts it to something the PHY can send to the memory. Either way the distance is the same and same steps need to be performed.


There is a memory controller in the IOD, it's the UMC and it drives the PHY.
What I mean is that if the memory commands form the CCD are encoded in something that then needs to be decoded at the UMC level it has a performance cost.
If the DDR commands are issued in the CCD and only proxied via the UMC is more efficient.


----------



## Robostyle

Daym guys, You talk about correcting CCD engineering, juicing another %% of performance, and blaming amd going intel with NDAs and such, and here I am, passed along for a piece of advice about voltages, LOL. Could You please give me directions to lamer section? Thank You


----------



## Nighthog

@Veii 

Got any suggestion on what to do with error 0 for TM5? [Voltage cutoff choke]

One of the Ballistix MAX 4400CL19 kits is misbehaving and not finding a proper solution.

Error 2 & 14 come up now and then, with some error 4. But mostly Error 0. Other times it was limited to error 5 only.
Tried various things but in length it's just not behaving as well as the other kit did.

Can't figure out what I should be focusing on to get it to work. 
This kit also doesn't like voltage more than ~1.610V. The other kit could do with around 1.64V maximum but the lower voltage limit might be causing issues.


----------



## ManniX-ITA

Robostyle said:


> Daym guys, You talk about correcting CCD engineering, juicing another %% of performance, and blaming amd going intel with NDAs and such, and here I am, passed along for a piece of advice about voltages, LOL. Could You please give me directions to lamer section?


Sorry, not knowing exactly what is CPU_VDDP still bothers me 



Robostyle said:


> Already mentioned before, I have a feeling it's all about balancing between vDIMM, vSOC, and VDDP - but maybe I'm losing something - so, again - what is required to make zen 3 stable at 1900-2000 fclk?


You shouldn't get WHEA at FCLK 1900, in theory.
Did you try to lower CCD? You can get WHEA if it's too high, maybe 1050 is too much.
I'd try with higher VSOC anyway, up to 1.18V.

For FCLK 2000 hardly you can make it stable considering you already have issues at 1900.
You probably need VSOC above 1.2V and IOD around 1100, considering how's going now.


----------



## Blameless

ManniX-ITA said:


> What I mean is that if the memory commands form the CCD are encoded in something that then needs to be decoded at the UMC level it has a performance cost.


I can't imagine whatever transport protocol being used has meaningful overhead, or if it's as easy to segregate data as it would need to be to send raw DRAM commands over IF, any at all. Why do we need a second memory controller driving the PHYs if the data coming from the CCDs is ready to go? Such transcoding is the whole point of a memory controller.



ManniX-ITA said:


> If the DDR commands are issued in the CCD and only proxied via the UMC is more efficient.


The elephant in the room in this scenario is how such commands can be scheduled/buffered/issued at the CCX/CCD level without having to engage in costly inter-CCX/CCD consultation. What happens when two or more CCXs/CCDs are all trying to access main memory? A pure FIFO setup would seem profoundly inefficient, given all the timing constraints involved in opening, accessing, and closing memory pages.

Page 21 here (also see page 35 in this) seems to show everything related to main memory mapping being on the IOD/through Fabric, which makes sense because only there can it be in a position rapidly respond to requests from any CCX. I imagine having to update the memory map at a CCX level for every physical memory access would have more latency, not less.



ManniX-ITA said:


> Sorry, not knowing exactly what is CPU_VDDP still bothers me


Same here.


----------



## ManniX-ITA

Blameless said:


> I can't imagine whatever transport protocol being used has meaningful overhead, or if it's as easy to segregate data as it would need to be to send raw DRAM commands over IF, any at all. Why do we need a second memory controller driving the PHYs if the data coming from the CCDs is ready to go? Such transcoding is the whole point of a memory controller.


My guess is because there must be a proxying between the two sources



Blameless said:


> The elephant in the room in this scenario is how such commands can be scheduled/buffered/issued at the CCX/CCD level without having to engage in costly inter-CCX/CCD consultation. What happens when two or more CCXs/CCDs are all trying to access main memory? A pure FIFO setup would seem profoundly inefficient, given all the timing constraints involved in opening, accessing, and closing memory pages.


There's for sure, the CPUs with more than 1 CCD are NUMA aware with 2 domains.
Maybe they use the SCF channel as control plane.



Blameless said:


> Page 21 here (also see page 35 in this) seems to show everything related to main memory mapping being on the IOD/through Fabric, which makes sense because only there can it be in a position rapidly respond to requests from any CCX. I imagine having to update the memory map at a CCX level for every physical memory access would have more latency, not less.


Very interesting this GPUOpen optimization document, thanks 👍 
So in Matisse at least there's still the CCM, one for every CCX.
First time I see this Coherent Slave unit.
Guess it's all about how they communicate with each other, which looks not much likely DDR4 as I thought.
They also transfer data from one CCX to another.
Looks more like the CS is controlling the DDR4 memory controller.


----------



## Robostyle

ManniX-ITA said:


> Sorry, not knowing exactly what is CPU_VDDP still bothers me
> 
> You shouldn't get WHEA at FCLK 1900, in theory.
> Did you try to lower CCD? You can get WHEA if it's too high, maybe 1050 is too much.
> I'd try with higher VSOC anyway, up to 1.18V.
> 
> For FCLK 2000 hardly you can make it stable considering you already have issues at 1900.
> You probably need VSOC above 1.2V and IOD around 1100, considering how's going now.


The same)

I will try low vCCD and high vIOD. Maybe VDDPs  also what keeps me this low. It's hard for novice to set it right actually when it's not simple "more volts - more OC", but picking out the right voltages, I clearly understand I might get errors with 1900-2000fclk by simply pushing too much (too low?) on vddp and vddg.
Or even worse - missing 5mV "window of stability", lol
And I'm really sceptical right now about 2000fclk, already tinkered with SOC. No matter what voltages I set, I get hundreds of whea right after boot. Pushing vSOC up to 1.25V and vIOD to 1.15V somewhat closes me to the right spot, that way I see less and less bandwidth penalty - but at 1.3V system starts to tell me voltages are waaay excessive.

I wonder if it could get better with new firmwares, or that's completely on silicon? I've seen before people saying agesas are a mess - is it this level of bad, so you can count on new OC headroom even with an old gear?


----------



## ManniX-ITA

Robostyle said:


> Pushing vSOC up to 1.25V and vIOD to 1.15V somewhat closes me to the right spot, that way I see less and less bandwidth penalty - but at 1.3V system starts to tell me voltages are waaay excessive.


IOD at 1150mV is borderline to too high for 24/7 usage.
I need it at 1140mV to get better performances than FCLK 1900.
VSOC at 1.25V is where it starts eating too much in the power budget and costing CPU performances.
If you can keep it at 1.23V or below is the sweet spot.
At 1.3V my CPU crashes brutally 

The only option I've found that is limiting the performance penalty when the DF is really stressed is CLKREQ#.
But it's only available in the AMD PBS menu which is almost always hidden.
You need a special BIOS for that.


----------



## Robostyle

ManniX-ITA said:


> I need it at 1140mV to get better performances than FCLK 1900.
> At 1.3V my CPU crashes brutally
> 
> The only option I've found that is limiting the performance penalty when the DF is really stressed is CLKREQ#.
> But it's only available in the AMD PBS menu which is almost always hidden.
> You need a special BIOS for that.


Totally the same. 
BTW, I have CBS and PBS visible, C8DH 3601


----------



## ManniX-ITA

Robostyle said:


> BTW, I have CBS and PBS visible, C8DH 3601


Wonderful, then try with CLKREQ# enabled if the option is there with FCLK above 1900. It should help.


----------



## Robostyle

ManniX-ITA said:


> Wonderful, then try with CLKREQ# enabled if the option is there with FCLK above 1900. It should help.


Welp, no luck finding that one - PBS has only one option, “Data link feature exchangen/off”. Thought maybe it was sorted to cbs, again, havent found it yet.
LCLK - what is it?


----------



## Veii

Robostyle said:


> Welp, no luck finding that one - PBS has only one option, “Data link feature exchangen/off”. Thought maybe it was sorted to cbs, again, havent found it yet.
> LCLK - what is it?


LCLK belongs to DPM link speed management
One of many dynamic "links" - another one is dLDO

You can unlock it with RU Tool, override it
As mentioned once here , and probably once in this thread here ~ else the menu options likely are "just missing or hidden" inside AMITSE (EFI module)
AMD_PBS is an own readable UEFI-Var "category" . You wouldn't have to compare HEX
but you still would need to export it from your bios, decrypt it with IFR Extrator the exported PE32 header (UEFI tool) and check which QuestionID matches the option you are looking for

Example of a bin export, this here is AMD CBS








Same goes for CLKREQ#
Changes are instant (soo make F12 screenshots before you change "random" hex pointers), but i haven't seen anything from it's change yet
F5 to run the menu and select UEFI (variables). CTRL+W to override save, CTRL+ALT+DEL to exit and reboot (EFI USB). CTRL+PageUp/Down to scroll HEX, PageUp/Down to change pages/navigation


----------



## Veii

Nighthog said:


> @Veii
> 
> Got any suggestion on what to do with error 0 for TM5? [Voltage cutoff choke]
> 
> One of the Ballistix MAX 4400CL19 kits is misbehaving and not finding a proper solution.
> 
> Error 2 & 14 come up now and then, with some error 4. But mostly Error 0. Other times it was limited to error 5 only.
> Tried various things but in length it's just not behaving as well as the other kit did.
> 
> Can't figure out what I should be focusing on to get it to work.
> This kit also doesn't like voltage more than ~1.610V. The other kit could do with around 1.64V maximum but the lower voltage limit might be causing issues.


Can you please send me a ZT screenshot and try couple of things. Collecting more error data








Slowing down tRRD & tWTR allows for less voltage to work (most of the times)
But it's generally slower - really depends on what it comes with. Probably just indicates "lack of current"
However this "current" arrives, be it via higher VDIMM or stronger RTT_PARK
But 0 up to the time it arrives, can be overcurrent PCB crash too. Really really depends

Feels like only i am playing with custom RTTs, at least to the extend of trying new things out
Probably that's my advice. Change your powering methodic 
Will check it tomorrow then with you, but it needs more data


----------



## Nighthog

Veii said:


> Can you please send me a ZT screenshot and try couple of things. Collecting more error data
> View attachment 2517305
> 
> Slowing down tRRD & tWTR allows for less voltage to work (most of the times)
> But it's generally slower - really depends on what it comes with. Probably just indicates "lack of current"
> However this "current" arrives, be it via higher VDIMM or stronger RTT_PARK
> But 0 up to the time it arrives, can be overcurrent PCB crash too. Really really depends
> 
> Feels like only i am playing with custom RTTs, at least to the extend of trying new things out
> Probably that's my advice. Change your powering methodic
> Will check it tomorrow then with you, but it needs more data


This should be more than enough, just was lacking some information, this added some things I was not aware of with regard to the error behaviours.
I've not shared a ZenTimings because I constantly am changing settings trying to figure out what might be the cause or solve it, so nothing is a real "base" to work from. Been also exploring new combinations or variables I've not tested before discussed here as of late if they would work but had not much luck.

As a clue one of the kits did tWTRS 2, with tWTRL 5 @ 5000Mts from what I could tell before I changed kits. Was just doing a direct swap to see if the other kit was as good or better. Trouble was noted that it was spewing these errors now. Had to loosen them up a bit. (but not before wasting a day or two trying 5100-5200Mts)
First there was a lower voltage threshold and then I've now been trying to relax timings in various combos to figure out what is the issue exactly, seems to have been several factors. It's just not as good as the other pair even though it's so much easier to deal with accepting settings to POST.
procODT, RZQ settings have had no effect to solve it at all, more made it worse then what I was using from the start.

I noted a RttPark correlation to ProcODT.
The lower, weaker RttPark the higher your ProcODT requirement or range goes.
*RZQ/5* RttPark likes best 34.3 ProcODT but boots upward to 40Ohm ProcODT.
*RZQ/6* RttPark... works in the 34.3 to 53.3Ohm range. But not really liking 34.3Ohm, being too low.
Could not figure out exact ProcODT it liked in the end as seemed it was OK with anything but 34.3Ohm.
*RZQ/7*, I could not run at all.
but I managed to get have RttPark set to *disabled* if I lowered my frequency to 4800Mts.
[disabled, RZQ/2, disabled] ~highly unstable @ 4800Mts. [disabled, RZQ/3, disabled] was just blue-screen heaven.

RttWr I've been trying RZQ/2 & RZQ/3 but nothing is better than just going with disabled thus far.
RttNom I can use anything I like, seems to not play a part at all but the higher the better, unless disabled.

*[RZQ/1, disabled, RZQ/5]* <--Seems like a good choice? [ProcODT 34.3]
I also noted these kits like high running DDRVDDP [2.5V] set to in the 2.700V-2.800V range for less errors overall if going for something unstable and just want to have it more stable to avoid blue-screens with unorthodox settings..

EDIT:
Gonna be trying [RZQ/1, disabled, RZQ/6] a little more with some looser timings to see if it likes it better or not. (though it has training, post issues)


----------



## Sphex_

Well, I've given up on 1900+ MHz FCLK, the WHEAs are inescapable. So instead I've turned my attention towards trying to gain performance (mainly latency) by lowering my timings at MCLK 3800 MHz. But this is proving to be challenging...

*Memory Kit:* F4-4266C19-8GTZ (2x8GB Samsung B-Die, Single Rank)
*Motherboard:* MSI B550 Gaming Carbon Wifi
*BIOS / AGESA:* 1.72 (1.2.0.3b SMU 56.53.0)
*Goal:* Lower latency / better performance through lower timings at 3800 MHz Memory Clock
*Current Stable Settings:*








*Issue: *I'm attempting to use the above settings, but tighten the primary timings and the subtimings that rely off of those (like tCWL, tRP, tRTP, tWR, etc.) The main difference here is that I'm setting the VDIMM to 1.5V as opposed to 1.4V. This is the highest voltage I'm willing to set, and at this voltage, the DIMMs don't seem to exceed 43°C in my case, which is good but not great.

Right off the bat, my computer won't even POST if I set tCL to 15 (1T, GDM off). It just does not like that value, I do not know if this is a BIOS issue or not. However, it *does* POST with tCL set to 14. Unfortunately no combination of lower primary timings (and the subtimings that rely off of those, as explained many times by Veii) seems to work. 14-14-14-14 and 14-15-15-15 do not pass memory tests (Tests 2,6,10,12 1usmus_v3 preset). The computer will POST, Windows will boot, but errors will be thrown within the first minute or so when running TM5. I've tried loosening tRFC from RC*6 to RC*8, I've tried loosening RCDRD slightly, I've tried raising the vSOC, different ProcODT, different resistances, all to no avail.

It's kind of wild this kit cannot do tighter timings than 3800 CL16 but I'm grasping at straws at this point. Any help or pointers would be appreciated!


----------



## Ethelneth

garf333 said:


> Hello friends.
> 
> I'd like to ask as to what the consensus baseline we can expect with Micron Rev. B 16GB dies.
> 
> I have a set of Crucial Ballistix 3600 32GB (16GBx2), which are single rank Micron Rev. Bs
> 
> I've done a little bit of memory overclocking with Zen2 (3200 AFRs to 3600, 16-19-19-40 with tightened secondary timings, which is probably the first time I've hit the silicon lottery) but there doesn't seem to be much online 'documentation' of what the newer Rev B 16GBs can do apart from anecdotal evidence that these have the potential to overclock 'well'.
> 
> Would anyone have any good idea of what I should realistically be aiming for, and which secondary timings to pay attention to?
> 
> I usually just do:
> Primary timings, TFAW, TRAS, the two SCLs and TRFC, and try for 1T without Gear Down.
> 
> Currently am testing this with a 5900X and an X570 Hero.
> 
> Thank you! :]


Currently running 16GBx4 of 16Gb Micron rev B ICs (thaiphoon reports them as C9BLH ICs).
3600 CL16 flat at stock voltage (1,356V measured):









3800 tRCDRD 17 downvolted (couldn't get tRCDRD 16 stable at any voltage):









Note that these can get a bit too hot without direct ventilation. I had dimm1,2 approaching 70°C even if downvolted while running TM5.


----------



## byDenoso

Sphex_ said:


> Well, I've given up on 1900+ MHz FCLK, the WHEAs are inescapable. So instead I've turned my attention towards trying to gain performance (mainly latency) by lowering my timings at MCLK 3800 MHz. But this is proving to be challenging...
> 
> *Memory Kit:* F4-4266C19-8GTZ (2x8GB Samsung B-Die, Single Rank)
> *Motherboard:* MSI B550 Gaming Carbon Wifi
> *BIOS / AGESA:* 1.72 (1.2.0.3b SMU 56.53.0)
> *Goal:* Lower latency / better performance through lower timings at 3800 MHz Memory Clock
> *Current Stable Settings:*
> View attachment 2517321
> 
> *Issue: *I'm attempting to use the above settings, but tighten the primary timings and the subtimings that rely off of those (like tCWL, tRP, tRTP, tWR, etc.) The main difference here is that I'm setting the VDIMM to 1.5V as opposed to 1.4V. This is the highest voltage I'm willing to set, and at this voltage, the DIMMs don't seem to exceed 43°C in my case, which is good but not great.
> 
> Right off the bat, my computer won't even POST if I set tCL to 15 (1T, GDM off). It just does not like that value, I do not know if this is a BIOS issue or not. However, it *does* POST with tCL set to 14. Unfortunately no combination of lower primary timings (and the subtimings that rely off of those, as explained many times by Veii) seems to work. 14-14-14-14 and 14-15-15-15 do not pass memory tests (Tests 2,6,10,12 1usmus_v3 preset). The computer will POST, Windows will boot, but errors will be thrown within the first minute or so when running TM5. I've tried loosening tRFC from RC*6 to RC*8, I've tried loosening RCDRD slightly, I've tried raising the vSOC, different ProcODT, different resistances, all to no avail.
> 
> It's kind of wild this kit cannot do tighter timings than 3800 CL16 but I'm grasping at straws at this point. Any help or pointers would be appreciated!


In order to get tCL 15, try lower tCWL to 14 and increase tRDWR by 2 and tWRRD in "auto", is also good reduce tWR to 10/12 first to see if it POST


----------



## byDenoso

My new Stable settings (i accidentally clicked in "OK" when TM5 was over)
I've noticed than my CPU works better with VDDG CCD = VDDG IOD (Anything lower then 1085mv on IOD causes reboots / WHEA)


----------



## Veii

Nighthog said:


> This should be more than enough, just was lacking some information, this added some things I was not aware of with regard to the error behaviours.
> I've not shared a ZenTimings because I constantly am changing settings trying to figure out what might be the cause or solve it, so nothing is a real "base" to work from. Been also exploring new combinations or variables I've not tested before discussed here as of late if they would work but had not much luck.


Ah that is fine, share everything whenever you need help ~ it's a good idea source with many different people's tries. I share funky stuff too sometimes
mmm, keep a look at tRFC mini  I sttill have big plans for the Error Sheets, but not really the mindset to sit and finish it
(purposely destabilize my memory to collect more data)
But also don't really want to bother chitos on the big community sheet (even with write permissions) ~ soo i edit it on mine for now

Errors,
I have 3 feelings
Main one is that low tRP probably causing charge cut issues & not really VDIMM being an issue for the zero's

The errors report:
















#14 usually comes together with a zero & often a PCB crash.
Here i feel like you don't have PCB crashes (soo it shouldn't be a VDIMM scaling issue) but rather a "lack of power"
#0 mostly is a voltage issue, and #5 & #0 either report an issue with voltage cut (lack of voltage choke) or a timing overlap (tRDWR, tWRRD ~ but can be the same for tRRD, tWTR both badly matched)

Soo what i really think it is, considering #14 & #5 appear which are 0mb copy/mirror moves (one to one duplications)
is simply a powerdown choke

Out of nowhere, tCKE & tRP look wrong
tRP might pass, when it doesn't error on big datasizes
But bank to bank and dimm to dimm duplication makes issues
Soo something in the middle chokes.

You can try to resolve it with more CAD_BUS, or try to redo tCKE
I think tCKE is wrong for this.
My math would say tCKE 21
Problem ~ tCKE beyond half cutting point reverses the behaviour . it think the max tCKE was 32 and the half cutting is 16
It goes (small) 2 to 15 (max), and 32 (small) to 16 (max) ~ and 1 for "always on"
soo the middle is reversed
* correct me on the range, i forgot what min and max tCKE was (number)

EDIT:
= idk what to use. Because two tCKE's always work for MCLK, 1900 was 9 & 16 for example
4133 (2066 MCLK should be 14, but i remember 6 run too ~ soo probably 7is 2100, 8 is 2200, 11 = 2500)


Veii said:


> I think tCKE is wrong for this.
> 
> 
> 
> My math would say tCKE 21
> Problem ~ tCKE beyond half cutting point reverses the behaviour
> 
> 
> 
> 4133 (2066 MCLK should be 14, but i remember 6 run too ~ soo probably 7is 2100, 8 is 2200, 11 = 2500)
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

~ hmm it might actually be correct. lol

RTT_NOM i wouldn't run too high personally. It covers the ceiling , but sinus curve needs to ricochet back down
Soo as low as possible, yet bit higher soo it won't reflect back
I can see it would show issues with tCKE and generally RTT_WR , once NOM is "lower" , near the /6 range
/5 - /6 is fine, /7 only bellow 1.54v
I've seen it only misbehave by different "used" VDIMM

Keep the RTT_WR /2 , it's good to have it
But adjust PARK and NOM range

PARK you'll probably figure out quite fast, as it has an association with procODT and ClkDrvStr.
You should notice once procODT is too low, or low procODT misses ClkDrvStr ~ well generally once dimms are "underpowered".
Keep in mind RTT_WR /3 and /2 , fully have different behaviour ranges. Both change lower and upper limits of NOM+PARK
I did get PARK to drop fully with WR /2 , this works - but it made me issues generally long term stability issues and timing issues with tCKE + SETUP timings

Generally tCKE and RTT_WR are both hard to time, but doable
SETUP + WR are worse to time, because SETUP Timings are fixed cuts, and WR does shift this "fixed cut" left and right to align it up to need


Nighthog said:


> *[RZQ/1, disabled, RZQ/5]* <--Seems like a good choice? [ProcODT 34.3]


Give something weaker a shot
NOM /5 , WR /2, PARK /6
Park can be /7 too, depends if you need to increase ClkDrvStr or not. Can remain on /5 if you don't get PCB Crashes #4 with it (to preserve your 20-20-20-20 CAD_BUS)
Get the zero's away, for mirror move errors we can take care later too (this likely is either tRP, tRRD_/tWTR , tRDWR or tCKE) ~ something past "one operation" and rather a "transition timing". Or just purely tCKE timing on this MCLK


Veii said:


> idk what to use. Because two tCKE's always work for MCLK, 1900 was 9 & 16 for example


We should make a MCLK list for tCKE @Nighthog . Like the one for SETUP Timings.








3 should always run each MCLK. Then it's +1 every 100mhz steps.


Veii said:


> Then it's +1 every 100mhz steps.


Personally i think this methodic is slightly wrong. It should be +1 every 3 steps not 2, but it falls into the range.
(especially because 1800 MCLK is tCKE 7 to my math, but tCKE 6 to AMD's bios math ~ both are correct)
Need to get this tested & written out (3 step scaling for tCKE). Soo much ideas are on backtrack


----------



## Audioboxer

This is where I've got to with my b-die, 12 cycles stable in MemTest5 with anta777 extreme










1.42v. I couldn't get tWTRL fully stable at 8. The SCLs were causing me a lot of bother as well, so I just left them at 4.

CL14 boots but I can't get it stable at 1.55v. Did try going a bit higher with active cooling, but still struggling to get it stable at 3800. Might be do-able, but going to need high voltage and goodness knows how much work on secondary timings.

Think I might leave it here unless anyone has any other suggestions to squeezing a bit more out at CL16? I tried 1.4v but it error'd out. I've already came down from 1.45v to 1.42v.

I've had GDM off and booting at Cl15, but it seems a nightmare to get stable.


----------



## Veii

Audioboxer said:


> I've had GDM off and booting at Cl15, but it seems a nightmare to get stable.


Everything is a nightmare when you title it such 
GDM off 2T, only shows that your set was badly powered. It doesn't need any voltage change to run
RZQ/1 is high , but ignore them for now

Try to replicate these timings








Doublecheck in the ASUS bios if tCCD_L is 6 for you
If it's 7 then change tFAW to 42

This has to run for you @ 2T
Ignore the right side 

You should run TM5 1usmus_v3 config , soo you actually have some idea what the errors mean
tRFC Calculator (mini) TM5 Error Description - Sheet

Key issues i see on your set, 
tRP is low ?
tRAS comes from where ? 
It's either tRCD *2 or tRCD+tRTP
tRC has to be tRAS + tRP

And the rest like tWR is without reason too low for you 
tCWL is low, soo likely you have boot issues when you go -1 tCL = 15, because tRDWR missmatches and tCWL is too low

Make a before and after Aida64 readout, to have an idea if you improve anywhere at all or all is lost work for nothing. 0.3ns improvement is feelable
but 0.3ns variance between 4-5 tests = instability . 0.1 to 0.2ns is test by test variance


----------



## mongoled

Veii said:


> Try to replicate these timings


And not the frequency


----------



## Audioboxer

Veii said:


> Everything is a nightmare when you title it such
> GDM off 2T, only shows that your set was badly powered. It doesn't need any voltage change to run
> RZQ/1 is high , but ignore them for now
> 
> Try to replicate these timings
> 
> 
> 
> 
> 
> 
> 
> 
> Doublecheck in the ASUS bios if tCCD_L is 6 for you
> If it's 7 then change tFAW to 42
> 
> This has to run for you @ 2T
> Ignore the right side
> 
> You should run TM5 1usmus_v3 config , soo you actually have some idea what the errors mean
> tRFC Calculator (mini) TM5 Error Description - Sheet
> 
> Key issues i see on your set,
> tRP is low ?
> tRAS comes from where ?
> It's either tRCD *2 or tRCD+tRTP
> tRC has to be tRAS + tRP
> 
> And the rest like tWR is without reason too low for you
> tCWL is low, soo likely you have boot issues when you go -1 tCL = 15, because tRDWR missmatches and tCWL is too low
> 
> Make a before and after Aida64 readout, to have an idea if you improve anywhere at all or all is lost work for nothing. 0.3ns improvement is feelable
> but 0.3ns variance between 4-5 tests = instability . 0.1 to 0.2ns is test by test variance


Thanks for the reply! The settings above aren't what I ran GDM off and CL15 on lol, I maybe should have been clearer. GDM off and CL15 was something I briefly tried when just starting out tweaking this RAM. I didn't put a lot of effort into it and got scared off easily.

The above is based solely on trying to get as tight as possible on CL16 on 1.5v or below. My results above were at 1.42v and mostly from following integralfx/MemTestHelper and some advice from someone I know who did a lot with SR b-die. I'm on DR though so have been stabbing in the dark a little learning along the way.

A lot of that guide was like "On AMD, drop tRCD by 1 until unstable. Repeat with tRP." so that is what I was doing. I've spent a few weeks and lots of MemTest5 running overnight to just keep dropping timings one by one lol.

I'm currently stability checking these timings










Because they dropped my latency down to 57.x in AIDA64 where as the timings in my post above were 59.x. But this is at a bump to 1.5v at the moment to see if it will pass 9~12 cycles. 2 hours in so far.

Still, I'm happy to take feedback on timings for CL16 and will take a look at where I may be going wrong. I know just because it passes 9~12 hours of a stability test overnight it doesn't mean it's "good timings" 

If I give GDM off and CL15 a go I will start afresh with timings and will give yours a go!

*Edit* - I have clocked what you said about tRAS and as an effect tRC. I re-read the master guide and noticed I've made a few mistakes!


----------



## Veii

Audioboxer said:


> Still, I'm happy to take feedback on timings for CL16 and will take a look at where I may be going wrong.


Run flat timings sets 
Best advice i can give you

16-16-16-16
or work away 15-15-15-15

the advices to drop something till it doesn't work, are for later ~ later when you have a good baseline
I feel you try without having a baseline
Get a baseline for your frequency , a flat timings baseline
Then adjust primaries lower and keep tertiaries high

TM5 1usmus_v3 (20 cycles)


https://www.overclock.net/attachments/tm5-zip.341454/










This will run at only 1.4vDIMM


----------



## Audioboxer

Veii said:


> Run flat timings sets
> Best advice i can give you
> 
> 16-16-16-16
> or work away 15-15-15-15
> 
> the advices to drop something till it doesn't work, are for later ~ later when you have a good baseline
> I feel you try without having a baseline
> Get a baseline for your frequency , a flat timings baseline
> Then adjust primaries lower and keep tertiaries high
> 
> TM5 1usmus_v3 (20 cycles)
> 
> 
> https://www.overclock.net/attachments/tm5-zip.341454/
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This will run at only 1.4vDIMM


I was running 16-16-16-16 to start with, only dropped primaries when secondary timings were guaranteed stable.










This has been running stable for 2 hours now and counting. I changed tRAS to tRCDRD + tRTP.

tRC wouldn't work at 34, so I increased it to 38.

At this point I'm not bothering with CL15, just trying to get the most out of CL16 and have that profile saved. Will work on CL15 at some point in the future if I fancy giving it a go


----------



## Sphex_

byDenoso said:


> In order to get tCL 15, try lower tCWL to 14 and increase tRDWR by 2 and tWRRD in "auto", is also good reduce tWR to 10/12 first to see if it POST


Tried it. No dice, unfortunately. Very strange. There's got to be a key to this.


----------



## ManniX-ITA

Veii said:


> This will run at only 1.4vDIMM


And should give you around 54.x in AIDA latency 

@Veii
about tCWL
something I forgot to ask you since longtime

Is it really better to keep it lower than tCL?
it is worth trying to get it as low as possible or counter productive?










Cause from what I see in the specs it's convenient for Read to Write to keep it same as tCL (eg 16 - 16 = 0) but it'll cost more for Read after Write (16).
While tCWL lower is adding latency to Read to Write (eg 16 - 14 = 2) but should improve Read after Write (14).

Didn't notice big improvements going -2 but I wonder if it's worth to investigate it.


----------



## Robostyle

ManniX-ITA said:


> You shouldn't get WHEA at FCLK 1900, in theory.
> Did you try to lower CCD? You can get WHEA if it's too high, maybe 1050 is too much.
> I'd try with higher VSOC anyway, up to 1.18V.
> 
> For FCLK 2000 hardly you can make it stable considering you already have issues at 1900.
> You probably need VSOC above 1.2V and IOD around 1100, considering how's going now.


Went back to 3302 (agesa 1.2.0.0?), couldn't flash earlier BIOSes, it says "unrecognized" so there's no way back to 1.1.x.x
And now I have stable IF and ram OC, but CO totally screwed up.

I guess my fantasies about stable 2000fclk OC are coming back from the old 2xxx C8DH BIOS, with the previous 1.1. agesa. 
Or maybe it wasn't even stable, but at least it didn't make tons of whea, which made me think that 3866:1933 and 4000:2000 were doable.


----------



## Nighthog

Veii said:


> Ah that is fine, share everything whenever you need help ~ it's a good idea source with many different people's tries. I share funky stuff too sometimes
> mmm, keep a look at tRFC mini  I sttill have big plans for the Error Sheets, but not really the mindset to sit and finish it
> (purposely destabilize my memory to collect more data)
> But also don't really want to bother chitos on the big community sheet (even with write permissions) ~ soo i edit it on mine for now
> 
> Errors,
> I have 3 feelings
> Main one is that low tRP probably causing charge cut issues & not really VDIMM being an issue for the zero's
> 
> The errors report:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> #14 usually comes together with a zero & often a PCB crash.
> Here i feel like you don't have PCB crashes (soo it shouldn't be a VDIMM scaling issue) but rather a "lack of power"
> #0 mostly is a voltage issue, and #5 & #0 either report an issue with voltage cut (lack of voltage choke) or a timing overlap (tRDWR, tWRRD ~ but can be the same for tRRD, tWTR both badly matched)
> 
> Soo what i really think it is, considering #14 & #5 appear which are 0mb copy/mirror moves (one to one duplications)
> is simply a powerdown choke
> 
> Out of nowhere, tCKE & tRP look wrong
> tRP might pass, when it doesn't error on big datasizes
> But bank to bank and dimm to dimm duplication makes issues
> Soo something in the middle chokes.
> 
> You can try to resolve it with more CAD_BUS, or try to redo tCKE
> I think tCKE is wrong for this.
> My math would say tCKE 21
> Problem ~ tCKE beyond half cutting point reverses the behaviour . it think the max tCKE was 32 and the half cutting is 16
> It goes (small) 2 to 15 (max), and 32 (small) to 16 (max) ~ and 1 for "always on"
> soo the middle is reversed
> * correct me on the range, i forgot what min and max tCKE was (number)
> 
> EDIT:
> = idk what to use. Because two tCKE's always work for MCLK, 1900 was 9 & 16 for example
> 4133 (2066 MCLK should be 14, but i remember 6 run too ~ soo probably 7is 2100, 8 is 2200, 11 = 2500)
> 
> ~ hmm it might actually be correct. lol
> 
> RTT_NOM i wouldn't run too high personally. It covers the ceiling , but sinus curve needs to ricochet back down
> Soo as low as possible, yet bit higher soo it won't reflect back
> I can see it would show issues with tCKE and generally RTT_WR , once NOM is "lower" , near the /6 range
> /5 - /6 is fine, /7 only bellow 1.54v
> I've seen it only misbehave by different "used" VDIMM
> 
> Keep the RTT_WR /2 , it's good to have it
> But adjust PARK and NOM range
> 
> PARK you'll probably figure out quite fast, as it has an association with procODT and ClkDrvStr.
> You should notice once procODT is too low, or low procODT misses ClkDrvStr ~ well generally once dimms are "underpowered".
> Keep in mind RTT_WR /3 and /2 , fully have different behaviour ranges. Both change lower and upper limits of NOM+PARK
> I did get PARK to drop fully with WR /2 , this works - but it made me issues generally long term stability issues and timing issues with tCKE + SETUP timings
> 
> Generally tCKE and RTT_WR are both hard to time, but doable
> SETUP + WR are worse to time, because SETUP Timings are fixed cuts, and WR does shift this "fixed cut" left and right to align it up to need
> 
> Give something weaker a shot
> NOM /5 , WR /2, PARK /6
> Park can be /7 too, depends if you need to increase ClkDrvStr or not. Can remain on /5 if you don't get PCB Crashes #4 with it (to preserve your 20-20-20-20 CAD_BUS)
> Get the zero's away, for mirror move errors we can take care later too (this likely is either tRP, tRRD_/tWTR , tRDWR or tCKE) ~ something past "one operation" and rather a "transition timing". Or just purely tCKE timing on this MCLK
> 
> We should make a MCLK list for tCKE @Nighthog . Like the one for SETUP Timings.
> View attachment 2517372
> 
> 3 should always run each MCLK. Then it's +1 every 100mhz steps.
> 
> Personally i think this methodic is slightly wrong. It should be +1 every 3 steps not 2, but it falls into the range.
> (especially because 1800 MCLK is tCKE 7 to my math, but tCKE 6 to AMD's bios math ~ both are correct)
> Need to get this tested & written out (3 step scaling for tCKE). Soo much ideas are on backtrack


Great info here! thanks.

I tried [RZQ/5, RZQ/2, RZQ/6] but it ran worse giving me error 1, 8, and 2 I might recall within the first cycle, when it managed to POST.

After that I decided to give the new F34 "final release" bios a try.
I noted this kit can't run 19-19-19-46 spec @ XMP 4400 with GDM:disabled. Only does it with GDM:enabled. Had to do 19-20-19-46 etc for it to work with GDM:disabled.
So this pair has a weaker tRCDRD than the other pair. (the other kit had no issues with 19-19-19 GDM:disabled, i recall)

Mostly AUTO setting I relaxed everything and still giving errors @ 5000Mts regardless of sub-timings around "stock" AUTO variables.
*tRAS* might be a issue at this frequency.
I changed it to *47 * it managed fine for *~1 hour* until error 14 came back again. No other errors 7-11, 7-14 tRDD/tWTR. *@46* tRAS I was having more trouble already in early cycles.

tCKE I was using 21 for a long time but started to play around with it because I was not getting anywhere, there was a small note to take it "might" have been better in the 11 range rather than 21 from some anecdotes I made from observation. So I was just using it temporarily to see what it does overall. Nothing "bad" to note running it like that versus the proper "21".
I've not seen any real effect of changing around tCKE yet on this kit, but I need further testing to compare results.

RttPark has issues with RZQ/6... You struggle with Memory training, F9 way to often. RZQ/5 has no issues whatsoever.

Overall there might be a issue with the tight tWTR I was trying but loosening them to 7-14 AUTO didn't fix issues overall.
Adjusting tRAS had a better overall effect. Might need it to be even looser to function than I tried.
Low subtimings seems to have a general effect to cause Error 0 though, so adjustment might be needed in the end from what I was trying to run.

I do see error 15 come about after a bit of time testing when things look good in general for stability but not there fully.


----------



## Akex

Hi, can you tell me if something is wrong with my schedules? An inconsistency can be?
Here is my stable base, 1usmusv3 80cycle ok, Anta 25 cycle ok, DRAM calculator 48h ok >















Since then for fun I try to switch to C13, here is the result>















How is it that latency level I have exactly the same? It bothers me not to find the culprit ^^


----------



## XPEHOPE3

Akex said:


> How is it that latency level I have exactly the same? It bothers me not to find the culprit ^^


See it @Veii with your own eyes what I've been talking about previously. As soon as tPHYRDL raises from 26 to 28 on at least one of the channels (A/B), with the rest of timings mostly the same, Aida latency would raise (and negate whatever positive effect tCL drop would have). I've seen this on my kit trying to go from tCL/tCWL 16/16 to 16/14, 15/14 and 14/14. It would require tPHYRDL raise on either or both of memory channels. Only tCL/tCWL 14/14 + tPHYRDL 28/28 could lower Aida latency thus far (compared to 16/16 + 26/26), but was nowhere near as stable.


----------



## Akex

XPEHOPE3 said:


> See it @Veii with your own eyes what I've been talking about previously. As soon as tPHYRDL raises from 26 to 28 on at least one of the channels (A/B), with the rest of timings mostly the same, Aida latency would raise (and negate whatever positive effect tCL drop would have). I've seen this on my kit trying to go from tCL/tCWL 16/16 to 16/14, 15/14 and 14/14. It would require tPHYRDL raise on either or both of memory channels. Only tCL/tCWL 14/14 + tPHYRDL 28/28 could lower Aida latency thus far (compared to 16/16 + 26/26), but was nowhere near as stable.


Ok I understand, thank you for your analysis. Is it possible to modify the value in question? Either not the bios itself or via a Bios Mod? I looked carefully and unless I am mistaken it does not appear on the 2404 bios of the b550 Strix-E.


----------



## craxton

hmmm, ive ran furmark WITH TM5 25 cycles, passed!
ran y-cruncher 4 passes (as im still stuck at home so i didnt give much more time)
PASSED, 
yet here today while running chrome, HWinfo, razer synapse in the back, afterburner, and discord "in chrome"
i get a "GREEN" screen? possible blue screen like win 10 but im using win 11 atm. 

im unsure what this would be, as no WHEA events were recorded. and it happened in such a way would suggest ram was at fault here.
but none the less, while the system is "radiating heart" and running a 25 cycle run, im good to go (while the house is warmer as well)
(reported voltage is 1.524/1.528) 
notice anything "big" one might get this completely "random" GSOD or idk BSOD? (was indeed 100% green however)

so


----------



## craxton

Ethelneth said:


> Spoiler
> 
> 
> 
> Currently running 16GBx4 of 16Gb Micron rev B ICs (thaiphoon reports them as C9BLH ICs).
> 3600 CL16 flat at stock voltage:
> View attachment 2517319
> 
> 
> 3800 tRCDRD 17 downvolted (couldn't get tRCDRD 16 stable at any voltage):
> View attachment 2517320
> 
> 
> Note that these can get a bit too hot without direct ventilation. I had dimm1,2 approaching 70°C even if downvolted while running TM5.


do yourself a favor, 
right click your TM5 exe and click,
properties, compatibility, "change settings for all users",
then select run this program as administrator. 
TM5 is screaming at ya as is about it lol...if you dont do it this way,
then you can right click and hit run as admin manually "everytime" you
launch TM5.


----------



## Nighthog

Seems with *RttWR @ RZQ/2* I need to use *RttPark @ RZQ/7*. Doesn't like stronger RttPark at all, RZQ/5 gave blue-screen heaven feelings while earlier tries @ RZQ/6 was problematic.

More testing, unknown territory here. No idea on which RttNom or ProcODT in combination is best...
Isn't without errors though to standard [disabled, disabled, RZQ/5&6]

EDIT: RZQ/5 & RZQ/4 for RttNom seems more reasonable... but not stable either.
Tried more voltage again, not good either... Maybe less?

*EDIT2:* *Less voltage is better, below 1.600V?

EDIT3: still not there but closer? Error 7 now after a longer time.*


----------



## XPEHOPE3

Akex said:


> Is it possible to modify the value in question?


There is no direct way to my knowledge. It's getting its value from memory training. If you force memory training process once again for the same timings, it might train to different values. For example, I had like every combination of 28,30,32 for tPHYRDL for either of memory channels for the same set of timings. So I basically try to bruteforce it by trying to train+post again and again with the same timings, or change some secondary timings (like tRTP 8->10 for you), or change powering (VDIMM, procODT, ClkDrvStr, etc). But I've already tried and it seems that for exactly the use case of lowering tCL/tCWL the approach doesn't work unless you really are into messing with powering your RAM.
Also you can search for Veii's posts for "MBIST" string to see his recommendations for memory training settings (which I mostly adhere to, apart from setting # of agressors to max instead of mid setting). And I tend to give up on certain combination of settings if I can't post with it 3-5 times in a row.


----------



## Audioboxer

Hey @Veii thanks for the help earlier, I polished off my CL16 profile and I'm happy with it. Was going to move over to GDM off stable next on your advice, but I thought I'd have another crack at CL14 first










I took one of my basic settings stable profiles, changed to tCL14, bumped voltage to 1.55v (I'm active cooled, doesn't go above 40 degrees) and increased ProcODT to 48.

No dice though, an error on 6 followed by an error on 12 13 minutes in.

Can yourself or anyone else with experience giving CL14 a go point me in the right direction? I don't mind going a bit higher than 1.55v, but given how quickly this error'd I think I need to sort my timings first to have a real shot at this.


----------



## sendap

does it make any sense to change tWTRL from 12 to 8? 8 is stable but i do not see any obvious performance differences.


----------



## Akex

@XPEHOPE3 
I started to document myself on MBIST, how can I tell you that I hardly understood anything about what to do or not. I understood the principle and are theoretical operation, but in practice I am blind with options of which I do not know their effect.
Here are the screenshots of the bios.





















After enabling MBIST I left the rest at their defaults, not knowing who and what, at least to see the behavior on startup ... didn't post.
I would be happy to learn more but it's not won ^^

@Veii 
Is it possible for you to take an eye when you have time to have an analysis from you, I read your previous post which deals with the subject but I get stuck on this over and over again > 








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Try to replicate these timings And not the frequency :D :D




www.overclock.net


----------



## kratosatlante

Some advice, according to taipoon is micron e die
This is the xmp, and 3800 cl 16 is the best I got, just put the 3600 profile that the calculator gave, 1.5v set vrop 1.46
last bios ch7 4402 cpu pbo+200 only


----------



## Nighthog

kratosatlante said:


> Some advice, according to taipoon is micron e die
> This is the xmp, and 3800 cl 16 is the best I got, just put the 3600 profile that the calculator gave, 1.5v set vrop 1.46
> last bios ch7 4402 cpu pbo+200 only


That's 16Gbit Micron Rev.E, not the same as 8Gbit Micron Rev.E. (DRAM calculator is outdated and doesn't support 16Gbit Rev.E)
Generally behaves worse but similar to bad binned 8Gbit Micron Rev.E. But your not ever getting any good results from these kits. Frequency is really limited to around the 4000Mhz range overall because of a voltage ceiling limit I found on the sample I had, a single rank 2x16GB Kingston 3600 CL18-22-22 kit.

Though work alright down in the usual 3600-3800Mts range as a budget option.
The 16Gbit Rev.E chips just aren't that good. You want the Rev.B 16Gbit for the performance option. But they are more expensive and only sold direct from Crucial only.


----------



## Veii

Akex said:


> How is it that latency level I have exactly the same? It bothers me not to find the culprit ^^


Is this through safemode or why do you lack powermanagement & readouts ?
Write performance is bad 30400MB/s is your goal, but sometimes you overshoot it sometimes you undershoot
Is this by any chance a dual CCD 8 core ?
Can you run ZenTimings Debug menu

tRAS is "low" for you
either too low or too high
Either tRCD+tRTP or tRCDavg*2 or tRCDavg+tBURST

Also on both sets tRFC is too low
It get's postponed
Either you run it as 215, with tWR 10 , tRTP 5 (soo tRAS then 16+5 = 21)
Or you run 258 , with either tRP 6 or 8, soo tWR 12 or 16

On both sets tWTR_L is slow, but tRRD_L is too tight
Match tRRD_L either with tRTP
Or keep them on their own but then match tWTR_L with *2 tRRD_L

I wish the forum would allow us to see written messages further back than 3 months
If anybody still has the GDM On, Off, 1T comparison ~ i seems like don't have it anymore

To showcase that flat timings perform better, and this memhelper guide ~ how well minded it was, does mislead people to always go lower on the timings.
Lower is rarely better


sendap said:


> does it make any sense to change tWTRL from 12 to 8? 8 is stable but i do not see any obvious performance differences.
> 
> View attachment 2517426


Barely
You can drop tRRD_L to 5, tWTR_L to 10, tWR to 10 and tRTP to 5
This will give you a bit of boost
Or ignore all that, and run higher tRTP, higher tWR, higher tRRD_ and go for tRAS = tRCD+tRTP
Like my example shows



Akex said:


> Is it possible to modify the value in question?
> 
> 
> XPEHOPE3 said:
> 
> 
> 
> Also you can search for Veii's posts for "MBIST" string to see his recommendations for memory training settings
Click to expand...

PHY & tMOD, no
Not at all
MSI boards have access to them, but i haven't seen them anywhere inside UEFI capsules so far
It looks to be an MSI exclusive thing only. Integrated in post . Can not find any way to change them

But they will change by the tMAC.tMAW setup, which is accessible inside AMD CBS , near the BURST mode override
And they will change by tRFC2 and 4
Which actually @XPEHOPE3 , you ? mentioned that my tRFC 2 is bad
Problem on such, they don't change. They have never changed on my side and stay consistent


Spoiler: Examples throughout 4 months



































Thats with PBO, but here it actually overshoot again 16B linkspeed-limit

Yet across all boards and bioses, it remained the same for me


Tho now when i compare more, tPHYWRL changes likely by timings


Spoiler

























Akex said:


> After enabling MBIST I left the rest at their defaults, not knowing who and what, at least to see the behavior on startup ... didn't post.


You should not enable it that way.
It does post that way , but data-eye only mode will take 60-65sec to train
sometimes over a minute

Memory training functions anyways without pure Data-Eye mode
But this are your locations for the changes








Last picture only needs to have VRM Patterns to A or 9
And 3 Aggressors
Yet both Pattern modes


Audioboxer said:


> I polished off my CL16 profile and I'm happy with it.


Can we see ?
Working with GDM makes no sense , barely
You will have to redo all your timings if you want to get away GDM (if there are issues)
Because no voltage increase is needed in order to switch away GDM
but a change with procODT , CAD_BUS balancing and RTT balancing is needed
It will clearly show if dimms are unstable or not (badly powered) ~ soo starting with GDM off, 2T saves time
1T then is another topic on its own and can need between 0.04-0.06vDIMM more to keep up same-timing stability


----------



## kratosatlante

Nighthog said:


> That's 16Gbit Micron Rev.E, not the same as 8Gbit Micron Rev.E. (DRAM calculator is outdated and doesn't support 16Gbit Rev.E)
> Generally behaves worse but similar to bad binned 8Gbit Micron Rev.E. But your not ever getting any good results from these kits. Frequency is really limited to around the 4000Mhz range overall because of a voltage ceiling limit I found on the sample I had, a single rank 2x16GB Kingston 3600 CL18-22-22 kit.
> 
> Though work alright down in the usual 3600-3800Mts range as a budget option.
> The 16Gbit Rev.E chips just aren't that good. You want the Rev.B 16Gbit for the performance option. But they are more expensive and only sold direct from Crucial only.


Then they are even worse, they are 2 kits of 32gb, hyperx predator, better than that I will not be able to get it


----------



## sendap

Veii said:


> Barely
> You can drop tRRD_L to 5, tWTR_L to 10, tWR to 10 and tRTP to 5
> This will give you a bit of boost
> Or ignore all that, and run higher tRTP, higher tWR, higher tRRD_ and go for tRAS = tRCD+tRTP
> Like my example shows


thanks, i will give it a try.


----------



## Akex

@Veii
Thank you for your analysis, I will switch back to the 3800C14 to refine the profile with your recommendation (formula).
I have a 5800X with a single CCD. Yes I bench AIDA in safe mode so as not to suffer the possible variations of windows (background software and other) just to have an identical environment between each test, is this a bad idea?
For MBIST I put aside temporarily, although I will come back to it once the corrections of the timings are finished and validated.
The ZT debug report attached.
Thank you 

Edit: For tRAS, are you referring to tRCD-RD or WR?


----------



## mongoled

@Veii

Man how do you do it ?

You spend so much of your most valuable resource (time) helping people who dont follow your instructions.

If I had one golden rule it would be to not help people that wont listen to starting with *GDM disabled.*

You do your best to assist them and they still insist to do their own thing.

Cut them off for your own sake


----------



## Audioboxer

Veii said:


> Can we see ?
> Working with GDM makes no sense , barely
> You will have to redo all your timings if you want to get away GDM (if there are issues)
> Because no voltage increase is needed in order to switch away GDM
> but a change with procODT , CAD_BUS balancing and RTT balancing is needed
> It will clearly show if dimms are unstable or not (badly powered) ~ soo starting with GDM off, 2T saves time
> 1T then is another topic on its own and can need between 0.04-0.06vDIMM more to keep up same-timing stability


Sorry for delay in responding, timings aren't much different from prior pages. I did an anta777 overnight last night but no picture of it, so ran this for last 2 hours just to have something to post.


----------



## Akex

mongoled said:


> @Veii
> 
> Man how do you do it ?
> 
> You spend so much of your most valuable resource (time) helping people who dont follow your instructions.
> 
> If I had one golden rule it would be to not help people that wont listen to starting with *GDM disabled.*
> 
> You do your best to assist them and they still insist to do their own thing.
> 
> Cut them off for your own sake


As much I agree with you but the reverse is also true. There is far too much intervention scattered right to left, and it is not easy to find the information we need. Why am I telling you this? Because I thought as you did this morning, and yet I have been following the thread carefully from almost the beginning. I think that for his good and his free time, it is preferable that he gives us a tutorial with the basic rules concerning the timings, the mistakes not to be made, because we must also not forget that sometimes the information of the one and the other are in total contradiction.
I finished this post to show my gratitude for all the efforts made by him and others in this vast world which is DRAM.


----------



## aditrex

Can someone confirm this 5950x will perform better then 5800x with 4sticks duo to dual Chipley design I keep wondering this current i found myself doing better with 2x8 on my 5800x while there was struggle when trying 4x8 but unfortunately don't have 5900 or 5950x to test myself


----------



## mongoled

Akex said:


> As much I agree with you but the reverse is also true. There is far too much intervention scattered right to left, and it is not easy to find the information we need. Why am I telling you this? Because I thought as you did this morning, and yet I have been following the thread carefully from almost the beginning. I think that for his good and his free time, it is preferable that he gives us a tutorial with the basic rules concerning the timings, the mistakes not to be made, because we must also not forget that sometimes the information of the one and the other are in total contradiction.
> I finished this post to show my gratitude for all the efforts made by him and others in this vast world which is DRAM.


The reverse is also true for oh so many things in the World we live in.

Thats why I emphasized "GDM"

Because if you have spent enough time assisting people with their RAM who are not just happy to have some "basic settings" working then you will know that GDM is the most frustrating factor when attempting to tie down a "baseline" for a given RAM set.

But how ever many times we explain to peeps regards GDM, the majority of people dont listen and do their own thing.

I would have written those people off once they did not listen to that advice.

Thats all I have ot say on this matter and I commend @Veii for having such patience, I do not ....


----------



## Audioboxer

I'm guilty to coming to the party late on the GDM advice, but it is true for newer people like myself (I'm new to b-die) quite a lot of the guidance online from general searches advise keep GDM on, or keep it on "till the end" and give it a go to see if you can get it stable. It's basically passed off as "free extra stability" and/or "ignore it if you're happy with tCL14/16" :/










Took my same settings from above, turned it off and only other change was going 53/53/53 on the setups. I don't even know what they do, the master mem guide here just says try 63/63/63 and then change as needed. I seen someone else do 53/53/53 on b-die DR. But yeah, errors out on 1 a few mins in.

Unless I need to play around with the setup values more, just shows that my timings from a few posts above will pass anta777 overnight (about 7 hours) and 1usumusv3 20 cycles with GDM on, but problems with GDM off with the same timings.

I can feel myself going right back to the start, as I do appreciate @Veii advice and am not ignoring it. I was just desperate to lock down a tCL16 profile after the weeks I've spent on memory already lol. It's tough to do something then be told you probably did it "wrong" and have to start again  I mean, I'm stable above, but I like learning and trying to do things more optimally.










50/50/50 made it a little bit further lol, cycle 2, error on 2, but yeah, messing with settings I don't really know what they're doing.


----------



## Akex

Audioboxer said:


> I'm guilty to coming to the party late on the GDM advice, but it is true for newer people like myself (I'm new to b-die) quite a lot of the guidance online from general searches advise keep GDM on, or keep it on "till the end" and give it a go to see if you can get it stable. It's basically passed off as "free extra stability" and/or "ignore it if you're happy with tCL14/16" :/
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Took my same settings from above, turned it off and only other change was going 53/53/53 on the setups. I don't even know what they do, the master mem guide here just says try 63/63/63 and then change as needed. I seen someone else do 53/53/53 on b-die DR. But yeah, errors out on 1 a few mins in.
> 
> Unless I need to play around with the setup values more, just shows that my timings from a few posts above will pass anta777 overnight (about 7 hours) and 1usumusv3 20 cycles with GDM on, but problems with GDM off with the same timings.
> 
> I can feel myself going right back to the start, as I do appreciate @Veii advice and am not ignoring it. I was just desperate to lock down a tCL16 profile after the weeks I've spent on memory already lol. It's tough to do something then be told you probably did it "wrong" and have to start again  I mean, I'm stable above, but I like learning and trying to do things more optimally.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 50/50/50 made it a little bit further lol, cycle 2, error on 2, but yeah, messing with settings I don't really know what they're doing.


I am not the most qualified to help you, but at home ClkDrvSTR on 60ohm solved my problem with 50/50/50 on 4x8 Bdie.
ProcODT isn't too tall, right? Who told you to put on 48ohm? Maybe less is good. I'll try procODT 36.9ohm.


----------



## Audioboxer

Akex said:


> I am not the most qualified to help you, but at home ClkDrvSTR on 60ohm solved my problem with 50/50/50 on 4x8 Bdie.


It's funny you say that, I'm in the process of running an old stable profile (Not the one above) with far looser timings through a test right now with 53/53/53 and 60/20/24/24 after a friend said just what you have, increase ClkDrvStr. So far 8 minutes and counting 👍

If it passes 3 cycles I'll try it with the timings above. My BIOS has about 8 profiles at the moment with different DDR4 timings lol. A few stable.


----------



## Akex

Audioboxer said:


> It's funny you say that, I'm in the process of running an old stable profile (Not the one above) with far looser timings through a test right now with 53/53/53 and 60/20/24/24 after a friend said just what you have, increase ClkDrvStr. So far 8 minutes and counting 👍
> 
> If it passes 3 cycles I'll try it with the timings above. My BIOS has about 8 profiles at the moment with different DDR4 timings lol. A few stable.


If ever, try 60/20/20/24. it seems to me if I'm not mistaken, that if you go up ClkDrvSTR then you go down CsOdtSetup. In any case, this is the rule that I followed and that worked.


----------



## Audioboxer

Akex said:


> If ever, try 60/20/20/24. it seems to me if I'm not mistaken, that if you go up ClkDrvSTR then you go down CsOdtSetup. In any case, this is the rule that I followed and that worked.


Cool thanks, will try that. Just passed 3 cycles with the above. Obviously not properly stable but that is an improvement over an issue within 1-7 minutes. Now to test the profile above and/or tighter timings.


----------



## XPEHOPE3

Veii said:


> Or you run 258 , with either* tRP 6* or 8, soo tWR 12 or 16


@Akex Misprint - tRTP is meant.


Veii said:


> I wish the forum would allow us to see written messages further back than 3 months
> If anybody still has the GDM On, Off, 1T comparison ~ i seems like don't have it anymore


Do you mean your saved links don't work anymore? That might be due to this thread being cleaned recently.
Anyway, searching forum found this


Veii said:


> Which actually @XPEHOPE3 , you ? mentioned that my tRFC 2 is bad
> Problem on such, *they don't change*. They have never changed on my side and stay consistent
> ...
> Tho now when i compare more, tPHYWRL changes likely _by timings_


I was speaking about rounding of values in your tRFC calculator. It's done via "round" function which sometimes rounds down, thus resulting cycles would give lower latency than targeted.
By "They don't change" you mean what? tPHYRDL? They might change but not necessarily will, just as you saw tPHYWRL. Yes, due to, for example, _other timings changes_ (as I said above)
Also I noticed on your 4000-C19 kit you had tPHYRDL 26/28 on A1/A2 and tCL/tCWL 14/15. Would be interesting to see timing screens for A1/A2 from the same setup but with tCL=tCWL=16. I think that might result in tPHYRDL = 26/26 (not necessarily from one training attempt).



Akex said:


> how can I tell you that I hardly understood anything about what to do or not. I understood the principle and are theoretical operation, but in practice I am blind with options of which I do not know their effect.


Read spoiler here to see what to set and where.


----------



## Akex

We agree that this is how I have to change the timings?









I ask because my English is not good and in doubt, before starting a stress test ... A quick bench


----------



## Audioboxer

No such luck for me @Akex










Didn't think it would be as easy as "just transplanting ClkDrvStr 60" into the mix. Tried a few different Str settings and messed about with ProcODT as well. There might be a combination in here that works but right now it's like blindly throwing darts at a dart board.

The kind of stubborn behaviour Veii and others would say is ultimately wasting your own time!










This went 3 cycles stable with GDM disabled, might give it 20 cycles now and see if I have a base to start with for GDM disabled. Voltages are a bit higher on this (VDDG/VDDP) as it was a "safe stable" profile, so might even drop them a bit before doing a 20 cycle.


----------



## Akex

Audioboxer said:


> No such luck for me @Akex
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Didn't think it would be as easy as "just transplanting ClkDrvStr 60" into the mix. Tried a few different Str settings and messed about with ProcODT as well. There might be a combination in here that works but right now it's like blindly throwing darts at a dart board.
> 
> The kind of stubborn behaviour Veii and others would say is ultimately wasting your own time!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This went 3 cycles stable with GDM disabled, might give it 20 cycles now and see if I have a base to start with for GDM disabled. Voltages are a bit higher on this (VDDG/VDDP) as it was a "safe stable" profile, so might even drop them a bit before doing a 20 cycle.


Try CommandRate 2T.


----------



## Audioboxer

Akex said:


> Try CommandRate 2T.


True, could help










Gonna let this run out to 20 cycles though, just over halfway.


----------



## paih85

clean error. @1.45v only. dual rank 2x16gb. aida latency ~52.6 ns


----------



## XPEHOPE3

Audioboxer said:


> Gonna let this run out to 20 cycles though, just over halfway.


I recently had a run with the first error on cycle #23 (tests 12 and 5). Happened when tried to go from 202.76ns tRFC to 198.62ns tRFC. As one approaches tightest boundary of such settings one has to run TM5 1usmus_v3 config longer to catch such "building-up" errors. Maybe 25 cycles even are not enough.









And to catch 195.52ns tRFC error (test 2) I needed ~16 cycles:









This testing provides estimate on tRFC value, and it's *faster than binary search*, proposed here.
Here's the math. Suppose all settings _apart from tRFC_ are the same between the three runs, and two runs failed at certain # of cycle, while the third run (say, with default tRFC of 350ns) didn't. That would imply whatever errors you encounter come from tRFC (the third run isn't necessary if you are sure the two other runs fail exactly due to tRFC). Let's name failed runs as A and B, cycle number at which it failed as A_cycle and B_cycle, etc. (Those are not always present in the ending screen, so you can setup *HWINFO64 audio alerts* on free RAM available and after each cycle of TM5 passed you'll hear an alert, go check if there are any errors. For the sake of this test you can stop TM5 on the first error).
What I think is that the smaller the difference between tight tRFC and failing one, the more cycles TM5 needs to catch an error. And I think the dependence is *linear*. Assuming this reverse linear dependence, an equation can be written: A_cycle*(ok_tRFC - A_tRFC) = B_cycle*(ok_TRFC - B_tRFC). Solving this yields ok_tRFC = (A_cycle*A_tRFC - B_cycle*B_tRFC)/(A_cycle-B_cycle). [Obviously, if you have errors in the same cycles, you have to use exact minutes errors happened instead of "_cycle", but those are rarely in the log] Using screenshots above, and inserting numbers: ok_tRFC=(21*384-16*378)/(21-16)=2016/5=403.2. And guess what? I have this stable (at tRFC 392 < 403.2):









Of course the boundary achieved isn't tight (that's called "conservative") because testing times depend on tRFC value a lot.
If anyone is ready to waste his time to test this math I'll be glad to hear your results


----------



## Audioboxer

XPEHOPE3 said:


> I recently had a run with the first error on cycle #23 (tests 12 and 5). Happened when tried to go from 202.76ns tRFC to 198.62ns tRFC. As one approaches tightest boundary of such settings one has to run TM5 1usmus_v3 config longer to catch such "building-up" errors. Maybe 25 cycles even are not enough.
> View attachment 2517489
> 
> 
> And to catch 195.52ns tRFC error (test 2) I needed ~16 cycles:
> View attachment 2517490
> 
> 
> This testing provides estimate on tRFC value, and it's *faster than binary search*, proposed here.
> Here's the math. Suppose all settings _apart from tRFC_ are the same between the three runs, and two runs failed at certain # of cycle, while the third run (say, with default tRFC of 350ns) didn't. That would imply whatever errors you encounter come from tRFC (the third run isn't necessary if you are sure the two other runs fail exactly due to tRFC). Let's name failed runs as A and B, cycle number at which it failed as A_cycle and B_cycle, etc. (Those are not always present in the ending screen, so you can setup *HWINFO64 audio alerts* on free RAM available and after each cycle of TM5 passed you'll hear an alert, go check if there are any errors. For the sake of this test you can stop TM5 on the first error).
> What I think is that the smaller the difference between tight tRFC and failing one, the more cycles TM5 needs to catch an error. And I think the dependence is *linear*. Assuming this reverse linear dependence, an equation can be written: A_cycle*(ok_tRFC - A_tRFC) = B_cycle*(ok_TRFC - B_tRFC). Solving this yields ok_tRFC = (A_cycle*A_tRFC - B_cycle*B_tRFC)/(A_cycle-B_cycle). [Obviously, if you have errors in the same cycles, you have to use exact minutes errors happened instead of "_cycle", but those are rarely in the log] Using screenshots above, and inserting numbers: ok_tRFC=(21*384-16*378)/(21-16)=2016/5=403.2. And guess what? I have this stable (at tRFC 392 < 403.2):
> View attachment 2517492
> 
> 
> Of course the boundary achieved isn't tight (that's called "conservative") because testing times depend on tRFC value a lot.
> If anyone is ready to waste his time to test this math I'll be glad to hear your results


I'm no expert, far from it, I had Micron e die before this and a pretty meh bin so it was 3733 and some DRAM calculator settings and calling it a day. Only since I got a new processor (can do 1900 now) and switched over to this b die have I had to get my learning hat on and listen to others and make my own mistakes along the way.

Prior to popping up in here on the last pages I was running anta777 overnight. I will continue doing that as it can end up 7-9 hours on DR. 1usmusv3 I've just been doing for advice on knowing what errors mean for short blasts of stability. 20 cycles is about 2 hours for me, I'd never sign that off as long term stable.

I believe tRFC is pretty temperature sensitive. While it can scale great with voltage to get really tight I noticed your peak temps are around 45. My newbie take is under 50 for b die is just about necessary but also the closer you get to 50 the more likely you will be for super tight timings to give in. Running a test for hours is likely to get temps up.

Point a fan at your ram and it should stay under 40, or as you've found out maybe just need to loosen up tRFC. Take all this with a "I could be completely wrong" though, I'm far from knowledgeable on DDR4 let alone the specifics of b die.


----------



## XPEHOPE3

Audioboxer said:


> Point a fan at your ram and it should stay under 40


That's already with active cooling set up like this. 😅 Given it's whopping 31C ambient here I'd say it's "good enough".
And yes, those temps hold even for longer periods (notice how I have to run 6.5 hours because I have 64GB kit). And I saw people running 1usmus_v3 for 100 cycles  for smaller kits exactly for the reason you stated
I also ran anta777 extreme until I found situation where it didn't find errors while 1usmus_v3 did. But it does find some errors much faster than 1usmus_v3.

Also it's important to run y-cruncher (pressing 1-7-0 to run all tests) especially if you messed with voltages/resistances. That also would fail if your CPU overclock is faulty.


----------



## Audioboxer

XPEHOPE3 said:


> That's already with active cooling set up like this. 😅 Given it's whopping 31C ambient here I'd say it's "good enough".
> And yes, those temps hold even for longer periods (notice how I have to run 6.5 hours because I have 64GB kit). And I saw people running 1usmus_v3 for 100 cycles  for smaller kits exactly for the reason you stated
> I also ran anta777 extreme until I found situation where it didn't find errors while 1usmus_v3 did. But it does find some errors much faster than 1usmus_v3.
> 
> Also it's important to run y-cruncher (pressing 1-7-0 to run all tests) especially if you messed with voltages/resistances. That also would fail if your CPU overclock is faulty.


Ooft, the wonder of the dark arts of memory overclocking/stability testing lol. Good luck!

Meanwhile, this seems to be semi-stable for me, passed 20 cycles










1.45v on VDIMM.

My goal is to try and get CL15 but I'm not sure where to even begin right now. Previously I worked on secondaries first, primaries last, but now I have the "right hand side" to worry about. Like should I just leave the setups at 53 now? Then 60/20/24/24 doesn't seem optimal, suggestions earlier to try 60/20/20/24 instead. 

If anyone has any guidance for where I should go next that would be great. This is some progress for GDM off for me anyway. That's a start.


----------



## spajdr

Hello gentlemen,
I got finally stable 1933FLCK with 4x8GB.
Is there anything I could improve on timings or on anything else?


----------



## mongoled

Audioboxer said:


> Ooft, the wonder of the dark arts of memory overclocking/stability testing lol. Good luck!
> 
> Meanwhile, this seems to be semi-stable for me, passed 20 cycles
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 1.45v on VDIMM.
> 
> My goal is to try and get CL15 but I'm not sure where to even begin right now. Previously I worked on secondaries first, primaries last, but now I have the "right hand side" to worry about. Like should I just leave the setups at 53 now? Then 60/20/24/24 doesn't seem optimal, suggestions earlier to try 60/20/20/24 instead.
> 
> If anyone has any guidance for where I should go next that would be great. This is some progress for GDM off for me anyway. That's a start.


Few things stick out to me, but please beaware I dont have experience with DR so what I am going to point out are general "rules"

Firstly as you are using tRTP @8 then tWR should be 16 (tRTPx2), the lowest you should drop tWR is minus 2 from that value, hence 14.

Next tRDRDSD/tRDRDDD set those to 4 and tWRWRSD/tWRWRDD set those to 6.

Also your tRFC values, im unsure what rules you are following for setting those.

If you going to tighten your primaries than ideally set AddrCmdSetup/CsODTSetuo/CkeSetup back to 0 and set CMD2T to 2T


----------



## Audioboxer

mongoled said:


> Few things stick out to me, but please beaware I dont have experience with DR so what I am going to point out are general "rules"
> 
> Firstly as you are using tRTP @8 then tWR should be 16 (tRTPx2), the lowest you should drop tWR is minus 2 from that value, hence 14.
> 
> Next tRDRDSD/tRDRDDD set those to 4 and tWRWRSD/tWRWRDD set those to 6.
> 
> If you going to tighten your primaries than ideally set AddrCmdSetup/CsODTSetuo/CkeSetup back to 0 and set CMD2T to 2T


Thanks, IIRC the skeleton of these settings was just ripped out of the DRM calculator and then used when I first got this RAM for an overnight stability test. I haven't done anything else with them other than get the PC booting with GDM off.

I'll do what you said then run the stability test again for 20 cycles. Not big changes but I want this base bulletproof before I save it as my starting point template for GDM off.


----------



## mongoled

Audioboxer said:


> Thanks, IIRC the skeleton of these settings was just ripped out of the DRM calculator and then used when I first got this RAM for an overnight stability test. I haven't done anything else with them other than get the PC booting with GDM off.
> 
> I'll do what you said then run the stability test again for 20 cycles. Not big changes but I want this base bulletproof before I save it as my starting point template for GDM off.


Please be aware of the following and source the info required from people using DR before you decide to go futher with your testing.

Regarding your RttNom/RttWr/RttPark values.

If you are not aware these values are responsible for powering the dimms.

RttPark of RZQ/1 is the most aggressive settings and has been known to kill dimms once your vDIMM voltage increases over 1.5v.

As you are going to be aiming for CAS 15 then for sure you are going to have to increase your vDIMM from 1.45v.

So I strongly suggest you look to see how other people are powering there DR modules and pay attention to those that are NOT using RttPark set to RZQ/1

FYI for my 4x8GB modules I use the following settings while pushing 1.52v

RttNom RZQ/7
RttWr RZQ/3
RttPark RZQ/3


----------



## Audioboxer

mongoled said:


> Please be aware of the following and source the info required from people using DR before you decide to go futher with your testing.
> 
> Regarding your RttNom/RttWr/RttPark values.
> 
> If you are not aware these values are responsible for powering the dimms.
> 
> RttPark of RZQ/1 is the most aggressive settings and has been known to kill dimms once your vDIMM voltage increases over 1.5v.
> 
> As you are going to be aiming for CAS 15 then for sure you are going to have to increase your vDIMM from 1.45v.
> 
> So I strongly suggest you look to see how other people are powering there DR modules and pay attention to those that are NOT using RttPark set to RZQ/1
> 
> FYI for my 4x8GB modules I use the following settings while pushing 1.52v
> 
> RttNom RZQ/7
> RttWr RZQ/3
> RttPark RZQ/3


Thanks soo much for that tip! I haven't read this before and just took it for granted disabled/3/1 was sort of "universal" for b-die DR. Guess it makes sense why the poster on the last page is using 3 [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

The more you learn 

*Edit*: Changing it to 3 means my PC doesn't post, LOL. I guess it's back to the drawing board with all timings. Kids, this is why you don't try and cut corners with memory overclocking


----------



## mongoled

@Audioboxer 

For your CL15 I would attempt this

Regards your issue with not posting with RZQ/3, thats a first for me!

The values that are marked as AUTO, I would change these to AUTO in your CL16 settings to see if it will post after setting RttPark RZQ to 3


----------



## Nighthog

Audioboxer said:


> I'm no expert, far from it, I had Micron e die before this and a pretty meh bin so it was 3733 and some DRAM calculator settings and calling it a day. Only since I got a new processor (can do 1900 now) and switched over to this b die have I had to get my learning hat on and listen to others and make my own mistakes along the way.
> 
> Prior to popping up in here on the last pages I was running anta777 overnight. I will continue doing that as it can end up 7-9 hours on DR. 1usmusv3 I've just been doing for advice on knowing what errors mean for short blasts of stability. 20 cycles is about 2 hours for me, I'd never sign that off as long term stable.
> 
> I believe tRFC is pretty temperature sensitive. While it can scale great with voltage to get really tight I noticed your peak temps are around 45. My newbie take is under 50 for b die is just about necessary but also the closer you get to 50 the more likely you will be for super tight timings to give in. Running a test for hours is likely to get temps up.
> 
> Point a fan at your ram and it should stay under 40, or as you've found out maybe just need to loosen up tRFC. Take all this with a "I could be completely wrong" though, I'm far from knowledgeable on DDR4 let alone the specifics of b die.


I learned Micron Rev.E [D9WFL] get temperature sensitive the higher frequency you run them irregardless of timings, though tight settings make it harder to pass if you reach the temperature threshold the frequency allows.
@ 5000Mts this [D9WFL] has a temperature threshold ~46C where it will blue-screen if you allow it to run that high for too long as errors get exponential at that temperature.
@5100Mts, I've noted the threshold might be even lower ~36C where you can't exceed it if you want to have any stability at all. It's great when your system is idle 34-36C for foolish tries to see if you can make it run.
The older rev.E [D9VPP] where quite sensitive as well if I didn't have them cooled well enough but can't remember at which threshold they could tolerate at the lower frequencies they managed.
Rev.J where a breeze to use and never found a limit at the settings/speeds I tried it with. Could run them passive air-cooled as far as I could see. They didn't get that hot but managed only ~4800Mts with the kit I used, but 1.700V wasn't a issue like with Rev.E [D9VPP] who would get much hotter running like that requiring good airflow/water blocks.
The Rev.E [D9WFL] doesn't tolerate as much voltage (~1.600V max) but you hit this ceiling if you want to go for frequency where you get lower and lower temperature limits.


----------



## Audioboxer

mongoled said:


> @Audioboxer
> 
> For your CL15 I would attempt this
> 
> Regards your issue with not posting with RZQ/3, thats a first for me!
> 
> The values that are marked as AUTO, I would change these to AUTO in your CL16 settings to see if it will post after setting RttPark RZQ to 3
> 
> View attachment 2517506


Ok so before I seen this post I decided to Auto a few things in the BIOS anyway, ProcODT, Nom, Wr and Park when on auto do the above, 43.6, disabled, 3, 1.

Then I tried what you have given me, no post again. Then I tried Park at 1, it posts, but BSOD the second the desktop loaded. So I've just tried disabling Nom again and now I'm on the desktop, no BSOD yet but I haven't started testing yet. So, current settings










Biggest issue for me is therefore getting this posting with Park on 3. Won't even post, and it's looking like 7/3/1 might have caused my BSOD, but I'd need to test that. As I'm typing this though I still haven't BSOD with disabled, 3, 1. Will try running a TestMem5 now.

Maybe it's the DrvStr?


----------



## mongoled

@Audioboxer

set all DrvStr to AUTO

report back

Your tRDWR/tWRRD values are extemely high, is that what they default to ??

** EDIT **

After you set those AUTO values, can you turn off the PC, remove the power from the PSU, let sit for 1 minute, then power it back up and report if the AUTO values have changed ...


----------



## XPEHOPE3

mongoled said:


> Regards your issue with not posting with RZQ/3, thats a first for me!


Regular for me. With 4*16GB DR I could only post to RTTPark/2 once on AGESA 1.2.0.3a. On AGESA 1.2.0.3b it's much easier, but gave no profit yet. RTTPark/3 just won't post at all for me, but then I didn't try all the possible combinations. Even if I did, successful combination is unlikely to survive an AGESA update.


----------



## Veii

XPEHOPE3 said:


> I was speaking about rounding of values in your tRFC calculator. It's done via "round" function which sometimes rounds down, thus resulting cycles would give lower latency than targeted.


Yes yes
Just re'menioning it, because tRFC 4 and tRFC2 influenc tMAC generation. Also influence tMAC.tMAW generation (tRC_Page)
And funnily should generate tRFC 1 (reverse) ?

I never had issues with it, soo absolutely never bothered to check about it. At least all inconsistency issues where not depending on these (as they got resolved)
Tho looked on on MSI boards and PSONE's work in reaching 46.8 ?, sub 47ns @ 4000MT/s 14-14-14-14
In private decided that he probably runs SPD modified kits with lower values we can not change. But the MSI latency tweak , or alone the access to them surely gives an upper hand
Yet ASRock with their most limited bios out of all board partners (tho stable, to give credit where it's due) ~ doesn't have such. We don't even get any telemetry faking options ~ soo never bothered


XPEHOPE3 said:


> Also I noticed on your 4000-C19 kit you had tPHYRDL 26/28 on A1/A2 and tCL/tCWL 14/15. Would be interesting to see timing screens for A1/A2 from the same setup but with tCL=tCWL=16. I think that might result in tPHYRDL = 26/26 (not necessarily from one training attempt).


Good catch, i'll take a look
First picture was made to show BURST changes with some new IMC FW update after SMU 56.46/56.50 ~ which broke/changed how tFAW behaves

Mostly the reason for comment was ~ that throughout all the testing , they never "randomly" changed on boot
Now it can be different ~ i'll remember to take a look and note down. Especially when memory training is beyond broken atm
2000 posts, 2033 posts every 2nd reboot, 2067 posts one of 6 reboots  don't ask me about 2100. . .
But if i desync MCLK from UCLK - 2100 posts every time. MCLK has training issues for me. Timings are really tight 4000 C14
(goes up to 2033 without issues, 2067 not fully stable soo i'm back to 15-15)
and 4200 15-15-15 are really tight sets.
Need to spend (once a month as always) 12-14h to figure out the maximum limits of these dimms and somehow at the same time fix broken memory training

Every windows to uefi reboot needs 2 restarts.
Every coldboot needs two restartst. It's beyond annoying . But i had that early with 2100 & why CsOdtDrvStr beyond 30 was required for Vermeer (got set by me) . Mostly 40 runs but that depends on ClkDrvStr too
24-20-24-20 / 24-20-20-24 was Matisse only
(but Yuri's 30-20-20-24 or 24-20-20-24 trick, worked well on my B350 Tomahawk. Just they do not work at all anymore for me on Vermeer. Memory training is just purely a mess for anything non Rev.E/B)


ManniX-ITA said:


> @Veii
> about tCWL
> something I forgot to ask you since longtime
> 
> Is it really better to keep it lower than tCL?
> it is worth trying to get it as low as possible or counter productive?


Counterproductive
Don't focus 100% on JEDEC rulesets , but your feeling is correct
But the same goes for both tRCD's
It nearly always is counterproductive, but there is not only one correct method of optimizing DRAM and SDRAM

At the very beginning i did the same too, it probably was good practice by all the Intel OCers & the public resources build upon such
But figured at least a year ago, that it's contra productive. You desync it
One lower often passes when you adjust your chain (tho it creates new foreign "overlapping" timing issues when using it)
But 2 lower (it can go down 4 lower) is not a good idea.
Tho i'm lacking bit more research time with it , to 100% decide.
It can be used for tRC ruleset (tRCD_WR+tCWL+tWR+tBURST ~ well or tCCD_L)
That seems to align, but the major part likely is the tRCD_WR.
On pure flat sets it desync's it and causes performance loss
Gives read bandwidth but loses copy & at absolute best gave 0.2ns improvement.
I'd rate it the same as the SCLs. They give a performance boost but you also trade something for it.

I run for at least a year the experimental mindset for tRCD_WR pushing, but ultimately settled to do everything possible in bruteforcing low tRCD (both)
That gave the most performance bump (EDIT: and settled for tRP = tRCDavg, as i was not running tRAS as bursty but rather as 2-4 loops based ~ tFAW)
tRRD_ increase doesn't cut thaat badly into the latency or performance. tRDWR increase does, but around +1 is bearable, +2 "wasted" already hides issues
tRC is a remain open topic. Same for tRAS.
I see the tRAS intel "trick" performs good, but can also see that it limits my possible MCLK. I think it's too bursty. tRAS+1 = tRC trick for 1x tFAW refresh mode (that way burst refresh) worked better than tRASmin trick
Still haven't decided. There are couple more tricks & exploits i want to try (SCL and SD, DD tricks) i'm not fully comfortable with ~ yet.

RTTs i nearly nailed down so far.
Temp savings are worth the hassle, and i would never go back to the old Yuri research. (but he did fantastic work with Matisse !)

tWTR_ i still struggle slightly. Figured a balancing trick for SD, DD & why i sometimes run +2 in between RD & WR, and sometimes +3 ~ inspiration psone [chiphell] 
Generally yes, performance is key but latency is first, (higher SD, DD's give more perf but can easily overlap other timings and cause perf issues)
If by lower latency bandwidth suffers, it's disbalanced. Soo Aida64 is my best friend for such. SiSandra too when the CPU, the powerplan & the OS is settled


mongoled said:


> @Veii
> Man how do you do it ?
> You spend so much of your most valuable resource (time) helping people who dont follow your instructions.
> If I had one golden rule it would be to not help people that wont listen to starting with *GDM disabled.*
> You do your best to assist them and they still insist to do their own thing.
> Cut them off for your own sake


Don't be too harsh to people.
There is a far to big intelOC scene & JEDEC (holy book) praising scene, which people are looking back at
I find it more sad, that such thing wasn't tested beforehand but simply accepted. GDM on is slower for many reasons.
It is sub 70MB/s faster in read & copy , because not everything is 2T slowed.
It does half the strain to the PCB and one of the major reasons why high speed kits "function" that easily. 

But it does hide powering issues, it does round timings and allows lower tRFC (by the lower PCB strain)
Unless you can run -2 tCL,-2 tRCD with it (12-12-12 instead 14-14-14) , i see absolutely no reason to ever consider it. Maybe when you push MCLK records or on XOC (sub 100ns tRFC)
0.7-1.3ns latency difference (with and without it) are significant. 0.2ns drop is already "significant" ~ tho it could be also test-by-test error. Over 0.5ns difference (which is between 1T and 2T) is already a feelable part 
Feelable in the sense of "trackable across many rendering benchmarks". Not a tiny difference

Probably the most important reason to settle for 2T instead of GDM, is to finally see if your dimms are powered correctly and your timing "loop" is correctly set.
It will very fast fail if powering is bad to begin with.
You'll always have to start from the scratch, when you want GDM away.

CL14 looks good, i know
Lower numbers look always good ~ but it makes more fun (personally) when your "bad" timings are plain faster than tCL 15 or 14 kits 
H*ck, we should blame Companies like G.Skill, for continuing this trend. "High voltage, low tCL , bad tRCD binning kits" ~ because the low tCL number looks good
Or basing PCB binning off of tCL ...
No wonder "different thinking people" get that much crossfire and hate. The whole industry is messed up
But you can't help it. Just keep repeating and reposting the same thing to new people. Someday it will reach the masses 
Nobody new can do anything against being marketing fooled, don't blame everyone who comes to ask for help 
The only reason we see no 1.65v kits, is likely that B-die has architectural issues beyond 1.6v. (well beyond 1.7v for sure) where ICs just stop functioning and drop out 
(needing maxmem of 1C per PCB side)
I'd never buy high voltage XMP kits. They are pretested but would very surely think they are lower but stretched binning.
Good binning can run low voltage with tight tRCD. 
Only would buy high Frequency kits, to know the PCB is not a snowflake (A0) ^^' , but except for that, voltage will not magically change binning to some extend
Only fool people to spend 70-100$ more for their "probably lower quality" low tCL sets.
But as stated, "the whole industry is likely messed up" 
There was no competition to even bother caring at all. Near the end of DDR4 we finally start to get board-partners take care which PCB they use and actually bother matching sets 
(Kind of. Situation is still bad)
Soo don't bother all too much. Don't think only about yourself, while yes ~ it's annoying for sure  


Audioboxer said:


> True, could help
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Gonna let this run out to 20 cycles though, just over halfway.


Yes 2T , 1T is a whole new topic and everything has to be perfect to run pure 1T 

You can fail by heat here, because RTT_PARK is too strong 
Also the set will perform worse, as the board falls back to SETUP timings
It's the best to remove them ~ at least for 2T.
You don't need another slowdown, while beyond the half cutting point (half of the max value) they switch to Command Rate 2T type of behaviour . Soo slow down things to maintain stability
I'd really wipe them away

tRTP is too high here. I know it fits tRFC , it's a clean divider, soo it will be stable
But you can likely pass it with tRTP 6
If you fail, then you can give tRRD 6-8, tWTR 5-14 a try , but with SD, DD 1-4-4-1-6-6. At worst 1-3-3-1-6-6
This has to pass then, but all is theory ~ till you show results. Multiple benchmarks of aida64 cache result (easier to use than SiSoftware Sandra)
But always ignore the first Aida64 test after boot. 
It needs some load till it activates C-States, and power management actually starts to function (after boot)
Another advice is to take Autoruns for Windows - Windows Sysinternals
Run the Autoruns64.exe and disable all Microsoft Edge, Java, Flash & One Drive ~ updating EXE's & DLL's which autorun 
That should mostly be enough to keep consistency between tests. 


Akex said:


> If ever, try 60/20/20/24. it seems to me if I'm not mistaken, that if you go up ClkDrvSTR then you go down CsOdtSetup. In any case, this is the rule that I followed and that worked.


Ty for this (i'll remember it) . Probably spread around Matisse Era
You'd need beyond 30 CsOdtDrvStr to fix broken memory training

I think you can take a read AMD max overclocking voltage on this whole thread
The theory won't change. The voltages can slightly because Ryzen keeps changing Firmware and so basic behaviour. But the theory doesn't
ClkDrvStr is good to use. Low ProcODT is very valuable. But Vermeer autocorrects on too many parts. Soo you need to actively benchmark, in order to find little flukes 
All procODTs will post, but only 1 of them will give no variance or sub 0.2ns variance between tests.
Do not cherry pick test tests. At least not when testing consistency between tests. Power management needs time to utilize and boost consistently.
You likely also haven't heard of this sheet. Use it as competitive motivation 








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com






Akex said:


> I have a 5800X with a single CCD. Yes I bench AIDA in safe mode so as not to suffer the possible variations of windows (background software and other) just to have an identical environment between each test, is this a bad idea?
> For MBIST I put aside temporarily, although I will come bac


You lack WMI (error reporting), Powermanagement & so proper cache boost, and it's not real 
For me as exception (like it seems) Safe-Mode performs 0.3ns worse than booted maintained windows

You can get the normal OS behaving better than Safe-Mode
But safe-mode will hide WHEAs as it lacks correct drivers, powerplans and also any type of cache speedup (boost)
It's fine to only start comparing on it, but it does only help yourself & will never show if your CPU is actually stable to begin with
* Notes on "you lack write bandwidth" soo curve optimizer, powerplan or something made issues. In order to exceed perfect half bandwidth ~ something has to either Overboosted (cpu bug) or you had a messed up dual CCD unit 
Soo i point to overboost issue ~ but you wouldn't even be able to track your inconsistency, as it's under safe-mode


----------



## mongoled

XPEHOPE3 said:


> Regular for me. With 4*16GB DR I could only post to RTTPark/2 once on AGESA 1.2.0.3a. On AGESA 1.2.0.3b it's much easier, but gave no profit yet. RTTPark/3 just won't post at all for me, but then I didn't try all the possible combinations. Even if I did, successful combination is unlikely to survive an AGESA update.


Great!

So @audiotest can try RZQ/2 its better than RZQ/1


----------



## Veii

Nighthog said:


> The older rev.E [D9VPP] where quite sensitive as well if I didn't have them cooled well enough but can't remember at which threshold they could tolerate at the lower frequencies they managed.


Yep , it's funny
Rev.E posts everything i trow at them, but after 1hour even sub 40c they start to spill out errors.
I can not accept any stable results of them sub 1hour testing 


XPEHOPE3 said:


> Regular for me. With 4*16GB DR I could only post to RTTPark/2 once on AGESA 1.2.0.3a. On AGESA 1.2.0.3b it's much easier, but gave no profit yet. RTTPark/3 just won't post at all for me, but then I didn't try all the possible combinations. Even if I did, successful combination is unlikely to survive an AGESA update.


RZQ , DQs & procODT behavior already changed since 1.2.0.0. (They changed much more in the hidden, as new germlings continue to appear day by day)
it's unlikely to change again, but better run something weaker ~ till you actually see it making issues
Except RTT work and tCKE timing - there is no other method to lower strain or heat on the dimms (well maybe by not using such tight tRRD_ and tWTR timing) 
But you'll need to exceed 1.6v sooner or later 
RTTs are VDIMM , procODt and ClkDrvStr sensitive
Also tCKE and SETUP timings can mess them up easily

RTT_WR is great to use, but you don't really need it for any capacity.
Only utilize it at the very end, as it changes how NOM and PARK behave
NOM you want more the higher you go with voltage and PARK you want it weaker the more procODT , ClkDrvStr or VDIMM you give
Disabled only works with RTT_WR is utilized, but you're not even close to such


----------



## Audioboxer

mongoled said:


> @Audioboxer
> 
> set all DrvStr to AUTO
> 
> report back
> 
> Your tRDWR/tWRRD values are extemely high, is that what they default to ??
> 
> ** EDIT **
> 
> After you set those AUTO values, can you turn off the PC, remove the power from the PSU, let sit for 1 minute, then power it back up and report if the AUTO values have changed ...












Error'd on 12.

And yeah my tRDWR and tWRRD come up with those figures on auto :/

I just tried DrvStr on auto with 7/3/3 and again won't post. Put just about everything on auto and I get this










DrvStr on auto just defaults to 24.

Going to turn off/unplug and wait 5 minutes as you recommend but I'm going to assume 18/7 will still be the values.

*edit:* Yeah, still 18/7


----------



## paih85

Audioboxer said:


> Error'd on 12.
> 
> And yeah my tRDWR and tWRRD come up with those figures on auto :/
> 
> I just tried DrvStr on auto with 7/3/3 and again won't post. Put just about everything on auto and I get this
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> DrvStr on auto just defaults to 24.
> 
> Going to turn off/unplug and wait 5 minutes as you recommend but I'm going to assume 18/7 will still be the values.
> 
> *edit:* Yeah, still 18/7



try my setting..



paih85 said:


> clean error. @1.45v only. dual rank 2x16gb. aida latency ~52.6 ns
> 
> 
> View attachment 2517491


----------



## Audioboxer

mongoled said:


> Great!
> 
> So @audiotest can try RZQ/2 its better than RZQ/1


Nope lol, not for having it. Will not boot on 2 either, demands 1 lol.










The only difference on this run from above is DrvStr on auto, error'd out this time on 10.

I'll go try some RttPark on 2/3 with some of my CL16 profiles with GDM on.



paih85 said:


> try my setting..


Can't seem to boot with RttPark on 3. I'll try though.

I'm on AGESA V2 PI 1.2.0.3 Patch A. Looks like patch B could help? I don't have that available for my board yet though.


----------



## XPEHOPE3

Veii said:


> Tho looked on on MSI boards and PSONE's work in reaching 46.8 ?, sub 47ns @ 4000MT/s 14-14-14-14


Why isn't it on the list then? Not stable?


Veii said:


> On pure flat sets it desync's it and causes performance loss
> Gives read bandwidth but loses copy & at absolute best gave 0.2ns improvement.


Fantastic, but that 0.2ns is exactly the result I got going from 3866-16 flat to 3866-16-15-15-15. 15 flat even when posts gives higher latency (due to tPHYRDL becoming 28 instead of 26). I think to run 3866-15 flat I need to redo powering, but that would eat too much time (again). I'd better flash new *stable* Gigabyte AGESA 1.2.0.3b BIOS.


Veii said:


> tRC is a remain open topic. Same for tRAS.


From my current testing there was no perf improvement going from tRAS 34 to tRAS 36 to tRAS 32, irrespective of tRFC being 56, 48 or 49 (tRFC being fixed on 392, the lowest stable I managed to find).


Veii said:


> Every windows to uefi reboot needs 2 restarts.
> Every coldboot needs two restartst. It's beyond annoying .


Suppose you are a noob 😅 going into this topic for advice on this matter. What would you advice yourself?) I remember you saying, apart from CsOdtDrvStr and MBIST, that you can relax secondary/tertiary timings to ease posting. Given what I've just written about tRAS and tRC I think one can consider them even tertiary, third-world timings 🤣, and relax those, as they really can forbid posting. (Forget about mathematically beautiful relationships for a moment ).


----------



## mongoled

XPEHOPE3 said:


> due to tPHYRDL becoming 28 instead of 26


Good catch !!

Can confirm on my setup

[email protected] defaults tPHYRDL to 26
[email protected] defaults tPHYRDL to 28

[email protected] has better latency by 0.2-0.3 ns compared to CL14


----------



## Audioboxer

Yeah, I'm giving up on RttPark 2/3. Maybe once Patch B hits my mobo.

Thought I was getting somewhere with timings but I crashed again










21 minutes in. Changes from earlier were changing tRDWR/tWRRD to something more sensible than auto, tWR to 14 and my SD/DD's back to 5/5/7/7 just because error #10 I had previously seemed to suggest it could be them.

Now I have an error 12 again 🤣 This is at 1.5v. Unless VDDP/VDDG could play a role now but they aren't exactly low.


----------



## Veii

Audioboxer said:


> Now I have an error 12 again 🤣


Check tRFC mini - TM5 error description








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com












Try to run 40-20-30-20 CAD_BUS
60-20-20-24 also is an option
same as 30-20-30-20


XPEHOPE3 said:


> Why isn't it on the list then? Not stable?


He is also a teacher like me, but maintains the CH Chiphell forum
We barely have any connection - only our results often jump sites


XPEHOPE3 said:


> I'd better flash new *stable* Gigabyte AGESA 1.2.0.3b BIOS.


Our beta is strange, but it looks stable
At least fallback functions on bad tCL (too well i think) but memory training is too short
I think i have 1203A too - They should have gotten it mid April, but ASRock delivered it mid-july now. They are slow



XPEHOPE3 said:


> Suppose you are a noob 😅 going into this topic for advice on this matter.
> What would you advice yourself?) I remember you saying, apart from CsOdtDrvStr and MBIST, that you can relax secondary/tertiary timings to ease posting.


I am as it seems 
4067 runs 14-14-14 flat
But 3600 can not even run 13-13-13 flat . . .
Soo i'm down to 3200 with very failsafe settings to figure this out ~ just 6:10min per cycle is really bad 








I feel tRAS, tRC, and tWRRD where causing issues
Currently run tRAS*2 + tCCD_L (6)
Match tRRD_L with tRTP
Keep tFAW = tCCD_L * tRRD_S
and dropped both SD, DD's by 1 to make them even weaker and hide issues
Also tRDWR is +1 more than it has to be
Somehow tWRRD 3 didn't post at all , while math would put them at 9 and not 12 (it would be fine) well idk

Probably something with powering is wrong.
I am too frighten to put PARK back to /5 for these snowflakes
Run 1.64v so far, but usually 1.66v
Will have to see what it takes to bring back 13-13-13 @ 1.7v
As long as RTT_WR /2 doesn't run, i really don't want to drop PARK further. A0 snowflakes could smoke away
Powering is "ok" because 4067C14-14 1T works
But something prevents me 13 or 12 ,
Sharing because of tMOD 24 , tPDA 24, tPHYRDL 24

Also sharing because i used your tRFC 2 & 4 + 1 change
I should figure out today if they make "the key difference" or not
Kind of in the mood to get a flat C13 set , well actually C12 but i gave up on the Rev.E for now (tCWL 10 , tCL 13 runs, tCL12 not at all) ~i'm a failure lol~ 
Above are what "failsafe" means for me
Probably can increase tRDWR +1. But it's already failsafe enough 
EDIT:
* don't run 2067 FCLK as baseline, to prevent post-failure shenanigans. High FCLK low MCLK trick really seems to work out well now. It made big issues before 1.2.0.0. Ty @craxton


----------



## Audioboxer

Veii said:


> Check tRFC mini - TM5 error description
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> View attachment 2517510
> 
> Try to run 40-20-30-20 CAD_BUS
> 60-20-20-24 also is an option
> same as 30-20-30-20
> 
> He is also a teacher like me, but maintains the CH Chiphell forum
> We barely have any connection - only our results often jump sites
> 
> Our beta is strange, but it looks stable
> At least fallback functions on bad tCL (too well i think) but memory training is too short
> I think i have 1203A too - They should have gotten it mid April, but we have mid-july now. They are slow
> 
> 
> I am as it seems
> 4067 runs 14-14-14 flat
> But 3600 can not even run 13-13-13 flat . . .
> Soo i'm down to 3200 with very failsafe settings to figure this out ~ just 6:10min per cycle is really bad
> View attachment 2517511
> 
> I feel tRAS, tRC, and tWRRD where causing issues
> Currently run tRAS*2 + tCCD_L (6)
> Match tRRD_L with tRTP
> Keep tFAW = tCCD_L * tRRD_S
> and dropped both SD, DD's by 1 to make them even weaker and hide issues
> Also tRDWR is +1 more than it has to be
> Somehow tWRRD 3 didn't post at all , while math would put them at 9 and not 12 (it would be fine) well idk
> 
> Probably something with powering is wrong.
> I am too frighten to put PARK back to /5 for these snowflakes
> Run 1.64v so far, but usually 1.66v
> Will have to see what it takes to bring back 13-13-13 @ 1.7v
> As long as RTT_WR /2 doesn't run, i really don't want to drop PARK further. A0 snowflakes could smoke away
> Powering is "ok" because 4067C14-14 1T works
> But something prevents me 13 or 12 ,
> Sharing because of tMOD 24 , tPDA 24, tPHYRDL 24
> 
> Also sharing because i used your tRFC 2 & 4 + 1 change
> I should figure out today if they make "the key difference" or not
> Kind of in the mood to get a flat C13 set , well actually C12 but i gave up on the Rev.E for now (tCWL 10 , tCL 13 runs, tCL12 not at all) ~i'm a failure lol~
> Above are what "failsafe" means for me
> Probably can increase tRDWR +1. But it's already failsafe enough


Thanks, will do. Was just left on auto from earlier when we were doing some troubleshooting. Auto seems to default to 24-24-24-24.


----------



## Veii

Audioboxer said:


> Thanks, will do. Was just left on auto from earlier when we were doing some troubleshooting. Auto seems to default to 24-24-24-24.


24-20-24-24 works , same as 24-20-20-24 (matisse and older)
But GDM off, needs ClkDrvStr boost - and broken memory training needs CsOdtDrv bump. ~ when you bump ClkDrvStr, you can lower procODT by one. 
Stability needs to be tested with y-cruncher all tests (1-7-0) for 4 loops or over 50min

You can search if you have a 1.8v CPU voltage option and push it to 1.83 (preferred) or 1.85. Higher might cause issues with VDDG/VDDP voltages
Also fix Standy VDDP voltage to 0.9v or if possible, 0.86v
===================
Also new Aida64 update










https://download.aida64.com/aida64extreme_build_5741_d2s5ypwhqn.zip


----------



## XPEHOPE3

Veii said:


> Also sharing because i used your tRFC 2 & 4 + 1 change
> I should figure out today if they make "the key difference" or not


Dunno, from other people's screenshots, it seems one cat get away with whatever tRFC2, tRFC4 are set. And that's why I'm not sold on the idea that tMAC or anything at all gets secretly computed from tRFC2 or tRFC4


Veii said:


> Also new Aida64 update


They also say that metrics are not comparable between different Aida64 bench dll versions.


Veii said:


> 4067 runs 14-14-14 flat
> But 3600 can not even run 13-13-13 flat . . .


I'm no physicist and no electrician. But can't it be like this: powering is good for 4067-14, because load is high and there is _no excess_ of amperes/voltages, but then for 3600-13 with same powering load is still kinda high enough so that high amperes are produced, but not entirely consumed and have to go somewhere and break something; and then for 3200-13 there's too little load and no high amperes are produced, so no excess to break anything.


----------



## Audioboxer

Veii said:


> 24-20-24-24 works , same as 24-20-20-24 (matisse and older)
> But GDM off, needs ClkDrvStr boost - and broken memory training needs CsOdtDrv bump. ~ when you bump ClkDrvStr, you can lower procODT by one.
> Stability needs to be tested with y-cruncher all tests (1-7-0) for 4 loops or over 50min
> 
> You can search if you have a 1.8v CPU voltage option and push it to 1.83 (preferred) or 1.85. Higher might cause issues with VDDG/VDDP voltages
> Also fix Standy VDDP voltage to 0.9v or if possible, 0.86v
> ===================
> Also new Aida64 update
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> https://download.aida64.com/aida64extreme_build_5741_d2s5ypwhqn.zip












40/20/30/20 got me further, but 45 minutes in, error on 10, could it be as simple as needing to drop tWR?

Now that I've switched to 40/20/30/20 I guess I could also test 4/4 and 6/6 again on SD and DDs.


----------



## XPEHOPE3

Audioboxer said:


> 40/20/30/20 got me further, but 45 minutes in, error on 10, could it be as simple as needing to drop tWR?


Altough playing around gives experience, I believe you'd be much better off starting from definitely stable baseline and changing settings 1 group at a time


----------



## sendap

@Audioboxer

maybe my settings help out a bit? Very similar to yours and stable for weeks now...



Spoiler: 3800C15


----------



## Audioboxer

XPEHOPE3 said:


> Altough playing around gives experience, I believe you'd be much better off starting from definitely stable baseline and changing settings 1 group at a time


I've got a few CL16 stable profiles, some with super tight timings. My headache has been GDM off and even knowing a baseline to start from. I tried to just pull in the DRAM calculator values for CL16 which will pass fine (GDM on) but even they seem to be causing issues.

It's knowing whether it's timings or resistances right now that is driving me mad lol.



sendap said:


> @Audioboxer
> 
> maybe my settings help out a bit? Very similar to yours and stable for weeks now...
> 
> 
> 
> Spoiler: 3800C15
> 
> 
> 
> 
> View attachment 2517521


Unfortunately I cannot boot RttPark 3 at all. Not sure if it's cause of Patch A of this bios version or something else as I've never tried booting RttPark 3 before. I'll try copy some of your timings anyway, but I'll have to boot at 6/3/1 or disabled/3/1.


----------



## Veii

@XPEHOPE3
This will be interesting for you








tPHYRDL seems to scale normally by MCLK
Same for tSTAG and tMRD
All looks very natural to me, and nothing that is "by boot" changing
Now only tRFC 2/4 +1 or old way, needs to be tested

It shows me also, that 3800 13-13-13 can not post
All of them are fine till 1.63v, but i'll test now 3733 longer

Main boot failure issue was tWRRD or SD,DD's
1T needs to be "tested" now and how much voltage increase really is needed (if anything)

EDIT:
Oh make that "fine till 3666", 3733 Error #6 fully, soo lack of voltage ~ which was expected fully with only 1.63v instead of 1.66v

It also shows me that it really is every 3 steps for "perfect scaling" instead only "every 100MCLK" = +1 tCL, +1 tRCD
We'll see what is required for 3800C13-13 to run. My casual rule was making it run , considering 4067 C14-14 is fine, soo 4200 C15-15 is rock solid (possibly 4233 should still run)
More updates later with rock solid results. Seems like 3600C12-12 can not work, unless i get the powering on 3800C13-13 correct & runnable ~ seems to need slightly more umpf 


Audioboxer said:


> but 45 minutes in, error on 10, could it be as simple as needing to drop tWR?


It's tRFC desync or low SCL
Will without doing anything SCL 5-5 be fine ?
Try this








My Sheet doesn't support Dual Rank 16Gb dimms
They are slightly different
















Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com




I don't want to call other Engineers research mine and steal code. When i figure a better method out, i'll fix it for Dual Rank 
Bottom sheet by Chitos, is a community project anyways~


----------



## XPEHOPE3

Audioboxer said:


> I've got a few CL16 stable profiles, some with super tight timings. My headache has been GDM off and even knowing a baseline to start from. I tried to just pull in the DRAM calculator values for CL16 which will pass fine (GDM on)


DRAM calculator is for Matisse and mostly irrelevant. To GDM off one has to use 2T at first as it doesn't require anything basically. For my 4*16GB DR I started from 3800-16-16-16-16 VDIMM 1.45, GDM off, CR 2T, _everything else about RAM on Auto_. PBO disabled, PBO scalar Manual, Scalar 1x, SVM disabled.


----------



## Audioboxer

XPEHOPE3 said:


> DRAM calculator is for Matisse and mostly irrelevant. To GDM off one has to use 2T at first as it doesn't require anything basically. For my 4*16GB DR I started from 3800-16-16-16-16 VDIMM 1.45, GDM off, CR 2T, _everything else about RAM on Auto_. PBO disabled, PBO scalar Manual, Scalar 1x, SVM disabled.
> 
> View attachment 2517523


Thanks, good point, I never thought about just putting most on auto and rolling with it. I'll do that tonight and run something for like 7~8 hours because just now I feel like I'm throwing darts at a dartboard blind and just hoping something sticks.

@Veii I have that "1.8v CPU voltage option", is it something that I should be putting to 1.83v just now or just leave it auto until I get a stable base?


----------



## XPEHOPE3

Veii said:


> tPHYRDL seems to scale normally by MCLK
> Same for tSTAG and tMRD


never tracked that tPHYRDL dependence on frequency alone since I only discovered tPHYRDL influence when I already hit my ceiling of 3866. So I only saw it change from timings, voltages, resistance changes. But it's interesting, you are right)
However I see I guess misuse of the wording "scale normally": tPHYRDL is stuck on 26 (at least for A1, hope you checked A2 too), as well as tMRD at 8, however tSTAG actually scales with frequency linearly. Can you elaborate on what you meant by "scale normally" here?


----------



## mongoled

Audioboxer said:


> Thanks, good point, I never thought about just putting most on auto and rolling with it. I'll do that tonight and run something for like 7~8 hours because just now I feel like I'm throwing darts at a dartboard blind and just hoping something sticks.
> 
> @Veii I have that "1.8v CPU voltage option", is it something that I should be putting to 1.83v just now or just leave it auto until I get a stable base?


Set it now

Don't give up , we just need to figure out a few things.

What is the vDIMM?

Set tRDWR to 11


----------



## Audioboxer

mongoled said:


> Set it now
> 
> Don't give up , we just need to figure out a few things.
> 
> What is the vDIMM?


Been running with 1.5v. I'm actively cooled so not worried about temps. Never go above 40. Mostly 36-38 under load.

Not gonna give up but might just auto everything as above and get a clean base with GDM off lol.

Wondering if because I can't get RttPark 3 to boot that is causing me difficulties compared to other DR kits on 6/3/3. Should I be trying Nom on 6 so it's 6/3/1 or is that not a good idea?


----------



## mongoled

Audioboxer said:


> Been running with 1.5v. I'm actively cooled so not worried about temps. Never go above 40. Mostly 36-38 under load.
> 
> Not gonna give up but might just auto everything as above and get a clean base with GDM off lol.


Is there a particular reason you are using a ProcODT of 43 ohms?


----------



## Audioboxer

mongoled said:


> Is there a particular reason you are using a ProcODT of 43 ohms?


That's just running on auto from when I auto'd quite a few of those settings earlier.

If anyone else is running DR right now with RttPark 3 can you reply to me and let me know if you're on AGESA V2 PI 1.2.0.3 Patch A? Or were on it before upgrading to Patch B.

Just out of interest to know if this not posting could be a patch A thing. Asus tend to be a bit slow putting out the newest BIOS for this board.


----------



## Veii

XPEHOPE3 said:


> never tracked that tPHYRDL dependence on frequency alone since I only discovered tPHYRDL influence when I already hit my ceiling of 3866. So I only saw it change from timings, voltages, resistance changes. But it's interesting, you are right)
> However I see I guess misuse of the wording "scale normally": tPHYRDL is stuck on 26 (at least for A1, hope you checked A2 too), as well as tMRD at 8, however tSTAG actually scales with frequency linearly. Can you elaborate on what you meant by "scale normally" here?


It changes step by step, it changes "normally" ~ the board knows what to do
It doesn't randomly jump and changes naturally on MCLK step by step increases

I have a dual dimm daisy-chain / fly-by layout
It's not a 4 dimm where 1 & 3 get first the Daisy Chain current which then hits the 2 & 4 "main one" as ceiling/wall
Soo if only 1 & 3 would be used, the signal might reflect back (RTT) & one of the reasons why missplacing dimms on DaisyChain can make issues

A1 / B1 for me (no change, every dimm has their own channel ~ for misprediction something else is to blame)
I saw right now error #10 by missplaced tRFC 2 , while tRFC 4 was correct (accident)
Fixed it to "my" method and it survived one loop but later was crashing on #7 and then back to the #1 explosion
But #6 issue is gone with +10mV








#7 pretty much indicates that my powering is too weak together with the #1 explosion
But there where differences and your +1 on tRFC 2/4 because of up rounding didn't work and made things worse. The time-window was too small and only on the edge of voltage stability (1.65v now)
Soo for the bigger picture, it makes close to zero difference - when powering is correct. (but if one is mistyped and the other correct, it does make a difference)
I'll keep exploring when it makes sense and change rounding method, if it only leads to positive changes. I'm stubborn  but till it doesn't show a benefit, i'll stay to the old method.
If it shows no negative issue, i might not care and listen ~ but currently it's experimental , soo i can not change a functional sheet which so far always works


----------



## mongoled

Audioboxer said:


> That's just running on auto from when I auto'd quite a few of those settings earlier.


When you are able to and if you are willing can you also set ProcODT to 36.9 ohms and see if it posts. 

If it does, set RttPark to RZQ/2, hopefully it posts 😊


----------



## Audioboxer

mongoled said:


> When you are able to and if you are willing can you also set ProcODT to 36.9 ohms and see if it posts.
> 
> If it does, set RttPark to RZQ/2, hopefully it posts 😊


Yeah I will do. I'm 15 minutes into trying a test with voltages auto apart from VDDP at 0.9v, CPU 1.8v at 1.83v and RttNom at 6.

For visibility on this page, I asked on the last page if anyone else has DR did you have RttPark booting at 3 on bios AGESA V2 PI 1.2.0.3 Patch A? Patch B isn't here for my board yet, hopefully within the next week.


----------



## XPEHOPE3

XPEHOPE3 said:


> DRAM calculator is for Matisse and mostly irrelevant. To GDM off one has to use 2T at first as it doesn't require anything basically. For my 4*16GB DR I started from 3800-16-16-16-16 VDIMM 1.45, GDM off, CR 2T, _everything else about RAM on Auto_. PBO disabled, PBO scalar Manual, Scalar 1x, SVM disabled.
> 
> View attachment 2517523


Oh forgot I also set VSOC and VDDG* voltages @Audioboxer


----------



## Audioboxer

XPEHOPE3 said:


> Oh forgot I also set VSOC and VDDG* voltages @Audioboxer


Yeah I'll probably do that too, auto puts mine quite close to where I'd likely run them anyway.

@mongoled 36.9 posts fine, but again, RttPark will not post on 2 or 3, only 1. As soon as I see Patch B bios is out for this board I'll give it a go.

My one last throw everything at the wall failed after 25 minutes as well lol










Instead of "wasting" more time I'm going to auto most timings out tonight and run 16-16-16-16 GDM off 2T overnight and make sure its fine. Then I'll get some advice on what timings to work on first and start from scratch.


----------



## Sphex_

Sphex_ said:


> Well, I've given up on 1900+ MHz FCLK, the WHEAs are inescapable. So instead I've turned my attention towards trying to gain performance (mainly latency) by lowering my timings at MCLK 3800 MHz. But this is proving to be challenging...
> 
> *Memory Kit:* F4-4266C19-8GTZ (2x8GB Samsung B-Die, Single Rank)
> *Motherboard:* MSI B550 Gaming Carbon Wifi
> *BIOS / AGESA:* 1.72 (1.2.0.3b SMU 56.53.0)
> *Goal:* Lower latency / better performance through lower timings at 3800 MHz Memory Clock
> *Current Stable Settings:*
> View attachment 2517321
> 
> *Issue: *I'm attempting to use the above settings, but tighten the primary timings and the subtimings that rely off of those (like tCWL, tRP, tRTP, tWR, etc.) The main difference here is that I'm setting the VDIMM to 1.5V as opposed to 1.4V. This is the highest voltage I'm willing to set, and at this voltage, the DIMMs don't seem to exceed 43°C in my case, which is good but not great.
> 
> Right off the bat, my computer won't even POST if I set tCL to 15 (1T, GDM off). It just does not like that value, I do not know if this is a BIOS issue or not. However, it *does* POST with tCL set to 14. Unfortunately no combination of lower primary timings (and the subtimings that rely off of those, as explained many times by Veii) seems to work. 14-14-14-14 and 14-15-15-15 do not pass memory tests (Tests 2,6,10,12 1usmus_v3 preset). The computer will POST, Windows will boot, but errors will be thrown within the first minute or so when running TM5. I've tried loosening tRFC from RC*6 to RC*8, I've tried loosening RCDRD slightly, I've tried raising the vSOC, different ProcODT, different resistances, all to no avail.
> 
> It's kind of wild this kit cannot do tighter timings than 3800 CL16 but I'm grasping at straws at this point. Any help or pointers would be appreciated!


Any advice for getting my computer to even POST at CL15? CL14 POSTs but setting tCL to 15 causes issues. Totally confusing. More info above^


----------



## Veii

Audioboxer said:


> Instead of "wasting" more time I'm going to auto most timings out tonight and run 16-16-16-16 GDM off 2T overnight and make sure its fine. Then I'll get some advice on what timings to work on first and start from scratch.


tWR s too low here, should be 14 (half of tRTP, where tRTP is the multiplier you use for tRFC)
But #6 says it's a voltage issue

I mentioned to try SCL 5 too
But generally all ends up to lack of voltage or bad resistance
RTT_NOM /6 only is required once you exceed 1.48v, well you can be fine with /7 till around 1.54-1.55v
But it will need support to lower RTT_PARK
Even more when you / we have no idea what PCB these things are on
If they are on A0/B0 , then it's dangerous to exceed 1.51v , 1.52v at best
1.54v can result in a lost memory channel and 1.56v could kill these instantly. * Really depends what you own
* without changes to RTT

After long testing or long PC usage without dusting, it might be a good idea to re'seat both rams
Also after many high voltage sessions, because the contacts start to corrode by heat & high current
Simple re'plugging, already does clean them, but i have to mention it for dusty scenarios

EDIT:
I want to also re'mention again to run tRRD_ and tWTR slower
There is no reason why you should prevent yourself from low primaries, by straining the PCB that much
tRRD_ 5-7-30 (tFAW 30)
tWTR 5-14
~ this will lower VDIMM requirements 

You will need to check ASUS SPD-Z tool, to figure out what tCCD_L your kits run
Also mentioned this , but you didn't listen
Please check and figure this value out ~ ASUS Bios Category "Tool"
Then use this value for tFAW. Which is tRRD_S * tCCD_L = tFAW

If you continue to fail, there are more failsafe options - but start to do changes please
#6 pretty much says "i need more current"
How you deliver this, by high ClkDrvStr , or different way - is up to you (us , when you listen)
But to prevent you from killing your dimms (who knows what PCB these are on) - better weaken RTT's
Often there is no way around going beyond 1.5v. But voltage does not mean anything. Current that arrives depends on the Resistance and Powering setup
(CAD_BUS, RTT, ProcODT, and Voltage ~ google how Ohm's law functions. Amperage is what makes heat and titled as "current". Not VDIMM, VDIMM doesn't matter, just a value)


----------



## Audioboxer

I'd be shocked if these auto settings don't pass 😂

If and when they do, where on earth does one start? Resistances and trying to get 15-15-15-15 passing first?


----------



## PJVol

Sphex_ said:


> Any advice


I may have not as high binned chips as yours but think they're in the same ballpark.
Anyway, you can try to boot with these timings (24/7 set):










There may be some issues with MBIST. For example my pc might not boot right after changing CL15 to 16 in this preset, but will do after power cycle.

PS: One important thing.
There's no way to boot with [email protected] with tRDWR 8.


----------



## Audioboxer

Veii said:


> tWR s too low here, should be 14 (half of tRTP, where tRTP is the multiplier you use for tRFC)
> But #6 says it's a voltage issue
> 
> I mentioned to try SCL 5 too
> But generally all ends up to lack of voltage or bad resistance
> RTT_NOM /6 only is required once you exceed 1.48v, well you can be fine with /7 till around 1.54-1.55v
> But it will need support to lower RTT_PARK
> Even more when you / we have no idea what PCB these things are on
> If they are on A0/B0 , then it's dangerous to exceed 1.51v , 1.52v at best
> 1.54v can result in a lost memory channel and 1.56v could kill these instantly. Really depends what you own
> 
> After long testing or long PC usage without dusting, it might be a good idea to reset both rams
> Also after many high voltage sessions, because the contacts start to corrode by heat high current
> Simple re'plugging, already does clean them, but i have to mention it for dusty scenarios


I've resorted to AUTOing my settings as above and running a 20 cycle.

How do I find out what PCB I have? Take out and remove heatsinks?










This is TB but I've heard its unreliable.


----------



## Veii

Sphex_ said:


> Any advice for getting my computer to even POST at CL15? CL14 POSTs but setting tCL to 15 causes issues. Totally confusing. More info above^


You likely tried to run tCL 15 with tCWL 16
tCWL can / should not exceed tCL. It didn't work and still doesn't work on AMD
Give tCWL 14 a try, but increase tRDWR by +2

that will post very likely
tFAW is 6 times ?
Is tCCD_L for you 6 ~ are you sure it's not a 7 ?
Bioses have a memory-z or SPD-Z tool to check & read out XMP profiles + generate tCCD_L . They use it for XMP timing prediction

276 tRFC runs as / 8 well, but doesn't as /7
soo tWR 14 is purely wrong, should be tWR 16
Possibly runnable as tWR 12, but tRTP needs to be 6 then too ~ except exceptions
tWR 14 anyways is wrong, however i shuffle it around 
It shouldn't prevent you to post, but it will error out if you keep it that way

Give tWRRD a bit latency, to 3 for example
tWRRD = X * SCL = equal or lower than tRCD , not higher
Soo 4 (SCL) * 3 (value) = 12, this works 

Or increase SCL to 5 & 5*3= 15, it works too
The rest is fine, just tCWL makes issues for you & maybe the lack of tWRRD can make issues
SD;DD's are tight, they only will be stable if everything is perfect
If you have issues, lower them to 1-4-4-1-6-6 . This will pass but cut away a bit of perf


Audioboxer said:


> How do I find out what PCB I have? Take out and remove heatsinks?











OC'ing T-Force 4133 cl18


I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...




www.overclock.net




Removing heatsinks is dangerous & not needed (thermal epoxy)
As these are dual sided - dual rank
We don't know what the main side is
Take them out and make centered Trace pictures of them
and one from the side, to check the height of the IC's (helps figure out if it's A0 or A1/A2)

The community here has shematics of A0,A1,A2 PCBs
Thaiphoon burner sadly lies on this part
Could be B1 but could also be a custom PCB
A = single rank
B = dual rank (both sided)
At least most of the times the layers are correct
Soo 8 layers is not bad at all 








Funnily tRRD_S is higher than tRRD_L on them.
Doesn't work scaling wise for me yet


PJVol said:


> There may be some issues with MBIST. For example my pc might not boot right after changing CL15 to 16 in this preset, but will do after power cycle.


There is, but nothing we can do 
Have the same

My dimms are really bellow the average on binning
it's an excuse 🤭
It's a lower binning than 3200 C14-14-14 
And even a worse PCB than most FlareX kits.
IC's are ok, but close to everyone here has better b-dies 
Less complaining, more powering finetuning ~ then it works with high voltage


----------



## Audioboxer

Veii said:


> You likely tried to run tCL 15 with tCWL 16
> tCWL can / should not exceed tCL. It didn't work and still doesn't work on AMD
> Give tCWL 14 a try, but increase tRDWR by +2
> 
> that will post very likely
> tFAW is 6 times ?
> Is tCCD_L for you 6 ~ are you sure it's not a 7 ?
> Bioses have a memory-z or SPD-Z tool to check & read out XMP profiles + generate tCCD_L . They use it for XMP timing prediction
> 
> 276 tRFC runs as / 8 well, but doesn't as /7
> soo tWR 14 is purely wrong, should be tWR 16
> Possibly runnable as tWR 12, but tRTP needs to be 6 then too ~ except exceptions
> tWR 14 anyways is wrong, however i shuffle it around
> It shouldn't prevent you to post, but it will error out if you keep it that way
> 
> Give tWRRD a bit latency, to 3 for example
> tWRRD = X * SCL = equal or lower than tRCD , not higher
> Soo 4 (SCL) * 3 (value) = 12, this works
> 
> Or increase SCL to 5 & 5*3= 15, it works too
> The rest is fine, just tCWL makes issues for you & maybe the lack of tWRRD can make issues
> SD;DD's are tight, they only will be stable if everything is perfect
> If you have issues, lower them to 1-4-4-1-6-6 . This will pass but cut away a bit of perf
> 
> 
> 
> 
> 
> 
> 
> 
> 
> OC'ing T-Force 4133 cl18
> 
> 
> I built my first real PC just a couple months ago. I've recently been trying to get the most out of the system... both just for ****s and for some extra performance. My current build is PCPartPicker Part List CPU: AMD Ryzen 5 3600 3.6 GHz 6-Core Processor ($174.15 @ Walmart) CPU Cooler...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> Removing heatsinks is dangerous & not needed (thermal epoxy)
> As these are dual sided - dual rank
> We don't know what the main side is
> Take them out and make centered Trace pictures of them
> and one from the side, to check the height of the IC's (helps figure out if it's A0 or A1/A2)
> 
> The community here has shematics of A0,A1,A2 PCBs
> Thaiphoon burner sadly lies on this part
> Could be B1 but could also be a custom PCB
> A = single rank
> B = dual rank (both sided)
> At least most of the times the layers are correct
> Soo 8 layers is not bad at all
> 
> 
> 
> 
> 
> 
> 
> 
> Funnily tRRD_S is higher than tRRD_L on them.
> Doesn't work scaling wise for me yet
> 
> There is, but nothing we can do
> Have the same
> 
> My dimms are really bellow the average on binning
> it's an excuse 🤭


Thanks, I'll get some pictures and also get the tCCD_L value for the community as well as soon as this testing it done. 1 hour in.


----------



## Audioboxer

@Veii I believe 6 is what you were after?










Also










LOL

I went away from the PC for a bit, so I think the error has came about 1 hour 20 in or something. Hoping it's just because my AUTO settings are a bit messy and not something else.

Going to try and more closely match settings from here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## Veii

Audioboxer said:


> @mongoled 36.9 posts fine, but again, RttPark will not post on 2 or 3, only 1. As soon as I see Patch B bios is out for this board I'll give it a go.


You can also give ClkDrvStr 60 a try 
But be aware #4 errors are PCB crashes
#13 usually too but these are rather overvoltage issues

36.9Ω should allow it to run
Soo something else bothers
even 40Ω is better than 43.6 ~ but 40 will work, soo something else bothers



Audioboxer said:


> @Veii I believe 6 is what you were after?


Yes ~ soo tRRD_S * 6 = tFAW
I see SOC loadline is too droopy, but that's fine
What isn't fine, is the set SOC
Between IOD and SOC is less than 40mV gap 
It needs as absolute minimum to be 40mV for this generation
Soo either increase switching frequency (rather not) or just put a bit more SOC on it 








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net


----------



## Ethelneth

craxton said:


> do yourself a favor,
> right click your TM5 exe and click,
> properties, compatibility, "change settings for all users",
> then select run this program as administrator.
> TM5 is screaming at ya as is about it lol...if you dont do it this way,
> then you can right click and hit run as admin manually "everytime" you
> launch TM5.


I did myself the favor and re run it elevated. What is the difference apart from using 3,8GBx16 vs 758MBx82? Can you elaborate about the drawbacks of running unelevated compatibility mode?


----------



## sendap

Veii said:


> And even a worse PCB than most FlareX kits.


I do have a FlareX Kit. What PCB is most likely used for that kit?


----------



## Audioboxer

Veii said:


> You can also give ClkDrvStr 60 a try
> But be aware #4 errors are PCB crashes
> #13 usually too but these are rather overvoltage issues
> 
> 36.9Ω should allow it to run
> Soo something else bothers
> even 40Ω is better than 43.6 ~ but 40 will work, soo something else bothers
> 
> 
> Yes ~ soo tRRD_S * 6 = tFAW
> I see SOC loadline is too droopy, but that's fine
> What isn't fine, is the set SOC
> Between IOD and SOC is less than 40mV gap
> It needs as absolute minimum to be 40mV for this generation
> Soo either increase switching frequency (rather not) or just put a bit more SOC on it
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net


Bumped the VSOC and I'll leave PC running on another test. Tomorrow I'll get some pics of my memory.

Thanks again for help today hope to have a stable base from tomorrow to work with.


----------



## Sphex_

PJVol said:


> I may have not as high binned chips as yours but think they're in the same ballpark.
> Anyway, you can try to boot with these timings (24/7 set):
> 
> View attachment 2517537
> 
> 
> There may be some issues with MBIST. For example my pc might not boot right after changing CL15 to 16 in this preset, but will do after power cycle.
> 
> PS: One important thing.
> There's no way to boot with [email protected] with tRDWR 8.


Had no idea RDWR effected what tCL is set to and vice versa. There's so much different information all over the internet, I have all of these different formulas for determining what each timing should be but I have no idea which one is correct. 

And thanks for posting those timings. They certainly look doable, I'll try to get them working tonight!


Veii said:


> You likely tried to run tCL 15 with tCWL 16
> tCWL can / should not exceed tCL. It didn't work and still doesn't work on AMD
> Give tCWL 14 a try, but increase tRDWR by +2
> 
> that will post very likely
> tFAW is 6 times ?
> Is tCCD_L for you 6 ~ are you sure it's not a 7 ?
> Bioses have a memory-z or SPD-Z tool to check & read out XMP profiles + generate tCCD_L . They use it for XMP timing prediction
> 
> 276 tRFC runs as / 8 well, but doesn't as /7
> soo tWR 14 is purely wrong, should be tWR 16
> Possibly runnable as tWR 12, but tRTP needs to be 6 then too ~ except exceptions
> tWR 14 anyways is wrong, however i shuffle it around
> It shouldn't prevent you to post, but it will error out if you keep it that way
> 
> Give tWRRD a bit latency, to 3 for example
> tWRRD = X * SCL = equal or lower than tRCD , not higher
> Soo 4 (SCL) * 3 (value) = 12, this works
> 
> Or increase SCL to 5 & 5*3= 15, it works too
> The rest is fine, just tCWL makes issues for you & maybe the lack of tWRRD can make issues
> SD;DD's are tight, they only will be stable if everything is perfect
> If you have issues, lower them to 1-4-4-1-6-6 . This will pass but cut away a bit of perf


I made the changes you suggested:

tCL 16 -> 15
tCWL 16 -> 14
tRDWR 8 -> 10
tWR 14 -> 16
tWRRD 1 --> 3









Oh, and my tCCD_L is 6, according to the Memory-Z tool in the BIOS.

These changes allowed my computer to POST and Boot to Windows! But I do have some questions about your suggestions for the other timings:

You questioned how I arrived at a tFAW of 24. Isn't the formula tFAW = RRDS*4 *or **6?
Isn't the formula for tWR = RAS-RCD?
Doesn't tRTP have to be a clean divider of RFC? and RFC is tRC *6 or *8?
How is tRWRD effected by tCL?
As I said to PJVol above, I have all of these different formulas written down in a notebook but I don't know which ones are correct and which ones aren't. This is leading to me setting values like tRDWR incorrectly and causing POST issues and what not


----------



## XPEHOPE3

Audioboxer said:


> I went away from the PC for a bit, so I think the error has came about 1 hour 20 in or something.


Yeah, I also ran other voltages, as I said, and those used 40mV spacing as per Veii's advice. Note that whatever you see in ZenTimings is effectively applied voltage, not the one set in BIOS (slightly higher). E.g. if you set VDDP to 900mV in BIOS you'll see what you see in your screenshot (0.8973V). To see VDDP 0.9002V in ZenTimings one needs to set VDDP to 902mV in BIOS.
However I believe that those voltages depend not only on RAM settings but also on motherboard peculiarities (that is, one can't necessarily copy those from other user even if both users have the same AGESAs and SMUs)


----------



## XPEHOPE3

Sphex_ said:


> Had no idea RDWR effected what tCL is set to and vice versa.


It's easy to notice: if you set tRDWR to auto and start fiddling with tCL/tCWL, you'll see tRDWR changing. For tCL/tCWL 16/16 -> 16/14 I get tRDWR +2. For 16/14->15/14 I get tRDWR +1.
Meaning that formula used in Ryzen Google Calculator is incorrect (it divides tCL-tCWL difference by 2).


----------



## Veii

sendap said:


> I do have a FlareX Kit. What PCB is most likely used for that kit?


It nearly always is A1
They sometimes even put A2 on it as lucky win - but nobody at G.Skill headquarters cared. Tho not only G.Skill is to blame
3200C14-14 is a low "good b-die" binning. Every "good b-die" will run this.
I had a kit which could do 3800C14 flat on Zen 1 Threadripper, and one lemon which didn't even pass 3400 C14 flat (tho at this time i was an amateuer memOCer)
The "new" flareX seem to be A0 some of them ~ while some according to Intel OCer seem to have a quite great batch of b-dies.

But because of such PCB luck, i don't even want 3600 kits anymore
4000+ to at least have some guarantee that the PCB can do 4000
Although at this point of time, i don't mind
Can work with every lemon  Just look for new toys to gather experience. Was looking for A3 :/



Sphex_ said:


> You questioned how I arrived at a tFAW of 24. Isn't the formula tFAW = RRDS*4 *or **6?


Now it's both
SubUrgent and Urgent Burst refresh
It changed behaviour since the new FW on SMU 56.46+ (well AGESA 1.2.0.0 and pre 1.1.9.1)


Sphex_ said:


> Isn't the formula for tWR = RAS-RCD?


It has too many formula's , yet there is not "one correct" method of designing your timings chain








Usually has to be tRRD_S + tWTR_S as minimum value
But it works different too
Pretty much matching it for tRFC makes more sense i feel. And makes things easier
tRTP is the multiplier , tWR is something that is less than 3 decimals inside tRFC value (both tRTP and tWR)
and tRRD_L can be also equal to tRTP

Many methods. Think outside of the box when you know what to do
Else follow the rules till you know how to debug stability.
New research and tricks are always welcome. Don't blindly follow JEDEC textbook. There are too many iterations of it, and every new revision designer, trows away old research and starts from scrattch
Do so yourself too, ignore the book and try to figure out new better ways


Sphex_ said:


> Doesn't tRTP have to be a clean divider of RFC? and RFC is tRC *6 or *8?


You do math in ns, not in virtual values
Perfect clean divider is better, but often more than 1 value works as clean divider
.5 and .25 values work too, just won't work for 1x BURST refresh type of operation (1 x tFAW trick for example)


Sphex_ said:


> How is tRWRD effected by tCL?


I don't know. Non ?
tRCD_RD is
tCWL goes the same amount down as tRDWR goes the same amount up. -2 tCWL = +2 tCWL


XPEHOPE3 said:


> To see VDDP 0.9002V in ZenTimings one needs to set VDDP to 902mV in BIOS.


Every voltage is SET except SOC - which is GET voltage
Don't try to match them +1 mV, you can not
VDDG is dynamic and cLDO_VDDP also
Changing VDDG IOD changes CCD , and the opposite. They balance themself
Only SOC can be set higher because GET value matters (it has loadlines after all)
cLDO_VDDP and VDDG are not influenced by loadlines


Sphex_ said:


> Oh, and my tCCD_L is 6, according to the Memory-Z tool in the BIOS.


Wasting latency on tRC hides potential misstimmed timings.
Keep it tRAS+tRP 
It's only used for stability sake, but the whole set waits till tRC elapses before it continues. Soo pushing it higher , does slow everything down and will hide timing missmatches
Only Micron IC's are awkward for some reason there
Samsung ICs can run it. Clean transition tRP+tRAS = tRC


----------



## JellyFish3D

Heya

This is what I've managed so far.

















The setup seems to be finally stable as I've been trying to lower DRAM voltage, currently it is set to 1.52 V in BIOS and is reported as 1.536 V in HWiNFO. Although I think there is something weird going on with my L3 Cache and I have no idea what it is, it's all over the place. I have copycatted a little from similar 4000c15 setup on Zen RAM OC from "Loudzy" sheet mainly some of the drive strengths and RttNom which have allowed me to drop DRAM voltage from 1.53 in BIOS which gets reported as 1.552 in HWiNFO to current 1.52. According to HWiNFO the voltage steps are weird on my motherboard as they overshoot by up to 0.02V so this -1 step in voltage helped out quite a bit with reducing heat. Currently there is a fan on top of both RAM sticks and the temps seem fine (to the touch, no temp sensor on these Viper bad boys sadly) so far but I intend to daily this setup and therefore want to check that I don't do anything crazy with Rtt's and my current voltage as I don't have much experience configuring them, any tips on figuring those out together with drive strengths? Even if there is nothing wrong with current setup it would be nice to know how to work out Rtt's and drive strengths for future overclocks.

Just before previous setup I've been trying out tCKE and setup times but they seem to do no difference for my current setup, perhaps I didn't even needed them to begin with. But still, these timings survive overnight.









The memory kit is PVS416G413C9K


Spoiler: Taiphoon














The PCB layout is indeed A0 as Taiphoon reports it


Spoiler: Viper Steel 4133C19


----------



## Veii

Alright, finally some results 👨‍🎓
It's on the edge of "just fine"
1.65v, 1.67 already gives overcurrent issues
and SD , DD 1-4-4-1-6-6 or slower cause #2 errors (sync issues)
Same goes for tRDWR as 9 , no possibility ~ instantly complains by overlapping timings
This is as tight as it get's (tRDWR 6 + 2) ~ well not that anything more lose allowed to function when primaries are that low, heh
EDIT: Actually a 7 might even run, but i can not see any voltage headroom left 








1T is for another day, and 3733 is still in works
It requires these 1.68v but either lacks powering or overcurrent crashes by using 120ohm ClkDrvStr
RTT_PARK Disabled still keeps it suffering on Overvoltage #13

RTT_WR /2 needs to finally run on this PCB - then i have a bit more voltage playroom
Pretty sure 3800 will require at least 1.72v lol
No way going even slightly higher than 1.66v right now 
At least amateur me fixed their set's, ~ now all belongs to voltage taming and preventing PCB crashes 
(soo tCKE and powerdown trickery it is)


----------



## LePr3

Any tips to get this running 1t? This is Veii's set from way back. I've already got 2t stable.
1t will only 'boot' to the bios with ProcODT 34, RttWr/1, Park/6, ClkDrvStr 120 but will quickly restart the computer automatically within 6 secs. The setup timings I've seen posted around 3-3-15 don't post, and fake 1t 56-56-56 doesn't seem to work with Matisse. 53-53-53 is the closest I can get but will error in TMR #3 & #4 errors after 20mins. I do change tRDWR to 9 when trying for 1t 'cause dual rank.
3950x with dual rank B-die 1.565v.


----------



## byDenoso

What timings should i tigher to have better 1% and 0,1%Lows in games?
I have a R5 3600 paired with Vega 56 with 2x8 hynix DJR [email protected] Ram









My timings (TM5 20cycles stable so far)


----------



## craxton

Veii said:


> But because of such PCB luck, i don't even want 3600 kits anymore
> 4000+ to at least have some guarantee that the PCB can do 4000
> Although at this point of time, i don't mind
> Can work with every lemon  Just look for new toys to gather experience. Was looking for A3 :/


So you disagree with "buildzoid"
as in this video ( 16:19 ) shows some 3600c14 bin that he sounds like he "adores"
this kit. (yes its for a 5950x use case, but none the less) 
at the price point however i too would sway from getting this kit. but then again,





Ethelneth said:


> Can you elaborate about the drawbacks of running unelevated compatibility mode?


no, unfortunately i can not. 
but im sure someone here can granted the question is seen.
its best to use 1usmusv3 config as the "errors" have been broken down 
for the most part by the other person above in whom i quoted (unsure if he had help?)
but none the less, when you get an error youll be able to know what that error is
by using this page (scroll down some youll see it)

im not as well versed in why TM5 needs admin rights, 
really why any application needs such privileges honestly. 
i have an "idea" why TM5 might need admin privs, but i dont wanna speak 
and not be anywhere near accurate with "what i think" vs why it actually needs 
privs.


----------



## Veii

craxton said:


> So you disagree with "buildzoid"
> as in this video ( 16:19 ) shows some 3600c14 bin that he sounds like he "adores"
> this kit. (yes its for a 5950x use case, but none the less)
> at the price point however i too would sway from getting this kit. but then again,


The price is identical to a 4000 C16-16-16 kit
150bucks for 16gb b-die , about right ~ often retails for 280€-310€

But i think he speaks more mainstream
for the voltage , it's a low XMP binning
And likely a stretched binning , stretched bad stock

I need to watch the whole video, if this is a typical "buyers will be happy" guide
Then it's fine. Depends on the userbase level.
He often mentions "casuals need to go away from his channel" , but also gets a lot of views from "casuals"
I can't judge him on this , he knows his stuff and is funny to talk with 
I do not have anything even slightly bad against him. We just likely experienced two different realities ~ things he recommends, i don't. (mainboards including)
Exotic behaviour i do, his community is literally on war against me
But we together, i think are fine. Can not disagree with him without knowing the targeted userbase, just not the type of roulette i want to roll with ~ and rather go directly 4000+ for the same price
Tho to his credit, we both went the cheap path with the vipers at the same time. He with a 4400 set, i with a 4000 set while they where 80-120$ and nobody knew or used them.
Both love them ~ soo likely share the same mindset, yet no idea what the target audience for this buyers guide was 

EDIT:
I remember, he went with the same biostar i wanted to get 🤭
We really aren't that different, but yes ~ just different experienced realities & slightly different music taste


----------



## byDenoso

LePr3 said:


> Any tips to get this running 1t? This is Veii's set from way back. I've already got 2t stable.
> 1t will only 'boot' to the bios with ProcODT 34, RttWr/1, Park/6, ClkDrvStr 120 but will quickly restart the computer automatically within 6 secs. The setup timings I've seen posted around 3-3-15 don't post, and fake 1t 56-56-56 doesn't seem to work with Matisse. 53-53-53 is the closest I can get but will error in TMR #3 & #4 errors after 20mins. I do change tRDWR to 9 when trying for 1t 'cause dual rank.
> 3950x with dual rank B-die 1.565v.
> 
> View attachment 2517564


try to loosen TRR_ to 6-9 and TWTRLto 5-14
its too tight,
And ckedrvstr to 20


----------



## craxton

Veii said:


> The price is identical to a 4000 C16-16-16 kit
> 150bucks for 16gb b-die , about right ~ often retails for 280€-310€
> 
> But i think he speaks more mainstream
> for the voltage , it's a low XMP binning
> And likely a stretched binning , stretched bad stock
> 
> I need to watch the whole video, if this is a typical "buyers will be happy" guide
> Then it's fine. Depends on the userbase level.
> He often mentions "casuals need to go away from his channel" , but also gets a lot of views from "casuals"
> I can't judge him on this , he knows his stuff and is funny to talk with
> I do not have anything even slightly bad against him. We just likely experienced two different realities ~ things he recommends, i don't. (mainboards including)
> Exotic behaviour i do, his community is literally on war against me
> But we together, i think are fine. Can not disagree with him without knowing the targeted userbase, just not the type of roulette i want to roll with ~ and rather go directly 4000+ for the same price
> Tho to his credit, we both went the cheap path with the vipers at the same time. He with a 4400 set, i with a 4000 set while they where 80-120$ and nobody knew or used them.
> Both love them ~ soo likely share the same mindset, yet no idea what the target audience for this buyers guide was
> 
> EDIT:
> I remember, he went with the same biostar i wanted to get 🤭
> We really aren't that different, but yes ~ just different experienced realities & slightly different music taste


well put, but i wasnt directing it "like" shots being fired lol.
but at the same time i know (here) one has to be 100% mindful of whats
said otherwise "shots fired" 

the use case is for those "wanting" XMP to work and not have to fuss with it, 
or those wanting to "overclock as well" 
as they have "lots" of headroom. also goes onto mention another "non bdie"
kit that scales extremely well in MHZ but at this moment i cant be bothered to 
rewatch for that spot even tho its not really that long (in the ram side)
to find it. (most that entire video was for the "best 5950x pairing for 
board/ram" not so much on price. and what he likes/dislikes vs what "normies"
would be using it/board for.

im semi "his" community but i cant state im against you in any way shape 
or form. how i see it, your name is tagged more than any other i see PERIOD 
thus you respond to most those tags. to where its harder to get his attention 
unless on a live stream or immediately upon upload (rather get a response anyhow) 

he does make a good point if your a BCLK overclocker to go for B550 boards 
that the x570 chipset just yells and cries about it, which my x570 "sister board" 
to the b550 i use now did just that. to where as this one doesnt much mind nor care. 

i suppose i agree with pieces of what he states especially on MSI boards and being 4 dim boards (any 4 dimm board)
minus a few boards with "new" memory layouts (4 dimm only) 

-------------------------------------------------------------------------------------------------------------------
(off topic)
since getting this 4x8 set to "run" 38/c14 and having strange things (due to SD/DD/SCL) 
i now know why i was getting such behaviors. 51xxx mbs read and like 45xxx copy....
to where as now, 57xxx and 55xxx

no y-cruncher has not been ran YET, as movie/bed time is approaching so ill re-run 
TM5 with some GPU stress test after jus to be sure. but none the less, "happy/proud"
i finally got this to "work" without "copying" someone elses work. (rttpark 4) was the magic trick/with fan)

(yes a screenshot of a screenshot, since for whatever reasons the site wouldnt allow me to post the 
"actual pic?" might be something i killed to run the aida bench idk.

(safe mode states 51.6 in win 10) but no such latency scores with the "services" i cant turn off in win 11
and safe mode doesnt "like" to run/work? (do you have issue with safe mode in win 11???
but thats cheating, and for whatever reasons i cant get the "script" to 
run in powershell so i gave up there...


----------



## gled_fr

Hi guys,

I reached my limits here, stable and runs well but I am sure a pro could do better.

1900Mhz FCLK is the max I had stable, 1933 starts giving WHEA errors even though ram is stable @ 4000Mhz with 2000 FCLK with the exact same timings.

Any idea what I could improve to get lower latency without loosing too much bandwidth ? Or any way I could get to disable GDM ? It does not POST without it with those timings.


----------



## ManniX-ITA

LePr3 said:


> Any tips to get this running 1t?


Setup timings on Matisse are more likely between 61 and 63.
Double check if 228 for tRFC is not too low.
In case also try ClkDrvStr at 120 Ohm.


----------



## mongoled

So what do we do when we have already "maxed out" tRFC values and we want to push lower ??

For example running [email protected] as per @XPEHOPE3 findings keeps tPHYRDL as low as we can (26 instead of 28 when running [email protected]), but the issue is the following if we decide to abide by the "rules"

Using [email protected], [email protected], [email protected], [email protected] and [email protected], the lowest tRFC we can use as per the rules is 270, but we are leaving performance on the table.

For the run below I "forcefully" apply a -4 to tRAS (26) and a -1 to tRC (40) to give me a tRFC of 240, which successfully passed TM5.

What other options are available ? Ideally we would like to a way to control tPHYRDL rather than leave it to memory training to decide ....


----------



## mongoled

Audioboxer said:


> @Veii I believe 6 is what you were after?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Also
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> LOL
> 
> I went away from the PC for a bit, so I think the error has came about 1 hour 20 in or something. Hoping it's just because my AUTO settings are a bit messy and not something else.
> 
> Going to try and more closely match settings from here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


This is what I meant regards just choosing "auto", there is no gurantee that it will work and as you can see even though certain values are completely relaxed it still fails.

The non AUTO values you are running are close to perfect (note re tWR I also suggested as had Veii to increase it to 14 from 12, think you missed the comment) so its a matter of just finding what the cause of the issue is for you.

The frustrating part is working out what is stopping you from changing your RttPark value as this could be the key to your issues.

Have you tested different memory straps to see if RttPark starts to behave i.e. reset BIOS, set 3600/1800 save settings, reboot, go into BIOS then manually set RttPark to a weaker value and see if it posts ??

Or don't change any settings, turn off PC from PSU and simply switch your dimm positions then retest to see if anything changes


----------



## mongoled

craxton said:


> well put, but i wasnt directing it "like" shots being fired lol.
> but at the same time i know (here) one has to be 100% mindful of whats
> said otherwise "shots fired"
> 
> the use case is for those "wanting" XMP to work and not have to fuss with it,
> or those wanting to "overclock as well"
> as they have "lots" of headroom. also goes onto mention another "non bdie"
> kit that scales extremely well in MHZ but at this moment i cant be bothered to
> rewatch for that spot even tho its not really that long (in the ram side)
> to find it. (most that entire video was for the "best 5950x pairing for
> board/ram" not so much on price. and what he likes/dislikes vs what "normies"
> would be using it/board for.
> 
> im semi "his" community but i cant state im against you in any way shape
> or form. how i see it, your name is tagged more than any other i see PERIOD
> thus you respond to most those tags. to where its harder to get his attention
> unless on a live stream or immediately upon upload (rather get a response anyhow)
> 
> he does make a good point if your a BCLK overclocker to go for B550 boards
> that the x570 chipset just yells and cries about it, which my x570 "sister board"
> to the b550 i use now did just that. to where as this one doesnt much mind nor care.
> 
> i suppose i agree with pieces of what he states especially on MSI boards and being 4 dim boards (any 4 dimm board)
> minus a few boards with "new" memory layouts (4 dimm only)
> 
> -------------------------------------------------------------------------------------------------------------------
> (off topic)
> since getting this 4x8 set to "run" 38/c14 and having strange things (due to SD/DD/SCL)
> i now know why i was getting such behaviors. 51xxx mbs read and like 45xxx copy....
> to where as now, 57xxx and 55xxx
> 
> no y-cruncher has not been ran YET, as movie/bed time is approaching so ill re-run
> TM5 with some GPU stress test after jus to be sure. but none the less, "happy/proud"
> i finally got this to "work" without "copying" someone elses work. (rttpark 4) was the magic trick/with fan)
> 
> (yes a screenshot of a screenshot, since for whatever reasons the site wouldnt allow me to post the
> "actual pic?" might be something i killed to run the aida bench idk.
> 
> (safe mode states 51.6 in win 10) but no such latency scores with the "services" i cant turn off in win 11
> and safe mode doesnt "like" to run/work? (do you have issue with safe mode in win 11???
> but thats cheating, and for whatever reasons i cant get the "script" to
> run in powershell so i gave up there...
> View attachment 2517579


Nice you have flat 14s running, good modules 

More interesting for me is that even at [email protected] you have tPHYRDL training at 26! I am not able to get my modules to train at this value when using [email protected] ...

Shame you are doing this on Windows 11 as we cant do a more direct comparisson with your TM5 time.

Its very slow! Dont know if its because of too much auto correction on your set or because of Windows 11.

You can seem my TM5 time in the screenshots below your post, TM5 runs between 2:49 to 2:52 minutes for me with "worse" timings


----------



## Taraquin

gled_fr said:


> Hi guys,
> 
> I reached my limits here, stable and runs well but I am sure a pro could do better.
> 
> 1900Mhz FCLK is the max I had stable, 1933 starts giving WHEA errors even though ram is stable @ 4000Mhz with 2000 FCLK with the exact same timings.
> 
> Any idea what I could improve to get lower latency without loosing too much bandwidth ? Or any way I could get to disable GDM ? It does not POST without it with those timings.
> 
> View attachment 2517581


Try tRAS 31, tRC 45 and tRFC 270, tRTP 6. How much volt at ram?


----------



## mongoled

OK, so it looks like tCL and Cmd2T are the timings that directly influence tPHYRDL

Setting either tCL to 14 or Cmd2T to 1T at 3800mhz forces tPHYRDL to 28...

Looks like I will be sticking with [email protected] with [email protected] as dropping to 2T results in loss of read throughput but no loss in latency....


----------



## Audioboxer

mongoled said:


> This is what I meant regards just choosing "auto", there is no gurantee that it will work and as you can see even though certain values are completely relaxed it still fails.
> 
> The non AUTO values you are running are close to perfect (note re tWR I also suggested as had Veii to increase it to 14 from 12, think you missed the comment) so its a matter of just finding what the cause of the issue is for you.
> 
> The frustrating part is working out what is stopping you from changing your RttPark value as this could be the key to your issues.
> 
> Have you tested different memory straps to see if RttPark starts to behave i.e. reset BIOS, set 3600/1800 save settings, reboot, go into BIOS then manually set RttPark to a weaker value and see if it posts ??
> 
> Or don't change any settings, turn off PC from PSU and simply switch your dimm positions then retest to see if anything changes


I'll try 3600/1800 on a bios reset and see if it boots RttPark 3.

After my AUTO eveything failed I changed a few things. On advice from @Veii I took VSOC off auto and made it 1.125v. The reason for this is the gap over my VDDG IOD on auto. VDDG CCD remains on auto. I put CLDO VDDP to 0.9v and CPU 1.80v is at 1.83v.

I then copied most of @XPEHOPE3 DR AUTO settings. Their settings were quite similar to mine for most things on AUTO but notable changes were some timings RttNom on 7 and 24/20/24/24 instead of 24/24/24/24










It has now passed, thankfully. I have a baseline for GDM disabled at 3800. Not entirely sure what got me over the line compared to my AUTO settings failing










Could just be as "simple" as my VSOC droop was too much, but I also wonder if RttNom on 7 made a difference? It was disabled by AUTO for me.

Up next, where do I go from here? I roughly understand where I'd like to end up with 15-15-15-15, but I'd rather take it slow and steady now to get there. My DrvStr settings at 24/20/24/24 are much lower than what I was attempting previously, so when would they come into play? I appreciate all the advice and guidance, I guess the main difference for me and my past experience is I'm now working with GDM off and the right hand side is much more important. When I done my CL16 profiles for this RAM with GDM on, not much thought went into resistances and DrvStr.

I don't mind this taking a week or few weeks to sort out, but I'd rather not waste my own time doing anything stupid or throwing darts at a dartboard blind again


----------



## XPEHOPE3

mongoled said:


> Using [email protected], [email protected], [email protected], [email protected] and [email protected], the lowest tRFC we can use as per the rules is 270, but we are leaving performance on the table.


Per what rules is tRFC 270 for those settings? Isn't it 240 just as you used for test?
Also I was able to run just about any tRFC irrespective of tRC or tRTP. So you can try like pushing closer to 120ns by just changing tRFCs only. I feel like tRFC divisible by 4 are easier to post (236,232,228~120ns already).


mongoled said:


> Its very slow! Dont know if its because of too much auto correction on your set or because of Windows 11.
> 
> You can seem my TM5 time in the screenshots below your post, TM5 runs between 2:49 to 2:52 minutes for me with "worse" timings


Note that @craxton even has faster clocked CPU! But you have lower tRFC, lower *SCL and 1T. I think that gives that of a difference.

@Audioboxer
pls edit your screenshots in Paint to provide VDIMM info (every time) so that people don't have to remember it from previous posts 
Also it's interesting to see your ZenTimings for *B2* stick to check tPHYRDL and tRDWR (if it's on auto) there.
You should start running y-cruncher (pressing 1-7-0 in the menu) for at least 4 iterations to verify voltage and current stability (also of your CPU). Because in the end RAM controller, etc. eat from the same powerbudget as CPU.
After that you can start buying Aida64 and recording your latency progress 
And 25 cycles of TM5 are much better than 20 cycles, especially when you are going to tighten tRFC

To push (slightly) higher clocks or lower primaries I had to set SD/DD to 1-4-4-1-6-6 (from 1-5-5-1-7-7). But getting 38-15 on our sticks is quite easy even without it ("just set 'em to 15" lol, tCWL on Auto set itself to 14, but you better set it yourself like that, as well as tRDWR to 10):









However for me tPHYRDL jumped to 28, so perf gain wasn't much.


----------



## Nighthog

Audioboxer said:


> I'll try 3600/1800 on a bios reset and see if it boots RttPark 3.
> 
> After my AUTO eveything failed I changed a few things. On advice from @Veii I took VSOC off auto and made it 1.125v. The reason for this is the gap over my VDDG IOD on auto. VDDG CCD remains on auto. I put CLDO VDDP to 0.9v and CPU 1.80v is at 1.83v.
> 
> I then copied most of @XPEHOPE3 DR AUTO settings. Their settings were quite similar to mine for most things on AUTO but notable changes were some timings RttNom on 7 and 24/20/24/24 instead of 24/24/24/24
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> It has now passed, thankfully. I have a baseline for GDM disabled at 3800. Not entirely sure what got me over the line compared to my AUTO settings failing
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Could just be as "simple" as my VSOC droop was too much, but I also wonder if RttNom on 7 made a difference? It was disabled by AUTO for me.
> 
> Up next, where do I go from here? I roughly understand where I'd like to end up with 15-15-15-15, but I'd rather take it slow and steady now to get there. My DrvStr settings at 24/20/24/24 are much lower than what I was attempting previously, so when would they come into play? I appreciate all the advice and guidance, I guess the main difference for me and my past experience is I'm now working with GDM off and the right hand side is much more important. When I done my CL16 profiles for this RAM with GDM on, not much thought went into resistances and DrvStr.
> 
> I don't mind this taking a week or few weeks to sort out, but I'd rather not waste my own time doing anything stupid or throwing darts at a dartboard blind again


*tCWL = tCL* is harder to run than *tCWL-2/-1 <= tCL
AddrCmdDrvStr* is usually not liked to be anything but *20 Ohm* for many setups. (adds lots of stability to run 20)

Just quick observations on those two changes you had.


----------



## Audioboxer

XPEHOPE3 said:


> Per what rules is tRFC 270 for those settings? Isn't it 240 just as you used for test?
> Also I was able to run just about any tRFC irrespective of tRC or tRTP. So you can try like pushing closer to 120ns by just changing tRFCs only. I feel like tRFC divisible by 4 are easier to post (236,232,228~120ns already).
> Note that @craxton even has faster clocked CPU! But you have lower tRFC, lower *SCL and 1T. I think that gives that of a difference.
> 
> @Audioboxer
> pls edit your screenshots in Paint to provide VDIMM info (every time) so that people don't have to remember it from previous posts
> Also it's interesting to see your ZenTimings for *B2* stick to check tPHYRDL and tRDWR (if it's on auto) there.
> You should start running y-cruncher (pressing 1-7-0 in the menu) for at least 4 iterations to verify voltage and current stability (also of your CPU). Because in the end RAM controller, etc. eat from the same powerbudget as CPU.
> After that you can start buying Aida64 and recording your latency progress
> And 25 cycles of TM5 are much better than 20 cycles, especially when you are going to tighten tRFC
> 
> To push (slightly) higher clocks or lower primaries I had to set SD/DD to 1-4-4-1-6-6 (from 1-5-5-1-7-7). But getting 38-15 on our sticks is quite easy even without it ("just set 'em to 15" lol, tCWL on Auto set itself to 14, but you better set it yourself like that, as well as tRDWR to 10):
> View attachment 2517599
> 
> 
> However for me tPHYRDL jumped to 28, so perf gain wasn't much.


I actually meant to ask how do I get VDIMM to show lol. Is it something I can change in the BIOS or do only certain motherboards show the information in ZenTimings? It's 1.5v above but I will do what you said if I need to manually add it in.

Thanks for some guidance on where to head next.

Just for a "laugh" there waiting on some responses I decided to chuck tCL onto 14 and see if it boots. Flat 14 booted, but error'd quickly. tCL14 on its own showed some potential










Just ended it there though because it's not my main focus right now. 

I'll do Y-Cruncher now with the settings that passed 20 cycles but also edit my .cfg file for 25 cycles going forward.



Nighthog said:


> *tCWL = tCL* is harder to run than *tCWL-2/-1 <= tCL
> AddrCmdDrvStr* is usually not liked to be anything but *20 Ohm* for many setups. (adds lots of stability to run 20)
> 
> Just quick observations on those two changes you had.


Thanks, good to know, I appreciate that information.


----------



## XPEHOPE3

Audioboxer said:


> do only certain motherboards show the information in ZenTimings


That. ZenTimings can't get VDIMM for ASUS mobos.


----------



## paih85

retest with lower trfc / trtp /twr.. same vdimm @1.45v. No active cooling + n200 case. 😅


----------



## XPEHOPE3

paih85 said:


> retest with lower trfc / trtp /twr.. same vdimm @1.45v. No active cooling + n200 case.


RTTPark /3 seems to do little to help with temps here. @Veii why?


----------



## Audioboxer

paih85 said:


> retest with lower trfc / trtp /twr.. same vdimm @1.45v. No active cooling + n200 case. 😅
> 
> View attachment 2517606
> 
> 
> View attachment 2517607


Nice I'm hoping to get something like this eventually. I'm staying at 1.5v just now as I've got active cooling but it's great to see you do that at 1.45v.

I also looked up your BIOS version, it's on the B patch. Here is hoping when Asus roll that out to my mobo it might fix me not posting at RttPark 3. Should hopefully be any day now it drops on the X570 mobos.

Just noticed your temps though 🔥😱 lol


----------



## paih85

Audioboxer said:


> Nice I'm hoping to get something like this eventually. I'm staying at 1.5v just now as I've got active cooling but it's great to see you do that at 1.45v.
> 
> I also looked up your BIOS version, it's on the B patch. Here is hoping when Asus roll that out to my mobo it might fix me not posting at RttPark 3. Should hopefully be any day now it drops on the X570 mobos.
> 
> Just noticed your temps though 🔥😱 lol


----------



## Mach3.2

Is it normal for tertiary timings to be not matched for both sticks in dual channel? tRDWR and tWRRD is also different between the A2 and B2 stick. tPHYRDL is different too, 28 on A2 and 26 on B2. Does anyone know what is tPHYRDL?

Edit: I believe both tRDWR and tWRRD are set to auto.



















Still on the old set of timing, having lots of trouble trying to tighten tRP to 15..
Banged on my head for the entire night but not much progress, maybe next time when I find more energy.


Spoiler: Horrible handwritten notes

















Spoiler: Timings for first 3 runs of TM5


----------



## Audioboxer

Y-Cruncher going fine, that's 4 cycles passed, but I'll let it go a bit longer.


----------



## mongoled

XPEHOPE3 said:


> Per what rules is tRFC 270 for those settings? Isn't it 240 just as you used for test?
> Also I was able to run just about any tRFC irrespective of tRC or tRTP. So you can try like pushing closer to 120ns by just changing tRFCs only. I feel like tRFC divisible by 4 are easier to post (236,232,228~120ns already).


As per the formula found here while using the tRFC/tRP checker field set to 1/2 validator.

Using the values I quoted ([email protected], [email protected], [email protected], [email protected] and [email protected] @3800mhz) gives tRFC/tRFC2/tRFC4 of 270/201/123 respectivly



XPEHOPE3 said:


> Note that @craxton even has faster clocked CPU! But you have lower tRFC, lower *SCL and 1T. I think that gives that of a difference.


As I said, too many different variables, main one being a different OS, yes I have some tighter timings but @craxton has tRCDRD set to 14 which is a very performant timing!

Anyhow, just waiting for the following TM5 to finish, this looks like it will be my new 24/7 settings, more performant than [email protected], [email protected] and [email protected]

Here is a Sisoft Sandra result









Details for Result ID AMD Ryzen 5 5600X 6-Core Processor (6C 12T 4.85GHz, 1.9GHz IMC, 6x 512kB L2, 32MB L3)







ranker.sisoftware.co.uk





And rankings for 5600x (non certified results are omitted)








Details for Component AMD Ryzen 5 5600X 6-Core







ranker.sisoftware.co.uk


----------



## Audioboxer

XPEHOPE3 said:


> Per what rules is tRFC 270 for those settings? Isn't it 240 just as you used for test?
> Also I was able to run just about any tRFC irrespective of tRC or tRTP. So you can try like pushing closer to 120ns by just changing tRFCs only. I feel like tRFC divisible by 4 are easier to post (236,232,228~120ns already).
> Note that @craxton even has faster clocked CPU! But you have lower tRFC, lower *SCL and 1T. I think that gives that of a difference.
> 
> @Audioboxer
> pls edit your screenshots in Paint to provide VDIMM info (every time) so that people don't have to remember it from previous posts
> Also it's interesting to see your ZenTimings for *B2* stick to check tPHYRDL and tRDWR (if it's on auto) there.
> You should start running y-cruncher (pressing 1-7-0 in the menu) for at least 4 iterations to verify voltage and current stability (also of your CPU). Because in the end RAM controller, etc. eat from the same powerbudget as CPU.
> After that you can start buying Aida64 and recording your latency progress
> And 25 cycles of TM5 are much better than 20 cycles, especially when you are going to tighten tRFC
> 
> To push (slightly) higher clocks or lower primaries I had to set SD/DD to 1-4-4-1-6-6 (from 1-5-5-1-7-7). But getting 38-15 on our sticks is quite easy even without it ("just set 'em to 15" lol, tCWL on Auto set itself to 14, but you better set it yourself like that, as well as tRDWR to 10):
> View attachment 2517599
> 
> 
> However for me tPHYRDL jumped to 28, so perf gain wasn't much.


After y-cruncher was a success I moved on to trying to replicate this, so the only change made was flat 15's and tRDWR to 10.










Here we have an error. So it seems my issues from the last few days has likely been around trying to get 15-15-15-15 stable and what voltage or resistance combo is needed. I'm still at 1.5v VDIMM.

Will try above but with 40 ClkDrvStr first.

*Edit*: Error on 10 within a few minutes










Gonna wait for some advice on what to try next rather than stabbing in the dark again.

I have noticed your VSOC is quite a bit higher than mine. Guess I'll try another small bump in VSOC and maybe 1.52v VDIMM.










VSOC 1.2v and VDIMM 1.55v seem to have made things worse lol.

Will have a look at resistances. Maybe 15 flat is going to be a dud for these sticks?


----------



## XPEHOPE3

mongoled said:


> Using the values I quoted ([email protected], [email protected], [email protected], [email protected] and [email protected] @3800mhz) gives tRFC/tRFC2/tRFC4 of 270/201/123 respectivly


Can't be. Only for tRC 45 it is. For 40 it's 240 (but you need -5 for tRC manually put to blue cell). Check 0.7b_D list now before someone edits it.


----------



## Nighthog

Finally a result with no errors @ 5000Mts, with decent tight settings, not absolute minimum but a base to work from.
I need to keep the dimms below 44C if I want to avoid issues in general as chances of errors increase into 46C where it will crash in general.

Needed to set ~1.590V to have it work, more voltage is a issue. though this means I most likely can't run tCL @ 17 as that one requires ~1.600V to work without issues from earlier testing on the other pair.
I also needed to set DDRVPP to 2.740V on this kit to pass this round, 2.5V isn't enough to work.

CLDO_VDDP is only 950mv. (edit: 1000mv)
SoC voltage is excessive but enough to work. I was trying manual OC before and it required more SoC @ these higher FCLK frequencies in the 2200+ range to pass Y-cruncher. When only using PBO this amount isn't necessary.
There is a Termination voltage offset for this round -0.025V. Was just testing, it was passing with no adjustment earlier. Might be able to have even less.

EDIT: Forgot to say TSME was enabled...
EDIT2: *Added TSME Enabled & Disabled comparison.*


----------



## XPEHOPE3

Audioboxer said:


> Y-Cruncher going fine, that's 4 cycles passed, but I'll let it go a bit longer.


BTW really only 3 cycles passed. You can scroll up and see the first one being just a setup cycle allocating memory.


Audioboxer said:


> so the only change made was flat 15's and tRDWR to 10.


Maybe tRDWR set back to 11. For previous setup tRDWR should have been roundup(tRCDRD/2)+2[because DR]+(tCL-tCWL)=8+2+2=12, but was stable at 11 for unknown reason. I thought for 15 flat you need to lower it because of the same unknown reason  but it seems than now formula above may work and gives 8+2+1=11.

If that won't work, I'd change SD/DD to 1-4-4-1-6-6, and if that fails, fiddle with right hand side. For me prodODT 40 and CAD_BUS 40-20-30-20 seem to perform best.

@Nighthog 
tSTAG 12? much wow


----------



## Audioboxer

XPEHOPE3 said:


> BTW really only 3 cycles passed. You can scroll up and see the first one being just a setup cycle allocating memory.
> 
> Maybe tRDWR set back to 11. For previous setup tRDWR should have been roundup(tRCDRD/2)+2[because DR]+(tCL-tCWL)=8+2+2=12, but was stable at 11 for unknown reason. I thought for 15 flat you need to lower it because of the same unknown reason  but it seems than now formula above may work and gives 8+2+1=11.
> 
> If that won't work, I'd change SD/DD to 1-4-4-1-6-6, and if that fails, fiddle with right hand side. For me prodODT 40 and CAD_BUS 40-20-30-20 seem to perform best.


Ah right I counted 0 as the first. I let it run another full one anyway from that picture. I'll give that advice a go! Bumping voltage did not work xD Made things worse it seems.

What is a safe VSOC limit anyway? I think you're running about 1.2v, correct?


----------



## Veii

XPEHOPE3 said:


> RTTPark /3 seems to do little to help with temps here. @Veii why?


Can't imagine it
Maybe RGB, maybe GPU heat, maybe Ripjaws half coverage heatsinks
Too many factors, nearly no details
Maybe eben negative pressure airflow instead of positive pressure ~ who knows


----------



## Blameless

Mach3.2 said:


> Is it normal for tertiary timings to be not matched for both sticks in dual channel?


It's not unusual for some sub timings to be different between channels when left on auto. These are presumably set during training to account for different trace lengths or other electrical properties that may not be identical.


----------



## mongoled

XPEHOPE3 said:


> Can't be. Only for tRC 45 it is. For 40 it's 240 (but you need -5 for tRC manually put to blue cell). Check 0.7b_D list now before someone edits it.


Sorry my bad, tRC should have been quoted as 45


----------



## mongoled

Audioboxer said:


> Ah right I counted 0 as the first. I let it run another full one anyway from that picture. I'll give that advice a go! Bumping voltage did not work xD Made things worse it seems.
> 
> What is a safe VSOC limit anyway? I think you're running about 1.2v, correct?


Dude, did you try switching the dimms around ?


----------



## mongoled

Completed, now for some performance screenshots


----------



## XPEHOPE3

Mach3.2 said:


> Is it normal for tertiary timings to be not matched for both sticks in dual channel? tRDWR and tWRRD is also different between the A2 and B2 stick. tPHYRDL is different too, 28 on A2 and 26 on B2.


Yes, and I was writing about it for past several pages. On auto those can be different. tPHYRDL from the name seems like read latency of PHY component of RAM. Dunno what it is, but I saw it in DDR4 specs somewhere.


----------



## byDenoso

i was testing the influence of the subtimings (gaming wise), and i realized than the tRDD_, tFAW, tRP, tRC and tRFC is the most important ones.
So i'll work on tightening subs instead of loosening them to lower primaries.


----------



## Audioboxer

XPEHOPE3 said:


> BTW really only 3 cycles passed. You can scroll up and see the first one being just a setup cycle allocating memory.
> 
> Maybe tRDWR set back to 11. For previous setup tRDWR should have been roundup(tRCDRD/2)+2[because DR]+(tCL-tCWL)=8+2+2=12, but was stable at 11 for unknown reason. I thought for 15 flat you need to lower it because of the same unknown reason  but it seems than now formula above may work and gives 8+2+1=11.
> 
> If that won't work, I'd change SD/DD to 1-4-4-1-6-6, and if that fails, fiddle with right hand side. For me prodODT 40 and CAD_BUS 40-20-30-20 seem to perform best.
> 
> @Nighthog
> tSTAG 12? much wow


All below is on 1.5 VDIMM











Same as my stable profile, just changed to flat 15s, crashed within minutes on 1.










Changed DD and SD's to 4/4 and 6/6. Crashed wihtin minutes on 13.










Kept SD and DD's on 4/4 and 6/6 and also set DrvStr to 40/20/30/20 and ProcODT to 40. Crashed in 15 minutes on 6.

Not having much luck lol. Wondering if 15-15-15-15 is going to be out of my reach or there is something to get me across that line. I've ran 16-15-15-13 on a CL16 profile OK.

A crash on 6 might suggest a bit more VDIMM could help??? I guess I could play about with RttNom as well, maybe 6 or disabled again?

With crashes on all different numbers its not helping narrow this down xD



mongoled said:


> Dude, did you try switching the dimms around ?


Not yet, do you mean just swapping them between current slots, or trying them in the other mobo slots?


----------



## Veii

@craxton Good Job !
Happy to see you succeeded your goal
I hope you also healed and feel better now 


Audioboxer said:


> Gonna wait for some advice on what to try next rather than stabbing in the dark again.


SCL * X = equal or bellow tRCDWR = tWRRD
5 tWRRD is too high for used 5-5 SCL ~ try with 3
26 WR, 14 tRTP are awkward

If you feel that tRTP is fine that high then WR should be the double of it
Trying yes, but you have an error description sheet. It should help


----------



## XPEHOPE3

Audioboxer said:


> 40/20/30/20 and ProcODT to 40. Crashed in 15 minutes on 1


Why do you say "on 1" if it crashed on test 6 and not even first cycle?

Anyway, I'd pick the setting where you crash the latest and try to vary VDIMM, procODT, CAD_BUS there.

For what it's worth you can replicate my whole settings from this 3800-15 post. Note that I ran vCore LLC normal ("droopiest") and vSoc LLC Turbo (1 setting lower than the most flat LLC), PBO disabled, manual Scalar to 1x.


----------



## byDenoso

Audioboxer said:


> All below is on 1.5 VDIMM
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Same as my stable profile, just changed to flat 15s, crashed within minutes on 1.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Changed DD and SD's to 4/4 and 6/6. Crashed wihtin minutes on 13.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Kept SD and DD's on 4/4 and 6/6 and also set DrvStr to 40/20/30/20 and ProcODT to 40. Crashed in 15 minutes on 6.
> 
> Not having much luck lol. Wondering if 15-15-15-15 is going to be out of my reach or there is something to get me across that line. I've ran 16-15-15-13 on a CL16 profile OK.
> 
> A crash on 6 might suggest a bit more VDIMM could help??? I guess I could play about with RttNom as well, maybe 6 or disabled again?
> 
> With crashes on all different numbers its not helping narrow this down xD
> 
> 
> 
> Not yet, do you mean just swapping them between current slots, or trying them in the other mobo slots?


You can Bump VDDG IOD and vSOC a bit and test again. Lower RTT park is good too.


----------



## Veii

byDenoso said:


> i was testing the influence of the subtimings (gaming wise), and i realized than the tRDD_, tFAW, tRP, tRC and tRFC is the most important ones.
> So i'll work on tightening subs instead of loosening them to lower primaries.


You didn't test if lowering primaries does any change
Because 200MB/s and a difference of 0.5-0.6ns is a big difference
More than these timings do bring. Primaries always have higher priority, especially tRCDRD
tCL is less important

Minimum FPS increase by memory bandwidth and rather access latency
Games will scale different between each game, depending on the datasize this programm uses
Games are not specific loadtype and don't deserve to be optimized for
Every game will perform different
Optimize for higher IPC not for specific program loadtypes 
Minimum fps will increase once instructions to memory back to cache ~ can be fullfiled in shorter time = lower mem and fabric latency (intercore latency which SiSoftware Sandra shows)


----------



## Audioboxer

XPEHOPE3 said:


> Why do you say "on 1" if it crashed on test 6 and not even first cycle?
> 
> Anyway, I'd pick the setting where you crash the latest and try to vary VDIMM, procODT, CAD_BUS there.
> 
> For what it's worth you can replicate my whole settings from this 3800-15 post. Note that I ran vCore LLC normal ("droopiest") and vSoc LLC Turbo (1 setting lower than the most flat LLC), PBO disabled, manual Scalar to 1x.


I edited the post shortly after posting, it was a typo.

Will keep trying. I did try those settings from your post, that is what crashed here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## mongoled

Audioboxer said:


> Not yet, do you mean just swapping them between current slots, or trying them in the other mobo slots?


Current slots!


----------



## Audioboxer

Veii said:


> @craxton Good Job !
> Happy to see you succeeded your goal
> I hope you also healed and feel better now
> 
> SCL * X = equal or bellow tRCDWR = tWRRD
> 5 tWRRD is too high for used 5-5 SCL ~ try with 3
> 26 WR, 14 tRTP are awkward
> 
> If you feel that tRTP is fine that high then WR should be the double of it
> Trying yes, but you have an error description sheet. It should help


I wasn't focusing on the secondaries all that much on the basis they passed at flat 16s. They're basically just really loose AUTO settings right now.

I wanted to see if I could get flat 15s passing a stability test even if it was with those loose timings. So I know some of them might not make sense.


----------



## XPEHOPE3

Audioboxer said:


> I did try those settings from your post, that is what crashed here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


No, those are not my settings which crashed according to screenshot in the linked post.


----------



## Audioboxer

XPEHOPE3 said:


> No, those are not my settings which crashed according to screenshot in the linked post.


Linked to wrong post, sorry [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## byDenoso

Veii said:


> You didn't test if lowering primaries does any change
> Because 200MB/s and a difference of 0.5-0.6ns is a big difference
> More than these timings do bring. Primaries always have higher priority, especially tRCDRD
> tCL is less important
> 
> Minimum FPS increase by memory bandwidth and rather access latency
> Games will scale different between each game, depending on the datasize this programm uses
> Games are not specific loadtype and don't deserve to be optimized for
> Every game will perform different
> Optimize for higher IPC not for specific program loadtypes
> Minimum fps will increase once instructions to memory back to cache ~ can be fullfiled in shorter time = lower mem and fabric latency (intercore latency which SiSoftware Sandra shows)


Actually i've tried to lower primaries, but with no sucess.
My tRC lower than 56 just spit errors, tRP lower than 17 too, i've followed your "Shenanigans" but didn't work (maybe because my board limit vDIMM to 1,5vmax)
And yes, my goal is to increase IPC


----------



## mongoled

Performance numbers















Only difference between the sets is the following

tCL is 15 in the first screenshot and 14 in the second screenshot
tCWL is 14 in the first screenshot and 12 in the second screenshot (has to change to the next optimum tCWL value)
tRCDRD is 15 in the first screenshot and 14 in the second screenshot
tRAS is 30 in the first screenshot and 26 in the second screenshot
tRC is 38 in the first screenshot and 40 in the second screenshot
tRDWR is 9 in the first screenshot and 10 in the second screenshot (has to change to the next optimum tRDWR value)
tWRRD is 4 in the first screenshot and 1 in the second screenshot (has to change to the next optimum tWRRD value)
tRDRDSCL/tWRWRSCL are set to 4 in the first screenshot and 5 in the second screenshot (small note: I know from testing on an previous BIOS that there is no performance difference between using 4 or 5)

So to summarize, on post tPHYRDL is trained at different values dependent on what tCL/Cmd2T is set.

Memory Training
tCL @14 sets tPHYRDL to 28 while tCL @15 sets tPHYRDL to 26


----------



## XPEHOPE3

Audioboxer said:


> Linked to wrong post, sorry [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Again, not my settings as I have different voltages.

@mongoled 
Can you pls point me to your screenshot with tCL14 performance? (aka "previous 24/7")


----------



## mongoled

XPEHOPE3 said:


> Again, not my settings as I have different voltages.
> 
> @mongoled
> Can you pls point me to your screenshot with tCL14 performance? (aka "previous 24/7")


Will have to redo those on the new bios

I only have an old screensot with them all from BIOS A.85

@XPEHOPE3 ive updated my previous post with my "24/7" settings


----------



## Sphex_

PJVol said:


> I may have not as high binned chips as yours but think they're in the same ballpark.
> Anyway, you can try to boot with these timings (24/7 set):
> 
> View attachment 2517537
> 
> 
> There may be some issues with MBIST. For example my pc might not boot right after changing CL15 to 16 in this preset, but will do after power cycle.
> 
> PS: One important thing.
> There's no way to boot with [email protected] with tRDWR 8.


After some tuning with great advice from Veii, I decided to plug these values in and see what happened. Rock Solid overnight TM5. Dropped my memory latency even further. Idk what kit you have but these were literally plug n play for me. Thanks for the Timings bro!


----------



## Audioboxer

XPEHOPE3 said:


> Again, not my settings as I have different voltages.
> 
> @mongoled
> Can you pls point me to your screenshot with tCL14 performance? (aka "previous 24/7")


Good point, my bad. Felt a bit nervous pumping my voltages that much higher than they are, but it did get me the furthest yet










This is with a VDIMM of 1.45v instead of my usual 1.5v. So I might try that.


----------



## gled_fr

Taraquin said:


> Try tRAS 31, tRC 45 and tRFC 270, tRTP 6. How much volt at ram?


Thank you, 57.4ns latency now ! Stability test running, so far no errors. RAM is at 1.45V, the stock XMP voltage.

It's funny relaxing tras and trc improved latency. Should I try disabling GDM with those settings ?


----------



## Mach3.2

imo always try settings with GDM off at 1T, only turn on GDM if you ran out of options.


----------



## spajdr

Hi gents,
Any tip what to set here? to prevent errors from reporting.
Tried ClkDrvStr set to 24 Ω , no difference.


----------



## reddify

Veii said:


> You didn't test if lowering primaries does any change
> Because 200MB/s and a difference of 0.5-0.6ns is a big difference
> More than these timings do bring. Primaries always have higher priority, especially tRCDRD
> tCL is less important
> 
> Minimum FPS increase by memory bandwidth and rather access latency
> Games will scale different between each game, depending on the datasize this programm uses
> Games are not specific loadtype and don't deserve to be optimized for
> Every game will perform different
> Optimize for higher IPC not for specific program loadtypes
> Minimum fps will increase once instructions to memory back to cache ~ can be fullfiled in shorter time = lower mem and fabric latency (intercore latency which SiSoftware Sandra shows)


This is a very very valid point, I like it, it makes sense!
But what will give the most benefit to IPC? Lower latency or read/write/copy bandwidth? I am sure you mentioned it in the post, but sorry my english is not very good, I didn´t get it. Can you please write it more clear what we should prefer? Perhaps what is good / bad trade? Like 0.5ns slower latency for 200MB/s more copy is good or not?


----------



## Audioboxer

Argh, almost










2 hours in, error on 13.

I decided earlier to have one last YOLO pending waiting on ASUS releasing patch B bios for this board and seeing if I could get RttPark 3. So I took @XPEHOPE3 voltage settings, stuck 40 on ClkDrvStr and grabbed a load of settings I was trying a day ago. Good news is I'm not getting the 12 errors I was getting before, I'm guessing pumping voltages took care of that. Bad news is 13 is a new error for me lol










As for RAM over heating










VDIMM is 1.46V.

Would RttNom 6 be classed as stronger than 7?


----------



## gled_fr

Mach3.2 said:


> imo always try settings with GDM off at 1T, only turn on GDM if you ran out of options.


GDM off same settings is not stable, errors out pretty quickly.

GDM off:








GDM on:








I am still learning, but it's weird since every timing that GDM is supposed to even out, is already even.
I understand that trfc2 and trfc4 could be lower, but it does not matter at the temp I am running, correct?

I also tried the timings from this previous post since RAM seemed similar, no luck errors out almost right away, even though was able to boot.

Any ideas how to improve further ?


----------



## Audioboxer

gled_fr said:


> GDM off same settings is not stable, errors out pretty quickly.
> 
> GDM off:
> View attachment 2517662
> 
> 
> GDM on:
> View attachment 2517663
> 
> 
> I am still learning, but it's weird since every timing that GDM is supposed to even out, is already even.
> I understand that trfc2 and trfc4 could be lower, but it does not matter at the temp I am running, correct?
> 
> I also tried the timings from this previous post since RAM seemed similar, no luck errors out almost right away, even though was able to boot.
> 
> Any ideas how to improve further ?


I'm hardly the one to be asking given where I am lol but your situation is quite similar to mine. A tight CL16 profile with GDM on will pass fine (mines were 16-15-15-13), but taking GDM off kind of starts you from scratch especially if you are aiming for 1T.

I've got DR too so you're going to have to do what I'm doing and switch to 2T and try and find a stable base at 15-15-15-15. Lots of good advice given to me over last pages and importantly here is the error code document tRFC Calculator (mini)

From what I'm discovering GDM off and/or CL15 might require both voltage changes from whatever you have stable right now and more important ProcODT down to CkeDrvStr seem to be far more crucial when working with GDM off/trying to achieve 1T.


----------



## gled_fr

Audioboxer said:


> I'm hardly the one to be asking given where I am lol but your situation is quite similar to mine. A tight CL16 profile with GDM on will pass fine (mines were 16-15-15-13), but taking GDM off kind of starts you from scratch especially if you are aiming for 1T.
> 
> I've got DR too so you're going to have to do what I'm doing and switch to 2T and try and find a stable base at 15-15-15-15. Lots of good advice given to me over last pages and importantly here is the error code document tRFC Calculator (mini)
> 
> From what I'm discovering GDM off and/or CL15 might require both voltage changes from whatever you have stable right now and more important ProcODT down to CkeDrvStr seem to be far more crucial when working with GDM off/trying to achieve 1T.


Ah thank you 

switch to 2T, find a stable base then work our way to 1T from there ?

I'll reread answers to your posts in the last pages too. 

Learning curve is really interesting !


----------



## Audioboxer

gled_fr said:


> Ah thank you
> 
> switch to 2T, find a stable base then work our way to 1T from there ?
> 
> I'll reread answers to your posts in the last pages too.
> 
> Learning curve is really interesting !


It seems in most cases you've basically got to start all over again. I guess that is what drives some of the regular posters mad, over 500 pages of people probably coming in saying "GDM off won't work but my settings with it on pass 8+ hours of MemTest5" 

You've got an Asus board on same BIOS as me, check for me if you can boot RttPark 3 at some point. As you can see from here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread most posters using DR end up going 6/3/3. You could try the settings on that post, but never expect mem settings to just be plug and play, rarely that simple.

I can't boot RttPark 3 no matter what I do. I'm hoping it's just this Patch A of the Asus Bios we have and Patch B fixes it.

Your memory is basically a better binned version of mine so it will be interesting to see where you end up. Have you tried going for CL14 at 3800? With that binning it could be do-able.


----------



## Veii

reddify said:


> This is a very very valid point, I like it, it makes sense!
> But what will give the most benefit to IPC? Lower latency or read/write/copy bandwidth? I am sure you mentioned it in the post, but sorry my english is not very good, I didn´t get it. Can you please write it more clear what we should prefer? Perhaps what is good / bad trade? Like 0.5ns slower latency for 200MB/s more copy is good or not?


I really don't know.
Aida64 is nothing but a short term latency test. Consistent if you set it up, but just a memory test

SiSofttware Sandra is far better, and there inter-core latency is nearly always key
Bandwidth then is calculated by many variables, soo generally a higher "bandwidth" result is better. 
You can benchmark miners, benchmark Cinebench and Geekbench ~ benchmark 3D Mark CPU tests and time spy cpu focus

You can benchmark superpi 1.5 SX for memory & cpu boost perfomance
Use benchmate, to not only test superpi but also 7zip compiling times
There are game benchmarks, which are more synthetic ~ but ultimately cross core latency plays the biggest role in IPC gain

Better PBO boosting does change cache results, but FCLK OC does influence it too
MemoryOC always is worth it, because it is connected to cache in some way or another. Even when L3 cache is full , DRAM is utilized
BAR mode also utilizes DRAM and windows 11 utilizes NVMEs as another place when DRAM is full

Both
I always test latency first, if it improves ~ then bandwidth 
If bandwidth didn't, then something is offsync. But if latency is consistent ~ it was a testing variance
Low timings improve dram efficiency. This is key
A good set has good efficiency too, soo will deliver low latency - values are only virtual placeholders. Numbers lower doesn't mean better
But higher means nearly always "worse" 

Never really watched bandwidth unless it really crashed strongly
It either is inside testing variance or it sinks strongly by 1000-2000MB/s 
Bandwidth will always improve if the set is consistent. Latency will mostly show first if it was a good or bad change. And many tests will show if latency was fake or consistent


----------



## gled_fr

Audioboxer said:


> It seems in most cases you've basically got to start all over again. I guess that is what drives some of the regular posters mad, over 500 pages of people probably coming in saying "GDM off won't work but my settings with it on pass 8+ hours of MemTest5"
> 
> You've got an Asus board on same BIOS as me, check for me if you can boot RttPark 3 at some point. As you can see from here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread most posters using DR end up going 6/3/3. You could try the settings on that post, but never expect mem settings to just be plug and play, rarely that simple.
> 
> I can't boot RttPark 3 no matter what I do. I'm hoping it's just this Patch A of the Asus Bios we have and Patch B fixes it.
> 
> Your memory is basically a better binned version of mine so it will be interesting to see where you end up. Have you tried going for CL14 at 3800? With that binning it could be do-able.


I was able to boot those exact settings a bit earlier. I think I had to hard reset once ( black screen after bios ) and then it booted fine in windows, lots of errors in tm5. I may just go back to those settings and try to see the error codes in the sheet link you gave me !

I did try in the past cl14 and 16 was the best I could go without errors.
I shall retry with GDM on just for fun.


----------



## Audioboxer

gled_fr said:


> I was able to boot those exact settings a bit earlier. I think I had to hard reset once ( black screen after bios ) and then it booted fine in windows, lots of errors in tm5. I may just go back to those settings and try to see the error codes in the sheet link you gave me !


You managed to boot GDM off 1T above without adding any values into the Setup's. I don't know enough about these values other than it seems quite a lot of people need to use them when it comes to GDM off 1T. Maybe don't add anything if you don't need to. But as I said I don't know enough about them.

Does this mean you also booted RttPark on 3 earlier? Or did you leave your Rtt settings on auto?


----------



## gled_fr

Audioboxer said:


> You managed to boot GDM off 1T above without adding any values into the Setup's. I don't know enough about these values other than it seems quite a lot of people need to use them when it comes to GDM off 1T. Maybe don't add anything if you don't need to. But as I said I don't know enough about them.
> 
> Does this mean you also booted RttPark on 3 earlier? Or did you leave your Rtt settings on auto?


I did set everything manually like shown on paih85 screenshot, rtt and voltages included. Too bad it was not stable. I shall try to stabilize it.


----------



## Audioboxer

gled_fr said:


> I did set everything manually, rtt and voltages included


Hmm, thanks, dunno what that means for my memory sticks then, they simply won't boot with RttPark 3. I even reset the bios and put them on 3600/1800. 

Best of luck as well, I'm sure you'll get there!


----------



## gled_fr

Audioboxer said:


> Hmm, thanks, dunno what that means for my memory sticks then, they simply won't boot with RttPark 3. I even reset the bios and put them on 3600/1800.
> 
> Best of luck as well, I'm sure you'll get there!


Thanks, I am sure you'll get it too 

Let me know if you want me to test something else for you, I f unfortunately don't know enough to help at this point... it's mostly shots in the dark with a tiny understanding.


----------



## Audioboxer

gled_fr said:


> Thanks, I am sure you'll get it too
> 
> Let me know if you want me to test something else for you, I f unfortunately don't know enough to help at this point... it's mostly shots in the dark with a tiny understanding.


You seem to have good binned b-die memory so I wouldn't be surprised if once you get going you end up with really good results. As I said I wouldn't even rule out giving CL14 a go.

It was just RttPark 3 thanks. Most people I've been speaking to over last pages aren't on Asus boards and one other poster had mentioned AGESA V2 PI 1.2.0.3 Patch A caused issues booting RttPark 3. Patch B is out now but Asus haven't updated all their mobos yet.


----------



## reddify

@Veii 
Thanks a lot for the detailed reply, much appreciated


----------



## XPEHOPE3

mongoled said:


> ive updated my previous post with my "24/7" settings


Thx. But too much changes to ascertain that it was tPHYRDL what gave ns drop.


Audioboxer said:


> but it did get me the furthest yet
> 2 hours in, error on 13.


Please, don't stop TM5 prematurely, let it run and collect more errors. Some error descriptions say explicitly that there are connected errors, even in specific order.


gled_fr said:


> It's funny relaxing tras and trc improved latency.


It was tRFC drop which gave you latency drop.


----------



## craxton

Veii said:


> Happy to see you succeeded your goal
> I hope you also healed and feel better now


yes, me too!! completly re ran TM5 last night while running FURMARK
and to my surprise SD/DD values being fixed cause nomore issues and removed that extra HALF
and HOUR time to test i was seeing. Thinking i had some kind of bug/error not being shown.
(i didnt run hwinfo this round, nor did i shut off background tasks) but none the less 10% usage
at desktop is "good" enough to know most of my "ram" is being hit as hard as TM5 can hit it.

at this point, with that 90mm fan hitting 100% at all times ive gotten used to it to i cant even tell its in there by now.
the GPU/Case fans are quite a bit louder by a margin.

yes, as a matter of fact today ive felt back to 100%.


Spoiler



to which the past few days ive just "played" cold war zombies and had no crashes which is strange to say the least
but regardless 9 days of "bleh and ugh" for some good news upon return to work for a promotion, to which were moving
so idk how well thatll go....
















mongoled said:


> Or don't change any settings, turn off PC from PSU and simply switch your dimm positions then retest to see if anything changes


100% agreed thats one thing i FORGOT to mention is that @XPEHOPE3 
mentioning (i think was him) to check and see if your "better" dimms were in slots A2/B2 as the better
set needs to be in those slots (normally) thats one of two things i know helped, along with the added fan, and RTTpark/4 from /3



mongoled said:


> Shame you are doing this on Windows 11 as we cant do a more direct comparisson with your TM5 time.


i honestly dont know for sure if its WIN11 or not, id have to assume its due to leaving "synapse, cfos speed, msi AB, PX1 etc"
running in the background causing my time to "rise" but upon this last test session it ended at 3:01 
ive not ran the test on win 10 however, tho i suppose i can give it a try since all those same programs
run at startup just the same as win 11 i run now. 

@Audioboxer 
read the first "quote" to mongoled i wrote, i have "4x8, but theyre not a "4x8" set
theyre all the same sticks, but leaving twrrd auto shows slots A1/B1 auto to 3 and A2/B2 auto to 4 
swapping this reversed it to A1/B1 4 and A2/B2 3 so i manually set 3 now. 
but before swapping these sticks i was having alot of issues with just the 90mm fan blowing on the dimms 
at 1.54v in bios (1.528 reported) swapping along with what ive mentioned (also above in this same post)
RTTpark/4 from rttpark 3 gave just enough headroom that (most my other settings from my previous 4000/2000 (rtt/proc settings)
worked just fine. so if you have a previous "stable" selection start by just swapping ONE setting at a time.

several swaps can give you alot of grey hair and make you "tap-out" rather quickly as i did 
for a week or more. but seeing those with sticks that i know for sure "are lesser" than what my sticks now do
i knew these t-force sticks had it in them to run c14-14 flat, it was just me making big chages/to many at one time.
(if you go back several pages youll see Xpehope3 (i think) mention about some timings being "higher like from 14 to 17 means its "lesser"
and from 14 to 17 making it "harder to run" as its "faster" so find that post/comment itll help as 
SCL/DD/SD can (will) make it easier/harder to get what your after.


----------



## Audioboxer

craxton said:


> yes, me too!! completly re ran TM5 last night while running FURMARK
> and to my surprise SD/DD values being fixed cause nomore issues and removed that extra HALF
> and HOUR time to test i was seeing. Thinking i had some kind of bug/error not being shown.
> (i didnt run hwinfo this round, nor did i shut off background tasks) but none the less 10% usage
> at desktop is "good" enough to know most of my "ram" is being hit as hard as TM5 can hit it.
> 
> at this point, with that 90mm fan hitting 100% at all times ive gotten used to it to i cant even tell its in there by now.
> the GPU/Case fans are quite a bit louder by a margin.
> 
> yes, as a matter of fact today ive felt back to 100%.
> 
> 
> Spoiler
> 
> 
> 
> to which the past few days ive just "played" cold war zombies and had no crashes which is strange to say the least
> but regardless 9 days of "bleh and ugh" for some good news upon return to work for a promotion, to which were moving
> so idk how well thatll go....
> 
> 
> 
> View attachment 2517665
> 
> 
> 
> 
> 
> 100% agreed thats one thing i FORGOT to mention is that @XPEHOPE3
> mentioning (i think was him) to check and see if your "better" dimms were in slots A2/B2 as the better
> set needs to be in those slots (normally) thats one of two things i know helped, along with the added fan, and RTTpark/4 from /3
> 
> 
> i honestly dont know for sure if its WIN11 or not, id have to assume its due to leaving "synapse, cfos speed, msi AB, PX1 etc"
> running in the background causing my time to "rise" but upon this last test session it ended at 3:01
> ive not ran the test on win 10 however, tho i suppose i can give it a try since all those same programs
> run at startup just the same as win 11 i run now.
> 
> @Audioboxer
> read the first "quote" to mongoled i wrote, i have "4x8, but theyre not a "4x8" set
> theyre all the same sticks, but leaving twrrd auto shows slots A1/B1 auto to 3 and A2/B2 auto to 4
> swapping this reversed it to A1/B1 4 and A2/B2 3 so i manually set 3 now.
> but before swapping these sticks i was having alot of issues with just the 90mm fan blowing on the dimms
> at 1.54v in bios (1.528 reported) swapping along with what ive mentioned (also above in this same post)
> RTTpark/4 from rttpark 3 gave just enough headroom that (most my other settings from my previous 4000/2000 (rtt/proc settings)
> worked just fine. so if you have a previous "stable" selection start by just swapping ONE setting at a time.
> 
> several swaps can give you alot of grey hair and make you "tap-out" rather quickly as i did
> for a week or more. but seeing those with sticks that i know for sure "are lesser" than what my sticks now do
> i knew these t-force sticks had it in them to run c14-14 flat, it was just me making big chages/to many at one time.
> (if you go back several pages youll see Xpehope3 (i think) mention about some timings being "higher like from 14 to 17 means its "lesser"
> and from 14 to 17 making it "harder to run" as its "faster" so find that post/comment itll help as
> SCL/DD/SD can (will) make it easier/harder to get what your after.


Thanks for tips. I'm in slot A2/B2. I've tried swapping the sticks around in these slots, but I haven't experimented with A1/B1.

I've got a super loose "mess" of settings stable at flat 16's GDM off 2T, the fun has really kicked off trying to get flat 15's stable lol. Up next is the battle for 1T if I get there 

As advice above I'm going to start letting TestMem run out, instead of bailing when errors start popping. As long as it doesn't BSOD obviously.


----------



## XPEHOPE3

craxton said:


> 100% agreed thats one thing i FORGOT to mention is that @XPEHOPE3
> mentioning (i think was him) to check and see if your "better" dimms were in slots A2/B2 as the better
> set needs to be in those slots (normally) thats one of two things i know helped


I actually said the reverse: better sticks should be in worse slots (A1/B1) as those, I think, are powered "after", and thus "worse" than, A2/B2 slots. But I remember I edited that post because at first I wrote as you said 🤣
And regarding tWRRD being 4 on one channel and 3 on another, I sometimes saw tRDWR switch when I tried different setting, and returned back. Also I saw situation with tRDWR 9/8 failing TM5, but setting tRDWR to 9 fixed issue. But in your case tWRRD seemed to need to be lower to fulfil tWRRD <= rounddown(tRCD_avg/tWRWRSCL).



Audioboxer said:


> I'm in slot A2/B2. I've tried swapping the sticks around in these slots, but I haven't experimented with A1/B1.


Since you only have 2 sticks you should only use them in the slot pair recommended by your mobo manual, which is usually A2/B2.


----------



## PJVol

Sphex_ said:


> Idk what kit you have but these were literally plug n play for me. Thanks for the Timings bro!


Mine is with b-die chips, don't know what pcb revision is, binned at 17-18-18-38 @ 1.35V.


----------



## gled_fr

Audioboxer said:


> Argh, almost
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 2 hours in, error on 13.
> 
> I decided earlier to have one last YOLO pending waiting on ASUS releasing patch B bios for this board and seeing if I could get RttPark 3. So I took @XPEHOPE3 voltage settings, stuck 40 on ClkDrvStr and grabbed a load of settings I was trying a day ago. Good news is I'm not getting the 12 errors I was getting before, I'm guessing pumping voltages took care of that. Bad news is 13 is a new error for me lol
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> As for RAM over heating
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> VDIMM is 1.46V.
> 
> Would RttNom 6 be classed as stronger than 7?


I had the same error earlier, solved by lowering my ClkDrvStr and my procodt


----------



## gled_fr

Thanks to you guys, this is what seems to be stable now:








GDM off, CL15. 
CL14 with those settings => windows just bluescreen.

Now if i read correctly, seems like tras is too high ( tras = trcd + trtp ), and thus trc is too high too. Gonna try that next, along with trying to lower further trfc.

Seems like I also need to work on trefi, which is not modifiable on amd if i understand correctly ?

Ahh so much more reading to do, but huge progress already, thanks everyone ! Taking more advices if you have of course


----------



## spajdr

Any tips? I'm not planning to go higher with FCLK, but would like to get this stable.
RAM voltage is 1.45V


----------



## gled_fr

spajdr said:


> Any tips? I'm not planning to go higher with FCLK, but would like to get this stable.
> RAM voltage is 1.45V
> 
> View attachment 2517685


this error codes list says it could be voltage or proc_odt wrong.

Check also if you don't have WHEA errors due to the IF running at 2Ghz ( OCCT will tell you if you run a mem stability test if that's the case )


----------



## spajdr

Thanks for the link @gled_fr 
No WHEA errors so far, I spent a lot of time to tune voltages 
If it's not ProcODT issue then I'm afraid that lowering VDDP or VSOC could make WHEA errors to appear, will test.


----------



## gled_fr

spajdr said:


> Thanks for the link @gled_fr
> No WHEA errors so far, I spent a lot of time to tune voltages
> If it's not ProcODT issue then I'm afraid that lowering VDDP or VSOC could make WHEA errors to appear, will test.


I wish I was able to get the IF stable at 2Ghz 

PS: thanks Audioboxer for the link


----------



## KedarWolf

This is on my MSI B550 Tomahawk I'm using as a placeholder until the MSI Repair Centre fixes my Unify-X they've had 45 days. :/


----------



## craxton

Audioboxer said:


> but I haven't experimented with A1/B1.


as you already were told, dont bother with swapping to A1/B1 its only gonna help
(maybe help) if your running 4x8 SR to which your running DR dimms. my bad.



XPEHOPE3 said:


> I actually said the reverse: better sticks should be in worse slots (A1/B1) as those, I think, are powered "after", and thus "worse" than, A2/B2 slots. But I remember I edited that post because at first I wrote as you said


i dont recall now how it was put, but im pretty sure how i put it is what you said. 
to which i did put the "better" sticks in A2/B2 
and that helped me before i even "got stable" with lowering errors somehow. 
i did have "one good/one worse" paired for the 4000/2000 c16-16 on my 5600x and had no issue 
but this 5800x wont do past 1900fclk without screaming its lungs out and having issues with 
USB dropouts, display dropouts, strange STRANGE stuff.....



KedarWolf said:


> This is on my MSI B550 Tomahawk I'm using as a placeholder until the MSI Repair Centre fixes my Unify-X they've had 45 days


what happened to the unify? 
the tomahawk is identical to the gaming edge in most senses, and 
i think its a pretty good board minus having a locked bios. 
which i do have PBS open (only PBS at this time) no amd overclocking section.
which eder is workin on/i think? idk wrote and said hed send me a few things, i mentioned placing 
in his gdrive and ill see it and there was a bios file so i gave it a shot. 

here  is a direct link if you aim to try a "better" bios.
unless you already unlocked it yourself?


----------



## XPEHOPE3

craxton said:


> to which i did put the "better" sticks in A2/B2


How did you determine those were better sticks? Due to tWRRD timing difference alone?


----------



## PJVol

mongoled said:


> Here is a Sisoft Sandra result


Idk, just run overall benchmark and there are some kPT's evrywhere )) and no Gb/s as in yours. May be I need to register or buy? How can I compare it?
Here's the result itself:








Details for Result ID ASRock B550 Extreme4 (AMD Ryzen 5 5600X 6-Core Processor; AMD F19 Host Bridge; 2x 8GB DDR4 PC4-28800; AMD Radeon RX 5700 XT; Samsung SSD 970 EVO Plus 1TB)







ranker.sisoftware.co.uk


----------



## KedarWolf

Is this latency any good? Waits for peeps to catch on, and no, not photoshop.


----------



## KedarWolf

This on a motherboard that cost me $150 Canadian dollars.


----------



## Akex

KedarWolf said:


> This on a motherboard that cost me $150 Canadian dollars.
> 
> View attachment 2517730
> 
> 
> View attachment 2517732


@Veii explains that it is not a good idea to run with safe mode. Here is the explanation at the bottom of the post > [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## Audioboxer

gled_fr said:


> Thanks to you guys, this is what seems to be stable now:
> View attachment 2517682
> 
> 
> GDM off, CL15.
> CL14 with those settings => windows just bluescreen.
> 
> Now if i read correctly, seems like tras is too high ( tras = trcd + trtp ), and thus trc is too high too. Gonna try that next, along with trying to lower further trfc.
> 
> Seems like I also need to work on trefi, which is not modifiable on amd if i understand correctly ?
> 
> Ahh so much more reading to do, but huge progress already, thanks everyone ! Taking more advices if you have of course


I'd try running the 1usmus_v3 profile like most people in here do, as you can see from 1 of my errors I got it over 2 hours in lol. The error sheet is also based on the 1usmus_v3 profile, anta777 while a good test to also run IIRC doesn't line up with the error sheet. So harder to diagnose.

My goal is 25 cycles stable in 1usmus_v3, then y-cruncher and finally a 9~12 cycle overnight of anta777 extreme. Won't run anything longterm if there is even a single error.

Trying again now with some changes to ProcODT and ClkDrvStr.

As I can see you can boot RttPark 3 fine. For anyone knowledgeable in this topic what could be reasons for RAM not wanting to boot anything but RttPark 1? I've tried 3600/1800, tried default BIOS settings, tried 1T/2T, tried swapping sticks and now even tried other dimm slots just for the hell of it. My b-die DR just refuses to post on RttPark 2/3 lol.


----------



## Veii

Akex said:


> @Veii explains that it is not a good idea to run with safe mode. Here is the explanation at the bottom of the post > [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


KedarWolf is a long time with us, he knows how to benchmark and optimize windows
Don't think he needs to run it on SafeMode, but maybe it had a comparison reason


KedarWolf said:


> Is this latency any good? Waits for peeps to catch on, and no, not photoshop.


Bet you can not beat this 








Bugs, lovely lovely bugs (19/29/2020)


craxton said:


> for some good news upon return to work for a promotion


I hope it's a significant one 
Glad you're doing better~


----------



## mongoled

Audioboxer said:


> Hmm, thanks, dunno what that means for my memory sticks then, they simply won't boot with RttPark 3. I even reset the bios and put them on 3600/1800.
> 
> Best of luck as well, I'm sure you'll get there!


When you switched the dimms did you try to boot with a different RttPark or did you just try to run TM5 ??



XPEHOPE3 said:


> Thx. But too much changes to ascertain that it was tPHYRDL what gave ns drop.


I am 90% confident that the change is from tPHYRDL, very easy to test, will just set tCL to 15 from 14, values that have to be changed will be changed i.e. tRDWR/tWRRD and tCWL as the PC will not post if left at same values (tRDWR/tWRRD)



craxton said:


> ...snip @Audioboxer
> read the first "quote" to mongoled i wrote, i have "4x8, but theyre not a "4x8" set
> theyre all the same sticks, but leaving twrrd auto shows slots A1/B1 auto to 3 and A2/B2 auto to 4
> swapping this reversed it to A1/B1 4 and A2/B2 3 so i manually set 3 now.
> but before swapping these sticks i was having alot of issues with just the 90mm fan blowing on the dimms
> at 1.54v in bios (1.528 reported) swapping along with what ive mentioned (also above in this same post)
> RTTpark/4 from rttpark 3 gave just enough headroom that (most my other settings from my previous 4000/2000 (rtt/proc settings)
> worked just fine. so if you have a previous "stable" selection start by just swapping ONE setting at a time.
> 
> several swaps can give you alot of grey hair and make you "tap-out" rather quickly as i did
> for a week or more. but seeing those with sticks that i know for sure "are lesser" than what my sticks now do
> i knew these t-force sticks had it in them to run c14-14 flat, it was just me making big chages/to many at one time.
> (if you go back several pages youll see Xpehope3 (i think) mention about some timings being "higher like from 14 to 17 means its "lesser"
> and from 14 to 17 making it "harder to run" as its "faster" so find that post/comment itll help as
> SCL/DD/SD can (will) make it easier/harder to get what your after.


 😀


XPEHOPE3 said:


> How did you determine those were better sticks? Due to tWRRD timing difference alone?


Best way to determine is to test the sticks independantly, for me this is a must if you are running 4 sticks.

Thats why I have to run [email protected] as three of the four sticks can do it @14 but one of them cant



I had a hard lock when running TM5 last night on settings that had previously passed, only difference was that I set "Power Supply Idle Current" to AUTO from "Typical"

Looks like agesa 1.2.0.3b has re-introduced issues that had been ammended in previous BIOS ...


----------



## mongoled

PJVol said:


> Idk, just run overall benchmark and there are some kPT's evrywhere )) and no Gb/s as in yours. May be I need to register or buy? How can I compare it?
> Here's the result itself:
> 
> 
> 
> 
> 
> 
> 
> 
> Details for Result ID ASRock B550 Extreme4 (AMD Ryzen 5 5600X 6-Core Processor; AMD F19 Host Bridge; 2x 8GB DDR4 PC4-28800; AMD Radeon RX 5700 XT; Samsung SSD 970 EVO Plus 1TB)
> 
> 
> 
> 
> 
> 
> 
> ranker.sisoftware.co.uk


Ooooouuuu

Ive never seen that before!

Had to Google what kPT is and could not find anything!

Those runs I did are not registered, just installed and ran it, I had previously registered an account but cant remeber the password 🤣


----------



## Akex

Veii said:


> KedarWolf is a long time with us, he knows how to benchmark and optimize windows
> Don't think he needs to run it on SafeMode, but maybe it had a comparison reason
> 
> Bet you can not beat this
> View attachment 2517737
> 
> Bugs, lovely lovely bugs (19/29/2020)
> 
> I hope it's a significant one
> Glad you're doing better~


Sorry ^^


----------



## Audioboxer

mongoled said:


> When you switched the dimms did you try to boot with a different RttPark or did you just try to run TM5 ??
> 
> 
> I am 90% confident that the change is from tPHYRDL, very easy to test, will just set tCL to 15 from 14, values that have to be changed will be changed i.e. tRDWR/tWRRD and tCWL as the PC will not post if left at same values (tRDWR/tWRRD)
> 
> 
> 😀
> 
> Best way to determine is to test the sticks independantly, for me this is a must if you are running 4 sticks.
> 
> Thats why I have to run [email protected] as three of the four sticks can do it @14 but one of them cant
> 
> 
> 
> I had a hard lock when running TM5 last night on settings that had previously passed, only difference was that I set "Power Supply Idle Current" to AUTO from "Typical"
> 
> Looks like agesa 1.2.0.3b has re-introduced issues that had been ammended in previous BIOS ...


I tried RttPark 2/3. Simply will not post lol.

I guess I could try 4, but I haven't seen anyone run 4.

At this point I'm literally holding out that 1.2.0.3a doesn't like it which one poster mentioned. Though gled_fr almost has the same mobo as me, on the same bios revision and with DR b-die and can post RttPark 3 fine.

They're running in A1/B1, me, primarily A2/B2, but as I said I tried RttPark 3 on A1/B1 as well.

Gonna take some pictures of my memory shortly and see if anyone can figure out what PCB it is, I did forget to do that in last day or two for Veii after they mentioned it.


----------



## mongoled

Well I would hold off doing futher testing until you can work out what going on with your RttPark, have you tried falling back to an earlier BIOS just to test RttPark ?


----------



## Audioboxer

mongoled said:


> Well I would hold off doing futher testing until you can work out what going on with your RttPark, have you tried falling back to an earlier BIOS just to test RttPark ?


Forgive me for being an idiot but I didn't think I could do that  BIOS updates have been one way traffic for me for a long time.

I've got a test running just now so as soon as it's finished I will look into that.


----------



## gled_fr

Audioboxer said:


> As I can see you can boot RttPark 3 fine. For anyone knowledgeable in this topic what could be reasons for RAM not wanting to boot anything but RttPark 1? I've tried 3600/1800, tried default BIOS settings, tried 1T/2T, tried swapping sticks and now even tried other dimm slots just for the hell of it. My b-die DR just refuses to post on RttPark 2/3 lol.


I have a mini itx board, maybe the difference is just pcb ? There's only 2 dimms slots on my mb and the traces are probably shorter ?


----------



## mongoled

Sisoft Sandra database is such a mess!!

At least it looks that way to me.

Check this out, the below link contains the aggregate results for "all" CPUs in the category "Inter Thread Efficiency", I have gone to the page that has results from 140 - 154 that should contain one of my scores but it is not there !








Top Processor Inter-Thread Efficiency Ranks







ranker.sisoftware.co.uk





This is the score I am talking about, 88.40GB/s








Details for Result ID AMD Ryzen 5 5600X 6-Core Processor (6C 12T 4.85GHz, 1.9GHz IMC, 6x 512kB L2, 32MB L3)







ranker.sisoftware.co.uk





Maybe the ranker only shows results that are part of a "Team" ....
Nope its not that, ive found one of my old registered results








Details for User mongoled







ranker.sisoftware.co.uk





Not in the "main" ranking ....

Now to find out what password I used ....
Nothing to do with the password, my username is an "unacceptable" word ....


----------



## Audioboxer

gled_fr said:


> I have a mini itx board, maybe the difference is just pcb ? There's only 2 dimms slots on my mb and the traces are probably shorter ?


Ah, I didn't notice that was the difference between I and F X570 Gaming.

I'm going to try a BIOS with AM4 AGESA V2 PI 1.2.0.1 Patch A.


----------



## Audioboxer

mongoled said:


> Well I would hold off doing futher testing until you can work out what going on with your RttPark, have you tried falling back to an earlier BIOS just to test RttPark ?


I've managed to get RttPark 3 posting and double-checked it on A1/B1 and A2/B2. But it required me to set the DDR4 speed to DDR4-2133.

I even default setting the whole BIOS and just tried running DOCP, which obviously posts, but then when manually selecting 6/3/3 it won't post again.

Not really sure what this tells me.... I'm going to save my updated profiles to a USB stick and now try rolling back to an older BIOS verison.

@Veii Not sure how helpful these pictures are but here is my memory for PCB


Spoiler


----------



## Veii

Audioboxer said:


> @Veii Not sure how helpful these pictures are but here is my memory for PCB
> 
> 
> Spoiler


Last Picture is kind of usable
But rather make a birdview type of picture with more light (illuminating the traces ~ soo they reflect back light)
and from both sides of the dimm - because this is Dual Rank
You do not know which side is the primary and which is the back of it

It looks like typical A2, depends on the other side
EDIT:
Sadly this side is too blurry








can not differentiate A2 from A1 or even A3

EDIT2:
Not every cam / lense can focus up close ~ soo a further one is fine too
But something like this - the traces reflect back the light
This here is an A0 ~ a custom but it's A0


Spoiler






















If you can check the traces, you don't have to remove the heatsink
Just for dual rank, you have to check both sides ~ which of them is the primary one


----------



## XPEHOPE3

mongoled said:


> Counting from left to right
> 
> Best pair dimm stick 1 = BP1
> Best pair dimm stick 1 = BP2
> Worse pair dimm bad stick = WPB
> Worse pair dimm good stick = WPG
> 
> 1 -------- 2 -------- 3 -------- 4
> BP1 --- WPB --- BP2 --- WPG
> 
> Thats how I have them ordered, may help also...


@craxton my recommendation for putting best pair of sticks to worse slots was based on this post. @mongoled did I interpret you right? Are the slots on your diagram A1-A2-B1-B2?



mongoled said:


> Best way to determine is to test the sticks independantly, for me this is a must if you are running 4 sticks.


Do you only test frequency, primaries and VDIMM to determine stick order? Or do you go all the way and variate other voltages, resistances and other than primary timings? From what I gather at first you are testing 2 pairs separately, then test two sticks from worst pair separately. That is 4 times the usual memory OC process =/ I'm asking did you find any way to speed up the process? I'd appreciate a thorough guide 🤓
BTW since you test 4 times anyway, why won't you test just each individual stick?


----------



## mongoled

@XPEHOPE3

Below is meant to signify only a change to tCL, but obviously other values have to be changed otherwise no post.

So tCWL, tRDWR & tWRRD were set to AUTO values,

everything else is identical

tCL is 15 in the first screenshot and 14 in the second screenshot
tCWL is 14 in the first screenshot and 12 in the second screenshot (has to change to the next optimum tCWL value)
tRDWR is 9 in the first screenshot and 10 in the second screenshot (has to change to the next optimum tRDWR value)
tWRRD is 4 in the first screenshot and 1 in the second screenshot (has to change to the next optimum tWRRD value)















From the above,

AIDA64 L1 latency improves when using tCL @15 instead of @14
DRAM Memtest improves when using tCL @15 instead of @14
Sisoft Sandra seems to within margin of error, though there is a distinct change in U0-C0T0 <> U2-C1T0 Data Latency

So why the improvement ? It looking that tPHYRDL is directly effecting the result, only way to really confirm it is to be able to force it to train at 26 when using tCL set to 14 but I have not found a way to achieve that!


----------



## Audioboxer

Veii said:


> Last Picture is kind of usable
> But rather make a birdview type of picture with more light (illuminating the traces ~ soo they reflect back light)
> and from both sides of the dimm - because this is Dual Rank
> You do not know which side is the primary and which is the back of it
> 
> It looks like typical A2, depends on the other side
> EDIT:
> Sadly this side is too blurry
> 
> 
> 
> 
> 
> 
> 
> 
> can not differentiate A2 from A1 or even A3
> 
> EDIT2:
> Not every cam / lense can focus up close ~ soo a further one is fine too
> But something like this - the traces reflect back the light
> This here is an A0 ~ a custom but it's A0
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2517740
> 
> View attachment 2517741
> 
> 
> 
> If you can check the traces, you don't have to remove the heatsink
> Just for dual rank, you have to check both sides ~ which of them is the primary one


Tried to get some better lighting, any of these easier to work with?


Spoiler










































When you say traces do you mean the small bits of metal?

I'll get some better pictures, I took the above before seeing your example.


----------



## mongoled

XPEHOPE3 said:


> @craxton my recommendation for putting best pair of sticks to worse slots was based on this post. @mongoled did I interpret you right? Are the slots on your diagram A1-A2-B1-B2?
> 
> Do you only test frequency, primaries and VDIMM to determine stick order? Or do you go all the way and variate other voltages, resistances and other than primary timings? From what I gather at first you are testing 2 pairs separately, then test two sticks from worst pair separately. That is 4 times the usual memory OC process =/ I'm asking did you find any way to speed up the process? I'd appreciate a thorough guide 🤓
> BTW since you test 4 times anyway, why won't you test just each individual stick?


E7C35v2.1.pdf (msi.com) page 5, and yes, order is correct as per my diagram

A1 ----- A2 ------- B1 ----- B2
BP1 --- WPB --- BP2 --- WPG

Best pair dimm stick 1 = BP1
Best pair dimm stick 2 = BP2
Worse pair dimm bad stick = WPB
Worse pair dimm good stick = WPG

I also did it the long way, brief explanation, as I did not buy my 2 pairs of sticks at the same time I found settings that were stable for the 1 pair, these were 14-14-14-14-1T.

When I got the second pair I simply chucked them in and tried to run at the same settings which failed.

From these I started testing the new pair in the same manner I tested the first pair.

Through this testing I found out that the new pair were not as good as the second pair, so I tested each dimm separately.

Testing was real quick using TM5, just set tRCDRD to 14 and see what would happen, after an hour a so of playing I found that tRCDRD @14 was not possible, whatever I changed with regards to powering the dimm, voltages, resistences etc, all I could achieve was shifting where the errors would appear.

Once I set tRCDRD to 15 TM5 would pass at a breeze without having to play with other settings.

I simply used my 24/7 settings for the good pair, dropped tRCDRD to 15, then did any fine tuning that was needed


----------



## XPEHOPE3

@mongoled
So... you've got your good kit in A2/B2 originally, got bad kit, put it to A1/B1, found that tRCDRD 14 isn't stable anymore, switched sticks according to your method and again found that tRCDRD 14 isn't stable. Meaning switching sticks might not have provided any benefit compared to running relaxed settings with original stick order of bad-good-bad-good. Am I missing something?

Also I thought it's strange that tCL=tCWL+2 runs easier than tCL=tCWL, as "how can running tighter timing can be easier?". But you seem to agree with Nighthog on this.


----------



## spajdr

Hello guys again 
still struggling with FCLK 2000/MCLK 200
What I did found, can't go lower on ProcODT than 36.9 otherwise PC will not boot.
min. VSOC voltage must be set to 1.08750 V otherwise WHEA error
ClkDrvStr changed from 40 to 24
CLDO VDDP changed from 0.9500V to 0.900V - made no difference
VDDG CCD changed from 1.050V to 0.960V (just found this needs to be higher than 0.960V, otherwise WHEA error again).
As you can see error is still number 6, but sporadically I can also spot error number 0.
Any tips would be greatly welcome.


----------



## XPEHOPE3

spajdr said:


> As you can see error is still number 6, but sporadically I can also spot error number 0.


From Veii's error descriptions and from your timings one can suspect wrong tRDWR and tWRRD. tRDWR should be at least 10 for you, but most probably 11. tWRRD might be good according to Veii's rules, but for 4 dimms it might also need a bump to 4 or 5.
Try setting on Auto both settings and see what the board would recommend.


----------



## deadfelllow

Hello guys i need advice for sub timings

I have a Crucial Ballistix RGB CL16 kit BL8G36C16U4BL,M8FE1

Micron Rev.E C9BLM A2 LAYER










I have those timigs and my system is %100 stable for an hour i also tested before 2 hours of memtes5 1usmus config it was stable as well.

cant lower tRFC 
also tRC
trdds
trddl
tfaw also good
maybe i can try to change tWR

Now which timings shoud i change.

I tried to change tRP 12 tRAS 21 it wasnt stable i got errors instant.

Maybe i can change tCWL to 13 or 12

I also have 4x8 sticks(ALL SR) I cant do stable 3800 because of 4x8 stick config i also have bad motherboard which is Asus prime B550m-k

And Advices?

Thanks.


----------



## spajdr

@deadfelllow for a start, enable GDM.


----------



## spajdr

XPEHOPE3 said:


> From Veii's error descriptions and from your timings one can suspect wrong tRDWR and tWRRD. tRDWR should be at least 10 for you, but most probably 11. tWRRD might be good according to Veii's rules, but for 4 dimms it might also need a bump to 4 or 5.
> Try setting on Auto both settings and see what the board would recommend.


Thanks for the tip 
Auto settings set it to 9 and 3, I tried to set it manually to 11 and 5 (tRDWR/tWRRD) but sadly no difference. Still error 6.


----------



## deadfelllow

spajdr said:


> @deadfelllow for a start, enable GDM.


why?

i have tcl at 14 and stable.

what is the benefits of gdm?


----------



## mongoled

spajdr said:


> @deadfelllow for a start, enable GDM.


For a start we don't do that here

😝

GDM can help those who want quick shortcuts but it impacts performance (slightly) and masks issues


----------



## XPEHOPE3

spajdr said:


> enable GDM.


People with GDM enabled rarely if ever get help here. Most of the knowledge here (incl. the error descriptions above) gets accumulated on GDM off setups.

@deadfelllow 
5 cycles of 1usmus_v3 config are not enough to ascertain stability. 25 is recommended, no less than 20.
How did you know you can't lower tRFC? Wasn't it posting or was it not stable? 
Also did you try using SD/DD timings 1-5-5-1-7-7 or 1-5-4-1-7-6? Those when higher actually might enhance performance. But can easily prevent posting or stability.

Also you get tPHYRDL 28 from training and who knows how much it is on your B memory channel (check in ZenTimings please). You might be better off relaxing some of the timings (for example, tCL to 15 just like @mongoled did some posts above, or tRRD_/tFAW back to like 6/8/24) to make tPHYRDL get trained to 26/26 setup (for A/B memory channels). That should improve Aida latency if you are after that.

Also I thought to point you to this list, but you've already beaten every 4*8 Micron there Or rather would beat when you pass longer TM5 stability test and maybe y-cruncher test


----------



## mongoled

XPEHOPE3 said:


> @mongoled
> So... you've got your good kit in A2/B2 originally, got bad kit, put it to A1/B1, found that tRCDRD 14 isn't stable anymore, switched sticks according to your method and again found that tRCDRD 14 isn't stable. Meaning switching sticks might not have provided any benefit compared to running relaxed settings with original stick order of bad-good-bad-good. Am I missing something?
> 
> Also I thought it's strange that tCL=tCWL+2 runs easier than tCL=tCWL, as "how can running tighter timing can be easier?". But you seem to agree with Nighthog on this.


Will get back to you on this later ..


----------



## spajdr

@XPEHOPE3 Ok, surprised that I got some help here then  because I have various issues with GDM disabled above 3600Mhz.
Suppose I will stay at 1967 FCLK then and 56.5ns being reported in AIDA64.
Getting FCLK/MCLK 2000Mhz stable seems to be real pain in the ass.


----------



## Robostyle

VDDG CCD too low? PBO off, CPU is at stock

or maybe win corrupted already due to my tinkering....


Spoiler: zentim


----------



## Audioboxer

mongoled said:


> Well I would hold off doing futher testing until you can work out what going on with your RttPark, have you tried falling back to an earlier BIOS just to test RttPark ?


So I've spent some time doing some testing mate.

First thing I did was roll back to an earlier BIOS with AM4 AGESA V2 PI 1.2.0.1 Patch A. After this all I did was load BIOS optimized defaults, put RAM on 1.4v and 3800 and rebooted. Obviously posted fine. I then tried RttPark 3, no post.

So I put it down to 3200, which is what RAM is rated for, posted fine. Slowly kept pushing it up and it kept posting till 3400.

Upgraded back to AMD AM4 AGESA V2 PI 1.2.0.3 Patch A (latest BIOS) and did the same thing, and it worked up to 3400 as well. Weird thing is when I was trying to get it to post on this BIOS earlier I was having issues 

So, not sure what to think. I don't think it's AGESA, it must either be my mobo, memory or a combination of the two. Obviously the above testing was with everything on BIOS auto other than VDIMM and the memory frequency. Loaded my safe CL16 GDM Off profile (at 3400 instead of 3800) and here it is booting with 6/3/3










Does anyone know if RttPark hits a higher frequency "block" is it just the RAM quality or something? For now it seems if I go above 3400 I need to be on RttPark 1.

Moving on from this I've driven myself almost insane trying to get flat 15 passing a stability test. Maybe my memory just isn't good enough.










That was the closest I have got and I've driven myself mad making small changes to the right hand side, and loosening some timings, but no go.

I've got CL16 profiles with GDM on that are stable, so for now I guess I'll just focus on improving the timings on my GDM disabled CL16 profile.

Thanks for all the help to the regular posters in here, I've learned a bit and while I might be out of my depth for flat 15, or my memory genuinely not good enough, never say never. I might be back at 15 at some point


----------



## tcclaviger

So I've been tweaking for a bit and this seems to be the best stable configuration I can come up with. Raising FCLK over this to 1866/1933/2000 works, but with WHEAs and 1900 is locked out, will not work with any combination of settings (3900x had the same issue, work around using 1866 with 101.8 bclk). Up at the higher speeds I RAM latency comes down into the 52.x range, anything tighter is no-go on these sticks.

*Where can I squeeze more out of the current FCLK and get latency down to the 52.x range?* I know the RAM is capable, but not sure what/where to adjust from where I'm at to squeeze that last bit out.

Have tried getting GD disabled, cannot exceed 3600 with it disabled.

Have tried messing with ProcODT, RTT, CAD, nothing seems to work better than auto for all these settings.

4x Team Dark Pro 3200C14 sticks, sequential serial numbers, C7H, 5950x

Everything is under water and chilled at 50f water temp at all time, RAM has been happy at 1.5-1.55 for over a year, so it's fine, stays very cool. Ideally I'd prefer to keep the ram under 1.575 daily, but I've found no benefit of going up to 1.575 vs 1.53 or 1.55, it's not enough extra to push timings tighter than this.















I've ordered 4x Patriot Viper Steel Part# PVS416G440C9K to play with and see if I can get better, if not, they'll go in the Linux box. Thoughts on the two different bins and expectations would be appreciated


----------



## craxton

KedarWolf said:


> This on a motherboard that cost me $150 Canadian dollars.
> 
> View attachment 2517730
> 
> 
> View attachment 2517732


Is this win 10 safe mode, or win 11? 
I get some strange issue in win 11 trying safe mode to where an "error" warning pops up and don't go way. Or some kind of popup box.


----------



## craxton

XPEHOPE3 said:


> How did you determine those were better sticks? Due to tWRRD timing difference alone


Nope, due to the fact that the xmp profile 
Although they're the same sticks, same model, same in EVERYWAY except manufacturing dates, says that there's a few timings that have changed from I.E. 45 to 96 (not exact numbers) but yea and from 7-7 to 13-13
Can't post shots of it ATM but they're on here a few pages back several times in fact...
Im running ycruncher c17 atm (only c17) as I keep crashing on test iteration 3 only c17. 
Can't adjust CPU_VDDP so idk how I'm to counter this "easy" ATM on iteration 3 since turning off all other tests, and it just passed. Turning my co down a little helped?.
Maybe I was wrong and it's not c17 crashing. Since iteration 5 is starting now by the time I finished this write up.


----------



## Audioboxer

Looks like CL16 might be more of my skill range lol, and it's possible CL15 is just not going to play nice with this RAM. Ignore any dodgy timings, I just wanted a run with something a bit more sensible than my really loose CL16 profile.

Also for anyone who knows a bit more about b-die than me, I believe these three kits have it

F4-3600C16Q-32GTZN (SR 4x8)
‎F4-4000C16D-32GTZR (DR 2x16)
‎F4-4000C17Q-32GTZR (SR 4x8)

What would technically be "the best" for trying to maximise at 3800?

Cheers


----------



## reddify

Audioboxer said:


> F4-3600C16Q-32GTZN (SR 4x8)
> ‎F4-4000C16D-32GTZR (DR 2x16)
> ‎F4-4000C17Q-32GTZR (SR 4x8)
> 
> What would technically be "the best" for trying to maximise at 3800?
> 
> Cheers


Hi, I can partially answer your question - I have the F4-4000C16D-32GTZR kit running as 3800 CL14 flat.


----------



## Mach3.2

Wild guess, but I'd imagine 2* DR sticks would be _slightly _easier on the IMC as compared to 4* SR sticks, thus "easier" to get 3800 flat 14 timings.


----------



## Audioboxer

reddify said:


> Hi, I can partially answer your question - I have the F4-4000C16D-32GTZR kit running as 3800 CL14 flat.


Thanks! I did try to search before asking in here and the only thing that really caught my eye was an apparent claim that DR RAM can technically come as Hynix but I'm not sure if that's true.


----------



## mongoled

@Audioboxer
Have you tried, just to see, the other RZQs ?

You should try just so you know you have covered your bases.

So try RZQ/7 and work your way down to RZQ/1 just to see if any of the others post.

Your either at the limit of what your combinaton of hardware can achieve or its the powering of the dimms thats holding you back and RttPark is a big part of that.


----------



## reddify

Audioboxer said:


> Thanks! I did try to search before asking in here and the only thing that really caught my eye was an apparent claim that DR RAM can technically come as Hynix but I'm not sure if that's true.


It is CL16-19-19-39, but it is guaranteed Bdie.


----------



## Audioboxer

mongoled said:


> @Audioboxer
> Have you tried, just to see, the other RZQs ?
> 
> You should try just so you know you have covered your bases.
> 
> So try RZQ/7 and work your way down to RZQ/1 just to see if any of the others post.
> 
> Your either at the limit of what your combinaton of hardware can achieve or its the powering of the dimms thats holding you back and RttPark is a big part of that.


I tried 4 a few times but I'll try 5~7. When you say limit of hardware, is that mobo and RAM or RAM only? As you can see above I think I'm going to go shopping for new RAM anyway lol.

I actually have a Corsair Vengeance Pro set lying around to be sold I can actually test with RttPark as well.


----------



## Robostyle

reddify said:


> 3800 CL14 flat.


vDIMM?


----------



## XPEHOPE3

Audioboxer said:


> Ignore any dodgy timings, I just wanted a run with something a bit more sensible than my really loose CL16 profile.


BTW tight secondaries can prevent you from pushing tighter primaries. But your run is still somewhat valuable as research of how tight you can tighten secondaries (in nanoseconds, not cycles).


----------



## mongoled

XPEHOPE3 said:


> @mongoled
> So... you've got your good kit in A2/B2 originally, got bad kit, put it to A1/B1, found that tRCDRD 14 isn't stable anymore, switched sticks according to your method and again found that tRCDRD 14 isn't stable. Meaning switching sticks might not have provided any benefit compared to running relaxed settings with original stick order of bad-good-bad-good. Am I missing something?


Yeah you got it right

one small clarification, its more like

good-bad-good-good
14-----15-----14----14



Just wondering why did you ask if "you were missing something" ? 

I am curious, as its like you were expecting something to happen and it didnt, please spill the beans on your secret 

 


XPEHOPE3 said:


> Also I thought it's strange that tCL=tCWL+2 runs easier than tCL=tCWL, as "how can running tighter timing can be easier?". But you seem to agree with Nighthog on this.


Unaware of what Nighthog view is on "this".

I just look to see what the BIOS sets these at if they are left on AUTO and on my setup they dont follow the tCL=tCWL rule, I think you are looking at it from the a fixed point of view, dont get me wrong the POV you are looking at it i.e. an "optimization" that increases performance but does so without causing additional load to the system is valid and thats why its strange as we are expecting things to follow a pre conceived knowledge and in this circumstance this does not match that pre conceived knowledge and we dont know how to deal with it.

😂 😂 

There probably isnt any significance in terms of "how can running tighter timing can be easier?" and the engineers know that using tCL=tCWL+2 is an effective way to improve performance irrespective of "pre conceived" knowledge


----------



## mongoled

tcclaviger said:


> I've ordered 4x Patriot Viper Steel Part# PVS416G440C9K to play with and see if I can get better, if not, they'll go in the Linux box. Thoughts on the two different bins and expectations would be appreciated


I have these, look to my sig.

I hope you get some "good" ones, one of my pairs can do 14-14-14-14-1T-26-40-240 3800mhz with 1.52v, the other pair can do 14-14-15(tRCDRD)-14-1T-26-40-240 3800mhz with 1.52v.

One of the sticks of the set can do tRCDRD @14 the other @15, so I run whats in my sig.

From what ive seen recently you may not be getting the same dimms that I have, some reports of newer "versions" running on A0 PCBs, mine are A2s.

When you get them take some pics, there templates around here somewhere showing the difference between A0, A1 and A2 PCBs


----------



## Audioboxer

XPEHOPE3 said:


> BTW tight secondaries can prevent you from pushing tighter primaries. But your run is still somewhat valuable as research of how tight you can tighten secondaries (in nanoseconds, not cycles).


Oh don't worry I'm giving up on CL15 lol. With my memory not booting anything other than RttPark 1 at over 3400 I think it's met its match anyway. 










That's my AIDA. If I can improve my latency a bit from here I'll be happy and call it a good education and a good day. Not even too sure where I should go from above, but some of the secondaries can probably be knocked into better shape and maybe 1T/GDM off will be achieveable at flat 16s.


----------



## reddify

Robostyle said:


> vDIMM?


1.48V VDIMM set in BIOS, 1.49V get in Zentimings.


----------



## munch06

domdtxdissar said:


> The deed is done, have gotten this fully stable
> 
> BIOS 3501 with AGESA V2 PI 1.2.0.2
> dual CCD 5950x
> 4x8GB gskill 3600 CL16
> 1900:3800 @ flat CL14 + T1 GDM-OFF
> Screenshot of TM 1umus 25 cycle + Memtest 20000% stable (do notice this is my old bloaty windows install with lots of stuff running in background)
> View attachment 2490191
> 
> 
> 
> Newest OCCT 8.1.3 1 hour large dataset extreme + 4 iteration in y-cruncher with all tests (same boot as above)
> View attachment 2490192
> 
> 
> Some performance number:
> The SiSoftSandra v2021.31.12 (from Mar 5th, 2021). Not sure this is a good match with CTR..
> Intel latency checker
> View attachment 2490194
> 
> 
> 
> Next we have dram calc easy + normal bench together with cinebench r23
> View attachment 2490195
> 
> 
> And lastly we have SotTR @ 1080p lowest as a gamebench running on my new 24/7 settings =288 CPU average fps
> View attachment 2490196
> 
> 
> Very happy with these results and my new 24/7 settings
> Maybe i will try to push for higher fclk now 😎
> 
> Feel free to leave any comments or questions


oh damm well done, I been working on mine for weeks trying to hit this, wonder how close I can get with 64gb, im at 3733


----------



## domdtxdissar

Have anyone tried playing around with the new OCCT memory benchmark ?

Leaderboards can be found here

This is my 5950x @ 1900 fclk
4x8GB memory at CL14 timings








CPU numbers:


----------



## PJVol

mongoled said:


> Those runs I did are not registered, just installed and ran it


I've sorted it out )) here's mine (prev. was a bit better 87,94 but 0.1ns worse latency)








Лучшие результаты - Эффективность энергоснабжения процессора







ranker.sisoftware.co.uk




I was simply confused by someone's translation of "Processor Inter-Thread Efficiency" to russian, that is back to english sounds like "Processor's power supply efficiency", *** 

OCCT Mem/CPU:
00:00:00 - Info - Test schedule started at 2021-07-17 23:14:27
00:00:00 - Info - CPU - Benchmark started
00:00:10 - Info - CPU - 1 threads, SSE : 90.53
00:00:10 - Info - CPU - Benchmark started
00:00:21 - Info - CPU - 12 threads, SSE : 532.77
00:00:21 - Info - CPU - Benchmark started
00:00:32 - Info - CPU - 1 threads, AVX : 172.76
00:00:32 - Info - CPU - Benchmark started
00:00:43 - Info - CPU - 12 threads, AVX : 942.94
00:00:43 - Info - Test schedule completed

@domdtxdissar
Didn't see how to submit...

Oh...nice, license owners only, hmm... good luck to'em with such stupid move, but I'll pass


----------



## JellyFish3D

JellyFish3D said:


> Heya
> 
> This is what I've managed so far.
> 
> View attachment 2517555
> View attachment 2517556
> 
> 
> The setup seems to be finally stable as I've been trying to lower DRAM voltage, currently it is set to 1.52 V in BIOS and is reported as 1.536 V in HWiNFO. Although I think there is something weird going on with my L3 Cache and I have no idea what it is, it's all over the place. I have copycatted a little from similar 4000c15 setup on Zen RAM OC from "Loudzy" sheet mainly some of the drive strengths and RttNom which have allowed me to drop DRAM voltage from 1.53 in BIOS which gets reported as 1.552 in HWiNFO to current 1.52. According to HWiNFO the voltage steps are weird on my motherboard as they overshoot by up to 0.02V so this -1 step in voltage helped out quite a bit with reducing heat. Currently there is a fan on top of both RAM sticks and the temps seem fine (to the touch, no temp sensor on these Viper bad boys sadly) so far but I intend to daily this setup and therefore want to check that I don't do anything crazy with Rtt's and my current voltage as I don't have much experience configuring them, any tips on figuring those out together with drive strengths? Even if there is nothing wrong with current setup it would be nice to know how to work out Rtt's and drive strengths for future overclocks.
> 
> Just before previous setup I've been trying out tCKE and setup times but they seem to do no difference for my current setup, perhaps I didn't even needed them to begin with. But still, these timings survive overnight.
> 
> View attachment 2517562
> 
> The memory kit is PVS416G413C9K
> 
> 
> Spoiler: Taiphoon
> 
> 
> 
> 
> View attachment 2517553
> 
> 
> 
> The PCB layout is indeed A0 as Taiphoon reports it
> 
> 
> Spoiler: Viper Steel 4133C19
> 
> 
> 
> 
> View attachment 2517554


Bumping since that was my first post and by the time it got verified message popped up few pages behind.

Improved memory latency by playing with VDDG's CCD and IOD. Still not sure what is up with L3 Cache though.


----------



## PJVol

JellyFish3D said:


> Still not sure what is up with L3 Cache though





Spoiler: Set EDC to 500A


----------



## JellyFish3D

PJVol said:


> Spoiler: Set EDC to 500A
> 
> 
> 
> 
> View attachment 2517822


That was it! Thank you. Memory latency seems to dropped down even further, nice.



Spoiler: AIDA64


----------



## XPEHOPE3

mongoled said:


> Just wondering why did you ask if "you were missing something" ?
> 
> I am curious, as its like you were expecting something to happen and it didnt, please spill the beans on your secret


I was asking if I missed something from your posts (like some fact or some argument) because I didn't see the full logic behind your statement that such stick ordering *is better than the other*. It appears it is no better since you can't get 14-flat anyway. Did you make performance comparison between current "good-bad-good-good" setup and, for example, "bad-good-good-good"? Or maybe did you make timings comparison and one setup allowed for tighter timings than the other? If you did something along these lines and posted it somewhere, I could have missed that, and hence I asked the question.


----------



## tcclaviger

mongoled said:


> I have these, look to my sig.
> 
> I hope you get some "good" ones, one of my pairs can do 14-14-14-14-1T-26-40-240 3800mhz with 1.52v, the other pair can do 14-14-15(tRCDRD)-14-1T-26-40-240 3800mhz with 1.52v.
> 
> One of the sticks of the set can do tRCDRD @14 the other @15, so I run whats in my sig.
> 
> From what ive seen recently you may not be getting the same dimms that I have, some reports of newer "versions" running on A0 PCBs, mine are A2s.
> 
> When you get them take some pics, there templates around here somewhere showing the difference between A0, A1 and A2 PCBs


Great to hear, that's a little tighter, 26-40 than I was running the Team Dark Pros before I did bunch of work recently to get to my current timings, 28-42 was how I was running the Dark Pros, so, I imagine they're similar bins, with the nod going to the Patriots (my dark pros will not hit 4000 or above with anything resembling decent timings even in 2:1 mode).

1st thing I'll be doing is pulling all the heat spreaders off so I can put them under water, I'll verify A2 or A0.


----------



## tcclaviger

JellyFish3D said:


> Bumping since first post got popped.
> 
> Improved memory latency by playing with VDDG's CCD and IOD. Still not sure what is up with L3 Cache though.


Win 11?


----------



## JellyFish3D

tcclaviger said:


> Win 11?


Nope, Win 10.










Got the L3 cache and latency fixed though



JellyFish3D said:


> That was it! Thank you. Memory latency seems to dropped down even further, nice.
> 
> 
> 
> Spoiler: AIDA64
> 
> 
> 
> 
> View attachment 2517823


----------



## craxton

(got my issue with y-cruncher crashing solved) took 1.15soc (50mv steps from there down)
CLDO_VDDP was i believe the culprit however, since i did get a crash
during the sisandra overall cpu bench run i was doing.
adjusting it "correctly with that 50mv" step i just mentioned countered the crash,
even tho y-cruncher wasnt crashing anymore up-to iteration 6 with the
tests being 15-16-17-18 being active all else turned off (thats where i was getting crashes)
with all going now im good.

one thing tho, does sisandra report others running 4x8 as running 2x16???
is that normal?








Well, if any 5800x users here wish to "compare" results?
for "overall CPU" and "overall Memory"
id like to know how "good/bad" this 5800x really is, (note my normal CO values as
i thought that was why i was crashing, which to this day i had ZERO crashes)
i dont know if bumping back to a -20 all core minus core 4 being -17 will change much from now being -15 all core and 4 being -9

(EDIT) adding OCCT since i just noticed a "benchmark" section in the latest version i have
write seems "low" since a 3700x is whippin my ass..... unsure if thats "normal" but doesnt seem like it should be
so again, 5800x users OCCT takes about 30 seconds or so to run.... (sisandra depends on what test you click)
give me some insight pls...

















Details for Result ID AMD Ryzen 7 5800X 8-Core Processor (8C 16T 4.83GHz, 1.9GHz IMC, 8x 512kB L2, 32MB L3)







ranker.sisoftware.co.uk













Details for Result ID AMD F19 (Ryzen3/TR3 Matisse) Host Bridge; 2x 16GB Team Group TEAMGROUP-UD4-3200 DDR4 (3.8GHz 18% OC 128-bit) PC4-25600 (14-14-14-28 8-42-14-14)







ranker.sisoftware.co.uk





@XPEHOPE3 
here are some screen shots of the "claimed" better/worse sticks i have. even tho 
all will do 4000/c14-14 (at 1.6+volts) didnt test individually like i should've.
but here they are. dates are the only difference between the two.


----------



## Akex

craxton said:


> (got my issue with y-cruncher crashing solved) took 1.15soc (50mv steps from there down)
> CLDO_VDDP was i believe the culprit however, since i did get a crash
> during the sisandra overall cpu bench run i was doing.
> adjusting it "correctly with that 50mv" step i just mentioned countered the crash,
> even tho y-cruncher wasnt crashing anymore up-to iteration 6 with the
> tests being 15-16-17-18 being active all else turned off (thats where i was getting crashes)
> with all going now im good.
> 
> one thing tho, does sisandra report others running 4x8 as running 2x16???
> is that normal?
> View attachment 2517829
> 
> Well, if any 5800x users here wish to "compare" results?
> for "overall CPU" and "overall Memory"
> id like to know how "good/bad" this 5800x really is, (note my normal CO values as
> i thought that was why i was crashing, which to this day i had ZERO crashes)
> i dont know if bumping back to a -20 all core minus core 4 being -17 will change much from now being -15 all core and 4 being -9
> 
> (EDIT) adding OCCT since i just noticed a "benchmark" section in the latest version i have
> write seems "low" since a 3700x is whippin my ass..... unsure if thats "normal" but doesnt seem like it should be
> so again, 5800x users OCCT takes about 30 seconds or so to run.... (sisandra depends on what test you click)
> give me some insight pls...
> View attachment 2517830
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Details for Result ID AMD Ryzen 7 5800X 8-Core Processor (8C 16T 4.83GHz, 1.9GHz IMC, 8x 512kB L2, 32MB L3)
> 
> 
> 
> 
> 
> 
> 
> ranker.sisoftware.co.uk
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Details for Result ID AMD F19 (Ryzen3/TR3 Matisse) Host Bridge; 2x 16GB Team Group TEAMGROUP-UD4-3200 DDR4 (3.8GHz 18% OC 128-bit) PC4-25600 (14-14-14-28 8-42-14-14)
> 
> 
> 
> 
> 
> 
> 
> ranker.sisoftware.co.uk
> 
> 
> 
> 
> 
> @XPEHOPE3
> here are some screen shots of the "claimed" better/worse sticks i have. even tho
> all will do 4000/c14-14 (at 1.6+volts) didnt test individually like i should've.
> but here they are. dates are the only difference between the two.
> View attachment 2517832
> View attachment 2517833
> View attachment 2517834
> View attachment 2517835


The problem with the current benchmarks is that none is really 100% reliable and you all know it, when it comes to ranking all means are good to finish first. Also, it is easy to pass OCCT stable with a Curve over -30 on most cores, which will artificially inflate the scores, but what about idle stability afterwards? I know I may sound boring but it's reality and I see this behavior every day on every forum that talks about the Curve Optimizer.
I don't work at AMD and what follows is my opinion on my own, but if you have a majority of cores at -30 on a chip with a single CCD, either the base curve is really zero, either you have more than a golden sample, and having tested a large number of 5600X / 5800X I can certify you that it is unbelievable, which does not mean that it cannot happen.


----------



## craxton

Akex said:


> Also, it is easy to pass OCCT stable with a Curve over -30 on most cores


idk about that at all.... my CO was found using core cycler and nearly 5 days of running it 
while i played COC and pokemon go on my phone to leave the system alone while it ran an assload of tests. 
my 5600x however was **** and only did -12 on its (best) not fused best either and a +9 on another all other cores were - offset.
but the IMC was golden hell platinum honestly holding ANY FCLK 1:1:1 without issue and never throwing WHEA fits. (other than hard crashes when CO tuning)
the 5800x is not so great on IMC luck but has GREAT sil quality of 125-130 range.... but for sure wont hold -30 CO without offset to voltage and
be AVX/2 stable.


----------



## Akex

@XPEHOPE3 @Veii 
Today I had some time to do some testing for tPHYRDL, not all of the recommendations given over the last few days did not work. However, I managed to keep 26 instead of 28 in C13 by switching to 1T. I just have to start all over again.
Thank you for guiding me

As a reminder [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## gled_fr

so yeah, after running the 3rd test batch ( currently on the 82nd cycles of 1usmus_v3 ), finally an error showed up. The previous two 30cycles no errors at all. OCCT passed 1h.









What do you think guys, tras to 31 or CkeDrvStr at 24 ?

Currently running vdimm 1.45V, they reach 50-51C during testing ( 40ish during gaming ), should I try to increase voltage to reach tCL 14 or play with VDDG_CCD to try to stabilize the IF at faster than 1900 and increase the frequency ?

Trying to figure out the path to even lower latency and/or better bandwidth...


----------



## Akex

gled_fr said:


> so yeah, after running the 3rd test batch ( currently on the 82nd cycles of 1usmus_v3 ), finally an error showed up. The previous two 30cycles no errors at all. OCCT passed 1h.
> 
> View attachment 2517842
> 
> 
> What do you think guys, tras to 31 or CkeDrvStr at 24 ?
> 
> Currently running vdimm 1.45V, they reach 50-51C during testing ( 40ish during gaming ), should I try to increase voltage to reach tCL 14 or play with VDDG_CCD to try to stabilize the IF at faster than 1900 and increase the frequency ?
> 
> Trying to figure out the path to even lower latency and/or better bandwidth...


In your place I would have stabilized the current profile before wanting to do more FCLK. I think 1900Mhz is already good with correct timings.


----------



## yann3804

Hi!

I recently purchased a new build.
-Ryzen 5600x,
-RTX3080,
-32Gb of Flare X 3200CL14 (2x16Gb), Dual Rank F4-3200C14D-32GFX-G.SKILL International Enterprise Co., Ltd. 
(Confirmed B-Die in Thaiphoon burner)

I'm not a big overclocker, I just want something a bit better than stock XMP.
I don't care about milking out every single bit of performance and mess with this stuff for days.
*I just want a plug n' play that will slightly outperform XMP with robust stability (because we all know XMP isn't optimized at all) *

This is currently what I'm running with: (3200 14-14-14 + GDM enabled), with 1.4V VDIMM. It's stable as far as I can tell, but it's with GDM enabled.
Also don't know if I should aim for higher than 3200, maybe go for 3400 or 3600? Is there even any noticeable difference in games?










Thanks for any help.


----------



## Akex

yann3804 said:


> Hi!
> 
> I recently purchased a new build.
> -Ryzen 5600x,
> -RTX3080,
> -32Gb of Flare X 3200CL14 (2x16Gb), Dual Rank F4-3200C14D-32GFX-G.SKILL International Enterprise Co., Ltd.
> (Confirmed B-Die in Thaiphoon burner)
> 
> I'm not a big overclocker, I just want something a bit better than stock XMP.
> I don't care about milking out every single bit of performance and mess with this stuff for days.
> *I just want a plug n' play that will slightly outperform XMP with robust stability (because we all know XMP isn't optimized at all) *
> 
> This is currently what I'm running with: (3200 14-14-14 + GDM enabled), with 1.4V VDIMM. It's stable as far as I can tell, but it's with GDM enabled.
> Also don't know if I should aim for higher than 3200, maybe go for 3400 or 3600? Is there even any noticeable difference in games?
> 
> View attachment 2517849
> 
> 
> Thanks for any help.


Hello, the problem is that you are going to have some for a few days, especially if you have never practiced and this despite the help that the people on the forum will provide you.
I am not an expert on anything, but in your place I would have bought a crucial 3600C16 kit which is around 90-100 € in France, this will prevent you from "wasting" time increasing frequency and you can concentrate on GDM OFF and on timings only.
Either way prepare yourself psychologically.
To answer your question about the games; Yes and no, depends on the game, FarCry5 from 3200C14 to 3800C14 I have a good performance gain all like Black Deset Online or Tomb Raider and others like Horizon Zero Dawn no gain not even 1 fps.
I let the most seasoned guide you by wishing you a good day


----------



## Sleepycat

yann3804 said:


> Hi!
> 
> I recently purchased a new build.
> -Ryzen 5600x,
> -RTX3080,
> -32Gb of Flare X 3200CL14 (2x16Gb), Dual Rank F4-3200C14D-32GFX-G.SKILL International Enterprise Co., Ltd.
> (Confirmed B-Die in Thaiphoon burner)
> 
> I'm not a big overclocker, I just want something a bit better than stock XMP.
> I don't care about milking out every single bit of performance and mess with this stuff for days.
> *I just want a plug n' play that will slightly outperform XMP with robust stability (because we all know XMP isn't optimized at all) *
> 
> This is currently what I'm running with: (3200 14-14-14 + GDM enabled), with 1.4V VDIMM. It's stable as far as I can tell, but it's with GDM enabled.
> Also don't know if I should aim for higher than 3200, maybe go for 3400 or 3600? Is there even any noticeable difference in games?
> 
> View attachment 2517849
> 
> 
> Thanks for any help.


You can easily hit 3600 CL14-15-14-24 @ 1.4V with that memory. I have even hit 3866 CL16 @ 1.46V. Looking at your Zentimings screenshot, you have a lot of settings that you can optimise if you want to tweak it for more performance. And it should still remain stable too.


----------



## tcclaviger

yann3804 said:


> Hi!
> 
> I recently purchased a new build.
> -Ryzen 5600x,
> -RTX3080,
> -32Gb of Flare X 3200CL14 (2x16Gb), Dual Rank F4-3200C14D-32GFX-G.SKILL International Enterprise Co., Ltd.
> (Confirmed B-Die in Thaiphoon burner)
> 
> I'm not a big overclocker, I just want something a bit better than stock XMP.
> I don't care about milking out every single bit of performance and mess with this stuff for days.
> *I just want a plug n' play that will slightly outperform XMP with robust stability (because we all know XMP isn't optimized at all) *
> 
> This is currently what I'm running with: (3200 14-14-14 + GDM enabled), with 1.4V VDIMM. It's stable as far as I can tell, but it's with GDM enabled.
> Also don't know if I should aim for higher than 3200, maybe go for 3400 or 3600? Is there even any noticeable difference in games?
> 
> View attachment 2517849
> 
> 
> Thanks for any help.


Definitely game specific and in most, spending time optimizing the GPU boost curve is time better spent than tweaking memory. The CPU twaeks, then, once you're GPU custom curve is done, and CPU is fully done and stable, then go for memory as it's all that will be left.


----------



## yann3804

Akex said:


> Hello, the problem is that you are going to have some for a few days, especially if you have never practiced and this despite the help that the people on the forum will provide you.
> Either way prepare yourself psychologically.


I mean, there has to be something simple that can be done to my timings, right? Again, not looking for anything crazy. It could be as simple as setting the fclk to 3600, setting the primaries then AUTOing the rest no? I just don't want to spend too much time on this hehe.



Sleepycat said:


> You can easily hit 3600 CL14-15-14-24 @ 1.4V with that memory. I have even hit 3866 CL16 @ 1.46V. Looking at your Zentimings screenshot, you have a lot of settings that you can optimise if you want to tweak it for more performance. And it should still remain stable too.


I have no doubt about that ahah. I basically just took the Dram calculator and played around with the settings a bit, not having any idea what I'm actually doing 
It would be so kind if you could let me know which settings I should be looking at. (considering you have a similar memory kit)



tcclaviger said:


> Definitely game specific and in most, spending time optimizing the GPU boost curve is time better spent than tweaking memory. The CPU twaeks, then, once you're GPU custom curve is done, and CPU is fully done and stable, then go for memory as it's all that will be left.


interesting. but I don't think I want to tweak GPU or CPU for now, only memory, even if it's for negligible amounts of performance, as crazy as that sounds.


----------



## gled_fr

Akex said:


> In your place I would have stabilized the current profile before wanting to do more FCLK. I think 1900Mhz is already good with correct timings.


I am working on that, just thinking on how to reach low 50s latency and/or gain a few more bandwidth.

Still testing now, but I read the last pages and advices to others from @Veii and it was very enlightening, especially when he talked about:

Twr = 2*tRTP ( went from 10 to 12 )
higher ClkDrvStr you can lower ProcODT ( ClkDrvStr went from 30 to 40, dropped ProcODT from 40 to 36.9, also increased CsOdtStr from 20 to 30 ).

That alone allowed me to -1 the *SD ( 5->4, 7->6 ) and it passed already 30 cycles. On its way to the 80s now overnight.

That should give me a stable base to see how to go lower .

Quick test ( unstable because WHEA errors due to IF ) showed around 1GB/s increase and almost 1ns gain going from 1900 to 1933 IF with ram at 3866, same settings but higher vdimms and vddgs, unable to boot at more than that.
I also quickly tried my settings with tCL 14 and lots of errors 6 and 0, which tells me it should be doable to stabilize and bring me in the lower 54 but I need more work there.

Anyway, letting the current run finalize on the flat 15 hopefully stable this time before trying to go lower !


----------



## mongoled

Audioboxer said:


> I tried 4 a few times but I'll try 5~7. When you say limit of hardware, is that mobo and RAM or RAM only? As you can see above I think I'm going to go shopping for new RAM anyway lol.
> 
> I actually have a Corsair Vengeance Pro set lying around to be sold I can actually test with RttPark as well.


Most likely combination of both. Without having a different motherboard to test with you can't really know. Even if you test with other RAM and let's say it can do RttPark at something other than RZQ/1 you will have only ruled out its something to do with your ram, motherboard combo, as to which of the two you won't really know unless you try those modules in a different motherboard


----------



## Audioboxer

mongoled said:


> Most likely combination of both. Without having a different motherboard to test with you can't really know. Even if you test with other RAM and let's say it can do RttPark at something other than RZQ/1 you will have only ruled out its something to do with your ram, motherboard combo, as to which of the two you won't really know unless you try those modules in a different motherboard


I'm going to pickup some more memory, so we'll see how it works out with this mobo. My Corsair memory is Micron E die, I'd like to get some more B die to test it.

Leaning towards the 4000C16 DR. That way if 4000/2000 ever becomes a more mainstream thing without WHEA errors I've got a pretty decent XMP profile to work with.

I can boot 2000 on this board/CPU but get the WHEA errors flooding in.










Trying to tighten up some secondaries at CL16 with this. Going OK.

When it comes to it what's the best process for attempting 1T other than "just put it on 1T" lol. I'm guessing RttPark 3 might have helped here even at CL16? It seems I need to use the Setups to get 1T GDM disabled booting at 3800.


----------



## mongoled

Audioboxer said:


> I'm going to pickup some more memory, so we'll see how it works out with this mobo. My Corsair memory is Micron E die, I'd like to get some more B die to test it.
> 
> Leaning towards the 4000C16 DR. That way if 4000/2000 ever becomes a more mainstream thing without WHEA errors I've got a pretty decent XMP profile to work with.
> 
> I can boot 2000 on this board/CPU but get the WHEA errors flooding in.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Trying to tighten up some secondaries at CL16 with this. Going OK.
> 
> When it comes to it what's the best process for attempting 1T other than "just put it on 1T" lol. I'm guessing RttPark 3 might have helped here even at CL16? It seems I need to use the Setups to get 1T GDM disabled booting at 3800.


You set 1T along with AddrCmdSetup @56. Very few sets can do "pure" 1T 3800 mhz with 32GB of RAM (using AddrCmdSetup is like 1.5T as 1T is too aggressive )


----------



## Audioboxer

mongoled said:


> You set 1T along with AddrCmdSetup @56. Very few sets can do "pure" 1T 3800 mhz with 32GB of RAM (using AddrCmdSetup is like 1.5T as 1T is too aggressive )


I'll give that a go later then.

Isn't GDM on like 1.5T as well? Forgive my ignorance if I'm wrong here. On that note if I'm not going to run CL15 is it best to stick to 2T GDM disabled if my options end up this or GDM enabled?


----------



## mongoled

Audioboxer said:


> I'll give that a go later then.
> 
> Isn't GDM on like 1.5T as well? Forgive my ignorance if I'm wrong here. On that note if I'm not going to run CL15 is it best to stick to 2T GDM disabled if my options end up this or GDM enabled?


Yes, but GDM does a whole load of other things, hidden in the background! That's one of the reasons we don't want to use it as we "loose some control" of things we can't "see"!


----------



## MyUsername

Audioboxer said:


> I'm going to pickup some more memory, so we'll see how it works out with this mobo. My Corsair memory is Micron E die, I'd like to get some more B die to test it.
> 
> Leaning towards the 4000C16 DR. That way if 4000/2000 ever becomes a more mainstream thing without WHEA errors I've got a pretty decent XMP profile to work with.
> 
> I can boot 2000 on this board/CPU but get the WHEA errors flooding in.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Trying to tighten up some secondaries at CL16 with this. Going OK.
> 
> When it comes to it what's the best process for attempting 1T other than "just put it on 1T" lol. I'm guessing RttPark 3 might have helped here even at CL16? It seems I need to use the Setups to get 1T GDM disabled booting at 3800.


4000cl16 are okay, they can do 14, 15, 14, 14 2T 3800 with fairly tight tertiary timings at 1.5V. I got some 4000cl14 chasing the white rabbit, I wanted straight 14s, yer right all I could achieve was 0.02 less volts at the same timings lol


----------



## mongoled

MyUsername said:


> 4000cl16 are okay, they can do 14, 15, 14, 14 2T with fairly tight tertiary timings at 1.5V. I got some 4000cl14 chasing the rabbit, I wanted straight 14s, yer right all I could achieve was 0.02 less volts at the same timings lol


It's the chase that counts

😁😁😂


----------



## Audioboxer

MyUsername said:


> 4000cl16 are okay, they can do 14, 15, 14, 14 2T 3800 with fairly tight tertiary timings at 1.5V. I got some 4000cl14 chasing the white rabbit, I wanted straight 14s, yer right all I could achieve was 0.02 less volts at the same timings lol


There's some 3800CL14 sets but with the pricing of them I'd probably be looking at dropping down to 16GB (2x8) just now over getting 32GB (2x16) at 4000CL16.

I found this site last night which is pretty handy B-Die Finder

It ranks the 4000CL16 at 8ns and the 3800CL14 at 7.4ns. But I think I'd rather have 32GB for longevity.

Also for the pros, is this just fluctuations in testing?



















Or is there some "over tightening" / poorly aligned tightening going on?

The difference is my stable profile from earlier, versus my next step which was attempting to tighten some settings. The profile with the lower tRFC and some lower secondaries seems to be performing worse with latency. Multiple tests in the 58.x range, whereas the first profile is more often in the 57.x range.


----------



## domdtxdissar

domdtxdissar said:


> So i decided to also test this in windows11... Pretty much same settings as above.
> 
> 5950x @ 4700/4600 static OC, SMT enabled
> 4x8GB memory sticks
> 
> View attachment 2516294
> 
> 1800:3600 T1 setup-time + CL14-14-14-14
> *19107.4 H/S over 15min run*
> upto 605 H/S per core
> 
> View attachment 2516295
> 
> 1900:3800 T1 setup-time + CL14-14-14-14 and the tweaks i got suggested a few pages back (tRRDL=5, tWR=10 and tRTP=5)
> *19769 H/S over 15min run*
> upto 625 H/S per core
> 
> View attachment 2516296
> 
> 1900:3800 T1 setup-time + CL14-14-14-14
> *19855.7 H/S over 15min run*
> upto 632 H/S per core
> 
> A few thoughts on the runs above:
> 
> Scaling between 1800:3600 and 1900:3800 seems pretty good. Theoretical max scaling should be 5.5%. (1900/1800)
> Iam seeing upwards to ~4% improved real-performance (19769/19107) with the only change being fclk 1800 vs 1900.
> 
> 
> tRRDL=5, tWR=10 and tRTP=5 setup performed alittle worse then my regular "flat cl 14" setup
> 
> For fun i also tried a setup with tighter timings then the flat cl14-14-14-14 baseline.. To my big surprise it performed even better
> In theory (math) it should not perform better, but i cant argue with the numbers im seeing:
> View attachment 2516297
> 
> 1900:3800 T1 setup-time + CL14-8-14-12-24-36
> *20038.6 H/S over 15min run*
> upto 638 H/S per core
> 
> *Can any of you guys make heads or tails of this ? *
> Seems like i found me some new daily 24/7 settings by just playing around.


So iam back to a Sophia-Script slimmed windows 10 install.
My asymmetric timings netting above 20000 H/s in the Monero RandomX Miner was not a windows11 fluke it seems 
(instructions how to install the miner can be found here)

Same settings as before:

5950x @ 4700/4600 static OC, SMT enabled
4x8GB memory sticks
Rest of information in screenshot









1900:3800 T1 setup-time + CL14-8-14-12-24-36
*20208.7 H/S ! over 15min run*
upto 641 H/S per core

25 cycles in TestMem 1usmus cfg with same settings








Which means the real performance in my current win10 install is even better than my previous windows11 install, even when win11 it put up Aida numbers like this, which only brings me back to that Aida64 cant really be trusted as true "performance index" like ive said many times before


----------



## Audioboxer

domdtxdissar said:


> So iam back to a Sophia-Script slimmed windows 10 install.
> My asymmetric timings netting above 20000 H/s in the Monero RandomX Miner was not a windows11 fluke it seems
> (instructions how to install the miner can be found here)
> 
> Same settings as before:
> 
> 5950x @ 4700/4600 static OC, SMT enabled
> 4x8GB memory sticks
> Rest of information in screenshot
> 
> View attachment 2517868
> 
> 1900:3800 T1 setup-time + CL14-8-14-12-24-36
> *20208.7 H/S ! over 15min run*
> upto 641 H/S per core
> 
> 25 cycles in TestMem 1usmus cfg with same settings
> View attachment 2517869
> 
> 
> Which means the real performance in my current win10 install is even better than my previous windows11 install, even when win11 it put up Aida numbers like this, which only brings me back to that Aida64 cant really be trusted as true "performance index" like ive said many times before
> View attachment 2517870


Oooft, that's some nice results. Makes me want to take a gamble on a F4-3600C16Q set rather than looking at 4000C16 

SR instead of DR too.


----------



## Veii

Audioboxer said:


> There's some 3800CL14 sets but with the pricing of them I'd probably be looking at dropping down to 16GB (2x8) just now over getting 32GB (2x16) at 4000CL16.
> 
> I found this site last night which is pretty handy B-Die Finder
> 
> It ranks the 4000CL16 at 8ns and the 3800CL14 at 7.4ns. But I think I'd rather have 32GB for longevity.
> 
> Also for the pros, is this just fluctuations in testing?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Or is there some "over tightening" / poorly aligned tightening going on?
> 
> The difference is my stable profile from earlier, versus my next step which was attempting to tighten some settings. The profile with the lower tRFC and some lower secondaries seems to be performing worse with latency. Multiple tests in the 58.x range, whereas the first profile is more often in the 57.x range.


The bottom picture has less soc droop, throttles on L3 cache and throttles on write bandwidth
If it was the first test, that's fine
But it either looks like lack of powerbudget because something took performance before aida was run/mid run
Or it really was idle and either heat on the vrms changed behavior, house installation changed current stability betweeen night and day power
Or you changed more things and limited powerbudget throttles ypur results

I think it's not only, a powerbudget thing
Write throttle is often a fabric stability and core stability part
Has less to do with mclk
But 64B link may also react to memory more, compared to 32B single CCD links

About the memory math
Dont fall for it
The math was done on tCL, the math is wrong
The ns transfer time math has to be done on tRCD , to justify binning per MCLK
And then there is still the open topic of voltage increase

MyUsername wrote it well,
Best he could do is 0.02v less
Sure its a variance thing, but my feeling remains that high voltage xmp kits, have barely anything left in them
While low voltage lower tRCD kits might have more potential left

Heh you can also just go with 4x A2 4400C19-19 vipers and have hell(ish) eeh, fun time 
Balancing two hungry PCBs on a 25/75% powering daisy chain layout 🤭
At least the custom A2 pcb (more like A1+) would behave better haha
No really decide your goals.
Ignore PCB lottery or ignore IC lottery
There are low timings 3600 kits out there, or high timings 4000+ kits
Ignore tCL, it's marketing with high voltage

Every short trace PCB (A1-A2) will allow low tCAS to function
Only A0 struggles with it, yet here i am with tCL13
Really, don't fall for this tCAS let me call it "fandom"
It does give perf and i've been there with hynic MFR running 14-X-19 , and it lowered latency well
But ultimately, the non moving tRCD was the maim perf loss around it. Which you barely can do anything about it
Brute force it, kind of ~ but then that goes to every IC out there


----------



## Audioboxer

Dropped my tRFC on my first profile as it passed on the second, almost got me into 56.x territory, never been this low.

So between the profiles it either has to be tightening tWTRL, TWR, tRTP or switching to tCWL 14 tRDWR 12 which actually made me _worse_ off.

Just to understand now where either my memory is at its limits or my mobo or a combination of both. The more I learn the more I think my mobo might be wheezing a bit at this point too.



Veii said:


> The bottom picture has less soc droop, throttles on L3 cache and throttles on write bandwidth
> If it was the first test, that's fine
> But it either looks like lack of powerbudget because something took performance before aida was run/mid run
> Or it really was idle and either heat on the vrms changed behavior, house installation changed current stability betweeen night and day power
> Or you changed more things and limited powerbudget throttles ypur results
> 
> I think it's not only, a powerbudget thing
> Write throttle is often a fabric stability and core stability part
> Has less to do with mclk
> But 64B link may also react to memory more, compared to 32B single CCD links
> 
> About the memory math
> Dont fall for it
> The math was done on tCL, the math is wrong
> The ns transfer time math has to be done on tRCD , to justify binning per MCLK
> And then there is still the open topic of voltage increase
> 
> MyUsername wrote it well,
> Best he could do is 0.02v less
> Sure its a variance thing, but my feeling remains that high voltage xmp kits, have barely anything left in them
> While low voltage lower tRCD kits might have more potential left
> 
> Heh you can also just go with 4x A2 4400C19-19 vipers and have hell(ish) eeh, fun time
> Balancing two hungry PCBs on a 25/75% powering daisy chain layout 🤭
> At least the custom A2 pcb (more like A1+) would behave better haha
> No really decide your goals.
> Ignore PCB lottery or ignore IC lottery
> There are low timings 3600 kits out there, or high timings 4000+ kits
> Ignore tCL, it's marketing with high voltage
> 
> Every short trace PCB (A1-A2) will allow low tCAS to function
> Only A0 struggles with it, yet here i am with tCL13
> Really, don't fall for this tCAS let me call it "fandom"
> It does give perf and i've been there with hynic MFR running 14-X-19 , and it lowered latency well
> But ultimately, the non moving tRCD was the maim perf loss around it. Which you barely can do anything about it
> Brute force it, kind of ~ but then that goes to every IC out there


Ah, good catch, I didn't notice L3 cache.

And for the rest of the info, thanks again. I'm going to pay more attention to more timings than just the tCL and try and make an informed decision. Then whatever I buy the fun begins again 

I've learned a lot the past week thanks to everyone in here, but I'm still very fresh and have a long way to go.


----------



## Veii

Audioboxer said:


> Just to understand now where either my memory is at its limits or my mobo or a combination of both. The more I learn the more I think my mobo might be wheezing a bit at this point too.


Your mobo is nearly never the issue
Bet you can reach these results on an X470 too maybe even B450 tomahawk 

I think the strix-f was maintained by Reous too
Forgot if X570 or B550, but i'm nearly confident you have bios mods out there

Boards are an issue beyond 4200+ MCLK

Edit: your tRDWR is at its limits
DR need tRCD/2 +2
Or +1 with added tWRRD delay

You already run this as low as it gets 
For some balancing it might even be too low
But generally lower tCWL messes up balancing, depends really
You run +4 on tRC, soo that likely hides couple more issues
As tRC has to elaps, whatever you set on it
Other timings can overlap, as memory timings chain is not a straightforward A to B mechanic
Many timings overlap at the same time and dual bank groups run two operation's at the same time, not one

Yet tRC has to elaps before anything can progress
Soo it easily hides latency mismatches and why XOC guys push that value first up
It "gives" stability by slowing everything down when everything waits for it


----------



## Audioboxer

Veii said:


> Your mobo is nearly never the issue
> Bet you can reach these results on an X470 too maybe even B450 tomahawk
> 
> I think the strix-f was maintained by Reous too
> Forgot if X570 or B550, but i'm nearly confident you have bios mods out there
> 
> Boards are an issue beyond 4200+ MCLK


Good to know, I'm not planning on changing my mobo anyway, I recently drained my loop to add another radiator and I'd rather wait to see what the X570s revisions are like or just hold off till "next gen". The Dark Hero is often OOS here or price inflated and while the Aorus Master is an upgrade over the X570f, there just isn't enough in it to justify buying it and dealing with the change over.

I'll drop some money into some nice new ram kits, this time with RGB (makes your computer go faster, duh) and if they're a winner I'll just sell this RAM and my Corsair Vengeance which I was planning to sell anyway.

I think the BIOS mods might be for the B550. But I'll check.

*edit* - I'll have a look at those settings you mentioned above from tRC to tRDWR


----------



## Mach3.2

yann3804 said:


> I mean, there has to be something simple that can be done to my timings, right? Again, not looking for anything crazy. It could be as simple as setting the fclk to 3600, setting the primaries then AUTOing the rest no? I just don't want to spend too much time on this hehe.


Memory testing is time consuming, there is no escape. If you do not have the time for memory testing, I'd suggest you just leave it on stock XMP.


----------



## Veii

Audioboxer said:


> SR instead of DR too.


Finally on the PC,
Dual Rank generally is faster and results do appear in games
But so is also 4x SR equally fast
Technically speaking, SR could OC higher frequency (even when DR is faster at the same given freq)
But then daisy chain layout comes in as a problem, soo finding "good DR kits" is either rare or retails for the typical 130-160 bucks per 16gb market (which was held for 2+ years on b-die)
It's a lot of money for memory, considering also that DDR4 is soon EoL well at least a year more.
Then having to learn working with 4 bank groups , similar to GDDR6 (quad data rate) - will be fun. In comparison this here is straight forward and easy 
(learning to OC AMD GPU's ~timings~ , will then be a valuable skillset)


Audioboxer said:


> think the BIOS mods might be for the B550. But I'll check.











[Sammelthread] - ASUS X570 Strix Series (X570-E Gaming, X570-E Gaming Wifi II, X570-F Gaming, X570-I Gaming)


ROG Strix X570-E Gaming ROG Strix X570-E Gaming Wifi II ROG Strix X570-F Gaming ROG Strix X570-I Gaming BIOS/UEFI Versionen Reviews & VRM Häufig gestellte Fragen BIOS Mods Changelog Download Flashing and using on your own risk! Added VDDP Voltage Might be helpful for CPU...




www.hardwareluxx.de




X570 








I remember the F lineup always was the cut down version - bios mostly, while the PCB remained high quality
For the Strix lineup , the E part was always higher tier
Unsure why XE even was needed to exist - probably only an IO upgrade and to make use of the DARK terminology as rarely anyone bought the Formula's with VRM blocks 

Pick a board based upon VRM setup , and just go with it
AMD continues to enforce boards being equal 
(a long history lesson about it nobody really wants to read Should i change chips)
Every board will manage it
Have to check ViperTW's report, but i think the limit is even higher, before Daisy-Chain vs T-Topology & DR vs SR , start to be a pure motherboard limit 
They are not, even when old Zen gen 1/2 research showed higher potential FCLK on T-Topology Boards.
It was just different signal integrity "on stock" without much work towards optimizing it. Everyone learns soo nobody is to blame for history. 

But today i really don't care about the boards (unless they have problematic parts build in, haha)
Every board you pick, will overclock memory well
ITX continue to be better , same as generally 2 dimm boards ~ looking at upcoming 2 EVGA 2-dimm boards 


Audioboxer said:


> *edit* - I'll have a look at those settings you mentioned above from tRC to tRDWR


Might really need to give tRDWR +1 if it bothers and overlaps
But you'll notice. tRC = tRP+tRAS. Lower is possible , higher is wasting latency and masking timings

SD,DD's lower does not benefit performance, it eats away performance but helps in stability
Higher values here give more perf by the potential issue of overlapping with other timings 
That MSi 1-5-4-1-7-6 trick, allows for tRDWR to go 1 step lower, but it's unclear if it really is faster than 1-5-5-1-7-7 or 1-4-4-1-6-6 for DR


----------



## Veii

Audioboxer said:


> I'll drop some money into some nice new ram kits, this time with RGB (makes your computer go faster, duh) and if they're a winner I'll just sell this RAM and my Corsair Vengeance which I was planning to sell anyway.


Keep in mind, RGB does indeed heat the dimms up - for OC it matters, for casual operation barely
2c delta exists at absolute minimum, but i lean more towards the 4c region (turned off and turned on RGB)
Also keep in mind Trident Z lightning control needs to keep running as a service, else the memory does not remember RGB off state

Yet the Ripjaws have a half covering Heatspreader initially designed for A0 layout where the ICs where further upwards
Soo today it only covers half of it ~ including their attached heatspreader (half IC coverage) with A1 and A2 layouts
(temps are fine, but the issue is an issue ~ one might just drive without a heatspreader at this point)

Another problem, Ripjaws appear to be 8 layer while RGB Trident Z's are 10 layer ~ both having the same pricetag
Idk what is a better option , both are "downtrades"
But when you go with Ripjaw's (what i'd do) , just replace the heatspreader
8 layer or 10 layer, whatever - but a service focused RGB kit which you can not programm to be off, is more annoying i feel 

Some "old clients" went with the Dominator CMDAF2 Ram cooler ontop of Ripjaws
Or ontop of Teamforce ARGB kits (which are full coverage RGB yet capable to run tight timings)
Really depends, there are many options ~ i couldn't care less if it lights up or not, but do care if it increases temps beyond 2c delta
Soo if you can keep RGB kits cold, eh why not - 10 layer PCB is a nice thing to have


Audioboxer said:


> The Dark Hero is often OOS here or price inflated


The dark hero shares more marketing and XOC popularity than the remain lineup
the E & B550 XE are considerable.
Personally don't like dual NIC boards unless they share the same brand (no Realtek x Intel mix)
Would rather go with the XE instead the dark hero at any time
But then the XE is not soo cheap & EVGA Dark (expensive) will come out soon

EDIT:
Just stay with your board
There is close to zero reason to upgrade
Maybe if you lack fan headers 

You can flash the bios either with AFUWIN or with USB flashback (button)
Not "in-Bios"


----------



## Audioboxer

Veii said:


> Finally on the PC,
> Dual Rank generally is faster and results do appear in games
> But so is also 4x SR equally fast
> Technically speaking, SR could OC higher frequency (even when DR is faster at the same given freq)
> But then daisy chain layout comes in as a problem, soo finding "good DR kits" is either rare or retails for the typical 130-160 bucks per 16gb market (which was held for 2+ years on b-die)
> It's a lot of money for memory, considering also that DDR4 is soon EoL well at least a year more.
> Then having to learn working with 4 bank groups , similar to GDDR6 (quad data rate) - will be fun. In comparison this here is straight forward and easy
> (learning to OC AMD GPU's ~timings~ , will then be a valuable skillset)
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Sammelthread] - ASUS X570 Strix Series (X570-E Gaming, X570-E Gaming Wifi II, X570-F Gaming, X570-I Gaming)
> 
> 
> ROG Strix X570-E Gaming ROG Strix X570-E Gaming Wifi II ROG Strix X570-F Gaming ROG Strix X570-I Gaming BIOS/UEFI Versionen Reviews & VRM Häufig gestellte Fragen BIOS Mods Changelog Download Flashing and using on your own risk! Added VDDP Voltage Might be helpful for CPU...
> 
> 
> 
> 
> www.hardwareluxx.de
> 
> 
> 
> 
> X570
> View attachment 2517872
> 
> I remember the F lineup always was the cut down version - bios mostly, while the PCB remained high quality
> For the Strix lineup , the E part was always higher tier
> Unsure why XE even was needed to exist - probably only an IO upgrade and to make use of the DARK terminology as rarely anyone bought the Formula's with VRM blocks
> 
> Pick a board based upon VRM setup , and just go with it
> AMD continues to enforce boards being equal
> (a long history lesson about it nobody really wants to read Should i change chips)
> Every board will manage it
> Have to check ViperTW's report, but i think the limit is even higher, before Daisy-Chain vs T-Topology & DR vs SR , start to be a pure motherboard limit
> They are not, even when old Zen gen 1/2 research showed higher potential FCLK on T-Topology Boards.
> It was just different signal integrity "on stock" without much work towards optimizing it. Everyone learns soo nobody is to blame for history.
> 
> But today i really don't care about the boards (unless they have problematic parts build in, haha)
> Every board you pick, will overclock memory well
> ITX continue to be better , same as generally 2 dimm boards ~ looking at upcoming 2 EVGA 2-dimm boards
> 
> Might really need to give tRDWR +1 if it bothers and overlaps
> But you'll notice. tRC = tRP+tRAS. Lower is possible , higher is wasting latency and masking timings
> 
> SD,DD's lower does not benefit performance, it eats away performance but helps in stability
> Higher values here give more perf by the potential issue of overlapping with other timings
> That MSi 1-5-4-1-7-6 trick, allows for tRDWR to go 1 step lower, but it's unclear if it really is faster than 1-5-5-1-7-7 or 1-4-4-1-6-6 for DR


Excellent, thank you, I didn't know BIOS mods existed for this mobo. I knew the E model was technically better but I got the F model in a bundle deal with a 3900XT when I bought it.

Some more quick testing










Dropped tRC to 52, 57.2ns. Obviously not stability tested.










Dropped tCWL to 14, increased tRDWR to 10 and dropped tWR to 14, boom, choking and very likely instability.


----------



## Veii

Audioboxer said:


> Excellent, thank you, I didn't know BIOS mods existed for this mobo. I knew the E model was technically better but I got the F model in a bundle deal with a 3900XT when I bought it.
> 
> Some more quick testing
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Dropped tRC to 52, 57.2ns. Obviously not stability tested.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Dropped tCWL to 14, increased tRDWR to 10 and dropped tWR to 14, boom, choking and very likely instability.


Yes yes, too many changes
Just ignore that tCWL
It causes much more problems than it's worth it
It should be changed at the very very end - yet i barely to ever touch it. Only if i do tRC trickery & exploits

Can note too that it can not be an Odd value, this refuses to post (logically it should work, but FW says no)
And it can not be higher than tCL , that also refuses to post at any setting
Equal or 1 step lower if you use odd tCL. No reason to ever go lower - unless you do some specific changes

tRDWR you can keep at 9,
higher will eat away perf and this flag does actually lower it quite a bit
But you can have issues with it - soo it's also something you lower at the very end if there is headroom left in your chain

EDIT:
Oh tCWL 14 = -2 , might need tRDWR 11 , when tRDWR 9 should be "the baseline" for you
having it on 8 is already lower than "it has to run"
Great that it's possible with your kits, but you trade away stability unless verified it's rock solid with no wasted tRC delay

EDIT2:
I'm gonna go grab some coffee
This run rocksolid the last high fps (600+) game session. No random framespikes or programm crashes








Kind of in the mood to get 3733 to run ~somehow~ today
Been PCB crashing with higher than 1.66v or by overcurrent issues 
C14 doesn't do it up till 1.7v, but for C13 it seems powering being to noisy ~ likely need to rebalance it again


----------



## Audioboxer

Veii said:


> Yes yes, too many changes
> Just ignore that tCWL
> It causes much more problems than it's worth it
> It should be changed at the very very end - yet i barely to ever touch it. Only if i do tRC trickery & exploits
> 
> Can note two that it can not be an Odd value, this refuses to post
> And it can not be higher than tCL , that also refuses to post at any setting
> Equal or 1 step lower if you use odd tCL. No reason to ever go lower - unless you do some specific changes
> 
> tRDWR you can keep at 9,
> higher will eat away perf and this flag does actually lower it quite a bit
> But you can have issues with it - soo it's also something you lower at the very end if there is headroom left in your chain


Yeah I tried only changing it to 10










Latency up to 58.3ns.

I'll take my 57.2, stability test it (tRC dropped to 52) and go from there. See if I can get into 56.x range over next few days


----------



## domdtxdissar

domdtxdissar said:


> So iam back to a Sophia-Script slimmed windows 10 install.
> My asymmetric timings netting above 20000 H/s in the Monero RandomX Miner was not a windows11 fluke it seems
> (instructions how to install the miner can be found here)
> 
> Same settings as before:
> 
> 5950x @ 4700/4600 static OC, SMT enabled
> 4x8GB memory sticks
> Rest of information in screenshot
> 
> View attachment 2517868
> 
> 1900:3800 T1 setup-time + CL14-8-14-12-24-36
> *20208.7 H/S ! over 15min run*
> upto 641 H/S per core
> 
> 25 cycles in TestMem 1usmus cfg with same settings
> View attachment 2517869
> 
> 
> Which means the real performance in my current win10 install is even better than my previous windows11 install, even when win11 it put up Aida numbers like this, which only brings me back to that Aida64 cant really be trusted as true "performance index" like ive said many times before
> View attachment 2517870


And some dram benches at same settings


----------



## spajdr

Gents, so from what I catched here, L3 low performance is fixed by setting EDC to 500 in bios?
Because I get like 100GB/60GB/40GB or something like that only.
Or did I need to fiddle with some voltage again.


----------



## Robostyle

I have problems with some sort of intermittent errors when trying to pass tm5. Seems stable at first, but then it's always 1-3 errors pop-up at the end, ~18,19,20 iteration cycle. 
This is how it passed the last 5 tries over last night, one by one:
1) tm5 thread crash after ~10 iter, state 8
2) tm5 20 cycles passed, 0 error.
3) tm5 20 cycles, 3 errors after ~15 iterations.
4) tm5 20 cycles, 1 error at the end
5) tm5 20 cycles passed, 0 error. 

I've already posted screenshot, HCI memtest stable 2200%, same goes for ycruncher, 2.5h 100% fine. Only thing bothering me with random errors is tm5


----------



## adversary

Veii said:


> Finally on the PC,
> Dual Rank generally is faster and results do appear in games
> But so is also 4x SR equally fast
> Technically speaking, SR could OC higher frequency (even when DR is faster at the same given freq)
> But then daisy chain layout comes in as a problem, soo finding "good DR kits" is either rare or retails for the typical 130-160 bucks per 16gb market (which was held for 2+ years on b-die)



what you exactly mean by "But then daisy chain layout comes in as a problem"?
is daisy chain ok for 2 dimms generally, or it is ok only with dual-rank 2 dimms?

I run 32GB dual-rank with daisy chain board now.
in future, if we hopefuly get Zen3 refresh, I was roughly planning 12 core CPU, most probably to keep same RAM as it provided really good scores, and most likely 2 DIMMs type board (as I plan to keep same RAM). keeping eye if MSI Unify-X with X570S will come out (and will check all other specs, and expirience from others, of course).

but would like to get overall some better insight on daisy chain, 2 DIMMS type boards, and dual-rank RAM.

(if you need to know PCB layout of this RAM kit, I can picture it or check or provide link of it, it is not definitely B0, it is B1 or B2).


----------



## spajdr

Set EDC to 500 but my L3 cache is still low, any tips guys?
By the way, got it stable with GDM disabled  even though only with 2T Cmd2T.


----------



## Mach3.2

Anything running in the background while you're benching cache?

Cache latency should be in the 10.x ns range, depending on the max CPU frequency that can be ran. 28.1ns is way too high, something is up.


----------



## spajdr

@Mach3.2
Absolutely nothing at all.
I changed VSOC from 1.08750V to 1.18V, nothing it look like this








read/write/copy improved but still slow latency

EDIT.: and if I run all tests its slow as before in the end again :-/


----------



## domdtxdissar

spajdr said:


> @Mach3.2
> Absolutely nothing at all.
> I changed VSOC from 1.08750V to 1.18V, nothing it look like this
> View attachment 2517876
> 
> read/write/copy improved but still slow latency
> 
> EDIT.: and if I run all tests its slow as before in the end again :-/
> 
> View attachment 2517877


This is standard windows11 + aida64 L3 problem... Nothing new and you cant fix it

I had exactly the same when i was testing win11


----------



## spajdr

@domdtxdissar didn't know that, thanks


----------



## XPEHOPE3

yann3804 said:


> I don't care about milking out every single bit of performance and mess with this stuff for days.
> *I just want a plug n' play that will slightly outperform XMP with robust stability (because we all know XMP isn't optimized at all) *
> 
> This is currently what I'm running with: (3200 14-14-14 + GDM enabled), with 1.4V VDIMM. It's stable as far as I can tell, but it's with GDM enabled.


3600-14 is easily stable on b-dies 3200-14 bin:










Audioboxer said:


> Multiple tests in the 58.x range, whereas the first profile is more often in the 57.x range.


Please start tracking you tPHYRDL *on both memory channels* (A2 and B2 sticks). If it's 26 on one setup and 28 on the other, you can easily gain 0.5ns latency.
Also for my setup tRTP 8 gives more latency than tRTP 10, and tRTP 6 gives loads of errors. So yes, sometimes it's overtightening, maybe in your case too.


domdtxdissar said:


> which only brings me back to that Aida64 cant really be trusted as true "performance index" like ive said many times before


Or Aida64 latency is also sensitive to CPU clock since on your first screen it's 5000, and on the second it's 5050.


----------



## Audioboxer

XPEHOPE3 said:


> 3600-14 is easily stable on b-dies 3200-14 bin:
> View attachment 2517878
> 
> 
> Please start tracking you tPHYRDL *on both memory channels* (A2 and B2 sticks). If it's 26 on one setup and 28 on the other, you can easily gain 0.5ns latency.
> Also for my setup tRTP 8 gives more latency than tRTP 10, and tRTP 6 gives loads of errors. So yes, sometimes it's overtightening, maybe in your case too.
> Or Aida64 latency is also sensitive to CPU clock since on your first screen it's 5000, and on the second it's 5050.


It's 26 on both, meant to mention this a day or so ago when I seen others talking about it. I'll play around with tRTP and see what results I get.


----------



## XPEHOPE3

Anyone knows why a setup which was TM5 stable can become TM5 unstable? No difference in timings for both channels, ambient temps became lower, also lower SoC current...
Stable on 13.07:









Unstable on 18.07:









Meanwhile I was testing lower tRAS values, and they too were unstable:
tRAS 32, tRC 49







tRAS 30, tRC 49







tRAS 32 tRC 56


----------



## Veii

spajdr said:


> Gents, so from what I catched here, L3 low performance is fixed by setting EDC to 500 in bios?
> Because I get like 100GB/60GB/40GB or something like that only.
> Or did I need to fiddle with some voltage again.


The EDC flag in the BIOS does influence one stage of the sensoring and throttling

Generally it's up to fit to "overdrive" cache , till it reaches peak limits
Which depends on how many cores are resting (not sleeping & freeing voltage)

problem to such, high EDC (no limit) allows more voltage to pass through
which can be detected by FIT as "too much current" and will be throttled back
It's good to open up PPT power limit
But limit it on TDC for allcore workloads
Yet keep EDC wide open ~ 400A is usually enough

Internally it will limit itself back to the pre-programmed FUSE limit
But you'll get a bit more cache overdrive
Just need to be cautious (again) with open limiters, that more voltage will be provided and the CPU can frequency overboost too - soo that way get unstable
Soo it's a good practice to put powersuply idle control to Typical Current & DF-C States manually disabled
Global C-State generation is important to use , for boosting beyond the 3.7/3.8 P0 idle state
it's important allowing the CPU the ability to lower voltage and lower powerstates - soo more power reserves are free for cores "that matter" or are needed

My unit, i run 175-135-400
Stock is 65-55-120
I could just run 160-100-400 , as i'm reaching that 120W mark (SOC / memOC FLCK being hungry for power)
but just so you know , limiting TDC will throttle back voltage and then frequency on allcore loads 
Usually it's good practice to let it just about hold 98% usage on Cinebench R20 .
Soo powerviruses like y-cruncher won't destabilize the CPU by overcurrent or P95 similar loads

Ooor what also works , is just utilizing curve optimizer with open EDC limit
More voltage will be pushed, but also more negative CO can be used to "fight against it"
Many methods are possible, Matisse generation had a similar use where "enabling PBO" pushed 75-125mV more into the CPU for no reason. They all used a negative vcore offset 
Or limited EDC for "less voltage = more frequency" , but here EDC is used for something more important ~ soo only TDC limit can be used to limit voltage
PPT limit is rather a powersuply hardcap limit. You don't want any limiter there as it will lower frequency in general


----------



## Veii

XPEHOPE3 said:


> Unstable on 18.07:


Error 4
PCB crash 
House current or early on "better" training
Generally PCB crash by overvoltage

I like to test at night, as nightpower is cleaner than day time
But you seems like unluckily where on the edge of stability
Can only recommend to work away this strong RTT_PARK , but you'll know what to do


----------



## Veii

adversary said:


> what you exactly mean by "But then daisy chain layout comes in as a problem"?
> is daisy chain ok for 2 dimms generally, or it is ok only with dual-rank 2 dimms?
> 
> I run 32GB dual-rank with daisy chain board now.
> in future, if we hopefuly get Zen3 refresh, I was roughly planning 12 core CPU, most probably to keep same RAM as it provided really good scores, and most likely 2 DIMMs type board (as I plan to keep same RAM). keeping eye if MSI Unify-X with X570S will come out (and will check all other specs, and expirience from others, of course).
> 
> but would like to get overall some better insight on daisy chain, 2 DIMMS type boards, and dual-rank RAM.
> 
> (if you need to know PCB layout of this RAM kit, I can picture it or check or provide link of it, it is not definitely B0, it is B1 or B2).


Daisy chain still will split current with the Slave set to some extend
Pure 1 DPC boards , will not
T-Topology split it equally 50/50 with all 4 slots, but this 50% was a bit too weak for A2 PCBs , which love current
I still think it would've been better to stay on T-Topology, but AMD is the engineer here

Daisy Chain is a bit "strong" for A0 PCBs, which are very sensitive to changes and badly balancing die instantly (well they show first lost memory channels before death)
Daisy Chain is fine enough for 2 dimms, technically "the better option" according to AMD
More current to them (A2) and all is fine
But you still have to split current with 2 more empty dimm slots and let it flow through them before it reaches your main dimms
It's a waste, but people like many dimm setups
Can not understand why we couldn't just keep it the old days. All 4 dimm boards where T-Topology, Some that are Daisy-Chan give them dual stack support (ASUS DR DC) (intel Z series only ~ 2 dimms on one dimm PCB)
and keep some more 2 dimm only pcb's out there for OCers
All was fine that way, but AMD had to enforce Daisy Chain onto everyone
Eh "every board should behave the same" mentality 

You are fully fine with 2x DR, but you will have a very bad time with 4x DR. 4xSR still will be a bad time, but possible at least
The slave set just barely get's anything after the main set uses all
AMD will know what they do, but i really dislike 4 dimms on Daisy-Chain. Such a bad idea to begin with and hard to work without RTT's redesign

EDIT:
If there where more mATX or ATX 2 dimm boards, i'd consider not only going for ITX
But so far, ITX it is - just that it lacks a 2ndary PCIe slot for expansion and capture-cards

Thunderbolt was part of the resolve, if it would for once function well
_~enough ranting~_


----------



## Blameless

XPEHOPE3 said:


> Anyone knows why a setup which was TM5 stable can become TM5 unstable?


Differences in memory training or countless potential environmental factors can do this, especially if you're near the edge of stability.

Took me a month to dial in settings for a mismatched 4x32GiB setup on one of my systems because setting that would pass while cold wouldn't pass while warm, settings that would pass while warm wouldn't pass while cold, and settings that could pass both wouldn't always train correctly. Probably tried a hundred permutations of settings before I found something that I couldn't make error eventually and that would always pass training.


----------



## XPEHOPE3

Veii said:


> I like to test at night, as nightpower is cleaner than day time


Well, failed test was run overnight while passed test was run from like 10 am to 17 pm. BTW that can be seen from TM5 interface  


Veii said:


> But you seems like unluckily where on the edge of stability
> Can only recommend to work away this strong RTT_PARK , but you'll know what to do


How is it possible to verify if I'm "on the edge of stability" or not? Running TM5 and getting the first error after 5h of testing is too slow  Also @Blameless didn't you come up with any hints in the end? Like "edge of stability settings train much harder" maybe?

Also I'm yet to see anyone running RTTPark other than /1 on 64GB RAM. The best I did was /2, but not memclk 3867:


----------



## spajdr

@Veii Thank you for your valuable information


----------



## Audioboxer

Veii said:


> Daisy chain still will split current with the Slave set to some extend
> Pure 1 DPC boards , will not
> T-Topology split it equally 50/50 with all 4 slots, but this 50% was a bit too weak for A2 PCBs , which love current
> I still think it would've been better to stay on T-Topology, but AMD is the engineer here
> 
> Daisy Chain is a bit "strong" for A0 PCBs, which are very sensitive to changes and badly balancing die instantly (well they show first lost memory channels before death)
> Daisy Chain is fine enough for 2 dimms, technically "the better option" according to AMD
> More current to them (A2) and all is fine
> But you still have to split current with 2 more empty dimm slots and let it flow through them before it reaches your main dimms
> It's a waste, but people like many dimm setups
> Can not understand why we couldn't just keep it the old days. All 4 dimm boards where T-Topology, Some that are Daisy-Chan give them dual stack support (ASUS DR DC) (intel Z series only ~ 2 dimms on one dimm PCB)
> and keep some more 2 dimm only pcb's out there for OCers
> All was fine that way, but AMD had to enforce Daisy Chain onto everyone
> Eh "every board should behave the same" mentality
> 
> You are fully fine with 2x DR, but you will have a very bad time with 4x DR. 4xSR still will be a bad time, but possible at least
> The slave set just barely get's anything after the main set uses all
> AMD will know what they do, but i really dislike 4 dimms on Daisy-Chain. Such a bad idea to begin with and hard to work without RTT's redesign
> 
> EDIT:
> If there where more mATX or ATX 2 dimm boards, i'd consider not only going for ITX
> But so far, ITX it is - just that it lacks a 2ndary PCIe slot for expansion and capture-cards
> 
> Thunderbolt was part of the resolve, if it would for once function well
> _~enough ranting~_


Thanks, this is also pushing me to go 2x16GB DR to get 32GB rather than 4x8GB SR when looking at these Trident Z RGB/Neo kits. Even though a poster a page or so back has a reaaaaally nice 3600CL16 4x8GB set. But I guess that's the luck of the draw in the world of memory.


----------



## Veii

XPEHOPE3 said:


> Well, failed test was run overnight while passed test was run from like 10 am to 17 pm. BTW that can be seen from TM5 interface
> How is it possible to verify if I'm "on the edge of stability" or not? Running TM5 and getting the first error after 5h of testing is too slow  Also @Blameless didn't you come up with any hints in the end? Like "edge of stability settings train much harder" maybe?
> 
> Also I'm yet to see anyone running RTTPark other than /1 on 64GB RAM. The best I did was /2, but not memclk 3867:
> View attachment 2517885


That's unfortunate, but you can not know unless you push further and further
I currently have issues with +/- 20mV , or if one timing is missmatching everything breaks
Can not lower SD, DD's to 1-4-4-1-6-6 anymore the "easy way" . It times out this time

I unintentionally ignored that you run such high capacity
Then for sure go for RTT_WR /2
maybe even /1 but /2 has to work
Just WR change, changes how both NOM and PARK behave, soo you'll surely face couple of CMOS reset scenarios
If "nothing" changes , in the case of nothing negative happens ~ then all is good
Only when you go with lower timings, you'll notice instantly any negative change

Currently "as long as it doesn't make problems" but is weaker, ~ rather prefer such


Audioboxer said:


> Thanks, this is also pushing me to go 2x16GB DR to get 32GB rather than 4x8GB SR when looking at these Trident Z RGB/Neo kits. Even though a poster a page or so back has a reaaaaally nice 3600CL16 4x8GB set. But I guess that's the luck of the draw in the world of memory.


8gb SR kits remained better binning overall
I really wish there was a successor to the 8gb Vipers
The TeamForce ARGB 3600 are not bad at all (hidden gem) , but are designed like a sparkly stone. Too much RGB noise for my taste. Yet can not deny CL12-12 benchmarks by cm87
Better results than i can get with my cheap b-dies ~ their PCB is better. Eh every persons PCB here is better

Pick what you feel comfortable with
Either you pay by money or by time at the very end.
The hardware nearly never is the issue 

If you have the motivation, on the dark hero i played with 4x8 A2's
Yes the board was Ok'ish but i didn't have much fun with it. Mostly WHEA related with 3 CPU swaps (two 5950X)
You can get 4x8 to work, but it remains a pain 'n a half. For the huge pricetag it asks, i really can not recommend it neither for CPU CO (CTR) OC or memOC
It's not a good practice to mix two NIC brands on one board. Even when all intentions where good to begin with

EDIT:
You know what i should try,
Mixing Rev.E A2 with B-Die A0 on the ProArt 🤭
Just considering the tRCD 18 wall, might be only for high Freq scenarios to challenge myself - as Rev.E seems to keep that hardwall on higher freq. Soo it should equalize itself
Someday as a challenge & content piece surely ~ just to have it done.
The moment of time i can sacrifice my nice vipers - as they may die from such experiment 

@Nighthog are your Rev.B on A3 or A2 PCB ?
How direct / curvy are the PCB traces
I got no luck in hitting a micron A3 PCB sadly


----------



## Blameless

XPEHOPE3 said:


> How is it possible to verify if I'm "on the edge of stability" or not?


If any tightening of timings, reduction in voltage, or minor changes to drive strengths result in immediate instabilities.



XPEHOPE3 said:


> Running TM5 and getting the first error after 5h of testing is too slow


Then do all your memory testing at a clock step higher than you plan on actually using, or, if you think you may be temperature limited, use higher ambients or lower case fan speed settings than you'll use in practice.

I also notice you have GDM disabled...if you're running T2 and all even timings anyway, disabling GDM will provide essentially no benefit, and could still significant harm stability.


----------



## XPEHOPE3

Veii said:


> Currently "as long as it doesn't make problems" but is weaker, ~ rather prefer such


I thought the same and reverted to 3867-16. At least it posts every time or every other time, although to tPHYRDL 26/28 often instead of 26/26.


Veii said:


> I unintentionally ignored that you run such high capacity
> Then for sure go for RTT_WR /2
> maybe even /1 but /2 has to work
> Just WR change, changes how both NOM and PARK behave, soo you'll surely face couple of CMOS reset scenarios


I tried RTTWR /2 on previous BIOS and never posted. Probably because it was the only setting changed, while you probably mean to change other RTTs as well, or maybe something else?

I actually thought of persuading 1T instead of 15 on primaries to drop latency. A it's probably the only optimization left for me...

Also @Veii what do you think of tRAS=2*tRP rule from the recent amazing screenshots above? People are setting records with tRP-tRAS-tRC 12-24-36, 14-28-42 or something.


----------



## XPEHOPE3

Blameless said:


> I also notice you have GDM disabled...if you're running T2 and all even timings anyway, disabling GDM will provide essentially no benefit, and could still significant harm stability.


On my screenshots tRCD*=tRP=15. Also I preferred to be on the same page with Veii-the-think-tank regarding GDM otherwise his help might have been unusable for my GDM-on setups.


Blameless said:


> If any tightening of timings, reduction in voltage, or minor changes to drive strengths result in immediate instabilities.


Exactly my case =/ Any changes here render TM5 unstable: VDIMM 1.53->1.54, CAD_BUS 40-20-30-20 -> 30-20-30-20, procODT 40->36.9. And no timings can be lowered 
I persuaded 15 primaries to know the limits. Probably I'll get better limits from 16-flat...


Blameless said:


> Then do all your memory testing at a clock step higher than you plan on actually using, or, if you think you may be temperature limited, use higher ambients or lower case fan speed settings than you'll use in practice.


I can't post higher memclk. And I'm using nature uses higher ambients now than my PC is going to encounter.


----------



## Audioboxer

_Attempts to have a look at GDM disabled 1T_

Yikes!

_Walks away_

🤣

I think I'll take my 57.2ns on 2T and be happy! Talk about TestMem5 errors if not reboots/BSOD.

Anyway, I've bought some F4-4000C16D-32GTZR so I'll have some fun with it in the days to come. Fingers crossed it performs a bit better or is easier to work with than my 3200C14. Stuck with DR in the end, it's what I have a little experience with.

3800 14 flat will be the dream, but even if I can get 14-15-x-x that'll be nice.


----------



## gled_fr

so now I am puzzled,

I got errors on this:








Ok ,error 4 and 0, let's lower ClkDrvStr and RTT_NOM ( since rzq/7 should be ok up to 1.5V from what I read here, and I am running 1.45V ).

Now I lost .7ns by just modifying that: ???








can someone explain why the latency increase please ? very puzzled...

And it's clear my ram doesn't like rzq/7, rzq/6 goes back down to high 55.








Restarting 8h of tm5, starts to be hard to stabilize those 15 flat...


----------



## Robostyle

*Veii*


Veii said:


> If you have the motivation, on the dark hero i played with 4x8 A2's
> Yes the board was Ok'ish but i didn't have much fun with it. Mostly WHEA related with 3 CPU swaps (two 5950X)


Wait - so whea and fclk problems differ between same vendor motherboards?


----------



## XPEHOPE3

gled_fr said:


> can someone explain why the latency increase please ? very puzzled...


It's normal if you ran just one test. If it's on average, it's not. Also L1 read cache increased for some reason.
Did you check what was tPHYRDL on the second stick? It might have changed from 26 to say 28 and cause sub 1ns gain in latency.


----------



## Audioboxer

Hmm, before my order ships later tonight/tomorrow, quick question

DDR4-4000MHz CL17-17-17-37 1.35V (SR 4x8GB)

DDR4-4000MHz CL16-19-19-39 1.40V (DR 2x16GB)

Both of these are b-die but what technically has the better chance of achieving 3800 14 flat? I seen someone mention they managed it on the CL16 set, but due to its tRCDRD XMP value I think 15 is more likely.

But first set is obviously 4xSR to contend with.


----------



## Blameless

XPEHOPE3 said:


> On my screenshots tRCD*=tRP=15.


My mistake. Was hard to see the images on my laptop.



XPEHOPE3 said:


> Also I preferred to be on the same page with Veii-the-think-tank regarding GDM otherwise his help might have been unusable for my GDM-on setups.


If you do back off to 16 on the rest of the primaries, it won't hurt anything to test GDM both ways.



XPEHOPE3 said:


> Exactly my case =/ Any changes here render TM5 unstable: VDIMM 1.53->1.54, CAD_BUS 40-20-30-20 -> 30-20-30-20, procODT 40->36.9. And no timings can be lowered


Lower the margin the more difficult it is to be certain of it. In such scenarios, you have to be prepared to tolerate extremely protracted test cycles, unless you want to risk intermittent, and inopportune, instability.



gled_fr said:


> Now I lost .7ns by just modifying that: ???


You may want to run the bench a few times, rebooting between and averaging the results (or just dropping the best and worst set), to account for the possibility of training outliers that could influence things.


----------



## Veii

XPEHOPE3 said:


> I thought the same and reverted to 3867-16. At least it posts every time or every other time, although to tPHYRDL 26/28 often instead of 26/26.
> I tried RTTWR /2 on previous BIOS and never posted. Probably because it was the only setting changed, while you probably mean to change other RTTs as well, or maybe something else?
> 
> I actually thought of persuading 1T instead of 15 on primaries to drop latency. A it's probably the only optimization left for me...
> 
> Also @Veii what do you think of tRAS=2*tRP rule from the recent amazing screenshots above? People are setting records with tRP-tRAS-tRC 12-24-36, 14-28-42 or something.


I think primaries are harder to stabilize than Command Rate. Command rate only helps on higher frequency, but low tRCD will purely refuse to run nevertheless if 2T or 1T

" tRAS = tRP*2 ",
Generally hold nothing from/on it ~ even hear it for the first time

tRP needs to be there to (p)recharge, and it optimally matches tRCD delay for both read and write, or rather for "average", when you have enough unused current left
But tRAS+tRTP seems to work as tRASmin , as you can see on my timings

I am not sure yet if it really is better than the other tRAS+1=tRC exploit for 1x tFAW
But both seem to focus on burst refresh mode instead of the typical tRCD*2 (+ potentially tBURST or tCCD_L) type of delay math
i do think all of them work, but i am not sure what really leads to best throughput for all datasets
Would need to collect couple of "done" timing sets (work i do now for example) and compare them then with SiSandra
Which methods leads to universally better dataset perf ~ as that is memOC all about.
You can finetune DDR/SDRAM to perform better for every type of dataset, yet it will show weakness on another ones. Soo lower is not always better

Intel guys technically don't have tRC , soo tRAS*2+tBL is common there
Same we can do with tRAS+1 = tRC & 1x tFAW exploit

I don't know what really is better yet
But i don't like this tRAS ruleset
I do start to like tRAS= tRCD+tRTP & tRRD_L = tRTP one, tho it requires everything to be perfect ~ soo unlikely recommendable as entry ruleset.
tRCD*2 is easier and consistent & tRCDavg*2 + tCCD_L is even more consistent as Failsafe option (micron, hynix, spectek)
=================================
Someday when i have enough presets and find programmer friends
~ i / he should make an app for such XMP import & preset configuration.
Soo people can select same XMP timings but "translated" to different presents for different dataset optimisations
Then we'd have a memOC programm and a CPU OC programm 🤭


----------



## gled_fr

XPEHOPE3 said:


> It's normal if you ran just one test. If it's on average, it's not. Also L1 read cache increased for some reason.
> Did you check what was tPHYRDL on the second stick? It might have changed from 26 to say 28 and cause sub 1ns gain in latency.


I did not check the tPHYRDL on the second stick indeed ! Thank you, will do next time ! 

I ran a couple tests though and latency were consistently in the mid 56s.

Chasing those 1time errors after 7+hours is.. interesting


----------



## gled_fr

Veii said:


> Someday when i have enough presets and find programmer friends
> ~ i / he should make an app for such XMP import & preset configuration.
> Soo people can select same XMP timings but "translated" to different presents for different dataset optimisations
> Then we'd have a memOC programm and a CPU OC programm 🤭


I don't have your knowledge on OC subjects, but i would happily help with the programming part. Hit me up on that when you want !


----------



## Veii

gled_fr said:


> I don't have your knowledge on OC subjects, but i would happily help with the programming part. Hit me up on that when you want !


I don't think i can afford you for now🤭
EDIT:
But it can be possible to make a funding and funding split option for the work~
CTR works equally , from a business perspective
I just don't like the selected subscription based decision on it
Donationware methodology usually works better


----------



## mongoled

XPEHOPE3 said:


> I was asking if I missed something from your posts (like some fact or some argument) because I didn't see the full logic behind your statement that such stick ordering *is better than the other*. It appears it is no better since you can't get 14-flat anyway. Did you make performance comparison between current "good-bad-good-good" setup and, for example, "bad-good-good-good"? Or maybe did you make timings comparison and one setup allowed for tighter timings than the other? If you did something along these lines and posted it somewhere, I could have missed that, and hence I asked the question.


Good question



We know on ryzen daisy chain motherboards that A2 and B2 are the "optimized" dimm slot combination as per the motherboard notification you get when you put the RAM into slot A1/B1. The logic is that my two "weaker" RAM modules will have a better chance of tighter secondary timings when placed in the "optimized" dimm slots.

The first time I tried this I did hope it would make a difference with regards to running tighter tRCDRD but alas no change.

I have not tested other combinations using the following logic, seeing ive tested the "bad" tRCDRD stick in the "best" dimm slot (A2) and it could not do tRCDRD @14 there was no reasoning to try the other dimm slots.


----------



## XPEHOPE3

Veii said:


> for different dataset optimisations


Can you please elaborate on what are you calling a dataset? I saw multiple times for example in error descriptions that word ("while for bigger datasets tRP, tRFC") which make little sense in the context I read it.

@mongoled 
Yeah, good theory, but not supported by practice in that particular case. Even opposite as in @craxton 's case.


----------



## Veii

XPEHOPE3 said:


> Can you please elaborate on what are you calling a dataset? I saw multiple times for example in error descriptions that word ("while for bigger datasets tRP, tRFC") which make little sense in the context I read it.


TM5 description have testing datasets, but they are with a different meaning

Usage datasets are what SiSandra shows, 256kb 512kb, 2MB and so on

Well in the end it's not that far off, 
Package Dataset Size


mongoled said:


> We know on ryzen daisy chain motherboards that A2 and B2 are the "optimized" dimm slot combination as per the motherboard notification you get when you put the RAM into slot A1/B1. The logic is that my two "weaker" RAM modules will have a better chance of tighter secondary timings when placed in the "optimized" dimm slots.


it's because Daisy Chain link attaches to the first and 3rd slot, but the wall/end arrives on slot 2 and 4
If you optimize RTTs to cut properly it might even work with slot 1 & 3
But it's hard to prevent signal reflection back , when there is nothing into slot 2 & 4 ~ soo DIMMs are unstable

Also there was a big issue with stock coolers heating up the first dimm - which caused in the server segment couple of issues
Soo dimm 2 & 4 changed to primary ones , early on it was 1 & 3 
But for industrial purposes , it changed and because stock coolers remain performing the best as "push down" options ~ yet dimms where dying that way


----------



## gled_fr

Veii said:


> I don't think i can afford you for now🤭
> EDIT:
> But it can be possible to make a funding and funding split option for the work~
> CTR works equally , from a business perspective
> I just don't like the selected subscription based decision on it
> Donationware methodology usually works better


I would just take 10-20% of the donations in such a project, after all it is mostly implementing your work and research, the programming part is not the hardest


----------



## Veii

gled_fr said:


> I would just take 10-20% of the donations in such a project, after all it is mostly implementing your work and research, the programming part is not the hardest


If you only knew from somebody who can not code at all ~ yet has many ideas ^^'
20% only works with 2-3 people, would feel bad bellow 30% with one person only
~ might result in less than minimum wage in the US , can't do this (only could do it if i had to pay another 20% for an UI designer for example) ~ soo 40/60,
but only 20% is not enough to keep up the motivation.

In what are you specialised ?
Programming languages, Eco Systems ?
I wanted to learn android studio, but miss time to focus on learning all essential knowledge paths & then also learn to design an UI ~ it's a lot of work

Haven't fully figured out where ABL Memory training - Debug Values sit, soo i can not automate it fully sadly.
Meaning, it mostly requires not only a rule based visual section (which shouldn't be that hard)
But optimally a Stable/Not stable question-response field. Soo people don't have to watch over somebody's head & guide them what they should do.

DRAM Calculator had a lot of pretested presets & even couple of benchmarks plus assisting tools
Yet it still required community input & it could not really generate much at all. Because every performant preset was based upon Yuri's testing.
Such took him a lot of time and i understand why he couldn't maintain it anymore.
A tool that works on rule based generation - with "presets" that adjust themself based on what we learned throughout the time. Doesn't need a maintainer, once the code is solid
It skips waiting for answer frustration and if the user could have this as not only desktop but mobile app ~ it would make everything far easier for them.

The Problem to all is really that A LOT of "IF" scenarios must be build
Which is soo much work and such huge codeblock ~ it's impossible to pay far bellow minimum wage.
There are too many scenarios why something could be unstable & a program that takes the user in their hands step by step ~ simply doesn't exist 

EDIT:
Ultimately, all % depends on the Team size & if it ends up a company that does more than 1 project for Zen (tax and stuff)
But the first person on a team needs a higher than average payment ~ later it averages out based on the work type and hours spend
EDIT 2:
Also depends if server costs are associated with it or app/program license costs ~ for example Apple / Android Dev costs and similar


----------



## gled_fr

Veii said:


> If you only knew from somebody who can not code at all ~ yet has many ideas ^^'
> 20% only works with 2-3 people, would feel bad bellow 30% with one person only
> ~ might result in less than minimum wage in the US , can't do this (only could do it if i had to pay another 20% for an UI designer for example) ~ soo 40/60,
> but only 20% is not enough to keep up the motivation.
> 
> In what are you specialised ?
> Programming languages, Eco Systems ?
> I wanted to learn android studio, but miss time to focus on learning all essential knowledge paths & then also learn to design an UI ~ it's a lot of work
> 
> Haven't fully figured out where ABL Memory training - Debug Values sit, soo i can not automate it fully sadly.
> Meaning, it mostly requires not only a rule based visual section (which shouldn't be that hard)
> But optimally a Stable/Not stable question-response field. Soo people don't have to watch over somebody's head & guide them what they should do.
> 
> DRAM Calculator had a lot of pretested presets & even couple of benchmarks plus assisting tools
> Yet it still required community input & it could not really generate much at all. Because every performant preset was based upon Yuri's testing.
> Such took him a lot of time and i understand why he couldn't maintain it anymore.
> A tool that works on rule based generation - with "presets" that adjust themself based on what we learned throughout the time. Doesn't need a maintainer, once the code is solid
> It skips waiting for answer frustration and if the user could have this as not only desktop but mobile app ~ it would make everything far easier for them.
> 
> The Problem to all is really that A LOT of "IF" scenarios must be build
> Which is soo much work and such huge codeblock ~ it's impossible to pay far bellow minimum wage.
> There are too many scenarios why something could be unstable & a program that takes the user in their hands step by step ~ simply doesn't exist


I've been programming for more than 2decades now, had fun with many languages, used to do low level realtime communication on linux, still on it nowadays building rtc platforms. Tbh I have a full time job already, so my interest would be more to bring an easier way to people wanting to over clock their ram than depending on the income. If it brings some money, all the better, that would help, but it's more something i would work on in my free time.

The lots of IF scenarios are not too much a problem, it's probably a decision tree/loop to build, could even have a server component that evolves and the user part is just a frontend to read values from the computer/launch tests and all the calculations made on a server . that would make a mobile option easy actually. It's just time that could maybe also be optimized for some general rules ( a few decisions trees that refers to other decisions trees, no need to code that, rather just build a DSL that reads those decision trees ).

Making that decision tree remote also alleviate greatly the maintenance time of the code and makes it easier to deploy. 

Just a raw 2mn thought that needs to be polished but that is probably how I would start something like that.


----------



## gled_fr

First 30cycles passed, hopefully this is the one !! _crossing fingers_


----------



## XPEHOPE3

Veii said:


> TM5 description have testing datasets, but they are with a different meaning


Let's focus on exactly the meaning of "dataset" and dataset sizes in your TM5 error descriptions. What do you mean by those? It doesn't seem to be about "32Mb" within "Variable tests 32Mb" string. Also it doesn't seem to be about the number of TM5 cycles or tests passed until any of the errors.



Veii said:


> Usage datasets are what SiSandra shows, *256kb 512kb, 2MB* and so on


Bold text is not about "dataset", it's about "buffer size" a program can use to perform data operation on (copy, move, free, etc.) Regarding programs doing performance measurements, they obviously average timing results of lots of operations (copying, reading, etc). _Total data_ copied, read, etc. used in those operations is the _dataset_. It may be bigger or smaller in terms of bytes, bigger or smaller in terms of number of buffers (not the same thing!). Both buffer data and buffer locations can be fixed, random, or otherwise deliberately programmed e.g. to stress potential caches, like in TM5.


Veii said:


> Well in the end it's not that far off,
> Package Dataset Size


What's that about?.. What's not far off from what?  😅 What is "Package Dataset Size"?

That whole comment didn't make your usage of the word "dataset" any more clear, only less


----------



## Veii

XPEHOPE3 said:


> Let's focus on exactly the meaning of "dataset" and dataset sizes in your TM5 error descriptions. What do you mean by those? It doesn't seem to be about "32Mb" within "Variable tests 32Mb" string. Also it doesn't seem to be about the number of TM5 cycles or tests passed until any of the errors.


In TM5's case, it's random data created, which then is split into specific data-sizes chunks, and copied back and forth with selected DDR Matrix location
Soo it mostly is bank to bank, chip to chip - bank group to bankgroup or dimm to dimm
That's what i ment by dataset "size"
There are tests which use a fixed testing pattern of 64Mb inside their set sector , or copy it back
There are tests which then collect all together and mirror a 128mb clone ~ deciphering how TM5 exactly works only the cfg makers know
But "Variable Test" & "Random Test" perform different.
#5 error description is quite old, i should renew it but it remains correct
It's a mirror move without a fixed data "size" but rather copies everything.
It comes after 10 which i count as "one of couple" burst test sizes. It's hard to explain for me

SiSandra the multi-core efficiency test, is also using fixed sizes which land in the CPU cache and are moved towards ram and back to the cache, then from one core to another
Aida64 does the method you explain as buffer sizes , but SiSandra has different testing methods.
In order to build a graph with different "buffer sizes" it will need to copy and and read it out ~ yet it's not always random read tests
That's what i call a "dataset size" or "instruction set size".
How it exactly tests the access latency and bandwidth is unknown to me - but it states different "dataset sizes" which it tests

I use this wording from Donghyuk Lee's PDF about "optimizing memory for different dataset sizes & program algorithm sizes"
Page 45 ~ while he writes it here as Segment Length


https://arxiv.org/pdf/1604.08041.pdf


This is a big piece i learned from while starting to build a tRFC based calculator - but kept missing crucial information

Problem is , i understand what i mean - but should likely change how i call it or rephrase
At first wiki was only made for me , but the requests for support increased too much. I should edit couple of descriptions to give a more clear picture. I mean it's in works anyways. But it depends on the patterns which tests error with/from
This here online is a very very rough sheet to help what to focus on

Oh i don't think this PDF here is the original i read. It misses couple of pages, but it looks to be close. Found couple of graphs i remember


gled_fr said:


> Tbh I have a full time job already, so my interest would be more to bring an easier way to people wanting to over clock their ram than depending on the income. If it brings some money, all the better, that would help, but it's more something i would work on in my free time.


This makes sense 
Yes it clearly should remain donationware at best - supportive work only
As someone who started with fully nothing and learned from free resources ~ i value the ability to inform yourself without having to base your knowledge based on your wallet.
A software should not be restrictive when it is crucial for the persons functionality. (I mean ok it doesn't help getting XMP to run, not fully ~ but it could with TM5 decipher support).
I have to talk with 1usmus closer on his TM5 config which we pretty much main at this point ~ but i think he'll be fine as support for his tool is needed too. I'll resolve that part with him

Ultimately the dream would be full access to data-eye readouts but RAM loves to hang up a system in a not resettable state
Sadly fully automating it wouldn't work that easy unless we get support from people who can read, modify and decipher SMU ~ to modify them in realtime on Windows or Linux
Some of them are Shamino, 1rusanovBG (ZenTimings, ZenState), The Stilt and i think couple more modders. Well and 1usmus also

All of them have busy private life's and maaybe 1rusanovBG (InfraredBG) could assist on such project if it ends up OpenSource + couple more PSP Tool (github) supportive People
But that's the "ultimate goal" and rather a dream for now. I miss knowledge to read export such readings. The bios (SMU) supports a dump of it tho. Just no idea where it places it to grab the data.

Soo my visualisation is rather something along the lines of projects we already have - like the DRAM calculator
Just purely ruleset based ~ with toggleable "modes" , or "exploit presets" who modify imported XMP profiles
Optimally something a mobile user can access and type their generated XMP values in. Then actively ask & respond if it was stable or with what it error'd
A "Holding Hand" Utility 
It's too time-consuming answering everyone with mostly the same answers
And people can easily try experimental exploit presets or share their own research.
Better than only waiting on one Dev to pretest these timings and give "done presets".
Done universal rulesets for specific exploits ~ makes everything easier.


----------



## craxton

i think its safe to say, im "good enough"
(one is win 11, the other is done thru win 10)
but TM5 does pass win 10 as well, 
only difference between times is that i can tell is if i dont run my "auto" 
start programs. takes off around 7 minutes?? unless thats the difference between win 10 and win 11...


----------



## gled_fr

Veii said:


> This makes sense
> Yes it clearly should remain donationware at best - supportive work only
> As someone who started with fully nothing and learned from free resources ~ i value the ability to inform yourself without having to base your knowledge based on your wallet.
> A software should not be restrictive when it is crucial for the persons functionality. (I mean ok it doesn't help getting XMP to run, not fully ~ but it could with TM5 decipher support).
> I have to talk with 1usmus closer on his TM5 config which we pretty much main at this point ~ but i think he'll be fine as support for his tool is needed too. I'll resolve that part with him
> 
> Ultimately the dream would be full access to data-eye readouts but RAM loves to hang up a system in a not resettable state
> Sadly fully automating it wouldn't work that easy unless we get support from people who can read, modify and decipher SMU ~ to modify them in realtime on Windows or Linux
> Some of them are Shamino, 1rusanovBG (ZenTimings, ZenState), The Stilt and i think couple more modders. Well and 1usmus also
> 
> All of them have busy private life's and maaybe 1rusanovBG (InfraredBG) could assist on such project if it ends up OpenSource + couple more PSP Tool (github) supportive People
> But that's the "ultimate goal" and rather a dream for now. I miss knowledge to read export such readings. The bios (SMU) supports a dump of it tho. Just no idea where it places it to grab the data.
> 
> Soo my visualisation is rather something along the lines of projects we already have - like the DRAM calculator
> Just purely ruleset based ~ with toggleable "modes" , or "exploit presets" who modify imported XMP profiles
> Optimally something a mobile user can access and type their generated XMP values in. Then actively ask & respond if it was stable or with what it error'd
> A "Holding Hand" Utility
> It's too time-consuming answering everyone with mostly the same answers
> And people can easily try experimental exploit presets or share their own research.
> Better than only waiting on one Dev to pretest these timings and give "done presets".
> Done universal rulesets for specific exploits ~ makes everything easier.


DM me if you want, happy to provide a skeleton that could be used for such a 'guiding hand' tool. 

I can see building pretty easily a web version, usable on mobile phones while tweaking the bios, and later adding an app that would use the web version API, adding more functions like testing and reading/setting values ...

I suppose a web version that asks the user to input the informations needed then starts to guide him should be OK to start ( for example ask the user to input info from zentiming then starts the process ).

Let me know, happy to start something like that !


----------



## gled_fr

gled_fr said:


> First 30cycles passed, hopefully this is the one !! _crossing fingers_
> View attachment 2517929


So In just realized TM5 was stuck on the same test for hours... Timer was still going up but stuck on cycle 36 test 15... Don't know if it was a bug of TM5 or something wrong with my settings ... Relaunched tm5 :/


----------



## gled_fr

OK so there's something real weird,

TM5 got stuck without errors again, computer still working and timer still going up, SSE speed though in ms/GB, first time I see this. Is it just a bug after 24h of testing without reboot or something wrong with my settings ?

I did a clean reboot and relaunched tm5 to check.
Getting puzzled a lot ...


----------



## Veii

gled_fr said:


> View attachment 2517938
> 
> OK so there's something real weird,
> 
> TM5 got stuck without errors again, computer still working and timer still going up, SSE speed though in ms/GB, first time I see this. Is it just a bug after 24h of testing without reboot or something wrong with my settings ?
> 
> I did a clean reboot and relaunched tm5 to check.
> Getting puzzled a lot ...


That usually means that one core/thred is crashing, and TM5 can not correct itself or continue
It just will hang up.

You should try to loop y-cruncher for a bit of time (1-7-0 key combination)
At least 4 loops, preferably more - of all tests
That should show voltage instability issues quite fast

On your screenshot i see that SOC is less than 40mV apart from IOD.
The absolute minimum is 40mV for Vermeer (38mV will hardcrash) , soo fixing the loadline or adding bit more SOC soo it droops to 1.1, likely will resolve the issue (Matisse liked a 50mV stepping)
cLDO_VDDP is also higher than VDDG CCD, technically both are runnable at the same voltage ~ but you might want to lower VDDP or increase CCD voltage
Take a read at this thread, if you haven't








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




They are still valid, just lower voltage ~ requires lower procODT, requires lower cLDO_VDDP and might require 1.8v CPU line at 1.83v as minimum


gled_fr said:


> DM me if you want,


I'll write you tomorrow 
It's 2:40AM right now. Usually fine for me and usually near my casual wake up time, but today was a long day ~ soo i'll write you after you wake up 👋


----------



## gled_fr

Veii said:


> That usually means that one core/thred is crashing, and TM5 can not correct itself or continue
> It just will hang up.
> 
> You should try to loop y-cruncher for a bit of time (1-7-0 key combination)
> At least 4 loops, preferably more - of all tests
> That should show voltage instability issues quite fast
> 
> On your screenshot i see that SOC is less than 40mV apart from IOD.
> The absolute minimum is 40mV for Vermeer (38mV will hardcrash) , soo fixing the loadline or adding bit more SOC soo it droops to 1.1, likely will resolve the issue (Matisse liked a 50mV stepping)
> cLDO_VDDP is also higher than VDDG CCD, technically both are runnable at the same voltage ~ but you might want to lower VDDP or increase CCD voltage
> Take a read at this thread, if you haven't
> 
> 
> 
> 
> 
> 
> 
> 
> AMD max overclocking voltage
> 
> 
> Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> They are still valid, just lower voltage ~ requires lower procODT, requires lower cLDO_VDDP and might require 1.8v CPU line at 1.83v as minimum


Thanks for the explanation and the link !

My voltages were still on Auto, I was waiting to try to stabilize the ram then move to IF 2000 and work on those at that time to get rid of the WHEA errors, I understand now it is all linked and need to work together 

Interesting is I tried to drop IOD at 1 and latency increased from 55.8 to 56.2, restoring IOD solved that right away.
Increased vsoc to 1.15 ( 1.1313 reported ), dropped vddp to 0.9 ( 0.8973 reported ) to match CCD and left IOD at 1.05 ( 1.0477 reported ).

[edit] unstable, working on it


----------



## craxton

gled_fr said:


> My voltages were still on Auto


as Veii mentioned running y-cruncher will tell alot..
i was HCI, TM5 (with furmark) stable. but i myself was crashing 
on y-cruncher on the third iteration. took me from 1.12 upto 1.15 SOC (50mv increments (DOWN) from SOC
to get stable. 29 iterations is what i ran (i started it before going to bed and let it be.)
which i might have 'over' ran it idk?
this is what i have now.... (nota 5950x tho)
BIOS REPORTED
CLDO_VDDP- .930 .929 
CCD - .980 .9799
IOD - 1.030 1.0271

my 5600x would do 2000/4000 without any whea issues at all 
but this 5800x however has well its worse than i am with my own issues.
so, are you aiming to run "2000" without shutting the WHEA logger off?
is that your end goal? atm this chip im running is pushing 1900fclk
even on unstable timings it has no issues WHEA wise, but above 1900
different story, have you tried anything higher? or are you already seen WHEA 19s 
as is???


----------



## gled_fr

craxton said:


> as Veii mentioned running y-cruncher will tell alot..
> i was HCI, TM5 (with furmark) stable. but i myself was crashing
> on y-cruncher on the third iteration. took me from 1.12 upto 1.15 SOC (50mv increments (DOWN) from SOC
> to get stable. 29 iterations is what i ran (i started it before going to bed and let it be.)
> which i might have 'over' ran it idk?
> this is what i have now.... (nota 5950x tho)
> BIOS REPORTED
> CLDO_VDDP- .930 .929
> CCD - .980 .9799
> IOD - 1.030 1.0271
> 
> my 5600x would do 2000/4000 without any whea issues at all
> but this 5800x however has well its worse than i am with my own issues.
> so, are you aiming to run "2000" without shutting the WHEA logger off?
> is that your end goal? atm this chip im running is pushing 1900fclk
> even on unstable timings it has no issues WHEA wise, but above 1900
> different story, have you tried anything higher? or are you already seen WHEA 19s
> as is???


Yes, currently testing vsoc 1.1250 ( reporting pure 1.1 ), vsoc 1.15 crashed right away, I also increased vddp back to 1V ( so vddp > CCD ).

2 iterations of y-cruncher so far, will let it run as long as possible but stability could be any of the two.

Endgoal is indeed IF2000/Ram 4000 with no WHEA errors and with CL15 or 14 if possible, slowly working my way there.

1900 is totally fine and happy, 1933 WHEA starts even if memtest pass. I was able to boot on a previous motherboard 2000 and pass tm5 at cl16 with my previous stable settings, but WHEA everywhere. With the current motherboard I don't even boot more than 1933.

Trying to stabilize for now 1900 cl 15, and learning a lot in the process, then move to cl14 which I think is doable ( lots of 6 and 0 errors last time I tried, but it booted ), and when i feel more confident to work on the infinity fabric stability, move toward 2000.


----------



## craxton

gled_fr said:


> Endgoal is indeed IF2000/Ram 4000 with no WHEA errors and with CL15 or 14 if possible, slowly working my way there.


id almost bet c14-14 is doable (with/or/without a fan)
unsure 4000c14 will be doable or (easy) to do anyhow...i can "boot" 4000/2000 c14 with 1.6V
but i didnt try to get that stable.....



gled_fr said:


> I was able to boot on a previous motherboard 2000 and pass tm5 at cl16 with my previous stable settings, but WHEA everywhere. With the current motherboard I don't even boot more than 1933.


i as well passed (all ram tests) at 4000mhz on this board/CPU (5800x) but was flooded with WHEA 19s 
i dont have another board atm, but as i stated my 5600x would do any FCLK from 100% 2033 and down 
without any lockouts and whea free... (regardless) of what voltages i was running....
this chip now however seems to have "SUPER" strange things happen with display dropouts, USB cutouts, audio issues
(with being 100% stable in ram tests) (now that i know) it needs this much voltage however to be "near/stable" 
at 1900/3800 i may myself give my 2000/4000 c16-16 profile another shot. 

only difference between now and then, is me having an unlocked "updated" bios thanks to Eder
strange when i first flashed it tho, went into bios and only AMD PBS options were present for overclocking.
now those as well as AMD overclocking and the other option "not sure" what its called. 

i am curious however since installing the 5800x "did it magically" awaken WHEAs that were "magically sleeping" 
before while using the 5600x, to where as if i were to install the 5600x again would it still be WHEA 19 free....
id have to imagine thats not the case and the 5600x is indeed just a "golden" sample IMC....orrrr
me dropping it somehow knocked the WHEA 19s out of it indefinitely, yes somewhat being serious with that last sentence....
none the less tho, will give it another shot once i get my day going after i "sleep" and wake up again.


----------



## mongoled

XPEHOPE3 said:


> Can you please elaborate on what are you calling a dataset? I saw multiple times for example in error descriptions that word ("while for bigger datasets tRP, tRFC") which make little sense in the context I read it.
> 
> @mongoled
> Yeah, good theory, but not supported by practice in that particular case. Even opposite as in @craxton 's case.


More like a hunch based on simple logic, theory would need more real data


----------



## mongoled

Veii said:


> That usually means that one core/thred is crashing, and TM5 can not correct itself or continue
> It just will hang up.


I am also getting this while playing with different Rtt values, ive been trying higher RttPark (RZQ/6 from 3) with lower RttNom (RZQ/5 from 7) this is coming from a stable CO and stable RTTs in the sense of completing TM5 runs while using 6/3/3


----------



## Audioboxer

Got two sets of the 4000C16 sets coming today, so I'll give both a whirl and see if one beats the other 👀

First port of call, making sure they boot RttPark 3 fine 😂


----------



## Robostyle

Having problems with lowering rcdrd to match other primaries, no matter how loosen other subs are or wgat Vdimm I set. Is it doable on dualranks, or thats just my kit being ****e?


----------



## mongoled

Audioboxer said:


> Got two sets of the 4000C16 sets coming today, so I'll give both a whirl and see if one beats the other 👀
> 
> First port of call, making sure they boot RttPark 3 fine 😂


Hours of fun !

May the OC Gods be merciful


----------



## reddify

Audioboxer said:


> Got two sets of the 4000C16 sets coming today, so I'll give both a whirl and see if one beats the other 👀
> 
> First port of call, making sure they boot RttPark 3 fine 😂


Here is a motivation, GL 
For RttPark 3, try to play with the DrvStr values a bit, it could help you.


----------



## Audioboxer

reddify said:


> Here is a motivation, GL
> For RttPark 3, try to play with the DrvStr values a bit, it could help you.


Very tasty. I'd be delighted if one of my sets can pull that off.

That's why I bought two 🤣 One will either get returned or sold on. Or potentially passed on to friends or family for some of the cost of purchase.

Though that write speed, what is going on there? lol!


----------



## Veii

Audioboxer said:


> Very tasty. I'd be delighted if one of my sets can pull that off.
> 
> That's why I bought two 🤣 One will either get returned or sold on. Or potentially passed on to friends or family for some of the cost of purchase.
> 
> Though that write speed, what is going on there? lol!


Perfect half -1, for 1CCD units
Mostly Fabric stability dependent, barely has to do with MCLK at all
Hitting perfect half of maximum FCLK/MCLK , will only happen once in a blue moon. Pretty much impossible. Got it only once and never again, as Windows uses resources for it

Check the PCBs if they are identical, before you plug them in


gled_fr said:


> Thanks for the explanation and the link !
> 
> [edit] unstable, working on it











This block potentially can help you
for DR it's +2 on procODT, near the 34ohm range
And -2 as minimum on RTT_PARK (/4 and lower, /3 is fine for you)
* for many dimm setups it's +1 & -1, as they remain 8gb dimms

SOC , CCD, IOD, are all 2100 FCLK focused
But you can give this a try too
840mV cLDO_VDDP, 960ish CCD, 1040ish IOD, 1085 (1080 GET) SOC
Should be fine with only 1900 FCLK ~ y-cruncher will tell you 

Generally VDDG CCD voltage will make you issues in the long run
procODT to run low needs ClkDrvStr bump - which needs AddrCmdDrvStr bump (assisting memory training)
and low procODT to run, all other voltages needs to be low.
cLDO_VDDP that low can make issues beyond 1900 MCLK, but it should run. It doesn't limit 2100 FCLK ability tho

At the very end if this runs and you miss around 1ns latency, bump up that 1.8v rail.
1.83 is fine, 1.85v won't complain. 1.93v is about the limit where it won't complain ~ that max limit also depends on procODT & cLDO_VDDP, soo your mileage will vary
* if that 1.8v rail does no changes, better revert it ~ but sometimes it's needed. Depends on the voltages you run. This is experimental but runs, and low procODT is always nice ot have


----------



## Veii

craxton said:


> i am curious however since installing the 5800x "did it magically" awaken WHEAs that were "magically sleeping"
> before while using the 5600x, to where as if i were to install the 5600x again would it still be WHEA 19 free....
> id have to imagine thats not the case and the 5600x is indeed just a "golden" sample IMC....orrrr
> me dropping it somehow knocked the WHEA 19s out of it indefinitely, yes somewhat being serious with that last sentence....


Haha, i can say my unit is not dropped
But it's more funky. Same goes to i think it was kim nk, with also a 1st supply dual CCD unit with broken DPM links (unrecognized) soo he also run 2100 FCLK without issues

Tho about the "magical awake" part
It's funny, my board initially reported
5/6 WHEA loggers
Switched to the ASUS Creator, then it changed to 9/10 loggers
Now i'm back on the ITX and it remains 9/10 loggers
















Somebody would think the new windows updates (10 and now 10X) would have changed / added it
but that's across 3 wipe-installs and identical behavior

Rather shows to me that the ProArt updated something in PSP FW
Tho yet there are no #19's

Porting new microcode from 1203A down to 56.50 1200 gave me a 2100 lock
But using now "pure" 56.53 A, the lock is gone. Memory training is beyond broken on 2100 MCLK, but 2100 FCLK boots easily and remains stable.
2133 boots but eats me 4ns away. (sttill feels like it switches to 2:1 mode somewhy). At least no 20+ anymore
=====================
Also F, so close
(EDIT: oh i hit perfect perfect half on write, heh)























1:27:00 no error, 1:28:00 one "timeout issue" 💤
Might be really tRFC 2 & 4 at this point, but i nearly got it running @ 1T

Figured that low primaries like more low SCL.
Figured tWRRD delay is bad, but it's barely doing anything to latency. 0.1ns maybe (inside test-by-test variance)
Lower SCL gave the bandwidth benefit. No adjustments to tWRRD (3-3 then 8-4) was bad, and 3-3, 8-1 could work but still desynced somewhere after time. 2-2 8-6 now works
(well nearly, but no perf or latency loss)
Soo the added tWRRD delay does close to no perf penalty by subtracting lower SCL benefit from it. Same latency, bit more bandwidth ~ but sync'ing is an issue


----------



## byDenoso

Thanks to @Veii , i've managed to get a new stable OC.
There's still room to improvement.


----------



## gled_fr

Veii said:


> View attachment 2517977
> 
> This block potentially can help you
> for DR it's +2 on procODT, near the 34ohm range
> And -2 as minimum on RTT_PARK (/4 and lower, /3 is fine for you)
> * for many dimm setups it's +1 & -1, as they remain 8gb dimms
> 
> SOC , CCD, IOD, are all 2100 FCLK focused
> But you can give this a try too
> 840mV cLDO_VDDP, 960ish CCD, 1040ish IOD, 1085 (1080 GET) SOC
> Should be fine with only 1900 FCLK ~ y-cruncher will tell you
> 
> Generally VDDG CCD voltage will make you issues in the long run
> procODT to run low needs ClkDrvStr bump - which needs AddrCmdDrvStr bump (assisting memory training)
> and low procODT to run, all other voltages needs to be low.
> cLDO_VDDP that low can make issues beyond 1900 MCLK, but it should run. It doesn't limit 2100 FCLK ability tho
> 
> At the very end if this runs and you miss around 1ns latency, bump up that 1.8v rail.
> 1.83 is fine, 1.85v won't complain. 1.93v is about the limit where it won't complain ~ that max limit also depends on procODT & cLDO_VDDP, soo your mileage will vary
> * if that 1.8v rail does no changes, better revert it ~ but sometimes it's needed. Depends on the voltages you run. This is experimental but runs, and low procODT is always nice ot have


Yes I had a new TM5 "freeze" last night after 30 successful cycles, even though Y-cruncher passed happily 6 cycles.
Settings that failed:
Vsoc: 1.1250 ( reporting 1.1 )
VDDP: 1 ( Reporting 0.9976 )
CCD: 0.9 ( Reporting 0.8973 )
IOD: 1.05 ( Reporting 1.0477 )

Will work on that today following the settings you sent, reporting soon, thank you


----------



## craxton

Veii said:


> Switched to the ASUS Creator, then it changed to 9/10 loggers
> Now i'm back on the ITX and it remains 9/10 loggers


so your saying you went from the ITX to the creator, back to the ITX
and it now has more sources active??

im still only seeing 5 sources being active but i didnt swap boards....



Veii said:


> Somebody would think the new windows updates (10 and now 10X) would have changed / added it
> but that's across 3 wipe-installs and identical behavior


i reinstalled several times as well, and seen no changes in "active sources" 
hell, up-to installing the 5800x i really didnt know what a WHEA 19 was 
as i hadnt seen nor encountered one ever. 
(to be honest) i didnt know what ALOT of things were on "computers" until i came here...
had no idea any of these problems with AMD were a thing....since i have used AMD for years now? (2400g-1600af-3600xt-5600x-5800x)
all of which i had GREAT overclocking with and no issues (except for that last one, maybe it needs dropped????)
as literally all others were except the 3600xt and it too didnt like 4x8 sets of ram...(QVL listed at that)




Veii said:


> (EDIT: oh i hit perfect perfect half on write, heh)


what exactly is "half" whatever the full read is, take it /2 ?



byDenoso said:


> There's still room to improvement.


....i dont get this here sure 1T and not as much ram, but you did WAY MORE cycles than i did and i 
still hit 3 hours to finish 25 cycles with a 5800x and 32gb of ram...the aida test is Veii run (this time no background startup tasks ran
but HWiNFO..
im Prime stable, Ycruncher stable, TM5 stable (have not ran HCI) but why does it take SO LONG 
when others have "lesser" timings for the most part and its taking 5-10 minutes (GIVE OR TAKE) less to run TM5 
(i quoted your post but this question is for someone who can give an answer) 

(so this) wouldnt be "perfect" as its flawed from what it shows as being "realistic"
@Veii is there anything with my "strengths" that look like its 'killing' 
my chip or damaging in any way? im curious (extremely) as why im seeing such high test times with TM5 
when im not using the machine and just letting the test run.


----------



## damt610

Hi everyone,
I have a problem with my PC: Ryzen 5 5600x, MSI B550 Gaming Plus and Patriot Viper Steel 2x8GB GB, 4400MHzCL19.
I spent a lot of time on OC RAM and came to one 100% stable setting:



I tried to stabilize GDM OFF and I always have single errors:



I am so close and I have no idea what can be improved to eliminate errors. 
Anyone have an idea what errors 2, 4, 10 mean and how can they be fixed?


----------



## craxton

damt610 said:


> Hi everyone,
> I have a problem with my PC: Ryzen 5 5600x, MSI B550 Gaming Plus and Patriot Viper Steel 2x8GB GB, 4400MHzCL19.
> I spent a lot of time on OC RAM and came to one 100% stable setting:
> 
> 
> 
> I tried to stabilize GDM OFF and I always have single errors:
> 
> 
> 
> I am so close and I have no idea what can be improved to eliminate errors.
> Anyone have an idea what errors 2, 4, 10 mean and how can they be fixed?


THIS not the other
on second thought thats not it either give me a min or two
(would seem thats actually my 2x8 profile nevermind.) only thing i changed was proc and RTTs
so that should "work" for you.... its not to "tight" and not to loose.
(EDIT) although this profile has GDM on, and i searched the entire history of me being here
to find where i ran this without it, it would seem (back then) i never turned off GDM
or at least with how MSI has it set i couldnt figure out how back then....
but in theory this should work.
as i left GDM on and had 16-15-15-15 working without issues


----------



## Veii

craxton said:


> except for that last one, maybe it needs dropped????)


Please not 


craxton said:


> what exactly is "half" whatever the full read is, take it /2 ?


tRFC mini shows this:








Realistic should be "realistic maximum"
But it's a placeholder - usually it needed to source from a whole transfer time chart - to calculate timing effectiveness
But it's close
Potential is the maximum bandwidth for this MCLK/FCLK & write with a 16B link = 1 CCD unit - can only be perfect half (-1)
Mentioned about only "once in a blue moon" hitting perfect perfect half
(another run & try and it's again -1)








Usually it's an indicator of throttle and clock or fabric instability - yet has barely anything to do with MCLK *
* check the Zen 3 RamOC Sheet, not every 2100 FCLK is really "rock stable" but behind doors autocorrecting. Mine was also slightly, but that's fixed after couple of times redoing my voltages & baselines








* likely 4200C14-14 would be close to maximum bandwidth, instead of C15-15. And yes it throttled minimalistically ~ soo potentially the result can be better, now that i've fixed it

For dual CCD users such is hard.
I haven't seen anyone ever hit 100% full MCLK bandwidth. As usually there are efficiency losses

Memory timings (low or high) only change operation "efficiency".
That's why bandwidth varies and usually higher bandwidth = better timing efficiency & why there was a saying of
Latency plays a role in this, as better timing efficiency = nearly always better access & process/round-trip latency
Buut, that's another whole topic for it's own "which type of latency test is now correct to follow". Soo our gotten used to "random access latency" which tests core by core *, is good enough 
* reason why 16 core units need 2-3 min to run it, 6 core units need less than 40 sec


craxton said:


> @Veii is there anything with my "strengths" that look like its 'killing'
> my chip or damaging in any way? im curious (extremely) as why im seeing such high test times with TM5
> when im not using the machine and just letting the test run.











you are missing 22MB/s there ~ which compared to other 30398 , 30397 results, is already quite significant

Usually latency enchancers and other cheatery do lower FCLK stability or somehow kill off latency
A tradeoff by all these performance enchancers.
Which do include ASUS's fMAX enchancers & performance enchancers.
I haven't tested how harsh CTR is cutting into this , but i think as fabric remains constant (give me 5min i'll show you something) ~ it won't wiggle, as it's only FCLK and CPU Core stability dependent
Well it indicates throttling of some sort


----------



## byDenoso

damt610 said:


> Hi everyone,
> I have a problem with my PC: Ryzen 5 5600x, MSI B550 Gaming Plus and Patriot Viper Steel 2x8GB GB, 4400MHzCL19.
> I spent a lot of time on OC RAM and came to one 100% stable setting:
> 
> 
> 
> I tried to stabilize GDM OFF and I always have single errors:
> 
> 
> 
> I am so close and I have no idea what can be improved to eliminate errors.
> Anyone have an idea what errors 2, 4, 10 mean and how can they be fixed?


First adjust tFAW to 4x RRDS (or tRRDS *tCCDL), than fix your tRFC(it should be at 384 - 285 - 176) and set tRTP to 8 of it. is also good to set tWR to 2xtRTP (keep on 16), also set your tWRRD to 4 and procODT to 30ohm.
Also your PCB is crashing, try to adjust RTT to a weaker value ( try 7/0/6).


----------



## byDenoso

Veii said:


> Memory timings (low or high) only change operation "efficiency".
> That's why bandwidth varies and usually higher bandwidth


Any advice to reduce my tRP to 17? my board is limited to 1,5v and i get a PCB Crash using basically any RTT values.


----------



## Veii

Veii said:


> (give me 5min i'll show you something)


@craxton
.
















It seems to be 3ns penalty on 4.85Ghz
can test again on 1833-1800-967 how much the penalty is. Usually 7-8ns by going 2:1 mode
But only to illustrate the write bandwidth part. Also i lost read because it's not in sync but that's kind of expected
If you lose that much Write bandwidth, something with your voltages is not fine ~ as this point is purely FCLK related (well and CurveOptimizer)

I'd start by increasing the 1.8v line to at least 1.83 and see if that does anything to Write or only Access Latency. 
It doesn't look like memory is the issue, and Write has nothing to do with it (on Zen)


----------



## Robostyle

Veii said:


> Potential is the maximum bandwidth for this MCLK/FCLK & write with a 16B link = 1 CCD unit - can only be perfect half (-1)
> Mentioned about only "once in a blue moon" hitting perfect perfect half
> (another run & try and it's again -1)
> 
> 
> 
> 
> 
> 
> 
> 
> Usually it's an indicator of throttle and clock or fabric instability - yet has barely anything to do with MCLK *


And what if you loose on read/copy, but write b/w if "perfect half"?


Spoiler: cachemem


----------



## Veii

byDenoso said:


> Any advice to reduce my tRP to 17? my board is limited to 1,5v and i get a PCB Crash using basically any RTT values.


If you mean this post


byDenoso said:


> Thanks to @Veii , i've managed to get a new stable OC.
> There's still room to improvement.


Then, hmm
1.5v is quite a bit on 005
706 would like it more & 1.52 on 005 might already destabilize A0 PCBs, where 1.54+ can kill them
tRP 16 should run, but i think you go too low on tRCD_WR (doing math)

Yep, this set would require tRC 40 with such "preset"
While tRAS is 40. Your tRCDWR is too low
You can go 22 on tRAS and 40 on tRC (with the same set you run atm)
It might not post - if it doesn't, then go for tRAS 26 , tRC 44
Problem, tRFCns for the chips ~ if you go thaat low , ,you can not use *6 mode anymore , soo you need to increase tRTP and tWR . Well for tRTP it depends


----------



## Veii

Robostyle said:


> And what if you loose on read/copy, but write b/w if "perfect half"?


Ever Reaching perfect Read or perfect write will be hard to nearly impossible
Dual Rank Dimms do better on such
Write is just FCLK focused at the end & will indicate throttling.
But also will be influenced by bloaty OS state
(soo this part is complicated. Even when its my daily OS, i can not guarantee anyone else will also have consistent results with Aida64)
EDIT:


Robostyle said:


> And what if you loose on read/copy, but write b/w if "perfect half"?


The screenshot also shows Throttle on L3
4.85 held should be 10.4ns not 10.8 ~ or 10.5ns on an allcore (PBO is faster) ~ meaning your cores do not perform equally or EDC limiter throttles too strong
(memOC need a slight EDC lift)








^ stock limits
Soo try something along 165W-113A-280A , or just directly run EDC 400A
140A is EDC fuse limit on it, soo FIT won't really allow you to exceed it unless you telemetry fake it ~ meaning, ,don't worry about running high EDC limiters, as long as TDC limit is small (98-99% peak on Cinebench R20)

maybe Performance enhancers are still active, check the per CCX OC menu and the normal PBO menu ~ ASUS has two active ones
Also under Tools (category top right) , disable ASUS Crate Service ~ then you also need to disable it with "autoruns" Autoruns for Windows - Windows Sysinternals as this is ASUS Spyware DLL (it injects itself into every new windows installation ~ soo spyware, not bloatware)


----------



## craxton

Veii said:


> you are missing 22MB/s there ~ which compared to other 30398 , 30397 results, is already quite significant


(dont hit me that hard) not while i tested with everything under the sun running lol
even chrome was open in the back...here tho i think this is more what you were meaning?
(just closed chrome and other tasks in the taskbar not killing windows stuff)


----------



## byDenoso

Veii said:


> If you mean this post
> 
> Then, hmm
> 1.5v is quite a bit on 005
> 706 would like it more & 1.52 on 005 might already destabilize A0 PCBs, where 1.54+ can kill them
> tRP 16 should run, but i think you go too low on tRCD_WR (doing math)
> 
> Yep, this set would require tRC 40 with such "preset"
> While tRAS is 40. Your tRCDWR is too low
> You can go 22 on tRAS and 40 on tRC (with the same set you run atm)
> It might not post - if it doesn't, then go for tRAS 26 , tRC 44
> Problem, tRFCns for the chips ~ if you go thaat low , ,you can not use *6 mode anymore , soo you need to increase tRTP and tWR . Well for tRTP it depends


Hmm,7/0/6 works too, i've tested but seems like 0/0/5 was more stable.
I run RDCWR Low because i can do tRDWR 8, if i increase it didn't post.
I'll try tRC 40 but i'm but i don't think it will work (anything below 55 just don't post, but i may be doing something wrong.)
I'll test it with tRP17 and repply later.
Thanks for the input!


----------



## Veii

craxton said:


> (dont hit me that hard) not while i tested with everything under the sun running lol


Who tests Aida64 with background programms running 🤭


craxton said:


> Tho i think this is more what you were meaning?


Yes now it's correct ~ well slightly overboosting (maybe DF-C_States are on ~ but the result its fine , if consistent across reboots)


byDenoso said:


> I'll test it with tRP17 and reply later.


tRP 16 is what your preset requires
tRCDavg = tRP
But tRP sadly is voltage dependent. Tho wasting latency on it doesn't really bother much
Might be no way around just running tRCD_WR 10
If it makes issues higher, you clearly have other sync problems 

No set has to error on tWR+tRTP or primaries increase


----------



## craxton

Veii said:


> maybe DF-C_States are on


not at all in fact i got them OFF without using zenstates every boot.
typical current idle and (OFF) for DF-Cstates in bios.
someone mentioned it, i tried and tried to get it working right but finally
it "just did"



Veii said:


> Who tests Aida64 with background programms running


i do it would seem lol (even windows update trying to find something to do)
from time to time. but i only see "consistency" while running in safe mode with
little to no background process its almost always "overboost"
but as i see some more of what you said, i will indeed bump the 1.8v line and see if that "holds up"
while not in safe mode.... since after that run i am back down to what i first showed.
100% of the time.
(EDIT)
this is safe mode so yes im cheating, but none the less
i took around 10 runs (mostly write speed) and all were consistent with each other
minus 1 run where i got 30416 instead of 30417
(this is with 1.83v btw)


----------



## byDenoso

Veii said:


> Who tests Aida64 with background programms running 🤭
> 
> Yes now it's correct ~ well slightly overboosting (maybe DF-C_States are on ~ but the result its fine , if consistent across reboots)
> 
> tRP 16 is what your preset requires
> tRCDavg = tRP
> But tRP sadly is voltage dependent. Tho wasting latency on it doesn't really bother much
> Might be no way around just running tRCD_WR 10
> If it makes issues higher, you clearly have other sync problems
> 
> No set has to error on tWR+tRTP or primaries increase


I've tried and it just dont post.
Now messing with twrrd/trdwr to see if it posts


----------



## Robostyle

Veii said:


> The screenshot also shows Throttle on L3


Well, some improvements...



Spoiler: cachemem custom limits












And I've got used to 10.8 since Intel lol.



CPU was totally on stock, turned off all enhancements, both bios PBOs and fmax for memOC finetune. As well as killed all background processes before, hell, even explorer got fired for a moment.
Crate services....ugh, its both spy-and-bloatware. Removed that one instantly after fresh start, still I can't manage RGBs inside the case, so definitely something remains in the registry.

BTW, I have strange screen dropouts and dwm gives out errors in event logs. Dunno why though, fabric and memOC were stable after all tweaking and tests.

P.S. I beleive it's either BIOS or aida bug, but not throttle of some sort. With limits You provided, aida bounces with results at range of ~100 GB/s each time I click L3 read or write or copy, no matter what, shows ~760 GB/s first time, then second later 690 GB/s, then again 720, etc


----------



## domdtxdissar

Veii said:


> For dual CCD users such is hard.
> I haven't seen anyone ever hit 100% full MCLK bandwidth. As usually there are efficiency losses


This is the closet ive gotten with my dual ccd cpu.








Once in a blue moon i hit 59700+ read also, but haven't taken screenshot of that


----------



## audiotest

mongoled said:


> Great!
> 
> So @audiotest can try RZQ/2 its better than RZQ/1


Hi, thanks for the mention. It took me a while to realise it was a typo even though I was almost certain I'd never posted in this thread, lol. But it was for sure educational, I've been reading through since earlier this morning and I learned a lot.  On a sidenote, it's been a cool coincidence when I noticed your location since I happen to be the greatest Anna Vissi fan ever, efharisto mate.


----------



## Audioboxer

LOL, you couldn't make this up. So I ordered 2 kits of of the F4-4000C16, both were Amazon warehouse very good. Arrived today and someone had gutted them and replaced the kits with 4000 CL18-22-22-42 which I presume is Micron E or Hynix. 4000 ranked but cmon Amazon, whoever inspected these should look them over more than to just go its 4000 sticks, it's all good, put them back up for sale.

So some ******* has bought 2 packs of memory presumably to take the b-die and swap it with slightly cheaper sticks. Imagine going through all that effort to save like I dunno £60 or something? Taking the risk Amazon would actually notice and presumably ban your account or something.

Unless Amazon somehow made a mess of packing returns. They got a mouthful anyway but as expected just the usual apology and send back for a full refund.

Anyone ever seen anything like this on Amazon? I've bought Warehouse for years and only ever had a few issues. Saves me right thinking there is 2 in stock in the warehouse deals I'll take both and return the slower bin 😂

Change of plan, I'm buying new and I think I'll spend a bit more and try and hunt down a 4000+ CL14 rank or even just take a look at that 3800 CL14 set.










If anyone is in the UK and sees these go back into the Amazon Warehouse for sale in the next week or so, do not buy them!

/rant over 😂


----------



## gled_fr

Ok, still running some tests,y-cruncher stable so far


Latest numbers:








Very interesting that changing either vsoc to 1.10625 (next step from the 1.1 it is set now, to have it reported as 1.0813 ) or ClkDrvStr to 30 ( from the current 40 ), latency increases to 56.3, even though y-cruncher is stable with both.

Hoping TM5 will not freeze this time !


----------



## Mach3.2

damt610 said:


> Anyone have an idea what errors 2, 4, 10 mean and how can they be fixed?











tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com





This could be helpful, courtesy of Veii.


----------



## gled_fr

Again, locked tm5 but y-cruncher was ok :/

Gonna try to raise a bit VSOC, even if it makes latency increase...









[edit]

Increasing the vsoc to 1.1125 ( two steps from the previous picture ) latency increased only to 59ns instead of 62 with vsoc 1.10625.

running tm5 again, hopefully no freeze this time...


----------



## Kristoast

Hello Overclockers!

I recently built my first AMD based PC(see sig) and have been messing around with memory overclocking and PBO/CO for the past few weeks. I have seen varying responses and guides around Ryzen 5000 CPUs that seem to have changing answers month to month so I figured I would finally post here.

To start, is it more preferable to work on the memory overclock first or getting the CO set? I've done a lot of messing around with the CO and managed to get -24, -27 and -30 on the rest with +75 boost(this setting didn't seem to affect much). This was with my RAM at default/auto settings in the BIOS/no docp.

I decided to go back and start from square one with the RAM OC and then redo CO once that was locked in. My PC doesn't post once I enable docp until I drop the frequency to 3666/1833. I can get that stable, but I can't seem to get any higher. I have tried disabling docp as well and pushing up the frequency based off the DDR4 memtesthelper guide on github, but that still stops me at 3666 as well and that guide doesn't seem to have been updated for Ryzen 5000 either. I'm just trying to get a feel for if I should be able to push the clock higher before I tighten down the timings.
Here is ZenTimings for where I am definitely stable(TM5 anta777extreme, Karhu 5000%+), docp enabled but dropped to 3666. DRAM voltage at 1.4










Any thoughts or suggestions?

Thank you!


----------



## craxton

Audioboxer said:


> Anyone ever seen anything like this on Amazon?


as a matter of fact, YES with only RAM but it was BRANDNEW 
was supposed to be some 3600 Bdie kits from (i forget atm) 
was instead Samsung c die but was made to return/get something different 
i should have knew better than to order ram from amazon with a "certain" model in mind.
after reading the bad reviews i knew why people were "happy" and people were indeed PISSED
as those like me, were getting the same garbage bin. while others were getting the "lucky" selection they had made. 

which i indeed did, got a 970evo and most my money back out of it.
(THOSE) were the WORST sticks id ever had. corrupt my OS and never EVER did i get them stable at any frequency.
was the only time id ever returned something to amazon.....


----------



## XPEHOPE3

gled_fr said:


> latency increases to 56.3


Are you checking tPHYRDL values on the other stick? 



Veii said:


> Now i'm back on the ITX and it remains 9/10 loggers
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Somebody would think the new windows updates (10 and now 10X) would have changed / added it


Where does one look at this in event logger? Can't seem to find "WHEA successfully initialized" anywhere. kernel-whea and whea-logger event views are empty and I presumed I just didn't have any WHEA errors. But maybe they are just not logged/registered??



craxton said:


> but why does it take SO LONG
> when others have "lesser" timings for the most part and its taking 5-10 minutes (GIVE OR TAKE) less to run TM5


@byDenoso screen shows he only has 16 GB RAM, and tests it as long as you test your 32 GB. Yes, your timings are *that* good, maybe you should be like 😎



Veii said:


> In TM5's case, it's random data created, which then is split into specific data-sizes chunks, and copied back and forth with selected DDR Matrix location
> Soo it mostly is bank to bank, chip to chip - bank group to bankgroup or dimm to dimm
> That's what i ment by dataset "size"


Oh, so you did mean "Test Block Size" from configs, ok. HTH me decipher relevant errors when I encounter them.


----------



## craxton

@mongoled 
do me a favor and post your 32gb setup TM5 run real quick (your c15-15)


XPEHOPE3 said:


> es, your timings are *that* good,


once mongoled responds youll see my concern. "its not much difference" 
but considering "14-14" would be "faster" than "15-15"
shouldn he have longer run-time?
(btw) you can find this event viewer stuff by going to 
event viewer-applications and services logs-Microsoft-kernel whea-operations
(ignore the 4000 WHEA logs here (last one i had was 6-29-2021


----------



## gled_fr

XPEHOPE3 said:


> Are you checking tPHYRDL values on the other stick?


I do, following your previous advice  26 both, did not changed from the different tests I've run.

Current y-cruncher stable after 4h run ( all the other tests were too, although I would stop at 1h-1h30 ) but with my luck tm5 will freeze in about 3h 









What is interesting is that I upped rttPark to RZQ/3 from /4, everything else is the same. Well no, I did take the sticks out to take a picture in case we need to identify the PCB before that run and I added a fan on my case pushing air in in front of the ram ( mini itx case, mesh panels, fan is mounted on the panel, no space inside, ram temps did not change much though ).

Another thing too, I ran twice Aida before y-cruncher: 55.8. Without reboot, ran it twice after y-cruncher and as you can see in the screenshot 55.6. Not complaining, I'll take it if tm5 do not freeze on me again...

Last note, while running y-cruncher I can see vsoc going from 1.0875 to a bit higher ( low 1.09?? ), but stays at 1.0875 during tm5. I suppose this is due to the load being higher on the ram.


----------



## gled_fr

gled_fr said:


> I do, following your previous advice  26 both, did not changed from the different tests I've run.
> 
> Current y-cruncher stable after 4h run ( all the other tests were too, although I would stop at 1h-1h30 ) but with my luck tm5 will freeze in about 3h
> 
> View attachment 2518037
> 
> 
> What is interesting is that I upped rttPark to RZQ/3 from /4, everything else is the same. Well no, I did take the sticks out to take a picture in case we need to identify the PCB before that run and I added a fan on my case pushing air in in front of the ram ( mini itx case, mesh panels, fan is mounted on the panel, no space inside, ram temps did not change much though ).
> 
> Another thing too, I ran twice Aida before y-cruncher: 55.8. Without reboot, ran it twice after y-cruncher and as you can see in the screenshot 55.6. Not complaining, I'll take it if tm5 do not freeze on me again...
> 
> Last note, while running y-cruncher I can see vsoc going from 1.0875 to a bit higher ( low 1.09?? ), but stays at 1.0875 during tm5. I suppose this is due to the load being higher on the ram.


and it froze again... at 20 cycles.









The weird part it's only tm5. Gonna run a different preset for double checking overnight... this is more than puzzling now..


----------



## craxton

gled_fr said:


> and it froze again... at 20 cycles.


have you tried re-downloading TM5????
(actual link) just make sure to change cycles...


----------



## mongoled

audiotest said:


> Hi, thanks for the mention. It took me a while to realise it was a typo even though I was almost certain I'd never posted in this thread, lol. But it was for sure educational, I've been reading through since earlier this morning and I learned a lot.  On a sidenote, it's been a cool coincidence when I noticed your location since I happen to be the greatest Anna Vissi fan ever, efharisto mate.


Yes thats right, born in Cyprus, moved to Greece and became a superstar, my mothers Auntie was a "minder" for her in the early years while she was in Greece





Audioboxer said:


> LOL, you couldn't make this up. So I ordered 2 kits of of the F4-4000C16, both were Amazon warehouse very good. Arrived today and someone had gutted them and replaced the kits with 4000 CL18-22-22-42 which I presume is Micron E or Hynix. 4000 ranked but cmon Amazon, whoever inspected these should look them over more than to just go its 4000 sticks, it's all good, put them back up for sale.
> 
> So some ***** has bought 2 packs of memory presumably to take the b-die and swap it with slightly cheaper sticks. Imagine going through all that effort to save like I dunno £60 or something? Taking the risk Amazon would actually notice and presumably ban your account or something.
> 
> Unless Amazon somehow made a mess of packing returns. They got a mouthful anyway but as expected just the usual apology and send back for a full refund.
> 
> Anyone ever seen anything like this on Amazon? I've bought Warehouse for years and only ever had a few issues. Saves me right thinking there is 2 in stock in the warehouse deals I'll take both and return the slower bin 😂
> 
> Change of plan, I'm buying new and I think I'll spend a bit more and try and hunt down a 4000+ CL14 rank or even just take a look at that 3800 CL14 set.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> If anyone is in the UK and sees these go back into the Amazon Warehouse for sale in the next week or so, do not buy them!
> 
> /rant over 😂


Thats just naughty, you must be pretty deflated after all the aniticipation..





craxton said:


> @mongoled
> do me a favor and post your 32gb setup TM5 run real quick (your c15-15)
> 
> once mongoled responds youll see my concern. "its not much difference"
> but considering "14-14" would be "faster" than "15-15"
> shouldn he have longer run-time?
> (btw) you can find this event viewer stuff by going to
> event viewer-applications and services logs-Microsoft-kernel whea-operations
> (ignore the 4000 WHEA logs here (last one i had was 6-29-2021
> View attachment 2518036
> 
> View attachment 2518035


Here you go, but its not just my tCL @15 times that are faster its also my tCL @14 times also

Both tCL 14/15 fall within 2:49 to 2:52 mins

tCL @15









[email protected]


----------



## Audioboxer

mongoled said:


> Yes thats right, born in Cyprus, moved to Greece and became a superstar, my mothers Auntie was a "minder" for her in the early years while she was in Greece
> 
> 
> 
> 
> Thats just naughty, you must be pretty deflated after all the aniticipation..
> 
> 
> 
> 
> Here you go, but its not just my tCL @15 times that are faster its also my tCL @14 times also
> 
> Both tCL 14/15 fall within 2:49 to 2:52 mins
> 
> tCL @15
> View attachment 2518043
> 
> 
> [email protected]
> View attachment 2518044


Yeah I was pretty angry last night but it is what it is, just gonna pick out the best set, new, I can find/price today and order it 

I guess its the small risk you take with the Amazon warehouse, unless you're just getting a new bashed package that is unopened or something. I suppose it was a little odd how they had two sets of the same RAM in stock in the warehouse listed in the same condition. Clearly was sent back together.


----------



## domdtxdissar

mongoled said:


> Both tCL 14/15 fall within 2:49 to 2:52 mins


Do we know if core cpu mhz affect results ? Iam getting even faster 25 cycle times with my 32GB set @ 1900 fclk (~2hours and 30-40 mins i think)
1 cycle take around 6min and 10sec in the start for me


----------



## byDenoso

craxton said:


> ....i dont get this here sure 1T and not as much ram, but you did WAY MORE cycles than i did and i
> still hit 3 hours to finish 25 cycles with a 5800x and 32gb of ram...the aida test is Veii run (this time no background startup tasks ran
> but HWiNFO..
> im Prime stable, Ycruncher stable, TM5 stable (have not ran HCI) but why does it take SO LONG
> when others have "lesser" timings for the most part and its taking 5-10 minutes (GIVE OR TAKE) less to run TM5
> (i quoted your post but this question is for someone who can give an answer)
> 
> (so this) wouldnt be "perfect" as its flawed from what it shows as being "realistic"
> @Veii is there anything with my "strengths" that look like its 'killing'
> my chip or damaging in any way? im curious (extremely) as why im seeing such high test times with TM5
> when im not using the machine and just letting the test run.





XPEHOPE3 said:


> @byDenoso screen shows he only has 16 GB RAM, and tests it as long as you test your 32 GB. Yes, your timings are *that* good, maybe you should be like 😎


Actually i just modified the 1usmus and MT config to do more cycles and to take more time in each testing to show instabilities.
That's why it takes sooooo much time, but is more reliable, it would take half of the time with "stock" TM5 settings.


----------



## mongoled

domdtxdissar said:


> Do we know if core cpu mhz affect results ? Iam getting even faster 25 cycle times with my 32GB set @ 1900 fclk (~2hours and 30-40 mins i think)
> 1 cycle take around 6min and 10sec in the start for me


That would be extremely fast!

The first cycle takes less time than the last cycles.

I do believe CPU frequency does play a role, but in @craxton case he is using a 5800x, where as I am using a 5600x so logically the 5800x sustained mhz should be higher than what I can achieve.

Can you double check your values for completed 25 cycles TM5 runs as im confident that there are not too many peeps who have posted faster times than what I have posted while using a 5600x with 32GB I could understand a time within 2:40 mins while using flat 14s but 2:30 is a big stretch


----------



## byDenoso

mongoled said:


> Yes thats right, born in Cyprus, moved to Greece and became a superstar, my mothers Auntie was a "minder" for her in the early years while she was in Greece
> 
> 
> 
> 
> Thats just naughty, you must be pretty deflated after all the aniticipation..
> 
> 
> 
> 
> Here you go, but its not just my tCL @15 times that are faster its also my tCL @14 times also
> 
> Both tCL 14/15 fall within 2:49 to 2:52 mins
> 
> tCL @15
> View attachment 2518043
> 
> 
> [email protected]
> View attachment 2518044



Wow, that 6ghz core 4 effective clock


----------



## mongoled

byDenoso said:


> Wow, that 6ghz core 4 effective clock


Not "real",

apparantly its a momentary overboost bug that can lead to hard crashes


----------



## mongoled

@craxton

increase your CCD/IOD to somthing similar to mine (1.020/1.060) and report back, I reckon your times will be faster


----------



## Audioboxer

Anyway, I dropped some of my voltages this morning on my current set to see how she gets on and its all good so far (though my VSOC has dipped a bit low for the 0.5 gap, will fix that)










Believe it or not I didn't actually know before now the higher you pump VSOC the more it might end up drawing power from the CPU (?) and potentially lowering boost clocks. I guess it's pretty minor though and/or requires you to get more towards 1.2v+.

Though I have to say I think on some brief testing it can be the difference between my 5950x hitting 5075 on a few cores and 5050. I even seen 5150 once, but literally just once. Mostly seems to top out at 5050/5075.


----------



## Robostyle

What's AMD's position regarding Vdroop?


----------



## kim nk

These days, I tried to buy several kinds of cpu with 2119 2121 sus, pgs and get cpu without more than 3800 WHEA error, but failed. crying
The cpu, which was 5800x ccd2, was sold because it didn't have bandwidth and latency.



I hope the results come out like this and there is no WHEA error. 









Some people have recently come up with this.









































(레이턴시-4) 4000 13-15-13-13-26/리얼1T 49.6ns TM5


* 테스트장비CPU : 5600X (2113SUS, 이볼브X + 아틱 420 전면샌드위치)M/B : MSI …




quasarzone.com





Some people show these results with CL14 4000 OLOY memory. Every time I see something like this, I try to keep up with that standard of CPU pulling, but it's very difficult to get. Is there any tip to find a CPU that has no WHEA error on 4200 CL15 with normal bandwidth? Even if I bought the latest product, the results were not good.


----------



## Audioboxer

Robostyle said:


> What's AMD's position regarding Vdroop?


Not sure if this question was inspired by me mentioning the "gap", but I took my advice from @Veii who said a 0.5 difference between VSOC and VDDG is required for optimal running.

Ignore me if that's not what you were asking.


----------



## XPEHOPE3

craxton said:


> this event viewer stuff by going to
> event viewer-applications and services logs-Microsoft-kernel whea-operations


Thank you. Only getting non-error messages 42 and 5, with 10 event sources.


gled_fr said:


> I do, following your previous advice  26 both


Just checking  Then autocorrection it is, or background Windows activity. I always stop real-time anti-malware protection, for example, and verify through task manager there's no ethernet activity. Both can gain latency. Anyway. hope you test at least 10 times and throw away single outliers both too low and too high.


gled_fr said:


> and it froze again... at 20 cycles.


I had the same problem (and reported here back then). Yes, TM5 just loses one of the threads. You can see that in task manager. It first starts with N threads (N being number of either logical or physical cores). But during *one of the tests* _one TM5 thread dies and frees some memory_. The the _rest of the tests_ in the same cycle pass _faster_ (as they have less memory), and after test 15 memory gets freed. Then next cycle doesn't start for some reason. The whole problem for you should be determining the *test on which a thread dies*, and consider that test failing and check it in Veii's error description. The best I could do to assist myself was this:

Be near PC being tested, don't disable it's sound system, and setup HWiNFO repeated sound alert on free memory above 2GB (threshold varies for you!). Then it would play sounds after every TM5 cycle end, but also when one of the threads fail.
Roll back to previous TM5-stable settings



byDenoso said:


> Actually i just modified the 1usmus and MT config to do more cycles and to take more time in each testing to show instabilities.


Then please rename your config accordingly (like 1usmus v3 200%) not to mislead people. Also @craxton can you please verify you didn't change anything in the config?



craxton said:


> once mongoled responds youll see my concern. "its not much difference"
> but considering "14-14" would be "faster" than "15-15"
> shouldn he have longer run-time?


I already answered that here:


XPEHOPE3 said:


> Note that @craxton even has faster clocked CPU! But you have lower tRFC, lower *SCL and 1T. I think that gives that of a difference.


----------



## Audioboxer

Oh yeah from above speaking of TM5 "crashing", is that to do with luck and the app or can it mean memory is unstable.

I've had it a few times where TM5 frees up the memory to begin a new cycle but the cycle never actually begins even though the timer keeps going. Searching online suggests it can just be a bug of the app, but I'd rather not just believe that in case it could be memory instability.

Meant to ask this days ago.


----------



## byDenoso

mongoled said:


> Not "real",
> 
> apparantly its a momentary overboost bug that can lead to hard crashes


@Veii says than you need to disable DF Cstates and set "Typical Current Iddle" on the processor menu to disable the overboost bug.


----------



## byDenoso

XPEHOPE3 said:


> Then please rename your config accordingly (like 1usmus v3 200%) not to mislead people. Also @craxton can you please verify you didn't change anything in the config?


Ok
I've leave my pc testing overnight and i have a new stable result.
Almost 0.5ns Gain over the last timings set.
Since i couldn't do tRP 17, even with the advices than @Veii gave me, i was trying to lower tCL and tRFC, but to work i had to lower tWR (to match rdds+rwtrs) and tRTP (to match tRFC as a divider and tWR).









*PS: 1Usmus modified Profile used (250% instead 100% in each test and 40 cycles instead 30)*


I Just dont know why i have a "hard cap" of 29810MB/s Write indepentent of timings, is probably CPU Clock related.


----------



## fireanimal

Just looking for some input on a strange bandwidth issue I am having with unlinked FCLK MCLK. I have another system with a 5950x and 32gb of Samsung B-Die that doesn't have this issue with the bandwidth. I am wondering if it is the 5800x or SR Micron Rev-B ram that is not scaling with the faster MCLK?

Thanks!
.


----------



## Blameless

Robostyle said:


> What's AMD's position regarding Vdroop?


I'm sure someone will correct me if I'm mistaken, but I don't think AMD has publicly published a load-line specification.

It's possible to infer what the default loadlines are for various boards and guess at what they should be from perceived clock behavior. It's clear that some degree of droop is specified, but again, I haven't seen official specifications anywhere.



byDenoso said:


> I Just dont know why i have a "hard cap" of 29810MB/s Write indepentent of timings, is probably CPU Clock related.


It's because the write performance of the Fabric from each CCD is half that of the read...you can fully saturate the Fabric's upstream on a single CCD part at well below the write bandwidth the memory is usually capable of.










The write bandwidth you're seeing is exactly what it should be for your FCLK on a single CCD part.


----------



## Veii

Robostyle said:


> As well as killed all background processes before, hell, even explorer got fired for a moment.


Killing windows explorer has more negative effects than positive
It will restart and then start more services than you had on normal boot 


XPEHOPE3 said:


> Where does one look at this in event logger? Can't seem to find "WHEA successfully initialized" anywhere. kernel-whea and whea-logger event views are empty and I presumed I just didn't have any WHEA errors. But maybe they are just not logged/registered??











Every Reboot










gled_fr said:


> Last note, while running y-cruncher I can see vsoc going from 1.0875 to a bit higher ( low 1.09?? ), but stays at 1.0875 during tm5. I suppose this is due to the load being higher on the ram.


Only the FFT test really focused on high EDC values and IF
It's a nearly no IPC heavy test but will show if voltages missmatch
Overshooting in our case is not that bad - but undershooting can make it voltage choke
y-cruncher has different types of AVX2 and SSE loads, and nearly always will voltage or frequency throttle with it.
Not uncommon that SOC also get throttled, be it my VRM heat or just by the load differences


domdtxdissar said:


> Do we know if core cpu mhz affect results ? Iam getting even faster 25 cycle times with my 32GB set @ 1900 fclk (~2hours and 30-40 mins i think)
> 1 cycle take around 6min and 10sec in the start for me


Recently could test it with 4.65 and 4.85 loads
It barely moved, maybe 10ms at best
I do think core amount does indeed speed it up and IPC likely too, considering it is slower on Matisse and far slower on Summit Ridge (8c (1700X) vs 6, or 6 vs 2+2 ~ 1200AF)
The biggest difference seems to be MCLK speed
My C13 set takes quite a long , 2:10-2:20 to pass 25 rounds, soo i expect about 4:30h for 32GB ~ yet dual rank remains faster at the same Freq in comparison


Robostyle said:


> What's AMD's position regarding Vdroop?


Stock behavior loves loadline Vdroop
AMD never gives direct universal advices, as there is leaky and not leaky silicon


kim nk said:


> hese days, I tried to buy several kinds of cpu with 2119 2121 sus, pgs and get cpu without more than 3800 WHEA error, but failed. crying
> The cpu, which was 5800x ccd2, was sold because it didn't have bandwidth and latency.





kim nk said:


> I hope the results come out like this and there is no WHEA error.











1MB/s missing
Close to perfect 


kim nk said:


> Is there any tip to find a CPU that has no WHEA error on 4200 CL15 with normal bandwidth? Even if I bought the latest product, the results were not good.


We have no 100% direct reason why it WHEA's still
Dual CCD 6,8c seems to be some kind of broken ~ DPM link broken, but that's all we have
Aside from it being IO related issue by the link to the PCH , there is really not much. Sometimes PCH attached IO (build in) can make issues, but from the same board ~ only the GPU, Bios and CPU make the difference (well any voltages)

2133 is fantastic 
i still have slight throttle with it, 4ns
But write shows nearly no throttle, soo OCer also does not WHEA ~ if he WHEA's it's not CPU or fabric related, else write would go down strong & not only 1MB/s (see Zen RAM OC sheet, many results with 33596, 33589MB/s ~ only one result with 33598 / 33599 Target Result. And only one 2133 FLCK 34119 / 34128 ~ also 7MB/s throttle
Zen RAM Overclocking Sheet Please submit the 47.7ns ~ if it's y-cruncher stable too 


XPEHOPE3 said:


> Thank you. Only getting non-error messages 42 and 5, with 10 event sources.


10/10 , or 9 out of 10 like usual ?


Audioboxer said:


> Oh yeah from above speaking of TM5 "crashing", is that to do with luck and the app or can it mean memory is unstable.


I never had that "bad luck" - butt saw it twice on other people's systems
It seems to bug out also when the screen darkens for some reason, even when hibernation is clearly disabled

It nearly always was "an unstable core" - mostly happening with CTR running (configured)
But so far always an instability thing - else i'd notice it happening for me too by the 3digit hours spend with this program


fireanimal said:


> I am wondering if it is the 5800x or SR Micron Rev-B ram that is not scaling with the faster MCLK?


I do feel between 18-22-22 and 19-19-19 everything looks fine
Even the added latency by the SETUP times (63)
Also very glad to see the SETUP timings "pattern" functions well ~ very very happy

Aside from the 8-9ns added ontop, it was kind of expected
You have 12ns ontop , soo there seems to be more than one issue ~ maybe 1.8v rail being too weak higher MCLK (which can easily make 1-2ns difference ~ if it's lacking)
But else,it looks normal
The increase tho is quite high ~ i think to match the same ns latency for 1900, you needed a 5000+ result , or near 4800+
@Nighthog is the person to ask S


Blameless said:


> The write bandwidth you're seeing is exactly what it should be for your FCLK on a single CCD part.


Slightly unsure with Matisse, as they are dual CCD (for his result)
But you are very correct
And higher than these values mostly is an indicator of overboost or dual CCD bugs. ~ lower nearly always an indicator of active throttling/error correction, or just unstable cores
(Sometimes the CPU exceeds it for me by a big jump, but then only for one test and settles back down to the locked state)


----------



## Audioboxer

Veii said:


> Killing windows explorer has more negative effects than positive
> It will restart and then start more services than you had on normal boot
> 
> View attachment 2518078
> 
> Every Reboot
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Only the FFT test really focused on high EDC values and IF
> It's a nearly no IPC heavy test but will show if voltages missmatch
> Overshooting in our case is not that bad - but undershooting can make it voltage choke
> y-cruncher has different types of AVX2 and SSE loads, and nearly always will voltage or frequency throttle with it.
> Not uncommon that SOC also get throttled, be it my VRM heat or just by the load differences
> 
> Recently could test it with 4.65 and 4.85 loads
> It barely moved, maybe 10ms at best
> I do think core amount does indeed speed it up and IPC likely too, considering it is slower on Matisse and far slower on Summit Ridge (8c (1700X) vs 6, or 6 vs 2+2 ~ 1200AF)
> The biggest difference seems to be MCLK speed
> My C13 set takes quite a long , 2:10-2:20 to pass 25 rounds, soo i expect about 4:30h for 32GB ~ yet dual rank remains faster at the same Freq in comparison
> 
> Stock behavior loves loadline Vdroop
> AMD never gives direct universal advices, as there is leaky and not leaky silicon
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 1MB/s missing
> Close to perfect
> 
> We have no 100% direct reason why it WHEA's still
> Dual CCD 6,8c seems to be some kind of broken ~ DPM link broken, but that's all we have
> Aside from it being IO related issue by the link to the PCH , there is really not much. Sometimes PCH attached IO (build in) can make issues, but from the same board ~ only the GPU, Bios and CPU make the difference (well any voltages)
> 
> 2133 is fantastic
> i still have slight throttle with it, 4ns
> But write shows nearly no throttle, soo OCer also does not WHEA ~ if he WHEA's it's not CPU or fabric related, else write would go down strong & not only 1MB/s (see Zen RAM OC sheet, many results with 33596, 33589MB/s ~ only one result with 33598 / 33599 Target Result. And only one 2133 FLCK 34119 / 34128 ~ also 7MB/s throttle
> Zen RAM Overclocking Sheet Please submit the 47.7ns ~ if it's y-cruncher stable too
> 
> 10/10 , or 9 out of 10 like usual ?
> 
> I never had that "bad luck" - butt saw it twice on other people's systems
> It seems to bug out also when the screen darkens for some reason, even when hibernation is clearly disabled
> 
> It nearly always was "an unstable core" - mostly happening with CTR running (configured)
> But so far always an instability thing - else i'd notice it happening for me too by the 3digit hours spend with this program
> 
> I do feel between 18-22-22 and 19-19-19 everything looks fine
> Even the added latency by the SETUP times (63)
> Also very glad to see the SETUP timings "pattern" functions well ~ very very happy
> 
> Aside from the 8-9ns added ontop, it was kind of expected
> You have 12ns ontop , soo there seems to be more than one issue ~ maybe 1.8v rail being too weak higher MCLK (which can easily make 1-2ns difference ~ if it's lacking)
> But else,it looks normal
> The increase tho is quite high ~ i think to match the same ns latency for 1900, you needed a 5000+ result , or near 4800+
> @Nighthog is the person to ask S
> 
> Slightly unsure with Matisse, as they are dual CCD (for his result)
> But you are very correct
> And higher than these values mostly is an indicator of overboost or dual CCD bugs. ~ lower nearly always an indicator of active throttling/error correction, or just unstable cores
> (Sometimes the CPU exceeds it for me by a big jump, but then only for one test and settles back down to the locked state)


I did 24 hours, yes, a full 24 hours non-stop with Corecycler to test my curve, but thanks for pointing this out as I might have to look into it further.

My screen does go into standby quite quickly if you mean that by darken, so I will also try turning off screen standby.


----------



## byDenoso

Blameless said:


> It's because the write performance of the Fabric from each CCD is half that of the read...you can fully saturate the Fabric's upstream on a single CCD part at well below the write bandwidth the memory is usually capable of.












Yeap, i'm very close to the limit of my single CCD Cpu, probably is alreadly in the limit but i'll only able to reach it with with no programs in the background.




Veii said:


> 1MB/s missing
> Close to perfect


How to improve my read and copy rate without touching cpu clocks?


----------



## Robostyle

Veii said:


> Stock behavior loves loadline Vdroop
> AMD never gives direct universal advices, as there is leaky and not leaky silicon


So I guess I'll stick to using LLC3 then instead of auto, no matter how beefy dark hero's VRM is. 
Especially for SOC, I guess, it won't hurt at all.


----------



## Veii

Robostyle said:


> So I guess I'll stick to using LLC3 then instead of auto, no matter how beefy dark hero's VRM is.
> Especially for SOC, I guess, it won't hurt at all.


A good PWM/VRM setup doesn't always mean "low loadlines"


http://imgur.com/a/jFg2jPc

 (gallery link)

This is what i used ~ but on stock/auto it was already well tuned
The CPU loadline mostly was CTR optimized ~ and can need a more droopy version for some CPUs (loss in score for PBO but you can R20 bench it to find yours)

PowerPhase Control on Extreme = Full Phase mode , generally is better ~ but i honestly had more ripple with a 5950X (two) , than keep it on Optimized
(more consistent CTR voltage difference of 1-2mV droop at worst) ~ soo rather use Extreme with 8 core units, to maintain better ripple. Maybe 12 core , depends

For my 90A stages, i still do run a loadline vdroop on vcore, but with maxed out switching freq (nearly)
for SOC i run a flat loadline with the weakest switching freq

The board on my side runs loadline 5 (strongest droop) on stock, and usually that leads to the best results
But near flat lv 2 loadline [vcore] with high switching freq ~ was a better option (on one side for CTR matching VID & V_TEL & on the other side, better with Curve Optimizer + positive vcore offset)


byDenoso said:


> How to improve my read and copy rate without touching cpu clocks?


Probably cleaning windows a bit
Sophia-Script, then black viper script & at the end WPD APP (windows update block) + maybe ontop of all, thread scheduler to background services & autoruns64 (microsoft) to block injected DLLs which keep autostarting (IExplorer, chrome update, java update, ASUS DLLs or mouse software, WinToGo services, Printer DLLs, SysMain services, plug'n'play one)

I always use Thread Scheduler to BG Services ~because the results remain consistent
Either the OS is maintained or it isn't. Was better for low buffer audio drivers and generally my usual work
Gamers mostly to program focused, but then random services can or can not "randomly" interfere. I don't like happy accidents while collecting data, only in RL 
Soo when it's bad, at least it remains bad till i fix/clean it


----------



## Veii

This 1T is starting to get annoying ^^'








Anybody sees any issue why it potentially can be a "sync issue" ?








At least to document,
6-2-6 now functions better than 7-3-6 ~ it posted on 625 & 725 but i really don't like 1.65v & RTT_PARK /5, too dangerous

Probably browsing memory intensive pages and g-sheets is a bad idea , but it has to remain stable
It could maybe pass without me touching the PC ~ tho it won't be rock solid then, when it times out here
tRFC 2 & 4 i gave a slight modification, 123 was wrong to begin with.
Only haven't tried 272-203-125 instead of 272-202-124

Maybe just 10mV more will fix it, now that powering is better (hopefully) and doesn't give overcurrent or thermal errors
No explosion of #2 either as usual, soo clearly not a heat issue anymore. Something with my timings seems to be off slightly 

EDIT:
I can only think to drop SD,DD's to 1-5-4-1-7-6
And decrease tWR , tRTP, & tRFC
Problem ~ tRAS will be too high (tRCD+tRTP) and 21 is the settable AMD limit then. It won't be as fluid and likely cost me perf, even when tRFC potentially can be lower by some margin (tRTP issue)


----------



## Robostyle

Veii said:


> This is what i used ~ but on stock/auto it was already well tuned


Well I've mostly guided with info from one of usmus reviews:


Spoiler: LLC Auto, VID 1.35 @4.4Ghz

















Spoiler: LLC3, 1.35V aswell















Quote: "Alongside with raised median voltage also more overshoots...by 1.43V. Software showed 1.325V, RMS - 1.34V. Also raised undershoot\overshoot diff, thus LLC3 shows itself is a bit worse than auto" - whatever that means, afterwards, he mentions that "BIOS with agesa 1.1.9. worked poorly with such hardware".

Thus I've tried to make my OC mostly with llc on auto.


----------



## gled_fr

)


Audioboxer said:


> I did 24 hours, yes, a full 24 hours non-stop with Corecycler to test my curve, but thanks for pointing this out as I might have to look into it further.
> 
> My screen does go into standby quite quickly if you mean that by darken, so I will also try turning off screen standby.


my screen was on full time last time it crashed.

I do suspect now an issue with my PBO settings instead of a RAM issue. I did test with my previous cl16 / gdm on and got a crash at 16 cycles again.

I am currently testing tm5 with stock xmp and pbo auto instead of my custom settings to see. Weird, I had no issues and ran corecycler for close to 30h during a weekend...
I am starting to suspect my CO is ok during load, but maybe too aggressive on one core during idle ?




craxton said:


> have you tried re-downloading TM5????
> (actual link) just make sure to change cycles...


I did, no more luck...


----------



## Veii

Robostyle said:


> Well I've mostly guided with info from one of 1usmus reviews:
> 
> 
> Spoiler: LLC Auto, VID 1.35 @4.4Ghz
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Spoiler: LLC3, 1.35V aswell
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Quote: "Alongside with raised median voltage also more overshoots...by 1.43V. Software showed 1.325V, RMS - 1.34V. Also raised undershoot\overshoot diff, thus LLC3 shows itself is a bit worse than auto" - whatever that means, afterwards, he mentions that "BIOS with agesa 1.1.9. worked poorly with such hardware".
> 
> Thus I've tried to make my OC mostly with llc on auto.


He is correct.
LLC3 on full load was also readable as badly performing
That's why i mentioned the core amount , part
Even when they "look beefy" - it's not a good time
(he has a 5950X & i think a 5900X)

He mentions that not only undershoot but also overshoot got worse on this set loadline
Which means on both parts it's a worse option ~ where he is correct too.
It mostly is dependent between full phase and "optimal" mode.
RMS = measured, Software = HWInfo or CTR

Median = Flat, earth median , but also can mean Zero = Unison (another word)
Idk when he got the DH, i could play with it and actually saw different behaviours on two people's systems. The same was for the normal Hero 8.
Some needed positive vcore, some needed telemetry faking to adjust readouts being normal
I still think the boards are tuned well, but i didn't in general have a good time with it. Neither PBO nor MemOC. Yet marketing and people seem to love this board a lot.
Can't deny my experience, but everyone comes with "best board for XOC, highest mem OC out there" wordings. People are soo much in love with it, that they attack other who don't share the same believe ~ lol

I think a capable board, but somehow the whole Hero 8 lineup shows QC issues somewhy.
Don't like that there keeps popping up a new revision after another flagship , but i believe they'll manage it
Probably all DH and Hero lineups are fine, if retuned by the user ~ but i couldn't blindly recommend it so far.


----------



## Ramad

Robostyle said:


> What's AMD's position regarding Vdroop?


If set to AUTO, Vdroop is set to Level 1 on ASUS motherboards which translates to 80mV - 90mV and gives the best results of stability and CPU longevity. Level 2 is 60mV - 70mV which is still acceptable. Vdroop below 50mV is not advisable, so use Level 1(Auto) or Level 2.


----------



## Robostyle

Veii said:


> Probably all DH and Hero lineups are fine, if retuned by the user ~ but i couldn't blindly recommend it so far.


Misread that like "if retuRned by the user" - couldn't agree more  
It's all about marketing. Though it's still much better than my previous M10H, obviously, but both MBs are not that perfect, M10H is a mess at all, C8DH - hope only at this stage. And it's like July already, and they still didn't fix things I would really like them to.

Anyway, you mentioned Vcore offset - is it only for manual OC, or you can use it with curve optimizer aswell?


----------



## Robostyle

Ramad said:


> If set to AUTO, Vdroop is set to Level 1 on ASUS motherboards which translates to 80mV - 90mV and gives the best results of stability and CPU longevity. Level 2 is 60mV - 70mV which is still acceptable. Vdroop below 50mV is not advisable, so use Level 1(Auto) or Level 2.


That comes for both cpu and SOC?


----------



## Ramad

Robostyle said:


> That comes for both cpu and SOC?


Mainly for CPU. SOC Vdroop is minor as it does not pull much current so the voltage spikes are also minor.


----------



## gled_fr

gled_fr said:


> )
> 
> 
> my screen was on full time last time it crashed.
> 
> I do suspect now an issue with my PBO settings instead of a RAM issue. I did test with my previous cl16 / gdm on and got a crash at 16 cycles again.
> 
> I am currently testing tm5 with stock xmp and pbo auto instead of my custom settings to see. Weird, I had no issues and ran corecycler for close to 30h during a weekend...
> I am starting to suspect my CO is ok during load, but maybe too aggressive on one core during idle ?
> 
> 
> 
> I did, no more luck...


Ok so there's something real wrong there. Stock settings no pbo all auto, ram set to XMP also tm5 freeze... RAM XMP off, freezes too... grrr, probably time for a clean reinstall and I may have been chasing the wrong issues for the past couple days...


----------



## domdtxdissar

Veii said:


> This 1T is starting to get annoying ^^'


Tell me about it..








And that is 2hours and 40min for 32gigs 25 cycle run, been below that before


----------



## Veii

Diva is finally listening, 1T @ 1.64vDIMM
after the 5th 1h+ attempt today and couple more yesterday








Error #2 was procODT related for me (resistance or voltage mention was correct, but it missed direction)
The way to solve it was,

Increase procODT +1 (normal on MCLK increase, nothing to do with FCLK just destroys Signal Integrity ~ if too high)
decrease VDIMM by 20mV (as 1.66-1.67v was already overcurrent)
Decrease RTT_PARK by one more to /7, as ProcODT is higher & shift back RTT_NOM to /6 instead /5 (less applied VDIMM after all)
Usually as a bonus ~ is to also decrease ClkDrvStr, on procODT increase or voltage increase
~ but currently it's fine how it is 

Error #2 was a plague also since SMU 56.50 came out and broke my set
Annoying but now solvable

Notes:

Too much arriving current will trigger #11 or #1
Too much VDIMM will trigger #13
Bad CAD_BUS will trigger #1
Bad tWRRD/tRDWR/SCL will trigger #14 & #3
SD, DD 1-5-4-1-7-6 [MSI] are worse than 1-5-5-1-7-7 & 1-4-4-1-6-6. They can help lower tRDWR by -1, but so does also tWRRD delay. Doesn't work on ODD timings well 
tRFC mini, is perfectly fine for now. No need to change rounding method (but i do seem to convert one time too much between integer ⇌ ns, idea for a future update) 
Now with slightly improved powering foundation,
~ i expect 4067C14-14 to run & hopefully 4267C15-15 , soo i can work cosy on 2133 FCLK 
_should have raised tRCD wall by +1 MCLK step with this result
* someday 3800C13-13 is the goal, when i can use 1.7v without crashing/killing my dimms_


----------



## craxton

byDenoso said:


> @Veii says than you need to disable DF Cstates and set "Typical Current Iddle" on the processor menu to disable the overboost bug.


its not "always" that way with every board, to get FULL turning OFF of DF-Cstates 
on my MSI board, one has to set power supply idle control to "typical current idel" and set DF-States to OFF.
if one does not set typical current idle then DF-Cstates remain "half" active leaving package state active while C6 state is off.
this way im talking above manages this, (do note that i didnt set anything in zenstates i just opened it to show DF-Cstates are indeed off)
unless i missed something somewhere and its not 100% off? 
@Veii does the image below show DF-Cstates being off?
or should one of those boxes be ticked on? 
this is "default" nothing done but opened on my end. 












XPEHOPE3 said:


> Thank you. Only getting non-error messages 42 and 5, with 10 event sources.


no prob, mine has 5 and did have 5 while using the 5600x so nothing else started recording events. 



XPEHOPE3 said:


> I already answered that here:


i missed that, or "overlooked" it but still, 
if i could tighten SD/DD and SCL i think i could counter what mongol has 
as loosening SCL one tick seems to KILL c14 and makes it slower than c18....


----------



## Veii

craxton said:


> @Veii does the image below show DF-Cstates being off?
> or should one of those boxes be ticked on?
> this is "default" nothing done but opened on my end.


Yes it's off "package C6 = DF_C-State"
But Global C-State generation is off, which is bad. Halfway fine for an allcore, but very bad for PBO
I would enable Global-C State control in the bios
Be sure to reboot and doublecheck that DF-C States remain off. It's buggy and one turns off the other one here and there


----------



## craxton

well, from 10000 (yes ten thousand) WHEAs in an hour to 300 in an hour
4000/2000 i think thats a DAM GOOD thing. but i got tired of fiddling with it
(edit) those 10,000 were while the pc was on IDLE, the 300 is with me running TM5
and all sorts of other things including OCCT....
(anything over 930mv on CLDO_VDDP crashes the machine) no matter if i use 50mv stepping
all the way to 70mv stepping hitting the "max" iod ccd voltage ranges that i have bookmarked as
a recommended value to not go over....needless to say, i think anything "under" 2000fclk ill be able to do
before long, but its still not 2000 🥺anyway thought id share that (nomore USB/DISPLAY/STRANGE bullshit anymore either)
99.9999% sure that was indeed related to CCD/IOD/VDDP voltages (NOT CPU_VDDP) cant change that
even the option deep inside the bios does nothing can max the offset out either direction which would 100% blow someones chip up
and its doing nothing to change CPU_VDDP voltage which i cant monitor anyhow, but still if it changed nothing recorded this change.




Veii said:


> I would enable Global-C State control in the bios
> Be sure to reboot and doublecheck that DF-C States remain off. It's buggy and one turns off the other one here and there


Ill get it a shot now, as this is how ive been running the PC for a little while now, around 2 weeks give or take.
might i ask, whats bad for it this way?
these would state they are indeed all off? (i just re-enabled C6 monitoring (all of C6 residency)
but C0 and C1 are those not part of DF-Cstates?
(EDIT) this is the same settings, change nothing btw. df-c states are still turned off inside the bios
and typical current idle is still set.


----------



## XPEHOPE3

Audioboxer said:


> is that to do with luck and the app or can it mean memory is unstable.
> 
> I've had it a few times where TM5 frees up the memory to begin a new cycle but the cycle never actually begins even though the timer keeps going.


System is definitely unstable. And since it happens when memory is stressed, memory influences that instability. I heard somewhere that those threads are dying because they suddenly get voltage drop/spike, so it's more of a powering issue where CPU+RAM eat from one powerbudget. There's no code in TM5 to check for such situation, so it doesn't report it as error.


Veii said:


> 10/10 , or 9 out of 10 like usual ?


Well, judge yourself:








Just as in your screen, it says "Error record format is 10", and that has nothing to do with number of sources. The log also says "10 error sources are active". But as you can see from the list, there are only 9 consecutive "42" events. On my other system with Skylake CPU I have record format 10, active error sources = 5, and there actually are 5 consecutive "42" events.


gled_fr said:


> I do suspect now an issue with my PBO settings instead of a RAM issue. I did test with my previous cl16 / gdm on and got a crash at 16 cycles again.
> 
> I am currently testing tm5 with stock xmp and pbo auto instead of my custom settings to see. Weird, I had no issues and ran corecycler for close to 30h during a weekend...


Corecycler with certain Prime95 settings isn't as heavy on memory, as TM5, I think. I cured my TM5-crashing-thread issue by going PBO *disabled *(that means stock limits) + vSOC LLC one above flat (that means the least voltage droop) + PBO scalar manual to 1x, and overall starting from scratch with XMP + GDM off + 2T. Although I left vCore LLC on Auto (most voltage droop), it might also need a change (see also start of current post)



Veii said:


> Notes:
> 
> Too much arriving current will trigger #11 or #1
> Too much VDIMM will trigger #13
> Bad CAD_BUS will trigger #1
> Bad tWRRD/tRDWR/SCL will trigger #14 & #3


Is it going to the list or are you still not sure?

EDIT:


Veii said:


> I use this wording from Donghyuk Lee's PDF about "optimizing memory for different dataset sizes & program algorithm sizes"
> Page 45 ~ while he writes it here as Segment Length
> https://arxiv.org/pdf/1604.08041.pdf


Notice how that document doesn't contain word "dataset" at all 😅 And segment length from the first glance can only be related to buffer size used, as segment length describes parts of TL-DRAM (tiered DRAM), that is, DRAM _caching_. I don't even know if it's really implemented in consumer products or not. But if it is, smaller buffer sizes might fit into caches, while dataset as a whole never would.


----------



## Veii

XPEHOPE3 said:


> Is it going to the list or are you still not sure?


Most yes, better formatted.
Half of it is already written out, but not that clear as in this notes quote

#2's continue to come back on tRRD & tWTR missmatch
Same for #10's ~ on 3733+
Ultimately it doesn't stop, but i need to figure out the priority , because the options keep stacking (too many possible reasons)
The delay when #2 arrives starts to matter quite a bit & if it's one or an explosion also means something completely different.

Pretty much continue to be plagued with #2's , when also tFAW is 4* and not tCCD_L times (stable)
Yes likely it never ends.
Continue to have issues with #4 and #13 for overcurrent & PCB crashes going up to 1.68+ / ~ soo likely another thing i have to see how to resolve. But this is pretty much at the limit for now on 1.66v
Could be potentially stable on 3733, but the PCB is just far to weak for these lucky ICs.

#6 remains to be a "lack of current issue". Easiest fix is +20mV each MCLK bump up ~ else shifting powering impedances around works too
#0 & #12 together (more #12's) is the same thing but "misses 10mV VDIMM" ~ pretty much the same thing to #6, depends if it spams anything else or it's only lonely #12s with some #0's
The "reason" list, information list grows and grows.(@gled_fr). Soo the debug plan likely can be fullfilled ~ but i'm still not good enough to start today and push out tomorrow a whole holy book of 1usmus_V3 decryption

The plan is surely "in planning" and in consideration.
Yet i need more data and even better results.
Am far, but stupid voltage wall ~ i think these IC's on tRCD can be pushed even further.
Maybe,
~ surpassing 1.7v wall and understanding why/how to use RTT_WR /1 or set others on disabled.
(if i can surpass 1.75v voltage wall without needing maxmem & can daily it ~ then i actually achieved something)
~ understanding better the relationship of tWTR and tRRD, as i keep desync'ing them (requires too much trial and error still ~ no concrete ruleset)

Yea that's about it what's missing. Then i should be fine with memOC knowledge ~ maybe playing a bit with RC_PAGE
* oh and figuring out tCKE scale fully

Funny story,
Even when tCKE = 1 , which has to disable any powerdown
Enabling powerdown pushes me #2 & #10's over, even when powerdown should not function at all.
It's funny, IF any PD really happens ~ then likely it just interferes with RTT_WR


----------



## XPEHOPE3

@Veii 
just brining to attention that I edited my previous post a little😇



Veii said:


> Even when tCKE = 1 , which has to disable any powerdown
> Enabling powerdown pushes me #2 & #10's over, even when powerdown should not function at all.
> It's funny, IF any PD really happens ~ then likely it just interferes with RTT_WR


I was asking once how to set RTT_WR to non-auto, if it just doesn't post. Do I have to force tCKE off from 1 to enable powerdown?

Also I almost finished TestMem5 automation script to collect per-cycle screenshots with information if there were any errors. It's possible to even get all the errors in format "cycle: list of errors", but that requires further work, and might not be needed.
Just teasing 😎


----------



## jomama22

Veii said:


> Most yes, better formatted.
> Half of it is already written out, but not that clear as in this notes quote
> 
> #2's continue to come back on tRRD & tWTR missmatch
> Same for #10's ~ on 3733+
> Ultimately it doesn't stop, but i need to figure out the priority , because the options keep stacking (too many possible reasons)
> The delay when #2 arrives starts to matter quite a bit & if it's one or an explosion also means something completely different.
> 
> Pretty much continue to be plagued with #2's , when also tFAW is 4* and not tCCD_L times (stable)
> Yes likely it never ends.
> Continue to have issues with #4 and #13 for overcurrent & PCB crashes going up to 1.68+ / ~ soo likely another thing i have to see how to resolve. But this is pretty much at the limit for now on 1.66v
> Could be potentially stable on 3733, but the PCB is just far to weak for these lucky ICs.
> 
> #6 remains to be a "lack of current issue". Easiest fix is +20mV each MCLK bump up ~ else shifting powering impedances around works too
> #0 & #12 together (more #12's) is the same thing but "misses 10mV VDIMM" ~ pretty much the same thing to #6, depends if it spams anything else or it's only lonely #12s with some #0's
> The "reason" list, information list grows and grows.(@gled_fr). Soo the debug plan likely can be fullfilled ~ but i'm still not good enough to start today and push out tomorrow a whole holy book of 1usmus_V3 decryption
> 
> The plan is surely "in planning" and in consideration.
> Yet i need more data and even better results.
> Am far, but stupid voltage wall ~ i think these IC's on tRCD can be pushed even further.
> Maybe,
> ~ surpassing 1.7v wall and understanding why/how to use RTT_WR /1 or set others on disabled.
> (if i can surpass 1.75v voltage wall without needing maxmem & can daily it ~ then i actually achieved something)
> ~ understanding better the relationship of tWTR and tRRD, as i keep desync'ing them (requires too much trial and error still ~ no concrete ruleset)
> 
> Yea that's about it what's missing. Then i should be fine with memOC knowledge ~ maybe playing a bit with RC_PAGE
> * oh and figuring out tCKE scale fully
> 
> Funny story,
> Even when tCKE = 1 , which has to disable any powerdown
> Enabling powerdown pushes me #2 & #10's over, even when powerdown should not function at all.
> It's funny, IF any PD really happens ~ then likely it just interferes with RTT_WR


tCKE = 1 doesn't disable all power down states, it just controls the delay period for the cke cycle, which is part of every power state of the memory.

It has mostly to do with the self refresh cycle which is also referred to as active power down. Active power down is just as it sounds, it is still fully "active" and not entering a low power state.

My best guess is that tCKE is the delay in cycles from when CKE (clock enable) becomes high and when CLK (the actual clock used for operations) becomes active again, and vise versa.


----------



## rhhek

My mismatched 48GB RAM kit (4 sticks) with my Ryzen 1600 and Asrock B450m Pro4 (1.40V DRAM limitation by the board)

The motherboard uses a daisy chain topography for the memory slots. I put the 3600 MHz kit in the "slower" slots.

Currently the 2933 MHz at 16-18-18-36-54 timing with T1 command rate + Gear Down Mode + Power Down Mode + Bank Group Swap on auto + BGS alt on auto is stable after running memtesthelper for about 36 hours.

At 3000 MHz, it was stable for about 12 hours, and then when I restarted to computer and ran the memtesthelper again, it threw a memory error in a few minutes. 3133 MHz throws errors almost as soon as I start the stability test.

I tried using T2 and disabled the power down mode with 3200 and 3133 MHz with the same timings, but both of them threw errors almost as soon as I started the memtesthelper.

I understand the CPU, motherboard and the different RAM kits are a major handicap to the RAM overclocking. I'm curious if there's still a way to go beyond the current 2933 MHz setting.

The reason why I added 32GB to my original 16GB kit is because Cities Skylines uses a little over 30GB RAM by itself, and that's after pruning the Steam Workshop subscriptions. I'm missing about 1000 props/textures for the custom buildings I'm using in order to cut down on memory usage back when I just had the 16 GB kit. Maybe I could have searched hard for a 32GB kit that matched closer to my 16GB kit.

I am currently testing 3066 MHz with Power Down Mode disabled + Bank Group Swap disabled + BGS alt enabled.

EDIT: The 3066 MHz attempt also threw memory errors.


----------



## hazium233

Veii said:


> Yes now it's correct ~ well slightly overboosting (maybe DF-C_States are on ~ but the result its fine , if consistent across reboots)


I have seen these write bandwidths that are too high occasionally and have wondered why that is happening. So it is mostly from DF C-states?

I had wondered if maybe somehow write test was hitting cache and getting result thrown off, but then I did see in the AMD Monitor (if it is accurate), FCLK sometimes slightly too high.



craxton said:


> i took around 10 runs (mostly write speed) and all were consistent with each other
> minus 1 run where i got 30416 instead of 30417


When I would see 30400-something at 3800 it was less common, with the rest at 30399 or maybe 30398. eg 3 out of 15 runs or something like that.

It seemed like when I was looking at VDDG CCD steps that some steps were more likely to give the values that were too high.


----------



## tcclaviger

Well, the Patriot Viper PVS416G440C9K arrived, 4 sticks. Serials are... close to sequential, there's 1 box between their numbers. Confirmed A2 PCB with extra capacitors, like Buildzoid's sets are, testing on C6H and 3900x before swapping into the watercooling setup, the Team Dark Pro B-die in the water rig now are so good I'll be surprised if the Vipers can beat them.


----------



## craxton

hazium233 said:


> When I would see 30400-something at 3800 it was less common, with the rest at 30399 or maybe 30398. eg 3 out of 15 runs or something like that.
> 
> It seemed like when I was looking at VDDG CCD steps that some steps were more likely to give the values that were too high.


well, i cant pass y-cruncher with any less IOD/CCD voltage ranges. 
and for sure cant stay in windows with anymore cLDO_VDDP voltage as i hard crash no BDOS/GSOD
no WHEA 18 logged or anything of the sort. 

currently the only thing i can get to happen with DF-Cstates is either fully "off" showed in my zenstates pic above
or this pic below no matter how i try to config it inside the bios and id much rather not have to use zenstates everytime i 
log into windows to get C-states working correctly. maybe i can set a "scheduled task" to do it for me? 
or i wonder if someone already has one to do just that?


----------



## craxton

@Veii
is this what its supposed to look like?
if so, set power supply idle control to "TYPICAL" and
turn ON DF-Cstates, if this isnt what its supposed to have checked then do advise,
i searched back to page 446 and have yet to find it unless i passed it.... 
(the original image of you sharing this tool) 
i thought i had it bookmarked but it would seem thats indeed about DF-Cstates but 
i have no indications to which is what, but indeed have a better understanding of why its needed for PBO
and not a good idea to have turned off for PBO


----------



## gled_fr

K reinstalled windows, back in business.

Long story short, it is very likely something was broken with my previous windows install, even xmp off and pbo off were freezing tm5 ( even a fresh reinstall of tm5 ).

Changes currently being tested:

upped vsoc a bit following @Veii advice preparing for testing IF2000
cldo_vddp 900mv
CCD a bit higher too
IOD < vsoc-50mV a step up from my previous test
all the rest the same.
pbo settings the same 235/140/190 ( the last two are motherboard limits ), scalar changed to 6 and CO the same as before ( 0 -5 best cores, -15 on 3 cores and -20 the rest ). Tested with @Veii tool the SI to 117.2 at stock.

Y-cruncher passed, tm5 still running but passed so far 24 cycles.

Here's the screenshot with stock numbers too in notepad:









Quick questions:

Should I be concerned by the diff on the CPU cache numbers between stock and the settings i am trying ?
55.0ns, previous try with almost those settings was 55.8 ?!
kinda nervous about windows corruption now, something I should be concerned about with those settings ?

I am going to let tm5 run overnight of course after a restart, need to use the PC...


----------



## craxton

gled_fr said:


> K reinstalled windows, back in business.
> 
> Long story short, it is very likely something was broken with my previous windows install, even xmp off and pbo off were freezing tm5 ( even a fresh reinstall of tm5 ).
> 
> Changes currently being tested:
> 
> upped vsoc a bit following @Veii advice preparing for testing IF2000
> cldo_vddp 900mv
> CCD a bit higher too
> IOD < vsoc-50mV a step up from my previous test
> all the rest the same.
> pbo settings the same 235/140/190 ( the last two are motherboard limits ), scalar changed to 6 and CO the same as before ( 0 -5 best cores, -15 on 3 cores and -20 the rest ). Tested with @Veii tool the SI to 117.2 at stock.
> 
> Y-cruncher passed, tm5 still running but passed so far 24 cycles.
> 
> Here's the screenshot with stock numbers too in notepad:
> 
> View attachment 2518187
> 
> 
> Quick questions:
> 
> Should I be concerned by the diff on the CPU cache numbers between stock and the settings i am trying ?
> 55.0ns, previous try with almost those settings was 55.8 ?!
> kinda nervous about windows corruption now, something I should be concerned about with those settings ?
> 
> I am going to let tm5 run overnight of course after a restart, need to use the PC...


somewhere back in this thread, theres a comment either regarding a bench OS 
(win 10) to install on a USB drive, its a stripped down version of WIN 10 that 
runs perfect for what we do here. (i was JUST on that page too and dont see it near where i thought i was)
im almost positive @KedarWolf was the one who posted it? anyhow anyhow, not quite what you asked about
but it will indeed keep your main install from corruption


----------



## Audioboxer

XPEHOPE3 said:


> System is definitely unstable. And since it happens when memory is stressed, memory influences that instability. I heard somewhere that those threads are dying because they suddenly get voltage drop/spike, so it's more of a powering issue where CPU+RAM eat from one powerbudget. There's no code in TM5 to check for such situation, so it doesn't report it as error.
> Well, judge yourself:
> View attachment 2518168
> 
> Just as in your screen, it says "Error record format is 10", and that has nothing to do with number of sources. The log also says "10 error sources are active". But as you can see from the list, there are only 9 consecutive "42" events. On my other system with Skylake CPU I have record format 10, active error sources = 5, and there actually are 5 consecutive "42" events.
> Corecycler with certain Prime95 settings isn't as heavy on memory, as TM5, I think. I cured my TM5-crashing-thread issue by going PBO *disabled *(that means stock limits) + vSOC LLC one above flat (that means the least voltage droop) + PBO scalar manual to 1x, and overall starting from scratch with XMP + GDM off + 2T. Although I left vCore LLC on Auto (most voltage droop), it might also need a change (see also start of current post)
> 
> Is it going to the list or are you still not sure?
> 
> EDIT:
> Notice how that document doesn't contain word "dataset" at all 😅 And segment length from the first glance can only be related to buffer size used, as segment length describes parts of TL-DRAM (tiered DRAM), that is, DRAM _caching_. I don't even know if it's really implemented in consumer products or not. But if it is, smaller buffer sizes might fit into caches, while dataset as a whole never would.


Best way to root out the issue mate? 25 cycles of TM5 pass, Corecycler passes for over 24 hours and I don't get things like reboots or what have you.

I guess I could just null my CPU curve just now and spend days running TM5 to see if it crashes.

Could it be anything to do with voltage settings on memory, like VSOC? Droop issues?

It doesn't happen that often (TM5 crash) so it's very hard to troubleshoot


----------



## XPEHOPE3

Audioboxer said:


> Could it be anything to do with voltage settings on memory, like VSOC? Droop issues?


You could have read my whole message 😅 , yes it can.


Audioboxer said:


> 25 cycles of TM5 pass


"But not always" 
Are you y-cruncher stable for at least 10 cycles? What about OCCT AVX2 stability?


----------



## Audioboxer

XPEHOPE3 said:


> You could have read my whole message 😅 , yes it can.
> "But not always"
> Are you y-cruncher stable for at least 10 cycles? What about OCCT AVX2 stability?


Sorry still drinking my morning coffee lol.

Y-cruncher was only 6 cycles, I'll go for longer there first. I guess I'm trying to figure out if its memory or CPU settings.


----------



## spajdr

Hello guys again,
any advice what to set differently?


----------



## Audioboxer

spajdr said:


> Hello guys again,
> any advice what to set differently?
> 
> View attachment 2518202











tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com





Rtt values maybe.

@XPEHOPE3 First time I've ever seen it but I got a PC reboot running y-cruncher, so you've helped me find out what you already knew. We're not stable! 😂

Reboots during y-cruncher, is that more likely to be on the CPU end? I'm going to null my curve at the moment anyway and run y-cruncher again.

Not had a PC reboot in ages, even during all my time running TM5 it was just those crashes in the app (and even they were rare). So I guess something is right on the edge of unstable, making me think its a curve value that might need to drop a few notches that CoreCycler just didn't catch.


----------



## spajdr

@Audioboxer ok, trying *7 / off / 5* now. Cheers


----------



## rhhek

rhhek said:


> My mismatched 48GB RAM kit (4 sticks) with my Ryzen 1600 and Asrock B450m Pro4 (1.40V DRAM limitation by the board)
> 
> The motherboard uses a daisy chain topography for the memory slots. I put the 3600 MHz kit in the "slower" slots.
> 
> Currently the 2933 MHz at 16-18-18-36-54 timing with T1 command rate + Gear Down Mode + Power Down Mode + Bank Group Swap on auto + BGS alt on auto is stable after running memtesthelper for about 36 hours.
> 
> At 3000 MHz, it was stable for about 12 hours, and then when I restarted to computer and ran the memtesthelper again, it threw a memory error in a few minutes. 3133 MHz throws errors almost as soon as I start the stability test.
> 
> I tried using T2 and disabled the power down mode with 3200 and 3133 MHz with the same timings, but both of them threw errors almost as soon as I started the memtesthelper.
> 
> I understand the CPU, motherboard and the different RAM kits are a major handicap to the RAM overclocking. I'm curious if there's still a way to go beyond the current 2933 MHz setting.
> 
> The reason why I added 32GB to my original 16GB kit is because Cities Skylines uses a little over 30GB RAM by itself, and that's after pruning the Steam Workshop subscriptions. I'm missing about 1000 props/textures for the custom buildings I'm using in order to cut down on memory usage back when I just had the 16 GB kit. Maybe I could have searched hard for a 32GB kit that matched closer to my 16GB kit.
> 
> I am currently testing 3066 MHz with Power Down Mode disabled + Bank Group Swap disabled + BGS alt enabled.
> 
> EDIT: The 3066 MHz attempt also threw memory errors.


I'm going to disable Bank Group Swap and Gear down mode just to see what would happen with the 2933 MHz.

I'm looking for a guide on how to try to tighten down the timings. I saw the one from the author of the DRAM Calculator, but I was wondering if there something more exact with stepping down the primary, secondary and then the tertiary timing values?

Alternatively, should I use the 32 GB kit's 18-22-22-42-64 timing and then try to increase the MHz?


----------



## Nighthog

craxton said:


> its not "always" that way with every board, to get FULL turning OFF of DF-Cstates
> on my MSI board, one has to set power supply idle control to "typical current idel" and set DF-States to OFF.
> if one does not set typical current idle then DF-Cstates remain "half" active leaving package state active while C6 state is off.
> this way im talking above manages this, (do note that i didnt set anything in zenstates i just opened it to show DF-Cstates are indeed off)
> unless i missed something somewhere and its not 100% off?


On Gigabyte X570 Aorus Xtreme:
*Typical Current Idle* : Package C6-States are *OFF
Low Current Idle* : Package C6-States are *ON*

There isn't another setting around to adjust this "Package C6-States"

Core C6-States can be adjusted in AMD CBS settings with the DF-Cstates.


----------



## Audioboxer

Hmm, I auto'd out my memory voltage settings and was going to try that first with y-cruncher before my CPU curve but at the last second in the BIOS I also tried dropping the auto oc boost frequency from +100 to +75.

Yeah, I know, should try one thing or one set of values at a time, but anyway, now my y-cruncher is over an hour in on its way to 10.

So it's looking like my reboot might have been too large a CPU boost value for my curve or some memory voltage settings. The fun of stability on the line, finding out that tiny bit of instability that is only cropping up rarely.

Gonna guess its the +100mhz on CPU in combination with a curve value that might need increased by like 1 or 2 notches. Dropping to +75 looks like it might have made it happy for now. Surprised 24 hours of CoreCycler hadn't picked up on this but here is a good reminder to use multiple stability testing apps.

The auto voltage values on my memory are very close to the manual settings I had dialed in. So I don't think it's the memory voltages.


----------



## XPEHOPE3

Nighthog said:


> On Gigabyte X570 Aorus Xtreme:
> *Typical Current Idle* : Package C6-States are *OFF
> Low Current Idle* : Package C6-States are *ON*
> 
> There isn't another setting around to adjust this "Package C6-States"
> 
> Core C6-States can be adjusted in AMD CBS settings with the DF-Cstates.


I couldn't have those changes stick after reboot or actually influence Package C6-States on B550 Gigabyte Aorus Pro V2 with 1.2.0.3A AGESA BIOSes. What AGESA does your BIOS use?



Audioboxer said:


> Surprised 24 hours of CoreCycler hadn't picked up on this


It tests single core, while you fail multicore. So no wonder. Total powerbudget and total heat are not tested. Please use HWiNFO to know what kind of power/volts/temps you get *per-core*, it's available in latest version.


----------



## Nighthog

Audioboxer said:


> Hmm, I auto'd out my memory voltage settings and was going to try that first with y-cruncher before my CPU curve but at the last second in the BIOS I also tried dropping the auto oc boost frequency from +100 to +75.
> 
> Yeah, I know, should try one thing or one set of values at a time, but anyway, now my y-cruncher is over an hour in on its way to 10.
> 
> So it's looking like my reboot might have been too large a CPU boost value for my curve or some memory voltage settings. The fun of stability on the line, finding out that tiny bit of instability that is only cropping up rarely.
> 
> Gonna guess its the +100mhz on CPU in combination with a curve value that might need increased by like 1 or 2 notches. Dropping to +75 looks like it might have made it happy for now. Surprised 24 hours of CoreCycler hadn't picked up on this but here is a good reminder to use multiple stability testing apps.
> 
> The auto voltage values on my memory are very close to the manual settings I had dialed in. So I don't think it's the memory voltages.


Not all cores are stable at higher frequencies.

The AUTO OC Boost settings just sets the maximum clocks allowed higher. So if you don't want overboost, you set it to a lower value or disable it overall.

I use this with my 3800X to limit clocks @ 4600Mhz for stability issues where the cores aren't stable at higher frequencies if I fully tweak it to maximum performance.



XPEHOPE3 said:


> I couldn't have those changes stick after reboot or actually influence Package C6-States on B550 Gigabyte Aorus Pro V2 with 1.2.0.3A AGESA BIOSes. What AGESA does your BIOS use?


AGESA 1.2.0.3b, F34
The latest & greatest.


----------



## Audioboxer

Nighthog said:


> Not all cores are stable at higher frequencies.
> 
> The AUTO OC Boost settings just sets the maximum clocks allowed higher. So if you don't want overboost, you set it to a lower value or disable it overall.
> 
> I use this with my 3800X to limit clocks @ 4600Mhz for stability issues where the cores aren't stable at higher frequencies if I fully tweak it to maximum performance.
> 
> 
> 
> AGESA 1.2.0.3b, F34
> The latest & greatest.


Yup I'm figuring out that is what it is. I spent about a week with CoreCyler and guides trying to reign in my curve and stability test it but obviously staying with one app has shown its limitations. Tbf I didn't know about y-cruncher until I joined in with this topic.

I mean it (CoreCyler) did root out instabilities, my final curve ended up -5 on one of my best cores, -15 on the other two and -20 on one. The rest seemed to be okay with -30. But clearly in there one or a few cores crap out with a +100mhz boost on top. Maybe even +75, but it's holding up so far with y-crunch running.


----------



## XPEHOPE3

mongoled said:


> Only CoreCycler ?
> 
> CoreCycler for me is just a primer for finding something that looks to be OK, after I found something its then onto Y-Cruncher to see if its stable, if Y-Cruncher crashes on specific tests (N32/N64 are particularly sensitive to CO) I tweak CO on core that crashed then hone in Y-Cruncher just to run on the crashing test.
> 
> Once its stopped crashing on the particular core I return to Y-Cruncher full test suite.
> 
> After Y-Cruncher is stable I do another CoreCycler, then use the system normally for an extended period of time to possibly catch idle crashes before moving to other types of stress tests


@Audioboxer see also this.
+ I remember on one of the y-cruncher tests there always is a huge temperature and current spike in the end, for less than 2 seconds, but usually it's captured by HWiNFO. I get up to 89C on tDie sensor


----------



## Audioboxer

XPEHOPE3 said:


> @Audioboxer see also this.
> + I remember on one of the y-cruncher tests there always is a huge temperature and current spike in the end, for less than 2 seconds, but usually it's captured by HWiNFO. I get up to 89C on tDie sensor


Thanks. I'm glad I'm learning all this now rather than plodding on thinking my CPU settings were locked in due to CoreCyler. It's making me wonder if some of my past errors in TM5 runs were contributed to by an unstable CPU curve 😤

That's completely on me though for either not having a 100% stable CPU or for not doing mem testing on CPU auto/safe settings.

You're right about the temps, my highest spike on tDie is reading 91 degrees! I'm liking this y-cruncher, it's pushing my PC even harder than prime95!

Water temps are still only 34-35 degrees after 2 hours of y-cruncher. So it's not the loop/fan curve, it's just that brutal pushing the CPU it can hit 91 degrees under testing 🔥


----------



## Audioboxer

Ooft, make that 92 degrees it managed to peak at.

A bit happier I _seem_ to have rooted out my CPU instability, however, this is just with a core clock boost drop from 100 to 75. Want to retest my curve again as much as I can.

Once this hits 10 going to now take my memory voltages off auto, put them back to where they were and run y-cruncher again.

Notice it maxed out my EDC, but I assume that is quite normal for this. My settings are 270 PPT, 150 TDC and 190 EDC.


----------



## fireanimal

I was more concerned with the loss of bandwidth as it should be increasing with mclk, but it actually goes down. Wondering what would cause this behavior? With the 2-3 ns latency difference that is due to me not shutting down my Aquacomputer service.












Veii said:


> I do feel between 18-22-22 and 19-19-19 everything looks fine
> Even the added latency by the SETUP times (63)
> Also very glad to see the SETUP timings "pattern" functions well ~ very very happy
> 
> Aside from the 8-9ns added ontop, it was kind of expected
> You have 12ns ontop , soo there seems to be more than one issue ~ maybe 1.8v rail being too weak higher MCLK (which can easily make 1-2ns difference ~ if it's lacking)
> But else,it looks normal
> The increase tho is quite high ~ i think to match the same ns latency for 1900, you needed a 5000+ result , or near 4800+
> @Nighthog is the person to ask S


----------



## XPEHOPE3

fireanimal said:


> the loss of bandwidth as it should be increasing with mclk, but it actually goes down.


Only if you run memclk=fclk=uclk. If you don't run it like that there has to be a delay to synchronize memclk and fclk clocks, and that delay varies nontrivially, because it *probably *involves some algebra and modulus arithmetic on clock numerators (for 1900 it's 57/3, numerator is 57, for 1933 it's 58/3, numerator is 58, etc). For example, here is me going from 3600-1800 to 3600-1900 and 3600-2000 and getting lower latency on 3600-2000. Actually on fclk 1933, 1967 and 2000 latency was similar and much less than on fclk 1900.
tldr: you can try different fclk to lower latency instead of or in addition to varying memclk


----------



## Mach3.2

Audioboxer said:


> Notice it maxed out my EDC, but I assume that is quite normal for this. My settings are 270 PPT, 150 TDC and 190 EDC.


I find the gains are really small for the amount of power you draw when you push the PPT boundary. There's really not much left to squeeze out of the 5900X/5950X if your ambient temps aren't like 10+ deg Celsius and/or you don't have a beefy custom loop with lots of thermal capacity to absorb the amount of heat these chip throw out.

I settled with 145W PPT, 105A TDC and 170A EDC for my daily PBO power limits.
My ambient temps are usually at least 30 deg Celsius on most days, just to give a frame of reference. Max Tdie temp on my 5900X are around 86 deg Celsius, cooled using a 360mm EK-aio.


----------



## Audioboxer

Mach3.2 said:


> I find the gains are really small for the amount of power you draw when you push the PPT boundary. There's really not much left to squeeze out of the 5900X/5950X if your ambient temps aren't like 10+ deg Celsius and/or you don't have a beefy custom loop with lots of thermal capacity to absorb the amount of heat these chip throw out.
> 
> I settled with 145W PPT, 105A TDC and 170A EDC for my daily PBO power limits.
> My ambient temps are usually at least 30 deg Celsius on most days, just to give a frame of reference. Max Tdie temp on my 5900X are around 86 deg Celsius, cooled using a 360mm EK-aio.


Yup, you're likely right.

When I bought my 5950x I also bought another radiator to add to my loop so I entered the world of playing with the curve and CPU settings feeling thermals are _no_ issue. And they aren't really, during demanding games I tend to have 70-75 degrees tops and most other games 65-70. Idle/desktop I don't pay too much attention to due to boost spikes, but usually around 38-50 degrees depending on what is going on.

Mafia Definitive edition is the one game that's managed to get my CPU to 80 degrees during gaming, but I've read about how poorly optimised this game is from the 2K launcher to unlocking the 60FPS cap (which I did) also causing more heat generation.

So I've been getting pretty good performance on my settings and with a reasonably generous curve. But as I have uncovered weeks and weeks later I've had a small instability tucked away that needed to be rooted out and I'm likely generating more excess heat than needed just for a tiny bit of performance.

Will likely rethink my whole approach to the 5950x but for now I'm just going to do some more testing on this curve with OCCT next and see if there is more issues than just the +100mhz setting being too high.


----------



## fireanimal

Thing is I tested this on my other system - 5950x and Samsung B-Die Dual Rank and indeed the bandwidth did increase as expected with mclk. So I don't know if its the 5800x, Single Rank Dimms, or a settings issue.



XPEHOPE3 said:


> Only if you run memclk=fclk=uclk. If you don't run it like that there has to be a delay to synchronize memclk and fclk clocks, and that delay varies nontrivially, because it *probably *involves some algebra and modulus arithmetic on clock numerators (for 1900 it's 57/3, numerator is 57, for 1933 it's 58/3, numerator is 58, etc). For example, here is me going from 3600-1800 to 3600-1900 and 3600-2000 and getting lower latency on 3600-2000. Actually on fclk 1933, 1967 and 2000 latency was similar and much less than on fclk 1900.
> tldr: you can try different fclk to lower latency instead of or in addition to varying memclk


----------



## domdtxdissar

mongoled said:


> That would be extremely fast!
> 
> The first cycle takes less time than the last cycles.
> 
> I do believe CPU frequency does play a role, but in @craxton case he is using a 5800x, where as I am using a 5600x so logically the 5800x sustained mhz should be higher than what I can achieve.
> 
> Can you double check your values for completed 25 cycles TM5 runs as *im confident that there are not too many peeps who have posted faster times than what I have* *posted* while using a 5600x with 32GB I could understand a time within 2:40 mins while using flat 14s but 2:30 is a big stretch


Here you go
32gigs @ 25 cycle = 2 hours and 35 min
Do note the dram calc bench numbers also... 








But it should also be said that this is a *faster then average* dual CCD setup  (running 4 memory sticks ontop that)


----------



## rhhek

My mismatched 48GB RAM kit (4 sticks) with my Ryzen 1600 and Asrock B450m Pro4 (1.40V DRAM limitation by the board)

The motherboard uses a daisy chain topography for the memory slots. I put the 3600 MHz kit in the "slower" slots.

Currently the 2933 MHz at 16-18-18-36-54 timing with T1 command rate + Gear Down Mode + Power Down Mode + Bank Group Swap on auto + BGS alt on auto is stable after running memtesthelper for about 36 hours. It is also stable with GDM and BGS disabled, and BGS alt enabled.

Any attempts at going for 3000 MHz with the same timings, even if I use T2 command rate, ends in a failure.

I understand the CPU, motherboard and the different RAM kits are a major handicap to the RAM overclocking. I'm curious if there's still a way to go beyond the current 2933 MHz setting.

Alternatively, should I use the DRAM calculator's 14-17-18-17-36-56 timing values to try to tighten down 2933 MHz? This is assuming that my 3200 MHz kit is weaker than my 3600 MHz kit, although I'm not sure if the slot locations for the kits also have an impact.


----------



## spajdr

@domdtxdissar thanks for the screenshot as I still have 1-2 errors during 25 cycles and wanted to see some rtt settings with someone that also have 4x8GB (although I have only Micron kits).
Or 1933Mhz may be too much for my 4x8GB config :-/


----------



## mongoled

domdtxdissar said:


> Here you go
> 32gigs @ 25 cycle = 2 hours and 35 min
> Do note the dram calc bench numbers also...
> View attachment 2518218
> 
> But it should also be said that this is a *faster then average* dual CCD setup  (running 4 memory sticks ontop that)


Yes for sure,

2 CCD CPUs are faster then 1 CCD CPUs when it comes to TM5 and DRAM Calc MemBench test (along with many other things 🤣 😀),

nethertheless very nice results


----------



## Audioboxer

Quick question because of everything all of you have helped me learn but when a core crashes should it not produce a WHEA error? Just asking as I checked my WHEA logs and I still have no errors in them.

Or does WHEA only happen sometimes with unstable cores/fabric?

I've not had any more issues, just asking as I had a thought to check my event viewer logs for reboots from earlier but no WHEA in sight. Wondered if it would help me track down what core it was that caused a reboot.


----------



## mongoled

Audioboxer said:


> Quick question because of everything all of you have helped me learn but when a core crashes should it not produce a WHEA error? Just asking as I checked my WHEA logs and I still have no errors in them.
> 
> Or does WHEA only happen sometimes with unstable cores/fabric?
> 
> I've not had any more issues, just asking as I had a thought to check my event viewer logs for reboots from earlier but no WHEA in sight. Wondered if it would help me track down what core it was that caused a reboot.


The WHEA 18 errors are not always caught in time to be written to the event log unfortunately.

Ideally you need to be able to track down which core is causing the system to halt.

I think ive seen people mention to enable logging in HWInfo64, in this way you at least know which core was running when the PC crashes

Fabric WHEAs are usually error 19


----------



## Audioboxer

mongoled said:


> The WHEA 18 errors are not always caught in time to be written to the event log unfortunately.
> 
> Ideally you need to be able to track down which core is causing the system to halt.
> 
> I think ive seen people mention to enable logging in HWInfo64, in this way you at least know which core was running when the PC crashes


Thanks, I'll keep this in mind if I get any more instability.


----------



## craxton

Nighthog said:


> Package C6-States are


so this is what i need then,


(EDIT)
SCRATCH ALL THAT.
so, MSI users/ maybe others, (i know its been shown but that turned off both packagec6 and C6 residency
so here goes, set what you see in the FIRST PIC then REBOOT!!!!
then go back into bios, and change NBIO option shown below...
i set and TRIED and TRIED to get that working the other way around, but the main page takes PRIORITY
as always on this board and the other MSI boards i had....

(if another MSI user wishes to confirm this is correct?? on how they too
would get C6 package off and C6 residency on)

















now, to get COMPLETE package and C6 residency both to be off just simply set
typical power (power supply idle control)
and turned OFF df-cstates. (turning off DF-Cstates doesnt turn off both, just c6 residency
(to anyone needing this, sorry if its not understandable)
im pretty sure C6 residency is what Veii stated to be turned on which looks like the image below
using zenstates debug. (if it looks any other way that might be why you crash)
strange one has to have an unlocked BIOS to get this to set. so if you have an MSI board,
you can grab a modded bios from Eder here (dont blame anyone but yourself if you try this,
and BRICK your board, its not easy to brick a MSI board with bios flashback features!)


----------



## spajdr

Hi guys, still can't figure out what RTT settings I should try, getting 1 or 2 errors at test #4 during 40m up to 120m.
No WHEA errors.
VDIMM 1.8V


View attachment 2518202


----------



## Audioboxer

I don't know if anyone helping me out before remembers me saying over DDR-3400 I couldn't get anything other than RttPark 1 posting, well, I just tried something I probably should have then which is just trying 1 stick of the 16GB.

Because that's my issue. One stick will boot RttPark 3 fine even at DDR-3800, the other won't.

Does this just mean one of my sticks of RAM is the lowest common denominator and is holding the other back?


----------



## gled_fr

Audioboxer said:


> I don't know if anyone helping me out before remembers me saying over DDR-3400 I couldn't get anything other than RttPark 1 posting, well, I just tried something I probably should have then which is just trying 1 stick of the 16GB.
> 
> Because that's my issue. One stick will boot RttPark 3 fine even at DDR-3800, the other won't.
> 
> Does this just mean one of my sticks of RAM is the lowest common denominator and is holding the other back?


I had this issue with my previous ram kit, but they were not b-die... and indeed, one stick was better than the other, had to tune to the bad one ( with the limited tuning I did ).


----------



## fireanimal

Here is a set of Micron Rev B's at 3800 CL13. Just wondering if there is any other minor tweaks I can do to this set. Also tRCDRD is at its lower limit, no matter what I do I cannot even post if I lower it.


----------



## XPEHOPE3

Audioboxer said:


> One stick will boot RttPark 3 fine even at DDR-3800, the other won't.


Now that's interesting. Did you just post or run TM5? Was the better stick in the "better" or "worse" RAM slot originally? I don't remember if you tried switching previously and if you have 2- or 4-slot motherboard. But assuming 4-slot, you can try putting best stick to A2 and worse to B2 (then you'd be along what @craxton did) or best stick to B2, worst to A2 (setup a-la @mongoled )


----------



## gled_fr

And the result, 60 cycles, one single error 4 on the 58th cycle :/ but at least no freeze !








At that point, kinda tempted to try to go directly to cl14 or higher IF, chasing that single error 4 is gonna be painful. From previous tests, it was hard.

I wonder if I should not just disable RttNom and go Park/1 like it is on stock, lowering also the different *str to flat 24 like stock... Is there any drawback or an obvious better way ?


----------



## gled_fr

domdtxdissar said:


> Here you go
> 32gigs @ 25 cycle = 2 hours and 35 min
> Do note the dram calc bench numbers also...
> 
> But it should also be said that this is a *faster then average* dual CCD setup  (running 4 memory sticks ontop that)


Kinda curious about your PBO settings for the high CB score ! The highest I went was in the 29k...

Kinda tempted to test your RTT and Str sets too, since chasing a very rare issue, but it probably would not work , you have single rank and I have dual ranks...

Also, what is your vdimm ?


----------



## Audioboxer

XPEHOPE3 said:


> Now that's interesting. Did you just post or run TM5? Was the better stick in the "better" or "worse" RAM slot originally? I don't remember if you tried switching previously and if you have 2- or 4-slot motherboard. But assuming 4-slot, you can try putting best stick to A2 and worse to B2 (then you'd be along what @craxton did) or best stick to B2, worst to A2 (setup a-la @mongoled )


Better slot, A2/B2. All I did was remove the B2 stick, turn back on, go 6/3/3, reboot and let it boot into Windows to confirm timings in ZenTimings.

Then thought I'll try the other stick on its own and it wouldn't post.

But heres where things now get even more messed up. Neither stick will post... LOL.

Cause I tried the stick that was posting on its own again to see if TM5 would run for a bit and I can't get it posting.

So I went away there and dug out my Corsair Vengeance Pro Micron E Die. Displays the exact same issue the B Die does, will post RttPark 3 up to DDR4-3400, will not post any higher.

I know Micron E Die isn't quite as good as B Die and this isn't the best bin ever (18-22-22-42) but that is far too much of a coincidence.

So I guess it's likely my motherboard or CPU? More likely motherboard? I'm going to go get some much older bios versions and give them a go.

No one else in here seems to be running an X570-F Strix so I don't have any comparison to other users on this mobo running RttPark 3 fine on the latest two BIOS revisions.


----------



## craxton

Audioboxer said:


> Better slot, A2/B2. All I did was remove the B2 stick, turn back on, go 6/3/3, reboot and let it boot into Windows to confirm timings in ZenTimings.
> 
> Then thought I'll try the other stick on its own and it wouldn't post.
> 
> But heres where things now get even more messed up. Neither stick will post... LOL.
> 
> Cause I tried the stick that was posting on its own again to see if TM5 would run for a bit and I can't get it posting.
> 
> So I went away there and dug out my Corsair Vengeance Pro Micron E Die. Displays the exact same issue the B Die does, will post RttPark 3 up to DDR4-3400, will not post any higher.
> 
> I know Micron E Die isn't quite as good as B Die and this isn't the best bin ever (18-22-22-42) but that is far too much of a coincidence.
> 
> So I guess it's likely my motherboard or CPU? More likely motherboard? I'm going to go get some much older bios versions and give them a go.
> 
> No one else in here seems to be running an X570-F Strix so I don't have any comparison to other users on this mobo running RttPark 3 fine on the latest two BIOS revisions.


clear cmos when swapping these sticks out. give that a shot, unless you did.
SAVE any profiles to a usb stick that you wish to keep however


----------



## domdtxdissar

gled_fr said:


> Kinda curious about your PBO settings for the high CB score ! The highest I went was in the 29k...
> 
> Kinda tempted to test your RTT and Str sets too, since chasing a very rare issue, but it probably would not work , you have single rank and I have dual ranks...
> 
> Also, what is your vdimm ?


I'm using CTR instead of PBO..
Vdimm @ 1.54 in bios (=1.537 average)









If you want to use PBO CO with a 5950x + asus motherboard i can recommend 245edc 225tdc and whatever PPT limit your cooling can handle. (asus bios 3003 have the fastest PBO CO boosting with the correct tweaks/secrets, but memory-training and usb drop-outs etc can be a problem there, reason i went to a newer bios is because usb problems with hp reverb g2 )
Screenshot below is my alltime high in Cinebench, done with PBO CO on bios 3003
(have never been able to match this ST scores with CTR)








And some y-cruncher scores at same settings:


----------



## Audioboxer

craxton said:


> clear cmos when swapping these sticks out. give that a shot, unless you did.
> SAVE any profiles to a usb stick that you wish to keep however


Yeah I've been using my screwdriver to clear CMOS over and over lol

Downloading a number of older BIOS versions right now to give them a whirl.


----------



## gled_fr

domdtxdissar said:


> I'm using CTR instead of PBO..
> Vdimm @ 1.54 in bios (=1.537 average)
> 
> 
> If you want to use PBO CO with a 5950x + asus motherboard i can recommend 245edc 225tdc and whatever PPT limit your cooling can handle. (asus bios 3003 have the fastest PBO CO boosting with the correct tweaks/secrets, but memory-training and usb drop-outs etc can be a problem there, reason i went to a newer bios is because usb problems with hp reverb g2 )
> Screenshot below is my alltime high in Cinebench, done with PBO CO on bios 3003
> (have never been able to match this ST scores with CTR)


Thanks, have not been using CTR yet. PBO is pretty good, although since the latest bios ( 4002 ) it seems like even if I put bigger edc and tdc, bios enforce the motherboard limits ( 190 / 140 ).
Seen that in hwinfo while running occt power test, even if I put stronger edc/tdc, it still caps at 100% at those limits.

I'll give a try to CTR at some point ! For now trying to stabilize that memory single error 4 after 6h run of tm5 is not fun


----------



## Audioboxer

Tried a couple of even older BIOS revisions, no joy. Either I have two sets of memory that won't post RttPark 3 above 3400, my mobo has issues or it's maybe the CPU? Makes next to no sense one stick booted it once but I can't get it to do it again lol.

Gonna have to wait until Amazon refund me and I pickup some more RAM I guess. Or hunt down someone else who has a X570F Gaming board and see if it has any issues with RttPark values.


----------



## JellyFish3D

craxton said:


> have an unlocked BIOS to get this to set. so if you have an MSI board,
> you can grab a modded bios from Eder here


I don't have "AMD CBS" menu under "Settings\Advanced\..." and therefore have to use ZenStates to Enable Core C6-State, otherwise both are off upon boot in ZenStates. Now sadly I have b450 and don't seem to find any recently modded BIOSes out there and it is most likely VERY bad idea for me to try flash B550 tomahawks BIOS. 

Let's say I'm feeling adventurous and would like to attempt modding (unlocking locked options) in my BIOS for B450 tomahawk, where should I look?
I know there is a guide on win-raid on how to update/replace modules but how does one unveil the good stuff in BIOS?


----------



## PeterPete

Hello guys I´ve tried to read up on the last 50 pages but I still have a couple questions for my 24/7 timings. 










It´s stable on tm5 and Karhu but I´m still unsure about:

1. my tCCD_L is 7. Should i adjust tFAW then or am I gonna be fine?

2. I have no idea what to do with tWRRD. Should i just keep it at 4 or is 3 or 1 better in terms of stability? 

3. Same goes for tRTP. Should i increase it to 9 or is 8 fine?


----------



## craxton

JellyFish3D said:


> I don't have "AMD CBS" menu under "Settings\Advanced\..." and therefore have to use ZenStates to Enable Core C6-State, otherwise both are off upon boot in ZenStates. Now sadly I have b450 and don't seem to find any recently modded BIOSes out there and it is most likely VERY bad idea for me to try flash B550 tomahawks BIOS.
> 
> Let's say I'm feeling adventurous and would like to attempt modding (unlocking locked options) in my BIOS for B450 tomahawk, where should I look?
> I know there is a guide on win-raid on how to update/replace modules but how does one unveil the good stuff in BIOS?


good question to which, im not able to answer as i aim to mod bios options as well.
but lack the "know-how" to do such.
the link i posted has your board in there i do believe. you just download it
to your flash drive and flash it normally. thats about it. unsure if he has updated you
to the latest version or not, as hes been busy lately.
but it should be the last version at the latest.
(edit) by version i mean bios revision/agesa!



PeterPete said:


> Should i adjust tFAW then or am I gonna be fine?


4* tRRD_S so, 4x4=16



PeterPete said:


> Same goes for tRTP. Should i increase it to 9 or is 8 fine?


im unsure the rule here, but if you use this
it should help you (although) before it wasnt allowing one to change some of the
things its allowing now, as it might be broken.
if you increase tRTP you can use this to get your tRFC values and
if your using 8 tRTP then 384/285/176
i believe would be your tRFC value needed for tRTP *8
the tRFC values your using however im pretty sure are tRTP *6
for 288/214/132
i could be wrong, so dont hold me to this....


----------



## PeterPete

craxton said:


> im unsure the rule here, but if you use this
> it should help you (although) before it wasnt allowing one to change some of the
> things its allowing now, as it might be broken.
> if you increase tRTP you can use this to get your tRFC values and
> if your using 8 tRTP then 384/285/176
> i believe would be your tRFC value needed for tRTP *8
> the tRFC values your using however im pretty sure are tRTP *6
> for 288/214/132
> i could be wrong, so dont hold me to this....


thanks for the tool! i didnt knew it existed


----------



## JellyFish3D

craxton said:


> the link i posted has your board in there


I can't see any B450's here, I'm on my own. If someone could direct me to "how to" unlock BIOS options I could give it a try, after all there is a flashback option on this mobo so I don't see why not break some stuff for fun.


Spoiler: GDrive folders


----------



## craxton

JellyFish3D said:


> I can't see any B450's here, I'm on my own. If someone could direct me to "how to" unlock BIOS options I could give it a try, after all there is a flashback option on this mobo so I don't see why not break some stuff for fun.
> 
> 
> Spoiler: GDrive folders
> 
> 
> 
> 
> View attachment 2518258


well, thats one thing i didnt pay attention to, assumed i seen b550 for whatever reason.
im unaware if youll find it anywhere. but you might be able to "use his paypal" and send him a DM thru here
to get it done, otherwise my apologies.


----------



## PJVol

PeterPete said:


> my 24/7 timings


Can't your CPU boot at 1900 fclk and so run memory @3800 or do you just want to limit RAM voltage for 24/7 ?


----------



## PeterPete

PJVol said:


> Can't your CPU boot at 1900 fclk and so run memory @3800 or do you just want to limit RAM voltage for 24/7 ?


unfortunately my cpu cant handle 1900 
im hoping a future agesa update for my mobo will fix it since im still on 1.2.0.0


----------



## craxton

@JellyFish3D 
is there a reason you have a 5600x paired with a b450 board?
atm one can nab the tomahawk b550 on amazon for 100 usd. (used-good)
which is what condition i nabbed my gaming edge wifi board in which (was still brand new) minus the box being
opened all the other stuff inside had not been, thus was able to register warranty etc.
i know replacing an entire board is not logical and im only stating this as im looking for an EXTREMLY CHEAP 
2 dimm board (probably b450) to avoid gen 4 chipsets to try this 5800x in at 4000/2000 without WHEA 19s.
(again, not a logical thing) but regardless if i get a board and indeed i dont have WHEA 19s (board without gen 4 support)
then well, we shall see.


----------



## PJVol

*mongoled*
Managed to improve a bit, but I think it should have been like this from the start - something was wrong with prev tests:








Details for Result ID AMD Ryzen 5 5600X 6-Core Processor (6C 12T 4.85GHz, 1.9GHz IMC, 6x 512kB L2, 32MB L3)







ranker.sisoftware.co.uk


----------



## JellyFish3D

craxton said:


> is there a reason you have a 5600x paired with a b450 board?





Spoiler: The reason



I wasn't planing from the start to go with B450 and 5600X, bought tomahawk and 3600 together a while ago, somewhere in the end of 2019. Recently saw unopened 5600x on sale locally for cheap and couldn't resist, ended up selling my older 3600 and in total got 5600X for 95$.



I get WHEA warnings on boot even WITH the "WHEA Error suppressor". I seem to get less of them depending on SoC voltage and therefore have bumped it up a few steps from recommended minimum of "4000 - <1137,5mV". CCD and IOD seem to also have and affect, anything below 1040 CCD plagues me with WHEA warnings on boot, IOD at 1V and below destroys my memory latency. I was playing with these voltages yesterday and thought that I somewhat fixed these warnings made atleast 20 reboots and was getting anywhere from 0 to 4 warnings and called it a day. Today upon rebooting today it seems like I'm back at square one and haven't really done anything. This is insanity.


Spoiler: WHEA warnings 19















I seem to have fixed my TM5 freeze issue though, yeah I had it as well but my first thoughts on it were that "I probably have done too many cycles" and didn't bothered looking back at it. I believe for me it was disabling c-states and setting idle control to "typical current idle". Although I can't be sure yet, I will test overnight again just to be sure. Beside c-states I have also disabled monitor sleep and made slight changes to CCD and IOD voltages, anyways here are the results so far.


Spoiler: 150 cycles















Now I do have CO on and PBO with these limits PPT 100 TDC 90 EDC 400. The way I "calculated" my CO's was by the method Veii have proposed a while back before/after? the thread was closed for cleanup. There was a cheat sheet with which you could translate your CPPC's to CO's. Can't seem to find the post again, perhaps because it was just an experiment and it is gone now (the cheat sheet)?
I seem not to have any crashes or reboots for the past over 3 weeks (gaming/idling/videos&music) with the calculates CO's (16.16.19.23.21.17), I did run y-cruncher with these for total of about 15 hours aswell as CoreCycler for also about the same amount of time (probably should still do more CoreCycling), no cores crashing. This could very well be the culprit of my issues with TM5 "freezing" if these CO's are wrong.


----------



## Veii

JellyFish3D said:


> Now I do have CO on and PBO with limits these limits PPT 100 TDC 90 EDC 400. The way I "calculated" my CO's was by the method Veii have proposed a while back before/after? the thread was closed for cleanup. There was a cheat sheet with which you could translate your CPPC's to CO's.


here 








5900x CCX Temperature Delta


Hello! with my 5900x i am observing an 8-9K Temperature Delta at full load. see screenshot. Curve Settings are all in range of -21-30 with exception of core0 at -16. So i dont suspect it to be accountable. Cooler is an ekwb supremacy evo with about 85l/h flow rate. is it worth considering a...




www.overclock.net




still valid but hard to explain

It's how Project Hydra will function (similar)
Although PHydra is far more advanced 
You are sure that it's y-cruncher stable in the first place ?


JellyFish3D said:


> I did run y-cruncher with these for total of about 15 hours aswell as CoreCycler for also about the same amount of time


Alright
I dropped mine another -2 , all together for higher sustained frequency & because cores could do it


----------



## JellyFish3D

Veii said:


> here
> 
> 
> 
> 
> 
> 
> 
> 
> 5900x CCX Temperature Delta
> 
> 
> Hello! with my 5900x i am observing an 8-9K Temperature Delta at full load. see screenshot. Curve Settings are all in range of -21-30 with exception of core0 at -16. So i dont suspect it to be accountable. Cooler is an ekwb supremacy evo with about 85l/h flow rate. is it worth considering a...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> still valid but hard to explain
> 
> It's how Project Hydra will function (similar)
> Although PHydra is far more advanced
> You are sure that it's y-cruncher stable in the first place ?
> 
> Alright
> I dropped mine another -2 , all together for higher sustained frequency & because cores could do it


I mean i have this screenshot, you'll just have to believe me that CO's are (16.16.19.23.21.17)  This is without C-States and with Typical current idle I believe. Minimum vcore seem to drop to 0.200 with C-states and low current idle.


Spoiler: y-cruncher















My CPPC's are (pardon the awful phone pic, needed a picture to set stuff up in BIOS). This was taken with 10x scalar, wiped CO's. Although CTR have always seemed to crash on me, even on stock without manual CO's, probably because of overboosting. I don't think that I was disabling C-states back then. I should probably try again.


Spoiler: CPPC


----------



## Veii

JellyFish3D said:


> This was taken with 10x scalar, wiped CO's.


Neither Scalar nor CO's will influence ACPI / CPPC rating 


JellyFish3D said:


> Although CTR have always seemed to crash on me,


Can you verify if you are a pure 6 core unit ? ~ ZenTimings Debug
You could need +5 or +10mV positive vcore offset

You should also start with less frequency and not +200 limiters, to figure out CO range
I think you can hold it, but idk how many -2 steps you need to go down, before it's stable
at the end, it frequency throttles only because of Voltage and barely because "cores are weak"
Weak cores crash

X10 is also too strong, X6 is fine, X8 was the max i needed - X7 runs


----------



## JellyFish3D

Veii said:


> Neither Scalar nor CO's will influence ACPI / CPPC rating


Do I miss something? 


Spoiler: Manual CO X1 Scalar PBO 100 90 400 - CPPC's

















Spoiler: No CO Auto Scalar PBO 100 90 400 - CPPC's

















Veii said:


> Can you verify if you are a pure 6 core unit ? ~ ZenTimings Debug





Spoiler: ZenTimings Debug


----------



## Veii

JellyFish3D said:


> Do I miss something?


Interesting.
It rather looks like a bug than anything else
It really should not modify it.
But i had powerplans change it's behavior and readouts

The remain funny thing is that the "quality distance" matches
But i can not deny that boards might cheat here again
What happens on X2 scalar ? compared to X1
i'll double verify it ~ but it sounds to me like another bug


Veii said:


> It really should not modify it.


Modify i mean "influence" it
CPPC ratings aside from FIT being constantly having an eye on the cores & adjusting itself
CPPC tags have to be "looted out" on post , and fully be OS independent
Unless something with CPPC Preferred cores & CPPC on it's own breaks for you

This distance should also be visible / testable with tool.exe ~ AMD V/F Curve





Tool1007.zip







drive.google.com




At best it varied between 0.5-1 value
I'll test it now to see what's up , brb


----------



## JellyFish3D

Veii said:


> What happens on X2 scalar ? compared to X1


Looks the same with X2 scalar NO CO's with previous PBO limits.



Spoiler: X2 Scalar

















Veii said:


> But i had powerplans change it's behavior and readouts


I am using custom powerplan found here on forum but I also changed to stock Balanced powerplan just to check and CPPC remained the same.


Spoiler: Powerplan


----------



## JellyFish3D

Veii said:


> This distance should also be visible / testable with tool.exe ~ AMD V/F Curve
> 
> 
> 
> 
> 
> Tool1007.zip
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> At best it varied between 0.5-1 value
> I'll test it now to see what's up , brb


My Sil Quality seem to differ depending on settings, variance on both is within 0.5-1. This is on stock Balanced powerplan.


Spoiler: No CO X6 Scalar PBO 100 90 400

















Spoiler: Manual CO X6 Scalar +200 PBO 100 90 400


----------



## Veii

JellyFish3D said:


> Looks the same with X2 scalar NO CO's with previous PBO limits.
> 
> 
> 
> Spoiler: X2 Scalar
> 
> 
> 
> 
> View attachment 2518305
> 
> 
> 
> 
> 
> I am using custom powerplan found here on forum but I also changed to stock Balanced powerplan just to check and CPPC remained the same.
> 
> 
> Spoiler: Powerplan
> 
> 
> 
> 
> View attachment 2518307


Here it is








I know faking can be easy , but you gotta believe me 
On the powerplan, you might need to remove the maximum boost limits to show your true ACPI values - but it wouldn't matter all too much


JellyFish3D said:


> My Sil Quality seem to differ depending on settings


I see, i don't have such
But i can see why "the result could be better" with good CO limits


----------



## JellyFish3D

Veii said:


> I know faking can be easy , but you gotta believe me


I believe you  

I confirm no differences between scalar changes, stuff gets funky when I change boost limits as well as CO's.


Spoiler: CPPC and Sil qual change on frequency limit +100

















Spoiler: Sil qual only change upon disabling CO with previous settings


----------



## byDenoso

Finishing the tests with tRC 56, seems stable for now.


----------



## mongoled

Audioboxer said:


> Tried a couple of even older BIOS revisions, no joy. Either I have two sets of memory that won't post RttPark 3 above 3400, my mobo has issues or it's maybe the CPU? Makes next to no sense one stick booted it once but I can't get it to do it again lol.
> 
> Gonna have to wait until Amazon refund me and I pickup some more RAM I guess. Or hunt down someone else who has a X570F Gaming board and see if it has any issues with RttPark values.


Try to reseat the CPU.

If I were to choose between either the motherboard or the CPU being the cause I would probably pick the CPU, but thats just going on a hunch.

Very much doubt you were unfortunate enough to have two different types of dimms that show the same issue.



PJVol said:


> *mongoled*
> Managed to improve a bit, but I think it should have been like this from the start - something was wrong with prev tests:
> 
> 
> 
> 
> 
> 
> 
> 
> Details for Result ID AMD Ryzen 5 5600X 6-Core Processor (6C 12T 4.85GHz, 1.9GHz IMC, 6x 512kB L2, 32MB L3)
> 
> 
> 
> 
> 
> 
> 
> ranker.sisoftware.co.uk


Are you using 24/7 settings or your benchmark settings for that run ?

Have only ever run Sandra with my 24/7 settings.

@Veii I imagine that score of yours, 95.92GB/s, is a bugged run ??

I have one like that from my x370 motherboard

Details for Result ID AMD Ryzen 5 3600 6-Core Processor (6C 12T 4.52GHz, 1.91GHz IMC, 6x 512kB L2, 2x 16MB L3) - 95.99GB/s


----------



## Audioboxer

mongoled said:


> Try to reseat the CPU.
> 
> If I were to choose between either the motherboard or the CPU being the cause I would probably pick the CPU, but thats just going on a hunch.
> 
> Very much doubt you were unfortunate enough to have two different types of dimms that show the same issue.
> 
> 
> Are you using 24/7 settings or your benchmark settings for that run ?
> 
> Have only ever run Sandra with my 24/7 settings.
> 
> @Veii I imagine that score of yours, 95.92GB/s, is a bugged run ??
> 
> I have one like that from my x370 motherboard
> 
> Details for Result ID AMD Ryzen 5 3600 6-Core Processor (6C 12T 4.52GHz, 1.91GHz IMC, 6x 512kB L2, 2x 16MB L3) - 95.99GB/s


So it's time to drain my whole loop and go again xD

Just before I do this can anyone explain how or why the CPU might cause this?


----------



## PJVol

mongoled said:


> Are you using 24/7 settings or your benchmark settings for that run ?


24/7, i.e. PBO2 / mem [email protected]


Veii said:


> Neither Scalar nor CO's will influence ACPI / CPPC rating


Boost Override do influence.


----------



## Robostyle

Guys, could somebody help with training settings? TM5 gives me 3 errors in 25 cycles - 4,9,14
vDIMM 1.42v. Tried 1.38V and 1.4V before - tm5 ended with error 2.


----------



## Audioboxer

Robostyle said:


> Guys, could somebody help with training settings? TM5 gives me 3 errors in 25 cycles - 4,9,14
> vDIMM 1.42v. Tried 1.38V and 1.4V before - tm5 ended with error 2.
> View attachment 2518323


You might need to pump VDIMM up to 1.45v for that bin at CL16 and I'd also run the DrvStr on auto at first or maybe 24/20/24/24. Put ProcODT back to 40 or 43.6 whilst doing that as well.

I'm no expert, but the main thing I'd try first is getting a reasonably tight main and secondary timing set stable on as close to auto settings as possible when it comes to the right hand side with ZenTimings. Leave more of the tinkering with resistances when you are trying to really tighten up, drop CL or maybe give 1T a go with GDM off.


----------



## Robostyle

Audioboxer said:


> You might need to pump VDIMM up to 1.45v for that bin at CL16 and I'd also run the DrvStr on auto at first or maybe 24/20/24/24. Put ProcODT back to 40 or 43.6 whilst doing that as well.
> 
> I'm no expert, but the main thing I'd try first is getting a reasonably tight main and secondary timing set stable on as close to auto settings as possible when it comes to the right hand side with ZenTimings. Leave more of the tinkering with resistances when you are trying to really tighten up, drop CL or maybe give 1T a go with GDM off.


That's what auto set me to - 43.6, 24/24/24/24.
HCI Memtest is 2000% stable though.
Couldn't stabilize tRCDRD at 16, no matter what voltage I threw on it


Spoiler: HCI














Does it mean TM5 is more "robust"?

P.S. Made my assumptions back from my intel tests


Spoiler: Gskill















That is vDIMM 1.425.


----------



## hazium233

craxton said:


> well, i cant pass y-cruncher with any less IOD/CCD voltage ranges.
> and for sure cant stay in windows with anymore cLDO_VDDP voltage as i hard crash no BDOS/GSOD
> no WHEA 18 logged or anything of the sort.


Hmmm, 30417 is basically like 1901MHz FCLK so if it was consistent it is like BCLK or just FCLK was a little higher than set. Or it was set and I missed that part.

I don't know that I had tweaked all the miscellaneous unlocked settings in the mod bios 1.60 to full benefit, plus my testing amount went down a lot recently, heh.


----------



## Veii

craxton said:


> (anything over 930mv on CLDO_VDDP crashes the machine) no matter if i use 50mv stepping
> all the way to 70mv stepping hitting the "max" iod ccd voltage ranges that i have bookmarked as
> a recommended value to not go over....needless to say, i think anything "under" 2000fclk ill be able to do
> before long, but its still not 2000 🥺


It might have a chance 
I had at the very very start CCD issues beyond 940mV
IO Error #19 you won't likely be able to resolve, till we get it correctly nailed down and inspect more of our brolken dual ccd units ~ to find a pattern
Unless they swapped factory or GLFO has internal production line issues ~ such should not vary thaat much
WHEA is not an IMC error for sure. A bad IMC will refuse to post or only error #6 & error clearly on y-cruncher FFT



craxton said:


> might i ask, whats bad for it this way?


Disabling C-State generation, fixes the CPU at P0 powerstate = 3.7 or 3.8Ghz
Then does PBO boost upwards yet falls back to 3.7Ghz
This is as so problematic, because 3.7 requires around 1025-1100mV sustained ~ to keep cores alive.
You lose at absolute minimum 20W from the powerbudget or 200mV in potential savings (per core so to say)
You also lose the ability to have dLDO averager function & it won't put cores to hibernation or parking without this functionality

Cores do not have to join lowest P3 state (sub 550mhz) in order to be parked or hibernated (sleeping is deep suspension, sorry for the confusing of words)
They don't have to drop to 900-920mV in order to be qualified as "parkable" ~ soo "technically" Vermeer doesn't need powerplans
But without this feature enabled, not only are the powerstep jumps too harsh (if they even function bellow P0 state) , but you waste far to much powerdraw for nothing
6 core units are already soo restrictive in their by AMD defined specs ~ and dual CCD units require it + CPPC in order to keep signal integrity high

It has only negative effects not using it ~ technically also not using DF-C States but nothing we can do against Overboost Bugs till AMD fixes it hopefully with 1203B or 1.3.0.0


tcclaviger said:


> Well, the Patriot Viper PVS416G440C9K arrived, 4 sticks. Serials are... close to sequential, there's 1 box between their numbers. Confirmed A2 PCB with extra capacitors, like Buildzoid's sets are, testing on C6H and 3900x before swapping into the watercooling setup, the Team Dark Pro B-die in the water rig now are so good I'll be surprised if the Vipers can beat them.


Good success !
If you need RTT values to test as 4x A2 on Daisy Chain is painful ~ just complain in this thread


rhhek said:


> I understand the CPU, motherboard and the different RAM kits are a major handicap to the RAM overclocking. I'm curious if there's still a way to go beyond the current 2933 MHz setting.


Take a read here








NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking...


Quote: Originally Posted by xcr89 trfc (alt) same value should go in trfc2 and trfc4? The CLDO_VDDP says 425 it should be 0.425 in bios? Any idea how i can improve my timings further or what values i should try out to get better ns on memory, the docp profile that i based the fast preset on...




www.overclock.net




cLDO_VDDP is very important for Summit Ridge and Pinnacle Ridge 
A B350 board can run +3600MT/s easily , likely even 3733+
People overjudge these entry level boards ~ it's nearly always user error
Grab TM5 to test things. https://www.overclock.net/attachments/tm5-zip.341454/
It's good to know "you error" but this knowledge helps nobody.
Get this thing and look up the error descriptions here:








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com






XPEHOPE3 said:


> I was asking once how to set RTT_WR to non-auto, if it just doesn't post. Do I have to force tCKE off from 1 to enable powerdown?


Usually no, tCKE in combination with RTT_WR makes issues
Same as CAD_BUS TIMINGs do ~ but they coexist together with a lot of work

RTT_WR changes NOM and PARK behaviour once you enable or change it's strengthness
I do have a feeling /2 requires high VDIMM-IN to even function, but /3 has to run close to always
Using RTT_WR generally has a RTT_PARK range. Barely any influence to RTT_NOM
If WR trows errors ~ it's because WR keeps autocorrecting and something bothers it. Be it too low ClkDrvStr , tCKE usage or SETUP Times usage
If it fully refuses to post - either PARK is too strong , or non existent
I'd need an example of what doesn't work for you 


XPEHOPE3 said:


> automation script to collect per-cycle screenshots with information if there were any errors


A screenshot tool that barely uses RAM would be really helpful for it.
It's beyond me why TM5 never get's updated to log better before a BSOD or reboot corrupts the log.txt ~ but that's the dev's problem 


XPEHOPE3 said:


> Notice how that document doesn't contain word "dataset" at all 😅 And segment length from the first glance can only be related to buffer size used, as segment length describes parts of TL-DRAM (tiered DRAM), that is, DRAM _caching_. I don't even know if it's really implemented in consumer products or not. But if it is, smaller buffer sizes might fit into caches, while dataset as a whole never would.


mmm, personal wording vs public phrasing
I need to work on it. Am no engineer (not directly, methodology is a bit different than engineers one)


Audioboxer said:


> Not sure if this question was inspired by me mentioning the "gap", but I took my advice from @Veii who said a 0.5 difference between VSOC and VDDG is required for optimal running.


40mV
50mV stepping is Matisse, while according to The Stilt's extensive research, it's 42mV before hard crash, but AMD's behaviour was 50mV
Vermeer is 40mV, or any fixed mV stepping - as long as consistency remains and you scale that up


byDenoso said:


> Almost 0.5ns Gain over the last timings set.


How's actually the progress for you fighting against the latency loss ?


Kristoast said:


> Here is ZenTimings for where I am definitely stable(TM5 anta777extreme, Karhu 5000%+), docp enabled but dropped to 3666. DRAM voltage at 1.4
> 
> 
> 
> 
> 
> 
> 
> 
> Any thoughts or suggestions?


You won't like this reponse 
cLDO_VDDP is far to high
Match it as absolute minimum with VDDG CCD, which if really stable on stock ~ looks fine at 950mV
It is influencing at what MCLK you can post but lower is always better ~ as it allows for lower procODT to function (if remain powering is correct)

Is this 4x8GB Micron Rev.E ?
Or maybe Hynix CJR ?

You want to push ClkDrvStr to something along the lines of 30-20-30-20 for the start
Maybe 40-20-30-24 if the board struggles with 4 dimms

You also want to work GDM away and start your foundation as GMD off 2T ~ yes it's faster , and saves time for you
Give SD,DD's a try as 1-4-4-1-6-6 (tRDRD = 4-4)
In the ASUS Bios go to Tools - ASUS SPD-Z , disable first both armory crates and other asus spyware (if something more is left) & read out the XMP profiles
The Bios will generate tCCD_L value for you. Remember it , it is important
Check all 4 dimms if they have the same tCCD_L value
If it's 6, then use tRRD_S * tCCDL (6) = 42 for you.
If it's 7 , then you likely are looking at 49 as a value

Let us know which ICs these are , then we can talk about a baseline 
For tRAS as a baseline you want tRCD*2 + tCCD_L . This will always work, doesn't matter how bad the kit is.
Then tRC = tRP + tRAS (which will also always work if tRAS is correct to begin with)


mongoled said:


> @Veii I imagine that score of yours, 95.92GB/s, is a bugged run ??


I think it was legit, but looking at March ~ it might have been a 4.95+ Ghz run + BCLK 102
At the time i didn't have any Patch-D bios and played around how to exceed 1.1.0.0A functionality
Yet BAR mode and Curve optimizer functioned fully (aside from all the marketing nonsense and disagreenment)
This was 1202 with the cache boost then








It's close, but i have focused on something else - likely it doesn't show the best potential usecases
Didn't even notice 95 was "a lot" at this point of time
Was just comparing Inter-Core Latencies and where throttle really happens ++ how powerplans scale up
Was also trying to see why Inter-Thread can not be lower than 9.5ns & breaking 20ns wall ~ yea about that, been some time / haven't score focused benched on it


Spoiler




















^ same day as above









^ this one was from February, 12th (to this day i haven't beaten my multi score lol)


This was from 28th of November, where i played between minimum Idle states learning the overboost "bug"
7% idle state was the best result on 4.65 stock


Spoiler














This was near the end of February and could match. Yes i was playing with BLCK and how i noticed that RC03 CTR Core-Layout Remap, "broke" my first core
But i am sure, i've never run CTR + SiSandra
Never really had "bugs" with SiSandra , but i surely played a lot of with powerplans and utilizing overboost (maan i need to finish my powerplan someday zZZ)

Sadly i corrupted at the end my main install and lost quite a few pictures. Wiping then Twitter to free up the nametag also didn't help the issue much
Seems like i have to score a 100GB/s result, to be happy these days ^^#
==============================================================
Aaa soo many pings, i can't find the message about the vcore offset question 😐 excuse me,
Pretty much the reason i use it, aside from having a unit with broken V/F curve for the cores (soo fixing it that way, as it was designed/binned for a 5950X to begin with)
Is to match board specific vdroop. Generally fight against ripple by using more droopy loadline + slight positive vcore offset ~ matching VID as close as possible to V-TEL (applied telemetry voltage) for the CPU
There are droops, and alone by using +5mV positive offset, you reset any preconfigured curves or other board-partner cheating shenanigans, that are there
Some need positive offsets, some need negative offsets

Mostly board specific what works for you the best
Early on i used +60mV added voltage ontop of -30 Allcore CO.
But 1usmus's CTR CO method based upon AMD resources (figured out myself) is a better scaling. Soo i just use 10mv more to flatten out VID droop + loadline , with supplied vcore








Keep in mind, VDROOP you get on little amount cores (less VRM Amperage Strain) vs what you get on an allcore @ high current (a lot of A-Strain)
Then also both loads between high voltage allcore vs low voltage allcore
all of these will have different vdroop behavior ~ up to VRMs capabilities & DrMos balancing.

You'd need to be cautious when you use this behavior to really tune it for all the voltage ranges.
Even when PX boost has no droop, an allcore full throttle load can then have negative effects.

I mostly use it again "for balancing and board tuning" these days
Early on as CurveOptimizer support - but now it's not needed after figuring out how Yuri works


----------



## Veii

PJVol said:


> Boost Override do influence.


Yes sadly 
You are correct. This complicates it a bit without reason








Good to know, i never noticed it ~ ty 


Robostyle said:


> Guys, could somebody help with training settings? TM5 gives me 3 errors in 25 cycles - 4,9,14
> vDIMM 1.42v. Tried 1.38V and 1.4V before - tm5 ended with error 2.
> View attachment 2518323


#4 is a PCB crash, either by overcurrent or by bad RTT values
#2's are fine, you can work them away
#4 are more serious
Also you want to match tRP to tRCDavg
Either drop tRCD_WR to 15, or increase tRP to 17
You should also give 1-4-4-1-6-6 SD,DD's a try at first

Powering issue looks to be it for you
Soo give 30-20-30-20 a try with your current VDIMM
#4 you have to get away first 
Generally #6, #0, #12, #4 are bad and need to be taken away first. It doesn't matter if later more errors appear


----------



## rhhek

My mismatched 48GB RAM kit (4 sticks) with my Ryzen 1600 and Asrock B450m Pro4 (1.40V DRAM limitation by the board)

The motherboard uses a daisy chain topography for the memory slots. I put the 3600 MHz kit in the "slower" slots.

I've been tightening down the timings at 2933 MHz and currently testing 16-17-16-16-26-54 with gear down mode disabled at T1 command rate. Once I finish tightening the primary timings, I'll start on the secondary ones.

Even when I tried loosing timing to something like 18-22-22-22, 3200 MHz isn't stable. 3000 MHz wasn't stable even with the original 16-18-18-36-54 timings. Tcas at 15 crashes and tRCDRD at 16 causes the OS to BSOD but tRCDWR at 16 works fine.

All of the RTT_PARK, RTT_NOM, RTT_WR, CAD_BUS (CLKDrvStr/AddrCmdDrvStr/CsOdtDrvStr/CKEDrvStr), VDDP, CLDO_VDDP, and SOC voltage have been set to default or auto as I'm not sure of what vaules to start with. ProcODT is 53.3 Ohms, which was set by the original XMP timing or by the motherboard when it was training the RAM.

I could use the Dram calculator for the starting point, but I don't trust its calculation when it said that it doesn't support Micron's B-die and it's not designed for two pairs of mismatched RAM.


----------



## byDenoso

Veii said:


> How's actually the progress for you fighting against the latency loss ?


Actually petty bad 
tRC anything lower than 55 just wont post. I suspect of TRDWR...
I cant lower my tRP to 17 because the 1,5v cap of my board, even loosening secundaries (i didnt test with higher tRFC).
I was only able to reduce tRAS to 38 and tRC to 56 (with tRP 18).
I'm thinking in lower my SCL's and adjust my TRDWR/RD timings.


----------



## Veii

byDenoso said:


> Actually petty bad
> tRC anything lower than 55 just wont post. I suspect of TRDWR...
> I cant lower my tRP to 17 because the 1,5v cap of my board, even loosening secundaries (i didnt test with higher tRFC).
> I was only able to reduce tRAS to 38 and tRC to 56 (with tRP 18).
> I'm thinking in lower my SCL's and adjust my TRDWR/RD timings.


Screenshot ?
You shouldn't need anywhere near that voltage
tRRD tWTR bump does nothing ?
tWR bump usually helps with "less" voltage


----------



## byDenoso

Veii said:


> Screenshot ?
> You shouldn't need anywhere near that voltage
> tRRD tWTR bump does nothing ?
> tWR bump usually helps with "less" voltage












I'm using this for now, 1,5v is needed on CL15, but seems that i'll have to go CL16 if i want to lower tRTP, i didnt test with loosening TWR, only tRDD/tWTR


----------



## Veii

byDenoso said:


> View attachment 2518356
> 
> 
> I'm using this for now, 1,5v is needed on CL15, but seems that i'll have to go CL16 if i want to lower tRTP, i didnt test with loosening TWR, only tRDD/tWTR


Is 240ns your tRFC wall ?
You can just run more of everything, more tWR, more tRTP
And then use tRCD 20 + for example 12 tRTP 
Depends, i am not sure what you run

But i see 1.5v on RTT 005, which is quite some dangerous path you take


----------



## byDenoso

Veii said:


> Is 240ns your tRFC wall ?
> You can just run more of everything, more tWR, more tRTP
> And then use tRCD 20 + for example 12 tRTP
> Depends, i am not sure what you run
> 
> But i see 1.5v on RTT 005, which is quite some dangerous path you take













I drop to CL16 until i get tRP17 stable. Now i'm getting error 0 and 4, i'll lower VDIMM and fix my RTT (7 / 0 / 6 is good i think).




Veii said:


> Is 240ns your tRFC wall ?


Actually i'm almost sure than the wall is on 230ns.


----------



## Veii

byDenoso said:


> I drop to CL16 until i get tRP17 stable. Now i'm getting error 0 and 4, i'll lower VDIMM and fix my RTT (7 / 0 / 6 is good i think).


This is not a primaries issue


http://imgur.com/z3wfcBK

 Pasted that way - typical cloudflare photodna nonsense

Mirror move is a transition issue between dimms 
Give tRRD 6-8
tWTR 5-14 a try and report back
Also increase tRDWR to 11 for now


----------



## byDenoso

Now i'm getting these errors, sry taking so long, i was in a "blue screen heaven" (until i adjusted CAD_BUS, RTT's, CLDO_Vddp and VDIMM).


----------



## Veii

byDenoso said:


> View attachment 2518359
> 
> 
> Now i'm getting these errors, sry taking so long, i was in a "blue screen heaven" (until i adjusted CAD_BUS, RTT's, CLDO_Vddp and VDIMM).


Now you actually do have powering issues 
#4
Give a pure 705 a try, else 706 it is


----------



## craxton

Veii said:


> Unless they swapped factory or GLFO has internal production line issues ~ such should not vary thaat much
> WHEA is not an IMC error for sure. A bad IMC will refuse to post or only error #6 & error clearly on y-cruncher FFT


i tried for a while, and lowered the 'overall' WHEA 19s down from 10,000 within 5 hours time to
around 300 or so at 4000/2000, and i actually manage to post and have no crashing issues up-to 1.000 cLDO_VDDP
while im not running this in no way shape or form, it wasnt "better" in countering my WHEA 19 issue at 2000fclk.
thus after a few hours of trying/failing i reverted back to 3800/1900c14-14
(EDIT) performance was ON PAR with what it should be, 
and wasnt causing issues as usual, but the WHEA 19s im more so worried about causing issues.



Veii said:


> Disabling C-State generation, fixes the CPU at P0 powerstate = 3.7 or 3.8Ghz
> Then does PBO boost upwards yet falls back to 3.7Ghz
> This is as so problematic, because 3.7 requires around 1025-1100mV sustained ~ to keep cores alive.


so if core c6 state is on, then thats "GOOD" and what im after, thus making sure "PACKAGE C6 State" is off
in zenstates? pic below is (what is setting at boot) opened hwinfo to show c states being "active"












Veii said:


> You lose at absolute minimum 20W from the powerbudget or 200mV in potential savings (per core so to say)
> You also lose the ability to have dLDO averager function & it won't put cores to hibernation or parking without this functionality


couldnt this "overtime" cause some degradation? i know its not using "max" voltage but still its keeping voltage current
"steady" at all times above the idle state minimum preferred when cores are parked vs unparked?

(btw) most the 5600x shots ive seen seem extremely similar to what scores (with 200mhz oc)
get as mine was, *i dont have any previous screenshots of mine atm but they are back in this thread,
will add it if i manage to find it.


Spoiler



but in the process of packing up for a move to ohio.... tomorrows
the last day in Ky (31 years) hopefully this will introduce better opportunities....


----------



## Veii

craxton said:


> so if core c6 state is on, then thats "GOOD" and what im after, thus making sure "PACKAGE C6 State" is off
> in zenstates? pic below is (what is setting at boot) opened hwinfo to show c states being "active"


Yes


craxton said:


> couldnt this "overtime" cause some degradation? i know its not using "max" voltage but still its keeping voltage current


P0 is binned to be low and constant, same as CTR's p1 was at 1.15v ~ close to nothing can cause a degradation that way


craxton said:


> hopefully this will introduce better opportunities....


I wish you only the best~


----------



## byDenoso

Veii said:


> Now you actually do have powering issues
> #4
> Give a pure 705 a try, else 706 it is



Still having error 2, 6 and 12
Should i use 2T instead?


----------



## byDenoso

Now i'm having some fun...


----------



## Veii

byDenoso said:


> Still having error 2, 6 and 12
> Should i use 2T instead?


Error #2 and #6 mostly relates to "not enough current"
Pure 6 at the start is about 20mV VDIMM missing
#2 is a long balancing and timing fight "something times out according to TM5 descriptons"

#12 and #0 are slightly timeouts, slight powering issues, mostly related to lack of VDIMM

On your point i think you just overvolt it - but i don't know
Haven't seen people struggle with CL15 thaat much, on such low MT/s
Do you remember your PCBs ?
CL16 on 3800 needed 1.36-1.38vDIMM, CL15 around the 1.46 mark
1.5+ is already quite a bit , as people get CL14 to run at 1.48v @ 3800MT/s - well but some also need 1.6v there 

Generally, you only fight now with your powering issues, soo we'll see what can happen
If you don't resolve them, your primaries won't drop magically


byDenoso said:


> Now i'm having some fun...


Fun indeed 
You'll be stuck on this for a bit

Why don't you run 16-20-20-20-40-60 ?
Would be soo much easier & either work away tRCD 20 or up to 3800MT/s
Balancing high tRRD is not easy
5-7-4-12 runs,
5-7-5-14 does
6-8-5-14 also

other combinations need balancing elsewhere
Stay on lower ones till you are sure they are completely fine
Your errors continue to say "there are issues with them"
And your tFAW continues to be bad , even tho i told you to figure out tCCD_L from the bios and use this = tRRD_S * tCCD_L = tFAW

Seeing you can actually post and run this with 1.42v - 1.5v is far too much & you have issues elsewhere. You where overvolting the whole time as it seems
Give more procODT a try. I just now notice you are on Matisse ~ far less cLDO_VDDP , far less VDDG_IOD (wonder if i haven't told you)
And your tRTP or tWR is wrong. If you really use *8 here , then you need to continue this scaling = tRTP 8, 16. Same for tWR, 16,32 and so on
more values work ~ but i have to re'mention it


----------



## byDenoso

Veii said:


> On your point i think you just overvolt it - but i don't know
> Haven't seen people struggle with CL15 thaat much, on such low MT/s
> Do you remember your PCBs ?


Yeap, is a A1 PCB, Hynix DJR




Veii said:


> Generally, you only fight now with your powering issues, soo we'll see what can happen
> If you don't resolve them, your primaries won't drop magically


Got it, i'll work hard on it.




Veii said:


> Why don't you run 16-20-20-20-40-60 ?
> Would be soo much easier & either work away tRCD 20 or up to 3800MT/s
> Balancing high tRRD is not easy


Actually i've tested 16-20-20-40-60 and it worked stable, but i want to continue the jorney to "Find the missing MB/s/latency".




Veii said:


> And your tFAW continues to be bad , even tho i told you to figure out tCCD_L from the bios and use this = tRRD_S * tCCD_L = tFAW


my tCCD_L is 5ns (7 clock i guess?) so tFAW would be 7xRdds?




Veii said:


> Seeing you can actually post and run this with 1.42v - 1.5v is far too much & you have issues elsewhere. You where overvolting the whole time as it seems
> Give more procODT a try. I just now notice you are on Matisse ~ far less cLDO_VDDP , far less VDDG_IOD (wonder if i haven't told you)
> And your tRTP or tWR is wrong. If you really use *8 here , then you need to continue this scaling = tRTP 8, 16. Same for tWR, 16,32 and so on
> more values work ~ but i have to re'mention it


I can lower CLDO_VDDP until 820mv, but i can't lower SOC and VDDG_IOD voltages lower than that because my Matisse just randomly restarts.
And worst of all, My CPU cant FCLK 1900, i've tried of several methods with no sucess.


----------



## Veii

byDenoso said:


> my tCCD_L is 5ns (7 clock i guess?) so tFAW would be 7xRdds?


Probably even gigabyte has an SPD-Z tool (named differently) that deciphers Intel XMP ~ inside the bios
It likely is different each frequency, but you can use it - yes
Either 4* or tCCD_L *


byDenoso said:


> I can lower CLDO_VDDP until 820mv, but i can't lower SOC and VDDG_IOD voltages lower than that because my Matisse just randomly restarts.


Stay with 900mV then, even DRAM calculator mentioned this
More is not needed. Early on people could drop it to 700mV.
VDDG IOD and SOC you'll figure out together with y-cruncher
OC'ing T-Force 4133 cl18 bottom part of the post, but i think you've read it already
50mV stepping or 75mV , but 75mV doesn't always work

2T will need more ClkDrvStr, and 1T will also
If you want to run low CAD_BUS, you need a strong procODT
I think the opposite way is better & generates less heat


----------



## byDenoso

Veii said:


> Probably even gigabyte has an SPD-Z tool (named differently) that deciphers Intel XMP ~ inside the bios
> It likely is different each frequency, but you can use it - yes
> Either 4* or tCCD_L *


Is 7 clocks, i used the ROG program to see it.
So will be 7*RDDS




Veii said:


> Stay with 900mV then, even DRAM calculator mentioned this
> More is not needed. Early on people could drop it to 700mV.
> VDDG IOD and SOC you'll figure out together with y-cruncher
> OC'ing T-Force 4133 cl18 bottom part of the post, but i think you've read it already
> 50mV stepping or 75mV , but 75mV doesn't always work


Apparently increase tRFC had decreased the amount of errors, just with error 4 for now..


----------



## gled_fr

gled_fr said:


> And the result, 60 cycles, one single error 4 on the 58th cycle :/ but at least no freeze !
> View attachment 2518242


Again gonna need your help guys.

So starting at the above settings ( one single error 4 at 58 cycles ), I tried to correct that by testing one by one:

ClkDrvStr at 30 instead of 40 => almost immediate error 8 ( in the first 10mn ).
Vdimm at 1.445 instead of 1.45 => error 10 after around 30 cycles.
RttNom /7 instead of /6 => error 1 after around 10 cycles.
RttPark /4 instead of /3 => error 12 after around 30 cycles, then error 14 on cycle 42.

Lowest latency observed on those tests was 54.6ns, most runs were between 54.7 and 55.2ns

I am currently trying with ProcODT 36.9 instead of 34.3, but kinda at a loss on what to do next.

It's like a never ending story, it seems to be almost stable though, so I am sure I am just missing that little thing that will push it stable ! Any idea what could help ?


----------



## Veii

gled_fr said:


> It's like a never ending story, it seems to be almost stable though, so I am sure I am just missing that little thing that will push it stable ! Any idea what could help ?


Probably an air conditioner, if the room keeps getting warmer and warmer on such long tests
or an UPS if house current is the issue


----------



## gled_fr

Veii said:


> Probably an air conditioner, if the room keeps getting warmer and warmer on such long tests
> or an UPS if house current is the issue


Temperature is pretty good, stable around 24-25C during the day and during the night tests it's actually going down.
Ram goes around 48-50C during the tests pretty fast ( around 10mn ) but not higher. Should I think of adding a waterblock to put the ram in my loop ?

Computer is already on a UPS 

It seems like there's something I am missing, like I am changing one thing at a time but maybe need to change a couple at the same time to reach stable ?

At that point, would you consider the single error 4 to not be an issue, knowing it appeared at 58 cycles ?

Or go with "Vdimm at 1.445 instead of 1.45 => error 10 after around 30 cycles" => change tWR to 10 instead of 12 after that since error 10 with just vdimm ?


----------



## Veii

gled_fr said:


> At that point, would you consider the single error 4 to not be an issue, knowing it appeared at 58 cycles ?
> 
> Or go with "Vdimm at 1.445 instead of 1.45


Dropping voltage doesn't seem to help you
it's too far into the test. It can be anything external at this point too
Like the CPU loosing stability at an hours long allcore test


----------



## XPEHOPE3

Veii said:


> Usually no, tCKE in combination with RTT_WR makes issues
> Same as CAD_BUS TIMINGs do ~ but they coexist together with a lot of work
> 
> RTT_WR changes NOM and PARK behaviour once you enable or change it's strengthness
> I do have a feeling /2 requires high VDIMM-IN to even function, but /3 has to run close to always
> Using RTT_WR generally has a RTT_PARK range. Barely any influence to RTT_NOM
> If WR trows errors ~ it's because WR keeps autocorrecting and something bothers it. Be it too low ClkDrvStr , tCKE usage or SETUP Times usage
> If it fully refuses to post - either PARK is too strong , or non existent
> I'd need an example of what doesn't work for you


What's the difference between tCKE 0 and tCKE 1? Do both qualify as "tCKE not used"? For pretty much anything above XMP my board sets tCKE to 1 if on Auto (meaning my whole progress was based on this setting).


----------



## Veii

XPEHOPE3 said:


> What's the difference between tCKE 0 and tCKE 1? Do both qualify as "tCKE not used"? For pretty much anything above XMP my board sets tCKE to 1 if on Auto (meaning my whole progress was based on this setting).


I'm sorry, I don't know.
Zero should not be used at all - because it can not be defined as such
I don't think it can even in HEX
tCKE on 1 is always on, while i phrased it wrongly ~ thank you @jomama22
tCKE max should be the opposite, yet i'm not sure how "always sleeping" can work while memory has to be always active.
But maybe it means "all cells except X are sleeping" ~ i am honestly not sure

It was a mystery that tCKE started to get used without running PD-Mode on Vermeer
And then also seeing/learning about Aggressive Powerdown and Normal Powerdown , which this tCKE value changes
Still a too foreign topic with lack of information. Surely the Chiphell community knows far more
At least the range is kind of figured out


----------



## Kristoast

Veii said:


> You won't like this reponse
> cLDO_VDDP is far to high
> Match it as absolute minimum with VDDG CCD, which if really stable on stock ~ looks fine at 950mV
> It is influencing at what MCLK you can post but lower is always better ~ as it allows for lower procODT to function (if remain powering is correct)


I'll take any info I can get so I appreciate the response! 
In the time since I initially posted I have probably bookmarked about 5 of your other posts on this thread. Lots of great information, but sometimes a bit jarring to put it all together. With what I was able to find, I was able to get these settings to run through y-cruncher, karhu, tm5, and hci memtest without errors other than WHEA 19 popping up about twice a minute since boot. I wasn't able to find a clear answer on how to alleviate the WHEA errors other than a few discussions on this thread a few months back that didn't really have a resolution other than to drop down to 3733/1866 (which worked for me). Docp is off and most timings except the main 4, tcwl, and procODT are on auto.


Spoiler

















Veii said:


> Is this 4x8GB Micron Rev.E ?
> Or maybe Hynix CJR ?


Should be 4x8GB Samsung B-die


Spoiler

















> You want to push ClkDrvStr to something along the lines of 30-20-30-20 for the start
> Maybe 40-20-30-24 if the board struggles with 4 dimms
> 
> You also want to work GDM away and start your foundation as GMD off 2T ~ yes it's faster , and saves time for you
> Give SD,DD's a try as 1-4-4-1-6-6 (tRDRD = 4-4)
> In the ASUS Bios go to Tools - ASUS SPD-Z , disable first both armory crates and other asus spyware (if something more is left) & read out the XMP profiles
> The Bios will generate tCCD_L value for you. Remember it , it is important
> Check all 4 dimms if they have the same tCCD_L value
> If it's 6, then use tRRD_S * tCCDL (6) = 42 for you.
> If it's 7 , then you likely are looking at 49 as a value
> 
> Let us know which ICs these are , then we can talk about a baseline
> For tRAS as a baseline you want tRCD*2 + tCCD_L . This will always work, doesn't matter how bad the kit is.
> Then tRC = tRP + tRAS (which will also always work if tRAS is correct to begin with)


I'll try to mess around with some of these tonight. Per my above zentimings, I did manage to get GDM off 2T.
Getting rid of the extra ASUS bloatware was one of the first things I did on my new build! 
tCCD_L was blank under XMP, but was 6 under JEDEC. Sorry for the confusion on my part, but what timing is tRRD_S * tRRD_L plugged in for?

Thanks for taking the time to look at this! It is much appreciated! I try to learn what I can from searching this forum, but it's a lot info to take in and comprehend.

Edit: Read another post and saw tRRDS * tRRDL should be the value for tFAW. Messed around with some setting and am currently running some stability tests for these timings:


Spoiler


----------



## Veii

Kristoast said:


> Should be 4x8GB Samsung B-die


Very likely C-Die
Please doublechec








^ source HardwareLuxx
ending on C = C-Die


----------



## Kristoast

Veii said:


> Very likely C-Die
> Please doublechec
> View attachment 2518400
> 
> ^ source HardwareLuxx
> ending on C = C-Die


They are all labeled as ver 4.31(Corsair). It was actually one of the first things I checked when I received them.


----------



## craxton

Kristoast said:


> They are all labeled as ver 4.31(Corsair). It was actually one of the first things I checked when I received them.


for those to be B-die they act just like the C-die set i had. which
were HORRIBLE to overclock or even use XMP on AMD systems (built for AMD)
turned out they were C-die which for a long time i had thought they were B-die
for the timings your trying to run on those id have to go with what Veii is stating.
awful loose to be B-die. if those are indeed B-die you should have no issues running c16-16
or even with a little work something like this
(3200c14-14 tforce dark pro) see if you can do this set here tho (not c14-14) look at the second picture...
if those cant do c16-16 (4x8 set so you shouldn have issues) might need your own proc/RTT/Drv strength's etc

(EDIT) @Veii looks like those are indeed B-die says B-die finder...


----------



## gled_fr

Finally a stable run !

So either 36.9 ProcODT did the trick, or like @Veii said previous settings were already OK and something external triggered error 4

Now to work my way to CL14 and try to get lower latency !

it's good to see some progress


----------



## craxton

i think i have a problem....(missing two {2400G-another 3600XT} which were sold...
didnt realize i had these in the closet....no wonder ive been broke since i started PC gaming/tinkering....
(clarify-knew i had the 5600x but thought i sold the 3600xt and gave the 1600af to my uncle)


Spoiler



(dont mind the shoes ETC got most of everything packed and ready to go for the morning.)


----------



## craxton

Ok, so here lately ive been "gaming" more than what i was before, 
and well me hitting 70c in DaysGone (cracked but regardless)
ive been wondering *** is causing this. as when i close the game im still hitting 65-higher
while with just chrome open. i thought "randomly" to open zenstates and what i found was x10 scaler..
which i have MANUALLY set inside bios to x2 (this happened on verified bios not just the modded one too)
so i set it back to x2 with zenstates (reason its strange is bc i set EDC/TDC/PPT DOWN tdc as low as 48, EDC as low as 80
and STILL (before seeing the x10 scaler) i was STILL pinging out 70c in game and 65+ at idle....
has ANYONE else had this happen? or have they had a "high ass temp" that they know should NOT be the case?
i can run dam near any game without issue but this x10 scaler "bug/issue" im getting is starting to make me wonder how this
is happening....


----------



## Audioboxer

lol, my bad luck of the past week goes from annoying (having to return memory to Amazon for refund) to worse. Decided to give my loop early spring cleaning on the basis of reseating my CPU in case it was causing any issues with memory. All seemed to go well draining, cleaning, repasting and then putting back together. Usual leak tests done, no leaks.

While I booted up and posted I was having terrible issues getting my commander pro to be recognised in ICUE and Windows kept making the sound as if USB was being plugged/unplugged. Whilst trying to troubleshoot this the PC just turned off.

Then it seemed absolutely no power was going to it. Great, thought the power supply had blown. But I tested it with the jig that allows it, fans and anything directly connected to the power supply to power up (commander pro clearly working as fans and everything else run through this and it was powering).

So I took memory out, CPU out and graphics one by one trying to see if power would come back through the motherboard. Nothing.

Took the motherboard out of the case to test it suspended safely on its own, nothing. Still dead. What I have noticed is on the back down the bottom centrally if my power supply is connected and turned on it heats up ridiculously within seconds. To the point it'll get too hot to touch.

No idea what has happened, seems like a short-circuit of some sorts or something else. No evidence of water or water damage.

ASUS customer support so far have been absolutely dreadful. You spend all your time telling them what you've done to begin with, they respond with a generic have you done this, when you have. Now begins my 5th different agent who keep coming back asking stupid things like have you updated the BIOS when it appears your mobo is dead. If I finally get this to RMA (it's under warranty) goodness knows what to expect.

So on that note if you've got to the end of this post I'm considering buying an Aorus X570 master. If Asus take this back and repair it, great, I'll just sell it. Seems like it can be like 4-6 weeks or longer if Asus RMA something for repair.

Is the Gigabyte a good shout?



Robostyle said:


> That's what auto set me to - 43.6, 24/24/24/24.
> HCI Memtest is 2000% stable though.
> Couldn't stabilize tRCDRD at 16, no matter what voltage I threw on it
> 
> 
> Spoiler: HCI
> 
> 
> 
> 
> View attachment 2518331
> 
> 
> 
> Does it mean TM5 is more "robust"?
> 
> P.S. Made my assumptions back from my intel tests
> 
> 
> Spoiler: Gskill
> 
> 
> 
> 
> View attachment 2518330
> 
> 
> 
> 
> That is vDIMM 1.425.


Yeah TM5 and y-cruncher seem to be the best ways to "punish" memory to make sure it is truly stable. Even then some TM5 profiles seem to push memory a bit more and/or can find out instability better than others.

1usmusv3 and anta777 seem to be the most recommended.

If you're not passing them then IMO you cannot call yourself stable even if you can bench and play games for weeks with no crashes.


----------



## PJVol

Veii said:


> inspect more of our brolken dual ccd units


Curios what you meant by "broken" ))
BTW talked to two "dual-CCD" 5600Х owners on a local forum. Both have no issues running 2000+ FCLK, no #19's, but supposedly have lower SIDD cores. One specimen can easily handle < -10 CO magnitudes on two best cores, that however reduces its SC performance noticeably.


----------



## Audioboxer

Okay, I'm actually having a look at the B550 boards over X570. I only run one 4.0 NVMe 2TB drive and the only other thing I'd lose is my Lian Li front USB C connector.

But according to the list here the VRMs on the B550 Master may even outperform those on the X570 Master Motherboard VRM Tier List v2 (currently AMD only)

For CPU/RAM overclocking is the B550 Master worth a look?


----------



## mongoled

Audioboxer said:


> lol, my bad luck of the past week goes from annoying (having to return memory to Amazon for refund) to worse. Decided to give my loop early spring cleaning on the basis of reseating my CPU in case it was causing any issues with memory. All seemed to go well draining, cleaning, repasting and then putting back together. Usual leak tests done, no leaks.
> 
> While I booted up and posted I was having terrible issues getting my commander pro to be recognised in ICUE and Windows kept making the sound as if USB was being plugged/unplugged. Whilst trying to troubleshoot this the PC just turned off.
> 
> Then it seemed absolutely no power was going to it. Great, thought the power supply had blown. But I tested it with the jig that allows it, fans and anything directly connected to the power supply to power up (commander pro clearly working as fans and everything else run through this and it was powering).
> 
> So I took memory out, CPU out and graphics one by one trying to see if power would come back through the motherboard. Nothing.
> 
> Took the motherboard out of the case to test it suspended safely on its own, nothing. Still dead. What I have noticed is on the back down the bottom centrally if my power supply is connected and turned on it heats up ridiculously within seconds. To the point it'll get too hot to touch.
> 
> No idea what has happened, seems like a short-circuit of some sorts or something else. No evidence of water or water damage.
> 
> ASUS customer support so far have been absolutely dreadful. You spend all your time telling them what you've done to begin with, they respond with a generic have you done this, when you have. Now begins my 5th different agent who keep coming back asking stupid things like have you updated the BIOS when it appears your mobo is dead. If I finally get this to RMA (it's under warranty) goodness knows what to expect.
> 
> So on that note if you've got to the end of this post I'm considering buying an Aorus X570 master. If Asus take this back and repair it, great, I'll just sell it. Seems like it can be like 4-6 weeks or longer if Asus RMA something for repair.
> 
> Is the Gigabyte a good shout?
> 
> 
> 
> Yeah TM5 and y-cruncher seem to be the best ways to "punish" memory to make sure it is truly stable. Even then some TM5 profiles seem to push memory a bit more and/or can find out instability better than others.
> 
> 1usmusv3 and anta777 seem to be the most recommended.
> 
> If you're not passing them then IMO you cannot call yourself stable even if you can bench and play games for weeks with no crashes.


Thats bad luck man.

So its looking likely that the motherboard was the issue all along.

Hopefully you wont have too much downtime.

Ive only used MSI the last few years so dont have any personal experience with other vendors, though I do keep reading that Gigabyte are not really up to scratch as they were in the past ...


----------



## Mach3.2

Basically running the same set of primaries I ran on 1800 IF, but I loosen some timings in the tCL 14 screenshot to the timings in the tCL 15 screenshot since the tCL 14 set BSOD'd on me. The loosening of some timings didn't result in increased latency, and the tCL 14 timings seem to have more test to test variances between 6 tests too. The tCL14 timing ended in a BSOD somewhere after 1 or 2 hour of TM5 default @1usmus test. I went out to run some errants so I didn't know if there's any error generated in TM5 while I'm away.

tCL 14 AIDA Memory bandwidth test

Read (MB/s)​Write (MB/s)​Copy (MB/s)​Latency (ns)​55972​55869​51600​57.3​55869​55943​51616​57.0​55955​55934​51655​57.1​55959​55925​51577​57.0​55976​55930​51609​57.1​55937​55925​51604​56.9​

tCL 15 AIDA Memory bandwidth test

Read (MB/s)​Write (MB/s)​Copy (MB/s)​Latency (ns)​55978​55792​51473​56.9​55952​55768​51451​56.9​55978​55756​51453​56.8​55953​55771​51459​57.0​55980​55759​51479​57.0​55990​55754​51408​57.0​

@Veii Could the CPU be autcorrecting the RAM when running the tCL 14 set of timings?


----------



## Audioboxer

mongoled said:


> Thats bad luck man.
> 
> So its looking likely that the motherboard was the issue all along.
> 
> Hopefully you wont have too much downtime.
> 
> Ive only used MSI the last few years so dont have any personal experience with other vendors, though I do keep reading that Gigabyte are not really up to scratch as they were in the past ...


Seems to be, one thing I've noticed when I was trying to test it on a quickly put together "test bench", more like platform lol, is the back of the board getting to untouchable temps very quickly after the power supply is turned on. Something has clearly gone wrong.

Think I'm going to pickup a B550 Master, they're going fairly cheap now. That or the X570 Tomahawk. I'll see what retailer says tomorrow about the Strix. Fingers crossed they just refund but given its 9 months on it'll likely be the repair avenue.


----------



## Kristoast

craxton said:


> for those to be B-die they act just like the C-die set i had. which
> were HORRIBLE to overclock or even use XMP on AMD systems (built for AMD)
> turned out they were C-die which for a long time i had thought they were B-die
> for the timings your trying to run on those id have to go with what Veii is stating.
> awful loose to be B-die. if those are indeed B-die you should have no issues running c16-16
> or even with a little work something like this
> (3200c14-14 tforce dark pro) see if you can do this set here tho (not c14-14) look at the second picture...
> if those cant do c16-16 (4x8 set so you shouldn have issues) might need your own proc/RTT/Drv strength's etc
> 
> (EDIT) @Veii looks like those are indeed B-die says B-die finder...
> View attachment 2518407
> 
> View attachment 2518405
> 
> View attachment 2518404


Well I'll be! The CL16 timings you posted were the right ones to finally get me into 3800/1900 without constant WHEA 19 errors. I'll run it through TM5, Karhu, and some others while I'm working today to make sure it really is good. And yeah, I did check for this SKU on bdie finder before I bought them as well. I knew I'd probably be sacrificing some sort of performance by sticking with the Vengeance Pro RGBs, but I at least wanted to make sure they were b-dies.


Spoiler















To be fair, I'm not sure that I like that I don't know exactly which settings I changed that allowed it to work correctly at 3800, but it's still a leap in the right direction.


----------



## rhhek

Where can I find information about manually setting the RTT_PARK, RTT_NOM, RTT_WR, CAD_BUS (CLKDrvStr/AddrCmdDrvStr/CsOdtDrvStr/CKEDrvStr), VDDP, CLDO_VDDP, ProcODT and SOC voltage values?

I think if I could find a stable setting, I could try for CL15 with 2933 MHz or go beyond the 2933 MHz that I'm stuck at no matter what timing values I try.

I can't use the Dram calculator as a starting point because of I'm using two different RAM kits (3200 MHz CL16 Samsung B-die and 3600 MHz CL16 Micron B-die) on an Asrock B450m Pro4 board that uses a daisy chain topography. The Ryzen 1600's notoriously weak IMC certainly doesn't help either.


----------



## XPEHOPE3

Mach3.2 said:


> @Veii Could the CPU be autcorrecting the RAM when running the tCL 14 set of timings?


There's an easier explanation: screenshot with tCL 14 shows tPHYRDL 28, while for tCL15 it's 26. Don't know what it was on the other channel (on B2 stick). But 28 is slower than 26.


----------



## gled_fr

Audioboxer said:


> So on that note if you've got to the end of this post I'm considering buying an Aorus X570 master. If Asus take this back and repair it, great, I'll just sell it. Seems like it can be like 4-6 weeks or longer if Asus RMA something for repair.
> 
> Is the Gigabyte a good shout?


Oh man :/ at least that probably explains the issue you had no POSTing with Park < /1 :/

I had issues with the aorus pro wifi mini itx, so far the asus x570-i has been better ( even though I mostly migrated for the temp sensor header on the board, since I use the water temp for my fans curve ).

PBO on the gigabyte, results were less than stellar, about 2k points less than the asus. It took a long time also for the aorus to get the AGESA updates too compared to the Asus.

I was able though to boot at IF 2000 on the Aorus, which I can't yet with the asus. 

It's also itx boards, so don't know if it applies to full size ones ?


----------



## sendap

Veii said:


> 4.85 held should be 10.4ns not 10.8 ~ or 10.5ns on an allcore (PBO is faster) ~ meaning your cores do not perform equally or EDC limiter throttles too strong
> (memOC need a slight EDC lift)


could it be that AIDA uses just core 0 during the latency test and you are just unlucky when this core is on of the weakest on on your CPU?


----------



## Audioboxer

gled_fr said:


> Oh man :/ at least that probably explains the issue you had no POSTing with Park < /1 :/
> 
> I had issues with the aorus pro wifi mini itx, so far the asus x570-i has been better ( even though I mostly migrated for the temp sensor header on the board, since I use the water temp for my fans curve ).
> 
> PBO on the gigabyte, results were less than stellar, about 2k points less than the asus. It took a long time also for the aorus to get the AGESA updates too compared to the Asus.
> 
> I was able though to boot at IF 2000 on the Aorus, which I can't yet with the asus.
> 
> It's also itx boards, so don't know if it applies to full size ones ?


Funnily enough right now ASUS is lagging way behind with their X570 boards lol. Still stuck on Patch A. Even the B550 Master has had Patch B for 10 days now.

There is a lot of horror stories around Gigabyte and BIOS issues, then the revisions they needed for the X570 Aorus Master to fix a few things. But it seems at least in terms of BIOS rollouts they've improved a lot in the last 6 months or so.

I do see quite a lot of good OCing levels hit with the B550 boards. Some of the X570 top end boards too, to be fair. Seems like any option will likely do me better than the Strix F Gaming. Crossing my fingers I can just push for a refund tomorrow or even a gift card. Retailer is now OOS on the Strix F Gaming on their site and for in-store pickup anyway. So it would have to be a repair, or off to a repair centre for a refurb.

The Strix F Gaming seemed to treat me OK with PBO, can't lie there, but memory has been a bit of a joke and I presume the more instability I was finding even with settings that seemed previously stable were due to the board deteriorating. Still be interested to know what has gone wrong. The board is completely spotless, I can't see any obvious signs of burning or corrosion.

I'm going to guess some sort of power failure, or failure to transfer or handle power properly, resulting in some inevitable "bang", board dead lol. Even the RGB is dead.

*edit:* My Strix would boot 2000 FCLK, but anything 1933~2000 was WHEA error central. 2000 especially. Only 1900 had zero WHEA errors.


----------



## Robostyle

Veii said:


> #4 is a PCB crash, either by overcurrent or by bad RTT values
> #2's are fine, you can work them away
> #4 are more serious
> Also you want to match tRP to tRCDavg
> Either drop tRCD_WR to 15, or increase tRP to 17
> You should also give 1-4-4-1-6-6 SD,DD's a try at first
> 
> Powering issue looks to be it for you
> Soo give 30-20-30-20 a try with your current VDIMM
> #4 you have to get away first
> Generally #6, #0, #12, #4 are bad and need to be taken away first. It doesn't matter if later more errors appear


I give up. The worst bin one can ever get I guess:








vDIMM 1.45v.
I've tried different set-ups, from RCDWR 15 to RCDRD/RP 17, tRFC >320.

Or couldit be so, that Ive corrupted win so bad with unstable conf stresstesting, that tm5 is no more valid until I reinstall the os?


----------



## Mach3.2

XPEHOPE3 said:


> There's an easier explanation: screenshot with tCL 14 shows tPHYRDL 28, while for tCL15 it's 26. Don't know what it was on the other channel (on B2 stick). But 28 is slower than 26.


The tPHYRDL for the B2 stick in both screenshots are 26. I wasn't expecting 2 ticks of tPHYRDL to be that powerful.


----------



## gled_fr

booting at 1933 IF CL15 no problem. WHEA 19 all over the place... Gonna try playing with ccd / iod to stabilize that ...


----------



## Ethelneth

Mach3.2 said:


> View attachment 2518436
> View attachment 2518437
> 
> 
> Basically running the same set of primaries I ran on 1800 IF, but I loosen some timings in the tCL 14 screenshot to the timings in the tCL 15 screenshot since the tCL 14 set BSOD'd on me. The loosening of some timings didn't result in increased latency, and the tCL 14 timings seem to have more test to test variances between 6 tests too. The tCL14 timing ended in a BSOD somewhere after 1 or 2 hour of TM5 default @1usmus test. I went out to run some errants so I didn't know if there's any error generated in TM5 while I'm away.
> 
> tCL 14 AIDA Memory bandwidth test
> 
> Read (MB/s)​Write (MB/s)​Copy (MB/s)​Latency (ns)​55972​55869​51600​57.3​55869​55943​51616​57.0​55955​55934​51655​57.1​55959​55925​51577​57.0​55976​55930​51609​57.1​55937​55925​51604​56.9​
> 
> tCL 15 AIDA Memory bandwidth test
> 
> Read (MB/s)​Write (MB/s)​Copy (MB/s)​Latency (ns)​55978​55792​51473​56.9​55952​55768​51451​56.9​55978​55756​51453​56.8​55953​55771​51459​57.0​55980​55759​51479​57.0​55990​55754​51408​57.0​
> 
> @Veii Could the CPU be autcorrecting the RAM when running the tCL 14 set of timings?


Did you try if you can run tRCDRD 16 at 1800?


----------



## Audioboxer

I've seen the B550 UNIFY-X cuts two of the DIMMS, that should in theory make it even better for overclocking memory on 2x16GB, right?


----------



## craxton

gled_fr said:


> booting at 1933 IF CL15 no problem. WHEA 19 all over the place... Gonna try playing with ccd / iod to stabilize that ...


cLDO_VDDP might be the best bet to tinker with if your stable on IOD/CCD. 



Kristoast said:


> Well I'll be! The CL16 timings you posted were the right ones to finally get me into 3800/1900 without constant WHEA 19 errors.


What V-Dimm you running to get that stable? Spoiler-those same timings run 4000/2000 fclk on 5000 chips. If your chip posts. (My 5800x has whea 19s but runs fine, my 5600x has no issues running it at all but is horrible at core overclocking) might be user error. 



Kristoast said:


> To be fair, I'm not sure that I like that I don't know exactly which settings I changed that allowed it to work correctly at 3800, but it's still a leap in the right direction.


This entire thread back to page 350 will fill you full and burst with stuff you can learn and test.


----------



## Mach3.2

Ethelneth said:


> Did you try if you can run tRCDRD 16 at 1800?


I believe there is a tRCDRD hard wall for Micron Rev. B, I briefly tried 16 but it was very unstable so I went with 17.


----------



## spajdr

Yep, agree with @Mach3.2 tRCDRD at 16 is a big NO at 1800.


----------



## Ethelneth

Mach3.2 said:


> I believe there is a tRCDRD hard wall for Micron Rev. B, I briefly tried 16 but it was very unstable so I went with 17.





spajdr said:


> Yep, agree with @Mach3.2 tRCDRD at 16 is a big NO at 1800.


16-16-16-16-32 looks probably stable for me at 1800 (see [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread) 1866 was very unstable and 1900 unbootable however.


----------



## spajdr

@Ethelneth ahh well I have BL8G30C15U4R.M8FE kits and it's a no go


----------



## Kristoast

craxton said:


> What V-Dimm you running to get that stable? Spoiler-those same timings run 4000/2000 fclk on 5000 chips. If your chip posts. (My 5800x has whea 19s but runs fine, my 5600x has no issues running it at all but is horrible at core overclocking) might be user error.


V-Dimm is at 1.40v. Just tried switching to 3866 and 4000, but I couldn't post on either. Was able to run 5 iterations y-cruncher, karhu up to 6500%, tm5 without any errors on 3800/1900. I'd love to be able to push it up to 4000/2000, but not sure what the next steps would be (I am content at 3800, but might mess around to see if I can tighten the timings anymore).



craxton said:


> This entire thread back to page 350 will fill you full and burst with stuff you can learn and test.


Yep, I've been jumping around it all week. It's A LOT of info and trying to piece it together has been jarring to say the least. I think the biggest thing holding me back from any breakthroughs is not wanting to mess with any of the 'power' settings too much until I fully understand them since I don't want to accidentally fry anything.


----------



## Mach3.2

Ethelneth said:


> 16-16-16-16-32 looks probably stable for me at 1800 (see [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread) 1866 was very unstable and 1900 unbootable however.


Maybe I'll try giving flat 16 a go on another day, when i tired running tRCD on 16 my tCL was running on 15.


On another topic,








A single error 12 popped while the 3rd cycle was running, and a single Bus/Interconnect WHEA popped 2 minutes into cycle 18.

I'm thinking I should add an extra stepping of voltage to VDDG IOD, any ideas?

Current voltage settings in BIOS:
vSOC: 1.140V
CLDP VDDP: 0.9V
VDDG CCD: 0.94V
VDDG IOD: 1.02V

Edit: Increased both VDDG CCD and VDDG IOD by a tick to 0.98V and 1.06V, passed 25 cycles of default 1usmus_v3 with no errors.


----------



## Robostyle

BTW, my sticks dont have 042 code - what does that suppose to mean?


Spoiler: gskill


----------



## Akex

Veii said:


> tRAS is "low" for you
> either too low or too high
> Either tRCD+tRTP or tRCDavg*2 or tRCDavg+tBURST


When you say tRCD, you mean tRCDRD ? How do you find the tRCDavg and tBURST?



Veii said:


> Also on both sets tRFC is too low
> It get's postponed
> Either you run it as 215, with tWR 10 , tRTP 5 (soo tRAS then 16+5 = 21)
> Or you run 258 , with either tRP 6 or 8, soo tWR 12 or 16


We agree that we're speaking about tRTP 6 or 8 and not tRP?

Thank you.


----------



## PJVol

Veii said:


> Either tRCD+tRTP or tRCDavg*2


My apologies if this has already been discussed here, but can you, or anyone else in the know, confirm that the tRCDWR is actually being used by the Zen2/3 memory controller?
Anybody got an idea?


----------



## hsn

I put fan on my ram, and this is cool (i think).


----------



## Audioboxer

Small win, got a full refund for my Strix F Gaming because its not in stock any more with retailer. £270 back. Got a B550 Unify X coming today I spent £160 on.

Net win, getting a board that should be better for overclocking for much less than the retail RRP of the Strix last year.


----------



## Ethelneth

Mach3.2 said:


> Maybe I'll try giving flat 16 a go on another day, when i tired running tRCD on 16 my tCL was running on 15.
> 
> 
> On another topic,
> View attachment 2518475
> 
> A single error 12 popped while the 3rd cycle was running, and a single Bus/Interconnect WHEA popped 2 minutes into cycle 18.
> 
> I'm thinking I should add an extra stepping of voltage to VDDG IOD, any ideas?
> 
> Current voltage settings in BIOS:
> vSOC: 1.140V
> CLDP VDDP: 0.9V
> VDDG CCD: 0.94V
> VDDG IOD: 1.02V
> 
> Edit: Increased both VDDG CCD and VDDG IOD by a tick to 0.98V and 1.06V, passed 25 cycles of default 1usmus_v3 with no errors.


Are your memory temps fine? I started getting random TM5 errors and whea 19 warnings on a previously stable setup when ambient temperature increased and the dimms under stress started exceeding 60°C


----------



## XPEHOPE3

XPEHOPE3 said:


> Also I almost finished TestMem5 automation script to collect per-cycle screenshots with information if there were any errors. It's possible to even get all the errors in format "cycle: list of errors", but that requires further work, and might not be needed.
> Just teasing 😎





Veii said:


> A screenshot tool that barely uses RAM would be really helpful for it.
> It's beyond me why TM5 never get's updated to log better before a BSOD or reboot corrupts the log.txt ~ but that's the dev's problem


TestMem5 *automation *script v1.0.0 is released 😇


----------



## byDenoso

After 2 days trying to lower my tRP to 17 and failing (i've worked around with all secondaries and terciaries, my pc just frooze), i've followed @Veii suggestions and i give 16-20-20-40-60 a try, it passed, and then i tried 15-20-20-40-60.
I've forgot to screenshot the TM5 results but here is my new stable 24/7 settings.


----------



## craxton

Audioboxer said:


> Got a B550 Unify X coming today I spent £160 on.


where in the hell did you find one of those at????
all see are at mininum 250/350 USD


----------



## Audioboxer

craxton said:


> where in the hell did you find one of those at????
> all see are at mininum 250/350 USD


Amazon Warehouse https://www.amazon.co.uk/MSI-B550-U...1&keywords=B550+Unify+X&qid=1627152046&sr=8-2

£180 for new, warehouse had various offers. I think I might have grabbed the last Warehouse offer lol.

Took a gamble but this mobo looks totally unused. Nothing opened and even box was sealed. Going to set it up tomorrow.


----------



## Mach3.2

Ethelneth said:


> Are your memory temps fine? I started getting random TM5 errors and whea 19 warnings on a previously stable setup when ambient temperature increased and the dimms under stress started exceeding 60°C


Shooting in the blind here, the non RBG sticks of Crucial Ballistix does not have temp sensors.


----------



## Asutz

Hi,

after months of testing.
still not 100% clear sound, popups, crackling noises etc. issues since b450 board with r3 1200 and 2700x and now with the 5600x
tried different soc voltages, ccd / iod / vddp / vddg and so one

ch7 bios not liking both manuell vddg voltages.

suggestions for timing and voltages that can help or how are the chances to get rid of sound popups with another board ?
thanks in advance


----------



## spajdr

@Asutz I'm not sure if it will help you, but I have it set like this.








No WHEA, no sound/USB issues.


----------



## craxton

Audioboxer said:


> Took a gamble but this mobo looks totally unused


thats exactly how i got my B550 gaming edge wifi board...which said
USED-GOOD but when it came in the only thing opened was the box, the
board package, wifi antennas, pamplet etc all were unopened.
(same thing with my old 1660 super evga version (un-opened package but the box
was opened) everything else still there (B4 the great PC scurge) is the US dollar that
much different than that in EUROs atm??? 180 euros vs 250/300 usd is quite the difference....
(EDIT) was higher this morning when i looked...
(another edit) found the NON X version for around the price you mentioned in US currency 
but still its the unify not the unify X








HOLY **** i guess the US dollar is worthless rightnow....


----------



## byDenoso

@Veii Finally some progress, after 2 days trying (and failing), i managed to get 4 cycles stable, looks like my board was not 100% stable at 1866FCLK (actually it were, but i had to give a large bump on SOC and VDDG_IOD voltages, it probably made tRP17 impossible), so i lowered to 1833, loosened secondaries and tweaked SOC and VDDG voltages and now it passes until 4 cycles (still testing).


----------



## byDenoso

ALMOST DONE!
Now is the hard part...


----------



## Audioboxer

Can confirm this morning it was my Strix F Gaming that must have "blown up". B550 Unify X turning on fine with my current power supply. Just need to build everything again fill my loop and its time to test.

I love the cute "test bench" legs MSI give you with the motherboard 🤣

Also that clear CMOS button on the back of the mobo 😍 Having to take the side off a Lian Li O11 XL any time it was necessary to clear the CMOS on a Strix was awful.


----------



## Ezalor

PeterPete said:


> Hello guys I´ve tried to read up on the last 50 pages but I still have a couple questions for my 24/7 timings.
> 
> View attachment 2518253
> 
> 
> It´s stable on tm5 and Karhu but I´m still unsure about:
> 
> 1. my tCCD_L is 7. Should i adjust tFAW then or am I gonna be fine?
> 
> 2. I have no idea what to do with tWRRD. Should i just keep it at 4 or is 3 or 1 better in terms of stability?
> 
> 3. Same goes for tRTP. Should i increase it to 9 or is 8 fine?


Your setup should be able to do 3800, if you have tried and failed, just try to ease up on tRCDRD, go from 16 to 18, and i am sure you will succeed.

I have the same memory as you, but 4 sticks, and i was running 3800 at 16-16-16-16 for a long time, but being unstable. Then i saw one of the seniors here saying (it could have been Mannix or Craxton, cant remember) that easing up on tRCDRD is one of the easiest ways out of being stuck on getting forward with timings or instability.

Now im running 16-8-18-16 and it is perfectly stable!


----------



## Ezalor

PeterPete said:


> unfortunately my cpu cant handle 1900
> im hoping a future agesa update for my mobo will fix it since im still on 1.2.0.0


I am 4 day behind in this tread so my above answer didnt see this! But if unless you havent tried very loose timings already at 3800 (inc tRCDRD at 18), i still suggest you try it


----------



## Audioboxer

lol, something I didn't see coming is the CPU slot on this motherboard must be slightly to the left of the one on my Strix.

So two of my watercooling pipe runs are off. One can be shortened and be OK, the other needs to be redone. Thankfully I have some hard tubing left over.

Just one of these things you don't think about until something like a motherboard change and the small variances.

I will get back to my memory testing yet!


----------



## Mach3.2

Audioboxer said:


> lol, something I didn't see coming is the CPU slot on this motherboard must be slightly to the left of the one on my Strix.
> 
> So two of my watercooling pipe runs are off. One can be shortened and be OK, the other needs to be redone. Thankfully I have some hard tubing left over.
> 
> Just one of these things you don't think about until something like a motherboard change and the small variances.
> 
> I will get back to my memory testing yet!


The pains of hard tubing.


----------



## spajdr

Hello gents,
Both errors happened at nearly same time (around 1h 44m)
Any idea what to set differently this time?


----------



## Audioboxer

lol these MSI bios show ohm values instead of like RttPark 3. Can anyone tell me how you convert to the ohm values? 🤣

Thanks


----------



## spajdr

@Audioboxer default value is 240 ... so 240:7 (RZQ/7) would be 34.3 ohms if that helps


----------



## Audioboxer

spajdr said:


> @Audioboxer default value is 240 ... so 240:7 (RZQ/7) would be 34.3 ohms if that helps


Was just trying to figure out what RttPark 3 was lol. I presume 240:3 so 80?


----------



## sendap

correct


----------



## tcclaviger

Patriot Viper 4400s.. what can I say.

Currently have 2 under water, cold and high voltage.

1 arrived bad, instant C5 qcode on power up, other 3 sticks fine, but 3 makes no sense so went with 2.

RTT values the C7H auto selected were grossly unstable, went back to what it used for the 4 stick setup and....working well now. GD disabled 1t, still dialing in but seems promising. 

Have another pack of 4400s in the mail, want my 4x8 no gear down 3770C14 setup since 3800(+) is a no-go (thanks Asus/AMD).

As soon as I typed the above, crashed. I'm not super impressed, probably scrapping 4x8 and taking the easy way out with gskills new -a sku 4000C16D 16x2 kit.


----------



## craxton

Audioboxer said:


> Was just trying to figure out what RttPark 3 was lol. I presume 240:3 so 80?


You can go into "advanced/amd overclocking section and set those rtt settings with rtt/3/7 etc. It's the way it should be there. Just don't change them inside the main page if your using those settings or it over throws it...


----------



## Blameless

Got everything-I-can-think-of-stable on my wife's new workstation a while ago:









It's using:

- Two individual 32GiB Samsung OEM 2667 CL19 (JEDEC only, no XMP profile) M-die DIMMs I bought two years ago for $120 a piece, played with for a while, then threw in a box for a year after my Crosshair VIII impact bit the dust.

plus

- Some 2x32GiB Kingston HyperX OEM pull from an Alienware that I got second hand with the CPU, just cause it was cheap. These are Micron 16Gb B-die, rated for 3200 CL20, 1.25v, I think.

One of the Samsung DIMMs won't even POST with more than 1.32v and both are super sensitive to temperature. I've got cheap aftermarket heatsinks on them, which help. The Micron stuff likes voltage and aren't stable at these settings at below 1.29v, so there is a very narrow range where they overlap, at least at 3600.

Rtt Park of /3 is an absolute no go on this setup and /2 is flaky. Needs an RZQ of /1 here to be stable.

Had a hell of a time getting it to consistently train correctly until I reduced the resistance for ClkDrvStr below that of AddrCmd, which is the opposite of what nearly all of my lower density setups like.

These Samsung ICs also hate too low of a tRAS or tRC, so that is necessarily loose. None of these DIMMs can tighten tRFC much further.

tRCD and tRP cannot be tightened without more volts and more volts either results in too much heat, or the weak Samsung DIMM dropping out.

Probably a few small things I can improve upon, but since it's as close to unconditionally stable as it gets here (and this system is going to be doing real work for real money), I think I'm going to leave it alone. No training issues; boots warm or cold in any ambient a human with normal clothes would tolerate. Stable as hot as I can get things in a closed case with fans at 30% or higher. Can pass any test or combination of tests I've attempted.

The Gigabyte board (which I'm using because it came with my RTX 3080) is a bit strange as well, some extremely in depth settings in some places, but missing some obvious ones elsewhere. For example, it has no option to adjust VRM switching frequency or phase shedding anywhere, but allows me to put in memory training seeds and set each CCX as it's own NUMA node (if I care to).


----------



## tcclaviger

So this Viper, it's acting like poo trying to get 3770 @ 14 and tight subs. Was ready to rip it out and then thought "Self, remember there's a point at which 2:1 no longer matters and you get the same latency with a lot more bandwidth"...

Working towards that now, this is stable and I'm no where near done tweaking it...


----------



## element229

[email protected] base (4.6 allcore / 4.8 singlecore)---3800Mhz-C16-15-13-28-1T GDM ON---1.4v---SOC 1.2v---BIOS AGESA 1.2.0.3b---HCI---200%---F4-3600C16-16GTRS

MSI MEG ACE x570, Stats captured in a full windows 10 boot.

See pics. My best cores on ccd1 are 0 & 2. My curve optimizer says -3 -20 -3 -14 -16, -18 -20 -20 -21 -21 -22 -21. 

Note1: There seems to be a bug with EDC, so you MUST set EDC Auto OR limit EDC to the current to your specific model of CPU. (I had errors with PBO2 that were impossible to find while using my MSI "motherboard EDC limit" which was 220Amps default. Just leave EDC auto, it manages its power best. Seems if you try to set an EDC, it doesn't handle power as well and there could be problems over the stock level (5900x is 140 Amps).

Note2: If you're rebooting at idle, you're probably (A) pushing the undervolt on your best core too far causing its neighbors to crash, or (B) Hitting a diagnostic voltage during a power state transition to idle, or (C) not providing adequate VDDP/VCCD




























Please let me know if you have suggestions or would like more information. I basically tried every combination of every setting until I could run flawlessly at all core 4.6 with extremely low latency and my dimm temps never go over about 45c.


Have a good one.
My ram can be found under several different models: F4-3600C16D-32GTRG, F4-3600C16D-32GTRS, F4-3600C16D-32GTZN, F4-3600C16D-32GTZS, F4-3600C16D-32GTZR

rebooted, ran all the tests again. lookin good. almost every time I do this test it looks like this or better. If Windoze does something in the background, i see 55.4ns










Edit - oops, My CPU-Z score is slightly slower than that because I brought down my juice or something... here's my actual in-windows score:


----------



## tcclaviger

Last tweaking of the memory for the day, have it doing Karhu for the evening now. Not sure I put any faith in AIDA anymore, the system is notably snappier at 2:1 with 4417 than at 1:1 with 3770.

Very curious what I can do with the 4000 16-16-16 Dual Rank 16x2 that's coming Wednesday!!

PBO - Disabled, didn't want boost happy Core 0 to falsely represent latency lol.


----------



## Audioboxer

So RttPark 3 is struggling to boot on this new board, a board which is explicitly for memory overclocking. Must just be the quality of my b-die. Unless it could somehow be the CPU, but it's been running fine and performs well.

Still, this board seems to be a bit more stable, timings that were struggling before seem to be running fine. So now begins seeing what I can come up with for daily timings.

I've noticed the board autos at 36.9ohm ProcODT and all 20's on DrvStr. Prior board operated at 43.6ohm and all 24's on auto. Not sure if that signifies a "better signal" or its just variance between manufacturers auto settings.

On a related note anyone know what can change tPHYRDL? Previously on my old board both my sticks were at 26, now one is at 28 and another 26.


----------



## mongoled

Audioboxer said:


> So RttPark 3 is struggling to boot on this new board, a board which is explicitly for memory overclocking. Must just be the quality of my b-die. Unless it could somehow be the CPU, but it's been running fine and performs well.
> 
> Still, this board seems to be a bit more stable, timings that were struggling before seem to be running fine. So now begins seeing what I can come up with for daily timings.
> 
> I've noticed the board autos at 36.9ohm ProcODT and all 20's on DrvStr. Prior board operated at 43.6ohm and all 24's on auto. Not sure if that signifies a "better signal" or its just variance between manufacturers auto settings.
> 
> On a related note anyone know what can change tPHYRDL? Previously on my old board both my sticks were at 26, now one is at 28 and another 26.


Would not have gone down that route of getting a "2nds" motherboard as I would always be second guessing if any possible issues I were seeing were one of the reasons the motherboard was initially sent back.

On the assumption the motherboard is good, maybe the CPU is the culprit ?

Now to your question, tCL and 2tCmd are the values that effect tPHYRDL along with the memclk frequency.

FYI, I upped to tCL 15 from 14 @3800 as tCL 14 was kicking all my sticks to tPHYRDL @28


----------



## Audioboxer

mongoled said:


> Would not have gone down that route of getting a "2nds" motherboard as I would always be second guessing if any possible issues I were seeing were one of the reasons the motherboard was initially sent back.
> 
> On the assumption the motherboard is good, maybe the CPU is the culprit ?
> 
> Now to your question, tCL and 2tCmd are the values that effect tPHYRDL along with the memclk frequency.
> 
> FYI, I upped to tCL 15 from 14 @3800 as tCL 14 was kicking all my sticks to tPHYRDL @28


True, but it genuinely looked unopened, still sealed with the manufacturers tape.

I don't know enough about RttPark and the other resistances to know if them not booting is commonly a sign of mobo/CPU issues or simply the memory itself is struggling at that frequency/resistance value. I mean surely there is a reason out of the gate DR b-die seems to prefer disabled/3/1?

Hmm, I'll have a look but I just copy/pasted some settings from before and it was 26/26 then. I guess there might be some things in the MSI bios I haven't looked at. It's a lot different from ASUS, I think I prefer the ASUS layout tbf lol. But hooray, VDIMM and MEM VTT show in ZenTimings now.


----------



## mongoled

Audioboxer said:


> True, but it genuinely looked unopened, still sealed with the manufacturers tape.
> 
> I don't know enough about RttPark and the other resistances to know if them not booting is commonly a sign of mobo/CPU issues or simply the memory itself is struggling at that frequency/resistance value. I mean surely there is a reason out of the gate DR b-die seems to prefer disabled/3/1?
> 
> Hmm, I'll have a look but I just copy/pasted some settings from before and it was 26/26 then. I guess there might be some things in the MSI bios I haven't looked at. It's a lot different from ASUS, I think I prefer the ASUS layout tbf lol. But hooray, VDIMM and MEM VTT show in ZenTimings now.


First red flag,

Ive never bought an MSI motherboard (European market), brand new, that had a sticker sealing the box and ive bought quite a number over the last few years.

The only place there was a sticker sealing something is on the antistatic bag that holds the motherboard.

The only time I bought a "brand new" MSI motherboard that had a sticker sealing the box was when I received (Amazon.de) a motherboard that someone had swapped out with a destroyed one (ICs torn off from the back).


----------



## Audioboxer

mongoled said:


> First red flag,
> 
> Ive never bought an MSI motherboard (European market), brand new, that had a sticker sealing the box and ive bought quite a number over the last few years.
> 
> The only place there was a sticker sealing something is on the antistatic bag that holds the motherboard.
> 
> The only time I bought a "brand new" MSI motherboard that had a sticker sealing the box was when I received (Amazon.de) a motherboard that someone had swapped out with a destroyed one (ICs torn off from the back).


Yeah possibly Amazon added it then if they checked it. If it was opened and used whoever put it back together literally used nothing other than the mobo and even then there wasn't a bit of dust, fingerprint or mark on it.

It's running fine so I doubt I can blame my memory not booting at RttPark 3 at 3800mhz on the board, again. I'll pickup some new b-die soon now that Amazon refunded me and try it.

My memory for example cannot do SCLs on 3 at 3800. I've seen quite a lot of people run their SCLs on 3 even at 3800 with b-die.

For now going to see what I can get out of this b-die as it seems to be running a bit better on this board timing wise.


----------



## Nighthog

I decided to finally put in all my 4x8GB Crucial Ballistix MAX rather than running 2x8GB @ 5000Mts..

Surprised to see it's not stable with AUTO settings @ 4200Mts, 4400XMP doesn't boot either.
This *Rev.1.0* X570 Aorus Xtreme just doesn't mange better than *~4200-4266Mts* with *4x* dimms and you need to massage it to get working as well.
Better quality Rev.E didn't improve the possibility to boot higher frequency for 4x single rank memory either.

EDIT:

WOW... I'm surprised!
4x8GB @ 4200Mts is faster than 2x8GB @ 5000Mts, in both Y-cruncher benchmark & Linpack Extreme benchmark.
With no tuning!

Example results:
Y-cruncher: 179.469 seconds (computation time) vs 194.625s
Linpack: 200GFLOPS vs 190GFLOPS

AIDA64 says otherwise for the Memory benchmark with 5000Mts being better but real applications perform better with slower 4x8Gb.

EDIT2:
Nevermind...
*Forgot I ran much higher voltages for 5000Mts that eats into the CPU power budgets. Why CPU speed was running faster for 4200Mts than 5000Mts.*


----------



## XPEHOPE3

Blameless said:


> Got everything-I-can-think-of-stable on my wife's new workstation a while ago:


Sorry, couldn't resist 😇 😅

----------
Unrelated:
Anyone saw such ending from TM5?!


----------



## mongoled

XPEHOPE3 said:


> Sorry, couldn't resist 😇 😅
> 
> Anyone saw such ending from TM5?!
> View attachment 2518684


Thats insane

🤣 🤣


----------



## Audioboxer

XPEHOPE3 said:


> Sorry, couldn't resist 😇 😅
> 
> ----------
> Unrelated:
> Anyone saw such ending from TM5?!
> View attachment 2518684


lol

You've reminded me I should check and see if I can do above 1900 without WHEA errors on this board. 1900 is fine as it was before, no WHEA, but booting 1933-2000 previously had me seeing WHEA.

Though I'm not sure how much of WHEA is on CPU and how much it is also on mobo and AGESA.

I love that the MSI boot code dial turns into a CPU temperature sensor. I get to see the lovely 90 in red led when running y-cruncher lol.


----------



## Blameless

Been increasingly annoyed with how divorced AIDA64's Cachemem seems to be from actual memory performance, especially on this platform.

Case in point, some identical settings, except for tRAS/tRC (and tRFC 2/4) in AIDA64:



















If I was just using AIDA to quickly assess if my tuning was doing anything, I'd come to the conclusion that these were senseless tweaks, despite seeming stable and not requiring any extra voltage.

Now the same sets of timings in WinRAR (which has always been one of the more memory performance limited/dependent real-world consumer apps):


















These results are reproducible...the tighter timings that do nothing in AIDA64 are fairly significant in WinRAR's compression benchmark.


----------



## XPEHOPE3

@Blameless notice how you have different tPHYRDLs (at least for A memory channel). Usually 28 gives higher latency though.
Also to measure consistently one has to use the same data size, and your Winrar screens show different.
With that said, me too couldn't get any difference from Aida for tRAS and tRC, although the same TM5 config was finishing slightly faster for tighter tRAS+tRC.


----------



## kratosatlante

tcclaviger said:


> So this Viper, it's acting like poo trying to get 3770 @ 14 and tight subs. Was ready to rip it out and then thought "Self, remember there's a point at which 2:1 no longer matters and you get the same latency with a lot more bandwidth"...
> 
> Working towards that now, this is stable and I'm no where near done tweaking it...


I have same cpu and 2 kits viper try your settings and reply


----------



## Blameless

XPEHOPE3 said:


> @Blameless notice how you have different tPHYRDLs (at least for A memory channel). Usually 28 gives higher latency though.


It's the same on both channels and is set according to tRAS or tRC on this board. I have no direct manual control over the timing.



XPEHOPE3 said:


> Also to measure consistently one has to use the same data size, and your Winrar screens show different.


That's just because I let the test run longer, letting it process more. The bold benchmark result is achived at the same one-minute mark for both.


----------



## Ezalor

Hello.
I have not presented any hard data/screenshots of my system until now, i hope i can spark some interest for my setup, that could use a little advice on how to progress.

Having had this setup (5950x, Aorus X570 Pro and 4x8 GSkill FlareX 3200c14 since December 2019, all my attempts to get away from stock speeds and get 3600 and above stable, have been unsucessfull.

Until 3 months ago or so when @Veii posted a Zentimings view of a 2x8 setup of the same FlareX. I copied it and voila, i had an almost stable 3800-setup.

I was running 3800 and 16-16-16-16, but could not understand what made it unstable. It was stable enough to daily everything i do, including a few games, but i was not content with the situation.

Then a month back someone wrote, to someone else with similar problems, "just ease up on the tRCDRD", i tried that, and going from 16 to 18 made all the difference.

I lost a bit performance, but now it is totally stable. Today it looks like this, after a bit more tinkering:










I am quite happy with this, especially the low voltages required to run this.
VDimm 1.41 and all the other VDDG's ,VDDP and VSOC is quite low.
tRAS TRC at 42 is also noticably low i think.

But tips would be very welcome on what to try next, i cannot quite let go of the goal of seing 54.x in latency. I been trying alot of stuff, but cannot get it below 55. This is how it performs right now:









Running 3866/1933 gets me below 55ns, but with the famous Whea19, so i am sticking to 3800.

Also, a pic of OCCT running, temps max out at 43C after 45 min.










So, any suggestions on my setup would be greatly appreciated!


----------



## domdtxdissar

XPEHOPE3 said:


> @Blameless notice how you have different tPHYRDLs (at least for A memory channel). Usually 28 gives higher latency though.
> Also to measure consistently one has to use the same data size, and your Winrar screens show different.
> With that said, me too couldn't get any difference from Aida for tRAS and tRC, although the same TM5 config was finishing slightly faster for tighter tRAS+tRC.


We have other real "real-world benchmarks" to measure the performance difference between different settings.
A few months back in this thread we started using the Monero RandomX Miner as a benchmark (instructions how to install the miner can be found here)

Results from *ManniX-ITA *can be found here: *18550.8 H/S* over 15 min run

Here are my latest results with a Sophia-Script slimmed windows 10 install: 20208.7 H/S over 15min run

My previous results with win11: *20038.6 H/S over 15min run*

My older results with bloatware win10: *19723.4 H/S over 15min run*

Each of the links above have many different memory configurations compared...
I did test *T1 GDM vs T2 GDM-off vs T1 Setup-time* in my oldest post above.

I would also recommend everyone very much to read the following post as it shows one of the reasons why *Aida64 cant be used as a performance metric/index alone*..


RonLazer said:


> Sorry for the delay, had some real work to do, but I finished my testing, I'll explain my methodology a bit first though.
> 
> *OS:* Windows 20H2 x64. It's my Bench OS so it's quite lightweight. I used @ManniX-ITA High-Performance Power plan.
> *CPU:* 5600X [email protected] SET (LLC 1, droops to 1.2V) - SMT enabled.
> *BIOS:* Spread Spectrum: disabled, Global C-States: enabled, PLL/1P8 Voltage locked to 2V, DFE/FFE training enabled.
> *Memory:* See Zentimings in screenshot, had to adjust the DRAM and SOC voltages as I increased frequency.
> *Benchmark:* Linpack Extreme 1.1.5, with the standard 3Gb test run 5 times.
> View attachment 2512597
> 
> *Why Linpack?*
> It's as close to a "real-world" memory test as any benchmark gets, it will hammer the memory controller AND the CPU so the CCD portion of the infinity-fabric gets hot, uses fairly representative memory in it's "Standard" benchmark (3Gb of heavy IO is about typical for most games/computational-software) and is multi-threaded. The problem with Aida64 bandwidth and latency tests is they put absolutely zero strain on the memory controller, Geekbench is too short and too synthetic, and y-cruncher is a fair substitute but is far heavier than any real-world use-case and so only really useful for scoring HWBot points or really proving a point about stability.
> 
> *Why a static Overclock?*
> It stops thermal variation affecting PBO, and allows comparison across different silicon-quality CPUs. Linpack is a very heavy memory benchmark, but still mostly scales with CPU and so without locking the CPU core ratio we'd just be comparing who has the best-binned 5600X. It also isolates the impact of higher SOC power pulling from the PBO power/current budget.
> 
> *Why GearDownMode?*
> This means we're not fiddling with CAD setups etc. to stabilize our respective overclocks - which will impact performance. Feel free to adjust drive-strengths/ProcODT/RTTs to match your boards/dimms impedances, they won't dramatically affect the results. I can't even run CR 1T at 3800 with my 4x8gb kit, and Linpack doesn't particularly care about latency in isolation anyway.
> 
> *What about the SOC-derived voltages?*
> Feel free to tune SOC/CCD/IOD/VDDP/PLL to match your CPU, I just didn't want to get bogged down in fine-tuning these to squeeze out the last few % when the goal is to show and compare qualitative trends. I just used ballpark values I know have worked in the past. The timings are not very tight at all, because I didn't want this to be a comparison of memory controllers, but instead of the infinity fabric link itself.
> 
> As both the memory/CPU overclock are quite mild, in theory anyone can try and replicate this, including those with 5900X or 5950X's by disabling the 2nd CCD and limiting the number of active cores in the BIOS.
> 
> Here is the full graph from 1800MHz to 2033MHz:
> View attachment 2512596
> 
> The drop-off is obviously distorting the scale so let's remove 2033MHz:
> View attachment 2512598
> 
> Not quite sure what happened at 1933MHz, it even failed to POST a few times so I think I have a weak "FCLK hole" at that frequency on my CPU. The overall trend seems to basically show what I claimed initially - that FCLK equalization mechanism stops functioning properly after 1900MHz. The actual memory performance under load is barely increasing beyond 1900MHz, despite the fact that the timings are constant so we should see a rise in throughput solely on the memory side, the infinity fabric link is clearly bottlenecking the memory performance. As far as I've been able to tell, speeds over 1900MHz are basically just for show, or very very light workloads. I've observed this same behavior in multiple benchmarks before, this is the first time I've properly collected the data on it.
> 
> Here is my screenshot for the 2033MHz run:
> View attachment 2512599
> 
> You can literally see the performance dropping off as the CPU gets further into the benchmark, and the data-fabric and IOD get hotter, and hence less stable. This is why brief "bursty" benchmarks like Aida64 are insufficient, they don't actually push the CPU at all so instability doesn't kick in hard enough to manifest as performance degradation.
> 
> I'd like to see some people try and replicate these tests (should be pretty easy for anyone with 4 sticks of B-die) and a Zen3 CPU. This will allow us to compare and see if the performance stagnation kicks in at 1933MHz for everyone, and if the sharp drop-off at 2033MHz is also a universal feature. A few tips to improve reproducibility:
> 
> 1. Start with a single 2gb run first to "wake up the CPU". If you don't then the first loop will be slower than the others. I assume this is due to scheduler behaviour, could also be core parking.
> 2. Close all background processes, ideally run in Windows 10 Diagnostic Mode.
> 3. If a run is anomalously low, reboot and try again. Memory training is super variable and boot-to-boot variation can sometimes be larger than changes in timings/frequency/voltages.
> 
> *Working Conclusion?*
> I'd like to see more results, but I strongly suspect the optimal fclk frequency for pragmatic daily usage really is 1900Mhz and no amount of fiddling is going to fix this. If there was a magic setting in the CBS that fixed all the issues and unlocked the full potential of higher clocked memory with no risks or downsides - why haven't AMD just turned it on for us?
> 
> Also if there was, someone would have found it by now. I've tried almost all of them, some of them help a little, nothing actually changes this overall trend. You can definitely hack together a BIOS config that will spit out excitingly low latency numbers, but as soon as your CPU gets hot it will probably crumple, and even if it doesn't - are the gains really worth the extra strain you're putting on your CPU with the higher SOC voltages? Probably not.


For those who don't want to open a new page to read that whole quote with pictures, this is the gist of it: (Only Aida64 show scaling above fclk1900 while real apps/benchmarks don't)








In one of my links to the results from the Monero RandomX Miner above, i found around 4% real performance increase going from flck 1800 to flck 1900 on otherwise same settings with static OC, and no or even negative from going above 1900, with my system at least.

Sadly i don't think many will read and understand this post and will just continue the hunt for "fake/useless" aida64 numbers above 1900 with no bearing on the real performance they are actually getting.

I will end with a useless aida64 screenshot. This is my dual CCD 5950x + 4x8gb memory windows11 install putting up 51.1ns latency numbers @ 1900 fclk:
My current win10 settings have around ~0.5ns higher memory latency numbers in aida64, but are performing better in everything i try to benchmark.






VS








_edit_
One other easy program to compare real memory performance is dram calculator's easy/default mem benchmark


----------



## Blameless

Took a closer look at tPHYRDL on this setup and it's not directly based off any specific timing, but does train more often to the tighter 26 at looser tRAS/tRC. Some other settings that seem to influence wether training sticks it at 26 or 28 are VDDP (I adjusted both CLDO and CPU VDDP) and, oddly enough "DRAM Map Inversion". Higher VDDP and having the map inverted tend to prompt 26 more readily.

Can't find any good correlation between what tPHYRDL winds up at an performance, however. Some times a particularly bad performing training has 26, while a good one sets 28, and vice versa.

ARock really skimped on the training controls on this firmware, so I have limited ability to tune related parameters.


----------



## XPEHOPE3

domdtxdissar said:


> Only Aida64 show scaling above fclk1900 while real apps/benchmarks don't


Can you please provide the @RonLazer 's quote about this? He didn't provide screenshots about it, and I don't see him mentioning Aida64 showed scaling in his case.
The other posts (about miner) I saw. I used to use xmrig to test, but it didn't show effects of some changes which GeekBench 3 and Aida64 did.
Anyway, I understand Aida64 latency and bandwidth tests are nowhere near enough to test performance. I only use them to guide what to test in terms of stability. And after TM5 run I already have another performance metric (the time of the run itself). After I collect several timing configs which pass stability and are "good enough" in terms of Aida, I can test performance with other means.

@Blameless 
tPHYRDL from our testing can get retrained after whatever timing, RAM-related voltage or resistance you change. One notable confirmed change was tCL15 vs tCL14 (or tCL16). That triggered tPHYRDL from 26 to 28 (or from 28 to 26) resulting in config with higher tCL but lower tPHYRDL giving better latency.
It seems +2 tPHYRDL overcomes -1 tCL, but for other timings net effect can be different, as you saw judging from this


Blameless said:


> Some times a particularly bad performing training has 26, while a good one sets 28, and vice versa.


----------



## byDenoso

Seems like i'm really close to stabilize my kit with tRP 17


----------



## Blameless

XPEHOPE3 said:


> Anyway, I understand Aida64 latency and bandwidth tests are nowhere near enough to test performance. I only use them to guide what to test in terms of stability. And after TM5 run I already have another performance metric (the time of the run itself). After I collect several timing configs which pass stability and are "good enough" in terms of Aida, I can test performance with other means.


The issue is that AIDA64 has traditionally been used as very fast way to see if settings are doing anything, and thus worthy of testing further. If AIDA64's benchmark is not revealing meaningful performance differences between settings, it's kinda useless.

Certainly, there are plenty of other tests, some of which are almost as fast, but that doesn't absolve AIDA of it's dubious utility.



XPEHOPE3 said:


> @Blameless
> tPHYRDL from our testing can get retrained after whatever timing, RAM-related voltage or resistance you change. One notable confirmed change was tCL15 vs tCL14 (or tCL16). That triggered tPHYRDL from 26 to 28 (or from 28 to 26) resulting in config with higher tCL but lower tPHYRDL giving better latency.
> It seems +2 tPHYRDL overcomes -1 tCL, but for other timings net effect can be different, as you saw judging from this


On this setup VDDP is proving to be the most reliable way to control tPHYRDL training.

At the settings I was using above, below 840mV one or both channels is virtually always 28. From 850-860 it can go either way. 870mV and up is always 26.

Regardless, the effect of tPHYRDL seems to be extremely small, in and of itself.


----------



## XPEHOPE3

Blameless said:


> Regardless, the effect of tPHYRDL seems to be extremely small, in and of itself.


I routinely encounter +0.7ns Aida latency going from 26/26 to 26/28 everything else being equal. What difference do you get?


Blameless said:


> At the settings I was using above, below 840mV one or both channels is virtually always 28. From 850-860 it can go either way. 870mV and up is always 26.


Thank you for the testing!


Blameless said:


> Certainly, there are plenty of other tests, some of which are almost as fast, but that doesn't absolve AIDA of it's dubious utility.


What two tests would you recommend for latency and read throughput which would be more sensitive to timings change and be sub 10 minutes? The latter should include time for several runs, if averaging is needed to get stable metrics.


----------



## Blameless

XPEHOPE3 said:


> I routinely encounter +0.7ns Aida latency going from 26/26 to 26/28 everything else being equal. What difference do you get?


There is no strong correlation between reported AIDA64 latency and tPHYRDL on this system. I cannot predict whether I'm getting 26/26 26/28 or 28/28 based on AIDA64's benchmark. I normally get 57.7 to 58ns in the latency bench, but I can rarely see as high as 58.6. I've seen tPHYRDL 26/26 and 28/28, at both extremes.



XPEHOPE3 said:


> What two tests would you recommend for latency and read throughput which would be more sensitive to timings change and be sub 10 minutes? The latter should include time for several runs, if averaging is needed to get stable metrics.


WinRAR's built-in benchmark is _very_ sensitive to memory performance and takes one minute. It's not perfect as it's slightly susceptible to CPU performance (and thus temperature), but it did show well beyond margin of error changes to settings that did nothing to AIDA64's bench.

Y-cruncher and XMRig are also good candidates, but they are more CPU sensitive so may require a fixed/all core OC to to isolate the memory enough to be reliable, unless one can very carefully control boosting.

I still use ADIA64 as it's there and it's fast, and might catch something others miss.

Still looking for other quick and reliable options that are reflective of actual memory performance.


----------



## byDenoso

Ezalor said:


> Hello.
> I have not presented any hard data/screenshots of my system until now, i hope i can spark some interest for my setup, that could use a little advice on how to progress.
> 
> Having had this setup (5950x, Aorus X570 Pro and 4x8 GSkill FlareX 3200c14 since December 2019, all my attempts to get away from stock speeds and get 3600 and above stable, have been unsucessfull.
> 
> Until 3 months ago or so when @Veii posted a Zentimings view of a 2x8 setup of the same FlareX. I copied it and voila, i had an almost stable 3800-setup.
> 
> I was running 3800 and 16-16-16-16, but could not understand what made it unstable. It was stable enough to daily everything i do, including a few games, but i was not content with the situation.
> 
> Then a month back someone wrote, to someone else with similar problems, "just ease up on the tRCDRD", i tried that, and going from 16 to 18 made all the difference.
> 
> I lost a bit performance, but now it is totally stable. Today it looks like this, after a bit more tinkering:
> 
> View attachment 2518739
> 
> 
> I am quite happy with this, especially the low voltages required to run this.
> VDimm 1.41 and all the other VDDG's ,VDDP and VSOC is quite low.
> tRAS TRC at 42 is also noticably low i think.
> 
> But tips would be very welcome on what to try next, i cannot quite let go of the goal of seing 54.x in latency. I been trying alot of stuff, but cannot get it below 55. This is how it performs right now:
> 
> View attachment 2518740
> 
> Running 3866/1933 gets me below 55ns, but with the famous Whea19, so i am sticking to 3800.
> 
> Also, a pic of OCCT running, temps max out at 43C after 45 min.
> 
> View attachment 2518742
> 
> 
> So, any suggestions on my setup would be greatly appreciated!


Maybe you can do 16-16-16 if you loose the subtimings


----------



## gled_fr

Soo no matter what I do on cldo vddp, CCD or IOD voltages, IF 1933 is WHEA 19 land... And by a lot... 1900 is rock stable...

What is weird is that tm5 passes at 1933 without trouble.. It's just generating WHEA 19 by the hundreds...


----------



## Ezalor

byDenoso said:


> Maybe you can do 16-16-16 if you loose the subtimings


Any tip on what subtimings are affected/connected to tRCDRD more than others?

I have been trying randomly to loosening secondary/tertiearies but not made progress (The curse of not knowing what you're doing) . I might try putting everything on 16-16-16-16 and the rest on auto just to see if it works, but i am pretty sure that my current 16-8-18-14 with good secondary/tertiary timings will be better.


----------



## mongoled

gled_fr said:


> Soo no matter what I do on cldo vddp, CCD or IOD voltages, IF 1933 is WHEA 19 land... And by a lot... 1900 is rock stable...
> 
> What is weird is that tm5 passes at 1933 without trouble.. It's just generating WHEA 19 by the hundreds...


Just putting this here as this is new to you (and probably many others) but trust me its nothing new and yes its "weird"

First screen shot is not using Manni-ITX WHEA 19 "suppressor"

2nd screenshot is ...


----------



## Ezalor

byDenoso said:


> Maybe you can do 16-16-16 if you loose the subtimings


Said and done, put everything on flat 16, and the rest on auto. Better performance than i expected actually, but lower. Exept for L3 latency, went from 10.5 to 10.3.

The big hits are being applied on Trc, Trfc, Tfaw, Twr. But OCCT memtest gave first error after only 3 minutes.


----------



## Veii

Blameless said:


> At the settings I was using above, below 840mV one or both channels is virtually always 28. From 850-860 it can go either way. 870mV and up is always 26.


This could have a valid point
I noticed on my 13-13 sets that it dropped to 24 on B1 but held 26 on A1 @ 0.83v ~ while my current 4200C15-15 set holds 26 for both @ 0.9 VDDP
* lower than 860mV doesn't train 2100 MCLK. 850 is the wall ~ but it changes procODT behavior & requirement

According to more intel Research
tPHYRDL has more to do with _SG & _DD's. (more information soon, learning intel OC)
Which have to do with tCWL & tWTR_L
But there is no direct change with tRDWR & tCWL - on PHYRDL or MRDPDA
* yet these latency differences are 0.2ns at best for me between correctly powered B1 slot
** it rather shows as IMC autocorrection , than has anything to do wih IOL missmatch. Same concludes for 10th and 11th gen intel. It does not change the stability outcome tho

I'll research further with low cLDO_VDDP and the range required for MCLK IMC to function
But "Bad IMC" wording *≠* Refused FCLK.
High FCLK has to work on all units till 2000. It was a bad idea before but now can agree to test it split. MCLK individually and FCLK individually
MCLK for cLDO_VDDP & procODT + RTT_WR range
FCLK for VDDG CCD, IOD & SOC range. Also +/- 1 procODT if boot fails
========================================================
You guys should give tWRWR & tRDRD ~ DD's 2 or 1 a try

















Spoiler: 2 vs 4 ~ nearly always 75-100MB/s difference. Often more





















The difference between identical and different is around 1gb 300MB/S read & Copy
Sadly only 2GB/s Linpack (60GB/s between 3666C13 & 4200C15)
Compared to intel's AVX512 we have no chance


Spoiler: Overclocker Madness777














But out of all testing, it can make sense that we focus on tWTR_S 2 or lower ~ for timing design
It's harder to stabilize, and #2 errors appear more, but i didn't get issues with tWTR 3-14 either instead of 5-14

My testing on 3666 & 3733 was nearly a waste of time
RTT_WR /2 does not work on beyond 4000+
It's a PCB thing , i can not get it to function after 3-4 days of try
RTT_NOM in the 1.66v range can be disable or /7 easily, /6 works but /5 will already show #4's or other mirror-timing test missmatches.
RTT_WR /2 can clearly not work with tCKE influence and RTTs knowledge learned , 1:1 replicates on 10th gen for RTT's
* at least i figured an IC crashing hardwall at 1.68v

More information later, but give:
1-5-2-1-7-2 (SR)
1-4-2-1-6-2 (DR) a try
For 4 dimm setups, we need to figure out PHY's IOL autocorrection behavior.
Could be simply something like "different cLDO_VDDP" required
~ it does give some nice boost, if you can stabilize it

@XPEHOPE3 About tRCD_WR
I tested it now a lot, but i can not find a performance penalty or reason it makes issues. On no tRCD (low or high) preset.
But i could see it causing issues with my Rev.E's
It does change ~something~ with it , but i can not verify any performance decrease or stability decrease by it on B-Die. Nothing. B-Die just takes it
It accepts it, but does nothing
Yet on Rev.E it causes boot issues if it was too low.
~ topic is on hold. Can not deny it not functioning as it breaks for me. But i had no performance increase by it whatsoever.
Only have a performance penalty by missmatching tCL & tRCD on odd Experimental sets.
As long as tRP meets the (p)recharge target, nothing makes issues - soo i am not sure for now. Will not deny it, but can not see a reason to use it. Flat timings generally always performed better for me

EDIT:
Also OCCT Extreme is great for CO balancing now
If one core fails, you should not change this single Core CO (values are like the bios Core 0-15) / this is if you follow my CO cheat sheet
But you should change anything around this core (+1 or less - value)
Then when it stabilizes -2 on everything for 25mhz more boost. Then if one fails again adjust anything +1 till it's stable.
Cores will fail after 10-15min pretty consistently.
Cores do not fail on their own. dLDO is there. Balancing is the key for manual CO tuning. Core failure is possible if the distance is an issue & not the CO value on it's own
Yet manual CO tuning changes the magnitude and never overrides AMDs predefined binning (FIT's defined)

EDIT2:
@XPEHOPE3 please check on legit and dual CCD 6,8 cores if DPM LCLK functions.
There can be a difference between RTX PCIe 4.0 aware and 3.0 restricted GPUs
and there can be differences between NVMe enforcing 4.0 and 3.0


Spoiler: This has to function on "legit" units














Haven't seen it functioning on any dual CCD 1st supply unit
EDIT2.5:
Same would go for FCLK DPM at the center on the left ~ if this is active on these units
#19 clearly is an IO / PCH issue, but part of the issue can be the IO-Die CPU settings too
Had it only once by doing really stupid things and never ever again. Yet haven't seen DPM function at all on my sample

EDIT3:
1.8v Rail seems to have a connection with cLDO_VDDP range & behavior. So also modify the strength of procODT you can use
I'm not sure if they are directly connected or just is a side effect. But the influence is there


----------



## mongoled

Veii said:


> EDIT:
> Also OCCT Extreme is great for CO balancing now
> If one core fails, you should not change this single Core CO (values are like the bios Core 0-15)
> But you should change anything around this core (+1 or less - value)
> Then when it stabilizes -2 on everything for 25mhz more boost. Then if one fails again adjust anything +1 till it's stable.
> Cores will fail after 10-15min pretty consistently


Interesting, its something I thought about but never got round to testing


----------



## Ezalor

Made a mistake, missed to put tRas on auto, in the post above it is still on manual 28, after auto being applied it went to 58.
But, stability went even worse after that, first error after only 1.50







minutes.


----------



## Audioboxer

Veii said:


> EDIT:
> Also OCCT Extreme is great for CO balancing now
> If one core fails, you should not change this single Core CO (values are like the bios Core 0-15) / this is if you follow my CO cheat sheet
> But you should change anything around this core (+1 or less - value)
> Then when it stabilizes -2 on everything for 25mhz more boost. Then if one fails again adjust anything +1 till it's stable.
> Cores will fail after 10-15min pretty consistently.
> Cores do not fail on their own. dLDO is there. Balancing is the key for manual CO tuning. Core failure is possible if the distance is an issue & not the CO value on it's own
> Yet manual CO tuning changes the magnitude and never overrides AMDs predefined binning (FIT's defined)


Mind blown at this revelation. I "fixed" my falling down core by reducing its value, but now I guess I could have done it _wrong_.

2, 5, 11 and 14 are my best cores. 2, 11 and 14 are at -15. Haven't tried them higher (started at -15), but core 5 kept falling. Reduced it to -5 to stop that.

The rest of my cores didn't fall even up at -30. But this is now making me think core 4 and 6 being at -25 to -30 might have been having an issue on core 5? Am I understand that correctly?


----------



## spajdr

Slowly tightening timings but that tRCDRD ... any idea how to get it to 19 stable? If I set it I get errors in two mins.


----------



## Audioboxer

spajdr said:


> Slowly tightening timings but that tRCDRD ... any idea how to get it to 19 stable? If I set it I get errors in two mins.
> View attachment 2518829


Voltage is my only guess for having a crack at tRCDRD. Its the most stubborn setting on any memory I think. Hence why flat timing memory fetches much more money than memory that runs a lower tCL than it does tRCDRD.

I guess you could quickly try running 16-16-19-16 just to see if loosening other main timings allows tRCDRD to come down but I dunno, at 3800 you might just find you can't get it lower.

But I'm far from an expert here, just have a little experience with a very stubborn tRCDRD on my old Mircon E-die kit.


----------



## spajdr

@Audioboxer thanks for the tip. By the way how far did you get with your old E-die kit?


----------



## Veii

spajdr said:


> @Audioboxer thanks for the tip. By the way how far did you get with your old E-die kit?


Enterprise [MOD] Wiped couple of my Rev.E results ~ he didn't edit the posts to filter out drama. (understandable but i'm still annoyed)


Spoiler: Here are couple of Rev.E examples between 1.55-1.65v @ 42c peak / don't fear the voltage



































^ last one is what i ended up with
It's 31-35c outdoors, near the 30 mark indoors. Don't fear the voltage , really


----------



## Mach3.2

Audioboxer said:


> Voltage is my only guess for having a crack at tRCDRD. Its the most stubborn setting on any memory I think. Hence why flat timing memory fetches much more money than memory that runs a lower tCL than it does tRCDRD.
> 
> I guess you could quickly try running 16-16-19-16 just to see if loosening other main timings allows tRCDRD to come down but I dunno, at 3800 you might just find you can't get it lower.
> 
> But I'm far from an expert here, just have a little experience with a very stubborn tRCDRD on my old Mircon E-die kit.


While looking for Micron Rev. B overclocking info on Google, I frequently find people complaining about Micron ICs (Rev. E and Rev. B) having very stubborn tRCDRD walls.

I guess that's why B die is still king for ram OC, those can do very tight tRFC and flat primaries.


----------



## spajdr

@Veii Well I didn't put more than 1.45V for now, but when touching them, they are pretty hot, so before I continue I should probably put some RAM cooler on kits?
Great results by the way, thanks for posting these. I'm unsure if mine kits can go so high.
They have all same timings tho as you could see below.:


----------



## Audioboxer

spajdr said:


> @Audioboxer thanks for the tip. By the way how far did you get with your old E-die kit?


I used it with my 3900XT and couldn't boot 1900/3800 on that chip, so I was running 1866/3733. I was really noobish at this point with memory but IIRC I had to run 19 tRCDRD at 3733. Nothing lower would work and even then I'm still not 100% sure I was running properly stable for the year or so I was running it 

When I say nothing would work I mean with some safe-ish DRAM calculator settings for 3733, so I also didn't pump voltage too high on my E-die. I later learned E-die can actually be OK with higher voltages and it begins to scale a bit with them. IIRC it seems to have a bit of a wall around 1.4~1.45v, but then can take off a bit again nearer 1.5v+. Though I don't want to speak of proper experience here.


----------



## spajdr

So I tried a RAM settings what Veii posted just to see if it works at least for 3000Mhz and it still not even booted


----------



## Veii

spajdr said:


> So I tried a RAM settings what Veii posted just to see if it works at least for 3000Mhz and it still not even booted


You have over 5 settings to pick from
Presets
They include RTTs
Just scale the frequency down 

Dont yours have a temp sensor ?
Ballistix should have one


----------



## spajdr

@Veii Yep, tried them all, nothing work. Tried with same RTT settings even if they had only 2x8 rather than 4x8 as me, also tried RTT settings as auto.
I could go lower with frequency but if settings for 3800Mhz does not even boot at 3000Mhz, I don't want to try it at lower frequency.
These CL15 3000Mhz kits does not have temp sensor at least Taiphoon Burner or HWINFO64 not showing it.


----------



## Mach3.2

Veii said:


> Dont yours have a temp sensor ?
> Ballistix should have one


As far as i know only the RBG Ballistix kits and the Ballistix Max kits have built in temp sensors.


----------



## Veii

Mach3.2 said:


> As far as i know only the RBG Ballistix kits and the Ballistix Max kits have built in temp sensors.


mmmm~


spajdr said:


> @Veii Yep, tried them all, nothing work. Tried with same RTT settings even if they had only 2x8 rather than 4x8 as me, also tried RTT settings as auto.
> I could go lower with frequency but if settings for 3800Mhz does not even boot at 3000Mhz, I don't want to try it at lower frequency.
> These CL15 3000Mhz kits does not have temp sensor at least Taiphoon Burner or HWINFO64 not showing it.


I should have read your spoiler that you run 4 dimms
You didn't post a zentimings screenshot, else i would have noticed that
Unsure how your cLDO_VDDP is
Unsure what your PCB is. A2s would have to run this
4 dimms would need -2 steps RTT_Park and +2 steps procODT. Although only 1 step is enough on it
TWR on my sets was big, soo that shouldn't cause issues
tRFC was big, tRC too

You can only fail by bad RTTs and not enough VDIMM
RTTs require high vdimm

Idk else, lacks too much information. Didnt notice you run 4 of them
Can't say whats wrong, far too many unspoken variables
Maybe tRCD 18 is not enough on 3800, which usually works
But if you struggle even with tRCD 20 preset, you clearly mess something up

If 2T didnt post too, then idk
But"it errors" also doesn't help anybody
Whete does it error, what does it do. How is your zentimings screenshot looking
I dont know anything. Can't help you that way


----------



## spajdr

@Veii I changing timings a lot due to permanent testing.
What RTT settings I used for all profiles are these








And I did use Cmd2T - 2T for all profiles you mentioned.
I'm not mad if it sound like that  not at all.
Thanks again for checking.
Both kits use 8 layers rev A2.
What timings primarily affects minimum fps in the games? that's what I'm mainly looking for.

EDIT.: added more voltage settings
1.05V SB - 1.050V (auto)
2.5V SB - 2.500V (auto)
CPU 1.80V - 1.800V (auto)
VTTDDR 0.737V (auto)
VPPMEM 2.500V (auto)
DRAM Voltage 1.55V (for all profiles), currently using 1.475V for the settings above.


----------



## Mach3.2

spajdr said:


> What timings primarily affects minimum fps in the games? that's what I'm mainly looking for.











[Guide] - RAM Timings und deren Einfluss auf Spiele und Anwendungen (AMD) - Update 23.05.2020


RAM Timings und deren Einfluss auf Spiele und Anwendungen Testsystem | Aida64 Benchmark | Konvertieren und Rendern | Spiele Benchmark | RAM Takt vs Timings | Zusammenfassung Einleitung In diversen Tests wurde bereits festgestellt, dass durch das Optimieren von RAM Timings die Leistung...




www.hardwareluxx.de





He only talked about avg fps, but there should also be inprovements in the 0.1% fps.


----------



## XPEHOPE3

Veii said:


> @XPEHOPE3 About tRCD_WR


It was @PJVol who asked about tRCDWR here 


PJVol said:


> My apologies if this has already been discussed here, but can you, or anyone else in the know, confirm that the tRCDWR is actually being used by the Zen2/3 memory controller?
> Anybody got an idea?


----------



## PJVol

---


----------



## XPEHOPE3

Veii said:


> Haven't seen it functioning on any dual CCD 1st supply unit
> EDIT2.5:
> Same would go for FCLK DPM at the center on the left ~ if this is active on these units


Here's mine screenshot of 2CDD 5600x


----------



## PJVol

Veii said:


> About tRCD_WR


Yeah, it was me who asked about the tRCDWR influence on memory performance in this post
[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
which was left unnoticed. 

As for the reasons behind my interest, here are some tests I ran to make sure the difference is reproducible(just 8 vs 15):


----------



## seamonkeyhd

Hi everyone! I am getting WHEA instantly with this setup. I would appreciate any feedback or help. Thanks

4 SR DIMMs


----------



## Blameless

Veii said:


> You guys should give tWRWR & tRDRD ~ DD's 2 or 1 a try


My older Intel setups left me with the impression that most 'different DIMM' timings wouldn't do anything with only one DIMM per channel, but that's evidently not the case here.

"2" seems to work fine on this setup and does produce slightly better performance. Read and copy in AIDA64 are up a few hundred MiB/s and I can consistently crack 110k MIPS in 7-Zip...with them set to 6/4 I max out at between 108k and 109.7k.

Did need to bump VDDP 10mV to consistently train to tPHYRDL 26 with them set to 2 though.



PJVol said:


> Yeah, it was me who asked about the tRCDWR influence on memory performance in this post
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> which was left unnoticed.
> 
> As for the reasons behind my interest, here are some tests I ran to make sure the difference is reproducible(just 8 vs 15):


Hard to isolate any single timing given the variances at play and the cap on write bandwith with single CCD parts, but I am quite confident that tRCDWR is being observed and is doing something, even if all it's doing is reducing the minimum effective tRC.

https://web.eic.nctu.edu.tw/lpsoc/c...pplemental/3. DRAM Memory-Access Protocol.pdf -- page 10 (11.1.9 A Write Cycle).

I'm not sure how mandatory all of those operations are, but tRCD is always a limit on minimum tRAS/tRC and write operations will use tRCDWR.

I can also reproduce performance differences in some tests.


----------



## biggbosss

Hi, i want some help resolving a rare but annoying whea error problem i have.
I have a 5600x, a b450 a-pro with latest bios (agesa 1.2.0.2 i think), a flarex 3200c14 b die kit 16gb, single rank.
I copied the ram settings from this post in this thread AMD max overclocking voltage from @Veii
The cpu is on pbo on +200 with no offset/curve optimizer or anything (all stock but pbo +200)
To my problem: cpu and ram look stable at 3800c16/1900IF with no whea errors on hwinfo and it run tm5 anta777 for 12 hours and occt for 90 minutes with no errors, but, once a week or less i have a reboot due to whea error 18 "Error Type: Cache Hierarchy " (the Error Processor APIC ID: changes every time.)
It happened a few times while playing games, i tried to raise vsoc one step (from 1.0625 to 1.0750)hoping it would go away but today after 10 days it crashed again while playing dragon quest 11.
I am not an expert, i just read this forum and try in my spare time, i would just raise all voltages a bit until it works but it's likely not gonna work and a waste of time so i hope anyone has any idea what i could change to make this 99% stable settings a 100% stable config.
I attach my zentimings, ram voltage is 1.40v, vsoc in zentimings is lower than what i input in my bios, (in this case the input on bios was 1.0625).
(those are the original i input before raising , unsuccesfully, vsoc one step to 1.0750)


----------



## seamonkeyhd

biggbosss said:


> Hi, i want some help resolving a rare but annoying whea error problem i have.
> I have a 5600x, a b450 a-pro, a flarex 3200c14 b die kit 16gb, single rank.
> I copied the ram settings from this post in this thread AMD max overclocking voltage from @Veii
> The cpu is on pbo on +200 with no offset/curve optimizer or anything (all stock but pbo +200)
> To my problem: cpu and ram look stable at 3800c16/1900IF with no whea errors on hwinfo and it run tm5 anta777 for 12 hours and occt for 90 minutes with no errors, but, once a week or less i have a reboot due to whea error 18 "Error Type: Cache Hierarchy Error Processor APIC ID: 8".
> It happened a few times while playing games, i tried to raise vsoc one step (from 1.0625 to 1.0750)hoping it would go away but today after 10 days it crashed again while playing dragon quest 11.
> I am not an expert, i just read this forum and try in my spare time, i would just raise all voltages a bit until it works but it's likely not gonna work and a waste of time so i hope anyone has any idea what could i change to make this 99% stable settings a 100% stable config.
> I attach my zentimings, ram voltage is 1.40v, vsoc in zentimings is lower than what i input in my bios, (in this case the input on bios was 1.0625).
> (those are the original i input before raising , unsuccesfully, vsoc one step to 1.0750)
> View attachment 2518865


Do you have core optimizer set up? your core 4 (apic id 8) seems like it needs more juice.

edit: sorry, I missed the part where u mentioned u didn’t have curve optimizer. Anyways, I got that error before when I was working on my curve and one of the cores could not handle the negative offset.


----------



## Audioboxer

On the hunt for some new b-die this time, no Amazon deals. All these marginal bin differences are driving me a bit nutty. What would be best ranked out of this lot for potential if all priced similarly?

F4-4000C16D-32GTRS (16-19-19-39) 1.40v
F4-3600C14D-32GTRS (14-15-15-35) 1.45v
F4-4266C17D-32GTZRB (17-18-18-38) 1.50v
F4-4000C16D-32GTZR (16-19-19-39) 1.40v

Aim is to run 3800 at best timings possible.


----------



## biggbosss

seamonkeyhd said:


> Do you have core optimizer set up? your core 4 (apic id 8) seems like it needs more juice.
> 
> edit: sorry, I missed the part where u mentioned u didn’t have curve optimizer. Anyways, I got that error before when I was working on my curve and one of the cores could not handle the negative offset.


thanks, that's why i am surprised by this error,after a night of tm5 i was sure it was gonna be all fine and then boom the first reboot, i copied everything from veii becuse he always knows what he's doing, maybe he has an idea


----------



## PJVol

biggbosss said:


> has any idea what i could change


The quickest you can try is to lower your boost override value by a step or two.
-----------------

As for the reasons, why it happens...
It probably not as simple as it may seem to.
My simplified idea of WTFU is that voltage supply can't keep up with that of requested by boosted p-states for some reason,
be it agesa bug, or something more severe, and have a strong belief, those shouldn't be requested at all.


----------



## biggbosss

i tried "for fun" to lower vsoc rather than raise it this time, from 1.0625 (my first value) to 1.0500 (what i think veii suggested to input in the bios in the first place in that post)
pc froze on chrome after one hour, could be a coincidence but i guess i am gonna try and raise vsoc to 1.0875 and see what happens)
Trying to lower or remove pbo is also a good idea (i honestly thought pbo was always going to be stable because it just followed the stock voltage/frequency curve but maybe i was wrong)


PJVol said:


> The quickest you can try is to lower your boost override value by a step or two.
> -----------------
> 
> As for the reasons, why it happens...
> It probably not as simple as it may seem to.
> My simplified idea of WTFU is that voltage supply can't keep up with that of requested by boosted p-states for some reason,
> be it agesa bug, or something more severe, and have a strong belief, those shouldn't be requested.


----------



## gled_fr

mongoled said:


> Just putting this here as this is new to you (and probably many others) but trust me its nothing new and yes its "weird"
> 
> First screen shot is not using Manni-ITX WHEA 19 "suppressor"
> 
> 2nd screenshot is ...
> 
> View attachment 2518810
> View attachment 2518811


Thank you,

I was starting to suspect those errors are either bugs, or something not really important... I'll do more stability testing above IF1900, but it seems like Manni-ITX suppressor is gonna get here too..


----------



## gled_fr

Audioboxer said:


> On the hunt for some new b-die this time, no Amazon deals. All these marginal bin differences are driving me a bit nutty. What would be best ranked out of this lot for potential if all priced similarly?
> 
> F4-4000C16D-32GTRS (16-19-19-39) 1.40v
> F4-3600C14D-32GTRS (14-15-15-35) 1.45v
> F4-4266C17D-32GTZRB (17-18-18-38) 1.50v
> F4-4000C16D-32GTZR (16-19-19-39) 1.40v
> 
> Aim is to run 3800 at best timings possible.


I have the F4-3600C14D-32GTZN (14-15-15-35) 1.45v, got them at 15 flat, 55ns 3800Mhz. I am sure I can optimize that a bit more, and go down to cl14 without too much trouble. First try at flat 14's I was putting 1.5V and some errors. I am sure could run lower vdimm with different resistances.
You saw the current results in the previous screenshots 

They boot fine at 4000 too.

I would suspect though that the F4-4000C16D at 1.4V would be a better bin.


----------



## XPEHOPE3

PJVol said:


> the difference is reproducible(just 8 vs 15):


Do you attribute L2 difference to tRCDWR or to run-to-run variance? What about L3?


----------



## Veii

XPEHOPE3 said:


> It was @PJVol who asked about tRCDWR here
> 
> 
> PJVol said:
> 
> 
> 
> Yeah, it was me who asked about the tRCDWR influence on memory performance in this post
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> which was left unnoticed.
> 
> As for the reasons behind my interest, here are some tests I ran to make sure the difference is reproducible(just 8 vs 15):
Click to expand...

Far too many pings a day, let alone connected by "days". Forgot who to ping (not unhappy, but don't be mad about me on such)
It wasn't unnoticed, as you could read that i tested a lot of things and needed time to confirm or deny
Many messages are on backtrack and i have a good memory - just slightly overwhelmed by remembering names ~ yet not the content. No message is missed intentionally and all are read. Even if i respond after 4-7 days (up to question type or difficulty of request)

Same, kind of
I can notice it does something, but i can not notice it being anyhow useful
Can not fully confirm it helps lowering tRP , or it remains a voltage thing with blinded by the "expected result" of doing something
Yet always tCL,tRCD, tRP being flat and identical - lead to the best performance ~ compared to these odd sets
It's unclear



XPEHOPE3 said:


> Here's mine screenshot of 2CDD 5600x
> View attachment 2518859


Yes as i thought
FCLK DPM, normal DPM LCLK (tho a flag) , and GMI links are doing something on your side
They are broken for me (powermanagement)

But yours are active for some reason
How does core layout look like ?
LCLK PCH & PCIe do nothing, but that can be also just lack of PCIe 4.0 device
I haven't seen a unit where it also is broken like for me ~ but i need to verify it with the ASUS board ttoo. Still have SPI & downgrade experiments on it to do after i find a GPU & able to get some thermal paste
Tho i think it didn't function there either, and was sample exclusive

@kim nk can you do me a favor on your dual CCD or single CCD unit , run Tool.exe





Tool1007.zip







drive.google.com




VermeerPM and report back how LCLK and DPM flags behave for you ?
If they are active or fully broken (DPM & GMI links)


----------



## gled_fr

Very interesting that IF1933+ does not post at cldo_vddp 0.9, but post fine at 0.880.

Still a ton of work to do to stabilize that. IF2000 is error 6 land for now, and a few different ones on if1966 as you can see. I wonder if I should up the VDIMM from 1.45 to a bit higher...

I'll do some stabilization first, then disable whea 19 I guess...


----------



## XPEHOPE3

Blameless said:


> At the settings I was using above, below 840mV one or both channels is virtually always 28. From 850-860 it can go either way. 870mV and up is always 26.


I confirm. I tried going tRRD_S/tFAW from 5/20 to 4/16. tPHYRDL would only train to 26/30 until I move VDDP from 880mv to 900mv. Then it trains to 26/26


----------



## Audioboxer

gled_fr said:


> I have the F4-3600C14D-32GTZN (14-15-15-35) 1.45v, got them at 15 flat, 55ns 3800Mhz. I am sure I can optimize that a bit more, and go down to cl14 without too much trouble. First try at flat 14's I was putting 1.5V and some errors. I am sure could run lower vdimm with different resistances.
> You saw the current results in the previous screenshots
> 
> They boot fine at 4000 too.
> 
> I would suspect though that the F4-4000C16D at 1.4V would be a better bin.


Okay, F4-3600C14D-32GTZRA, 3600MHz CL14-14-14-34 1.45V, is around the same price as well. How does that compare to F4-4000C16D-32GTRSA at DDR4-4000MHz CL16-16-16-36 1.40V.

I actually meant to post F4-4000C16D-32GTRSA above but copied some wrong data. Seems like 4000 straight 16s at 1.40v should be a better bin, but I guess it's understandable a straight 14 bin needs to run at 1.45v even at 3600.


----------



## KedarWolf

Audioboxer said:


> On the hunt for some new b-die this time, no Amazon deals. All these marginal bin differences are driving me a bit nutty. What would be best ranked out of this lot for potential if all priced similarly?
> 
> F4-4000C16D-32GTRS (16-19-19-39) 1.40v
> F4-3600C14D-32GTRS (14-15-15-35) 1.45v
> F4-4266C17D-32GTZRB (17-18-18-38) 1.50v
> F4-4000C16D-32GTZR (16-19-19-39) 1.40v
> 
> Aim is to run 3800 at best timings possible.


if money is no object, check out the new Royal Elite 3600 CL14, it's really good.


----------



## gled_fr

Audioboxer said:


> Okay, F4-3600C14D-32GTZRA, 3600MHz CL14-14-14-34 1.45V, is around the same price as well. How does that compare to F4-4000C16D-32GTRSA at DDR4-4000MHz CL16-16-16-36 1.40V.
> 
> I actually meant to post F4-4000C16D-32GTRSA above but copied some wrong data. Seems like 4000 straight 16s at 1.40v should be a better bin, but I guess it's understandable a straight 14 bin needs to run at 1.45v even at 3600.


I would still think, but I am no expert, that the [email protected] is better than the [email protected]

With my F4-3600C14D-32GTZN (14-15-15-35) 1.45v I am having the hardest time atm going to CL14, even at 3800. Stable settings, but just changing to cl14 everything becomes a nightmare of instability ( up to the point of windows not booting ).

_Fun fact: I do often know now if a test is going to be unstable or not if the screen flickers a bit ( go to black for 300ms ish then come back ), before tm5 tells me what's wrong _


----------



## KedarWolf

gled_fr said:


> I would still think, but I am no expert, that the [email protected] is better than the [email protected]
> 
> With my F4-3600C14D-32GTZN (14-15-15-35) 1.45v I am having the hardest time atm going to CL14, even at 3800. Stable settings, but just changing to cl14 everything becomes a nightmare of instability ( up to the point of windows not booting ).
> 24-14-24-24
> _Fun fact: I do often know now if a test is going to be unstable or not if the screen flickers a bit ( go to b regularlack for 300ms ish then come back ), before tm5 tells me what's wrong _


I think the Elite is 3600 14-14-14 but it depends on your IMC, most peeps on 2x16GB getting 14-16-8-14 or 14-15-8-14 at 3800 MHz at best even with the regular CL14 3600 kit.


----------



## Audioboxer

gled_fr said:


> I would still think, but I am no expert, that the [email protected] is better than the [email protected]
> 
> With my F4-3600C14D-32GTZN (14-15-15-35) 1.45v I am having the hardest time atm going to CL14, even at 3800. Stable settings, but just changing to cl14 everything becomes a nightmare of instability ( up to the point of windows not booting ).
> 
> _Fun fact: I do often know now if a test is going to be unstable or not if the screen flickers a bit ( go to black for 300ms ish then come back ), before tm5 tells me what's wrong _


Yeah I'm looking at the 4000 straight 16s. I've got another massive issue to sort first though, I swear I have no luck at the moment. Using PC before bed and boom, black screen. PC hadn't restarted or anything just lost display. So I restarted it and now I have bios error code d6. Can't get any display, even after a CMOS reset.

I'm using a riser cable so I hope it's just died on me or something and it's not my graphics card that's given in. Don't have time to troubleshoot tonight but I swear I'm gonna be mad if I have to drain this loop again.

There isn't actually too much online about error code d6. No idea what's gonna happen if my card is dead, its in the EVGA step up queue for a 3080 🤦‍♂️


----------



## gled_fr

Audioboxer said:


> Yeah I'm looking at the 4000 straight 16s. I've got another massive issue to sort first though, I swear I have no luck at the moment. Using PC before bed and boom, black screen. PC hadn't restarted or anything just lost display. So I restarted it and now I have bios error code d6. Can't get any display, even after a CMOS reset.
> 
> I'm using a riser cable so I hope it's just died on me or something and it's not my graphics card that's given in. Don't have time to troubleshoot tonight but I swear I'm gonna be mad if I have to drain this loop again.
> 
> There isn't actually too much online about error code d6. No idea what's gonna happen if my card is dead, its in the EVGA step up queue for a 3080 🤦‍♂️


you sure you have a stable power supply or no leaks in your loop ?


----------



## Audioboxer

gled_fr said:


> you sure you have a stable power supply or no leaks in your loop ?


Power supply is an Asus Thor 850, seems to be OK. No leaks.

It's a phanteks riser mount so possibly not the best quality, but it has been running for like almost a year now. Still, a different board with a riser cable and I guess there might be new issues.

Considering I went X570 to B550 one thing I hadn't considered is by default does the CPU handle the PCIE Lane for graphics? If so it could possible mean an issue with my CPU... Hope not. I'll do some troubleshooting tomorrow. Fingers crossed its the riser cable.


----------



## element229

I got my 5900x running at 2000 FCLK. The latency and performance on single core is WORSE than 3800.

I found one major cause of my WHEA Errors Bus/Interconnect. IT CAN ABSOLUTELY BE SUBTIMINGS. All I had to do to boot at 2000 and eliminate the WHEA errors was loosen my subtimings. (And obviously I had to loosen my primaries a little). The solution seems to be: tRDRDSCL & tWRWRSCL from 4 to 5. tRDWR from 10 to 12. tWRRD from 1 to 2 (or even 3). tRDRDSD from 4 to 6, tRDRDDD from 3 to 5. tWRWRSD from 6 to 8. tWRWRDD from 5 to 7. tCKE from 6 to 8. vDIMM increase by .4v. ClkDrvStr, AddCmdDrvStr, CsODTDrvStr, CkeDrvStr from 24-20-24-24 to 30-24-24-24. 

So, all the people struggling for stability... If you haven't increased your subtimings juuust right, you might want to try again. Every one of those memory settings needs to be good. And your TWR & tCWL cannot be too low.

Also, if you're struggling with a high tRCDRD, then for the love of god, try a higher tCL like C16 and lower your tRCDRD. You might be stuck because your subtimings are off, say for example, tRDWR might want 11 or 12...

Side note: Seamonkey you need to set tWRWRSD should be higher than tWRWRDD. 

PS - With two CCDs, Ryzen 5000 series, don't be scared of pushing 1.2v soc, 1.0v VDDP, 1.1v ccd, 1.5v iod.


----------



## XPEHOPE3

Veii said:


> You guys should give tWRWR & tRDRD ~ DD's 2 or 1 a try


Usually when it's hard to post for my PC it attempts posting two times, and the third time is always the charm -- it just boots to JEDEC. However as soon as I set any of SD/DD to 3 or 2 (didn't check 1), my PC just keeps trying to post! It might take 10+ attempts before it finally resorts to JEDEC. One time it was just stuck during one of the posts, but cold boot let it proceed trying.


----------



## PJVol

XPEHOPE3 said:


> Do you attribute L2 difference to tRCDWR or to run-to-run variance? What about L3?


Yes, L3 copy tend to deviate most, though regardless of timings used. As for L2, don't think it worth any attention.


----------



## XPEHOPE3

Audioboxer said:


> I'm using a riser cable


Well, do you recognize the fact that it could have killed your previous board and starts to kill this one? They might be evil and even burn.
Also they can have limited amount of times it can be reseated in the PCI-e slot


----------



## Comalive

element229 said:


> I got my 5900x running at 2000 FCLK. The latency and performance on single core is WORSE than 3800.
> 
> I found one major cause of my WHEA Errors Bus/Interconnect. IT CAN ABSOLUTELY BE SUBTIMINGS. All I had to do to boot at 2000 and eliminate the WHEA errors was loosen my subtimings. (And obviously I had to loosen my primaries a little). The solution seems to be: tRDRDSCL & tWRWRSCL from 4 to 5. tRDWR from 10 to 12. tWRRD from 1 to 2 (or even 3). tRDRDSD from 4 to 6, tRDRDDD from 3 to 5. tWRWRSD from 6 to 8. tWRWRDD from 5 to 7. tCKE from 6 to 8. vDIMM increase by .4v. ClkDrvStr, AddCmdDrvStr, CsODTDrvStr, CkeDrvStr from 24-20-24-24 to 30-24-24-24.
> 
> So, all the people struggling for stability... If you haven't increased your subtimings juuust right, you might want to try again. Every one of those memory settings needs to be good. And your TWR & tCWL cannot be too low.
> 
> Also, if you're struggling with a high tRCDRD, then for the love of god, try a higher tCL like C16 and lower your tRCDRD. You might be stuck because your subtimings are off, say for example, tRDWR might want 11 or 12...
> 
> Side note: Seamonkey you need to set tWRWRSD should be higher than tWRWRDD.
> 
> PS - With two CCDs, Ryzen 5000 series, don't be scared of pushing 1.2v soc, 1.0v VDDP, 1.1v ccd, 1.5v iod.


For me memory settings seem to be irrelevant. I can reset BIOS to factory settings and set fclk to 2000 as the only change; that is enough to cause the WHEA 19 spam.


----------



## Audioboxer

XPEHOPE3 said:


> Well, do you recognize the fact that it could have killed your previous board and starts to kill this one? They might be evil and even burn.
> Also they can have limited amount of times it can be reseated in the PCI-e slot


That looks like a NZXT issue more than anything, I've got a phanteks mount inside a Lian Li O11 XL. As I said I'll try tomorrow without it. If it works I'll redo my piping with it horizontal. With the sheer weight if the GPU block it'll need some support though lol.


----------



## gled_fr

Previous stable ( I did test trp 16, tras 24 and trc 30 as stable too, but do not have the screenshot ):








Still trying to finalize my IF1900 timings and a few stupid questions:

if I lower tCL or tRCDRD to 14, it's error 6 land, even after upping the vdimm to 1.47 from 1.45, any ideas ?
if I try twr 10 trrdl 4 and trdrdscl 2 and twrwrscl 2, it seems stable but I get some screen flicker, which tells me it is not stable and won't pass an overnight test, any ideas ?
currently trying the following settings below, is it really too low SCLs ?
from the settings below, trtp 8 throws errors 6 0 0 13, so scl and voltage ?











A bit lost now 

[edit] testing above but with trp 16 trc 40 and trtp 8 to see if it makes a difference. 30mn so far without an error, and no screen flicker, but who knows, still 2h to complete 25 tm5 cycles.


----------



## gled_fr

gled_fr said:


> Previous stable ( I did test trp 16, tras 24 and trc 30 as stable too, but do not have the screenshot ):
> View attachment 2518966
> 
> 
> Still trying to finalize my IF1900 timings and a few stupid questions:
> 
> if I lower tCL or tRCDRD to 14, it's error 6 land, even after upping the vdimm to 1.47 from 1.45, any ideas ?
> if I try twr 10 trrdl 4 and trdrdscl 2 and twrwrscl 2, it seems stable but I get some screen flicker, which tells me it is not stable and won't pass an overnight test, any ideas ?
> currently trying the following settings below, is it really too low SCLs ?
> from the settings below, trtp 8 throws errors 6 0 0 13, so scl and voltage ?
> 
> View attachment 2518964
> 
> 
> 
> 
> A bit lost now
> 
> [edit] testing above but with trp 16 trc 40 and trtp 8 to see if it makes a difference. 30mn so far without an error, and no screen flicker, but who knows, still 2h to complete 25 tm5 cycles.


And seems like another stable set found:








now to try again tcl or trcdrd or trp 14...


----------



## Dudelll

Hi guys, i hope someone might be able to clarify some missconceptions i have regarding the RTT values.

I understand those values are termination resistances that can be changed to minimize reflections in the signal the dram chip receives or sends and i suppose those resistances are in parallel to ground?

I've seen quite often that some settings might be considered dangerous in combination with high voltages e.g. 1.6V and 0-0-5 (Nom, WR, Park) but i dont exactly get why this combination might be potentially unsafe.

From a basic view onto this, which might be where i am completly wrong, i would assume that low resistances will lead to higher current flow and thus might damage the chip, which would be in agreement with rtt Park at 5 beeing unsafe due to the low resistance this imposes.

However this makes no sense with rtt nom = 7 considered safe, so i guess i am missing something here.

Additionally what exactly is the consequence of disabling one of those values, will this be more or less dangerous than a high or low resistance value?

Sorry if this was explained already in detail elsewhere i just read through the last 50 pages but found no real answer aside from overall recommodations for certain values.


----------



## Audioboxer

XPEHOPE3 said:


> Well, do you recognize the fact that it could have killed your previous board and starts to kill this one? They might be evil and even burn.
> Also they can have limited amount of times it can be reseated in the PCI-e slot


Just tried with the graphics card directly plugged in, still getting D6.

I know this is the totally wrong topic to ask this but am I correct to assume with motherboard error codes VGA/display is one of the last things it cycles through? Just trying to narrow down if it could be the CPU. Doesn't seem to be, but I took it out, checked pins and reseated it anyway.

I've sent a ticket to EVGA, on the assumption my graphics card has kicked the bucket. What a horrible couple of weeks for me! lol


----------



## Mach3.2

Audioboxer said:


> Just tried with the graphics card directly plugged in, still getting D6.
> 
> I know this is the totally wrong topic to ask this but am I correct to assume with motherboard error codes VGA/display is one of the last things it cycles through? Just trying to narrow down if it could be the CPU. Doesn't seem to be, but I took it out, checked pins and reseated it anyway.
> 
> I've sent a ticket to EVGA, on the assumption my graphics card has kicked the bucket. What a horrible couple of weeks for me! lol


On my MSI X570 Tomahawk it cycles in this order: CPU > DRAM > VGA > BOOT device

Should be the same order for your board too.


----------



## mongoled

Audioboxer said:


> Just tried with the graphics card directly plugged in, still getting D6.
> 
> I know this is the totally wrong topic to ask this but am I correct to assume with motherboard error codes VGA/display is one of the last things it cycles through? Just trying to narrow down if it could be the CPU. Doesn't seem to be, but I took it out, checked pins and reseated it anyway.
> 
> I've sent a ticket to EVGA, on the assumption my graphics card has kicked the bucket. What a horrible couple of weeks for me! lol


D6 points to no display output.

Check your power connections.

Try different gfx card output, i.e. if you are using DP switch to HDMI etc.

Have you made it into the BIOS at all ?

Check its not defaulted to CSM mode ?


----------



## mongoled

In such situation it would be

Set mothrboard on cardboard box outside of case.

Connect 1 stick of RAM

Connect PSU cables

Connect VGA

Then try to post

IF the error remains, swithc VGA to different PCIe slot

Test again ...


----------



## Audioboxer

mongoled said:


> D6 points to no display output.
> 
> Check your power connections.
> 
> Try different gfx card output, i.e. if you are using DP switch to HDMI etc.
> 
> Have you made it into the BIOS at all ?
> 
> Check its not defaulted to CSM mode ?


Yeah I've changed power connections. I even reassembled my graphics card with its old fan (removed watercooling block). The fan and led is powering. Tried HDMI and DP.

The way it cut off to a black screen last night when browsing the web makes me think it's the graphics card. But I'm a bit worried if it's the PCIE slot and/or CPU controlling the PCIE slot. That's why I asked about the BIOS cycling through CPU/RAM first.

Will likely just RMA the card to EVGA and see if they find anything.


----------



## mongoled

Could also be the "dodgy" motherboard you purchased

🤣 😀😍


----------



## Audioboxer

mongoled said:


> Could also be the "dodgy" motherboard you purchased
> 
> 🤣 😀😍


I tried the second PCIE slot on the board and still not working, though IIRC that second slot is limited in speed/power.

I'm thinking with the other board dying and something going wrong here after it was working fine its one of my components. Only really narrows it down to CPU or GPU.

My 2080Ti has always been noisy, but apparently that is just coil whine. No coil whine now 🤣


----------



## Audioboxer

LOL, one of my best friends who lives nearby pretty much told me NO when I asked if they could test my card in their PC (watercooled as well, so the hassle of draining). Might be able to hassle a family member later.

But anyway, the funny bit, I found this digging through old boxes










No idea where it came from, don't think I've ever used it. Possibly taken out of a family members PC at some point long ago. I think its some sort of really old Nvidia card lol.

DVI only, but I hooked it up to an old monitor I have and it cleared the D6 code but landed on 02 at the boot stage. Which I'm not too bothered about, it's likely a handshake issue with such an old card not being compatible. 02 online has quite a few people say they had to boot with HDMI first, then setup the bios properly then switch to DP. 

So it seems my 2080Ti is infact, dead. EVGA are accepting an RMA which is good.

Sorry for taking this topic, offtopic, but my adventures continue! One of these days I'll just get back to memory testing...


----------



## spajdr

Mach3.2 said:


> [Guide] - RAM Timings und deren Einfluss auf Spiele und Anwendungen (AMD) - Update 23.05.2020
> 
> 
> RAM Timings und deren Einfluss auf Spiele und Anwendungen Testsystem | Aida64 Benchmark | Konvertieren und Rendern | Spiele Benchmark | RAM Takt vs Timings | Zusammenfassung Einleitung In diversen Tests wurde bereits festgestellt, dass durch das Optimieren von RAM Timings die Leistung...
> 
> 
> 
> 
> www.hardwareluxx.de
> 
> 
> 
> 
> 
> He only talked about avg fps, but there should also be inprovements in the 0.1% fps.


So I did some tests and basically there is 0% improvements in min. fps in one of the tested game (SOTTR).
That was 15-16-16-16 3000Mhz vs 15-20-10-14 3933Mhz. Tried to change other secondary timings but also no difference.
So all that tweaking seems to go nowhere :-/


----------



## Veii

Dudelll said:


> However this makes no sense with rtt nom = 7 considered safe, so i guess i am missing something here.


They are Termination Impedances. They are used as resistances , soo your first theory was right
But on their nature, they are impedances - and depend on what you feed into them (VDIMM, cLDO_VDDP, procODT & CAD_BUS values)

Because impedances are multipliers, a weaker value is always less harsh
On RTTs part, they are annoying - slightly.
RTTs function as gates, you can imagine rubber gates that reflect well. Or metal walls for an audio based overview

A sinus curve signal (how ever it's strength and travel distance was generated ~ by the above mentioned factors)
= CKE, needs to move up and down in a constant flow motion.
The distance between these reflections - is the "data eye".
The "data-eye" can define "the noise threshold" , "the range of signal size & strength" (wideness), and the jitter/ripple (see PSU testing for a great illustration)

The data-eye size, is measured as a little box (left, right distance and height headroom)
On PCB design process trance lengths are timed and curved (slowed down) to match the memory controller send out signal strength & both channels functioning at the same time IO-L's & tPHY values
Traces get also curved to increase resistance, but that's a more extended topic for a little post.

A good data-eye needs to have perfectly stacked thin CKE signals with as little as possible deviation.


Spoiler: Illustrations:












^ high frequency with bad RTT_NOM & cut off-times. Bad ceiling and too random








^ different filter, more dense and cleaner ~ yet too random
Centric missmatched








^ In theory good intention with followed specs, but with screwed up PCB traces ~ signals do not arrive in constant matter. Not a powering but PCB design issue








^ lecture illustration on how to read it








^ technically better crosspoint and technically better/bigger data-eye
But with issues on RTT_PARK (floor) and RTT_NOM (ceiling) , being too noisy. PARK looking better on the right side, yet top having a potential to reflect back once signal get's stronger and so wider











And this is how (right) a clean data-eye can look, especially focusing on the ceiling part and "size" of the little "tunnel"
Which is exactly where the RTT's come into play - shaping it
Dynamic ODT = RTT_WR

Let me drop you couple of "easier to follow" and a "needs translation" based guide ~ although i strongly try to keep this post as short as possible
The Secrets of PC Memory: Part 3 | bit-tech.net ~ 1
The Secrets of PC Memory: Part 3 | bit-tech.net ~2
The Secrets of PC Memory: Part 3 | bit-tech.net ~ 3
DDR4 设计概述以及分析仿真案例_信号 ~ technical

In general, Unlike Intel where boardpartners actively tune their boards by themself and so memory OC capabilities vary between boards
AMD does take the Sun Tsu Leader approach ~ and enforces boardpartners to follow their in house defined specifications
Board Engineers continue to refine their trace design , placement & now EVGA does take over 2 of these parts ~ where one belongs to AMD
Yet all of them focus 100% on following given drive specifications & designing their boards modular.
Pretty much resulting in close to every board overclocking memory identical , with little caveats. ~ soo also why a fully open AMD CBS is very important.

The post contained more self-learning than answers,
But in general , it's a balancing thing
VTT MEM (not every board has this)
CPU VDDP and cLDO_VDDP (not every board has both)
The type of memory training, their extend and their "snooping method"
All of this plays a role in which settings you should pick

If i have to write a book about how i go onto things, it rather would be a season based movie ~ as books lack illustration and documentation is frustrating with the lack of tools we have
Remember that you don't want a signal to reflect back . Soo you don't want your walls/gates on RTT , to be set too strong = too tight
Keep in mind that while i mentioned DQs , RZQ, procODT and CAD_BUS behavior changed since SMU 56.50 ~ there where also more options introduced with an IMC FW update (tFAW behavior for example)
Note for yourself that high VDIMM does not mean "high arriving amperage" on the dimms - and stronger RTT's do increase thermals more.

At the end, what you pick depends on the PCB you run (DIMM) and the voltage tolerances it has
(mine clearly fails at 1.68v, but is perfectly fine on 1.66v @ 737 or 1.65v @ 736 ~ in a hot summer day)
It's a too open question. But generally you want to remember how Ohm's Law functions, and remember/learn how Data-Eyes looks
Experiment that ClkDrvStr does function as strength multiplier.
Remember that Signal Integrity is key on everything & low procODT is very important.
Don't forget that VDIMM is not the creator of high arriving Amperage & also that powerdown here plays an important resource in how thermals are defined ~ yet all are MCLK dependent.
=================================================================
Soo this seems so far the fastest TM5 run i had ~ Win 22000.100 fresh install
CPU seems slightly slower than usual (LinX) ~ but this could be because i haven't disabled WinDef, Antivirus, Security Center and stuff, yet
Guess it averages out, but the Bandwidth increase is a new PB 

1.65vDIMM ~ yet cozy on 30c Room & outdoor-temp
_* who says you should not daily more than 1.5v _















Might try to improve it a slight bit (voltage hardwall ~ A0 PCB reason) , but lazy me should finally face 2133 FCLK
This 47.7ns run is mocking me 🤭
I'd also really like to play with A3 PCB Dimm's - don't have any nearby


----------



## byDenoso

Nem stable settings with fixed voltages (on VDDP and VDDG)
I've found than 3666mhz with tRP17 give me less performance than 3733 with tRP 18, now trying to get tRP17 stable again.


----------



## Veii

byDenoso said:


> View attachment 2519015
> 
> 
> Nem stable settings with fixed voltages (on VDDP and VDDG)
> I've found than 3666mhz with tRP17 give me less performance than 3733 with tRP 18, now trying to get tRP17 stable again.


Will tWRRD 5 work for you ?
tRC is 1 too low - it can keep up stability, but then it would need to be 40 or 41. Soo 58 or 41 , pick one
tRRD_L is low, match it with tRTP if you want to run it as low as possible (yet it makes sense to compensate there and lower primaries)

Rest looks ok.
You can try the DD's bandwidth "trick" and put them both to the lowest setting you can select ~ but doing it, is makes stabilizing harder 
I'd run tRP 20 with this and not bother at all with odd sets
Well or focus to drop tRCD further (tRCD 19, tRP 19, tRAS 38, tRC 57)


----------



## byDenoso

Veii said:


> Will tWRRD 5 work for you ?
> tRC is 1 too low - it can keep up stability, but then it would need to be 40 or 41. Soo 58 or 41 , pick one
> tRRD_L is low, match it with tRTP if you want to run it as low as possible (yet it makes sense to compensate there and lower primaries)
> 
> Rest looks ok.
> You can try the DD's bandwidth "trick" and put them both to the lowest setting you can select ~ but doing it, is makes stabilizing harder
> I'd run tRP 20 with this and not bother at all with odd sets
> Well or focus to drop tRCD further (tRCD 19, tRP 19, tRAS 38, tRC 57)












Actually i've drop tCL because i was getting error 6 (too low vDIMMs because the 1,5v of my b450 board) and loosened subs.
I get a Big increase in stability with tFAW > 7*RDDS and tRTP = RDDS + WTRS.
i'll take a Nap and when i wake up i'll se if i get some error, if it pass, i'll deal with subtimings until it get unstable.

Oh, i almost forgot...i get better Read with memory interleaving size in 256kb and better copy with 512kb, i just don't know why.
I spend the night adjusting my VDDG/VDDP voltages until it stops throttling (no more iddle reboots with low VDDG_IOD). And increasing VDDP actually gave me better performance than the "default" (900mv).


----------



## Veii

Bit better, but still bloaty install ~ can't hold 33599 write yet, something eats bit too much RAM on idle
v22000.100 with MS Teams just got far more annoying after wiping any MS-Edge traces


byDenoso said:


> I get a Big increase in stability with tFAW > 7*RDDS and tRTP = RDDS + WTRS.


This is because tFAW get's suspended (killed and repeated) if it is too low or memory does nothing till tFAW elapses
Same for tRC and tRFC (tRFC get's suspended and doubled up to 9x inside tREFI range, if tRFC is too low)
tRTP you can do by many reasons, but i don't think you need to get it that low. Well it's fine soo why not
But tRDD_L you want to match with tRTP , at least try so.

Generally increasing both tRRD and tWTR will help, everyone too many people push them soo low and later complain that they can not lower primaries at all
This taxes soo much the PCB, and requires low voltage. They give big perf but _L ones should be higher than usual. _S ones are a balancing thing with SD, DDs


byDenoso said:


> Actually i've drop tCL because i was getting error 6 (too low vDIMMs because the 1,5v of my b450 board) and loosened subs.


You gain more voltage headroom with higher tRRD, tWTR and tWR
See me running 20ns more tRFC and far higher tWR 
I have non left either / was fun till 1.66v.
tCL will either post and accept the voltage or fully refuse to post (then it was clearly not enough)


byDenoso said:


> I spend the night adjusting my VDDG/VDDP voltages until it stops throttling (no more iddle reboots with low VDDG_IOD). And increasing VDDP actually gave me better performance than the "default" (900mv).


Good job ! 
Rest well o/


----------



## mongoled

Audioboxer said:


> LOL, one of my best friends who lives nearby pretty much told me NO when I asked if they could test my card in their PC (watercooled as well, so the hassle of draining). Might be able to hassle a family member later.
> 
> But anyway, the funny bit, I found this digging through old boxes
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> No idea where it came from, don't think I've ever used it. Possibly taken out of a family members PC at some point long ago. I think its some sort of really old Nvidia card lol.
> 
> DVI only, but I hooked it up to an old monitor I have and it cleared the D6 code but landed on 02 at the boot stage. Which I'm not too bothered about, it's likely a handshake issue with such an old card not being compatible. 02 online has quite a few people say they had to boot with HDMI first, then setup the bios properly then switch to DP.
> 
> So it seems my 2080Ti is infact, dead. EVGA are accepting an RMA which is good.
> 
> Sorry for taking this topic, offtopic, but my adventures continue! One of these days I'll just get back to memory testing...


Im sure you are wracking your brains working out what the cause of all this malaki is! 

Will probably work in CSM mode...


----------



## Dudelll

Veii said:


> They are Termination Impedances. They are used as resistances , soo your first theory was right
> But on their nature, they are impedances - and depend on what you feed into them (VDIMM, cLDO_VDDP, procODT & CAD_BUS values) [...]


Now this is what i call an answer. Thank you very much, guess i need some time to go through the additional information you provided but this will be very helpful for sure.


----------



## Veii

Dudelll said:


> Now this is what i call an answer. Thank you very much, guess i need some time to go through the additional information you provided but this will be very helpful for sure.


They are confusing, because of their behavior
I'm sorry that i can not provide you a more "technical" answer
Can only help with what to run and why it won't run - but not fully why they misbehave. Too many factors

Remember the Ohm's law and work with it.
What arrives to the dimms, the Amperage is all it maters & the creation of heat
Traces on their own have fixed resistances and it is somewhere clear that ITX boards could potentially have less than ATX boards
Although i do feel that even ITX boards would be enforced to maintain the same trace "ripple & distance" - soo all boards do behave the same for global AGESA blobs

There are normally pretested Training values and a lot less than you can set up on for example a Z170 or Z470 board
You are dependent on AMD and their "hopefully stable" next SMU update - with who knows how many hidden changes 
But on the other hand, nearly every board behaves universal and research moves faster up.

What i wanted to say before,
PCB Makers which include DIMM PCB makers, already have tested a wide combination of Termination Impedances and finetune their gear
What you can select from, is what was already tested as "potentially functioning"
You don't have to do rocket science and be a PCB engineer. But what you should do, is stop trusting auto values and start to collect behavior data
My Rev.E's where completely different than my B-Die's ~ even when the PCB preconfigured termination-impedances (before RTT) where identical
The theory remained that:

You should give more RTT_NOM on higher VDIMM
Less RTT_PARK (weaker) else it can crash or even kill PCBs on too high input voltage
same goes for when you increase ClkDrvStr or procODT, less RTT_PARK else you might get #4 errors which are PCB crashes
See:
tRFC Calculator (mini) the TM5 Error description field

cLDO_VDDP remains to influence MCLK training behavior and FCLK has barely any influence with it. Close to zero
Testing high FCLK individually (fixing VDDG & procODT range) and later then upping MCLK ~ is a method you can try

Keep in mind, procODT will influence what arrives to the dimms, and RTT_WR (if you are able to jump down to /2) both /3 and /2 change how NOM (ceiling) and PARK (floor) behave
WR is needed in order to generate the lack on one of both, but WR is not needed to stabilize and build a top and floor Gate (RTT)
Then only the dimm capacity matters how strong PARK needs to be ~ and the dimm amount
EDIT:
WR is dynamic and will cause issues with misstimed CAD_BUS SETUP Timings, misstimed tCKE and generally badly timed powerdown ~ which all are MCLK depedend
WR is just a bonus, but powering has to function without it too.
Also GDM off 2T is to pick, which shows powering issues - GDM on does not show them, as the PCB internal MUX run at half speed & so is slower in general.
GDM off 2T and GDM on both do not require any VDIMM increase to stabilize equally. Only 1T is then something else


----------



## seamonkeyhd

Hi @Veii , I was hoping you can take a look at this.









Am I doing something wrong? I cannot get 4000/2000 WHEA free. These are 4 SR GSKILL Trident Z Neo 3600CL16 (16-16-16-36 1.35v) DIMMs. 3800/1900 does not show any WHEA at all.


----------



## Blameless

Veii said:


> Same for tRC and tRFC


Are you sure you don't mean tRAS and tRC? Those timings are windows that can get extended/repeated.



Veii said:


> (tRFC get's suspended and doubled up to 9x inside tREFI range, if tRFC is too low)


I don't think this is how tRFC works. Too low of a tRFC doesn't result in an extended refresh cycle, just an incomplete refresh or refresh recovery period...and often very abrupt instability.


----------



## XPEHOPE3

Veii said:


> Soo this seems so far the fastest TM5 run i had ~ Win 22000.100 fresh install


From my recent tests (also on 56.53, but on 4*16 DR) SD 4/6 give more bandwidth than 5/7 at no latency cost.


----------



## Veii

Blameless said:


> I don't think this is how tRFC works. Too low of a tRFC doesn't result in an extended refresh cycle, just an incomplete refresh or refresh recovery period...and often very abrupt instability.


To what i learned, tRFC will be repeated up to 9 times
Which is why i don't always run the lowest tRFC till it crashes
It's time window can be too short: Optimally it's shifted & repeated again, without a crash.
One of the reasons why people see no improvement with lower tRFC. Their starting point was already too low to begin with

Very sure on that part


Blameless said:


> Are you sure you don't mean tRAS and tRC? Those timings are windows that can get extended/repeated.
> I don't think this is how tRFC works. Too low of a tRFC doesn't result in an extended refresh cycle, just an incomplete refresh or refresh recovery period...and often very abrupt instability.


tRC is not "time-break" able to what i know
It always "has to elapse" and explains why it can hide missmatched timings.
A DRAM engineer here (been some time 5-7months) wrote a long article of how fascinating he still finds it that a little IC can have over 1.3 million little cells which all have to be able to run that timing window
It was a question about tRP+tRAS = tRC and why XMP often appears to be slightly higher and different.

I'm not sure if tRP can be time-broken, but tRC certainly can not
Yet between tRC as tRAS+1 or tRAS+tRP , there was an autocorrection and shifting happening.
tRAS+1 trick only worked if transition timings (tRRD, tWTR) where higher , tFAW was bursty 1x mode equal or smaller than tRRD_S & tRDWR had excessive wasted latency on it

Soo i'm not sure if tRC can not be repeated (if too short) - but i am sure it can not be time-broken and has to elapse.
Another reason why i picked it as anchor and trow away the old matching CAS latency idea for tRFC prediction. tRC was/is a fixed time window and can be used well for discharge prediction. Well i had reasons ^^'

tRAS entended, i am not sure
I have not read anywhere that they could be time-broken at all.
Maybe could get repeated if they are too short, but i haven't seen such behavior yet
Actually, maybe 
Maybe they can be time-broken if too long, but i haven't seen or read anything anywhere about this.
Nor experienced it myself while playing with couple tRAS formula's.
Lower tRAS always result in better performance when it's really stable
BZ's experience is the opposite. For him tRAS does nothing and only lower tRC increased performance consistently

tRC for my way of balancing (lower than tRP+tRAS) does close to nothing.
It only does something if i use tRCD_WR as exploit , or do another exploit for 1x tFAW mode. Oor a 3rd one which is focusing on half tBURST length & requires left charges from previous operation in the cells. Soo a recharge stacking method
(2 or 8gb dimms, 4 for dual rank ~ instead of 4 or 8)
Each of them functions but stability on them is hard to maintain.
Currently run the tRAS = tRCD+tRTP trick + tRTP = tRRD_L.
Later one might not be needed, but i try to get tWTR_S down to 2 stable like intel OCer do. Requires balancing with SD, DD's soo try-and-research progress.

Generally seen interesting behaviors and different timing balancing methods (soo i stopped following JEDEC, as there are far more than 1 method to get your timings balanced)
But haven't seen tRAS ever being time-broken nor tRC. Well tRC for sure haven't seen being time broken, tRAS could technically work as repeat ~ yet no idea about shortening it. Always wondered why tRAS can not go lower than 21 ~ when it should be possible to my C13-13 testing


seamonkeyhd said:


> Am I doing something wrong? I cannot get 4000/2000 WHEA free. These are 4 SR GSKILL Trident Z Neo 3600CL16 (16-16-16-36 1.35v) DIMMs. 3800/1900 does not show any WHEA at all.


It can be a lot
GDM enabled will hide powering issues - GDM off 2T should be your focus since the very beginning

WHEA Free unlikely, it either works or doesn't work
#19 are not FCLK or MCLK related , if you mean these

Did the board autopredict your tRDRD & tWRWR SD, DDs ?
They look messy, usually it's 1-4-4-1-6-6 or 1-4-3-1-6-5 (1-5-4-1-7-6 , but that one is actually worse ~ well it helps lower tRDWR -1 but for such there are better tricks out there)
DD usually is lower or equal to SD here. Higher nearly never unless misspredicted

Can you doublecheck and confirm that all your dimms have tPHYRDL 28 ?
If one is lower, it means that cLDO_VDDP is a bit weak for this MCLK and you should increase it slightly or decrease procODT once


XPEHOPE3 said:


> From my recent tests (also on 56.53, but on 4*16 DR) SD 4/6 give more bandwidth than 5/7 at no latency cost.


i wonder if 4x 16 wouldn't need 1-3-3-1-5-5
Higher capacity needed these lower to my tests
And lower values , at least on SD never gave performance but rather lost performance
Higher values resulted in better performance - except now for DD's

if i run 1-4-4-1-6-6 i "leave latency on the table" and lose performance
If i wanted to run something unstable and have balancing issues with tRRD & tWTR, i just "loosen" SD,DDs up to to 1-4-4-1-6-6 and that hides my misstimed timings

Been running before 1-6-6-1-9-9 but that only was possible when i relaxed tRRD and tWTR , in the case of lowered one value and broke the 2 stepping in between _S and _L
That usually gave more perf, but 1-5-5-1-7-7 if the set was fine, run better than 1-4-4-1-6-6 for 2x8
4 dimms always liked 1-4-4-1-6-6 more , soo for 16gb each, i wonder if 1-3-3-1-5-5 wouldn't even be better here


----------



## mongoled

Just like to add have also found that increasing CLDO_vDDP helps to keep tPHYRDL to a lower value


----------



## Audioboxer

mongoled said:


> Im sure you are wracking your brains working out what the cause of all this malaki is!
> 
> Will probably work in CSM mode...


I know, right? Part of me is wondering is it at all possible my graphics card has been the issue all along and it somehow "fried" my old mobo before kicking the can fully this time around? At the rate I'm going all I need to do now is replace the CPU and memory and it'll be a pc of whole new parts.

Don't I need to get into the BIOS to change to CSM mode?  My card is packaged up anyway, just waiting for some labels from EVGA.


----------



## seamonkeyhd

Veii said:


> To what i learned, tRFC will be repeated up to 9 times
> Which is why i don't always run the lowest tRFC till it crashes
> It's time window can be too short: Optimally it's shifted & repeated again, without a crash.
> One of the reasons why people see no improvement with lower tRFC. Their starting point was already too low to begin with
> 
> Very sure on that part
> 
> tRC is not "time-break" able to what i know
> It always "has to elapse" and explains why it can hide missmatched timings.
> A DRAM engineer here (been some time 5-7months) wrote a long article of how fascinating he still finds it that a little IC can have over 1.3 million little cells which all have to be able to run that timing window
> It was a question about tRP+tRAS = tRC and why XMP often appears to be slightly higher and different.
> 
> I'm not sure if tRP can be time-broken, but tRC certainly can not
> Yet between tRC as tRAS+1 or tRAS+tRP , there was an autocorrection and shifting happening.
> tRAS+1 trick only worked if transition timings (tRRD, tWTR) where higher , tFAW was bursty 1x mode equal or smaller than tRRD_S & tRDWR had excessive wasted latency on it
> 
> Soo i'm not sure if tRC can not be repeated (if too short) - but i am sure it can not be time-broken and has to elapse.
> Another reason why i picked it as anchor and trow away the old matching CAS latency idea for tRFC prediction. tRC was/is a fixed time window and can be used well for discharge prediction. Well i had reasons ^^'
> 
> tRAS entended, i am not sure
> I have not read anywhere that they could be time-broken at all.
> Maybe could get repeated if they are too short, but i haven't seen such behavior yet
> Actually, maybe
> Maybe they can be time-broken if too long, but i haven't seen or read anything anywhere about this.
> Nor experienced it myself while playing with couple tRAS formula's.
> Lower tRAS always result in better performance when it's really stable
> BZ's experience is the opposite. For him tRAS does nothing and only lower tRC increased performance consistently
> 
> tRC for my way of balancing (lower than tRP+tRAS) does close to nothing.
> It only does something if i use tRCD_WR as exploit , or do another exploit for 1x tFAW mode. Oor a 3rd one which is focusing on half tBURST length & requires left charges from previous operation in the cells. Soo a recharge stacking method
> (2 or 8gb dimms, 4 for dual rank ~ instead of 4 or 8)
> Each of them functions but stability on them is hard to maintain.
> Currently run the tRAS = tRCD+tRTP trick + tRTP = tRRD_L.
> Later one might not be needed, but i try to get tWTR_S down to 2 stable like intel OCer do. Requires balancing with SD, DD's soo try-and-research progress.
> 
> Generally seen interesting behaviors and different timing balancing methods (soo i stopped following JEDEC, as there are far more than 1 method to get your timings balanced)
> But haven't seen tRAS ever being time-broken nor tRC. Well tRC for sure haven't seen being time broken, tRAS could technically work as repeat ~ yet no idea about shortening it. Always wondered why tRAS can not go lower than 21 ~ when it should be possible to my C13-13 testing
> 
> It can be a lot
> GDM enabled will hide powering issues - GDM off 2T should be your focus since the very beginning
> 
> WHEA Free unlikely, it either works or doesn't work
> #19 are not FCLK or MCLK related , if you mean these
> 
> Did the board autopredict your tRDRD & tWRWR SD, DDs ?
> They look messy, usually it's 1-4-4-1-6-6 or 1-4-3-1-6-5 (1-5-4-1-7-6 , but that one is actually worse ~ well it helps lower tRDWR -1 but for such there are better tricks out there)
> DD usually is lower or equal to SD here. Higher nearly never unless misspredicted
> 
> Can you doublecheck and confirm that all your dimms have tPHYRDL 28 ?
> If one is lower, it means that cLDO_VDDP is a bit weak for this MCLK and you should increase it slightly or decrease procODT once
> 
> i wonder if 4x 16 wouldn't need 1-3-3-1-5-5
> Higher capacity needed these lower to my tests
> And lower values , at least on SD never gave performance but rather lost performance
> Higher values resulted in better performance - except now for DD's
> 
> if i run 1-4-4-1-6-6 i "leave latency on the table" and lose performance
> If i wanted to run something unstable and have balancing issues with tRRD & tWTR, i just "loosen" SD,DDs up to to 1-4-4-1-6-6 and that hides my misstimed timings
> 
> Been running before 1-6-6-1-9-9 but that only was possible when i relaxed tRRD and tWTR , in the case of lowered one value and broke the 2 stepping in between _S and _L
> That usually gave more perf, but 1-5-5-1-7-7 if the set was fine, run better than 1-4-4-1-6-6 for 2x8
> 4 dimms always liked 1-4-4-1-6-6 more , soo for 16gb each, i wonder if 1-3-3-1-5-5 wouldn't even be better here


Here is what I have at the moment.. 










and yes, the tPHYRDL is the same for all DIMMs. 
tRDRD and tWRWR were set auto
I have set them manually like you mentioned. I lowered the procODT.


----------



## Veii

mongoled said:


> Just like to add have also found that increasing CLDO_vDDP helps to keep tPHYRDL to a lower value


Yes that is pretty much clear now. Thank you @XPEHOPE3 for bringing that up
It will easily show if cLDO_VDDP is "too low"

I haven't tested if procODT helps with such








* Very unstable Right side powering preset, do not replicate

860mV seems to be "just enough" for memory to train @ 28ohm. It refuses to train @ 30ohm procODT
it appears to be better than the old 900mV "always working" trick

840mV surely changes down to tPHYRDL 24 on the furthest slot only
Maybe something can be done with RTTs to fix that, or it needs 120ohm ClkDrvStr (800mV cLDO_VDDP)
I've had 120-20-24-24 running but it only caused me PCB crashes. Potentially a thing, but it's interesting

It surely drops to 24 bellow 850mV cLDO_VDDP
and training only functions if you decrease procODT - else it doesn't at all and hangs in a loop


seamonkeyhd said:


> Here is what I have at the moment..


Aah i see an issue
CAD_BUS setup timings are MCLK dependent








It's still strongly WIP
But 2000 MCLK requires tCKE 11 and SETUP Timings 4-4-18, if you want to use them
Keep in mind , this can mess up RTT_WR behavior and you very likely need to drop it

6-3-3 for dual rank worked fantastic , but for 4 dimms it wasn't that perfect (dark hero for example)
Can you run RTT 703 above 1.46v ~ with the SETUP time changes above ?
Will it post ?


----------



## XPEHOPE3

Veii said:


> i wonder if 4x 16 wouldn't need 1-3-3-1-5-5


I described how my kit/board behave with values of "3" here:


XPEHOPE3 said:


> Usually when it's hard to post for my PC it attempts posting two times, and the third time is always the charm -- it just boots to JEDEC. However as soon as I set any of SD/DD to 3 or 2 (didn't check 1), my PC just keeps trying to post! It might take 10+ attempts before it finally resorts to JEDEC. One time it was just stuck during one of the posts, but cold boot let it proceed trying.


Anyway, mind you, I'm on AGESA 1.2.0.3B, that might have changed SD 4/6 vs 5/7 performance. Also I think it's faster for you to "just test it"  by changing those two values and running Aida (without trying to fix anything if it doesn't post).


Veii said:


> To what i learned, tRFC will be repeated up to 9 times


According to DDR4 spec it will, but only within its "budget". That is, if refresh cycle happens that much during some timeframe, _it won't happen during another timeframe_ resulting in the same amount of refresh cycles overall. And _that _would likely result in error. I only get TM5 errors going beyond 200ns tRFC while still having lower latency scores. I wish it could be remedied by voltage/impedance changes 



Veii said:


> Yes that is pretty much clear now. Thank you @XPEHOPE3 for bringing that up


I'd gladly take credit for bringing tPHYRDL topic in the first place (as can be seen via forum search) 😇 But it was @Blameless who found more or less direct VDDP influence on it.


----------



## Blameless

Veii said:


> To what i learned, tRFC will be repeated up to 9 times
> It's time window can be too short: Optimally it's shifted & repeated again, without a crash.


Do you have any references for this?



Veii said:


> One of the reasons why people see no improvement with lower tRFC. Their starting point was already too low to begin with


Pretty much all of my memory will see improved performance with reduced tRFC, right up until the point it will no longer post.

My B-die _might _be different, as I can tighten tRFC on it further than I can anything else, but it's languishing in a 3700X system so haven't really pushed it to it's limits.



Veii said:


> Soo i'm not sure if tRC can not be repeated (if too short) - but i am sure it can not be time-broken and has to elapse.


I'm almost positive it can be extended or repeated, but yes, it cannot be broken--it's a minimum value, like tRAS.

Previously linked: https://web.eic.nctu.edu.tw/lpsoc/courses/MS2017Spring/supplemental/3. DRAM Memory-Access Protocol.pdf

I'm pretty sure the tRC value I'm using must be repeated/extended for opening pages for writes because it's considerably shorter than the minimum timing formula referenced. However, I can also clearly show that it performs better at this value, and is as stable as can be practically determined. Evidently the overhead from a repeat during short writes is not enough to overcome the advantages for reads or perhaps burst writes.



Veii said:


> Another reason why i picked it as anchor and trow away the old matching CAS latency idea for tRFC prediction. tRC was/is a fixed time window and can be used well for discharge prediction. Well i had reasons ^^'


Your formula results in almost exactly the floor for stable tRFC on my 8Gb CRJ, but well is below what will boot on my 16Gb Samsung M-die and is probably borderline on my 16Gb Micron B/E stuff.

I assume it's mostly intended for Samsung B-die?



Veii said:


> BZ's experience is the opposite. For him tRAS does nothing and only lower tRC increased performance consistently


tRAS and tRC are so intimately linked that I haven't bothered to test them separately...extending tRC seems to be de facto extending tRAS, no matter what tRAS is set to, as far as I can tell. Haven't looked into it in great depth, however.


----------



## Veii

XPEHOPE3 said:


> I'd gladly take credit for bringing tPHYRDL topic in the first place (as can be seen via forum search) 😇 . But it was @Blameless who found more or less direct VDDP influence on it.


Mmm we all contributed,
Without reading the posts, i came to the same conclusion the recent 4 days
You gave the focus point ~ which was important. Cudos are there where it's deserved
I ignored it because the board does what it does, and latency change wasn't the key factor for it. It didn't bother and never noticed it being suspicious
Yet i do think it has to do with IO-L prediction and behaves similar to tWRWR_SG , on intel ~ if not identical


Blameless said:


> Pretty much all of my memory will see improved performance with reduced tRFC, right up until the point it will no longer post.
> 
> My B-die _might _be different, as I can tighten tRFC on it further than I can anything else, but it's languishing in a 3700X system so haven't really pushed it to it's limits.


My PCB allows down to 114ns, but i trade heat for it and was experimenting with tWR and tRTP matching for it
Still driving that personal idea train, till it causes me hard issues.
It hasn't so far , mini module functions ~ but it's not perfect.
tRFC can be lower by a magniture of 1/8th + 1/12th + 1/16th of tRC, near * 5.875 range, instead of "minimum listed 6* range
1usmus knows far more on the balancing and i couldn't get to this day out how to make tSTAG out of thin air and use it in the tRFC formula

I see people use x value * by 25MT/s frequency steps and the community calculator researched it by themself








This part tRFC 2 and 4 i lack
Even as contributor, i don't want to borrow or steal code ~ soo i haven't figured a better JEDEC alike method out for higher than 8gb dimms
Don't have 16gb modules to struggle with them and upgrade tRFC mini

tRFC 1 should be fine, but considering 1 is calculated from 2 ~ i don't think it's that's great to use for 16gb dimms
For the Rev.E's i just remained to use *11 or *12 mode
While it works, it messes up the core reason of it, which was discharge prediction ~ considering & expecting tRP to be correct, soo tRC = tRP+tRAS.
It kept working for low tRC or for SO_DIMM DDR3 , where tRC had to be "get up" , it continued to match well
But at the end, it still depends on your hardwall. Either you can or can not run one step lower

I do use tRC as very valuable anchor, as it can not be time-broken
Started initially to replicate the whole "operation chain" , and that way tried to "calculate" how long tRFC has to be, to always catch it.
But i couldn't make tSTAG out of thin air and missed couple of timings.
Abandoned/Paused the personal docs calculator and just released this tiny module, with little changes over the time ~ yet it keeps functioning.
Good enough allowing me to run 114ns , lower than the usual 120ns wall.



Blameless said:


> Do you have any references for this?


Been some time, quite some long time - i stopped looking into technical papers
But it was readable on SDRAM explained pages. Well pretty much everywhere it stated that inside the finite range of tREFI ~ it could be postponed up to 9 times (soo likely 8+)
tREFI on AMD i expect to be "perfect" as we can not modify it and it always changes.


Blameless said:


> Pretty much all of my memory will see improved performance with reduced tRFC, right up until the point it will no longer post.


mmm~, i couldn't find that yet
It caused me more strain and more issues ~ maybe if memory would be cooler i could try
But always lost performance if i don't match tRTP and tWR for it
Down to 5 tRTP and tWR 10 functioned, which appear to also do the same on Intel ~ same trick same stable result

Just tRFC issues only appear after 9-19 cycles, often fails just before the end of cycle 19 after over an hour
The real "problem" really lies that no matter how much it's dissagreed, the little tool functions with consistently better results
I was never forced to redo it. Can see little balancing issues ~ but the methodic was kept functioning. Soo i didn't bother to research for better methods, when the results where great
Someday tho i want to get that one step lower "perfect calculation" done. But there is no way unless i figure out how 1usmus went lower than the similar method i use (likely he used) to get up with tRFC

He clearly didn't base it off out of thin air and calculated it, but all his timings where tested. Nothing in DRAM calculator was really "calculated" ~ nothing timing based
To this day haven't figured out how he utilizes tSTAG for his advantage


----------



## Blameless

Veii said:


> This part tRFC 2 and 4 i lack
> Even as contributor, i don't want to borrow or steal code ~ soo i haven't figured a better JEDEC alike method out for higher than 8gb dimms


The tRFC formula most often quoted, even by 1usmus (tRFC2 = tRFC/1.346 and tRFC4 = tRFC2/1.625), is derived directly from the JEDEC timings for 8Gb (gigabit) ICs. You can do the same thing for any size IC.

4Gb ICs are 260ns / 160ns / 110ns and 260/1.346 = 160/1.625= 110.
8Gb just extended this to 350/260/160. So 350/1.4545...=260/1.346=160.
16Gb adds 550ns. So 550/350/260, 550/1.5714 = 350/1.4545=260

I forget what 32Gb ICs use, but since there are no 32Gb ICs in any DDR4 UDIMMs that I know of, it's probably not very relevant to most of us. That said, even JEDEC's figures seem mostly arbitrary, given how easily the spec can be violated and how variable and IC type dependent the workable values are.


----------



## Ramad

Blameless said:


> I don't think this is how tRFC works. Too low of a tRFC doesn't result in an extended refresh cycle, just an incomplete refresh or refresh recovery period...and often very abrupt instability.


Correct. tREFI is the time between refresh cycles and tRFC is the refresh cycle. The memory controller will issue a refresh cycle that lasts a time that equals tRFC every passed tREFI.










For all RAM densities, tREFI is 7.8us if the IMC uses tRFC/1, 7.8us/2 for tRFC/2 and 7.8us/4 for tRFC/4, that is when RAM is operating between 0C and 85C, between 85C and 95C the RAM takes over and runs in shorter tREFI intervals of 7.8us/2, 7.8us/4 and 7.8us/8 for tRFC/1, tRFC/2 and tRFC/8 respectively.

Shortening tRFC, which is the time required for the RAM IC to recharge the 1 bit cells will result in data corruption, most noticeable symptom is sound crackling that some complains about while running half of the required tRFC. Low tRFC will result a silent data cancer that will corrupt something in any of running programs or somthing is saved from RAM to disk.


----------



## Veii

Ramad said:


>


Why has (base) be a world-clock value ?
I can't understand the logic behind this, even when the data is laying infront of me, it makes no sense. Too tired
Couldn't understand before, can neither now

Any fixed time delay has to be a placeholder changing by used frequency, thermals and behave different by input current
No fixed world clock can be accurate across the whole frequency range. I can not understand why soo many JEDEC values are written in fixed values
It doesn't stick in my head why JEDEC can be followed when ICs are too variable.

This have to be either predictions or maximum values.
Just then for predictions it will match Samsung's manufacturing (IC behavior) yet no micron's.


> tREFI is the time between refresh cycles and tRFC is the refresh cycle. The memory controller will issue a refresh cycle that lasts a time that equals tRFC every passed tREFI.


You explain it likely well, but the logic remains missing to me
I can note it down and quote it, but that's it - it lacks logic or connections for it, soo it will never be remembered
Guess i can not overclock memory, but only like a monkey press buttons, trial and error 🙉


----------



## Blameless

Veii said:


> Why has (base) be a world-clock value ?


It's just saying that the maximum refresh interval goes down with the more granular refresh modes.



Veii said:


> Any fixed time delay has to be a placeholder changing by used frequency, thermals and behave different by input current
> No fixed world clock can be accurate across the whole frequency range. I can not understand why soo many JEDEC values are written in fixed values


The specifications are fixed intervals in time, not in cycles. The number of cycles depends on the clock speed of the memory.

An 8Gb IC is required, by JEDEC spec, to spend 350ns on a full refresh cycle. This applies to any and all speed grades.

350ns is 420 cycles for a 1200MHz (DDR4-2400) part, or 560 cycles for a 1600MHz (3200MT/s) part, for example.



Veii said:


> This have to be either predictions or maximum values.
> Just then for predictions it will match Samsung's manufacturing (IC behavior) yet no micron's.


They are specifications for stock, reference, parts. If an IC made by anyone claiming to conform to JEDEC spec does not work with values at least this low for tRFC or at least this high for tREFI, at or below spec temperature, it's defective.

Of course, all of us OCers know that specs are just guidelines and some parts can safely violate them more than others.


----------



## gled_fr

New stable, 54.8ns still, dropping trfc from 270 to 260 did not change much, but at least it matches the calculator. scl to 2 and trrdl 4 was making one of the tm5 thread crash ( the classic freeze ).









I really fear going to tcl 14 now but I feel like it's the way to get that latency down further. 

If I understand correctly, to go down to 14 on tcl, trcdrd and trp, I should up vdimm and lower procodt, maybe change also clkdrvstr, am I right ?


----------



## Veii

Blameless said:


> Of course, all of us OCers know that specs are just guidelines and some parts can safely violate them more than others.


Your posts i understand
Somehow Ramad's do not stick in my head at all. Nothing of it. Is it by the short length or by the phrasing, idk. 


gled_fr said:


> If I understand correctly, to go down to 14 on tcl, trcdrd and trp, I should up vdimm and lower procodt, maybe change also clkdrvstr, am I right ?


Up VDIMM and lower RTT_PARK by one
Stay on the same MCLK + timings ~ and just try to post
How much voltage was this at ?
Maybe 734 would be better, maybe 623 would be better

procODT and cLDO_VDDP are together
our known procODT range is based on 900mV cLDO_VDDP, which remains to function even with 2167 MCLK.
No reason to change it unless you have PCB crashes and need to lower something that is not VDIMM
ClkDrvStr and procODT go together, but that is if you want less procODT.
ClkDrvStr and RTT_PARK go together, but you can decide what to lower and increase the other
You might not even need to lower ClkDrvStr. For now at least while signal remains clean on low voltage (hopefully clean)

EDIT:
I don't like your tWR of 12
13 or 16 would suite better i think.
You can certainly try 13 and see if it makes stability issues ~ or just remember it, if you ever face errors which mention tWR


----------



## Blameless

Veii said:


> Your posts i understand
> Somehow Ramad's do not stick in my head at all. Nothing of it. Is it by the short length or by the phrasing, idk.


Something is usually lost in translation.

I understand what Ramad is saying, but judging from these flag icons, I'm the native English speaker here, so I probably have an edge on an English language forum.


----------



## byDenoso

Veii said:


> You gain more voltage headroom with higher tRRD, tWTR and tWR
> See me running 20ns more tRFC and far higher tWR
> I have non left either / was fun till 1.66v.
> tCL will either post and accept the voltage or fully refuse to post (then it was clearly not enough)


i'm getting a ton of error 0,2 and 12, and when i tweak RTT's i get error 5 and 14. 
I'm really close to stabilize with tRP 17 but if it doesn't, i'll keep tRP 18 and call it a day.


----------



## Ramad

Veii said:


> Why has (base) be a world-clock value ?
> I can't understand the logic behind this, even when the data is laying infront of me, it makes no sense. Too tired
> Couldn't understand before, can neither now
> 
> Any fixed time delay has to be a placeholder changing by used frequency, thermals and behave different by input current
> No fixed world clock can be accurate across the whole frequency range. I can not understand why soo many JEDEC values are written in fixed values
> It doesn't stick in my head why JEDEC can be followed when ICs are too variable.
> 
> This have to be either predictions or maximum values.
> Just then for predictions it will match Samsung's manufacturing (IC behavior) yet no micron's.
> 
> You explain it likely well, but the logic remains missing to me
> I can note it down and quote it, but that's it - it lacks logic or connections for it, soo it will never be remembered
> Guess i can not overclock memory, but only like a monkey press buttons, trial and error 🙉


RAM time is divided into tREFI long sections of of 7.8us that is around 15000 clock-cycles (can't remember the correct number). tREFI includes all RAM operations that are read, write and refresh. From the RAM time tREFI = 0 clock-cycles to the time tREFI = ~15000 - tRFC clock-cycles is a time used for write and read, the last part reserved for RFC were the RAM stops all operations and starts a refresh cycle that takes tRFC long clock-cycles.

Increasing tREFI (which is not possible with AMD Ryzen) will result in more write and operations before hitting the refresh cycle RFC, and the same happens when decreasing tRFC which results in more time in the tREFI interval for write and read operations.

I think that the diagram below will give you a better idea of what I'm trying to explain here, It's of a 4Gb RAM IC but only the tRFC values changes for an 8Gb or 16Gb ICs, the idea is still the same.


----------



## gled_fr

Veii said:


> Up VDIMM and lower RTT_PARK by one
> Stay on the same MCLK + timings ~ and just try to post
> How much voltage was this at ?
> Maybe 734 would be better, maybe 623 would be better
> 
> procODT and cLDO_VDDP are together
> our known procODT range is based on 900mV cLDO_VDDP, which remains to function even with 2167 MCLK.
> No reason to change it unless you have PCB crashes and need to lower something that is not VDIMM
> ClkDrvStr and procODT go together, but that is if you want less procODT.
> ClkDrvStr and RTT_PARK go together, but you can decide what to lower and increase the other
> You might not even need to lower ClkDrvStr. For now at least while signal remains clean on low voltage (hopefully clean)
> 
> EDIT:
> I don't like your tWR of 12
> 13 or 16 would suite better i think.
> You can certainly try 13 and see if it makes stability issues ~ or just remember it, if you ever face errors which mention tWR


I am at 1.45V on my stable settings.

Before seeing your post I booted same timings except tcl14 at 1.5V and procodt 34.3 => usually I would get error 6 right away, this time not but it's only 2 cycles of tm5, there was a screen flicker when stopping the test, so I guess it is not stable.

As you asked [EDIT 1 mybad, forgot to change back tcl, the tests below are with tcl14, doing it again for tcl 15 ]:

I tried booting at vdimm 1.47V and Rtt_Park rzq/4, it does not post.
It does post at vdimm 1.5V Rtt_Park rzq/4 and windows boot.
it does post at vdimm 1.48V Rtt_Park rzq/4 but windows does not boot ( black screen after bios )
it does post at vdimm 1.49V Rtt_Park rzq/4 and windows boot.

[EDIT 2] Test take 2, this time with the stable timings:

it does post and boot windows at vdimm 1.47 and rtt_park rzq/4
it does post and boot at vdimm 1.46 and rtt_park rzq/4
it also does post and boot at vdimm 1.45 and rtt_park rzq/4

I guess vdimm 1.49V then for lowering tcl, trcdrd and trp ?

I am a bit confused by "Maybe 734 would be better, maybe 623 would be better".

I will up tWR, thanks


----------



## seamonkeyhd

Veii said:


> Yes that is pretty much clear now. Thank you @XPEHOPE3 for bringing that up
> It will easily show if cLDO_VDDP is "too low"
> 
> I haven't tested if procODT helps with such
> View attachment 2519043
> 
> * Very unstable Right side powering preset, do not replicate
> 
> 860mV seems to be "just enough" for memory to train @ 28ohm. It refuses to train @ 30ohm procODT
> it appears to be better than the old 900mV "always working" trick
> 
> 840mV surely changes down to tPHYRDL 24 on the furthest slot only
> Maybe something can be done with RTTs to fix that, or it needs 120ohm ClkDrvStr (800mV cLDO_VDDP)
> I've had 120-20-24-24 running but it only caused me PCB crashes. Potentially a thing, but it's interesting
> 
> It surely drops to 24 bellow 850mV cLDO_VDDP
> and training only functions if you decrease procODT - else it doesn't at all and hangs in a loop
> 
> Aah i see an issue
> CAD_BUS setup timings are MCLK dependent
> 
> 
> 
> 
> 
> 
> 
> 
> It's still strongly WIP
> But 2000 MCLK requires tCKE 11 and SETUP Timings 4-4-18, if you want to use them
> Keep in mind , this can mess up RTT_WR behavior and you very likely need to drop it
> 
> 6-3-3 for dual rank worked fantastic , but for 4 dimms it wasn't that perfect (dark hero for example)
> Can you run RTT 703 above 1.46v ~ with the SETUP time changes above ?
> Will it post ?


I changed the tCKE to 11, Setup to 4-4-18
RTT to 703 and VDIMM 1.4v
it reset the OC on boot because it failed..


----------



## gled_fr

gled_fr said:


> I am a bit confused by "Maybe 734 would be better, maybe 623 would be better".


Just dawned on me it's the rtt  7 3 4 or 6 3 3  Ah sometimes brain doesn't register as fast as it should


----------



## craxton

mongoled said:


> Would not have gone down that route of getting a "2nds" motherboard as I would always be second guessing if any possible issues I were seeing were one of the reasons the motherboard was initially sent back.
> 
> On the assumption the motherboard is good, maybe the CPU is the culprit ?
> 
> Now to your question, tCL and 2tCmd are the values that effect tPHYRDL along with the memclk frequency.
> 
> FYI, I upped to tCL 15 from 14 @3800 as tCL 14 was kicking all my sticks to tPHYRDL @28


"sorry for a late but in response been busy"
but i gotta disagree with you, my b550 gaming edge board is used from amazon, 
again tho wasnt opened in the packages (none of them) only the box was opened and 
registered for warranty none the less on MSI website.
come to think of it my EVGA 2070 S FTW 3 ULTRA+ is the same way (USED-GOOD) condition.
which again, registered on EVGAs website for warranty and is yet to "fail" me...
......wait, near ALL i own is either USED-GOOD/LIKE NEW, and ive had no issues with the 
products and have been able to register warranties...
@Audioboxer did you try to register the warranty on your board?


----------



## domdtxdissar

Veii said:


> =================================================================
> Soo this seems so far the fastest TM5 run i had ~ Win 22000.100 fresh install
> CPU seems slightly slower than usual (LinX) ~ but this could be because i haven't disabled WinDef, Antivirus, Security Center and stuff, yet
> Guess it averages out, but the Bandwidth increase is a new PB
> 
> 1.65vDIMM ~ yet cozy on 30c Room & outdoor-temp
> _* who says you should not daily more than 1.5v _
> View attachment 2519012
> View attachment 2519013
> 
> Might try to improve it a slight bit (voltage hardwall ~ A0 PCB reason) , but lazy me should finally face 2133 FCLK
> This 47.7ns run is mocking me 🤭
> I'd also really like to play with A3 PCB Dimm's - don't have any nearby


At what clockspeed did you run LinX ? 
Results seems slower than they should..

This is my old "fake 6 core zen3" running un-optimized settings in bloat windows10
(should atleast get 290++ Gflops if i try the same today with better settings)


----------



## rossi594

Is anybody running the 1.2.0.3 C agesa on high fclk yet? Heared there are supposed to be less whea 19s with that.


----------



## Robostyle

What can cause tm5 crash at the end of testing? Mine crashes at 23rd/24th of 25cycles, or 29th of 30 cycles, etc.
ycruncher rock solid for 12h

And btw, couldnt these trash application’s background updaters - that keep on running even if you kill main task - crash tm5 in the middle of the process? Because Ive just seen it today.
First tm5 crashed at ~20-23 cycle, also took down dwm and nvm container, but then ran 3 times 25 cycles without a blink. Within the same system, no prior reboots.

Like that, if you wanna proper ram testing, do it in safe mode..


----------



## XPEHOPE3

Robostyle said:


> Mine crashes at 23rd/24th of 25cycles, or 29th of 30 cycles, etc.


Had that when testing tRFC slightly below its minimum.
Also I had TM5 errors as soon as I connected to the PC being tested via RDP. Ofc that means instability. That's the point of testing  not the fancy screenshots


----------



## gled_fr

Ah the joy of the christmas tree lightning up when trying to go to 14s  ( vdimm @1.5V, it does not boot without it at those settings ) )


----------



## Veii

domdtxdissar said:


> At what clockspeed did you run LinX ?
> Results seems slower than they should..
> 
> This is my old "fake 6 core zen3" running un-optimized settings in bloat windows10
> (should atleast get 290++ Gflops if i try the same today with better settings)
> View attachment 2519090


It usually holds around 4.65ish on AVX2 out of 4.85 SSE and 4.725ish AVX. Potentially can be near 4.8 if i lower CO further, but without giving it voltage, it doesn't scale up further / EDIT: Well that's far lower than usual expected results ~ Thermals 


Spoiler: Cheap Excuse, but also bit of reality



1.15v was what LinX holds ~ which with CTR would be near 4375-4450 unless i do run negative CO, which is close to telemetry faking.

You seem to use only 76A EDC tho ?
Either your sample runs bellow 1v at 4.85 - or SOC takes less
Likely all 3 of them. Turned 2nd CCD off + 7-8A lower SOC powercut and a better sample

Unsure if EDC FUSE limit applies to you when you turn the 2nd CCD off ~ don't think so, yet you're not even close to 120A load
We surely have big performance differences and capability differences.
I don't think it can be comparable.

I can work on it slightly more (negative CO) but rather the FUSE limit is my core issue + 2nd CCD eats too much with this too small EDC limit set by AMD
Yet CTR performs worse than my PBO on stock, and only slowly behind on CO overdriving (which disables OB functionality).
Working with Yuri for 3-4 months, lead to no positive change for me. But OB feature got implemented after the CO discovery, but it remained to perform worse.
At least it's close now, but still remains worse as CTR is switching too slow. P-Hydra might be then better when it's CO aware

Weighted both out, but high FCLK makes more sense with held boost and 4.85 on SSE loads or light AVX loads
Compared to focusing on Allcore Render performance with lower memory & fabric performance ~ less IPC

Telemetry faking it is what i lack for PBO, but this bios doesn't have it.
I'd need to continue breaking my bios on a board with miniSPI header for which i have no cables for.
On an unfinished 2nd PC setup atm without a GPU.
I can't set priority on this, don't have workloads which benefit from AVX2 to bother with it atm 
It's beyond annoying, and gives me big struggle (alone by cores having a messed up V/F curve ~ but it is what it is) ^ ^'
Till anybody bothers assisting me in figuring out how to OPN rebrand this unit ~ and let microcode recognize it's a true 16 core (well 14 core, but maybe 16 if unlockable)
Till 1usmus finishes ProjectHydra research too ~ i just have to bear with what i have & someday telemetry fake it, soo EDC FUSE doesn't constantly throttle


=======================================
EDIT:
It appears to not be only EDC Fuse, that doesn't trigger here
But simple 65°C PROCHOT hardlock by AMD
It seems to modify my FIT PRE low limit of 1.45v too (as for peak allowed voltage @ X thermals), soo likely just a thermal reason at this point

Well telemetry faking will help, so also more negative CO,
But it's fine how it is right now ~ EDIT2: i'll see if i can get a bit more frequency out of annoying AMD PROCHOT throttle, tho CO's are pretty tight already 















I expected CCA throttle, but actually it doesn't do it here anymore. It's not FIT-Q score throttle either ~ surprisingly
Purely thermals related as it seems. Nothing i can do against that one tho.
No budget for a cheap 2nd GPU or Storage, let alone any AIO. Maybe someday i'll come back to beat those OCCT, LinX and 3DMark results 

Please doubletest with option 4 (8GB)
Usually i was running 10, but BZ started to run 8Gb on all his tests, same as madness777 ~ soo just for comparison sake
Makes me wonder tho what you'd score on 4.550 ^^''
DynamicOC ASUS feature here would really help, not that it makes any sense for other workloads - but you know 🤭

Lesson learned today:


Code:


Do not buy 5600X's for any type of AVX2 Render workloads.
They are fine for gaming and daily usage, but anything serious needs to be held bellow 65°C
5800X doesn't do this (95°C Limit) ~ yet an AIO might be needed even for a 5600X

Well or hope Project Hydra will be a successor and help against such nonsense 

EDIT 2.5:
Additionals













up to 200Mhz + 40mV max allowed boost ~ lost on 6c higher than 65°C Limit , is a quite pathetic choice by AMD ~ to phrase it nicely 
It peaked once to 679 SC, but came down to 675 again ~ which appears to be caused this time by FIT-Q (it lost 2-3mV of peak 1.45v allowed boost)
SVI 2 category on the left (2nd picture) only took 1.388v , but maybe one core was FIT-Q throttled. Likely fixable with slightly more negative CO

EDIT 3:
I need to rephrase, it's worse than it seems 


Code:


Do not buy 5600X's at all. Unless you pair it with any AIO, be it even 120mm
The 65°C ProcHOT limit, will be enforced on any type of load. FMA/SSE/AVX.
Every GPU will heat the CPU beyond 70°C just by existing in a case (for gaming scenarios)
Loosing because of such 150-200Mhz ~ because heatpipes on an Aircooler, including thermal paste ~ both scale after 75-80c well.
Only AIOs are not interested in the surface temp of the unit they cool, heatpipes are !
Loosing for no reason frequency by a far too low set hardlimit, was a bad decision by AMD.
Every other CPU 5800X and higher are set to 95°C, soo grab any AIO or do not buy this unit if you care for frequency.

Vermeer is soo densely packaged, and when 250W air coolers barely hold it bellow 70c on load ~ a limit sub 85c is purely bad design and unrealistic.
Summer or not, when 90W push it to 20c above ambient ~ simply as heat pipes can not function on such low surface temp. The CPU FW design was a bad idea with such unrealistic limits

Another allcore load at 55c THM Sensor ~ SSE & FMA Worload







No VID throttle, no thermal throttle, no frequency throttle, no FCLK throttle, no loadline throttle between V-TEL & VID
_~ only SVI2 SOC has 40mV droop_
Guess i'll go and get sanding paper now, as this logicless issue annoys me far to much


----------



## Robostyle

XPEHOPE3 said:


> Had that when testing tRFC slightly below its minimum.
> Also I had TM5 errors as soon as I connected to the PC being tested via RDP. Ofc that means instability. That's the point of testing  not the fancy screenshots


SFXs like this is also tRFC fault?


Spoiler: crunch


----------



## mongoled

craxton said:


> "sorry for a late but in response been busy"
> but i gotta disagree with you, my b550 gaming edge board is used from amazon,
> again tho wasnt opened in the packages (none of them) only the box was opened and
> registered for warranty none the less on MSI website.
> come to think of it my EVGA 2070 S FTW 3 ULTRA+ is the same way (USED-GOOD) condition.
> which again, registered on EVGAs website for warranty and is yet to "fail" me...
> ......wait, near ALL i own is either USED-GOOD/LIKE NEW, and ive had no issues with the
> products and have been able to register warranties...
> @Audioboxer did you try to register the warranty on your board?


You can disagree all you like



Thats why I said "I" would not go down that route, because of the possible second guessing that would go on if something was not acting how I expected it should.

Its the possibility of getting something that may have been tampared with that puts me off buying such items.

Never said anywhere that other people should not buy them

So the way I see it your only diagreement is with probability not with me


----------



## mongoled

gled_fr said:


> Thank you,
> 
> I was starting to suspect those errors are either bugs, or something not really important... I'll do more stability testing above IF1900, but it seems like Manni-ITX suppressor is gonna get here too..


Sorry forgot to add,

Definately not a bug and definately there are reasons for the WHEA 19s and my understanding is that are many things that can trigger WHEA 19s, basically anything that passes data over the PCIe bus can trigger WHEA 19s, be it audio, usb, graphics etc etc



Audioboxer said:


> I know, right? Part of me is wondering is it at all possible my graphics card has been the issue all along and it somehow "fried" my old mobo before kicking the can fully this time around? At the rate I'm going all I need to do now is replace the CPU and memory and it'll be a pc of whole new parts.
> 
> Don't I need to get into the BIOS to change to CSM mode?  My card is packaged up anyway, just waiting for some labels from EVGA.


If I remember correctly BIOS pre agesa 1.2.x.x had CSM enabled by default.

On later BIOS this was changed, forgot about that little detail.

🤣


----------



## Mach3.2

Unstable CO and/or insufficient vSOC while trying to push the IF in 1:1 sync can also trigger WHEA 19s in my experience.


----------



## pewpewlazer

Tried bumping up to ddr3800/1900 fclk tonight and was able to run AIDA64 and then start TM5, but after a few minutes it straight up rebooted. No BSOD, no WHEA, no freezing, just reboot. Left it idle on the desktop while finishing my dinner and it rebooted again. After that, it would continue to reboot as soon as it loaded Windows. Bumping vDIMM from 1.41v -> 1.45v had zero affect.

Is this an FCLK stability issue? Are there any settings that can help here besides playing with vSOC (currently at 1.0875, tried 1.125 as well) and vDDG (both currently at 0.9976v)?


----------



## Veii

mongoled said:


> Its the possibility of getting something that may have been tampared with that puts me off buying such items.
> Never said anywhere that other people should not buy them
> So the way I see it your only disagreement is with probability not with me


Yea, the possibility is surely there
The chance is very low, as there are +90% casuals, yet from these not many return the board unless it has post issues or some other bad experience
A bios post issue, is probably the best thing you can get on such. 14 Days refund policy is not that long tho
Another option are RMA for repair boards which hopefully where repaired or ones that have coil whine
I can agree well, that warehouse items often have user-dislike issues, soo you might also dislike it at some point

Tho when it comes to ebay or generally 2nd hand
Close to everything i own is 2nd hand
I do buy new medical items and headsets. Probably other consume items too, soo bathroom stuff, cloths
Chairs are complicated, they are often overpriced and used is not hygienical either - soo it really depends

As for barebones electronic, close to everything that is repairable is 2nd hand for me personally
Monitors 100% so far (got a Samsung U32J590UQU for 150€ ~ it running 4k was just a free bonus & early my AOC Q3279VWFD8 for 130-140 bucks, as my main gaming unit)
Mice was used, storage is complicated but was used in good condition. Keyboards are complicated between hygienic or not. Soundcards are used, desks are used
I like saving money, when there is barely for food or rent 🤭

On Amazon warehouse, generally shops you have no refund possibility ~ such is complicated to do
Ebay is the same but at least you see the goods picture
Amazon seems to barely pass, as you can still send it back ~ yet generally in understand both sides very well
Would i only buy new, i wouldn't have half of what i own right now.
Neither a chair, nor a 2nd monitor for the 2nd build-in-progress pc
Or a desk.

Well ok, beds and mattresses i wouldn't buy used, clearly not without inspection and clearly not if it isn't washable
That is on the same line as cloths. Possible, but i'd rather not and skip this route 
Bed frames on the other hand, or wardrobe's, other furniture ~ why not. As long as it doesn't come from a smokers home (you can't wash wood, heh)
But mostly only physical repairable gear and nothing hygienical.


----------



## domdtxdissar

Veii said:


> It usually holds around 4.65ish on AVX2 out of 4.85 SSE and 4.725ish AVX. Potentially can be near 4.8 if i lower CO further, but without giving it voltage, it doesn't scale up further / EDIT: Well that's far lower than usual expected results ~ Thermals
> 
> 
> Spoiler: Cheap Excuse, but also bit of reality
> 
> 
> 
> 1.15v was what LinX holds ~ which with CTR would be near 4375-4450 unless i do run negative CO, which is close to telemetry faking.
> 
> You seem to use only 76A EDC tho ?
> Either your sample runs bellow 1v at 4.85 - or SOC takes less
> Likely all 3 of them. Turned 2nd CCD off + 7-8A lower SOC powercut and a better sample
> 
> Unsure if EDC FUSE limit applies to you when you turn the 2nd CCD off ~ don't think so, yet you're not even close to 120A load
> We surely have big performance differences and capability differences.
> I don't think it can be comparable.
> 
> I can work on it slightly more (negative CO) but rather the FUSE limit is my core issue + 2nd CCD eats too much with this too small EDC limit set by AMD
> Yet CTR performs worse than my PBO on stock, and only slowly behind on CO overdriving (which disables OB functionality).
> Working with Yuri for 3-4 months, lead to no positive change for me. But OB feature got implemented after the CO discovery, but it remained to perform worse.
> At least it's close now, but still remains worse as CTR is switching too slow. P-Hydra might be then better when it's CO aware
> 
> Weighted both out, but high FCLK makes more sense with held boost and 4.85 on SSE loads or light AVX loads
> Compared to focusing on Allcore Render performance with lower memory & fabric performance ~ less IPC
> 
> Telemetry faking it is what i lack for PBO, but this bios doesn't have it.
> I'd need to continue breaking my bios on a board with miniSPI header for which i have no cables for.
> On an unfinished 2nd PC setup atm without a GPU.
> I can't set priority on this, don't have workloads which benefit from AVX2 to bother with it atm
> It's beyond annoying, and gives me big struggle (alone by cores having a messed up V/F curve ~ but it is what it is) ^ ^'
> Till anybody bothers assisting me in figuring out how to OPN rebrand this unit ~ and let microcode recognize it's a true 16 core (well 14 core, but maybe 16 if unlockable)
> Till 1usmus finishes ProjectHydra research too ~ i just have to bear with what i have & someday telemetry fake it, soo EDC FUSE doesn't constantly throttle
> 
> 
> =======================================
> EDIT:
> It appears to not be only EDC Fuse, that doesn't trigger here
> But simple 65°C PROCHOT hardlock by AMD
> It seems to modify my FIT PRE low limit of 1.45v too (as for peak allowed voltage @ X thermals), soo likely just a thermal reason at this point
> 
> Well telemetry faking will help, so also more negative CO,
> But it's fine how it is right now ~ EDIT2: i'll see if i can get a bit more frequency out of annoying AMD PROCHOT throttle, tho CO's are pretty tight already
> View attachment 2519143
> View attachment 2519144
> 
> I expected CCA throttle, but actually it doesn't do it here anymore. It's not FIT-Q score throttle either ~ surprisingly
> Purely thermals related as it seems. Nothing i can do against that one tho.
> No budget for a cheap 2nd GPU or Storage, let alone any AIO. Maybe someday i'll come back to beat those OCCT, LinX and 3DMark results
> 
> Please doubletest with option 4 (8GB)
> Usually i was running 10, but BZ started to run 8Gb on all his tests, same as madness777 ~ soo just for comparison sake
> Makes me wonder tho what you'd score on 4.550 ^^''
> DynamicOC ASUS feature here would really help, not that it makes any sense for other workloads - but you know 🤭
> 
> Lesson learned today:
> 
> 
> Code:
> 
> 
> Do not buy 5600X's for any type of AVX2 Render workloads.
> They are fine for gaming and daily usage, but anything serious needs to be held bellow 65°C
> 5800X doesn't do this (95°C Limit) ~ yet an AIO might be needed even for a 5600X
> 
> Well or hope Project Hydra will be a successor and help against such nonsense
> 
> EDIT 2.5:
> Additionals
> View attachment 2519148
> View attachment 2519149
> 
> up to 200Mhz + 40mV max allowed boost ~ lost on 6c higher than 65°C Limit , is a quite pathetic choice by AMD ~ to phrase it nicely
> It peaked once to 679 SC, but came down to 675 again ~ which appears to be caused this time by FIT-Q (it lost 2-3mV of peak 1.45v allowed boost)
> SVI 2 category on the left (2nd picture) only took 1.388v , but maybe one core was FIT-Q throttled. Likely fixable with slightly more negative CO
> 
> EDIT 3:
> I need to rephrase, it's worse than it seems
> 
> 
> Code:
> 
> 
> Do not buy 5600X's at all. Unless you pair it with any AIO, be it even 120mm
> The 65°C ProcHOT limit, will be enforced on any type of load. FMA/SSE/AVX.
> Every GPU will heat the CPU beyond 70°C just by existing in a case (for gaming scenarios)
> Loosing because of such 150-200Mhz ~ because heatpipes on an Aircooler, including thermal paste ~ both scale after 75-80c well.
> Only AIOs are not interested in the surface temp of the unit they cool, heatpipes are !
> Loosing for no reason frequency by a far too low set hardlimit, was a bad decision by AMD.
> Every other CPU 5800X and higher are set to 95°C, soo grab any AIO or do not buy this unit if you care for frequency.
> 
> Vermeer is soo densely packaged, and when 250W air coolers barely hold it bellow 70c on load ~ a limit sub 85c is purely bad design and unrealistic.
> Summer or not, when 90W push it to 20c above ambient ~ simply as heat pipes can not function on such low surface temp. The CPU FW design was a bad idea with such unrealistic limits
> 
> Another allcore load at 55c THM Sensor ~ SSE & FMA Worload
> View attachment 2519152
> 
> No VID throttle, no thermal throttle, no frequency throttle, no FCLK throttle, no loadline throttle between V-TEL & VID
> _~ only SVI2 SOC has 40mV droop_
> Guess i'll go and get sanding paper now, as this logicless issue annoys me far to much


New runs for my fake 6core 5600X(T) 

Linx stresstest 8gb = 291 Gflops









But i think Linx scale more (too much) with clockspeed then with memory settings, so i also did a Monero RandomX Miner run as i think it relay more on pure memory performance.. (instructions how to install the miner can be found here)

Managed to get a very stable 8647.1 H/s hashrate with 6 cores.









Did also a run with the normal benchmark suite with the fake 5600x









Waiting for Hydra now... if all goes according to plan, alpha release is later today for patrons


----------



## XPEHOPE3

Robostyle said:


> SFXs like this is also tRFC fault?


Didn't see anything like that. The only graphical glitches I saw while fiddling with RAM timings stemmed from tWRRD/tRDWR/_SCL being too low.


----------



## Veii

domdtxdissar said:


> Waiting for Hydra now... if all goes according to plan, alpha release is today for patrons


Ooh this is great 
Looking forward to it too
Sadly lost contact to Yuri, remade social media parts including Discord

Please report with success~
Also thank you for all the benchmarks. Monero i remember staying near 8200 ish. It scaled strongly with MCLK (well actually FCLK and cache bandwidth, like CoD Warzone)
Will test it tonight. For now i'll surely lap this unit ~ too annoyed about the ProcHOT limit. Heatpipes need more Delta-T Headroom to function...

I wonder tho , for people with 5900X and maybe 5950X
This shouldn't be a core amount thing, soo likely also not microcode thing for 1CCD downgrades
Cache perf clearly suffers when you disable the 2nd CCD, but what about thermal limits (tool.exe) 
THM current Temp and THM PBO limits exist, but pretty much do nothing when your hardlimit is 65c


----------



## Audioboxer

craxton said:


> "sorry for a late but in response been busy"
> but i gotta disagree with you, my b550 gaming edge board is used from amazon,
> again tho wasnt opened in the packages (none of them) only the box was opened and
> registered for warranty none the less on MSI website.
> come to think of it my EVGA 2070 S FTW 3 ULTRA+ is the same way (USED-GOOD) condition.
> which again, registered on EVGAs website for warranty and is yet to "fail" me...
> ......wait, near ALL i own is either USED-GOOD/LIKE NEW, and ive had no issues with the
> products and have been able to register warranties...
> @Audioboxer did you try to register the warranty on your board?


Yeah just registered it fine. Serial on box matched serial on mobo and CHK code accepted OK.

Amazon have clearly added the tape I took off though, as I did check YouTube unboxing videos and it seems MSI do indeed not put any sealing tape over their boxes.

Whether it was a return or Amazon put it somewhere wrong in the warehouse and then had to check it, it looked totally unused and warranty has just registered fine.


----------



## tcclaviger

Now for a bit of surprising oddball tweaking:
2 Sticks of F4-4000-C16D-32GVKA (Primary Slots)
2 Sticks of Patriot Viper 4400 C19 (Secondary Slots)

Currently testing the below for errors, with TRDWR 10 and TWRRD 3 (8/3 doesn't play nicely). Have about 6 hours gaming on them with no issues, and about 12 total with no crashes mixed workload/benchmarks. Shocked at how well the C7H handled triple rank with asymmetric sticks. PC is working great now, only held back by max FCLK, not sure if it's Bios, AGESA, or CPU, but 1900 is D7 endlessly nothing helps it, reaches windows 1933/1966/2000 but with WHEA pouring out, no setting corrects it.

Holding out for X570 Dark from EVGA, if it still WHEAs like a mofo chip is going to get replaced. Temps are good though (16c water temps).


----------



## XPEHOPE3

Veii said:


> 1T then is another topic on its own and can need between 0.04-0.06vDIMM more to keep up same-timing stability


*Is VDIMM the only thing possible to stabilize 1T?*

I have this stable (tPHYRDL 26/26):







Aida read-copy-latency:
56538-55614 55.4-55.5, once 55.3

And 1T posts with either of the tCKE/setup timings tricks (56*3 means setup timings 56-56-56, "just" 56 means setup timings 56-auto-auto, resulting in 56-0-0 in ZenTimings):

11-56*3 phy28/28 56963-55849 55.8, once 55.6, some 56
10-56*3 phy28/28 57035-55971 55.6-55.8
9-56*3 phy28/28 56943-56008 55.6-55.8
8-56*3 phy28/28 56874-55741 55.8-56
7-56*3 phy28/28 56973-55777 55.6-55.8, once 55.4
6-56*3 phy28/28 56932-56074 55.7-55.8, some 55.9, once 55.5
5-56*3 phy28/28 56869-55904 55.8-55.9
3-56*3 phy28/28 56443-55936 55.8-56.2
1-56*3 phy28/28 56832-55816 55.9+ once 55.7
11-56 phy28/28 56770-55947 55.7-55.9
11-54*3 phy28/28 56956-55904 55.7-56
10-54*3 phy28/28 56815-55894 55.7-56
7-54*3 phy28/28 56869-55772 55.7-56
1-53 phy28/28 56942-55741 55.6-55.7, some 56
7-53 phy28/28 56988-55812 55.7, twice 55.5, some 55.9+
8-53 phy28/28 56871-55618 55.7-56
9-53 phy28/28 56895-55952 55.7-56
10-53 phy28/28 56730-55778 56+, once 55.8
11-53 phy28/28 56948-55935 55.8-55.9, once 55.5,7



Spoiler: These post but bsod or bad tPHYRDL



12-53 28/30
7-56*3 34/28
4-56*3 28/30, 30/30
2-56*3 28/30, 30/28
12-56*3 32/30
12-54*3 28/30
11-52*3 phy28/30 bsod
11-48*3 forever posts
11-63*3 also phy28/30
11-58*3 30/28
11-55*3 28/30
10-63*3 28/30 bsod



*What are the options to bring tPHYRDL down in this case?* VDDP to 950mv only makes worse.

I tried checking stability of ~best performing options:

7-53: tm5 gave 6,12 within 2 minutes, lots of other errors, 4s,0,5,3
7-56*3:


Spoiler: TM5 log after 3.5 minutes



Customize: Default @1usmus_v3
Start testing at 13:13, 4.9Gb x12
Ошибка в тесте 12 через .
Ошибка в тесте 12 через .
Ошибка в тесте 12 через .
Ошибка в тесте 12 через .
Ошибка в тесте 12 через .
Ошибка в тесте 12 через .
Ошибка в тесте 12 через .
Error in test #12 through 1m 45s.
Ошибка в тесте 0 через .
Ошибка в тесте 2 через .
Ошибка в тесте 0 через .
Ошибка в тесте 2 через .
Ошибка в тесте 2 через .
Ошибка в тесте 2 через .
Ошибка в тесте 0 через .



In both cases PC hangs before first cycle finishes.


----------



## Robostyle

XPEHOPE3 said:


> Didn't see anything like that. The only graphical glitches I saw while fiddling with RAM timings stemmed from tWRRD/tRDWR/_SCL being too low.


Exactly what I am interested in - if it is win10 fault, win10 corrupt or ram unstable.
Nvidia container and desktop manager keep crahsing while ram test keep on going like nothing happened.
As well as that screenshot - while desktop graphics glitch, ycruncher made 30 iterations before I manually stopped it without single error. The same goes to tm5

Event logger has report of background apps crashes, but 0 hardware errors for the last 7 days. Mostly codes 1000/10000/10xxx, etc.


----------



## XPEHOPE3

@domdtxdissar 
What specifically did you need to change to ensure stability when you went from GDM off 2T here to GDM off 1T?


----------



## domdtxdissar

XPEHOPE3 said:


> @domdtxdissar
> What specifically did you need to change to ensure stability when you went from GDM off 2T here to GDM off 1T?


Well firstly a newer bios was needed, i could never run T1 setup-time with bios 3003 like i have in that screenshot (think 3003 got released at end of 2020)

When i first made the change / the 56 trick got known, i was at bios 3501 (same as iam running today)
And with bios 3501 a few things changed compared to the older bioses, suddenly i could run much lower proc, lower vdimm was required and RTT also behave differently etc.

The following is needed for me today to run these settings:

IOD + CCD + VDDP + SOC voltages need to be "tuned/correct" (*in correlation to both themselves together with vdimm and proc + RTT*) (RTT 6-3-3 worked fine on older bioses, now 6 wont work whatever settings)(If i try to change one voltage from todays settings up or down i get worse results 90% of the time)


Proc need to low (~34/37 for my 4x8gb setup)


All timings need to be 100% stable in pure T2 before you make the jump


To pass 25 cycle testmem i needed to lower vdimm from my old ~1.57v to 1.54v. (this is also very temperature depended, i don't pass 25 cycles on the warmest days.. need to run at night for lower temp in summer)


I prepare everything in bios before i set T1, so when i change to T1 that's the only settings i change. (if i want to change something later i need to turn off T1 before trying to boot again after change (even if the only change is fan-curve))


----------



## XPEHOPE3

domdtxdissar said:


> so when i change to T1 that's the only settings i change.


Meaning you also use setup timings and tCKE on 2T?

Also, don't you update your BIOS now because you are too satisfied with current results? 😅


----------



## domdtxdissar

XPEHOPE3 said:


> Meaning you also use setup timings and tCKE on 2T?


Yes, but both ways work -> you can change tCKE and setup-time together with T1 (i did this in the beginning)



XPEHOPE3 said:


> Also, don't you update your BIOS now because you are too satisfied with current results? 😅


Yeah, there is a saying: don't try to fix what's not broken 

Have pretty decent performance atm and no problems, so i don't really see the need to change anything.. but that Asus 1.2.0.3 Patch C BETA BIOS sure looks alittle fun to play around with i have to admit..
If Hydra behaves maybe i wont update bios until its needed for the 5950x V-Cache edition  (will preorder soon as possible, think i got my 5950x in November last year so its time for a new toy)


----------



## Oversemper

Hello, Everybody! I was trying to get 1T command rate working without gear down mode, which seems impossible for my setup, but then just out of curiosity I've check T2 mode without gear down mode. And guess what, latency with T2 gear down mode OFF is about 1ns lower than T1 with gear down mode ON. But memtest bench is about 1.5 second longer. I did all tests multiple times (about 10 times each) to determine consistent results. Below screenshots and the rest of bios settings. Did not notice any difference for FPS in SotTR, PUBG or CS GO. In this situation which settings are best to use?
T1 GearDownMode ON:














T2 GearDownMode OFF:
















Spoiler: All bios settings (!long!)



[2021/07/29 21:03:56]
Ai Overclock Tuner [Manual]
BCLK Frequency [100.0000]
SB Clock Spread Spectrum [Disabled]
Performance Enhancer [Auto]
Memory Frequency [DDR4-3733MHz]
FCLK Frequency [1866MHz]
CPU Core Ratio [Auto]
Core VID [Auto]
CCX0 Ratio [Auto]
TPU [Keep Current Settings]
Performance Bias [Auto]
PBO Fmax Enhancer [Auto]
Precision Boost Overdrive [Auto]
Precision Boost Overdrive Scalar [Auto]
Max CPU Boost Clock Override [Auto]
Platform Thermal Throttle Limit [Auto]
DRAM CAS# Latency [16]
Trcdrd [19]
Trcdwr [16]
DRAM RAS# PRE Time [16]
DRAM RAS# ACT Time [36]
Trc [58]
TrrdS [4]
TrrdL [6]
Tfaw [16]
TwtrS [4]
TwtrL [12]
Twr [14]
Trcpage [Auto]
TrdrdScl [4]
TwrwrScl [4]
Trfc [545]
Trfc2 [Auto]
Trfc4 [Auto]
Tcwl [16]
Trtp [12]
Trdwr [8]
Twrrd [4]
TwrwrSc [1]
TwrwrSd [7]
TwrwrDd [7]
TrdrdSc [1]
TrdrdSd [5]
TrdrdDd [5]
Tcke [1]
ProcODT [43.6 ohm]
Cmd2T [1T]
Gear Down Mode [Enabled]
Power Down Enable [Disabled]
RttNom [Rtt_Nom Disable]
RttWr [RZQ/3]
RttPark [RZQ/1]
MemAddrCmdSetup [Auto]
MemCsOdtSetup [Auto]
MemCkeSetup [Auto]
MemCadBusClkDrvStren [24.0 Ohm]
MemCadBusAddrCmdDrvStren [20.0 Ohm]
MemCadBusCsOdtDrvStren [20.0 Ohm]
MemCadBusCkeDrvStren [24.0 Ohm]
Mem Over Clock Fail Count [Auto]
VDDCR CPU Load Line Calibration [Auto]
VDDCR CPU Current Capability [100%]
VDDCR CPU Switching Frequency [200]
VDDCR CPU Power Phase Control [Optimized]
VDDCR CPU Power Duty Control [T.Probe]
VDDCR SOC Load Line Calibration [Auto]
VDDCR SOC Current Capability [100%]
VDDCR SOC Switching Frequency [200]
VDDCR SOC Power Phase Control [Optimized]
VDDCR CPU Voltage [Auto]
VDDCR SOC Voltage [Manual]
VDDCR SOC Voltage Override [1.05000]
DRAM Voltage [1.35000]
VDDG CCD Voltage Control [1.000]
VDDG IOD Voltage Control [1.000]
CLDO VDDP Voltage [0.950]
1.0V SB Voltage [Auto]
1.2V SB Voltage [Auto]
CPU 1.80V Voltage [Auto]
VTTDDR Voltage [Auto]
VPP_MEM Voltage [Auto]
VDDP Standby Voltage [Auto]
CPU Core Current Telemetry [Auto]
CPU SOC Current Telemetry [Auto]
Security Device Support [Enable]
SHA-1 PCR Bank [Disabled]
SHA256 PCR Bank [Enabled]
SHA384 PCR Bank [Disabled]
Pending operation [None]
Platform Hierarchy [Enabled]
Storage Hierarchy [Enabled]
Endorsement Hierarchy [Enabled]
TPM 2.0 UEFI Spec Version [TCG_2]
Physical Presence Spec Version [1.3]
Disable Block Sid [Disabled]
Selects TPM device [Enable Discrete TPM]
Erase fTPM NV for factory reset [Enabled]
PSS Support [Enabled]
NX Mode [Enabled]
SVM Mode [Disabled]
SMT Mode [Auto]
Core Leveling Mode [Automatic mode]
SATA Port Enable [Enabled]
SATA Mode [AHCI]
NVMe RAID mode [Disabled]
SMART Self Test [Auto]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
Hot Plug [Disabled]
HD Audio Controller [Disabled]
PCIEX16_1 Mode [GEN 4]
PCIEX16_2 Mode [Auto]
PCIEX16_3 Mode [Auto]
PCIEX1_1 Mode [Auto]
PCIEX1_2 Mode [Auto]
M.2_1 Link Mode [GEN 4]
M.2_2 Link Mode [Auto]
SB Link Mode [Auto]
PCIEX16_1 Bandwidth Bifurcation Configuration [Auto Mode]
PCIEX16_2 Bandwidth Bifurcation Configuration [Auto Mode]
When system is in working state [Aura Off]
Intel LAN Controller [Auto]
USB power delivery in Soft Off state (S5) [Enabled]
ErP Ready [Disabled]
Restore AC Power Loss [Power Off]
Power On By PCI-E [Disabled]
Power On By RTC [Disabled]
Above 4G Decoding [Enabled]
Resize BAR Support [Auto]
SR-IOV Support [Disabled]
Legacy USB Support [Enabled]
XHCI Hand-off [Enabled]
JetFlashTranscend 64GB 1.00 [Auto]
Samsung Flash Drive FIT 1100 [Auto]
USB Device Enable [Enabled]
U32G1_9 [Enabled]
U32G1_7 [Enabled]
U32G1_8 [Enabled]
U32G1_2 [Enabled]
U32G2_C11 [Enabled]
USB3 [Enabled]
USB4 [Enabled]
U32G2_C4 [Enabled]
U32G2_5 [Enabled]
U32G2_6 [Enabled]
USB1 [Enabled]
USB2 [Enabled]
Network Stack [Disabled]
Device [N/A]
CPU Temperature [Monitor]
CPU Package Temperature [Monitor]
MotherBoard Temperature [Monitor]
T_Sensor Temperature [Monitor]
CPU Fan Speed [Monitor]
CPU Optional Fan Speed [Monitor]
Chassis Fan 1 Speed [Monitor]
Chassis Fan 2 Speed [Monitor]
M.2 Fan Speed [Monitor]
W_PUMP+ Speed [Monitor]
AIO PUMP Speed [Monitor]
PCH Fan Speed [Monitor]
CPU Core Voltage [Monitor]
3.3V Voltage [Monitor]
5V Voltage [Monitor]
12V Voltage [Monitor]
CPU Q-Fan Control [Auto]
CPU Fan Step Up [0 sec]
CPU Fan Step Down [0 sec]
CPU Fan Speed Lower Limit [200 RPM]
CPU Fan Profile [Standard]
Chassis Fan 1 Q-Fan Control [Auto]
Chassis Fan 1 Q-Fan Source [CPU]
Chassis Fan 1 Step Up [0 sec]
Chassis Fan 1 Step Down [0 sec]
Chassis Fan 1 Speed Low Limit [200 RPM]
Chassis Fan 1 Profile [Standard]
Chassis Fan 2 Q-Fan Control [Auto]
Chassis Fan 2 Q-Fan Source [CPU]
Chassis Fan 2 Step Up [0 sec]
Chassis Fan 2 Step Down [0 sec]
Chassis Fan 2 Speed Low Limit [200 RPM]
Chassis Fan 2 Profile [Standard]
WATER PUMP+ Control [Disabled]
AIO PUMP Control [Disabled]
M.2 Fan Q-Fan Control [Auto]
M2 Q-Fan Source [CPU]
M.2 Fan Step Up [0 sec]
M.2 Fan Step Down [0 sec]
M.2 Fan Speed Low Limit [200 RPM]
M.2 Fan Profile [Standard]
Above 4GB MMIO Limit [39bit (512GB)]
Fast Boot [Enabled]
Next Boot after AC Power Loss [Normal Boot]
Boot Logo Display [Auto]
POST Delay Time [3 sec]
Bootup NumLock State [On]
Wait For 'F1' If Error [Enabled]
Option ROM Messages [Force BIOS]
Interrupt 19 Capture [Disabled]
AMI Native NVMe Driver Support [Auto]
Setup Mode [Advanced Mode]
Launch CSM [Disabled]
OS Type [Windows UEFI mode]
Flexkey [Reset]
Load from Profile [1]
Profile Name [1866_lowvolFB]
Save to Profile [2]
DIMM Slot Number [DIMM_A2]
Bus Interface [PCIEX16_1]
Download & Install ARMOURY CRATE app [Enabled]
Overclock [Auto]
Power Down Enable [Auto]
Cmd2T [Auto]
Gear Down Mode [Auto]
CAD Bus Timing User Controls [Auto]
CAD Bus Drive Strength User Controls [Auto]
Data Bus Configuration User Controls [Auto]
Infinity Fabric Frequency and Dividers [Auto]
ECO Mode [Disable]
Precision Boost Overdrive [Auto]
LN2 Mode [Auto]
SoC/Uncore OC Mode [Disabled]
VDDP Voltage Control [Auto]
VDDG Voltage Control [Auto]
NUMA nodes per socket [Auto]
LCLK DPM [Auto]
LCLK DPM Enhanced PCIe Detection [Auto]
Core Performance Boost [Auto]
Global C-state Control [Auto]
IOMMU [Auto]
TSME [Auto]
Custom Pstate0 [Auto]
L1 Stream HW Prefetcher [Auto]
L2 Stream HW Prefetcher [Auto]
Core Watchdog Timer Enable [Auto]
Power Supply Idle Control [Auto]
SEV ASID Count [Auto]
SEV-ES ASID Space Limit Control [Auto]
Streaming Stores Control [Auto]
Local APIC Mode [Auto]
ACPI _CST C1 Declaration [Auto]
MCA error thresh enable [Auto]
PPIN Opt-in [Auto]
Fast Short REP MOVSB [Enabled]
Enhanced REP MOVSB/STOSB [Enabled]
IBS hardware workaround [Auto]
DRAM scrub time [Auto]
Poison scrubber control [Auto]
Redirect scrubber control [Auto]
Redirect scrubber limit [Auto]
NUMA nodes per socket [Auto]
Memory interleaving [Auto]
Memory interleaving size [Auto]
1TB remap [Auto]
DRAM map inversion [Auto]
ACPI SRAT L3 Cache As NUMA Domain [Auto]
ACPI SLIT Distance Control [Auto]
ACPI SLIT remote relative distance [Auto]
GMI encryption control [Auto]
xGMI encryption control [Auto]
CAKE CRC perf bounds Control [Auto]
4-link xGMI max speed [Auto]
3-link xGMI max speed [Auto]
xGMI TXEQ Mode [Auto]
PcsCG control [Auto]
Disable DF to external downstream IP SyncFloodPropagation [Auto]
Disable DF sync flood propagation [Auto]
CC6 memory region encryption [Auto]
Memory Clear [Auto]
Overclock [Auto]
Power Down Enable [Auto]
Disable Burst/Postponed Refresh [Auto]
DRAM Maximum Activate Count [Auto]
Cmd2T [Auto]
Gear Down Mode [Auto]
CAD Bus Timing User Controls [Auto]
CAD Bus Drive Strength User Controls [Auto]
Data Bus Configuration User Controls [Auto]
Data Poisoning [Auto]
DRAM Post Package Repair [Default]
RCD Parity [Auto]
DRAM Address Command Parity Retry [Auto]
Write CRC Enable [Auto]
DRAM Write CRC Enable and Retry Limit [Auto]
Disable Memory Error Injection [True]
DRAM ECC Symbol Size [Auto]
DRAM ECC Enable [Auto]
DRAM UECC Retry [Auto]
Data Scramble [Auto]
DFE Read Training [Auto]
FFE Write Training [Auto]
PMU Pattern Bits Control [Auto]
MR6VrefDQ Control [Auto]
CPU Vref Training Seed Control [Auto]
Chipselect Interleaving [Auto]
BankGroupSwap [Auto]
BankGroupSwapAlt [Auto]
Address Hash Bank [Auto]
Address Hash CS [Auto]
Address Hash Rm [Auto]
SPD Read Optimization [Enabled]
MBIST Enable [Disabled]
Pattern Select [PRBS]
Pattern Length(VMR) [6]
Aggressor Channel [1 Aggressor Channel]
Aggressor Static Lane Control [Disabled]
Target Static Lane Control [Disabled]
Worst Case Margin Granularity [Per Chip Select]
Read Voltage Sweep Step Size [1]
Read Timing Sweep Step Size [1]
Write Voltage Sweep Step Size [1]
Write Timing Sweep Step Size [1]
Precision Boost Overdrive [Auto]
Precision Boost Overdrive Scalar [Auto]
FCLK Frequency [Auto]
SOC OVERCLOCK VID [0]
UCLK DIV1 MODE [Auto]
VDDP Voltage Control [Auto]
VDDG Voltage Control [Auto]
SoC/Uncore OC Mode [Auto]
LN2 Mode [Auto]
ACS Enable [Auto]
PCIe ARI Support [Auto]
PCIe ARI Enumeration [Auto]
PCIe Ten Bit Tag Support [Auto]
cTDP Control [Auto]
EfficiencyModeEn [Auto]
Package Power Limit Control [Auto]
APBDIS [Auto]
DF Cstates [Auto]
CPPC [Auto]
CPPC Preferred Cores [Auto]
NBIO DPM Control [Auto]
Early Link Speed [Auto]
Presence Detect Select mode [Auto]
Preferred IO [Auto]
CV test [Auto]
Loopback Mode [Auto]
SRIS [Auto]
Data Link Feature Exchange [Disabled]


----------



## tcclaviger

WUT... these timings are sooo weird, but they work and test clean so... ¯\_(ツ)_/¯
Scored quite well in HWBOT benchmarks today, the weird thing, they're outperforming many people's 3800/3866 CL 14 and CL 12 so... maybe there's an actual advantage AIDA is not representing well....


----------



## PJVol

Veii said:


> Well that's far lower than usual expected results ~ Thermals


Your results are well inline with the others (in 2ccd 5600X owners club), and based on what I've seen so far, these are generally a bit worse performers compared to vanilla 5600x.
That, I believe is due to low SIDD nature of that 2nd CCD of "binned-out" 59x0. Cores can handle quite high CO magnitutes, but require higher voltages to reach the same frequency.
And no way 5600X would hit 290 in linpack unless chilled below 60. I've ran it two times with 28° and 30° mb sensor temps (you know how it correlate with ambient temps on ASRock boards (do you?  )
and the results differ by less than a second.


----------



## byDenoso

Oversemper said:


> Hello, Everybody! I was trying to get 1T command rate working without gear down mode, which seems impossible for my setup, but then just out of curiosity I've check T2 mode without gear down mode. And guess what, latency with T2 gear down mode OFF is about 1ns lower than T1 with gear down mode ON. But memtest bench is about 1.5 second longer. I did all tests multiple times (about 10 times each) to determine consistent results. Below screenshots and the rest of bios settings. Did not notice any difference for FPS in SotTR, PUBG or CS GO. In this situation which settings are best to use?
> T1 GearDownMode ON:
> View attachment 2519210
> View attachment 2519211
> 
> 
> T2 GearDownMode OFF:
> View attachment 2519212
> View attachment 2519213
> 
> 
> 
> 
> Spoiler: All bios settings (!long!)
> 
> 
> 
> [2021/07/29 21:03:56]
> Ai Overclock Tuner [Manual]
> BCLK Frequency [100.0000]
> SB Clock Spread Spectrum [Disabled]
> Performance Enhancer [Auto]
> Memory Frequency [DDR4-3733MHz]
> FCLK Frequency [1866MHz]
> CPU Core Ratio [Auto]
> Core VID [Auto]
> CCX0 Ratio [Auto]
> TPU [Keep Current Settings]
> Performance Bias [Auto]
> PBO Fmax Enhancer [Auto]
> Precision Boost Overdrive [Auto]
> Precision Boost Overdrive Scalar [Auto]
> Max CPU Boost Clock Override [Auto]
> Platform Thermal Throttle Limit [Auto]
> DRAM CAS# Latency [16]
> Trcdrd [19]
> Trcdwr [16]
> DRAM RAS# PRE Time [16]
> DRAM RAS# ACT Time [36]
> Trc [58]
> TrrdS [4]
> TrrdL [6]
> Tfaw [16]
> TwtrS [4]
> TwtrL [12]
> Twr [14]
> Trcpage [Auto]
> TrdrdScl [4]
> TwrwrScl [4]
> Trfc [545]
> Trfc2 [Auto]
> Trfc4 [Auto]
> Tcwl [16]
> Trtp [12]
> Trdwr [8]
> Twrrd [4]
> TwrwrSc [1]
> TwrwrSd [7]
> TwrwrDd [7]
> TrdrdSc [1]
> TrdrdSd [5]
> TrdrdDd [5]
> Tcke [1]
> ProcODT [43.6 ohm]
> Cmd2T [1T]
> Gear Down Mode [Enabled]
> Power Down Enable [Disabled]
> RttNom [Rtt_Nom Disable]
> RttWr [RZQ/3]
> RttPark [RZQ/1]
> MemAddrCmdSetup [Auto]
> MemCsOdtSetup [Auto]
> MemCkeSetup [Auto]
> MemCadBusClkDrvStren [24.0 Ohm]
> MemCadBusAddrCmdDrvStren [20.0 Ohm]
> MemCadBusCsOdtDrvStren [20.0 Ohm]
> MemCadBusCkeDrvStren [24.0 Ohm]
> Mem Over Clock Fail Count [Auto]
> VDDCR CPU Load Line Calibration [Auto]
> VDDCR CPU Current Capability [100%]
> VDDCR CPU Switching Frequency [200]
> VDDCR CPU Power Phase Control [Optimized]
> VDDCR CPU Power Duty Control [T.Probe]
> VDDCR SOC Load Line Calibration [Auto]
> VDDCR SOC Current Capability [100%]
> VDDCR SOC Switching Frequency [200]
> VDDCR SOC Power Phase Control [Optimized]
> VDDCR CPU Voltage [Auto]
> VDDCR SOC Voltage [Manual]
> VDDCR SOC Voltage Override [1.05000]
> DRAM Voltage [1.35000]
> VDDG CCD Voltage Control [1.000]
> VDDG IOD Voltage Control [1.000]
> CLDO VDDP Voltage [0.950]
> 1.0V SB Voltage [Auto]
> 1.2V SB Voltage [Auto]
> CPU 1.80V Voltage [Auto]
> VTTDDR Voltage [Auto]
> VPP_MEM Voltage [Auto]
> VDDP Standby Voltage [Auto]
> CPU Core Current Telemetry [Auto]
> CPU SOC Current Telemetry [Auto]
> Security Device Support [Enable]
> SHA-1 PCR Bank [Disabled]
> SHA256 PCR Bank [Enabled]
> SHA384 PCR Bank [Disabled]
> Pending operation [None]
> Platform Hierarchy [Enabled]
> Storage Hierarchy [Enabled]
> Endorsement Hierarchy [Enabled]
> TPM 2.0 UEFI Spec Version [TCG_2]
> Physical Presence Spec Version [1.3]
> Disable Block Sid [Disabled]
> Selects TPM device [Enable Discrete TPM]
> Erase fTPM NV for factory reset [Enabled]
> PSS Support [Enabled]
> NX Mode [Enabled]
> SVM Mode [Disabled]
> SMT Mode [Auto]
> Core Leveling Mode [Automatic mode]
> SATA Port Enable [Enabled]
> SATA Mode [AHCI]
> NVMe RAID mode [Disabled]
> SMART Self Test [Auto]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> Hot Plug [Disabled]
> HD Audio Controller [Disabled]
> PCIEX16_1 Mode [GEN 4]
> PCIEX16_2 Mode [Auto]
> PCIEX16_3 Mode [Auto]
> PCIEX1_1 Mode [Auto]
> PCIEX1_2 Mode [Auto]
> M.2_1 Link Mode [GEN 4]
> M.2_2 Link Mode [Auto]
> SB Link Mode [Auto]
> PCIEX16_1 Bandwidth Bifurcation Configuration [Auto Mode]
> PCIEX16_2 Bandwidth Bifurcation Configuration [Auto Mode]
> When system is in working state [Aura Off]
> Intel LAN Controller [Auto]
> USB power delivery in Soft Off state (S5) [Enabled]
> ErP Ready [Disabled]
> Restore AC Power Loss [Power Off]
> Power On By PCI-E [Disabled]
> Power On By RTC [Disabled]
> Above 4G Decoding [Enabled]
> Resize BAR Support [Auto]
> SR-IOV Support [Disabled]
> Legacy USB Support [Enabled]
> XHCI Hand-off [Enabled]
> JetFlashTranscend 64GB 1.00 [Auto]
> Samsung Flash Drive FIT 1100 [Auto]
> USB Device Enable [Enabled]
> U32G1_9 [Enabled]
> U32G1_7 [Enabled]
> U32G1_8 [Enabled]
> U32G1_2 [Enabled]
> U32G2_C11 [Enabled]
> USB3 [Enabled]
> USB4 [Enabled]
> U32G2_C4 [Enabled]
> U32G2_5 [Enabled]
> U32G2_6 [Enabled]
> USB1 [Enabled]
> USB2 [Enabled]
> Network Stack [Disabled]
> Device [N/A]
> CPU Temperature [Monitor]
> CPU Package Temperature [Monitor]
> MotherBoard Temperature [Monitor]
> T_Sensor Temperature [Monitor]
> CPU Fan Speed [Monitor]
> CPU Optional Fan Speed [Monitor]
> Chassis Fan 1 Speed [Monitor]
> Chassis Fan 2 Speed [Monitor]
> M.2 Fan Speed [Monitor]
> W_PUMP+ Speed [Monitor]
> AIO PUMP Speed [Monitor]
> PCH Fan Speed [Monitor]
> CPU Core Voltage [Monitor]
> 3.3V Voltage [Monitor]
> 5V Voltage [Monitor]
> 12V Voltage [Monitor]
> CPU Q-Fan Control [Auto]
> CPU Fan Step Up [0 sec]
> CPU Fan Step Down [0 sec]
> CPU Fan Speed Lower Limit [200 RPM]
> CPU Fan Profile [Standard]
> Chassis Fan 1 Q-Fan Control [Auto]
> Chassis Fan 1 Q-Fan Source [CPU]
> Chassis Fan 1 Step Up [0 sec]
> Chassis Fan 1 Step Down [0 sec]
> Chassis Fan 1 Speed Low Limit [200 RPM]
> Chassis Fan 1 Profile [Standard]
> Chassis Fan 2 Q-Fan Control [Auto]
> Chassis Fan 2 Q-Fan Source [CPU]
> Chassis Fan 2 Step Up [0 sec]
> Chassis Fan 2 Step Down [0 sec]
> Chassis Fan 2 Speed Low Limit [200 RPM]
> Chassis Fan 2 Profile [Standard]
> WATER PUMP+ Control [Disabled]
> AIO PUMP Control [Disabled]
> M.2 Fan Q-Fan Control [Auto]
> M2 Q-Fan Source [CPU]
> M.2 Fan Step Up [0 sec]
> M.2 Fan Step Down [0 sec]
> M.2 Fan Speed Low Limit [200 RPM]
> M.2 Fan Profile [Standard]
> Above 4GB MMIO Limit [39bit (512GB)]
> Fast Boot [Enabled]
> Next Boot after AC Power Loss [Normal Boot]
> Boot Logo Display [Auto]
> POST Delay Time [3 sec]
> Bootup NumLock State [On]
> Wait For 'F1' If Error [Enabled]
> Option ROM Messages [Force BIOS]
> Interrupt 19 Capture [Disabled]
> AMI Native NVMe Driver Support [Auto]
> Setup Mode [Advanced Mode]
> Launch CSM [Disabled]
> OS Type [Windows UEFI mode]
> Flexkey [Reset]
> Load from Profile [1]
> Profile Name [1866_lowvolFB]
> Save to Profile [2]
> DIMM Slot Number [DIMM_A2]
> Bus Interface [PCIEX16_1]
> Download & Install ARMOURY CRATE app [Enabled]
> Overclock [Auto]
> Power Down Enable [Auto]
> Cmd2T [Auto]
> Gear Down Mode [Auto]
> CAD Bus Timing User Controls [Auto]
> CAD Bus Drive Strength User Controls [Auto]
> Data Bus Configuration User Controls [Auto]
> Infinity Fabric Frequency and Dividers [Auto]
> ECO Mode [Disable]
> Precision Boost Overdrive [Auto]
> LN2 Mode [Auto]
> SoC/Uncore OC Mode [Disabled]
> VDDP Voltage Control [Auto]
> VDDG Voltage Control [Auto]
> NUMA nodes per socket [Auto]
> LCLK DPM [Auto]
> LCLK DPM Enhanced PCIe Detection [Auto]
> Core Performance Boost [Auto]
> Global C-state Control [Auto]
> IOMMU [Auto]
> TSME [Auto]
> Custom Pstate0 [Auto]
> L1 Stream HW Prefetcher [Auto]
> L2 Stream HW Prefetcher [Auto]
> Core Watchdog Timer Enable [Auto]
> Power Supply Idle Control [Auto]
> SEV ASID Count [Auto]
> SEV-ES ASID Space Limit Control [Auto]
> Streaming Stores Control [Auto]
> Local APIC Mode [Auto]
> ACPI _CST C1 Declaration [Auto]
> MCA error thresh enable [Auto]
> PPIN Opt-in [Auto]
> Fast Short REP MOVSB [Enabled]
> Enhanced REP MOVSB/STOSB [Enabled]
> IBS hardware workaround [Auto]
> DRAM scrub time [Auto]
> Poison scrubber control [Auto]
> Redirect scrubber control [Auto]
> Redirect scrubber limit [Auto]
> NUMA nodes per socket [Auto]
> Memory interleaving [Auto]
> Memory interleaving size [Auto]
> 1TB remap [Auto]
> DRAM map inversion [Auto]
> ACPI SRAT L3 Cache As NUMA Domain [Auto]
> ACPI SLIT Distance Control [Auto]
> ACPI SLIT remote relative distance [Auto]
> GMI encryption control [Auto]
> xGMI encryption control [Auto]
> CAKE CRC perf bounds Control [Auto]
> 4-link xGMI max speed [Auto]
> 3-link xGMI max speed [Auto]
> xGMI TXEQ Mode [Auto]
> PcsCG control [Auto]
> Disable DF to external downstream IP SyncFloodPropagation [Auto]
> Disable DF sync flood propagation [Auto]
> CC6 memory region encryption [Auto]
> Memory Clear [Auto]
> Overclock [Auto]
> Power Down Enable [Auto]
> Disable Burst/Postponed Refresh [Auto]
> DRAM Maximum Activate Count [Auto]
> Cmd2T [Auto]
> Gear Down Mode [Auto]
> CAD Bus Timing User Controls [Auto]
> CAD Bus Drive Strength User Controls [Auto]
> Data Bus Configuration User Controls [Auto]
> Data Poisoning [Auto]
> DRAM Post Package Repair [Default]
> RCD Parity [Auto]
> DRAM Address Command Parity Retry [Auto]
> Write CRC Enable [Auto]
> DRAM Write CRC Enable and Retry Limit [Auto]
> Disable Memory Error Injection [True]
> DRAM ECC Symbol Size [Auto]
> DRAM ECC Enable [Auto]
> DRAM UECC Retry [Auto]
> Data Scramble [Auto]
> DFE Read Training [Auto]
> FFE Write Training [Auto]
> PMU Pattern Bits Control [Auto]
> MR6VrefDQ Control [Auto]
> CPU Vref Training Seed Control [Auto]
> Chipselect Interleaving [Auto]
> BankGroupSwap [Auto]
> BankGroupSwapAlt [Auto]
> Address Hash Bank [Auto]
> Address Hash CS [Auto]
> Address Hash Rm [Auto]
> SPD Read Optimization [Enabled]
> MBIST Enable [Disabled]
> Pattern Select [PRBS]
> Pattern Length(VMR) [6]
> Aggressor Channel [1 Aggressor Channel]
> Aggressor Static Lane Control [Disabled]
> Target Static Lane Control [Disabled]
> Worst Case Margin Granularity [Per Chip Select]
> Read Voltage Sweep Step Size [1]
> Read Timing Sweep Step Size [1]
> Write Voltage Sweep Step Size [1]
> Write Timing Sweep Step Size [1]
> Precision Boost Overdrive [Auto]
> Precision Boost Overdrive Scalar [Auto]
> FCLK Frequency [Auto]
> SOC OVERCLOCK VID [0]
> UCLK DIV1 MODE [Auto]
> VDDP Voltage Control [Auto]
> VDDG Voltage Control [Auto]
> SoC/Uncore OC Mode [Auto]
> LN2 Mode [Auto]
> ACS Enable [Auto]
> PCIe ARI Support [Auto]
> PCIe ARI Enumeration [Auto]
> PCIe Ten Bit Tag Support [Auto]
> cTDP Control [Auto]
> EfficiencyModeEn [Auto]
> Package Power Limit Control [Auto]
> APBDIS [Auto]
> DF Cstates [Auto]
> CPPC [Auto]
> CPPC Preferred Cores [Auto]
> NBIO DPM Control [Auto]
> Early Link Speed [Auto]
> Presence Detect Select mode [Auto]
> Preferred IO [Auto]
> CV test [Auto]
> Loopback Mode [Auto]
> SRIS [Auto]
> Data Link Feature Exchange [Disabled]


Try bump clkdrvstr to 40/60ohms if you wanna to get 1T stable.


----------



## gled_fr

Ahha finally a stable cl14 ( ok at 1.5V VDIMM ):








OK, just joking, I just set the primary timings, all secondaries/tertiaries are on auto. the good news is it's stable. The bad is it's all auto and feel very loose, and it's VDIMM 1.5V

I also had to set the RTT* to 6 3 3 and the *DrvStr 40 20 30 20 or it would not boot on auto ( I did no try other settings ).

ProcOdt on auto was booting at 60. Felt too high so I toned it down as seen on the screenshot.

Now to get those subtimings in control and try to lower vdimm !


----------



## Dasa

gled_fr said:


> Now to get those subtimings in control and try to lower vdimm !


I wouldn't be worried about 1.5v.
I am happy with 1.56v for 24\7 use but do have a fan blowing directly over the sticks.


----------



## mongoled

Veii said:


> Yea, the possibility is surely there
> The chance is very low, as there are +90% casuals, yet from these not many return the board unless it has post issues or some other bad experience
> A bios post issue, is probably the best thing you can get on such. 14 Days refund policy is not that long tho
> Another option are RMA for repair boards which hopefully where repaired or ones that have coil whine
> I can agree well, that warehouse items often have user-dislike issues, soo you might also dislike it at some point
> 
> Tho when it comes to ebay or generally 2nd hand
> Close to everything i own is 2nd hand
> I do buy new medical items and headsets. Probably other consume items too, soo bathroom stuff, cloths
> Chairs are complicated, they are often overpriced and used is not hygienical either - soo it really depends
> 
> As for barebones electronic, close to everything that is repairable is 2nd hand for me personally
> Monitors 100% so far (got a Samsung U32J590UQU for 150€ ~ it running 4k was just a free bonus & early my AOC Q3279VWFD8 for 130-140 bucks, as my main gaming unit)
> Mice was used, storage is complicated but was used in good condition. Keyboards are complicated between hygienic or not. Soundcards are used, desks are used
> I like saving money, when there is barely for food or rent 🤭
> 
> On Amazon warehouse, generally shops you have no refund possibility ~ such is complicated to do
> Ebay is the same but at least you see the goods picture
> Amazon seems to barely pass, as you can still send it back ~ yet generally in understand both sides very well
> Would i only buy new, i wouldn't have half of what i own right now.
> Neither a chair, nor a 2nd monitor for the 2nd build-in-progress pc
> Or a desk.
> 
> Well ok, beds and mattresses i wouldn't buy used, clearly not without inspection and clearly not if it isn't washable
> That is on the same line as cloths. Possible, but i'd rather not and skip this route
> Bed frames on the other hand, or wardrobe's, other furniture ~ why not. As long as it doesn't come from a smokers home (you can't wash wood, heh)
> But mostly only physical repairable gear and nothing hygienical.


Thats the thing, we have no idea why things end up at Amazon Warehouse, but looking at my past history of buying "new" items from Amazon and noticing that they are not new means to me that its more probable that those who are "dishonest" in the items they send back and the reasons they send them back will have more chance of making it to Amazon Warehouse than regular Amazon depot.

Regards 2nd hand items, somehow I place more value on these items than those that go to Amazon Warehouse as there is a chance that these items were actually used by those who are selling them so there is an "emotional" value of the product that is being sold meaning a higher probability that the item will actually function as advertised (yes, I am taking a leap of faith here).

Of course "needs must" as with most people sometime in our lives we buy and still buy second hand items.


----------



## XPEHOPE3

What are the OCCT recommended stability test settings? 1 hour AVX large-extreme-variable?


----------



## Oversemper

byDenoso said:


> Try bump clkdrvstr to 40/60ohms if you wanna to get 1T stable.


That was über-advice! I just set MemCadBusClkDrvStren to 60 Ohm and T1 without GDM just works stable! Without bumping any voltages! Memtest, ramtest, IBM, Prime95, Cinebench r23, all without errors. But latency in AIDA64 at T1 GDM OFF is ~0.2ns *bigger* than at T2, which is unexplainable to me. But membench finishes faster both than T2 and T1 GDM ON:


----------



## byDenoso

Oversemper said:


> That was über-advice! I just set MemCadBusClkDrvStren to 60 Ohm and T1 without GDM just works stable! Without bumping any voltages! Memtest, ramtest, IBM, Prime95, Cinebench r23, all without errors. But latency in AIDA64 at T1 GDM OFF is ~0.2ns *bigger* than at T2, which is unexplainable to me. But membench finishes faster both than T2 and T1 GDM ON:
> View attachment 2519269
> View attachment 2519270
> View attachment 2519271


Probably because your tRFC, you must set the 2 and 4 values too, fix it.
With your timings it must be: tRFC: 464 tRFC2:345 tRFC4:212
You'll get a lower latency.


----------



## gled_fr

Finally getting the subtimings down on cl14, still some work to do, but I was hoping for better latency than that already ( 54.7-54.8 at cl15 with better subs ):








BTW, what is better ?
Trp 15 tras 24 TRC 39
Or 
Trp 14 tras 25 TRC 39 ?

It seems like I have some errors with TRC 38, and TRC = trp + tras but it doss not seem to make a difference one or the other


----------



## Kildar

This is what I have.
Does anyone think I can improve it?


----------



## sendap

looks like subtimings are on AUTO and very lose. Also your AIDA ver is very old.


----------



## Veii

Kildar said:


> This is what I have.
> Does anyone think I can improve it?
> 
> View attachment 2519293


GDM off, 2T, tCL 15, tFAW 48
900mV cLDO_VDDP at worst 950mV
10mV more SOC - your loadline droops to much
tCKE 9 for 3800MT/s
tRTP 8 or 16,
tWR 16 or 32
generally tRC 50

Anything you can improve:
Close to everything, but you'll notice once you disable GDM and issues start to show


----------



## Oversemper

byDenoso said:


> Probably because your tRFC, you must set the 2 and 4 values too, fix it.
> With your timings it must be: tRFC: 464 tRFC2:345 tRFC4:212
> You'll get a lower latency.


Before I've tried (arbitrarily) 450 and 500 for tRFC, both times required CMOS clearing to POST. It was due to unfortunate numbers or RAM cannot work below the current value? I've took 545 from the dram calc. Any settings may help to lower tRFC to 464?


----------



## Mach3.2

Oversemper said:


> Before I've tried (arbitrarily) 450 and 500 for tRFC, both times required CMOS clearing to POST. It was due to unfortunate numbers or RAM cannot work below the current value? I've took 545 from the dram calc. Any settings may help to lower tRFC to 464?


Micron Rev. E can't do very low tRFC, about 290ns is all you gonna get, maybe 280+ns if you're lucky.
Try:
tRFC: 545
tRFC2: 405
tRFC4: 249

Check this out, courtesy of Veii.


----------



## Veii

@Mach3.2 i think linking the timings soo @Oversempler has options to try - might be more worth
Mini docs has no *11 or *12 mode for Rev.E
He/she will likely not notice this little imprint either 🤭


----------



## Mach3.2

Veii said:


> @Mach3.2 i think linking the timings soo @Oversempler has options to try - might be more worth
> Mini docs has no *11 or *12 mode for Rev.E
> He/she will not notice this little imprint either 🤭
> View attachment 2519309


You meant the Ryzen Google Calculator spreadsheet? 😅


----------



## byDenoso

Oversemper said:


> Before I've tried (arbitrarily) 450 and 500 for tRFC, both times required CMOS clearing to POST. It was due to unfortunate numbers or RAM cannot work below the current value? I've took 545 from the dram calc. Any settings may help to lower tRFC to 464?


You can try tRFC 580, tRFC2 431 and tRFC4 265
Also try Drop your tRTP to 5 and tWR to 10 and test again.


----------



## Oversemper

Mach3.2 said:


> Micron Rev. E can't do very low tRFC, about 290ns is all you gonna get, maybe 280+ns if you're lucky.
> Try:
> tRFC: 545
> tRFC2: 405
> tRFC4: 249





byDenoso said:


> You can try tRFC 580, tRFC2 431 and tRFC4 265
> Also try Drop your tRTP to 5 and tWR to 10 and test again.


Set 545/405/249 and latency is a tad bit lower, consistently. Later check tRTP 5 and tWR 10. Your advice is much appreciated!


----------



## Mach3.2

Oversemper said:


> Set 545/405/249 and latency is a tad bit lower, consistently. Later check tRTP 5 and tWR 10. Your advice is much appreciated!
> View attachment 2519313
> View attachment 2519314


by the way you can try tRC = tRAS + tRP too. tRC should be 52.


----------



## Veii

Mach3.2 said:


> You meant the Ryzen Google Calculator spreadsheet? 😅


This post [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread 6 presets
cLDO_VDDP voltage just defines MCLK range
But 4 dimms might need doubled tWR
and +2 steps on RTT_PARK soo -2 on the divider = more ohm


----------



## byDenoso

Is this a good result?


----------



## gled_fr

Is there a real benefit to run cl14 vs cl15 ?

At that point I don't see a diff in Aida, actually write speed is a bit lower on cl14 vs 15, timings are more relaxed, and vdimm at 1.5.

Seems like I can't break that 54.8ns latency, same latency between cl14 and 15 and slightly worse write perf.

Should I just go ahead and forget about 14, instead try to get IF1933 working without WHEA ?


----------



## XPEHOPE3

I think this is the best I can do regarding RAM, at least on this BIOS (beta one, with AGESA 1.2.0.3b)

Notes on changes tried:

GDM off 1T won't give in, see above.
GDM on 1T gives slightly higher latency and slightly lower read and copy bandwidth, contrary to @Blameless ' suggestion.
tRRDS-tWTRL 4-5-16-3-12 can be made stable on tPHYRDL 26/26 with some VDDP, but neither latency nor bandwidth improve
tRCDWR 8 is stable and gives +100MB/s copy speed, but latency would be 55.4-ish
SCLs-tRDWR-tWRRD can be made stable at 2-10-6 and 2-8-8, but without any improvements


Spoiler: 2-10-6










56173/55352/55.1-55.4 read/copy/latency





Spoiler: 2-8-8










56330/55384/55.2-55.4


Also TM5 test time was worse than with


Spoiler: 5-9-5










56372/55550/55.3-55.4



SD/DD 5-5-7-7 give worse bandwidth and latency. Anything like 3 and below produces repeated POST attempts until BIOS succumbs to JEDEC or I have to shut it down.
tRFC 384 (below 200 ns) gives errors with any tRC/tRTP. tRTP 8 gives errors, as well as tRAS 30.
I had 16-15-15-15-36-56 TM5 stable one day, but after a week it won't pass TM5 with single error 4. Even if it was stable, performance almost didn't improve: 56647/55612/54.9-55.1, one 54.7
I think I need to start OCing CPU. It surely will improve bandwidth, but I feel it might also improve latency.

I hope to reproduce these settings on non-beta BIOS, then OC CPU. Then maybe revert CPU OC and try GDM off 1T from scratch (XMP + GDM off + 1T). But I don't feel any motivation for 1T as I didn't see much performance difference. Sure there was bandwidth bump, maybe it would be even higher with CPU OC, but latency also bumped, and I'm not alone like this.


----------



## Yviena

Does anyone what the issue could be that sometimes windows just stops booting , like USB just stops receiving power after the windows loading logo, and i need to reboot multiple times? it doesn't seem to be due to Curve optimizer, as it still happened with it disabled.


----------



## gled_fr

XPEHOPE3 said:


> View attachment 2519357
> 
> 
> I think this is the best I can do regarding RAM, at least on this BIOS (beta one, with AGESA 1.2.0.3b)
> 
> Notes on changes tried:
> 
> GDM off 1T won't give in, see above.
> GDM on 1T gives slightly higher latency and slightly lower read and copy bandwidth, contrary to @Blameless ' suggestion.
> tRRDS-tWTRL 4-5-16-3-12 can be made stable on tPHYRDL 26/26 with some VDDP, but neither latency nor bandwidth improve
> tRCDWR 8 is stable and gives +100MB/s copy speed, but latency would be 55.4-ish
> SCLs-tRDWR-tWRRD can be made stable at 2-10-6 and 2-8-8, but without any improvements
> 
> 
> Spoiler: 2-10-6
> 
> 
> 
> 
> View attachment 2519358
> 56173/55352/55.1-55.4 read/copy/latency
> 
> 
> 
> 
> 
> Spoiler: 2-8-8
> 
> 
> 
> 
> View attachment 2519359
> 56330/55384/55.2-55.4
> 
> 
> Also TM5 test time was worse than with
> 
> 
> Spoiler: 5-9-5
> 
> 
> 
> 
> View attachment 2519361
> 56372/55550/55.3-55.4
> 
> 
> 
> SD/DD 5-5-7-7 give worse bandwidth and latency. Anything like 3 and below produces repeated POST attempts until BIOS succumbs to JEDEC or I have to shut it down.
> tRFC 384 (below 200 ns) gives errors with any tRC/tRTP. tRTP 8 gives errors, as well as tRAS 30.
> I had 16-15-15-15-36-56 TM5 stable one day, but after a week it won't pass TM5 with single error 4. Even if it was stable, performance almost didn't improve: 56647/55612/54.9-55.1, one 54.7
> I think I need to start OCing CPU. It surely will improve bandwidth, but I feel it might also improve latency.
> 
> I hope to reproduce these settings on non-beta BIOS, then OC CPU. Then maybe revert CPU OC and try GDM off 1T from scratch (XMP + GDM off + 1T). But I don't feel any motivation for 1T as I didn't see much performance difference. Sure there was bandwidth bump, maybe it would be even higher with CPU OC, but latency also bumped, and I'm not alone like this.


Do you have those settings with the WHEA silencer on ?

I 'may' have copied your voltage and try running OCCT like you, I am seeing less WHEA than usual it seems at IF1933


----------



## Blameless

XPEHOPE3 said:


> GDM on 1T gives slightly higher latency and slightly lower read and copy bandwidth, contrary to @Blameless ' suggestion.


GDM enabled should make T1 and T2 command rate identical (at 2T) and round every odd timing up to the next even number.

At settings I can run GDM off, if I'm running 2T command rate and all even timings, turning GDM on is almost within margin of error.

What sort of difference are you seeing?



XPEHOPE3 said:


> tRRDS-tWTRL 4-5-16-3-12 can be made stable on tPHYRDL 26/26 with some VDDP, but neither latency nor bandwidth improve


I haven't noticed any difference between tPHYRDLs, in and of themselves either. There may be some, but if so, it's below noise level/boot to boot training variance.



XPEHOPE3 said:


> tRFC 384 (below 200 ns) gives errors with any tRC/tRTP. tRTP 8 gives errors, as well as tRAS 30.


Probably a side effect of the four DIMMs. Sometimes increasing memory VPP can help, but often not.



Yviena said:


> Does anyone what the issue could be that sometimes windows just stops booting , like USB just stops receiving power after the windows loading logo, and i need to reboot multiple times? it doesn't seem to be due to Curve optimizer, as it still happened with it disabled.


I've had borderline memory training do this. Tuning drive strengths has helped me in the past. No guarantee it's the same issue for you, however.


----------



## Yviena

Hmm the third value at 30-40ohm should have fix the memory training tho.


----------



## XPEHOPE3

Blameless said:


> There may be some, but if so, it's below noise level/boot to boot training variance.


For your setup maybe, but for me +2 tPHYRDL means +0.6ns latency. +2/+2 means +1ns suggesting non-linear increase.


Blameless said:


> What sort of difference are you seeing?


I believe it was latency 56+ (56-56.4-ish), reads 56200-ish. It was so bad, I didn't bother screening or writing it down. Yes, tPHYRDL were 28/28 just as with GDM off 1T



Blameless said:


> Sometimes increasing memory VPP can help, but often not.


I don't think I even have this in BIOS  but maybe... Thank you anyway.



gled_fr said:


> Do you have those settings with the WHEA silencer on ?


I don't seem to need it, never had a WHEA in event log, even when testing GDM off 1T produced BSODs.


----------



## Veii

Dasa said:


> I wouldn't be worried about 1.5v.
> I am happy with 1.56v for 24\7 use but do have a fan blowing directly over the sticks.


+1
sub 1.52 with the old harsh RTTs by DRAM Calculator
till 1.6v once you lower RTT_PARK by 1 step (/1 to /2 - or /5 to /6)
till 1.7v (mostly b-die destabilizes at 1.68v) - when you drop it two more /4 or /7

Have no thermal issues at all with 1.65v
But have voltage crash issues, a hardlimit at 1.68v with these B-Dies
Rev.E was similar, sub 45c at worst ~ but the hardlimit was 1.72v there
No reason to fear voltage, as long as you adjust "powering" a bit


gled_fr said:


> Is there a real benefit to run cl14 vs cl15 ?
> 
> At that point I don't see a diff in Aida, actually write speed is a bit lower on cl14 vs 15, timings are more relaxed, and vdimm at 1.5.


Barely to my experience
There was at least a 4ns difference on Hynix and Rev.E instead of running 16-18 or 18-19 , just running 14-18 ~ considering tRCD wall doesn't move at all, soo voltage goes only towards tertiaries & transition timings
But honestly on b-die ~ no
On Rev.E the difference between tCL 14 , tCWL 14 (with lower tRDWR as that gives a lot of bandwidth)
vs CL13 , tCWL12 , was deminishing. Maaybe 0.5ns at best , but that would also mean generally lower tRC and more voltage

Flat primaries generally outperform it close to always.
tCL13 , tCWL 10 for example performed worse than tCL13 tCWL 12
The addition you had to push on tRDWR ~ was starting to be negative and eat more latency and bandwidth, than tCWL did give at 10
tCL 12 then needed beyond 1.7+ which was not feesable unless i hold them sub 30c (possible, but then the bios training also plays a role into this).
To quote buildzoid
"What is a 12. This bios doesn't understand what CL12 means" 🤭

Answer is, no 
Match tCL with tRCD and you'll have a good time
Drop tCL -1 and you will need to adapt tCWL.
It can give a bit of bandwidth, but bellow tCWL 14 you start to have diminishing returns and bellow tCWL 12 ~ the tRDWR requirement just is not cutting it = negative scaling


Yviena said:


> Does anyone what the issue could be that sometimes windows just stops booting , like USB just stops receiving power after the windows loading logo, and i need to reboot multiple times? it doesn't seem to be due to Curve optimizer, as it still happened with it disabled.


If you mean BSOD on boot - sometimes, but that was after one crash or failed boot
Pressing couple times enter or CTRL+ALT+DEL once, and it will post ~ then run by itself SysMain service and storage management service in order to repair itself
Soo after such an event, you likely want to wait 1-2 min and reboot again. Else all your benchmark results will be skewed


XPEHOPE3 said:


> GDM on 1T gives slightly higher latency and slightly lower read and copy bandwidth, contrary to @Blameless ' suggestion.











This is the difference when timings don't play a role
I lost the tCL 16 comparison ontop of this pic

GDM does run 2T on the timings and rounds, but it does start as 1T ~ what you pick there doesn't change the behavior, as it's GDM ON or OFF, no T mode influence
Bandwidth is slightly higher, tiny tiny bit
But it does round timings, prevent odd tWR & tRTP. Lowers internal MUX frequency to half ~ faking the lowest tRFC you can run and hides powering issues you instantly will see once you go to 2T
2T doesn't require any vdimm increase, even when "pcb strain" returns to normal
1T does require far more work.

The only reason the picture says 2.5T, is because people offput it before as 1.5T
In easy math theory , 1T+2T+1T = 1.5T if you round down
But it's more 2.5T than 1.5T , as this is not DDR3 anymore.


XPEHOPE3 said:


> but for me +2 tPHYRDL means +0.6ns latency. +2/+2 means +1ns suggesting non-linear increase.


But PHY training values have no influence on powering or PCB strain
That's a bios thing and a training thing
Command rate is a memory PCB thing and has no connection to Memory training (nearly non)

Two different things, sadly with unfortunate outcomes for your setup
But still completely different things with no connection in between


pewpewlazer said:


> Tried bumping up to ddr3800/1900 fclk tonight and was able to run AIDA64 and then start TM5, but after a few minutes it straight up rebooted. No BSOD, no WHEA, no freezing, just reboot. Left it idle on the desktop while finishing my dinner and it rebooted again. After that, it would continue to reboot as soon as it loaded Windows. Bumping vDIMM from 1.41v -> 1.45v had zero affect.
> 
> Is this an FCLK stability issue? Are there any settings that can help here besides playing with vSOC (currently at 1.0875, tried 1.125 as well) and vDDG (both currently at 0.9976v)?


Would've been great if you attached any ZenTimings screenshots

Likely just bad memory training, well rather missmatching CAD_BUS values
3rd value aside for helping with memory training, also helps Cold & Warm boot issues
It generally creates more heat and more strain to the board - but helps out
Vermeer likes 30+ here, Matisse liked 24+ here
CsOdtDrvStr
* i found that 40ohm was needed for Vermeer's broken memory training, but that strongly depends on how procODT and ClkDrvStr behave
soo 30-20-30-20
40-20-40-20
40-20-30-24
60-20-20-24
it really depends 


PJVol said:


> And no way 5600X would hit 290 in linpack unless chilled below 60.


Chilled indeed, but that should be resolvable ~ yet the tracking fact stays sadly that there is a huge perf loss because of useless thermal limits. Heatpipes can not work on such low temp optimally


PJVol said:


> Your results are well inline with the others (in 2ccd 5600X owners club), and based on what I've seen so far, these are generally a bit worse performers compared to vanilla 5600x.


Mmm , i acknowledge the powerbudget cut thanks to the 2nd active CCD for me, but it's at this point not even an EDC FUSE limit
Such was a very bad design choice by AMD.
It can not use the reason of "stress prevention for the fabric" with their 122A EDC fuse limit.
This one is a purely unlogical limit ~ which will degrade performance on any possible usecase.
GPUs will heat up the case. There is no way how you can keep the Delta-T that low , to prevent frequency throttle on any games.
When 90W already is too much dense heat to cool away without lapping it or using any +120mm AIO

You seem to boost higher than me 


XPEHOPE3 said:


> Is VDIMM the only thing possible to stabilize 1T?


Only thing possible ?
Well timings issues will be shown , but it's mostly tRFC related or tRRD, tWTR.
2T command rate "timings" behave close to identical as to 1T "timings"
the "chain" is the same, and their timing is identical
* _Any primaries that run on 2T will run on 1T without issues, but anything around them which depends on PCB strain ~ will behave different and can easily require more VDIMM_

I think powering plays a big role and PCB strain (which falls into the powering category)
Between GDM and 2T there is no VDIMM push required tho 
1T is something else, but working with 2T makes more sense
Because unlike GDM changes ~ GDM on, timings pretty much are worthless when you go to 2T
These timings where based upon half-frequency MUX and pretty much half resulting PCB strain.
All of them can be called "fake" upon GDM off 2T change ~ which is why for this tiny tiny bit potentially more bandwidth on GDM ~ it makes no sense to bother with it
The results are too small and you start with a bad foundation.
It's far too much waste of time ~ and only comparable if you have only flat timings to compare with. Else rounding will happen and skew your comparison results
* The picture above was build upon a foundation of Burst Refresh and burst transitions. Soo it will show differences up to how long "the chain" takes to be processed.
And when it runs on half speed, such is significantly shown
It's using an exploit as foundation & i changed timing behavior since AGESA 1.1.0.0 Patch A - but the differences are clear
Oh and it uses a different powerplan when we could actually utilize deep-sleep states , soo the boost frequency was 4.65Ghz ~ visible on the 10.9ns cache delay
Sadly these days, overboost [bug] is too random & i can not count on the boosting taking equal time & being consistent, as it was before. Soo the PP is not used anymore


----------



## XPEHOPE3

Veii said:


> But PHY training values have no influence on powering or PCB strain
> That's a bios thing and a training thing
> Command rate is a memory PCB thing and has no connection to Memory training (nearly non)
> 
> Two different things, sadly with unfortunate outcomes for your setup
> But still completely different things with no connection in between


I think there is this connection:

PCB strain results from current and that can vary from load
GDM off 1T obviously means more load "somewhere" compared to GDM off 2T. I presume, only on address and command buses
That means, for example, ACT commands are encountered up to 2 times as often, meaning tRRD_ timings required may need a bump (so that ACT commands would require as little current as on 2T)
Since those timings are unchanged in the example, training process sees failures and tries to lower number of incoming commands (and therefore current requirements) by bumping non-auto timings, tPHYRDL one of those.
Also I don't understand why do you keep reposting that obsoleted screenshot with old AGESA and 2.5T instead of redoing the experiment. Proper science means replication of results  Maybe you'll also see bandwidth loss. Or, for example, confirm my experience that setting GDM on 2T might not even POST when GDM off 2T/1T POST Ok, as well as GDM on 1T.


----------



## gled_fr

Veii said:


> +1
> sub 1.52 with the old harsh RTTs by DRAM Calculator
> till 1.6v once you lower RTT_PARK by 1 step (/1 to /2 - or /5 to /6)
> till 1.7v (mostly b-die destabilizes at 1.68v) - when you drop it two more /4 or /7
> 
> Have no thermal issues at all with 1.65v
> But have voltage crash issues, a hardlimit at 1.68v with these B-Dies
> Rev.E was similar, sub 45c at worst ~ but the hardlimit was 1.72v there
> No reason to fear voltage, as long as you adjust "powering" a bit
> 
> Barely to my experience
> There was at least a 4ns difference on Hynix and Rev.E instead of running 16-18 or 18-19 , just running 14-18 ~ considering tRCD wall doesn't move at all, soo voltage goes only towards tertiaries & transition timings
> But honestly on b-die ~ no
> On Rev.E the difference between tCL 14 , tCWL 14 (with lower tRDWR as that gives a lot of bandwidth)
> vs CL13 , tCWL12 , was deminishing. Maaybe 0.5ns at best , but that would also mean generally lower tRC and more voltage
> 
> Flat primaries generally outperform it close to always.
> tCL13 , tCWL 10 for example performed worse than tCL13 tCWL 12
> The addition you had to push on tRDWR ~ was starting to be negative and eat more latency and bandwidth, than tCWL did give at 10
> tCL 12 then needed beyond 1.7+ which was not feesable unless i hold them sub 30c (possible, but then the bios training also plays a role into this).
> To quote buildzoid
> "What is a 12. This bios doesn't understand what CL12 means" 🤭
> 
> Answer is, no
> Match tCL with tRCD and you'll have a good time
> Drop tCL -1 and you will need to adapt tCWL.
> It can give a bit of bandwidth, but bellow tCWL 14 you start to have diminishing returns and bellow tCWL 12 ~ the tRDWR requirement just is not cutting it = negative scaling


Thank you, that is what I could come up with atm, single error 2 after 50ish cycles, nothing else in the 60 cycle test.
I may increase a bit more vdimm to see if i can drop trcdrd to 14 !








I still need to work on trdwr and twrrd, haven't tested yet if I can do lower on that batch


----------



## Veii

XPEHOPE3 said:


> Also I don't understand why do you keep reposting that obsoleted screenshot with old AGESA and 2.5T instead of redoing the experiment. Proper science means replication of results


Because i can't be bothered 10hours on the same 16-16-16 + 14-14-14 screenshot and wipe my windows installation, to justify mistrust from entitled people

Probably it's more 110min+100min+110min 5:30h
Plus
100+90+100min 4:50h
And between all these wait for windows services to settle 4-5min

Then expect that these timings work for the first time and generally redo that on a 32-34c summer day, while there is more than enough on backtrack
I really ! Can't be bothered to fight with people & again have moderators erase (not even bothered to edit) my posts ~ soo the work is gone for nothing, ontop of that when everything shared was out of cost and i don't have anything from all this double work
Mistrust is not a problem of mine  nothing i need to doubleproof or take away the timings guess work for new broken AGESA's
Its been already enough hassle to continuously fix my 15-15 preset, which AMD keeps breaking

Even if you don't mean it that way (i hope)
You forget how much work such a screenshot is, or don't respect it ~ soo don't care and want only finished copyable work (but i hope it's not that)
Sorry i can't be bothered. My time is more worth than arguing about a personal mistrust problem




XPEHOPE3 said:


> Maybe you'll also see bandwidth loss. Or, for example, confirm my experience that setting GDM on 2T might not even POST when GDM off 2T/1T POST Ok, as well as GDM on 1T


GDM has no 1T or 2T
Its on or off. And when it's on , it's 1T+2T+1T 
Confirming bios bugs will be hard when asrock takes a month behind every other board partner, to release bioses
It's good that they dont release untested thinga, but then because of such ever Board partner gets this 2-3 months before release
Their 1.2.0.3B is also a patch A , as B is broken
But nobody cares that it says B even when everybody knows about it (i hope)
Msi wasnt much different, but at least users reported about it
Asrocks communtiy appears to be more passive about things, and is happy when they get bioses
Even when its just 5-8 weeks later than anybody else

I might retest it but it's really a waste of time
Timings on GDM bring nothing
And the bios is too stupid to recognize CL 12
Unless something new comes out or the bios gets unlocked ~ it's just a waste of time
Your request sounds rather more needy and trolling/sarcastic ~ than asking nicely about it
On such behaviour, i couldn't care less to spend a full 10h day for it

EDIT:
As i might remake it with better timings once bioses are in a stable state
Currently we play the waiting game , with an unannounced date 
But right now, it makes no sense to waste time like this, confirming something i know and been talking about for quite some time, since Matisse even
The result stays as result. On which flat timings you test it or how they perform is another topic ~ but i don't think it's "just retestable" without spending your whole day to make timings which work on all 3 states.
It's too much work for such expectation. Mocking or not, there is no way how you can request such amount of work casually from me.


----------



## XPEHOPE3

Sorry, I didn't think that was too much work. In my view, should you have any single set of settings, stable at those 3 configurations, testing performance difference is as hard as booting and running Aida 3 times. In any case there was no need (in my view) to wipe out Windows. If you don't have such a set of settings, I thought obtaining one wasn't that of a problem for 2-dimm SR setup, given your knowledge, *because test in question doesn't seem to require timings being tight. *That is, I thought it's possible to let's say get your "easy to run" 3800-16 set and test difference on it. Do you mean that GDM off 1T/2T/on relative performance would be any different for tighter set?

I also judged from these quotes that once you have a single GDM off 1T stable set with even timings, which you probably have, that set would definitely POST with GDM off 2T and GDM on 1T. And most probably be stable.


Blameless said:


> At settings I can run GDM off, if I'm running 2T command rate and all even timings, turning GDM on is almost within margin of error.





Veii said:


> * _Any primaries that run on 2T will run on 1T without issues, but anything around them which depends on PCB strain ~ will behave different and can easily require more VDIMM_


But then of course if you are not interested in the topic, why bother? I didn't see improvements with GDM on (at all), neither did you (latency-wise). Only @Blameless suggested there could be, w/o any proof (just as me).

On a side note, if you are annoyed by your posts no longer available due to moderation or forum update changing links, then I think you can create topics with any of the findings you deem important to get saved, because topic starting post won't get deleted due to mid-topic moderation, and topics are easily accessed from user profile, and their links are less likely to change than a link to post in a huge thread which move around on each moderation even if your posts are not deleted.


----------



## Blameless

XPEHOPE3 said:


> But then of course if you are not interested in the topic, why bother? I didn't see improvements with GDM on (at all), neither did you (latency-wise). Only @Blameless suggested there could be, w/o any proof (just as me).


I never suggested that GDM on would ever be faster than GDM off at the same clocks and timings. I suggested that if you had stability issues with GDM off, but were using even timings and T2 command rate anyway, you shouldn't lose appreciable performance by enabling GDM, but could gain stability.


----------



## XPEHOPE3

Blameless said:


> I never suggested that GDM on would ever be faster than GDM off at the same clocks and timings.


Yes, my memory strengthened your original post somewhat . Still GDM off benefit was quite appreciable latency-wise for me.


Blameless said:


> I also notice you have GDM disabled...if you're running T2 and all even timings anyway, disabling GDM will provide essentially no benefit, and could still significant harm stability.


----------



## byDenoso

These errors are driving me nuts...


----------



## boldenc

My AIDA64 benchmark looks low compared to results here with same setup.
Any advice to improve it?


----------



## Oversemper

byDenoso said:


> Also try Drop your tRTP to 5 and tWR to 10 and test again.


Worked and tested stable. Big thanks!
*UPDATE*: Was to rush to celebrate. Prime95 gives a rounding error at 5/10, 6/12 and 7/14 tRTP/tWR within 1-3 first passes (20-30 minutes till error) in 100% of runs. At 12/14 tRTP/tWR, as dram calc proposes, Prime95 is rock-solid infinitely (6+ hours). Added a screenshot.



Mach3.2 said:


> by the way you can try tRC = tRAS + tRP too. tRC should be 52.


At 52 did not post, but motherboard recovered itself by adjusting 52 to 55. I guess I can lower the previous tRC value of 58 to 55. I'll test it later.

Further, all this is at default memory voltage of 1.35v. Should it be possible to gain anything by increasing the voltage of my Micron Rev. E? How usually Rev. E responds to a voltage increase? Maybe I can chase CL15 now that GDM is stable at OFF? I'd appreciate greatly some general advice! I'm not gonna increase Infinity Fabric frequency coz I need CPU to run at low voltages (one loop for GPU and CPU) and stability without WHEAs comes first for me.


----------



## Veii

byDenoso said:


> View attachment 2519470
> 
> 
> These errors are driving me nuts...


#13 = overvoltage crash or overheat
#4 = overcurrent PCB crash

I think the answer is clear 
Lower VDIMM
706 was the trick, 607 worked but was worse - give 706 a try and report back
Else you likely have to drop something - mostly it's dropping voltage, as the resolve

Something else to ask,
There is no way for you to drop procODT down to 34 ?
cLDO_VDDP is lower than usual, and Matisse run 28ohm for 3800MT/s 2x8gb kits
While it was hard for people - 30ohm was easier
34 has to run for you easily

Yea something to ask:
Can't you drop VDDG IOD slightly , to allow you staying @ 1.1vSOC ?
* or just fixing SOC loadline to actually stay @ 1.1 and not 1.125v
** 1.05v IOD was needed , sometimes 1075 even ~ to bruteforce FCLK instability @ 1900 or upwards (the days where there was no enforced +1901 FCLK boot lock)

Matisse had negative scaling after 1.15v, while after 1.1v it wasn't such a good time & generally pushed min-procODT up that way
Lower voltages there, have to help you with signal integrity ~ soo lower allowed procODT can run & your RTTs can be "weaker"
It's already weak but something still causes overcurrent crashes, maybe NOM here is wrong
Either way, give 706 a try & if that doesn't work ~ give 736 or 636 a try
#4 has to disappear first

Oh my little sheet states tCKE 8 for 1867Mhz MCLK
Might want to "just try" tCKE 8 instead of 7.
It could also cause such errors to appear


Oversemper said:


> At 52 did not post, but motherboard recovered itself by adjusting 52 to 55. I guess I can lower the previous tRC value of 58 to 55. I'll test it later.


Considering tRC is not allowing itself to be tRP+tRAS , it's masking some latency issue
Be it too low tRAS or something else on the tertiaries
For Rev.E try to use the tCCD_L trick
tRCDmax (_RD*2) + tCCD_L (6-7)
You can try with tRCDavg (((_RD+_WR)/2) + tCCD_L)
or the same for tRCDmin ~ which would be taking tRCD_WR as anchor. Tho that rarely to never really works out

Overall , this is an issue you want to have resolved
Soo increase tRAS, till your tRP+tRAS math = minimum bootable tRC actually works

Later if you want a bit more bonus bandwidth
Drop both tWRWR & tRDRD DD's down to 2
(doing it now will make everything harder to stabilize)


Oversemper said:


> Should it be possible to gain anything by increasing the voltage of my Micron Rev. E? How usually Rev. E responds to a voltage increase? Maybe I can chase CL15 now that GDM is stable at OFF? I'd appreciate greatly some general advice!











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Ahha finally a stable cl14 ( ok at 1.5V VDIMM ): OK, just joking, I just set the primary timings, all secondaries/tertiaries are on auto. the good news is it's stable. The bad is it's all auto and feel very loose, and it's VDIMM 1.5V I also had to set the RTT* to 6 3 3 and the *DrvStr 40 20...




www.overclock.net




Generally neutral.
tCL moves, tRP & tRAS moves
Tertiaries mostly get wiggle room , but Rev.E has a cap on tRCD and tRFC range.
You can wiggle it down +1 MCLK step ~ rather extend it
But barely.

My presets all are on 1.6v+
1.65v was cozy for them
More didn't have any benefit whatsoever

Something else tho.
Your SOC voltage is too tight
You need at absolute minimum 42mV distance between IOD and SOC
This is a GET voltage, soo loadline included 
Either drop IOD slightly or increase SOC slightly.
50mV distance is good to keep up - but the absolute minimum is 42mV
Your SOC voltage is too "tight"


----------



## Veii

XPEHOPE3 said:


> Sorry, I didn't think that was too much work. In my view, should you have any single set of settings, stable at those 3 configurations, testing performance difference is as hard as booting and running Aida 3 times.


Not that easily sadly.
I would need to jump back to windows 10, soo it will indicate if boosting is correct & hold the 10.4ns L3 cache
Timings on 1T would work on GDM, but powering will not
It's likely that i overcurrent / overvoltage PCB crash ~ but i'd need to TM5 it ~ which on 3 presets takes time (well not as much as on 2 flat timing illustrations)

Afterwards likely would need to redo VDDP , VDDG, SOC voltages ~ as there surely will be somebody who moans at me running "far to high voltages for this 1900 FCLK"
Then when i touch cLDO_VDDP, my powering will break, procODT will break and i have to retest it
There is no way for me how it wouldn't take 6 hours with 1 timing set, or bellow 10h for two timing sets ~ to make the same learnable illustration
It's not feasable expecting powering on 1T vs GDM to function identical and not PCB crash ~ when PCB strain is halved on GDM


XPEHOPE3 said:


> hat is, I thought it's possible to let's say get your "easy to run" 3800-16 set and test difference on it


I did, the picture had a half top - 16-16-16 and 14-14-14-14 test
Both where on it, and why i mentioned 10h at first 


XPEHOPE3 said:


> But then of course if you are not interested in the topic, why bother? I didn't see improvements with GDM on (at all), neither did you (latency-wise). Only @Blameless suggested there could be, w/o any proof (just as me).


It's not a no interest, just far to much work required doing it correctly ~ for something replicable (voltages)
Maybe again with a new bios, but right now it's a waste of time ~ when Patch-C likely again will redo many things (extend is unknown yet, but surely will touch on the cache topic)

Bandwidth is slightly bit higher with GDM , vs 2T
But it only makes sense to run it when you push 5000+ MT/s (although actually not really)
Or just run flat 12-12-12 timings ~ there , halved PCB strain surely will help & might just by a tiny bit, exceed 1T 13-13-13 bandwidth & latency
This part i actually want to test.
It bothers me that my B-dies can not run 12-12-12-12 beyond 3633, haven't tried GDM on , if that reaches 3800 finally 
It appears more to be a bios issue, than even the IC limit

Except this potential benefit, i see absolutely non running GDM and focusing your timings on it
They won't be usable with GDM off, unless they where good to begin with. Then only powering would require an adjustment & not VDIMM.
It's double and tripple the work dealing with GDM for nearly no gain ~ when your goal is 1T.
Fully not recommendable by me wasting time researching timings with GDM ~ doing half hearted work only and not putting 1T as the main goal


Veii said:


> Bandwidth is slightly bit higher with GDM , vs 2T


2T should only be a mid-pause stop & not a finalization
It should be used for checking timings accuracy & seeing where your ICs start to cause trouble **
1T then needs far more work and is the main goal.
GDM to 1T is close to impossible. Doing the hard work and actually getting GDM away, is more rewarding for your spend time.
I can not see a reason why doing "not usable" timings on GDM would lead to anything ~ except wanting to be done fast with it
* only potentially a 12-12-12 set, but idk how feasible theory with reality is. I have to play with this idea
** also the ability to prevent rounding and use odd timings, is a big benefit vs GDM


----------



## byDenoso

Veii said:


> #13 = overvoltage crash or overheat
> #4 = overcurrent PCB crash
> 
> I think the answer is clear
> Lower VDIMM
> 706 was the trick, 607 worked but was worse - give 706 a try and report back
> Else you likely have to drop something - mostly it's dropping voltage, as the resolve
> 
> Something else to ask,
> There is no way for you to drop procODT down to 34 ?
> cLDO_VDDP is lower than usual, and Matisse run 28ohm for 3800MT/s 2x8gb kits
> While it was hard for people - 30ohm was easier
> 34 has to run for you easily
> 
> Yea something to ask:
> Can't you drop VDDG IOD slightly , to allow you staying @ 1.1vSOC ?
> * or just fixing SOC loadline to actually stay @ 1.1 and not 1.125v
> ** 1.05v IOD was needed , sometimes 1075 even ~ to bruteforce FCLK instability @ 1900 or upwards (the days where there was no enforced +1901 FCLK boot lock)
> 
> Matisse had negative scaling after 1.15v, while after 1.1v it wasn't such a good time & generally pushed min-procODT up that way
> Lower voltages there, have to help you with signal integrity ~ soo lower allowed procODT can run & your RTTs can be "weaker"
> It's already weak but something still causes overcurrent crashes, maybe NOM here is wrong
> Either way, give 706 a try & if that doesn't work ~ give 736 or 636 a try
> #4 has to disappear first
> 
> Oh my little sheet states tCKE 8 for 1867Mhz MCLK
> Might want to "just try" tCKE 8 instead of 7.
> It could also cause such errors to appear












It was just running fine and then i had a blue screen with "DPC Watchdog Violation"
You think than its better run 15-20-20-20-40-60 instead?


----------



## Kildar

I just updated AIDA64 to the latest version from an older version I have had and my read and write speeds drop from the lower 70's to the upper 50's. Latency has stayed pretty much the same.


----------



## Veii

byDenoso said:


> View attachment 2519553
> 
> 
> It was just running fine and then i had a blue screen with "DPC Watchdog Violation"
> You think than its better run 15-20-20-20-40-60 instead?


Uhm, rather not 
Your timings could be fine
But you can focus later on dropping that tRCD slightly with more voltage
It has a bit wiggle room. Not much ~ honestly barely anything. But a bit exists 
Just get it stable first ~ then you can start to drop tRAS and tRC together till you fully refuse to post or have other issues

244ns tRFC hmmm
C-Die ?


----------



## XPEHOPE3

XPEHOPE3 said:


> I hope to reproduce these settings on non-beta BIOS












Reproduced, but TM5 runtime is somewhat slower.


----------



## Veii

XPEHOPE3 said:


> View attachment 2519565
> 
> 
> Reproduced, but TM5 runtime is somewhat slower.


I really wonder about your cores / or Gigabyte's predefined cheatery (every AIB is to blame not only they)
Why is your L3 not sitting at 10.9ns = 4.65Ghz 

This increase happened once after Patch D / soo i wonder what is wrong.
Likely EDC limit triggers and throttles back the short burst allcore tests of Aida64

EDIT:
You have to sit at 600-610GB/s cache, across all 3 of them
Mostly 550 on the worst, but that not only scales by core frequency, but also FCLK & powerplan core freq suspension behavior (faster idle state = less strain = higher cache boost)
L2 latency is correct. 2.5ns only comes when you are at 4.85Ghz and mostly beyond 1900 FCLK

EDIT 2:
5600X should be fully fine with these limits








TDC maaybe can be lower to prevent voltage throttle, but it should be fine
If you'd like to compare this for me 
L3 won't boost higher than FIT allows, soo no worry there just lifting first Stage EDC limit. It will be captured by EDC FUSE (122A) at the end anyways
VID limit you can not lift so far, and prochot limit also not - any core requesting higher than 1.4v tho will be throttled back
THM limit is worthless i feel like

EDIT 3:
Even Write shows throttle because of something
30932MB/s should be your target out of 30933.3333MB/s peak


----------



## XPEHOPE3

Veii said:


> I really wonder about your cores / or Gigabyte's predefined cheatery (every AIB is to blame not only they)
> Why is your L3 not sitting at 10.9ns = 4.65Ghz


It's not only on Gigabyte, also on ASUS for some. And there are others like that in the list.


Veii said:


> 5600X should be fully fine with these limits
> 
> 
> 
> 
> 
> 
> 
> 
> TDC maaybe can be lower to prevent voltage throttle, but it should be fine
> If you'd like to compare this for me


Yeah, I'm about to start OCing CPU. Don't _really _know where to start honestly, not to mention what to do further  Regarding limits I think I should be able to set them like this: two of them shouldn't be reachable, and third one should actually hard limit my OC. I thought temperature limit would be best since I have front-mounted AIO for 5600X with offset mount and good enough paste.
I've already spent more than 2 months on OCing and just want to move on with life  Wish CPU OC was as simple as setting limits (+scaler, pbo-max, etc), running CTR to get CO estimates, then repeatedly run corecycler + all-core stability tests until CO values converge. Hope it takes two weeks, not two months


----------



## Veii

XPEHOPE3 said:


> Regarding limits I think I should be able to set them like this: two of them shouldn't be reachable, and third one should actually hard limit my OC.


That was what we usually did with Matisse.
PPT is the powersuply or cooler limit
TDC was the boost voltage limit
EDC the allcore and sustained voltage limit

Now EDC throttles on too many places and has to be lifted.
PPT remains to be a powersuply limit soo a lift there is not bad , but the easiest way to work with it / is ignore all limits and set there a "target powerdraw"
EDC has to be gone as interconnect , inside fabric all GMI links depend on this and by default it was designed for 1800 FCLK CPU limit. MemOC SOC cuts deeply into these "for user made" limits

What you can use as current rule,
Cinebench R20 ,TDC has to be held at 98%, EDC usually 100%
But right now we want EDC to be lifted since cache overdrive exists
Soo TDC is the only voltage limiter which has some kind of useful usage


XPEHOPE3 said:


> Don't _really _know where to start honestly, not to mention what to do further


You could use my cheat sheet and grab CTR - to configure it hold 4.85Ghz with own Curve Optimizer values (but disable the OB feature of it)


Spoiler














But at very first, you want to fix that throttle
Get the write bandwidth to always be perfect half of FCLK (it's only FCLK based and has nearly no connection to MCLK timings)
Then get cache boost as stable as possible @ 10.9ns (4.65) or 10.4ns (4.85Ghz)

Later you only need to work on the cores holding the boost freq you set
TM5 has to hold it on all cores, same as CPU-Z
CTR Boost tester = Cine single core, should also allow each of the cores to boost to the same specified frequency
Then the rest is just playing with CO and lowering & lowering these values , soo all cores request less VID, run less voltage and the powerbudget limiter allows higher freq to run @ X specific workload

The biggest challenge is this 122A EDC Fuse limit - when SOC cuts soo deeply into the powerbudget
Soo you'd need to get the cores using as low voltage as possible, to average it out
And now what is more important, is holding temps bellow 65c else it will just loose frequency for no reason.


XPEHOPE3 said:


> I've already spent more than 2 months on OCing and just want to move on with life


Once in there, it will never end 😘


XPEHOPE3 said:


> Wish CPU OC was as simple as setting limits (+scaler, pbo-max, etc), running CTR to get CO estimates, then repeatedly run corecycler + all-core stability tests until CO values converge


I've never run Core Cycler tbh 
It takes too long 
And then even if you error - there is no guide how to do it
Well or you can utilize 1usmus's Project Hydra tool & ignore manual CO finetuning 
Wonder how's @domdtxdissar progress so far
Curious if the alpha is a usable upgrade compared to CTR


----------



## Blameless

I like CoreCycler a lot. Finds errors OCCT and y-cruncher often don't catch. It does take a while though.


----------



## sendap

Veii said:


> Later you only need to work on the cores holding the boost freq you set
> TM5 has to hold it on all cores, same as CPU-Z


I just checked that. I have CO set and PBO +100. All tested over days with Corecycler. So it is stable.
Running TM5 my cores boost to ~4750Mhz. But they should boost to 4950Mhz? All this with standardt limits (142/95/140).
I raised EDC to 300 because I saw the EDC hitting its limit when running TM5. With EDC @300 HWinfo reported EDC 155 when running TM5 but the boost went down by 50Mhz.
Confused...


----------



## XPEHOPE3

Veii said:


> But at very first, you want to fix that throttle
> Get the write bandwidth to always be perfect half of FCLK (it's only FCLK based and has nearly no connection to MCLK timings)
> Then get cache boost as stable as possible @ 10.9ns (4.65) or 10.4ns (4.85Ghz)


I don't know either the throttle reason or how to fix it. In Tool1007 I see both PPT Frequency Limiter and FIT PID Voltage Limiter temporarily drop from 4.65, as well as EDC Current Value hit 90.000. If raising limits won't help, I have no idea what to do.


Veii said:


> Cinebench R20 ,TDC has to be held at 98%


Does it have to be R20 and not R23?


Veii said:


> Once in there, it will never end 😘


"Everything that has a beginning, has an end, Neo" 😎


----------



## byDenoso

Veii said:


> Uhm, rather not
> Your timings could be fine
> But you can focus later on dropping that tRCD slightly with more voltage
> It has a bit wiggle room. Not much ~ honestly barely anything. But a bit exists
> Just get it stable first ~ then you can start to drop tRAS and tRC together till you fully refuse to post or have other issues
> 
> 244ns tRFC hmmm
> C-Die ?


My board has a 1.5v cap
So i cant put more voltage than it.
tRP 17 is a bit NO on my kit and drop tRDCD is a blue screen heaven.
Setup times may help?
Or ir just for 4 dimms?
I get error 15 with tRP17


----------



## domdtxdissar

Veii said:


> [/SPOILER]
> Well or you can utilize 1usmus's Project Hydra tool & ignore manual CO finetuning
> Wonder how's @domdtxdissar progress so far
> Curious if the alpha is a usable upgrade compared to CTR


Well, let me tell you, alpha is alpha 
Right now its only "Gamemode" and "allcore avx1 and avx2" mode that works... 1-16 threads profiles comes later.
And Hydra seems more tweaked towards stability then pure performance right now -> CTR have better performance atm *

Think and hope its okai if i share some screenshots from Hydra 
Here is what i call a bug with the diagnostic, while it seems like the devs think its okai for a 5950x's to pull over 300 watt in the XOC profile. (i don't agree👀)








At the end of the ~6 hour diagnostic for a 5950x you get something like this:
(copied from the log) (5800x takes about 3 hours since half the cores)









Here are the data for the best 5600x ive ever seen btw: (platinum sample)









After you are done with diagnostic you get a table like this where its very easy to adjust CO either by single core or by whole CCD
CO in hydra almost work the same way as normal "AMD PBO CO" --> -30 CO in bios = +180 CO in Hydra
If a core have +120 CO in hydra its the same as -20 CO in bios and if i understood it correctly (not sure) the starting-point/zero-point was around -30 CO in hydra. (so even with negative -10 CO in hydra you get the same boosting as you would do with -3.3 CO in bios)

The CO boost comes ontop of the regular "real frequency" gotten from above --> a better name for "real frequency" would be minimum/base (ST) frequency in my eyes.











All in all, its work in progress and iam still using CTR for everyday tasks 

Over to something else, im pretty sure you already know this, but if you dont:
Earlier you have been talking about the max boost level for 5600x @ 4.65ghz with PBO CO, but there is one way around this:
MSI agesa 1.1.0.0 (a,b or c dont matter) allows for +500mhz PBO limit on a 5600x. (doesn't exist on official site for unify-x cause card is newer then that agesa)
Set CO first -> reboot -> then go in the (other) OC menu and set the wanted PBO limit. (but be warned about USB and memory training problems with earlier bioses as you know)

Lastly ive gotten tired of my 56 setup-time for T1 since i'm running 4 memory sticks, so ive ordered myself some 10layers F4-4000C14D-32GTZR
Just crossing my fingers for a good IO die together with gold CCD's for my "soon-to-be" 5950 v-cache edition so i can hopefully stretch their legs alittle, or can atleast try for CL12 or CL13 @ 1900 

* = this is my current CTR gamemode boosting which i think will take some development-time for hydra to beat


----------



## XPEHOPE3

domdtxdissar said:


> But i think Linx scale more (too much) with clockspeed then with memory settings, so i also did a Monero RandomX Miner run as i think it relay more on pure memory performance.. (instructions how to install the miner can be found here)


BTW pool choice is important as e.g. Nanopool has static share difficulty of 480000 while e.g. MineXMR pool has autoadjusting difficulty unless specified explicitly.


----------



## spajdr

Best I got was 55.4ns while having TM5 stable for 3hrs 1usmus_v3.
Anything I could set better without worrying much about possible stability issue with TM5?


----------



## Sleepycat

spajdr said:


> Best I got was 55.4ns while having TM5 stable for 3hrs 1usmus_v3.
> Anything I could set better without worrying much about possible stability issue with TM5?
> View attachment 2519624


Something doesn't seem right. Your memory results are very low for 3933 MHz. And your L3 cache results are also very low, about 10-15% of others.


----------



## pewpewlazer

Sleepycat said:


> Something doesn't seem right. Your memory results are very low for 3933 MHz. And your L3 cache results are also very low, about 10-15% of others.


L3 cache results look normal if he's running Windows 11... can't comment on the memory results.


----------



## Blameless

XPEHOPE3 said:


> BTW pool choice is important as e.g. Nanopool has static share difficulty of 480000 while e.g. MineXMR pool has autoadjusting difficulty unless specified explicitly.


Any recentish version of XMRig should have a benchmark script included, if you want to try that.



spajdr said:


> Anything I could set better without worrying much about possible stability issue with TM5?


Probably several things, but I'd start by making tRC = tRAS + tRP and knocking tFAW down to 24.

Looks like four single sided sticks of Micron E-die?



Sleepycat said:


> Something doesn't seem right. Your memory results are very low for 3933 MHz. And your L3 cache results are also very low, about 10-15% of others.


As noted by pewpewlazer the L3 cache figure looks like Windows 11. Write bandwidth is where it should be, but I bet the loose tRC and very loose tFAW are what's killing read/copy.


----------



## Netarangi

Hi all,

can someone let me know what timings I can improve (Loosen or tighten) on the below pic?










I have an Auros Elite Wifi, Ryzen 5600x and it's Team T-Force XTREEM ARGB 16GB (2x 8GB) 3600 ram.

I've seen mixed reviews that it could be B-Die, but it seems very fragile with any settings higher than 3200mhz at cl14. Could be Hynix.

I can't get it to post with any lower TRCDWR or TRCDRD.

Really appreciate any help! I'm still a newbie but learning


----------



## XPEHOPE3

Blameless said:


> Any recentish version of XMRig should have a benchmark script included, if you want to try that.


I know, but xmrig didn't show any improvements in time after some timings change while e.g. Geekbench 3 or Aida did.

@Sleepycat 
Care to share your current 4*16GB RAM OC results and compare with mine above? 😇


----------



## spajdr

Blameless said:


> Any recentish version of XMRig should have a benchmark script included, if you want to try that.
> 
> Probably several things, but I'd start by making tRC = tRAS + tRP and knocking tFAW down to 24.
> 
> Looks like four single sided sticks of Micron E-die?
> 
> As noted by pewpewlazer the L3 cache figure looks like Windows 11. Write bandwidth is where it should be, but I bet the loose tRC and very loose tFAW are what's killing read/copy.


Indeed I'm running on 4x SS sticks
tRAS + TRP = tRC is a no go, it does not boot.
I will try tRC 56 which seems to boot for now.
And will try tFAW 24, thanks 
And yes I'm running Windows 11 so L3 results are "normal".

EDIT.: tRC 56 is 100+ errors in few seconds, trying tRC 58 now.
Maybe I need different voltages/resistances to be set somewhere? I don't know.

EDIT.: single error #12 in 25mins, what should be changed now?


----------



## Blameless

spajdr said:


> tRAS + TRP = tRC is a no go, it does not boot.


This usually means your tRAS should be increased; might help with stability and shouldn't hurt as you still have room in tRC for it.

Could try loosening tRAS to 42.



spajdr said:


> EDIT.: tRC 56 is 100+ errors in few seconds, trying tRC 58 now.
> Maybe I need different voltages/resistances to be set somewhere? I don't know.
> 
> EDIT.: single error #12 in 25mins, what should be changed now?
> 
> View attachment 2519673


Your tWR is too tight for your tRTP. Normally it's expected that it will be double tRTP. Sometimes it's beneficial to set it lower, but I usually don't bother setting it less than 1.5x tRTP. That said, your tRTP can probably be tightened a little.

Quad SR sometimes benefits from disabling RttWr; something like 7/--/2 for the Rtts might work. Drive strength could also be too agressive where you have them. Might want to see if 40/24/24/24, 40/30/30/30, 60/30/30/30, or even straight 30s helps. You might need to loosen tRP, 16 is fairly tight for micron at these speeds.

After that you have it stable see if tRDRDSLC and tWRWRSCL can work at 4 and tWCL at 14-15.


----------



## gled_fr

Alright, so it seems like this RAM likes 1.51V VDIMM, subtimings now the same as cl15 !









so cl15 54.8ns cl14 54.6ns => .2ns going 1.45 to 1.51 vdimm.

I wonder if I can go tighter than that on subtimings.

I also tried to get lower TRCDRD to 14 to have flat primaries, but even at 1.52v, or 1.515 with rtt 633 or 734, error 0 at the beginning, then 6 or 2... which is confusing, overvoltage crash then undervolt issues ? That one is gonna get difficult...

I also tried to lower vsoc, cldo_vddp, ccd and iod, and I got some black screen after running tm5 for a bit. I may have lowered them too much, need to work on that too...


----------



## MrHoof

Got a pretty fun ram/cpu/motherboard combo. Its more easy to get this stable @3800mhz then getting it to error unless I go for tCL 14. I feel like I dont learn much tho cause everything just works all the time. Currently running 1.51v VDIMM and this has been running a month since stress testing with tm5 without hiccups.

So here my question, is there a chance I get to tCL 14 with working on RTTs? Its the only thing thats always on AUTO cause I just dont understand those at all. 
XMP of this kit is 3600 17-18-18


----------



## byDenoso

MrHoof said:


> Got a pretty fun ram/cpu/motherboard combo. Its more easy to get this stable @3800mhz then getting it to error unless I go for tCL 14. I feel like I dont learn much tho cause everything just works all the time. Currently running 1.51v VDIMM and this has been running a month since stress testing with tm5 without hiccups.
> 
> So here my question, is there a chance I get to tCL 14 with working on RTTs? Its the only thing thats always on AUTO cause I just dont understand those at all.
> XMP of this kit is 3600 17-18-18
> 
> View attachment 2519693


I Think than this RTT is a little bit harsh on 1.51v, try 7/0/6


----------



## Netarangi

Anyone used Project Hydra yet? It’s reading -20% to 15% vdroop for me and errors as soon as it starts the prime95 tests


----------



## gled_fr

MrHoof said:


> Got a pretty fun ram/cpu/motherboard combo. Its more easy to get this stable @3800mhz then getting it to error unless I go for tCL 14. I feel like I dont learn much tho cause everything just works all the time. Currently running 1.51v VDIMM and this has been running a month since stress testing with tm5 without hiccups.
> 
> So here my question, is there a chance I get to tCL 14 with working on RTTs? Its the only thing thats always on AUTO cause I just dont understand those at all.
> XMP of this kit is 3600 17-18-18


You can see my post just before yours, to go from CL15 to CL14 I had to up the vdimm from 1.45 to 1.51, pretty much everything else was the same, but it took a long time to figure out how to stabilize it and find the vdimm allowing me to run. If you already are at 1.51, my guess is higher voltage will be needed, or relaxing some subtimings. Not sure you will gain what you expect ( .2ns in my experience so far ).

Not an expert, but I think you definitely should need to work on the RTT / ProcODT and probably some *Str too.

Your VSOC and IOD are also very close to each other, you should make sure they keep 50mV appart at all time.


----------



## PJVol

MrHoof said:


> Got a pretty fun ram/cpu/motherboard combo


Can you post thaiphoon screen of your RAM, or SPD info at least? Just out of curiousity, as it looks very similar to mine.
If it by any chance is 17-18-18-38 / 62-631-469-289-15-8-42 / 1.35V, then (according to @Veii), such high Vdimm just masking incorrect timings.
And btw, what did you find funny about that combo?


----------



## Taraquin

spajdr said:


> Indeed I'm running on 4x SS sticks
> tRAS + TRP = tRC is a no go, it does not boot.
> I will try tRC 56 which seems to boot for now.
> And will try tFAW 24, thanks
> And yes I'm running Windows 11 so L3 results are "normal".
> 
> EDIT.: tRC 56 is 100+ errors in few seconds, trying tRC 58 now.
> Maybe I need different voltages/resistances to be set somewhere? I don't know.
> 
> EDIT.: single error #12 in 25mins, what should be changed now?
> 
> View attachment 2519673


I have a rev E set. You can run most timings except for tRCDRD, tRC and tRFC tight.

Try tRRDS 4, tRRDL 6, tFAW 16, up to 5, 7, 20 if it doesnt work. Try tWR 12, tRTP 6, tRC might need a bit more like 59-60, tRFC might run a bit lower, maybe 560-580, twtrs 4, twtrl 12, tRP might run fine at 12.


----------



## mongoled

Looks like I destroyed one stick of my godly set by removing the heatspreaders.



After removing the heatspreaders (using heatgun) the dead stick was OK as I was testing them on each stage of progression.

Whatever happened happened when I was cleaning the sticky gunk off the module.

I can see I broke off two tiny ICs, though measuring using a multimeter it seems they are not even ICs but tiny "bridges".

I managed to fix the bridges by soldering a fine piece of wire but the stick remains dead.


----------



## Yviena

OK i just did a 30 cycle TM5 with no errors but windows still frequently loses all usb power, and freezes during loading of windows.


----------



## spajdr

Yviena said:


> OK i just did a 30 cycle TM5 with no errors but windows still frequently loses all usb power, and freezes during loading of windows.


And when having opened HWINFO64 during TM5 run, no WHEA errors are reported?


----------



## Blameless

mongoled said:


> I can see I broke off two tiny ICs, though measuring using a multimeter it seems they are not even ICs but tiny "bridges".
> 
> I managed to fix the bridges by soldering a fine piece of wire but the stick remains dead.
> 
> 
> 
> View attachment 2519747


Those should be decoupling resistors. Couldn't measure any resistance through them?



Yviena said:


> OK i just did a 30 cycle TM5 with no errors but windows still frequently loses all usb power, and freezes during loading of windows.


Chances are that FCLK is too high, or SoC voltage incorrect. It's also possible that your PSU has really bad cross load characteristics on the +5v rail, which generally powers memory, chipset, and USB ports.


----------



## Yviena

spajdr said:


> And when having opened HWINFO64 during TM5 run, no WHEA errors are reported?


Nope no WHEA


----------



## mongoled

Blameless said:


> Those should be decoupling resistors. Couldn't measure any resistance through them?


They are tiny. 

I'm unsure if they are decoupling resistors. When i short the ends of a working decoupling resistor while it is soldered on the PCB my digital multimeter beeps signifying its 'open' i.e. Its shorted. 

That's not what I expected. There are other decoupling resistors on the PCB, when I shorted those they were "closed" i.e. no beep

That's why I decided to use a fine wire to short the two points where the decoupling resistor was. 

I did try with slightly larger decoupling resistors I pulled from a notebook motherboard but it didn't work. 

The "working area' is tiny, I'm going to have to scratch the trace to give me a larger surface area to solder to and then measure to see if it is "open" as I may not have made a good connection with my previous attempt.


----------



## MrHoof

PJVol said:


> Can you post thaiphoon screen of your RAM, or SPD info at least? Just out of curiousity, as it looks very similar to mine.
> If it by any chance is 17-18-18-38 / 62-631-469-289-15-8-42 / 1.35V, then (according to @Veii), such high Vdimm just masking incorrect timings.
> And btw, what did you find funny about that combo?


Well fun compared to my old cpu/mobo 3600/x570 aorus elite, with the same kit I never got it stable at 1T if it did boot it would error instantly. At the end I was stuck at 3800C16-16-16 1.42V cause I couldnt make CL15 stable aswell in 2T.

Same ram with new cpu/motherboard has 0 problems to run 1T and CL-15 was rather easy to archiev 1.48v to boot it and 1.51 to get it stable dunno why this would mask errors tho. It feels like I can just punch in whatever subtimings I want and it never errors.
















@byDenoso Tested if RTT 7/0/6 would boot and seems to be working fine so far, what advantage does this give over 0/0/5 ?

@gled_fr I thought lower *Str is better or is my understanding wrong here? 1T works flawless @20 ClkDrvStr.


----------



## Veii

Yviena said:


> OK i just did a 30 cycle TM5 with no errors but windows still frequently loses all usb power, and freezes during loading of windows.


TM5 "only" tests the memory
It can technically fail on FCLK instability , but that is rare

You always should verify y-cruncher 4 loops all tests (1-7-0 Key combination)
And OCCT Extreme AVX2 (for 1h = demo)

There are 3 things to remember:

MCLK can be tested individually for figuring out procODT, cLDO_VDDP, RTTs + CAD_BUS & VDIMM
FCLK will need to be tested individually if it can reach perfect half write bandwidth (1 CCD), in y-cruncher & OCCT. (1.8v Rail needs tuning, procODT, VDDG, SOC)
Going later 1:1 mode putting both puzzle pieces together will need once again a loop of TM5+Y-cruncher+OCCT ~ as VDIMM for memory will change and so procODT will change
These issues you describe, are either VDDG related or Chipset related (I/O functionality belongs to the PCH)
(if y-cruncher & OCCT pass with X running voltage ~ miss a screenshot of Aida64 & ZenTimings on your post)
Can also not exclude that you aren't EDC or FCLK throttling that way, without data ~ soo no idea sorry. It needs stability confirmations.
TM5 is just here to test Allcore SSE stability and timings stability ~ has barely any CPU influence at all.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
My work atm:
~ still miss 1MB/s and have slight throttle








====================================================
Also big warning for SMU 56.53 & likely older
If you run your 1.8v rail at 2030mV , your SOC near the 1.3v Range & push VDDG IOD upwards to 1.2+
It will bug out and push maximum allowed VDDG IOD of 1287.5mV ~ instead of the set 1.2v. *⚠*
Be aware ~ with bad luck, this can fry your IMC.
It is benchable at this voltage, but Y-cruncher will insta crash and TM5 will cause a random reboot. (security reboot)

1.18 is taken , but don't see any of the mentioned voltages as replicable
I want it rock-stable, then you guys will get more info

Oh tWTR_S to 6 (beyond 5) is not soo bad, but slows down latency by 0.4-0.5ns and eats 200MB/s Read & Copy
(helps stabilize primaries +1 MCLK step ~ soo the tradeoff is considerable)
While tWTR_S at 3 or 2 is giving a big bandwidth boost, but far to hard to stabilize at high MCLK
tWRWR, tRDRD DD's lowest possible remains beneficial.
Unsure about many-dimm setups (2 per lane)

EDIT:
Another info,
I've reworked the tCKE to MCLK range a bit on the same Docs Sheet
It is now usable on a wider range ~ but still misses alternative options to select from 

EDIT2:
I have to rephrase slightly,


> Anything AT & BEYOND 1.2v VDDG IOD is broken and bugs out


FIT catches it, but be aware really
1199mV works tho 🤦‍♂️
Unsure if it switches to LN2 more or what's exactly up. But it certainly is bugged ~ rather dangerously bugged


----------



## BloodDivine

@Veii 

Don't you also need PCI-E load to test FCLK? I had sessions where it passed Y-Cruncher and OCCT without WHEA but it would throw WHEA while I was gaming


----------



## Veii

BloodDivine said:


> @Veii
> 
> Don't you also need PCI-E load to test FCLK? I had sessions where it passed Y-Cruncher and OCCT without WHEA but it would throw WHEA while I was gaming


DPM & DPM LCLK links are always active as long as your gpu runs "prefer maximum performance"

Fabric instability will be shown well withy-cruncher or OCCT
PCIe 4.0 can drop out after 2000 FCLK
AMD knew this for Matisse and Renoir (mobile)

It's kind of the opposite
GPU load and 4.0 links will rarely change their frequency
Its the FCLK to adapt for this, even when the links are send from the IO-Die

Its part of WHEA #19, but that is I/O Related
Soo all just a settings thing till stress tests pass
The later part of the issue has barely anything to do with FCLK
I mean technically USB & SATA dropouts are a side product of PCH link speed consistency

But such is a long story
You can not work with it, barely to non ~ is what i try to say (AMD CBS, SMU, DPM)
Don't worry about it, as it will manifest as an "unbootable" FCLK state
Absolutely not an "unstable" state

GPU driver crashes are connected to an unstable OC
So are framedrops and spikes
(I have big one on 2133 till i get throttling under control)
But the GPU and the PCIe link are not the issue
Either it runs or it doesn't


----------



## tcclaviger

Seems accurate.
3800*16 = 60,800
59170/60800 = .97319 (or 97.319% throughput efficiency).

The 7xxxx results are physically impossible, was never correct.


----------



## byDenoso

MrHoof said:


> Tested if RTT 7/0/6 would boot and seems to be working fine so far, what advantage does this give over 0/0/5 ?


Well, a strong RTT means more heat, and it would make the PCB's Crash.
7/0/6 is a better choice for +1,47v










My new stable settings, with tRC56 and lower tRAS (just uploading it here because i'll update my bios now).


----------



## gled_fr

Veii said:


> EDIT:
> Also OCCT Extreme is great for CO balancing now
> If one core fails, you should not change this single Core CO (values are like the bios Core 0-15) / this is if you follow my CO cheat sheet
> But you should change anything around this core (+1 or less - value)
> Then when it stabilizes -2 on everything for 25mhz more boost. Then if one fails again adjust anything +1 till it's stable.
> Cores will fail after 10-15min pretty consistently.
> Cores do not fail on their own. dLDO is there. Balancing is the key for manual CO tuning. Core failure is possible if the distance is an issue & not the CO value on it's own
> Yet manual CO tuning changes the magnitude and never overrides AMDs predefined binning (FIT's defined)


Do you have a link to your CO cheat sheet ?

Would like to try to see if this method improves my current PBO2 CO


----------



## PJVol

MrHoof said:


> dunno why this would mask errors tho.


Yours, according to SPD are bit different, reported as A1 (don't know, what that revision means, tbh), better RC, though RFC and RCD are the same, a bit worse tFAW.
Anyway you may try to copy/paste my 24/7 timings (1.44V Vdimm) to run and compare the results. If they don't get worse, then this will mean overtightened timings.

PS: It seems reasonable to update AIDA to 6.33.5700 at least.


----------



## Yviena

Veii said:


> TM5 "only" tests the memory
> It can technically fail on FCLK instability , but that is rare
> 
> You always should verify y-cruncher 4 loops all tests (1-7-0 Key combination)
> And OCCT Extreme AVX2 (for 1h = demo)
> 
> There are 3 things to remember:
> 
> MCLK can be tested individually for figuring out procODT, cLDO_VDDP, RTTs + CAD_BUS & VDIMM
> FCLK will need to be tested individually if it can reach perfect half write bandwidth (1 CCD), in y-cruncher & OCCT. (1.8v Rail needs tuning, procODT, VDDG, SOC)
> Going later 1:1 mode putting both puzzle pieces together will need once again a loop of TM5+Y-cruncher+OCCT ~ as VDIMM for memory will change and so procODT will change
> These issues you describe, are either VDDG related or Chipset related (I/O functionality belongs to the PCH)
> (if y-cruncher & OCCT pass with X running voltage ~ miss a screenshot of Aida64 & ZenTimings on your post)
> Can also not exclude that you aren't EDC or FCLK throttling that way, without data ~ soo no idea sorry. It needs stability confirmations.
> TM5 is just here to test Allcore SSE stability and timings stability ~ has barely any CPU influence at all.
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> My work atm:
> ~ still miss 1MB/s and have slight throttle
> View attachment 2519776
> 
> ====================================================
> Also big warning for SMU 56.53 & likely older
> If you run your 1.8v rail at 2030mV , your SOC near the 1.3v Range & push VDDG IOD upwards to 1.2+
> It will bug out and push maximum allowed VDDG IOD of 1287.5mV ~ instead of the set 1.2v. *⚠*
> Be aware ~ with bad luck, this can fry your IMC.
> It is benchable at this voltage, but Y-cruncher will insta crash and TM5 will cause a random reboot. (security reboot)
> 
> 1.18 is taken , but don't see any of the mentioned voltages as replicable
> I want it rock-stable, then you guys will get more info
> 
> Oh tWTR_S to 6 (beyond 5) is not soo bad, but slows down latency by 0.4-0.5ns and eats 200MB/s Read & Copy
> (helps stabilize primaries +1 MCLK step ~ soo the tradeoff is considerable)
> While tWTR_S at 3 or 2 is giving a big bandwidth boost, but far to hard to stabilize at high MCLK
> tWRWR, tRDRD DD's lowest possible remains beneficial.
> Unsure about many-dimm setups (2 per lane)
> 
> EDIT:
> Another info,
> I've reworked the tCKE to MCLK range a bit on the same Docs Sheet
> It is now usable on a wider range ~ but still misses alternative options to select from
> 
> EDIT2:
> I have to rephrase slightly,
> FIT catches it, but be aware really
> 1199mV works tho 🤦‍♂️
> Unsure if it switches to LN2 more or what's exactly up. But it certainly is bugged ~ rather dangerously bugged


Hmm i did not have this issue at all before i started messing with Curve optimizer could it be that even if corecycler was running for 2-3 days without errors that windows boot triggers even higher boost clocks thus erroring out?

tho it did happen again when i disabled curve optimizer but maybe the changes did not take affect on the first reboot.


----------



## mongoled

I tried again but still failed.

I removed from a set of GSkills (again killed by removing heatspreader) a dual decoupling resistor and used just the one side to replace the single decoupling resistors.

Multimeter registers that they are soldered on OK, but still C5 error on post.

Think I am going to stick the RAM module in an oven and hope for the best









The watercooling stuff I ordered arrived today, what a shame im never going to able to find out if these would have made a difference to the RAM overclocking capability of the "godly" set...



For anyone interested here is the area thats left uncovered when using the Alphacool D-RAM heatsink on Viper A2 PCBs, its about 2 mm


----------



## Nighthog

mongoled said:


> I tried again but still failed.
> 
> I removed from a set of GSkills (again killed by removing heatspreader) a dual decoupling resistor and used just the one side to replace the single decoupling resistors.
> 
> Multimeter registers that they are soldered on OK, but still C5 error on post.
> 
> Think I am going to stick the RAM module in an oven and hope for the best
> 
> View attachment 2519851
> 
> 
> The watercooling stuff I ordered arrived today, what a shame im never going to able to find out if these would have made a difference to the RAM overclocking capability of the "godly" set...
> 
> 
> 
> For anyone interested here is the area thats left uncovered when using the Alphacool D-RAM heatsink on Viper A2 PCBs, its about 2 mm
> 
> View attachment 2519852


Sad to see the mishap and trying to fixing not working out.

I can confirm the 2mm gap for A2 PCB on my Micron Rev.E kits.
There should be a similar gap with A3 16Gbit sticks as well.

The heat sinks should be updated for the newer memory kits.
They are designed for B0, dual-sided memory kits with the thermal pads that come in the kit.

I would recommend a thermal-pad replacement, 7-8 or 11watt ones rather than the included ones which are probably the worst kind you can get (2-3W?). (huge temperature difference improvement with the 6+ watt pads if you read some reviews for GPU memory thermal-pad replacements. 20C to 40C extra cooling capability)


----------



## Nighthog

I finally managed to get a 20cycle stability for running 4x8GB with the Ballistix MAX kits.

What a struggle to find what the issue was being.

Ended being CLDO_VDDP... 1100mv was unstable and produced a Error every 30-60minutes...
Needed 1110mv to pass TM5 1usmus 20cycle. I was trying lots of things but was in the end only CLDO_VDDP complaining.

Can for once in the past 1-2weeks move on and try to improve this instead rather than trying to find stability.

Daisy-chain motherboards are really troublesome with 4x dimms when you want maximum frequency.


----------



## mongoled

Nighthog said:


> Sad to see the mishap and trying to fixing not working out.
> 
> I can confirm the 2mm gap for A2 PCB on my Micron Rev.E kits.
> There should be a similar gap with A3 16Gbit sticks as well.
> 
> The heat sinks should be updated for the newer memory kits.
> They are designed for B0, dual-sided memory kits with the thermal pads that come in the kit.
> 
> I would recommend a thermal-pad replacement, 7-8 or 11watt ones rather than the included ones which are probably the worst kind you can get (2-3W?). (huge temperature difference improvement with the 6+ watt pads if you read some reviews for GPU memory thermal-pad replacements. 20C to 40C extra cooling capability)


Good info!

I also bought two Gelid GP-Ultimate 90 x 50 x 1 mm thermal packs pads for this purpose they are advertised as 15 W/mK.

I used this on the side of the RAM modules and the enclosed thermal pad on the back.

When running with no active cooling they get nice and hot

 

TM5 of a mixed match set that can do tRCDRD @14 @ 3800 mhz using the Aquacool heatsinks and 2 x 40 mm fan ...


----------



## Wacholek

Hi everyone,

I have unusual problem with my new setup.

Ryzen 9 5950x

ASUS ROG CROSSHAIR VIII IMPACT X570

2x Patriot 16GB (2x8GB) 4400MHz CL19 Viper Steel



At first I had Asus X570-E with 3900x. On that setup max IF was 1866Mhz but was working at 1800Mhz with memory set to 3600Mhz CL14 T1 and turned off all other sleep futures like Geardown. . I had to change some impedance setting to get it stable but it was 100% stable. My 3900x was not booting at 1900Mhz.



Than I bought ASUS ROG CROSSHAIR VIII IMPACT X570 and 5950x.

My 5950x was running flawlessly on the same 1800Mhz settings as 3900x. Did not boot a 1900Mhz but boot at 2000Mhz. Soc voltage was on auto so at 2000Mhz was 1.18V.

2000Mhz was running no problem on both motherboards. Memory 4000Mhz CL16 T2 without any addition afford. All on auto. Turned off all other sleep futures like Geardown.

My 3900x boot at 1900Mhz and working stable on CROSSHAIR VIII IMPACT when it was not booting on X570-E. Both memory sets behave the same. The same timings, OC potential.



I was happy. 5950x was running on CROSSHAIR VIII IMPACT for 2 weeks 24/7 on that settings mining monero. Super stable without any problems and reboots. 0 windows hardware error.

Cpu was cool by water but the whole setup was not ready than. Just a test for 2 weeks.

After that the CPU was removed from the Motherboard and put to the box. Motherboard was left alone in the Streacom DA2 case because I was waiting for a GPU and to build a custom loop for all.

About a month and a half later I assembled everything again.

And now the funny part. 

At first startup I noticed that motherboard detected a CPU change. I through, CPU was removed so maybe that's why. After setting everything like it was before at next reboot I noticed that bios was lagging. When switching the bios cards (left, right key) wideo was hawing a very frame rate like and lagging all the time. Windows boot was super long and all the programs was really sluggish. After a while HW info detected a Windows Hardware errors/. Memory test did not put any errors after a 10min of test however more and more HW errors where in HW info and super laggy system. No reboots tough.
After a bunch of testing I narrowed the problem to the IF frequency. At 1800Mhz was no problem.

So after a month of laying in the box my 5950x broke down and not working on 2000Mhz anymore. I cannot test it on the different motherboard because I sold 3900x with the old motherboard.

I also disassembled the whole setup including motherboard vrm and SB radiator. Cleaned everything. CPU had no bends and no dirt. Cleaned anyway. No change. Second set of memory. No change.

Anyone had similar problem? Any ideas.


----------



## domdtxdissar

Nighthog said:


> Ended being CLDO_VDDP... 1100mv was unstable and produced a Error every 30-60minutes...
> Needed 1110mv to pass TM5 1usmus 20cycle. I was trying lots of things but was in the end only CLDO_VDDP complaining.


CLDO_VDDP @ 1110mv ??
The recommended value is from 900mv to 950mv


----------



## Nighthog

domdtxdissar said:


> CLDO_VDDP @ 1110mv ??
> The recommended value is from 900mv to 950mv


If you want to run ~3800 and less.

More frequency requires more. Seems to scale with MCLK/UCLK frequency range.
1:2 Mode with for for example 5000Mts (1250UCLK) requires less rather than 1:1 4266Mts (2133UCLK)


----------



## byDenoso

Nighthog said:


> I finally managed to get a 20cycle stability for running 4x8GB with the Ballistix MAX kits.
> 
> What a struggle to find what the issue was being.
> 
> Ended being CLDO_VDDP... 1100mv was unstable and produced a Error every 30-60minutes...
> Needed 1110mv to pass TM5 1usmus 20cycle. I was trying lots of things but was in the end only CLDO_VDDP complaining.
> 
> Can for once in the past 1-2weeks move on and try to improve this instead rather than trying to find stability.
> 
> Daisy-chain motherboards are really troublesome with 4x dimms when you want maximum frequency.


Why you run cldo_VDDP so high?
And that this voltage REALLY do?


----------



## Veii

Wacholek said:


> So after a month of laying in the box my 5950x broke down and not working on 2000Mhz anymore. I cannot test it on the different motherboard because I sold 3900x with the old motherboard.
> 
> I also disassembled the whole setup including motherboard vrm and SB radiator. Cleaned everything. CPU had no bends and no dirt. Cleaned anyway. No change. Second set of memory. No change.
> 
> Anyone had similar problem? Any ideas.


This has to be a forced PSP-FW update
It happens on every new boot or board swap
If the CPU FW is older, and the AGESA requires it, it will make one

The problem on that is,
You rarely to never can revert back, till you bug it out with unstable memOC

Can you give a bit more infornation on the setup
Which bios version, soo which SMU

I have a bit of a problem with this
FCLK locks sit in the ABL ~ AGESA Bootloader & not PSP
Unless you used anything 1.1.0.0 Patch C related, you shouldnt have had any lockdown issues

There is one thing tho,
LCLK the toggle in AMD overclocking, has to be enabled
Disabling it does bug out some security features, wipes part of the thermal limit, and wipes the PPT throttle limit

In such case also introduces 1 whole ns more latency. Only good if used with CTR else better enabled
What you can do about it, i honestly think not much

Downgrading to anything that has SMU 50.26/56.30 or upgrading to 56.50
I would likely downgrade, then let it sit again for such a long time till it discharges fully
Then let it force update PSP-FW, the same way you documented
But such is unrealistic tbh ~ waiting 1 month

Unless you where explicitly on SMU 56.34 which does have a 1900 lock
There might be again some lockdown attempts happening on newer SMU
Depends, please share a bit more information 
Sadly PSP-FW updates are nearly always "one-way"


----------



## PJVol

@mongoled
I asked my older brother, who's in electronics mostly, about those broken elements on photo, and he told me they are capacitors.


----------



## MrHoof

PJVol said:


> Yours, according to SPD are bit different, reported as A1 (don't know, what that revision means, tbh), better RC, though RFC and RCD are the same, a bit worse tFAW.
> Anyway you may try to copy/paste my 24/7 timings (1.44V Vdimm) to run and compare the results. If they don't get worse, then this will mean overtightened timings.
> 
> PS: It seems reasonable to update AIDA to 6.33.5700 at least.


That wont work, like I said this kit needs 1.48v at flat c15 to boot into bluescreen. Also I dont worry to much about the ram, if it dies I replace it, dont even have a fan on them but they are not temp sensetive to my luck.

But after all tRP 13 wasnt stable, I did 6 cycle anta extreme in the past but redone the test yesterday with 10 cycles and got a error12 5 minutes into cycle 10. Did some minor adjustments and redone a 12 cylce test today.










edit: dont know if RTT 7/0/6 has done anything, cant see any diffrence in temps or performance over 0/0/5.


----------



## PJVol

MrHoof said:


> That wont work


"won't work" is not exactly "don't work", whatever, its your business.


----------



## MrHoof

PJVol said:


> "won't work" is not exactly "don't work", whatever, its your business.


I mean It will not even train at 1.44v, I tried already in the past with various procODT / DrvStr settings and couldnt get it to work. Maybe at the weekend I give it another shot but not in the mood to reset bios right now, my case is really small, pins hard to reach and I dont have a reset bios switch.


----------



## Veii

MrHoof said:


> But after all tRP 13 wasnt stable, I did 6 cycle anta extreme in the past but redone the test yesterday with 10 cycles and got a error12 5 minutes into cycle 10. Did some minor adjustments and redone a 12 cylce test today.


1.42-1.46v is required for a flat CL15-15-15 set
A flat 14-14-14 set requires near 1.48-1.56v
All depends on RTT and procODT

Going with lowest 2ndaries and sacrificing flat timings stability, is the wrong way to pick
if your 2ndaries and tertiaries really are fine - you will be able to run 15-15-15-21-36, tRTP 6, tWR 12








On your 1.5v+

Oor 15-15-15-15-23-38, tRTP 8, tWR 16
266-198-122 (140ns)
This should run sub 1.48v

The same would be for 14-14-14-28-42 or 14-14-14-14-22-36 (tRTP 8, tWR 16)

"Errors" on Anta's config are not deciphered, nobody knows what they mean
On 1usmus_v3 they are
tRFC Calculator (mini) TM5 error description


https://www.overclock.net/attachments/tm5-zip.341254/



You run high cLDO_VDDP with low procODT
28.8 likes between 850-900mV
30 around 860-940mV
32 from 900mV onwards

Either you stay at 900mV or you increase procODT / but you'll figure this out soon or later
Your distance between IOD and SOC is 39.8mV
Considering this was on idle and not mid load,you likely droop below 42mV
42mV is the absolute lowest required for stabiliy, 39 and lower will already randomly crash.
Fix your loadline or increase SOC slightly

EDIT:
I can see 1T, but it seems to me that you mask lack of procODT and lack of ClkDrvStr,simply by more VDIMM
I think you can do better than that
Flat timings generally are faster than odd ones you currently run


----------



## MrHoof

IOD and SOC is like that even on XMP, those are on auto and it never crashed random so far running since november last year weird.
I choose 950mV VDDP cause it gave me more stable benchmarks compared to 900mv in read/copy, and if I increase procODT on the current set i get unstable latency results. Aida is probably not the best tool to test thoose i guess .

But giving those suggestions a try at the weekend.

edit: And error in test 12 I fixed by looking at a old comment from you that said error 12 is probably something ending to short or recharge was not done in time. That was I guess for the 1usmus config but I think it was still trp to short wich caused to not recharge in time, i just increased trp by 1 and lowered tras by 1.


----------



## Veii

MrHoof said:


> edit: And error in test 12 I fixed by looking at a old comment from you that said error 12 is probably something ending to short or recharge was not done in time. That was I guess for the 1usmus config but I think it was still trp to short wich caused to not recharge in time, i just increased trp by 1 and lowered tras by 1.


mmm,
Anta's test order is slightly different. Sadly we can not translate them over
But on the other hand, both tests take equally long and are equally great
Generally you need to run it beyond 45min, in order to reach thermal equilibrium

Oh you waste also a bit of latency on the SD, DD's
1-5-5-1-7-7 would be the requirement
1-4-4-1-6-6 on 2x8gb, leaves some playroom on the table (higher values here are better, later you can drop DD's to 2 for more bandwidth at the very end)
Just quite honestly, focus on flat primaries and then drop to 14-14-14

You can give RTT_WR /3 a try for SR b-dies
it will be incompatible with SETUP-Timings , and can cause issues with bad tCKE - but generally helps, now that 706 runs for you

PARK on /6 will lower received amperage
low procODT will lower send current
Low VDIMM also
low ClkDrvStr will barely amplify it
- soo at the very end, your dimms are underpowered 

It's no wonder, you need such high VDIMM


----------



## MrHoof

7/3/6 booted fine, I test with current timings tomorrow.

edit: 2-5-5 2-7-7 also boots without problem gonna do a aida to compare.
edit2:1-5-5 1-7-7 is little better, but i think i miss understood when u said dd to 2 thats why I normaly only do this stuff on weekends. So u mean 1-5-2 1-7-2 with DDs ?
2-5-5 2-7-7 resuluts in 39gb read 37gb copy 🤣


----------



## Veii

MrHoof said:


> 7/3/6 booted fine, I test with current timings tomorrow.
> edit2:1-4-4 1-7-7 is little better, but i think i miss understood when u said dd to 2 thats why I normaly only do this stuff on weekends. So u mean 1-4-2 1-7-2 with DDs ?
> 2-4-4 2-7-7 resuluts in 39gb read 37gb copy 🤣


Yea like this








Actually you can just use these timings 
Then 14-14-14-14-22-36 will be identical (272-202-124 tRFC)

EDIT:
tCKE is different for you
This was with BLCK, which is not showing itself








Was/Am working towards 2133+
That's the reason for tCKE 14+

EDIT2:
There is more performance with tWTR_ 5-14, but 6-14 is big times more stability - just also big times perf loss


----------



## Wacholek

Veii said:


> This has to be a forced PSP-FW update
> It happens on every new boot or board swap
> If the CPU FW is older, and the AGESA requires it, it will make one
> 
> The problem on that is,
> You rarely to never can revert back, till you bug it out with unstable memOC
> 
> Can you give a bit more infornation on the setup
> Which bios version, soo which SMU
> 
> I have a bit of a problem with this
> FCLK locks sit in the ABL ~ AGESA Bootloader & not PSP
> Unless you used anything 1.1.0.0 Patch C related, you shouldnt have had any lockdown issues
> 
> There is one thing tho,
> LCLK the toggle in AMD overclocking, has to be enabled
> Disabling it does bug out some security features, wipes part of the thermal limit, and wipes the PPT throttle limit
> 
> In such case also introduces 1 whole ns more latency. Only good if used with CTR else better enabled
> What you can do about it, i honestly think not much
> 
> Downgrading to anything that has SMU 50.26/56.30 or upgrading to 56.50
> I would likely downgrade, then let it sit again for such a long time till it discharges fully
> Then let it force update PSP-FW, the same way you documented
> But such is unrealistic tbh ~ waiting 1 month
> 
> Unless you where explicitly on SMU 56.34 which does have a 1900 lock
> There might be again some lockdown attempts happening on newer SMU
> Depends, please share a bit more information
> Sadly PSP-FW updates are nearly always "one-way"


To be honest , I never thought it would be that complicated problem. 
The factory bios was 2702 so AGESA V2 PI 1.1.0.0 Patch C. 
But soon after that I upgraded to 3402 AGESA V2 PI 1.2.0.1 Patch A and it was working fine until I let the board and CPU seat on the shelf. 
But definitely from the beginning 1900Mhz was not possible. 
After that I tried every bios with the same results. 
But there is one more think. All laggy stuff is always when CPU is on the factory boost. When I set manually 4Ghz in bios it boots "normally". Under windows programs are running slower but not more than 10% slower. There is Windows error generations present but CPU passes every test I through at it except mining. Aida memory test is more less ok. Slower but ok. 
Mining monero is almost completely gone. Before on the same settings I get 19300h/s now there is 2000h/s. 
And there is one more think that I noticed. 1.8 PLL voltage. It was always set to auto and was around 1.86V, and it it is at the same level at 1800Mhz. But at 2000Mhz it is 2.01V. After manual setting it to 1.8V there is no boot. Minimum voltage is 1.95V with a good boot. 

To sum it up. Can you tell me what can I do now? I do understand what you wrote but it is still to overwhelming for me. 
I can remove this cpu and let it discharge for two months but I would need your guidance how to prepare the motherboard for the next force PSP-FW update. 
In the meantime I can use other processor such as 5800x in the setup.


----------



## MrHoof

ok i just quickly tried 1-5-2 1-7-2 and the first time i got a bugged write result at 30850(only 1 run wich i didnt take a screenshot of ) wich is i think over the max of 1900mhz IF max. But read and copy increased aswell by like 100mb.


----------



## domdtxdissar

Nighthog said:


> If you want to run ~3800 and less.
> 
> More frequency requires more. Seems to scale with MCLK/UCLK frequency range.
> 1:2 Mode with for for example 5000Mts (1250UCLK) requires less rather than 1:1 4266Mts (2133UCLK)





Spoiler: 20 cycles @ 2:51:77















_edit_
Nevermind then, run cLDO_VDDP  @ 1110mv together with 1400mv vsoc if you want to 

@ * Veii*
Did you see my post regarding +500 PBO bosting with 5600x on agesa 1.1.1.0 ? Have you tried ?


----------



## Veii

domdtxdissar said:


> @ * @Veii*
> Did you see my post regarding +500 PBO bosting with 5600x on agesa 1.1.1.0 ? Have you tried ?


I did. Don't get that luxury 
ASRock never released AGESA 1.1.0.0D
We never got beyond +200 FCLK boost sadly

People tried to override it, but with no success later
Once the AGESA blob is compiled , same for the AMD OVERCLOCKING section
You can not really open it.
You certainly can not sign it afterwards
==========================
@Nighthog is correct
2:1 or 1:X:1 is easier than 1:1:1
VDIMM requirements increase - noise increases
Idk if 1050+ really is needed, as higher cLDO_VDDP requires far more procODT to balance it out
Soo 36.9+, maybe 40+ even








While we speak about difficulty








Here's some bugs
0W PPT, 0c THM
Happens if you disable LCLK fully







Lovely Zen Gremlins (bugs)

You can utilize it in combination with CTR and Hydra
Fully wipe any powerlimits
But EDC Fuse still is active - and it will try to throttle down constantly
At least on one stage
Similar to EDC bug, just with less effects
I can see it being useful if you have similar throttle or for dynamicOC ASUS feature 
Depends really , but hey it exists


----------



## gled_fr

Current daily stable ( don't have the screenshot, but it's tm5 60cycle stable, occt, ycruncher alone and ycruncher + heaven stable ):








Latest stable session tm5 session,but it was not that stable, framerate was very unstable during gaming, back to drawing board:








I also tried going down the voltage ( gotta love that l3 cache latency). What is interesting is that iod sub 1V ( bios before the droop ), it's a black screen even if it POST, min voltage able to run ( I did try also RTT 633 with again a single error, so I am missing something here too ):








So again trying at the regular voltage, single error territory again:








I am having the hardest time getting trcdrd down to 14, so trying to squeeze a bit more of the subtimings, and single error long after the beginning of the run territory is confusing... Those runs have the best copy and write bandwidth I was able to get, and seem to run in the 54.5-54.6 latency... just can't get stable.

What is also interesting, is that it seems like at some point one of my cores was unstable with lower cldo_vddp, ccd and iod, when it was stable with the 'normal' ones, which I don;t understand yet. No issue after going from -30 to -29 CO on that core.


----------



## byDenoso

Veii said:


> Flat timings generally are faster than odd ones you currently run


So a 15-20-20-40-60 will perform better than 15-20-18-38-56?
Disconsider the secondaries for that comparison


----------



## Veii

byDenoso said:


> So a 15-20-20-40-60 will perform better than 15-20-18-38-56?
> Disconsider the secondaries for that comparison


You can use tRAS = tRCD + tRTP
And then it will
But micron is another story


----------



## Wacholek

Veii said:


> This has to be a forced PSP-FW update
> It happens on every new boot or board swap
> If the CPU FW is older, and the AGESA requires it, it will make one
> 
> The problem on that is,
> You rarely to never can revert back, till you bug it out with unstable memOC
> 
> Can you give a bit more infornation on the setup
> Which bios version, soo which SMU
> 
> I have a bit of a problem with this
> FCLK locks sit in the ABL ~ AGESA Bootloader & not PSP
> Unless you used anything 1.1.0.0 Patch C related, you shouldnt have had any lockdown issues
> 
> There is one thing tho,
> LCLK the toggle in AMD overclocking, has to be enabled
> Disabling it does bug out some security features, wipes part of the thermal limit, and wipes the PPT throttle limit
> 
> In such case also introduces 1 whole ns more latency. Only good if used with CTR else better enabled
> What you can do about it, i honestly think not much
> 
> Downgrading to anything that has SMU 50.26/56.30 or upgrading to 56.50
> I would likely downgrade, then let it sit again for such a long time till it discharges fully
> Then let it force update PSP-FW, the same way you documented
> But such is unrealistic tbh ~ waiting 1 month
> 
> Unless you where explicitly on SMU 56.34 which does have a 1900 lock
> There might be again some lockdown attempts happening on newer SMU
> Depends, please share a bit more information
> Sadly PSP-FW updates are nearly always "one-way"


I just verified what smu version I have now. It is 56.53. And it sucks.
The oldest bios I can get is 2311 AGESA V2 PI 1.1.0.0 PatchB so SMU 56.33.
Or 3402 with AGESA V2 PI 1.2.0.1 Patch A witch should have SMU 56.50.
What should I do than?

EDIT:
I made a bios downgrade to 2311. Now SMU is 56.33 at least that is what AIDA said. 
Now there is no possibility that I can boot to 1900Mhz or 2000Mhz. POST error 07.


----------



## Alastair

So I am trying to overclock my ram. I have AVEXIR Core 2 8GBX4 3600 18-20-20-20-44 kit for my 3800X. And it is turning out to be rather difficult. I have given up on trying to reach 3800/1900. So I am also trying to tighten them up. 

My ram is B-die. But they seem to be garbage grade B-Die. Specifically the IC's are K4A8G085WB-BCTD. We know garbage tier B-die does seem to be a thing. Buildzoid got his hands on a set of Antec Series 3 ram that had BCBP B-die but it didn't overclock particularly well. Another funny thing is that firstly Antec Memory's website is a literal copy/paste of Avexir's website and their series 7 katana ram has the exact same specs as the Avexir's I have. So if anyone has the Katana series 7 and has gotten some good performance out of them let me know. 

The ram rolls over at 1.4V or above. So cranking 1.5V into them does nothing except cause the system to not POST. 

Here is what the timings look like on the stock XMP. 








And Aida 64 numbers. I know it says CR1 but with GDM on its actually CR2. CR1 wont post with GDM off. 










At this point I am wondering if I shouldn't drop down to something like 3466 and try tightening this up because 18-19-19-19-39 GDM OFF at 3600 failed (I tried to copy the primaries from a corsair B-die kit) And GDM On makes 18-19-19-19-39 actually 18-20-20-20-40 and performs the exact same as stock XMP in Aida and in Timespy CPU.


----------



## byDenoso

Veii said:


> You can use tRAS = tRCD + tRTP
> And then it will
> But micron is another story


Can you explain me better about micron?


----------



## mongoled

@tcclaviger

can you tell me about the Vipers your bought, are they still with A2 PCB and where did you purchase them from ?

Cheers


----------



## BK2000

I scrolled through hundreds of pages in thread and thought to myself: Fine I'll share my dram timings.
This is to my knowledge *THE BEST & LOWEST LATENCY DAILY SETUP of all 553 pages of posts here*_._
And it's achieved with only *1.5v*.
And it's a more powerful setup of *DR 4x8G*.
And it's in a much more difficult to stabilize* Gear1 & GDM off & CR1T mode*.
And it's stressed tested to run almost* without WHEAs, so much better Linpack / real world workload performance* than those posts with 2000 or over FCLKs who doesn't even dare showing you how much dark crap WHEAs they get (or maybe they are simply too noob to know).
Nough said...


----------



## deadfelllow

Alastair said:


> So I am trying to overclock my ram. I have AVEXIR Core 2 8GBX4 3600 18-20-20-20-44 kit for my 3800X. And it is turning out to be rather difficult. I have given up on trying to reach 3800/1900. So I am also trying to tighten them up.
> 
> My ram is B-die. But they seem to be garbage grade B-Die. Specifically the IC's are K4A8G085WB-BCTD. We know garbage tier B-die does seem to be a thing. Buildzoid got his hands on a set of Antec Series 3 ram that had BCBP B-die but it didn't overclock particularly well. Another funny thing is that firstly Antec Memory's website is a literal copy/paste of Avexir's website and their series 7 katana ram has the exact same specs as the Avexir's I have. So if anyone has the Katana series 7 and has gotten some good performance out of them let me know.
> 
> The ram rolls over at 1.4V or above. So cranking 1.5V into them does nothing except cause the system to not POST.
> 
> Here is what the timings look like on the stock XMP.
> View attachment 2519978
> 
> And Aida 64 numbers. I know it says CR1 but with GDM on its actually CR2. CR1 wont post with GDM off.
> View attachment 2519980
> 
> 
> 
> At this point I am wondering if I shouldn't drop down to something like 3466 and try tightening this up because 18-19-19-19-39 GDM OFF at 3600 failed (I tried to copy the primaries from a corsair B-die kit) And GDM On makes 18-19-19-19-39 actually 18-20-20-20-40 and performs the exact same as stock XMP in Aida and in Timespy CPU.



Its not a B die. It's a C die. Thaiphoon sees as a B die but it isnt. 

And C dies are voltage sensitive i do not recommend to go over 1.4ish volts


----------



## XPEHOPE3

Veii said:


> 5600X should be fully fine with these limits
> 
> 
> 
> 
> 
> 
> 
> 
> TDC maaybe can be lower to prevent voltage throttle, but it should be fine
> If you'd like to compare this for me
> L3











How would you comment on this? L3 cache got cured by your limits. Write bandwidth didn't.
What I set was the following: set PBO from Disabled to Manual both under AMD CBS and AMD overclocking, input all 3 of your limits, set Scalar to Manual 1x also under AMD overclocking (was previously set under AMD CBS).
Previous screen for comparison.


----------



## Veii

XPEHOPE3 said:


> View attachment 2520031
> 
> How would you comment on this? L3 cache got cured by your limits. Write bandwidth didn't.
> What I set was the following: set PBO from Disabled to Manual both under AMD CBS and AMD overclocking, input all 3 of your limits, set Scalar to Manual 1x also under AMD overclocking (was previously set under AMD CBS).
> Previous screen for comparison.


L3 was expected, written here but maybe not soo nicely written 
CoreCycler - tool for testing Curve Optimizer settings & CoreCycler - tool for testing Curve Optimizer settings
AMDs "limits" on stock are no limits
They are "a helping thing" for the users , yet the FUSE limits are artificial ~ especially the 5600X are hardthrottled
Lifting one stage of the throttling, is good - but doing it this way (sadly the only way i saw possible so far)
will also push more allcore current for the same test and if you touch scalar or not modify CO values - they will request more VID.. Peaking over 1.4v and then being hard throttled again *

* This was/is one of the reasons i kept my -30 CO , +85mV offset trick for soo long.
Cores requested a very low VID, FIT didn't catch them that way being near the 1.4v peak limit and so didn't frequency throttle.
Meaning, SSE & AVX loads could pull more and more current , without FIT noticing

An positive offset put on the PWM section, is not noticed by FIT (but a negative offset will eat away perf)
It does notice if the CPU exceeds (in our case) 1.45v - and will hard throttle on 1.55v by another sensor or hard shutdown on 1.75+ (can't say more)
But all these are 3 different sensors, and away from the 1.4v limit which we seem to have on our units
Which is also away from the PPT throttle limit, the CCA (Amperage) throttle limit (for AVX2 and helper for the EDC fuse limit) & the procHot 65c hard throttle limit
All these are different sensors. Kind of a godsend to have tool.exe but there are more sensors than these listed 8 ones that can trigger package throttle or GMI linkspeed (slowdown)

I think your cache performs exactly how it has to, and low L2 + L3 latency is also correct.
Usually one doesn't need to lift it that high like i did, but one should keep in mind that SOC and generally memOC will strongly cut into the powerbudget. You have to lift them up slowly
People see performance improvements with limits, because like on Matisse - a harsh EDC limit will lower provided voltage, and let the cores only throttle boost-state once voltage drops bellow their range
Here we can't do this anymore

AMD "fixed" L3 cache.
But "fixed" is a bad wording. They maaybe increased the link speed from 1.0x to 1.5x, but didn't really allow it to reach maximum boost of 2.0x
They reworked a lot, but such is currently lost potential & left performance on the table.

I know it's a lot of work, but please note down your VID & Freq held on all the 9 tests (on your old limits)
And then redo this with "my" well the "open limits" ~ and adjust TDC slightly higher or lower, till you meet the same VID and hold the same Freq
The most important part is keeping requested VID low.
Then you can compare both on Geekbench and SiSoftware Sandra Inter-Thread , Test

If the numbers are correct, you will see a performance uplift, by letting cache boost up to it's peak state
But i am not entirely sure how well this "overdrive till throttle" method is, for frame consistency
Usually will notice such in rhythm games where 2-3fps drops (600+ hold) are shown as stutter. Also FCLK Package throttle shows that way in inconsistent framerate
Just overall , keep this in mind ~ i haven't confirmed it's "the best" method to go on it.. Only so far the "other visible" way to limit back PBO overcurrent, by lifting 1st stage of powerthrottle


XPEHOPE3 said:


> Write bandwidth didn't.


This likely is a voltage and CO thing then ~ as all of these tests are also short burst allcore tests

Usually it's nearly always purely FCLK focused.
but it can be procODT, VDDP and 1.8 VDD related 
===============================================
About cache, once lifting these limits - keep your eye on the ACPI Perf Monitor








This thing.
Do not trust AMDs boosting system will manage and prevent overboost
It can very well overboost bug out once cache throttle is lifted.
Mentioning this, as cache perf has to do with powerbudget management - which has to do with powerplan and idle states (yes i have non atm, only P0 state)
Sadly at 1203A state, we still can not start using DF_C-States again, to gain back a bit of perf and lower latency
Hard suspended cores will oerboost spike
Usually 120-130% is what we can run, 160+ are overboost spikes.

EDIT2:
I do run atm Scalar 7, but was staying on a long time at 6 , and a bit of time on 8
Lifted EDC needs a redo on the CO values , as PBO will supply more voltage and it very easily can result that way in "loss of performance"


----------



## Alastair

deadfelllow said:


> Its not a B die. It's a C die. Thaiphoon sees as a B die but it isnt.
> 
> And C dies are voltage sensitive i do not recommend to go over 1.4ish volts


I am going on what I got off the IC's. K4A8G085WB-BCTD. I thought these were B's


----------



## deadfelllow

Alastair said:


> I am going on what I got off the IC's. K4A8G085WB-BCTD. I thought these were B's


just think about your kit 3600 18-20-20-20-44 

samsung kits be like 3600 14-14-14-28

or even 3600 16-16-16-32

so Its C die %100 percent

there is nothing like a bad bin b die. Its a C die.


----------



## Alastair

deadfelllow said:


> just think about your kit 3600 18-20-20-20-44
> 
> samsung kits be like 3600 14-14-14-28
> 
> or even 3600 16-16-16-32
> 
> so Its C die %100 percent
> 
> *there is nothing like a bad bin b die.* Its a C die.


Bad bin B die does exist. It can't not exist. Especially older B-dies. And I am going to go with garbage B. Like buildzoid got with that Antec kit. I am sure not all B die is a golden egg so the rejects HAVE to go somewhere. Besides I am going by the product number on my IC's. I took my spreaders off and that's what is on the PCB. K4A8G085WB-BCTD

Its like saying bad CPU's don't exist. They don't just toss the rejects in the bin. They just get sold as a cheaper lower level part.


----------



## byDenoso

Veii said:


> Do not trust AMDs boosting system will manage and prevent overboost
> It can very well overboost bug out once cache throttle is lifted.


Does overboost bug happens on Matisse too?
or only Vermeer?


----------



## byDenoso

Error 15 is so annoyng...let put all SD/DD's into 1


----------



## Alastair

deadfelllow said:


> just think about your kit 3600 18-20-20-20-44
> 
> samsung kits be like 3600 14-14-14-28
> 
> or even 3600 16-16-16-32
> 
> so Its C die %100 percent
> 
> there is nothing like a bad bin b die. Its a C die.


I will try some C-Die like timings and try treating them like C's and see where that goes.


----------



## deadfelllow

you can try

3733MHz CL17-21-8-21-42 1.36/1.37vdimm

Cas latency - 17
tRCDRD - 21
tRCDWR - 8
tRP -21
tRAS - 42


----------



## XPEHOPE3

Veii said:


> and *adjust TDC* slightly higher or lower, till you meet the same VID and hold the same Freq


Why would it matter if it's not hit by any of the tests?
Anyway, since my caches don't throttle now, I don't think potential performance uplift would be appreciable.
Running 9 tests via two boots (and then some while adjusting TDC, but then I wouldn't run every test, just the ones showing most and least VID and freq) sounds not as threatening, but I tried and got somewhat lost. _CPU Core VID (Effective)_ sensor I can report more or less easily, but frequencies... Do you want effective frequencies or what? Average over all cores maximums/averages? What should be HWiNFO polling period? Some tests are so short I have to lower polling period to 100ms and run the test several times, and only then I do see frequency does hit 4650. And AMD monitor doesn't catch it.
Small potential benefit, unclear methodology, no current symptoms of cache problems - looks like waste of time.

What seems to throttle is Write bandwidth, although by a little (so, again, might be waste of time). The only cue I have for that is the following.
AMD Per Core shows the same problem as HWiNFO shows:








The first core is late to the party all the time. Moreover, that write bandwidth test doesn't seem to provide uniform load on CPU, because core frequencies are not 100% all the time. The test starts at 4650, then drops somewhat, then cores 1-5 are at 4650, but core 0 isn't up until the end. Also both PPT Frequency Limiter and FIT VID Voltage Limiter in AMD Monitor do drop a little, *but they drop at the start of the test. *And yes, I've set HWiNFO to capture at 500ms to catch this. Setting to 100ms shows core 0 actually reaches 4650MHz (during first part of test, during second - 4645 MHz), but thread 0 usage is still not 100%:








*Can anyone confirm that even when you have perfect Write bandwidth, your HWiNFO would still show the same core usage pattern during Write bandwidth test?* Please set 100ms polling period in HWiNFO for that...


----------



## deadfelllow

deadfelllow said:


> you can try
> 
> 3733MHz CL17-21-8-21-42 1.36/1.37vdimm
> 
> Cas latency - 17
> tRCDRD - 21
> tRCDWR - 8
> tRP -21
> tRAS - 42


----------



## deadfelllow

deadfelllow said:


> you can try
> 
> 3733MHz CL17-21-8-21-42 1.36/1.37vdimm
> 
> Cas latency - 17
> tRCDRD - 21
> tRCDWR - 8
> tRP -21
> tRAS - 42


@Alastair


----------



## Alastair

deadfelllow said:


> @Alastair


Yeah I have a few suggestions to try. If I can hit 65ns I think I will be happy.


----------



## Alastair

deadfelllow said:


> @Alastair


ps I cant even boot 3733 at XMP


----------



## Veii

XPEHOPE3 said:


> Why would it matter if it's not hit by any of the tests?





XPEHOPE3 said:


> Running 9 tests via two boots (and then some while adjusting TDC, but then I wouldn't run every test,


Hm ?
Running the 9 y-cruncher tests and note down VID and generally held frequency

Aida64 is a too short burst test
Snapshot pooling would be needed, but that will influence 100% the Write bandwidth test.
Alone when enabled wifi does eat 1-2 MB/s away from it on idle
Maybe CTR can log Aida64 but rarely
Aida does push itself to realtime one some tests and freezes HWInfo
it's unlikely that you can track it that way

Only Y-cruncher, that has a 2 min held time - it's easy enough to track it with default pooling period of 2000ms


----------



## deadfelllow

Alastair said:


> ps I cant even boot 3733 at XMP


try at 3600 or increase soc voltage a little.

if it boots 3600 we can try increasing the voltages


----------



## Alastair

deadfelllow said:


> try at 3600 or increase soc voltage a little.
> 
> if it boots 3600 we can try increasing the voltages


I've decoupled fclk to try rule out the possibility of instability there


----------



## PJVol

*Veii*
Hi, did you notice the same in the latest fw for your itx? Looks like "internal rollback"


----------



## XPEHOPE3

Veii said:


> Hm ?
> Running the 9 y-cruncher tests and note down VID and generally held frequency


Original quote didn't contain "y-cruncher", so I thought you were speaking about 9 cache bandwidth tests of Aida 


Veii said:


> and adjust TDC slightly higher or lower, till you meet the same VID and hold the same Freq
> The most important part is keeping requested VID low.


But then why would you aim to "hold the same freq"? Isn't the goal to get higher freq at same or lower VID? Or is it just for comparison purposes?


----------



## XPEHOPE3

Veii said:


> About cache, once lifting these limits - keep your eye on the ACPI Perf Monitor
> 
> 
> 
> 
> 
> 
> 
> 
> This thing.


I don't have objects/counters with the same name as in your screenshot. But each counter has a description. Can you please post one? I assume it's in English.
The closest I get is object "Processor Performance", counter "% of Maximum Frequency", but instances are named differently: PPM_Processor_<number> instead of your 0,<number>.
Also during Write bandwidth test it doesn't overshoot. And during y-cruncher first test all those counters are straight 100%. Is it because I didn't fiddle with powerplans and you did? Or does it take setting scalars/CO to make it overshoot like on your screen? Seems like setting your limits isn't enough.

Can it be Win 11 difference? Or is it because one of us has chipset drivers installed and the other one doesn't?

EDIT: NVM, found it under "Сведения о процессоре"/"Производительность процессора %". And it does overshoot...


----------



## Alastair

deadfelllow said:


> you can try
> 
> 3733MHz CL17-21-8-21-42 1.36/1.37vdimm
> 
> Cas latency - 17
> tRCDRD - 21
> tRCDWR - 8
> tRP -21
> tRAS - 42


Gear down mode off I assume. Because if I just set cas to 17 and leave gdm on Its just going to give me cas 18 anyway?


----------



## Wacholek

PJVol said:


> *Veii*
> Hi, did you notice the same in the latest fw for your itx? Looks like "internal rollback"
> View attachment 2520053


That is correct. My CROSSHAIR VIII IMPACT did not get it yet.
I think they screw up something witch 53.
They definitely screw up my CPU.








MSI Also Rolls Out AMD AGESA 1.2.0.3 Patch C BETA BIOS Firmware For Its X570 & B550 Motherboards


MSI has also started rolling out the latest AMD AGESA 1.2.0.3 Patch C for its X570 & B550 lineup of motherboards.




wccftech.com


----------



## MK-Professor

I had these timings 14-14-14-14-28-42 for the last 7 months with no issues, recently I update my bios from 1202(2020/10/29) to version 2407(2021/07/21) and I can't get the same timings as before. I have to admit I had all my settings to auto, except the ram voltage(1.42) and the timings.

So I went from this
















to this


----------



## BK2000

ManniX-ITA said:


> I've set this one nice little 4066 MHz puppy as my daily:
> 
> View attachment 2490638
> View attachment 2490639
> 
> 
> Still living the dream!
> Tested only for 5 TM5 cycles.


What little puppy? Your WHEAs are over the roof! More like a gigantic turtle to me.
Timings loose as hell as well. Obviously your latency took a bloody dip.


----------



## Alastair

deadfelllow said:


> try at 3600 or increase soc voltage a little.
> 
> if it boots 3600 we can try increasing the voltages


I got frustrated because I feel like I am going NOWHERE and took the spreader off again. Because 1 it was 1am and I was tired and just pulled it off didn't really clean it up or anything. And 2 this kit is frustrating me.



I wiped it down with isopropyl. And low and behold K4A8G085WC-BCTD. 



I don't know if I just misread it because I was tired or what. But these are in fact...... 



C dies 



_dies inside_



SO. With that knowledge in hand. Where do we go from here. I don't want to buy a new memory kit. But I might consider it for Zen 3+ / Zen3 refresh. But at this moment I am unemployed so there are no $$$ in the bank right now so I have to make what I got WORK.


----------



## XPEHOPE3

Veii said:


> Do not trust AMDs boosting system will manage and prevent overboost
> It can very well overboost bug out once cache throttle is lifted.
> Mentioning this, as cache perf has to do with powerbudget management - which has to do with powerplan and idle states (yes i have non atm, only P0 state)
> Sadly at 1203A state, we still can not start using DF_C-States again, to gain back a bit of perf and lower latency
> Hard suspended cores will oerboost spike
> Usually 120-130% is what we can run, 160+ are overboost spikes.


LOOOL
Look at what happens when I run Aida write bandwidth test:













WTH?


----------



## Kildar

This seems to be the best I can do on this kit...


----------



## spajdr

XPEHOPE3 said:


> View attachment 2520044
> 
> 
> *Can anyone confirm that even when you have perfect Write bandwidth, your HWiNFO would still show the same core usage pattern during Write bandwidth test?* Please set 100ms polling period in HWiNFO for that...


I can confirm I can see similar result for Core 0 T0/T1 Usage, it's 62/63% for me during Write bandwidth AIDA64 test.


----------



## XPEHOPE3

spajdr said:


> I can confirm I can see similar result for Core 0 T0/T1 Usage, it's 62/63% for me during Write bandwidth AIDA64 test.


What write bandwidth do you get and at what FCLK?


----------



## Alastair

XPEHOPE3 said:


> Why would it matter if it's not hit by any of the tests?
> Anyway, since my caches don't throttle now, I don't think potential performance uplift would be appreciable.
> Running 9 tests via two boots (and then some while adjusting TDC, but then I wouldn't run every test, just the ones showing most and least VID and freq) sounds not as threatening, but I tried and got somewhat lost. _CPU Core VID (Effective)_ sensor I can report more or less easily, but frequencies... Do you want effective frequencies or what? Average over all cores maximums/averages? What should be HWiNFO polling period? Some tests are so short I have to lower polling period to 100ms and run the test several times, and only then I do see frequency does hit 4650. And AMD monitor doesn't catch it.
> Small potential benefit, unclear methodology, no current symptoms of cache problems - looks like waste of time.
> 
> What seems to throttle is Write bandwidth, although by a little (so, again, might be waste of time). The only cue I have for that is the following.
> AMD Per Core shows the same problem as HWiNFO shows:
> View attachment 2520043
> 
> 
> The first core is late to the party all the time. Moreover, that write bandwidth test doesn't seem to provide uniform load on CPU, because core frequencies are not 100% all the time. The test starts at 4650, then drops somewhat, then cores 1-5 are at 4650, but core 0 isn't up until the end. Also both PPT Frequency Limiter and FIT VID Voltage Limiter in AMD Monitor do drop a little, *but they drop at the start of the test. *And yes, I've set HWiNFO to capture at 500ms to catch this. Setting to 100ms shows core 0 actually reaches 4650MHz (during first part of test, during second - 4645 MHz), but thread 0 usage is still not 100%:
> View attachment 2520044
> 
> 
> *Can anyone confirm that even when you have perfect Write bandwidth, your HWiNFO would still show the same core usage pattern during Write bandwidth test?* Please set 100ms polling period in HWiNFO for that...


Single CCD ryzens don't get full write bandwidth. So 30ish GB/s is about what you should expect from a single CCD ryzen. Which is why the memory controller isn't under full load.

It only writes 16B/cycle. Vs 32B/cycle on Read. AMD did it to save power budget. So effectively your memory controller is only at half load


EDIT: I thought you were talking about your memory controller usage. I'm tired. I'm going to bed. It's 1am. Night


----------



## spajdr

XPEHOPE3 said:


> What write bandwidth do you get and at what FCLK?


----------



## Veii

XPEHOPE3 said:


> LOOOL
> Look at what happens when I run Aida write bandwidth test:



Might want to doublecheck if DF_C-States really where off ?
Yep it's a mess atm,


BK2000 said:


> What little puppy? Your WHEAs are over the roof! More like a gigantic turtle to me.
> Timings loose as hell as well. Obviously your latency took a bloody dip.


2nd post and 2nd time rude.
Come down from your high horse and behave
Not only are you rude towards everyone who give their best, but try to gather some impression with the lose timings you run


BK2000 said:


> And it's stressed tested to run almost* without WHEAs, so much better Linpack / real world workload performance* than those posts with 2000 or over FCLKs who doesn't even dare showing you how much dark crap WHEAs they get (or maybe they are simply too noob to know).
> 
> 
> BK2000 said:
Click to expand...

Nice CPU Error. Likely WHEA #18 
Just go back to the forum you came from. We don't need another Thread lockdown because of somebody who's adrenaline got higher , by the single success he experienced.

Initially i wanted to offer you to submit your score at








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com




But considering you WHEA (which is a bit embarrassing considering you mentioned "no whea") ~ that's i guess not the right place for you either 

Might want to share your voltages on this "supposedly not allcore" setup, soo we can actually learn anything from your post ~ other than reading the toxicity you spread ?

EDIT:
I want to also remind you that CAD_BUS SETUP timings beyond the half cutting point , turn into Command Rate 2T mode
Soo that's not a pure 1T either


----------



## XPEHOPE3

@spajdr 
Great! That means I don't have a cue to why is my write bandwidth throttled, because yours isn't although you see the same load 



Veii said:


> Might want to doublecheck if DF_C-States really where off ?


In BIOS they are, in ZenStates they are not.

@Veii 
I believe that's just another Dreamer account.

Also I've found that Aida64 latency actually always uses Core0 (and a little of Core1) to test latency. It's obvious both from HWiNFO and ACPI performance measurement. So @craxton maybe that's why you have higher latency than e.g. @mongoled at comparative timings - maybe your Core0 is the worst.


----------



## Veii

XPEHOPE3 said:


> @Veii
> I believe that's just another Dreamer account.
> 
> Also I've found that Aida64 latency actually always uses Core0 (and a little of Core1) to test latency. It's obvious both from HWiNFO and ACPI performance measurement. So @craxton maybe that's why you have higher latency than e.g. @mongoled at comparative timings - maybe your Core0 is the worst.


He wrote different. This appears to be a similar behavior to Bloax - tho even he had more dignity, and was rather trolling than really being a b**ch to everyone.
That's why he got banned, else usually a good OCer. Kind of miss him. Sadly he behaved very rude to Intel owners


XPEHOPE3 said:


> Also I've found that Aida64 latency actually always uses Core0 (and a little of Core1) to test latency. It's obvious both from HWiNFO and ACPI performance measurement. So @craxton maybe that's why you have higher latency than e.g. @mongoled at comparative timings - maybe your Core0 is the worst.


Ahm,
I'm not sure on each of the tests individually , as it shifts to realtime mode and hangs anything up that's not Aida64
But the latency test goes through all cores individually and then makes a short burst allcore test
A 5950X for example takes between 2-3 min to complete
While a 5600X does this in sub 30sec

EDIT:
Hey, it could be just another bloated installation 
Get Autoruns (Microsoft) 








Autoruns for Windows - Sysinternals


See what programs are configured to startup automatically when your system boots and you login.



docs.microsoft.com




and maybe compare what you autorun, to what i have








axp17ZL39Q.mp4


Watch "axp17ZL39Q.mp4" on Streamable.




streamable.com


----------



## XPEHOPE3

Disabling Package C6-State didn't make a difference, I still get overshoots of "% Processor Performance" counter for at least one SMT-core on some of the test runs. I believe this is usual performance counter inconsistency as explained in descriptions (they provide wrong values if they happen at certain time relative to too high priority task).



Veii said:


> But the latency test goes through all cores individually and then makes a short burst allcore test


That's 100% not what I see from ACPI measurement and HWiNFO (don't run together). Only the first logical core gets 100% usage in HWiNFO, rest are almost idle.








Only core 0 and core 1 are active throughout the test. And core 0 was active prior to the test. As soon as you run Aida64, your worst CPPC core gets raised (core 8 for me). After you run at least one test in Aida64, Core 0 gets raised instead (red on my screen).



Alastair said:


> So effectively your memory controller is only at half load


Problem is, it's less than a half. For my FCLK of 5800/3 = 1933.(3) I should get near 16*5800/3=30933.(3) MB/s, but I get ~10MB/s lower.


----------



## Veii

XPEHOPE3 said:


> Disabling Package C6-State didn't make a difference, I still get overshoots of "% Processor Performance" counter for at least one SMT-core on some of the test runs. I believe this is usual performance counter inconsistency as explained in descriptions (they provide wrong values if they happen at certain time relative to too high priority task).
> 
> 
> That's 100% not what I see from ACPI measurement and HWiNFO (don't run together). Only the first logical core gets 100% usage in HWiNFO, rest are almost idle.
> View attachment 2520088
> 
> Only core 0 and core 1 are active throughout the test. And core 0 was active prior to the test. As soon as you run Aida64, your worst CPPC core gets raised (core 8 for me). After you run at least one test in Aida64, Core 0 gets raised instead (red on my screen).


mmm,
Yea for me neither
But 130% peak is normal. 160-200+ is not 
Somehow ACPI doesn't track it, but 5950X take more than double the time to testt


----------



## XPEHOPE3

Veii said:


> Somehow ACPI doesn't track it, but 5950X take more than double the time to test


Can you please post a screen of ACPI performance monitor showing load pattern of Aida latency test? One from 5600X to compare with mine (and maybe one from 5950X).


----------



## Blameless

PJVol said:


> *Veii*
> Hi, did you notice the same in the latest fw for your itx? Looks like "internal rollback"
> View attachment 2520053


I also have an ASRock B550 Phantom Gaming ITX/AX. SMU Checker still shows 56.53, which jives with what I saw when I updated my bios this morning.










Looks like no rollback for this board.


----------



## Veii

Blameless said:


> I also have an ASRock B550 Phantom Gaming ITX/AX. SMU Checker still shows 56.53, which jives with what I saw when I updated my bios this morning.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Looks like no rollback for this board.
> 
> 
> PJVol said:
> 
> 
> 
> *@Veii*
> Hi, did you notice the same in the latest fw for your itx? Looks like "internal rollback"
Click to expand...

Ours is patch A , it's not B
Even when they say B

They maybe rolled it back, as when you disable LCLK - SMU fully breaks (again)


----------



## Veii

Blameless said:


> I also have an ASRock B550 Phantom Gaming ITX/AX. SMU Checker still shows 56.53, which jives with what I saw when I updated my bios this morning.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Looks like no rollback for this board.











Yours actually might be B 
Awkward
I didn't see this update


----------



## PJVol

XPEHOPE3 said:


> Can anyone confirm that even when you have perfect Write bandwidth, your HWiNFO would still show the same core usage pattern during Write bandwidth test?


During the "write bandwidth test" threads are loaded in the following order: 11-9-7-5-3-1-10-8-6-4-2-0. And sometimes hwinfo just can not catch the last thread load, so it shows <100% for core 0.


----------



## PJVol

Blameless said:


> I also have an ASRock B550 Phantom Gaming ITX/AX. SMU Checker still shows 56.53


Yeah, just checked both files from the ASRock site for your ITX (L2.12 and L2.14) and they seem to be identical (smu for cezanne is old - 64.46). Something certainly is messed with the last update


----------



## Veii

PJVol said:


> Yeah, just checked both files from the ASRock site for your ITX (L2.12 and L2.14) and they seem to be identical. Something certainly is messed with the last update


Just did too, it was Patch A
But the new one is Patch-C

SMU, ABL , Chipset FW stays identical
I missed this patch C

So far nothing new
I can test SMU breaking bugs again - but AGESA blob got updated
Well "updated"
On one hand ABL is Patch B, on the other hand AGESA initially was patch A
This now is Patch B with AGESA Blob Patch C

Eh whatever, it runs 
Here is the version without AMI Security checks @Blameless


http://www.filedropper.com/vb55pitx2


The only issue you can have, is issues with BAR mode if you cmos reset ~ as disabled AMI security checks, will break encryption to some extend
Soo CSM sometimes doesn't want to be enabled.
Nothing big, just so you know - if you experience it, you will need to CMOS reset , then configure CSM off 4G on, and then only it runs again
Here is the same thing for @PJVol,


http://www.filedropper.com/vb550ex42



Only so you can play with RU-Tool or similar tools





RU.EXE + RU.EFI


R U an engineer? You must be a BIOS engineer to find me here! This is home of RU.EXE and RU.EFI.




ruexe.blogspot.com





I recommend to flash it normally via bios, so your NVRAM profiles stay
Also recommend to load afterwards your highest FCLK possible - which will cause it to reboot 3 times
Just to ensure nothing random happens (psp )
Oh AMD CBS + Settings stay, but CO needs to be reconfigured after a profile load

EDIT:
So far nothing awkward
Same latency, same Memory Bandwidth
Same WHEA free (shown where experiments 24h ago)







Feels like no changes at all
I'll need to dig through it to see what this AGESA implements at all
Likely such changes will only show up, once hidden entries actually start to have assigned menu points

EDIT2:








If this is to believe, then it doesn't matter for us anyways 
Only maybe interesting thing would be , to check which ABL these SMU 56.52 guys , run
As it's fine for ASRock and fine for us as it seems.
Nothing FCLK related (issues vise) ~ to what i can see

EDIT3:
Aside from what seems to be more consistently hitting 200GB/s L3 for some reason
This time without even disabling Wifi
There shouldn't be a change. I doubt this is also anything but randomness ~ but it makes you suspicious 








Well at least it shows that Aida64 can be somewhat consistent.
Just closed my browser and rerun it - killing no services. Soo WinUpdate also runs


----------



## Blameless

I flashed it by using Instant Flash to go back to 1.80 then Flashrom to erase the ROM and then write the 2.14 image.

Haven't noticed any changes yet either, but I haven't tested for WHEAs at previously borderline FCLKs.


----------



## PJVol

Veii said:


> Only maybe interesting thing would be , to check which ABL these SMU 56.52 guys , run


This is what bios report:









Checked a couple of x570 boards (taichi and PGx4) - 56.53 inside, b450 pro4 and b550 HDV both with 56.52
Just curious, if there's a similar confusion with other vendors' boards and what this might mean... 
Haven't noticed anything different from the 1.2.0.3 b so far.


----------



## Veii

PJVol said:


> This is what bios report:
> View attachment 2520121


Ooh you are one of "those"
Hmmm.
This split makes no sense , to be quite honest


Blameless said:


> I flashed it by using Instant Flash to go back to 1.80 then Flashrom to erase the ROM and then write the 2.14 image.
> 
> Haven't noticed any changes yet either, but I haven't tested for WHEAs at previously borderline FCLKs.


It should have passed secure checks, edits are tiny 
I can't change much, else i break secure capsule
Yes the same - down to 1.60 for me and then Flashrom
But be aware , flashrom can actually brick the board - as AMD did SPI lockdown nonsense with AGESA 1.1.8.0+ (soo 1191 & 1200)


----------



## Alastair

So now that I have established that my RAM is infact C-die I have switched my approach.
So firstly I decided to establish a baseline of how low I can go on volts with XMP.

So I set procODT to 40 because apparently my motherboards auto setting to 53.3 is too high? What effect does that have?
My drive strengths are all on 20ohm.

xmp3600 18-20-20-20-44.
POSTs but crashes windows on start up @ 1.26V set in bios
Logs to windows unstable @ 1.27V set in bios GET seems to be 1.29V
Memtest unstable @ 1.28V SET 1.3V GET
Seems happy @ 1.29SET 1.31GET









so it seems I have a baseline. Where to from here.


----------



## Wacholek

Veii said:


> This has to be a forced PSP-FW update
> It happens on every new boot or board swap
> If the CPU FW is older, and the AGESA requires it, it will make one
> 
> The problem on that is,
> You rarely to never can revert back, till you bug it out with unstable memOC
> 
> Can you give a bit more infornation on the setup
> Which bios version, soo which SMU
> 
> I have a bit of a problem with this
> FCLK locks sit in the ABL ~ AGESA Bootloader & not PSP
> Unless you used anything 1.1.0.0 Patch C related, you shouldnt have had any lockdown issues
> 
> There is one thing tho,
> LCLK the toggle in AMD overclocking, has to be enabled
> Disabling it does bug out some security features, wipes part of the thermal limit, and wipes the PPT throttle limit
> 
> In such case also introduces 1 whole ns more latency. Only good if used with CTR else better enabled
> What you can do about it, i honestly think not much
> 
> Downgrading to anything that has SMU 50.26/56.30 or upgrading to 56.50
> I would likely downgrade, then let it sit again for such a long time till it discharges fully
> Then let it force update PSP-FW, the same way you documented
> But such is unrealistic tbh ~ waiting 1 month
> 
> Unless you where explicitly on SMU 56.34 which does have a 1900 lock
> There might be again some lockdown attempts happening on newer SMU
> Depends, please share a bit more information
> Sadly PSP-FW updates are nearly always "one-way"


If I would have a second motherboard with older PSP is it possible that when I connect my 5950x to that motherboard the PSP will downgrade and I will not have to wait a month?


----------



## domdtxdissar

Have received my new 2x16gb 4000C14d

Took some pictures of the 10 layers pcb, for those interested.



Spoiler: Pictures























































Think i will try for flat CL14 tomorrow with pure T1 without (56) setup-time, wish me luck


----------



## MyUsername

domdtxdissar said:


> Have received my new 2x16gb 4000C14d
> Think i will try for flat CL14 tomorrow with pure T1 without (56) setup-time, wish me luck


I have wasted so much time chasing that, I can boot with these timings but it's about a billion miles from being stable. Is there really any difference between trcdrd 14 to 15 and 1t to 2t that you can actually notice?


----------



## deadfelllow

@Alastair

My friend just bought team t force vulcan [email protected]

In thaiphoon it sees as a B die as well but it is not


I oc'ed kits to 3533 mhz with timigs

17-19-19-19-38 with 1.28 volts


As i said C dies are voltage sensitive.

You can even try lower the xmp voltage.

it wasnt boot @3533 18-20-20-20 with 1.35 volt

but i changed to 1.28 volt @3533 17-19-19-38

it booted and stable as well


Consider this. @Alastair


----------



## gled_fr

Kildar said:


> This seems to be the best I can do on this kit...
> 
> View attachment 2520073


GDM disabled, Cmd2T: 1T

look at my previous screenshots, we have the same kit you can go lower. Flat cl15 1.45 vdimm or very tight subtimings 1.46vdimm

your vsoc seems high so does your cldo_vddp.

You'll have to work on your procodt, rtt* and *DrvStr

In my non expert opinion, there's no benefits at this point to try to reach cl14, I get the same latency and bandwidth at flat 15 primaries, unless I finally crack the trcdrd 14 which prove to be not stable even at 1.52V.


----------



## Alastair

deadfelllow said:


> @Alastair
> 
> My friend just bought team t force vulcan [email protected]
> 
> In thaiphoon it sees as a B die as well but it is not
> 
> 
> I oc'ed kits to 3533 mhz with timigs
> 
> 17-19-19-19-38 with 1.28 volts
> 
> 
> As i said C dies are voltage sensitive.
> 
> You can even try lower the xmp voltage.
> 
> it wasnt boot @3533 18-20-20-20 with 1.35 volt
> 
> but i changed to 1.28 volt @3533 17-19-19-38
> 
> it booted and stable as well
> 
> 
> Consider this. @Alastair


Yes 3200 16-18-18-18-38 is the same timings as the 3200mhz version of my kit. My ram comes in 3200 16-18-18-18-38 and 3600 18-20-20-20-44.

When it comes to C-dies what are we looking at for a starting point on the secondaries and tertiary's? Because since this ram isn't on my boards QVL it could be going a bit screwy with the secondary and tertiary timings and making life difficult for me. Things like timings being in a ratio or in sync with one another. I've seen forum posts saying TRP, TRC, TWR, TRTP and TRFC being linked somehow? Or TRFC is a multiple of TRC. Or TRC is TRAS+TRP. I feel a bit out of my depth. In the DDR3 days I didn't bother with secondaries or tertiary's. I aimed for my primaries and that was that.

Also how does c-die respond to other settings like drive strengths, PROCODT etc. And also secondary voltages like dramVPP and termination voltage.

I don't know if it's relevant. But my gigabyte motherboard is VERY aggressive on memory voltages.

SET VDIMM 1.35V = GET 1.38V
DRAM termination 0.6V set = 0.67V get (no I wasn't using VTT 0.6 with 1.35vdimm)
The VPP is also weird as well but I'm not at my computer so I can't tell you exact readouts there right now. 

So I don't know if my motherboard screwing up the voltages is having an effect on stability as well.


----------



## gled_fr

Ok same perfs flat 15s primaries than cl14 trcdrd 15, but at 1.46v instead of 1.51v vdimm.

I think I am going to give up chasing trcdrd 14 for now, and be happy with that cl15 24/7 settings:









i was able to reduce vddp, ccd and iod voltages too from previous cl15 settings. Still not able to run at IF1933 without a ton of WHEA though, that I still need to understand if it could work...


----------



## w0wkin

Does anyone else have been experiencing mouse lagging and hanging in the beginning of Prime95 blend testing? Is it normal?


----------



## spajdr

w0wkin said:


> Does anyone else have been experiencing mouse lagging and hanging in the beginning of Prime95 blend testing? Is it normal?


In my case if that happens I have unstable RAM settings or WHEA error.


----------



## Audioboxer

Should finally be seeing my RMA GPU ship in next day or so, what a saga... lol. Back to memory though, I've narrowed my budget down to 3 options all priced within a small amount of each other 

3600 CL14 (14-15-15-35) at 1.45V - Cheapest option
4000 CL16 (16-16-16-36) 1.40V
4400 CL17 (17-18-18-38) at 1.50V - Highest speed at a reasonable CL for downclocking

I'm thinking that the 4000 CL16 is the best option. Main goal is to try and hit 3800 CL14. Though being rated for 4000 CL16 could be nice if I can get IF 2000 without WHEA errors in the future. Boots just now but get WHEA.


----------



## Veii

Audioboxer said:


> 4000 CL16 (16-16-16-36) 1.40V


Best option
lowest VDIMM and best binning out of the 3
200MCLK more , just 1 tRCD more
The other stepup is more voltage, yet 2 tRCD more
Consider Corsair LPX has also high binned b-dies out

Also Ripjaws are 8 layer but no RGB & the heatsink is designed for A0 PCB / A1 A2 are half covered only (it cools well but still)
TridentZ are 10 layer , yet have RGB and software that has to always run to turn off their RGBs. No EEPROM flash


----------



## Audioboxer

Veii said:


> Best option
> lowest VDIMM and best binning out of the 3
> 200MCLK more , just 1 tRCD more
> The other stepup is more voltage, yet 2 tRCD more
> Consider Corsair LPX has also high binned b-dies out
> 
> Also Ripjaws are 8 layer but no RGB & the heatsink is designed for A0 PCB / A1 A2 are half covered only (it cools well but still)
> TridentZ are 10 layer , yet have RGB and software that has to always run to turn off their RGBs. No EEPROM flash


Thanks Veii I thought so. I seen the Corsair 4000 CL16 and 2x8GB is OK for stock but 2x16GB either doesn't seem to be stocked or even exist. I'll have a second look, I need 2x16. RGB really doesn't bother me, I don't care. Happy to have none if it means cooler RAM and/or less software running.

*edit *- Found they do a Ripjaws version F4-4000C16D-32GVKA So same b-die but no RGB.


----------



## Akex

Any idea to help boot with GDM OFF 2T?
Thank you


----------



## Kildar

gled_fr said:


> GDM disabled, Cmd2T: 1T
> 
> look at my previous screenshots, we have the same kit you can go lower. Flat cl15 1.45 vdimm or very tight subtimings 1.46vdimm
> 
> your vsoc seems high so does your cldo_vddp.
> 
> You'll have to work on your procodt, rtt* and *DrvStr
> 
> In my non expert opinion, there's no benefits at this point to try to reach cl14, I get the same latency and bandwidth at flat 15 primaries, unless I finally crack the trcdrd 14 which prove to be not stable even at 1.52V.


What's weird is it won't post at 14 but I can get 4000/2000 at those timings. It's just not stable. I wonder if loosening timings and running at 4000/2000 would be better?


----------



## domdtxdissar

domdtxdissar said:


> Have received my new 2x16gb 4000C14d
> 
> Took some pictures of the 10 layers pcb, for those interested.
> 
> 
> 
> Spoiler: Pictures
> 
> 
> 
> 
> View attachment 2520151
> 
> View attachment 2520152
> 
> View attachment 2520153
> 
> View attachment 2520154
> 
> View attachment 2520155
> 
> View attachment 2520156
> 
> 
> 
> 
> Think i will try for flat CL14 tomorrow with pure T1 without (56) setup-time, wish me luck


New bios and new memory sticks are fighting me at every step of the road, but have managed to stabilize a "baseline-profile".









Working on tightening the secondary timings atm: (still work in progress, new timings marked in green)








Pure T1 are proving much harder then expected... Not so sure i will be able to run pure T1 with this 32gig set anymore.. But there is no doubt this memory is better binned then my previous 4x8GB sticks. tRFC @ 228 and below seems possible


----------



## Dasa

Anyone else seeing a jump in SOC power use with IF over 1600?
My system with the V set to values for my 4000c15 OC goes from ~1.5w idle 6-7w load to ~7-8w idle 10-13w load just by changing from 1600IF or lower to anything over 1600IF in or out of 1:1.
The increased V is adding ~1-2w load but doesn't affect idle.
Verified with power use from wall.


----------



## FleischmannTV

I've got a MSI X570 Tomahawk and it's the same. Mine goes from 3.5W idle / 7W load to 10W idle / 15W load with my 5800X. I've also noticed that raising the IF >1600 automatically enables SOC/Uncore OC Mode which cannot be disabled until IF is at <= 1600. Keeping voltages the same doesn't change it.


----------



## Dasa

Thanks it is interesting to hear from someone with a different chipset & brand MB experiencing the same behavior.

Don't think I have seen SOC/Uncore OC Mode in the GB B550 BIOS.
Apparently it should allow a drop in idle power use due to reduced clocks\v when disabled but I have never seen them drop in software and shouldn't be the reason for the increase in load power use unless it does something else on top of disabling idle states for IF.


----------



## TimeDrapery

Dasa said:


> Thanks it is interesting to hear from someone with a different chipset & brand MB experiencing the same behavior.
> 
> Don't think I have seen SOC/Uncore OC Mode in the GB B550 BIOS.
> Apparently it should allow a drop in idle power use due to reduced clocks\v when disabled but I have never seen them drop in software and shouldn't be the reason for the increase in load power use unless it does something else on top of disabling idle states for IF.


It's there in a few places (AMD Overclocking, XFR Enhancement, and SMU Options [as APBDIS, also "kind of" as DF C-States but not really]) and it certainly impacts power budgeting/consumption but fully functional DF C-States aren't really a thing last time I checked... Although it has been a while and I have updated BIOS and CPU since then so perhaps I should check again (overboost bug is definitely still a thing... Thank you ZenTimings... Although I'm still confused on why you do what you do) and see what they're like nowadays

@craxton

Sorry dude! I've been away for a minute... Here's where I'm at with the new 5800X










I hate the cache throttling, I hate that you have to use a tool to somewhat work around it because of the lack of persistence once you apply the EDC limit, I hate that AMD took the original "Motherboard" limit away through an update without saying so, and I love the CPU... It's been a blast ****ing with CO counts over and over and over again with different Fmax settings and I love playing with the memory and the controller... I wish I could figure out how to **** with memory training more but that's ongoing, Gigabyte took away options previously available (or maybe AMD did through a similar update?) in those submenus, no idea why, now I'm more confused 😂😂😂😂😂

Ah! I'm rather stoned so I totally forgot to add the part about ZenTimings!

_*Edit*_: This is wrong, it doesn't reactivate full DF S-States but it does enable full C-6 states and that's what I'm finding confusing

Does anyone know why running ZenTimings appears to reactivate full DF C-States? For example, I'm running the boost tester with no ZenTimings window (the application isn't running)... My cores approach 0MHz but never reach it, they stay around 24MHz or so according to HWiNFO64 in snapshot polling mode

If I'm running ZenTimings though... My cores go all the way to 0MHz (core parking is disabled in the Windows 10 Power Plan I created) and I see higher effective clocks in HWiNFO64, again in snapshot polling mode, and I see the OB bug slither out and jack my effective clocks to 11 gazillion MHz as it's wont to do

Why would this be? I used to think it was AIDA64 highjacking something about powering so it can individually select cores during testing but now I'm finding myself documenting a ZenTimings window in some of my testing and I'm seeing this isn't the case... I'm not very concerned about it, I actually find it useful at times, but I'm intrigued as to why this would be

Any ideas?


----------



## Dasa

TimeDrapery said:


> It's there in a few places (AMD Overclocking, XFR Enhancement, and SMU Options [as APBDIS, also "kind of" as DF C-States but not really]) and it certainly impacts power budgeting/consumption but fully functional DF C-States aren't really a thing last time I checked.


Ah right under my nose thanks.
SOC/Uncore OC Mode enabled vs disabled doesn't seem to make any difference to CPU SoC Power use idle or load at 1600IF or 2000IF.


----------



## TimeDrapery

Dasa said:


> Ah right under my nose thanks.
> SOC/Uncore OC Mode enabled vs disabled doesn't seem to make any difference to CPU SoC Power use idle or load at 1600IF or 2000IF.


It's (it being SOC/Uncore OC Mode) likely either enabled in another submenu or DF C-States are disabled by default on your BIOS/board... What BIOS are you on?


----------



## XPEHOPE3

TimeDrapery said:


> If I'm running ZenTimings though... My cores go all the way to 0MHz (core parking is disabled in the Windows 10 Power Plan I created) and I see higher effective clocks in HWiNFO64, again in snapshot polling mode, and I see the OB bug slither out and jack my effective clocks to 11 gazillion MHz as it's wont to do


Main question to ask here I think is if you disabled ZenTiming's monitoring of voltages.


----------



## TimeDrapery

XPEHOPE3 said:


> Main question to ask here I think is if you disabled ZenTiming's monitoring of voltages.


Yup, that looks like it was the culprit... I disabled voltage monitoring and now core speed is lower, as it was without ZenTimings, and cores aren't dropping to 0MHz

So, what's this mean? Is it interfering with the polling interval and all the data presented via HWiNFO64 while it's running is false? Or do the cores clock lower and higher? Or does it matter 😂😂😂😂😂


----------



## Dasa

TimeDrapery said:


> It's (it being SOC/Uncore OC Mode) likely either enabled in another submenu or DF C-States are disabled by default on your BIOS/board... What BIOS are you on?


SoC/Uncore mode was still on Auto in once place so set it to disabled\disabled in both places with DF C-States changed form auto to enabled but no difference at 2000IF.
SoC/Uncore mode enabled\enabled at 1600IF still drops to ~2w idle.

Edit: oh yeah BIOS is F13j.
SoC V is set in the first overclocking menu and left at 0 under SoC/Uncore.


----------



## XPEHOPE3

Progress regarding write bandwidth throttle I have.
Out of luck I decided to test in safe mode (w/o network) and I managed to get exactly 2 types of results:
















Notice how write bandwidth / CPU clock remains constant: 30915/3698 ~ 30953/3702.5 ~ 8.36. BTW, 836=4*11*19 
Also sometimes CPU clock is reported as 3697.9 instead of 3698, with the same bandwidth. I get 30915 result considerably more often than 30953.
Checked the same thing without safe mode and CPU clock always reported 4650.1 while write bandwidth was any value from 30921 to 30925.

Judging from the fact that 30953 is above potential maximum of 30933.(3), I would say that might be a Windows counter problem. That is, I suspect Aida64 uses Windows performance counters to report write bandwidth, and since those bug out, write bandwidth also bugs out.
@Veii any thoughts?


----------



## TimeDrapery

Dasa said:


> SoC/Uncore mode was still on Auto in once place so set it to disabled\disabled in both places with DF C-States changed form auto to enabled but no difference at 2000IF.
> SoC/Uncore mode enabled\enabled at 1600IF still drops to ~2w idle.
> 
> Edit: oh yeah BIOS is F13j.
> SoC V is set in the first overclocking menu and left at 0 under SoC/Uncore.


There shouldn't be a difference at 2000MHz so that makes sense, at 1600MHz you should see an even larger difference if you let the PHY power down by enabling... Powerdown Mode 😂😂😂😂😂


----------



## domdtxdissar

I found this buildzoid video to be pretty interesting in regards to the usefulness of Aida64: AIDA's and Geekbench's memory tests don't detect bad tRRD and tFAW timings








Its not so long ago ppl were recommending "custom tFAW setup" to get better latency in (only) Aida64, with no regards to "real performance" in less synthetic benchmarks.


----------



## Dasa

domdtxdissar said:


> I found this buildzoid video to be pretty interesting in regards to the usefulness of Aida64:


Maybe accurate for the Intel test platform he used but it seems to be within margin of error when I test tFAW 6,12,16,24 with 4-4 or 4-6
Timespy CPU score is 13388-13552
Ran at 4-4-16 twice and scored 13552 first run and 13403 second run.
The new 3dmark CPU benchmark also didn't seem to see much difference.

Since I am running 4-6 I had been wondering if tFAW 16 was overly tight.
Maybe with a more consistent benchmark it would be possible to see a small difference.


----------



## Kildar




----------



## glnn_23

Started stability testing with a 5700g


----------



## Netarangi

glnn_23 said:


> Started stability testing with a 5700g
> View attachment 2520337


Sick let us know how it goes! Do you have a comparable aida64 with another cpu?


----------



## Audioboxer

Narrowed down my next purchase to two sets of Ripjaws

DDR4-3600MHz CL14-14-14-34 1.45V
32GB (2x16GB)

DDR4-4000MHz CL16-16-16-36 1.40V
32GB (2x16GB)

The CL14 set is a little bit more expensive. This would lead me to think it might be a slightly better binning even running at 1.45v at 3600?

Ripjaws are cheaper than RGB sets, I couldn't care less about RGB and as I have a 2 dimm motherboard now even if the RGB causes 0.5 degrees more of heat I need to take that into account with airflow and 2 dimms.


----------



## reddify

domdtxdissar said:


> I found this buildzoid video


BZ restart PC, run AIDA once, and take the result as valid. Then restart, enter BIOS, change values, enter Win, again run AIDA right after the reboot and again take the 1st AIDA result as valid. Then he compare those two results and says a verdict.
Am I the only one who see a strange thing? Like, when you start AIDA, then 1st (2,3...) result is almost never accurate. You need to run it few times. And then - as @Veii said - you are looking as well for consistency. If the memory latency results are more than .3 ns different, it means the ram is not stable.
Conclusion? I am confused!


----------



## sendap

reddify said:


> If the memory latency results are more than .3 ns different, it means the ram is not stable.


i disagree. On a daily Win install there is lots of background noise. And AIDA is very sensitive to that. So a difference in ns from run to run is normal.
Sometimes you get 10 results that differ by max 0.1ns and then on the 11th run it is +0.5ns
Best way to mitigate is a stripped down Win install.
I get best and consistent latency results when running WIN in diagnostics mode (not to confuse with save mode). But be carefull, some folks locked themselves out by running diagnostics mode.


----------



## Henry Owens

Kildar said:


> View attachment 2520327


How did you do this ,😭


----------



## domdtxdissar

domdtxdissar said:


> New bios and new memory sticks are fighting me at every step of the road, but have managed to stabilize a "baseline-profile".
> View attachment 2520228
> 
> 
> Working on tightening the secondary timings atm: (still work in progress, new timings marked in green)
> View attachment 2520229
> 
> 
> Pure T1 are proving much harder then expected... Not so sure i will be able to run pure T1 with this 32gig set anymore.. But there is no doubt this memory is better binned then my previous 4x8GB sticks. tRFC @ 228 and below seems possible


Done tightening the timings for now, think i will switch over to trying to stabilize T1, with or without 56 setup-time now..
Managed to squeeze out *228 (120ns) tRFC* together with *tWR 10* and *tRTP 5* which is a new record for me


----------



## Kildar

Henry Owens said:


> How did you do this ,😭


Golden 5900x, B-Die ram and a Good MB!


----------



## MrHoof

Veii said:


> 1.42-1.46v is required for a flat CL15-15-15 set
> A flat 14-14-14 set requires near 1.48-1.56v
> All depends on RTT and procODT
> 
> Going with lowest 2ndaries and sacrificing flat timings stability, is the wrong way to pick
> if your 2ndaries and tertiaries really are fine - you will be able to run 15-15-15-21-36, tRTP 6, tWR 12
> 
> 
> 
> 
> 
> 
> 
> 
> On your 1.5v+
> 
> Oor 15-15-15-15-23-38, tRTP 8, tWR 16
> 266-198-122 (140ns)
> This should run sub 1.48v
> 
> The same would be for 14-14-14-28-42 or 14-14-14-14-22-36 (tRTP 8, tWR 16)


I tried alot of things this weekend.all at 1.51v
15-15-15-21-36, tRTP 6, tWR 12, trfc 216 would not boot cause anyting below 250 dosnt even boot, 260 is still unstable.

15-15-15-15-23-38, tRTP 8, tWR 16 266-198-122 (140ns), error 2,12 in 1usmus tm5 in minutes. Alos tried 15-15-15-14-24-38 and up to 36.3 proc odt and 40 clkdrvstr same result. But tRAS-TRC below 25-40 is just unstable.

After that I tried to maybe train cl14 by miracle but ofc that did not work.

So I just made tripple sure my current timings are stable and they dont error or crash in any test. ycrunsher all test 3 cycle pass. karhu 2h 7000% pass. tm5 1usmus 25cycle pass. tm5 anta 12 cycle pass.

I also did bench flat 15-15-15-25-40 compared to 15-8-15-14-26-40 and the 8 trcdwr gains me about 400 mb copy and just perform overall better.









The kit is rated 3600 cl17 afterall and on my old board needed 1.44v aswell for Flat c16/32/42. So i dont think 1.51v is to unrealistic for a tight c15 set.


----------



## Dollar

domdtxdissar said:


> I found this buildzoid video to be pretty interesting in regards to the usefulness of Aida64: AIDA's and Geekbench's memory tests don't detect bad tRRD and tFAW timings
> 
> Its not so long ago ppl were recommending "custom tFAW setup" to get better latency in (only) Aida64, with no regards to "real performance" in less synthetic benchmarks.


If you still want to use AIDA I suggest using the photoworxx test as it shows massive performance increase with tighter tFAW.


----------



## Dasa

glnn_23 said:


> Started stability testing with a 5700g


I would love to see how that does in TimeSpy CPU benchmark with that RAM speed or the new 3dmark CPU benchmark.

Maybe also with a fixed all core OC to see how the IPC compares to 5800X.


----------



## XPEHOPE3

If anyone wondered what this value is in AMD Monitor (SVI2 SOC Set Volt):







It's exactly equal to SOC OVERCLOCK VID Voltage:

















43 hex = 67 dec, 1.55-67*0.00625=1.13125.
SOC OVERCLOCK VID by default is 0 and it translates to SVI2 SOC Set Volt of 1.2. So that 0 is actually 56 in dec (38 in hex)

However, I don't know what this setting is about


----------



## XPEHOPE3

XPEHOPE3 said:


> Progress regarding write bandwidth throttle I have.
> Out of luck I decided to test in safe mode (w/o network) and I managed to get exactly 2 types of results:
> View attachment 2520294
> View attachment 2520295
> 
> 
> Notice how write bandwidth / CPU clock remains constant: 30915/3698 ~ 30953/3702.5 ~ 8.36. BTW, 836=4*11*19
> Also sometimes CPU clock is reported as 3697.9 instead of 3698, with the same bandwidth. I get 30915 result considerably more often than 30953.
> Checked the same thing without safe mode and CPU clock always reported 4650.1 while write bandwidth was any value from 30921 to 30925.


Some more progress...
I've changed just about everything in my BIOS apart from CO and vCore and in ZenStates Power tab, to see if it has any effect on Write bandwidth results of Aida64, and found the following.
If I set default PBO limits and clear all ticks on ZenStates Power tab, I get almost perfect result. (I have FCLK 1933.(3), so for 1-CCD CPU one should expect 16*1933.(3)=30933.(3) MB/s)







Package C6-State has no influence, Core C6-State drops result somewhat, but the main problem arises from Core Performance Boost (notice it raises CPU freq):



















If I set PBO Limits on both AMD Overclocking and AMD CBS to values from @Veii (175/65/400), even removing all the ticks doesn't usually recover Write bandwidth:








Finally, the only BIOS setting I found affecting Write bandwidth is disabling AMD Cool-n-Quiet (this screen with Veii's limits):







Unfortunately it consistently drops the result.


I think I need to try my luck fiddling with Curve Optimizer.


----------



## Danny.ns

The following is, I think, the best I can do with my DR B-die and 5900x. Some notes:

Vdimm is 1.51V (1.505 will show errors at around ~100% HCI).
CPU cannot POST 1900fclk, >1900 POSTs fine but WHEAs when gaming.
1T is very unstable. I can get it somewhat stable with setup timings but performance suffers.
tRCDRD at 14 is very tough. I tried with 1.55V and "auto" secondary and tertiary timings but it still errored. I dont think I want more than 1.55V daily.
Some might comment on "high" CLDO VDDP - its not required, it's just what my Dark Hero defaults to at 3733mhz. Its stable with 0.95V as well..
tCWL 12 doesnt POST.
I'm not certain about ProcODT, RTTs and DrvStr..

Any comments? Anything I should change/try?


----------



## Kildar

Kildar said:


> Golden 5900x, B-Die ram and a Good MB!


Spoke too soon... crashed while gaming today...Complete black screen and restart.


----------



## boldenc

is this error related to ram ? I see the test is running but no errors are recorded but it will pop up those windows


----------



## TimeDrapery

Spoiler






XPEHOPE3 said:


> If anyone wondered what this value is in AMD Monitor (SVI2 SOC Set Volt):
> View attachment 2520389
> 
> It's exactly equal to SOC OVERCLOCK VID Voltage:
> View attachment 2520392
> 
> View attachment 2520393
> 
> 
> 43 hex = 67 dec, 1.55-67*0.00625=1.13125.
> SOC OVERCLOCK VID by default is 0 and it translates to SVI2 SOC Set Volt of 1.2. So that 0 is actually 56 in dec (38 in hex)
> 
> However, I don't know what this setting is about






@XPEHOPE3,

If you don't set an override for SOC voltage then you can use this option to select the SOC VID used

For example, I'm running 1.175V so I enter 1181mV in the AMD Overclocking menu and leave that XFR Enhancement menu completely alone because... Why do hexadecimal when I don't have to? If you enter the BIOS after inputting a SOC VID in the AMD Overclocking menu and then you check the XFR Enhancement menu after saving and exiting (and reentering) the BIOS you'll see that the hexadecimal value for the mV SOC VID you set is entered in that field (it "translates" it for you)


----------



## boldenc

So guys I need help, I can't pass TM5 without this Thread Error Handlers pop up, I even tried everything on stock and still show up.


----------



## reddify

boldenc said:


> So guys I need help


Post ZenTimings. Anyway it looks like too high FCLK to me.


----------



## boldenc

reddify said:


> Post ZenTimings. Anyway it looks like too high FCLK to me.


It will do the same with any FCLK even on stock, everything on Auto.
it looks CPU gone bad ?


----------



## Mach3.2

Are you overclocking your CPU?

Unstabe CPU OC can crash TM5 threads. You need to make sure your CPU OC is stable before you start to OC your RAM.


----------



## Akex

XPEHOPE3 said:


> If anyone wondered what this value is in AMD Monitor (SVI2 SOC Set Volt):
> View attachment 2520389
> 
> It's exactly equal to SOC OVERCLOCK VID Voltage:
> View attachment 2520392
> 
> View attachment 2520393
> 
> 
> 43 hex = 67 dec, 1.55-67*0.00625=1.13125.
> SOC OVERCLOCK VID by default is 0 and it translates to SVI2 SOC Set Volt of 1.2. So that 0 is actually 56 in dec (38 in hex)
> 
> However, I don't know what this setting is about


It is for strength the P0 of the SoC


----------



## XPEHOPE3

TimeDrapery said:


> I'm running 1.175V so I enter 1181mV in the AMD Overclocking menu


Why do you want to set something there in the first place?


----------



## Henry Owens

Kildar said:


> Golden 5900x, B-Die ram and a Good MB!


What dram voltage? Makes me wish I went with higher quality ram. Also I returned my 5800 that could do 2000flk and boot higher before I really knew what I had for a 5900 that can only do 1900. Could be worse.


----------



## Kildar

Henry Owens said:


> What dram voltage? Makes me wish I went with higher quality ram. Also I returned my 5800 that could do 2000flk and boot higher before I really knew what I had for a 5900 that can only do 1900. Could be worse.


1.5v on the dram, but the system crashed to a black screen and rebooted on me so it seems it's not stable.
Got to fine-tune it a little more


----------



## Henry Owens

Kildar said:


> 1.5v on the dram, but the system crashed to a black screen and rebooted on me so it seems it's not stable.
> Got to fine-tune it a little more


Haha damn, memory can take so long.. could be one of 30 things haha. How is your 5900 overclocked?


----------



## Kildar

Henry Owens said:


> Haha damn, memory can take so long.. could be one of 30 things haha. How is your 5900 overclocked?


PBO


----------



## Henry Owens

Kildar said:


> PBO


Mine is pbo -30 all core +200 stable 
Cinebench score?


----------



## seamonkeyhd

Hi everyone!

I picked up these XPG Spectrix D41 kits and I wanted to know if they are Micron Rev E. Here is the Thaiphoon Report.
Here are the primary timings I found on the kit: 3200MHz CL16-20-20 @ 1.35v
Part Number: AX4U32008G16A-ST41
Another thing, *what is a safe daily DRAM voltage I can run this kit on?*
Thanks in advance!


----------



## boldenc

Mach3.2 said:


> Are you overclocking your CPU?
> 
> Unstabe CPU OC can crash TM5 threads. You need to make sure your CPU OC is stable before you start to OC your RAM.


it is getting weird,
2x 5900x and 1x 3900x throwing threads errors on stock settings.
Memtest, HCI are stable.
What could be the reason now ?


----------



## boldenc

this is with the 3900x, always will happen once the cycle 5 starts
the 2x 5900x can't pass one cycle.
Those are all default settings, no PBO.
tried with XMP and default ram @ 2133 - same.
This sticks going bad? They still pass all other memtest, they are old sticks and were always stable, I can't remember I tried TM5 before with them or not.
But no other app showed instability issue.
Btw TM5 still continue the test and say no errors, could it be Windows issue ?


----------



## reddify

boldenc said:


> this is with the 3900x, always will happen once the cycle 5 starts
> the 2x 5900x can't pass one cycle.
> Those are all default settings, no PBO.
> tried with XMP and default ram @ 2133 - same.
> This sticks going bad? They still pass all other memtest, they are old sticks and were always stable, I can't remember I tried TM5 before with them or not.
> But no other app showed instability issue.
> Btw TM5 still continue the test and say no errors, could it be Windows issue ?
> 
> View attachment 2520455



"_If you experience issues with all threads crashing upon launch with the extreme config it might help to edit the row "Testing Window Size (Mb)=1408". Replace the window size with your total RAM (minus some margin for Windows) divided by your processors available threads (e.g. 12800/16 = 800 MB per thread)_."
Source: MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper · GitHub


----------



## Taraquin

Any suggestions on what to tweak? Are ProcODT, RTTs, etc okay with each other? Voltages are configured manually, testmem 5 usmus is stable, I run ProcODT etc on auto, but there might be possible to improve them. Voltages are I finally changed my 3060ti to another one with 3 fans so now I can set voltage a bit higher without overheating. My last 3060ti blew hot air straight at my ram which made it dislike voltages above 1.45V. Getting 60k, 32k, 55k and 52.4ns in aida with +200 PBO and -30 CO.


----------



## boldenc

reddify said:


> "_If you experience issues with all threads crashing upon launch with the extreme config it might help to edit the row "Testing Window Size (Mb)=1408". Replace the window size with your total RAM (minus some margin for Windows) divided by your processors available threads (e.g. 12800/16 = 800 MB per thread)_."
> Source: MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper · GitHub


Sometimes, instant crash on launch, sometimes after some cycles.
It happens even with Serj default profile.


----------



## boldenc

So far what I noticed.
No threads error if I keep the max ram usage for test under 87%
Once I used more ram for test, once it passes the 87% it will throw the threads errors.
Does it look the memory is going bad ?


----------



## Spectre73

Is anyone able to provide a stable B-die config for 3600 MHz MEMCLK? I am getting WHEA errors at 3800 MEMCLK on my Aorus master (never had that problem on unify-x). Something workable - prefareably with RAM voltage not going above 1,45 - the lower the better.


----------



## TimeDrapery

XPEHOPE3 said:


> Why do you want to set something there in the first place?


That's a good question ... I like it better than an offset/override of SOC voltage because it's fancy (truly I don't have a better reason, it doesn't seem like it works all that much differently considering results are identical)

_IF, and only if,_ DF C-States functioned properly I'd see myself using it in the same way I use the AMD Overclocking's "Manual OC" menu to set SOC voltage so that it would request that VID during the time it occupied P0 and then would idle down during occupation of lesser power states as setting an override would kill power management and an offset would apply during all power states, not just P0


----------



## TimeDrapery

boldenc said:


> So far what I noticed.
> No threads error if I keep the max ram usage for test under 87%
> Once I used more ram for test, once it passes the 87% it will throw the threads errors.
> Does it look the memory is going bad ?


Considering all the changes you've made hardware-wise with the issue persisting I'd reinstall Windows (wipe the drives) and download TM5 again before continuing

It's silly to troubleshoot further until you're at a known good point


----------



## XPEHOPE3

Spectre73 said:


> Is anyone able to provide a stable B-die config for 3600 MHz MEMCLK? I am getting WHEA errors at 3800 MEMCLK on my Aorus master (never had that problem on unify-x). Something workable - prefareably with RAM voltage not going above 1,45 - the lower the better.











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


I have problems with some sort of intermittent errors when trying to pass tm5. Seems stable at first, but then it's always 1-3 errors pop-up at the end, ~18,19,20 iteration cycle. This is how it passed the last 5 tries over last night, one by one: 1) tm5 thread crash after ~10 iter, state 8 2)...




www.overclock.net


----------



## boldenc

TimeDrapery said:


> Considering all the changes you've made hardware-wise with the issue persisting I'd reinstall Windows (wipe the drives) and download TM5 again before continuing
> 
> It's silly to troubleshoot further until you're at a known good point


Finally it was windows problem, new windows and no more thread errors.
The test has been running for 4 hours now and no errors.


----------



## TimeDrapery

boldenc said:


> Finally it was windows problem, new windows and no more thread errors.
> The test has been running for 4 hours now and no errors.


@boldenc 

Nice!


----------



## Spectre73

XPEHOPE3 said:


> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> I have problems with some sort of intermittent errors when trying to pass tm5. Seems stable at first, but then it's always 1-3 errors pop-up at the end, ~18,19,20 iteration cycle. This is how it passed the last 5 tries over last night, one by one: 1) tm5 thread crash after ~10 iter, state 8 2)...
> 
> 
> 
> 
> www.overclock.net


Sorry to say this, but these are not good timings. Only your primaries are good, but that does not amount to a good performance. For starters, your tRFC is way to high. There are many other bad settings.
Take a look at these here. That was my go to for 3800 MHz RAM, sadly, on my Aorus Master, I get WHEA errors, so I decided to move down a few FCLK steps. But this will be my starting point for 3600 I just do not know which timings I can improve upon and which ones have to stay the same.


----------



## Netarangi

Recommendations for timings? Struggling to get 1T GDM off with CL14 3800.

What else can I improve?


----------



## deadfelllow

Hey guys, I have a Crucial Ballistix RGB 3600 mhz cl 16. Default XMP 16-18-18-36

I tested 3 hours of TM5 with 1usmus config and its %100 stable(I ASSUME). What can i do more?

Any ideas Thanks.

PS : Cant lower the tRC below 52 instant error
Cant lower tRFC instant error. Below 535 blue screens.
when i try to change tWR 16 to 12 it gives errors.
Tried tRP 12 tRAS 21 gave me error as well after 40 minutes.
Cant lower TCWL its not posting at 13.
also tRTP and tRDWR.

Tried cl 13 at 1.65 volts gave me error after 15 minutes.
Ik that Micron E dies are not voltage sensitive and also CL value is scaling via voltage. But gave me error cl13 @ 1.65 v

Current Values = VDIMM : 1.52 V - Soc = 1.05 , IOD = 1

Any further ideas?

Thanks.


----------



## XPEHOPE3

Spectre73 said:


> Sorry to say this, but these are not good timings. Only your primaries are good, but that does not amount to a good performance. For starters, your tRFC is way to high. There are many other bad settings.


I know, but that answers your request as stated  (as you didn't ask for tight timings). tRFC for my kit is near 202ns, but I have 4 DRs and you have 4 SRs, so my settings _might not_ transfer easily. However if you are interested, you can grab my stable secondaries and tertiaries from my 3866-16 setup here (or any other suitable entry). Beware that tWRRD and tRDWR from DR would _definitely_ be suboptimal for SR.


----------



## spajdr

@deadfelllow what number of error you get?


----------



## Lobstar

So I cavemanned in the 1usmus B-Die RAM timings and it works surprisingly well on my system. What's the best resource out there for learning how to get this tighter? I'm on Patriot ViperSteel 4400CL19.


----------



## deadfelllow

spajdr said:


> @deadfelllow what number of error you get?


6 and 8 i guess.


----------



## Sleepycat

Spectre73 said:


> Sorry to say this, but these are not good timings. Only your primaries are good, but that does not amount to a good performance. For starters, your tRFC is way to high. There are many other bad settings.
> Take a look at these here. That was my go to for 3800 MHz RAM, sadly, on my Aorus Master, I get WHEA errors, so I decided to move down a few FCLK steps. But this will be my starting point for 3600 I just do not know which timings I can improve upon and which ones have to stay the same.
> View attachment 2520572


You can't compare your timings to his. He is running 4x16GB B-die. That is tough on the memory controller. He can tighten the subtimings more, but it is less straight forward with 64GB.


----------



## Sleepycat

Spectre73 said:


> Is anyone able to provide a stable B-die config for 3600 MHz MEMCLK? I am getting WHEA errors at 3800 MEMCLK on my Aorus master (never had that problem on unify-x). Something workable - prefareably with RAM voltage not going above 1,45 - the lower the better.


Can you show us your Zentimings screenshot? What VSoc are you running for 3800/1900?


----------



## PJVol

Netarangi said:


> Recommendations for timings? Struggling to get 1T GDM off with CL14 3800


I'd leave primaries @15 flat, and I dont think there's much left to improve considering Vdimm is 1.5V already (unless you step up with FCLK)
My 24/7 setup running [email protected] 1T at 1.44V fast and rock stable.


----------



## Spectre73

Sleepycat said:


> Can you show us your Zentimings screenshot? What VSoc are you running for 3800/1900?


This are my old 1900/3800 timings and voltages:








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Any suggestions on what to tweak? Are ProcODT, RTTs, etc okay with each other? Voltages are configured manually, testmem 5 usmus is stable, I run ProcODT etc on auto, but there might be possible to improve them. Voltages are I finally changed my 3060ti to another one with 3 fans so now I can set...




www.overclock.net





As I said, worked flawless on Unify-X but has trouble runnning WHEA free (WHEA 18) on Aorus x570 Master 1.0 - I really spend much time on this and I am ready to run more relaxed MEMCLK for hassle free operation, at this point. Maybe with a new board. (x570S). Not so sure though.


----------



## PJVol

Spectre73 said:


> has trouble runnning WHEA free (WHEA 18) on Aorus x570 Master 1.0


WHEA 18 means CPU error. Are you sure its 18, cause it should restart your PC? If so, check your CPU OC/tuning.


----------



## Sleepycat

Spectre73 said:


> This are my old 1900/3800 timings and voltages:
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Any suggestions on what to tweak? Are ProcODT, RTTs, etc okay with each other? Voltages are configured manually, testmem 5 usmus is stable, I run ProcODT etc on auto, but there might be possible to improve them. Voltages are I finally changed my 3060ti to another one with 3 fans so now I can set...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> As I said, worked flawless on Unify-X but has trouble runnning WHEA free (WHEA 18) on Aorus x570 Master 1.0 - I really spend much time on this and I am ready to run more relaxed MEMCLK for hassle free operation, at this point. Maybe with a new board. (x570S). Not so sure though.


The only time I had WHEA's it was due to my CPU vcore being too low for certain cores in my CCD1. So if you are using curve optimizer, I would recommend increasing the offset for each core by +10, to see if it reduces WHEA. If you are not running curve optimizer, then I recommend turning it on to give a +10 offset. 

With regards to memory clocks, I only messed around with 32GB for a short while as I currently run 64GB. If you want to see my settings, I have unoptimized rough settings for 3867/1933 back from when I was just messing around.


----------



## Netarangi

PJVol said:


> I'd leave primaries @15 flat, and I dont think there's much left to improve considering Vdimm is 1.5V already (unless you step up with FCLK)
> My 24/7 setup running [email protected] 1T at 1.44V fast and rock stable.


OH I definitely don't need 1.5. I can run this at 1.45 I accidentally booted it with 1.5 from a 1t attempt. 

With this in mind, what can I work on? Trfc trtp?


----------



## mongoled

PJVol said:


> @mongoled
> I asked my older brother, who's in electronics mostly, about those broken elements on photo, and he told me they are capacitors.


All due respect to your brothers work, but I dont think they are capacitors.

Waiting for the Viper Steel 4400mhz to come back in stock @Amazon.de, a little concerned that the price for these modules keeps dropping, wondering if whatever is left is what people are returning after binning them and the available stock is just the same stock going round and round ....

Can someone who is running 2 x 8GB b-die with tight timings @ 3800mhz post your TM5 25 cycle run so I can compare the time it takes.

Im pulling times that I believe to be rediculously fast and am unsure as to the reasons, my only guess its because the dimms are running cooler because they are now water cooled.

Unfortunately I dont have any 16GB runs to compare to on my 5600x ..

Here is what I did yesterday, this is with background tasks running, streaming music, while using the computer etc etc


----------



## PJVol

Netarangi said:


> With this in mind, what can I work on? Trfc trtp?


ProcODT 32-34, tRFC 270-280 (calculate the exact value based on trp and trc, for example trc 44, trtp 6 and trfc 44*6 = 264, rdwr 9), but tbh, I don't get what are you gonna achieve with this 2T, since [email protected] CR1 should be faster anyway.


----------



## Taraquin

Lobstar said:


> So I cavemanned in the 1usmus B-Die RAM timings and it works surprisingly well on my system. What's the best resource out there for learning how to get this tighter? I'm on Patriot ViperSteel 4400CL19.
> View attachment 2520614


What voltage are you running? I got the same, but a ****ty bin. If your bin is okay you can try 2t, gdm off, cl, trcd and trp 15, tras 30, trc 45, trfc 270, trtp 6. I can run that at 1.46V at 3800, but my bin is poor.


Lobstar said:


> So I cavemanned in the 1usmus B-Die RAM timings and it works surprisingly well on my system. What's the best resource out there for learning how to get this tighter? I'm on Patriot ViperSteel 4400CL19.
> View attachment 2520614


If volt is at 1.45V, try 2t, gdm off, tcl/trcd/trp 15, tras 30, trc 45, trfc 270, trtp 6. My ****ty bin can do that at 1.46V at 3800.


----------



## PJVol

mongoled said:


> All due respect to your brothers work, but I dont think they are capacitors.


Looking again at the photo, it seems you're right, and they are resistors indeed. My brother just told me that "capacitors are yellow and resistors are black" 
These can be VTT termination or pull-down resistors (there's no decoupling ones). Decoupling capacitors are really bigger, on the photo with a-cool heatspreader on pcb.


mongoled said:


> Can someone who is running 2 x 8GB b-die with tight timings @ 3800mhz post your TM5 25 cycle run so I can compare the time it takes


If you had screens from 3 tm5 cycles, we could compare them too, at least I have a lot of them


----------



## Niki_i

Dear experts!
I'm using 5950x with Asus b550-xe gaming (agesa 1.2.0.3 patch A) and Crucial ballistix 2x32gb 3600, video card (while expecting normal prices) old gts 450.

On 3733/1866 all stress tests are passed stable, on 3800/1900 it seems like "IF hole" and pc doesn't post under any settings, 3866/1933 and 4000/2000 posts, but on 4000/2000 WHEA immediately appear after entering windows (WHEA 19 -bus / interconnection error) 100 per minute.
At 3866/1933, it is significantly better, WHEA in stress tests, with daily pc use 1-2 per day. But this can be achieved only by setting CPU 1.8v voltage to 1.94v, anything higher or lower gives more WHEA.
There are no memory errors itself, Testmem extreme1 @ anta777 and OCCT on 3866/1933 [email protected] passes without memory errors, but with WHEA.
I tried all possible combinations of voltages, nothing helps to get rid of WHEA 19-bus / interconnection error.
Now I'm using it on 3866/1933:

CPU 1.8v voltage 1.94v
SOC 1.1v
IOD 1.02v
CCD 0.94v
CLDO VDDP 0.9v
Vdimm 1.39v
Using CPU with pbo+curve optimizer CPU passed all stress-tests rock stable, without pbo there's no difference at all.
With such voltages i get the smallest ammount of WHEA.
There was a thought, is it possible that the main reason for WHEA is the video card? It works on pci-e 2.0, sometimes whistling-hissing sounds jump from it (as I understand it, this is a sign of its unstable work or pci-e) and sometimes when the PC starts before the bios appears, a message is displayed that the pci-e device is not recognized, but the pc starts up.
Is it possible that replacing the video card (planning for 3060 or 3070) will help to get rid of WHEA? Or i'm "lucky" with the processor or motherboard?


----------



## mongoled

PJVol said:


> Looking again at the photo, it seems you're right, and they are resistors indeed. My brother just told me that "capacitors are yellow and resistors are black"
> These can be VTT termination or pull-down resistors (there's no decoupling ones). Decoupling capacitors are really bigger, on the photo with a-cool heatspreader on pcb.
> 
> If you had screens from 3 tm5 cycles, we could compare them too, at least I have a lot of them


Im pretty sure that the RAM should function without those but im not wanting to pull them off one of the sticks to test, will probably eventually do it

😄😄

Im wondering if somehow the SPD got corrupt, as the system does attempt to cycle once the power button is pressed and gets through a couple of LED diagnostic codes then reverts to beep beep beep ...

Ahhh, but the times is not consistent between runs and gets slower on each iteration, hopefully someone else will be able to provide a screenshot of tight b-die, 3800 mhz and 5600x.

Just playing around with 1T, cant get both dimms down to tPHYRDL @26, A2 is on 28, while B2 is on 26, this is using straights 14s.

Also a couple of anomalies, on previous test 1T 0-0-0 was significantly slower at TM5 around 5-7 minutes compared to 1T 56-0-0, re-running the test again to see if the time is the same.

And if I try to use 3-3-15 with 1T this results in almost instant bluescreens once in Windows desktop where as 0-0-0 is perfectly fine.....


----------



## PJVol

Niki_i said:


> Or i'm "lucky" with the processor or motherboard?


You're as "lucky" as 99% of 5000 cpu owners here , except those having 2-ccd 5600's.

@mongoled
Just launched 25-laps marathon.


----------



## mongoled

PJVol said:


> You're as "lucky" as 99% of 5000 cpu owners here , except those having 2-ccd 5600's.
> 
> @mongoled
> Just launched 25-laps marathon.


Cheers bud



Sure takes less time then testing 32GB

😄😄


----------



## mongoled

Niki_i said:


> Dear experts!
> I'm using 5950x with Asus b550-xe gaming (agesa 1.2.0.3 patch A) and Crucial ballistix 2x32gb 3600, video card (while expecting normal prices) old gts 450.
> 
> On 3733/1866 all stress tests are passed stable, on 3800/1900 it seems like "IF hole" and pc doesn't post under any settings, 3866/1933 and 4000/2000 posts, but on 4000/2000 WHEA immediately appear after entering windows (WHEA 19 -bus / interconnection error) 100 per minute.
> At 3866/1933, it is significantly better, WHEA in stress tests, with daily pc use 1-2 per day. But this can be achieved only by setting CPU 1.8v voltage to 1.94v, anything higher or lower gives more WHEA.
> There are no memory errors itself, Testmem extreme1 @ anta777 and OCCT on 3866/1933 [email protected] passes without memory errors, but with WHEA.
> I tried all possible combinations of voltages, nothing helps to get rid of WHEA 19-bus / interconnection error.
> Now I'm using it on 3866/1933:
> 
> CPU 1.8v voltage 1.94v
> SOC 1.1v
> IOD 1.02v
> CCD 0.94v
> CLDO VDDP 0.9v
> Vdimm 1.39v
> Using CPU with pbo+curve optimizer CPU passed all stress-tests rock stable, without pbo there's no difference at all.
> With such voltages i get the smallest ammount of WHEA.
> There was a thought, is it possible that the main reason for WHEA is the video card? It works on pci-e 2.0, sometimes whistling-hissing sounds jump from it (as I understand it, this is a sign of its unstable work or pci-e) and sometimes when the PC starts before the bios appears, a message is displayed that the pci-e device is not recognized, but the pc starts up.
> Is it possible that replacing the video card (planning for 3060 or 3070) will help to get rid of WHEA? Or i'm "lucky" with the processor or motherboard?


Anything that passes data over the PCIe bus can trigger WHEA 19s, so yeah could be your gfx card, but its most likely either CPU/motheboard combo, dont waste your time with it unless you enjoy tweaking to hell with the prospect of gaining "nothing"


----------



## Ishanji

Danny.ns said:


> The following is, I think, the best I can do with my DR B-die and 5900x. Some notes:
> 
> Vdimm is 1.51V (1.505 will show errors at around ~100% HCI).
> CPU cannot POST 1900fclk, >1900 POSTs fine but WHEAs when gaming.
> 1T is very unstable. I can get it somewhat stable with setup timings but performance suffers.
> tRCDRD at 14 is very tough. I tried with 1.55V and "auto" secondary and tertiary timings but it still errored. I dont think I want more than 1.55V daily.
> Some might comment on "high" CLDO VDDP - its not required, it's just what my Dark Hero defaults to at 3733mhz. Its stable with 0.95V as well..
> tCWL 12 doesnt POST.
> I'm not certain about ProcODT, RTTs and DrvStr..
> 
> Any comments? Anything I should change/try?
> 
> View attachment 2520404


Hey, i have the same exact set of sticks so 1T actually is a struggle to get stable. 
I have a somewhat stable flat15 T1 Profile without setup timings but it errores on cycle 14 tm5 with 1usmus config. I had a stable one with 56-56-56 Setup timings but i lost it in a full bios reset -.- didn't hassle to get it back, wanted to go straight for a pure 1T profile.... getting it stable gives me headaches^^
But i have flat14 T2 profile @ 1.55 which is stable and is almost equall in bandwidth performance then the 1T Profile @ same latency an still has some room for improvements.
Dimm temperature is not right in the screen, they peaked at 46.0°C under air.
To get them stable i needed 120Ohms on ClkDrvStr so you might wanna give it a try.


----------



## Spectre73

PJVol said:


> WHEA 18 means CPU error. Are you sure its 18, cause it should restart your PC? If so, check your CPU OC/tuning.


I am not sure. I am at work right now. It is definitely a cache/interconnect error, if that is a whea 19, than I was mistaken.


----------



## Netarangi

PJVol said:


> I'd leave primaries @15 flat, and I dont think there's much left to improve considering Vdimm is 1.5V already (unless you step up with FCLK)
> My 24/7 setup running [email protected] 1T at 1.44V fast and rock stable.


OH I definitely don't need 1.5. I can run this at 1.45 I accidentally booted it with 1.5 from a 1t attempt. 

With this in mind, what can I work on? Trfc trtp?


----------



## Niki_i

PJVol, mongoled Thanks for reply!


----------



## XPEHOPE3

Sleepycat said:


> If you want to see my settings, I have unoptimized rough settings for 3867/1933 back from when I was just messing around.
> View attachment 2520669


How did you get tRFC that low? My 4*16 start erring at 198 ns already


----------



## Sleepycat

XPEHOPE3 said:


> How did you get tRFC that low? My 4*16 start erring at 198 ns already


Those settings are just for 2x16GB though, it's much tougher using 4x16GB. With 4 sticks, I can only get it to POST and run stably at 3600.

I just created an initial starting point with the DRAM calculator, and then started working downwards for all settings while testing stability. I think I rebooted my PC about 500 times in a span of 4 weeks.

If you want to see my 4x16GB settings which I run now, WHEA-free and passes TM5 and OCCT Large Extreme, here they are. It also runs fine in 1T with GDM on. Hopefully it will help you with your settings. My kits are 2 packs of F4-3200C14D-32GTSK.


----------



## XPEHOPE3

Sleepycat said:


> My kits are 2 packs of F4-3200C14D-32GTSK.


I have 1 pack of F4-3200C14-64 something. Did you try my settings of 3866-16?


----------



## PJVol

@Netarangi
You seem to miss my post, 3h ago.


----------



## PJVol

mongoled said:


> Sure takes less time then testing 32GB


You know what? 
When I got back to PC, monitor was in standby, and guess what I've seen on the desktop when I hit "space" ???
Right, Nothing )))
It seems tm5 window was left focused, and handled kb event that somehow passed through logon app (there wasn't "Enter" button on it).

Anyways, I can tell you, tm5 cycles stopped slowing down somewhere between 12 and 15 pass. After that I measured an average cycle time to be 206-208 seconds. Last cycle I've seen was 19, so basic math gives 25 * 207= 1h 26m 15s. I'm pretty sure, that is very close to actual time elapsed.

Nice experience, btw. Never ran it so long, and it suddenly turned out, my RAM sticks can't handle such marathon without additional cooling, so 1st try failed with errors (almost random) started to pop up somewhere at the 6th or 7th cycle. 
So I quickly mounted old sillverston case fan in front of DIMMs and the 2nd try was successful (aside from not having any result, lol)
My closed case with all parts watercooled had almost no airflow where the ram slot are.


----------



## Audioboxer

About to buy some new memory, between

F4-3600C14D-32GVKA
CL14-14-14-34 1.45V

and

F4-4000C16D-32GVKA
CL16-16-16-36 1.40V

I've seen some 4000C16 sets manage 3800 CL14, but often tRCDRD is stubborn and sits on 15. I know lower binned voltage is usually king, but would the C14 set possibly have a better chance of doing 3800 14-14-14?

It's the slightly more expensive of the two. But I'd rather not spend the money if the 4000 set is better and/or the chances of both are quite the same for 3800 CL14 being stable.


----------



## mongoled

PJVol said:


> You know what?
> When I got back to PC, monitor was in standby, and guess what I've seen on the desktop when I pressed keyboard space ???
> Right, Nothing )))
> It seems tm5 window was left focused, and handled kb event that somehow passed through logon app.
> Nice experience, btw. Anyways, I can tell you, tm5 cycles stopped slowing down somewhere between 12 and 15 pass. After that I measured an average cycle time to be 206-208 seconds. Last cycle I've seen was 19, so basic math gives 25 * 207= 1h 26m 15s. I'm pretty sure, that is very close to actual time elapsed.


Same thing just happened to me, was cursing like a fool as on the bench OS there is no password required and yup, pressed spacebar and it closed it

😄😄😄

Thats where I would expect it to be, between 1h 23m - 1h 26m.

Looks like the cooler temperature is helping or something is amiss ...


----------



## domdtxdissar

mongoled said:


> All due respect to your brothers work, but I dont think they are capacitors.
> 
> Waiting for the Viper Steel 4400mhz to come back in stock @Amazon.de, a little concerned that the price for these modules keeps dropping, wondering if whatever is left is what people are returning after binning them and the available stock is just the same stock going round and round ....
> 
> Can someone who is running 2 x 8GB b-die with tight timings @ 3800mhz post your TM5 25 cycle run so I can compare the time it takes.
> 
> Im pulling times that I believe to be rediculously fast and am unsure as to the reasons, my only guess its because the dimms are running cooler because they are now water cooled.
> 
> Unfortunately I dont have any 16GB runs to compare to on my 5600x ..
> 
> Here is what I did yesterday, this is with background tasks running, streaming music, while using the computer etc etc
> 
> View attachment 2520680


TestMEM5 cant be used as a performance "benchmark".. The more apps/programs you have open the more memory you use -> less for TestMem to stresstest --> Faster runtime if you use the computer at the same time. 
I think i already said many months ago that testmem cant be used as a performance index/benchmark..


----------



## XPEHOPE3

PJVol said:


> When I got back to PC, monitor was in standby, and guess what I've seen on the desktop when I hit "space" ???
> Right, Nothing )))
> It seems tm5 window was left focused, and handled kb event that somehow passed through logon app (there wasn't "Enter" button on it).


BTW with my automation script you won't lose your results in such a case


----------



## mongoled

domdtxdissar said:


> TestMEM5 cant be used as a performance "benchmark".. The more apps/programs you have open the more memory you use -> less for TestMem to stresstest --> Faster runtime if you use the computer at the same time.
> I think i already said many months ago that testmem cant be used as a performance index/benchmark..


What you have said is valid, however as I always use TM5 in the same way results should be comparative to previous results and they are not, thats the "issue" and its not just a one off run I am seeing this, its across many different runs, same OS usage, i.e. couple of tabs open in Edge, music playing through Edge with HWInfo6, ZenTimings & TM5 running ...

** EDIT **
Good observation, BenchOS takes longer to complete then my WorkOS, WorkOS obviously has more resources taking up RAM, however still unsure if thats the reason behind the difference in times as we are not talking about a couple of minutes here and there.

Going to have to do the exact same run that I posted earlier but in the BenchOS to get a like for like comparison with the only thing being different is the OS and resources its taking ....


----------



## PJVol

mongoled said:


> Looks like the cooler temperature is helping or something is amiss ...


Idk, if it was the reason the tm5 ran faster in your case, but at current ambient temps, there's no way mine would have passed 25 cycles error free, if I didn't provide some direct airflow.


----------



## XPEHOPE3

PJVol said:


> Never ran it so long, and it suddenly turned out, my RAM sticks can't handle such marathon without additional cooling, so 1st try failed with errors (almost random) started to pop up somewhere at the 6th or 7th cycle.


Guess all your entries need to be removed then?)))


----------



## XPEHOPE3

mongoled said:


> Can someone who is running 2 x 8GB b-die with tight timings @ 3800mhz post your TM5 25 cycle run so I can compare the time it takes.
> 
> Im pulling times that I believe to be rediculously fast and am unsure as to the reasons


Can you please monitor when TM5 does free memory? Normally it frees memory only after test #15. Sometimes it frees some memory during end of test #11. Any other memory freeing meant for me a dead thread (but then it won't run up to 25-th cycle).
Also you allocate just 864*12 MB = 10368 MB. Are you sure you were allocating as little on previous (slower) runs?


----------



## PJVol

XPEHOPE3 said:


> Guess all your entries need to be removed then?)))


 I honestly attached there screens of as many as 3 cycles of tm5 passed ))

On a serious note, for me personally, these 25 tm5 cycles are kinda similar to testing all cores with corecycler script using workloads, that average user hardly would ever encounter in a daily usage, if at all, but thats again, a matter of taste.
It's the question of what degree of stability you trying to achieve, 99,99% or 99,99999999%...


----------



## MrHoof

well for somone who claimed rock stable. I would have guessed u could pass more then 6 cycles without errors at 1.44v u should not need airflow.


----------



## PJVol

MrHoof said:


> well for somone who claimed rock stable. I would have guessed u could pass more then 6 cycles without errors at 1.44v u should not need airflow


The dimms starts heating somewhere at the 7th pass, on top of that I didn't restore my 24/7 case fan settings after clearing BIOS and most of the case fans were running as set in "silent" profile, so the case airflow was minimal.
And, btw, "rock stable" doesn't necessarily mean you can put your PC in the oven and pass all tests with the same settings. And why the hell shouldn't I need airflow, let me ask?


----------



## mongoled

XPEHOPE3 said:


> Can you please monitor when TM5 does free memory? Normally it frees memory only after test #15. Sometimes it frees some memory during end of test #11. Any other memory freeing meant for me a dead thread (but then it won't run up to 25-th cycle).
> Also you allocate just 864*12 MB = 10368 MB. Are you sure you were allocating as little on previous (slower) runs?


Unsure how to check this as task manager does not show TM5 memory allocation.

Looking at HWInfo64 the "Physical Memory Used" is always around 15xxx, have never seen it drop below this but obviously I had not been watching it, just taking note of it now that you have asked.

Was on cycle 14 and now its on cycle 18, didnt see any drop ...


----------



## MrHoof

PJVol said:


> I have. The dimms starts heating somewhere at the 7th pass, on top of that I didn't restore my 24/7 case fan settings after clearing BIOS and most of the case fans were running as set in "silent" profile, so the case airflow was minimal.


OR it might be a lack of voltage when the heat increases. To actuly pass more then 15 cycles i had to to go from 1.49v to 1.51. Could it be that b-die needs higher voltage to stay stable at higher temps? my max temp is 56/58.5°C on the dimms.


----------



## PJVol

mongoled said:


> Unsure how to check this as task manager does not show TM5 memory allocation.


The tm5 itself shows?
It deallocates memory somewhere after #11 (#15 is just too short) and start allocating again at #6. When all is closed, mine shows 1,1x12Gb and ~450-500Mb available while the cycle is running.


----------



## XPEHOPE3

mongoled said:


> Looking at HWInfo64 the "Physical Memory Used"


I've just set up an audio alert in HWiNFO64 on Physical Memory Available to be above 1000MB. So if I'm near tested PC I never miss when TM5 deallocates.
But yes, of course TM5 itself shows available memory (13378 MB on your screen).


----------



## PJVol

Here we go 
In the background are Firefox with 10 tabs open, EPIC launcher, WWZ game, CB R23 , etc...








Normally it takes 3m 10-15s in my system for the first cycle.


----------



## Veii

To trow something in this discussion
Honestly i think the PC has to be able to run in an oven scenario
90-92c with y-cruncher on high core count units
It has to be able to sustain stability and throttle itself , without crashing on said voltages

;Mosfets change ripple by heat soo also loadline changes
So also procODT behavior changes on a hot infinity fabric and the signal to the dimms can get to noisy. Hence the increase of VDIMM.
But the same can be said for the dimms itself, where heat increases resistance and cold/frost decreases but increases voltage efficiency = less required

TM5 20+ cycles, aside from giving it the ability to test tREFI errors too
Is something i set as stability range, upon error observation.
1usmus_v3 is quite efficient, but thermal equilibrium still plays a role in it.
Soo like anta's test , 1usmus_v3 20 cycles is the absolute minimum to set it ~ resulting in about equal the strain and equal in testing delay

Also to figure out tRFC and tREFI mistakes or other rounding mistakes
I personally prefer 25 cycles,, but zip files are not uploadable. Soo 20+ for good old sake it is 

Thermal equilibrium part:
45min minimum, on either CPU based or memory based test ~ in order to 100% reach thermal equilibrium

EDIT:
I still do run my 1.65v , and don't have focused direct airflow on the dimms
Just slightly to the side angled
And it's still every day 28-30c outside and nearly also inside.
It's no excuse 😇
You daily the voltage you can afford to daily (thanks to RTTs)
If you have stability issues, increase your timings ~ starting with higher RTTs
Competitiveness here and there, daily stability remains a key of this thread here & my only target point. I don't practice XOC


----------



## PJVol

Veii said:


> Soo 20+ for good old sake it is


Ok, boss. Changing config to 20 cycles. 25 is so loooong, aside from watching for monitor not going to sleep.


----------



## mongoled

PJVol said:


> Ok, boss. Changing config to 20 cycles. 25 is so loooong, aside from watching for monitor not going to sleep.


1 hr isnt long

😄 😄

Think of the guys with 64GB of RAM, now thats long


----------



## Sleepycat

XPEHOPE3 said:


> I have 1 pack of F4-3200C14-64 something. Did you try my settings of 3866-16?


I have had settings like yours, nothing will make mine boot at 3666 when I run 4 sticks. It is probably because my board is a X570. It's not that good for memory overclocking.


----------



## Bezcit

Veii said:


> You daily the voltage you can afford to daily (thanks to RTTs)
> If you have stability issues, increase your timings ~ starting with higher RTTs
> Competitiveness here and there, daily stability remains a key of this thread here & my only target point. I don't practice XOC


Hello, please, if you say "higher RTT", it means:
A) Increase RZQ/x values, like RZQ/6 to RZQ/7 and such
or
B) Increase the ohms itself, like 40ohm to 80ohm and such

Because I have a bit temperature problems with my Bdie dual rank (2x16) on UnifyX, the two DIMMs are very close to each other. 3800 CL14 flat, VDIMM 1.48V, 36.9 6/3/3, 40/20/30/20. It´s stable even 30 cycles of 1usmusV3, until a very hot summer day it throw an error, # says it ram overheating (usually hapens at 45-50°C DIMM range).


----------



## mongoled

Lets see how this holds out


----------



## Mach3.2

Sleepycat said:


> I have had settings like yours, nothing will make mine boot at 3666 when I run 4 sticks. It is probably because my board is a X570. It's not that good for memory overclocking.


It's probably your CPU's IMC tapping out, 2 DIMM Per Channel (DPC) strains the IMC more than 1DPC.


----------



## gled_fr

Audioboxer said:


> About to buy some new memory, between
> 
> F4-3600C14D-32GVKA
> CL14-14-14-34 1.45V
> 
> and
> 
> F4-4000C16D-32GVKA
> CL16-16-16-36 1.40V
> 
> I've seen some 4000C16 sets manage 3800 CL14, but often tRCDRD is stubborn and sits on 15. I know lower binned voltage is usually king, but would the C14 set possibly have a better chance of doing 3800 14-14-14?
> 
> It's the slightly more expensive of the two. But I'd rather not spend the money if the 4000 set is better and/or the chances of both are quite the same for 3800 CL14 being stable.


I have a F4-3600C14 ( granted I think it is a 14 15 15 35 ? ) and trcdrd at 14 / 3800 is proving to be... challenging.... still have not cracked it yet. it boots fine but can't stabilize fully.

I have put that in pause since I am getting the same performance with flat 15's and good subtimings at a lower vdimm.

Trying now to reach IF1900+ ( trying 1933 atm ), it boots fine too, but reducing the amounts of WHEA 19 is also proving to be difficult. No matter if I increase or decrease voltages it does not seem to make a difference...


----------



## Audioboxer

gled_fr said:


> I have a F4-3600C14 ( granted I think it is a 14 15 15 35 ? ) and trcdrd at 14 / 3800 is proving to be... challenging.... still have not cracked it yet. it boots fine but can't stabilize fully.
> 
> I have put that in pause since I am getting the same performance with flat 15's and good subtimings at a lower vdimm.
> 
> Trying now to reach IF1900+ ( trying 1933 atm ), it boots fine too, but reducing the amounts of WHEA 19 is also proving to be difficult. No matter if I increase or decrease voltages it does not seem to make a difference...


Yeah I think I might just save myself £30 and buy the F4-4000C16D-32GVKA set. I too get WHEA at 1933~2000, but I guess further bios updates might get more of us there eventually.

The F4-4000C14 sets might be prime for 3800 tRCDRD 14 but they cost a bomb. IIRC even the 3800C14 XMP set runs at like 14-16-16-36.

F4-3600C14 14-14-14-34 1.45v is a new bin from this year, but I'd guess some of the older F4-3600C14 14-15-15-35 1.45v sets can easily switch to that from XMP.


----------



## TimeDrapery

Spoiler






mongoled said:


> Lets see how this holds out
> 
> 
> 
> View attachment 2520722






@mongoled 

Sooooo... How long did it hold out, friend???


----------



## 1devomer

I rebuilt my custom AIO watercooling loop, lapping the AIO block in the process.
Both the cpu and the coldplate are lapped flat.

I then spent some time fiddling with the memory, before verifying the all-cores oc.
VSOC: 1.1v/1.05v
VDDG IO/CCD: Auto or 0.975v
VMEM: 1.5v
WHEA free.


----------



## mongoled

TimeDrapery said:


> @mongoled
> 
> Sooooo... How long did it hold out, friend???


Wont know until i go back to the office tomorrow

I was meant to put a password on the account but forgot to do it so I cant access the PC via RDP (im connecting through a VPN)

😂 😂

Oh well, hopefully its a nice suprise, quick test runs got to cycle 3 without an error


----------



## TimeDrapery

Spoiler






mongoled said:


> Wont know until i go back to the office tomorrow
> 
> I was meant to put a password on the account but forgot to do it so I cant access the PC via RDP (im connecting through a VPN)
> 
> 😂 😂
> 
> Oh well, hopefully its a nice suprise, quick test runs got to cycle 3 without an error






@mongoled 

😂😂😂😂😂, love that... Good the quick test sounds promising!


----------



## umea

ignore, phone glitched


----------



## umea

I've been trying to step up freq from [email protected] stable, GDM off 1T, but have been having a lot of trouble.
5900x, B550I Phantom ITX, F4-4266C17D-32GVKB
Another problem maybe is that it takes 40 minutes to finish the first cycle.

Anyone have experience with this kit or board?


----------



## TimeDrapery

Spoiler






umea said:


> I've been trying to step up freq from [email protected] stable, GDM off 1T, but have been having a lot of trouble.
> 5900x, B550I Phantom ITX, F4-4266C17D-32GVKB
> Another problem maybe is that it takes 40 minutes to finish the first cycle.
> 
> Anyone have experience with this kit or board?






@umea 

Hmmmmm... I'm sure it's not _the worst_ way to go about overclocking your memory but the way you are doing this is likely to be harder than it needs to be

The first thing I'd do is determine the frequencies I'm capable of running... Set VDIMM (and your other voltages [SOC, VDDG, etc.] too) as high as you're comfy with setting it, input some loose baseline timings, and start increasing the frequency until you're not able to get past POST

Once you're there, back the freq off a step and start tightening timings


----------



## Sleepycat

Mach3.2 said:


> It's probably your CPU's IMC tapping out, 2 DIMM Per Channel (DPC) strains the IMC more than 1DPC.


Yes, I agree. When I pull out 2 sticks, the thing just decides to fly.


----------



## Sleepycat

gled_fr said:


> I have a F4-3600C14 ( granted I think it is a 14 15 15 35 ? ) and trcdrd at 14 / 3800 is proving to be... challenging.... still have not cracked it yet. it boots fine but can't stabilize fully.
> 
> I have put that in pause since I am getting the same performance with flat 15's and good subtimings at a lower vdimm.
> 
> Trying now to reach IF1900+ ( trying 1933 atm ), it boots fine too, but reducing the amounts of WHEA 19 is also proving to be difficult. No matter if I increase or decrease voltages it does not seem to make a difference...


Even at 3600 CL14 (4-sticks), I need to set tRCDRD to 15 to pass stability. So in the end, I run CL14-8-15-14-28.


----------



## Sleepycat

umea said:


> I've been trying to step up freq from [email protected] stable, GDM off 1T, but have been having a lot of trouble.
> 5900x, B550I Phantom ITX, F4-4266C17D-32GVKB
> Another problem maybe is that it takes 40 minutes to finish the first cycle.
> 
> Anyone have experience with this kit or board?


Being a 4266 CL17-18-18-38 @ 1.5V kit, I'd take a different approach. I would set memory clocks from bottom up like you are doing (start at 3200 and then go upwards), but I would set latency timings from top down (start at CL17-18-18-38 and then work downwards step by step).

For example, with your kit, I would OC this way: 
1) Set timings to 3600 CL17-18-18-38 @ 1.35V first. If it works, then push it to 3800 or 3866.
2) If it doesn't work, then increase VDIMM to 1.4V and try again. Keep going upwards to 1.5V limit.
3) Once I find a memory clock that works high enough to satisfy me, then I start moving CL timings downwards step by step. So CL17-17-17-37, CL16-16-16-36 etc....
4) At some point in this process, your VDIMM will become insufficient for stability, so increase DRAM voltage again, up to the limit that you are comfortable with (I would limit to 1.5V, and ensure adequate airflow onto the memory).

Don't jump straight to CL14, as these kits are binned for highest memory clocks and not lowest latencies, unlike the F4-3200C14D-32GVKB kits.


----------



## umea

Spoiler






TimeDrapery said:


> @umea
> 
> Hmmmmm... I'm sure it's not _the worst_ way to go about overclocking your memory but the way you are doing this is likely to be harder than it needs to be
> 
> The first thing I'd do is determine the frequencies I'm capable of running... Set VDIMM (and your other voltages [SOC, VDDG, etc.] too) as high as you're comfy with setting it, input some loose baseline timings, and start increasing the frequency until you're not able to get past POST
> 
> Once you're there, back the freq off a step and start tightening timings





I'll give this a shot, thanks.


----------



## Veii

Bezcit said:


> Hello, please, if you say "higher RTT", it means:
> A) Increase RZQ/x values, like RZQ/6 to RZQ/7 and such
> or
> B) Increase the ohms itself, like 40ohm to 80ohm and such
> 
> Because I have a bit temperature problems with my Bdie dual rank (2x16) on UnifyX, the two DIMMs are very close to each other. 3800 CL14 flat, VDIMM 1.48V, 36.9 6/3/3, 40/20/30/20. It´s stable even 30 cycles of 1usmusV3, until a very hot summer day it throw an error, # says it ram overheating (usually happens at 45-50°C DIMM range).


It was ment for the negative side ~ but i can see it being strangely phrased
If you have issues, start with higher ohm values = lower RTT dividers.

But if you have thermal issues, start with higher rtt dividers or lower Ohm results
I didn't say the "type of issue" soo it can be confusing. Sorry

6-3-3 is already quite fine for 2x 16gb dimms
6-3-4 will be hard to get running
7-3-4 might work , as 1.48v is not high. Soo RTT_NOM can be used as only /7 here, might need /6 but i doubt

Lowering procODT in general and so lowering cLDO_VDDP to the lowest possible without having missmatching tPHYRDL & tMRDPDA between both dimms (zentimings)
will already help with heat and increase signal integrity/cleanness of the signal
That you can then amplify stronger with ClkDrvStr (CAD_BUS) and so lower RTT_PARK further
At best, you'd run RTT_WR /2, but that one is hard
Soo it makes likely more sense, to start working with RTT_WR /3 + tCKE range
Utilizing and controlling the signal pulse.
error descripts are not always 100% correct, but 50c is quite something.
You can still consider to increase tRFC or just increase tWR.

Higher RTT dividers, will need more VDIMM
But it will not mean , that more heat will be the result of it
Just consider it


----------



## Merciless_Rick

Audioboxer said:


> About to buy some new memory, between
> 
> F4-3600C14D-32GVKA
> CL14-14-14-34 1.45V
> 
> and
> 
> F4-4000C16D-32GVKA
> CL16-16-16-36 1.40V
> 
> I've seen some 4000C16 sets manage 3800 CL14, but often tRCDRD is stubborn and sits on 15. I know lower binned voltage is usually king, but would the C14 set possibly have a better chance of doing 3800 14-14-14?
> 
> It's the slightly more expensive of the two. But I'd rather not spend the money if the 4000 set is better and/or the chances of both are quite the same for 3800 CL14 being stable.


Been lurking this forum for months now... Had to reply because I've seen you talk about getting a new ram kit and ask specifically about the F4-4000C16D-32GVKA kit.
I've owned this set for a bit over a month now and I'm quite impressed; managed to boot at 4000 cl 16 with gdm on, but was far from stable and haven't tinkered at 4000 again.
Running 3800 tcwl [email protected] 15-15-15-30-45 1T gdm disabled between 1.44-1.45v on my B550 Unify X(close to stable but not quite there yet!
I'm def a novice and most of what I've learned has been on this forum.
I haven't managed to get flat [email protected], though I've learned a lot since I last tried.
I was tempted to buy the 3600 cl14 too...super low latencies! But the 4000 kit while being a smidge slower in latencies is def the better binned kit... though I believe the 3600 kit is more expensive(at least in the States)
Anyway I've run the 4000 on an X570 Unify, B550 Unify X, and an Asus B550 gaming edge... Have an amazing performance on all boards. Asus had a stable 3866 oc but wouldn't boot XMP or 4000 loose manual timings; B550 Unify X can boot 4000 with my 5600x but I haven't really put in the time to get stable as I've been focused on 3800 cl14 sub 55ns stable.
Here's some of my timings so far... Keep in mind haven't worked out all the kinks yet:


----------



## TimeDrapery

Spoiler






umea said:


> I'll give this a shot, thanks.






@umea 

For sure! Have fun and keep checking in, I've learned a ton from this thread and the members that contribute to it regularly (props dudes, you know who you are) so just dive in, read, experiment, contribute, and ask questions

There's nothing wrong with going @Sleepycat 's route either, I'm just impatient and find that cranking voltages up and finding lower limits for powering once I've attained whatever clock speed or timing goals I set out for is faster and requires less guess work, YMMV so go with what you're most comfortable with


----------



## TimeDrapery

Spoiler






Merciless_Rick said:


> Been lurking this forum for months now... Had to reply because I've seen you talk about getting a new ram kit and ask specifically about the F4-4000C16D-32GVKA kit.
> I've owned this set for a bit over a month now and I'm quite impressed; managed to boot at 4000 cl 16 with gdm on, but was far from stable and haven't tinkered at 4000 again.
> Running 3800 tcwl [email protected] 15-15-15-30-45 1T gdm disabled between 1.44-1.45v on my B550 Unify X(close to stable but not quite there yet!
> I'm def a novice and most of what I've learned has been on this forum.
> I haven't managed to get flat [email protected], though I've learned a lot since I last tried.
> I was tempted to buy the 3600 cl14 too...super low latencies! But the 4000 kit while being a smidge slower in latencies is def the better binned kit... though I believe the 3600 kit is more expensive(at least in the States)
> Anyway I've run the 4000 on an X570 Unify, B550 Unify X, and an Asus B550 gaming edge... Have an amazing performance on all boards. Asus had a stable 3866 oc but wouldn't boot XMP or 4000 loose manual timings; B550 Unify X can boot 4000 with my 5600x but I haven't really put in the time to get stable as I've been focused on 3800 cl14 sub 55ns stable.
> Here's some of my timings so far... Keep in mind haven't worked out all the kinks yet:
> View attachment 2520785
> View attachment 2520786
> View attachment 2520787
> View attachment 2520788






@Merciless_Rick

Very cool stuff! Why the unequal SCL timings and/or (I see these are set to the same value in a later ZenTimings screenshot) the SD/DD mismatches? I'd think that with your nice, low voltages you could reduce ProcODT further, have you tried? If you look through the thread a lot of people running 32GB DR DIMMs see good results from a 4-1-4-4/4-1-6-6 set, are you seeing different on yours?

Thanks for sharing, 1T is tough!


----------



## Netarangi

PJVol said:


> @Netarangi
> You seem to miss my post, 3h ago.


Hey sorry it got lost amongst the other posts. I should check my notifications  My bad! Thank you for the reply.

I thought cl14 would be faster and was obsessed with getting 1T working. I'll start over with cl15.










Getting error 6 instantly. I've tried different ProcODT, voltages on SOC and DRAM, raising primaries. Could only boot with DrvStr at 60.

What do?

Edit #2: Got it to begin testing with AddrCmdSetup 56. No idea what number does lol.


----------



## kairi_zeroblade

@Netarangi 
How much did you already spent over those kits just to get to higher memory frequencies?? does the AIDA64 bench really bother you guys??


----------



## mongoled

@domdtxdissar

Just confirming the logic you implied makes perfect sense

More RAM taken by OS means less RAM available for testing meaning TM5 takes less time to complete.



Now here is a completed 3800 [email protected], time taken to complete is where I would expect it to be.

Dilemma is ive ran out of things to optimise

😄😄

Switching to 1T pushes tPHYRDL to 28 on both dimms, ive played with a ton of settings and cant get it to 26 when I use a combination of tCL @14 and Cmd2T @2T.

Anyone got any ideas that have yet to be discussed

🤣🤣

@TimeDrapery
PC had rebooted using 1.56 vdimm, upped it to 1.57v and voila



Going to run a few hours of Y-Cruncher ....

** EDIT **
After Y-Cruncher will change AddrCmdSetup to 56 with the others at 0 ...

Added Y-Cruncher, its not 7 hrs but around 5 1/2 as I accidently paused it ...


----------



## Netarangi

kairi_zeroblade said:


> @Netarangi
> How much did you already spent over those kits just to get to higher memory frequencies?? does the AIDA64 bench really bother you guys??


I'm building a PC for my younger brother so using all the ram kits.

Sorry I've bothered you with my posts. I'll leave now


----------



## kairi_zeroblade

Netarangi said:


> Sorry I've bothered you with my posts. I'll leave now


nope..you weren't a bother, well for me, spending that much on rams to get low latencies, would be just better off with a higher processor for me or an additional budget on a good Gen 4 NVME, CPU Cooler or GPU..memory alone isn't the center of latency issues..


----------



## Audioboxer

Merciless_Rick said:


> Been lurking this forum for months now... Had to reply because I've seen you talk about getting a new ram kit and ask specifically about the F4-4000C16D-32GVKA kit.
> I've owned this set for a bit over a month now and I'm quite impressed; managed to boot at 4000 cl 16 with gdm on, but was far from stable and haven't tinkered at 4000 again.
> Running 3800 tcwl [email protected] 15-15-15-30-45 1T gdm disabled between 1.44-1.45v on my B550 Unify X(close to stable but not quite there yet!
> I'm def a novice and most of what I've learned has been on this forum.
> I haven't managed to get flat [email protected], though I've learned a lot since I last tried.
> I was tempted to buy the 3600 cl14 too...super low latencies! But the 4000 kit while being a smidge slower in latencies is def the better binned kit... though I believe the 3600 kit is more expensive(at least in the States)
> Anyway I've run the 4000 on an X570 Unify, B550 Unify X, and an Asus B550 gaming edge... Have an amazing performance on all boards. Asus had a stable 3866 oc but wouldn't boot XMP or 4000 loose manual timings; B550 Unify X can boot 4000 with my 5600x but I haven't really put in the time to get stable as I've been focused on 3800 cl14 sub 55ns stable.
> Here's some of my timings so far... Keep in mind haven't worked out all the kinks yet:
> View attachment 2520785
> View attachment 2520787
> View attachment 2520788
> View attachment 2520791


Thanks for some feedback! I've got a B550 Unify X as well.

I might give the 3600C14 set a go, have hardly seen anyone report on this years XMP bin which is 14-14-14-34. I'm guessing a voltage bump to 1.5v might stand a chance of taking the frequency from 3600 to 3800 without changes. I guess we'll see!


----------



## colkoni

Hi all!, this is my first post on this forum.

Im trying to get my memory oc stable, here are zentimings and testmem error pic. any advice what to do next ? 
(and yes i copied all the settings from the google doc sheet) thanks in advance!.


----------



## Mach3.2

Nobody really know what the errors meant for anta's tm5 config, you should switch to [email protected]_v3 config, and run at least 20 cycles of it to verify timings.

[email protected]_v3 errors can be deciphered using Veii's tRFC calculator, there's a sheet explaining what the errors meant.

Change the .txt extension to .cfg, then import into tm5.


----------



## Audioboxer

Bought the F4-3600C14D-32GVKA. Not many people talking about the 14-14-14-34 set of this so excited to share the journey! Still waiting on my replacement GPU coming over from Germany, but it should only be a few more days. New memory will likely be here around same time.

Thankfully EVGA have managed to replace my 2080Ti with another 2080Ti. I say thankfully because they've been known to replace some RMAs with a 3070 as they say it is perfomance equivalent. I have a 2080Ti watercooling block and IMO the 3070 is not totally on par with the 2080Ti.

No idea what killed my X570F Gaming, but I wonder if it was the GPU. EVGA haven't said what is wrong, just tested return and accepted RMA. Not even sure if a GPU could kill a motherboard then die a bit later itself  It made quite a bit of coil whine but it's my understanding that is quite normal on a 2080Ti when its drawing a lot of power.


----------



## colkoni

Changed testmem cfg to 1usmus_v3

Got errors 40-45 min in to testing. max temps were 45.1c and 45.3.





Spoiler: pics


----------



## Audioboxer

colkoni said:


> Changed testmem cfg to 1usmus_v3
> 
> Got errors 40-45 min in to testing. max temps were 45.1c and 45.3.
> 
> 
> 
> 
> 
> Spoiler: pics
> 
> 
> 
> 
> View attachment 2520834
> View attachment 2520835


Have you tried working with 2T first? GDM off and 1T seems to be the promise land with tight timings and flat 14s at 3800 seems to be something only a smaller % of b-die bins will achieve without needing very high voltage. So maybe try tRCDRD at 15.

While I'm still quite the noob with memory I have found tRRDL is sometimes just best left at 6 for stability. Might be safer with a tRFC around 250~270 as well for now. Though with multiple errors I doubt it's a single timing.

Error code descriptions are shown here tRFC Calculator (mini)


----------



## Requiem4u

colkoni said:


> Changed testmem cfg to 1usmus_v3
> 
> Got errors 40-45 min in to testing. max temps were 45.1c and 45.3.


Maybe try tRAS 28, tRC 42, tRRDL 6, tWTRL 12, tRFC 252 and tRDWR 9. If CMD 2T, try setup 0,0,0 or 3,3,15.


----------



## Ishanji

colkoni said:


> Changed testmem cfg to 1usmus_v3
> 
> Got errors 40-45 min in to testing. max temps were 45.1c and 45.3.
> 
> 
> 
> 
> 
> Spoiler: pics
> 
> 
> 
> 
> View attachment 2520834
> View attachment 2520835


Hey got the same kit and i can tell you 1T is hard to achieve with them on [email protected]
It's way easier to go [email protected] 1T and then start improving this profile once it's stable.
It is probably a powering issue you got there,my Kit behaves better with RTTPark=RZQ/3 so you might want to try it
and maybe loosen your tWTRL to 15 and stay on tWTRS=4 gave lots of stability for me and yea like Audioboxer said tRDDL= 6.
If you go slower on tRFC 252/187/115, it helps with Vdimm requirement.
tCWL=12 gave about 200mb/s read and 400mb/s write bandwidth more then tCWL=14.
Also my kit refuses to boot with tRDWR lower then 10 and they seem to like high ClkDrvStr try 60 or even 120 Ohm there.
If all this doesn't help, you might need to fiddle with ProcODT 36.9 Ohm


----------



## 1devomer

Potato cpu final overclock, it passed 30min of CB R20 (27passes) and the quick TM5 test.

C-States/CPPC/CoreBost: Disabled
VCPU: 1.45v
VSOC: 1.1v
VDDG IOD: 0.925v
VDDG CCD: 0.925v
VDDP: Auto = 0.9976v
VMEM: 1.5v


CPU CB R20 t°: 82.5°
MEM TM5 t°: 43.8°
AMBIENT: 27°- 30°












Can't really do much more with this potato cpu, the 2nd CCX is awful, bringing down the whole cpu.
Going above 4125Mhz, i got WHEA error 19 Error Type: Bus/Interconnect Error Processor APIC ID: 0, when i reboot.

Attached below the .txt bios settings file.


----------



## rdr09

1devomer said:


> Potato cpu final overclock, it passed 30min of CB R20 (27passes) and the quick TM5 test.
> 
> VCPU: 1.45v
> VSOC: 1.1v
> VDDG IOD: 0.925v
> VDDG CCD: 0.925v
> VDDP: Auto = 0.9976v
> VMEM: 1.5v
> 
> CPU CB R20 t°: 82.5°
> MEM TM5 t°: 43.8°
> AMBIENT: 27°- 30°
> 
> View attachment 2520854
> 
> 
> 
> 
> Can't really do much more with this potato cpu, the 2nd CCX is awful, bringing down the whole cpu.
> Going above 4125Mhz, i got WHEA error 19 Error Type: Bus/Interconnect Error Processor APIC ID: 0, when i reboot.
> 
> Attached below the .txt bios settings file.


We get about the same score but my R5 3600 was oc'ed to 4.2GHz and RAM set at DOCP 3600 Cl16.

That's on a B550 same with my Asus X470 Pro. The CPU can't oc to 4.2GHz on my B350F Strix.

Your tuned RAM compensates for lack of cpu oc.


----------



## 1devomer

rdr09 said:


> We get about the same score but my R5 3600 was oc'ed to 4.2GHz and RAM set at DOCP 3600 Cl16.
> 
> That's on a B550 same with my Asus X470 Pro. The CPU can't oc to 4.2GHz on my B350F Strix.
> 
> Your tuned RAM compensates for lack of cpu oc.


Yeah, still i'm a bit salty, regarding the cpu oc behaviour.

The 32Meg WSON WindBond bios i ordered, to be able to flash a x470 bios, arrived today.
Need to figure out exactly how to keep both chips soldered, we will see how it goes.


----------



## domdtxdissar

domdtxdissar said:


> Done tightening the timings for now, think i will switch over to trying to stabilize T1, with or without 56 setup-time now..
> Managed to squeeze out *228 (120ns) tRFC* together with *tWR 10* and *tRTP 5* which is a new record for me
> View attachment 2520354


Countless hours bruteforcing settings and one new windows-install later, ive finally managed to stabilize (very) tight CL14 timings together with T1 setup-time 

I can truly say that its much harder to stabilize T1 setup-time with 2x16GB then with 4x8GB when you are right on the edge. Pretty much one setting/voltage up or down at this point and it wont pass 25 cycles TestMEM 1usmus cfg.. Even if i just switch position on my memory sticks in the motherboard memory-slots it will fail  (found this out after nearly wasting 5 days)

But here we go, 25 cycles 1usmus together with 1 hour OCCT large dataset: 









Some synthetic numbers:









Real benchmarking in Linpack Xtreme:



Spoiler: 16 cores at 4500mhz - T1 55 setup-time = 639 and 666 score

















Spoiler: My old 4x8GB setup with flat CL14 timings: 16 cores at 4500mhz - T1 56 setup-time = 634 and 660 score

















Spoiler: 16 cores at 4500mhz - Pure T2 = 630 and 660 score

















Spoiler: 16 cores at 4500mhz - T1 GDM = 629 and 655 score















Some key takeaways from this Linpack testing on this setup:


*Pure T2 is not all that much faster then T1 GDM, difference is 1 and 5 gigaflops. *(but GDM takes longer to "stabilize" the score)
*T1 setup-time is suprisling much faster than T1 GDM, difference is 10 and 15 gigaflops *
*T1 setup-time is also faster then pure T2 by 9 and 10 gigaflops*
My new 2x16 settings also beat my old flat CL14 4x8GB settings by a decent margin.

Sadly i cant run pure T1 and test this difference between it and setup-time, but i don't think it can be all that much looking at numbers above.... Will concentrate on tightening the timings even more instead of trying for pure T1 for now. (bricked my everyday windows install when i tried for T1 yesterday)

As a bonus i also did some 6 core runs in Linpack so even those with 5600x cpus can compare memory performance numbers if they want 



Spoiler: 6 cores at 4500mhz - T1 55 setup-time = 266 and 268 score

















Spoiler: 6 cores at 4650mhz - T1 55 setup-time = 274 and 276 score

















Spoiler: And for fun, a 6 cores at 4850mhz - T1 55 setup-time = 286 score run with fans on auto and warm-room (can push above 290 when maxed)


----------



## mongoled

domdtxdissar said:


> Countless hours bruteforcing settings and one new windows-install later, ive finally managed to stabilize (very) tight CL14 timings together with T1 setup-time
> 
> I can truly say that its much harder to stabilize T1 setup-time with 2x16GB then with 4x8GB when you are right on the edge. Pretty much one setting/voltage up or down at this point and it wont pass 25 cycles TestMEM 1usmus cfg.. Even if i just switch position on my memory sticks in the motherboard memory-slots it will fail  (found this out after nearly wasting 5 days)
> 
> But here we go, 25 cycles 1usmus together with 1 hour OCCT large dataset:
> View attachment 2520863
> 
> 
> Some synthetic numbers:
> View attachment 2520864
> 
> 
> Real benchmarking in Linpack Xtreme:
> 
> 
> 
> Spoiler: 16 cores at 4500mhz - T1 55 setup-time = 639 and 666 score
> 
> 
> 
> 
> View attachment 2520865
> 
> 
> 
> 
> 
> 
> Spoiler: My old 4x8GB setup with flat CL14 timings: 16 cores at 4500mhz - T1 56 setup-time = 634 and 660 score
> 
> 
> 
> 
> View attachment 2520872
> 
> 
> 
> 
> 
> 
> Spoiler: 16 cores at 4500mhz - Pure T2 = 630 and 660 score
> 
> 
> 
> 
> View attachment 2520866
> 
> 
> 
> 
> 
> 
> Spoiler: 16 cores at 4500mhz - T1 GDM = 629 and 655 score
> 
> 
> 
> 
> View attachment 2520867
> 
> 
> 
> 
> Some key takeaways from this Linpack testing on this setup:
> 
> 
> *Pure T2 is not all that much faster then T1 GDM, difference is 1 and 5 gigaflops. *(but GDM takes longer to "stabilize" the score)
> *T1 setup-time is suprisling much faster than T1 GDM, difference is 10 and 15 gigaflops *
> *T1 setup-time is also faster then pure T2 by 9 and 10 gigaflops*
> My new 2x16 settings also beat my old flat CL14 4x8GB settings by a decent margin.
> 
> Sadly i cant run pure T1 and test this difference between it and setup-time, but i don't think it can be all that much looking at numbers above.... Will concentrate on tightening the timings even more instead of trying for pure T1 for now. (bricked my everyday windows install when i tried for T1 yesterday)
> 
> As a bonus i also did some 6 core runs in Linpack so even those with 5600x cpus can compare memory performance numbers if they want
> 
> 
> 
> Spoiler: 6 cores at 4500mhz - T1 55 setup-time = 266 and 268 score
> 
> 
> 
> 
> View attachment 2520869
> 
> 
> 
> 
> 
> 
> Spoiler: 6 cores at 4650mhz - T1 55 setup-time = 274 and 276 score
> 
> 
> 
> 
> View attachment 2520870
> 
> 
> 
> 
> 
> 
> Spoiler: And for fun, a 6 cores at 4850mhz - T1 55 setup-time = 286 score run with fans on auto and warm-room (can push above 290 when maxed)
> 
> 
> 
> 
> View attachment 2520871


Very nice, well done.

See your CPU/RAM/Motherboard combination is also not able to do [email protected] while running 3800 tCL14 and 1T.

Its nice of you to do some comparison for us 5600x users, but the reality is that its not really a valid comparison due to the lower ProcHot values for the 5600x and lower max boost frequencies etc etc.

Are you also watercooling the dimms as your dimm temps are really low !

Just completed this


----------



## colkoni

Requiem4u said:


> Maybe try tRAS 28, tRC 42, tRRDL 6, tWTRL 12, tRFC 252 and tRDWR 9. If CMD 2T, try setup 0,0,0 or 3,3,15.


yay!
I did try this and after one error, raised voltage 0,01. know it is "stable" it lasted all 20 testmem5 cycles.

Now what ? should i try CR1 or start tighten more timings? i was hoping to get lower latency.



Spoiler: proof













I ran the aida64 benchmark after the testmem5 cycles, and had those other windows open so it might affect the results.


----------



## domdtxdissar

mongoled said:


> See your CPU/RAM/Motherboard combination is also not able to do [email protected] while running 3800 tCL14 and 1T.


Yeah i always get 28 when enabling T1, both with and without GDM... T2 run with [email protected] tho.



mongoled said:


> Its nice of you to do some comparison for us 5600x users, but the reality is that its not really a valid comparison due to the lower ProcHot values for the 5600x and lower max boost frequencies etc etc.


Cant you set static OC @ 4.5ghz allcore and compare ? All my numbers in post above are with static OC so they can be used in comparisons between different systems..
If you have problems booting 4.5ghz from bios its really easy to boot stock settings and use CTR to set the static OC once in windows and ready to benchmark. (which also ignore any power/frequency/temp limitations you have with PBO _hint*hint_)



mongoled said:


> Are you also watercooling the dimms as your dimm temps are really low !


Just have lots of fans 
(120mm straight at memory)













mongoled said:


> View attachment 2520878


Very nice 
Would be interesting if you could do a comparison like i did in Linpack.. set 4500mhz static oc and compare number between T1 GDM, T2, T1 setup-time and pure T1


----------



## Audioboxer

domdtxdissar said:


> Countless hours bruteforcing settings and one new windows-install later, ive finally managed to stabilize (very) tight CL14 timings together with T1 setup-time
> 
> I can truly say that its much harder to stabilize T1 setup-time with 2x16GB then with 4x8GB when you are right on the edge. Pretty much one setting/voltage up or down at this point and it wont pass 25 cycles TestMEM 1usmus cfg.. Even if i just switch position on my memory sticks in the motherboard memory-slots it will fail  (found this out after nearly wasting 5 days)
> 
> But here we go, 25 cycles 1usmus together with 1 hour OCCT large dataset:
> View attachment 2520863
> 
> 
> Some synthetic numbers:
> View attachment 2520864
> 
> 
> Real benchmarking in Linpack Xtreme:
> 
> 
> 
> Spoiler: 16 cores at 4500mhz - T1 55 setup-time = 639 and 666 score
> 
> 
> 
> 
> View attachment 2520865
> 
> 
> 
> 
> 
> 
> Spoiler: My old 4x8GB setup with flat CL14 timings: 16 cores at 4500mhz - T1 56 setup-time = 634 and 660 score
> 
> 
> 
> 
> View attachment 2520872
> 
> 
> 
> 
> 
> 
> Spoiler: 16 cores at 4500mhz - Pure T2 = 630 and 660 score
> 
> 
> 
> 
> View attachment 2520866
> 
> 
> 
> 
> 
> 
> Spoiler: 16 cores at 4500mhz - T1 GDM = 629 and 655 score
> 
> 
> 
> 
> View attachment 2520867
> 
> 
> 
> 
> Some key takeaways from this Linpack testing on this setup:
> 
> 
> *Pure T2 is not all that much faster then T1 GDM, difference is 1 and 5 gigaflops. *(but GDM takes longer to "stabilize" the score)
> *T1 setup-time is suprisling much faster than T1 GDM, difference is 10 and 15 gigaflops *
> *T1 setup-time is also faster then pure T2 by 9 and 10 gigaflops*
> My new 2x16 settings also beat my old flat CL14 4x8GB settings by a decent margin.
> 
> Sadly i cant run pure T1 and test this difference between it and setup-time, but i don't think it can be all that much looking at numbers above.... Will concentrate on tightening the timings even more instead of trying for pure T1 for now. (bricked my everyday windows install when i tried for T1 yesterday)
> 
> As a bonus i also did some 6 core runs in Linpack so even those with 5600x cpus can compare memory performance numbers if they want
> 
> 
> 
> Spoiler: 6 cores at 4500mhz - T1 55 setup-time = 266 and 268 score
> 
> 
> 
> 
> View attachment 2520869
> 
> 
> 
> 
> 
> 
> Spoiler: 6 cores at 4650mhz - T1 55 setup-time = 274 and 276 score
> 
> 
> 
> 
> View attachment 2520870
> 
> 
> 
> 
> 
> 
> Spoiler: And for fun, a 6 cores at 4850mhz - T1 55 setup-time = 286 score run with fans on auto and warm-room (can push above 290 when maxed)
> 
> 
> 
> 
> View attachment 2520871


I was trying to figure out why I've become addicted to the 'memory game' after not bothering for years and this is it. AMD have done a really good job with Ryzen, especially the 5xxx chips, that overclocking is "less" fun. There's still work to do and I cringe at how many people will be running unstable curves whilst thinking they are stable, but it's become really user friendly. Which is a good thing!

Memory on the other hand, this is the dark arts. Lots of timings and things to change, lots of targets to aim for and the satisfaction of putting in tens if not hundreds of hours to get every last drop of performance out of your sticks. Lots of learning to do! Well done, that is some dedication and nice timings!


----------



## sendap

domdtxdissar said:


> [email protected]


i have seen this come up lately. It was never talked about before as far as i remember. What is this tPHYRDL about? What does it do?


----------



## Mach3.2

domdtxdissar said:


> Just have lots of fans
> (120mm straight at memory)
> View attachment 2520889


That's a lot of Noctuas($$$$$)


----------



## Requiem4u

colkoni said:


> yay!
> I did try this and after one error, raised voltage 0,01. know it is "stable" it lasted all 20 testmem5 cycles.
> 
> Now what ? should i try CR1 or start tighten more timings? i was hoping to get lower latency.


My CPU is 5800X so it can be different latency for you. Try just after windows startup to get better results.
I hope someone like @Veii will guide you further with ProcODT and RTT:s to get more voltage etc. Maybe slower subtimings to get 1T.
I can't get 1T or CL14 flat just yet so I can not tell.
I just find out how to turn off RGB on my Gskill ram, that should help me because of lower temps. I have no sensors.


----------



## PJVol

domdtxdissar said:


> those with 5600x cpus can compare memory performance numbers


Questionable gains from tightening to 14 tbh, considering the efforts needed ...


----------



## Bezcit

Veii said:


> It was ment for the negative side ~ but i can see it being strangely phrased
> If you have issues, start with higher ohm values = lower RTT dividers.
> 
> But if you have thermal issues, start with higher rtt dividers or lower Ohm results
> I didn't say the "type of issue" soo it can be confusing. Sorry
> 
> 6-3-3 is already quite fine for 2x 16gb dimms
> 6-3-4 will be hard to get running
> 7-3-4 might work , as 1.48v is not high. Soo RTT_NOM can be used as only /7 here, might need /6 but i doubt
> 
> Lowering procODT in general and so lowering cLDO_VDDP to the lowest possible without having missmatching tPHYRDL & tMRDPDA between both dimms (zentimings)
> will already help with heat and increase signal integrity/cleanness of the signal
> That you can then amplify stronger with ClkDrvStr (CAD_BUS) and so lower RTT_PARK further
> At best, you'd run RTT_WR /2, but that one is hard
> Soo it makes likely more sense, to start working with RTT_WR /3 + tCKE range
> Utilizing and controlling the signal pulse.
> error descripts are not always 100% correct, but 50c is quite something.
> You can still consider to increase tRFC or just increase tWR.
> 
> Higher RTT dividers, will need more VDIMM
> But it will not mean , that more heat will be the result of it
> Just consider it


Thank you for detailed reply and very good advice!
I switched RTTs from 6/3/3/ to 7/3/4/, ODT from 36.9 to 30.0, and thermals are much better now


----------



## domdtxdissar

PJVol said:


> Questionable gains from tightening to 14 tbh, considering the efforts needed ...


Can you show Zentimings together with Linpack ?  Much easier to compare numbers then you know what the other guy is running 
_edit_
Are you running these settings ?









One of the things we don't know atm is the difference between T1 and T1 setup-time in Linpack.
Also seems like dualrank vs singlerank don't matter much here


----------



## domdtxdissar

One thing is for sure, 4000C14D is very very good (if not the best) binned b-die on the market.
Just completed initial stabilitytesting @ 216 tRFC (113ns) on a dualrank 32gigs setup 
30min OCCT Memory SSE stresstest


----------



## XPEHOPE3

Veii said:


> Single CCD can run
> 
> 
> 
> 
> 
> 
> 
> 
> To override allcore EDC throttle


I have dual-CCD, and if I issue that very command I get TDC limit changed! To actually change EDC limit I have to issue a ..._SetPPTLimit command. I feel scared issuing commands left and right like that...
Do you have an updated version of this? Where can one get it? Is the forum where you obtained the tool in the first place open to newcomers?


----------



## MrHoof

Veii said:


> 113 Binning value is already good, 118 is fantastic - haven't seen 120+ so far


@Veii









well after checking some pages more this isnt speical i gues ignore this post


----------



## PJVol

domdtxdissar said:


> Are you running these settings ?


Yep, basically those. And allcore 4650 gave me 275Gflops.


domdtxdissar said:


> T1 and T1 setup-time in Linpack


The latter mean AddrCmdSetup > 31 ?


----------



## domdtxdissar

PJVol said:


> Yep, basically those. And allcore 4650 gave me 275Gflops.
> 
> The latter mean AddrCmdSetup > 31 ?


Yeah, i pretty much mean any numbers other then 0-0-0 when i talked about "T1 setup-time"


----------



## PJVol

XPEHOPE3 said:


> if I issue that very command I get TDC limit changed! To actually change EDC limit I have to issue a ..._SetPPTLimit command. I feel scared issuing commands left and right like that...


Don't use the top mailbox, cause it appears to be broken.
Use the bottom one instead, select Set EDC Limit 0x55, enter the value in mA in the field above and click Apply.


----------



## craxton

XPEHOPE3 said:


> @spajdr
> Great! That means I don't have a cue to why is my write bandwidth throttled, because yours isn't although you see the same load
> 
> In BIOS they are, in ZenStates they are not.
> 
> @Veii
> I believe that's just another Dreamer account.
> 
> Also I've found that Aida64 latency actually always uses Core0 (and a little of Core1) to test latency. It's obvious both from HWiNFO and ACPI performance measurement. So @craxton maybe that's why you have higher latency than e.g. @mongoled at comparative timings - maybe your Core0 is the worst.


"ive been away" so im unsure if mongoled upgraded to a 5800x or hes still beating me with
his 5600x lol with my c14/3800 vs his c15/3800 setup. 
none the less, i have done absolutly NOTHING on my pc really besides some netflix for 
well all but 10 minutes


Spoiler



thats all i can get out of her nowdays it seems lol 
before she jumps to the "after netflix"



but i will say, its literally FREEZING in my inlaws basement. yes, moved out of our OWN home
to move north with her mfn MOM TF?!?!? but i am already working so....
back to it being freezing in here...so i pretty much turned the 90mm fan off i was running an let 
the pc run thru tests (forgot about it honestly) while it ran for around 100+ iterations of y-cruncher with 
kombuster heating up in the background and have "yet" had any issues with anything. the one thing
i didnt do was ramp any fans at all up....

also did the same with TM5/HCI. but yesterday i had a random reboot happen twice, so i dialed back my CO
each time i had this random reboot. yet i have no logs recorded or WHEA errors anyhow to see if it was indeed 
a crash, or just windows doing its thing....i dont much have a "decent" spot for my keyboard other than my lap at the end of a bed atm using a 720p tv that looks horrible too....
im almost positive that if i ran for THIS LONG without issues on the CO i was running that its possibly not the issue...maybe the basement warmed up or something and i had some ram overheating, im unsure??


----------



## craxton

anyone know if "MSI" is still being douche bags with their bios releases
or are they now unlocking things themselves? lol yea im really asking bc 
im unsure where my backup of this unlocked might be hiding at in storage or 
my personal bag atm...(pretty FD up i brought all my pc stuff here while stuff i really needed
went into storage)


----------



## umea

Honest question, what are the settings that I should fiddle with to get GDM off/1T running stably? From what I'm reading a lot of it has to do with RTT values + setup times. Should I focus on getting a good OC on 2T running first and then work on getting 1T running? Or is starting at 1T / GDM off worth it?

Edit: Managed to get cl15 flat 3800 GDM off + 1T running stable(?) and am working on tightening timings, how much of a performance increase is 3800 14 flat?


----------



## mil777

Has anyone ever found a solution to TM5 randomly stopping the test and going idle?

I'm semi-new to RAM overclocking and I've used Karhu before, but as you know, when you get an error you don't know what could actually be the culprit.
So I've seen that TM5 can help in troubleshooting because there's multiple error codes, but no matter if I try anta777 or 1usmus, I've never had a single test go from start to finish without giving up somewhere in the middle without showing any errors. There's other people reporting on it too - 1 2.

You can see in my screenshot; the test is still counting time as if it's active, but all the memory is freed up, the line where it's supposed to display which test it's currently running is blank.
And before you say, no it's not one of those short pauses inbetween tests, if I leave it like this it won't resume the testing. I saw it stop at the 7 minute mark and it's still stuck 9 minutes later.
Sometimes it stops after half an hour or later, but I've never had the test actually finish.

Is there anything I could try to make this work?


----------



## mongoled

domdtxdissar said:


> Yeah i always get 28 when enabling T1, both with and without GDM... T2 run with [email protected] tho.
> 
> 
> Cant you set static OC @ 4.5ghz allcore and compare ? All my numbers in post above are with static OC so they can be used in comparisons between different systems..
> If you have problems booting 4.5ghz from bios its really easy to boot stock settings and use CTR to set the static OC once in windows and ready to benchmark. (which also ignore any power/frequency/temp limitations you have with PBO _hint*hint_)
> 
> 
> Just have lots of fans
> (120mm straight at memory)
> View attachment 2520889
> 
> 
> 
> 
> 
> Very nice
> Would be interesting if you could do a comparison like i did in Linpack.. set 4500mhz static oc and compare number between T1 GDM, T2, T1 setup-time and pure T1


No issues for 4500 mhz on this CPU



You must have low ambient temperatures along with those fans !

Here are the following Y-Cruncher results @4500 mhz (funnily enough, enabling GDM results in my requiring to reset BIOS....)

1T "Pure"








2T "Pure"








2T 56-0-0


----------



## domdtxdissar

mongoled said:


> No issues for 4500 mhz on this CPU
> 
> 
> 
> You must have low ambient temperatures along with those fans !
> 
> Here are the following Y-Cruncher results @4500 mhz (funnily enough, enabling GDM results in my requiring to reset BIOS....)
> 
> 1T "Pure"
> View attachment 2520972
> 
> 
> 2T "Pure"
> View attachment 2520973
> 
> 
> 2T 56-0-0
> View attachment 2520974


That's very strange.. you are getting ~same numbers with T1 and T2 while i'm clearly seeing different scores with different settings.. 
Are you sure your numbers are correct ? Seems counterintuitive with T2 being just as fast as pure T1.

These are my numbers: (how it should look i think.. *maybe your not bandwidth limited with only 6 core ?*)

16 cores at 4500mhz - *T1 55 setup-time* = 639 and 666 score








16 cores at 4500mhz - *Pure T2* = 630 and 660 score








16 cores at 4500mhz - *T1 GDM* = 629 and 655 score








"56 setup-time" is only used when you cant run pure T1, so there is no point to run it with T2


----------



## Audioboxer

domdtxdissar said:


> One thing is for sure, 4000C14D is very very good (if not the best) binned b-die on the market.
> Just completed initial stabilitytesting @ 216 tRFC (113ns) on a dualrank 32gigs setup
> 30min OCCT Memory SSE stresstest
> View attachment 2520922


That is 7ns so it literally HAS to be the best bin on the maket, I think lol.

I seen that set and wanted it, but just a little too expensive for me. Had to settle with 7.7777777ns


----------



## spajdr

@mil777 I'm not sure if it's related to your issue but make sure to run TM5 as admin, so right click on TM5 icon and choose Run as Administrator


----------



## boldenc

Guys, which kit should be the better bin for the same price?
[email protected] 1.35v
[email protected] 1.35v


----------



## umea

domdtxdissar said:


> That's very strange.. you are getting ~same numbers with T1 and T2 while i'm clearly seeing different scores with different settings..
> Are you sure your numbers are correct ? Seems counterintuitive with T2 being just as fast as pure T1.
> 
> These are my numbers: (how it should look i think.. *maybe your not bandwidth limited with only 6 core ?*)
> 
> 16 cores at 4500mhz - *T1 55 setup-time* = 639 and 666 score
> View attachment 2520975
> 
> 
> 16 cores at 4500mhz - *Pure T2* = 630 and 660 score
> View attachment 2520976
> 
> 
> 16 cores at 4500mhz - *T1 GDM* = 629 and 655 score
> View attachment 2520977
> 
> 
> "56 setup-time" is only used when you cant run pure T1, so there is no point to run it with T2


What is the downside of running 56 setup time vs 0 on T1? Running 56 avoids near instant BSOD for me, but I was only just fiddling around with different settings.


----------



## Audioboxer

boldenc said:


> Guys, which kit should be the better bin for the same price?
> [email protected] 1.35v
> [email protected] 1.35v


3200 is slightly better at the same price I think. At 3600 you really need to push 14 or 15 to be better than the 3200C14 at 1.35v.

But I wouldn't take my word as definitive, someone else probably knows better than me. I've got a 3200C14 set that runs 3800C16 fine, but I struggled a bit with 3800C15. Though I think my bin just isn't that great coupled with me being new to properly optimising RAM. Still, I've bought another set to replace my 3200C14, but if I was buying again from scratch and my choice was both you've listed I'd go 3200C14 again. For many people it's a great choice. Buildzoid still recommends it.

Part of the hunt with all these b-die kits just seems to be luck on how good a set you get overall, whatever its XMP rating. I've seen 3600C16 sets manage 3800C14.


----------



## XPEHOPE3

mil777 said:


> Has anyone ever found a solution to TM5 randomly stopping the test and going idle?


Do you have "Motherboard" PBO limits set?
Main reason for that behaviour is a silently crashing thread. I got rid of it when I disabled all PBO and set PBO Scalar to 1.



domdtxdissar said:


> "56 setup-time" is only used when you cant run pure T1, so there is no point to run it with T2


Judging from his results there is! As T2+setup was faster than T2


----------



## Audioboxer

XPEHOPE3 said:


> Do you have "Motherboard" PBO limits set?
> Main reason for that behaviour is a silently crashing thread. I got rid of it when I disabled all PBO and set PBO Scalar to 1.


This. I fixed my TM5 timeouts by reducing my curve undervolt. My CPU was passing CoreCyler for 24 hours straight and I wasn't seeing any crashing in apps or games, but TM5 would occassionally timeout overnight. Stopped doing that when I fixed my curve.

So, if TM5 times out I think it's safe to say it's due to your CPU overclock/curve/PBO settings. I've seen one or two posts online casually dismiss it as a "buggy app", but it's clearly not. 99.9% CPU related.


----------



## mil777

spajdr said:


> @mil777 I'm not sure if it's related to your issue but make sure to run TM5 as admin, so right click on TM5 icon and choose Run as Administrator


It's all the same, tried it many times with and without Run as Admin, the only difference is that message.



XPEHOPE3 said:


> Do you have "Motherboard" PBO limits set?
> Main reason for that behaviour is a silently crashing thread. I got rid of it when I disabled all PBO and set PBO Scalar to 1.





Audioboxer said:


> This. I fixed my TM5 timeouts by reducing my curve undervolt. My CPU was passing CoreCyler for 24 hours straight and I wasn't seeing any crashing in apps or games, but TM5 would occassionally timeout overnight. Stopped doing that when I fixed my curve.
> 
> So, if TM5 times out I think it's safe to say it's due to your CPU overclock/curve/PBO settings. I've seen one or two posts online casually dismiss it as a "buggy app", but it's clearly not. 99.9% CPU related.


Huh this is interesting...

Actually I'm not running any PBO/Curve but the CPU is overclocked via 1usmus' CTR. However it's been completely stable and I've never had any issues with CPU overclock.
Maybe switching between TM5 tests triggers different profiles in CTR and it catches some instability though I haven't caught any problems while stress testing the CPU?
Alright I'm gonna try with everything disabled, no PBO, no CTR and hopefully it works, thanks!


----------



## boldenc

Unstable CPU could cause TM5 to silently crash, also corrupted Windows could cause the same.
Try to create new Windows user and re-run the test if you still have problem after reverting all settings to stock.


----------



## mongoled

domdtxdissar said:


> That's very strange.. you are getting ~same numbers with T1 and T2 while i'm clearly seeing different scores with different settings..
> Are you sure your numbers are correct ? Seems counterintuitive with T2 being just as fast as pure T1.
> 
> These are my numbers: (how it should look i think.. *maybe your not bandwidth limited with only 6 core ?*)
> 
> 16 cores at 4500mhz - *T1 55 setup-time* = 639 and 666 score
> View attachment 2520975
> 
> 
> 16 cores at 4500mhz - *Pure T2* = 630 and 660 score
> View attachment 2520976
> 
> 
> 16 cores at 4500mhz - *T1 GDM* = 629 and 655 score
> View attachment 2520977
> 
> 
> "56 setup-time" is only used when you cant run pure T1, so there is no point to run it with T2


100% correct, why do you think I said that making your CPU into a 5600x is not indicative of having a 5600x



Ive previously posted Linpack results and the conclusion on my 5600x (was using 32GB at that time) was that Linpack is not sensitive (very little difference) to changes in memory be it timings or frequency


----------



## Audioboxer

mil777 said:


> It's all the same, tried it many times with and without Run as Admin, the only difference is that message.
> 
> 
> 
> Huh this is interesting...
> 
> Actually I'm not running any PBO/Curve but the CPU is overclocked via 1usmus' CTR. However it's been completely stable and I've never had any issues with CPU overclock.
> Maybe switching between TM5 tests triggers different profiles in CTR and it catches some instability though I haven't caught any problems while stress testing the CPU?
> Alright I'm gonna try with everything disabled, no PBO, no CTR and hopefully it works, thanks!


What chip do you have? If it has access to a curve, so 5xxx, with no offence meant to 1usmus I'd stay away from CTR. AMD really have done a good job optimising these new chips and the curve and some proper PBO values are all you need.

Anyway, that aside, I bet if you uninstall or deactivate CTR for now and run TM5 you won't get crashing. If you're working on your memory overclock just now other than having a stable CPU it doesn't matter if its overclocked. Just run it on auto/default even, at least until you're confident seeing yourself TM5 won't be crashing anymore. Then at that point I'd still recommend not going back to CTR and working a curve/PBO values instead, but that's completely up to yourself.

Right now for SCIENCE! the best thing to do is just prove to yourself your TM5 runs wont crash if your CPU is actually stable. Do a whole week of RAM testing without OCing the CPU. I found in my case I could go days without TM5 timing out, then bam, it randomly happened again one night. Since sorting my curve it didn't do it in weeks.


----------



## mongoled

3800/1900 14-14-14-14-26-38-16-228-1T


----------



## mil777

Audioboxer said:


> What chip do you have? If it has access to a curve, so 5xxx, with no offence meant to 1usmus I'd stay away from CTR. AMD really have done a good job optimising these new chips and the curve and some proper PBO values are all you need.
> 
> Anyway, that aside, I bet if you uninstall or deactivate CTR for now and run TM5 you won't get crashing. If you're working on your memory overclock just now other than having a stable CPU it doesn't matter if its overclocked. Just run it on auto/default even, at least until you're confident seeing yourself TM5 won't be crashing anymore. Then at that point I'd still recommend not going back to CTR and working a curve/PBO values instead, but that's completely up to yourself.
> 
> Right now for SCIENCE! the best thing to do is just prove to yourself your TM5 runs wont crash if your CPU is actually stable. Do a whole week of RAM testing without OCing the CPU. I found in my case I could go days without TM5 timing out, then bam, it randomly happened again one night. Since sorting my curve it didn't do it in weeks.


Yes it's a 5900X and I used CTR from previous gen so I got used to it, but I'll try Curve once I finish with the RAM.

Unfortunately, disabling any kind of overclock on the CPU didn't help with TM5.
I thought it was going well, it ran for 2 hours and got to 20th cycle on 1usmus_v3 but still "timed out".
This is getting frustrating.



boldenc said:


> Unstable CPU could cause TM5 to silently crash, also corrupted Windows could cause the same.
> Try to create new Windows user and re-run the test if you still have problem after reverting all settings to stock.


This current Windows install is just a few days old, I doubt that could be the issue with an install that fresh?


----------



## Bezcit

mil777 said:


> Yes it's a 5900X and I used CTR from previous gen so I got used to it, but I'll try Curve once I finish with the RAM.
> 
> Unfortunately, disabling any kind of overclock on the CPU didn't help with TM5.
> I thought it was going well, it ran for 2 hours and got to 20th cycle on 1usmus_v3 but still "timed out".
> This is getting frustrating.
> 
> 
> This current Windows install is just a few days old, I doubt that could be the issue with an install that fresh?


Do you open any applications / programs during the TM5 test? If yes, it´s the culprit. Because it fails memory allocation hence crash a thread = TM5 just continue counting time but actually do nothing.


----------



## mil777

Bezcit said:


> Do you open any applications / programs during the TM5 test? If yes, it´s the culprit. Because it fails memory allocation hence crash a thread = TM5 just continue counting time but actually do nothing.


No, I didn't open anything after the test started, I left the computer and was just checking periodically if the test is still running.
The only applications running in the background are HWInfo and MSI Afterburner (without overclock on the GPU). I don't see why it would suddenly have shortage of memory after it's been doing fine for 2 hours and I haven't touched anything in the meantime.

I also wanted to test this theory so I started the test again, then opened a browser with many tabs and also opened a game too but the test still kept going.
I noticed that the "Used by test" allocation varies when I open other stuff so the program can detect and reacts to changes.

But there's also something else I've noticed in Task Manager. It shows that it's using 2.2MB per thread even though 98% of all memory is allocated and the application itself shows only 363MB available.








Btw, the folder where I ran TM5 from is on a second SSD where I keep these small portable programs, so I will try to run it from system disk tonight.
Maybe some power saving feature kicks in and temporarily puts the drive to sleep. I don't know, I'm running out of ideas, this is so bizarre 😩


----------



## byDenoso

My new stable settings, it take 10min less to complete than the earlier result.


----------



## Requiem4u

colkoni said:


> yay!
> I did try this and after one error, raised voltage 0,01. know it is "stable" it lasted all 20 testmem5 cycles.
> 
> Now what ? should i try CR1 or start tighten more timings? i was hoping to get lower latency.


[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

Check this out. Lower temps and higher voltage can be done if you want to try 1T.


----------



## Audioboxer

mil777 said:


> Yes it's a 5900X and I used CTR from previous gen so I got used to it, but I'll try Curve once I finish with the RAM.
> 
> Unfortunately, disabling any kind of overclock on the CPU didn't help with TM5.
> I thought it was going well, it ran for 2 hours and got to 20th cycle on 1usmus_v3 but still "timed out".
> This is getting frustrating.
> 
> 
> This current Windows install is just a few days old, I doubt that could be the issue with an install that fresh?


Did you default the BIOS CPU settings or is PBO still turned on? CPU voltage and CPU LLC on auto?


----------



## mil777

Audioboxer said:


> Did you default the BIOS CPU settings or is PBO still turned on? CPU voltage and CPU LLC on auto?


I didn't default all the settings, but PBO is set to disabled.
CPU voltage is auto, but the LLC is set to 3 and some other settings that were in DRAM Calc under the "Best CPU/DRAM stability" like Current Capability, Frequency Switching etc. (do these things even make sense?)
But none of the settings actually overclock the CPU, I feel like this shouldn't be the reason a stress tool to just fail in the middle of the test while Karhu, MemTestPro, P95, OCCT, Realbench all work fine.

I'll try setting everything back to default except RAM timings and related voltages.



P.S. running TM5.exe from system disk didn't help


----------



## boldenc

@*mil777*

did you swap CPU's on that PC?


----------



## XPEHOPE3

mil777 said:


> I didn't default all the settings, but PBO is set to disabled.


Did you set it disabled in both menus? In "AMD overclocking" and "AMD CBS" under XFR Enhancement that is


----------



## Audioboxer

mil777 said:


> I didn't default all the settings, but PBO is set to disabled.
> CPU voltage is auto, but the LLC is set to 3 and some other settings that were in DRAM Calc under the "Best CPU/DRAM stability" like Current Capability, Frequency Switching etc. (do these things even make sense?)
> But none of the settings actually overclock the CPU, I feel like this shouldn't be the reason a stress tool to just fail in the middle of the test while Karhu, MemTestPro, P95, OCCT, Realbench all work fine.
> 
> I'll try setting everything back to default except RAM timings and related voltages.
> 
> 
> 
> P.S. running TM5.exe from system disk didn't help


LLC should really just be left on auto for CPU anyway, especially when using PBO. Default everything but RAM timings and voltage. Give that a go first. PBO on auto normally means default disabled.

You can always install Ryzen Master for monitoring only and when you load it up it will tell you what your CPU algorithm is running as (PBO, auto OC, default).

DRAM Calc is outdated anyway, not really suitable for newest gen CPUs. Some data or timings you can pull from it might still generally be OK, but you'll find better advice in this topic for where to start with settings, voltages and things. Believe it or not a lot of the settings you mentioned above are just best left on auto unless you genuinely need to change them.

I've learned when starting out seeking a baseline less is more, generally. The less you tweak and change when starting out in the bios the less of a headache you might have trying to find out what isn't stable.

Something is crashing your TM5 threads and it's about finding out what. CPU seems to be a big culprit from it happening to me and good advice in this topic suggesting that was the cause.


----------



## mil777

boldenc said:


> @*mil777*
> 
> did you swap CPU's on that PC?


PC was built last week with all new parts except CPU which I ran on a different board previously.



XPEHOPE3 said:


> Did you set it disabled in both menus? In "AMD overclocking" and "AMD CBS" under XFR Enhancement that is


Uhh, no. I thought it's enough to just disable it in one place. But according to Ryzen Master apparently disabling in one spot was enough.


Audioboxer said:


> LLC should really just be left on auto for CPU anyway, especially when using PBO. Default everything but RAM timings and voltage. Give that a go first. PBO on auto normally means default disabled.
> 
> You can always install Ryzen Master for monitoring only and when you load it up it will tell you what your CPU algorithm is running as (PBO, auto OC, default).
> 
> DRAM Calc is outdated anyway, not really suitable for newest gen CPUs. Some data or timings you can pull from it might still generally be OK, but you'll find better advice in this topic for where to start with settings, voltages and things. Believe it or not a lot of the settings you mentioned above are just best left on auto unless you genuinely need to change them.
> 
> I've learned when starting out seeking a baseline less is more, generally. The less you tweak and change when starting out in the bios the less of a headache you might have trying to find out what isn't stable.
> 
> Something is crashing your TM5 threads and it's about finding out what. CPU seems to be a big culprit from it happening to me and good advice in this topic suggesting that was the cause.


Ok so installed Ryzen Master, when running TM5 it says "OC Mode: Default", so I guess that means PBO is disabled.
I reverted the "stability" settings I previously mentioned to default, TM5 timed out after an hour anyway.

I only used DRAM Calc. for a baseline, the plan was to continue with DDR4 OC Guide so here I am.
The baseline was 12hr Karhu stable so I figured it saves lot of time than starting with much looser settings from the guide and spending like 2 days of testing just to get to the same place (or just spend those 2 days to get a stress testing tool to work lol).

As a last effort I'm going to completely reset the BIOS without even an XMP profile to see if this would run at safest settings possible.

Also I want to thank everyone for being so helpful and patient 😊


----------



## TimeDrapery

Spoiler






mongoled said:


> @domdtxdissar
> 
> Just confirming the logic you implied makes perfect sense
> 
> More RAM taken by OS means less RAM available for testing meaning TM5 takes less time to complete.
> 
> 
> 
> Now here is a completed 3800 [email protected], time taken to complete is where I would expect it to be.
> 
> Dilemma is ive ran out of things to optimise
> 
> 😄😄
> 
> Switching to 1T pushes tPHYRDL to 28 on both dimms, ive played with a ton of settings and cant get it to 26 when I use a combination of tCL @14 and Cmd2T @2T.
> 
> Anyone got any ideas that have yet to be discussed
> 
> 🤣🤣
> 
> @TimeDrapery
> PC had rebooted using 1.56 vdimm, upped it to 1.57v and voila
> 
> 
> 
> Going to run a few hours of Y-Cruncher ....
> 
> ** EDIT **
> After Y-Cruncher will change AddrCmdSetup to 56 with the others at 0 ...
> 
> Added Y-Cruncher, its not 7 hrs but around 5 1/2 as I accidently paused it ...
> 
> View attachment 2520860
> 
> 
> View attachment 2520815






@mongoled

NICE! Good to hear there's hope for the flat 14! The subsequent results you've shared are righteous!

I'm currently experimenting with the powering of my 4×8GB SR DIMMs in between running CoreCycler in order to refine (and better understand!) my Curve Optimizer configuration...
















Currently though... Grocery shopping 😂😂😂😂😂


----------



## umea

Got this done with some fiddling, is stable (ran 30 cycles of TM5 1usmus_v3), next step is to see if I can get 14 flat running and get rid of setup times...
Any advice on getting rid of setup times?


----------



## Sleepycat

umea said:


> View attachment 2521041
> 
> 
> Got this done with some fiddling, is stable (ran 30 cycles of TM5 1usmus_v3), next step is to see if I can get 14 flat running and get rid of setup times...
> Any advice on getting rid of setup times?


Not if you want to run 1T GDM off. It will likely not post if you reduce the setup times too much.


----------



## umea

What do setup times affect performance wise?


----------



## TimeDrapery

Spoiler






umea said:


> What do setup times affect performance wise?






@umea 

Well, setup timings affect memory performance (mainly) through the enhanced stability they provide when they're configured appropriately for your system and its components/configuration as well as your own goals

Setup timings aren't the same as many of the other timing parameters... For one, the values you're entering in the BIOS represent picoseconds as opposed to nanoseconds and, additionally, they're not representative of the duration of an event like most timing parameters are (instead they represent... Something like a "hold time"/"delay" to the IMC [like, "wait _x_ picoseconds and then send the read/write command"])

In my personal experience setup timings have been instrumental in stabilizing some of my better memory overclocks, especially those OCs where I run 4×8GB SR DIMMs... Like all the talk about tPHYDRL as of late, these setup timings help us to accommodate some of the idiosyncracies found amongst our various kits and mobos


----------



## mongoled

TimeDrapery said:


> @mongoled
> 
> NICE! Good to hear there's hope for the flat 14! The subsequent results you've shared are righteous!
> 
> I'm currently experimenting with the powering of my 4×8GB SR DIMMs in between running CoreCycler in order to refine (and better understand!) my Curve Optimizer configuration...
> View attachment 2521033
> 
> View attachment 2521032
> 
> Currently though... Grocery shopping 😂😂😂😂😂


Have you tested your dimms in sets, i.e. 2 x 8GB.

Coming from experience, it will save you time in the long run to work out what the dimms can do when they are in pairs as once you have worked out the weakest link (the worst tRCDRD @ a given frequency for a dimm/s) you then only need to concentrate on getting the powering of the dimms correct when you place all 4 dimms back into the system.

Unsure if you read it, but I managed to destroy one of my 4 sticks while getting the heatspreaders off so now I am running a two dimms that came from two different kits.

You can see they are different as the PCB is a slightly different color, though has been no obstacle in getting flat 14s and tRFC down to 228, obviously watercooling the dimms helps immensly.

So of the 4 dimms I had three could do tRCDRD @14/3800 while one could do it @ 15/3800.

Now have a total of 3 working dimms ....


----------



## Audioboxer

mil777 said:


> PC was built last week with all new parts except CPU which I ran on a different board previously.
> 
> 
> Uhh, no. I thought it's enough to just disable it in one place. But according to Ryzen Master apparently disabling in one spot was enough.
> 
> Ok so installed Ryzen Master, when running TM5 it says "OC Mode: Default", so I guess that means PBO is disabled.
> I reverted the "stability" settings I previously mentioned to default, TM5 timed out after an hour anyway.
> 
> I only used DRAM Calc. for a baseline, the plan was to continue with DDR4 OC Guide so here I am.
> The baseline was 12hr Karhu stable so I figured it saves lot of time than starting with much looser settings from the guide and spending like 2 days of testing just to get to the same place (or just spend those 2 days to get a stress testing tool to work lol).
> 
> As a last effort I'm going to completely reset the BIOS without even an XMP profile to see if this would run at safest settings possible.
> 
> Also I want to thank everyone for being so helpful and patient 😊


Yes, that means default. Reset your bios to default and run XMP memory settings, or run loose timings such as auto and put your FCLK/memory at the 1:1 settings you want. Probably 3800/1900.

First thing to do, check for WHEA errors under event manager logs to make sure you are OK running 1900 IF. If you have WHEA errors drop to 1800 IF and 3600 memory for now.

Once confirmed error free in regards to WHEA run this for 12 hours at least, so maybe try overnight Releases · sp00n/corecycler

Corecycler attempts to test cores individually at their highest frequencies, whereas some traditional CPU stability tests will hit all cores at once which isn't as useful for testing the way lighter load boosts work on Ryzen.

Trying to figure out if any of your cores are crashing even on default spec settings. I don't want to alarm or stress you at this point but I was helping someone on another forum who was having cores fail on a 5950x with corecycler even on default settings and they had to RMA the chip. Replacement worked fine.

If cores crash on default spec there are a few more things to try before panicking including reseating the CPU.


----------



## mil777

mil777 said:


> As a last effort I'm going to completely reset the BIOS without even an XMP profile to see if this would run at safest settings possible.


Just woke up to another failed test.
The CPU was running at 3.7Ghz baseclock, RAM was 2400 CL16 JEDEC timings, BIOS all default settings except I disabled PBO instead of leaving it on Auto.
It's safe to say there's no way to get this working on my machine so I'm giving up here.

Every other tool works fine (meaning they show errors if there are any, they don't "time out" mid-testing).
The PC doesn't crash/BSOD/reboot even with CPU overclocked and a bunch of random settings picked up from DRAM Calc. so I'll rather trust general stability and multiple programs than just a single one (which still hasn't thrown a single error regardless of failing to complete the test).




Audioboxer said:


> Yes, that means default. Reset your bios to default and run XMP memory settings, or run loose timings such as auto and put your FCLK/memory at the 1:1 settings you want. Probably 3800/1900.
> 
> First thing to do, check for WHEA errors under event manager logs to make sure you are OK running 1900 IF. If you have WHEA errors drop to 1800 IF and 3600 memory for now.
> 
> Once confirmed error free in regards to WHEA run this for 12 hours at least, so maybe try overnight Releases · sp00n/corecycler
> 
> Trying to figure out if any of your cores are crashing even on default spec settings. I don't want to alarm or stress you at this point but I was helping someone on another forum who was having cores fail on a 5950x with corecycler even on default settings and they had to RMA the chip. Replacement worked fine.


Was just typing this message above when you posted.
I doubt the CPU is crashing at base clock of 3.7 and 1200 IF. If that's the case then I would've had way more issues running it a whole GHz above that in other tests or games and that's just not what's going on.
I've been running WHEA-free 1900 IF since Zen3 release, but that doesn't matter since the program fails even at absolute minimum spec.

I'm starting to think it's a software compatibility issue since I did a fresh install just a few days ago, I don't know how else to explain it.
This is the only program that makes trouble and coincidentally it's the only abandoned program of the bunch.

And what do you mean by "5950X failing on default settings"? Do you mean at base clock like I tested here or just default boost?


----------



## TimeDrapery

Spoiler






mongoled said:


> Have you tested your dimms in sets, i.e. 2 x 8GB.
> 
> Coming from experience, it will save you time in the long run to work out what the dimms can do when they are in pairs as once you have worked out the weakest link (the worst tRCDRD @ a given frequency for a dimm/s) you then only need to concentrate on getting the powering of the dimms correct when you place all 4 dimms back into the system.
> 
> Unsure if you read it, but I managed to destroy one of my 4 sticks while getting the heatspreaders off so now I am running a two dimms that came from two different kits.
> 
> You can see they are different as the PCB is a slightly different color, though has been no obstacle in getting flat 14s and tRFC down to 228, obviously watercooling the dimms helps immensly.
> 
> So of the 4 dimms I had three could do tRCDRD @14/3800 while one could do it @ 15/3800.
> 
> Now have a total of 3 working dimms ....






@mongoled 

I did see that! RIP DIMM... The water-cooling setup looks awesome though, the tRFC is evidence enough of the performance benefits to me

Soon enough I'll take it apart and build out the custom loop

The Curve Optimizer makes me feel like a caveman, I've got such a large backlog of testing results to try and make sense of... I feel like I understand it so little that just throwing a billion different configurations at it and comparing the results after letting it run it's testing in an attempt to orient myself appropriately when adjusting the curve further is all that I can do 😂😂😂😂😂 I feel like the current config is doing alright so far although it's not performing as well in the OCCT benches I do recognize that I took it off "Motherboard" limits / 10× scalar and set them to Auto / Auto which likely accounts for the performance reduction as the CPU bench is surely a black hole in disguise, devouring all power available 😂😂😂😂😂

Some time ago I binned all my sticks independently and in pairs, I think I bought four 2×8GB SR kits and kept the ones that binned the best while the rest are sitting in timeout until they behave better... Somewhere around my Google or Microsoft is my spreadsheet detailing all of this...


----------



## mongoled

mil777 said:


> Just woke up to another failed test.
> The CPU was running at 3.7Ghz baseclock, RAM was 2400 CL16 JEDEC timings, BIOS all default settings except I disabled PBO instead of leaving it on Auto.
> It's safe to say there's no way to get this working on my machine so I'm giving up here.
> 
> Every other tool works fine (meaning they show errors if there are any, they don't "time out" mid-testing).
> The PC doesn't crash/BSOD/reboot even with CPU overclocked and a bunch of random settings picked up from DRAM Calc. so I'll rather trust general stability and multiple programs than just a single one (which still hasn't thrown a single error regardless of failing to complete the test).
> 
> 
> 
> Was just typing this message above when you posted.
> I doubt the CPU is crashing at base clock of 3.7 and 1200 IF. If that's the case then I would've had way more issues running it a whole GHz above that in other tests or games and that's just not what's going on.
> I've been running WHEA-free 1900 IF since Zen3 release, but that doesn't matter since the program fails even at absolute minimum spec.
> 
> I'm starting to think it's a software compatibility issue since I did a fresh install just a few days ago, I don't know how else to explain it.
> This is the only program that makes trouble and coincidentally it's the only abandoned program of the bunch.
> 
> And what do you mean by "5950X failing on default settings"? Do you mean at base clock like I tested here or just default boost?


This is what I would do.

Turn off PSU, remove CMOS battery, reset CMOS with jumper for a couple of minutes.

Remove CPU and RAM, make sure nothing that should not be there is not there i.e. hair, dirt, plastic etc etc.

Reseat components.

After this, insert battery back into motherboard

Have a pre-prepared USB flash drive with the latest BIOS and re-flash the BIOS, I could not see what motherboard you are using .....

Dont change any BIOS settings, leave everything on default settings.

Then do a clean Windows install, once this is completed, run a different system stress tester such as Realbench, Y-Cruncher etc etc and see if there are any instabilities with those applications.

If all is good start with a 10 cycle 1usmus TM5 profile, see if it "times out", 

Arghhhh, sorry, its not helpful you dont have a sig so we know what components you are running without having to search through your post history, not helpful at all as I was wanting to quickly see what RAM, PSU, mobo you had etc on the quick and and cant .........

Was going to go into next steps, please get a sig up !


----------



## mongoled

TimeDrapery said:


> @mongoled
> 
> I did see that! RIP DIMM... The water-cooling setup looks awesome though, the tRFC is evidence enough of the performance benefits to me
> 
> Soon enough I'll take it apart and build out the custom loop
> 
> The Curve Optimizer makes me feel like a caveman, I've got such a large backlog of testing results to try and make sense of... I feel like I understand it so little that just throwing a billion different configurations at it and comparing the results after letting it run it's testing in an attempt to orient myself appropriately when adjusting the curve further is all that I can do 😂😂😂😂😂 I feel like the current config is doing alright so far although it's not performing as well in the OCCT benches I do recognize that I took it off "Motherboard" limits / 10× scalar and set them to Auto / Auto which likely accounts for the performance reduction as the CPU bench is surely a black hole in disguise, devouring all power available 😂😂😂😂😂
> 
> Some time ago I binned all my sticks independently and in pairs, I think I bought four 2×8GB SR kits and kept the ones that binned the best while the rest are sitting in timeout until they behave better... Somewhere around my Google or Microsoft is my spreadsheet detailing all of this...


Well post up what those sticks can do



Re CO, you got to take into account differences in different BIOSs!

The BIOS im currently running is completly different to the previous BIOS with regards to CO and Scaler and what voltages gets pushed to what applications, saw a 150-200 point decrease in CB23 multicore that needs telemetry hacking to recover some of the performance, im hoping the next BIOS gets back to where the previous BIOS was....

I also run Scaler on AUTO, and have stopped using "Motherboard" limits and have gone back to manual PPT/TCD/EDC settings.

Alot to keep a lid on with each BIOS update !

Although ive destroyed hardware im not regretting the move to watercooling the RAM, yet ....


----------



## Audioboxer

mil777 said:


> Just woke up to another failed test.
> The CPU was running at 3.7Ghz baseclock, RAM was 2400 CL16 JEDEC timings, BIOS all default settings except I disabled PBO instead of leaving it on Auto.
> It's safe to say there's no way to get this working on my machine so I'm giving up here.
> 
> Every other tool works fine (meaning they show errors if there are any, they don't "time out" mid-testing).
> The PC doesn't crash/BSOD/reboot even with CPU overclocked and a bunch of random settings picked up from DRAM Calc. so I'll rather trust general stability and multiple programs than just a single one (which still hasn't thrown a single error regardless of failing to complete the test).
> 
> 
> 
> Was just typing this message above when you posted.
> I doubt the CPU is crashing at base clock of 3.7 and 1200 IF. If that's the case then I would've had way more issues running it a whole GHz above that in other tests or games and that's just not what's going on.
> I've been running WHEA-free 1900 IF since Zen3 release, but that doesn't matter since the program fails even at absolute minimum spec.
> 
> I'm starting to think it's a software compatibility issue since I did a fresh install just a few days ago, I don't know how else to explain it.
> This is the only program that makes trouble and coincidentally it's the only abandoned program of the bunch.
> 
> And what do you mean by "5950X failing on default settings"? Do you mean at base clock like I tested here or just default boost?


Poster I was helping 5950x optimisation advice

They mentioned stock/default so I just took that as the same position you find yourself in. Corecycler was still crashing on cores for them until they got another 5950x.

Fresh install of Windows could come next, but if there are still issues then I'd look at taking the CPU out, examining the pins and reseating it. Topic above wasn't about MemTest timing out, but because MemTest timing out is usually because of the CPU, something which I experienced myself, it just got me thinking about ways to make sure your CPU is indeed stable at default settings.

I was actually passing CoreCycler fine but one of my curve settings must have been right on the edge and light core workloads really are the most "brutal" way to fish out your final CPU instabilities. Such as desktop use and seeing random apps crash. Once I reduced my undervolt a bit on the curve TestMem has never timed out again for me so far. I got about 2 weeks of continuous use out of it before my GPU died and I'm currently waiting on my RMA to be delivered to rebuild my PC lol.

The longest I ran Corecycler non-stop was 24 hours but even the developer of that script has IIRC said something to the extent of even longer would be needed to really catch small instabilities. So, as even this topic will tell you desktop use/light core loads will really be the final piece of the puzzle to make sure one of these Ryzens on PBO/Curve is stable.

I hope it's nothing to do with your CPU, I'm just throwing all of this into the ring to give you something to try. TestMem obviously is an older app but lots of people, like those in this topic, use it for hundreds and hundreds of hours and never see it timeout. They're on B550/X570 motherboards, using the latest Ryzens and often with similiar memory so when the general thought is timing out is CPU related it probably usually is.


----------



## Audioboxer

mongoled said:


> Well post up what those sticks can do
> 
> 
> 
> Re CO, you got to take into account differences in different BIOSs!
> 
> The BIOS im currently running is completly different to the previous BIOS with regards to CO and Scaler and what voltages gets pushed to what applications, saw a 150-200 point decrease in CB23 multicore that needs telemetry hacking to recover some of the performance, im hoping the next BIOS gets back to where the previous BIOS was....
> 
> I also run Scaler on AUTO, and have stopped using "Motherboard" limits and have gone back to manual PPT/TCD/EDC settings.
> 
> Alot to keep a lid on with each BIOS update !
> 
> Although ive destroyed hardware im not regretting the move to watercooling the RAM, yet ....
> 
> 
> 
> View attachment 2521098
> View attachment 2521099
> View attachment 2521100


I'm tempted to watercool my RAM, but I'd need a 2 DIMM block. I believe they make them? Also I see you are a man of culture, performance > RGB.

Watercooling my RAM would mean some re-doing of my runs, but as much as I like to say I hate pipe bending, I guess there is something enjoyable about it. Especially when you "wing it" and manage to eyeball your bends 

I've got 3 rads in my current setup, 2x360 and 1x120, but I have spoke to a few people that said their D5 pumps had no issues operating with 3x360 rads, even rads of the restrictive variety (Corsair/HWLabs). I've got slim rads (most restrictive) and my biggest regret was not going thick, at least on the bottom. Though I am happy with my temps overall.


----------



## mongoled

Audioboxer said:


> I'm tempted to watercool my RAM, but I'd need a 2 DIMM block. I believe they make them? Also I see you are a man of culture, performance > RGB.
> 
> Watercooling my RAM would mean some re-doing of my runs, but as much as I like to say I hate pipe bending, I guess there is something enjoyable about it. Especially when you "wing it" and manage to eyeball your bends
> 
> I've got 3 rads in my current setup, 2x360 and 1x120, but I have spoke to a few people that said their D5 pumps had no issues operating with 3x360 rads, even rads of the restrictive variety (Corsair/HWLabs). I've got slim rads (most restrictive) and my biggest regret was not going thick, at least on the bottom. Though I am happy with my temps overall.


My main issue with regards to watercooling the RAM was attempting to create a bend between the CPU and RAM block, issue being its extremely difficult to get two bends in such a short amount of tube which resulted in undue tension at the RAM modules.

This was resulting in some weird TM5 issues where I was getting errors that indicated powering/overheating issues.

After I removed my attempt and decided to go with two 90 degree fittings with a straight tube those errors went away, not to mention me *hitting myself when attempting to hook up my curved tubing between the CPU and RAM block !

RGB is "pretty colours" nice for kids so I stick to just setting it to a white LED, saying that, should have got a RAM block with RGB

😀😀

Just get a 4 dimm RAM waterblock, its not like its going to go bad or worsen your performance and you are "future" proofed ....

Eye balling the bends is a good one, thats how I do most of mine


----------



## mil777

mongoled said:


> Spoiler
> 
> 
> 
> This is what I would do.
> Turn off PSU, remove CMOS battery, reset CMOS with jumper for a couple of minutes.
> Remove CPU and RAM, make sure nothing that should not be there is not there i.e. hair, dirt, plastic etc etc.
> Reseat components.
> After this, insert battery back into motherboard
> Have a pre-prepared USB flash drive with the latest BIOS and re-flash the BIOS, I could not see what motherboard you are using .....
> Dont change any BIOS settings, leave everything on default settings.
> Then do a clean Windows install, once this is completed, run a different system stress tester such as Realbench, Y-Cruncher etc etc and see if there are any instabilities with those applications.
> If all is good start with a 10 cycle 1usmus TM5 profile, see if it "times out",
> Arghhhh, sorry, its not helpful you dont have a sig so we know what components you are running without having to search through your post history, not helpful at all as I was wanting to quickly see what RAM, PSU, mobo you had etc on the quick and and cant .........
> Was going to go into next steps, please get a sig up !


The sig is now up, sorry!

I've just assembled the PC last week and keep in mind I'm very anal about these things so I clean everything thoroughly before installing and check socket/slots for debris, I even gently cleaned the contact pins on the RAM before inserting it.
Like I previously mentioned, the Windows install is as fresh as it gets. I've now spent more time trying to get TM5 to run than actually using the computer since the install.

The only things installed are like 3 monitoring tools and one game. There's no bloat, additional motherboard control or RGB software, everything is ran off a preconfigured Aquacomputer Quadro.
But I will definitely do an overnight CPU stress test first before I jump to draining and disassembling the loop I still have blisters from 😅

Also now that you've mentioned BIOS, looks like the version I flashed initially was the most recent one which I just checked is a Beta version (2420). 
I should probably go back to one version before that (2407).



Audioboxer said:


> Poster I was helping 5950x optimisation advice
> 
> They mentioned stock/default so I just took that as the same position you find yourself in. Corecycler was still crashing on cores for them until they got another 5950x.
> 
> Fresh install of Windows could come next, but if there are still issues then I'd look at taking the CPU out, examining the pins and reseating it. Topic above wasn't about MemTest timing out, but because MemTest timing out is usually because of the CPU, something which I experienced myself, it just got me thinking about ways to make sure your CPU is indeed stable at default settings.
> 
> I was actually passing CoreCycler fine but one of my curve settings must have been right on the edge and light core workloads really are the most "brutal" way to fish out your final CPU instabilities. Such as desktop use and seeing random apps crash. Once I reduced my undervolt a bit on the curve TestMem has never timed out again for me so far. I got about 2 weeks of continuous use out of it before my GPU died and I'm currently waiting on my RMA to be delivered to rebuild my PC lol.
> 
> The longest I ran Corecycler non-stop was 24 hours but even the developer of that script has IIRC said something to the extent of even longer would be needed to really catch small instabilities. So, as even this topic will tell you desktop use/light core loads will really be the final piece of the puzzle to make sure one of these Ryzens on PBO/Curve is stable.
> 
> I hope it's nothing to do with your CPU, I'm just throwing all of this into the ring to give you something to try. TestMem obviously is an older app but lots of people, like those in this topic, use it for hundreds and hundreds of hours and never see it timeout. They're on B550/X570 motherboards, using the latest Ryzens and often with similiar memory so when the general thought is timing out is CPU related it probably usually is.


Yeah I understand, I need to confirm my CPU is rock stable. It's just strange I don't have any instabilities popping up anywhere else, be it stress tools or general usage.
I still haven't tried CoreCycle which I definitely will do now but isn't that hammering the CPU with high load and this is probably a low load issue like you've just said?


----------



## Audioboxer

mongoled said:


> My main issue with regards to watercooling the RAM was attempting to create a bend between the CPU and RAM block, issue being its extremely difficult to get two bends in such a short amount of tube which resulted in undue tension at the RAM modules.
> 
> This was resulting in some weird TM5 issues where I was getting errors that indicated powering/overheating issues.
> 
> After I removed my attempt and decided to go with two 90 degree fittings with a straight tube those errors went away, not to mention me *hitting myself when attempting to hook up my curved tubing between the CPU and RAM block !
> 
> RGB is "pretty colours" nice for kids so I stick to just setting it to a white LED, saying that, should have got a RAM block with RGB
> 
> 😀😀
> 
> Just get a 4 dimm RAM waterblock, its not like its going to go bad or worsen your performance and you are "future" proofed ....
> 
> Eye balling the bends is a good one, thats how I do most of mine


I've got a 2 DIMM board though (Unify X) so I was worried it wouldn't fit properly. Will consider it when my GPU arrives and I get to test the memory I bought.

Yeah I don't mind the blocks having RGB, it's fans that tend to peform pretty poorly once RGB comes into the equation.



mil777 said:


> The sig is now up, sorry!
> 
> I've just assembled the PC last week and keep in mind I'm very anal about these things so I clean everything thoroughly before installing and check socket/slots for debris, I even gently cleaned the contact pins on the RAM before inserting it.
> Like I previously mentioned, the Windows install is as fresh as it gets. I've now spent more time trying to get TM5 to run than actually using the computer since the install.
> 
> The only things installed are like 3 monitoring tools and one game. There's no bloat, additional motherboard control or RGB software, everything is ran off a preconfigured Aquacomputer Quadro.
> But I will definitely do an overnight CPU stress test first before I jump to draining and disassembling the loop I still have blisters from 😅
> 
> Also now that you've mentioned BIOS, looks like the version I flashed initially was the most recent one which I just checked is a Beta version (2420).
> I should probably go back to one version before that (2407).
> 
> 
> Yeah I understand, I need to confirm my CPU is rock stable. It's just strange I don't have any instabilities popping up anywhere else, be it stress tools or general usage.
> I still haven't tried CoreCycle which I definitely will do now but isn't that hammering the CPU with high load and this is probably a low load issue like you've just said?


CoreCyler uses Prime95 but the script sets it up in a way where it only hammers 1 core at a time, so it's simulating "light" workloads on a single core which allows the CPU to boost that one core higher than an all-core workload boosts.


----------



## colkoni

Audioboxer said:


> I'm tempted to watercool my RAM, but I'd need a 2 DIMM block. I believe they make them? Also I see you are a man of culture, performance > RGB.
> 
> Watercooling my RAM would mean some re-doing of my runs, but as much as I like to say I hate pipe bending, I guess there is something enjoyable about it. Especially when you "wing it" and manage to eyeball your bends
> 
> I've got 3 rads in my current setup, 2x360 and 1x120, but I have spoke to a few people that said their D5 pumps had no issues operating with 3x360 rads, even rads of the restrictive variety (Corsair/HWLabs). I've got slim rads (most restrictive) and my biggest regret was not going thick, at least on the bottom. Though I am happy with my temps overall.


Same here, Ekwb has the acrylic topped ram block what i don't like, and the acetal is discontinued sadly. 

Now i have an cheap alseye ram cooler (10-15$)

Just for thought, meaby use soft tubing so If you need to reseat or change ram, you don't have to empty and refill.

Rad thickness won't do that mouch difference, more surface area with fans is lot better.


----------



## mongoled

colkoni said:


> Same here, Ekwb has the acrylic topped ram block what i don't like, and the acetal is discontinued sadly.
> 
> Now i have an cheap alseye ram cooler (10-15$)
> 
> Just for thought, meaby use soft tubing so If you need to reseat or change ram, you don't have to empty and refill.
> 
> Rad thickness won't do that mouch difference, more surface area with fans is lot better.


This no good for you ?









Alphacool D-RAM Cooler X4 Universal - Acetal Black Nickel


Mit den neuen Alphacool D-RAM Kühlern können nun alle beliebigen Speicherbausteine gekühlt werden. Dieser Kühlblock wird einfach auf die optional erhältlichen Kühlmodule oder auf vorhandene Heatspreader mit einem Lochabstand von 110mm...




www.aquatuning.de


----------



## mongoled

mil777 said:


> The sig is now up, sorry!
> 
> I've just assembled the PC last week and keep in mind I'm very anal about these things so I clean everything thoroughly before installing and check socket/slots for debris, I even gently cleaned the contact pins on the RAM before inserting it.
> Like I previously mentioned, the Windows install is as fresh as it gets. I've now spent more time trying to get TM5 to run than actually using the computer since the install.
> 
> The only things installed are like 3 monitoring tools and one game. There's no bloat, additional motherboard control or RGB software, everything is ran off a preconfigured Aquacomputer Quadro.
> But I will definitely do an overnight CPU stress test first before I jump to draining and disassembling the loop I still have blisters from 😅
> 
> Also now that you've mentioned BIOS, looks like the version I flashed initially was the most recent one which I just checked is a Beta version (2420).
> I should probably go back to one version before that (2407).
> 
> 
> Yeah I understand, I need to confirm my CPU is rock stable. It's just strange I don't have any instabilities popping up anywhere else, be it stress tools or general usage.
> I still haven't tried CoreCycle which I definitely will do now but isn't that hammering the CPU with high load and this is probably a low load issue like you've just said?


Thats better, where was I .....

Do your inital testing with no additonal software installed, though I highly doubt it has anything to do with that.

Reason for re-flashing the BIOS is and someone please correct me if what I am about to write is incorrect, but I suspect that CTR writes information to somewhere in the BIOS just like Ryzen Master does, hence the reason that you really need to wipe this info from the BIOS, just to make sure its not causing "hidden" issues.

As you got fixated on TM5 (understand and know that feeling  ) best to get some other stability testing out the way then move back onto the TM5 issue.

Now I know you are watercooled and running 4 x 8GB, which is very helpful to know



Do the things that have been mentioned and lets see if the other stress testing progs come back clean ....


----------



## Audioboxer

mongoled said:


> This no good for you ?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Alphacool D-RAM Cooler X4 Universal - Acetal Black Nickel
> 
> 
> Mit den neuen Alphacool D-RAM Kühlern können nun alle beliebigen Speicherbausteine gekühlt werden. Dieser Kühlblock wird einfach auf die optional erhältlichen Kühlmodule oder auf vorhandene Heatspreader mit einem Lochabstand von 110mm...
> 
> 
> 
> 
> www.aquatuning.de


x4 I believe is for 4 DIMMS, it's the x2 I need which seems to be harder to find due to possibly being discontinued. Aliexpress has other brands for x2, and I guess a lower end brand for something like RAM cooling won't be as big a risk as using unbranded CPU/GPU blocks.


----------



## Hale59

colkoni said:


> Same here, Ekwb has the acrylic topped ram block what i don't like, and the acetal is discontinued sadly.
> 
> Now i have an cheap alseye ram cooler (10-15$)
> 
> Just for thought, meaby use soft tubing so If you need to reseat or change ram, you don't have to empty and refill.
> 
> Rad thickness won't do that mouch difference, more surface area with fans is lot better.


Beware, if it is a 2 DIMM board, like, for example, the Unify X, you can use the EK-RAM Monarch X2. But it won't work with a board with 4 DIMM slots.

How far and wide are you looking for the EK-RAM Monarch X2? Because I found it for sale:
1 -





EKWB EK-RAM Monarch X2 Waterblock, Nickel/Acetal


EKWB EK-RAM Monarch X2 Waterblock, Nickel/Acetal



www.mmadld.top





2 - EKWB EK-RAM Monarch X2 Waterblock, Nickel/Acetal

@Audioboxer


----------



## mongoled

Audioboxer said:


> x4 I believe is for 4 DIMMS, it's the x2 I need which seems to be harder to find due to possibly being discontinued. Aliexpress has other brands for x2, and I guess a lower end brand for something like RAM cooling won't be as big a risk as using unbranded CPU/GPU blocks.


Thats why I said previously to get the X4 for "future proofing" and was more for @colkoni who was looking for black acetal


----------



## XPEHOPE3

@mil777 
What Power Reporting Deviation from HWiNFO64 do you see on average during TM5 run?


----------



## mil777

XPEHOPE3 said:


> @mil777
> What Power Reporting Deviation from HWiNFO64 do you see on average during TM5 run?


Here, I did a bit more testing to see how it behaves in other programs. Runs were approx. 10 mins each.


Spoiler



TM5








Karhu








HCI MemTest








OCCT Memory








CinebenchR20 1 run








Realbench











Timers were always reset after the tests were started and before they were stopped because idle values jump around quite a bit.


----------



## PJVol

mongoled said:


>


Is it just me, or the videocard's PCB is bent down notiecably on the right side?


----------



## mongoled

PJVol said:


> Is it just me, or the videocard's PCB is bent down notiecably on the right side?


Yup that's correct, gpu "sag"


----------



## XPEHOPE3

mil777 said:


> TM5


That means CPU draws 16.4% less power than shown in HWiNFO (PPT) causing it to underperform. Maybe CPU (or memory) doesn't receive enough current for that load. If you haven't given up on this, probably you can determine what core fails (via HWiNFO average effective clock after you see premature ending on otherwise idle PC) and raise its CO.
Also I remember that changing some timings (at 3800-14, vSOC 1.2V, VDIMM 1.54, tRRDS 7->6, tWRRD 6->5) allowed me to finish TM5 (although with errors). Also lowering VDIMM helped (on tRRDS 6 and 7, tWRRD 5, VDIMM 1.53). On easier to run RAM settings I didn't get that problem though (3866-16, vSOC 1.13, vDIMM 1.53).
TLDR: I'd try to raise some voltages for that TM5 problem since your Power Reporting Deviation >100%


----------



## PJVol

XPEHOPE3 said:


> That means CPU draws 16.4% less power than shown in HWiNFO (PPT) causing it to underperform


IMHO, TM5 is not heavy enough allcore load to judge deviation accuracy. According to CB data, MB actually underreporting a bit, but not so much to worry about.
Mine btw reports exactly the same 110W under tm5.


----------



## mil777

XPEHOPE3 said:


> That means CPU draws 16.4% less power than shown in HWiNFO (PPT) causing it to underperform. Maybe CPU (or memory) doesn't receive enough current for that load. If you haven't given up on this, probably you can determine what core fails (via HWiNFO average effective clock after you see premature ending on otherwise idle PC) and raise its CO.
> Also I remember that changing some timings (at 3800-14, vSOC 1.2V, VDIMM 1.54, tRRDS 7->6, tWRRD 6->5) allowed me to finish TM5 (although with errors). Also lowering VDIMM helped (on tRRDS 6 and 7, tWRRD 5, VDIMM 1.53). On easier to run RAM settings I didn't get that problem though (3866-16, vSOC 1.13, vDIMM 1.53).
> TLDR: I'd try to raise some voltages for that TM5 problem since your Power Reporting Deviation >100%


It would be very difficult to catch a failing thread since TM5 drops load across all cores inbetween cycles and that's probably when it happens (if it's a CPU problem).
I'm going to try CoreCycler for that.
Running TM5 with a CTR overclock lowered the average deviation to 108%. 116% was all default, no PBO.

It's strange that changing RAM timing and voltages is what allowed you to finish TM5.
Isn't the entire point of the program to find RAM instability and report it, not stop testing without warning the user?
Even if I have a CPU problem, this is a poor implementation of how to handle it, there should be at least something dumped in the log.

Also I flashed a prior version of BIOS, no changes.


----------



## KILO_17

Hello all! I have been reading through this thread and forum and have been picking up loads of helpful information. Recently moved from a 3700x to a 5900x while using the same RAM. From what I've gathered from my brief reading here for some the grail is 3800/1900 flat 14's. My current timings I feel are relatively stable after 1 hr of OCCT AVX and SSE stress tests, and 1100% memtestpro all error free. These are all with PBO disabled and no OC, working to stabilize RAM timings before tackling PBO/CO. 

My question for all of you is are there any additional timings/impedance values/voltages that I should change to increase stability for these timings (flat 16's) and for this 4 x SR DIMM configuration? May give 14's a shot if there is nothing else to tighten with the current timings.

Also, after playing around in BIOS, how do you MSI guys change the various RZQ values (please pardon the ignorance)? The values that are available are 60, 180 ohm, etc, I have no idea how to get the various 7/3/3 values other members here are getting. 

Any and all feed back is welcome.











-Cheers


----------



## Mach3.2

KILO_17 said:


> Also, after playing around in BIOS, how do you MSI guys change the various RZQ values (please pardon the ignorance)? The values that are available are 60, 180 ohm, etc, I have no idea how to get the various 7/3/3 values other members here are getting.


The value for RZQ/7 is actually *240*/7=34.28, which is rounded off to 34 ohm in MSI's BIOS.


----------



## colkoni

Hale59 said:


> Beware, if it is a 2 DIMM board, like, for example, the Unify X, you can use the EK-RAM Monarch X2. But it won't work with a board with 4 DIMM slots.
> 
> How far and wide are you looking for the EK-RAM Monarch X2? Because I found it for sale:
> 1 -
> 
> 
> 
> 
> 
> EKWB EK-RAM Monarch X2 Waterblock, Nickel/Acetal
> 
> 
> EKWB EK-RAM Monarch X2 Waterblock, Nickel/Acetal
> 
> 
> 
> www.mmadld.top
> 
> 
> 
> 
> 
> 2 - EKWB EK-RAM Monarch X2 Waterblock, Nickel/Acetal
> 
> @Audioboxer


Hmm... Are you sure these linked stores are legit ? they are the *same* site and can't find any information about them.


----------



## Bezcit

KILO_17 said:


> I have no idea how to get the various 7/3/3 values other members here are getting.


It´s easy. The base value is 240, and RZQ/something are the dividers. So for example, 40ohm is RZQ/6, because 240:40=6. and RZQ/3 is 80ohm, because 240:3=80. Etc


----------



## thomasck

Hi boys all good? I've upgraded from the taichi x370 + 3900X @ 3733CL15 which were working flawlessly for almost two years to a 5900X + Unify-X and kept the RAM because it is on the mobo's QVL, its a Predator 4000 CL19 which is running under the timings below. The question is, is there anywhere there that I can improve or timings that don't make sense? ZenTimings and Aida bench are below. Thanks for any input.
5900X totally stock and pbo off.
Ram is set to 1.46V, sock to 1.080mV, vddp 0.900mv, vddg and iod to 0.950mv. No WHEA errors.


----------



## XPEHOPE3

mil777 said:


> Isn't the entire point of the program to find RAM instability and report it, not stop testing without warning the user?


That one bug it doesn't catch, but it is admittedly rare.


mil777 said:


> since TM5 drops load across all cores inbetween cycles and that's probably when it happens


No, it happens otherwise. During one of the tests before test #15 one of the thread crashes and some memory gets freed. After that tests up until test #15 pass faster than they usually do (because of lesser dataset), and some other threads may also die. Then after test #15 all memory is released but TM5 fails to allocate new memory (presumably because of dead threads) and waits forever. I wrote an automation script to catch things like that. You can use this script to know on what test exactly does it fail. If it fails *on the same test all the time*, you can try using these error descriptions to maybe fix something in voltages/resistances/timings. If you are a programmer you can also try to alter the script so that it restarts TM5 if it fails prematurely to simulate a 25-cycle run or automate learning on what tests thread crash.


----------



## PJVol

thomasck said:


> Hi boys all good


Hi again! 
I'd try trtp/twr 6/12
But something else may need to be corrected, as [email protected] on 2ccd zen3 should give 53-54ns.

PS: Just for thought, too low IOD may potentially be the cause of some specific and annoying bugs.


----------



## KILO_17

Bezcit said:


> It´s easy. The base value is 240, and RZQ/something are the dividers. So for example, 40ohm is RZQ/6, because 240:40=6. and RZQ/3 is 80ohm, because 240:3=80. Etc





Mach3.2 said:


> The value for RZQ/7 is actually *240*/7=34.28, which is rounded off to 34 ohm in MSI's BIOS.


Wow that simple, thank you both!

So for a given target for a lower ProcODT (< 43 ohm), it would stand to reason to have these values greater thus using lower impedance values? Is that the goal? Sorry for my noobishness.


----------



## TimeDrapery

Spoiler






KILO_17 said:


> Wow that simple, thank you both!
> 
> So for a given target for a lower ProcODT (< 43 ohm), it would stand to reason to have these values greater thus using lower impedance values? Is that the goal? Sorry for my noobishness.






That's the general idea, take your VDIMM into account when configuring your RTTs as that's an important element of optimizing the powering of your memory during overclocking


----------



## thomasck

PJVol said:


> Hi again!
> I'd try trtp/twr 6/12
> But something else may need to be corrected, as [email protected] on 2ccd zen3 should give 53-54ns.
> 
> PS: Just for thought, too low IOD may potentially be the cause of some specific and annoying bugs.


Hello fellow Taichi user!  All good with you?
Fine, I will try your suggestion! What about the IOD? What do you recommend? I thought that could be same as VDDG CCD.


----------



## PJVol

thomasck said:


> All good with you?
> Fine, I will try your suggestion! What about the IOD? What do you recommend? I thought that could be same as VDDG CCD.


Still alive, thanks! ))
As for IOD, 1- and 2-chiplet cpu's may differ regarding their response to vddg voltages, though the exact picture is still mute for me. But it would be safe to assume 0.95-1.00 and 1.00-1.05 for the CCD and IOD respectively.
Anyway, afaik, low IOD can cause some issues with usb powering, and I heard some had problems with sound, so they are easier to detect, wheras CCD bus/ifops issues are not clear for me yet. Hope, next revision or whatever comes between zen 3 and 4 won't have that buggy glofo die.


----------



## KILO_17

TimeDrapery said:


> That's the general idea, take your VDIMM into account when configuring your RTTs as that's an important element of optimizing the powering of your memory during overclocking


That makes sense, will do. Thank you. 

Is there a general rule to follow in stepping them up down? ie along the lines of cldo VDDP / VDDG CCD / VDDG IOD / VSOC - 0.900 / 0.950 / 1.000 / 1.050 / 1.100 etc?


----------



## TimeDrapery

Spoiler






KILO_17 said:


> That makes sense, will do. Thank you.
> 
> Is there a general rule to follow in stepping them up down? ie along the lines of cldo VDDP / VDDG CCD / VDDG IOD / VSOC - 0.900 / 0.950 / 1.000 / 1.050 / 1.100 etc?






@KILO_17 

Yes, it differs by generation... The way Zen 3 is said to like it is with a 40 (80 / 120 / etc.) mV stepping

So this looks something like...

CLDO VDDP ---> 900mV
VDDG IOD ---> 980mV
VDDG IOD ---> 1060mV
VSOC ---> 1150mV (it doesn't appear that VSOC is bound to a precise 40mV stepping... Obviously none of them are truly "bound" to this pattern, consensus is that VDDGs and VDDP seem to perform best when they adhere to it though)

I tend to find myself running a higher VSOC than if I'd followed the 40mV stepping pattern... I'm not quite sure why as of yet (perhaps because I think it looks cool in ZenTimings 😂😂😂😂😂)...


----------



## KedarWolf

This is what works for me. TM5 stable running Usmus overnight at 1000%.


----------



## KILO_17

TimeDrapery said:


> Spoiler
> 
> 
> 
> CLDO VDDP ---> 900mV
> VDDG IOD ---> 980mV
> VDDG IOD ---> 1060mV
> VSOC ---> 1150mV (it doesn't appear that VSOC is bound to a precise 40mV stepping... Obviously none of them are truly "bound" to this pattern, consensus is that VDDGs and VDDP seem to perform best when they adhere to it though)
> 
> 
> I tend to find myself running a higher VSOC than if I'd followed the 40mV stepping pattern... I'm not quite sure why as of yet (perhaps because I think it looks cool in ZenTimings 😂😂😂😂😂)...


Nice thanks for the example. I'll give the + 40/80/120 mV as try. I keep getting WHEA 19's if VDDG CCD is <1000 mV.

I'll shoot for: 

CLDO VDDP -- 900 mV
VDDG CCD -- 1040 mV
VDDG IOD -- 1080 mV
VSOC -- 1120 mV 

I've ready here that stepping up VSOC a click or two should also stabilize against WHEA 19.


----------



## TimeDrapery

Spoiler






KILO_17 said:


> Nice thanks for the example. I'll give the + 40/80/120 mV as try. I keep getting WHEA 19's if VDDG CCD is <1000 mV.
> 
> I'll shoot for:
> 
> CLDO VDDP -- 900 mV
> VDDG CCD -- 1040 mV
> VDDG IOD -- 1080 mV
> VSOC -- 1120 mV
> 
> I've ready here that stepping up VSOC a click or two should also stabilize against WHEA 19.






@KILO_17

Looking good, looking good... I'd run 1125mV VSOC but that's not grounded in evidence, just my OCD 😂😂😂😂😂

"_I've ready here that stepping up VSOC a click or two should also stabilize against WHEA 19._"

Yessir, I've read this here as well although my solution to the flood was too reduce memory and fabric clocks to 3800 MT/s and 1900MHz respectively as the resolution otherwise isn't quite established as of yet by AMD (wouldn't it be nice? Maybe... Just maybe... it would even still be nice even if they don't bother fixing whatever the proximate cause of the issues is but did deliver an in-depth, detailed explanation of the issue... Yeah right 😂😂😂😂😂) or the community

Let us know how it's going for you!!!

*EDIT*: I just remembered another tidbit of free chicken that may be of help...

VDDG/VDDPs are "_*set*_" voltages (meaning that if you want to run 900mV then you enter 900 in the relevant field within the BIOS and leave it at that regardless of what's reported by monitoring software while in the OS)

VSOC is a "_*get*_" voltage (meaning that if you're going to run 1125mV then you'll adjust loadline calibration(s) (LLC) and/or the voltage you're requesting via override/offset within the BIOS so that monitoring software reports the VSOC you want to run, whilst under a workload, when you're in the OS)

For example, in this ZenTimings of mine ... 








you can see that ZenTimings reports VSOC as 1.175V and the others as they are depicted in the screenshot

However, my VDDGs/VDDP are set, in the AMD Overclocking submenu within the BIOS, to: 900/980/1060

Whereas my VSOC is set to 1181mV in the AMD Overclocking submenu within the BIOS and my VCORE SOC LLC is set to "Turbo" in order to maintain that 1.175V reading regardless of work being performed (obviously true voltage fluctuates throughout the time the PC is turned on however I believe these fluctuations are slight enough to not lose sleep over)

Hopefully that's of some help to you as well


----------



## boldenc

Guys, who ever had WHEA error regarding Error Type: Bus/Interconnect Error Source: Machine Check Exception at 1900FCLK, had a chance to stabilize it?
I have tried vSOC up to 1.125v and VDDG CCD up to 0.980v. Should I try more or don't put much hope ?


----------



## KILO_17

TimeDrapery said:


> Spoiler
> 
> 
> 
> @KILO_17
> 
> Looking good, looking good... I'd run 1125mV VSOC but that's not grounded in evidence, just my OCD 😂😂😂😂😂
> 
> "_I've ready here that stepping up VSOC a click or two should also stabilize against WHEA 19._"
> 
> Yessir, I've read this here as well although my solution to the flood was too reduce memory and fabric clocks to 3800 MT/s and 1900MHz respectively as the resolution otherwise isn't quite established as of yet by AMD (wouldn't it be nice? Maybe... Just maybe... it would even still be nice even if they don't bother fixing whatever the proximate cause of the issues is but did deliver an in-depth, detailed explanation of the issue... Yeah right 😂😂😂😂😂) or the community
> 
> 
> 
> Let us know how it's going for you!!!
> 
> *EDIT*: I just remembered another tidbit of free chicken that may be of help...
> 
> VDDG/VDDPs are "_*set*_" voltages (meaning that if you want to run 900mV then you enter 900 in the relevant field within the BIOS and leave it at that regardless of what's reported by monitoring software while in the OS)
> 
> VSOC is a "_*get*_" voltage (meaning that if you're going to run 1125mV then you'll adjust loadline calibration(s) (LLC) and/or the voltage you're requesting via override/offset within the BIOS so that monitoring software reports the VSOC you want to run, whilst under a workload, when you're in the OS)
> 
> For example, in this ZenTimings of mine ...
> View attachment 2521270
> 
> you can see that ZenTimings reports VSOC as 1.175V and the others as they are depicted in the screenshot
> 
> However, my VDDGs/VDDP are set, in the AMD Overclocking submenu within the BIOS, to: 900/980/1060
> 
> Whereas my VSOC is set to 1181mV in the AMD Overclocking submenu within the BIOS and my VCORE SOC LLC is set to "Turbo" in order to maintain that 1.175V reading regardless of work being performed (obviously true voltage fluctuates throughout the time the PC is turned on however I believe these fluctuations are slight enough to not lose sleep over)
> 
> Hopefully that's of some help to you as well


Thank you for the extensive feedback! Thank you for the SET/GET tidbits. Upon entering the various voltages, I thought I was going insane punching in VSOC just to see ZenTimings reporting 1.100 V. 

Also, I can only speak for my mobo, but I don't get VSOC +/- 0.005 V granularity. I tried entering 1.125 but it will only take 1.120 (OCD triggered). After trying to test 1.120 V I got a WHEA19 while memtest was loading threads.

Running memtest now w/VSOC at 1.130 V and let it run overnight while I'm work haha. 

Cheers!


----------



## KILO_17

boldenc said:


> Guys, who ever had WHEA error regarding Error Type: Bus/Interconnect Error Source: Machine Check Exception at 1900FCLK, had a chance to stabilize it?
> I have tried vSOC up to 1.125v and VDDG CCD up to 0.980v. Should I try more or don't put much hope ?


I was able to run WHEA19 free at IF 1900 (stable 1 hour OCCT SSE/AVX2 and memtestpro 1000%) but had to use the following:

cLDO VDDP -- 0.900 V
VDDG CCD = VDDG IOD -- 1.050 V 
VSOC -- 1.100 V (VSOC LLC 3)

Perhaps give these a try? Let us know how it works out for you.


----------



## glnn_23

Sold my 5700g and back with a 5950x


----------



## boldenc

KILO_17 said:


> I was able to run WHEA19 free at IF 1900 (stable 1 hour OCCT SSE/AVX2 and memtestpro 1000%) but had to use the following:
> 
> cLDO VDDP -- 0.900 V
> VDDG CCD = VDDG IOD -- 1.050 V
> VSOC -- 1.100 V (VSOC LLC 3)
> 
> Perhaps give these a try? Let us know how it works out for you.


Unfortunately didn't work, rebooted with whea error during game.


----------



## boldenc

it looks vSOC helped, still testing. it is currently set to 1.1875v.
no crashes no whea errors. Is that voltage fine for 24/7 ?


----------



## mongoled

glnn_23 said:


> Sold my 5700g and back with a 5950x
> 
> View attachment 2521298


Are you watercooling the dimms ?

Very low ambient temps ?


----------



## glnn_23

mongoled said:


> Are you watercooling the dimms ?
> 
> Very low ambient temps ?


No water but do have a 120mm fan over them. Ambient might have been around 14C.


----------



## Mach3.2

boldenc said:


> no crashes no whea errors. Is that voltage fine for 24/7 ?











AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




vSOC maxes out at 1.3V, but I haven't seen anyone talk about negative effects of high vSOC. Personally I'm not comfortable going above 1.2V for 24/7 settings


----------



## mongoled

glnn_23 said:


> No water but do have a 120mm fan over them. Ambient might have been around 14C.


That explains the low temps thanks!

@Mach3.2 
Ive used 1.25v for testing over a period of several days, nothing bad happened, but obviouly the duration of time is not very long ...


----------



## Mach3.2

mongoled said:


> @Mach3.2
> Ive used 1.25v for testing over a period of several days, nothing bad happened, but obviouly the duration of time is not very long ...


I also tried 1.26V while briefly testing 1933MHz FCLK, but 1933MHZ FCLK is a total no go, can't eliminate the WHEAs even with 1.26V SET vSOC, so I went back to 1866MHz FLCK.

Still, it remains to be seen whether the IMC can deteriorate with too high vSOC for 24/7 operations.


----------



## Audioboxer

Somewhat related due to VSOC discussion above, but am I right to say using a higher VSOC can eat into Ryzen CPU boosting/clock speeds due to the power share between RAM and CPU?

Or have I got that wrong/confused?

My 3600C14 bdie is due to arrive on Thursday, but still waiting on my GPU as its stuck in customs just now  Hopefully by the end of this week I've got my main rig back up and running lol.


----------



## XPEHOPE3

Audioboxer said:


> am I right to say using a higher VSOC can eat into Ryzen CPU boosting/clock speeds due to the power share between RAM and CPU?


You are.


----------



## Bruizer

@Veii or anyone, any thoughts on why if I change cl from 14 to 15 my computer won't boot into bios or windows, just throws code 22 on my Asus Dark Hero.

Also, does anything look wrong/out of place with these timings/settings (vdimm is 1.45)? Recently changed RTT from 7/3/1 to 6/3/3, lowered ProcODT from 43 to 36.9, and raised ClkDrvStr to 40.


----------



## KILO_17

boldenc said:


> Unfortunately didn't work, rebooted with whea error during game.


Damn, sorry to hear. Based on what I've read here those settings pretty weird from the convention here.

Edit: The VDDG CCD/IOD stepping and VSOC's resulted free of errors after running memtest overnight to approx 1400%. Thank you all for the input and recommendations.


----------



## Audioboxer

Bruizer said:


> @Veii or anyone, any thoughts on why if I change cl from 14 to 15 my computer won't boot into bios or windows, just throws code 22 on my Asus Dark Hero.
> 
> Also, does anything look wrong/out of place with these timings/settings (vdimm is 1.45)? Recently changed RTT from 7/3/1 to 6/3/3, lowered ProcODT from 43 to 36.9, and raised ClkDrvStr to 40.
> 
> View attachment 2521339


Try autoing out the right hand side with tCL 15 and see if it boots, or go back to the 7/3/1 and 24/20/24/24. Might be a resistance issue.

If you can get it booting then you can go from there if there is some instability that needs worked on.

Is 14 unstable or do you just want to try flat 15?


----------



## Bruizer

Audioboxer said:


> Try autoing out the right hand side with tCL 15 and see if it boots, or go back to the 7/3/1 and 24/20/24/24. Might be a resistance issue.
> 
> If you can get it booting then you can go from there if there is some instability that needs worked on.
> 
> Is 14 unstable or do you just want to try flat 15?


14 was actually stable based on my tests (Tm5 anta777 extreme, OCCT) but I had issues with BFV crashing and remembered Veii telling me once that it would probably be better to just run cl15. So you can imagine the surprise when i loosened it to 15 to do some testing and it wouldn't boot.


----------



## paih85

Bruizer said:


> @Veii or anyone, any thoughts on why if I change cl from 14 to 15 my computer won't boot into bios or windows, just throws code 22 on my Asus Dark Hero.
> 
> Also, does anything look wrong/out of place with these timings/settings (vdimm is 1.45)? Recently changed RTT from 7/3/1 to 6/3/3, lowered ProcODT from 43 to 36.9, and raised ClkDrvStr to 40.
> 
> View attachment 2521339


try trdwr/twrrd = 10/3


----------



## Audioboxer

Bruizer said:


> 14 was actually stable based on my tests (Tm5 anta777 extreme, OCCT) but I had issues with BFV crashing and remembered Veii telling me once that it would probably be better to just run cl15. So you can imagine the surprise when i loosened it to 15 to do some testing and it wouldn't boot.


A game crashing might be unstable GPU/CPU overclock rather than memory, but if you can get 15 booting you can obviously test that.

It might be one of your secondary timings that needs to be altered with 15, I was just guessing resistances.


----------



## Veii

Bruizer said:


> 14 was actually stable based on my tests (Tm5 anta777 extreme, OCCT) but I had issues with BFV crashing and remembered Veii telling me once that it would probably be better to just run cl15. So you can imagine the surprise when i loosened it to 15 to do some testing and it wouldn't boot.


tCWL 15, will show tCL 14 being -1
Dual rank requires +2 on tRDWR
soo when tCWL ≠ tCL , but -1 
then tRDWR needs to be +1

This change and it will post
IOD is only 30mV behind SOC
Increase SOC slightly or fix loadline
Likely run 1.125v soo loadline drops to 1.1 flat


----------



## Bruizer

Veii said:


> tCWL 15, will show tCL 14 being -1
> Dual rank requires +2 on tRDWR
> soo when tCWL ≠ tCL , but -1
> then tRDWR needs to be +1
> 
> This change and it will post
> IOD is only 30mV behind SOC
> Increase SOC slightly or fix loadline
> Likely run 1.125v soo loadline drops to 1.1 flat


So if I stick with 14 cl, should tRDWR be 9 or 10? If cl 15 what should it be?

And I'm a little confused on tCWL. Should it be equal to tCL ideally? Thank you for your patience!


----------



## boldenc

new windows improved a bit the latency
regarding the L3 , what should I try to improve the L3 cache scores ?















scores and latency ?


----------



## TimeDrapery

Spoiler






Bruizer said:


> So if I stick with 14 cl, should tRDWR be 9 or 10? If cl 15 what should it be?
> 
> And I'm a little confused on tCWL. Should it be equal to tCL ideally? Thank you for your patience!






@Bruizer

If you keep tCL at 14 then try setting tCWL to 14, tRDWR to 8, and tWRRD to 3

If you set tCL to 15 then try setting tCWL to 14, tRDWR to 9, and tWRRD to 2

Regarding what tCWL should be set to ... Experiment and see what performs best for your system

If you set tCWL lower than tCL it's probably easiest to set tRDWR and tWRRD to Auto and see what values pop up in ZenTimings for you


----------



## Audioboxer

Bruizer said:


> So if I stick with 14 cl, should tRDWR be 9 or 10? If cl 15 what should it be?
> 
> And I'm a little confused on tCWL. Should it be equal to tCL ideally? Thank you for your patience!


Put it on 9 for 15.

8 is fine for 14 if it boots and is stable. Otherwise 10.

I believe that's about right... lol.


boldenc said:


> new windows improved a bit the latency
> regarding the L3 , what should I try to improve the L3 cache scores ?
> 
> View attachment 2521399
> View attachment 2521400
> scores and latency ?


Have you tried your SCLs on 4 instead of 5?


----------



## mil777

I think I finally solved my TM5 issue, just managed to do 2 successful runs in a row.

So basically I was looking at CPU being unstable/broken because that's what most people recommended, so I ran CoreCycler overnight at all default settings and the next morning I woke up to this:


Spoiler: CoreCycler Performance Counter error














At first I thought this is a CPU error, but as it turns out the author responded here that it's a Windows issue.
The similarity of issues that I had both in TM5 and CoreCycler was so strange (both "timing out" without actually throwing errors on the CPU or the RAM) so I thought this is the same problem that's killing TM5.
There's is a .bat file that comes with CoreCycler under the "tools" folder that is supposed to fix this automatically but I manually reset the Windows Performance Counter just to be sure and then reran CoreCycler, but this time with both CPU and RAM overclock which didn't show instability in 15 hours.

Then I proceeded to run TM5 again and I was finally able to finish the test without timing out, this was a second run:









Still can't believe this is how I fixed it, accidentally by trying to fix another program.
Maybe it's a bit early to judge, but before doing this I could never finish a single 25 cycle run and now it did two consecutive runs.
I hope this can be helpful to others if they encounter this bug.


----------



## Audioboxer

mil777 said:


> I think I finally solved my TM5 issue, just managed to do 2 successful runs in a row.
> 
> So basically I was looking at CPU being unstable/broken because that's what most people recommended, so I ran CoreCycler overnight at all default settings and the next morning I woke up to this:
> 
> 
> Spoiler: CoreCycler Performance Counter error
> 
> 
> 
> 
> View attachment 2521416
> 
> 
> 
> At first I thought this is a CPU error, but as it turns out the author responded here that it's a Windows issue.
> The similarity of issues that I had both in TM5 and CoreCycler was so strange (both "timing out" without actually throwing errors on the CPU or the RAM) so I thought this is the same problem that's killing TM5.
> There's is a .bat file that comes with CoreCycler under the "tools" folder that is supposed to fix this automatically but I manually reset the Windows Performance Counter just to be sure and then reran CoreCycler, but this time with both CPU and RAM overclock which didn't show instability in 15 hours.
> 
> Then I proceeded to run TM5 again and I was finally able to finish the test without timing out, this was a second run:
> View attachment 2521417
> 
> 
> Still can't believe this is how I fixed it, accidentally by trying to fix another program.
> Maybe it's a bit early to judge, but before doing this I could never finish a single 25 cycle run and now it did two consecutive runs.
> I hope this can be helpful to others if they encounter this bug.


It's funny where a path can lead you down at times but I'm really happy CoreCycler brought you to the solution and it thankfully wasn't any sort of problem with your CPU!


----------



## boldenc

Audioboxer said:


> Have you tried your SCLs on 4 instead of 5?


SCLs improved the performance but unfortunately it will crash TM5 instantly with thread errors. I tried more vdimm up to 1.45v but still crashed.


----------



## Audioboxer

boldenc said:


> SCLs improved the performance but unfortunately it will crash TM5 instantly with thread errors. I tried more vdimm up to 1.45v but still crashed.
> 
> View attachment 2521418


Try dropping AddrCmdDrvStr down to 20 and see if it makes any difference. Then simply as a one off, try voltage a bit nearer to 1.5 and see if it makes a difference.

I've got that RAM and can get SCLs stable at 4 with 3800C16. I can't go any lower than 4 though.


----------



## Kildar

I wonder what Windows 11 is going to do to all this?


----------



## boldenc

Audioboxer said:


> Try dropping AddrCmdDrvStr down to 20 and see if it makes any difference. Then simply as a one off, try voltage a bit nearer to 1.5 and see if it makes a difference.
> 
> I've got that RAM and can get SCLs stable at 4 with 3800C16. I can't go any lower than 4 though.


I noticed something weird, this error is not related to stability. it is something with the ram window size settings.
If I run the program without admin privilege, it will run correctly with full ram usage 98% with no errors.
If I run with admin privilege, I have to change the window ram size to like 800mb and keep the full ram usage under 85% to avoid the thread errors.
Tried with another PC and same behavior too.


----------



## KedarWolf

Audioboxer said:


> Put it on 9 for 15.
> 
> 8 is fine for 14 if it boots and is stable. Otherwise 10.
> 
> I believe that's about right... lol.
> 
> 
> Have you tried your SCLs on 4 instead of 5?


My tCL at 14 and tCWL at 12, I have to run 10-1, but tCWL 12 gives me a bit more copy and write and helps latency a bit.


----------



## Veii

KedarWolf said:


> My tCL at 14 and tCWL at 12, I have to run 10-1, but tCWL 12 gives me a bit more copy and write and helps latency a bit.


Been some time 
Try to push tRDRD & tWRWR DD's to 2
Try between 2 & 3
I am confident 2 should also work for Dual Rank, 3 likely for 4x16

Free "more bandwidth" trick
But only at the very very end ~ as stabilizing it is not easy

Only untested thing is that + BankGroupSwap ~ as it may be too short for it (non Alternative function mode)
Just a little advice that has pretty much zero sideeffects

SD's are needed the old way
too low gifts performance & masks latency issues ~ but can allow one step lower tRDWR Requirement
Too high, overlaps with remain timings and will destabilize
Higher = more bandwidth, but too high = choke

Distance between tRDRD & tWRWR SD depends on tRRD_S & tWTR_S


----------



## KedarWolf

Veii said:


> Been some time
> Try to push tRDRD & tWRWR DD's to 2
> Try between 2 & 3
> I am confident 2 should also work for Dual Rank, 3 likely for 4x16
> 
> Free "more bandwidth" trick
> But only at the very very end ~ as stabilizing it is not easy
> 
> Only untested thing is that + BankGroupSwap ~ as it may be too short for it (non Alternative function mode)
> Just a little advice that has pretty much zero sideeffects
> 
> SD's are needed the old way
> too low gifts performance & masks latency issues ~ but can allow one step lower tRDWR Requirement
> Too high, overlaps with remain timings and will destabilize
> Higher = more bandwidth, but too high = choke
> 
> Distance between tRDRD & tWRWR SD depends on tRRD_S & tWTR_S


Anything under 4 I get errors in TM5. 

Edit: I'm confused, do you mean SCL's?


----------



## PJVol

To all those who was sought for performance scaling above 1900 fclk and weren't satisfied with the result.
If you have sisoft sandra installed or don't mind to install it, can you compare the results of the "Processor Science Analysis" test between, lets say, 1900 and 2000 IF configs?
The most interesting part of the benchmark is GEMM score.

@Veii found this while comparing 1900 vs 2000IF in full suite bencmarks, such as "Overall CPU" or "Overall Memory". Before the only indication of throttling for me was GB5 multi test, that showed some degradation, but results were far from consistent and reproducible.

Here is the "Processor Scientific Analysis" results:
* vdd18 in Auto run at the bottom was made just for fun, and to show how this voltage affect stability and performance in my case.









Matrix multiply test cleary shows throttling, and results are reproducible.

Other tests from the suite showed no noticeable regression, for example* Inter-Thread Efficiency* or *Cache & Memory Latency


















*

So far, the results suggests the CPU execution blocks themselves are affected at some degree.
Though it would be interesting to know, what FFT's and GEMM calculations exactly do, I mean what CPU instructions were used, and why high FCLK affect them so differently.
And if it adds something, matrix dimension is 3264x3264 and FFT block size 16mb

So, it would be nice if someone could check it out for themselves to see how reliable it is.


----------



## XPEHOPE3

Some news on me trying to overclock CPU. I never had a WHEA error while having PBO+CO disabled and on scalar 1. But now I do (with PBO+some limits+CO+scalar 4):









What's more interesting is to compare *timings *of those errors with these errors:









I do have SVM disabled in BIOS, although I did install WSL2 and Ubuntu, that's probably why the service tries to run. Please note that I did run y-cruncher test N64 during those Hyper-V-Hypervisor errors and on 17.08 (today) *EACH *of those errors lead to a reboot, some even didn't trigger WHEA error (like the one on 22:37:51)


----------



## Bruizer

TimeDrapery said:


> @Bruizer
> 
> If you keep tCL at 14 then try setting tCWL to 14, tRDWR to 8, and tWRRD to 3
> 
> If you set tCL to 15 then try setting tCWL to 14, tRDWR to 9, and tWRRD to 2
> 
> Regarding what tCWL should be set to ... Experiment and see what performs best for your system
> 
> If you set tCWL lower than tCL it's probably easiest to set tRDWR and tWRRD to Auto and see what values pop up in ZenTimings for you





Audioboxer said:


> Put it on 9 for 15.
> 
> 8 is fine for 14 if it boots and is stable. Otherwise 10.
> 
> I believe that's about right... lol.


@TimeDrapery & @Audioboxer 

Thank you both very much!!!


----------



## boldenc

I have been playing with timings to maximize the final touch and it was not a pleasure as every wrong timing pc will not boot, I had to clear cmos as the motherboard didn't auto revert and no clear button 
and after finding the lowest timings for booting, now I get an error in TM5, it is error #15
current vdimm @ 1.400v
What do you guys suggest to change in my current settings to make it stable ?


----------



## Mach3.2

Err #15 can be anything, what's your last known stable set of timings?


----------



## boldenc

that was last working settings, I changed lot of timings compared to the old stable settings


----------



## umea

PJVol said:


> Still alive, thanks! ))
> As for IOD, 1- and 2-chiplet cpu's may differ regarding their response to vddg voltages, though the exact picture is still mute for me. But it would be safe to assume 0.95-1.00 and 1.00-1.05 for the CCD and IOD respectively.
> Anyway, afaik, low IOD can cause some issues with usb powering, and I heard some had problems with sound, so they are easier to detect, wheras CCD bus/ifops issues are not clear for me yet. Hope, next revision or whatever comes between zen 3 and 4 won't have that buggy glofo die.


Going to second the low IOD causing usb powering issues. Was running into very bad stuttering issues that I tested a couple different things but raising my IOD/CCD got rid of it. (For reference, stuttering was occuring with .970 IOD, upping to 1.06 IOD removed it, at 1900fclk). Initially thought that it was too low trfc, but even raising it to around 150ns didn't change anything. Going to lower it back down.

I've been enjoying no stuttering with 3800cl15 and 4.6 all core (pushing over 400 fps in all fps games so I can make use of my 390hz monitor), but I think pretty soon I'm going to try to make the push to 3800 cl14... Will probably restart from scratch on another bios save.


----------



## Mach3.2

boldenc said:


> that was last working settings, I changed lot of timings compared to the old stable settings


I'd start experimenting by tightening tRRD, tWTR and tRDRD/tWRWR SCL seperately so it's easier to get a clue which timing is causing the instability.

You probably also need a little bit more vDIMM to stabilise the tighter tertiaries


----------



## mongoled

Yay, ive resuscitated the "dead" RAM stick



The issue turned out to be one of the other decoupling resistors that was situated next to the broken off one.

It looked to be OK, but it was not.

Ive mentioned previously how small the resistors are, well here you go

😂😂









So to troubleshoot, I removed one of these from a working stick and attempted to post the system, was greeted with a error code "C5", this was excellent as it was the same error code that was occurring on the dead stick.

So I then bridged the gap with a fine piece of wire and attempted to post and yep it did !











So with this knowledge I moved onto the dead stick.

I removed my previous attempts and bridged the two missing resistors and attempted to post, but it would not, error code C5. So I thought I would re-attach the tiny resistor to one of the places where I had bridged the pads with a wire.

Still no go, I then thought to myself there must be another resistor that is not connected properly and to my good fortune it was next to the first one that I had attempted to resolder. (left is fine wire, middle right is the one I fluxed/resoldered and right to that is the resistor I re-attached)









 

And here is my trusty old soldering iron as the iron I usually use for this type of work had decided to die ....









Now Im just running some TM5 to see if they are stable with previous known good settings so far so good cycle 6 no errors so far, but saying that my first attempt the memory was badly trained and errors galore.

Am wondering if these resistors are required for memory training ...


----------



## boldenc

well things are getting worse, for some reason I am failing test #15 with any settings no matter what is the ram speed/ or latency.
I updated the bios early today to agesa patch c, I have tested before the update 3200/3600 and passed 20 cycles TM5 and was working on the 3800 so not sure what has changed.
I loaded everything to default and going to re-test the ram now.


----------



## mongoled

OK so im real happy that the RAM posts



But having stability issues at previous known stable settings.

Tomorrow im going to take the RAM waterblock off and cool the dimms with some fans just to rule out that its not something to do with how the RAM sits in the dimms as there is almost no clearence between each dimms heatspreader. 

This may be forcing the dimms to sit in an "unatural position",so when the waterblock places pressure on the dimms through tightening it causes tension on the dimms and can cause the type of errors im seeing.

Had the same issue when running two sticks, know stable settings were failing, after adjusting how I was mounting the two dimms the issue went way.

Hopefully thats all it is and I wont have to do more work on the RAM sticks


----------



## Frosted racquet

Hi guys, need a little input regarding an issue with my RAM kit. 

Running 5600x OCed (if it matters: +200MHz, -20 CO, 125W PPT, 90A TDC, 130A EDC, tested in CoreCycler for couple days, fully stable), 2x16GB G.Skill Ripjaws V DDR4 3600Mb/s CL16 F4-3600C16D-32GVKC (Dual Rank, Hynix CJR according to Thaiphoon) on an ITX MSI B550i motherboard in CM NR200P case.

The issue is when running TM5 (with 1usmus_v3 and [email protected] configs, haven't tested others) on XMP settings (3600 CL16 1.35V) it almost always throws an #13, sometimes #4 error which according to 1usmus_v3 config details is related to DIMM temperatures.

There's no physical space to put a fan to blow on the DIMMs, as the CPU cooler (Mugen 5) and PSU obstruct them. There's no RAM temperature sensor so I don't know the actual temps, but I realize it can be very toasty inside the ITX case.

Has anyone seen temperature issues with their RAM on just 1.35v?


----------



## Veii

KedarWolf said:


> Edit: I'm confused, do you mean SCL's?


No.








As mentioned "hard to stabilize" & should be only used at the very end 
But possible,
DD's at 2.


PJVol said:


> Here is the "Processor Scientific Analysis" results:
> * vdd18 in Auto run at the bottom was made just for fun, and to show how this voltage affect stability and performance in my case.


Yes, it influences it
It starts to influence it - if you lack SOC voltage
Or the opposite, if you have too much SOC voltage, it hides other lack of voltages

Current ASUS Bioses start to modify the 1.8v higher and higher
It's a balance thing i guess
It is affected by SOC, cLDO_VDDP and procODT

Haven't seen yet it affecting CCD stability


Spoiler: Hydra Playground & Short Review



Also played with Hydra ~ and i am a bit unsatisfied for now
It's powerful, but still alpha. It too often skips SSE loads, and falls back to bad stock PBO. Same for latest CTR ~ both Patreon, don't come even close to holding 4.85 sustained. 4.6, maybe 4.7 if dynamic

Speaking of dynamic, here are "apparently safe" voltage ranges for 6 cores, in case you go manual OC








OC & Normal / Stock















And Undervolt Recommendations









Neither CTR, nor Hydra can exceed 4.7
Here are some "by AMDs binning being off" values








But still not close to personal CO work as
-17
-15
-14
-19
-21
-12

To give it credit,
"Micro CO range" is more accurate & for non broken samples, when it functions better and doesn't let the CPU go back to AMD_Boost mode
It can be very useful, than doing it by hand in the Bios








This Feature for example is very powerful - but it's algorithm still pushes the CPU too often into AMD_BOOSTING mode. Which logically performs horrible without CO modification
Soo with or without user CO correction - it's ability is too lacking yet. *But as for the "functioning" part ~ proof of work is functioning correctly and i see great future & timesaver for it/us.*
Just fails same as CTR, for units with broken V/F curve who require pre-CO user input correction

It also needs support for SSE & AVX (both individual, not A or B) to as best as possible never fall to AMD_BOOST mode back.
Soo currently non affinity aware tasks continue to perform very bad with it. So also games who do push to gamemode, but remain SSE and affinity unaware.
Two scenarios Alpha is not yet build for.
It surely needs more control on CO TUNE - but the ability of it , that part is great and functions. (I'd like to see each of the options options
(1T-2T, 4T, 6T, Game, each of them should have individual CO "overdrive" access" not only either AVX or either SSE.) ~ (want to see it, as for my odd sample, it remains not extreme enough and so performs 175-200Mhz less than it actually could / * tested with BLCK, potential is there, still unused potential)
Sadly again, SSE allcore and AVX Allcore need a split for CO

Testing time took me 3-4 hours with voltage prediction
Else it was around 45min
Expect dual CCD to take 8-9h

Failure on Reboot = Restore, functioned flawlessly. Better than CTR. Good job @1usmus
Sadly lost contact to you thx to Discord 2015 Acc restoration, but see this as little review when you check back OCN 

Hydra Silver
CTR Gold










I believe, someday being able to replace my manual PBO
But it appears to take more time still.
Love the far more granule CO control - just Hydra let's it too often switch to AMD_BOOST mode, which then drops the reason to use it.
Same for CTR and why i can not use it daily ~ general perf is lower in any load-type
OB + Manual CO works only if manual CO correction is lowered by big manitudes. This defeats the purpose of Software CO (OB-Feature) correction.
Software CO letting sample back to AMD_BOOST defeats purpose of using Software , and results are very low.
~ Because you can not use "good PBO" with Software OB. And you can not only use Software OB, because it let's sample too often fall back to AMD_BOOST which performs very bad without user-CO
A or B , or A + weaken B
A+ (overdriven CTR or Hydra) is still possible, but results remain better AMD_BOOOST, weaker Software_OB result
Evens out to mediocre at best

Either A or either B
I hope A.) Software CO will hold Vermeer more tight and don't let it fall back to "not optimal" AMD_BOOST (soo it won't lose perf)
Someday someday Yuri-Tools will finally beat my PBO of 4.85 allcore. I believe & support ~ but so far, half a year was not enough. Keep fighting ✊


Veii said:


> Love the far more granule CO control


This is a good timesaver for Dual CCD clients
I hope, i can get "faster" good results out.
It likely will struggle to beat my by hand work ~ but alone for fast results with thaat many cores. It can be worth it 

Conclusion:
It's good, but not good enough (Alpha v0.9 PRO)
Not good enough to beat my PBO so far, let alone surpass it without the need to use BLCK
I look forward to full functionality versions, as half of it appears WIP 😇


mongoled said:


> Yay, ive resuscitated the "dead" RAM stick


The issue is close to always infront of you. Just have to take time off and look neutral on it
Good job , bravo !
Now look it becoming a better overclocker than the rest


----------



## PJVol

Veii said:


> Yes, it influences it
> It starts to influence it - if you lack SOC voltage
> Or the opposite, if you have too much SOC voltage, it hides other lack of voltages


Yes, and it's (vdd18) the only thing that affects (or rather minify throttling). No other voltages do any help. Have tried vSOC in 1.05 - 1.2 range - zero effect.
But...
You seem to miss the point, that is regardless of how much vdd18 was pumped in,
I found that GEMM test clearly shows instability at some point of the CPU-DRAM path, when DF is overclocked above 1900.









And yes, I've ran through all usual suspects, such as
AIDA, tm5, DRAM calc membench, CB's (20/23), and lot more, and NONE showed anything extraordinary, except small deviation in GeekBench 5 Multi.
I just wanna know, does that test reliable enough or the results are specific forr my PC config, and thats it.
The bench itself takes 2-3 minutes at most.

Attached configs subjected to compare.


----------



## MrHoof

@PJVol













Shouldnt I score higher since its a Mutli core benchmark? Gotta look into it, cause mine isnt much higher for a 5800x, testing some more tomorrow.


----------



## XPEHOPE3

@MrHoof 
The point was to compare e.g. 1900MHz and 2000MHz FCLK, but both of your runs show 1.9GHz IMC...



Veii said:


> -17
> -15
> -14
> -19
> -21
> -12


Can you please post your whole 4.85 CPU config? Limits, vcore offset, LLC, scalar. I assume you did test y-cruncher with those and it passed? Does it also hold 4.85 for e.g. 2nd and 3rd tests? Do you still not run CoreCycler/OCCT per core SSE full? 
From my CPPCs I think my sample should be better than yours, yet one of my best cores requires -5 CO offset 💩 to pass CoreCycler. And in any case y-cruncher doesn't hold 4.85 for 2-3 tests because of PROCHOT limit, hitting 85°C at 4.5GHz.

Also do you by any chance have screenshots from the tool with AMD monitor and per core monitor showing current FIT, amperage, etc. during CB23 run when you do hit 4.85? I keep seeing suspicious CCA frequency limiter being hit sometimes even lower than PROCHOT. I think it's voltage-related and wonder why I hit it and you don't


----------



## domdtxdissar

Veii said:


> Spoiler: Hydra Playground & Short Review
> 
> 
> 
> Also played with Hydra ~ and i am a bit unsatisfied for now
> It's powerful, but still alpha. It too often skips SSE loads, and falls back to bad stock PBO. Same for latest CTR ~ both Patreon, don't come even close to holding 4.85 sustained. 4.6, maybe 4.7 if dynamic
> 
> Speaking of dynamic, here are "apparently safe" voltage ranges for 6 cores, in case you go manual OC
> 
> 
> 
> 
> 
> 
> 
> 
> OC & Normal / Stock
> View attachment 2521581
> View attachment 2521582
> 
> And Undervolt Recommendations
> View attachment 2521583
> 
> 
> Neither CTR, nor Hydra can exceed 4.7
> Here are some "by AMDs binning being off" values
> View attachment 2521584
> 
> But still not close to personal CO work as
> -17
> -15
> -14
> -19
> -21
> -12
> 
> To give it credit,
> "Micro CO range" is more accurate & for non broken samples, when it functions better and doesn't let the CPU go back to AMD_Boost mode
> It can be very useful, than doing it by hand in the Bios
> View attachment 2521585
> 
> This Feature for example is very powerful - but it's algorithm still pushes the CPU too often into AMD_BOOSTING mode. Which logically performs horrible without CO modification
> Soo with or without user CO correction - it's ability is too lacking yet. *But as for the "functioning" part ~ proof of work is functioning correctly and i see great future & timesaver for it/us.*
> Just fails same as CTR, for units with broken V/F curve who require pre-CO user input correction
> 
> It also needs support for SSE & AVX (both individual, not A or B) to as best as possible never fall to AMD_BOOST mode back.
> Soo currently non affinity aware tasks continue to perform very bad with it. So also games who do push to gamemode, but remain SSE and affinity unaware.
> Two scenarios Alpha is not yet build for.
> It surely needs more control on CO TUNE - but the ability of it , that part is great and functions. (I'd like to see each of the options options
> (1T-2T, 4T, 6T, Game, each of them should have individual CO "overdrive" access" not only either AVX or either SSE.) ~ (want to see it, as for my odd sample, it remains not extreme enough and so performs 175-200Mhz less than it actually could / * tested with BLCK, potential is there, still unused potential)
> Sadly again, SSE allcore and AVX Allcore need a split for CO
> 
> Testing time took me 3-4 hours with voltage prediction
> Else it was around 45min
> Expect dual CCD to take 8-9h
> 
> Failure on Reboot = Restore, functioned flawlessly. Better than CTR. Good job @1usmus
> Sadly lost contact to you thx to Discord 2015 Acc restoration, but see this as little review when you check back OCN
> 
> Hydra Silver
> CTR Gold
> View attachment 2521591
> 
> 
> 
> I believe, someday being able to replace my manual PBO
> But it appears to take more time still.
> Love the far more granule CO control - just Hydra let's it too often switch to AMD_BOOST mode, which then drops the reason to use it.
> Same for CTR and why i can not use it daily ~ general perf is lower in any load-type
> OB + Manual CO works only if manual CO correction is lowered by big manitudes. This defeats the purpose of Software CO (OB-Feature) correction.
> Software CO letting sample back to AMD_BOOST defeats purpose of using Software , and results are very low.
> ~ Because you can not use "good PBO" with Software OB. And you can not only use Software OB, because it let's sample too often fall back to AMD_BOOST which performs very bad without user-CO
> A or B , or A + weaken B
> A+ (overdriven CTR or Hydra) is still possible, but results remain better AMD_BOOOST, weaker Software_OB result
> Evens out to mediocre at best
> 
> Either A or either B
> I hope A.) Software CO will hold Vermeer more tight and don't let it fall back to "not optimal" AMD_BOOST (soo it won't lose perf)
> Someday someday Yuri-Tools will finally beat my PBO of 4.85 allcore. I believe & support ~ but so far, half a year was not enough. Keep fighting ✊
> 
> This is a good timesaver for Dual CCD clients
> I hope, i can get "faster" good results out.
> It likely will struggle to beat my by hand work ~ but alone for fast results with thaat many cores. It can be worth it
> 
> Conclusion:
> It's good, but not good enough (Alpha v0.9 PRO)
> Not good enough to beat my PBO so far, let alone surpass it without the need to use BLCK
> I look forward to full functionality versions, as half of it appears WIP 😇
> 
> The issue is close to always infront of you. Just have to take time off and look neutral on it
> Good job , bravo !
> Now look it becoming a better overclocker than the rest


So i take it you tried Hydra patreon alpha 0.9 A (or B) ?
These versions dont support 1-16 thread profiles yet.. *Only AVX / gamemode profile is working in those versions.*

Not so strange it didn't beat your optimized PBO CO settings since your cpu was running stock in everything other then avx (allcore) and gamemode.. In gamemode it should crush your PBO settings tho.. Did you do a cpu speed comparison in timespy / vantage.. ? (use "xoc" 1400mv gameprofile)

Its only the unreleased (to public patreon) 0.9*C* that have 1-16 threads profile active, but this version is a "alpha alpha".. with much performance overhead and gamemode not working...


----------



## mongoled

May just be I got the order of the modules mixed up.

Now that I have them in the "correct" order ive reached the 10th cycle with no errors so far, hopefully it stays that way!

Ive asked a question in the voltage mods section if someone happens to know a little bit about electronics would appreciate an answer.


----------



## boldenc

For future reference if someone faced same error. After more testing, it was my curve optimizer settings for my best cores causing error 15 despite these settings passed corecycler, ycruncher for hours, it gave me error 15 in TM5.


----------



## Nighthog

boldenc said:


> For future reference if someone faced same error. After more testing, it was my curve optimizer settings for my best cores causing error 15 despite these settings passed corecycler, ycruncher for hours, it gave me error 15 in TM5.


I've seen similar stuff, Error 15 can be Core voltage error caused, maybe CPU cache?
It's a a tricky error as it's not always that.


----------



## Audioboxer

Good news, my 2080Ti I received back from EVGA works great, PC is up and running again and the silicon on this card is slightly better than my failed one, I can do 2115mhz on this whereas last struggled to hit 2080 and remain stable.

Bad news is thanks to the idiots in the UK that voted for Brexit, UK Border Force slapped a VAT charge of £180 on my RMA despite it being... an RMA. BOR286 form filled in and now a fight to reclaim back the charge.

3600C14 memory is due to arrive tomorrow, so back in the memory game. Looking forward to it.

Oh, I'd add GC-Extreme thermal paste seems to be working better for me than Grizzly Kryonaut. Had a tip to change to it and my thermals on my CPU and GPU are a bit better. Was also a bit easier to spread which was a bonus.











That is what I call some nice idles.


----------



## boldenc

Nighthog said:


> I've seen similar stuff, Error 15 can be Core voltage error caused, maybe CPU cache?
> It's a a tricky error as it's not always that.


Just changing curve to less aggresive settings made it pass the 20 cycles. While testing with same old curve with 1600fclk it failed with error15 too so looks it is mainly core voltage related.


----------



## BarrettDotFifty

So I took advice from you all and stabilized this with the goal of running a flat set of primaries, GDM off and optimal RTT. Any ideas about what's next to improve for this particular setup or perhaps there's something odd in this state?


----------



## Audioboxer

BarrettDotFifty said:


> So I took advice from you all and stabilized this with the goal of running a flat set of primaries, GDM off and optimal RTT. Any ideas about what's next to improve for this particular setup or perhaps there's something odd in this state?
> 
> View attachment 2521663


Did you have a go at tCL 14 at any point at 3600? It's difficult to achieve at 3800, my 3200C14 sticks can't manage it, but should be worth a go at 3600. Either flat 14s or 15 for tRCDRD. I run 1900/3800 as its fine with my 5950x, no WHEA.

Not sure what I'd advise on timings, but you could attempt to bring down VDDG voltage. Try 0.975v for both and see if stable.

Depending on your VDIMM voltage tRFC might be able to come down a bit. If you're at 1.45v+, try 270~280. If you can get it stable somewhere in that range, try 250~260 next.


----------



## BarrettDotFifty

Audioboxer said:


> Did you have a go at tCL 14 at any point at 3600?


Yes, but I can't bring tRCDRD down to 14 for a flat set of timings (causes all sorts of errors and it's very difficult to track down, while aiming for GDM off and optimal RTT). With a setup of 14-15-14 I get almost the same latency results as with a 15-15-15 setup and considering the higher voltage necessities, I decided to drop it.


----------



## Audioboxer

BarrettDotFifty said:


> Yes, but I can't bring tRCDRD down to 14 for a flat set of timings (causes all sorts of errors and it's very difficult to track down, while aiming for GDM off and optimal RTT). With a setup of 14-15-14 I get almost the same latency results as with a 15-15-15 setup, so I decided to drop it.


Yeah, tRCDRD is evil. Everyone hates it 😂

Flat 15's is fine then, I edited in above try bringing down tRFC a bit. It's probably the last change for you that might bring down latency. Other than that I'd shift to focus on reducing voltage as much as possible.


----------



## PJVol

MrHoof said:


> Shouldnt I score higher since its a Mutli core benchmark? Gotta look into it, cause mine isnt much higher for a 5800x, testing some more tomorrow.


Gotta look into your scores in other mc benchmarks, such as CB, blender, etc.

Can you make the same test, but this time with memory/infinity fabric at 4000/2000, or 3933/1966, and post the results?


----------



## MrHoof

PJVol said:


> Gotta look into your scores in other mc benchmarks, such as CB, blender, etc.
> Can you make the same test, but this time with memory/infinity fabric at 4000/2000, or 3933/1966, and post the results?










my best CB23 score. on HWBOT thats top 20

well but wont be WHEA free, but gonna do that now.








Blue 1900fclk daily profile
Red 1933fclk 17-18-18-38-56-336 1.1v soc
Green 1933fclk 17-18-18-38-56-336 1.2v soc
just used XMP timing with tuned subtimings.

edit: Red looks actuly not that bad for lose primary timings.


----------



## mongoled

OK, thats two TM5s completed in a row, safe to say the RAM is working as it was before











Tomorrow will attach the RAM waterblock


----------



## PJVol

MrHoof said:


> well but wont be WHEA free, but gonna do that now.


Dont mind whea's - pretty much 999 out of 1000 vermeer's has it, when DF OC'ed above 1900, whether or not said errors was made explicit.
And thanks for the tests.

One note regarding graphs.
Red bar reports 2000 fclk and Green has no data shown.
Also, Red and Blue shows 4.85 cpu clock, wheras bottom (Green) at the default clock.
And very low result for the Green possibly may indicate desync'ed FCLK and UCLK, which happen quite often when you set just the memory clock in bios, without FCLK being set accordingly.

So would you mind doublecheck your results and the settings used.
Thanks!

PS: as for CB score, it obviosly is fine and there's nothing to worry about.


----------



## domdtxdissar

mongoled said:


> OK, thats two TM5s completed in a row, safe to say the RAM is working as it was before
> 
> 
> 
> View attachment 2521715
> 
> 
> Tomorrow will attach the RAM waterblock


Good to hear it worked out for you 

Maybe not the right thread, but im also doing some tinkering..









Baseline settings @ 500w bios in warm room and all fans on auto (silent)


----------



## Mach3.2

domdtxdissar said:


> Good to hear it worked out for you
> 
> Maybe not the right thread, but im also doing some tinkering..
> View attachment 2521752
> 
> 
> Baseline settings @ 500w bios in warm room and all fans on auto (silent)
> View attachment 2521753


How warm is your room, seem like it's around 20 deg Celsius ambient?

IMO there's little point in going liquid metal + stock cooler, you might as well go all the way with a custom loop. A custom loop would have the benefit of higher thermal capacity, allowing the GPUs to boost higher for longer.


----------



## domdtxdissar

Mach3.2 said:


> How warm is your room, seem like it's around 20 deg Celsius ambient?
> 
> IMO there's little point in going liquid metal + stock cooler, you might as well go all the way with a custom loop. A custom loop would have the benefit of higher thermal capacity, allowing the GPUs to boost higher for longer.


Room was ~27 degrees celsius (gpu idle temp is pretty much ambient on this setup)
Do you think i'm getting sub 60 degrees max GPU hotspot temp while running stock cooling on a 520w bios ? 😇

Will play around with 1000w bios this weekend if everything goes according to plan


----------



## MrHoof

PJVol said:


> One note regarding graphs.
> Red bar reports 2000 fclk and Green has no data shown.
> Also, Red and Blue shows 4.85 cpu clock, wheras bottom (Green) at the default clock.
> And very low result for the Green possibly may indicate desync'ed FCLK and UCLK, which happen quite often when you set just the memory clock in bios, without FCLK being set accordingly.


Both runs were 1933, Sandra just reports it as 2000 and no idea why I does not report anything for green but was for sure 1933. Zentimings was showing synced 1933 fclk/uclk i checked that ofc.
Green dropped to baseclock cause of the 1.2v soc I guess. GREEN was run first then i went into Bios and lowerd only soc to 1.1v for the RED and booted backup the settings else are the same.

edit: I can repeat the test in the evening as this was done on Windows Balanced powerplan.


----------



## mongoled

domdtxdissar said:


> Good to hear it worked out for you
> 
> Maybe not the right thread, but im also doing some tinkering..
> View attachment 2521752
> 
> 
> Baseline settings @ 500w bios in warm room and all fans on auto (silent)
> View attachment 2521753


Get some masking tape on those tiny SMDs !

You dont want any liquid metal getting on those by mistake


----------



## domdtxdissar

mongoled said:


> Get some masking tape on those tiny SMDs !
> 
> You dont want any liquid metal getting on those by mistake


They have 5 layers of nail polish 
Maybe not so easy to see since i used clear color, but its there


----------



## mongoled

Audioboxer said:


> Good news, my 2080Ti I received back from EVGA works great, PC is up and running again and the silicon on this card is slightly better than my failed one, I can do 2115mhz on this whereas last struggled to hit 2080 and remain stable.
> 
> Bad news is thanks to the idiots in the UK that voted for Brexit, UK Border Force slapped a VAT charge of £180 on my RMA despite it being... an RMA. BOR286 form filled in and now a fight to reclaim back the charge.
> 
> 3600C14 memory is due to arrive tomorrow, so back in the memory game. Looking forward to it.
> 
> Oh, I'd add GC-Extreme thermal paste seems to be working better for me than Grizzly Kryonaut. Had a tip to change to it and my thermals on my CPU and GPU are a bit better. Was also a bit easier to spread which was a bonus.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> That is what I call some nice idles.


Interested to see how you get on with the memory, was not too long ago you were not wanting to spend much time on this

😂😂

Wish you luck in getting your money back, the number of idiots in the World is increasing at an exponential value.


----------



## PJVol

MrHoof said:


> Sandra just reports it as 2000 and no idea why


Yep, you're right. Just checked, it does misreport mem/uclk clocks indeed.


----------



## Audioboxer

mongoled said:


> Interested to see how you get on with the memory, was not too long ago you were not wanting to spend much time on this
> 
> 😂😂
> 
> Wish you luck in getting your money back, the number of idiots in the World is increasing at an exponential value.


I am a little disappointed with my 3200C14 set compared to other people's so selling it will recoup a fair chunk of the cost of the 3600C14 set and I'm confident I'll be able to push better timings at 3800 now 

Due today so I'll have a quick look at DOCP tonight and see how it sets things up.


----------



## Mach3.2

domdtxdissar said:


> Room was ~27 degrees celsius (gpu idle temp is pretty much ambient on this setup)
> Do you think i'm getting sub 60 degrees max GPU hotspot temp while running stock cooling on a 520w bios ? 😇
> 
> Will play around with 1000w bios this weekend if everything goes according to plan


So you did went all the way, I stand corrected. Have fun with overclocking your card. 😃


----------



## Audioboxer

Spoiler
























Don't have time to work on these just now, have work to do, but I'm assuming with the RipJaws heatsinks being shorter it should be easier to tell what PCB these are? Will snap some better pics later.

edit - I can spare 5~10 mins to at least make sure they are booting OK. XMP profile 1 and auto settings


----------



## Audioboxer

First thing I wanted to make sure I can do, boot RttPark 3. Regulars in this topic might remember all the issues I was having doing that on my 3200C14 set, well, here we are, 6/3/3 and no issues at 3800. 

Anyway, no time to play any further, will be back later tonight for the real fun!


----------



## umea

Any suggestions on troubleshooting anta's config? I haven't noticed any problems in games and 1usmus_v3 runs stable for 25 cycles (no errors), but I get error 12 relatively quickly on Anta's config


----------



## XPEHOPE3

PJVol said:


> it does misreport mem/uclk clocks indeed.


It seems to be bugged af. Try e.g. to delete a result (via Manage results... button). I consistently get a crash.


umea said:


> I get error 12 relatively quickly on Anta's config


Have you checked the usual suspects like memory temperature and CPU stability? How many iterations of y-cruncher all-tests did you check?


----------



## PJVol

XPEHOPE3 said:


> It seems to be bugged af. Try e.g. to delete a result (via Manage results... button). I consistently get a crash


It is. It get crashed on exporting result into anything other than a ".txt" as well. I think the module is buggy itself, since exported "All users results"(txt) show correct clocks.


----------



## Audioboxer

Had a bit of time to throw some "random" numbers into this and give it 3 cycles. Good news is compared to my other set of b-die not only does RttPark 3 boot fine, GDM disabled 1T also doesn't need the Setup's to boot. "Bad news" is me hoping tRCDRD might be fine at 14 because the memory is binned at 3600 flat 14s was wishful thinking 😂 Got some errors minutes in with tRCDRD on 14. Passed a 3 cycle fine on 15.

SCLs also look like they'll be fine going below 4, couldn't run them below that on the other ram either.

Now whether to persist with trying to get tRCDRD stable at 14 or not... I see this is probably why a lot of people just go with flat 15's.


----------



## mongoled

Audioboxer said:


> Had a bit of time to throw some "random" numbers into this and give it 3 cycles. Good news is compared to my other set of b-die not only does RttPark 3 boot fine, GDM disabled 1T also doesn't need the Setup's to boot. "Bad news" is me hoping tRCDRD might be fine at 14 because the memory is binned at 3600 flat 14s was wishful thinking 😂 Got some errors minutes in with tRCDRD on 14. Passed a 3 cycle fine on 15.
> 
> SCLs also look like they'll be fine going below 4, couldn't run them below that on the other ram either.
> 
> Now whether to persist with trying to get tRCDRD stable at 14 or not... I see this is probably why a lot of people just go with flat 15's.


Im missing something here ??

Can you go over what you ended up replacing as what I remember is that your motherboard was having issues i.e. getting hot and then your vga went poof also.

You were using an Asus motherboard before and now you have an MSI.

Did you test those modules that would not post other RttPark values on the MSI ??


----------



## Audioboxer

mongoled said:


> Im missing something here ??
> 
> Can you go over what you ended up replacing as what I remember is that your motherboard was having issues i.e. getting hot and then your vga went poof also.
> 
> You were using an Asus motherboard before and now you have an MSI.
> 
> Did you test those modules that would not post other RttPark values on the MSI ??


3200C14. F4-3200C14D-32GTZ.

I couldn't boot RttPark 3 above 3400 on either motherboard. This memory also couldn't seem to boot GDM disabled 1T at 3800 without needing to use the Setups. Also couldn't go below SCL4. While I've only tested 3 cycles above, SCL below 4 either didn't boot on my 3200C14 or error'd out within seconds.

New set will boot RttPark 3 fine at 3800 and I tested GDM disabled/1T at 40/20/30/24 and it booted fine.

Just a better set of memory all round, I just need to plan my "ground zero" for where I hope to go with it. GDM disabled with 2T seems to "train" both sticks to tPHYRDL on 26. If I mess around with GDM enabled/1T one of the sticks seems to go to 28.

tRCDRD seems like it might be a pipe dream at 14 at 3800 as well, but it's early days. If it can boot and last 5 mins in MemTest5 there is hope


----------



## mongoled

Just testing tRCDRD @14, previously with air cooled RAM modules would have been spammed with many error 6/10/0 and other values after a couple of cycles.

Error 13 just popped up on the 6th cycle though I doubt it has something to do with heat.

So cooling the dimms more effectively allows tRCDRD to run @14 without totally spamming TM5 with errors.

Probably one of the reasons the few people who are showing tRCDRD stable @14 are at low ambient temps and with a load of fans or are water cooling the dimms .


----------



## mongoled

Audioboxer said:


> 3200C14. F4-3200C14D-32GTZ.
> 
> I couldn't boot RttPark 3 above 3400 on either motherboard. This memory also couldn't seem to boot GDM disabled 1T at 3800 without needing to use the Setups. Also couldn't go below SCL4. While I've only tested 3 cycles above, SCL below 4 either didn't boot on my 3200C14 or error'd out within seconds.
> 
> New set will boot RttPark 3 fine at 3800 and I tested GDM disabled/1T at 40/20/30/24 and it booted fine.
> 
> Just a better set of memory all round, I just need to plan my "ground zero" for where I hope to go with it. GDM disabled with 2T seems to "train" both sticks to tPHYRDL on 26. If I mess around with GDM enabled/1T one of the sticks seems to go to 28.


Now im with you



regards tPHYRDL, you going to have to work out what cause it to drop to 28, on my setup it can be somewhat fixed with higher vDDP but that is dependent on how hard you are pushing the modules.

Look at my screengrab above.

Keeping tCL @15 allows tPHYRDL to stay at 26 while using 1T (56-0-0) and tRCDRD @14


----------



## Audioboxer

mongoled said:


> Now im with you
> 
> 
> 
> regards tPHYRDL, you going to have to work out what cause it to drop to 28, on my setup it can be somewhat fixed with higher vDDP but that is dependent on how hard you are pushing the modules.
> 
> Look at my screengrab above.
> 
> Keeping tCL @15 allows tPHYRDL to stay at 26 while using 1T (56-0-0) and tRCDRD @14


Thanks, great timing! I think it seems to be switching to 1T that causes it (with current settings). I can boot 1T without the setups (left at 0-0-0) unless you are advising booting at 56-0-0 can help retain 26.

Apart from running a 25 cycle to see if I can get a baseline locked in, I guess I'll have a poke around tRCDRD at 14. I've got active cooling and usually keep temps below 40 around 1.5~1.52v. I'm happy to stability test up to 1.6v, but I'm wondering how much of that would be worth it to chase flat 14's. I've also got to look at the right hand side even at 2T, I've just left it on auto just now for stability testing. I presume some of it, even at 2T, might help with tRCDRD 14.

I do have one question for you, I've seen a few people run tCKE 9, what is that relevance over 1? It's one setting I haven't really learned anything about.


----------



## umea

XPEHOPE3 said:


> It seems to be bugged af. Try e.g. to delete a result (via Manage results... button). I consistently get a crash.
> Have you checked the usual suspects like memory temperature and CPU stability? How many iterations of y-cruncher all-tests did you check?


I'll try running y-cruncher again to see later


----------



## mongoled

Audioboxer said:


> Thanks, great timing! I think it seems to be switching to 1T that causes it (with current settings). I can boot 1T without the setups (left at 0-0-0) unless you are advising booting at 56-0-0 can help retain 26.
> 
> Apart from running a 25 cycle to see if I can get a baseline locked in, I guess I'll have a poke around tRCDRD at 14. I've got active cooling and usually keep temps below 40 around 1.5~1.52v. I'm happy to stability test up to 1.6v, but I'm wondering how much of that would be worth it to chase flat 14's. I've also got to look at the right hand side even at 2T, I've just left it on auto just now for stability testing. I presume some of it, even at 2T, might help with tRCDRD 14.
> 
> I do have one question for you, I've seen a few people run tCKE 9, what is that relevance over 1? It's one setting I haven't really learned anything about.


Well ive not tested "true" 1T as previously this would results in bluescreens while entering Windows, however, when I went back to 2 dimms I found out that it may have been caused by my use of 3-3-15 for the setup values.

Will have to return to true 1T on these modules now that they are watercooled and the discovery of the setup values issue.

Using tCL @15 compared to @14 I lose around 400 mbytes of read bandwidth Arghh, loss in bandwidth is not related to tCL but to not running "true" 1T, but latency improves by 0.2/.3 ns, so its either loose bandwith with tCL @15 or gain latency ..

tCKE is to do with power saving, that go hand in hand with setup values ... Veii has gone through this, search forum


----------



## mongoled

Oh, missed the 2T part, it does not effect how tRCDRD runs, well at least not on my setup.

tRCDRD potential does seem tied to the powering of dimms and quality of dimm PCB, hence the reason dropping temps helps ...


----------



## Audioboxer

mongoled said:


> Well ive not tested "true" 1T as previously this would results in bluescreens while entering Windows, however, when I went back to 2 dimms I found out that it may have been caused by my use of 3-3-15 for the setup values.
> 
> Will have to return to true 1T on these modules now that they are watercooled and the discovery of the setup values issue.
> 
> Using tCL @15 compared to @14 I lose around 400 mbytes of read bandwidth, but latency improves by 0.2/.3 ns, so its either loose bandwith with tCL @15 or gain latency ..
> 
> tCKE is to do with power saving, that go hand in hand with setup values ... Veii has gone through this, search forum
> 
> 
> 
> View attachment 2521773


That latency is sexy so I'll likely take your advice into account. To the layman seems strange you can get tRCDRD stable at 14 but only if using tCL 15 lol. The joys of memory!

I'm not stressing over 1T for now, just found it interesting I could boot it into windows with no need for using Setup when my old RAM needed it to even post at 3800. But I need to get a stable base at 2T as the smart memory overclockers do before worrying about 1T.










I made a quick edit to the above 3 cycle, tRTP to 6 and TWTRL to 10, that done the 3 cycle. I guess at this point I'll now do a 25 cycle. Try and get something locked in before any more poking around.


----------



## mongoled

Audioboxer said:


> That latency is sexy so I'll likely take your advice into account. To the layman seems strange you can get tRCDRD stable at 14 but only if using tCL 15 lol. The joys of memory!
> 
> I'm not stressing over 1T for now, just found it interesting I could boot it into windows with no need for using Setup when my old RAM needed it to even post at 3800. But I need to get a stable base at 2T as the smart memory overclockers do before worrying about 1T.


No no no,

that has nothing to do with it!

tRCDRD can run @14 not because tCL is @15 but because the dimms are watercooled.

[email protected] just allows tPHYRDL to run @26 otherwise I would have left tCL @14

Yup, concentrate on 2T first !


----------



## Audioboxer

mongoled said:


> No no no,
> 
> that has nothing to do with it!
> 
> tRCDRD can run @14 not because tCL is @15 but because the dimms are watercooled.
> 
> [email protected] just allows tPHYRDL to run @26 otherwise I would have left tCL @14
> 
> Yup, concentrate on 2T first !


Ah, I get you, and shows I'm learning. When I read that and thought that was what you meant even I thought "That is strange", hence my comment LOL. Glad I just misread you. I understand the link now to the prior post as well as we were talking about [email protected] and what might make it go to 28.

I think I might go watercooled too, I can get 2 DIMM blocks on Aliexpress from Bykski which should be fine. My current loop can be adapted quite easily to include the RAM.


----------



## mongoled

Audioboxer said:


> Ah, I get you, and shows I'm learning. When I read that and thought that was what you meant even I thought "That is strange", hence my comment LOL. Glad I just misread you. I understand the link now to the prior post as well as we were talking about [email protected] and what might make it go to 28.
> 
> I think I might go watercooled too, I can get 2 DIMM blocks on Aliexpress from Bykski which should be fine. My current loop can be adapted quite easily to include the RAM.


😁😁

As a first time RAM watercooler here is my quick run down.

1/ Don't buy Alphacool modules from Aquacooling.de, they have bad stock that they are trying to shift
2/ Removing the heatspreaders is a nightmare, use a heat gun, take extreme care of the tiny SMDs 🤣🤣
3/ Make simple bends from CPU to RAM block if using PETG tubing
4/ Pay attention to get the correct thickness thermal pads
5/ You are not going to be able to switch the modules quick and easy, so you learn your memory on air, get stable settings configs sorted, then you put them under water

Through the trial and tribulations ive been through im happy to have them water cooled


----------



## umea

mongoled said:


> 😁😁
> 
> As a first time RAM watercooler here is my quick run down.
> 
> 1/ Don't buy Alphacool modules from Aquacooling.de, they have bad stock that they are trying to shift
> 2/ Removing the heatspreaders is a nightmare, use a heat gun, take extreme care of the tiny SMDs 🤣🤣
> 3/ Make simple bends from CPU to RAM block if using PETG tubing
> 4/ Pay attention to get the correct thickness thermal pads
> 5/ You are not going to be able to switch the modules quick and easy, so you learn your memory on air, get stable settings configs sorted, then you put them under water
> 
> Through the trial and tribulations ive been through im happy to have them water cooled


What are your thermals like under load? I unfortunately got bad kit where I had to remove the heatsync since even with a 120mm fan running on it it'd go up to 48 degrees, they max out at 42 now with nothing on it but long term I might look into water cooling with a custom loop entirely. I use an ITX pc though so it might be a little more tedious


----------



## mongoled

umea said:


> What are your thermals like under load? I unfortunately got bad kit where I had to remove the heatsync since even with a 120mm fan running on it it'd go up to 48 degrees, they max out at 42 now with nothing on it but long term I might look into water cooling with a custom loop entirely. I use an ITX pc though so it might be a little more tedious


No idea unfortunately, these Patriot Viper Steels do not have a thermal diode...


----------



## XPEHOPE3

Finally managed to get stable CO (negative 18,11,5,22,16,14, where 11 and 5 are for 2 best cores), limits (PPT/TDC/EDC 175/80/140) & scalar (5). Here are the results (previous on the left, w/o CPU OC):













Notice how latency improved with just CPU OC. Should it be possible to boost frequency of just core 0, it would also improve the same way.

y-cruncher, OCCT and TM5 temps and clocks:




















With those settings I only get throttling on PROCHOT and VID, not on FIT or TDC (checked during y-cruncher).



Spoiler: Benchmarks (either single|multi, or time|rate, etc)




BenchBeforeAfterCPU-Z636,5335066,6660,9755162,05SuperPi 4M35,56434,110Cinebench R23153511472159512016Geekbench 516769217,66717459516Geekbench 36699,535724,759343,75 mem9393 mem6897368419409 mem9416 memAIDA64 photoworxx28057,83328293Intel MLC71,075 ns51222,875 read18,625 ns cache20,25 ns cache70,3 ns51231,9 read17,98 ns cache19,42 ns cacheLinpack Xtreme (1-3-3)87,072 s250,911 Gflops80,97269,818xmrig 1M126,219 s7922,767 h/s120,3728307,567xmr-stak-rx nanopool, 15min612,792 h/s7353,6 h/s667,0758004,7testmem5 1usmus_v323555 s23487 sFF XIV208,384 fps28675210,33291507z 32MB dict8199,2 compr10055 decom847710506rar3891,53955DRAM calculator106,47 easy206,56 dflt3,2 ns57,4 ns106,68205,693,155,8time spy9196139824208 extreme6927 extreme94411401344266922fire strike347872584814133348512632814365

3DMark CPU124816All (12)Before93218603639486058405933After97219173696497561746261


----------



## gled_fr

Audioboxer said:


> First thing I wanted to make sure I can do, boot RttPark 3. Regulars in this topic might remember all the issues I was having doing that on my 3200C14 set, well, here we are, 6/3/3 and no issues at 3800.
> 
> Anyway, no time to play any further, will be back later tonight for the real fun!


Curious if you can stabilize flat 14's with gdm off and 1t


----------



## Koboldness

gled_fr said:


> Curious if you can stabilize flat 14's with gdm off and 1t


It should be easy with the ram


----------



## Audioboxer

gled_fr said:


> Curious if you can stabilize flat 14's with gdm off and 1t


Not sure if I'll manage it. My baseline came back stable










Only thing I left a bit higher than normal for now was tRFC.

But switched tRCDRD to 14 gets me fast errors on test 6. Gone as high as 1.55v.

*edit* - LOL










That's how quick it can fall at 14. I guess VSOC might come into it.


----------



## bukbuk123

I bought a 5900x and tried overclocking.

I overclocked more than 4133mhz, and I heard a ticking sound and it was unstable.

Finally, I overclocked at 4066mhz, passed tm5 20 cycles, and there's no whea19 error in the Event Viewer.
I wonder if this is a safe voltage and a safe setting.

Anyone help me


----------



## gled_fr

Audioboxer said:


> Not sure if I'll manage it. My baseline came back stable
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Only thing I left a bit higher than normal for now was tRFC.
> 
> But switched tRCDRD to 14 gets me fast errors on test 6. Gone as high as 1.55v.
> 
> *edit* - LOL
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> That's how quick it can fall at 14. I guess VSOC might come into it.


Funny I have the same issue with my 3600C14, although I believe yours to be a better bin ( mine are 14 15 iirc at xmp )... I did not go above 1.52 Vdimm though...


----------



## Audioboxer

gled_fr said:


> Funny I have the same issue with my 3600C14, although I believe yours to be a better bin ( mine are 14 15 iirc at xmp )... I did not go above 1.52 Vdimm though...


Can you run 3600 flat 14s at 1.45v? If you can then there really isn't any difference and it might just be G.SKILL trying to make a bit more money. Maybe a few of those bins in your model range couldn't do 3600 flat 14.

@mongoled I found out what gets me tPHYRDL on one stick, it's tCL 14 when ran at 1T. Like you if I switch to tCL 15 at 1T it goes back down to 26. Makes me wonder if I should just aim for flat 15's @ 1T.

I can actually boot 1T without messing with any resistances, but LOL at those errors










As you can see tPHYRDL to 28.


----------



## Veii

mongoled said:


> 1/ Don't buy Alphacool modules from Aquacooling.de, they have bad stock that they are trying to shift


Oh how so ?
What defines "bad" stock ?
Do they still use oversized screws not round thin ?


mongoled said:


> Through the trial and tribulations ive been through im happy to have them water cooled


I'd only get blocks for using "actual heatsinks"
Cooling the heatsinks with water is another topic


bukbuk123 said:


> no whea19 error in the Event Viewer.


Have you checked here ?








#20 is something else
#18 is voltage related, CCD and cores
#19 is IO related from the chipset away or broken DPM powermanagement/issues (USB, Audio, NIC, Chipset overheating, LCLK issues with PCIe 4.0 and so on)


BarrettDotFifty said:


> Any ideas about what's next to improve for this particular setup or perhaps there's something odd in this state?


tRTP 5 if you can afford it. It can potentially run on Dual Rank. Does on intel, soo i see no issues
CCD is huge for you - drop it at least 1020 or lower - try after which point y-cruncher starts to crash (all tests)
Doublecheck your SOC loadline when opening TM5, if it will not drop lower than 1087.7mV. If it reaches 1087mV, then give it at least 5mV more and lower switching frequency as low as possible
Smart Powerstages efficiency drops strongly at 700Khz and higher. Well generally so does also noise increase.
Doesn't matter much for the CPU side, but does a lot for the SOC side.

Later try to drop both tRDRD & tWRWR DD's to 2. Either it works or it breaks
If it breaks, you should likely run tWRRD 7, or increase SCLs to 4 as lower is not always better. Test it and do not use the first or 2nd run of Aida64. Give it time to settle to idle mode after the first run (on a reboot)
The CPU needs to run something first, before it settles down to their C-States.
~ meaning the first result of Aida64 is always strange and you should skip/ignore it.


PJVol said:


> You seem to miss the point, that is regardless of how much vdd18 was pumped in,
> I found that GEMM test clearly shows instability at some point of the CPU-DRAM path, when DF is overclocked above 1900.


Will try to get some results


XPEHOPE3 said:


> Can you please post your whole 4.85 CPU config? Limits, vcore offset, LLC, scalar. I assume you did test y-cruncher with those and it passed? Does it also hold 4.85 for e.g. 2nd and 3rd tests? Do you still not run CoreCycler/OCCT per core SSE full?
> From my CPPCs I think my sample should be better than yours, yet one of my best cores requires -5 CO offset 💩 to pass CoreCycler. And in any case y-cruncher doesn't hold 4.85 for 2-3 tests because of PROCHOT limit, hitting 85°C at 4.5GHz.
> 
> Also do you by any chance have screenshots from the tool with AMD monitor and per core monitor showing current FIT, amperage, etc. during CB23 run when you do hit 4.85? I keep seeing suspicious CCA frequency limiter being hit sometimes even lower than PROCHOT. I think it's voltage-related and wonder why I hit it and you don't


Many requests.
Ok i'll see what i can do
AVX only holds 4.85 if ProcHOT is not reached or TDC limit is not reached.
CCA covers throttle on TDC, EDC & VIDmax throttle
VIDmax throttle happens by FIT if PROCHOT is reached, soo maximum allowed VID is throttled ~ refusing you to hold higher clock.
Visible for me, only PROCHOT is throttled. 

When i drop CO's all by -2 i get as expected -25mhz maximum hold.
Cores peak VID 1.4v limit (another limit not VIDmax , but connected) soo they only peak at 4.825 or 4.820Ghz


----------



## Veii

Audioboxer said:


> @mongoled I found out what gets me tPHYRDL on one stick, it's tCL 14 when ran at 1T. Like you if I switch to tCL 15 at 1T it goes back down to 26. Makes me wonder if I should just aim for flat 15's @ 1T.
> 
> I can actually boot 1T without messing with any resistances, but LOL at those errors


tPHYRDL will jump down because of RTT and cLDO_VDDP issues
tCL just increases strain.
It has a predefined table , but:
Bad tPHYRDL means bad powermanagement
Increase cLDO_VDDP maybe to 920mV and it will resolve

#0's are voltage / powering issues
PCB issues


----------



## mongoled

Veii said:


> Oh how so ?
> What defines "bad" stock ?
> Do they still use oversized screws not round thin ?
> 
> I'd only get blocks for using "actual heatsinks"
> Cooling the heatsinks with water is another topic


Lookie here

Read through my subsequent posts


----------



## bukbuk123

Veii said:


> 여기서 확인하셨나요?













When I used 5800x, there was also a whea#19 error at 4000mhz, but there was no whea#19 error after changing to 5900x.
I think it's weird that whea#19 didn't happen even when I successfully boot to 4200mhz.



I can not speak English very well sorry


----------



## mongoled

Veii said:


> tPHYRDL will jump down because of RTT and cLDO_VDDP issues
> tCL just increases strain.
> It has a predefined table , but:
> Bad tPHYRDL means bad powermanagement
> Increase cLDO_VDDP maybe to 920mV and it will resolve
> 
> #0's are voltage / powering issues
> PCB issues


These tweaks help on 2 dimm configs, not so much on 4 sticks

So good advice for Audioboxer


----------



## mongoled

bukbuk123 said:


> View attachment 2521811
> 
> 
> 
> When I used 5800x, there was also a whea#19 error at 4000mhz, but there was no whea#19 error after changing to 5900x.
> I think it's weird that whea#19 didn't happen even when I successfully boot to 4200mhz.
> 
> 
> 
> I can not speak English very well sorry


What version/build of Windows 10 ??


----------



## mongoled

Audioboxer said:


> @mongoled I found out what gets me tPHYRDL on one stick, it's tCL 14 when ran at 1T. Like you if I switch to tCL 15 at 1T it goes back down to 26. Makes me wonder if I should just aim for flat 15's @ 1T.
> 
> I can actually boot 1T without messing with any resistances, but LOL at those errors
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> As you can see tPHYRDL to 28.


Veii advice is good, try it

Thats what mine does followed by bluescreen

😂😂


----------



## bukbuk123

mongoled said:


> What version/build of Windows 10 ??


Windows 10 Pro
Version 21H1
OS build 19043.1165

I think this is the most recent version


----------



## Audioboxer

mongoled said:


> Veii advice is good, try it
> 
> Thats what mine does followed by bluescreen
> 
> 😂😂


It's interesting how only one stick changes to 28 or is that quite normal? 

1T looks like it's going to be a challenge on my earlier settings anyway. I'll sleep on it. I don't mind leaving it on 2T in the meantime. But I am coming around to the idea of just going for flat 15's on 1T at 3800. That was my original goal with my other sticks which couldn't be achieved.


----------



## Requiem4u

Audioboxer said:


> It's interesting how only one stick changes to 28 or is that quite normal?
> 
> 1T looks like it's going to be a challenge on my earlier settings anyway. I'll sleep on it. I don't mind leaving it on 2T in the meantime. But I am coming around to the idea of just going for flat 15's on 1T at 3800. That was my original goal with my other sticks which couldn't be achieved.


Maybe chance RAM positions? 1T seems to be too much for my memory or CPU too. Since latency is ok.


----------



## XPEHOPE3

Audioboxer said:


> only one stick changes to 28 or is that quite normal?


My stats say yes.


Veii said:


> When i drop CO's all by -2 i get as expected -25mhz maximum hold.


Strange, I see otherwise trend: lowering CO gave me higher clocks (because temps get lower) + instability. In all tests I have +200MHz set as PBO boost offset. Maybe I should try lowering that...


Veii said:


> VIDmax throttle happens by FIT if PROCHOT is reached, soo maximum allowed VID is throttled ~ refusing you to hold higher clock.


Wow, I never paid attention to this throttle being conditional to temps!


----------



## Audioboxer

lol, before bed I pulled some of my old 3800 flat 15 notes together from trials with old RAM and tried a quick "plug and play" for GDM disabled/1T










Have to say I'm a bit surprised at how quickly it died, but at least I can run RttPark 3 with these sticks.










Found some of my older more relaxed flat 15 timings. Not gonna lie will be quite gutted if I can't get flat 15 1T stable given a lot of people manage it on bins worse than this ram. Will switch over to 2T (for some reason 2T 15 makes my tPHYRDL 28) and make sure these timings will pass before continuing to mess with resistances on 1T.


----------



## Veii

@PJVol & @XPEHOPE3
As per Request - Collection:


Spoiler: Proof of System Integrity ~ Aida64

















Spoiler: Y-Cruncher Collection ~ ProcHot Throttle












And no-thermal throttle ~ IMC










Spoiler: Remain pictures of it


































Spoiler: CPU-ID Baseline & AVX2































Spoiler: OCCT Mem & CPU / Uses HWInfo Lib - doesn't allow Tool.exe to sniff

























Spoiler: Cinebench R20 & R23


























===========================================================
R23:




















Spoiler: SiSoftware Sandra Scientific GEMM & Inter-Thread Latency Comparison












It didn't log my old 5600X local scores, sad. 90GB/s was not a bug ~ likely 92 wasn't either, but 2nd CCD eats 18-20A EDC, and SOC eats a lot.
I really don't have an easy time power managing it. Very happy that it performs kind of near your guys results


Bios Settings
* Keep in mind, 90% of what you see are Results with Sniffing Tools running. Do not take scores serious. 
Date has been included on each of them, in order to verify actuality & was tested without reboots


----------



## Veii

Little shiny update








Testing out new offbrand 15.7W/mK Paste
CPU Jumps now quite fast between 12-15c in less than a sec
But aircoolers are not suited for such ! Scales positive sub 60c, but surely not for air coolers by it's reactivenes ~ yet weak perf beyond 72c
Same fab as the "too expensive" Thermalright TFX ~ but half the Price (SYY 157)

I'd need Kingpin KPx or Noctua NT-H2 , if i ever want to keep this sub 60c
But the paste is great for AIOs i feel like. No Airconditioner to do scientific testing


Spoiler: 5600X Lapping history backwards














































Learned from it:

Unlike TSMC
14nm and 12nm
GLFO 7nm (3xxx and 5xxx Series)
Has 3 Uniqueness'es

There are no more side solderclamps / while it did improve for 12nm - yet the CPU remained strongly Concave before GLFO
Like Igor from Igorslab mentioned here ~ GLFO's given Heatspreader is soft and adapts the first burn shedule. = *Swapping CPU Coolers likely will result in worse cooling perf* unless it performs superior to your old setup
The out-of-the-box flatness is beyond decent. Just be sure to tighten it down well, as it's more thick than early generations and transfers heat slower/worse . It got very reactive after lapping it around 0.5mm lower than the rest
I can not confirm the stamps do not come from the FAB and it intentionally was bulkier on one of the sides to offset stamping pressure
But what i can clearly see, is the remain stamp circle and that it intentionally was designed thicker on the place
What i can also very well see - remains that Ryzen is Concave. Even when the current shape is more like a seawave or sandbeach, than really having "an own" shape
* yet you should remember, that it could be one of the sides being more tighten down compared to the others.

I'll potentially got a 5600G to play around and some other little surprises
Right now focusing on building Boutique Builds , to pass through the monetary times. Then hopefully soon create more content and change continents for good. 

Probably should have started the post with this


Spoiler: Goodbye 40th unit














Now that warranty is gone for good

Notes for the Future:

Marble-Stone is more polished than glass. Results appear more shiny
800 & 1200 Grit are still enough ~ but tape the corners and not the sides. Also only switch to 1200 Grit for pure copper, to have a very shiny result
Do not change your coolers after you've decided what to use.
Honestly nothing to learn. I did everything right, but it's too exhausting 4 + 2h (2nd day)
Only fantastic samples deserve long lapping. Staying on the Nickel silver side is more than acceptable, as the Heatsink will adjust to your Cooler anyways.
Just makes sense to slim it down slightly and remove the stamp imprint slightly


----------



## boldenc

boldenc said:


> View attachment 2521537


Heyo, what is the reason for getting worse results with tighter latency @ 14-14-14 ?


----------



## PJVol

Veii said:


> The out-of-the-box flatness is beyond decent


So, IOD is under "RYZ" and CCD under "EN" ? )
Do you know what alloy the heatspreader is made of ?



Veii said:


> It didn't log my old 5600X local scores, sad. 90GB/s was not a bug ~ likely 92 wasn't either


Thanks.
The GEMM score numbers look kinda discrete and similar to what I get with different DF clock.
Though, the inconsistency of FFT scores is conspicuous. Hmm... 
1900 result with question mark (?) looks weird as well, as if CPB turned off.
Just run a bench once more, to make sure results are reproducible.


Spoiler: GEMM and FFT


----------



## Audioboxer

Audioboxer said:


> lol, before bed I pulled some of my old 3800 flat 15 notes together from trials with old RAM and tried a quick "plug and play" for GDM disabled/1T
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Have to say I'm a bit surprised at how quickly it died, but at least I can run RttPark 3 with these sticks.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Found some of my older more relaxed flat 15 timings. Not gonna lie will be quite gutted if I can't get flat 15 1T stable given a lot of people manage it on bins worse than this ram. Will switch over to 2T (for some reason 2T 15 makes my tPHYRDL 28) and make sure these timings will pass before continuing to mess with resistances on 1T.












OK so I took a combination of the timings I was trying to get my old memory stable at flat 15 (never managed it) and what I recently passed with this memory at tCL14 and just made sure it was OK for 25 cycles. It seems to be, though I need to run y-cruncher.

Anyway, my bigger question is what to do about 1T/resistances. My old memory wasn't really for working with resistance tweaking so this is a new part of the memory end game for me.

I tried the 6/3/3 I often see combined with 40/20/30/20, no such luck getting 1T stable. Any other combinations work well? 36.9 is ProcODT on auto with this memory, again, I see most people around here but I guess for 1T I can play around with it.


----------



## mongoled

Audioboxer said:


> OK so I took a combination of the timings I was trying to get my old memory stable at flat 15 (never managed it) and what I recently passed with this memory at tCL14 and just made sure it was OK for 25 cycles. It seems to be, though I need to run y-cruncher.
> 
> Anyway, my bigger question is what to do about 1T/resistances. My old memory wasn't really for working with resistance tweaking so this is a new part of the memory end game for me.
> 
> I tried the 6/3/3 I often see combined with 40/20/30/20, no such luck getting 1T stable. Any other combinations work well? 36.9 is ProcODT on auto with this memory, again, I see most people around here but I guess for 1T I can play around with it.


Set 1T and AddrCmsSetup to 56, the other setup timings @0

Dont change anything else, see if there is a difference and report back ...


----------



## Audioboxer

mongoled said:


> Set 1T and AddrCmsSetup to 56, the other setup timings @0
> 
> Dont change anything else, see if there is a difference and report back ...












3 cycles passed. Admittedly the resistances and setups are my biggest knowledge gap. For example, I thought the setups were really just there to help you POST. This memory has no issues booting into Windows with GDM disabled and 1T at 0-0-0. I just end up with TM5 errors.

The only thing that has changed is tPHYRDL back down to 26 because of 1T and the DrvStr's all changed back to 20. For some reason tCL15 and 2T had them automatically go to 24.

So I guess my question is what does this mean? I often see people play with resistances and Rtt to do GDM Disabled and 1T. Mine are just on AUTO lol. Although in those instances where 6/3/3 or 40/20/30/20 are used I see 0-0-0 on setups.


----------



## mongoled

Audioboxer said:


> 3 cycles passed. Admittedly the resistances and setups are my biggest knowledge gap. For example, I thought the setups were really just there to help you POST. This memory has no issues booting into Windows with GDM disabled and 1T at 0-0-0. I just end up with TM5 errors.
> 
> The only thing that has changed is tPHYRDL back down to 26 because of 1T and the DrvStr's all changed back to 20. For some reason tCL15 and 2T had them automatically go to 24.
> 
> So I guess my question is what does this mean? I often see people play with resistances and Rtt to do GDM Disabled and 1T. Mine are just on AUTO lol. Although in those instances where 6/3/3 or 40/20/30/20 are used I see 0-0-0 on setups.


RTT values when on AUTO seem to be effected by memory training though I have not been able to spot a consistent pattern at all !

Just so you are aware using AddrCmdDrvStr @56 effectively makes 1T "1.5T" .

Does not look like I will be able to get tRCDRD stable @14, watercooling has helped somewhat, but not enough to get round the weaknesses of the one stick....


----------



## Audioboxer

mongoled said:


> RTT values when on AUTO seem to be effected by memory training though I have not been able to spot a consistent pattern at all !
> 
> Just so you are aware using AddrCmdDrvStr @56 effectively makes 1T "1.5T" .
> 
> Does not look like I will be able to get tRCDRD stable @14, wastercooling has helped somewhat, but not enough to get round the weaknesses of the one stick....


Ah right, so the people I see with 0-0-0 are running true 1T? I guess my next question then is should I go back to 0-0-0 and play around with resistances/DrvStr? Or if things don't work on the 6/3/3 and 40/20/30/20 am I pretty much out of luck?

Also if 56 is effectively 1.5T is that pretty similar to GDM on/1T?

Thanks for knowledge!

And yeah, tRCDRD really is the devil LOL


----------



## mongoled

Audioboxer said:


> Ah right, so the people I see with 0-0-0 are running true 1T? I guess my next question then is should I go back to 0-0-0 and play around with resistances/DrvStr?
> 
> Also if 56 is effectively 1.5T is that pretty similar to GDM on/1T?
> 
> Thanks for knowledge!


No! GDM does other things that we dont see, where as using the AddrCmdDrvStr setup timing does not.

Yes, if they are running 0-0-0 without GDM enabled its "pure" 1T, with GDM enabled other things are adjusted which we dont know, but comparing performance between these two configs shows clear differences.

Somewhere Veii explains this in a bit more detail



site:overclock.net AddrCmdDrvStr veii - Google Search



Happy hunting


----------



## Audioboxer

mongoled said:


> No! GDM does other things that we dont see, where as using the AddrCmdDrvStr setup timing does not.
> 
> Yes, if they are running 0-0-0 without GDM enabled its "pure" 1T, with GDM enabled as other things adjusted we dont know, but comparing performance between these two configs shows clear differences.


Great, I'd prefer this over GDM enabled then 

I've seen another 3600C14 set manage with 0-0-0 so I guess I'll try a bit more. I guess if I can boot with 0-0-0 it's promising, but errors quickly on 6 in TM5 may suggest my IMC isn't good enough?

*edit* - Just noticed you added a better way to search this forum, thanks! Always found it challenging doing a search lol. A lot of advice seems to be for SR memory, but I'll give this DR set a go!


----------



## mongoled

Audioboxer said:


> Great, I'd prefer this over GDM enabled then
> 
> I've seen another 3600C14 set manage with 0-0-0 so I guess I'll try a bit more. I guess if I can boot with 0-0-0 it's promising, but errors quickly on 6 in TM5 may suggest my IMC isn't good enough?


You can try

1/ Increasing ClkDrvStr i.e. 60.0 ohms
2/ Increasing vSOC
3/ Play with different ProcODT values, the lower the ProcODT the less vSOC you should try to use as well as lower ClkDrvStr

Think of it as a balancing act !


----------



## Audioboxer

mongoled said:


> You can try
> 
> 1/ Increasing ClkDrvStr i.e. 60.0 ohms
> 2/ Increasing vSOC
> 3/ Play with different ProcODT values, the lower the ProcODT the less vSOC you should try to use as well as lower ClkDrvStr
> 
> Think of it as a balancing act !


9 variables, balancing act is the best way to describe it  I need to do some more reading and I'm doing that with Veii's posts from above










Speaking of throwing things at a wall, this got me over a minute in. 6/3/3 with ProODT 36.9 was erroring out within seconds on 6. So I guess there might be hope for me yet if I do some more reading and find my magical "balance".

Error 10 suggest RttNom being on disabled will be a no go.


----------



## Audioboxer

boldenc said:


> Heyo, what is the reason for getting worse results with tighter latency @ 14-14-14 ?


.8 of a difference could easily be attributed to background apps. I wouldn't worry about it.

As for expecting much lower on tCL14, while I'm far from an expert GDM on can "hide" minor issues/chokes on performance. I'd recommend trying to get timings stable with GDM disabled and 2T first.

You can see I just learned above GDM disabled with 1T and AddrCmdSetup at 56 while "similar" to GDM enabled/1T being "1.5T", it is a more "pure" 1.5T.


----------



## Audioboxer

@mongoled I seen @Veii mention here that DR tends to need higher ClkDrvStr. Given the majority of this topic is SR, a lot of the values I am seeing do seem to be for SR. Veii mentions a notch or two above 40










But there is nothing above 60 other than 120, and while it gave my anxiety to run something that high the memory did hold out for 9 minutes before crashing, unsurprisingly, on 4 (value too high).

This is longer than the 1 minute 42 I it held out at 60. So I guess progress, somewhat. Maybe Veii can chime in when they have time for some further advice on DR. I'm reading as much as I can just now but still feeling a bit lost at understanding what is helping stability go longer versus what has to be balanced to allow ClkDrvStr to have a chance at 40/60. It's my understanding my VDDG voltages should be fine for matisse and could even go to 0.95v.


----------



## Koboldness

Audioboxer said:


> You can see I just learned above GDM disabled with 1T and AddrCmdSetup at 56 while "similar" to GDM enabled/1T being "1.5T", it is a more "pure" 1.5T.


This is not true. According to @Veii GDM on is more like 2.5T. There is his image about it. Avoid GDM like a plague.


----------



## Audioboxer

Koboldness said:


> This is not true. According to @Veii GDM on is more like 2.5T. There is his image about it. Avoid GDM like a plague.


Yeah, what you said, I know from this topic GDM enabled should be avoided like the plague so thanks for the correction.


----------



## dimi0815

How do I get rid of WHEA19 errors? For many BIOS versions, I wouldn't see any of these show up even with 2000 MHz or 2100 MHz IF. As of the latest BIOS for MSI B550 Unify-X, I am plagued by tons of WHEA 19 errors as soon as I go over 1900 IF.

What's the most promising combination of ProcODT, RTTs and DrvStr values to get rid of these using 2x 16 GB sticks (B-Die, dual-ranked)?


----------



## Audioboxer

dimi0815 said:


> How do I get rid of WHEA19 errors? For many BIOS versions,* I wouldn't see any of these show up even with 2000 MHz or 2100 MHz IF*. As of the latest BIOS for MSI B550 Unify-X, I am plagued by tons of WHEA 19 errors as soon as I go over 1900 IF.
> 
> What's the most promising combination of ProcODT, RTTs and DrvStr values to get rid of these using 2x 16 GB sticks (B-Die, dual-ranked)?


Are you absolutely sure, 2100 IF and no WHEA errors? Just flash back to the earlier BIOS and reconfirm that is the case.

I have a B550 Unify-X and get WHEA the second I go over 1900.


----------



## Veii

Audioboxer said:


> 9 variables, balancing act is the best way to describe it  I need to do some more reading and I'm doing that with Veii's posts from above
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Speaking of throwing things at a wall, this got me over a minute in. 6/3/3 with ProODT 36.9 was erroring out within seconds on 6. So I guess there might be hope for me yet if I do some more reading and find my magical "balance".
> 
> Error 10 suggest RttNom being on disabled will be a no go.


sorry for confusing
#10 suggests to increase NOM - increase the ohm
Some bioses have it as dividers, some have it as translated out value in ohms
Soo stronger = more ohm, weaker = less ohm

#4 is then a pure PCB crash, as it was "too much" 








Either you can figure out the combination, or you might want to give 920mV cLDO_VDDP a try and scale up procODT one notch
That should allow less ClkDrvStr to be used, but less RTT_PARK is generally better ~ as noise aside, it's quite heavy taxing to the dimms.
Aside from resulting in more heat, it also will max out in voltage earlier than /3 or higher.

You can work towards getting RTT_WR /2 to run, dual rank should be able to do it - and A2 PCBs too
But while it's better in for example allowing 13-13-13 to run, it will fail on higher MT/s
A tradeoff. Higher potential MT/s = balancing RTTs and signal integrity
Lower timings = using stronger filtering (RTT_WR /2) but also far higher VDIMM with low PARK
All a cooling thing i guess

I can not recommend enough to start with higher tRRD & tWTR, also higher tWR and tRTP ~ if you want to bruteforce lower tRCD
Lower primaries at the end still win, even when tertiaries do give a lot of perf at first. They limit strongly how low your primaries can go.
You might want to start using tCKE , if you have struggle running pure 1T on it








This is usable in it's current state
Not perfect (finished), but good enough 

To SETUP timings you should only resolve at the very very end.
The end where you figured after which voltage you PCB crash - and RTTs do nothing
Soo likely after 10-12 more TM5 passes with ruled out cLDO_VDDP , procODT and tCKE options
Who knows, you might even be able to decrease cLDO_VDDP , if your memory controller is great. That should decrease procODT (keep an eye on tPHYRDL desync) and so generally improve noise
Low noise signal then can be easily amplified with 120ohm ClkDrvStr. But beyond 60 generally doesn't lead to good results. Yet it can work 
DR or SR ,is just a PCB strain difference ~ an RTT difference and a bit of timing difference
But not much of one


PJVol said:


> Thanks.
> The GEMM score numbers look kinda discrete and similar to what I get with different DF clock.
> Though, the inconsistency of FFT scores is conspicuous. Hmm...
> 1900 result with question mark (?) looks weird as well, as if CPB turned off.
> Just run a bench once more, to make sure results are reproducible.


Will do,
Just picked some online results and tried to understand how they where run

I do think that GEMM test is barely scaling with MCLK but rather a powering thing
Because of such i'd want to test 3800C14-14-14 on it with the same high voltages ~ just to rule out it's not something as simply as a "powerbudget difference"
We'll see ~ been some time want to remake a bit more extreme 14-14. 13-13 won't run beyond 3633  Last 14-14 was at 1.6v. 1.65 should give me a bit more playroom, might even outperform it we'll see 


PJVol said:


> So, IOD is under "RYZ" and CCD under "EN" ? )
> Do you know what alloy the heatspreader is made of ?



















The stamps by accident align 
The font and QR code is at the bottom half, but the RYZEN is font is centered
The stamp on itself remained a long time there,

If we go by the theory that this was by my heatsink deformed
It would show the top left and top right - still having a holding clamp stamp
While the center is pressed down further, but no where near close to centered as first two gens








That one had a more strange shape, while 12nm improved from it
but both had side clamps for holding the chip before solder








More smooth center - they improved 12nm, but yes both had long living side clamps ~ which all of them result in a circular cooling shape at the start (Concave)
Funnily on all of the units, the outer outer ring, is the one that goes down first. Like a hollow ring on the sides, even without the intention to smooth the edges. One could thing they are Convex that way, but really are not 

Alloy material, sadly no
I have fun to collect labor fingerprints of them ~ seeing if they improve or not
It certainly is actively worked on, and thanks to Igor's research we know they deform now (good thing but i am not sure because of cooler swap issues)
I'll confirm or deny the half half lifted strange result with another 5000 series ~ if it was my 2 cooler screws deforming it or it's out of the fab that uneven
Kind of want to get an APU (waiting atm) but my Ram kit will never do 4300+ (A0 PCB too weak). Not even remotely exceed 1.68v even when cooling is funnily no issue with non focused single fan
We'll see here too. Tempted to learn moving in the 5000MT/s area (saw a Rev.E suicide run of 2467 FCLK on it @ 43ns [which is high for it]), but certainly need better RAMs for such


----------



## Requiem4u

dimi0815 said:


> How do I get rid of WHEA19 errors? For many BIOS versions, I wouldn't see any of these show up even with 2000 MHz or 2100 MHz IF. As of the latest BIOS for MSI B550 Unify-X, I am plagued by tons of WHEA 19 errors as soon as I go over 1900 IF.
> 
> What's the most promising combination of ProcODT, RTTs and DrvStr values to get rid of these using 2x 16 GB sticks (B-Die, dual-ranked)?


It is mainly VSOC, VDDP, VDDG CCD and IOD. Test running Aida64 men & cache bench and Hwinfo64 tells how many errors you got. VDDP and CCD lower can be better.


----------



## Veii

dimi0815 said:


> How do I get rid of WHEA19 errors? For many BIOS versions, I wouldn't see any of these show up even with 2000 MHz or 2100 MHz IF. As of the latest BIOS for MSI B550 Unify-X, I am plagued by tons of WHEA 19 errors as soon as I go over 1900 IF.
> 
> What's the most promising combination of ProcODT, RTTs and DrvStr values to get rid of these using 2x 16 GB sticks (B-Die, dual-ranked)?


RTTs depend on the board too 
2 dimm setups , same as ITX liked 6-3-3 the most (for entry)
~ for 4 dimm boards it's not thaat great, as traces are longer. Might need more WR or less NOM ~ it's fine but not thaat great
Between 1.42-1.56ish VDIMM it was fine
That at +2 steps over SR, which moves between 32-34 ohm @ 1900 FCLK

SR:
28ohm only functions with lower than 900mV cLDO_VDDP at 1900 MCLK
30ohm only functions with high VDIMM at 2100 MCLK, else 32 was the minimum

instead of 30 for 1900 & 32+ for 2100
Usually 34 for 2100, soo that would be 40ohm for DR

Soo 36ohm for 3800 as always functioning minimum
40 for 2000, 42 for 2100
-1 on them only works when you finetune PARK, cLDO_VDDP, & ClkDrvStr
ClkDrvStr helps to lower procODT one step further, just be aware of it's side-effects written down bellow
==============================================================
Really depends how you power them
more excessive VDIMM, will lift push requirements on procODT, RTT_PARK & ClkDrvStr (can be used less)
PARK should always be as weak as you can manage to get it running. ClkDrvStr is an amplifier ~ it will also amplify a noisy signal that reached the dimms

cLDO_VDDP defines the strengthness of the signal on the traces to the dimms
IOD does help the fabric run this higher UCLK, but VDDP is what influences the memory controller (MCLK) and so also 2:1 mode results

procODT does influence the whole fabric (soo will destabilize CCDs too, if CCD voltage is too high on procODT bump)
and also the strengthness of the VDDP signal.
EDIT: 
Soo for 2:1 mode, where UCLK is low, you surely want to lower procODT as low as possible & only work with VDDP and ClkDrvStr 
~ when you go for very high MCLK results 5000+
Logically if you have access to it, you'd also want to lower CPU VDDP , but barely boards show this (still)

ClkDrvStr takes over the arrived signal to the traces and amplifies it another time
RTTs are then functioning like gates. They still all have functions as impedances (amplifiers) but here they increase or decrease the "gate" size (height)

Easiest to remember, is focusing on all ohm values as impedances (all listed at least)
They are termination impedances and are used for the opposite = resistance. Either as gates or as current (A) "filtering"
But they remain impedances in their implementation
Soo less ohm is always better, except for RTT. There all 3 of them have unique characteristics. Only WR you want strong. NOM depends on the VDIMM and noisyness of it (less is better but you can easily need a lot of it)
PARK always should be as low as possible, as low as the cleanness of your signal allows it. Or the smallest size of trace length (MB PCB depended)
NOM & PARK need to be retuned once you touch WR, as WR has priority and is capable to generate "disabled" NOM or PARK.
Disabling rarely is the way to go - but i can see it helping if you want to run as low VDIMM as possible (has barely any reason as PARK defines heat, but eh you know) 

Color Explanation:
Sidenotes & Personal-Comments


----------



## Audioboxer

Veii said:


> sorry for confusing
> #10 suggests to increase NOM - increase the ohm
> Some bioses have it as dividers, some have it as translated out value in ohms
> Soo stronger = more ohm, weaker = less ohm
> 
> #4 is then a pure PCB crash, as it was "too much"
> 
> 
> 
> 
> 
> 
> 
> 
> Either you can figure out the combination, or you might want to give 920mV cLDO_VDDP a try and scale up procODT one notch
> That should allow less ClkDrvStr to be used, but less RTT_PARK is generally better ~ as noise aside, it's quite heavy taxing to the dimms.
> Aside from resulting in more heat, it also will max out in voltage earlier than /3 or higher.
> 
> You can work towards getting RTT_WR /2 to run, dual rank should be able to do it - and A2 PCBs too
> But while it's better in for example allowing 13-13-13 to run, it will fail on higher MT/s
> A tradeoff. Higher potential MT/s = balancing RTTs and signal integrity
> Lower timings = using stronger filtering (RTT_WR /2) but also far higher VDIMM with low PARK
> All a cooling thing i guess
> 
> I can not recommend enough to start with higher tRRD & tWTR, also higher tWR and tRTP ~ if you want to bruteforce lower tRCD
> Lower primaries at the end still win, even when tertiaries do give a lot of perf at first. They limit strongly how low your primaries can go.
> You might want to start using tCKE , if you have struggle running pure 1T on it
> 
> 
> 
> 
> 
> 
> 
> 
> This is usable in it's current state
> Not perfect (finished), but good enough
> 
> To SETUP timings you should only resolve at the very very end.
> The end where you figured after which voltage you PCB crash - and RTTs do nothing
> Soo likely after 10-12 more TM5 passes with ruled out cLDO_VDDP , procODT and tCKE options
> Who knows, you might even be able to decrease cLDO_VDDP , if your memory controller is great. That should decrease procODT (keep an eye on tPHYRDL desync) and so generally improve noise
> Low noise signal then can be easily amplified with 120ohm ClkDrvStr. But beyond 60 generally doesn't lead to good results. Yet it can work
> DR or SR ,is just a PCB strain difference ~ an RTT difference and a bit of timing difference
> But not much of one
> 
> Will do,
> Just picked some online results and tried to understand how they where run
> 
> I do think that GEMM test is barely scaling with MCLK but rather a powering thing
> Because of such i'd want to test 3800C14-14-14 on it with the same high voltages ~ just to rule out it's not something as simply as a "powerbudget difference"
> We'll see ~ been some time want to remake a bit more extreme 14-14. 13-13 won't run beyond 3633  Last 14-14 was at 1.6v. 1.65 should give me a bit more playroom, might even outperform it we'll see
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> The stamps by accident align
> The font and QR code is at the bottom half, but the RYZEN is font is centered
> The stamp on itself remained a long time there,
> 
> If we go by the theory that this was by my heatsink deformed
> It would show the top left and top right - still having a holding clamp stamp
> While the center is pressed down further, but no where near close to centered as first two gens
> 
> 
> 
> 
> 
> 
> 
> 
> That one had a more strange shape, while 12nm improved from it
> but both had side clamps for holding the chip before solder
> 
> 
> 
> 
> 
> 
> 
> 
> More smooth center - they improved 12nm, but yes both had long living side clamps ~ which all of them result in a circular cooling shape at the start (Concave)
> Funnily on all of the units, the outer outer ring, is the one that goes down first. Like a hollow ring on the sides, even without the intention to smooth the edges. One could thing they are Convex that way, but really are not
> 
> Alloy material, sadly no
> I have fun to collect labor fingerprints of them ~ seeing if they improve or not
> It certainly is actively worked on, and thanks to Igor's research we know they deform now (good thing but i am not sure because of cooler swap issues)
> I'll confirm or deny the half half lifted strange result with another 5000 series ~ if it was my 2 cooler screws deforming it or it's out of the fab that uneven
> Kind of want to get an APU (waiting atm) but my Ram kit will never do 4300+ (A0 PCB too weak). Not even remotely exceed 1.68v even when cooling is funnily no issue with non focused single fan
> We'll see here too. Tempted to learn moving in the 5000MT/s area (saw a Rev.E suicide run of 2467 FCLK on it @ 43ns [which is high for it]), but certainly need better RAMs for such


Thanks for the response Veii, I've been reading quite a lot of your older posts speaking to other posters about ProcODT, Rtt's and DrvStr's. I'm understanding them better individually, but struggling with putting them all together.

When this passed










It lured me into thinking switching over to 1T should just be about voltages/resistances. But given your advice above I'll put tRRDS to 6, tRRDL to 8, trtp to 8 and tWR to 16 before going any further. I'll increase VDIMM to 1.5v (cooling is fine).

Switching to 1T boots into Windows with no changes to the above, but quick errors on 6. Adding 56 to AddrCmdSetup seems to stabilise 1T but mongoled explained to me that is like 1.5T.

I guess where I'm struggling is where do I start with 1T pure? You talk about VDDP and ProcODT first but then all the Rtt's and DrvStr's seem to come into play at the same time for balancing. Right now I feel like I have 8 or 9 variables to change without a baseline. Unless I go 6/3/3 which seems to be quite common.

If my memory wasn't booting with certain values it would "help"  It seems I can boot 1T with just about anything! lol

For example










If this were to be a "baseline" of sorts I'd be wondering what to put together first with ProcODT/Rtt's/DrvStr's and voltages to try and get it passing TM5.

But with the often seen 6/3/3 and 40/20/30/20 it errors on 6 first very quickly










Dropping ProcODT down to 34.3 skipped the 6 error but resulted in 12 then 2










And finally ClkDrvStr 60 manages the furthest, 8 minutes 50 and then crashes on 10










Which then makes me think is it actually the timings because of a crash on 10? (tWR/tRDWR/tWRRD/etc) or are my Rtt's and DrvStr's unstable still?  

Feel like I'm spinning soo many plates at once, probably because of a false sense of confidence if something passes at 2T, the timings should be fine for 1T and it'll just be the resistances and voltages. Clearly not quite.

What have I learned so far? Well, I think ProcODT of 34.3 is going to be "better" than 36.9 for me. It seems as if 40/20/30/20 might not work well enough on my RAM. So far ClkDrvStr 60 seems to be carrying for longer. 6/3/3 seems like a "baseline", disabled/3/1 seems to result in more crashes around RttNom not being strong enough.

I'll keep trying! lol It seems as if GDM disabled and 1T should be achievable on this RAM in _some_ configuration.

*edit - *Went back and read some more Veii comments and it seems to be 60/20/40/20 is a choice more than 60/20/30/20. Well, with 40 on CsOdtDrvStr I had to drop ProcODT down to 30 to stop it crashing on 6 within a minute










So, 10 minutes is further than 8 minutes, but a crash on 4 suggests too high Rtt/DrvStr


----------



## whocares7

Hello,

Seems like this Patch C made the things a bit messier for my 24/7 stable setup (Patch A).









Some single #4/6 errors still occur occasionally in the very end of stability test.
I'm wiggling around RTTs Auto or 7/3/2. 6/3/3 produce cold boots.


----------



## XPEHOPE3

boldenc said:


> Heyo, what is the reason for getting worse results with tighter latency @ 14-14-14 ?



With GDM on you can never be sure as it fiddles with some timings under the hood
You've got +100 CPU MHz in the first screen, and frequency of Core #0 influences Aida64 latency test
If tPHYRDL on B2 slot in the first setup is 26 and in the second setup is above 26, it can produce latency bump
Aida64 latency is better measured w/o Windows Defender running, as well as other tasks e.g. Steam (but in the same environment). Also one should run the test multiple times (double click on the cell with the result) and then pick some value from resulting distribution with clear outliers removed (mean/median/lowest/... etc)
I once caught a case with overtightened tRTP giving higher latency (tRTP 8 > tRTP 10)


----------



## Veii

Audioboxer said:


> Switching to 1T boots into Windows with no changes to the above, but quick errors on 6.


Error #6 means mostly 20mV or more missing in VDIMM (well in result amperage, how ever you amplify it)
#0,#2,#12 and rarely but someday #1 all mean slightly missmatched voltage. Often it's +/- 1 step = 10mV

#6 means more than 20mV soo it likely is simply lack of VDIMM
Let me repost a PM answer here, it fitts









This GDM comparison took a long time to make
1.6v was what i needed for pure 1T ~ while 2T was around 1.52ish
If your timings are harsh, it can happen that you destabilize your CPU too.
Started first with XMP , then with 16-16-16 to push FCLK. Been a lot of work till i get to a point of "just playing with timings"
And still every time i change something little (which destabilizes instantly) it can mess up my CPU voltages.
Soo i often switch VDDG voltages and procODT to make it slightly better and less voltage used. Yet if it can not reach 48.5, i do something wrong.
That's where i like Aida64, i know how it behaves and what bandwidth i have to reach.
If anything starts to throttle ~ it will be instantly seen

But till you get to the point where you can afford to run 1T ~ it will need a lot of time
Curve optimizer will change how consistent and stable your cache + latency results are
They will change how much you can drop VDDG CCD.
Then every MCLK step you take, will destabilize the fabric again and you have to re'figure out the voltages for the CPU
It's very recommendable to have baselines and not just start out of nowhere.
Timings will drop slowly slowly, but for example if i change tRRD to 1 more , it is unstable. One less and it's unstable 

What makes sense, is to take a break from pushing lower and lower primaries, and just jump down to lower frequency , use stupid low latency timings and see how RTTs behave and where you max out your memory/pcb. At which voltage they do not function anymore. On this you adjust RTTs and come back to your old baseline ~ with hopefully better powering
Doing things back and forth, you'll get 1T to run
But "just changing it" will not work
You will surely need to spend over 20h on it (debugging) minimum 

EDIT:
Yet all that work required is nothing - as you start with a baseline
Compared to coming from GDM, where nothing is reusable and you can start from scratch.
It's just not worth to spend time with GDM , even when it has helpful properties


----------



## umea

Audioboxer said:


> Thanks for the response Veii, I've been reading quite a lot of your older posts speaking to other posters about ProcODT, Rtt's and DrvStr's. I'm understanding them better individually, but struggling with putting them all together.
> 
> When this passed
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> It lured me into thinking switching over to 1T should just be about voltages/resistances. But given your advice above I'll put tRRDS to 6, tRRDL to 8, trtp to 8 and tWR to 16 before going any further. I'll increase VDIMM to 1.5v (cooling is fine).
> 
> Switching to 1T boots into Windows with no changes to the above, but quick errors on 6. Adding 56 to AddrCmdSetup seems to stabilise 1T but mongoled explained to me that is like 1.5T.
> 
> I guess where I'm struggling is where do I start with 1T pure? You talk about VDDP and ProcODT first but then all the Rtt's and DrvStr's seem to come into play at the same time for balancing. Right now I feel like I have 8 or 9 variables to change without a baseline. Unless I go 6/3/3 which seems to be quite common.
> 
> If my memory wasn't booting with certain values it would "help"  It seems I can boot 1T with just about anything! lol
> 
> For example
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> If this were to be a "baseline" of sorts I'd be wondering what to put together first with ProcODT/Rtt's/DrvStr's and voltages to try and get it passing TM5.
> 
> But with the often seen 6/3/3 and 40/20/30/20 it errors on 6 first very quickly
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Dropping ProcODT down to 34.3 skipped the 6 error but resulted in 12 then 2
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> And finally ClkDrvStr 60 manages the furthest, 8 minutes 50 and then crashes on 10
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Which then makes me think is it actually the timings because of a crash on 10? (tWR/tRDWR/tWRRD/etc) or are my Rtt's and DrvStr's unstable still?
> 
> Feel like I'm spinning soo many plates at once, probably because of a false sense of confidence if something passes at 2T, the timings should be fine for 1T and it'll just be the resistances and voltages. Clearly not quite.
> 
> What have I learned so far? Well, I think ProcODT of 34.3 is going to be "better" than 36.9 for me. It seems as if 40/20/30/20 might not work well enough on my RAM. So far ClkDrvStr 60 seems to be carrying for longer. 6/3/3 seems like a "baseline", disabled/3/1 seems to result in more crashes around RttNom not being strong enough.
> 
> I'll keep trying! lol It seems as if GDM disabled and 1T should be achievable on this RAM in _some_ configuration.
> 
> *edit - *Went back and read some more Veii comments and it seems to be 60/20/40/20 is a choice more than 60/20/30/20. Well, with 40 on CsOdtDrvStr I had to drop ProcODT down to 30 to stop it crashing on 6 within a minute
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> So, 10 minutes is further than 8 minutes, but a crash on 4 suggests too high Rtt/DrvStr


We are basically in the same seat although I got 3800cl15 flat running on 1t with 56-56-56 setup timings. I'm going to go back to 2t and see if I can grt 3800cl14 running and then seeing if I can transfer it to 1t. Although trying to figure out how to get it running stably by juggling procodt etc is a pain...


----------



## XPEHOPE3

Veii said:


> Bios Settings
> * Keep in mind, 90% of what you see are Results with Sniffing Tools running. Do not take scores serious.
> Date has been included on each of them, in order to verify actuality & was tested without reboots


Wow, thank you for those insightful images! I removed screenshots from quote though

In the end of the post I'll provide my screenshots, but I'd like to highlight the differences.

You never hit CCA frequency limiter. I hit it even on y-cruncher FFT
Your VID Current Value is always way below VID Limit. So I'd say this is connected to 1, and CCA limit *is just misplaced label* of Voltage limit. I think I hit it because I have vCore LLC with the most droop, while you have one below flat. That I think allows your CPU to actually use lower set voltage to get higher frequencies, not the CO numbers.
I have somewhat better temps than you, especially in CB R23 multi. For some reason I have higher score than you, although I too had sniffing tools open, but also CPU mining and OneDrive. Even CTR reported lower clocks...
I previously reported ~660 CPU-z single core, but now I get ~670. Most probably because I used to have something open in background previously. However, for me on this test CTR shows C01 always loaded, and C02/C03 jumping back 'n forth.
Your FIT Current Value is much lower than mine, although you have higher scalar (7 vs 5). I observed FIT current value to rise as I rise scalar, so I wonder how was that possible 









The values above have much more difference for me than for you. I thought that's how HWiNFO64 computes Power Reporting Deviation, but for the test on which I made this screenshot (y-cruncher BKT) I get 70,8% PRD, while 46,247/71,192=0,649 





Spoiler: y-cruncher

































Spoiler: CB R23
































Spoiler: CPU-Z


----------



## Audioboxer

Veii said:


> Error #6 means mostly 20mV or more missing in VDIMM (well in result amperage, how ever you amplify it)
> #0,#2,#12 and rarely but someday #1 all mean slightly missmatched voltage. Often it's +/- 1 step = 10mV
> 
> #6 means more than 20mV soo it likely is simply lack of VDIMM
> Let me repost a PM answer here, it fitts
> View attachment 2521955
> 
> 
> This GDM comparison took a long time to make
> 1.6v was what i needed for pure 1T ~ while 2T was around 1.52ish
> If your timings are harsh, it can happen that you destabilize your CPU too.
> Started first with XMP , then with 16-16-16 to push FCLK. Been a lot of work till i get to a point of "just playing with timings"
> And still every time i change something little (which destabilizes instantly) it can mess up my CPU voltages.
> Soo i often switch VDDG voltages and procODT to make it slightly better and less voltage used. Yet if it can not reach 48.5, i do something wrong.
> That's where i like Aida64, i know how it behaves and what bandwidth i have to reach.
> If anything starts to throttle ~ it will be instantly seen
> 
> But till you get to the point where you can afford to run 1T ~ it will need a lot of time
> Curve optimizer will change how consistent and stable your cache + latency results are
> They will change how much you can drop VDDG CCD.
> Then every MCLK step you take, will destabilize the fabric again and you have to re'figure out the voltages for the CPU
> It's very recommendable to have baselines and not just start out of nowhere.
> Timings will drop slowly slowly, but for example if i change tRRD to 1 more , it is unstable. One less and it's unstable
> 
> What makes sense, is to take a break from pushing lower and lower primaries, and just jump down to lower frequency , use stupid low latency timings and see how RTTs behave and where you max out your memory/pcb. At which voltage they do not function anymore. On this you adjust RTTs and come back to your old baseline ~ with hopefully better powering
> Doing things back and forth, you'll get 1T to run
> But "just changing it" will not work
> You will surely need to spend over 20h on it (debugging) minimum
> 
> EDIT:
> Yet all that work required is nothing - as you start with a baseline
> Compared to coming from GDM, where nothing is reusable and you can start from scratch.
> It's just not worth to spend time with GDM , even when it has helpful properties


Thanks Veii you've given me the boost of optimism I needed lol. There's soo much information in this topic, soo many other people with similar binned ram and specs and it can be frustrating when 6/3/3 and 40/20/30/20 works for others but appears incredibly unstable for you 

I've spent hours reading your old posts in this topic, it's a goldmine but it's pretty overwhelming at times. Like, I just came across you advising to try 3-3-15 at tCKE 9 and I'm trying to learn what that does and if it might help me. As you can see above I've had 25 cycle runs pass with disabled/3/1 and 20-20-20-20. Then today I found out 1T with AddrCmdSetup 56, so 56-0-0 let's me run 1T relatively easily. But that's more like 1.5T, right?

It gets confusing figuring out what exactly I should be locking in, a 2T profile and considering 3-3-15 or 1T with 56-0-0 or... something else... LOL. End goal I'd like to have a go at 1T pure, but I'm awfully confused now about what my 2T profile should even look like, especially considering I have two that have passed 25 cycles already, 1 passed ycruncher and the other still to run it.

But they're both on auto for resistances and setups which for me defaults to disabled/3/1 and 20-20-20-20. That seems to pass things fine for me at 2T and at 1T with AddrCmdSetup 56. But it seems good advice is to still change the resistances anyway even if auto is stable (good practice, lower strain on ICM and what not). My head is spinning so I think I'll need to pick up tomorrow and re-read your reply lol. Thanks though, you're like an encyclopedia in this topic!

*edit* - Here is a quick illustration

This is from earlier today










A flat 15 and 2T, just with everything on auto (defaulted to 24-24-24-24 here, it's normally 20s).










Threw 3-3-15 into a 3 cycle with 6/3/3 and 40/20/30/20 just because I seen you mention 3-3-15 for 3800. Some of the timings/voltage above are different, it was done quickly for me to test 3-3-15.

What is "correct" to pursue? As of tonight, I would think 6/3/3 to try and get RttPark off 1 going forward, but the setups I dunno if I should just leave at 0-0-0 for the time being


----------



## Veii

whocares7 said:


> Hello,
> 
> Seems like this Patch C made the things a bit messier for my 24/7 stable setup (Patch A).
> 
> View attachment 2521926
> 
> 
> Some single #4/6 errors still occur occasionally in the very end of stability test.
> I'm wiggling around RTTs Auto or 7/3/2. 6/3/3 produce cold boots.
> 
> View attachment 2521928


Can you guarantee that SOC won't drop even 10mV under load, as VDDG is just 40mV away from SOC.
If you drop even 2mV , it will choke on voltage. Usually it's capable to manage itself, but your SOC is either too low or your VDDG IOD slightly too high
Be sure that whatever SOC you put in the bios - you won't get slightly even slightly bellow 40mV (distance) on any load you run. Usually 50mV , but 40 is the absolute limit between IOD and SOC

It's not a big deal if you use more SOC than needed, but it is a big deal if SOC drops lower than this. It will make issues

Cold Boots depend on CsOdtDrvStr, 60-20-40-20, give that a try
or 40-20-40-20. Oor 40-20-30-24 depends
But cold boot issues, training issues aside from being PHY dependend (which you can only set in AMD CBS) ~ CsOdtDrvStr (the 3rd CAD_BUS value) is what controls warm boots and cold boots
30+ was/is needed for Vermeer. 24 was needed for Matisse

What you should also try, is figuring out tCCD_L on the bios XMP profile recognition
Then use that tCCD_L * tRRD_S = tFAW.
tFAW got messed up at 4* , because new AGESA and new IMC FW implemented and changed the behavior slightly

For you i just think it's a SOC loadline issue, nothing more 
Well and a CAD_BUS issue
#4 are PCB crashes, soo surely a CAD_BUS issue
Give 40-20-40-20 a try


----------



## Veii

Audioboxer said:


> Thanks Veii you've given me the boost of optimism I needed lol. There's soo much information in this topic, soo many other people with similar binned ram and specs and it can be frustrating when 6/3/3 and 40/20/30/20 works for others but appears incredibly unstable for you
> 
> I've spent hours reading your old posts in this topic, it's a goldmine but it's pretty overwhelming at times. Like, I just came across you advising to try 3-3-15 at tCKE 9 and I'm trying to learn what that does and if it might help me. As you can see above I've had 25 cycle runs pass with disabled/3/1 and 20-20-20-20. Then today I found out 1T with AddrCmdSetup 56, so 56-0-0 let's me run 1T relatively easily. But that's more like 1.5T, right?
> 
> It gets confusing figuring out what exactly I should be locking in, a 2T profile and considering 3-3-15 or 1T with 56-0-0 or... something else... LOL. End goal I'd like to have a go at 1T pure, but I'm awfully confused now about what my 2T profile should even look like, especially considering I have two that have passed 25 cycles already, 1 passed ycruncher and the other still to run it.
> 
> But they're both on auto for resistances and setups which for me defaults to disabled/3/1 and 20-20-20-20. My head is spinning so I think I'll need to pick up tomorrow and re-read your reply lol. Thanks though, you're like an encyclopedia in this topic!


6-3-3 is what i recommeded after playing with an X570 ITX (2 dimm) and a Dark Hero (bad experience hah)
6-3-3 works on 4x A2, but it's not thaat great. Yet it is possible to run them finally on Daisy Chain
633 on 2 dimm boards is great. But because NOM is higher here - i can see the "minimum VDIMM requirements" are higher than usual

About tCKE and SETUP timings
tCKE appears to be used without directly enabled powerdown. There is normal and Aggressive powerdown
tCKE also defines the strengthness of the CKE (clock) signal , not only the timed power-down
These two, always vary between MCLK.
RTTs are fixed, but they should be changed when you increase strain on your PCB - be it by low timings or by higher MCLK. They are just gates, soo it's always recommended to run RTT_PARK to the lowest you can afford to run in the current state
What you run will anyways change, also when you can drop procODT lower will change ~ once you play with CAD_BUS values

SETUP timings bellow the half cutting point, are signal shifting delays
They are fixed delays and not adapting
tCKE is also a fixed delay calculated from MCLK

Both tCKE and SETUP Timings have to match in delay, which is ~ well it's hard
RTT_WR is another one = dynamic on-die-termination impedance. Similar to Processor On-Die Termination = procODT
WR has priority and does dynamically move the CKE signal (CKE LOW = PARK, CKE HIGH = NOM) . It has control over both and the highest priority.
Sadly higher capacity need to run RTT_WR (well it's good)
But because WR is dynamic, and both CKE and SETUP timings are not dynamic, they can interfere

Either you run WR + tCKE (to lower PCB strain and so heat on too high input current)
or you run CKE + SETUP timings without WR
WR and SETUP timings bother each, but it is fine right now ~ i posted a list, this should help 
matching all 3 together is extremely hard and i abandoned it. No setup timings anymore but much more work on powering

Generally SETUP timings are a thing you can do at the very end, but beyond 32 or 33 (the half cutting point) they change behavior. They start to behave similar to how Command Rate behaves.
tCKE (9) you can run, with 3-3-15 too. No issue @ 1900MCLK
But because SETUP timings are delays, it will slow down your latency result.
It will only improve it, if it was unstable to begin with. Keep this in mind, you can use them till 1T is fine for you & later you can drop them
I dropped them now fully, but was running at least 2+ months with them on 1T, as they helped a lot with my bad A0 PCB
tCKE is still important, but SETUP timings are not needed anymore for me. Maybe in the future again who knows ~ right now strongest possible tWR (/2) is the goal to get running beyond 4000MT/s.
Then i can exceed this 1.68v hard wall and lower timings further 

don't fear the voltage, but drop PARK as low as it can go without you seeing a negative effect.
You'll see an effect sooner or later , but it should be as weak as possible ~ allowing you to run as much VDIMM as possible


----------



## Audioboxer

Veii said:


> What you should also try, is figuring out tCCD_L on the bios XMP profile recognition
> Then use that tCCD_L * tRRD_S = tFAW.
> tFAW got messed up at 4* , because new AGESA and new IMC FW implemented and changed the behavior slightly


Sorry to jump in here, I remember you showing me how to find this on my ASUS board with my old memory. Think I've pulled it up on my Unify-X with my new memory










So does this mean a value of 6?

I am on the new AGESA, AMD ComboAM4PIV2 1.2.0.3c. I have read a few people moaning about 1.2.0.3c and memory, and some issues especially with MSI.



Veii said:


> 6-3-3 is what i recommeded after playing with an X570 ITX (2 dimm) and a Dark Hero (bad experience hah)
> 6-3-3 works on 4x A2, but it's not thaat great. Yet it is possible to run them finally on Daisy Chain
> 633 on 2 dimm boards is great. But because NOM is higher here - i can see the "minimum VDIMM requirements" are higher than usual
> 
> About tCKE and SETUP timings
> tCKE appears to be used without directly enabled powerdown. There is normal and Aggressive powerdown
> tCKE also defines the strengthness of the CKE (clock) signal , not only the timed power-down
> These two, always vary between MCLK.
> RTTs are fixed, but they should be changed when you increase strain on your PCB - be it by low timings or by higher MCLK. They are just gates, soo it's always recommended to run RTT_PARK to the lowest you can afford to run in the current state
> What you run will anyways change, also when you can drop procODT lower will change ~ once you play with CAD_BUS values
> 
> SETUP timings bellow the half cutting point, are signal shifting delays
> They are fixed delays and not adapting
> tCKE is also a fixed delay calculated from MCLK
> 
> Both tCKE and SETUP Timings have to match in delay, which is ~ well it's hard
> RTT_WR is another one = dynamic on-die-termination impedance. Similar to Processor On-Die Termination = procODT
> WR has priority and does dynamically move the CKE signal (CKE LOW = PARK, CKE HIGH = NOM) . It has control over both and the highest priority.
> Sadly higher capacity need to run RTT_WR (well it's good)
> But because WR is dynamic, and both CKE and SETUP timings are not dynamic, they can interfere
> 
> Either you run WR + tCKE (to lower PCB strain and so heat on too high input current)
> or you run CKE + SETUP timings without WR
> WR and SETUP timings bother each, but it is fine right now ~ i posted a list, this should help
> matching all 3 together is extremely hard and i abandoned it. No setup timings anymore but much more work on powering
> 
> Generally SETUP timings are a thing you can do at the very end, but beyond 32 or 33 (the half cutting point) they change behavior. They start to behave similar to how Command Rate behaves.
> tCKE (9) you can run, with 3-3-15 too. No issue
> But because SETUP timings are delays, it will slow down your latency result.
> It will only improve it, if it was unstable to begin with. Keep this in mind, you can use them till 1T is fine for you & later you can drop them
> I dropped them now fully, but was running at least 2+ months with them on 1T, as they helped a lot with my bad A0 PCB
> tCKE is still important, but SETUP timings are not needed anymore for me. Maybe in the future again who knows ~ right now strongest possible tWR (/2) is the goal to get running beyond 4000MT/s.
> Then i can exceed this 1.68v hard wall and lower timings further
> 
> don't fear the voltage, but drop PARK as low as it can go without you seeing a negative effect.
> You'll see an effect sooner or later , but it should be as weak as possible ~ allowing you to run as much VDIMM as possible


I'm going to leave this running tonight










I want to see if the 6/3/3 and 40/20/30/20 is OK.

Take me away from RttPark 1.

Though 6 x tRRDS would mean my tFAW should be 24!


----------



## Veii

Audioboxer said:


> So does this mean a value of 6?
> 
> I am on the new AGESA, AMD ComboAM4PIV2 1.2.0.3c. I have read a few people moaning about 1.2.0.3c and memory, and some issues especially with MSI.


Yes,
No issues for me - although Patch C is for APUs , and has no change for consumer Ryzen
It runs for me Patch C with AGESA and ABL patch B








Good luck
Hopefully both tPHYRDL are the same value for you on A1 and B1
You very likely will need to go up with SCL's , but you'll notice a bandwidth difference on Aida64

be sure to ignore the first result and give it at least 10sec to settle down C-States after it receives load (after the reboot)


Audioboxer said:


> Though 6 x tRRDS would mean my tFAW should be 24!


Yes.
When 16 runs, 16 runs - but it can come a time when it won't run anymore 
Just so you know


----------



## Audioboxer

Veii said:


> Yes,
> No issues for me - although Patch C is for APUs , and has no change for consumer Ryzen
> It runs for me Patch C with AGESA and ABL patch B
> 
> 
> 
> 
> 
> 
> 
> 
> Good luck
> Hopefully both tPHYRDL are the same value for you on A1 and B1
> You very likely will need to go up with SCL's , but you'll notice a bandwidth difference on Aida64
> 
> be sure to ignore the first result and give it at least 10sec to settle down C-States after it receives load (after the reboot)
> 
> Yes.
> When 16 runs, 16 runs - but it can come a time when it won't run anymore
> Just so you know


I'll keep that in mind even although it seems like everyone runs 16 lol.

tPHYRDL seems quite funny. 2T CL15 wants to be 28, but 1T CL15 will go to 26.

Then 2T CL14 wants to be 26 but so far for me 1T CL14 wants to be 28 

2T CL15 has both sticks on 28. 2T CL14 has both sticks on 26. 2T CL15 has both sticks on 26.

The only time my sticks are miss-matched is 1T CL14. Then it is 26 on one and 28 on the other. That could be a settings issue but I seen it happens to @mongoled as well. Happens at 3800. If I run my sticks at 3600 as they are rated for I believe 1T is 26 for both.

Would make you think it's one of the memory sticks but I did do a quick swap of DIMMs and I believe same DIMM went 28 (A1). Making me think its AGESA/mobo or a combination of multiple things.


----------



## Veii

XPEHOPE3 said:


> You never hit CCA frequency limiter. I hit it even on y-cruncher FFT


Yes, i did if i drop CO's lower.
Some of my worst cores peaked 1.4v VID and dLDO Injector pushed the rest down, soo it generally lost frequency

Good cores need less negative CO - bad cores need more negative CO to filter too excessive current.
I don't think they are bad cores, even when they are titled such. Yuri thinks the same, current CPUs are overvolted a bit.
i could run 5ghz on sub 1.4v-TEL, while only 4.925ish on 1.45v+
Less voltage is better ~ but likely an issue of FIT throttling to early.

We figured it out at the same time (together) so i can talk about it a bit. ~ it' s not purely his research, soo no friends betrayal 

If you have a crashing core, you change anything around it - to work with dLDO Injector
You don't have to change this bad core.

I still overdrive CTR and now Hydra.
But have to drop my magnitudes -2 , Results are better and it can use their OB feature to extend this limited CO 

The behavior of +25mhz = -2 CO on everything, still functions
Hydra now is more accurate, which is lovely ~ but public 0.9A version is too limiting for my taste. It will take some time till it can beat my PBO

I don't CCA throttle, because it never reaches VID throttle
CO does change what VID is requested, and FIT does adapt to this
But i cheat a bit  Well focus on fixing the mess AMD gave me with this broken unit and it's broken V/F curve. I love my sample but don't love AMDs enforced PBO fMAX limits and CO limits . . . or useless PROCHOT 

Soo if i go down to -2 of my CO (in the positive range) to weaken it down, only then Hydra and CTR passes
Both on their own are too weak .But then if i do this ~ then i can not always hold 4.85, which doesn't make me happy.


XPEHOPE3 said:


> Your VID Current Value is always way below VID Limit. So I'd say this is connected to 1, and CCA limit *is just misplaced label* of Voltage limit. I think I hit it because I have vCore LLC with the most droop, while you have one below flat. That I think allows your CPU to actually use lower set voltage to get higher frequencies, not the CO numbers.


I don't think CCA limit is misslabled, but 1.4v being another sensor that limits it.
I used strong VID request drop (CO) , then LLC to 2 to tame it - as 1 overshoots
And when it was more fluidy, slight positive vcore on the VRMs side , which is undetected by FIT

FIT detects request VID but not delivered voltage.
Early on was running -30 CO on all cores (it's a magnitude changer , currently run per core correction for AMDs misslablement) with +85mV positive vcore
This also wasn't detected by FIT, soo it was my way of telemetry faking, as the CPU will boost up the more VID it has
You can easily exceed 1.55v if FIT is stupid. You can exceed 1.6v without destroying the silicon ~ but there are limits of what i should share by friendliness
FITs throttle is too artificial in their current state ~ i hope Zen3D is better. There is a lot of potential left on the table

Soo yes, i run atm with VDROOP of 0% 
On allcore loads it goes to -1% which is a bit more supplied voltage than it asks 
On normal boost it's close to perfect at 0%, soo VID-V = delivered V-TEL
That allows me to go as close to possible with CO. 
Else on stock stock, a high loadline droop was better.
but as you user started to influence and change AMDs CO binning, you will need to change the voltage too
CO settings are no overriders but magnitude changers !


XPEHOPE3 said:


> I have somewhat better temps than you, especially in CB R23 multi. For some reason I have higher score than you, although I too had sniffing tools open, but also CPU mining and OneDrive. Even CTR reported lower clocks...


Oh my temps are bad , i know that haha
Someday i need an AIO to fix it. Even a 120mm should keep it sub 60c, but no funds atm. Want also to play with dual rank dimms - but my 2nd PC is not done yet, miss a GPU and a storage drive.
Soo i'm not going down to Win10 yet to benchmark . Can not submit benchmarks with Win11 buggy cache

Keep in mind, my 2nd CCD remains active 
I should try if PatchC finally fixed buggy DF_States, to lower 20-30W (18-20A from EDC away) . 2nd CCD is idle but not sleeping, they are lowest frequency idling , because DF-States was unusable
I hope it's fixed.
We do have a big difference in available boosting budget.
2100 FCLK eats also a lot. I try what i can, but still am strongly powerbudget limited.
Try to offset it by undervolting cores as much as possible - but still struggle on multicore loads, it just eats too much.


XPEHOPE3 said:


> I previously reported ~660 CPU-z single core, but now I get ~670. Most probably because I used to have something open in background previously. However, for me on this test CTR shows C01 always loaded, and C02/C03 jumping back 'n forth.


mmm
674 here, don't think i can go higher than that
675 should be possible , unsure
Latest AGESAs changed SC performance for Matisse and earlier too. It improved on stock 


XPEHOPE3 said:


> Your FIT Current Value is much lower than mine, although you have higher scalar (7 vs 5). I observed FIT current value to rise as I rise scalar, so I wonder how was that possible


Powerdraw 
I have on idle in general much higher powerdraw on EDC

I really try every possible thing to telemetry fake it. Was able to bug out THM sensor and PPT, both at zero
But FIT started to panic and throttle  like the EDC bug
Happens if you disable LCLK fully - sadly PROHOT limit still was applied. I really wish it wouldn't be that stupidly low  It's soo irresponsible, even the 5800X has it at 95c not 65c
Trying atm a buffer overflow (HEX) by using 








As EDC limit. It defaulted to me at 460A maxed out. Here and there pulls 126A now instead 123A
But VID limit + PROCHOT limit are triggering

FIT FUSE Limit you can override with TOOL.exe, but i saw no change - as it was limited by EDC fuse or by prochot
maybe try this EDC limit.
CCA is 99% EDC FUSE focused 

Increased TDC to 90, but Cinebench AVX2 runs at max 81 so far
Maybe 80A will be better. Have to see. 65 was good enough, i saw not much of a frequency change.
When prochot throttles frequency, TDC didn't care ~ maaybe some more perf can be get out of this, but idk. no time to test it yet. Later when Win10 is on it and my 2nd PC is done to record footage


----------



## Veii

Audioboxer said:


> I'll keep that in mind even although it seems like everyone runs 16 lol.
> 
> tPHYRDL seems quite funny. 2T CL15 wants to be 28, but 1T CL15 will go to 26.
> 
> Then 2T CL14 wants to be 26 but so far for me 1T CL14 wants to be 28
> 
> 2T CL15 has both sticks on 28. 2T CL14 has both sticks on 26. 2T CL15 has both sticks on 26.
> 
> The only time my sticks are miss-matched is 1T CL14. Then it is 26 on one and 28 on the other. That could be a settings issue but I seen it happens to @mongoled as well. Happens at 3800. If I run my sticks at 3600 as they are rated for I believe 1T is 26 for both.
> 
> Would make you think it's one of the memory sticks but I did do a quick swap of DIMMs and I believe same DIMM went 28 (A1). Making me think its AGESA/mobo or a combination of multiple things.


Don't really care much about it
The board will predict what it predicts . It functions how it should , but both dimms have to get the same value
It's like IO-L's and RTL's on Intel. Just that you can not change it here.
Don't bother with it , but thanks to @XPEHOPE3 @Blameless and me we figured what it was. Big thanks to Hrenore3 (is it Cyrillic ?) for even noticing something there is fishy.
It's just showing bad powering by MCLK. When you drop cLDO_VDDP too low, or procODT too low, it will shift to another strap ~ when the furthest channel can not receive same amount of current
Typical memory training IOL prediction.
But tPHYRDL matches more to Intels tWRWR_SG value ~ soo it changes with tCWL & tCL behavior. But so it should also with tRRD and tWTR

In general, don't overthink it.
When it is not in sync, autocorrection happens - latency is worse
Give your best to figure out when it will be in sync. It's not only timings related, but mostly voltage related. But the issue happens on cold boot
When the board is done with training, you can lower voltages and it will not move. But on cold boot you will notice "too low cLDO_VDDP" or too low procODT


----------



## XPEHOPE3

Veii said:


> Powerdraw


Yes, you do have more powerdraw than me. But I thought higher powerdraw should mean higher FIT values, not lower. What are those FIT values anyway? I saw situations where FIT Current Value = sum of Per Core FIT Current Values, but also *2 of that. But then what are those per core FIT values? And on certain AVX2 loads those values somehow drop completely.



Veii said:


> (is it Cyrillic ?)


😄 it is and means "dick horseradish cutter


Veii said:


> then LLC to 2 to tame it - as 1 overshoots


It overshoots still on your single core CPU-Z 



Veii said:


> If you have a crashing core, you change anything around it - to work with dLDO Injector


You probably mean "core crashing on multithreaded load"? Because if it crashes during CoreCycler changing any other CO values doesn't help at all, the offending core would still crash in CoreCycler.


----------



## XPEHOPE3

XPEHOPE3 said:


> I previously reported ~660 CPU-z single core, but now I get ~670. Most probably because I used to have something open in background previously. However, for me on this test CTR shows C01 always loaded, and C02/C03 jumping back 'n forth.


Well, I don't know what's more bs: my PC, my settings, or CPU-Z, but I tried to replicate it and failed. If I close everything, CPU-Z single core is around 660. If I open AMD monitor or CTR, it can get to 666 now. So single-core score raises when more applications are running! Multi-core obviously degrades.
But again that single-core test isn't single-core at all, since any sniffing software shows it always uses core #0 as well as one of the two best cores (#1 or #2). So at all times 2 cores are used.


----------



## Veii

XPEHOPE3 said:


> Yes, you do have more powerdraw than me. But I thought higher powerdraw should mean higher FIT values, not lower. What are those FIT values anyway?


They are mostly related to EDC, idk tbh
They vary instantly by load - for example y-cruncher
They could vary by temps, and we can enforce them (although people reported it doesn't work anymore, soo maybe again AMD changed SMU HEX location as always zZZ)
I haven't seen a reason yet to build scripts which override FIT limit to something higher
Got the math out in the old post , but yet it is useless ? It showed no difference as you never hit FIT limit, but FIT dynamically adjusted up and down.

Honestly no idea
But the VDD 1.8v rail, does seem to have another sensor which does track 1.8v current (not voltage)
Soo it appears that 1.8v rail makes a difference when you increase it ~ rather, it appears that something tracks if there is enough current on this rail and if not ~ throttles.
I am not sure, Yuri knows far more, but Yuri will not be able to talk about it , unless he figured it out by himself
Nothing that was shared to you, is allowed to be mentioned and you must ignore the question, according to NDA - you are not allowed to even say you can not talk about it, but must quit the talk

Yet for things he figures out, or i figure out things i read - soo figure out things how they behave without being 1:1 the same quoted thing i could read/heard/saw ~ only then i can talk about it
Hydra & CTR behavior i can talk slightly on Overboost things - as i figured his scaling out, without ever looking how he does it and without knowing what AMD supported or didn't support

Honestly idk more, else you'd know new findings by now
I post what i know, soo research is pushed forward
Meanwhile people in the industry track it and keep making our lifes harder against exploits and other funny things 
Yet these people can not for god's love finally fix their broken DF_C-States , and allow variable FCLK & variable SOC to be a thing again
How hard must it be to enable STAMP behavior on consumer ryzens (modify code) when everything in this agesa is already implemented and just not active
CPUs could boost soo much better and stay colder, if we can save this useless SOC current that has to run zZZ
I'm ranting again, but this will be one of those things, that won't be fixed till the new gen magically randomly fixes it on a newer AGESA

SOC cuts soo much into the powerbudget
Same as non functional APBDIS ~ even when it's there, and has to function. Nothing
Kind of lame


XPEHOPE3 said:


> It overshoots still on your single core CPU-Z











slightly, but that's my positive offset and not that much the LLC 
674 was my best according to this post
Funnily now windows 11 , does push it to the "best core" it's not only "first core"








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


https://www.hardwareluxx.de/community/threads/ram-timings-und-deren-einfluss-auf-spiele-und-anwendungen-amd-update-23-05-2020.1269156/ He only talked about avg fps, but there should also be inprovements in the 0.1% fps. So I did some tests and basically there is 0% improvements in min. fps in...




www.overclock.net





Honestly, i think we can override PROCHOT. it should be possible via SMU call








I do think that SMNCLK is the one controlling FMax for our CPUs (theory)
People tried to override 200mhz PBO override - but i'd need to downgrade to my Patch 1100 A backup, to check how tool.exe behaves and looks
Gladly on "CPU swap recognized" , i had 4 reboots , but could instantly load the profile
Soo even with an PSP FW update on Patch C (B) , FCLK remained unlocked (gladly)
But i do still think that the broken LCLK logger - or something with DPM, is the key reason to all these FCLK WHEA issues
Even when #19 is Chipset - then IO - related (mostly, if it isn't PCIe 4.0 related after 2000+)

Mmm, quite sure that only LCLK is bugged on our dual CCD units - and that's allowing higher FCLK to run without WHEAs
That or some other sensor is bugged, which can not throttle back.
Disabling LCLK does result in broken THM and PPT , fully broken powermanagement, but not broken enough where prochot won't function (sadly)
Enabling it does no change, and 2100 FCLK still functions ~ soo it has to be bugged somehow. I've seen it functioning on normal units
===========================
EDIT: Final 2.20 bios is out
Let's break FCLK again and lock down our cpu's for ever
Nah let's see, i am curious if there was any AMD PBS change ever, anything


----------



## Veii

Erased EDIT:
We got nothing - it's the same, i didn't notice the microcode update since 1203A
It's all the same, no new menus nothing
Same microcode , Patch A had AGESA patchB - and so has Patch C , AGESA Patch B

Something appears to have updated internally, but it's nothing i can see or track or feel
Just memory booted instantly, potentially something updated but i'll just run TM5 and notice no change (likely)

If there is something fishy, you'll know 
* also still same korean font bug 
EDIT2:
Same thing, nothing out of the ordinary
Tested 5 times (CPU-Z) same scores, +/- 3.0 on MC, +/- 0.1 on SC








EDIT 3:
And DF_C-States is still a broken mess too
Still overboosts on Patch-C
Will they ever fix this ? 








Cores suspend fully, and you get more Read & Copy Bandwidth
But nobody does want that random reboot unstableness because of far to high boosting - broken boosting after waking up
EDIT4:
I might actually run this for 2-3 days and see if i get random reboots
How system stability feels, and how bad FPS stability feels with this bug. If CTR/Hydra reboots and such things
Would be happy if i can cut away 20W+ of power, when deep sleep of cores fully functions (it shows it doesn't function without bugs, but we'll see)


----------



## seansplayin

Hopefully this can help someone trying to get (4) 8GB sticks of Gskill 4266 cl19 stable at decent speeds. I don't think I won the fclk lottery as stabilizing the last 66 mhz required raising the VDDG IOD 1.0 > 1.15v which inturn required raising the SOC voltage 1.08 > 1.15v. Dram voltage is at 1.49v


----------



## Solohuman

What are the opinions of AMD memory overclockers with the inbuilt memory diagnostic tool in Win 10?


----------



## Audioboxer

Noticed someone else managed a flat 14 with similar timings so decided to start here and see if I could manage it. I had a safe tCL14 profile that passed 25 cycles I tweaked. tRCDRD still error'd quickly on 6 on 14 up to 1.55v, so just ran it with 15 for now. Going to guess error 14 is about DrvStr in this situation. Will try with 40/20/30/20.

Unrelated but is it normal for the MSI bios to seemingly always add 0.01v to VDIMM?


----------



## MrHoof

Veii said:


> Can you guarantee that SOC won't drop even 10mV under load, as VDDG is just 40mV away from SOC.
> If you drop even 2mV , it will choke on voltage. Usually it's capable to manage itself, but your SOC is either too low or your VDDG IOD slightly too high
> Be sure that whatever SOC you put in the bios - you won't get slightly even slightly bellow 40mV (distance) on any load you run. Usually 50mV , but 40 is the absolute limit between IOD and SOC
> 
> It's not a big deal if you use more SOC than needed, but it is a big deal if SOC drops lower than this. It will make issues


I think some boards do not report those 100% accurate, atleast on my Asus x570i if I set both to AUTO my Board will have 38mv reported distance by Zentmings after vDroop and my now tuned values have 39mv after vDroop and so far never crashed randomly cause of that. If it was unstable I would see rare WHEA from my experience with my old r3600/x570 auros elite.

Took yesterday some time to fine tune my voltages. So far is still stable, did a karhu 12h run overnight.







edit: If I would lower vddg ccd, how would it show if its unstable. Did not play around with it yet.


----------



## mongoled

Audioboxer said:


> Noticed someone else managed a flat 14 with similar timings so decided to start here and see if I could manage it. I had a safe tCL14 profile that passed 25 cycles I tweaked. tRCDRD still error'd quickly on 6 on 14 up to 1.55v, so just ran it with 15 for now. Going to guess error 14 is about DrvStr in this situation. Will try with 40/20/30/20.
> 
> Unrelated but is it normal for the MSI bios to seemingly always add 0.01v to VDIMM?


Mine according to SET (BIOS), GET (HWInfo) is 0.2x volts 😀


----------



## Mach3.2

Same behavior on my X570 Tomahawk, GET in hwinfo is ~0.2V more than SET voltage in BIOS. ZenTimings show the exact SET value.


----------



## Kildar




----------



## PJVol

Audioboxer said:


> Unrelated but is it normal for the MSI bios to seemingly always add 0.01v to VDIMM?


It was the case in earlier ASRock bioses, but recent fw seem to fix, so at least on my board VRM reported values are identical to those set in the bios.


----------



## Audioboxer

Audioboxer said:


> Noticed someone else managed a flat 14 with similar timings so decided to start here and see if I could manage it. I had a safe tCL14 profile that passed 25 cycles I tweaked. tRCDRD still error'd quickly on 6 on 14 up to 1.55v, so just ran it with 15 for now. Going to guess error 14 is about DrvStr in this situation. Will try with 40/20/30/20.
> 
> Unrelated but is it normal for the MSI bios to seemingly always add 0.01v to VDIMM?


Decided to tweak a few things










Dropped tCKE 9 3-3-15 for now, I just don't understand it enough at the moment. I seen it helped someone get 2T flat 14s on DR, but tRCDRD at 14/3800 just seems hellish to pull off unless your RAM is in top 5%. Stuck with 6/3/3 and went 40/20/30/20 as it seems a popular choice for DR. ProcODT down to 34.3 because of bump to CsOdtDrvStr. A few changes to timings (some loosened, but tRTP tightened).

Also for the first time I stopped doing my fan routine I normally do for TM5. As I'm watercooled I like silence but when running TM5 due to how hard it hammers RAM I've been increasing all my fan speed outwith their normal curve that runs off water temp. RAM normally peaks around 40 under these conditions with TM5, peaked at 45/46 here. I know nothing in normal use will hit RAM as hard as TM5 but I wanted to see what my RAM temps would go to under my normal cooling setup. With me on a 2 DIMM board now with the ram right next to each other this is obviously increasing temps a bit too.

Question now is where do I go next? Other than y-cruncher which I'm about to start. Timings are quite tight, though I can work on tRFC a bit. Ram is moved away from disabled/3/1 on Rtt's which AUTO prefers. DrvStr I guess could have been tested at flat 20's, but I wanted to see if 40/20/30/20 would work OK. I was struggling with 1T pure at flat 15s, not sure if tCL14 will make that even harder.

Open to suggestions  I will move to my flat 15 profile at some point as well, but seeing as I can run tCL14 at 3800 I wanted to "start" here.


----------



## mongoled

Audioboxer said:


> Decided to tweak a few things
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Dropped tCKE 9 3-3-15 for now, I just don't understand it enough at the moment. I seen it helped someone get 2T flat 14s on DR, but tRCDRD at 14/3800 just seems hellish to pull off unless your RAM is in top 5%. Stuck with 6/3/3 and went 40/20/30/20 as it seems a popular choice for DR. ProcODT down to 34.3 because of bump to CsOdtDrvStr. A few changes to timings.
> 
> Also for the first time I stopped doing my fan routine I normally do for TM5. As I'm watercooled I like silence but when running TM5 due to how hard it hammers RAM I've been increasing all my fan speed outwith their normal curve that runs off water temp. RAM normally peaks around 40 under these conditions with TM5, peaked at 45/46 here. I know nothing in normal use will hit RAM as hard as TM5 but I wanted to see what my RAM temps would go to under my normal cooling setup. With me on a 2 DIMM board now with the ram right next to each other this is obviously increasing temps a bit too.
> 
> Question now is where do I go next? Other than y-cruncher which I'm about to start. Timings are quite tight, though I can work on tRFC a bit. Ram is moved away from disabled/3/1 on Rtt's which AUTO prefers. DrvStr I guess could have been tested at flat 20's, but I wanted to see if 40/20/30/20 would work OK. I was struggling with 1T pure at flat 15s, not sure if tCL14 will make that even harder.
> 
> Open to suggestions  I will move to my flat 15 profile at some point as well, but seeing as I can run tCL14 at 3800 I wanted to "start" here.


Any specific reason why you are not attempting to reduce your tRFC?


----------



## Audioboxer

mongoled said:


> Any specific reason why you are not attempting to reduce your tRFC?


Nah I just normally do it "last" lol. I'll be on it next. I normally just go with a reasonably low tRFC and hit up everything else first. I don't even know what my methodology behind doing that is other than thinking as its temp/voltage sensitive it might throw other timings off at first.

I came from Micron E die as well to B-die so I guess it's just a bit of a knowledge gap with how low it can go. I've always thought 270~280 was already quite low but I do see some pictures of 220~250.

So it's not that I'm not going to do it.


----------



## mongoled

While using [email protected] [email protected] and [email protected] tRFC /tRFC2/tRFC4 should be 264/196/121

I would try

[email protected] [email protected]
240/178/110

You may need to raise vDIMM

😊

Also tWR you can try 10


----------



## Audioboxer

mongoled said:


> While using [email protected] [email protected] and [email protected] tRFC /tRFC2/tRFC4 should be 264/196/121
> 
> I would try
> 
> [email protected] [email protected]
> 240/178/110
> 
> You may need to raise vDIMM
> 
> 😊


Thanks, will do. Just want to do y-cruncher first with this lot of timings before moving on.


----------



## mongoled

Audioboxer said:


> Thanks, will do. Just want to do y-cruncher first with this lot of timings before moving on.


👌


----------



## Audioboxer

mongoled said:


> 👌


Looking like things are going to be OK with y-cruncher as well 










I'll try your above settings for the TM5 run tonight and see how I get on!


----------



## boldenc

XPEHOPE3 said:


> Well, I don't know what's more bs: my PC, my settings, or CPU-Z, but I tried to replicate it and failed. If I close everything, CPU-Z single core is around 660. If I open AMD monitor or CTR, it can get to 666 now. So single-core score raises when more applications are running! Multi-core obviously degrades.
> But again that single-core test isn't single-core at all, since any sniffing software shows it always uses core #0 as well as one of the two best cores (#1 or #2). So at all times 2 cores are used.


CPUZ single thread score is weird, normal I get around 688 - 690, but sometimes I get 695 and one time even I got 700. I think Patch C bios changed something related to boost, it is like the CPU want to boost but something is limiting it.
Btw AMD monitor from where I can get?


----------



## walkman_w902

Hi, guys! 
I'm working on RJ 5 F4-4000C15D 4*8Gb overclock since Patch C rolled in and corrupted my previous modest results ([email protected]). My ultimate goal now is [email protected] what is quite on par with [email protected] xmp on this memory (IF>1866 don't boot on my system with 4*8 setup). I've managed to made 14-15-14-14-30-44 with secondary and other timings tuned with help of Ryzen Google calculator, but keep getting errors in test 10, 5 and 2 (screenshots included). Most likely I've overlooked something, but cannot understand what exactly. VDIMM is 1,49V, max temp of individual memory 56C. If anyone can point out where my error can be, I would be thankful greatly.


Spoiler: ZenTimings

















Spoiler: testmem


----------



## XPEHOPE3

boldenc said:


> Btw AMD monitor from where I can get?


Here. Note that it depends on Power Table reverse engineering, and that changes by CPU, AGESA, etc. So it is somewhat outdated and has misplaced labels. I'm going to work on fixing it 😎


----------



## Audioboxer

walkman_w902 said:


> Hi, guys!
> I'm working on RJ 5 F4-4000C15D 4*8Gb overclock since Patch C rolled in and corrupted my previous modest results ([email protected]). My ultimate goal now is [email protected] what is quite on par with [email protected] xmp on this memory (IF>1866 don't boot on my system with 4*8 setup). I've managed to made 14-15-14-14-30-44 with secondary and other timings tuned with help of Ryzen Google calculator, but keep getting errors in test 10, 5 and 2 (screenshots included). Most likely I've overlooked something, but cannot understand what exactly. VDIMM is 1,49V, max temp of individual memory 56C. If anyone can point out where my error can be, I would be thankful greatly.
> 
> 
> Spoiler: ZenTimings
> 
> 
> 
> 
> View attachment 2522050
> 
> 
> 
> 
> 
> 
> Spoiler: testmem


Interesting to see more anecdotal evidence patch C isn't great for memory.

I'm no expert and I don't have SR memory, but I'm going to do the easy thing I'll say for everyone now, get GDM disabled first! 2T! 

That will also make it easier for people in this topic more knowledgeable than me to diagnose your errors. It's my understanding with GDM enabled other things can be modified automatically and it's harder to diagnose problems.

Plus, GDM disabled 2T should produce better latency when tweaked properly. At least, that's my understanding.

But as for the errors themselves, 2, 5 and 10 from here tRFC Calculator (mini)

B-die over 50 degrees is more likely to begin erroring out as well so I'd keep that in mind. If you can point a fan at your RAM for now and try to keep it under 50 and see if you get those errors again.


----------



## umea

Audioboxer said:


> Decided to tweak a few things
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I seen it helped someone get 2T flat 14s on DR, but tRCDRD at 14/3800 just seems hellish to pull off unless your RAM is in top 5%


I'm actually in the exact same seat as you right now lol... Although outside of primary timings I've left everything quite loose, getting trcdrd to 14 is the biggest problem, as the moment it goes from 15 to 14 it errors out of its ass... 6s, 12s, basically everything. At least now that I've verified its not any of the other primaries I can focus on it completely. I'm running 7/3/1, and will go through the full process of elimination with procodt/cadbus/rtt again to try to get it to work... Which will take a very long time lol.


----------



## Audioboxer

umea said:


> I'm actually in the exact same seat as you right now lol... Although outside of primary timings I've left everything quite loose, getting trcdrd to 14 is the biggest problem, as the moment it goes from 15 to 14 it errors out of its ass... 6s, 12s, basically everything. At least now that I've verified its not any of the other primaries I can focus on it completely. I'm running 7/3/1, and will go through the full process of elimination with procodt/cadbus/rtt again to try to get it to work... Which will take a very long time lol.


You trying on 2T, yeah? I seen someone manage it with 6/3/3 and 60/20/20/20 with tCKE 9 and 3-3-15 2T. Basically what my first post was. Though I didn't catch their VDIMM voltage, I presume 1.55-1.57v or something. When I tried those Rtts, DrvStr and flat 14s it was still a full on disco at stage 6.

Main issue with tRCDRD is its clearly not just a throw voltage at it issue, but the overall package. I thought buying this b-die that is rated for 3600 flat 14 might make it a bit easier, but nah, it's solid at 3600 flat 14 but errors out the ass at 3800 tRCDRD 14 🤣

@mongoled your settings error'd after 8 minutes but I bumped the voltage and I'm now at 20 minutes, so it looks like you're right. I went with 1.54v in the bios which MSI seems to report at 1.55v. Will see if it passes before trying to come down a bit.


----------



## umea

Yeah, I'm gonna try to isolate resistance/voltages first and then tighten things one by one to see if it aids it.. I am trying on 2t again as well. I was satisfied somewhat with achieving 1T 3800cl15 flat with very tight secondary/tertiaries and 56 setup times but I really would like to reach pure 1T cl14 flat 3800... I'm pretty sure my kit is able to (4266 17 18 18 38 kit), its just a matter of finding the right stuff. Worst case, I try to up frequency and settle for cl15. Only problem is DPC spikes above 1900fclk start to get bigger and more common and its more difficult to stabilize. From what my friend told me another benefit to disabling a ton of stuff in bios is that it lowers vsoc requirement (he runs 1900fclk at 1.08vsoc 3800 cl14 flat 1t pure). At least I won't have to throw stupid high voltages at it I guess..


----------



## Audioboxer

umea said:


> Yeah, I'm gonna try to isolate resistance/voltages first and then tighten things one by one to see if it aids it.. I am trying on 2t again as well. I was satisfied somewhat with achieving 1T 3800cl15 flat with very tight secondary/tertiaries and 56 setup times but I really would like to reach pure 1T cl14 flat 3800... I'm pretty sure my kit is able to (4266 17 18 18 38 kit), its just a matter of finding the right stuff. Worst case, I try to up frequency and settle for cl15. Only problem is DPC spikes above 1900fclk start to get bigger and more common and its more difficult to stabilize. From what my friend told me another benefit to disabling a ton of stuff in bios is that it lowers vsoc requirement (he runs 1900fclk at 1.08vsoc 3800 cl14 flat 1t pure). At least I won't have to throw stupid high voltages at it I guess..


I can boot FCLK all the way up to 2000 but I get WHEA errors above 1900. If I can ever run 2000 WHEA free I'd be happy with 4000 CL16. No more 14s 🤣 I think 14 is now my most hated number.

Flat 15s was working for me with 1T and 56 setup but I was struggling with 1T pure. Can boot fine without the 56 setup but I was tearing my hair out trying to figure out what combination of Rtt/DrvStr and voltage might be needed to pass TM5.

I think that is why I've gone back to work on 14 at 3800 2T and see what I can get running here. Wouldn't mind using 2T if it's tCL14. Though I will try 56 setup with these timings at some point. 14 with 1T does seem to shift my tPHYRDL to 28 though. 15 with 1T it stayed at 26.

edit - @mongoled error on 0










Not really wanting to pump more voltage just now just for tRFC, so I guess I'll ease back on it a bit. Though maybe it's tRAS not being happy as well.

Temps getting into 40s with tRFC being voltage and heat dependent might also be the cause. Might ramp my fans up again to test that lol.


----------



## MrHoof

@Audioboxer try scl´s at 4 setting them lower does not gain much performance anyway, u can try going back to 2 later on.


----------



## Audioboxer

MrHoof said:


> @Audioboxer try scl´s at 4 setting them lower does not gain much performance anyway, u can try going back to 2 later on.


I'll keep that in mind! Passed at 2 OK with higher tRFC so it's possibly just a balancing act.

Got a run going at 250/186/114 at 1.53v just now. Will see if it makes it.


----------



## MrHoof

Audioboxer said:


> I'll keep that in mind! Passed at 2 OK with higher tRFC so it's possibly just a balancing act.
> 
> Got a run going at 250/186/114 at 1.53v just now. Will see if it makes it.


tRFC also depends alot on the kit my own lowest to boot at 1.52v is 252 but that will result in a bluescreen so yours is already doing better then mine .

edit: at the moment testing those timings almost done I guess.













running 1T on this motherboard/cpu combo seems to easy tbh, seeing the struggle others have.

edit2: still not sure if tcke 9 does anythign for stabilty or performance but it does not hurt it either. Auto would set it to 1.
edit3: tRDRDSD/DD tWRWRSD/DD at 1 improved copy by ~200mb/s and latency by .2ns.


----------



## Veii

XPEHOPE3 said:


> Here. Note that it depends on Power Table reverse engineering, and that changes by CPU, AGESA, etc. So it is somewhat outdated and has misplaced labels. I'm going to work on fixing it 😎


If you want to dig a bit, here is the up to date version - but this time it has an "ASUS Verified" Check
Seems ASUS XOC guys where not happy sharing their OC Tool outside of their ROG exclusive lineup ~ even when the lock is just "selfish/marking reasoned" to have 🙃
Don't really have much motivation to dig with Cutter Cutter (Radare2 based on Ghydra) similar into it
C8Tool.rar ~ June, 30th, 2021

Original source was HWBot , not exactly this thread exclusive, but Update 1007 (2020 October) has been some time since it was shared



Audioboxer said:


> Dropped tCKE 9 3-3-15 for now, I just don't understand it enough at the moment. I seen it helped someone get 2T flat 14s on DR, but tRCDRD at 14/3800 just seems hellish to pull off unless your RAM is in top 5%.
> 
> Just needs voltage
> 
> 
> Audioboxer said:
> 
> 
> 
> Open to suggestions
> 
> 
> 
> mongoled said:
> 
> 
> 
> 240/178/110
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

270-201-123 , 2x 16GB (if staying at typical 14-15-30-45 base
mini is not dual rank aware
Likely something around this looks reasonable 









* DR needs B2 option


----------



## XPEHOPE3

Veii said:


> C8Tool.rar ~ June, 30th, 2021


Nah, says "Not supported", can't even test anything =/


----------



## umea

Taking into account Veii's last post about DR needing trfc/35x55, decided to bring on my stable 1T 56 setup time settings. 
Changed: tRTP (5->6), tRAS (25->28), and tRC (40->42) as well as trfc like mentioned.









Time to see if it holds out for 25 cycles. I also had it running stable (well, 3 cycles) with my loose settings on 6/3/1, 6/3/2, and 7/3/1. It seems tRCDRD is the final boss, as changing it to 14 starts erroring out on just about everything (tons of 6s, 12s, 2s,etc immediately) no matter what I've tested so far. Will test these timings with 6/3/2 and 6/3/1 to see if there's a difference.


----------



## Veii

XPEHOPE3 said:


> Nah, says "Not supported", can't even test anything =/


Yes, it has a new flag for system check, same as TurboV and latet MemTweakit
"just" need to decompile it with Cutter or Ghydra to fix it ~ in case anybody wants to bother 


umea said:


> Taking into account Veii's last post about DR needing trfc/35x55


Not my research
Values are based upon JEDEC contributions
But generally DR has different tRFC2 than SR 8gb 
tRFC4 is generated from 2 at the end anyways


----------



## mongoled

Veii said:


> * DR needs B2 option
> View attachment 2522096


Is this also valid for 4x8GB?


----------



## Veii

mongoled said:


> Is this also valid for 4x8GB?


no 
its chip size and chip amount 
capacity size depends on bank group swap option - interleaving
But tRFC2 depends on chip size and amount


----------



## mongoled

As I cant get all four dimms to run at [email protected] ive been playing with aggressively lowering tRFC though I am not seeing any "gains" from doing this.

Ive tested with AIDA64, Sisoft and Membench.

Aggressive being 228/169/104 ...

Next candidate for 24/7 settings


----------



## Veii

mongoled said:


> As I cant get all four dimms to run at [email protected] ive been playing with aggressively lowering tRFC though I am not seeing any "gains" from doing this.
> 
> Ive tested with AIDA64, Sisoft and Membench.
> 
> Aggressive being 228/169/104 ...
> 
> Next candidate for 24/7 settings
> 
> View attachment 2522115


You can try to take the path of tRAS = tRCDRD+tRTP 
tRC= tRP + tRAS

Then just run higher tWR & tRFC


----------



## mongoled

Veii said:


> You can try to take the path of tRAS = tRCDRD+tRTP
> tRC= tRP + tRAS
> 
> Then just run higher tWR & tRFC


Hmmm, ive never tried this before.

So with my current settings I would be looking at

tRAS @21
tRC @35

and then something like

tRTP @7
tWR @12
tRFC/tRFC2/tRFC4 @245/182/112

Will give it a try, thanks !


----------



## Audioboxer

Veii said:


> If you want to dig a bit, here is the up to date version - but this time it has an "ASUS Verified" Check
> Seems ASUS XOC guys where not happy sharing their OC Tool outside of their ROG exclusive lineup ~ even when the lock is just "selfish/marking reasoned" to have 🙃
> Don't really have much motivation to dig with Cutter Cutter (Radare2 based on Ghydra) similar into it
> C8Tool.rar ~ June, 30th, 2021
> 
> Original source was HWBot , not exactly this thread exclusive, but Update 1007 (2020 October) has been some time since it was shared
> 
> 
> 270-201-123 , 2x 16GB (if staying at typical 14-15-30-45 base
> mini is not dual rank aware
> Likely something around this looks reasonable
> View attachment 2522095
> 
> 
> * DR needs B2 option
> View attachment 2522096












This passed or would you still recommend I change the values?



umea said:


> Taking into account Veii's last post about DR needing trfc/35x55, decided to bring on my stable 1T 56 setup time settings.
> Changed: tRTP (5->6), tRAS (25->28), and tRC (40->42) as well as trfc like mentioned.
> View attachment 2522103
> 
> 
> Time to see if it holds out for 25 cycles. I also had it running stable (well, 3 cycles) with my loose settings on 6/3/1, 6/3/2, and 7/3/1. It seems tRCDRD is the final boss, as changing it to 14 starts erroring out on just about everything (tons of 6s, 12s, 2s,etc immediately) no matter what I've tested so far. Will test these timings with 6/3/2 and 6/3/1 to see if there's a difference.


If you don't mind me asking what is the significance of running tCKE at 7?


----------



## Veii

mongoled said:


> Hmmm, ive never tried this before.
> 
> So with my current settings I would be looking at
> 
> tRAS @21
> tRC @35
> 
> and then something like
> 
> tRTP @7
> tWR @12
> tRFC/tRFC2/tRFC4 @245/182/112
> 
> Will give it a try, thanks !


Yep, but keep also in mind that tRAS 21 often does not work
The same goes for low tRFC

You very like will need to work with *8 , tRTP 8, tWR 16 and higher tRFC
You'll notice :3








Tried to drop tRTP with tWR & tRAS to 22-37, but that was already a no-go
can not see anywhere any wiggle room ~ but on the positive side , 144ns tRFC are fine with higher heat and high voltage. Soo i'm perfectly fine with it.
just want to mention that there is close to zero wiggle room, and the old GDM comparison picture 14-14-14 also needed high voltage (1.6v) , to make 14-14-14-28-29 even be possible
tRASmin is a more humane way ~ but it's remaining a "minimum" value

If something small is off, it will never work
Start in little steps is what i want to tell 
tRTP 8 or maybe even 10 with tWR 20 (dual rank usually needed double tWR)
Way lower tRAS will give enough performance to cover big tWR bandwidth loss. Later you can scale down

Tried to drop tRRD_L or tWTR_L, nothing 
Maybe SCL later and maybe tFAW , unsure if it has any wiggle room either

Bruteforcing low primaries ~ your main goal still , nevertheless if it can or can not do it the easy way
At the end, the hassle is worth


Audioboxer said:


> This passed or would you still recommend I change the values?


Yes it's better 
unless you exactly know why they are lower faster, better copy the fabs binning process/ruleset


----------



## Audioboxer

Veii said:


> Yep, but keep also in mind that tRAS 21 often does not work
> The same goes for low tRFC
> 
> You very like will need to work with *8 , tRTP 8, tWR 16 and higher tRFC
> You'll notice :3
> View attachment 2522117
> 
> Tried to drop tRTP with tWR & tRAS to 22-37, but that was already a no-go
> can not see anywhere any wiggle room ~ but on the positive side , 144ns tRFC are fine with higher heat and high voltage. Soo i'm perfectly fine with it.
> just want to mention that there is close to zero wiggle room, and the old GDM comparison picture 14-14-14 also needed high voltage (1.6v) , to make 14-14-14-28-29 even be possible
> tRASmin is a more humane way ~ but it's remaining a "minimum" value
> 
> If something small is off, it will never work
> Start in little steps is what i want to tell
> tRTP 8 or maybe even 10 with tWR 20
> Way lower tRAS will give enough performance to cover big tWR bandwidth loss. Later you can scale down
> 
> Tried to drop tRRD_L or tWTR_L, nothing
> Maybe SCL later and maybe tFAW , unsure if it has any wiggle room either
> 
> Bruteforcing low primaries ~ your main goal still , nevertheless if it can or can not do it the easy way
> At the end, the hassle is worth
> 
> Yes it's better
> unless you exactly know why they are lower faster, better copy the fabs binning process/ruleset


Thanks. So 264/168/125, but I presume that would be on the basis of me changing tRAS and tRC to 29/44? What about some of the other secondary timings?


----------



## Veii

Audioboxer said:


> Thanks. So 264/168/125, but I presume that would be on the basis of me changing tRAS and tRC to 29/44? What about some of the other secondary timings?


Compare your result to the screenshot above


----------



## mongoled

Veii said:


> Yep, but keep also in mind that tRAS 21 often does not work
> The same goes for low tRFC
> 
> You very like will need to work with *8 , tRTP 8, tWR 16 and higher tRFC
> You'll notice :3
> View attachment 2522117
> 
> Tried to drop tRTP with tWR & tRAS to 22-37, but that was already a no-go
> can not see anywhere any wiggle room ~ but on the positive side , 144ns tRFC are fine with higher heat and high voltage. Soo i'm perfectly fine with it.
> just want to mention that there is close to zero wiggle room, and the old GDM comparison picture 14-14-14 also needed high voltage (1.6v) , to make 14-14-14-28-29 even be possible
> tRASmin is a more humane way ~ but it's remaining a "minimum" value
> 
> If something small is off, it will never work
> Start in little steps is what i want to tell
> tRTP 8 or maybe even 10 with tWR 20 (dual rank usually needed double tWR)
> Way lower tRAS will give enough performance to cover big tWR bandwidth loss. Later you can scale down
> 
> Tried to drop tRRD_L or tWTR_L, nothing
> Maybe SCL later and maybe tFAW , unsure if it has any wiggle room either
> 
> Bruteforcing low primaries ~ your main goal still , nevertheless if it can or can not do it the easy way
> At the end, the hassle is worth


The settings i suggested I would try worked first time



But had slightly worse latency than the 24/7 settings I am aiming for (228/169/104).

Looking like frquency is the next step up, but my next stable jump is to 4133 mhz (FCLK 1966/2000 results in no post, reset BIOS scenario and 1933/2033 results in unreliable post )

😂😂


----------



## Koboldness

Something intetesting:
According to my three CPU ZEN3, all the same - 5800X, and three different memory kits, all 2x 16GB, to achieve flat 14 and mainly 14 tRCDRD, depends more on a CPU than on a ram itself.
Why? On two of the three 5800X, all three 2x 16GB memory kits are capable to run 3800/1900 flat 14. On the third 5800X, no one kit is able to do so, the CPU is able to run flat 15 or 14tCL+15tRCDRD mixed.
Anyway, the fact I am able to play with my memory is only thanks to this forum and people like @Veii, @mongoled, @KedarWolf and others. So BIG Thank You to you, thanks to you, I'm happy to overclock the memory. You teach me something new every day, that's great


----------



## Mach3.2

IMC silicon lottery strikes again


----------



## Audioboxer

Koboldness said:


> Something intetesting:
> According to my three CPU ZEN3, all the same - 5800X, and three different memory kits, all 2x 16GB, to achieve flat 14 and mainly 14 tRCDRD, depends more on a CPU than on a ram itself.
> Why? On two of the three 5800X, all three 2x 16GB memory kits are capable to run 3800/1900 flat 14. On the third 5800X, no one kit is able to do so, the CPU is able to run flat 15 or 14tCL+15tRCDRD mixed.
> Ram kits are all GSkill, namely: F4-4000C16D-32GTZR, F4-4000C16D-32GTZRA, F4-4400C17D-32GTRS.
> The screenshot is my daily, atm on test bench, CPU cooler Noctua NH-U14S, and one 120mm vent over ram. When its in the case, I use Corsair Vengeance as ram cooler, which is one 60mm fan. The other two CPU are in my wife and my son PCs.
> As well a tip, for me, the lowest ram temperature is when RttNom is disabled, Wr /3 and Park /4. ODT 36.9 +-1.
> Anyway, the fact I am able to play with my memory is only thanks to this forum and people like @Veii, @mongoled, @KedarWolf and others. So BIG Thank You to you, thanks to you, I'm happy to overclock the memory. You teach me something new every day, that's great


Interesting, would never have considered it could be CPU related as well!

_Looks at 5950x and what I paid for you, curse you 5950x!_ 🤣


----------



## boldenc

I have 2 latencies that can't go any lower, tCWL and tWRRD. 
PC doesn't boot with anything less. I tried up to 1.500v


----------



## Koboldness

Audioboxer said:


> Interesting, would never have considered it could be CPU related as well!
> 
> _Looks at 5950x and what I paid for you, curse you 5950x!_ 🤣


It may be, or as well may not be the reason. Take it with grain of salt, because sample of 3 CPUs and 3 memory kits I would still consider as really very small


----------



## mongoled

boldenc said:


> I have 2 latencies that can't go any lower, tCWL and tWRRD.
> PC doesn't boot with anything less. I tried up to 1.500v
> 
> View attachment 2522120


@Audioboxer
Already gave you some very good advice which you gave a like, but you have not taken this advice on board at all.



Audioboxer said:


> .8 of a difference could easily be attributed to background apps. I wouldn't worry about it.
> 
> As for expecting much lower on tCL14, while I'm far from an expert GDM on can "hide" minor issues/chokes on performance. I'd recommend trying to get timings stable with GDM disabled and 2T first.
> 
> You can see I just learned above GDM disabled with 1T and AddrCmdSetup at 56 while "similar" to GDM enabled/1T being "1.5T", it is a more "pure" 1.5T.


People will be more willing to help you if you can show a stable set with GDM Disabled as no one wants to waste their time second guessing what GDM is doing in the background !

And start with "flat" timings i.e. drop the tRCDRW @10 until you have known stable set of timings that you can compare to....


----------



## Audioboxer

mongoled said:


> @Audioboxer
> Already gave you some very good advice which you gave a like, but you have not taken this advice on board at all.
> 
> 
> 
> People will be more willing to help you if you can show a stable set with GDM Disabled as no one wants to waste their time second guessing what GDM is doing in the background !
> 
> And start with "flat" timings i.e. drop the tRCDRW @10 until you have known stable set of timings that you can compare to....


Uh, what? Wrong tag? I am not running GDM lol.

*edit* - Sorry, I noticed you were tagging me to advise boldenc 🤣 Yeah @boldenc get GDM disabled and begin from there. It was the first thing I learned coming into this topic.

Going to try Veii settings from here https://www.overclock.net/attachments/1629674894789-png.2522095/

Involves loosening some timings but at this moment in time I'm all about having multiple BIOS profiles to stack up and see what scores each get and if any can help me with 1T pure more easily.


----------



## mongoled

Audioboxer said:


> Uh, what? Wrong tag? I am not running GDM lol.
> 
> *edit* - Sorry, I noticed you were tagging me to advise boldenc 🤣 Yeah @boldenc get GDM disabled and begin from there. It was the first thing I learned coming into this topic.
> 
> Going to try Veii settings from here https://www.overclock.net/attachments/1629674894789-png.2522095/
> 
> Involves loosening some timings but at this moment in time I'm all about having multiple BIOS profiles to stack up and see what scores each get and if any can help me with 1T pure more easily.


Well I did already suggest exactly those tRFC values a couple of posts back, before Veii gave similar advice

😝

But didnt know about the DR tRFC tweak ...



mongoled said:


> While using [email protected] [email protected] and [email protected] tRFC /tRFC2/tRFC4 should be 264/196/121
> 
> I would try
> 
> [email protected] [email protected]
> 240/178/110
> 
> You may need to raise vDIMM
> 
> 😊
> 
> Also tWR you can try 10


----------



## boldenc

mongoled said:


> @Audioboxer
> Already gave you some very good advice which you gave a like, but you have not taken this advice on board at all.
> 
> 
> 
> People will be more willing to help you if you can show a stable set with GDM Disabled as no one wants to waste their time second guessing what GDM is doing in the background !
> 
> And start with "flat" timings i.e. drop the tRCDRW @10 until you have known stable set of timings that you can compare to....


I never tried to run with GDM off, so now I just change GDM to disabled and reset all timings to default and start from there ?


----------



## boldenc

this is the current settings with GDM disabled


----------



## mongoled

boldenc said:


> this is the current settings with GDM disabled
> 
> View attachment 2522121


Do the below, reboot and post ZenTimings screenshot (should post)


----------



## Audioboxer

Holding up OK so far, though I'm not sure why Veii recommended tRP 15. I left it at 14


----------



## boldenc

mongoled said:


> Do the below, reboot and post ZenTimings screenshot (should post)
> 
> View attachment 2522122


booted fine


----------



## Veii

Audioboxer said:


> Holding up OK so far, though I'm not sure why Veii recommended tRP 15. I left it at 14


tRP generally should be near or equal to either tCL or tRCD. Mostly tRCD
You can only use less, if some timing is shorter and (p)recharge happens earlier that way, soo it would "overcharge" slightly and not timely "discharge"
because tRCDWR is not 13, i rounded up - to be sure it will be enough

tRP 14 + tRAS 29 = 43 tho
tRC will need to pass , soo if there is a timing issue - it will be masked by tRC 
For example this "lack of delay for precharge between loops" ~ but it can also work "just because" you use more voltage and usual

Good luck~

* oh if the set really is perfect, then tRDWR 8 should also pass 
But if not, you could need an adjustment on SD's / well tRCD 15 is the issue


----------



## mongoled

boldenc said:


> booted fine
> 
> View attachment 2522124


Now try

tRDWR @11
tWRRD @1


----------



## boldenc

mongoled said:


> Now try
> 
> tRDWR @11
> tWRRD @1


posted


----------



## Audioboxer

Veii said:


> tRP generally should be near or equal to either tCL or tRCD. Mostly tRCD
> You can only use less, if some timing is shorter and (p)recharge happens earlier that way, soo it would "overcharge" slightly and not timely "discharge"
> because tRCDWR is not 13, i rounded up - to be sure it will be enough
> 
> tRP 14 + tRAS 29 = 43 tho
> tRC will need to pass , soo if there is a timing issue - it will be masked by tRC
> For example this "lack of delay for precharge between loops" ~ but it can also work "just because" you use more voltage and usual
> 
> Good luck~
> 
> * oh if the set really is perfect, then tRDWR 8 should also pass
> But if not, you could need an adjustment on SD's / well tRCD 15 is the issue


I think I follow. Does this mean its preferable to change to tRC 43 or go with what Veii said and use tRP 15?

tRDWR on 8 normally passes fine, just put it to 9 to stick to what Veii showed me for this run.

Thanks


----------



## mongoled

boldenc said:


> posted
> 
> View attachment 2522125


So tell us, what are you wanting to achive ?

You should run this through 25 cycles of TM5 and a few hours of Y-Cruncher to see if it holds up.

Then you know you have a stable config to work from ..


----------



## boldenc

mongoled said:


> So tell us, what are you wanting to achive ?
> 
> You should run this through 25 cycles of TM5 and a few hours of Y-Cruncher to see if it holds up.
> 
> Then you know you have a stable config to work from ..


I am trying to achieve the lowest latency possible under 55ns

If I change to GDM enabled with current settings It should post?


----------



## Audioboxer

Jumping a little ahead here (1T pure), but I'd like to ask for learning, @Veii 










what does "depends if 6/4 exists or not" mean? Referring to Rtt on 6/4?


----------



## Mach3.2

Audioboxer said:


> Jumping a little ahead here (1T pure), but I'd like to ask for learning, @Veii
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> what does "depends if 6/4 exists or not" mean? Referring to Rtt on 6/4?


Probably referring to error #6 and #4.


----------



## Audioboxer

Mach3.2 said:


> Probably referring to error #6 and #4.


Ah right, that makes sense, would need to run for longer and see if they came up. Was just giving it a quick spin because prior attempts on 1T spat out a lot of errors on 6 right away, some on 0. ClkDrvStr needs to go from 40 to 60 to stop that at the start but as you can see error 1 comes up early.

Anyway, back to working on 2T profiles.


----------



## mongoled

boldenc said:


> I am trying to achieve the lowest latency possible under 55ns
> 
> If I change to GDM enabled with current settings It should post?


Im not understanding why you are fixated on GDM enabled its been explained by numerous people numerous times on this thread to concentrate on getting a stable set with GDM disabled and taking it from there.

You can get lower than 55ns with 2T no problem, though you will probably have to go to flat 15s etc.

I dont know if it will post with GDM enabled, the PC is in your hands 

😀


----------



## boldenc

And that what you get with to much play 😄


----------



## umea

Koboldness said:


> Something intetesting:
> According to my three CPU ZEN3, all the same - 5800X, and three different memory kits, all 2x 16GB, to achieve flat 14 and mainly 14 tRCDRD, depends more on a CPU than on a ram itself.
> Why? On two of the three 5800X, all three 2x 16GB memory kits are capable to run 3800/1900 flat 14. On the third 5800X, no one kit is able to do so, the CPU is able to run flat 15 or 14tCL+15tRCDRD mixed.
> Ram kits are all GSkill, namely: F4-4000C16D-32GTZR, F4-4000C16D-32GTZRA, F4-4400C17D-32GTRS.
> The screenshot is my daily, atm on test bench, CPU cooler Noctua NH-U14S, and one 120mm vent over ram. When its in the case, I use Corsair Vengeance as ram cooler, which is one 60mm fan. The other two CPU are in my wife and my son PCs.
> As well a tip, for me, the lowest ram temperature is when RttNom is disabled, Wr /3 and Park /4. ODT 36.9 +-1.
> Anyway, the fact I am able to play with my memory is only thanks to this forum and people like @Veii, @mongoled, @KedarWolf and others. So BIG Thank You to you, thanks to you, I'm happy to overclock the memory. You teach me something new every day, that's great


Looks like when I inevitably get zen3+ I'll play the amazon return game until I get a good chip


----------



## XPEHOPE3

mongoled said:


> But didnt know about the DR tRFC tweak ...


That's not a DR tweak, that's density tweak. Mine 4*16GB DR sticks have normal density (as per Thaiphoon Burner) and don't need that tweak.


----------



## mongoled

boldenc said:


> And that what you get with to much play 😄


Never ever had such message on my MSI


----------



## mongoled

XPEHOPE3 said:


> That's not a DR tweak, that's dendsity tweak. Mine 4*16GB DR sticks have normal density (as per Thaiphoon Burner) and don't need that tweak.


Thanks for being factually correct, I took a shortcut


----------



## mongoled

umea said:


> Looks like when I inevitably get zen3+ I'll play the amazon return game until I get a good chip


I dont like this behavoir at all ....


----------



## boldenc

mongoled said:


> Never even had such message on my MSI


Up and running again so next step to try 15 flat?
Should I increase vdimm to 1.50v?
Currently @ 1.45v
I will keep gdm disabled for now.


----------



## mongoled

boldenc said:


> Up and running again so next step to try 15 flat?
> Should I increase vdimm to 1.50v?
> Currently @ 1.45v
> I will keep gdm disabled for now.


Only you know if you reached your 55ns target!

I did say you should test for stability first, im out

Good luck


----------



## umea

mongoled said:


> I dont like this behavoir at all ....


Well it remains to be seen if it truly is the CPU, but Amazon is not a small company nor is it a good one so I have no qualms using their return policy to the fullest. That's how I see it at least.


----------



## boldenc

mongoled said:


> Only you know if you reached your 55ns target!
> 
> I did say you should test for stability first, im out
> 
> Good luck


Thank you for the help but I was not looking for stability at first. I was going to work on stability after I find the lowest latencies I can post with.


----------



## Veii

Audioboxer said:


> Jumping a little ahead here (1T pure), but I'd like to ask for learning, @Veii
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> what does "depends if 6/4 exists or not" mean? Referring to Rtt on 6/4?


Depends if you hit error #6 or error #4
You should always let it run a bit longer, to figure out what really is going on
Tiny timeout issue could be tRP


----------



## mongoled

boldenc said:


> Thank you for the help but I was not looking for stability at first. I was going to work on stability after I find the lowest latencies I can post with.


----------



## Audioboxer

Veii said:


> Depends if you hit error #6 or error #4
> You should always let it run a bit longer, to figure out what really is going on
> Tiny timeout issue could be tRP


Thanks Veii, it was just a quick run for fun and I wanted to ask about that part of the error message for an explanation. I'm working on 2T just now with your advice from earlier and need to make sure that is 100% stable first.



XPEHOPE3 said:


> That's not a DR tweak, that's dendsity tweak. Mine 4*16GB DR sticks have normal density (as per Thaiphoon Burner) and don't need that tweak.


What would 'normal density' be in Typhoon burner?

Mine says 8 Gb B-die (Boltzmann / 20nm) / 1 die.


----------



## Veii

boldenc said:


> Thank you for the help but I was not looking for stability at first. I was going to work on stability after I find the lowest latencies I can post with.


You have let's say 30 timings , make them two a set affecting each other
15^15 combinations, if math is correct
Too many rabbit holes - because aside from timings, you have also powering settings which change not only by timings but also by PCB strain on the chips (which increases by voltage and by timings)

Far too many rabbit holes
Step by step else you'll give up too early ~ i can even make a bet, that you will give up too early
You need something to fallback too for voltage checking and something to boot for letting windows repair corrupt sectors on countless bluescreens 
Not a good idea this approach.


umea said:


> Looks like when I inevitably get zen3+ I'll play the amazon return game until I get a good chip


Also not a good idea to trust amazon
Zen3D will be sold out close to instantly for the next 4 months, as it was with Vermeer

Pick an unknown shop or be prepared to stay/sleep infront of microcenter ~ to have a chance getting the first batch
CPU Supply didn't change, fabs didn't change ~ it will be the same story as it was for Vermeer from November till March, April

Or stay on amazon , but the chances will be very low again and it makes more sense to find a shop of trust


----------



## umea

Veii said:


> Also not a good idea to trust amazon
> Zen3D will be sold out close to instantly for the next 4 months, as it was with Vermeer
> 
> Pick an unknown shop or be prepared to stay/sleep infront of microcenter ~ to have a chance getting the first batch
> CPU Supply didn't change, fabs didn't change ~ it will be the same story as it was for Vermeer from November till March, April
> 
> Or stay on amazon , but the chances will be very low again and it makes more sense to find a shop of trust


Heh, well worst case I wait. Generally though from my experience Amazon has been pretty good (mostly if it's directly from amazon). The reason they're good for things like this is literally just because their return policy is so lenient because they just do not care unless you are returning 20 things a month. So if I were to buy say 5 5900x zen3d and send back 4, they wouldn't even bat an eye. People I know would just buy mice and send back the ones they don't like lol.

That is to say for other things that aren't basically a mini-lottery, I will always choose a local shop over Amazon, as I'd rather give them the business than Amazon.

In other news










These settings run stable on both 1T with setup times and 2T no setup times. Either way, I've tried a ton and can't figure out how to get tRCDRD to 14.

What is the downside of having 14 15 14 14? Is there some level of desync issue? Also, these run stably regardless of park being 1 2 or 3.

Also to @Audioboxer, I have 7 tCKE as the chart that Veii posted had it as optimal, but I think it's time I started messing with it as well. Might see if I can just get higher freq flat 15 to run nicely.


----------



## XPEHOPE3

umea said:


> These settings run stable on both 1T with setup times and 2T no setup times.


What are the latencies for both?



Audioboxer said:


> What would 'normal density' be in Typhoon burner?
> 
> Mine says 8 Gb B-die (Boltzmann / 20nm) / 1 die.


8Gb is "normal", other values are 4 (low) and 16 (high).


----------



## umea

XPEHOPE3 said:


> What are the latencies for both?


Running 4.6ghz all core locked for stable tm5 testing
55.4 1T 56 56 56 setup times
And very differing results on 2T. Anywhere from 55.0 to 55.9
Likely too close to be able to tell without averaging out large sample size.


----------



## Audioboxer

@Veii I tried your settings with two changes per what @mongoled told me










That being if I left tRP at 14 I should put tRC to 43 and I also went for tRDWR 8. As for where I go from here I guess this is a slightly more relaxed profile than my other tCL14 one










and maybe I'll have a look at 1T now if this passes y-cruncher OK. Oh, I almost forgot I reduced my voltages as well, 0.95v on VDDG and VSOC like 1.1 but it droops down a little. VDIMM dropped 0.1v as well just because of 264 tRFC vs 250 tRFC.

TB included for die but I have seen above @XPEHOPE3 has answered my question. I guess this means the "tRFC tweak" might not have been necessary for me, a bit confused, but OK TM5 passed anyway and with less voltage


----------



## XPEHOPE3

Audioboxer said:


> OK TM5 passed anyway and with less voltage


It took longer (2 minutes) and tested less memory (864 vs 832 MBs per core).
Since you have multiple stable setups you are already expected to use Aida64 latency (or try Intel MLC latency) to choose what to pursue.


----------



## GRABibus

Stable OC : F4-3800C14-16GTZN x 2











Best Aida64 bench :









I could break 60GB/s read value at 3800MHz RAM frequency


----------



## Audioboxer

XPEHOPE3 said:


> It took longer (2 minutes) and tested less memory (864 vs 832 MBs per core).
> Since you have multiple stable setups you are already expected to use Aida64 latency (or try Intel MLC latency) to choose what to pursue.


Learning is my main goal right now, like, I wouldn't even have noticed the less memory tested. Though I did notice it took longer but I put that down to some looser timings.

My main goal apart from learning is tackling 1T pure. Not due to chasing latency, I'm genuinely not even worried about latency right now, but I want to know what makes 1T pure work and when it isn't working, why.

With that latest pass above to me, someone without much knowledge, would think change to 1T and play about with resistances. But it's looking like I'm learning just now voltage may play a bigger role with 1T. I went lower on VSOC above and dropped VDDG from 0.975v to 0.95v but when moving to 1T and just upping ClkDrvStr to 60 I was getting fast errors on 6 again, something I didn't get here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread with slightly higher VSOC/VDDG.

Upping my VSOC and VDDG again seems to help clear errors on 6, but errors on 10 can pop up within the first 5~10 minutes. I ended up wanting another tCL14 profile with slightly more relaxed timings as I thought it might help me with pure 1T, but it's looking more complicated than that. So I'm trying to learn and tackle 1T pure whether it needs slacker timings, more voltage or some combination of resistances I haven't managed to crack yet.

I wouldn't like to think it's not possible at all with this RAM, rather, I'm just not knowledgeable enough to thread the needle yet needed to balance 1T pure. If I can manage it I'll be happy, even if I switch back to 2T for better latency in the end.


----------



## XPEHOPE3

GRABibus said:


> Stable OC : F4-3800C14-16GTZN x 2


Wow, "GDM on" crew strikes back hard 😄 
An Aida64 screenshot without safe mode would be nice though


----------



## PJVol

*@mongoled*
Can you do me a favor (?  ) and compare Scientific Analysis from Sandra Lite for various FCLK (MCLK) configs, at least 3800 (or 3733, in case of fclk hole) and the first bootable step above 3800 (i.e. 3866, or better 3933 or 4000) ?

I found a way to test, whether 1900+ fclk is stable, regardless of WHEA being reported or any voltage brute-forcing used.


Spoiler: My results for the 3600, 3800, 3933 and 4000 - all CL15:

















Spoiler: And how they correlate with that of GB5 Multicore: 















In case of GB5 - Machine Learning test (perhaps Image Inpainting too) obviously uses the same type of workload as the 1st Sandra test, which is matrix-matrix multiply.


----------



## GRABibus

XPEHOPE3 said:


> Wow, "GDM on" crew strikes back hard 😄
> An Aida64 screenshot without safe mode would be nice though


Here it is :










No particular optimizations in windows, except closing some processes.


----------



## Veii

GRABibus said:


> No particular optimizations in windows, except closing some processes.


This post should help you, the same order








[YT] 5950X WARZONE RAM SPEED FPS BENCHMARK







www.overclock.net






Audioboxer said:


> With that latest pass above to me, someone without much knowledge, would think change to 1T and play about with resistances. But it's looking like I'm learning just now voltage may play a bigger role with 1T. I went lower on VSOC above and dropped VDDG from 0.975v to 0.95v but when moving to 1T and just upping ClkDrvStr to 60 I was getting fast errors on 6 again, something I didn't get here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread with slightly higher VSOC/VDDG.
> 
> Upping my VSOC and VDDG again seems to help clear errors on 6, but errors on 10 can pop up within the first 5~10 minutes. I ended up wanting another tCL14 profile with slightly more relaxed timings as I thought it might help me with pure 1T, but it's looking more complicated than that. So I'm trying to learn and tackle 1T pure whether it needs slacker timings, more voltage or some combination of resistances I haven't managed to crack yet.
> 
> I wouldn't like to think it's not possible at all with this RAM, rather, I'm just not knowledgeable enough to thread the needle yet needed to balance 1T pure. If I can manage it I'll be happy, even if I switch back to 2T for better latency in the end.


Testing with Aida64 or at least SiSoftware Sandra Inter-tread
Would be helpful, to figure out after which voltage you start to see throttling
It is quite visible, and there wouldn't be a need to "y-cruncher benchmark" it continuously
Usually Aida64 can also be very accurate - but for such you'd need to have your windows act consistent. 

Lack of voltage optimally will not crash y-cruncher
But can always start to package throttle internally (trow away the first 2 Aida64 results)


----------



## XPEHOPE3

@GRABibus wow, you have higher CPU clock in safe mode! Never saw that tbh. OCing CPU to 5k would lower latency further, if you seek it.


----------



## Audioboxer

Veii said:


> This post should help you, the same order
> 
> 
> 
> 
> 
> 
> 
> 
> [YT] 5950X WARZONE RAM SPEED FPS BENCHMARK
> 
> 
> 
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> Testing with Aida64 or at least SiSoftware Sandra Inter-tread
> Would be helpful, to figure out after which voltage you start to see throttling
> It is quite visible, and there wouldn't be a need to "y-cruncher benchmark" it continuously
> Usually Aida64 can also be very accurate - but for such you'd need to have your windows act consistent.
> 
> Lack of voltage optimally will not crash y-cruncher
> But can always start to package throttle internally (trow away the first 2 Aida64 results)


Do you mean in terms of helping with 1T or just something I should be doing to find out if I'm throttling with any of the timings that pass TM5?


----------



## GRABibus

XPEHOPE3 said:


> @GRABibus wow, you have higher CPU clock in safe mode! Never saw that tbh. OCing CPU to 5k would lower latency further, if you seek it.


For those test I have set up a static OC 4.75GHz.
And yes, in safe mode, the CPU frequency is higher, maybe an overshoot at Aida launch or a bad reading from CPU-Z


----------



## Audioboxer

Alright, speaking of AIDA, I honestly haven't bothered with benching whilst learning but I guess I should to look for issues and start knowing what to look for in benchmarks 🤣

Such as cache/throttling issues Veii mentioned.










I see people using safe mode but this is just from my normal Windows. Anything look of concern here? This is my tighter profile out of the two tCL14s I have saved.

I've seen people down at like 51~53ns, and my guess is that can also be to do with CPU/SR/DR? As in, a 5950x with DR will have a higher bottom out than chips with less cores and on SR memory? Or am I wrong to think that? Some of the leaderboards I've seen tend to be dominated with SR at the top.

I'm happy with 56 anyway, I remember my Micron E-die was like 65 or something 😂 But of course if I can go lower I'll try my best to get there. Some useful tips in this topic over the weeks even pointed out to me overtightening can increase latency even if still stable. Like with tRTP. I guess I should look at that!


----------



## gled_fr

Audioboxer said:


> Alright, speaking of AIDA, I honestly haven't bothered with benching whilst learning but I guess I should to look for issues and start knowing what to look for in benchmarks 🤣
> 
> Such as cache/throttling issues Veii mentioned.
> 
> I've seen people down at like 51~53ns, and my guess is that can also be to do with CPU/SR/DR? As in, a 5950x with DR will have a higher bottom out than chips with less cores and on SR memory? Or am I wrong to think that? Some of the leaderboards I've seen tend to be dominated with SR at the top.
> 
> I'm happy with 56 anyway, I remember my Micron E-die was like 65 or something 😂 But of course if I can go lower I'll try my best to get there. Some useful tips in this topic over the weeks even pointed out to me overtightening can increase latency even if still stable. Like with tRTP. I guess I should look at that!


I get about 54.6-54.8ns and slightly better speeds with about the same ram as you, you should have a slighlty better bin according to XMP.
CL14 and 15 does not make a difference in AIDA for me. I also have a 5950X. It could be though that I am on
a ITX board, so 2 slots only. 1.46V for 15, 1.515 for cl14 and different trcd, trp/tras, all other subtimings being equal ( iirc ).
Your cache looks fine to me, although I do get 10.3ns for the l3 consistently. Usually when I got 10.5 something would fail during a loong tm5 test ( as in 60 cycles tests ).

Not on the PC, but I'm pretty sure you can find the stable 1T settings I used for that in my previous screenshots 

Still working on that flat 14s for the fun of it though, and alternating with trying to get IF > 1900 without WHEAs...

trcdrd doesn't like at all the 14 and haven't found yet a voltage combination that allows no WHEAs...


----------



## Audioboxer

gled_fr said:


> I get about 54.6-54.8ns and slightly better speeds with about the same ram as you, you should have a slighlty better bin according to XMP.
> CL14 and 15 does not make a difference in AIDA for me. I also have a 5950X. It could be though that I am on
> a ITX board, so 2 slots only. 1.46V for 15, 1.515 for cl14 and different trcd, trp/tras, all other subtimings being equal ( iirc ).
> 
> Not on the PC, but I'm pretty sure you can find the stable 1T settings I used for that in my previous screenshots
> 
> Still working on that flat 14s for the fun of it though, and alternating with trying to get IF > 1900 without WHEAs...
> 
> trcdrd doesn't like at all the 14 and haven't found yet a voltage combination that allows no WHEAs...


The B550 Unify X only has two DIMMs as well!

I was just reading there I should close all applications that might be "latency hogs", so I guess that is why people use safe mode lol. I'll try closing everything I can. I know the Nvidia stuff is a joke (I've got an external USB DAC and everyone complained about Nvidia with latency and it causing issues like popping over USB).

Other than that I guess some things could be overtightened or maybe your 5950x curve/PBO settings are more efficient than mine.

I was struggling with 1T at CL15 as well, but I will get back to it. I guess if you're running in 1T that might shave a bit off latency?


----------



## gled_fr

Audioboxer said:


> The B550 Unify X only has two DIMMs as well!
> 
> I was just reading there I should close all applications that might be "latency hogs", so I guess that is why people use safe mode lol. I'll try closing everything I can. I know the Nvidia stuff is a joke (I've got an external USB DAC and everyone complained about Nvidia with latency and it causing issues like popping over USB).
> 
> Other than that I guess some things could be overtightened or maybe your 5950x curve/PBO settings are more efficient than mine.
> 
> I was struggling with 1T at CL15 as well, but I will get back to it. I guess if you're running in 1T that might shave a bit off latency?


I do have the minimal number of services at launch yes ( nvidia control panel grrr ), although I just used sophia scripts and that was it.

I also reworked recently my CO tuning, and many cores are at -30 now. I need to redo that following @Veii method of changing cores around the failing one instead of the classic corecycler +1 on core that failed till stable. Still not really clear on how to proceed on that though.

You have better tRFC than me ( Can't recall where I left it, but I think I am at 264 ), so I suspect that if you get 1T, you'll get better results than me 

For me, the key to stabilize 1T was procODT at 36.9 after spending countless tries at 34. After that it was a walk in the park to lower subs like the DDs to 2 to get a bit more bw.


----------



## Audioboxer

gled_fr said:


> I do have the minimal number of services at launch yes ( nvidia control panel grrr ), although I just used sophia scripts and that was it.
> 
> I also reworked recently my CO tuning, and many cores are at -30 now. I need to redo that following @Veii method of changing cores around the failing one instead of the classic corecycler +1 on core that failed till stable. Still not really clear on how to proceed on that though.
> 
> You have better tRFC than me ( Can't recall where I left it, but I think I am at 264 ), so I suspect that if you get 1T, you'll get better results than me
> 
> For me, the key to stabilize 1T was procODT at 36.9 after spending countless tries at 34. After that it was a walk in the park to lower subs like the DDs to 2 to get a bit more bw.


Every set is different I guess, 1T has been very unkind to me so far, even resulting in me trying with 60 ClkDrvStr whereas I see most people run 40. But I'll get back to it soon and try to find out what "magical" combination my memory needs. It definitely seems to want a bit more VSOC on 1T than 2T to mitigate early errors on 6.

Does your tPHYDRL jump up to 28 on one stick with 1T CL14? I only seem to be able to keep it at 26 with 2T CL14 and 1T CL15.


----------



## gled_fr

Audioboxer said:


> Does your tPHYDRL jump up to 28 on one stick with 1T CL14? I only seem to be able to keep it at 26 with 2T CL14 and 1T CL15.


I tend to recall I am always at 26 tPHYDRL, but I would have to confirm that on the computer. 

I am running daily on the CL15 timings though, since no point for me to run CL14 with more vdimm for no gains.


----------



## walkman_w902

Audioboxer said:


> Interesting to see more anecdotal evidence patch C isn't great for memory.
> 
> I'm no expert and I don't have SR memory, but I'm going to do the easy thing I'll say for everyone now, get GDM disabled first! 2T!
> 
> That will also make it easier for people in this topic more knowledgeable than me to diagnose your errors. It's my understanding with GDM enabled other things can be modified automatically and it's harder to diagnose problems.
> 
> Plus, GDM disabled 2T should produce better latency when tweaked properly. At least, that's my understanding.
> 
> But as for the errors themselves, 2, 5 and 10 from here tRFC Calculator (mini)
> 
> B-die over 50 degrees is more likely to begin erroring out as well so I'd keep that in mind. If you can point a fan at your RAM for now and try to keep it under 50 and see if you get those errors again.


Well, they did something right with Patch C at least - previously I wasn't able to turn off GDM with settings above 3600, no matter how loose timings were. And now it's working on 3733.
Did some research and testing today - managed to find baseline OC 3733CL16 with VDIMM 1.37 or maybe lower - didn't have much time to test it extensively on 25+ cycles and Y-Crunch, looks like it's fine, but I'm eager for more.









Secondly, tried to make a work with 3733CL14 (VDIMM=1,47), but on my best effort I can't get rid of this at very start:














Played quite a lot with voltages, CAD_BUS and procODT, but it doesn't get any better than this, only new errors and BSODs arising. tWR 16 according to notes is too slow and 14 is too tight. VDIMM 1.448 too low and 1.562 too high. Temp at the hottest stick aren't above 53.5C and 56,5 is usually the threshold when I'm starting to pick up overheating errors. Need to rethink my strategy for now, any advices would be much much appreciated.


----------



## Audioboxer

gled_fr said:


> I tend to recall I am always at 26 tPHYDRL, but I would have to confirm that on the computer.
> 
> I am running daily on the CL15 timings though, since no point for me to run CL14 with more vdimm for no gains.


Makes sense! Whenever you have a minute I'd appreciate seeing what you ran for 1T at CL15.


----------



## gled_fr

Audioboxer said:


> Makes sense! Whenever you have a minute I'd appreciate seeing what you ran for 1T at CL15.


Sorry took me some time to get back to the actual computer.

here are my current daily settings ( 1.46Vdimm ):









That is running with the PBO settings:
PPT 320 / EDC 220 / TDC 180 / Scalar 6 / Max boost +50
CO: -4 Core 0 / -1 Core 1 / -29 Core 2&13 / -21 Core 6 / -18 Core 8 and 9 / -25 COre 11 / -16 Core 15 / -30 all other cores.


----------



## mongoled

PJVol said:


> *@mongoled*
> Can you do me a favor (?  ) and compare Scientific Analysis from Sandra Lite for various FCLK (MCLK) configs, at least 3800 (or 3733, in case of fclk hole) and the first bootable step above 3800 (i.e. 3866, or better 3933 or 4000) ?
> 
> I found a way to test, whether 1900+ fclk is stable, regardless of WHEA being reported or any voltage brute-forcing used.
> 
> 
> Spoiler: My results for the 3600, 3800, 3933 and 4000 - all CL15:
> 
> 
> 
> 
> View attachment 2522149
> 
> 
> 
> 
> 
> 
> Spoiler: And how they correlate with that of GB5 Multicore:
> 
> 
> 
> 
> View attachment 2522150
> 
> 
> 
> 
> In case of GB5 - Machine Learning test (perhaps Image Inpainting too) obviously uses the same type of workload as the 1st Sandra test, which is matrix-matrix multiply.


Was going to get round to this before you asked

🤣😂

I can do 3800 vs 4133 will do my best to normalise the timings as best I can as I only have a stable set for 4133 with flat 16s, will try to make one with flat 15s


----------



## Audioboxer

gled_fr said:


> Sorry took me some time to get back to the actual computer.
> 
> here are my current daily settings ( 1.46Vdimm ):
> 
> View attachment 2522221
> 
> 
> That is running with the PBO settings:
> PPT 320 / EDC 220 / TDC 180 / Scalar 6 / Max boost +50
> CO: -4 Core 0 / -1 Core 1 / -29 Core 2&13 / -21 Core 6 / -18 Core 8 and 9 / -25 COre 11 / -16 Core 15 / -30 all other cores.


Thanks I think my attempts were quite near this so I hope I can find my solution soon enough. I can't imagine it's my memory that simply won't do 1T given its bin so I guess I'd have to consider CPU/board. Though part of the reason I bought the Unify-X was for memory overclocking! Out of interest what AGESA patch are you on?

My CPU is currently 270/160/190. I don't mess with scalar after advice it just causes extra heat and instability for very little gains. But I guess if you're stable at 6x it might contribute to why your bench might be a bit better.










This is roughly what I was working on with 1T and 15. If I run 40/20/30/20 it spits out like 5~6 errors on 6 which results in a BSOD. If I increase the ClkDrkStr to 60 it can make it past 6 without a BSOD but still errors. At a point where I don't really know where to go, other than "blindly" changing voltages and resistances. Bit disappointing I seem to be having as much issues with 1T with this memory.



















Fiddle around with some timings, voltages and resistances and boom can clear the quick errors on 6 at the start lol. This is why I think I must be able to find a combination, eventually. But every change I make seems to bring up different errors. I guess this is the joys of 1T.


----------



## mongoled

Veii said:


> EDIT:
> Another info,
> I've reworked the tCKE to MCLK range a bit on the same Docs Sheet
> It is now usable on a wider range ~ but still misses alternative options to select from


Ive just been through all the posts since this one in search of the updated tCKE information but could not find it.

If you get a chance can you repost it


----------



## mongoled

Audioboxer said:


> Thanks I think my attempts were quite near this so I hope I can find my solution soon enough. I can't imagine it's my memory that simply won't do 1T given its bin so I guess I'd have to consider CPU/board. Though part of the reason I bought the Unify-X was for memory overclocking! Out of interest what AGESA patch are you on?
> 
> My CPU is currently 270/160/190. I don't mess with scalar after advice it just causes extra heat and instability for very little gains. But I guess if you're stable at 6x it might contribute to why your bench might be a bit better.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This is roughly what I was working on with 1T and 15. If I run 40/20/30/20 it spits out like 5~6 errors on 6 which results in a BSOD. If I increase the ClkDrkStr to 60 it can make it past 6 without a BSOD but still errors. At a point where I don't really know where to go, other than "blindly" changing voltages and resistances. Bit disappointing I seem to be having as much issues with 1T with this memory.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Fiddle around with some timings, voltages and resistances and boom can clear the quick errors on 6 at the start lol. This is why I think I must be able to find a combination, eventually. But every change I make seems to bring up different errors. I guess this is the joys of 1T.


Have you tried increasing your SCL values from 2 to 4 ?


----------



## Audioboxer

mongoled said:


> Have you tried increasing your SCL values from 2 to 4 ?


Nah, that's on the agenda next. Don't have time right now for proper testing, the above was just a quick example before I get to work.

The only reoccuring theme I've found so far is unless I run with ClkDrvStr 60 I end up with too many errors on 6 at the start which results in a BSOD. But my feeling from that is 60 is quite strong on the PCB and it might be resulting in lots of other crashes 5~10 minutes in.

I'll try the SCLs on 4 later.

*edit* - Snuck in one last experiment, AUTO out most settings










I've had errors that seem to suggest RttNom issues a few times on 1T, but everyone and their dog seems to run 6/3/3 with DR so the Rtt's are one of those things I have next to no knowledge on other than "run the settings 99% of other people run". I'm obsessing over the DrvStrs and playing around with some timings but I don't even know if there is a combination of Rtt's I should be trying other than 6/3/3. Because right now the only thing that seems to be a constant for me is if I don't run ClkDrvStr 60 I end up with too many errors on 6 to continue testing.


----------



## XPEHOPE3

Audioboxer said:


> This is roughly what I was working on with 1T and 15. If I run 40/20/30/20 it spits out like 5~6 errors on 6 which results in a BSOD.


Pay attention to this post maybe? It says clearly you need more VDIMM.


----------



## mongoled

So tRFC 228 passed 25 cycles of TM5, will do a few hours of Y-Cruncher then move onto getting 4133 mhz flat 15s somewhat stable for @PJVol experiment

Oh crap, just noticed tRTP is set to 7 arrgggghhhh,

oh well will redo this later, onto 4133 mhz ....


----------



## Audioboxer

XPEHOPE3 said:


> Pay attention to this post maybe? It says clearly you need more VDIMM.


I've tried up to 1.55v, didn't _seem_ to make a difference, so just reverted back to VDIMM that was stable at 2T. But hey, I'll try up to 1.6v later.

Can someone explain the "principles" behind 1T pure? If your memory isn't capable of it will it remain true it won't matter how loose a timing you run it'll struggle? I guess I can try dropping down to 3600/1800 just to see if I can get 1T pure running at 3600.

Just trying to figure out if it's worth spending 10s of hours on it if there is a "quicker" way to figure out if my memory, CPU, mobo or combination of the lot are simply not going to work on 1T pure.


----------



## Audioboxer

Experiment time










3800/C16 1.58v, down she goes right away.










3600/C16 1.55v, down again right away.










3600/C16, ClkDrvStr 60, made it to 4 cycles.

So my best progress has been on 3600/1800 and still needing ClkDrvStr 60. Not 100% sure what this is telling me other than maybe just give up on GDM disabled 1T


----------



## mongoled

@PJVol
Before I go any further which may not be the case just wanted to post this as results are not consistent between runs.

In the image below the 177 GFlops run was done first, after it finished I waited for 30 seconds then ran the test and the second run was 188 GFlops ???









Another run at 4133 mhz (tweaking voltages, LinpackXtreme is not passing residual tests ...)









At least the FFT test is consistent ..


----------



## mongoled

Audioboxer said:


> Experiment time
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 3800/C16 1.58v, down she goes right away.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 3600/C16 1.55v, down again right away.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 3600/C16, ClkDrvStr 60, made it to 4 cycles.
> 
> So my best progress has been on 3600/1800 and still needing ClkDrvStr 60. Not 100% sure what this is telling me other than maybe just give up on GDM disabled 1T


Dude you ain't even chasing rainbows

😂😂

Just use 1T with a setup timing and call it a day, the only thing worth the time and effort figuring out is tRCDRD and even then you got to put a time limit on how much time you spend on it, lol


----------



## Audioboxer

mongoled said:


> Dude you ain't even chasing rainbows
> 
> 😂😂
> 
> Just use 1T with a setup timing and call it a day, the only thing worth the time and effort figuring out is tRCDRD and even then you got to put a time limit on how much time you spend on it, lol


I know, I just get irritated at my lack of knowledge coming up against "Is something do-able if you know how to find the exact combination needed?".

I guess just now my advice for anyone would be do not spend the extra £20~30 on the 3600 14-14-14-14 rated memory. As of now the cheaper 3600 14-15-15-15 seems to be fully capable of performing better, silicon luck YMMV. Unless I also have a secondary issue such as my CPU or mobo holding me back a bit. One thing I did want to try was rolling back the AGESA c patch MSI have put out as beta right now. Just to make sure it wasn't funky on the memory front. There are a few complaints about the last few MSI bios and issues with memory on their QVL list.

But I'd be very surprised if this was BIOS related. _Seems_ to be bad luck with the memory IMC. I guess if I understood tCKE a bit more I could play around with it! Will put a bit more time into understanding it.


----------



## Mach3.2

@Audioboxer Being able to run 1900MHz IF, I'd say you're ahead of the curve already.


----------



## Audioboxer

Mach3.2 said:


> @Audioboxer Being able to run 1900MHz IF, I'd say you're ahead of the curve already.


Thank you for some perspective. I genuinely thought the newer 5xxx chips from AMD almost had 1900 IF as a shoe-in.


----------



## Mach3.2

Audioboxer said:


> Thank you for some perspective. I genuinely thought the newer 5xxx chips from AMD almost had 1900 IF as a shoe-in.


My sample size is approximately 2 CPUs, both can't post on 1900MHz IF.

Take that as you will.


----------



## Audioboxer

Mach3.2 said:


> My sample size is approximately 2 CPUs, both can't post on 1900MHz IF.
> 
> Take that as you will.


Same motherboard used? But yeah the luck of the draw on AMD when it comes to IF and memory overclocking can be wild. One has to keep hoping AGESA work can slowly bring more people a bit of luck with IF.


----------



## whocares7

Veii said:


> Can you guarantee that SOC won't drop even 10mV under load, as VDDG is just 40mV away from SOC.
> If you drop even 2mV , it will choke on voltage. Usually it's capable to manage itself, but your SOC is either too low or your VDDG IOD slightly too high
> Be sure that whatever SOC you put in the bios - you won't get slightly even slightly bellow 40mV (distance) on any load you run. Usually 50mV , but 40 is the absolute limit between IOD and SOC


Strangely that behavior occurred after Patch C update.
Changed vSOC LLC to 2 to tame the vdroop but now it seems to overshoot a bit..(1.11V)









I'll try to rework the whole CAD_BUS/vSOC/VDDG setups (50mv steps etc.)


----------



## Mach3.2

Audioboxer said:


> Same motherboard used? But yeah the luck of the draw on AMD when it comes to IF and memory overclocking can be wild. One has to keep hoping AGESA work can slowly bring more people a bit of luck with IF.


Yup, on the same X570 Tomahawk. The IF for this 5900X seem to top out at 1866MHz, 1933MHz is WHEA galore even with 1.2V++ of vSOC.

Just luck of the draw I guess, made my peace with it.


----------



## PJVol

mongoled said:


> just wanted to post this as results are not consistent between runs


Thanks!
Can you clarify, what config your results were compared to (if at all )?
What was the 180.66 Gflops result?

The point is to compare them to the results of 100% fclk-stable configs, such as 3600 - 3800 Mt/s, i.e. to whichever is affordable.

For my PC, the GEMM scores are quite consistent up to 1900Mhz, but start to regress significantly @1933 and above, while FFT ones remain unaffected.
Lookin at my results (will add one more with IF 2033), you can see the circa linear dependence of the GEMM scores on *vdd18* voltage.

I emphasize it, because that is the ONLY voltage affecting the result (given the RAM is stable, of course), so all above 1900 is basically in the same ballpark.
They differ solely due to the less vdd18 used for 3933 fclk (~1.9-1.95) and up to a maximum 2.1V for the 2066 run.

Don't know if you're still on MSI, but I'm looking forward to redo the test on my office PC with a B450 Mortar mb, hoping to confirm some of my assumptions.
Well, anyway, now we're getting somewhere


----------



## Veii

mongoled said:


> will do my best to normalise the timings as best I can as I only have a stable set for 4133 with flat 16s, will try to make one with flat 15s


Normalize the voltages please too
As it will be mostly a "lack of powerbudget" thing , going with higher FCLK
FCLK on their own will increase SOC current needed and EDC current wasted, soo maybe just focus on output Amperage for both SVI2 SOC & CPU sensors & focus on amperage on SOC and EDC ~ to normalize the result


whocares7 said:


> Strangely that behavior occurred after Patch C update.


Loadlines can change on a bios update - as the modules get also updated. But it never is for the worse
A PSP FW update will be pushed randomly , not always onto the CPU - soo once it's in there from new AGESAs (if supplied)
Even on downgrading ~ it will keep the new voltage behavior characteristics. Even when you downgrade and the boosting table for example changes
It will still remain how RZQ scales, how procODT scales and what your minimum voltages are now (on the old bios with the new PSP FW patch) *

SOC loadline you want to keep peaking what you set in the bios - but GET out the voltage you really want
That is if we speak about minimum voltage difference
But more SOC is not a bad thing, excessive
Less than your target, is an issue 

It can come a time where you'd need to increase the 1.8v line to minimum 1.83 - maximum 1.86 (without negative effects)
1.93+ , soo near 1.96 is then for 2000+ if you really need it
But IF you need it, means only that you'd use low procODT somehow, minimum cLDO_VDDP somehow - already have high SOC running because of FCLK and only then have to bump VDD 1.8v Rail, because memory will not train else with such low cLDO_VDDP
Or bios will missmatch IOL's between them, in our case it's tPHY values

* just so you know, once something drastically changes
For example IMC FW update, it will stay that way
Which is why i moan against AMDs hidden non documented changes between AGESA's. As one bad update (looking at the FCLK lock nonsense again) will be hardcoded till they fix it with another update
Nothing "a user" can do against that, soo they should be pushed very rarely and not that randomly onto us, with documented changes !
_(__looking at Spectre.v5 & branch prediction changes in the hidden)_


----------



## Audioboxer

Mach3.2 said:


> Yup, on the same X570 Tomahawk. The IF for this 5900X seem to top out at 1866MHz, 1933MHz is WHEA galore even with 1.2V++ of vSOC.
> 
> Just luck of the draw I guess, made my peace with it.


Ah so you have that black hole thing I've heard about? Can boot 1933 but can't boot 1900? Weird if that is what it is. And yeah, I get WHEA on 1933. For a real Christmas tree of WHEA though I boot 2000 then it's like severe spam 😂


----------



## domdtxdissar

Audioboxer said:


> Experiment time
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 3800/C16 1.58v, down she goes right away.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 3600/C16 1.55v, down again right away.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 3600/C16, ClkDrvStr 60, made it to 4 cycles.
> 
> So my best progress has been on 3600/1800 and still needing ClkDrvStr 60. Not 100% sure what this is telling me other than maybe just give up on GDM disabled 1T


You could try to run RTT's @ 7-3-3, it seems to work better then 6-3-3 for me atleast after further testing on my setup..
I also get the furthest with ClkDrvStr 60 on pure T1, but in the end i always end up with error 4 = pcb crash, so its seems like ClkDrvStr 40 is the highest usable for me also.

I'm just trying for even tighter tRAS -> tRC settings atm 








Have pretty much given up on pure T1 without setuptime on this daisychain 4 memoryslot CH8 motherboard, it simply cant be done with dualrank..  (2x8GB is so easy its not even funny)

But not all hope is lost, since i have a MEG B550 Unify-X on its way in the mail to me.. This should be a much better fit for my very nicely binned 2x16GB sticks and maybe pure T1 CL14 on dual rank can finally be achieved🙏🙏

The best thing is that i don't stand to lose that much money on this change either as my brother will buy my current rig consisting of CH8 and 5950x + my old 4x8GB stick when the new "5950 XT" get released.. My latest result with that combo is shown below so its not like its a bad deal for him either:







This last weekend i also completed the modification/installation of my GPU waterblock which gave me some pretty nice scores, now i have everything ready and can just drop that new zen3 v-cache edition in a rig ready for benching when i get it, it just need to get released first 



Spoiler: 3dmark scores



*Port Royal = 16 050* *@ *I scored 16 050 in Port Royal


Graphics Score = 16050
*TIME SPY =22 666 *@ I scored 22 666 in Time Spy


Graphics Score = 23 449
CPU Score = 19 062
*TIME SPY EXTREME = 12 180* @ I scored 12 180 in Time Spy Extreme


Graphics Score = 12 258
CPU Score = 11 760
*FIRE STRIKE = 43 513* @ I scored 43 513 in Fire Strike


Graphics Score = 49 613
Physics Score = 44 674
Combined Score = 22 188
*FIRE STRIKE extreme = 27 138 @* I scored 27 138 in Fire Strike Extreme


Graphics Score = 27 940
Physics Score = 44 267
Combined Score = 15 113
*FIRE STRIKE ULTRA = 15 072 * @ I scored 15 072 in Fire Strike Ultra


Graphics Score = 14 796
Physics Score = 44 514
Combined Score = 8 140


----------



## Mach3.2

Audioboxer said:


> Ah so you have that black hole thing I've heard about? Can boot 1933 but can't boot 1900? Weird if that is what it is. And yeah, I get WHEA on 1933. For a real Christmas tree of WHEA though I boot 2000 then it's like severe spam 😂


Yep, that's the one, 1900MHz FCLK hole.


----------



## Audioboxer

domdtxdissar said:


> You could try to run RTT's @ 7-3-3, it seems to work better then 6-3-3 for me atleast after further testing on my setup..
> I also get the furthest with ClkDrvStr 60 on pure T1, but in the end i always end up with error 4 = pcb crash, so its seems like ClkDrvStr 40 is the highest usable for me also.
> 
> I'm just trying for even tighter tRAS -> tRC settings atm
> View attachment 2522287
> 
> Have pretty much given up on pure T1 without setuptime on this daisychain 4 memoryslot CH8 motherboard, it simply cant be done with dualrank..  (2x8GB is so easy its not even funny)
> 
> But not all hope is lost, since i have a MEG B550 Unify-X on its way in the mail to me.. This should be a much better fit for my very nicely binned 2x16GB sticks and maybe pure T1 CL14 on dual rank can finally be achieved🙏🙏
> 
> The best thing is that i don't stand to lose that much money on this change either as my brother will buy my current rig consisting of CH8 and 5950x + my old 4x8GB stick when the new "5950 XT" get released.. My latest result with that combo is shown below so its not like its a bad deal for him either:
> View attachment 2522286
> 
> This last weekend i also completed the modification/installation of my GPU waterblock which gave me some pretty nice scores, now i have everything ready and can just drop that new zen3 v-cache edition in a rig ready for benching when i get it, it just need to get released first


"Glad" I'm not alone but I also wish you the best of luck, I have the B550 Unify-X and while I'll presume it is helping me a bit push the memory on 2 DIMMs it's not helped so far get 1T stable 

I had a go at 3800C15 with 5/3/2 and 60/20/40/20 on the basis of trying a more powerful Nom/Park and upping CsOdtDrvStr. All sorts of "fun". Some runs lasting 5~7 minutes before an error but a rainbow of errors ranging from 0 to 4 to 12 to 1 when I was playing around with voltage/ProcODT. Very difficult to figure out a base to go with. Was trying tCKE on 9 as well.

Seems like a "waste" of time right now, just going to work away at the best timings I can do, lowest voltage they'll run on and then I might move to AddrCmdSetup 1T depending on if there is even any latency gain to be had. Don't mind running 2T if not.

When you get the Unify-X try the latest stable BIOS first MSI MEG B550 UNIFY X Motherboard There is a few complaints the C bios is messing around with people's memory overclocks.



Mach3.2 said:


> Yep, that's the one, 1900MHz FCLK hole.


That sucks, but to me that seems like something that in theory, should, be able to be fixed by AGESA updates? I mean, being able to post 1933+ but not 1900 is just


----------



## rbys

@Mach3.2 We're tied for first place using micron rev.b, each with a result of 56ns 👀Zen RAM Overclocking


----------



## Mach3.2

rbys said:


> @Mach3.2 We're tied for first place using micron rev.b, each with a result of 56ns 👀Zen RAM Overclocking
> 
> 
> View attachment 2522304


tRCDRD doesn't budge below 18? The lowest my 3600MHz sticks go is 17, not sure if that's possible for your 3200MHz sticks.



Audioboxer said:


> That sucks, but to me that seems like something that in theory, should, be able to be fixed by AGESA updates? I mean, being able to post 1933+ but not 1900 is just


Might be fixable with an update to the IMC firmware but I'm not counting on it. 🌚


----------



## rbys

Mach3.2 said:


> tRCDRD doesn't budge below 18? The lowest my 3600MHz sticks go is 17, not sure if that's possible for your 3200MHz sticks.
> 
> 
> Might be fixable with an update to the IMC firmware but I'm not counting on it. 🌚


I tried all the way up to 1.45VDIMM and it wouldn't even POST. 3200C16 kit eh


----------



## gled_fr

Audioboxer said:


> Thanks I think my attempts were quite near this so I hope I can find my solution soon enough. I can't imagine it's my memory that simply won't do 1T given its bin so I guess I'd have to consider CPU/board. Though part of the reason I bought the Unify-X was for memory overclocking! Out of interest what AGESA patch are you on?
> 
> My CPU is currently 270/160/190. I don't mess with scalar after advice it just causes extra heat and instability for very little gains. But I guess if you're stable at 6x it might contribute to why your bench might be a bit better.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This is roughly what I was working on with 1T and 15. If I run 40/20/30/20 it spits out like 5~6 errors on 6 which results in a BSOD. If I increase the ClkDrkStr to 60 it can make it past 6 without a BSOD but still errors. At a point where I don't really know where to go, other than "blindly" changing voltages and resistances. Bit disappointing I seem to be having as much issues with 1T with this memory.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Fiddle around with some timings, voltages and resistances and boom can clear the quick errors on 6 at the start lol. This is why I think I must be able to find a combination, eventually. But every change I make seems to bring up different errors. I guess this is the joys of 1T.


I am on 1.2.0.3 Patch A, there's only 1.2.0.3 Patch B available atm for my mb, and it's beta so I'll wait a bit...

I know the pain, even though I went directly to 1T without going to 2T first.

Started from loose [email protected] GDM on and XMP subtimings, vdimm at XMP.
The process I went through:

turn gdm off, as per the first thing I learned reading here and 1T on directly since it was booting with the recommended rtt 6 3 3, I figured I might as well work with that right away
leave vddp and vddgs to what xmp was happy with. correct VSOC to have some distance of at least 50mV with droop to IOD.
tune the primaries down to flat 15. tune secondaries to what it's stable at, then tertiaries. I also did a lot of punching random numbers from people having the same RAM or just bdie, trying to stabilize their settings since I am still learning what it all means.
At that point I had to play with the rtt, *drvstr and procodt a lot to find the sweet spot => that was the painful part of trying to understand what errors meant what and chasing my tail, finally found some stability after a lot of trial and errors. and a lot of long tests with single errors.
from there, I started getting vddp and vddgs as low as possible, also getting vsoc down in the process.
once I found the bottom limits for the voltages, that allowed me to go down further on the subtimings, adding just a tiny bit of vdimm to stabilize the tighter subs.

Well all that to say, you'll find the combination that make it work 

For me at some point it was increasing procodt to 36 from 34 that made a huge leap progress after days of being stuck... you may have to do the opposite and go down lower ? I tend to recall increasing clk means you have to decrease procodt ? or maybe other str are playing and you should just go up one notch on one of them ?


----------



## Veii

domdtxdissar said:


> You could try to run RTT's @ 7-3-3, it seems to work better then 6-3-3 for me atleast after further testing on my setup..
> I also get the furthest with ClkDrvStr 60 on pure T1, but in the end i always end up with error 4 = pcb crash, so its seems like ClkDrvStr 40 is the highest usable for me also.


In this case, be sure you need X-20-24-24 or X-20-30-24, or even 40-20-40-20
Keep in mind that cLDO_VDDP is another factor - which you can lower with remain voltages - if you want to run ClkDrvStr 60
60-20-20-24 works for example, but will need a lower cLDO_VDDP voltage , just then low CsOdtDrvStr of 20 only - means it could make problems with training. Soo maaybe more VDDP is required
Depends. Low VDDP helps procODT to go down. More VDD 1.8v, helps in low procODT to go down 


gled_fr said:


> I tend to recall increasing clk means you have to decrease procodt ?


Correct 
Balancing thing. ProcODT is a global multiplier for it - ClkDrvStr is an "end-chain" multiplier. At the very end. Soo if you increase ClkDrvStr , then you have to lower procODT and maybe to lower procODT you need to lower all other voltages around it VDDP & VDDG 
1.8v rail is a bit different


----------



## mongoled

PJVol said:


> Thanks!
> Can you clarify, what config your results were compared to (if at all )?
> What was the 180.66 Gflops result?
> 
> The point is to compare them to the results of 100% fclk-stable configs, such as 3600 - 3800 Mt/s, i.e. to whichever is affordable.
> 
> For my PC, the GEMM scores are quite consistent up to 1900Mhz, but start to regress significantly @1933 and above, while FFT ones remain unaffected.
> Lookin at my results (will add one more with IF 2033), you can see the circa linear dependence of the GEMM scores on *vdd18* voltage.
> 
> I emphasize it, because that is the ONLY voltage affecting the result (given the RAM is stable, of course), so all above 1900 is basically in the same ballpark.
> They differ solely due to the less vdd18 used for 3933 fclk (~1.9-1.95) and up to a maximum 2.1V for the 2066 run.
> 
> Don't know if you're still on MSI, but I'm looking forward to redo the test on my office PC with a B450 Mortar mb, hoping to confirm some of my assumptions.
> Well, anyway, now we're getting somewhere


Looks like I didnt get my message across very well.

The first image I posted was to show that the results are not consistent.



> In the image below the 177 GFlops run was done first, after it finished I waited for 30 seconds then ran the test and the second run was 188 GFlops ???


To repeat the above quote, those two run were done one after the other without changing any settings .

The green bar in that picture is just a baseline, thats why I quoted the values (rounded off) for the red and blue bars.

I fully understood what you want me to do, but before I was going to do that I needed to determine for myself how the benchmark runs and its consistency !

Now onto the second picture that has the 206 GFlops for GEMM test, the only difference between the blue and green bar is I tweaked vSOC and vdd18 voltage.

Now...... as explained above im still trying to get a baseline understanding on how consistent this test is and I just ran the below

These are again two consecutive runs without changing any settings, here I am using my new 3800/1900 24/7 candidate profile.









Notice the trend ? The GEMM test is not consistent, I would not expect such a variation in the results.

My next question is how are you getting such high results or why am I getting such low results ?

Only my 4133/2067 run comes anywhere near your 3600/3800 runs ??

Admittedly I do not have the latest version installed (got notification of the update the other day) but I highly doubt that explains the difference in my results from yours.

Will install the latest version and see if the results change ...

** EDIT **
No difference with latest version

Are you running a fixed clock ? I am running my PBO/CO 24/7 settings, maybe thats the reason....

And to answer your query regards vdd18 voltage, its the key along with vSOC for performance not to tank when running high FCLK, my CPU sample does not need such high vdd18 voltage for 2066 mhz, I SET 1.89v and GET 1.94v.

For the 1900 runs I just left vdd18 voltage on defaults that gives me 1.84v (will increase this to see if it effects FCLK performance at 1900 mhz)

On a sidenote the C-patch BIOS is allowing 4133/2067 to run without the anomolies I was seeing with previous BIOS, these anomolies include USB "sticking", audio "glitches" and LatencyMon freaking out.

So far LatencyMon is behaving and USB sticking along with audio glitches are far far less occuring ..


----------



## mongoled

Veii said:


> Normalize the voltages please too
> As it will be mostly a "lack of powerbudget" thing , going with higher FCLK
> FCLK on their own will increase SOC current needed and EDC current wasted, soo maybe just focus on output Amperage for both SVI2 SOC & CPU sensors & focus on amperage on SOC and EDC ~ to normalize the result


Thats improbable !

My CPU sample can do FCLK 1900 and 2067 reliably, 1966/2000 dont post at all and 1933/2033 its hard to get them to post.

So going with 1900 vs 2067 its impossible to normalise vSOC and get results that are not flawed, if I run the same vSOC I do for 1900 with 2067 then the 2067 performance will tank, almost half the performance !


----------



## mongoled

@domdtxdissar
Lowering tRP is next on my list on releasing the bottleneck. Seeing watercooling the RAM has assisted in lowering tRFC hopefully will be the same with tRP

😊


----------



## Audioboxer

mongoled said:


> Thats improbable !
> 
> My CPU sample can do FCLK 1900 and 2067 reliably, 1966/2000 dont post at all and 1933/2033 its hard to get them to post.
> 
> So going with 1900 vs 2067 its impossible to normalise vSOC and get results that are not flawed, if I run the same vSOC I do for 1900 with 2067 then the 2067 performance will tank, almost half the performance !


Damn, the more I read about these FCLK holes the more my brain asks what is going on with AGESA/Ryzen CPUs? lol

To the layman it seems to make no sense whatsoever a LOWER figure won't POST but a higher one will.

Can anyone give me the ELI5 on why this can happen?


----------



## PJVol

What is eli5?


----------



## Audioboxer

PJVol said:


> What is eli5?


"Explain like I'm 5". Basically asking someone to dumb something down for you lol.


----------



## mongoled

Audioboxer said:


> Damn, the more I read about these FCLK holes the more my brain asks what is going on with AGESA/Ryzen CPUs? lol
> 
> To the layman it seems to make no sense whatsoever a LOWER figure won't POST but a higher one will.
> 
> Can anyone give me the ELI5 on why this can happen?


Not asking for much

🤣 🤣 😂


----------



## Audioboxer

mongoled said:


> Not asking for much
> 
> 🤣 🤣 😂


Yours is the most extreme I've seen, can't post 1966 but 2067 works?


----------



## mongoled

Audioboxer said:


> Yours is the most extreme I've seen, can't post 1966 but 2067 works?


For sure!

Only AMD can tell us and they are not saying anything ...


----------



## domdtxdissar

Veii said:


> In this case, be sure you need X-20-24-24 or X-20-30-24, or even 40-20-40-20
> Keep in mind that cLDO_VDDP is another factor - which you can lower with remain voltages - if you want to run ClkDrvStr 60
> 60-20-20-24 works for example, but will need a lower cLDO_VDDP voltage , just then low CsOdtDrvStr of 20 only - means it could make problems with training. Soo maaybe more VDDP is required
> Depends. Low VDDP helps procODT to go down. More VDD 1.8v, helps in low procODT to go down
> 
> Correct
> Balancing thing. ProcODT is a global multiplier for it - ClkDrvStr is an "end-chain" multiplier. At the very end. Soo if you increase ClkDrvStr , then you have to lower procODT and maybe to lower procODT you need to lower all other voltages around it VDDP & VDDG
> 1.8v rail is a bit different


Seems like 40-20-24-24 and 40-20-20-20 was the difference between passing 25 cycles or failing the run
(or it could also have been the small vsoc bump  )






vs








One thing is for certain atleast, i cant go any lower tRas -> tRC then this if i want to pass 25 cycles 
tRP 11 is also no bueno @ 1.57vdimm

Can also run DD's at 2, but don't think i saw any difference in the numbers..
And i canceled my B550 UNIFY-X order.. waiting for X570S UNIFY-X MAX instead since i need 2x M.2 PCI gen4 😇


----------



## Audioboxer

domdtxdissar said:


> Seems like 40-20-24-24 and 40-20-20-20 was the difference between passing 25 cycles or failing the run
> (or it could also have been the small vsoc bump  )
> View attachment 2522355
> vs
> View attachment 2522356
> 
> 
> One thing is for certain atleast, i cant go any lower tRas -> tRC then this if i want to pass 25 cycles
> tRP 11 is also no bueno @ 1.57vdimm
> 
> Can also run DD's at 2, but don't think i saw any difference in the numbers..
> And i canceled my B550 UNIFY-X order.. waiting for X570S UNIFY-X MAX instead since i need 2x M.2 PCI gen4 😇


Interesting settings, I'm about to try the GDM 1T via Setup shortly from this (pure 1T can go in the bin just now lol, fed up with it)










So I'll keep that in mind about CkeDrvStr going to 24.

Any reason you're running the VDDG IOD as high? Like, does it help with stability or is it just on AUTO? I think if left to auto mine is around 1.05~1.06.

My first thought was getting tRCDRD rolling at 14 might need it. I gave up at 14 at 3800 with my RAM fairly quickly.

Seeing as I bought a 2TB PCIE 4.0 drive I'm holding out on 1 slot fine for now, but that X570S UNIFY-X MAX does look tasty.


----------



## domdtxdissar

Audioboxer said:


> Any reason you're running the VDDG IOD as high? Like, does it help with stability or is it just on AUTO? I think if left to auto mine is around 1.05~1.06.


Hmm i don't actually think its my VDDG IOD 1060mv that is is "high", but its your VDDG IOD that's unusual low at only 975mv (?)
Anyway, if i lower voltages ill get WHEA errors with these new bioses.. (above AGESA 1.2.0.0)

On bioses from the start of the year i was running much lower VDDG CCD without any problems, so voltages is also very much bios depended...








(bios from December 2020)


----------



## Audioboxer

domdtxdissar said:


> Hmm i don't actually think its my VDDG IOD 1060mv that is is "high", but its your VDDG IOD that's unusual low at only 975mv (?)
> Anyway, if i lower voltages ill get WHEA errors with these new bioses.. (above AGESA 1.2.0.0)
> 
> On bioses from the start of the year i was running much lower VDDG CCD without any problems, so voltages is also very much bios depended...
> View attachment 2522358
> 
> (bios from December 2020)


Thanks, I can't actually remember where I took the 0.975v for CCD/IOD from, but I just sort of ran with it and I have no WHEA at 1900. But it does have me thinking about whether running it this low could have detrimental effects elsewhere?

But your post also makes me think I'll have a look at my CCD at some point as well and see if it can run lower. Ultimately, if I can run voltages lower with no issues that is of course better!


----------



## PJVol

mongoled said:


> Notice the trend ? The GEMM test is not consistent, I would not expect such a variation in the results.


Not a big variation, tbh, if we drop the one or two false positive ones.
Here I ran it 7 consequetive times, 1st and 2nd (didn't fit), 203 and 219 were out of the ordinary for sure. 6th was done after a 20-30s pause.


Spoiler: results 3-7

















mongoled said:


> My next question is how are you getting such high results or why am I getting such low results ?
> Only my 4133/2067 run comes anywhere near your 3600/3800 runs ??


Idk, likely the usual limiters, i.e. temps and silicon quality. On the other hand, yours seem to indicate positive scaling in response to the DF clock.
For a minute, I even thought, if such scaling discrepancy have something to do with the so called "FCLK-holes".



mongoled said:


> Are you running a fixed clock ? I am running my PBO/CO 24/7 settings, maybe thats the reason....


No, I had never ran it OC'ed for any significant period of time, other than for curiosity, doing some short benchmarks.

On a side note, what else I found worrying:
Something has really changed since AGESA 1.1.9.0, regarding OC stability, cause with a recent BIOS-es the CPU can't hold SSE or AVX loads with 4700Mhz anymore, even at 1.35V,
basically in the same tests, which were passed easily before with [email protected] on 1.1.9.0 AGESA and SMU 56.40.
Yet, to it's credit, new bios helped to acheive some neat scores in


Spoiler: GB 5 and CPU profile



basically top ones for the conventionally cooled 5600X 


























Result not found







www.3dmark.com









P2.10 4066CL15 18°C - Geekbench Browser


Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.



browser.geekbench.com










mongoled said:


> And to answer your query regards vdd18 voltage, its the key along with vSOC for performance not to tank when running high FCLK, my CPU sample does not need such high vdd18 voltage for 2066 mhz, I SET 1.89v and GET 1.94v.


Then I see two promising areas of focus for further digging (until someone is kind enough to contribute to the cause and provide their data  ):
1. Our CPU specimens are differ too much in IOD quality or
2. (this I lean more toward) The motheboard design, particulary VRM one, as well as PCB traces and elements quality do the trick.
Otherwise how one can explain, why vdd18 on my asrock board matters so much, and at the same time the influence of other voltages is close to ZERO.
So, I'll hold on the final thoughts until testing it on MSI board, likely tomorrow.


----------



## mongoled

PJVol said:


> Not a big variation, tbh, if we drop the one or two false positive ones.
> Here I ran it 7 consequetive times, 1st and 2nd (didn't fit), 203 and 219 were out of the ordinary for sure. 6th was done after a 20-30s pause.
> 
> 
> Spoiler: results 3-7
> 
> 
> 
> 
> View attachment 2522360
> 
> 
> 
> 
> Idk, likely the usual limiters, i.e. temps and silicon quality. On the other hand, yours seem to indicate positive scaling in response to the DF clock.
> For a minute, I even thought, if such scaling discrepancy have something to do with the so called "FCLK-holes".
> 
> 
> No, I had never ran it OC'ed for any significant period of time, other than for curiosity, doing some short benchmarks.
> 
> On a side note, what else I found worrying:
> Something has really changed since AGESA 1.1.9.0, regarding OC stability, cause with a recent BIOS-es the CPU can't hold SSE or AVX loads with 4700Mhz anymore, even at 1.35V,
> basically in the same tests, which were passed easily before with [email protected] on 1.1.9.0 AGESA and SMU 56.40.
> Yet, to it's credit, new bios helped to acheive some neat scores in
> 
> 
> Spoiler: GB 5 and CPU profile
> 
> 
> 
> basically top ones for the conventionally cooled 5600X
> View attachment 2522364
> 
> 
> View attachment 2522365
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Result not found
> 
> 
> 
> 
> 
> 
> 
> www.3dmark.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> P2.10 4066CL15 18°C - Geekbench Browser
> 
> 
> Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.
> 
> 
> 
> browser.geekbench.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Then I see two promising areas of focus for further digging (until someone is kind enough to contribute to the cause and provide their data  ):
> 1. Our CPU specimens are differ too much in IOD quality or
> 2. (this I lean more toward) The motheboard design, particulary VRM one, as well as PCB traces and elements quality do the trick.
> Otherwise how one can explain, why vdd18 on my asrock board matters so much, and at the same time the influence of other voltages is close to ZERO.
> So, I'll hold on the final thoughts until testing it on MSI board, likely tomorrow.


Temps should be a none issue as I have a full custom loop with CB23 going no higher than 78C even with ambient temps of 27C.

I've now got my baseline ready just running the tests now.

SisoftSandra database has been reset.

Have set a 4.5Ghz manual overclock using SET 1.325v which with vdroop gives me GET 1.3v

Results coming soon....

** EDIT **
a w.t.f moment is coming

🤣

Drum roll ......

First set of results are in and I am stumped! After each run the results for the GEMM test kept going up !!

Is there some sort of AI built into this test

😂😂

4.5 Ghz manual overclock
vCORE: SET 1.325v, GET 1.3v

vSOC: SET 1.1375v, GET 1.375v
CLDO vDDP: SET 0.905v, GET 0.903v
vDDG CCD: SET 1.025v, GET 1.024v
vDDG IOD: SET 1.065v, GET 1.062v
vDIMM: SET 1.48v, GET 1.50v









Now onto the 4133/2067 results .....

4.5 Ghz manual overclock
vCORE: SET 1.325v, GET 1.3v

vSOC: SET 1.2875v, GET 1.282v
CLDO vDDP: SET 0.925v, GET 0.924v
vDDG CCD: SET 1.065v, GET 1.625v
vDDG IOD: SET 1.105v, GET 1.104v
vDIMM: SET 1.52v, GET 1.54v
PLL18: SET 1.89v, GET 1.94v









I added a LinpackExtreme just to show there is no weirdness with regards to consistency of results using Linpack

I cant explain what is happening here in both baselines, was it a chance occurance that the 1900 FCLK results scaled each time I ran the test, and the huge inconsistencies in the 2067 FCLK test (im going to re-run these with a higher PLL18 voltage ..)

For both 1900 and 2067 FCLK here are the temps (from motherboard diagnostic LED) and power draw (Belkin watt meter) of system load during scientific test

23% into test 64C with power draw from 204-221W
46% into test 56C with power draw from 176-178W
69% into test 72C with power draw from 195-202W

** EDIT2 **
Increasing PLL18 voltage to 1.91v (SET) resulted in lower performance in LinpackXtreme, so I decided to lower PLL18 voltage to 1.88v (SET) and compare LinpackXtreme results, the results were the same as 1.89v (SET).

So I re-ran the scientific tests again and here are the results


----------



## Nikila

I got a new Gigabyte B450M DS3H with AITC 3000 Ram. But I cant get it to running at 3000Mhz. It is locked in 2133. I have a Ryzen 5 1600. I tried to enable XMP but after enabling XMP my pc won't boot up at all until resetting the BIOS. Please someone help me. I don't know anything about "Memory overclocking".


----------



## MikeS3000

I'm running 4x8 G.Skill Trident Z Neo Hynix DJR ram. It's not B-die but I think it's still fairly quick and affordable. Is there anything I can try at 3800 speed to tighten timings any more?


----------



## rbys

55.8ns with a Micron Rev B. 16GB x 2 SR 3200 C16 kit:










Too bad that I can't lower tCL, tCWL, tRCDRD... at all. Maybe I could do better if I had a 3600 C16 kit instead .


----------



## Veii

Nikila said:


> I got a new Gigabyte B450M DS3H with AITC 3000 Ram. But I cant get it to running at 3000Mhz. It is locked in 2133. I have a Ryzen 5 1600. I tried to enable XMP but after enabling XMP my pc won't boot up at all until resetting the BIOS. Please someone help me. I don't know anything about "Memory overclocking".


cLDO_VDDP at 700mV
840mV for 3334MT/s,
913 or 700 for 3467MT/s
866mV for 3400 MT/s
NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking... 


domdtxdissar said:


> Seems like 40-20-24-24 and 40-20-20-20 was the difference between passing 25 cycles or failing the run


As probably one of the phew who ever got 1T stable . or Semi 1T ~ good job !
Can you try to work your process up with SETUP timings, taking this sheet into consideration ?
* not copy, as it's not perfect

Figuring out values bellow the 32/33 half-cutting point, to be a true 1T ?








Should be possible to revert this 56-0-0
maybe 4-0-0 or 4-3-15, something along these lines


----------



## Kildar

WINDOWS 11 USERS!!

KiLL Widgets when testing! It eats up a bunch of processor time.

That is all...


----------



## Veii

Kildar said:


> WINDOWS 11 USERS!!
> 
> KiLL Widgets when testing! It eats up a bunch of processor time.
> 
> That is all...


Remove them fully with 








GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11


:zap: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11 - GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-t...




github.com


----------



## KedarWolf

Veii said:


> Remove them fully with
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11
> 
> 
> :zap: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11 - GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-t...
> 
> 
> 
> 
> github.com


I swear by this script for removing Windows 10/11 bloatware etc.

Edit: It's for customizing your Windows ISO/install.wim before installing Windows. Sophia script works on the live O/S I think.









Optimize-Offline Guide - Windows Debloating Tool, Windows 1803, 1903, 19H2, 1909, 20H1 and LTSC 2019


All credit goes to GodHand and who wrote and maintains this script. And to @gdeliana who created the fork of Godhand' s Script we are using for...




forums.mydigitallife.net





and use this fork of it.









Releases · gdeliana/Optimize-Offline


Optimize-Offline is a Windows 10 offline image optimization framework. - gdeliana/Optimize-Offline




github.com


----------



## tcclaviger

mongoled said:


> @tcclaviger
> 
> can you tell me about the Vipers your bought, are they still with A2 PCB and where did you purchase them from ?
> 
> Cheers


Sorry for the delay, was on vacation. Confirmed A2 pcb, purchased from B&H Photo.


----------



## Audioboxer

Veii said:


> Remove them fully with
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11
> 
> 
> :zap: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11 - GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-t...
> 
> 
> 
> 
> github.com


Thanks for this I really need to look into it. Worried I'll blow up my Windows installation but gotta have a go removing junk lol.


----------



## domdtxdissar

mongoled said:


> Temps should be a none issue as I have a full custom loop with CB23 going no higher than 78C even with ambient temps of 27C.
> 
> I've now got my baseline ready just running the tests now.
> 
> SisoftSandra database has been reset.
> 
> Have set a 4.5Ghz manual overclock using SET 1.325v which with vdroop gives me GET 1.3v
> 
> Results coming soon....
> 
> ** EDIT **
> a w.t.f moment is coming
> 
> 🤣
> 
> Drum roll ......
> 
> First set of results are in and I am stumped! After each run the results for the GEMM test kept going up !!
> 
> Is there some sort of AI built into this test
> 
> 😂😂
> 
> 4.5 Ghz manual overclock
> vCORE: SET 1.325v, GET 1.3v
> 
> vSOC: SET 1.1375v, GET 1.375v
> CLDO vDDP: SET 0.905v, GET 0.903v
> vDDG CCD: SET 1.025v, GET 1.024v
> vDDG IOD: SET 1.065v, GET 1.062v
> vDIMM: SET 1.48v, GET 1.50v
> 
> View attachment 2522416
> 
> 
> Now onto the 4133/2067 results .....
> 
> 4.5 Ghz manual overclock
> vCORE: SET 1.325v, GET 1.3v
> 
> vSOC: SET 1.2875v, GET 1.282v
> CLDO vDDP: SET 0.925v, GET 0.924v
> vDDG CCD: SET 1.065v, GET 1.625v
> vDDG IOD: SET 1.105v, GET 1.104v
> vDIMM: SET 1.52v, GET 1.54v
> PLL18: SET 1.89v, GET 1.94v
> 
> View attachment 2522419
> 
> 
> I added a LinpackExtreme just to show there is no weirdness with regards to consistency of results using Linpack
> 
> I cant explain what is happening here in both baselines, was it a chance occurance that the 1900 FCLK results scaled each time I ran the test, and the huge inconsistencies in the 2067 FCLK test (im going to re-run these with a higher PLL18 voltage ..)
> 
> For both 1900 and 2067 FCLK here are the temps (from motherboard diagnostic LED) and power draw (Belkin watt meter) of system load during scientific test
> 
> 23% into test 64C with power draw from 204-221W
> 46% into test 56C with power draw from 176-178W
> 69% into test 72C with power draw from 195-202W
> 
> ** EDIT2 **
> Increasing PLL18 voltage to 1.91v (SET) resulted in lower performance in LinpackXtreme, so I decided to lower PLL18 voltage to 1.88v (SET) and compare LinpackXtreme results, the results were the same as 1.89v (SET).
> 
> So I re-ran the scientific tests again and here are the results
> 
> View attachment 2522425


I have spent quite some time (many hours) finding the settings which give me the highest scores in this benchmark.. Seems to scale mostly from 1.8vPLL but also vsoc + IOD and CCD voltages.

Benchmarks was done with 6 core "5600x" @ *static 4.5ghz* so numbers are comparable.

Baseline 1900fclk run with 1.8vPLL @ 1.8v and *throttling so all the runs are pretty close* = scores around 168gigaflops








My highest scoring settings combo at 1900fclk = ~212 gigaflops average with peak at 248 gigaflops









My highest scoring settings combo at 1933fclk = heavy throttling and whea errors








My highest scoring settings combo at 1866fclk = decent scores for this speed i guess








I was observing the same as you, each run the results for the GEMM test kept going up. And seemingly by the exact same amount also sometimes... Not sure this benchmark can be trusted 

All testruns can be round here


----------



## MrHoof

domdtxdissar said:


> I was observing the same as you, each run the results for the GEMM test kept going up. And seemingly by the exact same amount also sometimes... Not sure this benchmark can be trusted











same here all are the exact same voltage/timings


----------



## mongoled

tcclaviger said:


> Sorry for the delay, was on vacation. Confirmed A2 pcb, purchased from B&H Photo.


Thanks for the confirmation, managed to fix the stick I damaged.

How you get on with your dimms ?



domdtxdissar said:


> I have spent quite some time (many hours) finding the settings which give me the highest scores in this benchmark.. Seems to scale mostly from 1.8vPLL but also vsoc + IOD and CCD voltages.
> 
> Benchmarks was done with 6 core "5600x" @ *static 4.5ghz* so numbers are comparable.
> 
> Baseline 1900fclk run with 1.8vPLL @ 1.8v and *throttling so all the runs are pretty close* = scores around 168gigaflops
> View attachment 2522464
> 
> 
> My highest scoring settings combo at 1900fclk = ~212 gigaflops average with peak at 248 gigaflops
> View attachment 2522470
> 
> 
> My highest scoring settings combo at 1933fclk = heavy throttling and whea errors
> View attachment 2522466
> 
> 
> My highest scoring settings combo at 1866fclk = decent scores for this speed i guess
> View attachment 2522467
> 
> 
> I was observing the same as you, each run the results for the GEMM test kept going up. And seemingly by the exact same amount also sometimes... Not sure this benchmark can be trusted
> 
> All testruns can be round here





MrHoof said:


> View attachment 2522488
> 
> 
> same here all are the exact same voltage/timings


Thanks ever so much, was hoping @PJVol was going to respond back so very much appreciate you guys going out your way to run this test suite to confirm what I have been seeing.

Wonder whats going on with PJVol sample and he is able to show more consistent results that seem to be higher then what we are all achieving ...


----------



## domdtxdissar

mongoled said:


> Wonder whats going on with PJVol sample and he is able to show more consistent results..


I dont think/know if this is whats happening with PJVol's results, but one way to make them consistent is to run too low 1.8v PLL voltage so they "throttle" like i show above in my first screenshot. (numbers are not going up after each consecutive run)



mongoled said:


> ...results that seem to be higher then what we are all achieving ...


If you want higher numbers just run higher clockspeed.. So far its just you and me that have been running static clocks @ 4.5ghz (with 6 cores, smt on) 

@ *Veii*
I will test diffrent values from that setup-timing table if i find the time after work today.

One strange thing tho, on my 4x8gb addcmdsetup 56 was the sweetspot like most other are running.
On my 2x16GB set addcmdsetup 5*5* is needed for some reason.. I get errors after only few mins with 56. (tested from 50 all the way up to max 63, 55 was the sweetspot on this memory configuration)


----------



## mongoled

domdtxdissar said:


> I dont think/know if this is whats happening with PJVol's results, but one way to make them consistent is to run too low 1.8v PLL voltage so they "throttle" like i show above in my first screenshot. (numbers are not going up after each consecutive run)
> 
> 
> If you want higher numbers just run higher clockspeed.. So far its just you and me that have been running static clocks @ 4.5ghz (with 6 cores, smt on)


Because of the incosistency in the results its not possible to determine if using PBO/CO assists in reaching a higher score.

When I used PBO/CO I got the same inconsistencies but never getting close to consistently getting the 2xx that PJVol posted and he said he is also running PBO/CO.

That is what I am talking about ...

All in all I think its best to disregard the results of the Scientific benchmark and others that use GEMM until we find out some information on why we are seeing what we are seeing


----------



## Audioboxer

domdtxdissar said:


> I dont think/know if this is whats happening with PJVol's results, but one way to make them consistent is to run too low 1.8v PLL voltage so they "throttle" like i show above in my first screenshot. (numbers are not going up after each consecutive run)
> 
> 
> If you want higher numbers just run higher clockspeed.. So far its just you and me that have been running static clocks @ 4.5ghz (with 6 cores, smt on)
> 
> @ *Veii*
> I will test diffrent values from that setup-timing table if i find the time after work today.
> 
> One strange thing tho, on my 4x8gb addcmdsetup 56 was the sweetspot like most other are running.
> On my 2x16GB set addcmdsetup 5*5* is needed for some reason.. I get errors after only few mins with 56. (tested from 50 all the way up to max 63, 55 was the sweetspot on this memory configuration)


Hmm interesting. I decided last night with my tightest C14 profile I was really down at the end rummaging around for taking 1~2 off a timing and instead of that I'd change direction to 1T with Setups. I ended up with a few issues just changing that profile to 1T/56. Boots fine of course, every 1T option boots for me, even pure. But I was getting an error or two just trying to pass a 3 cycle. Ended up loosening my timings a bit but went to sleep before trying much more.

Noticed you mention 55, and quickly jumped on it










3 cycle passes no problem. Some of my timings above haven't been reverted to their tightest (tWTRL/tWR was 8/10 on my saved BIOS), but I'll double check that later.

Not saying 56 _wouldn't_ pass for me if I spent more time on it, maybe my resistances need a tweak. But it's funny how it seems 55 is keen for the 25 cycle now 

No idea myself how going from 56 to 55 could make such a difference??? Maybe a potential 2x16 DR thing???


----------



## mongoled

Audioboxer said:


> But it's funny how it seems 55 is keen for the 25 cycle now


Probably 56 is on a "boundry" and dropping to 55 puts you on the other side of the curve ....

To test you would need to find a way to reliably test throughput between the two, unfortunately that is not possible.

For the record I see the same throughput/latency using 1T pure vs 1T with setup timings which makes absolutely no sense to me and as I have mentioned pure 1T is a no go but 1T using 56 is perfectly stable ...


----------



## Audioboxer

mongoled said:


> Probably 56 is on a "boundry" and dropping to 55 puts you on the other side of the curve ....
> 
> To test you would need to find a way to reliably test throughput between the two, unfortunately that is not possible.
> 
> For the record I see the same throughput/latency using 1T pure vs 1T with setup timings which makes absolutely no sense to me and as I have mentioned pure 1T is a no go but 1T using 56 is perfectly stable ...


Good way to put it. Once I've managed to pass a 25 cycle and y-cruncher with 1T/55 I might dedicate a small bit of time to poking around with 56. Dom does run some slightly different Rtt/resistances than me. There is possibly some margins for getting 56 to pass. For what end? Who knows, just for "science" I guess to see if its possible.

As for 1T pure, I'm just forgetting it exists right now  My tPHYRDL jumps to 28/26 whether I'm using 1T Pure or 55. It seems at 3800 with tCL on 14 it's just the way it is. Only if I run tCL 15 and 1T at 3800 (pure or with setup) does it drop back down to 26/26.

The one thing I never understood is tCL 15 at 2T changes to 28 lol.

But I can see above that happens for Dom as well on 2x16 3800 tCL 14. Unless his 2nd stick is also on 28. Wonder if it's anything to do with all of us stuck at 15 on tRCDRD?


----------



## mongoled

Audioboxer said:


> The one thing I never understood is tCL 15 at 2T changes to 28 lol


This is most likely to do with a "bug" in the BIOS.

I have something similar which was not happening with earlier BIOS with settings that worked, 

on current BIOS flat 15s work fine at 4133/2067, it I switch to flat 16s it gets stuck at memory training ....


----------



## Audioboxer

mongoled said:


> This is most likely to do with a "bug" in the BIOS.
> 
> I have something similar which was not happening with earlier BIOS with settings that worked,
> 
> on current BIOS flat 15s work fine at 4133/2067, it I switch to flat 16s it gets stuck at memory training ....


Ahhh, interesting! Given the limitations of my old memory I never actually tried this new set of memory on any BIOS other than the one I am currently on 7D13vA41(Beta version), AMD ComboAM4PIV2 1.2.0.3c.

Will be interesting to see what newer BIOS bring to the table. I guess I could flashback to older BIOS versions but right now I don't want to touch anything like that as I have a setup I'm fairly happy with 

As much as I like AMD CPUs and had no issues switching over from intel and enjoying AMD motherboards getting PCIE 4.0 NVMe "early", it seems the history of the AMD BIOS has been a hell of a bumpy ride. Even now who knows what on earth is going on with the IF... Really inconsistent.


----------



## tolis626

Hey guys. First time posting in this thread. I tried to read as much as I could, but I did get a bit lost even though I'm not a newbie. RAM overclocking still seems like voodoo to me. Please forgive any stupidity that you may see.

So here's the thing. Ever since I bought my 5900x, I haven't bothered messing with my RAM and left it at XMP. It's ok, it's a B-die 3600CL16 kit from G.Skill, but I've seen 5900x's doing much better than mine with the only difference being the memory, so I decided to go down the rabbit hole of memory overclocking again. I used to run 3800MHz CL16 on my 3800x, but I decided to push this kit a bit, see what it's capable of. 3600MHz CL14 works like a charm at 1.45V in BIOS (more like 1.425V read in OS), so I decided to bump it up a notch to 3800MHz. Without messing with anything else, it failed to boot at 1.475V and 1.5V. I had to set it to either 1.51 or 1.52V in BIOS for it to boot (can't remember which one it was). I also bumped procODT to 43.6Ω and loosened tRAS and tRC a bit. It booted and seemed to run fine, but I got an error about 1 hour into testing with Karhu RAM test. As I don't feel very comfortable going higher in voltage, I'd appreciate some pointers as to where I can go next. FYI, this is at 1T and GDM off, but I'm trying to avoid 2T and GDM on if I can and, given that it's a single rank kit, I think I can. Below is a screenshot of the failed attempt. Any advice is welcome! Thanks!

PS : These DIMMs do get a bit toasty at 1.5V. What's the max temp I should look out for?

PS2 : I've tried changing some stuff. Tried up to 1.52V (In BIOS), tried procODTs of 36.9Ω, 40Ω and 43.6Ω, tried increasing tRFC, tRAS and tRC a tad, tried increasing primary timings other than tCL a bit, tried different RttWr, RttNom and RttPark options, yada yada yada, nothing works. It will pop an error at some point within the first hour, usually within the first 10 minutes. I am confused. I also tried disabling the RGB lights on my RAM and that helped with temperatures, but not stability. Maybe it's time to go 2T?


----------



## Mach3.2

Audioboxer said:


> As much as I like AMD CPUs and had no issues switching over from intel and enjoying AMD motherboards getting PCIE 4.0 NVMe "early", it seems the history of the AMD BIOS has been a hell of a bumpy ride. Even now who knows what on earth is going on with the IF... Really inconsistent.


It's really these small things that leave a bad taste in my mouth.

Admittedly my previous Intel platform was the i7 4770 and I didn't do any overclocking on my previous PC so there really isn't any recent Intel data point that I can reference to.


----------



## Audioboxer

Mach3.2 said:


> It's really these small things that leave a bad taste in my mouth.
> 
> Admittedly my previous Intel platform was the i7 4770 and I didn't do any overclocking on my previous PC so there really isn't any recent Intel data point that I can reference to.


I came from an i5 4960k lmao, my PC was basically a workhorse for years mostly being used for other things and no real upgrades for about 5 years. I decided while I don't play games as much as I used to with the shortages of consoles I'd go all in on a PC upgrade and ignore a PS5.

So I went with a 3900xt and X570f gaming. Happy to move to AMD at that point due to them really being better value for money than intel. But the more I got used to AMD the small issues came up. Overclocking a 3900XT wasn't much fun with PBO and I've always been reluctant to do manual overclocking on these chips. But the 5xxx series introduced better single core and the curve which is a step in the right direction. Thankfully I recouped a reasonable amount of money on my 3900XT and managed to snag a 5950x for RRP when it came back in stock.

That being said over a year now with AMD bioses has shown me how janky they can be, from USB issues for ages, to the weird IF inconsistency to RAM settings deciding to simply go from stable to unstable. Then there was all the "issues" with AMD powerplans and individuals _needing_ to tweak them until AMD scrapped them with the 5xxx processors. It seems as much as the hardware itself can be quite impressive AMD have a lot of work to do with software.


----------



## mongoled

Mach3.2 said:


> It's really these small things that leave a bad taste in my mouth.
> 
> Admittedly my previous Intel platform was the i7 4770 and I didn't do any overclocking on my previous PC so there really isn't any recent Intel data point that I can reference to.


Its the price of innovation!

Waiting to see how Intel does things when they eventually move to something completely new


----------



## Kildar

Veii said:


> Remove them fully with
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11
> 
> 
> :zap: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11 - GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-t...
> 
> 
> 
> 
> github.com


Yes, that's what I did. It's useless right now until they let third-party developers in.


----------



## tolis626

tolis626 said:


> Hey guys. First time posting in this thread. I tried to read as much as I could, but I did get a bit lost even though I'm not a newbie. RAM overclocking still seems like voodoo to me. Please forgive any stupidity that you may see.
> 
> So here's the thing. Ever since I bought my 5900x, I haven't bothered messing with my RAM and left it at XMP. It's ok, it's a B-die 3600CL16 kit from G.Skill, but I've seen 5900x's doing much better than mine with the only difference being the memory, so I decided to go down the rabbit hole of memory overclocking again. I used to run 3800MHz CL16 on my 3800x, but I decided to push this kit a bit, see what it's capable of. 3600MHz CL14 works like a charm at 1.45V in BIOS (more like 1.425V read in OS), so I decided to bump it up a notch to 3800MHz. Without messing with anything else, it failed to boot at 1.475V and 1.5V. I had to set it to either 1.51 or 1.52V in BIOS for it to boot (can't remember which one it was). I also bumped procODT to 43.6Ω and loosened tRAS and tRC a bit. It booted and seemed to run fine, but I got an error about 1 hour into testing with Karhu RAM test. As I don't feel very comfortable going higher in voltage, I'd appreciate some pointers as to where I can go next. FYI, this is at 1T and GDM off, but I'm trying to avoid 2T and GDM on if I can and, given that it's a single rank kit, I think I can. Below is a screenshot of the failed attempt. Any advice is welcome! Thanks!
> 
> PS : These DIMMs do get a bit toasty at 1.5V. What's the max temp I should look out for?
> 
> PS2 : I've tried changing some stuff. Tried up to 1.52V (In BIOS), tried procODTs of 36.9Ω, 40Ω and 43.6Ω, tried increasing tRFC, tRAS and tRC a tad, tried increasing primary timings other than tCL a bit, tried different RttWr, RttNom and RttPark options, yada yada yada, nothing works. It will pop an error at some point within the first hour, usually within the first 10 minutes. I am confused. I also tried disabling the RGB lights on my RAM and that helped with temperatures, but not stability. Maybe it's time to go 2T?
> View attachment 2522560


Sorry for the spam, boys, but changing to 2T also fails. This is getting ridiculous.


----------



## Audioboxer

tolis626 said:


> Sorry for the spam, boys, but changing to 2T also fails. This is getting ridiculous.


I would try 3800 at tCL15 first considering GDM is disabled. I've got a set that is binned for 3600 14-14-14-34, but even "only" going to 3800 I cannot get tRCDRD stable at 14 and I had to do a bit of work to begin to get tCL14 profiles, with tRCDRD at 15, stable. Other than just pump voltage.

So I would try flat 15 at 2T first. Try and get a feeling for your RAM at 3800. If you're still struggling even just go flat 16 at 3800 to try and get some sort of baseline.


----------



## Mach3.2

Audioboxer said:


> That being said over a year now with AMD bioses has shown me how janky they can be, from USB issues for ages, to the weird IF inconsistency to RAM settings deciding to simply go from stable to unstable. Then there was all the "issues" with AMD powerplans and individuals _needing_ to tweak them until AMD scrapped them with the 5xxx processors. It seems as much as the hardware itself can be quite impressive AMD have a lot of work to do with software.


I'm only on AMD's platform for the last 7 months and so far I'm pretty happy with my computer, less the FCLK hole that seem to be on many of these CPUs.

Regarding USB issues, I don't experience the widely reported "mouse hitching" issue, but it's my external USB SSD that is acting weird. 

Turns out it's because of hwinfo sensor window because I only ever get terrible response from my USB SSD when hwinfo sensor window is open, and I can replicate the issue on demand by starting hwinfo's sensor window. Killing hwinfo made the problem disappear.



mongoled said:


> Its the price of innovation!
> 
> Waiting to see how Intel does things when they eventually move to something completely new


Yep, for the most part I'm happy with my system. Let's see what Intel can pull out from their hat.


----------



## mongoled

tolis626 said:


> Sorry for the spam, boys, but changing to 2T also fails. This is getting ridiculous.


Nothing ridiculous about this seeing we have no idea where exactly the issue is !

The reason many use TM5 to test with is because it gives error codes that assist us in working out where possible issues may lay.

So I strongly suggest you download it and set it to run 25 cycles and post us what error codes it comes up with ...


----------



## tolis626

Audioboxer said:


> I would try 3800 at tCL15 first considering GDM is disabled. I've got a set that is binned for 3600 14-14-14-34, but even "only" going to 3800 I cannot get tRCDRD stable at 14 and I had to do a bit of work to begin to get tCL14 profiles, with tRCDRD at 15, stable. Other than just pump voltage.
> 
> So I would try flat 15 at 2T first. Try and get a feeling for your RAM at 3800. If you're still struggling even just go flat 16 at 3800 to try and get some sort of baseline.


Thanks for the insight!

That said, I know for a fact that my RAM will run no problem at 3800MHz with flat 15s for timings (1T, GDM off, taken from the 3800MHz fast profile of Ryzen DRAM Calculator) at under 1.45V. It was running like that for almost a year on my 3800x, tested multiple times with no issues. I am using that as my baseline. I just had never dared to push my luck with higher clocks or tighter timings, because I thought I wouldn't be able to do 3800MHz CL14 and anything above 1900MHZ fclk would fail on my 3800X.

Now, if what I'm currently testing fails too, I'll give a higher tRCDRD a shot, see where it takes me. 2T failed just as quickly as 1T, so I think that my problem isn't with the primary timings. Hmmm...


mongoled said:


> Nothing ridiculous about this seeing we have no idea where exactly the issue is !
> 
> The reason many use TM5 to test with is because it gives error codes that assist us in working out where possible issues may lay.
> 
> So I strongly suggest you download it and set it to run 25 cycles and post us what error codes it comes up with ...


Well, I paid money for Karhu, so I'm getting my money's worth, damn it! 

In all seriousness, I've grown to like this little tool a lot. I mean, it found issues where HCI had failed to do so, it does so quickly and it does so conveniently. I haven't used TM5, but any time I thought I'd give it a shot, it was all in Russian and I didn't even bother downloading it. I don't know what it is, but there's something about writter Russian that stresses me out. 

Having said that, if I can't find any solution to my problems with Karhu, I'll give it a shot, maybe it'll give me some pointers. Thanks for the suggestion!


----------



## mongoled

tolis626 said:


> Thanks for the insight!
> 
> That said, I know for a fact that my RAM will run no problem at 3800MHz with flat 15s for timings (1T, GDM off, taken from the 3800MHz fast profile of Ryzen DRAM Calculator) at under 1.45V. It was running like that for almost a year on my 3800x, tested multiple times with no issues. I am using that as my baseline. I just had never dared to push my luck with higher clocks or tighter timings, because I thought I wouldn't be able to do 3800MHz CL14 and anything above 1900MHZ fclk would fail on my 3800X.
> 
> Now, if what I'm currently testing fails too, I'll give a higher tRCDRD a shot, see where it takes me. 2T failed just as quickly as 1T, so I think that my problem isn't with the primary timings. Hmmm...
> 
> Well, I paid money for Karhu, so I'm getting my money's worth, damn it!
> 
> In all seriousness, I've grown to like this little tool a lot. I mean, it found issues where HCI had failed to do so, it does so quickly and it does so conveniently. I haven't used TM5, but any time I thought I'd give it a shot, it was all in Russian and I didn't even bother downloading it. I don't know what it is, but there's something about writter Russian that stresses me out.
> 
> Having said that, if I can't find any solution to my problems with Karhu, I'll give it a shot, maybe it'll give me some pointers. Thanks for the suggestion!


Here is the direct link



https://testmem.tz.ru/tm5.rar



Run the program as admin, then close it

Go into the bin folder and delete the cfg.link file

Then open the Mt.cfg file with notepad, find the word "Cycles" and change it to 25 save and close the file.

Now when you run it it will be for 25 cycles.

Any error codes that pop up post them here


----------



## XPEHOPE3

mongoled said:


> Here is the direct link
> 
> https://testmem.tz.ru/tm5.rar
> Run the program as admin, then close it
> 
> Go into the bin folder and delete the cfg.link file
> 
> Then open the Mt.cfg file with notepad


You could have bothered checking what config it would be. Obviously not 1usmus_v3 (wrong test sequence, no tests past test #5), for which there are error codes.
Here is the correct config.



tolis626 said:


> What's the max temp I should look out for?


45°C for all B-dies as per specs.


----------



## walkman_w902

Feel like I should post an update for the history since it looks I'm the only one around here trying to OC 4 sticks of SR. Spent 5 days (mostly evenings/nights) on them and now I'm fed up
Problem is that 4 sticks are incredibly more taxing for the IMC comparing to the 2 sticks: with 2 of them I can boot up to 4066 on memory even though WHEAs show up. With 4 of them 3733 is the limit (eventually I found 3800 & 3866 are achievable, but that's another story).
My ultimate goal was 3733 14-14-14-14-28, but I can't even do 3733 15-15-15-15-30. So many times I was correcting for one remaining error, but after that it was a blast of them. Here is the example, 3733CL15 gave me one error 5 on the last 4 minutes of 25 cycles. Tiny timeout issues are my worst enemies.







On the other hand "safe" OC with conservative 16-16-16-16-32 works flawlessly on 3800. I'm also able to boot them on 3866, but at some point of 25 cycles testing they gave me 4 WHEAs.







So now I'm sticking with this, since I don't want to invest more time to making what seems like impossible with my IMC:







It looks stable, Prime95 Large FFT for 1,5 hours went well, but I've got a few questions:
1. Currently voltages are on Auto setting except for VDIMM=1.4 and VSOC sitting at 1.1. It looks like my MB sets up VDDP way too high, what are your thoughts? Should I drop it down to 0,9 or 0,95 maybe? I have weird reboot and start up issues though: sometimes after I initiate reboot from Windows my screen goes black, peripherals turn off, but system continues working and doesn't cut off power and initiate POST. Same thing for cold starts - it POSTs normally, but after that screen goes black and no signs of Windows booting are shown.
2. Are there any interrelation between procODT and CAD_BUS timings, some general rule of thumb like with RttNom?
3. Should tWR and tCL/tRCDs be in sync in terms of ns in calculator? I was getting a lot of "tWR being too slow" errors while testing, but after that I decrease it by 1 I was getting a lot of tRFC issues.


----------



## walkman_w902

tolis626 said:


> Hey guys. First time posting in this thread. I tried to read as much as I could, but I did get a bit lost even though I'm not a newbie. RAM overclocking still seems like voodoo to me. Please forgive any stupidity that you may see.
> 
> So here's the thing. Ever since I bought my 5900x, I haven't bothered messing with my RAM and left it at XMP. It's ok, it's a B-die 3600CL16 kit from G.Skill, but I've seen 5900x's doing much better than mine with the only difference being the memory, so I decided to go down the rabbit hole of memory overclocking again. I used to run 3800MHz CL16 on my 3800x, but I decided to push this kit a bit, see what it's capable of. 3600MHz CL14 works like a charm at 1.45V in BIOS (more like 1.425V read in OS), so I decided to bump it up a notch to 3800MHz. Without messing with anything else, it failed to boot at 1.475V and 1.5V. I had to set it to either 1.51 or 1.52V in BIOS for it to boot (can't remember which one it was). I also bumped procODT to 43.6Ω and loosened tRAS and tRC a bit. It booted and seemed to run fine, but I got an error about 1 hour into testing with Karhu RAM test. As I don't feel very comfortable going higher in voltage, I'd appreciate some pointers as to where I can go next. FYI, this is at 1T and GDM off, but I'm trying to avoid 2T and GDM on if I can and, given that it's a single rank kit, I think I can. Below is a screenshot of the failed attempt. Any advice is welcome! Thanks!
> 
> PS : These DIMMs do get a bit toasty at 1.5V. What's the max temp I should look out for?
> 
> PS2 : I've tried changing some stuff. Tried up to 1.52V (In BIOS), tried procODTs of 36.9Ω, 40Ω and 43.6Ω, tried increasing tRFC, tRAS and tRC a tad, tried increasing primary timings other than tCL a bit, tried different RttWr, RttNom and RttPark options, yada yada yada, nothing works. It will pop an error at some point within the first hour, usually within the first 10 minutes. I am confused. I also tried disabling the RGB lights on my RAM and that helped with temperatures, but not stability. Maybe it's time to go 2T?


I suggest you to use @gled_fr general approach. It helped me a lot when I was playing with the voltages, RTT and CAD_BUS. Your RTT settings on the screenshot seems kinda strange, were they autoconfigured by MB?


gled_fr said:


> Started from loose [email protected] GDM on and XMP subtimings, vdimm at XMP.
> The process I went through:
> 
> turn gdm off, as per the first thing I learned reading here and 1T on directly since it was booting with the recommended rtt 6 3 3, I figured I might as well work with that right away
> leave vddp and vddgs to what xmp was happy with. correct VSOC to have some distance of at least 50mV with droop to IOD.
> tune the primaries down to flat 15. tune secondaries to what it's stable at, then tertiaries. I also did a lot of punching random numbers from people having the same RAM or just bdie, trying to stabilize their settings since I am still learning what it all means.
> At that point I had to play with the rtt, *drvstr and procodt a lot to find the sweet spot => that was the painful part of trying to understand what errors meant what and chasing my tail, finally found some stability after a lot of trial and errors. and a lot of long tests with single errors.
> from there, I started getting vddp and vddgs as low as possible, also getting vsoc down in the process.
> once I found the bottom limits for the voltages, that allowed me to go down further on the subtimings, adding just a tiny bit of vdimm to stabilize the tighter subs.


----------



## walkman_w902

XPEHOPE3 said:


> 45°C for all B-dies as per specs.


In 25 cycles of tm5? I'd call that impossible, even on my open bench it gets up to 50C with 1.4V, 22-24 ambient temp and fan aimed at them. "Limit" for my kit is 56,5C, after that I get a bunch of overheating errors. In games and working tasks it doesn't get above 42-43C on the hottest stick in case.


----------



## KedarWolf

Wow, is b-die ever temperature sensitive. I ran 1usmus_v3 at 1000% for eight cycles overnight, it started the seventh cycle when I woke up for work five hours later, no errors.

I turn my A/C off when I'm at work, get home, two errors just from my place heating up.

I have two 60mm RAM fans on it at 6800 RPM too.


----------



## MTup

Wow, I haven't posted here in years, actually since my FX8350 days anyhow bought this set of memory recently that is fairly new to the market from what I see. I have 16gb and a 5800x with a Gibibyte X570 itx. I would like to get it to 3800 frequency but haven't had any luck. 3600 has passed all the tests finally with the help here. This memory is 3600 Cl14 14 14 14 34. See what you think so far please and if you think 3800 frequency would be worth doing.


----------



## Sleepycat

walkman_w902 said:


> In 25 cycles of tm5? I'd call that impossible, even on my open bench it gets up to 50C with 1.4V, 22-24 ambient temp and fan aimed at them. "Limit" for my kit is 56,5C, after that I get a bunch of overheating errors. In games and working tasks it doesn't get above 42-43C on the hottest stick in case.


It depends on what clocks you run as well. Mine are 4x16GB sticks of B-die (2 kits of F4-3200C14D-32GTZSK), running at 3600 CL14-14-14-28 @ 1.48V. My case is old-school from 2009, with only 1 intake and 1 exhaust fan, and I have one of those DIMM coolers with 2x60mm fans, set to spin at 2600 rpm out of a max of 4200rpm). Yet, running 1usmus TM5, I hit a peak of 46.1 ºC and it idle at 35.1 ºC (ambient is 17.5 ºC, in-case temperature probe is 29 ºC)). I think it is because of the low 3600MHz DIMM clock.

So 45 ºC is possible.


----------



## mongoled

XPEHOPE3 said:


> You could have bothered checking what config it would be. Obviously not 1usmus_v3 (wrong test sequence, no tests past test #5), for which there are error codes.
> Here is the correct config.
> 
> 45°C for all B-dies as per specs.


FYI, this post was made from my laptop at home with my Ryzen PC at the office.

Nothing to do with being "bothered" as if I wasnt "bothered" why did I even make that post ???

More to do with not being aware that the default config produced by TM5 does not enable all the tests, this was compounded by the fact that I looked at the "Test Sequence" and saw that all the tests are included in the "Test sequence" construct.

The first time I used TM5 was several years ago, so if there is something I did wrong it was not remembering how the TM5 config is preconfigured by default.

Unsure why/or where this negativity has come from, maybe you did not understand that your post is passive aggressive....


----------



## Veii

On stock, the config of SerJ , is different than the one from Anta & 1usmus
Different order of tests, different testing time, different meaning of errors


----------



## mongoled

New 24/7 profile completed

Now to test tRP @12

















** EDIT **
No no no, lol

Straight away error 0, which means needs more voltage for minimal gains so drawing a line on this for the time being

🤣🤣


----------



## Audioboxer

Damn, 25 cycle was really unstable. Don't think it's temperature, even though I'm running my fans a bit slower to resemble real world use, 47 degrees as a peak shouldn't be tipping this I don't think. Over 50 is where it really gets bad usually for b-die. Though error 13 does infer it _could_ be overheating.


----------



## mongoled

Audioboxer said:


> Damn, 25 cycle was really unstable. Don't think it's temperature, even though I'm running my fans a bit slower to resemble real world use, 47 degrees as a peak shouldn't be tipping this I don't think. Over 50 is where it really gets bad usually for b-die. Though error 13 does infer it _could_ be overheating.


Up your vSOC, I would say thats too low for what you are attempting to run.

I am running 1.1375v for my sig settings ...

Oh and when you are going for baseline stop squeezing i.e. why do you have tRRDS and tRRDL set to the same value ? 

Leave some breathing room i.e. set tRRDL to 6


----------



## Audioboxer

mongoled said:


> Up your vSOC, I would say thats too low for what you are attempting to run.
> 
> I am running 1.1375v for my sig settings ...


Good shout, dom's VSOC was up at 1.156v. Back to 2T for today then tonight I will try a cooler run combined with a higher VSOC.

I guess I shouldn't be surprised 1T/1.5T requires more VSOC.

Also a good reminder for new visitors to the topic, 3 cycles is NOT stable


----------



## mongoled

Audioboxer said:


> Good shout, dom's VSOC was up at 1.156v. Back to 2T for today then tonight I will try a cooler run combined with a higher VSOC.
> 
> I guess I shouldn't be surprised 1T/1.5T requires more VSOC.


Forgot to say, although error 13 in the notes says "overheating" its not the only cause of triggering an error 13

I was getting error 13 on my watercooled dimms, then I found out what was triggering it in my case, basically as I was forcing tRFC lower and lower I did not raise tWR to 12 from 10 (tRTP is @6).

Basically I was not leaving enough time on the refresh for tWR to act and this was triggering errors 3, 4, 13 & 14.

Wasted alot of time and PC hours trying to get tRFC 228 stable and it was all because of one setting

😂 😂


----------



## Audioboxer

mongoled said:


> Forgot to say, although error 13 in the notes says "overheating" its not the only cause of triggering an error 13
> 
> I was getting error 13 on my watercooled dimms, then I found out what was triggering it in my case, basically as I was forcing tRFC lower and lower I did not raise tWR to 12 from 10 (tRTP is @6).
> 
> Basically I was not leaving enough time on the refresh for tWR to act and this was triggering errors 3, 4, 13 & 14.
> 
> Wasted alot of time and PC hours trying to get tRFC 228 stable and it was all because of one setting
> 
> 😂 😂


Interesting bit of timing theory for people to consider. I would say at this point with me running tWR 12 I will leave it be for now until I see how VSOC helps.

I do have a 2T profile with these settings with tWR at 10, but I am learning what you get away with at 2T may well not be exactly what you get away with at 1T/1.5T or as you've found out if you keep lowering tRFC!


----------



## Veii

Audioboxer said:


> Don't think it's temperature, even though I'm running my fans a bit slower to resemble real world use, 47 degrees as a peak shouldn't be tipping this I don't think. Over 50 is where it really gets bad usually for b-die.


B-die "starts" to get unstable at 42c on the common ~120ns tRFC
More tRFC , higher temp range.

After 42c only the possibility increases
But it depends on tRFC after all, and tRP 
If you run CKE and more RTT_WR (less park) higher voltage will not do anything ~ it won't result in more heat
(30c indoors example and 1.65v)


----------



## Audioboxer

And done. Versus this










I committed an act to be frowned upon which is changing multiple things at once. Thought process went, VSOC needs to go up as per advice, so it went up two notches. My VSOC seems to droop quite a bit on this board so like 1.15v really runs at 1.125v. With some errors on 6 I wondered if my RttNom wasn't helping. Correct me if I'm wrong, but I believe running RttNom 7 is "weaker" than RttNom 6 potentially putting less strain on the IMC. But of course it could mean running a weaker RttNom hurts stability. Given that I didn't play about with VSOC at AddrCmdSetup 56 previously, I actually set it from 55 back to 56.

But with what @Veii has said above I actually wonder if temp also helped










As you can see here these temps belong to the 25 cycle pass above. Max temp seen was 40.5 and average temp was 39. On the failed run temps managed to get to 46~47 peak.

The passed test has taken a minute longer but I'm not too concerned about that. Main clarification I guess I'm looking for just now is if RttNom passes at 7 is it beneficial to leave it there over 6 in terms of less strain on the IMC? 6/3/3 seems popular on DR, but I have seen a few 7/3/3s.


----------



## sonixmon

domdtxdissar said:


> I have spent quite some time (many hours) finding the settings which give me the highest scores in this benchmark.. Seems to scale mostly from 1.8vPLL but also vsoc + IOD and CCD voltages.
> 
> Benchmarks was done with 6 core "5600x" @ *static 4.5ghz* so numbers are comparable.
> 
> Baseline 1900fclk run with 1.8vPLL @ 1.8v and *throttling so all the runs are pretty close* = scores around 168gigaflops
> View attachment 2522464
> 
> 
> My highest scoring settings combo at 1900fclk = ~212 gigaflops average with peak at 248 gigaflops
> View attachment 2522470
> 
> 
> My highest scoring settings combo at 1933fclk = heavy throttling and whea errors
> View attachment 2522466
> 
> 
> My highest scoring settings combo at 1866fclk = decent scores for this speed i guess
> View attachment 2522467
> 
> 
> I was observing the same as you, each run the results for the GEMM test kept going up. And seemingly by the exact same amount also sometimes... Not sure this benchmark can be trusted
> 
> All testruns can be round here


Thanks for sharing your settings. With additional air cooling on ram I am able to match your settings @3800. I had already been running tfaw a little lower at 12 so I left it there. But other than that same and stable (2 hour test) which is fine for my purposes.


----------



## Audioboxer

Having a wee go at tRCDRD 14 again with timings above










No Christmas tree of errors on 6 within 20 seconds which is where I've found myself with 14 previously. But an error on 10 which is also something I've struggled with frequently.










Added 0.1v to VDIMM and it goes a tiny bit further, but then an "explosion" on 13 seems to suggest too much VDIMM or need higher RttNom. Issue with increasing RttNom to 6 seems to be it brings back crashes on 6 within 30 seconds.

This is my struggle with tRDCRD 14, seems no matter what I change in accordance to error messages if it either blows up earlier or gets me a tiny bit further forward and then its fresh error messages.

Not even entirely sure how 1.54v can be "too much voltage" for B-die? We're talking cooling meaning between 30~40 degrees even at that voltage.

I guess my question is if RttNom is to be stronger, which I assume is 6, what else might need to be changed so that a stronger RttNom doesn't cause issues itself?

Here is the RttNom on 6










1.53v had it crashing on 6, 1.54v has it going a few minutes and crashing on 13. But not the "explosion" of 13s like above, where it was 3 at once. Just one 

This is what drives me nuts, trying to figure out what to change, what not to change and if I do change something is there a secondary setting that might need changed I wasn't thinking about... Messages telling me to try lowering VDIMM at the same time as increasing RttNom, but then it appears increasing VDIMM _might_ help  










RttNom 5 with 1.55v.

I guess where I have a knowledge gap is could anyone explain the relationship between RttNom and VDIMM? A lot of the errors descriptions are mentioning VDIMM and RttNom at the same time. Either increase/decrease, or too much voltage/increase Nom strength. So I'm assuming there is quite a close link between the two?

I mean, "#10 at the very start = increase RTT_NOM to something stronger", I presume very start indicates within a minute or two? But with RttNom already at 5 it seems pretty strong?

*edit* - The tldr is probably those managing tRCDRD 14 at 3800 on 2x16GB what VDIMM are you having to run? I would expect 1.55~1.58v is probably quite common, but it's a challenge to see at times with those running 2x16GB in this topic often on Asus boards and VDIMM isn't auto showing on ZenTimings screenshots.


----------



## Thanh Nguyen

Anyone here can run 4000/2000 stable tm5?


----------



## mongoled

Audioboxer said:


> Having a wee go at tRCDRD 14 again with timings above
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> No Christmas tree of errors on 6 within 20 seconds which is where I've found myself with 14 previously. But an error on 10 which is also something I've struggled with frequently.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Added 0.1v to VDIMM and it goes a tiny bit further, but then an "explosion" on 13 seems to suggest too much VDIMM or need higher RttNom. Issue with increasing RttNom to 6 seems to be it brings back crashes on 6 within 30 seconds.
> 
> This is my struggle with tRDCRD 14, seems no matter what I change in accordance to error messages if it either blows up earlier or gets me a tiny bit further forward and then its fresh error messages.
> 
> Not even entirely sure how 1.54v can be "too much voltage" for B-die? We're talking cooling meaning between 30~40 degrees even at that voltage.
> 
> I guess my question is if RttNom is to be stronger, which I assume is 6, what else might need to be changed so that a stronger RttNom doesn't cause issues itself?
> 
> Here is the RttNom on 6
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 1.53v had it crashing on 6, 1.54v has it going a few minutes and crashing on 13. But not the "explosion" of 13s like above, where it was 3 at once. Just one
> 
> This is what drives me nuts, trying to figure out what to change, what not to change and if I do change something is there a secondary setting that might need changed I wasn't thinking about... Messages telling me to try lowering VDIMM at the same time as increasing RttNom, but then it appears increasing VDIMM _might_ help
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> RttNom 5 with 1.55v.
> 
> I guess where I have a knowledge gap is could anyone explain the relationship between RttNom and VDIMM? A lot of the errors descriptions are mentioning VDIMM and RttNom at the same time. Either increase/decrease, or too much voltage/increase Nom strength. So I'm assuming there is quite a close link between the two?
> 
> I mean, "#10 at the very start = increase RTT_NOM to something stronger", I presume very start indicates within a minute or two? But with RttNom already at 5 it seems pretty strong?
> 
> *edit* - The tldr is probably those managing tRCDRD 14 at 3800 on 2x16GB what VDIMM are you having to run? I would expect 1.55~1.58v is probably quite common, but it's a challenge to see at times with those running 2x16GB in this topic often on Asus boards and VDIMM isn't auto showing on ZenTimings screenshots.


Also as you push vDIMM, lower RttPark to 5 or 6 and test


----------



## Audioboxer

mongoled said:


> Also as you push vDIMM, lower RttPark to 5 or 6 and test


Thanks, I never thought about lowering RttPark further. Will give it a go.

Still interested if anyone is reading to know what VDIMM some of you needed for tRCDRD 14 at 3800. I think 1.55~1.58v should be in the ballpark for most people?


----------



## KedarWolf

Here is me at 1usmus_v3 at 1000%, 8 cycles. I attached my .cfg, just rename it, remove the .txt to use it.


----------



## Thanh Nguyen

What can I do to make a latency lower?


----------



## Audioboxer

Thanh Nguyen said:


> What can I do to make a latency lower?
> View attachment 2522691


Are you just trying to bench a number or are you trying to run this as your daily system? If daily/main PC, do this first










Set up an event viewer custom list to check for WHEA errors.

If you ask me above 1900 FCLK there is no point in trying to run anything as a daily PC if you're getting WHEA errors. It's IF instability, whether it boots, benches or even plays games or not.

No WHEA at 2000 would mean a hell of a golden CPU, in which case the first thing to do is not be using GDM mode. Test with GDM disabled and 2T, then move onto 1T.

If you're not wanting to look at any of the above, I guess you could try your SCLs on 3 or 2 instead of 4. When it comes to memory though most of the pro's in this topic aren't offering any advice unless GDM is disabled


----------



## nibroc313

Am I doing everything right? I feel very paranoid that something is going wrong. VDDG CCD = 1.0v in bios, VDDG IOD = 1.05v in bios, CLDO VDDP = .900v in bios, and VDIMM = 1.52v. I also do not know what to set my LLC settings to.


----------



## Veii

Audioboxer said:


> Messages telling me to try lowering VDIMM at the same time as increasing RttNom, but then it appears increasing VDIMM _might_ help


The opposite 
NOM is CKE high
NOM needs to increase if VDIMM increases or generally signal strength increases
I can see (theory) that stronger tCKE also would require more NOM - but only a theory so far

PARK is CKE low - floor
Too tight CKE low, will shrink the gate
A smaller gate, on a never ending sinus curve ~ increases it's strengthness, increases it's speed , increases strain on the PCB
Small tube fluid flow, vs wide tube fluid flow. Wide = less ohm

Too tight NOM will result in the CKE signal to reflect back , or at best just drop faster than it can reflect upwards back
Too low NOM will result CKE signal overshooting beyond the ceiling and never falling down

In general, NOM depends on PARK ~ they both have to work together (you can not see data-eye sadly, unless somebody figures out where ABL stores the debug/training file ~ location)
PARK & NOM depend on WR. WR has the highest priority - and WR can "adapt" for the lack of NOM ~ if needed
On low clean but thin voltage, there is no need to use either WR nor NOM. Boards have a preconfigured ceiling and floor. Even if you "disable" it. Traces have adapted for it. Soo for the 1.2-1.3v region

Using NOM in general should be required after 1.46v (realistically) but after 1.48v (common knowledge)
More VDIMM = more NOM
Too much NOM = needs adjustment on PARK (stronger park), else fall time & raise time will differ ~ balance thing 

Generally, start with the least amount of PARK you can get away with.
And with the highest amount of WR you can get away with
if NOM needs to be set or not - depends on many factors, so also the MB PCB

Repeating so it's remembered,
~ WR changes NOM & PARK behavior. A2 can run WR /2 , but fail faster on higher MCLK
(NOM */6* = 40 , WR */3* = 80, PARK* /3* = 80 ... *≠* .... NOM */6* = 40, WR */2* = 120 , PARK */3* = 80) ~ it's rather closer to (NOM */7* = 34.3, WR */2* = 120 , PARK */5* = 48)
It's better taming high voltage (1.62+) on low freq, but too much WR will cause issues in achieving higher MT/s.
Might still be an option for only 3800MT/s guys
But again, RTT_WR changes NOM & PARK scaling. Their requirements change upon RTT_WR change

EDIT:
Another sidenote, MEM-IC's same as VRAM-IC's have a +/- voltage scaling for their set clock
You can overpower and underpower lower frequency sets too. Just so it's remembered when pushing 13-13 or 12-12 on low MCLK
* also another reason why more RTT_WR can be useful for certain applications


----------



## MrHoof

So I had the chance to try out a 3200 cl14 kit today and compare it to my daily setup with a 3600 cl 17 kit.
I tried my current timings wich just resulted in a rainbow of erros but even at a flat cl 15, I couldnt get it stable it would alway error with error 8 everytime
Ended up with a 16-12-16-16-28-44 276 @1.46 volts wich I confirmend with 10 cycles so far. Gonna test it with a difrrent 3600x/x470 crosshair vII tomorrow to 25 cycle but at 3733mhz 2t since the 3600x refuse to boot at 1900fclk and 1t is not stable either .

Did a 25 cycle 16-16-16-32-50-300 @1.42v cause I just wanted to make sure it will work since I couldnt get cl15 stable at all.









But it did run 1T without problem aswell ony my CPU/Motherboard combo, so I would say the kit itself does not matter much.

edit: also I couldnt see any diffrence between 0/0/5 and 6/3/7 RTT in temps or stablilty, still confused about those.


----------



## Audioboxer

Veii said:


> The opposite
> NOM is CKE high
> NOM needs to increase if VDIMM increases or generally signal strength increases
> I can see (theory) that stronger tCKE also would require more NOM - but only a theory so far
> 
> PARK is CKE low - floor
> Too tight CKE low, will shrink the gate
> A smaller gate, on a never ending sinus curve ~ increases it's strengthness, increases it's speed , increases strain on the PCB
> Small tube fluid flow, vs wide tube fluid flow. Wide = less ohm
> 
> Too tight NOM will result in the CKE signal to reflect back , or at best just drop faster than it can reflect upwards back
> Too low NOM will result CKE signal overshooting beyond the ceiling and never falling down
> 
> In general, NOM depends on PARK ~ they both have to work together (you can not see data-eye sadly, unless somebody figures out where ABL stores the debug/training file ~ location)
> PARK & NOM depend on WR. WR has the highest priority - and WR can "adapt" for the lack of NOM ~ if needed
> On low clean but thin voltage, there is no need to use either WR nor NOM. Boards have a preconfigured ceiling and floor. Even if you "disable" it. Traces have adapted for it. Soo for the 1.2-1.3v region
> 
> Using NOM in general should be required after 1.46v (realistically) but after 1.48v (common knowledge)
> More VDIMM = more NOM
> Too much NOM = needs adjustment on PARK (stronger park), else fall time & raise time will differ ~ balance thing
> 
> Generally, start with the least amount of PARK you can get away with.
> And with the highest amount of WR you can get away with
> if NOM needs to be set or not - depends on many factors, so also the MB PCB
> 
> Repeating so it's remembered,
> ~ WR changes NOM & PARK behavior. A2 can run WR /2 , but fail faster on higher MCLK
> (NOM */6* = 40 , WR */3* = 80, PARK* /3* = 80 ... *≠* .... NOM */6* = 40, WR */2* = 120 , PARK */3* = 80) ~ it's rather closer to (NOM */7* = 34.3, WR */2* = 120 , PARK */5* = 48)
> It's better taming high voltage (1.62+) on low freq, but too much WR will cause issues in achieving higher MT/s.
> Might still be an option for only 3800MT/s guys
> But again, RTT_WR changes NOM & PARK scaling. Their requirements change upon RTT_WR change
> 
> EDIT:
> Another sidenote, MEM-IC's same as VRAM-IC's have a +/- voltage scaling for their set clock
> You can overpower and underpower lower frequency sets too. Just so it's remembered when pushing 13-13 or 12-12 on low MCLK
> * also another reason why more RTT_WR can be useful for certain applications


Ahhhh, thanks soo much for taking the time to type that up. It also makes sense for me now why on XMP on kits rated 1.45v and below, which is most of them, the disabled/3/1 tends to be the default for DR. Also makes sense to me now why everyone was encouraging me to get away from nom disabled when I was starting to go above 1.45v.

On the park side of things @mongoled earlier had recommended I try rttpark 4~6 and funnily enough going to 6 caused my first non-post I've seen on this RAM. But 4-5 booted OK (no real stability testing done). Was still an interesting detour for me but until your post I was kind of "just trying it" without much understanding for why. 

It truly is a balancing act and it definitely helps if you somewhat understand what on earth you're trying to balance


----------



## Blameless

XPEHOPE3 said:


> 45°C for all B-dies as per specs.


45C is the JEDEC reduced temperature range for most DRAM. This specification is only meaningful, in and of itself, if ASR is enabled and there was a memory temperature sensor that could allow the use of the reduced refresh frequency, which would help performance at or below 45C (because tREFI would double).

It may be a good ballpark figure to target, but the correlation with the reduced self refresh spec is coincidental, in this context.



Sleepycat said:


> So 45 ºC is possible.


Depending on ambients, it might even be easy. However, the temperature that one requires to be stable will vary with one's samples and settings.


----------



## tolis626

Well, after trying a myriad of different things, I failed at getting 3800MHz stable with tight timings. I got tired of testing and failing for now. I'm sticking with my tested and stable 3600MHz 14-15-14-30-44 1T at 1.45V. Coincidentally, as I was wondering if it's a temperature issue, it's not. The settings I just posted were at an almost constant 52C during testing and they never even flinched. No errors, no WHEA, no instability, nada. I will inevitably feel mazochistic again soon, so I will be back testing stuff, but my last hope is that it has to do with these NOM/PARK/whatever settings that I have no clue about, so I will be studying the excellent post by @Veii and trying again when I feel like it. If anyone has something to suggest that may help my situation, you are more than welcome to do so. Thanks for all the help and the treasure trove of information boys!

EDIT : I felt the need to punish myself after overeating for dinner, so here I go again. If this fails badly I'm taking a break. BUT! It seems to be working for now, or at least it looks like I'm taking steps in the right direction. I kind of cheated and copied (and modified) some of the settings used by @KedarWolf, as he's using a similar kit to mine (probably everything same, except it's dual rank so it's 2x16GB instead of my measly 2x8GB). So far it's been going for just over an hour without fail. It's sitting at a constant 54/53C (DIMM 1/DIMM 2) at 1.51V (set in BIOS, 1.504V read by HWiNFO64). The culprits may have been either tRCDRD or tCKE, both have been raised. Maybe someone could take a peek and see if I'm doing anything massively wrong or that I'm an idiot. If it works, though, I'll be a happy idiot! 

( PS : Ignore the really high CPU temps, I am playing around with PBO/CO to get the max out of this puppy, but it's getting toasty running Cinebench R20 at 200W PPT)


----------



## Audioboxer

Audioboxer said:


> And done. Versus this
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I committed an act to be frowned upon which is changing multiple things at once. Thought process went, VSOC needs to go up as per advice, so it went up two notches. My VSOC seems to droop quite a bit on this board so like 1.15v really runs at 1.125v. With some errors on 6 I wondered if my RttNom wasn't helping. Correct me if I'm wrong, but I believe running RttNom 7 is "weaker" than RttNom 6 potentially putting less strain on the IMC. But of course it could mean running a weaker RttNom hurts stability. Given that I didn't play about with VSOC at AddrCmdSetup 56 previously, I actually set it from 55 back to 56.
> 
> But with what @Veii has said above I actually wonder if temp also helped
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> As you can see here these temps belong to the 25 cycle pass above. Max temp seen was 40.5 and average temp was 39. On the failed run temps managed to get to 46~47 peak.
> 
> The passed test has taken a minute longer but I'm not too concerned about that. Main clarification I guess I'm looking for just now is if RttNom passes at 7 is it beneficial to leave it there over 6 in terms of less strain on the IMC? 6/3/3 seems popular on DR, but I have seen a few 7/3/3s.


Hmmm










Wanted to try a flat 15 with this profile so I have my 14/15 profiles up to date. Only change made was to tRAS/tRC, outside of changing to 15-15-15-15.

My fan curve however was back on the daily curve rather than ramped up for testing, so peaks of 48 degrees. Makes it look like temps are what caused this like with the 14 profile when it had 8 errors but passed after a VSOC bump and lower temps. If so as Veii pointed out to me shows how temp sensitive b-die _could_ become after like 42 degrees if your timings are proper tight.

Unless anyone can see any other reason why the 14 profile would pass but not 15?

On a related note here is the "downside" to a 2 DIMM board, your ram sticks are very close to each other so ramp up temps a bit easier than a 4 DIMM with some spacing between 2 sticks  I guess if you have RGB ram it might add another degree or so into the mix as well.

*edit* - Probably is just temps again, keeping it down at around 40~42 and we're going good so far










I did drop VDIMM a bit as well but that'll be fine on flat 15s down to the point where it conflicts with tRFC being low.


----------



## PJVol

Thanh Nguyen said:


> Anyone here can run 4000/2000 stable tm5?


It's not that unusual to do so. The question is, does it really make sense for 24/7?
The vast majority of "vermeers" faces kinda hardware limitation of data fabric, when running above 1900mhz. I think IF PHY's just cannot function reliably enough, without pushing some internal voltages close to their safe limits.
Surely, the silicon quality and/or mb's power circuits design could factor in, as well.
But even then, hardly one may consider such an operating mode as reliable, let alone talking of diminishing returns.
For example, I can pass all stability tests with 2000/4000 and even 2033/4066, and most benches do show positive scaling, compared to 1900/3800 setup, but some don't, actually showing the opposite, i.e. negative scaling with IF 1900+.


----------



## kot0005

Is anyone able to run their 5900x at 1900Fclk ?

Vddsoc 1.145v
Dramvoltage 1.46v
Vddg ccd 0.950v
Vddg iod 1.02v
Vddp .95v
Llc lv 3

3800 16T

I keep getting interconnect whea errors above 1800fclk, no matter how many volts i pump into soc, i tried from 1.09 to 1.145, dont rrally wana go higher.

Lower voltage causes like 10 whea errors with cpu z bench, highest causes like 1 or 2 errors with cpu z test

Is my memory controller just bad ? 

My cpu overclocks decently tho.


----------



## Nizzen

kot0005 said:


> Is anyone able to run their 5900x at 1900Fclk ?
> 
> Vddsoc 1.145v
> Dramvoltage 1.46v
> Vddg ccd 0.950v
> Vddg iod 1.02v
> Vddp .95v
> Llc lv 3
> 
> 3800 16T
> 
> I keep getting interconnect whea errors above 1800fclk, no matter how many volts i pump into soc, i tried from 1.09 to 1.145, dont rrally wana go higher.
> 
> Lower voltage causes like 10 whea errors with cpu z bench, highest causes like 1 or 2 errors with cpu z test
> 
> Is my memory controller just bad ?
> 
> My cpu overclocks decently tho.


My old 5900x couldn't do 3733mhz stable, no matter what. My 5950x can do 3866 easy. Memory controller lottery


----------



## Audioboxer

Audioboxer said:


> Hmmm
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Wanted to try a flat 15 with this profile so I have my 14/15 profiles up to date. Only change made was to tRAS/tRC, outside of changing to 15-15-15-15.
> 
> My fan curve however was back on the daily curve rather than ramped up for testing, so peaks of 48 degrees. Makes it look like temps are what caused this like with the 14 profile when it had 8 errors but passed after a VSOC bump and lower temps. If so as Veii pointed out to me shows how temp sensitive b-die _could_ become after like 42 degrees if your timings are proper tight.
> 
> Unless anyone can see any other reason why the 14 profile would pass but not 15?
> 
> On a related note here is the "downside" to a 2 DIMM board, your ram sticks are very close to each other so ramp up temps a bit easier than a 4 DIMM with some spacing between 2 sticks  I guess if you have RGB ram it might add another degree or so into the mix as well.
> 
> *edit* - Probably is just temps again, keeping it down at around 40~42 and we're going good so far
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I did drop VDIMM a bit as well but that'll be fine on flat 15s down to the point where it conflicts with tRFC being low.


Answered my own questions










I've seen a few people across the web say things like "just keep it below 50 degrees" which is partly where I picked up that flawed advice. As Veii pointed out around 42 and above is clearly where issues with tight tRFC can arise.

I had errors on 0, 8 and 12 just because temps managed to peak at 48. Earlier on it was temps at 47. Now with temps peaking at 41, no errors.

Good visual reminder for anyone temps as high as 46~48 can begin to bring in the errors in TM5.


----------



## KedarWolf

I think this is my best ever Sandra.

I tried 14-16-8-14-21 2T.



Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 181.43GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.9ns (9.6ns - 59.8ns)
Inter-Thread (same Core) Latency : 9.8ns
Inter-Core (same Module) Latency : 20.8ns
Inter-Module (same Package) Latency : 58.4ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.67GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1769.41MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.80ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 38.31MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.4ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 21.7ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.6ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 21.8ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.0ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 21.3ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 58.0ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 57.7ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 57.9ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 56.9ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.7ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.9ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.3ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.5ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.7ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.8ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 21.8ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.0ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 21.3ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.3ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 58.0ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 57.7ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 57.9ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.0ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.6ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.9ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.4ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.5ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 20.6ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.2ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 21.0ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.5ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.3ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.3ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 57.9ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.8ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 58.1ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.6ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 59.0ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 58.1ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.9ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.5ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.5ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.9ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 20.6ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 20.2ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.0ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.5ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.3ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.3ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 57.9ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 57.8ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.1ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.3ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 59.0ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 57.9ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.9ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.3ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.9ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 23.0ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 22.4ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 21.2ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 58.1ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.1ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 58.8ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.8ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.2ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.6ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.8ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.7ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 21.6ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.7ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.9ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.8ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.3ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.8ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 20.8ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 20.6ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 57.3ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 57.8ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 57.1ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 58.5ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 58.2ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.9ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 58.3ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.7ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.5ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 23.0ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.3ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 22.3ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.2ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 58.4ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 57.8ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.6ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.4ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 59.1ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 59.0ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 59.1ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 20.7ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 21.8ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.8ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.5ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 23.0ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 21.3ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 22.4ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.2ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 58.3ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.7ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.7ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.4ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 59.2ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 59.0ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 59.1ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.1ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 21.3ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 20.8ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.9ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 57.3ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.1ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.2ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 59.1ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.5ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.9ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 19.0ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.6ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.1ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.6ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.0ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 21.3ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 20.8ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.5ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.9ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.3ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.1ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.2ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 59.0ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.4ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 59.0ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.5ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 22.4ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.1ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.1ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.0ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 59.1ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.8ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 59.5ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.0ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 59.1ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.8ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 22.0ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.6ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 23.1ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.8ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.5ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 22.4ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.1ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 58.2ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.0ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 59.0ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.8ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 59.4ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.9ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 59.3ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 21.6ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.2ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.5ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 57.9ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 59.1ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 58.7ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.8ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.4ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.8ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 20.2ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.4ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 20.8ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 21.1ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.6ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.7ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.2ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.7ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.1ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 59.0ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 58.7ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.6ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.3ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.6ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.3ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.2ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.1ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.6ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.0ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 59.4ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.2ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.3ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.4ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 21.5ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.0ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 22.5ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.0ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 22.5ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.6ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.3ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.1ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.1ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.6ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 58.9ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 59.4ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.3ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.3ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.6ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 19.0ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 20.9ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 19.6ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 21.1ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 20.2ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.4ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.2ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 57.8ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.1ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 58.4ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.6ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.5ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.1ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.4ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.6ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 19.0ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 20.5ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 19.6ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 21.1ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 20.2ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.9ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 21.5ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.6ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 22.2ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.2ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 21.8ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.3ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 58.1ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 57.7ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 58.3ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.6ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 58.4ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.2ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.4ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.6ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 18.9ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 21.5ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.6ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 22.2ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.2ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 21.6ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.5ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 20.2ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.6ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 20.6ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.5ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.2ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.7ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.2ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 58.1ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.5ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.3ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 57.9ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.0ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 19.2ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 20.2ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.6ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 20.6ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.4ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.5ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 22.7ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 20.9ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.9ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.6ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 58.3ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 58.0ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 58.8ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.2ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 58.7ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.8ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.9ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 20.4ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 21.4ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.5ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.7ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.4ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 22.7ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 20.9ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 22.0ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.3ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 21.6ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.2ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.9ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.8ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 57.8ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.8ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.2ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 59.3ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 58.7ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.1ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 19.6ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.8ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 23.0ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.8ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.4ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 23.0ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 22.1ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 20.2ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 20.4ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 58.2ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.5ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.7ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 59.0ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.8ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.5ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.8ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.9ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.2ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.5ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.6ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.2ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 20.2ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 20.4ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 20.9ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 59.0ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 59.2ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 59.5ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.6ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 59.1ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.9ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.6ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.5ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.3ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.4ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.3ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 22.1ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.6ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.7ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 20.9ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.6ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.7ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 59.3ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 59.1ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 59.0ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 59.3ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.8ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.7ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.4ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.4ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.9ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.5ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.9ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 20.4ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 20.9ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 20.2ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 21.7ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 20.8ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 21.6ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.0ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.4ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.3ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 58.7ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 58.0ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 58.8ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.8ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 59.0ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 58.4ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.9ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.8ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.6ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 21.2ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 21.2ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.5ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.3ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.3ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 58.2ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 58.4ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.7ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 58.5ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 59.2ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.6ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 59.1ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.6ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 20.7ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 23.1ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.4ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.6ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.3ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 59.4ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.8ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 59.4ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 58.9ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 59.7ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 59.2ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 59.8ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 59.3ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.7ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.9ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.5ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.7ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.3ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.8ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 58.3ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 58.6ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.6ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.3ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.6ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.2ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 21.0ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.7ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.7ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 59.1ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 58.8ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 59.3ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 58.6ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 59.8ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 59.4ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 59.4ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 59.3ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 20.1ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.8ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.6ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.6ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.9ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 58.3ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.9ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.9ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.6ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.1ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 21.9ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.2ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.8ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.0ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.5ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 58.8ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.0ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.6ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.5ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.6ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.3ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 59.0ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.3ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.4ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.5ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.3ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 58.8ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 20.3ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 21.5ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 20.6ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 22.3ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.3ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 20.7ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 18.9ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 20.5ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.7ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 21.2ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.3ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.2ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 20.4ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 23.0ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.3ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.4ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.0ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.7ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 20.5ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.1ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 20.3ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.4ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 22.1ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 20.2ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 20.4ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 20.9ns
1x 64bytes Blocks Bandwidth : 26GB/s
4x 64bytes Blocks Bandwidth : 28.58GB/s
4x 256bytes Blocks Bandwidth : 104.42GB/s
4x 1kB Blocks Bandwidth : 331.12GB/s
4x 4kB Blocks Bandwidth : 516.4GB/s
16x 4kB Blocks Bandwidth : 729.87GB/s
4x 64kB Blocks Bandwidth : 999GB/s
16x 64kB Blocks Bandwidth : 612GB/s
8x 256kB Blocks Bandwidth : 611.36GB/s
4x 1MB Blocks Bandwidth : 609.24GB/s
16x 1MB Blocks Bandwidth : 29.89GB/s
8x 4MB Blocks Bandwidth : 19.29GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.85GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1009
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 4.85GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.85GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1009
Latest Version : A20F10-16
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 229 : CPU microcode update available. Check for an updated System BIOS with updated microcode.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## Alpharevx

Hello @Veii
So i managed to get RTT 6/3/3 GDM OFF 2T stable by increasing ClkDrvStr to 60ohm and CsOdtDrv to 30ohm, before i was using RTT 7/3/1 with 24/20/24/24
Now CLDO_VDDP 0.9v, CCD 0.95 , IOD 1.0v VDIMM 1.40v
I got 4x8gb Micron Rev.E Corsair Vengeance RGB PRO C18

Are these settings ok for this setup? anything i can improve? thank you.


----------



## sonixmon

Veii said:


> The opposite
> NOM is CKE high
> NOM needs to increase if VDIMM increases or generally signal strength increases
> I can see (theory) that stronger tCKE also would require more NOM - but only a theory so far
> 
> PARK is CKE low - floor
> Too tight CKE low, will shrink the gate
> A smaller gate, on a never ending sinus curve ~ increases it's strengthness, increases it's speed , increases strain on the PCB
> Small tube fluid flow, vs wide tube fluid flow. Wide = less ohm
> 
> Too tight NOM will result in the CKE signal to reflect back , or at best just drop faster than it can reflect upwards back
> Too low NOM will result CKE signal overshooting beyond the ceiling and never falling down
> 
> In general, NOM depends on PARK ~ they both have to work together (you can not see data-eye sadly, unless somebody figures out where ABL stores the debug/training file ~ location)
> PARK & NOM depend on WR. WR has the highest priority - and WR can "adapt" for the lack of NOM ~ if needed
> On low clean but thin voltage, there is no need to use either WR nor NOM. Boards have a preconfigured ceiling and floor. Even if you "disable" it. Traces have adapted for it. Soo for the 1.2-1.3v region
> 
> Using NOM in general should be required after 1.46v (realistically) but after 1.48v (common knowledge)
> More VDIMM = more NOM
> Too much NOM = needs adjustment on PARK (stronger park), else fall time & raise time will differ ~ balance thing
> 
> Generally, start with the least amount of PARK you can get away with.
> And with the highest amount of WR you can get away with
> if NOM needs to be set or not - depends on many factors, so also the MB PCB
> 
> Repeating so it's remembered,
> ~ WR changes NOM & PARK behavior. A2 can run WR /2 , but fail faster on higher MCLK
> (NOM */6* = 40 , WR */3* = 80, PARK* /3* = 80 ... *≠* .... NOM */6* = 40, WR */2* = 120 , PARK */3* = 80) ~ it's rather closer to (NOM */7* = 34.3, WR */2* = 120 , PARK */5* = 48)
> It's better taming high voltage (1.62+) on low freq, but too much WR will cause issues in achieving higher MT/s.
> Might still be an option for only 3800MT/s guys
> But again, RTT_WR changes NOM & PARK scaling. Their requirements change upon RTT_WR change
> 
> EDIT:
> Another sidenote, MEM-IC's same as VRAM-IC's have a +/- voltage scaling for their set clock
> You can overpower and underpower lower frequency sets too. Just so it's remembered when pushing 13-13 or 12-12 on low MCLK
> * also another reason why more RTT_WR can be useful for certain applications


This is extremely helpful thank you very much! Not understanding what all the values mean is one thing, knowing how they interact is half the battle. Hoping this helps with my very close to full stable OC.


----------



## GRABibus

Hi,
I finally could boot with GDM off with following settings:









ASUS ROG X570 Crosshair VIII Overclocking &amp...


Good stuff! :) Regarding RAM temperature, I was similarly confused by peoples low temperatures when I was looking into the subject myself. My modules don't have built in temp sensors, but did have nice black heatspreaders and I have an IR thermometer. Mine were getting upto nearly 60°C at 1.4v...




www.overclock.net





these settings are fully stable with GDM enabled, but crashes in a minute on karhu’s ram test or aida64 cache stress test with GDM off.

what do you advise me to change on timings settings to be stable ?

thanks.


----------



## Audioboxer

GRABibus said:


> Hi,
> I finally could boot with GDM off with following settings:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ASUS ROG X570 Crosshair VIII Overclocking &amp...
> 
> 
> Good stuff! :) Regarding RAM temperature, I was similarly confused by peoples low temperatures when I was looking into the subject myself. My modules don't have built in temp sensors, but did have nice black heatspreaders and I have an IR thermometer. Mine were getting upto nearly 60°C at 1.4v...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> these settings are fully stable with GDM enabled, but crashes in a minute on karhu’s ram test or aida64 cache stress test with GDM off.
> 
> what do you advise me to change on timings settings to be stable ?
> 
> thanks.


Work on a stable 2T profile first with GDM off before going to 1T.

On a quick glance, booting tRCDRD 13 and benching is one thing, having it stable is another. Many of us with well binned ram struggle for 14 stable at 3800 let alone 13. I'd ease off on it to 14/15 for now.

Other than that look at some of my settings above for DR 2x16 or some other posters. Your VSOC is low for GDM off 1T, mine had to increase compared to 2T. Not sure what your VDIMM is, but I'm guessing 1.5v+ in which case resistances and Rtt comes into play. Again, as you can see above I'm running 7/3/3 and 40/20/30/20. 6/3/3 is also common.

Basically all these steps usually needed to try 1T and get it stable come on the back of getting 2T stable first. Unless you are lucky to plug and play someone else's settings from the get go.

I can boot into Windows and even run benches on quite a lot of timings, including flat 14s at 3800, but booting up that TM5 and getting it to run 25 cycles is a whole different ballgame for 1T or running tRCDRD at 14 or below at 3800.

I actually don't know if I've ever seen someone run tRCDRD at 13 stable at 3800. I'm guessing someone with golden RAM and a lot of voltage will have, but damn, it is not common.


----------



## XPEHOPE3

Blameless said:


> 45C is the JEDEC reduced temperature range for most DRAM. This specification is only meaningful, in and of itself, if ASR is enabled and there was a memory temperature sensor that could allow the use of the reduced refresh frequency, which would help performance at or below 45C (because tREFI would double).
> 
> It may be a good ballpark figure to target, but the correlation with the reduced self refresh spec is coincidental, in this context.


You are right! I've read Micron's document as well but previously didn't see it mentioning 45°C threshold and thought that was manufacturer-specific.


----------



## umea

Well time to catch up on the thread and start the journey to pure 1T again...








These have remained my settings for a while, stable at 14/14/15/14 as well but didn't care enough.
Going to aim for stable 2T 3800 14 14 14 14 first.... hell begins...


----------



## Veii

Yours truly, the meme








Just as you praise it that it can not fail, as thermal equilibrium 45-50min passed
~ literally within one minute 😣

Likely CAD_BUS or powersuply got warmer.
====================================
Makes me wonder if our minimum testing schedule has to increase to 25 loops
Normally #15 is what fails after 19th cycle, lol

I think i got the trick on SCLs to push bandwidth


Spoiler: But yet unstable


----------



## KedarWolf

KedarWolf said:


> I think this is my best ever Sandra.
> 
> I tried 14-16-8-14-21 2T.
> 
> 
> 
> Code:
> 
> 
> SiSoftware Sandra
> 
> Benchmark Results
> Aggregate Inter-Thread Bandwidth : 181.43GB/s
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Benchmark Results
> Average Inter-Thread Latency : 39.9ns (9.6ns - 59.8ns)
> Inter-Thread (same Core) Latency : 9.8ns
> Inter-Core (same Module) Latency : 20.8ns
> Inter-Module (same Package) Latency : 58.4ns
> Results Interpretation : Lower Scores mean Better Performance.
> Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.
> 
> Performance per Thread
> Aggregate Inter-Thread Bandwidth : 5.67GB/s
> No. Threads : 32
> Results Interpretation : Higher Scores mean Better Performance.
> Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.
> 
> Performance vs. Power
> Processor(s) Power : 105.00W
> Aggregate Inter-Thread Bandwidth : 1769.41MB/s/W
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 3.80ns/W
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Capacity vs. Power
> Total Cache Size : 707.05kB/W
> Results Interpretation : Higher Scores mean Better Performance.
> 
> Performance vs. Speed
> Aggregate Inter-Thread Bandwidth : 38.31MB/s/MHz
> Results Interpretation : Higher Scores mean Better Performance.
> Average Inter-Thread Latency : 0.08ns/MHz
> Results Interpretation : Lower Scores mean Better Performance.
> 
> Detailed Results
> Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
> U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.4ns
> U0-M0C0T0 <> U4-M0C2T0 Data Latency : 21.7ns
> U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.6ns
> U0-M0C0T0 <> U8-M0C4T0 Data Latency : 21.8ns
> U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.0ns
> U0-M0C0T0 <> U12-M0C6T0 Data Latency : 21.3ns
> U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
> U0-M0C0T0 <> U16-M1C0T0 Data Latency : 58.0ns
> U0-M0C0T0 <> U18-M1C1T0 Data Latency : 57.7ns
> U0-M0C0T0 <> U20-M1C2T0 Data Latency : 57.9ns
> U0-M0C0T0 <> U22-M1C3T0 Data Latency : 56.9ns
> U0-M0C0T0 <> U24-M1C4T0 Data Latency : 58.7ns
> U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.9ns
> U0-M0C0T0 <> U28-M1C6T0 Data Latency : 58.3ns
> U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.5ns
> U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
> U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.5ns
> U0-M0C0T0 <> U5-M0C2T1 Data Latency : 21.7ns
> U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.8ns
> U0-M0C0T0 <> U9-M0C4T1 Data Latency : 21.8ns
> U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.0ns
> U0-M0C0T0 <> U13-M0C6T1 Data Latency : 21.3ns
> U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.3ns
> U0-M0C0T0 <> U17-M1C0T1 Data Latency : 58.0ns
> U0-M0C0T0 <> U19-M1C1T1 Data Latency : 57.7ns
> U0-M0C0T0 <> U21-M1C2T1 Data Latency : 57.9ns
> U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.0ns
> U0-M0C0T0 <> U25-M1C4T1 Data Latency : 58.6ns
> U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.9ns
> U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.4ns
> U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.5ns
> U2-M0C1T0 <> U4-M0C2T0 Data Latency : 20.6ns
> U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.2ns
> U2-M0C1T0 <> U8-M0C4T0 Data Latency : 21.0ns
> U2-M0C1T0 <> U10-M0C5T0 Data Latency : 20.5ns
> U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.3ns
> U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.3ns
> U2-M0C1T0 <> U16-M1C0T0 Data Latency : 57.9ns
> U2-M0C1T0 <> U18-M1C1T0 Data Latency : 57.8ns
> U2-M0C1T0 <> U20-M1C2T0 Data Latency : 58.1ns
> U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.6ns
> U2-M0C1T0 <> U24-M1C4T0 Data Latency : 59.0ns
> U2-M0C1T0 <> U26-M1C5T0 Data Latency : 58.1ns
> U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.9ns
> U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.5ns
> U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.5ns
> U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.9ns
> U2-M0C1T0 <> U5-M0C2T1 Data Latency : 20.6ns
> U2-M0C1T0 <> U7-M0C3T1 Data Latency : 20.2ns
> U2-M0C1T0 <> U9-M0C4T1 Data Latency : 21.0ns
> U2-M0C1T0 <> U11-M0C5T1 Data Latency : 20.5ns
> U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.3ns
> U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.3ns
> U2-M0C1T0 <> U17-M1C0T1 Data Latency : 57.9ns
> U2-M0C1T0 <> U19-M1C1T1 Data Latency : 57.8ns
> U2-M0C1T0 <> U21-M1C2T1 Data Latency : 58.1ns
> U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.3ns
> U2-M0C1T0 <> U25-M1C4T1 Data Latency : 59.0ns
> U2-M0C1T0 <> U27-M1C5T1 Data Latency : 57.9ns
> U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.9ns
> U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.3ns
> U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.9ns
> U4-M0C2T0 <> U8-M0C4T0 Data Latency : 23.0ns
> U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.5ns
> U4-M0C2T0 <> U12-M0C6T0 Data Latency : 22.4ns
> U4-M0C2T0 <> U14-M0C7T0 Data Latency : 21.2ns
> U4-M0C2T0 <> U16-M1C0T0 Data Latency : 58.1ns
> U4-M0C2T0 <> U18-M1C1T0 Data Latency : 58.1ns
> U4-M0C2T0 <> U20-M1C2T0 Data Latency : 58.8ns
> U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.8ns
> U4-M0C2T0 <> U24-M1C4T0 Data Latency : 59.2ns
> U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.6ns
> U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.8ns
> U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.7ns
> U4-M0C2T0 <> U1-M0C0T1 Data Latency : 21.6ns
> U4-M0C2T0 <> U3-M0C1T1 Data Latency : 20.7ns
> U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.9ns
> U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.8ns
> U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.3ns
> U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.8ns
> U4-M0C2T0 <> U13-M0C6T1 Data Latency : 20.8ns
> U4-M0C2T0 <> U15-M0C7T1 Data Latency : 20.6ns
> U4-M0C2T0 <> U17-M1C0T1 Data Latency : 57.3ns
> U4-M0C2T0 <> U19-M1C1T1 Data Latency : 57.8ns
> U4-M0C2T0 <> U21-M1C2T1 Data Latency : 57.1ns
> U4-M0C2T0 <> U23-M1C3T1 Data Latency : 58.5ns
> U4-M0C2T0 <> U25-M1C4T1 Data Latency : 58.2ns
> U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.9ns
> U4-M0C2T0 <> U29-M1C6T1 Data Latency : 58.3ns
> U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.7ns
> U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.5ns
> U6-M0C3T0 <> U10-M0C5T0 Data Latency : 23.0ns
> U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.3ns
> U6-M0C3T0 <> U14-M0C7T0 Data Latency : 22.3ns
> U6-M0C3T0 <> U16-M1C0T0 Data Latency : 58.2ns
> U6-M0C3T0 <> U18-M1C1T0 Data Latency : 58.4ns
> U6-M0C3T0 <> U20-M1C2T0 Data Latency : 57.8ns
> U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.6ns
> U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.4ns
> U6-M0C3T0 <> U26-M1C5T0 Data Latency : 59.1ns
> U6-M0C3T0 <> U28-M1C6T0 Data Latency : 59.0ns
> U6-M0C3T0 <> U30-M1C7T0 Data Latency : 59.1ns
> U6-M0C3T0 <> U1-M0C0T1 Data Latency : 20.7ns
> U6-M0C3T0 <> U3-M0C1T1 Data Latency : 21.8ns
> U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.8ns
> U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
> U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.5ns
> U6-M0C3T0 <> U11-M0C5T1 Data Latency : 23.0ns
> U6-M0C3T0 <> U13-M0C6T1 Data Latency : 21.3ns
> U6-M0C3T0 <> U15-M0C7T1 Data Latency : 22.4ns
> U6-M0C3T0 <> U17-M1C0T1 Data Latency : 58.2ns
> U6-M0C3T0 <> U19-M1C1T1 Data Latency : 58.3ns
> U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.7ns
> U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.7ns
> U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.4ns
> U6-M0C3T0 <> U27-M1C5T1 Data Latency : 59.2ns
> U6-M0C3T0 <> U29-M1C6T1 Data Latency : 59.0ns
> U6-M0C3T0 <> U31-M1C7T1 Data Latency : 59.1ns
> U8-M0C4T0 <> U10-M0C5T0 Data Latency : 21.1ns
> U8-M0C4T0 <> U12-M0C6T0 Data Latency : 21.3ns
> U8-M0C4T0 <> U14-M0C7T0 Data Latency : 20.8ns
> U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.7ns
> U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.9ns
> U8-M0C4T0 <> U20-M1C2T0 Data Latency : 57.3ns
> U8-M0C4T0 <> U22-M1C3T0 Data Latency : 58.1ns
> U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.2ns
> U8-M0C4T0 <> U26-M1C5T0 Data Latency : 59.1ns
> U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.5ns
> U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.9ns
> U8-M0C4T0 <> U1-M0C0T1 Data Latency : 19.0ns
> U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.6ns
> U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.1ns
> U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.5ns
> U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.6ns
> U8-M0C4T0 <> U11-M0C5T1 Data Latency : 21.0ns
> U8-M0C4T0 <> U13-M0C6T1 Data Latency : 21.3ns
> U8-M0C4T0 <> U15-M0C7T1 Data Latency : 20.8ns
> U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.5ns
> U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.9ns
> U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.3ns
> U8-M0C4T0 <> U23-M1C3T1 Data Latency : 58.1ns
> U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.2ns
> U8-M0C4T0 <> U27-M1C5T1 Data Latency : 59.0ns
> U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.4ns
> U8-M0C4T0 <> U31-M1C7T1 Data Latency : 59.0ns
> U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.5ns
> U10-M0C5T0 <> U14-M0C7T0 Data Latency : 22.4ns
> U10-M0C5T0 <> U16-M1C0T0 Data Latency : 58.1ns
> U10-M0C5T0 <> U18-M1C1T0 Data Latency : 58.1ns
> U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.0ns
> U10-M0C5T0 <> U22-M1C3T0 Data Latency : 59.1ns
> U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.8ns
> U10-M0C5T0 <> U26-M1C5T0 Data Latency : 59.5ns
> U10-M0C5T0 <> U28-M1C6T0 Data Latency : 59.0ns
> U10-M0C5T0 <> U30-M1C7T0 Data Latency : 59.1ns
> U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.8ns
> U10-M0C5T0 <> U3-M0C1T1 Data Latency : 22.0ns
> U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.6ns
> U10-M0C5T0 <> U7-M0C3T1 Data Latency : 23.1ns
> U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
> U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.8ns
> U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.5ns
> U10-M0C5T0 <> U15-M0C7T1 Data Latency : 22.4ns
> U10-M0C5T0 <> U17-M1C0T1 Data Latency : 58.1ns
> U10-M0C5T0 <> U19-M1C1T1 Data Latency : 58.2ns
> U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.0ns
> U10-M0C5T0 <> U23-M1C3T1 Data Latency : 59.0ns
> U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.8ns
> U10-M0C5T0 <> U27-M1C5T1 Data Latency : 59.4ns
> U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.9ns
> U10-M0C5T0 <> U31-M1C7T1 Data Latency : 59.3ns
> U12-M0C6T0 <> U14-M0C7T0 Data Latency : 21.6ns
> U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.2ns
> U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.5ns
> U12-M0C6T0 <> U20-M1C2T0 Data Latency : 57.9ns
> U12-M0C6T0 <> U22-M1C3T0 Data Latency : 59.1ns
> U12-M0C6T0 <> U24-M1C4T0 Data Latency : 58.7ns
> U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.8ns
> U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.4ns
> U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.8ns
> U12-M0C6T0 <> U1-M0C0T1 Data Latency : 20.2ns
> U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.4ns
> U12-M0C6T0 <> U5-M0C2T1 Data Latency : 20.8ns
> U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
> U12-M0C6T0 <> U9-M0C4T1 Data Latency : 21.1ns
> U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.6ns
> U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
> U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.7ns
> U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.2ns
> U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.7ns
> U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.1ns
> U12-M0C6T0 <> U23-M1C3T1 Data Latency : 59.0ns
> U12-M0C6T0 <> U25-M1C4T1 Data Latency : 58.7ns
> U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.6ns
> U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.3ns
> U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.6ns
> U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.3ns
> U14-M0C7T0 <> U18-M1C1T0 Data Latency : 58.2ns
> U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.1ns
> U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.6ns
> U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.0ns
> U14-M0C7T0 <> U26-M1C5T0 Data Latency : 59.4ns
> U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.2ns
> U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.3ns
> U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.4ns
> U14-M0C7T0 <> U3-M0C1T1 Data Latency : 21.5ns
> U14-M0C7T0 <> U5-M0C2T1 Data Latency : 21.0ns
> U14-M0C7T0 <> U7-M0C3T1 Data Latency : 22.5ns
> U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.0ns
> U14-M0C7T0 <> U11-M0C5T1 Data Latency : 22.5ns
> U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.6ns
> U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
> U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.3ns
> U14-M0C7T0 <> U19-M1C1T1 Data Latency : 58.1ns
> U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.1ns
> U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.6ns
> U14-M0C7T0 <> U25-M1C4T1 Data Latency : 58.9ns
> U14-M0C7T0 <> U27-M1C5T1 Data Latency : 59.4ns
> U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.3ns
> U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.3ns
> U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.6ns
> U16-M1C0T0 <> U20-M1C2T0 Data Latency : 19.0ns
> U16-M1C0T0 <> U22-M1C3T0 Data Latency : 20.9ns
> U16-M1C0T0 <> U24-M1C4T0 Data Latency : 19.6ns
> U16-M1C0T0 <> U26-M1C5T0 Data Latency : 21.1ns
> U16-M1C0T0 <> U28-M1C6T0 Data Latency : 20.2ns
> U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.4ns
> U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.2ns
> U16-M1C0T0 <> U3-M0C1T1 Data Latency : 57.8ns
> U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.1ns
> U16-M1C0T0 <> U7-M0C3T1 Data Latency : 58.4ns
> U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.6ns
> U16-M1C0T0 <> U11-M0C5T1 Data Latency : 58.5ns
> U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.1ns
> U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.4ns
> U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.8ns
> U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.6ns
> U16-M1C0T0 <> U21-M1C2T1 Data Latency : 19.0ns
> U16-M1C0T0 <> U23-M1C3T1 Data Latency : 20.5ns
> U16-M1C0T0 <> U25-M1C4T1 Data Latency : 19.6ns
> U16-M1C0T0 <> U27-M1C5T1 Data Latency : 21.1ns
> U16-M1C0T0 <> U29-M1C6T1 Data Latency : 20.2ns
> U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
> U18-M1C1T0 <> U20-M1C2T0 Data Latency : 18.9ns
> U18-M1C1T0 <> U22-M1C3T0 Data Latency : 21.5ns
> U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.6ns
> U18-M1C1T0 <> U26-M1C5T0 Data Latency : 22.2ns
> U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.2ns
> U18-M1C1T0 <> U30-M1C7T0 Data Latency : 21.8ns
> U18-M1C1T0 <> U1-M0C0T1 Data Latency : 57.3ns
> U18-M1C1T0 <> U3-M0C1T1 Data Latency : 58.1ns
> U18-M1C1T0 <> U5-M0C2T1 Data Latency : 57.7ns
> U18-M1C1T0 <> U7-M0C3T1 Data Latency : 58.3ns
> U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.6ns
> U18-M1C1T0 <> U11-M0C5T1 Data Latency : 58.4ns
> U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.2ns
> U18-M1C1T0 <> U15-M0C7T1 Data Latency : 58.4ns
> U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.6ns
> U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
> U18-M1C1T0 <> U21-M1C2T1 Data Latency : 18.9ns
> U18-M1C1T0 <> U23-M1C3T1 Data Latency : 21.5ns
> U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.6ns
> U18-M1C1T0 <> U27-M1C5T1 Data Latency : 22.2ns
> U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.2ns
> U18-M1C1T0 <> U31-M1C7T1 Data Latency : 21.6ns
> U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.5ns
> U20-M1C2T0 <> U24-M1C4T0 Data Latency : 20.2ns
> U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.6ns
> U20-M1C2T0 <> U28-M1C6T0 Data Latency : 20.6ns
> U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.5ns
> U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.2ns
> U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.7ns
> U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.2ns
> U20-M1C2T0 <> U7-M0C3T1 Data Latency : 58.1ns
> U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.5ns
> U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.3ns
> U20-M1C2T0 <> U13-M0C6T1 Data Latency : 57.9ns
> U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.0ns
> U20-M1C2T0 <> U17-M1C0T1 Data Latency : 19.2ns
> U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
> U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
> U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.5ns
> U20-M1C2T0 <> U25-M1C4T1 Data Latency : 20.2ns
> U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.6ns
> U20-M1C2T0 <> U29-M1C6T1 Data Latency : 20.6ns
> U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.4ns
> U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.5ns
> U22-M1C3T0 <> U26-M1C5T0 Data Latency : 22.7ns
> U22-M1C3T0 <> U28-M1C6T0 Data Latency : 20.9ns
> U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.9ns
> U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.6ns
> U22-M1C3T0 <> U3-M0C1T1 Data Latency : 58.3ns
> U22-M1C3T0 <> U5-M0C2T1 Data Latency : 58.0ns
> U22-M1C3T0 <> U7-M0C3T1 Data Latency : 58.8ns
> U22-M1C3T0 <> U9-M0C4T1 Data Latency : 58.2ns
> U22-M1C3T0 <> U11-M0C5T1 Data Latency : 58.7ns
> U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.8ns
> U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.9ns
> U22-M1C3T0 <> U17-M1C0T1 Data Latency : 20.4ns
> U22-M1C3T0 <> U19-M1C1T1 Data Latency : 21.4ns
> U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.5ns
> U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.7ns
> U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.4ns
> U22-M1C3T0 <> U27-M1C5T1 Data Latency : 22.7ns
> U22-M1C3T0 <> U29-M1C6T1 Data Latency : 20.9ns
> U22-M1C3T0 <> U31-M1C7T1 Data Latency : 22.0ns
> U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.3ns
> U24-M1C4T0 <> U28-M1C6T0 Data Latency : 21.6ns
> U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.2ns
> U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.9ns
> U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.8ns
> U24-M1C4T0 <> U5-M0C2T1 Data Latency : 57.8ns
> U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.8ns
> U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.2ns
> U24-M1C4T0 <> U11-M0C5T1 Data Latency : 59.3ns
> U24-M1C4T0 <> U13-M0C6T1 Data Latency : 58.7ns
> U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.1ns
> U24-M1C4T0 <> U17-M1C0T1 Data Latency : 19.6ns
> U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.8ns
> U24-M1C4T0 <> U21-M1C2T1 Data Latency : 23.0ns
> U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.8ns
> U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
> U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.4ns
> U24-M1C4T0 <> U29-M1C6T1 Data Latency : 23.0ns
> U24-M1C4T0 <> U31-M1C7T1 Data Latency : 22.1ns
> U26-M1C5T0 <> U28-M1C6T0 Data Latency : 20.2ns
> U26-M1C5T0 <> U30-M1C7T0 Data Latency : 20.4ns
> U26-M1C5T0 <> U1-M0C0T1 Data Latency : 58.2ns
> U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.5ns
> U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.7ns
> U26-M1C5T0 <> U7-M0C3T1 Data Latency : 59.0ns
> U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.8ns
> U26-M1C5T0 <> U11-M0C5T1 Data Latency : 58.5ns
> U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.8ns
> U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.9ns
> U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U19-M1C1T1 Data Latency : 20.5ns
> U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.6ns
> U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.2ns
> U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
> U26-M1C5T0 <> U29-M1C6T1 Data Latency : 20.2ns
> U26-M1C5T0 <> U31-M1C7T1 Data Latency : 20.4ns
> U28-M1C6T0 <> U30-M1C7T0 Data Latency : 20.9ns
> U28-M1C6T0 <> U1-M0C0T1 Data Latency : 59.0ns
> U28-M1C6T0 <> U3-M0C1T1 Data Latency : 59.2ns
> U28-M1C6T0 <> U5-M0C2T1 Data Latency : 59.5ns
> U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.6ns
> U28-M1C6T0 <> U9-M0C4T1 Data Latency : 59.1ns
> U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.9ns
> U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.6ns
> U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.5ns
> U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.6ns
> U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.3ns
> U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.4ns
> U28-M1C6T0 <> U23-M1C3T1 Data Latency : 20.3ns
> U28-M1C6T0 <> U25-M1C4T1 Data Latency : 22.1ns
> U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.6ns
> U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.7ns
> U28-M1C6T0 <> U31-M1C7T1 Data Latency : 20.9ns
> U30-M1C7T0 <> U1-M0C0T1 Data Latency : 58.6ns
> U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.7ns
> U30-M1C7T0 <> U5-M0C2T1 Data Latency : 59.3ns
> U30-M1C7T0 <> U7-M0C3T1 Data Latency : 59.1ns
> U30-M1C7T0 <> U9-M0C4T1 Data Latency : 59.0ns
> U30-M1C7T0 <> U11-M0C5T1 Data Latency : 59.3ns
> U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.8ns
> U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.7ns
> U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.4ns
> U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.4ns
> U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.9ns
> U30-M1C7T0 <> U23-M1C3T1 Data Latency : 20.5ns
> U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.9ns
> U30-M1C7T0 <> U27-M1C5T1 Data Latency : 20.4ns
> U30-M1C7T0 <> U29-M1C6T1 Data Latency : 20.9ns
> U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
> U1-M0C0T1 <> U3-M0C1T1 Data Latency : 20.2ns
> U1-M0C0T1 <> U5-M0C2T1 Data Latency : 21.7ns
> U1-M0C0T1 <> U7-M0C3T1 Data Latency : 20.8ns
> U1-M0C0T1 <> U9-M0C4T1 Data Latency : 21.6ns
> U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.0ns
> U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.4ns
> U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.3ns
> U1-M0C0T1 <> U17-M1C0T1 Data Latency : 58.7ns
> U1-M0C0T1 <> U19-M1C1T1 Data Latency : 58.0ns
> U1-M0C0T1 <> U21-M1C2T1 Data Latency : 58.8ns
> U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.8ns
> U1-M0C0T1 <> U25-M1C4T1 Data Latency : 59.0ns
> U1-M0C0T1 <> U27-M1C5T1 Data Latency : 58.4ns
> U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.9ns
> U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.8ns
> U3-M0C1T1 <> U5-M0C2T1 Data Latency : 20.6ns
> U3-M0C1T1 <> U7-M0C3T1 Data Latency : 21.2ns
> U3-M0C1T1 <> U9-M0C4T1 Data Latency : 21.2ns
> U3-M0C1T1 <> U11-M0C5T1 Data Latency : 20.5ns
> U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.3ns
> U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.3ns
> U3-M0C1T1 <> U17-M1C0T1 Data Latency : 58.2ns
> U3-M0C1T1 <> U19-M1C1T1 Data Latency : 58.4ns
> U3-M0C1T1 <> U21-M1C2T1 Data Latency : 58.7ns
> U3-M0C1T1 <> U23-M1C3T1 Data Latency : 58.5ns
> U3-M0C1T1 <> U25-M1C4T1 Data Latency : 59.2ns
> U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.6ns
> U3-M0C1T1 <> U29-M1C6T1 Data Latency : 59.1ns
> U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.6ns
> U5-M0C2T1 <> U7-M0C3T1 Data Latency : 20.7ns
> U5-M0C2T1 <> U9-M0C4T1 Data Latency : 23.1ns
> U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.4ns
> U5-M0C2T1 <> U13-M0C6T1 Data Latency : 22.6ns
> U5-M0C2T1 <> U15-M0C7T1 Data Latency : 21.3ns
> U5-M0C2T1 <> U17-M1C0T1 Data Latency : 59.4ns
> U5-M0C2T1 <> U19-M1C1T1 Data Latency : 58.8ns
> U5-M0C2T1 <> U21-M1C2T1 Data Latency : 59.4ns
> U5-M0C2T1 <> U23-M1C3T1 Data Latency : 58.9ns
> U5-M0C2T1 <> U25-M1C4T1 Data Latency : 59.7ns
> U5-M0C2T1 <> U27-M1C5T1 Data Latency : 59.2ns
> U5-M0C2T1 <> U29-M1C6T1 Data Latency : 59.8ns
> U5-M0C2T1 <> U31-M1C7T1 Data Latency : 59.3ns
> U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.7ns
> U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.9ns
> U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.5ns
> U7-M0C3T1 <> U15-M0C7T1 Data Latency : 20.7ns
> U7-M0C3T1 <> U17-M1C0T1 Data Latency : 58.3ns
> U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.8ns
> U7-M0C3T1 <> U21-M1C2T1 Data Latency : 58.3ns
> U7-M0C3T1 <> U23-M1C3T1 Data Latency : 58.6ns
> U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.6ns
> U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.3ns
> U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.6ns
> U7-M0C3T1 <> U31-M1C7T1 Data Latency : 58.2ns
> U9-M0C4T1 <> U11-M0C5T1 Data Latency : 21.0ns
> U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.7ns
> U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.7ns
> U9-M0C4T1 <> U17-M1C0T1 Data Latency : 59.1ns
> U9-M0C4T1 <> U19-M1C1T1 Data Latency : 58.8ns
> U9-M0C4T1 <> U21-M1C2T1 Data Latency : 59.3ns
> U9-M0C4T1 <> U23-M1C3T1 Data Latency : 58.6ns
> U9-M0C4T1 <> U25-M1C4T1 Data Latency : 59.8ns
> U9-M0C4T1 <> U27-M1C5T1 Data Latency : 59.4ns
> U9-M0C4T1 <> U29-M1C6T1 Data Latency : 59.4ns
> U9-M0C4T1 <> U31-M1C7T1 Data Latency : 59.3ns
> U11-M0C5T1 <> U13-M0C6T1 Data Latency : 20.1ns
> U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.8ns
> U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.6ns
> U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.6ns
> U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.9ns
> U11-M0C5T1 <> U23-M1C3T1 Data Latency : 58.3ns
> U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.9ns
> U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.9ns
> U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.6ns
> U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.1ns
> U13-M0C6T1 <> U15-M0C7T1 Data Latency : 21.9ns
> U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.2ns
> U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.8ns
> U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.0ns
> U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.5ns
> U13-M0C6T1 <> U25-M1C4T1 Data Latency : 58.8ns
> U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.0ns
> U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.6ns
> U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.5ns
> U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.6ns
> U15-M0C7T1 <> U19-M1C1T1 Data Latency : 58.3ns
> U15-M0C7T1 <> U21-M1C2T1 Data Latency : 59.0ns
> U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.3ns
> U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.4ns
> U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.5ns
> U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.3ns
> U15-M0C7T1 <> U31-M1C7T1 Data Latency : 58.8ns
> U17-M1C0T1 <> U19-M1C1T1 Data Latency : 20.3ns
> U17-M1C0T1 <> U21-M1C2T1 Data Latency : 21.5ns
> U17-M1C0T1 <> U23-M1C3T1 Data Latency : 20.6ns
> U17-M1C0T1 <> U25-M1C4T1 Data Latency : 22.3ns
> U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.3ns
> U17-M1C0T1 <> U29-M1C6T1 Data Latency : 20.7ns
> U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
> U19-M1C1T1 <> U21-M1C2T1 Data Latency : 18.9ns
> U19-M1C1T1 <> U23-M1C3T1 Data Latency : 20.5ns
> U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.7ns
> U19-M1C1T1 <> U27-M1C5T1 Data Latency : 21.2ns
> U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.3ns
> U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.2ns
> U21-M1C2T1 <> U23-M1C3T1 Data Latency : 20.4ns
> U21-M1C2T1 <> U25-M1C4T1 Data Latency : 23.0ns
> U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.3ns
> U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.4ns
> U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.0ns
> U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.7ns
> U23-M1C3T1 <> U27-M1C5T1 Data Latency : 20.5ns
> U23-M1C3T1 <> U29-M1C6T1 Data Latency : 20.1ns
> U23-M1C3T1 <> U31-M1C7T1 Data Latency : 20.3ns
> U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.4ns
> U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
> U25-M1C4T1 <> U31-M1C7T1 Data Latency : 22.1ns
> U27-M1C5T1 <> U29-M1C6T1 Data Latency : 20.2ns
> U27-M1C5T1 <> U31-M1C7T1 Data Latency : 20.4ns
> U29-M1C6T1 <> U31-M1C7T1 Data Latency : 20.9ns
> 1x 64bytes Blocks Bandwidth : 26GB/s
> 4x 64bytes Blocks Bandwidth : 28.58GB/s
> 4x 256bytes Blocks Bandwidth : 104.42GB/s
> 4x 1kB Blocks Bandwidth : 331.12GB/s
> 4x 4kB Blocks Bandwidth : 516.4GB/s
> 16x 4kB Blocks Bandwidth : 729.87GB/s
> 4x 64kB Blocks Bandwidth : 999GB/s
> 16x 64kB Blocks Bandwidth : 612GB/s
> 8x 256kB Blocks Bandwidth : 611.36GB/s
> 4x 1MB Blocks Bandwidth : 609.24GB/s
> 16x 1MB Blocks Bandwidth : 29.89GB/s
> 8x 4MB Blocks Bandwidth : 19.29GB/s
> 
> Benchmark Status
> Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.85GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
> Microcode : A20F10-1009
> Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
> Platform Compliance : x64
> No. Threads : 32
> System Timer : 10MHz
> Page Size : 2MB
> 
> Processor
> Model : AMD Ryzen 9 5950X 16-Core Processor
> URL : https://www.amd.com
> Speed : 4.85GHz
> Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.85GHz
> Modules per Processor : 2 Unit(s)
> Cores per Processor : 8 Unit(s)
> Threads per Core : 2 Unit(s)
> Front-Side Bus Speed : 100MHz
> Revision/Stepping : 21 / 0
> Microcode : A20F10-1009
> Latest Version : A20F10-16
> L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
> L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
> L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
> Rated Power (TDP) : 105.00W
> 
> Memory Controller
> Speed : 1.9GHz (100%)
> Min/Max/Turbo Speed : 950MHz - 1.9GHz
> 
> Performance Enhancing Tips
> Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
> Tip 229 : CPU microcode update available. Check for an updated System BIOS with updated microcode.
> Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


Upgraded to the newest BIOS from A21 I think it was.



Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 174.55GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.7ns (9.6ns - 59.7ns)
Inter-Thread (same Core) Latency : 9.8ns
Inter-Core (same Module) Latency : 20.7ns
Inter-Module (same Package) Latency : 58.2ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.45GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1702.27MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.78ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 36.85MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 19.3ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.6ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 20.0ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 19.5ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 20.4ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 20.6ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.4ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 57.0ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 56.8ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 57.2ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 57.1ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 57.9ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 57.7ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 57.9ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 58.0ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 19.3ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 19.6ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 20.1ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 19.5ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 20.4ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 20.6ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.4ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 57.0ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 56.7ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 57.1ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 57.1ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 57.8ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 57.7ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 58.0ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 58.0ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 19.2ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 20.8ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.6ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 21.3ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.3ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.8ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 56.7ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 56.8ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 56.9ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 57.4ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 57.8ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 58.1ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 58.1ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 58.0ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 19.2ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.9ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 19.2ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 20.8ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 19.6ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 21.3ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.3ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.8ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 56.7ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 56.8ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 57.0ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 57.5ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 57.9ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 58.1ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 58.2ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 58.1ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.8ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 20.8ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.6ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 21.3ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 20.8ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 57.4ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 57.2ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 57.4ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 57.8ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 57.8ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 58.2ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.3ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 58.5ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 19.6ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 19.3ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.9ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.8ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 20.8ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.6ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 21.3ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 20.8ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 57.4ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 57.2ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 57.4ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 57.8ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 57.8ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 58.3ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 58.3ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 58.5ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.6ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 22.1ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 21.5ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.7ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 57.6ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 57.8ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 57.7ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 58.2ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 58.6ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 58.8ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 59.0ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 59.1ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 20.1ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 20.9ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.8ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.9ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.6ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 22.1ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 21.5ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.8ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 57.5ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 57.8ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 57.8ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 58.3ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.6ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 58.8ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 59.0ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 59.1ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.8ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 21.8ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.1ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 57.5ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 57.5ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 57.6ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.7ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.4ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 58.5ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.7ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.8ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 19.5ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.8ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 20.8ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.6ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.6ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.8ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 21.8ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.1ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 57.6ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.6ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.5ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.7ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.3ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 58.5ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.7ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.9ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.6ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.9ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 57.6ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 57.8ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 58.0ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 58.0ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 59.0ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 58.8ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.9ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 59.0ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 20.3ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 21.3ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.6ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 22.1ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 20.9ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.7ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.5ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.9ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 57.6ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 57.8ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 58.0ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 58.1ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 59.0ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 58.8ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 59.0ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 59.0ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 21.7ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 58.2ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 58.0ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.0ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.5ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.0ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 59.0ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 59.6ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.7ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 20.6ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.5ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 21.5ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.3ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 21.8ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.6ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.8ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 22.0ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 58.2ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 58.0ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.0ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.5ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.0ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 59.1ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 59.6ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.6ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 58.1ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.8ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 58.2ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.4ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.2ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 59.0ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.6ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 59.4ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.5ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 21.0ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 20.9ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.7ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.2ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.9ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.8ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.8ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 58.1ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.9ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 58.2ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 58.3ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.1ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 59.1ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.7ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 59.4ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 19.3ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 19.5ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.9ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 20.1ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 20.6ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 20.8ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.6ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 57.3ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 57.4ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 57.3ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 58.0ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 57.9ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 57.8ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 58.3ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 58.4ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.9ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 19.3ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 19.6ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.9ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 20.2ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 20.7ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 20.8ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.6ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 19.0ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 20.6ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 19.8ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 21.3ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.3ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.9ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 56.8ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 57.4ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 57.3ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 57.8ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.5ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 57.9ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 58.0ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.7ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 19.4ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.8ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 19.0ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 20.6ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 19.8ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 21.3ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.3ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.9ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.6ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 20.8ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.5ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 21.2ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 20.7ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 57.1ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.4ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 57.6ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 57.8ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.9ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 58.0ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.1ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 58.2ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 19.4ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.0ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.9ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.6ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 20.8ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.5ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 21.2ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 20.7ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.5ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 21.9ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.0ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.3ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 57.3ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 57.9ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.9ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 58.4ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.8ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 58.2ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.4ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 58.3ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.9ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 20.7ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 19.8ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.7ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.5ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 21.9ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.0ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 21.3ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.3ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 22.2ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 21.6ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 58.1ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.3ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.1ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 58.8ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.5ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 59.1ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.0ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.2ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 20.2ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 19.9ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 20.8ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.5ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 9.9ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.3ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 22.2ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 21.6ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.7ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 22.1ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 57.7ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 58.6ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 58.3ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 59.0ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 58.6ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 59.0ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 59.2ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 59.2ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 20.6ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 21.3ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.5ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 21.9ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.3ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.9ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.7ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 22.1ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 21.7ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 58.1ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.5ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 58.6ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 59.0ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.5ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 59.0ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.3ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.3ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 20.8ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.4ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 21.3ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 21.0ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 22.1ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.6ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.8ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 21.9ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 57.9ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 58.2ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 58.7ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 58.8ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.7ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.9ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.4ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 59.2ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.6ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.9ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 20.8ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.3ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 21.6ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 22.0ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 21.7ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 19.4ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 19.5ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 20.1ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 19.6ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 20.3ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 20.6ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.4ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 57.1ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 56.7ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 57.1ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 57.1ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.8ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 57.7ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 58.0ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 58.0ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.3ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 20.9ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.7ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 21.4ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.4ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 21.0ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 57.0ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 57.0ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.2ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 57.7ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 58.1ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 58.3ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.4ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 58.3ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.9ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 20.8ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.6ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 21.4ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 20.9ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 57.3ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 57.3ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 57.3ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.7ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 57.8ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 58.2ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.3ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 58.4ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.6ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 22.1ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 21.4ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.7ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 57.8ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 57.9ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 57.8ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 58.3ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 58.8ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 58.9ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 59.1ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 59.1ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.9ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 21.8ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.1ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 57.6ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 57.5ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 57.6ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.8ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.3ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 58.6ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.7ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.8ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.6ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.9ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 57.6ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 57.9ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 58.1ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 58.1ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 59.0ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 58.8ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 59.0ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 59.0ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 21.8ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 58.2ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.9ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.1ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.5ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 58.9ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 59.1ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 59.5ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 59.6ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 58.2ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.8ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.2ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.5ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.2ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 59.1ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.5ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 59.3ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 19.3ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 19.5ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.9ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 20.1ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 20.7ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 20.8ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.7ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 19.0ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 20.6ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 19.8ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 21.3ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.4ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.9ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.6ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 20.8ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.5ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 21.2ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 20.7ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.5ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 21.9ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.2ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.4ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.3ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 22.1ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 21.6ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.7ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 22.1ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 21.7ns
1x 64bytes Blocks Bandwidth : 26.12GB/s
4x 64bytes Blocks Bandwidth : 28.33GB/s
4x 256bytes Blocks Bandwidth : 99.15GB/s
4x 1kB Blocks Bandwidth : 323GB/s
4x 4kB Blocks Bandwidth : 509.3GB/s
16x 4kB Blocks Bandwidth : 687.87GB/s
4x 64kB Blocks Bandwidth : 996.6GB/s
16x 64kB Blocks Bandwidth : 584.68GB/s
8x 256kB Blocks Bandwidth : 604.5GB/s
4x 1MB Blocks Bandwidth : 612.84GB/s
16x 1MB Blocks Bandwidth : 22.56GB/s
8x 4MB Blocks Bandwidth : 19.78GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.85GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1016
Computer : MSI MS-7D13 (MSI MEG B550 UNIFY-X (MS-7D13))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Speed : 4.85GHz
Min/Max/Turbo Speed : 2.2GHz - 3.4GHz - 4.85GHz
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Front-Side Bus Speed : 100MHz
Revision/Stepping : 21 / 0
Microcode : A20F10-1016
Latest Version : A20F10-16
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Data/Unified Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Data/Unified Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Power (TDP) : 105.00W

Memory Controller
Speed : 1.9GHz (100%)
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Notice 242 : Dynamic OverClocking/Turbo engaged. Environment conditions may influence performance.
Tip 229 : CPU microcode update available. Check for an updated System BIOS with updated microcode.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## mongoled

Veii said:


> The opposite
> NOM is CKE high
> NOM needs to increase if VDIMM increases or generally signal strength increases
> I can see (theory) that stronger tCKE also would require more NOM - but only a theory so far
> 
> PARK is CKE low - floor
> Too tight CKE low, will shrink the gate
> A smaller gate, on a never ending sinus curve ~ increases it's strengthness, increases it's speed , increases strain on the PCB
> Small tube fluid flow, vs wide tube fluid flow. Wide = less ohm
> 
> Too tight NOM will result in the CKE signal to reflect back , or at best just drop faster than it can reflect upwards back
> Too low NOM will result CKE signal overshooting beyond the ceiling and never falling down
> 
> In general, NOM depends on PARK ~ they both have to work together (you can not see data-eye sadly, unless somebody figures out where ABL stores the debug/training file ~ location)
> PARK & NOM depend on WR. WR has the highest priority - and WR can "adapt" for the lack of NOM ~ if needed
> On low clean but thin voltage, there is no need to use either WR nor NOM. Boards have a preconfigured ceiling and floor. Even if you "disable" it. Traces have adapted for it. Soo for the 1.2-1.3v region
> 
> Using NOM in general should be required after 1.46v (realistically) but after 1.48v (common knowledge)
> More VDIMM = more NOM
> Too much NOM = needs adjustment on PARK (stronger park), else fall time & raise time will differ ~ balance thing
> 
> Generally, start with the least amount of PARK you can get away with.
> And with the highest amount of WR you can get away with
> if NOM needs to be set or not - depends on many factors, so also the MB PCB
> 
> Repeating so it's remembered,
> ~ WR changes NOM & PARK behavior. A2 can run WR /2 , but fail faster on higher MCLK
> (NOM */6* = 40 , WR */3* = 80, PARK* /3* = 80 ... *≠* .... NOM */6* = 40, WR */2* = 120 , PARK */3* = 80) ~ it's rather closer to (NOM */7* = 34.3, WR */2* = 120 , PARK */5* = 48)
> It's better taming high voltage (1.62+) on low freq, but too much WR will cause issues in achieving higher MT/s.
> Might still be an option for only 3800MT/s guys
> But again, RTT_WR changes NOM & PARK scaling. Their requirements change upon RTT_WR change
> 
> EDIT:
> Another sidenote, MEM-IC's same as VRAM-IC's have a +/- voltage scaling for their set clock
> You can overpower and underpower lower frequency sets too. Just so it's remembered when pushing 13-13 or 12-12 on low MCLK
> * also another reason why more RTT_WR can be useful for certain applications


Excellent info Veii !

The only thing that is not clear and this is down to us peeps not determining a baseline terminology to describe key logic statements.

What do I mean ??

So lets look at Veii excellent post

We have the use of the following words when describing Rtts, CKE etc etc

"High", "Low", "Tight", "Least", "Increase", "Stronger", "More" and others

Some of you may have understood where I am going with this and this is a question that keeps getting asked by peeps who want to get involved with tweaking memory.

These descriptive words dont help someone understand clearly whats going on.

For example when we say "stronger tCKE" in the context of using numbers to define what is stronger we need to know is stronger a higher tCKE value or a lower tCKE value ??

The same goes for when we say "require more NOM" what is more NOM in the context of RZQ/X is it a bigger integer or a lower integer or is more talking about more Ohms ??

Its about getting a baseline of how to describe these entities and the "direction" of logic and then to stick to it so it becomes consistent.

Think we can get to some sort of agreement ??

Below is a great example


Veii said:


> Generally, start with the least amount of PARK you can get away with.
> And with the highest amount of WR you can get away with


I understand here Veii is talking about ohms, but others who are new to this may think that he is talking about the integer value X found after the Rtts (RZQ/X).

Least amount of PARK in ohms is 34 ohms, but if we think its RZQ/1 that is 240 ohms the complete opposite!


----------



## tomzyka

Hey guys,
i got a new kit and first of all I would like to thank you, especially those who provide constant useful information, because without you I wouldn't have come so far!

I hope someone could help me with my recent problem:

This is my recent profile and I got it 25 cycles TM5 stable (don't mind the missing voltages/resistances, this is because it is on my gaming os and there are several components stripped + faceit ac. The complete ZenTimings will be in the next screenshot)


Spoiler: TM5















My problem is that these settings are TM5 stable but not with Karhu. What could cause that?


Spoiler: Karhu + AIDA + full ZenTimings















I already increased VSOC from 1.1V to 1.125V but that did not fixed it, should I increase it more or could it be another problem? (These settings w/o Setup times and 2T are completely stable with Karhu) 

I did not touched PBO/CO yet, just set it on manual and the default PPT/TDC/EDC limits.


----------



## ManniX-ITA

tomzyka said:


> I already increased VSOC from 1.1V to 1.125V but that did not fixed it, should I increase it more or could it be another problem? (These settings w/o Setup times and 2T are completely stable with Karhu)


What did you set in Advanced?


----------



## Veii

mongoled said:


> We have the use of the following words when describing Rtts, CKE etc etc
> 
> "High", "Low", "Tight", "Least", "Increase", "Stronger", "More" and others


xD
Low values - in generall

CKE , Clock Signal with "weak" can be delivered by many methods (low cLDO_VDDP, low ClkDrvStr, low VDIMM)
tCKE , mostly is "more or less" - the pure value

RTTs sometimes are translated , sometimes are not
It's hard, i see but it is what it is

tCKE "stronger" also means "more" , because higher value will cause "later" suspension.
I am not sure if tCKE only controls powerdown = timed , or actually controls increased strength of the CKE signal.
it shouldn't ~ for such CAD_BUS does control CkeDrvStr and OdtDrvStr

RTTs more value (ohm) means tighter gate. More Value is more impedance, but also translates to more termination impedance = tighter gate = more resistance
More = more ^^'

RZQ i don't know if it really is 240ohm, i don't think so ~ but it can be the something else.
As intel switched to 360ohm too last bioses & i know since 1191, a lot changed
Idk how to phrase it

MSI is the only one that translates these values
But also the only one which pushes now because of AMD CBS linking bugs - 1.6v SOC on the Vermeer APUs.
(they either messed up the SOC VID or the LN2 flag)
Links CBS & AMD OVERCLOCKING to the main menu - but has bios bugs thanks to that which insta kill APUs
And removes AMD CBS and OVERCLOCKING from the main menu. . .
Shouldn't even be bothered to link it to the main menu and wipe easy accessibility
(do more work, to make less options visible. and then doesn't even do correct work, soo bugs it out and nearly kills APUs 
~ some reported insta death thanks to their work hiding stuff. There is a reason board partners do not translate AMD CBS values. Bugs are dangerous there)

Anywho~
There is no way to get it correct 
It will be always missunderstood


----------



## Audioboxer

tomzyka said:


> Hey guys,
> i got a new kit and first of all I would like to thank you, especially those who provide constant useful information, because without you I wouldn't have come so far!
> 
> I hope someone could help me with my recent problem:
> 
> This is my recent profile and I got it 25 cycles TM5 stable (don't mind the missing voltages/resistances, this is because it is on my gaming os and there are several components stripped + faceit ac. The complete ZenTimings will be in the next screenshot)
> 
> 
> Spoiler: TM5
> 
> 
> 
> 
> View attachment 2522864
> 
> 
> 
> 
> My problem is that these settings are TM5 stable but not with Karhu. What could cause that?
> 
> 
> Spoiler: Karhu + AIDA + full ZenTimings
> 
> 
> 
> 
> View attachment 2522865
> 
> 
> 
> 
> I already increased VSOC from 1.1V to 1.125V but that did not fixed it, should I increase it more or could it be another problem? (These settings w/o Setup times and 2T are completely stable with Karhu)
> 
> I did not touched PBO/CO yet, just set it on manual and the default PPT/TDC/EDC limits.


Just an outside chance but have you tried a Setup of 55? Seemed to help another poster in this topic.

Also CsOdtDrvStr might be worth trying at 24/30.

On DR tRTP might be worth keeping at 6.


----------



## tomzyka

ManniX-ITA said:


> What did you set in Advanced?


In AMD CBS
Both Prefetcher enabled, Globale C-state Control + DF Cstates disabled, Power Supply Idle Control: Typical Current Idle, Memory Clear disabled, ECC disabled, TSME disabled, DFE Read & FFE Write Training enabled, BGS disabled & BGSalt enabled, Adress Hash Bank & Adress Hash CS & Adress Hash Rm & SPD Read Optimization enabled, IOMMU disabled, APBDIS 1, Fixed SOC Pstate P0, CPPC enabled, CPPC Preferred Cores disabled, NBIO DPM Control Manual - Socket 0/1 NBIO 0/1/2/3 Target DPM Level all on 2



Audioboxer said:


> Just an outside chance but have you tried a Setup of 55? Seemed to help another poster in this topic.
> 
> Also CsOdtDrvStr might be worth trying at 24/30.
> 
> On DR tRTP might be worth keeping at 6.


I tried the 55 Setup time but this results in a lot of errors in TM5. CsOdtDrvStr at 30 results in Error 4 in Cycle 18 of TM5 1usmus_v3 config. I could try it at 24 and or tRTP 6


----------



## Veii

tomzyka said:


> Globale C-state Control + DF Cstates disabled,


Take for example this


http://imgur.com/a/hE6Pf0a

Global C-State control needs to be enabled

APBDIS doesn't need to be enabled


tomzyka said:


> NBIO 0/1/2/3 Target DPM Level all on 2


DPM level on all of them, is not good 


tomzyka said:


> CPPC Preferred Cores disabled,


also needs to be enabled (for windows)


----------



## tomzyka

Veii said:


> Take for example this
> 
> 
> http://imgur.com/a/hE6Pf0a
> 
> Global C-State control needs to be enabled
> 
> APBDIS doesn't need to be enabled
> 
> DPM level on all of them, is not good
> 
> also needs to be enabled (for windows)


Alright thank you, I will try it with some changed Bios settings.
Is there a reason why C-State control needs to be enabled in terms of stress testing? Because my games feel better with it disabled and the performance is the same. CPPC Preferred Cores enabled makes performance worse in my situation, that's why I disabled it.

I saw that you mentioned months ago that "DPM LCLK has to be at 2-1-1-2-2-1-1-2 or 2-1-1-1-2-1-1-1 & DF-States as of 1200 & 1202 still need to be disabled". Is there a way to find out which value combination fits better to my system?


----------



## XPEHOPE3

tomzyka said:


> My problem is that these settings are TM5 stable but not with Karhu. What could cause that?


25 cycles might not be enough to check tRFC values close to lowest possible. E.g. 202ns are stable for me, but 198ns fails at 24-th cycle. So 200ns might fail after 25th cycle easily.


tomzyka said:


> CPPC Preferred Cores enabled makes performance worse in my situation, that's why I disabled it.


That's probably because cores #0 and #1 have easier time holding top frequency than best-by-CPPC cores, just like in my case. This can be verified with CoreCycler ("Small" FFTs, "Large"/"Huge" would fail for you I think; with cores set to "0,1,a,b", where a and b are numbers of your best CPPC cores, unless they are 0 or 1) and HWiNFO64. I believe the frequency held in such a test (for a given core at a given FFT size) will be the same with and without CPPC being enabled in BIOS.


----------



## Alpharevx

Hope i won't be ignored, so i'm running 4x8gb Micron E-Die, RTTs 6/3/3 with 60/20/30/20 for GDM OFF 2T VDIMM 1.40v procODT 34.3 Ω
is ClkDrvStr at 60 Ω safe for these RTT/procODT/VDIMM?


----------



## Arashi

EDIT: problem solved


----------



## PJVol

mongoled said:


> why we are seeing what we are seeing


I don't know, to be honest. But what I am 99% sure of is that the board (Extreme4) is to blame for the hell of a throttling, which happenes at IF > 1900, unless pushed vdd18 to its limit.
It became apparent after redoing some tests with the same CPU and RAM modules on the msi b450 board.



Spoiler: AIDA cache & mem

















Spoiler: 1usmus membench

















Spoiler: Sandra Lite GEMM and FFT tests 















I just doublechecked that the scaling in aida and 1usmus membench is inline with what have been observed previosly. And also made three runs of Sandra scientific benchmark at 3800, 4000 and 4066 fclk.

As you may see in screenshots, there's no any signs of negative scaling in MSI board tests, typical of the Asrock board.
And the fact, that I didn't even touch vdd18 (there wasn't such thing in bios, tbh, lol) strongly suggests that something is screwed in this particular Asrock board design.

As for GEMM test scores inconsistency, I don't think it worth much attention, you can see a similar pattern here, in my scores.
Only FCLK scaling is matter here so the scores SHOULD NOT decrease going from IF1900 to IF2000.
The conclusion, based on my testing - I have a flawed design board (or bios, that is less likely, but surely possible)
And your Unify seem to have been designed properly as well.

PS: testing was performed on this config: 

MSI B450 Mortar Titanium ITX / BIOS agesa 1.2.0.2 smu 56.50
Ryzen 5600X
2x8Gb Galax HOF 3600 17-18-18-38 1.35V
Radeon RX 570 4Gb
2 x Samsung's m.2 250 & 500Gb

PPS: up to and including 1933 - WHEA-free. At 2000 - 2033 - there were some, but not much, at least not hundreds, as on ASRock


----------



## PJVol

Arashi said:


> My TM5 couldn't show the error message in english for whatever reason but I assumed it means it failed test 15, and this error would keep popping up no matter what settings I changed.


Yes, it just says - the error number 15.


Arashi said:


> I also tried tinkering with the resistances but I have to admit I have no idea what those numbers do and what I was doing


I should admit that too, at least as far as RTT's and setup timings goes. 
Best solution for you is to try to catch Veii here and interrogate him thoroughly


----------



## Arashi

PJVol said:


> Yes, it just says - the error number 15.


Thanks for clearing that up. Now at least I know I didn't read the error message wrong.


----------



## sonixmon

First I would like to thank everyone in this community for their feedback and sharing of information it has been extremely helpful. Tuning memory on Ryzen is more difficult (to be fair, also tuning more than I have in past including secondary timings etc.) My last OC was a 4790k at 4.8ghz all core (tested 4.9 but too hot) and 2133mhz ram (4x8).

Ok so I have some more details in my case anyway confirmed dealing with temps. With the best timings I have been able to achieve (shown below) the ram needs to stay below 41-42 for stability. The temp fan was achieving this (Big ugly fan). When I installed the Corsair fan it is only keeping Ram at 44-45 and would fail stability test. I could force room AC down and open case to keep under 71 and would run stable 2 hours. That isn't desirable for summer so I spent most of the afternoon yesterday tweaking back to get stability up to 45 degrees. For some reason one DIMM is hotter than other, may swap slots and see if it follows stick (fan position didn't seem to matter for either fan).

This also required tweaking PROCODT, Park etc. after a recent post explaining a little more. I found this also helped first OC remain stable longer a few degrees higher but 43-44 still max. After loosening some timings I was able to get stable (for a 1 hour test so far, peaked at 45 after 20 mins). I had to drop primaries and some secondary's a little (I might try to retighten them later).
Outside of Water cooling ram (not going to happen in this build) or maybe a winter OC (since my room over garage is warm this time of year Up to 74 and I like 68 max in winter). TRAS and TRC were biggest issue with higher temps. I had to go up 1 tick on TRAS or it would fail at 44 degrees (that was my last change for stability).

I followed this review for my latest timings and he has similar temp discovery with TRAS/TRC. Might try to tweak my secondary back but thankful TRFC still stable.

G.Skill DDR4 3600 TridentZ Neo 16GB: Testing & Overclocking - G.Skill DDR4 3600 CL14 TridentZ Neo 16GB Review - Page 2 - Overclockers Club

Seems it might be specific to Ram sticks and affect everyone's differently. Definitely something to test with a fan if you are struggling for stability during testing though PC runs games fine etc.




Spoiler: Tightest timings, best scores































Spoiler: 45 Degree Safe Timings































Spoiler: Final Temps and Fan pictures





























I will be keeping both of these profiles on a USB for backup. Continue to tweak in test once temps drop again (ready for Fall temps!).


Edit: I also was able to drop voltage from 1.565 to 1.5.


----------



## LionAlonso

Hi!
I have some questions that im sure someone here will be able to answer them, or atleast hope so!
I have my ram at 3800, but there is a few things i have to say, first of all my ram hits *58* degrees or so at top temps, while gaming,so i cant tighten trfc a lot.
Anyways here is my actual zentimings:
Its TM5(extreme1), ycruncher and OCCT stable.








I have bdie, dual rank 2x 16 originally at 3200C14. I guess not very good bin.
My questions are:

Right now i have gdm enabled, i havent had time/knowledge to try to turn it off, but as of right now, with GDM on them, is it different for them to be 16 16 16 16 32 48 vs 16 15 15 15 30 45? or with GDM they autocorrect so having them at 15 doesnt matter because tCL still 16?
Right now as u can see I have the voltage at 1.39V, and with this timings i have 55.4ns at aida, do you guys think is worth it knowing my high temps at load (due to airflow and 3080 ti heat) to go up in voltage and try to get GDM off? it will be better latency? i want something for daily basis, but i dont really know if it will be worth.
Any comments will be aprecciated.
Thanks everyone!


----------



## sonixmon

LionAlonso said:


> Hi!
> I have some questions that im sure someone here will be able to answer them, or atleast hope so!
> I have my ram at 3800, but there is a few things i have to say, first of all my ram hits *58* degrees or so at top temps, while gaming,so i cant tighten trfc a lot.
> Anyways here is my actual zentimings:
> Its TM5(extreme1), ycruncher and OCCT stable.
> View attachment 2522926
> 
> I have bdie, dual rank 2x 16 originally at 3200C14. I guess not very good bin.
> My questions are:
> 
> Right now i have gdm enabled, i havent had time/knowledge to try to turn it off, but as of right now, with GDM on them, is it different for them to be 16 16 16 16 32 48 vs 16 15 15 15 30 45? or with GDM they autocorrect so having them at 15 doesnt matter because tCL still 16?
> Right now as u can see I have the voltage at 1.39V, and with this timings i have 55.4ns at aida, do you guys think is worth it knowing my high temps at load (due to airflow and 3080 ti heat) to go up in voltage and try to get GDM off? it will be better latency? i want something for daily basis, but i dont really know if it will be worth.
> Any comments will be aprecciated.
> Thanks everyone!


In my personal experience heat of DRAM is a definite factor. Read posts bout AddrCmdSetup to get GDM off, might work for you.

Honestly you would have to decide if it is worth it but I can speak from my experience that is isn't worth it but I would probably do it again if that make sense. I like to tinker and push things as far as I can (safely) so it is more of the challenge then the end result. You can look at my recent post above for current settings, ram and scores.

Below are some screenshots from my old 2x16gb 3600CL16 kit that I pushed to 3800CL16 1T GDMoff (non-b-die). It was a very good kit just would not operate below CL16. My new kit is B-Die and runs at CL14 but no matter what speed (above 2133) it requires either GDM on or AddrCmdSetup55/56.

Not a ton of difference but fun along the journey (for me).

Best on my previous kit (though latency was 56 with services stopped).










Progression of Timespy with the above kit 11071, my current best is 11410 (see above post).


----------



## tolis626

Since I haven't bought AIDA64 like apparently everyone else here, and since I don't feel like shelling out 50$ just to run one test, I thought I'd run the built-in benchmark in Ryzen DRAM Calculator after reading the post by @PJVol above. Below that are my current settings in ZenTimings. Is it just me, or does my latency seem rather high for what I'm running?


----------



## sonixmon

tolis626 said:


> Since I haven't bought AIDA64 like apparently everyone else here, and since I don't feel like shelling out 50$ just to run one test, I thought I'd run the built-in benchmark in Ryzen DRAM Calculator after reading the post by @PJVol above. Below that are my current settings in ZenTimings. Is it just me, or does my latency seem rather high for what I'm running?
> View attachment 2522938
> View attachment 2522939


















These are my old settings (ram only stable under 42c) I have not run on new settings just yet.


----------



## umea

Decided to try raising freq instead of lowering to 14 flat and got this far... Time to mess with procodt/cad_bus it seems as i think 1.55v is enough for 3933cl15. Tried to get 4000cl15 to run but computer restarts after about 20 minutes, might mess with some settings on that as well but I know that 2000fclk isnt super commonly stable on 5900x.


----------



## nanoshunter

tolis626 said:


> Since I haven't bought AIDA64 like apparently everyone else here, and since I don't feel like shelling out 50$ just to run one test...


Any reason not to take the free AIDA64Extreme one year licence via your Asus board armory crate?


----------



## tolis626

sonixmon said:


> View attachment 2522940
> View attachment 2522941
> 
> These are my old settings (ram only stable under 42c) I have not run on new settings just yet.


Aha! I see! Doesn't look much better than mine, so I think mine's in line with what it should be. Thanks a bunch for calming me down! 


nanoshunter said:


> Any reason not to take the free AIDA64Extreme one year licence via your Asus board armory crate?


What? Where can I find that? I can't see it in Armory Crate or Asus' support page for my motherboard.


----------



## BloodDivine

> What? Where can I find that? I can't see it in Armory Crate or Asus' support page for my motherboard.


You need to redeem it I guess 
Aida 64 Extreme (asus.com)


----------



## tolis626

BloodDivine said:


> You need to redeem it I guess
> Aida 64 Extreme (asus.com)


Opa, kalispera! 

Well, there's no "Redeem" tab in the "Featured" section of Armory Crate on my PC. Guess no Aida64 for me.


----------



## sonixmon

tolis626 said:


> Aha! I see! Doesn't look much better than mine, so I think mine's in line with what it should be. Thanks a bunch for calming me down!
> 
> What? Where can I find that? I can't see it in Armory Crate or Asus' support page for my motherboard.


I did a quick run with my new (looser timings) and it was more inline with yours. Also AIDA worth the cost for OC folks, been using since Finalwire days. Usually they runs specials for multiyear and I will renew then. Only need subscription for upgrades so usually only if getting new hardware.


----------



## umea

umea said:


> Decided to try raising freq instead of lowering to 14 flat and got this far... Time to mess with procodt/cad_bus it seems as i think 1.55v is enough for 3933cl15. Tried to get 4000cl15 to run but computer restarts after about 20 minutes, might mess with some settings on that as well but I know that 2000fclk isnt super commonly stable on 5900x.
> 
> View attachment 2522945


I got this stable on TM5 (20 cycles complete no problem), but get whea errors. Will mess with vermeer and buddies and see if I can get it going but if not back to the 3800 14 flat hell grind...
Changed ClkDrvStr to 40 and something else (don't remember what) to make it stable.

Anyone have details on how to troubleshoot whea errors?


----------



## tolis626

sonixmon said:


> I did a quick run with my new (looser timings) and it was more inline with yours. Also AIDA worth the cost for OC folks, been using since Finalwire days. Usually they runs specials for multiyear and I will renew then. Only need subscription for upgrades so usually only if getting new hardware.
> 
> View attachment 2522963
> 
> View attachment 2522964


Whaaaaaat? I'm actually getting better numbers? That's insane by my standards. I've always been a silicon lottery loser when it comes to memory (RAM, GPUs, you name it), so I'm actually genuinely surprised and excited I got a good result.

Also, got Aida64, screw it. Here's the results.








Not the best I've seen, but considering that I'm not that great at memory overclocking like some of you guys, I think it's a pretty good result! I will let the thing be for the time being, but I'll go back and see about messing with it some more, maybe get it down to 54ns.


----------



## mongoled

@tolis626 
You should investigate if your dimms are A0 PCB, because if they are and you are pushing over 1.5v with RttPark set to RZQ/1 you may end up killing your RAM.

Change RttPark to RZQ/3 and test for stability....


----------



## PJVol

@mongoled
Can you tell what the PCB rev. is on the photo? (for the HOF's on the left)


----------



## mongoled

PJVol said:


> @mongoled
> Can you tell what the PCB rev. is on the photo? (for the HOF's on the left)
> View attachment 2522999


No, there is a template somewhere on OC.net that shows the difference between the PCBs.

It also gives you an idea on how the pictures must be taken to be able to determine what the PCB is.

I cannot tell what the HOFs are from the picture you posted..


----------



## ManniX-ITA

tomzyka said:


> In AMD CBS
> Both Prefetcher enabled, Globale C-state Control + DF Cstates disabled, Power Supply Idle Control: Typical Current Idle, Memory Clear disabled, ECC disabled, TSME disabled, DFE Read & FFE Write Training enabled, BGS disabled & BGSalt enabled, Adress Hash Bank & Adress Hash CS & Adress Hash Rm & SPD Read Optimization enabled, IOMMU disabled, APBDIS 1, Fixed SOC Pstate P0, CPPC enabled, CPPC Preferred Cores disabled, NBIO DPM Control Manual - Socket 0/1 NBIO 0/1/2/3 Target DPM Level all on 2


I meant the Advanced tab in Kahru 

But that's interesting as well.
You should enable C-State as said by @Veii.
And set also Power Supply Idle Control to Auto or Low otherwise it will not go to the lower state.
Had stability issues with DPM control in manual with this specific BIOS I'm using now, so maybe it's worth checking if Auto makes a difference.


----------



## tolis626

mongoled said:


> @tolis626
> You should investigate if your dimms are A0 PCB, because if they are and you are pushing over 1.5v with RttPark set to RZQ/1 you may end up killing your RAM.
> 
> Change RttPark to RZQ/3 and test for stability....


Hmmm... Interesting. Thanks for clarifying that in time. 

Any idea how I can go about doing that? I have no idea how to tell what revision it is.


----------



## ManniX-ITA

PJVol said:


> Can you tell what the PCB rev. is on the photo? (for the HOF's on the left)


Hard to tell with this picture.
Looks like an A1/B1/custom on that based on the IC positions.


----------



## Mach3.2

ManniX-ITA said:


> Hard to tell with this picture.
> Looks like an A1/B1/custom on that based on the IC positions.
> 
> View attachment 2523005


@PJVol Could be an A0 for the HOF sticks, A1 is for ECC DIMMs afaik.


----------



## PJVol

ManniX-ITA said:


> Hard to tell with this picture.


Well, the chips layout on dimms look similar to that of the 1st picture (spaced evenly  ). This was from another angle








Anyway, wanna thank all those who responded.


----------



## tomzyka

ManniX-ITA said:


> I meant the Advanced tab in Kahru
> 
> But that's interesting as well.
> You should enable C-State as said by @Veii.
> And set also Power Supply Idle Control to Auto or Low otherwise it will not go to the lower state.
> Had stability issues with DPM control in manual with this specific BIOS I'm using now, so maybe it's worth checking if Auto makes a difference.


Oh well, I have CPU cache enabled, RNG Default and unticked Stress FPU 


Alright I have enabled C-States now and changed the DPM values to 2-1-1-2-2-1-1-2, I will also test Auto.

But I may have found the issue in my case. Is it possible that a ram oc is stable with SMT disabled but will fail with SMT enabled? I did the TM5 test after gaming while SMT was disabled in BIOS and it had no errors after 25 Cycles, the next day I did the test with Karhu (and enabled SMT in the meantime) and an error appeared. (GDM off, 2t, w/o setup times wasn't a problem with SMT being either disabled or enabled)


----------



## ManniX-ITA

tomzyka said:


> Oh well, I have CPU cache enabled, RNG Default and unticked Stress FPU


I remember CPU Cache can trigger errors also with IF unstable, not sure.



tomzyka said:


> But I may have found the issue in my case. Is it possible that a ram oc is stable with SMT disabled but will fail with SMT enabled?


Yes SMT and also SVM will raise the temps and can make IF/memory unstable.



PJVol said:


> Well, the chips layout on dimms look similar to that of the 1st picture (spaced evenly  ). This was from another angle


Yes I counted 5 ICs before but they are 4


----------



## Audioboxer

(Benched in normal Windows installation, haven't used safe mode or any of these fancy stripped down Windows installations)

Continuing to work on my 15 profile just now to get it totally finalised before polishing off 14 profile. Bit of a generic question now, but where would you guys go next from here? I tested voltage dropping to 0.96v on VDDG from 0.975v. I know some people can run 0.95v and even 0.9v I _think_ I've seen on CCD.

As for timings, tRFC is close to the edge at 250 at 1.5v. I can go lower but part of my mindset for my flat 15 profile was keep VDIMM lower than I run it on my 14 profile. I've not tried tRTP 5 which I've seen someone else run. Veii recommended 6 is already the lowest for DR. tRAS and tRC can come down a bit, they've just not been touched from the baseline 30/45 for flat 15. As for how low, I'm not 100% sure, 26/40 is run on my 14 profile.

I think outside of that, that's about it? I guess I could see if any "weaker" resistances pass OK to reduce IMC load? Try lowering ProcODT another notch? Don't think any of that leads to performance, but efficiency tweaking is still part of the memory game if you ask me!


----------



## tomzyka

tomzyka said:


> Hey guys,
> i got a new kit and first of all I would like to thank you, especially those who provide constant useful information, because without you I wouldn't have come so far!
> 
> I hope someone could help me with my recent problem:
> 
> This is my recent profile and I got it 25 cycles TM5 stable (don't mind the missing voltages/resistances, this is because it is on my gaming os and there are several components stripped + faceit ac. The complete ZenTimings will be in the next screenshot)
> 
> 
> Spoiler: TM5
> 
> 
> 
> 
> View attachment 2522864
> 
> 
> 
> 
> My problem is that these settings are TM5 stable but not with Karhu. What could cause that?
> 
> 
> Spoiler: Karhu + AIDA + full ZenTimings
> 
> 
> 
> 
> View attachment 2522865
> 
> 
> 
> 
> I already increased VSOC from 1.1V to 1.125V but that did not fixed it, should I increase it more or could it be another problem? (These settings w/o Setup times and 2T are completely stable with Karhu)
> 
> I did not touched PBO/CO yet, just set it on manual and the default PPT/TDC/EDC limits.


So apparently these Settings aren't stable with SMT enabled. Got an error 10 in the 12th cycle with SMT enabled. Decided to change tRDWR and tWRRD from 9-3 to 10-4 and got it TM5 stable now:










I'm going to do a test with Karhu tomorrow and see how it goes


----------



## Audioboxer

tomzyka said:


> So apparently these Settings aren't stable with SMT enabled. Got an error 10 in the 12th cycle with SMT enabled. Decided to change tRDWR and tWRRD from 9-3 to 10-4 and got it TM5 stable now:
> 
> View attachment 2523038
> 
> 
> I'm going to do a test with Karhu tomorrow and see how it goes


I would guess it was tRDWR, 12/9 is very tight. Some people even struggle with 14/9. 12/10 gives me something else to test though!


----------



## Audioboxer

Holding up OK so far, couldn't boot 12/10 for tCWL/tRDWR. What is the theoretical lowest on tRAS? IIRC is it 22/23? Don't want to take it too low. My 14 profile runs 26/40.


----------



## tolis626

mongoled said:


> @tolis626
> You should investigate if your dimms are A0 PCB, because if they are and you are pushing over 1.5v with RttPark set to RZQ/1 you may end up killing your RAM.
> 
> Change RttPark to RZQ/3 and test for stability....


Hey man. First off, thanks again for the invaluable info. For a second there you had me worried that I was doing it all wrong. BUT! Turns out that, according to this review by Overclockers.com, my kit is actually A2, so I should be good to go. Regardless, I took your advice and changed my settings. Right now I'm near the 6400% mark with no errors using 5/3/3 (NOM/WR/PARK) and I also added a AddrCmdYadaYada of 55, while also dropping my RAM voltage by 0.01V to 1.5V flat (reads 1.496V in HWiNFO64). Seems rock solid so far, and it also seems that it helped with temperatures too. I mean, fair enough, I got every fan on full tilt and it stabilized at 47-48C (which is realistically how high it can go during normal use). Thing is, even so, before these changes it would creep up to the low-mid 50s, so there's a definite improvement there. Room temp is controlled by AC at 25C always during the summer.

If this ends up finishing testing with no errors, I'll see about tightening some secondaries. But that's gonna have to wait a bit. RAM tuning is a bit tiring, and I think my settings should perform very near to the best case scenario I could hope for without water cooling everything.

EDIT : Everything's going fine. Realistically, if it was unstable, it would've probably shown it by now (over 2 hours and 8000% coverage in Karhu). BUT! For some reason, in ZenTimings my tPHYRDL is 28. Shouldn't it be 26? Hmmmm...








EDIT 2 : With that said, performance is actually marginally better.


----------



## sonixmon

tolis626 said:


> Whaaaaaat? I'm actually getting better numbers? That's insane by my standards. I've always been a silicon lottery loser when it comes to memory (RAM, GPUs, you name it), so I'm actually genuinely surprised and excited I got a good result.
> 
> Also, got Aida64, screw it. Here's the results.
> View attachment 2522985
> 
> Not the best I've seen, but considering that I'm not that great at memory overclocking like some of you guys, I think it's a pretty good result! I will let the thing be for the time being, but I'll go back and see about messing with it some more, maybe get it down to 54ns.


Yea that's not bad! I'm not very good either just read a lot and copy what others try with similar B-Die sets. Heat is my biggest issue with this set and is probably why it was sold as a 3600 kit and cheaper than the 3800 kit. At least I can get 3800 CL14 with fans. I do not want to go custom loop for this rig so I think I found my max in two different profiles (winter and spring/summer) LOL.

I have also started using Hydra for now (until I have time to do custom core offset) and it helped my temps but underclocks when cpu not in demand so it impacts my scores some. If I turn it off it seems cpu stays in profile but havent confirmed this.


----------



## sonixmon

Does anyone have knowledge about AddrCmdSetup etc? I haven't been able to find any info online about these settings. Trying to understand what exactly it does and what the levels do.


----------



## Audioboxer

tolis626 said:


> Hey man. First off, thanks again for the invaluable info. For a second there you had me worried that I was doing it all wrong. BUT! Turns out that, according to this review by Overclockers.com, my kit is actually A2, so I should be good to go. Regardless, I took your advice and changed my settings. Right now I'm near the 6400% mark with no errors using 5/3/3 (NOM/WR/PARK) and I also added a AddrCmdYadaYada of 55, while also dropping my RAM voltage by 0.01V to 1.5V flat (reads 1.496V in HWiNFO64). Seems rock solid so far, and it also seems that it helped with temperatures too. I mean, fair enough, I got every fan on full tilt and it stabilized at 47-48C (which is realistically how high it can go during normal use). Thing is, even so, before these changes it would creep up to the low-mid 50s, so there's a definite improvement there. Room temp is controlled by AC at 25C always during the summer.
> 
> If this ends up finishing testing with no errors, I'll see about tightening some secondaries. But that's gonna have to wait a bit. RAM tuning is a bit tiring, and I think my settings should perform very near to the best case scenario I could hope for without water cooling everything.
> 
> EDIT : Everything's going fine. Realistically, if it was unstable, it would've probably shown it by now (over 2 hours and 8000% coverage in Karhu). BUT! For some reason, in ZenTimings my tPHYRDL is 28. Shouldn't it be 26? Hmmmm...
> View attachment 2523129
> 
> EDIT 2 : With that said, performance is actually marginally better.
> View attachment 2523130


Seems to be quite common that when doing 3800 tCL14 1T tPHYRDL switches to 28 on one stick. Or maybe even both. It does it for one stick for me.

2T runs at 26.

Apparently 28 will give a small latency penalty but I guess if your overall gain from running 1T outweighs that it's all good.


----------



## sonixmon

sonixmon said:


> Does anyone have knowledge about AddrCmdSetup etc? I haven't been able to find any info online about these settings. Trying to understand what exactly it does and what the levels do.


Found this after searching again but don't feel more knowledgeable!


_AddrCmdSetup_ _- _Where one/mobo places a bit representative of 'setup time/timing' for the _"address and command pins"_ against the clock of the memory, ie RAM's clock speed.
_CsOdtSetup_ - Where one/mobo places a bit representative of 'setup time/timing' for the _"CS and ODT pins"_ against the clock of the memory, ie RAM's clock speed.
_CkeSetup_ - Where one/mobo places a bit representative of 'setup time/timing' for the _"CkeSetup pins"_ against the clock of the memory, ie RAM's clock speed.
Have been running 55 but just tried 10-56. 53 posts after few mem training but errors, 54 posts ok errors testing. So going up one to 56 for just a little more stability.


----------



## Audioboxer

Passed with 0.95v on VDDG.

Even though it passes not so sure about running tRTP at 5 after Veii mentioned 6 is lowest for DR.










Instead of knowing what services and Windows crap to turn off I grabbed this from safe mode. I guess if I pushed my tRFC lower I might get down into 53.x 👀


----------



## Veii

Audioboxer said:


> Passed with 0.95v on VDDG.
> 
> Even though it passes not so sure about running tRTP at 5 after Veii mentioned 6 is lowest for DR.


Ah nono, that was because tWR 12 was theoretically quite "impossible" for DR ~ and some bioses didn't even allow "6" to run
Matching tRTP = half of tWR , or rather the opposite ~ focusing on tRTP being a clean divider of tRFC , made things easier
just wasn't always stable

As for stbaility
Good job !,
Just consider to benchmark both (high and low voltage) ~ because Vermeer autocorrects whereever it can

Consider trying 860mV cLDO_VDDP & lower CCD, then higher IOD
Just for me this killed score, read was lower and latency was higher (with lower voltages)
Somehow Write kept up the same bandwidth

Yep, check for latency results ~ and push VDD 1.8v line, bit up ~ till you see no positive scaling after running 3 consecutive tests (one after another with 5-10sec break in between)
* 1.93v is common later. Should have no issues with 1.83v "on stock". 1.96 can be stable but often isn't

Also you might want to try and push SCL up (be sure to adjust tWRRD again ~ (SCL * tWRRD = tRCDRD or lower value))
Then after you found the SCL which gives you the best copy bandwidth , drop tRDRDSCL - to the lowest value which gives you the best Read bandwidth (that was stable = 2 here)
Soo something like 2-5, or 4-5 as SCLs
tRDRD_SCL is chipselect delay
tRDRD & tWRWR DD's are "Different Dimm" Delays ~ which do also make changes for 2 dimms. They are not only used for 4 DPC setups and not only Dual Rank
DD's you can drop to as low as you can afford. They do boost bandwidth ~ but always doublecheck


Spoiler: Illustrations


----------



## Audioboxer

Veii said:


> Ah nono, that was because tWR 12 was theoretically quite "impossible" for DR ~ and some bioses didn't even allow "6" to run
> Matching tRTP = half of tWR , or rather the opposite ~ focusing on tRTP being a clean divider of tRFC , made things easier
> just wasn't always stable
> 
> As for stbaility
> Good job !,
> Just consider to benchmark both (high and low voltage) ~ because Vermeer autocorrects whereever it can
> 
> Consider trying 860mV cLDO_VDDP & lower CCD, then higher IOD
> Just for me this killed score, read was lower and latency was higher (with lower voltages)
> Somehow Write kept up the same bandwidth
> 
> Yep, check for latency results ~ and push VDD 1.8v line, bit up ~ till you see no positive scaling after running 3 consecutive tests (one after another with 5-10sec break in between)
> * 1.93v is common later. Should have no issues with 1.83v "on stock". 1.96 can be stable but often isn't
> 
> Also you might want to try and push SCL up (be sure to adjust tWRRD again ~ (SCL * tWRRD = tRCDRD or lower value))
> Then after you found the SCL which gives you the best copy bandwidth , drop tRDRDSCL - to the lowest value which gives you the best Read bandwidth (that was stable = 2 here)
> Soo something like 2-5, or 4-5 as SCLs
> tRDRD_SCL is chipselect delay
> tRDRD & tWRWR DD's are "Different Dimm" Delays ~ which do also make changes for 2 dimms. They are not only used for 4 DPC setups and not only Dual Rank
> DD's you can drop to as low as you can afford. They do boost bandwidth ~ but always doublecheck
> 
> 
> Spoiler: Illustrations


Ahhh, gotcha, I just remembered us talking about 6 but I understand better now.

Some great tips in the rest of the post. I just assumed the SCLs work best mirroring each other but interesting to know they can independently push bandwidth. From my AIDA results above I think it looks like copy bandwidth could be improved. Read seems OK but I'm sure I've seen some people at 596xx at 3800 meaning scope for improvement.

And again with the 1.8v CPU line I thought that was mostly for stability. I've had it on 1.83v previously but reverted it when giving up on 1T pure. Will look at it again now if it can actually improve scaling.

DD's I thought pretty much floored at 4/6 and 4/6 on DR, I've seen SR bottomed out at all 1's. I'll have a look at them as well if they can theoretically go lower on DR.


----------



## tomzyka

tomzyka said:


> View attachment 2523038
> 
> 
> I'm going to do a test with Karhu tomorrow and see how it goes












Well that was a quick test... idk what do to honestly, maybe changing tWRRD to 3 but still weird that it runs 30 cycles TM5 and fails after 2 mins Karhu. I would really appreciate it if someone could help me with that


----------



## Audioboxer

tomzyka said:


> View attachment 2523186
> 
> 
> Well that was a quick test... idk what do to honestly, maybe changing tWRRD to 3 but still weird that it runs 30 cycles TM5 and fails after 2 mins Karhu. I would really appreciate it if someone could help me with that


Have you tried running flat 14's just to check stability? Also, try 1.53~1.54v on VDIMM.

With it erroring that quick on Karhu should be quick to test.

I've never used Karhu before so is it possible it picks up on CPU instability as well? TM5 seems to crash on cores but keep running unable to finish with CPU issues, maybe Karhu knows to bring up an error?


----------



## ManniX-ITA

tomzyka said:


> Well that was a quick test... idk what do to honestly, maybe changing tWRRD to 3 but still weird that it runs 30 cycles TM5 and fails after 2 mins Karhu. I would really appreciate it if someone could help me with that


Did you try with CPU Cache disabled in Kahru?
Probably not a memory issue if TM5 can pass 30 cycles.


----------



## tomzyka

Audioboxer said:


> Have you tried running flat 14's just to check stability? Also, try 1.53~1.54v on VDIMM.


Only with 2t and without setup times, that wasn't a problem. The exact same settings on 2t (tRDWR/tWRRD 9/3, CsOdtDrvStr 30 and no setup times) run perfectly fine with no errors in Karhu (tested until 15000%). But these settings on 1t are propably too much for the CPU right now :/



ManniX-ITA said:


> Did you try with CPU Cache disabled in Kahru?
> Probably not a memory issue if TM5 can pass 30 cycles.


No not yet, I will do it after the next test. I'm trying my luck with tRDWR/tWRRD 10/3 right now, 9/3 got an error after 6645% and 10/4 after 91% but yea it's propably too much strain on the CPU somewhere


----------



## Audioboxer

tomzyka said:


> Only with 2t and without setup times, that wasn't a problem. The exact same settings on 2t (tRDWR/tWRRD 9/3, CsOdtDrvStr 30 and no setup times) run perfectly fine with no errors in Karhu (tested until 15000%). But these settings on 1t are propably too much for the CPU right now :/
> 
> 
> No not yet, I will do it after the next test. I'm trying my luck with tRDWR/tWRRD 10/3 right now, 9/3 got an error after 6645% and 10/4 after 91% but yea it's propably too much strain on the CPU somewhere


Have you got custom PBO values and a curve setup? If so, remove the curve and auto out all other CPU values. Try it again then.

You've got me interested in trying out Karhu now lol.


----------



## tomzyka

Audioboxer said:


> Have you got custom PBO values and a curve setup? If so, remove the curve and auto out all other CPU values. Try it again then.
> 
> You've got me interested in trying out Karhu now lol.


No I have just set PBO to manual and set the default PPT/TDC/EDC values (142/95/140) and I set a positive offset of 2000mA for the CPU Core Current Telemetry to get the 100% CPU Power Reporting Deviation during Cinebench, that's it


----------



## Audioboxer

tomzyka said:


> No I have just set PBO to manual and set the default PPT/TDC/EDC values (142/95/140) and I set a positive offset of 2000mA for the CPU Core Current Telemetry to get the 100% CPU Power Reporting Deviation during Cinebench, that's it


For testing sake I would auto that all out, aka, return to bios defaults, just for a quick test. Best to rule everything out.


----------



## ManniX-ITA

tomzyka said:


> No I have just set PBO to manual and set the default PPT/TDC/EDC values (142/95/140) and I set a positive offset of 2000mA for the CPU Core Current Telemetry to get the 100% CPU Power Reporting Deviation during Cinebench, that's it


I would set PBO to Disabled and no telemetry and test again with Kahru.


----------



## tomzyka

Audioboxer said:


> For testing sake I would auto that all out, aka, return to bios defaults, just for a quick test. Best to rule everything out.





ManniX-ITA said:


> I would set PBO to Disabled and no telemetry and test again with Kahru.


Thank you guys for your help, really appreciate it! I'll try that and keep you updated


----------



## Audioboxer

tomzyka said:


> Thank you guys for your help, really appreciate it! I'll try that and keep you updated


I know I had some issues with TM5 timing out until I made adjustments to my PBO curve so I know testing memory can find CPU instabilities. So it's worth trying it. PBO values, especially default ones like above really shouldn't be an issue. I don't know enough about the second thing you adjusted, so if it's going to be anything I would guess that.

If I knew more about Karhu I could maybe give more input about it erroring that quickly, but I've never tried it before and just seen its 10 euros. When TM5 seems to do the job for free I guess it's "better"  Though I probably will buy it later just because I see it often used and it seems a good piece of software.


----------



## mongoled

The TM5 timing out issue is a strange one, I also think it happens when other applications grab memory away from TM5 when it's running.

I say this because I dont see this occuring on my benchOS, but when I boot into my workOS and run TM5 it does it quite often and when I've seen it happen it's when TM5 is going to the next cycle.

BenchOS vs WorkOS are also using different chipset drivers also...


----------



## Audioboxer

mongoled said:


> The TM5 timing out issue is a strange one, I also think it happens when other applications grab memory away from TM5 when it's running.
> 
> I say this because I dont see this occuring on my benchOS, but when I boot into my workOS and run TM5 it does it quite often and when I've seen it happen it's when TM5 is going to the next cycle.
> 
> BenchOS vs WorkOS are also using different chipset drivers also...


You could have a good point here, I'm notorious for just benching/stability testing as is with Windows and while I don't like bloat my taskbar/notification area has 16 icons in it lol. 16. Probably why when I use AIDA under normal circumstances my latency can be like 2~3 higher than it is in safe mode.

While I was passing core-cycler and y-cruncher it just so happens when I changed my curve it did seem to help stop the TM5 timeouts.


----------



## MrHoof

For those running tCWL 12 @tCL 15 does it actuly improve performance over lower tRDWR? For me tCWL 14 and tRDWR 8 perform better then tCWL 12 tRDWR 10. Diffrence is about 150mb read and copy on aida.


----------



## Audioboxer

MrHoof said:


> For those running tCWL 12 @tCL 15 does it actuly improve performance over lower tRDWR? For me tCWL 14 and tRDWR 8 perform better then tCWL 12 tRDWR 10. Diffrence is about 150mb read and copy on aida.


I'll test that tomorrow. 12/10 doesn't actually post for me. At least it doesn't post on my current timings.

This was my AIDA on 12/12










One thing I actually thought is my read should be able to go a bit higher. So we'll see!


----------



## MrHoof

Audioboxer said:


> I'll test that tomorrow. 12/10 doesn't actually post for me. At least it doesn't post on my current timings.


ye I am on 16GB single rank if for you with tCWL 12 tRDWR 12 is lowest that boots then 14/10 would probably work too, as far as I know u wanna keep tCWL at a even number thats why 13 is out of question.

so close to getting to 58gb read.


----------



## lmfodor

KedarWolf said:


> Here is me at 1usmus_v3 at 1000%, 8 cycles. I attached my .cfg, just rename it, remove the .txt to use it.
> 
> View attachment 2522673


Hi @KedarWolf, I hope you are doing well. I'm still using your timings and they are working very well from long time ago. I noticed that you changed the tRTP to 21 and before you were using 19. What was the reason? Just to learn. Your config works very well with my memorys. From your original timings I changed the AddCmdSetup to 56 to enable 1T GDM off and CkeSetup to 12 and tCKE to 16, that allow a lower latency in serveral tests (copyright @ManniX-ITA )  These are my current timings and the benchs. The latency is high because I had a lot of services.










PS: I'm still using 3003 BIOS. For some strange reason, when I tried 3701 or even 3801 BIOS, my read speed went down to the half.. I don't know why. I will try again..Very weird..


----------



## lmfodor

ManniX-ITA said:


> I meant the Advanced tab in Kahru
> 
> But that's interesting as well.
> You should enable C-State as said by @Veii.
> And set also Power Supply Idle Control to Auto or Low otherwise it will not go to the lower state.
> Had stability issues with DPM control in manual with this specific BIOS I'm using now, so maybe it's worth checking if Auto makes a difference.


Hi @ ManniX-ITA, so long! As a general rule of thumb, always disable C-States and also set PSU Idle to typical power, because if I didn't you had a lot of cold reboots. I'm still on an old SMU (56.37) that has more "boost" and "not broken L3 cache?". In that version, should I enable C-States and set the PSU idle control to Low? What happened to me with AMD is that to gain performance and stability, I had to read and touch a lot of things to avoid WHEA, reboots, 41 events ... you know, all the known problems of AMD in this last generation. At some point I got tired of touching so many things and following the rules of the forums without a deep knowledge of the subject. I go through every single thing I try to optimize. PBO with curve optimizer, Memories where I never managed to exceed the 1933 FCLK and then play fine with the CCD / IOD values. It becomes quite difficult for those who want to get performance and stability out of it, right? 
I know that you and Veii developed a lot the theme of the C-States and the power plans .. the peaks and the hibernation modes, which for me are all broken. Should I upgrade to the latest version of BIOS Agesa 1.203 Patch C? It's worth it? Excuse a question with a little frustration. There came a time when I couldn't follow you! Thanks as always for your help.


----------



## gled_fr

Updated bios with latest 1.2.0.3 Patch C, same everything as before, just loaded previous profile, seems like I lost .2ns :/

I'll check stability in a few.

Vdimm still at 1.46V:


----------



## lmfodor

gled_fr said:


> Updated bios with latest 1.2.0.3 Patch C, same everything as before, just loaded previous profile, seems like I lost .2ns :/
> 
> I'll check stability in a few.
> 
> Vdimm still at 1.46V:
> View attachment 2523275


Very good results! What's your VDIMM? 1.5v? 
Thanks!


----------



## KedarWolf

lmfodor said:


> Hi @KedarWolf, I hope you are doing well. I'm still using your timings and they are working very well from long time ago. I noticed that you changed the tRTP to 21 and before you were using 19. What was the reason? Just to learn. Your config works very well with my memorys. From your original timings I changed the AddCmdSetup to 56 to enable 1T GDM off and CkeSetup to 12 and tCKE to 16, that allow a lower latency in serveral tests (copyright @ManniX-ITA )  These are my current timings and the benchs. The latency is high because I had a lot of services.
> 
> View attachment 2523270
> 
> 
> PS: I'm still using 3003 BIOS. For some strange reason, when I tried 3701 or even 3801 BIOS, my read speed went down to the half.. I don't know why. I will try again..Very weird..


Oh, I went back to 19-21, I was just testing something.


----------



## ManniX-ITA

Nice to read you again 



lmfodor said:


> Should I upgrade to the latest version of BIOS Agesa 1.203 Patch C? It's worth it?


I really don't know, depends on the motherboard.
Both the GB Master and the Unify-X releases have been a huge disappointment with any 1.2.0.3 for me.
Especially the Master with the 3800x, real mess.
But I see many others have been luckier than me, especially on the Master with a 5000.



lmfodor said:


> Memories where I never managed to exceed the 1933 FCLK and then play fine with the CCD / IOD values.


FCLK higher than 1900 is very tricky.
I managed to find the correct values comparing a good GB5 run at FCLK 1900 with one at higher FCLK.
If the voltages are not right some test score will drop dramatically, 20-30%, while others bumping up the same.
When you get all the tests above 95% at least, most of them above 100% compared to FCLK 1900 then you got the voltages right.



lmfodor said:


> As a general rule of thumb, always disable C-States and also set PSU Idle to typical power, because if I didn't you had a lot of cold reboots. I'm still on an old SMU (56.37) that has more "boost" and "not broken L3 cache?". In that version, should I enable C-States and set the PSU idle control to Low?


Unless very specific conditions, is always better to have C-States enabled. Otherwise the clock boosting will be limited.
The PSU idle seems to have an impact on how low the processor power state can go. I wasn't able to verify it.
For me it's a matter of general stability and especially resume from standby.
What I'm pretty sure about now is that the behavior is linked to the chipset drivers.

I've been always perfectly stable with ErP Enabled and PSU Idle to Typical.
But with the latest chipset drivers this has changed.
Same issue on GB Master with different releases and the Unify-X where I still run with the same old BIOS, the A21O.

Now I'm only stable with ErP Disabled and PSU Idle to Low.
Otherwise I get random reboots/memory related BSODs and black screen/disk corruption at standby resume.
If you still have stability issues it's worth a try testing older chipset drivers (2.13 or early 2.16)


----------



## lmfodor

ManniX-ITA said:


> Nice to read you again
> 
> 
> 
> I really don't know, depends on the motherboard.
> Both the GB Master and the Unify-X releases have been a huge disappointment with any 1.2.0.3 for me.
> Especially the Master with the 3800x, real mess.
> But I see many others have been luckier than me, especially on the Master with a 5000.
> 
> 
> 
> FCLK higher than 1900 is very tricky.
> I managed to find the correct values comparing a good GB5 run at FCLK 1900 with one at higher FCLK.
> If the voltages are not right some test score will drop dramatically, 20-30%, while others bumping up the same.
> When you get all the tests above 95% at least, most of them above 100% compared to FCLK 1900 then you got the voltages right.
> 
> 
> 
> Unless very specific conditions, is always better to have C-States enabled. Otherwise the clock boosting will be limited.
> The PSU idle seems to have an impact on how low the processor power state can go. I wasn't able to verify it.
> For me it's a matter of general stability and especially resume from standby.
> What I'm pretty sure about now is that the behavior is linked to the chipset drivers.
> 
> I've been always perfectly stable with ErP Enabled and PSU Idle to Typical.
> But with the latest chipset drivers this has changed.
> Same issue on GB Master with different releases and the Unify-X where I still run with the same old BIOS, the A21O.
> 
> Now I'm only stable with ErP Disabled and PSU Idle to Low.
> Otherwise I get random reboots/memory related BSODs and black screen/disk corruption at standby resume.
> If you still have stability issues it's worth a try testing older chipset drivers (2.13 or early 2.16)


Hi, what it is ErP? I just enabled CStates, left PSU in Auto and disabled DFStates and testing last AGESA. I have a Dark Hero, but I guess with almost an Year with these processors we all share a common CPU parameters. I mean , for instance should we enable Preferred Cores? Is there any specific parameter that could affect cold reboots? I think most AMD user disabled Cstates for lack of knowledge. 

If I had to build a PC again I would definitely go for Intel. I can't believe it takes so long and these BSODs or cold reboots issues continues. I just looked at my event viewer and I have at least 2 errors 41 per month. They almost go unnoticed. But I come with errors since December. I know the BIOS parameters almost by heart. I think we should have a set of recommended parameters. It can't be that complex

Thanks Mannix!


Sent from my iPhone using Tapatalk Pro


----------



## PJVol

*@mongoled*
Remember increasing GEMM scores from run to run in your tests? 





















And look at the two bottom test in GB5 multi test, its 5600X and 5700G compared at 3800CL15 and 4000CL15 respectively.


----------



## mongoled

PJVol said:


> *@mongoled*
> Remember increasing GEMM scores from run to run in your tests?
> View attachment 2523289


The AI is out to get us 

😂😂

Until we understand how the GEMM test works I think we should discount it


----------



## mongoled

Have you noted the pattern that L3 cache takes a latency hit when we push FCLK ?

PLL18 "fixes" the L3 latency hit somewhat and improves performance elsewhere such as LinxXtreme etc etc


----------



## PJVol

Yep, l3 is the culprit (i think) of all those out of normal scaling order results. Some instructions seem to really stress it in a power restricted scenarios.


----------



## mongoled

PJVol said:


> Yep, l3 is the culprit (i think) of all those out of normal scaling order results. Some instructions seem to really stress it in a power restricted scenarios.


Have you tested different EDC values regards high FCLK and L3 cache latency?


----------



## PJVol

You mean, does it help to ease throttling?
Aida usually show some improvement in a 11.0 - 10.4ns range with a 5600X, not only L3, but also ram latency, regardless of FCLK clock set.
Gonna check, how 5700g will behave. Just get it back to "msi-home" , since an office-pc needs a CPU asap, after 3600x retirement )


----------



## mongoled

PJVol said:


> You mean, does it help to ease throttling?


well first to determine if there is a clear pattern/relationship and hence seeing if it effects throttling, which we are pretty sure it does


----------



## Audioboxer

Might seem like a silly question but is there tangible benefit to dropping tRCDWR lower? I see quite a lot of people drop it to 8~10, but others just run flat timings.


----------



## mongoled

Audioboxer said:


> Might seem like a silly question but is there tangible benefit to dropping tRCDWR lower? I see quite a lot of people drop it to 8~10, but others just run flat timings.


Bigger epeen

 🤣 😂


----------



## Audioboxer

mongoled said:


> Bigger epeen
> 
> 🤣 😂


Well, yes, welcome to the world of overclocking  

Just wondering, legitimately, if it actually does anything. Your brain thinks lowering a timing = benefit, but with some memory timings also lowering something = potential instability for little or no gain


----------



## ManniX-ITA

Audioboxer said:


> Just wondering, legitimately, if it actually does anything.


I remember that I've tested it once and yes it does make a difference.
But not that big, it's the delay introduced to switch the active row.
Especially the RW is very subtle with synthetic benchmarks like AIDA.
AIDA Write & Copy benchmarks of course.
Probably easier to spot the effect if you set it abnormally high.
It does have a big impact on specific workloads where small chunks are accessed over a very large dataset in memory.

BTW if you didn't noticed latest HWInfo introduced CPU IOD Hotspot temperature monitoring.
Not sure how reliable it is... only peaking 38.4c while CCDs topped 79c, seems a bit low.


----------



## mongoled

Anyone want a stable tRCDRD @14 @3800mhz?

Easy peasy, just increase tRDRDSC to 2 from 1

😊

But.... but..... there is a huge performance hit on L1 read bandwidth

😂😂


----------



## Mach3.2

Audioboxer said:


> Might seem like a silly question but is there tangible benefit to dropping tRCDWR lower? I see quite a lot of people drop it to 8~10, but others just run flat timings.


There's measurable increase in AIDA write bandwidth in my setup. But how much does it actually matter in the real world, I have no idea. 🙃


----------



## Audioboxer

Mach3.2 said:


> There's measurable increase in AIDA write bandwidth in my setup. But how much does it actually matter in the real world, I have no idea. 🙃


We don't do real world around here, just pretty numbers on benchmarks


----------



## ManniX-ITA

mongoled said:


> But.... but..... there is a huge performance hit on L1 read bandwidth


Hit on L1 is weird... I'll try that


----------



## mongoled

Mach3.2 said:


> There's measurable increase in AIDA write bandwidth in my setup. But how much does it actually matter in the real world, I have no idea. 🙃


See, thats the thing, we are using AIDA64 but the results are run to run variance and the changes made to tRCDRW fall within this variance.

So I choose to use timings that I have an idea on where they "fit in" in the bigger picture of keeping things "synced" rather than add another unknown variance into the equation.

Dropping something like tRAS, tRC has a clearer effect in things other than AIDA64 so I would much rather add unknowns to things that clearly effect performance compared to something that may effect performance


----------



## domdtxdissar

mongoled said:


> See, thats the thing, we are using AIDA64 but the results are run to run variance and the changes made to tRCDRW fall within this variance.
> 
> So I choose to use timings that I have an idea on where they "fit in" in the bigger picture of keeping things "synced" rather than add another unknown variance into the equation.
> 
> Dropping something like tRAS, tRC has a clearer effect in things other than AIDA64 so I would much rather add unknowns to things that clearly effect performance compared to something that may effect performance


Careful now, the next thing you know people will say you hate aida64.. 

(ive been told more then once that i hate both TestMEM and Aida because i don't think they can/should be used as a "performance metric/index" between different systems)


----------



## Audioboxer

mongoled said:


> Anyone want a stable tRCDRD @14 @3800mhz?
> 
> Easy peasy, just increase tRDRDSC to 2 from 1
> 
> 😊
> 
> But.... but..... there is a huge performance hit on L1 read bandwidth
> 
> 😂😂


So you're saying there is a chance to run tRCDRD 14 with _ease_? I'm on it! 🤣










But what I'm actually going to do first is "for science" give that 8 a 25 cycle.

Funnily enough I can't post 14/8 on tCWL/tRDWR. Seems to need a 14/9 or 14/10. tRFC is kind of at its limit now for 1.5v.


----------



## mongoled

Audioboxer said:


> So you're saying there is a chance to run tRCDRD 14 with _ease_? I'm on it! 🤣
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But what I'm actually going to do first is "for science" give that 8 a 25 cycle.
> 
> Funnily enough I can't post 14/8 on tCWL/tRDWR. Seems to need a 14/9 or 14/10. tRFC is kind of at its limit now for 1.5v.


Actually there may be a use for settings tRDRDSC to 2 and that is to enable you to get the right settings for powering the dimms, but thats about it 



Am on the 10th cycle and have had one error 4, nothing else.

Going to stop it now as the hit to L1 read bandwidth is real, 40x00 vs 57x00 mbytes/s


----------



## PJVol

ManniX-ITA said:


> Hit on L1 is weird...


Actually, memory read is hit.


----------



## Audioboxer

mongoled said:


> Actually there may be a use for settings tRDRDSC to 2 and that is to enable you to get the right settings for powering the dimms, but thats about it
> 
> 
> 
> Am on the 10th cycle and have had one error 4, nothing else.
> 
> Going to stop it now as the hit to L1 read bandwidth is real, 40x00 vs 57x00 mbytes/s


Yeah I'm even a bit lukewarm on returning to my 14 profile at the moment. 15 keeps my boys on tPHYRDL 26, performance is pretty good in benchmarks and I guess if I have a stab at 1T pure again it _might _be a bit more successful on tCL15.

Plus I set myself a goal of 1.5v max on this profile. Not for any cooling reasons, just a goal on the basis of wanting to run less with tCL15 than 14. Only roof I've hit so far is where tRFC can be dropped to.

But wherever I get to with secondary timings and voltages on my 15 profile I'll see if most transfer over to 14.


----------



## tomzyka

I got really hyped yesterday after my settings reached 10000% with Karhu...


Spoiler: Karhu 10000%















decided to test them with 25 cycles TM5 and reality hit me right in my face


Spoiler: TM5 Error 15















After the Karhu run yesterday I really thought tRDWR/tWRRD 10/3 would be the key but apparently it's still not stable (I did not touched anything in Bios and tested with CPU cache enabled in Karhu). Well the good thing is that the errors in Karhu with the previous settings were probably not cpu related. I'm still confused that all the previous settings were TM5 stable and couldn't pass Karhu and exactly this setting that can pass Karhu is not TM5 stable


----------



## Audioboxer

tomzyka said:


> I got really hyped yesterday after my settings reached 10000% with Karhu...
> 
> 
> Spoiler: Karhu 10000%
> 
> 
> 
> 
> View attachment 2523324
> 
> 
> 
> 
> decided to test them with 25 cycles TM5 and reality hit me right in my face
> 
> 
> Spoiler: TM5 Error 15
> 
> 
> 
> 
> View attachment 2523325
> 
> 
> 
> 
> After the Karhu run yesterday I really thought tRDWR/tWRRD 10/3 would be the key but apparently it's still not stable (I did not touched anything in Bios and tested with CPU cache enabled in Karhu). Well the good thing is that the errors in Karhu with the previous settings were probably not cpu related. I'm still confused that all the previous settings were TM5 stable and couldn't pass Karhu and exactly this setting that can pass Karhu is not TM5 stable


Even after multiple explanations of how tCKE works from Veii I'm still iffy on it lol but maybe just try leaving it at 1? Also I might have said to you already but bumping CsOdtDrvStr to 24 or 30 won't hurt. I run it at 30 just now and haven't tried to lower it as of yet. With you running ProcODT 34.3 like me it might need to be higher.

I might be talking out of my ass but I believe CsOdt is one of the resistances that helps lower ProcODT if you bump it up a notch or two from 20. 36.9 is quite common as standard for DR it seems so with you lowering to 34.3 that is why I'm thinking a bit more CsOdt might help minor instability.


----------



## tomzyka

Audioboxer said:


> Even after multiple explanations of how tCKE works from Veii I'm still iffy on it lol but maybe just try leaving it at 1? Also I might have said to you already but bumping CsOdtDrvStr to 24 or 30 won't hurt. I run it at 30 just now and haven't tried to lower it as of yet. With you running ProcODT 34.3 like me it might need to be higher.
> 
> I might be talking out of my ass but I believe CsOdt is one of the resistances that helps lower ProcODT if you bump it up a notch or two from 20. 36.9 is quite common as standard for DR it seems so with you lowering to 34.3 that is why I'm thinking a bit more CsOdt might help minor instability.


CsOdtDrvStr at 30 works like a charm on my 2t sets, 40/20/30/20 is the key. But the value of 30 on 1t resulted in a PCB Crash (Error 4) on a previous test. CsOdtDrvStr at 24 resulted in Error 5 with my previous tRDWR/tWRRD values at 9/3 while these values with CsOdtDrvStr at 20 were perfectly fine. But you are right, with my new tRDWR/tWRRD values at 10/3, CsOdtDrvStr at 24 could work. I will give it a shot, so thanks for that!
If that won't work I can try tCKE at 1 instead of 8. Thank you a lot for your input, I really appreciate it.


----------



## Audioboxer

tomzyka said:


> CsOdtDrvStr at 30 works like a charm on my 2t sets, 40/20/30/20 is the key. But the value of 30 on 1t resulted in a PCB Crash (Error 4) on a previous test. CsOdtDrvStr at 24 resulted in Error 5 with my previous tRDWR/tWRRD values at 9/3 while these values with CsOdtDrvStr at 20 were perfectly fine. But you are right, with my new tRDWR/tWRRD values at 10/3, CsOdtDrvStr at 24 could work. I will give it a shot, so thanks for that!
> If that won't work I can try tCKE at 1 instead of 8. Thank you a lot for your input, I really appreciate it.


Also try ProcODT at 36.9 if you think you're going to have to stay on 20. I remember someone earlier in the topic saying they had to switch from 34.3 to 36.9 to get 1T stable.


----------



## Audioboxer

Veii or anyone else, looking for some knowledge again lol. tPHYWRL, what would trigger this from a 7 to 9? Noticed it was 7 earlier, its 9 now during a stability test I'm running.

tPHYWDL is still at 26, just RL that has changed. I presume 9 is "slower"?

*edit* - Interesting, it was changing tCWL/tRDWR to 14/9. So 12/12 gets me tPHYWRL 7, but 14/9 is tPHYWRL 9. Unfortunately, I can't seem to boot 14/8. Unless it's one of my other secondary timings preventing 14/8?


----------



## MrHoof

Audioboxer said:


> Veii or anyone else, looking for some knowledge again lol. tPHYWRL, what would trigger this from a 7 to 9? Noticed it was 7 earlier, its 9 now during a stability test I'm running.
> 
> tPHYWDL is still at 26, just RL that has changed. I presume 9 is "slower"?
> 
> *edit* - Interesting, it was changing tCWL/tRDWR to 14/9. So 12/12 gets me tPHYWRL 7, but 14/9 is tPHYWRL 9. Unfortunately, I can't seem to boot 14/8. Unless it's one of my other secondary timings preventing 14/8?


That one thing i wanted to find out too, tPHYWRL 9 changes to 7 with tCWL12. But still I seem to get slightly better resulst with lower tRDWR. Is there any other advantage to gain with lower tCWL? Basicly tCWL is the last timing i could still run tighter but unsure if it is worth it.

Also i think DR is what limits you to tRDWR 9.


----------



## PJVol

TOP URGENT !
Is anyone got a clue, could this MX-4 remnants be the reason for the boot stuck at 98 post code ?
All conventional solutions weren't help. This happened after switching from 5700g back to 5600x.
.


----------



## Audioboxer

PJVol said:


> TOP URGENT !
> Is anyone got a clue, could this MX-4 remnants be the reason for the boot stuck at 98 post code ?
> All conventional solutions weren't help. This happened after switching from 5700g back to 5600x.
> .
> View attachment 2523361


In theory, no, as the paste should be non-conductive. IIRC boot code 98 is something at the final stages of initialisation, though someone can correct me if wrong. You're going to need to test with 1 memory stick and possibly test reseating CPU/trying old CPU again. Check for damaged or bent pins on CPU. 

Possibly it's also the video handshake issues that sometimes come up. Try running an HDMI cable from your graphics card to monitor instead of display port if you're using display port.


----------



## PJVol

Audioboxer said:


> In theory, no,


Yep, you're right. Cleaning pcb didn't help.

Forgot to mention, one weird thing happened as of yesterday.
Recently, after updating to the latest agesa 1.2.0.3c bios, there was a message right before windows logon, something like "you won't be able to get back to prev. firmware,... etc", ok, flashed and forgot it.

But yesterday, after switching CPU to 5700g, another message appeared, saying
"New CPU installed. Do I want to keep fTPM settings or reset module. Y/N?".
I entered "N", which got me back to the same message after reboot.
Then I answered "Y" and somehow managed to boot successfully and disabled "secure boot". But there was more in the message, like "had I answer 'N', I can switch back to my old cpu".

Just curious, was it meant, that now I can't put my 5600X back and code 98 has something to do with TPM?  ffs...


----------



## PJVol

Wow, after 5th attempt, look what was appeared on the screen, lol ))
I am not sure, what answer is correct, and I have nothing encrypted on my PC (i think so  )
And the POST led says 98)). It seems it was always so with this code, just monitor didn't catch up with GPU display PHY.

So which answer is correct, does anyone know?


----------



## Mach3.2

Have you tried reflashing your BIOS?

Not the same situation, but when I swapped CPUs, I couldn't get fTPM to work until I reflashed my BIOS. Restoring defaults didn't help at all for some weird reason.


----------



## PJVol

Mach3.2 said:


> Have you tried reflashing your BIOS?


No, I haven't. I just don't need fTPM to work until update to win11 sometimes in the 2022, may be summer 
Anyway, to proceed I need to enter something and leaning to "Y" atm ...

UPD:
Well, did push "Y" and booted successfully. OMG, what a mess all this TPM/PSP/and God-knows-what-else they trying to shove in ...


----------



## gled_fr

Audioboxer said:


> *edit* - Interesting, it was changing tCWL/tRDWR to 14/9. So 12/12 gets me tPHYWRL 7, but 14/9 is tPHYWRL 9. Unfortunately, I can't seem to boot 14/8. Unless it's one of my other secondary timings preventing 14/8?


Curious about the bench diff between 14/9 and 12/12.
I do boot 14/8 here. 12/8 no way. Might give a try to 12/12 after the current stability test.

Still working on 1.2.03 patch C bios changes ( from 1.2.0.3 patch A ):

same settings as before, latency goes to 54.8 instead of 54.6ns ( [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread )
harmonizing trtp to 5 because twr is 10, and setting trfc to 260 from 258 (obviously trfc2 and 4 set accordingly too) because trfc needs to be divided as integer with trtp gets 54.7ns. TRFC 255 gets a single error 10 and a single 3 on the long 60cycles test, far into the test.
still testing stability and need to work on that further, but upping vdimm to 1.5 from 1.46 and setting trfc to 245 ( and again trfc2/4 accordingly ) from point above seems to get back the 54.6ns latency [EDIT: stability testing at 1.495 vdimm now, 1.5 vdimm did one error 4, and I want to avoid as much as possible having to find a new procodt/rtt/drvstr balance]

Stupid that going from patch A to patch C, same settings I lost 0.2ns and that I have to up vdimm to regain that. At least I have trtp and twr going together, which I missed previously.


----------



## micsway

Hi,

I have a question about Rtt. Was told that 6-3-3 was optimal for dual rank setups with particular regards to temps. I wanted to test this out and found auto ran cooler. Keen to get peoples input on this.


ran TM5 for 10min without a fan so excuse the errors please:

Rtt 6 3 3 = Avg temp 51.4/51.3 Max temp = 54.4/54.4
Rtt d 3 1 = Avg temp 49.9/49/9 Max temp 53.1/53.1 (auto)

prior to these two runs I did a 10min warm up run to heat up the sticks to avoid cold start.


----------



## gled_fr

micsway said:


> Hi,
> 
> I have a question about Rtt. Was told that 6-3-3 was optimal for dual rank setups with particular regards to temps. I wanted to test this out and found auto ran cooler. Keen to get peoples input on this.


If I understood correctly, it's not only the RTTs, but also vdimm/procodt/drvstr. those works together.


----------



## ioannis91

Hello guys. I am getting low L3 scores in aida64 even though I am on AGESA 1.2.0.2. Mobo is B450 Tomahwak (non MAX), cpu is on PBO (125w, 75A, 95A), no CO, no AutoOC. RAM has passed all the usual testing (TM5, y-cruncher, OCCT, you name it). Any help on this?


----------



## ManniX-ITA

micsway said:


> Keen to get peoples input on this.


You need to get rid of the errors before you can compare temperatures.


----------



## mongoled

ioannis91 said:


> Hello guys. I am getting low L3 scores in aida64 even though I am on AGESA 1.2.0.2. Mobo is B450 Tomahwak (non MAX), cpu is on PBO (125w, 75A, 95A), no CO, no AutoOC. RAM has passed all the usual testing (TM5, y-cruncher, OCCT, you name it). Any help on this?
> View attachment 2523467
> 
> View attachment 2523468


If you have not tweaked your EDC values then the score you are getting are exactly where they should be.

If you want the L3 cache to reach 600 Gb/s you need to raise EDC to 500+


----------



## ioannis91

mongoled said:


> If you have not tweaked your EDC values then the score you are getting are exactly where they should be.
> 
> If you want the L3 cache to reach 600 Gb/s you need to raise EDC to 500+


the stock EDC is 90A and I have seen that with 95A I am getting the best all-core frequencies. Anything over or under 95A gives worst all-core. I am talking more about the L3 latency though.


----------



## mongoled

ioannis91 said:


> the stock EDC is 90A and I have seen that with 95A I am getting the best all-core frequencies. Anything over or under 95A gives worst all-core. I am talking more about the L3 latency though.


Im sorry, but I cant make this more clearer for you.

If you want your L3 cache throughput to be higher you need to change EDC to be 500+ (experiment, you may need 400+ it varies...)

With EDC at 90/95A your throughput is where it should be.

Hope you understand ...


----------



## ManniX-ITA

ioannis91 said:


> I am talking more about the L3 latency though.


L3 latency is linearly dependent on Core 0 frequency clock.
You need to achieve higher clock and have a cooling that can keep it sustained for the whole duration of the test to get a better result.










This is the L3 latency test running on my 5950x.

Another reason for bad L3 latency could be a bloated Windows install, you need to close everything to get a good result.
Got 11.2ns on main install so I did a quick check on the BenchOS to verify there wasn't an issue with the settings.
Different AGESA version also produces very different results, I'm using 1.2.0.1 release.

This is with EDC at 245A:


----------



## Audioboxer

gled_fr said:


> Curious about the bench diff between 14/9 and 12/12.
> I do boot 14/8 here. 12/8 no way. Might give a try to 12/12 after the current stability test.
> 
> Still working on 1.2.03 patch C bios changes ( from 1.2.0.3 patch A ):
> 
> same settings as before, latency goes to 54.8 instead of 54.6ns ( [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread )
> harmonizing trtp to 5 because twr is 10, and setting trfc to 260 from 258 (obviously trfc2 and 4 set accordingly too) because trfc needs to be divided as integer with trtp gets 54.7ns. TRFC 255 gets a single error 10 and a single 3 on the long 60cycles test, far into the test.
> still testing stability and need to work on that further, but upping vdimm to 1.5 from 1.46 and setting trfc to 245 ( and again trfc2/4 accordingly ) from point above seems to get back the 54.6ns latency [EDIT: stability testing at 1.495 vdimm now, 1.5 vdimm did one error 4, and I want to avoid as much as possible having to find a new procodt/rtt/drvstr balance]
> 
> Stupid that going from patch A to patch C, same settings I lost 0.2ns and that I have to up vdimm to regain that. At least I have trtp and twr going together, which I missed previously.


I'll try and get you some benches later. I noticed Veii say many pages ago that testing had shown it's better to go with a lower tRDWR than lower tCWL. So I'd presume if you can boot 14/8 you're in the best position. I've noticed quite a few people can boot 14/8, so I don't know if my IMC is just not good enough or if there is any other timings I need to look at to help boot 14/8.

Interestingly I just noticed at 14/8 your tPHYWRL is at 9. I would have guessed it would be at 7. I still don't really know what this timing is/does, no one answered me earlier, but I just assumed lower would be better lol. You can maybe go to 12/12 and boot into windows and see if it drops to 7. If it does I guess a lower tCWL drops it down???

@Veii I tried dropping VDDP and CDD lower whilst increasing IOD a bit, this passed 25 cycles










What is the Vermeer recommended voltage window just so I know I don't go too low, if there is a low to high window Vermeer expects?

*edit* - I found this AMD max overclocking voltage



> CCDs have positive scaling with low voltage and low VDDP (CPU VDDP)
> IMC remains to have positive scaling with low voltage and so better signal integrity
> VDDG IOD remains to have the same scaling like Matisse, while it feels comfortable near 980-1080mV
> VDDG CCD has negative scaling beyond 950-980mV. It has positive scaling sub 940mV. Down to 850mV
> SOC has a big range 980-1280mV


----------



## ioannis91

mongoled said:


> Im sorry, but I cant make this more clearer for you.
> 
> If you want your L3 cache throughput to be higher you need to change EDC to be 500+ (experiment, you may need 400+ it varies...)
> 
> With EDC at 90/95A your throughput is where it should be.
> 
> Hope you understand ...


Yeah I got it. EDC goes as high as 168A on my mobo and with 168A I am getting a bit under 600GB/s L3 cache scores. But I leave it on 95A cause the all core score is better.


----------



## mongoled

ioannis91 said:


> Yeah I got it. EDC goes as high as 168A on my mobo and with 168A I am getting a bit under 600GB/s L3 cache scores. But I leave it on 95A cause the all core score is better.


Unfortunately thats the way it goes..... good though you have seen the impact for yourself on the L3 cache throughput


----------



## ioannis91

ManniX-ITA said:


> L3 latency is linearly dependent on Core 0 frequency clock.
> You need to achieve higher clock and have a cooling that can keep it sustained for the whole duration of the test to get a better result.
> Another reason for bad L3 latency could be a bloated Windows install, you need to close everything to get a good result.
> Got 11.2ns on main install so I did a quick check on the BenchOS to verify there wasn't an issue with the settings.
> Different AGESA version also produces very different results, I'm using 1.2.0.1 release.


I have a noctua u12s which keeps it cool during the test. Core 0 is not my best core so it clocks lower I guess. Windows install is new, I did a format 4 days ago. Thanks for the answer!
I just checked and the thing is that core0 boosts to 4650MHz (effective clock) as it should, but still 11.2-11.4ns latency..


----------



## ManniX-ITA

Audioboxer said:


> *edit* - I found this AMD max overclocking voltage


IMO, this post is pretty old and recent AGESA versions behavior can be quite different.

These CCD voltage recommendations are more relevant for 1CCD.
Also every sample can have a very different range of CCD voltage that works better.
With 2 CCDs it's usually +50/100mV more than that.
My 5950x bottom CCD voltage is 950mV. Below that I can't boot, BSODs or audio crackling/USB issues/awful performances.
Can't even run at 950mV, audio crackling.
Mine scales positively up to 1020-1050mV at FCLK 1900 and 1080-1100mV for FCLK 1900+.

There's also a relation with CO and how low you can go with counts.
My sample is average, good samples that can go very low with counts seems to work fine with lower CCD voltage.


----------



## Audioboxer

ManniX-ITA said:


> IMO, this post is pretty old and recent AGESA versions behavior can be quite different.
> 
> These CCD voltage recommendations are more relevant for 1CCD.
> Also every sample can have a very different range of CCD voltage that works better.
> With 2 CCDs it's usually +50/100mV more than that.
> My 5950x bottom CCD voltage is 950mV. Below that I can't boot, BSODs or audio crackling/USB issues/awful performances.
> Can't even run at 950mV, audio crackling.
> Mine scales positively up to 1020-1050mV at FCLK 1900 and 1080-1100mV for FCLK 1900+.
> 
> There's also a relation with CO and how low you can go with counts.
> My sample is average, good samples that can go very low with counts seems to work fine with lower CCD voltage.


Yeah I thought 8 months ago, that's a long time with AMD BIOS lol. What is the best way to test CCD voltage stability?










I'm assuming possibly not TM5 if it runs OK? Just passed the quick 3 cycle here on 0.9v. I presume better to do CPU testing like OCCT, Prime95 and corecycler?

No audio crackling so far, though I'm just testing YouTube videos. I do have an external USB DAC that handles my audio.


----------



## ManniX-ITA

Audioboxer said:


> Yeah I thought 8 months ago, that's a long time with AMD BIOS lol. What is the best way to test CCD voltage stability?


Stability at least 4 cycles, better more, of y-cruncher stress test.
For performance scaling I use GB5, looking at single score AES-XTS.
When CCD is too high or too low the score drops.


----------



## Audioboxer

ManniX-ITA said:


> Stability at least 4 cycles, better more, of y-cruncher stress test.
> For performance scaling I use GB5, looking at single score AES-XTS.
> When CCD is too high or too low the score drops.


My 25 cycle above was at 0.925v, but I'll give this 0.9v 4 cyces of y-cruncher just to see what happens. But as you've pointed out performance dropping is a bigger concern than "appears to be stable at this voltage". What is GB5?


----------



## Mach3.2

Geekbench 5


----------



## ManniX-ITA

Audioboxer said:


> My 25 cycle above was at 0.925v, but I'll give this 0.9v 4 cyces of y-cruncher just to see what happens. But as you've pointed out performance dropping is a bigger concern than "appears to be stable at this voltage". What is GB5?


Geekbench 5:










I'd suggest to make different runs with each CCD voltage and compare them online.
You can set a baseline and compare side-by-side the results.
Wrong CCD is clearly reflected on AES-XTS but also on other tests.
Around 4300-4500 is the desired range.


----------



## Audioboxer

ManniX-ITA said:


> Geekbench 5:
> 
> View attachment 2523497
> 
> 
> I'd suggest to make different runs with each CCD voltage and compare them online.
> You can set a baseline and compare side-by-side the results.
> Wrong CCD is clearly reflected on AES-XTS but also on other tests.
> Around 4300-4500 is the desired range.












Good news is it didn't crash, bad news is it does seem a bit low at 0.9v. Now to try higher.

Though in terms of issues not sure what this is about










I just booted up the app and ran the CPU benchmark, didn't change anything else.

*edit* -










0.925v results in slightly higher AEX-XTS but more importantly










Going to guess if I ran y-cruncher on 0.9v it would be unstable. I do need to test y-cruncher with 0.925v as well, but for one test to be invalid and the other valid with the only thing changed CCD voltage, it seems it's that.

My PBO is just 270/160/190 so it might not be totally optimal for my chip. Kind of just left it there, figured out a curve and moved over to more seriously getting memory sorted first.










0.95v










0.975v

I think I've found my 'ceiling' with current PBO settings. 4330 looks to be where I am right now. 0.9v seems to be unstable, only bench that came back invalid. 0.925v seems like it might be OK. 0.95v/0.975v has been y-cruncher tested.

Improving my GB5 scores seems like it would now come down to getting better PBO settings/better curve.

Thanks for name-dropping GB5. I have heard of it, but never used it before.


----------



## sonixmon

micsway said:


> Hi,
> 
> I have a question about Rtt. Was told that 6-3-3 was optimal for dual rank setups with particular regards to temps. I wanted to test this out and found auto ran cooler. Keen to get peoples input on this.
> 
> 
> ran TM5 for 10min without a fan so excuse the errors please:
> 
> Rtt 6 3 3 = Avg temp 51.4/51.3 Max temp = 54.4/54.4
> Rtt d 3 1 = Avg temp 49.9/49/9 Max temp 53.1/53.1 (auto)
> 
> prior to these two runs I did a 10min warm up run to heat up the sticks to avoid cold start.


You might need active cooling to push that far. In order for me to get CL14 and low trfc I had to add a fan to the RAM. It helped and I can get OC stable but the ram can actually go farther with better cooling (i.e. when it is cool in room). End of summer has been hot here so I had to make two profiles for OC. Only other option would be to add custom loop and tie in ram, but I do not plan to do that.
My kit doesnt like to be above 42-44 for extreme OC or 48 for tight timings.


----------



## Audioboxer

sonixmon said:


> You might need active cooling to push that far. In order for me to get CL14 and low trfc I had to add a fan to the RAM. It helped and I can get OC stable but the ram can actually go farther with better cooling (i.e. when it is cool in room). End of summer has been hot here so I had to make two profiles for OC. Only other option would be to add custom loop and tie in ram, but I do not plan to do that.
> My kit doesnt like to be above 42-44 for extreme OC or 48 for tight timings.


Can confirm. If I let my RAM go above 42 degrees to like 46-48 I can start getting errors in TM5. With a fan on a high RPM I can keep it around 40. TM5 pushes ram higher temp than normal usage but it's better to get things passing in TM5 so you have a thermal overhead during normal use.

I've got a 2 DIMM board and I'm considering picking up this for my loop 30.41US $ 10% OFF|Bykski RAM Water Cooling Block use for Dual Channel 2pcs RAM Cooled / Copper Cooled RGB Radiator|Fans & Cooling| - AliExpress

Other brands don't seem to stock their 2 DIMM coolers any more.


----------



## mongoled

Audioboxer said:


> Can confirm. If I let my RAM go above 42 degrees to like 46-48 I can start getting errors in TM5. With a fan on a high RPM I can keep it around 40. TM5 pushes ram higher temp than normal usage but it's better to get things passing in TM5 so you have a thermal overhead during normal use.
> 
> I've got a 2 DIMM board and I'm considering picking up this for my loop 30.41US $ 10% OFF|Bykski RAM Water Cooling Block use for Dual Channel 2pcs RAM Cooled / Copper Cooled RGB Radiator|Fans & Cooling| - AliExpress


You worked out that your RAM is A0 PCB ?

If its A2 PCB then you may want to go with different RAM heatsinks as those in the pictures does not look like it will cover the RAM modules entirely..

I now have the EK Monarch that are a much better product than the Alphacool ramsinks I originally purchased that did not cover the RAM modules entirely ..


----------



## Audioboxer

mongoled said:


> You worked out that your RAM is A0 PCB ?
> 
> If its A2 PCB then you may want to go with different RAM heatsinks as those in the pictures does not look like it will cover the RAM modules entirely..
> 
> I now have the EK Monarch that are a much better product than the Alphacool ramsinks I originally purchased that did not cover the RAM modules entirely ..
> 
> View attachment 2523508


I actually posted my RipJaws under the spoiler on this post [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

No who knows how to identify commented, I couldn't find Veii's post telling me how to identify previously and I just kind of left it there lol. If those pictures are good enough maybe someone can help now or let me know where to look again for how to identify.

Funny thing is the default RipJaws heatsinks are pretty crap when it comes to covering the whole RAM lol. Should make it easier for identifying though!


----------



## mongoled

Audioboxer said:


> I actually posted my RipJaws under the spoiler on this post [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> No who knows how to identify commented, I couldn't find Veii's post telling me how to identify previously and I just kind of left it there lol. If those pictures are good enough maybe someone can help now or let me know where to look again for how to identify.
> 
> Funny thing is the default RipJaws heatsinks are pretty crap when it comes to covering the whole RAM lol. Should make it easier for identifying though!


Just a couple of pages back ManniX-ITA posted the images you need to compare to!









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


These are my old settings (ram only stable under 42c) I have not run on new settings just yet. Aha! I see! Doesn't look much better than mine, so I think mine's in line with what it should be. Thanks a bunch for calming me down! :D Any reason not to take the free AIDA64Extreme one year licence...




www.overclock.net


----------



## Audioboxer

mongoled said:


> Just a couple of pages back ManniX-ITA posted the images you need to compare to!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> These are my old settings (ram only stable under 42c) I have not run on new settings just yet. Aha! I see! Doesn't look much better than mine, so I think mine's in line with what it should be. Thanks a bunch for calming me down! :D Any reason not to take the free AIDA64Extreme one year licence...
> 
> 
> 
> 
> www.overclock.net


Excellent thanks, I'll take the modules out and have a look.

Those appear to be A layouts, are B layouts for DR not different?










Y-cruncher seems to be going fine so far with VDDG CCD at 0.925v.


----------



## mongoled

Audioboxer said:


> Those appear to be A layouts, are B layouts for DR not different?


Unsure, someone with DR will need to chime in!

On a side note 4066/2033 has decided to boot up more reliably now

😂😂

Hopefully will be able to tweak it to a stable profile as 4133/2067 is too much of a stretch to use as a 24/7 settings ...


----------



## Audioboxer

mongoled said:


> Unsure, someone with DR will need to chime in!
> 
> On a side note 4066/2033 has decided to boot up more reliably now
> 
> 😂😂
> 
> Hopefully will be able to tweak it to a stable profile as 4133/2067 is too much of a stretch to use as a 24/7 settings ...


That's why I was hunting for the Veii post, IIRC they mentioned to me that both sides needed looked at to properly identify a DR PCB.

Also, jeeez, IF is wild with what it will boot but GL getting stable!

Typhoon Burner says B1 (8 layers) but it's notoriously wrong with PCBs.


----------



## mongoled

Audioboxer said:


> That's why I was hunting for the Veii post, IIRC they mentioned to me that both sides needed looked at to properly identify a DR PCB.
> 
> Also, jeeez, IF is wild with what it will boot but GL getting stable!
> 
> Typhoon Burner says B1 (8 layers) but it's notoriously wrong with PCBs.


Ammendment, should have said post (not boot!).

Have not seen anywhere a detailed explanation of the memory training settings which could be helpful in error 07 scenarios..


----------



## tolis626

So, as I keep reading this thread, I kept getting the feeling that my RAM should've been performing a bit better with my current settings, but I kept getting 55.0-55.5ns of latency in Aida64. Turns out, it's just my bloated Windows installation. Ran a test in safe mode and these are the results.








I think I'm good on memory.


----------



## Audioboxer

tolis626 said:


> So, as I keep reading this thread, I kept getting the feeling that my RAM should've been performing a bit better with my current settings, but I kept getting 55.0-55.5ns of latency in Aida64. Turns out, it's just my bloated Windows installation. Ran a test in safe mode and these are the results.
> View attachment 2523526
> 
> I think I'm good on memory.


Yeah Windows under normal operating with apps in the background can probably add anywhere from 1~3.0 ns to results. It's nice to know more clearly where your baseline is 

At the end of the day no one is sitting in safe mode with nothing running during day to day use, but when a lot of results get posted online people are either in safe mode, cut down windows installations and/or have all background apps closed.

If you're on DR 2x16GB I think anywhere between 54~55 ns seems pretty average/good, especially if running with a 5xxx chip. It's my understanding some of the 5xxx chips, especially the 5950x can add a little bit of latency.


----------



## MrHoof

@Audioboxer no WHEA with those low CDD voltages? Any lower than 1.025v and I start to get WHEA at fclk 1900.

edit: nvm I am stupid, was thinking off IOD


----------



## tolis626

Audioboxer said:


> Yeah Windows under normal operating with apps in the background can probably add anywhere from 1~3.0 ns to results. It's nice to know more clearly where your baseline is
> 
> At the end of the day no one is sitting in safe mode with nothing running during day to day use, but when a lot of results get posted online people are either in safe mode, cut down windows installations and/or have all background apps closed.
> 
> If you're on DR 2x16GB I think anywhere between 54~55 ns seems pretty average/good, especially if running with a 5xxx chip. It's my understanding some of the 5xxx chips, especially the 5950x can add a little bit of latency.


Yeah, figured out as much. I just needed to know that my system wasn't performing poorly for the set timings. If it did, I would've done something wrong. But it's about in line with what I'd expect now. The bloat I need adding 1-1.5ns of latency is acceptable to me.

Other than that, I'm not running DR. My kit is 2x8GB SR. I know it should be able to do better, but it's been hell trying to figure out what was wrong before and why I got errors, so I'm not optimizing my timings further as of yet. 3800C14 should be able to get like in the 52-53ns range, but meh.


----------



## Audioboxer

MrHoof said:


> @Audioboxer no WHEA with those low CDD voltages? Any lower than 1.025v and I start to get WHEA at fclk 1900.
> 
> edit: nvm I am stupid, was thinking off IOD


Just finished a run at 0.95v on IOD










No WHEA either










My last WHEA errors are from days ago when I was briefly messing around with booting 2000 FCLK.

Other changes from last 25 cycle were VSOC dropped 1 notch, CCD at 0.925v, VDDP at 0.86v. I auto'd out tWRRD just to see where it chose to go, 1, then just to try it out I dropped my DD's by 2 each. 4->2 and 6->4. Might try and see if SDs can come down now.

My TM5 run has come in a few minutes quicker. Used to getting around 2 hours 43 minutes.

Not really sure if I should be trying to drop voltages any lower, 0.9v on CCD seemed to get me a GB5 error. But it's quite fun as well to play the game of voltage dropping 

*edit* - No WHEA at 0.925v on IOD either










No WHEA at 0.9v on IOD either lol










In theory how low should IOD be able to run at something like 1900 FCLK?


----------



## spajdr

Just for info, latest W11 preview version have L3 cache speed mostly fixed.


----------



## mongoled

tolis626 said:


> but it's been hell trying to figure out what was wrong before and why I got errors, so I'm not optimizing my timings further as of yet. 3800C14 should be able to get like in the 52-53ns range, but meh





mongoled said:


> tolis626 said:
> 
> 
> 
> Thanks for the insight!
> 
> That said, I know for a fact that my RAM will run no problem at 3800MHz with flat 15s for timings (1T, GDM off, taken from the 3800MHz fast profile of Ryzen DRAM Calculator) at under 1.45V. It was running like that for almost a year on my 3800x, tested multiple times with no issues. I am using that as my baseline. I just had never dared to push my luck with higher clocks or tighter timings, because I thought I wouldn't be able to do 3800MHz CL14 and anything above 1900MHZ fclk would fail on my 3800X.
> 
> Now, if what I'm currently testing fails too, I'll give a higher tRCDRD a shot, see where it takes me. 2T failed just as quickly as 1T, so I think that my problem isn't with the primary timings. Hmmm...
> 
> Well, I paid money for Karhu, so I'm getting my money's worth, damn it!
> 
> In all seriousness, I've grown to like this little tool a lot. I mean, it found issues where HCI had failed to do so, it does so quickly and it does so conveniently. I haven't used TM5, but any time I thought I'd give it a shot, it was all in Russian and I didn't even bother downloading it. I don't know what it is, but there's something about writter Russian that stresses me out.
> 
> Having said that, if I can't find any solution to my problems with Karhu, I'll give it a shot, maybe it'll give me some pointers. Thanks for the suggestion!
> 
> 
> 
> 
> 
> 
> mongoled said:
> 
> 
> 
> Here is the direct link
> 
> 
> 
> https://testmem.tz.ru/tm5.rar
> 
> 
> 
> Run the program as admin, then close it
> 
> Go into the bin folder and delete the cfg.link file
> 
> Then open the Mt.cfg file with notepad, find the word "Cycles" and change it to 25.
> 
> Now when you run it it will be for 25 cycles.
> 
> Then add the line
> 
> Test Sequence=6,12,2,10,5,1,4,3,0,13,9,14,7,8,1,11,15
> 
> Save and close the file.
> 
> Any error codes that pop up post them here
> 
> 
> 
> Click to expand...
Click to expand...

You never got back to me

☺

Could have made your life easier

😂

One day you will return to it (tighter timings) and running TM5 and seeing the error codes will help us attempt to diagnose the issue

😊


----------



## MrHoof

Audioboxer said:


> In theory how low should IOD be able to run at something like 1900 FCLK?


no idea but my last test must have been flawed in someway, now the WHEA start at 0.925
I guess more testing to do on the weekend.


----------



## Audioboxer

MrHoof said:


> no idea but my last test must have been flawed in someway, now the WHEA start at 0.925
> I guess more testing to do on the weekend.
> View attachment 2523556


Oooft, that's some low VDDP!

You should check low CCD with GeekBench 5 like I did. When I went to 0.9v my AES-XTC score under single core seemed to be held back. Was better at 0.925v.


----------



## tolis626

mongoled said:


> You never got back to me
> 
> ☺
> 
> Could have made your life easier
> 
> 😂
> 
> One day you will return to it (tighter timings) and running TM5 and seeing the error codes will help us attempt to diagnose the issue
> 
> 😊


OOPS  

Hahaha sorry mate, I just didn't end up using TM5. I have it saved, I'm going to try it once I start pushing my RAM again. But I just needed a break after having to deal with error after error after error. But the fact that I'm happy with it now doesn't mean that I won't go for better timings. I want to squeeze every last bit of performance on my system, always have, always will. I remember the painstaking process of overclocking the RAM on my old rig with a 4790k. Took me a while to figure out that I couldn't go above 2200MHz without raising vSA, then it took forever to realize that my DIMMs just didn't like voltage all that much. I could do 2400MHz 10-12-12-26 1T (IIRC) at 1.6V. Same settings would cause errors at 1.65V. Maybe it was heat, but I never had a reading in that system to know. Still, these DIMMs had been through a lot. And it was worth it. My 4790k was for some reason only stable at 4.8GHz once RAM was overclocked too, otherwise I was stuck at 4.7GHz. And weirdly, I could do 4.8GHz on the same voltage as 4.7GHz needed without the RAM overclock. It was a weird chip, but with everything overclocked it took the first Ryzens and the 8th gen to make it feel old and outdated.


----------



## MrHoof

AES-XTC singlecore 4310 +-5 from stock to 0.95v. Gonna run those voltage over the weekend and lookout for stutters or audio crackling.








edit: WHEA 19 with IOD 0.95v/1.05v SOC also with stock SOC 1.1v while gaming. Gonna test individual first with stock SOC and push IOD +25mv higher when I see WHEA pop up or get audio crackling and then go back to SOC.


----------



## Yviena

Are the L3 Cache benchmarks from aida64 valid in win11 or are they bugged?


----------



## Audioboxer

Testing IOD at 0.925v and I thought might as well drop the tRCDWR to 8 and tWTRS to 3. Not sure what else I can really lower now lol. Up next might just be trying 1T pure again.


----------



## MrHoof

Audioboxer said:


> Testing IOD at 0.925v and I thought might as well drop the tRCDWR to 8 and tWTRS to 3. Not sure what else I can really lower now lol. Up next might just be trying 1T pure again.


Same kit would always crash at 7% karhu with my old CPU&Motherboard 3600/x570 auros elite. Now with a 2 dimm board and this 5800x it never struggled with 1T.
edit: Maybe asus Optimem does something after all. Most people running 1T without setup I saw using asus boards.


----------



## Audioboxer

MrHoof said:


> Same kit would always crash at 7% karhu with my old CPU&Motherboard 3600/x570 auros elite. Now with a 2 dimm board and this 5800x it never struggled with 1T.
> edit: Maybe asus Optimem does something after all.


I was struggling with TM5 errors on 6/10/12 depending on what resistances I was running at 1T without 56 setup. That was running higher voltages though. Will be interesting to try again with lower voltages and see if I can get the IMC to stop crashing.

DR is a bit harder to get stable at 1T pure than SR I believe. I'm sure if I put some more hours into it I might find the Rtt/ProcODT/resistance combo I need.


----------



## PJVol

I'm not sure, is this result ok or not for my memory sticks... since I have no idea what it should be.
So, does anyone care to clarify?
Vdimm 1.542V


----------



## ManniX-ITA

PJVol said:


> So, does anyone care to clarify?


Maybe @YoungChris could help.


----------



## mongoled

PJVol said:


> I'm not sure, is this result ok or not for my memory sticks... since I have no idea what it should be.
> So, does anyone care to clarify?
> Vdimm 1.542V
> View attachment 2523636
> View attachment 2523637


Are you asking if the results are good with regards to timings or performance ??

I cant give you any insight with regards to performance, but if those are b-dies then you are running very loose timings.









Good looking performance though


----------



## ManniX-ITA

mongoled said:


> I cant give you any insight with regards to performance, but if those are b-dies then you are running very loose timings.


Not sure, it's 1T with GDM Off and FCLK in-sync.
Pretty good IMO at that VDIMM.
FCLK out of sync does not put anywhere near close the same strain as in-sync.
You can boot and bench timings which are impossible with in-sync.

There are a lot of posts from Sparky in the Unify-X thread:









MSI B550 Unify / Unify-X Overclocking & Discussions...


Screw my 5900x's, I may need to get a Renoir...




www.overclock.net





But they are almost all with VDIMM around 1.8-1.9V if I recall correctly.


----------



## mongoled

ManniX-ITA said:


> Not sure, it's 1T with GDM Off and FCLK in-sync.
> Pretty good IMO at that VDIMM.
> FCLK out of sync does not put anywhere near close the same strain as in-sync.
> You can boot and bench timings which are impossible with in-sync.
> 
> There are a lot of posts from Sparky in the Unify-X thread:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> MSI B550 Unify / Unify-X Overclocking & Discussions...
> 
> 
> Screw my 5900x's, I may need to get a Renoir...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> But they are almost all with VDIMM around 1.8-1.9V if I recall correctly.


My understanding is that high FCLK has no effect in what frequency/timings a set of modules can achieve.

I can only guess you are talking about the strain on the CPUs IMC not the DRAM modules.

As ive never had a 5xxxG CPU I cannot talk from experience ..


----------



## ManniX-ITA

mongoled said:


> My understanding is that high FCLK has no effect in what frequency/timings a set of modules can achieve.


It does if it's out of sync; with my 5950x I can boot at FCLK 2067 out-of-sync with timings I can't even POST at the same clock in-sync.
They effectively go from 1/3 to 1/2 slower so low timings works cause they run very slow...
I used to test timings for 4200 MHz in out-of-sync but I realized quickly it's meaningless.
Didn't really read about it somewhere, just what I've learned testing myself.


----------



## mongoled

ManniX-ITA said:


> It does if it's out of sync; with my 5950x I can boot at FCLK 2067 out-of-sync with timings I can't even POST at the same clock in-sync.
> They effectively go from 1/3 to 1/2 slower so low timings works cause they run very slow...
> I used to test timings for 4200 MHz in out-of-sync but I realized quickly it's meaningless.
> Didn't really read about it somewhere, just what I've learned testing myself.


Im not getting my point across very well.

As you have prior experience and I do not I can only follow your advice.

But I believe the reasons for this is not to do with the RAM modules but with what the CPU IMC can handle.

Yes I understand that my point is kinda pointless as what difference does it make if the RAM can handle it but the CPU cannot ...


----------



## ManniX-ITA

mongoled said:


> But I believe the reasons for this is not to do with the RAM modules but what the CPU IMC can handle.


You have to consider the clock of the RAM and the UMC.
The timings are defining the rate/cadence/timing at which the UMC issues the DDR commands.
When the MCLK is 2200 (DDR 4400) and UCLK is 1100 that means that every odd clock tick a command is skipped.
It's like instead of running at 1T runs at 2T, instead of 2T runs at 4T.
But the delta is even more bigger as it's like all timings are doubled.
The RAM itself has double the time to process everything.
Still not correct but it's grossly like running those timings at the UCLK instead of the MCLK.


----------



## RosaPanteren

ManniX-ITA said:


> IMO, this post is pretty old and recent AGESA versions behavior can be quite different.
> 
> These CCD voltage recommendations are more relevant for 1CCD.
> Also every sample can have a very different range of CCD voltage that works better.
> With 2 CCDs it's usually +50/100mV more than that.
> My 5950x bottom CCD voltage is 950mV. Below that I can't boot, BSODs or audio crackling/USB issues/awful performances.
> Can't even run at 950mV, audio crackling.
> Mine scales positively up to 1020-1050mV at FCLK 1900 and 1080-1100mV for FCLK 1900+.
> 
> There's also a relation with CO and how low you can go with counts.
> My sample is average, good samples that can go very low with counts seems to work fine with lower CCD voltage.


Thank you @ManniX-ITA 

Turns out I've probably been running to low on CCD(0.95-0.98v) and perhaps a bit low on IOD.

How do you go about vsoc, keeping it in a range of min. 40-50mv from IOD voltage?

Any tip on finding cldo_vddp sweetspot or is it just to go as low as stability allow?


----------



## mongoled

RosaPanteren said:


> Thank you @ManniX-ITA
> 
> Turns out I've probably been running to low on CCD(0.95-0.98v) and perhaps a bit low on IOD.
> 
> How do you go about vsoc, keeping it in a range of min. 40-50mv from IOD voltage?
> 
> Any tip on finding cldo_vddp sweetspot or is it just to go as low as stability allow?


If vSOC is too low you will see LinpackXtreme GFlops dropping

Depends how high you are pushing FCLK/MCLK frequency.

For example for me to push 4133/2067 I need close to 1.3v and IOD 1.1v so obviously out of the 40-50mv range ...


----------



## ManniX-ITA

RosaPanteren said:


> How do you go about vsoc, keeping it in a range of min. 40-50mv from IOD voltage?


I keep it at least at 60mV from IOD. Had issues at 50mV.
Depends on the whole profile settings but going up will steal something from the power budget.
But if you need it, tight RAM timings/huge PBO limits/high FCLK, at the end can give you higher performances.



RosaPanteren said:


> Any tip on finding cldo_vddp sweetspot or is it just to go as low as stability allow?


Depends on the RAM modules, the timings, on the specific CPU sample, the AGESA, so many things.
With the latest AGESA releases didn't find any advantage going higher or lower than 900mV.
For a relaxed configuration going lower it's possible but I didn't see any practical advantage.
Used to run at 850/880mV with the 3800x long time ago but then only had stability issues with it.



mongoled said:


> If vSOC is too low you will see LinxXtreme GFlops dropping


Correct, very intensive CPU workload in general.
Also needed for tight timings on RAM; higher vSOC and IOD supports high bandwidth and low latency transfer on IF.


----------



## Audioboxer

My 1T pure story, again, in a few images










THE 12's, ALL THE 12's 










RttNom to 6, let's go! .... Triple 6's please 










ClkDrvStr 60, it's your time to shine, 1 minute and we have..... 12 again 










A little bit of voltage you say, some more ProcODT you say? Enter.... 10 

Conclusion? Screw 1T pure, come back to me AddrCmdSetup 56



















That'll do, that'll do


----------



## mongoled

Audioboxer said:


> My 1T pure story, again, in a few images
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> THE 12's, ALL THE 12's
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> RttNom to 6, let's go! .... Triple 6's please
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ClkDrvStr 60, it's your time to shine, 1 minute and we have..... 12 again
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> A little bit of voltage you say, some more ProcODT you say? Enter.... 10
> 
> Conclusion? Screw 1T pure, come back to me AddrCmdSetup 56
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> That'll do, that'll do


With 12's you are at the boarderline of what the dimms can handle, only thing ive found that shows some improvement is balancing the powering of the dimms (Rtts) with the vDIMM you are running along with finding the correct ProcODT.

Ive managed to eliminate the 12s for my 4067/2033 flat 15s profile but am now stuck on the 10s

🤣🤣

Increasing tWR is not helping at all, hopefully I can stumble on the correct combination of settings as performance is nice, dont see any USB issues, no sound distortion issues, no GFlops reduction issues (before anyone asks, there are WHEA 19s of course 😂😂).

Only issue other than getting it TM5 stable is getting it to post reliably, setting "PMU Pattern bits" to 1 seems to have helped but thats going against the recommended 6-10.


----------



## Veii

mongoled said:


> My understanding is that high FCLK has no effect in what frequency/timings a set of modules can achieve.
> 
> I can only guess you are talking about the strain on the CPUs IMC not the DRAM modules.
> 
> 
> 
> ManniX-ITA said:
> 
> 
> 
> FCLK out of sync does not put anywhere near close the same strain as in-sync.
> You can boot and bench timings which are impossible with in-sync.
Click to expand...

2167 for example are easier to stabilize on 2:1 mode
But 1:1 mode is hard ~ it functions but CPU package throttles

2:1 mode does help against the strain, and signal integrity is cleaner
But it does not affect if low tRCD can be benched
It only does affect how "low" of vdimm you can use - but yet not how "well" dimms can scale

Better signal integrity can equally happen ~ if your powersuply is better - or spread spectrum is on, to combat EMI
Depends on many factors,
But ~ 2:1 mode does not "help" in running absurd timings. Either you can or you can not. It only lowers minimum voltage needed for it by a tiny bit

The same story goes back to 1T vs 2T
tRCD won't wiggle just because it's 2T 
Either it works, or it doesn't


----------



## Audioboxer

mongoled said:


> With 12's you are at the boarderline of what the dimms can handle, only thing ive found that shows some improvement is balancing the powering of the dimms (Rtts) with the vDIMM you are running along with finding the correct ProcODT.
> 
> Ive managed to eliminate the 12s for my 4067/2033 flat 15s profile but am now stuck on the 10s
> 
> 🤣🤣
> 
> Increasing tWR is not helping at all, hopefully I can stumble on the correct combination of settings as performance is nice, dont see any USB issues, no sound distortion issues, no GFlops reduction issues (before anyone asks, there are WHEA 19s of course 😂😂).
> 
> Only issue other than getting it TM5 stable is getting it to post reliably, setting "PMU Pattern bits" to 1 seems to have helped but thats going against the recommended 6-10.


To me now it's just not worth it for 1T pure. I've learned a lot thanks to yourself, Veii and others but I still don't really understand why 1T Pure becomes soo radically unstable compared to using Setups. With the benchmark above in safe mode I think those are respectable numbers for DR and up next for me will be watercooling and trying to squeeze some more out of tRFC. My 245 is pretty much the bottom at 1.5v, even 242 brings issues. More voltage needed for lower.

At this point I don't even know if I managed to get 1T pure stable would it even do much to my benchmark?


----------



## mongoled

@Audioboxer
Forgot to say, may have to try lowering tRCDRW to see if its somehow a sync issue

🤣 😂

Well i did tell you a while ago to forget about it, tRCDRD is where its at

😂 😂


----------



## Veii

Audioboxer said:


> I've learned a lot thanks to yourself, Veii and others but I still don't really understand why 1T Pure becomes soo radically unstable compared to using Setups.


You can focus on trying to get it CKE stable - and if that doesn't work, test all SETUP Timings through from 1 to 32
both have to be identical AddressCommandSetup & Chipselect-OnDieTerminationSetup (CsOdt)

After the half cutting point, it switches to CommandRate like behavior


----------



## Audioboxer

mongoled said:


> @Audioboxer
> Forgot to say, may have to try lowering tRCDRW to see if its somehow a sync issue
> 
> 🤣 😂
> 
> Well i did tell you a while ago to forget about it, tRCDRD is where its at
> 
> 😂 😂


I know you did, it was just a quick attempt again seeing as my main difference from before is running lower VDDP and VDDG and I wanted to see if they somehow lowered stress on the memory. 

tRCDRD I'm not bothered about on 15 profile, 15 obviously works. I guess when I go back to work on my 14 profile I'll have a go again at 14. Such a tease when things boot fine and benchmark, but fail TM5. I much prefer it when they don't post at all and that doesn't give you hope 

I think I might wait till this MSI bios is out of beta before going back to 14 profile. There was some comments that the C patch was screwing around with some peoples memory.


----------



## mongoled

Just messing with you



BETA, non BETA, very rarely there is a difference in my past experience with regards to what you are hoping for

:/

Here is where I am stuck

After each cycle, bing, up pops the 10s

🤣🤣


----------



## Audioboxer

Veii said:


> You can focus on trying to get it CKE stable - and if that doesn't work, test all SETUP Timings through from 1 to 32
> both have to be identical AddressCommandSetup & Chipselect-OnDieTerminationSetup (CsOdt)
> 
> After the half cutting point, it switches to CommandRate like behavior


Is that the likes of tCKE 9 3-3-15. I tried that once and got a BSOD when loading up TM5. I gave up there as I didn't really know what else to change the tCKE value to


----------



## mongoled

Veii said:


> You can focus on trying to get it CKE stable - and if that doesn't work, test all SETUP Timings through from 1 to 32
> both have to be identical AddressCommandSetup & Chipselect-OnDieTerminationSetup (CsOdt)
> 
> After the half cutting point, it switches to CommandRate like behavior


Stop giving him hope

😂😂😂


----------



## Veii

mongoled said:


> Here is where I am stuck
> 
> After each cycle, bing, up pops the 10s
> 
> 🤣🤣


^^
Why do you run tCKE 16 - does it just work ?








Wouldn't 12 work better ?
Could be something simple as badly timed tCKE, on the end of each round


----------



## Veii

mongoled said:


> Stop giving him hope
> 
> 😂😂😂


Sadly i can not help much with 1T DR
Maybe soon
Hope is always good. Accepting failure is not good


----------



## Audioboxer

Veii said:


> Sadly i can not help much with 1T DR
> Maybe soon
> *Hope is always good. Accepting failure is not good*


Shhh, I had finally accepted it 

And yes, the day you work on DR will be a good day 

Whilst I have your attention Veii, what is the way to determine a DR PCB again? mongoled linked me to the A0-1-2 diagrams but I'm sure you once pointed out both sides of the DR memory need to be looked at?

I have some old pictures here from when I got the memory



















Might be a bit blurry to tell but if you could please remind me how to tell I can take the sticks out later and check for myself 










Typhoon just has the pretty generic B1 (8 layers).


----------



## mongoled

Veii said:


> ^^
> Why do you run tCKE 16 - does it just work ?
> 
> 
> 
> 
> 
> 
> 
> 
> Wouldn't 12 work better ?
> Could be something simple as badly timed tCKE, on the end of each round


I ended up leaving tCKE on AUTO as I had previously tried the recommended values but found that it was increasing L1 memory latency over 1ns

** shrugs **



Veii said:


> Sadly i can not help much with 1T DR
> Maybe soon
> Hope is always good. Accepting failure is not good


Hope is good, though I wouldn't describe it as accepting failure, sometimes failure is acceptable because maybe it was "not the right time" for you to succeed


----------



## Veii

Audioboxer said:


> Whilst I have your attention Veii, what is the way to determine a DR PCB again? mongoled linked me to the A0-1-2 diagrams but I'm sure you once pointed out both sides of the DR memory need to be looked at?
> 
> I have some old pictures here from when I got the memory


A and B series are identical
but B series only is recognizable from the Main side
Soo you have to figure out which side is the main side. Stickers do not tell the truth

Speaking about figuring out,
This is B3 ?!
Are you sure it's dual rank at all, or could it be 2048mb chips

You can recognize Rev.3 by having long direct traces. "Super short" traces
As A1 & A2 are "short" trace layout - yet have curvatures.

A1 is not always for ECC . ECC chip can be gone and yet the PCB be valuable.
Do not mistake this please 
A1 was known for running very low timings, while A2 was known to need more current ~ in order to even function
A2 was rather designed for Higher MT/s , and be more resilient ~ yet caused many problems on low quality boards. As the strain by them (required) is higher.

EDIT:
As for ultra-short trace layout
I would strongly consider abandoning DR RTTs ~ and go with something as weak as possible
Traces appear very direct - i think it should be very sensitive to voltage changes


----------



## Audioboxer

Veii said:


> A and B series are identical
> but B series only is recognizable from the Main side
> Soo you have to figure out which side is the main side. Stickers do not tell the truth
> 
> Speaking about figuring out,
> This is B3 ?!
> Are you sure it's dual rank at all, or could it be 2048mb chips
> 
> You can recognize Rev.3 by having long direct traces. "Super short" traces
> As A1 & A2 are "short" trace layout - yet have curvatures.
> 
> A1 is not always for ECC . ECC chip can be gone and yet the PCB be valuable.
> Do not mistake this please
> A1 was known for running very low timings, while A2 was known to need more current ~ in order to even function
> A2 was rather designed for Higher MT/s , and be more resilient ~ yet caused many problems on low quality boards. As the strain by them (required) is higher.
> 
> EDIT:
> As for ultra-short trace layout
> I would strongly consider abandoning DR RTTs ~ and go with something as weak as possible
> Traces appear very direct - i think it should be very sensitive to voltage changes


I have no real idea other than calling it DR because 2x16GB and ZenTimings says DR










And I didn't even know a A3/B3 or... any '3' existed 

Auto on Rtts runs the 'standard' RttNom disabled, RttWr 3, RttPark 1. My other 2x16GB kit runs this. It seems most people with 2x16 get that on auto.

By going with something 'as weak as possible' what would you be referring to? I will of course try it if you could give me some guidance, thanks.

I'm going to switch over to watercooling so I should be able to get some very clear pictures of the whole module in the weeks to come when heatsinks are off.


----------



## Veii

Audioboxer said:


> By going with something 'as weak as possible' what would you be referring to? I will of course try it if you could give me some guidance, thanks.
> I'm going to switch over to watercooling so I should be able to get some very clear pictures of the whole module in the weeks to come when heatsinks are off.


Watercooling can heat up the dimms more than a swapped heatsink with direct air cooling

Something along the lines of 623 or 524
else 604 likely. Who knows they might even run 725

Bioses are neither PCB; nor IC aware


----------



## MrHoof

Audioboxer said:


> At this point I don't even know if I managed to get 1T pure stable would it even do much to my benchmark?


 1T , 1T 56-0-0 , 2T























If u want me to do other benchmarks aswell I can do that just tell me wich.


----------



## Audioboxer

Veii said:


> Watercooling can heat up the dimms more than a swapped heatsink with direct air cooling
> 
> Something along the lines of 623 or 524
> else 604 likely. Who knows they might even run 725
> 
> Bioses are neither PCB; nor IC aware


Thanks, I'll give them all a shot. IIRC I've booted RttPark 4/5 previously, but 5 seemed a bit unstable.

So it might not be DR then? Also what's the lowdown on B3 if it is that? Haven't seen anyone talk about B3, so I guess it might not be as "good" as the others?

Also should I be worried about changing ProcODT or DrvStrs just now or simply play around with Rtts?










I accidentally booted RttPark 6 just there instead of 5 lol



MrHoof said:


> 1T , 1T 56-0-0 , 2T
> View attachment 2523662
> View attachment 2523663
> View attachment 2523664
> 
> 
> If u want me to do other benchmarks aswell I can do that just tell me wich.


Thanks, I did expect 1T pure to be faster with latency, it was just about how much faster. Seems there isn't much in it in which case 1T with Setups is still good


----------



## mongoled

Veii said:


> As for ultra-short trace layout
> I would strongly consider abandoning DR RTTs ~ and go with something as weak as possible
> Traces appear very direct - i think it should be very sensitive to voltage changes


Thank you, thank you, thank you.

As my dimms are A2s just stuck RttPark to RZQ/7 without changing anything else and it didn't throw an error 10 after three cycles!

Let's see how long this holds out

😁

Arghhh

It's just decided to throw some error 13s instead and has nothing to do with overheating.

Back to the balancing act.....


----------



## Veii

Audioboxer said:


> So it might not be DR then? Also what's the lowdown on B3 if it is that? Haven't seen anyone talk about B3, so I guess it might not be as "good" as the others?


There was only one person with Oloy Blade kits, which where A3.
But had a very bad time with 4 of them

Close to non - they are still too rare

You shouldn't trust Benchmarks on unstable results
56 is still SETUP Timing 1T beyond half cutting point = Command Rate similar (not pure 1T)
In order to conclude real difference - both or all 3 examples have to be stable
You can orient to this on my GDM comparison. It has a good 1T vs 2T view. Soo around 0.7ns less. I don't remember
But also 300ish MB/s more bandwidth

While 2T 14-14-14 needed there around 1.53v?
1T needed exactly 1.6v


----------



## mongoled

Veii said:


> There was only one person with Oloy Blade kits, which where A3.
> But had a very bad time with 4 of them
> 
> Close to non - they are still too rare
> 
> You shouldn't trust Benchmarks on unstable results
> 56 is still SETUP timing
> In order to conclude real difference - both or all 3 examples have to be stable
> You can orient to this on my GDM comparison. It has a good 1T vs 2T view. Soo around 0.7ns less. I don't remember
> But also 300ish MB/s more bandwidth


Was going to say the same thing but Veii beat me to it, 2T to 1T has more effect on read throughput than latency...


----------



## Audioboxer

Veii said:


> There was only one person with Oloy Blade kits, which where A3.
> But had a very bad time with 4 of them
> 
> Close to non - they are still too rare
> 
> You shouldn't trust Benchmarks on unstable results
> 56 is still SETUP timing
> In order to conclude real difference - both or all 3 examples have to be stable
> You can orient to this on my GDM comparison. It has a good 1T vs 2T view. Soo around 0.7ns less. I don't remember
> But also 300ish MB/s more bandwidth


Oh well, I guess its fun to be messing around with something with a small sample size.

I edited in above probably before you quoted, but should I worry about ProcODT/DrvStr whilst playing around with Rtts or just try them first?

For example about to run TM5 on










Just because its what you seemed least confident about (7/2/5).

I'll also switch back to 2T to try some benches.


----------



## Veii

mongoled said:


> Was going to say the same thing but Veii beat me to it, 2T to 1T has more effect on read throughput than latency...


Soo seems like the deal happened
less than a month, i should have some DR
Unsure if B3 or Audioboxer was lucky - but it's interesting to know.
Makes me like these 1.45v rated kits now more 


Audioboxer said:


> I edited in above probably before you quoted, but should I worry about ProcODT/DrvStr whilst playing around with Rtts or just try them first?


Usually procODT goes along with cLDO_VDDP
You likely can experiment with tCKE
but you should test what your maximum MCLK is - for RTT_WR
Then decide if /2 is reasonable on higher frequency or not

Either less voltage to begin with - or stronger RTT_NOM with more relaxed RTT_PARK
Generally i think ,unless something is different here ~ these should be easier to power than A1 or A2
You'll figure it out. But matching tCKE and RTT_WR behavior is likely the first priority
Matching all 3, just asks for trouble 
Drop these SETUP timings and go for low MCLK same timings - till you can run 1T and got your powering correct

Would need to look for my 13-13-13 vs 15-15-15 examples, where only 13-13-13 with RTT_WR /2 worked, but higher than 3700+ needed _WR /3 ~ as the PCB was failing
Generally A0's fail beyond 4000 quite fast
Soo i'm bored atm and don't push much. There is not much to push here anymore 
Still working on 2133, but it doesn't move much. Maybe once Hydra is done ~ soo Precision Boost, doesn't bother me much anymore

Hydra 0.7D is fun tho - could have a chance to beat my PBO
At the moment it holds 4.925, with peaks to 4.95
Had to adjust each core individually tho - as the "scan" just had it at 4.75 (weak)
The "red marked showing bottlenecking core" ~ feature is very good 
Just miss SSE and AVX loads split for Per-Core CO
Maybe in the future when i find more time ~ i'd be consider sitting with @1usmus a bit more. It could need some balancing on predictions. But on the core, now is in a usable and potentially PBO beatable state 😇
Only SSE and AVX need more individual tracking & control ~ then it's great


----------



## Audioboxer

Veii said:


> Soo seems like the deal happened
> less than a month, i should have some DR
> Unsure if B3 or Audioboxer was lucky - but it's interesting to know.
> Makes me like these 1.45v rated kits now more












The 7/2/5 got through what I name the "clench your butt 3 cycle" aka "if your memory is really unstable it won't even manage 3 cycles".

Question now is do I leave it for 25 cycles or should I try some other Rtt combinations for 3 cycles before settling on one for a full 25?


----------



## mongoled

Audioboxer said:


> clench your butt 3 cycle


Squeaky bum time

😄 😄


----------



## Audioboxer

mongoled said:


> Squeaky bum time
> 
> 😄 😄


Hahaha, yes, as Sir Alex Ferguson would say. Don't get me wrong I view the 20->25 as squeaky bum time as well. I honestly feel like I should step up to the 50 cycle soon as well.


----------



## mongoled

Audioboxer said:


> Hahaha, yes, as Sir Alex Ferguson would say. Don't get me wrong I view the 20->25 as squeaky bum time as well. I honestly feel like I should step up to the 50 cycle soon as well.


Exactly, Sir is Sir

 

You are getting addicted to TM5

😂 😂


----------



## Audioboxer

mongoled said:


> Exactly, Sir is Sir
> 
> 
> 
> You are getting addicted to TM5
> 
> 😂 😂


The thrill of passing without errors is addictive! I don't even care as much about the benchmarks lol, that TM5 no errors detected is where it is at 😍

Now I feel everything I've learned so far is out the window having to test a lot of Rtt values again! Thank goodness for Veii though and his never-ending knowledge lol.

Going to let the 725 run out, it seems like it's theoretically the "weakest" Rtts Veii suggested to me unless I'm reading it wrong.


----------



## mongoled

Audioboxer said:


> The thrill of passing without errors is addictive! I don't even care as much about the benchmarks lol, that TM5 no errors detected is where it is at 😍
> 
> Now I feel everything I've learned so far is out the window having to test a lot of Rtt values again! Thank goodness for Veii though and his never-ending knowledge lol.
> 
> Going to let the 725 run out, it seems like it's theoretically the "weakest" Rtts Veii suggested to me unless I'm reading it wrong.


Remember thats on the basis that your ram modules have short traces, as per Veii advice.

Am trying 6/2/6....


----------



## Audioboxer

mongoled said:


> Remember thats on the basis that your ram modules have short traces, as per Veii advice.
> 
> Am trying 6/2/6....


Seems likely he's probably right. These 1.45v 14-14-14-14 sets are a new addition to GSKILL given the prior bin was 14-15-15-15. With how "bad" the RipJaw heatsinks are for full coverage it does expose more of the bottom of the sticks.

And I guess if 7/2/5 passes the traces must be shorter? 6 park boots for me so I guess I could try it next.

If you remember my old 2x16GB set I couldn't even boot anything other than RttPark 1 above 3400 lol.


----------



## mongoled

Audioboxer said:


> If you remember my old 2x16GB set I couldn't even boot anything other than RttPark 1 above 3400 lol.


How could I forget

 

6/2/6 turned the 10s into single 2, 3 & 9.

Upping vDIMM by .02 ........


----------



## Audioboxer

mongoled said:


> How could I forget
> 
> 
> 
> 6/2/6 turned the 10s into single 2, 3 & 9.
> 
> Upping vDIMM by .02 ........


Try the 7-2-5 lol, I'm still holding up. Although you're in another ballpark right now with your IF and memory frequency.

Have you noticed watercooling your memory better than a high speed fan then? Veii said to me some posts ago watercooling could result in worse performance than good heatsinks and a fan.


----------



## mongoled

Audioboxer said:


> Have you noticed watercooling your memory better than a high speed fan then? Veii said to me some posts ago watercooling could result in worse performance than good heatsinks and a fan.


I never had a high speed fan but 2 small 80mm fans.

With those I could never push low tRFC stable, with the ram watercooled I can, though I spent a disproportionate amount of money on quality thermal pads to maximise the heat transfer

😆


----------



## Audioboxer

mongoled said:


> I never had a high speed fan but 2 small 80mm fans.
> 
> With those I could never push low tRFC stable, with the ram watercooled I can, though I spent a disproportionate amount of money on quality thermal pads to maximise the heat transfer
> 
> 😆


lol, I love it, spend more on thermal pads than the water block.

I don't mind using the fan but during TM5 testing I do have to crank it to 100% to keep my temps at 40 max. Some better heatsinks might bring that down a bit but if I'm going to pry off the RipJaw heatsinks I'm just thinking I might as well add them to my loop.

It's not expensive if using the Bykski 2 DIMM block but the thermal pads that come with it will probably be pretty poor.

Before I even get it watercooled I guess I best figure out this revision 3 PCB and what Rtts are going to be "best". Might even help me return to 1T pure but I'm not even going to mention that right now


----------



## werks

hello everyone,
i am trying to get tRCDRD 14 stable, but i get hit with alot of error 12/2 and 10.
tRCDRD 15 is stable no errors.
i am running 4x8gb.
has anyone got any tips?


----------



## Audioboxer

werks said:


> hello everyone,
> i am trying to get tRCDRD 14 stable, but i get hit with alot of error 12/2 and 10.
> tRCDRD 15 is stable no errors.
> i am running 4x8gb.
> has anyone got any tips?
> 
> 
> View attachment 2523675


Give up now and work on a flat 15 profile at 3800


----------



## mongoled

werks said:


> hello everyone,
> i am trying to get tRCDRD 14 stable, but i get hit with alot of error 12/2 and 10.
> tRCDRD 15 is stable no errors.
> i am running 4x8gb.
> has anyone got any tips?
> 
> 
> View attachment 2523675


You are at the tRCDRD border, 

there are no tips unfortunately.

All I can tell you is to test your sticks in pairs to determine which dimm cant do tRCDRD @14.

I have four A2 dimms, three of them can do tRCDRD @14 but one cant ....


----------



## Audioboxer

mongoled said:


> You are at the tRCDRD border,
> 
> there are no tips unfortunately.
> 
> All I can tell you is to test your sticks in pairs to determine which dimm cant do tRCDRD @14.
> 
> I have four A2 dimms, three of them can do tRCDRD @14 but one cant ....


This actually reminds me for what it's worth I never actually tried one stick on its own for 14 here....

Anyway, 7/2/5 is now into squeaky bum time at the 20->25 end for me. Almost done!


----------



## Audioboxer

@Veii This passed 25 cycles at 7/2/5 

Not really sure what this tells me though lol. What would you try next? Stick with 7/2/5 or try another combination?


----------



## Veii

Audioboxer said:


> @Veii This passed 25 cycles at 7/2/5
> 
> Not really sure what this tells me though lol. What would you try next? Stick with 7/2/5 or try another combination?


Good job 
Bad prediction appeared to be functioning 
Are DD's auto ?

Get that SETUP timing away and take a look at tCKE . 9 for you
Low RTTs help with heat and you can use more VDIMM now

tCKE will mess up RTTs
I think once RTTs work without SETUP times - then you are fine
Maybe back up to 1-4-4-1-6-6 tWRWR , tRDRD
Also consider to use tWRRD here - at least value 4, or 3

You know, just start with SCL 4-4 , tWRRD 3
Too high tRDWR can also cause issues.
7.5+2 (DR) 9.5 , move in the 10-11 area (give 2 more, we end up at 11.5-12)
soo 11-3, with 1-4-4-1-6-6. If CMOS resets, 12-3,1-5-4-1-7-6

EDIT:
I'd honestly confirm these timing changes with 2T , without SETUP timings
and then see how much VDIMM you need for 1T pure
Consider there, that CAD_BUS 30-20-30-20 or 30-20-24-24 can be needed
last section depends after which point you will have post issues as cLDO_VDDP 860mV is low, soo procODT has to be lower too

Another thing, with low cLDO_VDDP, push the VDD 1.8v line to at least 1.83v
And lower the DRAM VPPM 2.5v line to 2.4v if it allows you


----------



## Audioboxer

Veii said:


> Good job
> Bad prediction appeared to be functioning
> Are DD's auto ?
> 
> Get that SETUP timing away and take a look at tCKE . 9 for you
> Low RTTs help with heat and you can use more VDIMM now
> 
> tCKE will mess up RTTs
> I think once RTTs work without SETUP times - then you are fine
> Maybe back up to 1-4-4-1-6-6 tWRWR , tRDRD
> Also consider to use tWRRD here - at least value 4, or 3
> 
> You know, just start with SCL 4-4 , tWRRD 3
> Too high tRDWR can also cause issues.
> 7.5+2 (DR) 9.5 , move in the 10-11 area (give 2 more, we end up at 11.5-12)
> soo 11-3, with 1-4-4-1-6-6. If CMOS resets, 12-3,1-5-4-1-7-6
> 
> EDIT:
> I'd honestly confirm these timing changes with 2T , without SETUP timings
> and then see how much VDIMM you need for 1T pure
> Consider there, that CAD_BUS 30-20-30-20 or 30-20-24-24 can be needed
> last section depends after which point you will have post issues as cLDO_VDDP 860mV is low, soo procODT has to be lower too
> 
> Another thing, with low cLDO_VDDP, push the VDD 1.8v line to at least 1.83v
> And lower the DRAM VPPM 2.5v line to 2.4v if it allows you


I started running this before you responded just because @mongoled mentioned it lol










Should I try and see if Park is OK at 6?

DDs aren't auto no, I reduced to 2/4 because you mentioned potentially higher bandwidth.


----------



## Veii

Audioboxer said:


> Should I try and see if Park is OK at 6?
> DDs aren't auto no, I reduced to 2/4 because you mentioned potentially higher bandwidth.


Sure

Yes yes, but you aren't in a state where you can afford instability 
They are at the very very end options


----------



## Audioboxer

Veii said:


> Sure
> 
> Yes yes, but you aren't in a state where you can afford instability
> They are at the very very end options


Thanks I'll let this run and then go back to your prior reply and take away setup and loosen up some timings.

If Park 6 looks OK does it need nom 6 or should I have tried 7/2/6?


----------



## sonixmon

MrHoof said:


> 1T , 1T 56-0-0 , 2T
> View attachment 2523662
> View attachment 2523663
> View attachment 2523664
> 
> 
> If u want me to do other benchmarks aswell I can do that just tell me wich.


Thanks for sharing these, I feel much better about Setup 56 now since I cannot post 1T without it (no matter the Latency if above 3200mhz)




werks said:


> hello everyone,
> i am trying to get tRCDRD 14 stable, but i get hit with alot of error 12/2 and 10.
> tRCDRD 15 is stable no errors.
> i am running 4x8gb.
> has anyone got any tips?
> 
> 
> View attachment 2523675


Check your temps, many of us struggle for low (14) trfc etc, over 42-48c.


----------



## sonixmon

You all have me wanting to play with TM5 (I need more spare time!).


----------



## Audioboxer

@Veii 6/2/6 passed as well.

RttPark 7 next?  

I guess the real next move is back to 2T first and prepare to try for 1T without setups?

*edit:* lol, no RttPark 7 doesn't post.










Run something like this based off your older post? I changed those two voltages you asked, one to 1.83v and the other to 2.4v.


----------



## YoungChris

ManniX-ITA said:


> Maybe @YoungChris could help.


What's up?


----------



## mongoled

First attempt at 4066/2033 with tRCDRD @16,

unfortunately tRCDRD @15 is not possible

two error 2s, switched to ProcODT 34.3, lets see if that changes anything


----------



## ManniX-ITA

YoungChris said:


> What's up?


About @PJVol post here:









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


no idea but my last test must have been flawed in someway, now the WHEA start at 0.925 I guess more testing to do on the weekend. Oooft, that's some low VDDP! You should check low CCD with GeekBench 5 like I did. When I went to 0.9v my AES-XTC score under single core seemed to be held back...




www.overclock.net





Good perf for those timings?


----------



## PJVol

@Veii
The professor's opinion is lacking, so wouldn't it really be nice if he deigned to share it? 
Or at least hint to the direction to proceed to.


----------



## Veii

PJVol said:


> @Veii
> The professor's opinion is lacking, so wouldn't it really be nice if he deigned to share it?
> Or at least hint to the direction to proceed to.


Sorry , i can't follow


----------



## Audioboxer

Passed OK @Veii

7 minutes slower than my 1T profile but this is the first time I've tried tCKE 9 so it gives me a new 2T baseline. Is your advice to try to get 1T working from here? DRAM VPPM is at 2.4v. VDD 1.8v is at 1.83v. I'm confident I can switch between 6/2/6 and 7/2/5.


----------



## PJVol

Veii said:


> Sorry , i can't follow


Oh, I should have been clearer, it was refered regarding my post here:








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


no idea but my last test must have been flawed in someway, now the WHEA start at 0.925 I guess more testing to do on the weekend. Oooft, that's some low VDDP! You should check low CCD with GeekBench 5 like I did. When I went to 0.9v my AES-XTC score under single core seemed to be held back...




www.overclock.net




Thought you followed the discussion while responding @mongoled on fclk/uclk sync question )


----------



## Veii

PJVol said:


> Oh, I should have been clearer, it was refered regarding my post here:
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> no idea but my last test must have been flawed in someway, now the WHEA start at 0.925 I guess more testing to do on the weekend. Oooft, that's some low VDDP! You should check low CCD with GeekBench 5 like I did. When I went to 0.9v my AES-XTC score under single core seemed to be held back...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> Thought you followed the discussion while responding @mongoled on fclk/uclk sync question )


Yes yes
But i do not know how APUs scale
Saw a 42-43ns result
It's close to the 4600 result on the Zen RAM Docs

Haven't gotten the 5600G to play with , yet


Audioboxer said:


> Passed OK @Veii
> 
> 7 minutes slower than my 1T profile but this is the first time I've tried tCKE 9 so it gives me a new 2T baseline. Is your advice to try to get 1T working from here? DRAM VPPM is at 2.4v. VDD 1.8v is at 1.83v. I'm confident I can switch between 6/2/6 and 7/2/5.


That's fine, if Aida64 is consistent - go for 1T
You'll have a lot of fun squashing errors
#0, #6 are very annoying - these have priority


----------



## PJVol

Veii said:


> But i do not know how APUs scale


Of course I meant it when I asked for your opinion. Thus seeking for the advice for RAM tuning solely based on this:


Veii said:


> It only does affect how "low" of vdimm you can use - but yet not how "well" dimms can scale
> ...
> But ~ 2:1 mode does not "help" in running absurd timings. Either you can or you can not. It only lowers minimum voltage needed for it by a tiny bit
> ...
> Either it works, or it doesn't


so we could leave the FCLK desync and scaling aspects aside, just considering memory itself, i.e. timings and resistance/voltages

But its ok, nvm.


----------



## Audioboxer

@Veii Finding I have the same issues with 1T I had trying it before










ClkDrvStr 60 is "needed" to get 9 minutes in, but it seems it's causing issues with how strong it is.










Dropped the voltage a bit and even dropped CkeDrvStr to 20 and still getting errors complaining about voltage or PCB crash. Temps are around 40 degrees as they always are.

ClkDrvStr on 30/40 ends up with lots of 6 errors at the start and it's difficult to know what to change.

So I'm at the crossroads of do I stick with ClkDrvStr 60 and see if I can get it working or drop down to 40 and try and figure out what needs increased elsewhere?


----------



## Veii

Audioboxer said:


> ClkDrvStr 60 is "needed" to get 9 minutes in, but it seems it's causing issues with how strong it is.


Just increasing procODT, and staying with ClkDrvStr 40-20-30-24, 40-20-40-20 ~ is no option ?


----------



## Audioboxer

Veii said:


> Just increasing procODT, and staying with ClkDrvStr 40-20-30-24, 40-20-40-20 ~ is no option ?


Nah, lots of 6's


----------



## Veii

Audioboxer said:


> Nah, lots of 6's


why not 15-15-15-15-30-45 ?
Could be too low cLDO_VDDP too


----------



## Audioboxer

Veii said:


> why not 15-15-15-15-30-45 ?
> Could be too low cLDO_VDDP too


Just left over from my 1T profile. I'll switch them and try increasing VDDP a bit.


----------



## MrHoof

I have no experience with DR but isnt 1.55v little to high for a cl 15 set? my SR 15-14-14-26-40-260 need 1.52v.


----------



## Audioboxer

MrHoof said:


> I have no experience with DR but isnt 1.55v little to high for a cl 15 set? my SR 15-14-14-26-40-260 need 1.52v.


Yeah I was running 1.5v. Just increased to 1.55v for 1T to try rule out VDIMM being too low. As long as you keep it cool 1.55v should be fine.

@Veii




























All of these were attempted with VDDP at 0.92v. Having ProcODT at 36.9 seemed to produce the worst result.

So even although I've found out I can run a much weaker Park than I thought it's still the same issues when trying to go to 1T pure  6 and 12, 6 and 12, 6 and 12... lol

The only thing that seems to get me some progress past a minute is ClkDrvStr 60 but that seems to have its own troubles due to strength. Seems to eventually crash PCB.


----------



## MrHoof

Well when I try to push cl 14 and go for around 1.55v it looks similar to what u just run into thats why i was pointing it out. Never tried 1.55v with my cl 15 set and it does not end up in errors in the first seconds. I tought my pcb would could not handle 1.55v, i guess i have more to try tomorrow. Still amazed how my kit just does not care about temps and stays stable at 55°c+ when I tried my brothers 3200 cl14 kit it would error everytime going over 45°C.


----------



## TimeDrapery

There's something very different about how SMU 56.53.0 performs and I don't know if I like it yet

I haven't benched these timings yet nor have I run TM5 as I'm trying to see how voltage behaviors have changed from F12










What really sucks, in my opinion, is it seems like Curve Optimizer has a lesser effect on performance than it did on F12... I might just be imagining things so far but it feels worse

Performance during the CPU benchmark on OCCT Pro is garbage compared to F12, Curve Optimizer behaves _very_ differently from F12

AIDA64 Cache & Memory benchmark performance, especially with regards to L3 throttling, is far worse

Trying to establish a baseline

PBO disabled, many esoteric CBS settings on Auto, loadline on Auto/SOC loadline on Turbo, OC'd through the silly Gigabyte menu with CBS and AMD Overclocking untouched, all C-States business on Enabled... I tried to touch it as little as possible, all timings are set manually as well as memory/SOC voltages


----------



## whocares7

Looks like I should have thrown the TUF board out of the window to accomplish a pure 1T.setup .

VDDP - 0.9V
VDD 1.8V - 1.85V
VDIMM - 1.45V


----------



## Audioboxer

MrHoof said:


> Well when I try to push cl 14 and go for around 1.55v it looks similar to what u just run into thats why i was pointing it out. Never tried 1.55v with my cl 15 set and it does not end up in errors in the first seconds. I tought my pcb would could not handle 1.55v, i guess i have more to try tomorrow. Still amazed how my kit just does not care about temps and stays stable at 55°c+ when I tried my brothers 3200 cl14 kit it would error everytime going over 45°C.


tRFC is the first thing to be temp sensitive on my RAM. I too can run up to around 50 degrees but if I have a low tRFC, or a tRFC that is near the edge in regards to my voltage once it goes above 42 degrees it is likely to bring up an error eventually.

I have tried the voltage I run at with 1T/56, I just upped it in those tests last night to try and help. Scratching my head at how unstable 1T pure becomes considering how tight I can run 1T/56 and with a really relaxed RttPark. Unsure if this is a sign of the rev3 PCB Veii thinks I have with short traces. Might just be my inexperience coupled with a small sample size of said PCB. I'm probably the worst person in existence to have such a PCB and be working on figuring it out 

I guess it would be interesting to hear from other people who have 2x16 kits if they too are capable of booting and stability testing something like 6/2/6 or 7/2/5.


----------



## Veii

Audioboxer said:


> All of these were attempted with VDDP at 0.92v. Having ProcODT at 36.9 seemed to produce the worst result.
> 
> So even although I've found out I can run a much weaker Park than I thought it's still the same issues when trying to go to 1T pure  6 and 12, 6 and 12, 6 and 12... lol


The opposite 
#12, are #2 - which is a timeout issue
Soo timings or tCKE 

#6 are actual hardcrashes ~ be it PCB, or IMC voltage related
#12 you can get away 



whocares7 said:


> Looks like I should have thrown the TUF board out of the window to accomplish a pure 1T.setup .
> 
> VDDP - 0.9V
> VDD 1.8V - 1.85V
> VDIMM - 1.45V
> 
> View attachment 2523758


Браво *!*
Good job , finally someone manages it 

What PCB are your Dimms on ?


----------



## mongoled

@Veii
Have you noted that using different tCKE with AddrCmdSetup set to 56 results in different L1 memory latency?

As I got two error 2s after a 25 cycle TM5 using tCKE @16 the next step would be to use @12, but that results in an increase in latency of around 1 to 1.2ns....


----------



## mongoled

Audioboxer said:


> Might just be my inexperience


Bro, I think you are way passed this part 😂😂


----------



## domdtxdissar

Audioboxer said:


> tRFC is the first thing to be temp sensitive on my RAM. I too can run up to around 50 degrees but if I have a low tRFC, or a tRFC that is near the edge in regards to my voltage once it goes above 42 degrees it is likely to bring up an error eventually.
> 
> I have tried the voltage I run at with 1T/56, I just upped it in those tests last night to try and help. Scratching my head at how unstable 1T pure becomes considering how tight I can run 1T/56 and with a really relaxed RttPark. Unsure if this is a sign of the rev3 PCB Veii thinks I have with short traces. Might just be my inexperience coupled with a small sample size of said PCB. I'm probably the worst person in existence to have such a PCB and be working on figuring it out
> 
> I guess it would be interesting to hear from other people who have 2x16 kits if they too are capable of booting and stability testing something like 6/2/6 or 7/2/5.


I can boot and bench both 6/2/6 and 7/2/5 settings @ T1 56, but pure 1 without setuptime is still no bueno..

Like "*whocares7" *said above here, i more and more start getting the feeling its my motherboard holding me back in regards to memory OC..
I run a almost 2 year old version1 Asus CH8 hero which i plan to change out as soon as the x570s unify-x max get released (use 2x pci.gen.4 m.2 drives)
(got my CH8 delivered together with my old 3950x in January 2020)


----------



## Veii

mongoled said:


> @Veii
> Have you noted that using different tCKE with AddrCmdSetup set to 56 results in different L1 memory latency?


I haven't ever had the need to use such high setup times. Unsure how much they increase latency
tCKE does a bit - but i haven't seen the values of it, change "how much"
it just adds a tiny bit more ~ 0.2 - 0.3 more


----------



## Audioboxer

Veii said:


> The opposite
> #12, are #2 - which is a timeout issue
> Soo timings or tCKE
> 
> #6 are actual hardcrashes ~ be it PCB, or IMC voltage related
> #12 you can get away
> 
> 
> Браво *!*
> Good job , finally someone manages it
> 
> What PCB are your Dimms on ?


The only constant so far for me seems to be the _best results_ come with ClkDrvStr 60, but I don't know if that means I should stick with 60 or figure out why 40 can't run as long as 60 can.

In other news this passed a 25 cycle this morning










I wanted to see how low ProcODT could go with a low VDDP. Only other change to the profile from prior testing was loosening DD's back to 4/6 per your advice they should be the last thing tried.

Not sure if this "helps" much to achieve anything, but I just wanted to experiment with ProcODT. It runs at 34.3 on the profile normally.



domdtxdissar said:


> I can boot and bench both 6/2/6 and 7/2/5 settings @ T1 56, but pure 1 without setuptime is still no bueno..
> 
> Like "*whocares7" *said above here, i more and more start getting the feeling its my motherboard holding me back in regards to memory OC..
> I run a almost 2 year old version1 Asus CH8 hero which i plan to change out as soon as the x570s unify-x max get released (use 2x pci.gen.4 m.2 drives)
> (got my CH8 delivered together with my old 3950x in January 2020)


Try a TM5 run for me if you can be bothered with 7/2/5 or 6/2/6. I would hope it's not my motherboard, I went and bought a 2 DIMM that is supposed to be great for memory overclocking 

More likely it's my memory and potentially whatever the realities are around this rev3 PCB. I'm sure I've seen someone else on this forum with the 2x16GB 3600 14-14-14-14 memory so I might ask them to check what PCB they have.


----------



## Veii

Audioboxer said:


> Not sure if this "helps" much to achieve anything, but I just wanted to experiment with ProcODT. It runs at 34.3 on the profile normally.


You did not benchmark it. But it was written all over here - that a lot of procODTs can work, just that it would autocorrect


----------



## mongoled

@Audioboxer 
Quick and easy test to see if you have too low ProcODT is to simply run LinpackXtreme benchmark (1-3-5-enter), if you get a "fail" increase ProcODT.

Others stress tests won't show any issues but LinpackXtreme will


----------



## whocares7

Veii said:


> What PCB are your Dimms on ?


Dunno ... Custom B2s? I can't say for sure, but these sticks aren't so temperature constrained..


----------



## Audioboxer

Veii said:


> You did not benchmark it. But it was written all over here - that a lot of procODTs can work, just that it would autocorrect


Do you mean in AIDA?










This is with 34.3 and DDs at 2/4










Just benched that there with 












mongoled said:


> @Audioboxer
> Quick and easy test to see if you have too low ProcODT is to simply run LinpackXtreme benchmark (1-3-5-enter), if you get a "fail" increase ProcODT.
> 
> Others stress tests won't show any issues but LinpackXtreme will


But thanks for this mongoled, my ProcODT is no doubt unstable I didn't know about the tip you provided. Which I'll check now!


----------



## mongoled

@Audioboxer
I discovered it by accident when forcing 4133/2067 to ProcODT @28

🤣🤣


----------



## Audioboxer

mongoled said:


> @Audioboxer
> I discovered it by accident when forcing 4133/2067 to ProcODT @28
> 
> 🤣🤣


Seemed to be over quite quick, so you can tell me if I entered anything wrong. First time I've ever ran Linkpack










I'm not even trying to run ProcODT at 28.2 for any real reason other than waking up this morning and thinking what else can I tinker with and see how it goes  Though in the back of my mind I was hoping to try and figure out how ProcODT could end up helping my eventual goal of ever getting 1T pure stable.


----------



## Veii

whocares7 said:


> Dunno ... Custom B2s? I can't say for sure, but these sticks aren't so temperature constrained..
> 
> View attachment 2523822
> View attachment 2523823


mmm
I clearly can not recognize B-PCB's
The traces are all direct traces ~ compared to A-Layout
The bottom is just different ~ soo it would need to be opened


----------



## domdtxdissar

Audioboxer said:


> The only constant so far for me seems to be the _best results_ come with ClkDrvStr 60, but I don't know if that means I should stick with 60 or figure out why 40 can't run as long as 60 can.
> 
> In other news this passed a 25 cycle this morning
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I wanted to see how low ProcODT could go with a low VDDP. Only other change to the profile from prior testing was loosening DD's back to 4/6 per your advice they should be the last thing tried.
> 
> Not sure if this "helps" much to achieve anything, but I just wanted to experiment with ProcODT. It runs at 34.3 on the profile normally.
> 
> 
> 
> Try a TM5 run for me if you can be bothered with 7/2/5 or 6/2/6. I would hope it's not my motherboard, I went and bought a 2 DIMM that is supposed to be great for memory overclocking
> 
> More likely it's my memory and potentially whatever the realities are around this rev3 PCB. I'm sure I've seen someone else on this forum with the 2x16GB 3600 14-14-14-14 memory so I might ask them to check what PCB they have.


3 cycles @ 7/2/5
Can do a full 25 cycles run but don't see what the point would be as ive already have verified these memory timings and settings @ 7/3/3


----------



## Audioboxer

domdtxdissar said:


> 3 cycles @ 7/2/5
> Can do a full 25 cycles run but don't see what the point would be as ive already have verified these memory timings and settings @ 7/3/3
> View attachment 2523824


Great thanks, I was only really asking because when Veii thought I had a rev3 PCB with short traces I was hoping to see if that meant differences with Rtts compared to rev 0/1/2. Do you know what PCB you have?

My prior experience with b-die has only been a 3200C14 kit that couldn't even boot anything other than RttPark 1 over 3400


----------



## domdtxdissar

Audioboxer said:


> Great thanks, I was only really asking because when Veii thought I had a rev3 PCB with short traces I was hoping to see if that meant differences with Rtts compared to rev 0/1/2. Do you know what PCB you have?
> 
> My prior experience with b-die has only been a 3200C14 kit that couldn't even boot anything other than RttPark 1 over 3400


Have no other information then gskill saying its a custom 10 layer PCB design and these pictures:






















_edit_

testmem still running:


----------



## Audioboxer

domdtxdissar said:


> Have no other information then gskill saying its a custom 10 layer PCB design and these pictures:
> View attachment 2523825
> 
> View attachment 2523826
> View attachment 2523827


I think that is their best binned b-die on sale, it's certainly the most expensive lol. So it wouldn't surprise me if its some custom job.

Mad though even it struggles with 1T pure!  Then there are other people with pretty "standard" C16 bins running 1T pure no issues with 40/20/30/20 and that is it  Whereas my 1T pure experience with 40/20/30/20 is like a damn Christmas tree going off 30 seconds into TM5.

Guess that is the luck of the draw with memory silicon unless you do have a mobo or CPU which isn't helping the cause. It seems DR or 2x16GB can be a bit more challenging to get 1T pure up and running than 8GB SR.


----------



## Hale59

domdtxdissar said:


> Have no other information then gskill saying its a custom 10 layer PCB design and these pictures:


I can do the same with cheap ram of mine:


----------



## Veii

Hale59 said:


> I can do the same with cheap ram of mine:


Without SETUP Timings (delays) is pure 1T
or ones sub value 32


----------



## domdtxdissar

Audioboxer said:


> I think that is their best binned b-die on sale, it's certainly the most expensive lol. So it wouldn't surprise me if its some custom job.
> 
> Mad though even it struggles with 1T pure!  Then there are other people with pretty "standard" C16 bins running 1T pure no issues with 40/20/30/20 and that is it  Whereas my 1T pure experience with 40/20/30/20 is like a damn Christmas tree going off 30 seconds into TM5.
> 
> Guess that is the luck of the draw with memory silicon unless you do have a mobo or CPU which isn't helping the cause. It seems DR or 2x16GB can be a bit more challenging to get 1T pure up and running than 8GB SR.


Yeah thinks it comes down to the cpu+motherboard+memory combo.. every part most be up for the challenge of pure T1 

And i will kinda have the means to put this theory to the test.. I will replace my CH8 motherboard with a UNIFY-X MAX first which should be the best motherboard for 2x16gb sticks.
After that i will replace my 5950x with a 5950 3Dnow! edition 

My current 2x16GB should have no problems with pure T1, so we will see if the problem was motherboard or cpu..

In regards to dualrank vs singlerank, i still have my very good 4x8gb set. If i just want to run only 2x8gb sticks, pure T1 is a cakewalk, so easy its not even funny... will run almost all settings you throw at it.









@ *Hale59*

LOL why are you quoting me and posting screens of singlerank 2x8gb @ tRCDRD 15 timings with 56 T1 setup time on a 4core 3100 ? What are this suppose to show ?


----------



## Audioboxer

domdtxdissar said:


> Yeah thinks it comes down to the cpu+motherboard+memory combo.. every part most be up for the challenge of pure T1
> 
> And i will kinda have the means to put this theory to the test.. I will replace my CH8 motherboard with a UNIFY-X MAX first which should be the best motherboard for 2x16gb sticks.
> After that i will replace my 5950x with a 5950 3Dnow! edition
> 
> My current 2x16GB should have no problems with pure T1, so we will see if the problem was motherboard or cpu..
> 
> In regards to dualrank vs singlerank, i still have my very good 4x8gb set. If i just want to run only 2x8gb sticks, pure T1 is a cakewalk, so easy its not even funny... will run almost all settings you throw at it.
> 
> View attachment 2523837
> 
> 
> @ *Hale59*
> 
> LOL why are you posting screens of singlerank 2x8gb @ flat 14 timings with 56 t1 setup time on a 4core 3100 ? What are this suppose to show ?


I bought a B550 Unify X with memory in mind and I'd be wrong to say it isn't helping, it could be helping me get better timings or use less voltage or what have you, but it's not helped with 1T (so far)  My 5950x seems pretty decent, so I guess it's all part of the puzzle. It is funny to see pretty tight timings with decent voltage numbers sail through a 25 and then all you do is switch to 1T pure and it's a war zone  I might have a go at 1T Pure at 3600/1800 and see if 3800/1900 is causing any issues.

With 2 DIMMs I just wouldn't go with 2x8. I'd rather have 32GB.


----------



## PJVol

Audioboxer said:


> how ProcODT could end up helping my eventual goal


Not sure will it help, but just an observation:
(in a tedious searching for an answer, - who the hell is raising PHYRDL in various configs with the same MCLK, tCL and tCWL )










For the current config tightening RAS-RP and RTP-WR did nothing.
ProcODT 34.3 goes straight to PHYRDL 28 (from 26) and worsen mem latency a bit
ProcODT 32 - no go, i.e. boot through 2 cold starts and a 5-7 warm ones (apu specific) back to default.
Side notes:

 vdimm was 1.524V everywhere
 with procODT 40Ohms it feels more stable (unlike Vermeer)
 mem latency result was "clicked-out" from corresponding field and the best one was chosen out the 10 clicks in a row with a 2-3 sec interval.


----------



## Hale59

domdtxdissar said:


> @ *Hale59*
> 
> LOL why are you posting screens of singlerank 2x8gb @ tRCDRD 15 timings with 56 T1 setup time on a 4core 3100 ? What are this suppose to show ?


Why? Are we only suppose to post 2X16GB Dual rank? LOL
Since is this sub-forum only about Ryzen 5000?
What is your problem? Do I have to ask you permission to post? LOL


----------



## Hale59

I can even post more...


----------



## Audioboxer

PJVol said:


> Not sure will it help, but just an observation:
> (in a tedious searching for an answer, - who the hell is rasing PHYRDL in various configs with the same MCLK, tCL and tCWL )
> View attachment 2523840
> 
> 
> 
> For the current config tightening RAS-RP and RTP-WR did nothing.
> ProcODT 34.3 goes straight to PHYRDL 28 (from 26) and worsen mem latency a bit
> ProcODT 32 - no go, i.e. boot through 2 cold starts and a 5-7 warm ones (apu specific) back to default.
> Vdimm was 1.524V everywhere.


That's interesting! My observations so far had only extended to

tPHYRDL 26

15 1t (doesn't need to be pure)
14 2t

tPHYRDL 28

15 2t
14 1t

But I hadn't been changing ProcODT here, just left at 34.3. When I've got 5 mins I might try and see if ProcODT changes any of the above behaviour on my memory.

Only other thing I found out for my memory is tPHYWRL will go to 7 if tCWL is at 12.

*edit* - No such luck 14 1T still likes 28 lol










I guess I'll run a test on tCL 14 and see if I'm lucky enough to just be able to run my 15 settings or if I need to go right back to my 14 profile and work from there.

I seem to get a ~0.5 latency hit with tPHYRDL 28 so it just doesn't seem worth it to go to tCL14 unless I can shift it back down to 26.


----------



## Veii

Hale59 said:


> Why? Are we only suppose to post 2X16GB Dual rank? LOL
> Since is this sub-forum only about Ryzen 5000?
> What is your problem? Do I have to ask you permission to post? LOL


It was because of the multiple pages discussion about Dual Rank and "pure 1T"
While you posted as "i can do this too" ~ which has Setup Timings

That's the confusion
Nobody is attacking anybody 
We try to figure out why it doesn't function for people without SETUP timings . What is missing


Audioboxer said:


> Only other thing I found out for my memory is tPHYWRL will go to 7 if tCWL is at 12.
> 
> *edit* - No such luck 14 1T still likes 28 lol


tPHYRDL will only shift up, if training was bad.
But tPHYWRL remains behaving how it should - honestly RDL does too
they are IOL's , while WRL and similar ~ likely change by tCWL
Both is normal


----------



## Audioboxer

Veii said:


> It was because of the multiple pages discussion about Dual Rank and "pure 1T"
> While you posted as "i can do this too" ~ which has Setup Timings
> 
> That's the confusion
> Nobody is attacking anybody
> We try to figure out why it doesn't function for people without SETUP timings . What is missing
> 
> tPHYRDL will only shift up, if training was bad.
> But tPHYWRL remains behaving how it should - honestly RDL does too
> they are IOL's , while WRL and similar ~ likely change by tCWL
> Both is normal


But when you say training was bad what does that mean exactly? Putting 'bad' in a sentence makes me think not stable, or it could be better if better timings were used?

Given how many people get tPHYRDL 28 at 3800 tCL14 though is it just _normal_ behaviour?

While I haven't done a lot of testing as I said above I do seem to notice a small latency hit when I end up with one DIMM 28 and one 26 lol. So I feel more comfortable just staying at tCL15.

And yeah my tCWL definitely drops WRL to 7 with 12, confirmed that.


----------



## mongoled

Ive got great news,

unsure if this will be helpful for anyone but was helpful for me



As we get older "we" get fixed in our ways, we get a little bit lazy, especially in the brain



So when something "works" and has "worked" for a long time its easy to get "stuck" and not go over old ground again.

So after many BIOS updates and finding a certain value worked for posting at a certain frequency, which was consistent across all the updates, I stopped checking two certain values.

CLDO vDDP voltage and relationship to FCLK posting.

Well ive found out that using vDDP @ 0.885v (not tried anything else yet) allows me to post with no issues whatsoever using FCLK @2033 mhz

Cold boot, warm boot, cold boot, warm makes no difference.

  

Looks like im going to have to cover the other ranges I was having issues with (1933/1966/2000 | Sometimes/Never/Never).

Its amazing to see this works, if its the same for the other ranges than great.

Have not made any stability tests yet, just running TM5.

Really excited, the holy grail maybe here, FCLK holes bye bye bye



** EDIT **
Just need to say it may also be effected by the combination of ProcODT, vSOC with vDDP etc that I used, 

not verified yet, but should be relatively easy to test


----------



## Audioboxer

mongoled said:


> Ive got great news,
> 
> unsure if this will be helpful for anyone but was helpful for me
> 
> 
> 
> As we get older "we" get fixed in our ways, we get a little bit lazy, especially in the brain
> 
> 
> 
> So when something "works" and has "worked" for a long time its easy to get "stuck" and not go over old ground again.
> 
> So after many BIOS updates and finding a certain value worked for posting at a certain frequency, which was consistent across all the updates, I stopped checking two certain values.
> 
> CLDO vDDP voltage and relationship to FCLK posting.
> 
> Well ive found out that using vDDP @ 0.885v (not tried anything else yet) allows me to post with no issues whatsoever using FCLK @2033 mhz
> 
> Cold boot, warm boot, cold boot, warm makes no difference.
> 
> 
> 
> Looks like im going to have to cover the other ranges I was having issues with (1933/1966/2000 | Sometimes/Never/Never).
> 
> Its amazing to see this works, if its the same for the other ranges than great.
> 
> Have not made any stability tests yet, just running TM5.
> 
> Really excited, the holy grail maybe here, FCLK holes bye bye bye
> 
> 
> 
> ** EDIT **
> Just need to say it may also be effected by the combination of ProcODT, vSOC with vDDP etc that I used,
> 
> not verified yet, but should be relatively easy to test


lol bro you're going to get me started on my next journey, trying to find a FCLK above 1900 where I don't get WHEA.

I just tried to boot 2033 for the hell of it without changing RAM divider, got to desktop but rebooted. Wouldn't even know where to begin with voltages necessary to feed 2033.

Are you WHEA free at that?


----------



## mongoled

Audioboxer said:


> lol bro you're going to get me started on my next journey, trying to find a FCLK above 1900 where I don't get WHEA.
> 
> I just tried to boot 2033 for the hell of it without changing RAM divider, got to desktop but rebooted. Wouldn't even know where to begin with voltages necessary to feed 2033.
> 
> Are you WHEA free at that?


no, lol

thats going to get investigated also


----------



## Veii

Audioboxer said:


> But when you say training was bad what does that mean exactly? Putting 'bad' in a sentence makes me think not stable, or it could be better if better timings were used?
> Given how many people get tPHYRDL 28 at 3800 tCL14 though is it just _normal_ behaviour?
> 
> While I haven't done a lot of testing as I said above I do seem to notice a small latency hit when I end up with one DIMM 28 and one 26 lol. So I feel more comfortable just staying at tCL15.
> And yeah my tCWL definitely drops WRL to 7 with 12, confirmed that.


"Bad predictions & bad training".
Honestly nothing we can do about it,
We can extend training delays ~ if boardpartners let AMD CBS - UMC - DDR4 - SECURITY - PHY open
Soo also let DDR4 Burst Refresh Override mode open

But nothing you can really do
You have to hope that board engineers have it configured correctly.
Same goes for ECC
I only had it once (tPHYRDL missmatch), but that was once in a blue moon ~ it never happened again. Training kept being successfull

3rd CAD_BUS Value helps against broken memory training, but it's always been broken for anything non Rev.E
At least most boards do not need 6 manual reboots, to have a successful post


----------



## TimeDrapery

So this tPHYDRL mismatch is an "issue"? It doesn't result in instability but rather in greater memory latency?


----------



## Veii

TimeDrapery said:


> View attachment 2523853
> 
> 
> So this tPHYDRL mismatch is an "issue"? It doesn't result in instability but rather in greater memory latency?


I see it as an issue ~ as it only happened - if cLDO_VDDP (for me) was too low or procODT was too low (yet couldn't break training again, once it locked in 26)
Soo IOL latency increased.
It's doing it for stability reasons - and i wouldn't even notice it "missbehaving", if it wasn't for the community here

But nevertheless, it's different between PCBs and different between dimm amount or rank amount
Soo i wouldn't bother much with it. Only if you see variation between both dimms ~ then it's really an issue. 
Else anything is behaving and scaling how it should.


----------



## TimeDrapery

Spoiler






Veii said:


> I see it as an issue ~ as it only happened - if cLDO_VDDP (for me) was too low or procODT was too low (yet couldn't break training again, once it locked in 26)
> Soo IOL latency increased.
> It's doing it for stability reasons - and i wouldn't even notice it "missbehaving", if it wasn't for the community here
> 
> But nevertheless, it's different between PCBs and different between dimm amount or rank amount
> Soo i wouldn't bother much with it. Only if you see variation between both dimms ~ then it's really an issue.
> Else anything is behaving and scaling how it should.






@Veii 

That was my thinking as well, only when the mismatch occurs between DIMMs on the same channel should this be an issue... Otherwise it's simply different latencies between channels, which is what we want "training" to catch and produce adjustments to accommodate

It is interesting, to me, that different timing sets produce different results for tPHYDRL between channels... A flat 16 set, in my system, produces 26 across the board whereas flat 15s produce 28/26


----------



## umea

Audioboxer said:


> I think that is their best binned b-die on sale, it's certainly the most expensive lol. So it wouldn't surprise me if its some custom job.


oh now I'm tempted 😥 although I know the limiting factor right now is most likely my CPU.. well, limiting factor being able to get 14 flat lol. When I'm not lazy I'll give a look at seeing if I can get it on one stick.


----------



## whocares7

TimeDrapery said:


> It is interesting, to me, that different timing sets produce different results for tPHYDRL between channels... A flat 16 set, in my system, produces 26 across the board whereas flat 15s produce 28/26


Same behavior occurs to me when CR=2 is set with a flat 15 set.
CR=1 does not produce tPHYDRL mismatch.
Hm...


----------



## TimeDrapery

Spoiler






whocares7 said:


> Same behavior occurs to me when CR=2 is set with a flat 15 set.
> CR=1 does not produce tPHYDRL mismatch.
> Hm...






@whocares7 

Right, I imagine it has to do with CR more than most anything else unless it's producing the mismatch on the same memory channel in which case the PHY is not getting something it needs


----------



## TimeDrapery

Ah good, the OB issue is still alive and well! 61,955MHz... Best that OC, peoples


----------



## Audioboxer

Veii said:


> I see it as an issue ~ as it only happened - if cLDO_VDDP (for me) was too low or procODT was too low (yet couldn't break training again, once it locked in 26)
> Soo IOL latency increased.
> It's doing it for stability reasons - and i wouldn't even notice it "missbehaving", if it wasn't for the community here
> 
> But nevertheless, it's different between PCBs and different between dimm amount or rank amount
> Soo i wouldn't bother much with it. *Only if you see variation between both dimms ~ then it's really an issue.*
> Else anything is behaving and scaling how it should.


That's the issue I get at tCL14 at 3800, one DIMM goes 28 the other is 26.

I guess I could do a bit more testing with looser timings and what not at tCL14 at 3800, just to see. I'd now be interested to know if I bought a 3800C14 ranked kit could I end up seeing 28 still? 

The strangest thing for me is getting 28 at tCL15 2T, but if I boot 1T it goes to 26 lmao.



TimeDrapery said:


> @Veii
> 
> That was my thinking as well, only when the mismatch occurs between DIMMs on the same channel should this be an issue... Otherwise it's simply different latencies between channels, which is what we want "training" to catch and produce adjustments to accommodate
> 
> It is interesting, to me, that different timing sets produce different results for tPHYDRL between channels... A flat 16 set, in my system, produces 26 across the board whereas flat 15s produce 28/26


Try 1T with flat 15's, it gives me 26. As I just said to Veii 2T gives me that 28/26 lol.

It's the other way around for me with tCL14, 2T gives me 26/26, 1T gives me 28/26.



umea said:


> oh now I'm tempted 😥 although I know the limiting factor right now is most likely my CPU.. well, limiting factor being able to get 14 flat lol. When I'm not lazy I'll give a look at seeing if I can get it on one stick.


I honestly wouldn't spend a lot on b-die, unless you have money to burn. It seems it's really the luck of the draw and seemingly your other components like CPU/mobo also get thrown into that draw. I've seen people spend on higher binned b-die like myself and others and we end up not being able to do 1T pure or 3800 flat 14s and other people can on "lesser" bins.

Though from my little knowledge so far it seems if you want to see the pretty numbers and 1T pure and don't mind 16GB, get yourself 2x8GB SR and "sail" to success. The bigger challenges seem to come from 2x16GB DR and while some lucky sobs seem to still walk to 1T pure and even 3800 flat 14s, I'd say more people start to get issues with both of those at 2x16GB DR.


----------



## Veii

whocares7 said:


> Same behavior occurs to me when CR=2 is set with a flat 15 set.
> CR=1 does not produce tPHYDRL mismatch.
> Hm...











They did not change between dimm's , but you are right here
2T upped it to 28
I made tho some interesting discoveries

SETUP timings, 63 is max
Soo 31 and bellow won't switch to command rate mode

About patterns,
58-0-0 did post with #0 spam
54 not post, following my scaling rulesets
56 post, BSOD
57 BSOD
58, #0 spam only, BSOD
59, #6 spam ~ rare #12 rare #0 no BSOD but bad Aida64 - also L1 crashes on Copy down to 1200GB/s
60, appears stable

Which means it's going upwards the higher you go in MCLK
Errors appear instantly or remains stable
Will report in 4-5h (busy atm) if it really ended up stable

SETUP Timings score








Is decent. We can accept it
But L3 cache is messed up. Can not hold 640 or even 670 peaks.
Latest windows version 19043.1200 messed up things for me. I was on 19041 which was great ~ down to 48.1 / 48.3 max
Downgraded down to finish 2133, as Win11 did not fix L3 on the .100 version i was. Currently running cleaned GhostSpectreOS ~ manually cleaned ontop

Anywho, report that "fake 1T" is in acceptable states
Read looses 100MB/s, Copy looses 50-60MB/s. Still Holds (even easier) max write bandwidth

Pure 1T likely still has a better taste to it ~ because you know that everything is perfect.
But i think it passes latency wise.
Only the unstable SETUP Timings value, pushed it up to 49.2 / 49.3ns 

EDIT:
I want to also mention, that it absolutely did not post on stock
Everything broke lose and even CMOS cleared, with "wrong" AddrCmdSETUP


----------



## MrHoof

I am looking at a DR kit to get since I am done with my SR kit there is nothing left to do and have money to burn. 3600-16-16-16-36 1.35v for 232€ or 3600-14-15-15-35 1.45v for 285. Gonna decide tomorrow but probably gonna get the c16 one.


----------



## TimeDrapery

Audioboxer said:


> The strangest thing for me is getting 28 at tCL15 2T, but if I boot 1T it goes to 26 lmao.
> 
> Try 1T with flat 15's, it gives me 26. As I just said to Veii 2T gives me that 28/26 lol.
> 
> It's the other way around for me with tCL14, 2T gives me 26/26, 1T gives me 28/26.


@Audioboxer

I will soon

Lowering tCL to 14 also kicks both channels to 26 for me (on F12, I've yet to do this with F13)

Regardless of tPHYDRL, OCCT Pro shows better results with flat 15s... Nothing huge but certainly noticeable


----------



## umea

Audioboxer said:


> I honestly wouldn't spend a lot on b-die, unless you have money to burn. It seems it's really the luck of the draw and seemingly your other components like CPU/mobo also get thrown into that draw. I've seen people spend on higher binned b-die like myself and others and we end up not being able to do 1T pure or 3800 flat 14s and other people can on "lesser" bins.
> 
> Though from my little knowledge so far it seems if you want to see the pretty numbers and 1T pure and don't mind 16GB, get yourself 2x8GB SR and "sail" to success. The bigger challenges seem to come from 2x16GB DR and while some lucky sobs seem to still walk to 1T pure and even 3800 flat 14s, I'd say more people start to get issues with both of those at 2x16GB DR.


Yeah, my kit was already pretty expensive, 4266 17 18 18 38 (329usd). It definitely comes down to other components as well sadly and even within good bins there will be some lottery. 

Of course if I can sell the 2-3 systems worth of parts I have laying around I might try building a little rig just for OCing...


----------



## TimeDrapery

Dropping a pair of sticks does make everything much, much simpler


















Also... HWiNFO64 now reports "Average Active Core Count"? Well that's nifty!

I think it's pretty nifty how easy these 2× SR DIMMs are to OC as well, nothing like #s @Veii is throwing up with his "six"-core (insanity!) but I like how it's looking










Tightening turnaround timings increases bandwidth and helps reduce latency... Dropping them all the way does too but for some reason it feels so wrong 😂😂😂😂😂


















Here's 1T "pure", who knows how stable it is, I do notice that (even with flat 14s) I've got one channel on 28 and one on 26 for tPHYDRL... Boo










We'll see what comes of it...










The only thing changed from my earlier post wherein I described most esoteric BIOS settings on Auto is that, following the OB incident, I've set APBDIS to 1 and the fixed SOC p-state to 0 in an attempt to avoid a repeat of the highest OC I've ever attained

Stable enough to keep stability testing, I guess... 😂😂😂😂😂










Don't see many posting OCCT benches but, in case someone's interested... Oh yeah, experimenting with powering now and then I'll keep stability testing










Too much bouncing on latency run-to-run... Gotta play with ProcODT (all with the same timing set and drive strengths set to 40.0Ω-20.0Ω-30.0Ω-20.0Ω)


*ProcODT*_*28.2Ω*__*30.0Ω*__*32.0Ω*__*34.3Ω*__*36.9Ω*_*Initial Run*53.4 ns54.6 ns55.0 ns53.4 ns53.9 ns*1st Run*53.1 ns54.0 ns53.6 ns53.6 ns53.1 ns*2nd Run*53.0 ns52.8 ns53.1 ns52.8 ns55.0 ns*3rd Run*53.2 ns53.1 ns53.2 ns53.0 ns52.9 ns

So I don't know exactly how to interpret the results... I figure I'll go for the lowest average with the smallest range...? 😂😂😂😂😂


*ProcODT**28.2Ω**30.0Ω**32.0Ω**34.3Ω***36.9Ω**Range*53.0 - 53.4 ns (0.4 ns)*52.8 - 54.6 ns (1.8 ns)53.1 - 55.0 ns (1.9 ns)52.8 - 53.6 ns (0.5 ns)52.9 - 55.0 ns (2.1 ns)*Average*53.175 ns53.625 ns53.725 ns53.15 ns*53.725 ns

The system defaults to all 24.0Ω for drive strengths with these DIMMs so I may try 40.0Ω-24.0Ω-24.0Ω-24.0Ω if I'm unhappy with the results that populate the above table as testing progresses... Yeah I'll try it, here's another table...


*ProcODT*_*28.2Ω *__*30.0Ω*__*32.0Ω**__*34.3Ω*__*36.9Ω*_*Initial Run*54.7 ns53.6 ns53.1 ns54.1 ns54.8 ns*1st Run*53.0 ns52.9 ns52.7 ns53.4 ns53.6 ns*2nd Run*55.0 ns52.9 ns52.8 ns53.3 ns55.3 ns*3rd Run*53.3 ns52.9 ns53.0 ns54.4 ns52.7 ns

and my interpretation


*ProcODT**28.2Ω**30.0Ω**32.0Ω***34.3Ω**36.9Ω**Range*53.0 - 55.0 ns (2.0 ns)52.9 - 53.6 ns (0.7 ns)52.7 - 53.1 ns (0.4 ns)*53.3 - 54.4 ns (1.1 ns)52.7 - 55.3 ns (2.6 ns)*Average*54.0 ns53.075 ns52.9 ns*53.8 ns54.1 ns

Clear winner with 40.0Ω-24.0Ω-24.0Ω-24.0Ω and 32.0Ω... now more stability testing

Coming along nicely, this is the 25 cycle @ 100% rather than the quick 1 cycle @ 1000% that I was running earlier... DIMMs' temperatures are looking good










That's probably as toasty as they'll get, I'll bet Karhu will take them just a smidge above this










Ack, an error... Let's wait it out and see what else comes our way










I'm not sure what to think of the error, the help sheet authored by @Veii talks about voltages and resistances and I'm guessing drive strengths but that could be way off base... Unless I get some additional "indicators" (errors 😂😂😂😂😂) I'll likely increase CsOdtDrvStr to 30.0Ω and re-run the ProcODT testing as I did above

On second thought, I'll likely increase ClkDrvStr to 60.0Ω and leave the other three to 24.0Ω and then re-run the ProcODT testing... I wonder if the optimal value will drop to 30.0Ω...?










It's a stupid singular 2... Okay, I'll try the ClkDrvStr uptick

A shot in the dark before I head off to bed...










@Veii

Why is the L3 cache throttling issue a thing at all? Like, what is the throttling that takes place under those conditions intended to "fix" ("band-aids")? OB?


----------



## XPEHOPE3

Veii said:


> I only had it once (tPHYRDL missmatch), but that was once in a blue moon ~ it never happened again. Training kept being successfull


Well, wait until you get your new nightmare DR kit 


TimeDrapery said:


> It is interesting, to me, that different timing sets produce different results for tPHYDRL between channels... A flat 16 set, in my system, produces 26 across the board whereas flat 15s produce 28/26


tPHYDRL can vary even for the same timing set between cold boots, with some influence on latency, up to 0.7ns.

Also tPHYDRL is sensitive to VDDP: raising it can allow for lower tPHYDRL.


----------



## TimeDrapery

Spoiler






XPEHOPE3 said:


> Well, wait until you get your new nightmare DR kit
> tPHYDRL can vary even for the same timing set between cold boots, with some influence on latency, up to 0.7ns.
> 
> Also tPHYDRL is sensitive to VDDP: raising it can allow for lower tPHYDRL.






Makes sense to me


----------



## Veii

XPEHOPE3 said:


> Well, wait until you get your new nightmare DR kit
> tPHYDRL can vary even for the same timing set between cold boots, with some influence on latency, up to 0.7ns.
> 
> Also tPHYDRL is sensitive to VDDP: raising it can allow for lower tPHYDRL.


Would love to see it once in a blue moon on 24
But so far, even 13-13-13 held it at 26

Except the hardlocked bios with close to no options
And very slow memory training (it works)
Everything works fine.

Interestingly, "old profiles" loaded ~ appear to change CBS settings, i have no access to
Sadly 1200 rewrote USB locations and patches ~ soo HEX don't align and old "good" profiles can not be used
Currently a little struggle to keep up 48.5, mostly it's a bit higher


----------



## TimeDrapery

Veii said:


> Would love to see it once in a blue moon on 24
> But so far, even 13-13-13 held it at 26
> 
> Except the hardlocked bios with close to no options
> And very slow memory training (it works)
> Everything works fine.
> 
> Interestingly, "old profiles" loaded ~ appear to change CBS settings, i have no access to
> Sadly 1200 rewrote USB locations and patches ~ soo HEX don't align and old "good" profiles can not be used
> Currently a little struggle to keep up 48.5, mostly it's a bit higher


@Veii 

What did they hide away this go around?


----------



## mongoled

mongoled said:


> Ive got great news,
> 
> unsure if this will be helpful for anyone but was helpful for me
> 
> 
> 
> As we get older "we" get fixed in our ways, we get a little bit lazy, especially in the brain
> 
> 
> 
> So when something "works" and has "worked" for a long time its easy to get "stuck" and not go over old ground again.
> 
> So after many BIOS updates and finding a certain value worked for posting at a certain frequency, which was consistent across all the updates, I stopped checking two certain values.
> 
> CLDO vDDP voltage and relationship to FCLK posting.
> 
> Well ive found out that using vDDP @ 0.885v (not tried anything else yet) allows me to post with no issues whatsoever using FCLK @2033 mhz
> 
> Cold boot, warm boot, cold boot, warm makes no difference.
> 
> 
> 
> Looks like im going to have to cover the other ranges I was having issues with (1933/1966/2000 | Sometimes/Never/Never).
> 
> Its amazing to see this works, if its the same for the other ranges than great.
> 
> Have not made any stability tests yet, just running TM5.
> 
> Really excited, the holy grail maybe here, FCLK holes bye bye bye
> 
> 
> 
> ** EDIT **
> Just need to say it may also be effected by the combination of ProcODT, vSOC with vDDP etc that I used,
> 
> not verified yet, but should be relatively easy to test


Soooooooooo frustrating.

Today everything went back to normal

 

I dont get it, I tested it last night, cold post, let it sit few minutes, started fine, few warm boots, started fine, cold post, didnt let it sit started fine, few boots to OS, shut downs, let it sit etc etc

It posted each and every time.

Ive been playing with ProcODT, vDDP, memory training settings etc etc, nothing is getting it to play nice again ......


----------



## Audioboxer

TimeDrapery said:


> Dropping a pair of sticks does make everything much, much simpler
> 
> View attachment 2523873
> 
> View attachment 2523874
> 
> 
> Also... HWiNFO64 now reports "Average Active Core Count"? Well that's nifty!
> 
> I think it's pretty nifty how easy these 2× SR DIMMs are to OC as well, nothing like #s @Veii is throwing up with his "six"-core (insanity!) but I like how it's looking
> 
> View attachment 2523876
> 
> 
> Tightening turnaround timings increases bandwidth and helps reduce latency... Dropping them all the way does too but for some reason it feels so wrong 😂😂😂😂😂
> 
> View attachment 2523881
> 
> View attachment 2523882
> 
> 
> Here's 1T "pure", who knows how stable it is, I do notice that (even with flat 14s) I've got one channel on 28 and one on 26 for tPHYDRL... Boo
> 
> View attachment 2523883
> 
> 
> We'll see what comes of it...
> 
> View attachment 2523884
> 
> 
> The only thing changed from my earlier post wherein I described most esoteric BIOS settings on Auto is that, following the OB incident, I've set APBDIS to 1 and the fixed SOC p-state to 0 in an attempt to avoid a repeat of the highest OC I've ever attained
> 
> Stable enough to keep stability testing, I guess... 😂😂😂😂😂
> 
> View attachment 2523885
> 
> 
> Don't see many posting OCCT benches but, in case someone's interested... Oh yeah, experimenting with powering now and then I'll keep stability testing
> 
> View attachment 2523886
> 
> 
> Too much bouncing on latency run-to-run... Gotta play with ProcODT (all with the same timing set and drive strengths set to 40.0Ω-20.0Ω-30.0Ω-20.0Ω)
> 
> 
> *ProcODT*_*28.2Ω*__*30.0Ω*__*32.0Ω*__*34.3Ω*__*36.9Ω*_*Initial Run*53.4 ns54.6 ns55.0 ns53.4 ns53.9 ns*1st Run*53.1 ns54.0 ns53.6 ns53.6 ns53.1 ns*2nd Run*53.0 ns52.8 ns53.1 ns52.8 ns55.0 ns*3rd Run*53.2 ns53.1 ns53.2 ns53.0 ns52.9 ns
> 
> So I don't know exactly how to interpret the results... I figure I'll go for the lowest average with the smallest range...? 😂😂😂😂😂
> 
> 
> *ProcODT**28.2Ω**30.0Ω**32.0Ω**34.3Ω***36.9Ω**Range*53.0 - 53.4 ns (0.4 ns)*52.8 - 54.6 ns (1.8 ns)53.1 - 55.0 ns (1.9 ns)52.8 - 53.6 ns (0.5 ns)52.9 - 55.0 ns (2.1 ns)*Average*53.175 ns53.625 ns53.725 ns53.15 ns*53.725 ns
> 
> The system defaults to all 24.0Ω for drive strengths with these DIMMs so I may try 40.0Ω-24.0Ω-24.0Ω-24.0Ω if I'm unhappy with the results that populate the above table as testing progresses... Yeah I'll try it, here's another table...
> 
> 
> *ProcODT*_*28.2Ω *__*30.0Ω*__*32.0Ω**__*34.3Ω*__*36.9Ω*_*Initial Run*54.7 ns53.6 ns53.1 ns54.1 ns54.8 ns*1st Run*53.0 ns52.9 ns52.7 ns53.4 ns53.6 ns*2nd Run*55.0 ns52.9 ns52.8 ns53.3 ns55.3 ns*3rd Run*53.3 ns52.9 ns53.0 ns54.4 ns52.7 ns
> 
> and my interpretation
> 
> 
> *ProcODT**28.2Ω**30.0Ω**32.0Ω***34.3Ω**36.9Ω**Range*53.0 - 55.0 ns (2.0 ns)52.9 - 53.6 ns (0.7 ns)52.7 - 53.1 ns (0.4 ns)*53.3 - 54.4 ns (1.1 ns)52.7 - 55.3 ns (2.6 ns)*Average*54.0 ns53.075 ns52.9 ns*53.8 ns54.1 ns
> 
> Clear winner with 40.0Ω-24.0Ω-24.0Ω-24.0Ω and 32.0Ω... now more stability testing
> 
> Coming along nicely, this is the 25 cycle @ 100% rather than the quick 1 cycle @ 1000% that I was running earlier... DIMMs' temperatures are looking good
> 
> View attachment 2523889
> 
> 
> That's probably as toasty as they'll get, I'll bet Karhu will take them just a smidge above this
> 
> View attachment 2523892
> 
> 
> Ack, an error... Let's wait it out and see what else comes our way
> 
> View attachment 2523898
> 
> 
> I'm not sure what to think of the error, the help sheet authored by @Veii talks about voltages and resistances and I'm guessing drive strengths but that could be way off base... Unless I get some additional "indicators" (errors 😂😂😂😂😂) I'll likely increase CsOdtDrvStr to 30.0Ω and re-run the ProcODT testing as I did above
> 
> On second thought, I'll likely increase ClkDrvStr to 60.0Ω and leave the other three to 24.0Ω and then re-run the ProcODT testing... I wonder if the optimal value will drop to 30.0Ω...?
> 
> View attachment 2523907
> 
> 
> It's a stupid singular 2... Okay, I'll try the ClkDrvStr uptick
> 
> A shot in the dark before I head off to bed...
> 
> View attachment 2523911
> 
> 
> @Veii
> 
> Why is the L3 cache throttling issue a thing at all? Like, what is the throttling that takes place under those conditions intended to "fix" ("band-aids")? OB?


Great detailed post. The overclocker in me wants a 2x8GB SR kit now but the realist in me screams "Be happy with your 32GB, you have 2 DIMMs" 

As I said earlier the 28/26 seems to be common when chasing 3800 tCL14 1T. Happens to me as well. Only 2T at 3800 sticks with 26/26.

But hopefully @Veii gets a DR 2x16 soon and maybe all of us on 2x16 have some more hope lol. Unless Veii gets one of those magical DR kits that just boots 3800 flat 14 1T no problem


----------



## Mach3.2

Audioboxer said:


> Great detailed post. The overclocker in me wants a 2x8GB SR kit now but the realist in me screams "Be happy with your 32GB, you have 2 DIMMs"
> 
> As I said earlier the 28/26 seems to be common when chasing 3800 tCL14 1T. Happens to me as well. Only 2T at 3800 sticks with 26/26.
> 
> But hopefully @Veii gets a DR 2x16 soon and maybe all of us on 2x16 have some more hope lol. Unless Veii gets one of those magical DR kits that just boots 3800 flat 14 1T no problem


You can send a set to him 😜


----------



## whocares7

Lets see how much VDIMM can be dropped down.

1.44V
Weakened a bit ClkDrvStr and RTTPARK..
Added also a 120mm to cool these sticks directly (ugly thing)...


----------



## Audioboxer

Mach3.2 said:


> You can send a set to him 😜


lol, before I buy more memory I think I need a new phone, this camera on my phone is always blurry even although lens is clear!

@Veii do any of these help a bit more with PCB or too blurry?





































lol at how poor RipJaw heatsink coverage is


----------



## mongoled

Oh my word, thats pathetic coverage


----------



## Mach3.2

The thermal tape probably only covers about half the DRAM IC lol.....


----------



## Audioboxer

mongoled said:


> Oh my word, thats pathetic coverage


Now you know why I'm going to considering watercooling them lol. Even a third party heatsink would upgrade them.


----------



## ManniX-ITA

mongoled said:


> Oh my word, thats pathetic coverage


No, you don't understand; It's for a better aerodynamic Cx


----------



## rossi594

Did anybody try the new agesa 1.2.0.4 yet?


----------



## Audioboxer

rossi594 said:


> Did anybody try the new agesa 1.2.0.4 yet?


Not out for me yet, but seems soon



> What's new:
> 1. Update to COMBOAM4v2PI 1.2.0.4
> 2. SMU firmware updated for Vermeer, Cezanne and Picasso
> 3. TPM enabled by default











MSI First To Release AMD AGESA 1.2.0.4 BIOS Firmware For B550 & B450 Motherboards - Updated SMU & TPM Enabled By Default For Windows 11


MSI is the first motherboard manufacturer to release the latest AMD AGESA 1.2.0.4 BIOS Firmware for its B550 and B450 motherboards.




wccftech.com





*edit* - Oh wait, manual links at bottom. Just not updated here MSI MEG B550 UNIFY X Motherboard

I'll give it a go!


----------



## rossi594

Audioboxer said:


> Not out for me yet, but seems soon
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> MSI First To Release AMD AGESA 1.2.0.4 BIOS Firmware For B550 & B450 Motherboards - Updated SMU & TPM Enabled By Default For Windows 11
> 
> 
> MSI is the first motherboard manufacturer to release the latest AMD AGESA 1.2.0.4 BIOS Firmware for its B550 and B450 motherboards.
> 
> 
> 
> 
> wccftech.com
> 
> 
> 
> 
> 
> *edit* - Oh wait, manual links at bottom. Just not updated here MSI MEG B550 UNIFY X Motherboard
> 
> I'll give it a go!


I am especially curious if it affects whea behavior


----------



## Audioboxer

rossi594 said:


> I am especially curious if it affects whea behavior


Flashing now. Doubt it will do anything for WHEA but I'll let you know. 1900 is fine here, even with low IF voltages. Anything above and its a WHEA party. Even 1933.


----------



## ManniX-ITA

Eder said:


> No beta yet but I can unlock the latest release if you need it. Flashing beta right now on the x570 Unify.
> 
> Btw only placing these posts here because of the FCLK instability we experience lately.
> 
> They changed the PCI subsystem menu you can only choose chipset generation, option to change generation on PCI lanes is gone in my case.


@Eder 

Could you please unlock latest A43 for Unify-X? 






MEG_B550_UNIFY-X_BIOS_A43.zip







drive.google.com





Thanks! 🙏

The 1.2.0.4 BIOSes are at:









MSI First To Release AMD AGESA 1.2.0.4 BIOS Firmware For B550 & B450 Motherboards - Updated SMU & TPM Enabled By Default For Windows 11


MSI is the first motherboard manufacturer to release the latest AMD AGESA 1.2.0.4 BIOS Firmware for its B550 and B450 motherboards.




wccftech.com


----------



## Audioboxer

Hmm, interesting.

I'll start with the expected, 1933/1966/2000 are still WHEA factories. 2000 especially. They all boot, but WHEEEEAAAAAA!

1900 gave me a single WHEA on my old voltages, VDDG CCD/IOD at 0.925v










That 12:18:36 is me booting 1900 at VDDG 0.925v. Everything earlier is me celebrating 1933-2000 with my WHEA buddies.

When you upgrade this MSI BIOS you lose all your old profiles, so have to manually re-enter everything. So I just auto'd out VDDG and get this










No WHEA now.

So it seems whatever has changed behind the scenes is going to need me to redo my voltages. Not a big issue though, but interesting nonetheless. One could ask was 0.925v really stable on the prior BIOS, but there was 100% no WHEA, TM5 was passing fine, Corecycler ran fine, etc.

So I guess my early finding with 1.2.0.4 is if you were running low IF voltages maybe expect to need a small bump to avoid WHEA at 1900.

*Edit* - I love how my RAM on auto does 666 tRFC, this DR 2x16GB is indeed the damn devil


----------



## mongoled

Audioboxer said:


> *Edit* - I love how my RAM on auto does 666 tRFC, this DR 2x16GB is indeed the damn devil


You will find its not just yours that does it

Wait till you buy a watt-o-meter and you see 66.6W when you post

😂😂


----------



## Audioboxer

So someone in here will shoot me for doing this, but, I've got to ask. So, disclaimer, I'm a bad man for GDM enabled, but, that out of the way, here comes the questions....










So, everything on auto in my BIOS apart from a few things (basic CPU changes such as peferred cores/etc, but no PBO, no curve and no overclocking), those being manually setting VDIMM, VSOC and VDDP. VSOC on auto hovers around 1.08v which I tend to find _can_ be a bit low for 3800. VDDP at 0.86v as that was fine previously.

I got into the third cycle with loose auto timings and 3800 flat 14s. I wasn't surprised 1.52v might not be enough for 3800 flat 14s, regardless of the secondary timings.










Bump up to 1.55v, which some GSKILL kits are even binned at for retail sale. Near instant crash on 6. In fact, I've done it multiple times and quickest crash was around 15 seconds.

My question would then be, why? RAM is about 38 degrees under TM5.










Seeing as the only other variable off AUTO was VDDP, I tried dropping it to 0.8v. Test on average could go a little further and was less likely to crash on 6.

Could this somehow be related to Veii saying he thought my PCB was rev 3 with short traces and it is more voltage sensitive? I mean, I wouldn't like to think my B-die will struggle to go above 1.52~1.53v. Then again, with GDM enabled and Rtt/resistances on auto I'm willing to take my education and be told I'm an idiot 

*edit -*










0.83v on VDDP again bypasses the quick fall on 6, but still drops quite early to an error. So is this some balancing act between VDDP and VDIMM for me if I want to try run something like 1.55v?

*edit2 - *










Just for science, of course, making sure I wasn't going to be worrying about what my RAM is rated for.


----------



## umea

Audioboxer said:


> lol, before I buy more memory I think I need a new phone, this camera on my phone is always blurry even although lens is clear!
> 
> @Veii do any of these help a bit more with PCB or too blurry?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> lol at how poor RipJaw heatsink coverage is


I have a ripjaw set as well, it was so bad that I had to tear it off and now have a 120mm fan blowing on them directly. It was over 50 degrees during TM5 bad, even with a fan on it.


----------



## Thanh Nguyen

need help guys. What cause massive penalty to latency? I remember when I first got the system, the latency is in the 50s. As low as 53 at 4000/2000, but now latency is in the 60s.


----------



## rossi594

@Audioboxer Thanks for testing, some of the wheas are "fixable" with the right voltages, but usually not the ones that appear in a herd of 100. I also had whea's at 1900 when stable before on 1.2.0.3 patch b. It's a shame amd doesn't use the same fclk syncing above 1900 ...


----------



## domdtxdissar

Audioboxer said:


> So someone in here will shoot me for doing this, but, I've got to ask. So, disclaimer, I'm a bad man for GDM enabled, but, that out of the way, here comes the questions....
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> So, everything on auto in my BIOS apart from a few things (basic CPU changes such as peferred cores/etc, but no PBO, no curve and no overclocking), those being manually setting VDIMM, VSOC and VDDP. VSOC on auto hovers around 1.08v which I tend to find _can_ be a bit low for 3800. VDDP at 0.86v as that was fine previously.
> 
> I got into the third cycle with loose auto timings and 3800 flat 14s. I wasn't surprised 1.52v might not be enough for 3800 flat 14s, regardless of the secondary timings.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Bump up to 1.55v, which some GSKILL kits are even binned at for retail sale. Near instant crash on 6. In fact, I've done it multiple times and quickest crash was around 15 seconds.
> 
> My question would then be, why? RAM is about 38 degrees under TM5.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Seeing as the only other variable off AUTO was VDDP, I tried dropping it to 0.8v. Test on average could go a little further and was less likely to crash on 6.
> 
> Could this somehow be related to Veii saying he thought my PCB was rev 3 with short traces and it is more voltage sensitive? I mean, I wouldn't like to think my B-die will struggle to go above 1.52~1.53v. Then again, with GDM enabled and Rtt/resistances on auto I'm willing to take my education and be told I'm an idiot
> 
> *edit -*
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 0.83v on VDDP again bypasses the quick fall on 6, but still drops quite early to an error. So is this some balancing act between VDDP and VDIMM for me if I want to try run something like 1.55v?
> 
> *edit2 - *
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Just for science, of course, making sure I wasn't going to be worrying about what my RAM is rated for.


Do you also get errors at IOD 1050-1080mv ?

Anyway, i did try a run @ RTT 7-2-5 and it failed after awhile (15 cycles), back to 7-3-3 which just completed full 25 cycle run.








vs









_edit_



Thanh Nguyen said:


> need help guys. What cause massive penalty to latency? I remember when I first got the system, the latency is in the 50s. As low as 53 at 4000/2000, but now latency is in the 60s.


Have you checked for WHEA errors ?

exp.fr which also have bought a "binned" 5950x from the same source as you, have the same experience i believe.. The seller is showing Cinebench screenshots at 2000:4000 speeds (cinebench don't really care about memory) and naturally ppl think they can run that speeds, but they are have having massive amounts of WHEA errors @ fclk above 1933 which is giving reduced performance..


----------



## Audioboxer

Audioboxer said:


> So someone in here will shoot me for doing this, but, I've got to ask. So, disclaimer, I'm a bad man for GDM enabled, but, that out of the way, here comes the questions....
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> So, everything on auto in my BIOS apart from a few things (basic CPU changes such as peferred cores/etc, but no PBO, no curve and no overclocking), those being manually setting VDIMM, VSOC and VDDP. VSOC on auto hovers around 1.08v which I tend to find _can_ be a bit low for 3800. VDDP at 0.86v as that was fine previously.
> 
> I got into the third cycle with loose auto timings and 3800 flat 14s. I wasn't surprised 1.52v might not be enough for 3800 flat 14s, regardless of the secondary timings.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Bump up to 1.55v, which some GSKILL kits are even binned at for retail sale. Near instant crash on 6. In fact, I've done it multiple times and quickest crash was around 15 seconds.
> 
> My question would then be, why? RAM is about 38 degrees under TM5.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Seeing as the only other variable off AUTO was VDDP, I tried dropping it to 0.8v. Test on average could go a little further and was less likely to crash on 6.
> 
> Could this somehow be related to Veii saying he thought my PCB was rev 3 with short traces and it is more voltage sensitive? I mean, I wouldn't like to think my B-die will struggle to go above 1.52~1.53v. Then again, with GDM enabled and Rtt/resistances on auto I'm willing to take my education and be told I'm an idiot
> 
> *edit -*
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 0.83v on VDDP again bypasses the quick fall on 6, but still drops quite early to an error. So is this some balancing act between VDDP and VDIMM for me if I want to try run something like 1.55v?
> 
> *edit2 - *
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Just for science, of course, making sure I wasn't going to be worrying about what my RAM is rated for.


Okay, self-quote, but now I feel like my head is up my own arse 










I decided to put everything on AUTO, even VSOC and VDDP. VDDP for some reason instead of autoing at 0.9v decided to jump to 1.09v. Seems way too high, but I decided, screw it, I'll run a TM5.

Then the above happens 

Less VDIMM voltage than the testing above for 3800 flat 14, less VSOC and a wonky VDDP at 1.09v. Can anyone help me explain *** is going on? Yes, I know GDM makes it harder to make sense of due to whatever it is doing behind the scenes, but why is my memory crashing on 1.52~1.55v but manages to squeak out a pass on 1.5v? Why did it seem like higher VDDP in the first post was causing failures more quickly yet now the memory is like "Bro, I don't even care about 1.09v on VDDP "?


----------



## rossi594

Audioboxer said:


> Okay, self-quote, but now I feel like my head is up my own arse
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I decided to put everything on AUTO, even VSOC and VDDP. VDDP for some reason instead of autoing at 0.9v decided to jump to 1.09v. Seems way too high, but I decided, screw it, I'll run a TM5.
> 
> Then the above happens
> 
> Less VDIMM voltage than the testing above for 3800 flat 14, less VSOC and a wonky VDDP at 1.09v. Can anyone help me explain *** is going on? Yes, I know GDM makes it harder to make sense of due to whatever it is doing behind the scenes, but why is my memory crashing on 1.52~1.55v but manages to squeak out a pass on 1.5v? Why did it seem like higher VDDP in the first post was causing failures more quickly yet now the memory is like "Bro, I don't even care about 1.09v on VDDP "?


Shouldn't vddp be derived from vsoc? It's higher. Something is up here.


----------



## Audioboxer

rossi594 said:


> Shouldn't vddp be derived from vsoc? It's higher. Something is up here.


It autos to 0.9v on 3600 C14.










1.49v lol


----------



## sonixmon

Audioboxer said:


> Do you mean in AIDA?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This is with 34.3 and DDs at 2/4
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Just benched that there with
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But thanks for this mongoled, my ProcODT is no doubt unstable I didn't know about the tip you provided. Which I'll check now!


I tried this too and though I could run ProcODT @28-34 and pass it seems the best AIDA64 results are at 32 so I moved one step down to 32 in my profile.



Thanh Nguyen said:


> need help guys. What cause massive penalty to latency? I remember when I first got the system, the latency is in the 50s. As low as 53 at 4000/2000, but now latency is in the 60s.
> 
> View attachment 2523956


Also check running background apps and services, if it is not WHEA. Try a safemode run to eliminate them easily.


----------



## Audioboxer

Audioboxer said:


> It autos to 0.9v on 3600 C14.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 1.49v lol


1.48v brought first errors










So










Back up to 1.5v for another 3 cycle.

I believe my VSOC is about 1.1v on auto, it's just this MSI board droops quite a bit on VSOC which makes it end up less than VDDP.

But I really do need a bit of guidance from Veii on my adventures today and what the heck is going on with this memory. Hopefully first, confirmation what this PCB is. Then hopefully some insight into what is going on with my VDDP results and VDIMM looking like my RAM struggles with 1.54~1.55v.

I guess for now I will manually drop the VDDP a bit and see how it gets on.

*edit* - Quick example, again










Only change from above is putting the VDIMM to 1.55v, crash on 6 right away. Like here.


----------



## TimeDrapery

Audioboxer said:


> So someone in here will shoot me for doing this, but, I've got to ask. So, disclaimer, I'm a bad man for GDM enabled, but, that out of the way, here comes the questions....
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> So, everything on auto in my BIOS apart from a few things (basic CPU changes such as peferred cores/etc, but no PBO, no curve and no overclocking), those being manually setting VDIMM, VSOC and VDDP. VSOC on auto hovers around 1.08v which I tend to find _can_ be a bit low for 3800. VDDP at 0.86v as that was fine previously.
> 
> I got into the third cycle with loose auto timings and 3800 flat 14s. I wasn't surprised 1.52v might not be enough for 3800 flat 14s, regardless of the secondary timings.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Bump up to 1.55v, which some GSKILL kits are even binned at for retail sale. Near instant crash on 6. In fact, I've done it multiple times and quickest crash was around 15 seconds.
> 
> My question would then be, why? RAM is about 38 degrees under TM5.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Seeing as the only other variable off AUTO was VDDP, I tried dropping it to 0.8v. Test on average could go a little further and was less likely to crash on 6.
> 
> Could this somehow be related to Veii saying he thought my PCB was rev 3 with short traces and it is more voltage sensitive? I mean, I wouldn't like to think my B-die will struggle to go above 1.52~1.53v. Then again, with GDM enabled and Rtt/resistances on auto I'm willing to take my education and be told I'm an idiot
> 
> *edit -*
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 0.83v on VDDP again bypasses the quick fall on 6, but still drops quite early to an error. So is this some balancing act between VDDP and VDIMM for me if I want to try run something like 1.55v?
> 
> *edit2 - *
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Just for science, of course, making sure I wasn't going to be worrying about what my RAM is rated for.


I wouldn't say you are an idiot, GDM set to Enabled just isn't the flavor of the day

If it works and it meets your "needs" there's nothing "wrong" with it

It's pretty common for mobos to keep increasing voltages past commonly accepted values, again, if it works then it works

I'll bet you can get what you want from that kit, I'd start with loosening secondaries/tertiaries and giving it some breathing room if you're gonna make another run at 1T with or without setup timings, they're only adding picoseconds anyways


----------



## Audioboxer

TimeDrapery said:


> I wouldn't say you are an idiot, GDM set to Enabled just isn't the flavor of the day
> 
> If it works and it meets your "needs" there's nothing "wrong" with it
> 
> It's pretty common for mobos to keep increasing voltages past commonly accepted values, again, if it works then it works


lol thanks but GDM will be coming off. The above has only come about today as I updated to a new BIOS and was testing FCLK again. At the same time I thought why not play around with memory on AUTO as I never really did that since buying this kit.

Where I have a bit of a knowledge gap right now is why my b-die seems to be this sensitive to VDIMM. I'm only keeping things on AUTO at the moment as it lets me test memory like it will be as factory standard whilst I play around with a few variables. I never managed to get 3800 flat 14 passing anything at 2T in the prior weeks but I also don't think I ever tested it at 1.5v. My perception was to be at around 1.55v. Now I'm wondering if all the testing I was trying in the last 2 weeks was getting thrown off because my memory is struggling at over 1.53v.

And if it is I'm looking for some insight into why. I've never heard of b-die crapping out at such a "low voltage". Most stories I've read are it will happily keep scaling up to 1.6v and maybe even beyond if cooled properly. Throw into the mix Veii already thinks I'm running a revision 3 PCB which may explain why I'm facing some challenges those on more common PCBs don't seem to. He said my traces seemed short and that could mean voltage sensitive, so I hope the new pictures I took can help when he has the time to see them.

I'm going to manually drop VDDP to something more reasonable and see how it gets on with flat 14. If it can pass at least a 3 cycle then it further looks like my issue is stability at 1.55v with this memory. Which in some regards would be disappointing if I can't scale above that even with proper cooling.


----------



## ManniX-ITA

Audioboxer said:


> I believe my VSOC is about 1.1v on auto, it's just this MSI board droops quite a bit on VSOC which makes it end up less than VDDP.


Your VSOC is getting auto-corrected to 1.14-1.15V due to the VDDP at 1100mV.
Which is not a good thing, you have to expect erratic results and instability.
VDDP at 1100mV is unnecessarily high and considered dangerous over 1050mV.
I never suffered catastrophic issues but it almost never helped me at that voltage except very exotic settings at FCLK 2067.


----------



## Audioboxer

ManniX-ITA said:


> Your VSOC is getting auto-corrected to 1.14-1.15V due to the VDDP at 1100mV.
> Which is not a good thing, you have to expect erratic results and instability.
> VDDP at 1100mV is unnecessarily high and considered dangerous over 1050mV.
> I never suffered catastrophic issues but it almost never helped me at that voltage except very exotic settings at FCLK 2067.


It doesn't seem to matter, anyway










Manually dropped to a more reasonable but still quite high 0.93v. The only reason I left it there in previous tests was to minimise how many variables I was playing with and because I thought a higher VDDP might have been helping the 3800 flat 14 pass. I was running VDDP as low as 0.86v with my stable settings yesterday before this bios update lol.

Seems that I've narrowed things down to my memory is crapping out at 1.55v and I need to figure out why this is. Is it rev 3 PCB related?

In the mean time I'll try and see if these auto settings, with VDDP manually set, can pass anything at 2T GDM disabled. Hopefully Veii can help shed some more light on my PCB later and this seeming 1.54~1.55v ceiling I might have.


----------



## MrHoof

So ordered a 32gb 3600 cl14-15-15-34 kit, gonna arrive in 1-2 days. Gonna be intresting if that will work at 1T aswell so far tested 2 SR kits and both did 1T.


----------



## ManniX-ITA

Audioboxer said:


> Seems that I've narrowed things down to my memory is crapping out at 1.55v and I need to figure out why this is. Is it rev 3 PCB related?


Are you sure it's not temp related?


----------



## sonixmon

MrHoof said:


> So ordered a 32gb 3600 cl14-15-15-34 kit, gonna arrive in 1-2 days. Gonna be intresting if that will work at 1T aswell so far tested 2 SR kits and both did 1T.


That is the kit (or similar) that I ordered. runs 3800CL14 but is temp sensitive and needs GDM on or setup 55-56 (any timings over when over 3200mhz). Could be silicone lottery but who knows. My last kit (non B-Die) would do 3800CL16 1T Pure but CL16 was the lower limit. Still an improvement but probably not worth it in the end.

For grins I emailed Gskill and their response was 2T or GDM is normally required over 3200 and that is normal. Also mentioned MB and IMC but I told them my previous ram kit had no issues at CL16. They still said that's normal etc.

GL and keep us posted!


----------



## Audioboxer

ManniX-ITA said:


> Are you sure it's not temp related?


Crashing on 6 in 15~20 seconds? My temp at that point is lucky to be 34~35 degrees lol. My max temps are like 40 degrees after 20+ mins of TM5.










Some issues on 2T GDM disabled, but at least it's not error 6/12/2 lmao.

Here is my temps from that run above


----------



## ManniX-ITA

Audioboxer said:


> Here is my temps from that run above


Looks good.
Maybe this A43 BIOS sucks badly? 
Just wondering


----------



## Audioboxer

ManniX-ITA said:


> Looks good.
> Maybe this A43 BIOS sucks badly?
> Just wondering


Nah this won't be to do with the BIOS. For like 2 weeks now I was fighting to try and achieve flat 14 and/or 1T pure. The profile I was running before this BIOS update is here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread I was messing with ProcODT in that post but timings were previously 25 cycle stable at 34.3.

You'll notice the voltage is 1.5v VDIMM. Weeks ago I just decided 1.5v would be my by choice ceiling for tCL15. Not that I wouldn't go over but I wanted to see how hard I could push at that voltage. When I was trying for flat 14 or 1T Pure I was throwing above 1.5v at it and getting a lot of 6 errors, like I was earlier today even with the memory on loose timings, auto, GDM enabled.

It's complete coincidence today simply because my BIOS defaulted due to an upgrade I thought I'll mess around with flat 14 again and see if anything has changed with AGESA. When I got this ram my first port of call was GDM disabled. Didn't even bother testing with it on. Doing it today has uncovered what seems to be a voltage ceiling on this b-die of around 1.5v before instability. Which could also explain any issues I was having in the past 2 weeks when I tried anything above 1.5v, even trying to drop tRFC lower on my tCL15 profile.

The RAM is rated 3600 14-14-14-14 1.45v. To only have a 0.05v overheard would be pretty poor for b-die if you ask me. Veii said a few days ago it looked like I had a rev 3 PCB, so I'm really now just waiting for him to see those new pictures I took to possibly confirm it. It may be the case rev 3 PCBs are really bad for voltage above 1.5v. Sample size of them is pretty low, even Veii hasn't seen many of them. Stay tuned I guess, especially anyone who was looking at these 3600 flat 14 rated GSKILL bins.










In other news, error 8 = error 1 which can be voltage related so I took VSOC off manual and gave it 1.125v. ClkDrvStr to 30 as well, but I'm going to guess removing the 8's from this quick cycle with GDM disabled was VSOC.

With all the timings still on auto might now give this a 25 cycle just to see if it can actually pass with 3800 flat 14. Worry about timings/Rtts later.

I just wanted to update my MSI BIOS then go back to my CPU/RAM settings that were working fine and now I've opened a whole new can of worms  Though I do want to get to the bottom of what is going on with this set of RAM in regards to voltage/100% what PCB it is.


----------



## rossi594

Audioboxer said:


> 1.48v brought first errors
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> So
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Back up to 1.5v for another 3 cycle.
> 
> I believe my VSOC is about 1.1v on auto, it's just this MSI board droops quite a bit on VSOC which makes it end up less than VDDP.
> 
> But I really do need a bit of guidance from Veii on my adventures today and what the heck is going on with this memory. Hopefully first, confirmation what this PCB is. Then hopefully some insight into what is going on with my VDDP results and VDIMM looking like my RAM struggles with 1.54~1.55v.
> 
> I guess for now I will manually drop the VDDP a bit and see how it gets on.
> 
> *edit* - Quick example, again
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Only change from above is putting the VDIMM to 1.55v, crash on 6 right away. Like here.


Looks like A2 to me.


----------



## Audioboxer

rossi594 said:


> Looks like A2 to me.


Any known challenges with A2 and a VDIMM ceiling? Here is the post where Veii thought it might be revision 3 [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread



> You can recognize Rev.3 by having long direct traces. "Super short" traces
> As A1 & A2 are "short" trace layout - yet have curvatures.


Though if it is A2, from that Veii post



> A2 was known to need more current ~ in order to even function


Meaning more current might be needed to support higher voltages???


----------



## TimeDrapery

Audioboxer said:


> Nah this won't be to do with the BIOS. For like 2 weeks now I was fighting to try and achieve flat 14 and/or 1T pure. The profile I was running before this BIOS update is here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread I was messing with ProcODT in that post but timings were previously 25 cycle stable at 34.3.
> 
> You'll notice the voltage is 1.5v VDIMM. Weeks ago I just decided 1.5v would be my by choice ceiling for tCL15. Not that I wouldn't go over but I wanted to see how hard I could push at that voltage. When I was trying for flat 14 or 1T Pure I was throwing above 1.5v at it and getting a lot of 6 errors, like I was earlier today even with the memory on loose timings, auto, GDM enabled.
> 
> It's complete coincidence today simply because my BIOS defaulted due to an upgrade I thought I'll mess around with flat 14 again and see if anything has changed with AGESA. When I got this ram my first port of call was GDM disabled. Didn't even bother testing with it on. Doing it today has uncovered what seems to be a voltage ceiling on this b-die of around 1.5v before instability. Which could also explain any issues I was having in the past 2 weeks when I tried anything above 1.5v, even trying to drop tRFC lower on my tCL15 profile.
> 
> The RAM is rated 3600 14-14-14-14 1.45v. To only have a 0.05v overheard would be pretty poor for b-die if you ask me. Veii said a few days ago it looked like I had a rev 3 PCB, so I'm really now just waiting for him to see those new pictures I took to possibly confirm it. It may be the case rev 3 PCBs are really bad for voltage above 1.5v. Sample size of them is pretty low, even Veii hasn't seen many of them. Stay tuned I guess, especially anyone who was looking at these 3600 flat 14 rated GSKILL bins.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> In other news, error 8 = error 1 which can be voltage related so I took VSOC off manual and gave it 1.125v. ClkDrvStr to 30 as well, but I'm going to guess removing the 8's from this quick cycle with GDM disabled was VSOC.
> 
> With all the timings still on auto might now give this a 25 cycle just to see if it can actually pass with 3800 flat 14. Worry about timings/Rtts later.
> 
> I just wanted to update my MSI BIOS then go back to my CPU/RAM settings that were working fine and now I've opened a whole new can of worms  Though I do want to get to the bottom of what is going on with this set of RAM in regards to voltage/100% what PCB it is.


I don't have much experience with GDM set to Enabled but I do recall, from my brief episodes of poking at it, VDIMM was something it didn't seem to like as much as when GDM is set to Disabled

1.5000V was about where the DIMMs started to get uncomfortable for me with the GDM enabled, unfortunately for knowledge... It's also when I flipped it to Disabled


----------



## Audioboxer

TimeDrapery said:


> I don't have much experience with GDM set to Enabled but I do recall, from my brief episodes of poking at it, VDIMM was something it didn't seem to like as much as when GDM is set to Disabled
> 
> 1.5000V was about where the DIMMs started to get uncomfortable for me with the GDM enabled


Good to know that, that might also be an issue. GSKILL does sell 1.55v rated b-die kits, but they like many of their bins will be hand-picked to handle whatever a default BIOS will throw at them at the rated voltage.

Even with GDM off though and the past 2 weeks I spent experimenting it does on reflection make sense to me going above 1.5v was adding to issues. I kept finding myself coming back to 1.5v 2T or 1T with setup timings.

*edit* - Quick way to test the above










Same GDM disabled profile that just passed a 3 cycle at 1.5v, boom, the usual crash on 6 with something like 1.55v.

Seems my PCB is just instantly crashing on VDIMM above 1.5v. I have to say if there isn't an "answer" for this, then thank goodness I haven't watercooled this set yet (void warranty). B-die that can't reliably go above 1.5v is pretty "pointless". In which case I'd consider returning this given what I paid for it. So here is hoping someone has some answers and/or solutions, whether it's resistance/current related or something. It's a B550 Unify X, so if you want a capable 2 DIMM board you couldn't ask for more lol.


----------



## TimeDrapery

Audioboxer said:


> Good to know that, that might also be an issue. GSKILL does sell 1.55v rated b-die kits, but they like many of their bins will be hand-picked to handle whatever a default BIOS will throw at them at the rated voltage.
> 
> Even with GDM off though and the past 2 weeks I spent experimenting it does on reflection make sense to me going above 1.5v was adding to issues. I kept finding myself coming back to 1.5v 2T or 1T with setup timings.


Righteous, it does make sense considering "binning" as my XMP defaults to 1.35000V seeing as it's 3200CL14

The Auto rules for VDDP are interesting, it used to be talked about as an "error" or a "bad prediction" when it would yeet the voltage that high... Looking at Robert Hallock's entry in the community sheets he's not running it that high on whatever Zen 2 processor he's got on there so who knows


----------



## Audioboxer

Okay, school boy attending class










Error 6 quickly = IMC crash due to VDIMM voltage, I've learned that from my testing above and earlier.

But IMC ≠ PCB. For example










A PCB crash is a different error.

I, however, have been using the terms IMC and PCB interchangeably as I thought they were both the same thing, the brains of the DDR4 memory. Therefore when I was getting these 6 crashes I have just been saying for about 10+ posts now "my memory can't handle above 1.5V!".

From good old Google and trying to research PCBs it seems I've just learned the IMC is related to the CPU, so in my case, my 5950x? So does this mean going above 1.5v on my RAM is causing my CPU to _crash_, which in turn is causing the ram instability?


----------



## rossi594

Audioboxer said:


> Any known challenges with A2 and a VDIMM ceiling? Here is the post where Veii thought it might be revision 3 [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> 
> Though if it is A2, from that Veii post
> 
> 
> 
> Meaning more current might be needed to support higher voltages???


A2 gets up to higher frequencies easier, A0 in combination with the right mainbaord can time better. But A2 is pretty much the go to these days and most of the mainboards work better with it.


----------



## Audioboxer

rossi594 said:


> A2 gets up to higher frequencies easier, A0 in combination with the right mainbaord can time better. But A2 is pretty much the go to these days and most of the mainboards work better with it.


Interesting, thanks. Does Veii post make sense to you though in regards to thinking I had ultra short traces?


----------



## mongoled

Audioboxer said:


> I've just learned the IMC is related to the CPU


Your a brave man

😁😁


----------



## Audioboxer

mongoled said:


> Your a brave man
> 
> 😁😁


So am I right or wrong in this instance? lol

I mean, I'll be the first to say I'm a walking example in this topic of man stumbles into a room of experts and makes an arse of themselves


----------



## ManniX-ITA

Audioboxer said:


> IMC is related to the CPU


Yes, IMC stands for Integrated Memory Controller.
Higher VSOC can help in that case, but as you can see at the end of the description can be also related to RAM voltage: "give it +1 VDIMM".
ProcODT, SCL, tWRRD are also mentioned.
Depends on the situation.
I guess means that the IMC can't handle properly the DRAM due to many reasons.
Sometimes the VDIMM is not appropriate for the CAD_BUS/ProcODT settings, too high or too low.
Or the ProcODT is wrong and whatever else you change will not help.
Depends on the context


----------



## Audioboxer

ManniX-ITA said:


> Yes, IMC stands for Integrated Memory Controller.
> Higher VSOC can help in that case, but as you can see at the end of the description can be also related to RAM voltage: "give it +1 VDIMM".
> ProcODT, SCL, tWRRD are also mentioned.
> Depends on the situation.
> I guess means that the IMC can't handle properly the DRAM due to many reasons.
> Sometimes the VDIMM is not appropriate for the CAD_BUS/ProcODT settings, too high or too low.
> Or the ProcODT is wrong and whatever else you change will not help.
> Depends on the context


Pumping the ram voltage up is what is causing the crashing though lol.

But thankfully thanks to this amazing topic  all of today's stressing about my RAM is _probably_ unfounded. It's likely my IMC crashing and not some RAM voltage ceiling. Question then becomes figuring out how to fix this. Can it be anything to do with IOD? Or is that just IF stability?

I guess this is quite normal once going north of 1.5v?


----------



## MrHoof

found those pictures on german review of a gskill tridentz 3800 cl14-16-16 kit that looks I would say identical to yours @Audioboxer and @domdtxdissar seems to have a extra component on the first picture in the middle area. Am no help tho on identifying them but the pictures should help maybe.


----------



## domdtxdissar

domdtxdissar said:


> Do you also get errors at IOD 1050-1080mv ?
> 
> Anyway, i did try a run @ RTT 7-2-5 and it failed after awhile (15 cycles), back to 7-3-3 which just completed full 25 cycle run.
> 
> View attachment 2523959
> 
> vs
> View attachment 2523960
> 
> 
> _edit_
> 
> 
> 
> Have you checked for WHEA errors ?
> 
> exp.fr which also have bought a "binned" 5950x from the same source as you, have the same experience i believe.. The seller is showing Cinebench screenshots at 2000:4000 speeds (cinebench don't really care about memory) and naturally ppl think they can run that speeds, but they are have having massive amounts of WHEA errors @ fclk above 1933 which is giving reduced performance..


Managed to lower the vdimm to 1.545v which is the lowest i can run these settings with. (1.54v failed after ~1 hour)









@ *MrHoof *and* Audioboxer*

*The ultimate HARDWARELUXX Samsung 8Gb B-Die list - all manufacturers (06.09.21)*




Spoiler: Older information



A1 or A2 PCB - easy recognition


----------



## MrHoof

A1 gets close but none of those match. Also aren´t Dual rank PCB diffrent to single rank ones cause i think those in that post are SR?


----------



## Audioboxer

MrHoof said:


> found those pictures on german review of a gskill tridentz 3800 cl14-16-16 kit that looks I would say identical to yours @Audioboxer and @domdtxdissar seems to have a extra component on the first picture in the middle area. Am no help tho on identifying them but the pictures should help maybe.


Yeah that looks very similar, I need to get some better pictures of mine, but if the above is a 2x16GB kit I dare say that is the same PCB.

I have no idea how to identify it either though lol.


----------



## ManniX-ITA

Audioboxer said:


> It's likely my IMC crashing and not some RAM voltage ceiling. Question then becomes figuring out how to fix this. Can it be anything to do with IOD? Or is that just IF stability?
> 
> I guess this is quite normal once going north of 1.5v?


Could be you need adjusting IOD/SOC/etc...
Above 1.5V lots of things can go wrong, maybe you need different ProcODT, CAD, RTT...
It's where usually it's too high for "normal" timings and too low for something better.
After that both my DR kits need 1.6V and more but then the temperature becomes an issue.


----------



## domdtxdissar

Seems like pretty much all gskill highend sets are "a2 black" PCB

*HARDWARELUXX SPD database + instructions for reading out IC (on hold)*


----------



## Audioboxer

ManniX-ITA said:


> Could be you need adjusting IOD/SOC/etc...
> Above 1.5V lots of things can go wrong, maybe you need different ProcODT, CAD, RTT...
> It's where usually it's too high for "normal" timings and too low for something better.
> After that both my DR kits need 1.6V and more but then the temperature becomes an issue.


Thanks. Today has given me hope for being able to achieve 3800 flat 14 anyway lol. I just tried taking IOD off auto in my BIOS and putting it to 1.05 and for some reason it's locked at 1.0 or 0.99 as ZenTimings shows. I guess this is why on AUTO it isn't going to like 1.05 which I've seen it do before.

Anyone know a reason why IOD wouldn't go above 1.0? Other settings in the BIOS that might limit it? Keep in mind I just upgraded my BIOS so my CPU side of things are on AUTO just now.

Hopefully not a bug or something with AGESA 1.2.0.4 lol. Or maybe ZenTimings isn't reading the value properly on AGESA 1.2.0.4?


----------



## MrHoof

domdtxdissar said:


> Seems like pretty much all gskill highend sets are "a2 black" PCB
> 
> *HARDWARELUXX SPD database + instructions for reading out IC (on hold)*


That list seems outdated there is no high bin 16gb on it. Apperently thaiphoon reads it as b1 might be a newer pcb type.


----------



## sonixmon

Audioboxer said:


> Pumping the ram voltage up is what is causing the crashing though lol.
> 
> But thankfully thanks to this amazing topic  all of today's stressing about my RAM is _probably_ unfounded. It's likely my IMC crashing and not some RAM voltage ceiling. Question then becomes figuring out how to fix this. Can it be anything to do with IOD? Or is that just IF stability?
> 
> I guess this is quite normal once going north of 1.5v?


I have found when I up the voltage I have to reconfigure the ProcODT, CAD, RTT etc.


----------



## Audioboxer

sonixmon said:


> I have found when I up the voltage I have to reconfigure the ProcODT, CAD, RTT etc.


This is definitely part of the problem. I've gone full circle today making mistakes, showing my knowledge gaps, calling an IMC a PCB and even for a brief spell running TM5 with GDM enabled 

But, learning is all part of the game. And I still need to learn how to run 1.51~1.52v+ without the IMC crashing on these sticks.

And now figure out why I can't seem to run IOD higher than 1.0v


----------



## TimeDrapery

ManniX-ITA said:


> Yes, IMC stands for Integrated Memory Controller.
> Higher VSOC can help in that case, but as you can see at the end of the description can be also related to RAM voltage: "give it +1 VDIMM".
> ProcODT, SCL, tWRRD are also mentioned.
> Depends on the situation.
> I guess means that the IMC can't handle properly the DRAM due to many reasons.
> Sometimes the VDIMM is not appropriate for the CAD_BUS/ProcODT settings, too high or too low.
> Or the ProcODT is wrong and whatever else you change will not help.
> Depends on the context


This is a great explanation, thanks @ManniX-ITA! 

tWRRD as well as its mate are related to the IMC


----------



## TimeDrapery

Double post, sorry!


----------



## Audioboxer

My BIOS now has both VDDG set at 1.05v yet this is how they are reading in ZenTimings. Does HWINFO64 report these voltages (can't find them under sensor status)? Either there is an issue with AGESA 1.2.0.4 or ZenTimings has an issue with AGESA 1.2.0.4 and can't read from BIOS correctly.

Unless something is locking them at 1.0v max?


----------



## TimeDrapery

Audioboxer said:


> My BIOS now has both VDDG set at 1.05v yet this is how they are reading in ZenTimings. Does HWINFO64 report these voltages (can't find them under sensor status)? Either there is an issue with AGESA 1.2.0.4 or ZenTimings has an issue with AGESA 1.2.0.4 and can't read from BIOS correctly.
> 
> Unless something is locking them at 1.0v max?


A lot of settings fields in your BIOS "translate" inputs to other settings fields... Check to see that your CBS/AMD Overclocking submenus aren't populated with inputs


----------



## Audioboxer

MrHoof said:


> found those pictures on german review of a gskill tridentz 3800 cl14-16-16 kit that looks I would say identical to yours @Audioboxer and @domdtxdissar seems to have a extra component on the first picture in the middle area. Am no help tho on identifying them but the pictures should help maybe.


Traced the source of these Does the new high-end RAM for Ryzen 5000 live up to its promise? - G.SKILL DDR4-3800 CL14 2x 16GB kit put through its paces | Page 3 | igor´sLAB

Even though that is the 3800CL14 bin it's probably very close to this 3600CL14 given this is a 14-14-14-14 bin.

Might have a poke around with some of those timings. Funny to see Igors Lab running with that 1.09v VDDP lol.

Would be good to get this PCB identified if it's not A2.



TimeDrapery said:


> A lot of settings fields in your BIOS "translate" inputs to other settings fields... Check to see that your CBS/AMD Overclocking submenus aren't populated with inputs


I will try and figure it out tomorrow, never had this issue previously and the only thing I've done in the last 24 hours is update the BIOS.

The BIOS reports the voltages have changed but ZenTimings insists otherwise.


----------



## TimeDrapery

Alrighty, back to work...

Here's the current effort










Last night's sleepy time effort was to increase ClkDrvStr to 60.0Ω which allowed me to trade my #2 for a #10... I'm not trying to trade up in errors though, I'm trying to resolve the one I already got! So, I rolled the config back and have now lowered AddrCmdDrvStr from 24.0Ω to 20.0Ω

The last #2 appeared roughly 52 minutes into testing so it's about 11 minutes remaining this go-around to see what's what

Well, JK, TM5 had its lunch stolen by Windows or something and decided to do an infinity test with no workload so I became frustrated and have decided to use OCCT Pro to stress test for a bit

In addition, here's some shots of the bench results and their standings... I think that's a pretty cool feature


































Even better... There's an option to run the test for a certain duration! No more hovering to see if time goes faster when you stare at the display... Yeah, right










Selecting the AVX2 option does warm up the DIMMs, I imagine they'll get hotter as the test continues... The only thing I wish for with this testing suite is some sort of output informing you of what error occurred during testing

It could be arbitrary like TM5, it's just nice to try and pin errors to fixes










I also love the addition of the 'Skins' feature with this version

Halfway there!










Okay, that's a good sign... I'll have to run TM5 again to see if it's improved and that #2 is eliminated










TM5 ran through just fine so far, no #2 so I'll keep drive strengths at 40.0Ω-20.0Ω-24.0Ω-24.0Ω meow

I'll run Karhu overnight as well and see what comes of that, the only other thing I can think of to do is to reduce tWTRS to 3










Anyways, if you did hang in through this and the last post, thanks... I hope this helps someone out and illuminates at least one way to reach 3800CL14 with 1T CR and no setup timings


----------



## Audioboxer

Can confirm BIOS is broken by MSI, VDDG voltages can't go above 0.99v lol. Well, with the Unify X bios anyway.


----------



## TimeDrapery

Audioboxer said:


> Can confirm BIOS is broken by MSI, VDDG voltages can't go above 0.99v lol. Well, with the Unify X bios anyway.


Oh jeez, how embarrassing for MSI 😂😂😂😂😂


----------



## Veii

WHEA #19 investigation continues
Setup, 6700XT (Samsung) + 5600X & ITX/AX Board

I think, the only reason for me not to WHEA right now, is pure coincidence
Either my ITX has Revision.03 and it continues to be random what you get ~ while this has buggy revision.02
(ProArt has guaranteed Rev.03)


Spoiler














Oor i always had Rev.02 (don't think so) and it only doesn't WHEA, as i erased at first the wrong ROM-Chip, soo my ethernet port is dead
Shops in germany keep selling the F4-4000C16D-16GTZNA 16-16-16 - as GTZN 16-19-19 (A2 PCB)
Glady it's still b-die, but just so people know


Spoiler























More information tomorrow
Tried downgrading to SMU 56.26
But windows didn't even want to load
Restored my SPI-Copy to it - but it didn't do anything. Downgraded to potentially fix PSP-FW ~ as that board came with patch-C 1900 Lock (SMU 56.34) , but nothing
Tomorrow i'll see what i can do. Young person doesn't trust cross-border shipping his gear sadly, but next month i get a 5950X to play with (X570 Tomahawk, 3080Ti FE, Team Group Argb 32Gb 3600C14)

At worst, board will be returned towards a ProArt or Strix-A
CPU , appears mediocre ~ 113 V/F score, maybe turns great with hydra, maybe not
Could also be returned as it WHEA's #19 on 1900 at any voltage

@Blameless was it you with the other ITX/AX ?
Can you check how many Error Sources are active ? 10 or 9
I get 9, he get's 10 on the same board, same SPI ROM, same bios profile ~ same typical OS
The only thing different between us two, was his Revision.02 Intel chip ~ which has a huge reddit post of issues & me with the fixed .03 (maybe) but rather dead NIC
(Also fails Intel's own Suite Adapter Tests)

It doesn't look to be the GPU, but LCLK for him is fixed at 5, for me at 1.
Uses PCie 4.0 full lanes ~ but LCLK DPM doesn't wiggle too.
==============================================
Also both Tests, even up to 61-0-0, keep erroring
I can not compare this ~ it makes issues with tCKE + RTT_WR
And with 1.65v, it's too risky dropping Powerdown (anything i change so far, results in failed stability)
See the posted result as unverified. Even when it holds up long and Bandwidth results appear similar between pure 1T and 1T + SETUP Timings
* EDIT: Could likely just be heat, where SETUP timings mess up my tCKE timings.


Spoiler


----------



## KedarWolf

TimeDrapery said:


> Alrighty, back to work...
> 
> Here's the current effort
> 
> View attachment 2523986
> 
> 
> Last night's sleepy time effort was to increase ClkDrvStr to 60.0Ω which allowed me to trade my #2 for a #10... I'm not trying to trade up in errors though, I'm trying to resolve the one I already got! So, I rolled the config back and have now lowered AddrCmdDrvStr from 24.0Ω to 20.0Ω
> 
> The last #2 appeared roughly 52 minutes into testing so it's about 11 minutes remaining this go-around to see what's what
> 
> Well, JK, TM5 had its lunch stolen by Windows or something and decided to do an infinity test with no workload so I became frustrated and have decided to use OCCT Pro to stress test for a bit
> 
> In addition, here's some shots of the bench results and their standings... I think that's a pretty cool feature
> 
> View attachment 2523988
> 
> View attachment 2523989
> 
> View attachment 2523990
> 
> View attachment 2523991
> 
> 
> Even better... There's an option to run the test for a certain duration! No more hovering to see if time goes faster when you stare at the display... Yeah, right
> 
> View attachment 2523992
> 
> 
> Selecting the AVX2 option does warm up the DIMMs, I imagine they'll get hotter as the test continues... The only thing I wish for with this testing suite is some sort of output informing you of what error occurred during testing
> 
> It could be arbitrary like TM5, it's just nice to try and pin errors to fixes
> 
> View attachment 2523993
> 
> 
> I also love the addition of the 'Skins' feature with this version
> 
> Halfway there!
> 
> View attachment 2523998
> 
> 
> Okay, that's a good sign... I'll have to run TM5 again to see if it's improved and that #2 is eliminated
> 
> View attachment 2524006
> 
> 
> TM5 ran through just fine so far, no #2 so I'll keep drive strengths at 40.0Ω-20.0Ω-24.0Ω-24.0Ω meow
> 
> I'll run Karhu overnight as well and see what comes of that, the only other thing I can think of to do is to reduce tWTRS to 3
> 
> View attachment 2524018
> 
> 
> Anyways, if you did hang in through this and the last post, thanks... I hope this helps someone out and illuminates at least one way to reach 3800CL14 with 1T CR and no setup timings
> 
> View attachment 2524022


Please stop playing the Meow Game right meow. Cat puns freak meowt, seriously, I'm not kitten you.


----------



## mongoled

Have given up on 4066/2033



Back to 4133/2067

 

Just to re-affirm increasing vDDP corrects the misaligned tPHYRDL values between the modules.

So I am going to take a different approach.

I will be setting my vDDP to the value that stops the imbalance.

For running 4133/2067 with flat 16s and 2T and tCKE along with setup timings vDDP at 0.98v leaves all four dimms at tPHYRDL 26.

Next I will be leaving vDDG IOD on AUTO, this is setting 1.15v and I am not going to touch it for the time being, let this CPU be a guinea pig

Hopefully this will be the on the right track to resolve the USB/Audio "sticking" issues .....


----------



## Audioboxer

Went back to the previous MSI bios and VDDG voltages work fine again. Hopefully just an MSI bug and not an issue with AGESA 1.2.0.4.

@Veii Sorry for all the spam yesterday when I was all over the place with my memory. When you've got a minute though can you see if you think this is an A2/B2 PCB? [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread These seem to be similar to what I have. Thanks!


----------



## mongoled

Audioboxer said:


> Went back to the previous MSI bios and VDDG voltages work fine again. Hopefully just an MSI bug and not an issue with AGESA 1.2.0.4.
> 
> @Veii Sorry for all the spam yesterday when I was all over the place with my memory. When you've got a minute though can you see if you think this is an A2/B2 PCB? [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread These seem to be similar to what I have. Thanks!


Are you able to make out the marking on the RAM modules seeing that some are pretty naked ??

The positioning of the modules and the distance from the bottom of the PCB sure looks similar to A2s.

Finding out what the modules are will allow us to determine their rank (just so we know for sure) ...


----------



## Audioboxer

mongoled said:


> Are you able to make out the marking on the RAM modules seeing that some are pretty naked ??
> 
> The positioning of the modules and the distance from the bottom of the PCB sure looks similar to A2s.
> 
> Finding out what the modules are will allow us to determine their rank (just so we know for sure) ...


I compared it to the latest pictures I had taken and they look identical [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread Or at a minimum very similar. The only difference is my ram is 3600C14 and those pics are from 3800C14. It does seem GSKILL use A2 PCB on most of their more expensive kits.

Whilst I've got your attention my IOD autos to 1.15v as well










I presume that is a bit high for the CPU under normal circumstances? I started a stability test anyway lol. Just wanting to test today if I can creep up towards 1.55v without the ICM crashes by playing around with VSOC/IOD/Proc/Rtt/DrvStr. That's my goal for the day, find a way to confirm to myself I will be OK at higher VDIMM voltages!

*edit *- 1.52v seems to be where the very quick crashes on 6 begin


----------



## mongoled

Audioboxer said:


> I presume that is a bit high for the CPU under normal circumstances?


Well we have been told that this is a dangerously high value, that the BIOSs default to this, well .......

Thats why i said my CPU will be a guinea pig!

Just playing with getting vSOC as low as possible before I start some stability testing.


----------



## ManniX-ITA

Audioboxer said:


> I presume that is a bit high for the CPU under normal circumstances?


Yes it's probably too high and will push VSOC near 1.2V.
Mine at FCLK 1900 with IOD 1140mV is slower than 1080mV.
While at FCLK 2000 is the opposite.


----------



## ManniX-ITA

mongoled said:


> Well we have been told that this is a dangerously high value, that the BIOSs default to this, well .......


Dangerously high for VDDP.
Using it since quite a while on 5950x and still lives 
Guess for FCLK 2067 is barely enough!


----------



## mongoled

ManniX-ITA said:


> Dangerously high for VDDP vDDG IOD


----------



## Audioboxer

ManniX-ITA said:


> Yes it's probably too high and will push VSOC near 1.2V.
> Mine at FCLK 1900 with IOD 1140mV is slower than 1080mV.
> While at FCLK 2000 is the opposite.


Ouch, no way I'm going to risk that then even if I am doing 3 cycles right now for experimenting. I have to say its very worrying what these mobos will auto at, between VDDP wanting to shoot as high as 1.09v and now me seeing VDDG will just go to 1.15v 

In related news I took that 1.08v and just slapped it on my VDDG










Admittedly I also AUTO'd the DrvStr again for the moment and dropped Proc to 32. VSOC dropped a little as well. Something has helped stop the IMC crashes on 6 at the start. I can get it every time between 15-30 seconds when using voltage like 1.52~1.55v.

The variable I never really played with much previously was VDDG CCD. Always just left it at 0.975v, or more commonly I dropped it to 0.925~0.95v. I wonder how much of a difference it can play in regards to pushing more VDIMM and IMC stability?

I'll try pushing VDIMM a bit higher now.

*edit* - 1.55 VDIMM has brought the 6 errors back with a vengeance, and I'm struggling to find any combination that gets rid of them.


----------



## Blameless

rossi594 said:


> Shouldn't vddp be derived from vsoc?


Some stuff (namely all the skimpy documentation with every AM4 board I've encountered) says it's derived from vDIMM, but I also see people saying CLDO VDDP is derived from vSoC, like VDDG.

I've never seen anyone actually try to get a physical measurement that could prove things either way, and I've never gone out of my way to check it myself as I've never found more than 1v useful and normally run less than 900mV.



MrHoof said:


> seems to have a extra component on the first picture in the middle area. Am no help tho on identifying them but the pictures should help maybe.


Which component are you referring to exactly?

In the middle area of the PCB I see the SPD EEPROM in the first image and the RGB controller in the second.



Veii said:


> @Blameless was it you with the other ITX/AX ?
> Can you check how many Error Sources are active ? 10 or 9
> I get 9, he get's 10 on the same board, same SPI ROM, same bios profile ~ same typical OS
> The only thing different between us two, was his Revision.02 Intel chip ~ which has a huge reddit post of issues & me with the fixed .03 (maybe) but rather dead NIC
> (Also fails Intel's own Suite Adapter Tests)
> 
> It doesn't look to be the GPU, but LCLK for him is fixed at 5, for me at 1.
> Uses PCie 4.0 full lanes ~ but LCLK DPM doesn't wiggle too.


Yeah, I have an ASRock B550 Phantom Gaming ITX/AX, with a REV_02 i225-v.

Where do you want me to check the number of active error sources?



Audioboxer said:


> The variable I never really played with much previously was VDDG CCD. Always just left it at 0.975v, or more commonly I dropped it to 0.925~0.95v. I wonder how much of a difference it can play in regards to pushing more VDIMM and IMC stability?


Some of my setups are very picky about VDDG CCD, but more with regards to WHEA errors or random reboots during extended testing...not so much with regard to memory directly. However, I also only have one B-die setup which currently has my worst AM4 part in it, so I'm not pushing particularly high memory clocks or tight timings on most of my AM4 setups.


----------



## mongoled

@Audioboxer
Increase vSOC!


----------



## Audioboxer

mongoled said:


> @Audioboxer
> Increase vSOC!


Took a slight detour and a different approach. Since yesterday I've been paranoid my memory can't run at 1.55v. Now, all of you know that is BS, but proving something to yourself is the best way to alleviate an irrational worry. So, inspired by Igors Lab (they were using 1.55v at rated 3800) Does the new high-end RAM for Ryzen 5000 live up to its promise? - G.SKILL DDR4-3800 CL14 2x 16GB kit put through its paces | Page 3 | igor´sLAB I decided lets run at XMP, run your memory at what it is rated for at 1.55v










I CMOS reset my BIOS, left EVERYTHING on auto, even CPU settings, and the only change I made was memory to XMP profile 1 and VDIMM to 1.55v.

As most of you would expect, no issues with 1.55v. No IMC crashes. Yes, it's GDM enabled, but it's still feeding 1.55v.

Thankfully, unlike Igors Lab, I do not have










that on auto  Almost seems criminal to suggest 1.17v in a review. Or at least to me after reading some comments in here that seems very excessive.

Now, the fun does begin when I change to 3800/1900. I obviously want to run that, my IF seems stable at that. I don't care about flat 14's, even if there is a chance. I want to now figure out why I'm getting so much difficulty with the IMC at 3800 and 1.55v. But, importantly, this slight detour has proven to myself 1.55v is fine with this b-die. Sometimes just doing something like this is a small win for your own mind regardless of what other people with far more experience/knowledge have already told you.



Blameless said:


> Some stuff (namely all the skimpy documentation with every AM4 board I've encountered) says it's derived from vDIMM, but I also see people saying CLDO VDDP is derived from vSoC, like VDDG.
> 
> I've never seen anyone actually try to get a physical measurement that could prove things either way, and I've never gone out of my way to check it myself as I've never found more than 1v useful and normally run less than 900mV.
> 
> 
> 
> Which component are you referring to exactly?
> 
> In the middle area of the PCB I see the SPD EEPROM in the first image and the RGB controller in the second.
> 
> 
> 
> Yeah, I have an ASRock B550 Phantom Gaming ITX/AX, with a REV_02 i225-v.
> 
> Where do you want me to check the number of active error sources?
> 
> 
> 
> Some of my setups are very picky about VDDG CCD, but more with regards to WHEA errors or random reboots during extended testing...not so much with regard to memory directly. However, I also only have one B-die setup which currently has my worst AM4 part in it, so I'm not pushing particularly high memory clocks or tight timings on most of my AM4 setups.


We've been trying to identify the PCB in that image as it seems to be the same PCB I am running. Best guess so far seems to be it is indeed A2/B2.

DR kits just seem to have far less exposure online than SR when it comes to identifying PCBs and even testing/overclocking, in general. Understandable I guess seeing as SR kits are the overclocking champions.


----------



## Blameless

Audioboxer said:


> We've been trying to identify the PCB in that image as it seems to be the same PCB I am running. Best guess so far seems to be it is indeed A2/B2.
> 
> DR kits just seem to have far less exposure online than SR when it comes to identifying PCBs and even testing/overclocking, in general. Understandable I guess seeing as SR kits are the overclocking champions.


It does look like a semi-custom B2. The key thing about layout is trace length and component spacing. If it's doubled sided, it should be "B", and the shorter trace length layout is usually a "2" (or rarely three for PCBs that accomodate the larger IC packages).


----------



## ManniX-ITA

Blameless said:


> Some stuff (namely all the skimpy documentation with every AM4 board I've encountered) says it's derived from vDIMM, but I also see people saying CLDO VDDP is derived from vSoC, like VDDG.


I'm not sure who said it, guess it was TheStilth or 1usmus? Maybe @Veii knows.
But I don't think it's derived either from SOC or DIMM voltage, it has its own VDD pins on the AM4.
Guess there's another reason why it should be lower than SOC.


----------



## MrHoof

Blameless said:


> Which component are you referring to exactly?


was talking about this picture from the 1.55v rated kit, same layout but not exactly.



domdtxdissar said:


> Have no other information then gskill saying its a custom 10 layer PCB design and these pictures:
> View attachment 2523825



Btw kit arrived, testing atm with XMP thats were I am so far. PCB looks aswell like the one from igors lab pics and audioboxers.









edti: btw weird thing happening, tCKE auto defaulting to 0 what?


----------



## Blameless

ManniX-ITA said:


> I'm not sure who said it, guess it was TheStilth or 1usmus? Maybe @Veii knows.
> But I don't think it's derived either from SOC or DIMM voltage, it has its own VDD pins on the AM4.
> Guess there's another reason why it should be lower than SOC.


That would be CPU VDDP. CLDO VDDP is a different voltage that has to be derived from something else because of that cLDO which implies a low dropout regulator.


----------



## Audioboxer

Audioboxer said:


> Took a slight detour and a different approach. Since yesterday I've been paranoid my memory can't run at 1.55v. Now, all of you know that is BS, but proving something to yourself is the best way to alleviate an irrational worry. So, inspired by Igors Lab (they were using 1.55v at rated 3800) Does the new high-end RAM for Ryzen 5000 live up to its promise? - G.SKILL DDR4-3800 CL14 2x 16GB kit put through its paces | Page 3 | igor´sLAB I decided lets run at XMP, run your memory at what it is rated for at 1.55v
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I CMOS reset my BIOS, left EVERYTHING on auto, even CPU settings, and the only change I made was memory to XMP profile 1 and VDIMM to 1.55v.
> 
> As most of you would expect, no issues with 1.55v. No IMC crashes. Yes, it's GDM enabled, but it's still feeding 1.55v.
> 
> Thankfully, unlike Igors Lab, I do not have
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> that on auto  Almost seems criminal to suggest 1.17v in a review. Or at least to me after reading some comments in here that seems very excessive.
> 
> Now, the fun does begin when I change to 3800/1900. I obviously want to run that, my IF seems stable at that. I don't care about flat 14's, even if there is a chance. I want to now figure out why I'm getting so much difficulty with the IMC at 3800 and 1.55v. But, importantly, this slight detour has proven to myself 1.55v is fine with this b-die. Sometimes just doing something like this is a small win for your own mind regardless of what other people with far more experience/knowledge have already told you.
> 
> 
> 
> We've been trying to identify the PCB in that image as it seems to be the same PCB I am running. Best guess so far seems to be it is indeed A2/B2.
> 
> DR kits just seem to have far less exposure online than SR when it comes to identifying PCBs and even testing/overclocking, in general. Understandable I guess seeing as SR kits are the overclocking champions.


Interesting little journey for me indeed










Step up to 3800/1900 leaving everything on auto apart from manually setting flat 16 and I changed tCWL to 16 just incase the memory tried to boot it with 14. At this point VDDP decided to stop being sensible at 0.9v and shoot up to 1.1v. So, 3800/1900 must trigger this.










I then decided I'll switch to flat 14. Thankfully no 6 error within 30 seconds, but a double 10 about 2 mins in.










I thought I'll try bumping VSOC a bit as auto might be a bit too low for flat 14 at 3800. Taking VSOC off auto and manually increasing it then decided to change VDDG to 1.15v. This resulted in the 6 crashes coming back.










So then I capped VDDG back to a more reasonable 1.1v which removed the instant 6 crashes but the double 10's came back.










Last thing I tried was increasing the VSOC even more, which resulted in crashing on 6 coming back.

I don't have enough experience with error 10s, my thoughts were just flat 14s are struggling at 3800 and I navigated towards trying to increase VSOC. Increasing VSOC seems to bring its own issues, resulting in crashing on 6 again once it got high enough.

So let alone resistances the relationships between the voltages seems like it's going to be key for me trying to stabilise going up to 1.55v at 3800/1900, especially with GDM disabled.


----------



## ManniX-ITA

Blameless said:


> That would be CPU VDDP. CLDO VDDP is a different voltage that has to be derived from something else because of that cLDO which implies a low dropout regulator.


Can't CLDO VDDP be derived from CPU VDDP?
VDDCR_SOC as well is the rail for cLDO VDDG.


----------



## Blameless

ManniX-ITA said:


> Can't CLDO VDDP be derived from CPU VDDP?


CLDO VDDP doesn't seem to need to be lower than CPU VDDP. I generally set them to the same voltage, as this seems to work best, which shouldn't be the case if CPU VDDP was the base for CLDO VDDP. Some boards I've used also only have one voltage setting, presumably for both...though I supposed that could have a built in offset.



ManniX-ITA said:


> VDDCR_SOC as well is the rail for cLDO VDDG.


This is what the UEFI descriptions of the voltages and all the other available documentation of boards tend to say and it could well apply to CLDO VDDP as well. However, the same descriptions of CLDO VDDP say it's derived from vDIMM, which is also entirely plausible for a voltage in that range related to memory or the memory controller.


----------



## ManniX-ITA

Blameless said:


> CLDO VDDP doesn't seem to need to be lower than CPU VDDP. I generally set them to the same voltage, as this seems to work best, which shouldn't be the case if CPU VDDP was the base for CLDO VDDP. Some boards I've used also only have one voltage setting, presumably for both...though I supposed that could have a built in offset.


Could also be like for MSI that CPU VDDP in the BIOS is the VDDP for the CPUs without cIOD.
Or that AMD is doing the usual background correction when it's set lower than cLDO.
I'm less prone about it being derived by the VDIMM cause I could imagine the IMC behavior would impacted by ProcODT, CAD, RTT settings.


----------



## Audioboxer

MrHoof said:


> was talking about this picture from the 1.55v rated kit, same layout but not exactly.
> 
> 
> 
> 
> Btw kit arrived, testing atm with XMP thats were I am so far. PCB looks aswell like the one from igors lab pics and audioboxers.
> View attachment 2524049
> 
> 
> edti: btw weird thing happening, tCKE auto defaulting to 0 what?


At 3600 with XMP timings I was getting tCKE 0 as well.










Changed away from GDM and a 2T at 1.55v at least doing 3 cycles.










Switching to flat 14 seemed to bring back VDDP going to 1.1v and no such luck with test, error on 13. Which could suggest too much voltage or RttNom issues, likely tied up in instability with tRCDRD being at 14.










So what do you do with a potential too much voltage error? You add more! Interestingly though 1.56v has brought back my best friend, the 6 IMC crash within 30 seconds. Would I be correct to presume there might be another "wall" at 1.55v where if exceeding it the IMC is going to need a whole new set of voltages/resistances to try and balance things?

I might now try a tCL14 at 1.55v but switching tRCDRD to 15.


----------



## Audioboxer

Something unrelated to my voltage adventures is I've just discovered I can boot a 12/10 on tCWL/tRDWR when tCL is 14. When tCL is 15 the lowest I can boot is 12/12.

Just something interesting I found there when trying to piece back together my daily tCL15 profile I was using prior to this bios update wiping everything.


----------



## umea

It's a bit strange because I run into a similar issue as you Audioboxer, hence why sometimes when you post about doing something weird I give it a shot too. I know that my ram can actually handle up to 1.62v or more, but I also run into instant 6s and unfortunately testing the same things as you haven't resulted in anything. It seems my IMC just cannot handle 3800 flat 14s, regardless of voltage. I can run tRCDRD at 15 fine with everything else at 14, hell, I can run 14-8-15-12 3800 fine, though I am unsure if theres any benefit to running uneven timings... I'll mess around with vermeer voltages later on, but I've basically resigned to accepting 3800CL15 flat for now until I can play the silicon lottery with CPUs.


----------



## Audioboxer

umea said:


> It's a bit strange because I run into a similar issue as you Audioboxer, hence why sometimes when you post about doing something weird I give it a shot too. I know that my ram can actually handle up to 1.62v or more, but I also run into instant 6s and unfortunately testing the same things as you haven't resulted in anything. It seems my IMC just cannot handle 3800 flat 14s, regardless of voltage. I can run tRCDRD at 15 fine with everything else at 14, hell, I can run 14-8-15-12 3800 fine, though I am unsure if theres any benefit to running uneven timings... I'll mess around with vermeer voltages later on, but I've basically resigned to accepting 3800CL15 flat for now until I can play the silicon lottery with CPUs.


Yeah I wonder if its CPU more than memory for most of us. Part of me wishes I bought the 3800CL14 ranked kit for a bit more but then again it's 14-16-16-16 ranked and in theory a 3600CL14 14-14-14-14 bin should be pretty much the same as the 3800. Especially once you bump the rated 1.45v up to 1.5v to be in line with the 3800 kit. Ymmv though, bin is guaranteed, thinking you should get something with more voltage is not.

The 5950x seems to be the worst CPU to buy if you want to get into memory overclocking, but obviously you benefit massively in day to day use using such a CPU over getting flat 14s instead of flat 15. Just frustrating when you see some people win the silicon lottery with their 5950x and it doesn't seem to have such a sensitive IMC.

Did you ever manage 1T pure at flat 15? I even struggled with that. Though my side journey down the road of understanding voltage might help me revisit that. I've currently taken the flat 15 profile I was running at 1.5v max and am trying to see if I can now get it stable at 1.55v. Not only might that let me lower tRFC more it could have the ability to let me try 1T pure again. Especially with me now running a more sensible IOD than I ever have before. We'll see.

More posters might pickup these DR 2x16GB kits in the weeks and months to come and maybe we'll all learn a bit more. Heck, AMD/MSI have more to learn with these damn janky bios updates. Imagine letting loose a BIOS update that bugs VDDG voltages to 1.0v max


----------



## Veii

Blameless said:


> Yeah, I have an ASRock B550 Phantom Gaming ITX/AX, with a REV_02 i225-v.
> 
> Where do you want me to check the number of active error sources?











This here 
For him it's 10/10 active v19043.1200 OS
But 19041 is good enough ~ honestly even better than 19043
#42 are for each "active" core 
As my CCD is 8 cores each, i have 8 - the other is blacklisted by AMD
==================================================
Also you might want to check Windows/System32








Take over permissions and wipe them away 
They will load an OTA microcode on the Ryzen and bypass the one that's in the bios
Also are capable to override and patch yours in the bios ~ if AMD decides to do so because of ~reasons~
Mostly Spectre reasons, but it's never known


----------



## K0N574N71N

Hi at all,

I've been reading a lot past 2 hours: Obviously there isn't that one perfect setting for everbody, because every system is different.

So is there like a beginners guide, where everything is explained like the different voltages, mem timings, RTTs, how to test IF, and so on? 

And if not - is somebody willing to write a guide? going through all those 600 pages is quite hard.


greetings


----------



## Audioboxer

K0N574N71N said:


> Hi at all,
> 
> I've been reading a lot past 2 hours: Obviously there isn't that one perfect setting for everbody, because every system is different.
> 
> So is there like a beginners guide, where everything is explained like the different voltages, mem timings, RTTs, how to test IF, and so on?
> 
> And if not - is somebody willing to write a guide? going through all those 600 pages is quite hard.
> 
> 
> greetings


This is a good read to get to grips with a lot of the basics, apps to use and also fundamentals that stay the same across different setups MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper But as you'll see skimming this topic GDM disabled first is one of the main takeaways you'll get from this topic whereas that guide sort of just implies give it a try at the end.

But the memory game is full of pain, mistakes, learning, wasted hours, giving up and then trying again 

That is unless you buy a specific bin of memory and just really go with the defaults. You wouldn't be reading this topic if you were happy doing that though lol.










Plugged most of my prior profile into this










Main changes were sticking with 2T for now (RIP tPHYRDL) and coming away from that stupid 0.925v on VDDGs. Ignore 6/2/6, 7/2/5 was also fine.

3 cycles isn't 25 cycles but previously that old profile would crash on 6/12 within a minute with VDIMM at 1.55v.

I'm warming up to simply staying on 2T and not messing with setups, but tPHYRDL makes zero sense to me. At tCL15 it won't go to 26 unless at some form of 1T, but at tCL14 it is 26 on 2T and then 28 on some form of 1T.

I guess if I stayed at 2T I could explore tCL14, such as 14-15-15-15 to get the little **** back down to 26. Reason for wanting to do this is because its 28/26 or 26/26. It never seems to go 28/28. A mismatch between the two seems to contribute upwards of ~0.5ms to latency.


----------



## MrHoof

This is going well so far. One thing i noticed tPHYRDL will be 28 at 3800 tCL 14 on 1 dimm unless I go to minimum 0.95v CLDO VDDP.

First setings that made it past 2 cycles. Currently still running just started cycle 4 and temps are not going up anymore. Look promising. 1.53v VDIMM







'


----------



## Audioboxer

MrHoof said:


> This is going well so far. One thing i noticed tPHYRDL will be 28 at 3800 tCL 14 on 1 dimm unless I go to minimum 0.95v CLDO VDDP.
> 
> First setings that made it past 2 cycles. Currently still running just started cycle 4 and temps are not going up anymore. Look promising.
> View attachment 2524064
> '


Congrats! If I go near 1T pure my 5950x just seems to explode 

What you said about tPHYRDL was interesting though, I can't ever seem to get it to 26/26 on tCL14 at 1T










Case in point. Ignore TM5 I just ran it for a "laugh". But here are settings similar to yours and my tPHYRDL still insists on being 28 at tCL14 1T on one DIMM. Wondering if this is because of the 5950x IMC...

It would certainly be interesting to hear from more people running a 5950x if they can get 26/26 on 1T with tCL14 and if they can at what point does it revert to 28/26?










Whereas 2T? Not a problem, have 26 fine sir. Even at 0.9v on VDDP 

*Edit* - I went scrounging across this forum and the Internet for ZenTimings screenshots of a 5950x and 1T tCL14. Found what I expected, just about every screenshot at 3800 shows tPHYRDL 28. Only 26 screenshots come from 3600. So from now on when memory things don't work for me it's time to blame the CPU  Though I shouldn't be moaning and instead be grateful I can boot 1900 IF without WHEA. RIP to everyone whose 5950x can't do 1900.

Been a learning curve for me though to find out how much the CPU IMC can impact your memory overclocking. Makes much more sense to me now why Buildzoid and others buy the AMD G chips to push the crazy memory overclocks.










And maybe reality for me at 3800 is just going to come down to 2T tCL14 vs 1T (likely with setups) tCL15 and a lot of benchmarks to see what gets the best results. One thing I am now going to try though is seeing if that tCWL/tRDWR 12/10 that boots when on tCL14 could actually be stable.


----------



## TimeDrapery

I'll have a screenshot of the Tweaker page from my Gigabyte BIOS to post later today, perhaps someone can show and tell what the different voltages available there pertain to

@KedarWolf 

No can do, it be like that meow 😂😂😂😂😂


----------



## mongoled

If anyone cant seem to get LinpackXtreme to behave with the residual check failing after you have been through everything you can think of ive discovered something else that effects it !

tRDRDSCL & tWRWRSCL !

Had them on 4, upped them to 5 and so far so good, will see tomorrow if the behaviour continues.



Otherwise its the two files Veii mentioned earlier as ive changed their names and cant be arsed putting them back

😂 😂


----------



## sonixmon

Audioboxer said:


> Interesting little journey for me indeed
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Step up to 3800/1900 leaving everything on auto apart from manually setting flat 16 and I changed tCWL to 16 just incase the memory tried to boot it with 14. At this point VDDP decided to stop being sensible at 0.9v and shoot up to 1.1v. So, 3800/1900 must trigger this.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I then decided I'll switch to flat 14. Thankfully no 6 error within 30 seconds, but a double 10 about 2 mins in.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I thought I'll try bumping VSOC a bit as auto might be a bit too low for flat 14 at 3800. Taking VSOC off auto and manually increasing it then decided to change VDDG to 1.15v. This resulted in the 6 crashes coming back.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> So then I capped VDDG back to a more reasonable 1.1v which removed the instant 6 crashes but the double 10's came back.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Last thing I tried was increasing the VSOC even more, which resulted in crashing on 6 coming back.
> 
> I don't have enough experience with error 10s, my thoughts were just flat 14s are struggling at 3800 and I navigated towards trying to increase VSOC. Increasing VSOC seems to bring its own issues, resulting in crashing on 6 again once it got high enough.
> 
> So let alone resistances the relationships between the voltages seems like it's going to be key for me trying to stabilise going up to 1.55v at 3800/1900, especially with GDM disabled.


Have you tried to increase PLL? Just a thought but it did help me with my 3800/1900 (I think I am running 1.88 on my CL14 profiles).


----------



## Audioboxer

sonixmon said:


> Have you tried to increase PLL? Just a thought but it did help me with my 3800/1900 (I think I am running 1.88 on my CL14 profiles).


When its at default (1.8v) HWINFO reports it as 1.83v. I've increased it in the BIOS to 1.83v a few times, which reports at like 1.86v IIRC.

I haven't tried pushing it further, I guess I could do just that! See if it even helps with IMC crashing. IIRC Veii said its OK to even try up to 1.9~1.93v, though I dunno if everyone's HWINFO overshoots or if this is yet again the MSI bios at play. For example, VDIMM set in the MSI bios always ends up + 0.01v. So 1.54v in the bios reports at 1.55v on VDIMM.










In other news this 12/10 has potential for a 25 cycle. I have no idea why 12/10 will only boot on tCL14, 12/12 is lowest for tCL15, but I guess it's just another one of these things. I presume 12/8 will be a no POST on tCL14, but I'll give it a go for the sake of it.

*edit* 1.88V reports at 1.906


----------



## sonixmon

Audioboxer said:


> When its at default (1.8v) HWINFO reports it as 1.83v. I've increased it in the BIOS to 1.83v a few times, which reports at like 1.86v IIRC.
> 
> I haven't tried pushing it further, I guess I could do just that! See if it even helps with IMC crashing. IIRC Veii said its OK to even try up to 1.9~1.93v, though I dunno if everyone's HWINFO overshoots or if this is yet again the MSI bios at play. For example, VDIMM set in the MSI bios always ends up + 0.01v. So 1.54v in the bios reports at 1.55v on VDIMM.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> In other news this 12/10 has potential for a 25 cycle. I have no idea why 12/10 will only boot on tCL14, 12/12 is lowest for tCL15, but I guess it's just another one of these things. I presume 12/8 will be a no POST on tCL14, but I'll give it a go for the sake of it.
> 
> *edit* 1.88V reports at 1.906


I tested up to 2.0 with 2000 fclk, but I wouldn't go past that. Every mv seemed to help but not worth it at that point.


----------



## Audioboxer

sonixmon said:


> I tested up to 2.0 with 2000 fclk, but I wouldn't go past that. Every mv seemed to help but not worth it at that point.


Interesting! Can you check for me if your HWINFO reports your BIOS figure or if it overshoots? Thanks.

Trying to figure out if I've been effectively running at 1.83v anyway even when BIOS runs 1.8v lol.


----------



## TimeDrapery

sonixmon said:


> I tested up to 2.0 with 2000 fclk, but I wouldn't go past that. Every mv seemed to help but not worth it at that point.


When you say every mV seemed to help what were you seeing that indicates this?


----------



## sonixmon

Audioboxer said:


> Interesting! Can you check for me if your HWINFO reports your BIOS figure or if it overshoots? Thanks.
> 
> Trying to figure out if I've been effectively running at 1.83v anyway even when BIOS runs 1.8v lol.


My current profile is set to 1.8 manually and is reading 1.808 in HWinfo



TimeDrapery said:


> When you say every mV seemed to help what were you seeing that indicates this?


In the forums someone had posted about the possibility of more PLL voltage helping with IMC/WHEA issues with fclk over 1900. Also mentioned some said removing 4 pin CPU pwr connector helped. I decided to test those theories.
For me PLL definitely helped, I worked my way up to 2.0, as I increased it got better, managed to boot almost WHEA free and PC seemed to run like normal until benchmark then WHEAs came but not constant, more occasional in groups. Before adjusting PLL PC took 2 mins just to get to desktop (felt like I was running old mechanical HD). I was not willing to go past 2.1 and would not run 24/7 even if it worked.

The 4 Pin CPU connector was inconclusive, I did see a difference it seemed but definitely did not resolve and the day I put it back in it ran the same before/after.


----------



## mongoled

Ooooh, played Doom in "arcade" mode for 40 minutes with no crash at 4133/2067 flat 16s, never been able to do that before.

Now onto TM5, if that passes then onto 4 hours of Realbench, followed by a few hours of Y-Cruncher.

I've done successful TM5 at these settings in the past but not on this BIOS so hopefully it wont do anything weird as I want to tweak it further

😁😁


----------



## Audioboxer

sonixmon said:


> My current profile is set to 1.8 manually and is reading 1.808 in HWinfo
> 
> 
> 
> In the forums someone had posted about the possibility of more PLL voltage helping with IMC/WHEA issues with fclk over 1900. Also mentioned some said removing 4 pin CPU pwr connector helped. I decided to test those theories.
> For me PLL definitely helped, I worked my way up to 2.0, as I increased it got better, managed to boot almost WHEA free and PC seemed to run like normal until benchmark then WHEAs came but not constant, more occasional in groups. Before adjusting PLL PC took 2 mins just to get to desktop (felt like I was running old mechanical HD). I was not willing to go past 2.1 and would not run 24/7 even if it worked.
> 
> The 4 Pin CPU connector was inconclusive, I did see a difference it seemed but definitely did not resolve and the day I put it back in it ran the same before/after.


Thanks, so it seems to be an MSI thing multiple voltages overshoot lmao.










Mine at auto/1.8


----------



## TimeDrapery

Audioboxer said:


> Thanks, so it seems to be an MSI thing multiple voltages overshoot lmao.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Mine at auto/1.8


I'm sure lots of boards do this... You know... To "enhance comparability" 😂😂😂😂😂


----------



## mongoled

@TimeDrapery 
Does your asrock overvolt also?


----------



## Veii

Veii said:


> Also you might want to check Windows/System32
> 
> 
> 
> 
> 
> 
> 
> 
> Take over permissions and wipe them away
> They will load an OTA microcode on the Ryzen and bypass the one that's in the bios
> Also are capable to override and patch yours in the bios ~ if AMD decides to do so because of ~reasons~
> Mostly Spectre reasons, but it's never known


I forgot one, just found them @mongoled 
Windows 11 users mostly have mcupadate's in Sys32
But WinSxS , is for 64bit ~ they hide here too:








Downgraded recently, for score submission
My Win10 ProWS didn't have the Sys32 dll's but does have WinSxS one hidden
Wiping and rebooting ~ seems to disable it
Noticed it randomly by browsing Autoruns64 libs and services


ManniX-ITA said:


> I'm not sure who said it, guess it was TheStilth or 1usmus? Maybe @Veii knows.


The Stilt has a long technical check for Matisse
50mV was defined by AMD and was kept up without enforcing UncoreOC mode.
It ignored any VDDG input and did autocorrect/autobalance it down for itself.
Later bioses allowed now for Matisse to split CCD and IOD voltage ~ but i personally still think it does autocorrect

cLDO_VDDP and procODT belong together, well and are also influenced by VDD18
Up to specs and since gen1 ~ VDIMM and cLDO_VDDP where working together. There was a spread fear that high VDIMM can push VDDP and kill the unit.
I do think this was a specs missunderstandment

Usually most is borrowed from SOC , VDDG and VDDP (both)
CPU VDDP has own lines, but i am sure there is one more voltage that is not mentioned
The community here spread it the reverse way (which technically is also correct to some extend)
IOD + offset = SOC (for balancing algorithm)
SOC - offset = minimum VDDG (balanced) is the technical part of it

VDDG CCD ⇄ cLDO_VDDP , is different by design
Matisse and lower was different than Vermeer and upcoming
Vermeer has no issue running CCD = VDDP , but Matisse had to follow AMDs predefined stepping
Holding the voltage stepping made more sense than only following minimum values
The Stilt concluded it being near the 43-44mV as minimum difference, but realistically 48mV
50mV was/is AMDs algorithm. 50 & 75mV stepping we community concluded as being the go to. Mostly me pushing following it, as bios bugs applied nonsense or even by bugs killed couple of samples till variable SOC & variable FCLK got hardlocked/banned and nobody wants to talk about it.

Vermeer i figured 40mV is the absolute lowest
clDO_VDDP min , because now of VDD18 interaction is not perfectly known
More and more we get examples where 860mV works out. 850mV only when everything is perfect
(same for me ~ but memory training is broken on other parts, it's not VDDP that refuses to train higher MCLK)

Because we do not know 100% the maximum safe range of VDD18 & haven't gotten Vermeer = Matisse on procODT behavior = 28ohm (need +1 atm for minimum working)
There is no way to fix VDDP min voltage as ruleset.
Just to keep in mind beyond 1050mV is dangerous
Recent bugs i've seen it be pushed to 1150mV . . .
It appears to survive, but then also same bugs on MSI and ASUS killed Cezanne units instantly ~ pushing 1.3v cLDO_VDDP . . .
Soo i am not sure about current IMC-FW really being "fine" with 1100mV cLDO_VDDP.
I would never go above 1050mV ~ unless the sample can be kept up constantly bellow 60c at any workload.
Even less when behavior changes randomly *
* yes my 2100FCLK is unstable again zZZ #13 and #2 issues. Maybe 1.25v SOC starts degrading (doubt), maybe 1.65vDIMM starts degrading A0's or just silent microcode updates missbehave oor current 3.0 chipset FW and SMU FW update changed something. We'll see. Random gremlins


TimeDrapery said:


> I'm sure lots of boards do this... You know... To "enhance comparability" 😂😂😂😂😂


Never had issues with this, was just normal - soo i didn't bother at first pushing it higher.
Since ASUS started to push it by FCLK ~ we can do too. Unsure if it really is a good idea beyond 1.93v


Audioboxer said:


> @Veii Sorry for all the spam yesterday when I was all over the place with my memory. When you've got a minute though can you see if you think this is an A2/B2 PCB? [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread These seem to be similar to what I have. Thanks!


I saw it, noted and saved.
Waiting for my Dual Rank toys to arrive, to start checking PCBs more closely
Dual rank. . . is different ~ i can not read them
They are not A2's this picture. Could be custom A1 but they are not A1 either
We'll see


----------



## TimeDrapery

The artist


mongoled said:


> @TimeDrapery
> Does your asrock overvolt also?


The ASRock B450M Steel Legend did, the Gigabyte B550M Pro-P and the B550 AORUS MASTER does... I'll bet it's something the vendor "didn't even notice" yet it helps with "compatibility" (I think you can read "compatability" as "outperforms our competition" but I might be crazed 😂😂😂😂😂)

It's never by much but I have a real hard time believing that, with the state of tech these days, they couldn't make it do what it's supposed to do with less "margin"... Again though, there's always the chance I'm wrong!


----------



## mongoled

Veii said:


> 2100FCLK is unstable again zZZ #13 and #2


Was this profile previously tested stable on current BIOS? 

Please post a ZenTimings screenshot of that profile 😁


----------



## mongoled

TimeDrapery said:


> The artist
> 
> 
> The ASRock B450M Steel Legend did, the Gigabyte B550M Pro-P and the B550 AORUS MASTER does... I'll bet it's something the vendor "didn't even notice" yet it helps with "compatibility" (I think you can read "compatability" as "outperforms our competition" but I might be crazed 😂😂😂😂😂)
> 
> It's never by much but I have a real hard time believing that, with the state of tech these days, they couldn't make it do what it's supposed to do with less "margin"... Again though, there's always the chance I'm wrong!


Compatability. Huh

😂😂😍

Well it's down to us to find out what the real voltage is and compare it to what Hwinfo64 reads. 

The X570 Unify does not have any inbuilt measuring points, does you current motherboard? 

😊


----------



## PJVol

sonixmon said:


> Also mentioned some said removing 4 pin CPU pwr connector helped.


Its weird not to mention the third method - your PC case should be located strictly in a south-north direction along the long side.



Veii said:


> we do not know 100% the maximum safe range of VDD18


Don't ask me how do I know, but it's highly likely 2.1V.
CLDO_VDDP 850mv with Cezanne is fine on a daily 3800CL15 setup (and is VDDIO_MEM derived).


----------



## Veii

mongoled said:


> Was this profile previously tested stable on current BIOS?
> 
> Please post a ZenTimings screenshot of that profile 😁


It's the same one i keep testing - and often benchmarking
Haven't updated the bios.
Since i set SETUP timings and it started to fail, after other cold boot attempts ~ it keeps erroring on my old bios profile that was stable

I keep testing TM5 several times, between OS and between other changes
Having my 48.5 as a target ~ while often resulting in 48.9/48.8 if random Microsoft services keep reactivating themself

Keep loading the same bios profiles, which override hidden AMD CBS settings i have no access to
Soo when anything change ~ or one timing is missmatching, it will be instantly seen.
Maybe it's my chipselect bandwidth experiments and memory training fixed something buggy.
Or it's just cores crashing ~ although #13 is "overheating" issues. Maybe powerdown bugged again, not entirely sure








It's this thing i keep playing with
Pushing tRDRD_SCL down , looked beneficial for Read bandwidth. Keeping tWRWR_SCL up to 5 instead of 4, was beneficial for Copy Bandwidth

Tried going lower tRAS, lower tFAW, lower SCL or tRDWR. Nothing wiggles
Even changing CkeDrvStr ~ or RTT = errors or fully no boot.
Idk what i can improve anymore, but surely want to beat these 47.8ns results ~ which aren't even stable (20min stable, CPU 4.95 degrading allcore). Want to beat them as it's showing a bad example for the community of what to "copy".

It's still waiting time for me. Ram's are pretty maxed out. Well beyond maxed out, these A0's
Only a bios unlock or board-swap can allow some potential changes ~ which i wait for atm.
ProArt is sitting and collecting dust. Waiting for Universal Audio to fix Ryzen Audio issues (powermanagement / IO-PCIe does problems with Pci-e DSP's and compute units, but no Matisse unit locally to jumpt to it)
Typical thunderbolt 4 pci-e virtualization and passthrough issues ~ soo proArt is unused yet.

ITX/AX i'll stop recommending now till the #19 is resolved. If Intel Rev.02 is really causing issues (which was known since Intel Z170) or it all along is just Zen LCLK DPM (PCIe) powermanagement towards the chipset.
Or till we can update intel Nic FW and fix it ~ as intel's own adapter diagnostic tools are failing on it somehow
Depends on Blameless's answer how many active error sources he sees

I'll jump back to 1-5-5-1-7-7 on memory , see if i can stabilize it.
Or what exactly the issue is.
Maybe it really is degrading :/ but i doubt tbh
Wanted to wait with it (memory pushing), till my Hydra 09D core-by-core is finished ~ soo annoying PBO package throttle is gone.

EDIT:
Attached ITX/AX bios profile
Has to have no extension ~ to be loaded , soo attachment is .zip 
EDIT2:
I think to remember, bios profiles worked across both X570 and B550 asrock boards without issues. This is is on 1203*C*


----------



## Audioboxer

TimeDrapery said:


> I'm sure lots of boards do this... You know... To "enhance comparability" 😂😂😂😂😂


Pretty careless of them in some cases as all it can take to throw off stability is a few notches too much voltage lol.

I get things can sometimes have a little variation but my CPU voltage is off by 0.03 lol. 1.81 OK, but 1.83 is 

VDIMM I get goes up in 0.01 increments, so 1.5 would become 1.51v, but why even do this with VDIMM? Surely it of all voltages makes sense to be running at what you select in the BIOS! 0.01 on VDIMM can definitely cause some minor instability!

I guess anyone who knows their stuff and is messing with the BIOS will quickly notice, but that's not the point. Strange to me why MSI does this. Didn't happen on my ASUS board.


----------



## TimeDrapery

mongoled said:


> Compatability. Huh
> 
> 😂😂😍
> 
> Well it's down to us to find out what the real voltage is and compare it to what Hwinfo64 reads.
> 
> The X570 Unify does not have any inbuilt measuring points, does you current motherboard?
> 
> 😊


It does, I'll have to review the literature for the board and get the measurements going!


----------



## MrHoof

my board dosnt even have a VDIMM readout in hwinfo or the bios .

Btw the tm5 run earlier lasted until 10th cycle and threw a error in test 7 follow by 15.
Temp is my biggest problem so far in my itx case nr200, got a 120mm fan at the moment pointing at them with a bit of plastic between the dimms to give some breathing room else they touch each other. But only like 1/3 of the fan is actuly not blocked by other stuff, gotta buy something that fits better.


----------



## Audioboxer

I figured out earlier that while tCL14 can boot tCWL/tRDWR 12/10 its not stable and I do not plan to try and see if it can be made stable 

Back to my trusted 12/12










The benefit to getting up to 1.55v is being able to drop tRFC lower, but I'm not sure I'll get through a 25 cycle. My temps are approaching 43 now with active cooling whereas I was around 40 before. You've all seen how awful those RipJaws heatsinks are. With tRFC getting even lower I fully expect it to be even more temp sensitive. 42+ seems to be where low tRFC begins crapping out on b-die.

With RttPark on 5 I don't think there is even any other ways to try and offset DIMM temps. Probably going to be likely 1.55v territory will have to be watercooling or at least changing these awful heatsinks. If this fails I'll see how low tRFC can go at 1.53v. 245 was my previous tRFC at 1.5v, but that was tweaked to like the last drop. Right on the stability threshold for 1.5v.


----------



## TimeDrapery

Alright, time to play with some of these voltages

So for starters I'll maintain 40mV stepping because it's comfy... That means:
• *CLDO VDDP* *--->* _*980mV*_ (which did indeed bump tPHYDRL to the same value on both channels, 26, and reduced memory latency in AIDA64's Cache & Memory Benchmark... With 14 flats and 1T "pure" [still cracks me up to call it "pure" when we're talking picoseconds])
• *VDDG CCD* *--->* *1060mV*
• *VDDG IOD* *--->* *1140mV*
• *VSOC* *--->* *1200mV* (I know, that's a 60mV step... Sorry, OCD 😂😂😂😂😂)

I've also set *PLL* to *2000mV*










Okay, so that's a pretty immediate and easily noticable improvement... I suppose I should run through ProcODTs again real quick like... Same drive strengths and RTTs as depicted above in the ZenTimings...


*ProcODT**28.2Ω**30.0Ω**32.0Ω***34.3Ω**36.9Ω**Initial Run*52.7 ns55.0 ns52.7 ns52.9 ns52.9 ns*1st Run*52.4 ns53.5 ns52.7 ns52.6 ns52.7 ns*2nd Run*52.3 ns53.2 ns52.7 ns52.7 ns54.6 ns*3rd Run*52.7 ns53.2 ns52.4 ns52.4 ns53.1 ns

My interpretation of the results...


*ProcODT**28.2Ω**30.0Ω**32.0Ω***34.3Ω**36.9Ω**Average*52.5 ns53.7 ns52.6 ns*52.7 ns52.8 ns*Range*0.4 ns1.8 ns0.3 ns*0.5 ns0.6 ns

Alright, sticking with 32.0Ω ProcODT then!

No dice with 2000/4000 speeds though... That sucks 😂😂😂😂😂


----------



## Blameless

Veii said:


> This here
> For him it's 10/10 active v19043.1200 OS
> But 19041 is good enough ~ honestly even better than 19043


Kernel-WHEA lists ten active error sources on mine.

I'm on build 19042.1202. Had some issues with 21H1 not liking my fixes for it's DCOM error spam, so I went back to 20H2.



Veii said:


> Also you might want to check Windows/System32
> 
> 
> 
> 
> 
> 
> 
> 
> Take over permissions and wipe them away
> They will load an OTA microcode on the Ryzen and bypass the one that's in the bios
> Also are capable to override and patch yours in the bios ~ if AMD decides to do so because of ~reasons~
> Mostly Spectre reasons, but it's never known


[/QUOTE]

Renamed the mcupdates, but there was no apparent change in anything (performance, error free FCLK, etc). Since the file is older than the microcode in the firmware I don't think it's being applied...AIDA64 was reporting the same microcode either way.



Audioboxer said:


> Thanks, so it seems to be an MSI thing multiple voltages overshoot lmao.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Mine at auto/1.8


Both of my MSI boards (a B550 Gaming Edge Wifi and a B550M PRO-VDH WIFI) also report about 30mV over what's set here...among other oddities. Not sure if it's a reporting/sensor calibration issue, or if it's deliberately overvolting.

Interestingly enough, my ASRock board defaults to 1.83v and has no flat 1.8v option (it's only adjustable in 50mV increments). My current 5800X sample doesn't like more than 1.88v regardless.


----------



## MrHoof

So far i can tell the only combination i found that got me anywhere past 2min tm5 is 7/3/3 43.3procODT 40-20-24-30 this is getting atleast a few cycles in before errors.... I still have 2 weeks to return this kit and go back to SR


----------



## Audioboxer

MrHoof said:


> So far i can tell the only combination i found that got me anywhere past 2min tm5 is 7/3/3 43.3procODT 40-20-24-30 this is getting atleast a few cycles in before errors.... I still have 2 weeks to return this kit and go back to SR
> View attachment 2524104


The pain of dual rank claims another  1T pure is more of a challenge on DR as well.

I bet if you ran AddrCmdSetup of 55 or 56 you'd see a much better TM5 run. You might also need a higher VSOC if you aim to achieve 1T pure.

All of us DR owners are waiting for Veii to get his DR kits if we're part of the wider group who aren't lucky enough to have an IMC and PCB that just handles flat 14 and/or 1T like a pro at 3800.

Though I dare say "limitations" of DR will be limitations for many even with a master working on them. Hence most folks heavy into overclocking sticking to SR. I don't want to give up my 32GB so I won't even be thinking about going to SR 2x8GB. Just working my hardest to squeeze the most performance I can out of my current set.

I eventually got an error with a lower tRFC and 1.55v. I think for all I've fought to get to 1.55v over the past 48 hours it's just not sensible for temps with these crap heatsinks. Edging above 42 degrees to 43+ just brings about random instabilities and while real world use isn't as heavy as TM5 if it doesn't pass TM5 it's a no go, end of. Need that thermal buffer for piece of mind.

And if I can't get tRFC lower than 245 with stability, passing 1.55v with tRFC at 245 is pointless. It can pass at 1.5v!


----------



## MrHoof

Audioboxer said:


> The pain of dual rank claims another  1T pure is more of a challenge on DR as well.
> 
> I bet if you ran AddrCmdSetup of 55 or 56 you'd see a much better TM5 run.


I am not giving up so fast  but thats an option.

edit : atm Aida SR left vs DR right (not 100% stable) done until weekend, took a day off today but was worth it


----------



## Audioboxer

MrHoof said:


> I am not giving up so fast  but thats an option.


Try bringing your ProcODT down as well. My kit defaults at 36.9 and as I start to use DrvStr other than 20 it seems to like 34.3 or even lower.

Someone can correct me if wrong but I think last gen Ryzens liked 40+.

*Edit* - That's a nice latency benchmark for DR. Tighten up those timings and you'll be at 51.x I would think! Lowest I've seen is










But I'm sure I read somewhere that a 5950x will have a latency overhead, so being at 54ns with that makes me feel a bit better lol.

Bench in Windows safe mode if you want to bench without background jank. It should give you a figure nearer your real starting base. You'd be surprised at additional latency that can be added from apps. Looking at you Nvidia


----------



## Veii

Blameless said:


> Renamed the mcupdates, but there was no apparent change in anything (performance, error free FCLK, etc). Since the file is older than the microcode in the firmware I don't think it's being applied...AIDA64 was reporting the same microcode either way.


The signing keys are old. There are zero-day exploit .dll's from year 1901 in the current windows 
I wouldn't trust it - especially since intel announced OTA microcode updates "just recently"

Both WinSxS and Sys32

Soo 10 out of 10 error sources right ?
I got 9 / 10


----------



## TimeDrapery

I've got to stick the old USB drive in the compooter in order to screenshot my BIOS so that'll be a sec...

I've got PLL set to 2.0V from 1.8V (on Auto) and then CPU VDDP is set to 980mV (from 900mV on Auto + 80.0 mV positive offset)

It seems to have improved stability and, like I'd said earlier, tPHYDRL is showing 26 on both channels but it doesn't look like it helps whatsoever with WHEA above 1900/3800 speeds


----------



## MrHoof

Audioboxer said:


> Try bringing your ProcODT down as well. My kit defaults at 36.9 and as I start to use DrvStr other than 20 it seems to like 34.3 or even lower.
> 
> Someone can correct me if wrong but I think last gen Ryzens liked 40+.


I tried that ofc, but any lower then 40 results in error in test 6 and 40 fails in test 12 everytime. I used to run 28.2 on SR. My board is stupid af and defaults to 60ohm procODT on any kit with 24-24-24-24. Basicly all I did was testing diffrent procODT RTT cad bus setting all day with the settings that got past 10cycles.


----------



## sonixmon

It will be interesting to see some results in SR vs DR. Most reviewers were recommending DR for better FPS with Zen3. This of course would depend on the overclocks on each.

From what at least one person posted the difference of AddrCmdSetup of 55 or 56 vs true 1T was not that much difference in testing and probably not noticeable in use (other than that placebo affect).


----------



## Audioboxer

MrHoof said:


> I tried that ofc, but any lower then 40 results in error in test 6 and 40 fails in test 12 everytime. I used to run 28.2 on SR. My board is stupid af and defaults to 60ohm procODT on any kit with 24-24-24-24. Basicly all I did was testing diffrent procODT RTT cad bus setting all day with the settings that got past 10cycles.


If I see another error 6 I'm throwing my PC out of a window!

I'm guessing you tried the often seen 40/20/30/20? For some reason my ram quite likes a 7/2/5 on the Rtts. A 7/3/3 seems to be OK as well. But I'm mostly playing around with 2T or 1T with setups. I gave up on 1T pure quite quickly after struggling to find anything that would pass even 1~2 cycles.

Meaning you could well be right a higher ProcODT might help with 1T pure stability.


----------



## sonixmon

Audioboxer said:


> If I see another error 6 I'm throwing my PC out of a window!
> 
> I'm guessing you tried the often seen 40/20/30/20? For some reason my ram quite likes a 7/2/5 on the Rtts. A 7/3/3 seems to be OK as well. But I'm mostly playing around with 2T or 1T with setups. I gave up on 1T pure quite quickly after struggling to find anything that would pass even 1~2 cycles.
> 
> Meaning you could well be right a higher ProcODT might help with 1T pure stability.


I gave up on 1T Pure when I got my new kit and it refuses to post anything 1T Pure! 🤣 Only change in the system was the ram, my old kit was running 3800CL16 1T Pure. I am pretty sure it was DR but I heard they did several revisions of that ram. Sold it to partially fund the new kit and cant find old Zen Timing screenshot (yet) but I believe I confirmed that when I had them early on.


----------



## MrHoof

Audioboxer said:


> If I see another error 6 I'm throwing my PC out of a window!
> 
> I'm guessing you tried the often seen 40/20/30/20? For some reason my ram quite likes a 7/2/5 on the Rtts. A 7/3/3 seems to be OK as well. But I'm mostly playing around with 2T or 1T with setups. I gave up on 1T pure quite quickly after struggling to find anything that would pass even 1~2 cycles.
> 
> Meaning you could well be right a higher ProcODT might help with 1T pure stability.


yes but even on my single rank kits i used to run 20/20/20/24 my board/cpu realy does not like CkeDrvStr at 20 it wont cause errors but aida will be less stable overall. On SR i had read/write/latency
57.7GB and 53.5gb copy ~52ns as avg but 20/20/20/20 benched often below that.

edit: also I did not see a single bluescreen today only errors in tm5.


----------



## Audioboxer

sonixmon said:


> I gave up on 1T Pure when I got my new kit and it refuses to post anything 1T Pure! 🤣 Only change in the system was the ram, my old kit was running 3800CL16 1T Pure. I am pretty sure it was DR but I heard they did several revisions of that ram. Sold it to partially fund the new kit and cant find old Zen Timing screenshot (yet) but I believe I confirmed that when I had them early on.


This kit teases me as it will literally post just about anything, but then the fun begins in TM5. In regards to 1T pure it will even post with default settings, like disabled/3/1 and 20/20/20/20 at 3800/1900. Although that is mega unstable (not setting up Rtts/DrvStr), the one thing I've found that managed to get my PC to BSOD/reboot within seconds of TM5.

With the funny side effect it wipes my steam login details and erases all my ICUE fan profiles  I guess this is how you destroy a Windows installation!

But sadly even when the Rtts and DrvStr come into play I never managed to find something that would run 1T Pure. An error normally within a minute or so. Surprisingly on Zen 3 the difference between 1T Pure and 1T with setups doesn't appear to be much!

I'm going to be testing tCL14 at 2T vs tCL15 at 1T (with setup) soon because both of them manage to keep my tPHYRDL at 26. 53.8ns is my best result so far with tCL15 1T (with setup). I would be interested to hear from anyone else with DR and a 5950x what the lowest they've been able to achieve is? At 3800 of course.


----------



## TimeDrapery

Veii said:


> I forgot one, just found them @mongoled
> Windows 11 users mostly have mcupadate's in Sys32
> But WinSxS , is for 64bit ~ they hide here too:
> View attachment 2524071
> 
> Downgraded recently, for score submission
> My Win10 ProWS didn't have the Sys32 dll's but does have WinSxS one hidden
> Wiping and rebooting ~ seems to disable it
> Noticed it randomly by browsing Autoruns64 libs and services
> 
> The Stilt has a long technical check for Matisse
> 50mV was defined by AMD and was kept up without enforcing UncoreOC mode.
> It ignored any VDDG input and did autocorrect/autobalance it down for itself.
> Later bioses allowed now for Matisse to split CCD and IOD voltage ~ but i personally still think it does autocorrect
> 
> cLDO_VDDP and procODT belong together, well and are also influenced by VDD18
> Up to specs and since gen1 ~ VDIMM and cLDO_VDDP where working together. There was a spread fear that high VDIMM can push VDDP and kill the unit.
> I do think this was a specs missunderstandment
> 
> Usually most is borrowed from SOC , VDDG and VDDP (both)
> CPU VDDP has own lines, but i am sure there is one more voltage that is not mentioned
> The community here spread it the reverse way (which technically is also correct to some extend)
> IOD + offset = SOC (for balancing algorithm)
> SOC - offset = minimum VDDG (balanced) is the technical part of it
> 
> VDDG CCD ⇄ cLDO_VDDP , is different by design
> Matisse and lower was different than Vermeer and upcoming
> Vermeer has no issue running CCD = VDDP , but Matisse had to follow AMDs predefined stepping
> Holding the voltage stepping made more sense than only following minimum values
> The Stilt concluded it being near the 43-44mV as minimum difference, but realistically 48mV
> 50mV was/is AMDs algorithm. 50 & 75mV stepping we community concluded as being the go to. Mostly me pushing following it, as bios bugs applied nonsense or even by bugs killed couple of samples till variable SOC & variable FCLK got hardlocked/banned and nobody wants to talk about it.
> 
> Vermeer i figured 40mV is the absolute lowest
> clDO_VDDP min , because now of VDD18 interaction is not perfectly known
> More and more we get examples where 860mV works out. 850mV only when everything is perfect
> (same for me ~ but memory training is broken on other parts, it's not VDDP that refuses to train higher MCLK)
> 
> Because we do not know 100% the maximum safe range of VDD18 & haven't gotten Vermeer = Matisse on procODT behavior = 28ohm (need +1 atm for minimum working)
> There is no way to fix VDDP min voltage as ruleset.
> Just to keep in mind beyond 1050mV is dangerous
> Recent bugs i've seen it be pushed to 1150mV . . .
> It appears to survive, but then also same bugs on MSI and ASUS killed Cezanne units instantly ~ pushing 1.3v cLDO_VDDP . . .
> Soo i am not sure about current IMC-FW really being "fine" with 1100mV cLDO_VDDP.
> I would never go above 1050mV ~ unless the sample can be kept up constantly bellow 60c at any workload.
> Even less when behavior changes randomly *
> * yes my 2100FCLK is unstable again zZZ #13 and #2 issues. Maybe 1.25v SOC starts degrading (doubt), maybe 1.65vDIMM starts degrading A0's or just silent microcode updates missbehave oor current 3.0 chipset FW and SMU FW update changed something. We'll see. Random gremlins
> 
> Never had issues with this, was just normal - soo i didn't bother at first pushing it higher.
> Since ASUS started to push it by FCLK ~ we can do too. Unsure if it really is a good idea beyond 1.93v
> 
> I saw it, noted and saved.
> Waiting for my Dual Rank toys to arrive, to start checking PCBs more closely
> Dual rank. . . is different ~ i can not read them
> They are not A2's this picture. Could be custom A1 but they are not A1 either
> We'll see


Yeah I've never encountered issues due to this either, just something I noticed along the way...

What's ASUS pushing by FCLK? VDDP? PLL? From my understanding PLL helps components stay sync'd up so pushing it higher likely helps whatever PCI stuff is bungling up the mix, yeah?


----------



## TimeDrapery

Audioboxer said:


> This kit teases me as it will literally post just about anything, but then the fun begins in TM5. In regards to 1T pure it will even post with default settings, like disabled/3/1 and 20/20/20/20 at 3800/1900. Although that is mega unstable (not setting up Rtts/DrvStr), the one thing I've found that managed to get my PC to BSOD/reboot within seconds of TM5.
> 
> With the funny side effect it wipes my steam login details and erases all my ICUE fan profiles  I guess this is how you destroy a Windows installation!
> 
> But sadly even when the Rtts and DrvStr come into play I never managed to find something that would run 1T Pure. An error normally within a minute or so. Surprisingly on Zen 3 the difference between 1T Pure and 1T with setups doesn't appear to be much!
> 
> I'm going to be testing tCL14 at 2T vs tCL15 at 1T (with setup) soon because both of them manage to keep my tPHYRDL at 26. 53.8ns is my best result so far with tCL15 1T (with setup). I would be interested to hear from anyone else with DR and a 5950x what the lowest they've been able to achieve is? At 3800 of course.


I don't remember it being a severe difference on Matisse either... I'd consider them "minute adjustments to signaling" more than a "timing" like we consider tCL, tRP, etc.


----------



## Veii

TimeDrapery said:


> Yeah I've never encountered issues due to this either, just something I noticed along the way...
> 
> What's ASUS pushing by FCLK? VDDP? PLL? From my understanding PLL helps components stay sync'd up so pushing it higher likely helps whatever PCI stuff is bungling up the mix, yeah?


VDD1.8
Same thing, just a different name
They started to push it - while before it was just "design choice" or rather "bug" ~ by ASRock


----------



## Audioboxer

TimeDrapery said:


> I don't remember it being a severe difference on Matisse either... I'd consider them "minute adjustments to signaling" more than a "timing" like we consider tCL, tRP, etc.


My "I have no clue what I'm talking about" understanding is at 55/56 or anything really over the 'halfway point' it begins to behave more like the command rate. So it's sort of 1.5T or something, rather than 1T pure. In theory it should perform a bit better than 2T but maybe not quite as good as 1T pure.

I'll just call it the better looking brother/sister of GDM enabled 1T


----------



## sonixmon

Audioboxer said:


> This kit teases me as it will literally post just about anything, but then the fun begins in TM5. In regards to 1T pure it will even post with default settings, like disabled/3/1 and 20/20/20/20 at 3800/1900. Although that is mega unstable (not setting up Rtts/DrvStr), the one thing I've found that managed to get my PC to BSOD/reboot within seconds of TM5.
> 
> With the funny side effect it wipes my steam login details and erases all my ICUE fan profiles  I guess this is how you destroy a Windows installation!
> 
> But sadly even when the Rtts and DrvStr come into play I never managed to find something that would run 1T Pure. An error normally within a minute or so. Surprisingly on Zen 3 the difference between 1T Pure and 1T with setups doesn't appear to be much!
> 
> I'm going to be testing tCL14 at 2T vs tCL15 at 1T (with setup) soon because both of them manage to keep my tPHYRDL at 26. 53.8ns is my best result so far with tCL15 1T (with setup). I would be interested to hear from anyone else with DR and a 5950x what the lowest they've been able to achieve is? At 3800 of course.


Keep us posted on the benchmarks, definitely interested in your results! 



TimeDrapery said:


> Yeah I've never encountered issues due to this either, just something I noticed along the way...
> 
> What's ASUS pushing by FCLK? VDDP? PLL? From my understanding PLL helps components stay sync'd up so pushing it higher likely helps whatever PCI stuff is bungling up the mix, yeah?


1.8v stock, though my Auto was 1.7x

It would make sense as I have hear B550 is much better for overclocking (especially ram) so maybe it is related. I went x570 for me PCIe4.0 lanes (though it is really overkill as I only currently have 1 PCI4.0 nvme drive). Hindsight I would have gone B500 saved a few $ and possibly had better OC capability.


----------



## TimeDrapery

Audioboxer said:


> My "I have no clue what I'm talking about" understanding is at 55/56 or anything really over the 'halfway point' it begins to behave more like the command rate. So it's sort of 1.5T or something, rather than 1T pure. In theory it should perform a bit better than 2T but maybe not quite as good as 1T pure.
> 
> I'll just call it the better looking brother/sister of GDM enabled 1T


Ah I gotcha! I know this will not make everything clear (unless mud is the standard 😂😂😂😂😂) but it might help


----------



## Audioboxer

TimeDrapery said:


> Ah I gotcha! I know this will not make everything clear (unless mud is the standard 😂😂😂😂😂) but it might help
> 
> View attachment 2524117


Nope, I have no idea what any of that means 

My totally non-scientific guesstimate _answer_ above is just pieced together from bits and pieces from other posters I trust and gluing it together with "Well, it's not 1T pure and it's not 2T, so lets call it 1.5T" 

Why it runs stable for some of us, especially on DR, but 1T pure throws a rage fit with the same timings and drops 3000 errors within 20 seconds I have no idea. But if it works, it works!

When I run tCL15 its literally the only way I can get tPHYRDL 26 at 3800. For whatever reason I guess I'll never know, 2T thinks it should "train" at 28/26 whereas my 1.5T decides 26/26 is the right way.

Ryzen (5950x IMC), AMD bios and memory, I guess. Welcome to the party of insanity.


----------



## TimeDrapery

Audioboxer said:


> Nope, I have no idea what any of that means
> 
> My totally non-scientific guesstimate _answer_ above is just pieced together from bits and pieces from other posters I trust and gluing it together with "Well, it's not 1T pure and it's not 2T, so lets call it 1.5T"
> 
> Why it runs stable for some of us, especially on DR, but 1T pure throws a rage fit with the same timings and drops 3000 errors within 20 seconds I have no idea. But if it works, it works!


Right, if it works then it works ... I dig

I'd think, were you interested to actually know, it shouldn't be too hard to convert one clock cycle to nanoseconds, convert that to picoseconds, and then compare with that chart to see when and if the setup timings actually behave similarly to a command rate change between 1T/2T... Perhaps the scale of things is off within my mind but I still fail to grasp the comparison between these setup timings and a command rate change as, were it the case that setup timings past a certain point behave similarly to a change in command rate, many other parameters would be impacted and neither 1T nor 2T command rates should function appropriately considering that cycles stack

It is what it is, I'm pretty positive they exist to accommodate different designs of CPUs, memory, and motherboards though so dismissing them from a "purity" standpoint as "lesser performing" is certain to leave you short a few tools that otherwise would be hanging from your belt

As the ultimate in subjective experience... With Matisse I topped a few sheets using setup timings whilst others stayed where they were at because they didn't know how to work with them and/or what to expect from their inclusion











But, y'know...

Hella










😂😂😂😂😂


----------



## Veii

Audioboxer said:


> Blameless said:
> 
> 
> 
> Kernel-WHEA lists ten active error sources on mine.
> 
> I'm on build 19042.1202. Had some issues with 21H1 not liking my fixes for it's DCOM error spam, so I went back to 20H2.
> 
> 
> 
> Both of my MSI boards (a B550 Gaming Edge Wifi and a B550M PRO-VDH WIFI) also report about 30mV over what's set here...among other oddities. Not sure if it's a reporting/sensor calibration issue, or if it's deliberately overvolting.
> 
> Interestingly enough, my ASRock board defaults to 1.83v and has no flat 1.8v option (it's only adjustable in 50mV increments). My current 5800X sample doesn't like more than 1.88v regardless.
Click to expand...

Same








1.93 set 
Never figured out that Vcore sensor
Bottom is VSOC, top is Vcore VR VOUT


----------



## Audioboxer

TimeDrapery said:


> Right, if it works then it works ... I dig
> 
> I'd think, were you interested to actually know, it shouldn't be too hard to convert one clock cycle to nanoseconds, convert that to picoseconds, and then compare with that chart to see when and if the setup timings actually behave similarly to a command rate change between 1T/2T... Perhaps the scale of things is off within my mind but I still fail to grasp the comparison between these setup timings and a command rate change as, were it the case that setup timings past a certain point behave similarly to a change in command rate, many other parameters would be impacted and neither 1T nor 2T command rates should function appropriately considering that cycles stack
> 
> It is what it is, I'm pretty positive they exist to accommodate different designs of CPUs, memory, and motherboards though so dismissing them from a "purity" standpoint as "lesser performing" is certain to leave you short a few tools that otherwise would be hanging from your belt
> 
> As the ultimate in subjective experience... With Matisse I topped a few sheets using setup timings whilst others stayed where they were at because they didn't know how to work with them and/or what to expect from their inclusion
> 
> 
> View attachment 2524118
> 
> 
> But, y'know...
> 
> Hella
> 
> View attachment 2524119
> 
> 
> 😂😂😂😂😂


I probably should spend a bit more time putting the effort in to learn, that way I might even find out values other than 55/56 work out. Might play around more with the numbers at some point!


----------



## TimeDrapery

Alrighty gentlemen and gentlewomen...

My lazy ass got up and inserted the USB drive so... What do you know about the highlighted voltage options?

Most especially those called, "MR6VrefDQ Control" and "CPU Vref Training Seed Control"? Considering they're found under "AMD CBS" I presume they take input in hexadecimal... What good are they?

Also, "A_VDD18S5"...? S5 makes me sleepy... Same voltage for the two options though?

Since the forum is being bunk about my images look at the links underneath here...



Spoiler












210907160028


Image 210907160028 in Gigabyte B550 AORUS MASTER BIOS Screenshots album




ibb.co












210907160055


Image 210907160055 hosted in ImgBB




ibb.co












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Image 210907160106 hosted in ImgBB




ibb.co












210907160116


Image 210907160116 hosted in ImgBB




ibb.co












210907160120


Image 210907160120 hosted in ImgBB




ibb.co












210907160158


Image 210907160158 hosted in ImgBB




ibb.co












210907160238


Image 210907160238 hosted in ImgBB




ibb.co












210907160322


Image 210907160322 hosted in ImgBB




ibb.co












210907160307


Image 210907160307 hosted in ImgBB




ibb.co












210907160344


Image 210907160344 hosted in ImgBB




ibb.co


----------



## gled_fr

@Audioboxer

I just did a quick test tcwl 12 trdwr 12 ( which results in tphywrl 7 ) vs tcwl 14 trdwr 8 ( which results in tphywrl 9 ).

It seems like 14/8 gives around 400-500MB/s more copy speed and .3-.4ns less latency, all other being identical.

from my limited testing, 14/8 is better, even with higher tphywrl.


----------



## Audioboxer

gled_fr said:


> @Audioboxer
> 
> I just did a quick test tcwl 12 trdwr 12 ( which results in tphywrl 7 ) vs tcwl 14 trdwr 8 ( which results in tphywrl 9 ).
> 
> It seems like 14/8 gives around 400-500MB/s more copy speed and .3-.4ns less latency, all other being identical.
> 
> from my limited testing, 14/8 is better, even with higher tphywrl.


For whatever reason I can't run 14/8 on tCL15, needs to be 14/9. 14/8 will need tCL14 just as 12/10 (this isn't stable) does. I'm not sure why the tighter timings need the tighter tCL lol.

I'll do some testing of my own across my tCL 14 and 15 profiles with those variances. Veii did say to me a while back dropping the tCWL isn't a priority and your testing shows why.


----------



## sonixmon

TimeDrapery said:


> Ah I gotcha! I know this will not make everything clear (unless mud is the standard 😂😂😂😂😂) but it might help
> 
> View attachment 2524117


Hmmm is that 1.75T 😂

For whatever reason I only need to sett AddrCmdSetup 55-56 the rest seem ok at 0.


----------



## TimeDrapery

sonixmon said:


> Hmmm is that 1.75T 😂
> 
> For whatever reason I only need to sett AddrCmdSetup 55-56 the rest seem ok at 0.


😂😂😂😂😂, I think so... Or 1.78125T if we're being exact

On Vermeer this seems to be the case for me as well, just the first bub... On Matisse, for me, it hated that and quickly organized a strike amongst its comrades


----------



## TimeDrapery

Ack! Dubs!


----------



## Audioboxer

sonixmon said:


> Hmmm is that 1.75T 😂
> 
> For whatever reason I only need to sett AddrCmdSetup 55-56 the rest seem ok at 0.


Ah, I get how to read it now. So not "1.5T" but "1.75T" 

So.... try 48 for 1.5T!!!


----------



## TimeDrapery

Audioboxer said:


> Ah, I get how to read it now. So not "1.5T" but "1.75T"
> 
> So.... try 48 for 1.5T!!!


Yes! Yes! Now you are getting it!!! 😂😂😂😂😂

It's all 1.75T when you really get down to it... A sort of dualist monism to be honest


----------



## gled_fr

gled_fr said:


> Curious about the bench diff between 14/9 and 12/12.
> I do boot 14/8 here. 12/8 no way. Might give a try to 12/12 after the current stability test.
> 
> Still working on 1.2.03 patch C bios changes ( from 1.2.0.3 patch A ):
> 
> same settings as before, latency goes to 54.8 instead of 54.6ns ( [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread )
> harmonizing trtp to 5 because twr is 10, and setting trfc to 260 from 258 (obviously trfc2 and 4 set accordingly too) because trfc needs to be divided as integer with trtp gets 54.7ns. TRFC 255 gets a single error 10 and a single 3 on the long 60cycles test, far into the test.
> still testing stability and need to work on that further, but upping vdimm to 1.5 from 1.46 and setting trfc to 245 ( and again trfc2/4 accordingly ) from point above seems to get back the 54.6ns latency [EDIT: stability testing at 1.495 vdimm now, 1.5 vdimm did one error 4, and I want to avoid as much as possible having to find a new procodt/rtt/drvstr balance]
> 
> Stupid that going from patch A to patch C, same settings I lost 0.2ns and that I have to up vdimm to regain that. At least I have trtp and twr going together, which I missed previously.


So, instead of all that, it seems like upping IOD a tiny bit ( 1.005 instead of 1.0 ) allowed to get back to 54.6ns latency at 1.46vdimm.

No need to go all the way to 1.5vdimm and all the issues that went with stabilizing that.

tRFC 260 happy...


----------



## gled_fr

gled_fr said:


> So, instead of all that, it seems like upping IOD a tiny bit ( 1.005 instead of 1.0 ) allowed to get back to 54.6ns latency at 1.46vdimm.
> 
> No need to go all the way to 1.5vdimm and all the issues that went with stabilizing that.
> 
> tRFC 260 happy...


So confirmed, all it took to get back 54.6ns latency on 1.2.0.3 patch C was to up vddg_iod from 1.0V to 1.005V...


----------



## mongoled

🤣🤣

Not quite there









One error 1 on TM5

😂😂

And Y-Cruncher crapped out pretty early.

High FCLK has knocked out of whack my CO values, going to need to restest those to see if I can get something that is more stable.

Been on this wild goose chase before, hope this time I can nail down the instability that high FCLK is causing in CO ....


----------



## mongoled

Veii said:


> It's the same one i keep testing - and often benchmarking
> Haven't updated the bios.
> Since i set SETUP timings and it started to fail, after other cold boot attempts ~ it keeps erroring on my old bios profile that was stable
> 
> I keep testing TM5 several times, between OS and between other changes
> Having my 48.5 as a target ~ while often resulting in 48.9/48.8 if random Microsoft services keep reactivating themself
> 
> Keep loading the same bios profiles, which override hidden AMD CBS settings i have no access to
> Soo when anything change ~ or one timing is missmatching, it will be instantly seen.
> Maybe it's my chipselect bandwidth experiments and memory training fixed something buggy.
> Or it's just cores crashing ~ although #13 is "overheating" issues. Maybe powerdown bugged again, not entirely sure
> View attachment 2524080
> 
> It's this thing i keep playing with
> Pushing tRDRD_SCL down , looked beneficial for Read bandwidth. Keeping tWRWR_SCL up to 5 instead of 4, was beneficial for Copy Bandwidth
> 
> Tried going lower tRAS, lower tFAW, lower SCL or tRDWR. Nothing wiggles
> Even changing CkeDrvStr ~ or RTT = errors or fully no boot.
> Idk what i can improve anymore, but surely want to beat these 47.8ns results ~ which aren't even stable (20min stable, CPU 4.95 degrading allcore). Want to beat them as it's showing a bad example for the community of what to "copy".
> 
> It's still waiting time for me. Ram's are pretty maxed out. Well beyond maxed out, these A0's
> Only a bios unlock or board-swap can allow some potential changes ~ which i wait for atm.
> ProArt is sitting and collecting dust. Waiting for Universal Audio to fix Ryzen Audio issues (powermanagement / IO-PCIe does problems with Pci-e DSP's and compute units, but no Matisse unit locally to jumpt to it)
> Typical thunderbolt 4 pci-e virtualization and passthrough issues ~ soo proArt is unused yet.
> 
> ITX/AX i'll stop recommending now till the #19 is resolved. If Intel Rev.02 is really causing issues (which was known since Intel Z170) or it all along is just Zen LCLK DPM (PCIe) powermanagement towards the chipset.
> Or till we can update intel Nic FW and fix it ~ as intel's own adapter diagnostic tools are failing on it somehow
> Depends on Blameless's answer how many active error sources he sees
> 
> I'll jump back to 1-5-5-1-7-7 on memory , see if i can stabilize it.
> Or what exactly the issue is.
> Maybe it really is degrading :/ but i doubt tbh
> Wanted to wait with it (memory pushing), till my Hydra 09D core-by-core is finished ~ soo annoying PBO package throttle is gone.
> 
> EDIT:
> Attached ITX/AX bios profile
> Has to have no extension ~ to be loaded , soo attachment is .zip
> EDIT2:
> I think to remember, bios profiles worked across both X570 and B550 asrock boards without issues. This is is on 1203*C*


Thanks, I think its because when everything is on a knifes edge its impossible for it to always be stable.

A difference in the electrical noise (day to day variation) may effect stability testing when there is hardly any leeway,

well this is what I tell myself

😂😂

Will have a play with your settings on my 32GB setup




TimeDrapery said:


> It does, I'll have to review the literature for the board and get the measurements going!


Dude, where are those measurements

😂 😂



MrHoof said:


> my board dosnt even have a VDIMM readout in hwinfo or the bios .


Ahhh, thats not very good ...



Audioboxer said:


> When I run tCL15 its literally the only way I can get tPHYRDL 26 at 3800. For whatever reason I guess I'll never know, 2T thinks it should "train" at 28/26 whereas my 1.5T decides 26/26 is the right way.


Its been repeated several times, have you tried to push vDDP when you see this ???


----------



## Audioboxer

mongoled said:


> Thanks, I think its because when everything is on a knifes edge its impossible for it to always be stable.
> 
> A difference in the electrical noise (day to day variation) may effect stability testing when there is hardly any leeway,
> 
> well this is what I tell myself
> 
> 😂😂
> 
> Will have a play with your settings on my 32GB setup
> 
> 
> 
> Dude, where are those measurements
> 
> 😂 😂
> 
> 
> Ahhh, thats not very good ...
> 
> 
> Its been repeated several times, have you tried to push vDDP when you see this ???


Yes, of course, vDDP makes no difference. Though haven't pushed it any higher than the 1.09v the mobo will sometimes even default to. I think it's a 5950x thing. A page or so ago I posted my "findings" from scouring the web, most ZenTimings screenshots with a 5950x have the 28/26 issue at tCL14 1T. My additional findings have just been the weird 1T/2T situations for 14/15.

I tried 48 AddrCmdSetup for a laugh and while it posts it crashes loading into Windows.


----------



## mongoled

Audioboxer said:


> Yes, of course, vDDP makes no difference. Though haven't pushed it any higher than the 1.09v the mobo will sometimes even default to. I think it's a 5950x thing. A page or so ago I posted my "findings" from scouring the web, most ZenTimings screenshots with a 5950x have the 28/26 issue at tCL14 1T. My additional findings have just been the weird 1T/2T situations for 14/15.
> 
> I tried 48 AddrCmdSetup for a laugh and while it posts it crashes loading into Windows.


So I dropped IOD to 1.12v and guess what,

my dimms moved to 28/26 ...

So you may have others things to test



Just testing with Y-Cruncher at 28/26 to see if it stops failing ..


----------



## Audioboxer

mongoled said:


> So I dropped IOD to 1.12v and guess what,
> 
> my dimms moved to 28/26 ...
> 
> So you may have others things to test
> 
> 
> 
> Just testing with Y-Cruncher at 28/26 to see if it stops failing ..


Dropped IOD meaning it was even higher? What sort of voltage were we talking? lol










What would be strange for me though is why this is 26/26 but switching to 2T goes 28/26. One would think 2T would be "easier" for the RAM to train at 26/26.


----------



## mongoled

Audioboxer said:


> Dropped IOD meaning it was even higher? What sort of voltage were we talking? lol
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> What would be strange for me though is why this is 26/26 but switching to 2T goes 28/26. One would think 2T would be "easier" for the RAM to train at 26/26.


There will be some algorithms that determine according to certain settings what to apply, my guess is that the algorithm is lacking some information to apply the "correct" values.

Re IOD, I previously stated I would be leaving it on AUTO, which give 1.15v, so I have dropped it to 1.12v, but I am at 4133/2067 which obviously needs more IOD than 3800/1900 ....


----------



## Audioboxer

mongoled said:


> There will be some algorithms that determine according to certain settings what to apply, my guess is that the algorithm is lacking some information to apply the "correct" values.
> 
> Re IOD, I previously stated I would be leaving it on AUTO, which give 1.15v, so I have dropped it to 1.12v, but I am at 4133/2067 which obviously needs more IOD than 3800/1900 ....


I'll have a play around with multiple voltages, but I was testing VDDP yesterday trying to get 26/26 at 2T with tCL15. As I said most of the pictures of ZenTimings I managed to find yesterday featuring a 5950x did have 28 tCL14/1T. Even ones with GDM enabled, and across a range of voltage values.

I'm quite happy enough with 1T/56 on tCL15 I can easily get 26/26. My benchmark comparisons with tCL14 on 2T might decide where I land. I don't want to run 28/26 so it's either tCL14 2T or tCL15 1T at the moment.

I had a rare case of a TM5 timeout last night at cycle 10, haven't seen one of those for ages. Eased up on tRFC a few notches and it's given me a nice round 130ns  This passed a 25 cycle. I knew 245 was right on the edge of stability at 1.5v, especially with temps around 40~41. CPU is at default just now so unlike in the past it's not a curve that caused it. I think TM5 timeouts can also be very minor RAM instability, maybe not enough to error TM5 but enough to randomly cause a crash.


----------



## Blameless

Veii said:


> The signing keys are old. There are zero-day exploit .dll's from year 1901 in the current windows
> I wouldn't trust it - especially since intel announced OTA microcode updates "just recently"
> 
> Both WinSxS and Sys32


I'd rather not have sfc and DISM fail integrity checks unless I can demonstrate some advantage with removing/renaming the files.



Veii said:


> Soo 10 out of 10 error sources right ?
> I got 9 / 10


Yes. 10 sources, record format version 10, and ten information event 42s (nine before the even ID 5, one after) each startup.



Veii said:


> Never figured out that Vcore sensor


Mine seems to track closely to half of requested core VID. Probably HWiNFO misinterpreting something.



TimeDrapery said:


> Most especially those called, "MR6VrefDQ Control" and "CPU Vref Training Seed Control"? Considering they're found under "AMD CBS" I presume they take input in hexadecimal... What good are they?


On my MSI boards they are listed as setup times, the first one with a range of 0-127 and the other with a range of 0-255, in decimal, but I've seen other boards list them differently and want input in hex...MR6 is 7-bits long and the other evidently 8-bits so how that's translated should be immaterial.

Haven't played with them much, and didn't notice much when I did. Might investigate them further at some point.

The PMU training seed in the same area seems to improve the results of memory training (faster memory), if training can pass. The highest setting is normally 10 (dec) or a (hex). I usually set it to maximum on any board with the setting (all of my MSI, ASUS, and Gigabyte AM4 boards, but not my ASRock).



TimeDrapery said:


> Also, "A_VDD18S5"...? S5 makes me sleepy... Same voltage for the two options though?


Analog 1.8v?

S5 is power off, so probably meaningless except for some sort of standby power for something. I probably wouldn't mess with it unless I was having issues with WOL or something that's supposed to wake the system from power off.

The normal 1.8v is the CPU PLL voltage.


----------



## mongoled

mongoled said:


> So I dropped IOD to 1.12v and guess what,
> 
> my dimms moved to 28/26 ...
> 
> So you may have others things to test
> 
> 
> 
> Just testing with Y-Cruncher at 28/26 to see if it stops failing ..


Looking like an unstable memory overclock, 2 hours have just elapsed in the Y-Cruncher test, was getting nowhere near that duration when it was on 26/26, going to leave it for another hours then onto to finding what's required to stabilise the overclock with 26/26..

** EDIT **
Yup, passed the 3 hour mark, reeeeeboot time ................


----------



## Zdenal

Hello Overclockers, I have been forced by my wife to build a own PC for her 👧 
I opted for AMD, specifically the 5800X. Because I had a free 4x8GB 3200C14 Gskill at home, I chose Dark Hero. Even for that, it has a completely unlocked BIOS. After reading the AMD memory OC section back and forth, I wanted to do an OC of at least 3800 with flat 14 and t2. It finally succeeded, even t1 with 56-0-0.
Now I'm wondering if it makes sense to try "pure" t1, or leave memory OC as it is, and move to OC the CPU 🤔


----------



## mongoled

Zdenal said:


> Hello Overclockers, I have been forced by my wife to build a own PC for her 👧
> I opted for AMD, specifically the 5800X. Because I had a free 4x8GB 3200C14 Gskill at home, I chose Dark Hero. Even for that, it has a completely unlocked BIOS. After reading the AMD memory OC section back and forth, I wanted to do an OC of at least 3800 with flat 14 and t2. It finally succeeded, even t1 with 56-0-0.
> Now I'm wondering if it makes sense to try "pure" t1, or leave memory OC as it is, and move to OC the CPU 🤔


Careful now your post is going to trigger a stampede

😂 😂

Very nice, someone got lucky

 

Go as high as you can go


----------



## Hale59

Zdenal said:


> Hello Overclockers, I have been forced by my wife to build a own PC for her 👧
> I opted for AMD, specifically the 5800X. Because I had a free 4x8GB 3200C14 Gskill at home, I chose Dark Hero. Even for that, it has a completely unlocked BIOS. After reading the AMD memory OC section back and forth, I wanted to do an OC of at least 3800 with flat 14 and t2. It finally succeeded, even t1 with 56-0-0.
> Now I'm wondering if it makes sense to try "pure" t1, or leave memory OC as it is, and move to OC the CPU 🤔


Can you quickly run the same memory test with same timings with just 2 sticks? Thanks


----------



## Audioboxer

Zdenal said:


> Hello Overclockers, I have been forced by my wife to build a own PC for her 👧
> I opted for AMD, specifically the 5800X. Because I had a free 4x8GB 3200C14 Gskill at home, I chose Dark Hero. Even for that, it has a completely unlocked BIOS. After reading the AMD memory OC section back and forth, I wanted to do an OC of at least 3800 with flat 14 and t2. It finally succeeded, even t1 with 56-0-0.
> Now I'm wondering if it makes sense to try "pure" t1, or leave memory OC as it is, and move to OC the CPU 🤔


Can you even dual rank bro? SR is for the peasants.



Just kidding with 4 sticks of SR that is very good what you've achieved so far. 1T pure could be a challenge on 4 sticks but I say have it at. I wouldn't be disheartened if its a struggle, you're in a great position just now.

Could be worth seeing if your SCLs can come down to 2-3.


----------



## mongoled

Hale59 said:


> Can you quickly run the same memory test with same timings with just 2 sticks/? Thanks


Just change the following

tRDRDSD/tRDRDDD to 5
tWRWRSD/tWRWRDD to 7
tRDRDSCL/tWRWRSCL to 2

and probably tRDWR to 7

Then 

RttWr: Disabled
RttPark: 6

No need for them to run the test with two sticks


----------



## mongoled

Audioboxer said:


> Can you even dual rank bro? SR is for the peasants.
> 
> 
> 
> Just kidding with 4 sticks of SR that is very good what you've achieved so far. 1T pure could be a challenge on 4 sticks but I say have it at. I wouldn't be disheartened if its a struggle, you're in a great position just now.
> 
> Could be worth seeing if your SCLs can come down to 2-3.


Not required for 4 x 8GB single rank 4/5 is where it is at


----------



## Hale59

mongoled said:


> Just change the following
> 
> tRDRDSD/tRDRDDD to 5
> tWRWRSD/tWRWRDD to 7
> tRDRDSCL/tWRWRSCL to 2
> 
> and probably tRDWR to 7
> 
> Then
> 
> RttWr: Disabled
> RttPark: 6
> 
> No need for them to run the test with two sticks


Sure it will work? You running Ryzen 5000, and I am on Ryzen 3000.

Let him do me the favor to run it.


----------



## Audioboxer

mongoled said:


> Not required for 4 x 8GB single rank 4/5 is where it is at


Good to know that, admittedly I'm a bit clueless with SR.

Here's me now thinking what happens if I bought a new mobo and 4x8GB for testing


----------



## mongoled

Hale59 said:


> Sure it will work? You running Ryzen 5000, and I am on Ryzen 3000.
> 
> Let him do me the favor to run it.


For sure he can do the favour,

but he is on 5800x

From 4 single rank dimm to go to 2 single rank dimm, thats all that needs to be changed .....


----------



## mongoled

Audioboxer said:


> Good to know that, admittedly I'm a bit clueless with SR.
> 
> Here's me now thinking what happens if I bought a new mobo and 4x8GB for testing


Sounds like you have more money than time

🤣 😂 😂


----------



## Hale59

mongoled said:


> For sure he can do the favour,
> 
> but he is on 5800x
> 
> From 4 single rank dimm to go to 2 single rank dimm, thats all that needs to be changed .....


I am aware he is on 5000.
But I will check on your advice, soon.
@mongoled I have sent you a PM.


----------



## Hale59

@mongoled Sent you PM and fixed it


----------



## Veii

Hopefully these PMs are this time respectful phrased 
.
Experimented a bit by an old found screenshot








The only time i ever saw tPHYRDL being 24. While it refused to post fully at 3200 strangely
Don't remember seeing it on the pure 13-13-13 either strangely.

Experimenting with tRDRD drop & SCL rebalance (lower tRDRDSCL) , for getting tRDWR -1 to work 
Also jumping between 736 , 737 & 637 right now. 

It seems that tRDWR "distance" and SCL "amount" does change how low tPHYRDL can train. 
Back to 48.5 on stock stock - CMOS wiped my CBS, but it hits it now consistent.
Higher SCL and tRDWR missmatch loses 2000 MB/s
No luck with any SETUP time tho, nothing in the 31, 32, 33 range ~ but patterns make a bit more progress
L3 remains missing 40GB/s ~ nevertheless of PBO settings. Seems either win-update or current chipset drivers throttle back "infinite cache boost"


Spoiler


----------



## mongoled

Veii said:


> Hopefully these PMs are this time respectful phrased
> .
> Experimented a bit by an old found screenshot
> View attachment 2524181
> 
> The only time i ever saw tPHYRDL being 24. While it refused to post fully at 3200 strangely
> Don't remember seeing it on the pure 13-13-13 either strangely.
> 
> Experimenting with tRDRD drop & SCL rebalance (lower tRDRDSCL) , for getting tRDWR -1 to work
> Also jumping between 736 , 737 & 637 right now.
> 
> It seems that tRDWR "distance" and SCL "amount" does change how low tPHYRDL can train.
> Back to 48.5 on stock stock - CMOS wiped my CBS, but it hits it now consistent.
> Higher SCL and tRDWR missmatch loses 2000 MB/s
> No luck with any SETUP time tho, nothing in the 31, 32, 33 range ~ but patterns make a bit more progress
> L3 remains missing 40GB/s ~ nevertheless of PBO settings. Seems either win-update or current chipset drivers throttle back "infinite cache boost"
> 
> 
> Spoiler


tRC @39 is correct?

Had a quick play with your settings, no point on 4 x SR to push to 15 tCL as it pushes tPHYRDL to 28

So I am playing with this (will return to the 24/7 config later ..)

0.1v extra and the gain is only .3ns, so hard to get more out of this frequency and regular Windows install (only have AV disabled).


----------



## Hale59

@TimeDrapery you have PM...


----------



## TimeDrapery

Hale59 said:


> @TimeDrapery you have PM...


Yay! 😂😂😂😂😂 I'll scope that as soon as I've got a minute away from work

@mongoled 

They're coming! I got distracted by Curve Optimizer again! 😂😂😂😂😂


----------



## mongoled

@TimeDrapery 
You have a "Rep+" bot acting on your behalf ?
😂 😂 😂


----------



## TimeDrapery

mongoled said:


> @TimeDrapery
> You have a "Rep+" bot acting on your behalf ?
> 😂 😂 😂


Yeah, my OCD brain 😂😂😂😂😂

It's why I stay off social media... "Oooooh, a button!" and then I'm in trouble 😂😂😂😂😂


----------



## mongoled

TimeDrapery said:


> Yeah, my OCD brain 😂😂😂😂😂
> 
> It's why I stay off social media... "Oooooh, a button!" and then I'm in trouble 😂😂😂😂😂


Ouuuuuiiiiiiiii

😃😃


----------



## Zdenal

Hale59 said:


> Can you quickly run the same memory test with same timings with just 2 sticks? Thanks


Sure I will do it tomorrow.


----------



## Audioboxer

Ooft, I've been doing some RAM testing and this is the highest I've ever seen temps. It is a heatwave today though and my fan curve on my RAM is back down from 100% to like 40~60%.

No crashes though, I guess even just increasing tRFC a little bit can help it hold out.

I really need to get rid of these crap heatsinks, so I guess it's time to finally decide to watercool or not...

Speaking of that, unrelated, but does anyone know if a D5 pump would be okay to handle 3x360 rads and 1x120? Currently got 2x360 and 1x120. If I'm going to semi-drain to add the RAM to the loop I might pickup another 360 if my D5 pump won't totally die.


----------



## ManniX-ITA

Audioboxer said:


> No crashes though, I guess even just increasing tRFC a little bit can help it hold out.


Not too low tRFC and tRCD helps a lot.
My DR kit holds perfectly fine up to 56c after 2h of TM5.


----------



## Audioboxer

ManniX-ITA said:


> Not too low tRFC and tRCD helps a lot.
> My DR kit holds perfectly fine up to 56c after 2h of TM5.


I've literally moved from 245 to 247 lol










But 245 was literally like the cliff edge of stability at 1.5v. If I so much as sneezed at the RAM or, in my testing, gone to like 43~44 degrees, errors would crop up. Whereas if I kept it at 40 degrees it would last beyond 25 cycles at 245.

So maybe quite a bit to do with VDIMM coupled with temp just managing to push me off that cliff edge at 245.


----------



## mongoled

Audioboxer said:


> Ooft, I've been doing some RAM testing and this is the highest I've ever seen temps. It is a heatwave today though and my fan curve on my RAM is back down from 100% to like 40~60%.
> 
> No crashes though, I guess even just increasing tRFC a little bit can help it hold out.
> 
> I really need to get rid of these crap heatsinks, so I guess it's time to finally decide to watercool or not...
> 
> Speaking of that, unrelated, but does anyone know if a D5 pump would be okay to handle 3x360 rads and 1x120? Currently got 2x360 and 1x120. If I'm going to semi-drain to add the RAM to the loop I might pickup another 360 if my D5 pump won't totally die.


You will need two pumps, I'm guessing you will be going through CPU, GPU and probably RAM.


----------



## Veii

mongoled said:


> tRC @39 is correct?


It was a mistake, i catched myself later - but only had these as "pictured"

I instantly lose 2000 MB/s copy, if anything is slightly off ~ which means if tWRRD is +1 too much
Still trying to fix the slight "latency waste" on tRDWR ~ so far unsure about MSI vs stock "latency enhance mode"


Spoiler: Playing right now with





















Dual rank T-Force ARGB 14-15-15 1.45v, struggled to post 3600C14-14-14 2T / honestly didn't expect much on 1.45v binned kits, but still ^^'
MSI X570 Tomahawk Wifi
5 out of 10 sensors active. Realtek 2.5gbit
SMU 56.50 was a broken mess ~ SMU readouts missing
current public patch-C 56.52 was another broken mess, artifacts in the bios and restores failed Boot from Attempt 1, while failing boot attempt 2 after cmos
It loads settings which failed 2 reboots before onto the CPU - in this case IOD and CCD as 1.1v
Not capable to restore on bad memory training.

Glad for Eder's bios mod, so far functioning, but sample only hits 118 V/F score. Failed on stock loadlines CTR to be even "bronze" rated. Else with an AIO [email protected]
Founders edition illustration is on idle. 72C , 3080ti but horrible thermal pads.

CPU somehow struggles to boot 1020 CCD, 1120 IOD, 1.1875 SOC (too much CCD ?)
Board else looks good with 6 phase ISL 60A. But the bios is plain bad. Sadly this "badness" repeats from B450 to X570 now on all examples i could try.

It's only after october infront of me, soo no big records or anything for now ~ but just wanted to report a bit of things
All "clients" that are send to me , have somehow Bronze & Silver samples.
They had been following some twitter "Tweakers" who push high voltage allcores as "warzone runs better" . Close to all of them degrade their samples 

Anywho, little report
Maybe, hopefully this guys CPU is bugged as half of the sensors are missing.
Hopefully it wouldn't WHEA at 1900 and above, soo i can finally have 1 existing sample on realtek NICs. But you never know
Waiting for 1.2.0.4 bios so far

EDIT:
T-Force ARGB, have no thermal sensor :I
And 3080ti FE pushes hot air exactly on the dimms
Chipset holds 53c on idle, on an O11-Dynamic with 6 intake - 3 exh fans ~ soo vertical mount would be a bad idea too (PCH could crash)


----------



## Audioboxer

mongoled said:


> You will need two pumps, I'm guessing you will be going through CPU, GPU and probably RAM.


Meh, not up for the hassle of that just now, will just stick with what I've got then and add the RAM to the loop. Fitting another rad in the side of the case would be easy but working on a 2nd pump would be a PITA and might even need a 2nd commander pro.


----------



## duarte36

hello , just to post my experience. i have some Ripjaws kits , 3200 cl14 DR / SR , 2x16, 4x8 ,after getting tired of temps and those junk ripjaws , i got the royal elite 4000 cl14 . no bsod , only a few wheas 20 , what i searched and its supposed to be low vcore . so i'm trying to stabilize that for now. and i don't know yet if i'm gonna try to play with timmings .


----------



## MrHoof

Running with 2t for now to find the limit of the kit.
1.47v VDIMM









this is testing atm at 1.525 VDIMM









edit: and also this time again lower tRDWR>lower tCWL in aida atleast.









I take 1:30h for now, testing gonna continue later


----------



## jvidia

Hi!

What 32GB b-die kit do you recommend to run at [email protected] to use with my system?

I'm at the moment running at that speed and cl but I want to move into 32GB territory.

Thanks!


----------



## MrHoof

jvidia said:


> Hi!
> 
> What 32GB b-die kit do you recommend to run at [email protected] to use with my system?
> 
> I'm at the moment running at that speed and cl but I want to move into 32GB territory.
> 
> Thanks!


Well this kit above is the 2x16gb gskill 3600 14-15-15-35 1.45v bin. Dunno if lucky but looks like it can do that BUT 1T gonna be no fun


----------



## sonixmon

jvidia said:


> Hi!
> 
> What 32GB b-die kit do you recommend to run at [email protected] to use with my system?
> 
> I'm at the moment running at that speed and cl but I want to move into 32GB territory.
> 
> Thanks!


You didnt say your budget. If money is no object get 3800-4000 CL14 and then run it as fast as your fclk will go. Otherwise get 3600CL14 and OC as far as it can go like I did. 1T pure is (no setup or GDM) may or may not work for you (part of the Lottery).


----------



## Blameless

ManniX-ITA said:


> Very interesting this GPUOpen optimization document, thanks 👍
> So in Matisse at least there's still the CCM, one for every CCX.
> First time I see this Coherent Slave unit.
> Guess it's all about how they communicate with each other, which looks not much likely DDR4 as I thought.
> They also transfer data from one CCX to another.
> Looks more like the CS is controlling the DDR4 memory controller.


Bit of a throwback, but I just saw this on Anandtech: Does an AMD Chiplet Have a Core Count Limit?

According to AMD's recent HotChips presentation Zen3 CCXes use a bi-directional ring bus (much like pre-mesh Intel Core i parts), with the fabric interface evidently being one of the ring stops.

Further evidence that cores proper just contain cores, but may also have implications for diagnosing FCLK related cache hierarchy errors.

Also makes me wonder what the ring bus voltage is...wouldn't be surprised if it was CPU 1.8v/PLL, but it could easily be pre-LDO vcore or CLDO VDDG CCD.


----------



## Veii

Blameless said:


> Further evidence that cores proper just contain cores, but may also have implications for diagnosing FCLK related cache hierarchy errors.
> Also makes me wonder what the ring bus voltage is


If you compare Aida64 (L1+L2) & L3 Bandwidth "bugs" (when cores are unstable) and compare SiSandra - you can map out how it functions

L3 is a shared pool with multiple GMI connections who are load dependent
Between CCDs there is a bidirectional connection
Actually if you take a closer look at SiSandra, it's all these 78ns ones as "link amount"
Between cores there is a direct connection down to 2ns (neighbor connection)
Between the same CCX there is a multi link-connection (through cache but not always L3)

The CCX remains to be a CCX. But CCD is the interposer, no multi CCX ~ not directly
Take a closer look at the die shots and you can see each little cache complex (core + L1 + L2) is an own little puzzle piece with symmetrical connections on the sides for it's symmetrical neighbors
L3 shared pool remains centered which is close to how the EPYC diagram looks like

RIng (CCX) on ring (CCD) on ring (CPU) on tree (cores inside 1 CCX by half L3 cache section)

Numa per section is/will be used indicated by AGESA
~ which also has a connection to core interleaving, channel amount interleaving, CCX interleaving, ECC, and cache GMI interleaving
Especially the last part is important on this discussion of how "visible" L3 cache overdrives and how autocorrection is behaving

There is something missing , public sensor wise ~ on that i'm confident from a private standpoint
But i haven't seen bioses give the ability to control magnitudes.
The only similar in behavior thing, is PBO Scalar, and half or fullspeed DPM LCLK toggle
Yet this is only a part of something X user can influence.
We lack access to such. It's too early to babycry myself about the lack of this ~ when we get floor1 locked on maximum Boost Speed (sad)

There are more important things to complain about like,

lack of functioning APBDIS & STAMP / to safely overdrive FCLK further & fix wasted 20W on idle
lack of control on PROCHOT
lack of control on CCA , and EDC FUSE throttle
lack of override on SMNCLK & Boost FMAX
too low artificial limit on FIT PRE-V
And again, part 1 ~ no STAMP & variable SOC/FCLK 
While sensorics/residency functions. . .








EDIT:
I wonder if *x*GMI is CC*X* based, and GMI is CCD based 🤔


----------



## PJVol

Blameless said:


> I've never seen anyone actually try to get a physical measurement that could prove things either way


Not literally physical, but based on a smu telemetry data, it should be clear, what voltage rail is the source for the CLDO_VDDP:
Below is the max power observed during AIDA read bandwidth test (avg. out of 3 runs).


CLDO_VDDP set in bios, V0.900​0.950​1.000​VDDCR_SOC_POWER, W13.3​13.27​13.31​VDDIO_MEM_POWER, W11.75​12.24​12.80​



Veii said:


> But i haven't seen bioses give the ability to control magnitudes.


Isn't bios the only way to control it?
Perhaps you mean magnitudes visibility via firmware requests?



Veii said:


> lack of functioning APBDIS & STAMP


Just curious what STAMP is? Maybe you meant STAPM?
And what the purpose of overriding SMNCLK ? I may be wrong, but is it just the Control Fabric plane operating frequency ?


----------



## Henry Owens

duarte36 said:


> hello , just to post my experience. i have some Ripjaws kits , 3200 cl14 DR / SR , 2x16, 4x8 ,after getting tired of temps and those junk ripjaws , i got the royal elite 4000 cl14 . no bsod , only a few wheas 20 , what i searched and its supposed to be low vcore . so i'm trying to stabilize that for now. and i don't know yet if i'm gonna try to play with timmings .
> View attachment 2524195


Why don't you raise soc to 1.15?


----------



## Mach3.2

Veii said:


> SMU 56.50 was a broken mess ~ SMU readouts missing


SMU readout bug/broken power tables on certain BIOS versions(7C84v153, 7C84v15) can be fixed by loading defaults, save changes then rebooting back into the BIOS and manually entering all the options again. Restoring saved BIOS profiles w/ the bug seem to restore some hidden options, which will also restore the bug.



Veii said:


> Maybe, hopefully this guys CPU is bugged as half of the sensors are missing.


For what it's worth I also only have 5 WHEA sources active on my 5900X + X570 Tomahawk Wifi build, could be a motherboard thing. Mobo flashed with Eder's 7C84v17 modded BIOS.


----------



## ManniX-ITA

Veii said:


> I wonder if *x*GMI is CC*X* based, and GMI is CCD based


I've always thought the xGMI links are the GMI links dedicated to the iGPU.
If you change the speed in CBS menu doesn't have any effect on my 3800x/5950x.
Maybe someone with a 4/5xxxG can try if it does affect iGPU? @PJVol maybe?



PJVol said:


> Not literally physical, but based on a smu telemetry data, it should be clear, what voltage rail is the source for the CLDO_VDDP:


Awesome 
Didn't think VDDIO_MEM was in the telemetry data!
Half watt every 50mV is quite something.
Thanks for testing it.


----------



## RosaPanteren

Hmmm I get 4 enteries in the WHEA operational log everytime I boot, no matter I the bios is bone stock or I run PBO curve and mem OC

2x id 42 then one id 5 and another id 42

No more whea in operational log, error log or reported by HWinfo ect. if I run the pc for hours...just these on every startup


Freshly cleared cmos in pic and same operational whea appears









Looking back I have had this on both a 5800x and the 5950x with same mobo/dram

Is this "Normal" behavior or something I should try to mitigate


----------



## Mach3.2

RosaPanteren said:


> Hmmm I get 4 enteries in the WHEA operational log everytime I boot, no matter I the bios is bone stock or I run PBO curve and mem OC
> 
> 2x id 42 then one id 5 and another id 42
> 
> No more whea in operational log, error log or reported by HWinfo ect. if I run the pc for hours...just these on every startup
> 
> 
> Freshly cleared cmos in pic and same operational whea appears
> View attachment 2524236
> 
> 
> Looking back I have had this on both a 5800x and the 5950x with same mobo/dram
> 
> Is this "Normal" behavior or something I should try to mitigate


Normal behavior, you should only be worried about WHEA recoverable errors in system logs.


----------



## Henry Owens

Is there pll Voltage adjust on x570?
What would it mean if I can boot flck 2000 but when I start a stress test the computer shuts off?


----------



## Audioboxer

RosaPanteren said:


> Hmmm I get 4 enteries in the WHEA operational log everytime I boot, no matter I the bios is bone stock or I run PBO curve and mem OC
> 
> 2x id 42 then one id 5 and another id 42
> 
> No more whea in operational log, error log or reported by HWinfo ect. if I run the pc for hours...just these on every startup
> 
> 
> Freshly cleared cmos in pic and same operational whea appears
> View attachment 2524236
> 
> 
> Looking back I have had this on both a 5800x and the 5950x with same mobo/dram
> 
> Is this "Normal" behavior or something I should try to mitigate


Don't worry about that, setup a WHEA only warning/error log and that will catch the nasties










Warnings tend to the the IF nonsense (for me trying above 1900), errors tend to be if you're working on your curve like I was above and got core crashes during stability testing.


----------



## PJVol

ManniX-ITA said:


> I've always thought the xGMI links are the GMI links dedicated to the iGPU.


I think GMI is related to 1st zen connections and xGMI2 - inter-chip GMI - apperared later along with zen2 and chiplets, both IFOPs and IFIS.
In the Vermeer public doc's there are 6 link status registers dxio: : pcs - 4 _instSERDESAG0-AG3 (supposedly IFOP) and 2 _instSERDESAP2-AP3 (IFIS ??)

PS: Actually the opposite, G-links are inter-socket and P-links are for the IO. In 17h PPR (which has illustations, btw) CCD links referred to as GMI2.


----------



## Blameless

PJVol said:


> Not literally physical, but based on a smu telemetry data, it should be clear, what voltage rail is the source for the CLDO_VDDP:
> Below is the max power observed during AIDA read bandwidth test (avg. out of 3 runs).
> 
> 
> CLDO_VDDP set in bios, V0.9000.9501.000VDDCR_SOC_POWER, W13.313.2713.31VDDIO_MEM_POWER, W11.7512.2412.80


Thanks for checking that out.

Looks like the description of the value in the UEFI/documentation is correct.


----------



## jvidia

Anyone here with the G.Skill F4-4000C16D-32GTZRA ?


----------



## Blameless

Veii said:


> If you compare Aida64 (L1+L2) & L3 Bandwidth "bugs" (when cores are unstable) and compare SiSandra - you can map out how it functions
> 
> L3 is a shared pool with multiple GMI connections who are load dependent
> Between CCDs there is a bidirectional connection
> Actually if you take a closer look at SiSandra, it's all these 78ns ones as "link amount"
> Between cores there is a direct connection down to 2ns (neighbor connection)
> Between the same CCX there is a multi link-connection (through cache but not always L3)
> 
> The CCX remains to be a CCX. But CCD is the interposer, no multi CCX ~ not directly
> Take a closer look at the die shots and you can see each little cache complex (core + L1 + L2) is an own little puzzle piece with symmetrical connections on the sides for it's symmetrical neighbors
> L3 shared pool remains centered which is close to how the EPYC diagram looks like
> 
> RIng (CCX) on ring (CCD) on ring (CPU) on tree (cores inside 1 CCX by half L3 cache section)


Interesting analysis. Maybe I'm not visualizing things correctly, but I stil feel there is still a fair degree of uncertainty about exact layout...some of the stuff we can infer from what AMD has said, the physical die shots/x-rays, and latency benchmarks could fit more than one kind of topology.



Veii said:


> I wonder if *x*GMI is CC*X* based, and GMI is CCD based


Wouldn't it be the other way around? I'm under the impression that the x implies an inter-chip interconnect, rather than an intra-chip one.



ManniX-ITA said:


> Half watt every 50mV is quite something.


It's more than I was expecting, but since it's powering part of the memory PHY it should depend heavily on number of memory devices and the memory settings being used.



Henry Owens said:


> Is there pll Voltage adjust on x570?
> What would it mean if I can boot flck 2000 but when I start a stress test the computer shuts off?


The CPU 1.8v is the voltage you are looking for.

An immediate reboot means you are super flaky on either FCLK or memory stability. If you're confident the memory can handle 2000, my gut feeling is that, unless you have considerable headroom left with regards to vSoC, CLDO vDDG, and CPU 1.8v, you probably aren't going to stabilize 2000FCLK.


----------



## Zdenal

Hale59 said:


> Can you quickly run the same memory test with same timings with just 2 sticks? Thanks


So, 2x8 is much easier than I thought, interesting.
Anyway, there is 2x8 with just the same settings as 2x16, 2x8 with changes suggested by @mongoled, and just for fun I tried 4133 with flat 15 t1 56-0-0 and just quick test of TM5. Now I am tempted to stay with 2x8 a bit longer.


----------



## Hale59

Zdenal said:


> So, 2x8 is much easier than I thought, interesting.
> Anyway, there is 2x8 with just the same settings as 2x16, 2x8 with changes suggested by @mongoled, and just for fun I tried 4133 with flat 15 t1 56-0-0 and just quick test of TM5. Now I am tempted to stay with 2x8 a bit longer.


Does your 2x8GB at 3800/1900 1:1 passes memory test without errors?


----------



## umea

Audioboxer said:


> Yeah I wonder if its CPU more than memory for most of us. Part of me wishes I bought the 3800CL14 ranked kit for a bit more but then again it's 14-16-16-16 ranked and in theory a 3600CL14 14-14-14-14 bin should be pretty much the same as the 3800. Especially once you bump the rated 1.45v up to 1.5v to be in line with the 3800 kit. Ymmv though, bin is guaranteed, thinking you should get something with more voltage is not.
> 
> The 5950x seems to be the worst CPU to buy if you want to get into memory overclocking, but obviously you benefit massively in day to day use using such a CPU over getting flat 14s instead of flat 15. Just frustrating when you see some people win the silicon lottery with their 5950x and it doesn't seem to have such a sensitive IMC.
> 
> Did you ever manage 1T pure at flat 15? I even struggled with that. Though my side journey down the road of understanding voltage might help me revisit that. I've currently taken the flat 15 profile I was running at 1.5v max and am trying to see if I can now get it stable at 1.55v. Not only might that let me lower tRFC more it could have the ability to let me try 1T pure again. Especially with me now running a more sensible IOD than I ever have before. We'll see.
> 
> More posters might pickup these DR 2x16GB kits in the weeks and months to come and maybe we'll all learn a bit more. Heck, AMD/MSI have more to learn with these damn janky bios updates. Imagine letting loose a BIOS update that bugs VDDG voltages to 1.0v max


I can't even run pure 1T 3600 14 flat lolol.


----------



## ZealotKi11er

Is it just me or good ram with good timings are not sold as much as they used to be. Most kits are 3600 cl18-22.


----------



## Audioboxer

umea said:


> I can't even run pure 1T 3600 14 flat lolol.


I probably can't either. I mean my sticks are rated for 3600 flat 14, so do pass TM5 fine at that with GDM 1T. I've not tested 2T but I'm sure it's fine.

1T pure just seems to blow up my IMC, but I guess you've given me something to try on a rainy day, 1T pure at 3600 flat 14.


----------



## Zdenal

Hale59 said:


> Does your 2x8GB at 3800/1900 1:1 passes memory test without errors?


I did not try, because there is no point. It passed as 4x8, I expect it would pass 2x8 with the same settings as well as it´s basically much easier, no? I thought you are just interested in bandwidth comparison in between the two.


----------



## PJVol

Can someone tell me why 32MB of RAM is needed instead of 16GB? I mean, I can imagine such rare use cases where it might help, but judging by the user base of this very forum, 32 GB configs come across 3-5 times more often than with 16 GB...


----------



## ManniX-ITA

PJVol said:


> Can someone tell me why 32MB of RAM is needed instead of 16GB?


Personally I abuse tabs and have between 2-4 GB only for the browser always committed.
But most importantly, 8GB of RAM caching for my drives with Primocache.


----------



## ManniX-ITA

Blameless said:


> It's more than I was expecting, but since it's powering part of the memory PHY it should depend heavily on number of memory devices and the memory settings being used.


Indeed, my mem Power tops 13W at 900mV!


----------



## ManniX-ITA

PJVol said:


> I think GMI is related to 1st zen connections and xGMI2 - inter-chip GMI - apperared later along with zen2 and chiplets, both IFOPs and IFIS.


If I bring down to the lowest the GMI links speed, can't even POST.
It does have an effect on performances.
While the xGMI link settings below doesn't have any effect whatsoever.
Maybe they just don't get applied.

I think I've read someone claiming the xGMI settings in CBS are reducing the iGPU bus speed.
But I don't have an APU so I've never been able to check.


----------



## Mach3.2

PJVol said:


> Can someone tell me why 32MB of RAM is needed instead of 16GB? I mean, I can imagine such rare use cases where it might help, but judging by the user base of this very forum, 32 GB configs come across 3-5 times more often than with 16 GB...


I like 32GB.

I can easily max out 32GB of RAM back when I was still regularly stitching multiple photos together in Photoshop. Basically for photo/video editing software, it will use all the RAM it can, and if you have too little RAM, the data will overflow into swap space and you'll start to notice the software getting less responsive. The larger your document, the more RAM you need.

I'm also lazy, I have at least 50++ tabs opened on Chrome. 😅


----------



## PJVol

*@ ManniX-ITA & Mach3.2*
Ok guys, my curiosity is satisfied.
May be I haven't got such habbit to keep 100+ tabs in browser  (10-15 max. indeed)
... or my home PC is hardly ever been used other than for the occasional gaming or some urgent patch-fix-work on the company-side projects I involved. Though I'd like to note, having the same 16Gb in an office PC minus 3-4Gb eaten by IGP, and 2-3 IDE's being loaded simultaneously, work nice so far (Qt Creator and two IntelliJ).


----------



## Mach3.2

PJVol said:


> *@ ManniX-ITA & Mach3.2*
> Ok guys, my curiosity is satisfied.
> May be I haven't got such habbit to keep 100+ tabs in browser  (10-15 max. indeed)
> ... or my home PC is hardly ever been used other than for the occasional gaming or some urgent patch-fix-work on the company-side projects I involved. Though I'd like to note, having the same 16Gb in an office PC minus 3-4Gb eaten by IGP, and 2-3 IDE's being loaded simultaneously, work nice so far (Qt Creator and two IntelliJ).


I can probably get away with a 2*8GB kit even with my nasty habit of leaving 50++ tabs open in chrome. RAM consumption is currently 6.6/31.9GB. Highest I've seen it go with Chrome and bloatware running in the background is around 11GB of usage.

I'll usually close my browser before I start gaming anyway, so the only reason I have 32GB of RAM is because I felt like doing it.


----------



## PJVol

ManniX-ITA said:


> If I bring down to the lowest the GMI links speed, can't even POST.
> It does have an effect on performances.
> While the xGMI link settings below doesn't have any effect whatsoever.


Seems logical, looking at the scheme 










and since I'm right for this part ↓↓↓ , I'll try tomorrow


ManniX-ITA said:


> Maybe someone with a 4/5xxxG can try if it does affect iGPU?


----------



## ManniX-ITA

PJVol said:


> Seems logical, looking at the scheme


You mean that those xGMI links could be dedicated to I/O like USB/SATA/SoC?


----------



## PJVol

ManniX-ITA said:


> You mean that those xGMI links could be dedicated to I/O like USB/SATA/SoC?


Obviously they do, in a consumer quater-of-IOD. Whereas GMI2 are just IFOP's.


----------



## ManniX-ITA

PJVol said:


> Obviously they do, in a consumer quater-of-IOD. Whereas GMI2 are just IFOP's.


Thanks! I'll check it out.
In theory reducing to the minimum the speed should kill the M.2 drives throughput connected to the SoC.
And the USB as well.


----------



## XPEHOPE3

PJVol said:


> Can someone tell me why 32MB of RAM is needed instead of 16GB?


I need huge RAM disks for both work (temporary image-related dataset creation, and/or virtual machines) and for e.g. converting lossless music.


Mach3.2 said:


> I'm also lazy, I have at least 50++ tabs opened on Chrome.


I have 820 tabs in Firefox. It just doesn't load a tab unless you click on it  No,Chrome can't do the same. Yes, I need a Tree Style Tab extension to handle that much tabs. No, Firefox only uses 1GB currently (with 13 tabs loaded), not 16.


----------



## sonixmon

ManniX-ITA said:


> Personally I abuse tabs and have between 2-4 GB only for the browser always committed.
> But most importantly, 8GB of RAM caching for my drives with Primocache.


Agree currently at 4GB with Chrome as I type this LOL but it is probably an overkill for gaming.



XPEHOPE3 said:


> I need huge RAM disks for both work (temporary image-related dataset creation, and/or virtual machines) and for e.g. converting lossless music.
> I have 820 tabs in Firefox. It just doesn't load a tab unless you click on it  No,Chrome can't do the same. Yes, I need a Tree Style Tab extension to handle that much tabs. No, Firefox only uses 1GB currently (with 13 tabs loaded), not 16.


I need to revisit FF, been a few years and switched to Chrome because it follows me between PC's (I assume FF may do this now as well).

Has anyone tried making an OC profile for 8-16GB for gaming? I noticed in a video someone shared by buildzoid where he booted windows with limited ram for benchmarking. I mean not something for daily but could be interesting for competitive gaming...


----------



## mongoled

Zdenal said:


> So, 2x8 is much easier than I thought, interesting.
> Anyway, there is 2x8 with just the same settings as 2x16, 2x8 with changes suggested by @mongoled, and just for fun I tried 4133 with flat 15 t1 56-0-0 and just quick test of TM5. Now I am tempted to stay with 2x8 a bit longer.


Can you tell me if you noticed a difference in your L1 latency results when comparing your 2 x SR with 4 x SR AIDA benchmarks ?

I see my 2 x 8GB configs having around 1.0 to 0.7 ns better latency compared to 4 x 8GB with the same settings apart from those that I change for the different configs.


----------



## mongoled

Here is some info that may be beneficial to working out the FCLK "issues"

While testing the 4133/2067 profile ive noted the following.

As I am still getting the USB/Audio "sticking" issues here is what ive seen.

USB "sticking" issues only occur when the PC is not underload, if the PC is underload there is no "sticking"

The same for audio "sticking".

Seems to have something to do with how the Ryzen ecosystem schedules its power savings, in other words, a sync issue ...

I am now playing with chipset voltage and chipset CLDO voltage to see if they effect the "sticking" issue.

IOD voltage is not the full solution to issues when using high FCLK.

Disclaimer, as I am concentrating on IOD and chipset voltages, there is a possibilty that CCD voltage is also part of the equation, but my prior testing did not show this to be the case ...

** EDIT **
So.... ive pushed chipset voltage to 1.2v from the default 1.0v and pushed chipset cLDO to 1.25v from the default 1.2v.

Has definitely helped, at least over the several reboots, cold boots, but ive seen this before only for things to change on another day.

Will go back to stability testing with these voltages ...

** EDIT2 **
Maybe more to do with the distance between the two different voltages,

ive now set them to chipset voltage 1.0v (default voltage) and lowered cLDO voltage to 1.15v from default 1.2v.

Im still getting the odd "sticking" issue buts its acting in the same manner as using 1.2/1.25, 

will play with the delta value ....


----------



## Henry Owens

Blameless said:


> Interesting analysis. Maybe I'm not visualizing things correctly, but I stil feel there is still a fair degree of uncertainty about exact layout...some of the stuff we can infer from what AMD has said, the physical die shots/x-rays, and latency benchmarks could fit more than one kind of topology.
> 
> 
> 
> Wouldn't it be the other way around? I'm under the impression that the x implies an inter-chip interconnect, rather than an intra-chip one.
> 
> 
> 
> It's more than I was expecting, but since it's powering part of the memory PHY it should depend heavily on number of memory devices and the memory settings being used.
> 
> 
> 
> The CPU 1.8v is the voltage you are looking for.
> 
> An immediate reboot means you are super flaky on either FCLK or memory stability. If you're confident the memory can handle 2000, my gut feeling is that, unless you have considerable headroom left with regards to vSoC, CLDO vDDG, and CPU 1.8v, you probably aren't going to stabilize 2000FCLK.


I read that increasing the pll can possibly increase flck stability. That is the one setting I have not messed with.


----------



## ManniX-ITA

Henry Owens said:


> I read that increasing the pll can possibly increase flck stability. That is the one setting I have not messed with.


From my understanding the Intel's PLL corresponding should be CPU_VDD1.8.
It does have an effect on FCLK stability and speed.

But it has a massive impact on temperatures.
You need at least an AIO to raise it and with dual CCD must be a good one.
Going from 1.8V to 1.95V means over 10c more on my 5950x and leads to instability.

Also depending on settings doesn't always increase stability, could have the opposite effect.
On my setup is improving only at specific voltages, around 1.84V and 1.96V.
You need to test it with Linpack Extreme.


----------



## Henry Owens

ManniX-ITA said:


> From my understanding the Intel's PLL corresponding should be CPU_VDD1.8.
> It does have an effect on FCLK stability and speed.
> 
> But it has a massive impact on temperatures.
> You need at least an AIO to raise it and with dual CCD must be a good one.
> Going from 1.8V to 1.95V means over 10c more on my 5950x and leads to instability.
> 
> Also depending on settings doesn't always increase stability, could have the opposite effect.
> On my setup is improving only at specific voltages, around 1.84V and 1.96V.
> You need to test it with Linpack Extreme.


Ok so watching temps I could see with up to around 1.95?


----------



## Henry Owens

ManniX-ITA said:


> Personally I abuse tabs and have between 2-4 GB only for the browser always committed.
> But most importantly, 8GB of RAM caching for my drives with Primocache.


Would you use primocache with a gen 4 SSD?


----------



## ManniX-ITA

Henry Owens said:


> Ok so watching temps I could see with up to around 1.95?


Yes.
Check with Linpack Extreme benchmark and Geekbench 5.
If something is wrong some of the GB5 test results will start showing swinging results, dropping below the 100% baseline at default 1.8V.



Henry Owens said:


> Would you use primocache with a gen 4 SSD?


I do of course, only for L1 caching.
I have a Samsung 970 EVO Plus 500GB at Gen3 x2 for L2 caching of SATA HDDs and SSD.

Without caching:










With caching:










One of the very few software I bought and I'm fully satisfied with.
But I should have bought a better Gen4 SSD, the 980 Pro is weird; got busted by the good offer.


----------



## mongoled

ManniX-ITA said:


> Yes.
> Check with Linpack Extreme benchmark and Geekbench 5.
> If something is wrong some of the GB5 test results will start showing swinging results, dropping below the 100% baseline at default 1.8V.
> 
> 
> 
> I do of course, only for L1 caching.
> I have a Samsung 970 EVO Plus 500GB at Gen3 x2 for L2 caching of SATA HDDs and SSD.
> 
> Without caching:
> 
> View attachment 2524379
> 
> 
> With caching:
> 
> View attachment 2524381
> 
> 
> One of the very few software I bought and I'm fully satisfied with.
> But I should have bought a better Gen4 SSD, the 980 Pro is weird; got busted by the good offer.


Looks like a benchmark gimmick,

do you see differences in real world applications ??


----------



## ManniX-ITA

mongoled said:


> Looks like a benchmark gimmick,
> 
> do you see differences in real world applications ??


No trust me, not a gimmick 
Below the L1 cache size (minus overhead) is like working on a RAM disk.
SATA HDDs and SSDs are acting like an M.2 drive.
First time I play a game loading from HDD is faster than usual then it's just like it's on a SSD.


----------



## mongoled

ManniX-ITA said:


> No trust me, not a gimmick
> Below the L1 cache size (minus overhead) is like working on a RAM disk.
> SATA HDDs and SSDs are acting like an M.2 drive.
> First time I play a game loading from HDD is faster than usual then it's just like it's on a SSD.


So I would guess you must have 2000% rock stable memory overclock along with everything else so not to cause data corruption


----------



## ManniX-ITA

mongoled said:


> So I would guess you must have 2000% rock stable memory overclock along with everything else so not to cause data corruption


Yes that's crucial, it's one of the main reasons I have a BenchOS to test every profile change 
If I boot the main install with an unstable system could be a disaster.


----------



## Henry Owens

ManniX-ITA said:


> Yes that's crucial, it's one of the main reasons I have a BenchOS to test every profile change
> If I boot the main install with an unstable system could be a disaster.


I am pretty happy with my ram of or 3800 14-14-14-28 right now it is getting about 55 latency in Aida64 but 4000/2000 would just be badass. Sad my 5800 I returned did it easily, I didn't know what I had at the time.


----------



## duarte36

good morning all. i'm following along time ago, i have a dark hero and a 5900x that seem at leat a nice one. i was trying to play with ddr4 , but it seems like ripjaws are a joke in most of the time. i have 4x8gb ripjaws 3200 cl14 that does 4000 cl16 , that work for years in my 8700k overclocked to 5.0. 
now with ryzen 5900 x i got 3200 cl14 2x16Gb ripjaws DR , a really joke, i can't do anything with them beside docp . yesterday i received ma new kit royal elite gtes 4000 cl14 2x16Gb DR, before start playing around i only pu docp and fclk at 2000 . all works , but i get some whea's id: 20 , but like information, not like un error. all other settings are at default . if someone can help i appreciate . like i said before, if i can put it working normally like that i don't know if it worth trying to play around with timings, memorys are already ones of best.
i got 1 to 3 whea id 20 while working in the pc. if i'm gonna play something i get around 100/130 , but without problems, not bsod , or crashing. they are posted like information not like error.


----------



## Mach3.2

I was browsing the Asus Dark Hero Crosshair VIII OC thread and I noticed someone mentioning that VDDG IOD GET is capped below 1V in ZenTiming even when it is SET above 1V in the BIOS while runnnig the new AGESA 1.2.0.4 BIOS.

I remember @Audioboxer also noticed this on his MSI board. Can anyone with an Asus/Asrock board corroborate this finding on their boards running the AGESA 1.2.0.4 beta BIOS?


----------



## duarte36

Mach3.2 said:


> I was browsing the Asus Dark Hero Crosshair VIII OC thread and I noticed someone mentioning that VDDG IOD GET seem to be capped below 1V even when it is SET above 1V in the BIOS when runnnig the new AGESA 1.2.0.4 BIOS.
> 
> I remember @Audioboxer also noticed this on his MSI board. Can anyone with an Asus/Asrock board corroborate this finding on their boards running the AGESA 1.2.0.4 beta BIOS?


Yes , i tried the 3901 bios and i got much more wheas also. i roll back to 3801.
amd is trying to resolve the problem , trying to limit the boards . i'm start thinking that my 8700k @ 5000Ghz with ddr4 @ 4000 cl16 keep in good shape and work better than amd, that foul everybody. i hope i could be wrong....


----------



## Audioboxer

Mach3.2 said:


> I was browsing the Asus Dark Hero Crosshair VIII OC thread and I noticed someone mentioning that VDDG IOD GET is capped below 1V in ZenTiming even when it is SET above 1V in the BIOS while runnnig the new AGESA 1.2.0.4 BIOS.
> 
> I remember @Audioboxer also noticed this on his MSI board. Can anyone with an Asus/Asrock board corroborate this finding on their boards running the AGESA 1.2.0.4 beta BIOS?


Damn, so it's an AGESA 1.2.0.4 bug. Here I was going around just blaming MSI.

Well done AMD 

On another note has anyone actually managed 1933+ FCLK WITHOUT WHEA errors? I know many can boot/bench/run stability tests, heck I can boot 1933/1966/2000/2033 without any "holes" but always seeing some WHEA. I've done some voltage pumping, never managed to get completely WHEA free. Whereas 1900 can run like 0.925v on CCD/IOD without a WHEA


----------



## duarte36

Audioboxer said:


> Damn, so it's an AGESA 1.2.0.4 bug. Here I was going around just blaming MSI.
> 
> Well done AMD
> 
> On another note has anyone actually managed 1933+ FCLK WITHOUT WHEA errors? I know many can boot/bench/run stability tests, heck I can boot 1933/1966/2000/2033 without any "holes" but always seeing some WHEA. I've done some voltage pumping, never managed to get completely WHEA free. Whereas 1900 can run like 0.925v on CCD/IOD without a WHEA


that is what i'm looking for . i'm not having thousands of whea errors, i have 3 in a night of work . i got 100 if i start playing games.. i'm just trying to find what and if it's possible eliminate those few errors, i i dont whant to mess with all at the same time to get lost in that war against amd.  i hope i can fins a way to make those whea getting lost in space


----------



## PJVol

ManniX-ITA said:


> Maybe someone with a 4/5xxxG can try if it does affect iGPU? @PJVol maybe?


Can't find in my BIOS anything as low-level-ish as xGMI. These are the places in that awfully messed MSI menu tree, where i've been searching for it.

ed: Common Bios Settings are on 2nd pic. NBIO section have nothing related.


----------



## ManniX-ITA

PJVol said:


> Can't find in my BIOS anything as low-level as xGMI. These are the places in that awfully messed MSI menu tree, where i've been searching for it.


It's in the CBS menu but maybe only visible if fully unlocked.
I'll reboot later and take screenshots.


----------



## Audioboxer

Doing some benching there










Produced










But a few days ago










Produced










What is most likely to impact read/write/copy between those settings? The only real difference is a few points added to tRFC and tRCDWR.

I guess I have also tried changing the CPU 1.8v from 1.83v to 1.88v just to see if anything scaled. I can try reverting that. Or could it even be my CPU curve? I redid it after I reverted back from AGESA 1.2.0.4 due to the bugs. Can CPU boosting impact read/write/copy to the tune of hundreds?


----------



## Mach3.2

Audioboxer said:


> Doing some benching there
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Produced
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But a few days ago
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Produced
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> What is most likely to impact read/write/copy between those settings? The only real difference is a few points added to tRFC and tRCDWR.
> 
> I guess I have also tried changing the CPU 1.8v from 1.83v to 1.88v just to see if anything scaled. I can try reverting that. Or could it even be my CPU curve? I redid it after I reverted back from AGESA 1.2.0.4 due to the bugs. Can CPU boosting impact read/write/copy to the tune of hundreds?


Going from 8 to 15 for tRCDWR likely lost you that ~300MB/s of write and copy bandwidth.

tRFC can also affect memory bandwidth but I'm not a 100% sure that 2 ns difference robbed you of ~300MB/s in read bandwidth.


----------



## mongoled

@Audioboxer
AIDA64 can often have such differences (300-400 GB/s) in throughput from run to run variances.

In future use something like Dram calculator Memtest benchmark to compare different runs, the variance in time taken to complete the benchmark is small.

Mach3.2 remarks are valid, just we dont know if you did several runs or just one run ....


----------



## Audioboxer

Mach3.2 said:


> Going from 8 to 15 for tRCDWR likely lost you that ~300MB/s of write and copy bandwidth.
> 
> tRFC can also affect memory bandwidth but I'm not a 100% sure that 2 ns difference robbed you of ~300MB/s in read bandwidth.


And you are spot on










Is with










And I also noticed something I probably would have been more familiar with had I been more into benching memory before now which is AIDA64 can be a bit "off" with benching unless ran maybe twice or even a few times. I presume this is to do with how Ryzen chips boost and on first run might catch the chip "sleeping"?

Though I did try a few runs with tRCDWR at 15 and it never jumped to 597xx region. So its probably a combination of both.

Going to now test tCWL/tRDWR at 14/9 instead of 12/12. 14/8 only seems to boot on tCL14 for whatever reason lol.


----------



## Mach3.2

Audioboxer said:


> And I also noticed something I probably would have been more familiar with had I been more into benching memory before now which is AIDA64 can be a bit "off" with benching unless ran maybe twice or even a few times. I presume this is to do with how Ryzen chips boost and on first run might catch the chip "sleeping"?


I usually run my AIDA memory benches back to back for 7 runs after rebooting my bench OS and waiting for windows to settle down(usually about 4 minutes wait), and I always discard the first run. I then average out the 6 runs and that will usually give a pretty good ballpark indication of the expected read/write/copy/latency numbers.


----------



## Audioboxer

Mach3.2 said:


> I usually run my AIDA memory benches back to back for 7 runs after rebooting my bench OS and waiting for windows to settle down(usually about 4 minutes wait), and I always discard the first run. I then average out the 6 runs and that will usually give a pretty good ballpark indication of the expected read/write/copy/latency numbers.


Gotcha, I'm learning in the ways of benchmarking now 

Speaking of benching, does anyone have any results to compare to for DR 2x16 on a 5950x? Like what figures/latency are good to be aiming for at 3800? I have it in my head that DR latency along with running a 5950x will be higher than SR on other processors. I've seen a few of those 51.x SR results and I know that is out of the question. But I'm presuming around 54ns is a good result for my setup?

Read/write I'm used to seeing a lot of 59xxx around 3800, so I'm more familiar with that. It's latency I'm a bit more unsure of. Especially DR latency given a lot of bench screenshots end up being SR for the overclocking factor.


----------



## mongoled

After all these years I may have finally found a use for the following voltage controls !!

DRAM CH_A VREF Voltage
DRAM CH_B VREF Voltage

Seeing that Y-Cruncher was passing when dimms were defaulting to 28/26 and failing when dimms were defaulting to 26/26 I decided to give these voltages a try and viola Y-Cruncher is still going strong after 3 hours.

Basically I did the following, reduced CH_B (the "good" dimm slots when using a 4 dimm daisy chained board) by 0.01 volts (0.75v) and increased CH_A by 0.01 volts (0.77v) .

 










Could be a chance occurence so will need to test again after a few reboots, cold boots etc.


----------



## ManniX-ITA

Audioboxer said:


> The only real difference is a few points added to tRFC and tRCDWR.


Not a difference but it is really faster with SCL at 2 instead of 4/5?


----------



## Audioboxer

Audioboxer said:


> Gotcha, I'm learning in the ways of benchmarking now
> 
> Speaking of benching, does anyone have any results to compare to for DR 2x16 on a 5950x? Like what figures/latency are good to be aiming for at 3800? I have it in my head that DR latency along with running a 5950x will be higher than SR on other processors. I've seen a few of those 51.x SR results and I know that is out of the question. But I'm presuming around 54ns is a good result for my setup?
> 
> Read/write I'm used to seeing a lot of 59xxx around 3800, so I'm more familiar with that. It's latency I'm a bit more unsure of. Especially DR latency given a lot of bench screenshots end up being SR for the overclocking factor.


To answer my own question I forgot I had this in my bookmarks Zen RAM Overclocking

So here for example is a DR kit down at 51.2


http://imgur.com/Ap6qUNm


How much of that drop in latency though is to do with timings and how much would it be to do with CPU versus me being at 54ns on a 5950x?



ManniX-ITA said:


> Not a difference but it is really faster with SCL at 2 instead of 4/5?


I'll test that out for you, I kind of just left them there due to passing stability tests.


----------



## ManniX-ITA

duarte36 said:


> i got 1 to 3 whea id 20 while working in the pc.


The few occasions I got WHEA 20 were due to insufficient IOD / CCD voltages.
And it always ended with a WHEA 18 and black screen & reboot.
You should really fix it.


----------



## ManniX-ITA

Audioboxer said:


> How much of that drop in latency though is to do with timings and how much would it be to do with CPU versus me being at 54ns on a 5950x?


My usual latency at 3800CL14 was 54.1ns.


----------



## mongoled

@Audioboxer 
Thats a combination of several things, 1 CCD CPU, very low tRP, very low tRCDRD, very low tRFC and very low ambient temps ...

Non comparable to your setup


----------



## Audioboxer

ManniX-ITA said:


> My usual latency at 3800CL14 was 54.1ns.


That's great thanks, I'm pretty much around that










Thats with SCLs on 4 so it really doesn't make a difference. A few times my write speed seemed a bit lower but after running it 4 times it came up a bit. I guess if the SCLs on 2 don't seem to be doing much I am as well as leaving them at 4?

I guess there is possibly a small drop on write speeds, but I couldn't even tell you if the SCLs are predominantly about write. I thought they were latency 



mongoled said:


> @Audioboxer
> Thats a combination of several things, 1 CCD CPU, very low tRP, very low tRCDRD, very low tRFC and very low ambient temps ...
> 
> Non comparable to your setup


Yeah I know it's not comparable I just wanted to figure out what would be making the most difference, a 1CCD CPU seems to contribute a fair bit to lower latency. The rest you pointed out obviously helping a lot as well.

I've bought the Bykski 2 DIMM block so here is hoping I can get my memory temps down further now!


----------



## duarte36

ManniX-ITA said:


> The few occasions I got WHEA 20 were due to insufficient IOD / CCD voltages.
> And it always ended with a WHEA 18 and black screen & reboot.
> You should really fix it.


i'm trying , without mess with everything else for now. but it's just a good thing put the sticks at DOCP and everything else in auto he start and i never got a bsod until now. only thos whea 20. 
i was with plenty of doubts trying to do something with the old ripjaws, this kit arrived yesterday and i'm really glad. i was lucky that the first kit from ripjaws worked like a charm im my intel 8700k . 3200 cl 14 overclocked to 4000 cl16 @ 1.42v , and 8700k @5000Mhz for years, then i purchased ripjaws for AMD ... bad,really bad decision ^^


----------



## Hale59

Zdenal said:


> I did not try, because there is no point. It passed as 4x8, I expect it would pass 2x8 with the same settings as well as it´s basically much easier, no? I thought you are just interested in bandwidth comparison in between the two.


Lets not delve into that, because that is not I asked and you agreed upon.
Anyway, although our memory is 3200MHz CL14, is is not exactly the same memory.
My PCB is A1, 10 layers. What is yours?


----------



## Hale59

mongoled said:


> Just change the following
> 
> tRDRDSD/tRDRDDD to 5
> tWRWRSD/tWRWRDD to 7
> tRDRDSCL/tWRWRSCL to 2
> 
> and probably tRDWR to 7
> 
> Then
> 
> RttWr: Disabled
> RttPark: 6
> 
> No need for them to run the test with two sticks


unfortunately your suggestions do not work with my memory and the rest of my hardware.
But I have my ways to make it work, as I have shown previously.


----------



## Audioboxer

What surprises me is how little difference going from tCL15 to tCL14 can have if your secondary timings are already really tight. Which in turn makes me really want to try and look at 3833~4000 on memory and tCL15 or even 16 at 4000 if it was needed.

Just a shame I don't feel comfortable running with WHEA errors even if benching/stability tests will pass. Damn you AMD, make the BIOS better and the chips go a bit further  I don't seem to have any FCLK holes but even at 1933 I haven't been able to shut up WHEA.


----------



## domdtxdissar

Was building and installing a everyday computer for one of my family members earlier today and lol how easy it is to tweak a single CCD cpu running single rank memory compared to my normal rig 😆
Think i spent like 15mins to get pure T1 4000 running.. Pretty much everything is on auto except me inputting the memory timings manually and setting 1.5vdimm









Have also done a Sisoft Inter-Thread Efficency Performance Benchmark to verify i'm getting the same score with my 2x16 setup compared to my old 4x8 on my main rig... Numbers are pretty much identical so performancewise the cpu don't really care if its 2x16 or 4x8, dualrank is dualrank.









My old 4x8GB run:


----------



## sonixmon

Audioboxer said:


> What surprises me is how little difference going from tCL15 to tCL14 can have if your secondary timings are already really tight. Which in turn makes me really want to try and look at 3833~4000 on memory and tCL15 or even 16 at 4000 if it was needed.
> 
> Just a shame I don't feel comfortable running with WHEA errors even if benching/stability tests will pass. Damn you AMD, make the BIOS better and the chips go a bit further  I don't seem to have any FCLK holes but even at 1933 I haven't been able to shut up WHEA.


I agree, If only we could get to 1933-2000 fclk without WHEA!

So is that why my tphyrdl is almost always 28? I have one screenshot of it at 26 but it was one of the GDM On profiles and overall was slower. Should I be concerned with this or not? I have never really paid attention to this until you all mentioned it on thread. I have not seen the 26/28 issue myself though.

I am thinking of finding my best CL15 secondary timings and then benchmarking between CL14 and CL15 (if I have time).


----------



## Audioboxer

sonixmon said:


> I agree, If only we could get to 1933-2000 fclk without WHEA!
> 
> So is that why my tphyrdl is almost always 28? I have one screenshot of it at 26 but it was one of the GDM On profiles and overall was slower. Should I be concerned with this or not? I have never really paid attention to this until you all mentioned it on thread. I have not seen the 26/28 issue myself though.
> 
> I am thinking of finding my best CL15 secondary timings and then benchmarking between CL14 and CL15 (if I have time).


tPHYRDL is weird, I've seen one or two people manage 26/26 at 1T 3800 on a 5950x but I just can't get that replicated. It's always 28/26. I then can't answer whether that is down to ram, mobo, CPU, bios settings or a combination of multiple.

Makes little sense to me why switching the command rate has such an effect, especially in instances where nothing else changes. For example, 2T at tCL15 for me runs at 28/26 but 1T is 26/26. But 2T on tCL14 is 26/26 whereas 1T is 28/26. This is all at 3800 of course.

I've just given up worrying about it as the latency and benchmark figures I'm getting I'm happy with at tCL15 with 1T on setup. Once I get my waterblock and swap from these awful RipJaws heatsinks I'll see if temp being any lower can do anything else for my RAM. Failing that I think I'm nearing the end of my journey unless AMD can figure out more stable WHEA above 1900.

I'll stick around though for any findings Veii might come up with playing around with 2x16GB DR


----------



## XPEHOPE3

Henry Owens said:


> But I should have bought a better Gen4 SSD, the 980 Pro is weird; got busted by the good offer.


What other Gen4 SSD? WD 850 something?


domdtxdissar said:


> Think i spent like 15mins to get pure T1 4000 running


Is it 1usmus_v3_25-stable? Strange it didn't even need tCKE 


mongoled said:


> Basically I did the following, reduced CH_B (the "good" dimm slots when using a 4 dimm daisy chained board) by 0.01 volts (0.75v) and increased CH_A by 0.01 volts (0.77v) .


Just wow! Interesting how ZenTimings reports MEM VTT as max of per-channel voltages, not half of vDIMM. Also can't this trick be used to mitigate problems of single stick being unable to run good tRCDRD like in IIRC @Audioboxer case?
Also since your fix was kinda related to tPHYRDL, did you check if raising VDDP would also help to stabilize y-cruncher?


----------



## PJVol

domdtxdissar said:


> how easy it is to tweak a single CCD cpu running single rank memory compared to my normal rig


I would say the main contributing factor is tweaked architecture of Cezanne compared to Vermeer (from my little experience with both chips), mainly much more stable interconnections, plus a dozen of new features, disabled in Vermeer.


----------



## Zdenal

domdtxdissar said:


> Was building and installing a everyday computer for one of my family members earlier today and lol how easy it is to tweak a single CCD cpu running single rank memory compared to my normal rig 😆
> Think i spent like 15mins to get pure T1 4000 running.. Pretty much everything is on auto except me inputting the memory timings manually and setting 1.5vdimm
> 
> 
> Have also done a Sisoft Inter-Thread Efficency Performance Benchmark to verify i'm getting the same score with my 2x16 setup compared to my old 4x8 on my main rig... Numbers are pretty much identical so performancewise the cpu don't really care if its 2x16 or 4x8, dualrank is dualrank.


This has nothing to do with single/dual rank and 1/2 CCD. Although yes, SR IS easier, this your build is easier due to Cezanne, because IMC is part of the CPU die and it´s breeze to OC ram with it.


----------



## mongoled

XPEHOPE3 said:


> What other Gen4 SSD? WD 850 something?
> Is it 1usmus_v3_25-stable? Strange it didn't even need tCKE
> Just wow! Interesting how ZenTimings reports MEM VTT as max of per-channel voltages, not half of vDIMM. Also can't this trick be used to mitigate problems of single stick being unable to run good tRCDRD like in IIRC @Audioboxer case?
> Also since your fix was kinda related to tPHYRDL, did you check if raising VDDP would also help to stabilize y-cruncher?


In this scenario vDDP is already much higher than all my other config and it is this way as so to keep tPHYRDL at 26/26.

As already explained in previous posts, I could not get Y-Cruncher stable and TM5 was throwing different single errors on 25 cycle runs. 

Since changing the VREF voltages, I also have a completed TM5 25 cycle run. 

In the past I have tried to solve my single stick tRCDRD @15 issue using this but it does not help. tRCDRD wall is not voltage sensitive.


----------



## ManniX-ITA

XPEHOPE3 said:


> What other Gen4 SSD? WD 850 something?


There are many others now better.
The latest Corsair MP 600 Pro XT, the Sabrent Rocket 4 Plus, the Plextor M10P, the new MSI and Cardea models...


----------



## ManniX-ITA

PJVol said:


> Can't find in my BIOS anything as low-level-ish as xGMI. These are the places in that awfully messed MSI menu tree, where i've been searching for it.


Getting too old 
The speed setting in the BIOS is only for xGMI links.
What is split between GMI and xGMI is the Encryption control.
Maybe I remember an old CBS menu for the GB Master.

Reducing xGMI links speed to 6.4Gbps didn't hit the I/O performances.
Still 2.9GB/s copying from the 970 Pro on the PCH to the 980 Pro on the CPU.












Spoiler: This is where to find it on the MSI BIOS


----------



## mongoled

Finally have a nailed down config for 4133/2067 flat 16s without any random idle reboots.

Now need to do a few reboots, retests, to see if it holds...









But before doing that I need to check out the new 1.2.0.4 agesa to see if vDDG CCD/IOD has a max limit of 1.0v on my setup as that is going to throw a huge spanner in the works for alot of us



Oh and im sure ive got APBDIS set to 1 and DF C-States control to disabled so unsure what with the 217,000 (and others) Ghz CPU boost frequency

😂😂

** EDIT **
Ughhhh

same on my setup, I set

vSOC: 1.15v
vDDG IOD: 1.10v
vDDG CCD: 1.05v
vDDP 0.9v


----------



## Audioboxer

mongoled said:


> Finally have a nailed down config for 4133/2067 flat 16s without any random idle reboots.
> 
> Now need to do a few reboots, retests, to see if it holds...
> 
> View attachment 2524559
> 
> 
> But before doing that I need to check out the new 1.2.0.4 agesa to see if vDDG CCD/IOD has a max limit of 1.0v on my setup as that is going to throw a huge spanner in the works for alot of us
> 
> 
> 
> Oh and im sure ive got APBDIS set to 1 and DF C-States control to disabled so unsure what with the 217,000 (and others) Ghz CPU boost frequency
> 
> 😂😂
> 
> ** EDIT **
> Ughhhh
> 
> same on my setup, I set
> 
> vSOC: 1.15v
> vDDG IOD: 1.10v
> vDDG CCD: 1.05v
> vDDP 0.9v
> 
> View attachment 2524560


Yeah its an AGESA/AMD problem, not a board manufacturer problem.

AMD have unleashed a dud BIOS on everyone.


----------



## mongoled

Audioboxer said:


> Yeah its an AGESA/AMD problem, not a board manufacturer problem.
> 
> AMD have unleashed a dud BIOS on everyone.


My concerns are AMD are using this to "lock down" us overclockers 

😢


----------



## ManniX-ITA

mongoled said:


> My concerns are AMD are using this to "lock down" us overclockers
> 
> 😢


Naaa, they are just being again sloppy as they have been very often.
They have been overrun by gray aliens for sure, but that's another story


----------



## MrHoof

😁 I did it! What actuly made it work in the end was reseating or swapping the order of the dimms, got me to lower procODT working. 1.54v VDIMM









and here a DR 32GB1t vs SR 16GB 1T, DR has 1GB less read but 2GB more copy.


----------



## Mach3.2

MrHoof said:


> 😁 I did it! What actuly made it work in the end was reseating or swapping the order of the dimms, got me to lower procODT working. 1.54v VDIMM
> View attachment 2524575
> 
> 
> and here a DR 32GB1t vs SR 16GB 1T, DR has 1GB less read but 2GB more copy.
> View attachment 2524576


Very impressive latency.


----------



## Audioboxer

MrHoof said:


> 😁 I did it! What actuly made it work in the end was reseating or swapping the order of the dimms, got me to lower procODT working. 1.54v VDIMM
> View attachment 2524575
> 
> 
> and here a DR 32GB1t vs SR 16GB 1T, DR has 1GB less read but 2GB more copy.
> View attachment 2524576


Damn, just shows how much of a challenge a 2 CCD chip can be!










I doubt I'll beat that. I guess the write result is what happens from two CCDs?

Also interesting you've pretty much shown going from 14 to 15 tCL might not make much difference.

Then again I've got my curve going well on my 5950x so happy with it!


----------



## MrHoof

Audioboxer said:


> Damn, just shows how much of a challenge a 2 CCD chip can be!
> 
> I doubt I'll beat that. I guess the write result is what happens from two CCDs?
> 
> Also interesting you've pretty much shown going from 14 to 15 tCL might not make much difference.


ye 1 CCD has a write bandwidth limit cause of only a 16 bit bus while 32 bit for read, but has also a latency advantage.
Also since your kit is very similiar here what works for me 15-15-15-15-31-46-276 2T 1.47v and 14-8-14-14-26-40-240 2T at 1.525v for 1T 1.54v.

edit: But dunno how reliable those voltages are no readout anywhere, that is what I set in Bios.


----------



## domdtxdissar

XPEHOPE3 said:


> Is it 1usmus_v3_25-stable? Strange it didn't even need tCKE


Had to change a few settings and drop to T2 for 4266 MT/s speeds but still amazed how easy this platform with single rank is to tweak.. Its like night and day between my mainrig with dual ccd and dual rank memory 

Have spent close to zero time on this, and limited myself to under 1.2 vsoc because this is daily settings for family, but still happy with the results..
This Asus b550 strix f motherboard is missing pretty much all other voltage settings anyway..








This is actually way overkill anyway as this computer will manly be used to read and surf the internet and print some mails now and then 

This is my current dual CCD + dual rank memory mainsystem for comparison which i have spent months and countless hours tweaking: (also passes 25 cycles)








(*not done in windows safemode* )


----------



## sonixmon

domdtxdissar said:


> Had to change a few settings and drop to T2 for 4266 MT/s speeds but still amazed how easy this platform with single rank is to tweak.. Its like night and day between my mainrig with dual ccd and dual rank memory
> 
> Have spent close to zero time on this, and limited myself to under 1.2 vsoc, but still happy with the results..
> This Asus b550 strix f motherboard is missing pretty much all other voltage settings anyway..
> View attachment 2524582
> 
> This is actually way overkill anyway as this computer will manly be used to read to surf the internet and print some mails now and then
> 
> This is my current dual CCD + dual rank memory mainsystem for comparison: (also passes 25 cycles)
> View attachment 2524584
> 
> (*not done in windows safemode* )


Wow that is impressive, wonder if the IMC improved with G models or just good lottery? 

Interesting how SR is so much easier, everyone recommended DR and reviewers showed improved performance but if SR will OC better it may very well shrink or overcome that!?


----------



## Mach3.2

sonixmon said:


> Wow that is impressive, wonder if the IMC improved with G models or just good lottery?
> 
> Interesting how SR is so much easier, everyone recommended DR and reviewers showed improved performance but if SR will OC better it may very well shrink or overcome that!?


I don't think it's possible for 2* SR to beat 2*DR in copy bandwidth.


----------



## Zdenal

edit: please ignore, sorry for it.


----------



## ManniX-ITA

Zdenal said:


> It´s not impressive at all tbh, it´s all due to Cezanne APU. Because IMC is part of the die, those APU can go to mem oc 4800MHz easily. It has NOTHING to do with single / dual rank at all, he just don´t get it. There is a price tho, only PCIe 3.0 and half of the L3 cache. 4266 is rather poor, but let him dream.


Could you please just stop being offensive and childish, please?
Would be nice if you could take your Fight Club somewhere else.

Otherwise the admins will have to close and clean up again the thread. 
Which will leave us in the dark for days.

I think he knows more or less the difference being a seasoned overclocker.


----------



## Karagra

mongoled said:


> Finally have a nailed down config for 4133/2067 flat 16s without any random idle reboots.
> 
> Now need to do a few reboots, retests, to see if it holds...
> 
> View attachment 2524559


I wanted to test these timings out and was curious what you change around on this for (2) sticks of Steel Viper 4400CL19 vs your (4)?


----------



## Zdenal

edit: sorry again.


----------



## ManniX-ITA

Zdenal said:


> Sorry? How I am childish if I just explain the things? I am right and I was on topic. Now you are just offended me. I just told him the truth. Seriously, I don´t understand you.


Are you serious?



Zdenal said:


> *he just don´t get it*





Zdenal said:


> *but let him dream.*


If you don't understand that this is offensive and childish, I really can't help


----------



## Zdenal

edit: my fault, sorry.


----------



## ManniX-ITA

Zdenal said:


> While I was on topic, you started flood it with this trash talk


I'm not complaining you weren't on the topic or technically right. I actually agree on it.
It's the "trash talk", yours not mine, that is upsetting me.
If you want to start being offensive and start flaming with dom keep it private.
You answer was tailored to pick up a fight. Don't do it.


----------



## Zdenal

edit: my fault, sorry


----------



## ManniX-ITA

Zdenal said:


> Not at all! Maye because my english is not so good, if it sounds like that then I am really sorry, it was not mean like that.
> I will pay more attention next time.
> I did not want to fight anyone really, sorry for it.


Glad it was a misunderstanding, thanks


----------



## Audioboxer

domdtxdissar said:


> Had to change a few settings and drop to T2 for 4266 MT/s speeds but still amazed how easy this platform with single rank is to tweak.. Its like night and day between my mainrig with dual ccd and dual rank memory
> 
> Have spent close to zero time on this, and limited myself to under 1.2 vsoc because this is daily settings for family, but still happy with the results..
> This Asus b550 strix f motherboard is missing pretty much all other voltage settings anyway..
> View attachment 2524582
> 
> This is actually way overkill anyway as this computer will manly be used to read and surf the internet and print some mails now and then
> 
> This is my current dual CCD + dual rank memory mainsystem for comparison which i have spent months and countless hours tweaking: (also passes 25 cycles)
> View attachment 2524584
> 
> (*not done in windows safemode* )


Is it the 4000C14 kit that doesn't like 1T pure either? Such an expensive kit to get picky about 1T pure lol. Have you tested this kit with the Ryzen 7? No doubt its the 5950x IMC that makes 1T pure such a challenge.

*Edit* - Ignore me asking about the Ryzen 7, got your pictures mixed up with Mr Hoof on last page!


----------



## MrHoof

MrHoof said:


> and here a DR 32GB1t vs SR 16GB 1T, DR has 1GB less read but 2GB more copy.
> View attachment 2524576


ok nevermind there was still a bit left on the table just fixed tRDRDSD/tRDRDDD tWRWDD/tWRWSD to 6-6-4-4 and lowered tWTRS to 3, didnt think that would have such a impact.
More like 600MB less read and 2.4GB more copy and less latency 😁 Anyone can explain why SR has slightly better read performance?









The 194.51 was my SR 3800 16GB 15-8-14-14-26-260 kit.


----------



## domdtxdissar

Audioboxer said:


> Is it the 4000C14 kit that doesn't like 1T pure either? Such an expensive kit to get picky about 1T pure lol. Have you tested this kit with the Ryzen 7? No doubt its the 5950x IMC that makes 1T pure such a challenge.


Its the 2 best sticks from my old 4x8gb set shown below..
(before i got my current 2x16GB stick i tried playing around with the very same 2x8gb sticks which also gave me pure T1 on my current gaming 5950x rig, but sadly cpu IOD is still limiting me to 1900 fclk max even with single rank, but pure T1 was easy atleast)








The memory itself on the 5700g rig had no problem with 4000 MT/s @ pure T1, but like i said, had to drop to T2 for passing 25 cycles at 4266 speeds on this combo... Pretty sure being able to run pure T1 comes down to both CPU, memory(+rank) AND motherboard.. And i think this asus b550 strix f gaming sucks in regards to memory OC as it didn't even have IOD or CCD voltage control in bios.

Other limiting factor was time as i didn't spend much trying to optimize settings since this is a daily 24/7 computer for a novice family member which will pretty much only use it to read mail etc 

But just to reiterate, i have tested the follow combos on the same motherboard and cpu: (at 1900:3800)

2x8GB -> single rank = Pure T1 was easy (2sticks from the 4stick set)
4x8GB -> dual rank = setup time needed for T1
2x16GB -> dual rank = setup time needed for T1

Above was tested on my 5950x which refuse to scale above 1900:3800 and rev1.0 CH8 from 2019.
(did not test my 2x16 or the full 4x8GB on the 5700g as the new owner only bought 16 of my 32 gig set)

I hope i can maybe run pure T1 2x16GB when i get my 570s unify x max thanks to better memory layout/shielding, but if that don't work my last and only hope for pure T1 with dualrank is a 5950xt 3dnow! which i also will get when it get released 

(when i have gotten my new motherboard and cpu my brother will buy my current 5950x+CH8 and the last 2x8GB sticks from the 32gig set)


----------



## MrHoof

Here something I am confused about 🤣 Trying to run setup timings 55/56-0-0 results in a instant bluescreen for me "page fault in nonpaged area" on boot for 55 and for 56 while starting up tm5.


----------



## domdtxdissar

MrHoof said:


> Here something I am confused about 🤣 Trying to run setup timings 55/56-0-0 results in a instant bluescreen for me "page fault in nonpaged area" on boot for 55 and for 56 while starting up tm5.


Think *Veii *said he needed addcmdsetup 61 instead of the standard 56 a few pages back.. You can try to work your way up from 56 to the maximum 63. (but be prepared to reset/flash bios😆)

_edit_
He needed 60 for it to be stable


> About patterns,
> 58-0-0 did post with #0 spam
> 54 not post, following my scaling rulesets
> 56 post, BSOD
> 57 BSOD
> 58, #0 spam only, BSOD
> 59, #6 spam ~ rare #12 rare #0 no BSOD but bad Aida64 - also L1 crashes on Copy down to 1200GB/s
> 60, appears stable


----------



## MrHoof

I am not gonna try i guess, there is no flashback on my board. Just wanted to make some comparision benchmarks. I mean i just find it wierd that "pure" 1t works but setup timings dont.


----------



## PJVol

domdtxdissar said:


> Had to change a few settings and drop to T2 for 4266 MT/s


What are min tCL and tRCD (in ns) on that kit?
I've tried both my kits (G.Skill 3200CL15 and HOF 3600CL17), but failed to boot with tRCD lower than ~ 7.8ns no matter how much voltage DIMMs and SOC were fed, tried up to 1.6 Vdimm and 1.45 Vsoc - no go. 
May be I've reached the limit where tCL and tRCD just stop scaling.
The highest I've managed to boot and run tm5 is 4133 CL16 or 4400 CL18 HOF's and 4266 CL18 G.Skill.
4200 CL16 just refuse to post, since it lower than 7.5ns. 
Am I getting it right that CR2 won't help with unbootable CR1 settings, i.e. you'll need to boot with 1T anyway?


----------



## MrHoof

Well the same timings for me needed 0.015v more for 1T then 2T so if your getting to the voltage limit 2T might help.


----------



## PJVol

*MrHoof*
Im not sure its voltage limit, rather actual timings limit is reached. May be related to DIMM pcb physics.


----------



## domdtxdissar

PJVol said:


> What are min tCL and tRCD (in ns) on that kit?


This is what thaiphoon could read from my old 32GTZN kit
Since my 5950x is limited to 1900fclk without negative scaling i couldn't test the absolute limit on this set in regards to MT/s.. but lower then 14 tCL and tRCD @ 1900 was no bueno on what i would consider daily 24/7 voltages. (sub 1.57 vdimm)


















PJVol said:


> I've tried both my kits (G.Skill 3200CL15 and HOF 3600CL17), but failed to boot with tRCD lower than ~ 7.8ns no matter how much voltage DIMMs and SOC were fed, tried up to 1.6 Vdimm and 1.45 Vsoc - no go.
> May be I've reached the limit where tCL and tRCD just stop scaling.
> The highest I've managed to boot and run tm5 is 4133 CL16 or 4400 CL18 HOF's and 4266 CL18 G.Skill.5
> 4200 CL16 just refuse to post, since it lower than 7.5ns.
> Am I getting it right that CR2 won't help with unbootable CR1 settings, i.e. you'll need to boot with 1T anyway?


5700g @ 4266 =

Pure T1: didn't boot
T2: booted and ran 25 testmem cycles like nothing (10/10)
Didn't spend the time to find the correct setup-time for T1

5700g @ 4333 =

did not boot at T2
didn't try to lower timings / change RTT/DrvStr or increase the vsoc voltage above 1.2v due to time constraints


----------



## sonixmon

domdtxdissar said:


> Its the 2 best sticks from my old 4x8gb set shown below..
> (before i got my current 2x16GB stick i tried playing around with the very same 2x8gb sticks which also gave me pure T1 on my current gaming 5950x rig, but sadly cpu IOD is still limiting me to 1900 fclk max even with single rank, but pure T1 was easy atleast)
> View attachment 2524625
> 
> The memory itself on the 5700g rig had no problem with 4000 MT/s @ pure T1, but like i said, had to drop to T2 for passing 25 cycles at 4266 speeds on this combo... Pretty sure being able to run pure T1 comes down to both CPU, memory(+rank) AND motherboard.. And i think this asus b550 strix f gaming sucks in regards to memory OC as it didn't even have IOD or CCD voltage control in bios.
> 
> Other limiting factor was time as i didn't spend much trying to optimize settings since this is a daily 24/7 computer for a novice family member which will pretty much only use it to read mail etc
> 
> But just to reiterate, i have tested the follow combos on the same motherboard and cpu: (at 1900:3800)
> 
> 2x8GB -> single rank = Pure T1 was easy (2sticks from the 4stick set)
> 4x8GB -> dual rank = setup time needed for T1
> 2x16GB -> dual rank = setup time needed for T1
> 
> Above was tested on my 5950x which refuse to scale above 1900:3800 and rev1.0 CH8 from 2019.
> (did not test my 2x16 or the full 4x8GB on the 5700g as the new owner only bought 16 of my 32 gig set)
> 
> I hope i can maybe run pure T1 2x16GB when i get my 570s unify x max thanks to better memory layout/shielding, but if that don't work my last and only hope for pure T1 with dualrank is a 5950xt 3dnow! which i also will get when it get released
> 
> (when i have gotten my new motherboard and cpu my brother will buy my current 5950x+CH8 and the last 2x8GB sticks from the 32gig set)


I think the Strix B550-E is slightly better but dont know if would change the issue you had with voltage settings. This will be interesting to hear (when you test your new MB). I am wondering if a B550 would make a difference. One I have heard it is better for overall OC because you can push fsb a few MHZ to get more total OC. This does not work well with X570 chipset because it is very maxed out (PCIe lanes etc.). Again just what I read from an OC reviewer which makes me wonder if B550 would be less stress on CPU/IMC overall? Maybe not just wondering.

Anyone tried same ram/CPU in a B550 and x570 other models?


----------



## umea

Bored tonight so I'm going to try to see if I can hit rRCDRD 14 on a single stick (going to test both in each dimm), and potentially switching the sticks/dimms to see if that changes anything. I really want to hit 14 flat... even if it's at 2T or with setup timings.


----------



## Jdogdarkness

Hey i am glad to have stumbled onto this forum. Can someone explain to me how to use the tRFC calculator. Like am i only supposed to put in the timings or is the latency also need to be accounted for before etc? Or a thread explaining it. Thanks!
I THINK i have a great bin. Because i even with some weird problems in most benchmarks it over performs. But those remaining problems curtail stabilitly and consistency which is maddening! I can get mid 15k with my 5900x in 3Dmark timespy cpu portion with pbo on AT TIMES. With a pretty basic all core o.c can hit like 15700. There seems to be an L3 peculiarity which ive found some very limited information on but nothing definitive. Any help would be apreciated thank ya kindly!


----------



## Jdogdarkness

sonixmon said:


> I think the Strix B550-E is slightly better but dont know if would change the issue you had with voltage settings. This will be interesting to hear (when you test your new MB). I am wondering if a B550 would make a difference. One I have heard it is better for overall OC because you can push fsb a few MHZ to get more total OC. This does not work well with X570 chipset because it is very maxed out (PCIe lanes etc.). Again just what I read from an OC reviewer which makes me wonder if B550 would be less stress on CPU/IMC overall? Maybe not just wondering.
> 
> Anyone tried same ram/CPU in a B550 and x570 other models?


I haven't tried it but i have heard from Buildzoid and a few others that B550 has a more robust overclocking capability on memory and the cpu. I know that x570 can overclock fine but particularly like you said its the BCLK that really is the weakEST part of overclocking of those three areas on the x570. I see you got 3800mhz to run on your 5900x. For some reason mine doesn't like it. Will do above and below though lol


----------



## umea

umea said:


> Bored tonight so I'm going to try to see if I can hit rRCDRD 14 on a single stick (going to test both in each dimm), and potentially switching the sticks/dimms to see if that changes anything. I really want to hit 14 flat... even if it's at 2T or with setup timings.


Got distracted and forgot to do it but realized that it's honestly just not worth the trouble right now. Will see if a different cpu can hit flat 14s later on.. either way, here are both sides of this kit, any idea what PCB revision this is? F4-4266C17D-32GVKB-G.SKILL International Enterprise Co., Ltd.

















Also, is the only difference between the different lines for the same bin of kits just appearance/RGB? Should I want to buy another set, I'm unsure if I should go with Ripjaws V again (though the heatsink on this was god awful) or if the heatsink on the Royal kits are better.
This bin (and the other lines of this bin) are cool/interesting, although I know I am limited heavily currently by my CPU's chip.








F4-4000C14D-32GVK - G.SKILL International Enterprise Co., Ltd.


Ripjaws V DDR4-4000 CL14-15-15-35 1.55V 32GB (2x16GB) Ripjaws V series DDR4 DRAM memory is designed for sleek aesthetics and performance, making it an ideal choice for building a new PC system or for upgrading your system memory.




www.gskill.com












F4-4000C14D-16GVK - G.SKILL International Enterprise Co., Ltd.


Ripjaws V DDR4-4000 CL14-15-15-35 1.55V 16GB (2x8GB) Ripjaws V series DDR4 DRAM memory is designed for sleek aesthetics and performance, making it an ideal choice for building a new PC system or for upgrading your system memory.




www.gskill.com





I'm planning on building some PCs to sell soon, of which I think I could maybe use one temporarily to mess with a 5600x + SR to see how low I can push it... Either way, I'll see.


----------



## Audioboxer

umea said:


> Got distracted and forgot to do it but realized that it's honestly just not worth the trouble right now. Will see if a different cpu can hit flat 14s later on.. either way, here are both sides of this kit, any idea what PCB revision this is? F4-4266C17D-32GVKB-G.SKILL International Enterprise Co., Ltd.
> View attachment 2524671
> View attachment 2524672
> 
> 
> 
> Also, is the only difference between the different lines for the same bin of kits just appearance/RGB? Should I want to buy another set, I'm unsure if I should go with Ripjaws V again (though the heatsink on this was god awful) or if the heatsink on the Royal kits are better.
> This bin (and the other lines of this bin) are cool/interesting, although I know I am limited heavily currently by my CPU's chip.
> 
> 
> 
> 
> 
> 
> 
> 
> F4-4000C14D-32GVK - G.SKILL International Enterprise Co., Ltd.
> 
> 
> Ripjaws V DDR4-4000 CL14-15-15-35 1.55V 32GB (2x16GB) Ripjaws V series DDR4 DRAM memory is designed for sleek aesthetics and performance, making it an ideal choice for building a new PC system or for upgrading your system memory.
> 
> 
> 
> 
> www.gskill.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> F4-4000C14D-16GVK - G.SKILL International Enterprise Co., Ltd.
> 
> 
> Ripjaws V DDR4-4000 CL14-15-15-35 1.55V 16GB (2x8GB) Ripjaws V series DDR4 DRAM memory is designed for sleek aesthetics and performance, making it an ideal choice for building a new PC system or for upgrading your system memory.
> 
> 
> 
> 
> www.gskill.com
> 
> 
> 
> 
> 
> I'm planning on building some PCs to sell soon, of which I think I could maybe use one temporarily to mess with a 5600x + SR to see how low I can push it... Either way, I'll see.


I believe the 4000C14 DR kit is the best bin they sell or at least it's up there. Sold as being rated to run at 1.55v and guaranteed to run tRCDRD 15 at 4000.

I guess some people might say the 4000C16 rated kit at 1.4v is the best due how low the voltage is binned, but I'd wonder if the risk you run there is silicon and even at 1.55v on that kit you might not be able to match the one rated for it.

To sell something binned/rated for XMP there must be a little headroom unless the seller wanted lots of RMAs. So that to me suggests why the price of the 4000C14 kit is the highest 😆 Other than GSKILL wanting to take advantage of the overclocking community, a little lol. But that is memory for you, you can pay a lot less and end up with a golden bin, or pay a lot more to guarantee a higher chance of getting a golden bin.


----------



## Nighthog

domdtxdissar said:


> The memory itself on the *5700g* rig had no problem with 4000 MT/s @ pure T1, but like i said, had to drop to T2 for passing 25 cycles at 4266 speeds on this combo... Pretty sure being able to run pure T1 comes down to both CPU, memory(+rank) AND motherboard.. And i think this asus b550 strix f gaming sucks in regards to memory OC as *it didn't even have IOD or CCD voltage control in bios*.


VDDG_CDD & IOD control is not available for AMD APU processors like 4650G and 5700G etc.
They are only available for the chips that have a separate IOD/CCD chips.

Nothing unusual that the 5700G didn't provide those voltage controls on the motherboard, they are not available for any APU. You only have SoC and CLDO_VDDP to adjust in general with them.


----------



## Nighthog

Audioboxer said:


> I believe the 4000C14 DR kit is the best bin they sell or at least it's up there. Sold as being rated to run at 1.55v and guaranteed to run tRCDRD 15 at 4000.
> 
> I guess some people might say the 4000C16 rated kit at 1.4v is the best due how low the voltage is binned, but I'd wonder if the risk you run there is silicon and even at 1.55v on that kit you might not be able to match the one rated for it.
> 
> To sell something binned/rated for XMP there must be a little headroom unless the seller wanted lots of RMAs. So that to me suggests why the price of the 4000C14 kit is the highest 😆 Other than GSKILL wanting to take advantage of the overclocking community, a little lol. But that is memory for you, you can pay a lot less and end up with a golden bin, or pay a lot more to guarantee a higher chance of getting a golden bin.


They don't bin for GDM:disabled 1T...
I noted one Crucial 4400Mts 19-19-19 kit only did 19-19-19 with GDM:Enabled while GDM:disabled 1T it needed to relax tRCDRD to 20 to be stable.
They are´"tight" for the binning sometimes.

Not as much headroom as you might think.


----------



## umea

Audioboxer said:


> I believe the 4000C14 DR kit is the best bin they sell or at least it's up there. Sold as being rated to run at 1.55v and guaranteed to run tRCDRD 15 at 4000.
> 
> I guess some people might say the 4000C16 rated kit at 1.4v is the best due how low the voltage is binned, but I'd wonder if the risk you run there is silicon and even at 1.55v on that kit you might not be able to match the one rated for it.
> 
> To sell something binned/rated for XMP there must be a little headroom unless the seller wanted lots of RMAs. So that to me suggests why the price of the 4000C14 kit is the highest 😆 Other than GSKILL wanting to take advantage of the overclocking community, a little lol. But that is memory for you, you can pay a lot less and end up with a golden bin, or pay a lot more to guarantee a higher chance of getting a golden bin.


Yeah my bin is pretty good, but 4000cl14 seems to be the best for sure as like you said, 1.55v XMP means that there's probably even more headroom safely above that. To be honest I think the most limiting factor of my OC is just 5900x being a pain in the ass to get to run stuff like 14 flat.. Of course, it doesn't make sense to use a 5600x over a 5900x in terms of frames but when I end up building some PCs I'll keep one for a while to mess with ram OC on a 5600x just to see what is actually possible with my kit on a non 2ccd cpu. More than anything I'm curious how far we can push DR, and a 5900x is not ideal to see that it seems.


----------



## Audioboxer

Nighthog said:


> They don't bin for GDM:disabled 1T...
> I noted one Crucial 4400Mts 19-19-19 kit only did 19-19-19 with GDM:Enabled while GDM:disabled 1T it needed to relax tRCDRD to 20 to be stable.
> They are´"tight" for the binning sometimes.
> 
> Not as much headroom as you might think.


Definitely, I mean more in terms of timings and how high you might be able to push voltage above 1.55v, but 1T pure is its own game.



umea said:


> Yeah my bin is pretty good, but 4000cl14 seems to be the best for sure as like you said, 1.55v XMP means that there's probably even more headroom safely above that. To be honest I think the most limiting factor of my OC is just 5900x being a pain in the ass to get to run stuff like 14 flat.. Of course, it doesn't make sense to use a 5600x over a 5900x in terms of frames but when I end up building some PCs I'll keep one for a while to mess with ram OC on a 5600x just to see what is actually possible with my kit on a non 2ccd cpu. More than anything I'm curious how far we can push DR, and a 5900x is not ideal to see that it seems.


The 2CCD processors are definitely a pain in the arse, but you benefit greatly in other ways I guess.

What I would say is I bought 3600 flat 14 thinking 3800 flat 14 would be easily achievable and I have been struggling a bit. So much so instead of obsessing over it I've just gone for 3800 tCL15. I would presume getting 4000 at 14-15-15-15 is more likely to at least run 3800 flat 14 on the more stubborn processors, but that comes at the added premium of over £100 more than the 3600 flat 14 kit.

And it is STILL not a guarantee. There is a reason I would presume GSKILL haven't been selling a 3800 14 flat kit. They went from 3600 14-14-14-14 to 3800 14-16-16-16 to 4000 14-15-15-15  Skipping the most commonly run AMD IF/memory combo for flat 14, chip permitting, which will be 1900/3800 on Zen 3. I mean I'm surprised they didn't aim for 14-15-15-15 on that 3800 bin.

Though who knows, maybe that is still to come to milk more money out of the OCing community. The 4000 bin at 1.55v is the newest that's come out this year, it being released later than the 3800 14-16-16-16 bin.


----------



## o1dschoo1

Audioboxer said:


> I believe the 4000C14 DR kit is the best bin they sell or at least it's up there. Sold as being rated to run at 1.55v and guaranteed to run tRCDRD 15 at 4000.
> 
> I guess some people might say the 4000C16 rated kit at 1.4v is the best due how low the voltage is binned, but I'd wonder if the risk you run there is silicon and even at 1.55v on that kit you might not be able to match the one rated for it.
> 
> To sell something binned/rated for XMP there must be a little headroom unless the seller wanted lots of RMAs. So that to me suggests why the price of the 4000C14 kit is the highest 😆 Other than GSKILL wanting to take advantage of the overclocking community, a little lol. But that is memory for you, you can pay a lot less and end up with a golden bin, or pay a lot more to guarantee a higher chance of getting a golden bin.


Its luck of the draw. My 3200 kit can do it lol.


----------



## Audioboxer

o1dschoo1 said:


> Its luck of the draw. My 3200 kit can do it lol.


My 3200C14 kit can't even go above RttPark1 over 3400 lol. Flat 15 at 3800 was even a no go, had to be flat 16. So yeah, you're right.


----------



## o1dschoo1

Audioboxer said:


> My 3200C14 kit can't even go above RttPark1 over 3400 lol. Flat 15 at 3800 was even a no go, had to be flat 16. So yeah, you're right.


Ive found and heard the royal bdie kits are a little better than the regular trident kits.


----------



## Mach3.2

Nighthog said:


> They don't bin for GDM:disabled 1T...
> I noted one Crucial 4400Mts 19-19-19 kit only did 19-19-19 with GDM:Enabled while GDM:disabled 1T it needed to relax tRCDRD to 20 to be stable.
> They are´"tight" for the binning sometimes.
> 
> Not as much headroom as you might think.


I'm not sure if you've tried to downclock those Ballistix Max kits, but I'm wondering if the tRCDRD wall @ 3600MHz/3800MHz can be lowered to 15/16 or is it still around 17+ for those highly binned Ballistix Max kits?


----------



## Nighthog

Mach3.2 said:


> I'm not sure if you've tried to downclock those Ballistix Max kits, but I'm wondering if the tRCDRD wall @ 3600MHz/3800MHz can be lowered to 15/16 or is it still around 17+ for those highly binned Ballistix Max kits?


Micron tRCDRD works better for increased frequency than going down in frequency to try lower tRCDRD values.
These kits do GDM:disabled 1T @ 5000Mts with 23 tRCDRD for example.

I think they did tRCDRD @ 17 for 3800Mhz but I seem to have missed making any screenshots so have nothing to show for it. I was always trying to push the Frequency on these kits.


----------



## Audioboxer

o1dschoo1 said:


> Ive found and heard the royal bdie kits are a little better than the regular trident kits.


I wouldn't be surprised if the Royal kits are "super hand picked" but simultaneously it's also likely it's simply luck of the draw. As in, a RipJaws bin the same as a Royal bin has every chance to be better at OCing, you simply pay more for the better heatsinks and fancy RGB. Which many buyers are obviously happy to do, hence the RGB tax (though there is no doubting RipJaws heatsinks are total trash).

In terms of production to go through the extra effort of somehow making sure the bins for Royal can OC more than the bins for RipJaws would likely add extra time and cost over simply getting all the bins together that can 100% do, say, 4000 14-15-15-15 or 3600 14-14-14-14 and putting them into RipJaws/Trident Z/Royal. As long as they're sold at what they're rated for no buyer can have any legitimate complaint.

But this is simply speculation on my part on the basis of seeing total variation that sometimes has a RipJaw set performing better than a similarly binned Trident Z and vice-versa. Pure silicon lotterly. Even bins lower than other bins can sometimes come out top.

Though on top of memory bin you have mobos, IMC, cooling and more to deal with. Different bins doing better in the hands of different people due to their setups being different  Welcome to the memory game, strap in and have fun!


----------



## sonixmon

Jdogdarkness said:


> I haven't tried it but i have heard from Buildzoid and a few others that B550 has a more robust overclocking capability on memory and the cpu. I know that x570 can overclock fine but particularly like you said its the BCLK that really is the weakEST part of overclocking of those three areas on the x570. I see you got 3800mhz to run on your 5900x. For some reason mine doesn't like it. Will do above and below though lol


That is the review I saw as well, has me curious and may grab a good B550 board one day. I decided not to add a second PCI-4.0 nvme and stick with dual SSD raid 0 to save some money. So at this point a B550 would be enough for me. Probably not worth the effort but I may get board and try it. 

Yes I had a 5800x that would not do 1900 fclk (black hole issue) and WHEA over 1900 (1933-66). I grabbed a 5900x when they became available and were back at retail, thankfully it will run at 1900 but WHEA above. I didn't change any other components so it was definitely an IMC issue for me.


----------



## Audioboxer

sonixmon said:


> That is the review I saw as well, has me curious and may grab a good B550 board one day. I decided not to add a second PCI-4.0 nvme and stick with dual SSD raid 0 to save some money. So at this point a B550 would be enough for me. Probably not worth the effort but I may get board and try it.
> 
> Yes I had a 5800x that would not do 1900 fclk (black hole issue) and WHEA over 1900 (1933-66). I grabbed a 5900x when they became available and were back at retail, thankfully it will run at 1900 but WHEA above. I didn't change any other components so it was definitely an IMC issue for me.


I only ended up with a B550 due to my X570 crapping out, but I don't know if the FCLK issue is any different between B550 and X570. My understanding in terms of what Buildzoid is talking about is upping the bus speed over 100 Mhz. There is real issues doing that on the X570.

But if you're not looking to get a second 4.0 NVME drive I'd definitely say the B550 can offer some great value. The B550 Unify X's were going quite cheap in the UK for a while, though they're a bit scarce again at super cheap prices. Still at good prices though, at least compared to some of the rip off X570 prices because MUH RGB.

For the B550 Unify X though you have to make sure you'll be happy with 2 DIMMs. Fanless mobos all the way though, whether you go B550, X570S or I believe the Dark Hero is fanless. But I honestly don't think it's worth paying the price of the Dark Hero unless you have the budget and want it.

I got my B550 Unify X for like £165, a Dark Hero would cost me around/over £400. B550 Unify X at the moment in the UK is a bit nearer £200 now, but that's still half the price.


----------



## Owterspace

I own 2 kits of 3200C14 that I run together. My Royals are better than my Black and Whites hands down. They rip.


----------



## sonixmon

Audioboxer said:


> I only ended up with a B550 due to my X570 crapping out, but I don't know if the FCLK issue is any different between B550 and X570. My understanding in terms of what Buildzoid is talking about is upping the bus speed over 100 Mhz. There is real issues doing that on the X570.
> 
> But if you're not looking to get a second 4.0 NVME drive I'd definitely say the B550 can offer some great value. The B550 Unify X's were going quite cheap in the UK for a while, though they're a bit scarce again at super cheap prices. Still at good prices though, at least compared to some of the rip off X570 prices because MUH RGB.
> 
> For the B550 Unify X though you have to make sure you'll be happy with 2 DIMMs. Fanless mobos all the way though, whether you go B550, X570S or I believe the Dark Hero is fanless. But I honestly don't think it's worth paying the price of the Dark Hero unless you have the budget and want it.
> 
> I got my B550 Unify X for like £165, a Dark Hero would cost me around/over £400. B550 Unify X at the moment in the UK is a bit nearer £200 now, but that's still half the price.


Thanks for the feedback. Have you tried to play with fsb clock to gain a few mhz? Like I said probably not worth making a switch and overall I am happy with my MB but it is super sensitive to fsb.


----------



## umea

Realistically I probably will not be buying a ripjaws set again just due to the stock heatsinks being so trash, of course, I can still get fine results with them torn off and a 120mm fan running on them, but paying a bit extra for better heatsink (especially on an ITX mobo in my case) is fine by me. The real question is if I can turn off or remove the RGB while keeping the heatsink in tact/usable... Not a fan of RGB and I bet removing the RGB will give a .000001% increase in performance at least


----------



## Audioboxer

sonixmon said:


> Thanks for the feedback. Have you tried to play with fsb clock to gain a few mhz? Like I said probably not worth making a switch and overall I am happy with my MB but it is super sensitive to fsb.


Not yet it's actually something I forgot to revisit after a failed attempt at playing with it early on after getting my X570/3900XT combo.

Does it upset NVME drives or is it just SATA SSD drives you need to be careful with?



umea said:


> Realistically I probably will not be buying a ripjaws set again just due to the stock heatsinks being so trash, of course, I can still get fine results with them torn off and a 120mm fan running on them, but paying a bit extra for better heatsink (especially on an ITX mobo in my case) is fine by me. The real question is if I can turn off or remove the RGB while keeping the heatsink in tact/usable... Not a fan of RGB and I bet removing the RGB will give a .000001% increase in performance at least


I bought a water block so hopefully that rids me of me RipJaw heatsink woes. If I wasn't watercooling I'd definitely now pay the extra for better heatsinks. RGB apparently causes a tiny bit more stress on heat, but I don't think it's much. No idea why GSKILL didn't model the RipJaw heatsinks on the non-RGB Trident Z heatsinks. They were perfect.

And as you said RGB makes you go faster.


----------



## umea

What are signs of frying your ram? I tried running some timings on 1T pure and after the BSOD it seems like my RAM has a problem with over 1.55v.. previously stable settings are now erroring out with nothing else changing.. even more hair pulling scenarios.. For reference, was running 1.6v stable (overshot it just to be safe and check timings, ran 20 cycles of tm5), now the same settings error out with 1s and 4s and now some others as well.


----------



## umea

Audioboxer said:


> I bought a water block so hopefully that rids me of me RipJaw heatsink woes. If I wasn't watercooling I'd definitely now pay the extra for better heatsinks. RGB apparently causes a tiny bit more stress on heat, but I don't think it's much. No idea why GSKILL didn't model the RipJaw heatsinks on the non-RGB Trident Z heatsinks. They were perfect.
> 
> And as you said RGB makes you go faster.


I'm in an ITX case to make it travel ready so sadly I'm not going water cooling route, however next kit I buy will definitely be whatever cheapest one has the improved heatsinks on it.


----------



## Audioboxer

umea said:


> What are signs of frying your ram? I tried running some timings on 1T pure and after the BSOD it seems like my RAM has a problem with over 1.55v.. previously stable settings are now erroring out with nothing else changing.. even more hair pulling scenarios.. For reference, was running 1.6v stable (overshot it just to be safe and check timings, ran 20 cycles of tm5), now the same settings error out with 1s and 4s and now some others as well.


I'd probably go as far to say RAM is something that will just not post before its a massive issue. Other than situations where it does post and you potentially run the RAM for a longer period of time at really poor thermals (degrading it whilst its unstable).

There is a reason manufacturers offer all these "lifetime warranties" on RAM, it's pretty damn robust.

Though the above is hardly a scientific answer and I know before anyone quotes me there will be evidence online, especially on OCing forums, of people toasting their RAM.

tldr; You're more likely to nuke your Windows installation with unstable RAM before you nuke the RAM itself.


----------



## o1dschoo1

umea said:


> What are signs of frying your ram? I tried running some timings on 1T pure and after the BSOD it seems like my RAM has a problem with over 1.55v.. previously stable settings are now erroring out with nothing else changing.. even more hair pulling scenarios.. For reference, was running 1.6v stable (overshot it just to be safe and check timings, ran 20 cycles of tm5), now the same settings error out with 1s and 4s and now some others as well.


You should be good. People blast b die with 1.8v on air for benches regularly


----------



## sonixmon

Audioboxer said:


> Not yet it's actually something I forgot to revisit after a failed attempt at playing with it early on after getting my X570/3900XT combo.
> 
> Does it upset NVME drives or is it just SATA SSD drives you need to be careful with?


From what I read it can affect both, but most people are saying above 102. Not sure if they were on x570 though.

Of course YMMV










Hopefully 😂


----------



## mongoled

sonixmon said:


> From what I read it can affect both, but most people are saying above 102. Not sure if they were on x570 though.
> 
> Of course YMMV
> 
> View attachment 2524727
> 
> 
> Hopefully 😂


101.725 is the highest I can go.

But if you run no SATA devices it will scale alot higher, I've run up to 106.725 though have to add that this was on older BIOSs, have not tested this on newer BIOSs...


----------



## Audioboxer

sonixmon said:


> From what I read it can affect both, but most people are saying above 102. Not sure if they were on x570 though.
> 
> Of course YMMV
> 
> View attachment 2524727
> 
> 
> Hopefully 😂


Really don't feel comfortable trying it with a MP600 then cause I don't want that killed lmao.

And yeah IIRC my X570 wouldn't even post at 102.

In other news I found out what caused me to see a rare TM5 timeout, a core died in corecycler after like 18 hours. Wasn't one of the best 4, was one of the rest on -30. I did a new curve after the AGESA 1.2.0.4 shenanigans.

My prior curve topped out at -25, but I gave -30 a whirl on the rest this time. An overnight didn't pick it up but here I've let it go longer than an overnight and found the sneaky core. Back down to -25 for you.

Happy I gave it a go mind you (setting up a new curve), my boosting has been better on this new curve.

Also @mongoled I bought the third 360 rad, so I'm going to YOLO it into my build and see if 80-100% on the D5 handles the job. Along with the RAM block once it arrives. Some advice elsewhere said I should be fine as long as I'm happy to run the pump fast. I run it at like 80% anyway.


----------



## Audioboxer

Looks like Patriot is going to be stuffing new buyers with a worse bin. Not even sure if the 18-22-22-22 will even be b-die.

Just pointing it out as I've seen that patriot kit is quite popular.


----------



## mongoled

Guys/gals make your voices heard regarding the agesa bodged update! 





__





MSI Global English Forum


...




forum-en.msi.com


----------



## Luggage

Audioboxer said:


> Really don't feel comfortable trying it with a MP600 then cause I don't want that killed lmao.
> 
> And yeah IIRC my X570 wouldn't even post at 102.
> 
> In other news I found out what caused me to see a rare TM5 timeout, a core died in corecycler after like 18 hours. Wasn't one of the best 4, was one of the rest on -30. I did a new curve after the AGESA 1.2.0.4 shenanigans.
> 
> My prior curve topped out at -25, but I gave -30 a whirl on the rest this time. An overnight didn't pick it up but here I've let it go longer than an overnight and found the sneaky core. Back down to -25 for you.
> 
> Happy I gave it a go mind you (setting up a new curve), my boosting has been better on this new curve.
> 
> Also @mongoled I bought the third 360 rad, so I'm going to YOLO it into my build and see if 80-100% on the D5 handles the job. Along with the RAM block once it arrives. Some advice elsewhere said I should be fine as long as I'm happy to run the pump fast. I run it at like 80% anyway.


Cross posting this from the corecycler thread…


Luggage said:


> I have a new CO test workload - Blender Benchmark, scene Koro.
> 
> Still testing but, crashed one of my bad cores from -30 to -15. Repeatable.
> 
> Too late now but going to try it with my other “safe” cores tomorrow.


----------



## Mach3.2

sonixmon said:


> From what I read it can affect both, but most people are saying above 102. Not sure if they were on x570 though.
> 
> Of course YMMV
> 
> View attachment 2524727
> 
> 
> Hopefully 😂


My backup is a windows install USB 🤣


----------



## Veii

umea said:


> What are signs of frying your ram? I tried running some timings on 1T pure and after the BSOD it seems like my RAM has a problem with over 1.55v.. previously stable settings are now erroring out with nothing else changing.. even more hair pulling scenarios.. For reference, was running 1.6v stable (overshot it just to be safe and check timings, ran 20 cycles of tm5), now the same settings error out with 1s and 4s and now some others as well.


Lost memory channels on post are "near death" signs
If you have voltage issues on 1.55 where 1.56 could kill it, increase RTT_Park divider or lower the output ohm of it (same thing)

#4 you should not get in any case on any timings
CAD_BUS & RTTs are not timings
Technically setup and tCKE are, but they don't count here

Samsung 20mm IC's don't instantly die. They only get unstable at 1.71-1.73v (some at 1.78v)
PCBs die, either caps or resistors of it. I am not sure
ICs can not degrade either, but traces do oxidise by high current
Replugging them already cleans them, but doing it by hand once after long sessions (months) is advised
Unless you moved the PC, the likelyhood of oxidation is tiny. They are quite airtight pressed

Unstable PCB will show it's signs after 1.51v with negative scaling
The moment you start to lose channels, stop and back-down
#4 is a good sign that you do something stupid
But lost memory channels are the sign when you should cmos reset and don't continue pushing voltage further without drastic changes.

Usually boards can not spike-boot kill them if you push 1.7v out of nothing
But if its accepted, you need to be cautious
* on holidays atm, i saw my backtrack mentions


----------



## Henry Owens

MrHoof said:


> ok nevermind there was still a bit left on the table just fixed tRDRDSD/tRDRDDD tWRWDD/tWRWSD to 6-6-4-4 and lowered tWTRS to 3, didnt think that would have such a impact.
> More like 600MB less read and 2.4GB more copy and less latency 😁 Anyone can explain why SR has slightly better read performance?
> View attachment 2524620
> 
> 
> The 194.51 was my SR 3800 16GB 15-8-14-14-26-260 kit.
> View attachment 2524621


How do you go about setting proct odt/rttpark and clkdrvstrn?


----------



## umea

Veii said:


> Lost memory channels on post are "near death" signs
> If you have voltage issues on 1.55 where 1.56 could kill it, increase RTT_Park divider or lower the output ohm of it (same thing)
> 
> #4 you should not get in any case on any timings
> CAD_BUS & RTTs are not timings
> Technically setup and tCKE are, but they don't count here
> 
> Samsung 20mm IC's don't instantly die. They only get unstable at 1.71-1.73v (some at 1.78v)
> PCBs die, either caps or resistors of it. I am not sure
> ICs can not degrade either, but traces do oxidise by high current
> Replugging them already cleans them, but doing it by hand once after long sessions (months) is advised
> Unless you moved the PC, the likelyhood of oxidation is tiny. They are quite airtight pressed
> 
> Unstable PCB will show it's signs after 1.51v with negative scaling
> The moment you start to lose channels, stop and back-down
> #4 is a good sign that you do something stupid
> But lost memory channels are the sign when you should cmos reset and don't continue pushing voltage further without drastic changes.
> 
> Usually boards can not spike-boot kill them if you push 1.7v out of nothing
> But if its accepted, you need to be cautious
> * on holidays atm, i saw my backtrack mentions


Thanks, seems to have fixed itself or rather the settings I was trying were just inherently borked. Testing these primaries now, seems stable. Can't tighten them any further without erroring out (though I might mess with tRAS and tRC since I had 22/36 running stable at some point) but looking to mess with RTT and tighten secondaries as much as I can before pushing for 1T with setup timings (as I can't boot pure 1T).


----------



## Veii

MrHoof said:


> ok nevermind there was still a bit left on the table just fixed tRDRDSD/tRDRDDD tWRWDD/tWRWSD to 6-6-4-4 and lowered tWTRS to 3, didnt think that would have such a impact.
> More like 600MB less read and 2.4GB more copy and less latency 😁 Anyone can explain why SR has slightly better read performance?
> View attachment 2524620
> 
> 
> The 194.51 was my SR 3800 16GB 15-8-14-14-26-260 kit.
> View attachment 2524621


Increase SCL to 3,4,5 the point where you got the most bandwidth out on 1-5-5-1-7-7
(Adapt tWRRD [x] = tRCD =|< than X * SCL)
Then drop tRDRDSCL to the one you are stable (lower = better for chipselect)
Also first drop both DD's to 2 and try to stabilize them ~ after testing SCL on 1-5-5-1-7-7
At the end you can go with uneven SCL + 1-5-2-1-7-2 
But crucial is to focus on bandwidth here before mixing both, as it will get unstable alone by changing SD/DD's

* bad tWRRD or SCL will result in a loss of 4-5GB/s bandwidth
Even when stability is held up


----------



## Audioboxer

Luggage said:


> Cross posting this from the corecycler thread…


Thanks I'll give that a go today!










No WHEA issues but I guess I'll run it a few times.


----------



## mongoled

Audioboxer said:


> Some advice elsewhere said I should be fine as long as I'm happy to run the pump fast. I run it at like 80% anyway.


The advice is based on one key component and that is what is the optimum flow rate for a waterloop.

Its been generally accepted in water cooling circles that the optimum flow rate of a loop should be greater or equel to 1 GPM which is around 3.785 LPM, any flow rate below this will have diminishing returns.

My current loop consists of 2 radiators, 2 CPU blocks and one RAM block, the D5 in my loop running at full speed gives me a max flow rate of around 3.3 LPM.

I dont know if the flow meter is reliable, its something I need to test, but moving on...

My loop also has seven 90 degree bends which it has been said also restrict the flow of liquid.

So based on this information, of course you can run your loop with one D5, its up to you to decide if the performance you get out of your loop will be acceptable or not ....


----------



## Audioboxer

mongoled said:


> The advice is based on one key component and that is what is the optimum flow rate for a waterloop.
> 
> Its been generally accepted in water cooling circles that the optimum flow rate of a loop should be greater or equel to 1 GPM which is around 3.785 LPM, any flow rate below this will have diminishing returns.
> 
> My current loop consists of 2 radiators, 2 CPU blocks and one RAM block, the D5 in my loop running at full speed gives me a max flow rate of around 3.3 LPM.
> 
> I dont know if the flow meter is reliable, its something I need to test, but moving on...
> 
> My loop also has seven 90 degree bends which it has been said also restrict the flow of liquid.
> 
> So based on this information, of course you can run your loop with one D5, its up to you to decide if the performance you get out of your loop will be acceptable or not ....


I'll certainly be testing it and honestly reporting back. Due to the way my loop runs adding the radiator will be easy, as will taking it away if there are issues. Other than having to drain, but I've dealt with repeated draining after trying to fix my mobo dying and then graphics card dying 

I hear mixed reports on those flow meters you install and power off fan headers, but they're surely capable of giving a decent indicator. Good news for me is I minimized right angle bends in my loop and on top of that did pipe bending for those I needed rather than right angle fittings which are supposedly worse with flow.


----------



## Luggage

Audioboxer said:


> Thanks I'll give that a go today!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> No WHEA issues but I guess I'll run it a few times.


It doesn’t give whea - it crashes and fails to complete with too much neg CO.


----------



## Audioboxer

Luggage said:


> It doesn’t give whea - it crashes and fails to complete with too much neg CO.


That _should_ still result in this










When a core crashes it results in a red error WHEA, instead of the yellow warnings which come from trying to run 1900+ WHEA.

If it's a hard reboot the WHEA-Logger might not pick it up in time. The 3 above for me were cores crashing during CoreCycler.


----------



## rossi594

I am about to put a water block on my b-dies. From my calculations it should not matter which thermal pad I pick. (Even a 1.5 Wk/m should easyly be fine). Did anyone here make different experiences? Should I spend more on better pads?


----------



## ManniX-ITA

rossi594 said:


> I am about to put a water block on my b-dies. From my calculations it should not matter which thermal pad I pick. (Even a 1.5 Wk/m should easyly be fine). Did anyone here make different experiences? Should I spend more on better pads?


I would use good ones 

used this for my b-dies:








Gelid Solutions GP-Extreme – Thermal Pad 80x40x0.5mm. Ausgezeichnete Wärmeleitung, Idealer Lückenfüller. Einfache Installation Wärmeleitfähigkeit 12W: Amazon.de: Computer & Zubehör


Gelid Solutions GP-Extreme – Thermal Pad 80x40x0.5mm. Ausgezeichnete Wärmeleitung, Idealer Lückenfüller. Einfache Installation Wärmeleitfähigkeit 12W - Kostenloser Versand ab 29€. Jetzt bei Amazon.de bestellen!



www.amazon.de


----------



## rossi594

ManniX-ITA said:


> I would use good ones
> 
> used this for my b-dies:
> 
> 
> 
> 
> 
> 
> 
> 
> Gelid Solutions GP-Extreme – Thermal Pad 80x40x0.5mm. Ausgezeichnete Wärmeleitung, Idealer Lückenfüller. Einfache Installation Wärmeleitfähigkeit 12W: Amazon.de: Computer & Zubehör
> 
> 
> Gelid Solutions GP-Extreme – Thermal Pad 80x40x0.5mm. Ausgezeichnete Wärmeleitung, Idealer Lückenfüller. Einfache Installation Wärmeleitfähigkeit 12W - Kostenloser Versand ab 29€. Jetzt bei Amazon.de bestellen!
> 
> 
> 
> www.amazon.de


Lol, sorry to break it to you but yours were the worst in every test I read. (I would still consider those cheap ones).

I have some Fujipolys coming, but I could save those for a gpu if it doesn't matter.* Did you measure better temperatures with those over other pads?*


----------



## ManniX-ITA

rossi594 said:


> Lol, sorry to break it to you but yours were the worst in every test I read. (I would still consider those cheap ones).


More than this would be overkilling.
The Fujipoly are extremely good but also expensive.

They had an issue with the previous factory in China.
They were basically ripped off by their friendly forced Chinese partner 
The tests you see around are all based on Igor's Lab review.
Clearly those ones were awful. Even worse than any cheap 7 W/mK.

If they are in a plastic bag, as seen in Igor's video, they are bad.
Otherwise in a cardbox then are good.

I didn't compare them but they work fine.
And they are good otherwise wouldn't be used by almost everyone for the VRAM ICs and VRM part in the 3080/3090 threads.
There is better but not much at that price and not at all with the same Shore hardness level.


----------



## rossi594

ManniX-ITA said:


> More than this would be overkilling.
> The Fujipoly are extremely good but also expensive.
> 
> They had an issue with the previous factory in China.
> They were basically ripped off by their friendly forced Chinese partner
> The tests you see around are all based on Igor's Lab review.
> Clearly those ones were awful. Even worse than any cheap 7 W/mK.
> 
> If they are in a plastic bag, as seen in Igor's video, they are bad.
> Otherwise in a cardbox then are good.
> 
> I didn't compare them but they work fine.
> And they are good otherwise wouldn't be used by almost everyone for the VRAM ICs and VRM part in the 3080/3090 threads.
> There is better but not much at that price and not at all with the same Shore hardness level.


Igorslab test just happened in July, are you sure that those arrent the current ones? And how would I know that I am not getting the old / bad stock from a retailer? Gelid is from Hong Kong, so I assume they will manufacture in China again. With current shipping rates and the shipping delay ... I would be suprised if I would get ones from the new manufacturer anywhere.

I will ask them for a "new" sample and send it to igor, when I am in Hong Kong the next time. Then there shouldn't be any excuses if it still sucks.

Edit: should have read your post slower you told me how to tell.


----------



## ManniX-ITA

rossi594 said:


> Igorslab test just happened in July, are you sure that those arrent the current ones? And how would I know that I am not getting the old / bad stock from a retailer?


Problem is some seller in Amazon were sill shipping the bad batches.
But it's unlikely now.

They should arrive packaged as this:










Buy on Amazon and send them back in case.

But of course there are also alternatives:









One enjoy Thermalright Wärmeleitpads 12,8 W/mK, 85x45x0.5mm, Silikon Thermal Pad für Kühlkörper/GPU/CPU/LED-Kühler: Amazon.de: Computer & Zubehör


One enjoy Thermalright Wärmeleitpads 12,8 W/mK, 85x45x0.5mm, Silikon Thermal Pad für Kühlkörper/GPU/CPU/LED-Kühler: Amazon.de: Computer & Zubehör



www.amazon.de





The Odyssey are good albeit more expensive and stiff.

Those are praised by Igor:









EC360® Platinum 16,6W/mK Wärmeleitpad: Amazon.de: Computer & Zubehör


EC360® Platinum 16,6W/mK Wärmeleitpad: Amazon.de: Computer & Zubehör



www.amazon.de





But much more expensive (German engineering).

There is also a new line from Alphacool but they are extremely stiff and super expensive.


----------



## Audioboxer

I was just about to ask what thermal pads I should be using and what thickness lol. I'm presuming 0.5mm is the safe thickness? Wouldn't want the heatsinks not to be able to close.

Gelid also have this https://www.amazon.co.uk/Gelid-Solutions-GP-Ultimate-120x20x1-0mm-Installation/dp/B08MXB9Y6P/


----------



## rossi594

ManniX-ITA said:


> Problem is some seller in Amazon were sill shipping the bad batches.
> But it's unlikely now.
> 
> They should arrive packaged as this:
> 
> View attachment 2524783
> 
> 
> Buy on Amazon and send them back in case.
> 
> But of course there are also alternatives:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> One enjoy Thermalright Wärmeleitpads 12,8 W/mK, 85x45x0.5mm, Silikon Thermal Pad für Kühlkörper/GPU/CPU/LED-Kühler: Amazon.de: Computer & Zubehör
> 
> 
> One enjoy Thermalright Wärmeleitpads 12,8 W/mK, 85x45x0.5mm, Silikon Thermal Pad für Kühlkörper/GPU/CPU/LED-Kühler: Amazon.de: Computer & Zubehör
> 
> 
> 
> www.amazon.de
> 
> 
> 
> 
> 
> The Odyssey are good albeit more expensive and stiff.
> 
> Those are praised by Igor:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> EC360® Platinum 16,6W/mK Wärmeleitpad: Amazon.de: Computer & Zubehör
> 
> 
> EC360® Platinum 16,6W/mK Wärmeleitpad: Amazon.de: Computer & Zubehör
> 
> 
> 
> www.amazon.de
> 
> 
> 
> 
> 
> But much more expensive (German engineering).
> 
> There is also a new line from Alphacool but they are extremely stiff and super expensive.


The Alphacool ones are Fujipoly supplied. (At least the new ones with 11 / 14 / 17 Wm/k). At least the ones by Aquatuning. I just thought I'd pick up the cheapest ones that I can find in 120x20 and safe me the effort of cutting them to size (probably Phobya).

I referenced my calculations against the gddr6x power draw and pad benchmarks. (My results are inconclusive, I think the reason for the hot 3090 ics are not only their own power draw, but also the heat put into the pcb from the gpu).

Now I am a bit conflicted.


----------



## rossi594

Audioboxer said:


> I was just about to ask what thermal pads I should be using and what thickness lol. I'm presuming 0.5mm is the safe thickness? Wouldn't want the heatsinks not to be able to close.
> 
> Gelid also have this https://www.amazon.co.uk/Gelid-Solutions-GP-Ultimate-120x20x1-0mm-Installation/dp/B08MXB9Y6P/


After buying 8 of those for 4 dimms I would be spending more on the pads than on the water block.


----------



## rossi594

Nevermind my results match Igors observations. 7 W/(m*K) should be able to conduct less than the 55w output of the gddr6x, while there should not be any gain between the 11 and 17 W/(m*K).

I think I will go with the Phobyas and report back how it worked out. (I will just compare water and PCB temperature).


----------



## Audioboxer

rossi594 said:


> After buying 8 of those for 4 dimms I would be spending more on the pads than on the water block.


The cheaper ones can probably be cut up into the squares needed for the chips https://www.amazon.co.uk/Solutions-...-5mm-installation-Conductivity/dp/B01AAHL0QA/ I'm just looking for a confirmation on whether it's 0.5mm or 1mm for RAM?

In other news, call me crazy, but I'm going to give this bad boy a spin and keep the best out of the 2 bins I'll have










If that isn't easier to run flat 14 at 3800 then my IMC can go **** itself


----------



## rossi594

Audioboxer said:


> The cheaper ones can probably be cut up into the squares needed for the chips https://www.amazon.co.uk/Solutions-...-5mm-installation-Conductivity/dp/B01AAHL0QA/ I'm just looking for a confirmation on whether it's 0.5mm or 1mm for RAM?
> 
> In other news, call me crazy, but I'm going to give this bad boy a spin and keep the best out of the 2 bins I'll have
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> If that isn't easier to run flat 14 at 3800 then my IMC can go **** itself


It depends. With passive cooling it would not matter. The problem is the surface area of the heatspreader / heatsink. If you can't cool the air below ambient or generate more airflow you should not see any difference.

With liquid cooling you should follow the specs of datasheet for your cooler. (My EK one wants 0,5mm on the ic side and 1,5mm on the pcb side for single rank dimms).

*It will only make things easier if your dimms are erroring because they overheat.*


----------



## Audioboxer

rossi594 said:


> It depends. With passive cooling it would not matter. The problem is the surface area of the heatspreader / heatsink. If you can't cool the air below ambient or generate more airflow you should not see any difference.
> 
> With liquid cooling you should follow the specs of datasheet for your cooler. (My EK one wants 0,5mm on the ic side and 1,5mm on the pcb side for single rank dimms).
> 
> *It will only make things easier if your dimms are erroring because they overheat.*


Seeing as DR pretty much looks "the same" on either side I'd presume 0.5mm on both sides would be the safe shout. This Bykski 2 DIMM waterblock is likely going to come with some sort of thermal pads but they'll likely be the cheapest of the cheap. I will be able to see thickness I guess.


----------



## mongoled

Audioboxer said:


> Seeing as DR pretty much looks "the same" on either side I'd presume 0.5mm on both sides would be the safe shout. This Bykski 2 DIMM waterblock is likely going to come with some sort of thermal pads but they'll likely be the cheapest of the cheap. I will be able to see thickness I guess.


Dont assume anything !

The heat spreaders you purchase should come with specific instructions on what thickness pads to use dependent on the type of RAM you want to watercool.

The Alphacool heatspreaders compared to the EK Monarch are completely different with regards to the thickness of the pads that are required.

Skimp this detail at your peril

😝


----------



## Mach3.2

Hopefully it's still B-die. I'm getting a kit to see what I can do with it, and I'll probably sell it off to someone else after I'm done with it. 😃


----------



## Audioboxer

mongoled said:


> Dont assume anything !
> 
> The heat spreaders you purchase should come with specific instructions on what thickness pads to use dependent on the type of RAM you want to watercool.
> 
> The Alphacool heatspreaders compared to the EK Monarch are completely different with regards to the thickness of the pads that are required.
> 
> Skimp this detail at your peril
> 
> 😝


It's Bykski, I don't know what I should expect....

Only manufacturer I could get a 2 DIMM :/









32.1US $ 5% OFF|Bykski RAM Water Cooling Block use for Dual Channel 2pcs RAM Cooled / Copper Cooled RGB Radiator|Fans & Cooling| - AliExpress


Smarter Shopping, Better Living! Aliexpress.com




www.aliexpress.com





I can't even find any unboxings of it 



Mach3.2 said:


> View attachment 2524785
> 
> 
> Hopefully it's still B-die. I'm getting a kit to see what I can do with it, and I'll probably sell it off to someone else after I'm done with it. 😃


You should be OK with current stock, but yeah, that Buildzoid video will make you wonder a little.

#TeamSR, it's just... I want 32GB  I am interested to find out if my memory has any sort of responsibility for where my walls are or if it's nearly all on the IMC.

Given the 3600 14-14-14-14 and 4000 14-15-15-15 bins are very close in binning, I _think_ its 7ns vs 7.5ns, going to be interesting!

Up next, sending my PC with both bins to Veii and going "Pls sir, make these work!"


----------



## Mach3.2

Audioboxer said:


> You should be OK with current stock, but yeah, that Buildzoid video will make you wonder a little.
> 
> #TeamSR, it's just... I want 32GB  I am interested to find out if my memory has any sort of responsibility for where my walls are or if it's nearly all on the IMC.
> 
> Given the 3600 14-14-14-14 and 4000 14-15-15-15 bins are very close in binning, I _think_ its 7ns vs 7.5ns, going to be interesting!
> 
> Up next, sending my PC with both bins to Veii and going "Pls sir, make these work!"


I'd love to buy a 32GB kit of B-die but it's way over the "side project" budget. The fact that it's easier to tune SR sticks pretty much sealed the deal, with cost being the primary driving factor. 😅


----------



## Audioboxer

Mach3.2 said:


> I'd love to buy a 32GB kit of B-die but it's way over the "side project" budget. The fact that it's easier to tune SR sticks pretty much sealed the deal, with cost being the primary driving factor. 😅


Yeah the cost of 32GB (2x16) with the best bins is pretty ridiculous, but I guess GSKILL almost has that market totally cornered so can happily inflate prices. The others who are offering b-die mostly stick to SR or it's the much looser 2x16GB bins they sell.

I seen for example Corsair were offering that 4000 16-16-16-16 bin but it was 2x8GB only, GSKILL had the 2x16GB at 4000 16-16-16-16.


----------



## rossi594

Some of the Ram coolers have clearance issues between the heatspreaders because of the screws. Maybe you have to switch those out.


----------



## Audioboxer

rossi594 said:


> Some of the Ram coolers have clearance issues between the heatspreaders because of the screws. Maybe you have to switch those out.


I would like to think there won't be issues with a Bykski ram block with their own Bykski heatspreaders lol, unless you mean the heatspreaders have clearance issues due to the brand of RAM sticks?


----------



## rossi594

Audioboxer said:


> I would like to think there won't be issues with a Bykski ram block with their own Bykski heatspreaders lol, unless you mean the heatspreaders have clearance issues due to the brand of RAM sticks?


No it's just a bad design. The Bykski should be fine. The screws are counter sunk into the heatspreader. On the Alphacool they will push each other apart and make the tops not straigth so that the conductivity is bad.


----------



## mongoled

rossi594 said:


> No it's just a bad design. The Bykski should be fine. The screws are counter sunk into the heatspreader. On the Alphacool they will push each other apart and make the tops not straigth so that the conductivity is bad.


One of the reasons I got rid of the Alphacools along with other parts of poor workmanship ...


----------



## rossi594

mongoled said:


> One of the reasons I got rid of the Alphacools along with other parts of poor workmanship ...


I just bought the ek one new and sealed for 70$ bucks with 4 heatspreaders. I was not willing to go cheap or pay 130+.


----------



## rossi594

mongoled said:


> One of the reasons I got rid of the Alphacools along with other parts of poor workmanship ...


What was wrong with the Alphacool? I am thinking about getting their optane block, it's only 20$.


----------



## mongoled

rossi594 said:


> What was wrong with the Alphacool? I am thinking about getting their optane block, it's only 20$.


Start reading from here


----------



## Audioboxer

mongoled said:


> Start reading from here





> Pointless and its super hard to remove the heatsinks. High chance of ripping a memory chip off of the pcb and ruining your ram.




Good thing I bought RipJaws then which seem to have the worst heatsinks in existence.


----------



## rossi594

mongoled said:


> Start reading from here


Aquatuning is fairly reputable. I think it's just the Alphacool quality, everything they sell has been produced by a contract factory in China. He knew a replacement would be **** as wel =).

The block is an early model, the holes should be in the copper and only 20$. I think I will ordered. I can still send it back if I don't like it. The internal surface finish on the EKs is not great. It's good enough but not great. I would have prefered an acetal / pom top. But they stopped selling that version.


----------



## mongoled

rossi594 said:


> Aquatuning is fairly reputable. I think it's just the Alphacool quality, everything they sell has been produced by a contract factory in China. He knew a replacement would be **** as wel =).


Basically yes! The Aquatuning sales rep told me this direct in email


----------



## rossi594

Audioboxer said:


> Good thing I bought RipJaws then which seem to have the worst heatsinks in existence.


It's the thermal glue tape, not the heatspreaders. Just make sure you get it proper hot (75-80°C) and don't apply to much force.


----------



## Audioboxer

rossi594 said:


> It's the thermal glue tape, not the heatspreaders. Just make sure you get it proper hot (75-80°C) and don't apply to much force.


Yeah I've got my pipe bending heatgun ready to go






There are some people on YT using rulers and cards too, but I'd feel more comfortable with a little heat.


----------



## mongoled

Audioboxer said:


> Yeah I've got my pipe bending heatgun ready to go
> 
> 
> 
> 
> 
> 
> There are some people on YT using rulers and cards too, but I'd feel more comfortable with a little heat.


Also take care of the tiny ICs

I found out the hard way ...


----------



## Audioboxer

mongoled said:


> Also take care of the tiny ICs
> 
> I found out the hard way ...


Melting them? 

Definitely with these RipJaw heatsinks, half the bottom is exposed


----------



## mongoled

Audioboxer said:


> Melting them?
> 
> Definitely with these RipJaw heatsinks, half the bottom is exposed


No, when you leverage the heatspeader trying to remove it, you will understand when you get round to it

😂 😂


----------



## Audioboxer

mongoled said:


> No, when you leverage the heatspeader trying to remove it, you will understand when you get round to it
> 
> 😂 😂


Spend hundreds of £ on memory, destroy it removing the heatsinks


----------



## rossi594

I will put some masking tape and measure with a laser thermometer. Maybe I will use a hairdryer instead of the heatgun. Don't want to overheat them. I would not put force to them until the glue is fairly soft. Otherwise you maybe rip some ics off.


----------



## ManniX-ITA

Audioboxer said:


> I was just about to ask what thermal pads I should be using and what thickness lol. I'm presuming 0.5mm is the safe thickness? Wouldn't want the heatsinks not to be able to close.


Thickness depends on the heat-spreaders.
The Alphacool HS needs 0.5mm for DS and 1.0mm for SS.



rossi594 said:


> What was wrong with the Alphacool?


Some stuff as said by @mongoled has very poor workmanship... and I just remembered I have a couple of AIO to send them back in RMA!



rossi594 said:


> I referenced my calculations against the gddr6x power draw and pad benchmarks. (My results are inconclusive, I think the reason for the hot 3090 ics are not only their own power draw, but also the heat put into the pcb from the gpu).


The problem with the 3080/3090 ICs is more the hardness of the pad.

If you use decent ones it's perfectly fine but too stiff and the GPU will not make proper contact.
Thermal paste is not adequate as will probably not have a good contact for the RAM ICs.
You need very soft pads, right thickness for the block, to have good contact on both.

That's what I learned from reading the thread. Still have to do it for my 3090.


----------



## Audioboxer

Might seem like a daft question but given how few people do RAM watercooling would I be right to say the top of the heatspreaders would benefit from thermal paste before the block is screwed down? Seems to make sense to me to do that due to imperfections in the metals.


----------



## rossi594

Audioboxer said:


> Might seem like a daft question but given how few people do RAM watercooling would I be right to say the top of the heatspreaders would benefit from thermal paste before the block is screwed down? Seems to make sense to me to do that due to imperfections in the metals.


I thought it was common practise to put some. EK recommends it as well.

It's about filing gaps in the microstructure.

If you have single sided ICs make sure to put the ICs on the side that ends up directly touching the waterblock.


----------



## Audioboxer

rossi594 said:


> I thought it was common practise to put some. EK recommends it as well.
> 
> It's about filing gaps in the microstructure.
> 
> If you have single sided ICs make sure to put the ICs on the side that ends up directly touching the waterblock.


Yup, 100% makes sense, it's just one of those questions you ask whilst knowing the answer to because it's something you've never done before and want reassurance lol.


----------



## mongoled

Audioboxer said:


> Might seem like a daft question but given how few people do RAM watercooling would I be right to say the top of the heatspreaders would benefit from thermal paste before the block is screwed down? Seems to make sense to me to do that due to imperfections in the metals.


I used 1.5 mm Gelid Ultimate pad for that, 15 W/mK

😃

Regarding using thermal paste, I didn't want to do that as its messy and not sure how much "good contact" the block is going to make with both the dimms as you will have some imperfections in the mating due to the difficulty in assembling the two dimms heatspreaders so that they are exactly in line on both the horizontal and vertical plane. 

Besides Kryonaut has a thermal conductivity of 12,5 W/mk, that's lower than the Ultimate

😍


----------



## Luggage

mongoled said:


> I used 1.5 mm Gelid Ultimate pad for that, 15 W/mK
> 
> 😃
> 
> Regarding using thermal paste, I didn't want to do that as its messy and not sure how much "good contact" the block is going to make with both the dimms as you will have some imperfections in the mating due to the difficulty in assembling the two dimms heatspreaders so that they are exactly in line on both the horizontal and vertical plane.
> 
> Besides Kryonaut has a thermal conductivity of 12,5 W/mk, that's lower than the Ultimate
> 
> 😍


I would hope you don’t use a 1.5mm kryonaut spread


----------



## Audioboxer

mongoled said:


> I used 1.5 mm Gelid Ultimate pad for that, 15 W/mK
> 
> 😃
> 
> Regarding using thermal paste, I didn't want to do that as its messy and not sure how much "good contact" the block is going to make with both the dimms as you will have some imperfections in the mating due to the difficulty in assembling the two dimms heatspreaders so that they are exactly in line on both the horizontal and vertical plane.
> 
> Besides Kryonaut has a thermal conductivity of 12,5 W/mk, that's lower than the Ultimate
> 
> 😍


Ahhh, right, so use a pad on the top as well, good idea.

This will be getting "expensive" with pads 

I've got Gelid paste, might experiment before also buying 1.5mm pads. I redone my whole system with Gelid GC Extreme after running out of Kyronaut from all those damn tear downs trying to troubleshoot GPU/CPU. I think I prefer this paste, it was easier to spread and I honestly believe my CPU is seeing better results. GPU seems to be about the same.

It's the GPU I'm interested to see if another rad helps with for a few more degrees, my 2080Ti just seems a total heat monster. Fair enough it's running at 123% and overclocked to the max, but still


----------



## mongoled

Luggage said:


> I would hope you don’t use a 1.5mm kryonaut spread


I didn't understand but as you find it funny then 😂😂


----------



## MrHoof

Henry Owens said:


> How do you go about setting proct odt/rttpark and clkdrvstrn?


I did setup a failsafe timing set on 2T with a not to tight tRFC so I ruled out memory errors in TM5 when switching to 1T.
After that I tried combinations of diffrent RTT and drvstrn until i got rid of error 6 spam, you will get to a point were they stop or happen rare, at this point only make small changes to RTT/drvstr.
If you lower procODT little more VDIMM will be needed I had to increase it by 0.015v to get rid of the last few error 6.
ProcODT seemed to be the least important part to get past the 6 spam wall, anything from 30-43.6 did run for a few min before throwing a error in test 6. I sugget use sth between 32-36.9 for start.

As far as i understand higher divider is in most cases is better, less resistence means less heat. Not sure about NOM if off wouldnt be better.
For SR best working RTT on my setup are 7/3/6 20-20-20-24 procODT 28.2. 7/3/7 does not boot.
For DR I kept swapping around between NOM off/7/6; WR 1/2/3; PARK 2/3/4/5. Higher Park didnt boot. The one with the least error 6 were 7/2/4 7/2/5 7/3/3 7/3/2.
For DrvStr settings I tried any combination of Clk 30-40 AddrComnmand 20-24-30 CstODT 20-24-30 Cke 20-24-30 with the above RTTs.
I would suggest start with 40-20-24-30 those seem to work for alot of people and focus on RTT first and when u have only 1 or late error 6 left only then change procODT. If you lower procODT u maybe need add a little VDIMM and if u increase procODT u might be able to run little lower VDIMM.

Tried my best to explain it but its just ALOT trial and error .

edit: But I wouldnt have tried so hard if I didnt knew from my 2 SR set tests that both ran 1T without problems on my CPU/MB with lowest procODT, high RTT dividers and with lowest DrvStr. Its not guaranteed afterall prepare to invest alot of hours.


----------



## ManniX-ITA

mongoled said:


> Besides Kryonaut has a thermal conductivity of 12,5 W/mk, that's lower than the Ultimate


No it's not a good idea, always use a paste whenever you can 

The thickness of the thermal material is a primary factor for the heat flux.

This means that the heat flux for 0.1mm of thermal paste with 12,5 W/mK thermal conductivity for a 10c delta is:











While for 1.2mm (let's say it's 1.5mm compressed) of a thermal pad with 15 W/mK thermal conductivity:










Ten times energy less that can pass through!


----------



## mongoled

Audioboxer said:


> Ahhh, right, so use a pad on the top as well, good idea


😂😂 I initially read that as "you would be putting the pads on top of the Kyronaut 🤣🤣


----------



## mongoled

ManniX-ITA said:


> No it's not a good idea, always use a paste whenever you can
> 
> The thickness of the thermal material is a primary factor for the heat flux.
> 
> This means that the heat flux for 0.1mm of thermal paste with 12,5 W/mK thermal conductivity for a 10c delta is:
> 
> View attachment 2524808
> 
> 
> 
> While for 1.2mm (let's say it's 1.5mm compressed) of a thermal pad with 15 W/mK thermal conductivity:
> 
> View attachment 2524809
> 
> 
> Ten times energy less that can pass through!


Thanks for the ammendment, I knew I was missing something 😂😂😂

Though you need to assemble the dimms to perfection and hope you make good contact with the waterblock

@Luggage 
I got it now

🤩


----------



## ManniX-ITA

mongoled said:


> Thanks for the ammendment, I knew I was missing something 😂😂😂


I've learned quite a lot about thermals in the last year for my build 

I've another tip read in the 3090 thread that is applicable to RAM sticks.
Some people got excellent results spreading good thermal paste around the ICs.
So that the thermal pad in the spacing between the ICs instead of floating on void is connected to the PCB and ICs.
Got the VRAM temperatures some more degrees cooler with this trick, also helps reducing the PCB temperature.


----------



## Audioboxer

ManniX-ITA said:


> No it's not a good idea, always use a paste whenever you can
> 
> The thickness of the thermal material is a primary factor for the heat flux.
> 
> This means that the heat flux for 0.1mm of thermal paste with 12,5 W/mK thermal conductivity for a 10c delta is:
> 
> View attachment 2524808
> 
> 
> 
> While for 1.2mm (let's say it's 1.5mm compressed) of a thermal pad with 15 W/mK thermal conductivity:
> 
> View attachment 2524809
> 
> 
> Ten times energy less that can pass through!


I have no idea what any of this means so... I will just put paste over _everything_ 

So I've to melt my RAM sticks, accidentally rip off a chip taking off the heatsinks, then squeeze paste over everything before reassembling. Got it. Extra cool.

3800 flat 14 guaranteed.


----------



## MrHoof

Or just get lucky


----------



## Luggage

Audioboxer said:


> That _should_ still result in this
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> When a core crashes it results in a red error WHEA, instead of the yellow warnings which come from trying to run 1900+ WHEA.
> 
> If it's a hard reboot the WHEA-Logger might not pick it up in time. The 3 above for me were cores crashing during CoreCycler.












No WHEA since I thought I dialed in curve on the 22nd Aug. Koro crashes with core 4 on anything deeper than -15. I've been testing memory and benching y-cruncher, occt etc with core 4 at -30 (or -27, can't be sure lost original curve with bios) for three weeks with no WHEA or crashes until I ran Blender yesterday.


----------



## rossi594

Did anybody test the new gigabyte "memory stability" bios? Is anyone here running 2066 fclk with 4x8? (Couldn't find anyone in the spreadsheet).


----------



## sonixmon

rossi594 said:


> Did anybody test the new gigabyte "memory stability" bios? Is anyone here running 2066 fclk with 4x8? (Couldn't find anyone in the spreadsheet).


Notes from there site:

Improve memory compatibility
Big difference between compatibility and stability, but would be interesting if it helps someone's OC


----------



## rossi594

sonixmon said:


> Notes from there site:
> 
> Improve memory compatibility
> Big difference between compatibility and stability, but would be interesting if it helps someone's OC


Compatibility with lower cas and higher clock obv. =D


----------



## Audioboxer

rossi594 said:


> Did anybody test the new gigabyte "memory stability" bios? Is anyone here running 2066 fclk with 4x8? (Couldn't find anyone in the spreadsheet).


If it's based on the new AGESA it'll probably have the VDDG bug.


----------



## rossi594

Audioboxer said:


> If it's based on the new AGESA it'll probably have the VDDG bug.


You don't know Gigabyte they are always 3 Versions behind. This is still Patch B.


----------



## sonixmon

rossi594 said:


> You don't know Gigabyte they are always 3 Versions behind. This is still Patch B.


Maybe they are the smart ones (at least in this case).


----------



## umea

Audioboxer said:


> Spend hundreds of £ on memory, destroy it removing the heatsinks


I used a breadknife and no heat on my ripjaws heatsink. Since I'm aircooling though I'll be buying trident z neo for the better heatsinks. I'm looking at buying the 4000c14 kit as well, not sure if I want 16gb or 32gb though.. 

Do we know why it's much more common fir 5600x to have 'better' IMC? Or is it as simple as having more cores makes it more difficult for the CPU to handle high freq/low timing ram. Since I plan on building other PCs to sell (as I have 3 GPUs laying around), I might use the money I get back to build a 5600x rig for my side project and see what I can do with it both on SR and DR ..


----------



## ManniX-ITA

umea said:


> is it as simple as having more cores makes it more difficult for the CPU to handle high freq/low timing ram.


I'd say this!


----------



## mongoled

Audioboxer said:


> 3800 flat 14 guaranteed


No guarantee

😂😂


rossi594 said:


> Did anybody test the new gigabyte "memory stability" bios? Is anyone here running 2066 fclk with 4x8? (Couldn't find anyone in the spreadsheet).


Is this question just for Gigabyte users ??

Ive got a "stable" 4133/2067 profile but im not using it for 24/7 use because its not perfect ...


----------



## mongoled

Just an ammendment, im using 0.5 mm pads for the RAM waterblock not the 1.5 mm I previously stated


----------



## mongoled

mongoled said:


> Finally have a nailed down config for 4133/2067 flat 16s without any random idle reboots.
> 
> Now need to do a few reboots, retests, to see if it holds...
> 
> View attachment 2524559
> 
> 
> But before doing that I need to check out the new 1.2.0.4 agesa to see if vDDG CCD/IOD has a max limit of 1.0v on my setup as that is going to throw a huge spanner in the works for alot of us
> 
> 
> 
> Oh and im sure ive got APBDIS set to 1 and DF C-States control to disabled so unsure what with the 217,000 (and others) Ghz CPU boost frequency
> 
> 😂😂
> 
> ** EDIT **
> Ughhhh
> 
> same on my setup, I set
> 
> vSOC: 1.15v
> vDDG IOD: 1.10v
> vDDG CCD: 1.05v
> vDDP 0.9v
> 
> View attachment 2524560


Unfortunately did not survive a reboot,

going to play with the CH_A/CH_B channel on my 3800/1900 profile to see if it effects tRCDRD ...


----------



## Audioboxer

umea said:


> I used a breadknife and no heat on my ripjaws heatsink. Since I'm aircooling though I'll be buying trident z neo for the better heatsinks. I'm looking at buying the 4000c14 kit as well, not sure if I want 16gb or 32gb though..
> 
> Do we know why it's much more common fir 5600x to have 'better' IMC? Or is it as simple as having more cores makes it more difficult for the CPU to handle high freq/low timing ram. Since I plan on building other PCs to sell (as I have 3 GPUs laying around), I might use the money I get back to build a 5600x rig for my side project and see what I can do with it both on SR and DR ..


If you want to wait a few days I will let you know how I get on with my 4000C14 DR kit. Should be clear very quickly if it's my IMC or DR silicon I am having some struggles with.


----------



## rossi594

mongoled said:


> Unfortunately did not survive a reboot,
> 
> going to play with the CH_A/CH_B channel on my 3800/1900 profile to see if it effects tRCDRD ...


Are you running 4x8? And is it T1 pure? Or GDM on? (Just want to know whats currently possible).


----------



## mongoled

rossi594 said:


> Are you running 4x8? And is it T1 pure? Or GDM on? (Just want to know whats currently possible).


No 1T "pure"

32gb_4133-2067-16-16-16-16-32-48-288-2t


----------



## rossi594

mongoled said:


> No 1T "pure"
> 
> 32gb_4133-2067-16-16-16-16-32-48-288-2t


Not yet  you can do it bro


----------



## mongoled

rossi594 said:


> Not yet  you can do it bro


Not going to happen, one of my sticks is weak compared to the other three, its the weakest link

🤣🤣

Ive returned to looking for ways to get the weak stick stable with tRCDRD @14 @3800 mhz

Playing with CH_A/CH_B and VPP voltage ..


----------



## Audioboxer

mongoled said:


> Ive returned to looking for ways to get the weak stick stable with tRCDRD @14 @3800 mhz


And the circle is complete, back to the grind of 3800 flat 14.

What will it achieve? Basically no difference in benchmarks... BUT, it must be done. How can one sleep at night knowing it _might_ be possible to achieve 3800 flat 14?

I believe in you, with watercooling get that VDIMM up to 1.9v, flat 14 easy 

More seriously, has anyone ever achieved tCL13 at 3800?


----------



## mongoled

Audioboxer said:


> And the circle is complete, back to the grind of 3800 flat 14.
> 
> What will it achieve? Basically no difference in benchmarks... BUT, it must be done. How can one sleep at night knowing it _might_ be possible to achieve 3800 flat 14?
> 
> I believe in you, with watercooling get that VDIMM up to 1.9v, flat 14 easy
> 
> More seriously, has anyone ever achieved tCL13 at 3800?


Veii

 

Very early days, but may have stumbled on something here



As explained previously tRCDRD does not scale with vDIMM

** EDIT **
Argggghhh, error just popped up, but it almost got to 4 cycles, first time today to get that far !


----------



## Audioboxer

mongoled said:


> As explained previously tRCDRD does not scale with vDIMM


LIES!

Like RGB makes your PC go faster more VDIMM solves everything stability related 

Flat 14 on Micron E-die by running 2.1v! It works!


----------



## mongoled

Audioboxer said:


> LIES!
> 
> Like RGB makes your PC go faster more VDIMM solves everything stability related
> 
> Flat 14 on Micron E-die by running 2.1v! It works!


Careful, you going to make some n00b blow up the place

😂 😂


----------



## Audioboxer

mongoled said:


> Careful, you going to make some n00b blow up the place
> 
> 😂 😂


Looks at Reddit posts asking is 1.5~1.6v OK on a Ryzen processor to achieve a 4.3~4.4 all core manual "overclock" 🤔


----------



## mongoled

Audioboxer said:


> Looks at Reddit posts asking is 1.5~1.6v OK on a Ryzen processor to achieve a 4.3~4.4 all core manual "overclock" 🤔


There....I knew it .....you had been on reddit

😂 😂

Note: the "r" is lower case on purpose


----------



## Mach3.2

Audioboxer said:


> LIES!
> 
> Like RGB makes your PC go faster more VDIMM solves everything stability related
> 
> Flat 14 on Micron E-die by running 2.1v! It works!


Dude I blew up my Rev B sticks by pushing 2.5v VDIMM 🤕




mongoled said:


> There....I knew it .....you had been on reddit
> 
> 😂 😂
> 
> Note: the "r" is lower case on purpose


reddit can be special at times... 🙃


----------



## mongoled

Mach3.2 said:


> Dude I blew up my Rev B sticks by pushing 2.5v VDIMM 🤕


Video or it didnt happen

😂 😂


----------



## Mach3.2

mongoled said:


> Video or it didnt happen
> 
> 😂 😂












🤪


----------



## rossi594

mongoled said:


> Not going to happen, one of my sticks is weak compared to the other three, its the weakest link
> 
> 🤣🤣
> 
> Ive returned to looking for ways to get the weak stick stable with tRCDRD @14 @3800 mhz
> 
> Playing with CH_A/CH_B and VPP voltage ..


Are you sure it's not the board? That really starts to matter with 4 sticks at the limit.


----------



## mongoled

rossi594 said:


> Are you sure it's not the board? That really starts to matter with 4 sticks at the limit.


Sticks have been tested independently


----------



## rossi594

mongoled said:


> Sticks have been tested independently


I hope I get lucky and my 4 can do it.


----------



## Audioboxer

mongoled said:


> Sticks have been tested independently


That reminds me I really should test my 2x16 sticks one by one just to see if they can do it, though in a day or two I've got a new set to test anyway


----------



## cstkl1




----------



## mongoled

Me me me me me me me me me me me me me

😂 😂


----------



## umea

Audioboxer said:


> If you want to wait a few days I will let you know how I get on with my 4000C14 DR kit. Should be clear very quickly if it's my IMC or DR silicon I am having some struggles with.


Yeah I'm in no rush right now, I tested both of my sticks and neither can do tRCDRD 14 so it seems either I got a sad kit or a sad CPU, more likely the latter I think..


----------



## Audioboxer

umea said:


> Yeah I'm in no rush right now, I tested both of my sticks and neither can do tRCDRD 14 so it seems either I got a sad kit or a sad CPU, more likely the latter I think..


Well, I would hope a kit that is rated for 4000 tRCDRD 15 could achieve 3800 tRCDRD 14 but you never know with memory. If it's not rated for it you just can't guarantee it. I guess it's possible it still wants 15 at 3800 and just has the benefit of also being able to do 15 at 4000


----------



## RosaPanteren

Sorry for my ignorance on the matter...

Im new to Linpack X, and it seems Gflops have been greatly limited by low vsoc.

Going from 1.125 -> 1.15 -> 1.175 vsoc bumped Gflops from 250 -> 350 -> 412 running 30GB stresstest.

However running running only 10GB test resulted in 680 Gflops for vsoc @1.15v

Is it normal for Gflops to flux between different test sizes, or is something wrong?


----------



## sraney45

Hello, I am having issues with AIDA64 extreme cache and memory benchmark. 
Ryzen 9 5900x 
MSI b450 Tomahawk MAX (AGESA 1.2.0.2)
2070 SUPER Gigabyte Windforce
16x2 3600cl 14-15-15-35 @1.45v T-force Xtreme ARGB 
Corsair 850w PSU
x63 kraken 
2 120 PSW fans (nzxt)
H510i CASE.

Doesn't crash when Im playing games. Usually operating at ~1.32v Core Voltage and 4.7Ghz. Ram tightened to 14-14-14-28 @1.46 SoC 1.1

Wanted to bump frequency to 3800cl14. Wanted to get baseline memory/cache benchmarks for reference. This is when my problem started. AIDA64 goes black screen and PC cannot reboot. Must turn off A/C switch in back then the computer will restart. I changed CPU OC to default and tried to test just XMP 1. Works the first time and then if I try to test cache/memory again with AIDA64 it goes black again. Seems to only be able to complete the benchmark in AIDA64 reliably with no CPU OC and Ram default settings. Does AIDA64 not like my system? Does my board not have sufficient VRM to keep voltage stable during heavy load? Thinking of upgrading to B550 unify-x and maybe the superior VRAM will let me get my OC fix so I can go back to playing games. Any help is much appreciated, thanks!


----------



## MrHoof

Veii said:


> Increase SCL to 3,4,5 the point where you got the most bandwidth out on 1-5-5-1-7-7
> (Adapt tWRRD [x] = tRCD =|< than X * SCL)
> Then drop tRDRDSCL to the one you are stable (lower = better for chipselect)
> Also first drop both DD's to 2 and try to stabilize them ~ after testing SCL on 1-5-5-1-7-7
> At the end you can go with uneven SCL + 1-5-2-1-7-2
> But crucial is to focus on bandwidth here before mixing both, as it will get unstable alone by changing SD/DD's
> 
> * bad tWRRD or SCL will result in a loss of 4-5GB/s bandwidth
> Even when stability is held up


Got around to test this. DD seem to make no diffrence but SD do.

Current best
SCL SD/DD tRDWR/tWRRD result
2-2 6-6/4-4 7/3 57380MB read 55910MB copy 51.5 latency

6-6-4-4 to 7-7-5-5 = -300MB read -200MB, copy but keeping it like this as you said for now.
scl 2-2 to 3-3 = 0 change
scl 3-3 to 4-4 = -200MB read -200MB copy, back to 3-3
SD/DD 7-7-5-5 to 7-6-5-4 = 0 change
SD/DD 7-6-5-4 to 6-7-4-5 = back to good preformance multiple runs over 57.4/56GB and newest best latency of 51.4-5 avg
SD/DD 6-7-4-5 to 6-6-4-4 = 0 change
SD/DD 6-6-4-4 to 6-2-4-2 = 0 change
lower SD does not get past memory training

New
SCL SD/DD tRDWR/tWRRD result
3-3 6-7/4-5 7/3 57410MB read 56050MB copy 51.4 latency


----------



## domdtxdissar

RosaPanteren said:


> Sorry for my ignorance on the matter...
> 
> Im new to Linpack X, and it seems Gflops have been greatly limited by low vsoc.
> 
> Going from 1.125 -> 1.15 -> 1.175 vsoc bumped Gflops from 250 -> 350 -> 412 running 30GB stresstest.
> 
> However running running only 10GB test resulted in 680 Gflops for vsoc @1.15v
> 
> Is it normal for Gflops to flux between different test sizes, or is something wrong?


My numbers for my old memory setup you can use as a comparison:

5950x @ custom water+TechN block with latest CTR running.
SMT enabled for all runs
4x8GB (gskill 3600 cl16) running flat 14-14-14 timings running on T1 setup-time (no GDM)
Minimum required vdimm = 1.54v (maxtemp below 40degress even when gaming with a 3090)











Benchmark 3GB numbers with 6 cores

6 cores at 4.5ghz static OC = 266 Gflops
6 cores at PBO CO -30 = 281 Gflops
*6 cores maxed (static 4.85ghz) = 286 Gflops*
Benchmark 8GB extended numbers with 6 cores

6 cores at PBO CO -30 = 283 Gflops
*6 cores maxed (static 4.85ghz) = 287 Gflops*











Benchmark 3GB numbers with 16 cores

16 cores at 4.5ghz static OC = 641 Gflops
*16 cores maxed (static ~4750/4600mhz) = 654 Gflops*

Benchmark 8GB extended numbers with 16 cores

16 cores at 4.5ghz static OC = 668 Gflops
*16 cores maxed (static ~4750/4600mhz) = 680 Gflops*











Static OC @ 4675/4500mhz, 1.31v set = ~1.24 vcore get
Around 320watt usage (maxtemp = 93)

*Stresstest 10GB = ~700 Gflops*









Have numbers for my cpu at 8 and 12 corecount also if anyone are interested in those

If you are experiencing large run to run discrepancy, something is throttling.. most likely too high fclk.
(if i were to guesstimate, 80% of the ppl running above 1900/3800)


----------



## MrHoof

could you do a quick 16 thread run ? noone here seems to have 5800x to compare too.
edit: I guess make sense to be like 50% of 32thread I am at 344-343GFlops for 10gb.
edit2: i checkd HWinfo for coreclock and its running at 4.4-4.45ghz on avg. CO no auto OC.


----------



## domdtxdissar

MrHoof said:


> could you do a quick 16 thread run ? noone here seems to have 5800x to compare too.


8 cores PBO








Think i did some static OC numbers also, will see if i can find

_edit_
Cant find any old screens from 8 cores at static OC but can do a new run if u want.
(but then it would be with my new mem settings)


----------



## MrHoof

Nah dont need to can see already from those that yours would be higher anyway. Whats your avg CPU clockspeed avg over the run does it stay at max ?


----------



## domdtxdissar

MrHoof said:


> Nah dont need to can see already from those that yours would be higher anyway. Whats your avg CPU clockspeed avg over the run does it stay at max ?


Those screens are from 02.06.21 with my old 4x8gb memory timings.. Cant remember average cpu clockspeed for settings i never normally run.. Had disabled one CCD for that 8 core testing. (to make my 5950x behave like a better binned 5800x)
If you want real comparable numbers, testing have to be done on static clock, not PBO.


----------



## MrHoof

Well my PBO has really consistent results why would i need to test on static? Like in CB23 it will always run 4.7ghz as example.


----------



## SneakySloth

Is there anything obvious I can reduce here (apart from trfc, 270 works but needs 1.52v).


----------



## domdtxdissar

MrHoof said:


> Well my PBO has really consistent results why would i need to test on static?


If you want to compare numbers we both have to run at a static OC as my main (5950x) CCD is better binned then pretty much all 5800x out there -> it will bost higher with PBO and screw the results.
I can do a run at something like 8 cores at static 4500mhz or whatever your PBO is boosting to in this benchmark, to get more comparable numbers if you want

_edit_
8 cores at 4450 at static coming up.


----------



## MrHoof

domdtxdissar said:


> If you want to compare numbers we both have to run at a static OC as my main (5950x) CCD is better binned then pretty much all 5800x out there -> it will bost higher with PBO and screw the results.
> I can do a run at something like 8 cores at static 4500mhz if you want, like i said


Ah thats what u mean 44.5 would be nice, thats what it can hold atleast for 1 cylce on 10gb test and get 344gflops. My 5800x is one of the better ones if i compare my best CB23 result to hwbot 5800x resulst i am 20th on AIR cooling, you can see my setup few pages back.


----------



## domdtxdissar

MrHoof said:


> Ah thats what u mean 44.5 would be nice, thats what it can hold atleast for 1 cylce on 10gb test and get 344gflops. My 5800x is one of the better ones if i compare my best CB23 result to hwbot 5800x resulst i am 20th on AIR cooling, you can see my setup few pages back.



8 cores @ static 4450mhz
1150mv set vcore -> 1125mv get vcore
Maxed 25 cycle stable memory timings for this setup at 1545 vdimm

355 GFlops score

The most important thing to check for is that numbers not going down run after run because of throttling soc / running too high fclk / auto(whea)correction
(its normal first run is alittle slower then rest)









(had one other linpack running while talking screen to show temps/power etc)


----------



## MrHoof

SneakySloth said:


> Is there anything obvious I can reduce here (apart from trfc, 270 works but needs 1.52v).
> 
> View attachment 2524898


Could try 15-8-15-15-27-42-294


@domdtxdissar you also get the 30399mb write bandwith limit with 1 CCX disabled right? Btw thats one impressive 5950x


----------



## SneakySloth

MrHoof said:


> Could try 15-8-15-15-27-42-294
> 
> 
> @domdtxdissar you also get the 30399mb write bandwith limit with 1 CCX disabled right? Btw thats one impressive 5950x


Thank you. I'm currently running Karhu until 10000% for the above settings (at 5600 right now). I'll definitely try reducing the primaries and trc,trfc further to those.


----------



## RosaPanteren

domdtxdissar said:


> My numbers for my old memory setup you can use as a comparison:
> 
> 5950x @ custom water+TechN block with latest CTR running.
> SMT enabled for all runs
> 4x8GB (gskill 3600 cl16) running flat 14-14-14 timings running on T1 setup-time (no GDM)
> Minimum required vdimm = 1.54v (maxtemp below 40degress even when gaming with a 3090)
> 
> View attachment 2524887
> 
> 
> 
> Benchmark 3GB numbers with 6 cores
> 
> 6 cores at 4.5ghz static OC = 266 Gflops
> 6 cores at PBO CO -30 = 281 Gflops
> *6 cores maxed (static 4.85ghz) = 286 Gflops*
> Benchmark 8GB extended numbers with 6 cores
> 
> 6 cores at PBO CO -30 = 283 Gflops
> *6 cores maxed (static 4.85ghz) = 287 Gflops*
> 
> View attachment 2524888
> 
> 
> 
> Benchmark 3GB numbers with 16 cores
> 
> 16 cores at 4.5ghz static OC = 641 Gflops
> *16 cores maxed (static ~4750/4600mhz) = 654 Gflops*
> 
> Benchmark 8GB extended numbers with 16 cores
> 
> 16 cores at 4.5ghz static OC = 668 Gflops
> *16 cores maxed (static ~4750/4600mhz) = 680 Gflops*
> 
> View attachment 2524889
> 
> 
> 
> Static OC @ 4675/4500mhz, 1.31v set = ~1.24 vcore get
> Around 320watt usage (maxtemp = 93)
> 
> *Stresstest 10GB = ~700 Gflops*
> View attachment 2524885
> 
> 
> Have numbers for my cpu at 8 and 12 corecount also if anyone are interested in those
> 
> If you are experiencing large run to run discrepancy, something is throttling.. most likely too high fclk.
> (if i were to guesstimate, 80% of the ppl running above 1900/3800)


Thx!

What Im curios about is if it's normal to see reduction in GFlops between 30GB (problem size 62 497) and 10GB (problem size 35 000)

30GB (problem size 62 497) - 355 GFlops
10GB (problem size 35 000) - 680 GFlops

GFlops in same run is more or less consistent

And I haven't been able to stabilize 1T setup time yet.......freaking 3 weeks and still not able to get stable cl15 or cl14 @3800 🤬

Linpack scores with same timings for 1T GDM and 2T:










....and 1T GDM compared to 2T give me +500Mb write and 100Mb read....this is consistent on different timings as well. I can run the sticks with trp 13, tras 23, trc 36 and trfc 238, but then need to bump vdimm a bit, that resulted in Aida mem latency of 51.7ns on the 5800x I got......

Whats your Aida mem latency without CRT magic?


----------



## MrHoof

SneakySloth said:


> Thank you. I'm currently running Karhu until 10000% for the above settings (at 5600 right now). I'll definitely try reducing the primaries and trc,trfc further to those.


If that passes you can also try 15-8-14/15-14-26-40-280 but will maybe need a little bump in voltage for this.


----------



## domdtxdissar

MrHoof said:


> Could try 15-8-15-15-27-42-294
> 
> 
> @domdtxdissar you also get the 30399mb write bandwith limit with 1 CCX disabled right? Btw thats one impressive 5950x


Pretty sure i would hit it if i sat here running Aida a few times.. 








Back to 16 cores..


----------



## MrHoof

domdtxdissar said:


> Pretty sure i would hit it if i sat here running Aida a few times..
> View attachment 2524917
> 
> Back to 16 cores..


Thank you very much, that means i can still gain 10gflops somehow i guess. Gotta look to finetune vddg/soc or maybe even edc I guess.
edit: btw try tCWL 14 and see if you can lower tRDRW while leaving tWRRD on auto and check if u get better results.


----------



## domdtxdissar

RosaPanteren said:


> Thx!
> 
> What Im curios about is if it's normal to see reduction in GFlops between 30GB (problem size 62 497) and 10GB (problem size 35 000)
> 
> 30GB (problem size 62 497) - 355 GFlops
> 10GB (problem size 35 000) - 680 GFlops
> 
> GFlops in same run is more or less consistent
> 
> And I haven't been able to stabilize 1T setup time yet.......freaking 3 weeks and still not able to get stable cl15 or cl14 @3800 🤬
> 
> Linpack scores with same timings for 1T GDM and 2T:
> View attachment 2524904
> 
> 
> 
> ....and 1T GDM compared to 2T give me +500Mb write and 100Mb read....this is consistent on different timings as well. I can run the sticks with trp 13, tras 23, trc 36 and trfc 238, but then need to bump vdimm a bit, that resulted in Aida mem latency of 51.7ns on the 5800x I got......
> 
> Whats your Aida mem latency without CRT magic?
> 
> View attachment 2524913


Same behavior here..
30 gigs = 380 GFlops
10 gigs = 690 GFlops

Started a 3rd Linpack Xtreme run to show all runtime-stats in a screenshot..










> Whats your Aida mem latency without CRT magic?


~53.8ns @ 1900/3800 speeds with both CCD's enabled, in regular windows (not safemode)

No more testing, bed time now


----------



## LockAlive

Can someone post safe 3800 CL16 settings for 16GB (2x8GB) 4400 CL19 Steel Vipers? I just dont have time to test stability all days.


----------



## SneakySloth

LockAlive said:


> Can someone post safe 3800 CL16 settings for 16GB (2x8GB) 4400 CL19 Steel Vipers? I just dont have time to test stability all days.


Straight 16, GDM disabled 1T, 1.5v should work just fine.

16-16-16-16-34-50-300

You should still at least do 1 hour of OCCT memory testing.

Naturally with proper testing this can be significantly improved.


----------



## Thanh Nguyen

Anyone here has timing for dual rank ram which passes tm5 and has 50ms-52ms latency?


----------



## SneakySloth

Currently at this. Seems to be stable so far. I'm going to run TM5 overnight to make sure that it is.










I might try and get TRCDWR down to 8 and TRP to 14 but I'm not sure if I want to spend the time doing that. Also how much performance I can get out of lowering those timings

TRDWR does not go below 10, pc doesn't boot. Same goes for TWRRD at 2 (1 doesn't work). I could try and reduce TCWL but not sure if its really worth it. Only thing that I'm disappointed in is the TRFC, was hoping I could get it down to 252 but that requires 1.52/53 VDIMM. I'm more comfortable keeping things at 1.5


----------



## ManniX-ITA

Thanh Nguyen said:


> Anyone here has timing for dual rank ram which passes tm5 and has 50ms-52ms latency?


1 or 2 CCDs? At which FCLK?
FCLK 2000 and 1CCD could be feasible.

I'm at 53.2ns with 2 CCDs and FCLK 2000:


----------



## umea

ManniX-ITA said:


> 1 or 2 CCDs? At which FCLK?
> FCLK 2000 and 1CCD could be feasible.
> 
> I'm at 53.2ns with 2 CCDs and FCLK 2000:
> 
> View attachment 2524953


You are extremely lucky to hit over 1900 fclk with a 2ccd chip.. Anything over 1900 results in whea errors or no post :'( and my IMC can't even handle flat 14 @ 3800, so I'm **** outta luck sadly :'(


----------



## ManniX-ITA

umea said:


> You are extremely lucky to hit over 1900 fclk with a 2ccd chip.. Anything over 1900 results in whea errors or no post :'( and my IMC can't even handle flat 14 @ 3800, so I'm **** outta luck sadly :'(


More or less the same situation 
But I was able to stabilize FCLK 2000.
Not always possible and you need to tolerate very high voltages.
Once i was pretty sure it was stable, I've silenced the WHEA errors.


----------



## Steve_

Hi
I'm running a 5950x for relatively heavy workloads. I'd previously had quite a good memory overclock running 2x16GB.
For some of my workloads, I'd really like to go up to 4x16GB.
Does anyone have any tips for different settings / timings when trying this? So far, I'm *way *down on what I used to be able to achieve with 2x16.


----------



## umea

ManniX-ITA said:


> More or less the same situation
> But I was able to stabilize FCLK 2000.
> Not always possible and you need to tolerate very high voltages.
> Once i was pretty sure it was stable, I've silenced the WHEA errors.


what voltages are you running?


----------



## Thanh Nguyen

ManniX-ITA said:


> 1 or 2 CCDs? At which FCLK?
> FCLK 2000 and 1CCD could be feasible.
> 
> I'm at 53.2ns with 2 CCDs and FCLK 2000:
> 
> View attachment 2524953


Zen timming please.


----------



## ManniX-ITA

umea said:


> what voltages are you running?


These are all the relevant settings.

To avoid performance regression on heavy loads (Linpack Extreme and Monero miner), I had to enable CLKREQ# in the AMD PBS menu.
Not sure but I recall at 1933/1966 it was not needed.



Spoiler: Voltages


----------



## Audioboxer

ManniX-ITA said:


> These are all the relevant settings.
> 
> To avoid performance regression on heavy loads (Linpack Extreme and Monero miner), I had to enable CLKREQ# in the AMD PBS menu.
> Not sure but I recall at 1933/1966 it was not needed.
> 
> 
> 
> Spoiler: Voltages
> 
> 
> 
> 
> View attachment 2524963
> 
> 
> View attachment 2524964
> 
> 
> View attachment 2524965
> 
> 
> View attachment 2524966
> 
> 
> View attachment 2524967
> 
> 
> View attachment 2524968
> 
> 
> View attachment 2524969


Does a VSOC that high not eat away at the CPU performance?


----------



## ManniX-ITA

Audioboxer said:


> Does a VSOC that high not eat away at the CPU performance?


It does a bit but still much less than the performance uplift from the higher FCLK


----------



## Audioboxer

ManniX-ITA said:


> It does a bit but still much less than the performance uplift from the higher FCLK


Interesting, after I've discovered what my 4000 kit can do at 3800 I might have a look at 2000 for the hell of it. Out of interest with a 4000C14 kit how come you're running at tCL16?


----------



## ManniX-ITA

Audioboxer said:


> Interesting, after I've discovered what my 4000 kit can do at 3800 I might have a look at 2000 for the hell of it. Out of interest with a 4000C14 kit how come you're running at tCL16?


The XMP CL14-15 profile works fine but it's terrible. 
It gets immediately unstable Improving the secondary and tertiary timings.
Probably something could be improved with better thermals but I still have the original Ripjaws heatsink on.
Just setting CL14 doesn't help, latency gets worse than this CL16 profile.
I'd probably need more than 1.55V but it's just impossible now.


----------



## Audioboxer

ManniX-ITA said:


> The XMP CL14-15 profile works fine but it's terrible.
> It gets immediately unstable Improving the secondary and tertiary timings.
> Probably something could be improved with better thermals but I still have the original Ripjaws heatsink on.
> Just setting CL14 doesn't help, latency gets worse than this CL16 profile.
> I'd probably need more than 1.55V but it's just impossible now.


Ah yeah, forgot from the codename you have the RipJaws heatsinks. It's a bit of a joke GSKILL even sell a 1.55v RipJaw bin, the heatsinks are not good enough at 1.45v let alone 1.55v. At least the other bins of this ram come with Trident Z RGB/Neo or Royal heatsinks which are all proper full-size heatsinks.

Still I'd put it out there at 1.55v most people will need a fan if they plan to do any tightening over XMP profiles. I guess XMP might run at 1.53~1.54v if there is a little bit of overhead to maintain guaranteed stability at XMP.

I bought the RipJaw model because I plan on watercooling if it's a good overclocker and it's cheaper than the RGB bins. One of my sets is getting sold, just need to find out which one 










The pricing on NewEgg 

Thankfully I got mine cheaper than £422. £340, which is still a ludicrous price for RAM   Paying £500 for some RGB and shiny heatsinks


----------



## Thanh Nguyen

ManniX-ITA said:


> These are all the relevant settings.
> 
> To avoid performance regression on heavy loads (Linpack Extreme and Monero miner), I had to enable CLKREQ# in the AMD PBS menu.
> Not sure but I recall at 1933/1966 it was not needed.
> 
> 
> 
> Spoiler: Voltages
> 
> 
> 
> 
> View attachment 2524963
> 
> 
> View attachment 2524964
> 
> 
> View attachment 2524965
> 
> 
> View attachment 2524966
> 
> 
> View attachment 2524967
> 
> 
> View attachment 2524968
> 
> 
> View attachment 2524969


I got performance penalty when run 4000/2000. What can I do? Asus dark hero mobo.


----------



## ManniX-ITA

Audioboxer said:


> Still I'd put it out there at 1.55v most people will need a fan if they plan to do any tightening over XMP profiles. I guess XMP might run at 1.53~1.54v if there is a little bit of overhead to maintain guaranteed stability at XMP.


Well with the profile I'm running they peak 56c with TM5 in less than 40 minutes but despite that error free for 2h:30m  good binning means also better resilience to temperature stress



Audioboxer said:


> I bought the RipJaw model because I plan on watercooling if it's a good overclocker and it's cheaper than the RGB bins.


Me as well and the LEDs, which are totally useless if you ran them with a waterblock, are stealing power and producing heat.

I've tested a Royal Elite kit and it's nothing more than any Trident or Ripjaws.

If you want to go water, pick the Ripjaws. Not having the LEDs is only good.

This one is ridiculously expensive but at least better than any other I tried.
The 4000CL16 1.45V could only run tRCDRD at 17 while this one can go down to 16.
No luck with flat 14 at 3800 but I may need better heatsinks so I'll try it again.
Also this one actually boots at 4000CL14 without setup timings; crashes during TM5.
The 4000CL16 could not even POST.


----------



## Audioboxer

ManniX-ITA said:


> Well with the profile I'm running they peak 56c with TM5 in less than 40 minutes but despite that error free for 2h:30m  good binning means also better resilience to temperature stress
> 
> 
> 
> Me as well and the LEDs, which are totally useless if you ran them with a waterblock, are stealing power and producing heat.
> 
> I've tested a Royal Elite kit and it's nothing more than any Trident or Ripjaws.
> 
> If you want to go water, pick the Ripjaws. Not having the LEDs is only good.
> 
> This one is ridiculously expensive but at least better than any other I tried.
> The 4000CL16 1.45V could only run tRCDRD at 17 while this one can go down to 16.
> No luck with flat 14 at 3800 but I may need better heatsinks so I'll try it again.
> Also this one actually boots at 4000CL14 without setup timings; crashes during TM5.
> The 4000CL16 could not even POST.


Someone can correct me if I'm wrong but along with tRFC I believe tRCDRD can also be temp sensitive. Even if a kit is binned to be more temp resilient 56 degrees is still quite high for B-die IMO.

I start seeing TM5 errors with my tRFC at like 45~46 degrees on my tightest profile at 1.5v. Admittedly tRFC is 245 on it. Considering I have a 2 DIMM board these RipJaws heatsinks are just trash. The memory sticks being right next to each other just means things get toasty. Can't wait to get over to watercooling. I don't think RGB adds too much heat, maybe a degree or two, but even that can be the difference between stable and not stable and at least the RGB ram has good heatsinks. Just gotta turn RGB off 

My additional 360mm radiator arrived, so just waiting on my new memory and the block to arrive from China. Next week I'll likely do the drain/tear down and rebuild. Need some time to check this new bin and make sure it can be pushed further than my 3600C14.

*edit* - There is a 4000C16 bin that is 16-16-16-16 and is 1.4v rated. I've seen a few people mention that is potentially the "best bin" but I wonder if there is a bigger risk with tRCDRD on it considering it may well be the case even at 1.55v many of those bins fail to drop to tRCDRD 15 like the bin we have. Guess this is all part of the silicon lottery, do you pay more for a potentially higher chance at the tRCDRD wall or do you pay less and cross your fingers? If it was "easy" GSKILL would already be selling a 3800 14-14-14-14 bin as it would be their best seller with 5xxx chips more readily hitting 1900 FCLK. They don't mass produce and sell such a bin, their 3800C14 is 14-16-16-16 so that should tell us something 

tldr; Everyone hates tRCDRD


----------



## ManniX-ITA

Audioboxer said:


> I don't think RGB adds too much heat, maybe a degree or two


More than the heat I'm concerned with the power which is stolen from the ICs.



Audioboxer said:


> I start seeing TM5 errors with my tRFC at like 45~46 degrees on my tightest profile at 1.5v. Admittedly tRFC is 245 on it.


Yes I can keep them working at that temperature cause I don't stress too much tRCDRD, tRFC and tRRD/tWTR.
I guess when on water I'll be able to do better, we'll have to see.



Audioboxer said:


> There is a 4000C16 bin that is 16-16-16-16 and is 1.4v rated.


Indeed, could be the best bin. Unfortunately I'm now stuck with this kit, otherwise... 









G.Skill RipJaws V schwarz DIMM Kit 32GB, DDR4-4000, CL16-16-16-36 ab € 238,90 (2023) | Preisvergleich Geizhals Deutschland


✔ Preisvergleich für G.Skill RipJaws V schwarz DIMM Kit 32GB, DDR4-4000, CL16-16-16-36 ✔ Produktinfo ⇒ Typ: DDR4 DIMM 288-Pin • Takt: 4000MHz • Module: 2x 16GB • JEDEC: PC4-32000U… ✔ Speicher ✔ Testberichte ✔ Günstig kaufen




geizhals.de





The price is also quite good.
Which makes me wonder if they are really the best bin.
But on the paper...



Audioboxer said:


> Guess this is all part of the silicon lottery, do you pay more for a potentially higher chance at the tRCDRD wall or do you pay less and cross your fingers?


I have purchased 4-5 kits from the cheap 3200CL14 to the Royal Elite 4266C17 and except minimalistic differences they all had the same behavior and limits.
This one was the only one better. Not much but still better.
G.Skill has "normalized" the production to a single quality layer seems.
I was able to purchase the exact same 3200CL14 used by others and could not even remotely replicate the same timings.
Tested it up to 1.9V and it was crap compared to the original kit, same P/N, they sold years ago.


----------



## Audioboxer

ManniX-ITA said:


> More than the heat I'm concerned with the power which is stolen from the ICs.
> 
> 
> 
> Yes I can keep them working at that temperature cause I don't stress too much tRCDRD, tRFC and tRRD/tWTR.
> I guess when on water I'll be able to do better, we'll have to see.
> 
> 
> 
> Indeed, could be the best bin. Unfortunately I'm now stuck with this kit, otherwise...
> 
> 
> 
> 
> 
> 
> 
> 
> 
> G.Skill RipJaws V schwarz DIMM Kit 32GB, DDR4-4000, CL16-16-16-36 ab € 238,90 (2023) | Preisvergleich Geizhals Deutschland
> 
> 
> ✔ Preisvergleich für G.Skill RipJaws V schwarz DIMM Kit 32GB, DDR4-4000, CL16-16-16-36 ✔ Produktinfo ⇒ Typ: DDR4 DIMM 288-Pin • Takt: 4000MHz • Module: 2x 16GB • JEDEC: PC4-32000U… ✔ Speicher ✔ Testberichte ✔ Günstig kaufen
> 
> 
> 
> 
> geizhals.de
> 
> 
> 
> 
> 
> The price is also quite good.
> Which makes me wonder if they are really the best bin.
> But on the paper...
> 
> 
> 
> I have purchased 4-5 kits from the cheap 3200CL14 to the Royal Elite 4266C17 and except minimalistic differences they all had the same behavior and limits.
> This one was the only one better. Not much but still better.
> G.Skill has "normalized" the production to a single quality layer seems.
> I was able to purchase the exact same 3200CL14 used by others and could not even remotely replicate the same timings.
> Tested it up to 1.9V and it was crap compared to the original kit, same P/N, they sold years ago.


Yeah they're definitely running a bit of a _racket_ with all the bins and wild price fluctuations to presumably prey on the OCers desperate for the best benchmarks 

Such is life. At least GSKILL properly name and state their timings, unlike Corsair and Patriot who seem to be up to some nonsense right now with either quietly changing bins but not model number or making it hard to actually know what the timings are on their official site.

The 4000 16-16-16-16 set has to be the best on voltage alone, 1.4v is a great bin for a 4000 set. As I said I just wonder if the risk with them is trying to push lower tRCDRD at 3800 or even 4000 and what voltage it would require (keeping in mind tRCDRD doesn't really scale with voltage...). 1.55v is quite a high voltage bin, but at least it guarantees the RAM will run at 1.55v XMP and the timings are pretty tight. In theory you'd hope dropping down from 4000 to 3800 would give you a decent chance at tRCDRD 14.

I originally went the other way and thought this 3600 14-14-14-14 bin at 1.45v might manage 3800 14-14-14-14 with just a voltage boost, but it's proving to be tricky. So here is hoping binning higher on speed and dropping it down might work...

But I also think with a 1 CCD processor and better IMC this 3600 bin might even be fine for 3800 14-14-14-14 and possibly 1T pure. I've had a little bit of success myself pushing 3800 GDM Enabled 1T 14-14-14-14, but I don't want to run GDM. I'll know soon enough if it's my 2 CCD processor and IMC that is my real bottleneck.


----------



## ManniX-ITA

Audioboxer said:


> The 4000 16-16-16-16 set has to be the best on voltage alone, 1.4v is a great bin for a 4000 set. As I said I just wonder if the risk with them is trying to push lower tRCDRD at 3800 or even 4000 and what voltage it would require (keeping in mind tRCDRD doesn't really scale with voltage...)


I would definitely try this kit, I was you 
Guess you can buy them from someone with a 30 days return window so...


----------



## Audioboxer

ManniX-ITA said:


> I would definitely try this kit, I was you
> Guess you can buy them from someone with a 30 days return window so...


Nah, my adventures with RAM are over after this kit lmao. If it performs similarly to my 3600 14-14-14-14 kit I'll know it's likely my CPU/IMC that is more of a limiting factor.

Voltage won't bother me too much when watercooled so it really just be a silicon gamble, again, at 4000 16-16-16-16. This 4000 14-15-15-15 bin is the most expensive GSKILL do so if it can't meet what I'm trying to hit then as I said I'd think it's likely more CPU/IMC. Which wouldn't surprise me as I believe a 5950x is the worst processor, on average, for memory overclocking.

But it's great for everything else! Trade-offs!


----------



## SneakySloth

TRCDWR at 8 is definitely stable while TRP at 14 wasn't, I think I need to increase my ram voltage to get that down. I also run a GPU stress test during the memory test so that I can generate the maximum amount of heat in my system, essentially to emulate a gaming environment.

If anyone is looking for timings for 4x8 Patriot Viper 4400, then the following might work for you. My older kit I feel was definitely better binned than the new one.


----------



## Audioboxer

SneakySloth said:


> TRCDWR at 8 is definitely stable while TRP at 14 wasn't, I think I need to increase my ram voltage to get that down. I also run a GPU stress test during the memory test so that I can generate the maximum amount of heat in my system, essentially to emulate a gaming environment.
> 
> If anyone is looking for timings for 4x8 Patriot Viper 4400, then the following might work for you. My older kit I feel was definitely better binned than the new one.
> 
> 
> View attachment 2524980


At 1.5v that tRFC should be able to come down depending on your temps.










I run a tRFC of 247 at 1.5v. I had it at 245, but that was the absolute bottom of stability at 1.5v and it was super temp sensitive. Just going up to 247 gave me a little more headroom plus a nice rounded 130ns 

Fix your tRFC2/4 regardless, it can help a tiny bit with stability. tRFC 2 = tRFC / 1.346. tRFC 4 = tRFC 2 / 1.625.


----------



## SneakySloth

Audioboxer said:


> At 1.5v that tRFC should be able to come down depending on your temps.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I run a tRFC of 247 at 1.5v. I had it at 245, but that was the absolute bottom of stability at 1.5v and it was super temp sensitive. Just going up to 247 gave me a little more headroom plus a nice rounded 130ns
> 
> Fix your tRFC2/4 regardless, it can help a tiny bit with stability. tRFC 2 = tRFC / 1.346. tRFC 4 = tRFC 2 / 1.625.


I have a 80mm fan on top of the Ram so that helps manage the temperature so that shouldn't be a huge issue. Its mostly voltage that is holding me back. I'll try TRFC at 252 and 273 and see if that works at 1.5v. I kind of don't want to increase the voltage much over 1.5.

I will definitely fix the TRFC2/4 timings, I kinda forgot I had them all set the same still (thanks for pointing it out).

I think 4x8GB A2 sticks are harder to run though. I was able to do 3800CL14 with lower primaries and secondaries with 2x8GB.


----------



## mongoled

Audioboxer said:


> Nah, my adventures with RAM are over after this kit lmao. If it performs similarly to my 3600 14-14-14-14 kit I'll know it's likely my CPU/IMC that is more of a limiting factor.
> 
> Voltage won't bother me too much when watercooled so it really just be a silicon gamble, again, at 4000 16-16-16-16. This 4000 14-15-15-15 bin is the most expensive GSKILL do so if it can't meet what I'm trying to hit then as I said I'd think it's likely more CPU/IMC. Which wouldn't surprise me as I believe a 5950x is the worst processor, on average, for memory overclocking.
> 
> But it's great for everything else! Trade-offs!


Just to be clear, its not just a matter of whacking up the voltages!

Your going to have to also play with the Rtt values etc.

Just giving you a heads up so you dont have false expectation


----------



## LockAlive

My Vipers are able to easily achieve 3600 14-14-14-14 v1.45 (dont remember but i think v1.40 was ok) but it takes them much more than 1.40v to achieve 4000mhz 16-16-16, thats why i think this 4000mhz 16-16-16 1.4v is excellent bin and its cheap currently


----------



## umea

Audioboxer said:


> Ah yeah, forgot from the codename you have the RipJaws heatsinks. It's a bit of a joke GSKILL even sell a 1.55v RipJaw bin, the heatsinks are not good enough at 1.45v let alone 1.55v. At least the other bins of this ram come with Trident Z RGB/Neo or Royal heatsinks which are all proper full-size heatsinks.
> 
> Still I'd put it out there at 1.55v most people will need a fan if they plan to do any tightening over XMP profiles. I guess XMP might run at 1.53~1.54v if there is a little bit of overhead to maintain guaranteed stability at XMP.
> 
> I bought the RipJaw model because I plan on watercooling if it's a good overclocker and it's cheaper than the RGB bins. One of my sets is getting sold, just need to find out which one
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> The pricing on NewEgg
> 
> Thankfully I got mine cheaper than £422. £340, which is still a ludicrous price for RAM   Paying £500 for some RGB and shiny heatsinks


Sadly the cheapest I can find this kit is 490USD... No idea where else to find it. Either way, might end up buying it anyways later on depending on your tests.

Anyways, this passed, going to see what else I can tighten before trying to push to 1T with setup timings (as obviously pure 1T will not post).









Frankly it's kinda annoying to be limited by my chip's IMC. have tried just about every RTT / vermeer voltage setting I can think of really.. Nothing stops immediate spam of 6s on TM5.


----------



## MrHoof

Audioboxer said:


> At 1.5v that tRFC should be able to come down depending on your temps.


My old SR kit 2x8gb didnt even boot below 250 tRFC 260 was min that was stable. I dont think every kit can do really thight tRFC as I was also running 1.52VDIMM.


----------



## LockAlive

4000mhz 16-16-16 seems to be not available in US, thats why price is high there. In Germany its 286 euro G.Skill Ripjaws V - DDR4 - Kit - 32 GB: 2 x 16 GB - DIMM 288-PIN - 4000 MHz / PC4-32000 · [ PC-KING ]


----------



## Audioboxer

mongoled said:


> Just to be clear, its not just a matter of whacking up the voltages!
> 
> Your going to have to also play with the Rtt values etc.
> 
> Just giving you a heads up so you dont have false expectation


Of course! That's why I've gambled on a 4000 tRCDRD 15 set to see if it can achieve 3800 tRCDRD 14. As I said I went the other way first, 3600 tRCDRD 14 and thought I could "upclock" it, now I'm trying to "downclock" a 4000 set 



LockAlive said:


> My Vipers are able to easily achieve 3600 14-14-14-14 v1.45 (dont remember but i think v1.40 was ok) but it takes them much more than 1.40v to achieve 4000mhz 16-16-16, thats why i think this 4000mhz 16-16-16 1.4v is excellent bin and its cheap currently


Yeah it's definitely a great bin, my main goal right now is running at 3800 which is why I've taken a gamble with a set binned with a lower tRCDRD than 16.



LockAlive said:


> 4000mhz 16-16-16 seems to be not available in US, thats why price is high there. In Germany its 286 euro G.Skill Ripjaws V - DDR4 - Kit - 32 GB: 2 x 16 GB - DIMM 288-PIN - 4000 MHz / PC4-32000 · [ PC-KING ]


It's available on NewEgg for America F4-4000C16D-32 | Newegg.com

$265 for RipJaws set!


----------



## umea

I paid 320 or so off newegg for my 4266 17 18 18 38 kit. 
Also those settings I posted are still 1.5v and seem stable, even with 245/182/112 (128.9ns). 1T will require more vltg but might see how far I can push trfc as well.


----------



## LockAlive

umea said:


> I paid 320 or so off newegg for my 4266 17 18 18 38 kit.
> Also those settings I posted are still 1.5v and seem stable, even with 245/182/112 (128.9ns). 1T will require more vltg but might see how far I can push trfc as well.


At what voltage can you do 4000 16-16-16 on your 4266 17-18-18 set?


----------



## Audioboxer

Speaking of results/voltages, I can barely find anyone with the 4000 14-15-15-15 set on the whole of the internet. One or two people in this topic and that is it. I guess I shouldn't be surprised given this bin dropped this year, it costs a stupid amount and stock seems to be come and go.

Was trying to see if I could find out how anyone got on with a 1 CCD processor. For those buying SR as well this bin is probably just stupid to even entertain. DR is where it gets a bit more interesting.


----------



## LockAlive

Audioboxer said:


> Speaking of results/voltages, I can barely find anyone with the 4000 14-15-15-15 set on the whole of the internet. One or two people in this topic and that is it. I guess I shouldn't be surprised given this bin dropped this year, it costs a stupid amount and stock seems to be come and go.
> 
> Was trying to see if I could find out how anyone got on with a 1 CCD processor. For those buying SR as well this bin is probably just stupid to even entertain. DR is where it gets a bit more interesting.


The price for that is just stupid, its twice the price of 4000 16-16-16 in all shops around me


----------



## umea

LockAlive said:


> At what voltage can you do 4000 16-16-16 on your 4266 17-18-18 set?


I'll try it right now, but I can't run 2000fclk. Will let you know. Are you looking for 1T or 2T voltages? I can run 4000 16 16 36 2T with the rest on auto (just for simplicity sake) at 1.51v (maybe 1.5v).


----------



## umea

Audioboxer said:


> Speaking of results/voltages, I can barely find anyone with the 4000 14-15-15-15 set on the whole of the internet. One or two people in this topic and that is it. I guess I shouldn't be surprised given this bin dropped this year, it costs a stupid amount and stock seems to be come and go.
> 
> Was trying to see if I could find out how anyone got on with a 1 CCD processor. For those buying SR as well this bin is probably just stupid to even entertain. DR is where it gets a bit more interesting.


The 4000 14 15 15 35 SR kit on a 5600x good chip would probably destroy the rankings  though with DR i bet it can do some pretty crazy **** too. us 2ccd processor plebs will forever be hindered by the **** latency IMCs :')


----------



## Owterspace

I would be impressed seeing 4 sticks at 2K 1:1.


----------



## LockAlive

umea said:


> I'll try it right now, but I can't run 2000fclk. Will let you know. Are you looking for 1T or 2T voltages? I can run 4000 16 16 36 2T with the rest on auto (just for simplicity sake) at 1.51v (maybe 1.5v).


Classic 1T GDM On


----------



## MrHoof

letting that run for a bit 1.4V on 3600 CL-14-15-15-35 1.45V kit. Only did Set XMP timings, rest bios is default besides vddg/vddp.
edit: i guess 33mins are enough for those lose timings. I would say 4000 CL16 bin is probably about close to this bin.
that would mean your 3600-14-14-14 bin is better then 4000 CL16 @Audioboxer or they miss binned my kit.


----------



## Steve_

So seems like it's possible to get 4x16GB sticks working OK but you do have to 'sneak up' on it some what.
These are 1T GDM on, I'm afraid though...









For a bloaty Win10 install, I'm quite happy with the latency.
But I'm about 1000MB/s down on memory read/write/copy on my best 2x16GB setting.
I've found it very difficult to push some of the 2ndry/tertiary timings down but have to admit that I'm not that familiar with the rules for how each of them relate to each other.

Zen timings is:









If anyone's got any advice on how to tweak this further, I'd be most appreciative.


----------



## LockAlive

Anyone here has F4-4000C14D-16GVK set?


----------



## Audioboxer

LockAlive said:


> The price for that is just stupid, its twice the price of 4000 16-16-16 in all shops around me


Yeah, it really is a silly price, hence me crossing my fingers GSKILL aren't totally milking it and they know this is the best bin they put out.

For DR at a price on offer I'd say it could be worth a gamble (I haven't paid "RRP" for example), but if I was running 2x8 there is no way I'd buy this set. The other set they released this year at the same time, the 3600 14-14-14-14 is probably better value for SR if you want one of these "premium" bins. The Patriot SR 2x8s also seem to be really good value for overclocking.


----------



## MrHoof

LockAlive said:


> Anyone here has F4-4000C14D-16GVK set?


Not GVK but on Page 598* u can see some pictures. The 1.55v kit seems to have a slightly diffrent PCB then 3600/3800 kits. Would be nice to see a pic of a 4000 c16 stick but can not find one.

My kit still running 4000 cl16 1.4v 20 min so far. Going for 30min.

edit:* fixed page number
edit2: just posting it here and paint edited the to point out the diffrence i mean. not mine kit belongs to @domdtxdissar








added "resistor?" and might have more layers, 
2nd pic 3800-cl14-16-16


----------



## Audioboxer

MrHoof said:


> Not GVK but on Page 588 u can see some pictures. The 1.55v kit seems to have a slightly diffrent PCB then 3600/3800 kits. Would be nice to see a pic of a 4000 c16 stick but can not find one.
> 
> My kit still running 4000 cl16 1.4v 20 min so far. Going for 30min.


You sure, my page 588 doesn't seem to have pictures? The last PCB discussion I remember was us trying to identify my 3600 14-14-14-14 2x16 kit. Maybe both these kits which were released at the same time have a slightly different PCB?

*edit* - Ah, yeah forgot dom has this 4000 kit. Word is the trident z PCBs might be different than RipJaws (10 layer vs 8 layer), we'll know when mine arrive. Think I'll be the first RipJaw 4000 14-15-15-15 kit in this topic, at least recent pages.

Good thing is if I'm keeping this RAM I'll be taking my heatsinks off so will get proper pictures of whole PCB.


----------



## umea

LockAlive said:


> Classic 1T GDM On


works with 1.51v, would need higher with tighter timings though probably, gave me error 15 after 5 cycles but these settings are NOT properly done, just threw it together


----------



## LockAlive

I will soon have 4000 16-16-16 set to test so i can post some PCB pics, but do you maybe know if GVK/GTZN/GTZR versions have different/better pcbs?


----------



## Audioboxer

LockAlive said:


> I will soon have 4000 16-16-16 set to test so i can post some PCB pics, but do you maybe know if GVK/GTZN/GTZR versions have different/better pcbs?


If you are air cooling the Trident Z/Neo/RGB/Royal heatsinks are simply better, and the RGB can be turned off. RipJaw heatsinks are just not good enough, but it's not the end of the world if you have a 4 DIMM board and are OK maybe putting a fan on them if you want to push 1.5v+.

I'm buying RipJaws because my RAM will be watercooled once I've settled on what set I want. No point paying more.

PCBs will probably be the same on these higher end bins, but it might depend if you are going DR or SR and then I have seen commentary before about 8 layer vs 10 layer PCBs. I have no idea what difference that makes though, nor do I know if it's possibly something to do with the RGB and that having to be powered by the PCB.


----------



## LockAlive

Audioboxer said:


> If you are air cooling the Trident Z/Neo/RGB/Royal heatsinks are simply better, and the RGB can be turned off. RipJaw heatsinks are just not good enough, but it's not the end of the world if you have a 4 DIMM board and are OK maybe putting a fan on them if you want to push 1.5v+.
> 
> I'm buying RipJaws because my RAM will be watercooled once I've settled on what set I want. No point paying more.


You mean 4 dimms easier to cool than 2 dimms dual rank?


----------



## MrHoof

I am actuly gonna test now if turning off the led makes a diffrence in temps and if u can lower voltage. I am at the absolut lowest stable VDIMM right now gonna lower it by .01 and see what happens. Gonna report back in 30 mins.
edit: Nvm this is invalid forgot I increased scl yesterday by 1 wich can also make the a diffrence... will do it the other way around find new lowest VDIMM and turn them back on.
edit2: Nvm again maybe not so invalid -.01v error after 15 mins wich is is about the same as with led on. Gonna run 20 cycles to confirm scl 3 stable first .
edit3: On stable voltage 1.54 so far 40mins gonna do the full run on weekend. Temps are actuly 1-2°C cooler.


----------



## umea

LockAlive said:


> You mean 4 dimms easier to cool than 2 dimms dual rank?


Cooling on a 4dimm board will be easier due to them being spaced out more so less heat so close together, but 2dimm boards are generally better for ram OC


----------



## duarte36

hello . i have the f4-4000C14D-32GTES , 16GBx2 DR . windows boot and work at 1/1 on auto, i get whea error 20 only playing games , but without bsod , tired from playing with voltages and timings , they are working @ 3800 cl14 1/1 . for sure is IF , cause i have 4x8GB ripjaws 3200 cl14 that worked for years @ 4000 cl16 1.42v , and even those gave me whea errors. i think i stay like that for now, but i can take some pictures if anyone is interested.
Good luck and alot of patiente to all 'overclockers' here 

ps. Dark hero with 5900x


----------



## MrHoof

I am not the one who can help you with 3800mhz+ i just dont like errors in my windows event viewer . But no pic needed if u can just confirm it has that extra resistor i pointed out then its probably 99% chance its same.


----------



## umea

duarte36 said:


> hello . i have the f4-4000C14D-32GTES , 16GBx2 DR . windows boot and work at 1/1 on auto, i get whea error 20 only playing games , but without bsod , tired from playing with voltages and timings , they are working @ 3800 cl14 1/1 . for sure is IF , cause i have 4x8GB ripjaws 3200 cl14 that worked for years @ 4000 cl16 1.42v , and even those gave me whea errors. i think i stay like that for now, but i can take some pictures if anyone is interested.
> Good luck and alot of patiente to all 'overclockers' here
> 
> ps. Dark hero with 5900x


5900x and 5950x are a lot less likely to be whea-free and stable over 1900fclk than the 5800x or 5600x for example. Your best bet is to try to push timings as low as possible on 3800/1900. Here's what I'm running right now, working on tightening as much as I can before moving to 1T, although I am unsure of the latency difference between 2T and 1T 55 setup timing.. anyone have the comparison pics again?
Also, I'm pretty sure it's a lot easier to get 1T pure on 5600x/5800x than 5900x/5950x as well, even with DR


----------



## duarte36

MrHoof said:


> I am not the one who can help you with 3800mhz+ i just dont like errors in my windows event viewer . But no pic needed if u can just confirm it has that extra resistor i pointed out then its probably 99% chance its same.


----------



## MrHoof

Wth it does not. Is that rated 1.55v? so far i thought it must be cause of that.
edit: It is rated 1.55v ok now I am confused.


----------



## duarte36

MrHoof said:


> Wth it does not. Is that reted 1.55v so far i thought it must be cause of that? It is rated 1.55v ok now I am confused.


the only thing i can tell is that 'someone' from gskill told me that the best bin is GTES , it's more expensive , but just where it's true or not ....


----------



## Audioboxer

LockAlive said:


> You mean 4 dimms easier to cool than 2 dimms dual rank?


The Trident Z/Royal heatsinks cool better as they cover all the PCB, RipJaws are short at the sides and don't full cover memory chips.

4 DIMM will be easier to cool as well if you're 2x16 due to spacing. 2 RAM sticks right next to each other will heat each other up 



MrHoof said:


> Wth it does not. Is that rated 1.55v? so far i thought it must be cause of that.
> edit: It is rated 1.55v ok now I am confused.


Well, that's a Trident Z and Royal Set both different. My RipJaws should be here in a day or two and I'll see if it has that extra resistor.


----------



## duarte36

Audioboxer said:


> The Trident Z/Royal heatsinks cool better as they cover all the PCB, RipJaws are short at the sides and don't full cover memory chips.
> 
> 4 DIMM will be easier to cool as well if you're 2x16 due to spacing. 2 RAM sticks right next to each other will heat each other up
> 
> 
> 
> Well, that's a Trident Z and Royal Set both different. My RipJaws should be here in a day or two and I'll see if it has that extra resistor.


you gonna have 2 extra resistors ^^ just kiding  but careful , because it's possible also that you can get DR or SR ... they have that also...


----------



## Audioboxer

duarte36 said:


> you gonna have 2 extra resistors ^^ just kiding


In theory I'd expect the RipJaws to have the bargain basement binning of the lot that just squeezes out 4000 14-15-15-15 lol, but who knows!

I was going to take a guess and say maybe the resistor is something to do with RGB, but the Royal set has RGB so it rules out that. At least our sample size will grow with a RipJaw bin to look at. I'll be removing my heatsinks as well, so will get a good picture of the whole PCB.


----------



## umea

too bad they don't have a non fugly heatsink outside of the basic trident rgb/neo, even then, would just prefer a solid silver with logo or something rather than the god awful looking upper royal series


----------



## Audioboxer

umea said:


> too bad they don't have a non fugly heatsink outside of the basic trident rgb/neo, even then, would just prefer a solid silver with logo or something rather than the god awful looking upper royal series


The silver are quite nice, gold is terrible lol.


----------



## umea

wish someone made 3rd party heatsinks that i could slap on that don't look god awful


----------



## duarte36

Audioboxer said:


> The silver are quite nice, gold is terrible lol.


 have you read last posted, because i edited him. i know also that those kits exists in DR and SR .... like SU said .... just good luck ... ^^


----------



## Audioboxer

duarte36 said:


> have you read last posted, because i edited him. i know also that those kits exists in DR and SR .... like SU said .... just good luck ... ^^


Ahh, I didn't know that. I will have pictures here as soon as they arrive 😁 Fingers crossed!

I do have a question for anyone, how does SR work on a 2x16GB PCB? I haven't seen anyone in this topic post about having a 2x16GB SR kit. Seems quite rare.


----------



## duarte36

Audioboxer said:


> Ahh, I didn't know that. I will have pictures here as soon as they arrive 😁 Fingers crossed!
> 
> I do have a question for anyone, how does SR work on a 2x16GB PCB? I haven't seen anyone in this topic post about having a 2x16GB SR kit. Seems quite rare.


good question , but the answer from GSKILL is that they have both in production, so we can have one or other.... like i said to the guy , i buy a porsche , he arrives in 2 days , but who knows if he comes with a motor porsche or a motor bmw ... question of luck ??
That is already one of the reasons , why brands don't put in label if they are DR or SR . Bdie , edie .. etc...


----------



## MrHoof

Nah dont think there are 16gb SR B die dimms atleast not that i know. Only ones I heared of are Crucial Micron kits.



Audioboxer said:


> Ahh, I didn't know that. I will have pictures here as soon as they arrive 😁 Fingers crossed!
> 
> I do have a question for anyone, how does SR work on a 2x16GB PCB? I haven't seen anyone in this topic post about having a 2x16GB SR kit. Seems quite rare.


SR is single sided memory module and DR is both side populated. For 16GB single rank you need bigger memory chips.


----------



## duarte36

MrHoof said:


> Nah dont think there are 16gb SR B die dimms atleast not that i know. Only ones I heared of are Crucial Micron kits.


but why GSKILL told me that when i purchased the kit i could had one or other? they are producing both at the moment, maybe not B die either...

just simple as that, just send un e-mail to them and ask if the f4-4000cl14 are DR or SR.


----------



## MrHoof

duarte36 said:


> but why GSKILL told me that when i purchased the kit i could had one or other? they are producing both at the moment, maybe not B die either...
> 
> just simple as that, just send un e-mail to them and ask if the f4-4000cl14 are DR or SR.


Ye but there is nothing else besides B die that can do 4000cl14 so this is maybe miss information or mistake and he was talking about 4x8gb 4000cl14 wich is a thing too but would also count as dual rank.

edit: technically its single rank dimms but u have both channels populated wich makes it pefrom the same.


----------



## duarte36

it's hard , but i have also the crucial 4000 cl18 1.35v , they are SR . i know, they are cl18 but also 1.35v , who knows they found a way with 1.55 to SR? that's why i talk, but , where the truth start or end , i don't know at the moment.
like you said and well, you are talking dual channel , and not dual rank. 
i'm not a pro, but the question is, maybe the Gskill guy is less pro then me ... loool


----------



## MrHoof

not dual channel, but rather 2x dual channel 8x4 32GB SR wich perfrom the same as 1x dual channel 16x2 32GB DR.


----------



## duarte36

MrHoof said:


> not dual channel, but rather 2x dual channel single rank wich perfrom the same as 1x dual channel 32GB DR.


i understand, but the answer was ' we are producing both, DR and SR' he don't talked 2 or 4 sticks , or dual channel or what else. , i just want to make easy to understand my position. i'm not fighting, or telling that I'm wright or wrong... far from that. i'm just selling the fish at the same price i bought .


----------



## duarte36

just to finish. i'm not even sure if they are b-die.
just take ahead .


----------



## LockAlive

duarte36 said:


> just to finish. i'm not even sure if they are b-die.
> just take ahead .


Its very b-die


----------



## sonixmon

ManniX-ITA said:


> 1 or 2 CCDs? At which FCLK?
> FCLK 2000 and 1CCD could be feasible.
> 
> I'm at 53.2ns with 2 CCDs and FCLK 2000:
> 
> View attachment 2524953


Got a nice 5900x I will trade you for! 



Steve_ said:


> So seems like it's possible to get 4x16GB sticks working OK but you do have to 'sneak up' on it some what.
> These are 1T GDM on, I'm afraid though...
> View attachment 2525012
> 
> 
> For a bloaty Win10 install, I'm quite happy with the latency.
> But I'm about 1000MB/s down on memory read/write/copy on my best 2x16GB setting.
> I've found it very difficult to push some of the 2ndry/tertiary timings down but have to admit that I'm not that familiar with the rules for how each of them relate to each other.
> 
> Zen timings is:
> View attachment 2525013
> 
> 
> If anyone's got any advice on how to tweak this further, I'd be most appreciative.


Do you really need 64GB? 



duarte36 said:


> hello . i have the f4-4000C14D-32GTES , 16GBx2 DR . windows boot and work at 1/1 on auto, i get whea error 20 only playing games , but without bsod , tired from playing with voltages and timings , they are working @ 3800 cl14 1/1 . for sure is IF , cause i have 4x8GB ripjaws 3200 cl14 that worked for years @ 4000 cl16 1.42v , and even those gave me whea errors. i think i stay like that for now, but i can take some pictures if anyone is interested.
> Good luck and alot of patiente to all 'overclockers' here
> 
> ps. Dark hero with 5900x


Always test fclk seperate from ram, then OC ram to best fclk.


----------



## ManniX-ITA

Audioboxer said:


> Think I'll be the first RipJaw 4000 14-15-15-15 kit in this topic, at least recent pages.


Mine is the Ripjaws as well


----------



## LockAlive

I compared quickly my Steel Vipers 4400 CL19 to couple different "good" Gskill bins:

3600 14-14-14 1.45v - my Vipers can do that with 1.42v and tight subtimings

3800 14-16-16 1.50v - my Vipers can do that with 1.51v and tight subtimings

4000 16-16-16 1.40v - my Vipers can do that with 1.39v and tight subtimings

4000 14-15-15 1.55v - no chances i can do that, so many errors

So yeah seems like 4000 14-15-15 1.55v is amazing bin, thats why its so expensive.


----------



## duarte36

sonixmon said:


> Got a nice 5900x I will trade you for!
> 
> 
> 
> Do you really need 64GB?
> 
> 
> Always test fclk seperate from ram, then OC ram to best fclk.


thank you . gonna give it a try  i did 1 year ago +/- just don't remember results, new memory new nvme, etc .. need to start from the beginning. .


----------



## LockAlive

duarte36 said:


> thank you . gonna give it a try


Check how much voltage you need to run 3800 14-16-16


----------



## duarte36

LockAlive said:


> Check how much voltage you need to run 3800 14-16-16


my problem, is that i made 3 big surgerys, i think because anesthesia i got alot of memory problems. me not the pc ahahahah.  now i'm ok . , and gonna f.... the pc memory ahaha joking
but i started following you again , and i'm gonna give it a shoot.


----------



## duarte36

only a question. supposing that fclk can do 2000 , he must do it with cl14 / cl16 for example, or it's possible that he does with cl16 but not cl14 ?


----------



## Owterspace

My Ro


LockAlive said:


> So yeah seems like 4000 14-15-15 1.55v is amazing bin, thats why its so expensive.


My 3200C14 Royals (in gold  ) can do it.


----------



## umea

Well when I want to spend 550USD on RAM I'll buy the silver royal kit and see what it can do, though I know right now I'm limited by IMC so I might wait to see what Zen3D+ has to offer in terms of IMC or wait until next gen to incorporate it into my main rig. I plan on building a second rig though so that'll be fun to mess with


----------



## Sleepycat

If you want to know how high your current kit can go, just limit your FCLK to 1800 or 1866. Then set your DRAM to however high you want to test it. Don't bother with Aida64 as we know latency will be high, but do run TM5 and other memory testing to test for stability. Then you know how good your kit is.


----------



## ManniX-ITA

LockAlive said:


> 4000 14-15-15 1.55v - no chances i can do that, so many errors


Did you try same exact timings?


----------



## Taraquin

Helped at fellow 5600X-friend the other day and can share my experience with Samsung D-die. Bullzoid has 2 videos of them where he say they are similar to rev E. 

4000/2000 with no wheas was easy, running about same voltages as me on B550 Tomahawk with agesa 1.2.0.3B. 1.12v soc, 1.04 iod, 0.92 ccd, 0.88 vddp

As for the ram it is a cheap 2x8 3200 16-18-18 rgb kit. 

Ended up after some basic stabilitytesting with:
18-21-21-17-40, 66 rc, 5/7/16 rrds-faw, 16/8 wr/rtp, 18 cwl, 620 trfc, 2/10 rdwr/wrrd, 4/12 wtr, 4 scl, gdm on, 1.4V.

Slightly lower rc and trfc might work, but the others were at minimum, we tried 1.45V but did not help. 

Compared 2 stock fps (4000 at 18-22-22-44 and rest on auto) in Cyberpunk 1080low with dlss ultra perf went from 150 to 170fps avg, dram calc test went from 164 to 123 sec. 

All in all the Samsung D-die seems like a bad binned Micron rev E. It struggles with all primaries, rc and rfc is bad, trrd/faw okay, rtp okay, wr bad, scls okay. Best I can say about them is that they are very cheap and can clock really high.


----------



## Taraquin

LockAlive said:


> I compared quickly my Steel Vipers 4400 CL19 to couple different "good" Gskill bins:
> 
> 3600 14-14-14 1.45v - my Vipers can do that with 1.42v and tight subtimings
> 
> 3800 14-16-16 1.50v - my Vipers can do that with 1.51v and tight subtimings
> 
> 4000 16-16-16 1.40v - my Vipers can do that with 1.39v and tight subtimings
> 
> 4000 14-15-15 1.55v - no chances i can do that, so many errors
> 
> So yeah seems like 4000 14-15-15 1.55v is amazing bin, thats why its so expensive.


God, I wish I had your kit, my binning is terrible. Is this with GDM, 2T or 1T? Got the same as you and at 4000 flat 16 with gdm and tight subs lowest I can do is 1.44V (actual 1.45-1.46V due to Gigabyte fluctuating some).

I got 4000 flat 15 2T almost stable at 1.55V, but get some errors in TM5. With 4000 flat 15 2T you might be able to get 1.5V or sligthly higher vol stable.


----------



## Taraquin

Steve_ said:


> So seems like it's possible to get 4x16GB sticks working OK but you do have to 'sneak up' on it some what.
> These are 1T GDM on, I'm afraid though...
> View attachment 2525012
> 
> 
> For a bloaty Win10 install, I'm quite happy with the latency.
> But I'm about 1000MB/s down on memory read/write/copy on my best 2x16GB setting.
> I've found it very difficult to push some of the 2ndry/tertiary timings down but have to admit that I'm not that familiar with the rules for how each of them relate to each other.
> 
> Zen timings is:
> View attachment 2525013
> 
> 
> If anyone's got any advice on how to tweak this further, I'd be most appreciative.


Try tRC 41 or 43, try trrdl 6, twtrs 4, twtrl 12, tRCF 246(if rc is 41) or 258(if rc is 43), tWR 12, trtp 6, twrrd 3. What volt are you running? If your are at 1.5V+ tRFC 246(41) might work, if you are below 1.5V I would settle for 258(43).


----------



## frantatech

duarte36 said:


> good question , but the answer from GSKILL is that they have both in production, so we can have one or other.... like i said to the guy , i buy a porsche , he arrives in 2 days , but who knows if he comes with a motor porsche or a motor bmw ... question of luck ??
> That is already one of the reasons , why brands don't put in label if they are DR or SR . Bdie , edie .. etc...


No. 8GB Samsung B-die module is always single rank, 16GB Samsung B-die module is always dual rank. And that's exactly how the answer was meant. Yes, they are doing both SR and DR modules. But whether it is DR or SR is given by the capacity of the module.


----------



## duarte36

frantatech said:


> No. 8GB Samsung B-die module is always single rank, 16GB Samsung B-die module is always dual rank. And that's exactly how the answer was meant. Yes, they are doing both SR and DR modules. But whether it is DR or SR is given by the capacity of the module.


maybe a misunderstand between me and 'gskill' . cause i only buy 2x16gb now, it makes maybe 4/5 years i got the 4x8gb 3200 cl14, ripjaws that are amazing, but working in an intel 8700k @ 4000 cl16 , 1.42v .
i asked for the kit 2x16GB . lets forget this.
but thank you for the information in any case.


----------



## Owterspace

umea said:


> Well when I want to spend 550USD on RAM I'll buy the silver royal kit and see what it can do


Like 246 Canadian bucks..


----------



## umea

Owterspace said:


> Like 246 Canadian bucks..


32gb 4000 14 15 15 35 is not 246, the 16gb kit is around 300, where are you seeing this?


----------



## Owterspace

umea said:


> 32gb 4000 14 15 15 35 is not 246, the 16gb kit is around 300, where are you seeing this?


Sorry, I was talking about my 3200C14 Royals. They do 4000 14-15-15-35 1.55 no problem.


----------



## Audioboxer

Ran OCCT out of boredom, first time I've checked it out for memory










Only got the 1 hour timelimit with the free version, not sure how it compares to TM5 or y-cruncher, but I guess running another stability testing app on memory is never a bad thing!

Now hurry up and deliver my new set of RAM Amazon


----------



## umea

Weirdly enough I get worse latency with 1T and 56 setup time than I do with 2T no setup time, I consistently get 53.6-7 with 2T but am around 54.0 on 1T 56. Can anyone else with DR give it a shot and see what their results are like? Only thing I can see is somehow the 56 setup being unstable, have yet to do a long 25 cycle test on it.
Running 2CCD manual OC, 4850/4725 @ 1.36v. Might mess with PBO solely for AIDA64 latency circlejerking to see if I can push out higher boost clock

BTW: pretty sure that SMT on lowers latency on aida64 for anyone who happens to turn it off, but just be aware for general use (if you care) that it raises average interrupt to process latency and DPC latency by a lot



Spoiler: SMT off

























Spoiler: SMT on























ill do some more concrete testing with 1T setup times and GDM on vs 2T tomorrow or something


----------



## Audioboxer

umea said:


> Weirdly enough I get worse latency with 1T and 56 setup time than I do with 2T no setup time, I consistently get 53.6-7 with 2T but am around 54.0 on 1T 56. Can anyone else with DR give it a shot and see what their results are like? Only thing I can see is somehow the 56 setup being unstable, have yet to do a long 25 cycle test on it.
> Running 2CCD manual OC, 4850/4725 @ 1.36v. Might mess with PBO solely for AIDA64 latency circlejerking to see if I can push out higher boost clock
> 
> BTW: pretty sure that SMT on lowers latency on aida64 for anyone who happens to turn it off, but just be aware for general use (if you care) that it raises average interrupt to process latency and DPC latency by a lot
> 
> 
> 
> Spoiler: SMT off
> 
> 
> 
> 
> View attachment 2525060
> 
> View attachment 2525062
> 
> 
> 
> 
> 
> 
> Spoiler: SMT on
> 
> 
> 
> 
> View attachment 2525061
> 
> View attachment 2525063
> 
> 
> 
> 
> ill do some more concrete testing with 1T setup times and GDM on vs 2T tomorrow or something


IIRC 1T/56 brought improvements for me, I'd need to double check mind you. I got my latency down to 53.8.


----------



## Audioboxer

@umea

1T/56










2T










Latency not changing at all. This is the first time I've seen read go above 60,000, but read/write wildly fluctuates each time it's ran.

Above is










I guess if I keep it at 2T I can probably step back a bit with the DrvStrs. My very basic understanding of 1T/56 is it's more like 1.75T or something lol.

The only thing I don't like about 2T at tCL15 is it forces my tPHYRDL to 28 on one stick. So, 28/26. Would need to go to tCL14 to get it back to 26 at 2T


----------



## umea

The nice part about 2T is that it doesn't need any extra voltage, the settings I'm showing I'm running at 1.5v and it's stable.


----------



## Audioboxer

umea said:


> The nice part about 2T is that it doesn't need any extra voltage, the settings I'm showing I'm running at 1.5v and it's stable.


I don't think 1T/56 requires any more voltage for me? I'm at 1.5v mainly because of tRFC. I guess if I loosened up the tRFC I might find 2T can run at a lower voltage.

Out of interest if you run tCL15 does your kit jump to tPHYRDL 28 on one stick at 3800?


----------



## umea

Audioboxer said:


> I don't think 1T/56 requires any more voltage for me? I'm at 1.5v mainly because of tRFC. I guess if I loosened up the tRFC I might find 2T can run at a lower voltage.
> 
> Out of interest if you run tCL15 does your kit jump to tPHYRDL 28 on one stick at 3800?


nope, shows the exact same on both of dimms for meand maybe im misremembering but i thought that 1t needed more voltage, but maybe that's just with pure 1T. when i get a 5600x ill see if i can get 1T pure running so i can make proper comparison photos


















next step is to try to push to get below 53ns on aida but i think i'll have to mess with PBO and hope to push 5ghz single core to do that, as my current stable settings are already very tight


----------



## Audioboxer

umea said:


> nope, shows the exact same on both of dimms for meand maybe im misremembering but i thought that 1t needed more voltage, but maybe that's just with pure 1T. when i get a 5600x ill see if i can get 1T pure running so i can make proper comparison photos
> 
> 
> View attachment 2525066
> 
> View attachment 2525067
> 
> next step is to try to push to get below 53ns on aida but i think i'll have to mess with PBO and hope to push 5ghz single core to do that, as my current stable settings are already very tight


Should have clarified, tCL15 with 2T.

Although you might have just uploaded the same image by accident.


----------



## umea

Audioboxer said:


> Should have clarified, tCL15 with 2T.
> 
> Although you might have just uploaded the same image by accident.


oh woopsies ill try in a second, also i just uploaded both dimms to show they're the same lol


----------



## umea

nope, they're the same on 2T 3800 C15 as well for me


----------



## Audioboxer

umea said:


> nope, they're the same on 2T 3800 C15 as well for me
> View attachment 2525071
> 
> View attachment 2525070
> 
> View attachment 2525069


Interesting, I hope to find out if its something to do with my sticks when my 4000 rated set arrive or if it's the IMC.

I do notice you're running a 5900x which is obviously 12 core versus the 16 core on 5950x. All signs always point to the 5950x being the worst for memory overclocking/stability


----------



## umea

Audioboxer said:


> Interesting, I hope to find out if its something to do with my sticks when my 4000 rated set arrive or if it's the IMC.
> 
> I do notice you're running a 5900x which is obviously 12 core versus the 16 core on 5950x. All signs always point to the 5950x being the worst for memory overclocking/stability


id our thinking is correct then yeah I have a slight advantage in that front for sure, though between the two i would guess it just comes down to how good the silicon is on an individual chip. i still need to go through the sheet to find what the lowest latency on 5900x/5950x dual rank is


----------



## Audioboxer

umea said:


> id our thinking is correct then yeah I have a slight advantage in that front for sure, though between the two i would guess it just comes down to how good the silicon is on an individual chip. i still need to go through the sheet to find what the lowest latency on 5900x/5950x dual rank is


What I can't understand is why 2T runs at 28/26 but 1T will run at 26/26. On paper, makes no sense, considering 1T, even if it is with Setups, should be more strain on the memory/IMC.

tCL14 behaviour I guess I can understand more, it's 26/26 at 2T but 28/26 at 1T for me. It's tCL15 that is reversed, 26/26 at 1T but 28/26 at 2T  I've seen some other people get similar behaviour on a 5950x with DR/3800 so I'm not alone, just a case of trying to figure out what is causing it, memory, mobo, CPU or a combination. With a B550 Unify X, I'd rule out mobo. Can't really get many better boards for memory OCing. So as I said interested to see what results I get with this 4000 kit.


----------



## ManniX-ITA

umea said:


> Can anyone else with DR give it a shot and see what their results are like?


For me was 0.2-0.4ns better and between 100-300 MB/s more.
You may need to test different setup timings; test from 55 to 62.
Also test 56-0-0 and 56-56-56.

This morning while working I've experimented a bit with CL14-15-15-35, the XMP profile.
It's like a "surviving" profile that works thin razor. Quite a marketing gimmick 
It doesn't work at T2. Anything lower in GDM will trigger immediately errors.
As I said before it's terrible; fluctuating latency, 56-57ns, low bandwidth, crashing PBO boost.

Now I'm testing a CL15-15-15-27-43 profile.
Slightly better than the CL16 profile for latency, 0.3 ns less and stable.
I couldn't get to 62400 MB/s Read, lost 100 MB/s but I was able to gain 100 MB/s in write and copy.


----------



## umea

i havent rly looked at any read write copy stuff because im on trial so its effort but maybe ill buy it soon to save time, and ill do more testing with 1t, for now gonna see what lowest possible trfc is for me without erroring out, 120ns seems to give error 1 after a pass or two so it should be around 125ns.


----------



## i9forever

duarte36 said:


> hello . i have the f4-4000C14D-32GTES , 16GBx2 DR . windows boot and work at 1/1 on auto, i get *whea error 20* only playing games , but without bsod , tired from playing with voltages and timings , they are working @ 3800 cl14 1/1 . for sure is IF , cause i have 4x8GB ripjaws 3200 cl14 that worked for years @ 4000 cl16 1.42v , and even those gave me whea errors. i think i stay like that for now, but i can take some pictures if anyone is interested.
> Good luck and alot of patiente to all 'overclockers' here
> 
> ps. Dark hero with 5900x


Hello, please did you solve the whea 20 somehow yet? I have the same problem, ram is stable for hours in 1usmusV3, but trowing errors in games and in OCCT CPU large test.
Is the whea 20 related to cpu? Vcore, VDDP, CCD, IOD or SOC? Or is it harmless whea and just suppress it is enough?


----------



## Veii

Audioboxer said:


> The only thing I don't like about 2T at tCL15 is it forces my tPHYRDL to 28 on one stick. So, 28/26. Would need to go to tCL14 to get it back to 26 at 2T


That's a missprediction of IO-L and has no connection to timings
It only has a connection, if you leave something on auto, or depend on brand based cheatery
As for example, msi low latency mode, performance bias and similar things

Its an indication that the 2nd slot doesnt recieve enough current ~ and so memory prediction does what it has to do, predict functional settings at any cost

Be it by too low cLDO_VDDP or too low procODT
V_REF per channel, will help with this as @ManniX-ITA i think was it ~ mentioned
Could confirm it myself, change there on msi boards (10mV apart) matched both tPHY's
But pushed both to 28

Potentially it's better for higher frequency, but i had also other msi bios conflict issues from B450-X570
They'll get it together.

You guys might want to invest some time in checking/extending tPHYRDL 24-24 on 3133 strap and above
tWRRD, tRDWR and RTT_WR influence this
Memory traing remains a miracle, but it's one of the issues for running 13-13 

tCWL & tCL are not controling it
Just byproducts trying other straps for prediction, but yet nothing that influence it


----------



## Audioboxer

Veii said:


> That's a missprediction of IO-L and has no connection to timings
> It only has a connection, if you leave something on auto, or depend on brand based cheatery
> As for example, msi low latency mode, performance bias and similar things
> 
> Its an indication that the 2nd slot doesnt recieve enough current ~ and so memory prediction does what it has to do, predict functional settings at any cost
> 
> Be it by too low cLDO_VDDP or too low procODT
> V_REF per channel, will help with this as @ManniX-ITA i think was it ~ mentioned
> Could confirm it myself, change there on msi boards (10mV apart) matched both tPHY's
> But pushed both to 28
> 
> Potentially it's better for higher frequency, but i had also other msi bios conflict issues from B450-X570
> They'll get it together.
> 
> You guys might want to invest some time in checking/extending tPHYRDL 24-24 on 3133 strap and above
> tWRRD, tRDWR and RTT_WR influence this
> Memory traing remains a miracle, but it's one of the issues for running 13-13
> 
> tCWL & tCL are not controling it
> Just byproducts trying other straps for prediction, but yet nothing that influence it


You mean the 1st slot or 2nd slot? For me its A1 that will go to 28 whilst B1 stays on 26.

I have tried more VDDP and played with ProcODT previously to no result. But I guess I can look at V_REF, though I dunno where this is in the BIOS or if it needs one of those MSI "unlocked" BIOS mods?

Higher frequency does seem to influence things, not so problematic at 3600.

Thanks for confirming tCWL and tCL are not really where I should be looking.










For example, 3600 at 2T with same voltages/timings is 26/26.

Jump up to 3800 though and this



















Only 26 on B1.

*Edit* - I found DRAM CH_A VREF Voltage and it has a B as well. Says 0.6v is default/auto. Guess I'll try messing with them lol. I have no idea what safe/expected values are for these though!

Figured out while they can be set independently it's essentially the MEM VTT figure in ZenTimings and AUTO seems to be half of VDIMM. I tried bumping them up to 0.79v instead of 0.75v but it did nothing to tPHYRDL. Got some more figuring out to do it seems other than just pumping VTT lol.


----------



## Thanh Nguyen

What exactly value brings down the latency for AMD guys?


----------



## duarte36

i9forever said:


> Hello, please did you solve the whea 20 somehow yet? I have the same problem, ram is stable for hours in 1usmusV3, but trowing errors in games and in OCCT CPU large test.
> Is the whea 20 related to cpu? Vcore, VDDP, CCD, IOD or SOC? Or is it harmless whea and just suppress it is enough?


hello , i do not tried a lot, but i think my 5900x can't do 2000fclk, it's @ 1900 fclk without errors , and memory is @ 3800 14-15-15, not enough time to play around now . even 2100 he does ,with same errors... but @ 1900 do not give 1 single error .
even without bsod i do not want errors turning around in windows.


----------



## ManniX-ITA

Veii said:


> V_REF per channel, will help with this as @ManniX-ITA i think was it ~ mentioned


Thanks for the mention but no if I'm not wrong the culprit is @mongoled 



Thanh Nguyen said:


> What exactly value brings down the latency for AMD guys?


I can say tRC and tRFC for starter.
The awful XMP profile for my kit comes with tRC 94 and tRFC 700.

Just lowering these two to reasonable values brought the latency from 56-57ns back to 53ns.

I was able to get to 52.9ns with the tCL15 profile but the DIMMs are topping 61c and then overheating 
Have to replace the heatsinks and check again.


----------



## Veii

duarte36 said:


> only a question. supposing that fclk can do 2000 , he must do it with cl14 / cl16 for example, or it's possible that he does with cl16 but not cl14 ?


4000C14-14-14 needs 1.65-1.68v
4000C16-16-16 around 1.46-1.48
Very possible that it doesnt "just work" 

CL means nothing
EDIT: 15-15-15 could need 1.52-1.58v 


Audioboxer said:


> *Edit* - I found DRAM CH_A VREF Voltage and it has a B as well. Says 0.6v is default/auto. Guess I'll try messing with them lol. I have no idea what safe/expected values are for these though


Half of VDIMM
+/- 20mV
In order to change memory training, it needs a psu off cold boot
psu off + standby discharge by the powerbutton

missmatch both V_REF's and it should fix itself
consider using tWRRD on dual rank or many dimm setup's


----------



## Audioboxer

Veii said:


> 4000C14-14-14 needs 1.65-1.68v
> 4000C16-16-16 around 1.46-1.48
> Very possible that it doesnt "just work"
> 
> CL means nothing
> EDIT: 15-15-15 could need 1.52-1.58v
> 
> Half of VDIMM
> +/- 20mV
> *In order to change memory training, it needs a psu off cold boot*
> psu off + standby discharge by the powerbutton
> 
> missmatch both V_REF's and it should fix itself
> consider using tWRRD on dual rank or many dimm setup's


Thanks, I didn't know that!


----------



## Audioboxer

@Veii Not really getting any luck with cold boots, so I thought I'd see how high frequency wise can I go with it training at 26/26 with 2T above 3600










3667 is the highest.










3733 is when it swaps to 28.

Something that might be of interest is tCKE on AUTO seems to go to 0? at 3600~3667? 0 isn't even a valid number according to the BIOS.

It changes to 1 at 3733 which is also when tPHYRDL goes to 28. Coincidence?

*edit - *










One stick of memory, BIOS on default/auto other than me changing RAM to 3800/1.5v. 26 at 3800.










2 sticks of memory, same settings as above, all auto except 3800/1.5v. Now we have 28/26.

Both sticks on their own will give 26. So the issue seems to be when I use both DIMMs? So it could be the motherboard then???


----------



## Thanh Nguyen

ManniX-ITA said:


> Thanks for the mention but no if I'm not wrong the culprit is @mongoled
> 
> 
> 
> I can say tRC and tRFC for starter.
> The awful XMP profile for my kit comes with tRC 94 and tRFC 700.
> 
> Just lowering these two to reasonable values brought the latency from 56-57ns back to 53ns.
> 
> I was able to get to 52.9ns with the tCL15 profile but the DIMMs are topping 61c and then overheating
> Have to replace the heatsinks and check again.


What cause the performance loss when I run 4000/2000?


----------



## ManniX-ITA

Thanh Nguyen said:


> What cause the performance loss when I run 4000/2000?


Usually unstable Infinity Fabric.
You need to find the right voltages.
In some cases CLKREQ# is required to avoid it.

Read this post/whole thread:









WHEAService, WHEA errors suppressor - unleash Ryzen...


@anyone of yall, thats been running this since you had WHEA19 issues. have you noticed any strange things occur? have you needed to increase voltage ranges on IOD/CCD/cLDO_VDDP to keep 4000/2000 stable (or whatever IF clk your running?) ive managed to DRASTICLY lower my WHEA 19s at IF 2000...




www.overclock.net


----------



## LockAlive

Is it a good or bad PCB version?


http://imgur.com/8A42Q6Z


----------



## Thanh Nguyen

ManniX-ITA said:


> Usually unstable Infinity Fabric.
> You need to find the right voltages.
> In some cases CLKREQ# is required to avoid it.
> 
> Read this post/whole thread:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> WHEAService, WHEA errors suppressor - unleash Ryzen...
> 
> 
> @anyone of yall, thats been running this since you had WHEA19 issues. have you noticed any strange things occur? have you needed to increase voltage ranges on IOD/CCD/cLDO_VDDP to keep 4000/2000 stable (or whatever IF clk your running?) ive managed to DRASTICLY lower my WHEA 19s at IF 2000...
> 
> 
> 
> 
> www.overclock.net


I cant find clkreq in my bios. Dark hero.


----------



## ManniX-ITA

Thanh Nguyen said:


> I cant find clkreq in my bios. Dark hero.


Unfortunately it's not always exposed.
You have to try with just voltages.

Are you using the bios shared on HWBot for LN2?
I'm not sure if it's a normal beta bios or not.






ROG Crosshair VIII Hero / FORMULA / IMPACT / DARK HERO / EXTREME LN2 OC Guide


ROG CROSSHAIR VIII Series 4001 BETA BIOS 1. Update AGESA version to ComboV2PI 1206 New AGESA version has been applied, but there may be bugs. So please rollback to the previous version if you have any problems Thanks ROG CROSSHAIR VIII HERO BETA BIOS 4001 ROG CROSSHAIR VIII HERO WIFI BETA BIOS 40...



community.hwbot.org


----------



## Veii

Audioboxer said:


> Both sticks on their own will give 26. So the issue seems to be when I use both DIMMs? So it could be the motherboard then???


IMC FW & memory training belong to the AGESA blob
Part of it, preconfigured timings & resistances belong to the board.

If it fails on one channel, it has a reason
If it continues to fail after swapping both dimms, then its purely board related and not CPU or RAM
Maybe start with undervolting everything except the ram
Also consider to just jump down to AGESA 1.2.0.0, if the newer one causes issues ~ or jump to bios mods

Had the problem, but fixed it
Both to 28 instead of 26, but good enough
If its a strap issue, then 3800 has to match up both
Consider giving BGS pure, a try

tCKE only will influence it, as much as RTT and tRDWR/tWRRD
As in "it's unstable" auto corrected unstable 
Yet has no influence to it
If it would be one to one like tRDRD_SG, then tRRD_S+tCWL would be a trigger point
Considering low strap 3133 runs 24-24, at any tCL preset (12-12 or 15-15) ~ it has no connection to it. Just a sideproduct-issue


----------



## Audioboxer

Veii said:


> IMC FW & memory training belong to the AGESA blob
> Part of it, preconfigured timings & resistances belong to the board.
> 
> If it fails on one channel, it has a reason
> If it continues to fail after swapping both dimms, then its purely board related and not CPU or RAM
> Maybe start with undervolting everything except the ram
> Also consider to just jump down to AGESA 1.2.0.0, if the newer one causes issues ~ *or jump to bios mods*
> 
> Had the problem, but fixed it
> Both to 28 instead of 26, but good enough
> If its a strap issue, then 3800 has to match up both
> Consider giving BGS pure, a try
> 
> tCKE only will influence it, as much as RTT and tRDWR/tWRRD
> As in "it's unstable" auto corrected unstable
> Yet has no influence to it
> If it would be one to one like tRDRD_SG, then tRRD_S+tCWL would be a trigger point
> Considering low strap 3133 runs 24-24, at any tCL preset (12-12 or 15-15) ~ it has no connection to it. Just a sideproduct-issue


I tried both sticks on their own in the DIMM nearest the CPU which I believe is A1. With all default/auto like my pictures both booted with 26/26. I haven't tried them on their own in B1, I guess I should even although B1 always seems to be 26 when both are in use.

I'll also try playing more with voltages rather than just leaving on auto.

By BIOS mod do you mean like these by Eder I think it is? MSI B550 UNIFY-X - Google Drive


----------



## Steve_

sonixmon said:


> Got a nice 5900x I will trade you for!
> 
> 
> 
> Do you really need 64GB?
> 
> 
> 
> For part of my work flow, it's certainly a big advantage but not everything I do benefits from it so still weighing up whether I tune up 2x16 to the max or keep fiddling with 4x16


----------



## Veii

Thanh Nguyen said:


> I cant find clkreq in my bios. Dark hero.


AMD PBS half of it
DarkHero should have open bioses
Especially XOC/LN2 versions of them


----------



## Audioboxer

@Veii Here is something of interest! Instead of BIOS default timings with one stick I used my current timings. Same stick used below in each example.










B1 is the slot nearest my CPU. 26.










A1 is the slot furthest from my CPU. 28.

So it seems as if the issue is with slot A1 which is the furthest away slot out of the two. Question is then with only slot A1 occupied what could I try changing to see if I can get it to do 26 

Same behaviours are exhibited with 1 stick in A1 with tCL/command rate, even although you said not to pay much attention to them. (tCL14 2T = 26, tCL14 1T = 28, tCL15 2T = 28, tCL15 1T = 26).

Might have to try some other AGESA versions now.


----------



## XPEHOPE3

Veii said:


> In order to change memory training, it needs a psu off cold boot
> psu off + standby discharge by the powerbutton


I use an easier path to guarantee retraining: just post into bios, change nothing and "Save and exit".

I also use a desktop shortcut to reboot directly to BIOS (run with admin): .....

then cloudfare somehow prevents me from posting the damn command in text form...


----------



## rossi594

Taraquin said:


> Helped at fellow 5600X-friend the other day and can share my experience with Samsung D-die. Bullzoid has 2 videos of them where he say they are similar to rev E.
> 
> 4000/2000 with no wheas was easy, running about same voltages as me on B550 Tomahawk with agesa 1.2.0.3B. 1.12v soc, 1.04 iod, 0.92 ccd, 0.88 vddp
> 
> As for the ram it is a cheap 2x8 3200 16-18-18 rgb kit.
> 
> Ended up after some basic stabilitytesting with:
> 18-21-21-17-40, 66 rc, 5/7/16 rrds-faw, 16/8 wr/rtp, 18 cwl, 620 trfc, 2/10 rdwr/wrrd, 4/12 wtr, 4 scl, gdm on, 1.4V.
> 
> Slightly lower rc and trfc might work, but the others were at minimum, we tried 1.45V but did not help.
> 
> Compared 2 stock fps (4000 at 18-22-22-44 and rest on auto) in Cyberpunk 1080low with dlss ultra perf went from 150 to 170fps avg, dram calc test went from 164 to 123 sec.
> 
> All in all the Samsung D-die seems like a bad binned Micron rev E. It struggles with all primaries, rc and rfc is bad, trrd/faw okay, rtp okay, wr bad, scls okay. Best I can say about them is that they are very cheap and can clock really high.


Does that mean that whea 19s are a b-die related issue?


----------



## XPEHOPE3

Steve_ said:


> If anyone's got any advice on how to tweak this further, I'd be most appreciative.


I think only me and @Sleepycat run 16*4 in this thread. This list contains my results as well as some other 16*4. Notice how I have mostly much worse timings and much worse bin and worse CPU clocks than you but still the same latency. In your shoes I'd try:

Verify each change at least with TM5 run of 1usmus_v3 config for 25 cycles for stability. Yes, it takes 6.5 hours 💩 But if it's not stable, you might need to relax timings/clocks, not tighten them.
tRCDWR=tRP=14, GDM off, CR 2T
tRTP 10 or 8 whichever gives lower latency and is stable
Run Aida latency test (doubleclick the cell) multiple times and pick only those values which are not obvious outliers. First run is always slower... Also disable background things like Steam or Windows Defender realtime checks for testing (and remember to do it all the time)
SD/DD from 5-5-7-7 to 4-4-6-6
Check if stick in B1 slot also has tPHYRDL 26 and not 28 or more.


----------



## Audioboxer

Tried going back to some earlier BIOS revisions and no luck, same behaviours with tPHYRDL. The only way I can consistently get it to move around is changing either tCL or changing the command rate.

Giving up on it and I'll see what happens with my new memory when it arrives.

@Veii Does memory interleaving have anything to do with helping? Just noticed its something in the BIOS settings I've never messed with before.


----------



## MrHoof

@Audioboxer Coincidence I just messed around with memory interleaving going up in size reduces performance is what i can say about it, best resulst at 256byte or auto. tPHYRDL didnt change.


----------



## Taraquin

rossi594 said:


> Does that mean that whea 19s are a b-die related issue?


I don't think it's due to B-die itself. I have B-die and 5600X, no wheas at 4000. It seems like 5900X and 5950X is more prone to wheas. Maybe the extra stress tuned B-die puts on the IMC increases risk? Would be interesting to see if wheas increase with more tuning


----------



## rossi594

Taraquin said:


> I don't think it's due to B-die itself. I have B-die and 5600X, no wheas at 4000. It seems like 5900X and 5950X is more prone to wheas. Maybe the extra stress tuned B-die puts on the IMC increases risk? Would be interesting to see if wheas increase with more tuning


I think I have a pretty good soc (mine did 2000 flck at 1,040v) but I have tons of wheas. Even if I up the vsoc to 1,205v. Would be nice to know why does come up and maybe how to tune for not having them. Did you share your timings somewhere?


----------



## Audioboxer

MrHoof said:


> @Audioboxer Coincidence I just messed around with memory interleaving going up in size reduces performance is what i can say about it, best resulst at 256byte or auto. tPHYRDL didnt change.


Hmm, thanks.

I am wondering what the PHY Configuration section of DRAM settings might do.










Reason I'm asking is Tphy_rdlat is what the BIOS refers to as tPHYRDL. So I dunno if "Phy" configuration has anything to do with "Tphy" lol


----------



## MrHoof

They are actuly memory training settings, try setting those.








A or 10 is same most boards want hex.


----------



## Audioboxer

MrHoof said:


> They are actuly memory training settings, try setting those.
> View attachment 2525121
> 
> A or 10 is same most boards want hex.


Not sure if I should have had them set before now or if auto on everything basically covers 99% of situations, but I'll play around with these and see! Training seems to be tied up in the issues I'm having with DIMM A1.


----------



## MrHoof

I think PMU Pattern Bits increanse training time but can give better result if auto is dumb. Not sure if DFE/FEE trainings are not enabled on auto anyway.


----------



## Audioboxer

MrHoof said:


> I think PMU Pattern Bits increanse training time but can give better result if auto is dumb. Not sure if DFE/FEE trainings are not enabled on auto anyway.


Unfortunately no such luck helping out. 2T tCL15 still results in 28.

One other thing I have noticed is DFI MaxReadLatency also goes to 8 when it's 28. On 27 it drops down to 7.

Oh well, once my other sticks are here I'll be able to see if they behave the same way on tCL 14/15 and 1T/2T.


----------



## sonixmon

Audioboxer said:


> What I can't understand is why 2T runs at 28/26 but 1T will run at 26/26. On paper, makes no sense, considering 1T, even if it is with Setups, should be more strain on the memory/IMC.
> 
> tCL14 behaviour I guess I can understand more, it's 26/26 at 2T but 28/26 at 1T for me. It's tCL15 that is reversed, 26/26 at 1T but 28/26 at 2T  I've seen some other people get similar behaviour on a 5950x with DR/3800 so I'm not alone, just a case of trying to figure out what is causing it, memory, mobo, CPU or a combination. With a B550 Unify X, I'd rule out mobo. Can't really get many better boards for memory OCing. So as I said interested to see what results I get with this 4000 kit.


I consistently get 28/28, in all my screenshots of settings I have tried I only noticed 26 once and it was with GDM on vs 1T Setup 56 0 0. Also I almost always have run 56 0 0, I don't know if that is better or not. I really have not done any testing between 56, 56, 56 and 56, 0, 0 but between GDM on and 1T 56 my results are better with the latter.

Should I be concerned about 28 vs 26? Could be my secondary timings as I really am novice and mostly have copied others settings (who have similar ram) and see what is stable and works best for my setup. This is what I am currently running and is fine below 42c on ram. I call it my 3800Fast42Max profile! I also have a 3800Max45 profile for hotter times of year. LOL

Also I have not ever tested 2T for comparison since most have commented that 1T with setup has been better for them.


----------



## Audioboxer

sonixmon said:


> I consistently get 28/28, in all my screenshots of settings I have tried I only noticed 26 once and it was with GDM on vs 1T Setup 56 0 0. Also I almost always have run 56 0 0, I don't know if that is better or not. I really have not done any testing between 56, 56, 56 and 56, 0, 0 but between GDM on and 1T 56 my results are better with the latter.
> 
> Should I be concerned about 28 vs 26? Could be my secondary timings as I really am novice and mostly have copied others settings (who have similar ram) and see what is stable and works best for my setup. This is what I am currently running and is fine below 42c on ram. I call it my 3800Fast42Max profile! I also have a 3800Max45 profile for hotter times of year. LOL
> 
> Also I have not ever tested 2T for comparison since most have commented that 1T with setup has been better for them.
> 
> View attachment 2525124


I bet if you remove the Setup timing and change that profile to 2T it will be 26. When I run tCL14 at 3800 it needs 2T for 26*.

As for it being an issue having 28, it's not an issue in so far as it's a valid number to have. The issue is a mismatch between the DIMMs. A2 in your picture has 28, but does B2 have 26? I'm going to guess it does. This mismatch can add up to/around 0.5ns in latency from some of my testing. That doesn't mean stability issues, it's just the memory being funky as really it should be the same figure on both DIMMs.

I've never actually experienced 28/28 (but Veii/mongoled and others have spoken about getting 28/28), the only time I have a matching number is if I can get it to 26/26. Otherwise it's 28/26.

We've got different CPUs and different motherboards, but pretty similar DR 2x16GB b-die. Wondering if this is something DR b-die is more susceptible to?

*Unless I only run 1 DIMM










Ignore the auto/default timings, tCL14 at 3800 is still in play, but now it's tPHYRDL 26 with 1 stick. You could try that as well if you want. Take one of your sticks out and see if it swaps to 26 at 3800/1T.

*Edit* - I'm blind as a bat just noticed you said you get 28/28, that is fine lol.


----------



## Veii

@Audioboxer MSI's 3 different latency enhance modes do nothinf ?
Auto, msi mode and low latency
Sadly, with the most restrictive bios (asrock), i just get correct results
They fix flakiness by themselves update after update
Would need to dig in hex, what changed between our boards to figure good and bad changes

Chipset interleaving size depends on IC size and IC amount/rank amount too
BGS and BGS Alternative behaves different, soo likely also SD, DDs behave different by BGS changes

256 works great on 2x8gb
512 is rather recommendable for dual rank and SR 2048MB iCs
It depends
SiSoftware Sandra Inter-Core Latency tests shows it ~ after boosting & cache is consistent
Edit:
It can be also a difference by the single and dual CCD ~ yet also is a thing by dimm density. Sadly unclear with such low sample size

Still in holiday
Will see what we can figure out
Waiting for good results between 4267 & 3200C14 2021 DR kits
Heard 3600C11-11-11 😛
Waiting till the IntelOCer finishes binning, then i'll get them to play with on AMD

There are low timings and 5000+ MT/s C16 posting differences
One is better with timings, other scales great till 5067MT/s
I'll see & comment on the binning part, when i get them/one batch ~ in my hands


----------



## thigobr

I am getting tPHYRDL 28 on both channels when using setup timings... I tried many things to no avail: vSOC, VDDG, vREF, VDIMM, the MSI setting... It will only go back to 26 if I set CR 2T


----------



## SneakySloth

I think these are my final timings and they seem to be stable.

Patriot Viper 4400, 4x8GB, A2.


















Tests done:


TM5 75 cycles (50 + 25) (+ 4 hours of GPU stress test to heat up the system).
Karhu 18500% + Stress FPU + Cache enabled (+1.5 hours of GPU stress test).
2 hours Prime95 Large FFT
2 hours OCCT memory test AVX2


Regarding the tPHYRDL timing that some people have mentioned previously. Mine is 28 for A1, and A2 while 26 for B1 and B2.


----------



## Mach3.2

thigobr said:


> I am getting tPHYRDL 28 on both channels when using setup timings... I tried many things to no avail: vSOC, VDDG, vREF, VDIMM, the MSI setting... It will only go back to 26 if I set CR 2T
> 
> View attachment 2525138


For what's it worth my 2*16GB kit of Crucial Ballistix Rev Bs also default to tPHYRDL 28 on one of the channels on XMP timing, 1T GDM off.

@3733MHz, tCL 15 bumped it down to 26, tCL 14 pushed it back up to 28.


----------



## umea

Veii said:


> It can be also a difference by the single and dual CCD ~ yet also is a thing by dimm density. Sadly unclear with such low sample size
> Still in holiday
> Will see what we can figure out
> Waiting for good results between 4267 & 3200C14 2021 DR kits
> Heard 3600C11-11-11 😛
> Waiting till the IntelOCer finishes binning, then i'll get them to play with on AMD
> 
> There are low timings and 5000+ MT/s C16 posting differences
> One is better with timings, other scales great till 5067MT/s
> I'll see & comment on the binning part, when i get them/one batch ~ in my hands


I wish my IMC was able to handle proper stuff, if Zen3D+ wasn't around the corner I'd see if I can get my hands on a 5600x or a 5700g to mess around with to see what the 4266 2021 DR kit I have is capable of. Might still do it anyways tbh.
Has anyone tested a 5700g to see how the IMC holds up versus a 5600x? I remember seeing someone offhand mentioning that the G series has better IMCs than their X counterparts but there was no evidence to back it up


----------



## sonixmon

Audioboxer said:


> I bet if you remove the Setup timing and change that profile to 2T it will be 26. When I run tCL14 at 3800 it needs 2T for 26*.
> 
> As for it being an issue having 28, it's not an issue in so far as it's a valid number to have. The issue is a mismatch between the DIMMs. A2 in your picture has 28, but does B2 have 26? I'm going to guess it does. This mismatch can add up to/around 0.5ns in latency from some of my testing. That doesn't mean stability issues, it's just the memory being funky as really it should be the same figure on both DIMMs.
> 
> I've never actually experienced 28/28 (but Veii/mongoled and others have spoken about getting 28/28), the only time I have a matching number is if I can get it to 26/26. Otherwise it's 28/26.
> 
> We've got different CPUs and different motherboards, but pretty similar DR 2x16GB b-die. Wondering if this is something DR b-die is more susceptible to?
> 
> *Unless I only run 1 DIMM
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Ignore the auto/default timings, tCL14 at 3800 is still in play, but now it's tPHYRDL 26 with 1 stick. You could try that as well if you want. Take one of your sticks out and see if it swaps to 26 at 3800/1T.
> 
> *Edit* - I'm blind as a bat just noticed you said you get 28/28, that is fine lol.


Ok I am going to do some 2T testing this weekend. I have never seen 26/28 myself but I didnt start checking both ram modules until you mentioned a few weeks ago so all my history tracking screenshots are of single DIMM but I have checked 3-4 times with ZenTimings and never seen a mismatch yet. I will do some more checking tomorrow.
Thanks!


thigobr said:


> I am getting tPHYRDL 28 on both channels when using setup timings... I tried many things to no avail: vSOC, VDDG, vREF, VDIMM, the MSI setting... It will only go back to 26 if I set CR 2T
> 
> View attachment 2525138


Ok I plan to test 2T this weekend too, thanks!


----------



## Skull_Angel

Oi, old lurker here. It's been a while since I've put together a personal build I intend to tune and since ram seems to be the only worthwhile part to really tinker with for 5000 series I'm digging deeper into it than in the past. I've skimmed a lot of this thread picking up a ton of good info, big thanks to everyone and especially @Veii.

Currently at the point where I'm beginning to tighten primary timings and just wanted some confirmation on how my other settings look before I proceed. Any advice on what to tighten/loosen for general stability before moving forward would be appreciated.

Current system:
5600x
x570 Tomahawk (1.2.0.3b)
G.skill Flarex 2x16 3200 14-14-14-34 (b-die, rc b1)

Testing:
OCCT memory test - 30 min SSE, 30 min AVX2
TM5 - 2 runs of [email protected]
p95 - 12 hours blend, 12 threads

Aida64 benchmark shows consistent 57ns +/- 0.2 variation










I've tried pushing fclk with lose timings, but around 1900 gave me a massive headache. First try it booted w/o issue and passed testing, but ever since it hasn't made it past post, and honestly I'm ok with 1800 since it hasn't been fussy (no WHEAs).


----------



## Taraquin

rossi594 said:


> I think I have a pretty good soc (mine did 2000 flck at 1,040v) but I have tons of wheas. Even if I up the vsoc to 1,205v. Would be nice to know why does come up and maybe how to tune for not having them. Did you share your timings somewhere?











My B-die has a terrible bin, yours can probably get away with better timings


----------



## Taraquin

rossi594 said:


> I think I have a pretty good soc (mine did 2000 flck at 1,040v) but I have tons of wheas. Even if I up the vsoc to 1,205v. Would be nice to know why does come up and maybe how to tune for not having them. Did you share your timings somewhere?


How is your iod, ccd and vddp? How is your stepping? I try to stick to the 40mv stepping and keep vddp and ccd low, and iod and soc slightly above the performance treshold. I can set iod and soc 0.01V and all works fine, but setting one or both 0.02V lower or more I get a latencypenalty in aida. 1.08v soc is also 100% stable, but I loose a few perccent performance.

My MB has only 2 dimm slots, this will improve signal vs many 4 dimm MBs, it might reduce whea-risk.


----------



## Audioboxer

thigobr said:


> I am getting tPHYRDL 28 on both channels when using setup timings... I tried many things to no avail: vSOC, VDDG, vREF, VDIMM, the MSI setting... It will only go back to 26 if I set CR 2T
> 
> View attachment 2525138


Interesting to see another MSI/5950x combo displaying this! I'll double check what happens for me at tCL16 3800, I've only been using 14 or 15.

Yup, same as you

tCL16 1T/56 = 28, although again I only have it on one channel, so 28/26.
tCL16 2T = 26/26

Same as my tCL14 behaviour

tCL14 1T/56 = 28/26
tCL14 2T = 26/26

It's when I move to 15 it gets inverted

tCL15 1T/56 = 26/26
tCL15 2T = 28/26

I know @Veii said not to be primarily concerned with tCL when it comes to tPHYRDL, but this behaviour just seems weird and for me it's the only way to reproduce the 26/26 or 28/26. I can't figure out why tCL15 is the opposite way around from tCL14/16.


----------



## Steve_

XPEHOPE3 said:


> I think only me and @Sleepycat run 16*4 in this thread. This list contains my results as well as some other 16*4. Notice how I have mostly much worse timings and much worse bin and worse CPU clocks than you but still the same latency. In your shoes I'd try:
> 
> Verify each change at least with TM5 run of 1usmus_v3 config for 25 cycles for stability. Yes, it takes 6.5 hours 💩 But if it's not stable, you might need to relax timings/clocks, not tighten them.
> tRCDWR=tRP=14, GDM off, CR 2T
> tRTP 10 or 8 whichever gives lower latency and is stable
> Run Aida latency test (doubleclick the cell) multiple times and pick only those values which are not obvious outliers. First run is always slower... Also disable background things like Steam or Windows Defender realtime checks for testing (and remember to do it all the time)
> SD/DD from 5-5-7-7 to 4-4-6-6
> Check if stick in B1 slot also has tPHYRDL 26 and not 28 or more.


Thanks for this. This machine is my first AMD for a LONG time so I'm still pretty new to memory tuning to this level.

for point 1. - I've yet to run the full 6.5 hours with this setup. My technique has been a bit naughty and I've basically tweaked timings and checked speeds & latency and if repeat runs have been consistent and better than my previous timings, I've kept them and moved on after the quick memtest in the DRAMCalculator tool. At the point where it gets hard to make gains is where I've then started full stability checks. This worked quite well with 2x16GB - in that backing away slightly from the point where I stopped finding gains did pass full memory tests but I accept this is not the best way to test. I've seen a few comments suggesting the full 6.5 hours of testing is only required to ensure memory temps have stabilised. With my cooling solution, I get stabilised temps after 10 minutes and the worst spot is just under 44deg C so not too bad. However, I'm unsure whether it's still worth doing the full cycles just to ensure enough conditions have been met to ensure stability? I'm assuming I should, regardless of when temperatures stabilise?

For 2 onwards, I'll have more of a play today.

For 6. When running 2T with GDM off, all sticks are 26 tPHYRDL. I've not checked all yet with 1T GDM on. For interest, just keeping my current timings and going to 2T GDM off is significantly worse for speeds and latency. Is this an indication that I'm already pushing timings too hard and that GDM is fudging things? Or just that I can tune further with 2T GDM off? For info, I've never managed to boot 1T GDM off even with _really _loose timings.


----------



## RosaPanteren

I have seen someone mention need for new heat spreaders and came to think of one of Luumi's videos.

He uses some custome made heat spreaders from BartXstore









Custom RAM copper heatsinks for B-Die based RAM - Bartxstore


Custom made copper RAM heatsinks for memory extreme overclocking using dry ice or LN2. Designed for DDR4 chips - Samsung B-Die.




bartxstore.com





I would guess these could be attached to ram water blocks the same way the aluminium 3rd party ram modules from EK or Alphacool

They are pretty expensive @ 65 euro, so I contemplate on make my own from a 2-3mm copper sheet


----------



## mongoled

RosaPanteren said:


> I have seen someone mention need for new heat spreaders and came to think of one of Luumi's videos.
> 
> He uses some custome made heat spreaders from BartXstore
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Custom RAM copper heatsinks for B-Die based RAM - Bartxstore
> 
> 
> Custom made copper RAM heatsinks for memory extreme overclocking using dry ice or LN2. Designed for DDR4 chips - Samsung B-Die.
> 
> 
> 
> 
> bartxstore.com
> 
> 
> 
> 
> 
> I would guess these could be attached to ram water blocks the same way the aluminium 3rd party ram modules from EK or Alphacool
> 
> They are pretty expensive @ 65 euro, so I contemplate on make my own from a 2-3mm copper sheet


Very nice


----------



## Veii

Audioboxer said:


> I know @Veii said not to be primarily concerned with tCL when it comes to tPHYRDL, but this behaviour just seems weird and for me it's the only way to reproduce the 26/26 or 28/26. I can't figure out why tCL15 is the opposite way around from tCL14/16.


Close to every example i can see here, doesn't use tWRRD at all
Many are +3 on tRDWR instead of +1.5 or typical +2

Changing only tCL & tCWL, without touching tRDWR
Without actually testing if this preset, is actually stable
Such makes comparing predictions a very bad idea

You can not draw conclusions any channel mismatch happens, when you (many) don't bother to check stability first 
I'd always adapt tRDWR for it

If itself matching, tCL=tCWL
Then tRDWR = tRCDRD/2 , later +2 for DR or many dimms
Then if only +1 works, you have to use tWRRD

If tCWL ≠ tCL (soo tCWL is -1) , then tRDWR needs to be +1 ontop

I can easily see, alone logically, why IO-L so also tRDRD_SG, would end up higher , when tCWL matched or missmatches
Aka tRDWR matches or missmatches
=========================
Adapt tRDWR and check
When Memory training has to adapt for a flaw ~ which us why IOL is higher
Then you clearly have an issue
Not confirming stability, confuses theories

Between 28-28 & 26-26 is another story
But missmatching clearly shows issues
Considering i have this on B450 & X570 Tomahawk
It's not a board engineers flaw, and traces are correctly placed/made


----------



## rossi594

Taraquin said:


> How is your iod, ccd and vddp? How is your stepping? I try to stick to the 40mv stepping and keep vddp and ccd low, and iod and soc slightly above the performance treshold. I can set iod and soc 0.01V and all works fine, but setting one or both 0.02V lower or more I get a latencypenalty in aida. 1.08v soc is also 100% stable, but I loose a few perccent performance.
> 
> My MB has only 2 dimm slots, this will improve signal vs many 4 dimm MBs, it might reduce whea-risk.


I read that to high of a vddp can be bad so kept that low (also it should give your soc more power to through around). But I tried around a lot I was running 900 vddg and 850 vddp with 1.040 vsoc. But I increased both over 1v at some stage in the hopes to try to get rid of the whea 19s.

It seems a bit like searching the needle in the heystack with those 3 voltages. All you know is if you don't have enough vddg iod you will have usb disconnects and sound stuttering (at least for me) and if your vsoc is not high enough you won't get your memory stable and that vddg and vddp have to be at least 50mv lower than vsoc. But otherwise I don't know how those voltages affect each other or the wheas. I read somewhere that to high vsoc can also cause wheas.

I think I will try your settings with the new bios and see how it works out. Thanks for posting. I will update you.


Maybe I will try to set something up with gdm off. The halving of the speed that it can do for power saving and stability maybe masking instable settings and causing whea (just my theory).


----------



## umea

RosaPanteren said:


> I have seen someone mention need for new heat spreaders and came to think of one of Luumi's videos.
> 
> He uses some custome made heat spreaders from BartXstore
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Custom RAM copper heatsinks for B-Die based RAM - Bartxstore
> 
> 
> Custom made copper RAM heatsinks for memory extreme overclocking using dry ice or LN2. Designed for DDR4 chips - Samsung B-Die.
> 
> 
> 
> 
> bartxstore.com
> 
> 
> 
> 
> 
> I would guess these could be attached to ram water blocks the same way the aluminium 3rd party ram modules from EK or Alphacool
> 
> They are pretty expensive @ 65 euro, so I contemplate on make my own from a 2-3mm copper sheet


Ohhh this is exactly what I've been looking for, here's the video for those interested:


----------



## Audioboxer

Veii said:


> Close to every example i can see here, doesn't use tWRRD at all
> Many are +3 on tRDWR instead of +1.5 or typical +2
> 
> Changing only tCL & tCWL, without touching tRDWR
> Without actually testing if this preset, is actually stable
> Such makes comparing predictions a very bad idea
> 
> You can not draw conclusions any channel mismatch happens, when you (many) don't bother to check stability first
> I'd always adapt tRDWR for it
> 
> If itself matching, tCL=tCWL
> Then tRDWR = tRCDRD/2 , later +2 for DR or many dimms
> Then if only +1 works, you have to use tWRRD
> 
> If tCWL ≠ tCL (soo tCWL is -1) , then tRDWR needs to be +1 ontop
> 
> I can easily see, alone logically, why IO-L so also tRDRD_SG, would end up higher , when tCWL matched or missmatches
> Aka tRDWR matches or missmatches
> =========================
> Adapt tRDWR and check
> When Memory training has to adapt for a flaw ~ which us why IOL is higher
> Then you clearly have an issue
> Not confirming stability, confuses theories
> 
> Between 28-28 & 26-26 is another story
> But missmatching clearly shows issues
> Considering i have this on B450 & X570 Tomahawk
> It's not a board engineers flaw, and traces are correctly placed/made


Trust me I've tried _everything_ now including working with tRDWR lol.

At 3800 my findings are consistent, tCL 14 = 26/26 at 2T, 28/26 at 1T. tCL 15 = 28/26 at 2T, 26/26 at 1T. tCL 16 = 26/26 at 2T, 28/26 at 1T. If you remember last night I even went down to one stick only and found that if running that stick in B1/A1 I can get it to 26, but if there is two sticks A1 goes to 28.

3667 is the highest I can go on frequency before I start to see the behaviour above.

Just waiting on my new set of memory just now to see if it behaves the same or not.


----------



## Veii

rossi594 said:


> and that vddg and vddp have to be at least 50mv lower than vsoc.


40mV
42 set, 40 get
50mV was matisse. Rather 48mV


----------



## Veii

Audioboxer said:


> At 3800 my findings are consistent


Try 3833 2:2:1 mode 
Consistent is an issue 

Not random memory training, but consistent issue
Timing or voltage related


----------



## Audioboxer

Veii said:


> Try 3833 2:2:1 mode
> Consistent is an issue
> 
> Not random memory training, but consistent issue
> Timing or voltage related


Forgive me for the ignorance but what is 2:2:1 mode? Leaving FCLK at 1900?


----------



## MrHoof

So I tested a bit aswell, when i started trying T1 i was using 43.6ohm procODT and needed VDDP of 0.950v for 26/26 lower would desync as I posted like a week ago. Now with procODT 32ohm VDDP 0.9v will get me 26/26. Same RTT and DrvStr for both tests.

edit: 28/26 now happens VDDP at 0.875v.


----------



## sonixmon

sonixmon said:


> I consistently get 28/28, in all my screenshots of settings I have tried I only noticed 26 once and it was with GDM on vs 1T Setup 56 0 0. Also I almost always have run 56 0 0, I don't know if that is better or not. I really have not done any testing between 56, 56, 56 and 56, 0, 0 but between GDM on and 1T 56 my results are better with the latter.
> 
> Should I be concerned about 28 vs 26? Could be my secondary timings as I really am novice and mostly have copied others settings (who have similar ram) and see what is stable and works best for my setup. This is what I am currently running and is fine below 42c on ram. I call it my 3800Fast42Max profile! I also have a 3800Max45 profile for hotter times of year. LOL
> 
> Also I have not ever tested 2T for comparison since most have commented that 1T with setup has been better for them.
> 
> View attachment 2525124


So I had some time for quick testing and had interesting results (partially my fault I am sure). I imagine with such tight timings any major change will need recalibration (which I did not have time to do).

TLDR: Same timings 2T results in tPHYRDL 26 (matching), slightly slower scores on AIDA64, .1 ns lower latency and instability. Also wierd zentimings issue a BSOD and errors on DRAM Calc membench.

Details, I left timings the same as above and switched to 2T no setup times. Booted PC and noticed slower load of task items (placebo effect?/no). Ran Zentimings and confirmed 26/26. Closed all apps and services with my script. Ran AIDA64 and noticed slightly slower scores and .1 ns lower latency. Second AIDA run BSOD at start! Booted back up and rain again, almost identical results to first run. Switched to DRAM Calc membench and on easy scores slightly better, ran default test and 1/2 through errors kicked in and had to stop test. Noticed slight fclk drop too (1899.8 mhz). Checked Zentimings again and when switching between DIMMS thought I saw numbers change, did 2-3 times and caught the below screenshot with Zeros! TCL 0 Woohoo!  Clearly not stable.

For now I will stick with my tuned 1T setup 56 since it has the best results and of course is stable. I may try for best 2T settings when I get a chance but not sure when that might be.

Also hoping for some future flck improvements and getting to 2000 then going for TCL 15-16 but that is a wait and see.



Spoiler: 2T results



These are the ones I managed to get (before Zentimings in post above) 2nd one below is the glitch!






















Before:


----------



## Audioboxer

MrHoof said:


> So I tested a bit aswell, when i started trying T1 i was using 43.6ohm procODT and needed VDDP of 0.950v for 26/26 lower would desync as I posted like a week ago. Now with procODT 32ohm VDDP 0.9v will get me 26/26. Same RTT and DrvStr for both tests.
> 
> edit: 28/26 now happens VDDP at 0.875v.


I tried messing with ProcODT and VDDP and no luck. I'm going to give up for now though as wasting more time on this set of memory is pointless. My new set should be here by Sunday and then it will be back to square 1 to test it and at this point I'll have another set of memory to have a look at with 28 and 26 behaviour.

I've established my biggest issue is the mismatch, 28/26. It wouldn't bother me as much if it was simply running 28/28.


----------



## ManniX-ITA

Today I have finally removed the awful Ripjaws heatsinks and replaced them with the EKWB Monarch modules.

I really hope the intent of G.Skill is to facilitate people that are going to remove the heatsinks to use the sticks with a waterblock.
Cause my Ripjaws heatsinks were so badly mounted that it was really criminal 

But if your plan is to remove them, wow! It's great!
Took me less than 20 minutes to remove the HS and clean the ICs. Amazing.
In comparison with the TridentZ RGB kit it took more than 1 hours of hard work.



Spoiler: These are the two DIMMs just after the removal:
























The heatsink doesn't have a clip holding the 2 sides together.
Each side is just glued to the ICs.
And as you can see it was really in contact only on the 2 ICs on the outer sides (or only one!)

I was able to remove the big parts of the glue in minutes with the same plastic spatula I used to remove the HS.
Then just nails and a bit of TIM cleaner; the glue used on the TeridentZ was hard and sticky and covering all the ICs.
Here this awful job came out to be a big advantage.

As you can see both DIMMs have pencil markings; seems the manual binning is real.

Here's how I applied the thermal paste, the trick used for the VRAM on 3080/3090.
It didn't go as I planned of course 











The pink paste is Kyonaut Extreme, it's the first time I used it.
If I knew, I'd have used another paste...
It's very jelly and seems like melted cheese, making this long filaments that are ending up everywhere.

But it's ok, at the end it does the job.
In theory the paste should fill the empty spaces between the ICs and maybe a very thin layer on the IC.
Hard to do both with the Kryo Extreme; trying to remove the excess on the ICs would remove also the paste filling the spaces.
More important on a GPU card that is thin cause otherwise it could change then final thickness and cause contact issues with the GPU die.

Here's there's no GPU 
What matters is the block heatsinks can properly close.
Since the thermal pad was a bit longer than the 4 ICs, I've spat also a bit on the sides. More contact surface between the pad and the PCB.
The pads are EC360 Platinum, 16.6 W/mK. Probably overkill but I had those available.
In the center there's a blob of thermal putty, 10 W/mK; it's an almost solid paste. Adds contact between the PCB and the HS.

The result is that now I can run the tCL15 profile that was overheating at 61c in less than 2 TM5 cycles.
Thermal equilibrium around 6-7 cycles at 56.2.c which is just 0.1c more than the tCL 16 profile I could run before.
More than 5c difference, probably around 10c.

This is the profile right now, still have to make some adjustments. 
Not happy with it. But hey, below 53ns more than above.


----------



## Hale59

@ManniX-ITA , I would like to know how you removed the Ripjaws heatsinks.


----------



## Audioboxer

ManniX-ITA said:


> Today I have finally removed the awful Ripjaws heatsinks and replaced them with the EKWB Monarch modules.
> 
> I really hope the intent of G.Skill is to facilitate people that are going to remove the heatsinks to use the sticks with a waterblock.
> Cause my Ripjaws heatsinks were so badly mounted that it was really criminal
> 
> But if your plan is to remove them, wow! It's great!
> Took me less than 20 minutes to remove the HS and clean the ICs. Amazing.
> In comparison with the TridentZ RGB kit it took more than 1 hours of hard work.
> 
> 
> 
> Spoiler: These are the two DIMMs just after the removal:
> 
> 
> 
> 
> View attachment 2525223
> 
> 
> View attachment 2525224
> 
> 
> 
> 
> The heatsink doesn't have a clip holding the 2 sides together.
> Each side is just glued to the ICs.
> And as you can see it was really in contact only on the 2 ICs on the outer sides (or only one!)
> 
> I was able to remove the big parts of the glue in minutes with the same plastic spatula I used to remove the HS.
> Then just nails and a bit of TIM cleaner; the glue used on the TeridentZ was hard and sticky and covering all the ICs.
> Here this awful job came out to be a big advantage.
> 
> As you can see both DIMMs have pencil markings; seems the manual binning is real.
> 
> Here's how I applied the thermal paste, the trick used for the VRAM on 3080/3090.
> It didn't go as I planned of course
> 
> View attachment 2525228
> 
> 
> 
> The pink paste is Kyonaut Extreme, it's the first time I used it.
> If I knew, I'd have used another paste...
> It's very jelly and seems like melted cheese, making this long filaments that are ending up everywhere.
> 
> But it's ok, at the end it does the job.
> In theory the paste should fill the empty spaces between the ICs and maybe a very thin layer on the IC.
> Hard to do both with the Kryo Extreme; trying to remove the excess on the ICs would remove also the paste filling the spaces.
> More important on a GPU card that is thin cause otherwise it could change then final thickness and cause contact issues with the GPU die.
> 
> Here's there's no GPU
> What matters is the block heatsinks can properly close.
> Since the thermal pad was a bit longer than the 4 ICs, I've spat also a bit on the sides. More contact surface between the pad and the PCB.
> The pads are EC360 Platinum, 16.6 W/mK. Probably overkill but I had those available.
> In the center there's a blob of thermal putty, 10 W/mK; it's an almost solid paste. Adds contact between the PCB and the HS.
> 
> The result is that now I can run the tCL15 profile that was overheating at 61c in less than 2 TM5 cycles.
> Thermal equilibrium around 6-7 cycles at 56.2.c which is just 0.1c more than the tCL 16 profile I could run before.
> More than 5c difference, probably around 10c.
> 
> This is the profile right now, still have to make some adjustments.
> Not happy with it. But hey, below 53ns more than above.
> 
> View attachment 2525238
> View attachment 2525239


They really shouldn't be using RipJaws heatsinks on ram binned at 1.55v lmao

What method did you use for removing them, any heating up? Or just wedge a ruler right in there?

That paste looks like a crime scene  I guess if it works, it works. I wasn't going to put any paste on mine, just use thermal pads?


----------



## ManniX-ITA

Hale59 said:


> @ManniX-ITA , I would like to know how you removed the Ripjaws heatsinks.


Easy, so easy 

Lifted on the center, near the pins notch where there are no components, with a plastic pry tool similar to this one below.
It's from toolkit to open mobile phones:










You pluck your finger to keep it a bit lifted, under pressure.
Using the same plier you lift the heatsinks on the outer edges, pushing on the pins.
You have to keep firmly the DIMM.
Cause it's so easy that you could eject it at high speed toward the ceiling...

For the TridentZ it was a martyr.
Took a lot of time and force, had to use the dryer to heat the glue.
With the Ripjaws you wonder how it didn't fell out while it was inside the case burning something else....


----------



## ManniX-ITA

Audioboxer said:


> I wasn't going to put any paste on mine, just use thermal pads?


The thermal paste will increase the cooling efficiency. Up to you!
It's not critical but every degree is welcome to me 

Yes looks criminal but is not.
You have to try yourself the Kryonaut Extreme to understand what I mean


----------



## umea

Am I wrong or does 56.7 still seem really high?


----------



## Audioboxer

umea said:


> Am I wrong or does 56.7 still seem really high?


If there's no active cooling then at 1.57v the B550 Unify X will be tough on the DIMMs seeing as its a 2 DIMM board and two sticks right next to each other will heat each other up.

If there is a fan on that it seems a bit high. I'm at 40 degrees at 1.5v with a fan and stock RipJaws heatsinks. Though to achieve that during TM5 the fan is at 100%.

While changing the heatsinks obviously helps they really benefit from active cooling at over 1.5v.


----------



## Audioboxer

Here is a 4000C14 kit on... an Intel setup. Damn, lol. Haven't really paid attention to Intel memory OCing but I guess this is the one upperhand they still have over AMD for now 

Can anyone give me the ELI5 (explain like I'm 5) to why Ryzen has the relationship with memory coupling it does and possibly also what is AMDs problem with the IF madness? IF holes, some chips booting 2000+, others struggling to go over 1800. Is it a weakness of their design or a consequence of them pushing in other areas that something had to give and it appears to be the... IMC?


----------



## umea

you reminded me that intel exists and i went over to their thread, didn't even know this kit existed, has anyone looked into it? Are you a human? 20% off right now.. seems even better bin than mine (4266 17 18 18 38 vs 4400 with same timings and voltage hmm), 4000 cl 14 seems to be best bin still, but pretty interesting


----------



## umea

Audioboxer said:


> If there's no active cooling then at 1.57v the B550 Unify X will be tough on the DIMMs seeing as its a 2 DIMM board and two sticks right next to each other will heat each other up.
> 
> If there is a fan on that it seems a bit high. I'm at 40 degrees at 1.5v with a fan and stock RipJaws heatsinks. Though to achieve that during TM5 the fan is at 100%.
> 
> While changing the heatsinks obviously helps they really benefit from active cooling at over 1.5v.


honestly i completely forgot that not everyone runs active cooling on their ram... makes sense though, that's around the temp mine reached on ripjaw without active cooling, mine sits around 45c max at 3800c14 with tight timings on tm5 with 120mm fan on it + no heatsinks on, i reckon the copper heatsinks linked earlier will help distribute the heat a lot.. or i hope so at least, remains to be seen.


----------



## Audioboxer

umea said:


> you reminded me that intel exists and i went over to their thread, didn't even know this kit existed, has anyone looked into it? Are you a human? 20% off right now.. seems even better bin than mine (4266 17 18 18 38 vs 4400 with same timings and voltage hmm), 4000 cl 14 seems to be best bin still, but pretty interesting


It should be a better bin, yeah. 4400C17 is roughly 7.77ns and 4266C17 is 7.97ns. But that's a crude calculation and the other primary timings and voltage come into play.

I mean if we go by that simplistic way of looking at ram the 4000C14 kit is literally the lowest sold at 7ns. Hence the price it commands. But there's much more to consider if you ask me than looking at tCL and ram speed.


----------



## umea

Audioboxer said:


> It should be a better bin, yeah. 4400C17 is roughly 7.77ns and 4266C17 is 7.97ns. But that's a crude calculation and the other primary timings and voltage come into play.
> 
> I mean if we go by that simplistic way of looking at ram the 4000C14 kit is literally the lowest sold at 7ns. Hence the price it commands. But there's much more to consider if you ask me than looking at tCL and ram speed.


Yup, for now I'm gonna hold off on buying a new kit and wait to see how yours does + see what next gen CPUs have to offer.


----------



## Audioboxer

umea said:


> Yup, for now I'm gonna hold off on buying a new kit and wait to see how yours does + see what next gen CPUs have to offer.


The more I learn about AMD and memory it seems you very quickly hit diminishing returns and most of the fun seems to be with the Intel boys 

Once you hit 2 CCDs it seems like you've approached the real end game with AMD and that is when you're crossing your fingers for a golden bin of RAM that can hit low timings without putting much stress on the IMC.

Seems if you so much as look at a 5950x IMC funny it folds in on itself and starts spamming error 6.

My memory might be here tomorrow but if not tomorrow, Sunday!


----------



## umea

Audioboxer said:


> The more I learn about AMD and memory it seems you very quickly hit diminishing returns and most of the fun seems to be with the Intel boys
> 
> Once you hit 2 CCDs it seems like you've approached the real end game with AMD and that is when you're crossing your fingers for a golden bin of RAM that can hit low timings without putting much stress on the IMC.
> 
> Seems if you so much as look at a 5950x IMC funny it folds in on itself and starts spamming error 6.
> 
> My memory might be here tomorrow but if not tomorrow, Sunday!


We have the same experience, my 5900x IMC seems pretty average so unfortunately I can't do anything too fun.. My inner competitive nature wants to get a 5600x and some SR to try to see how far I can push it


----------



## XPEHOPE3

Steve_ said:


> I've seen a few comments suggesting the full 6.5 hours of testing is only required to ensure memory temps have stabilised.


Then you haven't seen this comment of mine.


Steve_ said:


> Is this an indication that I'm already pushing timings too hard and that GDM is fudging things?


If GDM is on, it's fudging whatever results you have  Also as long as you are not stable enough for all your needs, I'd say you actually don't have any "results". I had lots of GDM-on Aida64 screens for 3800-14 setup, but never managed to get it 1usmus_v3_25-stable. Then I switched to GDM off + 2T and disregarded all my previous work. All it gave me was at best "experience"  Basically you never know for sure what your changes actually do if you have GDM on.


Steve_ said:


> For info, I've never managed to boot 1T GDM off even with _really _loose timings.


I was able to post with these timings. But none of them were stable. Also you might need to look at memory training settings.


----------



## umea

Random question, if someone were dead set on getting 64gb of ram, would yall suggest 4x16 or 2x32?


----------



## Mach3.2

umea said:


> Random question, if someone were dead set on getting 64gb of ram, would yall suggest 4x16 or 2x32?


I'll probably get me a kit of 2*32GB Crucial Ballistix, though I'm not sure how well would dual rank Micron Rev. B overclock.

There's not much headroom to tighten timings for single rank Micron Rev. B, since these ICs do better when you push the frequency. Not sure how this info would extrapolate to dual rank sticks.


----------



## umea

I just gave an alright kit, someone was asking for suggestiosn, don't think they're into overclocking or anything so I just gave them something that'll run at XMP settings lol. Hard not to nerd out and try to suggest them some B-Die but I forget sometimes that not everyone is as crazy as us


----------



## rossi594

umea said:


> Random question, if someone were dead set on getting 64gb of ram, would yall suggest 4x16 or 2x32?


I would adjust my expectations. Most of those will run Quad Rank which is really really hard on the memory controller. So there won't be a need to buy kits that run 3600+ in my opp.

From there it depends on your board. 2 kits will be cheaper but you better make sure you get the same ics but your board has to be up to it. If not spend more on 2 dimms. Maybe take a look at hynix djrs or samsung d die, both are much easier on the memory controller and should allow you to run higher speeds.


----------



## Bal3Wolf

Mach3.2 said:


> I'll probably get me a kit of 2*32GB Crucial Ballistix, though I'm not sure how well would dual rank Micron Rev. B overclock.
> 
> There's not much headroom to tighten timings for single rank Micron Rev. B, since these ICs do better when you push the frequency. Not sure how this info would extrapolate to dual rank sticks.


i have 2 kits of Crucial Ballistix 32gig ddr 3600 overclocked to 3800 but heres wierd thing i just noticed my orginal kit i got last year was dual rank but the kit i got this year is single rank same ram model but they changed it. They both overclock to 3800 and run pretty much same timings these are micron e chips.


----------



## Skull_Angel

Update:
After reading more about the training issues the last several pages and digging for more info, I've evaluated my process for pushing fclk previously and have been successful in early testing. Currently stable up to 1900 fclk w/ no errors, but no luck pushing further. This got me excited and I've been working dirty to quickly optimize timings with good results.

Current results showing promise with no error reporting or WHEA.


----------



## Bal3Wolf

working on my memory still im running 4 sticks of Crucial Ballistix 3600 MHz DDR4 DRAM Desktop Gaming Memory Kit 32GB (16GBx2) CL16 BL2K16G36C16U4W (WHITE) overclocked to 3800mhz with timings in the screen shot im running out of things i can tighten i think any suggestions trc wont tighten down without errors or fail to post. What i found out tonight is my orginal kit i got last year is dual ranks but kit i got this month to give me 64gigs of memory is single ranks.
Are you a human?


----------



## Mach3.2

Bal3Wolf said:


> i have 2 kits of Crucial Ballistix 32gig ddr 3600 overclocked to 3800 but heres wierd thing i just noticed my orginal kit i got last year was dual rank but the kit i got this year is single rank same ram model but they changed it. They both overclock to 3800 and run pretty much same timings these are micron e chips.


Older 2*16GB Crucial Ballistix(pre 2021?) are mostly dual rank 8Gb Rev. E ICs, they recently changed it to single rank 16Gb Rev. B ICs. I'm running my single rank 2*16GB Rev. B kit at 3733MHz, 15-17-16-32.

Online ramblings basically say 16GB Rev. B behave like slightly better binned 8Gb Rev. Es.


----------



## Mach3.2

Bal3Wolf said:


> working on my memory still im running 4 sticks of Crucial Ballistix 3600 MHz DDR4 DRAM Desktop Gaming Memory Kit 32GB (16GBx2) CL16 BL2K16G36C16U4W (WHITE) overclocked to 3800mhz with timings in the screen shot im running out of things i can tighten i think any suggestions trc wont tighten down without errors or fail to post. What i found out tonight is my orginal kit i got last year is dual ranks but kit i got this month to give me 64gigs of memory is single ranks.
> Are you a human?
> 
> View attachment 2525277


Primaries seem exactly like what I expect these sticks to run, they don't really want to be tightened. tRFC can probably be ran at 290ns(551-409-252).


----------



## mongoled

Apparently the Viper Steel thing is a mistake



Currently at super low price (relatively speaking) on Amazon.de


----------



## Leoyzen

Hello， everyone.
Learning a lot from this forum.And I've got 2*16GB Crucial Ballistix 3600C18 kits, which shows 20/21 and single b-die, I believe it is Micron Rev.B C9BLJ(4400mhz).
After something I've successfully push my kits to 3800-C15-1T without GDM. And now I can't push it any more (push down tRC/tCL or SCL). I can boot with 3800-C14-1T but got tons of errors in TM5.
I'd like some advices from someone to going further(3800-C14-1T, or 5000-C18-1T)

Much appreciate.

3800-C14-1T:
I've test various procODT(28,30,32,34,36)/RTT(7-0-5,7-0-6)/CAD_Bus(20-20-20-20,40-20-30-20,60-20-40-20,60-20-30-20), none of them brings me stable( post, but got tons of errors in TM5).


4600(FCLK 1900)-C18-2T:
I can post and pass TM5, but every time when rebooting it got cold reboot(motherboard shutdown then power on), sometimes it failed to boot when the mem is in high temperature (46~50).
using various procODT/RTT/CAD_Bus too, can't see differences.


5000/4800(fclk 1900)-C18-2T:
can't event post....have to clear cmos.
using various procODT/RTT/CAD_Bus too.








.


----------



## Steve_

XPEHOPE3 said:


> Then you haven't seen this comment of mine.
> If GDM is on, it's fudging whatever results you have  Also as long as you are not stable enough for all your needs, I'd say you actually don't have any "results". I had lots of GDM-on Aida64 screens for 3800-14 setup, but never managed to get it 1usmus_v3_25-stable. Then I switched to GDM off + 2T and disregarded all my previous work. All it gave me was at best "experience"  Basically you never know for sure what your changes actually do if you have GDM on.
> I was able to post with these timings. But none of them were stable. Also you might need to look at memory training settings.


Thanks again for your reply. I've still not done full stability tests as there's a few other avenues I want to look at yet. But interestingly, I switched to 2T (GDM off) and your other timing suggestions and that's given me something in Aida that's as good as or even slightly better than my older 1T GDM on. (Although agree that without stability tests, these are not proper results!!) But I'll definitely be sticking with GDM off from now on based on this info and the quick experiments I've run.

Because there's almost no air gap between the memory sticks when running 4 sticks, my cooling solution isn't as effective as it was for just 2 sticks. This is something I'll look to improve but that's a slightly more medium term project. I can stabilise my ram temps at under 45 deg (about 23 ambient) during memory tests but at the expense of quite a lot of fan noise with my current layout. 'Normal' workloads are more like 43deg with much more managable noise levels. However, this will approach 50deg in the summer so I need to improve this.
One thing I've noticed (still trying to catch up on all the 600+ pages of good info here!!!) is that I might be making life difficult for myself by running RttPark at RZQ/1.
I've not been able to post at anything other than that so far but have been struggling to find a good 'guide' on how to tweak other settings when trying to move away from this. I'm sure the info is in this thread somewhere, I've just not found it yet!

Hence why I've not bothered to stability test yet as if I'm going to be starting again with all the timings when trying to get something other than RttPark = RZQ/1, any testing now would be a bit of a waste of time.

Again, thanks for your help


----------



## XPEHOPE3

Steve_ said:


> Because there's almost no air gap between the memory sticks when running 4 sticks, my cooling solution isn't as effective as it was for just 2 sticks.


My solution for this. 😎


Steve_ said:


> I might be making life difficult for myself by running RttPark at RZQ/1


I was only able to post RttPark /2 while varying procODT and only on certain AGESAs (1.2.0.2b,c and .3). As you can see from my results, /1 enough for at least 3866-16. But of course I'd be interested in results of your rttpark attempts😅


----------



## Audioboxer

My 2016 3200C14 kit couldn't post anything other than RttPark1 above 3400 lol. Not sure if that was simply bad luck, how b-dies might have been back in 2016 or something else. But it was attempted across two motherboards, one X570, one B550 and it showed the same behaviour.

I did briefly read elsewhere that some of the older b-die bins were being sought out, but I dunno if that was just in relation to a long extinct 3600 15-15-15-15 bin or something. I didn't pay too much attention when glancing over it. On paper I'd have thought newer 3200C14 bins would be the ones to chase due to refined silicon production, but who knows lol. All I know is over 3400 that kit demanded RttPark 1.


----------



## Audioboxer

Oh boy, @Veii going to need a lot of help figuring this mess out...

Posting above about RttPark 1 inspired me to dig out my 3200C14 set which I still haven't sold on yet, it's been lying in a drawer for over a month now. I couldn't remember how tPHYRDL behaved on it, because when I was tweaking it I was just starting my b-die journey in this topic and I was pretty lacking in knowledge. Anyway, I plugged it in, left everything on auto other than 3800/1900 and 1.5v










26/26 at 1T on tCL14, damn, my other set was doing 28/26.










26/26 at 2T on tCL14










For the heck of it I then decided lets try 6/3/3, so RttPark 3 and... it boots. Now @mongoled can tell you all I could not get this ram booting RttPark 3. At all. Um, hello, what is going on here?!










So I decided to start plugging in some of my tCL15 profile and bam, a change to 28/26.










Back to most on auto and it was 26/26 again.










I then decided to try and one by one find out what was causing the change to 28/26. Not ProcODT, it was fine at 34.3. Not tRAS/tRC changing and the finally, VDDP. 0.9v 28/26, 0.95v, 28/26, 0.975v, 28/26, 1.0v 28/26 and finally 1.05v and it changes back to 26/26.

Isn't 1.05v on VDDP pretty damn high? 

My bigger headache is trying auto settings on my 3600C14 set still results in 28/26 at 3800 on most configurations. So I really have no idea what is going on. And to make matters worse now I don't know why this RAM is now booting RttPark 3 

Talk about opening pandoras box on a Saturday.


----------



## Veii

Audioboxer said:


> I then decided to try and one by one find out what was causing the change to 28/26. Not ProcODT, it was fine at 34.3. Not tRAS/tRC changing and the finally, VDDP. 0.9v 28/26, 0.95v, 28/26, 0.975v, 28/26, 1.0v 28/26 and finally 1.05v and it changes back to 26/26.
> 
> Isn't 1.05v on VDDP pretty damn high?
> 
> My bigger headache is trying auto settings on my 3600C14 set still results in 28/26 at 3800 on most configurations. So I really have no idea what is going on. And to make matters worse now I don't know why this RAM is now booting RttPark 3
> 
> Talk about opening pandoras box on a Saturday.


Haha,
Well
Idk how to phrase it

Don't want to point a "i told you" line for both parts "lack of cLDO_VDDP" "bad powering"
I'm happy you figured it out, but the end result remains sadly,

On your ~#28 examples , the only thing you keep using is he 633 + 40-20-30-20 combination
Even when MSI should not be the target here for the issue ~ it keeps repeating across too many of their boards, down to B450
They work great for me, but all theory aside ~ at this point i wonder if IOL just increased as powering was "too strong & noisy"
Makes me really wonder why it performs much better on 20-20-20-20 for you
Wonder if PCB (dimms) are that sensitive

Else typical analysis would be,
"procODT is "high" , soo minimum working cLDO_VDDP is higher"
Or,
"procODT is "low", VDDP from IMC to Slots are low, powering is too low as RTT's a "too weak"
in later case, pushing just one of the options should have been enough

Give the auto trick a try, but AMD OVERCLOCKING enforce 860mV VDDP on RTT 7-3-3, 30-20-24-24 CAD_BUS
Maybe CAD_BUS is too strong here, but you can give it a try

Also 1050mV cLDO_VDDP is "just enough"
slightly higher is dangerous (beyond 1100 i wouldn't want to go), well already is dangerous as SOC skyrockets that way up if let on autocorrection without uncoreOC mode enabled & APBDIS 1 = P0 state
As for the VDDG CCD ~ just y-cruncher test that one. It should fail quite fast on BBP, SFT, N64, VST, C17
* back home


----------



## KedarWolf

Here is an old stand-by memory test I ran overnight.

I had to change a few voltages etc. for Windows 11 from the Dev Channel.



















If anyone wants to try it, get MemTest Pro 7.0, put the right script from the attached file in your MemTest Pro folder with the MTPclassic.exe in it. 

Install AutoHotkey, right-click on the script and Run Script.

In the attached file rename .txt to .zip.

It runs MemTest Pro spaced evenly and each instance on its own separate thread, like the first MemTest on thread 1, the second on thread 2 etc., the best way to run MemTest Pro. 

You can get MemTest Pro by donation now, but I'd suggest donating $5 or higher, it's really worth it, and it'll help the program devs.


----------



## Audioboxer

Veii said:


> Haha,
> Well
> Idk how to phrase it
> 
> Don't want to point a "i told you" line for both parts "lack of cLDO_VDDP" "bad powering"
> I'm happy you figured it out, but the end result remains sadly,
> 
> On your ~#28 examples , the only thing you keep using is he 633 + 40-20-30-20 combination
> Even when MSI should not be the target here for the issue ~ it keeps repeating across too many of their boards, down to B450
> They work great for me, but all theory aside ~ at this point i wonder if IOL just increased as powering was "too strong & noisy"
> Makes me really wonder why it performs much better on 20-20-20-20 for you
> Wonder if PCB (dimms) are that sensitive
> 
> Else typical analysis would be,
> "procODT is "high" , soo minimum working cLDO_VDDP is higher"
> Or,
> "procODT is "low", VDDP from IMC to Slots are low, powering is too low as RTT's a "too weak"
> in later case, pushing just one of the options should have been enough
> 
> Give the auto trick a try, but AMD OVERCLOCKING enforce 860mV VDDP on RTT 7-3-3, 30-20-24-24 CAD_BUS
> Maybe CAD_BUS is too strong here, but you can give it a try
> 
> Also 1050mV cLDO_VDDP is "just enough"
> slightly higher is dangerous (beyond 1100 i wouldn't want to go), well already is dangerous as SOC skyrockets that way up if let on autocorrection without uncoreOC mode enabled & APBDIS 1 = P0 state
> As for the VDDG CCD ~ just y-cruncher test that one. It should fail quite fast on BBP, SFT, N64, VST, C17
> * back home


My issue wasn't not listening or not believing you Veii (I trust you on everything memory!), it's that my 3600C14 set doesn't even behave on the basis of the above, here it is with VDDP as high as the 3200 set and it's still 28










That is everything default/auto apart from 3800, tCL15 and 2T.

So I still can't seem to figure out the combination of what causes 28/26 on this memory lol.

My 4000C14 set is 100% coming tomorrow, so I guess I'll see what it does  Three sets of b-die now and I bet they all behave differently with tPHYRDL lol.


----------



## AmateurRanger

I know this might have been asked a million times but I tried my best using thread searching but no vail..

Any insight on error meanings with [email protected]? Especially test2, seems to always get rare errors out of this test, is it temperature related as it tends to happen in the middle of late stage of the test where my RAM is 60c or higher

Many thanks!


----------



## Bal3Wolf

Mach3.2 said:


> Primaries seem exactly like what I expect these sticks to run, they don't really want to be tightened. tRFC can probably be ran at 290ns(551-409-252).


yea i tried those and 295ns no go.


----------



## umea

AmateurRanger said:


> I know this might have been asked a million times but I tried my best using thread searching but no vail..
> 
> Any insight on error meanings with [email protected]? Especially test2, seems to always get rare errors out of this test, is it temperature related as it tends to happen in the middle of late stage of the test where my RAM is 60c or higher
> 
> Many thanks!


There is not a complete key to what the rrors mean specifically with Anta's config, hence why if you use it you need to go slowly and change one setting at a time. Either way, 60c is high, my ram starts to error out past 45 degrees (B die is very temp sensitive), toss a fan onto it and see if that fixes it.


----------



## umeng2002

Just a reminder that curve optimizer negative offset will affect RAM stability, in Karhu at least. I was messing with my RAM OC and it would sometimes fail at 2000% coverage, sometimes at 300% after changing my curve off set. I reduced the negative offset and it passed Karhu to at least 10,000%. With the same memory timings, -25 CO, Karhu failed at 300%. -20 CO, Karhu failed at 1400% or 2200%. CO at -15, Karhu passed to at least 10,000%.

Just an FYI.


----------



## XPEHOPE3

Audioboxer said:


> And to make matters worse now I don't know why this RAM is now booting RttPark 3


Haven't you changed BIOS since you tried last time? 1.2.0.2a->b or b->c had some changes allowing me to boot /2 IIRC.


----------



## Skull_Angel

umeng2002 said:


> Just a reminder that curve optimizer negative offset will affect RAM stability, in Karhu at least. I was messing with my RAM OC and it would sometimes fail at 2000% coverage, sometimes at 300% after changing my curve off set. I reduced the negative offset and it passed Karhu to at least 10,000%. With the same memory timings, -25 CO, Karhu failed at 300%. -20 CO, Karhu failed at 1400% or 2200%. CO at -15, Karhu passed to at least 10,000%.
> 
> Just an FYI.
> 
> View attachment 2525365


Is that with an all-core or per-core offset? It may just be one or a few cores effecting stability if a stronger all-core offset didn't show signs previously; curve optomizer is kind of tough to test to begin with since even using core-cycler may not show low-load instability without days worth of testing. Due to it being equal to under-volting, I haven't gotten that far with tuning yet, but under-volting is normally best saved as the last step to help reduce variables.

edit: @Veii are there other lower steps for tRFC calculations? I'm currently running tRC*7 (336) using your calculator (3800, tCL 16, tRC 48), tRC*6 shows some instability and I'm not sure if it's because it doesn't sync-up with tRTP 8 well or another setting I'm overlooking. Or am I just reaching the limit of what 2x16Gb dual-rank should be able to reasonably handle?


----------



## umeng2002

It's all core. I haven't had time to dial in per core offsets.


----------



## Veii

Skull_Angel said:


> edit: @Veii are there other lower steps for tRFC calculations? I'm currently running tRC*7 (336) using your calculator (3800, tCL 16, tRC 48), tRC*6 shows some instability and I'm not sure if it's because it doesn't sync-up with tRTP 8 well or another setting I'm overlooking. Or am I just reaching the limit of what 2x16Gb dual-rank should be able to reasonably handle?


Not many.
I used a discharge prediction for it ~ which is not perfect but higher than average and more accurate then full-digit ns values
(i can use this accuracy for other calculations like tWR or tRTP)

If you want to make it better, you'd need to know how to calculate tSTAG and likely do it differently. Do the math tREFI & tMAW.tMAC based
Only the later we have access to, but it would require an education about page sizes by ICs, and capacity amount

Soo doing it this way, and trying to figure out which pattern of tBURST is the most effective for performance (variable), will make things many times more harder
This old flawed formula works so far ~ even when the anchor for it was just tRC as a "fixed has to elapse" delay
Early it was tCL, but while voltage variable ~ it's too PCB variable.
tRC was a good option to use as anchor,as it requires enought provided tRP and enough provided tRTP - to make consistent tRAS.

tRAS has wiggle room up to exploit method or slower timings method ((tRCD *2)+ maybe tCCD_L for stability)
Soo it remained tRC as typical anchor. Logically more voltage, lower tRP , lower tRC as a result, lower always stable tRFC
Fitts all nicely together, soo i have no intention to change anchor for math prediction yet ~ even when math looks extremely simple.

Dual Rank, and different IC sizes other than 1024mb cause issues on mini calculator.
(It misses formula's for it & i don't want to steal community made works from bellow linked sheet)
Rev.E especially and likely Rev.B - need to double it. *11, *12 and so on
nothing uncommon ~ but it doesn't break the ruleset really. It's just these ICs having their own higher range. Undefined by the reason why Rev.E needs ~270+ns or many Hynix +300ns

This is the other option (community project), but the sheet is close to always broken:
Test locked sheet , cloning it can work out ~ or requesting access for it








Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com




0.7b ~ repaired the 4 copy's again, but only a matter of days till it's broken again.
Usually history shows, children at 7-7:10AM wake up and do nonsense on it. Rec to copy it ~ in case it get's broken again


----------



## Skull_Angel

Veii said:


> Not many.
> I used a discharge prediction for it ~ which is not perfect but higher than average and more accurate then full-digit ns values
> (i can use this accuracy for other calculations like tWR or tRTP)
> 
> If you want to make it better, you'd need to know how to calculate tSTAG and likely do it differently. Do the math tREFI & tMAW.tMAC based
> Only the later we have access to, but it would require an education about page sizes by ICs, and capacity amount
> 
> Soo doing it this way, and trying to figure out which pattern of tBURST is the most effective for performance (variable), will make things many times more harder
> This old flawed formula works so far ~ even when the anchor for it was just tRC as a "fixed has to elapse" delay
> Early it was tCL, but while voltage variable ~ it's too PCB variable.
> tRC was a good option to use as anchor,as it requires enought provided tRP and enough provided tRTP - to make consistent tRAS.
> 
> tRAS has wiggle room up to exploit method or slower timings method ((tRCD *2)+ maybe tCCD_L for stability)
> Soo it remained tRC as typical anchor. Logically more voltage, lower tRP , lower tRC as a result, lower always stable tRFC
> Fitts all nicely together, soo i have no intention to change anchor for math prediction yet ~ even when math looks extremely simple.
> 
> Dual Rank, and different IC sizes other than 1024mb cause issues on mini calculator.
> (It misses formula's for it & i don't want to steal community made works from bellow linked sheet)
> Rev.E especially and likely Rev.B - need to double it. *11, *12 and so on
> nothing uncommon ~ but it doesn't break the ruleset really. It's just these ICs having their own higher range. Undefined by the reason why Rev.E needs ~270+ns or many Hynix +300ns
> 
> This is the other option (community project), but the sheet is close to always broken:
> Test locked sheet , cloning it can work out ~ or requesting access for it
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com


Thanks for your input. I think I'm beginning to understand teh ideas behind some of these relationships, but that does seem like more work than I'm willing to dig into to understand one timing.

As far as testing is going, this kit seems to be having no problem with tRFC 336 despite being RC rev.B; I guess that just further confirms the strengths of Samsung B-die, but my testing may not have been through enough yet. I'll keep a close eye on results especially when undervoting due to your info though, thanks again.


----------



## rossi594

Taraquin said:


> View attachment 2525164
> 
> My B-die has a terrible bin, yours can probably get away with better timings


Tryed it. Had to grab my cmos reset screwdriver and bend over early in the morning. Doesn't even post. Maybe it's my fault because I started on the same voltages and set ProcODT to 40 Ohms (Buildzoid recommended that for the Gigabyte 6 Layer Boards) and copied your other terminations.

The gigabyte saving profiles to hdd / usb is ****. Does save some voltages but no timings. Maybe I have to backroll my uefi just to copy my old timings ... so not fun.
I will wire up a button to the cmos reset when I install the water cooling loop.

Everytime I tell myself no you do not flash the bios if it doesn't fix the wheas. It's not worth it starting all over every few weeks.


----------



## Bal3Wolf

rossi594 said:


> Tryed it. Had to grab my cmos reset screwdriver and bend over early in the morning. Doesn't even post. Maybe it's my fault because I started on the same voltages and set ProcODT to 40 Ohms (Buildzoid recommended that for the Gigabyte 6 Layer Boards) and copied your other terminations.
> 
> The gigabyte saving profiles to hdd / usb is ****. Does save some voltages but no timings. Maybe I have to backroll my uefi just to copy my old timings ... so not fun.
> I will wire up a button to the cmos reset when I install the water cooling loop.
> 
> Everytime I tell myself no you do not flash the bios if it doesn't fix the wheas. It's not worth it starting all over every few weeks.


off topic a bit i made my own reset cmos switch out of some old push button switches to make ram overclocking so much easier lol.


----------



## Audioboxer

XPEHOPE3 said:


> Haven't you changed BIOS since you tried last time? 1.2.0.2a->b or b->c had some changes allowing me to boot /2 IIRC.


Great point, must be this. It seems it maxes out at booting RttPark 4. I tried the 7/2/5 I've ran before and it wouldn't post.

With everyone talking about CMOS reset one of the best things going from an X570F to a B550 Unify X was a dedicated CMOS reset button on the back of the case! Every mobo needs this lol.


----------



## ManniX-ITA

Audioboxer said:


> With everyone talking about CMOS reset one of the best things going from an X570F to a B550 Unify X was a dedicated CMOS reset button on the back of the case! Every mobo needs this lol.


There's also a 2-pin connector on the board, many boards have it.
Very handy if the back I/O panel is not comfy accessible.
I have a reset switch with an extension cable there:









Ytian 2 Pcs Computer PC Reset SW Taster Power EIN Aus Taste Knopf Schalter Kabel 50cm: Amazon.de: Computer & Zubehör


Ytian 2 Pcs Computer PC Reset SW Taster Power EIN Aus Taste Knopf Schalter Kabel 50cm: Amazon.de: Computer & Zubehör



www.amazon.de





The switch is out on the back toward the top, very handy.


----------



## umea

Bal3Wolf said:


> off topic a bit i made my own reset cmos switch out of some old push button switches to make ram overclocking so much easier lol.


age old trick is rewiring the reset button of your pc to the clear cmos pins


----------



## umea

posted a whole ago but reposting since no one had answers: is it true that ryzens apus often have better IMCs than their CPU counterparts? and if so has anyone tested how the 5700g compares to the 5600x in terms of imc quality?


----------



## ManniX-ITA

umea said:


> posted a whole ago but reposting since no one had answers: is it true that ryzens apus often have better IMCs than their CPU counterparts? and if so has anyone tested how the 5700g compares to the 5600x in terms of imc quality?


APUs have Monolithic die, they are not an MCM (Multi-chip Module).
Therefore no separate cIOD, they are inherently better.
They can easily go to FCLK:MCLK 1:1 up to 2200 MHz and over.


----------



## Luggage

umeng2002 said:


> Just a reminder that curve optimizer negative offset will affect RAM stability, in Karhu at least. I was messing with my RAM OC and it would sometimes fail at 2000% coverage, sometimes at 300% after changing my curve off set. I reduced the negative offset and it passed Karhu to at least 10,000%. With the same memory timings, -25 CO, Karhu failed at 300%. -20 CO, Karhu failed at 1400% or 2200%. CO at -15, Karhu passed to at least 10,000%.
> 
> Just an FYI.
> 
> View attachment 2525365


If mem test passes with lower CO, then CO was not stable.


----------



## rossi594

Luggage said:


> If mem test passes with lower CO, then CO was not stable.


Some boards default to pbo on (My Gigabyte B550 Vision D didn't even let me deactivate it). What is the best way to test pbo stability?


----------



## umea

ManniX-ITA said:


> APUs have Monolithic die, they are not an MCM (Multi-chip Module).
> Therefore no separate cIOD, they are inherently better.
> They can easily go to FCLK:MCLK 1:1 up to 2200 MHz and over.


is latency inherently worse in any way? just thinking out loud, might be fun to test one then


----------



## Luggage

I'm so sorry but I got lost in the threads between stability testing. Any quick pointers for the next step?
With 2T I have to start over from 161616 - not this weekend.
tRCDRD needs way too much voltage at 14
Might work on lowering tRFC but don't know if that's the priority now.
Agesa 1204 so VDDG does not take SET.
Under the red line is black magic - what's the latest on bus timings?













On the PBO side of things, did we find out what the CCA limiter is? With this colder weather ProcHot/THM doesn't trigger (<61C) but PPT || CCA does, even single threaded.



Spoiler


----------



## ManniX-ITA

umea said:


> is latency inherently worse in any way? just thinking out loud, might be fun to test one then


Latency is much better of course and it's a lot of fun tweaking with memory indeed


----------



## umea

ManniX-ITA said:


> Latency is much better of course and it's a lot of fun tweaking with memory indeed


well maybe ill go with that over a 5600x for testing rig, just a bit more expensive. worst case after im done with it i turn it into a minipc or something


----------



## umeng2002

Luggage said:


> If mem test passes with lower CO, then CO was not stable.


As with under volting my 2700X before I got a 5800X, idle/ low load (like a memory test) is what reveals bad under volting if you otherwise pass stressful tests.

With my 2700X it was just computer freezing at idle right when I was about to do something to a program, like click a link in Firefox or open a document. As if the voltage requested wasn't there to turbo up out of sleep, and the cpu just froze.

With curve optimizer, the undervolting is way more intelligent, but I didn't experience any issues until my Karhu RAM test started to fail in odd ways.

I don't know of a good program that will quickly test CPU stability when it's near idle/ low load. Everything is focused on balls to the walls utilization stability.


----------



## ManniX-ITA

umea said:


> well maybe ill go with that over a 5600x for testing rig, just a bit more expensive. worst case after im done with it i turn it into a minipc or something


Of course as pure CPU is quite a bit underperforming respect to the relative non APU counterpart.
But it does have GPU inside which has its value these days.
I'm planning as well a test setup with one of those.


----------



## umeng2002

Remember that they can cut cache sizes and share bandwidth with the iGPU, so an APU might have better memory overclocking, but the CPU performance can be worse.


----------



## ManniX-ITA

Luggage said:


> With 2T I have to start over from 161616 - not this weekend.
> tRCDRD needs way too much voltage at 14
> Might work on lowering tRFC but don't know if that's the priority now.


Looking at the results seems that GDM is heavily correcting.
I would check with tRCD/tRP/tRAS/tRC 16/16/32/48, could be faster.
Would also try SCL at 4/5 instead of 3, try to squeeze tWTR, check tRTP/tWR at 7/14 or 8/16.


----------



## umea

ManniX-ITA said:


> Of course as pure CPU is quite a bit underperforming respect to the relative non APU counterpart.
> But it does have GPU inside which has its value these days.
> I'm planning as well a test setup with one of those.


yup, price to performance as a cpu is not great, but with a gpu inside i could make a tiny box PC out of it when im done and use it as a mini movie machine or something. i also already have an extra b550 itx mobo laying around unused so


----------



## Luggage

umeng2002 said:


> As with under volting my 2700X before I got a 5800X, idle/ low load (like a memory test) is what reveals bad under volting if you otherwise pass stressful tests.
> 
> With my 2700X it was just computer freezing at idle right when I was about to do something to a program, like click a link in Firefox or open a document. As if the voltage requested wasn't there to turbo up out of sleep, and the cpu just froze.
> 
> With curve optimizer, the undervolting is way more intelligent, but I didn't experience any issues until my Karhu RAM test started to fail in odd ways.
> 
> I don't know of a good program that will quickly test CPU stability when it's near idle/ low load. Everything is focused on balls to the walls utilization stability.


I tested with CoreCycler for ages and still crashed out on Blender Benchmark scene Koro and I'm not 100% sure if OOCT Benchmark is stable. it's tricky.


----------



## frantatech

umea said:


> well maybe ill go with that over a 5600x for testing rig, just a bit more expensive. worst case after im done with it i turn it into a minipc or something


happy testing  but be aware it has only PCIe 3.0 and half of the L3 cache.


----------



## Luggage

ManniX-ITA said:


> Looking at the results seems that GDM is heavily correcting.
> I would check with tRCD/tRP/tRAS/tRC 16/16/32/48, could be faster.
> Would also try SCL at 4/5 instead of 3, try to squeeze tWTR, check tRTP/tWR at 7/14 or 8/16.


Hmm, yea basicly the same, lost a bit of copy but latency is more stable around 57


----------



## Audioboxer

Right you, no nonsense with tPHYRDL.


----------



## Taraquin

rossi594 said:


> Tryed it. Had to grab my cmos reset screwdriver and bend over early in the morning. Doesn't even post. Maybe it's my fault because I started on the same voltages and set ProcODT to 40 Ohms (Buildzoid recommended that for the Gigabyte 6 Layer Boards) and copied your other terminations.
> 
> The gigabyte saving profiles to hdd / usb is ****. Does save some voltages but no timings. Maybe I have to backroll my uefi just to copy my old timings ... so not fun.
> I will wire up a button to the cmos reset when I install the water cooling loop.
> 
> Everytime I tell myself no you do not flash the bios if it doesn't fix the wheas. It's not worth it starting all over every few weeks.


ProcODT 40 on those timings boots, but I get errors. 28-34 works fine without errors. How do I know how many layers my board has?


----------



## Mach3.2

Audioboxer said:


> Right you, no nonsense with tPHYRDL.


My Viper Steel kit just got picked up as well, should be here tomorrow night.


----------



## Audioboxer

Mach3.2 said:


> My Viper Steel kit just got picked up as well, should be here tomorrow night.


Good luck to you too!

For an experiment with heatsinks I just tried removing my Trident Z heatsinks from my 3200C14, came off relatively easily. Though I wonder if some of this is to do with them being from 2016 and the glue not being quite as strong. Don't mind taking these off because I'm going to replace the thermal pads and give the sticks to a friend of mine.

Bodes well for easily removing the RipJaws heatsinks for watercooling, seeing as they only cover "half the ram"


----------



## Mach3.2

Audioboxer said:


> Good luck to you too!
> 
> For an experiment with heatsinks I just tried removing my Trident Z heatsinks from my 3200C14, came off relatively easily. Though I wonder if some of this is to do with them being from 2016 and the glue not being quite as strong. Don't mind taking these off because I'm going to replace the thermal pads and give the sticks to a friend of mine.
> 
> Bodes well for easily removing the RipJaws heatsinks for watercooling, seeing as they only cover "half the ram"


But honestly I'm not too sure I have the time and energy to to deal with the new kit, school just started 2 weeks ago. 😵

Hopefully it's not too much of a time sink trying to do 3733 flat 15 1T on the Viper Steel kit. 🌚


----------



## Skull_Angel

I'm likely at the limit of what I want to accomplish. I haven't found any improvements from tightening timings since this earlier post; benchmarks either show lower results or need a substantial voltage bump for stability with little to no gains. If anyone has suggestions I'm open to check it out, but I'm pretty content to move onto undervolting to reign in temps a bit.


----------



## PJVol

umea said:


> yup, price to performance as a cpu is not great, but with a gpu inside i could make a tiny box PC out of it when im done and use it as a mini movie machine or something. i also already have an extra b550 itx mobo laying around unused so


I'd consider 5700G as well, as it's somewhere between 5600X and 5800X in medium/heavy load, closer to 5800X actually, and getting close to 5600X in single-thread.
I've done a couple of tests in the title thread.
More of my benches are here (Vol2008):


AMD APU 5000 серии (Cezanne) информация и опыт пользования. • Конференция Overclockers.ru


----------



## Veii

umea said:


> posted a whole ago but reposting since no one had answers: is it true that ryzens apus often have better IMCs than their CPU counterparts? and if so has anyone tested how the 5700g compares to the 5600x in terms of imc quality?


Unsure about the IMC FW as always ~ soo unsure about next gen IMC (including Zen3D, which we can compare after it's out)
Also where still waiting for the own option to play with it ~ and confirmation about stability,
But technically this could be possible


Spoiler














In general, around 2400 is possible ~ higher depends
1v clDO_VDDP seems to be enough for the IMC to train high MCLK - about SOC safetyness very unsure, but his timings are stable i guess 

Probably the most interesting thing to me, would be the benefits of it ~ still procrastinating
It's clearly running full bandwidth write links & L1 + L2 cache pretty much appear identical as to 1 CCD units
I'm not entirely convinced yet, that it performs slower (and in IPC) ~ even after many youtubers benchmarked it with casual settings

Always wanted one, but didn't expect to get a "broken" Dual CCD 16c Vermeer sample.
Now i can't to sell it away & it got lapped for the trophy set. 

When i get my hands on one ~ i'll compare them
Too many resources link to "it's slower, IPC is slower"
But synthetic results show another picture after 2000+ FCLK. We'll see, can't give a define answer still


umea said:


> well maybe ill go with that over a 5600x for testing rig, just a bit more expensive. worst case after im done with it i turn it into a minipc or something


I'd say, look in the used market for "strange behaving 6 & 8 cores" which are unstable
(likely to be either bronze samples or dual CCD broken units ~ as the V/F curve is messed up for stock operation)
~ as for perf in games (probably 8 core, so you don't have to fight against the 65c hard throttle limit)
Else, sure why not ~ it misses "not casual user" performance metrics and game benchmarks. You surely will have fun with
* saw @PJVol 's post afterwards, good writeup 


ManniX-ITA said:


> I'm planning as well a test setup with one of those.


Looking forward 
Wonder if we can arrange something (test shipping for a week or so to you, from DE to DE)
Also waiting for a weeks-test shipment from DE down to AT


Mach3.2 said:


> Hopefully it's not too much of a time sink trying to do 3733 flat 15 1T on the Viper Steel kit. 🌚


Not an AMD example, but voltage to timings are interesting 


Spoiler: Should be a piece of cake ~ nevertheless if lucky or not












^ credits to madness777 [Twitch]


tRCD 14 is not easy. But 15 should be easy till 4000+


----------



## rossi594

Taraquin said:


> ProcODT 40 on those timings boots, but I get errors. 28-34 works fine without errors. How do I know how many layers my board has?


Usually you pay extra for it, often it's advertised. I am very confident your board has 4 layers.


----------



## ManniX-ITA

Veii said:


> Looking forward
> Wonder if we can arrange something (test shipping for a week or so to you, from DE to DE)


Sure thing 
I'm not sure about the mainboard... thinking about replacing the Unify-X but don't know yet if and with what.
Tempted by the ASUS CH8 Extreme but it's still too expensive and the BIOS kinda sucks...


----------



## rossi594

ManniX-ITA said:


> Sure thing
> I'm not sure about the mainboard... thinking about replacing the Unify-X but don't know yet if and with what.
> Tempted by the ASUS CH8 Extreme but it's still too expensive and the BIOS kinda sucks...


Asus is usally not so strong with memory. If you running 2 dimms you could look at the evga dark. They are moving the soc closer to the pcie slots with the 90° rotation.


----------



## umea

PJVol said:


> I'd consider 5700G as well, as it's somewhere between 5600X and 5800X in medium/heavy load, closer to 5800X actually, and getting close to 5600X in single-thread.
> I've done a couple of tests in the title thread.
> More of my benches are here (Vol2008):
> 
> 
> AMD APU 5000 серии (Cezanne) информация и опыт пользования. • Конференция Overclockers.ru


great write up! thanks a ton, these things are super interesting, will be picking one up soon.


Veii said:


> Unsure about the IMC FW as always ~ soo unsure about next gen IMC (including Zen3D, which we can compare after it's out)
> Also where still waiting for the own option to play with it ~ and confirmation about stability,
> But technically this could be possible
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> In general, around 2400 is possible ~ higher depends
> 1v clDO_VDDP seems to be enough for the IMC to train high MCLK - about SOC safetyness very unsure, but his timings are stable i guess
> 
> Probably the most interesting thing to me, would be the benefits of it ~ still procrastinating
> It's clearly running full bandwidth write links & L1 + L2 cache pretty much appear identical as to 1 CCD units
> I'm not entirely convinced yet, that it performs slower (and in IPC) ~ even after many youtubers benchmarked it with casual settings
> 
> Always wanted one, but didn't expect to get a "broken" Dual CCD 16c Vermeer sample.
> Now i can't to sell it away & it got lapped for the trophy set.
> 
> When i get my hands on one ~ i'll compare them
> Too many resources link to "it's slower, IPC is slower"
> But synthetic results show another picture after 2000+ FCLK. We'll see, can't give a define answer still
> 
> I'd say, look in the used market for "strange behaving 6 & 8 cores" which are unstable
> (likely to be either bronze samples or dual CCD broken units ~ as the V/F curve is messed up for stock operation)
> ~ as for perf in games (probably 8 core, so you don't have to fight against the 65c hard throttle limit)
> Else, sure why not ~ it misses "not casual user" performance metrics and game benchmarks. You surely will have fun with
> * saw @PJVol 's post afterwards, good writeup


alright, you convinced me to grab one  this seems way too fun to try to push. might pick up a SR kit as well and test both that and my DR kit.


----------



## tomzyka

So I finally got my first tCL 13 setting @3733 completely stable:


























I'm sure I can reduce tRDWR to 10 (maybe even 9) but I didn't find a fix for the Karhu errors yet (Both values are TM5 stable). Nevertheless I'm quite happy with the result for now and I think the next steps are lowering tRAS+tRC+tRFC, finding the perfect procODT value and maybe trying to get tRCDRD 13 stable


----------



## Audioboxer

PCB looks to be the same as my 3600C14 set.

Ignore ZenTimings A1 name, for some reason since I had my 3200C14 set installed earlier the naming in ZenTimings is stuck. Didn't change for my 3600C14 either when I put it back in 

Need to get some proper timings put in and test some stability, it's just a frankenstein of my old settings right now lol.

*edit* - On quick messing around it seems my tPHYRDL behaviour is identical lol. Might be a PCB "issue"? My 3200C14 which was manufactured in 2016 is a different PCB than these. Wouldn't surprise me if it's MSI bios jank given that these newer PCBs are likely produced this year.



















My 2016 2x16GB 3200C14 PCB.

Even with the 4000C14 set covered with heatsinks you can see these are not the same PCB.


----------



## MrHoof

I think more a motherboard issue or maybe even memory controller, on my board I never had it get changed to 28 ever with 2x SR dimms but on DR it happens on really low vddp. I am more confused why it so random for you .
edit: nvm your 2016 set is also 2x16


----------



## Audioboxer

MrHoof said:


> I think more a motherboard issue or maybe even memory controller, on my board I never had it get changed to 28 ever with 2x SR dimms but on DR it happens on really low vddp. I am more confused why it so random for you .


The 3200C14 set responds in line with VDDP, these 3600C14 and 4000C14 PCBs literally don't seem to care about VDDP, it's tCL and command rate that are the only things that change them. Though I'll obviously explore more with this 4000C14 set before saying definitively.

Could it be anything to do with the motherboard QVL list is it called? Whether or not MSI have tested this PCB and tuned their BIOS properly for it? Or does it not work like that? Just strange I now have 3 2x16GB sets and the two that are the same PCB display the same behaviour, while the one that is a different PCB seems to behave how I'd describe as "normal".

When I go to watercool I'll get good pics of the PCB of whatever set I'm going to use and hopefully someone can try identify what the hell it is lol. My 4000C14 set doesn't seem to have the extra resistor a poster like 30 pages ago has. They have a Trident Z 4000C14 set.

Might be that the RipJaws set use the same PCB? Speaking of PCBs if anyone can identify my 3200C14 set above that would be cool, just to know! 2016 manufacturing date.

Also, instead of buying all this memory I should probably look next to a new phone. Autofocus is busted on this S20, pictures are always blurry no matter what


----------



## MrHoof

Well so far only @domdtxdissar PCB seems to have a diffrence from the newer 3600+ DR kits, maybe he can make a better pic to see the middle part better. I am rather curious now why there even is a diffrence when there are 2 other 4000cl14 kit pics that dont show it.

On my QVL list the fastest DR kit is 3600 cl17 so i doubt that.


----------



## Audioboxer

MrHoof said:


> Well so far only @domdtxdissar PCB seems to have a diffrence from the newer 3600+ DR kits, maybe he can make a better pic to see the middle part better. I am rather curious now why there even is a diffrence when there are 2 other 4000cl14 kit pics that dont show it.
> 
> On my QVL list the fastest DR kit is 3600 cl17 so i doubt that.


Going to find his pictures again to see if the manufacturing date is listed. My 3600C14 set is July 2021, the 4000C14 set is August 2021 and they both to my eye appear to be the same PCB.

Yeah, I'm just brainstorming as so far all I have is two PCBs the same displaying what seems to be the same behaviour around tPHYRDL and one PCB a lot older, 2016, which seems to behave like most in this topic expect with tPHYRDL. That being when vDDP is too low at higher frequency it will drop to 28. The positive thing about the 2016 PCB is it will happily go to 26/26 at 3800 as long as vDDP is raised.

vDDP from like 0.9v right up to 1.1v seems to make no difference helping on the new PCBs lol. Just doing the whole if your tCL is X and your command rate is Y, I'll either go 26/26 or 28/26 independent of voltage.


----------



## MrHoof

Well now you have atleast the kit out of the equation since they behave the same. I would compare to other people with a unify-x and if they have diffrent results I would look at the CPU.


----------



## Audioboxer

MrHoof said:


> Well now you have atleast the kit out of the equation since they behave the same. I would compare to other people with a unify-x and if they have diffrent results I would look at the CPU.


Problem is hardly anyone seems to have been picking up these 3600C14 or 4000C14 sets. Both were released at the same time but are GSKILLs most expensive bins. Throw in DR as well which is already more unpopular in the OCing world.

To be fair with DDR5 around the corner for a new gen, I don't exactly blame people not rushing out to buy stupidly priced b-die bins at the end of a cycle.

Then when I find someone with either one of these bins it's hoping they have a 5950x, another thing some memory fanatics avoid due to poor IMC 

I guess the first thing is trying to identify the PCB. In the next week or so I will have pictures without heatsinks. I feel better now knowing I've reproduced the behaviour on the same PCB twice and then I've also found out another 2x16GB PCB displays different behaviour.

*edit -*










Did something frowned upon but I decided to _cheat_ and take my 3600C14 set timings, go back to 2T and put tRCDRD to 14. Holding out so far, which is indeed an improvement over the 3600C14 set, it struggled quite a bit with tRCDRD 14 at 3800.

If this passes just goes to show tRCDRD comes down to silicon, and as I've been told a few times, doesn't really scale with voltage.


----------



## MrHoof

1.5v for CL14 thats impressive if it holds up, my kit would do like 10mins and start to error at 1.52v needs 1.54v for stable . There might be a chance you get to CL13.


----------



## Audioboxer

MrHoof said:


> 1.5v for CL14 thats impressive if it holds up, my kit would do like 10mins and start to error at 1.52v needs 1.54v for stable . There might be a chance you get to CL13.


My 3600C14 will do tCL14 at 1.5v, but it kept throwing a hissy fit with tRCDRD at 14 (have to leave it at 15). Hence why in the end I just went flat 15. Well, that and 1T at tCL14 gets me the 28/26 issue lmao. Only tCL15 at 1T results in 26/26.


----------



## Audioboxer

My TM5 above was still running, no errors, but as I'm off to bed soon I wanted to try something slightly different for the full 25










Quick question about DrvStrs, if something will pass at all 20s, is it beneficial to just leave them that low? Due to the weird tPHYRDL behaviour I'd likely just stay at 2T on tCL14. My understanding is the DrvStrs are often used to help with 1T. So if the above was to pass 25 cycles and be y-cruncher stable is there any point in changing from flat 20?


----------



## Audioboxer

lol, I heard you like tCL13 with your 3800. Funny thing for me isn't that this posts/boots, it's that tCL13 displays the exact same behaviour as tCL15 did on my 3600C14 bin.

At 2T it is 28/26, but at 1T it is 26/26.

So, to recap, we have

tCL13 2T = 28/26
tCL13 1T = 26/26

tCL14 2T = 26/26
tCL14 1T = 28/26

tCL15 2T = 28/26
tCL15 1T = 26/26

tCL16 2T = 26/26
tCL16 1T = 28/26

and this is across two PCBs, one rated 3600C14 and the other 4000C14. Well, tCL13 wasn't tried on the 3600C14, but if it even posted on it I guess it'll be the same.

The uneven tCLs are the reverse of the even


----------



## Veii

Audioboxer said:


> Quick question about DrvStrs, if something will pass at all 20s, is it beneficial to just leave them that low? Due to the weird tPHYRDL behaviour I'd likely just stay at 2T on tCL14. My understanding is the DrvStrs are often used to help with 1T. So if the above was to pass 25 cycles and be y-cruncher stable is there any point in changing from flat 20?


*CsOdtDrvStr* is needed for memory training - same as *cLDO_VDDP* (has a connection to RTT_NOM, too much causes post issues same as too much RTT_NOM)
* push one of both strong, or both slightly


Audioboxer said:


> if something will pass at all 20s, is it beneficial to just leave them that low?


If both are fine low, keep them ~ why not.
============================================
*ClkDrvStr* goes together with *ProcODT* & RTTs
*tCKE *goes together with RTT_WR, MCLK & CkeDrvStr
(although the DrvStr has another usage, and is just a sideproduct effect for PDM or Aggressive PDM ~ barely any timings connection)

*tCWL* goes together with tCL, tRDRD_SCL , tRDWR, tRRD_S, tWTR_S (expected to change SG & IOL's (Intel) ~ or tPHY*W*RL + *R*DL)
*tWR* goes together with tRAS, tRTP, Capacity & DIMM-PCB, VDIMM
*tRFC* goes together with tREFI ~ which depends on tSTAG (CPU Arch), tCKE (PDM Part) & tMAW.tMAC (RC_PAGE) + tFAW
*tFAW* plays together with tRRD_L or tRRD_S, tCCD_L (slightly depends on tRC wasted latency (value higher than tRP+tRAS distance))
*tRDRD* & *tWRWR* *DD*'s depend on chipselect by SCL's, on BGS, Powerdown & SETUP Timings

*AddrCmdDrv* - standby & VTT/Voltage stability issues, cold boot issues (higher fixes things, but degrades signal quality)
*CkeDrvStr *~ same thing as above, fully focused on PDM & Standby issue (acts as a heat multiplier, lower = better)
^ keep both as low as possible (MB PCB depended ~ Trace Distance depended)


----------



## Audioboxer

Veii said:


> *CsOdtDrvStr* is needed for memory training - same as cLDO_VDDP (has a connection to RTT_NOM, too much causes post issues same as too much RTT_NOM)
> If both are fine low, keep them ~ why not.
> 
> *ClkDrvStr* goes together with *ProcODT* & RTTs
> *tCKE *goes together with RTT_WR, MCLK & CkeDrvStr (although the DrvStr has another usage, and is just a sideproduct effect for PDM or Aggressive PDM ~ barely any timings connection)
> 
> *tCWL* goes together with tCL, tRDRD_SCL , tRDWR, tRRD_S, tWTR_S (expected to change SG & IOL's (Intel) ~ or tPHY*W*RL + *R*DL)
> *tWR* goes together with tRAS, tRTP, Capacity & DIMM-PCB, VDIMM
> *tRFC* goes together with tREFI ~ which depends on tSTAG (CPU Arch), tCKE & tMAW.tMAC + tFAW (RC_PAGE)
> *tFAW* plays together with tRRD_L or tRRD_S, tCCD_L (slightly depends on tRC wasted latency (value higher than tRP+tRAS distance))
> *tRDRD* & *tWRWR* *DD*'s depend on chipselect by SCL's, on BGS, Powerdown & SETUP Timings
> 
> *AddrCmdDrv* - standby & VTT/Voltage stability issues, cold boot issues (higher fixes things, but degrades signal quality)
> *CkeDrvStr *~ same thing as above, fully focused on PDM & Standby issue (acts as a heat multiplier, lower = better)


Thanks Veii another post of knowledge to be bookmarked. On the basis of heat and because I'm working with 2T just now I'm going to try and see if a 25 TM5 passes with them lower. At tCL14 I'm going to stick with 2T so I have 26/26 tPHYRDL.

What's your thoughts on tCL13? lol










Made it to 4 minutes before errors. Everything is just on auto mind you, so I might have a chance at 3800! Looks like a challenge 










0.01v VDIMM helped a little xD










lol, there it is again, the 26/26 at 1T on an uneven tCL.


----------



## Veii

Audioboxer said:


> Thanks Veii another post of knowledge to be bookmarked. On the basis of heat and because I'm working with 2T just now I'm going to try and see if a 25 TM5 passes with them lower. At tCL14 I'm going to stick with 2T so I have 26/26 tPHYRDL.
> 
> What's your thoughts on tCL13? lol
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Made it to 4 minutes before errors. Everything is just on auto mind you, so I might have a chance at 3800! Looks like a challenge


#9, try to lower tRRD_L delay
Or increase tWRRD , or drop both SD's
Mirror move issue (4mb)

Before doing any of the above, actually change WR to 24 not 26 ~ 26 is wrong to my math








==========================================
Casual tests usually every 5-6 Weeks once, when i go out








^ that's overheating issues "apparently"
Unclear as to why - as my window was even open, but guess something times out.
I can't believe DIMM-PCBs or ICs can degrade 
(#13 & #11's ~ #2 are a sideproduct, maybe something isn't in sync for me ~ but i still point towards CO issues)


Audioboxer said:


> What's your thoughts on tCL13? lol


Set looks normal, tCWL 12 = -1
tRDWR = 7 
DR soo it's 9 or 8 minimum

Whatever you try, tRDWR 12 is too much and hides issues on the last screenshot


----------



## Audioboxer

lol, tRCDRD 13 actually boots, but it's my favourite 666666666666666666 show within like 10 seconds.


----------



## Luggage

@Veii 


Luggage said:


> On the PBO side of things, did we find out what the CCA limiter is? With this colder weather ProcHot/THM doesn't trigger (<61C) but PPT || CCA does, even single threaded.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2525403
> 
> View attachment 2525404


Ignore the zen-timings I've moved on with @ManniX-ITA tips and looking at @Audioboxer similar 3600c14 ripjaws - needed to push soc a bit to get into 2T


----------



## Audioboxer

Luggage said:


> @Veii
> 
> Ignore the zen-timings I've moved on with @ManniX-ITA tips and looking at @Audioboxer similar 3600c14 ripjaws - needed to push soc a bit to get into 2T


Exactly the same memory as me and funny to see you have that same tPHYRDL issue at tCL14 1T. MSI board too. Different CPU though. Its looking to me like this might be an MSI issue!

Anyway, as your ram is exactly the same as mine I'd have worked with GDM disabled and gone with 2T at first.










That was my best running profile. 53.9ns in AIDA64.

Your IMC will be better than mine so you can maybe do better, your latency should/could get lower too as mine will be higher with 2 CCD. I'd be working with GDM disabled though, whatever timings you're aiming for.


----------



## Luggage

Audioboxer said:


> Exactly the same memory as me and funny to see you have that same tPHYRDL issue at tCL14 1T. MSI board too. Different CPU though. Its looking to me like this might be an MSI issue!
> 
> Anyway, as your ram is exactly the same as mine I'd have worked with GDM disabled and gone with 2T at first.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> That was my best running profile. 53.9ns in AIDA64.
> 
> Your IMC will be better than mine so you can maybe do better, your latency should/could get lower too as mine will be higher with 2 CCD. I'd be working with GDM disabled though, whatever timings you're aiming for.


Thank you, this thread is full of gold but it takes a lot of digging to find the nuggets >_<

Trying your settings with 2t first, if it’s not erroring out fast I’ll try 1t over night.


----------



## umea

Luggage said:


> Thank you, this thread is full of gold but it takes a lot of digging to find the nuggets >_<
> 
> Trying your settings with 2t first, if it’s not erroring out fast I’ll try 1t over night.


dig through veii's posts for the most part, they usually answer people's questions and eventually you'll probably gather enough baseline knowledge to try things out yourself


----------



## Veii

Luggage said:


> @Veii


Looks to me like EDC FUSE - that triggers
CCA is mostly EDC dependent, but 175A EDC is a bit low for the Fuse limit
Try to double up that set 175A limit to something 350ish - or try to max it out as 9999999


----------



## Mach3.2

My Viper Steel kit just got in, the thermal tape holding the heatspreaders to the DRAM ICs seem to be laughingly bad, the middle portion of the tape isn't even sticking to the ICs.. 🙃

Anyway I was watching Buildzoid's video on 16GB Rev. B Crucial Ballistix Max sticks and he mentioned that those are on A3 PCBs. The Ballistix Max PCB looked awefully lot like my 3600MHz CL16 Ballistix sticks so that caught my attention. Googling "DDR4 A3 PCB" turned up jack except that I can pay JEDEC money to look at sk hynix's design files for A3 PCB. Just curious if anyone is privy to the difference between A3 and A2 PCB.

Edit: Currently testing 15-15-15-15-28 1T tRFC 140ns, no errors yet 14 minutes in.

Easiest flat 15 1T GDM disabled attempt? 🤣 🤞

Edit2: 15 cycles default 1usmus_v3 config tm5 stable so far, will test for full 25 cycles after my lessons.

















tRDWR and tWRRD is currently on auto, I suppose tRDWR: 9 and tWRRD: 3 are good values to try on this kit?


----------



## mongoled

Mach3.2 said:


> My Viper Steel kit just got in, the thermal tape holding the heatspreaders to the DRAM ICs seem to be laughingly bad, the middle portion of the tape isn't even sticking to the ICs.. 🙃
> 
> Anyway I was watching Buildzoid's video on 16GB Rev. B Crucial Ballistix Max sticks and he mentioned that those are on A3 PCBs. The Ballistix Max PCB looked awefully lot like my 3600MHz CL16 Ballistix sticks so that caught my attention. Googling "DDR4 A3 PCB" turned up jack except that I can pay JEDEC money to look at sk hynix's design files for A3 PCB. Just curious if anyone is privy to the difference between A3 and A2 PCB.
> 
> Edit: Currently testing 15-15-15-15-28 1T tRFC 140ns, no errors yet 14 minutes in.
> 
> Easiest flat 15 1T GDM disabled attempt? 🤣 🤞
> 
> Edit2: 15 cycles default 1usmus_v3 config tm5 stable so far, will test for full 25 cycles after my lessons.
> 
> View attachment 2525484
> View attachment 2525485
> 
> 
> tRDWR and tWRRD is currently on auto, I suppose tRDWR: 9 and tWRRD: 3 are good values to try on this kit?


Here is your first target (if you can do tCL 14 without tPHYRDL dropping to 28 then go for it!)

Hopefully they are acting like the earlier versions


----------



## Taraquin

A few questions about how to calculate timings, maybe Veii can answear? 
Ras=cl+rcdrd or rcdrd+rp, but can be lower
Rc=ras+rp
Faw=rrds x 4
Wr=rtp x 2
Rfc=rc x rtp or a higher multiplier
Rdwr=rcdrd / 2
Gdm=run cl, cwl, wr and rtp even
Any rules for wtrs/l, wrrd or others? 

One thing I wonder is how/why we should use the 40mv stepping on Zen 3?


----------



## mongoled

Audioboxer said:


> Thanks Veii another post of knowledge to be bookmarked. On the basis of heat and because I'm working with 2T just now I'm going to try and see if a 25 TM5 passes with them lower. At tCL14 I'm going to stick with 2T so I have 26/26 tPHYRDL.
> 
> What's your thoughts on tCL13? lol
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Made it to 4 minutes before errors. Everything is just on auto mind you, so I might have a chance at 3800! Looks like a challenge
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 0.01v VDIMM helped a little xD
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> lol, there it is again, the 26/26 at 1T on an uneven tCL.


There is an "old" post of yours I am going to find to serve as a warning


----------



## Luggage

Veii said:


> Looks to me like EDC FUSE - that triggers
> CCA is mostly EDC dependent, but 175A EDC is a bit low for the Fuse limit
> Try to double up that set 175A limit to something 350ish - or try to max it out as 9999999


I’ll try tonight, should still be cold enough on the balcony for 15-17C water temp.
Don’t like raising the EDC since it drops SC boost, for some stupid AMD reason. 170A is what I’ve maxed out with with workloads - occt mem test and mt5 - AC effective @ ~4950.
But now I’m losing MC boost anyway with higher SOC to stabilize 2T might as well play around with EDC again.


----------



## Luggage

Audioboxer said:


> Exactly the same memory as me and funny to see you have that same tPHYRDL issue at tCL14 1T. MSI board too. Different CPU though. Its looking to me like this might be an MSI issue!
> 
> Anyway, as your ram is exactly the same as mine I'd have worked with GDM disabled and gone with 2T at first.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> That was my best running profile. 53.9ns in AIDA64.
> 
> Your IMC will be better than mine so you can maybe do better, your latency should/could get lower too as mine will be higher with 2 CCD. I'd be working with GDM disabled though, whatever timings you're aiming for.


No bueno - 1T bluescreen in Aida.
Though with x570 Unify I have 4 dimm-slots and older trace layout, apart from lottery…

2T with slightly looser secondary and tighter primary needs higher soc and/or vdimm. But got one boot with 53.x latency and after lowering voltage, crashing and raising them again I ended up at 56.x with exactly the same settings so I took an aspirin and went to bed. >_<


----------



## Audioboxer

So my flat 14 adventures aren't going to be totally straightforward, while I got near 2 hours through a TM5 with basically copying my previous profile and just changing to 14/2T I got a 2 error eventually. I guess I would be quite surprised to see flat 14 at 3800 pass at 1.5v. Seems that's probably a bit light on the voltage. Issue I have is when I go above 1.5v I start to get TM5 complaining about resistances/CAD_BUS/RttNom. This is why I previously capped at 1.5v and worked with it.

On that note before actually getting to sleep I decided first thing is first and I best check my old profile to see if I have anything stable on this new ram










Thankfully it passed TM5 or I would have been tearing my hear out.

But now I need to figure out balancing voltages/resistances when heading towards 1.55v. As this memory is binned for 1.55v I guess my question is does GDM enabled really do that much to correct/change things behind the scenes? I'm presuming what is happening is disabling GDM, whether you are 2T/1T requires "manually getting everything right"?

Either way, I'm confident tRCDRD 14 is fine, it's just figuring out what voltage will be needed to fully stabilise tCL14, with tRCDRD 14 and what Proc/Rtt/DrvStr it needs. With me about to watercool the RAM I really want to run it at 1.55v and maybe beyond, so I need to learn what resistances/Rtt it is super sensitive to above 1.5v and why. I guess VDDP might need looked at as well rather than just capping at 0.9v above 1.5v.



Luggage said:


> No bueno - 1T bluescreen in Aida.
> Though with x570 Unify I have 4 dimm-slots and older trace layout, apart from lottery…
> 
> 2T with slightly looser secondary and tighter primary needs higher soc and/or vdimm. But got one boot with 53.x latency and after lowering voltage, crashing and raising them again I ended up at 56.x with exactly the same settings so I took an aspirin and went to bed. >_<


Are you trying tCL15? As I just posted above once I need to go above 1.5v on this PCB to help with tCL14 I start to hit the added challenge of TM5 complaining about resistances/RttNom/CAD_BUS.

This happened to me on my 3600C14 set binned at 1.45v and it's happening to me on my 4000C14 set binned for 1.55v. They're both the same PCB.


----------



## Taraquin

Audioboxer said:


> So my flat 14 adventures aren't going to be totally straightforward, while I got near 2 hours through a TM5 with basically copying my previous profile and just changing to 14/2T I got a 2 error eventually. I guess I would be quite surprised to see flat 14 at 3800 pass at 1.5v. Seems that's probably a bit light on the voltage. Issue I have is when I go above 1.5v I start to get TM5 complaining about resistances/CAD_BUS/RttNom. This is why I previously capped at 1.5v and worked with it.
> 
> On that note before actually getting to sleep I decided first thing is first and I best check my old profile to see if I have anything stable on this new ram
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Thankfully it passed TM5 or I would have been tearing my hear out.
> 
> But now I need to figure out balancing voltages/resistances when heading towards 1.55v. As this memory is binned for 1.55v I guess my question is does GDM enabled really do that much to correct/change things behind the scenes? I'm presuming what is happening is disabling GDM, whether you are 2T/1T requires "manually getting everything right"?
> 
> Either way, I'm confident tRCDRD 14 is fine, it's just figuring out what voltage will be needed to fully stabilise tCL14, with tRCDRD 14 and what Proc/Rtt/DrvStr it needs. With me about to watercool the RAM I really want to run it at 1.55v and maybe beyond, so I need to learn what resistances/Rtt it is super sensitive to above 1.5v and why. I guess VDDP might need looked at as well rather than just capping at 0.9v above 1.5v.
> 
> 
> 
> Are you trying tCL15? As I just posted above once I need to go above 1.5v on this PCB to help with tCL14 I start to hit the added challenge of TM5 complaining about resistances/RttNom/CAD_BUS.
> 
> This happened to me on my 3600C14 set binned at 1.45v and it's happening to me on my 4000C14 set binned for 1.55v. They're both the same PCB.


Gdm is slightly better at getting stability at same voltage compared to 2T, atleast in my experience. If you only get the resistances errors the gdm might fix the issue. It worked for me. 1.5V 3800cl14 2T is golden sample sample territory. I got 3800 14-15-14 gdm stable at 1.54V on my poor bin, but flat 14 was impossible even at 1.54V.


----------



## Audioboxer

Taraquin said:


> Gdm is slightly better at getting stability at same voltage compared to 2T, atleast in my experience. If you only get the resistances errors the gdm might fix the issue. It worked for me. 1.5V 3800cl14 2T is golden sample sample territory. I got 3800 14-15-14 gdm stable at 1.54V on my poor bin, but flat 14 was impossible even at 1.54V.


I nearly hit 2 hours with it holding on but as others also pointed out to me if it was actually stable at 1.5v, especially with tight secondaries and a low tRFC that would be one hell of a result.

I tried going to 1.55v for a run but as above this seems to be around where my RAM/mobo/CPU start to get sensitive to VDIMM and complain about the other settings. Which I do know is common, another few posters have mentioned at around 1.55v with DR they had to completely rework their resistances/ProcODT/Rtts.

It's just with this ram rated for 1.55v GSKILL would have to be confident it didn't flip out when ran at 1.55v. So GDM must be putting in a shift to try and make sure if people can cool it and run at such a voltage it can autocorrect any timings or minor errors. Disabled/3/1 and 20/20/20/20 seems to be quite opportunistic once you get to 3800-4000, but that is what GDM will run with.

As for GDM itself I won't accept it  Was just asking questions on it myself to try and understand it a bit better. I guess I'll first explore 1.51-1.52v and see if a minor VDIMM bump will take me to 25 cycles on flat 14 without freaking out about resistances/rtt/drvstr. All things considered ProcODT of 34.3, 6/3/3 or 7/3/3 and 40/20/30/20 has served me well.

But I guess the end game for me now might be having to step outside my comfort zone with them if I want to run the likes of 1.55v+ with GDM disabled.

*edit *










lol, after me complaining above it decides not to fall within cycle 1/2 at 1.55v like it was doing last night 

I'd rather do some serious testing with 1.51v first, 1.5v nearly managed it and I have been having issues up at 1.55v. Temps didn't get above 38 degrees there but part of me wonders with how awful the RipJaws heatsinks are (they don't even cover all the ram chips), if heat sensitivity at higher voltage is also an issue. Though I would hope the DIMM temperature sensor was accurate.

Need to do some work just now so don't have time to actually let TM5 run its full course, will be back on it later.


----------



## Leoyzen

After lookup backward of threads and trying, I've got a close stable 3800C14 for my micron b-die SR.

It passed 1000%@MT7.0 and 30 [email protected]_1usmus_v3 but failed for [email protected] at third cycle with error #15 or #12.

Firstly I though it may related to memory heat issues (about 64C), so I change RTT from 7/0/5 to 7/0/6, this time temp comes to 60C, but error changed from #12 to #15.

There is not much info about this situation. I don't know whether it can be ignored. Any advice will be appreciated.


----------



## Audioboxer

Leoyzen said:


> After lookup backward of threads and trying, I've got a close stable 3800C14 for my micron b-die SR.
> 
> It got 1000%@MT7.0 and 30 [email protected]_1usmus_v3 passed.
> But failed for [email protected] at third cycle with error #15 or #12.
> 
> First I though it may related to memory heat issues (about 64C), so I change RTT from 7/0/5 to 7/0/6, this time temp comes to 60C, but error changed from #12 to #15.
> 
> There is much info about this situation. I don't know whether it can be ignored. Any advice?
> 
> View attachment 2525491
> View attachment 2525493


I don't know enough about Micron but I'd maybe switch to 2T for now and even run with tCL16 at around 1.45v to see if you can get a fully stable baseline. If you haven't already got another profile stable.

From a Samsung b-die perspective temps seem high but as I said I don't know enough about Micron to know if it's fine up at 60 degrees. My b-die can flip out at 45-47 degrees lol.

If you've got a spare 120mm fan lying around plug it in, crank it up to 100%, point it at your ram and see how you get on. TM5 runs ram hotter than most normal use will but you need a bit of a thermal overhead for daily stable.


----------



## Leoyzen

@Audioboxer Thanks for advices.

I've already got a stable profile at 3800C15-CR1T. And it passed all the test. It is also fine though at 60C+ during TM5 testing.
The temperature is about 40~45C when gaming, I think the temp is fine for me.
I've read several post which said micron b-die is ok with high voltage (1.5V+), but I'm not quite sure.

I will order a mem fan and also change my case to see if it is related to the mem temp, or just stay at 3800C15-CR1T-1.4V as I'm not seeing much differences between C15 and C14 in micron stick. 
I just wanna challenging the Mem stick(it is quite good and quite expensive....just don't want waste it)


----------



## umea

Leoyzen said:


> @Audioboxer Thanks for advices.
> 
> I've already got a stable profile at 3800C15-CR1T. And it passed all the test. It is also fine though at 60C+ during TM5 testing.
> The temperature is about 40~45C when gaming, I think the temp is fine for me.
> I've read several post which said micron b-die is ok with high voltage (1.5V+), but I'm not quite sure.
> 
> I will order a mem fan and also change my case to see if it is related to the mem temp, or just stay at 3800C15-CR1T-1.4V as I'm not seeing much differences between C15 and C14 in micron stick.
> I just wanna challenging the Mem stick(it is quite good and quite expensive....just don't want waste it)


Real world performance I'd say stick to CL15, if you want to overclock for the sole sake of it then spend the time but performance wise its not worth it. Latency benchmarking is fun though.

Edit: To clarify, I mean that the time spent trying to get 14 to work is probably not worth it. (I assume you are talking about 14 14 14 14). Unless you really want to compete in latency benchmarking or something I'd choose the much simpler, non time consuming cl15 flat any day.


----------



## Audioboxer

Couldn't resist a TM5 run, so been working on the laptop 

Good news first










So what is the "bad news"? From earlier










Finishes about 6 minutes quicker on tCL15.

As for what his tells me, I guess I'll need to bench and find out. Is it just the difference between 2T and 1T? Albeit it 1T with setups, or has the change to tCL14 resulted in some secondary timings being unhappy?

I'm sure I can run tCL14 1T, but then I get the stupid MSI BIOS 28/26 bug. I'm calling it that because it damn well looks like a bug. Running 28/26 definitely impacts latency.


----------



## Mach3.2

Audioboxer said:


> Couldn't resist a TM5 run, so been working on the laptop
> 
> Good news first
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> So what is the "bad news"? From earlier
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Finishes about 6 minutes quicker on tCL15.
> 
> As for what his tells me, I guess I'll need to bench and find out. Is it just the difference between 2T and 1T? Albeit it 1T with setups, or has the change to tCL14 resulted in some secondary timings being unhappy?
> 
> I'm sure I can run tCL14 1T, but then I get the stupid MSI BIOS 28/26 bug. I'm calling it that because it damn well looks like a bug. Running 28/26 definitely impacts latency.


Just tested tPHYRDL with my viper steel sticks as well, cl14 1T ended with tPHYRDL at 28, cl14 2T dropped it to 26.

I'm running flat 15 1T GDM off on my sticks to get the matched 26/26 tPHYRDL.

On my Crucial Ballistix kit, the same behavior could be observed, cl14 and cl16 1T > tPHYRDL: 28, cl15 1T > tPHYRDL: 26

So far I'm 25 cycles stable for these set of timings. Will probably try to tighten tRFC a little tomorrow morning if time permits.


----------



## Mach3.2

Leoyzen said:


> @Audioboxer Thanks for advices.
> 
> I've already got a stable profile at 3800C15-CR1T. And it passed all the test. It is also fine though at 60C+ during TM5 testing.
> The temperature is about 40~45C when gaming, I think the temp is fine for me.
> I've read several post which said micron b-die is ok with high voltage (1.5V+), but I'm not quite sure.
> 
> I will order a mem fan and also change my case to see if it is related to the mem temp, or just stay at 3800C15-CR1T-1.4V as I'm not seeing much differences between C15 and C14 in micron stick.
> I just wanna challenging the Mem stick(it is quite good and quite expensive....just don't want waste it)


The tRCDRD wall with these Rev. B ICs are holding you back in the latency department. I just swapped out my Ballistix Rev. B sticks for a Samsung B die kit, punched flat 15 and tightened tRFC on those sticks, and I basically shaved off about 1.2ns in latency and gained roughly 1GB/s in read, write and copy memory bandwidth. You might want to try tCL15 instead of 14, see if you can match tPHYRDL on both channels. Mismatched tPHYRDL can incur a latency penalty.

Here's my timings for 3733MHz.









Edit: Btw, there's no point spending too much time with these micron sticks at low frequencies, the tRCDRD wall and ~290-300ns tRFC basically hard cap the performance. You're already way ahead in the price to performance ratio department with some light tuning.


----------



## Audioboxer

Mach3.2 said:


> Just tested tPHYRDL with my viper steel sticks as well, cl14 1T ended with tPHYRDL at 28, cl14 2T dropped it to 26.
> 
> I'm running flat 15 1T GDM off on my sticks to get the matched 26/26 tPHYRDL.
> 
> On my Crucial Ballistix kit, the same behavior could be observed, cl14 and cl16 1T > tPHYRDL: 28, cl15 1T > tPHYRDL: 26
> 
> So far I'm 25 cycles stable for these set of timings. Will probably try to tighten tRFC a little tomorrow morning if time permits.
> 
> View attachment 2525497


Hmmm another MSI bios doing the exact same thing with SR this time, I'm noticing a pattern... MSI motherboards. I might contact them and say it looks like their memory training has a bug.

I tested 1T/2T benches and it does seem 1T gives a little boost to read/write/copy and a minor latency improvement (0.2~0.3ns). I mean, it would be strange if running 1T done absolutely nothing, especially given how hard it is to run 1T pure.

What this means for me on this MSI board is unless I can get onto 1T 26/26, tCL15 1T might actually beat or at least be as good as tCL14 2T. Somewhat hurting the fact I'm delighted to get a set of memory that can do tRCDRD 14 at 3800 even with my crappy 5950x IMC.

Given the way these MSI bios' are acting it then means my next 1T 26/26 option under 15 becomes... tCL13. So do I try and stabilise this?










  

I was excited it made it into the 3rd cycle before dropping two errors on 2. I've got no idea if this means wanting more voltage (error 2 can be voltage or resistance) or it's as I brought up earlier, once I go to 1.55v+ territory I'd need to redo resistances.

Trying to remember what @Veii said to me, once VDIMM increases VDDP might need to drop (or was it increase lmao)? I've got the notes bookmarked somewhere lol. Or was it ProcODT that drops...


----------



## Mach3.2

Veii also said cl13 is not easy... 🤣

I'm happy with flat 15, but I'll probably sell off this kit soon.

130USD to shave off 1.2ns of memory latency plus an extra 1GB/s gain in memory bandwidth doesn't exactly scream "good value proposition", especially when I'm hard capped at 1867MHz FCLK.🙂


----------



## Audioboxer

Mach3.2 said:


> Veii also said cl13 is not easy... 🤣
> 
> I'm happy with flat 15. 🙂


Was managed at 3733, albeit it with a better IMC than what I'm working with [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread 1.53v which is pretty damn good. I've got tCL14 at 1.51v at 3800, I would expect tCL13 to want more. How much more? Dunno. 1.57v might be higher than needed, but as above I'm getting error 2'd whether that is going to come down to VDIMM, or VSOC/VDDP or resistances/ProcODT.

I guess I'll try and be up for the challenge, especially if MSI don't fix their BIOS nonsense, but I'll definitely need more help trying to figure out if it's voltage or resistance TM5 is upset about...

*edit* - I tried just upping VSOC/VDIMM from above










Think that made things worse.










So next I read from the encyclopedia of Veii copied the Proc/Rtt/DrvStr the poster that managed tCL13 3733 was using and I fell down again in the third cycle, but a 10 this time. Not sure if the lower ProcODT and reducing OdtDrvStr is helping or not. I guess I'll change to 6/3/3 and see if error 10 this time was about RttNom.

Hoping I can get tCL13 1T stable at 3800 cause I'll tell you something, it's the fastest I've seen a TM5 cycle completed, 5 mins 20 seconds. I think my prior record is about 5 mins 45-50 on my tCL 15 1T profile.

*edit - *

Tried messing with tCKE, something I don't have much hands on knowledge with, no real luck










Will probably need to shelve tCL13 for now until I can get some pointers.


----------



## Leoyzen

@umea Yeah, Thanks.
I know it is quite time consuming, but I'm a geek and want to learn something about memory OC(more _scientific_ way or first principle), so I just buy new micron b-die to replacing my bad bin Trident-Z Royal CJR.
At now I have a stable profile which I can fallback, and wanna see if I can push the stick harder to know it's limit, and learning something may help with next generation Ryzen(more convenience for high FCLK).

Does "flat timing" mean a lot? 15-15-15 performs better than 14-15-15? The tRCD of micron chips stuck at 17, I don't know whether it is worth to push to C14-17-17(just for fun).


@Mach3.2 Thanks for the reply. I'm got same [email protected] when using 3800C14 right now. So maybe it's ok.
I have some questing about CAD_BUS and RTT from your screenshot.
I saw comments by @Veii in these thread:

SR using 0/0/5 when <=1.5, 7/0/5 or 7/0/6 when over 1.5 or 1.52,
40/20/30/20 or 60/20/40/20 for SR, and CsOdtDrvStr>= 30 may be required for micron rev.B
 but you are using 7/3/6 and 30/20/24/24 @1.43V, could you explain more? That will be appreciate


----------



## Taraquin

Audioboxer said:


> Was managed at 3733, albeit it with a better IMC than what I'm working with [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread 1.53v which is pretty damn good. I've got tCL14 at 1.51v at 3800, I would expect tCL13 to want more. How much more? Dunno. 1.57v might be higher than needed, but as above I'm getting error 2'd whether that is going to come down to VDIMM, or VSOC/VDDP or resistances/ProcODT.
> 
> I guess I'll try and be up for the challenge, especially if MSI don't fix their BIOS nonsense, but I'll definitely need more help trying to figure out if it's voltage or resistance TM5 is upset about...
> 
> *edit* - I tried just upping VSOC/VDIMM from above
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Think that made things worse.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> So next I read from the encyclopedia of Veii copied the Proc/Rtt/DrvStr the poster that managed tCL13 3733 was using and I fell down again in the third cycle, but a 10 this time. Not sure if the lower ProcODT and reducing OdtDrvStr is helping or not. I guess I'll change to 6/3/3 and see if error 10 this time was about RttNom.
> 
> Hoping I can get tCL13 1T stable at 3800 cause I'll tell you something, it's the fastest I've seen a TM5 cycle completed, 5 mins 20 seconds. I think my prior record is about 5 mins 45-50 on my tCL 15 1T profile.
> 
> *edit - *
> 
> Tried messing with tCKE, something I don't have much hands on knowledge with, no real luck
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Will probably need to shelve tCL13 for now until I can get some pointers.


From past experience with both B-die and rev E reducing only CL by 1 requires 0.03-0.05V extra. If you also change trcdrd, trp, trc and trfc it can be anywhere from 0.05 to 0.1V. Going from 16 to 15 on rev E 3733 required 1.4 to 1.44V, going from 17 to 16 on B-die 4000 req 1.39 to 1.44V.


----------



## Mach3.2

Leoyzen said:


> @umea Yeah, Thanks.
> I know it is quite time consuming, but I'm a geek and want to learn something about memory OC(more _scientific_ way or first principle), so I just buy new micron b-die to replacing my bad bin Trident-Z Royal CJR.
> At now I have a stable profile which I can fallback, and wanna see if I can push the stick harder to know it's limit, and learning something may help with next generation Ryzen(more convenience for high FCLK).
> 
> Does "flat timing" mean a lot? 15-15-15 performs better than 14-15-15? The tRCD of micron chips stuck at 17, I don't know whether it is worth to push to C14-17-17(just for fun).


A lot of the performance gains come from tightening tRFC and all 4 of the primary timings, something you can't really do on Micron Rev. B due to the tRCDRD wall. Just lowering tCL by 1 tick won't do you much good if your tRCDRD won't budge.

Micron ICs really excel in pushing higher frequency to offset the relatively loose primary timings, but Samsung B die is still king, nothing can come close.



Leoyzen said:


> @Mach3.2 Thanks for the reply. I'm got same [email protected] when using 3800C14 right now. So maybe it's ok.
> I have some questing about CAD_BUS and RTT from your screenshot.
> I saw comments by @Veii in these thread:
> 
> SR using 0/0/5 when <=1.5, 7/0/5 or 7/0/6 when over 1.5 or 1.52,
> 40/20/30/20 or 60/20/40/20 for SR, and CsOdtDrvStr>= 30 may be required for micron rev.B
> but you are using 7/3/6 and 30/20/24/24 @1.43V, could you explain more? That will be appreciate


Can't remember where I copied that, but I'll go with Veii's advice for RTT and CAD_BUS. 😂


----------



## MrHoof

@Audioboxer Might be worth swapping the order of the dimms and see if the situation getts better or worse or does not change at all. For my kit it made a diffrence.


----------



## Audioboxer

Taraquin said:


> From past experience with both B-die and rev E reducing only CL by 1 requires 0.03-0.05V extra. If you also change trcdrd, trp, trc and trfc it can be anywhere from 0.05 to 0.1V. Going from 16 to 15 on rev E 3733 required 1.4 to 1.44V, going from 17 to 16 on B-die 4000 req 1.39 to 1.44V.





MrHoof said:


> @Audioboxer Might be worth swapping the order of the dimms and see if the situation getts better or worse or does not change at all. For my kit it made a diffrence.


I'll try 1.6v once watercooled. My fan/air temps are fine even at 1.58v but I'll feel more comfortable running TM5 at those voltages once cooling is better. I'm going to test if I can actually get tCL14 to pass at 1.5v, but 1.51v is still great.

I found this older post from Veii that I believe, if I've read it right, might suggest 1.58~1.62v could be needed for tCL13 [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread Though as usual in this topic most of the wealth of knowledge is for SR, not DR 

When going that high on VDIMM though I need to try and figure out if some bigger changes are needed with Rtts/Resistances/Proc to balance with the high voltage.

And yeah I will check swapping DIMMs because once they're watercooled, LOL, they aren't being removed easily.


----------



## Veii

Audioboxer said:


> I found this older post from Veii that I believe, if I've read it right, might suggest 1.58~1.62v could be needed for tCL13


All voltage depends on RTTs  *
you can run it at lower voltage, on stronger park - but the chance to kill "a not soo good PCB" , is higher
A0's should close to all be gone now, but it's still something to keep in mind

13-13 , seems to be fine
tCL means close to nothing sadly, and lower tCL mostly results in lower performance, than a good flat timing set
Logically this is not possible on most of the dimms, as they are slow on tRCD
BZ explained it well & hopefully it will get more attention
"tRCD is what dimms should be branded as & not marketing tCL"

They voltage bin the PCB and not so much the ICs itself,
hence i can run tCL 14 too on a HynixMFR (20nm) , if enough voltage is supplied (1.62v)

Else about the first quote towards MrHoof - it ended up usable (tRCD+tRTP = tRAS) , as "minimum tRAS"
But minimum tRAS close to never works , unless anything around it is perfect
Or if it works, and you don't have anything perfect ~ it limits lowest tRCD possible
Going with tRCD*2 , or even tRCD*2 + tCCD_L , is better for stability and to help push primaries down

At the end, all falls back to tRCD, nevertheless how aggressive tertiaries are 
EDIT:
* VDIMM, is not the main source for heat ~ arriving amperage is
1.5v on the "older known RTTs" , get's far hotter than my 1.65v right now on Park -2 steps
And 1.7v on Rev.E RTT_WR /2 , is barely reaching 45c in a 30c hot summer room (last time i tested it)

VDIMM might be dangerous to some point, but it's not the main source of heat
It's always good to run the weakest possible RTT's you can get away with & then adapt when you struggle to stabilize things (#6 and similar) *

EDIT2:
Just that RTT's are also Mainboard PCB depended, and the cleanness of the signal (PSU ripple)
Many dimm setups, will need different RTTs (4x8) than 2x16 do ~ although they are very similar as for "IMC taxing"
Fly-By , ITX, and T-Topology will also need different ~ than any 4 dimm daisy-chain 

soo also for example 2x32gb might need stronger RTT_WR with weak NOM, and PARK around 120ohm
Instead of 4x16 who should be fine at PARK/3 = 80ohm , but will need more NOM and likely only run at WR /3 (80) instead WR /2 (120)
Also a last thing to consider - is that RZQ =240 ohm is very unlikely to be still a thing
AMD had long time ago plans, to change & extend it to 360ohm ~ around the same time Intel 11th gen came out, which up to bios version scales between 240 and 360ohm
** oh a last thing,
Intel & AMD, aside from on-die termination differences ~ are pretty similar when it comes to RTT scaling right now (except they have more fine steps)


----------



## Audioboxer

Veii said:


> All voltage depends on RTTs
> you can run it at lower voltage, on stronger park - but the chance to kill "a not soo good PCB" , is higher
> A0's should close to all be gone now, but it's still something to keep in mind
> 
> 13-13 , seems to be fine
> tCL means close to nothing sadly, and lower tCL mostly results in lower performance, than a good flat timing set
> Logically this is not possible most of the dimms, as they are slow on tRCD
> BZ explained it will & hopefully it will get more attention
> "tRCD is what dimms should be branded as & not marketing tCL"
> 
> They voltage bin the PCB and not so much the ICs itself,
> hence i can run tCL 14 too on a HynixMFR (20nm) , if enough voltage is supplied (1.62v)
> 
> Else about the first quote towards MrHoof - it ended up usable (tRCD+tRTP = tRAS) , as "minimum tRAS"
> But minimum tRAS close to never works , unless anything around it is perfect
> Or if it works, and you don't have anything perfect ~ it limits lowest tRCD possible
> Going with tRCD*2 , or even tRCD*2 + tCCD_L , is better for stability and to help push primaries down
> 
> At the end, all falls back to tRCD, nevertheless how aggressive tertiaries are


Does this mean it should be OK for me to try lower than RttPark 3? These new DR PCBs seem to be pretty damn good. I've got flat 14 passing at 1.51v with 3800 and that is RttPark 3.

I can boot 13 flat, but the idea of trying to stabilise tRCDRD 13 at 3800 gives me chills. The main reason I want to boot tCL13 is the funky MSI bios tPHYRDL nonsense that results in 1T working properly with uneven tCL at 26/26. From watching TM5 runs alone tCL13 at 1T results in the fastest clears of a cycle I've seen, like 5 minutes 15~20 seconds.

But error 2 and sometimes error 10 are cropping up trying to stabilise tCL13.


----------



## MrHoof

veii got me confused for a sec  but i think you meant quote towards Mach3.2 about tras.


----------



## Yviena

Veii said:


> Looks to me like EDC FUSE - that triggers
> CCA is mostly EDC dependent, but 175A EDC is a bit low for the Fuse limit
> Try to double up that set 175A limit to something 350ish - or try to max it out as 9999999


Doesn't High EDC break boosting? everytime i have set it high it seems to boost way lower in Cinebench.
i seem to get higher frequency with EDC set around 175-190


----------



## Bal3Wolf

question for you guys is 1.44 volts to much for micron e ram ? dram calc shows min 1.44 rec 1.45 max 1.46 when i import my xmp.


----------



## deadfelllow

Hello guys,

I have Patriot 4400c19 Kit which is currently working at 4066MHZ with 5600x(no whea errors) and GDM on.

What else i can try to tighten the timings? Thanks for help.

VDIMM = 1.55

Test was stable until 1.30 hours so dont worry about this timings.Its %99 stable.

The timings based on Zen spreadsheet.

@Veii any ideas Master?


----------



## mongoled

I thinks its becoming quite clear the issue with regards to FCLK and WHEA 19s.

The smaller the motherboard the less chance there will be WHEA 19s at higher FCLK, that is, if those WHEA are attributed to data that is passed over the PCIe bus.

Smaller motherboards equates to shorter traces, hence less WHEA 19s.....


----------



## Luggage

Yviena said:


> Doesn't High EDC break boosting? everytime i have set it high it seems to boost way lower in Cinebench.
> i seem to get higher frequency with EDC set around 175-190


It gets much harder to cool, that’s the main reason for losing boost. But I have the same experience and mainly with losing SC boost. 
But there is some other f*ckery going on as well, I did some testing this morning with a cold loop. I’ll get back to the screenshots after work…


----------



## Audioboxer

1.5v flat 14 3800.

The only thing I'm not happy with is completion time, seems it's largely down to 2T losing some performance over 1T.

Really need to try and get tCL13 stable lol, that way I can switch back to 1T and get 26/26 on tPHYRDL.


----------



## mongoled

Heads up for Europeans who are looking at single rank dimms

Two different prices for the same product

Seller Amazon - I am guessing these are returns being sold as new ...

Seller GadgetLifestyle and Fulfilled by Amazon


----------



## mongoled

Audioboxer said:


> 1.5v flat 14 3800.
> 
> The only thing I'm not happy with is completion time, seems it's largely down to 2T losing some performance over 1T.
> 
> Really need to try and get tCL13 stable lol, that way I can switch back to 1T and get 26/26 on tPHYRDL.


You shouldnt pay so much attention to the time, unless you can make your OS to use the exact same resources on each and every run.

😀

Use the DRAM Calc memtest to compare "times" as its very consistent ...

Good job with the flat 14s, its also clear, thats its not the IMC of your CPU but the quality of the PCB is better on the new set you purchased


----------



## Taraquin

Bal3Wolf said:


> question for you guys is 1.44 volts to much for micron e ram ? dram calc shows min 1.44 rec 1.45 max 1.46 when i import my xmp.


I ran my previous kit on that for half a year, no issues. It handles heat better than B-die, but I would consider som airfliw for 1.5V+. Biggest problem is negative tRCDRD scaling with higher voltage. On my kit at 3733 I could do 19 up to 1.4V, 20 up to 1.45V and needed 21 up to 1.5V. I could lower CL accordingly, but performance was only slightly better overall since higher tRCDRD reduced perf a bit.


deadfelllow said:


> Hello guys,
> 
> I have Patriot 4400c19 Kit which is currently working at 4066MHZ with 5600x(no whea errors) and GDM on.
> 
> What else i can try to tighten the timings? Thanks for help.
> 
> VDIMM = 1.55
> 
> Test was stable until 1.30 hours so dont worry about this timings.Its %99 stable.
> 
> The timings based on Zen spreadsheet.
> 
> @Veii any ideas Master?
> 
> 
> View attachment 2525630


tRTP 10, 8 or 6, tRDWR 10 or 8. Can`t see much else you can do  CL14 you probably need a bit more volt for.


----------



## Audioboxer

mongoled said:


> You shouldnt pay so much attention to the time, unless you can make your OS to use the exact same resources on each and every run.
> 
> 😀
> 
> Use the DRAM Calc memtest to compare "times" as its very consistent ...
> 
> Good job with the flat 14s, its also clear, thats its not the IMC of your CPU but the quality of the PCB is better on the new set you purchased


Will give that a shot! My comparison is tCL15 routine finishes around 2 hours 40 minutes and the only difference is it is running on 1T.

I guess I can try a 1T run with flat 14 and see what time it takes. I know 28/26 gives a latency penalty but time to completion is probably more about read/write/copy speeds is it not?


----------



## mongoled

Luggage said:


> It gets much harder to cool, that’s the main reason for losing boost. But I have the same experience and mainly with losing SC boost.
> But there is some other f*ckery going on as well, I did some testing this morning with a cold loop. I’ll get back to the screenshots after work…


This "uckery" came with the "B" patch.

Have not got round to working out where the missing performance has gone from CB23 (around 100-150 points) but its likely its down to the EDC.

The quick play I had showed that telemetry setting assisted in getting back some performance, but it needs a lot more investigation which I have not spent the time digging into it.

One of the reasons is its getting a little tiring to learn older BIOSs, get a handle on how they act etc etc, only for the "slate to be wiped clean" by a newer agesa ....


----------



## mongoled

Audioboxer said:


> Will give that a shot! My comparison is tCL15 routine finishes around 2 hours 40 minutes and the only difference is it is running on 1T.
> 
> I guess I can try a 1T run with flat 14 and see what time it takes. I know 28/26 gives a latency penalty but time to completion is probably more about read/write/copy speeds is it not?


DRAM Calc, as in 1usmus "Ryzen DRAM Calculator" --> MemBench (sorry called it Memtest in previous post).

Only takes a couple of minutes to run ...


----------



## mongoled

deadfelllow said:


> Hello guys,
> 
> I have Patriot 4400c19 Kit which is currently working at 4066MHZ with 5600x(no whea errors) and GDM on.
> 
> What else i can try to tighten the timings? Thanks for help.
> 
> VDIMM = 1.55
> 
> Test was stable until 1.30 hours so dont worry about this timings.Its %99 stable.
> 
> The timings based on Zen spreadsheet.
> 
> @Veii any ideas Master?
> 
> 
> View attachment 2525630


Not many people are going to be willing to spend time with you diagnosing while you have GDM turned on.

Others will probably step in to explain to you why ....

Start from this template and get a stable set with GDM disabled by completing a 25 cycle TM5 run.

Once you got a stable profile you can start tweaking it ...










What I achieved with the same dimms but 32GB and higher FCLK/MCLK


----------



## deadfelllow

mongoled said:


> Not many people are going to be willing to spend time with you diagnosing while you have GDM turned on.
> 
> Others will probably step in to explain to you why ....
> 
> Start from this template and get a stable set with GDM disabled by completing a 25 cycle TM5 run.
> 
> Once you got a stable profile you can start tweaking it ...
> 
> View attachment 2525634
> 
> 
> What I achieved with the same dimms but 32GB and higher FCLK/MCLK
> 
> View attachment 2525633


I'll try this when i got home with GDM OFF


----------



## Audioboxer

mongoled said:


> DRAM Calc, as in 1usmus "Ryzen DRAM Calculator" --> MemBench (sorry called it Memtest in previous post).
> 
> Only takes a couple of minutes to run ...


Not sure if the default settings are what I should be using?










Ran in Windows










Ran in safemode


----------



## mongoled

Forget safe mode, default settings are fine

Here is one of my runs on a "clean OS" only AV is disabled, no other tweaks










I would have expected a quicker time


----------



## Audioboxer

mongoled said:


> Forget safe mode, default settings are fine
> 
> Here is one of my runs on a "clean OS" only AV is disabled, no other tweaks
> 
> View attachment 2525636
> 
> 
> I would have expected a quicker time


tCL15 is quicker










Going to try tCL14 with 1T

My windows installation is quite bulky with background apps lol, that's why I tried safemode.










tCL14 1T helps a little, but tCL15 still beats it  I know 28/26 adds a little latency penalty, but not sure it should impact it this much.


----------



## Bal3Wolf

Taraquin said:


> I ran my previous kit on that for half a year, no issues. It handles heat better than B-die, but I would consider som airfliw for 1.5V+. Biggest problem is negative tRCDRD scaling with higher voltage. On my kit at 3733 I could do 19 up to 1.4V, 20 up to 1.45V and needed 21 up to 1.5V. I could lower CL accordingly, but performance was only slightly better overall since higher tRCDRD reduced perf a bit.
> 
> tRTP 10, 8 or 6, tRDWR 10 or 8. Can`t see much else you can do  CL14 you probably need a bit more volt for.


cool i got about all i can out of my ram i think having 4 16gig chips kinda limits me cant use gdm or cant even post unless i relax timings a ton, Only reason i need to push volts is to get the trfc down 1.45 or less and it has to run at 580+ to be stable.


----------



## mongoled

Audioboxer said:


> tCL15 is quicker
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Going to try tCL14 with 1T
> 
> My windows installation is quite bulky with background apps lol, that's why I tried safemode.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tCL14 1T helps a little, but tCL15 still beats it  I know 28/26 adds a little latency penalty, but not sure it should impact it this much.


Thats more like it


----------



## Audioboxer

mongoled said:


> Thats more like it


I guess it shows the difference 1T makes, even if it's using setups lol.

Now to contacting MSI to ask them to explore what their memory training is doing. Trying to gather data and it does seem like it could be an MSI BIOS issue. Seen it now on B550 and X570.


----------



## Mach3.2

mongoled said:


> Forget safe mode, default settings are fine
> 
> Here is one of my runs on a "clean OS" only AV is disabled, no other tweaks
> 
> View attachment 2525636
> 
> 
> I would have expected a quicker time


I can't seem to disable Windows Defender on my bench OS..🤨

How you'd go about disabling Windows Defender on your clean os?


----------



## Taraquin

Bal3Wolf said:


> cool i got about all i can out of my ram i think having 4 16gig chips kinda limits me cant use gdm or cant even post unless i relax timings a ton, Only reason i need to push volts is to get the trfc down 1.45 or less and it has to run at 580+ to be stable.
> 
> View attachment 2525637
> 
> 
> 
> 
> View attachment 2525639


Best time I got at 3800cl15 was 112sec, but I had to set tRCDRD to 20, but tRP ran at 11, gdm off, 525 tRFC and tWR/tRTP 10/5. I guess dual rank and 3 lower tRCDRD makes up for all my tighter timings.


----------



## ManniX-ITA

Mach3.2 said:


> I can't seem to disable Windows Defender on my bench OS..🤨
> 
> How you'd go about disabling Windows Defender on your clean os?


This is pretty old but maybe works still:









GitHub - W4RH4WK/Debloat-Windows-10: A Collection of Scripts Which Disable / Remove Windows 10 Features and Apps


A Collection of Scripts Which Disable / Remove Windows 10 Features and Apps - GitHub - W4RH4WK/Debloat-Windows-10: A Collection of Scripts Which Disable / Remove Windows 10 Features and Apps




github.com





Older: GitHub - Sycnex/Windows10Debloater: Script to remove Windows 10 bloatware.

But maybe Sophia does it as well, not sure:









GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11


:zap: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11 - GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-t...




github.com


----------



## Mach3.2

ManniX-ITA said:


> This is pretty old but maybe works still:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - W4RH4WK/Debloat-Windows-10: A Collection of Scripts Which Disable / Remove Windows 10 Features and Apps
> 
> 
> A Collection of Scripts Which Disable / Remove Windows 10 Features and Apps - GitHub - W4RH4WK/Debloat-Windows-10: A Collection of Scripts Which Disable / Remove Windows 10 Features and Apps
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> Older: GitHub - Sycnex/Windows10Debloater: Script to remove Windows 10 bloatware.
> 
> But maybe Sophia does it as well, not sure:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11
> 
> 
> :zap: The most powerful PowerShell module on GitHub for fine-tuning Windows 10 & Windows 11 - GitHub - farag2/Sophia-Script-for-Windows: The most powerful PowerShell module on GitHub for fine-t...
> 
> 
> 
> 
> github.com


I ran sophia script last night, but maybe I miseed something.


----------



## Taraquin

mongoled said:


> I thinks its becoming quite clear the issue with regards to FCLK and WHEA 19s.
> 
> The smaller the motherboard the less chance there will be WHEA 19s at higher FCLK, that is, if those WHEA are attributed to data that is passed over the PCIe bus.
> 
> Smaller motherboards equates to shorter traces, hence less WHEA 19s.....


You might be onto something  5600X/5800X has shorter/simpler traces than 59X0X due to 1 less CCD if I understand correct. That might explain why running ram faster is easier on one CCD, in general it seems the majority of 1 CCDs can do 2000-2100 fclk post agesa 1.2+, while very few 2 CCDs get above 1900-1966. I know and have talked to 5 others with 5600X, and we all can do 2000-2100fclk, but one has some wheas, he has a B550 strix if I remember correctly. 

Itx-boards on average should be able to hit highest fclk with no wheas if tracing is the main whea source.


----------



## KedarWolf

Bal3Wolf said:


> cool i got about all i can out of my ram i think having 4 16gig chips kinda limits me cant use gdm or cant even post unless i relax timings a ton, Only reason i need to push volts is to get the trfc down 1.45 or less and it has to run at 580+ to be stable.
> 
> View attachment 2525637
> 
> 
> 
> 
> View attachment 2525639


----------



## tomzyka

Audioboxer said:


> I guess it shows the difference 1T makes, even if it's using setups lol.
> 
> Now to contacting MSI to ask them to explore what their memory training is doing. Trying to gather data and it does seem like it could be an MSI BIOS issue. Seen it now on B550 and X570.


I saw your posts about tPHYRDL some pages ago and did some tests myself since we have the same kit but different mobo/cpu:

tCL 13 (tCWL 12) @1T -> tPHYRDL 26/26 (tPHYWRL 7/7)
tCL 13 (tCWL 12) @2T -> tPHYRDL 26/28 (tPHYWRL 7/7)

tCL 14 (tCWL 12) @1T -> tPHYRDL 26/28 (tPHYWRL 7/7)
tCL 14 (tCWL 12) @2T -> tPHYRDL 26/26 (tPHYWRL 7/7)

tCL 14 (tCWL 14) @1T -> tPHYRDL 26/28 (tPHYWRL 9/9)
tCL 14 (tCWL 14) @2T -> tPHYRDL 26/26 (tPHYWRL 9/9)

tCL 15 (tCWL 14) @1T -> tPHYRDL 26/26 (tPHYWRL 9/9)
tCL 15 (tCWL 14) @2T -> tPHYRDL 26/28 (tPHYWRL 9/9)

No matter what procODT or VDDP or tRDWR/tWRRD, they don't change. That's why tCL at 13 gave me a nice latency improvement (from 52.5 to 51.6), but tCL 13 @3800 is probably a lot harder to stabilise.

Regarding your tCL 13 setting: You should definitely try to swap the order of the dimms! I did several tests and with my latest settings my dimms in the "wrong order" resulted in error 1+2+10+13 after 25cycles TM5 while the dimms in the "right order" resulted in zero errors after 25cycles.


----------



## Audioboxer

tomzyka said:


> I saw your posts about tPHYRDL some pages ago and did some tests myself since we have the same kit but different mobo/cpu:
> 
> tCL 13 (tCWL 12) @1T -> tPHYRDL 26/26 (tPHYWRL 7/7)
> tCL 13 (tCWL 12) @2T -> tPHYRDL 26/28 (tPHYWRL 7/7)
> 
> tCL 14 (tCWL 12) @1T -> tPHYRDL 26/28 (tPHYWRL 7/7)
> tCL 14 (tCWL 12) @2T -> tPHYRDL 26/26 (tPHYWRL 7/7)
> 
> tCL 14 (tCWL 14) @1T -> tPHYRDL 26/28 (tPHYWRL 9/9)
> tCL 14 (tCWL 14) @2T -> tPHYRDL 26/26 (tPHYWRL 9/9)
> 
> tCL 15 (tCWL 14) @1T -> tPHYRDL 26/26 (tPHYWRL 9/9)
> tCL 15 (tCWL 14) @2T -> tPHYRDL 26/28 (tPHYWRL 9/9)
> 
> No matter what procODT or VDDP or tRDWR/tWRRD, they don't change. That's why tCL at 13 gave me a nice latency improvement (from 52.5 to 51.6), but tCL 13 @3800 is probably a lot harder to stabilise.
> 
> Regarding your tCL 13 setting: You should definitely try to swap the order of the dimms! I did several tests and with my latest settings my dimms in the "wrong order" resulted in error 1+2+10+13 after 25cycles TM5 while the dimms in the "right order" resulted in zero errors after 25cycles.


It's definitely MSI, now the "best" way to try and report this to them...

Error 2 seems to be my biggest enemy so far with tCL13 and I'm struggling to find out what voltage and/or resistance it doesn't like. I have tried swapping the DIMMs, don't think it makes a difference.


----------



## XPEHOPE3

Yviena said:


> Doesn't High EDC break boosting? everytime i have set it high it seems to boost way lower in Cinebench.
> i seem to get higher frequency with EDC set around 175-190


You can try using AMD monitor to see which limit actually limits clocks. But I'd assume higher EDC current results bumps temps higher than in bump clocks in you case and ProcHot limit hits earlier. It should depend on cooling obviously.


Audioboxer said:


> I know 28/26 adds a little latency penalty, but not sure it should impact it this much.


Latency-wise you lost 0.5ns, just as much as I lose with 26/26 -> 28/26
Also if you have that much time to test, you might as well try raising tRTP (and maybe tWR) to 6 (12) on 14-2T profile. I had a latency drop on tRTP 8 -> tRTP 10 once
+ I wouldn't call a tRCDWR 8 profile a "flat" 14, and I did see (read-)latency drops with that low tRCDWR


----------



## Audioboxer

XPEHOPE3 said:


> You can try using AMD monitor to see which limit actually limits clocks. But I'd assume higher EDC current results bumps temps higher than in bump clocks in you case and ProcHot limit hits earlier. It should depend on cooling obviously.
> Latency-wise you lost 0.5ns, just as much as I lose with 26/26 -> 28/26


Just to confirm as I can't remember, have you got an MSI motherboard as well or is your 28/26 just from forcing it with low VDDP?

Reason I'm asking again is I'm going to forward this topic to MSI along with an outline of the 'bug' I think exists with their memory training.

Lower tRCDWR was boosting results in AIDA64. That's why I had it this low. Will experiment with tRTP. I'm newish to benching, mostly just been stability testing and checking latency in AIDA64. I didn't even know DRAM Calculator had a bench lol.


----------



## Steve_

What BIOS would people recommend at the moment? I've not udpated for ages and it does seem some of the later (but not latest?) are actually quite good improvements.
There were some comments that suggest maybe AGESA V2 PI 1.2.0.3 Patch B is better than 1.2.0.3 Patch C?

I'm hoping to get time to update at the weekend but because my BIOS is so old, I think I'll need to start _everything_ from scratch as opposed to loading a previous profile and working from there.


----------



## Audioboxer

Sent a message off to MSI customer service, so we'll see if some findings can at least be passed over to whoever works on the BIOS and who knows, maybe people with an MSI BIOS will finally be able to run tPHYRDL 26/26 at tCL14 1T 3800


----------



## XPEHOPE3

Audioboxer said:


> Just to confirm as I can't remember, have you got an MSI motherboard as well or is your 28/26 just from forcing it with low VDDP?


Updated signature


Steve_ said:


> There were some comments that suggest maybe AGESA V2 PI 1.2.0.3 Patch B is better than 1.2.0.3 Patch C?


I vote for 1.2.0.3C. Had no difference against patch B.


----------



## Audioboxer

XPEHOPE3 said:


> Updated signature
> I vote for 1.2.0.3C. Had no difference against patch B.


Interesting, I contacted MSI anyway!

In other news, my waterblock arrived



















The thermal pads are complete crap, but for a price all in of £27 I can't complain too much. Can confirm heatsink size is perfect, properly covers sticks like a Trident Z heatsink. G.SKILL really need to stop using RipJaws heatsinks...

Unfortunately no instructions to tell you thermal pad size needed, but I'd guess it's 0.5mm.

Probably get around to it next week when I have time and also 100% make sure I'm happy with the DIMM order lol.


----------



## ManniX-ITA

Audioboxer said:


> Can confirm heatsink size is perfect, properly covers sticks like a Trident Z heatsink. G.SKILL really need to stop using RipJaws heatsinks...


Can you measure the distance between the screw holes on top to connect the heat spreader to the waterblock?
I'm curious to know if it's 11cm like the Alphacool/EKWB.


----------



## Audioboxer

ManniX-ITA said:


> Can you measure the distance between the screw holes on top to connect the heat spreader to the waterblock?
> I'm curious to know if it's 11cm like the Alphacool/EKWB.


Do you mean the distance between the holes on the heat-spreader? If so it is 11cm, yeah.


----------



## Requiem4u

Pure 1T is faster, I know, but nobody told me it is so fast Aida can't measure it.


----------



## mongoled

Requiem4u said:


> Pure 1T is faster, I know, but nobody told me it is so fast Aida can't measure it.
> View attachment 2525654


That means you are going to crash in any second

😂 😂


----------



## mongoled

Mach3.2 said:


> I can't seem to disable Windows Defender on my bench OS..🤨
> 
> How you'd go about disabling Windows Defender on your clean os?


Ahhhh, it was several months ago, I remember I had to try several methods until I got one to work.

Cant remember the resource, what I do remember is that I used "Local Security" to change some Windows Defender values and that got it to "stick" ...


----------



## Mach3.2

mongoled said:


> Ahhhh, it was several months ago, I remember I had to try several methods until I got one to work.
> 
> Cant remember the resource, what I do remember is that I used "Local Security" to change some Windows Defender values and that got it to "stick" ...


I went into safe mode and disabled Windows Defender using group policy, seem to be sticking for now.

But absolutely no change to AIDA latency numbers. I'm still wondering how MrHoof get 51.4ns on 3800 cl14, 3733 cl15 can't be too far off, but I'm only getting 54.7ns 😵


----------



## Requiem4u

mongoled said:


> That means you are going to crash in any second
> 
> 😂 😂


Yep, and it is flat 16 . 14-15-14 2T is ok and tested. So, no pure 1T for me I guess.


----------



## Mach3.2

Requiem4u said:


> Yep, and it is flat 16 . 14-15-14 2T is ok and tested. So, no pure 1T for me I guess.


Have you tried running it without overclocking your BCLK?

I remembered buildzoid saying BCLK overclocking is kinda dangerous on X570 boards.


----------



## domdtxdissar

Dont spend all your time trying to tweak tPHYWRL.. there are other ways to improve performance.
I'm getting this @ 1900 with 28/28


----------



## Audioboxer

domdtxdissar said:


> Dont spend all your time trying to tweak tPHYWRL.. there are other ways to improve performance.
> I'm getting this @ 1900 with 28/28
> View attachment 2525660


Increase VDDP to 0.95~1.05 just to see if that drops to 26/26.

The issue isn't 28/28 either, it's 28/26 which I believe causes the latency penalty. I don't doubt 28/28 could be slower as well, but I believe the mismatch causes a bigger problem.


----------



## Mach3.2

domdtxdissar said:


> Dont spend all your time trying to tweak tPHYWRL.. there are other ways to improve performance.
> I'm getting this @ 1900 with 28/28
> View attachment 2525660


Do you get higher AIDA memory latency on AMD PBO+CO? I assume you're using Hydra for your overclocking?


I remembered buildzoid saying AIDA memory latency test is quite dependant on the CPU single core performance; lower core boost = higher latency.

edit: Your read bandwidth is also way over the theoretical bandwidth for 3800MHz. 🙃


----------



## Requiem4u

Mach3.2 said:


> Have you tried running it without overclocking your BCLK?
> 
> I remembered buildzoid saying BCLK overclocking is kinda dangerous on X570 boards.


Yes, but this is so little FSB OC, not really matter. Tried everything else before. I mean I can play with that more but there is hole at 1900 MHz.


----------



## MrHoof

Requiem4u said:


> Yes, but this is so little FSB OC, not really matter. Tried everything else before. I mean I can play with that more but there is hole at 1900 MHz.


Did you try with diffrent VDDP? i have a 1900fclk hole with my current settings at 0.850v vddp too 0.8-0.825v will boot 0.85v wont and 0.875v will boot again. But anything below 0.9v Vddp will desync tPHYRDL 26/28.


----------



## Luggage

Veii said:


> Looks to me like EDC FUSE - that triggers
> CCA is mostly EDC dependent, but 175A EDC is a bit low for the Fuse limit
> Try to double up that set 175A limit to something 350ish - or try to max it out as 9999999





Yviena said:


> Doesn't High EDC break boosting? everytime i have set it high it seems to boost way lower in Cinebench.
> i seem to get higher frequency with EDC set around 175-190





mongoled said:


> This "uckery" came with the "B" patch.
> 
> Have not got round to working out where the missing performance has gone from CB23 (around 100-150 points) but its likely its down to the EDC.
> 
> The quick play I had showed that telemetry setting assisted in getting back some performance, but it needs a lot more investigation which I have not spent the time digging into it.
> 
> One of the reasons is its getting a little tiring to learn older BIOSs, get a handle on how they act etc etc, only for the "slate to be wiped clean" by a newer agesa ....





XPEHOPE3 said:


> You can try using AMD monitor to see which limit actually limits clocks. But I'd assume higher EDC current results bumps temps higher than in bump clocks in you case and ProcHot limit hits earlier. It should depend on cooling obviously.
> Latency-wise you lost 0.5ns, just as much as I lose with 26/26 -> 28/26
> Also if you have that much time to test, you might as well try raising tRTP (and maybe tWR) to 6 (12) on 14-2T profile. I had a latency drop on tRTP 8 -> tRTP 10 once
> + I wouldn't call a tRCDWR 8 profile a "flat" 14, and I did see (read-)latency drops with that low tRCDWR


So while it was still chilly out on the balcony with my 1260 supernova I ran my usual EDC 170A, 510A as per Veiis tip and 90A just for fun. To see what happens whitout "Prochot limiter" kicking in.
CB r23 real time 170A : 16531, 16536,16463, 16469, 16520. 
CB r23 real time 510A: 16486, 16466, 16519, 16484, 16556, 16518.
CB r23 real time 90A: 15870 - allmost spillt my coffee as I first thought it said 16870 >_<

And I checked limits with vermeer monitor while running CPU-z 16 and 1 thread stress test.
Mostly PPT and CCA follow suit - except 70A MC since it's EDC limited so CCA don't care...

Too many screenshots?


----------



## MrHoof

Uhm tried to lower tRAS/tRC -2 tRFC -6 while also changing tRTP/tWR -2 and this happend. 26/28 not 28/26 
to many changes at once to say anything but gonna do some more tests.









edit: it was trtp/twr 5/10








tRFC 120ns lets see if stable 
edit2: not stable 😢 instant pc lock up when starting tm5


----------



## Audioboxer

MrHoof said:


> Uhm tried to lower tRAS/tRC -2 tRFC -6 while also changing tRTP/tWR -2 and this happend. 26/28 not 28/26
> to many changes at once to say anything but gonna do some more tests.
> View attachment 2525667


Have you tried simply increasing VDDP? Put it at like 1.05. It can be a powering issue that it's not 26/26 on both DIMMs.


----------



## Audioboxer

Okkkk, remember how I switched my DIMMs around earlier to try and see if I could get tCL13 stable? Well, tPHYRDL is now sitting at 28/30 lol










So I just went ahead and blasted VDDP up to 1.05v and...










So I've now managed 28/28  

First time I've managed a 28/28 and it seems a bit... random, nothing else has changed timing wise.










If I loosen up some timings to more standardised profile its still 28, but its retained 28/28. Which is progress, I guess. Most important thing is to get away from the mismatch.


----------



## MrHoof

Ok so tRTP/tWR 5/10 need 0.05v more VDDP here and i had to force a retrain after it was set to 26/28 from 0.925v just changing vddp back to 0.95v did not fix it. I set tRDWR/tWRRD to auto to force the memory training and switched them back afterwards to 7/3 auto will do 8/3. So that means tRTP/tWR play a role too in this.


----------



## Audioboxer

MrHoof said:


> Ok so tRTP/tWR 5/10 need 0.05v more VDDP here and i had to force a retrain after it was set to 26/28 from 0.925v just changing vddp back to 0.95v did not fix it. I set tRDWR/tWRRD to auto to force the memory training and switched them back afterwards to 7/3 auto will do 8/3. So that mean tRTP/tWR play a role too in this.
> View attachment 2525669


I can't get A1 onto 26, I tried loosening up more timings but its still 28.










Anyway, I experimented with VDDP and around 0.93v is as low as I can go or B goes back up to 30 lol.

If you've managed to get 26/26 at 3800 tCL14 1T congrats, don't touch anything 

I'm going to take my 28/28 and just be happy I don't have a mismatch any more.










Uh, crap, just trying 1T pure and B1 is back down to 26.... so I'm 28/26 on this


----------



## MrHoof

Nah i am learning from this too and if it might help others I am not afraid to test it, i have for sure won the silicon/board lottery this time. 

edit: **** you quoted my typo before i edited it 🤣


----------



## Audioboxer

MrHoof said:


> Nah i am learning from this too and if it might help others I am not afraid to test it, i have for sure won the silicone/board lottery this time.


Well it looks like I've found out CmdSetup times might impact it as well... Just noticed you're running 1T Pure, when I've switched over to that it's put me on 28/26 

*edit* - Can confirm. Went back to CmdSetup 56 and I'm on 28/28 again. 1T Pure on a 5950x is a bit of a pipe dream anyway. TM5 simply hates it


----------



## MrHoof

So tRAS 24 tRC 38 wasnt stable error in 3rd cycle and now I tried my stable timings with old tras/trc/trfc and now tRTP/tWR 5/10 produce 26/26. So its not only those to. This is getting complicated.
















I am not sure tbh if its realy the 5950x there a only handful of no setup timing 1T screenshots with DR that i know of.


----------



## Audioboxer

lol, as expected, tCL13 still produces 26/26. So even if I can get tCL14 to 28/28 in my mind it makes no sense why a lower tCL would train at 26 

Struggling to get tCL13 stable though, it's going to take a heck of a lot of time with testing to see if I can do it. In the meantime if I can get tCL14 1T to 28/28, I'll get it tested in TM5 and be happy.


----------



## MrHoof

Ok this might be intresting, I went back to my old setting and suddenly they produced 28/26 and the only thing i changed recently was RTT to 7/3/4 from 7/3/3, it seems that a higher park divder makes training harder? yesterday 7/3/4 was still 26/26 and stable. 7/3/3 is giving 26/26 all the time.

edit: And with my current stable timings and 7/3/3 tRTP/tWR 5/10 send my motherboard to safe mode with a overclocking fail🤣
stable settings also submitted to the google doc sheet with 25 cylcs tm5. I guess there is nothing left to improve  when your favorit game ends to early.


----------



## Audioboxer

MrHoof said:


> Ok this might be intresting, I went back to my old setting and suddenly they produced 28/26 and the only thing i changed recently was RTT to 7/3/4 from 7/3/3, it seems that a higher park divder makes training harder? yesterday 7/3/4 was still 26/26 and stable. 7/3/3 is giving 26/26 all the time.
> 
> edit: And with my current stable timings and 7/3/3 tRTP/tWR 5/10 send my motherboard to safe mode with a overclocking fail🤣
> stable settings also submitted to the google doc sheet with 25 cylcs tm5. I guess there is nothing left to improve  when your favorit game ends to early.
> View attachment 2525674


You're spot on Rtts do something










RttNom 7, 30










RttNom 6, 28


----------



## SneakySloth

SneakySloth said:


> I think these are my final timings and they seem to be stable.
> 
> Patriot Viper 4400, 4x8GB, A2.
> 
> View attachment 2525145
> View attachment 2525147
> 
> 
> 
> Tests done:
> 
> 
> TM5 75 cycles (50 + 25) (+ 4 hours of GPU stress test to heat up the system).
> Karhu 18500% + Stress FPU + Cache enabled (+1.5 hours of GPU stress test).
> 2 hours Prime95 Large FFT
> 2 hours OCCT memory test AVX2
> 
> 
> Regarding the tPHYRDL timing that some people have mentioned previously. Mine is 28 for A1, and A2 while 26 for B1 and B2.



These timings sadly weren't stable. Running OCCT again after a few days showed an error within an hour.

Increasing trfc from 252 -> 264 and TWRRD from 2 -> 4 seems to have fixed the issue. Managed to drop VDIMM as well a little from 1.5 -> 1.49. No noticeable change in latency or read and copy.

Its TM5 50 cycles + OCCT for 18 hours (11 + 6 ) stable. I might run Karhu overnight as well tonight



















.


----------



## XPEHOPE3

Audioboxer said:


> I'm going to take my 28/28 and just be happy I don't have a mismatch any more.


You better bench it first. All other settings equal, tPHYRDL 28/28 gave worse latency than 28/26 or 26/28 for me.


----------



## Bal3Wolf

Think i reached the limits of my ram im not sure i can tigthen anymore timings been going of dram calc template and testing then tighting last few days 4x 16gig is def harder to tune then the 2 16gig chips. I am tighter then most the timings in dram calc now and no theres no way to run with gdm off no post unless i relax timings to 20 20 20 even at 1.55 volts i cant get a post at tighter timings. Anything pop out i can try to tweak ?


----------



## mongoled

Audioboxer said:


> lol, as expected, tCL13 still produces 26/26. So even if I can get tCL14 to 28/28 in my mind it makes no sense why a lower tCL would train at 26
> 
> Struggling to get tCL13 stable though, it's going to take a heck of a lot of time with testing to see if I can do it. In the meantime if I can get tCL14 1T to 28/28, I'll get it tested in TM5 and be happy.


Turn on GDM and see what happens


----------



## Taraquin

Bal3Wolf said:


> Think i reached the limits of my ram im not sure i can tigthen anymore timings been going of dram calc template and testing then tighting last few days 4x 16gig is def harder to tune then the 2 16gig chips. I am tighter then most the timings in dram calc now and no theres no way to run with gdm off no post unless i relax timings to 20 20 20 even at 1.55 volts i cant get a post at tighter timings. Anything pop out i can try to tweak ?
> 
> View attachment 2525720
> 
> View attachment 2525721
> 
> 
> View attachment 2525722


You can try lower tRP, tWR 12 and tRTP 6, tWRRD 3 or 1. Is tRFC rock bottom? I could run 535 on my rev E at 3800, but 15 lower isn't much. I could run tRP at 11, that gave a bit of perf vs 16.


----------



## Bal3Wolf

Taraquin said:


> You can try lower tRP, tWR 12 and tRTP 6, tWRRD 3 or 1. Is tRFC rock bottom? I could run 535 on my rev E at 3800, but 15 lower isn't much. I could run tRP at 11, that gave a bit of perf vs 16.


Anything lower then 15 won't post on TRP, TRFC pretty much locked 535 won't post, testing other timings can least get in windows with them.


----------



## Taraquin

Bal3Wolf said:


> Anything lower then 15 won't post on TRP, TRFC pretty much locked 535 won't post, testing other timings can least get in windows with them.


On my rev E tRFC wouldnt boot at 520, it got rare errors at 522 and was stable for a year at 525. You might be able to do 540, that adds up with 6 tRTP so it might be a good match. Some say that tCKE should be configured, around 8-10 could work fine with 3800 if I remember correctly. Slightly lower ccd and vddp might help stability. I run mine at 840 atm, but 1 CCD and SR might require less voltage.


----------



## Audioboxer

Good news is a 1T tCL14 run finishes a bit quicker than 2T, even at 28/28, bad news is I have some errors to deal with  

I'm guessing 1T might need a bit more voltage than 2T if I'm at the edge of stability?










Keeping in mind a 2T profile that is much tighter passed at 1.5v.


----------



## umea

yolo toss 1.55v at it and see if that fixes it


----------



## Audioboxer

umea said:


> yolo toss 1.55v at it and see if that fixes it


The fix is even stranger.... Instead of the "relaxed" timings I setup I went for the 2T timings and dropped VDDP back down to 0.9v










Surprisingly, tPHYRDL stuck at 28/28 despite yesterday being at 28/30 🤷‍♂️

I have absolutely no idea what is going on with it lol.

VDIMM is at 1.51v but I bet if I drop it back to 1.5v now it passes 25 cycles just fine. If it does I'm going to guess VDDP at 0.93v was causing an issue? Why would it be looser timings causing errors?  2's especially are about voltage/resistance.

y-cruncher time!


----------



## Veii

Audioboxer said:


> Surprisingly, tPHYRDL stuck at 28/28 despite yesterday being at 28/30 🤷‍♂️
> 
> I have absolutely no idea what is going on with it lol.


After big changes, you need to Cold Boot (PSU Off) - else memory training will be remembered
Also because memory clear is/should be - disabled
Timings changes do renew training, but not all powering changes do instantly result in a cold boot

In boards favor, it would rather try to load what worked - instead of retesting IOL's every reboot


Audioboxer said:


>


I had 5's , but think it was because of too high DD's


Spoiler: still fighting with this:




















Always keeps crashing after Cycle 22+
One would say tRFC
But if i change 2 & 4, +1 - they crash between the 2nd and 5th cycle , sub 30min

Funnily, #8 appears to be issues on WTR_
I think #5 appears to be related to CAD_BUS. Probably AddrCmdDrv being to low ~ but i forgot, got it but didn't make a screenshot (dumb)
Have tested it so far ~6ish rounds soo around 8-9h. Still questionable what really is wrong. Heat it isn't as outdooors is atm ~10c


About RTT_NOM,
Sadly no direct changes to be seen between /7 NOM or /5 NOM but with AddrCmdDrvStr additive (would love to get back 24/24)
Although with all tPHYRDL reports here,
Stability test them first, be sure they where indeed stable ~ before jumping to conclusions about influences
They will jump up and down, if DIMMs are unstable to begin with
Memory Training will give it's best, to make it ~somehow~ , stable 


Yviena said:


> Doesn't High EDC break boosting? everytime i have set it high it seems to boost way lower in Cinebench.
> i seem to get higher frequency with EDC set around 175-190


Yes and no
CCA throttle , can have different outcomes
Be it for example that FIT VID throttles
Be it because of procHOT throttle, Package Throttle or the other wattage throttle in AMD CBS , NBIO (there are two)

As for my sample
Aside from 65c forced prochot throttle, it also throttles after 1.4v VID (from 1.45v peak allowed range) 
~ when any core tries to request more than this value. dLDO sensor ignored but smoothing factored in
Soo what directly helped, where more negative CO's ~ to lower requested per-core VID

If your sample is not V/F broken to begin with & the loadlines behave correctly (CTR Free or new Hydra is your friend)
Then you can try to match up VID Req with V-TEL
That way finetune loadlines (with 1 under flat ~ vdroop) , so that VID + random positive core offset = ~0.1% vdroop

Meaning,
When cores actually do get what they request ~ it's easier to work with CO's.
Positive VRM vcore additive - is undetected by FIT ~ and won't trigger throttle
But negative global vcore offset ~ because of such, does close to no benefit (compared to lowering COs)
Kind of telemetry faking, but i guess everyone got used to working with COs 

Do this, or if you want to start very simple
Just run a maxed out negative CO (-30) and add as much positive vcore offset, as you need (between 45-85mV)
Clock stretching, is an old topic ~ performance stretching.
It's not much more a topic to deal with , as it would rather throttle first ~ before it can even try to performance stretch
Although "stretching" is a miss-understood term. For example with the EDC bug, (still works, but it's bad) ~ it will clock stretch
Kind of now the same on Matisse units ~ with the current AGESA's (with dLDO balancing)
It will package throttle inside, soo kill off IPC ~ while holding target frequency.
The "throttling" internally @ target frequency ~ is what was titled here as "clock stretching".
Clocks did held the frequency, the bug functioned ~ but sideeffects of it trigged FIT to panic throttle (similar to it thinking it reaches 1.55v and has to throttle somewhere)

The better method for CO balancing, remains by hand
"Old days" ~ it was easier to just use what CTR (Rev.6) did for CO balancing and scale that up "-2 on everything, every +25mhz ta"


Spoiler: For me:












+2 ACPI , -1 CO
Sometimes +1.5 APCI rating
Soo Hydra has more granular control and throttle reason detection ~ on dLDO range. What pushes every core down
If it's unstable, just +2 CO on everything , soo -18,-16,-14 to -16,-14,-12 ~ and it will be stable, but potentially lose 25mhz max boost


Eh you'll see.
Target is, to find your VID value per core and together per CCD
~ which does not trigger exceed FIT-PRE-V as FIT maximum allowed voltage, and figure after which voltage you guaranteed start to EDC throttle

Where you can save power, is on a tight TDC limit - for harsh workloads like y-cruncher
This potentially can give you better performance.
Else you always will have better perf with lower requested by-core VID, ~ when FIT doesn't throttle back 
Again, 1.4v peak was it for me - out of 1.45v
~ Sometimes it's 1.375, sometimes it's 1.45 out of 1.55 . Sample dependent
And also again ~ keep in mind dLDO (since AGESA 1.1.8.X).
If one core in the whole chain requests more voltage ~ others will suffer and lose freq. Soo you have to balance them.
~ Sometimes it's a good idea, to drop everything around that bad core, soo overall VID-Req is lower, because remain ones do not need that much.
Really depends 


Spoiler: EDIT:



At the end,
Close to all "gold" rated samples - have a lot more headroom in them left
Unlike Matisse which was power-saving focused.
This gen, has big potential , but was not free'd.
Currently close to all samples are overvolted, and the CO range AMD gives, is too small.
Gladly Hydra exists now, but i don't think a single person/army can change AMDs artificial limits
@ 1.375 + when FIT is not the issue ~ many can run beyond 5ghz on weak FMA/SSE workloads.
Dual CCDs range changes to +1.4v, but even that is far lower than what PBO supplies ~ around 1.47ish.
Samples appear to be weak and lose frequency, but rather overvolt themself and FIT throttles back.
dLDO helped the whole story, but still broken DF_C-States & sleepy cores ~ don't do a favor in saving power budget, this generation


----------



## sonixmon

Audioboxer said:


> Increase VDDP to 0.95~1.05 just to see if that drops to 26/26.
> 
> The issue isn't 28/28 either, it's 28/26 which I believe causes the latency penalty. I don't doubt 28/28 could be slower as well, but I believe the mismatch causes a bigger problem.


I have not been able to get 26/26 except once which was with GDM on but less throughput. I haven't seen he 26/28 issue but always 28/28 and I even tried flat 15 and 2T which my system didn't like, booted a few times but not good. Had some warmer days again here and my 45c profile crashed on me (didn't catch ram temp but was 44 last I checked before crash). Made another profile with XMP timings but left secondary tight (image below) and it had decent latency, need to membench later today.



















Bal3Wolf said:


> Think i reached the limits of my ram im not sure i can tigthen anymore timings been going of dram calc template and testing then tighting last few days 4x 16gig is def harder to tune then the 2 16gig chips. I am tighter then most the timings in dram calc now and no theres no way to run with gdm off no post unless i relax timings to 20 20 20 even at 1.55 volts i cant get a post at tighter timings. Anything pop out i can try to tweak ?
> 
> View attachment 2525720
> 
> View attachment 2525721
> 
> 
> View attachment 2525722


Try GDM off with Setup 56, made a big difference for me since I cant run 1T pure.


----------



## Steve_

When you guys have moved away from RttPark - RZQ/1, have you just set this to your intended value and left ProcODT, the other Rtts and _DrvStr on auto or has it been a case of trial and error trying to find combinations that boot?

I'm hoping to update BIOS at the weekend and then start again with all my timings.

I'm running 4x16GB at 3800 flat 14 at the moment (VDIMM 1.5V) although I've not run a full 25+ cycles of TM5. (Given this is a fairly new setup for me and I'm going to be starting from scratch with the updated BIOS.)
I have some active cooling but not as much as I'd like so anything that helps bring temps down and/or allows higher VDIMM for more tuning potential is something I'm interested in and if my understanding is correct, running RttPark at RZQ/2 or /3 etc should help.


----------



## Audioboxer

Veii said:


> After big changes, you need to Cold Boot (PSU Off) - else memory training will be remembered
> Also because memory clear is/should be - disabled
> Timings changes do renew training, but not all powering changes do instantly result in a cold boot
> 
> In boards favor, it would rather try to load what worked - instead of retesting IOL's every reboot
> 
> I had 5's , but think it was because of too high DD's
> 
> 
> Spoiler: still fighting with this:
> 
> 
> 
> 
> View attachment 2525781
> 
> View attachment 2525782
> 
> Always keeps crashing after Cycle 22+
> One would say tRFC
> But if i change 2 & 4, +1 - they crash between the 2nd and 5th cycle , sub 30min
> 
> Funnily, #8 appears to be issues on WTR_
> I think #5 appears to be related to CAD_BUS. Probably AddrCmdDrv being to low ~ but i forgot, got it but didn't make a screenshot (dumb)
> Have tested it so far ~6ish rounds soo around 8-9h. Still questionable what really is wrong. Heat it isn't as outdooors is atm ~10c
> 
> 
> About RTT_NOM,
> Sadly no direct changes to be seen between /7 NOM or /5 NOM but with AddrCmdDrvStr additive (would love to get back 24/24)
> Although with all tPHYRDL reports here,
> Stability test them first, be sure they where indeed stable ~ before jumping to conclusions about influences
> They will jump up and down, if DIMMs are unstable to begin with
> Memory Training will give it's best, to make it ~somehow~ , stable
> 
> Yes and no
> CCA throttle , can have different outcomes
> Be it for example that FIT VID throttles
> Be it because of procHOT throttle, Package Throttle or the other wattage throttle in AMD CBS , NBIO (there are two)
> 
> As for my sample
> Aside from 65c forced prochot throttle, it also throttles after 1.4v VID (from 1.45v peak allowed range)
> ~ when any core tries to request more than this value. dLDO sensor ignored but smoothing factored in
> Soo what directly helped, where more negative CO's ~ to lower requested per-core VID
> 
> If your sample is not V/F broken to begin with & the loadlines behave correctly (CTR Free or new Hydra is your friend)
> Then you can try to match up VID Req with V-TEL
> That way finetune loadlines (with 1 under flat ~ vdroop) , so that VID + random positive core offset = ~0.1% vdroop
> 
> Meaning,
> When cores actually do get what they request ~ it's easier to work with CO's.
> Positive VRM vcore additive - is undetected by FIT ~ and won't trigger throttle
> But negative global vcore offset ~ because of such, does close to no benefit (compared to lowering COs)
> Kind of telemetry faking, but i guess everyone got used to working with COs
> 
> Do this, or if you want to start very simple
> Just run a maxed out negative CO (-30) and add as much positive vcore offset, as you need (between 45-85mV)
> Clock stretching, is an old topic ~ performance stretching.
> It's not much more a topic to deal with , as it would rather throttle first ~ before it can even try to performance stretch
> Although "stretching" is a miss-understood term. For example with the EDC bug, (still works, but it's bad) ~ it will clock stretch
> Kind of now the same on Matisse units ~ with the current AGESA's (with dLDO balancing)
> It will package throttle inside, soo kill off IPC ~ while holding target frequency.
> The "throttling" internally @ target frequency ~ is what was titled here as "clock stretching".
> Clocks did held the frequency, the bug functioned ~ but sideeffects of it trigged FIT to panic throttle (similar to it thinking it reaches 1.55v and has to throttle somewhere)
> 
> The better method for CO balancing, remains by hand
> "Old days" ~ it was easier to just use what CTR (Rev.6) did for CO balancing and scale that up "-2 on everything, every +25mhz ta"
> 
> 
> Spoiler: For me:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> +2 ACPI , -1 CO
> Sometimes +1.5 APCI rating
> Soo Hydra has more granular control and throttle reason detection ~ on dLDO range. What pushes every core down
> If it's unstable, just +2 CO on everything , soo -18,-16,-14 to -16,-14,-12 ~ and it will be stable, but potentially lose 25mhz max boost
> 
> 
> Eh you'll see.
> Target is, to find your VID value per core and together per CCD
> ~ which does not trigger exceed FIT-PRE-V as FIT maximum allowed voltage, and figure after which voltage you guaranteed start to EDC throttle
> 
> Where you can save power, is on a tight TDC limit - for harsh workloads like y-cruncher
> This potentially can give you better performance.
> Else you always will have better perf with lower requested by-core VID, ~ when FIT doesn't throttle back
> Again, 1.4v peak was it for me - out of 1.45v
> ~ Sometimes it's 1.375, sometimes it's 1.45 out of 1.55 . Sample dependent
> And also again ~ keep in mind dLDO (since AGESA 1.1.8.X).
> If one core in the whole chain requests more voltage ~ others will suffer and lose freq. Soo you have to balance them.
> ~ Sometimes it's a good idea, to drop everything around that bad core, soo overall VID-Req is lower, because remain ones do not need that much.
> Really depends
> 
> 
> Spoiler: EDIT:
> 
> 
> 
> At the end,
> Close to all "gold" rated samples - have a lot more headroom in them left
> Unlike Matisse which was power-saving focused.
> This gen, has big potential , but was not free'd.
> Currently close to all samples are overvolted, and the CO range AMD gives, is too small.
> Gladly Hydra exists now, but i don't think a single person/army can change AMDs artificial limits
> @ 1.375 + when FIT is not the issue ~ many can run beyond 5ghz on weak FMA/SSE workloads.
> Dual CCDs range changes to +1.4v, but even that is far lower than what PBO supplies ~ around 1.47ish.
> Samples appear to be weak and lose frequency, but rather overvolt themself and FIT throttles back.
> dLDO helped the whole story, but still broken DF_C-States & sleepy cores ~ don't do a favor in saving power budget, this generation


You're spot on, whilst this was stable earlier and 28/28 at TM5 running










I noticed later on it had reverted back to 28/30.










Increasing VDDP to 0.93v brought it back to 28/28, but like before with 0.93v it's brought about an error.

If increasing VDDP is bringing about errors what can be done about that? 0.93v is pretty low, damn BIOS sometimes wants to auto at 1.05~1.09v lol.

*Edit* - Hmm a cold boot (PSU off for 3 minutes) with AddrCmdDrvStr 24 at 0.9v is training at 28/28. Guess I'll run a TM5 on this. Always just kept AddrCmdDrvStr at 20 till now. I think I've seen my memory run 24/24/24/24 on Auto once, but its mostly been 20/20/20/20.


----------



## Bal3Wolf

sonixmon said:


> I have not been able to get 26/26 except once which was with GDM on but less throughput. I haven't seen he 26/28 issue but always 28/28 and I even tried flat 15 and 2T which my system didn't like, booted a few times but not good. Had some warmer days again here and my 45c profile crashed on me (didn't catch ram temp but was 44 last I checked before crash). Made another profile with XMP timings but left secondary tight (image below) and it had decent latency, need to membench later today.
> 
> View attachment 2525796
> View attachment 2525797
> 
> 
> 
> Try GDM off with Setup 56, made a big difference for me since I cant run 1T pure.


GDM off is a no go i am running 4 16gig sticks when i had 2 i could run it off but sence i added 2 more not possable only way i have been able to even post with GDM off is set 19 19 19 then it will post but crash windows.


----------



## Veii

Audioboxer said:


> *Edit* - Hmm a cold boot (PSU off for 3 minutes) with AddrCmdDrvStr 24 at 0.9v is training at 28/28. Guess I'll run a TM5 on this. Always just kept AddrCmdDrvStr at 20 till now. I think I've seen my memory run 24/24/24/24 on Auto once, but its mostly been 20/20/20/20.


Same, i try to experiment with this now
But i see at 40 , it requires quite more RTT_NOM
Trying to "change" my set ~ soo it appeals to other good OCer better. Too many dislike/can't understand my tFAW = tCCD_L reasoning for BurstRefresh Override
Just to proof people wrong that it has no wasted delay ~ i change my set a bit

Also it allows out of nowhere the use tRDWR 8 instead of 9
But because tRCDRD is 7.5 (15) , i can not get it stable @ 8, yet. Needs delay shuffling around
Tested SCL & DD pushing down - part, while worth it for bandwidth, it desyncs the set a bit
Next goal is pushing tWTR_S to 2 and adjusting the set slightly ~ has a connection with tCWL after all
Then next next goal is getting 3600 on 24/24 tPHYRDL somehow - and later maybe pushing 14-14-14 higher than 4000MT/s

EDIT:
Oh Audioboxer, where you able to run RTT_WR 120ohm (/2) at 3800 or only sub 3600 ?
Would be PCB dependent. Sadly my 4000-A0 doesn't like it beyond 3600. Even when RTT_WR /2 was much better @ 13-13-13. I lose the scaling ability beyond 4000


----------



## sonixmon

Bal3Wolf said:


> GDM off is a no go i am running 4 16gig sticks when i had 2 i could run it off but sence i added 2 more not possable only way i have been able to even post with GDM off is set 19 19 19 then it will post but crash windows.


Confirming you did Setup timings at 56?


----------



## Audioboxer

Veii said:


> Same, i try to experiment with this now
> But i see at 40 , it requires quite more RTT_NOM
> Trying to "change" my set ~ soo it appeals to other good OCer better. Too many dislike/can't understand my tFAW = tCCD_L reasoning for BurstRefresh Override
> Just to proof people wrong that it has no wasted delay ~ i change my set a bit
> 
> Also it allows out of nowhere the use tRDWR 8 instead of 9
> But because tRCDRD is 7.5 (15) , i can not get it stable yet. Needs delay shuffling around
> Tested SCL & DD pushing down - part, while worth it, it desyncs the set a bit
> Next goal is pushing tWTR_S to 2 and adjusting the set slightly ~ has a connection with tCWL after all
> Then next next goal is getting 3600 on 24/24 tPHYRDL somehow - and later maybe pushing 14-14-14 higher than 4000MT/s
> 
> EDIT:
> Oh Audioboxer, where you able to run RTT_WR 120ohm (/2) at 3800 or only sub 3600 ?
> Would be PCB dependent. Sadly my 4000-A0 doesn't like it beyond 3600. Even when RTT_WR /2 was much better @ 13-13-13. I lose the scaling ability beyond 4000


I've just learned to have a look at it thanks to you so fingers crossed for this run 🤞 100% it was training at 28/28 with 0.9v as I made sure to unplug power supply. What does this DrvStr help with, the powering of the sticks? 

I'm pretty sure I've ran RttWr at 2 but I'll need to get back to you. I ran a 7/2/5 for example, but that was maybe on my 3600C14 set. Can't quite remember if I've tried it on this 4000 set. Once this TM5 run is finished I'll try it at 3800 for you.

Good luck getting stable you're pushing frequencies I haven't even dreamt of trying 😱


----------



## Veii

Luggage said:


> So while it was still chilly out on the balcony with my 1260 supernova I ran my usual EDC 170A, 510A as per Veiis tip and 90A just for fun. To see what happens whitout "Prochot limiter" kicking in.
> CB r23 real time 170A : 16531, 16536,16463, 16469, 16520.
> CB r23 real time 510A: 16486, 16466, 16519, 16484, 16556, 16518.
> CB r23 real time 90A: 15870 - allmost spillt my coffee as I first thought it said 16870 >_<
> 
> And I checked limits with vermeer monitor while running CPU-z 16 and 1 thread stress test.
> Mostly PPT and CCA follow suit - except 70A MC since it's EDC limited so CCA don't care...


Retest please with Limited TDC
EDC has to be free. For cache boost and in general for CO
Sorry , should have mentioned you in the earlier post too

CCA & EDC Fuse are connected
But CCA will throttle also by THM, by ProcOD, FIT-PRE Voltage Limiter and couple more sensors
by EDC for sure, soo push 400A+ on it - just to never hit this limiter

Scores can slightly be lower by enabling PBO - as the scalar (random) will also influence it a bit
And so change the VID request slightly higher = throttling even earlier on Freq

EDIT:
Limiting EDC, does technically limit supplied voltage & in Matisse era resulted in more perf that way = lower voltage, lower powerdraw , higher boosting
Currently EDC limiting is not a good idea, as it kills L3 performance and access time


----------



## MrHoof

In wich way does a lower RTT_WR might help? Also any idea what HIGH-Z setting does?


----------



## Veii

MrHoof said:


> In wich way does a lower RTT_WR might help? Also any idea what HIGH-Z setting does?


Sadly non, High-Z i'm worried about (maybe can try with rev.E later)
Same as procODT beyond 120ohm
RTT_WR controls both how PARK and NOM behave. It has the highest priority
Is there to assist PowerDown. Is there to shuffle around CKE signal & match Phase (google for "micron Dynamic On-Die Termination")
In general how On-Die Termination Impedances function just with function bonuses. Similar to procODT but on DIMM level

Increases signal strength, often by a bit too much
But also is capable to generate missing PARK or missing NOM values & adapt for them
Just sometimes can be a bit too strong for the PCB - buut helps strengthen signal (also cleans it up)
~ soo will help also with tighter tRCD or tCL , just increases noise and limits maximum MCLK
* not that 3800 or 4000 is anywhere near "high" ~ soo we shouldn't worry too much.

EDIT:
Oh also breaks with SETUP timings (and can cause timing issues with tCKE), as SETUP timings do delay Raise & Drop CKE signal
Similar to what RTT's do
Both SETUP & tCKE are MCLK timing dependent. RTTs are universal and PCB dependent (both MB and DIMM PCB)
I for example can not run these high SETUP timings, without delaying all 3 equally


----------



## MrHoof

Veii said:


> I for example can not run these high SETUP timings, without delaying all 3 equally


I can not run 0 0 55 or 0 0 56 either with my current settings those will bluescreen me instantly on boot/tm5. But since i am lucky enough that 0 0 0 works for me all the time i dont have any experience/didnt mess with those yet.


----------



## Bal3Wolf

sonixmon said:


> Confirming you did Setup timings at 56?


What exacty do you mean by setup timings at 56 kinda new to that term ?


----------



## LxT1N

Hi im new on ram oc this are my kit F4-3600C14-32GTZN + Asus Rog Crosshair VIII Dark Hero with Bios 3801 + Ryzen 5800x what are better 3800CL14 - 3800CL16 or 3600CL14?

My setting on my 5800x are PBO + Curve Optimizer

PPT : 120
TDC : 85
EDC : 130

Curve Optimizer : - 30 on all core

VDDSOC Voltage = 1.125V
DRAM = 1.45V
VDDG CCD Voltage = 1.05V
VDDG IOD Voltage = 1.05V
CLDO VDDP Voltage = 0.95V










can someone help me how i can tunning my ram kit ?


----------



## VPII

Look I understand that most of you use TM5 to test memory but I've mostly used Karhu memtest partly because I paid for it so I might as well use it. When I do test my memory I usually would let it run till 13000% or so, but just to be certain I've let it run last night through the night and stopped it at 20 000%. Now the reason I want to bring this up is I generally find it hard to get download link for the required TM5, I was given it before but I seem to have lost it.

Now interestingly I run my Ryzen 9 5950X with curve optimizer set to minus -25 for all cores as I have tested it before with OCCT and it passed without an issue with my G-skill Flare X DDR4 3200 CL14 running at 3800mhz CL16. For this I will add the first picture, however at this point in time OCCT will not pass with my memory running 3800 CL18, it will however pass with the memory running DOCP or the stock DDR4 3200 CL14 even 3333 CL14 but any higher would fail and I am not sure why.

I did however pick up that keeping the memory temps below or just over 40c helps with stability and as such I placed a fan blowing over the memory dimms. The reason I ran Karhu memtest again and for the extended period of time was to see whether the issue was actually with my memory, but it does not seem that way.


----------



## VPII

Okay and just as proof for this, I'm adding a picture of running OCCT to show the errors shown. Now this would happen even if I completely disable PBO, unless I set the memory speed to 3200 CL14.


----------



## Luggage

Veii said:


> Retest please with Limited TDC
> EDC has to be free. For cache boost and in general for CO
> Sorry , should have mentioned you in the earlier post too
> 
> CCA & EDC Fuse are connected
> But CCA will throttle also by THM, by ProcOD, FIT-PRE Voltage Limiter and couple more sensors
> by EDC for sure, soo push 400A+ on it - just to never hit this limiter
> 
> Scores can slightly be lower by enabling PBO - as the scalar (random) will also influence it a bit
> And so change the VID request slightly higher = throttling even earlier on Freq
> 
> EDIT:
> Limiting EDC, does technically limit supplied voltage & in Matisse era resulted in more perf that way = lower voltage, lower powerdraw , higher boosting
> Currently EDC limiting is not a good idea, as it kills L3 performance and access time



Limit TDC how much?
I cant really compare numbers right now as it's not as cold and CB r23 pushes over 61C but I tried TDC at 95A and EDC 510A and it seems cpu-z stays under 61C soo...



http://imgur.com/a/iVpvcsp


----------



## ManniX-ITA

Steve_ said:


> When you guys have moved away from RttPark - RZQ/1, have you just set this to your intended value and left ProcODT, the other Rtts and _DrvStr on auto or has it been a case of trial and error trying to find combinations that boot?


You should read as many posts you can from @Veii (search on top and select this discussion), he made some recent about this 

Definitely not Auto, you need to counter-balance the changes. You also need to test for at least 25 cycles cause sometimes the instabilities can arise after a long time when you change the default Rtt.

About temperatures it does help but just a little bit.
What really matters for temperatures is what you set as timings, some more than others.

It's better to reduce impendence especially when you raise VDIMM above 1.5-1.55V.
For some older PCB like A0 can be dangerous, the newer PCBs are more robust.
The advantage of a lower impendence Rtt can give you a slight more flexibility in timings.

I don't have any specific active cooling on the DIMMs but I can still get away with decent timings at 4000 MHz and 1.55V using RttPark at /1.
If the profile is well balanced and not every timing as low as possible it works fine with /1 and doesn't drop errors even with high temperatures.
More is tight, less allowance on temperature; it'll start erroring at 50c, 45c, 40c, etc... depends on the binning and if it's a B-die or not.


----------



## mongoled

Audioboxer said:


> You're spot on, whilst this was stable earlier and 28/28 at TM5 running
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I noticed later on it had reverted back to 28/30.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Increasing VDDP to 0.93v brought it back to 28/28, but like before with 0.93v it's brought about an error.
> 
> If increasing VDDP is bringing about errors what can be done about that? 0.93v is pretty low, damn BIOS sometimes wants to auto at 1.05~1.09v lol.
> 
> *Edit* - Hmm a cold boot (PSU off for 3 minutes) with AddrCmdDrvStr 24 at 0.9v is training at 28/28. Guess I'll run a TM5 on this. Always just kept AddrCmdDrvStr at 20 till now. I think I've seen my memory run 24/24/24/24 on Auto once, but its mostly been 20/20/20/20.


I don't think you can assume the error is because of vDPP. The fact that tPHYRDL is increasing could also be an indication that it is a timings that effects stability, which looks that way when we see the latency penalty......


----------



## Taraquin

LxT1N said:


> Hi im new on ram oc this are my kit F4-3600C14-32GTZN + Asus Rog Crosshair VIII Dark Hero with Bios 3801 + Ryzen 5800x what are better 3800CL14 - 3800CL16 or 3600CL14?
> 
> My setting on my 5800x are PBO + Curve Optimizer
> 
> PPT : 120
> TDC : 85
> EDC : 130
> 
> Curve Optimizer : - 30 on all core
> 
> VDDSOC Voltage = 1.125V
> DRAM = 1.45V
> VDDG CCD Voltage = 1.05V
> VDDG IOD Voltage = 1.05V
> CLDO VDDP Voltage = 0.95V
> 
> View attachment 2525919
> 
> 
> can someone help me how i can tunning my ram kit ?


RAS 30, RC 45, RFC 270, RRDS 4, RRDL 6, FAW 16, WTRS/L 4/12, WR 12, RTP 6, SCLs 4, RDWR 10, WRRD 3.


----------



## Skull_Angel

Hi guys, I'm back. After my last post I spent almost a day working with PBO and boost before I got frustrated (blackbox of spaghetti BS...) and went back to tweaking ram instead. [I just got caught up with the thread so I have a good idea how to take another look at PBO limits!]

I was able to post 3800 flat 14 2T at 1.46 vdimm and showed tPHYRDL 26/26, but TM5 threw 6s all over until 1.56v where it was 6s and 0s. I may not have been pushing enough vSOC and am still learning about rtt and drvstr, but temperatures didn't look like they were going to be friendly for 24/7 on a gaming focused rig to begin with (actively cooled with a tilted fan).

3800 flat 15 2T @ 1.44v has been making progress (can't get away from tPHYRDL 28/28), but trying to follow calculation guidelines with mixed [odd/even] numbers has been driving me up the wall with rare and random errors I'm getting (last was a single error 13). Temperatures were borderline in TM5 though, so I'm not sure if continuing is worth it considering it's currently showing a small increase in bandwidth while latency is mostly the same as flat 16 (average less than 0.4ns difference).

Over the last day I've gone back to my 3800 flat 16 profile to see what I could get out of it and it's been pretty solid as far as stability goes. My main concern is temperatures, the FlareX set I'm using has the notoriously bad Ripjaws heatsink, so I may need to loosen some timings or play with rtt/drvstr/voltages which I could use some advice on.










I just realized I haven't done any CR 1T testing... Looks like I get to start on another journey as well!


----------



## shnyaps

Hi guys. I have:
CPU Ryzen 9 3950x
MB MSI Godlike 570
RAM G.SKILL 4x32GB 4000Mhz CL18
Unfortunately it doesn't work at 3733Mhz (fclk 1866) - during post I get F9 - ram training problems.
Before this I had RAM G.SKILL 4x8GB 3800Mhz CL14 and had 3733Mhz (fclk 1866) with SOC 1.1125V.
1) Why doesn't new RAM work at 3733Mhz (fclk 1866)?
2) Any advice to run it at this speed?


----------



## Audioboxer

mongoled said:


> I don't think you can assume the error is because of vDPP. The fact that tPHYRDL is increasing could also be an indication that it is a timings that effects stability, which looks that way when we see the latency penalty......












Possibly not, but I ran AddrCmdDrvStr at 24 last night and VDDP at 0.9v and it's passed again. Done a few reboots there and it's holding out at 28/28. I guess AddrCmdDrvStr can help!


----------



## Veii

Skull_Angel said:


>


Your allcore TM5 is very close to the 1.4v wall
if this is stock stock - it's fine. Just keep it in mind, once you reach 1.4v VID , it will frequency throttle back


Spoiler














TM5 is a weak SSE/FMA load ~ it shouldn't need more than 1.3v at best . Likely can run bellow 1.2VID even
sub 1.35v-TEL is what you'd need at 4.85, soo sub 1.3v is easily doable on stock stock 

Doublecheck your limits are open enough so that you hit and hold 10.9ns L3
This is how it can look at stock without limits, which is very "bad"















The "worse one" is Hydra @ 5ghz with handtuned cores
Although L3 shows rather a 4.9Ghz hold (10.4 = 4.85Ghz) ~ soo questionable

10.9ns is what a correct 4.65Ghz boost should look like
But as memOC eats powerbudget ~ you might need to open up EDC and TDC slightly ~ visible on this horrible 11.2ns result (2nd CCD is hungry and SOC is hungry)
see 2nd page the core cycler thread (big posts)
========================================
I still want to write something big ~ prepare information,
but let me borrow this post, as it's fitting 
Back stable ~ as OCer friends where moaning about my tRRD_S * tCCD_L = tFAW "trick" not being stable and autocorrecting ~ after the 11th 20 cycle failure attempt








* A little trick to tell, run Aida64 before running anything. The TM5 available RAM refresh window, does eat away 0.2ns 
Still think that my tRRD_S * tCCD_L trick is leading to better performance than 4* mode , but it should just make a statement









There is a bit to write now about tWTR_
But i'll let it for later 
#3 & #8 should be nearly fine for now ~ only #10 is continuously mocking me & it's root-cause not fully figured out

In general,
Keep tWTR_S as low as possible, this is barely affecting latency but will show in other benchmarks ~ pretty much increasing the effectiveness of primaries
But also means, start with 5 or even 6 , till you reach your target tRCD 
This affects directly your Copy bandwidth, and can add up to 800MB/s ontop ~ up to balance between tWTR & tRRD (all 4)

tWTR_L is rather affecting Read , which is affected by the whole chain of timings and also tRRD, tRTP & tFAW open-time
~ increase, decrease it till you have no #8 and gain more Read. At least do not lose any Read bandwidth ~ as that means a desync
Copy is twice this operation, which is tWTR_S work . tRRD only covers bank to bank, tWTR covers dimm to dimm (very simplified)
==================================================
*Little question & challenge to you everyone*
*Can anybody run tWTR_S 2 ?*
It should be fully PCB dependent ~ tWTR_L needs a higher bump on Dual Rank, same for tWR
Wonder if any PCB can run it down to 2 
==================================================
AMD did a fantastic job at disabling the 2nd CCD 
It's not like one is a full 8 core CCD, and the 6 core one just has 2 cores fixed at 550mhz lowest P-State
It's absolutely not like they are "fused away" or suspended/destroyed ~ heh
Oops, i guess 








================================================
EDIT:
I had cores randomly crashing consistently after 1:07h soo Cycle 17 (at least for 8 times, with random errors. Sometimes an explosion sometimes #10, sometimes #6)
What fixed it , is turning down PROM 2.5v rail to 2.45v
It appears that 1.8V rail high, does negatively affect 2.5v rail. Or at least low procODT does destabilize that way cores
Just as information piece for a potential possibility 


Spoiler: I know, but ASRock doesn't ?, Their bios has bugs since 3 versions :D












Other screenshots corrupted, have to live with this one
It shows what i run, and how it defaults


----------



## LxT1N

Taraquin said:


> RAS 30, RC 45, RFC 270, RRDS 4, RRDL 6, FAW 16, WTRS/L 4/12, WR 12, RTP 6, SCLs 4, RDWR 10, WRRD 3.


thx i will try with this are possible to get 14-14-14-14? and how I can do the math for tRFC, tRFC2 and tRFC4


----------



## Audioboxer

@Veii Trying RttWr 2 for you 










That's the furthest I've got with a tCL13 mind you 👀

If you didn't see on last page in my response to mongoled, AddrCmdDrvStr 24 looks to have "fixed" my tPHYRDL 28/28 at tCL14 1T.


----------



## Veii

Audioboxer said:


> That's the furthest I've got with a tCL13 mind you 👀


Just really don't like your tRDWR 
9 is with matching tCWL= tCL
Soo 10 is -1 tCWL 
12 is far too high
Probably tWRRD needs to be 4 ~ but not 100% confident


----------



## Audioboxer

Veii said:


> Just really don't like your tRDWR
> 9 is with matching tCWL= tCL
> Soo 10 is -1 tCWL
> 12 is far too high
> Probably tWRRD needs to be 4 ~ but not 100% confident


12/12 was really just because tPHYWRL runs at 7 then lol. 12/10 showed some promise but I never got around to 25 cycling it. 12/9 doesn't boot. With tCL13 it depends on what tRDWR will be stable at.

With tCL14 I can run 14/8 or 14/9. I may revisit both and do some benching on my tCL14 profile. I'll also figure out if 12/10 is stable.

For now I'm just having another look at tCL13, AddrCmdDrvStr 24 really seems to have helped stabilise the DIMMs a little bit when running 1T.


----------



## Nighthog

Veii said:


> ==================================================
> *Little question & challenge to you everyone*
> *Can anybody run tWTR_S 2 ?*
> It should be fully PCB dependent ~ tWTR_L needs a higher bump on Dual Rank, same for tWR
> Wonder if any PCB can run it down to 2
> ==================================================


I've had tWTRS do 2 for my Kingston Rev.E & Rev.J but also Hynix DJR but really only @ 3800/1900 speeds easy.
Increased speed usually needs you to crank your DRAM voltage to have stability with low tWTRS.
My D9VPP Rev.E did 4333Mhz tWTRS 2 at some stage as I have a screenshot but unsure how stable it was as I've always struggled to get 4266/4333 stable with 4x dimms on the Xtreme Rev.1.0. (it was some considerable time back)

D9WFL Rev.E is currently doing tWTRS @ 3 with 4266 4xdimms. Not tried to push it yet though that hard though. (Crucial 4400CL19 kits)


----------



## eckengucker_1

Sorry for being late to the party. I'm running an old Ryzen 3600 on a Gigabyte B350 board coupled with grade 2x 16GB B2 3200-C14 B Dies.

After digging through 100 pages from 2020 on this setup is Testmem5 stable:









Following master *veii's *calculations everything should be alright. If got three questions thou:

1. Besides lowering tRFC to 270 what else could I alter? tRCDRD doesn't go lower than 15 
2. Are there some workaround reaching IF 1900? VSOC to 1.2v & running default RAM preset didn't help. Best I can do is 1867
3. Is AddrCmd / CsOdt / Cke: 56 / 56 /56 necessary or could I run 40 / 0 /0









As you see latency isn't that great. I guess there is no real chance of getting below 66ns..


----------



## Ezalor

VPII said:


> Okay and just as proof for this, I'm adding a picture of running OCCT to show the errors shown. Now this would happen even if I completely disable PBO, unless I set the memory speed to 3200 CL14.
> View attachment 2525923


Getting 4x8 FlareX in 3800 C16 flat GDM off 1T is not very common, absolutely impossible for me. Some tips:

Your RTTs seem to be for a 2x8 setup, i would try 7/3/3 or 7/3/1

ProcODT 36.9

And the thing that probably makes the biggest difference, rRCDRD from 16 to 18

And if done in the above order, and still not working, go from 1T to 2T


----------



## Skull_Angel

Veii said:


> Your allcore TM5 is very close to the 1.4v wall
> if this is stock stock - it's fine. Just keep it in mind, once you reach 1.4v VID , it will frequency throttle back
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> TM5 is a weak SSE/FMA load ~ it shouldn't need more than 1.3v at best . Likely can run bellow 1.2VID even
> sub 1.35v-TEL is what you'd need at 4.85, soo sub 1.3v is easily doable on stock stock
> 
> Doublecheck your limits are open enough so that you hit and hold 10.9ns L3
> This is how it can look at stock without limits, which is very "bad"
> View attachment 2525940
> View attachment 2525941
> 
> The "worse one" is Hydra @ 5ghz with handtuned cores
> Although L3 shows rather a 4.9Ghz hold (10.4 = 4.85Ghz) ~ soo questionable
> 
> 10.9ns is what a correct 4.65Ghz boost should look like
> But as memOC eats powerbudget ~ you might need to open up EDC and TDC slightly ~ visible on this horrible 11.2ns result (2nd CCD is hungry and SOC is hungry)
> see 2nd page the core cycler thread (big posts)
> ========================================
> I still want to write something big ~ prepare information,
> but let me borrow this post, as it's fitting
> Back stable ~ as OCer friends where moaning about my tRRD_S * tCCD_L = tFAW "trick" not being stable and autocorrecting ~ after the 11th 20 cycle failure attempt
> View attachment 2525943
> 
> * A little trick to tell, run Aida64 before running anything. The TM5 available RAM refresh window, does eat away 0.2ns
> Still think that my tRRD_S * tCCD_L trick is leading to better performance than 4* mode , but it should just make a statement
> View attachment 2525944
> 
> 
> There is a bit to write now about tWTR_
> But i'll let it for later
> #3 & #8 should be nearly fine for now ~ only #10 is continuously mocking me & it's root-cause not fully figured out
> 
> In general,
> Keep tWTR_S as low as possible, this is barely affecting latency but will show in other benchmarks ~ pretty much increasing the effectiveness of primaries
> But also means, start with 5 or even 6 , till you reach your target tRCD
> This affects directly your Copy bandwidth, and can add up to 800MB/s ontop ~ up to balance between tWTR & tRRD (all 4)
> 
> tWTR_L is rather affecting Read , which is affected by the whole chain of timings and also tRRD, tRTP & tFAW open-time
> ~ increase, decrease it till you have no #8 and gain more Read. At least do not lose any Read bandwidth ~ as that means a desync
> Copy is twice this operation, which is tWTR_S work . tRRD only covers bank to bank, tWTR covers dimm to dimm (very simplified)
> ==================================================
> *Little question & challenge to you everyone*
> *Can anybody run tWTR_S 2 ?*
> It should be fully PCB dependent ~ tWTR_L needs a higher bump on Dual Rank, same for tWR
> Wonder if any PCB can run it down to 2
> ==================================================
> AMD did a fantastic job at disabling the 2nd CCD
> It's not like one is a full 8 core CCD, and the 6 core one just has 2 cores fixed at 550mhz lowest P-State
> It's absolutely not like they are "fused away" or suspended/destroyed ~ heh
> Oops, i guess
> View attachment 2525945
> 
> ================================================
> EDIT:
> I had cores randomly crashing consistently after 1:07h soo Cycle 17 (at least for 8 times, with random errors. Sometimes an explosion sometimes #10, sometimes #6)
> What fixed it , is turning down PROM 2.5v rail to 2.45v
> It appears that 1.8V rail high, does negatively affect 2.5v rail. Or at least low procODT does destabilize that way cores
> Just as information piece for a potential possibility
> 
> 
> Spoiler: I know, but ASRock doesn't ?, Their bios has bugs since 3 versions :D
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Other screenshots corrupted, have to live with this one
> It shows what i run, and how it defaults


Ah, that explains my performance losses while I was trying to wrap my head around PBO and auto-OC; I completely overlooked VID and wondered why I kept throttling at low temperatures. Unfortunately that screenshot was just PBO limits set high so that testing wouldn't be effected by a lack of current, I hadn't planned on a manual CPU overclock since this rig will be mostly for gaming and I'm getting a bit lazy in my "old age". These new fangled auto-overclocking options are nice, but the lack of documentation makes it hard to manipulate behavior. Thanks for the tips on what to look for when setting them.

I think I misunderstood what you were trying to tell me about tFAW in an earlier post and this clears it up a little. What software can I use to determine/view tCCD_? I can't seem to view the setting in the MSI UEFI. I do really need to bookmark and take notes about timing relationships though; the more I read and refine settings, the more I have to look it up again to change things because I can't remember 😂

I still have questions about manipulating rtt/drvstr/voltage at different ranges (frequency and timings). I've searched a good bit of this thread, but there's still a lot to take in and search seems give me mostly other info (I may have missed it looking for other info too). My current settings are mostly trial and error with a little insight since I kind of understand what the settings do, but not how they relate/work together outside of what's written the the last dozen pages.

And LOL! It looks like AMD did the same thing they did when the old Phenom x2 and x3 were popular. They gave up "destroying" the weak cores on the x4 that didn't make the cut and just disabled them, had a lot of friends with cheap "Px4" in those days 🤣

edit: I'm just going blind, found tCCD_L in a sub-menu

edit2: looks like the static XMP value for tCCD_L, I can't find a current value


----------



## domdtxdissar

Veii said:


> *Little question & challenge to you everyone*
> *Can anybody run tWTR_S 2 ?*
> It should be fully PCB dependent ~ tWTR_L needs a higher bump on Dual Rank, same for tWR
> Wonder if any PCB can run it down to 2


I have no problem booting tWTRS 2 atleast..
Stock binning for this bdie dual rank 16GBx2 set is 14-15-15-15 @ 4000 MT/s









All others timings are my 24/7 daily settings @ 1.545 vdimm (which passed 25 cycles) which i showed Aida64 numbers for alittle earlier.
(aida memory read, write and copy bandwidth numbers are above theoretical max😇)


----------



## Audioboxer

@Veii I was OK with a 14/9, and tPHYRDL stayed at 28/28.

Also managed to drop my tRFC to 240. I had a bit of a hard cap at 245 on my 3600C14 set, at least at 1.5~1.51v. Looks like this set might be able to go lower with tRFC around this voltage and maybe even lower at higher VDIMM.










12/12 gives me the tPHYWRL 7, but yourself and some others have pointed out to me a few times it's sometimes best to run tCWL same as tCL, bandwidth might even be slightly better. Guess I need to do some testing!


----------



## VPII

Ezalor said:


> Getting 4x8 FlareX in 3800 C16 flat GDM off 1T is not very common, absolutely impossible for me. Some tips:
> 
> Your RTTs seem to be for a 2x8 setup, i would try 7/3/3 or 7/3/1
> 
> ProcODT 36.9
> 
> And the thing that probably makes the biggest difference, rRCDRD from 16 to 18
> 
> And if done in the above order, and still not working, go from 1T to 2T


MY friend, thank you so much for responding. I will surely try that.


----------



## frantatech

eckengucker_1 said:


> After digging through 100 pages from 2020 on this setup is Testmem5 stable:
> View attachment 2525953


Lies, you did not. Because if you really did, you would disable GDM after 25 pages already


----------



## VPII

Ezalor said:


> Getting 4x8 FlareX in 3800 C16 flat GDM off 1T is not very common, absolutely impossible for me. Some tips:
> 
> Your RTTs seem to be for a 2x8 setup, i would try 7/3/3 or 7/3/1
> 
> ProcODT 36.9
> 
> And the thing that probably makes the biggest difference, rRCDRD from 16 to 18
> 
> And if done in the above order, and still not working, go from 1T to 2T


Also if I mat ask, the RTT, which setting is it exacty as I have three settings and I am not sure what you mean by 7/3/3 or 7/3/1

I changed the other and I am testing now to see.


----------



## MrHoof

VPII said:


> Also if I mat ask, the RTT, which setting is it exacty as I have three settings and I am not sure what you mean by 7/3/3 or 7/3/1
> 
> I changed the other and I am testing now to see.


Nom/Wr/Park


----------



## LuxorITA

Hello all, i've read a lot of pages and im almost reaching my maximun headsick XD

I'm really stuck to reach ur fantastic latency, without falls in ram errors (i also didnt tried to go 3800mhz, i think for gaming is best to reach the lowest possible latency, right?)

here are my settings (copied all from Ryzen Dram Calculator with option 3733mhz/x470/fast preset, also i've copied all option from page "power supply system" Best CPU/DRAM Stability column (idk if it is worse).
*Dram voltage is set atm @1.36v*

Please, help me to improve finally these lantecies @Veii @mongoled @ManniX-ITA or *anybody else. *
Thx a lot to who will try help me









thumbnail here:


----------



## Dodgexander

I've been reading this thread since trying to get stable on my wife's system. But I've hit a brick wall and I don't know where to go from here.

Her specs are as follows:
Ryzen 5800x
Aorus Elite X570
2x 8gb Patriot Viper 4400mhz CL19 (single rank, B die)
Sabrent Rocket 1 TB NVME
RTX 2080
EVGA Supernova 650

First I have been testing for stability with FCLK, I settled on 1900 since above that there were too many WHEA errors. For initial stability I found I had to set SoC to 1.2v, and IOD to 1150.
I read some useful posts from the experts here and realized that my CCD voltage may also have been set too high, and since then was able to get FCLK 1900 stable with 1.15v on the SoC, 1050 IOD and 850 CCD.

Since I verified that stable (15 passes TM5 anta extreme, 1h OCCT Memory Test) I moved on to tuning the memory at 3800mhz.

I have been following the famous MemTestHelper guide here:
MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper · GitHub

I got all the way to reducing CL and left the PC overnight doing another TM5 anta extreme test. When I checked it this morning I found a single WHEA error, yet the test itself was error free.

What does this mean for my stability? Is it solely an infinity fabric issue if you get a WHEA or can it also be connected to memory timings?
This is what I have so far:









Bear in mind that ProcODT is set to 28ohms now, but before it was set to the auto setting of 60ohms. Since I have B die running at a high voltage I'm testing stability with the same settings as before, but with lower ProcODT in case that's the issue.

As yet I have not touched CPU OC









Any pointers?


----------



## MrHoof

Well I guess my submission for the google doc got deleted for some reason. @Veii any idea why ? Imgur: The magic of the Internet submission screenshot.


----------



## umea

Dodgexander said:


> I've been reading this thread since trying to get stable on my wife's system. But I've hit a brick wall and I don't know where to go from here.
> 
> Her specs are as follows:
> Ryzen 5800x
> Aorus Elite X570
> 2x 8gb Patriot Viper 4400mhz CL19 (single rank, B die)
> Sabrent Rocket 1 TB NVME
> RTX 2080
> EVGA Supernova 650
> 
> First I have been testing for stability with FCLK, I settled on 1900 since above that there were too many WHEA errors. For initial stability I found I had to set SoC to 1.2v, and IOD to 1150.
> I read some useful posts from the experts here and realized that my CCD voltage may also have been set too high, and since then was able to get FCLK 1900 stable with 1.15v on the SoC, 1050 IOD and 850 CCD.
> 
> Since I verified that stable (15 passes TM5 anta extreme, 1h OCCT Memory Test) I moved on to tuning the memory at 3800mhz.
> 
> I have been following the famous MemTestHelper guide here:
> MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper · GitHub
> 
> I got all the way to reducing CL and left the PC overnight doing another TM5 anta extreme test. When I checked it this morning I found a single WHEA error, yet the test itself was error free.
> 
> What does this mean for my stability? Is it solely an infinity fabric issue if you get a WHEA or can it also be connected to memory timings?
> This is what I have so far:
> View attachment 2525992
> 
> 
> Bear in mind that ProcODT is set to 28ohms now, but before it was set to the auto setting of 60ohms. Since I have B die running at a high voltage I'm testing stability with the same settings as before, but with lower ProcODT in case that's the issue.
> 
> As yet I have not touched CPU OC
> View attachment 2525994
> 
> 
> Any pointers?


Since it's a whea error I'd guess (might be wrong) that it has to do with vermeer voltages. CCD seems too low, and I don't think it should ever be lower than VDDP. Would try VDDP .9, CCD .94, IOD 1.05, see if that fixes it.


----------



## Audioboxer

domdtxdissar said:


> I have no problem booting tWTRS 2 atleast..
> Stock binning for this bdie dual rank 16GBx2 set is 14-15-15-15 @ 4000 MT/s
> View attachment 2525980
> 
> 
> All others timings are my 24/7 daily settings @ 1.545 vdimm (which passed 25 cycles) which i showed Aida64 numbers for alittle earlier.
> (aida memory read, write and copy bandwidth numbers are above theoretical max😇)
> View attachment 2525981


@Veii I just noticed this, tWTRS 2 required me to increase my VDIMM from 1.51v but I got it to boot










Will quickly drop down towards 1.51v to see what the cut off voltage is for not posting.

*edit* - 1.54v got to desktop but a BSOD not long after booting into Windows. Seems tWTRS 2 will be voltage hungry and possibly not daily safe anyway.


----------



## MrHoof

For my Kit tWTRS 2 is a no boot at 1.54v and 3 is unstable. Intresting tho will try if 1.55v gets tWTRS 3 stable, but i dont think am comfortable pushing more vDIMM than that for that.


----------



## Audioboxer

MrHoof said:


> For my Kit tWTRS 2 is a no boot at 1.54v and 3 is unstable. Intresting tho will try if 1.55v gets tWTRS 3 stable, but i dont think am comfortable pushing more vDIMM than that for that.


Does it even have all that big a performance boost? I put it at 3 without even really knowing what it did 🤣

If it requires a big voltage jump probably not worth it. I'll give 2 a TM5 run but I can guess right now it's probably very unstable. As I said 1.54v brought a BSOD.


----------



## MrHoof

Well its not erroring in any Ram test but i dont think this write result should be possible at 1900fclk but the only time i get those weird Write results is with tWRTS 3


----------



## Ezalor

VPII said:


> Also if I mat ask, the RTT, which setting is it exacty as I have three settings and I am not sure what you mean by 7/3/3 or 7/3/1
> 
> I changed the other and I am testing now to see.


Hello again.
MrHoof also pitched in, but anyway, it is in order RttNom 7/RttWr 3/ RttPark 3 (or 1)

Those settings are found under 'advanced memory settings/timings' ProcODT should be in the same menu.

Let us know how you get on.

If these tips still wont make it stable, i can say that your tRFC is maybe too tight. You could try a common set of numbers used for FlareX at 3800:
tRFC 288
tRFC2 144
tRFC4 132


----------



## eckengucker_1

frantatech said:


> Lies, you did not. Because if you really did, you would disable GDM after 25 pages already


Had my first run with same settings and GDM off but got Error 6 in Testmem. Solution would be fixing the RTTs right? I thought 7 / 3 / 3 would be good for DR?
*(old screenshot with GDM enable)*


----------



## KedarWolf

This passes TM5 and I get 54.3 latency in AIDA.

I can't do SCLs lower than 4, older RAM.

Also need tRCDRD at 16 or get errors. 252 tRFC is the sweet spot for me.

Does anyone suggest any other tweaks?

On my RAM 0-0-0 Setup works best.

Oh, also see this, it lowered my AIDA latency from 54.8 to 54.3 in Windows 10 and helps L3 cache issues with Windows 11. I'm still running 10 though.









Windows 11 Tweaks, Fixes and Modifications [Overview]


AMD 5000 series L3 Cache fix... Added to main tweaks/fixes/mods index post.




forums.mydigitallife.net


----------



## sonixmon

Bal3Wolf said:


> What exacty do you mean by setup timings at 56 kinda new to that term ?


Go back several pages in this thread and you will see people talking about and showing screenshots with Setup timings to get GDM off. Some need 56, 56, 56 others just 56, 0, 0.

AddrCmdSetup seems to be key


----------



## Skull_Angel

@Veii Still no luck on flat 14. Opening the profile in bios did not work (training issue?), I had to manually modify a different stable profile to get past post. Still throws #6 in TM5, but can get past 7 sec instead of instantly crashing now 😂 Tried stepping up vSOC from 1.1v to 1.15v with little effect (noticed quite a bit of droop though, picture is @ 1.15v). Not much luck with stepping up vDIMM either, it doesn't feel worth it to continue if I can't start to get it stable at around this point (1.56v) at least. Possible tCKE and setup may help(?), but I haven't learned enough to even begin with them.

View attachment 2526027


edit: wrong picture, this was the last trial run










edit2: Have been back on the flat 15 profile and decided to go back to basics with reviewing the github guide. Seems I was skipping a few important steps so I revised my settings along with using your tRRDS*tCCDL=tFAW guide and have currently passed 12 cycles/no errors


----------



## Bal3Wolf

sonixmon said:


> Go back several pages in this thread and you will see people talking about and showing screenshots with Setup timings to get GDM off. Some need 56, 56, 56 others just 56, 0, 0.
> 
> AddrCmdSetup seems to be key
> View attachment 2526024


wierd thing i been toying with 4000mhz/2000 and all of sudden i can run gdm off even at my old 3800mhz timings but i need to redo them now sence they arent stable so back to drawing board retuning 3800mhz with gdm off.


----------



## Veii

MrHoof said:


> Well I guess my submission for the google doc got deleted for some reason. @Veii any idea why ? Imgur: The magic of the Internet submission screenshot.


this screenshot got WHEA #19
It was requested to be whea free

Sadly idk about the history ~ i'm "sadly" no sheet maintainer ~ just look on it here and there to fix visual botherings
They did not accept my proposal for 1h minimum TM5 testing time (1:30h actually, 20cycles min ~ 25cycles rec)
And kept timings who just run 20min TM5 ~ in there (which is very dreaming)

New records from the same person now look correct, but old where flawed
Sheet is getting a bit unserious ~ but "sadly" still remains a good source for help and records


Audioboxer said:


> @Veii I just noticed this, tWTRS 2 required me to increase my VDIMM from 1.51v but I got it to boot


Ty
Also @domdtxdissar @Nighthog
Can't fully push it as PCB depended ~ but there is no way it posts for me even +50mV 
Overall very good to know, ty


MrHoof said:


> For my Kit tWTRS 2 is a no boot at 1.54v and 3 is unstable. Intresting tho will try if 1.55v gets tWTRS 3 stable, but i dont think am comfortable pushing more vDIMM than that for that.


i actually wonder why ?
I have not really issues dailying 1.65v


eckengucker_1 said:


> Had my first run with same settings and GDM off but got Error 6 in Testmem. Solution would be fixing the RTTs right?


Depends on "when" it came, "how many" came & if any error followed it
#6 at the very end - generally after the 20+ mark , can mean other issues aside from timings
single #6 at the very end for me indicated unstable voltages (in this case unstable 2.5v rail)
can indicate unstable IMC voltages too
In general #6 means either you are minimum 20mV off on VDIMM - or it's outside factors (voltages and resistances)

When #2 comes into play, or #0
then it can mean something dimm related, but still can be (you lack 10mV vdimm) or RTT powering is too weak


KedarWolf said:


> View attachment 2526023
> 
> 
> This passes TM5 and I get 54.3 latency in AIDA.
> 
> I can't do SCLs lower than 4, older RAM.
> 
> Also need tRCDRD at 16 or get errors. 252 tRFC is the sweet spot for me.
> 
> Does anyone suggest any other tweaks?
> 
> On my RAM 0-0-0 Setup works best.
> 
> Oh, also see this, it lowered my AIDA latency from 54.8 to 54.3 in Windows 10 and helps L3 cache issues with Windows 11. I'm still running 10 though.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Windows 11 Tweaks, Fixes and Modifications [Overview]
> 
> 
> AMD 5000 series L3 Cache fix... Added to main tweaks/fixes/mods index post.
> 
> 
> 
> 
> forums.mydigitallife.net











Ty~
Fixed the strange Read throttle, but could be coincidence
In general ~ this fix was long awaited for L3 on Win11
And MS didn't fix it themself (again). Generally good, now Win11 is usable again (downgraded to 10 for submission purposes)

Cache still is a bit jumpy, but it's ok'ish now
EDIT:
I have a suspicion , that ZenTimings is not functioning correctly on 2DPC boards & requested a revisit
ITX board sometimes loses 1000mb/s read & 400mb/s copy out of nowhere
Up to how you load the bios ~ how it wants to train (requested potentially more training readout values)

Have a suspicion , that tPHYRDL is not reported correctly on B1 ~ soo this still could be just a coincidence that it "fixed" itself after the change
In general, the change should do nothing bad ~ soo let's see 
Maybe it's a thing ~ maybe just a believe with no bad effects (registry part).

EDIT2:
Ignore my tRRD_L
I do research something stupid now 
It's still stable and all, but you know - it was on 8
* preparing to go back to 1x tFAW exploit (what JEDEC titles as "not possible")


KedarWolf said:


> Does anyone suggest any other tweaks?


[YT] 5950X WARZONE RAM SPEED FPS BENCHMARK that's all i do in this order (on an Optm offline iso)
ISCL rather not
Oh HPET is needed on Ryzen , but spectre v2 tweaks are not bothering to have (although i disable the SystemTimer Driver and disable SysMain service)
TimerBench: Ein Benchmark für Windows Timer can test HPET on / off, what results in more draw calls

Else the OTA microcode update erasing (mc_update) from Sys32 & WinSxS was just a good measure to have
Balanced powerplan as always ~ but not much more to do. We need to wait till AMD finally fixes the bugged out overboost issue (DF-C States issue)


----------



## Joe Flores

Do you guys know if AGESA 1.2.0.3 Patch C is worth updating BIOS for from Patch A on Ryzen 5800x? ROG C7H x470 MB.


----------



## Veii

Veii said:


> Ty~
> Fixed the strange Read throttle, but could be coincidence


Yes pure coincidence & no visible change on Win10 for me ~ @KedarWolf
Either memory training is broken between reboots (two different results)
Or windows desktop manager restores buggy results after reboots ~ error'd that snipping tool was broken this reboot

Something is surely messed up
Memory training, or Windows itself ~ very unsure , but sure that you can not compare results that way when every reboot is different . . .
















Usually missmatching tPHY would be root cause ~ but ZenTimings doesn't show them
Yet it feels that way


Joe Flores said:


> Do you guys know if AGESA 1.2.0.3 Patch C is worth updating BIOS for from Patch A on Ryzen 5800x? ROG C7H x470 MB.


Patch A had USB dropouts
Potentially a good idea to just downgrade to pure 1200 without patches (these patches introduced usb dropouts on a board that didn't have them)
Or stay on the newest
Patch C/D does nothing for Vermeer ~ nothing directly visible

There was an IMC FW change, or rather PSP FW update ~ but you can update , let it run and then downgrade (to have the PSP-FW Update injected)
Depends if you get usb dropouts or not


----------



## Bal3Wolf

So i been testing and i can boot with GSDM off into windows but even at loose timings that is worse perf i bsod, freeze, memory errors my board just wont run 64gigs with GDM OFF.


----------



## Dodgexander

umea said:


> Since it's a whea error I'd guess (might be wrong) that it has to do with vermeer voltages. CCD seems too low, and I don't think it should ever be lower than VDDP. Would try VDDP .9, CCD .94, IOD 1.05, see if that fixes it.


I remember reading a post from Veii mentioning CCD has positive scaling with negative voltage and it's setting that lower that got my initial FCLK tests stable. VDDP I've never noticed affecting any stability.

I wonder if it's specific to the 5800x that I need these different voltages. I'm actually testing now even less vsoc.

This whole thing feels more like a lottery. You feel like you're getting somewhere but then something doesn't make sense and you're back to square one.

A question for you guys; how are you finding out the limit of your FCLK clock? I understand lower procODT is necessary for high FCLK but what other settings do you key in?

The strange thing about my ram is I can't even getting it to run with 4400mhz cl19 xmp timings whilst decoupling the FCLK. Is this normal?


----------



## LuxorITA

Veii said:


> View attachment 2526060


@Veii 
Interesting preset 16gb Single Rank, is it stable? Can i try to copy in my config??
And what RAM voltage i have to put here??


----------



## Veii

LuxorITA said:


> @Veii
> Interesting preset 16gb Single Rank, is it stable? Can i try to copy in my config??
> And what RAM voltage i have to put here??


copy them from this post








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Your allcore TM5 is very close to the 1.4v wall if this is stock stock - it's fine. Just keep it in mind, once you reach 1.4v VID , it will frequency throttle back TM5 is a weak SSE/FMA load ~ it shouldn't need more than 1.3v at best . Likely can run bellow 1.2VID even sub 1.35v-TEL is what...




www.overclock.net




1.65vDIMM
CPU VDDP 860mV, 2.5v to 2.45v , 2.55 to 2.55v, 1.8v VDD/VTT to 1.93v


----------



## Skull_Angel

It's looking good so far! Got some quick tests done to narrow timings so they didn't look as sloppy then went for a full test, seems to be all good. Still monitoring the tPHYRDL 28/28, but I'm going to check out whether tWR=tRTP*4 shows any improvements over tRTP*2 since it may be stressing on DR.


----------



## Audioboxer

domdtxdissar said:


> I have no problem booting tWTRS 2 atleast..
> Stock binning for this bdie dual rank 16GBx2 set is 14-15-15-15 @ 4000 MT/s
> View attachment 2525980
> 
> 
> All others timings are my 24/7 daily settings @ 1.545 vdimm (which passed 25 cycles) which i showed Aida64 numbers for alittle earlier.
> (aida memory read, write and copy bandwidth numbers are above theoretical max😇)
> View attachment 2525981


Dom, I meant to ask you, how on earth did you get your latency down to 51.x with a 5950x  Did you disable a CCD for benching?


----------



## LuxorITA

Veii said:


> copy them from this post
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Your allcore TM5 is very close to the 1.4v wall if this is stock stock - it's fine. Just keep it in mind, once you reach 1.4v VID , it will frequency throttle back TM5 is a weak SSE/FMA load ~ it shouldn't need more than 1.3v at best . Likely can run bellow 1.2VID even sub 1.35v-TEL is what...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 1.65vDIMM
> *CPU VDDP 860mV, 2.5v to 2.45v , 2.55 to 2.55v, 1.8v VDD/VTT to 1.93v*


Sorry for my nubbish question but i very scare to wrong some option and fry my ram or something else at these "hard" levels.

So, i have in my bios a little bit confusion for names of ur values,
can u say me exactly what's the names on my bios? *cpu vddp* which one is on my bios called? *2.5v to 2.45 *what's the name on my bios? *2.55 to 2.55v* what's the name? *1.8v VDD/VTT to 1.93v *what's the name??










or Thumbnail click image here:








like *to risk ZERO:

CLDO VDDP Voltage: 

1.05V SB Voltage : 

2.5V SB Voltage : 

CPU 1.80V Voltage : 

VTTDDR Voltage : 

VPP_MEM Voltage : 

VDDP Standby Voltage : *

thx for the patience


----------



## Veii

LuxorITA said:


> like *to risk ZERO
> CLDO VDDP Voltage:
> 1.05V SB Voltage :
> 2.5V SB Voltage :
> CPU 1.80V Voltage :
> VTTDDR Voltage :
> VPP_MEM Voltage :
> VDDP Standby Voltage : *


Why do you try to copy settings that are not for average users
Beyond 1.54v is dangerous if you don't know what you do
Maybe it's not a good idea to try and copy my settings

also are you sure your CPU can even reach 2100 FCLK ?
~ is it a bugged Dual CCD 6,8 core ?


Code:


CLDO VDDP Voltage:  0.9
1.05V SB Voltage : 1.05
2.5V SB Voltage : 2.5
CPU 1.80V Voltage : 1.93
VTTDDR Voltage : half of VDIMM
VPP_MEM Voltage :2.45
VDDP Standby Voltage : 0.86 (but it wont allow you, soo 0.9)

You have cLDO_VDDP in the screenshot
But again, unlikely a good idea to copy them

tCKE 13 only works on 2100 MCLK , but will not on higher or lower
RTTs work but only with this voltage and only because 2x8 GB

Values are SET values not GET soo,
VDDG CCD 1020mV
VDDG IOD 1120mV
SOC 1.25v with Loadline droop to 1.24375v
* only SOC is GET, because loadlines exist. cLDO_VDDP & VDDG have no loadline

Good luck 


Audioboxer said:


> Dom, I meant to ask you, how on earth did you get your latency down to 51.x with a 5950x  Did you disable a CCD for benching?


He runs very high PBO or CTR 
Well configured


Skull_Angel said:


> but I'm going to check out whether tWR=tRTP*4 shows any improvements over tRTP*2 since it may be stressing on DR.


Same thing but , tWR = tRTP*2 , is an easy ruleset - correct would be tRTPns = single (works with two) digit decimal divider inside tRFCns range
soo sometimes value 8 works, sometimes value 9 works - depends by MCLK what this placeholder value translates in ns

tWR *2 is for DR, can help and was used before.
but tWR = tRTP *2 is the "correct" one. Doubling tWR is just a stability thing for Dual Rank (capacity independent)



Dodgexander said:


> The strange thing about my ram is I can't even getting it to run with 4400mhz cl19 xmp timings whilst decoupling the FCLK. Is this normal?


Higher MCLK needs higher cLDO_VDDP ~ it's purely MCLK related and has tiny to no connection towards FCLK
VDDG IOD the IO-Die and mostly what dictates higher Fabric clock stability

VDDG CCD is voltage-balanced down together with IOD by SOC
it's fine to keep it lower.
Since AGESA 1.1.8.X dDLO_Injector exists, and averages voltages out - soo values changed a bit
But it's fine to keep it as low as y-cruncher allows to (as low as you can afford it)

1.8V rail is needed to be pushed for FCLK stability - but pushing this one too much, messes up CAD_BUS, RTT's & can mess up other voltages
Aka one of the two 2.5v rails
It can also cause cores to crash - soo mess up CCD voltage.
Yet slight bump to at least 1.83v is needed. Bellow 1.86 you shouldn't feel any negative results. 1.93 is questionable, 1.96 and higher surely does issues ~ yet you can just run 2v with sadly unknown peak limits (buut you can run it ~ maybe can find a use for XOC)


Dodgexander said:


> how are you finding out the limit of your FCLK clock? I understand lower procODT is necessary for high FCLK but what other settings do you key in?


Part of the message above,
Higher IOD, higher SOC AMD max overclocking voltage and onwards

Least amount of cLDO_VDDP , soo low procODT can be used
y-cruncher and OCCT extreme for benchmarks
Mostly y-cruncher FFT  ~ but run them all for 4 loops (72min)
And aida64 to catch EDC & Package throttle on latency increases (by lack of voltage & autocorrection)

EDIT:
Easiest probably is,
pushing SOC bellow 1.3v - as that will also cover lack of VDDG (likely bellow 1.25v)
and then try to slim down vSOC without having big latency increases.
Then tightening it down till y-cruncher starts to fail & increase VDDG & 1.8v rail ~ till it's stable again


MrHoof said:


> Well its not erroring in any Ram test but i dont think this write result should be possible at 1900fclk but the only time i get those weird Write results is with tWRTS 3
> View attachment 2526006


this happens when CPU overboosts - because DF_C-States are active
That and Powersupply idle control (typical current) need to be set correspondingly ~ till AMD fixes their issues they're having since dLDO implementation


----------



## Audioboxer

Veii said:


> Why do you try to copy settings that are not for average users
> Beyond 1.54v is dangerous if you don't know what you do
> Maybe it's not a good idea to try and copy my settings
> 
> also are you sure your CPU can even reach 2100 FCLK ?
> ~ is it a bugged Dual CCD 6,8 core ?
> 
> 
> Code:
> 
> 
> CLDO VDDP Voltage:  0.9
> 1.05V SB Voltage : 1.05
> 2.5V SB Voltage : 2.5
> CPU 1.80V Voltage : 1.93
> VTTDDR Voltage : half of VDIMM
> VPP_MEM Voltage :2.45
> VDDP Standby Voltage : 0.86 (but it wont allow you, soo 0.9)
> 
> You have cLDO_VDDP in the screenshot
> But again, unlikely a good idea to copy them
> 
> tCKE 13 only works on 2100 MCLK , but will not on higher or lower
> RTTs work but only with this voltage and only because 2x8 GB
> 
> Values are SET values not GET soo,
> VDDG CCD 1020mV
> VDDG IOD 1120mV
> SOC 1.25v with Loadline droop to 1.24375v
> * only SOC is GET, because loadlines exist. cLDO_VDDP & VDDG have no loadline
> 
> Good luck
> 
> He runs very high PBO or CTR
> Well configured
> 
> Same thing but , tWR = tRTP*2 , is an easy ruleset - correct would be tRTPns = single (works with two) digit decimal divider inside tRFCns range
> soo sometimes value 8 works, sometimes value 9 works - depends by MCLK what this placeholder value translates in ns
> 
> tWR *2 is for DR, can help and was used before.
> but tWR = tRTP *2 is the "correct" one. Doubling tWR is just a stability thing for Dual Rank (capacity independent)


CTR being the Hydra app?

My PBO is just 270/160/190 with a curve.


----------



## domdtxdissar

Audioboxer said:


> Dom, I meant to ask you, how on earth did you get your latency down to 51.x with a 5950x  Did you disable a CCD for benching?


Affinity trickery*, one of the reasons AIDA64 cant be used for performance comparisons between different systems..

I can use show upwards to 75000mb/sec memory read numbers at 1900:3800 speeds if i want. My recommendation have always been to use other benchmarks then Aida if you want compare real performance numbers between different systems.

Aida64 is way too easy to manipulate to be taken seriously
(and some important performance settings aida dont even care about)

* = normally a dual ccd cpu have around +3ns in Aida64 compared to single ccd cpu.
This is because the measurement is jumping between ccd's, i'm simply forcing the load to stay on a single ccd like if it was a 5600x/5800x


----------



## Audioboxer

domdtxdissar said:


> Affinity trickery*, one of the reasons AIDA64 cant be used for performance comparisons between different systems..
> 
> I can use show upwards to 75000mb/sec memory read numbers at 1900:3800 speeds if i want. My recommendation have always been to use other benchmarks then Aida if you want compare real performance numbers between different systems.
> 
> Aida64 is way too easy to manipulate to be taken seriously.
> 
> * = normally a dual ccd cpu have around +3ns in Aida64 compared to single ccd cpu.
> This is because the measurement is jumping between ccd's, i'm simply forcing the load to stay on a single ccd like if it was a 5600x/5800x


Smart! I might try this just to see what happens for me, because 54ns looks to be a pretty hard wall for the 5950x ran normally. Lowest I've recorded is 53.9ns in AIDA64. Or maybe it was 53.8, just under 54 anyway.

The affinity thing is done via task manager isn't it?


----------



## Veii

Audioboxer said:


> CTR being the Hydra app?


Clock Tuner Ryzen
both are 1usmus tools


----------



## domdtxdissar

Audioboxer said:


> Smart! I might try this just to see what happens for me, because 54ns looks to be a pretty hard wall for the 5950x ran normally. Lowest I've recorded is 53.9ns in AIDA64. Or maybe it was 53.8, just under 54 anyway.
> 
> The affinity thing is done via task manager isn't it?


Sadly i think this is a CTR/hydra exclusive feature 😢


----------



## Audioboxer

domdtxdissar said:


> Sadly i think this is a CTR/hydra exclusive feature 😢


Oh right, I got confused. I was thinking of whatever it is I seen recommended if you're attempting to test core stability and I think under task manager you can tell Windows to prioritise cores or something. Had that in my mind.

Was just looking to do it for fun. Anything around 54ns I believe is the result one should aim for with a 5950x and it seems if you can squeak into the 53.x range you're doing great.

Hoping the 3D revision or whatever AMD are calling it (someone can correct me) might improve the IMC on the 2 CCD chips and give us a latency boost. I might be tempted to change my 5950x if so, next-gen stuff can wait some years for me, not really interested in being an early adopter on DDR5.


----------



## LuxorITA

Veii said:


> Why do you try to copy settings that are not for average users
> Beyond 1.54v is dangerous if you don't know what you do
> Maybe it's not a good idea to try and copy my settings
> 
> also are you sure your CPU can even reach 2100 FCLK ?
> ~ is it a bugged Dual CCD 6,8 core ?
> 
> 
> Code:
> 
> 
> CLDO VDDP Voltage:  0.9
> 1.05V SB Voltage : 1.05
> 2.5V SB Voltage : 2.5
> CPU 1.80V Voltage : 1.93
> VTTDDR Voltage : half of VDIMM
> VPP_MEM Voltage :2.45
> VDDP Standby Voltage : 0.86 (but it wont allow you, soo 0.9)
> 
> You have cLDO_VDDP in the screenshot
> But again, unlikely a good idea to copy them


I know, and im almost 98,9% sure it will not works, but im also almost desperate to try reach or find a quite preset compatible to me (3733 or 3800) that will give me not a 49 latency, not 50, but a "quiet" 52/53 with a good bandwith...
but im stuck at wall of 55ns, read: 55.5k and copy about 50.8k...

I tried to copy a tons of presets from here but too many highs or differents setup ranks so not stables. Some was ok but same my results.

Do you have a preset not impossible for me that can reach more?


----------



## Veii

LuxorITA said:


> I tried to copy a tons of presets from here but too many highs or differents setup ranks so not stables. Some was ok but same my results.
> 
> Do you have a preset not impossible for me that can reach more?


you don't find anything valuable here
Zen RAM Overclocking ?
I got a 14-10-12-14 preset with tight tRFC which you can try your dimms on
else my preset should need around 1.52v on 3800MT/s 
tCKE then needs to be 9 instead of 13
And likely RTT's at 736 , CAD_BUS 40-20-30-24


----------



## Frosted racquet

I'm starting to lose my mind, need some help. 

G.Skill RipjawsV 3600 running XMP profile, MSI B550I ITX, 5600X @stock. I'm getting random TM5 errors on XMP settings and I don't know *** is the reason.
1usmus cfg spits out error 5,8,0,13 seemingly at random. Happens on AGESA 1203 and beta 1204. Dirty contacts, temp issues?


----------



## SneakySloth

Frosted racquet said:


> I'm starting to lose my mind, need some help.
> 
> G.Skill RipjawsV 3600 running XMP profile, MSI B550I ITX, 5600X @stock. I'm getting random TM5 errors on XMP settings and I don't know *** is the reason.
> 1usmus cfg spits out error 5,8,0,13 seemingly at random. Happens on AGESA 1203 and beta 1204. Dirty contacts, temp issues?


Have you tried increasing the memory voltage a little?


----------



## Veii

Frosted racquet said:


> Dirty contacts, temp issues?


Far to high VDDG voltages, surpasses SOC
either run 1.1625v SOC or drop them (both) to 1.05v
Be sure it's y-cruncher stable first.

There are bad XMP kits (broken) but it's rather your stock setup
Also please share a Zentimings "DEBUG" screenshot/readout

EDIT:
1800FCLK , 1800MCLK 
should run at 
900,1000,1000,1100
VDDP, VDDG , SOC


----------



## Luggage

Veii said:


> Far to high VDDG voltages, surpasses SOC
> either run 1.1625v SOC or drop them (both) to 1.05v
> Be sure it's y-cruncher stable first.
> 
> There are bad XMP kits (broken) but it's rather your stock setup
> Also please share a Zentimings "DEBUG" screenshot/readout
> 
> EDIT:
> 1800FCLK , 1800MCLK
> should run at
> 900,1000,1000,1100
> VDDP, VDDG , SOC


That’s unfortunately MSI auto VDDG voltages for 3600-3800 
Took me ages to find out how to get my changes to stick since I changed in the wrong place and MSI reset them to 1.1 every time I entered bios…

Not to be a nag but what did you consider low TDC? [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
Hopefully it gets chilly again so I can go back to ignoring prochot and test some more this weekend.


----------



## Veii

Luggage said:


> Not to be a nag but what did you consider low TDC?


up to CPU , can be different
You watch HWInfo , TDC usage % - and note the highest TDC you run and then limit it slightly - so it stays in the 98-100% area
Then check if you see any improvements at all ~ as EDC limits , do lower allcore voltages
TDC is there to limit peak boost voltages, while PPT is rather a powersuply limiter - although also used as pure TDP draw limit for cooler design

soo what you need to max out is PPT, Package Power limit and the cTDP limit (both inside AMD CBS , NBIO ~ maybe SMU)
DF_C-States disabling that , is inside NBIO - SMU Common options
Powersuply power limit , should be inside AMD CBS , CPU Common options - or also NBIO (set to typical current)

Last two mentions are to prevent the overboost bug - but Generate C-States has to be enabled
If not, it will not be able to move anywhere lower than P0 Power profile , which is 3.7 or 3.8ghz ~ while P1 is near 2.1ish and P2 near 980mhz
The lowest P-State and the states in between , depend on this Generate C-States flag ~ and are needed , in order to manage powerbudget better = higher boost
DF-C States or C6 states (translated) ~ are there to fully hibernate cores (but the wakeup from hibernation triggers an infinite boost and can by attempts also draw 1.55v @ 55ghz target)
on OC_Mode, this can peak to 1.68v @ 5.9ghz (applied)


Spoiler














We worked towards powerplan optimizations pre-dLDO era , as it made sense & i worked on a powerplan to utilize overboost for a positive thing - with fixed limits
But these fixed limits, bugged CPPC tags
Soo until we have a clear path to take & AMD fixes their overboost mess
It is more than recommended ~ to disable DF_C-States & Set powersuply Idle control to typical current

Hydra needs it set to low current with DF-C states enabled
But Hydra & CTR (pic above is Hydra) does enforce DF-CStates enabled , in order to fully hibernate cores and share more powerstates in between
Else AMD still "locked" the ability to set per clock frequency, without pushing anything near it upwards too ~ oor bugging it out to drop to 3.7ghz p0 state
* which btw still is in works, but hydra future i should not talk about


Veii said:


> Then check if you see any improvements at all ~ as EDC limits , do lower allcore voltages
> TDC is there to limit peak boost voltages, while PPT is rather a powersuply limiter - although also used as pure TDP draw limit for cooler design


We have to use TDC now, as limiting EDC - does limit (x)GMI link speed limits - and in general slows down cache & access time latency
EDC needs to be open fully.
There are several stages of limiters - PBO are the first stage and if it was me ~ i'd put all to infinite
But you know, Matisse performed better with fixed limits as they lowered voltage usage ~ soo maybe it still can work out , but just with TDC


----------



## Frosted racquet

Veii said:


> Far to high VDDG voltages, surpasses SOC
> either run 1.1625v SOC or drop them (both) to 1.05v
> Be sure it's y-cruncher stable first.
> 
> There are bad XMP kits (broken) but it's rather your stock setup
> Also please share a Zentimings "DEBUG" screenshot/readout
> 
> EDIT:
> 1800FCLK , 1800MCLK
> should run at
> 900,1000,1000,1100
> VDDP, VDDG , SOC


Thanks for the quick reply.

I posted an old Zen Timings screenshot, sorry. I forgot the new AGESA 1204 changes the default VDDG etc voltages. TM5 screenshot is the most current one, so the errors appeared with the settings below. I've also attached the debug log.

Currently running y-cruncher to check for errors.


----------



## Audioboxer

Upgraded to Windows 11 release build from Windows 10, seems to be OK so far.

Not a big fan of losing text labels on taskbar though.

*edit* - StartisBack fixes that!


----------



## Dodgexander

Did another TM5 Extreme test overnight which passed, only to find a single WHEA error that happened probably the moment the test finished.
What do I need to look out for when this kind of thing happens? What could be dropping low on idle?

I have had the same problem now with 1150 soc and 1130 soc.
LLC is Turbo for soc. Good or bad idea?
VDDG is 1080
VCCD is 870
VDDP 900
VDIMM 1500

I don't understand since my system is 100% load stable at 1900 FCLK but I start to get these WHEA errors on idle when I've started tuning my memory. Tested OCCT, Ycruncher, TM5.


----------



## Audioboxer

Dodgexander said:


> Did another TM5 Extreme test overnight which passed, only to find a single WHEA error that happened probably the moment the test finished.
> What do I need to look out for when this kind of thing happens? What could be dropping low on idle?
> 
> I have had the same problem now with 1150 soc and 1130 soc.
> LLC is Turbo for soc. Good or bad idea?
> VDDG is 1080
> *VCCD is 870*
> VDDP 900
> VDIMM 1500
> 
> I don't understand since my system is 100% load stable at 1900 FCLK but I start to get these WHEA errors on idle when I've started tuning my memory. Tested OCCT, Ycruncher, TM5.


That seems unnecessarily low, could result in WHEA. Lowest I ever ran VCCD was 0.925v. Have it at 0.975v just now.


----------



## 1s1mple

Frosted racquet said:


> Thanks for the quick reply.
> 
> I posted an old Zen Timings screenshot, sorry. I forgot the new AGESA 1204 changes the default VDDG etc voltages. TM5 screenshot is the most current one, so the errors appeared with the settings below. I've also attached the debug log.
> 
> Currently running y-cruncher to check for errors.


I have the same kit, my first one I had to RMA it because at stock i had memory errors. 
You might have a defective kit.

Here's the new kit i got from RMA with some OC


----------



## Frosted racquet

@1s1mple which programs had shown errors for the defective kit? TM5 or?


----------



## MrHoof

Veii said:


> this screenshot got WHEA #19
> It was requested to be whea free


Ye well those were from my 4000mhz c16 test a few days prior, thats why opened the calender but i guess should have shown atleast that i run 1900fclk at the time of screenshot. But ye didnt put alot of effort into the submission for the reasons u listed aswell.



Veii said:


> i actually wonder why ?
> I have not really issues dailying 1.65v


Didnt think about RAM cooling when building this system, i can barley fit a fan that moves some air over the dimms . I am already reaching 44°C at 20°C ambient and dont wanna run the fan faster its getting to loud you know.



Veii said:


> this happens when CPU overboosts - because DF_C-States are active
> That and Powersupply idle control (typical current) need to be set correspondingly ~ till AMD fixes their issues they're having since dLDO implementation


Do i need to worry about "overboost"? Would rather like to stay with low current idle. 
edit: Did some google veii old post, if i dont randomly crash i guess overboost is ok?


----------



## Luggage

Veii said:


> up to CPU , can be different
> You watch HWInfo , TDC usage % - and note the highest TDC you run and then limit it slightly - so it stays in the 98-100% area
> Then check if you see any improvements at all ~ as EDC limits , do lower allcore voltages
> TDC is there to limit peak boost voltages, while PPT is rather a powersuply limiter - although also used as pure TDP draw limit for cooler design
> 
> soo what you need to max out is PPT, Package Power limit and the cTDP limit (both inside AMD CBS , NBIO ~ maybe SMU)
> DF_C-States disabling that , is inside NBIO - SMU Common options
> Powersuply power limit , should be inside AMD CBS , CPU Common options - or also NBIO (set to typical current)
> 
> Last two mentions are to prevent the overboost bug - but Generate C-States has to be enabled
> If not, it will not be able to move anywhere lower than P0 Power profile , which is 3.7 or 3.8ghz ~ while P1 is near 2.1ish and P2 near 980mhz
> The lowest P-State and the states in between , depend on this Generate C-States flag ~ and are needed , in order to manage powerbudget better = higher boost
> DF-C States or C6 states (translated) ~ are there to fully hibernate cores (but the wakeup from hibernation triggers an infinite boost and can by attempts also draw 1.55v @ 55ghz target)
> on OC_Mode, this can peak to 1.68v @ 5.9ghz (applied)
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> We worked towards powerplan optimizations pre-dLDO era , as it made sense & i worked on a powerplan to utilize overboost for a positive thing - with fixed limits
> But these fixed limits, bugged CPPC tags
> Soo until we have a clear path to take & AMD fixes their overboost mess
> It is more than recommended ~ to disable DF_C-States & Set powersuply Idle control to typical current
> 
> Hydra needs it set to low current with DF-C states enabled
> But Hydra & CTR (pic above is Hydra) does enforce DF-CStates enabled , in order to fully hibernate cores and share more powerstates in between
> Else AMD still "locked" the ability to set per clock frequency, without pushing anything near it upwards too ~ oor bugging it out to drop to 3.7ghz p0 state
> * which btw still is in works, but hydra future i should not talk about
> 
> We have to use TDC now, as limiting EDC - does limit (x)GMI link speed limits - and in general slows down cache & access time latency
> EDC needs to be open fully.
> There are several stages of limiters - PBO are the first stage and if it was me ~ i'd put all to infinite
> But you know, Matisse performed better with fixed limits as they lowered voltage usage ~ soo maybe it still can work out , but just with TDC


Tuning PBO before this thread I just raised PPT and EDC to keep them att 98-100% and set TDC 40A below EDC, because I read that somewhere. Ended up at 185 130 170.

But now I guess I need to get an unlocked bios - because I cant find half of those settings :/

I tried 200 130 700 though and TDC maxed out at 121,753A with HWinfo polling 200ms so I guess a 123-125 TDC limit should be just about right? Or should I just scrap it untill I can set PPL, cTDP and DF-C States?



http://imgur.com/a/Towrcz9


----------



## 1s1mple

Frosted racquet said:


> @1s1mple which programs had shown errors for the defective kit? TM5 or?


I used memtest86 and it showed a **** ton of errors.


----------



## MrHoof

@Luggage You must have a good cooling solution, my 5800x with "just" a u12a even at 100% fan speed will hit like 90°C at 105a TDC.


----------



## Luggage

MrHoof said:


> @Luggage You must have a good cooling solution, my 5800x with "just" a u12a even at 100% fan speed will hit like 90°C at 105a TDC.


I have a 1260 supernova out on my glaced balcony, TechN water block and LM (though I think the LM application isn’t soo good - gonna lap the IHS next tear down)

Edit: *** - what broke 80C? Halfway through that session after p95, y-cruncher and Linpak nothing had topped 75C so I stopped looking at temps >_<


----------



## Skull_Angel

Passing flat 15 with previous settings was a "fluke", as soon as the dimms hit 43C TM5 started with the random errors again. Timings are probably too tight and it's possible(likely) that the kit is using the older RC B-die; they seem to take everything I can "reasonably" throw at them until they warm up with borderline timings. Tried reducing voltages, but that just added instability. Tried to bruit-force it by adding voltage, but no increase in heat capacity. So I'm beginning to reduce timings and testing with warmer ambient temps to see what's needed for marathon-level stress loads.

@Veii That makes sense with tWR. My board auto-corrected to an odd number when I tried tRTP*4; I re-corrected trying tRTP*3, but no improvements were found.

Debating swapping kits if I can't reach some goals, but prices have jumped by ~1/3 from when I originally purchased 😒


----------



## MrHoof

Luggage said:


> I have a 1260 supernova out on my glaced balcony, TechN water block and LM (though I think the LM application isn’t soo good - gonna lap the IHS next tear down)
> 
> Edit: *** - what broke 80C? Halfway through that session after p95, y-cruncher and Linpak nothing had topped 75C so I stopped looking at temps >_<


well thats actuly really good , maybe cap it to somthing around 115a and u should be good thats still plenty for a 5800x I would say.


----------



## VPII

Ezalor said:


> Getting 4x8 FlareX in 3800 C16 flat GDM off 1T is not very common, absolutely impossible for me. Some tips:
> 
> Your RTTs seem to be for a 2x8 setup, i would try 7/3/3 or 7/3/1
> 
> ProcODT 36.9
> 
> And the thing that probably makes the biggest difference, rRCDRD from 16 to 18
> 
> And if done in the above order, and still not working, go from 1T to 2T


Hi @Ezalor when checking in the bios to change I only see the readings in ohm. Not sure what to set it as, tried several times even tried to copy the setting I had when it worked but struggle to get the same.

Sent from my Hisense Infinity H40 Lite using Tapatalk


----------



## Skull_Angel

VPII said:


> Hi @Ezalor when checking in the bios to change I only see the readings in ohm. Not sure what to set it as, tried several times even tried to copy the setting I had when it worked but struggle to get the same.
> 
> Sent from my Hisense Infinity H40 Lite using Tapatalk


Values commonly used (6/3/3, 7/3/3, ect) are based off RZQ/#; most of these AMD boards still seem to use RZQ=240, so 240/# is what you're looking at. 7/3/3 should be 34.29(34.3)/80/80.


----------



## mongoled

Luggage said:


> I have a 1260 supernova out on my glaced balcony, TechN water block and LM (though I think the LM application isn’t soo good - gonna lap the IHS next tear down)
> 
> Edit: *** - what broke 80C? Halfway through that session after p95, y-cruncher and Linpak nothing had topped 75C so I stopped looking at temps >_<


The Techn waterblock is badly suited for LM !

You will get better temps using thermal paste.

Its been designed to exagerate the bow in the center increasing the pressure on the CORE/IOD but that means the area surrounding the centered bow is slightly elevated.

The LM is too thin to fill this gap.

Reach out to TechN and ask them if you can "purchase" something that will help when using LM.

I was advised by them not to lap the coldplate.


----------



## Dodgexander

Veii said:


> Why do you try to copy settings that are not for average users
> Beyond 1.54v is dangerous if you don't know what you do
> Maybe it's not a good idea to try and copy my settings
> 
> also are you sure your CPU can even reach 2100 FCLK ?
> ~ is it a bugged Dual CCD 6,8 core ?
> 
> 
> Code:
> 
> 
> CLDO VDDP Voltage:  0.9
> 1.05V SB Voltage : 1.05
> 2.5V SB Voltage : 2.5
> CPU 1.80V Voltage : 1.93
> VTTDDR Voltage : half of VDIMM
> VPP_MEM Voltage :2.45
> VDDP Standby Voltage : 0.86 (but it wont allow you, soo 0.9)
> 
> You have cLDO_VDDP in the screenshot
> But again, unlikely a good idea to copy them
> 
> tCKE 13 only works on 2100 MCLK , but will not on higher or lower
> RTTs work but only with this voltage and only because 2x8 GB
> 
> Values are SET values not GET soo,
> VDDG CCD 1020mV
> VDDG IOD 1120mV
> SOC 1.25v with Loadline droop to 1.24375v
> * only SOC is GET, because loadlines exist. cLDO_VDDP & VDDG have no loadline
> 
> Good luck
> 
> He runs very high PBO or CTR
> Well configured
> 
> Same thing but , tWR = tRTP*2 , is an easy ruleset - correct would be tRTPns = single (works with two) digit decimal divider inside tRFCns range
> soo sometimes value 8 works, sometimes value 9 works - depends by MCLK what this placeholder value translates in ns
> 
> tWR *2 is for DR, can help and was used before.
> but tWR = tRTP *2 is the "correct" one. Doubling tWR is just a stability thing for Dual Rank (capacity independent)
> 
> 
> Higher MCLK needs higher cLDO_VDDP ~ it's purely MCLK related and has tiny to no connection towards FCLK
> VDDG IOD the IO-Die and mostly what dictates higher Fabric clock stability
> 
> VDDG CCD is voltage-balanced down together with IOD by SOC
> it's fine to keep it lower.
> Since AGESA 1.1.8.X dDLO_Injector exists, and averages voltages out - soo values changed a bit
> But it's fine to keep it as low as y-cruncher allows to (as low as you can afford it)
> 
> 1.8V rail is needed to be pushed for FCLK stability - but pushing this one too much, messes up CAD_BUS, RTT's & can mess up other voltages
> Aka one of the two 2.5v rails
> It can also cause cores to crash - soo mess up CCD voltage.
> Yet slight bump to at least 1.83v is needed. Bellow 1.86 you shouldn't feel any negative results. 1.93 is questionable, 1.96 and higher surely does issues ~ yet you can just run 2v with sadly unknown peak limits (buut you can run it ~ maybe can find a use for XOC)
> 
> Part of the message above,
> Higher IOD, higher SOC AMD max overclocking voltage and onwards
> 
> Least amount of cLDO_VDDP , soo low procODT can be used
> y-cruncher and OCCT extreme for benchmarks
> Mostly y-cruncher FFT  ~ but run them all for 4 loops (72min)
> And aida64 to catch EDC & Package throttle on latency increases (by lack of voltage & autocorrection)
> 
> EDIT:
> Easiest probably is,
> pushing SOC bellow 1.3v - as that will also cover lack of VDDG (likely bellow 1.25v)
> and then try to slim down vSOC without having big latency increases.
> Then tightening it down till y-cruncher starts to fail & increase VDDG & 1.8v rail ~ till it's stable again
> 
> this happens when CPU overboosts - because DF_C-States are active
> That and Powersupply idle control (typical current) need to be set correspondingly ~ till AMD fixes their issues they're having since dLDO implementation


The complicated aspect, at least for me is how each setting corresponds to each other.
When trying to boot my XMP 4400mhz profile I tried increasing CLDO_vddp but it doesn't help. The system keeps trying to train, 2-3 times and resets settings to default. ULCK is set to 1/2 MCLK but it doesn't post. Even tried 4400mhz XMP OFF with primaries set too 20-20-20-40 and rest auto but it doesn't train. Tried higher vdimm (upto 1.6v), high and low vsoc and low ProcODT but it still doesn't boot. Guides say you can get up to 5000mhz on B-die on Ryzen but my experience is very different.

Either way, I'm happy to tweak 1900mhz FCLK (3800mhz memory) but its guesswork what voltages and resistances to use. I understand from reading here that the aim in having lower resistance is to deliver a cleaner signal when using higher voltage, but_ which resistances correspond to each voltage_? Likewise, in reverse I understand higher resistances are recommended for lower voltages. In your previous (helpful) posts you state try to find the lowest ProcODT you can, presumably so you can keep the signal clean with higher voltage. But most people use 40ohm, some as much as 60.

And then you have CAD Bus termination settings, and bus settings. How do you correspond these with your settings? What is the process of elimination?

When is it necessary to adjust advance termination/advance settings, and how do you find out which are best for your own memory and CPU?


----------



## Ezalor

VPII said:


> Hi @Ezalor when checking in the bios to change I only see the readings in ohm. Not sure what to set it as, tried several times even tried to copy the setting I had when it worked but struggle to get the same.
> 
> Sent from my Hisense Infinity H40 Lite using Tapatalk


Skull_Angel's reply has the answer about the ohms. Have you tried the other things, and no difference? Procodt, trcdrd, trfc?


----------



## Luggage

mongoled said:


> The Techn waterblock is badly suited for LM !
> 
> You will get better temps using thermal paste.
> 
> Its been designed to exagerate the bow in the center increasing the pressure on the CORE/IOD but that means the area surrounding the centered bow is slightly elevated.
> 
> The LM is too thin to fill this gap.
> 
> Reach out to TechN and ask them if you can "purchase" something that will help when using LM.
> 
> I was advised by them not to lap the coldplate.


if my 5800X is as concave as my 3800X was, lapping it will probably help anyway.


http://imgur.com/wL7JMFA


But we will see.

Good thing about this I found out the aquacomputer service was adding 3ns latency.


http://imgur.com/a/tD7HmIm


Bad thing is i lost boost


----------



## Skull_Angel

Bit of bad news; as far as I can tell the heat instability is tied to the primary timings. I just can't get the ram to run stable flat 15 @ 3800 no matter how loose secondaries and tertiaries are when under "harsh" conditions (25C+ ambient). That coupled with earlier voltage and cad bus tweaking failures just means better cooling is necessary; replacing thermal tape might do it, but would still likely fail on hot summer days w/o A/C.

Now for the good news. Flat 16 @ 3800 seems solid all the way up to at least 35C ambient, even with tight secondary and tertiary timings. I'm not sure about pushing temps even further though, this last one had me literally sweating 😂










Just incase of a google search; this is the Gskill FlareX 16GBx2 3200 CL14-14-14-34 1.35v F4-3200C14D-32GFX kit, from research and personal testing they seem to be Samsung B-die/RC-type/Raw Card Revision B1.

The only problem is I can't decide whether to keep pushing and see fow far they'll go or be content and move back to messing with the CPU, lol


----------



## Frosted racquet

Veii said:


> Far to high VDDG voltages, surpasses SOC
> either run 1.1625v SOC or drop them (both) to 1.05v
> Be sure it's y-cruncher stable first.
> 
> There are bad XMP kits (broken) but it's rather your stock setup
> Also please share a Zentimings "DEBUG" screenshot/readout
> 
> EDIT:
> 1800FCLK , 1800MCLK
> should run at
> 900,1000,1000,1100
> VDDP, VDDG , SOC





Frosted racquet said:


> Thanks for the quick reply.
> 
> I posted an old Zen Timings screenshot, sorry. I forgot the new AGESA 1204 changes the default VDDG etc voltages. TM5 screenshot is the most current one, so the errors appeared with the settings below. I've also attached the debug log.
> 
> Currently running y-cruncher to check for errors.



Finished testing y-cruncher ~5 hours, Karhu RamTest ~2000%, HCI MemTest 800+% and no errors. Attached ZenTimings and the log again for convenience. If you have any further suggestions I'd be thankful.
EDIT: sometimes I get this error when starting TM5 with Extreme anta777 config:










@1s1mple I ran memtest86 when I bought the PC half a year ago, ran it again for 1 cycle and it didn't find any errors. I don't have bluescreens or any other obvious instability. The only reason I found out about TM5 errors was because I wanted to OC my RAM and realized there are errors with default settings.


----------



## Audioboxer

GP-Ultimate 0.5mm thermal pads arrived, so time to pry open my 4000C14 kit


----------



## Audioboxer

To say that the RipJaws heatinks come off easily would be an understatement, I think I could blow them off 🤣

PCB looks interesting, not sure I've seen one with that extra chip in the middle before


----------



## Mach3.2

Audioboxer said:


> To say that the RipJaws heatinks come off easily would be an understatement, I think I could blow them off 🤣
> 
> PCB looks interesting, not sure I've seen one with that extra chip in the middle before


They are probably using the same PCB for both Ripjaw and Trident Z RGB SKUs, with the difference that an RGB controller + LEDs will populate those empty pads for the Trident Z RGB SKU.









G.SKILL Trident Z Neo DDR4-3600 MHz CL16 2x8 GB Review


With a market that is flooded with "Ryzen Optimized" memory kits, it can be hard for a particular kit to stand out. The G.SKILL Trident Z Neo does just that. With a striking new take on the award winning Trident Z design and specifications that are as good as it gets for Ryzen, the Trident Z Neo...




www.techpowerup.com


----------



## Audioboxer

Mach3.2 said:


> They are probably using the same PCB for both Ripjaw and Trident Z RGB SKUs, with the difference that an RGB controller + LEDs will populate those empty pads for the Trident Z RGB SKU.


Ah yeah, good point. The gold trimmed square in the middle just caught my eye.

Looks like they are hand binned as well, what looks to be white writing on some chips. Thought it was glue at first but it's definitely marked in some way.

I can confirm 0.5mm is perfect for the Bykski ram block.


----------



## Audioboxer

Did a quick run of TM5 with just the heatsink swap, temps with RipJaws heatsinks were around 40~41 degrees, sometimes nearer 42 depending on ambient. So looking at a 4~6 degree improvement on air.

Question I do have though is, is it normal for one DIMM to be around a degree higher than the other or might that suggest a screw needs tightened/thermal pad placement checked?

For the thermal pads I just kept the whole 120mm strip as is and ran it across the memory chips. Then the block screws on. No gluing needed.

If watercooling maintains mid 30s (under TM5) I'll be happy, it will mean 1 less fan running!


----------



## Luggage

Audioboxer said:


> Did a quick run of TM5 with just the heatsink swap, temps with RipJaws heatsinks were around 40~41 degrees, sometimes nearer 42 depending on ambient. So looking at a 4~6 degree improvement on air.
> 
> Question I do have though is, is it normal for one DIMM to be around a degree higher than the other or might that suggest a screw needs tightened/thermal pad placement checked?
> 
> For the thermal pads I just kept the whole 120mm strip as is and ran it across the memory chips. Then the block screws on. No gluing needed.
> 
> If watercooling maintains mid 30s (under TM5) I'll be happy, it will mean 1 less fan running!












I guess so.

And now you made me order a ram-block. tsk tsk tsk


----------



## VPII

Ezalor said:


> Skull_Angel's reply has the answer about the ohms. Have you tried the other things, and no difference? Procodt, trcdrd, trfc?


HI there, I tried it all but still the same issue. Can you do me a favour and just give me the link to the correct TM5 to test the memory with. I know that my cpu with PBO and -25 for all core curve optimizer works and is stable. What I have done is to set the NO to RZQ/7 wr to off and Park to Rzq/5 which is what it was when it worked. I also set tCKE to 24 where it was before, even though I know 1 would work taken my 20 000% Karhu memtest.


----------



## Luggage

VPII said:


> HI there, I tried it all but still the same issue. Can you do me a favour and just give me the link to the correct TM5 to test the memory with. I know that my cpu with PBO and -25 for all core curve optimizer works and is stable. What I have done is to set the NO to RZQ/7 wr to off and Park to Rzq/5 which is what it was when it worked. I also set tCKE to 24 where it was before, even though I know 1 would work taken my 20 000% Karhu memtest.


"-25 all core CO on a 5950X stable"(sic) - _are you sure?_
What boost override are you running?


----------



## TimeDrapery

VPII said:


> HI there, I tried it all but still the same issue. Can you do me a favour and just give me the link to the correct TM5 to test the memory with. I know that my cpu with PBO and -25 for all core curve optimizer works and is stable. What I have done is to set the NO to RZQ/7 wr to off and Park to Rzq/5 which is what it was when it worked. I also set tCKE to 24 where it was before, even though I know 1 would work taken my 20 000% Karhu memtest.


@VPII 

Why set tCKE to 24? At 3800MT/s...?


----------



## Audioboxer

Luggage said:


> View attachment 2526236
> 
> 
> I guess so.
> 
> And now you made me order a ram-block. tsk tsk tsk


I suspect water temps will be around the same as the air temps I posted, albeit without a fan running at 100% lol.

Will fix the loop up tommorrow, adding my new radiator at the same time so will take a few hours.

Once watercooled I might take a stab at tCL13 again.


----------



## Joe Flores

Audioboxer said:


> Did a quick run of TM5 with just the heatsink swap, temps with RipJaws heatsinks were around 40~41 degrees, sometimes nearer 42 depending on ambient. So looking at a 4~6 degree improvement on air.
> 
> Question I do have though is, is it normal for one DIMM to be around a degree higher than the other or might that suggest a screw needs tightened/thermal pad placement checked?
> 
> For the thermal pads I just kept the whole 120mm strip as is and ran it across the memory chips. Then the block screws on. No gluing needed.
> 
> If watercooling maintains mid 30s (under TM5) I'll be happy, it will mean 1 less fan running!


Yeah one DIMM is usually always a bit hotter, due to heat density I would assume


----------



## musician

Audioboxer said:


> Question I do have though is, is it normal for one DIMM to be around a degree higher than the other or might that suggest a screw needs tightened/thermal pad placement checked?


Yes it´s normal, it as well depends on a case airflow. For me, usually the 1st module closest to the front case doors where are take in fans, is about 1°C colder.


----------



## Ezalor

VPII said:


> HI there, I tried it all but still the same issue. Can you do me a favour and just give me the link to the correct TM5 to test the memory with. I know that my cpu with PBO and -25 for all core curve optimizer works and is stable. What I have done is to set the NO to RZQ/7 wr to off and Park to Rzq/5 which is what it was when it worked. I also set tCKE to 24 where it was before, even though I know 1 would work taken my 20 000% Karhu memtest.


Sorry, I do not use tm5 so i cannot help you with that. You could also post a good pic of your zentimings of now. You also need to state whether your (bad) 7/0/5 is provably better or worse through more or less errors than 7/3/3. It is not a good idea to chase a solution on 7/0/5, best idea is to try to find another source of the problem, starting with trying flat 18's.

Also leaving 1T command rate and do 2T.


----------



## RosaPanteren

What power draw are 5950x users seeing when running Y-cruncher?

I'm on a x570 unify and setting PBO to advanced and limits to auto yields PPT of 280w, EDC 215A and TDC 185A running YC

Pic is for ref. and show a bit lower values



Spoiler: HwInfo















If I set limits to manual PPT 300, TDC 240 and EDC 600, I get nowhere near the same power draw, temps are 10c lower and CB scores and other bench tests yield lower score.....

This makes me think the auto setting is bugged somehow giving "unlimited" settings, or maybe the manual setting is the one which is and enforce some kind of restrictions....?

Is it normal and within reasonable safety to let the the cpu draw close to 280w? I got appropriate cooling and temps doesn't exceed 80c for 6 hour run of YC.

PBO curve is also set quite aggressiv


----------



## Requiem4u

Audioboxer said:


> Smart! I might try this just to see what happens for me, because 54ns looks to be a pretty hard wall for the 5950x ran normally. Lowest I've recorded is 53.9ns in AIDA64. Or maybe it was 53.8, just under 54 anyway.
> 
> The affinity thing is done via task manager isn't it?


Try Process Lasso free. You can set affinity and/or priority automatically for different programs. Just create rules.

Someone asked how to disable windows defender? Defender Control is small and easy program for that. I just don't remember to enable it.


----------



## SneakySloth

Does anyone know what's the max safe voltage for Hynix AFRs? Same as C/DJR?


----------



## XPEHOPE3

VPII said:


> Can you do me a favour and just give me the link to the correct TM5 to test the memory with.


Config here, link for distrib at start of _that_ thread or in google.


Requiem4u said:


> Try Process Lasso free.


It adds at least 1ns of latency.


----------



## Requiem4u

XPEHOPE3 said:


> Config here, link for distrib at start of _that_ thread or in google.
> It adds at least 1ns of latency.


Really? Haven't seen that much myself. You can shut down main program (GUI). Core engine, Governor is enought to set rules.


----------



## Veii

SneakySloth said:


> Does anyone know what's the max safe voltage for Hynix AFRs? Same as C/DJR?


AFR if 19nm , around 1.48
if 18mm around 1.46
if 20mm like MFR - 1.62v

AFR i can remember capped out at 3600MT/s - but that was long time ago
soo maybe we learned more since then


----------



## Veii

RosaPanteren said:


> This makes me think the auto setting is bugged somehow giving "unlimited" settings, or maybe the manual setting is the one which is and enforce some kind of restrictions....?


FIT-PRE throttles, as cores request too much VID (usually nothing new with PBO overvolting the unit)
But cache is boosting how it has to
Read here,








CoreCycler - tool for testing Curve Optimizer settings


Unless some BIOS setting is messed up, I'm pending to think that Core 2 is faulty. Which is a big problem considering is 1/1.... Yes it does happen. The gap with the other offsets should not be too high, though. If they are the best cores could be valuable, you have to bench them. Doesn't...




www.overclock.net


----------



## majsterz

Hello, i updated to the newest bios( from 3103 to 4603 ) on Crosshair VII Hero(WiFi) and applied overclock to my memory, but CLDO VDDP voltage keep automatically set to 1,1V even if i adjust it manually to 0,9V. Is it save for Zen2(3800x) cpu? Right now i set it to auto but it still on 1,1V.


----------



## Frosted racquet

Frosted racquet said:


> Finished testing y-cruncher ~5 hours, Karhu RamTest ~2000%, HCI MemTest 800+% and no errors. Attached ZenTimings and the log again for convenience. If you have any further suggestions I'd be thankful.
> EDIT: sometimes I get this error when starting TM5 with Extreme anta777 config:
> View attachment 2526224
> 
> 
> 
> @1s1mple I ran memtest86 when I bought the PC half a year ago, ran it again for 1 cycle and it didn't find any errors. I don't have bluescreens or any other obvious instability. The only reason I found out about TM5 errors was because I wanted to OC my RAM and realized there are errors with default settings.


Decreased RAM frequency and left latencies on auto, 3200 and 3466 don't show errors in TM5 anymore with zentimings below. Any suggestions what to change so that 3600 XMP works?


----------



## Veii

Frosted racquet said:


> Any suggestions what to change so that 3600 XMP works?


VDIMM (1.38) and tRDWR too low - give it +2
Also GDM is an issue, run 40-20-30-24 (CAD_BUS) and run 2T instead of GDM


----------



## VPII

Ezalor said:


> Sorry, I do not use tm5 so i cannot help you with that. You could also post a good pic of your zentimings of now. You also need to state whether your (bad) 7/0/5 is provably better or worse through more or less errors than 7/3/3. It is not a good idea to chase a solution on 7/0/5, best idea is to try to find another source of the problem, starting with trying flat 18's.
> 
> Also leaving 1T command rate and do 2T.


Hi there, I will try to 2T command rate instead of 1T to see if it worked as it is the only things I have not tried. Setting 80ohms for the wr, park or whatever does not work, the system gives a memory fail, I did try it but it won't start up. Here is the zentimings for my current setup.

@Luggage -25 all core has always worked for me. I did not want to try each core little by little, I start -10 all core and ran OCCT and when I passed I went to -15 and so on till I got to -25 and it passed, however, it does not pass now and the issue is my memory as it does pass when I set the memory ot DOCP or 3200 CL14.


----------



## Henry Owens

LxT1N said:


> Hi im new on ram oc this are my kit F4-3600C14-32GTZN + Asus Rog Crosshair VIII Dark Hero with Bios 3801 + Ryzen 5800x what are better 3800CL14 - 3800CL16 or 3600CL14?
> 
> My setting on my 5800x are PBO + Curve Optimizer
> 
> PPT : 120
> TDC : 85
> EDC : 130
> 
> Curve Optimizer : - 30 on all core
> 
> VDDSOC Voltage = 1.125V
> DRAM = 1.45V
> VDDG CCD Voltage = 1.05V
> VDDG IOD Voltage = 1.05V
> CLDO VDDP Voltage = 0.95V
> 
> View attachment 2525919
> 
> 
> can someone help me how i can tunning my ram kit ?


From your picture your vddg is 0.95 not 1.05


----------



## Veii

VPII said:


> @Luggage -25 all core has always worked for me. I did not want to try each core little by little, I start -10 all core and ran OCCT and when I passed I went to -15 and so on till I got to -25 and it passed, however, it does not pass now and the issue is my memory as it does pass when I set the memory ot DOCP or 3200 CL14.


This includes y-cruncher , for the global CO magnitude change
Use -2 steps instead -5


----------



## error-id10t

This is what I see on my system. Simple question; why can't I get it to boost to 4.85 as set? First AMD system so no idea really. I'm not hitting 1.45v which seems to be a limiter, so is it ProcHot which is set to 65 degrees and there's no way to change that?

I do hit it on single core but do these chips not do the same on multi?

FIT VID limit 1.45v
FIT PRE 1.45v
Latchup 1.45v
ProcHot 65
THM limit 95


----------



## Veii

error-id10t said:


> I do hit it on single core but do these chips not do the same on multi?


1.4VID is your limit , and if it hits 65c it will also PROCHOT throttle
CoreCycler - tool for testing Curve Optimizer settings and onwards


error-id10t said:


> so is it ProcHot which is set to 65 degrees and there's no way to change that?


 Blame AMDs crazy ideas about "low quality binning"
5800X has a limit of 105c


----------



## Luggage

VPII said:


> Hi there, I will try to 2T command rate instead of 1T to see if it worked as it is the only things I have not tried. Setting 80ohms for the wr, park or whatever does not work, the system gives a memory fail, I did try it but it won't start up. Here is the zentimings for my current setup.
> 
> @Luggage -25 all core has always worked for me. I did not want to try each core little by little, I start -10 all core and ran OCCT and when I passed I went to -15 and so on till I got to -25 and it passed, however, it does not pass now and the issue is my memory as it does pass when I set the memory ot DOCP or 3200 CL14.
> View attachment 2526318


So you didn't test from crashing to stable and you only tested with OCCT? Can you run Blender?
You change FCLK when you change memory speed as well.


----------



## Ezalor

VPII said:


> Hi there, I will try to 2T command rate instead of 1T to see if it worked as it is the only things I have not tried. Setting 80ohms for the wr, park or whatever does not work, the system gives a memory fail, I did try it but it won't start up. Here is the zentimings for my current setup.
> 
> @Luggage -25 all core has always worked for me. I did not want to try each core little by little, I start -10 all core and ran OCCT and when I passed I went to -15 and so on till I got to -25 and it passed, however, it does not pass now and the issue is my memory as it does pass when I set the memory ot DOCP or 3200 CL14.
> View attachment 2526318


Hello.
Again, i need to know the difference in quantity of errors between your setup and my suggestions, no way to help you otherwise. It is not a good idea to revert back to the starting point.

I have mad a pic with the old suggestions and a few new for you to try. If someone else has any comments about those, please pitch in 

Edit:
Forgot: tRRDS 5 , tRRDL 7


----------



## Luggage

Veii said:


> up to CPU , can be different
> You watch HWInfo , TDC usage % - and note the highest TDC you run and then limit it slightly - so it stays in the 98-100% area
> Then check if you see any improvements at all ~ as EDC limits , do lower allcore voltages
> TDC is there to limit peak boost voltages, while PPT is rather a powersuply limiter - although also used as pure TDP draw limit for cooler design
> 
> soo what you need to max out is PPT, Package Power limit and the cTDP limit (both inside AMD CBS , NBIO ~ maybe SMU)
> DF_C-States disabling that , is inside NBIO - SMU Common options
> Powersuply power limit , should be inside AMD CBS , CPU Common options - or also NBIO (set to typical current)
> 
> Last two mentions are to prevent the overboost bug - but Generate C-States has to be enabled
> If not, it will not be able to move anywhere lower than P0 Power profile , which is 3.7 or 3.8ghz ~ while P1 is near 2.1ish and P2 near 980mhz
> The lowest P-State and the states in between , depend on this Generate C-States flag ~ and are needed , in order to manage powerbudget better = higher boost
> DF-C States or C6 states (translated) ~ are there to fully hibernate cores (but the wakeup from hibernation triggers an infinite boost and can by attempts also draw 1.55v @ 55ghz target)
> on OC_Mode, this can peak to 1.68v @ 5.9ghz (applied)
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> We worked towards powerplan optimizations pre-dLDO era , as it made sense & i worked on a powerplan to utilize overboost for a positive thing - with fixed limits
> But these fixed limits, bugged CPPC tags
> Soo until we have a clear path to take & AMD fixes their overboost mess
> It is more than recommended ~ to disable DF_C-States & Set powersuply Idle control to typical current
> 
> Hydra needs it set to low current with DF-C states enabled
> But Hydra & CTR (pic above is Hydra) does enforce DF-CStates enabled , in order to fully hibernate cores and share more powerstates in between
> Else AMD still "locked" the ability to set per clock frequency, without pushing anything near it upwards too ~ oor bugging it out to drop to 3.7ghz p0 state
> * which btw still is in works, but hydra future i should not talk about
> 
> We have to use TDC now, as limiting EDC - does limit (x)GMI link speed limits - and in general slows down cache & access time latency
> EDC needs to be open fully.
> There are several stages of limiters - PBO are the first stage and if it was me ~ i'd put all to infinite
> But you know, Matisse performed better with fixed limits as they lowered voltage usage ~ soo maybe it still can work out , but just with TDC


So I got an unlocked 1203C bios and I'm not sure if I missed something but so far "tuned PBO + cooling" beats "unlimted EDC"

5800X
PPT cTDP Package power limit: 350
DF_C states disabled
EDC: 700
scalar: x10
BO:+200
CO: -15 27 27 15 30 15 27 30
From stresstest bonansa TDC should max out at 122A

TDC : BM CBr23 real time average of 5
130 : 16460 @ <60C
122: 16426 @ <60C
120 : 16475 @ <60C
105 : 16440 @ <60C
90 : 16463 @ <60C
80 : 16195 @ <53C <- now TDC is low enough to make a difference

PBO 185 124 166 : 16461 @ <61C
PBO 170 123 160 : 16466 @ <61C
PBO 190 126 170 : 16429 @ <61C
PBO 160 126 160 : [email protected] <62C

PBO 144 95 140 : 16399 @ <60C

RESET - 
PPT cTDP Package power limit: auto
PBO 170 124 166 : 16539 @ <60C


----------



## Audioboxer

Tried dropping my DD's again seeing as I'm at the end of my adventures with this profile and I also wanted to do a full TM5 run on Windows 11. Everything seems to be fine 

Now to drain the loop 

*edit* - Just noticed my BIOS auto'd VDDP to 1.09v again   Changing the DD's must have caused training to do that for whatever reason. Will have to manually set back to 0.9v and try again xD


----------



## deadfelllow

Guys GDM or 2T?? Which one is better?


----------



## umea

Start with GDM off 2T and work on getting that stable first, then see if you can get 1T working. 2T is better than GDM on.


----------



## umea

Audioboxer said:


> Tried dropping my DD's again seeing as I'm at the end of my adventures with this profile and I also wanted to do a full TM5 run on Windows 11. Everything seems to be fine
> 
> Now to drain the loop
> 
> *edit* - Just noticed my BIOS auto'd VDDP to 1.09v again   Changing the DD's must have caused training to do that for whatever reason. Will have to manually set back to 0.9v and try again xD


So it seems that the bin is just that much better on your RAM that you went from the same problem as me (infinite 6's instantly from tRCDRD 14) to being able to get it stable. Very interesting, now I want to test the 16gb and the 32gb versions...

That is to say that with 2v bz got the 16gb kit running 4800c14-13-8-12, not sure about stability though. but considering a 5700g can handle up to 2467fclk on some chips it might be pretty fun


----------



## error-id10t

Thanks very much, have already done CO.


Veii said:


> 1.4VID is your limit , and if it hits 65c it will also PROCHOT throttle
> CoreCycler - tool for testing Curve Optimizer settings and onwards
> Blame AMDs crazy ideas about "low quality binning"
> 5800X has a limit of 105c


Thanks a lot, read many of your posts and appreciate. Realise I've posted in the wrong thread so will post in the CO thread now on.


----------



## umea

Anyone have info on 32gb vs 16gb for purely gaming at 1080p high FPS? I play mostly competitive shooters. Curious about performance difference if there is any at all.


----------



## deadfelllow

Any ideas? I turned off the GDM recently.
Maybe i can lower tRFC a little like 260-ish or even 270
I can try to lower trp + tras = trc could be less.
maybe cl 15 trcdrd 15 ??? also tCWL?

for those who cannot see my voltages
soc = 1.15
IOD = 1.07
VDDG = 1
VDDP = 0.9
DIMM = 1.55 vTT = 0.775 

Thanks.


----------



## Luggage

Veii said:


> 1.4VID is your limit , and if it hits 65c it will also PROCHOT throttle
> CoreCycler - tool for testing Curve Optimizer settings and onwards
> Blame AMDs crazy ideas about "low quality binning"
> 5800X has a limit of 105c


My prochot starts to limit at 62C.


----------



## Audioboxer

umea said:


> So it seems that the bin is just that much better on your RAM that you went from the same problem as me (infinite 6's instantly from tRCDRD 14) to being able to get it stable. Very interesting, now I want to test the 16gb and the 32gb versions...
> 
> That is to say that with 2v bz got the 16gb kit running 4800c14-13-8-12, not sure about stability though. but considering a 5700g can handle up to 2467fclk on some chips it might be pretty fun


Seems I just got unlucky with my 3600C14 kit as I've seen people pushing them to 3800 flat 14 just fine. Especially the 3600 14-14-14-14 rated kits.

But yeah it shows how much tRCDRD 14 is silicon based at 3800. Tbf I'd be tearing my hair out if a 4000C14 kit couldn't do 3800 flat 14 🤣 My estimate is it can do it fine at 1.5V which is really good. One of these days I will try dipping under 1.5v to see if its stable. To do that though I'll need to loosen up some secondaries and tRFC.

The next project is what the heck do I need to run to try and stabilise tCL13. I can even boot tRCDRD 13 but lol at trying to stabilise it at 3800.

In other news I absolutely hate pipe bending and cutting but I should be back in action soon. Putting the Bykski waterblock on top is a little awkward with the screw setup, but after some trial and error I'm heatink pasted and block screwed down.


----------



## Sam_Oslo

VPII said:


> -25 all core has always worked for me. I did not want to try each core little by little, I start -10 all core and ran OCCT and when I passed I went to -15 and so on till I got to -25 and it passed, however, it does not pass now and the issue is my memory as it does pass when I set the memory ot DOCP or 3200 CL14.


Interesting statement about the effect of RAM/FCLK speed on CO degradation. But maybe the higher Uncore and FCLK are degrading your CO? 

I have noticed something similar on my 5700G, but these APUs hit much higher FCLK and this issue becomes more visible. It's a new build and I'm stll experimenting, but my CO needs about 5-6 more stepts to get form 3600Mhz-RAM, 1800-FCLK to 4266Mhz-RAM, 2133-FCLK.

This CO is a magi-box and nobody knows what's really happening in there, so I'm not sure if RAM or FCLK is the source of the problem. but I'm suspecting and focusing on the FCLK, at least for now. So maybe the higher FCLK is degrading your CO?


----------



## Frosted racquet

Veii said:


> VDIMM (1.38) and tRDWR too low - give it +2
> Also GDM is an issue, run 40-20-30-24 (CAD_BUS) and run 2T instead of GDM


Thanks again for the input. It seems that fixing VDDG and VDIMM voltages is sufficient to pass a couple hours of 1usmus and extreme anta777 configs. Also thanks to @SneakySloth for suggesting increasing VDIMM: I tried that before but it seems VDDG was also a problem.

Now I can try to actually tweak the settings further seeing that I have a stable base. This is my plan, after reading this guide: MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper
My goal is to keep RAM at 3600 while tuning timings and keeping voltage increases to a minimum as I'm running in and ITX case and temps can be high.


Spoiler






Code:


VSOC         1.1V
CLDO VDDP     0.9V
VDDG CCD     1V
VDDG IOD     1V
VDIMM    1.38V
----
tRRDS        6
tRRDL        6
tFAW        24
tWR        16
----
tRFC=The next tRFC you should try is half of default. If that is unstable, you know that your lowest tRFC is somewhere between 315 and 630, so you try the midpoint ((315 + 630) / 2 = 472.5, round down to 472). If that is stable, you know that your lowest tRFC is between 315 and 472, so you try the midpoint and so on.
----
tWTRS        4
tWTRL        12
tRTP        12
tCWL        tCL
----
tRDRDSCL    4
tWRWRSCL    4
----
Drop tCL by 1 until it's unstable.
If GDM is enabled drop tCL by 2.
Drop tRCD by 1 until unstable. Repeat with tRP.
Note: More IMC voltage may be necessary to stabilise tighter tRCD.
Set tRAS = tRCD(RD) + tRTP. Increase if unstable.
Set tRC = tRP + tRAS. Increase if unstable.
Increase tREFI until it's unstable. The binary search method explained in finding the lowest tRFC can also be applied here.
tREFI    32768 (Safe)
----
GDM Off, 1T CR, otherwise pure 2T


----------



## Audioboxer

Waterblock installed, just need to wait on a corsair adapter coming to hookup the RGB to my commander pro. Then we can go faster! Gotta clean those tubes as well, fingerprints everywhere from the tear down earlier 

Don't know if I'm the biggest fan of the screw down ram block approach, but I guess it's the cheapest way to do it.










Temps seem good, but I still have some airlocks in the loop at the moment. 4 radiators now  At least I can run TM5 without a fan at 100%!!! I'm sure over the course of 25 cycles the temps might creep up a bit more, but low to mid 30s and I'm happy.


----------



## domdtxdissar

Audioboxer said:


> Waterblock installed, just need to wait on a corsair adapter coming to hookup the RGB to my commander pro. Then we can go faster! Gotta clean those tubes as well, fingerprints everywhere from the tear down earlier
> 
> Don't know if I'm the biggest fan of the screw down ram block approach, but I guess it's the cheapest way to do it.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Temps seem good, but I still have some airlocks in the loop at the moment. 4 radiators now  At least I can run TM5 without a fan at 100%!!! I'm sure over the course of 25 cycles the temps might creep up a bit more, but low to mid 30s and I'm happy.


Very nice looking rig 

Seems like you are getting a ~6 degree delta between idle and load on the ram, so nothing earth shattering in regards to temps, but i'm sure its alot more silent then say a "ALSEYE RAM Cooler" at above 80% fan speed..

For a comparison, i was getting a 7 degree delta between idle and full load with the ALSEYE at 100% fan speed @ 1.54 vdimm on *8gb* stock trident neo sticks (dont know how much difference there is cooling-wise in regards to single rank 8gb and dual rank 16gb)


----------



## Audioboxer

domdtxdissar said:


> Very nice looking rig
> 
> Seems like you are getting a ~6 degree delta between idle and load on the ram, so nothing earth shattering in regards to temps, but i'm sure its alot more silent then say a "ALSEYE RAM Cooler" at above 80% fan speed..
> 
> For a comparison, i was getting a 7 degree delta between idle and full load with the ALSEYE all 100% fan speed @ 1.54 vdimm on dual 8gb stock trident neo sticks
> View attachment 2526403


If I can do a 25 cycle and only hit 33.5 degrees I'd be delighted. Will give it a go.

Your DIMMs are slightly different temps as most people's are but interesting it's soo little. Unless DR is what can cause a degree difference.

That RAM cooler actually looks pretty awesome. 2 DIMM boards are again the troublesome point with some of the fancy air coolers.


----------



## Skull_Angel

Luggage said:


> So I got an unlocked 1203C bios and I'm not sure if I missed something but so far "tuned PBO + cooling" beats "unlimted EDC"
> 
> 5800X
> PPT cTDP Package power limit: 350
> DF_C states disabled
> EDC: 700
> scalar: x10
> BO:+200
> CO: -15 27 27 15 30 15 27 30
> From stresstest bonansa TDC should max out at 122A
> 
> TDC : BM CBr23 real time average of 5
> 130 : 16460 @ <60C
> 122: 16426 @ <60C
> 120 : 16475 @ <60C
> 105 : 16440 @ <60C
> 90 : 16463 @ <60C
> 80 : 16195 @ <53C <- now TDC is low enough to make a difference
> 
> PBO 185 124 166 : 16461 @ <61C
> PBO 170 123 160 : 16466 @ <61C
> PBO 190 126 170 : 16429 @ <61C
> PBO 160 126 160 : [email protected] <62C
> 
> PBO 144 95 140 : 16399 @ <60C
> 
> RESET -
> PPT cTDP Package power limit: auto
> PBO 170 124 166 : 16539 @ <60C


x570 Tomahawk on unmodified 1203b, but on a 5600x. Having similar experiences with tightening EDC (currently testing 94) showing better performance vs unlimited or near limit. I'm having issues with hot cores not liking much CO offsets so it's currently disabled, boost set to 150, and MSI board so CBS menu is largely untouched, but PBO limits are showing similar behavior on air (NH-D15).

Current observations on TDC and EDC relationship are showing me highest gains when EDC is tightened enough to raise TDC values under moderate load (R23) and PPT is kept low enough that VID isn't allowed to reach 1.45v when loaded. Still needs more benchmarking and stability testing, but it's quite frustrating trying to learn the behavior and relationships of these limits.


----------



## Veii

Luggage said:


> So I got an unlocked 1203C bios and I'm not sure if I missed something but so far "tuned PBO + cooling" beats "unlimted EDC"


You do great analytics , ty
But it misses voltage data

As mentioned, free'd up first strage throttling, will increase voltages
Soo your CO will be messed up , and you'll need to increase it likely by -2 on everything
(only if your CO was fine to begin with)

For the analytic part ~ you should've run y-cruncher and note on every of these tests the global requested VID
If VID with PBO appears lower, then it was throttled because of FIT-PRE limits (the voltage wall before FIT-PRE)

Another problem, chained together tests
Unless on an aircooler - water will not react the same way to thermals instantly on a changed setting.
Also different boots might mess up memory training
But Tool.Exe should allow you in windows power draw overrides. For consistent testing without reboots

Sadly open limits will mess up voltages
soo you should note your global VID & your SVI2 applied


----------



## MrHoof

Audioboxer said:


> If I can do a 25 cycle and only hit 33.5 degrees I'd be delighted. Will give it a go.
> 
> Your DIMMs are slightly different temps as most people's are but interesting it's soo little. Unless DR is what can cause a degree difference.
> 
> That RAM cooler actually looks pretty awesome. 2 DIMM boards are again the troublesome point with some of the fancy air coolers.


Well from my experience with 2 SR 8x2GB kits and 1 DR 16x2GB kit temps are not much diffrent at same voltages. But Doms cooler is probably damn loud at 100% fanspeed, u could probably upgrade those fans on the cooler to some noctua ones if you care about the noise.


----------



## Audioboxer

MrHoof said:


> Well from my experience with 2 SR 8x2GB kits and 1 DR 16x2GB kit temps are not much diffrent at same voltages. But Doms cooler is probably damn loud at 100% fanspeed, u could probably upgrade those fans on the cooler to some noctua ones if you care about the noise.


It's more the temp difference between DIMMs I'm talking about. I have about a degree difference. Someone else earlier posted saying not to worry they have the same. Dom's difference between DIMMs is like 0.2~0.5 degrees.

I used decent enough 0.5mm thermal pads, so I think I'm all good there. Didn't use any thermal paste under heatsinks or thermal tape. Pads stay in place just fine with heatsinks being screwed down.

I did paste the top of the heatsinks but that's a no brainer, it needs something to fill the gaps between the metal surfaces.


----------



## Luggage

Veii said:


> You do great analytics , ty
> But it misses voltage data
> 
> As mentioned, free'd up first strage throttling, will increase voltages
> Soo your CO will be messed up , and you'll need to increase it likely by -2 on everything
> (only if your CO was fine to begin with)
> 
> For the analytic part ~ you should've run y-cruncher and note on every of these tests the global requested VID
> If VID with PBO appears lower, then it was throttled because of FIT-PRE limits (the voltage wall before FIT-PRE)
> 
> Another problem, chained together tests
> Unless on an aircooler - water will not react the same way to thermals instantly on a changed setting.
> Also different boots might mess up memory training
> But Tool.Exe should allow you in windows power draw overrides. For consistent testing without reboots
> 
> Sadly open limits will mess up voltages
> soo you should note your global VID & your SVI2 applied


Changed PBO values with RM so no reboots until reset.
Water temp changes very little with these short CB runs, mostly depending on outdoor temperature. (2L water and 1260 rad on balcony).
With Y-cruncher temp will go higher so prochot will throttle, trying to avoid that complication.
Can I use the voltage reading from Benchmate or do I have to run normal priority and have HWinfo64 running?


----------



## MrHoof

@Audioboxer Oh ye my current setup its 1.5°C diffrence between the dimms thought its cause of the slot they are in but that shouldnt matter much on youre watercooled setup.

@Luggage you only test with cinebench for the EDC? Cause ye I get slightly better CB23 resuluts with restirced EDC but better Aida64 cache results with free EDC at 160, it pulls 159.85 max even if i set it higher. With restriced EDC I never saw 700GB/s L3 cache results and more gflops in linpack.








'


----------



## Veii

Luggage said:


> Can I use the voltage reading from Benchmate or do I have to run normal priority and have HWinfo64 running?


HWinfo snapshot pooling should be enough
Water thermal equilibrium needs 11-12min minimum, usually longer

But i think water temp is not the main issue ~ although coldness will influence it
I think a 5800X had a prochot of 105c
Yet FIT-PRE will throttle back far before that on too high VID requests
EDC limits should do pretty much the same thing. It was the method to gain more perf on Matisse, soo it doesn't wonder me here having slightly similar results 

First stage throttle limits, should pretty much all be gone
Else you artificially cap yourself & don't see 2nd and 3rd stage throttling reason
Mostly visible on People's L3 cache readouts - latency access slowdowns 
a 4.85ghz 5800X has to have an access time of of 10.4 to 10.3ns 
no 10.7 or 10.9

But this later part also has to do with CO accuracy and balancing on it.
Soo i an not blame everyone not getting it in the 900-1000GB/s range. It's just a lot of work


----------



## MrHoof

Veii said:


> a 4.85ghz 5800X has to have an access time of of 10.4 to 10.3ns
> no 10.7 or 10.9


I alway get 10.7 at 4.85 on this asus bios the only time its get lower is going up in frequency or changing to the aida performance preset in bios.


----------



## Luggage

@Veii or use the occt benchmark for logging?


----------



## SneakySloth

Henry Owens said:


> From your picture your vddg is 0.95 not 1.05


Could be a wrong reading. I've had zentimings report strange readings on certain motherboards as well.


----------



## byDenoso

My best result so far.


----------



## LxT1N

Hi there i have ths Kit F4-3600C14-32GTZN + Dark Hero VIII Bios ist aktuell 3801 + Ryzen 5800x Stock and i would 3600CL14 Tuning to 14-14-14-14-28 but i became a error on TestMem5 with 1usmus Config if i put the data of DRam calculator what i do wrong?

I used thia data 

VDDSOC Voltage = 1.125V
DRAM = 1.45V
VDDG CCD Voltage = 1.05V
VDDG IOD Voltage = 1.05V
CLDO VDDP Voltage = 0.95V

any help how i can tuning my ram?


----------



## Taraquin

After trying for a long time to get cl15 flat stable at 4000 I gave up, it seems to require 1.55V+ which makes ram overheat. Settled at 16-15-8-15-31-46, 276 tRFC and most others rock bottom, currently using gdm since 2T gave random reboots during TM5 (between cycle 10 and 20) even though I got no errors, suspect overheat. Currently running 1.48 (1.5V reported), so lowering RCDRD, RP by 1, RC by 2 and tRFC by 12 required 0.04V. The performance increase was a bit underwhelming, 5fps in SOTTR, 1-2 sec in dram calc test.


----------



## Taraquin

LxT1N said:


> Hi there i have ths Kit F4-3600C14-32GTZN + Dark Hero VIII Bios ist aktuell 3801 + Ryzen 5800x Stock and i would 3600CL14 Tuning to 14-14-14-14-28 but i became a error on TestMem5 with 1usmus Config if i put the data of DRam calculator what i do wrong?
> 
> I used thia data
> 
> VDDSOC Voltage = 1.125V
> DRAM = 1.45V
> VDDG CCD Voltage = 1.05V
> VDDG IOD Voltage = 1.05V
> CLDO VDDP Voltage = 0.95V
> 
> any help how i can tuning my ram?
> View attachment 2526448
> View attachment 2526449
> View attachment 2526450
> View attachment 2526451
> View attachment 2526452
> View attachment 2526453
> View attachment 2526454


What error? Code? Try 900 vddp and 900 ccd, maybe cmddrvstr 20. You might need a bit more voltage to run 14 flat without gdm. Maybe 3800 cl15 and 2T might be a better choice? Dram calc often doesnt work well with ryzen 5000. 3600 don't need that high soc, 1.1v should be fine, 1.0v iod probably also works fine. For 3800 your soc/iod might be required.


----------



## Audioboxer

So on my basically silent fan profile, where some fans aren't even running, water temps get to 31 degrees and RAM temps seem to stabilise around 36 degrees. I'm happy with this. I've never had silence running TM5 

On a related note I've found out Barrow do a 2 DIMM waterblock as well Barrow RAM Water Cooling Block Kit Seems to be made almost identical to the Bykski but this one has fins. Might result in better cooling, but will likely also be more restrictive. The Bykski isn't restrictive at all, so a worthwhile option for those concerned about the numbers of rads/blocks they have with 1 pump.

But if every last degree is your aim the Barrow might be worth testing. I'm now running 4 rads, 1 GPU block, 1 CPU block and 1 memory block on 1 D5 pump. Maybe in the future I'll test the Barrow but I'm happy as is for the moment.


----------



## Veii

LxT1N said:


> but i became an error on TestMem5 with 1usmus Config, if i put the data of Dram Calculator. what do i do wrong?


DRAM Calculator is only for Matisse 3xxx series so far
And only was half-way similar till AGESA 1.1.0.0 patch B or lower

You run GDM mode, that has to be disabled with odd value timings

CAD_BUS has to be 40-20-30-24 (should work for you)
Or 24-20-24-24 at worst.
Start with 40 , and try to run Command Rate 2T

You also forgot to say "what error"
Take a look at the TM5 Error Description ~ visible as Sheet over here








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com


----------



## evilhf

I achieved this feat 
🙌


----------



## Audioboxer

evilhf said:


> View attachment 2526476
> 
> I achieved this feat
> 🙌


I'd like to start messing with BCLK, seeing as I have a B550 mobo, just a bit worried about my NVME drive.


----------



## Frosted racquet

Veii said:


> VDIMM (1.38) and tRDWR too low - give it +2
> Also GDM is an issue, run 40-20-30-24 (CAD_BUS) and run 2T instead of GDM





Frosted racquet said:


> Thanks again for the input. It seems that fixing VDDG and VDIMM voltages is sufficient to pass a couple hours of 1usmus and extreme anta777 configs. Also thanks to @SneakySloth for suggesting increasing VDIMM: I tried that before but it seems VDDG was also a problem.


Spoke too soon, after a bit more testing, not even the tRDWR, CAD_BUS and 2T modifications help


----------



## Audioboxer

Temps on the 25th cycle










Cycle complete. Wanted to test 1.5v VDIMM, wasn't sure why I was running 1.51v or what I was testing, but I knew 1.5v was OK previously.

For watercooling RAM I have noticed something which makes sense when you see it in action. Previously TM5 would cause my highest ram temps, even with a 120mm fan at 100% pointing at the RAM I could hit 40~41 degrees at 1.5v. Now TM5 is my ram at its coolest outside of idle/desktop use. Why? It's all about the water temps now.

So when I boot up a demanding game and have an overclocked 5950x/2080Ti dumping in heat and water temps reach 33~35 degrees that means RAM is around 35~38 degrees. Makes sense when you think about it, RAM goes from being cooled independently to part of a loop, so something like TM5 has no GPU running and light~medium CPU loads so water temp is like 31~32 degrees. Boot up a demanding game and water temp is going up a few degrees.

I'm running 4 rads, 3x360 and 1x120 and 17 fans (lol). Although not all fans are running during TM5. 3 of my rads are push/pull. If you have a loop that runs on higher water temps, maybe low 40s like I see some people hit  just make sure your RAM isn't best air-cooled for temps. I mean, if you're hitting RAM temps of like 50 degrees+, even water temps in the lows 40s should net you a small improvement. It's just with heavy RAM overclocking tRFC is very temp sensitive and a few degrees can make it unstable.

With very low tRFC I noticed 42 degrees can even be a tipping point.


----------



## LxT1N

Veii said:


> DRAM Calculator is only for Matisse 3xxx series so far
> And only was half-way similar till AGESA 1.1.0.0 patch B or lower
> 
> You run GDM mode, that has to be disabled with odd value timings
> 
> CAD_BUS has to be 40-20-30-24 (should work for you)
> Or 24-20-24-24 at worst.
> Start with 40 , and try to run Command Rate 2T
> 
> You also forgot to say "what error"
> Take a look at the TM5 Error Description ~ visible as Sheet over here
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com












this error i got in a few sec i have only put 14-14-14-14-28-42 the rest of auto only dram voltage on 1.45


----------



## Audioboxer

Could it be stable at 1.47v?! 

Place your bets now I guess! Even I'm a bit surprised. I was thinking 1.5v or nearer 1.5v would be needed for that tRFC and 3800 tCL/tRCDRD 14.


----------



## Audioboxer

Can't quite say I was expecting that, but there we go. I guess I was putting more voltage into this set from the get go than necessary 🤷

Guess I'll give 1.45v a quick shot for the hell of it 

*Edit* - 1.45v BSOD going into Windows. 1.46v is running a TM5 just now.
*Edit2* - 1.46v lasted about 10 minutes in TM5 and computer rebooted.

Seems 1.47v is the literal bottom for these timings, which I think is still great considering tRFC is 240. Will run a y-cruncher now.


----------



## Luggage

Veii said:


> HWinfo snapshot pooling should be enough
> Water thermal equilibrium needs 11-12min minimum, usually longer
> 
> But i think water temp is not the main issue ~ although coldness will influence it
> I think a 5800X had a prochot of 105c
> Yet FIT-PRE will throttle back far before that on too high VID requests
> EDC limits should do pretty much the same thing. It was the method to gain more perf on Matisse, soo it doesn't wonder me here having slightly similar results
> 
> First stage throttle limits, should pretty much all be gone
> Else you artificially cap yourself & don't see 2nd and 3rd stage throttling reason
> Mostly visible on People's L3 cache readouts - latency access slowdowns
> a 4.85ghz 5800X has to have an access time of of 10.4 to 10.3ns
> no 10.7 or 10.9
> 
> But this later part also has to do with CO accuracy and balancing on it.
> Soo i an not blame everyone not getting it in the 900-1000GB/s range. It's just a lot of work


Looking back at my screenshots with vermeer monitor and CPU-z stressing FIT-PRE stays at 1.5 all the time.
PPT, CCA and PRE-PID are the active limiters unless temp goes over 62C (as long as EDC is high enough, ie 166A+)
All my old Aida tests are **** though since I had Aqua computer service running and it added about 3ns to latency.
Pushing really high EDC raises L3 from low 700 to high 700, latency is now low 10 though.



http://imgur.com/a/tD7HmIm


----------



## MrHoof

@Luggage How is your experience with 1T? With setup timings or whithout.
@Audioboxer "tWTRS 2 required me to increase my VDIMM from 1.51v but I got it to boot " thats why it was 1.51v I guess.


----------



## gusocnet

So I have some Kingston HyperX kit that is Samsung C-die according to Thaiphoon Burner and I've been trying to oc it for a good while. Bear in mind I haven't really gotten down to all of the secondary and tertiary timings as I'm now trying to get it stable with lower tRFC.

With these timings (also VDDG CCD is 1050 mV but it doesn't show there somehow) I'd like to assume that I'm 100% stable - I've ran 160 cycles of the 1usmus profile in TM5 and got no errors whatsoever). But you can see that tRFC here is at 350ns, which I'd like to lower so I could move on to other timings.









Moving on, with these timings (you can see that I've lowered VDDP and I also lowered VDDG CCD to 975 mV as I was getting error #6 pretty early on with tests) I'm almost stable. I ran TM5 over night (1usmus profile, again) and in 90 cycles I got a single error #11. This could mean that RAM is overheating but I got a 90mm fan blowing on the sticks so I don't think that's an option, another possibility would be tFAW being "awkward value" or tRAS needing +1 but I assume that's not the case given the above timings and no errors.
This would leave a few other possibilities: vDIMM needs -1 or +1 stepping (tried both cases, 1.33V ****s out errors pretty much instantly and 1.35V starts erroring out after a few minutes and my monitor starts flickering a bit, so I assume 1.34V would be the sweet spot), could also be CAD_BUS not being optimal but I've tried increasing AddrCmdDrvStr to 24/30/40 Ohms and it errors out REALLY quick, also tried bumping CsOdtDrvStr but it didn't seem to help much either, and last but not least, could mean that tRFC is too low. Wouldn't it throw out errors more often during these 90 cycles if tRFC was indeed to low?
I'd like to add that I've tried playing with the setup timings as well but it also didn't seem to help all that much, it just made my ram slower apparently. I also played a bit more with SOC/VDDP/VDDG but lowering any of them made the tests throw out some more IMC voltage errors.










With that whole novel said and done, I decided to come here and seek some help to see if someone could give me some directions as to where I should go from here.


----------



## Luggage

MrHoof said:


> @Luggage How is your experience with 1T? With setup timings or whithout.
> @Audioboxer "tWTRS 2 required me to increase my VDIMM from 1.51v but I got it to boot " thats why it was 1.51v I guess.


Not good? Perhaps mostly because I haven’t got a clue about rtt, drvstr and setup - these are just lucky copys from you guys and some auto… same as I’d really like to get tRCDRD down to 14 but I really don’t know what to compensate/adjust, it’s err 3 in 5 minutes and then I give up ;P


----------



## MrHoof

Well I am not an expert either but rather lucky and have a 5800x aswell, might give those a try its the ony combination thats fully stable for me that I found so far.


Spoiler: timings















edit: trcdrd seems to depend on the dimms, if one can´t do it you gonna have bad time.


----------



## XPEHOPE3

LxT1N said:


> this error i got in a few sec i have only put 14-14-14-14-28-42 the rest of auto only dram voltage on 1.45


You can try using my 3600-14 stable profile.


----------



## Sleepycat

Audioboxer said:


> Can't quite say I was expecting that, but there we go. I guess I was putting more voltage into this set from the get go than necessary 🤷
> 
> Guess I'll give 1.45v a quick shot for the hell of it
> 
> *Edit* - 1.45v BSOD going into Windows. 1.46v is running a TM5 just now.
> *Edit2* - 1.46v lasted about 10 minutes in TM5 and computer rebooted.
> 
> Seems 1.47v is the literal bottom for these timings, which I think is still great considering tRFC is 240. Will run a y-cruncher now.


Nice! How does it impact your Aida64 scores? I had a latency increase when I used AddrCmdSetup 56 with 1T GDM off.


----------



## LxT1N

what i can changed here? to get low latency??


----------



## Sleepycat

LxT1N said:


> View attachment 2526572
> View attachment 2526573
> 
> 
> what i can changed here? to get low latency??


Does these memory settings pass TM5?


----------



## Skull_Angel

LxT1N said:


> View attachment 2526572
> View attachment 2526573
> 
> 
> what i can changed here? to get low latency??


It's possible GDM is hiding issues considering latency, some timings seem borderline and tWR looks too low (still learning, could be wrong). 

If it shows stable on 2t GDM-off, you could try to tighten tRAS [along with tCR]. You could even go for 1t stable, but may take a lot of work.


----------



## Veii

LxT1N said:


> View attachment 2526526
> 
> 
> this error i got in a few sec i have only put 14-14-14-14-28-42 the rest of auto only dram voltage on 1.45


This means you lack voltage ~ if the error is at the start
it's either bad powering or lack of +20mV memory voltage


LxT1N said:


> what i can changed here? to get low latency??


Is this even stable
I remember this was one your first messages - but no stability test got included
It looks me rather like Package throttle & auto correction

Can you first grab y-cruncher and run it as 1 enter 7 enter 0 enter
for 4 loops = 72min - to confirm CPU & IMC stability first ?
Honestly also TM5, but people asked you about it - and i didn't see any response


----------



## umea

Audioboxer said:


> Can't quite say I was expecting that, but there we go. I guess I was putting more voltage into this set from the get go than necessary 🤷
> 
> Guess I'll give 1.45v a quick shot for the hell of it
> 
> *Edit* - 1.45v BSOD going into Windows. 1.46v is running a TM5 just now.
> *Edit2* - 1.46v lasted about 10 minutes in TM5 and computer rebooted.
> 
> Seems 1.47v is the literal bottom for these timings, which I think is still great considering tRFC is 240. Will run a y-cruncher now.


1.47v for 3800 flat 14 is ridiculous lol. most ppl need 1.52-1.56.


----------



## LxT1N

Veii said:


> This means you lack voltage ~ if the error is at the start
> it's either bad powering or lack of +20mV memory voltage
> 
> Is this even stable
> I remember this was one your first messages - but no stability test got included
> It looks me rather like Package throttle & auto correction
> 
> Can you first grab y-cruncher and run it as 1 enter 7 enter 0 enter
> for 4 loops = 72min - to confirm CPU & IMC stability first ?
> Honestly also TM5, but people asked you about it - and i didn't see any response


i testedt it 2,5 Hours with tm5 1usmus config and was 0 errors temps was ok only 2-3 degree moren then stock are this normal? i have downloaded a 25 cycles from 1usmus config to look if the habe problem where i can get a y-crunches?



Sleepycat said:


> Does these memory settings pass TM5?


yes was no problem with 1usmus config after 2.5 hours only was 2-3 degree more on hwinfo



Skull_Angel said:


> It's possible GDM is hiding issues considering latency, some timings seem borderline and tWR looks too low (still learning, could be wrong).
> 
> If it shows stable on 2t GDM-off, you could try to tighten tRAS [along with tCR]. You could even go for 1t stable, but may take a lot of work.











tWR was before 12 and was ok thats because i changed it to 10 i dont now its was right

i made right know a 25cycles test with 1usmus config if there are finished i can tested it with 2t + gdm off are this for more stable? what abour the procodt?










this are the test right now need to waiting get finished.
with stock ram 14-15-15-15-35 1.45V i get 54-57 degree bei full work i think are the problem from the case?
i have the lian li o11 dynamic mini


----------



## Taraquin

Hmm, trying to stabilize 1t at 4000cl16 flat. With gdm it runs fine at 1.45V, when I set to 1.52V I get pcb/volt/overheat error after 4-5 rounds in TM5. With 1.5V I get various errors, typically possibly wrong rrds/rdwr. Is there any way to lower voltage reqs for 1T by procodt, resistances etc? Currently running 28, 24-20-24-24 atm. Problems pasting zentimings screenshot, can do later.


----------



## Audioboxer

Sleepycat said:


> Nice! How does it impact your Aida64 scores? I had a latency increase when I used AddrCmdSetup 56 with 1T GDM off.


My latency is pretty much bottomed out at 53.9~54.2ns now. Seems to be the floor with a 5950x at 3800/1900. If I can figure out how to disable 1 CCD I guess I could test if I've managed to get into 51.x range.



umea said:


> 1.47v for 3800 flat 14 is ridiculous lol. most ppl need 1.52-1.56.


Yeah it's got me nervous. 1.45v BSOD into windows, 1.46v made it about 10 minutes into TM5 and then a reboot. Think I'll run 1.48v daily just in case lol. Or maybe go for a 50 cycle TM5 at 1.47v. y-cruncher did the usual 4 cycles OK.



Taraquin said:


> Hmm, trying to stabilize 1t at 4000cl16 flat. With gdm it runs fine at 1.45V, when I set to 1.52V I get pcb/volt/overheat error after 4-5 rounds in TM5. With 1.5V I get various errors, typically possibly wrong rrds/rdwr. Is there any way to lower voltage reqs for 1T by procodt, resistances etc? Currently running 28, 24-20-24-24 atm. Problems pasting zentimings screenshot, can do later.


GDM probably trying to autocorrect things. Though I have noticed myself once I go to 1.52v~1.55v+, even with GDM disabled, it seems to require tweaking of resistances/procodt and so on to try and avoid PCB crashes. Part of the reason I've struggled having a go at tCL13, it requires more voltage and I'm not 100% sure if my PCB crashes are due to silicon struggling with tCL13 at 3800 or it's finding out how to balance a higher voltage with resistances.

I had to thread the eye of a needle to figure out how to get my tPHYRDL to train at 28/28 with tCL14 3800 1T. Seemed to benefit from AddrCmdDrvStr going to 24 over 20. Also RttNom at 6 seems to help, instead of 7. 26/26 is still super easy at tCL13/15, but I've given up thinking about why that is, 28/28 at tCL14 3800 1T is a success over 28/30.

In other words resistances can be very important once GDM is disabled.


----------



## deadfelllow

deadfelllow said:


> View attachment 2526344
> 
> 
> 
> 
> Any ideas? I turned off the GDM recently.
> Maybe i can lower tRFC a little like 260-ish or even 270
> I can try to lower trp + tras = trc could be less.
> maybe cl 15 trcdrd 15 ??? also tCWL?
> 
> for those who cannot see my voltages
> soc = 1.15
> IOD = 1.07
> VDDG = 1
> VDDP = 0.9
> DIMM = 1.55 vTT = 0.775
> 
> Thanks.


Anyone


----------



## LxT1N

Sleepycat said:


> Does these memory settings pass TM5?


yes was no problem with 1usmus config after 2.5 hours only was 2-3 degree more on hwinfo 



Skull_Angel said:


> It's possible GDM is hiding issues considering latency, some timings seem borderline and tWR looks too low (still learning, could be wrong).
> 
> If it shows stable on 2t GDM-off, you could try to tighten tRAS [along with tCR]. You could even go for 1t stable, but may take a lot of work.


tWR was before 12 and was ok thats because i changed it to 10 i dont now its was right

i made right know a 25cycles test with 1usmus config if there are finished i can tested it with 2t + gdm off are this for more stable? what abour the procodt? 



Veii said:


> This means you lack voltage ~ if the error is at the start
> it's either bad powering or lack of +20mV memory voltage
> 
> Is this even stable
> I remember this was one your first messages - but no stability test got included
> It looks me rather like Package throttle & auto correction
> 
> Can you first grab y-cruncher and run it as 1 enter 7 enter 0 enter
> for 4 loops = 72min - to confirm CPU & IMC stability first ?
> Honestly also TM5, but people asked you about it - and i didn't see any response


i testedt it 2,5 Hours with tm5 1usmus config and was 0 errors temps was ok only 2-3 degree moren then stock are this normal? i have downloaded a 25 cycles from 1usmus config to look if the habe problem where i can get a y-crunches?

this are the test right now need to waiting get finished.
with stock ram 14-15-15-15-35 1.45V i get 54-57 degree bei full work i think are the problem from the case?
i have the lian li o11 dynamic mini 









now the test are finished after 3 hours with 0 error are this then safe?


----------



## Audioboxer

@Veii Is there a relationship between RttNom and VDIMM? Previously I was convinced along with AddrCmdDrvStr RttNom was helping me sustain 28/28. Keeping it at 6 seemed to help. I've just cold booted (power supply off) 4 times now and RttNom 7 is keeping 28/28. Only change from days ago is VDIMM dropping to 1.47~1.48v.

Testing RttNom 7 now. Very cold this morning so those ambients drop the water temp and DIMM temps a bit further 👀


----------



## umea

Well you've convinced me to buy the same kit as you. Also if it runs for 3 hours with no errors you should be stable, if you want to really test it try anta's extreme config. But you should be fine.
Also, these came. Bought 2 sets because I figured I'll be buying another kit of ram soonish, and since it ships from the EU I might as well as shipping was already going to be expensive. Going to retest to see if it's actually my kit that's poorly binned stopping me from getting 14 flat or if it's my CPU.









I don't want to sound like a sore loser, but I wonder what the chances of the 5900x actually being a worse bin than the 5950x as maybe they're just failed 5950x chips? Dunno, just thinking of GPUs and stuff like that and maybe it's the case with CPUs. Either way, if it is my CPU then I'll probably buy another kit to mess around with until the next Zen3D comes out, and this time I might just grab a couple 5950xs and keep the best binned one.


----------



## LxT1N

VDDSOC Voltage = 1.1V
DRAM = 1.45V
VDDG CCD Voltage = 0.95v
VDDG IOD Voltage = 1.05V
CLDO VDDP Voltage = 0.90V

i have close all app and now the latency are 59 i try one more test with anta777 config but how i can get more safe my ram kit


----------



## umea

LxT1N said:


> View attachment 2526615
> 
> View attachment 2526616
> 
> 
> VDDSOC Voltage = 1.1V
> DRAM = 1.45V
> VDDG CCD Voltage = 0.95v
> VDDG IOD Voltage = 1.05V
> CLDO VDDP Voltage = 0.90V
> 
> i have close all app and now the latency are 59 i try one more test with anta777 config but how i can get more safe my ram kit


Let's start with this:
1. Disable GDM (gear down mode) and set it to 2T.
2. Run 1usmus and not anta's config for troubleshooting as we have a key for the errors.
3. Tighten to 14-14-14-14, set tRAS to 28, tRC to 42. run TM5.
4. After this, start tightening secondaries/tertiaries, this guide gives a general idea: MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper

Also tRFC can be calculated here: Google Sheets - create and edit spreadsheets online, for free.


----------



## Veii

Audioboxer said:


> @Veii Is there a relationship between RttNom and VDIMM? Previously I was convinced along with AddrCmdDrvStr RttNom was helping me sustain 28/28. Keeping it at 6 seemed to help. I've just cold booted (power supply off) 4 times now and RttNom 7 is keeping 28/28. Only change from days ago is VDIMM dropping to 1.47~1.48v.
> 
> Testing RttNom 7 now. Very cold this morning so those ambients drop the water temp and DIMM temps a bit further 👀


Yes
More VDIMM needs more RTT_NOM

You can lower it, till #13 or #14 appears
I could go down to 437 or 370 even
537 or 637 was the place it felt comfortable
But tbh 736 worked too~
Could help some timings, i feel it does a bit on tRRD & tFAW
But not entirely confident about it. As always, PCB dependent 

IOLs while having a connection to powering (also)
They have no direct connection to RTT_NOM
Same goes for tCKE



umea said:


> I don't want to sound like a sore loser, but I wonder what the chances of the 5900x actually being a worse bin than the 5950x as maybe they're just failed 5950x chips? Dunno, just thinking of GPUs and stuff like that and maybe it's the case with CPUs. Either way, if it is my CPU then I'll probably buy another kit to mess around with until the next Zen3D comes out, and this time I might just grab a couple 5950xs and keep the best binned one.


You are not thinking wrongly
It is too expensive to maintain several batches and remove fused dies
It's disabled on PSP-FW level ~ except when an oopsy happens
Dual CCD vs single CCD batches ~ have changed recently. Manufacture Labor cost has shifted

But all dual CCDs are 5950X
Same for EPYC
Tho a "CCX" has single L1+L2+Core packages placed ontop of the CCD substrate

I wish you good luck in getting the first Zen3D batch 🙏


----------



## LxT1N

umea said:


> Let's start with this:
> 1. Disable GDM (gear down mode) and set it to 2T.
> 2. Run 1usmus and not anta's config for troubleshooting as we have a key for the errors.
> 3. Tighten to 14-14-14-14, set tRAS to 28, tRC to 42. run TM5.
> 4. After this, start tightening secondaries/tertiaries, this guide gives a general idea: MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper
> 
> Also tRFC can be calculated here: Google Sheets - create and edit spreadsheets online, for free.


thx the problem if i testet it with 14-14-14-14-28-42 i got a error in 15 seconds


----------



## Taraquin

LxT1N said:


> thx the problem if i testet it with 14-14-14-14-28-42 i got a error in 15 seconds


Need a bit more voltage. Try 1.47V and see if it works.


----------



## umea

LxT1N said:


> thx the problem if i testet it with 14-14-14-14-28-42 i got a error in 15 seconds


Look at the bottom of the tRFC calculator sheet for the TM5 Error description, it'll tell you what the errors mean and you can go from there to troubleshoot.


Veii said:


> You are not thinking wrongly
> It is too expensive to maintain several batches and remove fused dies
> It's disabled on PSP-FW level ~ except when an oopsy happens
> Dual CCD vs single CCD batches ~ have changed recently. Manufacture Labor cost has shifted
> 
> But all dual CCDs are 5950X
> Same for EPYC
> Tho a "CCX" has single L1+L2+Core packages placed ontop of the CCD substrate
> 
> I wish you good luck in getting the first Zen3D batch 🙏


Thanks Veii, that's basically what I figured, it seems like the 5900x is just overall the worst for ram as they're basically failed 5950xs and have too many cores to really run things like a 5800x can (5800x is considerably easier to get 1T/ 3800 flat 14 running it seems). I'll probably go for a 5950x with zen3d and just sell this off.


----------



## Audioboxer

Got further than I have before with tCL13 👀 Gives me hope with the right voltage and resistances I _should_ be able to obtain it.

The return of tPHYRDL 26/26! The real victory


----------



## LxT1N

this are the result from anta777 config

are better then 3800CL16 or 3800cl14? and how many dram voltage i need for it? i will try to get one one then because i try to get 14-14-14-14-28-42 with 1.49v and all time the same error  for 3600cl14 flat


----------



## Audioboxer

Audioboxer said:


> Got further than I have before with tCL13 👀 Gives me hope with the right voltage and resistances I _should_ be able to obtain it.
> 
> The return of tPHYRDL 26/26! The real victory












Boom, I managed it. Two changes, VDIMM up to 1.55v and CkeDrvStr to 24. No idea which one helped me over the line, I guess probably VDIMM. Can always try dropping CkeDrvStr back to 20 now. @Veii what can CkeDrvStr even help with? lol. I just put it up to test it.

Might try for RttNom 6 but I'm probably spot on 5 might be needed once I get to 1.55v. Test finishes a bit quicker as well, my quickest up till now was like 2 hours 39 minutes. Quite a big VDIMM jump from 1.47~1.48v to 1.55v for tCL14 to tCL13, but I guess this is probably in line with expectations.

*edit* - Ooft, L3 cache on Windows 11 seems to be completely broken. I heard it was. So I guess if you care about memory benching stay away from Windows 11 for now. Here is a DRAM Calculator bench anyway, though I have no idea if there are bigger Windows 11 issues with memory performance










Guess we'll have to wait for some Windows 11 updates to see if MS fix their mess.

Next step, if I'm going to consider running 1.55v daily, see if tRFC will edge down some more 👀










Temps at 1.55v peaked at 35 degrees over 2 hours 36 mins, but ambient is pretty cool just now so water temps are down.


----------



## VPII

Ezalor said:


> Skull_Angel's reply has the answer about the ohms. Have you tried the other things, and no difference? Procodt, trcdrd, trfc?


Hi there, having tried T2 command rate the OCCT test ran without and issue untill it through a WHEA error, only one, nothing more while the test was still running.

Vdimm in bios is set to 1.43v.


----------



## mongoled

Audioboxer said:


> Boom, I managed it. Two changes, VDIMM up to 1.55v and CkeDrvStr to 24. No idea which one helped me over the line, I guess probably VDIMM. Can always try dropping CkeDrvStr back to 20 now. @Veii what can CkeDrvStr even help with? lol. I just put it up to test it.
> 
> Might try for RttNom 6 but I'm probably spot on 5 might be needed once I get to 1.55v. Test finishes a bit quicker as well, my quickest up till now was like 2 hours 39 minutes. Quite a big VDIMM jump from 1.47~1.48v to 1.55v for tCL14 to tCL13, but I guess this is probably in line with expectations.
> 
> *edit* - Ooft, L3 cache on Windows 11 seems to be completely broken. I heard it was. So I guess if you care about memory benching stay away from Windows 11 for now. Here is a DRAM Calculator bench anyway, though I have no idea if there are bigger Windows 11 issues with memory performance
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Guess we'll have to wait for some Windows 11 updates to see if MS fix their mess.
> 
> Next step, if I'm going to consider running 1.55v daily, see if tRFC will edge down some more 👀
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Temps at 1.55v peaked at 35 degrees over 2 hours 36 mins, but ambient is pretty cool just now so water temps are down.


Nice job, money comes in handy



Have you compared straight up performance between CL14/13 ??

Compare the times using DRAM Membench ...

On another note, I saw no latency improvement when using tWRTS set to 3, so why bother ??


----------



## LxT1N

VDDSOC Voltage = 1.1V
DRAM = 1.38V
VDDG CCD Voltage = 0.95v
VDDG IOD Voltage = 1.05V
CLDO VDDP Voltage = 0.90V

any help to get better prefomance on the 3800cl16? the temp are very similiar then the 3600cl14


----------



## Audioboxer

mongoled said:


> Nice job, money comes in handy
> 
> 
> 
> Have you compared straight up performance between CL14/13 ??
> 
> Compare the times using DRAM Membench ...
> 
> On another note, I saw no latency improvement when using tWRTS set to 3, so why bother ??


First bench I've tried on Windows 11 which as I said seems to have an L3 cache bug.

I ran a DRAM membench on Windows 10 with tCL14 but some of the secondaries were different. IIRC it was around 97/98. Will try to find it. I'm running another TM5 just now with a lower tRFC.

Not sure, I've just had it at 3 for ages.










Here was a tCL14 I did, though this might have been before I fixed my tPHYRDL issue on tCL14. Will have to retest.


----------



## Frosted racquet

Frosted racquet said:


> Spoke too soon, after a bit more testing, not even the tRDWR, CAD_BUS and 2T modifications help


Any help please?  The error codes are all over the place, so I don't know on what to focus and change in BIOS.


----------



## mongoled

Frosted racquet said:


> Any help please?  The error codes are all over the place, so I don't know on what to focus and change in BIOS.


Increase vSOC two steps and test again to see if anything has changed


----------



## umea

`


LxT1N said:


> View attachment 2526649
> View attachment 2526650
> 
> VDDSOC Voltage = 1.1V
> DRAM = 1.38V
> VDDG CCD Voltage = 0.95v
> VDDG IOD Voltage = 1.05V
> CLDO VDDP Voltage = 0.90V
> 
> any help to get better prefomance on the 3800cl16? the temp are very similiar then the 3600cl14


Sorry, try this tRFC mini


----------



## mongoled

LxT1N said:


> View attachment 2526649
> View attachment 2526650
> 
> VDDSOC Voltage = 1.1V
> DRAM = 1.38V
> VDDG CCD Voltage = 0.95v
> VDDG IOD Voltage = 1.05V
> CLDO VDDP Voltage = 0.90V
> 
> any help to get better prefomance on the 3800cl16? the temp are very similiar then the 3600cl14


I believe its been pointed out to you to disable GDM and set Cmd2T to 2T.

People will be more willing to help you if you do these steps.


----------



## umea

It's pretty funny how on reddit you'll have people telling you to keep GDM on because it's better and yet...


----------



## LxT1N

mongoled said:


> I believe its been pointed out to you to disable GDM and set Cmd2T to 2T.
> 
> People will be more willing to help you if you do these steps.


i will do it only gmd and 2t? what about procodt?


----------



## Luggage

umea said:


> It's pretty funny how on reddit you'll have people telling you to keep GDM on because it's better and yet...


It’s easier to get stable with nice numbers. Just as hard to get performance?


----------



## Audioboxer

umea said:


> It's pretty funny how on reddit you'll have people telling you to keep GDM on because it's better and yet...


lol, yeah, I see that quite often. GDM makes it very difficult to troubleshoot errors and it masks instability by seemingly autocorrecting. I'm not going to claim I'm an expert on memory overclocking but I know enough now to recognise a poor GDM enabled profile that is shown to be "stable". Primaries and secondaries that do not match the high latency and read/write throttling going on.

But it passes TM5! 🙈


----------



## mongoled

LxT1N said:


> i will do it only gmd and 2t? what about procodt?


Put it on AUTO


----------



## paih85

LxT1N said:


> thx the problem if i testet it with 14-14-14-14-28-42 i got a error in 15 seconds


try this. aida64 bench ~54ns

voltage: 1.45v


----------



## Audioboxer

With VDIMM going up thought I'd try lowering my tRFC










228 club!

y-cruncher time though, as 240 to 228 is quite a drop at once.


----------



## Danny.ns

Bored so some findings regarding the "FCLK 1900 hole"..

If I select the FCLK 1866 multiplier and up the BLCK to 101.625MHz, i get a FCLK of 1896MHz. I can play games, and do anything - not a single WHEA. But of course, upping the BCLK means CPU boost is disabled so locked at 3.7ghz.

For a moment, i thought i had an Eureka!-moment. I figured I would use spread spectrum to get BCLK of 99.8 which with FCLK 1900 multiplier should give a FCLK of.. 1896MHz (but keep CPU boosting normaly)! Alas, no POSTing allowed here.

If I select FCLK 1900 multiplier and lower the BLCK to 99Mhz, i should get a FCLK of 1881MHz - but this does not POST either.

Sigh.....


----------



## domdtxdissar

Audioboxer said:


> Boom, I managed it. Two changes, VDIMM up to 1.55v and CkeDrvStr to 24. No idea which one helped me over the line, I guess probably VDIMM. Can always try dropping CkeDrvStr back to 20 now. @Veii what can CkeDrvStr even help with? lol. I just put it up to test it.
> 
> Might try for RttNom 6 but I'm probably spot on 5 might be needed once I get to 1.55v. Test finishes a bit quicker as well, my quickest up till now was like 2 hours 39 minutes. Quite a big VDIMM jump from 1.47~1.48v to 1.55v for tCL14 to tCL13, but I guess this is probably in line with expectations.
> 
> *edit* - Ooft, L3 cache on Windows 11 seems to be completely broken. I heard it was. So I guess if you care about memory benching stay away from Windows 11 for now. Here is a DRAM Calculator bench anyway, though I have no idea if there are bigger Windows 11 issues with memory performance
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Guess we'll have to wait for some Windows 11 updates to see if MS fix their mess.
> 
> Next step, if I'm going to consider running 1.55v daily, see if tRFC will edge down some more 👀
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Temps at 1.55v peaked at 35 degrees over 2 hours 36 mins, but ambient is pretty cool just now so water temps are down.


Almost can't believe it, but it seems i'm also running CL13 now o_0
tPHYRDL @ 26/26 
1.545 vdimm

Had to drop tRDWR from 10 to 12 and tWRRD from 1 to 3, to make it happen..
Only on cycle 6 atm, but have never made it this far at cl13 before 









I were planning to wait for my new motherboard to install the ram cooler, but don't think i want to wait for that now..


----------



## LxT1N

mongoled said:


> I believe its been pointed out to you to disable GDM and set Cmd2T to 2T.
> 
> People will be more willing to help you if you do these steps.


















i got the GDM Disabled and Cmd2T on 2T the frist test was okay but the latency are not good around 58 are this normal with all apps close? or what i do wrong?


----------



## Audioboxer

domdtxdissar said:


> Almost can't believe it, but it seems i'm also running CL13 now o_0
> tPHYRDL @ 26/26
> 1.545 vdimm
> 
> Had to drop tRDWR from 10 to 12 and tWRRD from 1 to 3, to make it happen..
> Only on cycle 6 atm, but have never made it this far at cl13 before
> View attachment 2526676
> 
> 
> I were planning to wait for my new motherboard to install the ram cooler, but don't think i want to wait for that now..












I actually just tested 12/10 because Veii has been telling me off for tRDWR 12 lol. Seems to be OK, though test has taken a bit longer. Will need to do more testing!


----------



## Dodgexander

If anyone has any more help I'd really appreciate it. I feel like by the time this has finished my hair will turn grey!
I have been fighting with these for a couple of weeks and finally have a stable baseline at 1900mhz FCLK.
I discovered 1T was just a complete pain to get stable without GDM on, so went back to square one; this time with 1T and GDM OFF. Thank you to everyone in the thread who advises to run with GDM OFF (either with 1 or 2T) since everywhere else online says just to keep it on.









My issue? I seem to need *a lot of voltage* compared to everyone else to get 1900 stable. I read online stories of degradation, but is my voltage safe for 24/7 use?

From my position, what would experts do next?
Lower SoC/CCD/IOD voltages until unstable again, or just leave voltage and lower memory timings first?

On a side-note. I find it very hard to believe that some of the timings on the google sheet are fully stable. Many results people only test 1-2h of TM5...sometimes even without the Anta extreme profile and not other tests. In my experience this is not enough to be stable, and y-cruncher is a much better test to check for WHEA errors. I had wasted so much time only testing TM5 to see if stable, only to find later some memory timings caused my FCLK to become unstable in y-cruncher.


Danny.ns said:


> Bored so some findings regarding the "FCLK 1900 hole"..
> 
> If I select the FCLK 1866 multiplier and up the BLCK to 101.625MHz, i get a FCLK of 1896MHz. I can play games, and do anything - not a single WHEA. But of course, upping the BCLK means CPU boost is disabled so locked at 3.7ghz.
> 
> For a moment, i thought i had an Eureka!-moment. I figured I would use spread spectrum to get BCLK of 99.8 which with FCLK 1900 multiplier should give a FCLK of.. 1896MHz (but keep CPU boosting normaly)! Alas, no POSTing allowed here.
> 
> If I select FCLK 1900 multiplier and lower the BLCK to 99Mhz, i should get a FCLK of 1881MHz - but this does not POST either.
> 
> Sigh.....


I'm not sure if it helps you or not but in my google searches trying to find why I was getting just a single WHEA after hours of testing I found someone mention a bug that earlier Gigabyte firmware had on their Aorus range of boards. Not sure if it could also be an issue for Asus or others too, but it relates to manually setting BLCK. If you set BLCK manually in BIOS the option to enable or disable spread spectrum disappears...but in some cases it was still remaining enabled even when the option is no longer selectable.

The way around it is to set BLCK to Auto and then disable spread spectrum manually, or as some people have found; keep spread spectrum enabled as sometimes it can also help stability.


----------



## Dodgexander

Veii said:


> Oke so this is pretty clear for me at this point
> But i want to repost it here too, so it get's more attention
> 
> SMU 56.34 is BAD, very very bad
> Idk yet what of it is that horrible but it has a 1900FCLK limit in there
> Meaning - i can not even boot my 1900FCLK anymore. While 1867 boots & is stable without issues
> 
> I've seen and read the continues marketing attempts to bring people updating to 1.1.0.0 Patch C, updating to 1.1.8.0 and higher
> But i can not understand as enthousiast ~ why anyone would fall for this and give away performance
> AMD has done this once already , well several times for Matisse ~ slowly but surely cutting away features and maximum Fabric Clock
> 
> Now doing it again, is just plain wrong.
> These CPUs, Vermeer is capable of holding 2100FCLK
> Yes it's very hard to set up, and i have to admit to still struggle in getting it long stable
> ~ but 2067Mhz is like a childs toy , easy to stabilize under low voltage
> 
> There is absolutely nothing in newer Patches that justifies to trow away performance
> 
> no IPC gains
> no higher boostclock
> nothing done to cores in helping them to boost higher (core quality detection is variable up to used voltage and proc)
> no higher single core boost
> no higher render boost, for example SuperPi
> Nothing
> 
> Maybe the numbers are different & how "effective" fabric clock is now.
> Soo maybe these are IPC improvements
> But they remain a theoretical thing, when we have a hardlock on it
> It makes no sense for me to not only trow away memory bandwidth and low latency - but also be limited in even trying to stabilize "unstable fabric clock"
> At least on SMU 56.30 pre-patch C , i can try and work on 2100 FCLK
> On the newer "standartized user enforced" one ~ i can not ! We users got pretty much locked
> 
> And all that, just so BAR mode "maaybe" functions better and the chance of PCIe crashes are lower
> Although again, normal AGESA 1.1.0.0 SMU 56.30 does indeed haveBAR support & also Curve Optimizer support
> View attachment 2466989





Veii said:


> It's very interesting that you can post 1900
> Read my posts above , there is a lock beyond 1900
> for me idk why - guess i'm unlucky
> 
> Test stability with y-cruncher ,
> press number 1 to "component test", then 6 "to select all tests" and 0 " to start "
> it will take 18 min each loop - you nee to pass 4 cycles
> Beyond 3
> If you can pass that, then your problem is different
> 
> Your issue is your VDDP is higher than your VDDG CCD
> VDDP + x = VDDG +x = VSOC
> x always has to stay the same voltage stepping or a multiple of it
> Zen 3 likes 40mV as stepping
> you can use 2*40mV, 3*40mV and so on
> 
> As long as this scaling exists it will not have random crash-errors
> This was since Matisse the case an still exists - just this time it's 40mV not 50mV minimum scaling
> Readable here:
> OC'ing T-Force 4133 cl18 bottom part of the post
> 
> I've attache before some screenshots of stable settings
> for you
> either you push VDDP down to 950mV and increase VDDG CCD to 1000mV
> or you increase SOC to 1150 then you can push CCD to 1050
> There is no issue ifboth VDDG are identical
> but there is an issue if VDDP is too high or SOC too low
> 
> High IOD an low CCD are the advices i can give you for this generation
> Too high VDDG CCD voltage causes crashes and issues
> ~ it's important not to ignore CCD voltage this time
> 
> yes, but not only
> if you use 4 dimms try higher Clkdrvstr
> 4 dimms or dual rank can move beyond 60ohm
> Zen 3 can post beyond 2000 fabric even with 58ohm procODT
> Negative scaling wasnt found yet
> 2100 will run with 34-58ohm procODT, all off them work
> 
> SMU 56.34 is not able to go beyond 1900FCLK
> But you run too low SOC
> same post as the quote above
> voltage stepping - is important
> give SOC a bit more like 20mV
> or if you stay on auto , try to use global -50mV offset
> by default these AGESA's overvolt a bit on SOC
> And Zen3 is very SOC hungry
> 
> you can go up to 1.125v SOC without issues
> 2100 fabric will require you to run 1.2-1.25v SOC to have a chance of stability,
> if you decide to downgrade the bios one step down to AGESA 1.1.0.0 non patch C


Are these things still true today?
Should we downgrade to earlier bios version?
It's still valid that cldo_vddp + x = vddg ccd + x = vsoc ?
What about vddg iod?


----------



## umea

Audioboxer said:


> I actually just tested 12/10 because Veii has been telling me off for tRDWR 12 lol. Seems to be OK, though test has taken a bit longer. Will need to do more testing!


Now the real question is can you get 13 flat?


----------



## rossi594

Has anybody here run Patriot Viper Steels 4400 cl19 with the A2 pcb with voltages >1,5v (1,55 / 1,57) for an extended period of time? Did they crap out?


----------



## mongoled

LxT1N said:


> View attachment 2526684
> View attachment 2526685
> 
> i got the GDM Disabled and Cmd2T on 2T the frist test was okay but the latency are not good around 68 are this normal? or what i do wrong?


Am confused with your post, you say your latency is 68ns, but your screenshot says 57.4ns ???



rossi594 said:


> Has anybody here run Patriot Viper Steels 4400 cl19 with the A2 pcb with voltages >1,5v (1,55 / 1,57) for an extended period of time? Did they crap out?


I am using 1.57v, in HWInfo it is as 1.59/1.6v,

dimms are watercooled, Rtts are set to 6/3/6 (NOM/WR/PARK)

They have not "crapped" out yet


----------



## Audioboxer

umea said:


> Now the real question is can you get 13 flat?


It boots fine but errors on 6 happen within a minute which in my experience with previous b-die sets is usually the sign the silicon isn't good enough. I don't think I've seen anyone do 3800 tRCDRD 13 stable as of yet lol. Not saying it's impossible though.


----------



## mongoled

Audioboxer said:


> It boots fine but errors on 6 happen within a minute which in my experience with previous b-die sets is usually the sign the silicon isn't good enough. I don't think I've seen anyone do 3800 tRCDRD 13 stable as of yet lol. Not saying it's impossible though.


See you are fixated on the "silicon".

I believe its more to do with the PCB rather than the individual RAM chips (silicon) ...

A good way to prove this would be to remove all the modules from a "good stick" and move to the PCB of a "bad stick" and then see, but I dont have the equipment for such a job

😂 😂


----------



## umea

Audioboxer said:


> It boots fine but errors on 6 happen within a minute which in my experience with previous b-die sets is usually the sign the silicon isn't good enough. I don't think I've seen anyone do 3800 tRCDRD 13 stable as of yet lol. Not saying it's impossible though.


Well it's more likely that the IMC of the 5950x can't handle 32gb of cl13 flat. I'd bet someone could get it stable on a 5600x.

Got bored tonight so decided to mess with raising FCLK again, and for some reason 1933 worked when previously it would always restart or whea out after 5 minutes. No idea what changed but... good sign I guess? Time to try the next step.


----------



## Taraquin

Audioboxer said:


> My latency is pretty much bottomed out at 53.9~54.2ns now. Seems to be the floor with a 5950x at 3800/1900. If I can figure out how to disable 1 CCD I guess I could test if I've managed to get into 51.x range.
> 
> 
> 
> Yeah it's got me nervous. 1.45v BSOD into windows, 1.46v made it about 10 minutes into TM5 and then a reboot. Think I'll run 1.48v daily just in case lol. Or maybe go for a 50 cycle TM5 at 1.47v. y-cruncher did the usual 4 cycles OK.
> 
> 
> 
> GDM probably trying to autocorrect things. Though I have noticed myself once I go to 1.52v~1.55v+, even with GDM disabled, it seems to require tweaking of resistances/procodt and so on to try and avoid PCB crashes. Part of the reason I've struggled having a go at tCL13, it requires more voltage and I'm not 100% sure if my PCB crashes are due to silicon struggling with tCL13 at 3800 or it's finding out how to balance a higher voltage with resistances.
> 
> I had to thread the eye of a needle to figure out how to get my tPHYRDL to train at 28/28 with tCL14 3800 1T. Seemed to benefit from AddrCmdDrvStr going to 24 over 20. Also RttNom at 6 seems to help, instead of 7. 26/26 is still super easy at tCL13/15, but I've given up thinking about why that is, 28/28 at tCL14 3800 1T is a success over 28/30.
> 
> In other words resistances can be very important once GDM is disabled.


It's probably GDM doing it's 'magic', I get rare random errors if I try 2T, but I have no idea what to change with procodt, resistances etc and how to configure them according to each other :/ I'm on 2xSR so I usually go with disable/disable/5, can 6 or 7 be beneficial? I tried procodt 28, 34 and 37, no difference, same error-rate.


----------



## Audioboxer

Was able to confirm I will be OK going back up to RttNom 6. Not sure there is anything left to do with this profile? I guess I can see if RttPark can get lowered!


----------



## mongoled

tCL @13 wooooooooooo

😋😋

I did not expect that, sub 52 ns @3800/1900 tRCDRD @15.

tCL @14 gives me 52.7 ns @13 I'm getting 51.8 ns, everything else (except for tCWL) is equal.

But I need 1.62 volts in BIOS for TM5 not to crap out instantly on test 6

🥴🥴


----------



## Taraquin

Audioboxer said:


> Was able to confirm I will be OK going back up to RttNom 6. Not sure there is anything left to do with this profile? I guess I can see if RttPark can get lowered!


I envy your binning  Mine does 3800cl15 flat 2T at 1.47V, lower spews errors. Yours could probably do what mine does at 1.35V


----------



## Audioboxer

Taraquin said:


> I envy your binning  Mine does 3800cl15 flat 2T at 1.47V, lower spews errors. Yours could probably do what mine does at 1.35V


No doubt it's a good binning but I think lower temps might be helping as well! I might revisit flat 15 just to see what the voltage can go down to. Flat 14 seems to be OK at 1.47v.

1T Pure looks like the thing that isn't going to happen but I guess that has a lot to do with the IMC and a 5950x isn't great for that.


----------



## mongoled

DRAM Calc Membench hardly any difference between tCL 13 vs tCL 15


----------



## LxT1N

mongoled said:


> Am confused with your post, you say your latency is 68ns, but your screenshot says 57.4ns ???


 sorry i meant 58 what i can changed there?


----------



## Audioboxer

mongoled said:


> DRAM Calc Membench hardly any difference between tCL 13 vs tCL 15
> 
> View attachment 2526711
> 
> 
> View attachment 2526712


An improvement is an improvement 😏

Thanks for the idea of running 12/9 (tCWL/tRDWR), seems like I might even be able to chase that when running at 1.55v. TM5 running just now.

Something I have discovered is while RttPark 5 will boot fine and TM5 was OK after 15 mins I quickly noticed tPHYRDL out of sync again. Going back to 3 and it's back in sync.


----------



## mongoled

LxT1N said:


> sorry i meant 58 what i can changed there?


First you must check with TM5 25 cycles run to see if its stable.

Then after you have done this we can evaluate the next stage ...


----------



## mongoled

Audioboxer said:


> An improvement is an improvement 😏
> 
> Thanks for the idea of running 12/9 (tCWL/tRDWR), seems like I might even be able to chase that when running at 1.55v. TM5 running just now.
> 
> Something I have discovered is while RttPark 5 will boot fine and TM5 was OK after 15 mins I quickly noticed tPHYRDL out of sync again. Going back to 3 and it's back in sync.


Im hoping that when lowering tCL no other timings are going to need tweaking.

Just more vDIMM and balancing RTTs if required.

Will see with my TM5 run if this is the case.

So far first cycle passed with no errors ....

Park at 3 is OK while you are at 1.55v, but as you go higher on voltage you are going to need to increase RTTPark


----------



## LxT1N

mongoled said:


> First you must check with TM5 25 cycles run to see if its stable.
> 
> Then after you have done this we can evaluate the next stage ...












yes was stable no error i have used TM5 with 1usmus v3 config


----------



## Audioboxer

mongoled said:


> Im hoping that when lowering tCL no other timings are going to need tweaking.
> 
> Just more vDIMM and balancing RTTs if required.
> 
> Will see with my TM5 run if this is the case.
> 
> So far first cycle passed with no errors ....
> 
> Park at 3 is OK while you are at 1.55v, but as you go higher on voltage you are going to need to increase RTTPark


IIRC Veii said to me just dropping tCL is normally a voltage task, though you obviously do need to reconfigure tCWL if you were at 14.

Rtts and DrvStr as well possibly. I think going to CmdDrvStr 24 instead of 20 has helped me quite a bit. Still unsure if CkeDrvStr at 24 has done anything, I'll try reverting to 20 at some point.

I'll have a look at RttPark 4. 5 looked as if it had a chance at being stable but as I said it knocked my tPHYRDL out of sync. My favourite timing 🤣


----------



## mongoled

LxT1N said:


> View attachment 2526719
> 
> 
> yes was stable no error i have used TM5 with 1usmus v3 config


Up to what vDIMM voltage are you comfortable with ??


----------



## LxT1N

mongoled said:


> Up to what vDIMM voltage are you comfortable with ??


i used

VDDSOC Voltage = 1.1V
DRAM = 1.36V
VDDG CCD Voltage = 0.95v
VDDG IOD Voltage = 1.02V
CLDO VDDP Voltage = 0.90V


----------



## mongoled

LxT1N said:


> i used
> 
> VDDSOC Voltage = 1.1V
> DRAM = 1.36V
> VDDG CCD Voltage = 0.95v
> VDDG IOD Voltage = 1.02V
> CLDO VDDP Voltage = 0.90V


Language problem ....

I will try again,

What is the maximum vDIMM voltage you are OK with ????

As that will define what advise I can give !

And before you was using 1.45 v @ 3600 mhz and now you are at 1.36 v with 3800 mhz ???


----------



## LxT1N

mongoled said:


> Language problem ....
> 
> I will try again,
> 
> What is the maximum vDIMM voltage you are OK with ????
> 
> As that will define what advise I can give !
> 
> And before you was using 1.45 v @ 3600 mhz and now you are at 1.36 v with 3800 mhz ???


yes i have now 1.36v on 3800mhz i think this are okay but cant see any diference on the stock 1.45 3600mhz on the Temperature only on latency before i was 65 now are the on 58 thats because i ask what i do wrong


----------



## rul3s

Guys, anyone could run 5800x with 4 dimms SR at high memory speed? With two dimm I can go [email protected] but with 4 dimm I can only reach 3466 without errors.
Is this normal?
Thanks!


----------



## Audioboxer

tRDWR 9 seems to be okay, so @Veii will be happy  👀

Just need to try some benching and make sure its OK in results.










Lowest bench I've achieved!

Wished I had stayed on Windows 10 a bit longer, dunno what is going on with Windows 11 cache latency. Even though DRAM Calculator says Windows 10 above, it is Windows 11.


----------



## mongoled

LxT1N said:


> yes i have now 1.36v on 3800mhz i think this are okay but cant see any diference on the stock 1.45 3600mhz on the Temperature only on latency before i was 65 now are the on 58 thats because i ask what i do wrong


You do nothing wrong, to the contrary (apart from the GDM enabled) you are doing the right things.

On first look you seem to have a very good bin.

Set vDIMM to 1.45v, change tCL to 14 and then do a quick AIDA64, your latency should drop to some more.

I would attempt a 14-16-14-14 profile, as you know how to use the Ryzen Google "Calculator" fire in those primaries and check stability


----------



## Luggage

rul3s said:


> Guys, anyone could run 5800x with 4 dimms SR at high memory speed? With two dimm I can go [email protected] but with 4 dimm I can only reach 3466 without errors.
> Is this normal?
> Thanks!


My old set of GSkill flair 3200cl14


http://imgur.com/rMJkhnW


----------



## domdtxdissar

Audioboxer said:


> Was able to confirm I will be OK going back up to RttNom 6. Not sure there is anything left to do with this profile? I guess I can see if RttPark can get lowered!


You could try to lower your tRP and tRAS (+tRC)

I just completed this at 1.55vdimm.








Have installed my ram cooler so only have ~7 degree delta between idle and 25 cycles on the stock trident z sticks 

It was tWRRD1 stopping me from booting cl13 before, so iam trying a run with tRDWR 10 now..

_edit_

Nevermind, i will also try straight for tRDWR 9


----------



## gusocnet

Was trying to test my Samsung C-die a bit more to see how stable it was after updating my BIOS in hope it'd help a bit. Got error #2 with the timings below with the exception of CsOdtDrvStr which was 20, so I bumped it to 24 to see if it helped. VDDG CCD is 1050 mV but it doesn't show there.



http://imgur.com/a8z7TAy

I got error #2 with CsOdtDrvStr after like 40-50 cycles of testing I think (left it overnight). Now with the value at 24 I ran for a few hours and didn't get any errors but I'm not too confident on this solving my problem. Anyone got any ideas?


http://imgur.com/Ya2z1hw


----------



## LxT1N

mongoled said:


> You do nothing wrong, to the contrary (apart from the GDM enabled) you are doing the right things.
> 
> On first look you seem to have a very good bin.
> 
> Set vDIMM to 1.45v, change tCL to 14 and then do a quick AIDA64, your latency should drop to some more.
> 
> I would attempt a 14-16-14-14 profile, as you know how to use the Ryzen Google "Calculator" fire in those primaries and check stability


 i will try it with 14-16-14-14 because i have try 14-14-14-14-28-42 on 3600 but was not possible at 1.45-1.47-1.49 dont know why i got fast a error on tm5


----------



## Audioboxer

domdtxdissar said:


> You could try to lower your tRP and tRAS (+tRC)
> 
> I just completed this at 1.55vdimm.
> View attachment 2526740
> 
> Have installed my ram cooler so only have ~7 degree delta between idle and 25 cycles on the stock trident z sticks
> 
> It was tWRRD1 stopping me from booting cl13 before, so iam trying a run with tRDWR 10 now..
> 
> _edit_
> 
> Nevermind, i still try straight for tRDWR 9 now
> View attachment 2526748


Is there not a point where it doesn't really matter about lowering tRAS and tRP? Or tRAS anyway?










I gave anta777 a quick spin as some people say it's tougher on the ram than 1usmus. I know 7~9 cycles is what most want to see, but don't have time for that right now.


----------



## mongoled

LxT1N said:


> i will try it with 14-16-14-14 because i have try 14-14-14-14-28-42 on 3600 but was not possible at 1.45-1.47-1.49 dont know why i got fast a error on tm5


You understand that you are pushing the limits of RAM (and other things) when you are overclocking ????

Sorry to have to state the obvious, but the direction you are wanting to go is not "plug n play" but more like "plug n pray"

😂 😂

Anyhow back to your queries, tRCDRD @14 when running 3800 is not a straight forward thing for most b-die, thats why I asked you to use 16.

So please can you try with tRCDRD @16 and report back if TM5 is less prone to errors ...


----------



## mongoled

Audioboxer said:


> Is there not a point where it doesn't really matter about lowering tRAS and tRP? Or tRAS anyway?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I gave anta777 a quick spin as some people say it's tougher on the ram than 1usmus. I know 7~9 cycles is what most want to see, but don't have time for that right now.


When you see that things stop scaling then stop going lower, thats if you dont get errors.

Main concern is if you are pushing values that are inherently too "low" that autocorrection is going to kick in ....


----------



## Audioboxer

mongoled said:


> When you see that things stop scaling then stop going lower, thats if you dont get errors.
> 
> Main concern is if you are pushing values that are inherently too "low" that autocorrection is going to kick in ....


Yeah I'm not really bothered about trying to push tRP/tRAS, more-so tRAS as I'm sure I've read there is a "cut off" point for it where it doesn't really matter if you go lower it's past the point of scaling even if it passes stability tests.


----------



## LxT1N

mongoled said:


> You understand that you are pushing the limits of RAM (and other things) when you are overclocking ????
> 
> Sorry to have to state the obvious, but the direction you are wanting to go is not "plug n play" but more like "plug n pray"
> 
> 😂 😂
> 
> Anyhow back to your queries, tRCDRD @14 when running 3800 is not a straight forward thing for most b-die, thats why I asked you to use 16.
> 
> So please can you try with tRCDRD @16 and report back if TM5 is less prone to errors ...


😞 no this was the idea that i have to put my kit 3600cl14 flat then to much people tell me that 3800cl16 sre better then 3600cl14 thats because i have trying it on 3600cl16


----------



## domdtxdissar

Audioboxer said:


> Is there not a point where it doesn't really matter about lowering tRAS and tRP? Or tRAS anyway?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I gave anta777 a quick spin as some people say it's tougher on the ram than 1usmus. I know 7~9 cycles is what most want to see, but don't have time for that right now.


Well, i'm sure some ppl will disagree with me, but this is my reasoning

With tRP being a "base value" not "calculated" from other numbers, i would say lower is always better
_



tRP: Row Precharge Time. The amount of time it takes to deactivate (precharge) one row of memory and activate a new row of memory (on the same rank). This is how fast data is transferred from sense amplifiers back to the cells. You can think of this as essentially the “cooldown” between memory operations on the same rank, or side, of a DIMM. (Sidenote: it’s not necessary true that rank = side, especially for 4 or more DIMMs

Click to expand...

_Since you get tRC (performance) from tRP+tRAS, lower tRAS means lower tRC = better
_



tRAS: RAS Active Time. The minimum time between a row of memory being activated and precharged. This is the amount of cycles that a row of memory can be accessed for reading/writing. Just like the name suggests, it’s how long the RAS capacitor stays active once it receives a signal from the IMC.

Overclocking guidelines? : Hearsay says that a good starting point is something near tCL + tRP. The specific value you can reach depends on the die.

Click to expand...





tRC :Row Cycle Time. The minimum amount of time between activation commands to the same memory bank. Just like the name suggests, this is the amount of cycles that the IMC has to wait before it can send another activation signal to a bank of memory.

Overclocking guidelines? : By definition, the lowest this can go is tRAS + tRP. The reason is as follows: tRAS is the number of cycles from activation to precharging, and tRP is the number of cycles between precharging and the activation of another row. Thus, tRAS + tRP is the number of cycles between activating one row of memory and activating another. If you’ll think back one paragraph, that’s exactly what tRC is for.

Click to expand...

_Some argue that "flat" timings like 14-14-14-28-42 is the best, but in my testing, stuff like tRCDWR @ 8 and tRP 12 always outperform those..

My TRDWR 9 testing is still going strong


----------



## Audioboxer

domdtxdissar said:


> Well, i'm sure some ppl will disagree with me, but this is my reasoning
> 
> With tRP being a "base value" not "calculated" from other numbers, i would say lower is always better
> 
> 
> Since you get tRC (performance) from tRP+tRAS, lower tRAS means lower tRC = better
> 
> 
> Some argue that "flat" timings like 14-14-14-28-42 is the best, but in my testing, stuff like tRCDWR @ 8 and tRP 12 always outperform those..
> 
> My TRDWR 9 testing is still going strong
> View attachment 2526750


I'll have a play around, it's always fun to tinker. Without a doubt I did see some evidence of read/write improvement putting tRCDWR to 8.

I really hope the 3D chips or whatever AMD end up calling them will have better memory controllers because at the point we're at many will rightfully point out we're not really gaining anything. Constrained by CPU/architecture more than anything. Could probably run a flat 15 profile and get next to the same real world performance on a 5950x 

Though, when you watercool your ram, or seriously aircool it, you just have to push it!


----------



## mongoled

@LxT1N
I explained to you I don't do support via PM. 

I have provided you with what I would try (tRCDRD @16) and you PM asking for help with flat 14s.....

Sorry that my advice is not good for you, hopefully somone can give you all the time you need


----------



## LxT1N

mongoled said:


> @LxT1N
> I explained to you I don't do support via PM.
> 
> I have provided you with what I would try (tRCDRD @16) and you PM asking for help with flat 14s.....
> 
> Sorry that my advice is not good for you, hopefully somone can give you all the time you need


ok sorry


----------



## Audioboxer

domdtxdissar said:


> You could try to lower your tRP and tRAS (+tRC)
> 
> I just completed this at 1.55vdimm.
> View attachment 2526740
> 
> Have installed my ram cooler so only have ~7 degree delta between idle and 25 cycles on the stock trident z sticks
> 
> It was tWRRD1 stopping me from booting cl13 before, so iam trying a run with tRDWR 10 now..
> 
> _edit_
> 
> Nevermind, i will also try straight for tRDWR 9
> View attachment 2526748


Dom I meant to ask you what is it that causes your read and write to be mental? Is it bugging out because of you disabling 1 CCD to get an "actual" RAM latency rather than a latency constrained by 2 CCDs?

I mean, it _looks_ awesome 🤣 80,000 at 3800!


----------



## Audioboxer

Had a peak at tRP 13 and I dropped CsOdtDrvStr off 30 just to see if it was even needed. Fastest the test has completed but I doubt changing those two things is enough to cut off over a minute. Probably just the variations of test length in play.


----------



## rul3s

Luggage said:


> My old set of GSkill flair 3200cl14
> 
> 
> http://imgur.com/rMJkhnW


For me its just imposible. With 2 dimms (2ranks) I cant go higher as [email protected] with tight subtimmings (fast presset from calculator), but with 4 dimms (4ranks) I can't go behind 3466 with same timmings without getting BSOD.
Both RAM kits can reach the speed separately.

Actually I'm running those timmings for [email protected], is there anything wrong so I can't reach 3600 without getting BSOD?










any idea?

Thanks a lot!


----------



## Frosted racquet

mongoled said:


> Increase vSOC two steps and test again to see if anything has changed


Here's an update, I think I have it figured out with your help and @Veii.

Reverted back to XMP profile, only increased VSOC to 1.15v and no errors with 1usmus profile for 25 cycles, which is the first time there were no errors with XMP timing. Forgot to disable GDM that time, retested with GDM disabled and 2T, but this time various errors again. Wanted to cry and set the RAM on fire because I forgot GDM can be a pain like that.
Tried @Veii recommendation VDIMM 1.38v, tRDWR 10, CAD_BUS 40-20-30-24 but the errors kept popping up. Reverted back CAD_BUS to straight 24, after 5+ hours of testing, no errors. SO it seems either a combination of VSOC, VDIMM and tRDWR or just tRDWR were problematic.


----------



## MrHoof

rul3s said:


> For me its just imposible. With 2 dimms (2ranks) I cant go higher as [email protected] with tight subtimmings (fast presset from calculator), but with 4 dimms (4ranks) I can't go behind 3466 with same timmings without getting BSOD.
> Both RAM kits can reach the speed separately.
> 
> Actually I'm running those timmings for [email protected], is there anything wrong so I can't reach 3600 without getting BSOD?
> 
> View attachment 2526786
> 
> 
> any idea?
> 
> Thanks a lot!


Set procODT RTTs and all DrvStr to auto. The RTT for sure are for 2xSR fine but can be your problem at 4xSR, ProcODT might be fine at 40 but could also go lower. Also 1T without setup timings or GDM at 3800 is difficult rather start with 2T

edit: Also your vddg IOD is a little low maybe try .975


----------



## domdtxdissar

Audioboxer said:


> Dom I meant to ask you what is it that causes your read and write to be mental? Is it bugging out because of you disabling 1 CCD to get an "actual" RAM latency rather than a latency constrained by 2 CCDs?
> 
> I mean, it _looks_ awesome 🤣 80,000 at 3800!


I'm not running with one CCD disabled.. 
Using Hydra to correct the CPPC layout and forcing Aida to abide by it, in effect tweaking my dual ccd cpu to behaves like a single ccd in regards to memory latency, like Aida should have done from the get-go.

In regards to bandwidth,that is only because aida is a joke and should not be used as a performance metric, like i've said countless times now. Its simply affinity/hydra tweaks in regards to forcing CPPC layout.. Showing its way to easy to optimize for fantasy numbers in this "benchmark" with no bearing on how fast the setup really is.

Dram calc is a much better real performance indicator 



> Had a peak at tRP 13 and I dropped CsOdtDrvStr off 30 just to see if it was even needed. Fastest the test has completed but I doubt changing those two things is enough to cut off over a minute. Probably just the variations of test length in play.


Think we have also been through this previously in this thread, the more memory usage you have from other things then TestMem, the faster runtime you will have.. Think it was our german friend who showed a completed single cycle in something like under 1 minute since he had pretty much no free memory when the started TestMem..

The more optimized windows install you have, with low memory footprint, the slower will you complete 25 cycles..








32*816 = You (only) had 26 gigs free when started the stresstest.
If you had more programs/apps open while running the test, it it would have finished even faster 

Anyway, i completed my own 25 cycles @ tRDWR9 after hydra crashed testmem at cycle 23 on the first try ¤%#&%&%


----------



## Audioboxer

domdtxdissar said:


> I'm not running with one CCD disabled..
> Using Hydra to correct the CPPC layout and forcing Aida to abide by it, in effect tweaking my dual ccd cpu to behaves like a single ccd in regards to memory latency, like Aida should have done from the get-go.
> 
> In regards to bandwidth,that is only because aida is a joke and should not be used as a performance metric, like i've said countless times now. Its simply affinity/hydra tweaks in regards to forcing CPPC layout.. Showing its way to easy to optimize for fantasy numbers in this "benchmark" with no bearing on how fast the setup really is.
> 
> Dram calc is a much better real performance indicator
> 
> 
> Think we have also been through this previously in this thread, the more memory usage you have from other things then TestMem, the faster runtime you will have.. Think it was our german friend who showed a completed single cycle in something like under 1 minute since he had pretty much no free memory when the started TestMem..
> 
> The more optimized windows install you have, with low memory footprint, the slower will you complete 25 cycles..
> View attachment 2526854
> 
> 32*816 = You (only) had 26 gigs free when started the stresstest.
> If you had more programs/apps open while running the test, it it would have finished even faster
> 
> Anyway, i completed my own 25 cycles @ tRDWR9 after hydra crashed testmem at cycle 23 on the first try ¤%#&%&%
> View attachment 2526855


Thanks for the explanation! 

I guess that also makes sense about free memory available. I usually start a TM5 after a fresh reboot and it seems at the start it has less memory available in comparison to the following cycles. Either way I haven't been modifying my runs by closing anything so in theory the test parameters are the same each time.

Whilst I was watching the football I just quickly ran this to rest tRAS and tRC dropping down










But now I need to think about tRP and whether to stick with 13 or maybe try 12 like yourself and recalculate what I should use with tRAS/tRC.

I'm also planning to revisit RttNom 7. Who ever said a profile is ever complete? 👀

What I am happy to say is at least it looks like our bins are comparable at this level meaning others who buy this bin could hope to replicate.


----------



## RosaPanteren

Got the BartXstore heat spreader's today










And decided to try to solder them to the ram waterblock.......I got no soldering skill at all so that was fun, but it worked out okey, though not so pretty

The result would probably be same for alu heat spreader's ad the solder will be the thermal bottleneck



Spoiler: pic's






























Idea was to melt the dimms down.....probably a reasonable bad idea, but it worked out okey it seems









Yep I don't know squat about soldering..

Anyway I used a solder that is 96% tin, 3.5% silver and 0.5% copper, this has a thermal conductivity of 57-60 W/(mK)











Long story short, dimm temp now maxes out about 4-5c over water temp at full load.

Running fans at 600 rpm for the cpu/dimm loop I can't really hear them, and this gives a max dimm temp of about 25-26c at @1.56v rtt's 7/3/3

I used to have to run the dimm fan @1800 rpm to keep the dimm temp below/max of 38-40c, at 600rpm it would have been +50c easily

Loop draws cold air from the window so while room temp is about 22-23c, water temp is 20 +- 2c


----------



## evilhf

I got 2033mhz IF / 4066 stability in memory with tight latencies!!
Memory is blocked (Barrow Ram block) 4 sticks


----------



## KedarWolf

evilhf said:


> View attachment 2526881
> 
> I got 2033mhz IF / 4066 stability in memory with tight latencies!!
> Memory is blocked (Barrow Ram block) 4 sticks


Does it pass OCCT with no WHEA errors though?


----------



## evilhf

KedarWolf said:


> Does it pass OCCT with no WHEA errors though?


I have whea errors approximately after 30 seconds of open hwinfo , but everything works normally including I don't lose performance in cpuz comparing for example 4.7ghz allcores with 1900 in memory where I don't have whea errors.
Same score and frame gain in memory sensitive games...
So I don't worry about these mistakes...


----------



## evilhf

my pc 😜


----------



## Sleepycat

rul3s said:


> For me its just imposible. With 2 dimms (2ranks) I cant go higher as [email protected] with tight subtimmings (fast presset from calculator), but with 4 dimms (4ranks) I can't go behind 3466 with same timmings without getting BSOD.
> Both RAM kits can reach the speed separately.
> 
> Actually I'm running those timmings for [email protected], is there anything wrong so I can't reach 3600 without getting BSOD?
> 
> View attachment 2526786
> 
> 
> any idea?
> 
> Thanks a lot!


Some of the sub-timings you have there actually causes issues with POST and BSOD when I use them on my 4x16GB kit. I run 1.465V vDIMM on my dual rank B-die with the following settings:


----------



## error-id10t

Any suggestions what to tune here. I am not looking to overclock like most of you here, looking for some fine-tuning suggestions only.


----------



## Dodgexander

error-id10t said:


> Any suggestions what to tune here. I am not looking to overclock like most of you here, looking for some fine-tuning suggestions only.
> 
> View attachment 2526891
> View attachment 2526892


There's many people asking questions (including me) but not many people answering... Feels a bit like being at a busy bar and never getting served  I'll try buck the trend... Best advice I can give you is lower voltages one by one until unstable, then tune each memory timing one by one testing stability in-between. TM5 isn't the best test for FCLK stability, use y-cruncher instead. TM5 with anta extreme preset is good for tightening timings though.

Don't bother with the quick fix dram calculator. If you key in random values you'll never know where you went wrong. Patience and time is required in abundance.


----------



## PJVol

evilhf said:


> everything works normally including I don't lose performance in cpuz


Mind posting AIDA cache-memory bench result?


----------



## mongoled

Dodgexander said:


> Feels a bit like being at a busy bar and never getting served


Good analogy, just the "bar tenders" are the customers of the bar and most of them are just interested in getting drunk

😂 😂


----------



## LxT1N

i have trying to get 14-14-14-14-28-42 but i got error 2,6,10,11,12,13 that because i try this setting i dont know if the are good enough or what i can changed if someone help me to tuning more my ram kit please let me know what i need to do on this settings i will testet it with y-cruncher to see are this stable enough neeed to put cmd2t back to 1?

I used this data

VDDSOC Voltage = 1.1V
DRAM = 1.45V
VDDG CCD Voltage = 0.95V
VDDG IOD Voltage = 1.05V
CLDO VDDP Voltage = 0.9V


----------



## mongoled

Arghhh

errors popped up on cycle 20

reboot time ....

😂


----------



## LxT1N

are this right on my setting? i used dark hero 8 with dual ram kit 2x16gb

ProcODT : 40
Cmd2T : 2
Gear Down Mode : Disabled
Power Down Enable : Disabled
RttNom : Disable
RttWr : RZQ/3
RttPark : RZQ/1

MemCadBusClkDrvStren : 40
MemCadBusAddrCmdDrvStren : 20
MemCadBusCsOdtDrvStren : 30
MemCadBusCkeDrvStren : 40

any help? or i need to put

ProcODT : 28.2

MemCadBusClkDrvStren : 60
MemCadBusAddrCmdDrvStren : 20
MemCadBusCsOdtDrvStren : 24
MemCadBusCkeDrvStren : 24


and how long i need to make the y cruncher test?


----------



## Audioboxer

tRP 12 seems to suggest it will be OK, so dom and I are pretty much performing the same with this kit at 3800. Just to try RttNom 7 next then maybe RttPark 4/5.


----------



## mongoled

LxT1N said:


> are this right on my setting? i used dark hero 8 with dual ram kit 2x16gb
> 
> ProcODT : 40
> Cmd2T : 2
> Gear Down Mode : Disabled
> Power Down Enable : Disabled
> RttNom : Disable
> RttWr : RZQ/3
> RttPark : RZQ/1
> 
> MemCadBusClkDrvStren : 40
> MemCadBusAddrCmdDrvStren : 20
> MemCadBusCsOdtDrvStren : 30
> MemCadBusCkeDrvStren : 40
> 
> any help? or i need to put
> 
> ProcODT : 28.2
> 
> MemCadBusClkDrvStren : 60
> MemCadBusAddrCmdDrvStren : 20
> MemCadBusCsOdtDrvStren : 24
> MemCadBusCkeDrvStren : 24
> 
> 
> and how long i need to make the y cruncher test?
> 
> View attachment 2526914


Y-Cruncher

Press 1 --> Enter ---> Press 7 --> Enter --> Press 0

This will run all the tests, I run it for up to 4 hours


----------



## mongoled

Audioboxer said:


> tRP 12 seems to suggest it will be OK, so dom and I are pretty much performing the same with this kit at 3800. Just to try RttNom 7 next then maybe RttPark 4/5.


Can you stop posting ??

You are going to make my buy another Viper Steel kit

😂 😂


----------



## Audioboxer

mongoled said:


> Can you stop posting ??
> 
> You are going to make my buy another Viper Steel kit
> 
> 😂 😂












I've entered throw everything at a wall stage again, almost got tRCDRD 13 to pass a minute 👀 Previously it would duck out within 10~30 seconds. I know it doesn't really scale with voltage but pumping it up to 1.6v _seemed_ to help a tiny bit.

@domdtxdissar Have you tried playing around with tCRDRD 13 at all? Or are you completely stuck with the crashes within 10-30 seconds?


----------



## mongoled

Audioboxer said:


> I've entered throw everything at a wall stage again, almost got tRCDRD 13 to pass a minute 👀 Previously it would duck out within 10~30 seconds. I know it doesn't really scale with voltage but pumping it up to 1.6v _seemed_ to help a tiny bit.
> 
> @domdtxdissar Have you tried playing around with tCRDRD 13 at all? Or are you completely stuck with the crashes within 10-30 seconds?


Try 5/2/7


----------



## Mach3.2

LxT1N said:


> and how long i need to make the y cruncher test?


You run all tests for _at least_ 4 iterations; open y-cruncher, enter 1-7-0.


----------



## Audioboxer

mongoled said:


> Try 5/2/7


6 is the highest I can post park. Still fail around 1 minute.

First step is settings that let me get passed failing on 6 right at the start, but if I get passed that the 12/2's normally quickly follow 🤣

I shouldn't be surprised with tRCDRD 13 at 3800 though.


----------



## Bix

Looking for some advice please... I've spent a good while working on getting 2000fclk stable on my 5900x/b550 unify and think I've finally cracked it aside from the whea 19s (I'm 1hr y-cruncher stable and tested with LatencyMon). I've just been using XMP so far and not sure if it's best to tune PBO or memory next. I'm presuming both will have an impact on the voltages that are working currently...

Any help gratefully received!


----------



## PJVol

Does they look like A1 pcb revision?

















Thaiphoon reported A1/10 layer.
TBH, didn't expect that "el cheapo" package, that looked like kinda oem.


----------



## mongoled

Audioboxer said:


> tRP 12 seems to suggest it will be OK, so dom and I are pretty much performing the same with this kit at 3800. Just to try RttNom 7 next then maybe RttPark 4/5.


Just noticed something that both your and Dom are doing, this is solely based on the "Ryzen Google Calculator"

According to the timings you are using tRFC should be 180/134/82.

As you are not running those refresh rates I am guessing that alot of autocorrection is going on in the background which is keeping things stable at the cost of some performance.

The only reason I noticed that is because I accidently has a "wrong" tRC value for the tCL 13 set im trying to get stable, once I corrected it to the right value "error 10" started to appear, where as using the tighter timing and incorrect tRFC values was not giving me error 10s ....


----------



## Audioboxer

mongoled said:


> Just noticed something that both your and Dom are doing, this is solely based on the "Ryzen Google Calculator"
> 
> According to the timings you are using tRFC should be 180/134/82.
> 
> As you are not running those refresh rates I am guessing that alot of autocorrection is going on in the background which is keeping things stable at the cost of some performance.
> 
> The only reason I noticed that is because I accidently has a "wrong" tRC value for the tCL 13 set im trying to get stable, once I corrected it to the right value "error 10" started to appear, where as using the tighter timing and incorrect tRFC values was not giving me error 10s ....


Well, 180 is obviously not feasible. What is the calculator based on, official documentation or user made from learned knowledge? I guess I'll go look it up.

Not saying you're necessarily wrong, I don't know, but I'd like to know how someone or some thing is calculating 180/134/82 is _needed_. Especially when performance looks great where we are.

@Veii Care to weigh in on the timings me and Dom are running requiring 180/134/82? I might try booting it for a laugh but I'd be worried running 180 for tRFC might even nuke the Windows installation (if it even posts)  I've booted 220 ok, but that is already dropping under 120ns.


----------



## mongoled

Audioboxer said:


> Well, 180 is obviously not feasible. What is the calculator based on, official documentation or user made from learned knowledge? I guess I'll go look it up.
> 
> Not saying you're necessarily wrong, I don't know, but I'd like to know how someone or some thing is calculating 180/134/82 is _needed_. Especially when performance looks great where we are.
> 
> @Veii Care to weigh in on the timings me and Dom are running requiring 180/134/82? I might try booting it for a laugh but I'd be worried running 180 for tRFC might even nuke the Windows installation  I've booted 220 ok, but that is already dropping under 120ns.


Nothing to do with me being wrong!

Im just the messenger, the "Ryzen Google Calculator" was built by someone posting here based on RAM manufacturer resources, to my knowledge its one of the most accurate calculators we have access to.

I just inputted your timings and that is the tRFC values that it spits back.

To get tRP to 5 you need to modify the tRC function on the calculator to add tRC *5 .

Of course no one has to agree, though I do my best to keep things in sync ..


----------



## Audioboxer

mongoled said:


> Nothing to do with me being wrong!
> 
> Im just the messenger, the "Ryzen Google Calculator" was built my someone posting here based on RAM manufacturer resources, to my knowledge its one of the most accurate calculators we have accesss to.
> 
> I just inputted your timings and that is the tRFC values that it spits back.
> 
> To get tRP to 5 you need to modify the tRC function on the calculator to add tRC *5 ...


Fair enough, but those values for tRFC just seem way out of line. They don't post, obviously.

Damn manufacturers don't even care about secondary timings normally, just binning primary timings and leaving the motherboard to auto everything else 🤣

As long as membench looks good and stability tests pass this memory can autocorrect whatever it wants lol.


----------



## mongoled

Audioboxer said:


> Fair enough, but those values for tRFC just seem way out of line. They don't post, obviously.
> 
> Damn manufacturers don't even care about secondary timings normally, just binning primary timings and leaving the motherboard to auto everything else 🤣


Thats the point, you are running tRFC values that are not in sync with the other timings, obviously such low tRFCs are not going to work ..........

Unless you are going to -90C 

😂 😂


----------



## Audioboxer

mongoled said:


> Thats the point, you are running tRFC values that are not in sync with the other timings, obviously such low tRFCs are not going to work ..........
> 
> *Unless you are going to -90C*
> 
> 😂 😂


Challenge accepted 🥶

Yeah I get that, but that means someone is going to have to explain why manufacturers think 666 is an acceptable tRFC on a b-die chip running XMP


----------



## mongoled

Audioboxer said:


> Challenge accepted 🥶
> 
> Yeah I get that, but that means someone is going to have to explain why manufacturers think 666 is an acceptable tRFC on a b-die chip running XMP


😂 😂


----------



## Audioboxer

mongoled said:


> 😂 😂


I swear I'll do it!

But you have got me thinking about what my next venture will be, lowest VDIMM possible for sensible timings that pretty much, in terms of real world performance, perform like these stupid low (and in parts likely _incorrect_) tCL13 timings.

It's fun to overclock and it's fun to "underclock" and maximise performance on a set budget. 1.35v profile here we come 

Watercooling 1.35v, I might even hit -90 degrees!

Semi-serious about the above btw, but I think next will be trying to look at 2000 FCLK+. It can be booted, so let's see if I can stabilise it for benching/stability tests.


----------



## MrHoof

mongoled said:


> Nothing to do with me being wrong!
> 
> Im just the messenger, the "Ryzen Google Calculator" was built by someone posting here based on RAM manufacturer resources, to my knowledge its one of the most accurate calculators we have access to.
> 
> I just inputted your timings and that is the tRFC values that it spits back.
> 
> To get tRP to 5 you need to modify the tRC function on the calculator to add tRC *5 .
> 
> Of course no one has to agree, though I do my best to keep things in sync ..


As far as i understand it its, trc*trtp is the lowest value possbile "in sync" going higher shouldnt not mean its automaticly out of sync.


----------



## Pictus

mongoled said:


> Nothing to do with me being wrong!
> 
> Im just the messenger, the "Ryzen Google Calculator" was built by someone posting here based on RAM manufacturer resources, to my knowledge its one of the most accurate calculators we have access to.


It is, but it is broken again... Those kids... 
I wish it could work with _LibreOffice_.


----------



## mongoled

Pictus said:


> It is, but it is broken again... Those kids...
> I wish it could work with _LibreOffice_.


At least from the phone app you can copy the sheets to your Google account (if using Android) and then no one can break it again



Do this once someone fixes it...


----------



## Pictus

mongoled said:


> At least from the phone app you can copy the sheets to your Google account (if using Android) and then no one can break it again
> 
> 
> 
> Do this once someone fixes it...


I do not use phone anymore...


----------



## Audioboxer

The calculator does seem pretty sensible so I take back my earlier worries about what it was. Will just keep an eye on memory and benching when operating outside of potentially expected parameters.

Going to have a look at IF 2000 over the next few days so that will be WHEA suppression and trying to run stability tests and find out if they can pass. XMP settings to start with I guess, given I'm binned for 4000.

Any rough tips for me on voltage expectations for 2000 FCLK? More so, so I don't boot anything stupid and destroy Windows. I think I've seen VSOC will need to be nearer 1.2v. VDDP changes?


----------



## Mach3.2

Pictus said:


> I do not use phone anymore...


On the web version, try: File > make a copy


----------



## Veii

Audioboxer said:


> Well, 180 is obviously not feasible. What is the calculator based on, official documentation or user made from learned knowledge? I guess I'll go look it up.
> 
> Not saying you're necessarily wrong, I don't know, but I'd like to know how someone or some thing is calculating 180/134/82 is _needed_. Especially when performance looks great where we are.
> 
> @Veii Care to weigh in on the timings me and Dom are running requiring 180/134/82? I might try booting it for a laugh but I'd be worried running 180 for tRFC might even nuke the Windows installation (if it even posts)  I've booted 220 ok, but that is already dropping under 120ns.


The calculator was made by a group of people whp followed JEDEC and couple overclockers
The tRFC part is what i try to push, based on a Korean Researcher who based it's research upon several JEDEC revisions

Mind you, every new big revision, trows away old learned research
And also that memory the timings you set are half of what happens and modifies in realtime
Well 65-70%, half is a bit overemphasised

Currently on holiday (again) till the 9th, and then i'll get the dual ranks to play with (waiting for shipment from another OCer)

This needs a big post to explain things, and i think i've done in the past such posts
But in general,
- There is no need to push tRFC thaat low, but if you want ~ then calculate it "correctly"
(saying that while knowing my flaw and the lack of knowledge in tSTAG & tMRD states + working with tRC_PAGE blindly)

I had phrased that there is never only one correct way
That JEDEC is not "one" holy book, and that timings between platforms, soo also operation focus will be different

In such case flat flat timings operate different
That and the 1x tFAW exploit which up to JEDEC appears impossible works out (cycle stacking, bypassing tRC)
And so SD, DD, DG differences + tRRD_ & tWTR_ "distances/additives" drastically change, how primaries behave and operate

At the very end, like you mentioned
"It can autocorrect as much as it wants, as long as it's stable and performs"
Soo everything is fine

This wont answer your question,
But to say it in short
If you want to push, tTRP has to fit insife tRFCns
Same would be for tWRns, yet only tRTP matters

tRTP + tRCD = absolute minimum tRAS
Yet tRCDavg*2 = tRAS also is optimal
This here plays a key role , skipping tRP
tRP got quoted correctly, but memort does 4-5 things at the same time
Its not a one way path x + y = z
Soo what is called "in sync" means how it's phrased
But the "method of sync" ~ that will always be a debate, because memory timings can be delayed on one part, put om the other too low to always trigger if access is random in an average interval

It depends 
There is no "correct way" of operation, is what i learned
Only "is it stable ?" "Can it surpass reaching thermal equilibrium at X time ?" Is it at least 20+ (25+) cycle of this cfg or anta's 3 loops , stable ?
"Does it perform and keep performing between cold reboots ?"

My part in this tRFC calculator aside from some long discussion about tBURST, SizePage & tRFC
Was rather focused on discharge prediction
Not my research towards the prediction ~ but my anchor towards it set on tRC
It was initially in tCL

Discharge prediction + cycle stacking (not as good as 1usmus can optimize his timings)
Depends on VDIMM. Soo a direct affector is tRP & tRAS+tRP "correctness"
Even when to me explained well by engineers "never all of 1.6milion cells" would follow the perfect transition path
= +1 tRC, +2, +4, +8 all are used to stabilise and also "fix/hide" instability for XOC and well ~ XMP
As XMP is forced to follow heat dissipating laws & trace noise levels

Soo if heatsinks on these would improve, like the PCBs keep improving
We might get a new XMP standard , not intel extreme memory profile outdated with too lose timings
They pushed the work to bios engineers ~ on AMDs case, to AMD directly

Complicated topic, too long of a history lesson required,
In general,
Push it as low as performance keeps scaling (it will stop)
Then when it stops, it means it was too low and got postponed, soo increase it back

And if you want to experiment a bit
Focus on tRCD+tRP = tRAS
And increase tRTP as high as you like, or work in the calculator rulesets with tRTP being the multiplier for it
You can have enough fun, as "low" doesnt mean "performant"
Well chained together without wasted delay, means performance
Access time, is just a little side-goal, till it stops scaling much 

* i've run tRFC down to 113ns with around 1.56v
But that was with GDM help
Without, bellow 118 will be hard
All a voltage thing after all

Meanwhile, i sitt at 144ns, because of my tRASmin, following
Soo i invite you to join the 1.65-1.69v club too
It's cozy warm here & when you can daily it, why shouldn't you at the very end x)
EDIT:
If i drop tRFC further down, i get worse results not better results
It still scales by vdimm, but it depends on timings too
Too low will be postponed & show no access time difference


----------



## Audioboxer

Veii said:


> The calculator was made by a group of people whp followed JEDEC and couple overclockers
> The tRFC part is what i try to push, based on a Korean Researcher who based it's research upon several JEDEC revisions
> 
> Mind you, every new big revision, trows away old learned research
> And also that memory the timings you set are half of what happens and modifies in realtime
> Well 65-70%, half is a bit overemphasised
> 
> Currently on holiday (again) till the 9th, and then i'll get the dual ranks to play with (waiting for shipment from another OCer)
> 
> This needs a big post to explain things, and i think i've done in the past such posts
> But in general,
> ~ there is no need to push tRFC thaat low, but if you want ~ then calculate it "correctly"
> (saying that while knowing my flaw and the lack of knowledge in tSTAG & tMRD states + working with tRC_PAGE blindly)
> 
> I had phrased that there is never only one correct way
> That JEDEC is not "one" holy book, and that timings between platforms, soo also operation focus will be different
> 
> In such case flat flat timings operate different
> That and the 1x tFAW exploit which up to JEDEC appears impossible works out (cycle stacking, bypassing tRC)
> And so SD, DD, DG differences + tRRD_ & tWTR_ "distances/additives" drastically change, how primaries behave and operate
> 
> At the very end, like you mentioned
> "It can autocorrect as much as it wants, as long as it's stable and performs"
> Soo everything is fine
> 
> This wont answer your question,
> But to say it in short
> If you want to push, tTRP has to fit insife tRFCns
> Same would be for tWRns, yet only tRTP matters
> 
> tRTP + tRCD = absolute minimum tRAS
> Yet tRCDavg*2 = tRAS also is optimal
> This here plays a key role , skipping tRP
> tRP got quoted correctly, but memort does 4-5 things at the same time
> Its not a one way path x + y = z
> Soo what is called "in sync" means how it's phrased
> But the "method of sync" ~ that will always be a debate, because memory timings can be delayed on one part, put om the other too low to always trigger if access is random in an average interval
> 
> It depends
> There is no "correct way" of operation, is what i learned
> Only "is it stable ?" "Can it surpass reaching thermal equilibrium at X time ?" Is it at least 20+ (25+) cycle of this cfg or anta's 3 loops , stable ?
> "Does it perform and keep performing between cold reboots ?"
> 
> My part in this tRFC calculator aside from some long discussion about tBURST, SizePage & tRFC
> Was rather focused on discharge prediction
> Not my research towards the prediction ~ but my anchor towards it set on tRC
> It was initially in tCL
> 
> Discharge prediction + cycle stacking (not as good as 1usmus can optimize his timings)
> Depends on VDIMM. Soo a direct affector is tRP & tRAS+tRP "correctness"
> Even when to me explained well by engineers "never all of 1.6milion cells" would follow the perfect transition path
> = +1 tRC, +2, +4, +8 all are used to stabilise and also "fix/hide" instability for XOC and well ~ XMP
> As XMP is forced to follow heat dissipating laws & trace noise levels
> 
> Soo if heatsinks on these would improve, like the PCBs keep improving
> We might get a new XMP standard , not intel extreme memory profile outdated with too lose timings
> They pushed the work to bios engineers ~ on AMDs case, to AMD directly
> 
> Complicated topic, too long of a history lesson required,
> In general,
> Push it as low as performance keeps scaling (it will stop)
> Then when it stops, it means it was too low and got postponed, soo increase it back
> 
> And if you want to experiment a bit
> Focus on tRCD+tRP = tRAS
> And increase tRTP as high as you like, or work in the calculator rulesets with tRTP being the multiplier for it
> You can have enough fun, as "low" doesnt mean "performant"
> Well chained together without wasted delay, means performance
> Access time, is just a little side-goal, till it stops scaling much
> 
> * i've run tRFC down to 113ns with around 1.56v
> But that was with GDM help
> Without, bellow 118 will be hard
> All a voltage thing after all
> 
> Meanwhile, i sitt at 144ns, because of my tRASmin, following
> Soo i invite you to join the 1.65-1.69v club too
> It's cozy warm here & when you can daily it, why shouldn't you at the very end x)


Thank you Veii, I always love reading your posts and others like mongoled who help out. I've always got something to learn! I could join the high voltage club, and I may well get there soon, but first I have this to contend with










XMP at 4000  At least the tRFC has changed from 666, just 700 now  I love how XMP is like 1.55v please, but an MSI board is like "yes, but I'll add the trademark +0.01v".

First thing I need to figure out is I installed the WHEAService from here to help suppress the yellow Bus/Interconnect Error's but some of them are still getting through. Need to contact Manni and see if I'm doing something wrong or if Windows 11 might not be fully compatible with the service.

*edit* - Service doesn't seem to autostart on Windows 11. Starting it manually and I think it's working.


----------



## MrHoof

I think that tool is ment to be used when you are sure that its stable not when you just start testing 🤣


----------



## Veii

Audioboxer said:


> First thing I need to figure out is I installed the WHEAService from here to help suppress the yellow Bus/Interconnect Error's but some of them are still getting through. Need to contact Manni and see if I'm doing something wrong or if Windows 11 might not be fully compatible with the service.
> 
> *edit* - Service doesn't seem to autostart on Windows 11. Starting it manually and I think it's working.


Yes it causes issues with Win11
Oh check Kedarwolf's post about the cache fix
Windows 11 kernel "accidentally" was incapable to work with AMDs new cache system
It was known since the first official dev leak, but it was "a forgotten oopsy" by optimising for Alder Lake

Check if this fixes your variable L3 cache issues. At least the access latency part
ManniX, is a bit busy too atm. Soon 

About tRFC and DRAM
There is something in work, based upon this JEDEC part
You know i can't spill the beans, but the community will get something on this tRFC & Page_Size part (not by me)
Soo till then, the google docs collective calculator, has to do justice (be enough) and my mini module 
It's been in work since surely 8+ months ~ can't say the dev either


----------



## Audioboxer

It's actually broke in Windows 11 anyway, Manni confirmed lol.










A quick 3 cycle just to see if anything _exploded_. Only yellow warnings for WHEA, no red errors which is good.










While this is _scary_ I keep going...

I guess I'll stick with RAM XMP just now and try and test CPU/IF. I plucked the VDDG and VSOC values "out of thin air", but I'll see if they hold up as is.


----------



## Veii

Audioboxer said:


> Any rough tips for me on voltage expectations for 2000 FCLK? More so, so I don't boot anything stupid and destroy Windows. I think I've seen VSOC will need to be nearer 1.2v. VDDP changes?


Check AMD maximum voltahe thread, still valid
IOD changes, SOC ranges seem to fit
cLDO_VDDP only covers MCLK, not FCLM

If you can train 4400+ on 2:1 , then this is enough for memory
VDDP covers CAD_BUS connectivity and procODT
Soo also RTT, but close to zero FCLK connection
900 is enough, as is 950
860 works too , but could be maaybe a bit lacking for 2133, or can cause IOL issues


----------



## Luggage

Veii said:


> The calculator was made by a group of people whp followed JEDEC and couple overclockers
> The tRFC part is what i try to push, based on a Korean Researcher who based it's research upon several JEDEC revisions
> 
> Mind you, every new big revision, trows away old learned research
> And also that memory the timings you set are half of what happens and modifies in realtime
> Well 65-70%, half is a bit overemphasised
> 
> Currently on holiday (again) till the 9th, and then i'll get the dual ranks to play with (waiting for shipment from another OCer)
> 
> This needs a big post to explain things, and i think i've done in the past such posts
> But in general,
> - There is no need to push tRFC thaat low, but if you want ~ then calculate it "correctly"
> (saying that while knowing my flaw and the lack of knowledge in tSTAG & tMRD states + working with tRC_PAGE blindly)
> 
> I had phrased that there is never only one correct way
> That JEDEC is not "one" holy book, and that timings between platforms, soo also operation focus will be different
> 
> In such case flat flat timings operate different
> That and the 1x tFAW exploit which up to JEDEC appears impossible works out (cycle stacking, bypassing tRC)
> And so SD, DD, DG differences + tRRD_ & tWTR_ "distances/additives" drastically change, how primaries behave and operate
> 
> At the very end, like you mentioned
> "It can autocorrect as much as it wants, as long as it's stable and performs"
> Soo everything is fine
> 
> This wont answer your question,
> But to say it in short
> If you want to push, tTRP has to fit insife tRFCns
> Same would be for tWRns, yet only tRTP matters
> 
> tRTP + tRCD = absolute minimum tRAS
> Yet tRCDavg*2 = tRAS also is optimal
> This here plays a key role , skipping tRP
> tRP got quoted correctly, but memort does 4-5 things at the same time
> Its not a one way path x + y = z
> Soo what is called "in sync" means how it's phrased
> But the "method of sync" ~ that will always be a debate, because memory timings can be delayed on one part, put om the other too low to always trigger if access is random in an average interval
> 
> It depends
> There is no "correct way" of operation, is what i learned
> Only "is it stable ?" "Can it surpass reaching thermal equilibrium at X time ?" Is it at least 20+ (25+) cycle of this cfg or anta's 3 loops , stable ?
> "Does it perform and keep performing between cold reboots ?"
> 
> My part in this tRFC calculator aside from some long discussion about tBURST, SizePage & tRFC
> Was rather focused on discharge prediction
> Not my research towards the prediction ~ but my anchor towards it set on tRC
> It was initially in tCL
> 
> Discharge prediction + cycle stacking (not as good as 1usmus can optimize his timings)
> Depends on VDIMM. Soo a direct affector is tRP & tRAS+tRP "correctness"
> Even when to me explained well by engineers "never all of 1.6milion cells" would follow the perfect transition path
> = +1 tRC, +2, +4, +8 all are used to stabilise and also "fix/hide" instability for XOC and well ~ XMP
> As XMP is forced to follow heat dissipating laws & trace noise levels
> 
> Soo if heatsinks on these would improve, like the PCBs keep improving
> We might get a new XMP standard , not intel extreme memory profile outdated with too lose timings
> They pushed the work to bios engineers ~ on AMDs case, to AMD directly
> 
> Complicated topic, too long of a history lesson required,
> In general,
> Push it as low as performance keeps scaling (it will stop)
> Then when it stops, it means it was too low and got postponed, soo increase it back
> 
> And if you want to experiment a bit
> Focus on tRCD+tRP = tRAS
> And increase tRTP as high as you like, or work in the calculator rulesets with tRTP being the multiplier for it
> You can have enough fun, as "low" doesnt mean "performant"
> Well chained together without wasted delay, means performance
> Access time, is just a little side-goal, till it stops scaling much
> 
> * i've run tRFC down to 113ns with around 1.56v
> But that was with GDM help
> Without, bellow 118 will be hard
> All a voltage thing after all
> 
> Meanwhile, i sitt at 144ns, because of my tRASmin, following
> Soo i invite you to join the 1.65-1.69v club too
> It's cozy warm here & when you can daily it, why shouldn't you at the very end x)
> EDIT:
> If i drop tRFC further down, i get worse results not better results
> It still scales by vdimm, but it depends on timings too
> Too low will be postponed & show no access time difference


Have a nice vacation 
I’m doing some more edc 700 testing, whole evening of y-cruncher 1b and screenshots, trying to analyse now >_<
But I think I’ll start a new thread when I have something.
Quick Q though: edc700 pulls less power ?!?


----------



## Audioboxer

Veii said:


> Check AMD maximum voltahe thread, still valid
> IOD changes, SOC ranges seem to fit
> cLDO_VDDP only covers MCLK, not FCLM
> 
> If you can train 4400+ on 2:1 , then this is enough for memory
> VDDP covers CAD_BUS connectivity and procODT
> Soo also RTT, but close to zero FCLK connection
> 900 is enough, as is 950
> 860 works too , but could be maaybe a bit lacking for 2133, or can cause IOL issues


Thanks. I'm running y-cruncher just now to see if I can trigger any fails or reboots or red WHEA errors.

Excited if it seems OK, while I don't like the idea of running with WHEA warnings I do like the idea of a completely new RAM profile to tune (4000) 😁

3800 flat 14? NOPE! 4000 flat 14 here we come! 🤣

What I struggle to understand and anyone can chime in, if something does appear stable at 2000 FCLK because it passes all stress tests and benches, what's the deal with AMD not being able to stop the WHEA spam? In their eyes is it not actually stable?


----------



## mongoled

Veii said:


> And so SD, DD, DG differences + tRRD_ & tWTR_ "distances/additives" drastically change, how primaries behave and operate


If you happen to have a link where you discuss this in more detail please send it me

😊


Audioboxer said:


> what's the deal with AMD not being able to stop the WHEA spam? In their eyes is it not actually stable?


I will get the violin.... 

😂😂😝


----------



## Audioboxer

mongoled said:


> If you happen to have a link where you discuss this in more detail please send it me
> 
> 😊
> 
> I will get the violin....
> 
> 😂😂😝


lol

y-cruncher didn't crash/stop but like 15 mins in my USB devices started freaking out and my Corsair commander pro decided it needed a firmware update (it doesn't).

I'll take that as USB devices connecting/disconnecting like crazy and IF not stable 🤣 More voltage here we come!


----------



## Danny.ns

I have made some progress regarding the FCLK 1900 hole issue that I would like to share. I've been at it these last days and this is what I have found;

Choosing the FCLK 1933 multiplier, and lowering BLCK to 98.3MHz gives a FCLK of 1900MHz and this POSTs and boots every single time, 100% of tries. Recall, FCLK 1900 hole issue means I have NEVER even POSTed (reach BIOS) with FCLK 1900 and BLCK 100 even with 1.4Vsoc, 1.3VDDGs,1.1V VDDP and LN2 MODE Enabled.

Another thing I have noticed is that somehow, if I have booted with FCLK 1933 multiplier, it "moves" the un-POSTable "higher". This is very hard/flimsy to describe - bare with me please. So for example:
99.5 BCLK and FCLK 1900 will never POST.
99 BCLK and FCLK 1900 will never POST.
BUT, if i reset BIOS first. Then only change FCLK to 1933MHz, save and quit, come back to BIOS, I can now POST using the *FCLK 1900* *multiplier* at "much" higher BCLKs. For example, now;
99.5 BCLK and FCLK 1900 will POST
up to ~99.88 and FCLK 1900 will POST
100 BCLK and FCLK 1900 will still *NOT* POST.

The next step was to check stability (if there was any). So doing the "trick" above i found;
~99.8-99.88 BCLK with 1900FCLK multiplier gave me "uncureable" WHEAs when playing games. I only tested about 1.2VSOC, 1.1VDDGs so I didnt go crazy.
But with 99.75MHz BCLK and FCLK 1900 multiplier I seem to not get any WHEAs in BFV for example.

Also, CPU boosting works normally when lowering BCLK, but gets disabled (CPU stuck at 3700MHz) if you increase BCLK. So choosing FCLK 1900 multiplier and lowering BCLK is prefered (for me) over 1866 Multiplier with increased BCLK for this reason.

This means 99.75BCLK gives me a "stable" FCLK at 1895MHz (pretty close to the real deal).

So atm I am testing with HCI and trying to find best primary timings and I need 1.535Vdimm for this (Zentimings doesn't consider BCLK so its "fake" 1900);


----------



## Audioboxer

HNT test is what is causing my USB devices to freak out in y-cruncher. Anyone know what that test is about? Can obviously keep pumping voltage but it would be good to know what HNT is stressing most. I'm sure USB freaking out is a symptom not that HNT is testing USB 🤣


----------



## Audioboxer

lol, because iCUE is an absolute garbage piece of software every time instability freaks out my USB devices it basically wipes all my iCUE profiles/settings 

I think I've met my match, trying to stabilise 2000 FCLK and get it to pass HNT test in y-cruncher without freaking out.


----------



## mongoled

Audioboxer said:


> lol, because iCUE is an absolute garbage piece of software every time instability freaks out my USB devices it basically wipes all my iCUE profiles/settings
> 
> I think I've met my match, trying to stabilise 2000 FCLK and get it to pass HNT test in y-cruncher without freaking out.


increase iod for usb issues


----------



## umeng2002

Has anyone ran into RAM cooling issues?

My 4x8GB Samsung B-die keeps failing Karhu at like around 2000% coverage at different speeds, timings, and VDDG voltages. On my old motherboard, these timings passed Karhu to at least 10,000% coverage. The only thing different between them besides the motherboard is the amount of cooling fans I have installed (less in the new system).

I'm running just 1.38 to 1.4 v on the RAM.


----------



## Audioboxer

mongoled said:


> increase iod for usb issues


Thanks, I was trying to isolate which one could help. It kept nuking my iCUE settings though so I gave up for tonight lol.










My task at the moment was, question "Can I run tRCDRD 13 at 3800?"

Answer? Well, technically, it looks like I might be able to  Couldn't get past a minute before, put all settings on auto, and it's moving along. But I have no idea the full extent of what GDM does, tCL is stuck at 14 due to GDM and ProcODT is having a mad one and going to 60 on auto lol.

But still, I'll see if I can get something on 2T ticking along with tRCDRD 13.


----------



## domdtxdissar

mongoled said:


> Just noticed something that both your and Dom are doing, this is solely based on the "Ryzen Google Calculator"
> 
> According to the timings you are using tRFC should be 180/134/82.
> 
> As you are not running those refresh rates I am guessing that alot of autocorrection is going on in the background which is keeping things stable at the cost of some performance.
> 
> The only reason I noticed that is because I accidently has a "wrong" tRC value for the tCL 13 set im trying to get stable, once I corrected it to the right value "error 10" started to appear, where as using the tighter timing and incorrect tRFC values was not giving me error 10s ....


Working on a other timing set 
(was running tRC*7 before)









Still running 1.550 vdimm in bios -> minimum dram voltage in hwmonitor = 1.544v
tRCDRD 13 fails with lots error 6 after 2-3 seconds at these settings


----------



## MrHoof

I am trying to drop DrvStr settings atm this was with 1.555VDIMM gonna try 1.56v tomorrow, didnt think i would get that far at those low settings.


----------



## o1dschoo1

Got these ram clocks on a 1700x. Gonna see how far i can push tomorrow. https://valid.x86.fr/2y72mn


----------



## craxton

looks like in my time away ive missed some stuff.... 
quite alot actually... just wanted to drop in and give a hey to those 
who for sure didn miss me none  
been doing some cool ass shiz like well, changing the way this horrific city looks for one. and getting the new place set up finally...(if you look at the big coke sign at the atlanta braves
field we did that too) an arse load of CNC routing, lightburn, and what have you came 
into play...if anyone has something theyd like lit up hmu...
















(not an ad just glad to be back and show one of the 40 dope signs i built)
sorry its pretty far off topic as well.


----------



## Skull_Angel

umeng2002 said:


> Has anyone ran into RAM cooling issues?
> 
> My 4x8GB Samsung B-die keeps failing Karhu at like around 2000% coverage at different speeds, timings, and VDDG voltages. On my old motherboard, these timings passed Karhu to at least 10,000% coverage. The only thing different between them besides the motherboard is the amount of cooling fans I have installed (less in the new system).
> 
> I'm running just 1.38 to 1.4 v on the RAM.


Depends on a lot of factors (binning, die revision, pcb, heat dissapation, timings), but some B-die kits do have a very low tolerance for heat when you put the screws to them. I've posted in this thread about issues I've been having running lower than flat 16 @ 3800, my set just gets too unstable with tighter primary timings >42C. I can drop the secondaries and tertiaries low enough to compensate a little, which also adds heat, however they've been showing solid stability >42C at least.

Try using TestMem5 (TM5) with 1usmus v3 preset and using the error descriptions here to diagnose what may be happening. If you're error free for the first 3~4 cycles and then start getting random (non-consistent) errors, it _may_ be due to temperature related instability.


----------



## umeng2002

That’s the thing, I did 1usmus’ preset and it passed, just not in Karhu past about 2000 to 2500


----------



## Dodgexander

From the gift


mongoled said:


> Good analogy, just the "bar tenders" are the customers of the bar and most of them are just interested in getting drunk
> 
> 😂 😂


Haha I don't want to sound demanding but it's true. About 90% is someone like me asking what to do. 10% is people helping..I don't blame them since I cannot really help much myself.

It's a bit like everyone driving their broken cars to the repair shop when there's only a few mechanics to help 

Best advice I can give is just keep trying as many variables as you can to find the sweet spot. Sometimes it feels fruitless but once you find that initial stability that's when it starts to become fun.

A lot of results here in the thread will claim to be stable when not. Do not make my mistake and test test test long with many tests before you waste time later on.

Also do not try to learn advanced settings so much. They often make no sense and follow different patterns unit to unit. Trial and error is the only way!

Regarding temps this is from the GitHub guide:
The tRFC timings are very dependent on temperatures, as they are related to capacitor leakage which is affected by temperature. Higher temperatures will need higher tRFC values. tRFC2 and tRFC4 are timings that activate when operating temperature of DRAM hits 85°C. Below these temperatures, these timings don't do anything.
B-Die is temperature sensitive and its ideal range is ~30-40°C. Some may be able to withstand higher temperatures so YMMV.

Maybe you are getting unstable far into test because ram is getting too hot even at low voltage? It's hard to know without sensors on ram.


----------



## Audioboxer

domdtxdissar said:


> Working on a other timing set
> (was running tRC*7 before)
> View attachment 2526979
> 
> 
> Still running 1.550 vdimm in bios -> minimum dram voltage in hwmonitor = 1.544v
> tRCDRD 13 fails with lots error 6 after 2-3 seconds at these settings


lol, we're almost identical now










I guess I should try CmdSetup 55 just to go the whole way 

Have you tested if your VSOC can come down? I wouldn't be surprised if it can be dropped a notch or two.

*edit *- On the calculator this is more like what I should be running










Based on the formula a tRFC of 228 is acceptable for a tRC of 35. Will test properly later.










Oooft, my lowest ever bench


----------



## LxT1N

i habe a question i will try my tRFC on 288 need to put then tRFC 288 tRFC2 250 tRFC4 154 ? i have used tRFC mini it this right?


----------



## umea

umeng2002 said:


> Has anyone ran into RAM cooling issues?
> 
> My 4x8GB Samsung B-die keeps failing Karhu at like around 2000% coverage at different speeds, timings, and VDDG voltages. On my old motherboard, these timings passed Karhu to at least 10,000% coverage. The only thing different between them besides the motherboard is the amount of cooling fans I have installed (less in the new system).
> 
> I'm running just 1.38 to 1.4 v on the RAM.


most of us are running active cooling, whether in the form of a fan running on the ram at all times or liquid cooling.


----------



## Veii

Luggage said:


> Quick Q though: edc700 pulls less power ?!?


y-cruncher close to always triggers PROCHOT for me
It doesn't get to the point where FIT-PRE is a limiter
But also AVX2 tests have a fixed vdroop
Sounds to me like thermal limit comes later than voltage limit
When voltage limit is gone, thermal limit is the first throttle before voltage limit can be reached.
But scalar if on auto, can change it's range behaviour at any time
Edit:
Or cores switch to a lower strap, as vdroop by AVX2 + loadline droop was too strong
Hence "lower current draw"
Can't say about other users systems, without having it infont of me
Only know how it behaves for me and systems I've seen


Audioboxer said:


> 3800 flat 14? NOPE! 4000 flat 14 here we come! 🤣


Possible but needs near that 1.6v


Dodgexander said:


> Below these temperatures, these timings don't do anything.


This is sadly not the whole story and 2018 conclusion
It is not actively used, but is used
Also i might be wrong about "not actively" hence IMC FW changed so also tFAW, tMAC.tMAW, tMRD behavior and logically also tRFC2/4
Unsure here ~ but in general, this quote is more of an excuse than telling the whole story *
Same way as "tCKE doesnt do anything without PDM enabled"
Both half-true and doesn't tell the whole story.

Edit:
* i can't be sure about thermal limit throttle, as before that CPU ECC does package throttle and autocorrect
Unsure if thermal limit above 50c is triggered, and unsure how the current range is
But very sure that they are used and factored in
Unsure how active, at this point of time hence UNLIMITED tMAC.tMAW seems to be used, and not ? calculated unless user enforced

Too early agesa , to tell hidden settings behaviour
But fully changed since 1.1.8.X
Well also on matisse and earlier
Conclusion about tRFC2 was made based on one scenario not being met
Ignoring it actively changes tMRD decision, and should change tPHY decision
Also ignoring that what you see are "fixed" timings, and tMRD behavior changes in realtime up to suited need
DRAM is dynamic not in a single state
GDDR is not much different
~ except for quad or octa data-rate

@Danny.ns BLCK boost stop, is a bug with c-states
It does keep boost for me, till 102.75
102.85 does but out to 97.85, which is also a bug 
But precision boost, never bugged ot
It only bugs out if you disable LCLK DPM
Then THM & cTDP bugs out
Sadly ProcHOT hardthrottle nonsense still remains active


----------



## Audioboxer

Veii said:


> Possible but needs near that 1.6v


Not a problem 

My actual problem at the moment is USB issues with 2000 FCLK. y-cruncher test 17, HNTT is the quickest way to bring them out. Will have to see if I can fix them first before even thinking about memory at 4000.


----------



## Veii

Audioboxer said:


> What I struggle to understand and anyone can chime in, if something does appear stable at 2000 FCLK because it passes all stress tests and benches, what's the deal with AMD not being able to stop the WHEA spam? In their eyes is it not actually stable?


I don't want to say "AMD doesn't see the needle infront of all tree's (sensors)"
But i come to the same conclusion
The other one is an anti-consumer move, soo i doubt it's that 
Its a sensor that dual CCD bug units dont have enabled
A function for powermanagement, which bugs out
Hence the same WHEA 19 is stable on an MSI board with 2.5gbit realtek lan
(Another dual CCD 6 core with the same binning as mine, same factory even)

Lan issues, while being a potential still maybe unfixed issue
And maybe hidden under the WHEA #19 spam, if 10/10 sensors are active
Is not the main reason
That's current conclusion & progress of the research

If i get a functioning 6 core and later have the 5950X to play with
I can see what is different
If i get it figured out, you'll have a tool to override the ryzens
That is, if i get the access to required RSMU tools and the usage documention ~ without an NDA
Or learn PSP-FW better.
We'll see, if i figure it out ~ i'll share, soo x dev can get the applause for it
Might share it to Yuri , as thats the closest dev friend so far with the knowledge
Other friends are too busy


----------



## Audioboxer

Veii said:


> I don't want to say "AMD doesn't see the needle infront of all tree's (sensors)"
> But i come to the same conclusion
> The other one is an anti-consumer move, soo i doubt it's that
> Its a sensor that dual CCD bug units dont have enabled
> A function for powermanagement, which bugs out
> Hence the same WHEA 19 is stable on an MSI board with 2.5gbit realtek lan
> 
> Lan issues, while being a potential still maybe unfixed issue
> And maybe hidden under the WHEA #19 spam, if 10/10 sensors are active
> Is not the main reason
> That's current conclusion & progress of the research
> 
> If i get a function 6 core and later have the 5950X to play with
> I can see what is different
> If i get it figured out, you'll have a tool to override the ryzens
> That is, if i get the access to required RSMU tools and the support
> Or learn PSP-FW better.
> We'll see, it i figure it out ~ i'll share, soo x dev can get the applause for it
> Might share it to Yuri , as thats the closest dev friend so far with the knowledge
> Other friends are too busy


Does this mean if I disable LAN it _could_ help? Believe it or not I'm using WiFi with the included MSI antenna as I've got a Mesh WiFi network setup around my home and WiFi maxes out perfectly fine.


----------



## domdtxdissar

Audioboxer said:


> lol, we're almost identical now
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I guess I should try CmdSetup 55 just to go the whole way
> 
> Have you tested if your VSOC can come down? I wouldn't be surprised if it can be dropped a notch or two.
> 
> *edit *- On the calculator this is more like what I should be running
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Based on the formula a tRFC of 228 is acceptable for a tRC of 35. Will test properly later.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Oooft, my lowest ever bench


I actually started a Testmem with exactingly those timings before i went to work today  
The dram calc bench time is also very good 

Pretty sure this/those is will be final settings as my cpu/motherboard cant do above 1933 without reduced performance (even with the silencer turned on)


----------



## Mach3.2

Audioboxer said:


> Does this mean if I disable LAN it _could_ help? Believe it or not I'm using WiFi with the included MSI antenna as I've got a Mesh WiFi network setup around my home and WiFi maxes out perfectly fine.


Doubt so. I had mine disabled since I'm using an Intel I350 NIC, but I still get WHEA 19 spam at 1933MHz FCLK.


----------



## Veii

Audioboxer said:


> Does this mean if I disable LAN it _could_ help? Believe it or not I'm using WiFi with the included MSI antenna as I've got a Mesh WiFi network setup around my home and WiFi maxes out perfectly fine.


Unless you have 10/10 sensors active, and not 9/10
It could help. But i think thats a clear no
the remain #19 issues are connected to the PCH

But it's concluded to be a sideproduct , same as USB dropouts
The main issue maker is a sensor inside the ryzens
One for DPM / Link-Powermanagement which us bugged and not functioning on dual CCD bugged units
Hence we get no #19 and very very rarely #18

There are too many sensors, and it needs close inspection
Some people have access to all the resources, but their helping ~public sharing~ ability is restricted
If you want a tool for a permanent override/fix, it needs to be from someone who has no NDA
Complicated 

AMD could fix it at any time, but i feel they have no clue
It's a hardware "issue" but technically something they can fix and disable
Well "fix" likely with Zen3D , but FW-Fix for sure, if they would ever want
its already good progress, that we got AMD to lift this 56.34 Patch-C ABL FCLK lock
This was very valuable and good progress.
i think @Dodgexander quoted me on that part (message 8 months ago)
Gladly the "lock" was just an AGESA-BOOTLOADER (ABL) and not a permanent PSP-FW one ~ like feared to be 😅
Because if they would want to be anti-consumer, this is the way to shy away all the memory overclockers and ryzen users, away from AMD. A very effective method, locking it down like it still? is for Matisse (just to make PCIe 4.0 more stable)

EDIT:
Also no, it should be fixed
But disabling wont prevenr thr bios from loading the buggy DXE module
But this i think slowly should be fixed now


----------



## Audioboxer

Veii said:


> Unless you have 10/10 sensors active, and not 9/10
> It could help. But i think thats a clear no
> the remain #19 issues are connected to the PCH
> 
> But it's concluded to be a sideproduct , same as USB dropouts
> The main issue maker is a sensor inside the ryzens
> One for DPM / Link-Powermanagement which us bugged and not functioning on dual CCD bugged units
> Hence we get no #19 and very very rarely #18
> 
> There are too many sensors, and it needs close inspection
> Some people have access to all the resources, but their helping ~public sharing~ ability is restricted
> If you want a tool for a permanent override/fix, it needs to be from someone who has no NDA
> Complicated
> 
> AMD could fix it at any time, but i feel they have no clue
> It's a hardware "issue" but technically something they can fix and disable
> Well "fix" likely with Zen3D , but FW-Fix for sure, if they would ever want
> its already good progress, that we got AMD to lift this 56.34 Patch-C ABL FCLK lock
> This was very valuable and good progress.
> i think @Dodgexander quoted me on that part (message 8 months ago)
> Gladly the "lock" was just an AGESA-BOOTLOADER (ABL) and not a permanent PSP-FW one ~ like feared to be 😅
> Because if they would want to be anti-consumer, this is the way to shy away all the memory overclockers and ryzen users, away from AMD. A very effective method, locking it down like it still? is for Matisse (just to make PCIe 4.0 more stable)
> 
> EDIT:
> Also no, it should be fixed
> But disabling wont prevenr thr bios from loading the buggy DXE module
> But this i think slowly should be fixed now


Sounds like AMD being the baddies here then 

I guess this goes a long way to explain why 1900 is rock stable, but even just going to 1933 and it's a WHEA party. Almost seems like AMD are artificially capping OCing potential where they want to either due to incompetence or on purpose, for whatever reasons.

It will be interesting to see if Zen 3D _magically _stops the unnecessary WHEA.


----------



## lunatik

Audioboxer said:


> The calculator does seem pretty sensible so I take back my earlier worries about what it was. Will just keep an eye on memory and benching when operating outside of potentially expected parameters.
> 
> Going to have a look at IF 2000 over the next few days so that will be WHEA suppression and trying to run stability tests and find out if they can pass. XMP settings to start with I guess, given I'm binned for 4000.
> 
> Any rough tips for me on voltage expectations for 2000 FCLK? More so, so I don't boot anything stupid and destroy Windows. I think I've seen VSOC will need to be nearer 1.2v. VDDP changes?


Hi, i'm far from home, so can't really post a picture..
I'm running @ 4000mhz with 5600x, stable ram and y-cruncher (no wheas)
1.2 vsoc 
1.09 ccd 
1.1 iod 
1 vddp 
I think it was 1.48V flat 16 with 51.3-51.4 latency (ripjaws 4000c17 dr) 
(Also if i decrease ccd to 1.06 for example, i will get wheas and instant crash on y-cruncher..)
Hope it helps someone 😀


----------



## Audioboxer

lunatik said:


> Hi, i'm far from home, so can't really post a picture..
> I'm running @ 4000mhz with 5600x, stable ram and y-cruncher (no wheas)
> 1.2 vsoc
> 1.09 ccd
> 1.1 iod
> 1 vddp
> I think it was 1.48V flat 16 with 51.3-51.4 latency (ripjaws 4000c17 dr)
> (Also if i decrease ccd to 1.06 for example, i will get wheas and instant crash on y-cruncher..)
> Hope it helps someone 😀


No matter what I do I get WHEA above 1900. At certain voltages it does reduce the spam, but it never totally stops. Veii made it sound like dual CCD chips have a harder time of it above, which I guess maybe explains why your 5600x could be a golden chip that is fine above 1900 with WHEA.

The funny thing is I can go right down to 0.925v on CCD AND IOD at 1900 and no WHEA. But that serves little purpose and I believe it hurts my peformance. The interesting point is just no WHEA even that low.


----------



## Mach3.2

Veii said:


> Unless you have 10/10 sensors active, and not 9/10
> It could help. But i think thats a clear no
> the remain #19 issues are connected to the PCH


I only have 5 active WHEA error sources, I suppose the number of active WHEA error sources could be BIOS and motherboard dependant?


----------



## umea

Audioboxer said:


> No matter what I do I get WHEA above 1900. At certain voltages it does reduce the spam, but it never totally stops. Veii made it sound like dual CCD chips have a harder time of it above, which I guess maybe explains why your 5600x could be a golden chip that is fine above 1900 with WHEA.
> 
> The funny thing is I can go right down to 0.925v on CCD AND IOD at 1900 and no WHEA. But that serves little purpose and I believe it hurts my peformance. The interesting point is just no WHEA even that low.


if you want to find what voltages work best for your chip, give latencymon a shot and see what gives the lowest spikes/avg on DPC/interrupt to process latency. can do with or without running y cruncher


----------



## Veii

Audioboxer said:


> Sounds like AMD being the baddies here then
> 
> I guess this goes a long way to explain why 1900 is rock stable, but even just going to 1933 and it's a WHEA party. Almost seems like AMD are artificially capping OCing potential where they want to either due to incompetence or on purpose, for whatever reasons.
> 
> It will be interesting to see if Zen 3D _magically _stops the unnecessary WHEA.


I wouldn't trow them into the anti-consumer bin, yet
Currently i think, they are just clueless about the issue
And it by pure accident ended up "fixed" one some units

Like i accidentally wiped my ethernet rom chip, disabled that way one tracking sensor and have no problems beyond 2033
I-225V here is problematic Rev.02 not fixed Rev.03 like on the ProArt
(in progress trying to figure out if brands do not care which NIC revision they put on, or it depends on manufacturing date)
All is a bit of a clown fiesta, but going to reddit with it, could draw attention to an unfinished conclusion ~ people making up stuff and blaming companies wrongly 🙄

We'll see,
I try to get couple Zen3D's
Couple of people's builds are on a waiting line. But batch will be extremely tight ~ again
Pandemic defined working issues, do not do anything good for already lacking shortages and higher metal prices
(Hopefully won't earn a title as scalper, heh ~ but i feel, we'll have again for 3 months no supply & people will buy up all the cheap 5000 series)



Mach3.2 said:


> I only have 5 active WHEA error sources, I suppose the number of active WHEA error sources could be BIOS and motherboard dependant?
> View attachment 2527059


I had 4/5 active at first
Swapped to the ProArt & it went up to 9/10
Soo a FW thing.
You have 4/10, soo maybe something else is blocking windows error reports for you
Maybe a tweaked windows


----------



## Audioboxer

Veii said:


> I wouldn't trow them into the anti-consumer bin, yet
> Currently i think, they are just clueless about the issue
> And it by pure accident ended up "fixed" one some units
> 
> Like i accidentally wiped my ethernet rom chip, disabled that way one tracking sensor and have no problems beyond 2033
> I-225V here is problematic Rev.02 not fixed Rev.03 like on the ProArt
> (in progress trying to figure out if brands do not care which NIC revision they put on, or it depends on manufacturing date)
> All is a bit of a clown fiesta, but going to reddit with it, could draw attention to an unfinished conclusion ~ people making up stuff and blaming companies wrongly 🙄
> 
> We'll see,
> I try to get couple Zen3D's
> Couple of people's builds are on a waiting line. But batch will be extremely tight ~ again
> Pandemic defined working issues, do not do anything good for already lacking shortages and higher metal prices
> (Hopefully won't earn a title as scalper, heh ~ but i feel, we'll have again for 3 months no supply & people will buy up all the cheap 5000 series)
> 
> 
> I had 4/5 active at first
> Swapped to the ProArt & it went up to 9/10
> Soo a FW thing.
> You have 4/10, soo maybe something else is blocking windows error reports for you
> Maybe a tweaked windows


I might need to try something other than IF 2000 then, just to see if I have any luck. I know I can boot 2033/2066.

Reason being is I can't seem to shift my USB issues at 2000. Even at 1.15v on IOD. Run a stability test and USB goes crazy. I don't think it will damage any peripherals, but it is a bit worrying watching everything disconnect/reconnect rapidly. Plus, it's annoying every time my iCUE profile gets wiped lol.


----------



## Mach3.2

Veii said:


> I had 4/5 active at first
> Swapped to the ProArt & it went up to 9/10
> Soo a FW thing.
> You have 4/10, soo maybe something else is blocking windows error reports for you
> Maybe a tweaked windows


Now I'm confused, how did you count 4/10 active sources. 😅


Anyway my daily driver Windows install shouldn't be modded since I didn't run any clean up/debloat script on it. Could be motherboard/BIOS.


----------



## Veii

Audioboxer said:


> I might need to try something other than IF 2000 then, just to see if I have any luck. I know I can boot 2033/2066.


2133 for me
But its too hard to get stable
I mean Package Throttle keeps it stable and all
But the result is not satisfying enough

Try higher than 2066, ignore whea 19 spam 
Worry about the 18's


----------



## Veii

Mach3.2 said:


> Now I'm confused, how did you count 4/10 active sources. 😅
> 
> 
> Anyway my daily driver Windows install shouldn't be modded since I didn't run any clean up/debloat script on it. Could be motherboard/BIOS.


My bad, 5/10 
Sorry
What you can do, is enforce a PSP-FW upgrade my upgrading the board to Patch-C
Removing the CPU, cmos discharging it
Enabling power without the cpu (PSU)
And later removing ram, putting CPU in, and turning PSU on

That should be detected as "CPU got swapped"
And has to dual/tripple reboot, and make a FW upgrade

If you don't have hardware flashback abilities, use AFUWIN
But do not use AFUWIN bellow 1.1.8.1 or 1.2.0.0
This AGESA 1.2.0.0 jump, changes a lot of things and AFUWIN will brick the board
Same as flashrom will
Later from 1.2.0.0 , you can use AFUWIN again

A PSP-FW update, will only happen, if the AGESA jumps are too big
Or you change board's 
Not every AGESA push, has a PSP-FW blob with it

For an update/reflash to happen between boards, it also needs to missmatch the AGESA FW
Be it from a new to 1 year old version, or just a newer one, where it detects it as "CPU swapped/new CPU inserted"

Its common that voltage behaviour from current AGESA's, translates down to old AGESA's
But sadly also common, that memOC can brick PSP-FW and the cpu won't boot at all anymore, till you reset it on another board or another chipset


----------



## duarte36

hello, inside of whea errors , i stopped trying overclock ram because the only whea i see is event id 20 ^^ .. i can't find alot of information about . and due to some health problems by now , i don't have alot of time to play with.
anyone know that whea error?
thank you
dark hero / 5900x / gskill 4000 cl14 .


----------



## Netarangi

umea said:


> if you want to find what voltages work best for your chip, give latencymon a shot and see what gives the lowest spikes/avg on DPC/interrupt to process latency. can do with or without running y cruncher


I had no idea you could use latencymon for this.

What voltages are you talking about? Ccd vddp etc?


----------



## umea

Netarangi said:


> I had no idea you could use latencymon for this.
> 
> What voltages are you talking about? Ccd vddp etc?


yes, read from halfway down and further to understand the process.


----------



## Bix

umea said:


> if you want to find what voltages work best for your chip, give latencymon a shot and see what gives the lowest spikes/avg on DPC/interrupt to process latency. can do with or without running y cruncher


Any advice as to how best to use LatencyMon? I've been running it for 5mins at a time and comparing for each set of voltage settings.

Thought things were looking good with the above settings but TM5 threw 2 errors during the last 2 cycles - is this due to FCLK being unstable or a problem with the timings? I've been using XMP with frequency brought down to 4000 in the hope that that would eliminate RAM errors from the mix but maybe it hasn't!


----------



## Bix

umea said:


> yes, read from halfway down and further to understand the process.


You beat me to it, thanks!


----------



## Audioboxer

Bix said:


> View attachment 2527080
> 
> 
> 
> 
> Any advice as to how best to use LatencyMon? I've been running it for 5mins at a time and comparing for each set of voltage settings.
> 
> Thought things were looking good with the above settings but TM5 threw 2 errors during the last 2 cycles - is this due to FCLK being unstable or a problem with the timings? I've been using XMP with frequency brought down to 4000 in the hope that that would eliminate RAM errors from the mix but maybe it hasn't!


Try OCCT CPU test. y-cruncher would keep running for me even during my USB connections going mental. OCCT actually brought up a WHEA error on the CPU test.










I ran the large dataset.

I did subsequently manage to get OCCT to stop that error by increasing voltages, but at FCLK 2000, so far, I haven't been able to stop my USB issues.

Given what your memory is rated for if you run it on XMP/auto and just set the frequency to 4000, it should be passing OK. I would focus on trying to figure out if your CPU is also failing at the IF level.


----------



## Dodgexander

Veii said:


> i think @Dodgexander quoted me on that part (message 8 months ago)


I did, but does what you say about 40mv stepping's still exist, or was this older versions?


----------



## Taraquin

Sooo, after some tweaking and patience I got my 4000cl16 1T setup stable*, but running TM5 I get one error 15 at round 17 to 20 :/ I tried changing RRDL to 6, same happened. I tried 60-20-40-24 and 63 setup times, that seemed stable in TM5, but got me my first WHEA 19 since agesa 1.1.0.0 in May and a reboot during aida. Compared to the same settings and GDM I had to raise voltage by 0.04V and change drv str from 24-20-24-24. 2T worked at 1.45V. In dram calc GDM gave me 101 sec, 2T 99.9 and the current setup 98.9. Raising voltage to 1.5V gives the overheat and PCB crash error. Maybe 1.49V could work, but the error don`t seem voltage related. 1.47V gives me one single error 0 or 2 around round 10. Any tips on getting rid of that error 15?


----------



## Audioboxer

Taraquin said:


> Sooo, after some tweaking and patience I got my 4000cl16 1T setup stable*, but running TM5 I get one error 15 at round 17 to 20 :/ I tried changing RRDL to 6, same happened. I tried 60-20-40-24 and 63 setup times, that seemed stable in TM5, but got me my first WHEA 19 since agesa 1.1.0.0 in May and a reboot during aida. Compared to the same settings and GDM I had to raise voltage by 0.04V and change drv str from 24-20-24-24. 2T worked at 1.45V. In dram calc GDM gave me 101 sec, 2T 99.9 and the current setup 98.9. Raising voltage to 1.5V gives the overheat and PCB crash error. Maybe 1.49V could work, but the error don`t seem voltage related. 1.47V gives me one single error 0 or 2 around round 10. Any tips on getting rid of that error 15?
> View attachment 2527098


TM5 error 15 for me has always come down to tRFC. Either too low at the voltage selected or a heat issue where your memory doesn't like the temp it gets to with the tRFC you are running.

Are you active cooling?


----------



## Taraquin

Audioboxer said:


> TM5 error 15 for me has always come down to tRFC. Either too low at the voltage selected or a heat issue where your memory doesn't like the temp it gets to with the tRFC you are running.
> 
> Are you active cooling?


No, not direct to ram and it is close between dimms due to 2 slots. Intake fan blows on one. I tried higher tRFC but got same error then :/


----------



## Audioboxer

Taraquin said:


> No, not direct to ram and it is close between dimms due to 2 slots. Intake fan blows on one. I tried higher tRFC but got same error then :/












It can be a few things, I should have been clearer when I've got error 15 its been about tRFC. Some more for you to check.

VDIMM and/or tRFC is probably just a common reason for 15.


----------



## Bix

Audioboxer said:


> Try OCCT CPU test. y-cruncher would keep running for me even during my USB connections going mental. OCCT actually brought up a WHEA error on the CPU test.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I ran the large dataset.
> 
> I did subsequently manage to get OCCT to stop that error by increasing voltages, but at FCLK 2000, so far, I haven't been able to stop my USB issues.
> 
> Given what your memory is rated for if you run it on XMP/auto and just set the frequency to 4000, it should be passing OK. I would focus on trying to figure out if your CPU is also failing at the IF level.


Thanks for that, will go back to the voltage drawing board with OCCT added to the list. Feel like I'm banging my head against a wall trying to stabilise FCLK 2000 but can post 2100+ so definitely feel like it's do-able...


----------



## Audioboxer

Bix said:


> Thanks for that, will go back to the voltage drawing board with OCCT added to the list. Feel like I'm banging my head against a wall trying to stabilise FCLK 2000 but can post 2100+ so definitely feel like it's do-able...


Funnily enough I'm having a nightmare at FCLK 2000 with USB issues and Veii said I should give 2100+ a go instead. Seems counterproductive to go higher for stability but given the craziness of these Ryzen chips and infintity fabric, including the holes, it might just work! Looser memory timings needed obviously but the uplift in memory frequency should still result in more performance if higher than 2100 gets stabilised.


----------



## Taraquin

Audioboxer said:


> It can be a few things, I should have been clearer when I've got error 15 its been about tRFC. Some more for you to check.
> 
> VDIMM and/or tRFC is probably just a common reason for 15.


Yeah I saw that and tried loosening both tRFC and RRDL first but same error close to round 20. If it's due to tRFC and temp I don't think it's fixable atm :/ Gotta consider fan above ram.


----------



## LxT1N

LxT1N said:


> View attachment 2527046
> i habe a question i will try my tRFC on 288 need to put then tRFC 288 tRFC2 250 tRFC4 154 ? i have used tRFC mini it this right?


any help?


----------



## KedarWolf

This passed OCCT WHEA free and my custom cfg of 1usmus_v3_1000%x8.

Attached is the .cfg, just rename it and remove the .txt at the end.

This .cfg will find errors 25 cycles of TM5 at 100% may miss. Run it overnight as you sleep.


----------



## sonixmon

LxT1N said:


> View attachment 2526572
> View attachment 2526573
> 
> 
> what i can changed here? to get low latency??


GDM off, AddrCmdSetup 56 might be worth a try. You might have to tweak settings though because GDM On is changing some of your timings without you knowing it!


----------



## Veii

Dodgexander said:


> I did, but does what you say about 40mv stepping's still exist, or was this older versions?


Haven't seen much changes on VDDG
dLDO_injector has no to me known connection, with VDDG
VDDG on it's own does continue to balance itself, yet sadly without much public information about
"by how much/in which range/does it interpolate/is it still active after UncoreOC mode combined flag"
about it
It's pretty unclear , soo i still see both as one line, just with separated control ability

Either it remains one line & "control" is a visual "lie"
Or they are fully independent split
I rather think it's the first one, but you only controlling the distance about it. Like the minimum drop (i think)

It's especially interesting, as VDDG_CCD can match cLDO_VDDP
And even drop bellow it, as long as IOD is higher, soo VDDG'avg remains higher

I've studied it's behaviour the first couple months before writing the AMD OVERCLOCKING post
2033 took 1-2 weeks of fooling to get functioning, while playing with offsets inside AMDs predefined launch limits and voltages. Fully blind
2067 took then 1-2 months to stabilize fully without random throttle or issues
* mind you i never had usb dropouts, ever | they only came after AMD started to roll out a handful of patches, where every brand after Patch-D used an unknown number of them. Every board and bios compile date had different patches between 1.1.8.X-1.2.0.3A & A+/++
** i had audio crackling issues, but only soft. There was never WHEA #19 , only once. It was either stable or catastrophic failure & crash

2100 took i think 3-4 months after it
More than double the time, as memory was/is also quite maxed
Strain on 2:1 mode strongly differs, to 1:1 mode. Signal quality differs too, big times
CPU VDDP was the key word, but not only. A combination of voltages and distances

Soo for your question,
Yes it matters, as the absolute minimum value
SOC can be overshooting and excessive
But cLDO_VDDP, VDDG, 1.8(3)v rail, 2.5(2.45v) PROM
ProcODT (soo also memory RTTs)
~ all play a big factor in maximum FCLK

2133 was reachable March
2100 should have been rock stable at 50.1ns (16-16-16) near February/March
2100 current 15-15-15 was set couple of months ago & and since then, its public resource silence
* I'm still working on it, but it's not good enough so far

Latest updates, compared to early SMU 56.30 (Patch-A) did pretty much nothing as for memoryOC or FCLK
~ even if advertised differently
AMD put an FCLK hardlock first. Removed it by a community push & advertised untrueness about negative Curve Optimizer and new 2000 FCLK limits, just soo user update to these 1.1.8.X/1.2.0.0 AGESA with SPI Armor, and Spectre.v5 patches
* full curve optimizer and ResBAR existed since 1.1.0.0A, the filly open one ~ just without cache overdrive feature & dLDO support

Well it gave an cache boost and IPC boost
But broke their great idle efficiency, as DF-C(6) States are still broken since half a year so far
Also took away our +500mhz boost override ability.
Soo much about "for the user, for performance" 😐

They did a lot anti consumer unreleased in changelogs,
But yet i can not blame them from a business standpoint
Platform stability has higher priority, than enthusiast satisfaction
* even when perf takes a bit hit, but equals out by the IPC gains
Just there are soo many things which move backwards

Open-Source "for the consumer", and yet couldn't be more restrictive in platform information sharing, platform openness and developer support
Its just sad, nothing else really. The community on/for AMD is huge, but the treatment to us is very undesirable
It was common industry practice, but this restrictive NDA cr*p has to change & the marketing lies without telling users that there is a big security risk and they have to update, even with couple of negatives & issues along the way
Big lack of transparency by AMD is very undesirable current reality


----------



## Veii

Audioboxer said:


> Funnily enough I'm having a nightmare at FCLK 2000 with USB issues and Veii said I should give 2100+ a go instead. Seems counterproductive to go higher for stability but given the craziness of these Ryzen chips and infinity fabric, including the holes, it might just work!


I didn't say exactly such
But,
You can try to push it and start to fight against package throttle issues
This will help you finding correct voltages for your chip, even when they will be too high for for example 1900 FCLK

I got mine, and have no reason to trow them away even at 1800 FCLK timings push
They just work, soo why not 
Cut into powermanagement budget deeply, but it is what it is
~not like AMD wants to finally tackle their overboost mess on waking up hard suspended cores ~ anytime soon (DF_C-States)

Mind , you will need different tCKE and Setup Timings, for a different MCLK
Might want to stabilize memory first async
1900 FCLK, 2067 MCLK or even 2100 MCLK ~ to figure out value scaling (or checking tRFC mini shenanigans sheet)
RTTs need to be only set on full strain 1:1 mode


----------



## Dodgexander

Veii said:


> Haven't seen much changes on VDDG
> dLDO_injector has no to me known connection, with VDDG
> VDDG on it's own does continue to balance itself, yet sadly without much public information about
> "by how much/in which range/does it interpolate/is it still active after UncoreOC mode combined flag"
> about it
> It's pretty unclear , soo i still see both as one line, just with separated control ability
> 
> Either it remains one line & "control" is a visual "lie"
> Or they are fully independent split
> I rather think it's the first one, but you only controlling the distance about it. Like the minimum drop (i think)
> 
> It's especially interesting, as VDDG_CCD can match cLDO_VDDP
> And even drop bellow it, as long as IOD is higher, soo VDDG'avg remains higher
> 
> I've studied it's behaviour the first couple months before writing the AMD OVERCLOCKING post
> 2033 took 1-2 weeks of fooling to get functioning, while playing with offsets inside AMDs predefined launch limits and voltages. Fully blind
> 2067 took then 1-2 months to stabilize fully without random throttle or issues
> * mind you i never had usb dropouts, ever | they only came after AMD started to roll out a handful of patches, where every brand after Patch-D used an unknown number of them. Every board and bios compile date had different patches between 1.1.8.X-1.2.0.3A & A+/++
> ** i had audio crackling issues, but only soft. There was never WHEA #19 , only once. It was either stable or catastrophic failure & crash
> 
> 2100 took i think 3-4 months after it
> More than double the time, as memory was/is also quite maxed
> Strain on 2:1 mode strongly differs, to 1:1 mode. Signal quality differs too, big times
> CPU VDDP was the key word, but not only. A combination of voltages and distances
> 
> Soo for your question,
> Yes it matters, as the absolute minimum value
> SOC can be overshooting and excessive
> But cLDO_VDDP, VDDG, 1.8(3)v rail, 2.5(2.45v) PROM
> ProcODT (soo also memory RTTs)
> ~ all play a big factor in maximum FCLK
> 
> 2133 was reachable March
> 2100 should have been rock stable at 50.1ns (16-16-16) near February/March
> 2100 current 15-15-15 was set couple of months ago & and since then, its public resource silence
> * I'm still working on it, but it's not good enough so far
> 
> Latest updates, compared to early SMU 56.30 (Patch-A) did pretty much nothing as for memoryOC or FCLK
> ~ even if advertised differently
> AMD put an FCLK hardlock first. Removed it by a community push & advertised untrueness about negative Curve Optimizer and new 2000 FCLK limits, just soo user update to these 1.1.8.X/1.2.0.0 AGESA with SPI Armor, and Spectre.v5 patches
> * full curve optimizer and ResBAR existed since 1.1.0.0A, the filly open one ~ just without cache overdrive feature & dLDO support
> 
> Well it gave an cache boost and IPC boost
> But broke their great idle efficiency, as DF-C(6) States are still broken since half a year so far
> Also took away our +500mhz boost override ability.
> Soo much about "for the user, for performance" 😐
> 
> They did a lot anti consumer unreleased in changelogs,
> But yet i can not blame them from a business standpoint
> Platform stability has higher priority, than enthusiast satisfaction
> * even when perf takes a bit hit, but equals out by the IPC gains
> Just there are soo many things which move backwards
> 
> Open-Source "for the consumer", and yet couldn't be more restrictive in platform information sharing, platform openness and developer support
> Its just sad, nothing else really. The community on/for AMD is huge, but the treatment to us is very undesirable
> It was common industry practice, but this restrictive NDA cr*p has to change & the marketing lies without telling users that there is a big security risk and they have to update, even with couple of negatives & issues along the way
> Big lack of transparency by AMD is very undesirable current reality


I think this says a lot. Many people are looking for an easy time getting high FCLK but in reality, it takes a lot of time, even for someone like you.
If I would have known from the start it would be this hard, I probably would have just bought 3600 CL14 ram and be done with it, but AMD teased us with 2000 FCLK in pre-release media. Investment of more time for me is not possible, I have already spent almost a month trying to get stable at 1900 on my 5800X, and I don't think I'll bother to tweak further until we know more about where the WHEA fiasco ends. I think the time these things take is often not documented by people. It makes achievements look easy, but to someone who is learning from new I think it should be made more clear in guides that sometimes you can spend months before you are fully stable if you want high FCLK.


----------



## Audioboxer

This is probably my finalised profile. Might try CsOdtDrvStr down to 20.


----------



## domdtxdissar

tRFC 228 put up a really good fight with me, but in the end i have managed to knock it back in line

Had multiple runs where testmem simply would stop running without giving any errors, with timer still running, often at cycles between 15 and 24 🤬
What fixed it in the end was higher voltages.. +20mv to VDDP, CCD and IOD fixed testmem from stop running between cycles

I'm pretty sure this is also my finalised profile for awhile now.. 
We have the exact same settings now *Audioboxer 🤣*










Lots of things going on in this screen, so i will also write what it show:

25 cycles testmem 1usmus cfg
3000% Karhu ramtest
30min OCCT Large AVX
Aida64 memory benchmark with fantasy numbers
CPU-Z cpu bench, ST 709 and MT above 14k

Quick and easy gaming test in SotTR with daily 24/7 settings using hydra







295 average cpu fps 
(My old record with everything maxed and not stable was 314 average cpu fps i think, with these new memory stick and settings it should be good for ~320-330 fps when running bench settings )


----------



## umea

@domdtxdissar I know that Audioboxer experienced inability to run tRCDRD 14 @ 3800 with their old kit, how about yourself?


----------



## Frosted racquet

Frosted racquet said:


> Here's an update, I think I have it figured out with your help and @Veii.
> 
> Reverted back to XMP profile, only increased VSOC to 1.15v and no errors with 1usmus profile for 25 cycles, which is the first time there were no errors with XMP timing. Forgot to disable GDM that time, retested with GDM disabled and 2T, but this time various errors again. Wanted to cry and set the RAM on fire because I forgot GDM can be a pain like that.
> Tried @Veii recommendation VDIMM 1.38v, tRDWR 10, CAD_BUS 40-20-30-24 but the errors kept popping up. Reverted back CAD_BUS to straight 24, after 5+ hours of testing, no errors. SO it seems either a combination of VSOC, VDIMM and tRDWR or just tRDWR were problematic.


OK, another (frustrating) update. I've narrowed it down to tRDWR 10 and VDIMM 1.38v being required for stability. Passed 2x 30+ cycles of 1usmus profile. However...
Increasing VDIMM further to 1.4v results in an #4 error after 15+ cycles. How is VDIMM connected to other parameters? What do I need to change so I can increase VDIMM further, as I'm going to need it to further tweak the OC.


----------



## Audioboxer

domdtxdissar said:


> tRFC 228 put up a really good fight with me, but in the end i have managed to knock it back in line
> 
> Had multiple runs where testmem simply would stop running without giving any errors, with timer still running, often at cycles between 15 and 24 🤬
> What fixed it in the end was higher voltages.. +20mv to VDDP, CCD and IOD fixed testmem from stop running between cycles
> 
> I'm pretty sure this is also my finalised profile for awhile now..
> We have the exact same settings now *Audioboxer 🤣*
> 
> View attachment 2527194
> 
> 
> Lots of things going on in this screen, so i will also write what it show:
> 
> 25 cycles testmem 1usmus cfg
> 3000% Karhu ramtest
> 30min OCCT Large AVX
> Aida64 memory benchmark with fantasy numbers
> CPU-Z cpu bench, ST 709 and MT above 14k
> 
> Quick and easy gaming test in SotTR with daily 24/7 settings using hydra
> View attachment 2527199
> 
> 295 average cpu fps
> (My old record with everything maxed and not stable was 314 average cpu fps i think, with these new memory stick and settings it should be good for ~320-330 fps when running bench settings )


Gotta drop those DD's bro  4/2 and 6/4! Then we're identical! Well, technically I still need to drop to Setup 55 👀 Just goes to show this bin for others should be capable around this range as well.

I'm going to guess cause I have a B550 Unify X with only 2 DIMMs it might explain why I can squeeze these timings out on slightly less voltage. TM5 timing out with tRFC was something I experienced when I dropped down to 222. Suggesting I too needed more voltage at that point.


----------



## domdtxdissar

umea said:


> @domdtxdissar I know that Audioboxer experienced inability to run tRCDRD 14 @ 3800 with their old kit, how about yourself?


These are my old 4x8gb settings:








tRCDRD 14 ran just fine


----------



## Audioboxer

Yeah it just seems like my 3600 14-14-14-14 set, surprisingly, cannot handle tRCDRD 14 at 3800. If you ask me a reason to possibly consider saving a few bucks and buy the 3600 14-15-15-15 set.

I do think it's telling G.SKILL have not binned and sold a 3800 14-14-14-14 set, it would easily be their most popular seller (or up there), even if it was 1.5~1.55v rated. If you ask me shows they must struggle to mass bin tRCDRD 14 at 3800, because it would be the dumbest marketing decision ever not to tap into that part of the enthusiast market, especially with the arrival of Ryzen 5xxx which more often than not likes 1900 FCLK.

What I'm looking out for now is to find a 4000 14-15-15-15 bin that cannot handle tRCDRD 14 at 3800. Because if you ask me it even seems a bit strange they would opt for two killer 4000 sets, 16-16-16-16 at 1.4v and 14-15-15-15 at 1.55v before tackling 3800 14-14-14-14. I know intel exists, but it's pretty widespread knowledge next to no one is booting 2000 FCLK without WHEA/problems on AMD.

The 3800 bin they do sell IIRC is like 14-16-16-16 1.5v. I'm even surprised that hasn't been binned for 14-15-15-15.


----------



## umeng2002

Doesn't seem to be heat... 16-16-16-32 3733 MT/s runs to at least 9300% Karhu with Auto subtimings.


----------



## o1dschoo1

4x8 cl12 3200 on a 1700x on a x570 aorus LOL... https://valid.x86.fr/hj466i


----------



## Luggage

Veii said:


> y-cruncher close to always triggers PROCHOT for me
> It doesn't get to the point where FIT-PRE is a limiter
> But also AVX2 tests have a fixed vdroop
> Sounds to me like thermal limit comes later than voltage limit
> When voltage limit is gone, thermal limit is the first throttle before voltage limit can be reached.
> But scalar if on auto, can change it's range behaviour at any time
> Edit:
> Or cores switch to a lower strap, as vdroop by AVX2 + loadline droop was too strong
> Hence "lower current draw"
> Can't say about other users systems, without having it infont of me
> Only know how it behaves for me and systems I've seen
> 
> Possible but needs near that 1.6v
> 
> This is sadly not the whole story and 2018 conclusion
> It is not actively used, but is used
> Also i might be wrong about "not actively" hence IMC FW changed so also tFAW, tMAC.tMAW, tMRD behavior and logically also tRFC2/4
> Unsure here ~ but in general, this quote is more of an excuse than telling the whole story *
> Same way as "tCKE doesnt do anything without PDM enabled"
> Both half-true and doesn't tell the whole story.
> 
> Edit:
> * i can't be sure about thermal limit throttle, as before that CPU ECC does package throttle and autocorrect
> Unsure if thermal limit above 50c is triggered, and unsure how the current range is
> But very sure that they are used and factored in
> Unsure how active, at this point of time hence UNLIMITED tMAC.tMAW seems to be used, and not ? calculated unless user enforced
> 
> Too early agesa , to tell hidden settings behaviour
> But fully changed since 1.1.8.X
> Well also on matisse and earlier
> Conclusion about tRFC2 was made based on one scenario not being met
> Ignoring it actively changes tMRD decision, and should change tPHY decision
> Also ignoring that what you see are "fixed" timings, and tMRD behavior changes in realtime up to suited need
> DRAM is dynamic not in a single state
> GDDR is not much different
> ~ except for quad or octa data-rate
> 
> @Danny.ns BLCK boost stop, is a bug with c-states
> It does keep boost for me, till 102.75
> 102.85 does but out to 97.85, which is also a bug
> But precision boost, never bugged ot
> It only bugs out if you disable LCLK DPM
> Then THM & cTDP bugs out
> Sadly ProcHOT hardthrottle nonsense still remains active


More numbers - now with voltage

As you close in on a limit the usage changes in a strange way. fex PPT reached 190, ok so I raise limit to 195 - now PPT never reaches even 190... arghh










And even more screenshots



http://imgur.com/a/YFCmxTv


I really wish Vermeer Monitor was stable with something heavier than CPU-Z but it crashes with CB or Y-cruncher

Sorry >_>


----------



## Audioboxer

Would I be correct to assume with the way Setup times work, the lower you can go the better your performance should or could be? Like I know 56 to 55 is hardly a massive difference but that is in theory how it should be? Get stable closer to the cut off point and see better performance?

1T pure obviously being the absolute best position to be in, but that's jut hardly happening with a 5950x at 3800.


----------



## Veii

Audioboxer said:


> Get stable closer to the cut off point and see better performance?


The added latency difference between SETUP timings is far to small to matter
Picoseconds should it be, else y-secounds (smaller than ns)

But timings "world clock" value, changes between MCLK strap
Old easy math was 3 bumps on MCLK = +1 tCL, +1 tRCD
33.33, 66.67, 99.98/100Mhz
Soo technically every 200MT/s

Math is not that clean sadly,
Its a bit more than 3 bumps, but a bit less than 4
To equal out to the same delay taken

3800 C14-14 is slightly harder than 4000 C15-15
3200 C14-14 is slightly harder than 3600 C16-16
4200 C15-15 is a bit easier than 4000 C14-14
While 3800 13-13 is slightly harder than 4266 15-15

The higher you go, the easier it gets (sounds stupid)
Aside from equalising transfer time delays, with higher not nicely looking timings
It's easier for the ICs to run longer timed delays , compared to lower timings in lower speed
Its harder for the PCB, but it's not harder for the cells

3733 13-13 for example is far harder than 4000 C14-14
3600 technically being similar, still ending up harder
Hard to explain,
Just that timings even when it being placeholders
Is harder to sqeeze down, than just increasing frequency and running similar transfer time-delay, timings with a higher number

You can try to figure out a setup time + CKE from the sheer
Bellow SETUP 32 , 31 or lower
If you are bored
Or work towards tRCD+tRTP=tRAS part


Audioboxer said:


> Yeah it just seems like my 3600 14-14-14-14 set, surprisingly, cannot handle tRCDRD 14 at 3800.


It has to hold it at 3733
3800 is a bit of a bigger step'up, alone as tPHY should change too


----------



## Audioboxer

Veii said:


> The added latency difference between SETUP timings is far to small to matter
> Picoseconds should it be, else y-secounds (smaller than ns)
> 
> But timings "world clock" value, changes between MCLK strap
> Old easy math was 3 bumps on MCLK = +1 tCL, +1 tRCD
> 33.33, 66.67, 99.98/100Mhz
> Soo technically every 200MT/s
> 
> Math is not that clean sadly,
> Its a bit more than 3 bumps, but a bit less than 4
> To equal out to the same delay taken
> 
> 3800 C14-14 is slightly harder than 4000 C15-15
> 3200 C14-14 is slightly harder than 3600 C16-16
> 4200 C15-15 is a bit easier than 4000 C14-14
> While 3800 13-13 is slightly harder than 4266 15-15
> 
> The higher you go, the easier it gets (sounds stupid)
> Aside from equalising transfer time delays, with higher not nicely looking timings
> It's easier for the ICs to run longer timed delays , compared to lower timings in lower speed
> Its harder for the PCB, but it's not harder for the cells
> 
> 3733 13-13 for example is far harder than 4000 C14-14
> 3600 technically being similar, still ending up harder
> Hard to explain,
> Just that timings even when it being placeholders
> Is harder to sqeeze down, than just increasing frequency and running similar transfer time-delay, timings with a higher number
> 
> You can try to figure out a setup time + CKE from the sheer
> Bellow SETUP 32 , 31 or lower
> If you are bored
> Or work towards tRCD+tRTP=tRAS part
> 
> It has to hold it at 3733
> 3800 is a bit of a bigger step'up, alone as tPHY should change too


Very interesting, thanks Veii. Have you got a link to that sheet? It's the one thing I forgot to bookmark along with TM5 error list and google doc with confirmed results.


----------



## Audioboxer

Also LOL at Windows 11 cache issues










I'm aware you can attempt to fix this yourself with the registry, just thought I might hold on to see if MS fixes it themselves. Wouldn't want to mess with registry and then there is a proper fix. I have no idea why MS has been as crappy as they have with AMD for Windows 11, apparently next to all improvements and thought-processes from them went into Intel's upcoming releases.

Meanwhile, I've heard that Linux has been getting a lot of AMD love.


----------



## umeng2002

I'm sure Intel basically paid MS to make Windows 11 just so Alder Lake can work properly.


----------



## Nizzen

umeng2002 said:


> I'm sure Intel basically paid MS to make Windows 11 just so Alder Lake can work properly.


Is that a bad thing if it's performing VERY good?
I just want MORE performance, whatever the name or color the hardware has  
_Performance to the people_ !


----------



## Audioboxer

Nizzen said:


> Is that a bad thing if it's performing VERY good?
> I just want MORE performance, whatever the name or color the hardware has
> _Performance to the people_ !


Of course it's a good thing it just seems MS has neglected AMD which is a bad thing lol. I've heard the scheduler for handling Ryzen boosting and so on is also pretty poor on Windows 11 compared to 10. No doubt AMD has some blame in the mess too, they seem to be up to nonsense these days as well.

It's great AMD has been awesome on the hardware front for a while, but Intel will hit back and AMD really need to up their game with software, whether its BIOS jank or making sure operating systems play nicely with their hardware.


----------



## umeng2002

Look between the lines. MS has a "new" OS launching at the same time as Alder Lake with scheduler enhancements and everything in order make sure it works well. Meanwhile when AMD releases FX or Zen CPUs, MS is like, "yeah we'll get around to updating the scheduler a little bit in a few months... idk... we're pretty busy making sure Candy Crush works well on UWP."


----------



## Veii

Audioboxer said:


> I'm aware you can attempt to fix this yourself with the registry, just thought I might hold on to see if MS fixes it themselves. Wouldn't want to mess with registry and then there is a proper fix.


At very worst it does nothing
First and 3rd level cache where "unused" and kernel assigned

You can remove the DWORD-32's and it's as if nothing happened
The 2nd level cache was set as zero on stock, soo infinite

Generally a "good" thing, people report better results on Win11
And a good thing that ryzen still is decent without chipset drivers and other helping powerplans or kernel fixes/intel compiler opcache faking trickery

But it can likely be much better
Somebody should try if overboost is still an issue on Win11 kernel
I made a powerplan to trigger it nearly instant with a peak limiter , soo make a use out of this mess ~ but it was too aggressive, caused random idle reboots and needs an actual fix (on AMDs side)
Soo maybe check if Win11's scheduler fixes this now ~ and as to why AMD didn't want to touch it
(maybe they are overwhelmed with other work, but really it has been 5-6 months already)



Audioboxer said:


> Very interesting, thanks Veii. Have you got a link to that sheet?


Take a look at the 4th sheet, the shenanigans experimenting field
I tried to make/extend the values which work, for every many MCLK options
Not great, surely not perfect and without technical maths ~ but what worked, worked


----------



## spajdr

Audioboxer said:


> Also LOL at Windows 11 cache issues
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I'm aware you can attempt to fix this yourself with the registry, just thought I might hold on to see if MS fixes it themselves. Wouldn't want to mess with registry and then there is a proper fix. I have no idea why MS has been as crappy as they have with AMD for Windows 11, apparently next to all improvements and thought-processes from them went into Intel's upcoming releases.
> 
> Meanwhile, I've heard that Linux has been getting a lot of AMD love.


Not having that issue anymore using latest W11 insider preview on 5600X.


----------



## Audioboxer

Veii said:


> At very worst it does nothing
> First and 3rd level cache where "unused" and kernel assigned
> 
> You can remove the DWORD-32's and it's as if nothing happened
> The 2nd level cache was set as zero on stock, soo infinite
> 
> Generally a "good" thing, people report better results on Win11
> And a good thing that ryzen still is decent without chipset drivers and other helping powerplans or kernel fixes/intel compiler opcache faking trickery
> 
> But it can likely be much better
> Somebody should try if overboost is still an issue on Win11 kernel
> I made a powerplan to trigger it nearly instant with a peak limiter , soo make a use out of this mess ~ but it was too aggressive, caused random idle reboots and needs an actual fix (on AMDs side)
> Soo maybe check if Win11's scheduler fixes this now ~ and as to why AMD didn't want to touch it
> (maybe they are overwhelmed with other work, but really it has been 5-6 months already)
> 
> 
> Take a look at the 4th sheet, the shenanigans experimenting field
> I tried to make/extend the values which work, for every many MCLK options
> Not great, surely not perfect and without technical maths ~ but what worked, worked


Seems my current timings really don't like under the cut point. 3-3-15 and 9 for example struggle to even boot into Windows.

Think I'll just be sticking to 55/56 lol


----------



## Veii

Audioboxer said:


> Seems my current timings really don't like under the cut point. 3-3-15 and 9 for example struggle to even boot into Windows.
> 
> Think I'll just be sticking to 55/56 lol


That was tried on 3800 MT/s ?


----------



## Taraquin

.
Finally! Got 1T stable at 4000. A bit surprised that in order to lower tRP and tRC by 1 and tRCF by 12 I have to raise voltage by 0.03V which gives me the no 15 overheat\tRFC error at 16-20 cycles. Seems like 40 20 30 24 was the trick as 24 20 24 24 was impossible to stabilize at 1T. Actually 2T needs 1.45V aswell on these timings, but is a 1-2% percent slower.


----------



## anta777

WTRL=6 or 8
WTRS=3
WR=12 or WR=10 and RTP=5
SD/DD all =1
SCL all=3 or 2


----------



## Audioboxer

Veii said:


> That was tried on 3800 MT/s ?


1900/3800 yes


----------



## Taraquin

anta777 said:


> WTRL=6 or 8
> WTRS=3
> WR=12 or WR=10 and RTP=5
> SD/DD all =1
> SCL all=3 or 2


Wtrs 3 and/or wtrl 8 wont boot. I tried rtp 5 but get lower performance, maybe cause it don't add up as tRC x tRTP = tRFC then? Maybe tWR will work better? Will try. 

Haven't tried scls and SD/DD, thx for tip


----------



## MrHoof

I am done with DrvStr resistance. 24 ClkDrvStr is almost Stable but will always error late ....


----------



## musician

umeng2002 said:


> Look between the lines. MS has a "new" OS launching at the same time as Alder Lake with scheduler enhancements and everything in order make sure it works well. Meanwhile when AMD releases FX or Zen CPUs, MS is like, "yeah we'll get around to updating the scheduler a little bit in a few months... idk... we're pretty busy making sure Candy Crush works well on UWP."


and yet ADL use a hardware scheduler. This is just nonsense speculation. You never know how much is AMD helping / lobbing. Besides MS profits from either AMD and Intel new PC. I mean if you buy a new PC, you have to buy an OS as well and MSI really don´t care which one it is. It´s not like Windows for AMD are less profitable or anything like that 
And the cache thing @Audioboxer, is it a real performance drop, or just an AIDA bug as it was roughly like a year ago? As the AIDA just displayed wrong numbers but the cache performance was in the fact unaffected? 
And lets be honest, the market share is about 80% Intel, 20% AMD? It would be obvious that MS want to optimize its SW for the majority first.
The thing is, almost all Intel spreadsheets are public, while almost all AMD documentation is confident, so it _may_ play a role too. And this is especially sad because AMD has very big fan base.
Anyway, I would not be worry about it at all. ADL will be faster than 5000. But there is AMD 3D coming soon, I bet MS will be ready for the 3D cache launch.
TBH I am worrying much more about the AGESA state than about a Windows optimization. I am sure that bug-less AGESA would have much bigger impact than any OS optimization at all. 🙏


----------



## Thanh Nguyen

domdtxdissar said:


> tRFC 228 put up a really good fight with me, but in the end i have managed to knock it back in line
> 
> Had multiple runs where testmem simply would stop running without giving any errors, with timer still running, often at cycles between 15 and 24 🤬
> What fixed it in the end was higher voltages.. +20mv to VDDP, CCD and IOD fixed testmem from stop running between cycles
> 
> I'm pretty sure this is also my finalised profile for awhile now..
> We have the exact same settings now *Audioboxer 🤣*
> 
> View attachment 2527194
> 
> 
> Lots of things going on in this screen, so i will also write what it show:
> 
> 25 cycles testmem 1usmus cfg
> 3000% Karhu ramtest
> 30min OCCT Large AVX
> Aida64 memory benchmark with fantasy numbers
> CPU-Z cpu bench, ST 709 and MT above 14k
> 
> Quick and easy gaming test in SotTR with daily 24/7 settings using hydra
> View attachment 2527199
> 
> 295 average cpu fps
> (My old record with everything maxed and not stable was 314 average cpu fps i think, with these new memory stick and settings it should be good for ~320-330 fps when running bench settings )


How is your read and write and latency at that level?


----------



## Dodgexander

I swear I always get the worse binned CPUs. After weeks of testing 1900 FCLK I have vsoc at 1136 and vddg iod at 1060 to be stable. I've tried lowering each one but I get single WHEA's every few hours of testing with y-cruncher.

This is a lot better than vsoc 1215, vddg iod 1150 I had before but I'm still worried that 99% of people seem to have much lower vddg iod..

I've tried everything. First keeping vsoc high and going as low as 900 vddg iod and then working up in 20mv steps.
Second trying to keep vsoc just 40-50 higher than vddg iod and stepping both voltages up together from 900 iod up to 1050.
What could be the missing piece to lowering vddg iod more? I've already tried different resistances like procODT, drive strength, termination strength etc. I seem most stable with procODT at 34.3, 36 or 40. Lower than this is more unstable and doesn't seem to work with 1T.

Drive strengths are 40-20-20-24 and termination is disabled, disabled, RZQ5

I've tried raising and lowering vddg ccd and vddp, I have both sitting at 900 now but can seemingly run even less vddg ccd see stable.

Should I even worry about 1060 vddg iod degrading my CPU?

I'm on 2x 8gb 4400mhz viper steels and 5800x on an Aorus elite running ram at 3800mhz CL20 right now, GDM off, 1T. I plan to work on timings once I've got lowest stable on FCLK.


----------



## Mach3.2

My Zen 3 luck sucks as well, my 5600X can't seem to run negative curve optimiser properly at all, and have an FCLK hole at 1900MHz. My 5900X also have an FCLK hole at 5900X, and requires 1.1375V vSOC to run 1866MHz IF.

Just got a single WHEA 19 while surfing the web after a month or two running vSOC at 1.1375V so I'm not particularly worried about it.

But at least the CCD quality on my 5900X seem to be pretty decent, it takes -ve curve optimiser like a champ.

@Dodgexander VDDG IOD at 1.06V should be safe.








AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net


----------



## Veii

Taraquin said:


> Wtrs 3 and/or wtrl 8 wont boot. I tried rtp 5 but get lower performance, maybe cause it don't add up as tRC x tRTP = tRFC then? Maybe tWR will work better? Will try.
> 
> Haven't tried scls and SD/DD, thx for tip


tRFC part , is no define ruleset
It's something made based on discharge prediction
tRTP matters more for tRAS
tRFC mini, where you borrow this ~ expects a correct tRAS & tRC
Also expects tRP to be long enough (stable) to cover voltage requirements

Only then tRFC mini predicted-value, functions
Anta's suggestions, i wish they would work for me too
Sadly, tWTR_L bellow 9 is too low for me to even post. 11 works well instead of 14 or 15
tWTR_S 3 instead of 4, gives a slight bandwidth boost
If it works just like this, great but SCL's often 4 lead to better results instead of 2
~ expecting both to be stable of course

Giving fixed digit Clk values, is complicated. Everything scales by MCLK

Generally dont mix both
Anta is rather technically focused, mini tool is rather prediction based
Refined and functions, but still not a clear ruleset
Keep that in mind 🙂


----------



## Taraquin

Veii said:


> tRFC part , is no define ruleset
> It's something made based on discharge prediction
> tRTP matters more for tRAS
> tRFC mini, where you borrow this ~ expects a correct tRAS & tRC
> Also expects tRP to be long enough (stable) to cover voltage requirements
> 
> Only then tRFC mini predicted-value, functions
> Anta's suggestions, i wish they would work for me too
> Sadly, tWTR_L bellow 9 is too low for me to even post. 11 works well instead of 14 or 15
> tWTR_S 3 instead of 4, gives a slight bandwidth boost
> If it works just like this, great but SCL's often 4 lead to better results instead of 2
> ~ expecting both to be stable of course
> 
> Giving fixed digit Clk values, is complicated. Everything scales by MCLK
> 
> Generally dont mix both
> Anta is rather technically focused, mini tool is rather prediction based
> Refined and functions, but still not a clear ruleset
> Keep that in mind 🙂


So I should care about tRFC being dividable by tRC? Just use lowest working value for both?


----------



## Veii

Taraquin said:


> So I should care about tRFC being dividable by tRC? Just use lowest working value for both?


From the technical side, tRTPns matters inside tRFCns range (tRC just requires tRAS and tTP to be correct. While tRP matters too for tRFC)
tWRns showed to matter as for stability, but I haven't seen an engineer agree with me on pretty visible results between stable and unstable ~ but rather book theory

Can't answer 
Every OCer has different methodics
"It's stable" is all that matters ~ however you get it to be so


----------



## anta777

Our tRC,tRAS and tRP is not at all the same tRC,tRAS and tRP that is used by the system during memory regeneration (tRFC related).
True tRC,tRAS and tRP (tRFC related) we do not see.


----------



## anta777

For a stable tRFC, it absolutely does not matter what we set tRC,tRAS,tRTP,tRP in bios.
Since internal timing is used (depends on vendor memory).


----------



## Veii

anta777 said:


> For a stable tRFC, it absolutely does not matter what we set tRC,tRAS,tRTP,tRP in bios.
> Since internal timing is used (depends on vendor memory).


The problems ends then between settings who are stable, and settings that are not
When there is no path to take, there is no reason to move away from XMP ~ when 40% of the timings we do not see and realtime change

This is the issue,
It's clear that half we can't see & mostly control a little amount that also can be time-broken by memory if the values are plain st*pid by the user (seeable as lower does no perf change or even performs worse)

But the question ends to,
"Rules to follow are higher and not always stable"
Methods to gain stability are not always following JEDEC (see 1x tFAW exploit)


Spoiler






















* i don't run this anymore ~ have found more perfoming tricks
But it's one of these exotic ones, that nobody likes or can explain (to what i gather)
There are many events like this

If we shouldn't touch timings at all, as a lot depends on the tMRD and vendor firmware design, memOC would die out
And if we should try to find new methods and stability is held + performance is better ~ it appears to be wrong, as it doesnt follow JEDEC rules

I'm confused about the logistic path to take, here
Everyone copying everyone, doesn't bring up flaws nor research forward


----------



## XPEHOPE3

Luggage said:


> I really wish Vermeer Monitor was stable with something heavier than CPU-Z but it crashes with CB or Y-cruncher


It doesn't crash by itself during CB or y-cruncher for me. But it does crash when run together with HWiNFO because it doesn't access power monitor table correctly, I think.


anta777 said:


> For a stable tRFC, it absolutely does not matter what we set tRC,tRAS,tRTP,tRP in bios.
> Since internal timing is used (depends on vendor memory).


While that's what I was thinking too, I wonder if your writing comes from OC experience + general logic, or from insider information from memory/MB engineers?


----------



## anta777

*Veii*
Real FAW=16, so what is it worth equal to in the bios=8.
Controller amd fixes incorrect timings.
*X....*
second


----------



## Taraquin

So I followed your advice Veii and Anta. Got a bit further, can run my custom setup of 20 cycles usmus with no errors now  Lowering tRC og tRFC more gives me error 4, 5 and 15 after 10 cycles, setting voltage higher gives me error 4 and 5 around cycle 5. Lower voltage gave me error 0 and 2. Anyways a slight improvement from tRTP 6 and tRC 48\tRFC 288 that I ran previously. Haven`t tried SCLs\ SD yet, but can try later


----------



## anta777

WTRL<WR always.
Test tm5 with config universal.
[email protected]
Run along with furmark.
Then you have enough 3 cycles.


----------



## Luggage

XPEHOPE3 said:


> It doesn't crash by itself during CB or y-cruncher for me. But it does crash when run together with HWiNFO because it doesn't access power monitor table correctly, I think.
> While that's what I was thinking too, I wonder if your writing comes from OC experience + general logic, or from insider information from memory/MB engineers?


THANK YOU - it's because I run CB and Y-Cruncher through Benchmate. And Benchmate use some HWInfo hooks.

Now I just have to re-run things another cold night U_U


----------



## Taraquin

anta777 said:


> WTRL<WR always.
> Test tm5 with config universal.
> [email protected]
> Run along with furmark.
> Then you have enough 3 cycles.


Hmm, wtrl 8 booted, but got loads of error 4, scl's 3 same. Latency was worse in aida aswell, error-correcting maybe?


----------



## anta777

I only recognize stability with passed tm5 and universal config.
Get through with your stable timings

Maybe WTRL=9


----------



## Taraquin

anta777 said:


> I only recognize stability with passed tm5 and universal config.
> Get through with your stable timings
> 
> Maybe WTRL=9


Passed 20 rounds usmus with wtrl 10, but I can try 9


----------



## anta777

I know the config usmus is wrong (incorrect).
It has a lot of bugs.


----------



## Audioboxer

anta777 said:


> I only recognize stability with passed tm5 and universal config.
> Get through with your stable timings
> 
> Maybe WTRL=9


Are you anta777 behind the extreme profile? Does this mean universal config is to _replace_ your profile???


----------



## anta777

There is already the newest config - absolut, it replaces all the others.
Universal faster extreme, was created to replace him.


----------



## XPEHOPE3

anta777 said:


> Test tm5 with config universal.
> [email protected]
> Run along with furmark.


Do you have a way of deciphering what errors found with this config might mean?


anta777 said:


> I know the config usmus is wrong (incorrect).


How can a testing config be wrong, incorrect or bugged? Does it say it covers certain edge cases but actually doesn't? Does it give false positives? Isn't it just a test sequence with the only possible fault of providing "not enough coverage" for the commonly run 25 cycles?


----------



## MrHoof

Intresting i just tried the universal2 config and it actuly errored 2mins before then end in only 43mins. The same timings passed karhu 2h /1usmus 25cylce 2:50h. I am guessing its my ClkDrvStr at 30. Gonna repeat a run with the standard 40. 2 erros in test 1.

edit: yes it was, now gonna run 4 cycle.


----------



## anta777

*X....*
1.About errors:
tm5 can detect three kinds
1) tRCD,tRP,tRFC,tRRDS,tRRDL,tFAW, partially tRAS,tRC,tWR
2) tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE
3) voltage controller
You need to adjust the timings one by one.
-RCD,CL,RP,RRDS,RRDL,FAW,RAS,RC
-WR,RTP,WTRL,WTRS
-RDWR,WRRD,SD/DD,SCL
-RFC
2.Errors in the tests themselves and you should have discovered them yourself long ago


----------



## MrHoof

Is it worth increasing the amount of cylces or would you say 3 cycles are enough 99% of the time?


----------



## Veii

anta777 said:


> *X....*
> 1.About errors:
> tm5 can detect three kinds
> 1) tRCD,tRP,tRFC,tRRDS,tRRDL,tFAW, partially tRAS,tRC,tWR
> 2) tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE
> 3) voltage controller
> 2.Errors in the tests themselves and you should have discovered them yourself long ago


Deciphering a new config will take again at least 80-100hours 😣
Will see between your current and Arshia's current
If all 3 dont report errors , then i'll think about switching/skipping switching
(Will give them 2 tries, after a week)

Will intentionally make a mistake and see which of them finds it
"A bad config" to my experience either is
~ it doesn't find issues
~ like HCI and Karhu | is being influenced by 3rd paty issues like unstables cores or Test/Programm requiring too complex Instructions & so creating heat

Wouldn't call anything else "bad".
Easier as dev to use other people's config or not speak at all about his
Result would else be too bias talk

HCI & Karhu both are great
They are sadly too affected by outside memory instability and take too long
Memtestpro is also a great too, but all these are not efficient
Non of them are "bad" configs/options

Edit:
The good thing about 1usmus_v3
It finds issues very fast within first 3-6 cycles (10-15min on 2x8)

The bad thing about it,
It's too efficient. Thermal equilibrium doesn't get to be a factor at all.
Soo it needed extension towards 25 cycles.

Compared to old anta777 config,
It was faster and both found equal accuracy issues

Can't speak about potential future without seeing it in present time
No idea how much it misses or doesnt miss
Not a good idea to call anything ojt of people's work "bad"
Unless it was same runtime compared
(time, thermal equilibrium)


----------



## anta777

*MrHoof*
Another testers recommend 4 cycles.
I have three cycles + furmark.
In the first and last steps I run 3 cycles, on the intermediate - 1 cycle.


----------



## Luggage

anta777 said:


> WTRL<WR always.
> Test tm5 with config universal.
> [email protected]
> Run along with furmark.
> Then you have enough 3 cycles.


Why run with Furmark?
To put heat in system or some other reason because with an external radiator and watercooled GPU, furmark doesn't really affect my memory temps.


----------



## anta777

*Veii*
No, it won't work that way.
Author tm5 allows mirrormovie to use the parameter 0=1,2,3,4, but in usmus-config use parameter=16384! - nonsens (test14).
Author tm5 allows for pattern 2 param0 and param1 - max 8-digit hex number, but in usmus-config use 9-digit! - nonsens (tests 6,11,12,13).
Testing Window Size (Mb)=880, but better max 1536.
MirrorMove with Parameter=1 - devalues the test itself (test 3).
I'm not talking about incorrectly chosen patterns, parameters in tests, time and combination of tests.

And deciphering errors based on incorrect tests and random patterns is very powerful.


----------



## anta777

*Luggage*
To simulate maximum thermal stress in games.
You can simply reduce the speed of the cooling system


----------



## Veii

anta777 said:


> *Veii*
> No, it won't work that way.
> Author tm5 allows mirrormovie to use the parameter 0=1,2,3,4, but in usmus-config use parameter=16384! - nonsens.
> Author tm5 allows for pattern 2 param0 and param1 - max 8-digit hex number, but in usmus-config use 9-digit! - nonsens.
> I'm not talking about incorrectly chosen patterns, timing and combination of tests.


Wouldn't a broken config be always broken ?
Or be random broken, if this was an issue ?

Can't speak about the programm bugs
Both speak russian, they'll be able to communicate making correct configs ~ i expect ?
1usmus had 3 tries too and didn't bother to fix it, why so

Idk about issues, the config always works or always doesn't work
Nothing random ever happened with it ~ for me to call it "broken"
Just maybe "not intelligent enough?" ~ if it misses features
Idk, can't relate to any bugs, been using it too long & TM5 had updates
Not a dev or coder to judge here 🤔


----------



## anta777

Don't pretend.

Tm5 last updates(change test windows) happened already in version 0.5.
The rest of the variables were not affected by these updates.
In 0.11, it became possible to load author's configs.
In 0.12, the window displaying from 12 to 16 tests has been corrected.

Author tm5 Serj determines the possible admissible parameters of his program, not me, not 1usmus.
If parameter in mirrormovie 1,2,3,4 can not use 16384, real use another parameter.
If param0,1 for pattern 2 8-digit not use 9-digit, real use another.
I am not even talking about the wrong patterns, time, combination and parameters, since few people will understand it.
Little did you know, in the 2nd version of the config 1usmus there was an incorrect 14th test (2nd refreshstable), which 1usmus had to urgently remove after I emphasized several times to him about his mistake, so the 3rd version config appeared.


----------



## Audioboxer

Bit confused about what to run now lol. Most of the overclocking scene still says use [email protected], which I know for 3 cycles takes much longer than above, probably about 2 hours+. 1usmus v3 often used here as it's good to diagnose error messages thanks to Veii, 25 cycles of it takes about 2 hours 30 mins+.

This profile defaults to 3 cycles, but it's only taking just under 40 minutes. At least it passed  

I always follow up big changes to my profiles with y-cruncher, so I don't mind trying various TM5 profiles.


----------



## anta777

I'll post Absolut tomorrow.
Or I can send it to your mail today.


----------



## anta777

CWL=13 and RDWR=8
WRRD=4
DD(all)=1


----------



## Veii

anta777 said:


> Don't pretend


No need. I'm no dev to judge.
No right to speak about it ~ except that it did it's job
To the random % of features, it was capable at


anta777 said:


> Little did you know, in the 2nd version of the config 1usmus there was an incorrect 13th test (2nd refreshstable), which 1usmus had to urgently remove after I emphasized several times to him about his mistake, so the 3rd version config appeared


Why didn't he bother to fix it ?

Nothing need to worry if both yours and Arshia's are better
Please don't missunderstand neutral questioning, with protection

Hey,
That means, it can get even better ~ if he bothers to fix it
Strangely, mirror move errors are tracked
Will like to see how much more efficient your updates are
Could save a lot of time, depends on the time requirements

Time will tell
If it doesn't perform better, there is really no reason to give up something "half-functioning"


Audioboxer said:


> This profile defaults to 3 cycles, but it's only taking just under 40 minutes. At least it passed


Guess we need to standardise this as 6 loops then , or 10
It's too short to reach thermal equilibrium on it's own, without helping heating elements (GPU)

Efficiency will then tell which is better and finds issues first 🤭
Here is Arshia's


https://cdn.discordapp.com/attachments/666969437445816340/875127127710777424/SuperStableEditAv2.cfg










Memory Test config file v0.02Copyrights to the program belong to me.Serjte - Pastebin.com


Pastebin.com is the number one paste tool since 2002. Pastebin is a website where you can store text online for a set period of time.




pastebin.com




Haven't had time to try them for a whole day

Soo both collaborated here
Bare looks this one feels to take 6-8h
Yes we'll see what will speak for itself
Just soo many hours need to run into deciphering it, as revisons keep getting out

Feels similar to what i see about board manufactures
You can't get it right first, 2nd or 3rd time 😐
I hope this was it then with revisions

Edit:
Updates are good, but it's really bothersome
* also Arshia's words where ~ he prefers GSAT over it
Sadly GSAT doesn't give error descriptions out.
Very bothersome


----------



## MrHoof

anta777 said:


> CWL=13 and RDWR=8
> WRRD=4
> DD(all)=1


How do calculate RDWR and WRRD ? Why does WRRD need to be 4?
I am currently running CWL=14 RDWR=7 WRRD=3.


----------



## Audioboxer

anta777 said:


> CWL=13 and RDWR=8
> WRRD=4
> DD(all)=1


tCWL can't be put to 13 in my BIOS, only 12/14 lol


----------



## anta777

Serj:
"По моим наблюдениям, что совсем не является "истиной"!, тест работает
эффективно тогда, когда выполняется больше времени тепловой инерции
модуля памяти. Если на модуле нет радиатора, то время теплового
переходного процесса порядка "пары-тройки секунд". Если тест
выполняется короче, его эффективность существенно снижается. Но, опять
же подчеркну - это не есть истина, просто некоторые (неправильные)
наблюдения. ))"
translate
"According to my observations, which is not "true" at all !, the test works
effective when more thermal inertia time is performed
memory module. If the module does not have a heatsink, then the heat
transient process of the order of "a couple of seconds". If the test
is shorter, its effectiveness is significantly reduced. But again
I emphasize that this is not true, just some (wrong)
observation. ))"


----------



## anta777

*MrHoof*
Jedec and engineers motherboard:
RDWR=CL-CWL+5+WPRE
WRRD=CWL-CL+4+RPRE
RDRDSD/DD=4+RPRE
WRWRSD/DD=4+WPRE

If CL=CWL:
WRRD=RDRDSD/DD (with a well-written bios).


----------



## anta777

*Audioboxer*
Bios is correctly written, you need to rejoice.


----------



## anta777

*Veii*
Arshia config - "there is no point in running the same test in a row, it is better to just increase its execution time".


----------



## Veii

anta777 said:


> *Veii*
> Arshia config - "there is no point in running the same test in a row, it is better to just increase its execution time".


250% hold time is better than triple the cycle repetition amount ?
On your config


----------



## Audioboxer

anta777 said:


> *Audioboxer*
> Bios is correctly written, you need to rejoice.


Not sure on the English translation here but I'll see if I can find a way. Searching online seems to suggest tCWL 13 should be do-able. Maybe only on Intel?


----------



## anta777

*Veii*
Yes, but I created a new config- absolut, I can send it to the mail today


----------



## anta777

*Audioboxer
to be happy=rejoice*
Jedec:
CWL=11,12,14,16,18,20,22.


----------



## Taraquin

anta777 said:


> I only recognize stability with passed tm5 and universal config.
> Get through with your stable timings
> 
> Maybe WTRL=9


Wtrl 9 worked fine, ran your test without problems, but used ravencoinmining (the worst miningstressor) on the side instead of furmark (several drivers have protective measures from my experience that restricts load.)


----------



## anta777

Great.


----------



## Veii

anta777 said:


> *Veii*
> Yes, but I created a new config- absolut, I can send it to the mail today


Great !
Yes i at least want 45-50min for guaranteed thermal equilibrium reach
A big room ~50m² open test bench could need ~75-80min, before the difference to bigger rooms, gets far too small to matter (degree in C, delta)

Efficient tests are preferred (fast sequences, cycle ends), they could show fast issues within 15-20min (you can reboot faster)
* no requirement 
But new variant of error options come after the same cycle loop runs (40min after the start soo memory got warm)

Too many issues are just sync related
A well made sequence will find them at time (where heat doesn't matter)
But it still is a variable which needs at least a full cycle sequence to happen after >40min
To be very sure timings can hold the heat 😁

We had 1usmus_3 fail always either at the end of cycle 19 1:20h in
Or at the last last one #15, after 24 loops after 2:30h
Mostly at this time bad tRFC or unstable allcores showed up as issues

Edit:
Mostly at the very end, it was bad RTT's and/or low quality board components
Signal got noisy after a lot of time and failed stability
While passing the "timings" based tests
Resistances around powering failed


----------



## anta777

And it is not easier to just worsen artificial cooling?


----------



## Veii

anta777 said:


> And it is not easier to just worsen artificial cooling?


I have a 120mm fan at 300rpm only on the side
RTTs are "weak" , it doesn't heat up on my side at 1.65v daily
But people have good cases, bad cades but huge rooms
Ripsaw heatsinks that cool half of the ICs (cover half of A1,A2 PCB)

its for ease of use
Run config and go to bed
Notice if it fails the first round(s) or it fails after an hour
RGB slowly slowly creeps up in heat 4-5c on tridentZ's
It's bothersome explaining people, thermal equilibrium is a thing and you will fail mid-game with your GPU

Testing with a GPU test is worth, but does not much on an open bench :/
* pulling 500W for 7-8h sleep time, is hard to explain being "fine"

Having at least a full sequence loop after the 50min mark could be valuable
Overkill, but to be very sure it's fine. Guaranteeing it for the user before they RMA it for example

Industry uses membench, this takes 8-9 hours
Germans require karhu 10 000%, this also takes more than a night
See it as little endurance and keeping such requirements away as "the config is long enough where thermal equilibrium is no topic for debate"
Our loops took 1:30-1:40h
I extended my personal to 2:30h, Kedarwolf who prefers GSAT too ~ runs it at 10 000% testing time = 7-8h too

Little guarantee , nothing much more 😊
Wasting power and time is fine, in exchange of secureness and one problem less for debate (is it really really stable, topic)


----------



## anta777

I agree.
1usmus about test memory:
"I never test with one thing. In order not to muck myself with hours of testing, I drive TM5 cycles 5 at 100% (and not at 500%) and of course Lynx, gigs for 10-12 runs 5. This was always enough for me (3 years with the RAM) to reveal obvious problems with timings or signal lines.
All that comes to light in an hour or two means you need to find a way to cool both percent and memory.
There is also a concept as "spontaneous" errors, to combat which ECC was developed  therefore a home PC a priori cannot become a constant of stability"


----------



## MrHoof

Well those "spontaneous" errors are so rare that it be really unlucky to have them happen when running a test. The chance for that happening is really low.


----------



## Luggage

I should turn off my fans?


----------



## MrHoof

Thats what i am just doing but I am already at 56°C on the dimms after 14mins. Atleast no errors yet 🤣 normaly I max out at 45°C.

edit: And as i posted that i got a error but they normaly never ever get that hot. Atleast i know fan is 100% needed. 
edit2: Gonna try a RPM that is not audible.


----------



## anta777

<60C good


----------



## MrHoof

Anta777

Do you know many people that run 1T with DR like 4x8 or 2x16 without Setup timings? I am think I am the only on here. I cant be the only one.


----------



## Audioboxer

So running Furmark along with this new profile is the way to go? 

Might as well give it a go I guess. Seeing as my RAM is watercooled and my GPU is obviously in the loop it should be a good test.



MrHoof said:


> Anta777
> 
> Do you know many people that run 1T with DR like 4x8 or 2x16 without Setup timings? I am think I am the only on here. I cant be the only one.
> View attachment 2527397


I think anyone with 1 CCD has got a chance if their IMC is good. Biggest problem with 1T pure seems to be 2 CCD.


----------



## Taraquin

MrHoof said:


> Anta777
> 
> Do you know many people that run 1T with DR like 4x8 or 2x16 without Setup timings? I am think I am the only on here. I cant be the only one.
> View attachment 2527397


Isn`t setup times mainly required at 60+ drvstr? Maybe 40 is borderline.


----------



## MrHoof

Taraquin said:


> Isn`t setup times mainly required at 60+ drvstr? Maybe 40 is borderline.


Well on SR 2x8 i could even run 20 clkdrvsr. SR is a total diffrent story. As far as i know most people use setup timings to get past instant errors wich are mostly also not fixable by increasing clkdrvstr.


----------



## anta777

*Audioboxer*
My profile works regardless of furmark.
You don't need to load your pc with anything, and even put it in the refrigerator for the duration of the test.
Apparently it will be optimal for you.


----------



## KedarWolf

In AIDA64 go to Help, Check for Updates, I think it downloads a new Bench.dll, noticeable improvement.


----------



## MrHoof

anta777 said:


> *Audioboxer*
> My profile works regardless of furmark.
> You don't need to load your pc with anything, and even put it in the refrigerator for the duration of the test.
> Apparently it will be optimal for you.


No thats wrong but running furmark when you never gonna run AAA games or anything that will load up your GPU heavy to produce unrelastic temps is no point.
edit: The user should always consider the max temp they will reach in whatever usecase they have them self.


----------



## musician

Audioboxer said:


> I think anyone with 1 CCD has got a chance if their IMC is good. Biggest problem with 1T pure seems to be 2 CCD.


It´s not the first time I read something like this, but it´s not true. IMC is part of the IOD, not part of a CCD, hence number of CCD(s) does not matter at all.


----------



## Audioboxer

musician said:


> It´s not the first time I read something like this, but it´s not true. IMC is part of the IOD, not part of a CCD, hence number of CCD(s) does not matter at all.


Yes but is it not true 2 CCD chips on average tend to have _worse_ IMCs? Seems like most of the struggles with 1T and even at times simply overclocking RAM can be made worse by 2 CCD chips.


----------



## musician

Audioboxer said:


> Yes but is it not true 2 CCD chips on average tend to have _worse_ IMCs? Seems like most of the struggles with 1T and even at times simply overclocking RAM can be made worse by 2 CCD chips.


I seriously doubt this.


----------



## anta777

*MrHoof*
The point of testing is to create conditions that will definitely turn out to be worse than during normal operation.
Can be tested with a 5 minute test and cinebench.
Can be tested with a 120 minute test and linx.
Let everyone choose.


----------



## MrHoof

anta777 said:


> *MrHoof*
> The point of testing is to create conditions that will definitely turn out to be worse than during normal operation.


Well thats what i mean already running tm5 is worse then almost anything else i do to my system. In normal use i will not even hit tm5 temps. Ram overclocking is just a hobby for me not any practical use.


----------



## Audioboxer

musician said:


> I seriously doubt this.


If this weren't the case why do all the top memory overclockers buy 1 CCD chips, often the G variants?

I'm not saying you're wrong by the way I'm just trying to understand why I've been reading 2 CCD is harder to overclock memory on.


----------



## musician

Audioboxer said:


> If this weren't the case why do all the top memory overclockers buy 1 CCD chips, often the G variants?
> 
> I'm not saying you're wrong by the way I'm just trying to understand why I've been reading 2 CCD is harder to overclock memory on.


G variant is totally different reason, the IMC is part of the core and that´s why the memory can be clocked so high, there is not the crappy IOD.
edit: and OC favourite is dual CCD 5900X.


----------



## Veii

Audioboxer said:


> If this weren't the case why do all the top memory overclockers buy 1 CCD chips, often the G variants?
> 
> I'm not saying you're wrong by the way I'm just trying to understand why I've been reading 2 CCD is harder to overclock memory on.


Dual CCDs are harder to stabilise as silicon amperage is generally higher
But also have generally a better bin
There are more cores to balance and more tasks to check

IMC is fantastic. We can reach here and there 5400-5800MT/s
Fabric/interposter, linkspeeds are not that great
Signal integrity is not great and heat over scaling ~ integer scaling for heat by bandwidth is far to high
Wattage to bandwidth

Else we would've been on quad channel a long time ago and threadripper on Octo
Sadly taking thread ripper with same clock @ 360W
On octa channel, this would be around the 500W mark, 480ish
Same thematic was for HBM vs GDDR & consumer ryzen

Heat output is too dense by too high bandwidth
AMD maxed out the Vega 7 ,64 with hbm stacks ~ for bandwidth interleaving and stacking (maxed PCIe 3.0 x16)
But the heat output and low clocks by bad signal integrity, where big issues
Numa interleaving is still a thing , but it is around 80% more heatoutput by double the bandwidth

Ending here about the Dual CCD signal integrity part
Else IMC for MCLK is more than capable. Fabric is not thaat great yet
1CCD is generally less work
Probably it's more preferred, as it's cheaper and easier to push (heat)
It also hurts less, if something breaks


----------



## MrHoof

musician said:


> G variant is totally different reason, the IMC is part of the core and that´s why the memory can be clocked so high, there is not the crappy IOD.
> edit: and OC favourite is dual CCD 5900X


I would say depends what your go for. Single CCD for lowest latency but Dual CCD for more bandwith.


----------



## PJVol

Veii said:


> Fabric/interposter, linkspeeds are not that great


I'd say its quite an understatement ))


----------



## domdtxdissar

MrHoof said:


> I would say depends what your go for. Single CCD for lowest latency but Dual CCD for more bandwith.


You wanted bandwidth ? 








(Hydra shenanigans)

Anyway, completed 3 cycles on this new cfg with my "finalized" timings











anta777 said:


> CWL=13 and RDWR=8
> WRRD=4
> DD(all)=1


My motherboard bios also don't support tCWL = 13 (fails in memory training and don't recover, have to reset bios)

Could not run WRRD=4 and RDWR=8 when i was running tCL=13 and tCWL=12 (fails in memory training and don't recover, have to reset bios)
WRRD=4 and RDWR=8 together with DD's at 1 is working @ tCL=14 and tCWL=14








Do you recommend the DD=1 settings over my first profile ? Anything else you see that can be improved ?

On first profile i had tPHYRDL @ 26/26 and tPHYWRL=7
DD1 profile is tPHYRDL @ 28/28 and tPHYWRL=9

_edit_
After some testing in dram calc i can firmly say that my first profile is faster then the gimped WRRD=4 RDWR=8 tCL=14 and tCWL=14 profile when testing on my setup.. Around 97sec vs 98sec @ same static CPU OC


----------



## SneakySloth

Not exactly sure who the author is but according to this post (that is linked on the memory overclocking github)









[Sammelthread] - Ryzen RAM OC + mögliche Limitierungen


@The Professor Thx fürs benchen und nochmal klarstellen. Hat schon seinen Grund, warum ich hier öfters die CL16/CR1.5-GDM-Setups vorschlage :F. @coolhead Dein 3733CL15-CR1-Setup ist instabil.




www.hardwareluxx.de





We shouldn't use the Universal profile with a DIMM voltage of over 1.45?


----------



## sonixmon

MrHoof said:


> Anta777
> 
> Do you know many people that run 1T with DR like 4x8 or 2x16 without Setup timings? I am think I am the only on here. I cant be the only one.
> View attachment 2527397


I have the exact same kit as you and mine requires GDM on or Setup timings. Not my IMC because my last set of Hynix was DR 3600 CL16 and ran pure 1T fine even at 3800mhz but below CL16 was a no go of course. I even tried CL16, full auto anything but nothing above 3200 will run pure 1T on this kit!



Audioboxer said:


> Yes but is it not true 2 CCD chips on average tend to have _worse_ IMCs? Seems like most of the struggles with 1T and even at times simply overclocking RAM can be made worse by 2 CCD chips.


As mentioned above my CPU/IMC was ok at 3800 CL16 1T with my old ram kit but not my new kit!


----------



## Dodgexander

SneakySloth said:


> Not exactly sure who the author is but according to this post (that is linked on the memory overclocking github)
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Sammelthread] - Ryzen RAM OC + mögliche Limitierungen
> 
> 
> @The Professor Thx fürs benchen und nochmal klarstellen. Hat schon seinen Grund, warum ich hier öfters die CL16/CR1.5-GDM-Setups vorschlage :F. @coolhead Dein 3733CL15-CR1-Setup ist instabil.
> 
> 
> 
> 
> www.hardwareluxx.de
> 
> 
> 
> 
> 
> We shouldn't use the Universal profile with a DIMM voltage of over 1.45?


These TM5 profiles are getting silly now. I'm sure the broken English doesn't help but all we need is one profile, together with accurate indication of which test corresponds to each error.

It's obtrusively complicated, and everyone with their own idea of how long, and how many concurrent tests should be run.

I lost following the thread when it was recommended to run furmark or linx the same time as a TM5 profile...

Thanks for finding that post BTW. Next thing we are killing our ram following an unknown profile made by someone random who we can't even trace back to.


----------



## umea

SneakySloth said:


> Not exactly sure who the author is but according to this post (that is linked on the memory overclocking github)
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Sammelthread] - Ryzen RAM OC + mögliche Limitierungen
> 
> 
> @The Professor Thx fürs benchen und nochmal klarstellen. Hat schon seinen Grund, warum ich hier öfters die CL16/CR1.5-GDM-Setups vorschlage :F. @coolhead Dein 3733CL15-CR1-Setup ist instabil.
> 
> 
> 
> 
> www.hardwareluxx.de
> 
> 
> 
> 
> 
> We shouldn't use the Universal profile with a DIMM voltage of over 1.45?


how much voltage you run is completely dependent on what IC you have. most of the people here are running b-die which can run much higher voltages safely, i believe veii's daily is 1.6v and hasn't had any problems. most of us run 1.5v or higher fine as well


----------



## SneakySloth

umea said:


> how much voltage you run is completely dependent on what IC you have. most of the people here are running b-die which can run much higher voltages safely, i believe veii's daily is 1.6v and hasn't had any problems. most of us run 1.5v or higher fine as well


Definitely, I'm not arguing against that. Just wondering what that comment is referring to and whether it is generally okay to be using that profile? I only bring this up as that specific post is linked in a guide that is often shared everywhere which makes me think that person is someone who understands tm5 and its profiles.

As anta777 themselves are posting here, it should be fairly easy to clarify this.


----------



## umea

here's a run of my current ram settings, initially thought hmm idk what to do next because i can't run tRCDRD 14 but i think i'll see if i can lower the main timings a bit more, especially trp/tras/trc. this is at 1.5v btw, might see how low i can get it stable

also did this just to check how hot the ram gets, this is with a fan running at 100% on it, which is fine to me (i dont care about noise a ton) but im gonna install the copper heatsinks i got from bart's store and see how much that drops the temps with it at 100% and see if i can lower the fan speed and maintain a good temperature still.


----------



## mongoled

Dodgexander said:


> These TM5 profiles are getting silly now. I'm sure the broken English doesn't help but all we need is one profile, together with accurate indication of which test corresponds to each error.
> 
> It's obtrusively complicated, and everyone with their own idea of how long, and how many concurrent tests should be run.
> 
> I lost following the thread when it was recommended to run furmark or linx the same time as a TM5 profile...
> 
> Thanks for finding that post BTW. Next thing we are killing our ram following an unknown profile made by someone random who we can't even trace back to.


Thank for posting my thoughts

 

Im of this chain of thought, we want to find the source of the errors, hence the reason I use 1usmus v3 config, as so far this is the only config that gives us an inkling on where we should be looking to change things to stop memory errors.

Im am sure there are many of us would be willing to switch to other configs if they provided a similar source of information with regards to errors that are thrown.

Its as simple as that really.

So @anta777, are you able to provide the diagnostic information for the error codes that your config produces ??


----------



## Taraquin

umea said:


> here's a run of my current ram settings, initially thought hmm idk what to do next because i can't run tRCDRD 14 but i think i'll see if i can lower the main timings a bit more, especially trp/tras/trc. this is at 1.5v btw, might see how low i can get it stable
> 
> also did this just to check how hot the ram gets, this is with a fan running at 100% on it, which is fine to me (i dont care about noise a ton) but im gonna install the copper heatsinks i got from bart's store and see how much that drops the temps with it at 100% and see if i can lower the fan speed and maintain a good temperature still.
> View attachment 2527478


From my experience: If you run tRC higher, then you can lower tRCDRD. They both affect performance quite a bit. At 3800 I could run tRCRD at 15 and tRC at 43 or I could run tRCDRD at 17 and tRC at 34. Both worked and priduced similar performance. I ended up settling for 15 tRCDRD, but since agesa 1.2.0.2 I do 4000cl16 and 45 tRC since that became possible. 

Suggestion if you keep your current settings:
tRP 12 or 13 if possible, except for that there is little to do. 

Optional 14-14-14-28-42, see if that works? Lower tRP, tRCDRD and tRC all requires quite a bit of voltage.


----------



## umea

Taraquin said:


> From my experience: If you run tRC higher, then you can lower tRCDRD. They both affect performance quite a bit. At 3800 I could run tRCRD at 15 and tRC at 43 or I could run tRCDRD at 17 and tRC at 34. Both worked and priduced similar performance. I ended up settling for 15 tRCDRD, but since agesa 1.2.0.2 I do 4000cl16 and 45 tRC since that became possible.
> 
> Suggestion if you keep your current settings:
> tRP 12 or 13 if possible, except for that there is little to do.
> 
> Optional 14-14-14-28-42, see if that works? Lower tRP, tRCDRD and tRC all requires quite a bit of voltage.


nope, i cant get 14 flat no matter what i throw at it, spent weeks and probably a hundred hours total of restarting over and over because it always errors out a **** ton immediately. ive tried 14 14 14 28 42 and even judt 14 14 14 all the rest auto, but nothing ever worked


----------



## TimeDrapery

I'll try it but I'm not sure I trust it yet










Anyone know why latency would be such garbage? I'll have to check n see what background processes are running but it seems so high for the timing set... Yuck


----------



## anta777

*SneakySloth*
LMhz=anta777+nucl3arlion+xyligano
*domdtxdissar*
WTRL=6


----------



## Veii

umea said:


> how much voltage you run is completely dependent on what IC you have. most of the people here are running b-die which can run much higher voltages safely, i believe veii's daily is 1.6v and hasn't had any problems. most of us run 1.5v or higher fine as well


Hearing for the first time, that it's dangerous to run X voltage for Y test (for memory)
I daily 1.65v, it was a good sweetspot.
Can pick between 1.64-1.69v. Afterwards the ICs hardcrash
On Rev E till 1.72v before they hardcrash, but haven't notice any positives in running it beyond 1.66v

A0 PCB didn't like anything beyond 1.54v
It was dangerous to keep pushing it and lost memory channels
Then RTTs where remade/redesigned & i can daily higher voltage
But voltage ≠ Amperage arriving
Soo VDIMM ≠ Heat , not directly

1.65v set runs cooler to the touch than 1.51v at "old public RTTs"
Also as voltage helps , i see no reason not to run it
Couldn't extend so far beyond 1.69v. No RTT combination
Couldn't change RTT_WR to something stronger either.

EDIT:
All examples are stability oriented
XOC and Suicide-Runs (scores), are another topic
I don't participate in such


----------



## Taraquin

Taraquin said:


> From my experience: If you run tRC higher, then you can lower tRCDRD. They both affect performance quite a bit. At 3800 I could run tRCRD at 15 and tRC at 43 or I could run tRCDRD at 17 and tRC at 34. Both worked and priduced similar performance. I ended up settling for 15 tRCDRD, but since agesa 1.2.0.2 I do 4000cl16 and 45 tRC since that became possible.
> 
> Suggestion if you keep your current settings:
> tRP 12 or 13 if possible, except for that there is little to do.
> 
> Optional 14-14-14-28-42, see if that works? Lower tRP, tRCDRD and tRC all requires quite a bit of voltage.


Lower tRP is all I can think if then  Might give you a 1% performance  If you haven't used curve optimizer yet, then that is your go to performance increase. If you have a good bin the up to 5-6% performance in certain games/apps is possible


----------



## Frosted racquet

Frosted racquet said:


> OK, another (frustrating) update. I've narrowed it down to tRDWR 10 and VDIMM 1.38v being required for stability. Passed 2x 30+ cycles of 1usmus profile. However...
> Increasing VDIMM further to 1.4v results in an #4 error after 15+ cycles. How is VDIMM connected to other parameters? What do I need to change so I can increase VDIMM further, as I'm going to need it to further tweak the OC.


Anyone?


----------



## anta777

*mongoled*
1.About errors:
tm5 can detect three kinds
1) tRCD,tRP,tRFC,tRRDS,tRRDL,tFAW, partially tRAS,tRC,tWR
2) tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE
3) voltage controller
You need to adjust the timings one by one.
-RCD,CL,RP,RRDS,RRDL,FAW,RAS,RC
-WR,RTP,WTRL,WTRS
-RDWR,WRRD,SD/DD,SCL
-RFC
2.Errors in the tests themselves and you should have discovered them yourself long ago


----------



## mongoled

anta777 said:


> 2.Errors in the tests themselves and you should have discovered them yourself long ago


Thanks for not answering the question, or maybe, not understanding the question.

But lets say I am toooo stupid, from what you have written for number "2" you are saying that anybody who has not worked out what error codes come from which test is "stupid"

??


----------



## Audioboxer

domdtxdissar said:


> You wanted bandwidth ?
> View attachment 2527436
> 
> (Hydra shenanigans)
> 
> Anyway, completed 3 cycles on this new cfg with my "finalized" timings
> View attachment 2527437
> 
> 
> 
> My motherboard bios also don't support tCWL = 13 (fails in memory training and don't recover, have to reset bios)
> 
> Could not run WRRD=4 and RDWR=8 when i was running tCL=13 and tCWL=12 (fails in memory training and don't recover, have to reset bios)
> WRRD=4 and RDWR=8 together with DD's at 1 is working @ tCL=14 and tCWL=14
> View attachment 2527445
> 
> Do you recommend the DD=1 settings over my first profile ? Anything else you see that can be improved ?
> 
> On first profile i had tPHYRDL @ 26/26 and tPHYWRL=7
> DD1 profile is tPHYRDL @ 28/28 and tPHYWRL=9
> 
> _edit_
> After some testing in dram calc i can firmly say that my first profile is faster then the gimped WRRD=4 RDWR=8 tCL=14 and tCWL=14 profile when testing on my setup.. Around 97sec vs 98sec @ same static CPU OC


Same as me then with tCWL. I've seen some reports online of people running it at 13, but it's maybe intel/older AMD boards or something.

Anyway, you dropping some of those timings to 1 got me wanting to try it










Though I'm still not confident on this profile only running 3 cycles.










Also I know it's been pointed out to me time to complete is mainly influenced by how much memory gets tested, but any time I see a quicker finishing time it's hard not to think about it lol. Will need to run other benches and see if it's even worthwhile dropping DDD and RDD down to 1.



mongoled said:


> Thanks for not answering the question, or maybe, not understanding the question.
> 
> But lets say I am toooo stupid, from what you have written for number "2" you are saying that anybody who has not worked out what error codes come from which test is "stupid"
> 
> ??


I think it's just a bit of a language barrier understanding what @Veii had done was spend 100s of hours linking each TM5 test # to this document for errors tRFC mini

I don't think anta is meaning to state people in here don't understand, generally, what an error in TM5 could relate to.

If the community here was to move over to another profile the disadvantage in the short term is obviously losing Veii's knowledge of what each TM5 test number might relate to. That is obviously extremely useful when you're starting out and you might have all sorts of errors.

Ultimately I think whatever profile anyone runs it's always a good idea to also use y-cruncher, OCCT, Karhu or any other stability testing app. But there is no doubting 1usmus v3 with the error sheet is incredibly useful, especially when it comes to resistances/voltages. Or how much it helps new people try and understand memory overclocking, because let's be honest, once you "have the knowledge" it's very easy to forget/take for granted how difficult getting into memory overclocking can be for new people.

It shouldn't be an "elite club", as much as the old-timers hate answering the same questions over and over. It's good to share knowledge and try and help more people step into the world of memory overclocking. IMO, anyway.


----------



## anta777

*mongoled*
Tm5 can detect only three kinds, but each timing separately.
Personally, the config 1usmus is enough for you.
You deserve it.


----------



## anta777

*Audioboxer*
DD timings used only for 4 DIMM.
You can leave them in the auto.
The difference in performance can only be from mistakes in writing the BIOS.
Just remember SD=DD.

Random patterns cannot be tied to specific errors, since they are random, this is their meaning.
You can only conditionally bind mirrormovie and mirrormovie128 with errors controllers and voltages.


----------



## Audioboxer

anta777 said:


> *Audioboxer*
> DD timings used only for 4 DIMM.
> You can leave them in the auto.
> The difference in performance can only be from mistakes in writing the BIOS.
> Just remember SD=DD.
> 
> Random patterns cannot be tied to specific errors, since they are random, this is their meaning.












When on auto though SD≠DD


----------



## anta777

Errors of the bios authors,it is obvious.
Need to compare performance:
RDRDSD=5 RDRDDD=5
RDRDSD=4 RDRDDD=4
RDRDSD=5 RDRDDD=4
and
WRWR...... 7/7
6/6
7/6


----------



## mongoled

anta777 said:


> *mongoled*
> Tm5 can detect only three kinds, but each timing separately.
> Personally, the config 1usmus is enough for you.
> You deserve it.


Why thanks for leaving your ego on the table....

And subsequently telling anyone who has not worked out your error codes as being stupid.

Maybe thats why you decided not to answer the question

🤣🤣


----------



## anta777

*Tm5 can detect only three kinds, but each timing separately.
You need to configure memory sequentially, then what the errors are associated with will be known.*

1. FREQ + VDIMM, GDM, CMD.
2. RCD,CL,RP,RCDWR,RAS,RC.
3. WR,RTP,WTRS,WTRL.
4. SCL,SD/DD,RDWR,WRRD.
5. RFC.


----------



## domdtxdissar

anta777 said:


> *domdtxdissar*
> WTRL=6


Could not get tWTRL=6 to boot whatever settings i tried.

But i managed to lower tRAS by 1 to =22 -> tRC=34 -> tRFC=221
Is this the correct formula to calculate tRFC, do this look okai ?











Audioboxer said:


> Also I know it's been pointed out to me time to complete is mainly influenced by how much memory gets tested, but any time I see a quicker finishing time it's hard not to think about it lol. Will need to run other benches and see if it's even worthwhile dropping DDD and RDD down to 1.


Do you have a very bloaty windows install ? Everytime i see a screen with ~800mb used in the start of TestMem.. 800*32= is only 25.6 gigs.
When i start testmem with chrome with 20 tabs and lots of other programs open in background, i get something like ~912*32

How much stuff do you have running after windows restart ?
This is how my windows looks 2minutes after restart: (need ~2mins for everything to start in the background)















Btw, i found SCL=4 to be faster then SCL=2 in dram calc bench.
SCL=2 gives lower read speed but higher write, but in the end SCL=4 is faster.



Audioboxer said:


> When on auto though SD≠DD


Get 100% the same with asus bios also..



anta777 said:


> Errors of the bios authors,it is obvious.
> Need to compare performance:
> RDRDSD=5 RDRDDD=5
> RDRDSD=4 RDRDDD=4
> RDRDSD=5 RDRDDD=4
> and
> WRWR...... 7/7
> 6/6
> 7/6


Very hard to test the differences at this point, but i think the fastest on my setup is:

tRDRDSD=4
tRDRDDD=2
tWRWRSD=6
tWRWRDD=4

Believes it gives a little higher write speed then 4/4/6/6


----------



## anta777

Best test for compare - corona benchmark.

WTRL=7


----------



## Audioboxer

domdtxdissar said:


> Could not get tWTRL=6 to boot whatever settings i tried.
> 
> But i managed to lower tRAS by 1 to =22 -> tRC=34 -> tRFC=221
> Is this the correct formula to calculate tRFC, do this look okai ?
> View attachment 2527501
> 
> 
> 
> Do you have a very bloaty windows install ? Everytime i see a screen with ~800mb used in the start of TestMem.. 800*32= is only 25.6 gigs.
> When i start testmem with chrome with 20 tabs and lots of other programs open in background, i get something like ~912*32
> 
> How much stuff do you have running after windows restart ?
> This is how my windows looks 2minutes after restart: (need 2mins to start everything in background)
> View attachment 2527503
> View attachment 2527505
> 
> 
> Btw, i found SCL=4 to be faster then SCL=2 in dram calc bench.
> SCL=2 gives lower read speed but higher write, but in the end SCL is faster.
> 
> 
> Get 100% the same with asus bios also..
> 
> 
> 
> Very hard to test the differences at this point, but i think the fastest on my setup is:
> 
> tRDRDSD=4
> tRDRDDD=2
> tWRWRSD=6
> tWRWRDD=4
> 
> Believes it gives a little higher write speed then 4/4/6/6


You could say so, I guess





















Though I have firefox open when I took that screenshot and it can be a bit of a memory hog. I obviously don't have it running when I run TM5. I'll restart shortly and get a picture from a fresh boot.

Interesting on the SCLs, I've always just ran 2 because "it works".










Tbf I got my best membench with them at 2.










196 processes 

@domdtxdissar have you cut down on Windows services as well?


----------



## umea

Veii said:


> Hearing for the first time, that it's dangerous to run X voltage for Y test (for memory)
> I daily 1.65v, it was a good sweetspot.
> Can pick between 1.64-1.69v. Afterwards the ICs hardcrash
> On Rev E till 1.72v before they hardcrash, but haven't notice any positives in running it beyond 1.66v
> 
> A0 PCB didn't like anything beyond 1.54v
> It was dangerous to keep pushing it and lost memory channels
> Then RTTs where remade/redesigned & i can daily higher voltage
> But voltage ≠ Amperage arriving
> Soo VDIMM ≠ Heat , not directly
> 
> 1.65v set runs cooler to the touch than 1.51v at "old public RTTs"
> Also as voltage helps , i see no reason not to run it
> Couldn't extend so far beyond 1.69v. No RTT combination
> Couldn't change RTT_WR to something stronger either.
> 
> EDIT:
> All examples are stability oriented
> XOC and Suicide-Runs (scores), are another topic
> I don't participate in such


well, that was my knowledge based on what people said over on reddit (useless) but also that github overclocking guide. i guess it makes sense that if B-Die can run higher than "suggested" voltages then others can too. 
dropped tRAS and tRC ... time for 21/35. don't seem to be able to get tcl 13 and trp 13 to run properly yet but that's next step


----------



## PJVol

mongoled said:


> hence the reason I use 1usmus v3 config, as so far this is the only config that gives us an inkling on where we should be looking to change things to stop memory errors.


Not to argue which config is better, I just wanna say the following:
May be *I am *tooo stupid that I wasn't able to see how "error # descriptions or hints or inking or whatever" can help finding the wrong timing or impendance set.
Moreover, quite often it hints to the opposite of what I should have done to fix them, for example in a half of the cases the description of the error says "overheating or excessive voltage" when both weren't even close to where I should have start to worry.
So, I have serious doubts it may help me to find where I was mistaken, at all, unless some one prove my stupidity and blindness.

PS: I still using 1usmus v3 config, cause it's fast (have neither will nor patience to run these in hours)


----------



## domdtxdissar

anta777 said:


> Best test for compare - corona benchmark.
> 
> WTRL=7


Very small margins.. Done at static allcore OC

"Baseline" settings:







Score = 12198900
Score = 12190300
Score = 12118570 (outliner)

"Baseline + DD's at -2 (6/4/4/2) <-- Seems to be the fastest for me








Score = 12274400
Score = 12262300
Score = 12205300

"Baseline + SCL2"







Score = 12262000
Score = 12193700
Score = 12186600

"Baseline + SCL2 + DD's at -2 (6/4/4/2)"







Score = 12266000
Score = 12251800
Score = 12218200
Score = 12198900

DD's at 1 gave very low results. (6/1/4/1)

tWTRL=7 don't boot



Audioboxer said:


> @domdtxdissar have you cut down on Windows services as well?


Running a sophia script slimmed windows

What numbers are you gettinging in the corona benchmark ?


----------



## Enferlain

anta777 said:


> *mongoled*
> Tm5 can detect only three kinds, but each timing separately.
> Personally, the config 1usmus is enough for you.
> You deserve it.


I get error in 6 and 12 so those aren't related to your config I guess



mongoled said:


> Why thanks for leaving your ego on the table....
> 
> And subsequently telling anyone who has not worked out your error codes as being stupid.
> 
> Maybe thats why you decided not to answer the question
> 
> 🤣🤣


I don't think it's ego, just language barrier. Guy means the errors outside of what he listed are the same as the other configs


----------



## anta777

My new config for tm5 - absolut.








absolutnew.cfg







bit.ly




For 6-core processors time in main section in config need to increase 1750%.


----------



## SneakySloth

anta777 said:


> My new config for tm5 - absolut.
> 
> 
> 
> 
> 
> 
> 
> 
> absolutnew.cfg
> 
> 
> 
> 
> 
> 
> 
> bit.ly
> 
> 
> 
> 
> For 6-core processors time in main section in config need to increase 1750%.


Thank you anta777. How many cycles of this should we be running?


----------



## anta777

3, it has already installed


----------



## TimeDrapery

@anta777 

You think this new config will catch whatever this Universal config didn't?










That seems like a lot lower percentage for Karhu to error at for TM5 not to report an error

@mongoled 

It's okay dude, I'm stupid too 😂😂😂😂😂


----------



## domdtxdissar

Seems like ~1 hour runtime per cycle with 32 gigs ram
Last part is much faster then first..

36min for 1 cycle with 32 gigs memory








Right on time, 2 cycles in 1 hour and 12mins


----------



## anta777

*TimeDrapery*
I hope.


----------



## TimeDrapery

anta777 said:


> *TimeDrapery*
> I hope.


@anta777 

Me too 😂😂😂😂😂

Thanks for coming through in here and sharing all this with us, that's righteous of you


----------



## TimeDrapery

anta777 said:


> *TimeDrapery*
> I hope.


@anta777 

Also, to be clear, alongside your test config you recommend tightening timings in a certain order so as to associate errors with timing values to change?


----------



## anta777

True


----------



## MrHoof

anta777 said:


> For 6-core processors time in main section in config need to increase 1750%.


For 8-12-16 cores 1250% is fine? Why only a diffrence for 6?


----------



## anta777

16 threads -1250% (the config was written)
24 threads - >=830% 
32 threads - >=625%
12 threads - >=1670%


----------



## TimeDrapery

anta777 said:


> True


@anta777

Dope I'll reset and work it in the order you describe


----------



## anta777

Ok, only primary timings and tRFC - 3 cycles test, another enough 1 cycle.


----------



## SneakySloth

anta777 said:


> Ok, only primary timings and tRFC - 3 cycles test, another enough 1 cycle.


Just a quick question, should all DDs be 1 if we're using 4 sticks? And then all DD = SD? Just trying to figure out what else I can reduce here


----------



## anta777

No. DD use 4 sticks.
SD use dualrank.
Right SD=DD, but depends on the bios authors.
Choose the best option -use corona benchmark.


----------



## domdtxdissar

anta777 said:


> 16 threads -1250% (the config was written)
> 24 threads - >=830%
> 32 threads - >=625%
> 12 threads - >=1670%


lol you should had told me when i was writing about how it took 36minuts for a single pass for me 

Anyway i completed 3 cycles @ 1250% with a *32thread* 5950x running 2x16gb.
Seems like my CL13 and tRFC 221 baseline-set will pass everything thrown at it 😇


----------



## anta777

Good kit.


----------



## kim nk

anta777 said:


> 16 threads -1250% (the config was written)
> 24 threads - >=830%
> 32 threads - >=625%
> 12 threads - >=1670%


Hello! I have a question. I'm curious to see if this is the right setting for 5900X 
Memory share exceeds 93 to 94 or 10 minutes per cycle. Is it normal? 









And is this enough test? We passed the 3rd cycle.


----------



## anta777

Yes for 16 Gb.
But this minimum time.


----------



## kim nk

anta777 said:


> Yes for 16 Gb.
> But this minimum time.


I wonder how many weeks are recommended if you need to test with sufficient load. And how much TIME (%) should I raise for 5900X to be a sufficient test? Thank you for answering!


----------



## anta777

2500% - more than enough
10000% - maximum in tm5
But better 2500% and cycles=7
This is already for super perfectionists.


----------



## kim nk

anta777 said:


> 2500% - more than enough
> 10000% - maximum in tm5
> But better 2500% and cycles=7


I'm sorry for asking you one more question. 
5600X, 5800X, 5950X. Is 2500% load enough? I wonder if each CPU is the same at 16GB. 32GB. Does this change the number? I think a lot of my questions are being solved, so thank you so much!


----------



## anta777

*kim nk*
Time (main)*time(test)=implicitly sets the number of repetitions test.
16 Gb or 32 Gb number of repetitions test will be the same, just take a different execution time (for 32Gb will be 2 times more).
Config was written based on:
16 threads - >=1250% time
if there are more threads, then the testing time can be reduced,
if there are fewer threads, then the testing time can be increased.
It won't get any worse.
2500% is enough for 8 threads.


----------



## Dodgexander

@Veii @anta777 please could you clarify.

Why is there a warning not to run LMZ config with ram higher than 1.45v? I understand different ICs are safe at different voltages (also that voltage+drive strength=heat) but why should a test dictate a maximum voltage?

I do not understand this logic, if a RAM IC is safe at higher volts (for example, B die) then why should a test change this? Of course other IC its good to run max 1.45v maybe, but not B die.

I am a simple person, I just want one test to run between small changes, and if required, another longer test to run for bigger changes.


----------



## anta777

This opinion xyligano.
I believe that voltage does not matter.


----------



## error-id10t

I'm getting an error with TM5 and the new config file (absolutnew).

_Memory Manager #x not started. Fatal error, programm stopped!_

The other configs work. I haven't seen others comment, what am I doing wrong.


----------



## kim nk

anta777 said:


> *kim nk*
> Time (main)*time(test)=implicitly sets the number of repetitions test.
> 16 Gb or 32 Gb number of repetitions test will be the same, just take a different execution time (for 32Gb will be 2 times more).
> Config was written based on:
> 16 threads - >=1250% time
> if there are more threads, then the testing time can be reduced,
> if there are fewer threads, then the testing time can be increased.
> It won't get any worse.
> 2500% is enough for 8 threads.


Hello~! I'll ask you a question today as well. Which version of tm5 should the new config be installed and retrieved for the test? In Korea, can I use any of the two versions of adv5 version 1usmus_v3 to call config? If you have the latest version of tm5, I need a link to download it, so I'm asking. Have a good day today! Thank you always!


----------



## decalruma

hello, my first posting.
I'm a user who playing overclocking in south korea.

I have some questions to @anta777 about new config of tm5.

are there specific meanings about each numbering of tm5?

for example, can each number be matched with any timing?
can a user use the numbering of error to solve any problem of timing?

thank you for your answer in advance.


----------



## anta777

*error*
change 1536
Testing Window Size =1408 in config


----------



## anta777

*kim nk*






TestMem support page - TestMem V


Hardware testing. TestMem III



testmem.tz.ru


----------



## anta777

*decalruma*
Serj (author tm5):
Interaction of tests.
You run a program of two tests, errors start pouring in immediately at the beginning of the second test. It is logical to assume that the first test can be disabled, leaving only the second and testing will be faster. Yeah, we start testing and ... and there are no errors. Only the second test finds no errors! There is an explicit and implicit interaction between tests. For example, if you put something with an intensive data exchange before the regeneration test, then the matrix heats up and the probability of error will be greater. Alas, this is where the 'obvious' patterns ended. Implicit connections are difficult to establish, but they are there. Therefore, it is recommended to run tests in bulk, as the author did.
There is an implicit link in the data template. Tests of the "running 1" type, as a rule, have not very high detecting ability, but when they are alternated with 'pseudo-random' tests, they greatly increase the effectiveness of both. Most likely, leo is in local matrix warm-ups.


You need to configure memory sequentially.
Then it is immediately clear with what timing the error is associated.


----------



## decalruma

anta777 said:


> *decalruma*
> Serj (author tm5):
> Interaction of tests.
> You run a program of two tests, errors start pouring in immediately at the beginning of the second test. It is logical to assume that the first test can be disabled, leaving only the second and testing will be faster. Yeah, we start testing and ... and there are no errors. Only the second test finds no errors! There is an explicit and implicit interaction between tests. For example, if you put something with an intensive data exchange before the regeneration test, then the matrix heats up and the probability of error will be greater. Alas, this is where the 'obvious' patterns ended. Implicit connections are difficult to establish, but they are there. Therefore, it is recommended to run tests in bulk, as the author did.
> There is an implicit link in the data template. Tests of the "running 1" type, as a rule, have not very high detecting ability, but when they are alternated with 'pseudo-random' tests, they greatly increase the effectiveness of both. Most likely, leo is in local matrix warm-ups.
> 
> 
> You need to configure memory sequentially.
> Then it is immediately clear with what timing the error is associated.


what are the first test and second test?
I understand that you are emphasizing the influence of connections with the tests. 
but I have a fundamental problem.
I can't understand what are the tests which you said.


----------



## anta777

You cannot associate tests with timings.
Only Matrix, Interface, Addressing and Processor Controller errors can be detected.

1.Matrix ("analog" timings): RCD,RP,RRDS,RRDL,FAW,RFC,REFI, part RAS,RC,WR - pattern 1,2 (conditionally).
2.Interface ("digital" timings): tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE - pattern 0 (conditionally).
3. Addressing : CMD, GDM - pattern 1.
4. Processor controller : freq, voltage, CWL - mirrormovie and mirrormovie128, in this case, the error itself will be detected at startup Refreshstable (the beginning of any SimpleTest).


----------



## decalruma

anta777 said:


> You cannot associate tests with timings.
> Only Matrix, Interface, Addressing and Processor Controller errors can be detected.
> 
> 1.Matrix ("analog" timings): RCD,RP,RRDS,RRDL,FAW,RFC,REFI, part RAS,RC,WR - pattern 1,2 (conditionally).
> 2.Interface ("digital" timings): tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE - pattern 0 (conditionally).
> 3. Addressing : CMD - pattern 1.
> 4. Processor controller : freq, voltage, CWL - mirrormovie and mirrormovie128, in this case, the error itself will be detected at startup Refreshstable (the beginning of any SimpleTest).


does pattern mean Pattern Mode in config file? right?
How does the pattern param0 or param1 affect errors?
what does test block size mean?
sorry for my ignorance.


----------



## anta777

Right.
param0 or param1 only pattern 2, participates in random template generation
test block size: memory is shared test block size, then, inside the block, testing is performed by access by 64 byte (interleave=1) or 8 byte (interleave=0)


----------



## decalruma

anta777 said:


> Right.
> param0 or param1 only pattern 2, participates in random template generation
> test block size: memory is shared test block size, then, inside the block, testing is performed by access by 64 byte (interleave=1) or 8 byte (interleave=0)


if a user modify the interleaving size at bios options,
Will that affect the accuracy at the test block size in config file?
which size of memory interleaving do you recommand?


----------



## Audioboxer

domdtxdissar said:


> lol you should had told me when i was writing about how it took 36minuts for a single pass for me
> 
> Anyway i completed 3 cycles @ 1250% with a *32thread* 5950x running 2x16gb.
> Seems like my CL13 and tRFC 221 baseline-set will pass everything thrown at it 😇
> View attachment 2527551


Damn, noticed you've lowered some timings again, I guess I'll need to try and follow later 👀 Previously I was having problems with TM5 timing out when tRFC was dropped to nearer 220. Did you put SCLs to 4 to help with that or just because they run better at 4?

For now










This was set at 625% for 32 threads. But I doubled cycles to 6 as I just feel 3 is a bit short.


----------



## anta777

tRFC=224 or 240.
tRAS>=tRCD+tCL and tRCD=tRP better
*decalruma*
interleave=0 = Core 2 Duo

small test block size (minimum 4 Mb) - faster and harder

1=all memory
2=1/2 memory
3=1/3 memory


----------



## Audioboxer

anta777 said:


> tRFC=224 or 240.
> *decalruma*
> interleave=0 = Core 2 Duo
> 
> small test block size (minimum 4 Mb) - faster and harder


My tRFC? I used one of the calculations to get to 228 based on tRC which resulted in 227.5. I'll try 224 though.


----------



## anta777

tRFC and this tRC (in bios) not connected


----------



## decalruma

anta777 said:


> tRFC and this tRC (in bios) not connected


why not connected? I am very curious.


----------



## anta777

tRFC uses internal (vendor dependent) tRAS and tRP values

we do not see them


----------



## error-id10t

anta777 said:


> *error*
> change 1536
> Testing Window Size =1408 in config


Thanks very much.


----------



## decalruma

anta777 said:


> tRFC uses internal (vendor dependent) tRAS and tRP values
> 
> we do not see them


how can I calculate 224 or 240 with the timings in the screen shot(tcl 13 trcdrd 14 trcdwr 8 trp 12 tras 23)


----------



## Veii

Dodgexander said:


> @Veii @anta777 please could you clarify.
> 
> Why is there a warning not to run LMZ config with ram higher than 1.45v? I understand different ICs are safe at different voltages (also that voltage+drive strength=heat) but why should a test dictate a maximum voltage?


Answer is in post








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


how much voltage you run is completely dependent on what IC you have. most of the people here are running b-die which can run much higher voltages safely, i believe veii's daily is 1.6v and hasn't had any problems. most of us run 1.5v or higher fine as well Definitely, I'm not arguing against...




www.overclock.net






Request has no logic to it
Strain can be higher for MOSFETs but dimms are dimms
(Such request existed, but not for VDIMM)
They are not silicon and capacitor's do not degrade
They die or function, but do not change up to "safe" / unsafe voltages
Voltages still do not matter thaat much, its the combination of both RTT and VDIMM (and likely procODT / so also cLDO_VDDP)

Too high voltage or "st*pid RTTs"
Result in no boot.
The chance for a "dangerous boot" to happen is low
IF it happens, it will show as a lost memory channel ~ soo you'll know when you overdid it

Mostly common is to have errors and ICs dropping out
(Test freezes, test loops ~ dimm & cpu ecc)
Uncommom issues ~ random reboots , freezes in bios
Rare issues ~ successful single channel boot, inconsistent voltage error time result, 1/6 retries it posts
(too high voltage or simply bad training)

Timing issue then is shown by errors, by random reboots mid test, by no boot
Rare error part, is rather an overvoltage issue

GDDR and DDR voltage and frequency have to match
Both can have negative influences on too much VDIMM for X frequency


----------



## anta777

decalruma said:


> how can I calculate 224 or 240 with the timings in the screen shot(tcl 13 trcdrd 14 trcdwr 8 trp 12 tras 23)


no way
I count without this data


----------



## domdtxdissar

Audioboxer said:


> Damn, noticed you've lowered some timings again, I guess I'll need to try and follow later 👀 Previously I was having problems with TM5 timing out when tRFC was dropped to nearer 220. Did you put SCLs to 4 to help with that or just because they run better at 4?
> 
> For now
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This was set at 625% for 32 threads. But I doubled cycles to 6 as I just feel 3 is a bit short.


Using SCL 4 because i think i get alittle better performance with it


> Btw, i found SCL=4 to be faster then SCL=2 in dram calc bench.
> SCL=2 gives lower read speed but higher write, but in the end SCL is faster.


Can you do the same tests in the corona benchmark as me ? Then we will know alittle more... 
(static cpu oc needed)


----------



## Audioboxer

domdtxdissar said:


> Using SCL 4 because i think i get alittle better performance with it
> 
> 
> Can you do the same tests in the corona benchmark as me ? Then we will know alittle more...
> (static cpu oc needed)


Haven't tried a static OC with my 5950x, best way to go about it? I'm not a 1usmus patreon so I can't use that new app he is working on.

Interesting on the SCLs, I will have to look at that. Plus as I said I need to figure out what causes my TM5 timeouts at lower tRFC, if it's the tRFC itself, tRAS/tRC, a lack of voltage or a combination. Are you still on 1.55 VDIMM? I never had errors at lower tRFC on this set of RAM, just the few times I've tried those TM5 timeouts where it seems to crash but timer keeps going for hours happened.

That was at 220 and 222 IIRC.


----------



## mongoled

PJVol said:


> Not to argue which config is better, I just wanna say the following:
> May be *I am *tooo stupid that I wasn't able to see how "error # descriptions or hints or inking or whatever" can help finding the wrong timing or impendance set.
> Moreover, quite often it hints to the opposite of what I should have done to fix them, for example in a half of the cases the description of the error says "overheating or excessive voltage" when both weren't even close to where I should have start to worry.
> So, I have serious doubts it may help me to find where I was mistaken, at all, unless some one prove my stupidity and blindness.
> 
> PS: I still using 1usmus v3 config, cause it's fast (have neither will nor patience to run these in hours)


At this moment in time I just want something we can use as a diagnosis tool



Im still to have found time to go over the config and what Anta777 wrote to see if I can decipher how everything works.

And maybe then we can move out of the "stupid" club

 



Enferlain said:


> I don't think it's ego, just language barrier. Guy means the errors outside of what he listed are the same as the other configs


Yeah, I did say possible language barrier, though the comment "You deserve it" led me to believe something else ...



TimeDrapery said:


> @anta777
> @mongoled
> 
> It's okay dude, I'm stupid too 😂😂😂😂😂


Hey, proud members of the "stupid" club unite


----------



## Taraquin

Anta777: Really appreciate you contributing. A few questions:
When tuning ram, what timings have rulesets/ways to calculate and which don't? I understand some is controlled by mechanisms unknown to us. 
From what I have read/learned so far:
tRAS = tCL+tRCD (can be lower if low RW is used
tRC = tRAS + tRP
tFAW = tRRDS x 4
tWR = tRTP/2 or same as
tWTRL should be below tWR
tRFC don't need to be calculated but srt as low as possible

Corrections or any other 'rules'?


----------



## domdtxdissar

Audioboxer said:


> Haven't tried a static OC with my 5950x, best way to go about it? I'm not a 1usmus patreon so I can't use that new app he is working on.
> 
> Interesting on the SCLs, I will have to look at that. Plus as I said I need to figure out what causes my TM5 timeouts at lower tRFC, if it's the tRFC itself, tRAS/tRC, a lack of voltage or a combination. Are you still on 1.55 VDIMM? I never had errors at lower tRFC on this set of RAM, just the few times I've tried those TM5 timeouts where it seems to crash but timer keeps going for hours happened.
> 
> That was at 220 and 222 IIRC.


Just go in bios and set something like 1.25-1.3 vcore and 4.6ghz allcore.
If you are cooling limited (sub 200w) maybe 1.2vcore and 4.5ghz will be the best 

Dont worry about any pbo values as a static oc will overwrite it. (don't need to change any pbo settings before and after)
Doing a manual cpu oc is much easier then tuning memory 😆 

TM5 timeouts between cycles was fixed with a voltage bump across the board for me.. Everything +20mv









Vdimm is set 1.555v -> minimum voltage i see in hwmonitor is 1.544v
(max is 1.560v)


----------



## anta777

mongoled said:


> Im still to have found time to go over the config and what Anta777 wrote to see if I can decipher how everything works.
> 
> Yeah, I did say possible language barrier, though the comment "You deserve it" led me to believe something else ...


1.I doubt very much that you can understand.
2. I said what I wanted to say, the language barrier has nothing to do with it.


----------



## Taraquin

Audioboxer said:


> Haven't tried a static OC with my 5950x, best way to go about it? I'm not a 1usmus patreon so I can't use that new app he is working on.
> 
> Interesting on the SCLs, I will have to look at that. Plus as I said I need to figure out what causes my TM5 timeouts at lower tRFC, if it's the tRFC itself, tRAS/tRC, a lack of voltage or a combination. Are you still on 1.55 VDIMM? I never had errors at lower tRFC on this set of RAM, just the few times I've tried those TM5 timeouts where it seems to crash but timer keeps going for hours happened.
> 
> That was at 220 and 222 IIRC.


Until Hydra is finalized, isn't curve optimizer + pbo better? Using core cycler to find major instability, and adding - 1 offset on the failed core if you get random restarts even with stable CC. My best static OC that is avx stable on my 5600X is [email protected] ([email protected] is stable, but overheats in avx) . With CO - 29x2/-30x4 and +200 pbo and 90 PPT I get around 4.7 allcore, 4.85 single so a few % over all core OC, and a very nice idle/low load voltage of 850mv at 3.7GHz.


----------



## domdtxdissar

Taraquin said:


> Until Hydra is finalized, isn't curve optimizer + pbo better? Using core cycler to find major instability, and adding - 1 offset on the failed core if you get random restarts even with stable CC. My best static OC that is avx stable on my 5600X is [email protected] ([email protected] is stable, but overheats in avx) . With CO - 29x2/-30x4 and +200 pbo and 90 PPT I get around 4.7 allcore, 4.85 single so a few % over all core OC, and a very nice idle/low load voltage of 850mv at 3.7GHz.


In the context of finding what memory settings perform best in the corona benchmark the cpu clock need to to be static as they would influence the results otherwise..

Click the link.. 



> Using SCL 4 because i think i get alittle better performance with it



Offtopic: Hydra 1.0B is released and it work very well i would say.. Should have no problem outperforming PBO CO in 99% of the cases.. But stability needs some manual fine-tuning by the user atm.


----------



## Veii

anta777 said:


> tRAS>=. . . and tRCD=tRP better


Not tRCD+tRTP for tRASmin ?

If tRP = tRCD anyways, wouldn't it be tRCD*2 = tRAS optimal
tRAS = tRCD+tRTP works out for me
Lower than tRP


Taraquin said:


> Until Hydra is finalized, isn't curve optimizer + pbo better?


Current Hydra since 1.0X can give a preset for bios CO values to use
" i feel the analytic part (time) needs to increase for more accurate results. Core distance part

Manual method remains valid, but is unofficial 
It can be a useful tool even without directly using it
Still doesn't beat my PBO, but it would be a good tool with much more work
* CO values it still struggles with slightly, on 16 core units
** it needs 1h for 3 cores. 4-5h minimum for 16 cores


----------



## anta777

*Taraquin*
CL=CWL even
CWL=CL-1 odd
RAS=RC-RP
RP=RCD
WR=CL even 100% stable
WTRL=RTP=WR/2
WTRS=3(4)
RCDWR=8
SC=CCDS-3=1
SCL=CCDL-3=2,3,4
SD=DD
RDRDSD/DD=4+RPRE-1
WRWRSD/DD=4+WPRE-1
RDWR=CL-CWL+5+WPRE
WRRD=CWL-CL+4+RPRE 
tRFC ns convert timings, round up to the nearest divisible by 16.


----------



## anta777

*Veii*
on AMD
tRAS=tRC-tRP, this is how maximum productivity is achieved.
tRAS can only be reduced together with tRC.
tRAS optimal>=tRCD+tCL.


tRAS=tRCD+tRTP, if only tRC=tRCD+tRTP+tRP.
then it makes sens, 
otherwise senseless.


----------



## kim nk

anta777 said:


> tRFC uses internal (vendor dependent) tRAS and tRP values
> 
> we do not see them


If cl13 3800 is 13-13-13-13-26-39 when configuring the timing, what value do you prefer for trfc? trc x trtp 6 ? trc xtrtp7 ? trc xtrtp8? I used to know trc x trtp = trfc. 13-13-13-13-26-39 or is there a better timing? Now, tomorrow, we are going to test cl17 4800(xmp)17-19-19-19-39 1.60v memory. In addition, if trcd is 13 at 16 gb, the value is equal to or approximately lower than trcdwr at these values of trdwr8 to 9 trdrdscl4 twrwrscl4 scl x twrrd = trcdwr. I don't know if I have to calculate it like this. And 16gb trddsd5, trdrdd5, twrwrdsd7, twrwrdsd7, and these are usually used at 16gb. Is there a better value?
I have so many questions. I'm sorry!


----------



## mongoled

anta777 said:


> 1.I doubt very much that you can understand.
> 2. I said what I wanted to say, the language barrier has nothing to do with it.


Thanks for the confirmation, honesty is good


----------



## anta777

I don't care about your opinion
you can not write to me again


----------



## anta777

*kim nk*
tRFC only depends memory chips and density.
Samsung b-die and Hynix CJR/DJR still depend on voltage.
You translate ns into ticks,
round up to a multiple of 16.
Then you test by adding or subtracting 16.
We can put in bios tRC=64 tRAS=44 tRP=20 RRDS=6 FAW=40,
but the minimum stable tRFC will not change from this, 
since these values are not used for tRFC.


----------



## Audioboxer

domdtxdissar said:


> Just go in bios and set something like 1.25-1.3 vcore and 4.6ghz allcore.
> If you are cooling limited (sub 200w) maybe 1.2vcore and 4.5ghz will be the best
> 
> Dont worry about any pbo values as a static oc will overwrite it. (don't need to change any pbo settings before and after)
> Doing a manual cpu oc is much easier then tuning memory 😆
> 
> TM5 timeouts between cycles was fixed with a voltage bump across the board for me.. Everything +20mv
> View attachment 2527655
> 
> 
> Vdimm is set 1.555v -> minimum voltage i see in hwmonitor is 1.544v
> (max is 1.560v)


Won't be cooling limited, so I'll try 1.3/4.6 later for you. 

Nice, I'll have to look more closely at my voltages then when dropping the tRFC. I am a fair bit lower than you just now










Something in there is likely causing the timeouts with a lower tRFC.


----------



## Taraquin

anta777 said:


> *Taraquin*
> CL=CWL even
> CWL=CL-1 odd
> RAS=RC-RP
> RP=RCD
> WR=CL even 100% stable
> WTRL=RTP=WR/2
> WTRS=3(4)
> RCDWR=8
> SC=CCDS-3=1
> SCL=CCDL-3=2,3,4
> SD=DD
> RDRDSD/DD=4+RPRE-1
> WRWRSD/DD=4+WPRE-1
> RDWR=CL-CWL+5+WPRE
> WRRD=CWL-CL+4+RPRE
> tRFC ns convert timings, round up to the nearest divisible by 16.


Hmm, currently run CL 16 and WR 10, RTP 5, WR 12/RTP 6 gave me slighty worse performance. Upping to 16/8 sounds high, but I can try. Wtrl is minimum 9 now, 8 spews errors, that doesn't add up with CL 16 and WR 16. Gotta think about how to proceed. 

On non-B-die, how should one calculate tRAS and tRC? Another kit I have, Micron rev E can do 15-20(8)-11 at 3800, tRAS 21 works, but tRC below 58 is unstable.


----------



## Veii

anta777 said:


> *Veii*
> on AMD
> tRAS=tRC-tRP, this is how maximum productivity is achieved.
> tRAS can only be reduced together with tRC.
> tRAS optimal>=tRCD+tCL.
> 
> 
> tRAS=tRCD+tRTP, if only tRC=tRCD+tRTP+tRP.
> then it makes sense,
> otherwise senseless.


Aah i look at it from the opposite way
Yes tRC always is reduced

Do you have any explanation for tRC = tRAS + 1 working ?
(Only if tFAW is 1nCK)
Single rank (2*) 8* 1024mb

Edit:
It scales for 16-16-16-32-33 & 14-14-14-28-29 
With GDM, 2T, 1T


----------



## anta777

*Taraquin*
Micron tRCD=tRP
tRAS=tRC-tRP always
decrease tRAS only with tRC with tRAS=tRC-tRP


----------



## anta777

*Veii*
Have you compared performance?
tRC=tRAS+1 and tRC=tRAS+tRP


----------



## mongoled

anta777 said:


> I don't care about your opinion
> you can not write to me again


I can write to whom I want as long as I am respectul

😀


----------



## Veii

anta777 said:


> *Veii*
> Have you compared performance?
> tRC=tRAS+1 and tRC=tRAS+tRP


Yes, i went away from it later
It was used for a test between GDM and not GDM
Showing differences between what GDM does and why 2T is better to build your foundation on it
As GDM to 1T difference was far to big and it made not much sense to build a preset on GDM

Somewhere here on this thread , 7-8 ? months ago, was a comparison picture between it (6 benchmarks, 3* 14-14-14, 3* 16-16-16)

Downside, it needs much more vdimm
Was running long time tRAS = tRCD*2,
Went away from odd timings (pushing only tRP, only tRC and so on)

Stayed at the end at tRAS = tRCD+tRTP
Where tRTP was my key thing for many parts. tWR

Always treated tRC as a fixed "has to elaps" placeholder
A virtual timing. Soo at the end i picked it as anchor
tCL was not "serious enough". Every kit i have can reach low CAS with voltage
tRC did not wiggle with voltage but only with timings (to my eyes)

Postponed this burst refresh exploit and changed to tCDD_L * tRRD_S
Compared too many times between tRRDS 7 , tFAW 28 & tRRDS 6 , tFAW 36
Redid at the end the set, as other engineers where mocking me for tFAW being to long
But UrgentRefresh & SubUrgentRefresh methodic changed since 1.1.9.0+
" Burst Refresh Override" is the name of the flag

Changing this to dimm XMP tCCD_L , lead to more bandwidth
Having longer active tFAW

In order to 1nCK tFAW to work, it needed bump on tRRDS/L, bump on WTR_ & slight bump on tRDWR & UrgRef to be to 1 instead of 4
Sadly bump on tRDWR showed as too much bandwidth loss, results equalized when everything got tightened down
Soo i moved away from it

I'll revisit it
Main work was tightening down tRAS further
tRFC, went down to 112ns but it was too heat sensitive.
Up to 144.4ns liked it well. tWR 16/tRTP8 (15+8=23 tRAS, 1T)







^ bottom is what i run right now. tRRDS 6 sadly was bit faster on tFAW 36, but because people dont like it. This is on 4* mode


----------



## anta777

Where 1.1.9.0 ?
What is this?


----------



## Veii

anta777 said:


> Where 1.1.9.0 ?
> What is this?


Sorry
AGESA 1.1.8.X, 1.1.9.0, 1.1.9.1, 1.2.0.0
All where the same, a release mess.
Boardpartners got changes on 5-6 days base
~ soo every brand had a different bios update patch scale/amount of patches

It was the AGESA which introduced
SPI Armor, enabled dLDO_Injector, Updated IMC-FW, pushed Spectre v5 patches, created USB dropout issues, enabled SRIS for PCIe & LCLK DPM, broke SMU readouts before the fix, broke DF-C_States (c6 states cause overboot and self overvoltage)

A huge mess
This went on for two patches till 1.2.0.2 ~ delay to fix things
(Mess was from SMU 56.34+ -> 56.52)
Current 56.53 is ok, but not every 56.53 (Patch-C, Patch-B) is identical to this date
1.2.0.3 A, B, AB, is ok now , but it was a big mess
Overboost C6 States are still a broken mess , and over exceed maximum potential bandwidth
Sometimes pull 1.68v on OC_MODE, else hardcap at 1.55v by FIT


----------



## Taraquin

Anta777: What is WPRE and RPRE?


----------



## anta777

Write preamble
Read preamble


----------



## Taraquin

anta777 said:


> Write preamble
> Read preamble


Okay, but how do I calculate those? Or what are they derived from? Will try changing my setup but need to know what numbers to use


----------



## Audioboxer

domdtxdissar said:


> Just go in bios and set something like 1.25-1.3 vcore and 4.6ghz allcore.
> If you are cooling limited (sub 200w) maybe 1.2vcore and 4.5ghz will be the best
> 
> Dont worry about any pbo values as a static oc will overwrite it. (don't need to change any pbo settings before and after)
> Doing a manual cpu oc is much easier then tuning memory 😆
> 
> TM5 timeouts between cycles was fixed with a voltage bump across the board for me.. Everything +20mv
> View attachment 2527655
> 
> 
> Vdimm is set 1.555v -> minimum voltage i see in hwmonitor is 1.544v
> (max is 1.560v)












Just increased VSOC by one notch and VDDP by two. But I'd prefer to finish a 6 cycle to feel more confident. Still, looks like lower tRFC could well be on the menu without too much difficulty.

Unsure if SCLs on 4 also helped, guess I just need to try them at 2 as well. 3's might also be worth a look. And finally do some benching with a static CPU OC. Busy times ahead!

Btw how did you calculate the tRFC 221, just based off 22/34 for tRAS/tRC?


----------



## anta777

224 or 208 or 240 your real tRFC


----------



## Audioboxer

anta777 said:


> 224 or 208 or 240 your real tRFC


Memory "autocorrects" to 240?


----------



## Dodgexander

Audioboxer said:


> Memory "autocorrects" to 240?


I think he said earlier that you increase or decrease trfc in steps of 16 and do not see performance benefits in-between.


----------



## anta777

221 autocorrect 208 or 224 (know only authors bios)


----------



## whocares7

Looks like Universal2 config caught some powering issues (Test 9/12 on the 3rd cycle) which 1usmus config (25 cycles) wasn't previously.
Increasing ClkDrvStr=40 fixed the issue.


----------



## MrHoof

whocares7 said:


> Looks like Universal2 config caught some powering issues (Test 9/12 on the 3rd cycle) which 1usmus config (25 cycles) wasn't previously.
> Increasing ClkDrvStr=40 fixed the issue.
> 
> View attachment 2527692


Yep had the same happening for me but errors in test 1, increasing ClkDrvStr 30 to 40 fixed it. Gonna run 30 now on purpose on the new Absolut cfg to see if it catches it too.

edit: Oh your running 1T DR too without setup timings so I am not the only one


----------



## Taraquin

anta777 said:


> *Taraquin*
> CL=CWL even
> CWL=CL-1 odd
> RAS=RC-RP
> RP=RCD
> WR=CL even 100% stable
> WTRL=RTP=WR/2
> WTRS=3(4)
> RCDWR=8
> SC=CCDS-3=1
> SCL=CCDL-3=2,3,4
> SD=DD
> RDRDSD/DD=4+RPRE-1
> WRWRSD/DD=4+WPRE-1
> RDWR=CL-CWL+5+WPRE
> WRRD=CWL-CL+4+RPRE
> tRFC ns convert timings, round up to the nearest divisible by 16.


So I tried this, changed WR/RTP from 10/5 to 16/8, RAS from 29 to 32, RC from 45 to 48, wtrl to 8 again, tRFC to 288 and I got slightly lower copy aida, 1ns higher, 2 sec slower dram calc, SOTTR gave me reboot, TM5 universal got loads of error 4. My bet is wtrl 8 don't work. Looser tRC and tWR/tRTP might account for lower performance. Guess I'm stuck :/


----------



## anta777

WTRL<WR
WTRL>=WR/2
WTRL>WTRS
this interval worked
RTP=WR/2(better variant)


----------



## Taraquin

anta777 said:


> WTRL<WR
> WTRL>=WR/2
> WTRL>WTRS
> this interval worked
> RTP=WR/2(better variant)


Yeah, I currently run wtrl 9 like you suggested, tried 8 after loosening other timings. Can try again later with wtrl at 9  Thx for reply!


----------



## Veii

*Anta*
I've worked with this tRFC interval too (being 16)
Concluded it as half clock, 1/4th, 1/8th, 1/16th
Started the same with you ~ see tTFC mini shenanigans sheet
The "full cycle check 32 Clk" 

But out of this i made changes to tRFC mini module
Math has to be done in NS and tRTPns fall into this

Sadly unsure about how 1usmus worked on calculator
But like mentioned in the PMs, my calculator always matched his alternative result
The "faster" one was around *5.8725 ish something there
A 1/4th + 1/8th + 1/16th cycle
* will tell you more about it end of this week, when i'm home

Experimented with this and conclusion was,
This 16ck (half cycle stepping) is an issue, because it is fixed clock
It makes sense to do the math on fixed tRC value
Why, check cycle check thing 
It was made reverse , and all adds up

Fixed value 16 doesn't work out always
Sometimes it's less
At least my sticking nose into this showed different results
But nobody told me about fixed values or 32 being "full cycle" how to scale tRFC down
It got up from nothing and matched correctly to what you state 

Sadly bellow this "made up" *6 math, it nevee worked
Discharge was too fast, and it always required tRP and tRAS to be correct
Try to scale down tRFC in the same stepping you end up basic flat timing
16-16-16-32-48 , then half is 24, 1/8th is 12
Scale down in 6,12,24 steps 

14-14-14-28-42, half is 21, 10.5
Scale down in 21 value steps 

Math looks absurd, but reverse checked result matched up
Please try


----------



## anta777

*Veii*
For me calculator 1usmus is less than nothing.
1usmus is nobody for me, he is not an authority for me.

tRFC does not depend on the set tRAS,tRP and tRC.
tRAS=44
tRP=20
tRC=64
or
tRAS=36
tRP=16
tRC=52


tRFC in this variants = same.
tRFC depend only voltage (samsung b-die) and chip.
During the update, at least 8 passes (tRASvendor + tRPvendor), when converting ns to clock cycles, we get a loss of accuracy of a maximum of 8*(1 + 1) = 16 clock ticks.
Therefore, you can get the correct tRFC like this:
Convert ns to ticks, round up to the nearest multiple of 8 and add 8.
In the worst case, we lose 8 clocks if at our frequency tRASvendor and tRPvendor ideally translate into clocks.

Who has nothing to do, he can play with the minimum tRFC value at different frequencies, trying to win these 8 clock cycles.
But it makes no sense to do this, since we have two unknowns -tRASvendor and tRPvendor.


----------



## MrHoof

MrHoof said:


> Yep had the same happening for me but errors in test 1, increasing ClkDrvStr 30 to 40 fixed it. Gonna run 30 now on purpose on the new Absolut cfg to see if it catches it too.


Yes it did and in about the same time 40mins.


----------



## PJVol

Taraquin said:


> wtrl to 8 again


WTRL 8 might be too low for these. I previously ran 4/12, but decided to give 3/10 a try.
Just finished testing and below turned out stable in both LMHz and 1usmus configs, even shaved 10mv off of it for fun


----------



## Veii

anta777 said:


> tRFC depend only voltage (samsung b-die) and chip.
> During the update, at least 8 passes (tRASvendor + tRPvendor), when converting ns to clock cycles, we get a loss of accuracy of a maximum of 8*(1 + 1) = 16 clock ticks.
> Therefore, you can get the correct tRFC like this:
> Convert ns to ticks, round up to the nearest multiple of 8 and add 8.
> In the worst case, we lose 8 clocks if at our frequency tRASvendor and tRPvendor ideally translate into clocks.
> 
> Who has nothing to do, he can play with the minimum tRFC value at different frequencies, trying to win these 8 clock cycles.
> But it makes no sense to do this, since we have two unknowns -tRASvendor and tRPvendor.


mmm~
Tracking testing, needs time i know
Problem i have with too low tRFC
Never saw it auto corrected by little amount
Either it worked, it errord or it got postponed and had a big latency increase
Or testing was too random between runs (perf results) ~ live-autocorrect

I read postponed up to 8* inside tREFI range, if it is being too short
This was my focus point for it.
People pushed too low timings, often my high one where faster. Don't run the "push everything as low as possible" mentality
Swap to tRASmin took time and is only recent work, because of slightly better bandwidth

Is it really worst case 8nCK and not whole tRFC doubled, if postponed ?
Couldn't find information by how much it gets postponed, only that it will and can not be time-broken 🤔


----------



## anta777

if you set it correctly, then there is a maximum loss of 8 clock cycles
if set below, it depends on what the BIOS will do


----------



## Melan

My humble PVB416G360C7K Hynix CJR. FCLK 1900 straight up refuses to boot regardless of settings so I just settled for 3733.
Passed universal-2 and absolute tm5 configs. Couldn't get tWR 16 and tRTP 8 to work though.


----------



## XPEHOPE3

KedarWolf said:


> In AIDA64 go to Help, Check for Updates, I think it downloads a new Bench.dll, noticeable improvement.


Whatever it downloads, it doesn't update bench.dll version (as can be seen from your screenshot). And Aida developers do not recommend comparing measurements across bench.dll versions. So, it's strange to see any improvements due to this.


----------



## KedarWolf

I use a stripped-down bloatware removed Windows 10 with a ton of services not needed disabled.

See here how I do it.









Optimize-Offline Guide - Windows Debloating Tool, Windows 1803, 1903, 19H2, 1909, 20H1 and LTSC 2019


All credit goes to GodHand and who wrote and maintains this script. And to @gdeliana who created the fork of Godhand' s Script we are using for...




forums.mydigitallife.net





This is my O/S after running four hours with MSI Afterburner running.

*Edit: The second pic is with VMWare uninstalled.*


----------



## decalruma

anta777 said:


> *kim nk*
> tRFC only depends memory chips and density.
> Samsung b-die and Hynix CJR/DJR still depend on voltage.
> You translate ns into ticks,
> round up to a multiple of 16.
> Then you test by adding or subtracting 16.
> We can put in bios tRC=64 tRAS=44 tRP=20 RRDS=6 FAW=40,
> but the minimum stable tRFC will not change from this,
> since these values are not used for tRFC.


question.
why is the 16?
I'm very curious


----------



## decalruma

Veii said:


> ked with this tRFC interval too (being 16)
> Concluded it as half clock, 1/4th, 1/8th, 1/16th
> Started the same with you ~ see tTFC mini shenanigans sheet
> The "full cycle check 32 Clk"
> 
> But out of this i made changes to tRFC mini module
> Math has to be done in NS and tRTPns fall into this
> 
> Sadly unsure about how 1usmus worked on calculator
> But like mentioned in the PMs, my calculator always matched his alterna





anta777 said:


> *Veii*
> For me calculator 1usmus is less than nothing.
> 1usmus is nobody for me, he is not an authority for me.
> 
> tRFC does not depend on the set tRAS,tRP and tRC.
> tRAS=44
> tRP=20
> tRC=64
> or
> tRAS=36
> tRP=16
> tRC=52
> 
> 
> tRFC in this variants = same.
> tRFC depend only voltage (samsung b-die) and chip.
> During the update, at least 8 passes (tRASvendor + tRPvendor), when converting ns to clock cycles, we get a loss of accuracy of a maximum of 8*(1 + 1) = 16 clock ticks.
> Therefore, you can get the correct tRFC like this:
> Convert ns to ticks, round up to the nearest multiple of 8 and add 8.
> In the worst case, we lose 8 clocks if at our frequency tRASvendor and tRPvendor ideally translate into clocks.
> 
> Who has nothing to do, he can play with the minimum tRFC value at different frequencies, trying to win these 8 clock cycles.
> But it makes no sense to do this, since we have two unknowns -tRASvendor and tRPvendor.


8*(1 + 1) ? what is 8? what is (1+1)?
"round up to the nearest multiple of 8 and add 8" -> for example, if I have 252 ticks after converting ns to ticks, the nearest multiple of 8 = 256 right?
and 256 add 8 = 264? is it correct tRFC?
but 264 is not the multiple of 16. my understanding must be wrong.
please correct this.


----------



## XPEHOPE3

@anta777 
Sorry for being late to comment. Probably too much incoming... First of all, thank you for coming here! Some of your comments are enlightening and mythbusting  Some are puzzling and raising questions  Hope you can find time to answer some of those at least to increase available English-language info about TM5

Anyway, the main questions are:

Did you have access to TM5 source code or studied its disassembly?
Is it possible for anyone (me) to buy TM5 source code from Serj? I thought to offer let's say 50k rubles. But then where would I find Serj? Doesn't seem like he is out there. The first thing I'd do would be to make it open source (via github) so that everyone (you, me, etc.) would see how good it is. And fix it (e.g. fix language, add checks for wrong test parameters, etc)
IIRC you were an "Intel guy", disliking memory OC on AMD platform. And now you come to this AMD thread  Did your opinion change? Or do you just want wider statistics for your new config?



anta777 said:


> 2.Errors in the tests themselves and you should have discovered them yourself long ago





anta777 said:


> Author tm5 allows mirrormovie to use the parameter 0=1,2,3,4, but in usmus-config use parameter=16384! - nonsens (test14).


You are correct, I could have discovered that!



Testmem support page said:


> *MirrorMove*
> ... *Parameter*, который может принимать значения *1,2,3,4* ...
> ...
> *MirrorMove128*
> ... *Parameter*, который может принимать значения от *0 и больше [0 and more]*. ...
> Соответственно, *Parameter* задает кол-во дополнительных полос (проходов) для заполнения всего блока. Если судить по времени выполнения перемещения, то, для Core2 (наверно, и других процессоров с старым режимом интерливинга) часло *510* вызывает наибольшие проблемы.


I guess 1usmus either misread the spec or meant to use MirrorMove128 which does allow Parameter > 4 even as example (510 in quote)



anta777 said:


> *1.* Author tm5 allows for pattern 2 param0 and param1 - max 8-digit hex number, but in usmus-config use 9-digit! - nonsens (tests 6,11,12,13).
> *2.* Testing Window Size (Mb)=880, but better max 1536.
> *3.* MirrorMove with Parameter=1 - devalues the test itself (test 3).


Well, I don't think it's possible (or easy) to be sure that those are errors from the official site alone.

The page doesn't say "Pattern Param0" or "Pattern Param1" are 4-byte values internally. Default config suggests that, but it's written nowhere in a strict manner (in style of Serj  ). Or am I *that* blind?
Should a bigger value be specified, from programming side of view there are several possibilities of what _can_ happen.


Spoiler: Nothing interesting here



"Pattern Param1" value data flow is like this: config->integral value->function call->use in function. Reading a value from string to integral is done via e.g. atoi, atol, atoll C standard library functions (if Serj did use C at all...). If _atoi_ or _atol_ were used, undefined behaviour for 1usmus_v3 config would be triggered. Usually it means different values would be used for each program run, or some specific unknown value (dependent on input). But Test 6 according to practice does have high specificity, so it can't be different values each run. Specific value, however, can't be guessed in this case, unless one debugs the program. If the value was read from config as an 8-byte (e.g. via _atoll_) then it's important whether the SimpleTest function expects an 8-byte or a 4-byte value for param1. If it expects 4-byte, 8-byte value is just truncated and hence one can just remove leading halfbyte from each offending params and get the same behaviour (e.g. Test 6 would still behave like it was with 1usmus_v3). Next, if param1 actually 8-byte but used in SimpleTest as a 4-byte value, it depends on the specific algorithm Serj used to do this.



Nothing about it on official site _explicitly _suggesting what value is better. I can only guess that larger value is required if subblocks of certain tests somehow fit into one of the caches otherwise. To be sure one would have to see the size calculation code or debug it... Can you elaborate on the reason why exactly larger is better here? If it's somehow cache dependent, would we need to enlarge it even more for upcoming 3D-cache processors?
Anyway, suggested value routinely prevents start for some users (maybe that's why 1usmus chose safer one) and your old config did include info about it in Russian. I think it's valuable to add such info in English to the new config.
Again, I don't see from official site why is this. Yes, it does say that Parameter defines number of test subblocks, and >1 means more problems for IMC and DDR. And Test 5 is MirrorMove with 4 subblocks, so that case is kinda covered by the config. Test 3 from my testing does have _some slight specificity_ to tRDWR/tWRRD problems, while Test 5 didn't (although for @Veii it also did). I have screens for tRDWR/tWRRD of 10/4, 10/6, 8/5 erring on Test 3, but 10/5 NOT erring on Test 3, and that was repeatable, and no Test 5 errors were involved.



anta777 said:


> Random patterns cannot be tied to specific errors, since they are random, this is their meaning.





Testmem support page said:


> Pattern Mode=1 - тип шаблона. 0 = постоянный, 1 = переменный, 2 = случайный [*Pattern type: 0 = constant, 1 =variable, 3 = random*]
> Для генерации шаблона в режиме 2 используется простая формула получения RND = Значение * Param0 + Param1 [*To generate pattern in mode 2 a simple formula is used for RND = "value" * Param0 + Param1*]


Well, that looks like pseudorandom with seeds fixed by config. I don't understand what "value" can mean here. Serj's writings are often incomplete or cryptic  That's why I'd like to see the code myself...
But if its' pseudorandom with fixed seeds, it means the stream of values is the same between runs, although since available memory is different, the streams get divided differently for subblocks.



anta777 said:


> Only Matrix, Interface, Addressing and Processor Controller errors can be detected.
> 
> 1.Matrix ("analog" timings): RCD,RP,RRDS,RRDL,FAW,RFC,REFI, part RAS,RC,WR - pattern 1,2 (conditionally).
> 2.Interface ("digital" timings): tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE - pattern 0 (conditionally).
> 3. Addressing : CMD, GDM - pattern 1.
> 4. Processor controller : freq, voltage, CWL - mirrormovie and mirrormovie128, in this case, the error itself will be detected at startup Refreshstable (the beginning of any SimpleTest).


That list doesn't include tertiary timings like tRDWR. Are they "hidden" in 4? Or do you mean they cannot be detected by TM5?



anta777 said:


> CL=CWL even
> CWL=CL-1 odd
> RAS=RC-RP
> RP=RCD
> WR=CL even 100% stable
> WTRL=RTP=WR/2
> WTRS=3(4)
> RCDWR=8
> SC=CCDS-3=1
> SCL=CCDL-3=2,3,4
> SD=DD
> RDRDSD/DD=4+RPRE-1
> WRWRSD/DD=4+WPRE-1
> RDWR=CL-CWL+5+WPRE
> WRRD=CWL-CL+4+RPRE
> tRFC ns convert timings, round up to the nearest divisible by 16.


Interesting, but is it complete and "for everyone"? E.g. you were saying about SD/DD being 1 for 2*8. Is it only for b-dies, or for Micron/Hynix also? Is it still valid for 2*16, 4*16 setups? For example, people established that e.g. RDWR for 4*8 should be higher than for 2*8 (for the same kit) by at least 1 cycle (or more in case of e.g. one @Audioboxer 's kit requiring RDWR 12) Your formulas don't depend on ranks and number of dimms.

E.g. here are my 1usmus_v3_25-stable (also y-cruncher and OCCT-stable) 16*4 setup. I will be running your config soon too!













SD/DD/RDWR/WRRD seem to be just by your rules with RPRE=1 and WPRE=3, but RDWR needs to be 1 tick higher to be stable. Also note tRFC=392 isn't divisible by 16, and 384 isn't stable. Am I the lucky one to get no wasted 8 cycles then? But 200+ns tRFC is meeeeh still. Although I'm yet to see anyone in the world to beat my Aida read latency on Ryzen with 16*4GB setup.


----------



## XPEHOPE3

decalruma said:


> 8*(1 + 1) ? what is 8? what is (1+1)?


8 is number of full RAM refreshes during that tRFC period. First "1" comes from tRASvendor loss of accuracy, second "1" comes from tRPvendor loss of accuracy. Both tRASvendor and tRPvendor are setup as nanoseconds (just like in XMP), not in cycles, so conversion to cycles and back might yield higher value. Difference in ns is no larger than 1 cycle. What I see somewhat suspicious here: is it really only 8 passes? If there's regularly more, adding 8 wouldn't be enough.


----------



## decalruma

XPEHOPE3 said:


> 8 is number of full RAM refreshes during that tRFC period. First "1" comes from tRASvendor loss of accuracy, second "1" comes from tRPvendor loss of accuracy. Both tRASvendor and tRPvendor are setup as nanoseconds (just like in XMP), not in cycles, so conversion to cycles and back might yield higher value. Difference in ns is no larger than 1 cycle. What I see somewhat suspicious here: is it really only 8 passes? If there's regularly more, adding 8 wouldn't be enough.


is the RAM you mean the dimm? chip? bank?
because x8 ram have 16banks, maybe bank is not the ram you mean.
8 dimms are for server level. so I think that dimm is not the ram you mean.
if it is chip, how is 2Rx8 RAM? does it also need only 8?
I have to more study that the tRASvendor and tRPvendor, I don't know what these mean T_T.. I'm go to search it on the google.


----------



## Audioboxer

224 seems ok I guess. Will have a look at SCLs now and see if OK at 2 then back to benching.


----------



## Taraquin

Melan said:


> My humble PVB416G360C7K Hynix CJR. FCLK 1900 straight up refuses to boot regardless of settings so I just settled for 3733.
> Passed universal-2 and absolute tm5 configs. Couldn't get tWR 16 and tRTP 8 to work though.
> View attachment 2527767


WR 18 / RTP 9 might work? On my 3600 1900 fclk was possible after agesa 1.2.0.0, try a newer bios? 478 or 508 tRFC might work?


----------



## Dodgexander

I'm so excited, it's only taken me a month or so but I'm finally down to tightening primary timings. I honestly don't know how you guys have timings so low! My tcl won't go lower than 14.

With next I tried
trcdrd 14
trcdwr 14

But fails test. I read here from anta777 and also tried
trcdrd 14
trcdwr 8

But it's also unstable.

Are there other settings that correspond to tuning these?

Voltage is 1.1375 vsoc and 1.55vdimm not sure I want to go higher even on these SR B dies. (Viper steels). vddp I have at 900.. Haven't really needed more. It's worth trying more vsoc?


----------



## Dodgexander

Audioboxer said:


> 224 seems ok I guess. Will have a look at SCLs now and see if OK at 2 then back to benching.


Out of interest, how did you determine your procODT, drive strength and RTT settings are best?


----------



## Taraquin

Dodgexander said:


> I'm so excited, it's only taken me a month or so but I'm finally down to tightening primary timings. I honestly don't know how you guys have timings so low! My tcl won't go lower than 14.
> 
> With next I tried
> trcdrd 14
> trcdwr 14
> 
> But fails test. I read here from anta777 and also tried
> trcdrd 14
> trcdwr 8
> 
> But it's also unstable.
> 
> Are there other settings that correspond to tuning these?
> 
> Voltage is 1.375 vsoc and 1.55vdimm not sure I want to go higher even on these SR B dies. (Viper steels). vddp I have at 900.. Haven't really needed more. It's worth trying more vsoc?


What ram speed are you on? 1.375 soc is insanely high, even too high for cpu voltage. For 3800 1.05-1.15v is enough for 99%, for 4000 1.1-1.2V. If anything I would try lower soc. I run 4000/2000 at 1.12v soc, 1.04v iod, 0.84v ccd and vddp.


----------



## Blameless

decalruma said:


> is the RAM you mean the dimm? chip? bank?


Yes.



decalruma said:


> I have to more study that the tRASvendor and tRPvendor, I don't know what these mean T_T.. I'm go to search it on the google.


tRAS/tRP vendor = the tRAS/tRP values programmed into the SPD, which are specified in nanoseconds.

*Edit: *This is interpretation was mistaken. Anta seems to be referencing other values.

Apparently, the effective minimum tRFC that will take, for whatever reason, is limited to eight times that minimum tRC (or tRP + tRAS). The rest of the formula is to account for rounding errors.

For example, if we open the SPD profile of our memory ICs, or look it up in a datasheet, and see that our presumptive K4A8G085WB-BCPB (the ICs used in most decent B-die) based modules have a tRC(min) of 47.06ns, this means that the absolute min tRFC that will take is 376.48 ns. If we are trying to run 1900MHz(3800MTs) on your memory, we divide that by 1.9 to convert the ns to clock cycles, which leaves us with ~198.15. The nearest multiple of eight, rounded up, is 200, and Anta is recommending adding another eight to account for any rounding errors in the conversion or imprecision in true memory clock. So, 208 cycles should be the minimum sensible value for 1900MHz B-die.

B-die will often take values like this, but the formula is pretty useless for most other ICs as it produces values far lower than the ICs will support.


----------



## TimeDrapery

Blameless said:


> Yes.
> 
> 
> 
> tRAS/tRP vendor = the tRAS/tRP values programmed into the SPD, which are specified in nanoseconds.
> 
> Apparently, the effective minimum tRFC that will take, for whatever reason, is limited to eight times the default (vendor programmed/SPD) minimum tRC (or tRAS + tRFC). The rest of the formula is to account for rounding errors.
> 
> For example, if we open the SPD profile of our memory ICs, or look it up in a datasheet, and see that our presumptive K4A8G085WB-BCPB (the ICs used in most decent B-die) based modules have a tRC(min) of 47.06ns, this means that the absolute min tRFC that will take is 376.48 ns. If we are trying to run 1900MHz(3800MTs) on your memory, we divide that by 1.9 to convert the ns to clock cycles, which leaves us with ~198.15. The nearest multiple of eight, rounded up, is 200, and Anta is recommending adding another eight to account for any rounding errors in the conversion or imprecision in true memory clock. So, 208 cycles should be the minimum sensible value for 1900MHz B-die.
> 
> B-die will often take values like this, but the formula is pretty useless for most other ICs as it produces values far lower than the ICs will support.


@Blameless 

This is a really really excellent explanation, thank you for taking your time to post this


----------



## Taraquin

XPEHOPE3 said:


> @anta777
> But 200+ns tRFC is meeeeh still. Although I'm yet to see anyone in the world to beat my Aida read latency on Ryzen with 16*4GB setup.


Wasn`t it tRFC in ns Anta777 said? Then 387 would be closest. Does that work? 376 or 403 (194ns or 208ns). Try 403 and see if performance is the same? If what Anta says is correct (which I assume) then 394 and 403 should give same performance


----------



## Taraquin

Blameless said:


> Yes.
> 
> 
> 
> tRAS/tRP vendor = the tRAS/tRP values programmed into the SPD, which are specified in nanoseconds.
> 
> Apparently, the effective minimum tRFC that will take, for whatever reason, is limited to eight times the default (vendor programmed/SPD) minimum tRC (or tRP + tRAS). The rest of the formula is to account for rounding errors.
> 
> For example, if we open the SPD profile of our memory ICs, or look it up in a datasheet, and see that our presumptive K4A8G085WB-BCPB (the ICs used in most decent B-die) based modules have a tRC(min) of 47.06ns, this means that the absolute min tRFC that will take is 376.48 ns. If we are trying to run 1900MHz(3800MTs) on your memory, we divide that by 1.9 to convert the ns to clock cycles, which leaves us with ~198.15. The nearest multiple of eight, rounded up, is 200, and Anta is recommending adding another eight to account for any rounding errors in the conversion or imprecision in true memory clock. So, 208 cycles should be the minimum sensible value for 1900MHz B-die.
> 
> B-die will often take values like this, but the formula is pretty useless for most other ICs as it produces values far lower than the ICs will support.


Isn`t it the other way around converting to ns? On my setup I currently use tRFC 288 which reads in Zentimings as 144ns due to ramspeed being 4000. Isn`t tRFC formula ns/2000xram speed?


----------



## Audioboxer

Dodgexander said:


> Out of interest, how did you determine your procODT, drive strength and RTT settings are best?


ProcODT from mobo auto with these DR sticks and a B550 Unify X has been 36.9. Originally I was running CsOdtDrvStr at 30 based on 40/20/30/20, a fairly common combo, and unless I've remembered this incorrectly early on when learning about memory I believed OdtDrvStr goes up ProcODT should come down a notch or two. So 34.3 was decided on quite early and it just happened to "stick". As you can see from dom he too gets good results with 34.3 on the same set of memory as me.

Rtt's were based off another popular combo, 6/3/3. These DR sticks like to run RttPark 1 on auto, but that is with GDM enabled. With GDM disabled it seems better to try and run a weaker Park. I know I've been advised by Veii and mongoled the higher VDIMM goes the better it is to try and get Park nearer to 4~7. IIRC 3 is on the edge of "acceptable" at 1.55v. I can boot up to 6 at 3800, so I may try 4~5 on stability testing.

RttNom seems a bit more temperamental and harder to nail down. I've witnessed tPHYRDL behaviour change negatively with too weak an RttNom. At tCL14 I was running 5/6, but for whatever reason with this memory on an MSI board if I run uneven tCLs tPHYRDL 26/26 becomes easier to run lol. So we're back to 7, the weakest. I think Nom is mostly a case of run the weakest you can.

The DrvStr's are something I understand the least. Though ClkDrvStr has become pretty clear as the most important to try and stabilise 1T with GDM disabled. 40 is basically the sweet spot. If you're lucky 30 might work. I haven't really tested it. As I said I had OdtDrvStr at 30 for ages, but dropping down to 24 has been fine. CkeDrvStr was on 20 for ages, but it went to 24 as part of my tPHYRDL testing at tCL14. Seemed to help stabilise 28/28. Now that I'm on tCL13 and locked at 26/26, I might try dropping it to 20 again. 24 seems pretty popular though on many DR setups.

So best is pretty much ymmv. Gotta play around. I'd say dealing with the "right hand side" of ZenTimings when memory OCing is incredibly time consuming and as much as there are "plug and play" settings based on accrued knowledge, just going 6/3/3 and 40/20/30/20 is no guarantee for you at all. Plus even if it were to work it might not be optimal for your sticks. It's my understanding if you can weaken resistances or DrvStr that may help with heat and/or even timings elsewhere.

Veii explained it to me like "balancing" a dam. If you don't have the dam balanced either too much water or too little water is the result, which in turn, means unstable memory. I also think of it like balancing plates, gotta keep them all spinning, if any one plate drops its game over  Unstable RAM is unstable RAM, doesn't matter if it's a single error. I OC to daily, not bench, so there is an absolute no error acceptable principle for me, within reason. I'm obviously not running TM5/y-cruncher/OCCT for 50 hours in a row. Just hoping I can trust reasonable stability test timeframes combined with real-world usage over weeks/months showing no crashes/weirdness.


----------



## Blameless

XPEHOPE3 said:


> Interesting, but is it complete and "for everyone"? E.g. you were saying about SD/DD being 1 for 2*8. Is it only for b-dies, or for Micron/Hynix also? Is it still valid for 2*16, 4*16 setups? For example, people established that e.g. RDWR for 4*8 should be higher than for 2*8 (for the same kit) by at least 1 cycle (or more in case of e.g. one @Audioboxer 's kit requiring RDWR 12) Your formulas don't depend on ranks and number of dimms.


In practice, that formula only applies to 8Gb Samsung B-die ICs and maybe a few (in DDR4 terms) ancient 4Gb ICs from various vendors. This platform may register the calculated values and accurately set them for any IC, but other ICs simply cannot tolerate such tight tRFC, won't have time to charge their cells, and probably won't even POST/pass training.

In those cases, find the lowest tRFC that will train and round up to the nearest multiple of eight, then add eight more for a bit of margin and use that as your floor for testing.



Taraquin said:


> Isn`t it the other way around converting to ns?


Yes, but I was converting to cycles from ns.



Taraquin said:


> On my setup I currently use tRFC 288 which reads in Zentimings as 144ns due to ramspeed being 4000. Isn`t tRFC formula ns/2000xram speed?


Since we know ns is a billionth of a second we can just multiply or divide ns or cycles by the GHz of the actual memory clock, which is what I personally find easiest.


----------



## anta777

*Blameless*
tRASvendor and tRPvendor - this is not what we see in SPD.
They are much smaller.
Read the works of different authors.

You need to take the meaning tRFC in ns from practice since we do not know tRASvendor and tRPvendor.


----------



## anta777

*X....*
I had access to the author tm5 - Serj.
We corresponded and he answered my questions.
i didn't like amd because of one person- 1usmus.
At the moment I do not like neither intel nor amd.
I'm waiting for new processors.
9-digit - 1usmus had to ask the author.
Serj did use assembler.
if more memory is allocated per thread than testing window size
then you have to use AWE.
it is not associated with the processor cache
Mirrormovie with parameter=1 - I don't see the point
Serj


Spoiler: Serj about pattern 2



# 2 - generating a random number from (!!!) param0 and param1. If there are 0 - nonsense will come out
Param0 defines the initial values for the block template, and Param1 defines their modification within the block fill with the template.
RND generation is formed according to the classic version - OLD * Param0 with resettling to the bit grid. For example, there was a number 1.5T, Param0 = 2, after multiplication, you get 3T,
but only 2T fits into the bit grid, so it becomes 1T. The more Param0, the more sharply (more bits) changes in neighboring blocks. With Param0 = 1, there will actually be one and
the same, if 0 - there will be a painting of 0.
Param1 simply adds itself to each new value of the template, with the same clipping. If set to 0 - there will be no modification

Modes 0 and 1 ignore the settings of Param0,1


RDWR=CL-CWL+5+WPRE

SD- only dualrank
DD-only 4 dimm
rdwr does not depend on the number of planks
if there is an addiction,
All questions - to the bios authors

Your tRFC=280 ticks.


----------



## decalruma

Blameless said:


> Yes.
> 
> 
> 
> tRAS/tRP vendor = the tRAS/tRP values programmed into the SPD, which are specified in nanoseconds.
> 
> Apparently, the effective minimum tRFC that will take, for whatever reason, is limited to eight times the default (vendor programmed/SPD) minimum tRC (or tRP + tRAS). The rest of the formula is to account for rounding errors.
> 
> For example, if we open the SPD profile of our memory ICs, or look it up in a datasheet, and see that our presumptive K4A8G085WB-BCPB (the ICs used in most decent B-die) based modules have a tRC(min) of 47.06ns, this means that the absolute min tRFC that will take is 376.48 ns. If we are trying to run 1900MHz(3800MTs) on your memory, we divide that by 1.9 to convert the ns to clock cycles, which leaves us with ~198.15. The nearest multiple of eight, rounded up, is 200, and Anta is recommending adding another eight to account for any rounding errors in the conversion or imprecision in true memory clock. So, 208 cycles should be the minimum sensible value for 1900MHz B-die.
> 
> B-die will often take values like this, but the formula is pretty useless for most other ICs as it produces values far lower than the ICs will support.


thank you for your explanation which is very understandable to me 
but.
I know that the tRFC can be reduced by more inputing vDimm.
how about this?
it is posible for an user to read just 1.2v JEDEC Spec and XMP spec in the SPD.
we are playing overclocking basically with more inputing vDimm than the SPD spec.
I dont understand why is the 8 clocks.
I think that a type of clock fomula is not applicable to the analog timings which operate in nanosecond and are affected by vDimm because clock is not nanosecond and can vary with any vDimm.
the more increase the vdimm, the more reduce the tRFC whatever is the fomula.


----------



## mongoled

TimeDrapery said:


> Some day, I hope to be an authority for @anta777 😂😂😂😂😂
> 
> Thanks again for sharing your wealth of experience and knowledge...
> 
> You act like a **ing douchebag though and that's hardly an opinion... you're awful lucky that the endeavors you choose to dedicate yourself to keep you behind a monitor as I'd slap the ****ing dog ** out of you for having such a piss poor attitude were we to meet in-person
> 
> Then I'd bother you with questions about memory OC 😂😂😂😂😂
> 
> Again, thanks for your efforts and your time!
> 
> @mongoled
> 
> Don't worry dude, I care about your opinion and you can continue writing to me... Unless I get banned 😂😂😂😂😂


Not much more I will say apart from thanks for understanding, I would like to write loads but will leave it to the one sentance below

If there was one thing I could change in the way we are brought up its understanding what the ego is is the most fundamental thing we should be taught from the earliest age possible.


----------



## anta777

*decalruma*
tRFC only samsung b-die and Hynix CJR/DJR depend VDIMM


----------



## Blameless

anta777 said:


> *Blameless*
> tRASvendor and tRPvendor - this is not what we see in SPD.
> They are much smaller.
> Read the works of different authors.
> 
> You need to take the meaning tRFC in ns from practice since we do not know tRASvendor and tRPvendor.


In my experience, the SPD values usually match datasheet values for the ICs used. Module maker adjustments are usually, though certainly not always, confined to XMP.

If the datasheet values aren't what you're referring to, can you elaborate? Have any recommended reading?



decalruma said:


> I know that the tRFC can be reduced by more inputing vDimm.


There are a number of variables that can stabilize a flaky tRFC value and even within a given IC family there is a fair bit of per-sample variation in what the minimum stable tRFC will be. However, there is still a very strong trend that is dictated by IC.



decalruma said:


> it is posible for an user to read just 1.2v JEDEC Spec and XMP spec in the SPD.


I would think that the SPD value would usually be reflective of the vendor values mentioned, but Anta's statements make me unsure of that.

XMP is even more arbitrary and is almost certainly not a good source for anything the IC vendor would have specified.



decalruma said:


> I dont understand why is the 8 clocks.


You'll have to ask Anta for clarification.

Apparently values that aren't multiples of eight will be rounded. I'm not sure why this would be, but eight is plenty granular enough already...you'll never be able to accurately measure the performance difference resulting from tRFC +/-8 cycles because whatever it is, it's already dwarfed by things like training variance.



decalruma said:


> I think that a type of clock fomula is not applicable to the analog timings which operate in nanosecond and are affected by vDimm because clock is not nanosecond and can vary with any vDimm.
> the more increase the vdimm, the more reduce the tRFC whatever is the fomula.


Clocks vs. nanoseconds is neither here nor there. If the vendor settings mandate certain parameters in ns, those will be converted to clocks, because a clock strobe is how everything is timed in practice.

If the formula is reflective of a floor below which values won't take (I am not clear on this @anta777 ), then any other factors that might stabilize lower settings are moot.

If the formula is just a guideline, it can still be a good guideline, even if there are outliers where values slightly below it will occasionally work.


----------



## anta777

For example


https://www.cs.utah.edu/~rajeev/pubs/shevgoor-phd.pdf




https://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf


+
the entire list of references


----------



## XPEHOPE3

Blameless said:


> For example, if we open the SPD profile of our memory ICs, or look it up in a datasheet, and see that our presumptive K4A8G085WB-BCPB (the ICs used in most decent B-die) based modules have a tRC(min) of 47.06ns


And now people people would quote your incorrect understanding... That JEDEC tRCs are not what anta777 was talking about. He told those timings are not visible by the user while that tRC is.
Also Micron's datasheet has the same tRC values but in practice min tRFC is different, so yes, the formula in _the way you understood it_, does not apply to Microns.



anta777 said:


> Spoiler: Serj about pattern 2
> 
> 
> 
> # 2 - generating a random number from (!!!) param0 and param1. If there are 0 - nonsense will come out
> Param0 defines the initial values for the block template, and Param1 defines their modification within the block fill with the template.
> RND generation is formed according to the classic version - OLD * Param0 with resettling to the bit grid. For example, there was a number 1.5T, Param0 = 2, after multiplication, you get 3T,
> but only 2T fits into the bit grid, so it becomes 1T. The more Param0, the more sharply (more bits) changes in neighboring blocks. With Param0 = 1, there will actually be one and
> the same, if 0 - there will be a painting of 0.
> Param1 simply adds itself to each new value of the template, with the same clipping. If set to 0 - there will be no modification
> 
> Modes 0 and 1 ignore the settings of Param0,1


Then I'm correct, values are pseudorandom with fixed seeds and the same on each run, hence can potentially be connected to reasons of errors. In a sense it's even not random enough in your config because params are not coprime (both are divisible by 0x11111111). So the stream of values probably loops around (repeats itself) very fast for your test1. Default config uses coprime values 0x14AAB7 and 0x6E72A941.



anta777 said:


> Your tRFC=280 ticks.


If I just input any value <= 384 ticks I get TM5 errors on any config. The sooner the less the value. Do you mean I have to change something (e.g. from the right side of ZenTimings) together with tRFC to make it stable?


----------



## anta777

RTP=8


----------



## Melan

Taraquin said:


> WR 18 / RTP 9 might work? On my 3600 1900 fclk was possible after agesa 1.2.0.0, try a newer bios? 478 or 508 tRFC might work?


It is already the latest BIOS. 1900 FCLK is just a no go on this particular 3600. Maybe I'll win the lottery with Zen 3D 
496 tRFC is the closest one to 262ns which divides evenly by 16. I'll try tWR 18 and tRTP 9 later, but current timings so far were the only ones which didn't require me going into rabbit hole of resistances.


----------



## Blameless

XPEHOPE3 said:


> And now people people would quote your incorrect understanding... That JEDEC tRCs are not what anta777 was talking about. He told those timings are not visible by the user while that tRC is.


This is one of the documents Anta's linked me to -- https://user.eng.umd.edu/~blj/papers/memsys2017.pdf

He seems to be referencing undocumented minimum values that would require insider technical information or elaborate experimentation. Absent someone documenting these values, the JEDEC values, or your own tests, are the best you're going to get.

I updated my post to highlight my misinterpretation.



XPEHOPE3 said:


> Also Micron's datasheet has the same tRC values but in practice min tRFC is different, so yes, the formula in _the way you understood it_, does not apply to Microns.


The formula wouldn't apply to Micron regardless, because any of the "vendor" minimum values are, perforce, going to be _less_ than the JEDEC spec, usually by a long shot. If plugging in JEDEC values result in a tRFC that's too low (and it does, for almost anything that's not 8Gb B-die), plugging in the true minimum values is going to result in something that's _way_ too low.



XPEHOPE3 said:


> If I just input any value <= 384 ticks I get TM5 errors on any config. The sooner the less the value.


280 cycles @ 1933MHz is never going to work on your Micron/Hynix stuff. Your current tRFC settings are already pretty tight.


----------



## Audioboxer

Audioboxer said:


> 224 seems ok I guess. Will have a look at SCLs now and see if OK at 2 then back to benching.












SCLs at 2 are fine, as is VDDP back down to 0.9v. Guess up next is benching/static OC with benching.


----------



## anta777

*Blameless*
I think memory X... - samsung b-die.


----------



## XPEHOPE3

anta777 said:


> RTP=8


I tried that setting alone (w/o changing tRFC) previously and it gave worse AIDA measurements. I can try to use it together with tRFC later. Meanwhile your config seems to take enormous time with 1750 % (for 5600x, as you advised) and 64GB RAM:







~1h for just 5 tests


----------



## Blameless

anta777 said:


> *Blameless*
> I think memory X... - samsung b-die.


If it's Samsung B-die it should definitely be doing way tighter tRFC without issue.

F4-3200C14*D*-16GVK is Samsung B-die, but I think F4-3200C14-16GVK is Hynix.


----------



## XPEHOPE3

@Blameless Thaiphoon burner says it's B-die. As well as kit cost)) and 14-flat timings


----------



## Blameless

XPEHOPE3 said:


> @Blameless Thaiphoon burner says it's B-die. As well as kit cost)) and 14-flat timings


My mistake then.

Odd that you're having difficulty reducing tRFC. Maybe you do need to reduce tRAS and tRC...
_
Edit:_ It's not inconceivable that you just have a weak IC somewhere. You could try pulling one DIMM at a time to see if a significantly lower tRFC value will train correctly.


----------



## SneakySloth

So I tried the Abolute profile by Anta and everything seemed stable until I put my usual GPU load on the system while the memory testing is happening. As soon as I did that, errors popped up within 15 minutes.

@anta777 

Maybe running a gpu load with the new profile should still be a recommendation for anyone who's not on water cooling? A high GPU load + tm5 absolute gives errors but without gpu load I don't get any errors.

I toned down my TRFC by 16 (256 -> 272) and the temperature related errors are gone. Currently running with 2500% coverage and on the 7th cycle without any errors with 3 hours of GPU load mixed in.


----------



## anta777

It is logical.
At least at the last stage of testing and selection of primary timings.


----------



## SneakySloth

I might try and see if the VDIMM can be reduced further now that my TRFC is a bit loose but this should be good for now. This is with coverage changed to 2500% in the config.


----------



## anta777

Samsung B-Die
tRFC(approximately):
1.20V-211ns
1.30V-178ns
1.35V-160ns
1.40V-150ns
1.45V-140ns
1.50V-136ns
1.55V-120ns
1.60V-110ns


----------



## XPEHOPE3

Blameless said:


> Maybe you do need to reduce tRAS and tRC


That also gives errors. 32-48 is the lowest stable for me at this memclk and powering.



anta777 said:


> Samsung B-Die
> tRFC(approximately):


So you are saying it doesn't depend on other voltages/resistances and planks?


----------



## Audioboxer

SneakySloth said:


> So I tried the Abolute profile by Anta and everything seemed stable until I put my usual GPU load on the system while the memory testing is happening. As soon as I did that, errors popped up within 15 minutes.
> 
> @anta777
> 
> *Maybe running a gpu load with the new profile should still be a recommendation for anyone who's not on water cooling?* A high GPU load + tm5 absolute gives errors but without gpu load I don't get any errors.
> 
> I toned down my TRFC by 16 (256 -> 272) and the temperature related errors are gone. Currently running with 2500% coverage and on the 7th cycle without any errors with 3 hours of GPU load mixed in.


Watercooling is much like aircooling, temps go up too once the GPU is dumping in heat lol. It's just if your watercooling loop is setup well you're maybe talking RAM going from 31~32 degrees up to 34~38 degrees during gaming. Depending on your water temp, GPU output and fan curve.

Anything in the 30s with b-die is going to be good. If you've added memory to a loop that already runs quite hot then I would say you should really keep an eye on memory temps once the GPU is dumping out heat.

Only time it might be independent of each other is if your GPU is in a loop but RAM is on aircooling. Then your GPU is unlikely to have as big an impact. I guess this is probably the position most people are in and what you meant. Very few of us are watercooling the RAM as well lol.


----------



## anta777

*Х...*
tRFC only samsung b-die and Hynix CJR/DJR depend VDIMM
I am writing for the third time.


----------



## Blameless

XPEHOPE3 said:


> That also gives errors. 32-48 is the lowest stable for me at this memclk and powering.


Was a long shot. Minimum tRFC shouldn't be affected much by other timings, but most of the B-die I've used could do tRAS=tRCD+tRTP...my Patriots do 22 tRAS and 36 tRC at ~1800.

Is your motherboard T-topology? If so, I wonder if that could be impacting things.

Anyway, you could just have a weak stick/IC. Might be worth trying one DIMM at a time with tighter tRFC, just to rule things out.


----------



## anta777

tRAS=48
tRC=64
tRFC=140 ns
tRAS=22
tRC=36
tRFC=140 ns


----------



## XPEHOPE3

Here are your 3 quotes. Only the third quote says "VDIMM" not just "voltage". Anyway, this doesn't explain why can't I lower tRFC at 1.55 VDIMM for B-dies. Something else also matters then like what @Blameless says about 1 bad DIMM.


anta777 said:


> *kim nk*
> tRFC only depends memory chips and density.
> Samsung b-die and Hynix CJR/DJR still depend on voltage.





anta777 said:


> tRFC depend only voltage (samsung b-die) and chip.





anta777 said:


> *Х...*
> tRFC only samsung b-die and Hynix CJR/DJR depend VDIMM
> I am writing for the third time.


----------



## Blameless

TimeDrapery said:


> Most especially those called, "MR6VrefDQ Control" and "CPU Vref Training Seed Control"? Considering they're found under "AMD CBS" I presume they take input in hexadecimal... What good are they?





Blameless said:


> On my MSI boards they are listed as setup times, the first one with a range of 0-127 and the other with a range of 0-255, in decimal, but I've seen other boards list them differently and want input in hex...MR6 is 7-bits long and the other evidently 8-bits so how that's translated should be immaterial.
> 
> Haven't played with them much, and didn't notice much when I did. Might investigate them further at some point.


Took a look at MR6VrefDQ again and it's actually pretty straightforward. The value, hex or decimal, is a direct conversion from the binary M6[5:0] register values for the vREF calibration %.

Take a look at pages 116-123 here: https://www.micron.com/-/media/clie...ucts/data-sheet/dram/ddr4/16gb_ddr4_sdram.pdf

...and pages 13-14 here: https://media-www.micron.com/-/medi...df?la=en&rev=d58bc222192d411aae066b2577a12677

You can use this voltage divider calculator to figure our what voltage you want to plug into the formula on page 14 of the second document in order to get the reference value for table 37 in the first document.

Stick your true vDIMM in the first box, your RTT NOM value in the second, and the AddCmd output driver impedance in the third box. Take the output voltage it calculates, subtract it from vDIMM, divide that by two, then add the output voltage again to get the target vCENT_DQ. Now divide that by your vDIMM to get the vREFDQ%, which is what MR6[5:0] sets.

On that table 37 find the closest percentage and the look at the "Range 1" register value. For example, if you came up with 0.819 or 81.9%, you'd find 82.10% (the closest on the table) which is binary 100010, hex 22, or dec 34.

On my Gigabyte boards, this field is hex, so I'd use 22. On my MSI boards this field is decimal so I'd use 34. On my ASRock boards this setting is absent, so I have to rely on the auto detection, which should work perfectly fine if my ODT and drive strength settings are set correctly.

*Edit:* you can also select the 'Range 2' values in table 37 by putting adding a seventh bit to the front of the the binary number. There is very little reason to do this, however, as 'Range 1' is intended for module based setups and should cover all sensible settings. However, there may be some outliers.

*Edit 2:* Ran into some issues with setting these values on my MSI board. I'm not 100% certain yet, but I think MSI is flipping the endianness of the binary register values. I was trying to set 66.5%, which should be 1010 in binary or 10 in decimal, but this value resulted in a no post situation. I tried a few other random settings, some of which would post, some of which would not. Then, out of curiosity I took the whole seven-bit variable 0001010 and reversed it to 101000 which is 40 decimal and this figure works exactly as expected.


----------



## anta777

*X...*
voltage=VDIMM, I couldn't even think about anything else


----------



## Taraquin

anta777: Finally got around and tried your settings again with wtrl 9, wtrl 3 worked so changed to that aswell. I never understood how to calculate RPRE and WPRE so I left all the SD, DD etc on auto. How do I find\calculate RPRE\WPRE?

Compared to my other setup of tRAS 29, tRC 45, tWR 10 and TRTP 5 aida is similar. Same latency, but lost 0,5MB\s read. Dram calc test from your "nemesis" 1usmus got 1,7sec slower and SOTTR lost 3fps CPU avg which I guess is within margin of error. Looser WR\RTP and RC didn`t affect performance that much, only the dram calc test took a slight hit. I was surprised the difference wasn`t larger, but the timings might work better together with your suggestions  









Thank your for the help so far


----------



## coelacanth

anta777 said:


> Samsung B-Die
> tRFC(approximately):
> 1.20V-211ns
> 1.30V-178ns
> 1.35V-160ns
> 1.40V-150ns
> 1.45V-140ns
> 1.50V-136ns
> 1.55V-120ns
> 1.60V-110ns


I have a G.Skill F4-3800C16D-32GTZN (B-die) kit. I'm running it at 3600MT at 1.35V 16-16-16-16-36-52 (tCL-tRCDWR-tRCDRD-tRP-tRAS-tRC). On Auto tRFC tRFC2 and tRFC4 are 630 468 288. Based on the ranges you listed, I should be able to lower tRFC to 416 (231.111 ns) or less without touching the voltage (currently 1.35V)? With tRFC at 312 that would be 173.333 ns, so could I get it that low while still remaining at 1.35V?

Thank you.


----------



## anta777

*Taraquin*
tCKE=1 for beauty
WR=10 and RTP=5 if stable, then leave it that way
1usmus very far to "nemesis"


----------



## anta777

*coelacanth*
What's the problem
expose and check


----------



## TimeDrapery

mongoled said:


> Not much more I will say apart from thanks for understanding, I would like to write loads but will leave it to the one sentance below
> 
> If there was one thing I could change in the way we are brought up its understanding what the ego is is the most fundamental thing we should be taught from the earliest age possible.


@mongoled

I agree... the trouble (in my eyes) lies in that most people have such difficulty with letting go of ego/self due to suffering because they feel they're unique and separate from what they experience and perceive when "in reality"... "🎶 As a descendant of the stars, it's only right that I become one 🎶" 😂😂😂😂😂



Blameless said:


> Took a look at MR6VrefDQ again and it's actually pretty straightforward. The value, hex or decimal, is a direct conversion from the binary M6[5:0] register values for the vREF calibration %.
> 
> Take a look at page 118 here: https://www.micron.com/-/media/clie...ucts/data-sheet/dram/ddr4/16gb_ddr4_sdram.pdf
> 
> ...and page 13 here: https://media-www.micron.com/-/medi...df?la=en&rev=d58bc222192d411aae066b2577a12677
> 
> You can use this voltage divider calculator to figure our what voltage you want to plug into the formula on page 14 of the second document in order to get the reference value for table 37 in the first document.
> 
> Stick your true vDIMM in the first box, your RTT NOM value in the second, and the AddCmd output driver impedance, in the third box. Take the output voltage it calculates, subtract it from vDIMM, divide that by two, then add the output voltage again to get the target vCENT_DQ. Now divide that by your vDIMM to get the vREFDQ%, which is what MR6[5:0] sets.
> 
> On that table 37 find the closest percentage and the look at the "Range 1" register value. For example, if you came up with 0.819 or 81.9%, you'd find 82.10% (the closest on the table) which is binary 100010, hex 22, or dec 34.
> 
> On my Gigabyte boards, this field is hex, so I'd use 22. On my MSI boards this field is decimal so I'd use 34. On my ASRock boards this setting is absent, so I have to rely on the auto detection, which should work perfectly fine if my ODT and drive strength settings are set correctly.


@Blameless 

*You rock*

I'm gonna dig in on the docs you referenced, do the maths using the calc you linked, and see what comes out...

These ”esoteric" / "fine grained" settings are what I believe bring about a great OC, thanks again for taking your time to help me learn more about how this all works!


----------



## Enferlain

Can I treat this the same way ocwise as if I was just using a single kit? They have the same model number on the sticks


----------



## TimeDrapery

Enferlain said:


> View attachment 2527870
> 
> 
> Can I treat this the same way ocwise as if I was just using a single kit? They have the same model number on the sticks


You could try to, your best bet though is to bin the DIMMs individually and treat the four as one kit that performs at the level of the worst binned DIMM


----------



## XPEHOPE3

XPEHOPE3 said:


> Meanwhile your config seems to take enormous time with 1750 % (for 5600x, as you advised) and 64GB RAM:


It appeared to take only slightly less time than 1usmus_v3 (6:12 vs 6:31):








I also mined Ethereum in parallel, so there was some load on GPU (56° and 68° on hot spot).

Cycles took 2:00, 2:05 and 2:07 times.


----------



## Enferlain

TimeDrapery said:


> You could try to, your best bet though is to bin the DIMMs individually and treat the four as one kit that performs at the level of the worst binned DIMM


Yeah I think this might have been too ambitious for a first try










I think the sticks went up to around 63c but I was afk when it crashed.

If I change to 14 14 14 14 it doesn't boot, if I change cad to 24 24 20 24 it doesn't boot, if I put rttnom on disable it doesn't boot, feels like current settings are hair away from not booting as well. I'll mess around with cad values a bit and see if anything improves if not then it's timings again


----------



## domdtxdissar

In other shocking news

*AMD: Windows 11 Slows Our CPUs Up To 15%, Patch Coming
*
AMD has announced that all of its WIndows 11-compatible processors can suffer from reduced performance in some applications when used with the new operating system, with extreme outliers in eSports gaming titles dropping by up to 10–15%. For applications, AMD says that the performance impact weighs in at 3–5%. A software update _and_ a Windows Update are in the works to address the issues, with both expected to arrive in October 2021 (this month).

The errors impact every Ryzen CPU supported in Windows 11. That means all Zen+, Zen 2 and Zen 3 CPUs that comprise the Ryzen 2000, Ryzen 3000, Ryzen 4000, and Ryzen 5000 processors are impacted. In addition, select AMD EPYC processors for data centers, along with some newer Athlon chips, are also impacted. You can see the full list here, but suffice it to say that every AMD chip on our Best CPUs for gaming list is impacted.



umeng2002 said:


> Look between the lines. MS has a "new" OS launching at the same time as Alder Lake with scheduler enhancements and everything in order make sure it works well. Meanwhile when AMD releases FX or Zen CPUs, MS is like, "yeah we'll get around to updating the scheduler a little bit in a few months... idk... we're pretty busy making sure Candy Crush works well on UWP."


Indeed


----------



## Enferlain

domdtxdissar said:


> In other shocking news
> 
> *AMD: Windows 11 Slows Our CPUs Up To 15%, Patch Coming
> *
> AMD has announced that all of its WIndows 11-compatible processors can suffer from reduced performance in some applications when used with the new operating system, with extreme outliers in eSports gaming titles dropping by up to 10–15%. For applications, AMD says that the performance impact weighs in at 3–5%. A software update _and_ a Windows Update are in the works to address the issues, with both expected to arrive in October 2021 (this month).
> 
> The errors impact every Ryzen CPU supported in Windows 11. That means all Zen+, Zen 2 and Zen 3 CPUs that comprise the Ryzen 2000, Ryzen 3000, Ryzen 4000, and Ryzen 5000 processors are impacted. In addition, select AMD EPYC processors for data centers, along with some newer Athlon chips, are also impacted. You can see the full list here, but suffice it to say that every AMD chip on our Best CPUs for gaming list is impacted.
> 
> 
> 
> Indeed


Basically my guess about inconsistent ****ty cb scores and stuttering and other random **** being because of win11 was right PogU (and yet I still spent weeks messing around with pbo)


----------



## Melan

Considering you've installed a beta OS, I'm not sure why you were surprised. This bug was there for a while and calling it "shocking" is just click bait at this point.
Tbh you're not even supposed to get the update notification if you're on AMD right now.
There's no need to post about it here. The appropriate thread is in the news section.


----------



## domdtxdissar

Melan said:


> Considering you've installed a beta OS, I'm not sure why you were surprised. This bug was there for a while and calling it "shocking" is just click bait at this point.
> Tbh you're not even supposed to get the update notification if you're on AMD right now.
> There's no need to post about it here. The appropriate thread is in the news section.


We have been discussing the L3 bandwidth numbers in AIda64 for many months now in this very thread, this is a confirmation for what we were seeing. (the fault was win11 not aida)
It also don't matter, but I'm running windows 10. (changed back from 11 since i didn't like the layout/beta testing)

And who are you exactly, telling anyone what they should and shouldn't be posting in this thread ? If im not mistaken, this is your very first post in here (?), way to make an entrance i guess lol 

_edit_
Try clicking the quote from umeng2002 and you will get linked right back to the discussion we had about this a few days ago.


----------



## Dodgexander

Taraquin said:


> What ram speed are you on? 1.375 soc is insanely high, even too high for cpu voltage. For 3800 1.05-1.15v is enough for 99%, for 4000 1.1-1.2V. If anything I would try lower soc. I run 4000/2000 at 1.12v soc, 1.04v iod, 0.84v ccd and vddp.


My bad, I did the age-old mistake of mistyping voltage, I've corrected my post now but it's actually 1.1375vsoc. The ram is at 3800mhz. I definitely haven't been as lucky as you with my 5800x. I can't get lower than 1.060v vdg. vddp and ccd I've kept at 900 now, but I have gone lower on them prior to my recent changes.

With some tests today I've managed trcdrd 15 & trcdwr 8 but I can't get 14 stable on trcdrd. I can get trp really low and CL is at 14 fine. Do you think more vsoc will help with tightening trcdrd?



Audioboxer said:


> ProcODT from mobo auto with these DR sticks and a B550 Unify X has been 36.9. Originally I was running CsOdtDrvStr at 30 based on 40/20/30/20, a fairly common combo, and unless I've remembered this incorrectly early on when learning about memory I believed OdtDrvStr goes up ProcODT should come down a notch or two. So 34.3 was decided on quite early and it just happened to "stick". As you can see from dom he too gets good results with 34.3 on the same set of memory as me.
> 
> Rtt's were based off another popular combo, 6/3/3. These DR sticks like to run RttPark 1 on auto, but that is with GDM enabled. With GDM disabled it seems better to try and run a weaker Park. I know I've been advised by Veii and mongoled the higher VDIMM goes the better it is to try and get Park nearer to 4~7. IIRC 3 is on the edge of "acceptable" at 1.55v. I can boot up to 6 at 3800, so I may try 4~5 on stability testing.
> 
> RttNom seems a bit more temperamental and harder to nail down. I've witnessed tPHYRDL behaviour change negatively with too weak an RttNom. At tCL14 I was running 5/6, but for whatever reason with this memory on an MSI board if I run uneven tCLs tPHYRDL 26/26 becomes easier to run lol. So we're back to 7, the weakest. I think Nom is mostly a case of run the weakest you can.
> 
> The DrvStr's are something I understand the least. Though ClkDrvStr has become pretty clear as the most important to try and stabilise 1T with GDM disabled. 40 is basically the sweet spot. If you're lucky 30 might work. I haven't really tested it. As I said I had OdtDrvStr at 30 for ages, but dropping down to 24 has been fine. CkeDrvStr was on 20 for ages, but it went to 24 as part of my tPHYRDL testing at tCL14. Seemed to help stabilise 28/28. Now that I'm on tCL13 and locked at 26/26, I might try dropping it to 20 again. 24 seems pretty popular though on many DR setups.
> 
> So best is pretty much ymmv. Gotta play around. I'd say dealing with the "right hand side" of ZenTimings when memory OCing is incredibly time consuming and as much as there are "plug and play" settings based on accrued knowledge, just going 6/3/3 and 40/20/30/20 is no guarantee for you at all. Plus even if it were to work it might not be optimal for your sticks. It's my understanding if you can weaken resistances or DrvStr that may help with heat and/or even timings elsewhere.
> 
> Veii explained it to me like "balancing" a dam. If you don't have the dam balanced either too much water or too little water is the result, which in turn, means unstable memory. I also think of it like balancing plates, gotta keep them all spinning, if any one plate drops its game over  Unstable RAM is unstable RAM, doesn't matter if it's a single error. I OC to daily, not bench, so there is an absolute no error acceptable principle for me, within reason. I'm obviously not running TM5/y-cruncher/OCCT for 50 hours in a row. Just hoping I can trust reasonable stability test timeframes combined with real-world usage over weeks/months showing no crashes/weirdness.


thanks for the explanation. Supposedly B-die single rank shouldn't need high ProcODT or drive strength, although I read drive strength being higher can help when you have more sticks or dual rank memory... so although my auto defaults procODT to 40 I'm running it lower and it seems to be stable. drive strength I'm running low too. Termination is just 5/0/0 for me. It's hard to know which setting would give extra stability when there's not a clear pattern and it seems just trial and error. I'm getting to the stage now where I have a decent baseline, but will be looking to tweak certain timings to get the most out of my kit. Trying to compile all the useful info here from yourself, veii, anta777 and others but it's very complicated. Don't really want to be spending that much longer on ram because I didn't even start doing my PBO overclocking yet!

EDIT* added my results after tweaking each setting. Any suggestions where I've gone wrong, or can improve?


----------



## umeng2002

This is the new normal. You will upgrade. You will turn on TPM. You will buy Intel. You will not get a GPU for less than $2,000.00 plus tax. Don't forget to eat your bugs.


----------



## Audioboxer

domdtxdissar said:


> In other shocking news
> 
> *AMD: Windows 11 Slows Our CPUs Up To 15%, Patch Coming
> *
> AMD has announced that all of its WIndows 11-compatible processors can suffer from reduced performance in some applications when used with the new operating system, with extreme outliers in eSports gaming titles dropping by up to 10–15%. For applications, AMD says that the performance impact weighs in at 3–5%. A software update _and_ a Windows Update are in the works to address the issues, with both expected to arrive in October 2021 (this month).
> 
> The errors impact every Ryzen CPU supported in Windows 11. That means all Zen+, Zen 2 and Zen 3 CPUs that comprise the Ryzen 2000, Ryzen 3000, Ryzen 4000, and Ryzen 5000 processors are impacted. In addition, select AMD EPYC processors for data centers, along with some newer Athlon chips, are also impacted. You can see the full list here, but suffice it to say that every AMD chip on our Best CPUs for gaming list is impacted.
> 
> 
> 
> Indeed


MS and AMD have known about these issues for months as well lol. Software companies at their worst.


----------



## K0N574N71N

Blameless said:


> [...]
> So, 208 cycles should be the minimum sensible value for 1900MHz B-die.
> [...]


Thanks to you and @anta777 for explaining this!

What about RFC2 and 4 ? Will my mainboard (ASROCK B550 Extreme4) set them correctly when leaving those on auto? or do I have to calculate them myself? 
I've set RFC to 256, other values are 192 and 132. The tRFC calc from @Veii gives me 190 and 117 as result.


----------



## Melan

K0N574N71N said:


> What about RFC2 and 4


You can ignore them. Not sure they are even used on consumer boards. See this.


----------



## Veii

*Melan*
The Stilt, is correct on half of the story
Same story as tCKE without PDM Flag

They are used for calculation, but not used as tRFC intervals
_(although unclear since AGESA 1.1.8.X update package and IMC-FW change)_
Hence accuracy of them is important, not so much "when" they trigger

Not seeing something being actively used, doesn't mean it's skipped entirely
Whatever tRFC you want to use ~ mini Sheet has still a tRFC ⇋ tRFCns box
Math there is accurate - as multi decimal values have rounding errors


----------



## umeng2002

Mmmm... interesting.


----------



## Veii

K0N574N71N said:


> What about RFC2 and 4 ? Will my mainboard (ASROCK B550 Extreme4) set them correctly when leaving those on auto? or do I have to calculate them myself?
> I've set RFC to 256, other values are 192 and 132. The tRFC calc from @Veii gives me 190 and 117 as result.


Konstatin,
Bioses don't appear to be IC aware
They are tCCD_ aware

They never get it right on MCLK changes, and amount of usage is unclear
(they do get it right on JEDEC ranges tho)
Just clear that it still errors if they are off - but it doesn't show "clear" benefits filling 1,2,4 with the same value vs 1,2,4 with the JEDEC focused one

Also is not entirely clear how low you can go, as X2 and X4 mode are not directly used
(yet unsure since big update with burst refresh mode changes)
Use them , with whatever tRFC you want to run.
it won't be "worse" out of nowhere. I made sure math there is in the correct order ~ just translate your tRFC 1 to the rest or don't follow this and fill all 3 with the same value out. Up to you 
Both have no clear negatives, just if it is majorly off ~ it will be an error cause


----------



## decalruma

Question.

what is the tCKE?

I know that CKE is Clock Enable. 
I learned it works with AND circuits to toggle a signal.
I readed this in the JEDEC SPEC of DDR4 SDRAM.
so..

what is the tCKE( time of CKE )? 
and why does we need a tCKE value?
when does tCKE works?
how does tCKE works?

thank you for your answer in advance.


----------



## XPEHOPE3

Just as @Veii once dropped us a Tool
I'm dropping you a replacement:









It's temporarily on google drive, later on will be released open source on github. It's expected to only run on Vermeer 0x38... table versions and Matisse 0x24??03 table versions (check in ZenTimings debug report for example). But I only checked my CPU with 0x380905 table version.

Notice how it appeared I have two CCDs, but only one active. I can bet that won't be the case for @Veii (while original AMD monitor showed otherwise, I think)


----------



## Veii

XPEHOPE3 said:


> Just as @Veii once dropped us a Tool
> I'm dropping you a replacement:


Thank you a bunch
Generally want to say thank you the last 6-7 pages to everyone here
Everyone is very active (again) and keeps pushing further ~ i'm proud for the better results that come out of this ! Ty~ 

X,
I might have an update on it ~ but want to take a look at yours first 
The "update" i got before, was taken down and a "current" version got uploaded ~ slightly cut down

Topic switch,
I know *anta777*, it is random i can understand
But even random has patterns by the time (when, how long, what follows with it)
This here is mocking me atm. Explosion on RefreshStable test.
Difference ~ it's now mid, and it stays solid. It always triggers and amount of it changes by NOM
It does not look heat dependent & training magically stays consistent tonight (so far)

Used anta's pattern writeup and psone's trickery from chiphel
(till i can understand WPRE & RPRE for SD, DD calculation ~ better)
This was another 200-300MB/s write bump ~ but stability is not fully reached.
I wonder what causes this explosion after the cycle elapses. Old theory would say tCKE or RTT
RTT it isn't. tCKE is well timed, soo it for sure isn't. tWR and SCL it isn't either. tRFC shouldn't be & for heat it's too consistent, explodes and is silent error free again 🤔








* also finally back home. Will do Burst Refresh & Corona BW tests once i get this stable again with the requested "better" changes
tWR = tCL ~ wording has higher priority than it being tRTP related, to what i can test
Maybe conforms to tRFCns rule, but unlikely
tRTP /2 , wouldn't work on 15-15 odd set


----------



## Veii

XPEHOPE3 said:


> Notice how it appeared I have two CCDs, but only one active. I can bet that won't be the case for @Veii (while original AMD monitor showed otherwise, I think)


Idle








It's lovely 
And updates fast 
Load, SSE 4.85 AC hold (PBO)


----------



## decalruma

any body who can solve my problem?


I use gigabyte vision d-p mainboard with 5700g

write speed is abnormal when overclocking.













It was normal on the Dark Hero board which I used before I change my board as this vision d-p board.











the write speed of 3200mhz clocks is normal in vision d-p.


as the clock is raised over 3200mhz, the read speed normally increases, 
but the write speed rises less at a rate proportional to the clock even though all timings and voltages are all set to auto.


how can I fix this?

does anyone have a similar problem?


----------



## Veii

Veii said:


> Load, SSE 4.85 AC hold (PBO)











The biggest difference between our both , is FIT range @XPEHOPE3
For me on this low FIT range (or rather very low trigger) it should never throttle
Another abnormality is that PROCHOT doesn't show a frequency loss but it is on PPT
While prochot will drop FIT-V & has to drop PPT / there are no cTDP, Package Power or TDP limits
74c is clearly PROCHOT limit - but it doesn't wiggle
For anything else, i can hold 4.85 - but once it reaches 65c , it's hard throttle 

EDIT:
Also IOD_VDDIO_MEM_POWER ~ is halved for me & P3 state HUBCLK_FREQ_EFF seems to wiggle more
I'll get the same data from another bugged 6 core with the same binning in about a week from now - to see what is else bizarre & different
EDIT2:
EDC_LIMIT is for me far higher / top right - although i use a far bigger value there. There shouldn't be any limit in there
EDC_CAC only goes up on load


decalruma said:


> write speed is abnormal when overclocking.


This very likely is because of the overboost bug
Disable DF-C_States (enable global c-state generation) and set Powersuply to Typical Current (not low current)
This will kill efficiency, because cores can not fully suspend - but fixes this boost bug which exists since 6 months now

You will "waste" about 16-17W more and cores only can drop to lowest p-state 550mhz.
They can park and lower voltage, but not fully suspend and be inactive.
Better for stability tho


----------



## Blameless

Melan said:


> You can ignore them. Not sure they are even used on consumer boards. See this.


That has been my impression as well, though I have a suspicion this may be outdated and/or that some consumer boards are enabling access to FGR.

I can certainly induce instability with overly tight tRFC2, and might be seeing some performance impact, but it's small enough that I can't say for certain, yet. Needs more testing.

Whatever the case, any potential performance advantage, even if the setting was enabled, is probably too small for most to fuss over.


----------



## Dodgexander

anta777 said:


> *Taraquin*
> CL=CWL even
> CWL=CL-1 odd
> RAS=RC-RP
> RP=RCD
> WR=CL even 100% stable
> WTRL=RTP=WR/2
> WTRS=3(4)
> RCDWR=8
> SC=CCDS-3=1
> SCL=CCDL-3=2,3,4
> SD=DD
> RDRDSD/DD=4+RPRE-1
> WRWRSD/DD=4+WPRE-1
> RDWR=CL-CWL+5+WPRE
> WRRD=CWL-CL+4+RPRE
> tRFC ns convert timings, round up to the nearest divisible by 16.


If this is the case many people have their timings wrong. Especially RP=RCD.

Unless you mean RP=RCDWR

How do we find rpwe or wpre values?


----------



## Taraquin

Enferlain said:


> Yeah I think this might have been too ambitious for a first try
> 
> View attachment 2527883
> 
> 
> I think the sticks went up to around 63c but I was afk when it crashed.
> 
> If I change to 14 14 14 14 it doesn't boot, if I change cad to 24 24 20 24 it doesn't boot, if I put rttnom on disable it doesn't boot, feels like current settings are hair away from not booting as well. I'll mess around with cad values a bit and see if anything improves if not then it's timings again


Suggesting: Try scls at 4, wtrl at 12 and trrdl at 6, that is much easier to run. What voltage do you run the ram at? 14 flat with gdm on should be doable at 1.5V or maybe a bit lower if binning us good. Try 2T and gdm off, gdm autofixes things and errors can be harder to find. Try tRFC 288 if at 1.4-1.45V or 260 of you are at 1.45-1.5V.


----------



## Taraquin

Dodgexander said:


> My bad, I did the age-old mistake of mistyping voltage, I've corrected my post now but it's actually 1.1375vsoc. The ram is at 3800mhz. I definitely haven't been as lucky as you with my 5800x. I can't get lower than 1.060v vdg. vddp and ccd I've kept at 900 now, but I have gone lower on them prior to my recent changes.
> 
> With some tests today I've managed trcdrd 15 & trcdwr 8 but I can't get 14 stable on trcdrd. I can get trp really low and CL is at 14 fine. Do you think more vsoc will help with tightening trcdrd?
> 
> 
> thanks for the explanation. Supposedly B-die single rank shouldn't need high ProcODT or drive strength, although I read drive strength being higher can help when you have more sticks or dual rank memory... so although my auto defaults procODT to 40 I'm running it lower and it seems to be stable. drive strength I'm running low too. Termination is just 5/0/0 for me. It's hard to know which setting would give extra stability when there's not a clear pattern and it seems just trial and error. I'm getting to the stage now where I have a decent baseline, but will be looking to tweak certain timings to get the most out of my kit. Trying to compile all the useful info here from yourself, veii, anta777 and others but it's very complicated. Don't really want to be spending that much longer on ram because I didn't even start doing my PBO overclocking yet!
> 
> EDIT* added my results after tweaking each setting. Any suggestions where I've gone wrong, or can improve?
> View attachment 2527904
> 
> View attachment 2527905
> 
> View attachment 2527906


Suggestion, try 15-15-8-15-30-45, twtrl 9 or 8, tRTP 5, if that doesn't work try twr 12 and trtp 6. Scls don't affect performance that much, but 2 is a bit harder to run than 4. You can try tRFC 274 or 244. Latter might be diable at that high vdimm. 

For comparion my 4000 16 flat, 32-48, 288 tRFC, 16 wr, 8 rtp, 3/9 wtrs/l, 4 scls and rest like yours do dram calc test at 100.7 sec.


----------



## Enferlain

Taraquin said:


> Suggesting: Try scls at 4, wtrl at 12 and trrdl at 6, that is much easier to run. What voltage do you run the ram at? 14 flat with gdm on should be doable at 1.5V or maybe a bit lower if binning us good. Try 2T and gdm off, gdm autofixes things and errors can be harder to find. Try tRFC 288 if at 1.4-1.45V or 260 of you are at 1.45-1.5V.


Thanks, gonna give it a go. 1.45, didn't boot below that on 3600


----------



## Taraquin

Enferlain said:


> Thanks, gonna give it a go. 1.45, didn't boot below that on 3600


Try tRFC 288 then, that should improve performance. You could consider 2T instead of gear down mode and try 15-15-15-30-45. That should be easier to run


----------



## anta777

*Dodgexander*
RCDRD=RP
RCDWR real not use
*Veii*
CL even
WR=CL-1 or CL+1


----------



## Enferlain

Taraquin said:


> Try tRFC 288 then, that should improve performance. You could consider 2T instead of gear down mode and try 15-15-15-30-45. That should be easier to run





















I'm trying to understand this but my brain melts. Like how does he figure out which value works from all the tries?


----------



## Melan

He sets a value and tests.
First 30-20-20-20, if that errors then 20-30-20-20, if that errors then 20-20-30-20 and so on. Until he reaches 20-20-40-20 which supposedly errors less so next you test 30-20-*40*-20 with 40 being a determined value.
Repeat until you're stable or on the brink of insanity.


----------



## Taraquin

Enferlain said:


> View attachment 2527940
> 
> 
> View attachment 2527941
> 
> 
> I'm trying to understand this but my brain melts. Like how does he figure out which value works from all the tries?
> 
> View attachment 2527942


You may need a bit more voltage, try 1.47V. Or change to 2T and gdm off and CL 15, 30 tras, 45 trc. 64gb is hard to run. Might need at bit more IOD voltage.


----------



## Enferlain

Taraquin said:


> You may need a bit more voltage, try 1.47V. Or change to 2T and gdm off and CL 15, 30 tras, 45 trc. 64gb is hard to run. Might need at bit more IOD voltage.


Don't wanna do 2T or gdm off. I'll try to properly find out if the current main timings work at all. If they do I'll try the voltages if not I'll go up to 15 and 16 maybe.

Currently on these
1.45
soc 1.075
ccd .95
iod .9
vddp .9


----------



## Taraquin

Enferlain said:


> Don't wanna do 2T or gdm off. I'll try to properly find out if the current main timings work at all. If they do I'll try the voltages if not I'll go up to 15 and 16 maybe.
> 
> Currently on these
> 1.45
> soc 1.075
> ccd .95
> iod .9
> vddp .9


Point with GDM off is to allow for CL15, also 2T generally gives a bit better performance, but is slightly worse to stabilize. Gdm allows only even numbers for cl, cwl, wr and rtp. Iod should be higher than ccd. Try switching them. Iod might need 1v. I need 1.06v for 3800 and 1.12v for 4000. 24 20 24 24 ofyen works better than all at 20. For 1T you often need first to be 30-60 and third to be 30. With 2T or GDM 24 on first is often good enough.


----------



## Blameless

Ran into some issues with MR6VrefDQ on my MSI board that I'm trying to get some confirmation on.

I'm not 100% certain yet, but I think MSI is flipping the endianness of the binary register values. I was trying to set 66.5%, which should be 1010 in binary or 10 in decimal (what the board takes), but this value resulted in a no post situation. I tried a few other random settings, some of which would post, some of which would not. Then, out of curiosity I took the whole seven-bit variable 0001010 and reversed it to 101000 which is 40 decimal and this figure works exactly as expected and is at least as stable as Auto.

Anyone else have an MSI board they could set some MR6VrefDQ values on, and report back with which ones work, which ones don't, and what their RTT and drive strength values are?


----------



## Mach3.2

Enferlain said:


> View attachment 2527940


B die is temperature sensitive, your DIMMs are all reading at least 50++deg Celsius. Try directing some airflow onto the RAM witha spare fan; if you can bring it under 42 deg Celsius, your life would be much easier.


----------



## Audioboxer

Mach3.2 said:


> B die is temperature sensitive, your DIMMs are all reading at least 50++deg Celsius. Try directing some airflow onto the RAM witha spare fan; if you can bring it under 42 deg Celsius, your life would be much easier.


4 DIMMs, RGB and temps at 60 degrees 

Definitely needs active cooling and possibly even RGB off if those temps can't be brought under control.


----------



## PJVol

Blameless said:


> 101000


I'm not sure, but this could well be 72% (or 40 indeed)
Of course assuming this mapping from the ancient doc is still valid










Blameless said:


> set 66.5%, which should be 1010


Anyway, still don't get how 1010 suppose to be 66.5...


----------



## SneakySloth

Managed to drop tRAS (30 -> 24) and tRC (45 -> 39). 23 and 40 weren't stable but this seems good so far. Got a little bit better copy, read in AIDA and a bit faster time in ryzen calculator bench.

This is with 2500% coverage + 2 hours GPU stress test.


----------



## Veii

anta777 said:


> *Veii*
> CL even
> WR=CL-1 or CL+1


This works as for "most bandwidth" but is not the error cause on me sadly








Equally stable or equally unstable
Little 2x #1 errors at the beginning of the next cycle only

It's not NOM, that goes down to 120ohm "old day stable" without difference
It's not SD, DD - they run equally "good/bad" as 4-4-6-6, 6-6-8-8, and only the lowest the bios allows
It's not tWRRD, tried to push it to 5, sadly unclear still about my WPRE value to do the math (maybe after more experiments)
SCLs go down to 3-3 as lowest, give big bandwidth boosts but remain unstable (4-4,5-5 was most stable)
Dropping tRDRDSCL chipselect was working before, gives promised bandwidth but no combination can fix stability (soo also not this)
Increase in tRRD_L isn't the fix either.
Increase on tWTR_L to 9 or 10 (was old day helping) but did no change. 8 didn't make things worse

tWR works equally "good/bad" between 14,15,16
14 having the least bandwidth, 15 being perfect ~ as you state. But still unstable somewhy

Your config is very CPU intensive, according to @XPEHOPE3 's ZenMonitor, it is quite a high IPC run.
If you can not see anything potential as issue ~ i think it's just the CPU being unstable or tCKE 🤔
Only slightly trows single errors on cycle start - and then nothing. Doesn't look to be thermal either 🤔

* Config for 7 cycles, 1670% (12T) feels perfect
Sadly consistently errors at the start of every cycle once, starting after 28-30min already
(2,3,4,5,6,7) once


----------



## Enferlain

Taraquin said:


> Point with GDM off is to allow for CL15, also 2T generally gives a bit better performance, but is slightly worse to stabilize. Gdm allows only even numbers for cl, cwl, wr and rtp. Iod should be higher than ccd. Try switching them. Iod might need 1v. I need 1.06v for 3800 and 1.12v for 4000. 24 20 24 24 ofyen works better than all at 20. For 1T you often need first to be 30-60 and third to be 30. With 2T or GDM 24 on first is often good enough.


Alright, I will try both what you're saying and c16. Didn't really find anyone with 4x16 running cl14 it's all stuff like this, although these are 3800 not 3600










The higher ccd than iod I got from here

Thanks for the suggestions!



Mach3.2 said:


> B die is temperature sensitive, your DIMMs are all reading at least 50++deg Celsius. Try directing some airflow onto the RAM witha spare fan; if you can bring it under 42 deg Celsius, your life would be much easier.


I don't really have any space to put air directly on the ram. I'm planning on adding 2 more intake fans, maybe they will help with the ram as well since more air will enter the case and less warm air will stay in. This is pretty much the best I can do with what I have but even then the big ass power cable blocks out like half of the surface so not 100% sure

They're pretty much sandwiched between 2 things that generate the most heat so they get warmer than both of those. Basically the hottest part of the system behind primary ssd and chipset



Audioboxer said:


> 4 DIMMs, RGB and temps at 60 degrees
> 
> Definitely needs active cooling and possibly even RGB off if those temps can't be brought under control.


Yeah well, under control is 40c and 50c right now. I've only seen it at 60+ in summer and during tm5 but I never really paid attention to it since previously I just ran 2x16 either at 3200 or 3600 without much tuning.

Like this is pretty much idle









I went back to 3200c14 xmp for now, I will try 3600 c15 and c16 tomorrow


----------



## XPEHOPE3

Veii said:


> according to PJVOL's ZenMonitor


 @Veii again thinks all Russians are the same


----------



## anta777

*Veii*
tWRmin>=tCL
even tCL WR=CL+1


----------



## PJVol

XPEHOPE3 said:


> @Veii again thinks all Russians are the same


Strange, literally the same thing I thought of koreans


----------



## Mach3.2

Enferlain said:


> I don't really have any space to put air directly on the ram. I'm planning on adding 2 more intake fans, maybe they will help with the ram as well since more air will enter the case and less warm air will stay in. This is pretty much the best I can do with what I have but even then the big ass power cable blocks out like half of the surface so not 100% sure
> 
> They're pretty much sandwiched between 2 things that generate the most heat so they get warmer than both of those. Basically the hottest part of the system behind primary ssd and chipset
> 
> 
> 
> Yeah well, under control is 40c and 50c right now. I've only seen it at 60+ in summer and during tm5 but I never really paid attention to it since previously I just ran 2x16 either at 3200 or 3600 without much tuning.
> 
> Like this is pretty much idle
> View attachment 2527964
> 
> 
> I went back to 3200c14 xmp for now, I will try 3600 c15 and c16 tomorrow


All I can say is your current thermal sitaution is very likely to be kneecapping your RAM's overclocking potential.

For comparison, my ambient temps are 32°C, I only have a single 40mm fan providing airflow for 2 DIMMs, and max temp measured with a type K thermocouple stuck onto the RAM's heatspreader is 44.3°C after ~45 min of anta777 absolute config tm5 test. Your idle temps are literally my load temps.

ZenTiming for some context:


----------



## Luggage

Enferlain said:


> Alright, I will try both what you're saying and c16. Didn't really find anyone with 4x16 running cl14 it's all stuff like this, although these are 3800 not 3600
> 
> View attachment 2527962
> 
> 
> The higher ccd than iod I got from here
> 
> Thanks for the suggestions!
> 
> 
> 
> I don't really have any space to put air directly on the ram. I'm planning on adding 2 more intake fans, maybe they will help with the ram as well since more air will enter the case and less warm air will stay in. This is pretty much the best I can do with what I have but even then the big ass power cable blocks out like half of the surface so not 100% sure
> 
> They're pretty much sandwiched between 2 things that generate the most heat so they get warmer than both of those. Basically the hottest part of the system behind primary ssd and chipset
> 
> 
> 
> Yeah well, under control is 40c and 50c right now. I've only seen it at 60+ in summer and during tm5 but I never really paid attention to it since previously I just ran 2x16 either at 3200 or 3600 without much tuning.
> 
> Like this is pretty much idle
> View attachment 2527964
> 
> 
> I went back to 3200c14 xmp for now, I will try 3600 c15 and c16 tomorrow











Zip-ties to the rescue 😉


----------



## Enferlain

Mach3.2 said:


> For comparison, my ambient temps are 32°C, I only have a single 40mm fan providing airflow for 2 DIMMs, and max temp measured with a type K thermocouple stuck onto the RAM's heatspreader is 44.3°C after ~45 min of anta777 absolute config tm5 test. Your idle temps are literally my load temps.


Damn, that's pretty cool, especially with 32 ambient. In summer my ambient was around 35-40 and I think the ram was around 60-70c, but yeah I don't think I'm going to add active cooling. I don't really do anything that needs me to push the ram higher, I only want to tune it because I feel like it. My typical use case has the cpu sit at 10-20% 45-50c and gpu at 40-50c so I'm never going to realistically need the extra performance a ram oc would net me which is the main reason why I don't really want to take the asylum route of getting every single timing and voltage just right. I'm just taking shots with already tried stuff hoping for the best

Going for least effort most results and getting active cooling is more on the effort side. Still gonna add 2 more intake fans though.



Luggage said:


> Zip-ties to the rescue 😉


LMAO

--

Does it affect ram oc if I have a - .05 offset on the cpu?


----------



## Dodgexander

Taraquin said:


> Suggestion, try 15-15-8-15-30-45, twtrl 9 or 8, tRTP 5, if that doesn't work try twr 12 and trtp 6. Scls don't affect performance that much, but 2 is a bit harder to run than 4. You can try tRFC 274 or 244. Latter might be diable at that high vdimm.
> 
> For comparion my 4000 16 flat, 32-48, 288 tRFC, 16 wr, 8 rtp, 3/9 wtrs/l, 4 scls and rest like yours do dram calc test at 100.7 sec.


Thanks for this!, I'm trying trtp5 but it doesn't seem to improve performance. In a post above anta says:
WTRL=RTP=WR/2

If I move CL up to 15 I still can't drop twr lower than 16.

So I had moved trtp5 up to 8 to match half of twr. I can get lower trp no problem but twr won't budge.

I did manage lower trfc (240, (224 was unstable)) and also lower trc vis-à-vis tras but can't seem to bench better than 102.5.

I also changed cl to 15 since anta says twr should be -1 or +1 twr. Though it does bench a couple of ms slower.

Results:








I'm pretty happy with this. twr is my limiting factor. Just can't get it to run sub 16.

Any more tips? Has anyone hit a brick wall at twr16? I can't even post with it lower.


----------



## anta777

you can break the rules
WR=16
RTP=5 or 6
if it will be better (for your bios)


----------



## Audioboxer

Whilst waiting on AMD/MS to actually fix Windows 11 so it can work on Ryzen CPUs I think I'm going to give this a go GitHub - TheWorldOfPC/Windows11-Debloat-Privacy-Guide

I guess it's in line with what sophia script and some other things do but with it just being about debloating Windows 11 it seems pretty easy to follow.


----------



## Skull_Angel

Audioboxer said:


> Whilst waiting on AMD/MS to actually fix Windows 11 so it can work on Ryzen CPUs I think I'm going to give this a go GitHub - TheWorldOfPC/Windows11-Debloat-Privacy-Guide
> 
> I guess it's in line with what sophia script and some other things do but with it just being about debloating Windows 11 it seems pretty easy to follow.


I'm not sure if they have a version for it yet, but if they put out a copy of Education like they did for Win10 [assuming it's set up the same] it'll be the better version to have if you don't want to get into using a lot of third-party debloaters. The Win10 Edu version was basically Pro with more control for updates and bloat, iirc.

*____*
I got back into tuning after keeping up with the last several pages, with interesting results. 

Following @anta777 guidelines I was able to reduce voltage and drop Cmd to 1T with little issue; the results so far have been mixed with an increase in bandwidth, but slightly worse latency (average +0.3ns) using identical settings to Cmd 2T. The only difference between Cmd 1T and 2T being - 2T tPHYRDL 26/26, 1T tPHYRDL 28/28.

Current results:









I'm guessing the latency is due to tPHYRDL, but have no idea how to "correct" it. I have tried a few changes to termination and cad_bus, but so far it has just introduced instability without changing tPHYRDL.


----------



## decalruma

Veii said:


> View attachment 2527919
> 
> The biggest difference between our both , is FIT range @XPEHOPE3
> For me on this low FIT range (or rather very low trigger) it should never throttle
> Another abnormality is that PROCHOT doesn't show a frequency loss but it is on PPT
> While prochot will drop FIT-V & has to drop PPT / there are no cTDP, Package Power or TDP limits
> 74c is clearly PROCHOT limit - but it doesn't wiggle
> For anything else, i can hold 4.85 - but once it reaches 65c , it's hard throttle
> 
> EDIT:
> Also IOD_VDDIO_MEM_POWER ~ is halved for me & P3 state HUBCLK_FREQ_EFF seems to wiggle more
> I'll get the same data from another bugged 6 core with the same binning in about a week from now - to see what is else bizarre & different
> EDIT2:
> EDC_LIMIT is for me far higher / top right - although i use a far bigger value there. There shouldn't be any limit in there
> EDC_CAC only goes up on load
> 
> This very likely is because of the overboost bug
> Disable DF-C_States (enable global c-state generation) and set Powersuply to Typical Current (not low current)
> This will kill efficiency, because cores can not fully suspend - but fixes this boost bug which exists since 6 months now
> 
> You will "waste" about 16-17W more and cores only can drop to lowest p-state 550mhz.
> They can park and lower voltage, but not fully suspend and be inactive.
> Better for stability tho


I tried it. but It seems not to be solved by your solution..








write speed is abnormal yet.. OTL...


----------



## XPEHOPE3

Skull_Angel said:


> I'm guessing the latency is due to tPHYRDL, but have no idea how to "correct" it.


Try raising VDDP. It helped people in the past (as well as relaxing tRRD/tWTR, but then you lose something else)


----------



## decalruma

what is the tStag timing?
anybody here who can explains this timing for me?
It's also okay to only tell me a reference link.


----------



## Skull_Angel

XPEHOPE3 said:


> Try raising VDDP. It helped people in the past (as well as relaxing tRRD/tWTR, but then you lose something else)


Early results with only a VDDP bump are promising. Improved latency and consistency across benching, but no change to tPHYRDL; I'm alright with that if it's not an indication of timings being auto-corrected. Currently testing for stability

Thank you

edit: unstable, reverted to posted settings and they showed unstable upon retest. I know 1T on dual-rank can be much harder, may just revert to 2T and call it a day after through testing.


----------



## chitos123

I couldn't update Google Sheets anymore, It's getting harder and harder to live. sorry who waiting for an update 😥
Ownership is given to the person who wants the spreadsheet, please reply. C:









Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com


----------



## TimeDrapery

chitos123 said:


> I couldn't update Google Sheets anymore, It's getting harder and harder to live. sorry who waiting for an update 😥
> Ownership is given to the person who wants the spreadsheet, please reply. C:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com


I'll take it off your hands if you'd like!


----------



## mongoled

TimeDrapery said:


> I agree... the trouble (in my eyes) lies in that most people have such difficulty with letting go of ego/self due to suffering because they feel they're unique and separate from what they experience and perceive when "in reality"... "🎶 As a descendant of the stars, it's only right that I become one 🎶" 😂😂😂😂😂


I would take it a step futher, most people have no idea what the ego is and thats the underlying problem, nevermind coming to terms with it and "owning" it, its the other way round, we are governed by out egos (yes, I place myself in this bracket but at least I am aware of it and all that comes with it .....).

And yeah "reality" is such a personal thing, however, that should not stray from the confounds of our evolution and how we came about.

I better stop, this is a facinating subject for me though way way way offtopic, and more in the realms of "non-reality"

😂😂


----------



## mongoled

TimeDrapery said:


> I'll take it off your hands if you'd like!


Yay


----------



## Taraquin

Changed back to WR/RTP 10/5 and gained 1.5sec in dram calc test and 0.5Mb read in aida. TM5 passes, but I get a few errors after 3000% i karhu :/ Maybe lower wtrs/wtrl wasn't stable after all, never got it with 4/10, but 3/9 isn't errorfree. One thing I have noted is that latency is more consistent in a7da running 16/8 wr/rtp. I get 52-53ns every run. 10/5 get 52-55ns so although perf is slightly better there might be something 'off' sometimes.


----------



## Taraquin

Dodgexander said:


> Thanks for this!, I'm trying trtp5 but it doesn't seem to improve performance. In a post above anta says:
> WTRL=RTP=WR/2
> 
> If I move CL up to 15 I still can't drop twr lower than 16.
> 
> So I had moved trtp5 up to 8 to match half of twr. I can get lower trp no problem but twr won't budge.
> 
> I did manage lower trfc (240, (224 was unstable)) and also lower trc vis-à-vis tras but can't seem to bench better than 102.5.
> 
> I also changed cl to 15 since anta says twr should be -1 or +1 twr. Though it does bench a couple of ms slower.
> 
> Results:
> View attachment 2527981
> 
> I'm pretty happy with this. twr is my limiting factor. Just can't get it to run sub 16.
> 
> Any more tips? Has anyone hit a brick wall at twr16? I can't even post with it lower.


14 WR/7 RTP doesn't work? Tried using antas formula on tras and trc? I lost very little performance if any going from 16-16-16-29-45 to 16-16-16-32-48


Dodgexander said:


> Thanks for this!, I'm trying trtp5 but it doesn't seem to improve performance. In a post above anta says:
> WTRL=RTP=WR/2
> 
> If I move CL up to 15 I still can't drop twr lower than 16.
> 
> So I had moved trtp5 up to 8 to match half of twr. I can get lower trp no problem but twr won't budge.
> 
> I did manage lower trfc (240, (224 was unstable)) and also lower trc vis-à-vis tras but can't seem to bench better than 102.5.
> 
> I also changed cl to 15 since anta says twr should be -1 or +1 twr. Though it does bench a couple of ms slower.
> 
> Results:
> View attachment 2527981
> 
> I'm pretty happy with this. twr is my limiting factor. Just can't get it to run sub 16.
> 
> Any more tips? Has anyone hit a brick wall at twr16? I can't even post with it lower.


WR/RTP 14/7 don't work? I lost little if any perf going from 16 16 16 29 45 to 16 16 16 32 48 using antas recommendation. You could try 15 15 15 30 45, maybe that allows you to lower tRFC which impacts perf most of all timings? You run tighter timings than me, yet dram score is a bit slower, maybe the extra 200MHz is the key? Are you able to run more than 3800/1900 without wheas?


----------



## Taraquin

Enferlain said:


> Alright, I will try both what you're saying and c16. Didn't really find anyone with 4x16 running cl14 it's all stuff like this, although these are 3800 not 3600
> 
> View attachment 2527962
> 
> 
> The higher ccd than iod I got from here
> 
> Thanks for the suggestions!
> 
> 
> 
> I don't really have any space to put air directly on the ram. I'm planning on adding 2 more intake fans, maybe they will help with the ram as well since more air will enter the case and less warm air will stay in. This is pretty much the best I can do with what I have but even then the big ass power cable blocks out like half of the surface so not 100% sure
> 
> They're pretty much sandwiched between 2 things that generate the most heat so they get warmer than both of those. Basically the hottest part of the system behind primary ssd and chipset
> 
> 
> 
> Yeah well, under control is 40c and 50c right now. I've only seen it at 60+ in summer and during tm5 but I never really paid attention to it since previously I just ran 2x16 either at 3200 or 3600 without much tuning.
> 
> Like this is pretty much idle
> View attachment 2527964
> 
> 
> I went back to 3200c14 xmp for now, I will try 3600 c15 and c16 tomorrow


You don't need to go from 14 to 16, try 2T, gdm off and CL15. I sure that is easier to run than CL14 GDM  Maybe you could lower voltage a bit which drops temps and then allows you to run tighter tRFC which is very temp sensitive


----------



## Blameless

PJVol said:


> I'm not sure, but this could well be 72% (or 40 indeed)
> Of course assuming this mapping from the ancient doc is still valid
> View attachment 2527959
> 
> 
> Anyway, still don't get how 1010 suppose to be 66.5...


I probably sould have linked to my earlier post: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

0001010 is the MR6[5:0] register value that references 66.5% VrefDQ.


----------



## mongoled

So.......

considering that the author of said config "absolute" is either not willing or not able to assist with what the error codes signify for each test does anybody know of an English resource where the TM5 functions are explained ??

Found this here but sheds no light ...

An example below of why its important to have an understanding of this

[Test1]
Enable=1
Time (%)=240
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=2
Pattern Param0=0x77777777
Pattern Param1=0x33333333
Parameter=0
Test Block Size (Mb)=4

[Test6]
Enable=1
Time (%)=240
Function=SimpleTest
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=0
Test Block Size (Mb)=4

If I lower vDIMM than the above tests throw error 1s and few error 6s

If I increase vDIMM than the above tests throws many error 6s but few error 1s

So the reverse.

If we look at the differences in the test then we see that one test uses "Pattern Mode" 0, while the other users "Pattern Mode" 2

The other difference is in the "Pattern Param".

I feel its pretty important to be able to work out why there is such a distinct difference when simply changing vDIMM.

Logically, if I wanted people to use my work then I would do my best to assist those people in understanding my work.

Unfortunately anta777, for reasons unknown to me, does not want this, something that I dont understand.... (understand....well.....I could understand, but that would not be compliant with what my understanding of why overclock.net exists and that is to share our love/knowledge of all things overclocking)

** EDIT **
OK need to add this as it would be unfair otherwise

This is information that anta777 has shared that seems to be the only thing to guide us



anta777 said:


> You cannot associate tests with timings.
> Only Matrix, Interface, Addressing and Processor Controller errors can be detected.
> 
> 1.Matrix ("analog" timings): RCD,RP,RRDS,RRDL,FAW,RFC,REFI, part RAS,RC,WR - pattern 1,2 (conditionally).
> 2.Interface ("digital" timings): tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE - pattern 0 (conditionally).
> 3. Addressing : CMD, GDM - pattern 1.
> 4. Processor controller : freq, voltage, CWL - mirrormovie and mirrormovie128, in this case, the error itself will be detected at startup Refreshstable (the beginning of any SimpleTest).


and



anta777 said:


> Right.
> param0 or param1 only pattern 2, participates in random template generation
> test block size: memory is shared test block size, then, inside the block, testing is performed by access by 64 byte (interleave=1) or 8 byte (interleave=0)


Looks like this is what we have to go by, deciphering the meanings ...


----------



## Audioboxer

Anta seemed to suggest tRP should = tRCDRD and dom found SCL 4 to bench higher, so I guess I'm going to use this as my profile for beginning some serious benching and then I'll do what dom did and record results with different SCLs, tRP, etc.

I want to slim down my Windows 11 installation first though, then I'll get to benching.


----------



## Enferlain

Taraquin said:


> You don't need to go from 14 to 16, try 2T, gdm off and CL15. I sure that is easier to run than CL14 GDM  Maybe you could lower voltage a bit which drops temps and then allows you to run tighter tRFC which is very temp sensitive


Yeah I'm going to give it a go in a bit, thanks. I haven't been able to boot so far below 1.45. I tried 1.35 but I got sent straight into automatic repair lmao




Spoiler: xmp trfc is pretty litty


----------



## Blameless

mongoled said:


> An example below of why its important to have an understanding of this
> 
> [Test1]
> Enable=1
> Time (%)=240
> Function=SimpleTest
> DLL Name=bin\MT0.dll
> Pattern Mode=2
> Pattern Param0=0x77777777
> Pattern Param1=0x33333333
> Parameter=0
> Test Block Size (Mb)=4
> 
> [Test6]
> Enable=1
> Time (%)=240
> Function=SimpleTest
> DLL Name=bin\MT0.dll
> Pattern Mode=0
> Pattern Param0=0x0
> Pattern Param1=0x0
> Parameter=0
> Test Block Size (Mb)=4
> 
> If I lower vDIMM than the above tests throw error 1s and few error 6s
> 
> If I increase vDIMM than the above tests throws many error 6s but few error 1s
> 
> So the reverse.
> 
> If we look at the differences in the test then we see that one test uses "Pattern Mode" 0, while the other users "Pattern Mode" 2
> 
> The other difference is in the "Pattern Param".
> 
> I feel its pretty important to be able to work out why there is such a distinct difference when simply changing vDIMM.


I have next no knowledge of the internal workings of TestMem5, but if I had to hazard a guess I'd suggest Test1 is finding errors due to the charge falling on the low side of the data eye while test 6 is finding overshoots. A highly speculative solution I'd float is to either keep voltage on the low side and try to increase cooling and/or loosen tRFC, or increase voltage and reduce drive strength/increase output driver resistance slightly.


----------



## mongoled

Blameless said:


> I have next no knowledge of the internal workings of TestMem5, but if I had to hazard a guess I'd suggest Test1 is finding errors due to the charge falling on the low side of the data eye while test 6 is finding overshoots. A highly speculative solution I'd float is to either keep voltage on the low side and try to increase cooling and/or loosen tRFC, or increase voltage and reduce drive strength/increase output driver resistance slightly.


Thats a good logical way of seeing it



As such, i already tried this exact troubleshooting (loosen tRFC as the dimms are watercooled and play with Rtts Cad Bus etc) but could not find stability with the errors.

It would be nice if we can at least get some English resource with regards to the workings of TM5 rather than having to rely on third part info as even third party info is proving difficult to come across ...


----------



## Taraquin

Enferlain said:


> Yeah I'm going to give it a go in a bit, thanks. I haven't been able to boot so far below 1.45. I tried 1.35 but I got sent straight into automatic repair lmao
> 
> 
> 
> 
> Spoiler: xmp trfc is pretty litty
> 
> 
> 
> 
> View attachment 2528062


If you have a good bin you might be able to run 3600cl15 at 1.4V or below. I have a bad bin and can run 3800cl15 2T at 1.46V. Xmp values are terrible


----------



## Audioboxer

I ran that Windows 11 debloat script on a new install and it does indeed get rid of a lot of crap. Only thing it seems to have left is Microsoft Edge Update under Apps and I can't seem to figure out how to remove it.

Also even with this being done I still have 116 processes after a few minutes from boot. I have no idea how people get down to like 50-60. I even ran a BlackViper tweaked script to disable some Windows services 🤯

Though a quick look at the still running services and it seems that script is a bit outdated and leaves behind some new things that look safe to turn off.


----------



## domdtxdissar

mongoled said:


> Thats a good logical way of seeing it
> 
> 
> 
> As such, i already tried this exact troubleshooting (loosen tRFC as the dimms are watercooled and play with Rtts Cad Bus etc) but could not find stability with the errors.
> 
> It would be nice if we can at least get some English resource with regards to the workings of TM5 rather than having to rely on third part info as even third party info is proving difficult to come across ...


I think what Anta777 was getting at in the beginning was that the "error codes" for testmem5 with 1usmus cfg is simply wrong (don't work) --> they (in-effect testmem5) can't be trusted and/or should not be used to debug memory problems this way.. In my experiences i also have lots of cases where i got a error and tried to debug using error code, only to later discover that the problem was something totally different then the error code said it was...

Since most of the codes, if not all originate from *Veii*, using *his motherboard*, *his memory*, *his CPU* and *his settings* etc, i could very well see the same error code mean very different problems on different systems...

That's at least my understanding of what have been said.. And since you were demanding/asking (still doing) for a new debug/error sheet for his new cfg, something that can't be done for reasons above, you got that rather snappy remark back.. (deserve 1usmus cfg error-codes that don't work)

I have no horse in this race

I think the best way to go about this:

get a stable configuration with lax timings/settings and make sure it passes whatever time requirement you set for yourself
Only change settings one by one, then you know what changes made you have problems / what actually solved the problem (brute forcing settings)


----------



## SneakySloth

It


Audioboxer said:


> Anta seemed to suggest tRP should = tRCDRD and dom found SCL 4 to bench higher, so I guess I'm going to use this as my profile for beginning some serious benching and then I'll do what dom did and record results with different SCLs, tRP, etc.
> 
> I want to slim down my Windows 11 installation first though, then I'll get to benching.


Its interesting because I get a bit better performance in AIDA/DRAM Calculator with TRP = RCDRD - 2. Naturally the difference in real world usage will be almost zero but at least in synthetic tests, RCDRD - 2 is better on my setup.


----------



## anta777

What are the other timings?
tRC?
tRAS?
tRCD?
tRP?
If tRCD=tRP and tRC with tRAS decrease 2 ticks, =perfomance with RP=RCDRD-2


tRAS=tRC-tRP =better perfomance

tRP only plays a role for tRC.


----------



## Audioboxer

SneakySloth said:


> It
> 
> Its interesting because I get a bit better performance in AIDA/DRAM Calculator with TRP = RCDRD - 2. Naturally the difference in real world usage will be almost zero but at least in synthetic tests, RCDRD - 2 is better on my setup.


dom seemed to report that as well, but Anta has said to me twice now to use tRP = tRCDRD. I'll do my own testing shortly.


----------



## SneakySloth

anta777 said:


> What are the other timings?
> tRC?
> tRAS?
> tRCD?
> tRP?
> If tRCD=tRP and tRC with tRAS decrease 2 ticks, =perfomance with RP=RCDRD-2
> 
> tRP only plays a role for tRC.


This is what I tested to be stable overnight










Initially I was testing with tRP = 15, so then tRAS + tRP = tRC (15 + 24 = 39). 

Last night I tested with tRP = 13 (shown above). At the moment its tRAS + tRP + 2 = tRC. Its stable in the tests I've done and performance is a little better and more consistent (in Corona, AIDA etc).

tRC = 22 is not stable.
TRAS = 37 is not stable.


----------



## anta777

tRC=39
tRP=15
tRAS=24


tRP=13 tRAS=24 tRC=39 wrong, this case real tRP=39-24=15
tRC=tRAS+tRP


For big better consistent tWR=16 or RTP=6


----------



## SneakySloth

anta777 said:


> tRC=39
> tRP=15
> tRAS=24
> 
> 
> tRP=13 tRAS=24 tRC=39 wrong, this case real tRP=39-24=15
> tRC=tRAS+tRP


Yeah that's what I was thinking. Seems more logical that way. I'll put tRP back to 15 then. Maybe I'll try and see if I can get TWR down to 10 and tWTRL and tRTP down to 5.




Audioboxer said:


> dom seemed to report that as well, but Anta has said to me twice now to use tRP = tRCDRD. I'll do my own testing shortly.


Sounds good. It could just be a placebo that we're seeing with mismatched timings.


----------



## Audioboxer

New NVMe drive to go along with a fresh install of Windows










Can you overclock NVMe drives? _goes and messes with BCLK and destroys the drive_ 😂

It might just be me but so far it seems like on this clean install HWINFO is reporting lower boosting than my old install that was an upgrade from Windows 10. I wonder if that also plays a part in the mess MS has made with Ryzen CPUs on Windows 11? Somehow upgrading from Windows 10 results in "better" performance?

Hopefully the actual fix is on the way soon and not "soon" meaning the last day of October.


----------



## SneakySloth

anta777 said:


> tRC=39
> tRP=15
> tRAS=24
> 
> 
> tRP=13 tRAS=24 tRC=39 wrong, this case real tRP=39-24=15
> tRC=tRAS+tRP
> 
> 
> For big better consistent tWR=16 or RTP=6


With RTP = 6 I'm guessing tWTRL = 6 as well?


----------



## Enferlain

Audioboxer said:


> I ran that Windows 11 debloat script on a new install and it does indeed get rid of a lot of crap. Only thing it seems to have left is Microsoft Edge Update under Apps and I can't seem to figure out how to remove it.
> 
> Also even with this being done I still have 116 processes after a few minutes from boot. I have no idea how people get down to like 50-60. I even ran a BlackViper tweaked script to disable some Windows services 🤯
> 
> Though a quick look at the still running services and it seems that script is a bit outdated and leaves behind some new things that look safe to turn off.


Do you have a link to that script?


----------



## Dodgexander

Taraquin said:


> 14 WR/7 RTP doesn't work? Tried using antas formula on tras and trc? I lost very little performance if any going from 16-16-16-29-45 to 16-16-16-32-48
> 
> WR/RTP 14/7 don't work? I lost little if any perf going from 16 16 16 29 45 to 16 16 16 32 48 using antas recommendation. You could try 15 15 15 30 45, maybe that allows you to lower tRFC which impacts perf most of all timings? You run tighter timings than me, yet dram score is a bit slower, maybe the extra 200MHz is the key? Are you able to run more than 3800/1900 without wheas?


thanks man.
Yeah I get a brick wall at tWR16, I think my kit just doesn't like going any lower than its XMP. Some chips that are binned at high frequencies seem to like having lower timings more than others, but this one just won't budge on tWR. I'm running vDIMM at 1.51 so don't really want to go higher without some dedicated cooling.
I actually followed the DDR4 Overclocking Guide on GitHub so tWR was one of the first things I tested with other timings very high (so they do not become the limiting factor), and it doesn't move lower.
I thought this may be because tCL was low, but running tCL at 16 still doesn't let me post tWR 14.
I had rTP on 8 when I tested, but moved it back to 5 now since it doesn't let me run lower tWR.

You're right that 15-15-15-30-45 give similar performance, but I get a slight edge with 14-8-15-15-21-36. tRAS and tRP won't go lower so I'm following the formula of 15+21=36.

tRFC I'm actually pretty pleased with, 240 is divisible by 16. I tried 224 first (next step down) and it's not stable. 224 would be the absolute minimum ns for my speed and voltage, and I don't really want to go over vDIMM 1.51.

Overall I'm pretty pleased, I think the difference now is definitely that extra 200mhz. I can boot at higher FCLK but I just couldn't get WHEA free, I may revisit if they ever fix the stupid WHEA crap, but I honestly spend so much time wasted trying to get stable FCLK first I'm not really up to doing it some more

I have to just accept some people are luckier than others 

thank you for your help.


----------



## Audioboxer

Enferlain said:


> Do you have a link to that script?


I posted it on the last page but here it is again GitHub - TheWorldOfPC/Windows11-Debloat-Privacy-Guide

The video guide is worth watching 



 For whatever reason the written guide forgets to mention to copy install_wim_tweak.exe to C:\Windows.

I think other scripts/tools are more powerful and I know many use sophia script, but trying to just get it to up and go seems daunting. Soo many options.

I chose option 2 as I didn't want to nuke the store/Xbox. Option 1 is probably great for a test/bench install.

For services there is this but I think it's a bit outdated GitHub - madbomb122/BlackViperScript: Sets Win 10 Services based on Black Viper's Service Configurations


----------



## anta777

*SneakySloth*
WTRL you can exhibit any, WTRL<WR
Only in Jedec:
WTRL=RTP=7.5 ns


----------



## Ramad

decalruma said:


> what is the tStag timing?
> anybody here who can explains this timing for me?
> It's also okay to only tell me a reference link.


tStag = Staggering time

While the RAM is entering a refresh cycle RFC, it will need to map and chop the refresh work in smaller workloads. As an example, to refresh a million pages, it will not request a refresh of 1 x 1 mil. pages, but will divide these pages into say 8 refresh workloads of 1mil./8 = 125.000 pages for each refresh workload. This was an example to explain what tStag is.

tStag is an internal die timing that you don't have to worry about (since it can't be changed by the user) and is determined by the die manufacturer.


----------



## mongoled

Dropped down to two of my good dimms to see how they do water cooled, I had never tested them independantly from the 4 dimm setup.

Was a good time to visit this as I have some dimms to test next week so was a good time to take the dimms out.

First preliminary test


----------



## domdtxdissar

mongoled said:


> Dropped down to two of my good dimms to see how they do water cooled, I had never tested them independantly from the 4 dimm setup.
> 
> Was a good time to visit this as I have some dimms to test next week so was a good time to take the dimms out.
> 
> First preliminary test
> 
> 
> 
> View attachment 2528108


Are you also able to run T1 without 56 cmdsetup time when going down to SR ? 
That was my experience going from 4x8gb to 2x8b before i got my current DR sticks.


----------



## reqq

i dont think thats stable.. you have half L1 and L2 cache then what you should.. i had the same and it wasnt stable everywhere..


----------



## Skull_Angel

reqq said:


> i dont think thats stable.. you have half L1 and L2 cache then what you should.. i had the same and it wasnt stable everywhere..


That's normal for single CCD


----------



## reqq

Skull_Angel said:


> That's normal for single CCD


I see..makes sense. Weird mine overclock did that.


----------



## Luggage

Skull_Angel said:


> That's normal for single CCD





http://imgur.com/ELBazMS


Write is half bq single ccd yes but… the rest is low bq 5600x vs 5800x?


----------



## Skull_Angel

Luggage said:


> http://imgur.com/ELBazMS
> 
> 
> Write is half bq single ccd yes but… the rest is low bq 5600x vs 5800x?


I'm pretty sure that's the case. My 5600x results are much closer to @mongoled results than your 5800x results, and most other results I've seen for both CPUs more or less follow the same pattern. Makes me wish I spent extra on the 5800x some times, haha


----------



## Sleepycat

Audioboxer said:


> New NVMe drive to go along with a fresh install of Windows
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Can you overclock NVMe drives? _goes and messes with BCLK and destroys the drive_ 😂
> 
> It might just be me but so far it seems like on this clean install HWINFO is reporting lower boosting than my old install that was an upgrade from Windows 10. I wonder if that also plays a part in the mess MS has made with Ryzen CPUs on Windows 11? Somehow upgrading from Windows 10 results in "better" performance?
> 
> Hopefully the actual fix is on the way soon and not "soon" meaning the last day of October.


Damn that drive is quick. It's faster than a regular SN850. Is this with a BCLK OC?


----------



## 99belle99

I have been running 1900MHz 1:1:1 the past two weeks as I never bothered trying to mess with anything really until then as I have being about two years just running 3600MHz XMP 16, 16, 16 , 36, 53 with a 1800MHz IF.

Below is a run I just done now on AIDA64 for memory:


----------



## Skull_Angel

I'm hitting some weird issues. After moving back to 2T to more easily reach stability I've run into the same problem as earlier (with 1T) where a first pass is successful, but a second pass fails. I thought I had a decent idea about what to modify to increase stability, but I just don't understand the new test profile (@anta777 ABSOLUT) enough to narrow down areas to work on.

First run passed, but after a restart second failed:









edit: This should suggest a problem somwehere with voltage, termination, cad_buss, no?


----------



## SneakySloth

VDIMM maybe? 1.42 might be a little too low. Try going to 1.45 and see if that's stable. Then bring it down if it's stable at that.


----------



## Skull_Angel

SneakySloth said:


> VDIMM maybe? 1.42 might be a little too low. Try going to 1.45 and see if that's stable. Then bring it down if it's stable at that.


Possible. It was previously 1.45, but caused errors on initial 1T tuning that were alleviated by lowering voltage (after reviewing, it may have been due to tRFC being too long). I'm currently testing to see if EDC 104 may have been too low as well, bumped to 110 which is seems pretty average for 5600x PBO tweaks.


----------



## Sleepycat

Skull_Angel said:


> Possible. It was previously 1.45, but caused errors on initial 1T tuning that were alleviated by lowering voltage (after reviewing, it may have been due to tRFC being too long). I'm currently testing to see if EDC 104 may have been too low as well, bumped to 110 which is seems pretty average for 5600x PBO tweaks.


If voltage doesn't help, then my recommendation is to try the following one at a time in the following order to see if you regain stability.
Option 1:
ProcODT - 43.6 Ohm
ClkDrvStr - 24.0 Ohm
CsOdtDrvStr - 24.0 Ohm
CkeDrvStr - 24.0 Ohm

Option 2:
tWTRL - 12

Option 3:
tRDRDSD - 5
tRDRDDD - 5

Option 4:
tWRWRSD - 7
tWRWRDD - 7


----------



## decalruma

Veii said:


> View attachment 2527919
> 
> The biggest difference between our both , is FIT range @XPEHOPE3
> For me on this low FIT range (or rather very low trigger) it should never throttle
> Another abnormality is that PROCHOT doesn't show a frequency loss but it is on PPT
> While prochot will drop FIT-V & has to drop PPT / there are no cTDP, Package Power or TDP limits
> 74c is clearly PROCHOT limit - but it doesn't wiggle
> For anything else, i can hold 4.85 - but once it reaches 65c , it's hard throttle
> 
> EDIT:
> Also IOD_VDDIO_MEM_POWER ~ is halved for me & P3 state HUBCLK_FREQ_EFF seems to wiggle more
> I'll get the same data from another bugged 6 core with the same binning in about a week from now - to see what is else bizarre & different
> EDIT2:
> EDC_LIMIT is for me far higher / top right - although i use a far bigger value there. There shouldn't be any limit in there
> EDC_CAC only goes up on load
> 
> This very likely is because of the overboost bug
> Disable DF-C_States (enable global c-state generation) and set Powersuply to Typical Current (not low current)
> This will kill efficiency, because cores can not fully suspend - but fixes this boost bug which exists since 6 months now
> 
> You will "waste" about 16-17W more and cores only can drop to lowest p-state 550mhz.
> They can park and lower voltage, but not fully suspend and be inactive.
> Better for stability tho


I have solved my low write speed issue by reducing tfaw timing under 32.
write speed is lower with over 32 tfaw depending on tfaw value.
I dont know why it happens.


----------



## Audioboxer

Sleepycat said:


> Damn that drive is quick. It's faster than a regular SN850. Is this with a BCLK OC?


No BCLK overclock, I was just joking I might kill the drive or something if I tried that lol.

Keep in mind the drive is currently pretty much empty so I expect it to slow down a bit once it fills up.


----------



## mongoled

domdtxdissar said:


> I think what Anta777 was getting at in the beginning was that the "error codes" for testmem5 with 1usmus cfg is simply wrong (don't work) --> they (in-effect testmem5) can't be trusted and/or should not be used to debug memory problems this way.. In my experiences i also have lots of cases where i got a error and tried to debug using error code, only to later discover that the problem was something totally different then the error code said it was...


As previously asserted, its most likely a two way language problem.

Well thats the exact thing, is it not? we want to find ways to troubleshoot the error codes given by TM5, lets stop and think logically for a second.

Why would the author of TM5 software develop a means for an error to be relayed to the end users that is specific to a test of instructions ? One reason would be so that we could use these error codes to diagnose which type of memory tests are failing. Of course this is not going to tell us why the specific test is failing ...

Your opinions regards the reliability of the methods of correcting such errors is valid, but without us having an English resource where English speakers members of the forum that do have the option of understanding TM5 better along with how the different configs are created could only be a beneficial....



domdtxdissar said:


> Since most of the codes, if not all originate from *Veii*, using *his motherboard*, *his memory*, *his CPU* and *his settings* etc, i could very well see the same error code mean very different problems on different systems...


Yeah, again a valid point, but .......

I dont think thats fair to completely disregard Veii investigations, that in my opinion would be 1/ ignorant and 2/ disrespecting the efforts that Veii has put into attempting to decipher the error codes.

It needs more investigation, by more members, but unfortunately its only the Russian speaking members who have access to whatever data is available online regards to TM5 and configs.



domdtxdissar said:


> That's at least my understanding of what have been said.. And since you were demanding/asking (still doing) for a new debug/error sheet for his new cfg, something that can't be done for reasons above, you got that rather snappy remark back.. (deserve 1usmus cfg error-codes that don't work)
> 
> I have no horse in this race
> 
> I think the best way to go about this:
> 
> get a stable configuration with lax timings/settings and make sure it passes whatever time requirement you set for yourself
> Only change settings one by one, then you know what changes made you have problems / what actually solved the problem (brute forcing settings)


Im with you, also have no horse in this race, many of us do this for fun/hobby, my only race is to do my best to improve the freely available knowledge at this forum and of course to sooth my ego with the nice scores



Dont think that "demanding" is a fair way to reflect my posts, im not going to pull my posts, its all there to be seen, no demands anywhere, asking for someone to answer a question is not a demand .....

Now being snappy, well, as ive said its all there to be seen ....

Back to the overclocking



Yeah, I can run 1T no setup timings with 16GB, was just a quick test as I was leaving the office so didnt spend time putting all my 16GB settings back (can be seen from the other values that are not really for 2 x 8GB configs).

Funny thing today ive "lost" around .3 to .5 ns with the same settings

😂 🤣

Tried to post CL12, was a no go, but I didnt push past 1.7v as the aim is to find 24/7 configs


----------



## whocares7

MrHoof said:


> Yes it did and in about the same time 40mins.


I redid the test again with slight vSOC bump -1.125v SET (vSOC LLC2) and this did the trick.
So this config seems to be more taxing on the IMC/FCLK and easily breaks the 40mV ratio.


----------



## mongoled

reqq said:


> i dont think thats stable.. you have half L1 and L2 cache then what you should.. i had the same and it wasnt stable everywhere..


Others have already answered, all rock stable, its exactly how 5600x should be


----------



## anta777

*decalruma*
You must always strive FAW=16 and RRDS=4


----------



## Blameless

decalruma said:


> write speed is lower with over 32 tfaw depending on tfaw value.
> I dont know why it happens.


tFAW limits the number of row activates that can occur per rank in a given period to reduce current draw. If it's set to more than 4*tRRD_S it's potentially limiting performance.


----------



## Skull_Angel

I forgot to screenshot the successful passes for validation, but these are my final results [for now? lol!]. First test passed after modifying cad_bus settings, second after a full shutdown; both using TM5 ABSOLUT @anta777 config. Thank you to all who have contributed to this thread, the knowledge has been very helpful to many, myself included.










Now I'm going to try to enjoy a fully stable system before I get the bug again, haha.


----------



## Sleepycat

Audioboxer said:


> No BCLK overclock, I was just joking I might kill the drive or something if I tried that lol.
> 
> Keep in mind the drive is currently pretty much empty so I expect it to slow down a bit once it fills up.


Usually empty SN850s bench at about 6900-7000 read. Yours is probably the fastest I've seen.


----------



## Audioboxer

Sleepycat said:


> Usually empty SN850s bench at about 6900-7000 read. Yours is probably the fastest I've seen.


What chip is it using? MP600 Pro uses the Phison E18.

There is an even faster version now, the MP600 Pro XT. Same E18 but they've squeezed the read and write a bit higher. Guaranteed 7,000/7,000+.

Funnily enough I wonder if there is some "silicon lottery" with NVME drives now seeing as they're sold as "speeds up to". If so I guess it's quite like DDR4, you can pay more for an XT drive and should be guaranteed a baseline but you can maybe buy a regular Pro model and it ends up as good as or nearly as good as an XT anyway.

Though I think the XT model has some more upgrades, Phison E18 + 176 Layer whatever the layer part means.


----------



## Skull_Angel

Audioboxer said:


> What chip is it using? MP600 Pro uses the Phison E18.
> 
> There is an even faster version now, the MP600 Pro XT. Same E18 but they've squeezed the read and write a bit higher. Guaranteed 7,000/7,000+.
> 
> Funnily enough I wonder if there is some "silicon lottery" with NVME drives now seeing as they're sold as "speeds up to". If so I guess it's quite like DDR4, you can pay more for an XT drive and should be guaranteed a baseline but you can maybe buy a regular Pro model and it ends up as good as or nearly as good as an XT anyway.
> 
> Though I think the XT model has some more upgrades, Phison E18 + 176 Layer whatever the layer part means.


Likely covering their asses for when the speed drops with a more full drive; there's always that one group that didn't get the memo and demands "rated speeds" under sub-optimal conditions


----------



## decalruma

Blameless said:


> tFAW limits the number of row activates that can occur per rank in a given period to reduce current draw. If it's set to more than 4*tRRD_S it's potentially limiting performance.


why is not the trrdl but the trrds?
I know the tfaw is four activate windows.
trrdl is longer than trrds.
could It not have any problem with shorter tfaw than trrdl*4?
I cant understand why is the trrds, not trrdl.
plz tell me why is this.


----------



## mongoled

@domdtxdissar 

Here you go, now to move to lowering tRP


----------



## Audioboxer

Skull_Angel said:


> Likely covering their asses for when the speed drops with a more full drive; there's always that one group that didn't get the memo and demands "rated speeds" under sub-optimal conditions


Yeah that too, I don't think anyone is buying such fast drives to leave them empty so the general public need to be made aware speeds will drop.

I use it for Windows and some games, along with essential apps. Still fills up. But obviously photos, videos and other junk is stored on another drive/in the cloud.



decalruma said:


> I have solved my low write speed issue by reducing tfaw timing under 32.
> write speed is lower with over 32 tfaw depending on tfaw value.
> I dont know why it happens.
> View attachment 2528148
> 
> View attachment 2528149


Meant to quote this post earlier, this makes me want to give higher FCLK another go sometime soon. Though I guess 2367 and memory at 4733 is helped by a G CPU


----------



## anta777

*decalruma*
RRDS - different bank group
RRDL- same bank group
Read or write clever controller must choose different bank group for max performance.


https://media-www.micron.com/-/media/client/global/documents/products/technical-note/dram/tn_4003_ddr4_network_design_guide.pdf?rev=2be2d83e1c7d44ee9e72e3a2163f58b7


----------



## Audioboxer

@anta777 is there anything on this you would change?


----------



## Steve_

@Audioboxer - what was the trick you used to get both channels to run tPHYRDL = 26?
From flicking through the posts, it looks like it was more VDIMM, stronger RttNom and stronger ClkDrvStr.
I've just bumped up VDIMM to 1.55 and managed to get CL13 to post with 3800 and 4x16GB. However, I've lost tPHYRDL = 26 on all channels. Overall, this is a performance improvement for me but I'd like to try to get back to 26 on both channels.
Increasing ClkDrvStr tends to push both channels to 28 as opposed to both to 26.


----------



## Audioboxer

Steve_ said:


> @Audioboxer - what was the trick you used to get both channels to run tPHYRDL = 26?
> From flicking through the posts, it looks like it was more VDIMM, stronger RttNom and stronger ClkDrvStr.
> I've just bumped up VDIMM to 1.55 and managed to get CL13 to post with 3800 and 4x16GB. However, I've lost tPHYRDL = 26 on all channels. Overall, this is a performance improvement for me but I'd like to try to get back to 26 on both channels.
> Increasing ClkDrvStr tends to push both channels to 28 as opposed to both to 26.


Literally run an uneven tCL lol. So 13 or 15, pretty much always 26/26. Never been able to get tCL14/tCL16 to run 26/26 at 3800. The battle I had for a while was 28/30 at tCL14 and that was remedied by playing around with RttNom/AddrCmdDrvStr/CkeDrvStr. Managed to get it 28/28.

I'm going to guess running 4 DIMMs will be your challenge, I've only ever ran 2 and this is a 2 DIMM motherboard.


----------



## anta777

*Audioboxer*
tCL=14 tCWL=14 tRDWR=8 WRRD=4 have tried ?


----------



## Audioboxer

anta777 said:


> *Audioboxer*
> tCL=14 tCWL=14 tRDWR=8 WRRD=4 have tried ?


Yes, tCL14 works fine, it just pushes tPHYRDL to 28/28 and part of me was just happy to see tCL13 working at the memory binned 1.55v. I think it helps performance a little!

14/8 runs fine, I obviously just can't run tCWL 14 when tCL is 13. 12/8 is a no go.


----------



## MrHoof

whocares7 said:


> I redid the test again with slight vSOC bump -1.125v SET (vSOC LLC2) and this did the trick.
> So this config seems to be more taxing on the IMC/FCLK and easily breaks the 40mV ratio.


nice!
Well I am running IOD at .098 and SOC at 1.1/auto thats rather 120mV diffrence. Gona try to push IOD with ClkDrvStr at 30 first, maybe that already does the trick.


----------



## Blameless

decalruma said:


> why is not the trrdl but the trrds?
> I know the tfaw is four activate windows.
> trrdl is longer than trrds.
> could It not have any problem with shorter tfaw than trrdl*4?
> I cant understand why is the trrds, not trrdl.
> plz tell me why is this.


Because you could conceivably have four or more consecutive activates to different bank groups, which would use tRRD_S. If you were using tRRD_L*4 for tFAW it would cause a delay. This is why tRRD_S*4 is the fastest tFAW you can set...and what you should set, unless you need to loosen it up to preserve stability or fit within a certain power/heat envelope (which is almost completely irrelevant for desktop memory).


----------



## rossi594

I just opened a dedicated Whea 19 discussion thread, to make it easier to collect and find experiences and findings. (~700 Pages will make info hard to find for people new to the issue).

feel free to join in: AMD Ryzen 5000 (Zen3) Whea 19 Discussion Thread


----------



## kim nk

Hello. I recently tested Audioboxer's memory timing almost as it is with CL14. The results were timing when the memory voltage was set at 1.55V in BIOS, which generated a blue screen and used it at 1.58V. If there is a wrong part of this 16GB, please advise.
If the voltage is 1.58-1.6V, do I have to modify the TRFC as well? If so, I wonder how much I should give you. In addition, I wonder what I should do if I change this value correctly in the current state.









And since CL13 TCWL12 TRDWR8TWRRD4 is performed by TRFC 224 in TM5, the memory voltage was about 1.63V (BIOS). My memory also increased the amount of memory voltage required due to manual CPU over. In this case, should the TRFC be re-established based on the memory voltage?


----------



## anta777

1.60 samsung b-die tRFC=110ns


----------



## kim nk

anta777 said:


> 1.60 samsung b-die tRFC=110ns


If I calculate it, it will be around 1.6v and 224trfc. I'm confused about how to calculate. ㅠㅠ Can you express approximately 1.5v 1.52v 1.54v 1.58v in trfc? And if there is anything wrong with the other memory timing, please point out.


----------



## Nd4spdvn

Here is a set I developed in the last days in the light of the latest discussions. I also tried 14-14-14-22-36 and 14-14-14-23-37 together with tWR16 / tRTP 8, higher FAW etc. but it looks that it will require more than 1.55V to stabilize (if ever) and rid of errors, problem is that I have no cooling whatsoever on these 4 dimms and don't plan to add any as this is an openbench system in the living room. Would've loved a cas14 1T though.


----------



## decalruma

why has this happened?
trc 40 in bios but automatically changed as 75.
5700g 4800MHz cl16 1.62v
other timings have safe values.


----------



## mongoled

So peeps what do you think then ??

anta777 config passes with flying colors, but 1usmus DRAM Membench, well, see for yourselves .....









Will throw Y-Cruncher at it, I expect Y-Cruncher to fail pretty fast.....


----------



## Luggage

Nd4spdvn said:


> Here is a set I developed in the last days in the light of the latest discussions. I also tried 14-14-14-22-36 and 14-14-14-23-37 together with tWR16 / tRTP 8, higher FAW etc. but it looks that it will require more than 1.55V to stabilize (if ever) and rid of errors, problem is that I have no cooling whatsoever on these 4 dimms and don't plan to add any as this is an openbench system in the living room. Would've loved a cas14 1T though.


Open bench? Just rest a fan on the dimms!


----------



## Nd4spdvn

Yeah, thanks, I know, but this sits directly on the floor and it will pick up a ton of dust, plus I have the cpu's cooler Noctua fans to blow _toward_ the dimms helping a little. Also a cat is sometimes around...


Luggage said:


> Open bench? Just rest a fan on the dimms!


----------



## anta777

*kim nk*
3800
tRFC
1.60 (110ns)- 224 ticks
1.55 (120ns)- 240 ticks
1.50 (136ns)- 272 ticks

Other timings:
WTRL=6 or 7
it's all


----------



## kim nk

anta777 said:


> *kim nk*
> 3800
> tRFC
> 1.60 (110ns)- 224 ticks
> 1.55 (120ns)- 240 ticks
> 1.50 (136ns)- 272 ticks
> 
> Other timings:
> WTRL=6 or 7
> it's all


Thank you. To ask you another question here, if you look at TRFC (NS) at my timing, it will be marked 117.8947. What do you need to modify to get 110 (NS) and reduce TRFC by 3.2 when the voltage is added to 0.1? For example, 1.6V 224 --> 1.59 227 --> 1.58 230 --> 1.57 233 --> 1.56 236 --> 1.55V 240 I wonder if it's correct.









Twtrl It does not boot below 8.
The 110ns you mentioned is 1.6v and trfc 224, and I can't reduce it from 117.8947 to 7.8947.


----------



## anta777

there is a parabola dependence
ns in ticks, round up to a multiple of 8 and +8.

For 16-Gbit chips (micron,hynix,samsung)
ns (table Reous) in ticks, round up to a multiple of 16 and +16.


----------



## TimeDrapery

Audioboxer said:


> @anta777 is there anything on this you would change?


@Audioboxer 

Engage "Dark Mode" 😁😁😁😁😁


----------



## Audioboxer

TimeDrapery said:


> @Audioboxer
> 
> Engage "Dark Mode" 😁😁😁😁😁


Dark mode taskbar/start menu, light mode windows. I just prefer it that way lol. I think it's years of being used to light explorer 🌞🕶

I do use dark mode in many apps mind you.


----------



## mongoled

As expected, Y-Cruncher failed after a few minutes, back to 1usmus v3 config for me...


----------



## SneakySloth

mongoled said:


> As expected, Y-Cruncher failed after a few minutes, back to 1usmus v3 config for me...


What % coverage were you using with the Absolute profile? I wonder if the Universal profile works better for you









[email protected]







drive.google.com


----------



## MrHoof

So far I prefere the universal2 config over the absolute it just seems to find erros faster. I dont see the point running test 1 for 9 mins at the recommended settings thats default for 16 threads, Time (%)=240 for test 1 is maybe a little a long imo.


----------



## SneakySloth

MrHoof said:


> So far I prefere the universal2 config over the absolute it just seems to find erros faster. I dont see the point running test 1 for 9 mins at the recommended settings thats default for 16 threads, Time (%)=240 for test 1 is maybe a little a long imo.


You may be right. I just tried the universal profile after using the absolute one for the last few days. 

Absolute = stable 8 hours
Universal = errored within 30 minutes 8 times.


----------



## Skull_Angel

mongoled said:


> So peeps what do you think then ??
> 
> anta777 config passes with flying colors, but 1usmus DRAM Membench, well, see for yourselves .....
> 
> View attachment 2528193
> 
> 
> Will throw Y-Cruncher at it, I expect Y-Cruncher to fail pretty fast.....


Suspect it needs more passes. Encountered similar issues with runs of ABSOLUT using suggested .cfg changes for number of CPU threads.



MrHoof said:


> So far I prefere the universal2 config over the absolute it just seems to find erros faster. I dont see the point running test 1 for 9 mins at the recommended settings thats default for 16 threads, Time (%)=240 for test 1 is maybe a little a long imo.


Noooooooo, why you do dis?? Now I've got to check it out 🤣


----------



## SneakySloth

Universal2 seems to be a very good profile so far. Running it alongside a GPU load is finding errors in my previously assumed stable timings (those were verified using OCCT, TM5 Absolute, TM5 Anta777 with hours of testing).


----------



## glnn_23

Ran this the other day but still get whea errors unfortunately.


----------



## Audioboxer

glnn_23 said:


> Ran this the other day but still get whea errors unfortunately.
> View attachment 2528227


Got me thinking maybe I should lower my IOD to see if USB issues with the HNT test stop rather than pump it higher 🤔


----------



## Audioboxer

Hmm, anyone else had this issue? First time I've tried running TM5 since a fresh install. Yes, I'm using right click run as administrator.


----------



## Hale59

You need to reboot.


----------



## deadfelllow

Guys I used to run my rams @4066 mhz. After i changed my case something happened to my mobo it cant even boot 2800+ ram speed. I changed rams to another mb it worked very well. DDDDD what tu fuq happened. I cleaned the mobo with isopropyl alcohol and i am able to run 2933 mhz DDDDDD someone can explain to me what happened? !

ps : i can set fclk up to 2000.but memory freq cant go up.(its not about cpu related)


----------



## mongoled

SneakySloth said:


> What % coverage were you using with the Absolute profile? I wonder if the Universal profile works better for you
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [email protected]
> 
> 
> 
> 
> 
> 
> 
> drive.google.com


1750


Skull_Angel said:


> Suspect it needs more passes. Encountered similar issues with runs of ABSOLUT using suggested .cfg changes for number of CPU threads.


From prior experience if Membench throws errors it means the RAM is highly unstable. 

More passes are not going to help, the config should pretty much catch these errors straight away...


----------



## SneakySloth

mongoled said:


> 1750
> 
> From prior experience if Membench throws errors it means the RAM is highly unstable.
> 
> More passes are not going to help, the config should pretty much catch these errors straight away...


Have you tried the universal profile by any chance? That seems to be, at least on my setup, better at picking up errors.


----------



## Blameless

I've been using a modified (reduced time from 500% to 100% to get it to cycle faster) Anta Extreme1 profile for a while, but I'm trying this LMHz Universal2 on known borderline (mean time between errors is about six hours with the modded Anta or stock 1usmus_v3) settings to see if it's any faster at finding issues.


----------



## mongoled

SneakySloth said:


> Have you tried the universal profile by any chance? That seems to be, at least on my setup, better at picking up errors.


No I have not, though I think I've worked out that the absolute config does not catch IMC related dram clock issues.

I raised vSOC and now Membench passes along with TM5 with tRP @12, just running some Y-Cruncher to see if it holds out


----------



## Blameless

Takes an hour per pass of Unversal-2 to get through the 96GiB of mismatched Micron 16Gb E-die stuff I'm testing on my 3950X + X570 Aorus Elite (not what I would call a good board, but it came with my 3080) setup.

No errors yet after two complete passes, but I know for a fact these settings I'm using aren't quite stable.



mongoled said:


> No I have not, though I think I've worked out that the absolute config does not catch IMC related dram clock issues.


Do you have a link to that config?


----------



## Audioboxer

mongoled said:


> No I have not, though I think I've worked out that the absolute config does not catch IMC related dram clock issues.
> 
> I raised vSOC and now Membench passes along with TM5 with tRAS @12, just running some Y-Cruncher to see if it holds out


Well done finding this, I wouldn't run that profile for now.


----------



## SneakySloth

Blameless said:


> Takes an hour per pass of Unversal-2 to get through the 96GiB of mismatched Micron 16Gb E-die stuff I'm testing on my 3950X + X570 Aorus Elite (not what I would call a good board, but it came with my 3080) setup.
> 
> No errors yet after two complete passes, but I know for a fact these settings I'm using aren't quite stable.
> 
> 
> 
> Do you have a link to that config?


This is the absolute profile








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Best test for compare - corona benchmark. WTRL=7




 www.overclock.net





EDIT:

From what I tested yesterday, the universal profile seems to be good at finding voltage related issues. I had to bump up my VDIMM a little to fix the errors I was seeing. Maybe the absolute /anta is better at finding timing issues?


----------



## musician

I am done with the TM5 all together as I see the big inconsistencies at different configs. I will stay with Karhu, OCCT CPU large extreme variable and Y-Cruncher. And maaybe MemTestPro too at the final stage.


----------



## mongoled

Audioboxer said:


> Well done finding this, I wouldn't run that profile for now.


Well im still in the process of confirming this is indeed the case.

Should be pretty straight forward to find which test in the 1usmus v3 config in responsible for detecting Y-Cruncher errors that are related to IMC instability and then transplanting that into the absolute config.

Currently have not found the right combination to get it to run stable, just playing with vDDP/ProcODT as voltages are not the reason for the issue, well thats what i think

🤣 😂


----------



## Blameless

Universal2 passed it's standard run without errors. Might set it to run for more passes later, but I'm trying ABSOLUT first.


----------



## KedarWolf

Absolute passed for me, and this is Universal overnight, 30 cycles.


----------



## anta777

it is more correct to increase the testing time - up 2000%-10000%, rather than the number of cycles

For you:
tRAS=23 max tRAS for tRCconstanta - better
tCWL=14
RDWR=8
WRRD=4 or 5
tRFC=256 or 248

Why RCDRD<RP ?
RP=16
and
decrease RC with RAS


----------



## XPEHOPE3

Blameless said:


> Universal2 passed it's standard run without errors. Might set it to run for more passes later, but I'm trying ABSOLUT first.


It was recommended to run it along with Furmark to increase temps.

@anta777 
Thank you, but I'm surprised that tRFC 280 somehow did work although previously tRFC 384 (with other settings quite close to current) didn't work. I wonder how can that be?? Also @Blameless , if you are checking something which was 1usmus_v3-unstable previously, it might be interesting to retest it with 1usmus_v3 again before ditching other configs.

July, 39.6° max temp, tRFC 384 fail, but 392 pass














August, 40.8° max temp, tRFC 392 pass (with tighter tRRD* and more VDDP)








Now I've set tRFC to 280 and ran 1usmus_v3_25, Universal and anta777's absolut configs either while mining Ethereum or along Furmark. Temps were the highest for Universal config along Furmark, but difference is negligible and can be attributed to day-to-day variation of temperatures.
1usmus+mining=40.6°, 1usmus+furmark=42.4° (note how temps in October are the same as in July, even w/o central heating in my room)













absolut+mining=39.8°, absolut+furmark=42.2°













universal+mining=40.2°, universal+furmark=42.5°


----------



## Blameless

anta777 said:


> it is more correct to increase the testing time - up 2000%-10000%, rather than the number of cycles


Does that reliably result in errors being found in less time?

Some of these tests are only scheduled once per cycle and increasing the testing time makes a full cycle prohibitively long.

_Edit:_ I do see the tests repeating with an increase to cycle time, but it would still be easier to judge progress via number of cycles, IMO.



XPEHOPE3 said:


> It was recommended to run it along with Furmark to increase temps.


I do all my memory testing with reduced case fan speed (about 300rpm below what I normally use), elevated ambients (~30C intake temp), while running gminer (which has an even lower CPU/system memory impact than FurMark and will still max out the power limit on my cards with the right, or wrong, F/V curve).

Both Universal2 and ABSOLUT passed at settings that both 1usmus_v3 and a modded Anta Extreme1 will consistently fail. Universal2 ended before I usually encounter errors, but it took almost seven hours for ABSOLUT to complete it's three cycles, and I usually see an error in either of the older tests by then.


----------



## SneakySloth

Blameless said:


> Does that reliably result in errors being found in less time?
> 
> Some of these tests are only scheduled once per cycle and increasing the testing time makes a full cycle prohibitively long.
> 
> 
> 
> I do all my memory testing with reduced case fan speed (about 300rpm below what I normally use), elevated ambients (~30C intake temp), while running gminer (which has an even lower CPU/system memory impact than FurMark and will still max out the power limit on my cards with the right, or wrong, F/V curve).
> 
> Both Universal2 and ABSOLUT passed at settings that both 1usmus_v3 and a modded Anta Extreme1 will consistently fail. Universal2 ended before I usually encounter errors, but it took almost seven hours for ABSOLUT to complete it's three cycles, and I usually see an error in either of the older tests by then.


Would it be possible for you to post that custom extreme1 profile by any chance? I would definitely want to test it out.


anta777 said:


> it is more correct to increase the testing time - up 2000%-10000%, rather than the number of cycles
> 
> For you:
> tRAS=23 max tRAS for tRCconstanta - better
> tCWL=14
> RDWR=8
> WRRD=4 or 5
> tRFC=256 or 248
> 
> Why RCDRD<RP ?
> RP=16
> and
> decrease RC with RAS


Its weird because that's what I did. I changed the testing time to 2500% and the profile still didn't catch the errors that Universal2 did. These timings specifically. The voltage was apparently a little low. I had to increase it to 1.49v.











Same timings while running the Universal2 profile


----------



## Blameless

SneakySloth said:


> Would it be possible for you to post that custom extreme1 profile by any chance?


The only changes I made to it was to reduce the cycle time in the main section from 500% to 100% and increase the number of cycles from 3 to 10.

Edit: The profiles I'm using came from the link in this post...








Memory Testing with TestMem5 TM5 with custom configs


Hello everybody I am just making a very light tutorial with a collection of custom config files and a DOWNLOAD LINK for TM5 v0.12 anta777 absolut config *Official* Intel DDR4 24/7 Memory Stability Thread None of the work is mine but it seems like a pretty good and fast testing app




www.overclock.net


----------



## mongoled

lol,accidently left Y-cruncher running all night diagnosing the IMC issue, dropped to flat 14s to get a baseline with 56-0-0 setup timings










Looks like anta666 got what he wanted, people to test his configs

😂 😂

Think there is a thread here at overclock.net where peeps are already testing TM5 configs, think we should move those conversations there ...


----------



## Luggage

Veii said:


> up to CPU , can be different
> You watch HWInfo , TDC usage % - and note the highest TDC you run and then limit it slightly - so it stays in the 98-100% area
> Then check if you see any improvements at all ~ as EDC limits , do lower allcore voltages
> TDC is there to limit peak boost voltages, while PPT is rather a powersuply limiter - although also used as pure TDP draw limit for cooler design
> 
> soo what you need to max out is PPT, Package Power limit and the cTDP limit (both inside AMD CBS , NBIO ~ maybe SMU)
> DF_C-States disabling that , is inside NBIO - SMU Common options
> Powersuply power limit , should be inside AMD CBS , CPU Common options - or also NBIO (set to typical current)
> 
> Last two mentions are to prevent the overboost bug - but Generate C-States has to be enabled
> If not, it will not be able to move anywhere lower than P0 Power profile , which is 3.7 or 3.8ghz ~ while P1 is near 2.1ish and P2 near 980mhz
> The lowest P-State and the states in between , depend on this Generate C-States flag ~ and are needed , in order to manage powerbudget better = higher boost
> DF-C States or C6 states (translated) ~ are there to fully hibernate cores (but the wakeup from hibernation triggers an infinite boost and can by attempts also draw 1.55v @ 55ghz target)
> on OC_Mode, this can peak to 1.68v @ 5.9ghz (applied)
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> We worked towards powerplan optimizations pre-dLDO era , as it made sense & i worked on a powerplan to utilize overboost for a positive thing - with fixed limits
> But these fixed limits, bugged CPPC tags
> Soo until we have a clear path to take & AMD fixes their overboost mess
> It is more than recommended ~ to disable DF_C-States & Set powersuply Idle control to typical current
> 
> Hydra needs it set to low current with DF-C states enabled
> But Hydra & CTR (pic above is Hydra) does enforce DF-CStates enabled , in order to fully hibernate cores and share more powerstates in between
> Else AMD still "locked" the ability to set per clock frequency, without pushing anything near it upwards too ~ oor bugging it out to drop to 3.7ghz p0 state
> * which btw still is in works, but hydra future i should not talk about
> 
> We have to use TDC now, as limiting EDC - does limit (x)GMI link speed limits - and in general slows down cache & access time latency
> EDC needs to be open fully.
> There are several stages of limiters - PBO are the first stage and if it was me ~ i'd put all to infinite
> But you know, Matisse performed better with fixed limits as they lowered voltage usage ~ soo maybe it still can work out , but just with TDC


Old reply but…
I’m still working on PBO limits with and without high EDC.
Because of something on Reddit I ran wprime superpi with HWinfo64 (200ms polling) this morning with 200 115 700 cTDP 200, PPL 250, dCstate disable, common current draw. And got a 7GHz reading… is this HWinfo64 bugging out or your “overboosting mess”? Did I forget some more settings and do you have some older posts about it I can read up on?

Edit:


http://imgur.com/a/OubvrLm


----------



## Audioboxer

mongoled said:


> lol,accidently left Y-cruncher running all night diagnosing the IMC issue, dropped to flat 14s to get a baseline with 56-0-0 setup timings
> 
> View attachment 2528365
> 
> 
> Looks like anta666 got what he wanted, people to test his configs
> 
> 😂 😂
> 
> Think there is a thread here at overclock.net where peeps are already testing TM5 configs, think we should move those conversations there ...


12 hours of y-cruncher, that is one way to make sure something is stable!


----------



## mongoled

So... cant get tCL @13 to run some of the Y-Cruncher tests (N32, HNT)

Played around with many combinations, just fails.

TM5 passes no issues (1usmus v3).

I then wanted to try the flat 14s profile with GDM enabled, but setting GDM enabled on a rock stable profile results in having to reset the CMOS !

Cant get my head around that, I wanted to try GDM enabled to see if tPHYRDL will default to 26.

Did not see anywhere the GDM enabled requires an odd timings for it to post ........


----------



## Audioboxer

mongoled said:


> So... cant get tCL @13 to run some of the Y-Cruncher tests (N32, HNT)
> 
> Played around with many combinations, just fails.
> 
> TM5 passes no issues (1usmus v3).
> 
> I then wanted to try the flat 14s profile with GDM enabled, but setting GDM enabled on a rock stable profile results in having to reset the CMOS !
> 
> Cant get my head around that, I wanted to try GDM enabled to see if tPHYRDL will default to 26.
> 
> Did not see anywhere the GDM enabled requires an odd timings for it to post ........


HNT is brutal, if there is anything unstable it will find it. Especially above 1900 FCLK lol.


----------



## mongoled

Audioboxer said:


> HNT is brutal, if there is anything unstable it will find it. Especially above 1900 FCLK lol.


One of the few times ive not being able to stabalise Y-Cruncher (to some extent) while trying a huge number of different combination of settings.

Are you able to post your flat 14 profiles with GDM enabled ?


----------



## Audioboxer

mongoled said:


> One of the few times ive not being able to stabalise Y-Cruncher (to some extent) while trying a huge number of different combination of settings.
> 
> Are you able to post your flat 14 profiles with GDM enabled ?


With it enabled? I'd assume so, I'll check for you and edit this post in 5 mins.

edit - Something like this?










It's booted 28/26, so I'd have to mess around with Rtts/DrvStrs again to see if I can get 28/28 or maybe 26/26. But I've never managed 26/26 before at tCL14 at 3800 lol.

GDM automatically "corrects" tRTP to 6 btw, even though it's set to 5 in the BIOS. So that is interesting!


----------



## anta777

GDM on : CL,CWL,WR,RTP odd.


----------



## mongoled

Audioboxer said:


> With it enabled? I'd assume so, I'll check for you and edit this post in 5 mins.
> 
> edit - Something like this?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> It's booted 28/26, so I'd have to mess around with Rtts/DrvStrs again to see if I can get 28/28 or maybe 26/26. But I've never managed 26/26 before at tCL14 at 3800 lol.
> 
> GDM automatically "corrects" tRTP to 6 btw, even though it's set to 5 in the BIOS. So that is interesting!


Oh, you have some other odd timings in your config

Can you set those that are odd numbers to even numbers then see if it posts ?


----------



## mongoled

Now that is stupid, just because there is no odd timing when we use GDM then we have to reset the CMOS, lol.

Just because its not going to be used (GDM) then I would not expect such a scenario to require a CMOS reset

I simply nudged tWR to 11 and system posts and I get the same 26/28 you get also.


----------



## Audioboxer

mongoled said:


> Oh, you have some other odd timings in your config
> 
> Can you set those that are odd numbers to even numbers then see if it posts ?












Like this? This isn't a saved profile btw I just took my tCL13 profile and made it flat 14 GDM 1T lol.

No matter what I seem to try I can't stop tPHYRDL 28/26. On a GDM disabled 56/1T profile I did manage to get it going 28/28 with tCL14. But when tCL13 started passing stability tests that is when I gave up on tCL14 as tCL13 runs 26/26 easily


----------



## mongoled

Audioboxer said:


> Like this? This isn't a saved profile btw I just took my tCL13 profile and made it flat 14 GDM 1T lol.
> 
> No matter what I seem to try I can't stop tPHYRDL 28/26. On a GDM disabled 56/1T profile I did manage to get it going 28/28 with tCL14. But when tCL13 started passing stability tests that is when I gave up on tCL14 as tCL13 runs 26/26 easily


Thanks for that, I can't post my setup and require a CMOS reset when I attempt that. 

So you are OK running Y-Cruncher with tCL @13?


----------



## LxT1N

how i can get my tRFC?
tRFC2= tRFC/1,346, tRFC4 = tRFC/1,625
it this right?

VDDSOC Voltage = 1.0v | 1.15v
DRAM = 1.40v | 1.45v
VDDG CCD Voltage = 0.95v | 1.05v
VDDG IOD Voltage = 0.95v | 1.05v
CLDO VDDP Voltage = 0.855v | 1.050v

tCL : 16
tRCDRD : 16
tRCDWR : 16
tRP : 16
tRAS : 32
tRC : 48
tRRDS : 4 | 4 | 6
tRRDL : 4 | 6 | 6
tFAW : 16 | 16 | 24
tWTRS : 4 | 4 | 4
tWTRL : 8 | 10 | 12
tWR : 16
tRCPage : Auto
tRDRDSCL : 4
tWRWRSCL : 4
tRFC : 288
tRFC2 : 214
tRFC4 : 177
tCWL : 16
tRTP : 8 | 10 | 12
tRDWR : 8
tWRRD : 3
tWRWRSC : 1
tWRWRSD : 6
tWRWRDD : 6
tRDRDSC : 1
tRDRDSD : 4
tRDRDDD : 4
tCKE : 1

ProcODT : 40
Cmd2T : 2T
Gear Down Mode : Disabled
Power Down Enable : Disabled
RttNom : Disabled | RZQ/7 | RZQ/5
RttWr : RZQ/3 | RZQ/3 | RZQ/3
RttPark : RZQ/1 | RZQ/1 | RZQ/1

MemCadBusClkDrvStren : 24 | 24 | 24 | 60
MemCadBusAddrCmdDrvStren : 20| 20 | 24 | 20
MemCadBusCsOdtDrvStren : 20 | 24 | 24 | 24
MemCadBusCkeDrvStren : 24 | 24 | 24 | 24

i used a Kit F4-3600C14-32GTZN + ROG Crosshair VIII Dark Hero with Bios 3801 + Ryzen 5800x Stock

or i do something wrong? i will get stable 3800CL16


----------



## Audioboxer

mongoled said:


> Thanks for that, I can't post my setup and require a CMOS reset when I attempt that.
> 
> So you are OK running Y-Cruncher with tCL @13?


I've got an image somewhere with 7 passed cycles with this profile but I can't find it since installing my new NVMe drive and clean installing Windows lol










Had time to let 3 cycles pass there just to show nothing failing quickly.

That's the "tightest" profile with tRP on 12, I've been running tRP 14 recently.


----------



## anta777

*LxT1N*
your tRFC=296


----------



## LxT1N

anta777 said:


> *LxT1N*
> your tRFC=296


how do you get this result?


----------



## mongoled

Audioboxer said:


> I've got an image somewhere with 7 passed cycles with this profile but I can't find it since installing my new NVMe drive and clean installing Windows lol
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Had time to let 3 cycles pass there just to show nothing failing quickly.
> 
> That's the "tightest" profile with tRP on 12, I've been running tRP 14 recently.


Thats fine, mine almost instant fails, the fact that you can get some complete cycles done is enough for me


----------



## anta777

150 ns in ticks, rounded up to the nearest multiple 8 and +8


----------



## Luggage

LxT1N said:


> how do you get this result?











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


For example https://www.cs.utah.edu/~rajeev/pubs/shevgoor-phd.pdf https://users.ece.cmu.edu/~omutlu/pub/salp-dram_isca12.pdf + the entire list of references




www.overclock.net


----------



## LxT1N

are there right? or what i need to changed


----------



## K0N574N71N

LxT1N said:


> [...]


I'm curious - do you have Vanguard (Riot AntiCheat) installed?


----------



## LxT1N

K0N574N71N said:


> I'm curious - do you have Vanguard (Riot AntiCheat) installed?


yes


----------



## K0N574N71N

LxT1N said:


> yes


in case you're wondering... its vanguard thats blocks those values in the right column from being read


----------



## umea

K0N574N71N said:


> in case you're wondering... its vanguard thats blocks those values in the right column from being read


Oh of ****ing course lol thank you I will disable it next time... Was always confused why it would randomly not work.


----------



## K0N574N71N

umea said:


> Oh of ****ing course lol thank you I will disable it next time... Was always confused why it would randomly not work.


for me personally disabling vanguard hasn't helped. it broke zentimes completely, so eventually i had to install a separate OS for benching and testing


----------



## LxT1N

for dual rank 2x16gb ram which Rtt need to used? for Crosshair VIII Dark Hero? i used slot 2 und 4? on the board

RttNom : RZQ/7
RttWr : RZQ/3
RttPark : RZQ/3


----------



## Audioboxer

K0N574N71N said:


> in case you're wondering... its vanguard thats blocks those values in the right column from being read


Jeez oh, that's pretty screwy. Anticheat software that pretty much screws about with your system in a way it would claim it's trying to stop you doing to cheat in a game 😂



LxT1N said:


> for dual rank 2x16gb ram which Rtt need to used? for Crosshair VIII Dark Hero? i used slot 2 und 4? on the board
> 
> RttNom : RZQ/7
> RttWr : RZQ/3
> RttPark : RZQ/3


6/3/3 and 7/3/3 is commonly used but it's going to be tailored to your system/memory and what works for someone else might not be the numbers for you.


----------



## LxT1N

thx beacuse i have there on Auto and i get

RttNom : Disabled
RttWr : RZQ/3
RttPark : RZQ/1

thats because i ask


----------



## Audioboxer

LxT1N said:


> thx beacuse i have there on Auto and i get
> 
> RttNom : Disabled
> RttWr : RZQ/3
> RttPark : RZQ/1
> 
> thats because i ask


Auto runs that on just about everyone's dual rank. I believe it's fine with GDM enabled because GDM can dynamically change what it wants for stability. Once you go GDM disabled that is when you need to fine tune things like Rtts and DrvStr, especially if you aim for 1T.

Nearly everyone in this topic will run GDM disabled because it _can_ result in better performance overall, but more importantly it lets you know what is unstable down to individual timings where with GDM enabled it _might_ be masking or hiding instability. Basically, GDM enabled _could_ be harder to diagnose errors.


----------



## LxT1N

and what about the ProcODT? need to put there Auto?


----------



## Audioboxer

LxT1N said:


> and what about the ProcODT? need to put there Auto?


36.9 is the starter if you're on Ryzen 5xxx. Mine likes 34.3. Again, can depend on what speed you want to run, what timings, what command rate and so on. Sometimes changing Proc helps with stability.


----------



## LxT1N

yes i have 5800x and dark hero

and i habe another question how i know which timming i can put on 

tRDWR : 
tWRRD :


----------



## Audioboxer

LxT1N said:


> yes i have 5800x and dark hero
> 
> and i habe another question how i know which timming i can put on
> 
> tRDWR :
> tWRRD :


I don't know of specific formula myself but tWRRD is often 3 on DR, it works for me. If I leave it on auto it goes to 1, which also passes stability tests but Veii recommended 3 a while back.

tRDWR will partly depend on what you have tCWL set to, I can do 14/8, but when going to 12 tCWL lowest I can go is 9. 14/9, 14/10 and 14/11 I've seen as well. Just depends what your sticks can do.


----------



## LxT1N

my tCWL are 16 so i can put there 8?


----------



## K0N574N71N

anta777 said:


> CL=CWL even
> CWL=CL-1 odd
> RAS=RC-RP
> RP=RCD
> WR=CL even 100% stable
> WTRL=RTP=WR/2
> WTRS=3(4)
> RCDWR=8
> SC=CCDS-3=1
> SCL=CCDL-3=2,3,4
> SD=DD
> RDRDSD/DD=4+RPRE-1
> WRWRSD/DD=4+WPRE-1
> RDWR=CL-CWL+5+WPRE
> WRRD=CWL-CL+4+RPRE
> tRFC ns convert timings, round up to the nearest divisible by 16.


----------



## LxT1N

so i have tunning my kit with baseline 56 on the addrcmdsetup i tested it right now with [email protected] why my latency are ca 60?


----------



## Skull_Angel

LxT1N said:


> View attachment 2528435
> View attachment 2528436
> 
> 
> so i have tunning my kit with baseline 56 on the addrcmdsetup i tested it right now with [email protected] why my latency are ca 60?


IIRC, AddrCmdSetup will add latency since it's a delay, more than likely it's hiding issues with your other settings as well which mey be auto-corrected further adding to latency. Just eyeballing, some secondaries may be too tight if you haven't tailored interrupt and cad_bus for you individual setup.


----------



## Blameless

Alright, pretty sure I've got these setting stable:









Pulled the 2x32GiB of OEM Samsung 16Gb M-die I was using as it likes completely different drive strengths than the Micron 16Gb E-die stuff (not to mention a voltage wall on one of the DIMMs just under the sable voltage of everything else), and slapped in a 2x16GiB kit of 3200MT/s single sided Timetec stuff that I got for free, which said it was Hynix CJR, but is actually also the same 16Gb Micron E-die as in the OEM Kingston DIMMs in my main slots.

Had to bump vSoC, VDDP, and increase the resistance on AddCmdDrvStr, but it's now passing everything I can throw at it.

Tried GDM disabled, and it was actually fairly easy to stabilize, but it's also slightly slower, because I need to loosen tRDRDSCL to 5.

Not going to match many B-die setups, but it's not bad for 96GiB of mismatched garbage I paid ~200 dollars for.


----------



## TimeDrapery

Skull_Angel said:


> IIRC, AddrCmdSetup will add latency since it's a delay, more than likely it's hiding issues with your other settings as well which mey be auto-corrected further adding to latency. Just eyeballing, some secondaries may be too tight if you haven't tailored interrupt and cad_bus for you individual setup.


@Skull_Angel 

The setup timings do add latency but it's measured in picoseconds

Often performance will outweigh the picoseconds in overclocking use cases


----------



## Taraquin

LxT1N said:


> View attachment 2528435
> View attachment 2528436
> View attachment 2528450
> 
> 
> so i have tunning my kit with baseline 56 on the addrcmdsetup i tested it right now with [email protected] why my latency are ca 60?


It might be slightly too low soc voltage or iod voltage, that gives latency penalty. Try for instance 1.12v soc, 1.06 iod, 0.94 ccd and 0.9 vddp


----------



## Mach3.2

LxT1N said:


> View attachment 2528435
> View attachment 2528436
> View attachment 2528450
> 
> 
> so i have tunning my kit with baseline 56 on the addrcmdsetup i tested it right now with [email protected] why my latency are ca 60?


Try running aida on a clean windows install, you should be getting closer to 55ns or sub 55ns.


----------



## LxT1N

Taraquin said:


> It might be slightly too low soc voltage or iod voltage, that gives latency penalty. Try for instance 1.12v soc, 1.06 iod, 0.94 ccd and 0.9 vddp


this is what i have there

VDDSOC Voltage = 1.1v
DRAM = 1.45v
VDDG CCD Voltage = 0.95v
VDDG IOD Voltage = 1.05v
CLDO VDDP Voltage = 0.975v


----------



## jamsee

Please tell me what to improve I'm too lazy to figure it out myself


----------



## Taraquin

LxT1N said:


> this is what i have there
> 
> VDDSOC Voltage = 1.1v
> DRAM = 1.45v
> VDDG CCD Voltage = 0.95v
> VDDG IOD Voltage = 1.05v
> CLDO VDDP Voltage = 0.975v


Yeah, I saw that, and that is why I suggest slightly higher soc and iod and lower ccd and vddp. Can you try again but change the voltages as I suggested to see if it improves?


----------



## LxT1N

Taraquin said:


> Yeah, I saw that, and that is why I suggest slightly higher soc and iod and lower ccd and vddp. Can you try again but change the voltages as I suggested to see if it improves?


if i put 0.95 on my iod i have then problem (disconnected) on my logitech 🖱


----------



## Taraquin

LxT1N said:


> if i put 0.95 on my iod i have then problem (disconnected) on my logitech 🖱


Read what I wrote  1.12v sov, 1.06 iod, 0.94 ccd, 0.9 vddp


----------



## Danny.ns

jamsee said:


> View attachment 2528455
> 
> Please tell me what to improve I'm too lazy to figure it out myself


This is great but have you tried;
2T instead of GDM. I assume you have already tried 1T.
SCLs at 2
tRTP at 5 or 6 (5 with 2T, 6 with GDM)


----------



## jamsee

Danny.ns said:


> This is great but have you tried;
> 2T instead of GDM. I assume you have already tried 1T.
> SCLs at 2
> tRTP at 5 or 6 (5 with 2T, 6 with GDM)


This command rate configuration seems the best/easiest so probably not going to change it. I'll try SCLs at 2 and tRTP at 6 and stress test the next night, thanks


----------



## LxT1N

what are the max temperature for the ram kit on zen3?


----------



## Akex

Hi, it's been a while since I've been there, too busy with work.
I got my cousin's PC, he has 4x8 Crucial Micron E-Die C9BVK, I noticed the voltage scaling for tRC and tRFC is zero. Also I am annoying because I cannot follow the basic rule tRC = tRP + tRAS because below 50 impossible to boot. Same for tRFC, below 600 impossible to boot.
I peeled a lot of message, but the topic before too quickly to be able to find an answer to my question: What rule should I apply for tRC?
If in passing you see any inconsistency in the timings let me know. On the image only tRC and tRFC are not optimized, in auto.
@Veii Not that the opinion of others does not interest me far from there, but I must admit that your explanations are always clear and precise, if ever you are still among us, a quick little analysis is no refusal.
Welcome to all who can enlighten me on the EDie Micron.


----------



## Hale59

Slightly off-topic, but here is an app: Core-to-Core latency test and latency heat map generator:









Releases · CXWorld/MicroBenchX


Micro benchmarks CPU/GPU. Contribute to CXWorld/MicroBenchX development by creating an account on GitHub.




github.com





And you can create your heatmap picture:











https://www.capframex.com/assets/static/latency-heatmap.html



*EDIT: *It can be tested on both AMD and Intel


----------



## Blameless

Akex said:


> I got my cousin's PC, he has 4x8 Crucial Micron E-Die C9BVK, I noticed the voltage scaling for tRC and tRFC is zero. Also I am annoying because I cannot follow the basic rule tRC = tRP + tRAS because below 50 impossible to boot. Same for tRFC, below 600 impossible to boot.


Fairly typical for E-die.



Akex said:


> I peeled a lot of message, but the topic before too quickly to be able to find an answer to my question: What rule should I apply for tRC?


Still tRP + tRAS. Or more specifically, in your case, the tightest tRC you can run, minus tRP, should be your tRAS.


----------



## anta777

*Akex*
tRP=18
tRC=60 tRAS=42 or 59/41,58/40,57/39,56/38 etc
tRFC=600
tWR=12 tRTP=6
tWTRL=10(9,8,7,6)

SD only dualrank , you =1 or auto
DD only 4 DIMM


----------



## Frosted racquet

What timings can I try tightening with DR Hynix CJR? I had to increase tRDWR from 8 to 10, increase VDIMM to 1.38v, otherwise I had a lot of errors on XMP settings.
Still get an occasional error 0 with 1usmus and error 1 with Universal profiles. Tried increasing tWTRS from 5 to 6 but seems to error out sometimes.

Increasing frequency is difficult, 3733 I get WHEA 19 unless I increase vSOC but then I get a lot of error 6 and BSOD


----------



## Blameless

Frosted racquet said:


> What timings can I try tightening with DR Hynix CJR? I had to increase tRDWR from 8 to 10, increase VDIMM to 1.38v, otherwise I had a lot of errors on XMP settings.
> Still get an occasional error 0 with 1usmus and error 1 with Universal profiles. Tried increasing tWTRS from 5 to 6 but seems to error out sometimes.
> 
> Increasing frequency is difficult, 3733 I get WHEA 19 unless I increase vSOC but then I get a lot of error 6 and BSOD


tRCDWR, tRC, tRRD_S & _L, tFAW, and tRTP/tWR can probably be tightened significantly. tWTR_S & L should be able to handle a bit tighter. Sometimes setting RttNom to 34 or 40ohm can help.

A lot of mediocre bin CJR cannot handle tight primaries without active cooling or excessively loose subtimings. Sometimes the best results are achieved by loosening the primaries and tightening up everything else as far as is practicable.

This is one of my budget Timetec CJR DR kits at 1.32v:









That said, errors on XMP settings sounds like a serious misconfiguration somewhere, or defective memory.


----------



## LxT1N

i habe a question if i changed my CLDO VDDP Voltage = 0.9v go my automatic the tPHYRDL from 26 to 28? are this normal i have read the 26 are better then 28 are this right any help about the tPHYRDL?


----------



## Frosted racquet

Blameless said:


> tRCDWR, tRC, tRRD_S & _L, tFAW, and tRTP/tWR can probably be tightened significantly. tWTR_S & L should be able to handle a bit tighter. Sometimes setting RttNom to 34 or 40ohm can help.


I've previously tried tRRD_S/L and tFAW 6,6,24 and increased tFAW to some other value I can't remember, both with errors. The problem is I still don't have a 100% stable baseline. I don't know if changing some parameters introduces new errors or are they the same old issues still lingering.

I'll start with tRCDWR and see how it goes.



Blameless said:


> That said, errors on XMP settings sounds like a serious misconfiguration somewhere, or defective memory.


I've seen other people with the same issues with TM5. I can pass y-cruncher 10+ hours, HCI Memtest 1000%, RamTest ~6000% and Memtest86+without errors with XMP, only TM5 poses a problem.








Memory Testing with TestMem5 TM5 with custom configs


Opps....posted link in wrong thread. lol




www.overclock.net


----------



## mongoled

Frosted racquet said:


> I've previously tried tRRD_S/L and tFAW 6,6,24 and increased tFAW to some other value I can't remember, both with errors. The problem is I still don't have a 100% stable baseline. I don't know if changing some parameters introduces new errors or are they the same old issues still lingering.
> 
> I'll start with tRCDWR and see how it goes.
> 
> 
> I've seen other people with the same issues with TM5. I can pass y-cruncher 10+ hours, HCI Memtest 1000%, RamTest ~6000% and Memtest86+without errors with XMP, only TM5 poses a problem.
> 
> 
> 
> 
> 
> 
> 
> 
> Memory Testing with TestMem5 TM5 with custom configs
> 
> 
> Opps....posted link in wrong thread. lol
> 
> 
> 
> 
> www.overclock.net


Which TM5 config are you using ??


----------



## Frosted racquet

1usmus and Universal mostly


----------



## mongoled

Frosted racquet said:


> 1usmus and Universal mostly


What error is the 1usmus v3 config throwing ?


----------



## Frosted racquet

With the screenshot above (modified XMP profile, tRDWR from 8 to 10, increase VDIMM to 1.38v) sometimes I get error 0 usually after 15+ cycles, sometimes I can pass 25 cycles without errors.
I'm suspecting tRRD and tWTR, but from what I can see both are pretty loose.


----------



## mongoled

Frosted racquet said:


> With the screenshot above (modified XMP profile, tRDWR from 8 to 10, increase VDIMM to 1.38v) sometimes I get error 0 usually after 15+ cycles, sometimes I can pass 25 cycles without errors.
> I'm suspecting tRRD and tWTR, but from what I can see both are pretty loose.


Thats not the 1usmus v3 config though is it ?


----------



## Frosted racquet

mongoled said:


> Thats not the 1usmus v3 config though is it ?


No, meant with those ZenTimings settings


----------



## mongoled

Frosted racquet said:


> No, meant with those ZenTimings settings


OK im with you,

I dont have experience with DR Hynix CJR, though a couple of generic suggestions.

First are you able to increase RttPark to RZQ/2 or RZQ/3 ?

Also in combination with the RttPark change, I would first decrease voltage and if that does not work increase it slightly

I remember tweaking a set of Corsair CMK32GX4M2D3600C18 modules and less voltage was better, anything above 1.38v and I was getting weird stability issues, hence the reason I suggest weakening RttPark.

Hopefully CJR owners can chime in


----------



## Blameless

Frosted racquet said:


> I've seen other people with the same issues with TM5. I can pass y-cruncher 10+ hours, HCI Memtest 1000%, RamTest ~6000% and Memtest86+without errors with XMP, only TM5 poses a problem.


That's why we're using TM5. The errors it detects are real and an actually stable memory subsystem will pass it.

If XMP settings aren't stable and you're sure there aren't problems elsewhere (CPU or IMC), then the memory is defective by virtue of not being stable at it's rated specifications. Unfortunately, this is not terribly uncommon. Most module builders seem to leave very little in the way of margins for their various bins...banking on few of their customers really checking things out.


----------



## Toma

Akex said:


> Hi, it's been a while since I've been there, too busy with work.
> I got my cousin's PC, he has 4x8 Crucial Micron E-Die C9BVK, I noticed the voltage scaling for tRC and tRFC is zero. Also I am annoying because I cannot follow the basic rule tRC = tRP + tRAS because below 50 impossible to boot. Same for tRFC, below 600 impossible to boot.
> I peeled a lot of message, but the topic before too quickly to be able to find an answer to my question: What rule should I apply for tRC?
> If in passing you see any inconsistency in the timings let me know. On the image only tRC and tRFC are not optimized, in auto.
> @Veii Not that the opinion of others does not interest me far from there, but I must admit that your explanations are always clear and precise, if ever you are still among us, a quick little analysis is no refusal.
> Welcome to all who can enlighten me on the EDie Micron.
> 
> View attachment 2528467


These are my settings try to see if they work for you


----------



## KedarWolf

anta777 said:


> it is more correct to increase the testing time - up 2000%-10000%, rather than the number of cycles
> 
> For you:
> tRAS=23 max tRAS for tRCconstanta - better
> tCWL=14
> RDWR=8
> WRRD=4 or 5
> tRFC=256 or 248
> 
> Why RCDRD<RP ?
> RP=16
> and
> decrease RC with RAS


tCWL 12 gives me better write and copy in AIDA, tWRRD at 1 better too, tRDWR needs to be at 10 for tCWL 12, tRFC is according to the tRFC calculator, tRP 16 tRAS 26 gives me worst results and harder to get stable than my settings at 19-23 which started out as an experiment suggested by @Veii and I find really works well.

I DID change tRAS to 23 though, helps with latency a bit to have tRP+tRAS=tRC.

The TM5 is 3 cycles of Universal at 1000% I ran overnight.


----------



## Frosted racquet

mongoled said:


> First are you able to increase RttPark to RZQ/2 or RZQ/3 ?


Tried with RttPark RZQ/2 (120Ohm in BIOS I think), left VDIMM @1.38v; passed 10 cycles of Universal and 25 cycles of 1usmus, which is the first time I could pass both consecutively without errors. Now I'm running RamTest until 20000+% just in case. Afterwards will try with XMP settings + modified RttPark to rule it out as the only problematic setting.
Next, decreasing tRRD, tWTR etc. Fingers crossed it behaves better with new RttPark.


Blameless said:


> That's why we're using TM5. The errors it detects are real and an actually stable memory subsystem will pass it.
> 
> If XMP settings aren't stable and you're sure there aren't problems elsewhere (CPU or IMC), then the memory is defective by virtue of not being stable at it's rated specifications. Unfortunately, this is not terribly uncommon. Most module builders seem to leave very little in the way of margins for their various bins...banking on few of their customers really checking things out.


I'd agree with you but the way I see it there are two issues here:
-XMP profile doesn't dictate secondary or tertiary timings, that's the motherboards job. It's highly likely my MSI B550I ITX doesn't have a robust memory system and secondary/tertiary timings are at fault.
-Sending the RAM back for warranty won't yield any results as they'd probably just run memtest86+ and call them fault free...


----------



## Blameless

Frosted racquet said:


> -XMP profile doesn't dictate secondary or tertiary timings, that's the motherboards job. It's highly likely my MSI B550I ITX doesn't have a robust memory system and secondary/tertiary timings are at fault.


XMP 2.0 can include more and usually has at least the tRCs and RRDs and TFAW, while the JEDEC or AGESA formulae for the rest should work. Of course, none of this is a given and manual tuning should be better anyway.

Your MSI B550I should be a fairly solid board for memory OCing though. MSI usually keeps up with firmware pretty well and only having two slots is an advantage.



Frosted racquet said:


> -Sending the RAM back for warranty won't yield any results as they'd probably just run memtest86+ and call them fault free...


True.


----------



## LxT1N

this are what i get on windows 11 with my 16-16-16-16-32-48 are this okay? i see much people got low latence then me but i dont know why


----------



## Veii

LxT1N said:


> View attachment 2528532
> 
> 
> this are what i get on windows 11 with my 16-16-16-16-32-48 are this okay? i see much people got low latence then me but i dont know why


Try this patch, and report back if it helps please
kb numbers can be just written out, mb needs to be converted down to kb
Be sure to switch it to decimal instead of hex
Also grab the Win 11 chipset drivers







Win+R , type WinVer , just to know what you run


----------



## LxT1N

this?


----------



## Veii

LxT1N said:


> View attachment 2528537
> 
> 
> this?


?
Registry patch, from L1, L2 L3 visible values
First = 512
Secondary = 4096
Third = 32768


----------



## KedarWolf

Veii said:


> ?
> Registry patch, from L1, L2 L3 visible values
> First = 512
> Secondary = 4096
> Third = 32768


I edited my registry in Windows 10 for my 5950x with its L1, L2 and L3 cache sizes and I find it helps AIDA64, even latency a bit.

I'm waiting for the fix patches in a week or two before moving to Windows 11 though.


----------



## Veii

KedarWolf said:


> I'm waiting for the fix patches in a week or two before moving to Windows 11 though.


Am waiting for a confirmation before moving myself over again
Have to reinstall anyways here 
Then need to see how to configure opt-offl for Win11 ProWS


----------



## Blameless

I'm highly doubtful those registry entries are doing anything.

SecondLevelDataCache is something that started cropping up as a tuning recommendation in the 1990s and MS told people to stop using it about 15 years ago because it only works if the HAL can't detect cache size on parts with direct mapped caches, which haven't been used by any x86 architecture after the original P6/Pentium Pro, IIRC. I'm not sure any version of Windows ever even parsed those L1 and L3 entries and I'm pretty sure Windows stopped parsing "SecondLevelDataCache" after Windows XP.

Cache should be totally transparent to the OS.









Optimizing Your Memory Configuration






docs.microsoft.com










Microsoft KB Archive/183063 - BetaArchive Wiki







www.betaarchive.com


----------



## KedarWolf

Blameless said:


> I'm highly doubtful those registry entries are doing anything.
> 
> SecondLevelDataCache is something that started cropping up as a tuning recommendation in the 1990s and MS told people to stop using it about 15 years ago because it only works if the HAL can't detect cache size on parts with direct mapped caches, which haven't been used by any x86 architecture after the original P6/Pentium Pro, IIRC. I'm not sure any version of Windows ever even parsed those L1 and L3 entries and I'm pretty sure Windows stopped parsing "SecondLevelDataCache" after Windows XP.
> 
> Cache should be totally transparent to the OS.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Optimizing Your Memory Configuration
> 
> 
> 
> 
> 
> 
> docs.microsoft.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Microsoft KB Archive/183063 - BetaArchive Wiki
> 
> 
> 
> 
> 
> 
> 
> www.betaarchive.com


If "the system attempts to retrieve the L2 cache size from the Hardware Abstraction Layer (HAL) for the platform. If it fails, it uses a default L2 cache size of 256 KB." is a bug with Windows and HAL then maybe manually setting it is why it helps?


----------



## Veii

Waiting for @LxT1N to confirm whereever this does anything at all & show which version he/she runs
Funnily, if you put load on the OS , then cache behaves correctly.
Something appears to hardthrottle it.
Could be resolved with current chipset updates, could all be nonsense.
On Win 10 i saw nothing, sadly 

Waiting for a reply


----------



## KedarWolf

Veii said:


> Waiting for @LxT1N to confirm whereever this does anything at all & show which version he/she runs
> Funnily, if you put load on the OS , then cache behaves correctly.
> Something appears to hardthrottle it.
> Could be resolved with current chipset updates, could all be nonsense.
> On Win 10 i saw nothing, sadly
> 
> Waiting for a reply


Microsoft is releasing an update soon which is supposed to fix the L3 cache issue and soon after AMD is releasing a chipset driver which fixes the preferred cores problem.


----------



## LxT1N

im right know at work i can try it later


----------



## Blameless

KedarWolf said:


> If "the system attempts to retrieve the L2 cache size from the Hardware Abstraction Layer (HAL) for the platform. If it fails, it uses a default L2 cache size of 256 KB." is a bug with Windows and HAL then maybe manually setting it is why it helps?


As Microsoft has been stating for decades, this entry should only be relevant for direct-mapped caches. The HAL is also almost certainly not failing to identify the capabilities of processors where the correct driver has been loaded and the cache size is being listed accurately in Task Manager.

Even if, by chance the L2 size wasn't being detected and Windows wasn't managing memory in a way that allowed optimal utilization, the impact should be minimal-to-nonexistent on the 8-way associative L2 current AMD parts have. I can't completely rule out the SecondLevelDataCache setting having an effect on some setups, but I'd need to see benchmarks that couldn't be put down to scheduling, turbo, or memory training variations. I'm also doubtful that combining L2 would even be the correct way to set this variable, even if it were being parsed and was actually influencing the memory manager.

Regardless, setting L1 & L3 cache sizes wouldn't make any sense. On this architecture, the L2 is the largest layer of the inclusive caches, so anything above or below it in the hierarchy is wholly transparent to the OS memory manager irrespective of any associativity. Perforce, everything in the L1 is in the L2, and the L3 is only filled with L2 evictions. Even if it's possible to specify these cache sizes via the registry--and I do not believe it is, because I cannot find any mention of those entries in any official or semi-offical source--they shouldn't do anything.


----------



## Audioboxer

Super busy the past day but just quickly stopping by to post this First Windows 11 Patch Tuesday Makes Ryzen L3 Cache Latency Worse, AMD Puts Out Fix Dates as lol @ MS/Windows 11.



> In our own testing, a Ryzen 7 2700X "Pinnacle Ridge" processor, which typically posts an L3 cache latency of 10 ns, was tested to show a latency of 17 ns. This was made much worse with the October 12 "patch Tuesday" update, driving up the latency to 31.9 ns.


Don't mind us, we'll just make things... even worse, for the next week or so.


----------



## KedarWolf

Veii said:


> Waiting for @LxT1N to confirm whereever this does anything at all & show which version he/she runs
> Funnily, if you put load on the OS , then cache behaves correctly.
> Something appears to hardthrottle it.
> Could be resolved with current chipset updates, could all be nonsense.
> On Win 10 i saw nothing, sadly
> 
> Waiting for a reply











Microsoft's Windows 11 Ryzen-fixing PC patches are due to be released next week


AMD's cache latency and CPPC issues will soon be resolved




www.overclock3d.net


----------



## Ethelneth

anta777 said:


> there is a parabola dependence
> ns in ticks, round up to a multiple of 8 and +8.
> 
> For 16-Gbit chips (micron,hynix,samsung)
> ns (table Reous) in ticks, round up to a multiple of 16 and +16.


@anta777 I'm currently running the following:









do you recommend switching to tRFC 576 for 16Gb micron ICs? What about tRFC2 and 4? Should I run the usual tRFC/35*26 and tRFC/35*16?


----------



## Veii

KedarWolf said:


> Microsoft's Windows 11 Ryzen-fixing PC patches are due to be released next week
> 
> 
> AMD's cache latency and CPPC issues will soon be resolved
> 
> 
> 
> 
> www.overclock3d.net


Yes yes
But the test for this reg patch aside

"Just a bug by Microsoft"
A bug that intentionally does recognize CPPC tags and intentionally throttles cores down till load is applied
A bug that intentionally does more work instead of resulting in just "slower" cache but not sleeping cache 🤭
I am waiting for this too - but want to know more about this thing you posted. It did nothing for me on Win 10 and shouldn't do anything
Question is, why does it remain in registry. MS is known to clean their stuff at least once a decade. Win95 has been more than 1 & 1/2 decades 
======================================
I gave Anta's Team, config now neutral 2 weeks - likely more. Neutral testing on anything that is possible
I think i'll abandon it permanently, nearly sure but not entirely. Want to give it slightly bit more time ~ to be 100% confident not to use it

The config guaranteed breaks beyond 1.6vDIMM.
It makes now sense why it was warned not to run it over 1.56v
It has no connection to the timings used and i wasn't so far capable to find any powering combination making it function (i really tried to make it work _~somehow~_)
With all published fixes, % testing time calculations or cycle extensions. It guaranteed breaks on the start of the 2nd cycle. It doesn't matter if on cycle takes 28min, or 60min. The design is the fault

I think everything Anta777 wrote and learning by Serj about it's design ~ remains SerJ's design and has truth
But it is very clear to me now ~ that both configs differentiate in the methods they function.
It wouldn't matter how "well" they function, but they are a completely different design and not comparable
For a config that i can tell no working difference & working-type difference ~ to GSAT, HCI or Karhu. From something i can not tell apparat by all other programs & that strains the CPU too much ~ being able to error by the CPU instead by the RAM.
I see no reason to stick with it

MemOC is frustrating that way, when it can be everything and nothing at the same time.
Why should i run this vs GSAT for example. At least on GSAT there are no potential voltage testing issues.
Anywho, it's too early to write critique. Just want to sneak peek say ~ that the plans nearly are made. Unless i magically find a reason why i should prefer it

So far, it looks like a program that tests discharge with quite high strain and has nearly no connection to anything timing related. (learning when it errors and when not)
This is the conclusion i came to, after 20 different types of attempts getting along with this config and methodic of testing. Zero , well 1
If i pull voltage back, anything i trow at it passes. (even on stock stock CPU freq). But it is too harsh for weak PCBs ~ to be a timings only test. I see by such results & behavior no reason to even bother with it.
It doesn't find errors "faster" . It doesn't show the reason for errors
(yes that was how SerJ educated, but 1usmus config clearly behaves different ~ undoubtfully & consistent)
It doesn't stress the CPU less than any other LinX , MemtestPro, HCI, GSAT test out there (which are suboptimal for testing RAM timings but rather test whole fabric stability ~ soo errors can be influenced by such too)
Sadly i can not see neutrally why i should bother with it. I can not see any usecase ~ but i'll give it slightly bit more attempts, purely out of respect for the work.

Later Arshia + Anta config will be tested, maaybe that one is not broken when it comes to VDIMM amount ~ maaybe it is different in the testing methodology, we'll see.
And maybe Anta's personal configs are fine - but this version here, is broken for high VDIMM. Now i understand the reason for the warning ~ yet not the reason for the clear issue.
* Oh if all goes according to plan, i'll have a 5900X for a week to test with the 2x16GB 4000C16-16 dimms. I think it is now time (next week)


----------



## Sleepycat

After 10 months of trying to get my 4x16GB 3200 CL14 kit to OC as high as possible with stability, this is where I have landed on. I know of others with similar 3200 CL14 kits running at 3733, but for me, this is my ceiling. Due to my ceiling of 3600, I've been focusing on tightening subtimings instead.

But nothing above 3600 will POST, not even at CL16 or CL18, with vSOC up to 1.2V and VDIMM up to 1.5V.

So reaching out to Anta777 and Veii to get any other suggestions that I can do. I been slightly tightening certain sub timings based on the posts here, and even a change of 1 in those subtimings trigger an error in TM5. Am I missing on one of the Rtts or DrvStr which is limiting my ability to hit 3666. This is running on 1.465 VDIMM.


----------



## Veii

Sleepycat said:


> But nothing above 3600 will POST, not even at CL16 or CL18, with vSOC up to 1.2V and VDIMM up to 1.5V.
> 
> So reaching out to Anta777 and Veii to get any other suggestions that I can do. I been slightly tightening certain sub timings based on the posts here, and even a change of 1 in those subtimings trigger an error in TM5. Am I missing on one of the Rtts or DrvStr which is limiting my ability to hit 3666. This is running on 1.465 VDIMM.


If you touch anything, you will need to push tRDWR up
My personal math says 9+ , 8 likely only runs as everything is low
tCCD_ we have to depend on AMD's _great training_ algorithm

Anta's recommendation for tWR = tCL gives nice bandwidth numbers - but you have to pair that with tWTR_S 3 or lower
Like 3-8
tRRD_ you should push, that is to my 16-16 and downwards experiments, the key factor allowing me to run 15-15 at all, or 14-14 till 4067MT/s on this "bad" 4000C19-19 kits
Voltage aside, tRRD_ you should slow down.
You don't need fast transition timings and slow primaries. Primaries are more worth. Tertiaries are for later.

Running both SD's higher - means to my experience more bandwidth , but they will overlapp.
Higher capacity needs them at lower values.
tWTR_L does directly affect Read Bandwidth & tWTR_S was copy. tWR was also Read
I can't remember my exact findings, but i've posted it here.

What matters for stability distance between both tRRD_
What matters for bandwidth is each of the values (SCL, WR, tWTR_S & _L
tFAW doesn't matter thaat much , but you will lose Read Bandwidth if tRRD_S is pushed. Yet this is crucial sometimes ~ up to PCB and strain

I've never played with such capacity, to give advices ~ but pretty sure if these are 4x dual rank, you want to run the normal BankGroupSwap & at absolute worst double tWR if needed
tCL = tWR remains a great lesson - while lowering tWR 10, tRTP 5 , can work out ~ matching it with tCL has first stability priority (i can confirm Anta's teaching)
======================
You surely want to push CsOdtDrvStr to at least 30, and see if you can get away with the rest being 20ohm. This is trace length dependent
Such high capacity i expect should run 120-20-20-24, or 60-20-30-20, maybe even 60-20-40-20
Mostly it's not any holes, but just bad training. It still is not fixed

If my predictions would be accurate,
4x16 should need around 40-42ohm, the one above 40ohm procODT
I do feel tho, that 6-3-3 is a bit too . . . weak, for it.
If you still move bellow 1.45v, give 7-3-2 a try.
Else bump to 1.48v and give 6-3-2 or even be stupid (try pls) and see how 5-2-3 behaves. (if it will post at all @ 3400 & higher MT/s) . I fear for such WR_2 might mess things up, but it surely can help you here

IOD shouldn't need much of a push , but what about
950-980-1060-1125mV
VDDP-CCD-IOD-SOC
SOC should at least be 1.1vGET, the rest are SET values
======================
Short advices
tWR 14
tWTR_L 8, if that causes issues drop tWTR_S to 3 and tWTR_L to 8 ~ that has to run then. If that has issues, drop both SD, DD's to 1-4-4-1-6-6 at least or ignore it but give tRDWR +1


----------



## mongoled

Anyone have any experience with pushing tRP and Y-Cruncher not staying stable ?

So far tRP has not been influenced by increasing vDIMM, vSOC, vDDP etc or by changing Rtt, Cad bus etc values to an extent that Y-Cruncher will act consistently, i.e. sometime it wil crash after several cycles, sometimes in the first cycle etc etc.

Im now trying PLL 1.8v ...

Im pushing tRP @12 with tRFC @228, relaxing tRFC does not bring stability either ...


----------



## TimeDrapery

Here's my latest efforts with the 5800X and the TEAMGROUP B-die

Pretty meh so far... I'll keep plugging away


----------



## Taraquin

TimeDrapery said:


> Here's my latest efforts with the 5800X and the TEAMGROUP B-die
> 
> Pretty meh so far... I'll keep plugging away
> 
> View attachment 2528676
> 
> View attachment 2528677
> 
> View attachment 2528678


Try soc 1.1, iod 1.02, ccd 0.94 and vddp 0.9.they are way too high and eat away your powerbudget. Try trtp 6, wtrs 3, wtrl 10, 9 or 8, scl's 4.


----------



## anta777

*Ethelnet*
Micron b-die 16-gbit tRFC=290-300 ns, leave=560.
tRFC2/4 real not use for AMD.
tRAS=52-17=35


----------



## Frosted racquet

What do you suggest changing on current timings so I get rid of this error and continue tweaking the rest of the timings further?
XMP was unstable=> tRDWR from 8 to 10, 1.38v VDIMM, (maybe tWTRS from 5 to 6) and RttPark RZQ/2 fixed it.
Later modifications as follow:
tRRDS/L 6,6 tFAW 24 passed, 4,6,16 failed (don't remember the error, maybe 0 with 1usmus) so reverted back to 6,6,24
tWR 16, tRTP 8 failed as shown in screenshot


----------



## mongoled

mongoled said:


> Anyone have any experience with pushing tRP and Y-Cruncher not staying stable ?
> 
> So far tRP has not been influenced by increasing vDIMM, vSOC, vDDP etc or by changing Rtt, Cad bus etc values to an extent that Y-Cruncher will act consistently, i.e. sometime it wil crash after several cycles, sometimes in the first cycle etc etc.
> 
> Im now trying PLL 1.8v ...
> 
> Im pushing tRP @12 with tRFC @228, relaxing tRFC does not bring stability either ...


Needs some additional testing, i.e. warm boot. cold boot etc, but its passing this with increased PLL 1.8v.

Going to quickly try tCL @13 again with the raised PLL 1.8v to see if that behaves with Y-Cruncher ...

** EDIT **
PLL 1.8v increase did not help tCL @13 ...

** EDIT 2 **
So its looking like PLL 1.8v voltage has made a difference with regards to tight tRP when running Y-Cruncher, I just knocked out another 3+ hours session with no crashes, time to play with tCL @13 again and hopefully get it to hold


----------



## mongoled

Frosted racquet said:


> What do you suggest changing on current timings so I get rid of this error and continue tweaking the rest of the timings further?
> XMP was unstable=> tRDWR from 8 to 10, 1.38v VDIMM, (maybe tWTRS from 5 to 6) and RttPark RZQ/2 fixed it.
> Later modifications as follow:
> tRRDS/L 6,6 tFAW 24 passed, 4,6,16 failed (don't remember the error, maybe 0 with 1usmus) so reverted back to 6,6,24
> tWR 16, tRTP 8 failed as shown in screenshot


Decrease vDIMM to 1.37v


----------



## Blameless

Blameless said:


> Alright, pretty sure I've got these setting stable


Spoke a bit too soon on that one.

Was cycling through tests on this 2x32GiB DR + 2x16GiB SR E-die setup to verify everything was stable and had y-cruncher error out in the HNT test. After confirming it wasn't a CPU stability, SoC voltage, or vDDG issue, I spent the better part of the next two days testing various permutations of RTTs and drive strengths.

After increasing ProcODT from 40 to 43.4, RttNOM from 34 to 40, and Clk output dr from to 40 (making my output impedance straight 40s), I'm fairly confident that no test I'm familiar with will crash on this setup due to any hardware instability.

32 threads of y-cruncher HNT is quite a heavy load on both the CPU and memory. Testing in 27C ambients with reduced fan speeds and maxed out GPU load is causing the memory to crack 60C. Any increase to vDIMM pushes temps beyond what I can stabilize.

Probably should just have increased airflow and called it a day, but spending the extra time gives me that much more headroom.


----------



## heavyrain

anta777 said:


> thelnet





anta777 said:


> *mongoled*
> 1.About errors:
> tm5 can detect three kinds
> 1) tRCD,tRP,tRFC,tRRDS,tRRDL,tFAW, partially tRAS,tRC,tWR
> 2) tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE
> 3) voltage controller
> You need to adjust the timings one by one.
> -RCD,CL,RP,RRDS,RRDL,FAW,RAS,RC
> -WR,RTP,WTRL,WTRS
> -RDWR,WRRD,SD/DD,SCL
> -RFC
> 2.Errors in the tests themselves and you should have discovered them yourself long ago


so, tm5 is hard to find errors like tRDWR and tWRRD(sg,dg,dr,dd) ?


----------



## TimeDrapery

Taraquin said:


> Try soc 11, iod 1.02, ccd 0.94 and vddp 0.9.they are way too high and eat away your powerbudget. Try trtp 6, wtrs 3, wtrl 10, 9 or 8, scl's 4.


No thank you, with tCL at 15 I get tPHYDRL trained to 28/26 at lesser CLDO VDDP and the others are hella Y-Cruncher stable... I'm hoping they'll assist with stability at greater speeds than 3800MT/s, just looking to stabilize a timing set tighter than 16-16-16-16-24 before pushing speeds (hence the less tight secondaries)


----------



## anta777

RDWR,WRRD - composite timings.
RDWR=CL-CWL+5+WPRE
WRRDsd/dd=CWL-CL+4+RPRE
WRRDsg/dg only Intel =CWL+6+WTRL/WTRS
Jedec : WRRDsg/dg=CWL+4+WTRL/WTRS


----------



## TimeDrapery

anta777 said:


> RDWR,WRRD" - composite timings.
> RDWR=CL-CWL+5+WPRE
> WRRDsd/dd=CWL-CL+4+RPRE
> WRRDsg/dg only Intel =CWL+6+WTRL/WTRS
> Jedec : WRRDsg/dg=CWL+4+WTRL/WTRS


I realize you've said "only Intel" for the second to last... Where are you reading "WPRE" from to derive RDWR/WRRD?


----------



## Frosted racquet

mongoled said:


> Decrease vDIMM to 1.37v


Thanks for the reply. No dice, still same error 4 with 1usmus near the end of the test (probably after 20+ cycles the error appeared).


----------



## Skull_Angel

Frosted racquet said:


> Thanks for the reply. No dice, still same error 4 with 1usmus near the end of the test (probably after 20+ cycles the error appeared).


Do you know if you need CCD, ProcODT, AddrCmdDrvStr at those values for stability? If not, I'd try 0.9-0.94v, 34.3, 20.


----------



## Frosted racquet

Haven't experimented with those values yet, will try


----------



## LxT1N

i got this i have changed a litte bit my tuninning but i have a problem with battlefield are freezed y cruncher and tm5 got for me no problem valorant are no freezeed only on battlefiel any help?


----------



## Akex

Toma said:


> These are my settings try to see if they work for you
> View attachment 2528513


Thank you for sharing, nevertheless my preset is more efficient than yours and totally stable, I just tried to correct what was wrong and it's done.
I probably still have one or two possible improvements, but the big one is done. Result 54.3 ns (average over 10 bench) at 1.53v


----------



## Veii

TimeDrapery said:


> I realize you've said "only Intel" for the second to last... Where are you reading "WPRE" from to derive RDWR/WRRD?


SG, DG do not exist on AMD
Same as RTL/IO-L do not
For us it's tPHYRDL & tPHYWRL ~ which are on all boards identical , as AMD enforces such within their AGESA Blobs
ASUS does have sometimes the need to judge AMD for such, or supplies proprietary changes till anybody notices by a risk of backslash. Yet ASUS capital is high and they can afford such move
EVGA sits on a similar chair, but they ask AMD before engineers compile a new bios ~ as it comes encrypted to each of the boardpartners & all have to depend on their AMD Contact to forward & make the changes

Lack of access kind of is sad, but on the other side covers a bigger userbase with "acceptable results" ~ on the "it just works" thematic
(If AMD could only earn from the voltages too)
I personally wish tCCD_ access ~ when XMP to A-XMP conversion directly uses these.
They are not even made visible, alone giving users the ability to change it.
This doesn't bring AMD forward and helps nobody. They are also not in AMD CBS ~ DRAM HEX Timings 

EDIT:
We have to pray to boards getting things correct on tCWL changes
And sometimes bioses do not know tCL 12. The value 12


----------



## Taraquin

anta777 said:


> RDWR,WRRD - composite timings.
> RDWR=CL-CWL+5+WPRE
> WRRDsd/dd=CWL-CL+4+RPRE
> WRRDsg/dg only Intel =CWL+6+WTRL/WTRS
> Jedec : WRRDsg/dg=CWL+4+WTRL/WTRS


I gotta ask for the forth time anta: how do we calculate wpre and rpre?  

Did some testing yesterday on 3800cl15 1T. I tried following you rules, but wonder about a few thing. I ran 15 15 15 30 45, cwl and wr 14, rpe 7, trfc 274 (144ns). Is that they correct way? 

I have noticed that even though your recommendations gives me slightly lower performance in some cases (0.5MB lower read aida, 1.5sec dram calc) I get more consistent scores. Using 4000 16 16 16 32 48 288 trfc 16 wr 8 rtp I get 51.9-52.2 in aida almost every time. When I run 29 ras, 45 rc, 10 wr and 5 rtp I get 54-55ns flrst run, the I get 51.9-52.6. In SOTTR (cpu avg 1080 lowest) I get 234-237 with you recommendations. With the tighter timings I get anywhere from 230-238.

Is the tighter timings not always synced/adding up in cycles? Something doesn't always add up, therefore I get often better but sometimes worse performance? Don't know if you understand me, but I find this very interesting. Thank your for your patience and information though I don't always understand what you mean


----------



## mongoled

Taraquin said:


> I gotta ask for the forth time anta: how do we calculate wpre and rpre?


Dont you know its a secret (and I dont know it)


----------



## Blameless

mongoled said:


> View attachment 2528690


In my experience, the first four tests are highly unlikely to find memory errors, while N32, N64, and most especially HNT, tend to find problems soonest.


----------



## mongoled

Blameless said:


> In my experience, the first four tests are highly unlikely to find memory errors, while N32, N64, and most especially HNT, tend to find problems soonest.


Yes, very much so.

Im toying with tCL @13 with those tests, looks like A2 PCB is not able to handle the high vDIMM required for it.

Pretty much tied down tRP to 12 and the fix was more PLL 1.8v, so it seems that pushing tRP may be causing instability in FCLK.

Will post my new 24/7 16GB config soon, just waiting for Y-Cruncher to get to iteration 12 (currently on 8).

Have already completed run of TM5 1usmus v3 config, RealBench 4 hours and soon the Y-Cruncher.



** EDIT **
Completed new baseline for 2 x 8GB
15-14-14-12-26-38-228-1T

Note: APIDIS is set to 1, C-States disabled and "Typical Current" is being used, but still getting the CPU overboost bug ...










** EDIT2 **
Looks like I found something that works with tCL @13












Time for more investigation


----------



## anta777

*Taraquin*
WPRE=RDWR+CWL-CL-5
RPRE=WRRD+CL-CWL-4
Why ask the 4th time?


----------



## Luggage

anta777 said:


> RDWR,WRRD - composite timings.
> RDWR=CL-CWL+5+WPRE
> WRRDsd/dd=CWL-CL+4+RPRE
> WRRDsg/dg only Intel =CWL+6+WTRL/WTRS
> Jedec : WRRDsg/dg=CWL+4+WTRL/WTRS





anta777 said:


> *Taraquin*
> WPRE=RDWR+CWL-CL-5
> RPRE=WRRD+CL-CWL-4
> Why ask the 4th time?


Because these are the same equations just changed around? How do we get a value from this?


----------



## mongoled

Oh my, where is the popcorn emoji 

😂😂


----------



## mongoled

Luggage said:


> Because these are the same equations just changed around? How do we get a value from this?


Voodoo voodoo

😋


----------



## Taraquin

anta777 said:


> *Taraquin*
> WPRE=RDWR+CWL-CL-5
> RPRE=WRRD+CL-CWL-4
> Why ask the 4th time?


You never answered me, therefore I asked. Thank you for the reply, but as others here wonder, what is the base value. If you need rpre to find wrrd and wrrd to find rpre you have 2 unknowns, do you really wonder why I ask? I don't mean to be rude, but this is a mystery.

I understand wpre since rdwr can be calculated from half CL, but rpre remains a mystery...


----------



## anta777

write to the bios authors of your motherboard
let them add to the BIOS explicitly wpre and rpre


----------



## anta777

RPRE=1 or 2 usually.


----------



## SneakySloth

This seems to be stable now. Ran a bunch of different configs and programs to confirm. I'd have to increase VDIMM to lower timings like trfc. Lowering that beyond this point doesn't seem to help much in the benchmarks I've run.


----------



## mongoled

SneakySloth said:


> This seems to be stable now. Ran a bunch of different configs and programs to confirm. I'd have to increase VDIMM to lower timings like trfc. Lowering that beyond this point doesn't seem to help much in the benchmarks I've run.
> View attachment 2528833


If you use 1T and 56-0-0 setup timings I believe your tPHYRDL will be 26 rather than 28.

Have you tried ?

As that should improve latency and throughput ...

The only thing you may need to weak is vSOC ...


----------



## SneakySloth

mongoled said:


> If you use 1T and 56-0-0 setup timings I believe your tPHYRDL will be 26 rather than 28.
> 
> Have you tried ?
> 
> As that should improve latency and throughput ...
> 
> The only thing you may need to weak is vSOC ...


I did try enabling 1T but I mostly tried changing the DrvStrs and procODT value (with a few combinations of RTTs mixed in). Although I only spent a few hours on that, I couldn't get it to stabilize (errors within a few minutes). I don't think I tried AddrCmd at 56 though. I might give that a go, thanks for the advice.

The tPHYRDL is 28/28/26/26 right now. I think its been that ever since I added 2 more sticks of Ram.


----------



## Nd4spdvn

SneakySloth said:


> I don't think I tried AddrCmd at 56 though. I might give that a go, thanks for the advice.


It worked for me and I have the same dimms as you.


----------



## mongoled

SneakySloth said:


> I did try enabling 1T but I mostly tried changing the DrvStrs and procODT value (with a few combinations of RTTs mixed in). Although I only spent a few hours on that, I couldn't get it to stabilize (errors within a few minutes). I don't think I tried AddrCmd at 56 though. I might give that a go, thanks for the advice.
> 
> The tPHYRDL is 28/28/26/26 right now. I think its been that ever since I added 2 more sticks of Ram.


Its extremely hard to be able to run 1T without set up timings with 32GB and especially when using 4 x 8GB.

But using 56 AddrCmd should be doable, hopefully you can achieve that with few issues.

Also you would get better read throughput if you use tRDRDSCL/tWRWRSCL set to 4 or 5 rather than 2 or 3, 2 or 3 is for 2 x 8GB.

I highly doubt your setup will act different to mine as we are using the same RAM and both on MSI (i think the 3600 will act according to my 5600x, I never had 32GB when I had my 3600 ...)


----------



## Nd4spdvn

mongoled said:


> Its extremely hard to be able to run 1T without set up timings with 32GB and especially when using 4 x 8GB.
> 
> But using 56 AddrCmd should be doable, hopefully you can achieve that with few issues.
> 
> Also you would get better read throughput if you use tRDRDSCL/tWRWRSCL set to 4 or 5 rather than 2 or 3, 2 or 3 is for 2 x 8GB.


Agreed, have had the same experience with what you said above.


----------



## Veii

> RDWR=CL-CWL+5+WPRE
> WPRE=RDWR+CWL-CL-5












X = (15 - 14) *+* (5 + Y)
Y = (X + 14) *-* (14-(15-5)
X = 1 *+* 5 + Y
Y = X *+* 14 - 4

Y = X + 10
X = 6 + Y
X (tRDWR) using 9
9 = 6 + 3
Y = 3 ?
Y = 9 + 10
Y = 19 ? 

WPRE
19 = 9 + (-6)
23 - 15 = 8 - 5 = 3
3 *≠* 19 🤔

Am i stupid & can't do math , or this doesn't make any sense ?


----------



## anta777

???
True
X=15-14+5+Y=6+Y
Y=X+14-15-5=X-6
Y=6+Y-6=Y


----------



## SneakySloth

Veii said:


> X = (15 - 14) *+* (5 + Y)
> *Y = (X + 14) - (14-(15-5)*


It should be Y = X+14 - 15 - 5 => Y = X - 6 

I think...


----------



## mongoled

While you guys work out what what RPRE is (which we all will be grateful  )

I will post another possible config, Y-Cruncher is next on this set



13-13-15-13-30-44-220-1T


----------



## SneakySloth

mongoled said:


> Its extremely hard to be able to run 1T without set up timings with 32GB and especially when using 4 x 8GB.
> 
> But using 56 AddrCmd should be doable, hopefully you can achieve that with few issues.
> 
> Also you would get better read throughput if you use tRDRDSCL/tWRWRSCL set to 4 or 5 rather than 2 or 3, 2 or 3 is for 2 x 8GB.
> 
> I highly doubt your setup will act different to mine as we are using the same RAM and both on MSI (i think the 3600 will act according to my 5600x, I never had 32GB when I had my 3600 ...)


Just a quick question, is a higher AddrCmd (56 e.g.) 'bad' in any sense? If I remember correctly my motherboard always auto sets it to 0.


----------



## mongoled

SneakySloth said:


> Just a quick question, is a higher AddrCmd (56 e.g.) 'bad' in any sense? If I remember correctly my motherboard always auto sets it to 0.


No nothing like that



Its just adding more delay on the 1T cycle but not as much as a 2T cycle,

in my testing ive hardly noted any difference in performance compared to 1T and better read throughput than 2T and better latency as tPHYRDL should be 26 on all sticks when reverting to 1T.

I know that makes no sense at 2T is easier to do than 1T so why tPHYRDL increases to 28 I dont know, it seems a strange one...


----------



## Audioboxer

mongoled said:


> While you guys work out what what RPRE is (which we all will be grateful  )
> 
> I will post another possible config, Y-Cruncher is next on this set
> 
> 
> 
> 13-13-15-13-30-44-220-1T
> 
> View attachment 2528849


At first I thought that was flat 13 

I've tried really hard to stabilise flat 13, even up to 1.65v, but I can't stop the TM5 errors  

How did you finally figure out 1T pure? I remember you running with 56 for ages.



mongoled said:


> No nothing like that
> 
> 
> 
> Its just adding more delay on the 1T cycle but not as much as a 2T cycle,
> 
> in my testing ive hardly noted any difference in performance compared to 1T and better read throughput than 2T and better latency as tPHYRDL should be 26 on all sticks when reverting to 1T.
> 
> I know that makes no sense at 2T is easier to do than 1T so why tPHYRDL increases to 28 I dont know, it seems a strange one...


Makes about as much sense as having to go to tCL13 to get 26/26 rather than 28/26 at tCL14


----------



## mongoled

Audioboxer said:


> At first I thought that was flat 13
> 
> I've tried really hard to stabilise flat 13, even up to 1.65v, but I can't stop the TM5 errors
> 
> How did you finally figure out 1T pure? I remember you running with 56 for ages.


Look more carefully its only 2 x 8GB



Its down to the PCB, to be able to run the flat 13s,

on my dimms (8 layer PCB) so far I cannot run 13-13-14-13, Y-Cruncher crashes, TM5 passes, by upping tRCDRD to 15 Y-Cruncher is OK.

I believe your dimms are on a 10 layer PCB, which may give those dimms the edge in running a lower tRCDRD.

Once ive got a stable set with above settings I will revisit 13-13-14-13, but I cannot see anywhere to make improvements as I think vDIMM, vSOC, vDDP, ProcODT, ClkDrvStr and the Rtt's are all maxed out..



Audioboxer said:


> Makes about as much sense as having to go to tCL13 to get 26/26 rather than 28/26 at tCL14


Yup

😀 😀


----------



## mongoled

Anyone work out how to pause Y-Cruncher ?

Ive accidently done this a few times

Ok worked it out while writing this



Simply make a small selection in the Y-Cruncher window and when its meant to go to the next test it wont.

Simply pressing enter will allow it to continue, this does not stop the timer mind you


----------



## umea

Well I've been kinda AFK from messing with computer for a little bit but finally got around to installing the copper heatsinks, only to realize I'm an idiot and these are mostly beneficial to ATX boards + people who are watercooling/using LN2...


Spoiler: Pictures























I ended up with around a 4 degree increase, keep in mind this is with a 120mm fan running 100% on the dimms.
Without heatsinks:









With heatsinks:








I know the RTTs are different, but the 6/3/1 that was stable in the first pic errored o ut within minutes so I changed it back to what is normally also stable and safe (6/3/3). Either way, that wouldn't account for the 4 degree increase.

They look sexy at least I guess. I'll probably take them off and if anyone in NA would like to purchase them at a discount let me know. I paid 120euro+ shipping (have 2 sets), but I can work out a deal, just don't want to lose too much money and would hope that these go somewhere someone would appreciate them. These probably work fantastic for water cooling/LN2 but I don't have the space or money to invest in a full water cooling setup right now.

Also in other news, I decided that while my computer was taken apart, I might as well test to see if it's my sticks or my CPU that can't handle tRCDRD 14 at 3800. Seems like it's my CPU. Tried both sticks in both dimms one by one and neither could run tRCDRD 14 after fiddling for a while, so while there may be a possibility that I'm not getting the right setting, it seems a lot more likely that my CPU can't hit it. Of course it could be that both of my sticks are trash, who knows.


----------



## Audioboxer

mongoled said:


> Look more carefully its only 2 x 8GB
> 
> 
> 
> Its down to the PCB, to be able to run the flat 13s,
> 
> on my dimms (8 layer PCB) so far I cannot run 13-13-14-13, Y-Cruncher crashes, TM5 passes, by upping tRCDRD to 15 Y-Cruncher is OK.
> 
> I believe your dimms are on a 10 layer PCB, which may give those dimms the edge in running a lower tRCDRD.
> 
> Once ive got a stable set with above settings I will revisit 13-13-14-13, but I cannot see anywhere to make improvements as I think vDIMM, vSOC, vDDP, ProcODT, ClkDrvStr and the Rtt's are all maxed out..
> 
> 
> Yup
> 
> 😀 😀


Ah yeah, have you got a 2x16GB set as well? You were definitely running 56 weeks back 

Have you seen anyone manage tRCDRD 13 stable at 3800?


----------



## Luggage

umea said:


> Well I've been kinda AFK from messing with computer for a little bit but finally got around to installing the copper heatsinks, only to realize I'm an idiot and these are mostly beneficial to ATX boards + people who are watercooling/using LN2...
> 
> 
> Spoiler: Pictures
> 
> 
> 
> 
> View attachment 2528855
> 
> View attachment 2528856
> 
> 
> 
> 
> I ended up with around a 4 degree increase, keep in mind this is with a 120mm fan running 100% on the dimms.
> Without heatsinks:
> View attachment 2528857
> 
> 
> With heatsinks:
> View attachment 2528858
> 
> I know the RTTs are different, but the 6/3/1 that was stable in the first pic errored o ut within minutes so I changed it back to what is normally also stable and safe (6/3/3). Either way, that wouldn't account for the 4 degree increase.
> 
> They look sexy at least I guess. I'll probably take them off and if anyone in NA would like to purchase them at a discount let me know. I paid 120euro+ shipping (have 2 sets), but I can work out a deal, just don't want to lose too much money and would hope that these go somewhere someone would appreciate them. These probably work fantastic for water cooling/LN2 but I don't have the space or money to invest in a full water cooling setup right now.
> 
> Also in other news, I decided that while my computer was taken apart, I might as well test to see if it's my sticks or my CPU that can't handle tRCDRD 14 at 3800. Seems like it's my CPU. Tried both sticks in both dimms one by one and neither could run tRCDRD 14 after fiddling for a while, so while there may be a possibility that I'm not getting the right setting, it seems a lot more likely that my CPU can't hit it. Of course it could be that both of my sticks are trash, who knows.


Are you sure they work with paste? All I’ve seen for sale states 0.5mm pads for dual sided or 1.0 (backside) and 0.5 (front) for single sided.


----------



## umea

Luggage said:


> Are you sure they work with paste? All I’ve seen for sale states 0.5mm pads for dual sided or 1.0 (backside) and 0.5 (front) for single sided.


I'm not sure, I guess I could try using pads themselves but I was following this video:


----------



## PJVol

TimeDrapery said:


> Pretty meh so far... I'll keep plugging away


Just curious, if all those apps shown on the taskbar were lunched during AIDA cachemem bench?


----------



## TimeDrapery

PJVol said:


> Just curious, if all those apps shown on the taskbar were lunched during AIDA cachemem bench?


@PJVol

Nah, SOP for now is:
• Boot to Windows
• Sign in
• Run BoostTesterMannix to let the OS "get with it" as far as power management is concerned
• Close BoostTesterMannix
• Open AIDA64 and the AIDA64 Cache & Memory Benchmark
• Run it once (Alt + B)
• Run it again (Alt + B)
• Open and run any other benches I want depicted in the screenshot (unless I want something from HWiNFO64 included in the shot... In that case I'll open it and then open/run any benches)
• Open ZenTimings
• Capture screenshot

Here's where I think I'm heading for now...


----------



## SneakySloth

mongoled said:


> No nothing like that
> 
> 
> 
> Its just adding more delay on the 1T cycle but not as much as a 2T cycle,
> 
> in my testing ive hardly noted any difference in performance compared to 1T and better read throughput than 2T and better latency as tPHYRDL should be 26 on all sticks when reverting to 1T.
> 
> I know that makes no sense at 2T is easier to do than 1T so why tPHYRDL increases to 28 I dont know, it seems a strange one...


AddrCmdSetup at 56 seems to be okay with GDM disabled IT. I'm really surprised because IT without GDM has been a pain to even remotely stabalize. That alongside SCLs at 4 seems to have boosted my read and copy seems quite a bit. Plus I went from 103.5 in DRAM benchmark to 100.6.

Thanks again for your help.










Going to let this run overnight now to confirm stability.


----------



## TimeDrapery

Ah, always good to see!!!


----------



## mongoled

TimeDrapery said:


> Ah, always good to see!!!
> 
> View attachment 2528947


What are we looking for ?

😀😀


----------



## mongoled

Another stable set, now to hit on 13-13-14-13


----------



## TimeDrapery

mongoled said:


> What are we looking for ?
> 
> 😀😀


@mongoled










One of those red number things... 😭😭😂😭😭


----------



## mongoled

TimeDrapery said:


> @mongoled
> 
> View attachment 2528957
> 
> 
> One of those red number things... 😭😭😂😭😭


😂 😂

Let me get my voodoo doll out so next time I can work that out



Seriously you threw a stray ball as I was looking for things to do with 24/7 memory stability



Im guessing thats what the cores hit on light loads ??


----------



## TimeDrapery

mongoled said:


> 😂 😂
> 
> Let me get my voodoo doll out so next time I can work that out
> 
> 
> 
> Seriously you threw a stray ball as I was looking for things to do with 24/7 memory stability
> 
> 
> 
> Im guessing thats what the cores hit on light loads ??


@mongoled










😂😂😂😂😂, dude... Forreal though, I really appreciate @Veii 's explanation because the "equations / rules" I was seeing was really throwing me for a loop

I'm back to the 1usmus_v3 config as the short time I spent with the other two newer ones running intentionally "misconfigured" timings they didn't report the errors that 1usmus_v3 did, which indicated where I should look to resolve the error pattern(s)

Whether it does what @anta777 says it does or not is irrelevant to me as I'm not interested in whether that config confirms to the developer's intent, I care if it will help me to overclock my system memory

@anta777 , again, thanks for lending your expertise, experience and knowledge to the community via this thread and through making your config files available to the general public for use with TM5

@mongoled I want you to use the voodoo doll to tell Karhu to error earlier on in the tests 😂😂😂😂😂

Yup, that's Auto OC (boost override) at +200MHz, "Turbo" loadlines, and CO... Well, it's on but I dunno how close to "optimized" any curves are as each time I get to what I consider "stable" I think of something else to try and start all over 😂😂😂😂😂

I think it's telling that with both this 5800X and the 5600X I've yet to even feel the slightest inclination to explore all-core overclocking as of yet... Good job, AMD










Oh, it likes that too... We'll see what Karhu has to say about it now... The last Karhu run errored out at _*02:23:30*_ and *11775%* so we'll have to see if these changes take us further


----------



## Audioboxer

MS "we've fixed your L3 cache issues in the release preview"









Releasing Windows 11 Build 22000.282 to Beta and Release Preview Channels


Hello Windows Insiders, today we’re releasing Windows 11 Build 22000.282 to Windows Insiders in the Beta and Release Preview Channels. This update includes the following improvements: We fixed an L3 caching issue that might affect perfo




blogs.windows.com





Also MS, enjoy these ****ty results










Just about everything is worse than Windows 10, not to mention L3 latency is *still* higher, 10.2 is about standard on Windows 10. People have said read/write/copy is broken until AMD release their part of the fix, but I wouldn't be surprised if performance is still crap after the new chipset drivers.

Tldr; stay away from Windows 11 if you care about memory performance and continue to wait to see if its properly fixed any time soon.


----------



## Nizzen

Audioboxer said:


> MS "we've fixed your L3 cache issues in the release preview"
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Releasing Windows 11 Build 22000.282 to Beta and Release Preview Channels
> 
> 
> Hello Windows Insiders, today we’re releasing Windows 11 Build 22000.282 to Windows Insiders in the Beta and Release Preview Channels. This update includes the following improvements: We fixed an L3 caching issue that might affect perfo
> 
> 
> 
> 
> blogs.windows.com
> 
> 
> 
> 
> 
> Also MS, enjoy these ****ty results
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Just about everything is worse than Windows 10, not to mention L3 latency is *still* higher, 10.2 is about standard on Windows 10. People have said read/write/copy is broken until AMD release their part of the fix, but I wouldn't be surprised if performance is still crap after the new chipset drivers.
> 
> Tldr; stay away from Windows 11 if you care about memory performance and continue to wait to see if its properly fixed any time soon.


This is mine with latest update in win 11 DEV.
If it's good or bad, I don't know.








Edit: Looks like L3 is way higher than you...


----------



## Audioboxer

Nizzen said:


> This is mine with latest update in win 11 DEV.
> If it's good or bad, I don't know.
> View attachment 2528983


Read/Write/Copy are a bit better, but write is still low. L3 latency is still rubbish, for those memory timings should easily be around 10.2. The dev builds have more changes in them than the Release Preview/Beta. Only really paying attention to L3 at the moment, the rest will be dependent on memory timings, background apps running, how many times you've ran the test to get a better average and all the usual caveats of AIDA64. I normally run it in safe mode to check the main memory latency because I run a fairly heavy Windows installation in terms of background apps.

Through all my testing at 3800, around 54ns seems to be the best I can achieve. 53.7 my lowest on record. Which is pretty normal for a 5950x at 3800 in AIDA64.


----------



## Nizzen

Audioboxer said:


> Read/Write/Copy are a bit better, but write is still low. L3 latency is still rubbish, for those memory timings should easily be around 10.2. The dev builds have more changes in them than the Release Preview/Beta. Only really paying attention to L3 at the moment, the rest will be dependent on memory timings, background apps running, how many times you've ran the test to get a better average and all the usual caveats of AIDA64. I normally run it in safe mode to check memory latency because I run a fairly heavy Windows installation in terms of background apps.


I just ran with a lot of background programs and with chrome open. Your L3 speed looks very low?


----------



## Audioboxer

Nizzen said:


> I just ran with a lot of background programs and with chrome open. Your L3 speed looks very low?


Nvidia control panel/GeForce experience and ICUE are latency killers in my testing. ICUE is one of the worst pieces of software I think I've ever seen developed, but it's how I need to control my loop/fans.










How many processes you have running is a good indicator of whether to expect some higher latency numbers (main memory latency). Nearer 200 can be normal for me, discord, steam and a few other things aren't open for that screenshot.

Yeah, L3 read/write/copy still looks busted on the release preview. Insider channel has had the "fix" for a lot longer and no doubt some other experimental changes.

I know what my current memory timings bring in Windows 10 so if they can't be emulated in Windows 11 as of yet, it's Windows 11 that is still broke. I'm not switching onto the insider channel ever again with MS, most I will try is release preview. MS has really gone down hill in recent years with software development.


----------



## Veii

Audioboxer said:


> How many processes you have running is a good indicator of whether to expect some higher latency numbers (main memory latency). Nearer 200 can be normal for me, discord, steam and a few other things aren't open for that screenshot.


70 for me on idle
72 peak with aida & screenshot tool or shareX

68-69 is common  (sub 80 is fine on Win 11)
Sub 120 is fine for daily usage
EDIT:
124 right now with Discord,ShareX, Wifi and 43 operaGX tabs
4.6GB used (chromium) 1.3GB usage on idle







EDIT2:
i didn't know P0 on a 5950X is 3.4Ghz not 3.7. Quite a difference to the 5900X


----------



## Mach3.2

Audioboxer said:


> MS "we've fixed your L3 cache issues in the release preview"
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Releasing Windows 11 Build 22000.282 to Beta and Release Preview Channels
> 
> 
> Hello Windows Insiders, today we’re releasing Windows 11 Build 22000.282 to Windows Insiders in the Beta and Release Preview Channels. This update includes the following improvements: We fixed an L3 caching issue that might affect perfo
> 
> 
> 
> 
> blogs.windows.com
> 
> 
> 
> 
> 
> Also MS, enjoy these ****ty results
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Just about everything is worse than Windows 10, not to mention L3 latency is *still* higher, 10.2 is about standard on Windows 10. People have said read/write/copy is broken until AMD release their part of the fix, but I wouldn't be surprised if performance is still crap after the new chipset drivers.
> 
> Tldr; stay away from Windows 11 if you care about memory performance and continue to wait to see if its properly fixed any time soon.


Honestly there's no rush, Windows 10 is still supported till 2025.

Give them a year or so to iron out the folds.


----------



## kim nk

Audioboxer said:


> Ah yeah, have you got a 2x16GB set as well? You were definitely running 56 weeks back
> 
> Have you seen anyone manage tRCDRD 13 stable at 3800?


(지스킬4800CL17 후기) 4933 CL15 및 3800 CL13 %20댓글

3800 cl13 스트레이트 리얼1T 1.58v 50.7ns 답장&수정=


Two link trcrd13 tests were performed. The memory used passed the tm5 test by trcdrd 13 in two RAMs: oloy cl14 4000 xmp 14-15-15-35 1.55 and royal cl17 4800 xmp cl17-19-19-39.

5700G CPU has symptoms of TFAW value tightening. They returned to 5800X and responded positively to TRCDRD 13. We need a probability of pulling from two memories, but we bought two things and obtained TRCDRD 13. They pass 4,000 clocks on the 5800X CPU by catching a WHEA error at the timing of CL14141414 TRFC 240.


----------



## TimeDrapery

kim nk said:


> (지스킬4800CL17 후기) 4933 CL15 및 3800 CL13 %20댓글
> 
> 3800 cl13 스트레이트 리얼1T 1.58v 50.7ns 답장&수정=
> 
> 
> Two link trcrd13 tests were performed. The memory used passed the tm5 test by trcdrd 13 in two RAMs: oloy cl14 4000 xmp 14-15-15-35 1.55 and royal cl17 4800 xmp cl17-19-19-39.


@kim nk

*Hells yes, dude!!! That's really, really, REALLY good ****!!!*

While reading through the posts at the URL you linked us to in your post I noticed this passage,

"*the other day, after the trdwr study, i made one hypothesis for trdwr, tcwl, tras*,

*it's been very helpful to ramta this over*."

Would you be able and willing to explain this a little further? Please? I'm always trying to learn a new trick or two 😁😁😁😁😁

Also, please share more information with us regarding the process(es) you undertook to debug your memory OC related voltages (*CPU VDDP*, *CLDO VDDP*, *MEM VDDG*, *VDDG CCD*/*IOD*, *VDIMM*, and *VSOC*) in order to attain stability with the configuration depicted in the ZenTimings screenshots found at the URLs you linked us to in your post

Thank you for sharing this accomplishment with us! Once again... *GREAT JOB!!!*


----------



## sealxohd

I also have 3800 tRCD 13 stable at 1.52 V. 3794 to be precise. Need BCLK for 3800/1900 since I have a hole at 1900 FCLK. Does anyone know good RTTs for 1T GDM off with B1 PCB sticks? I could probably run something like 13-8-13-11-21 32 with ~1.65 V. My sticks can take voltage well but im just so bad with RTTs and Setup timings.

I also have massiv performance drops at 1933+ FCLK (WHEAs as well). I cant even bench AIDA since I get 8+ ns penatlty.


----------



## TimeDrapery

sealxohd said:


> View attachment 2528990
> 
> 
> I also have 3800 tRCD 13 stable at 1.52 V. 3794 to be precise. Need BCLK for 3800/1900 since I have a hole at 1900 FCLK. Does anyone know good RTTs for 1T GDM off with B1 PCB sticks? I could probably run something like 13-8-13-11-21 32 with ~1.65 V. My sticks can take voltage well but im just so bad with RTTs and Setup timings.
> 
> I also have massiv performance drops at 1933+ FCLK (WHEAs as well). I cant even bench AIDA since I get 8+ ns penatlty.


@sealxohd

Righteous! Y'all are just coming out of the woodwork, huh?!? That's some nice Karhu...ing you're doing there as well! Great coverage...

Regarding *RTTs*, why not test "the usual suspects" and see what floats to the top? For dual rank kits I commonly see recommendations of:

*RTT_PARK*: "*RZQ/6,* *RZQ/7*, or *Disabled*"
*RTT_WR*: "*RZQ/3* or *RZQ/2*"
*RTT_NOM*: "*RZQ/1* (although this has always seemed a bit much to me eyes) *RZQ/3*, *RZQ/5*, *RZQ/6*, or *RZQ/7*"

*Setup timings* could very well help you with stabilizing that "*1T*"* CR* / *GDM* "*Disabled*" timing set you're working... You could test with @Veii 's "*3-3-15*" with *drive strengths* set to "*40.0 Ω* / *20.0 Ω* / *20.0 Ω* / *20.0 Ω*" and see where you're at

If that setup timing configuration isn't helping then increasing/setting all three values to "*56*" may better assist you (you could also only set *AddrCmdSetup* to "*56*" and see how that pans out)

Although you may have to do some testing to determine what setup timing values perform best and are the most stable I've commonly seen that most people utilizing setup timings when overclocking their memory to set values within the small range of "*52* - *56*" and not too far outside of that range, if at all...

Keep up the great efforts you're putting forth and *thanks a ton for contributing to the community by posting in this thread*... Keep us updated with the results of your latest testing iterations!!!


----------



## kim nk

TimeDrapery said:


> @kim nk
> 
> *Hells yes, dude!!! That's really, really, REALLY good ****!!!*
> 
> While reading through the posts at the URL you linked us to in your post I noticed this passage,
> 
> "*the other day, after the trdwr study, i made one hypothesis for trdwr, tcwl, tras*,
> 
> *it's been very helpful to ramta this over*."
> 
> Would you be able and willing to explain this a little further? Please? I'm always trying to learn a new trick or two 😁😁😁😁😁
> 
> Also, please share more information with us regarding the process(es) you undertook to debug your memory OC related voltages (*CPU VDDP*, *CLDO VDDP*, *MEM VDDG*, *VDDG CCD*/*IOD*, *VDIMM*, and *VSOC*) in order to attain stability with the configuration depicted in the ZenTimings screenshots found at the URLs you linked us to in your post
> 
> Thank you for sharing this accomplishment with us! Once again... *GREAT JOB!!!*


From what I've heard of this experience, I've acquired 3800 trcrd13 possible memory by purchasing only several memories of oloy cl14 4000 cl14-15-35 1.55v and royal cl17 4800 cl17-19-19-39 1.6v. This selected yield memory was able to provide a very good required voltage and low timing for it, so that 14-14-14 straight timing was possible at about 1.55v even at 4000 clocks.









(뽑기-2편) 5600X(2133주차) 4.7G(CB_1.275V) 4000 14-14-14-14-28/리얼1T


뽑기 두번째 CPU인 5600X 2133SUS주차입니다지난 1편의 2137SUS에 대한 내용은 아래 링크를 …




quasarzone.com













5600X 4025 13-15-8-12-21/리얼1T (BCLK=100.6125)


이번에 (뽑기)한 2137SUS주차의 5600X로 4000 CL13 램오버를 수행합니다이 CPU의 멤컨 한계…




quasarzone.com













(뽑기-3편 재연) 5800X(2132주차) 4000 CL14 (feat 다크히어로)


최신주차 뽑기 세번째 CPU인 5800X 2132SUS주차로 보드를 다크히어로로 바꿔서 재연테스트를 해봅니다…




quasarzone.com


----------



## sealxohd

TimeDrapery said:


> @sealxohd
> 
> Righteous! Y'all are just coming out of the woodwork, huh?!?


Kind of  Im still pretty new to OC

Thanks for the info! I will try fiddling with everything a bit and give an update at some point. My nooby 1T attemps resulted mainly in bsod


----------



## Audioboxer

kim nk said:


> (지스킬4800CL17 후기) 4933 CL15 및 3800 CL13 %20댓글
> 
> 3800 cl13 스트레이트 리얼1T 1.58v 50.7ns 답장&수정=
> 
> 
> Two link trcrd13 tests were performed. The memory used passed the tm5 test by trcdrd 13 in two RAMs: oloy cl14 4000 xmp 14-15-15-35 1.55 and royal cl17 4800 xmp cl17-19-19-39.
> 
> 5700G CPU has symptoms of TFAW value tightening. They returned to 5800X and responded positively to TRCDRD 13. We need a probability of pulling from two memories, but we bought two things and obtained TRCDRD 13. They pass 4,000 clocks on the 5800X CPU by catching a WHEA error at the timing of CL14141414 TRFC 240.


That's impressive! I'd like to see it on DR though 

With inspiration from those screenshots I might give it a go on DR with some different timings (not as tight for some secondary).



Veii said:


> 70 for me on idle
> 72 peak with aida & screenshot tool or shareX
> 
> 68-69 is common  (sub 80 is fine on Win 11)
> Sub 120 is fine for daily usage
> EDIT:
> 124 right now with Discord,ShareX, Wifi and 43 operaGX tabs
> 4.6GB used (chromium) 1.3GB usage on idle
> View attachment 2528985
> 
> EDIT2:
> i didn't know P0 on a 5950X is 3.4Ghz not 3.7. Quite a difference to the 5900X


I seriously need to figure out what background stuff I can turn off. I've tried disabling some Windows 11 services, but I still have like 96 Windows processes.










Games and what not still run great, but most people in this topic seem to have much leaner Windows installations and it's annoying me LOL


----------



## umea

Idling I sit at 22 background processes (5 of which are from my drawing tablet drivers) and 36 windows processes.


----------



## Audioboxer

umea said:


> Idling I sit at 22 background processes (5 of which are from my drawing tablet drivers) and 36 windows processes.


Oooft, I definitely need some help with my Windows processes 










kim got me wanting to have a poke at tRCDRD 13 again and I guess getting to around a minute is progress! Used to the explosion of 6's within like 30 seconds lol. 1.57v was entered for VDIMM, but I sometimes forget MSI boards add an extra 0.01v.


----------



## kim nk

Audioboxer said:


> Oooft, I definitely need some help with my Windows processes
> 
> View attachment 2529029
> 
> 
> kim got me wanting to have a poke at tRCDRD 13 again and I guess getting to around a minute is progress! Used to the explosion of 6's within like 30 seconds lol. 1.57v was entered for VDIMM, but I sometimes forget MSI boards add an extra 0.01v.


Among the cl14 4000 memories, if you pull well, you get trcdrd13 and some are impossible. Some have a good memory voltage yield, some have a good trcrd yield, some have a good voltage, some have a good trcrd yield, and some have a good trcrd yield. Only lucky ㅠㅠ


----------



## Audioboxer

kim nk said:


> Among the cl14 4000 memories, if you pull well, you get trcdrd13 and some are impossible. Some have a good memory voltage yield, some have a good trcrd yield, some have a good voltage, some have a good trcrd yield, and some have a good trcrd yield. Only lucky ㅠㅠ


Voltage yield seems to be good, flat 14 at 1.47v from a few weeks ago










To drop to tCL13 needs around 1.55v










But sadly for me it looks like tRCDRD 13 might be impossible to stabilise!


----------



## Audioboxer

Can anyone with a low Windows processes list do this for me in powershell?

Get-Service | Select StartType, Status, Name, DisplayName | Where-Object {$_.Status -eq 'Running'} | Format-Table -AutoSize | Out-File -filepath "$Env:userprofile\Desktop\Running_Services.txt"

It'll output a text file on your desktop with running Windows services. Want to compare it to mine



> StartType Status Name DisplayName
> --------- ------ ---- -----------
> Automatic Running Adguard Service Adguard Service
> Manual Running Appinfo Application Information
> Manual Running AppXSvc AppX Deployment Service (AppXSVC)
> Automatic Running AudioEndpointBuilder Windows Audio Endpoint Builder
> Automatic Running Audiosrv Windows Audio
> Automatic Running BFE Base Filtering Engine
> Manual Running BluetoothUserService_4942c Bluetooth User Support Service_4942c
> Automatic Running BrokerInfrastructure Background Tasks Infrastructure Service
> Manual Running BTAGService Bluetooth Audio Gateway Service
> Manual Running BthAvctpSvc AVCTP service
> Manual Running bthserv Bluetooth Support Service
> Manual Running camsvc Capability Access Manager Service
> Automatic Running cbdhsvc_4942c Clipboard User Service_4942c
> Automatic Running CDPSvc Connected Devices Platform Service
> Automatic Running CDPUserSvc_4942c Connected Devices Platform User Service_4942c
> Automatic Running CoreMessagingRegistrar CoreMessaging
> Automatic Running CorsairGamingAudioConfig Corsair Gaming Audio Configuration Service
> Automatic Running CorsairLLAService Corsair LLA Service
> Automatic Running CorsairMsiPluginService Corsair MSI Plugin Service
> Automatic Running CorsairService Corsair Service
> Automatic Running CryptSvc Cryptographic Services
> Automatic Running DcomLaunch DCOM Server Process Launcher
> Manual Running DeviceAssociationService Device Association Service
> Automatic Running Dhcp DHCP Client
> Automatic Running DiagTrack Connected User Experiences and Telemetry
> Automatic Running DispBrokerDesktopSvc Display Policy Service
> Automatic Running Dnscache DNS Client
> Automatic Running DoSvc Delivery Optimization
> Automatic Running DPS Diagnostic Policy Service
> Manual Running DsSvc Data Sharing Service
> Automatic Running DusmSvc Data Usage
> Manual Running EFS Encrypting File System (EFS)
> Automatic Running EventLog Windows Event Log
> Automatic Running EventSystem COM+ Event System
> Automatic Running FontCache Windows Font Cache Service
> Manual Running hidserv Human Interface Device Service
> Automatic Running iphlpsvc IP Helper
> Manual Running KeyIso CNG Key Isolation
> Automatic Running LanmanServer Server
> Automatic Running LanmanWorkstation Workstation
> Automatic Running LGHUBUpdaterService LGHUB Updater Service
> Manual Running lmhosts TCP/IP NetBIOS Helper
> Automatic Running LSM Local Session Manager
> Automatic Running mpssvc Windows Defender Firewall
> Manual Running NcbService Network Connection Broker
> Manual Running netprofm Network List Service
> Manual Running NgcCtnrSvc Microsoft Passport Container
> Manual Running NgcSvc Microsoft Passport
> Automatic Running NlaSvc Network Location Awareness
> Manual Running NPSMSvc_4942c NPSMSvc_4942c
> Automatic Running nsi Network Store Interface Service
> Automatic Running NVDisplay.ContainerLocalSystem NVIDIA Display Container LS
> Automatic Running OneSyncSvc_4942c Sync Host_4942c
> Automatic Running PcaSvc Program Compatibility Assistant Service
> Manual Running PimIndexMaintenanceSvc_4942c Contact Data_4942c
> Manual Running PlugPlay Plug and Play
> Automatic Running Power Power
> Automatic Running ProfSvc User Profile Service
> Manual Running RmSvc Radio Management Service
> Automatic Running RpcEptMapper RPC Endpoint Mapper
> Automatic Running RpcSs Remote Procedure Call (RPC)
> Automatic Running SamSs Security Accounts Manager
> Automatic Running Schedule Task Scheduler
> Manual Running SecurityHealthService Windows Security Service
> Automatic Running SENS System Event Notification Service
> Automatic Running SgrmBroker System Guard Runtime Monitor Broker
> Automatic Running ShellHWDetection Shell Hardware Detection
> Automatic Running Spooler Print Spooler
> Automatic Running StateRepository State Repository Service
> Manual Running Steam Client Service Steam Client Service
> Manual Running StorSvc Storage Service
> Automatic Running SysMain SysMain
> Automatic Running SystemEventsBroker System Events Broker
> Manual Running TabletInputService Touch Keyboard and Handwriting Panel Service
> Automatic Running Themes Themes
> Manual Running TimeBrokerSvc Time Broker
> Manual Running TokenBroker Web Account Manager
> Automatic Running TrkWks Distributed Link Tracking Client
> Manual Running UdkUserSvc_4942c Udk User Service_4942c
> Manual Running UnistoreSvc_4942c User Data Storage_4942c
> Manual Running UserDataSvc_4942c User Data Access_4942c
> Automatic Running UserManager User Manager
> Automatic Running UsoSvc Update Orchestrator Service
> Manual Running VaultSvc Credential Manager
> Automatic Running Wcmsvc Windows Connection Manager
> Manual Running WdiSystemHost Diagnostic System Host
> Manual Running WdNisSvc Microsoft Defender Antivirus Network Inspection Service
> Automatic Running WinDefend Microsoft Defender Antivirus Service
> Manual Running WinHttpAutoProxySvc WinHTTP Web Proxy Auto-Discovery Service
> Automatic Running Winmgmt Windows Management Instrumentation
> Automatic Running wisvc Windows Insider Service
> Automatic Running WlanSvc WLAN AutoConfig
> Automatic Running WpnService Windows Push Notifications System Service
> Automatic Running WpnUserService_4942c Windows Push Notifications User Service_4942c
> Automatic Running wscsvc Security Center
> Automatic Running WSearch Windows Search
> Manual Running XboxGipSvc Xbox Accessory Management Service


Right now I have 93 Windows processes in task manager, that's before adding on the 80 background processes.










Crap like this I unfortunately cannot get away from, my PC _is_ for using, it's not just a test bench. So, some apps are just going to have to be running, end of, lol. But I seriously need to cut down somewhere.










This for example definitely needs to go, what a mess. Will have to Google how to totally wipe out Windows Widgets.

*edit* - OK, that was easy, winget uninstall "windows web experience pack"


----------



## umea

StartType Status Name DisplayName 
--------- ------ ---- ----------- 
Manual Running Appinfo Application Information 
Automatic Running AudioEndpointBuilder Windows Audio Endpoint Builder 
Automatic Running Audiosrv Windows Audio 
Automatic Running BrokerInfrastructure Background Tasks Infrastructure Service
Automatic Running camsvc Capability Access Manager Service 
Automatic Running CoreMessagingRegistrar CoreMessaging 
Automatic Running CryptSvc Cryptographic Services 
Automatic Running DcomLaunch DCOM Server Process Launcher 
Automatic Running DeviceInstall Device Install Service 
Automatic Running Dhcp DHCP Client 
Automatic Running Dnscache DNS Client 
Automatic Running gpsvc Group Policy Client 
Automatic Running LanmanWorkstation Workstation 
Automatic Running lmhosts TCP/IP NetBIOS Helper 
Automatic Running LSM Local Session Manager 
Automatic Running nsi Network Store Interface Service 
Automatic Running NVDisplay.ContainerLocalSystem NVIDIA Display Container LS 
Automatic Running Origin Web Helper Service Origin Web Helper Service 
Automatic Running Power Power 
Automatic Running ProfSvc User Profile Service 
Automatic Running RpcEptMapper RPC Endpoint Mapper 
Automatic Running RpcSs Remote Procedure Call (RPC) 
Automatic Running Schedule Task Scheduler 
Manual Running StateRepository State Repository Service 
Automatic Running STR Set Timer Resolution 
Automatic Running SystemEventsBroker System Events Broker 
Manual Running TimeBrokerSvc Time Broker 
Automatic Running UserManager User Manager 
Automatic Running Wcmsvc Windows Connection Manager 
Automatic Running Winmgmt Windows Management Instrumentation 
Automatic Running WTabletServicePro Wacom Professional Service


----------



## TimeDrapery

Audioboxer said:


> Can anyone with a low Windows processes list do this for me in powershell?
> 
> Get-Service | Select StartType, Status, Name, DisplayName | Where-Object {$_.Status -eq 'Running'} | Format-Table -AutoSize | Out-File -filepath "$Env:userprofile\Desktop\Running_Services.txt"
> 
> It'll output a text file on your desktop with running Windows services. Want to compare it to mine
> 
> 
> 
> Right now I have 93 Windows processes in task manager, that's before adding on the 80 background processes.
> 
> View attachment 2529034
> 
> 
> Crap like this I unfortunately cannot get away from, my PC _is_ for using, it's not just a test bench. So, some apps are just going to have to be running, end of, lol. But I seriously need to cut down somewhere.
> 
> View attachment 2529036
> 
> 
> This for example definitely needs to go, what a mess. Will have to Google how to totally wipe out Windows Widgets.
> 
> *edit* - OK, that was easy, winget uninstall "windows web experience pack"


@Audioboxer 

Isn't there some manner through which you can load your blinky pretties as well as your desired powering settings (fan / pump speeds) into "device" (pump, CPU cooler, fans, etc.) memory via iCUE so you don't have to have the software suite installed whatsoever?

I swear I've done this with each and every CORSAIR AIO I've ever owned and run and I'll be sorely disappointed if you simply *must* have iCUE installed alongside a custom loop... That's simply silly










There we are! That's much gooder, Karhu RAM Test...

I suppose I'll run Y-Cruncher at some point today / tonight in order to validate stability with configured voltages and then... call it a baseline...!


----------



## Audioboxer

TimeDrapery said:


> @Audioboxer
> 
> Isn't there some manner through which you can load your blinky pretties as well as your desired powering settings (fan / pump speeds) into "device" (pump, CPU cooler, fans, etc.) memory via iCUE so you don't have to have the software suite installed whatsoever?
> 
> I swear I've done this with each and every CORSAIR AIO I've ever owned and run and I'll be sorely disappointed if you simply *must* have iCUE installed alongside a custom loop... That's simply silly
> 
> View attachment 2529044
> 
> 
> There we are! That's much gooder, Karhu RAM Test...
> 
> I suppose I'll run Y-Cruncher at some point today / tonight in order to validate stability with configured voltages and then... call it a baseline...!


There might be, I'll have a look. I use a commander pro as the brains to my whole loop but I think once it has its settings stored it can just be left. I've got more fat to trim first before even worrying about Corsair's bloat lol. Trying to cut down on the Windows bloat first.


----------



## bfollett

Trying to get a Zen+ (2600x) memory stable above 3466Mhz. I have a 2X8Gb hynix cjr 3600 cl16 memory kit runing on a 450 chipset with latest compatible bios. Using an older version of Dram Calc (1.70). I found I could run at 3466 using the timings it suggests for 3400, which is great, but any attempt at 3533 or 3600 quickly generate errors in Windows no matter how loose I set the timings or increase the SOC voltage at these higher frequencies. I've read that I just may be stuck at 3466 but I also read that going above 3466 with ZEN+ often involves a lot of tweaking to voltages, termination block and cad bus settings. I lowering procODT to 48 which isn't even suggested by DRAM calc and it seems to help a bit with stability but TestMem5 still generate errors. I'm just blindly trying some of the values suggested by DRam Calc in different combinations with no success. Any help would be appreciated. Below is what I have working. The 2 columns displayed in DRAM Calc show the suggested settings for 3400 and my settings for 3466. As you can see I was able to match and even exceed a couple values.


----------



## Luggage

Audioboxer said:


> There might be, I'll have a look. I use a commander pro as the brains to my whole loop but I think once it has its settings stored it can just be left. I've got more fat to trim first before even worrying about Corsair's bloat lol. Trying to cut down on the Windows bloat first.


Trimming of bloat is good but I’m not sure you have the right priority here.
(Well if you still have widgets running YMMW)


----------



## TimeDrapery

Audioboxer said:


> There might be, I'll have a look. I use a commander pro as the brains to my whole loop but I think once it has its settings stored it can just be left. I've got more fat to trim first before even worrying about Corsair's bloat lol. Trying to cut down on the Windows bloat first.


@Audioboxer 

I gotcha but I'll let you know right meow, in my experience, iCUE is the ****ing devil and should burn in hellfire forevermore... Compared to Windows bloat it's nightmarish

Regarding Windows bloat... Download the latest Sophia-Script-for-Windows release (as well as the "GUI wrapper") and open the script file in a text editor so you can scroll on through and familiarize yourself with its contents... It doesn't do anything all that insane when run and, when you run the wrapper, you simply elect for our against the script to modify your installation as the script progresses using pop-up GUI elements

It seems hardcore but these dev(s) have done an absolutely _excellent_ job in making it quite the opposite for the majority of users interested in "trimming" their Windows installation(s)... 

Seriously though, figure out how to load you're configs for your loop to your controller / devices and ****ing nuke iCUE from wayyyyy out in space


----------



## Audioboxer

Luggage said:


> Trimming of bloat is good but I’m not sure you have the right priority here.
> (Well if you still have widgets running YMMW)


Not sure what you mean about priorities? I'm finished with my memory profiles for now, just having a look at a fresh Windows 11 installation and wanting to cut down on the crap?


----------



## TimeDrapery

Audioboxer said:


> Not sure what you mean about priorities? I'm finished with my memory profiles for now, just having a look at a fresh Windows 11 installation and wanting to cut down on the crap?


@Audioboxer 

If he's tracking along the same lines as I am... He also thinks iCUE is a higher priority capture / kill target than anything bundled with Windows


----------



## Audioboxer

TimeDrapery said:


> @Audioboxer
> 
> If he's tracking along the same lines as I am... He also thinks iCUE is a higher priority capture / kill target than anything bundled with Windows


Ah right, okay, I get that now. Yeah, I'm going to look at the user apps and what is running as well, just starting with Windows.

Having a look at Sophia script inside the Wrapped 2.5 just now.


----------



## Luggage

TimeDrapery said:


> @Audioboxer
> 
> If he's tracking along the same lines as I am... He also thinks iCUE is a higher priority capture / kill target than anything bundled with Windows


^^^^ THIS!
Well that is - I assume you are not running DragonCenter? Because in that case I’d recommend a fresh windows install.


----------



## Audioboxer

Luggage said:


> ^^^^ THIS!
> Well that is - I assume you are not running DragonCenter? Because in that case I’d recommend a fresh windows install.


Nah I avoid all motherboard crap like that. Only reason I have iCUE is for the loop.


----------



## TimeDrapery

Luggage said:


> ^^^^ THIS!
> Well that is - I assume you are not running DragonCenter? Because in that case I’d recommend a fresh windows install.


@Luggage 

I figured that's what you were saying!

@Audioboxer 

@Luggage is spot on with the clean installation of Windows should you have installed any Mobo Corp "utilities" since your last clean install


----------



## Audioboxer

TimeDrapery said:


> @Luggage
> 
> I figured that's what you were saying!
> 
> @Audioboxer
> 
> @Luggage is spot on with the clean installation of Windows should you have installed any Mobo Corp "utilities" since your last clean install


Nah, I purposefully made sure this Windows 11 clean install on my new SSD was going to be as light as could be. I even used some of this to get it up and running GitHub - TheWorldOfPC/Windows11-Debloat-Privacy-Guide

There are quite a few services some are disabling that I either simply need, or the loss of QOL just doesn't make it worth it. But I have been cutting down some. While I want to get my Windows as light as possible, I do use and work on this computer, it's never going to be a bench only installation and I'm not going to break anything I use for the sake of latency appearing lower in AIDA64 outwith safe mode lol.










In regards to memory, out of boredom I'm going to go back to my 1.47v power budget and have a more in-depth play around with it.

Never ran it on the Universal profile as only knew of 1usmus v3 and anta777 back when I did this










Plus I've let go of that stupid 12/12 on tCWL/tRDWR. Just need to accept tPHYWRL going to 9 lol.

tRFC of 224 (what I run at 1.55v) obviously does not like 1.47v. I loosened up a few other timings for the 3 cycle Universal run, but I'll go back to them in the days to come. See the most I can do at 1.47v.

Still have absolutely no idea what tPHYRDL is all about, only time it is going to run 26/26 for me is when it's an uneven tCL  Tried everything now and that is simply the way it's going to be, 26/26 at tCL13/15, 28/28 at tCL14/16.


----------



## Veii

Audioboxer said:


> It'll output a text file on your desktop with running Windows services. Want to compare it to mine





Spoiler






Code:


StartType  Status Name                     DisplayName               
---------  ------ ----                     -----------               
Automatic Running AudioEndpointBuilder     Windows Audio Endpoint Builder
Automatic Running Audiosrv                 Windows Audio             
Automatic Running BFE                      Base Filtering Engine     
Automatic Running BrokerInfrastructure     Background Tasks Infrastructure Service
   Manual Running BthAvctpSvc              AVCTP service             
Automatic Running CDPSvc                   Connected Devices Platform Service
Automatic Running CoreMessagingRegistrar   CoreMessaging             
Automatic Running CryptSvc                 Cryptographic Services    
Automatic Running DcomLaunch               DCOM Server Process Launcher
   Manual Running DeviceAssociationService Device Association Service
Automatic Running Dhcp                     DHCP Client               
Automatic Running DispBrokerDesktopSvc     Display Policy Service    
Automatic Running Dnscache                 DNS Client                
Automatic Running DPS                      Diagnostic Policy Service 
Automatic Running EventLog                 Windows Event Log         
Automatic Running EventSystem              COM+ Event System         
Automatic Running FontCache                Windows Font Cache Service
   Manual Running hidserv                  Human Interface Device Service
Automatic Running IKEEXT                   IKE and AuthIP IPsec Keying Modules
   Manual Running InstallService           Microsoft Store Install Service
   Manual Running iphlpsvc                 IP Helper                 
   Manual Running KeyIso                   CNG Key Isolation         
Automatic Running LanmanServer             Server                    
   Manual Running LicenseManager           Windows License Manager Service
   Manual Running lmhosts                  TCP/IP NetBIOS Helper     
Automatic Running LSM                      Local Session Manager     
Automatic Running mpssvc                   Windows Defender Firewall 
   Manual Running NcbService               Network Connection Broker 
   Manual Running netprofm                 Network List Service      
Automatic Running NlaSvc                   Network Location Awareness
Automatic Running nsi                      Network Store Interface Service
   Manual Running PlugPlay                 Plug and Play             
Automatic Running Power                    Power                     
Automatic Running ProfSvc                  User Profile Service      
Automatic Running RasMan                   Remote Access Connection Manager
   Manual Running RmSvc                    Radio Management Service  
Automatic Running RpcEptMapper             RPC Endpoint Mapper       
Automatic Running RpcSs                    Remote Procedure Call (RPC)
Automatic Running SamSs                    Security Accounts Manager 
Automatic Running Schedule                 Task Scheduler            
Automatic Running SENS                     System Event Notification Service
Automatic Running ShellHWDetection         Shell Hardware Detection  
   Manual Running SSDPSRV                  SSDP Discovery            
   Manual Running SstpSvc                  Secure Socket Tunneling Protocol Service
   Manual Running StateRepository          State Repository Service  
   Manual Running StorSvc                  Storage Service           
Automatic Running SystemEventsBroker       System Events Broker      
Automatic Running Themes                   Themes                    
   Manual Running TimeBrokerSvc            Time Broker               
   Manual Running TokenBroker              Web Account Manager       
Automatic Running UserManager              User Manager              
Automatic Running UsoSvc                   Update Orchestrator Service
Automatic Running W32Time                  Windows Time              
Automatic Running Wcmsvc                   Windows Connection Manager
   Manual Running WdiServiceHost           Diagnostic Service Host   
   Manual Running WinHttpAutoProxySvc      WinHTTP Web Proxy Auto-Discovery Service
Automatic Running Winmgmt                  Windows Management Instrumentation
Automatic Running WlanSvc                  WLAN AutoConfig           
Automatic Running WpnService               Windows Push Notifications System Service
Automatic Running WSearch                  Windows Search




I have less, because the ISO is wiped with Optimize Offline
Just follow this post








[YT] 5950X WARZONE RAM SPEED FPS BENCHMARK







www.overclock.net




Forget 3rd party registry/powershell based cleaners. They mostly cause a spam in event viewer
Other things you just have to stop with Autoruns64
* tho i run this already on a cleaned iso. But not as clean as @umea 's. Can learn something from him/her

EDIT:
The script from you doesn't seem to show disabled ones
Automatic ones have to run to not cause an event logger spam
Manual ones are triggered by their associations ~ if needed
More things can be Manual, but you would trade user limitation for performance
To get it even cleaner ~ Optimize Offline, needs to remove more things, but that then can be called a "cut down" OS
While this is a "cleaned" updateable one



Audioboxer said:


> There are quite a few services some are disabling that I either simply need, or the loss of QOL just doesn't make it worth it. But I have been cutting down some. While I want to get my Windows as light as possible, I do use and work on this computer, it's never going to be a bench only installation and I'm not going to break anything I use for the sake of latency appearing lower in AIDA64 outwith safe mode lol.


Learn Sophia-Script , don't depend on other automated scripts.
Learn sophia and toggle what you need by yourself 
Preferably, follow the order written (Stage 1 to 6)
~ also learn Optimize-Offline for the ISO itself, KedarWolf is your good resource for such
Absolutely don't like automated multi-purpose scripts ~ from being tech support, people use such nonsense and can reinstall their windows. . .
One for every category, never such combined ones with developer favor in them


Audioboxer said:


> In regards to memory, out of boredom I'm going to go back to my 1.47v power budget and have a more in-depth play around with it.
> 
> Never ran it on the Universal profile as only knew of 1usmus v3 and anta777 back when I did this


Don't missunderstand me ~ also @mongoled
Anta's collaboration profile is perfectly fine sub 1.55v & very good at finding issues ~ even tho it test "differently/as indented" and doesn't help much on problem search
(soo same thing as HCI, GSAT, Karhu 10 000%)
* but a good config nevertheless
Just, you should not run this if you move in the 1.6+ region - well 1.65v
As no timings can stabilize this and the test crashes after finishing the first cycle (always, consistent , and any % difficulty range ~ soo it's neither discharge nor thermals)


TimeDrapery said:


> It seems hardcore but these dev(s) have done an absolutely _excellent_ job in making it quite the opposite for the majority of users interested in "trimming" their Windows installation(s)...


Strongly agree
It cleans it correctly ~ with all associations on them
Not just disables, or stops it ~ then lets windows event viewer spam "access warnings or errors" as some scheduled tasks where not cleaned


----------



## TimeDrapery

Alrighty, what do you all think about errors produced this far along into stability testing utilizing Karhu RAM Test...?










Think it has anything to do with the overboosting of Core0 to 5719MHz...? 😂😂😂😂😂

This testing iteration I'd configured *APBDIS* at "*1*" and the *SOC p-state* to "*0*"... I was under the impression this configuration should be sufficient to prevent overboosting of the cores as depicted in the screenshot above but, obviously, this is not the case...

Sooooo... I'm an attempt to resolve this issue I'll now set *DF C-States* to "_*Disabled*_", *Power Supply Idle Control* to "_*Typical Current Idle*_", and then set all other exposed *C-State* options options to "*Enabled*"...

Good plan...? Thoughts...?


----------



## KedarWolf

Audioboxer said:


> Can anyone with a low Windows processes list do this for me in powershell?
> 
> Get-Service | Select StartType, Status, Name, DisplayName | Where-Object {$_.Status -eq 'Running'} | Format-Table -AutoSize | Out-File -filepath "$Env:userprofile\Desktop\Running_Services.txt"
> 
> It'll output a text file on your desktop with running Windows services. Want to compare it to mine
> 
> 
> 
> Right now I have 93 Windows processes in task manager, that's before adding on the 80 background processes.
> 
> View attachment 2529034
> 
> 
> Crap like this I unfortunately cannot get away from, my PC _is_ for using, it's not just a test bench. So, some apps are just going to have to be running, end of, lol. But I seriously need to cut down somewhere.
> 
> View attachment 2529036
> 
> 
> This for example definitely needs to go, what a mess. Will have to Google how to totally wipe out Windows Widgets.
> 
> *edit* - OK, that was easy, winget uninstall "windows web experience pack"


The below is a stripped fully functional Windows, which has a couple of extra things like a VPN service and a few benchmark services.



Code:


StartType  Status Name                           DisplayName                                   
---------  ------ ----                           -----------                                   
   Manual Running Appinfo                        Application Information                       
Automatic Running AudioEndpointBuilder           Windows Audio Endpoint Builder               
Automatic Running Audiosrv                       Windows Audio                                 
Automatic Running BFE                            Base Filtering Engine                         
Automatic Running BrokerInfrastructure           Background Tasks Infrastructure Service       
   Manual Running camsvc                         Capability Access Manager Service             
Automatic Running CoreMessagingRegistrar         CoreMessaging                                 
Automatic Running CryptSvc                       Cryptographic Services                       
Automatic Running DcomLaunch                     DCOM Server Process Launcher                 
Automatic Running DeviceAssociationService       Device Association Service                   
Automatic Running Dhcp                           DHCP Client                                   
Automatic Running Dnscache                       DNS Client                                   
Automatic Running DPS                            Diagnostic Policy Service                     
   Manual Running EpicOnlineServices             Epic Online Services                         
Automatic Running EventLog                       Windows Event Log                             
Automatic Running EventSystem                    COM+ Event System                             
Automatic Running FastestVPNService              FastestVPN Service                           
   Manual Running fdPHost                        Function Discovery Provider Host             
   Manual Running FDResPub                       Function Discovery Resource Publication       
Automatic Running FontCache                      Windows Font Cache Service                   
   Manual Running Futuremark SystemInfo Service  Futuremark SystemInfo Service                 
   Manual Running hidserv                        Human Interface Device Service               
Automatic Running IKEEXT                         IKE and AuthIP IPsec Keying Modules           
   Manual Running InstallService                 Microsoft Store Install Service               
   Manual Running KeyIso                         CNG Key Isolation                             
Automatic Running LanmanServer                   Server                                       
Automatic Running LanmanWorkstation              Workstation                                   
   Manual Running LicenseManager                 Windows License Manager Service               
   Manual Running lmhosts                        TCP/IP NetBIOS Helper                         
Automatic Running LSM                            Local Session Manager                         
Automatic Running mpssvc                         Windows Defender Firewall                     
   Manual Running netprofm                       Network List Service                         
   Manual Running NgcCtnrSvc                     Microsoft Passport Container                 
   Manual Running NgcSvc                         Microsoft Passport                           
Automatic Running NlaSvc                         Network Location Awareness                   
Automatic Running nsi                            Network Store Interface Service               
Automatic Running NVDisplay.ContainerLocalSystem NVIDIA Display Container LS                   
   Manual Running PlugPlay                       Plug and Play                                 
   Manual Running PolicyAgent                    IPsec Policy Agent                           
Automatic Running Power                          Power                                         
Automatic Running ProfSvc                        User Profile Service                         
   Manual Running QWAVE                          Quality Windows Audio Video Experience       
Automatic Running RpcEptMapper                   RPC Endpoint Mapper                           
Automatic Running RpcSs                          Remote Procedure Call (RPC)                   
Automatic Running SamSs                          Security Accounts Manager                     
Automatic Running Schedule                       Task Scheduler                               
   Manual Running seclogon                       Secondary Logon                               
Automatic Running SENS                           System Event Notification Service             
Automatic Running SgrmBroker                     System Guard Runtime Monitor Broker           
Automatic Running ShellHWDetection               Shell Hardware Detection                     
Automatic Running Spooler                        Print Spooler                                 
   Manual Running StateRepository                State Repository Service                     
   Manual Running StorSvc                        Storage Service                               
Automatic Running SystemEventsBroker             System Events Broker                         
Automatic Running Themes                         Themes                                       
   Manual Running TimeBrokerSvc                  Time Broker                                   
   Manual Running TokenBroker                    Web Account Manager                           
Automatic Running UserManager                    User Manager                                 
Automatic Running UsoSvc                         Update Orchestrator Service                   
   Manual Running VaultSvc                       Credential Manager                           
Automatic Running Wcmsvc                         Windows Connection Manager                   
   Manual Running WdiServiceHost                 Diagnostic Service Host                       
   Manual Running WinHttpAutoProxySvc            WinHTTP Web Proxy Auto-Discovery Service     
Automatic Running Winmgmt                        Windows Management Instrumentation           
Automatic Running WpnService                     Windows Push Notifications System Service     
Automatic Running WpnUserService_7bdb3c          Windows Push Notifications User Service_7bdb3c
Automatic Running wscsvc                         Security Center


----------



## SneakySloth

Sorry to make off topic posts here but to the people using stripped/cleaned windows: have you tried to install apps from the windows store? What about games? Have you noticed any problems with general usage in these modified OSes.


----------



## KedarWolf

SneakySloth said:


> Sorry to make off topic posts here but to the people using stripped/cleaned windows: have you tried to install apps from the windows store? What about games? Have you noticed any problems with general usage in these modified OSes.


If you follow the Optimise Offline guide, Windows Store and games work perfectly. Zero issues unless you try to remove stuff you shouldn't. The guide covers it all.

Tailor it for you though, things like Wi-Fi and Bluetooth may not work with my edits in the script.









Optimize-Offline Guide - Windows Debloating Tool, Windows 1803, 1903, 19H2, 1909, 20H1 and LTSC 2019


All credit goes to GodHand and who wrote and maintains this script. And to @gdeliana who created the fork of Godhand' s Script we are using for...




forums.mydigitallife.net


----------



## Audioboxer

Veii said:


> Spoiler
> 
> 
> 
> 
> 
> 
> Code:
> 
> 
> StartType  Status Name                     DisplayName
> ---------  ------ ----                     -----------
> Automatic Running AudioEndpointBuilder     Windows Audio Endpoint Builder
> Automatic Running Audiosrv                 Windows Audio
> Automatic Running BFE                      Base Filtering Engine
> Automatic Running BrokerInfrastructure     Background Tasks Infrastructure Service
> Manual Running BthAvctpSvc              AVCTP service
> Automatic Running CDPSvc                   Connected Devices Platform Service
> Automatic Running CoreMessagingRegistrar   CoreMessaging
> Automatic Running CryptSvc                 Cryptographic Services
> Automatic Running DcomLaunch               DCOM Server Process Launcher
> Manual Running DeviceAssociationService Device Association Service
> Automatic Running Dhcp                     DHCP Client
> Automatic Running DispBrokerDesktopSvc     Display Policy Service
> Automatic Running Dnscache                 DNS Client
> Automatic Running DPS                      Diagnostic Policy Service
> Automatic Running EventLog                 Windows Event Log
> Automatic Running EventSystem              COM+ Event System
> Automatic Running FontCache                Windows Font Cache Service
> Manual Running hidserv                  Human Interface Device Service
> Automatic Running IKEEXT                   IKE and AuthIP IPsec Keying Modules
> Manual Running InstallService           Microsoft Store Install Service
> Manual Running iphlpsvc                 IP Helper
> Manual Running KeyIso                   CNG Key Isolation
> Automatic Running LanmanServer             Server
> Manual Running LicenseManager           Windows License Manager Service
> Manual Running lmhosts                  TCP/IP NetBIOS Helper
> Automatic Running LSM                      Local Session Manager
> Automatic Running mpssvc                   Windows Defender Firewall
> Manual Running NcbService               Network Connection Broker
> Manual Running netprofm                 Network List Service
> Automatic Running NlaSvc                   Network Location Awareness
> Automatic Running nsi                      Network Store Interface Service
> Manual Running PlugPlay                 Plug and Play
> Automatic Running Power                    Power
> Automatic Running ProfSvc                  User Profile Service
> Automatic Running RasMan                   Remote Access Connection Manager
> Manual Running RmSvc                    Radio Management Service
> Automatic Running RpcEptMapper             RPC Endpoint Mapper
> Automatic Running RpcSs                    Remote Procedure Call (RPC)
> Automatic Running SamSs                    Security Accounts Manager
> Automatic Running Schedule                 Task Scheduler
> Automatic Running SENS                     System Event Notification Service
> Automatic Running ShellHWDetection         Shell Hardware Detection
> Manual Running SSDPSRV                  SSDP Discovery
> Manual Running SstpSvc                  Secure Socket Tunneling Protocol Service
> Manual Running StateRepository          State Repository Service
> Manual Running StorSvc                  Storage Service
> Automatic Running SystemEventsBroker       System Events Broker
> Automatic Running Themes                   Themes
> Manual Running TimeBrokerSvc            Time Broker
> Manual Running TokenBroker              Web Account Manager
> Automatic Running UserManager              User Manager
> Automatic Running UsoSvc                   Update Orchestrator Service
> Automatic Running W32Time                  Windows Time
> Automatic Running Wcmsvc                   Windows Connection Manager
> Manual Running WdiServiceHost           Diagnostic Service Host
> Manual Running WinHttpAutoProxySvc      WinHTTP Web Proxy Auto-Discovery Service
> Automatic Running Winmgmt                  Windows Management Instrumentation
> Automatic Running WlanSvc                  WLAN AutoConfig
> Automatic Running WpnService               Windows Push Notifications System Service
> Automatic Running WSearch                  Windows Search
> 
> 
> 
> 
> I have less, because the ISO is wiped with Optimize Offline
> Just follow this post
> 
> 
> 
> 
> 
> 
> 
> 
> [YT] 5950X WARZONE RAM SPEED FPS BENCHMARK
> 
> 
> 
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> Forget 3rd party registry/powershell based cleaners. They mostly cause a spam in event viewer
> Other things you just have to stop with Autoruns64
> * tho i run this already on a cleaned iso. But not as clean as @umea 's. Can learn something from him/her
> 
> EDIT:
> The script from you doesn't seem to show disabled ones
> Automatic ones have to run to not cause an event logger spam
> Manual ones are triggered by their associations ~ if needed
> More things can be Manual, but you would trade user limitation for performance
> To get it even cleaner ~ Optimize Offline, needs to remove more things, but that then can be called a "cut down" OS
> While this is a "cleaned" updateable one
> 
> 
> Learn Sophia-Script , don't depend on other automated scripts.
> Learn sophia and toggle what you need by yourself
> Preferably, follow the order written (Stage 1 to 6)
> ~ also learn Optimize-Offline for the ISO itself, KedarWolf is your good resource for such
> Absolutely don't like automated multi-purpose scripts ~ from being tech support, people use such nonsense and can reinstall their windows. . .
> One for every category, never such combined ones with developer favor in them
> 
> Don't missunderstand me ~ also @mongoled
> Anta's collaboration profile is perfectly fine sub 1.55v & very good at finding issues ~ even tho it test "differently/as indented" and doesn't help much on problem search
> (soo same thing as HCI, GSAT, Karhu 10 000%)
> * but a good config nevertheless
> Just, you should not run this if you move in the 1.6+ region - well 1.65v
> As no timings can stabilize this and the test crashes after finishing the first cycle (always, consistent , and any % difficulty range ~ soo it's neither discharge nor thermals)
> 
> Strongly agree
> It cleans it correctly ~ with all associations on them
> Not just disables, or stops it ~ then lets windows event viewer spam "access warnings or errors" as some scheduled tasks where not cleaned


Thanks for that Veii, will do some reading.

And yeah I'm fine running 1usmus v3 as normal, just doing some experimenting. I even let a good ole extreme run last night










Some nice temps when VDIMM comes down.


----------



## sealxohd

3/3/15 40/20/20/20 didnt work for me. I had a hard time to get even into windows but this doenst look too bad as a starting point. ClkDrvStr 60 Ohms seems du be pretty bad. 58/58/58 or 57/57/57 is very important for stability. I think I need to test more procODTs and RTTs. procODT lower than 34.4 doesnt seem to good and a too high RttPark devider/off results in F9s.


----------



## XPEHOPE3

Veii said:


> Am i stupid & can't do math , or this doesn't make any sense ?


You can't do math  I think you confused yourself with parentheses while you should have computed known sums and differences before trying to move smth to the other side of the equation.



Taraquin said:


> You never answered me, therefore I asked. Thank you for the reply, but as others here wonder, what is the base value. If you need rpre to find wrrd and wrrd to find rpre you have 2 unknowns, do you really wonder why I ask?


Since you already liked the following post


anta777 said:


> *Taraquin*
> CL=CWL even
> CWL=CL-1 odd
> RAS=RC-RP
> RP=RCD
> WR=CL even 100% stable
> WTRL=RTP=WR/2
> WTRS=3(4)
> RCDWR=8
> SC=CCDS-3=1
> SCL=CCDL-3=2,3,4
> SD=DD
> RDRDSD/DD=4+RPRE-1
> WRWRSD/DD=4+WPRE-1
> RDWR=CL-CWL+5+WPRE
> WRRD=CWL-CL+4+RPRE
> tRFC ns convert timings, round up to the nearest divisible by 16.


you can easily get your WPRE and RPRE if you have 4 DIMMs or DR memory and believe those formulae. RPRE = "lowest posting RDRDSD/DD" - 3, WPRE = "lowest posting WRWRSD/DD" - 3. So for 4-4-6-6 this yields 1 and 3.



mongoled said:


> Note: APIDIS is set to 1, C-States disabled and "Typical Current" is being used, but still getting the CPU overboost bug ...
> 
> 
> 
> 
> ** EDIT2 **





TimeDrapery said:


> Think it has anything to do with the overboosting of Core0 to 5719MHz...? 😂😂😂😂😂
> 
> This testing iteration I'd configured *APBDIS* at "*1*" and the *SOC p-state* to "*0*"... I was under the impression this configuration should be sufficient to prevent overboosting of the cores as depicted in the screenshot above but, obviously, this is not the case...
> 
> Sooooo... I'm an attempt to resolve this issue I'll now set *DF C-States* to "_*Disabled*_", *Power Supply Idle Control* to "_*Typical Current Idle*_", and then set all other exposed *C-State* options options to "*Enabled*"...


For both @mongoled and @TimeDrapery TLDR it's HWiNFO bug, not your setup bug
Notice how HWiNFO reports all zeroes for minimum core clocks. I would say it's not an overboost bug. Whenever I test my Zen power monitor table monitoring utility alongside HWiNFO (yes, it does run alongside it unlike AMD monitor Tool) I get the same bug in HWiNFO with 0 minimum clocks and some overboost on max clocks. That happens because HWiNFO *doesn't get the readout of the power monitor table at all or correctly* when other utilities also try to access it. For example, ZenTimings with monitoring enabled (disable in Tools/Options) also accesses that table, as well as AMD monitor (although without proper software locks like this in ZenTimings) and whatever tools using HWiNFO API under the hood. It might be that HWiNFO can't access the table also because of other reasons (like excessive load) but I haven't seen it yet.
I'm yet to check if my tool suffers from the same bug as it updates too fast to notice all zeroes or 5GHz readings.


----------



## TimeDrapery

XPEHOPE3 said:


> You can't do math  I think you confused yourself with parentheses while you should have computed known sums and differences before trying to move smth to the other side of the equation.
> 
> 
> Since you already liked the following post
> 
> you can easily get your WPRE and RPRE if you have 4 DIMMs or DR memory and believe those formulae. RPRE = "lowest posting RDRDSD/DD" - 3, WPRE = "lowest posting WRWRSD/DD" - 3. So for 4-4-6-6 this yields 1 and 3.
> 
> 
> 
> For both @mongoled and @TimeDrapery TLDR it's HWiNFO bug, not your setup bug
> Notice how HWiNFO reports all zeroes for minimum core clocks. I would say it's not an overboost bug. Whenever I test my Zen power monitor table monitoring utility alongside HWiNFO (yes, it does run alongside it unlike AMD monitor Tool) I get the same bug in HWiNFO with 0 minimum clocks and some overboost on max clocks. That happens because HWiNFO *doesn't get the readout of the power monitor table at all or correctly* when other utilities also try to access it. For example, ZenTimings with monitoring enabled (disable in Tools/Options) also accesses that table, as well as AMD monitor (although without proper software locks like this in ZenTimings) and whatever tools using HWiNFO API under the hood. It might be that HWiNFO can't access the table also because of other reasons (like excessive load) but I haven't seen it yet.
> I'm yet to check if my tool suffers from the same bug as it updates too fast to notice all zeroes or 5GHz readings.


@XPEHOPE3

Thanks for the explanation! I appreciate you linking to your tool again as well... I appreciate you!

My takeaway for my particular case, based off what I understand now from reading what you've said, is that neither *APBDIS* nor *DF C-States* need to be configured any differently than how they're configured when loading *Optimized Defaults* ("*Auto*") as any aberration in maximum CPU frequency only just so happens to correlate with very late stability testing errors and the "apparent" relation does not, in fact, exist... Is this accurate to the best of your knowledge?

Would you be willing and able to add calculated readouts similar to how HWiNFO64 displays sensor data (*current*, *minimum*, *maximum*, and *average* values)?


----------



## Audioboxer

So the 1.47V above came about because I would get reboots from TM5 running any lower, just sort of accepted that was as low as I could go a month or so back when looking at 3800 tCL14. Well, I've just tried what I should have back then, thinking about the most voltage sensitive timing... tRFC!










Pumped tRFC up a bit and the reboots on running disappear. I know this is only 3 cycle but it shows potential for 3800 14-14-14-14 being fine at an even lower VDIMM. Just gotta be mindful of tRFC when dropping VDIMM this low. I can't quite remember what tRFC is generally stated for around 1.45v, but 240 was obviously too low.

The further down this rabbit hole I go the more I wonder why G.SKILL simply hasn't tried to bin for 3800 14-14-14-14. It would easily be their most popular kit considering FCLK 2000 is just a pipe dream for many due to AMD not having a clue what they're doing.









F4-3800C14Q-32GTZN-G.SKILL International Enterprise Co., Ltd.


G.SKILL




www.gskill.com





The kit they do sell is 14-16-16-16 at... 1.5v.

Anyway, I'll play around with 1.45v a bit more and then see if we can go lower!


----------



## XPEHOPE3

@TimeDrapery 
I only say it's very easy to force HWiNFO into erring this way so I won't trust it on core clocks at least.


TimeDrapery said:


> as any aberration in maximum CPU frequency only just so happens to correlate with very late stability testing errors


@mongoled screen says such overshoot doesn't require instability.


TimeDrapery said:


> Would you be willing and able to add calculated readouts similar to how HWiNFO64 displays sensor data (*current*, *minimum*, *maximum*, and *average* values)?


I was thinking about it. Values are easy to compute, but no place on screen to show it for all the values. Currently I consider saving min/max/avg values after exit.


----------



## Taraquin

XPEHOPE3 said:


> You can't do math  I think you confused yourself with parentheses while you should have computed known sums and differences before trying to move smth to the other side of the equation.
> 
> 
> Since you already liked the following post
> 
> you can easily get your WPRE and RPRE if you have 4 DIMMs or DR memory and believe those formulae. RPRE = "lowest posting RDRDSD/DD" - 3, WPRE = "lowest posting WRWRSD/DD" - 3. So for 4-4-6-6 this yields 1 and 3.
> 
> 
> 
> For both @mongoled and @TimeDrapery TLDR it's HWiNFO bug, not your setup bug
> Notice how HWiNFO reports all zeroes for minimum core clocks. I would say it's not an overboost bug. Whenever I test my Zen power monitor table monitoring utility alongside HWiNFO (yes, it does run alongside it unlike AMD monitor Tool) I get the same bug in HWiNFO with 0 minimum clocks and some overboost on max clocks. That happens because HWiNFO *doesn't get the readout of the power monitor table at all or correctly* when other utilities also try to access it. For example, ZenTimings with monitoring enabled (disable in Tools/Options) also accesses that table, as well as AMD monitor (although without proper software locks like this in ZenTimings) and whatever tools using HWiNFO API under the hood. It might be that HWiNFO can't access the table also because of other reasons (like excessive load) but I haven't seen it yet.
> I'm yet to check if my tool suffers from the same bug as it updates too fast to notice all zeroes or 5GHz readings.


I have SR so tyat leaves me puzzled  But can try rWRRD base of 1 or 2 as anta recommended


----------



## Taraquin

Audioboxer said:


> So the 1.47V above came about because I would get reboots from TM5 running any lower, just sort of accepted that was as low as I could go a month or so back when looking at 3800 tCL14. Well, I've just tried what I should have back then, thinking about the most voltage sensitive timing... tRFC!
> 
> View attachment 2529100
> 
> 
> Pumped tRFC up a bit and the reboots on running disappear. I know this is only 3 cycle but it shows potential for 3800 14-14-14-14 being fine at an even lower VDIMM. Just gotta be mindful of tRFC when dropping VDIMM this low. I can't quite remember what tRFC is generally stated for around 1.45v, but 240 was obviously too low.
> 
> The further down this rabbit hole I go the more I wonder why G.SKILL simply hasn't tried to bin for 3800 14-14-14-14. It would easily be their most popular kit considering FCLK 2000 is just a pipe dream for many due to AMD not having a clue what they're doing.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> F4-3800C14Q-32GTZN-G.SKILL International Enterprise Co., Ltd.
> 
> 
> G.SKILL
> 
> 
> 
> 
> www.gskill.com
> 
> 
> 
> 
> 
> The kit they do sell is 14-16-16-16 at... 1.5v.
> 
> Anyway, I'll play around with 1.45v a bit more and then see if we can go lower!


Damn, you lucky bastard. I need 1.47V for 3800cl15 flat 1T to run stable  3800cl14 needs 1.55V+, but overheats and I have SR 2 sticks which should be easier.


----------



## TimeDrapery

XPEHOPE3 said:


> @TimeDrapery
> I only say it's very easy to force HWiNFO into erring this way so I won't trust it on core clocks at least.
> @mongoled screen says such overshoot doesn't require instability.
> I was thinking about it. Values are easy to compute, but no place on screen to show it for all the values. Currently I consider saving min/max/avg values after exit.


@XPEHOPE3 

You're right, the high max CPU frequency doesn't have to come along with instability... I hadn't thought about it that way and furthermore you're absolutely correct on how how easy it is to force HWiNFO64 into displaying silly values

Phooey, that was my scapegoat this morning... Now I've actually got to think on things 😂😂😂😂😂

You thinking you want to produce a "report" of some sort that would include these calculated values? That could be pretty cool 😎😎😎😎😎


----------



## Luggage

XPEHOPE3 said:


> You can't do math  I think you confused yourself with parentheses while you should have computed known sums and differences before trying to move smth to the other side of the equation.
> 
> 
> Since you already liked the following post
> 
> you can easily get your WPRE and RPRE if you have 4 DIMMs or DR memory and believe those formulae. RPRE = "lowest posting RDRDSD/DD" - 3, WPRE = "lowest posting WRWRSD/DD" - 3. So for 4-4-6-6 this yields 1 and 3.
> 
> 
> 
> For both @mongoled and @TimeDrapery TLDR it's HWiNFO bug, not your setup bug
> Notice how HWiNFO reports all zeroes for minimum core clocks. I would say it's not an overboost bug. Whenever I test my Zen power monitor table monitoring utility alongside HWiNFO (yes, it does run alongside it unlike AMD monitor Tool) I get the same bug in HWiNFO with 0 minimum clocks and some overboost on max clocks. That happens because HWiNFO *doesn't get the readout of the power monitor table at all or correctly* when other utilities also try to access it. For example, ZenTimings with monitoring enabled (disable in Tools/Options) also accesses that table, as well as AMD monitor (although without proper software locks like this in ZenTimings) and whatever tools using HWiNFO API under the hood. It might be that HWiNFO can't access the table also because of other reasons (like excessive load) but I haven't seen it yet.
> I'm yet to check if my tool suffers from the same bug as it updates too fast to notice all zeroes or 5GHz readings.


This would be very good to know - then I can turn all c-states and other saving measures back on and concentrate on maxing boost


----------



## Audioboxer

Taraquin said:


> Damn, you lucky bastard. I need 1.47V for 3800cl15 flat 1T to run stable  3800cl14 needs 1.55V+, but overheats and I have SR 2 sticks which should be easier.












Down we go  Will keep edging down with 3 cycles till I get a quick failure, then move onto a 25 cycle with whatever the lowest is to manage a 3 cycle.

Going to eat into my tRFC performance budget again at some point, but it's still interesting to find out how low you can get VDIMM whilst not hurting your primaries.

I think kim was spot on a page or so ago, two main jackpots you can hit with memory, voltage and tRCDRD. Ideally you hit the jackpot with both, but most of us will be somewhere in the middle. tRCDRD 13 looks to be out of my grasp at 3800, but 14 is still a good result. However, on voltage, it seems this kit is right up there with what it can do either at the lower end or top end.

I've now seen tRCDRD 13 stable at 3800 on SR, just looking for the person who won the lottery with DR and got it stable.


----------



## Magyar

Hello all,
I'm currently in the process of OCing my RAM with my new 5900X and I'm kind of facing a wall.
It seems I can't possibly tightens RRDS/L and FAW. Here is a screenshot of my current timing:








I've achieved smoothly 3800C14 @ 1.5V which seems like a standard around here and it's perfectly stable.
But now I wanted to tightens all the secondaries, which usually go fine. At least, on my previous intel build with an old 6700k, I could do 4/4/16 no problems.
But here I can't even run 6/8/24 without errors.
I'm really not familiar yet with the AMD platform, so any help would be greatly appreciated. I've heard that RTT and DrvStr play a massive role, but can't find any rules or tips on how to properly set them so they are currently on Auto.
I've set ProcODT at 40, because for my MB, buildzoid said it was the perfect setting in one of his video.

My RAM is 2DIMMs Dual Rank B-die kit from G-Skill (XMP 3200C14 @ 1.35)

Thanks


----------



## Audioboxer

1.41v, errors on 0/6 within seconds.
1.42v, error on 6 within a minute.

So back to 1.43v, seems to be my absolute floor, without scrambling around trying to loosen secondaries. I did try putting tRFC higher at 1.41/1.42v and it didn't help, so it seems it's the primaries at their limit.

Speaking of tRFC, 240 seems to have its floor around 1.47v, but I dropped down from 272 to 256 and it seems to have potential, even at 1.43v. Going on the basis tRFC should be in multiples of 16.

Going to now fix the tRFC2/4 values, then try and properly test this profile at 1.43v for stability.



Magyar said:


> Hello all,
> I'm currently in the process of OCing my RAM with my new 5900X and I'm kind of facing a wall.
> It seems I can't possibly tightens RRDS/L and FAW. Here is a screenshot of my current timing:
> View attachment 2529102
> 
> I've achieved smoothly 3800C14 @ 1.5V which seems like a standard around here and it's perfectly stable.
> But now I wanted to tightens all the secondaries, which usually go fine. At least, on my previous intel build with an old 6700k, I could do 4/4/16 no problems.
> But here I can't even run 6/8/24 without errors.
> I'm really not familiar yet with the AMD platform, so any help would be greatly appreciated. I've heard that RTT and DrvStr play a massive role, but can't find any rules or tips on how to properly set them so they are currently on Auto.
> I've set ProcODT at 40, because for my MB, buildzoid said it was the perfect setting in one of his video.
> 
> My RAM is 2DIMMs Dual Rank B-die kit from G-Skill (XMP 3200C14 @ 1.35)
> 
> Thanks


First thing you should be trying for is GDM disabled/2T. Leaving GDM enabled makes it too difficult to know what is causing stability issues due to it changing things itself behind the scenes.


----------



## Taraquin

Audioboxer said:


> View attachment 2529101
> 
> 
> Down we go  Will keep edging down with 3 cycles till I get a quick failure, then move onto a 25 cycle with whatever the lowest is to manage a 3 cycle.
> 
> Going to eat into my tRFC performance budget again at some point, but it's still interesting to find out how low you can get VDIMM whilst not hurting your primaries.
> 
> I think kim was spot on a page or so ago, two main jackpots you can hit with memory, voltage and tRCDRD. Ideally you hit the jackpot with both, but most of us will be somewhere in the middle. tRCDRD 13 looks to be out of my grasp at 3800, but 14 is still a good result. However, on voltage, it seems this kit is right up there with what it can do either at the lower end or top end.
> 
> I've now seen tRCDRD 13 stable at 3800 on SR, just looking for the person who won the lottery with DR and got it stable.


If you have any tips that might lower voltage requirements on my 3800cl15 I would be grateful  1.46V gets rare error 11 in TM5 universal.


----------



## Akex

Magyar said:


> Hello all,
> I'm currently in the process of OCing my RAM with my new 5900X and I'm kind of facing a wall.
> It seems I can't possibly tightens RRDS/L and FAW. Here is a screenshot of my current timing:
> View attachment 2529102
> 
> I've achieved smoothly 3800C14 @ 1.5V which seems like a standard around here and it's perfectly stable.
> But now I wanted to tightens all the secondaries, which usually go fine. At least, on my previous intel build with an old 6700k, I could do 4/4/16 no problems.
> But here I can't even run 6/8/24 without errors.
> I'm really not familiar yet with the AMD platform, so any help would be greatly appreciated. I've heard that RTT and DrvStr play a massive role, but can't find any rules or tips on how to properly set them so they are currently on Auto.
> I've set ProcODT at 40, because for my MB, buildzoid said it was the perfect setting in one of his video.
> 
> My RAM is 2DIMMs Dual Rank B-die kit from G-Skill (XMP 3200C14 @ 1.35)
> 
> Thanks


You should start by setting GDM OFF in 2T and then set your timings.
Your cLDO VDDP is too high, 0.900 should be enough

I've set ProcODT at 40, because for my MB, buildzoid said it was the perfect setting in one of his video. > Bullshit > Depends on CPU / DRAM / CM combo


----------



## Audioboxer

Taraquin said:


> If you have any tips that might lower voltage requirements on my 3800cl15 I would be grateful  1.46V gets rare error 11 in TM5 universal.
> View attachment 2529107


Well, error 11 in Universal seems to be VDIMM related. How do I know?










vs












I knew from 1usmus v3 that 1.41v and 1.42v were out of the question. 1.43v looked promising. Obviously it was still slightly unstable. Only further question to ask is it the primaries that need 1.44v or is a tRFC of 256 just a bit too low for 1.43v.

Either way, I'd rather not run a tRFC of 272 just for the sake of saving 0.01v if the primaries would pass at 1.43v. Going to work from a baseline of 1.44v now and I'll do an overnight later.

I think you'll just be at the mercy of VDIMM, so if it needs 1.47v, that's that. You could try loosening tWTRS to 4.


----------



## Akex

Taraquin said:


> If you have any tips that might lower voltage requirements on my 3800cl15 I would be grateful  1.46V gets rare error 11 in TM5 universal.
> View attachment 2529107


Some of your timings do not seem consistent, nevertheless I have a reservation on what I am going to tell you.

To reduce the voltage requirement you can for example increase by +1 tRCDRD. Then there is also a release of tRFC which can help you.

For the timings, this is what I would correct:
tCL = 15
tRCD RD / WR = 16
tRP = 15
tRAS = tRCD + tRTP = 16 + 7 = 23
tRC = tRP + tRAS = 38


----------



## Taraquin

Akex said:


> Some of your timings do not seem consistent, nevertheless I have a reservation on what I am going to tell you.
> 
> To reduce the voltage requirement you can for example increase by +1 tRCDRD. Then there is also a release of tRFC which can help you.
> 
> For the timings, this is what I would correct:
> tCL = 15
> tRCD RD / WR = 16
> tRP = 15
> tRAS = tRCD + tRTP = 16 + 7 = 23
> tRC = tRP + tRAS = 38


I run anta777's recommendations of flat primaries, tCL+ttRCDRD=tRAS and tRC = tRAS+tRP. Anta recommended WR= or +/-1 CL. I can run tRC 42, but not below, performance is very similar, but I must up voltage by 0.01-0.02V to stabilize. I can try tRCDRD 16 and see.


----------



## Taraquin

Audioboxer said:


> Well, error 11 in Universal seems to be VDIMM related. How do I know?
> 
> View attachment 2529110
> 
> 
> vs
> 
> View attachment 2529111
> 
> 
> 
> 
> I knew from 1usmus v3 that 1.41v and 1.42v were out of the question. 1.43v looked promising. Obviously it was still slightly unstable. Only further question to ask is it the primaries that need 1.44v or is a tRFC of 256 just a bit too low for 1.43v.
> 
> Either way, I'd rather not run a tRFC of 272 just for the sake of saving 0.01v if the primaries would pass at 1.43v. Going to work from a baseline of 1.44v now and I'll do an overnight later.
> 
> I think you'll just be at the mercy of VDIMM, so if it needs 1.47v, that's that. You could try loosening tWTRS to 4.


Can try 4 wtrs and see


----------



## Akex

Taraquin said:


> I run anta777's recommendations of flat primaries, tCL+ttRCDRD=tRAS and tRC = tRAS+tRP. Anta recommended WR= or +/-1 CL. I can run tRC 42, but not below, performance is very similar, but I must up voltage by 0.01-0.02V to stabilize. I can try tRCDRD 16 and see.


Yes indeed it's not bad, moreover we can trust Anta777 on the subject. However, what I have dictated to you are the rules that Veii has put in place. I think both are viable in any case. To see if I am not mistaken either and if I understood correctly because sometimes my English leaves to be desired.


----------



## hazium233

Sorry to go back a bit...



PJVol said:


> Not literally physical, but based on a smu telemetry data, it should be clear, what voltage rail is the source for the CLDO_VDDP:
> Below is the max power observed during AIDA read bandwidth test (avg. out of 3 runs).
> 
> 
> CLDO_VDDP set in bios, V0.900​0.950​1.000​VDDCR_SOC_POWER, W13.3​13.27​13.31​VDDIO_MEM_POWER, W11.75​12.24​12.80​


Was this Cezanne, Vermeer, or both?


----------



## Audioboxer

Should be able to bring that write up a bit with some tweaking. Used to seeing it in the 59xxx range. Latency is fine, not running in safe mode so there will be a small overhead. Probably closer to 54ns in safe mode. L3 still broke on Windows 11 just now.

VSOC on auto passed a Universal 3 run, but on auto it dips below the 0.5 gap Veii said to try and keep between VDDG and VSOC. Bumped it up to 1.125v and with vdroop just about keeps the 0.5 gap. I was running 1.15v previously which drooped to about 1.125v. Higher VSOC helped previously with stabilising tCL13, low tRFC and some other things on my 1.55v profile.


----------



## umea

Might dip my toes into SR stuff for a bit to see how it is (and to cure my boredom). Is this basically the best kit I can buy that's relatively cheap? https://ca.pcpartpicker.com/product...-2-x-8-gb-ddr4-4400-cl19-memory-pvs416g440c9k

BTW. not sure if it's a mistake, but on amazon it shows xmp being 15-19-19-39, is this correct?


----------



## umea

Audioboxer said:


> View attachment 2529119
> 
> 
> Should be able to bring that write up a bit with some tweaking. Used to seeing it in the 59xxx range. Latency is fine, not running in safe mode so there will be a small overhead. Probably closer to 54ns in safe mode. L3 still broke on Windows 11 just now.
> 
> VSOC on auto passed a Universal 3 run, but on auto it dips below the 0.5 gap Veii said to try and keep between VDDG and VSOC. Bumped it up to 1.125v and with vdroop just about keeps the 0.5 gap. I was running 1.15v previously which drooped to about 1.125v. Higher VSOC helped previously with stabilising tCL13, low tRFC and some other things on my 1.55v profile.


lol are you seriously running 1.44v 3800 14? that's insane.. really wanna see what the 16gb kit of this can do on a 5700g or 5600x


----------



## Audioboxer

umea said:


> lol are you seriously running 1.44v 3800 14? that's insane.. really wanna see what the 16gb kit of this can do on a 5700g or 5600x


lol yeah, I thought I was getting away with 1.43v but got a single 11 error in Universal2. It could be to do with tRFC, but I just went to 1.44v and we're all good.

Someone a while back posted a general guideline to the voltage each tRFC milestone might need but I can't find it again.










Dropped tWTRS, tRTP and tWR back down to more familiar timings. Think I'll leave this be now for a run over night.






Buildzoid played around with the SR kit. It's as insane as you'd expect.


----------



## umea

Audioboxer said:


> lol yeah, I thought I was getting away with 1.43v but got a single 11 error in Universal2. It could be to do with tRFC, but I just went to 1.44v and we're all good.
> 
> Someone a while back posted a general guideline to the voltage each tRFC milestone might need but I can't find it again.
> 
> View attachment 2529125
> 
> 
> Dropped tWTRS, tRTP and tWR back down to more familiar timings. Think I'll leave this be now for a run over night.
> 
> 
> 
> 
> 
> 
> Buildzoid played around with the SR kit


Yeah, the 4800 C14 got me thinking about running that on a 5700g which can reach 2400fclk  wonder how low the latency can go or if it might even end up comparing to intel in terms of memory latency.


----------



## Audioboxer

umea said:


> Yeah, the 4800 C14 got me thinking about running that on a 5700g which can reach 2400fclk  wonder how low the latency can go or if it might even end up comparing to intel in terms of memory latency.


Buildzoid just casually running it at 2.0v. No problem. lol.

I think my next adventure will be going well above 1.6v and seeing what I find. To do that though I really need to sort my FCLK out, never got the USB issues fixed at 2000 FCLK.


----------



## deadfelllow

Guys, Hello

I have a problem and idk why is this happening

I was getting 51ns on aida64.

Suddenly idk why im getting 60+ latency with exactly same settings.

My FCLK=UCLK=MCLK

there isi none background apps working

anyone please?


----------



## Taraquin

Audioboxer said:


> View attachment 2529119
> 
> 
> Should be able to bring that write up a bit with some tweaking. Used to seeing it in the 59xxx range. Latency is fine, not running in safe mode so there will be a small overhead. Probably closer to 54ns in safe mode. L3 still broke on Windows 11 just now.
> 
> VSOC on auto passed a Universal 3 run, but on auto it dips below the 0.5 gap Veii said to try and keep between VDDG and VSOC. Bumped it up to 1.125v and with vdroop just about keeps the 0.5 gap. I was running 1.15v previously which drooped to about 1.125v. Higher VSOC helped previously with stabilising tCL13, low tRFC and some other things on my 1.55v profile.











For comparison, the 3800cl15 1T setup


----------



## Audioboxer

Taraquin said:


> View attachment 2529127
> 
> For comparison, the 3800cl15 1T setup


Windows 11 as well? Hope the AMD chipset drivers tomorrow fix the read/write/copy.


----------



## deadfelllow

PLEASE HELP ME they re both same timings

dont worry about motherboard. I tested rams on the new mb they was working 51-ish ns as well


----------



## Taraquin

Audioboxer said:


> Windows 11 as well? Hope the AMD chipset drivers tomorrow fix the read/write/copy.


Nah, bloated windows 10.


----------



## PJVol

Taraquin said:


> If you have any tips that might lower voltage requirements on my 3800cl15 I would be grateful


Just wanted to ask about windows' "bloatness", and then saw your post above  
because 53+ latency is higher than one may expect from these settings.
Nevertheless, I see that voltage is a bit high for the setup too. Perhaps motherboard holding it back somehow.
Here is my many times proven stable config at 1.432V Vdimm:


Spoiler: 3800 CL15

















hazium233 said:


> Was this Cezanne, Vermeer, or both?


Vermeer.
Though it would be nice, if someone kindly provide more or less accurate entries layout from a 40 00 04 or 40 00 05 pm_table (smu 66.44 or later) for cezanne.


----------



## XPEHOPE3

PJVol said:


> Though it would be nice, if someone kindly provide more or less accurate entries layout from a 40 00 04 or 40 00 05 pm_table (smu 66.44 or later) for cezanne.


Couldn't you estimate most of the table yourself from the *irusanov* tools?


----------



## Audioboxer

y-cruncher is going OK, so just an anta777 overnight and I'll feel confident saying 1.44v is locked in!










Something else of interest, I tried running tCWL 14 tRDWR 7, but it didn't boot. So 14/8 it is. I then tried 12/9, that is what my tCL13 profile runs on, no boot. 12/10 boots. Unsure if tRDWR can be voltage sensitive. My tCL13 profile does run at 1.55v, I'm at 1.44v just now.

So I guess my options are 14/8 or 12/10. Running 14/8 for overnight testing.


----------



## Mach3.2

umea said:


> Might dip my toes into SR stuff for a bit to see how it is (and to cure my boredom). Is this basically the best kit I can buy that's relatively cheap? https://ca.pcpartpicker.com/product...-2-x-8-gb-ddr4-4400-cl19-memory-pvs416g440c9k
> 
> BTW. not sure if it's a mistake, but on amazon it shows xmp being 15-19-19-39, is this correct?


XMP1 is 1.45V 4400MHz 19-19-19, XMP2 is slightly looser at a lower frequency(still 4000+MHz) at 1.35V(iirc), but still 19-19-19. I have a set of these in my drawer.


----------



## Taraquin

PJVol said:


> Just wanted to ask about windows' "bloatness", and then saw your post above
> because 53+ latency is higher than one may expect from these settings.
> Nevertheless, I see that voltage is a bit high for the setup too. Perhaps motherboard holding it back somehow.
> Here is my many times proven stable config at 1.432V Vdimm:
> 
> 
> Spoiler: 3800 CL15
> 
> 
> 
> 
> View attachment 2529134
> 
> 
> 
> 
> 
> Vermeer.
> Though it would be nice, if someone kindly provide more or less accurate entries layout from a 40 00 04 or 40 00 05 pm_table (smu 66.44 or later) for cezanne.


Do you have stock powerlimits in PBO? I can try a bit lower voltages and see how it works out, thx for tip. Ram voltage is minimum due to poor binning it seems :/


----------



## TimeDrapery

For those poor souls battling with cache / package throttling...

What are your experiences in playing with "CAC trigger" (or whatever momma mobo names it in your BIOS) configurations to see if there's relief from the issue? I believe in my Gigabyte BIOS the option I'm referring is found under AMD CBS -> ... Link...? Or perhaps... DF -> and then Link... Bah! I don't recall now! 😂😂😂😂😂


----------



## hazium233

PJVol said:


> Vermeer.
> Though it would be nice, if someone kindly provide more or less accurate entries layout from a 40 00 04 or 40 00 05 pm_table (smu 66.44 or later) for cezanne.


Hmmm, I wonder why The Stilt said it was off VDDCR_SOC when Matisse came out.

Back in the day AMD themselves said VDDIO_Mem when they did the "Let's Talk DRAM" back with Summit Ridge, I thought they mus thave changed it for the chiplet parts.

AMD Monitor in the tool Veii shared looks like it has the entry for VDDIO_Mem, was that what you were using to look at the telemetry?

I also wonder since this voltage goes to the DDR4 PHY if it somehow could alter telemetry without actually coming from it?


----------



## PJVol

hazium233 said:


> Hmmm, I wonder why The Stilt said it was off VDDCR_SOC when Matisse came out.


Idk, why don't you ask him yourself? I saw him in radeon 6800 threads.


hazium233 said:


> AMD Monitor in the tool Veii shared looks like it has the entry for VDDIO_Mem, was that what you were using to look at the telemetry?


No, sadly its too old and not much is shown correctly. I use ZenTimings and SMU Debug Tool for it.


hazium233 said:


> I also wonder since this voltage goes to the DDR4 PHY if it somehow could alter telemetry without actually coming from it?


I highly doubt it, but the only way to check it, i think, is to test the voltage at the DDR VRM output, right above the DIMM slots on pcb.


----------



## umea

Mach3.2 said:


> XMP1 is 1.45V 4400MHz 19-19-19, XMP2 is slightly looser at a lower frequency(still 4000+MHz) at 1.35V(iirc), but still 19-19-19. I have a set of these in my drawer.


thanks, picked up a pair since this is seemingly teh best b-die i can get for a "reasonable" price + since it's amazon i can return it if the sticks are poop


----------



## PJVol

XPEHOPE3 said:


> Couldn't you estimate most of the table yourself from the *irusanov* tools?


A big chunk of it, but since Renoir it's layout differes too much. Rusanov itself said it has little info regarding Cezanne pmt...
I know for sure who has, but hardly he would talk publicly, since recently hwinfo64 updates are rolling out quite often 



Taraquin said:


> Do you have stock powerlimits in PBO? I can try a bit lower voltages and see how it works out, thx for tip. Ram voltage is minimum due to poor binning it seems :/


Nah... here are the settings


Spoiler: Operating points


----------



## TimeDrapery

AHA! It's called "*CAKE CRC Perf Bounds Control*" and it can be toggled between "*Auto*" and "_*Manual*_"

Selecting "*Manual*" exposes an additional configuration field beneath itself titled, "*CAKE CRC Perf Bounds*" which allows you to input values within a range of "*0*" to "*1000000*"

Supposedly, according to the help string, this setting determines what level of performance degradation is considered acceptable before the CPU throttles...


----------



## hazium233

PJVol said:


> No, sadly its too old and not much is shown correctly. I use ZenTimings and SMU Debug Tool for it.


Hmmm. After I posted that reply I tried to use AMD Monitor to look at difference between CLDO VDDP 0.850, 0.900 and 0.950 for my 5600X. Tested Read in AIDA.

Field "Mem Power" seemed to track with CLDO VDDP, while "SOC Power" seemed to have the same peak regardless. Those were under "Power Correlation," so I was not sure what those units are and exactly what it is reporting.

Time for something else then.


----------



## PJVol

TimeDrapery said:


> Supposedly, according to the help string, this setting determines what level of performance degradation is considered acceptable before the CPU throttles...


Very interesting. So supposedly, they are CAKE's that are utilized in Zen2/3 for the on-package interconnects?


----------



## Blameless

TimeDrapery said:


> AHA! It's called "*CAKE CRC Perf Bounds Control*" and it can be toggled between "*Auto*" and "_*Manual*_"
> 
> Selecting "*Manual*" exposes an additional configuration field beneath itself titled, "*CAKE CRC Perf Bounds*" which allows you to input values within a range of "*0*" to "*1000000*"
> 
> Supposedly, according to the help string, this setting determines what level of performance degradation is considered acceptable before the CPU throttles...











Infinity Fabric (IF) - AMD - WikiChip


Infinity Fabric (IF) is a proprietary system interconnect architecture that facilitates data and control transmission across all linked components. This architecture is utilized by AMD's recent microarchitectures for both CPU (i.e., Zen) and graphics (e.g., Vega), and any other additional...




en.wikichip.org





'CAKE CRC Perf Bounds Control' suggests an adjustable tolerance for infinity fabric/interconnect errors, before reducing the speed of the link. Haven't played with it much on the few boards I have that expose it.



PJVol said:


> Very interesting. So supposedly, they are CAKE's that are utilized in Zen2/3 for the on-package interconnects?


Given what it does, I expect it's used any time anything needs to go off chip, even on package.


----------



## TimeDrapery

Hey @PJVol and @Blameless thank you for replying... I haven't had much motivation to explore the impact of different *CAKE CRC Perf* *Bounds* configs on cache latencies or overall performance as of yet but I'll be sure to do so on my next available time slot

Please be sure to keep us informed about any findings y'all come across as I'm sure that your reporting will be valuable to at least some of us in the future... Even if it's just to corroborate "normal" behaviors

Another setting, again buried within *AMD CBS*, is "*RCD Parity*"... Available options in my Gigabyte BIOS are: "*Auto*", "*Disabled*", and "*Enabled*" and loading "*Optimized Defaults*" sets this option to "_*Auto*_"

There's some Intel docs on the first page of my DuckDuckGo search results however they appear to pertain mainly to PCI... 😭😭😭😭😭


----------



## Dodgexander

Just wanted to thank everyone for their help in the thread, I've finally got stable with tight-ish timings, also stable with some negative CO+200 boost, so really pleased with my results.
Not spectacular by any means, and I could probably push it a bit more pumping more vDIMM but decided 1.56v is about as high as I want to go without some dedicated cooling.

*















*


----------



## Taraquin

PJVol said:


> Just wanted to ask about windows' "bloatness", and then saw your post above
> because 53+ latency is higher than one may expect from these settings.
> Nevertheless, I see that voltage is a bit high for the setup too. Perhaps motherboard holding it back somehow.
> Here is my many times proven stable config at 1.432V Vdimm:
> 
> 
> Spoiler: 3800 CL15
> 
> 
> 
> 
> View attachment 2529134
> 
> 
> 
> 
> 
> Vermeer.
> Though it would be nice, if someone kindly provide more or less accurate entries layout from a 40 00 04 or 40 00 05 pm_table (smu 66.44 or later) for cezanne.


Compared my 4.8GHz allcore 4000cl15 2T to my results yesterday and see that L3 scores in general are worse. Also tested with MB-limits in pbo and CPU uses 84W vs 76W stock. This improved L3 RWC to around 550GB/s. The score you posted has 650+. Is this due to very high powerlimits in pbo?








This allcore oc/ram oc is slightly unstable.


----------



## Taraquin

Dodgexander said:


> Just wanted to thank everyone for their help in the thread, I've finally got stable with tight-ish timings, also stable with some negative CO+200 boost, so really pleased with my results.
> Not spectacular by any means, and I could probably push it a bit more pumping more vDIMM but decided 1.56v is about as high as I want to go without some dedicated cooling.
> 
> *
> View attachment 2529166
> 
> View attachment 2529167
> *


Good. WR should be double of RTP, try either 10/5 or 16/8, maybe 12/6? Some get better results with scls at 4, but maybe 2 is best for you?


----------



## TimeDrapery

Alright here's some good reading on what setting "*Power Supply Idle Control*" to "*Auto*", "*Disabled*", or "*Enabled*" _actually_ does (I guess... Mechanism of action?) to influence system behaviors observed within the OS during performance / stability testing

*Low power idle states - 8.4. Declaring Processors - 08 Processor Configuration and Control - ACPI Specification 6.4 documentation - Specs - UEFI.org*


----------



## mongoled

TimeDrapery said:


> @mongoled
> 
> View attachment 2528968
> 
> 
> 😂😂😂😂😂, dude... Forreal though, I really appreciate @Veii 's explanation because the "equations / rules" I was seeing was really throwing me for a loop
> 
> I'm back to the 1usmus_v3 config as the short time I spent with the other two newer ones running intentionally "misconfigured" timings they didn't report the errors that 1usmus_v3 did, which indicated where I should look to resolve the error pattern(s)
> 
> Whether it does what @anta777 says it does or not is irrelevant to me as I'm not interested in whether that config confirms to the developer's intent, I care if it will help me to overclock my system memory
> 
> @anta777 , again, thanks for lending your expertise, experience and knowledge to the community via this thread and through making your config files available to the general public for use with TM5
> 
> @mongoled I want you to use the voodoo doll to tell Karhu to error earlier on in the tests 😂😂😂😂😂
> 
> Yup, that's Auto OC (boost override) at +200MHz, "Turbo" loadlines, and CO... Well, it's on but I dunno how close to "optimized" any curves are as each time I get to what I consider "stable" I think of something else to try and start all over 😂😂😂😂😂
> 
> I think it's telling that with both this 5800X and the 5600X I've yet to even feel the slightest inclination to explore all-core overclocking as of yet... Good job, AMD
> 
> View attachment 2528981
> 
> 
> Oh, it likes that too... We'll see what Karhu has to say about it now... The last Karhu run errored out at _*02:23:30*_ and *11775%* so we'll have to see if these changes take us further


Im sticking with my tried and tested combo, 1usmus v3, several hours of Y-Cruncher (for a 24/7 config must be at least 3 hours), RealBench (4 hours) and then some gaming.

The first image, im not wanting to guess what that is, both X & Y are "ns", huh, no idea how im meant to interpret that without guessing





Veii said:


> 70 for me on idle
> 72 peak with aida & screenshot tool or shareX
> 
> 68-69 is common  (sub 80 is fine on Win 11)
> Sub 120 is fine for daily usage
> EDIT:
> 124 right now with Discord,ShareX, Wifi and 43 operaGX tabs
> 4.6GB used (chromium) 1.3GB usage on idle
> View attachment 2528985
> 
> EDIT2:
> i didn't know P0 on a 5950X is 3.4Ghz not 3.7. Quite a difference to the 5900X


So far ive never optimised an OS for benchmarks as im not "competing" though I am curious on how much difference these optimizations will make. All ive done on my "Bench OS" is to disable AV ....



kim nk said:


> I've acquired 3800 trcrd13 possible memory by purchasing only several memories of oloy cl14 4000 cl14-15-35 1.55v and royal cl17 4800 cl17-19-19-39 1.6v. This selected yield memory was able to provide a very good required voltage and low timing for it, so that 14-14-14 straight timing was possible at about 1.55v even at 4000 clocks.


Extreme binning is the only way to go of you are wanting to find the "best dimms" other than getting extremely lucky...



Veii said:


> Anta's collaboration profile is perfectly fine sub 1.55v & very good at finding issues


What is this "collaboration" profile, hope you are not talking about "absolute" profile as my testing has shown that its missing an obvious test ....



XPEHOPE3 said:


> You can't do math  I think you confused yourself with parentheses while you should have computed known sums and differences before trying to move smth to the other side of the equation.
> 
> Since you already liked the following post
> 
> you can easily get your WPRE and RPRE if you have 4 DIMMs or DR memory and believe those formulae. RPRE = "lowest posting RDRDSD/DD" - 3, WPRE = "lowest posting WRWRSD/DD" - 3. So for 4-4-6-6 this yields 1 and 3.
> 
> For both @mongoled and @TimeDrapery TLDR it's HWiNFO bug, not your setup bug
> Notice how HWiNFO reports all zeroes for minimum core clocks. I would say it's not an overboost bug. Whenever I test my Zen power monitor table monitoring utility alongside HWiNFO (yes, it does run alongside it unlike AMD monitor Tool) I get the same bug in HWiNFO with 0 minimum clocks and some overboost on max clocks. That happens because HWiNFO *doesn't get the readout of the power monitor table at all or correctly* when other utilities also try to access it. For example, ZenTimings with monitoring enabled (disable in Tools/Options) also accesses that table, as well as AMD monitor (although without proper software locks like this in ZenTimings) and whatever tools using HWiNFO API under the hood. It might be that HWiNFO can't access the table also because of other reasons (like excessive load) but I haven't seen it yet.
> I'm yet to check if my tool suffers from the same bug as it updates too fast to notice all zeroes or 5GHz readings.


Its getting harder and harder to keep track of whats what with regards to "bugs".

Maybe we need more testing to be sure that the "overshoot" issue is not causing instabilities ??

Personally ive never had any lockups, reboots etc etc whenever HWInfo has indicated an overshoot on frequency .

And thanks for the WPRE and RPRE info





Audioboxer said:


> y-cruncher is going OK


If you are aiming for a 24/7 config, in my experience, you need to aim for at least 3 hours ...


----------



## Taraquin

PJVol said:


> A big chunk of it, but since Renoir it's layout differes too much. Rusanov itself said it has little info regarding Cezanne pmt...
> I know for sure who has, but hardly he would talk publicly, since recently hwinfo64 updates are rolling out quite often
> 
> 
> Nah... here are the settings
> 
> 
> Spoiler: Operating points
> 
> 
> 
> 
> View attachment 2529154


Ah, my cooler is not capable of that, but I got a 10-15% boost in L3 GB/s going from stock 76W PPT to MB limit of 84W, I can check HW-info but think the values are 65A TDC and 88W PPT on the MB-limit setting, allcore is running at 4.6-4.65 in CB. I can override limit with allcore OC, but my cooler thermally throttles around 110W+ in CB20, works okay in games/aida though, but I'm not okay with 1.3V+ allcore daily.

Only good thing I can say is that I run plus 200 pbo at better negatives than you (-29x2, -30x4), yay  The ****ty ram bin, underwhelming cooler and okayish MB is another matter


----------



## mongoled

@Taraquin 
You have a 4.8 Ghz all core 5600x that is AVX2 stable ??

😃😃


----------



## Veii

mongoled said:


> What is this "collaboration" profile, hope you are not talking about "absolute" profile as my testing has shown that its missing an obvious test


That one Absolute 2021 made 
It only passes on 16-16-16, well it didn't matter with the timings, but was always erroring on voltage
Sadly my A0 only scales till 1.69v and 4067 14-14 only works beyond 1.62v
soo 15-15 4200 was what it can do. Well 4267 max , on the same timings (2133 FCLK)

Running bellow 1.55v was no option for me ~ it would be a waste
Hence when this config errors beyond such voltage ~ it makes no sense for me to use it
But it makes sense to use on consumer people or gaming setups. Not enthusiasts ~ which the config did it's job well

This is solely the reason i can not give @anta777 bad critque
The config works well, for what it is told be working
Practical usecase doesn't show difference between using HCI or Karhu, or even GSAT
BUT - it remains an useful and *functional* config.

Sadly the other part of the team (am bad with names) was right about not running it beyond 1.55v
It is a mystery to me why ~ but reality shows what it shows. I really tried a lot to get it straight ~ but it doesn't look to me, that it's testing actually timings accuracy, but only chokes and discharges ~ on the way it tests
Soo i'll still title it a working and useful config - just not for anything beyond 1.55v.
It has some flaw, but am not an engineer to decipher what or where it has a flaw.
Anywho - it's working and functional , soo no bad critique from me 


mongoled said:


> Extreme binning is the only way to go of you are wanting to find the "best dimms" other than getting extremely lucky...


Gladly never had to do this. I take what i have and bruteforce my way through till it functions 
Soo when i can , with my cheap 90ish bucks B-Dies ~ everyone can , with enough time spend
They are really not great, not even average i feel like. Maaybe just reaching average level, tho i'm suspicious they aren't / compared to what i saw friends get out of their dimms


mongoled said:


> So far ive never optimised an OS for benchmarks as im not "competing" though I am curious on how much difference these optimizations will make. All ive done on my "Bench OS" is to disable AV ....


Not my style either, hence i share the ISO to friends and use on client builds. (e-sport clients)
Everything has to function. I don't care much about Safe Mode or Suicide Runs.
My scores to the community have to be set as baselines and to show what is possible.
There are far more talented OCers out there than me ~ who push beyond what i would daily. Although my "daily" already is very questionable 
==========================================
@PJVol i wish i could relate to this Overboost HWInfo part
People told me the same that HWInfo might not track it correctly

Sadly this is far from the reality i experienced
OS , ACPI tracks overboost
Hydra & CTR track overboost & the system shows hard crashes on my Overboost triggerin powerplan now with dLDO
Random hard shutdowns, even on OC_MODE

This can not be explained as "bug" but as actual issue.
I whish AMD would see it the same way and finally fix their mess
It absolutely has nothing to do with multiple readout programs interfearing and it doesn't explain the CPU on OC_Mode requesting 1.68v
Or in FIT limited PB, requesting 1.55v and peaking to 55ghz
Sorry i can not follow the explanation that was tried to be given to me

Even if Windows potentially on it's core is an issue (doubt)
The fact remains, that it does hard crashes to me with the same ACPI spikes.
Soo even if ACPI spikes where nonsense - why does it crash perfectly with the same "non existing" issue
but doesn't crash with this bug prevented. Very unlogical to me.

If this issue wouldn't exist, i've long time released my powerplan
But it's very dangerous ~ in the sense that it is too aggressive and 100% now with dLDO functionality,brings ryzens to crashes & shutdowns
The same happens on units with bad V/F curve who didn't pass stability on stock stock.

Another thing is, that this bug also got triggered for me on 4000mhz allcore CTR. Voltage was fine ~ i've fixed my bad V/F curve
It couldn't be anything other than the overboost bug that crashed it ~ only triggered by the powerplan of mine. Without it , it never crashed on the same load with the same bios settings
All these explanations that "HWInfo might be an issue" ~ make zero sense to me.
Either windows kernel is the issue (ACPI) or the Ryzen boosting system is the issue.
I push it to the 2nd one, as it even shows the same instability on macOS with native SMC power management translation
















Hydra & CTR are known to enable DF_C-States upon opening (screenshot was without Hydra mode, but normal PBO) 
* i don't have a reason to run HWInfo these days anymore
They need it soo cores hard sleep and the boosting stepping to function.
Yuri knows about this, and has implemented a protection against overboot
Sadly the bug still happens and pushes stupid voltages through it , as spikes

That started to happen more extreme, since AMD enabled L3 cache to be load balanced and doubled bandwidth
Yet it happened before, but was controlable with my powerplan and hardcaps
Which also sadly broke CPPC. Bug Free Experience™


----------



## Taraquin

mongoled said:


> @Taraquin
> You have a 4.8 Ghz all core 5600x that is AVX2 stable ??
> 
> 😃😃


Yeah, but it thermally throttles due to insufficienct cooler :/ I get halfway through CB20 and then I get 90C plus and throttling. 1.32V, medium llc. Works great in SOTTR, aida etc though. I won the lottery on 5600X on both cores and io-die (4133/2066 whea free), but crap ram bin, inferior cooler and okayish MB holds me back


----------



## ioannis91

That's where I am with the trusty old FlareX, pretty basic compared to you guys but at least I tried I guess. So what's next? tRFC 256, tWTRL 8, SCLs at 3/3 or 2/2?


----------



## Taraquin

ioannis91 said:


> That's where I am with the trusty old FlareX, pretty basic compared to you guys but at least I tried I guess. So what's next? tRFC 256, tWTRL 8, SCLs at 3/3 or 2/2?
> View attachment 2529176


Try raising volt a bit and go for 15 15 15 30 45 if that is doable? Isn't 274 correct tRFC? (144ns dividable by 16). Next step down is 244(252 if 8 is added). WR should be double RTP. WR higher than wtrl.


----------



## Veii

ioannis91 said:


> That's where I am with the trusty old FlareX, pretty basic compared to you guys but at least I tried I guess. So what's next? tRFC 256, tWTRL 8, SCLs at 3/3 or 2/2?
> View attachment 2529176


Try to match tWR with tCL
Then drop tWTR_L to the same as tRTP , soo 8
if 4-8 makes you issues, drop it to 3-8 , tWTR_S being 3

Also check both channels, if you really only have tPHYRDL 26 on both of them
At the very end, push SD, DD's to 1-5-5-1-7-7, but that will either function or error if anything overlaps
I saw that tRDWR if too tight, will make this error

EDIT:
Before all that
Make Aida64 runs , soo you actually show improvements or not in Bandwidth
Trow away the first test ~ as it wouldn't have powermanagement functioning and setted correctly
3-4 till you have less than 0.3ns variance between tests 
Usually 0.2ns or lower ~ 0.3ns deviance, can already mean instability (package throttle) or just very unoptimized OS with random Microsoft DLLs doing DPC calls


----------



## ioannis91

Veii said:


> Try to match tWR with tCL
> Then drop tWTR_L to the same as tRTP , soo 8
> if 4-8 makes you issues, drop it to 3-8 , tWTR_S being 3
> 
> Also check both channels, if you really only have tPHYRDL 26 on both of them
> At the very end, push SD, DD's to 1-5-5-1-7-7, but that will either function or error if anything overlaps
> I saw that tRDWR if too tight, will make this error
> 
> EDIT:
> Before all that
> Make Aida64 runs , soo you actually show improvements or not in Bandwidth
> Trow away the first test ~ as it wouldn't have powermanagement functioning and setted correctly


What do you mean match tWR with tCL?
Yeah, it's 26 on both channels.
isn't 1-5-5-1-7-7 looser than what I have now or that's not how it works?


----------



## Veii

ioannis91 said:


> What do you mean match tWR with tCL?
> Yeah, it's 26 on both channels.


The same as it says
tCL 16 = tWR 16


ioannis91 said:


> isn't 1-5-5-1-7-7 looser than what I have now or that's not how it works?


These one are the opposite, at least to real life behavior
To textbook they are delays
To real life they give higher bandwidth the higher you go
But if they are too high, they overlap and cause issues

EDIT:
Yet if you drop these to the lowest possible
You can drop tWTR_ lower
Depends really, but still think 1-5-5-1-7-7 for 2x8gb, 1-4-4-1-6-6 for DR or many-dimm setups


----------



## Taraquin

Veii: Is low GB/s and latency L3 in aida solely to related to package throttling or does any voltage like vddg influence this? I see I get 480-500/10.8ns with 76W PPT, 550ish/10.7ns with 88W PPT and 650ish/10.3ns with [email protected] which uses about 115W full load.


----------



## TimeDrapery

Veii said:


> That one Absolute 2021 made
> It only passes on 16-16-16, well it didn't matter with the timings, but was always erroring on voltage
> Sadly my A0 only scales till 1.69v and 4067 14-14 only works beyond 1.62v
> soo 15-15 4200 was what it can do. Well 4267 max , on the same timings (2133 FCLK)
> 
> Running bellow 1.55v was no option for me ~ it would be a waste
> Hence when this config errors beyond such voltage ~ it makes no sense for me to use it
> But it makes sense to use on consumer people or gaming setups. Not enthusiasts ~ which the config did it's job well
> 
> This is solely the reason i can not give @anta777 bad critque
> The config works well, for what it is told be working
> Practical usecase doesn't show difference between using HCI or Karhu, or even GSAT
> BUT - it remains an useful and *functional* config.
> 
> Sadly the other part of the team (am bad with names) was right about not running it beyond 1.55v
> It is a mystery to me why ~ but reality shows what it shows. I really tried a lot to get it straight ~ but it doesn't look to me, that it's testing actually timings accuracy, but only chokes and discharges ~ on the way it tests
> Soo i'll still title it a working and useful config - just not for anything beyond 1.55v.
> It has some flaw, but am not an engineer to decipher what or where it has a flaw.
> Anywho - it's working and functional , soo no bad critique from me
> 
> Gladly never had to do this. I take what i have and bruteforce my way through till it functions
> Soo when i can , with my cheap 90ish bucks B-Dies ~ everyone can , with enough time spend
> They are really not great, not even average i feel like. Maaybe just reaching average level, tho i'm suspicious they aren't / compared to what i saw friends get out of their dimms
> 
> Not my style either, hence i share the ISO to friends and use on client builds. (e-sport clients)
> Everything has to function. I don't care much about Safe Mode or Suicide Runs.
> My scores to the community have to be set as baselines and to show what is possible.
> There are far more talented OCers out there than me ~ who push beyond what i would daily. Although my "daily" already is very questionable
> ==========================================
> @PJVol i wish i could relate to this Overboost HWInfo part
> People told me the same that HWInfo might not track it correctly
> 
> Sadly this is far from the reality i experienced
> OS , ACPI tracks overboost
> Hydra & CTR track overboost & the system shows hard crashes on my Overboost triggerin powerplan now with dLDO
> Random hard shutdowns, even on OC_MODE
> 
> This can not be explained as "bug" but as actual issue.
> I whish AMD would see it the same way and finally fix their mess
> It absolutely has nothing to do with multiple readout programs interfearing and it doesn't explain the CPU on OC_Mode requesting 1.68v
> Or in FIT limited PB, requesting 1.55v and peaking to 55ghz
> Sorry i can not follow the explanation that was tried to be given to me
> 
> Even if Windows potentially on it's core is an issue (doubt)
> The fact remains, that it does hard crashes to me with the same ACPI spikes.
> Soo even if ACPI spikes where nonsense - why does it crash perfectly with the same "non existing" issue
> but doesn't crash with this bug prevented. Very unlogical to me.
> 
> If this issue wouldn't exist, i've long time released my powerplan
> But it's very dangerous ~ in the sense that it is too aggressive and 100% now with dLDO functionality,brings ryzens to crashes & shutdowns
> The same happens on units with bad V/F curve who didn't pass stability on stock stock.
> 
> Another thing is, that this bug also got triggered for me on 4000mhz allcore CTR. Voltage was fine ~ i've fixed my bad V/F curve
> It couldn't be anything other than the overboost bug that crashed it ~ only triggered by the powerplan of mine. Without it , it never crashed on the same load with the same bios settings
> All these explanations that "HWInfo might be an issue" ~ make zero sense to me.
> Either windows kernel is the issue (ACPI) or the Ryzen boosting system is the issue.
> I push it to the 2nd one, as it even shows the same instability on macOS with native SMC power management translation
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Hydra & CTR are known to enable DF_C-States upon opening (screenshot was without Hydra mode, but normal PBO)
> * i don't have a reason to run HWInfo these days anymore
> They need it soo cores hard sleep and the boosting stepping to function.
> Yuri knows about this, and has implemented a protection against overboot
> Sadly the bug still happens and pushes stupid voltages through it , as spikes
> 
> That started to happen more extreme, since AMD enabled L3 cache to be load balanced and doubled bandwidth
> Yet it happened before, but was controlable with my powerplan and hardcaps
> Which also sadly broke CPPC. Bug Free Experience™


@Veii

*YES

Thank you for sharing your thoughts on OB issues... I'm of the same mind as you*... OSPM isn't reporting less-than-veridical values for CPU frequency as the frequencies displayed are actually what's reported through the registers, regardless of duration they're held for... They're "accurate" values

I dunno about you, or anyone else that's ever OC'd a CPU, but I've never set up a stable OC at... Say... 5000MHz, for an easy example, run it at that frequency, and then restarted to UEFI in order to change the CPU frequency to 5700MHz and, somehow, (please remember this is "make believe" and is only intended to describe "what's happening" and why this could result in instability) booted the system into the OS

In real life the system would likely crash before anything of consequence occurred and you'd be left wishing you had spent the ten seconds to connect that momentary switch to the "Clear CMOS" pins when you were buttoning up your build 😂😂😂😂😂

I'm pretty sure that this is likely the reason that running ZenTimings impacts reported frequencies in HWiNFO64, not an access pile-up but rather a driver call that sets register values based off what features the OSPM supports, such as very low power idle states, and then... Voila, the CPU core frequency overshoots in a major way when boosting from one of these very low power idle states and (possible), for the same reasons why opening Ryzen Master and then setting your CPU voltage to 1.55V and your core frequencies to 5700MHz would cause your system to crash, instability results... Perhaps to a lesser extent because it's not an all-core OC that's taking place during these overboost events but system instability nonetheless


----------



## Veii

Taraquin said:


> Veii: Is low GB/s and latency L3 in aida solely to related to package throttling or does any voltage like vddg influence this? I see I get 480-500/10.8ns with 76W PPT, 550ish/10.7ns with 88W PPT and 650ish/10.3ns with [email protected] which uses about 115W full load.


Low GB L3 cache relates either to frequency throttling cores (which is not package throttling)
Or to too low powerlimits ~ and so throttling on the first stage


TimeDrapery said:


> *Thank you for sharing your thoughts on OB issues... I'm of the same mind as you*... OSPM isn't reporting less-than-veridical values for CPU frequency as the frequencies displayed are actually what's reported through the registers, regardless of duration they're held for... They're "accurate" values


I was using it as a benefit. I tamed these short spike boosts
But dlDO messed the whole thing up - and it turned into hard crashes on low idle + then single core load focused tasks
The wakeup of hardsuspended cores caused them to spike too high and cause a hard crash ~ as dLDO tries to loadbalance it

It still happens, and this time with voltage spikes
but they are not "too dangerous" as they are too small and too short timed
Sadly, real world instability is affected by this bug - soo i can not recommend enough to disable full suspension of cores to C6 state
Also sadly if this means, far more wasted power, as cores only idle to 550mhz or 0.9ish volt instead of going lower


----------



## BloodDivine

ioannis91 said:


> That's where I am with the trusty old FlareX, pretty basic compared to you guys but at least I tried I guess. So what's next? tRFC 256, tWTRL 8, SCLs at 3/3 or 2/2?
> View attachment 2529176


I hope you're using memory fast boot disabled on BIOS else it TM5 wont catch any errors


----------



## ioannis91

Taraquin said:


> Try raising volt a bit and go for 15 15 15 30 45 if that is doable? Isn't 274 correct tRFC? (144ns dividable by 16). Next step down is 244(252 if 8 is added). WR should be double RTP. WR higher than wtrl.


tRFC must be multiples of 16, right? This refers to ns or ticks? From what you said the "multiples of 16" refers to ns.


----------



## Veii

Oh short question here in the group
Can you already buy outside of the US, the X570 EVGA Dark? 
I have my eyes on it & would need it for an event OC build

Same goes to waterblocks for the dimms
Well also ram , but idk if i feel like spendin 400 bucks for a GALAX set


----------



## ioannis91

BloodDivine said:


> I hope you're using memory fast boot disabled on BIOS else it TM5 wont catch any errors


Of course, I learnt that the hard way when I had my 2600..


----------



## Veii

ioannis91 said:


> tRFC must be multiples of 16, right? This refers to ns or ticks? From what you said the "multiples of 16" refers to ns.


According to Anta777
In ticks, within 8 ticks it has to be correct - else it's suspended
Soo a range of 16 & if you hit it wrongly, it is suspended by 8nCK

I looked at different documents and have my own ways ~ for tRTPns matching
But he is correct on what he states. If you want to follow this


----------



## Taraquin

ioannis91 said:


> tRFC must be multiples of 16, right? This refers to ns or ticks? From what you said the "multiples of 16" refers to ns.


Yes. It can be others stuff aswell, but according to anta777 it works best with at number of ns\ticks that is dividable by 16, you round up to nearest number or add 8 according to him. 144ns (16x9) is 274 tRC, so 274 or 282. 128ns is 244 or 252 tRFC. 144ns usually requires around 1.45V depending on binning, 128ns usually required 1.5V or above. According to tRFC voltage scaling 1.4V can do 150ns, while 1.5V can do 1.36V, but that is for B-die in general including ****ty bins like 3000cl14 and 3200cl15, and many of us have better bins than that. Mine is a relatively poor bin, but I can do 140ns at 1.45V som even mine is slightly better than the "offical curve".


----------



## Taraquin

Veii said:


> According to Anta777
> In ticks, within 8 ticks it has to be correct - else it's suspended
> Soo a range of 16 & if you hit it wrongly, it is suspended by 8nCK
> 
> I looked at different documents and have my own ways ~ for tRTPns matching
> But he is correct on what he states. If you want to follow this


How do you calculate by using tRTPns? I see some do tRC x tRTP = tRFC, but that is not in ns. My english is not so good, but does this mean that it can work ns divideable by 8 aswell?


----------



## ioannis91

Sorry guys, I've lost you  It is in ticks or in ns after all? If I take it in ticks then 272 is correct (272/16=17), but if I take it in ns then 274 is correct (144/16=9 and 144*3800/2000=273.6, so 274).


----------



## anta777

tRFC
8 Gbit chips:
ns convert ticks, round up to the nearest multiple of 8 and add 8

16 Gbit chips:
ns convert ticks, round up to the nearest multiple of 16 and add 16


----------



## Veii

Taraquin said:


> How do you calculate by using tRTPns? I see some do tRC x tRTP = tRFC, but that is not in ns. My english is not so good, but does this mean that it can work ns divideable by 8 aswell?


Some, is the blame to me
But core was tRTPns inside tRFCns

The same went for tWRns inside tRFCns
But hence i "enforced" tWR to be 2* tRTP and tRC to be tRFC focused ~ that multiplier anchor "nonsense" , it automatically was always correct

Then when i lowered tRAS = tRCD+tRTP , tRC always was low
Soo using tRTP 8 or higher, always worked well

Focusing now tWR = tCL thanks to anta777 , was good for bandwidth and i don't have to rely on tRTP anymore
Tho still the trick of tWR = tRTP *2
which was sometimes a push of tWR 10, tRTP 5 ~ worked well

In all honestly , follow Anta's resolve for tWR
And tRFC he gave you a great range in 16's steppings
That's "accurate enough" to my eyes
The "nonsense" i do with ns conversion is witchery at best. I mean like SpaceX "it's tested in Real life, not to text books" and it works ~ but i mean, being 8nCK off if it really only postpones to 8nCK and doesn't postpone the whole tRFC.
If it is that way ~ then slightly misshitting tRFC shouldn't be an issue at all 

Soo at the end, follow it by book and stay on 16nCK
At least you will guaranteed do it right
If the range is different we'll see, all up to the end result in numbers
But you can not do anything wrong following Anta's correct writing


----------



## deadfelllow

Guys Hello,

I have a problem and i dont know why. Here is the screenshots

















Check 2 aida64 memory benchmarks.

Why is my latency high even though timings are stable at 4000.
I updated the bios latest version it didnt fix.
Ramped up the EDC TDC PPT 999 it didnt fix.
All clocks are equal.(-MEMCLK-FCLK-UCLK)
Even 3600 cl14 flat is giving me 60+ ns.

The things is I have 2 gpus installed my motherboard does this even affect cpu latency?

Timings are not the same but it doesnt matter. 4000mhz should give me at least 51-52 latency.
I tried the change procodt / drvstrs or even memvoltage. It didnt help.

I was also thinking that maybe my mobo isn't syncing my clocks.
But how come my bandwith still good for 4000?

Except l3 

@Veii @mongoled @Taraquin

Any Ideas?


----------



## Veii

deadfelllow said:


> I was also thinking that maybe my mobo isn't syncing my clocks.
> But how come my bandwith still good for 4000?
> 
> Except l3
> 
> @Veii @mongoled @Taraquin
> 
> Any Ideas?


There are 2:1 mode bugs
even 4:1 mode bugs - but it's mostly package throttle at the high FCLK
Your write is holding perfect half, soo your FCLK is not throttling (VDDG is correct)
But you still can be VDD18 throttled or SOC throttled

Another problem
Your L3 Bandwidth is lower than what i get
If all your cores really hold 4.85 - you shouldn't get 10.5ns , but 10.4
Your OS appears fine, else write wouldn't be perfect half of MCLK - 16bit lane only (bit or byte ?)

Your L3 Bandwidth is also too low on removed first stage throttling
Either you reach beyond 65c prochot on this short burst allcore test of aida
or your curve optimizer are a mess
You should hit 640-650GB/s across them
At least consistent 620+ on the Copy and surely 670 on the Read
Read to write Aida64 sometimes messes up, sometimes Write drops to 610, sometimes it's 640 - but Read always is 660-670
Copy never should be bellow 600+ ~ yet Access time latency is for you higher. Clear issue with curve optimizer. You can not hit perfect 4.85

No idea about the double MemLatency bug
Can be just random windows update for you , or sysmain service
can be VDD throttle, can be DPM LCLK throttle by having two GPUs
Enable SRIS (AMD CBS) disable LCLK PCIe if you don't run 2x PCIe 4.0 & enable ACR + AES in NBIO, SMU
Also unlock cTDP and PackagePower limits there


----------



## Audioboxer

Sadly I had a timeout last night whilst running extreme. From past experience timeout is usually either unstable CPU (I knew it wasn't this), voltage or tRFC.

The answer this time? tRFC. Seems 256 is just a little too low for 1.44v. On the basis of going with multiples of 16, 272 is needed for 1.44v. No doubt going to 1.45v or 1.46v will allow 256 to pass. But this profile is based on lowest VDIMM I can achieve for CL14.


----------



## anta777

you have 8-Gbit chips


----------



## Audioboxer

anta777 said:


> you have 8-Gbit chips


Meaning? Asking in case you are suggesting I'm doing something wrong lol. If it's about number of cycles, I normally do 6~7 overnight, just 3 right now due to needing to use PC.

My PCB out of interest



















Overall goal of this little experiment was just to see how low I could run VDIMM with primaries at the equivalent of 3800 14-14-14-14.

If the 8-Gbit chips are in reference to helping calculate tRFC, I'm running 224 fine at 1.55v, so just theorycrafting that 256 clearly fell on the side of the border of unstable at 1.44v. 272 seems to be passing fine, TM5 isn't timing out now.


----------



## mongoled

Veii said:


> That one Absolute 2021 made
> It only passes on 16-16-16, well it didn't matter with the timings, but was always erroring on voltage
> Sadly my A0 only scales till 1.69v and 4067 14-14 only works beyond 1.62v
> soo 15-15 4200 was what it can do. Well 4267 max , on the same timings (2133 FCLK)
> 
> Running bellow 1.55v was no option for me ~ it would be a waste
> Hence when this config errors beyond such voltage ~ it makes no sense for me to use it
> But it makes sense to use on consumer people or gaming setups. Not enthusiasts ~ which the config did it's job well
> 
> This is solely the reason i can not give @anta777 bad critque
> The config works well, for what it is told be working
> Practical usecase doesn't show difference between using HCI or Karhu, or even GSAT
> BUT - it remains an useful and *functional* config.


I am guessing you did not see my post where the "absolute" config would pass no problem (not using xtreme vDIMM), but 1usmus DRAM Membench would throw errors straight away !

That is not what I would call a config that catches the main issues, hence the reason im not going to use it.



Veii said:


> Gladly never had to do this. I take what i have and bruteforce my way through till it functions
> Soo when i can , with my cheap 90ish bucks B-Dies ~ everyone can , with enough time spend
> They are really not great, not even average i feel like. Maaybe just reaching average level, tho i'm suspicious they aren't / compared to what i saw friends get out of their dimms


Yeah, but the cheaper the modules the more lucky you have to get or the more bruteforce you need to use





Taraquin said:


> Yeah, but it thermally throttles due to insufficienct cooler :/ I get halfway through CB20 and then I get 90C plus and throttling. 1.32V, medium llc. Works great in SOTTR, aida etc though. I won the lottery on 5600X on both cores and io-die (4133/2066 whea free), but crap ram bin, inferior cooler and okayish MB holds me back


Well you would need to test that CPU in a non Micro/Mini motherboard to really know that regards the FCLK, regards the CPU frequency, still a nice clock, but cannot count as "stable"





BloodDivine said:


> I hope you're using memory fast boot disabled on BIOS else it TM5 wont catch any errors


Never heard of this before !


----------



## mongoled

@deadfelllow

I answered your first post in detail 27 days ago, you never replied you never replied to say how you got on or took onboard the advice of GDM OFF









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Hello guys, I have Patriot 4400c19 Kit which is currently working at 4066MHZ with 5600x(no whea errors) and GDM on. What else i can try to tighten the timings? Thanks for help. VDIMM = 1.55 Test was stable until 1.30 hours so dont worry about this timings.Its %99 stable. The timings based...




www.overclock.net


----------



## deadfelllow

mongoled said:


> @deadfelllow
> 
> I answered your first post in detail 27 days ago, you never replied or took onboard any of the advice
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Hello guys, I have Patriot 4400c19 Kit which is currently working at 4066MHZ with 5600x(no whea errors) and GDM on. What else i can try to tighten the timings? Thanks for help. VDIMM = 1.55 Test was stable until 1.30 hours so dont worry about this timings.Its %99 stable. The timings based...
> 
> 
> 
> 
> www.overclock.net


It didnt even boot at that timings as i recall correctly. I also replied " I'll try this when i got home". I tried it.

The thing is Why my latency suddenly ramped up to 60-ish's. Veii wrote tons of things and i will try. I'm also open to you.


----------



## mongoled

deadfelllow said:


> It didnt even boot at that timings as i recall correctly. I also replied " I'll try this when i got home". I tried it.
> 
> The thing is Why my latency suddenly ramped up to 60-ish's. Veii wrote tons of things and i will try. I'm also open to you.


With GDM being ON I cannot spend the excessive time to troubleshoot such a config, thats why many people ask to use a stable set with GDM OFF to help troubleshoot any issues ...


----------



## Veii

mongoled said:


> Yeah, but the cheaper the modules the more lucky you have to get or the more bruteforce you need to use


People say, my CPU is 0.001% binning
I wish i was that lucky in life

Only luck was it's a problematic unit, the 40th sample which failed being something good and was last minute downgraded
One that is unstable on stock without modifications as AMD didn't bother to fix it's V/F curve. Well they forgot to turn off 10 cores, soo i think i shouldn't blame them for a curve :^)

Yet it really is not special.
I feel it's slightly above average at best.
Sometimes silver sometimes gold. I've seen soo many better CPUs out there, and have seen soo many better dimms out there
All just bruteforcing luck ~ it really is just slightly above average. Nothing i'd prais both picks for
Got even that lucky to break my NIC. What a failure

I think i should be a good example of what everyone can achieve. It's nothing special i feel.
Working so far with 20+ ryzen systems, mine is nearly the worst of all
Only couple guys got dead CPUs by SI's who package CPUs into static foil 🤦‍♂️
Or who paid random tweaker on Twitter, to run them an allcore at 1.35+ volts for extended time while rendering and gaming at 80+C
Degraded the units to bronze samples ~ well aside from being 1.15v cLDO_VDDP ****ed up , by bad bios predictions


Spoiler: This covers around my probability - self set range






Veii said:


> Zen 3 sheet ~ many can hold 2100, package throttle will ways happen
> Package throttle does not change FCLK stability reason, but shows lack of voltage
> 
> Sample is silver/gold
> Chance out of current to draw dual CCD bugged, ~5-6%
> Chance out of first batch to get better sample ~78-80%
> Chance for drawn first batch sample to hold 2100 FCLK stable ~83%
> 
> Chance for every Vermeer sample to reach 2000 FCLK ~98%
> * if WHEA #19 does not happen, because sensor does not report wrong values
> 
> Do not ignorantly think, AMD made no progress since 2nd gen
> Substrate color changed, PSP-FW & IMC-FW changed
> Scaling and "safeness" changed
> 
> Sample has not shown any-% degradation since nearly a year
> Not in frequency, not in requested voltage for stability
> Neither DIMM nor Silicon, as ranges fall within AMDs allowed and automatically applied
> Settings are undervolts, compared to real maximum voltage range for fabric frequency
> 
> Edit:
> Personal sample can hold 2133, but package throttle still is a bit too much
> Results are not satisfying enough, compared to the 2100 set





I continue to run the ideology that nearly every sample made ~ can run 2000 FCLK stable, as Voltage prediction for it is perfectly set in stone, till 2067FCLK
2100 really was a lot of work and 2133 still to this date is not done "good enough"



deadfelllow said:


> The thing is Why my latency suddenly ramped up to 60-ish's. Veii wrote tons of things and i will try. I'm also open to you.


Your L3 issue has no connection to MCLK or UCLK. L1 and L2 scale, but L3 does not. It depends on core frequency and throttling there


----------



## deadfelllow

Veii said:


> People say, my CPU is 0.001% binning
> I wish i was that lucky in life
> 
> Only luck was it's a problematic unit, the 40th sample which failed being something good and was last minute downgraded
> One that is unstable on stock without modifications as AMD didn't bother to fix it's V/F curve. Well they forgot to turn off 10 cores, soo i think i shouldn't blame them for a curve :^)
> 
> Yet it really is not special.
> I feel it's slightly above average at best.
> Sometimes silver sometimes gold. I've seen soo many better CPUs out there, and have seen soo many better dimms out there
> All just bruteforcing luck ~ it really is just slightly above average. Nothing i'd prais both picks for
> Got even that lucky to break my NIC. What a failure
> 
> I think i should be a good example of what everyone can achieve. It's nothing special i feel.
> Working so far with 20+ ryzen systems, mine is nearly the worst of all
> Only couple guys got dead CPUs by SI's who package CPUs into static foil 🤦‍♂️
> Or who paid random tweaker on Twitter, to run them an allcore at 1.35+ volts for extended time while rendering and gaming at 80+C
> Degraded the units to bronze samples ~ well aside from being 1.15v cLDO_VDDP ****ed up , by bad bios predictions
> I continue to run the ideology that nearly every sample made ~ can run 2000 FCLK stable, as Voltage prediction for it is perfectly set in stone, till 2067FCLK
> 2100 really was a lot of work and 2133 still to this date is not done "good enough"
> 
> 
> Your L3 issue has no connection to MCLK or UCLK. L1 and L2 scale, but L3 does not. It depends on core frequency and throttling there


I Know. I'll fix the co settings. Also I'll try to disconnect 1 gpu and try bench again.

@mongoled Btw GDM is off. I was using cr2 instead of gdm on. I was asking that why is my aida64 mem latency is so high even tho my rams @4066 cl 16-15 ish 260 @trfc


----------



## Veii

deadfelllow said:


> I Know. I'll fix the co settings. Also I'll try to disconnect 1 gpu and try bench again.
> 
> @mongoled Btw GDM is off. I was using cr2 instead of gdm on. I was asking that why is my aida64 mem latency is so high even tho my rams @4066 cl 16-15 ish 260 @trfc


Problem is, the magic ball can not reach that far to the distance ~ without providing us cordinates 
(you didn't submit any screenshots, nobody knows if you where stable to begin with)
You have to check yourself if 2T was stable at all
Just changing one thing - doesn't mean it would be stable
Although the transition from GDM to 2T, does not require any voltage increase
1T then is another thing, a completely different thing which can request 40-60mV more


----------



## deadfelllow

Veii said:


> Problem is, the magic ball can not reach that far to the distance ~ without providing us cordinates
> (you didn't submit any screenshots, nobody knows if you where stable to begin with)
> You have to check yourself if 2T was stable at all
> Just changing one thing - doesn't mean it would be stable
> Although the transition from GDM to 2T, does not require any voltage increase
> 1T then is another thing, a completely different thing which can request 40-60mV more


I know 42 min or karhu %1200 is not enough. But it shoudlnt give me random latency spikes.


----------



## Mach3.2

Audioboxer said:


> Meaning? Asking in case you are suggesting I'm doing something wrong lol. If it's about number of cycles, I normally do 6~7 overnight, just 3 right now due to needing to use PC.
> 
> My PCB out of interest
> 
> View attachment 2529188
> 
> 
> View attachment 2529189
> 
> 
> Overall goal of this little experiment was just to see how low I could run VDIMM with primaries at the equivalent of 3800 14-14-14-14.
> 
> If the 8-Gbit chips are in reference to helping calculate tRFC, I'm running 224 fine at 1.55v, so just theorycrafting that 256 clearly fell on the side of the border of unstable at 1.44v. 272 seems to be passing fine, TM5 isn't timing out now.





anta777 said:


> tRFC
> *8 Gbit chips:
> ns convert ticks, round up to the nearest multiple of 8 and add 8*
> 
> 16 Gbit chips:
> ns convert ticks, round up to the nearest multiple of 16 and add 16


I think anta is trying to say you should count tRFC in multiples of 8 ticks, then add 8 more ticks, since you have 8Gb B-Dies.


----------



## mongoled

@TimeDrapery
See, now you have something to do

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Get to work adding the logic for translating ns to ticks as per size of IC

You did ask for it

😃😃

Now where is that itch ....

😂 😂


----------



## Veii

deadfelllow said:


> I know 42 min or karhu %1200 is not enough. But it shoudlnt give me random latency spikes.


It will, it's far bellow thermal equilibrium
50-60minimum, but seen it error after 1:20h too
1:30+ was fine

Karhu and HCI german community, set "stable" rating as as 10 000% not 1000%
i think you'll better of running TM5


----------



## PJVol

Veii said:


> i wish i could relate to this Overboost HWInfo part


I'm not sure I'm following all this "overboost" thingy, at least I haven't experienced anything like that.
If I got it right, the issue can be seen if powerplan is deliberately set up so that the frequency spikes starts to occur?

PS: Not sure I understand, what HWInfo has to do to it either, sorry...


----------



## Veii

PJVol said:


> If I got it right, the issue can be seen if powerplan is deliberately set up so that the frequency spikes starts to occur?
> 
> PS: Not sure I understand, what HWInfo has to do to it either, sorry...


Did i mistake again names ? 
The powerplan can force trigger it, but without it - ACPI still logs the spikes
And ACPI doesn't depend on readout software
It just overboosts and crashes if it overboosts too high

EDIT , yes i did, @XPEHOPE3 
Last page, long post


----------



## ioannis91

So if I get it correctly according to what anta777 said, 140ns=266 ticks, closest multiple of 8 is 272 and then I add 8, so 280 tRFC is the one to put in the BIOS?


----------



## Audioboxer

Mach3.2 said:


> I think anta is trying to say you should count tRFC in multiples of 8 ticks, then add 8 more ticks, since you have 8Gb B-Dies.


lol, I'm still confused. Does this not mean I'm doing it right? Anta corrected me to run 224 a week or so back, so on the basis of 224 being correct for me on my 1.55v profile it's effectively adding 16 each time then till stable?

That's what I've been doing anyway, hence 240, 256, 272. 240 noped out right away at 1.44v, 256 held on but seems to be just unstable, enough to cause a timeout. 272 is solid.


----------



## hazium233

ioannis91 said:


> So if I get it correctly according to what anta777 said, 140ns=266 ticks, closest multiple of 8 is 272 and then I add 8, so 280 tRFC is the one to put in the BIOS?





Audioboxer said:


> lol, I'm still confused. Does this not mean I'm doing it right? Anta corrected me to run 224 a week or so back, so on the basis of 224 being correct for me on my 1.55v profile it's effectively adding 16 each time then till stable?
> 
> That's what I've been doing anyway, hence 240, 256, 272. 240 noped out right away at 1.44v, 256 held on but seems to be just unstable, enough to cause a timeout. 272 is solid.


Per anta, the 8 and add 8 is supposed to take out the uncertainty of the internal values for calculating tRFC.

I would have to go back, but also thought he said to use multiples of 16. Hence 256 or 272. Or 288.

Anecdotally, I seem to have had better luck with a multiple of 16.


----------



## Audioboxer

hazium233 said:


> Per anta, the 8 and add 8 is supposed to take out the uncertainty of the internal values for calculating tRFC.
> 
> I would have to go back, but also thought he said to use multiples of 16. Hence 256 or 272. Or 288.
> 
> Anecdotally, I seem to have had better luck with a multiple of 16.


Seems I'm fine then, 256 and 272 have been what I've been playing with. 256 seems to need a little more VDIMM than 1.44v is all.


----------



## mongoled

Veii said:


> Try to match tWR with tCL
> Then drop tWTR_L to the same as tRTP , soo 8
> if 4-8 makes you issues, drop it to 3-8 , tWTR_S being 3


Oh, ive not noticed this being posted before



Will have to give this a go and the new itch erm tick theory

Is the tick and itch also applied to tRFC2/4 ??

😂 😂


----------



## hazium233

Came back to the thread to ask about WRRD value, and an equation anta777 posted.

The one in the data sheets for minimum is:

WRRD = CWL + WBL/2 + WTR_S (or L)

S for different bank group, L for same. Makes sense, as this is the purpose of WTR_ and WTR starts at end of data burst.

But the value for Ryzen in bios has never been equal to above, usually low values 1 through maybe 7 predicted. I figured it must be an offset, or part of above.

The expression anta777 posted is hard for me to understand how it could work (given WTR), although it does seem like it would space IO properly:

WRRD = CWL - CL+4+RPRE

For timing set with CWL=CL, that should work out to 5t minimum.

Which does make sense to space the bursts, but that value does not seem to align with what is working in bios. Or should we be entering 5t instead of 1,2,3, etc. Bios prediction often ~3t for mundane speeds and single rank with CWL=CL.

edit:

Hmmm actually I suppose if BC4 or even OTF, then maybe the 4 in the equation (assuming WBL/2) would go to 2, making minimum really 3t with a 1t preamble.


----------



## Mach3.2

Audioboxer said:


> lol, I'm still confused. Does this not mean I'm doing it right? Anta corrected me to run 224 a week or so back, so on the basis of 224 being correct for me on my 1.55v profile it's effectively adding 16 each time then till stable?
> 
> That's what I've been doing anyway, hence 240, 256, 272. 240 noped out right away at 1.44v, 256 held on but seems to be just unstable, enough to cause a timeout. 272 is solid.


Yeah, 16 tick increments sound about right for 8Gb IC. But what do I know, I'm just running my old stable profile for Micron Rev. B which isn't following any guidelines, just straight up 290ns converted into ticks. 😅


----------



## Audioboxer

Mach3.2 said:


> Yeah, 16 tick increments sound about right for 8Gb IC. But what do I know, I'm just running my old stable probile for Micron Rev. B which isn't following any guidelines, just straight up 290ns converted into ticks. 😅


My extent of knowledge to the absolute fine details of memory overclocking is still at the point of "Does it pass TM5/y-cruncher? Yes? PARTY! 🥳🎉🥳"

But if anyone with knowledge advises me, I'll listen/change things 🤝


----------



## ioannis91

Did the rest of the timing as we discussed before. So now should I try to lower vdimm? According to this tRFC it may or may not do 1.44v.
What about stability testing? I did the 25 cycles or 1usmus, so now do I try the anta777 preset? And then what else? OCCT, y-cruncher, linpack?








P.S. Also, what about the other voltages? vddp and vddg. How can I check their stability and if I can lower them?


----------



## XPEHOPE3

Veii said:


> Did i mistake again names ?


Yes, I just ran out of jokes to comment on it🤣
Anyway, there's an easy way to distinguish readout bug from the overboost bug. When the first happens, clocks become zero *altogether*, and then some cores readouts show overboosting. If one sees some cores with 0Hz clocks, and some with normal clocks, and then one gets overboost reading, then it's overboost bug.


----------



## Taraquin

Now I'm confused  For 8gb sticks, should we use divideable by 8 for ns or for tics? For me it wirks either way since I run 4000MHz, but at 3800MHz it's more complicated. For now I run 280 tRFC at 4000 (136ns=272tics+8).


----------



## BloodDivine

@mongoled I had issue with that. With disabled (default value) it would pass every test possible only to fail in 25' of TM5 with fast boot enabled. 

I believe someone else experienced the same behavior


----------



## Audioboxer

Taraquin said:


> Now I'm confused  For 8gb sticks, should we use divideable by 8 for ns or for tics? For me it wirks either way since I run 4000MHz, but at 3800MHz it's more complicated. For now I run 280 tRFC at 4000 (136ns=272tics+8).


Right now I'm just going to stick to "add 16 on if its not stable"


----------



## anta777

*Taraquin*
you need to subtract 8 to the minimum stable, focusing on ns in the Reous table (256,264,272,280)
it is all


----------



## anta777

*hazium233*
AMD have not WRRDsg/dg (and they are not needed, enough WTRL,WTRS) (they need Intel, because use +2 for them)
only have WRRDdr/dd.


----------



## Luggage

XPEHOPE3 said:


> Yes, I just ran out of jokes to comment on it🤣
> Anyway, there's an easy way to distinguish readout bug from the overboost bug. When the first happens, clocks become zero *altogether*, and then some cores readouts show overboosting. If one sees some cores with 0Hz clocks, and some with normal clocks, and then one gets overboost reading, then it's overboost bug.


Like this?


http://imgur.com/a/XsVZ4JD


----------



## Veii

XPEHOPE3 said:


> Yes, I just ran out of jokes to comment on it🤣
> Anyway, there's an easy way to distinguish readout bug from the overboost bug. When the first happens, clocks become zero *altogether*, and then some cores readouts show overboosting. If one sees some cores with 0Hz clocks, and some with normal clocks, and then one gets overboost reading, then it's overboost bug.


Sorry, i don't know why it happens
maybe it's the meaning of the name , trying not to say it 

Cores to become zero mhz is correct behavior of C6 suspension. They should be capable to fully hard suspend
The wake up of them , has a too high priority and doesn't shift P-States
It turns into unlimited mode and boosts as short as the core allows it before it crashes. Before the Crash fit emergency throttles back
The same goes kinda for L3 cache, but here it's falling back, hence you see dynamic results up to amount of testing and trials (patterns between read,write,copy)
L3 does dynamically give random results - till you just run all together in their order. If you cherry pick one, it always will have time to peak boost and GB/s result will be higher

Clocks can only vary and fix their P-State, according to the lowest current running p-state
They have a distance between frequency steppings and can not fixate themself at random frequencies
They only can do that if cores are forced to hard suspend ~ which is what CTR and Hydra do & so have the ability to enforce a fixed freq stepping between cores
More on this is AMD confidential , sorry

Generally if you track ACPI readout - you can see when cores fall to 0 mode or stay within 100-110,120% rating
Or peak to 2000% and so on
These % values come from the highest P state of the sample. For me it being 3.7Ghz, for a 5800X being 3.8ghz. That's what is rated as boost , % over P0 state

Edit:
10% should be 550mhz


----------



## XPEHOPE3

Audioboxer said:


> lol, I'm still confused. Does this not mean I'm doing it right? Anta corrected me to run 224 a week or so back, so on the basis of 224 being correct for me on my 1.55v profile it's effectively adding 16 each time then till stable?
> 
> That's what I've been doing anyway, hence 240, 256, 272. 240 noped out right away at 1.44v, 256 held on but seems to be just unstable, enough to cause a timeout. 272 is solid.


Refer to this post:


anta777 said:


> Samsung B-Die
> tRFC(approximately):
> 1.20V-211ns
> 1.30V-178ns
> 1.35V-160ns
> 1.40V-150ns
> 1.45V-140ns
> 1.50V-136ns
> 1.55V-120ns
> 1.60V-110ns


For 1.44 you should consider 150ns not 140ns.
Let f = frequency, d = DRAM density
tRFC ticks = (((tRFC ns * f / 2000) + d - 1) div d) * d + d
for you: ((150*3800/2000 + 8 - 1) div 8) * 8 + 8 = ((285 + 7) div 8) * 8 + 8 = 36 * 8 + 8 = 296
If you insist on 140 ns then:
((140*3800/2000 + 8 - 1) div 8) * 8 + 8 = ((266+7) div 8) * 8 + 8 = 34 * 8 + 8 = 280



Luggage said:


> Like this?


No. On screenshot you only see minimums but not the timestamps when they occured. It could have been that those minimums appeared at different times. I suggest you enable logging in HWiNFO and then check the log if at some *single time point* all core clocks become 0.
On a side note, if your PC survives SUCH clocks it can only be readout bug I think. Overvolting to get those clocks probably would kill your CPU already.


----------



## Audioboxer

XPEHOPE3 said:


> Refer to this post:
> 
> For 1.44 you should consider 150ns not 140ns.
> Let f = frequency, d = DRAM density
> tRFC ticks = (((tRFC ns * f / 2000) + d - 1) div d) * d + d
> for you: ((150*3800/2000 + 8 - 1) div 8) * 8 + 8 = ((285 + 7) div 8) * 8 + 8 = 36 * 8 + 8 = 296
> If you insist on 140 ns then:
> ((140*3800/2000 + 8 - 1) div 8) * 8 + 8 = ((266+7) div 8) * 8 + 8 = 34 * 8 + 8 = 280
> 
> 
> No. On screenshot you only see minimums but not the timestamps when they occured. It could have been that those minimums appeared at different times. I suggest you enable logging in HWiNFO and then check the log if at some *single time point* all core clocks become 0.
> On a side note, if your PC survives SUCH clocks it can only be readout bug I think. Overvolting to get those clocks probably would kill your CPU already.


Thanks, that is exactly what I was looking for yesterday.

You're probably right about 150 on the basis of 1.44v really straddling the line of "acceptable" to be trying for around 140. I'll do more testing to make sure I'm happy staying where I am on this profile.


----------



## anta777

tRFC(approximately), not exactly.


----------



## PJVol

Veii said:


> Cores to become zero mhz is correct behavior of C6 suspension. They should be capable to fully hard suspend


Just out of curiosity, could it be that VRM just cant keep up with ramping voltage/current according to the predefined C6-C0 transition latency i.e. C-state boost?


----------



## Veii

PJVol said:


> Just out of curiosity, could it be that VRM just cant keep up with ramping voltage/current according to the predefined C6-C0 transition latency i.e. C-state boost?


I don't think so tbh
It was experimental and questionable before without dLDO
But with it actually made it unusable , as dLDO tried to balance something absurd

I do think FIT catches it, but it catches it on emergency mode (emergency throttle)
Hence PB only allows 1.55v peak - while OC mode allowed it to reach 1.68v with one core up
Bizzare is to see such extreme 5 digit numbers, 13ghz. I had 55ghz far back before dLDO came

OC_Mode did let it overboost on a normal dual CCD sample to 5.9ghz @ 1.68v VID
While usually held 1.48ish

Technically Vermeers emergency limiters are far higher than that
I do think that what you saw as OC_Mode voltage, can be run on customers system
But FIT at the current state will never allow it ~ although even that was hard capped and limited down.
Real maximum voltage range is far higher than what is allowed to us.
I am not too surprised too see these near 6ghz numbers
But i'm very surprised that OC_Mode still bugs the same way out , and only on single core peaks
FIT should never allow beyond 1.55v, but yet it took 1.68v.

Well both are lower than the maximum maximum limits. That's all i should say
Nevertheless, i am sure the issue exists and has zero do to with reading out tools
It exists on Windows 10, 11 and UNIX Kernel. It existed since SMU 56.30 before dLDO which was introduced at a combination of 56.34 and 56.36/7/8 - well something from all these weekly patches.

EDIT:
With it enabled, you have around 0.2ns less aida64 latency and generally was a great thing
Wouldn't it be just that broken
Since dLDO , it was too obscure and i can nobody recommend to run it. As it can hardcrash the system
Aside from AMD enforcing a disabled C6 state via chipset updates and via bios update (changing the AUTO behavior) of the option
I keep trying it every big SMU version - but it just doesn't hold it's frequency limits and exceeds them. Nothing bad about Rocket type powerplan boost, but with this bug, it's too extreme and crashes


----------



## Taraquin

So I have 3800cl15 1t and 4000cl16 1t working now. In SOTTR they perform the same. In aida 4000 does 52ns and do 60k, 32k, 55k vs 3800 which does 53ns, 57k, 30k, 53k. In dram calc 3800 uses 101sec, 4000 uses 100. I get about 25-50MHz lower allcore CPU-speed with 4000 vs 3800 due to 4000 using a few watts more from the IO-die. I need to run soc and iod 0.04V higher on 4000, but ram runs at 0.02V lower. I think I gonna stick with 4000cl16 








EDIT: I run tRFC at 264, this was an older scr-shot.


----------



## ioannis91

How can I optimize vsoc, vddp and vddg voltages? Which stability test can find instabilities in these voltages?


----------



## SneakySloth

I've found y-cruncher to be good for that and gaming (in the form of WHEA errors).


----------



## MrHoof

Also when going down with VDDP look for tPHYRDL on both dimms if one of them is at 28 instead of 26 u went to low.


----------



## SneakySloth

I think I'm gonna call this stable now. This is with 4x8GB Patriot Viper 4400 sticks. The universal2 profile was set to 1000% @ 8 cycles from the default of 100% @ 3.


----------



## Frosted racquet

Skull_Angel said:


> Do you know if you need CCD, ProcODT, AddrCmdDrvStr at those values for stability? If not, I'd try 0.9-0.94v, 34.3, 20.


VDDG CCD 940mV caused a restart in ycruncher, but passed both 1usmus and universal configs. Reverting CCD to 1v and keeping other suggested values passed ycruncher and both TM5 configs. Thanks for the suggestions.

Which game can scale with tightened timings? Preferably with built in benchmarks. Is Shadow of the Tomb Raider sensitive to RAM settings?


----------



## PJVol

MrHoof said:


> Also when going down with VDDP look for tPHYRDL on both dimms if one of them is at 28 instead of 26 u went to low.


What you mean "went to low" ?
I've had them 26/28 4 out of 5 boots on my 4000c16 2x8 gvka kit, and haven't seen any relation to VDDP yet.


----------



## Blameless

PJVol said:


> What you mean "went to low" ?
> I've had them 26/28 4 out of 5 boots on my 4000c16 2x8 gvka kit, and haven't seen any relation to VDDP yet.


Some setups are seeing a correlation between VDDP anf tPHYRDL. I can reliably get 28/28, a mix of 26/28, always get 26/26s on my 5800X/ASrock ITX setup by adjusting VDDP and I'm not the only one who has observed such behavior. I do have other setups where it doesn't seem to matter, however.


----------



## Veii

Taraquin said:


> I get about 25-50MHz lower allcore CPU-speed with 4000 vs 3800 due to 4000 using a few watts more from the IO-die. I need to run soc and iod 0.04V higher on 4000, but ram runs at 0.02V lower. I think I gonna stick with 4000cl16


Extend stock artificial limits which where rated for 1800FCLK, then maybe think about if CO needs globally a -2 drop
And push VDD line to around 1.83-1.86v
Shouldn't need 1.93v yet

Also doublecheck afterwards the result between 28 & 30 ProcODT
When you found that out, blindly push SOC higher and see if any throttling appears on latency (if results get better at all
They either will strongly or wont at all)
^ this is your sign if you lack power somewhere, IOD, VDD18, or maybe run too high cLDO_VDDP
ProcODT has to stay low, but too low can require other sides to be pushed down in voltage (VDDP, VDDG)

Then if this results in instability, you need to change how RTTs function slightly
More RTT_NOM helps, if cLDO_VDDP was too low
Not too low for IMC but too low for dimms powering
It's rare that 16 gb sets would need ClkDrvStr 60, soo thats the points to push

Keep in mind, too high VDD18 can cause instability and mess up VDDG CCD voltage or generally cause y-cruncher to crash cores
GL


----------



## PJVol

Blameless said:


> Some setups are seeing a correlation between VDDP anf tPHYRDL


I understand that may very well be the case, I just don't see this myself trying various mem setups, where, for example 26/28 may (and most likely do) occur either with vddp 0.85 or 1.05 v.
Anyway, gonna check it once more.

EDIT:
Yeah, you're right. Just checked and with a 4000CL16 setup, default VDDP 0.85 gives 26/28 phy RL's.
Setting it to 0.900 brings it back to 26/26, indeed, though didn't affect AIDA cachemem results.


Spoiler: 26/26

















Spoiler: 26/28














Got to check if it help with a [email protected] or [email protected] (may be stability wise).
--------------
Checked. VDDP 0.900
4200CL16 - both latencies 28.
4200CL15 - both are 26.


----------



## Taraquin

Veii said:


> Extend stock artificial limits which where rated for 1800FCLK, then maybe think about if CO needs globally a -2 drop
> And push VDD line to around 1.83-1.86v
> Shouldn't need 1.93v yet
> 
> Also doublecheck afterwards the result between 28 & 30 ProcODT
> When you found that out, blindly push SOC higher and see if any throttling appears on latency (if results get better at all
> They either will strongly or wont at all)
> ^ this is your sign if you lack power somewhere, IOD, VDD18, or maybe run too high cLDO_VDDP
> ProcODT has to stay low, but too low can require other sides to be pushed down in voltage (VDDP, VDDG)
> 
> Then if this results in instability, you need to change how RTTs function slightly
> More RTT_NOM helps, if cLDO_VDDP was too low
> Not too low for IMC but too low for dimms powering
> It's rare that 16 gb sets would need ClkDrvStr 60, soo thats the points to push
> 
> Keep in mind, too high VDD18 can cause instability and mess up VDDG CCD voltage or generally cause y-cruncher to crash cores
> GL


It seems MB limit was 150W, and well over 100A on both edc and tdc. Yet in CB it maxes out at 84W, only allcore oc allows fpr greater powerdraw. I have tested soc, vddg and vddp voltage. If I drop soc and iod by 20mv or more I get slightly worse aida scores and more fluctuations, dropping 10mv gives same result, tried higher aswell but made no difference. Ccd and vddp lower refuses to boot, but I find no positive/negative using higher voltage that I can recall, but can try again, so far I've kept them low to hold pwr-bugdet down. I have done little testing with other ProcODT, that might be worth looking into.


----------



## Veii

Taraquin said:


> EDIT: I run tRFC at 264, this was an older scr-shot.


This is your goal to beat
Me, following anta's ruleset blindly








Stock expectations and right usually my CO
i needed 1.53vDIMM
it can be possible at 1.46, but hence RTT was different & i just reused everything from 2100 down ~ this is the score you have to beat or approach (L1,L2,L3 included)
* i was hitting this






with tRTP 6 and tCWL 14 (accidents)
but couldn't stabilize it in the short time since the morning ~ soo this above should be fine as your realistic target & goal


----------



## Audioboxer

Veeeeeiiii, when do you get your DR sticks? Excited to see what you find 🤝

After watching Buildzoid hit 2.0v on the SR version of my kit I'm after someone on DR who isn't afraid of VDIMM 






Speaking of ClkDrvStr 60 it's the one thing that helped me run tRCDRD 13 at 3800 for a bit longer than "instant error 6s". Not sure what that tells me though. Going to assume IMC might just not be good enough to even attempt tRCDRD 13 at 3800.

I know tRCDRD doesn't really scale with voltage outwith the minimum voltage it requires to attempt to run, but I'd be interested to find out if I go to biiiig voltages, like 1.65v+, if it helps at all with tRCDRD 13 at 3800.

All that said, my next goal is probably trying to work on IF above 1900 some more. I hate it though, the USB instability is annoying AF and when I see the voltages needed at the mobo level to even try and hit 2000 with some stability it just gets me angry at AMD


----------



## Taraquin

Veii said:


> This is your goal to beat
> Me, following anta's ruleset blindly
> 
> 
> 
> 
> 
> 
> 
> 
> Stock expectations and right usually my CO
> i needed 1.53vDIMM
> it can be possible at 1.46, but hence RTT was different & i just reused everything from 2100 down ~ this is the score you have to beat or approach (L1,L2,L3 included)
> * i was hitting this
> View attachment 2529289
> with tRTP 6 and tCWL 14 (accidents)
> but couldn't stabilize it in the short time since the morning ~ soo this above should be fine as your realistic target & goal


Thx for taking the time. This with stock powerlimit aswell? With +200 pbo+CO and stock pwr-limit I get around 500GB/s on all L3 and 10.7-8ns, max 76W draw and 4.55-4.58GHz CB23 AC speed. My latency is 52, R/W/C is very similar to yours. With MB limit I get 550GB/s and 10.6-7ns, 84W pwr draw and 4.6-4.65GHz CB23 speed. I get ram overheat in TM5 if I use more than 1.48v (actual 1.5v), at 1.46v lowest I get tRC and tRFC is 45/280, lower gets errors due to voltage.

I can try your settings of procODT, cad etc and see how I fare  I'm beginning to wonder if my MB limits L3-perf when using CO+pbo since allcore OC gets significantly better L3-scores.

My allcore [email protected] avx-throttler got way better scores. Run in safety mode so latecy is actually 51 in standard windows.








On the 4.8 I get expected L3-scores.


----------



## PJVol

*@Veii*
After reading your description for the Error 11 in 1usmus config, I tried almost every timing/resistance/voltage to combat it, while testing this:
(almost every **** setting, except one)

















Finally got rid of it by raising Vsoc (it turned out 1,200V just wasn't enough).
So feel free to add it the list of possible sources for that error - lack of voltage for the UMC 
Btw, are all these rtt's can really help to lower Vdimm, or it's just kind of lottery or woodoo magic?

Sadly, this entry-entry-level board do mind running higher MCLK, so I'm finally stuck with memory config as below, and it wants ~ 1.62-1.63V










Any tips as to lower Vdimm?


----------



## Veii

Audioboxer said:


> Veeeeeiiii, when do you get your DR sticks? Excited to see what you find 🤝











Soon™ 
This week has potentially a 5900X build ongoing, but parts likely won't arrive till Friday/Monday
Ram maybe can arrive on Wednesday.

What should i bench it on, 3800 or just max out 4200/4267 again ?
Any wishes ?
Maybe just 1T pure any Freq ?


Taraquin said:


> This with stock powerlimit aswell?


Stock but without powerlimits
Else L3 cache will throttle up to SOC load and so it will not be comparable.
Other was my daily CO +200 @ 94c thermal limit (it will throttle at 65c prochot, but just so another throttle sensor is not triggered)

Most interesting is the tiny "non existent" frequency scaling on Aida64 - when you load all cores
On single core affinity focused, i can see latency dropping further and potentially breaking the algorithm ~ but that's unlikely the goal here

Idk about safemode, never got good results on it
It always loaded more services, than my normal installation & didn't support CPPC nor C-States correctly (well it didnt at all)
All results on it where worse than on the normal windows ~ for me 


PJVol said:


> *@Veii*
> After reading your description for the Error 11 in 1usmus config, I tried almost every timing/resistance/voltage to combat it, while testing this:
> (almost every **** setting, except one)
> 
> View attachment 2529293
> View attachment 2529294
> 
> 
> Finally got rid of it by raising Vsoc (it turned out 1,200V just wasn't enough).
> So feel free to add it the list of possible sources for that error - lack of voltage for the UMC
> Btw, are all these rtt's can really help to lower Vdimm, or it's just kind of lottery or woodoo magic?
> 
> Sadly, this entry-entry-level board do mind running higher MCLK, so I'm finally stuck with memory config as below, and it wants ~ 1.62-1.63V
> 
> View attachment 2529298
> 
> 
> Any tips as to lower Vdimm?


Thank you
Yes i need to start updating some stuff & probably fix couple of things for non 8gb user. Although it remans witchery for everyone.

Also need to update the errors really
Today was stuck on #5 , a spam of 3 in the first cycle
It ended up being a combination of "too high SD & DDs" with "too high tRRD_" 
That was fixed ~ didn't know "too high tRRD_" can cause issues too 


PJVol said:


> Btw, are all these rtt's can really help to lower Vdimm, or it's just kind of lottery or woodoo magic?


Heat is an issue, but it wasn't for me 
RTTs change how VDIMM + cLDO_VDDP +? /? procODT ~ behave

Here i needed 1.53vDIMM, else on 005 i needed 1.46vDIMM
Yet this 1.46v where hotter in general 

RTTs do change things
But it's a bit too much trial and error to get data-eye looking clean.
We technically can export memory training and data-eye logs , but practically i still have no idea where in ABL which partition and location ~ these readouts get exported.

A bit unfamiliar with Monolithic CPUs to help you, but what does control the fabric
Is it really SOC only ?
Wouldn't VDD18 push instead of SOC rather help ?
You have playroom till 1.3v SOC, but this still cuts soo deeply into the powerbudget ~ there has to be other options too
How is prochot on this unit
Also little requoted leak:








No IMC FW change. I think Zen3D will not have any advantages in MCLK OC. But we can hope WHEA #19 sensoric issues got resolved finally


----------



## PJVol

Veii said:


> A bit unfamiliar with Monolithic CPUs to help you, but what does control the fabric


I don't think there's a way to control it even in Vermeer - you just have to look how the SoC power abrupltly increases when crossing some FCLK "checkpoints", such as 1800, 2000 etc, and I see no changes in any metrics reflecting such a jumps.



Veii said:


> Wouldn't VDD18 push instead of SOC rather help ?
> You have playroom till 1.3v SOC, but this still cuts soo deeply into the powerbudget ~ there has to be other options too


I think the chip itself is fine and can run at least 2400 FCLK, rather it's the motherboard is limiting memory OC - cheap 4 layer pcb in contrast to 6-8 layer ITX boards and beefy VRMs from other vendors.
Vsoc in bios menu turns "warning red" when set above 1.350V, which one can assume hereof, is Vsoc max safe voltage for the Cezanne. And basically it consumes nothing, compared to Vermeer.












Veii said:


> But we can hope WHEA #19 sensoric issues got resolved finally


I still stands on it being the interposer issues, i.e. hella lot of interfaces and very high speed links, jumping off silicon passing it through and back )). IMO it's unlikely to be resolved until zen4.


Veii said:


> Wouldn't VDD18 push instead of SOC rather help ?


May be it help to stabilize some clock domains in the fabric's global one, but again, FCLK is not a problem with Cezanne.



Veii said:


> How is prochot on this unit


There's а much funnier thing - timed power limit (STAPM), which I immediately disable and forget 
As for procHOT - never saw it being asserted, either on 5600X or 5700G


----------



## Veii

PJVol said:


> I don't think there's a way to control it even in Vermeer - you just have to look how the SoC power abruptly increases when crossing some FCLK "checkpoints", such as 1800, 2000 etc, and I see no changes in any metrics reflecting such a jumps.


will need to test
higher frequency should be a bit higher amperage, but never noticed such thing


PJVol said:


> I still stands on it being the interposer issues, i.e. hella lot of interfaces and very high speed links, jumping off silicon passing it through and back )). IMO it's unlikely to be resolved until zen4.


It's strange that only bugged units don't have these issues.
Kind of still waiting for 2000 FCLK stable units who where not bugged to begin with.
Makes it more strange, when you think it's just a last minute LowLv-FW update that differentiates this unit from being a 16 core or a 6 core. It wasn't manufactured to be bugged or different. Yet behavior is different ~ but sadly consistent on all dual CCD bugged units
They all come from the same fab too, as others in europe for example where not active at this point of time.


PJVol said:


> There's а much funnier thing - timed power limit (STAPM), which I immediately disable and forget


Riight i forgot about this, likely SOC-P States function too ? 
You can disable such ?
If you have LCLK in AMD OVERCLOCKING - try disabling that. It bugs SMU out, bugs THM and power reporting.
Wonder if Cezanne will show the same issues


PJVol said:


> I think the chip itself is fine and can run at least 2400 FCLK, rather it's the motherboard is limiting memory OC - cheap 4 layer pcb in contrast to 6-8 layer ITX boards and beefy VRMs from other vendors.


mmmm
Only thing is your procODT looking high


PJVol said:


> As for procHOT - never saw it being asserted, either on 5600X or 5700G


Not sure i understand


----------



## PJVol

Veii said:


> It wasn't manufactured to be bugged or different.


Not that hard to imagine you'd have a whea-fest if it was ))



Veii said:


> higher frequency should be a bit higher amperage, but never noticed such thing


It may be your funny-chip didn't show it for some reason, but here are the power figures with various mclk/fclk and 1.000V Vsoc (running tm5):
3200 : 7W
3400 : 11.8W
3600 : 12.5W
3800 : 12.7W
and the story get better
3800 (Vsoc 1.05V) - 14W
3800 (Vsoc 1.1V) - 15W
4000 (Vsoc 1.1V) - 14W
Does it look like you're in control of it?


----------



## Veii

PJVol said:


> Not that hard to imagine you'd have a whea-fest if it was ))


The problem is, it does log #19s
But i don't get them so far

Got it only once, when i was doing really stupid things
It does log #18s too , which gladly do not come anymore


PJVol said:


> 3800 (Vsoc 1.1V) - 15W
> 4000 (Vsoc 1.1V) - 14W
> Does it look like you're in control of it?


This one could equally be just core frequency throttle or CCA package throttle
I'll check till the next post


----------



## PJVol

Veii said:


> But i don't get them so far


I really have no idea, what's exactly behind those issues, but applying simple logic, one can assume that 5600/5800 with disabled CCD has something twice as much (or as many) as a normal 5600/5800, besides the cores and caches, so this doubled resources is enough to keep 5600X interconnects in business and working as it should, not sure about 5800Х though
In addition, if we let the interposer go to hell with all its routing and extra switches, repeaters, etc... Boom! - 5700G and no whea.
Isn't it magic?


----------



## XPEHOPE3

Veii said:


> What should i bench it on, 3800 or just max out 4200/4267 again ?
> Any wishes ?
> Maybe just 1T pure any Freq ?


I'd wish to see proper RTTs/procODT recommendations for 2T for current BIOSes first.


PJVol said:


> As for procHOT - never saw it being asserted, either on 5600X or 5700G


Asserted as in HWiNFO? I never saw it either. But core frequency is limited anyway by one of the PMT limiters, just not the one named "procODT" in AMD monitor


----------



## umea

Are you going to be binning your 5900x Veii? Curious to see your results as you'd probably have the same configuration as me (using the same phantom ITX board for this one?)

Mostly just curious about what you'll be able to run in general, so far I've only found 1 or 2 instances of people being able to run 3800 flat 14 with DR on a 5900x period.


----------



## Veii

umea said:


> Are you going to be binning your 5900x Veii? Curious to see your results as you'd probably have the same configuration as me (using the same phantom ITX board for this one?)


Maybe, if time stays
It is projected to be on a B550 Creator
Actually this should be guaranteed I225-V Rev.03 not 02
If this board doesn't reach 60c , then the ITX can easily run it

Wonder if it is fair, as ASUS's CBS on this board is fully unlocked ~ but memory training feels more trustworthy on the ITX now


umea said:


> Mostly just curious about what you'll be able to run in general, so far I've only found 1 or 2 instances of people being able to run 3800 flat 14 with DR on a 5900x period.


Have only 1 week to build & bench , but I'll give my best
On this build i can't bench the 3070ti much. Just an e-sport warzone build where RAM timings and CPU Freq matters

Where these 2x8 or 2x16 ?
The showcase build will be interesting for you (next month),
Trying to get an EVGA X570 DARK and some 6900XTXH (not for me sadly) 😅


----------



## umea

Veii said:


> Maybe, if time stays
> It is projected to be on a B550 Creator
> Actually this should be guaranteed I225-V Rev.03 not 02
> If this board doesn't reach 60c , then the ITX can easily run it
> 
> Wonder if it is fair, as ASUS's CBS on this board is fully unlocked ~ but memory training feels more trustworthy on the ITX now
> 
> I'll give my best,
> On this build i can't bench the 3070ti much. Just an e-sport warzone build where RAM timings and CPU Freq matters
> 
> Where these 2x8 or 2x16 ?
> The showcase build will be interesting for you (next month),
> Trying to get an EVGA X570 DARK and some 6900XTXH (not for me sadly) 😅


2x16gb, one of which I think I saw on this thread a little while back. Like we had previously discussed 5900x seems to just be the worst in this generation for ram overclocking in terms of netting lower latencies. 5950xs being the top bin seems to give them some more wiggle room.

I would love to get an x570 dark for myself as well, I was thinking of selling my current rig (throwing the 6800XT I have laying around in instead of my 3080ti) and building another one. Not sure yet though. Might wait for next gen. I'm basically at a dead end in my RAM OCing with current hardware (spent around 100 hours trying to push further but no luck). My 5900x can't even handle tRCDRD 14 with either one of my sticks in either of my dimms on my Phantom ITX b550 board. I have PVS 4400C19 16gb kit coming in today, so I'll see.


----------



## Veii

umea said:


> (spent around 100 hours trying to push further but no luck)
> 
> 
> 
> My 5900x can't even handle tRCDRD 14 with either one of my sticks in either of my dimms on my Phantom ITX b550 board.
Click to expand...

I'm sorry to hear that
Oh umea, can you check your board NIC's revision








Like this
I've seen couple of Rev.02 and Rev.03 ITX/AX

Did you just bench timings or invested time into trial and error , RTTs ?
EDIT:
This might help you (loadlines and so on)













Only VDIMM changes between presets i'm trying


----------



## VPII

I am going to ask maybe a stupid question. I've been running Aida64 Cache & Memory benchmark a number of times without an issue while still on Windows 10, but recently when I run the benchmark it would reach the memory Memory Copy and the system would restart shortly there after, so I cannot run it to see where my latency is at. Running Maxxmem2 works fine. I even ran Karhu Memtest till 20 000% without an issue as per the attached picture. What would cause Aida64 Cache and Memory benchmark to fail like this?


----------



## umea

Veii said:


> I'm sorry to hear that
> Oh umea, can you check your board NIC's revision
> 
> 
> 
> 
> 
> 
> 
> 
> Like this
> I've seen couple of Rev.02 and Rev.03 ITX/AX
> 
> Did you just bench timings or invested time into trial and error , RTTs ?


I'll check my board's revision when I get home and check what firmware/bios version I'm on too for you. I invested entirely into trial and error and RTTs (didn't do a ton of benchmarking at all to be honest, I just wanted to try to figure out how to get it done). I tried just about every possible combination (if not every one, it's been a month or two) and still no luck. Tried a bunch to try to stabilize anything above 1900fclk but restarts occur on everything regardless of the voltages I tried.

Also I believe I copied those settinsg a while ago but I'll give it a shot again and see. Still need to take off the copper heatsinks off my sticks.


----------



## Veii

umea said:


> I tried just about every possible combination (if not every one, it's been a month or two) and still no luck.
> 
> Also I believe I copied those settinsg a while ago but I'll give it a shot again and see


Recently 2.5(5)V rail was causing issues and i've dropped that down to 2.45. It resolved
VDD18 you can move between 1.83 (stock) and 1.93 without issue, maybe just stay at 1.86 for now unless 1.93 does anything good
Phase Control on VCore was behaving awkward in CTR and Hydra ~ disabled feels fine
Overcurrent protection is not needed, overvoltage doesn't seem to trigger bellow 1.55, soo it's fine to be on
Switching frequency i kept low as by recommendations, because efficiency suffers on these at 600khz strongly
Positive offset is there to stabilize broken V/F and to match VID with V-TEL on allcore loads. On normal low ampere, it overshoots slightly but 10mV have never killed a CPU. FIT doesn't detect offsets, just there to keep stability up & voltage match , with droopy loadline


----------



## domdtxdissar

Veii said:


> Maybe, if time stays
> It is projected to be on a B550 Creator
> Actually this should be guaranteed I225-V Rev.03 not 02
> If this board doesn't reach 60c , then the ITX can easily run it
> 
> Wonder if it is fair, as ASUS's CBS on this board is fully unlocked ~ but memory training feels more trustworthy on the ITX now
> 
> Have only 1 week to build & bench , but I'll give my best
> On this build i can't bench the 3070ti much. Just an e-sport warzone build where RAM timings and CPU Freq matters
> 
> Where these 2x8 or 2x16 ?
> The showcase build will be interesting for you (next month),
> Trying to get an EVGA X570 DARK and some 6900XTXH (not for me sadly) 😅


You can try a few SotTR runs, or other game benches 








(we are looking at CPU game fps numbers which are not affected by GPU)

settings








Aida benches are not so interesting as aida only measure the performance in aida itself with little correlation to "real world"










VPII said:


> I am going to ask maybe a stupid question. I've been running Aida64 Cache & Memory benchmark a number of times without an issue while still on Windows 10, but recently when I run the benchmark it would reach the memory Memory Copy and the system would restart shortly there after, so I cannot run it to see where my latency is at. Running Maxxmem2 works fine. I even ran Karhu Memtest till 20 000% without an issue as per the attached picture. What would cause Aida64 Cache and Memory benchmark to fail like this?
> 
> View attachment 2529319


Too high boosting on cores on second CCD.
If your running PBO CO, reduce CO undervolt on cores 8-16

ps, you can double-click the latency tab alone to only run the latency test


----------



## mongoled

VPII said:


> I am going to ask maybe a stupid question. I've been running Aida64 Cache & Memory benchmark a number of times without an issue while still on Windows 10, but recently when I run the benchmark it would reach the memory Memory Copy and the system would restart shortly there after, so I cannot run it to see where my latency is at. Running Maxxmem2 works fine. I even ran Karhu Memtest till 20 000% without an issue as per the attached picture. What would cause Aida64 Cache and Memory benchmark to fail like this?
> 
> View attachment 2529319


Can you try Y-Cruncher

If u are using CO, then have a look at relaxing the values


----------



## VPII

mongoled said:


> Can you try Y-Cruncher
> 
> If u are using CO, then have a look at relaxing the values


Thank you I even tried it without any PBO set, as in disabled but will try it again now just to be sure.


----------



## PJVol

XPEHOPE3 said:


> Asserted as in HWiNFO? I never saw it either.


Asserted as when it is confirmed that something is true 
Related to CPU this assertion is true when PROCHOT_L pin is low, which means CPU is under the HTC (Hardware thermal control), where the CPU freq. is limited by some predefined low-power P-state, DF goes to lowest P-state and DRAM is throttled.
One of the condition upon which it enters HTC-active state is Tctl ≥ HTC temp limit ( = 90°C on 5600X by default, assuming that this is what HWInfo reports in main window under the operating points)
and exit therefrom upon PROCHOT_L deassertion and Tctl < HTC limit - HTC hysteresis.
Tbh, I have little idea, how it might happen if an adequate cooling is used.


XPEHOPE3 said:


> But core frequency is limited anyway by one of the PMT limiters,


Which ones? Not sure I understand what are they )


----------



## Luggage

XPEHOPE3 said:


> Refer to this post:
> 
> For 1.44 you should consider 150ns not 140ns.
> Let f = frequency, d = DRAM density
> tRFC ticks = (((tRFC ns * f / 2000) + d - 1) div d) * d + d
> for you: ((150*3800/2000 + 8 - 1) div 8) * 8 + 8 = ((285 + 7) div 8) * 8 + 8 = 36 * 8 + 8 = 296
> If you insist on 140 ns then:
> ((140*3800/2000 + 8 - 1) div 8) * 8 + 8 = ((266+7) div 8) * 8 + 8 = 34 * 8 + 8 = 280
> 
> 
> No. On screenshot you only see minimums but not the timestamps when they occured. It could have been that those minimums appeared at different times. I suggest you enable logging in HWiNFO and then check the log if at some *single time point* all core clocks become 0.
> On a side note, if your PC survives SUCH clocks it can only be readout bug I think. Overvolting to get those clocks probably would kill your CPU already.


Of course since I've been trying to catch it I have not gotten a single spectacular OB, especially not while logging. And I cant figure out what settings I've changed, or if they just stick now U_U
But I have managed to observe the "zeroing" of all core clocks and all core voltages - if all VID_min and all Core Clock_min and all Core Effective_min are zeroed... it only happens all at once.
Normal operation I can observe over time that Core Effective eventually sleep - except core 0, it never sleeps (because of HWinfo?). and Core Clock and VID never zero.



http://imgur.com/a/7G1inDP


----------



## XPEHOPE3

PJVol said:


> which means CPU is under the HTC (Hardware thermal control), where the CPU freq. is limited by some predefined low-power P-state, DF goes to lowest P-state and DRAM is throttled.
> One of the condition upon which it enters HTC-active state is Tctl ≥ HTC temp limit = 90°C ( on 5600X by default, presumably what it is reported in main HWInfo window under the operating points)


I think it's called THM limit, not procHOT limit.


PJVol said:


> Which ones?


These are my current findings. I assume all limit labels need to be shifted forward by 1 (ppt->tdc, tdc->thm, etc), so the temp limiter is "VOLTAGE_FREQUENCY"


> "PPT_FREQUENCY", // always = CCLK_LIMIT
> "TDC_FREQUENCY", // check by lowering PPT!!
> "THM_FREQUENCY", // reacts to TDC on some y-cr
> "PROCHOT_FREQUENCY", // always ok, since THM never reached
> "VOLTAGE_FREQUENCY", // always reacts, proportionate to temps
> "CCA_FREQUENCY", // always ok?? voltage
> "FIT_VOLTAGE", // probably L3 FIT + CCA_CAC need both to be high
> "FIT_PRE_VOLTAGE", // reacts on VST for PEAK_VOLTAGE near VID LIMIT, but not on FFT 1.45 vs 1.4493


BTW, *anyone knows what is CCA and CAC in AMD?*



Luggage said:


> But I have managed to observe the "zeroing" of all core clocks and all core voltages - if all VID_min and all Core Clock_min and all Core Effective_min are zeroed... it only happens all at once.


Cool, exactly like I saw.
If you are interested, in Excel one can make row names stick at the top even when you scroll the table down:

Scroll so that the first row seen is the one with table headers
View->Freeze panes->something about the first row



Luggage said:


> Of course since I've been trying to catch it I have not gotten a single spectacular OB


Probably by running HWiNFO+ZenTimings (with monitoring with as low auto refresh as possible)+CB23-multi.


----------



## Luggage

XPEHOPE3 said:


> I think it's called THM limit, not procHOT limit.
> 
> These are my current findings. I assume all limit labels need to be shifted forward by 1 (ppt->tdc, tdc->thm, etc), so the temp limiter is "VOLTAGE_FREQUENCY"
> 
> BTW, *anyone knows what is CCA and CAC in AMD?*
> 
> 
> Cool, exactly like I saw.
> If you are interested, in Excel one can make row names stick at the top even when you scroll the table down:
> 
> Scroll so that the first row seen is the one with table headers
> View->Freeze panes->something about the first row
> 
> Probably by running HWiNFO+ZenTimings (with monitoring with as low auto refresh as possible)+CB23-multi.


Multi? That’s not going to sleep any cores…


----------



## XPEHOPE3

Luggage said:


> Multi? That’s not going to sleep any cores…


Exactly. But in my case it produces both zero readings and overboosts if another PMT reading tool is running (didn't try ZenTimings though)


----------



## PJVol

XPEHOPE3 said:


> I think it's called THM limit, not procHOT limit.


THM limit is what you set in PBO menu. I was talking about HTC temperature limit, if that is what you mean under procHOT limit.
(which is presumably accessable by device 18 function 3 address 0x64, register bits 22-16)
I think I confused what HWInfo reported as "High Temperature Limit" and a HTC limit, shown as 115°C.


XPEHOPE3 said:


> I assume all limit labels need to be shifted forward by 1


You mean these?











XPEHOPE3 said:


> what is CCA and CAC











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Windows 11 as well? Hope the AMD chipset drivers tomorrow fix the read/write/copy. Nah, bloated windows 10.




www.overclock.net




Цацки )

Don't know what CCA is, but CCM stands for Cache Coherent Master


----------



## umea

Actually now that I'm trying SR. How many of you with 5950x/5900x have stabilized DR 32gb above 1900fclk? (looking at 2000+)


----------



## Luggage

XPEHOPE3 said:


> Exactly. But in my case it produces both zero readings and overboosts if another PMT reading tool is running (didn't try ZenTimings though)


CB r23 R23 - BINGO! 



http://imgur.com/a/qhEo1ze


----------



## ManniX-ITA

Luggage said:


> Of course since I've been trying to catch it I have not gotten a single spectacular OB, especially not while logging. And I cant figure out what settings I've changed, or if they just stick now U_U
> But I have managed to observe the "zeroing" of all core clocks and all core voltages - if all VID_min and all Core Clock_min and all Core Effective_min are zeroed... it only happens all at once.
> Normal operation I can observe over time that Core Effective eventually sleep - except core 0, it never sleeps (because of HWinfo?). and Core Clock and VID never zero.


How fast did you set the pooling rate?
Seems to me it's just the snapshot table is corrupted by the previous request.
Core 0 never sleep cause it's handling the legacy interrupts and some other stuff that can only run on it.


----------



## Luggage

ManniX-ITA said:


> How fast did you set the pooling rate?
> Seems to me it's just the snapshot table is corrupted by the previous request.
> Core 0 never sleep cause it's handling the legacy interrupts and some other stuff that can only run on it.


200ms


----------



## ManniX-ITA

Luggage said:


> 200ms


Then it's normal, the pure SMU command takes around 100-150ms, plus HWInfo reading the data.
Below 300 is prone to fail.


----------



## Luggage

I'll try 333ms next 
Because this one just invalidated the earlier theories?



http://imgur.com/a/dqxhOjD


----------



## ManniX-ITA

Luggage said:


> Because this one just invalidated the earlier theories?


Sorry I'm late to the party 
May I ask what are the earlier theories?


----------



## Luggage

ManniX-ITA said:


> Sorry I'm late to the party
> May I ask what are the earlier theories?


It’s goes back to [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
OB bugg or readout bug.


----------



## umea

umea said:


> Actually now that I'm trying SR. How many of you with 5950x/5900x have stabilized DR 32gb above 1900fclk? (looking at 2000+)


Question irrelevant sort of now.
Thought maybe 16gb vs 32gb would change how stabilizing higher FCLKs would function, doesn't seem so. Tested for about an hour now and am met with immediate restarts at anything above the step above 1900 fclk (which the step above provides whea errors).
Sucks. Seems it is just my CPU.

On the upside, I did stabilize 3800 14 flat 1T pure, basically a piece of cake on 16gb SR regardless of CPU it seems. Seems maybe it's a mix of my sticks and also cpu.

To those of you who do it, what is your methodology for binning CPUs and RAM sticks?


----------



## Thanh Nguyen

With 1.6v-1.7v, what is the max stable setting you can push the ram?


----------



## umea

Thanh Nguyen said:


> With 1.6v-1.7v, what is the max stable setting you can push the ram?


Depends on what frequency you're at. Give the spreadsheet a look and sort the VDIMM from highest to lowest to find ones in the range you're looking for Zen RamOC Leaderboards


----------



## XPEHOPE3

ManniX-ITA said:


> Sorry I'm late to the party
> May I ask what are the earlier theories?


My original post (the one Luggage linked was after that)



PJVol said:


> You mean these?


No, these are fine. I mean as named in quote, starting from PPT_FREQUENCY (offsets 30-37 in dec)



Luggage said:


> 200ms


In ZenTimings or HWiNFO?
I set 1000ms in HWiNFO and 50ms in my monitoring tool.



ManniX-ITA said:


> Then it's normal, the pure SMU command takes around 100-150ms, plus HWInfo reading the data.
> Below 300 is prone to fail.


Doesn't seem like it if HWiNFO (or my tool) runs alone at 50ms on my PC. The problem starts when they try to read together. I think it's because either "the faster updating wins" or because HWiNFO doesn't use PCI mutex.


----------



## Dodgexander

Taraquin said:


> Good. WR should be double of RTP, try either 10/5 or 16/8, maybe 12/6? Some get better results with scls at 4, but maybe 2 is best for you?


Wow, thank you so much man! I wasn't following that rule so I couldn't get stable lowering tWR on its own. I did as you said and dropped tWR to 10 while keeping tRTP at 5 and it booted.
Shaved my latency down from 55 to 52.8: I tried SCLs at 4 but that gave worse results than 2. So I reverted back to 2.
















I'm about half-way in the DDR4 sheet now, which I'm more than happy with . Looking at some better results than me I notice tighter tRCDRD/WR, tRP and tCWL.
I tried lowering these before I adjusted tWR (from your advice) but they just won't go lower. Is there something I'm missing or could running lower tWR now make these stable tighter?
Running SCLs at 4 instead of 2, its possible to run other secondary or primaries tighter?
I tried lowering vDIMM too, but I think tRFC is stopping me from running lower than 1.55v.


----------



## Tebore

Hoping to get some help here.
I have a kit of 32GB (2x16GB) Crucial Ballistix Kit that uses 8Gb Rev B chips in dual rank. Stock speed is PC2400 (16,16,16,39) @1.2V
I currently have it rock solid stable in all tests (P95, OCCT, y-cruncher), running 3433Mhz timings below








It's 34x101 and Zentimings isn't detecting the 101bclk so it thinks it's 34x100.
The board is a Gigabyte AB350M-D3H.

Any tips on pushing these to 3600mhz? I'm not sure if it's the RAM, SOC or a bug in the board but at these settings I can't set anything higher than 1.42V VDIMM. I previously had it running 1.45v @3200 (16,18,18,36) with a 1500x.

If I'm stuck here any tips on what timings to tune next? As you can see above some of the timings are already tuned to the best of my knowledge based on multiple guides online.


----------



## ioannis91

Hello guys! Is there anything else i can try or I am pretty much tight as it goes? Maybe tRCDWR 8? I tried tRFC 272 but it timed out with 1.45v and I was at 45C so i don't want to push voltage any higher. 
Also it would be nice if we had a guide saying about what the vddg voltages, RRTs, Drive Strength and Setup times do exactly and how should we use them. Yes, there are some guides on reddit here and there but they are kinda vague..


----------



## Taraquin

Veii said:


> Soon™
> This week has potentially a 5900X build ongoing, but parts likely won't arrive till Friday/Monday
> Ram maybe can arrive on Wednesday.
> 
> What should i bench it on, 3800 or just max out 4200/4267 again ?
> Any wishes ?
> Maybe just 1T pure any Freq ?
> 
> Stock but without powerlimits
> Else L3 cache will throttle up to SOC load and so it will not be comparable.
> Other was my daily CO +200 @ 94c thermal limit (it will throttle at 65c prochot, but just so another throttle sensor is not triggered)
> 
> Most interesting is the tiny "non existent" frequency scaling on Aida64 - when you load all cores
> On single core affinity focused, i can see latency dropping further and potentially breaking the algorithm ~ but that's unlikely the goal here
> 
> Idk about safemode, never got good results on it
> It always loaded more services, than my normal installation & didn't support CPPC nor C-States correctly (well it didnt at all)
> All results on it where worse than on the normal windows ~ for me
> 
> Thank you
> Yes i need to start updating some stuff & probably fix couple of things for non 8gb user. Although it remans witchery for everyone.
> 
> Also need to update the errors really
> Today was stuck on #5 , a spam of 3 in the first cycle
> It ended up being a combination of "too high SD & DDs" with "too high tRRD_"
> That was fixed ~ didn't know "too high tRRD_" can cause issues too
> 
> Heat is an issue, but it wasn't for me
> RTTs change how VDIMM + cLDO_VDDP +? /? procODT ~ behave
> 
> Here i needed 1.53vDIMM, else on 005 i needed 1.46vDIMM
> Yet this 1.46v where hotter in general
> 
> RTTs do change things
> But it's a bit too much trial and error to get data-eye looking clean.
> We technically can export memory training and data-eye logs , but practically i still have no idea where in ABL which partition and location ~ these readouts get exported.
> 
> A bit unfamiliar with Monolithic CPUs to help you, but what does control the fabric
> Is it really SOC only ?
> Wouldn't VDD18 push instead of SOC rather help ?
> You have playroom till 1.3v SOC, but this still cuts soo deeply into the powerbudget ~ there has to be other options too
> How is prochot on this unit
> Also little requoted leak:
> 
> 
> 
> 
> 
> 
> 
> 
> No IMC FW change. I think Zen3D will not have any advantages in MCLK OC. But we can hope WHEA #19 sensoric issues got resolved finally


With my current agesa it seems my MB won't let my CPU use more than 84W so I guess 550GB/s and 10.6ns is best. It's weird that a allcore oc can up these limits. Vrm max temp at 84W load is 67C so I wonder why it's limited. Hopefully a newer agesa/bios can fix this.


----------



## Blameless

umea said:


> To those of you who do it, what is your methodology for binning CPUs and RAM sticks?


Haven't done a ton of DDR4 binning...effort/reward ratio is low, especially now that DDR4 is fully mature and all the DRAM integrators are competitively binning stuff themselves. I could go out and buy twenty OEM B-die DIMMs and maybe get the same result as a top bin from one of the big brands...for ten times the cost. While I would happily pay a few bucks extra to _not_ get garish heatspreaders on my memory, I'm not willing to spend that much.

Anyway, my methodology does something like this:

One DIMM at a time in a known good board, throw in some sensible baseline settings, fire up Memtest86 test #8 (fast, not too stressful, but sensitive enough for this purpose), tune down vDIMM until there are just enough errors to get a good sample, adjust non-performance stability influencing parameters to find which ones reduce error rate the most, then increase speed/tighten performance related timings, rinse and repeat. Once I find what is optimal for one DIMM of that type, I test others against those settings, and exclude everything that doesn't match it. Then by process of elimination I tighten stuff up further, exclude more DIMMs, until I have the best 'kit' of however many DIMMs I'm going to use. Some times there are samples that do better with more voltage, or just need certain timings loosened to shine, but in general, if it's the highest frequency, tightest timings, at the lowest voltage, it will prove to be the best of the bunch.

CPUs are mostly the same thing. Take a known good board and known good memory and see if the CPU can do what your last sample did, and if it can, see if it can do better, and if it can then test future CPUs against that new baseline.

At this point, I mostly bin older memory, where it's affordable for me to buy craptons of it to play with. Been having some fun with about fifty OEM Hynix DDR3 BFR DIMMs I bought last year when a pile of pulls showed up on eBay for 8-10 dollars a stick, but that's a topic for another thread.


----------



## VPII

mongoled said:


> Can you try Y-Cruncher
> 
> If u are using CO, then have a look at relaxing the values


Okay I got it to complete by setting bios to optimized defaults with memory set DOCP meaning 3200 cl14. Ill try it again with optimized defaults but memory set to 3800 cl16 as it does work for everything else. It may have been my negative vcore offset with advance pbo that caused it but Ill play around with the vcurve optimizer as -25 all cores might be an issue.

Sent from my Hisense Infinity H40 Lite using Tapatalk


----------



## Taraquin

Dodgexander said:


> Wow, thank you so much man! I wasn't following that rule so I couldn't get stable lowering tWR on its own. I did as you said and dropped tWR to 10 while keeping tRTP at 5 and it booted.
> Shaved my latency down from 55 to 52.8: I tried SCLs at 4 but that gave worse results than 2. So I reverted back to 2.
> View attachment 2529364
> 
> View attachment 2529365
> 
> I'm about half-way in the DDR4 sheet now, which I'm more than happy with . Looking at some better results than me I notice tighter tRCDRD/WR, tRP and tCWL.
> I tried lowering these before I adjusted tWR (from your advice) but they just won't go lower. Is there something I'm missing or could running lower tWR now make these stable tighter?
> Running SCLs at 4 instead of 2, its possible to run other secondary or primaries tighter?
> I tried lowering vDIMM too, but I think tRFC is stopping me from running lower than 1.55v.


Good results, I think you are close to the limit at your binning/voltage  Is tRCDRD and tRP 14 impossible at 1.55V? For me, setting tRC a bit higher allowed me to run tRCDRD and tRP lower. Suggestion: try 14-14-14-28-42 and see if that works? If that works you might be able to run tRDWR at 7. Scl's is a bit weird, they seem to run better in even numbers like WR and CWL, some get better perf at 2 others at 4.


----------



## mongoled

ioannis91 said:


> View attachment 2529377
> 
> Hello guys! Is there anything else i can try or I am pretty much tight as it goes? Maybe tRCDWR 8? I tried tRFC 272 but it timed out with 1.45v and I was at 45C so i don't want to push voltage any higher.
> Also it would be nice if we had a guide saying about what the vddg voltages, RRTs, Drive Strength and Setup times do exactly and how should we use them. Yes, there are some guides on reddit here and there but they are kinda vague..


With the new info Anta777 has brought to this thread im yet to experiment with those values so I will go on what I know fron prior info.

For 2 x 8GB you want your SCLs to be both set to 2 not 4, 4 is for 2 x dual rank or 4 x single rank.

One of the main reasons there are no "real guides" for the stuff you asked about as is because the relationships between those values are not black and white, they are specific to your combination of motherboard/ram/cpu and need experimentation.

To understand you need to find some of Veii post with regards to these and then do your own experiments to see.

Here is one such post









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Messages telling me to try lowering VDIMM at the same time as increasing RttNom, but then it appears increasing VDIMM might help :unsure: o_O The opposite :D NOM is CKE high NOM needs to increase if VDIMM increases or generally signal strength increases I can see (theory) that stronger tCKE...




www.overclock.net


----------



## Blameless

Dodgexander said:


> Running SCLs at 4 instead of 2, its possible to run other secondary or primaries tighter?


Usually, but if you're actually seeing scaling with the tighter SLCs, trading them for other timings probably won't improve final performance.


----------



## mongoled

umea said:


> Depends on what frequency you're at. Give the spreadsheet a look and sort the VDIMM from highest to lowest to find ones in the range you're looking for Zen RamOC Leaderboards


Think I should hit that some time soon

😀

On a side note, I grabbed another 4 x 8GB Viper Steel 4400 mhz dimms from Amazon.de and both pairs are candidates for 3800 flat 14s



Looks like I may have a pair to sell soon

🤣 🤣


----------



## Taraquin

Blameless said:


> Haven't done a ton of DDR4 binning...effort/reward ratio is low, especially now that DDR4 is fully mature and all the DRAM integrators are competitively binning stuff themselves. I could go out and buy twenty OEM B-die DIMMs and maybe get the same result as a top bin from one of the big brands...for ten times the cost. While I would happily pay a few bucks extra to _not_ get garish heatspreaders on my memory, I'm not willing to spend that much.
> 
> Anyway, my methodology does something like this:
> 
> One DIMM at a time in a known good board, throw in some sensible baseline settings, fire up Memtest86 test #8 (fast, not too stressful, but sensitive enough for this purpose), tune down vDIMM until there are just enough errors to get a good sample, adjust non-performance stability influencing parameters to find which ones reduce error rate the most, then increase speed/tighten performance related timings, rinse and repeat. Once I find what is optimal for one DIMM of that type, I test others against those settings, and exclude everything that doesn't match it. Then by process of elimination I tighten stuff up further, exclude more DIMMs, until I have the best 'kit' of however many DIMMs I'm going to use. Some times there are samples that do better with more voltage, or just need certain timings loosened to shine, but in general, if it's the highest frequency, tightest timings, at the lowest voltage, it will prove to be the best of the bunch.
> 
> CPUs are mostly the same thing. Take a known good board and known good memory and see if the CPU can do what your last sample did, and if it can, see if it can do better, and if it can then test future CPUs against that new baseline.
> 
> At this point, I mostly bin older memory, where it's affordable for me to buy craptons of it to play with. Been having some fun with about fifty OEM Hynix DDR3 BFR DIMMs I bought last year when a pile of pulls showed up on eBay for 8-10 dollars a stick, but that's a topic for another thread.


It seems like byuing prebinned ram is best, you could be lucky byuing 20 kits of 4000cl17 and find 2 that runs 4000cl15 at 1.5V, or you could just buy 4000cl15 and run 3800cl13-14-14 at 1.55V. Question is if they extra price is worth the gains. My kit is a poor bin, but I paid 150usd for my 4400cl19 vipers and it can do 4000cl16 1T at 1.45V. If I spend 100usd more I could have bought 4000cl15 and probably run 4000cl15 flat at 1.5V. This would have gained me 1ns in aida and 500MB R/C and maybe 4 fps in SOTTR. Worth it in my opinion? No  

If ramtuning is your thing buy a B550/X570 ITX like Veii with 2 dimms and a 5600X or 5800X that can do 4200 whea free and a 4000cl15 kit. Then you get sub 50ns in aida and a few percent extra perf vs the regular 4 dimm B550 Tomahawk which naxes out at 3800


----------



## Blameless

Taraquin said:


> If ramtuning is your thing buy a B550/X570 ITX like Veii with 2 dimms and a 5600X or 5800X that can do 4200 whea free and a 4000cl15 kit.


I've got an ASRock B550 Phantom Gaming ITX/ax and I used to have a Crosshair VIII Impact. The Impact in particular was an amazing memory OCer, and stuff I was able to get 24/7 stable on that board won't even POST in half of my full-size boards; was my first AM4 board and it spoiled me pretty badly. Unfortunately, ASUS' early firmware had some major issues and the board bricked itself, repeatedly, and eventually for goo.

What I'm most lacking are CPU samples that will reliably do past 1900FCLK without errors.


----------



## Dodgexander

Taraquin said:


> It seems like byuing prebinned ram is best, you could be lucky byuing 20 kits of 4000cl17 and find 2 that runs 4000cl15 at 1.5V, or you could just buy 4000cl15 and run 3800cl13-14-14 at 1.55V. Question is if they extra price is worth the gains. My kit is a poor bin, but I paid 150usd for my 4400cl19 vipers and it can do 4000cl16 1T at 1.45V. If I spend 100usd more I could have bought 4000cl15 and probably run 4000cl15 flat at 1.5V. This would have gained me 1ns in aida and 500MB R/C and maybe 4 fps in SOTTR. Worth it in my opinion? No
> 
> If ramtuning is your thing buy a B550/X570 ITX like Veii with 2 dimms and a 5600X or 5800X that can do 4200 whea free and a 4000cl15 kit. Then you get sub 50ns in aida and a few percent extra perf vs the regular 4 dimm B550 Tomahawk which naxes out at 3800


Or just buy an itx with an apu and win.


----------



## Taraquin

Blameless said:


> I've got an ASRock B550 Phantom Gaming ITX/ax and I used to have a Crosshair VIII Impact. The Impact in particular was an amazing memory OCer, and stuff I was able to get 24/7 stable on that board won't even POST in half of my full-size boards; was my first AM4 board and it spoiled me pretty badly. Unfortunately, ASUS' early firmware had some major issues and the board bricked itself, repeatedly, and eventually for goo.
> 
> What I'm most lacking are CPU samples that will reliably do past 1900FCLK without errors.


Seems like it's much easier on 5600X or 5800X, vs dual ccds. Problem is that the higher required iod abd soc voltage eats into the pwr budget and causes lower clockspeeds. At 3800 my iod die uses around 19W max, at 4000 it uses 21W max, this from raising iod and soc by 40mv each. I can run 4066 and 4133, but I have to increase soc by 40mv for each 66MHz up and clockspeed drops slightly. Veii at 4200 uses about 30W at 130mv soc and 100mv iod above me if I remember currectly. He also has higher ccd and vddp. The small 2W change makes my CPU run 25-50MHz slower, and makes yields lower, SOTTR run identical at 3800cl5 and 4000cl16, aida and dram calc is slightly better at 4000 though. You could always up pwrlimut if you can, but it depends on your cooler, noise tolerance etc.


----------



## Taraquin

Dodgexander said:


> Or just buy an itx with an apu and win.


Yeah, too bad even an 5700G with 4533cl16 barely matches the gamingperformance of a 5600X with 3800cl14  But hey, they win in aida for what it's worth


----------



## Audioboxer

While 1.44v passed based on what Anta777 said about 1.45v is roughly what is expected for 140ns, I decided what's +0.01v VDIMM going to hurt when watercooled  Final profile I guess.










In true "it makes no sense what tPHYRDL is up to" fashion, 2T at tCL14 is 26/26. I guess I'll wait till AMD/MS fix memory issues on Windows 11 and bench what is better, being at 1T, or going 2T at tCL14 for 26/26. From some historic testing it seems to be the case 1T/56 at 28/28 will still edge out 2T at 26/26.

My next project will be trying to bruteforce tRCDRD 13 at 3800 for at least 3 cycles. Preliminary findings seem to be ClkDrvStr 60 can help clear early 6's, possibly suggesting it's the IMC struggling with the data rate of tRCDRD 13 at 3800. Higher VDIMM seems to help a bit, even though I'm running tCL13 at 1.55v and tRCDRD doesn't necessarily scale well with voltage. It seems to have a hard cap somewhere where it will even begin to try and run. 1.57~1.58v+ for example looks like it will help things a little over 1.55v.

Hopefully Veii getting some DR sticks can help all us DR folks out a bit 🤝 Though I'm beginning to really learn your IMC could ultimately be what holds your memory back.


----------



## XPEHOPE3

Blameless said:


> At this point, I mostly bin older memory, where it's affordable for me to buy craptons of it to play with. Been having some fun with about fifty OEM Hynix DDR3 BFR DIMMs I bought last year when a pile of pulls showed up on eBay for 8-10 dollars a stick, but that's a topic for another thread.


OT: I wish I had as much spare time as you do


----------



## mongoled

So here is the first attempt with four good dimms, basically its my 3 "old" dimms and one dimm from the other two sets I bought.

Baseline ready, I used the tick method for tRFC.

15-14-14-14-28-38-224-1T-56-0-0

Now to move into tCL 13


----------



## Audioboxer

mongoled said:


> So here is the first attempt with four good dimms, basically its my 3 "old" dimms and one dimm from the other two sets I bought.
> 
> Baseline ready, I used the tick method for tRFC.
> 
> 15-14-14-14-28-38-224-1T-56-0-0
> 
> Now to move into tCL 13
> 
> 
> 
> View attachment 2529383


Does running CCD over 1v help with the memory stability at 3800? Really nice timings for 4x8.

I'm currently trying to work with tRCDRD 13 in a similar way, as in I'm running 14-13-13-13 lol. Trying to bruteforce it without worrying if tCL13 is adding extra strain.


----------



## mongoled

Audioboxer said:


> Does running CCD over 1v help with the memory stability at 3800? Really nice timings for 4x8.
> 
> I'm currently trying to work with tRCDRD 13 in a similar way, as in I'm running 14-13-13-13 lol. Trying to bruteforce it without worrying if tCL13 is adding extra strain.


No, I wouldnt think so, I just found a nice spot for IOD at 1.060 @3800 and used the 40mv offset rule between CCD/IOD etc.

Its not something ive looked into for a long time

Not yet tried tRCDRD @13, want to get a result in the DRAM overclocking table with 4x8GB, with tCL to 13 from 15 latency is 51ns, just need to get a stable TM5


----------



## Audioboxer

mongoled said:


> No, I wouldnt think so, I just found a nice spot for IOD at 1.060 @3800 and used the 40mv offset rule between CCD/IOD etc.


Ah right, makes sense. Wonder if I should pay more attention to that "rule" lol. I haven't budged CCD off 0.975v since... forever.


----------



## mongoled

Audioboxer said:


> Ah right, makes sense. Wonder if I should pay more attention to that "rule" lol. I haven't budged CCD off 0.975v since... forever.


snap

😂 😂

13-14-14-14-28-42-224-1T-56-0-0 completed

Can someone point out to me what the "new" suggestions made by anta777 can be applied to the profile below ?

Will continue with this tomorrow, still under air cooling as im yet to decide which dimms to devourer


----------



## PJVol

Taraquin said:


> Yeah, too bad even an 5700G with 4533cl16 barely matches the gamingperformance of a 5600X with 3800cl14


Imagine, if they slap 32mb of L3 from above, call it 5700H and voila.
It'd 100% worth its money )


----------



## Luggage

PJVol said:


> Imagine, if they slap 32mb of L3 from above, call it 5700H and voila.
> It'd 100% worth its money )


3D cache


----------



## umea

Thanks for the ideas everyone. I have an idea for how to bin already prebinned kits. What I meant was buying top bins (i.e. 4000c14) and further binning through testing. Like previously mentioned some of the top bin kits (4000c14) some sticks will have good voltage yield vs tRCDRD, so I'm curious how consistent g.skills binning for it is.

Seems the CPU is much more important binning wise though when it comes to really pushing. Like how I mentioned my 5900x cannot run anything above 1900 without whea errors and cannot handle trcdrd 14 almost at all. 5900x seems to be the worst for RAM OC though as its basically a failed 5950x and unlike the 5800x it has too many cores/threads I guess for the IMC to handle certain things.

I was wrong about my 16gb 14 flat profile being stable so time to mess with it again. At the very least, I'm not met with immediate errors of every kind no matter what like I was with my DR sticks.

Also @Veii my board is Rev 2. Microcode Update (is this BIOS version?) A20F10/A201009


----------



## VPII

Okay @mongoled I ended up to test everything and my timings worked with the 3200 speed memory then I tired 3600 CL16 and all good then 3800 cl16 and all good. Then Instarted with advance PBO setting the vcurve optimizer to -10 all core and it worked, I tried -20 and it failed again but -15 all core worked no problems.
However the L3 cache latency is still pretty bad in Win11


----------



## ManniX-ITA

XPEHOPE3 said:


> Doesn't seem like it if HWiNFO (or my tool) runs alone at 50ms on my PC.


Full dump on the 3800x takes 100-150ms.
If you pool earlier either will fail or the SMU will get unstable.
Could be the 5000 is faster, I didn't really check.
Sadly there's no real global mutex, if you issue commands in parallel to the SMU it will get unstable and do crazy stuff.
You can use a mutex to avoid your program issuing commands in parallel but otherwise there's no mean to know, that I know of, if it's busy or not.
Also it's highly recommended to leave 25-50ms idle between each command otherwise again it gets unstable.


----------



## MrHoof

Found this video randomly while searching about data eye information. Found it rather intresting even tho I only understood like half of it. Explained some stuff decently well but beware of very slow speech .
Ensuring DDR4 Electrical Performance at Intended Data-Rate - YouTube


----------



## Taraquin

PJVol said:


> Imagine, if they slap 32mb of L3 from above, call it 5700H and voila.
> It'd 100% worth its money )


Yeah, then it would be the performance king by far, but yields would probably be terrible since the chip would be quite a bit larger vs 5700G due to the extra cache taking up space.


----------



## umea

I'm personally pretty excited for next gen APUs, rdna2 apus should be ridiculous


----------



## PJVol

Taraquin said:


> the chip would be quite a bit larger


Considering upcoming zen3+ should still fit AM4 socket, I don't think it would.


umea said:


> pretty excited for next gen APUs,


Can't share your excitement, just cezanne with navi gpu cores instead of vega? Not much for the year old arch, tbh.
What's more exciting is raphael with igpu chiplet (? is it still an APU)


----------



## Luggage

Taraquin said:


> Yeah, then it would be the performance king by far, but yields would probably be terrible since the chip would be quite a bit larger vs 5700G due to the extra cache taking up space.


V-cache 









AMD presents more details on Zen 3 3D V-Cache and the future of 3D stacking


Apparently, AMD was considering implementing Intel's Foveros 3D technology at some point, but later decided to go with TSMC's superior Micro Bump 3D packaging that is 1 micron thinner and quite a bit more efficient. This is only the beginning, as AMD plans to refine the interconnect pitch in the...




www.notebookcheck.net


----------



## Dodgexander

Taraquin said:


> Good results, I think you are close to the limit at your binning/voltage  Is tRCDRD and tRP 14 impossible at 1.55V? For me, setting tRC a bit higher allowed me to run tRCDRD and tRP lower. Suggestion: try 14-14-14-28-42 and see if that works? If that works you might be able to run tRDWR at 7. Scl's is a bit weird, they seem to run better in even numbers like WR and CWL, some get better perf at 2 others at 4.


I tried it (14-14-14-28-42) but benches don't seem any better than my current settings. Also it fails Anta absolut with errors. I think I'm stuck at 14-15-15-21-36. I was hopeful that lowering tWR and tRP would 'unlock' give a new opportunity to tighten other timings, but even with SCLs at 4 I can't get stable.

Is there something else that could bring we stability at 14-14-14-28-42? Maybe drive strength or procODT?

My guess is if I turned gear down on, or went to 2T it may run okay, but I'll just be going round in circles putting one setting up and another down to get similar-ish results I guess.

This isn't really a clean system either, I bet I could bench even better if I disabled background services etc, can't really do that since its not my own PC!


----------



## XPEHOPE3

ManniX-ITA said:


> Full dump on the 3800x takes 100-150ms.
> If you pool earlier either will fail or the SMU will get unstable.
> Could be the 5000 is faster, I didn't really check.
> Sadly there's no real global mutex, if you issue commands in parallel to the SMU it will get unstable and do crazy stuff.
> You can use a mutex to avoid your program issuing commands in parallel but otherwise there's no mean to know, that I know of, if it's busy or not.
> Also it's highly recommended to leave 25-50ms idle between each command otherwise again it gets unstable.


At my 5600x time it takes to issue "transfer PMT to DRAM" SMU command + reading those DRAM values is less than 1ms. At least when there's no load...
And there is this global PCI mutex used by ZenTimings and OpenHardwareMonitor at least. Also I believe 1usmus referred to that very mutex when saying Ryzen Master didn't use "the" mutex to control its own access to PMT.


----------



## VPII

mongoled said:


> Can you try Y-Cruncher
> 
> If u are using CO, then have a look at relaxing the values


@mongoled Interestingly I managed to get memory speed up to 3800 with Aida Cache and Memory benchmark passing but was still on the older Windows 11 build as I did not enable my Windows Insider Program. Unfortunately when I enabled Windows Insider Program and got Windows 11 KB5006746 or Windows 11 build 22000.282 the 3800 memory speed no longer would work and even dropping to 3600 CL16 was a no go. But L3 cache latency dropped from 29 / 30 to 11 but read, write and copy dropped a hell of a lot.


----------



## toljan2884

what can be fixed?


----------



## ManniX-ITA

XPEHOPE3 said:


> At my 5600x time it takes to issue "transfer PMT to DRAM" SMU command + reading those DRAM values is less than 1ms. At least when there's no load...
> And there is this global PCI mutex used by ZenTimings and OpenHardwareMonitor at least. Also I believe 1usmus referred to that very mutex when saying Ryzen Master didn't use "the" mutex to control its own access to PMT.


Thanks, I didn't see it at all!
Wow, 1ms is really fast. Definitely faster than the 3800x.
I remember I had to make a lot of tests to find the right timing.
Cause otherwise pulling it too fast was spitting out randomly gibberish.
And of course lots of unpredictable results from other commands.


----------



## mongoled

VPII said:


> @mongoled Interestingly I managed to get memory speed up to 3800 with Aida Cache and Memory benchmark passing but was still on the older Windows 11 build as I did not enable my Windows Insider Program. Unfortunately when I enabled Windows Insider Program and got Windows 11 KB5006746 or Windows 11 build 22000.282 the 3800 memory speed no longer would work and even dropping to 3600 CL16 was a no go. But L3 cache latency dropped from 29 / 30 to 11 but read, write and copy dropped a hell of a lot.


Glad to see you have made some headway. I have Windows 11 installed on a separate drive but I'm not paying too much attention to it until MS release patches that are shown to fix the outstanding issues with Ryzen CPUs.


----------



## Blameless

Dodgexander said:


> Is there something else that could bring we stability at 14-14-14-28-42? Maybe drive strength or procODT?


Test them.

Make a bootable Memtest86 USB drive, fire up test #8 (only), let it run 4 passes. Reduce vDIMM until it errors at a modest rate (three figures for the whole 4 pass run, which should take about six minutes). Try running three times per setting, warm reboots between each. Adjust ProcODT, run it again. Adjust RTTs, run it again. Whichever combination has the fewest average errors per pass is the one you want to keep.

If, after returning to your usual voltage, it's still not stable, you either need to brute force things with more voltage/cooling, or adjust other parameters. Sometimes Samsung ICs react well to reducing termination voltage below half of vDIMM.



toljan2884 said:


> View attachment 2529436
> 
> what can be fixed?


At first glance tWR is probably too low and tRC should be tRP + tRAS.


----------



## Taraquin

umea said:


> Thanks for the ideas everyone. I have an idea for how to bin already prebinned kits. What I meant was buying top bins (i.e. 4000c14) and further binning through testing. Like previously mentioned some of the top bin kits (4000c14) some sticks will have good voltage yield vs tRCDRD, so I'm curious how consistent g.skills binning for it is.
> 
> Seems the CPU is much more important binning wise though when it comes to really pushing. Like how I mentioned my 5900x cannot run anything above 1900 without whea errors and cannot handle trcdrd 14 almost at all. 5900x seems to be the worst for RAM OC though as its basically a failed 5950x and unlike the 5800x it has too many cores/threads I guess for the IMC to handle certain things.
> 
> I was wrong about my 16gb 14 flat profile being stable so time to mess with it again. At the very least, I'm not met with immediate errors of every kind no matter what like I was with my DR sticks.
> 
> Also @Veii my board is Rev 2. Microcode Update (is this BIOS version?) A20F10/A201009


If high ram speed is important for you, go for 5600X or 5800X, a possible explanation is that 2 ccds requires longer traces/intercommunication which increases risk of errors. You have the right MB as it seems ITX and mATX is less likely to whea above 3800, only 2 dimms might be another reason. If you primarily game the 5800X is often a better choice than 5900X it seems. Very few games benefint much from the extra 4 cores, but the 5800X has a bit lower ramlatency and usually can run ram 200-400MHz faster which often matters more. On avg running stock and same ramspeed 5800X is slightly faster than 5900X in games. If you do productivity then 5900X is much better


----------



## Taraquin

PJVol said:


> Considering upcoming zen3+ should still fit AM4 socket, I don't think it would.
> 
> Can't share your excitement, just cezanne with navi gpu cores instead of vega? Not much for the year old arch, tbh.
> What's more exciting is raphael with igpu chiplet (? is it still an APU)


No, it would still fit AM4 platform, but the single piece of silicon would increase quite a bit in since which leads to lower yields and higher prices.


----------



## Dodgexander

Blameless said:


> Test them.
> 
> Make a bootable Memtest86 USB drive, fire up test #8 (only), let it run 4 passes. Reduce vDIMM until it errors at a modest rate (three figures for the whole 4 pass run, which should take about six minutes). Try running three times per setting, warm reboots between each. Adjust ProcODT, run it again. Adjust RTTs, run it again. Whichever combination has the fewest average errors per pass is the one you want to keep.
> 
> If, after returning to your usual voltage, it's still not stable, you either need to brute force things with more voltage/cooling, or adjust other parameters. Sometimes Samsung ICs react well to reducing termination voltage below half of vDIMM.
> 
> 
> 
> At first glance tWR is probably too low and tRC should be tRP + tRAS.


Thanks. Testing RTT's alone would mean testing 343 combinations.

So at 18 min an adjustment that's about 100h worth of testing.

No pain, no gain I guess. I did try 7/3/3 and got errors later in my test men run so I guess the potential for more stability is there, but you get to the point where you wonder when it's best to quit and spend the time using your system instead of tweaking more!


----------



## Taraquin

Dodgexander said:


> I tried it (14-14-14-28-42) but benches don't seem any better than my current settings. Also it fails Anta absolut with errors. I think I'm stuck at 14-15-15-21-36. I was hopeful that lowering tWR and tRP would 'unlock' give a new opportunity to tighten other timings, but even with SCLs at 4 I can't get stable.
> 
> Is there something else that could bring we stability at 14-14-14-28-42? Maybe drive strength or procODT?
> 
> My guess is if I turned gear down on, or went to 2T it may run okay, but I'll just be going round in circles putting one setting up and another down to get similar-ish results I guess.
> 
> This isn't really a clean system either, I bet I could bench even better if I disabled background services etc, can't really do that since its not my own PC!


I tested a bot yesterday and drvstr has a lot to say. Tried 24 20 24 24, got loads of errors, 30 20 24 24 got a few errors, 40 20 24 24 won't boot, 40 20 30 24 is errorfree. All other settings left unchanged.


----------



## mongoled

Wonder how this is going to end up ?

Juicy


----------



## Veii

Pre-pre Sneak Peaks ~ DR testing







tRRD, tWTR where auto
tREF is 3 (use thaiphoon burner DRAM OC Profile on the far right ~ to find some new timings)

3 Findings, (+1)

This G.Skill set is on B1 PCB. G.Skill probably forgot something on it, but it behaves one to one like an ECC dimm. Everything runs but everything is unstable. Boot takes between 30-90sec , every boot ~ sometimes it needs a 2nd boot and this one will also take minimum 30sec. I got the worst of his bins to mock me, soo likely my findings will not bring B2 PCB people anything. Wait for it to post ~ Triggering MBIST can take 30-120sec to train alone 
2x16GB DIMMS urgently need 2.5vPROM or higher. Not 2.45v, that only works on 2x8GB dimms !
2x16GB dimms require 36.9 procODT to function, doesn't matter if 3600C14-14 or 4267C17-18-18 XMP
Difference between dual Rank and Single rank is just 0.2ns. Nothing to use as an excuse for high latency results 
Working on 2133 FCLK while we're at it
Hitting now 34120 / 34125 out of 34130MB/s Max Bandwidth
Slight throttle but working on it. XMP on this kits perfectly fit the maximum i think i can run on this chip

40-20-30-24 @ 36.9Ohm , 733 on 1.5vXMP feels well
60-20 functions, but is not the best.
It's too early to give more recommendations.
6/3/3 remains functioning, but that is for higher than 1.5v.

Sadly this is B1, a very annoying little sample
I don't think much research will help people - but you should check if you are on B1 or B2
And let it train , in this case enable MBIST on such B1 samples & make a coffee or something. As this post will take 2min 
At least it runs 4200C15-15-15 @ same 1.65v, but i think something doesn't like the strain
FCLK likes it , see's no issues. But CCDs somehow don't

Same week has an unfinished build, soo i can not promise much results within 1 week timeframe
1cycle needs 4:30min minimum

@domdtxdissar for SOTTR, i need a better GPU than this 650 here
Maybe if time remains i'll test the 5900X on it.
Also they removed Denuvo but enforce Online EPYC Games integration. Accepting , then linking the accounts and manually unlinking it
- allows you to play it without EPYC Games games host filtering

EDIT:
tRFC mini is fine for Dual Rank - but there is another potential FW issue with using them vs cloning tRFC 1 on all 3
An AMD FW issue that loses you a lot of bandwidth ~ bug. Still looking into it. Generally it functions and matches JEDEC results, soo no need to worry about 2x16gb DR's , but worry about 2x16gb SR

EDIT2:
"Heatsinks" @ Idle 








& WHEA Sensor function confirmation


----------



## mongoled

Dodgexander said:


> Thanks. Testing RTT's alone would mean testing 343 combinations.
> 
> So at 18 min an adjustment that's about 100h worth of testing.
> 
> No pain, no gain I guess. I did try 7/3/3 and got errors later in my test men run so I guess the potential for more stability is there, but you get to the point where you wonder when it's best to quit and spend the time using your system instead of tweaking more!


Try to skip some steps, no reason to go through every combination and even if you wanted to some wont post needing a CMOS reset


----------



## mongoled

So what gains are we looking at in terms of L1 latency from a standard Windows 10 install with AV disabled to a stripped down Windows 10 install ??

0.5 ns ??

As ive noted there are an increasing number of sub 50ns entries in the DRAM Overclocking database and I am wondering how so many are reducing their latency too such an extent as it does not seem to be coming from frequency/timings when I compare it to my setup ....


----------



## Mach3.2

mongoled said:


> So what gains are we looking at in terms of L1 latency from a standard Windows 10 install with AV disabled to a stripped down Windows 10 install ??
> 
> 0.5 ns ??
> 
> As ive noted there are an increasing number of sub 50ns entries in the DRAM Overclocking database and I am wondering how so many are reducing their latency too such an extent as it does not seem to be coming from frequency/timings when I compare it to my setup ....


Maybe I'm doing something wrong but there's absolutely no difference for my setup, maybe 0.05ns difference between bone stock windows 10 with minimal services running and windows defender turned on, and windows 10 cleaned with sophia script and windows defender disabled. 

IMO since AIDA latency results are heavily influenced by clock speed, there's not much meaning comparing between different setups.

As you've seen in this thread running hydra OC can give you close to 50ns of latency on 3800 flat 14, whereas with just PBO you're probably getting closer to 54ns.


----------



## Audioboxer

Compared to my tCL13 profile just playing around with the voltages/resistances. So above is VSOC and CsOdtDrvStr lowered. Will have a look at CkeDrvStr being lowered and VSOC possibly coming down to 1.09v. Then finally RttPark going weaker. I doubt ClkDrvStr will be happy coming down but I might try 30 as the last change.


----------



## glnn_23

Ran this the other day testing a couple of different 2 x 8Gb sets.


----------



## Audioboxer

glnn_23 said:


> Ran this the other day testing a couple of different 2 x 8Gb sets.
> 
> View attachment 2529461


Welcome to the tCL13 club! Up next I'd try dropping tRFC. I can run 224 fine at 1.55v.


----------



## Veii

Mach3.2 said:


> IMO since AIDA latency results are heavily influenced by clock speed, there's not much meaning comparing between different setups.


Can i disprove the first phrase ?








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


tRFC(approximately), not exactly.




www.overclock.net




The only real difference is between throttling and non throttling peak clock
Higher limits request higher VID, reach higher thermal load, get throttled faster

Decent setups have close to zero difference between stock with open limits and finetuned with open limits
Inter-Core latency doesn't change all too much on the same FCLK just because clocks run higher.
The only way to really cheat the system , is to affinity change your layout and ontop of that run OC_MODE without active throttling (not a thing i will ever do)
(OC_MODE still will be package throttled but not clock speed throttled ~ FIT remains active / Especially important for XOC guys, identical to how 6900XTXH now behave)

And also there is the same margin of error (too small but still existing 0.2ns) difference between single 2x8 and dual rank 2x16 at the same speed and same timings
The only difference here between dual rank and single rank guys, is the strain to the CCDs.
This remains a virtual silicon lottery value. Which VDDG voltage values each sample needs. Nothing we should cry about.
Else no ~ everyone can reach the same value as to everyone else. But i can see it makes sense to split 1 CCD vs Dual CCD results.
Bugged samples like mine draw from bad sides the worse cards. 2nd CCD who eats power, yet extremely restricted 6 core by AMD & not even stable at stock.

Ignoring all this WHEA mess, everyone else should have a far better & easier time ~ than me 
EDIT:
Clock speed potentially increases Bandwidth of the set, but does barely to non increase Random Access MemLatency
That's a fabric and intercore part.
L3 part and remain cache part yes ~ but not on mem latency. It really isn't behaving that way
A non throttling system on stock and a non throttling on maxed clock - will have the same mem-latency , with a tiny difference maybe. But it falls under margin of error

EDIT2:







While MemLatency only pegs the first core - it will keep the rest sleeping
Read, Copy , Write peg all cores starting from the last
1,2,3,4,5,6 cores
twice , then it decides the result
But Write especially will show throttling if FCLK is unstable
The other two not so much - yet they all peak allcore load, but step by step - for me it's 12 measurements. For dual CCD units this can take 2-3 min to finish
But yet this first core doesn't do anything
The result is identical between 4.85 and 4.65 , as long as cores can suspend (Global C-States) 
Cores never go bellow P0 state for me @ 3.7 , but this still does powersave ~ as realistic bandwidth on the other cores is between 0mhz and 100mhz


Audioboxer said:


> Speaking of ClkDrvStr 60 it's the one thing that helped me run tRCDRD 13 at 3800 for a bit longer than "instant error 6s". Not sure what that tells me though. Going to assume IMC might just not be good enough to even attempt tRCDRD 13 at 3800.


Are you by any chance having bad luck and got B1 PCBs ?
Read out in Thaiphoon Burner ?
#6 spam at the start sounds like the same ECC behavior ~ i experience


----------



## Mach3.2

Veii said:


> Can i disprove the first phrase ?
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> tRFC(approximately), not exactly.
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> The only real difference is between throttling and non throttling peak clock
> Higher limits request higher VID, reach higher thermal load, get throttled faster
> 
> Decent setups have close to zero difference between stock with open limits and finetuned with open limits
> Inter-Core latency doesn't change all too much on the same FCLK just because clocks run higher.
> The only way to really cheat the system , is to affinity change your layout and ontop of that run OC_MODE without active throttling (not a thing i will ever do)
> (OC_MODE still will be package throttled but not clock speed throttled ~ FIT remains active / Especially important for XOC guys, identical to how 6900XTXH now behave)
> 
> And also there is the same margin of error (too small but still existing 0.2ns) difference between single 2x8 and dual rank 2x16 at the same speed and same timings
> The only difference here between dual rank and single rank guys, is the strain to the CCDs.
> This remains a virtual silicon lottery value. Which VDDG voltage values each sample needs. Nothing we should cry about.
> Else no ~ everyone can reach the same value as to everyone else. But i can see it makes sense to split 1 CCD vs Dual CCD results.
> Bugged samples like mine draw from bad sides the worse cards. 2nd CCD who eats power, yet extremely restricted 6 core by AMD & not even stable at stock.
> 
> Ignoring all this WHEA mess, everyone else should have a far better & easier time ~ than me
> EDIT:
> Clock speed potentially increases Bandwidth of the set, but does barely to non increase Random Access MemLatency
> That's a fabric and intercore part.
> L3 part and remain cache part yes ~ but not on mem latency. It really isn't behaving that way
> A non throttling system on stock and a non throttling on maxed clock - will have the same mem-latency , with a tiny difference maybe. But it falls under margin of error


This is a lot to take in, but currently what you're trying to say is those who got higher latency(~53+ns) on 3800MHz CL14 vs lower latency at the same setting(~51ns) is because of some form of CPU throttling?

Higher clock speed increasing bandwidth, that I can accept, since that is what I observed here as well. I'm still not quite sure I understand how clock speed affects AIDA RAM latency(or if there's even any relationship at all) after reading your post.


----------



## Audioboxer

Veii said:


> Can i disprove the first phrase ?
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> tRFC(approximately), not exactly.
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> The only real difference is between throttling and non throttling peak clock
> Higher limits request higher VID, reach higher thermal load, get throttled faster
> 
> Decent setups have close to zero difference between stock with open limits and finetuned with open limits
> Inter-Core latency doesn't change all too much on the same FCLK just because clocks run higher.
> The only way to really cheat the system , is to affinity change your layout and ontop of that run OC_MODE without active throttling (not a thing i will ever do)
> (OC_MODE still will be package throttled but not clock speed throttled ~ FIT remains active / Especially important for XOC guys, identical to how 6900XTXH now behave)
> 
> And also there is the same margin of error (too small but still existing 0.2ns) difference between single 2x8 and dual rank 2x16 at the same speed and same timings
> The only difference here between dual rank and single rank guys, is the strain to the CCDs.
> This remains a virtual silicon lottery value. Which VDDG voltage values each sample needs. Nothing we should cry about.
> Else no ~ everyone can reach the same value as to everyone else. But i can see it makes sense to split 1 CCD vs Dual CCD results.
> Bugged samples like mine draw from bad sides the worse cards. 2nd CCD who eats power, yet extremely restricted 6 core by AMD & not even stable at stock.
> 
> Ignoring all this WHEA mess, everyone else should have a far better & easier time ~ than me
> EDIT:
> Clock speed potentially increases Bandwidth of the set, but does barely to non increase Random Access MemLatency
> That's a fabric and intercore part.
> L3 part and remain cache part yes ~ but not on mem latency. It really isn't behaving that way
> A non throttling system on stock and a non throttling on maxed clock - will have the same mem-latency , with a tiny difference maybe. But it falls under margin of error
> 
> EDIT2:
> View attachment 2529464
> 
> While MemLatency only pegs the first core - it will keep the rest sleeping
> Read, Copy , Write peg all cores starting from the last
> 1,2,3,4,5,6 cores
> twice , then it decides the result
> But Write especially will show throttling if FCLK is unstable
> The other two not so much - yet they all peak allcore load, but step by step - for me it's 12 measurements. For dual CCD units this can take 2-3 min to finish
> But yet this first core doesn't do anything
> The result is identical between 4.85 and 4.65 , as long as cores can suspend (Global C-States)
> Cores never go bellow P0 state for me @ 3.7 , but this still does powersave ~ as realistic bandwidth on the other cores is between 0mhz and 100mhz
> 
> Are you by any chance having bad luck and got B1 PCBs ?
> Read out in Thaiphoon Burner ?
> #6 spam at the start sounds like the same ECC behavior ~ i experience


Thaiphoon says B1










However, apparently these highest binned sticks only come in "one PCB"



















From what I've gathered they are all A2/B2 depending on SR/DR.

Supposedly A1/B1 would struggle with as tight timings?


----------



## Veii

Mach3.2 said:


> This is a lot to take in, but currently what you're trying to say is those who got higher latency(~53+ns) on 3800MHz CL14 vs lower latency at the same setting(~51ns) is because of some form of CPU throttling?
> 
> Higher clock speed increasing bandwidth, that I can accept, since that is what I observed here as well. I'm still not quite sure I understand how clock speed affects AIDA RAM latency(or if there's even any relationship at all) after reading your post.


Sorry for the late edit
But i just noticed now that it does test in multi peaks
1 core , 2 core 4, core , 6 core / two loops
That's for the bandwidth part ~ this is intercore latency focused, but can scale with cpuOC
the memory latency test on itself is soo low IPC, that it doesn't show to matter at all. There is no real difference between 4.65 and 4.85 maxed out.

While it does test this, other cores have to be able to sleep or park at least
So this is one of the reasons why the latency test the first one pretty much always is bad or unrealistic. Aside from windows loading their DLLs into other priority cores and ruining core parking

There is a difference between core amount on the samples, but to what SiSoftware Sandra shows me - it doesn't matter between 6 & 8 cores
The "multi ring bus" are very fast, 2 cores make no change. Potentially it averages out for 5800X users, as they have a 105c prochot, a 100mhz higher P0 state and higher boost
Soo maaybe they have 0.2-0.3ns lead when fully maxed out ~ but this is the absolute best case.
The testing shows that there is a too small difference with only 200mhz

I thought it does affect it, but the latest testing shows it doesn't, as long as both examples can not throttle
The difference is far to small to matter.
What i think really is the difference, is powerdraw and the limiters.
But without them at least on first stage ~ there is zero

I also see that i get prochot throttled on this 1-2sec burst allcore test for Read, Copy & Write
It doesn't reach my 4.85 on it

L3 Latency also tests only the best or first core (this should change soon)
Or the test is too fast and ZenPMTool can not track it.
Sadly readout aside ~ experience shows that it will be worse if "all cores" are not tuned . Which makes no sense if it only tests the first one


----------



## Veii

Audioboxer said:


> However, apparently these highest binned sticks only come in "one PCB"


The 3200C14-14-14 he got very lucky with, but this is on another PCB
This B1 here shows full ECC functionality and also MBIST training delays like a typical ECC dimm.

Maybe other newer 2021 revisions are fixed, but this here at least shows active ECC ~ to how it behaves
I do think you have the same problematic dimm , but it depends how long training takes for you
You should try to enable MBIST with both patterns , and let it train correctly. This could resolve the tPHY missmatch
For me it's 26-26 or 28-28, nothing in between ~ but they take minutes to post on a cold boot

EDIT:


Veii said:


> This B1 here shows full ECC functionality and also MBIST training delays like a typical ECC dimm.


I have to praise ASRock this time. Memory Training always trains when it can
It might take a veery long time, and even when i disagree that it shouldn't be accessible
Whatever they setup ~ MBIST and generally Training is correctly set up on this P2.20 SMU 56.53 Patch-C Bios



Audioboxer said:


> Supposedly A1/B1 would struggle with as tight timings?


I've never seen a consumer A1/B1 PCB, which has active ECC & so needs thaat long to post
They forget to disable something or intentionally kept it in. But it shows autocorrection behavior on my side ~ which is bothersome
A1 PCBs can run lower timings than A2, while A2 does introduce higher strain but is better for higher frequency (4133+)
Till 4000 they show no difference, except A2 being more power hungry


----------



## Audioboxer

Veii said:


> The 3200C14-14-14 he got very lucky with, but this is on another PCB
> This B1 here shows full ECC functionality and also MBIST training delays like a typical ECC dimm.
> 
> Maybe other newer 2021 revisions are fixed, but this here at least shows active ECC ~ to how it behaves
> I do think you have the same problematic dimm , but it depends how long training takes for you
> You should try to enable MBIST with both patterns , and let it train correctly. This could resolve the tPHY missmatch
> For me it's 26-26 or 28-28, nothing in between ~ but they take minutes to post on a cold boot
> 
> EDIT:
> 
> I have to praise ASRock this time. Memory Training always trains when it can
> It might take a veery long time, and even when i disagree that it shouldn't be accessible
> Whatever they setup ~ MBIST and generally Training is correctly set up on this P2.20 SMU 56.53 bios Patch-C Bios


What is MBIST? A BIOS setting?

I guess this could be a 2021 PCB revision. The 3600 14-14-14-14 DR set I had seemed to be the exact same PCB as this, although I never took the heatsinks off it. Both manufactured within a month of each other.

This set is August 2021 manufactured.


----------



## PJVol

Memory built-in self training test


----------



## Audioboxer

PJVol said:


> Memory built-in self training test


Thanks, I was asking about a BIOS setting due to Veii saying



> You should try to enable MBIST with both patterns


Thinking is it something that needs to be turned on?

Anyway, I've got 26/26 or 28/28, no mismatch now, it's just the weird behaviour of tCL13/15 will = 26/26 at 1T, 28/28 at 2T and tCL 14/16 will = 28/28 at 1T, 26/26 at 2T.

So if I want to run 1T I'm better running tCL13/15 lol.


----------



## XPEHOPE3

Veii said:


> Wait for it to post ~ Triggering MBIST can take 30-120sec to train alone


Did you try setting aggressors to max (as I do for 16*4), not middle setting?


Veii said:


> Can i disprove the first phrase ?





Veii said:


> What i think really is the difference, is powerdraw and the limiters.


Maybe that. Judging from my "records" on the OC list, enabling PBO+CO+200MHz boost definitely shove 0.5ns latency. I attributed that for core clocks only but didn't check w/o +200MHz. @Mach3.2 can you test this? (I'm lazy to do it😇)


Audioboxer said:


> What is MBIST? A BIOS setting?











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


tRAS scaling issue? what do you mean? The earlier settings you asked me to test on the Rev.E kit, gotta ask. Are they as low as they go for you or can they do better? Because my kits have all done much better on the sub timings in general. The settings you had were quite relaxed to be said. I...




www.overclock.net




and with screens [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## Audioboxer

XPEHOPE3 said:


> Did you try setting aggressors to max (as I do for 16*4), not middle setting?
> Just like mine  inb4 it throttles like that whatever you do 💩
> 
> Maybe that. Judging from my "records" on the OC list, enabling PBO+CO+200MHz boost definitely shove 0.5ns latency. I attributed that for core clocks only but didn't check w/o +200MHz. @Mach3.2 can you test this? (I'm lazy to do it😇)
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> tRAS scaling issue? what do you mean? The earlier settings you asked me to test on the Rev.E kit, gotta ask. Are they as low as they go for you or can they do better? Because my kits have all done much better on the sub timings in general. The settings you had were quite relaxed to be said. I...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> and with screens [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Thanks soo much, I'll have a poke around in the MSI BIOS and see where those settings are. I have an unlocked BIOS by a forum member from OC so if they are hidden on MSI BIOS I believe they should be available for me, somewhere.

*edit* - Playing around with the MBIST settings doesn't _magically _make 26/26 work at tCL14 1T, but it's still good to know where these settings are.


----------



## Veii

XPEHOPE3 said:


> Did you try setting aggressors to max (as I do for 16*4), not middle setting?


Sadly i can not access them, usually they only test one way, and not both patterns
Aggressors usually default to 1 instead of 3. 7 was too overdone
I sadly do not know what they (ASRock) run now, but usually MBIST (which is a category before the ECC field) ~ half of it get's skipped if the dimm doesn't support ECC
Yet here i am sitting half till 2 minutes waiting for memory training to finish

The kit i got was labeled to be the worst kit ~ "the most special of all which didn't even pass JEDEC stability testing"
The 3200C14-14-14 one 2021 model , run 4000C14-15 @ 1.55v (not a big achievement, but at least something)


Audioboxer said:


> Playing around with the MBIST settings doesn't _magically _make 26/26 work at tCL14 1T, but it's still good to know where these settings are.


Play around with 2.5v PROM , and higher voltage
It did train 26-26 for me once on 40-20-30-20 6-3-3
but on lower voltage near the 1.52-1.55v range it had to switch to 7-3-3 which dropped to 28-28

You know when MBIST actually runs the full way, when it takes over a minute to train 
Else a bigger portion of it is just skipped

Also give it a try to go bellow 36ohm procODT
Then it switched to 26-26, but instantly errors
Can try if you can drop PROM to 2.45 ~ if this posts at all, but i think you need over 2.5v now for it
It guaranteed refuses to post for me on 2.45v, at any procODT and VDIMM combination


----------



## Audioboxer

Veii said:


> Sadly i can not access them, usually they only test one way, and not both patterns
> Aggressors usually default to 1 instead of 3. 7 was too overdone
> I sadly do not know what they (ASRock) run now, but usually MBIST (which is a category before the ECC field) ~ half of it get's skipped if the dimm doesn't support ECC
> Yet here i am sitting half till 2 minutes waiting for memory training to finish
> 
> The kit i got was labeled to be the worst kit ~ "the most special of all which didn't even pass JEDEC stability testing"
> The 3200C14-14-14 one 2021 model , run 4000C14-15 @ 1.55v (not a big achievement, but at least something)
> 
> Play around with 2.5v PROM , and higher voltage
> It did train 26-26 for me once on 40-20-30-20 6-3-3
> but on lower voltage near the 1.52-1.55v range it had to switch to 7-3-3 which dropped to 28-28
> 
> You know when MBIST actually runs the full way, when it takes over a minute to train
> Else a bigger portion of it is just skipped
> 
> Also give it a try to go bellow 36ohm procODT
> Then it switched to 26-26, but instantly errors
> Can try if you can drop PROM to 2.45 ~ if this posts at all, but i think you need over 2.5v now for it
> It guaranteed refuses to post for me on 2.45v, at any procODT and VDIMM combination


Sorry for another question but what is the 2.5v PROM? Is it another voltage setting called that in the BIOS? Only other voltage setting I've ever played around with is the CPU 1.8v.

I'm guessing it's CHIPSET PHY voltage given its description says 2.5v default.

And yeah if I just enabled MBIST and leave deadeye as is I get bios code 25 for like 30-60 seconds on post.

*edit* - If 2.5V PROM is CHIPSET PHY voltage then 2.45v boots fine for me. Also quickly played around with 1.6v VDIMM, 40/20/30/20, 6-3-3 and ProcODT of 32~34.3 at various PHY voltages and she's sticking steady to 28/28 at tCL14 1T


----------



## Blameless

Dodgexander said:


> Thanks. Testing RTT's alone would mean testing 343 combinations.


You shouldn't have to test every permutation. RttPark is the big one for higher densities, RttWr will either be /3 /2 or disabled for most setups, and RttNom is usually 5-7 with fairly subtle differences.

In any case, you should be able to narrow in on optimal or near optimal settings by testing extremes first, then narrowing things down. It's like playing _Battleship_...you don't need to test every grid...just the ones around your initial hits.


----------



## Mach3.2

XPEHOPE3 said:


> Did you try setting aggressors to max (as I do for 16*4), not middle setting?
> 
> Maybe that. Judging from my "records" on the OC list, enabling PBO+CO+200MHz boost definitely shove 0.5ns latency. I attributed that for core clocks only but didn't check w/o +200MHz. @Mach3.2 can you test this? (I'm lazy to do it😇)


What do I have to do? Run AIDA memory tests with PBO boost clocks and without PBO boost clocks? 😅


----------



## XPEHOPE3

Mach3.2 said:


> What do I have to do? Run AIDA memory tests with PBO boost clocks and without PBO boost clocks? 😅


What are your current settings regarding PBO boost and limits? If your limits are open enough, I suggested just run like usual and compare with a run with PBO boost 0MHz instead of whatever you have set there now (200, 150, etc).


----------



## Veii

Audioboxer said:


> I'm guessing it's CHIPSET PHY voltage given its description says 2.5v default.
> 
> *edit* - If 2.5V PROM is CHIPSET PHY voltage then 2.45v boots fine for me. Also quickly played around with 1.6v VDIMM, 40/20/30/20, 6-3-3 and ProcODT of 32~34.3 at various PHY voltages and she's sticking steady to 28/28 at tCL14 1T


Sadly, that's all i know, for now
I have a chipset voltage which is on B550 1.05v - 1.06 is fine for it , 1.07 doesn't do anything for B550

Resources would state that 1.05vPROM-S5 & 2.5vPROM exist
Yet nothing states that S5 = chipset voltage
In general PCH to ROM voltage shouldn't start to cause issues just because it's back on normal load, by having dual rank on it
PROM 2.5vRail has to have another connection with something - to actually show issues when it drops lower (while it did not on 2x8)

You technically shouldn't be able to post anything sub 36.9ohm procODT,
Or at least nothing that is #6 free


----------



## Mach3.2

XPEHOPE3 said:


> What are your current settings regarding PBO boost and limits? If your limits are open enough, I suggested just run like usual and compare with a run with PBO boost 0MHz instead of whatever you have set there now (200, 150, etc).


CO settings: -30, -30, -28, -30, -30, -30, -30, -20, -30, -30, -30, -30
+75MHz boost override, 1X PBO Scalar.
PPT: 145W
TDC: 110A
EDC: 180A


----------



## XPEHOPE3

@Mach3.2 
Yeah, limits are open, just compare with and without boost override.


----------



## ioannis91

How do you find the right tRFC/2 and /4? I do it through dram calculator. Is it correct?


----------



## Mach3.2

XPEHOPE3 said:


> @Mach3.2
> Yeah, limits are open, just compare with and without boost override.


First run discarded, only the next 6 subsequent run is recorded.









If there's a difference it's a damn small one at less than 0.1ns averaged over 6 runs between +75MHz boost and no boost.


----------



## Akex

ioannis91 said:


> How do you find the right tRFC/2 and /4? I do it through dram calculator. Is it correct?


tRFC = tRC x [4-5-6-7 ect ect]
tRFC 2 = tRFC / 1.346
tRFC 4 = tRFC 2 / 1.625


----------



## Audioboxer

AMD have released Windows 11 chipset drivers https://www.amd.com/en/support/kb/release-notes/rn-ryzen-chipset-3-10-08-506










Read/Write/Copy is a bit better, latency is still too high. MS still have to do better with it. 10.2ns was pretty much standard for me on Windows 10. Incoming posts everywhere across social media saying "its all fixed!" in defence of Windows 11 when it clearly still isn't 100% there.


----------



## Luggage

Audioboxer said:


> AMD have released Windows 11 chipset drivers https://www.amd.com/en/support/kb/release-notes/rn-ryzen-chipset-3-10-08-506
> 
> View attachment 2529520
> 
> 
> Read/Write/Copy is a bit better, latency is still too high. MS still have to do better with it. 10.2ns was pretty much standard for me on Windows 10. Incoming posts everywhere across social media saying "its all fixed!" in defence of Windows 11 when it clearly still isn't 100% there.


Wasn’t AMDs job to fix CPPC preferred Cores and MSs to fix L3 cache?

edit: now that I read what I wrote that sounds totally backwards…


----------



## Dodgexander

mongoled said:


> So what gains are we looking at in terms of L1 latency from a standard Windows 10 install with AV disabled to a stripped down Windows 10 install ??
> 
> 0.5 ns ??
> 
> As ive noted there are an increasing number of sub 50ns entries in the DRAM Overclocking database and I am wondering how so many are reducing their latency too such an extent as it does not seem to be coming from frequency/timings when I compare it to my setup ....


Definitely has an impact, just closing Geforce Experience before running AIDA for me shaves at least 0.3ms off...sometimes more. The people who are at the top of the sheet will be using dedicated minimal installs, that's for sure. A dedicated disk with an install is probably a good idea anyway to avoid any corruption. Hydra also mentioned above shaves time off results.


----------



## Luggage

Dodgexander said:


> Definitely has an impact, just closing Geforce Experience before running AIDA for me shaves at least 0.3ms off...sometimes more. The people who are at the top of the sheet will be using dedicated minimal installs, that's for sure. A dedicated disk with an install is probably a good idea anyway to avoid any corruption. Hydra also mentioned above shaves time off results.


For example: Aqua computer service added about 3ns to mem latency for me, and 0.5 for L3



http://imgur.com/a/tD7HmIm


----------



## Audioboxer

Think I'm going to go back to Windows 10 for now, between AMD and MS it just doesn't seem properly ready.

I know it's lazy but @KedarWolf does anyone do lite ISOs of Windows 10 or am I going to have to learn this? Optimize-Offline Guide - Windows Debloating Tool, Windows 1803, 1903, 19H2, 1909, 20H1 and LTSC 2019  🤝


----------



## Veii

Akex said:


> tRFC = tRC x [4-5-6-7 ect ect]
> tRFC 2 = tRFC / 1.346
> tRFC 4 = tRFC 2 / 1.625


This method you stack rounding issues
tRFC 4 = tRFC / 2.1875
generally you turn it to ns first ,then do the math and at end round back
You never divide virtual values, but only ns values

tRFC mini manual section exits for exactly such
Either you know your virtual value, or you directly start with ns
But you never do math on virtual values as these where rounded already and will introduce stacking rounding issues


----------



## domdtxdissar

Veii said:


> @domdtxdissar for SOTTR, i need a better GPU than this 650 here
> Maybe if time remains i'll test the 5900X on it.
> Also they removed Denuvo but enforce Online EPYC Games integration. Accepting , then linking the accounts and manually unlinking it
> - allows you to play it without EPYC Games games host filtering


We are mainly looking at CPU Game FPS where GPU don't matter.. 

That's also why i ran all my latest game-benchmarks in 1080p 


http://imgur.com/a/RwxpB0T

(few different games in there)

Also recorded the SotTR run 😇





Memorysettings used:


----------



## Veii

domdtxdissar said:


> We are mainly looking at CPU Game FPS where GPU don't matter..


Logical, but i doubt it would even start
Will test it when i free up space

Its not quake or crysis to be fully CPU bound, would surprise me if it was
I'll give it a go but really doubt it would run at all.


----------



## mongoled

Im hoping its the incorrect tRFC4 value that caused this but highly doubt it

😂😂


----------



## mongoled

domdtxdissar said:


> We are mainly looking at CPU Game FPS where GPU don't matter..
> 
> That's also why i ran all my latest game-benchmarks in 1080p
> 
> 
> http://imgur.com/a/RwxpB0T
> 
> (few different games in there)
> 
> Also recorded the SotTR run 😇
> 
> 
> 
> 
> 
> Memorysettings used:
> View attachment 2529531


So little vDIMM


----------



## Audioboxer

domdtxdissar said:


> We are mainly looking at CPU Game FPS where GPU don't matter..
> 
> That's also why i ran all my latest game-benchmarks in 1080p
> 
> 
> http://imgur.com/a/RwxpB0T
> 
> (few different games in there)
> 
> Also recorded the SotTR run 😇
> 
> 
> 
> 
> 
> Memorysettings used:
> View attachment 2529531


Are you still finding SCL 4 is performing better? I really need to get around to testing that properly!


----------



## MrHoof

Audioboxer said:


> Are you still finding SCL 4 is performing better? I really need to get around to testing that properly!


For me 2 and 3 perform same and are both stable at 4 i see a small performance drop.

edit: Nvm i retested it to make sure I dont talk bs and suddenly 4 is giving the same reuslts in aida. I tested it a few time in the past and dropped like 200mb copy/read, i have no idea what changed.


----------



## domdtxdissar

Audioboxer said:


> Are you still finding SCL 4 is performing better? I really need to get around to testing that properly!


I found scl4 giving me best results.
2 and 3 behave 100% same



MrHoof said:


> For me 2 and 3 perform same and are both stable at 4 i see a small performance drop.
> 
> edit: Nvm i retested it to make sure I dont talks bs and suddenly 4 is giving the same reuslts in aida. I tested it a few time in the past and dropped like 200mb copy/read, i have no idea what changed.


Dont relay too heavy on Aida64 for performance testing..

Anta777 recommended corona benchmark, i like to test with dram calc and SotTR


----------



## MrHoof

domdtxdissar said:


> Recommend not to relay to heavy on Aida64 for performance testing..
> 
> Anta777 recommended corona benchmark, i like to test with dram calc and SotTR


Already did a follow up dram calc run and its also no diffrence at 4 191,4 sec at default 12GB 16T, but I do Aida first most of the time and it always showed a performance decrease so i didnt bother testing further.
Gonna download the SotTR demo i guess.


----------



## domdtxdissar

MrHoof said:


> Already did a follow up dram calc run and its also no diffrence at 4 191,4 sec at default 12GB 16T, but I do Aida first most of the time and it always showed a performance decrease so i didnt bother testing further.
> Gonna download the SotTR demo i guess.


In Aida i get around ~200-300mb/sec lower read but ~150mb/sec higher write with SCL 2's instead of SCL 4.

In dram calc i get maybe 0.5sec higher easy bench times on average, with SCL 2's instead of SCL 4.

Think i also have higher average minimum cpu fps numbers with SCL 4, if i calculate the average over something like 10 runs.

Difference in small, but its there.. think i also i showed the difference i found in the corona benchmark some pages back in this thread.


----------



## PhoenixMDA

@domdtxdissar
How high is your CPU power in watt in Game´s like BF5?
Your oc performance is really great, i wont to know how high the real power usage is in Game´s with high CPU usage.
I think arround 150-200W is that right and how much in low load game like normal game´s, so approximately.

P.S.
Of thinking about x570s Unify-x with 3D refresh, but i don´t want to change my 700W fanless for silent pc.


----------



## domdtxdissar

PhoenixMDA said:


> @domdtxdissar
> How high is your CPU power in watt in Game´s like BF5?
> Your oc performance is really great, i wont to know how high the real power usage is in Game´s with high CPU usage.
> I think arround 150-200W is that right and how much in low load game like normal game´s, so approximately.
> 
> P.S.
> Of thinking about x570s Unify-x with 3D refresh, but i don´t want to change my 700W fanless for silent pc.


I dont have BF5

With my "normal overclock" i'm getting these numbers while running everyday 24/7 hydra OC profiles

Around 130watt average and max 148watt in SotTR








Around 75 watt average and max 85watt in F1 2020








Around 220w for 137xx points in CPU-Z multithread








Check power/performance numbers for more stock systems in Cinebench r23 if interested here:


----------



## Veii

mongoled said:


> Im hoping its the incorrect tRFC4 value that caused this but highly doubt it


Give tWTR_L 10 a try & try to push CkeClkDrvStr to 24
If that doesn't work , remove this DrvStr but try 1-5-4-1-7-6 on them 
Let me know if any of this ever changed the result & when you get #10


----------



## mongoled

Mach3.2 said:


> Maybe I'm doing something wrong but there's absolutely no difference for my setup, maybe 0.05ns difference between bone stock windows 10 with minimal services running and windows defender turned on, and windows 10 cleaned with sophia script and windows defender disabled.
> 
> IMO since AIDA latency results are heavily influenced by clock speed, there's not much meaning comparing between different setups.
> 
> As you've seen in this thread running hydra OC can give you close to 50ns of latency on 3800 flat 14, whereas with just PBO you're probably getting closer to 54ns.


Nice conflicting opinions



I highly doubt you are doing anything wrong, just a little strange that two members have different results



Dodgexander said:


> Definitely has an impact, just closing Geforce Experience before running AIDA for me shaves at least 0.3ms off...sometimes more. The people who are at the top of the sheet will be using dedicated minimal installs, that's for sure. A dedicated disk with an install is probably a good idea anyway to avoid any corruption. Hydra also mentioned above shaves time off results.


Yeah, I guess they are, not sure im willing to spend the time to wipe the gaming OS and replace with a tweaked one.

Something I have noticed but dont understand the reasons and what I am going to describe occurs consistently.

Because I have the PC at my office, I often connect to it via RDP (from behind a VPN), ive noted that if I run an AIDA64 cache and mem test I get better results then when sitting in front of the PC !!

An example below, note L3 cache latency and memory latency, I never hit 10.4ns, lowest is always 10.5 and memory latency has .2ns shaved off.

The only thing I can think of is while I am connected via RDP, the RDP sessions sits on my best core that is core0, the next best core is core 4 and I am guessing that the test runs solely on core4 without flip flopping between core 0 and core 4 because the RDP session is "holding" core 0.

With this in mind, might as well forget the tweaked OS and just use RDP

😂 😂


----------



## mongoled

Veii said:


> Give tWTR_L 10 a try & try to push CkeClkDrvStr to 24
> If that doesn't work , remove this DrvStr but try 1-5-4-1-7-6 on them
> Let me know if any of this ever changed the result & when you get #10


Just running it with the correct tRFC4, then after its finished will try the above.

Look at my above post

 

Oh and strangely enough once I bumped to 3866 mhz write memory no longer hits 30999, but 30932, never had that issue at 3800 mhz !
Ughhh got that all wrong, was hitting 30399, doh


----------



## Veii

mongoled said:


> Look at my above post
> 
> 
> Mach3.2 said:
> 
> 
> 
> As you've seen in this thread running hydra OC can give you close to 50ns of latency on 3800 flat 14, whereas with just PBO you're probably getting closer to 54ns.
Click to expand...

Hydra @ 4.975-5.0 with affinity focus, gives me 50.8ns to 51ns
PBO gives me 48.5ns

It will be even higher on Aida64 if i isolate it and only test the first row, soo core affinity focus on the best core
But that's really not the goal to modify the testing / although i can see how this can give a big lead on the Zen3 OC sheet
Not that we can't modify WHEA reports at all ^^'


mongoled said:


> Just running it with the correct tRFC4, then after its finished will try the above.











Always doublecheck if the sheet is not broken.
because it was again 🤦‍♂️


----------



## mongoled

Veii said:


> Hydra @ 4.975-5.0 with affinity focus, gives me 50.8ns to 51ns
> PBO gives me 48.5ns
> 
> It will be even higher on Aida64 if i isolate it and only test the first row, soo core affinity focus on the best core
> But that's really not the goal to modify the testing / although i can see how this can give a big lead on the Zen3 OC sheet
> Not that we can't modify WHEA reports at all ^^'
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Always doublecheck if the sheet is not broken.
> because it was again 🤦‍♂️


It was not the sheet problem, I was following @Akex advice that that you corrected



Im running the correct values right now, on cycle 9, so far all is good, but those 10s appeared late on, for sure after the 16th cycle ...


----------



## Taraquin

So I finally tried all of anta777's recommendations, but some was impossible. Wtrl below 9 gives errors, scl 3 or 2 gives lots of errors, rdsd 4 and wrsd 6 gives rare reboots so I guess this is how far I can get without improving cooling to the ram. I'm satisfied that I only needed 0.02V vs 1T gdm on to stabilize gdm off, vs 2T I needed 0
01V. Tried 24 20 24 24, got lots of errors, tried 30 20 24 24, got some errors, 40 20 24 24 wouldn't boot, 40 20 30 24 is errorfree in karhu and TM5 so DrvStr was the major key for 1T pure. Also tried 60 20 30 24 and I got my first whea 19 in 5 months so it seems DrvStr can trigger that. ProcODT, setuptimes and different Rtts made no difference. Guess I'm happy with this considering the poor bin, tRAS 29, tRC 45 and tWR 10/RTP 5 also works, but I must test it a bit more to see if truly stable.


----------



## Dodgexander

So disheartening. I thought I managed to get 14-14-14-14-28-42 stable by running different RTT and Drive Strength but it failed right at the end of the test. My guess would be higher termination resistance is increasing heat.

...I did find some more stability but in practice changing all these settings don't seem to actually allow me to run tighter timings.

Also had a mess around trying 1T without any setup time. Higher procODT and RTT definitely helps but still didn't stabilize anything.

Right now I think I'm held back by my bins and perhaps also that I needed to use higher SoC than most. Seems the lower people can get their SoC the more they can push memory.


----------



## Dodgexander

Taraquin said:


> So I finally tried all of anta777's recommendations, but some was impossible. Wtrl below 9 gives errors, scl 3 or 2 gives lots of errors, rdsd 4 and wrsd 6 gives rare reboots so I guess this is how far I can get without improving cooling to the ram. I'm satisfied that I only needed 0.02V vs 1T gdm on to stabilize gdm off, vs 2T I needed 0
> 01V. Tried 24 20 24 24, got lots of errors, tried 30 20 24 24, got some errors, 40 20 24 24 wouldn't boot, 40 20 30 24 is errorfree in karhu and TM5 so DrvStr was the major key for 1T pure. ProcODT, setuptimes and different Rtts made no difference. Guess I'm happy with this considering the poor bin, tRAS 29, tRC 45 and tWR 10/RTP 5 also works, but I must test it a bit more to see if truly stable.
> View attachment 2529594


Interesting you had the opposite to me. I find drive strength didn't help at all with 1T and I needed the setup time. Great results though, I envy your FCLK!
Also have no idea how you managed this all at 1.45v!


----------



## Taraquin

Dodgexander said:


> Interesting you had the opposite to me. I find drive strength didn't help at all with 1T and I needed the setup time. Great results though, I envy your FCLK!
> Also have no idea how you managed this all at 1.45v!


Seems every MB is different, and CPUs also need different voltages, I seem to get no benefit from higher vddp\ccd running 840mv or 920mv gives me same results, but I get a bit more pwr-budget for my CPU running 840mv. My ram-binning is not good, it`s okay at tRFC, but it hates low tCL, tRC and tRP. I need 1.55V to stabilize 4000cl15 2T, but then ram overheats after a few minutes in karhu, TM5 etc. FCLK is probably due to mATX-board. It seems like many ITX and mATX-boards can do 4000-4200 fclk without whea 19, especially if CPU has only one CCD, maybe due to less complexity with traces etc.


----------



## Dodgexander

Taraquin said:


> Seems every MB is different, and CPUs also need different voltages, I get no benefit from . My ram-binning is not good, it`s okay at tRFC, but it hates low tRC and tRP. I need 1.55V to stabilize 4000cl15, but then ram overheats after a few minutes in karhu, TM5 etc. FCLK is probably due to mATX-board. It seems like many ITX and mATX-boards can do 4000-4200 fclk without whea 19, especially if CPU has only one CCD, maybe due to less complexity with traces etc.


Ah yes, of course. These two slot boards really do shine in that respect. In my years of overclocking I don't think I can say I've ever really had a motherboard or CPU pairing I've been happy with. I always seem to get the worse bins. Memory has been hit or miss.

I do wish there was a bit more sense behind changing these settings. As someone already said it's like playing battleship. There's very few patterns to be made with the AMD specific settings.


----------



## mongoled

mongoled said:


> Im running the correct values right now, on cycle 9, so far all is good, but those 10s appeared late on, for sure after the 16th cycle ...


Like clockwork,

On the 16th cycle an error 10 popped up, time to try your suggestion



** EDIT **
Errored after 2 cycles with tWTR_L and CLK/CKE changes, have reverted the CLK/CKE settings and am testing again ..


----------



## Taraquin

Dodgexander said:


> Ah yes, of course. These two slot boards really do shine in that respect. In my years of overclocking I don't think I can say I've ever really had a motherboard or CPU pairing I've been happy with. I always seem to get the worse bins. Memory has been hit or miss.
> 
> I do wish there was a bit more sense behind changing these settings. As someone already said it's like playing battleship. There's very few patterns to be made with the AMD specific settings.


I decided a few things after testing 2 4-dimm MBs with Ryzen 3600. I want a 2 dimm MB next time as it`s easier to OC ram, and that leaves me with expensive full ATX-boards like Unify, ITX which lacks connectivity or some mATX-boards. I only found 6 mATX-boards with 2 dimms, and only the Gigabyte B550m S2H and Gaming had heatsink over vrm. Gaming has few advantages over S2H and costed 60usd more so S2H it was. A few ITX-boards were good options aswell, and the Unify now cost 240usd, but costed over 300 in April when I bought the MB. S2H costed 110usd and fit the budget perfectly.

As for memory it`s a bit easier with B-die than many other kits as you can pay the premium and get awesome binning like 4000cl14\15, you know these kits will be great, or you could do like me and buy a cheap kit that atleast do high speed okay, but timings is another matter. I only paid 150usd for the Viper 4400cl14, that was the same price Ripjaws\FlareX 3200cl14. It was the cheapest B-die available except for Ripjaws 3000cl14, but then binning is so terrible that it might not do 3800cl16. I value bang for bucks, therefore I got the 5600X instead of 5800X, S2H instead of Unify and 4400cl19 instead of 4000cl14\15. I paid 660usd total then (5600X was overpriced) vs 1150usd which the 5800X\Unify\4000cl14\15 would have cost. The latter would prbably have given me a few percent better performance, but not worth it for me


----------



## KedarWolf

PhoenixMDA said:


> @domdtxdissar
> How high is your CPU power in watt in Game´s like BF5?
> Your oc performance is really great, i wont to know how high the real power usage is in Game´s with high CPU usage.
> I think arround 150-200W is that right and how much in low load game like normal game´s, so approximately.
> 
> P.S.
> Of thinking about x570s Unify-x with 3D refresh, but i don´t want to change my 700W fanless for silent pc.


Here is BF5 with an aggressive CPU Curve, -30, -7, -15 two top cores, 150 Scaler 6, Boost Override 150.










The .cvs file download and open with an Online CVS Viewer, it has stuff like my AX1600i voltages, GPU voltages, everything from HWInfo. Rename and remove the .txt.


----------



## Veii

mongoled said:


> Like clockwork,
> 
> On the 16th cycle an error 10 popped up, time to try your suggestion


So much towards a broken testing config 🙊

You can get #10s away with more RTT_NOM, but they turn to #2's
Not sure which to prioritise sadly
I think #2s are less worse than 10s
You'll figure it out
Just saying #10s likely have to do with powering, #2 likely have to do with transition timings such as tRRD, tWTR, tRDWR, SD DD

Soo 10 could also be a CAD_BUS issue, while #2 can also be a vdimm issue
Usually 0,6,2 appear on vdimm issues. Unsure about the 10 i forgot

What did you even get at the start ?


----------



## Bix

Still have some stress testing to do but finally seem to have 1t stable with 4x8 at 4000. Passed 3hrs of y-cruncher and 2000% Karhu as well so far. The timings aren't anything to shout about but any suggestions would be gratefully received. Wondering if I might be able to get my latency down a bit - my windows 10 install is a bloated mess and I still need to retune PBO but not sure if I can still bring it down a bit. This is my first time ocing with GDM off and I'm going off what I've read rather than experience in getting things stable so really keen to know if anything looks off. MB did most of the work for me as I only had to raise ClkDrvStr to 30 to get rid of errors going from 2t to 1t but got absolutely nowhere trying to get stable without setup timings. 

I'm trying to see how far I can get at 1.46V since anything above that runs too hot with my 4x8 setup... next step will be to re-think cooling so I can push further but for now I'm interested to see what I can do at 1.46V. I already tried raising tWR to 16 and setting tWTRL and tRTP to 8 in line with anta777's suggestions but was v unstable so set tWR to 12. Can't seem to get tRFC any lower either.


----------



## Veii

Bix said:


> Wondering if I might be able to get my latency down a bit - my windows 10 install is a bloated mess and I still need to retune PBO but not sure if I can still bring it down a bit. This is my first time ocing with GDM off and I'm going off what I've read rather than experience in getting things stable so really keen to know if anything looks off.


tCKE 9 is for 3800, try 11 - and try maaybe to remove AddrCmdSetup

Doublecheck if both A1 and B1 or A2 have the same tPHYRDL ~ in this case all 4 slots
Drop procODT oncce, you should be able to - and compare with multiple rounds if Latency varies over 0.2ns - over 0.3ns deviance ~ trow away the first result
Same goes for Write, it shouldn't vary more than 5MB/s, although dual CCD could maybe not hold full bandwidth

You don't need SETUP timings for SR kits, you should be able to handle this only with tCKE and maaybe 4-4-18 (if it works for you, try it out)


----------



## ZealotKi11er

I se so many people with 2000 but my 5950x cant post with anything over 1866MHz, Would anything help?


----------



## Veii

ZealotKi11er said:


> I se so many people with 2000 but my 5950x cant post with anything over 1866MHz, Would anything help?


VDD18 to 1.86v (over 1.83) , procODT beyond 34ohm and IOD beyond 1.05v , probably 1.1 AMD max overclocking voltage
Rest misses information, but also CAD_BUS 40-20-*30*-24

EDIT:
Probably also need to move away from SMU 56.34 - see (post) ZenTimings Screenshot


----------



## musician

ZealotKi11er said:


> I se so many people with 2000 but my 5950x cant post with anything over 1866MHz, Would anything help?


people with 2000 fclk have to use whea suppressor because there is hard wall at 1900 anyway. And some 5000x just can´t go above 1866. tbh, I would sell the cpu and try the silicon lottery with a new one


----------



## Akex

domdtxdissar said:


> We are mainly looking at CPU Game FPS where GPU don't matter..
> 
> That's also why i ran all my latest game-benchmarks in 1080p
> 
> 
> http://imgur.com/a/RwxpB0T
> 
> (few different games in there)
> 
> Also recorded the SotTR run 😇
> 
> 
> 
> 
> 
> Memorysettings used:
> View attachment 2529531


Didn't your AIDA have a bug? Isn't having more than 61K in bandwidth for 3800Mhz just impossible?


----------



## KedarWolf

Akex said:


> Didn't your AIDA have a bug? Isn't having more than 61K in bandwidth for 3800Mhz just impossible?


If you're using an older not updated version of AIDA it'll give you unrealistically high scores. :/


----------



## Taraquin

musician said:


> people with 2000 fclk have to use whea suppressor because there is hard wall at 1900 anyway. And some 5000x just can´t go above 1866. tbh, I would sell the cpu and try the silicon lottery with a new one


No, many of us don't have wheas above 1900 without supressor, but it's much easier with mATX and ITX vs ATX for some reason. ATX + 2 CCDs is a recipe for whea 19 :/


----------



## SneakySloth

The new win 11 update and chipset fixes the L3 Latency (its the same as Win 10 for me now) but it doesn't fix the bandwidth. It ranges from 1/3 the expected bandwidth to slightly higher.

Hopefully this isn't the only fix we get for this.


----------



## KedarWolf

Taraquin said:


> No, many of us don't have wheas above 1900 without supressor, but it's much easier with mATX and ITX vs ATX for some reason. ATX + 2 CCDs is a recipe for whea 19 :/


I preordered this, not mATX, but two DIMM, looks really good. 

Direct phase VRMs, no doublers I think.






MSI MEG X570S UNIFY-X MAX - 6 x Gen4 M.2, Direct 16+2 Phase 90A SPS, EXTREME OC, 2.5G LAN







www.msi.com





Waiting patiently for it to come into stock. 'sigh'


----------



## Dodgexander

Veii said:


> So much towards a broken testing config 🙊
> 
> You can get #10s away with more RTT_NOM, but they turn to #2's
> Not sure which to prioritise sadly
> I think #2s are less worse than 10s
> You'll figure it out
> Just saying #10s likely have to do with powering, #2 likely have to do with transition timings such as tRRD, tWTR, tRDWR, SD DD
> 
> Soo 10 could also be a CAD_BUS issue, while #2 can also be a vdimm issue
> Usually 0,6,2 appear on vdimm issues. Unsure about the 10 i forgot
> 
> What did you even get at the start ?


Any idea what 1 errors mean? Trying to get flat 14 but get about 12 errors in 1 and 2.
Using anta absolut.


----------



## Mach3.2

As far as I know there's currently no known correlation between the error numbers and the trigger for those error for anta's config. Anta basically said to change 1 setting at a time and run tests, that way you know exactly what timing is causing the error.


----------



## umea

musician said:


> people with 2000 fclk have to use whea suppressor because there is hard wall at 1900 anyway. And some 5000x just can´t go above 1866. tbh, I would sell the cpu and try the silicon lottery with a new one


not everyone needs to use whea suppressor i believe


----------



## musician

Taraquin said:


> No, many of us don't have wheas above 1900 without supressor, but it's much easier with mATX and ITX vs ATX for some reason. ATX + 2 CCDs is a recipe for whea 19 :/


It´s hard to believe. I have three! 5800X CPU. Two of them can do FCLK 1900, cl 14 or 13 no problem. But there is WHEA fest above 1900 no matter what. The last 5800X is even worse, there is max FCLK at 1866, WHEA fest coming at 1900 and above. I tried all the CPU in Asus Crosshair VIII Hero, Asus Crosshair VIII Dark Hero and MSI B550 Unify-X. The same result. 1/2 CCD does not matter at all, according to Veii there is just a bit more work with 2 CCDs units, but the OC capability is the same as 1 CCD. The 1 CCD units only advantage is a bit better ram latency.
I have tried numerous BIOS´s, settings, voltages etc etc, and just no, no matter what, there is the 1900 FCLK hard wall for the two and 1866 for the last one.


----------



## umea

My 5900x restarts on anything above 1900 regardless of the voltages I try. Just luck of the draw.


----------



## PhoenixMDA

@ KedarWolf & @domdtxdissar
Thx i think my NT can be enough, arround 200-250W is possible for CPU with my 3080 in 24/7, if i´m arround 150W is more as ok,
that is really good for the performance.
Then is my selected ram not useless like at ADL.


----------



## Taraquin

musician said:


> It´s hard to believe. I have three! 5800X CPU. Two of them can do FCLK 1900, cl 14 or 13 no problem. But there is WHEA fest above 1900 no matter what. The last 5800X is even worse, there is max FCLK at 1866, WHEA fest coming at 1900 and above. I tried all the CPU in Asus Crosshair VIII Hero, Asus Crosshair VIII Dark Hero and MSI B550 Unify-X. The same result. 1/2 CCD does not matter at all, according to Veii there is just a bit more work with 2 CCDs units, but the OC capability is the same as 1 CCD. The 1 CCD units only advantage is a bit better ram latency.
> I have tried numerous BIOS´s, settings, voltages etc etc, and just no, no matter what, there is the 1900 FCLK hard wall for the two and 1866 for the last one.


I have 3 whea 19 since April, and all of them occured due to idiotic voltage\cad etc settings. All your HKs are full ATX and it seems like mATX and ITX is much less likely to get wheas above 1900 fclk. If you look at the OC site, viritually all CPUs that do 4000 or above are 5600X or 5800X, so although there are a few dual CCDs that do it, they are in minority. My best bet on getting 2000 fclk+ is getting ITX or maybe some of the 2 dimm mATX, in your case you had no luck with Unify. Maybe the very few full ATX with 2 dimms can do it. Have you ever tried mATX or ITX?


----------



## KedarWolf

PhoenixMDA said:


> @ KedarWolf & @domdtxdissar
> Thx i think my NT can be enough, arround 200-250W is possible for CPU with my 3080 in 24/7, if i´m arround 150W is more as ok,
> that is really good for the performance.
> Then is my selected ram not useless like at ADL.


I'll run Cinebench and CPU-Z when I get home, see what they pull.


----------



## dante`afk

I have here 2 kits of 2x16gb F4-3200C14-16GVK

i mixed them by accident, how can I figure out which 2 sticks are one original kit? they all look the same in typhoon


----------



## KedarWolf

dante`afk said:


> I have here 2 kits of 2x16gb F4-3200C14-16GVK
> 
> i mixed them by accident, how can I figure out which 2 sticks are one original kit? they all look the same in typhoon


Consecutive serial numbers on the back sticker maybe?


----------



## musician

Taraquin said:


> I have 3 whea 19 since April, and all of them occured due to idiotic voltage\cad etc settings. All your HKs are full ATX and it seems like mATX and ITX is much less likely to get wheas above 1900 fclk. If you look at the OC site, viritually all CPUs that do 4000 or above are 5600X or 5800X, so although there are a few dual CCDs that do it, they are in minority. My best bet on getting 2000 fclk+ is getting ITX or maybe some of the 2 dimm mATX, in your case you had no luck with Unify. Maybe the very few full ATX with 2 dimms can do it. Have you ever tried mATX or ITX?


I don´t have problem to post at 2000 FCLK, I can post even 2133. I can show you passed TM5 1usmus at 2000, zero errors.
Then I run OCCT, CPU - Large - Extreme - Variable and then the WHEA fest begin  And nothing helps.


----------



## PhoenixMDA

KedarWolf said:


> I'll run Cinebench and CPU-Z when I get home, see what they pull.


THX but not necessary, for me is only the gaming watt important, because of usage GPU.
I know know that the power delivery is enough from my power supply.


----------



## Sam_Oslo

Taraquin said:


> My best bet on getting 2000 fclk+ is getting ITX or maybe some of the 2 dimm mATX, in your case you had no luck with Unify. Maybe the very few full ATX with 2 dimms can do it. Have you ever tried mATX or ITX?


I don't think the motherboard is such a limiting factor for FCLK that you would need a ITX/mATX. I believe the memory controller (and wrong voltage tweaks for it) is the biggest limiting factor of FCLK. So, a descent ATX motherboard should do the job.

I say this based on my own experience, because I have a pretty doll ATX MB when it comes to overclocking. My "Gigabyte B550 Vision D" is not an overclocking MB at all. It's actually a workstation, but (with a bit vSOC and CLDO VDDP tweaks), now it's behaving like a champ. I's not limiting my 5700G (with a good memory controller) at all, even at FCLK 2300.

EDIT: A 4 dimms ATX motherboard nay limit your vDimm for extreme overclocking, but a descant one won't limit your FCLK.


----------



## dante`afk

KedarWolf said:


> Consecutive serial numbers on the back sticker maybe?


no heatspreader, removed for waterblock


----------



## musician

Sam_Oslo said:


> I don't think the motherboard is such a limiting factor for FCLK that you would need a ITX/mATX. I believe the memory controller (and wrong voltage tweaks for it) is the biggest limiting factor of FCLK. So, a descent ATX motherboard should do the job.
> 
> I say this based on my own experience, because I have a pretty doll ATX MB when it comes to overclocking. My "Gigabyte B550 Vision D" is not an overclocking MB at all. It's actually a workstation, but (with a bit vSOC and CLDO VDDP tweaks), now it's behaving like a champ. I's not limiting my 5700G (with a good memory controller) at all, even at FCLK 2300.
> 
> EDIT: A descent 4 dimms ATX motherboard won't limit your FCLK.


You can´t compare memory overclocking capability of Zen 5000X vs 5000G like AT ALL. It´s just different chip, none IOD etc, hence it can overclock the memory to the sky...


Anyway, Veii said earlier that he don´t trust that anyone run stable 2000 or just above 1900 (?) FCLK without the WHEA suppressor. Considering my 3 samples, I don´t trust to anyone as well. The thing is I don´t want to use the suppressor, because it just hides the problem, but the problem is still there. It´s like cheating yourself. 
Soo, with the 1900 FCLK hard cap, the only way to increase the mem performance is milk latency, so flat 14, or CL13, and go for T1, eventually pure T1. Now I am starting to understand why many of you here are trying to find the T1 holy grail @ 1900FCLK and either the flat 14, tCL13 or some combination of it. Because it´s the only way.
So now I am with you.


----------



## KedarWolf

PhoenixMDA said:


> @ KedarWolf & @domdtxdissar
> Thx i think my NT can be enough, arround 200-250W is possible for CPU with my 3080 in 24/7, if i´m arround 150W is more as ok,
> that is really good for the performance.
> Then is my selected ram not useless like at ADL.


CPU-Z










Cinebench R23










Check out my CPU-Z multicore.


----------



## Sam_Oslo

musician said:


> You can´t compare memory overclocking capability of Zen 5000X vs 5000G like AT ALL. It´s just different chip, none IOD etc, hence it can overclock the memory to the sky...
> 
> 
> Anyway, Veii said earlier that he don´t trust that anyone run stable 2000 or just above 1900 (?) FCLK without the WHEA suppressor. Considering my 3 samples, I don´t trust to anyone as well. The thing is I don´t want to use the suppressor, because it just hides the problem, but the problem is still there. It´s like cheating yourself.
> Soo, with the 1900 FCLK hard cap, the only way to increase the mem performance is milk latency, so flat 14, or CL13, and go for T1, eventually pure T1. Now I am starting to understand why many of you here are trying to find the T1 holy grail @ 1900FCLK and either the flat 14, tCL13 or some combination of it. Because it´s the only way.
> So now I am with you.


I agree that "You can´t compare memory overclocking capability of Zen 5000X vs 5000G like AT ALL.", but you can compare the limiting factor of the motherboards. because the wiring, voltage, heat, etc of the MB would act exactly the same, and would have the same limiting factor.

Here, you can imagine the 5000G to be a 5000X with a better memory controller. Then based om my 5000G running at FCLK 2300 on a pretty doll ATX MB, one can argue that the 4 dimm ATX motherboard is not the limiting factor, but the CPU/memeory controller is. 

I haven't seen what Veii have said, but I guess he is explaining the limitings factor of 5000X CPUs. Do you mean that he is talking about limiting factor of ATX motherboards?. 

I don't know anything about WHEA suppressor.


----------



## umea

Sam_Oslo said:


> I don't think the motherboard is such a limiting factor for FCLK that you would need a ITX/mATX. I believe the memory controller (and wrong voltage tweaks for it) is the biggest limiting factor of FCLK. So, a descent ATX motherboard should do the job.
> 
> I say this based on my own experience, because I have a pretty doll ATX MB when it comes to overclocking. My "Gigabyte B550 Vision D" is not an overclocking MB at all. It's actually a workstation, but (with a bit vSOC and CLDO VDDP tweaks), now it's behaving like a champ. I's not limiting my 5700G (with a good memory controller) at all, even at FCLK 2300.
> 
> EDIT: A 4 dimms ATX motherboard nay limit your vDimm for extreme overclocking, but a descant one won't limit your FCLK.


G series can reach much higher fclks for various reasons, no reason to compare them.


----------



## umea

musician said:


> You can´t compare memory overclocking capability of Zen 5000X vs 5000G like AT ALL. It´s just different chip, none IOD etc, hence it can overclock the memory to the sky...
> 
> 
> Anyway, Veii said earlier that he don´t trust that anyone run stable 2000 or just above 1900 (?) FCLK without the WHEA suppressor. Considering my 3 samples, I don´t trust to anyone as well. The thing is I don´t want to use the suppressor, because it just hides the problem, but the problem is still there. It´s like cheating yourself.
> Soo, with the 1900 FCLK hard cap, the only way to increase the mem performance is milk latency, so flat 14, or CL13, and go for T1, eventually pure T1. Now I am starting to understand why many of you here are trying to find the T1 holy grail @ 1900FCLK and either the flat 14, tCL13 or some combination of it. Because it´s the only way.
> So now I am with you.


don't think flat 14 pure 1T is possible on 5900x/5950x with 32gb... well it could be possible, just no one has pulled it off yet as far as I know. we've all had to resort to 1T+ST (setup timings).


----------



## VPII

mongoled said:


> Glad to see you have made some headway. I have Windows 11 installed on a separate drive but I'm not paying too much attention to it until MS release patches that are shown to fix the outstanding issues with Ryzen CPUs.


Hi there, I finally got it working at 3800 with latest beta build Windows 11 for the L3 cache latency fix as well as with all core vcurve optimizer set to -25 minus 25 all core, but I learned to run the Ryzen Dram Calculator bench first otherwise it would still fail.


----------



## PhoenixMDA

dante`afk said:


> no heatspreader, removed for waterblock


Then not possible, what you can make is test high frequency every stick, do the best together for Kit 1. 
Or for 2 good kit do a better and a worse stick together, so in the most cases are the kit´s.


----------



## Blameless

musician said:


> It´s hard to believe. I have three! 5800X CPU.


Three is not a large sample.

None of my 5800Xes (have also had three) was completely WHEA free above 1900FCLK in any board (including two ITX/DTX boards), with any combination of settings, but it's not hard to believe there are parts that do better.



dante`afk said:


> I have here 2 kits of 2x16gb F4-3200C14-16GVK
> 
> i mixed them by accident, how can I figure out which 2 sticks are one original kit? they all look the same in typhoon


If the serial numbers or SPD date code don't reveal which were sold together, you're out of luck.

Not that it should matter, unless you think you've done something to one kit. The mean difference between DIMMs within one kit is likely no higher than the mean difference between DIMMs of different kits of the same SKU/bin. You could well test each stick individually and find that sticks from different kits are better matches for eachother.


----------



## Taraquin

musician said:


> I don´t have problem to post at 2000 FCLK, I can post even 2133. I can show you passed TM5 1usmus at 2000, zero errors.
> Then I run OCCT, CPU - Large - Extreme - Variable and then the WHEA fest begin  And nothing helps.


As I said, the problem seems to be much more likely with fullsize ATX/4 dimm. Maybe the longer/more complex traces is the issue. If you don't experience whea 19 except for occt then why don't you use 4000+? If whea only occurs in unrealistic liads, but never in games etc, then there is no problem in my opinion  I have also run occt in various configs, but haven't gotten whea so far.


----------



## Audioboxer

Playing around a bit more with my "tightest" profile, seems VSOC was happy to come down from 1.15v to 1.125v and CsOdtDrvStr was happy to drop to 20 from 24.


----------



## mongoled

Veii said:


> So much towards a broken testing config 🙊
> 
> You can get #10s away with more RTT_NOM, but they turn to #2's
> Not sure which to prioritise sadly
> I think #2s are less worse than 10s
> You'll figure it out
> Just saying #10s likely have to do with powering, #2 likely have to do with transition timings such as tRRD, tWTR, tRDWR, SD DD
> 
> Soo 10 could also be a CAD_BUS issue, while #2 can also be a vdimm issue
> Usually 0,6,2 appear on vdimm issues. Unsure about the 10 i forgot
> 
> What did you even get at the start ?


Oh, I dont remember what the error code was, just that it occurred as soon as the TM5 starts to run, so I quickly closed it.

I need to return to this testing some time soon as some work has arrived that needs getting done before I can continue.

Should be able to get back to this later today


----------



## Sam_Oslo

umea said:


> G series can reach much higher fclks for various reasons, no reason to compare them.


Yeah, I agree, we can't compare them, becouse they have totally different memory controller. But we can compare the limiting factor of the motherboard. 

I'm arguing that ATX motherboard is not the limiting factor of FCLK, neither for G or X series. But the memory controller (or wrong voltage taeweks for memory controller) is the main limiting factor of FCLK, both for G and X series.


----------



## Sam_Oslo

The ATX motherboard/4 dimm may limit very high FCLK of G-series, but a descent ATX shouldn't be a limiting factor for X-series at all. Because many G-series are running at FCLK 2200+ on many different motherboards. Mine is running at FCLK 2300 on a pretty doll ATX that is not a overclocking moterboard at all, it's actually a workstation.


----------



## MrHoof

umea said:


> don't think flat 14 pure 1T is possible on 5900x/5950x with 32gb... well it could be possible, just no one has pulled it off yet as far as I know. we've all had to resort to 1T+ST (setup timings).


I saw on so far here in this thread on page 676 @whocares7. Well its a flat 15 but pure 1T.


----------



## Bix

Veii said:


> tCKE 9 is for 3800, try 11 - and try maaybe to remove AddrCmdSetup
> 
> Doublecheck if both A1 and B1 or A2 have the same tPHYRDL ~ in this case all 4 slots
> Drop procODT oncce, you should be able to - and compare with multiple rounds if Latency varies over 0.2ns - over 0.3ns deviance ~ trow away the first result
> Same goes for Write, it shouldn't vary more than 5MB/s, although dual CCD could maybe not hold full bandwidth
> 
> You don't need SETUP timings for SR kits, you should be able to handle this only with tCKE and maaybe 4-4-18 (if it works for you, try it out)


Thanks for the help! 

Changed tCKE to 11 and removed AddrCmdSetup - booted into windows but get BSOD soon after.
Same with ProcODT down a step to 34.3
Couldn't post at all with 4-4-18 setup timings

Back with AddrCmdSetup at 56 I get tPHYRDL 28 on all 4 dimms (was 26 on all 4 at 2t)

Run to run variance in Aida is WAY higher than that for me... here are first 5 results after changing tCKE to 11

ReadWriteCopyLatency62429617825952954.162611618095959054.562585616485952954.362660618835953354.362073617795958054.4

I always thought this kind of variance was normal as I had similar with my 3600 on B450 but been using the same windows installation for years so that might be to blame...


----------



## Taraquin

Sam_Oslo said:


> Yeah, I agree, we can't compare them, becouse they have totally different memory controller. But we can compare the limiting factor of the motherboard.
> 
> I'm arguing that ATX motherboard is not the limiting factor of FCLK, neither for G or X series. But the memory controller (or wrong voltage taeweks for memory controller) is the main limiting factor of FCLK, both for G and X series.


It seems many ATx boards also can run 2000+ fclk on X-series, BUT few of them without whea 19. mATX and ITX seems less likely to get whea 19.


----------



## Sam_Oslo

Taraquin said:


> It seems many ATx boards also can run 2000+ fclk on X-series, BUT few of them without whea 19. mATX and ITX seems less likely to get whea 19.


As far as I know, the #19 is not a memory OC related issue, and you can't see it as a lower performance with CPU Benchmarks ether. So, it's not a CPU nor IMC issue.

It's rather a PCH (I/O issue). So you may have a point with ITX/mATX when it comes to #19.


----------



## ManniX-ITA

domdtxdissar said:


> lol I'm using newest version


Clearly the bandwidth is not right for 3800 MHz, well over the theoretical limit.
Is AIDA in general problematic with Win11?
Do you have maybe also a Win10 to boot to get an AIDA screenshot?
I'm thinking about switching as well to CL13 
But last time I tried the temperature bump was overkilling.


----------



## ManniX-ITA

Sam_Oslo said:


> As far as I know, the #19 is not a memory OC related issue, and you can't see it as a lower performance with CPU Benchmarks ether. So, it's not a CPU nor IMC issue.


I had WHEA 19 also related to memory OC; too low VDDG and/or VSOC for the aggressive timings and the result was low CPU-z and AIDA scores.


----------



## Sam_Oslo

ManniX-ITA said:


> I had WHEA 19 also related to memory OC; too low VDDG and/or VSOC for the aggressive timings and the result was low CPU-z and AIDA scores.


The "low VSOC for the aggressive timings" will of course result in low scores in CPU-z, AIDA, and other benchmarks too. Because it's unstable. An unstable overclock would perform poorely even without WHEA 19 too. So, one may ask, is it raelly reltaed to WHEA 19? 

I haven't instigated this aspect of the issue and won't rule out your findings, it may still be the case. But to me, the WHEA 19 is more of a PCH (I/O issue).


----------



## ManniX-ITA

Sam_Oslo said:


> An unstable overclock would perform poorely even without WHEA 19 too. So, one may ask, is it raelly reltaed to WHEA 19?


WHEAs 19 are reports of correctable errors, could be almost anything related to the platform.
The unstable OC could just result in poor performances without any WHEA 19.
But it's not the opposite that the unstable OC is related to the WHEA 19, they are not a root cause itself.


----------



## Luggage

ManniX-ITA said:


> Then it's normal, the pure SMU command takes around 100-150ms, plus HWInfo reading the data.
> Below 300 is prone to fail.


@XPEHOPE3 

333ms polling, no zentmiings. the only thing that could mess up things is superpi is running realtime - but it's sc...

Hmm unless benchmate is messing things up?

So I get the zero-ing at one time and the "ob" unrelatedly later. No recording of any volatge spike though.



http://imgur.com/a/IrGb3vV


----------



## Taraquin

As for going from 3800 to 4000-4200 you generally must loosen timings a bit and IOD requires a bit more power so the performancegain is quite small. For me it is at best 1-2% in certain scenarios going from 3800cl15 1T to 4000cl16 1T, but 4000cl16 needs less ram voltage and my ram overheats easily above 1.45V so therefore I stick with 4000cl16. For those not being able to do 3800+ whea free, don't worry, unless you plan on winning the latency-contest in aida64, getting cl14 or 15 and tuned subs on 3800 is top notch


----------



## Sam_Oslo

ManniX-ITA said:


> The unstable OC could just result in poor performances without any WHEA 19.


Yeah, exactly. This was actually my point. But if you agree with this point, then how can you conclude that your "low CPU-z and AIDA scores" are related to WHEA 19? How did you came to this conclusion?

So we are back to the score one. I can still can claim that; The WHEA 19 is not a CPU nor IMC issue, and you can't see it as a lower performance with CPU Benchmarks either. But it's rather a PCH (I/O issue). Unless you can explain how those "low CPU-z and AIDA scores" are related to WHEA 19.


----------



## ManniX-ITA

Sam_Oslo said:


> how can you conclude that your "low CPU-z and AIDA scores" are related to WHEA 19? How did you came to this conclusion?


Because fixing the voltages brought back the correct scores and I didn't get any more WHEA 19.



Sam_Oslo said:


> The WHEA 19 is not a CPU nor IMC issue


WHEA 19 is not a CPU and not IMC issue and neither a PCH issue 
It's an error event and it can be raised by either one of those issues or something else.
You can get it or not from "bad" almost everything related to the CPU.


----------



## Akex

domdtxdissar said:


> lol I'm using newest version, back to your cage
> No point to comment on things if you don't know what your talking about


It may be a mistake on my part because my English is not really the best, but it seems that your message is aggressive and is moving, or is it me who misunderstands your proposals?
Anyway, your test is wrong, it's pure and simple mathematics, you are in dual channel, so your speeds are those of a kit running above 5000Mhz.

@Veii Can you share the calculation formula please?


----------



## Sam_Oslo

ManniX-ITA said:


> Because fixing the voltages brought back the correct scores and I didn't get any more WHEA 19.


 As I have mentioned before, I haven't investigated this side of the matter and won't rule out your findings. And now you have an explanation, so it may be the case. It would be interesting to recreate the issue and investigate it. 



ManniX-ITA said:


> WHEA 19 is not a CPU and not IMC issue and neither a PCH issue


I have said it from the first post, and I'm happy that we can now agree that; the "WHEA 19 is not a CPU and not IMC issue" . I mean it's a more of a PCH I/O issue, than CPU and IMC issues. But as you mentioned, it's not limited to this either.

But the original point that started this discussion, still remains. How much of WHEA 19 errors is the effect of high FCLK? and why mATX and ITX seems less likely to get whea 19?


----------



## ManniX-ITA

Sam_Oslo said:


> How much of WHEA 19 errors is the effect of high FCLK? and why mATX and ITX seems less likely to get whea 19?


Eh... this is the one million dollar question 
All the WHEA 19 related to high FLCK are not payload error but control errors and share some common data like MciStat and MciMisc.
There are many theories; mine/ours mostly pointing towards desync issues which are triggering some components to flood the bus with this error.
The PCH and everything else connected to it can contribute so it's not unlikely that the small form factor can help in this case.


----------



## Veii

Dodgexander said:


> Using anta absolut.


Anta listed these in 3 categories
The way the config works, doesn't allow for correct pinpointing


Bix said:


> Thanks for the help!
> 
> Changed tCKE to 11 and removed AddrCmdSetup - booted into windows but get BSOD soon after.
> Same with ProcODT down a step to 34.3
> Couldn't post at all with 4-4-18 setup timings
> 
> Back with AddrCmdSetup at 56 I get tPHYRDL 28 on all 4 dimms (was 26 on all 4 at 2t)
> 
> Run to run variance in Aida is WAY higher than that for me... here are first 5 results after changing tCKE to 11
> 
> ReadWriteCopyLatency624296178259529*54.1*62611618095959054.562585*61648**59529*54.362660618835953354.362073617795958054.4
> 
> I always thought this kind of variance was normal as I had similar with my 3600 on B450 but been using the same windows installation for years so that might be to blame...


Honestly, it looks fine
Write is except for the 3rd test, within margin
the 0.5 to 0.3 is within margin of error, the 0.1 to 0.5 is not - but this 0.1 could be a fluke , hence you should trow away the first test
I've marked the irregulars

Honestly, switching to another command rate, requires a confirmation that the test even passes
Else your readouts have no weight to them


Taraquin said:


> It seems many ATx boards also can run 2000+ fclk on X-series, BUT few of them without whea 19. mATX and ITX seems less likely to get whea 19.





Veii said:


> But yet close to everybody (i still think everybody) has to be able to run 2000 FCLK with ease





Akex said:


> @Veii Can you share the calculation formula please?


You can easily copy it
Maximum bandwidth for MCLK is
((MT/s*2)*64)/8


> The memory clock for DDR3-1600 is 800Mhz, the data transfer rate is 2x due to DDR, the memory controller data path width to the DIMM is 64bits wide, which yields 800MHz x 2 x 64bits = 102.4Gbps or 12.8GB/s.


Unless you mean something else


----------



## domdtxdissar

ManniX-ITA said:


> Clearly the bandwidth is not right for 3800 MHz, well over the theoretical limit.
> Is AIDA in general problematic with Win11?
> Do you have maybe also a Win10 to boot to get an AIDA screenshot?
> I'm thinking about switching as well to CL13
> But last time I tried the temperature bump was overkilling.


Aida only (tries to) measure performance in Aida itself, which is not always have a good correlation to "real world performance", should not be taken too seriously..














Mistakes was made on the last screen.. (didnt notice r15 was hiding TM5 mainwindow)
Reason to show valid benchmate -> no trickery with windows timers


----------



## ManniX-ITA

domdtxdissar said:


> Aida only (tries to) measure performance in Aida itself, which is not always have a good correlation to "real world performance", should not be taken too seriously..


Yes it's only for my reference... but I don't understand, how's possible 85/80/85 GB/s?
Also on Windows 10??
It's just unrealistic or am I missing something?


----------



## domdtxdissar

ManniX-ITA said:


> Yes it's only for my reference... but I don't understand, how's possible 85/80/85 GB/s?
> Also on Windows 10??
> It's just unrealistic or am I missing something?


Yes screenshot from above are using win10 running AIda v 6.33.5700

Zen2 measured over theoretical memory limit all the time thanks L3 cache, same principle at work here, if nudged correctly, hydra can also make impossible numbers come true.. But this is only in Aida64 as ive said before.. Latency numbers are also not achievable for normal dual ccd users.


AIda v 6.50.5800 @ win11








AIda v 6.33.5766 *beta *@win10 (we were talking about this on a other forum)








Friend from 1usmus discord running a gigabyte+5950x system, AIda v 6.33.5700 @ win11 (pre L3 fix)








Windows version are not the culprit here


----------



## ManniX-ITA

domdtxdissar said:


> hydra can also make impossible numbers come true..


Ahhhh that's the culprit, Hydra 
Right, I've also got a 70 something while testing it, forgot it.
Thanks!


----------



## mongoled

umpth, not quite there

😂😂


----------



## Taraquin

mongoled said:


> umpth, not quite there
> 
> 😂😂
> 
> View attachment 2529850


That`s an insanely low ProcODT for dual rank!


----------



## umea

@GSKILL SUPPORT are you guys done with DDR4 bins? i guess it's too late, but for DDR5 if you could make good non-rgb heatsinks that would be awesome. Thick aluminum with large fins would be sick.


----------



## Audioboxer

Taraquin said:


> That`s an insanely low ProcODT for dual rank!


Its not DR, its SR 4x8GB lol.

But it IS and insanely good overclock for 4x8GB!


----------



## mongoled

Re, ProcODT, always been able to run it at 28 ohms, im guessing this has to do with my motherboard/CPU sample....



Well I re-ran the test without rebooting and it passed.

But all is not well....

The slight bump up to 1933 FCLK is not performing as it should as seen in LinpackXtreme results, also Y-Cruncher crashing at tests N32. Think the small bump of 33 mhz is going to need to me to re-investigate IOD/vSOC/PLL 1.8v which are probably going to need an increase in voltage.

At least ive found a balance for Rtt with 1.7v vDIMM



** EDIT **
Its not IOD, but either vSOC or PLL 1.8v, I increased both of those two notches and LinpackXtreme is where it should be and Y-Cruncher is not insta crashing on N32


----------



## Bix

Veii said:


> Honestly, it looks fine
> Write is except for the 3rd test, within margin
> the 0.5 to 0.3 is within margin of error, the 0.1 to 0.5 is not - but this 0.1 could be a fluke , hence you should trow away the first test
> I've marked the irregulars
> 
> Honestly, switching to another command rate, requires a confirmation that the test even passes
> Else your readouts have no weight to them












This is where I'm at now - tCKE changed to 11 and ProcODT lowered one step from 36.9 to 34.3 as suggested but now I'm getting a single error.
Any suggestions? Thanks again for taking the time.


----------



## PJVol

Sam_Oslo said:


> The WHEA 19 is not a CPU nor IMC issue, and you can't see it as a lower performance with CPU Benchmarks either


1) Surely it is (cpu) and 2) yes, I can.


----------



## Veii

Bix said:


> View attachment 2529886
> 
> 
> This is where I'm at now - tCKE changed to 11 and ProcODT lowered one step from 36.9 to 34.3 as suggested but now I'm getting a single error.
> Any suggestions? Thanks again for taking the time.


If you've lowered Proc & RTT_NOM is the minimum, then you just lack voltage
Depends on when this error came
I don't know if RTT_WR /2 could run for you
But give 3-2-3 a try and later drop to 3-2-2 or 3-1-2
They should function well enough at this frequency ~ just depends which PCB type you own

At worst 10mV bump and RTT_NOM /6, and the thing should've been resolved.
tCKE and SETUP timings are MCLK dependent ~ you should not copy 3800 settings upwards, as that might not function

Idk yet if 56-0-0 is fine for 4000MT/s, but tCKE 11 is and so is 13 for 4200 (dual rank included)
======================================================================================








^ XMP, just one step down to prevent package throttle. Only proof of RTT+CAD_BUS+ProcODT stability

I think i've nailed down the issue with dual rank now and have couple of RTT combinations to use
AddrCmdDrvStr has to be the lowest possible. This platform / boards have path length issues with dual rank. We need the best signal integrity we can get
1T by FW automatically changes it to 26-26 where distance is not reaching.
AddrCmdDrvStr pushes strengthness up, but there is i feel an architecture design issue for the traces. Soo it instantly fails
60-20-30-24 is usable and will help, but it does not fix the core issue of signals vanishing on 26-26 for this PCB
This should explain it well ~ without having to write it twice









*Advices:*

run 60-20-X-X
run over 36.9ohm procODT (for now)
give 3-2-3 or 3-1-2 or 3-2-2 a try after going beyond 1.52v (XMP for this is 1.5v)
drop down to 3600MT/s with any timings on pure 1T and fix powering as best as you can for it not to insta hard-shutdown









This is an expected result you want to see
It will spam #6 and #0, also #12 and #2
But it has to keep up stability on being tPHYRDL 26-26
Slightly off value on CAD_BUS or RTT, will result in an instant BSOD

You can run tCKE 7 or tCKE 1 at 3600MT/s to finetune it. It doesn't matter
You can use this also to probe from 1-32 values on first two AddrCmdSetup & CsOdtSetup. Either it's instant BSOD or it will keep up stability
Keep CAD_BUS 60-20-X-X , 120 runs, but we have an issue of badly designed traces here. We want as best signal integrity as possible
3600 & 4200 experience the same issue, and have no correlation to timings.
* maybe tCWL playing can force 28-28 1T, but i need more time to invest with stupid ideas.
Currently i'm out of attempts/ideas and can just title the clear that it is. A trace design issue & FW IO-L predication issue

EDIT:
While slowing down send CLK is a methodic
Same as just running GDM likely is a methodic
Both are not fixes ~ but just going around the problem.
We have to see how this is fixable, but the issue i don't think is any of the dimms ~ but on AMDs enforced board path-design targets.
1T 28-28 is technically a "fix" , but also can be branded as "going around the problem" ~ "hiding the problem".
Which is a clear data-path trace-length design issue. . .


----------



## Frosted racquet

@Veii Thanks for posting your findings regarding Dual Rank G.Skill RAM. If you look at my earlier post I've been having nothing but issues with F4-3600C16D-32GVKC on MSI B550 ITX board.
I'll experiment with your settings when I get home in a week; at this point with some previous suggestions I can sometimes pass TM5 and sometimes fail with 1 error (usually #4 and #0) on 1usmus profile


----------



## Veii

Frosted racquet said:


> F4-3600C16D-32GVKC


Thaiphoon Burner readout pls


----------



## Frosted racquet

Here you go


----------



## Veii

Frosted racquet said:


> Here you go


Hmm Hynix CJR , but same PCB ~ if readouts are to believe
Same JEDEC Categorization too.
Ty~








Only worry about voltage to RTT_NOM
At worst you need to make out of 323 , a 523 or 522 (near 1.4vVDIMM)
Need to try, and report back with a zentimings screenshot (hence tPHYRDL might be different ~ check both channels)


----------



## Frosted racquet

Will check in a week or two when I get home (currently only have TeamViewer access). Thanks again.


----------



## umea

Oh are you on 4266 17 18 18 38 kit Veii? That's the one I have too 

Edit: you are, didnt see your last post. interested to see what you can do with your kit on the 5900x.


----------



## Veii

umea said:


> Oh are you on 4266 17 18 18 38 kit Veii? That's the one I have too
> 
> Edit: you are, didnt see your last post. interested to see what you can do with your kit on the 5900x.


5900X parts arrive next week somewhere mid-week ~ EVGA Dark +Zen3D build had to get canceled sadly
I'm only allowed to touch CPU+RAM+MB (barely MB as it's needed for ThunderBolt 3) this time. Sadly not really do much with a 6800XT. Warranty afraid people :'(

Dual CCD people seem to constantly be PPT limited without much of a reason
I'll see if they'll give me time till the 7th of November, else might only have 3-4 days with it , which includes stress-testing & building

4267 one so far was told to be the most special one out of my supporter/lender's batch
3200C14-14 2021 performed strongly, this here did for him fail JEDEC too on some intel boards
My specific one has ECC enabled for some bizarre reason ~ but idk fully what ASRock uses currently for memory training settings. They work well, but take a long time to train

EDIT:
it's generally nice to see RTT_WR /1 functioning
Sadly didn't get to experience High-Z mode, didn't post on all of these attempts. Maybe i'll figure it out. Curious how ZenTimings reports that one

EDIT2:
But there is a 5950X build too in plan @ November
On that one i have full freedom  ~ just can't promise much playtime, hence Zen3D is soon out
I had my fun time with Vermeer and held my promise. Let's see who will maintain Zen3D this time


----------



## Taraquin

5800X with Zen3D is my dream, don't need extras cores since I mostly game, but slightly better ram oc and latency vs 2 ccds vs welcome


----------



## Luggage

Taraquin said:


> 5800X with Zen3D is my dream, don't need extras cores since I mostly game, but slightly better ram oc and latency vs 2 ccds vs welcome


With mature silicon boosting 200 more


----------



## Bix

Veii said:


> If you've lowered Proc & RTT_NOM is the minimum, then you just lack voltage
> Depends on when this error came
> I don't know if RTT_WR /2 could run for you
> But give 3-2-3 a try and later drop to 3-2-2 or 3-1-2
> They should function well enough at this frequency ~ just depends which PCB type you own
> 
> At worst 10mV bump and RTT_NOM /6, and the thing should've been resolved.
> tCKE and SETUP timings are MCLK dependent ~ you should not copy 3800 settings upwards, as that might not function
> 
> Idk yet if 56-0-0 is fine for 4000MT/s, but tCKE 11 is and so is 13 for 4200 (dual rank included)


Tried 3-2-3, 3-2-2 and 3-1-2 but couldn't post with any of them. I'm on A0 pcb:
EDIT: My bad, apparently they're custom A2









10mV bump to VDIMM and RTT_NOM /6 passed though (tPHYRDL is still 28 on all 4 slots).










Tried again without using AddrCmdSetup 56 but same BSOD as before as soon as I try to launch Aida.


----------



## MrHoof

Veii said:


> While slowing down send CLK is a methodic
> Same as just running GDM likely is a methodic
> Both are not fixes ~ but just going around the problem.
> We have to see how this is fixable, but the issue i don't think is any of the dimms ~ but on AMDs enforced board path-design targets.
> 1T 28-28 is technically a "fix" , but also can be branded as "going around the problem" ~ "hiding the problem".
> Which is a clear data-path trace-length design issue. . .


Not saying your are wrong but maybe optimem on asus motherboards isnt a marketing joke. Dunno how they would get around the enforced desing targets tho.

ASUS OptiMem: Careful routing of traces and vias to preserve signal integrity for improved memory overclocking
The only people I saw so far with DR dimms @3800mhz 1T without setup timings wohcare7(dark hero) and me (x570i) both on asus boards.


Spoiler: 1T















procODT works for me from 28.2-40ohm didnt test any higher procODT so far. RTT does not have any wiggle room at 7/3/3 for me and whocares7 was running 7/2/5. For cad bus I have similar experience 40-20-30-24 and 40-20-24-24 are the best options but clkdrv at 60 could help at thoose speeds you push 4200mhz+.
For who care7 even 30-20-20-20 was stable. This is anta abosult tho would not be suprised if it does not hold all stresstests.


Spoiler: whocares7 screenshot















edit: Thaiphoon also reads alteast mine and Auidoboxers kits also as B1. And I also did a mbist test like you said it takes 1minute+ to boot with it enabled.


----------



## umea

I think DR Pure 1T is more doable on 5800x. Bloax also got pure 1T running with 32gb 3800 flat 14 on his.

I'll see if I can fiddle around with it more too. Seeing DR Pure 1T on a 5900x just got me inspired.


----------



## umea

Veii said:


> 5900X parts arrive next week somewhere mid-week ~ EVGA Dark +Zen3D build had to get canceled sadly
> I'm only allowed to touch CPU+RAM+MB (barely MB as it's needed for ThunderBolt 3) this time. Sadly not really do much with a 6800XT. Warranty afraid people :'(
> 
> Dual CCD people seem to constantly be PPT limited without much of a reason
> I'll see if they'll give me time till the 7th of November, else might only have 3-4 days with it , which includes stress-testing & building
> 
> 4267 one so far was told to be the most special one out of my supporter/lender's batch
> 3200C14-14 2021 performed strongly, this here did for him fail JEDEC too on some intel boards
> My specific one has ECC enabled for some bizarre reason ~ but idk fully what ASRock uses currently for memory training settings. They work well, but take a long time to train
> 
> EDIT:
> it's generally nice to see RTT_WR /1 functioning
> Sadly didn't get to experience High-Z mode, didn't post on all of these attempts. Maybe i'll figure it out. Curious how ZenTimings reports that one
> 
> EDIT2:
> But there is a 5950X build too in plan @ November
> On that one i have full freedom  ~ just can't promise much playtime, hence Zen3D is soon out
> I had my fun time with Vermeer and held my promise. Let's see who will maintain Zen3D this time


Excited regardless. Really want to see what the EVGA dark is capable of but... those things are really hard to come by in general right now.

What did you mean by them being special from your lender's batches? I assume they pre-binned them for you.
Also do you have any good resources/posts on what memory training is and how to make use of it?


----------



## XPEHOPE3

Luggage said:


> So I get the zero-ing at one time and the "ob" unrelatedly later. No recording of any volatge spike though.


That ob reading was also strange. All the clocks were exactly 4000MHz apart from Core0 (5000MHz), but effective clocks were 0MHz for every core apart from Core0 (5000MHz) and Core5 (6593.6MHz). Since those are your two best CPPC cores, I think SuperPi just got rescheduled from one to another exactly before the readout time. Maybe, effective clocks are "computed" by some math algorithm which involves computing division (with time in denominator) and is unstable when time is near zero (because of too recent switch from core0 to core5) due to limited HW precision. Although a speculation, no voltage ob suggests math effects rather than an actual problem.


Veii said:


> ^ XMP, just one step down to prevent package throttle. Only proof of RTT+CAD_BUS+ProcODT stability


Thank you for the findings! What VDIMM was used for the stable screenshot?


----------



## Luggage

XPEHOPE3 said:


> That ob reading was also strange. All the clocks were exactly 4000MHz apart from Core0 (5000MHz), but effective clocks were 0MHz for every core apart from Core0 (5000MHz) and Core5 (6593.6MHz). Since those are your two best CPPC cores, I think SuperPi just got rescheduled from one to another exactly before the readout time. Maybe, effective clocks are "computed" by some math algorithm which involves computing division (with time in denominator) and is unstable when time is near zero (because of too recent switch from core0 to core5) due to limited HW precision. Although a speculation, no voltage ob suggests math effects rather than an actual problem.
> 
> Thank you for the findings! What VDIMM was used for the stable screenshot?


Actually my main suspect now is benchmate because I have some sus sc readings with my scores, don’t know and can’t set polling intervals. And it has monitoring hooks so ofc any mixing of monitoring apps, like you said zentimings and HWinfo64, is a bad idea.


----------



## Mach3.2

Went ahead and ordered a kit of these, not too sure what to expect other than it's 2*16GB dual rank B die. 

Cost per GB is roughly the same as the Patriot Viper Steel 4400MHz CL19 kit(after applying the $15 off coupon).


----------



## hazium233

I don't believe the vendors actually program the pcb type, so since it isn't there it can't be read. Actually they don't program die stepping either which is why the die is also a guess most of the time. For G.Skill, use the 042 code on the label, Corsair use version number for die. PCB you have to look.


----------



## Beginner1257

Taraquin said:


> 5800X with Zen3D is my dream, don't need extras cores since I mostly game, but slightly better ram oc and latency vs 2 ccds vs welcome


Hello 
I am worried that only 5900/5950 gets the 3D cache. 5600/5800 will be updated to the "XT", but with the same amount of cache (32MB).
Lets hope I am wrong.


----------



## Audioboxer

Wonder what happened with AGESA 1.2.0.4? AMD pretty much pushed it out buggy and now it seems to have gone AWOL 🤣


----------



## Luggage

Audioboxer said:


> Wonder what happened with AGESA 1.2.0.4? AMD pretty much pushed it out buggy and now it seems to have gone AWOL 🤣


Yea I just lost all my saved bios profiles and looked around for new betas but that 1203c-1203c-1204test-1203c timeline is… strange


----------



## Chaib

Hello guys 

I have been reading through a lot of this thread but im kinda overwhelmed by the amount information especially by @Veii

For reference I am running 4x8 Viper Steel 4400 A2 PCB and trying to get 3800 flat 14 idealy 1T stable. This config seems to be really hard to stabilize from what ive heard but ive not given up yet.










I have tried up to 1,58V and a dozen of combinations of ProcODT and RTTs but nothing seems to make a difference to stability or at least I didnt recognize any pattern yet. No Matter what I get Errors #6 within the first 20s of TM5.
Did I miss something important? Or is it simply not enough Vdimm? My current stable config is Flat 15s with 1,43V on the same sticks.

Id be thankful for any help


----------



## Requiem4u

Chaib said:


> Hello guys
> 
> I have been reading through a lot of this thread but im kinda overwhelmed by the amount information especially by @Veii
> 
> For reference I am running 4x8 Viper Steel 4400 A2 PCB and trying to get 3800 flat 14 idealy 1T stable. This config seems to be really hard to stabilize from what ive heard but ive not given up yet.
> 
> View attachment 2530020
> 
> 
> I have tried up to 1,58V and a dozen of combinations of ProcODT and RTTs but nothing seems to make a difference to stability or at least I didnt recognize any pattern yet. No Matter what I get Errors #6 within the first 20s of TM5.
> Did I miss something important? Or is it simply not enough Vdimm? My current stable config is Flat 15s with 1,43V on the same sticks.
> 
> Id be thankful for any help


Try 14-14-15-14. Then you know if it is tRCDRD.


----------



## Chaib

Requiem4u said:


> Try 14-14-15-14. Then you know if it is tRCDRD.


yea it runs 14s and trcd 15 with basically any random combination of settings as long as im above 1,48V Vdimm. But does that mean trcdrd 14 with reasonable voltage is a lost cause?


----------



## GSKILL SUPPORT

umea said:


> @GSKILL SUPPORT are you guys done with DDR4 bins? i guess it's too late, but for DDR5 if you could make good non-rgb heatsinks that would be awesome. Thick aluminum with large fins would be sick.



Not sure with DDR4.

For DDR5, Trident Z5 will have silver and black heat spreader variants that do not have RGB LEDs. 

Trident Z5 Family DDR5 Memory


----------



## KedarWolf

GSKILL SUPPORT said:


> Not sure with DDR4.
> 
> For DDR5, Trident Z5 will have silver and black heat spreader variants that do not have RGB LEDs.
> 
> Trident Z5 Family DDR5 Memory


Says RGB right on the heat spreaders. :/


----------



## umea

KedarWolf said:


> Says RGB right on the heat spreaders. :/


Look at the back two, the top of the heat spreader is black instead where the front two have RGB.



GSKILL SUPPORT said:


> Not sure with DDR4.
> 
> For DDR5, Trident Z5 will have silver and black heat spreader variants that do not have RGB LEDs.
> 
> Trident Z5 Family DDR5 Memory


That's exactly what I'm looking for thanks. Very excited to see the progression of bins.


----------



## hazium233

Chaib said:


> yea it runs 14s and trcd 15 with basically any random combination of settings as long as im above 1,48V Vdimm. But does that mean trcdrd 14 with reasonable voltage is a lost cause?


Probably so. I guess you could try sacrificing a goat, but tRCD has walls and it is still possible some memory controller, board, pcb combinations aren't going to do < 7.5ns.


----------



## KedarWolf

umea said:


> Look at the back two, the top of the heat spreader is black instead where the front two have RGB.
> 
> 
> That's exactly what I'm looking for thanks. Very excited to see the progression of bins.


Oh yes, my bad.


----------



## Audioboxer

Chaib said:


> yea it runs 14s and trcd 15 with basically any random combination of settings as long as im above 1,48V Vdimm. But does that mean trcdrd 14 with reasonable voltage is a lost cause?


Probably. tRCDRD doesn't really scale with voltage, it'll expect a voltage baseline and then just work in most cases where the sticks can do it.

Good way to check things with 4x8GB is run with 2x8GB or even test each DIMM individually.


----------



## mongoled

Audioboxer said:


> Probably. tRCDRD doesn't really scale with voltage, it'll expect a voltage baseline and then just work in most cases where the sticks can do it.
> 
> Good way to check things with 4x8GB is run with 2x8GB or even test each DIMM individually.


@Chaib 

You need to do this first of all to determine each pair independently from each other.

1.5v is toooo little for these memory modules when pushing tCL @14.

As others have explained tRCDRD does not scale with voltage once it hits a wall, so if you dont want to test the dimms in pairs then you need to run tRCDRD @15, raise vDIMM to 1.55v, put a fan over them.

And report back the results ...


----------



## ioannis91

Guys how can we make 12 and 2 errors go away in the first cycle? I am trying for 3800 15-15-15-30-45 and I can't get them to go away. Only thing that helped was NOM at 34 and RTTwr at the lowest setting. Those two decreased the errors to 1x error 12 and 2x error 2 but whatever I tried failed and produced more. I tried vsoc and procodt, and various drive strength, vdimm also to no avail..


----------



## ManniX-ITA

ioannis91 said:


> Guys how can we make 12 and 2 errors go away in the first cycle? I am trying for 3800 15-15-15-30-45 and I can't get them to go away. Only thing that helped was NOM at 34 and RTTwr at the lowest setting. Those two decreased the errors to 1x error 12 and 2x error 2 but whatever I tried failed and produced more. I tried vsoc and procodt, and various drive strength, vdimm also to no avail..


Not 100% sure but I think #12 and #2 were usually coming from the tRCDRD for me.
Up to which VDIMM did you try? You could need 1.55V if the binning is not good.
Try to set only tRCDRD to 16 and see if it gets better.


----------



## Chaib

Audioboxer said:


> Probably. tRCDRD doesn't really scale with voltage, it'll expect a voltage baseline and then just work in most cases where the sticks can do it.
> 
> Good way to check things with 4x8GB is run with 2x8GB or even test each DIMM individually.





mongoled said:


> @Chaib
> 
> You need to do this first of all to determine each pair independently from each other.
> 
> 1.5v is toooo little for these memory modules when pushing tCL @14.
> 
> As others have explained tRCDRD does not scale with voltage once it hits a wall, so if you dont want to test the dimms in pairs then you need to run tRCDRD @15, raise vDIMM to 1.55v, put a fan over them.
> 
> And report back the results ...


thank you for your advice
might have to try the individual dimms at the weekend

until then ive tried trcdrd 15 and lower other timings (might need to test over night for full stability)









I guess I could try for true 1T and lower trfc with a bit more voltage.
Anything else I could fix? Im still not 100% sure what the correct rtts are...


----------



## DeepOcean

Hey, do you have any advice on fixing excessive memory training on cold start? I found some threads that mention raising cldo vddp and vddg ccd but I didn't have any succes. I run those those timings which are really stable, 1hour anta777, 1usmus and some hours of prime95. Problem is it takes 7-10 attempts to boot, and if unlucky doesn't boot at all.


----------



## anta777

tRAS=34
FAW=16
WR=16
WTRL=8
WTRS=4


----------



## Audioboxer

Hmm, might be discovering something interesting with profiles, though this might be old news to the regulars in this topic. It seems I can pass 7~9 cycles of Anta777 no issues at all, repeatedly, same conditions, but in testing at the moment I seem to be able to continually trigger a TM5 timeout with 1usmus v3 (often as high as cycle 17~19). Need another few nights of testing due to length of cycles I'm doing but I'll report my findings more in a day or two.

I would always advocate multiple testing apps/profiles anyway, but it's just interesting for me to see it play out clearly and seemingly be repeatable. As I said it might be known knowledge around here, for example, that the 1usmus v3 profile is good at catching very minor instability with VDIMM/tRFC (what I think is behind the timeouts) but they might sail past with extreme.


----------



## Beginner1257

Ahoy all, I have finally finished my new gaming PC this morning, so far I have overclocked just the memory. This forum is full of great advice´s, ideas and all about it, anyway for now I have stealed just mr. @mongoled setup, sorry and thank you sir  And it looks really good! I will try to play with PBO during tomorrow, by the your guide, so again thank you in advance 
Anyway, I had to raise VDDP up to 0.98V to get PHY 26/26. It´s on the edge 🤔 But nothing else really helped about it.

3800 13-14-14-14 t2


----------



## Dodgexander

Chaib said:


> Hello guys
> 
> I have been reading through a lot of this thread but im kinda overwhelmed by the amount information especially by @Veii
> 
> For reference I am running 4x8 Viper Steel 4400 A2 PCB and trying to get 3800 flat 14 idealy 1T stable. This config seems to be really hard to stabilize from what ive heard but ive not given up yet.
> 
> View attachment 2530020
> 
> 
> I have tried up to 1,58V and a dozen of combinations of ProcODT and RTTs but nothing seems to make a difference to stability or at least I didnt recognize any pattern yet. No Matter what I get Errors #6 within the first 20s of TM5.
> Did I miss something important? Or is it simply not enough Vdimm? My current stable config is Flat 15s with 1,43V on the same sticks.
> 
> Id be thankful for any help


You share a very popular kit, with me and many others. Flat 14s just isn't possible for me, and may not be for you either. For 1t stability you can try 56 of addrcmdsetup. Trfc you want to use a multiple of 40.

Don't take shortcuts, make sure you can run looser timing before trying to jump on flat 14. Then when you have stability reduce each one by one until you see what causes the problem.

I ended up with 1.55v 14-8-15-15-21-36

Don't worry too much like I did. Most tweaks here make no meaningful difference.


----------



## umea

so, has everyone with the 4000c14 kit managed to get tRCDRD 14 stable? so far it seems to be the case

edit: also there is an improved bin of the 17-18-18-38 kit. 4266->4400 Are you a human?


----------



## DeepOcean

DeepOcean said:


> Hey, do you have any advice on fixing excessive memory training on cold start? I found some threads that mention raising cldo vddp and vddg ccd but I didn't have any succes. I run those those timings which are really stable, 1hour anta777, 1usmus and some hours of prime95. Problem is it takes 7-10 attempts to boot, and if unlucky doesn't boot at all.
> View attachment 2530084





anta777 said:


> tRAS=34
> FAW=16
> WR=16
> WTRL=8
> WTRS=4


thanks, but didn't work :/ i hope there is a way to fix ram training.. does cldo vddp work best in a certain range or do i can i just try around with keeping it on 1.1v


----------



## mongoled

Beginner1257 said:


> Ahoy all, I have finally finished my new gaming PC this morning, so far I have overclocked just the memory. This forum is full of great advice´s, ideas and all about it, anyway for now I have stealed just mr. @mongoled setup, sorry and thank you sir  And it looks really good! I will try to play with PBO during tomorrow, by the your guide, so again thank you in advance
> Anyway, I had to raise VDDP up to 0.98V to get PHY 26/26. It´s on the edge 🤔 But nothing else really helped about it.
> 
> 3800 13-14-14-14 t2


"Steal" away, thats what the posted configs are for

Those modules are looking like the go to modules for easy peasy flat 14s, you pay the price and you get the goods



Good job




umea said:


> so, has everyone with the 4000c14 kit managed to get tRCDRD 14 stable? so far it seems to be the case
> 
> edit: also there is an improved bin of the 17-18-18-38 kit. 4266->4400 Are you a human?


Its looking that most are, thats a nice bin also, though the price is not too bad





DeepOcean said:


> thanks, but didn't work :/ i hope there is a way to fix ram training.. does cldo vddp work best in a certain range or do i can i just try around with keeping it on 1.1v


You need to experiment with the range, there is no "best" range, some FCLK frequencies need a particular vDDP voltage to behave, you should start by testing from 0.880v and moving up in 40mv steps to see if there is a difference in how the board posts, 1.1v is the maximum/upper range, you should not be any where near that !


----------



## ManniX-ITA

DeepOcean said:


> thanks, but didn't work :/ i hope there is a way to fix ram training.. does cldo vddp work best in a certain range or do i can i just try around with keeping it on 1.1v


Did you try with 2 DIMMs only? Same training issues?
VDDP is generally best 900-950mV. 1.1V is very high. 
VDDG is also very high for a 5600x. I'd try with 950-1000mV.
Also would try with ProcODT 36.9/43 with ClkDrvStr at 40.


----------



## Taraquin

DeepOcean said:


> thanks, but didn't work :/ i hope there is a way to fix ram training.. does cldo vddp work best in a certain range or do i can i just try around with keeping it on 1.1v


Try the suggestions, but change wtrl to 9 or 10, 8 was impossible for me. Try Mannys suggestions on voltage, lower vddp and ccd might improve stability. 40-20-30-20 can often work well, but usually not required when running gdm.


----------



## DeepOcean

thanks guys, will start experimenting! just to be clear again, the settings are rock stable once i get into windows, it just takes above 7 times of reboots for mem training to POST, and sometimes doesn't at all. and ye gotta try with 2 sticks each as its mixed kits


----------



## mongoled

Audioboxer said:


> Wonder what happened with AGESA 1.2.0.4? AMD pretty much pushed it out buggy and now it seems to have gone AWOL 🤣


Yup its lost in action

😂 😂

Ive changed the manner im doing my testing, just a change in order.

I always used to concentrate on getting TM5 stable (1usmus v3) before moving to anything else, but while pushing 3866/1933, ive found its been relatively easy to get TM5 to pass a 25 run cycle, but Y-Cruncher is a fail.

Its three tests that are proving difficult and for different reasons, N32 and HNT seem to be related to PLL 1.8v once all other voltages/settings fail to bring stability, while VST seems to be related to vSOC/ProcODT.

So I am now concentrating on these three tests first.

Once ive got a stable combo for at least 10 runs, I will then switch Y-Cruncher to all tests for a 2 hours cycle.

Only then, after this passes, will I move to TM5.

Im pretty confident that many of the TM5 screen shots posted here are not Y-Cruncher stable, I base this on the fact that very few people are posting Y-Cruncher shots to prove stability.

Just to make myself clear, this is my new foundation for tweaking a 24/7 profile, not for some exteme benching for "competitive" results


----------



## Audioboxer

mongoled said:


> Yup its lost in action
> 
> 😂 😂
> 
> Ive changed the manner im doing my testing, just a change in order.
> 
> I always used to concentrate on getting TM5 stable (1usmus v3) before moving to anything else, but while pushing 3866/1933, ive found its been relatively easy to get TM5 to pass a 25 run cycle, but Y-Cruncher is a fail.
> 
> Its three tests that are proving difficult and for different reasons, N32 and HNT seem to be related to PLL 1.8v once all other voltages/settings fail to bring stability, while VST seems to be related to vSOC/ProcODT.
> 
> So I am now concentrating on these three tests first.
> 
> Once ive got a stable combo for at least 10 runs, I will then switch Y-Cruncher to all tests for a 2 hours cycle.
> 
> Only then, after this passes, will I move to TM5.
> 
> Im pretty confident that many of the TM5 screen shots posted here are not Y-Cruncher stable, I base this on the fact that very few people are posting Y-Cruncher shots to prove stability.
> 
> Just to make myself clear, this is my new foundation for tweaking a 24/7 profile, not for some exteme benching for "competitive" results


Y-cruncher is absolutely mandatory over 1900 FCLK as well IMO. HNT absolutely destroys my IF in seconds 🤣

Whereas I can run TM5 at 2000 FCLK and it plods along with no issues.


----------



## error-id10t

mongoled said:


> Its three tests that are proving difficult and for different reasons, N32 and HNT seem to be related to PLL 1.8v once all other voltages/settings fail to bring stability, while VST seems to be related to vSOC/ProcODT.


So you're suggesting VST first right? That forces a check on vsoc/procodt. Once good, you look at N32 and HNT which in theory fail if PLL is wrong?


----------



## Audioboxer

Audioboxer said:


> Hmm, might be discovering something interesting with profiles, though this might be old news to the regulars in this topic. It seems I can pass 7~9 cycles of Anta777 no issues at all, repeatedly, same conditions, but in testing at the moment I seem to be able to continually trigger a TM5 timeout with 1usmus v3 (often as high as cycle 17~19). Need another few nights of testing due to length of cycles I'm doing but I'll report my findings more in a day or two.
> 
> I would always advocate multiple testing apps/profiles anyway, but it's just interesting for me to see it play out clearly and seemingly be repeatable. As I said it might be known knowledge around here, for example, that the 1usmus v3 profile is good at catching very minor instability with VDIMM/tRFC (what I think is behind the timeouts) but they might sail past with extreme.


So I'd say preliminary results at the moment after another day/night of testing is while tRFC/VDIMM instability leading to errors or timeouts can be picked up across both profiles, timeouts relating to tRAS seem to be repeatedly missed by Anta777 extreme. At least under my test conditions.

I narrowed it down to flipping a switch between 22 tRAS and 24 tRAS. Out of 5 times doing a 25 cycle 1usmus v3, TM5 timed out 4 times. Sometimes as early as within 7 cycles, other times up at 17~19 cycles. When doing Anta777 extreme cycles (7 cycles), it passed every time.

With tRAS at 24 1usmus v3 finally passes, consistently, without any timeouts.

So my findings would suggest if you're playing with low tRAS values, do not _just_ rely on Anta777 extreme. I never got 1 TM5 error with tRAS 22 (only errors when pushing tRFC/VDIMM low ~ tRFC aiming for 208 for example), only timeouts.

I'd like to disclaimer this with I don't like OC scene drama that sometimes kicks off, I appreciate all work and development people do to bring us plebs testing apps/profiles and what not. I fully advocate for using multiple profiles and apps for stability testing. It's the best way to be safe! So I am not saying one profile is better than the other, simply sharing my own personal experience that to me, it _seems_, low tRAS values _could_ benefit from testing across multiple profiles. Then again I know many people will not drop tRAS below 26~28 as diminishing returns and/or even auto-correction.

But I have noticed an uptick of people dropping tRAS even as low as 21, and my feeling is some people might ignore timeouts thinking they are TM5 bugs or just something you close the app on and restart it. As above 1 time I managed to get tRAS 22 passed a 25 cycle. A timeout to me is simply instability, even if minor. Just because it's not a TM5 error doesn't mean it should be ignored.


----------



## mongoled

error-id10t said:


> So you're suggesting VST first right? That forces a check on vsoc/procodt. Once good, you look at N32 and HNT which in theory fail if PLL is wrong?


If only it was black and white!

Example, ive configs that are TM5, Y-Cruncher stable at 4133/2067, none of these configs required me to pay close attention to VST.

The difference with the 3866/1933 profile im attempting is that im pushing very tight timings (13-14-14-14), its these that are triggering the instability that is showing in the VST test (and N32/HNT).

For my 3800/1900 profile, running 15 tCL, I only need 1.1375v, pushing tCL to 13 vSOC needed to increase to 1.175v, now for 3866/1933 im having to go to 1.2v and its still not 100% stable.

The issue here is that the vSOC is going to eat into the CPUs power budget, so its all a fine balance.

So to your question, all I can say is to use Y-Cruncher first when you are pushing the boundries for stability, then move to TM5.

Right now what I do and does not matter the order is I am concentrating on VST, before I was concentrating on N32/HNT, its about getting a feel for the hardware, looking at characteristics when changing settings and taking it from there .....


----------



## umea

mongoled said:


> Those modules are looking like the go to modules for easy peasy flat 14s, you pay the price and you get the goods
> Its looking that most are, thats a nice bin also, though the price is not too bad !


Yep, for anyone pushing for that last bit of raw performance and has the money then this bin is definitely the "to buy" one. I'd like to grab a kit of it soon, just need to look to sell off my current kit.


----------



## Audioboxer

umea said:


> Yep, for anyone pushing for that last bit of raw performance and has the money then this bin is definitely the "to buy" one. I'd like to grab a kit of it soon, just need to look to sell off my current kit.


This kit will be great if AMD sort out the IMC for their 3D revisions or whatever they're called. 2 CCD chips really need to be able to push latency lower. I wouldn't say the 4000C14 kit is wasted on a 5950x, but it's limited. Both with latency and IF. AMD really have to sort IF.

Also I'm waiting for the first person who manages to do tRCDRD 13 at 3800 on a 5950x 🥳 Only seen it done with the Ryzens that have the best IMCs. Usually a G variant. Or it's SR sticks instead of DR. It's probably SR vs DR that is the biggest roadblock as long as your IMC isn't terrible.

A couple of minutes of TM5 error free is the best I've managed for 3800 13-13-13-13. Flat 14 with this kit is a complete joke. I've got it running at 1.45v with fairly tight timings.


----------



## umea

Audioboxer said:


> This kit will be great if AMD sort out the IMC for their 3D revisions or whatever they're called. 2 CCD chips really need to be able to push latency lower. I wouldn't say the 4000C14 kit is wasted on a 5950x, but it's limited. Both with latency and IF. AMD really have to sort IF.
> 
> Also I'm waiting for the first person who manages to do tRCDRD 13 at 3800 on a 5950x 🥳 Only seen it done with the Ryzens that have the best IMCs. Usually a G variant. Or it's SR sticks instead of DR. It's probably SR vs DR that is the biggest roadblock as long as your IMC isn't terrible.
> 
> A couple of minutes of TM5 error free is the best I've managed for 3800 13-13-13-13. Flat 14 with this kit is a complete joke. I've got it running at 1.45v with fairly tight timings.


Yeah, I'm also hoping that the 3d revisions will also have better IMCs. Realistically this kit is just absolutely ridiculous no matter what platform you use, but right now being limited to 1900fclk kind of sucks. Of course pushing lower is nice, but pushing lower AND being able to hit higher frequencies would be cool.

I'll probably pick up a 5950x with the chip update as well as the 4000c14 kit. Working on selling off a bunch of stuff I don't use in the meantime


----------



## KedarWolf

umea said:


> Yeah, I'm also hoping that the 3d revisions will also have better IMCs. Realistically this kit is just absolutely ridiculous no matter what platform you use, but right now being limited to 1900fclk kind of sucks. Of course pushing lower is nice, but pushing lower AND being able to hit higher frequencies would be cool.
> 
> I'll probably pick up a 5950x with the chip update as well as the 4000c14 kit. Working on selling off a bunch of stuff I don't use in the meantime


I'm getting a $4000 CAD tax refund in March of next year. Maybe a Samsung 49" G9 Neo monitor AND a 5950x with the new chip then. But I'll wait to see how other peeps say they do and perform first.


----------



## Dodgexander

For me y cruncher was best at finding max FCLK but has never been good finding memory issues. Once I got FCLK stable and whea free tm5 helped me the most, but only the more extreme profiles.

Same with the oc sheet, a lot of posts won't be 100% stable, especially high FCLK ones.


----------



## Audioboxer

First time trying Karhu, website seems to suggest 6400%+ is 99.41% accurate, but I will leave it running longer. Only thing I changed from default was enabling cache.

I like how 6400% comes in around the same time as a 25 cycle TM5 1usmus v3.


----------



## PJVol

@*XPEHOPE3*
Found pm_table labels for the Renoir's. Cezanne's table is larger, but not much, so I think we've got enough to recreate 95%+ of entry names.


----------



## Bix

Audioboxer said:


> View attachment 2530278
> 
> 
> First time trying Karhu, website seems to suggest 6400%+ is 99.41% accurate, but I will leave it running longer. Only thing I changed from default was enabling cache.
> 
> I like how 6400% comes in around the same time as a 25 cycle TM5 1usmus v3.


Nice temps! What kind of cooling are you using?


----------



## Audioboxer

Bix said:


> Nice temps! What kind of cooling are you using?


A Bykski 2 DIMM watercooling block.


----------



## Mach3.2

@Audioboxer no luck with pure 1T yet?


----------



## Bix

Audioboxer said:


> A Bykski 2 DIMM watercooling block.


Ah, that explains it
Been struggling with temps on air since I got my second set of DIMMs... NH-D15 doesn't leave much room for an extra fan!


----------



## Audioboxer

Mach3.2 said:


> @Audioboxer no luck with pure 1T yet?


It's pretty pointless on a 5950x, incredibly difficult. From the more research I do into setup times it honestly seems like there is no performance cost, or it's absolutely minimal.

I've been working on tRCDRD 13 and trying to brute force it. With my 3800 tCL13 profile I can continually get an error in Karhu on 7 seconds pretty much no matter what, even right up to 1.75v  As they say, tRCDRD does not scale with voltage...

Either my IMC cannot handle tRCDRD 13 at 3800, the memory cannot handle it or a combination of both. If it's the memory it's probably because it's DR. There are verified SR kits at 3800 tRCDRD 13.










Dropping down to 3733 gets to 6 minutes in. Might be fixable, but probably not. For whatever reason my tRFC timings went a bit crazy when coming off 3800, the BIOS seemed to override them. So I had to force it to 224 for all.










3667 at tRCDRD 13 looks like it'll probably be do-able. So I guess you could "bin" this kit for 3600 13-13-13-13. Or hey, if I'm bored I might try 12-13-13-13 at 3600. tCKE auto's at 0 at 3667, I didn't set that.

I'm going to have a look at FCLK 2000 now, see what timings I can run with the memory at 4000. The IF probably won't be stable, but as long as I don't run y-cruncher and destroy my USB ports memory tests will _probably_ run fine. Interested to see if I can do 4000 14-14-14-14 instead of 14-15-15-15.


----------



## Audioboxer

Good chance a tCL 12 profile is do-able. Couple of things though, Windows startup repair with 1.55v, so it's clear even with the frequency down at 3600 using tCL12 is going to need above 1.55v. I just quickly put it to 1.6v, might be a chance it could run less.

My good friend tPHYRL 28/26 is back, so that would need to be fixed.

Then there is the final question of how high could frequency go with tCL 12?










For anyone interested, no, tRCDRD 12 is not going to be happening lol. Errors even quicker than tRCDRD 13 at 3800 (7%).


----------



## mongoled

Audioboxer said:


> View attachment 2530308
> 
> 
> Good chance a tCL 12 profile is do-able. Couple of things though, Windows startup repair with 1.55v, so it's clear even with the frequency down at 3600 using tCL12 is going to need above 1.55v. I just quickly put it to 1.6v, might be a chance it could run less.
> 
> My good friend tPHYRL 28/26 is back, so that would need to be fixed.
> 
> Then there is the final question of how high could frequency go with tCL 12?
> 
> View attachment 2530310
> 
> 
> For anyone interested, no, tRCDRD 12 is not going to be happening lol. Errors even quicker than tRCDRD 13 at 3800 (7%).


Latency ?


----------



## XPEHOPE3

PJVol said:


> Found pm_table labels for the Renoir's. Cezanne's table is larger, but not much, so I think we've got enough to recreate 95%+ of entry names.


Where? Gimme-gimme! I also saw your posts at ryzen monitor github, so you know there is some info about Cezanne. Are you going to report the labels to ryzen_monitor or Ryzen SMU repos?


----------



## Audioboxer

Playing around with lowest VDIMM that might have a chance with tCL 12, seems to be 1.58v. 1.56~1.57v both have errors within 3 cycles.

Went to 2T for now as it's the quickest way I can get 26/26 with an even tCL.



mongoled said:


> Latency ?












Seems to be around 56ns with the settings above, but I can't guarantee they are stable and they are at 2T just now. L3 cache is still pretty broken, lol MS.



















Figured out what is causing 28/26 at 3600, it's the setup time. 1T pure above is 26/26, though it is of course completely unstable, even at ClkDrvStr 60. I left it at 60 to switch over to 1T/56 just to show that was the only change.

So the fun and games with tPHYRDL go on. If the tCL is uneven, then the setup time doesn't matter, it will be 26/26 even when using 56. When the tCL is even, 26/26 seems nearly impossible for me to achieve with a setup time. It's either 28/26 or 28/28.

Literally need a memory engineer at this point to try and explain tPHYRDL behaviour like this, especially the relationship with tCL 

*edit* - Oh yeah, I fixed the weird tRFC behaviour where it ignores your settings, it happens if you let tCKE be 0. So instead of AUTO just switched it to 1.


----------



## glnn_23

Ran this 3800c13 13 13 13 29 42 and the rest of the timings, except tCKE 9, on auto just to see if it would run. Pretty slow TM5.
Tried tightening timings up from there but never got past a couple of cycles of TM5.

Got a 3600c12 run here as well but needed 1.61v

Audioboxer can you get from 28/26 to 26/26 by raising cldo vddp


----------



## Audioboxer

glnn_23 said:


> Ran this 3800c13 13 13 13 29 42 and the rest of the timings, except tCKE 9, on auto just to see if it would run. Pretty slow TM5.
> Tried tightening timings up from there but never got past a couple of cycles of TM5.
> 
> Got a 3600c12 run here as well but needed 1.61v
> 
> Audioboxer can you get from 28/26 to 26/26 by raising cldo vddp
> 
> 
> View attachment 2530349
> View attachment 2530350


Nah, doesn't help. It's the setup timing causing it but with DR its mandatory for 1T.

3600CL12 looks to need about 1.6v for me as well, I found some errors at 1.58v.

Good to see you manage tRCDRD 13 at 3800, seems the SR bin of this kit can do it no problem.

*edit* - Even GDM 1T runs 26/26 fine


----------



## Audioboxer

@Veii and @mongoled as I approach something like 1.65 VDIMM what other timings or resistances might need to be changed to help stabilise a higher VDIMM?

I'm giving this tCL12 profile a go even at 3600 for a bit of fun and I've found a TM5 timeout on cycle 17 at 1.6v. Poster above needed 1.61v to achieve it on SR so fair enough I might get away with 1.61v as well. 1.58v resulted in actual TM5 errors so I know my issue is likely voltage. So far I've seen 1.44v at tCL14 3800, 1.55v at tCL13 3800 and it seems reasonable tCL12 even at 3600 would need 1.6-1.65v.

So I've now decided to go with a power budget of 1.65v for this experiment, it might even help me move up from 3600 if I can get it fully stable first. But I'm finding that simply going to 1.65v is resulting in being MORE unstable! I'm guessing at this kind of voltage things like the Rtts, ProcODT and maybe even some timings will need to be looked at.

Probably no more just leaving it on 7/3/3 and 34.3 lol. As you two seem to have quite a bit of experience at something like 1.65v and beyond some tips would be appreciated! Temps are no issue at all on water, it's impressive how such high VDIMM really does next to nothing to temps. It appears now my challenge is either the IMC and/or memory stability with a high VDIMM.


----------



## PJVol

XPEHOPE3 said:


> Are you going to report the labels to ryzen_monitor or Ryzen SMU repos?


Lol, actually, that's where I found it.









Renoir-Mobile-Tuning/SystemMonitor.cs at master · sbski/Renoir-Mobile-Tuning


Control power and temperature limits on AMD Renoir powered laptops. - Renoir-Mobile-Tuning/SystemMonitor.cs at master · sbski/Renoir-Mobile-Tuning




github.com


----------



## Audioboxer

Giving up on tCL12/3600 just now in lieu of some advice on high VDIMM. Will turn to 4000/2000. Going back to basics and attempting an XMP run first










Look at all those errors though 17 minutes in lol. At least there has been 0 USB wonkiness so far, but its y-cruncher that tends to cause that. Just want to see if I can get a 25 cycle TM5 at XMP first.


----------



## mongoled

@Audioboxer 
Increase RttPark to 4 or 5

You aint helping us by not telling us what errors you are getting in TM5, come on dude you are a veteran now !!

😂 😂


----------



## Audioboxer

mongoled said:


> @Audioboxer
> Increase RttPark to 4 or 5
> 
> You aint helping us by not telling us what errors you are getting in TM5, come on dude you are a veteran now !!
> 
> 😂 😂


lol I can't even remember now, I wasn't paying much attention. Just reproduced errors at 1.65v quite early but at 1.6v it was a timeout well into the test. IIRC it might have been 7/8.

Gave up on that for now anyway, I'm never going to run at 3600. But I probably will revisit it for fun at some point when bored. Just the idea of getting tCL12 stable is a fun side project.

Decided to take a serious stab at FCLK above 1900. I just got frustrated before with y-cruncher nuking my USB which in turn would delete all my ICUE profiles lmao.

Focusing on memory testing just now instead of jumping right into y-cruncher. I know IF is very likely unstable but I'm interested to see if memory stress tests can get by. If they can ill turn my eyes to IF and that damn HNT test.


----------



## mongoled

Audioboxer said:


> IF and that damn HNT test


Have a read here 

Large Multiplication (numberworld.org) (search page for HNT)

Im wondering if these propriety tests are failing for other reasons then system stability.

Still have not pinpointed a 100% workable fix for this test.

I can run it and get 12+ cycles out of it, reboot without changing any settings then it will fail after the first cycle.....


----------



## Audioboxer

mongoled said:


> Have a read here
> 
> Large Multiplication (numberworld.org) (search page for HNT)
> 
> Im wondering if these propriety tests are failing for other reasons then system stability.
> 
> Still have not pinpointed a 100% workable fix for this test.
> 
> I can run it and get 12+ cycles out of it, reboot without changing any settings then it will fail after the first cycle.....


Thanks, I'll give it a read.

I guess that could be possible, but it does pass fine for me at 1900, so something at 2000 is causing my USB to freak out when HNT is running. As USB issues are a known problem with WHEA/IF it's hard for me not to make that connection.

Instead of diving right into y-cruncher after TM5/Karhu, I might swing by OCCT and simply do some CPU testing and see if I can get it to WHEA error. Basically try giving every stability testing app a go I can think of that is not y-cruncher.

It's just such a PITA going through the HNT USB disconnects because even if ICUE is closed it nukes the corsair commander pro which stops my loop working properly until reconfigured, from scratch. Keyboard and mouse quickly connecting/disconnecting isn't an issue, but that commander pro just falls apart when facing the rapid USB connect/reconnect.

I guess in worst case scenario I'm even worried it gets damaged. It must be connecting/reconnecting USB like a games controller with a turbo button lol.

Not seeing any USB issues so far during normal use or memory stability testing, so I'd really like to try and replicate USB issues on something outside of y-cruncher HNT. Because it works at 1900 though I'd just find it hard to ever sign off 2000 as stable, no matter if it passes every other stability test in existence :/ I'm all for ignoring/suppressing WHEA logs as long as there is no performance degradation and stability test apps pass, but that clashes with y-cruncher issues. The funny thing though is the HNT test doesn't fail, my USB simply goes crazy....


----------



## mongoled

Audioboxer said:


> Thanks, I'll give it a read.
> 
> I guess that could be possible, but it does pass fine for me at 1900, so something at 2000 is causing my USB to freak out when HNT is running. As USB issues are a known problem with WHEA/IF it's hard for me not to make that connection.
> 
> Instead of diving right into y-cruncher after TM5/Karhu, I might swing by OCCT and simply do some CPU testing and see if I can get it to WHEA error. Basically try giving every stability testing app a go I can think of that is not y-cruncher.
> 
> It's just such a PITA going through the HNT USB disconnects because even if ICUE is closed it nukes the corsair commander pro which stops my loop working properly until reconfigured, from scratch. Keyboard and mouse quickly connecting/disconnecting isn't an issue, but that commander pro just falls apart when facing the rapid USB connect/reconnect.
> 
> I guess in worst case scenario I'm even worried it gets damaged. It must be connecting/reconnecting USB like a games controller with a turbo button lol.
> 
> Not seeing any USB issues so far during normal use or memory stability testing, so I'd really like to try and replicate USB issues on something outside of y-cruncher HNT. Because it works at 1900 though I'd just find it hard to ever sign off 2000 as stable, no matter if it passes every other stability test in existence :/ I'm all for ignoring/suppressing WHEA logs as long as there is no performance degradation and stability test apps pass, but that clashes with y-cruncher issues. The funny thing though is the HNT test doesn't fail, my USB simply goes crazy....


Its a strong possibility that HNT is FLCK sensitive,

easy way to test is by keeping FCLK @1900 and forcing other timings down to see if we can instigate errors in the HNT test while the other tests pass.

As I was not making any headway at troubleshooting at 3866/1933, i moved to 4067/2033 and unfortunately im seeing the same thing occurring once I push tCL downwards.

Screenshot below is what I described previously 



> I can run it and get 12+ cycles out of it, reboot without changing any settings then it will fail after the first cycle.....


So I fired TM5, just to see where its at and so far its going through OK, going to let this finish then try with something else that does NTT tests (integer algorithms) to see if it errors in those also.

Anyone know of another proggy that does NTT tests ????


----------



## Audioboxer

mongoled said:


> Its a strong possibility that HNT is FLCK sensitive,
> 
> easy way to test is by keeping FCLK @1900 and forcing other timings down to see if we can instigate errors in the HNT test while the other tests pass.
> 
> As I was not making any headway at troubleshooting at 3866/1933, i moved to 4067/2033 and unfortunately im seeing the same thing occurring once I push tCL downwards.
> 
> Screenshot below is what I described previously
> 
> 
> 
> So I fired TM5, just to see where its at and so far its going through OK, going to let this finish then try with something else that does NTT tests (integer algorithms) to see if it errors in those also.
> 
> Anyone know of another proggy that does NTT tests ????
> 
> View attachment 2530411


We'll work together! My 4000 memory tests look to be solid so far, and I'll see if I can begin to reign in the secondary timings away from XMP.

I might even try 2033 like yourself, I know it boots fine. There has been some recorded weirdness with FCLK and people being able to stabilise say 1933 easier than 1900 or 2033/2066 easier than 2000 lol. Gotta love AMD.

I guess it's all about performance penalties and whether or not you're comfortable saying you're stable. It would be good to find other number tests like y-cruncher to see.


----------



## mongoled

Audioboxer said:


> We'll work together! My 4000 memory tests look to be solid so far, and I'll see if I can begin to reign in the secondary timings away from XMP.
> 
> I might even try 2033 like yourself, I know it boots fine. There has been some recorded weirdness with FCLK and people being able to stabilise say 1933 easier than 1900 or 2033/2066 easier than 2000 lol. Gotta love AMD.
> 
> I guess it's all about performance penalties and whether or not you're comfortable saying you're stable. It would be good to find other number tests like y-cruncher to see.


I got an error 1 at cycle 11, so couldnt be arsed to wait as tRRDL was on 6 which is tight for the frequency (would have needed bumping to 8).

So I rebooted and lowered tFRC upped tCL and just giving TM5 another go, on a side note

Though have a tPHYRDL mismatch .... and more relative to you, this is pushing vDIMM to 1.68v


----------



## Audioboxer

I can't stand GDM so it got disabled, tCKE changed from auto making it 16 and just put some "safe" Rtts/DrvStrs. Giving Karhu a spin as well. Will let it go to 2 hours before trying to tighten some secondary timings for testing.

All those WHEA errors though  This is with an increase in VSOC to 1.2v, CCD to 1.05v, IOD to 1.09v and CPU 1.8v to 1.9v (Buildzoid said this can help IF instability). No USB issues though! lol

*edit* - @mongoled are you suppressing WHEA errors or do you not get any at 2033?


----------



## mongoled

@Audioboxer
As these Vipers dont have temp sensor, what difference in C are you seeing from your aircooled dimms to them being watercooled ?

S..............u............ r............p........r........e......s...s..e..d


----------



## Audioboxer

mongoled said:


> @Audioboxer
> As these Vipers dont have temp sensor, what difference in C are you seeing from your aircooled dimms to them being watercooled ?


At 1.5v on aircooled I would be around 40~41 degrees with my 120mm fan running 100% lmao. So a big difference on watercooled. I was running 1.65v earlier and it was still around 33~35 degrees.

The biggest difference with a watercooling loop is not doing stability tests it's running a game and dumping the heat from a GPU/CPU at 100% into a loop. My water temps get to like 33 degrees and memory is then 37~38 degrees under 100% load.

Ironically, memory stability tests become a _very poor_ way to test thermals on watercooling, if you have a single loop. Karhu/TM5 usage is not enough to really stress PBO and the GPU is in idle when they're running.

And sadface for me, Windows 11 can't suppress WHEA errors


----------



## mongoled

Audioboxer said:


> Karhu/TM5 usage is not enough to really stress PBO and the GPU is in idle when they're running.


On the contrary PBO is pushed to the max, while I run TM5 EDC flatlines at 125 amps that I believe to be an internal limiter that can only be effected by using telemetry or other voodoo.

Though not running any GPU stress is definitely missing when pushing water temps.

Thats the reason I run 4 hours RealBench as a minimum for a candidate 24/7 setup



** EDIT **
Forget Windows 11! 

Revisit it in 10 months time


----------



## Audioboxer

mongoled said:


> On the contrary PBO is pushed to the max, while I run TM5 EDC flatlines at 125 amps that I believe to be an internal limiter that can only be effected by using telemetry or other voodoo.
> 
> Though not running any GPU stress is definitely missing when pushing water temps.
> 
> Thats the reason I run 4 hours RealBench as a minimum for a candidate 24/7 setup


Ah, I should have checked, I just assumed with temps as "low" as they were the CPU wasn't being run hard. Karhu shows 100% EDC usage, but PPT is only 43% and TDC 34%. CPU temp around 47~48 degrees.










So CPU is being used pretty well. It likely is the lack of GPU that keeps the heat back. A 2080Ti pulling 330~380W dumps the heat in!

Can't escape the GPU always being the biggest enemy! If you're air cooled it will dump all that lovely heat into your case and impact the DIMMs and if you're watercooled it will dump all that lovely heat into the loop and raise DIMM temps a few degrees lol.

Big budget expense would probably be two loops, one for GPU only and the other for CPU/memory lol. 4 radiators will simply have to do me!

And yes, I'm still tempted to go back to Windows 10... Nearly did the other day.

*edit* - Going to leave XMP now and try and work on secondaries










lol at that tasty WHEA error count.


----------



## XPEHOPE3

PJVol said:


> Lol, actually, that's where I found it.


Thanks!
I was referring to ryzen_monitor and ryzen SMU repos. Are you going to report that GitHub - sbski/Renoir-Mobile-Tuning: Control power and temperature limits on AMD Renoir powered laptops. repo to them?
Anyway, I wonder where do all those obscure labels come from? Did sbski reverse engineered Ryzen Master?


----------



## Audioboxer

lol, the noob in me learns something new, tRFC values change per frequency stepping. Yes, even now after all these months of learning I hadn't really noticed that. I guess I've done most of my work at 3800.

Anyway, a tRFC of 240 is 120ns at 4000. Was wondering why my BIOS and even booting into Windows didn't want to accept 224 🤣

Bonus for the OCD peeps amongst us though 240 is a nice round 120ns exactly!


----------



## mongoled

Audioboxer said:


> lol, the noob in me learns something new, tRFC values change per frequency stepping. Yes, even now after all these months of learning I hadn't really noticed that. I guess I've done most of my work at 3800.
> 
> Anyway, a tRFC of 240 is 120ns at 4000. Was wondering why my BIOS and even booting into Windows didn't want to accept 224 🤣


😂 😂 😂

** EDIT **
Just saying, ive got my tRFC calculated "wrong"

I used the Ryzen Google Calculator with "tRFC Multiplier" set to "Manual(ns)"

But tRFC does not match the equation @XPEHOPE3 posted previously

(((tRFC ns * f/2000) + d -1) div d) * d + d


----------



## Audioboxer

mongoled said:


> 😂 😂 😂
> 
> ** EDIT **
> Just saying, ive got my tRFC calculated "wrong"
> 
> I used the Ryzen Google Calculator with "tRFC Multiplier" set to "Manual(ns)"
> 
> But tRFC does not match the equation @XPEHOPE3 posted previously
> 
> (((tRFC ns * f/2000) + d -1) div d) * d + d


I just added 16 onto 224 lmao. Anyway, tests are running fine just now with it at 240. Will revisit it if I have to later.


----------



## Audioboxer

Looking optimistic for memory, using some more sensible secondary timings just now rather than pushing them all down. Going to run some benches, try an OCCT CPU stability test and if we're looking good I'll do an overnight TM5.

Then it'll either be lower secondaries more, try flat 14 or bump up frequency a bit and see if it holds out. Probably go back to Windows 10 to suppress WHEA log if I think I can daily above 1900, but I'm worried about the HNT y-cruncher USB freakout still.


----------



## Audioboxer

@mongoled can you run the OCCT CPU test? I get a WHEA error right away and USB funkiness. Boooo.










These settings.

Gutted because










Finally a benchmark that gets me below 54ns! (around the floor with 3800/5950x).

Just goes to show memory stability tests are nowhere near hard enough on the CPU to test IF instability. And yes, my ICUE profiles have now been wiped again 

With my current voltages I'm unsure how much more meat I have on the bone

VSOC - 1.2v
VDDP - 0.9v
CCD - 1.05v
IOD - 1.09v
CPU 1.8 - 1.9v

I guess I can pump up VDDP and CCD/IOD a bit more. Buildzoid ran 1.8 at 2.0v but that seems a bit high.


----------



## mongoled

Audioboxer said:


> @mongoled can you run the OCCT CPU test? I get a WHEA error right away and USB funkiness. Boooo. Gutted because
> 
> View attachment 2530449
> 
> 
> Finally a benchmark that gets me below 54ns! (around the floor with 3800/5950x).
> 
> Just goes to show memory stability tests are nowhere near hard enough on the CPU to test IF instability. And yes, my ICUE profiles have now been wiped again


😂😂

Will give it a try tomorrow when I get back to the office. 

My TM5 test crashed at cycle 18 with no errors, will re-run it again with the "tick" tRFC/2/4 values


----------



## Audioboxer

mongoled said:


> 😂😂
> 
> Will give it a try tomorrow when I get back to the office.
> 
> My TM5 test crashed at cycle 18 with no errors, will re-run it again with the "tick" tRFC/2/4 values


Cheers. Just goes to show WHEA/AMD IF crappyness really limits memory performance 

I presume OCCT uses similar stressing to HNT.










Small CPU test drops the WHEA error detected as well. In event viewer there is no red crosses, it's "just" event 19 warnings, so I'm not sure if it's normal for WHEA error spam in OCCT and the test is just to be left running?

As I get USB funkiness I stop it anyway otherwise all sorts of chaos will go on lol.

If anyone else has experience running with WHEA please let me know if you get to a point where you have no WHEA errors in OCCT despite the warning event 19s still happening, or if OCCT will always throw up a WHEA error.










Corecycler is running fine, no USB issues, but it's really just testing 1 core at a time... I pumped my voltages up, I don't even know if IOD is "safe" at 1.15v but OCCT still has a hard time.


----------



## PJVol

XPEHOPE3 said:


> Did sbski reverse engineered Ryzen Master?


Don't think it was RM, but he or another contributor did mentioned where they scraped the info. Iirc some vendor 3rd party tool.


----------



## Bix

Audioboxer said:


> If anyone else has experience running with WHEA please let me know if you get to a point where you have no WHEA errors in OCCT despite the warning event 19s still happening, or if OCCT will always throw up a WHEA error.


Only way I can stop the warning events showing as WHEA errors in OCCT is by running the suppressor.


----------



## Audioboxer

Bix said:


> Only way I can stop the warning events showing as WHEA errors in OCCT is by running the suppressor.


Yeah, I've gathered from some research it's "fine" to get the WHEA errors in OCCT, what you don't want is the test stopping meaning it's a proper core crash.

However, I've found out my biggest issue doesn't seem to be CPU or memory instability, it's simply the damn USB ports going mental. My new setup involves...










Yes, another bloated piece of software I use, G Hub, has become my new stability benchmark. As above it happily shows my mouse is connected, however, when USB issues strike










Inactive! Though the curser itself will work, it's just all my mouse profiles stop working.

More interesting is the balancing act of voltages. In my mind I thought USB issues? Pump IOD up, however, it seems going higher with voltages results in *more* instability. Such as audio crackling on boot and the mouse disconnecting itself even on desktop (idle). So trying to keep VDDG voltages lower means the USB disconnects only seem to happen when the CPU is stress-tested. Above I got about 2 minutes 17 seconds in before the mouse disconnected. With higher voltages (IOD 1.10v+) it can die within 15~30 seconds.










I went up IF frequency and behaviour is quite similar, so I don't think it will make much difference trying to stabilise 2000 or 2033. But I fear I just won't get there, my USB issues seem to be quite extreme compared to other people. I've stopped ICUE blowing up by using OCCT small CPU, it's now Logitech G HUB I'm monitoring for a USB drop out lmao.

I've had a good play around with VDDG voltages and all I seem to be able to achieve is pushing for 2 minutes plus in OCCT before a drop out. If it were going longer I'd have more confidence, but right now I simply don't think I'll be able to stop these USB drop outs.

Seems I will be able to stability test and bench memory at 2000 FCLK+ till my hearts content, but the second the CPU is really hammered my USB ports just lose it. Funnily enough OCCT does not crash, I let it go for 20 minutes, so my CPU isn't crapping out, but USB instability is just not acceptable on any daily PC.

AMD and their damn USB problems, I really hope Intel do well with what they're putting out...


----------



## Veii

Sorry for being gone for like a week again,


XPEHOPE3 said:


> Thank you for the findings! What VDIMM was used for the stable screenshot?


XMP test was on 1.52v, XMP is 1.5v
Sadly, i had to clear up some things - and probably stop now receiving "Suicide Run-Benched" dimms anymore
There is no contact issue/drama - just saw it is an issue, and OC friend knows now


Spoiler: Overcurrent Issue ~ Oxidation





























This was on both 4267 & 4400 dimms, how i got them
Vipers i could clean, but the PCB was "broken" ~ something inside it.
Gave up on the 4267 , as tRCD 17 lock was stupid ~ but it ended up the same as the Vipers
They could post all my A0 settings, but as soon as i start any load ~ it Error #6

At first i thought it's a PCIe 4.0 , a stain issue with other words
But this wasn't it
Both dimms i got to test, are pretty much "fried".
The ICs are great on the 4400 Vipers, i believe ~ but i can not get anything at all on them stable. On both 3600 16-16 doesn't even pass
Soo i've given both up and turned to something more fun








Graphical Ryzen 
Doing a bit of research there since 1ish week, and supporting HWLuxx community ~ as couple of people started to show findings
Little mass community project
In general, i secured couple 3D-Mark places with it ~ but only have a 550W PSU, soo at best it's capped at 400W

Dimms and build
It's still ongoing, probably Monday will be everything shipped to me
This time with proper 4000C16-16 dimms, nothing "burned" by VDIMM
Then i can continue spending time on RTTs and CAD_BUS. On both kits it was a pure waste of time & i'm back to my (t)rusty 4000 kit
Soo likely results come out at the end of next week.
Saved bit of time as this 6800XT will be also pushed in.

In general wanted to tease & let you guys know, that high VDIMM - even post testing around 1.8-1.9
Can indeed damage the PCB but keep the ICs fine and functional
Soo an advice ~ please check your dimms, and clean the corrosion with a micro-fabric towel and bit of water or QDC Red/WD Green , if you have
Oxidation will sneak to your slots and then cleaning is an issue.
Just for people who find posting low timings is an issue. It's not the ICs. Either you can post and come to windows or the ICs are the issue
A "bad/damaged" DIMM-PCB will post everything you trow at it, but fail instantly with #6,#0,#12 at the first 10-15sec
=======================================================================
@Audioboxer
Hence you are on the Unify-X, and surely use the unlocked bios
USB Dropouts, same as audio crackling and actually PCIe dropouts ~ where a sideproduct issue of using dLDO and rewriting PM-Table against spectre.v5
They are coming from an unstable DPM link (several) from the IO-Die towards the PCH

Meaning,
PCH is unstable, or LCLK frequency missmatches and is messed up

Resolve options,

be sure you are not on SMU 56.52 or earlier (even when i know brands downgraded it). The "fix" was on Patch-C which is 56.5*3*. Even when AMD masked it as Cezanne only "fix". Both had equal issues
Be sure PSP-FW is on 5.17.0.0, (PSP-Security device, communication hub). This came with/after chipset driver 3.08.17.375. Both 3.08 & 3.09 are not cutting performance. 3.10 is with the new CPPC patches, and shouldn't be used (for now) on Win10 ~ till you can confirm it doesn't bother you. It also comes with updated powerplans (where you should disable usb powersaving in pp and d-manager saving)
Drop both GPU and PCH to PCIe 3.0 ~ check if DPM link issues resolve. As mentioned Gen & LCLK Link-Speed change accordingly. Your issue is the link between I/O-Die & PCH on high strain (likely enforced powersaving issue)
If that all isn't it, play with the DPM settings i once mentioned, link Speed 1 and 0 (1st and forth) force them both on highest 600mhz and see if 2 or 3 do any change, or it's not the DPM but something around it
Honestly at this point you should've resolved it.

2100 FCLK at the very start with PCIe 4.0 is an issue ~ 2067 worked easily
But it is just a posting and not stability issue. Hence it will wipe your PBO & CO first, and then after it trained - you can put it back on
Dual rank also on 900mV cLDO_VDDP, can run 2100 FCLK (potentially) ~ it's not a strain limitation either.

BAR Mode + CPU CO stability is a bit of an issue
But it's resolvable. Just so you know when your COs start to fail

I guess that was it with the updates
More interesting things to follow, just slightly annoyed that Microsoft adores intel a bit too much
AMD Zen performance on Win11 is still bad, and ADL will only be comparable on Win11.
You can't compare Apples to Pears, across operating systems ~ but only throttling Zen(3D) is the current situation and what surly industry would take as "no big issue".
I'm mad about microsoft (it's still them throttling L3 cache by enforced powersaving mechanisms)
Intel, even when DDR5 is purely marketing with high numbers , hence most don't understand that 3600C18-18 is still equal to 7200C36-36. People will buy the entry tax for very "bad" advertised samsung dimms.
Nothing i can do, but it makes me sad how stupid companies expect us to be


Spoiler: Not directly AMD oriented, but we will also have to think about DDR5 on AMD














It should just mean, that we users unless we can achieve DDR5 7200MT/s or higher on the supporting new platform~ we shouldn't even bother to try and stay on DDR4 
My advice, independent of CPU Vendor

Yep that was all needed rant so far 
Good luck on trying to fix the issues, and keep pushing~
I'll come back with results once the build is done
Currently little 6800XT beats every 3080 and nearly every 3080ti
I try to sell away a 3080ti FE - but i haven't found a buyer yet. If you know anybody or any warzone player who needs these NVIDIA filters ~ let me know
So i can invest into a 6900XTXH and have fun


----------



## Audioboxer

Thanks @Veii just the inspiration I needed after a few hours of getting angry at USB lmao. More so because I've just watched hours of memory stability testing, both in TM5 and Karhu pass without issues at 4000, and even with the brief CPU testing I've been doing, it's not the CPU cores crashing at IF 2000, it's simply USB freaking out. You mentioned one thing I can sort right away, hopefully










56.52. I'm still using the MSI 1.2.0.3c beta bios that they released a while back. They "updated" it to add Windows 11 support, but I believed this to just be turning on a bios setting we can do ourselves. I'll upgrade to the unlocked version of that BIOS and hope SMU is updated.

My GPU at least is already manually set to PCIe 3.0 because it's a 2080Ti and I'm using a riser cable which only supports 3.0. PSP-FW should be whatever the latest is, as I'm on Windows 11 I've only recently installed the latest AMD chipset drivers which fixed some Windows 11 issues.

Now, speaking of upgrading MSI bios, is there no way to export a profile and import it again? On ASUS you used to be able to do it across BIOS versions, but the one time I tried it on this B550 and it wouldn't accept profiles from an older BIOS version :/ PITA to have to write down all my profiles and re-do them lol.


----------



## Veii

Oh i forgot something important,
Zentimings
There is an issue, but the dev knows about it ~ it's AMD AGESA related








It finally got caught to be mismatched
Just was purely lucky to always have correctly trained slots
* soo ZT is not broken for 2DPC boards, everything is correctly reported (nearly)

Zentimings tho, has issues








Any anomaly ?
~ Remembered 4400 SPD, and so also their CCDL/S and dimm scaling behavior. 
Not that bioses are much intelligent and can recognize PCB or ICs ~ but in case they can, they will keep remembering wrong predictions = always mess up something

This issue is a WMI reading issue ~ according to ZT dev
But it is a Bios issue
The only thing that helps, is a CMOS reset. Or two of them plus loading factory defaults

Mentioning this, as tPHYRDL predications ~ and so pretty much "on boot" predictions, will be messed up too
Soo if anybody is stuck on a missmatch ~ double CMOS reset, just to be sure what you read in ZT is actually the truth and not some issue remembered from 2-3 boots before


----------



## Veii

Audioboxer said:


> Thanks @Veii just the inspiration I needed after a few hours of getting angry at USB lmao.
> 
> 
> Audioboxer said:
> 
> 
> 
> 56.52. I'm still using the MSI 1.2.0.3c beta bios that they release a while back. They "updated" it to add Windows 11 support, but I believed this to just be turning on a bios setting we can do ourselves. I'll upgrade to the unlocked version of that BIOS and hope SMU is updated.
Click to expand...

I don't think, it can be much of an inspiration - as you are nearly optionless

In the older days, i could transplant SMU versions back and forth ~ as long as there was not a size issue (newer one being bigger and lacking space to fit it)
I'm pretty sure @Eder can do this, if there is no size issue (which i doubt in this scenario) it should be just replacable via HEX without even breaking any signature (hence encryption key is transplanted too)

I wish for a B550 Gaming Carbon Wifi , unlock
But later when the "client" can afford to pay eder ~ soo i'm not putting the request out now 


Audioboxer said:


> Now, speaking of upgrading MSI bios, is there no way to export a profile and import it again?


You can export them to USB sticks
Else profiles are inside NVRAM , inside SPI-ROM in a tiny header
Technically transplantable ~ but they often change the location/menu order ~ soo loadling a profile from an older bios,can indeed change CBS settings, usb powering settings and so on
I had this, all my USB 3.0 ports where not functioning after loading Pre 1.1.8.X profiles onto 1.2.0.0  also bt flag in CBS got changed

Helpful for people with locked/hidden CBS, to enforce back some options between bioses
But causes more issues than it is worth it
And mentioning it on the post above ~ can very well fully mess up memory training or even recognition..
Better cmos reset *after not mid* a bios update, *after* a successful post
Then you are fine.
Also load defaults ,let it boot and then cmos again - after you swap dimms. As it will keep remembering IOL delay and other nonsense (didn't think it can even be an issue, till i saw it myself)

Sorry, i don't think i can give you a fix
USB issues have to be already resolved for everybody
Just till Patch-C , every vendor had a different amount of patches by AMD and up to publish times, bioses still vary between brands
It's only sad that 1204 was a mess.
Yes, try to manually import SMU 56.5*3* from ASRock boards or current EVGA Dark 1.03 bios ~ down to your MSI boards
I see all of them downgraded, but it was not the most optimal decision.

BRB, getting Bios PSP version snapshot
EDIT:
This is what Vendors want to run with corresponding received XHCI patches







But i think they are far further and just wait, till AMD gives an OK for releasing Zen3D Retail 1.0 Bioses


----------



## Audioboxer

Veii said:


> I don't think, it can be much of an inspiration - as you are nearly optionless
> 
> In the older days, i could transplant SMU versions back and forth ~ as long as there was not a size issue (newer one being bigger and lacking space to fit it)
> I'm pretty sure @Eder can do this, if there is no size issue (which i doubt in this scenario) it should be just replacable via HEX without even breaking any signature (hence encryption key is transplanted too)
> 
> I wish for a B550 Gaming Carbon Wifi , unlock
> But later when the "client" can afford to pay eder ~ soo i'm not putting the request out now
> 
> You can export them to USB sticks
> Else profiles are inside NVRAM , inside SPI-ROM in a tiny header
> Technically transplantable ~ but they often change the location/menu order ~ soo loadling a profile from an older bios,can indeed change CBS settings, usb powering settings and so on
> I had this, all my USB 3.0 ports where not functioning after loading Pre 1.1.8.X profiles onto 1.2.0.0  also bt flag in CBS got changed
> 
> Helpful for people with locked/hidden CBS, to enforce back some options between bioses
> But causes more issues than it is worth it
> And mentioning it on the post above ~ can very well fully mess up memory training or even recognition..
> Better cmos reset *after not mid* a bios update, *after* a successful post
> Then you are fine.
> Also load defaults ,let it boot and then cmos again - after you swap dimms. As it will keep remembering IOL delay and other nonsense (didn't think it can even be an issue, till i saw it myself)
> 
> Sorry, i don't think i can give you a fix
> USB issues have to be already resolved for everybody
> Just till Patch-C , every vendor had a different amount of patches by AMD and up to publish times, bioses still vary between brands
> It's only sad that 1204 was a mess.
> Yes, try to manually import SMU 56.5*3* from ASRock boards or current EVGA Dark 1.03 bios ~ down to your MSI boards
> I see all of them downgraded, but it was not the most optimal decision.
> 
> BRB, getting Bios PSP version snapshot


Yeah you can export but they don't let you import an older BIOS profile into newer one. Speaking of a new BIOS version










MSI haven't updated this board to SMU 56.53 :/

*edit *- Just noticed you mentioned you know MSI downgraded. I wouldn't even want to begin to try and mess with a BIOS file so unless someone else can do it I guess I'll just have to hold off till MSI put out a BIOS with a newer SMU version lol.

My BIOS is the same as the versions you posted other than SMU FW version.


----------



## Audioboxer

Ommmg I think I've stopped my USB drop outs! I don't want to touch the PC just now lmao, 7 minutes into an OCCT CPU small test and no drop outs so far.

I only changed two things over last failed run, CLKREQ# to enabled and Chipset to Gen 3. The CLKREQ# to enabled under PBS I don't even know what it does but another poster advised it to help with performance penalties if WHEA causes them.

Chipset Gen 3 because I think that is what @Veii advised I try above. I'm learning towards it maybe being this? Only issue if it's this is worrying what speeds my NVMe drive is now running at... IIRC it works off the CPU channel on the B550 to get full PCIE 4.0 whilst allowing the GPU to retain 16x. But if the chipset is set to 3.0 I presume this will now throttle my NVMe 🤮

But for now I'll just let this test run a full hour and monitor USB. My voltages aren't even high, they're actually set at what my 3800 profile is lol. Because I had to redo all my BIOS settings I forgot to bump up VSOC a little and the rest for 4000/2000. Effectively proving I likely didn't even need any more VDDG or VSOC to run this over 3800/1900.

*edit* - Damn, commander pro "blew up" at 21 minutes in, but that is massive progress over 1~2 minutes and USB issues. Now to see what setting helped.


----------



## Veii

Audioboxer said:


> Ommmg I think I've stopped my USB drop outs! I don't want to touch the PC just now lmao, 7 minutes into an OCCT CPU small test and no drop outs so far.
> 
> I only changed two things over last failed run, CLKREQ# to enabled and Chipset to Gen 3. The CLKREQ# to enabled under PBS I don't even know what it does but another poster advised it to help with performance penalties if WHEA causes them.
> 
> Chipset Gen 3 because I think that is what @Veii advised I try above. I'm learning towards it maybe being this? Only issue if it's this is worrying what speeds my NVMe drive is now running at... IIRC it works off the CPU channel on the B550 to get full PCIE 4.0 whilst allowing the GPU to retain 16x. But if the chipset is set to 3.0 I presume this will now throttle my NVMe 🤮
> 
> But for now I'll just let this test run a full hour and monitor USB. My voltages aren't even high, they're actually set at what my 3800 profile is lol. Because I had to redo all my BIOS settings I forgot to bump up VSOC a little and the rest for 4000/2000. Effectively proving I likely didn't even need any more VDDG or VSOC to run this over 3800/1900.
> 
> *edit* - Damn, commander pro "blew up" at 21 minutes in, but that is massive progress over 1~2 minutes and USB issues. Now to see what setting helped.


Seems to be a vendors bug
CLKREQ# on MSI boards seem to be needed, but @ManniX-ITA has far more experience
B550 links towards PCH have to be 3.0
I wanted to advice to push it to 3.0 - but they should be.
X570 links to PCH are 4.0, hence it can split them better later. I think PCH does mux 4.0 to 3.0 but not entirely confident

Anywho, you should run 3.0 to it at any point
There shouldn't even be an option for 4.0

Link to M.2 CPU, X16 and then PCH that spreads to IO ~ are all unique links / unless your m.2 sits on a PCH connected slot
With unique powermanagement in them
But as mentioned, hence you use the 3.10 Chipset update
Also enforce this















USB 3.1 wasn't affected by the dropouts at all, and shouldn't be affected by any patches

Else really, test around DPM links and actually "disable" AMD OVERCLOCKING ,LCLK DPM for PCIe - now that you run it on 3.0
This can cause issues
I would also once test without the PCIe extender, if USB issues are gone.
Because it can also be that PCIe extender, does require absurd LCLK clock , and that destabilizes everything ~ tho still on pcie 3.0 mode


----------



## umea

How can I upgrade the SMU on our board veii? I'm on 56.50.00 lol. What does the update fix?


----------



## XPEHOPE3

Veii said:


> Zentimings tho, has issues
> 
> 
> 
> 
> 
> 
> 
> 
> Any anomaly ?


What anomaly are you referring to? Can't see any as well as a reason for TB screenshot


----------



## Veii

XPEHOPE3 said:


> What anomaly are you referring to? Can't see any as well as a reason for TB screenshot


Left what is inside, right what is detected 
It remembered and loaded wrong dimms - bottom left of ZT


umea said:


> How can I upgrade the SMU on our board veii? I'm on 56.50.00 lol. What does the update fix?


The locations of the "data" is visible on SMU-Checker
Usually you shouldn't touch this, as it can very well fail verification and soft-brick the board. Unless you can flashback


----------



## Audioboxer

Veii said:


> Seems to be a vendors bug
> CLKREQ# on MSI boards seem to be needed, but @ManniX-ITA has far more experience
> B550 links towards PCH have to be 3.0
> I wanted to advice to push it to 3.0 - but they should be.
> X570 links to PCH are 4.0, hence it can split them better later. I think PCH does mux 4.0 to 3.0 but not entirely confident
> 
> Anywho, you should run 3.0 to it at any point
> There shouldn't even be an option for 4.0
> 
> Link to M.2 CPU, X16 and then PCH that spreads to IO ~ are all unique links / unless your m.2 sits on a PCH connected slot
> With unique powermanagement in them
> But as mentioned, hence you use the 3.10 Chipset update
> Also enforce this
> View attachment 2530465
> View attachment 2530466
> 
> USB 3.1 wasn't affected by the dropouts at all, and shouldn't be affected by any patches
> 
> Else really, test around DPM links and actually "disable" AMD OVERCLOCKING ,LCLK DPM for PCIe - now that you run it on 3.0
> This can cause issues
> I would also once test without the PCIe extender, if USB issues are gone.
> Because it can also be that PCIe extender, does require absurd LCLK clock , and that destabilizes everything ~ tho still on pcie 3.0 mode


It is CLKREQ# which helped, it got me to 21 minutes before my commander pro freaked out and said a FW update was available for my "generic device". Funnily enough keyboard was fine, my mouse was fine and the commander pro didn't lose profiles. Going to turn off all USB power saving settings and edit my power plan like you advised  Commander pro connects directly to USB slot on the motherboard.










I double checked the bios, that is what I set to Gen3, but I did it soo quickly I didn't even notice 1st time it has no Gen4 option lol. So, back to auto it goes. I don't even know if that is the proper PCH setting, this is called Chipset Gen Switch.










These are my voltages right now, I'll maybe increase VSOC slightly and IOD to 1.06v and see if that helps with whatever my commander pro was unhappy about after 20 minutes. But I'm running an OCCT test first with just the power plan changes/USB device manager changes.

Edit - Just rebooted to fix tWR to 14 lol. It was that way before BIOS update. Getting late and I'm making mistakes 🤣


----------



## XPEHOPE3

Veii said:


> Left what is inside, right what is detected
> It remembered and loaded wrong dimms - bottom left of ZT


I thought that was the usual Thaiphoon Burner bug of reporting something wrong about the memory


----------



## Veii

XPEHOPE3 said:


> I thought that was the usual Thaiphoon Burner bug of reporting something wrong about the memory


Generally should just show, that you can not trust tPHYRDL "changing" on user settings change
It can need a full CMOS reset before it won't remember any old WMI logs
1rusanovBG, wants to later implement proper SPD reading ~ but it's i think good to know that you can not relate on tPHYRDL being always correctly reported


----------



## XPEHOPE3

Veii said:


> but it's i think good to know that you can not relate on tPHYRDL being always correctly reported


I think it's only related to switching DIMMs which I never did. Whenever I saw "bad" tPHYRDL it also manifested as higher AIDA latency meaning ZenTimings reported tPHYRDL correctly (since that was the only thing changed)


----------



## MrHoof

Veii said:


> Generally should just show, that you can not trust tPHYRDL "changing" on user settings change


Can confirm it happend once were i had to aleast "force" a memory training by changing trdwr to auto to get it train correctly after going to low with VDDP and getting a missmatch, just fixing to VDDP to known working wasnt doing it.


----------



## Audioboxer

Just ran a y-cruncher HNT test and all my USB devices didn't spontaneously combust like they used to! Major progress with CLKREQ#. It would be good if @ManniX-ITA gets a minute to explain how it helps or what it does? Also any extra help with USB issues would help <3

Unfortunately about a minute into HNT I "lost" my mouse again, so USB issues persist, but they're like 80%+ better than before. Previously when I ran HNT everything blew up in a second, I'm talking keyboard, mouse, commander pro and more turning on/off/on/off/on/off like a rapid fire controller lol.

One thing I'm a bit confused about though is the motherboard USB connectors seem to be USB 2.0, that is what my commander pro connects to. So we're talking a USB 2.0 connection freaking out.










Commander pro connects to one of these. Unless 2.0 is affected just as 3.0 is?


----------



## XPEHOPE3

Veii said:


> It remembered and loaded wrong dimms - bottom left of ZT


So you are saying ZT read all the values from old memory or just some or just name of old memory? If it read all the values from old setup, it means exactly that one cannot trust ZT after switching DIMMs, not that one cannot trust ZT on reading any individual value like tPHYRDL.


----------



## Audioboxer

Okay here is something easily reproduced I should have picked up on way before now. 

If I run y-cruncher test 17, HNT, on 4000/2000 then the mouse pointer basically becomes unusable and lags/jerks around the screen.

If I run the same test on my 3800/1900 profile you couldn't even tell anything was running, mouse movement is the same as it always is.

Not sure if this is a consequence of WHEA spam but the same happens with OCCT. Mouse basically becomes unusable when a test is running.

Can anyone running 2000+ FCLK test y-cruncher or even OCCT for me and let me know if your mouse pointer remains responsive?


----------



## error-id10t

I'm running AGESA ComboV2 1.2.0.4 A with SMU 56.58.

This gets updated with BIOS right, anything wrong with running this? I've seen posts hinting 1.2.0.4 is a mess and nobody is running my SMU level.


----------



## Audioboxer

error-id10t said:


> I'm running AGESA ComboV2 1.2.0.4 A with SMU 56.58.
> 
> This gets updated with BIOS right, anything wrong with running this? I've seen posts hinting 1.2.0.4 is a mess and nobody is running my SMU level.


1.2.0.4 caps VDDG voltages to a maximum of 1.0v. Quite a lot of people run IOD higher than 1.0v so that's why it can cause issues.

You've reminded me, I might try 1.2.0.4 again just to see if MSI updated the SMU. 1.0v on IOD might be too low for 2000 FCLK but I'd be interested to quickly check if a higher SMU helps with USB issues....


----------



## dk_mic

Audioboxer said:


> Yeah you can export but they don't let you import an older BIOS profile into newer one. Speaking of a new BIOS version
> 
> View attachment 2530462
> 
> 
> MSI haven't updated this board to SMU 56.53 :/
> 
> *edit *- Just noticed you mentioned you know MSI downgraded. I wouldn't even want to begin to try and mess with a BIOS file so unless someone else can do it I guess I'll just have to hold off till MSI put out a BIOS with a newer SMU version lol.
> 
> My BIOS is the same as the versions you posted other than SMU FW version.


They have downgraded. You can probably flash 7D13vA3, which should have 56.53.0
My X570 Unify, cba to update right now:


----------



## Melan

@Veii Could you clarify one thing please? In ryzen google calc the tFAW field has A-1 (512B page size), A-2 (1KB page size) and A-3 (2KB page size) options. I've checked the datasheet for my ICs (H5AN8G8NCJR) and it says page size is 1KB.
I will make a wild guess that I should be using the A-2 option, but it seems A-1 wasn't making any problems so far. Is there any difference? Should I change tFAW to 20 (A-2), instead of 16 (A-1) which I have right now?


----------



## Veii

XPEHOPE3 said:


> So you are saying ZT read all the values from old memory or just some or just name of old memory? If it read all the values from old setup, it means exactly that one cannot trust ZT after switching DIMMs, not that one cannot trust ZT on reading any individual value like tPHYRDL.


ZT did read an old in bios stuck preset and DIMM information about it
This means because XMP also tracks tCCD_ and so also tREFI + tMAC.MAW , (RC_PAGE) ~ that prediction will be 99% messed up
Once on Memory Interleaving side, BankGroupSwap side and clearly on RTT + Remain tPHYRDL/tMRD behavior

It doesn't mean that ZT is the issue, but that the AGESA is a mess right now
Else yes, you can not trust them on a missmatch & you can not trust that they will be accurate or even change on user powering-change 
(we never know if they have changed that way and what really is reported or just WMI stuck cached result)
This is an issue. But it's not purely ZT's fault

I'm still hunting an unknown issue, where memory loses 6000MB/s performance without any visible change ~ and why i put at first ZT under fire
Yet ZT ended up showing that it does function on 2DPC boards ~ just that the bios can not be trusted.
Every reboot and profile load it showed different bandwidth results ~ this was on the tRRD_ testing post 1? month ago


Melan said:


> @Veii Could you clarify one thing please? In ryzen google calc the tFAW field has A-1 (512B page size), A-2 (1KB page size) and A-3 (2KB page size) options. I've checked the datasheet for my ICs (H5AN8G8NCJR) and it says page size is 1KB.


Not 100% sure, you'd have to ask Anta or chitos for DDR specifications
But if it lists it as default JEDEC being 350-260-160ns instead of 550-350-260ns
Then you can keep using A1 the common for 8x1024 IC's
In general also Dual Rank ended up with the same - soo 2 sided 8x1024mb IC = A-1 preset
only for 2048MB ICs such changes and is written as "High Density B-2"

Also meaning, the same mini module and google calculator remain functioning for 2x (8x1024mb) dimms


----------



## Audioboxer

Audioboxer said:


> Okay here is something easily reproduced I should have picked up on way before now.
> 
> If I run y-cruncher test 17, HNT, on 4000/2000 then the mouse pointer basically becomes unusable and lags/jerks around the screen.
> 
> If I run the same test on my 3800/1900 profile you couldn't even tell anything was running, mouse movement is the same as it always is.
> 
> Not sure if this is a consequence of WHEA spam but the same happens with OCCT. Mouse basically becomes unusable when a test is running.
> 
> Can anyone running 2000+ FCLK test y-cruncher or even OCCT for me and let me know if your mouse pointer remains responsive?


Had someone else confirm to me they can run y-cruncher test 17 at 2000 FCLK and their mouse doesn't become unresponsive. Not sure what to think, either the amount of WHEA 19s I'm getting is causing unresponsiveness or there is some more serious performance regression happening for me.

Going to try an older MSI bios with the newer SMU just to see if it does anything and then I'll consider reinstalling Windows 10 just to see if WHEA suppression helps with anything. Ultimately if I cannot stop the USB disconnects completely this issue is secondary even its linked, but it's such a jarring difference between 1900/3800 and 2000/4000 I want to investigate it anyway.

Something else I have noticed is when I run y-cruncher or even OCCT at 2000/4000 I can hear a slight whining noise, almost like a VRM noise but it's more higher pitched than say, like the sound of my 2080Ti VRM when it's pushed hard. The 2080Ti is very audible and more like a buzzing. I cannot hear this at 1800/3800. I'm going to guess it's my motherboard VRMs? People have said the B550 Unify X can have noisy VRMs, although I've never heard mine before. I don't think USB can "make noise" lmao, so that's my best guess. Still something interesting I've noticed that further highlights to me something is up at 2000/4000.

Edit - Older bios doesn't help, even AGESA 1.2.0.4 doesn't make a difference. Going back to Windows 10 now.


----------



## Audioboxer

Back on Windows 10, should have stayed here, might not be as pretty as Windows 11 but just feels more responsive and at least memory benches aren't screwed up.

Bad news for FCLK 2000 is even with WHEA suppressor it makes no difference to the extremely laggy USB performance I get when stress testing the CPU and there are still USB dropouts. Was hoping even if there were dropouts the performance wouldn't nuke itself, but it still does. If I run OCCT CPU test or y-cruncher the mouse still becomes near unusable and I get horrendous lag.

Guess I'm out of luck trying to run anything above 1900 FCLK. Can do memory stability tests/benchmarks, but anything hitting the CPU hard causes the whole PC to meltdown. If AMD don't improve things with the 3D cache or whatever it ends up being called I guess all eyes on Intel for next-gen, because leaving all this memory performance on the table hurts.


----------



## Blameless

Veii said:


> Else really, test around DPM links and actually "disable" AMD OVERCLOCKING ,LCLK DPM for PCIe - now that you run it on 3.0


The LCLK controls aren't just for the PCH and if you don't have at least 2-1-1-2 (which is, IIRC, the what the AMD OC setting for PCI-E 4.0 stuff will do) it will hit PCI-E 4.0 GPU slot bandwidth...which may or may not be worth it, depending on card and use case.



Audioboxer said:


> If I run y-cruncher test 17, HNT, on 4000/2000 then the mouse pointer basically becomes unusable and lags/jerks around the screen.
> 
> If I run the same test on my 3800/1900 profile you couldn't even tell anything was running, mouse movement is the same as it always is.
> 
> Not sure if this is a consequence of WHEA spam but the same happens with OCCT. Mouse basically becomes unusable when a test is running.


It's not a consequence of WHEA spam, that WHEA spam is a consequence of having to correct fabric or related errors. Those warnings aren't nothing, if they were, they would always be there at any FCLK, but they aren't, because at a low enough FCLK there aren't any errors to be corrected/resent.

Too many errors, even correctable ones, even if you don't allow the events to be reported, will cause problems, which is probably what you're seeing.



Audioboxer said:


> Can anyone running 2000+ FCLK test y-cruncher or even OCCT for me and let me know if your mouse pointer remains responsive?


I can't run 2000 stable enough to do anything, but I can run 1933/1967 and I get a similar experience you're having at 2000. At 1933 heavy loads will cause my mouse to chop up and random USB disconnects. 1967 on my current part will still past CPU/memory stress tests, but USB devices are all but completely unusable.


----------



## Audioboxer

Blameless said:


> The LCLK controls aren't just for the PCH and if you don't have at least 2-1-1-2 (which is, IIRC, the what the AMD OC setting for PCI-E 4.0 stuff will do) it will hit PCI-E 4.0 GPU slot bandwidth...which may or may not be worth it, depending on card and use case.
> 
> 
> 
> It's not a consequence of WHEA spam, that WHEA spam is a consequence of having to correct fabric or related errors. Those warnings aren't nothing, if they were, they would always be there at any FCLK, but they aren't, because at a low enough FCLK there aren't any errors to be corrected/resent.
> 
> Too many errors, even correctable ones, even if you don't allow the events to be reported, will cause problems, which is probably what you're seeing.
> 
> 
> 
> I can't run 2000 stable enough to do anything, but I can run 1933/1967 and I get a similar experience you're having at 2000. At 1933 heavy loads will cause my mouse to chop up and random USB disconnects. 1967 on my current part will still past CPU/memory stress tests, but USB devices are all but completely unusable.


Yeah I know it's not nothing, but most people see them and I guess a few lucky find a way to stabilise USB even with the auto-correcting.

But thanks for confirming you see the same USB basically becoming unusable when doing heavy CPU loads/stability testing.

*edit* - You gave me a good idea to try 1933 IF, and yeah, exact same result as 2000. The second I step over 1900 the USB lag happens.


----------



## Veii

Blameless said:


> The LCLK controls aren't just for the PCH and if you don't have at least 2-1-1-2 (which is, IIRC, the what the AMD OC setting for PCI-E 4.0 stuff will do) it will hit PCI-E 4.0 GPU slot bandwidth...which may or may not be worth it, depending on card and use case.


I ment inside AMD OVERCLOCKING
There is LCLK Global and LCLK PCIe enchanced detection
PCIe enchanced detection is only for PCIe 4.0 devices , to push it to 619mhz


----------



## Audioboxer

Outright disabling PBO seems to seriously improve mouse pointer performance whilst something like OCCT is running. It's smooth now for about 2-3 seconds and then there is a lag. Opposed to being almost unusable instantly.

USB devices also seemed to last a fair bit longer before first disconnect. I've got the CCD voltage as low as 0.9v right now, the same as VDDP. IOD between 1.0 and 1.05v.

If it's PBO being disabled that's helping I guess that is because the CPU is under less strain/power draw. Meaning it handles correcting WHEA errors easier if its not using PBO?

I also just flat out disabled the LCLK options so dunno if that's also helping lol. I'd gather it's PBO being off doing the most though. Which sucks given the performance uplift from a well tuned curve/PBO but first thing is first, continuing to see if USB disconnects can be eliminated with PBO disabled.

Disabling PBO and then running OCCT also seems to have severely diminished the whining noise I could hear from my case. I can't hear it at 1900/3800 at all, even with PBO. I'm guessing it's the motherboard VRM. Again potentially suggesting struggling with PBO at FCLK 2000.

*edit* - Just made it 25 minutes before the first USB disconnect in OCCT with these voltages and PBO disabled










So I guess I'll marginally play around with voltages and see if anything can get me through an hour.

*edit2* - Next finding, CPU 1P8 voltage has an extremely negative effect on USB/mouse performance if set to 1.9v. Talking lagging on desktop without anything running. Can run fine at 1.9v at 3800/1900, but quite clearly with a higher IF it's not only stopping scaling but causing performance issues/USB issues. I went the other way and brought it down under 1.8v to like 1.77v and this also produced USB lag/mouse pointer lag on the desktop.


----------



## Audioboxer

Alright, giving up again for now, but here are my best settings so far and findings










PBO disabled seems to have helped quite a bit in stabilising during CPU tests. I can only presume this is due to less power draw.

VTT or as its named in bios, CPU 1P8 voltage has a large impact on USB/mouse lag. Too low or too high and I lag on desktop, without even doing anything. Some sort of sweet spot "in the middle", around 1.8v, as default, or just over and mouse is mildly more responsive during testing, but still lags. Haven't found any way to completely stop mouse pointer lag during OCCT/y-cruncher.

VSOC doesn't seem to do much between 1.15~1.20v, going up to like 1.25v seems to hurt stability.

CCD seems to prefer being lower. 0.975v is where I left it for ages, but for whatever reason when battling FCLK 2000 it prefers to be down at 0.9~0.93v.

IOD is a challenge to nail down, too high and it's hopeless, but down low and it's hard to tell if it's any worse than around 1.05v. As much as its stated to be the "one to increase to stop USB dropouts", it really doesn't seem to be a silver bullet at all.

With settings above OCCT might run 20+ minutes before a USB disconnect, so y-cruncher test 17, HNT, is still the quickest way to get a USB disconnect. With the settings above I almost managed 2 full cycles (about 4~5 minutes), which is major progress from where I started this journey which was the second the test began all USB devices went utterly crazy.

Still don't think I'll be able to stop USB disconnects, it simply seems the CPU cannot handle correcting WHEA and being put under a heavy load. Which makes it utterly useless for daily running. Played some games and everything seems fine, but the CPU just seems a basketcase waiting to happen if stability testing apps can disconnect USB devices in minutes in the case of y-cruncher and within 20 minutes for OCCT small CPU.

I've seen a lot of TM5 screenshots out there of people on FCLK 2000+, something I can do no problem and that was with PBO enabled and a lot of other BIOS settings not changed I have now changed. I bet if most of them were made to run y-cruncher test 17 they would not be "stable"  USB disconnects seem to be the real problem at 1933+, not so much actually failing stability testing apps. TM5 and Karhu clearly don't hammer the CPU hard enough to produce USB disconnects (unless you maybe are super unstable). I don't have ANY mouse lag when running these apps. Fire up OCCT and/or y-cruncher and it's a different story with mouse lag.


----------



## MrHoof

I am also trying my luck with pushing fclk at the moment, did anyone ever had whea id19 with "Error source: Corrected Machine Check" instead of unknown error source?
I start getting those at 2000fclk.


----------



## MrHoof

Its kinda difficult to balance the CO when the cores behave so massive diffrently  look at that core 5 max power draw.









edit: oops this wasnt meant to be posted here.


----------



## Blameless

Veii said:


> I ment inside AMD OVERCLOCKING
> There is LCLK Global and LCLK PCIe enchanced detection
> PCIe enchanced detection is only for PCIe 4.0 devices , to push it to 619mhz


Yeah, I know. I'm saying that I'm pretty sure they are manipulating the same underlying settings.

The "2"s you can set in the manual DPM values are 619MHz, while "1"s are 300-something. The PCI-E 4.0 thing in AMD overclocking overrides the DPM values to at least 2-1-1-2, because that's the lowest setting that will enable full PCI-E 4.0 bandwidth to the CPU supported PCI-E lanes (tested with GPU and SSD PCI-E benchmarks). Basically, it's a less aggressive low-power state to make sure PCI-E 4.0 GPUs don't see any performance hit. At least as far as I can tell.



Audioboxer said:


> I also just flat out disabled the LCLK options so dunno if that's also helping lol.


I'd expect them to run full speed (2-2-2-2) if you disabled all the LCKL DPM. If it does anything, I would expect it to hurt, due to greater LCLK to fabric load. Anedotally, 2-1-1-2, or less, does seem to result in fewer errors at high FCLK with my samples, but isn't enough to make any higher FCLKs stable.


----------



## Audioboxer

Blameless said:


> Yeah, I know. I'm saying that I'm pretty sure they are manipulating the same underlying settings.
> 
> The "2"s you can set in the manual DPM values are 619MHz, while "1"s are 300-something. The PCI-E 4.0 thing in AMD overclocking overrides the DPM values to at least 2-1-1-2, because that's the lowest setting that will enable full PCI-E 4.0 bandwidth to the CPU supported PCI-E lanes (tested with GPU and SSD PCI-E benchmarks). Basically, it's a less aggressive low-power state to make sure PCI-E 4.0 GPUs don't see any performance hit. At least as far as I can tell.
> 
> 
> 
> I'd expect them to run full speed (2-2-2-2) if you disabled all the LCKL DPM. If it does anything, I would expect it to hurt, due to greater LCLK to fabric load. Anedotally, 2-1-1-2, or less, does seem to result in fewer errors at high FCLK with my samples, but isn't enough to make any higher FCLKs stable.


Thanks. Quite a bit of learning for me to do over the past 24 hours, mainly because I've never tried to properly stabilise FCLK above 1900 before. Going to ease off though, given the quite clear USB lagging I am seeing when CPU is under extreme load, coupled with the disconnects, I don't think I'll be getting this 5950x stable unless there are improvements with AGESA/from AMD. Fun to do memory stability/benching though, it is at least do-able and it lets you know how far your ram can be pushed! Then you get annoyed seeing how much performance is left on the table 

More than likely, knowing AMD, this is the end of the line and the only option will be buying their new CPUs next year. Who knows if USB issues will even be gone by then, chances are it's going to take next-gen, not just the 3D cache refresh. Seems these motherboards and Zen 3 will simply be plagued with USB issues as a design flaw.


----------



## PJVol

XPEHOPE3 said:


> So you are saying ZT read all the values from old memory


When experimenting with 4 dimms - 2 different gskill kits, lets call them "red" and "black" ), after the kits were swaped in A/B slots or only one kit was left, following by reboot, ZT might often show "red" kit in bottom drop down menu occupating both channels, whereas "black" is actually plugged in.


----------



## Veii

Blameless said:


> I'd expect them to run full speed (2-2-2-2) if you disabled all the LCKL DPM. If it does anything, I would expect it to hurt, due to greater LCLK to fabric load.


The moment i disabled LCLK DPM, THM sensor, as also common powerreporting bugged out
Sadly this didn't fix procHot throttle


----------



## rom.clown

Hello
this is my stable setting that i use for so far,


and i just up the speed to 3200 with same settings (xmp timing + trfc 440 + auto everything else). voltage 1.35v, soc auto at 1.1v
and it can boot up


Memory kit : CMK16GX4M2B3000C15
Micron B-Die 

jika saya menghadapi ketidakstabilan, urutan pengaturan seperti apa yang harus saya ubah?


----------



## mongoled

Audioboxer said:


> Cheers. Just goes to show WHEA/AMD IF crappyness really limits memory performance
> 
> I presume OCCT uses similar stressing to HNT.
> 
> View attachment 2530451
> 
> 
> Small CPU test drops the WHEA error detected as well. In event viewer there is no red crosses, it's "just" event 19 warnings, so I'm not sure if it's normal for WHEA error spam in OCCT and the test is just to be left running?
> 
> As I get USB funkiness I stop it anyway otherwise all sorts of chaos will go on lol.
> 
> If anyone else has experience running with WHEA please let me know if you get to a point where you have no WHEA errors in OCCT despite the warning event 19s still happening, or if OCCT will always throw up a WHEA error.
> 
> View attachment 2530452
> 
> 
> Corecycler is running fine, no USB issues, but it's really just testing 1 core at a time... I pumped my voltages up, I don't even know if IOD is "safe" at 1.15v but OCCT still has a hard time.


Is OCCT small CPU test meant to run like this ??

All the cores boost and hold the boost for several seconds then drop to idle and the cycle continues


----------



## mongoled

@Veii

Its looking like setting CsOdtDrvStr to 40 ohms resolves my non posting issue from either warm or cold boot.

Still needs more extended testing to confirm its the "fix" when running 4066/2033, however I experienced something ive not seen before as its the first time ive set this value to 40 ohms and that was a reboot when running TM5.

Ive adjusted tCKE to 11 from 1 which I was using previously, ive also set ProcODT to AUTO which has selected 36.9 ohms (it was previously on 34.3 ohms).

Any insight on how to "tame" CsOdtDrvStr, with regards to the reboot when running TM5 ?


----------



## Audioboxer

mongoled said:


> Is OCCT small CPU test meant to run like this ??
> 
> All the cores boost and hold the boost for several seconds then drop to idle and the cycle continues
> 
> View attachment 2530630


Seems to be a consequence of WHEA/issues with FCLK










Runs fine for me at 1900/3800.

I presume you get mouse pointer lag as well when it's running?

You could also try updating to the latest version.


----------



## mongoled

Audioboxer said:


> Seems to be a consequence of WHEA/issues with FCLK
> 
> View attachment 2530632
> 
> 
> Runs fine for me at 1900/3800.
> 
> I presume you get mouse pointer lag as well when it's running?
> 
> You could also try updating to the latest version.


No lag when OCCT is running in crippled mode

😂😂

Let me use those same settings as the screenshot you posted, mine is set to use 0 MB

😂😂


----------



## Audioboxer

mongoled said:


> No lag when OCCT is running in crippled mode
> 
> 😂😂
> 
> Let me use those same settings as the screenshot you posted, mine is set to use 0 MB
> 
> 😂😂


Could just be throttling at 80 degrees but it should be happy to go above that?


----------



## mongoled

Audioboxer said:


> Could just be throttling at 80 degrees but it should be happy to go above that?


New version is working fine



Thank goodness I didnt want to be on another wild goose chase

😂 😂

How long do you want me to run this ??


----------



## Audioboxer

mongoled said:


> New version is working fine
> 
> 
> 
> Thank goodness I didnt want to be on another wild goose chase
> 
> 😂 😂
> 
> How long do you want me to run this ??


If you're on FCLK 1933+ and have no mouse lag issues and no USB issues then just stop right away lol. I get them instantly on anything above 1900, well, mouse lag can be instant, USB disconnects can be anywhere from 2 mins in to around 20 minutes.

My mouse is wireless over USB, so obviously the WHEA spam and pressure on the CPU is causing latency issues. I guess if people have wired mice they might not be impacted as much as me, but even putting aside the mouse cursor lag, my longest run without a USB disconnect was only 21 minutes.

I guess I should have thought about plugging my mouse in directly over USB and see if that at least clears the mouse lag up.


----------



## mongoled

Audioboxer said:


> If you're on FCLK 1933+ and have no mouse lag issues and no USB issues then just stop right away lol. I get them instantly on anything above 1900, well, mouse lag can be instant, USB disconnects can be anywhere from 2 mins in to around 20 minutes.


No mouse lag, nothing.

I get what you are experiencing but not in the same way as yours when running 4133/2067, it happens occasionally that the mouse will get "stuck" momentarily. I also get audio "quirks", slight anomaly a "scratching" noise is in the audio.

Keep meaning to ask you, have you not played with the PCH voltage ??

There are two settings for voltages in the MSI main voltage adjustment section, cant remember the names of the top of my head, one is for the chipset CLDO and the other is ...... nope not coming to me (the name)

🤣

Let OCCT run for 8 mins, no issue with WHEA or mouse lag, back to TM5 !


----------



## Audioboxer

mongoled said:


> No mouse lag, nothing.
> 
> I get what you are experiencing but not in the same way as yours when running 4133/2067, it happens occasionally that the mouse will get "stuck" momentarily. I also get audio "quirks", slight anomaly and the sound, a "scratching" noise.
> 
> Keep meaning to ask you, have you not played with the PCH voltage ??
> 
> There are two settings for voltages in the MSI main voltage adjustment section, cant remember the names of the top of my head, one is for the chipset CLDO and the other is ...... nope not coming to me (the name)
> 
> 🤣


Yeah you described it better than I ever have, the mouse pointer getting "stuck" momentarily. Lag makes it sound like it's just consistently slow going around the screen, it's more it gets stuck, then zooms to catch up to where it should be. Jerking or getting stuck, more than lagging.

Playing around with CPU 1.8 has quite a large impact on my mouse. Different voltages took the mouse from basically unusable to gets stuck ever 2nd or 3rd second for like half a second. 1.83~1.86v probably the best, going higher ended up worse, as did going under 1.8v.

The PCH voltage is the one that is normally at 1.05v on auto isn't it? I think I briefly tried increasing it a bit, but I didn't play around with it much as most of the focus was on VDDG. But I came to find out VDDG really has little impact if it's not the source of issues. Other than me finding out it seems lower CCD helps a bit when pushing FCLK. IOD seemed to have very little impact, because I don't get audio issues. It also didn't seem to do much for the USB disconnects under heavy CPU load.

What do you run PCH voltage at?


----------



## mongoled

Audioboxer said:


> Yeah you described it better than I ever have, the mouse pointer getting "stuck" momentarily. Lag makes it sound like it's just consistently slow going around the screen, it's more it gets stuck, then zooms to catch up to where it should be. Jerking or getting stuck, more than lagging.
> 
> Playing around with CPU 1.8 has quite a large impact on my mouse. Different voltages took the mouse from basically unusable to gets stuck ever 2nd or 3rd second for like half a second. 1.83~1.86v probably the best, going higher ended up worse, as did going under 1.8v.
> 
> The PCH voltage is the one that is normally at 1.05v on auto isn't it? I think I briefly tried increasing it a bit, but I didn't play around with it much as most of the focus was on VDDG. But I came to find out VDDG really has little impact if it's not the source of issues. Other than me finding out it seems lower CCD helps a bit when pushing FCLK. IOD seemed to have very little impact, because I don't get audio issues. It also didn't seem to do much for the USB disconnects under heavy CPU load.
> 
> What do you run PCH voltage at?


Great! Now we are on the same page!

I thought your issue was with the mouse lagging all the time....

Unfortunately I could not find a solution other than dropping FCLK, I have stable 4133/2067 configs, only issue is the mouse and audio, its just not consistent, after one reboot it will run OK, then on the next the issues crop up.

I tried really hard to resolve that but alas could not find a reliable solution, you see, 4133/2067 would post correctly 70 % of the time and sometimes higher, but 4066/2033 its hit and miss, sometimes it will post fine for consecutive posts and then all of a sudden, boom, you need several warm/cold posts to get it to post again.

Really hope the cure is increasing CsOdtDrvStr !

I leave PCH values on default, thought you should give them a try


----------



## Audioboxer

mongoled said:


> Great! Now we are on the same page!
> 
> I thought your issue was with the mouse lagging all the time....
> 
> Unfortunately I could not find a solution other than dropping FCLK, I have stable 4133/2067 configs, only issue is the mouse and audio, its just not consistent, after one reboot it will run OK, then on the next the issues crop up.
> 
> I tried really hard to resolve that but alas could not find a reliable solution, you see, 4133/2067 would post correctly 70 % of the time and sometimes higher, but 4066/2033 its hit and miss, sometimes it will post fine for consecutive posts and then all of a sudden, boom, you need several warm/cold posts to get it to post again.
> 
> Really hope the cure is increasing CsOdtDrvStr !
> 
> I leave PCH values on default, thought you should give them a try


If your USB devices remain stable I guess it's not as much of a killer as the issues I end up facing. As I said the furthest I could run OCCT and not see a USB drop out was like 20 minutes. I played a game for a bit and it was fine, but feels like a ticking time bomb for my commander pro or mouse just randomly disconnecting/reconnecting. I know OCCT and y-cruncher push the CPU incredibly heavy, whereas gaming is actually quite light on the CPU, but I don't feel comfortable running a PC daily if it can't pass the heavy CPU stability apps. Well, it technically hasn't failed them as the stability apps keep running fine themselves, but USB going crazy is as good as a stability fail.

As I mentioned right at the start, Karhu and TM5 don't give me any issues, but they obviously don't crunch the CPU quite as heavy as OCCT/prime95/y-cruncher. Another thing I found was disabling PBO seemed to help a bit, further compounding it becoming clear WHEA just does too much "damage" to this CPU to really be bruteforced into daily use. Best just to stay at 1900/3800 and hope AMD stop being a terrible software developer and/or have to accept their next revision where the marketing translates into "We finally fixed WHEA, it was a hardware issue, but we'll market it as 3d cache"


----------



## mongoled

@Audioboxer 
Whats is your 5v railing showing when you run OCCT ?


----------



## Mach3.2

@Audioboxer Maybe you should get people with dual CCD chips to test for USB bugs at above 1900MHz FCLK. Considering the observation that there are more single CCD chips that seem to be able to clock the infinity fabric above 1900MHz WHEA free but very few dual CCD chips can do the same, I suspect the same trend might apply to your USB bug.


----------



## Audioboxer

mongoled said:


> @Audioboxer
> Whats is your 5v railing showing when you run OCCT ?


For FCLK 2000 or at 1900?










1900 sits at 5.010v when OCCT is running, will check 2000 shortly.



Mach3.2 said:


> @Audioboxer Maybe you should get people with dual CCD chips to test for USB bugs at above 1900MHz FCLK. Considering the observation that there are more single CCD chips that seem to be able to clock the infinity fabric above 1900MHz WHEA free but very few dual CCD chips can do the same, I suspect the same trend might apply to your USB bug.


Possibly yeah. I'm definitely not WHEA free, it's only WHEA free up to 1900. Anything above that I get WHEA 19. But some people seem to be able to run "stable" with WHEA 19 with no performance regression, whereas I can pass memory stability test apps and for as long as I've let them run, pass CPU stability testing, but the USB disconnects come quickly with CPU testing.

I'd guess if I could stop the USB issues I might have a chance at performance regression free 1933+. I at least don't have a 2CCD chip with FCLK holes, and it does do 1900 easily, WHEA free, so I shouldn't moan much. But after seeing memory benches with 4000 and seeing hours of TM5/Karhu passing, it's annoying 

ManniX-ITA seems to have a 5950x and has stopped his USB issues and has no performance penalties with WHEA, but the voltages he ended up using cause me MORE issues WHEAService, WHEA errors suppressor - unleash Ryzen...



> My 5950x works best at CCD/IOD/SOC voltages 1050/1080/1180 at FCLK 1900.
> That's not enough for FCLK 2000, needs 1080/1140/1250.


I mean, here is me at 1900










Going to FLCK 2000, pushing CCD that high for me causes instability. I know all chips are different, but here we have two 5950x and one seems to love having a lot of voltage pumped into it, whereas mine seems to get more unstable with "too much" voltage. IIRC Manni is on a B550 Unify X as well.

I was even trying CCD as low as 0.9v at FLCK 2000 simply because lower seemed to be helping out. From doing some reading online it actually seems to not be uncommon going lower with CCD might help with high FCLK instability, whereas IOD tends to like being kept around 1.05v+.


----------



## Audioboxer

Does anyone know if it would be normal FCKL2000 could cause my motherboard VRMs to whine? I mentioned it a few times in amongst my posts but I definitely hear a high pitched whine noise when using OCCT CPU test at FCLK2000 that I don't hear at FCLK1900.

Possibly just a consequence of the IF/CPU being more strained?

The B550 Unify X is supposed to have a noisy VRM, or it's common anyway, but mines is genuinely silent at 1900, even under heavy load.

*edit *- My thought is I wonder if anything that is on AUTO in the BIOS is changing power delivery/frequencies/settings when the IF is set to 2000? LinpackXtreme results in the same whining noise. CoreCycler is the only CPU testing app I have that doesn't, but that'll be down to it only running on 1 core at a time, as it also doesn't play any mouse jerkiness.


----------



## Audioboxer

Sorry for more spam, but here is something else I'm finding hard to get to grips with...










7 minutes in, 17 WHEA and sometimes around 30 seconds between each WHEA. This is with VSOC on AUTO, VDDP down as low as 0.85v and CCD at 0.95. IOD at 1.05v.

Reducing voltage is seeming to have an impact on lessening WHEA. I mean, I've had boots into Windows with WHEAs dumping just about every second or every few seconds. With a VSOC that low I'd be surprised if the memory can now hold out, but why is dropping voltage this "low" _reducing_ WHEA? 

It's hard to understand when Manni is pumping their voltage, for example, VSOC as high as 1.25v in pursuit of stability. I guess for some fun I'll try running Karhu or TM5 and see if the memory falls down...










17 minutes, 43 WHEA. For all intents and purposes that is LOW for me. I mean, from the other day










Higher VSOC, higher VDDP, higher CDD and higher IOD... probably like 3200+ WHEA in 1 hour.

*edit* - 100 WHEA in 30 mins, so potentially looking at around 200 in an hour










That's a lot better than 3000+. But is this just because of the power budget being reduced???

*edit2* - lol, I'm an idiot, it was Karhu that produced most of those WHEA in the first place. Once it's running it ramps them up. They're not dropping quite as fast as they did 2 days ago but the pace changes from like one every 20~30 seconds to one every 5~10 seconds. Leaving this post up though as we all have to learn  AMD literally making me lose my mind, take me back to just changing memory timings!!!

I was under the impression WHEA just dumped at a consistent rate, but this "revelation" for me explains why I have issues under extreme CPU loads, obviously the number of WHEA spitting out increases tenfold when y-cruncher or OCCT are running. Whereas desktop/IDLE use WHEA errors are greatly diminished. Karhu/TM5 obviously do not increase the WHEA output speed enough to cause mouse jerking or USB drop outs.


----------



## Audioboxer

And... for my final post for the night, a silver-lining after AMD basically destroyed my brain the last few days with WHEA/FCLK, due to all the digging in the BIOS I actually found MSI have a way to force a 5950x to run on 1 CCD only. I've wanted to have this for ages to see what my memory overclocking would be like if it weren't for the higher latency down to 2 CCD. Got my answer!










Done in safe mode to minimise background crap. So in theory the latency "penalty" for 2 CCD is indeed around 3.5ns. Though I'm not entirely sure if a 5950x with 1 CCD disabled is really comparable to an actual single CCD processor lol.


----------



## Mach3.2

Mailman just delivered the Teamgroup 2*16GB 3200MHz CL14 kit, installed the kit and immidiately went for 3733MHz flat 15 1T no setup timings. Guess what, immediate BSOD when I try to start tm5. 🤣

Seem like dual rank B-die sticks are the real challenge. Back onto my Crucial kit until I had time to play with the CAD_BUS with this dual rank B-die kit.









They look pretty sick in white too.


----------



## KedarWolf

Mach3.2 said:


> Mailman just delivered the Teamgroup 2*16GB 3200MHz CL14 kit, installed the kit and immidiately went for 3733MHz flat 15 1T no setup timings. Guess what, immediate BSOD when I try to start tm5. 🤣
> 
> Seem like dual rank B-die sticks are the real challenge. Back onto my Crucial kit until I had time to play with the CAD_BUS with this dual rank B-die kit.
> 
> View attachment 2530691
> 
> They look pretty sick in white too.


Here is my 2x16GB b-die CL16 3600 which is pretty much the same bin as CL14 3200. Mine is G.Skill though.


----------



## Mach3.2

KedarWolf said:


> Here is my 2x16GB b-die CL16 3600 which is pretty much the same bin as CL14 3200. Mine is G.Skill though.
> 
> 
> View attachment 2530692


I'll probably have to start from 2T first and establish a baseline, no more shortcuts by jumping straight to 1T.


----------



## Audioboxer

Mach3.2 said:


> Mailman just delivered the Teamgroup 2*16GB 3200MHz CL14 kit, installed the kit and immidiately went for 3733MHz flat 15 1T no setup timings. Guess what, immediate BSOD when I try to start tm5. 🤣
> 
> Seem like dual rank B-die sticks are the real challenge. Back onto my Crucial kit until I had time to play with the CAD_BUS with this dual rank B-die kit.
> 
> View attachment 2530691
> 
> They look pretty sick in white too.


No setup times is probably what "killed you" that quickly. While I can boot into Windows without setup times at 1T, TM5 starts singing within seconds.

DR kits that can do 1T without setup times at higher frequencies are like four leaf clovers.

That being said myself and more of the wider community have probably made far too much of a deal about "1T Pure". That result I posted above of 50.4ns is with 1T/56. I honestly think if there even is a performance penalty for using Setup times, it's within MOE. Meaning, it just does not matter, the benefits of DR, if you can get the timings to the same as SR sticks, outweighs anything that comes from having to use Setup times for 1T. The real struggle isn't the Setup timings, it's that DR sticks can often have a tougher time reaching as low timings as SR, unless you pay up for specific DR binning.

From my own experience the only other thing I can point to, is tPHYRDL, for me, has had some issues training at 26/26 when Setup timing is used. But this MSI board has led me on a stupid journey with tPHYRDL anyway, behaviour I cannot explain irrespective of 1T/56  As long as I keep my tCL uneven with Setup timing, training at 26/26 is a walk in the park. Like, nothing I do can shift it from 26/26, even extremely low voltages


----------



## Blameless

Regarding chipset voltages, I believe B550 and the 400 series are 1.05v default, but the X570 is a salvaged IOD and should be 1.0v stock. Some boards seem to mislabel the setting as "chipset 1.05v voltage", even on X570, and even if they actually use 1.0v by default.


----------



## Mach3.2

Audioboxer said:


> No setup times is probably what "killed you" that quickly. While I can boot into Windows without setup times at 1T, TM5 starts singing within seconds.
> 
> DR kits that can do 1T without setup times at higher frequencies are like four leaf clovers.
> 
> That being said myself and more of the wider community have probably made far too much of a deal about "1T Pure". That result I posted above of 50.4ns is with 1T/56. I honestly think if there even is a performance penalty for using Setup times, it's within MOE. Meaning, it just does not matter, the benefits of DR, if you can get the timings to the same as SR sticks, outweighs anything that comes from having to use Setup times for 1T. The real struggle isn't the Setup timings, it's that DR sticks can often have a tougher time reaching as low timings as SR, unless you pay up for specific DR binning.
> 
> From my own experience the only other thing I can point to, is tPHYRDL, for me, has had some issues training at 26/26 when Setup timing is used. But this MSI board has led me on a stupid journey with tPHYRDL anyway, behaviour I cannot explain irrespective of 1T/56  As long as I keep my tCL uneven with Setup timing, training at 26/26 is a walk in the park. Like, nothing I do can shift it from 26/26, even extremely low voltages


Yeah it's probably setup timings that I'm lacking.

Funny, now I can't seem to post flat 15 1T 56-0-0 anymore after posting that setting twice. I also noticed tPHYRDL mismatch at 28-26, but can't post that setting anymore to try different voltages.

Currently running TM5 at 16-16-16-32 2T to get a baseline profile.










Once I'm done with the flat 16 2T profile I'll probably try to boot flat 15 2T before trying flat 15 1T 56-0-0 again. I suppose I'm gonna need more than 1.5V for flat 15? As it stands it's not posting flat 15 1T 56-0-0 with 1.5V vDIMM.


My previous single rank viper steel kit didn't need more than 1.5v to run flat 15 1T though, so I'm kinda scratching my head here.


----------



## Audioboxer

Mach3.2 said:


> Yeah it's probably setup timings that I'm lacking.
> 
> Funny, now I can't seem to post flat 15 1T 56-0-0 anymore after posting that setting twice. I also noticed tPHYRDL mismatch at 28-26, but can't post that setting anymore to try different voltages.
> 
> Currently running TM5 at 16-16-16-32 2T to get a baseline profile.
> 
> View attachment 2530720
> 
> 
> Once I'm done with the flat 16 2T profile I'll probably try to boot flat 15 2T before trying flat 15 1T 56-0-0 again. I suppose I'm gonna need more than 1.5V for flat 15? As it stands it's not posting flat 15 1T 56-0-0 with 1.5V vDIMM.
> 
> 
> My previous single rank viper steel kit didn't need more than 1.5v to run flat 15 1T though, so I'm kinda scratching my head here.


_Around_ 1.45v should be enough to get flat 15 at 3800, so I'd say 1.5v to do flat 16 at 3733 seems a little high.

Keep your tRFC a bit higher for now, the lowest I managed to go at 1.44v was 272. If you're trying to do 132ns at 1.45v I'd say that is probably causing issues


> Samsung B-Die tRFC(approximately):
> 1.20V-211ns
> 1.30V-178ns
> 1.35V-160ns
> 1.40V-150ns
> 1.45V-140ns
> 1.50V-136ns
> 1.55V-120ns
> 1.60V-110ns
Click to expand...

Rtts are probably best put around the "DR _standard_" for now, 6/3/3 or 7/3/3. I'd leave doing your own thing there for later.

ProcODT _might_ be happier at 34.3, but it shouldn't make much difference running at 36.9.

tWRRD should be 3. I know AUTO sets it to 1, but Veii and others advised 3 for DR.

ClkDrvStr shouldn't need as high as 60, especially not at 2T. Lower to 40 for now.

My 3200C14 set struggled a bit with 3800 flat 15, but it was a 2016 set and that was back on my ASUS mobo and when I was a total noob with memory OCing. Bins produced now should, more often than not, be better than bins produced as long ago as like 2016.

Still, if you're struggling aim for tCL15 with something like 15-16-16-16 just to see if it passes OK. At 3733 I'd really be hoping your tRCDRD doesn't crap out at 16.


----------



## Mach3.2

Audioboxer said:


> _Around_ 1.45v should be enough to get flat 15 at 3800, so I'd say 1.5v to do flat 16 at 3733 seems a little high.
> 
> Keep your tRFC a bit higher for now, the lowest I managed to go at 1.44v was 272. If you're trying to do 132ns at 1.45v I'd say that is probably causing issues
> 
> Rtts are probably best put around the "DR _standard_" for now, 6/3/3 or 7/3/3. I'd leave doing your own thing there for later.
> 
> ProcODT _might_ be happier at 34.3, but it shouldn't make much difference running at 36.9.
> 
> tWRRD should be 3. I know AUTO sets it to 1, but Veii and others advised 3 for DR.
> 
> ClkDrvStr shouldn't need as high as 60, especially not at 2T. Lower to 40 for now.
> 
> My 3200C14 set struggled a bit with 3800 flat 15, but it was a 2016 set and that was back on my ASUS mobo and when I was a total noob with memory OCing. Bins produced now should, more often than not, be better than bins produced as long ago as like 2016.
> 
> Still, if you're struggling aim for tCL15 with something like 15-16-16-16 just to see if it passes OK. At 3733 I'd really be hoping your tRCDRD doesn't crap out at 16.


I was referring to this since I can't recall anything about DR off hand. But I'll give your suggestions a go once the current run ends with no error.


But yeah, if I can verify that tRCDRD indeed craps out at 16 I'm sending it back to Amazon. 🤣


----------



## Audioboxer

Mach3.2 said:


> I was referring to this since I can't recall anything about DR off hand. But I'll give your suggestions a go once the current run ends with no error.
> 
> 
> But yeah, if I can verify that tRCDRD indeed craps out at 16 I'm sending it back to Amazon. 🤣


I think that is with Veii pushing pretty high memory frequencies, so with VDIMM going up RttNom can often be increased. He seems to be responding to someone running SR at 4000, SR often prefers different Rtt values than DR.

tRCDRD crapping out at 16 at 3733 would be a bit of a bummer. I myself would be hoping for 15.


----------



## hazium233

It is setting WRRD 1t because CL-CWL = 2

Or if you rather 3 + CWL - CL = 1


----------



## Mach3.2

These sticks might be a dud, it's pretty tough to even get it to POST with XMP timings @ 3200MHz flat 14 2T.

Using the previous flat 16 2T profile which passed 25 cycles of [email protected] profile, just changing tCL to 15 and loosening tRFC to 160ns resulted in no POST. I even tried 1.55V vDIMM but still no joy.

I'll see if i can get this kit swapped for another set.


----------



## Audioboxer

Mach3.2 said:


> These sticks might be a dud, it's pretty tough to even get it to POST with XMP timings @ 3200MHz flat 14 2T.
> 
> Using the previous flat 16 2T profile which passed 25 cycles of [email protected] profile, just changing tCL to 15 and loosening tRFC to 160ns resulted in no POST. I even tried 1.55V vDIMM but still no joy.
> 
> I'll see if i can get this kit swapped for another set.


Is there a manufacturing date on them? I'm really surprised that just putting tCL to 15 resulted in no post. One thing you could try just to see is go with 1 stick only, then rotate, and see if it's one stick that's a dud. Not that that helps you much, but just be interesting to see if you're been really unlucky with 1 stick or it might be a bin to be wary of.

In other news I thought "maybe if I disabled 1 CCD it will help me run 1T pure with DR?" lol, no. Just trying it fun


----------



## mongoled

Audioboxer said:


> Is there a manufacturing date on them? I'm really surprised that just putting tCL to 15 resulted in no post. One thing you could try just to see is go with 1 stick only, then rotate, and see if it's one stick that's a dud. Not that that helps you much, but just be interesting to see if you're been really unlucky with 1 stick or it might be a bin to be wary of.
> 
> In other news I thought "maybe if I disabled 1 CCD it will help me run 1T pure with DR?" lol, no. Just trying it fun


Its all part of the fun and games

 

Look here 🤣









But it cant do the HNT test reliably.

 

Also tCL15 is triggering a 28/26 mismatch, note the Membench time its 92 seconds.

In a few minutes i will hopefully be posting a completed TM5 using 2T, the Membench time is 96 seconds.

Latency is 50 ns



1T even with setup timings is stressing the CPU mem controller because of the high FCLK when compared to 2T (note the slower Membench times referenced above) thats why 2T passes those tests (this is yet to be fully establised a did some quick runs before TM5.....)

Thats how i see it anyway



25 cycles no errors, its very nearly completed



** EDIT **
25 cycles finished, no errors


----------



## smackerrr

I made a seperate thread(3600 16 19 19 39 CJR on a 3900x need help) but this seems like the more correct thread to fix what I'm looking for. I've been changing settings and have the zentimings for each attempt and result, maybe someone can see something I'm not.
I decided to go full 1t with no GDM after more reading, and these are my results since.


















Second pic posted and logged into OS but auto restart after 15-20 seconds just opening some apps.








Third pic, restart after 6 sec of OCCT memory bench.









First pic is stable and as tight as I got with GDM Enabled(I did not go nearly as tight as I could but just for referance) This was around 1.4-1.408 V

Then i decided no more playing with GDM, and second and third pictures are attemps to get stable without GDM by loosening timings and upping V to 1.42 in BIOS (Ended up 1.424-1.432 in HWInfo).
Last pic is back to basically all auto settings that I tightened previously but I upped ProcODT to 53 and now it's stable. I will link to my other thread so you can see my 3733 timings too.
I'm hoping someone will see something I'm not seeing as far as a connection amongst the timings, and what I could try to tighten now without GDM and @ what voltage. Appreciate all the help


----------



## Audioboxer

mongoled said:


> Its all part of the fun and games
> 
> 
> 
> Look here 🤣
> 
> View attachment 2530748
> 
> 
> But it cant do the HNT test reliably.
> 
> 
> 
> Also tCL15 is triggering a 28/26 mismatch, note the Membench time its 92 seconds.
> 
> In a few minutes i will hopefully be posting a completed TM5 using 2T, the Membench time is 96 seconds.
> 
> Latency is 50 ns
> 
> 
> 
> 1T even with setup timings is stressing the CPU mem controller because of the high FCLK when compared to 2T (note the slower Membench times referenced above) thats why 2T passes those tests (this is yet to be fully establised a did some quick runs before TM5.....)
> 
> Thats how i see it anyway
> 
> 
> 
> 25 cycles no errors, its very nearly completed
> 
> 
> 
> ** EDIT **
> 25 cycles finished, no errors
> 
> 
> 
> View attachment 2530751


Niiiiice, and yeah I think 2T almost becomes mandatory over 4000. If you can get it stable though the performance uplift from 4000+ negates any small performance bump from running 1T over 2T. At least at 4000 I wasn't even bothering to try and run my DR at 1T lol. 4000 2T simply gives better results than 3800 1T.

While I can't seem to get IF 2000+ stable to any degree I'd be happy running, I think I will have some fun with memory and see what results I can get. Seeing as TM5 and Karhu will pass, I'd be fairly confident in my memory results. 

Though this will just end up getting me jealous of results when I go back to 3800/1900 🤣


----------



## PJVol

mongoled said:


> But it cant do the HNT test reliably.


Did you notice performance regression in linpack extreme 8gb tests?
I have similar scores, around 265-267 with a 2033 fclk, but still far from 275 obtained at 1900 and 3800CL15 ram.


----------



## hazium233

smackerrr said:


> Spoiler
> 
> 
> 
> 
> View attachment 2530763
> 
> 
> 
> 
> I'm hoping someone will see something I'm not seeing as far as a connection amongst the timings, and what I could try to tighten now without GDM and @ what voltage. Appreciate all the help


CJR is probably ok to 1.45V. I don't know if I would run it higher. DJR has XMPs to 1.55 or so and probably is more tolerant.

You want to get tRC lower, since it is a critical performance timing. Try ~ tRC = tRP + tRAS. If that is unstable you might need to increase tRAS or tRP.

Check ~250ns on tRFC. ~456t. If you want to be more conservative or temp resistant run higher.

Try to see if the SCLs will do 4t.

Try if WR will go down.

Test tRDWR 8, 9, 10 while tCL=tCWL. Similarly, try tWRRD 5t, 4t, 3t

tRDRDSD might do 4, tWRWRSD may go down a few ticks from where you have it.

If you have to turn on GDM to tighten especially tRC, it might be worth doing.

edit: I got lost in the pictures.

tRRDS will usually be able to do 4t with nearly any decent stuff and as such tFAW can do 16. If you just can't do it, try 5 and 20 or 6 and 24 for them respectively.

tRRDL can just be 8t, or 6 or 4. It is ultimately limited by tRC.


----------



## smackerrr

Just a update real quick, right after posting I tried 16 18 18 18 36 and 16 19 18 18 36 and had voltage up to 1.42 1.43 I tried upping ODT to 56 then 60, and ended up getting all kinda errors on mem test "your computer has problems copying x to y, cannot accurately store data".

So I've had to go back to 16 19 19 39 85 630 geardown enabled. I'm up to about 10% so far no errors yet fingers crossed. I thought i had messed em up for a second there felt weird.

Thanks for the reply above, I'll be getting into it ASAP

Edit: This is what I finally got it stable at no errors. 1.352 V
I just wish i could get it to at least this with GDM off so I can start from somewhere


----------



## MrHoof

I would suggest when going for GDM off dont go directly to 1T, get a stable 2T setup first and then make that work at 1T.


----------



## Mach3.2

Audioboxer said:


> Is there a manufacturing date on them? I'm really surprised that just putting tCL to 15 resulted in no post. One thing you could try just to see is go with 1 stick only, then rotate, and see if it's one stick that's a dud. Not that that helps you much, but just be interesting to see if you're been really unlucky with 1 stick or it might be a bin to be wary of.
> 
> In other news I thought "maybe if I disabled 1 CCD it will help me run 1T pure with DR?" lol, no. Just trying it fun


Can't find anything on the packaging, but thaipooh burner says manufactured in June this year.

I went ahead and requested a replacement set from Amazon, let's see how that one fares. If I get the same problem it's probably better to avoid that bin for me... 😂


----------



## MrHoof

Mach3.2 said:


> Can't find anything on the packaging, but thaipooh burner says manufactured in June this year.
> 
> I went ahead and requested a replacement set from Amazon, let's see how that one fares. If I get the same problem it's probably better to avoid that bin for me... 😂


The gskill 3600 14-15 or the 4000 16-16 if u are not lucky with the next kit similiar price range. I had decent luck with the 3600-14-15 but the 4000-14-15 is the kit ur looking for if u want the best.


----------



## Mach3.2

MrHoof said:


> The gskill 3600 14-15 or the 4000 16-16 if u are not lucky with the next kit similiar price range. I had decent luck with the 3600-14-15 but the 4000-14-15 is the kit ur looking for if u want the best.


I actually got my current kit for 210usd shipped, I'm not sure I can find the gskill 3600 14-15-15 bin without a significant increase in cost on my end.

But of course the age old saying of you pay for what you get might be in action here. It could simply be the fact that memory chips are so well binned nowadays that the best chips go into their best bin and the trash ends up in the lottery bin. 😔😂


----------



## MrHoof

Ye and i think team group bins are are closer to the the limit then gskills ones thats why the can sell at those price at times. I saw a few reports already with those kits not overclocking well. I was looking my self at the 3600 14-15 kit from teamgroup at 254€ when it was new released back when i bought my CPU (a year ago) and was wondering already how this can be 50-100€ cheaper then the same kit from gskill back then.


----------



## mongoled

PJVol said:


> Did you notice performance regression in linpack extreme 8gb tests?
> I have similar scores, around 265-267 with a 2033 fclk, but still far from 275 obtained at 1900 and 3800CL15 ram.


I've never ever seen close to 275 obtained even when running tCL @13 3800/1900, even from people running 5950x.

My highest ever LinpackXtreme at 3800/1900 when running the 3rd option is 271 Gflops using tCL @13

And that did not happen reliably across reboots, some reboots it would be 268/9 others 270/271.

I can't say I see any performance regression, TM5 completed time is within expected parameter as per memory already in use when test was run.

Though this is not yet capable of passing several hours of Y-Cruncher and looks like it locked up the PC last night while running Realbench.

Hopefully I can find what needs changing to get it stable.

Unfortunately increasing CsOdtDrvStr did not resolve my cold/warm boot issues....

Though looking at some of the "stability" results that have been accepted in the Zen RAM OC leaderboards, its fair to say I'm stable (to add my entry) even though I know it isn't......

** EDIT **
Just want to add, "performance regression" is such a broad term.

I see "performance regression" in AIDA64 L3 results, 580 GB/s instead of 620+ GB/s when compared to 3800/1900.

I see "performance increase" in DRAM Membench.

The "performance regression" is simply down to CPU power budget, not some instability ..


----------



## umea

smackerrr said:


> I just wish i could get it to at least this with GDM off so I can start from somewhere


Get 2T GDM off stable as a baseline and then move to trying to get 1T stable.


----------



## mongoled

Audioboxer said:


> Niiiiice, and yeah I think 2T almost becomes mandatory over 4000. If you can get it stable though the performance uplift from 4000+ negates any small performance bump from running 1T over 2T. At least at 4000 I wasn't even bothering to try and run my DR at 1T lol. 4000 2T simply gives better results than 3800 1T.
> 
> While I can't seem to get IF 2000+ stable to any degree I'd be happy running, I think I will have some fun with memory and see what results I can get. Seeing as TM5 and Karhu will pass, I'd be fairly confident in my memory results.
> 
> Though this will just end up getting me jealous of results when I go back to 3800/1900 🤣


1T being more performant than 2T goes without saying, irrespective if 2T gives "better" latency because of tPHYRDL mismatch.

And if your 2000 FCLK is not eating into your CPU budget because you are using a relatively low vSOC it will be more performant than 1900 ...

Just an image to show that Y-Cruncher needs more than a couple of hours to be acceptable as being "stable"


----------



## Audioboxer

Fake 1CCD 5950x with 4000/2000... If only that damn IF was stable at 2000.


----------



## Hookz

Hello! Why latencys are that high? Something is wrong but I don't know what.
These settings are 10000% stable in the Karhu ram test.


----------



## Melan

smackerrr said:


> just wish i could get it to at least this with GDM off so I can start from somewhere


Start by stabilizing that vSOC voltage. You're not running anything GDM off while it keeps changing on each boot. Set the SOC load-line calibration to mode 2 or whatever it is on asus boards.


----------



## Audioboxer

Hookz said:


> Hello! Why latencys are that high? Something is wrong but I don't know what.
> These settings are 10000% stable in the Karhu ram test.
> 
> View attachment 2530810


Voltages aren't optimal, ProcODT is too high, GDM might be masking/autocorrecting instability leading to timings not actually running at what they display as and latency will also be impacted by your CPU settings. So, PBO, curve and so on.

Your clock multiplier seems a bit low in the AIDA screenshot. Do you use PBO or a curve?

I'd be aiming for GDM disabled first, but if you want to stay with it on, lower ProcODT to 36.9 at least, VSOC _might_ be too low for 3800 tCL14, VDDP to 0.9v, IOD to 1.05v and CDD can probably be around 0.975v~1.0v.

Check your latency in safe mode as well just in case your Windows installation is quite heavy. Your latency isn't terrible or anything, but yeah, I'd probably be hoping for a bit lower with most of those timings.


----------



## Hookz

Audioboxer said:


> Voltages aren't optimal, ProcODT is too high, GDM might be masking/autocorrecting instability leading to timings not actually running at what they display as and latency will also be impacted by your CPU settings. So, PBO, curve and so on.
> 
> Your clock multiplier seems a bit low in the AIDA screenshot. Do you use PBO or a curve?
> 
> I'd be aiming for GDM disabled first, but if you want to stay with it on, lower ProcODT to 36.9 at least, VSOC _might_ be too low for 3800 tCL14, VDDP to 0.9v, IOD to 1.05v and CDD can probably be around 0.975v~1.0v.
> 
> Check your latency in safe mode as well just in case your Windows installation is quite heavy. Your latency isn't terrible or anything, but yeah, I'd probably be hoping for a bit lower with most of those timings.


I have PBO off and all core OC 4400MHz.
I can't boot without GDM so i think it has to be on. Thanks I will try in safe mode those values.


----------



## Audioboxer

Hookz said:


> I have PBO off and all core OC 4400MHz.
> I can't boot without GDM so i think it has to be on. Thanks I will try in safe mode those values.


Yeah the all core OC will probably result in lower latency in AIDA then. Just the trade off for what I presume could be better multicore results. I find PBO to be really good with these 5xxx chips, but it does put more strain on your cooling setup and take a bit of time to balance/figure out.

Unless I'm talking nonsense I think single core is what gets pushed when AIDA is calculating latency.


----------



## Hookz

Audioboxer said:


> Yeah the all core OC will probably result in lower latency in AIDA then. Just the trade off for what I presume could be better multicore results. I find PBO to be really good with these 5xxx chips, but it does put more strain on your cooling setup and take a bit of time to balance/figure out.
> 
> Unless I'm talking nonsense I think single core is what gets pushed when AIDA is calculating latency.


Wow 2 ns off in safe mode


----------



## Luggage

Hookz said:


> Wow 2 ns off in safe mode
> View attachment 2530811


Probably some service running. Aqua computer add 3ns for me. Do you use any rgb or fan software? The L latency is high because of your low AC.


----------



## Hookz

Luggage said:


> Probably some service running. Aqua computer add 3ns for me. Do you use any rgb or fan software? The L latency is high because of your low AC.


I use MSI Mystic Light for the RGB but i turn it off when i run AIDA64. What is AC? 😅


----------



## Luggage

Hookz said:


> I use MSI Mystic Light for the RGB but i turn it off when i run AIDA64. What is AC? 😅


Msi dragon center and mystic light are horrible. With my carbon I only installed to set a color - the I reinstalled windows… even when you turn it off it has lots of **** services running:/
AC = All Core (manual OC). If your PBO run 4.8 single core you should see low 10s on L3 latency.


----------



## Audioboxer

Hookz said:


> Wow 2 ns off in safe mode
> View attachment 2530811


If you open task manager in safe mode you will see there are like 45 running processes or something.

Most people in Windows will have 150-190 processes. While you can slim down Windows installations and many in this topic do, a daily PC just isn't going to operate like a test bench could. If you've got 32GB of RAM it is OK to let apps and services run 🤣

Though I do like to get a bench from safe mode as it gives me an indication of where my memory latency is before anything is running. If I can I will also try to avoid bloated software. I've finally ditched LG Hub because its awful and I'm just using the Onboard Memory Manager.

Corsair iCUE is another dreadful piece of software, bloated to the extreme, but it's the price I pay having a commander pro to do my loop and all my fans.

Also, while the joke is RGB makes your PC faster, the reality is RGB makes it slower. I don't think there is one application made by any hardware company using RGB that isn't total bloated trash running like 80 services/processes to control some lights.


----------



## domdtxdissar

mongoled said:


> I've never ever seen close to 275 obtained even when running tCL @13 3800/1900, even from people running 5950x.
> 
> My highest ever LinpackXtreme at 3800/1900 when running the 3rd option is 271 Gflops using tCL @13
> 
> And that did not happen reliably across reboots, some reboots it would be 268/9 others 270/271.
> 
> I can't say I see any performance regression, TM5 completed time is within expected parameter as per memory already in use when test was run.


I'm on holiday now, but these are my old scores running my old slower settings:

Benchmark 8GB extended numbers with 6 cores

6 cores at PBO CO -30 = 283 Gflops
*6 cores maxed (static 4.85ghz) = 287 Gflops*












Spoiler: Benchmark 3GB numbers with 6 cores



6 cores at 4.5ghz static OC = 266 Gflops
6 cores at PBO CO -30 = 281 Gflops
*6 cores maxed (static 4.85ghz) = 286 Gflops*


Seems like you are experiencing throttling with your high fclk without knowing it (?)


----------



## mongoled

domdtxdissar said:


> I'm on holiday now, but these are my old scores running my old slower settings:
> 
> Benchmark 8GB extended numbers with 6 cores
> 
> 6 cores at PBO CO -30 = 283 Gflops
> *6 cores maxed (static 4.85ghz) = 287 Gflops*
> 
> View attachment 2530822
> 
> 
> Seems like you are experiencing throttling with your high fclk without knowing it (?)


We have been through this before, a "halved" 5900x is not equivalent to a 5600x when PBO is used. 

Its already been documented in this thread probably around 120 pages ago, why do others who have participated in that conversation do not remember the context of the discussion I do not know.....


----------



## domdtxdissar

mongoled said:


> We have been through this before, a "halved" 5900x is not equivalent to a 5600x when PBO is used.
> 
> Its already been documented in this thread probably around 120 pages ago, why do others who have participated in that conversation do not remember the context of the discussion I do not know.....


Sorry but yes it is..
5950x with only 6 cores @ static 4.5ghz should perform 100% same as 5600x @ 4.5ghz static with all other settings beeing the same. 

As long as you compare @ same static clock its a valid comparison, and yeah, we have been through this before indeed


----------



## mongoled

domdtxdissar said:


> Sorry but yes it is..
> 5950x with only 6 cores @ static 4.5ghz should perform 100% same as 5600x @ 4.5ghz static all other settings beeing the same.


Did you miss where I say *PBO* ????

From 31st May this year, *PBO*, 3800/1900










Fixed 4.5 Ghz, again from 31st May this year


----------



## domdtxdissar

mongoled said:


> Did you miss where I say *PBO* ????
> 
> From 31st May this year, *PBO*, 3800/1900
> 
> View attachment 2530824
> 
> 
> Fixed 4.5 Ghz, again from 31st May this year
> 
> View attachment 2530825


Please stop moving the goal posts, where did you say PBO in your orginal post ? 
And its great you have non throtteling static 4.5ghz numbers @ 1900fclk from 31 may, now just show us scaling above 1900 all the way up to 2066 and this is a done deal..

If you can do this i will be the first to admit your single ccd 5600x can run above 1900flck without reduced scaling/throttling 

The problem is that i have been asking for many months for these exact numbers, but people never seem to be able to produce them, hence i asked: "are you sure your not experiencing throttling with your high fclk without knowing it (?)"

There is no need to get your pantis in a twist over this


----------



## rom.clown

does these value have to be equal ?


----------



## mongoled

domdtxdissar said:


> Please stop moving the goal posts, where did you say PBO in your orginal post ?
> And its great you have non throtteling static 4.5ghz numbers @ 1900fclk from 31 may, now just show us scaling above 1900 all the way up to 2066 and this is a done deal..
> 
> If you can do this i will be the first to admit your system can run above 1900flck without reduced scaling/throttling


You quoted my post 14268 where I explicitly tell you I'm talking about PBO. 

No moving of any goal posts!

Im not going to repeat the findings which you also participated in those several months ago. 

Will find you the start of discussions, I'm not going to go over old ground when this information has been previously discussed over several pages.

Those who can read carefully can see that I never said there was no throttling.......


----------



## domdtxdissar

mongoled said:


> Those who can read carefully can see that I never said there was no throttling.......


So just to nail it down then.

You are seeing not seeing the same scaling above 1900 as you are seeing below 1900 when running static clocks, correct ?

If so, this means you have throtting above 1900 fclk, period.

There are no way around this..

_edit_

This is how the scaling *can* look like above 1900 fclk: (and the numbers i have been asking other people running above 1900 for)












Spoiler: For those who dont know what we are talking about






RonLazer said:


> Sorry for the delay, had some real work to do, but I finished my testing, I'll explain my methodology a bit first though.
> 
> *OS:* Windows 20H2 x64. It's my Bench OS so it's quite lightweight. I used @ManniX-ITA High-Performance Power plan.
> *CPU:* 5600X [email protected] SET (LLC 1, droops to 1.2V) - SMT enabled.
> *BIOS:* Spread Spectrum: disabled, Global C-States: enabled, PLL/1P8 Voltage locked to 2V, DFE/FFE training enabled.
> *Memory:* See Zentimings in screenshot, had to adjust the DRAM and SOC voltages as I increased frequency.
> *Benchmark:* Linpack Extreme 1.1.5, with the standard 3Gb test run 5 times.
> View attachment 2512597
> 
> *Why Linpack?*
> It's as close to a "real-world" memory test as any benchmark gets, it will hammer the memory controller AND the CPU so the CCD portion of the infinity-fabric gets hot, uses fairly representative memory in it's "Standard" benchmark (3Gb of heavy IO is about typical for most games/computational-software) and is multi-threaded. The problem with Aida64 bandwidth and latency tests is they put absolutely zero strain on the memory controller, Geekbench is too short and too synthetic, and y-cruncher is a fair substitute but is far heavier than any real-world use-case and so only really useful for scoring HWBot points or really proving a point about stability.
> 
> *Why a static Overclock?*
> It stops thermal variation affecting PBO, and allows comparison across different silicon-quality CPUs. Linpack is a very heavy memory benchmark, but still mostly scales with CPU and so without locking the CPU core ratio we'd just be comparing who has the best-binned 5600X. It also isolates the impact of higher SOC power pulling from the PBO power/current budget.
> 
> *Why GearDownMode?*
> This means we're not fiddling with CAD setups etc. to stabilize our respective overclocks - which will impact performance. Feel free to adjust drive-strengths/ProcODT/RTTs to match your boards/dimms impedances, they won't dramatically affect the results. I can't even run CR 1T at 3800 with my 4x8gb kit, and Linpack doesn't particularly care about latency in isolation anyway.
> 
> *What about the SOC-derived voltages?*
> Feel free to tune SOC/CCD/IOD/VDDP/PLL to match your CPU, I just didn't want to get bogged down in fine-tuning these to squeeze out the last few % when the goal is to show and compare qualitative trends. I just used ballpark values I know have worked in the past. The timings are not very tight at all, because I didn't want this to be a comparison of memory controllers, but instead of the infinity fabric link itself.
> 
> As both the memory/CPU overclock are quite mild, in theory anyone can try and replicate this, including those with 5900X or 5950X's by disabling the 2nd CCD and limiting the number of active cores in the BIOS.
> 
> Here is the full graph from 1800MHz to 2033MHz:
> View attachment 2512596
> 
> The drop-off is obviously distorting the scale so let's remove 2033MHz:
> View attachment 2512598
> 
> Not quite sure what happened at 1933MHz, it even failed to POST a few times so I think I have a weak "FCLK hole" at that frequency on my CPU. The overall trend seems to basically show what I claimed initially - that FCLK equalization mechanism stops functioning properly after 1900MHz. The actual memory performance under load is barely increasing beyond 1900MHz, despite the fact that the timings are constant so we should see a rise in throughput solely on the memory side, the infinity fabric link is clearly bottlenecking the memory performance. As far as I've been able to tell, speeds over 1900MHz are basically just for show, or very very light workloads. I've observed this same behavior in multiple benchmarks before, this is the first time I've properly collected the data on it.
> 
> Here is my screenshot for the 2033MHz run:
> View attachment 2512599
> 
> You can literally see the performance dropping off as the CPU gets further into the benchmark, and the data-fabric and IOD get hotter, and hence less stable. This is why brief "bursty" benchmarks like Aida64 are insufficient, they don't actually push the CPU at all so instability doesn't kick in hard enough to manifest as performance degradation.
> 
> I'd like to see some people try and replicate these tests (should be pretty easy for anyone with 4 sticks of B-die) and a Zen3 CPU. This will allow us to compare and see if the performance stagnation kicks in at 1933MHz for everyone, and if the sharp drop-off at 2033MHz is also a universal feature. A few tips to improve reproducibility:
> 
> 1. Start with a single 2gb run first to "wake up the CPU". If you don't then the first loop will be slower than the others. I assume this is due to scheduler behaviour, could also be core parking.
> 2. Close all background processes, ideally run in Windows 10 Diagnostic Mode.
> 3. If a run is anomalously low, reboot and try again. Memory training is super variable and boot-to-boot variation can sometimes be larger than changes in timings/frequency/voltages.
> 
> *Working Conclusion?*
> I'd like to see more results, but I strongly suspect the optimal fclk frequency for pragmatic daily usage really is 1900Mhz and no amount of fiddling is going to fix this. If there was a magic setting in the CBS that fixed all the issues and unlocked the full potential of higher clocked memory with no risks or downsides - why haven't AMD just turned it on for us?
> 
> Also if there was, someone would have found it by now. I've tried almost all of them, some of them help a little, nothing actually changes this overall trend. You can definitely hack together a BIOS config that will spit out excitingly low latency numbers, but as soon as your CPU gets hot it will probably crumple, and even if it doesn't - are the gains really worth the extra strain you're putting on your CPU with the higher SOC voltages? Probably not.


----------



## mongoled

domdtxdissar said:


> So just to nail it down then.
> 
> You are seeing not seeing the same scaling above 1900 as you are seeing below 1900 when running static clocks, correct ?
> 
> If so, this means you have throtting above 1900 fclk, period.
> 
> There are no way around this..


As answered to @PJVol

Throttling is not happening for all types of workloads.

So as you are wanting an answer please make your question specific to the type of workload. 

As you don't remember the details of the previous conversation

Ughhhh most of my response got lost in the saving of post...


----------



## PJVol

Does anyone have an idea, what can be done to lower Vdimm?
Or I am stuck on some hardware limitation?









*@Veii*
Buddy-yyyyy!
When lowering Vdimm to 1.58, 1.57 and further it starts spamming with #7's, 3-4 per cycle, ocassionally coupled with #14's. Have any idea, what it might mean?

-----------------------------------------------

PS: Some observations

lowering procODT, VDDP (0.950 and less did, 1.000 - 1.050 is fine, 0.9 - no boot) caused PHYRDL mismatch.
Vsoc 1.3 and less - error #11
the PHYRDL mismatch itself results in increased mem latency by 0.4-0.5ns.


----------



## nick name

Is the floor for tFAW still 16?


----------



## Audioboxer

PJVol said:


> Does anyone have an idea, what can be done to lower Vdimm?
> Or I am stuck on some hardware limitation?
> View attachment 2530833
> 
> 
> *@Veii*
> Buddy-yyyyy!
> When lowering Vdimm to 1.58, 1.57 and further it starts spamming with #7's, 3-4 per cycle, ocassionally coupled with #14's. Have any idea, what it might mean?


I think I'd be confident enough to say 1.6v on VDIMM for 4400 is pretty decent for tCL17. To run nearer 1.5v will likely require tCL18 and close to 1.4~1.45v for tCL19.

For me to go from tCL14 at 3800 to tCL13 at 3800 required a jump from 1.44v to 1.55v. tCL is voltage hungry if you want to shift it down. Often not for massive performance gains, so if its temps you're worried about just try going with tCL18 and see what VDIMM can come down to.


----------



## PJVol

Audioboxer said:


> I think I'd be confident enough to say 1.6v on VDIMM for 4400 is pretty decent for tCL17


You may be right, and I am going around in circles.
And no, its not temps that worrying me most, but rather I can't feel the mb capabilities ceiling, i.e. how it looks like and what are the symptoms of when you hit the max. MCLK that a certain mb design actually allows.


----------



## glnn_23

PJVol I think some of those voltages are a bit high.
Running 4400c16 here with my old 5700g . Using an Impact mb might be a reason.



https://www.overclock.net/attachments/screenshot-201-png.2520337/


----------



## sonixmon

Hookz said:


> Hello! Why latencys are that high? Something is wrong but I don't know what.
> These settings are 10000% stable in the Karhu ram test.
> View attachment 2530810


Try AddrCmdSetup 56 with GDM off, this worked for me. It seems to correct posting issues and slightly better latency and throughput than GDM or 2T.


----------



## Veii

PJVol said:


> *@Veii*
> Buddy-yyyyy!
> When lowering Vdimm to 1.58, 1.57 and further it starts spamming with #7's, 3-4 per cycle, ocassionally coupled with #14's. Have any idea, what it might mean?


Both say "badly timed powerdown or bad powering"
In such case likely "unclean" powering

What about just increasing tRRD_ and that way dropping primaries & voltage ?
Probably also lowering cLDO_VDDP or procODT slightly , as both result in a too noisy signal ?


----------



## mongoled

@domdtxdissar
Sorry please bear with me as this 4066/2033 profile has not been behaving at all well when posting.

Just when I found out how to "fix" the VST test by increasing PLL 1.8v, the PC refuses to post until I set vDDP to AUTO which defaulted to 0.9v and ive managed to post.

The below image is using *PBO*, if I get round to fixing the posting issue with 4066/2033 I will do some static 4.5ghz runs.

I get the same GFlops with my 3800/1900 profile that is tCL 13 using the exact same PBO/CO settings.

The only think I can say with sureness is that getting the 4066/2033 profile to post reliably and give consistent GFlops is hit and miss.

Something with the training im guessing...


----------



## Hookz

sonixmon said:


> Try AddrCmdSetup 56 with GDM off, this worked for me. It seems to correct posting issues and slightly better latency and throughput than GDM or 2T.
> 
> View attachment 2530875


I tried but the PC didn't start. I tried other settings too but I can't get the PC to boot without GDM. Maybe i have to lower other timings but naah takes too much time to start over again


----------



## nick name

sonixmon said:


> Try AddrCmdSetup 56 with GDM off, this worked for me. It seems to correct posting issues and slightly better latency and throughput than GDM or 2T.
> 
> View attachment 2530875





sonixmon said:


> Try AddrCmdSetup 56 with GDM off, this worked for me. It seems to correct posting issues and slightly better latency and throughput than GDM or 2T.
> 
> View attachment 2530875


Holy cow. While it didn't work for the other person it seems to be working for me. Previously I would get an instant BSOD when starting Karhu at 1T and GDM off, but now it seems very promising. 

How did you learn about using AddrCmdSetup set to 56? And why does this seem to work? 









Edit:

Very, very promising.


----------



## Mach3.2

My layman understanding is AddrCmdSetup 56 adds delay(where exactly, I have no idea) which helps with stability because your RAM no longer have to hit the tight timings it has to hit at 1T GDM off.


----------



## smackerrr

Anyone know which Samsung die this is?


----------



## domdtxdissar

mongoled said:


> @domdtxdissar
> Sorry please bear with me as this 4066/2033 profile has not been behaving at all well when posting.
> 
> Just when I found out how to "fix" the VST test by increasing PLL 1.8v, the PC refuses to post until I set vDDP to AUTO which defaulted to 0.9v and ive managed to post.
> 
> The below image is using *PBO*, if I get round to fixing the posting issue with 4066/2033 I will do some static 4.5ghz runs.
> 
> I get the same GFlops with my 3800/1900 profile that is tCL 13 using the exact same PBO/CO settings.
> 
> The only think I can say with sureness is that getting the 4066/2033 profile to post reliably and give consistent GFlops is hit and miss.
> 
> Something with the training im guessing...
> 
> View attachment 2530899


Very good mongoled 
If we ignore the fact that a static OC is required for this comparison, as tempature and powersettings can affect the PBO clockspeed greatly in this benchmark, this is a good start aleast 

So right now we have your CL16 1900fclk and PBO run from May this year = 267 gflops
CL13 1900fclk PBO = 272 gflops (i think, if i understood you correctly)
Your run from above with CL14 2033fclk and PBO = 272 gflops

This is a alittle apples to oranges comparison 

For this to be done correctly we need multible runs, at same static cpu mhz, at same memory settings and at different infinity fabric clockspeeds to compare the scaling, as this should be the only thing changing between runs.. 

After all, we are only trying to determine if there is reduced scaling/no performance increase from going above 1900 fclk in Linpack. 

Testing at these diffrenct infinity fabric clockspeeds would be most helpfull: 1800 -> 1866 -> 1900 -> 1933 -> 1966 -> 2000 -> 2033 -> 2066

If i were to guess, i think the results will look something like the picture i posted in my last post, but i would be very happy to be shown otherwise


----------



## Mach3.2

smackerrr said:


> Anyone know which Samsung die this is?
> View attachment 2530938


If it takes 3600MHz 16-16-16-32 stable it's probably B die.


----------



## MrHoof

Mach3.2 said:


> If it takes 3600MHz 16-16-16-32 stable it's probably B die.


Would say its easier to just set trfc around 300 if it boots its b-die else d/c.


----------



## SneakySloth

smackerrr said:


> Anyone know which Samsung die this is?
> View attachment 2530938



I dont think that's B die. 3600 @ 18-19-19-39-58 is definitely not B-die.


----------



## stewwy

rom.clown said:


> does these value have to be equal ?


The answer is no, they don't. Why you often see it is that the best ram is Samsung b-die, and that can be looked for in the spec, if you see straight 14's at 3200 or straight 16's at 3600 the sticks are going to be b-die.


----------



## Veii

The problem with LinX testing on a 5600X, is the absurdly low procHot limit
It will frequency throttle beyond 65c, where higher FCLK and voltages increase this amount
Where i haven't been able to confirm, that procHOT is disabled in OC_Mode, hence FIT isn't ~ only little part of it

A 5800X optimally would be the target for such, as it adheres to the 95-105c limit

Probably it would be required to show such testing on 4.2 or 4.3ghz allcore near 1v, or 1.05v at worst
Soo there is no chance to even reach 60c on a 5600X

Another sadly part is, 
Even when for example my CPU is lapped, air coolers are incapable to scale well bellow 70-72c
The heatpipes are just not warming up in time, to be cooled down in time
Soo 5600X users, and gaming users have to stick to an AIO
Be it even a 120mm one 
Mainly as i haven't been able to sort this hardthrottle out, there is no data to share that can be interpreted as anyhow useful


----------



## PJVol

Veii said:


> What about just increasing tRRD_ and that way dropping primaries & voltage ?
> Probably also lowering cLDO_VDDP or procODT slightly , as both result in a too noisy signal ?


Did you mean increasing from 4/6 to, for example 5/7 ? Does it imply tFAW 20?
Lowering VDDP to 1.000 works but doesn't seem to allow further Vdimm reduction, as well as lowering VDDP leads to ocassional #5's or #7's. Actually, I think its ok to call it a day with that voltage.
That is where I am right now:


----------



## Veii

PJVol said:


> Did you mean increasing from 4/6 to, for example 5/7 ? Does it imply tFAW 20?
> Lowering VDDP to 1.000 works but doesn't seem to allow further Vdimm reduction, as well as lowering VDDP leads to ocassional #5's or #7's. Actually, I think its ok to call it a day with that voltage.
> That is where I am right now:


Pretty much
I sadly don't know if the PCB Type of them would be an issue beyond 4133/4167MT/s
But it's likely a PCB thing (tRRD_) ~ as an issue, on higher MCLK (i am running between tRRD_S 6 & 7, depends)
And "high voltage" is a noise issue then - it's not a "lack of VDIMM" issue or being "dangerous"

Also what is this ?









EDIT:
Higher procODT, will also increase the minimum acceptable voltage
You should clearly try RTT_NOM , even the weakest of them ~ if it doesn't fail. As the Ceiling limit will be needed, when RTT_WR is missing to calculate such
(You can't only count on trace length to be perfectly designed for different type's of DIMM PCB ~ on higher than marketed maximum MCLK range)
Generally your target is to get procODT down and lower at the same time cLDO_VDDP slightly
Soo that CAD_BUS doesn't need to use 60ohm as ClkDrvStr but only 40

EDIT 2:
High SOC takes over the ClkDrvStr work, and allows to run "potentially lower procODT"
But the sideeffect of high procODT is also that it only accepts "higher" voltage ~ soo the benefit diminishes
Lower all voltages and try to drop procODT. ProcODT should not be your dimm powering supporter *, and will only create too much noise limiting maximum FCLK
* sadly this expectation i think was pushed onto people near DRAM Calculator times. From several sites including HardwareLUXX & ComputerBase ~ soo also OC-UK
** the expectation that you have to run high procODT on higher capacity with more DIMM strain. procODT should *not* be your dimm powering fix, even when it's the easiest one


----------



## nick name

@Veii Can you tell me why running AddrCmdSetup at 56 allows me to run 3800MHz at 1T and GDM Off?


----------



## Audioboxer

nick name said:


> @Veii Can you tell me why running AddrCmdSetup at 56 allows me to run 3800MHz at 1T and GDM Off?







I can't watch this again at the moment but IIRC around 12 minutes in it talks about setup timings. Something about shifting the data eye.

It's a bit over my head but from what I gathered it's not really about delays and performance isn't necessarily going to be lower so no one should obsess over thinking 1T pure is needed for better benchmarks. Real world performance even less so. Like, if 55-56 is what you need on DR set it and forget it. Don't even think about it.

I'm benching at 50.4ns with 1CCD DR which is right down there with results from SR kits. So, no performance penalty with setup times I can see.

Only subsequent challenge I've come across is Setup timings and tPHYRDL, but my whole Setup is just whack with tPHYRDL. As long as I stay off even tCL it trains at 26/26 and that where I'm staying. tCL13 forever 🤣


----------



## nick name

Audioboxer said:


> I can't watch this again at the moment but IIRC around 12 minutes in it talks about setup timings. Something about shifting the data eye.
> 
> It's a bit over my head but from what I gathered it's not really about delays and performance isn't necessarily going to be lower so no one should obsess over thinking 1T pure is needed for better benchmarks. Real world performance even less, so, like, if 55-56 is what you need on DR set it and forget it. Don't even think about it.
> 
> Only subsequent challenge I've come across is Setup timings and tPHYRDL, but my whole Setup is just whack with tPHYRDL. As long as I stay off even tCL it trains at 26/26 and that where I'm staying. tCL13 forever 🤣


Sweet. I love stuff like this. Thank you.


----------



## Audioboxer

nick name said:


> Sweet. I love stuff like this. Thank you.


Enjoy, it's heavy stuff though lol, as I said almost like a foreign language to me.

So I come away basically thinking "So, what you're saying is use 56, enjoy TM5 passing and celebrate your AIDA64 results? Yup, good stuff, that's what I'll do" 🤣


----------



## nick name

Audioboxer said:


> Enjoy, it's heavy stuff though lol, as I said almost like a foreign language to me.
> 
> So I come away basically thinking "So, what you're saying is use 56, enjoy TM5 passing and celebrate your AIDA64 results? Yup, good stuff, that's what I'll do" 🤣


Well I just spent time trying to find my answer in a Samsung white paper so as long as I don't have to do the reading I'm sure this will be better.


----------



## error-id10t

Delete dup.


----------



## error-id10t

Really odd, so this is with 56.58 SMU. You can see that with no XMP the VDDG behaves correctly, CCD / IOD volts are as set in BIOS. If I enable XMP I'm stuck at the 1v limit, if I set it per XMP (XMP off) I'm still stuck at the 1v limit. I can keep the 1.35v RAM volts no problems, change to 1T etc but anything beoynd that it stuff it up and 1v limit appears.


----------



## PJVol

Veii said:


> Also what is this ?


Ahh.. actually I've made 2 sets of benchmarks on request for the local forum users, which is where the impact of tRCDWR = 1/2 tRCDRD can be seen. So the screen I posted is the tRCDWR 9 case, and there's another one, the same tests but with tRCDWR 18.


----------



## Dodgexander

error-id10t said:


> Really odd, so this is with 56.58 SMU. You can see that with no XMP the VDDG behaves correctly, CCD / IOD volts are as set in BIOS. If I enable XMP I'm stuck at the 1v limit, if I set it per XMP (XMP off) I'm still stuck at the 1v limit. I can keep the 1.35v RAM volts no problems, change to 1T etc but anything beoynd that it stuff it up and 1v limit appears.
> View attachment 2530957


This doesn't really make sense. I'm trying to understand your post.
Do you mean you can adjust CCD/IOD only with XMP off and only beneath 1v?

Or do you mean there was no CCD/IOD limit at all, then, since you enabled XMP it broke, meaning now there's a limit whether you have XMP on or not.

Also, do you try resetting defaults or clearing CMOS? You may be able to return to original state and never enable XMP this way.


----------



## mongoled

domdtxdissar said:


> Very good mongoled
> If we ignore the fact that a static OC is required for this comparison, as tempature and powersettings can affect the PBO clockspeed greatly in this benchmark, this is a good start aleast
> 
> So right now we have your CL16 1900fclk and PBO run from May this year = 267 gflops
> CL13 1900fclk PBO = 272 gflops (i think, if i understood you correctly)
> Your run from above with CL14 2033fclk and PBO = 272 gflops
> 
> This is a alittle apples to oranges comparison
> 
> For this to be done correctly we need multible runs, at same static cpu mhz, at same memory settings and at different infinity fabric clockspeeds to compare the scaling, as this should be the only thing changing between runs..
> 
> After all, we are only trying to determine if there is reduced scaling/no performance increase from going above 1900 fclk in Linpack.
> 
> Testing at these diffrenct infinity fabric clockspeeds would be most helpfull: 1800 -> 1866 -> 1900 -> 1933 -> 1966 -> 2000 -> 2033 -> 2066
> 
> If i were to guess, i think the results will look something like the picture i posted in my last post, but i would be very happy to be shown otherwise


Firstly, I only posted that screenshot as a quick synopsis, it was not added as a compare to anything.

Secondly, im sure your advice regards normalising the data to be consistent and static will be helpful for someone who is new to this as I fully agree with your sentiments on how this should be done



Hence the reason I said



mongoled said:


> Just when I found out how to "fix" the VST test by increasing PLL 1.8v, the PC refuses to post until I set vDDP to AUTO which defaulted to 0.9v and ive managed to post.


My mistake was not making myself clear, in that, because of said issue in posting I was not in a position to be able to run the tests with a static 4.5 ghz clock as I was too busy trying to get past this issue, hence the reason for posting a quick snapshot of what LinpackXtreme was achieving with 4066/2033 PBO ...



Veii said:


> The problem with LinX testing on a 5600X, is the absurdly low procHot limit
> It will frequency throttle beyond 65c, where higher FCLK and voltages increase this amount
> Where i haven't been able to confirm, that procHOT is disabled in OC_Mode, hence FIT isn't ~ only little part of it
> 
> A 5800X optimally would be the target for such, as it adheres to the 95-105c limit


Thank you for making this clear, unsure why domdtxdissar does not want to understand this, neither from the previous conversations regarding FCLK/LinpackXtreme or now ..........

Now back to my escapades ...

Cant trust anything anymore with high FCLK......

Its as if the system has a mind of its own!

Look below, 4066/2033, TM5 pass with only 0.860v for vDDP



There seems to be a relationship with vDDP and PLL 1.8v voltage.

I needed to push 1.9v for PLL 1.8v when running vDDP at 0.940v+ to be able to get LinpackXtreme results not to tank, problem was it stopped posting.

So I decided to re-visit low vDDP, now with vDDP set to 0.860v I get a system that posts consistently and only need to use PLL 1.8v set to 1.85v for LinpackXtreme results not to tank.

However, since making this change I am getting WHEA 18 errors on my weakest core which I never was getting before.

If I push PLL 1.8v any higher I go back to a non posting scenario


----------



## error-id10t

Dodgexander said:


> This doesn't really make sense. I'm trying to understand your post.
> Do you mean you can adjust CCD/IOD only with XMP off and only beneath 1v?
> 
> Or do you mean there was no CCD/IOD limit at all, then, since you enabled XMP it broke, meaning now there's a limit whether you have XMP on or not.
> 
> Also, do you try resetting defaults or clearing CMOS? You may be able to return to original state and never enable XMP this way.


The SMU or the AGESA (I don't which) limits CCD/IOD to 1v when using XMP or setting XMP manually. Known bug which is why others here don't even run those versions. But with XMP off and no tuning, this issue goes away. Juzt trying to understand why as only noticed it accidentally.


----------



## Nd4spdvn

error-id10t said:


> The SMU or the AGESA (I don't which) limits CCD/IOD to 1v when using XMP or setting XMP manually. Known bug which is why others here don't even run those versions. But with XMP off and no tuning, this issue goes away. Juzt trying to understand why as only noticed it accidentally.


Very interesting finding. Ive got the same board as you but when I tried the 14e BIOS despite not using any XMP whatsoever (DIMMS are PVS 4400-19 XMP) I STILL had the 1V CCD & IOD limit bug and with tons of WHEA at 3800 it made me revert to 14c BIOS . So, I am a bit confused by this and don't know what to make of it.


----------



## Veii

mongoled said:


> Thank you for making this clear, unsure why domdtxdissar does not want to understand this, neither from the previous conversations regarding FCLK/LinpackXtreme or now ..........


Its why i don't depend on it
~ prochot limit bothers, i have no AIO to give correctly running comparisons
I can't even compare it with powerdraw, as logically less FCLK = less required voltage = more boosting reserves = higher values. Not much rocket science to this
Same goes for, higher FLCK with default artificial limits = less boost score by higher require SOC. That's not package throttle

The way to compare it wouldn't even be an allcore i feel like
As first stage throttle is gone, 2nd stage isn't which is GMI link speedup ~ visible on L3 Aida. L3 to my old testing still did speed up, up to silicon strain, soo results where not consistent with an allcore
I know FIT works, but i don't fully know how much of what I don't know, remains still active

Using PBO should deliver consistent results
But being thermal limited remains still an issue

Another critique point is OpChache and branch prediction
These values as ManniX-ITA i think was it, showed continuous improvement the more times you run it
I can't take it serious as comparable benchmark, which also goes to the scientific SiSandra test
They all scale up thanks to branch prediction and instruction set learning

Non of them are random enough
While the monero miner was on one hand
Hence the difficulty changes on day by day bases, harshrate also changes *
* soo unless you compare it fast for yourself, it's not a comparable community benchmark either

It's not dom's fault
But I see too many issues to use it
Well majorly for me even with zero frequency throttle, is still the procHot throttle
After that is gone, maaybe i can compare something
So far every time you increase load, you will increase current and decrease boost
It doesnt matter if 1800 or 1900 FCLK


----------



## Veii

mongoled said:


> There seems to be a relationship with vDDP and PLL 1.8v voltage.


Yes
With how procODT behaves, which's range changes how VDDG and cLDO_VDDP behaves
Hence i mentioned (you can have issues if you go near that 1.93v mark), but 1.83v shouldn't cause any issue.i dont think 1.86 would either


----------



## error-id10t

Nd4spdvn said:


> Very interesting finding. Ive got the same board as you but when I tried the 14e BIOS despite not using any XMP whatsoever (DIMMS are PVS 4400-19 XMP) I STILL had the 1V CCD & IOD limit bug and with tons of WHEA at 3800 it made me revert to 14c BIOS . So, I am a bit confused by this and don't know what to make of it.


Just played with it more, it's not XMP. I can set XMP and play with timings as long as I set FCLK to 1600 and no more, if I raise it any higher the bug appears.  Anyhow little bit of fun to try figure what's triggering it for me at least.


----------



## blodflekk

Hi,
This is my first time using AMD, let alone overclocking on AMD. I've done my best to read online guides for timings, relationships and voltages/impedances. I also looked at the DRAM calculator for some things I was unsure of. I am running X570 dark hero, 5950x with just a PBO OC. Ram sticks are samsung B-die 2x16gb 3600 CL14-15-15-35 @ 1.45v. Can you guys let me know how I did and if there are any mistakes?
EDIT: These timings are 1000% stable in HCI memtest.


----------



## smackerrr

SneakySloth said:


> I dont think that's B die. 3600 @ 18-19-19-39-58 is definitely not B-die.


The other post I had last page with my actual timings is my other setup where I have 3600 CL16 CJR, this ones different. Corsair Vengeance 3600 CL18, but it seems like its B die. I run 16 16 16 32 52 331 stable on it.

Still working on the CJR kit though, that ones way more important for me.

Thanks for all the replies.


----------



## Veii

blodflekk said:


> Hi,
> This is my first time using AMD, let alone overclocking on AMD. I've done my best to read online guides for timings, relationships and voltages/impedances. I also looked at the DRAM calculator for some things I was unsure of. I am running X570 dark hero, 5950x with just a PBO OC. Ram sticks are samsung B-die 2x16gb 3600 CL14-15-15-35 @ 1.45v. Can you guys let me know how I did and if there are any mistakes?
> EDIT: These timings are 1000% stable in HCI memtest.
> View attachment 2531002


Confirm 2T GDM off stability, with 10 000% or 25 rounds 1usmus_v3 (TM5)

Likely tWR needs to be 12 (double tRTP) or 14 (=tCL) 
SD, DDs for Dual Rank, need to be 1-4-4-1-6-6 , test it
Bandwidth test it wit an average of 3-4 Aida64 results


----------



## Dodgexander

error-id10t said:


> The SMU or the AGESA (I don't which) limits CCD/IOD to 1v when using XMP or setting XMP manually. Known bug which is why others here don't even run those versions. But with XMP off and no tuning, this issue goes away. Juzt trying to understand why as only noticed it accidentally.


Thanks. Now it makes sense. My x570 Auros Elite seems to share this bug in recent bios too but there's no option to manually set XMP. The options are XMP on or off.

The Aorus owners thread has some posters who warn about it, but I didn't realize it was only when using XMP.

I think most users in this thread will be using manual timings without XMP enabled. Particularly on ram that's not optimized for Ryzen. My Patriot viper kit for example.


----------



## Dodgexander

smackerrr said:


> The other post I had last page with my actual timings is my other setup where I have 3600 CL16 CJR, this ones different. Corsair Vengeance 3600 CL18, but it seems like its B die. I run 16 16 16 32 52 331 stable on it.
> 
> Still working on the CJR kit though, that ones way more important for me.
> 
> Thanks for all the replies.


If that was B die you'd probably be getting timings two notches down from that at 3600. The best b die dimms here have results as high as 4000 cl14 and some can do 3800 cl14 too. Pretty sure I've seen 3600 cl12 at some stage with b die.

Mine are cheap patriot bins and can do 3800cl15. They almost do 14 but I just can't get stable.

Be careful with voltages if you aren't sure because b die can allow you to use a high number. If you push the same into another die you may break it.

Also remember the VEIL rule. Higher ProcODT increases the current going to your ram so high ProcODT and low voltage can be dangerous just like high voltage and low ProcODT.

in fact you can argue procODT is more dangerous.


----------



## domdtxdissar

mongoled said:


> Thank you for making this clear, unsure why domdtxdissar does not want to understand this, neither from the previous conversations regarding FCLK/LinpackXtreme or now ..........


This again ? 

Its not that i "dont understand", its perfectly clear for me, some people are using this fit temp limit excuse (when it dont matter for static oc) as a scapegoats to avid providing the data requested, the data that would prove if their high IF speed are throttling in linpack or not, once and for all, its simple as that 



> Where i haven't been able to confirm, that procHOT is disabled in OC_Mode, hence FIT isn't


No, 5600x are not limited by fit 65 temp limit throttling when running in OC mode.
There are nothing stopping you mongoled from doing this comparison at diffrent IF speeds when using a static OC.

If the cpu cant handle 4.5gh allcore / you dont trust me in regards to 65 temp limit in OC_mode, you can very well run low voltage and stay at 4ghz to be 100% sure to never break 65 degress.

But i fear we wont see results either way, because it would would require some admissions in regards to less then stellar scaling above 1900 fclk, and that we dont want


----------



## mongoled

Dodgexander said:


> Also remember the VEIL rule. Higher ProcODT increases the current going to your ram so high ProcODT and low voltage can be dangerous just like high voltage and low ProcODT.


Can you explain why high voltage and low ProcODT can be dangerous? I'm currently testing vDIMM @1.680v, vSOC @1.175v and ProcODT @28.2 ohms.

😀


----------



## PJVol

domdtxdissar said:


> No, 5600x are not limited by fit 65 temp limit throttling when running in OC mode.


Neither with PBO. The only limiter here is "Max_boost_clock" - 250Mhz (i.e. 4400 in stock or 4600 with +200 boost override), when temps are above 90°C. Not sure if it works in OC-mode (probably not)


----------



## Audioboxer

Speaking of high voltage, funny story, when I was trying to stabilise FCLK 2000 and was playing around with CPU 1.8v, I accidentally didn't scroll down far enough and entered 1.9v into VDIMM. Got into Windows and ran a y-cruncher and the PC basically lost it and rebooted. Not high enough I thought, but I was confused as I hadn't had a y-cruncher reboot previously, just USB disconnects. So I went back and changed 1.9v to 2.0v as I remembered Buildzoid pointing out a higher CPU 1.8v can sometimes help IF and he was running either 2.0v or it might have been more. Again, into Windows and y-cruncher caused the PC to lose it right away.

Then I noticed I had just pumped 2.0v through my memory on the second entry to the BIOS


----------



## MrHoof

Audioboxer said:


> Speaking of high voltage, funny story, when I was trying to stabilise FCLK 2000 and was playing around with CPU 1.8v, I accidentally didn't scroll down far enough and entered 1.9v into VDIMM. Got into Windows and ran a y-cruncher and the PC basically lost it and rebooted. Not high enough I thought, but I was confused as I hadn't had a y-cruncher reboots previously, just USB disconnects. So I went back and changed 1.9v to 2.0v as I remembered Buildzoid pointing out a higher CPU 1.8v can sometimes help IF and he was running either 2.0 or it might have been more. Again, into Windows and y-cruncher caused the PC to lose it right away.
> 
> Then I noticed I had just pumped 2.0v through my memory on the second entry to the BIOS


Well i guess good that you are watercooling your dimms afterall  else that could have ended bad.


----------



## Audioboxer

MrHoof said:


> Well i guess good that you are watercooling your dimms afterall  else that could have ended bad.


It was this video I had remembered the comment on trying to help with IF






Which he actually does run his VDIMM on 2.0v for extreme overclocking, so part of me just wonders if my eyes were on auto-pilot and looked to set VDIMM to 2.0v _on purpose_, but my brain and thought process was _looking_ for CPU 1.8.

But hey, silver-lining, at least I know I can boot into Windows with 2.0v on the VDIMM


----------



## Dodgexander

mongoled said:


> Can you explain why high voltage and low ProcODT can be dangerous? I'm currently testing vDIMM @1.680v, vSOC @1.175v and ProcODT @28.2 ohms.
> 
> 😀


That's dyslexia for you. Sorry😔


----------



## Veii

domdtxdissar said:


> No, 5600x are not limited by fit 65 temp limit throttling when running in OC mode.
> There are nothing stopping you mongoled from doing this comparison at diffrent IF speeds when using a static OC.
> 
> If the cpu cant handle 4.5gh allcore / you dont trust me in regards to 65 temp limit in OC_mode, you can very well run low voltage and stay at 4ghz to be 100% sure to never break 65 degress.
> 
> But i fear we wont see results either way, because it would would require some admissions in regards to less then stellar scaling above 1900 fclk, and that we dont want


2nd post (mine) should have cleared up this part
I mentioned that i'm not against this or hiding anything

Just that it makes no sense from an usage (comparison) standpoint
Hence branch prediction is active and will falsify the results the longer you run it
An low allcore as you wrote, i've mentioned too as a possible ~ probably only, option just to be sure to stay sub 60-62c in any case. As *FIT is not disabled on OC_Mode*

Soo i haven't denied it, just not delivered yet on this method of testing


PJVol said:


> Neither with PBO. The only limiter here is "Max_boost_clock" - 250Mhz (i.e. 4400 in stock or 4600 with +200 boost override), when temps are above 90°C. Not sure if it works in OC-mode (probably not)


Prochot is the only limiter for me currently active, that ruins my 4.85 on load
Which is not AVX2 exclusive and happens also in AVX/FMA title
THM at 94 doesn't bypass it ~ and it keeps consistently ruining the boost
I've wrote about it with exact same shown test on LinX ~ and around the time when i stopped carrying about this tool , as it was not really comparable.
(2? months ago, around the time BZ uploaded the tFAW comparison video with his 5950X)
Same was for SiSandra MATS test. Done it, maybe it was overlooked. But showed that results keep improving the longer & more often you run it.

Please don't missunderstand (both) that i did ignore them.
I'm times ago past these testing and don't bother right now. Prioritize other research, as my unit doesn't have WHEA #19 issues to even bother with this.
Only #18 when i do other stupid things with my cores , hydra and PBO ~ which slightly earns my time now
Also spend my time on something more fun which is RX Navi XT (XH & C) series, while waiting till zen3D/4D releases finally & Microsoft L3 throttle fix ~ to reinstall
Long past voltage searching or Vermeer platform support. ~ since my last score end of May

Only when AMD starts to role out PSP-FW fixes, then maybe WHEA thematic can be taken a look at again.
Currently it's waiting and waiting. I won't get RSMU access tool as it seems, soo i'm done with this topic. There is just not much to "research and fix" left.
Only fixing my own 2133 FCLK package throttle ~ then i'd be fully done with this sample and can sell it, or put in a trophy glas.
But who knows, this already takes 4-5 months. Might as well take 1 more till we get updated bioses
SPI ROM Armor also needs to be broken, but maybe will never be (lack of time) ~ people should just buy HW-SPI Flasher

EDIT:
Already considering selling it or not selling it
I don't want honestly. It's a rare sample, but Zen3D/4D is more appealing then going against an unfixable issue without AMD doing anything against it
I lack the tools to fix it, soo why even bother spending more time on it


Veii said:


> Only when AMD starts to role out PSP-FW fixes, then maybe WHEA thematic can be taken a look at again.


They are atm under ADL strain, soo i'm not judging them much.
They also have other priorities to focus. Navi drivers and their Frequency + VRAM Freq lockdowns ~ already are taking a lot of time
We start to get driver updates on weekly bases now, instead one in 1-2 months.
I see AMD does try on many sides, soo they don't deserve my bothering/mocking either 

It will fix itself, when it fixes itself
Or somebody like Yuri assists the community after being less busy with his projects (multiple)
As he surely is capable to rewrite Vermeer's ~ *when he wants to bother*.
*IF even*, as he'd need to burn business bridges, by going against AMD's decision
~ for an OCN community that piracy leaked Hydra Alpha or keeps fighting with him about how DDR4 functions and what he's seen by his research, similar how people fight with me against little things that don't much their experiences
Soo unsure that such is even worth it, for his reputation and development team (assisting in something against AMDs blessing)
(these people have to eat something after all ~ me too a little bit at least, soo i'm not bothering with a lost cause further/so far ~ till anything actually happens AGESA or RSMU wise)

EDIT2:
I think @ManniX-ITA was it
Here, CO's can function on a 5900X without being package throttled
Somebody i've still promised to take a look on dual CCDs (5950X & 5900X still aren't delivered yet, neither the better DR kits)


Spoiler: No CO throttle, but limited at -30 already












Excuse my poor picture, that's all i got send
MSI B550 Carbon Wifi


This goes in combination with CoreCycler - tool for testing Curve Optimizer settings also Asrock X370 Taichi Overclocking Thread with Asrock X370 Taichi Overclocking Thread
Then Asrock X370 Taichi Overclocking Thread pointing to still valid AMD max overclocking voltage and CoreCycler - tool for testing Curve Optimizer settings 
People keep fighting with me over little things, but beg for help (continuing half post above) then not even try to bookmark little snippets i share , for example here about CO tickery and how it functions

Well generally, ManniX ~ i think you've complained once about Hydra CO not functioning, i didn't forget that i'm still owing you a result
I can't say it doesn't function ~ a "bronze" 5900X is capable. When limits are already at -30 , there is no need use fMax extend to further allow frequency stretch and throttle








Rather stay on lower clock, and be sure it's not throttling at all ~ than push higher boost while consistently have irregular inaccurate results as boosting system keeps throttling in "fixed random matter" 

If people can't get their CPUs to behave correctly , what sense does it even make to compare results , when everything is dynamic 🤭
This includes Aida64 L3 cache for example and the complains against Microsoft ~ while they are right, still.
Review media claims performance results. People follow this and mention that our Bronze/silver samples are a 0.001% silicon lottery win. Funny 😅
Overclocker here should have given their best , and at least not judge that harshly against their own team. Judge review media for doing a poor job, but don't mock people who spend their time free here without any benefits except public global good (improving AMD research further)


----------



## blodflekk

Veii said:


> Confirm 2T GDM off stability, with 10 000% or 25 rounds 1usmus_v3 (TM5)
> 
> Likely tWR needs to be 12 (double tRTP) or 14 (=tCL)
> SD, DDs for Dual Rank, need to be 1-4-4-1-6-6 , test it
> Bandwidth test it wit an average of 3-4 Aida64 results


Thanks for your help! I have made these changes, will run HCI memtest overnight to check stability


----------



## Veii

blodflekk said:


> Thanks for your help! I have made these changes, will run HCI memtest overnight to check stability


TM5 if you miss it, was gettable here


https://www.overclock.net/attachments/tm5-zip.341254/


It was only 20 cycles, but for 32gb it should be plenty. Should take about 3 hours
Usually you'd want to run 25 cycles to catch tRFC issues too
config is read only to prevent self corruption on BSODs ~ might want to edit it to 25 cycles & put it back read-only or keep it how it is
(anything longer than 1h is acceptable on TM5)

TM5 needs to be run with Admin permissions, to have higher permissions taking as much memory as possible & scaling across all threads
The first time you'll have UAC warnings, just spam OK
On the next launch/reboot, they will be gone
If the config doesn't load and creates an MT.link file, erase it and it will autoload MT.cfg on the next launch (which has to be 1usmus_v3 his)

EDIT:
You don't need to care about Aida performance numbers, when you aren't passing TM5 stability testing or similar HCI/Karhu 10000%
(stability rating there was set far higher by the german community)
TM5 25 cycles, should catch 99% of the issues. Later you still can run GSAT (google memtest shell) or Karhu/HCI, if you use this in a server environment or financial side 
Or just finish off with OCCT extreme test-mode, (1h) for personal usecase
OCCT should also catch most of the core and voltage/memory stability issues, after TM5 which is purely a timings oriented test


----------



## blodflekk

You don't run the extreme preset on amd ?


----------



## Veii

blodflekk said:


> You don't run the extreme preset on amd ?


We do, anta made us an "ABSOLUTE" preset
But this preset while testing well voltage and discharge behavior - seems to miss timings differences

It also hardly errors after 1.55vDIMM guaranteed ~ soo it wasn't usable for people who daily 1.6-1.65v 
1usmus_v3 while not being fully perfect as it seems, still catches the errors well. This is really all it matters about it
It's lightweight to the CPU, low IPC load and catches errors that anta's test seem to overlook

I also wish for something better, but the attempt didn't succeed much
Else 3 cycles anta's old public config, (should also take 3h for 32gb) seems to be equally fine
Yea no, we just have something better functioning. Better in the sense of it catches things anta's overlooks.

HCI & Karhu are great
But are CPU stability dependent. Which is sub optimal sadly
TM5 ended up being a great option to only catch DRAM issues , with a very low chance to be fabric stability issues
Such catches y-cruncher very well, the component test mode (1-7-0) , 4 loops of such = 72min & later finishing off with OCCT Extreme (is a linpack large dataset mode)


----------



## mongoled

domdtxdissar said:


> This again ?
> 
> Its not that i "dont understand", its perfectly clear for me, some people are using this fit temp limit excuse (when it dont matter for static oc) as a scapegoats to avid providing the data requested, the data that would prove if their high IF speed are throttling in linpack or not, once and for all, its simple as that
> 
> 
> 
> No, 5600x are not limited by fit 65 temp limit throttling when running in OC mode.
> There are nothing stopping you mongoled from doing this comparison at diffrent IF speeds when using a static OC.
> 
> If the cpu cant handle 4.5gh allcore / you dont trust me in regards to 65 temp limit in OC_mode, you can very well run low voltage and stay at 4ghz to be 100% sure to never break 65 degress.
> 
> But i fear we wont see results either way, because it would would require some admissions in regards to less then stellar scaling above 1900 fclk, and that we dont want


Hey,

I do my best not to see things as someone being right or wrong in this domain thats our hobby, especially with these CPUs and the types of benching software we are using.

The simple matter of fact is and I think I can say this with a degree of confidence, is that nobody here can really have all the knowledge to be able to make that sort of judgement in that "I am right and you are wrong".

Moving on from that, its been documented by myself in these forums in previous conversation that I am in agreement that using a higher FCLK than 1900 can lead to performance degradation, but this is not black and white!

You come across as not agreeing with this POV and thats fine by me, its just that I dont understand this POV, thats all.

Im not interested in such "call outs" regards to why people are not posting what you are asking, even though some of us already done this several months ago.....

Anyhow, as I have some pressing work to get to ive done two screenshot for you.

4.5Ghz fixed clock
All setting exactly the same except MCLK/FLCK

*3800/1900 - Avg 266.9580
4066/2033 - Avg 267.3095*

Now....for high FCLK this result in only possible by getting the right combination of vDDP/PLL 1.8v voltages, at 1900, you can have "inefficient" vDDP/PLL 1.8v voltages and it wont effect the result by much, but with high FCLK it makes a huge difference.

If there is something not too your liking with regards to how I did these tests please let me know.

Now to a slight apology on my behalf for a misunderstanding, previously I commented



mongoled said:


> I've never ever seen close to 275 obtained even when running tCL @13 3800/1900, even from people running 5950x.
> 
> My highest ever LinpackXtreme at 3800/1900 when running the 3rd option is 271 Gflops using tCL @13
> 
> And that did not happen reliably across reboots, some reboots it would be 268/9 others 270/271.


I should have made it clear that I was talking about using PBO/CO not static overclock

And then more importantly (at least for me) when you posted the 280+ results my mind was stuck on a PBO/CO overclock, little did I notice that you were running a 4.85 Ghz static overclock for those results

 

So to sum up, yes, there is an "issue" going on when we push high FCLK, as to the causes, none of us can really know, the only person posting here who has put the countless hours into investigating such issue is @Veii and for that reason I would rather go with what Veii is saying then anyone else, however that does not mean that Veii is "correct"

And your points regards fit limit are valid, its just we cannot be completely sure due to the nature of these processors.

*3800/1900*









*4066/2033*









*Voltages (switched back to PBO)







*





Dodgexander said:


> That's dyslexia for you. Sorry😔


Thats OK bud, I was just concerned you had information that I hadnt come across before


----------



## Audioboxer

Bit of a noob question but if you don't ask you don't learn, at what point with AMD can it be beneficial running memory out of sync with IF or does that point not really exist and/or require too much of a leap from FCLK 1900?

Always stayed in sync myself but just wondering what sort of memory frequency do we have to talk about potentially seeing?

Also if memory is ran out or sync does that impact memory stability testing? Even if performance is worse, for science!, I would probably still like to run my memory speed higher and higher just to test what timings I can get stable. Doing this with FCLK 2000+ just brings the side effect of IF issues and if I could stay at 1900 and just play with memory for the fun of it I'd probably do just that.

But I'd want to be confident TM5, Karhu and others are properly testing my memory when it is out of sync.

In other words, I like overclocking memory and I'm a bit bored now stuck at 3800/1900 running tCL13 on a profile that genuinely can't really be tuned any more  But trying to stabilise FCLK 2000 has just been a failed effort, as I cannot seem to stop USB issues.


----------



## PuffyArgos

@Veii @mongoled
I hope you guys are keeping well. Some time ago you guys helped me to stabilize the following:



Spoiler: 3950x on Gigabyte B550 Pro V2 with TG 16g 3600c14 kit at 3800c14















Since then I have been watching everyone having fun with Ryzen 5000 and thought perhaps I could give a 5950x a shot to test out IF2000, even if I had to give up flat 14s (thinking even flat 16s at 2000mhz has more theortical bandwidth if the IMC can handle it).

I had a further thought that it would be nice to get away from the TG kits. It just seems everyone with gskill was getting better bins. If I would make the jump it seemed to also make sense to grab a dual rank kit to test out the advantages of rank interleaving.

The new machine is a 5950x on a Gigabyte B550 Pro V2 with GS 32g 3600c14.

As before, I decided to start by tightening timings with 1800 before moving to 1900 and then ultimately test out 2000 and higher. It has not gone well as I am still stuck at 1800.



Spoiler: 5950x on a Gigabyte B550 Pro V2 with GS 32g 3600c14 kit at 3600c14















This configuration boots fine and passes a quick 3 run test on TM5, however, I can't shake that pesky GDM. As soon as I disable GDM I am flooded with errors on test 6.

With the 3950x I can use 50 mV stepping at 1800 as follows
VDDP: 900
VDDG: 950
SOC: 1000
For 1900 you can see I use a double 50 mV and this works just fine.
VDDP: 900
VDDG: 1000
SOC: 1100

On the new kit I thought perhaps the 5000 series likes a bit more welly, but I wanted to avoid the 1.2v SOC setting my MB defaults on. I thought I would use a 75 mV step with a bit more juice to the memory controller. This works on 1800, but only with GDM on.
VDDP: 900
VDDG CCD: 950
VDDG IOD: 1000
SOC: 1050

I have kept the CAD bus the same with the logic that the board is the same. Perhaps this is faulty logic. I've made some changes to the data bus, but I'm not sure how this scales with voltage as it's very different from the data bus of my 1R kits.

Is there something I'm missing with these dual rank kits or the new CPU? Any thoughts on how to get away from running GDM?

I really appreciate your thoughts.


----------



## nick name

@PuffyArgos Setting AddrCmdSetup to 56 let's me run 1T with GDM off at 3800MHz. I didn't have to adjust SOC, VDDG, or VDDP.


----------



## Audioboxer

PuffyArgos said:


> @Veii @mongoled
> I hope you guys are keeping well. Some time ago you guys helped me to stabilize the following:
> 
> 
> 
> Spoiler: 3950x on Gigabyte B550 Pro V2 with TG 16g 3600c14 kit at 3800c14
> 
> 
> 
> 
> View attachment 2531108
> 
> 
> 
> 
> Since then I have been watching everyone having fun with Ryzen 5000 and thought perhaps I could give a 5950x a shot to test out IF2000, even if I had to give up flat 14s (thinking even flat 16s at 2000mhz has more theortical bandwidth if the IMC can handle it).
> 
> I had a further thought that it would be nice to get away from the TG kits. It just seems everyone with gskill was getting better bins. If I would make the jump it seemed to also make sense to grab a dual rank kit to test out the advantages of rank interleaving.
> 
> The new machine is a 5950x on a Gigabyte B550 Pro V2 with GS 32g 3600c14.
> 
> As before, I decided to start by tightening timings with 1800 before moving to 1900 and then ultimately test out 2000 and higher. It has not gone well as I am still stuck at 1800.
> 
> 
> 
> Spoiler: 5950x on a Gigabyte B550 Pro V2 with GS 32g 3600c14 kit at 3600c14
> 
> 
> 
> 
> View attachment 2531110
> 
> 
> 
> 
> This configuration boots fine and passes a quick 3 run test on TM5, however, I can't shake that pesky GDM. As soon as I disable GDM I am flooded with errors on test 6.
> 
> With the 3950x I can use 50 mV stepping at 1800 as follows
> VDDP: 900
> VDDG: 950
> SOC: 1000
> For 1900 you can see I use a double 50 mV and this works just fine.
> VDDP: 900
> VDDG: 1000
> SOC: 1100
> 
> On the new kit I thought perhaps the 5000 series likes a bit more welly, but I wanted to avoid the 1.2v SOC setting my MB defaults on. I thought I would use a 75 mV step with a bit more juice to the memory controller. This works on 1800, but only with GDM on.
> VDDP: 900
> VDDG CCD: 950
> VDDG IOD: 1000
> SOC: 1050
> 
> I have kept the CAD bus the same with the logic that the board is the same. Perhaps this is faulty logic. I've made some changes to the data bus, but I'm not sure how this scales with voltage as it's very different from the data bus of my 1R kits.
> 
> Is there something I'm missing with these dual rank kits or the new CPU? Any thoughts on how to get away from running GDM?
> 
> I really appreciate your thoughts.


DR so put 56 into AddrCmdSetup. If you have issues with 56, try 55.


----------



## PJVol

Veii said:


> Prochot is the only limiter for me currently active, that ruins my 4.85 on load


I guess I didn't miss all the posts you linked to, but still can't understand how this "prochot" issue look like. What do you mean "ruins 4.85"?
Can you share what's going on in more detail?

PS: You know, I think I lost interest in undisclosed Zen3 info for some time, because even without having access to it, and thanks to the community, there is little left untouched from the technical side of it.
So the issue you mention is definitely worth thinking )


----------



## PuffyArgos

@Audioboxer @nick name 
Thank you for the recommendation.

I tried both 55 and 56 to no avail. Of course, this was while I was still running a 75 mV step from VDDP: 900 for a SOC volatage of 1025 mV.

Having taken note that @Audioboxer left his SOC voltages stock, I did bump up to a double 50 mV step. This isn't quite 1200 mV, but at 1100 mV it is higher than the initial trials. This gets me past test 6 without AddrCmdSetup, and funny enough, fails test 6 with AddrCmdSetup. Perhaps AddrCmdSetup this is something I need to keep in mind when pushing higher voltages and higher IF clocks (1900 and 2000).

Now that I've made it past the initial IMC test with 1100 mV soc (a bit higher than I would haved expected for 1800...) I have basically ran straight into a brick wall errors on every test that isn't related to the IMC.😂



Spoiler: 1800 GDM Off






















I have increased VDIMM from 1.48V to 1.52V, but that hasn't made a dent in it. Thinking of moving tRAS to 30, tRP to 44 and tRFC to 264 as a start. If anyone sees something painfully obvious that I've botched here, please don't hesitate to let me know.


----------



## Audioboxer

PuffyArgos said:


> @Audioboxer @nick name
> Thank you for the recommendation.
> 
> I tried both 55 and 56 to no avail. Of course, this was while I was still running a 75 mV step from VDDP: 900 for a SOC volatage of 1025 mV.
> 
> Having taken note that @Audioboxer left his SOC voltages stock, I did bump up to a double 50 mV step. This isn't quite 1200 mV, but at 1100 mV it is higher than the initial trials. This gets me past test 6 without AddrCmdSetup, and funny enough, fails test 6 with AddrCmdSetup. Perhaps AddrCmdSetup this is something I need to keep in mind when pushing higher voltages and higher IF clocks (1900 and 2000).
> 
> Now that I've made it past the initial IMC test with 1100 mV soc (a bit higher than I would haved expected for 1800...) I have basically ran straight into a brick wall errors on every test that isn't related to the IMC.😂
> 
> 
> 
> Spoiler: 1800 GDM Off
> 
> 
> 
> 
> View attachment 2531120
> View attachment 2531121
> 
> 
> 
> 
> I have increased VDIMM from 1.48V to 1.52V, but that hasn't made a dent in it. Thinking of moving tRAS to 30, tRP to 44 and tRFC to 264 as a start. If anyone sees something painfully obvious that I've botched here, please don't hesitate to let me know.


Whatever errors you still have when using AddrCmdSetup time, I would not revert back to using 0. Quite honestly it should almost simply be stated to everyone "You will not get DR memory running 1T with GDM disabled and no Setup times". Actual reality, maybe you will, but you're likely going to need a Ryzen G chip and/or a good amount of "silicon luck".










That is what I am running, VSOC is not on AUTO, it is manually set to 1.15v which droops to around 1.125v.

Try 56/56/56, although most people on 5xxx CPUs tend to get by just fine only setting AddrCmdSetup to 56.

You can also try other values than 55/56, though going below 55 is likely to just increase instability. Try going higher if you need to, though my thoughts are it's not the Setup time being 56, but other instability you have at that point. 1T without setup times on DR will likely spit out LOTS of errors within seconds, often a lot of 6's. If they go away with Setup times then any other errors are possibly timings, resistance or voltage related.


----------



## Bix

PuffyArgos said:


> @Audioboxer @nick name
> Thank you for the recommendation.
> 
> I tried both 55 and 56 to no avail. Of course, this was while I was still running a 75 mV step from VDDP: 900 for a SOC volatage of 1025 mV.
> 
> Having taken note that @Audioboxer left his SOC voltages stock, I did bump up to a double 50 mV step. This isn't quite 1200 mV, but at 1100 mV it is higher than the initial trials. This gets me past test 6 without AddrCmdSetup, and funny enough, fails test 6 with AddrCmdSetup. Perhaps AddrCmdSetup this is something I need to keep in mind when pushing higher voltages and higher IF clocks (1900 and 2000).
> 
> Now that I've made it past the initial IMC test with 1100 mV soc (a bit higher than I would haved expected for 1800...) I have basically ran straight into a brick wall errors on every test that isn't related to the IMC.😂
> 
> 
> 
> Spoiler: 1800 GDM Off
> 
> 
> 
> 
> View attachment 2531120
> View attachment 2531121
> 
> 
> 
> 
> I have increased VDIMM from 1.48V to 1.52V, but that hasn't made a dent in it. Thinking of moving tRAS to 30, tRP to 44 and tRFC to 264 as a start. If anyone sees something painfully obvious that I've botched here, please don't hesitate to let me know.


You need to find a stable baseline at 2T rather than jumping straight to 1T. I'm sure others will correct me if I'm wrong but you should be able to get 2T stable without any setup timings.


----------



## Bix

Audioboxer said:


> Bit of a noob question but if you don't ask you don't learn, at what point with AMD can it be beneficial running memory out of sync with IF or does that point not really exist and/or require too much of a leap from FCLK 1900?






This is all pre Zen 3 but since the IMCs are the same I'm guessing it's still relevant.


----------



## Dodgexander

Audioboxer said:


> Bit of a noob question but if you don't ask you don't learn, at what point with AMD can it be beneficial running memory out of sync with IF or does that point not really exist and/or require too much of a leap from FCLK 1900?
> 
> Always stayed in sync myself but just wondering what sort of memory frequency do we have to talk about potentially seeing?
> 
> Also if memory is ran out or sync does that impact memory stability testing? Even if performance is worse, for science!, I would probably still like to run my memory speed higher and higher just to test what timings I can get stable. Doing this with FCLK 2000+ just brings the side effect of IF issues and if I could stay at 1900 and just play with memory for the fun of it I'd probably do just that.
> 
> But I'd want to be confident TM5, Karhu and others are properly testing my memory when it is out of sync.
> 
> In other words, I like overclocking memory and I'm a bit bored now stuck at 3800/1900 running tCL13 on a profile that genuinely can't really be tuned any more  But trying to stabilise FCLK 2000 has just been a failed effort, as I cannot seem to stop USB issues.


Taken from the DDR4 oc guide on GitHub. It's actually sooner than you think:










> For some reason there is a large black gap below the image that I can't remove on mobile, whatever.


In turn, these figures in the guide were taken from buildzoid. To match the latency people are getting post tightening timings I'd bet that FCLK and MCLK need to be even higher than in that graph though.

The limiting factor is FCLK and UCLK needs to match MCLK.

I tried it to run my ram at it's XMP 4400 and 4200 profile but my system won't post with MCLK and UCLK higher than 4000. Looking back now that is probably down to a bug with my motherboard limiting VDDG when using XMP.

@mongoled if I can write the rule correctly this time I believe procODT being high has a similar effect to vDIMM being high. Reading veils advice he says it's best to find lowest procODT to keep signal clean and raise voltage than it is to have lower vDIMM and raise procODT.
To use a loose example, some people have set procODT to 60 ohms and vDIMM 1.5v This high the electricity circulating the ram could be more dangerous than say 34.3 ohms and 1.65v.
So the limits of voltage widely talked about with ram is highly related to procODT also. Higher procODT the stronger the current, which is why it can be just, if not more dangerous then voltage.

And to further ramble on it's actually high current in electricity that makes getting an electric shock more dangerous. You can get shocked with a very high voltage and low current and survive. But you can get shocked by a high current and low voltage and die.


----------



## Audioboxer

Bix said:


> This is all pre Zen 3 but since the IMCs are the same I'm guessing it's still relevant.





Dodgexander said:


> Taken from the DDR4 oc guide on GitHub. It's actually sooner than you think:
> View attachment 2531129
> 
> 
> 
> In turn, these figures in the guide were taken from buildzoid. To match the latency people are getting post tightening timings I'd bet that FCLK and MCLK need to be even higher than in that graph though.
> 
> The limiting factor is FCLK and UCLK needs to match MCLK.
> 
> I tried it to run my ram at it's XMP 4400 and 4200 profile but my system won't post with MCLK and UCLK higher than 4000. Looking back now that is probably down to a bug with my motherboard limiting VDDG when using XMP.
> 
> @mongoled if I can write the rule correctly this time 8 believe procODT being high has a similar effect to vDIMM being high. Reading veils advice he says it's best to find lowest procODT to keep signal clean and raise voltage then it is to have lower vDIMM and raise procODT.
> To use a loose example, some people have set procODT to 60 ohms and vDIMM 1.5v This high the electricity circulating the ram could be more dangerous than say 34.3 ohms and 1.65v.
> So the limits of voltage widely talked about with ram is highly related to procODT also. Higher procODT the stronger the current, why can be just, if not more dangerous then voltage.
> 
> And to further ramble on it's actually high current in electricity that makes getting an electric shock more dangerous. You can get shocked with a very high voltage and low current and survive. But you can get shocked by a high current and low voltage and die.


Hmm, a quick peak at the table in that video and it simply seems it's not worth it to run daily due to latency, fine, but I guess if testing apps continue to function as they should I could go on to still having some fun with memory frequency and seeing what timings I can get stable.

Secondly, I might give Hydra a shot. Seems it's a lot better than CTR (and safer!), and while I think PBO with a good curve is probably all that is needed, I guess some fun looking at a hybrid scenario might fix that OCer itch for me 

Running out of things to do now, everything just kind of works... and works well. Which... is the end game, but you all know what it's like, it's fun to get that buzz of passing stability tests!


----------



## sealxohd

I just cant get 1T stable. I tried different voltages, restitances timings etc.

This was the chill 2T config I started with but even these timings were impossible to stabilize for me:









This setting is 1.53V. All the classic RTTs didnt work. 40/20/20/20 is also a nono.

I played at 1.65 V with a 1T setting as well, which actually was more stable then the one above:









Im back to my GDM Setting now:











PS: I dont know why tWR scales negativly with voltage for me. Under 1.52 V tWR 10 is stable but with more voltage it just gets worse.


----------



## Audioboxer

sealxohd said:


> I just cant get 1T stable. I tried different voltages, restitances timings etc.
> 
> This was the chill 2T config I started with but even these timings were impossible to stabilize for me:
> View attachment 2531132
> 
> 
> This setting is 1.53V. All the classic RTTs didnt work. 40/20/20/20 is also a nono.
> 
> I played at 1.65 V with a 1T setting as well, which actually was more stable then the one above:
> View attachment 2531134
> 
> 
> Im back to my GDM Setting now:
> 
> View attachment 2531133
> 
> 
> 
> PS: I dont know why tWR scales negativly with voltage for me. Under 1.52 V tWR 10 is stable but with more voltage it just gets worse.


If you're going to run a tRAS as low as 21 and tRP 11 I advise running TM5 1usmus v3 to check it doesn't timeout. I dare say running GDM enabled may allow GDM to auto-correct errors from the timings. IMO there is absolutely no point in running tRAS as low as 21 and all it may do is lead to stability issues. 22-24 is as low as I'd go, and I found out I was getting TM5 timeouts with 22.

The first picture you posted should be able to go to 1T with AddrCmdSetup 56. Change Rtts to 7/3/3, tCKE should be fine at 1, tRTP 6 or 7, TWR 12 or 14 and see if that passes without changing those primaries as of yet.

1.65v is a bit high for what you're trying at 3733. While my bin of RAM is technically better than yours, there is every change you could achieve this










At 3733. Though VDIMM might need to go a bit higher for you depending on "silicon luck". tRCDRD at 13, even at 3733 is a tall ask for DR, I'd be making sure it can pass with GDM disabled.


----------



## Asutz

Are the G.Skill Flare X cl14 Sticks still a good pick or what is better ? wanna replace 32gb Crucials in the future.


----------



## aditrex

Asutz said:


> Are the G.Skill Flare X cl14 Sticks still a good pick or what is better ? wanna replace 32gb Crucials in the future.


they are very solid i have them still on my second rig it can do fast timing 3733 cl14 15 15 .. at 1.48volts no problem but i got recently ripjaws32gb kit 4400cl17 they work flawless on 3800 flat cl14 1.45 volts


----------



## MrHoof

aditrex said:


> they are very solid i have them still on my second rig it can do fast timing 3733 cl14 15 15 .. at 1.48volts no problem but i got recently ripjaws32gb kit 4400cl17 they work flawless on 3800 flat cl14 1.45 volts


Nice that would mean that the 4400 c17 is similar to the 4000 c14 for a cheaper price. My 3600 14-15 kit needs 1.55v for flat 14 at 3800mhz.


----------



## nick name

MrHoof said:


> Nice that would mean that the 4400 c17 is similar to the 4000 c14 for a cheaper price. My 3600 14-15 kit needs 1.55v for flat 14 at 3800mhz.


I wish I had a DR 32GB kit. The 4400C19 does well, but those newer DR kits seem to do very well.


----------



## MrHoof

nick name said:


> I wish I had a DR 32GB kit. The 4400C19 does well, but those newer DR kits seem to do very well.


I tested SR 16GB before on this same setup and the diffrence in the end is like -500mb read and about +2.5gb copy with about the same latency. Anyone has a idea how DR is slightly worse in read test in aida?

edit: Can´t comment on Write results since 1CCD and always max results.


----------



## TimeDrapery

Okay, mostly unpacked from this move to the new spot... Now I should be able to start dedicating more of my time to scientific pursuits 😂😂😂😂😂

I'll tell you what's frustrating... Running OCCT's Memory test for a period of one hour and having it crash as soon as it completes testing because the many iterations of the CPU test / CoreCycler weren't sufficient to reveal Core 0's instability at a -7 CO offset... -5 is stable 😂😂😂😂😂










It's nice that it'll hold 4850MHz under OCCT's AVX2 load but very confusing to me at the same time as it'll readily peak at that frequency under TM5 but it won't hold it like when I run OCCT










Here's my baseline to start working up higher fabric / memory speeds

I did tighten further at 3800MT/s to see what that looks like... I feel like these new AGESA builds are better for CPU performance but mem OC seems handicapped

Not to mention big throttling on L3 in AIDA64 (and prolly outside of it in some way)... Testing tighter timing set now, we'll see if it survives OCCT's Memory test following TM5's work completing










Howdy! That worked!


----------



## TimeDrapery

This is the first build I've done in a while that's in a case 😂😂😂😂😂, I may rearrange my fans to more directly cool the DIMMs rather than rely on the air drawn by the top exhaust fans to pull air past em

Definitely going to add another two Corsair fans on the other side of the rad to get some push / pull going... Just gotta find where my hand tools went off to in the move 😂😂😂😂😂


----------



## TimeDrapery

Veii said:


> Spoiler
> 
> 
> 
> 2nd post (mine) should have cleared up this part
> I mentioned that i'm not against this or hiding anything
> 
> Just that it makes no sense from an usage (comparison) standpoint
> Hence branch prediction is active and will falsify the results the longer you run it
> An low allcore as you wrote, i've mentioned too as a possible ~ probably only, option just to be sure to stay sub 60-62c in any case. As *FIT is not disabled on OC_Mode*
> 
> Soo i haven't denied it, just not delivered yet on this method of testing
> 
> Prochot is the only limiter for me currently active, that ruins my 4.85 on load
> Which is not AVX2 exclusive and happens also in AVX/FMA title
> THM at 94 doesn't bypass it ~ and it keeps consistently ruining the boost
> I've wrote about it with exact same shown test on LinX ~ and around the time when i stopped carrying about this tool , as it was not really comparable.
> (2? months ago, around the time BZ uploaded the tFAW comparison video with his 5950X)
> Same was for SiSandra MATS test. Done it, maybe it was overlooked. But showed that results keep improving the longer & more often you run it.
> 
> Please don't missunderstand (both) that i did ignore them.
> I'm times ago past these testing and don't bother right now. Prioritize other research, as my unit doesn't have WHEA #19 issues to even bother with this.
> Only #18 when i do other stupid things with my cores , hydra and PBO ~ which slightly earns my time now
> Also spend my time on something more fun which is RX Navi XT (XH & C) series, while waiting till zen3D/4D releases finally & Microsoft L3 throttle fix ~ to reinstall
> Long past voltage searching or Vermeer platform support. ~ since my last score end of May
> 
> Only when AMD starts to role out PSP-FW fixes, then maybe WHEA thematic can be taken a look at again.
> Currently it's waiting and waiting. I won't get RSMU access tool as it seems, soo i'm done with this topic. There is just not much to "research and fix" left.
> Only fixing my own 2133 FCLK package throttle ~ then i'd be fully done with this sample and can sell it, or put in a trophy glas.
> But who knows, this already takes 4-5 months. Might as well take 1 more till we get updated bioses
> SPI ROM Armor also needs to be broken, but maybe will never be (lack of time) ~ people should just buy HW-SPI Flasher
> 
> EDIT:
> Already considering selling it or not selling it
> I don't want honestly. It's a rare sample, but Zen3D/4D is more appealing then going against an unfixable issue without AMD doing anything against it
> I lack the tools to fix it, soo why even bother spending more time on it
> 
> They are atm under ADL strain, soo i'm not judging them much.
> They also have other priorities to focus. Navi drivers and their Frequency + VRAM Freq lockdowns ~ already are taking a lot of time
> We start to get driver updates on weekly bases now, instead one in 1-2 months.
> I see AMD does try on many sides, soo they don't deserve my bothering/mocking either
> 
> It will fix itself, when it fixes itself
> Or somebody like Yuri assists the community after being less busy with his projects (multiple)
> As he surely is capable to rewrite Vermeer's ~ *when he wants to bother*.
> *IF even*, as he'd need to burn business bridges, by going against AMD's decision
> ~ for an OCN community that piracy leaked Hydra Alpha or keeps fighting with him about how DDR4 functions and what he's seen by his research, similar how people fight with me against little things that don't much their experiences
> Soo unsure that such is even worth it, for his reputation and development team (assisting in something against AMDs blessing)
> (these people have to eat something after all ~ me too a little bit at least, soo i'm not bothering with a lost cause further/so far ~ till anything actually happens AGESA or RSMU wise)
> 
> EDIT2:
> I think @ManniX-ITA was it
> Here, CO's can function on a 5900X without being package throttled
> Somebody i've still promised to take a look on dual CCDs (5950X & 5900X still aren't delivered yet, neither the better DR kits)
> 
> 
> Spoiler: No CO throttle, but limited at -30 already
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Excuse my poor picture, that's all i got send
> MSI B550 Carbon Wifi
> 
> 
> This goes in combination with CoreCycler - tool for testing Curve Optimizer settings also Asrock X370 Taichi Overclocking Thread with Asrock X370 Taichi Overclocking Thread
> Then Asrock X370 Taichi Overclocking Thread pointing to still valid AMD max overclocking voltage and CoreCycler - tool for testing Curve Optimizer settings
> People keep fighting with me over little things, but beg for help (continuing half post above) then not even try to bookmark little snippets i share , for example here about CO tickery and how it functions
> 
> Well generally, ManniX ~ i think you've complained once about Hydra CO not functioning, i didn't forget that i'm still owing you a result
> I can't say it doesn't function ~ a "bronze" 5900X is capable. When limits are already at -30 , there is no need use fMax extend to further allow frequency stretch and throttle
> 
> 
> 
> 
> 
> 
> 
> 
> Rather stay on lower clock, and be sure it's not throttling at all ~ than push higher boost while consistently have irregular inaccurate results as boosting system keeps throttling in "fixed random matter"
> 
> If people can't get their CPUs to behave correctly , what sense does it even make to compare results , when everything is dynamic 🤭
> This includes Aida64 L3 cache for example and the complains against Microsoft ~ while they are right, still.
> Review media claims performance results. People follow this and mention that our Bronze/silver samples are a 0.001% silicon lottery win. Funny 😅
> Overclocker here should have given their best , and at least not judge that harshly against their own team. Judge review media for doing a poor job, but don't mock people who spend their time free here without any benefits except public global good (improving AMD research further)



@Veii

Ok, this seems like it's not nearly as big as issue on my 5800X (although I'm still working the curve offsets on that one as I'm never quite happy / stable enough to let it lie) but throttling on this 5600X is *terrible*... What can I do to lessen it so I can move on to pushing my memory OC? So far I've:

• configured my BIOS based off what seems, to me, to be the consensus here...
• Typical Current Idle
• APBDIS 1 with PState 0
• DF C-States disabled
• C-States / Preferred Cores enabled
• Auto voltages / "High" VCORE LLC and "Turbo" VSOC LLC
• Motherboard limits
• 10× PBO Scalar
• Per-core CO offsets as follows:
• Core 0 (123): - 5
• Core 1 (123): - 26
• Core 2 (123): - 16
• Core 3 (123): - 23
• Core 4 (123): - 3
• Core 5 (123): - 28
• I've stability tested using the following:
• OCCT Pro CPU test:
• Large dataset
• Extreme
• Variable
• AVX / SSE
• 3s / 5s (switch active cores runtimes [1t / ⁿt])
• 3h runtime
• CoreCycler (defaults and "All", just SSE) for upwards of one billion hours

I'm doing CPU stability testing with memory at defaults, not even XMP so as to rule it out


----------



## TimeDrapery




----------



## PJVol

TimeDrapery said:


> but throttling on this 5600X


If under "throttling" you mean low allcore clocks in tm5 (if it was tm5 running) then it's not surprising at all given the VDD_CPU supplied according to HWInfo. Something is messed with your settings (or really bad or low SIDD sample).
It's gonna look something like this:


----------



## Audioboxer

New AMD chipset drivers, doubt they do much for memory but if you're on Windows 11 probably worth upgrading MSI MEG B550 UNIFY X Motherboard 

Link above might lead to my mobo (B550 Unify X) but chipset download is universal. Version 3.10.22.706.

Or I believe this is the direct link https://download.msi.com/dvr_exe/mb/amd_chipset_drivers_am4_wt.zip


----------



## mongoled

@PuffyArgos
Have you tried the previous suggestions re tRAS ??

Waiting for you to report back with your latest findings





Dodgexander said:


> @mongoled if I can write the rule correctly this time I believe procODT being high has a similar effect to vDIMM being high. Reading veils advice he says it's best to find lowest procODT to keep signal clean and raise voltage than it is to have lower vDIMM and raise procODT.
> To use a loose example, some people have set procODT to 60 ohms and vDIMM 1.5v This high the electricity circulating the ram could be more dangerous than say 34.3 ohms and 1.65v.
> So the limits of voltage widely talked about with ram is highly related to procODT also. Higher procODT the stronger the current, which is why it can be just, if not more dangerous then voltage.
> 
> And to further ramble on it's actually high current in electricity that makes getting an electric shock more dangerous. You can get shocked with a very high voltage and low current and survive. But you can get shocked by a high current and low voltage and die.


Cheers bud, got it loud and clear

thanks for the write up

 

@TimeDrapery
Bud



just tell us what you are aiming for

 

This config just knocked out a 3+ hrs Y-Cruncher, its still going, hopefully it will survive a reboot

😂 😂


----------



## TimeDrapery

PJVol said:


> Spoiler
> 
> 
> 
> If under "throttling" you mean low allcore clocks in tm5 (if it was tm5 running) then it's not surprising at all given the VDD_CPU supplied according to HWInfo. Something is messed with your settings (or really bad or low SIDD sample).
> It's gonna look something like this:



@PJVol

No, I meant it's throttling when the L3 cache is tested using AIDA64... Likely the fix is the same as what you've posted, although you circled "VCORE" not any VID I imagine I just need to work the curve offsets to get where you're at...?

@Audioboxer

Thanks, I updated Windows 11 and my chipset drivers before starting in on all this... For what it's worth, I hadn't considered that this might be "fixed" behavior 😂😂😂😂😂... Good job AMD / MS

@mongoled

I'm not sure... Of course

I think I'd like to have a good, solid 1T profile for everyday usage and a 2T profile for pushing FCLK... I know the thread's got all the info I need for both but I'm really interested to hear how others have reduced throttling on L3 cache as best they can with PBO

Did your latest survive reboot? 😁😁😁😁😁


----------



## mongoled

TimeDrapery said:


> I'm not sure... Of course
> 
> I think I'd like to have a good, solid 1T profile for everyday usage and a 2T profile for pushing FCLK... I know the thread's got all the info I need for both but I'm really interested to hear how others have reduced throttling on L3 cache as best they can with PBO
> 
> Did your latest survive reboot? 😁😁😁😁😁


Can you post an AIDA on what you are getting ?

Using EDC set to 500, with similar config as you I have saved









Just doing a TM5 on top of the Y-Cruncher, will then reboot and we will see


----------



## Mechan0

I don't know if anyone else has much experience with Dual Rank CJR but I feel like I'm out of my depth at this point to push this kit further. GDM off 1T seems to be an insurmountable barrier, 60 addrcmdstr lets me boot, 55 does not but it also errors about a minute into TM5. I've tried messing around with drive strengths but I feel I just be missing something or am so far away from stable none of it helps enough. This is my last stable config but if anyone has suggestions for timings, pushing fabric, GDM off I'm all ears.
EDIT: This is 1.4V VDIMM btw


----------



## TimeDrapery

@mongoled

Yessir! Lemme search through these last few screens I shot!

Here we go, this is illustrative of the L3 cache throttling










I've never tried to set curve offsets using "All-core" before... I wonder if that could help...?


----------



## ocisdead

TimeDrapery said:


> I'll tell you what's frustrating... Running OCCT's Memory test for a period of one hour and having it crash as soon as it completes testing because the many iterations of the CPU test / CoreCycler weren't sufficient to reveal Core 0's instability at a -7 CO offset... -5 is stable 😂😂😂😂😂


I was also a OCCT memory test fan for a while but It let me down recently. Timings that could pass a full hour of OCCT memtest would error out almost instantly in y-cruncher and this was absolutely timing related as loosening something i set too tight allowed y-cruncher to pass properly. I usually just run the last five tests.


----------



## PJVol

TimeDrapery said:


> Likely the fix is the same as what you've posted


nvm, that was related to PBO2 tuning.
Just didn't realise it's about kabbalistic experiments you doing )


TimeDrapery said:


> Here we go, this is illustrative of the L3 cache throttling


So, how is this illustrative and what you define as "L3 cache throttling" ?


----------



## sonixmon

nick name said:


> Holy cow. While it didn't work for the other person it seems to be working for me. Previously I would get an instant BSOD when starting Karhu at 1T and GDM off, but now it seems very promising.
> 
> How did you learn about using AddrCmdSetup set to 56? And why does this seem to work?
> 
> View attachment 2530907
> 
> 
> Edit:
> 
> Very, very promising.
> 
> View attachment 2530908


Sorry I was out of town a few days. I learned that trick on these forums from someone smarter than me . Also didnt know excatly what it did other than adjust timings slightly so it was cool to see the video that talked about it.

I basically did some testing, I made the best profiles I could (lowest timings etc.) one @ 2T, one @1T GDM On and then made the best 1T with setup 56. I found the best overall performance was 1T with setup 56 so that's what I stuck with.


----------



## TimeDrapery

Spoiler






PJVol said:


> nvm, that was related to PBO2 tuning.
> Just didn't realise it's about kabbalistic experiments you doing )
> 
> So, how is this illustrative and what you define as "L3 cache throttling" ?






@PJVol

Ah, good question... I suppose this could simply be what the CPU wants to do and is normal behavior however I know that a frequency of 4850MHz should produce greater bandwidth and lesser latency for L3 cache so I presume it's throttling due to too high of a VID

Again, that's me being presumptuous and I'm open to the prospect that (for whatever reason) my individual CPU is crap tier but I'm hoping it's not the case!

When I get home tonight I'll set an all-core OC just to eliminate PBO things from the equation and see what measures I get from AIDA64

You think it looks as it should?

I feel like the lesser VID you posted is indicative of what I need to shoot for to hold 4850MHz in TM5 and to correct throttling


----------



## Luggage

TimeDrapery said:


> @PJVol
> 
> Ah, good question... I suppose this could simply be what the CPU wants to do and is normal behavior however I know that a frequency of 4850MHz should produce greater bandwidth and lesser latency for L3 cache so I presume it's throttling due to too high of a VID
> 
> Again, that's me being presumptuous and I'm open to the prospect that (for whatever reason) my individual CPU is crap tier but I'm hoping it's not the case!
> 
> When I get home tonight I'll set an all-core OC just to eliminate PBO things from the equation and see what measures I get from AIDA64
> 
> You think it looks as it should?
> 
> I feel like the lesser VID you posted is indicative of what I need to shoot for to hold 4850MHz in TM5 and to correct throttling


You have tried EDC at 250++ and using TDC as limit?

edit: my old testing from veii discussion.


http://imgur.com/a/tD7HmIm


----------



## PJVol

TimeDrapery said:


> I feel like the lesser VID you posted is indicative of what I need to shoot for to hold 4850MHz in TM5 and to correct throttling


Dude! Why I have a feeling that now there's one more forum member whose posts need to be deciphered? 
------------------------------------
Seriously, it'd be nice, if you set L3 cache things aside or at least try to explain why is it so important for you.
And using the term "throttling" where its not implied to, won't do any help to these discussions.
Anyway, I'm open to help if you dare to proceed.



TimeDrapery said:


> You think it looks as it should?


If you provide the screen just with tm5 running alone with sensors open, it'd help.


----------



## PJVol

Veii said:


> I won't get RSMU access tool as it seems, soo i'm done with this topic


Im not sure, did you meant some specific tool here, but the "tool" )) that you shared here (from asus or whoever else) is very useful and powerful if some precautions were taken.

And 1st window is AFAIK RSMU mailbox.


----------



## TimeDrapery

PJVol said:


> Spoiler
> 
> 
> 
> Dude! Why I have a feeling that now there's one more forum member whose posts need to be deciphered?
> ------------------------------------
> Seriously, it'd be nice, if you set L3 cache things aside or at least try to explain why is it so important for you.
> And using the term "throttling" where its not implied to, won't do any help to these discussions.
> Anyway, I'm open to help if you dare to proceed.
> 
> 
> If you provide the screen just with tm5 running alone with sensors open, it'd help.



@PJVol

Well I think you feel like that because it's the case at hand 😂😂😂😂😂

I will post the screen you're describing once I'm home tonight!

I use the term throttling because it appears to me that the CPU throttles once it attempts to measure L3 cache bandwidth and latency... If this is a matter wherein I'm referring to the behavior I'm observing inaccurately then I'm happy to change up my wording

Would you be able to tell me why it's not an issue of throttling? If I lift limits using the "Tool" it no longer occurs... To me this indicates the CPU detects one more limits being met during operating and then it ... throttles 😂😂😂😂😂

Please, also share with us what you're referring to with regards to setting curve offsets in real-time

@Luggage 

Thanks for the tip! Looks like you've got it pretty well sorted, I'll definitely try going with TDC limiting as a way forward!


----------



## MrHoof

TimeDrapery said:


> @Luggage
> 
> Thanks for the tip! Looks like you've got it pretty well sorted, I'll definitely try going with TDC limiting as a way forward!


My u12a can handle up to 115 TDC, if it actually hits its it its close to 90°C. Just keep the cooling solution for this one in mind.


----------



## Audioboxer

TimeDrapery said:


> @PJVol
> 
> No, I meant it's throttling when the L3 cache is tested using AIDA64... Likely the fix is the same as what you've posted, although you circled "VCORE" not any VID I imagine I just need to work the curve offsets to get where you're at...?
> 
> @Audioboxer
> 
> Thanks, I updated Windows 11 and my chipset drivers before starting in on all this... For what it's worth, I hadn't considered that this might be "fixed" behavior 😂😂😂😂😂... Good job AMD / MS
> 
> @mongoled
> 
> I'm not sure... Of course
> 
> I think I'd like to have a good, solid 1T profile for everyday usage and a 2T profile for pushing FCLK... I know the thread's got all the info I need for both but I'm really interested to hear how others have reduced throttling on L3 cache as best they can with PBO
> 
> Did your latest survive reboot? 😁😁😁😁😁


The first Windows 11 chipset drivers were supposed to fix core priority issues. These ones are something to do with tweaking power plans as far as I can tell. So, hopefully more bug fixes or more performance.

It's probably still MS fault 🤣 Windows 11 was soo rushed, but it's getting there now in terms of performance. L3 cache still needs a bit more work IMO.

I went back to Windows 10 briefly but then restored my Windows 11 clone. Not going to lie, with StartAllBack to fix the task bar I kind of prioritised graphics/UI over performance. I just like the feel of Windows 11 lmao. But thankfully performance IS getting there now.


----------



## Luggage

MrHoof said:


> My u12a can handle up to 115 TDC, if it actually hits its it its close to 90°C. Just keep the cooling solution for this one in mind.


Stock is 95, creep up from that as cooling allows. Mine is over kill so if I raise all limits until they no longer throttle I end up at around 195 - 128 - 168, if I set EDC sky high I can't get EDC(edit) TDC to climb over 116-117. These limits interact strangely - especially around usage/optimize maximums. And the hidden FIT limits act even stranger in my un-educated mind. Still have no idea how the PPT and CCA limiters in zen/vermeer monitor really act.

And pet pewee is that sc, mc and mem-latency likes different setting =(


----------



## TimeDrapery

Audioboxer said:


> Spoiler
> 
> 
> 
> The first Windows 11 chipset drivers were supposed to fix core priority issues. These ones are something to do with tweaking power plans as far as I can tell. So, hopefully more bug fixes or more performance.
> 
> It's probably still MS fault 🤣 Windows 11 was soo rushed, but it's getting there now in terms of performance. L3 cache still needs a bit more work IMO.
> 
> I went back to Windows 10 briefly but then restored my Windows 11 clone. Not going to lie, with StartAllBack to fix the task bar I kind of prioritised graphics/UI over performance. I just like the feel of Windows 11 lmao. But thankfully performance IS getting there now.



@Audioboxer 

😂😂😂😂😂, figures as much... All I saw change was processor minimum to 100% and short running threads set to prefer performant processors 😂😂😂😂😂

@MrHoof 

I will! Thanks for the tip!


----------



## kim nk

Hello ..
In trcdrd 13, when the lowest tfaw timing value is lowered to 32 or less, a tm5 error occurs. Please help if you have a solution for this. I want to achieve tfaw16
















The rest of the timing trdwr , twrrd , etc. have been released in part.


----------



## Spectre73

After giving up on 1900 FCLK stability because of WHEA 19 I want to settle at 3600 with tight timings. I am down to this:









This fails Karhu test at 16k. Any idea what to dial down to stabilize this 24/7?


----------



## paih85

Spectre73 said:


> After giving up on 1900 FCLK stability because of WHEA 19 I want to settle at 3600 with tight timings. I am down to this:
> View attachment 2531392
> 
> 
> This fails Karhu test at 16k. Any idea what to dial down to stabilize this 24/7?


try my old setting. i hope this will help. 👌


----------



## Spectre73

paih85 said:


> try my old setting. i hope this will help. 👌
> 
> View attachment 2531394


I can't see how tightening up everything further will help me here? Your tRDRDSD and tWRWRSD is looser and you have differend procODT as well as DrvStr settings so maybe I will try this. Other than that, I fear I will only make it worse. I suppose the setup timings are for 1T GDM off, so probably of no help for me. Thank you nonetheless.


----------



## PuffyArgos

@mongoled thanks for checking up on me. I went quiet for a bit as it has taken an inordinate amount of time testing this kit (not used to the time for 32gig kits!).

Here is where I am now:


Spoiler: 5950x on Gigabyte B550 Pro V2 with GS 32g 3600c14 kit at 3600c14















Before moving up to 1900 I want to try to tighten the timings up a bit. My first thoughts are to get the SCLs to 2 and possibly tWTRS to 4 (although my BIOS won't let me set tWR lower than 10 so I'm not sure that this will improve performance).

If you see anything I've missed please do not hesitate to let me know. I will let you know how I get on with tightening timings before I start moving to higher freqs.

I appreciate you time and thoughts.


----------



## PuffyArgos

@Spectre73 


Spoiler: OP






Spectre73 said:


> After giving up on 1900 FCLK stability because of WHEA 19 I want to settle at 3600 with tight timings. I am down to this:
> View attachment 2531392
> 
> 
> This fails Karhu test at 16k. Any idea what to dial down to stabilize this 24/7?






I have a similar kit I am working on right now. Here's where I'm at:



Spoiler: 32g 3600c14















It was a long road to get here. Consider the following:

tWR = tRRDS + tWTRS
I could boot tWTRS < 6, but moving it up to match the above rule helped stabilize my kit.

tRTP = tWR/2

tRAS = tRCD + tWR + tBL (4)
I know the is dated, but it also matches tRAS = tCL + tRCD
If you're going to run flat 14s with tWR at 10 tRAS should be 28. If you slow down tWTRS and run tWR at 12 then tRAS should be 30.

tRP = TRCDWR + tCWL + tBL + tWR
tRP = 14 + 14 + 4 + 10 (or 12) = 42 (or 44)
With tWR at 10 this also matches tRP = tRAS + tRP

tRFC = 6 * tRP

At 1800, tCKE should be 6 or 7.
If you move to 1900 it should be 9.

With GDM off, I also had to run ClkDrvStr at 40 or 60 to avoid IMC errors until I used the setup times of 56. The setup times allowed me to drop ClkDrvStr down to 30 while leaving GDM off. This is absolutely key to ever getting to 1900 as your kit will overheat with ClkDrvStr at 60 with more than 1.5V.

Lastly, my kit's XMP profile is 1.45V. To tighten the timings like I did, I gave it a bit more at 1.48V.

I'm working on my timings a bit more and then working on 1900. I'll let you know how I get on as it may be helpful to you.


----------



## mongoled

TimeDrapery said:


> @mongoled
> 
> Yessir! Lemme search through these last few screens I shot!
> 
> Here we go, this is illustrative of the L3 cache throttling
> 
> View attachment 2531346
> 
> 
> I've never tried to set curve offsets using "All-core" before... I wonder if that could help...?


Oh,

didnt see you were using Windows 11!

As others have chimed in, you need to experiment with EDC/TDC limits, though from what ive seen the Windows 11 results are lagging Windows 10 results slightly ...

No, Y-Cruncher did not pass after a reboot.



Looks like I may have to abandon this 4067/2033 profile also as im not finding a combination to keep Y-Cruncher happy across reboots....


PuffyArgos said:


> @mongoled thanks for checking up on me. I went quiet for a bit as it has taken an inordinate amount of time testing this kit (not used to the time for 32gig kits!).
> 
> Here is where I am now:
> 
> 
> Spoiler: 5950x on Gigabyte B550 Pro V2 with GS 32g 3600c14 kit at 3600c14
> 
> 
> 
> 
> View attachment 2531396
> 
> 
> 
> 
> Before moving up to 1900 I want to try to tighten the timings up a bit. My first thoughts are to get the SCLs to 2 and possibly tWTRS to 4 (although my BIOS won't let me set tWR lower than 10 so I'm not sure that this will improve performance).
> 
> If you see anything I've missed please do not hesitate to let me know. I will let you know how I get on with tightening timings before I start moving to higher freqs.
> 
> I appreciate you time and thoughts.


Are you running a static CPU clock (4.0 Ghz) ?

Regarding your settings, they are where I would expect them to be.


----------



## ManniX-ITA

Veii said:


> Well generally, ManniX ~ i think you've complained once about Hydra CO not functioning, i didn't forget that i'm still owing you a result


I was more rambling that it looks not very efficient, took ages and didn't get a good CO table (maybe cause my 2nd CCD is much worse than the 1st).

Also the results are much worse than what CTR would do in Auto.
But with a lot of manual tweaking seems to work.
Anyway in the next weeks I'll move to the wc build and I'll test it a little bit more!


----------



## PuffyArgos

mongoled said:


> Oh,
> 
> didnt see you were using Windows 11!
> 
> As others have chimed in, you need to experiment with EDC/TDC limits, though from what ive seen the Windows 11 results are lagging Windows 10 results slightly ...
> 
> No, Y-Cruncher did not pass after a reboot.
> 
> 
> 
> Looks like I may have to abandon this 4067/2033 profile also as im not finding a combination to keep Y-Cruncher happy across reboots....
> 
> Are you running a static CPU clock (4.0 Ghz) ?
> 
> Regarding your settings, they are where I would expect them to be.


I was able to tighten timings down a bit and shed a ton of voltage on the SOC and resistance off the CAD bus. I will post an update for Spectre in about 2 hours time if you're interested in where I've gotten with it.

I am running a static CPU clock. My rigs are running multi-threaded workloads 24/7. I like to keep the rad fans at 60% with a max TDieAve of 65C at 20C ambient. Static clocks are the best way for me to squeeze every last hz from my voltage settings to meet these criteria. The 5950x is so new I haven't spent any time on the CPU clock. I just stuck it at 40 and gave it a safe voltage so I could rule out CPU for any stability issues while testing and pushing RAM.

So far I am underwhelmed by the DR kit. I'm not used to gigabyte BIOS, but I believe interleaving is on by default. If it is, the algorithm I'm running receives no performance gain from interleaving. My 1800 SR rig hashes at the same rate as my 1800 DR rig with the same CPU clock. As such, the DR kit is likely to become a Christmas present to my nephew and I have a set of F4-4800C17D-16GTRS arriving tomorrow.

The new kit has an XMP profile of 4800MT/s 17-19-19-19-39 at 1.6v. I'm looking forward to seeing how low I can get those primaries at 4200, 4000, and 3800 running that voltage. That said, I have always been a bit mystified about how the RTTs fit into the voltage equation. I know Veii discouraged me from running RTTPark at RZQ/5 with greater than 1.55 volts. I had planned to peek at the XMP settings to see how they run the RTTs at 1.6v, but I'm afraid it will be decided by the board and set to something ridiculously stupid. Would you be able to shed a bit of light on this for me?


----------



## nick name

PuffyArgos said:


> I was able to tighten timings down a bit and shed a ton of voltage on the SOC and resistance off the CAD bus. I will post an update for Spectre in about 2 hours time if you're interested in where I've gotten with it.
> 
> I am running a static CPU clock. My rigs are running multi-threaded workloads 24/7. I like to keep the rad fans at 60% with a max TDieAve of 65C at 20C ambient. Static clocks are the best way for me to squeeze every last hz from my voltage settings to meet these criteria. The 5950x is so new I haven't spent any time on the CPU clock. I just stuck it at 40 and gave it a safe voltage so I could rule out CPU for any stability issues while testing and pushing RAM.
> 
> So far I am underwhelmed by the DR kit. I'm not used to gigabyte BIOS, but I believe interleaving is on by default. If it is, the algorithm I'm running receives no performance gain from interleaving. My 1800 SR rig hashes at the same rate as my 1800 DR rig with the same CPU clock. As such, the DR kit is likely to become a Christmas present to my nephew and I have a set of F4-4800C17D-16GTRS arriving tomorrow.
> 
> The new kit has an XMP profile of 4800MT/s 17-19-19-19-39 at 1.6v. I'm looking forward to seeing how low I can get those primaries at 4200, 4000, and 3800 running that voltage. That said, I have always been a bit mystified about how the RTTs fit into the voltage equation. I know Veii discouraged me from running RTTPark at RZQ/5 with greater than 1.55 volts. I had planned to peek at the XMP settings to see how they run the RTTs at 1.6v, but I'm afraid it will be decided by the board and set to something ridiculously stupid. Would you be able to shed a bit of light on this for me?


Can I ask why you don't run the 5950X in the ASUS board?


----------



## PuffyArgos

nick name said:


> Can I ask why you don't run the 5950X in the ASUS board?


The only reason I bought the B550 board was because I watched a buildzoid motherboard roundup and he mentioned that the the memory topology in the B550 Aorus Pro V2 was better than even the topology of the x570i (and interestingly even pointed to the Asus board). This aligns with my experience as well. With the same CPU and RAM kit in each rig the B550 easily gets 1900 whereas after 18 months I still haven't gotten the Asus to post at 1900 with flat 14s.

It might not be the board. It could be a worse bin for either the RAM or the CPU, but until recently it was jammed into an NCase M1 and way too much of a pain to swap out CPU or RAM to test.


----------



## mongoled

PuffyArgos said:


> I was able to tighten timings down a bit and shed a ton of voltage on the SOC and resistance off the CAD bus. I will post an update for Spectre in about 2 hours time if you're interested in where I've gotten with it.
> 
> I am running a static CPU clock. My rigs are running multi-threaded workloads 24/7. I like to keep the rad fans at 60% with a max TDieAve of 65C at 20C ambient. Static clocks are the best way for me to squeeze every last hz from my voltage settings to meet these criteria. The 5950x is so new I haven't spent any time on the CPU clock. I just stuck it at 40 and gave it a safe voltage so I could rule out CPU for any stability issues while testing and pushing RAM.
> 
> So far I am underwhelmed by the DR kit. I'm not used to gigabyte BIOS, but I believe interleaving is on by default. If it is, the algorithm I'm running receives no performance gain from interleaving. My 1800 SR rig hashes at the same rate as my 1800 DR rig with the same CPU clock. As such, the DR kit is likely to become a Christmas present to my nephew and I have a set of F4-4800C17D-16GTRS arriving tomorrow.
> 
> The new kit has an XMP profile of 4800MT/s 17-19-19-19-39 at 1.6v. I'm looking forward to seeing how low I can get those primaries at 4200, 4000, and 3800 running that voltage. That said, I have always been a bit mystified about how the RTTs fit into the voltage equation. I know Veii discouraged me from running RTTPark at RZQ/5 with greater than 1.55 volts. I had planned to peek at the XMP settings to see how they run the RTTs at 1.6v, but I'm afraid it will be decided by the board and set to something ridiculously stupid. Would you be able to shed a bit of light on this for me?


OK, that makes sense now looking at your L3 cache results....

Regarding the F4-4800C17D-16GTRS and your comments, have you tested your CPU is able to post with FCLK higher than 1900 ??

As im sure you are aware its best to keep the IF clock in a 1:1 ratio, 1900 mhz seems to be the maximum most people can achive 24/7 stability.

Regards RTTs, you need to play with the dimms as RTT settings are very "personal" i.e. they are dimm/platform dependent.

Veii advice is good, but that advice is dependent on the PCB being used so you are going to have to find out what the PCB is.

I have not played with DR modules so im not in a position to offer advice based on experience.

Regards you SR dimms were you running 4 modules ?

If so that could be the reason you are seeing no difference between your DR dimms .....


----------



## PuffyArgos

Spectre73 said:


> I can't see how tightening up everything further will help me here? Your tRDRDSD and tWRWRSD is looser and you have differend procODT as well as DrvStr settings so maybe I will try this. Other than that, I fear I will only make it worse. I suppose the setup timings are for 1T GDM off, so probably of no help for me. Thank you nonetheless.





Spoiler: F4-3600C14-16GTZN Before

















Spoiler: F4-3600C14-16GTZN After














Quick summary of the changes:

Shed heat, dropped voltages and resistances
1. Dropped SOC down to 1000 mV, VDDG down to 950/950 mV
2. Dropped all CAD Bus resistances to 20 ohms 
3. Dropped ProcODT down to 30 ohms

Dropped primaries
4. tRAS from 28 to 26
5. tRC from 42 to 40
Note: not sure why this worked as my blk value should be greater than 2 and I haven't actually set tWR to 8. But it works.

Tightened timings
6. tRRDL from 6 to 4
7. tWRTS from 6 to 4
Note: this should indicate that I could attempt tWR of 8 (tWRS = tWRTS + tRRDS), but my BIOS doesn't allow a setting that low. May attempt hex edit in the future.
8. tRFC from 252 to 240
9. SCLs from 4 to 2

Anyway, both of these run stable and should form a good basis for you which you can work on your kit to keep 1T and GDM off.


----------



## domdtxdissar

All the intel guys seems to prefer to use memtestpro with the "runmemtestpro-script" so i thought i could give it a spin, but i can't get it to work properly..

Memtestpro by itself are working fine:







But when i try to run with the "runmemtestpro-script" it don't get any progress. Seems like it cant read the hardware stats either (?)







Script should look something like this when running:







Does anyone know if runmemtestpro don't support this Zen3 platform ?


----------



## KedarWolf

domdtxdissar said:


> All the intel guys seems to prefer to use memtestpro with the "runmemtestpro-script" so i thought i could give it a spin, but i can't get it work properly..
> 
> Memtestpro by itself are working fine:
> View attachment 2531567
> 
> But when i try to run with the "runmemtestpro-script" it don't get any progress. Seems like it cant read the hardware stats either (?)
> View attachment 2531568
> 
> Script should look something like this when running:
> View attachment 2531570
> 
> Does anyone know if runmemtestpro don't support this Zen3 platform ?


The Ryzen DRAM Calculator uses MemTest, download it, use the Test Ram option set the maximum % you want, let it run.


----------



## domdtxdissar

Some Milan-X (Zen3 V-Cache) memory news from Microsoft Azure



> We can report that as compared to the current, generally available HBv3 VMs with standard EPYC 3rd Gen “Milan” processors, these enhanced VMs provide:
> 
> Up to 80% higher performance for CFD workloads
> Up to 60% higher performance for EDA RTL simulation workloads
> Up to 50% higher performance for explicit finite element analysis workloads
> In addition, HBv3 VMs with Milan-X processors show significant improvements in workload scaling efficiency, peaking as high as 200% and staying sublinear across a broad range of workloads and models.













> Above in Figure 1, we share the results of running Intel Memory Latency Checker (MLC), a tool for measuring memory latencies and bandwidths. MLC outputs measured latencies in nanoseconds. On the right in Figure 1 is the output of the latency test running on a HBv3-series VM with a Milan CPU (EPYC 7V13) whereas on the left is the output of the same test but run against a HBv3-series VM enhanced with a Milan-X CPU (EPYC 7V73X).
> 
> Using this test, we measure best case latencies (shortest path) improving by 51% and worst case latencies (longest path) improving by 42%. For historical context, these are some of the largest relative improvements for memory latencies in more than a decade when memory controllers moved onto CPU packages.
> 
> It is important to note that the results measured here do not mean that Milan-X is improving the latency of DRAM accesses. Rather, the larger caches are causing the cache hit rate of the test to go up, which in turn produces a blend of L3 and DRAM latencies that, taken together, produce a better *real-world effective* results than would occur with a smaller amount of L3 cache.














> For memory bandwidth, the story is similar and similarly nuanced. We ran the industry standard STREAM benchmark run with typical settings. Specifically, this benchmark was run using the following:
> 
> 
> 
> ./stream_instrumented 400000000 0 $(seq 0 4 29) $(seq 30 4 59) $(seq 60 4 89) $(seq 90 4 119)
> 
> 
> 
> This returned a result of ~358 GB/s for STREAM-TRIAD:
> Note that the results above show measured bandwidths essentially identical to those measured from a standard 2-socket server with Milan processors using 3200 MT/s DIMMs in a 1 DIMM per channel configuration, such as HBv3-series with standard Milan CPUs. Note also that that problem test size run as part of the STREAM test (the 400000000 cited above) is much larger than can fit in caches. Hence, it effectively becomes a test of DRAM performance, specifically. This result is not surprising, as there is no difference in the physical DIMMs in these servers nor their ability to communicate with the CPUs memory controllers.
> 
> However, as seen below in measured performance of highly memory bandwidth limited apps with a reasonably large percentage of the active dataset fitting into the large L3 caches, the Azure HPC team is measuring performance uplifts of up to 80% as compared to such a reference Milan 2-socket server. Thus, it can be said that the amplification effect from the large L3 caches *up to 1.8x for effective memory bandwidth*, because the workload is performing as if it were being fed more like ~630 GB/s of bandwidth from DRAM.
Click to expand...









Some worst case compute-oriented benchmarks show only ~2% gains from all the cache, but as has been said time and time again, if your workload isn't memory bound, you're not going to get a significant performance boost.

The good news is most non-3D rendering consumer workloads happen to be memory bound. Some are bound by latency, some are bound by memory bandwidth.
Crossing my fingers that AMD can live up the +15% performance increase in games


----------



## blodflekk

my tRDWR is defaulting to 18 and I can't boot with anything less than 10, anything I should look at to remedy this? Everyone seems capable of hitting tRDWR = 8. I'm running teamgroup b die 3600 CL14 vdimm 1.45 SoC 1.1


----------



## Mach3.2

I think I'm done with the teamgroup 3200 cl14 kits, the 2nd set can't post 3733 15-16-16 1.52V vDIMM at 1T with 56-56-56 setup timing. The EZ debug LEDs on my mobo don't come on when I tried to POST cl15. 

2T 3733 16-16-16 POST just fine though, but I'm not gonna bother with memtesting those sticks since I already ordered a set of G.skill 3600 14-15-15 from newegg, hopefully those are better.

TL; DR avoid the teamgroup 3200 cl14 bin, you pay for what you get.


----------



## Audioboxer

blodflekk said:


> my tRDWR is defaulting to 18 and I can't boot with anything less than 10, anything I should look at to remedy this? Everyone seems capable of hitting tRDWR = 8. I'm running teamgroup b die 3600 CL14 vdimm 1.45 SoC 1.1


What is your tCWL set to?



Mach3.2 said:


> I think I'm done with the teamgroup 3200 cl14 kits, the 2nd set can't post 3733 15-16-16 1.52V vDIMM at 1T with 56-56-56 setup timing. The EZ debug LEDs on my mobo don't come on when I tried to POST cl15.
> 
> 2T 3733 16-16-16 POST just fine though, but I'm not gonna bother with memtesting those sticks since I already ordered a set of G.skill 3600 14-15-15 from newegg, hopefully those are better.
> 
> TL; DR avoid the teamgroup 3200 cl14 bin, you pay for what you get.


Is the 3600 14-14-14-14 set still costing more?


----------



## blodflekk

Audioboxer said:


> What is your tCWL set to?
> 
> 
> 
> tCWL is set to 14


----------



## Mach3.2

Audioboxer said:


> Is the 3600 14-14-14-14 set still costing more?


Yup the flat 14 bin is being sold at 304USD but I managed to get the 14-15-15 bin at 239USD since it was on sale. The 14-15-15 bin is currently being sold at 279USD.


----------



## XPEHOPE3

TimeDrapery said:


> It's nice that it'll hold 4850MHz under OCCT's AVX2 load


What's nice is that your F14c Gigabyte BIOS doesn't suffer from VDDG stuck at 1V bug!


TimeDrapery said:


> • Motherboard limits
> • 10× PBO Scalar


If it's L3 cache throttle you are talking, then it's Win 11 and motherboard limits to blame. If it's lower clocks then try setting PBO scalar to e.g. 5 otherwise you'll be limited by voltage.


domdtxdissar said:


> But when i try to run with the "runmemtestpro-script" it don't get any progress. Seems like it cant read the hardware stats either (?)


Did you try running the script w/o HWiNFO?


----------



## domdtxdissar

XPEHOPE3 said:


> Did you try running the script w/o HWiNFO?


Yeah same problem with hwinfo closed, simply don't think runmemtestpro support the amd platform.


----------



## Audioboxer

XPEHOPE3 said:


> What's nice is that your F14c Gigabyte BIOS doesn't suffer from VDDG stuck at 1V bug!
> If it's L3 cache throttle you are talking, then it's Win 11 and motherboard limits to blame. If it's lower clocks then try setting PBO scalar to e.g. 5 otherwise you'll be limited by voltage.
> Did you try running the script w/o HWiNFO?


I _think_ 14c is still AGESA 1.2.0.3. 14e is the switch to AGESA 1.2.0.4.


----------



## KedarWolf

domdtxdissar said:


> Yeah same problem with hwinfo closed, simply don't think runmemtestpro support the amd platform.


MemTestPro works with AMD. I have scripts that work with Version 7.0. I'll share them when I get home from work.

If you don't have 7.0 and bought it within the last year, email their supports and they'll send you the new version.

If you bought it more than a year ago, it only cost 5 USD to get the latest version.

The scripts WON'T work with older versions.


----------



## PuffyArgos

nick name said:


> Can I ask why you don't run the 5950X in the ASUS board?


So I took your implication that the 5950x should probably get the 'better' of my equipment. I've picked up an ASRock B550 itx/ax board to pair with the 5950x and put it in the chassis with the custom loop running an NexXxos Monsta 360mm with 6 Noctua NF-A12s in push/pull. I've also dropped in the new F4-4800C17D-16GTRS kit. Haven't had time to tune anything though.

Would have never picked up the new board or done the swapping had you not asked the question, it's much appreciated.


----------



## Audioboxer

I hadn't actually ran Karhu for longer than 2 hours, so, just for prosperity, here's the 10000%. I read around 10000% is a fairly accepted "fully stable" Karhu coverage to aim for.

Pretty much done with memory now, just hoping either new AGESA can help FCLK or worst comes to the worst it's an upgrade to the AMD 3D cache chips so that 4000 memory can actually be used as... 4000 memory.

Cba changing to intel at the moment and DDR5 memory looks like a total rip off until it matures a bit. If you've got money to burn, IMO, you'd be best dumping it into the highest tier DDR4 bins for another year or two.


----------



## Thanh Nguyen

3d v cache uses the same socket or need a new mobo?


----------



## KedarWolf

domdtxdissar said:


> Yeah same problem with hwinfo closed, simply don't think runmemtestpro support the amd platform.


Put the scripts in the same folder and your MemTestPro 7.0 MTPclassic.exe.

Rename the attachment and remove the .txt.


----------



## TimeDrapery

AHHHHH

Why is CoreCycler running Kagari absolutely destroying my ****ing curve?!? 😂😂😂😂😂

In a matter of a day of testing it dropped from Auto / Huge / SSE P95 "stable" at a bunch of stupid offsets that obviously weren't stable to a bunch of offsets that I'm too ashamed of to share 😂😂😂😂😂

I'm not actually asking a question here, I'm just bitching... Thanks for reading!


----------



## umea

wonder if we'll see any more improved ddr4 bins now that ddr5 is out... either way, the most expensive 32gb ddr4 bin is still cheaper than the cheapest ddr5 one im pretty sure so yeah, not worth at all right now


----------



## Audioboxer

Thanh Nguyen said:


> 3d v cache uses the same socket or need a new mobo?


Same motherboard.



umea said:


> wonder if we'll see any more improved ddr4 bins now that ddr5 is out... either way, the most expensive 32gb ddr4 bin is still cheaper than the cheapest ddr5 one im pretty sure so yeah, not worth at all right now


Probably not anything faster than the 4000 14-15-15-15 bin, but I'm not sure why G.SKILL haven't been able to bin a 3800 14-14-14-14. It would be their best seller.

Unless it's just that much of a challenge to consistently bin that and retail it. One would think nearly all the 4000 14-15-15-15 bins should be able to do it. Unless G.SKILL are just happy pretty much unofficially telling people buy that bin if you want it.

But their current 14-16-16-16 bin for 3800 just feels a bit dated.


----------



## iraff1

Hey guys,

I currently run 4x16gb Single Rank Crucial Modules, 17-18-17-34-51 FLCK 1866 fully stable.
I have a new kit coming of 4x16gb Dual Rank G-Skill Samsung B-Die modules. I just now realized that these are dual rank and not single rank.

From your experience and expertise, is it better to just stick with the crucial modules i have now or try the b-die anyway? Thinking it will be quad rank i hear there will be a lot of complations that comes with it.

The particular gskill kit is: 2x F4-3600C14D-32GTZN (which according to b-die finder is 100% b-die)

Thanks.


----------



## iraff1

I realize now that all Samsung B-Die 16gb sticks has to be dual rank because the samsung b-die ic is a 8gb one. I've seen people that has 4x16 gb b-die have really tight timings and at least an flck of 1900 so i have my hopes up.


----------



## ManniX-ITA

iraff1 said:


> I realize now that all Samsung B-Die 16gb sticks has to be dual rank because the samsung b-die ic is a 8gb one. I've seen people that has 4x16 gb b-die have really tight timings and at least an flck of 1900 so i have my hopes up.


Yes, my guess is they can do better than the Crucial ones.
But it could be hard to achieve FCLK 1900 with tight timings, you need a lot of luck.
Very often with 4 DIMMS you get limited to FCLK 1833/1866.


----------



## iraff1

ManniX-ITA said:


> Yes, my guess is they can do better than the Crucial ones.
> But it could be hard to achieve FCLK 1900 with tight timings, you need a lot of luck.
> Very often with 4 DIMMS you get limited to FCLK 1833/1866.


Yeah, i have a couple of 5950x coming too that are no longer being used, i will sample these and see if i can get lucky, but if not i will definitely be fine running these in 3600/1800 flck as long as i can get the timings down a bit from the crucial.


----------



## mongoled

@domdtxdissar 
In case you missed it,

I did as you asked 









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Can you explain why high voltage and low ProcODT can be dangerous? I'm currently testing vDIMM @1.680v, vSOC @1.175v and ProcODT @28.2 ohms. 😀 That's dyslexia for you. Sorry😔




www.overclock.net





.....


----------



## etfreind

Hello Guys,

I was wondering if anyone would be able to tell Debug Level=1 or Debug Level=7 on TM5 stability test ?


----------



## domdtxdissar

KedarWolf said:


> Put the scripts in the same folder and your MemTestPro 7.0 MTPclassic.exe.
> 
> Rename the attachment and remove the .txt.


Thanks, your script seems to be working just fine, but the whole reason for me buying testmempro instead of just using dram calc like i have done before, was because i thought i could use the slick GUI from runtestmempro-script








But since runtestmempro-script don't support the AMD platform i will just use regular testmempro in the future.. No need for all these tabs when i get them all in a single window with the pro version i bought.. 



mongoled said:


> @domdtxdissar
> In case you missed it,
> 
> I did as you asked
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Can you explain why high voltage and low ProcODT can be dangerous? I'm currently testing vDIMM @1.680v, vSOC @1.175v and ProcODT @28.2 ohms. 😀 That's dyslexia for you. Sorry😔
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> .....


Yes i saw and thanks for the runs 
Thought there were no need to say anymore as the data showed exactly what was predicted.. (same gigaflops score at 1900 as with 2033)
Few, if any at all can show scaling above 1900fclk in linpack.

Some people like their high fclk and say the reason is "hidden clock throttling" because limited by fit values, i think the reason is auto correction from all these WHEA-errors that ppl hide with the suppressor.

But in the end it dont matter what the reason is, data show there is reduced scaling / can be negative performance above 1900 fclk in heavy memory benchmarks like linpack / corona / miner etc.
If you only use "light/easy" programs and/or only like to bench Aida64 there is no problem and this won't effects you, even if you run something like "2200fclk". But i still think people should be honest and admit there is/can be scaling issues above 1900 infinity fabric clock  (some are even running with worse gamingperformance without knowing it because they see better aida numbers)

Maybe this is alittle offtopic, but i guess all this also comes down to point of view.. Following this thread it seems some guys just like to stresstest different memory settings solely for the reason of stressteing memory. (looking at you *Audioboxer ) * I like to try to set highscores in different benchmarks if i can, and for that i need to min-max everything i can to extract maximum performance, stresstesting memory-settings is only a small part of this journey towards my"end goal"  But as with all hobbies there are lots of different views and different opinions about everything.

_edit_

By "reduced scaling above 1900" i mean you don't see the same performance gain each tick above 1900 as you get below 1900.
Example below with made up numbers just to should what i mean and how it could look: ("TES6IN2026" is a normal workload like gaming while "baida58" is a light workload here in fantasyland)

1800:3600 = 100 score in TES6IN2026 - 100 score in baida58
1833:3660 = 110 score in TES6IN2026 - 110 score in baida58
1866:3733 = 120 score in TES6IN2026 - 120 score in baida58
1900:3800 = 130 score in TES6IN2026 - 130 score in baida58
1933:3866 = 118 score in TES6IN2026 - 129 score in baida58
1966:3933 = 125 score in TES6IN2026 - 138 score in baida58
2000:4000 = 127 score in TES6IN2026 - 146 score in baida58
2033:4066 = 129 score in TES6IN2026 - 151score in baida58
2066:4133 = 117 score in TES6IN2026 - 155 score in baida58
2100:4200 = 97 score in TES6IN2026 - 156 score in baida58
2133:4266 = 80 score in TES6IN2026 - 129 score in baida58
2166:4333 = 79 score in TES6IN2026 - 110 score in baida58

For the normal workload reduced scaling start at 1900 while the light workload are holding decent numbers almost all the way to 2100


----------



## mongoled

domdtxdissar said:


> Yes i saw and thanks for the runs
> Thought there were no need to say anymore as the data showed exactly what was predicted.. (same score at 1900 as with 2033)
> Few, if any at all can show scaling above 1900fclk in linpack.
> 
> Some people like their high fclk and say the reason is "hidden clock throttling" because limited by fit values, i think the reason is auto correction from all these WHEA-errors that ppl hide with the suppressor.
> 
> But in the end it dont matter what the reason is, data show there is reduced scaling / negative performance above 1900 fclk in heavy memory benchmarks like linpack / corona / miner etc.
> If you only use "light/easy" programs and/or only like to bench Aida64 there is no problem and this won't effects you, even if you run something like 2200fclk. But i still think people should be honest and admit there is/can be scaling issues above 1900 infinity fabric clock  (some even get negative performance without knowing it)


Thanks, was unsure as you requested the runs and then you didnt post anything.

I thought the general consensus was there is a performance hit in most systems when going above 1900, just the reasons were never pinned down.

I dont think its solely down to WHEA 19s, well at least not in my case (though I do get loads!), but a number of things coming together, though I do agree that for a 24/7 config its not "reliable" as ive seen after every reboot the system acts differently with regards to GFlops....

So until Zen3d arrives im sticking to 3800/1900 and as tight as I can get it which is 13-14-14-14, only issue im having is getting Y-Cruncher to behave, some reboots its runs for hours on end, other reboots it fails after a few cycles, no pattern to whats failing, sometime N32, sometimes VST ....

Just testing now with fixed 4.6Ghz clock, and am probably going to invest into a new PSU as the one im currently using was purchased in 2011 ...


----------



## Audioboxer

domdtxdissar said:


> Thanks, your script seems to be working just fine, but the whole reason for me buying testmempro instead of just using dram calc like i have done before, was because i thought i could use the slick GUI from runtestmempro-script
> View attachment 2531810
> 
> But since runtestmempro-script don't support the AMD platform i will just use regular testmempro in the future.. No need for all these tabs when i get them all in a single window with the pro version i bought..
> 
> 
> Yes i saw and thanks for the runs
> Thought there were no need to say anymore as the data showed exactly what was predicted.. (same gigaflops score at 1900 as with 2033)
> Few, if any at all can show scaling above 1900fclk in linpack.
> 
> Some people like their high fclk and say the reason is "hidden clock throttling" because limited by fit values, i think the reason is auto correction from all these WHEA-errors that ppl hide with the suppressor.
> 
> But in the end it dont matter what the reason is, data show there is reduced scaling / can be negative performance above 1900 fclk in heavy memory benchmarks like linpack / corona / miner etc.
> If you only use "light/easy" programs and/or only like to bench Aida64 there is no problem and this won't effects you, even if you run something like "2200fclk". But i still think people should be honest and admit there is/can be scaling issues above 1900 infinity fabric clock  (some are even running with worse gamingperformance without knowing it because they see better aida numbers)
> 
> Maybe this is alittle offtopic, but i guess all this also comes down to point of view.. Following this thread it seems some guys just like to stresstest different memory settings solely for the reason of stressteing memory. (looking at you *Audioboxer ) * I like to try to set highscores in different benchmarks if i can, and for that i need to min-max everything i can to extract maximum performance, stresstesting memory-settings is only a small part of this journey towards my"end goal"  But as with all hobbies there are lots of different views and different opinions about everything.
> 
> _edit_
> 
> By "reduced scaling above 1900" i mean you don't see the same performance gain each tick above 1900 as you get below 1900.
> Example below with made up numbers just to should what i mean and how it could look: ("TES6IN2026" is a normal workload like gaming while "baida58" is a light workload here in fantasyland)
> 
> 1800:3600 = 100 score in TES6IN2026 - 100 score in baida58
> 1833:3660 = 110 score in TES6IN2026 - 110 score in baida58
> 1866:3733 = 120 score in TES6IN2026 - 120 score in baida58
> 1900:3800 = 130 score in TES6IN2026 - 130 score in baida58
> 1933:3866 = 118 score in TES6IN2026 - 129 score in baida58
> 1966:3933 = 125 score in TES6IN2026 - 138 score in baida58
> 2000:4000 = 127 score in TES6IN2026 - 146 score in baida58
> 2033:4066 = 129 score in TES6IN2026 - 151score in baida58
> 2066:4133 = 117 score in TES6IN2026 - 155 score in baida58
> 2100:4200 = 97 score in TES6IN2026 - 156 score in baida58
> 2133:4266 = 80 score in TES6IN2026 - 129 score in baida58
> 2166:4333 = 79 score in TES6IN2026 - 110 score in baida58
> 
> For the normal workload reduced scaling start at 1900 while the light workload are holding decent numbers almost all the way to 2100


lol, definitely. I get a bigger high out of passing a stability test than I do running benchmarks. Which means I'm probably a bit mad seeing as OCing is supposed to be about the pursuit of better benches/FPS/etc


----------



## ManniX-ITA

domdtxdissar said:


> Some people like their high fclk and say the reason is "hidden clock throttling" because limited by fit values, i think the reason is auto correction from all these WHEA-errors that ppl hide with the suppressor.
> 
> But in the end it dont matter what the reason is, data show there is reduced scaling / can be negative performance above 1900 fclk in heavy memory benchmarks like linpack / corona / miner etc.
> If you only use "light/easy" programs and/or only like to bench Aida64 there is no problem and this won't effects you, even if you run something like 2200fclk. But i still think people should be honest and admit there is/can be scaling issues above 1900 infinity fabric clock  (some are even running with worse performance without knowing it because they see better aida numbers)


We already dissected this a while ago 

Part of the performance degradation is because of the massive amount of WHEA errors; meaning the load due to the event log processing.
With the correct settings (voltages & co), avoiding the real performance degradation due to IF instability, you can get performance scaling up with high FCLK.
The suppressor is helping with the first part, the second part is a matter of luck with sample/board.
Sometimes the sample is just not capable. And if that's the case best to stay at FCLK 1900.
If it's achievable, you may need to have CLKREQ# exposed. If it's not available and you need it it's again better to stay at FCLK 1900.

It's impossible to see scaling up with FCLK with Linpack.
Simply because it's not taking advantage of the higher bandwidth on the Infinity Fabric.
Check the memory bandwidth with HWInfo while running Linpack against the miner.
The miner is taking advantage of the higher bandwidth, you'll see almost double average/peak compared to Linpack.

Linpack is very harsh and has a thermal load similar to Prime95 Small FFT.
Running at high FCLK also has a thermal impact (up to 6c) and together if the cooling is not top notch the result can be lower throughput.

Corona benchmark is not able to scale with FCLK.
It's more dependent on memory latency than bandwidth.


----------



## mongoled

Audioboxer said:


> lol, definitely. I get a bigger high out of passing a stability test than I do running benchmarks. Which means I'm probably a bit mad seeing as OCing is supposed to be about the pursuit of better benches/FPS/etc


Thats because running benchmarks with high scores is easy peasy compared to tweaking a high overclock 24/7 stable setup

😁😁


----------



## KedarWolf

Can someone link my the spreadsheet for @Veii 's TRFC Calculator, no amount of searching will let me find it.


----------



## Mach3.2

KedarWolf said:


> Can someone link my the spreadsheet for @Veii 's TRFC Calculator, no amount of searching will let me find it.











tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com


----------



## ManniX-ITA

Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com


----------



## Audioboxer

ManniX-ITA said:


> We already dissected this a while ago
> 
> Part of the performance degradation is because of the massive amount of WHEA errors; meaning the load due to the event log processing.
> With the correct settings (voltages & co), avoiding the real performance degradation due to IF instability, you can get performance scaling up with high FCLK.
> The suppressor is helping with the first part, the second part is a matter of luck with sample/board.
> Sometimes the sample is just not capable. And if that's the case best to stay at FCLK 1900.
> If it's achievable, you may need to have CLKREQ# exposed. If it's not available and you need it it's again better to stay at FCLK 1900.
> 
> It's impossible to see scaling up with FCLK with Linpack.
> Simply because it's not taking advantage of the higher bandwidth on the Infinity Fabric.
> Check the memory bandwidth with HWInfo while running Linpack against the miner.
> The miner is taking advantage of the higher bandwidth, you'll see almost double average/peak compared to Linpack.
> 
> Linpack is very harsh and has a thermal load similar to Prime95 Small FFT.
> Running at high FCLK also has a thermal impact (up to 6c) and together if the cooling is not top notch the result can be lower throughput.
> 
> Corona benchmark is not able to scale with FCLK.
> It's more dependent on memory latency than bandwidth.


Or you could be like me and it appear that you are getting a performance uplift, stability testing isn't failing and yet... USB, USB cannot handle the WHEA when the CPU is under extreme loads.

Solution? Unplug every usb device, disable every USB port and never again use a USB device. Take that AMD software engineers. You won't be forcing me to buy a 3D cache chip.


----------



## ManniX-ITA

Audioboxer said:


> Or you could be like me and it appear that you are getting a performance uplift, stability testing isn't failing and yet... USB, USB cannot handle the WHEA when the CPU is under extreme loads.


Yes this high variance in the tolerable voltages for IOD and CCD can create this kind of awkward situations.
Theoretically it'd better to have a CPU that needs less voltage to operate but in this case it works against.
Maybe if one day AMD will finally proper fix the USB issues it could work but I wouldn't hold my breath.


----------



## PuffyArgos

Ok, so I have ditched the DR kit I have recently been discussing in favor of a set of gskill F4-4800C17-8GTRS 1.6V. I've paired the kit with the 5950x and an ASRock Phantom Gaming itx/ax board.

1800 was a piece of cake. It'll do 25 cycles of TM5. I didn't screen capture the result because it is pretty unimpressive, but the timings are as follows:


Spoiler: IF-1800 Timings at 1.48V














1900 has been tough though. I wasn't expecting it to be as one of my TG 3600C14 kits will do flat 14s at 3800 no problem. In fact, all I needed to do was take my timings from 3600, add a bit of vdimm and sock voltage and it was good to go. It has been running 24/7 for the better part of a year. My thought was that if the new kit could do 17-19-19-19 at 1.6V, the then following would loosely hold true.

480017191919460016181818440015171717420014161616400013151515380012141414360011131313

I don't know how realistic it was, but I was expecting I could achieve flat 14s at 3800 and attempt flat 15s at 4000 if my IMC could handle 2000mhz. I could rest easy about throwing shed loads of voltage at this kit as the XMP profile boots VDIMM 1.6v with 24/24/24/24 CAD Bus. 

All that said, I couldn't get anywhere close to stable at 3800 using my 3600 timings so I decided to back off a bit and try something a bit less aggressive as follows:


Spoiler: IF-1900 Timings at 1.52V














I can only get the IMC stable with more VDIMM, Soc voltage, procODT, and CAD bus. Using a quick 3 cycle TM5 to test I receive the following errors:

Cycle 1: 7
Cycle 2: 2, 10, 1, 1, 1, 4, 4, 9, 7, 11, 11
Cycle 3: 12, 10, 10, 10, 5, 4, 4, 4, 0, 0, 13, 9, 9, 14, 1, 1, 15

I feel like the CAD bus is not optimal, but it seems like I have tried every combination under the sun without luck. If anyone has some thoughts I would be greatful for them.

As a side note, I was able to get the system to boot with flat 14s at IF-2000mhz


Spoiler: IF-2000 Timings at 1.6V














Only about 600 errors through 3 cycles of TM5, lol. A project for after I've sorted out 3800 anyway.


----------



## ManniX-ITA

PuffyArgos said:


> Cycle 1: 7
> Cycle 2: 2, 10, 1, 1, 1, 4, 4, 9, 7, 11, 11
> Cycle 3: 12, 10, 10, 10, 5, 4, 4, 4, 0, 0, 13, 9, 9, 14, 1, 1, 15


The 2,10 at Cycle 2 looks like tRCDRD too tight.
But the whole sequence suggest overheating.
Are you monitoring the temperature?


----------



## PuffyArgos

ManniX-ITA said:


> The 2,10 at Cycle 2 looks like tRCDRD too tight.
> But the whole sequence suggest overheating.
> Are you monitoring the temperature?


HWInfo reports high 40s on both sticks. At 3600 I'm at mid 40s on both.


----------



## nick name

PuffyArgos said:


> HWInfo reports high 40s on both sticks. At 3600 I'm at mid 40s on both.


With tight timings I will see errors start around 42*C.


----------



## PuffyArgos

ManniX-ITA said:


> The 2,10 at Cycle 2 looks like tRCDRD too tight.
> But the whole sequence suggest overheating.
> Are you monitoring the temperature?





Spoiler: IF-1900 Timings and Testing at 1.52V














Backing off on TRCDRD did the trick. I'll tighten timings a bit and see if I can get 25 runs.


----------



## domdtxdissar

PuffyArgos said:


> Ok, so I have ditched the DR kit I have recently been discussing in favor of a set of gskill F4-4800C17-8GTRS 1.6V. I've paired the kit with the 5950x and an ASRock Phantom Gaming itx/ax board.
> 
> 1800 was a piece of cake. It'll do 25 cycles of TM5. I didn't screen capture the result because it is pretty unimpressive, but the timings are as follows:
> 
> 
> Spoiler: IF-1800 Timings at 1.48V
> 
> 
> 
> 
> View attachment 2531952
> 
> 
> 
> 1900 has been tough though. I wasn't expecting it to be as one of my TG 3600C14 kits will do flat 14s at 3800 no problem. In fact, all I needed to do was take my timings from 3600, add a bit of vdimm and sock voltage and it was good to go. It has been running 24/7 for the better part of a year. My thought was that if the new kit could do 17-19-19-19 at 1.6V, the then following would loosely hold true.
> 
> 480017191919460016181818440015171717420014161616400013151515380012141414360011131313
> 
> I don't know how realistic it was, but I was expecting I could achieve flat 14s at 3800 and attempt flat 15s at 4000 if my IMC could handle 2000mhz. I could rest easy about throwing shed loads of voltage at this kit as the XMP profile boots VDIMM 1.6v with 24/24/24/24 CAD Bus.
> 
> All that said, I couldn't get anywhere close to stable at 3800 using my 3600 timings so I decided to back off a bit and try something a bit less aggressive as follows:
> 
> 
> Spoiler: IF-1900 Timings at 1.52V
> 
> 
> 
> 
> View attachment 2531953
> 
> 
> 
> I can only get the IMC stable with more VDIMM, Soc voltage, procODT, and CAD bus. Using a quick 3 cycle TM5 to test I receive the following errors:
> 
> Cycle 1: 7
> Cycle 2: 2, 10, 1, 1, 1, 4, 4, 9, 7, 11, 11
> Cycle 3: 12, 10, 10, 10, 5, 4, 4, 4, 0, 0, 13, 9, 9, 14, 1, 1, 15
> 
> I feel like the CAD bus is not optimal, but it seems like I have tried every combination under the sun without luck. If anyone has some thoughts I would be greatful for them.
> 
> As a side note, I was able to get the system to boot with flat 14s at IF-2000mhz
> 
> 
> Spoiler: IF-2000 Timings at 1.6V
> 
> 
> 
> 
> View attachment 2531955
> 
> 
> 
> Only about 600 errors through 3 cycles of TM5, lol. A project for after I've sorted out 3800 anyway.


Do you get same errors at T2 GDM-disable ? Could be IMC


----------



## PuffyArgos

Ok, so I just noticed when I ran an Aida benchmark that it wasn't reporting my memclock properly, it was showing high. I had a look at hwinfo and noticed my bus clock is at 108.2. This is entirely unexpected as I have it set to manual in BIOS at 100mhz.


Spoiler: hwinfo bus clock














This is my first ASRock board. It doesn't appear that I have an option to disable spread spectrum control. I would think that manually assigning a bus clock would automatically disable it though. That high would suggest something else is at play though. I have PBO disabled and a static OC of 4300 set. With PBO enabled I get the same behavior. In fact, I noticed it while PBO was enabled and thought it might have been a behavior of PBO. When I moved to a static clock the behavior remained.

Seems I may have wasted 2 days of testing... I will give an update once I can get this bus clock sorted. Not having any luck at present, but at least I have a problem identified.



domdtxdissar said:


> Do you get same errors at T2 GDM-disable ? Could be IMC


I haven't tried with 2T, that's a good idea.


----------



## Audioboxer

lol.... Karhu rebooted PC within like 2 seconds.










Karhu doesn't reboot PC now, but errors very quicky.

TIME TO PUSH 1.7V! ⚡










So what you're saying is we need to go higher still....


----------



## domdtxdissar

Audioboxer said:


> View attachment 2532002
> 
> 
> lol.... Karhu rebooted PC within like 2 seconds.
> 
> View attachment 2532003
> 
> 
> Karhu doesn't reboot PC now, but errors very quicky.
> 
> TIME TO PUSH 1.7V! ⚡
> 
> View attachment 2532012
> 
> 
> So what you're saying is we need to go higher still....


If you really are deadset on running CL12, use maxmem, something like 6gb should do just fine


----------



## Audioboxer

domdtxdissar said:


> If you really are deadset on running CL12, use maxmem, something like 6gb should do just fine


Just messing around for fun. I was struggling a bit to get it fully stable at 3600 so I never really thought it would ever be stable at 3800.

On a related note why is it that helps? I think buildzoid restricts memory amount when doing extreme ocing.


----------



## domdtxdissar

Audioboxer said:


> Just messing around for fun. I was struggling a bit to get it fully stable at 3600 so I never really thought it would ever be stable at 3800.
> 
> On a related note why is it that helps? I think buildzoid restricts memory amount when doing extreme ocing.


If i remember correctly, maxmem in needed at these high voltages to stop/reduce the PCB crash (above 1.6-1.65 vdimm)


----------



## Audioboxer

domdtxdissar said:


> If i remember correctly, maxmem in needed at these high voltages to stop/reduce the PCB crash (above 1.6-1.65 vdimm)


That makes sense, I guess. But at this point it seems to just be pushing numbers for the sake of it (like I was) because there is no real point in running your memory at a reduced capacity.

On the basis of "Hey, the stability test passes when I only have 3GB active!" 

But I might look into it for some fun, really have nothing else to do right now pending a new BIOS update and seeing if there is any hope at all for FCLK 2000 on these chips. I doubt AMD cares anymore when they're working on getting their 3D cache variants out.


----------



## Hibbing

Audioboxer said:


> View attachment 2532002
> 
> 
> lol.... Karhu rebooted PC within like 2 seconds.
> 
> View attachment 2532003
> 
> 
> Karhu doesn't reboot PC now, but errors very quicky.
> 
> TIME TO PUSH 1.7V! ⚡
> 
> View attachment 2532012
> 
> 
> So what you're saying is we need to go higher still....


Try SCL 4.


----------



## Mach3.2

Audioboxer said:


> That makes sense, I guess. But at this point it seems to just be pushing numbers for the sake of it (like I was) because there is no real point in running your memory at a reduced capacity.
> 
> On the basis of "Hey, the stability test passes when I only have 3GB active!"
> 
> But I might look into it for some fun, really have nothing else to do right now pending a new BIOS update and seeing if there is any hope at all for FCLK 2000 on these chips. I doubt AMD cares anymore when they're working on getting their 3D cache variants out.


But hey, thread titles says 24/7 stability. at some point we just gotta say to ourselves 3800mhz 14-14-14-28 or 15-15-15-30 is a more than decent overclock for everyday use. 🤣

If only there is a time compress feature for mem testing.. 🤪


----------



## Audioboxer

Mach3.2 said:


> But hey, thread titles says 24/7 stability. at some point we just gotta say to ourselves 3800mhz 14-14-14-28 or 15-15-15-30 is a more than decent overclock for everyday use. 🤣
> 
> If only there is a time compress feature for mem testing.. 🤪


Of course it is, but I think I am understandably mad at AMD and their stupid USB/IF issues 



Hibbing said:


> Try SCL 4.


It's just tCL12, getting that stable at 3800 is going to be a nightmare with voltage. I was just doing it for fun, was happy enough it even booted!

Even on watercooling there's no way I'd daily voltage that high for like 0.3ns less latency. Not when tCL13 runs at 1.55v.


----------



## MyUsername

Audioboxer said:


> Of course it is, but I think I am understandably mad at AMD and their stupid USB/IF issues
> 
> 
> 
> It's just tCL12, getting that stable at 3800 is going to be a nightmare with voltage. I was just doing it for fun, was happy enough it even booted!
> 
> Even on watercooling there's no way I'd daily voltage that high for like 0.3ns less latency. Not when tCL13 runs at 1.55v.


Dude, you're gonna need 2 volts to probably just get them bench stable lol


----------



## Audioboxer

MyUsername said:


> Dude, you're gonna need 2 volts to probably just get them bench stable lol


I can actually bench no problem










Unless by bench stable you mean showing the results it _should_ show, then yes, the current results are awful showing how unstable I am 

Even though I ran the above in Windows 11 with all my normal background apps running the latency let alone read/write and copy are way worse than what they are at tCL13.


----------



## jcpq

Hello
Can anyone help me overcome these errors?


----------



## mirzet1976

jcpq said:


> Hello
> Can anyone help me overcome these errors?
> 
> View attachment 2532151


----------



## Audioboxer

jcpq said:


> Hello
> Can anyone help me overcome these errors?
> 
> View attachment 2532151











tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com





Quick and dirty check, put tRCDRD to 15 and see if 3 cycles pass.

Other than that, SCLs to 4 for now, VSOC might need a few notches higher and try VDIMM at 1.55v just to see. I'm not familiar or comfortable enough talking about ProcODT/Rtts on SR, but they might need looked at.


----------



## nick name

jcpq said:


> Hello
> Can anyone help me overcome these errors?
> 
> View attachment 2532151


Whoa. For me 3800 with 1T and GDM off would instantly crash when tested unless AddrCmdSetup is set to 56. I think it's amazing that you can complete a test without it. Perhaps AddrCmdSetup at 56 will help you too.


----------



## Audioboxer

nick name said:


> Whoa. For me 3800 with 1T and GDM off would instantly crash when tested unless AddrCmdSetup is set to 56. I think it's amazing that you can complete a test without it. Perhaps AddrCmdSetup at 56 will help you too.


SR can often do 1T without setup times. It's DR that almost always needs it.


----------



## MyUsername

Audioboxer said:


> I can actually bench no problem
> 
> View attachment 2532144
> 
> 
> Unless by bench stable you mean showing the results it _should_ show, then yes, the current results are awful showing how unstable I am
> 
> Even though I ran the above in Windows 11 with all my normal background apps running the latency let alone read/write and copy are way worse than what they are at tCL13.


Just mental, I think your memory and imc combo are probably the best you can hope for, but even at tcl12 there's a lot of correction going on. I can't even boot at tcl13 man. I have one stick that'll moan at test 14 with 1usmus, the other stick errors all over the place 2, 8, 10, 11, 14, POS stick, 1900fclk is weird unless I enable LN2, but that breaks cppc in Win 11, but I'm back to Win 10 until 11 has matured anyway. But give my IOD 1.2V after droop and it'll be happy doing 2000fclk all day with maybe three whea's all day with the suppressor, I just have to keep the memory under 43'C while testing, usually about 40-41'C max.


----------



## Audioboxer

MyUsername said:


> Just mental, I think your memory and imc combo are probably the best you can hope for, but even at tcl12 there's a lot of correction going on. I can't even boot at tcl13 man. I have one stick that'll moan at test 14 with 1usmus, the other stick errors all over the place 2, 8, 10, 11, 14, POS stick, 1900fclk is weird unless I enable LN2, but that breaks cppc in Win 11, but I'm back to Win 10 until 11 has matured anyway. But give my IOD 1.2V after droop and it'll be happy doing 2000fclk all day with maybe three whea's all day with the suppressor, I just have to keep the memory under 43'C while testing, usually about 40-41'C max.


Actually wondering what someone would achieve with a G chip and this bin. The 5950x while likely better than the 5900x (most of these are probably rejected 5950x bins lol) still probably has an IMC that pales in comparison to some of the 1 CCD chips or G chips.

The memory bin itself is obviously golden, I used to think memory bins with low voltage ratings would be the best and I dare say a 3200C14 at 1.35v or the 4000C16 at 1.4v _can_ be golden. But a 1.55v bin needs so much going for it to retail at 1.55v. High thermal overhead, high voltage tolerance and then coupled with 4000C14, it likely gives the best chance of 3800 running at the tightest timings possible.

I hope AMDs 3D cache chips are what everyone wants them to be, might be one last upgrade for me before hunkering down for a few years and not even thinking about DDR5/PCIe 5.0 and new chips.


----------



## MyUsername

Audioboxer said:


> Actually wondering what someone would achieve with a G chip and this bin. The 5950x while likely better than the 5900x (most of these are probably rejected 5950x bins lol) still probably has an IMC that pales in comparison to some of the 1 CCD chips or G chips.
> 
> The memory bin itself is obviously golden, I used to think memory bins with low voltage ratings would be the best and I dare say a 3200C14 at 1.35v or the 4000C16 at 1.4v _can_ be golden. But a 1.55v bin needs so much going for it to retail at 1.55v. High thermal overhead, high voltage tolerance and then coupled with 4000C14, it likely gives the best chance of 3800 running at the tightest timings possible.
> 
> I hope AMDs 3D cache chips are what everyone wants them to be, might be one last upgrade for me before hunkering down for a few years and not even thinking about DDR5/PCIe 5.0 and new chips.


G chips probably can't do much more than you can already achieve timing wise, that's already nuts at cl13 3800M/Ts. Mem clocks I can't see going higher than 4400, it would be interesting to see the limits of DR kits though. Most of the crazy high fclk have been on SR kits haven't they?. On my 3900x I just about got 4400 on a 4000 cl16 kit at 2 volts I think on a Gigabyte Master, it wasn't even stable enough to save a picture, my 5950x can just about do 4333 and with my fclk @1:1. I think the crazy speeds and stupid tight timings on imc depends on the quality of the wafer they're made from, at stock 99% may be stable but you'll find the quality when you push it. I think the iod imc on my 3900x is better than on my 5950x.

I have a 4000cl16 1.4V kit and they're utter dog poo, fine at rated speed, but straight 14s 1.55V and TM5 spams 100s of errors both sticks individually and crashes hard. Pure gamble on what you buy I reckon, all you can do is go by tight timings on the sticker to give you the best chance at 3800 straight 14. These 4000cl14 kits at 1.55v need cooling no choice about it and I think Sammy b dies are safe up to 1.6 volts but obviously get warm.

These 3D cache chips are going to be quick, but that's the cores. The same lottery with the SoC IOD's will be the same as with 3000 and 5000 series, so I think the 1900Fclk blackholes will still exist on some, Fclk will be the same. I had a chat with my mate at work about DDR5, he said yeah it will be awesome, I said it won't. It needs 1 or 2 years for Samsung B-die equivalent to be made. Yeah DDR5 has high bandwidth but poor latency. And PCIe 5 has no use for us, only for the server market can utilize this properly, I have 3 1TB Corsair MP600 first gen in raid 0 11.5GB/s read and 12.3GB/s write and I really can't see me needing more than this for a long time.


----------



## Audioboxer

MyUsername said:


> G chips probably can't do much more than you can already achieve timing wise, that's already nuts at cl13 3800M/Ts. Mem clocks I can't see going higher than 4400, it would be interesting to see the limits of DR kits though. Most of the crazy high fclk have been on SR kits haven't they?. On my 3900x I just about got 4400 on a 4000 cl16 kit at 2 volts I think on a Gigabyte Master, it wasn't even stable enough to save a picture, my 5950x can just about do 4333 and with my fclk @1:1. I think the crazy speeds and stupid tight timings on imc depends on the quality of the wafer they're made from, at stock 99% may be stable but you'll find the quality when you push it. I think the iod imc on my 3900x is better than on my 5950x.
> 
> I have a 4000cl16 1.4V kit and they're utter dog poo, fine at rated speed, but straight 14s 1.55V and TM5 spams 100s of errors both sticks individually and crashes hard. Pure gamble on what you buy I reckon, all you can do is go by tight timings on the sticker to give you the best chance at 3800 straight 14. These 4000cl14 kits at 1.55v need cooling no choice about it and I think Sammy b dies are safe up to 1.6 volts but obviously get warm.
> 
> These 3D cache chips are going to be quick, but that's the cores. The same lottery with the SoC IOD's will be the same as with 3000 and 5000 series, so I think the 1900Fclk blackholes will still exist on some, Fclk will be the same. I had a chat with my mate at work about DDR5, he said yeah it will be awesome, I said it won't. It needs 1 or 2 years for Samsung B-die equivalent to be made. Yeah DDR5 has high bandwidth but poor latency. And PCIe 5 has no use for us, only for the server market can utilize this properly, I have 3 1TB Corsair MP600 first gen in raid 0 11.5GB/s read and 12.3GB/s write and I really can't see me needing more than this for a long time.


Yeah the gamble on what you buy is why I think I'm re-thinking why it's worth buying something binned at 1.55v with tight timings. For months I was on the "lowest voltage with low timings" train. Sure, I'm going guess it's absolutely possible there is a 4000 14-15-15-15 bin that can't do 3800 14-14-14-14. Heck, I briefly had a 3600 14-14-14-14 1.45v bin, a bin released alongside 4000 14-15-15-15 this year that could not do tRCDRD 14 at 3800. I was pretty damn surprised at that, seemed logical to me a 3600 bin at flat 14 could jump up to 3800 flat 14. Nope.

Instead, this bin can damn well run 3800 flat 14 at 1.44v!










I guess you can sum it up as you do get what you pay for, but, if you pay less you can roll the dice and possibly end up with the same performance whilst saving yourself some money. RNG!










When I was messing around with 4000 14-14-14-14 I managed to pull in 49.3ns, but this was with 1 CCD disabled and ultimately an IF of 2000 I couldn't manage to stop USB issues with. What has me excited about the above though is this is running a normal voltage/normal timings and normal CPU curve. The above isn't with anything stupid like 2V on the DRAM, or a static CPU OC at a ridiculous voltage. It's what I would run if the IF was stable. So fingers crossed AMD sorts out the IF on the 3D cache chips.

So single CCD seems to remain king for latency, but given that that 2 CCD latency increase is _only _2~3ns, you arguably get far more benefits for your overall PC having something like a 5950x. As above if you're obsessed with latency benchmarks just disable a CCD on your 5950x 😂 Did take me a while to discover there was a setting for that in the MSI bios! Pretty cool though, so you can take those pictures of 48.x/49.x latency and feel part of the "low latency kids table" https://docs.google.com/spreadsheet...BfT1WkUU*N4j_JRj3KJNcsYnYfBNfhw#gid=321590489

@mongoled doing us proud with 50.4ns, which is funnily enough exactly what I can achieve with my daily 3800 profile and 1 CCD disabled










He sneaked up to 3866 though, but I feel comfortable enough saying that basically is the 3800 club 

The above two results give an idea that tCL13 (13-8-14-12) at 3800 will not beat tCL14 (14-14-14-14) at 4000. The 4000 profile will achieve about 1.0ns less. Not only that there were a few secondary timings I ran a bit looser on my 4000 profile to hypothetically reduce the strain with stability testing/benchmarking at 2000 IF. Hypothetically could be scope to push that 49.3 down a little more.

So it just goes to show how desperate we'd all be for AMD to sort out at least the 2000 IF. Especially given most decent DDR4 kits will achieve 4000. Lets hope they do it, because all neutrals should be happy to admit Intel are back in the game! Main issue right now is DDR5 is not worth using IMO, but that will change over time.


----------



## ManniX-ITA

MyUsername said:


> These 3D cache chips are going to be quick, but that's the cores. The same lottery with the SoC IOD's will be the same as with 3000 and 5000 series, so I think the 1900Fclk blackholes will still exist on some, Fclk will be the same. I had a chat with my mate at work about DDR5, he said yeah it will be awesome, I said it won't. It needs 1 or 2 years for Samsung B-die equivalent to be made. Yeah DDR5 has high bandwidth but poor latency. And PCIe 5 has no use for us, only for the server market can utilize this properly, I have 3 1TB Corsair MP600 first gen in raid 0 11.5GB/s read and 12.3GB/s write and I really can't see me needing more than this for a long time.


The new 3D chips could benefit from improved node fabrication. Otherwise I'd expect they would have big issues keeping the temperatures in check.
Hopefully also the IMC and the IF substrate have been pimped up. But I wouldn't expect AMD has done anything about the FCLK. It's not a metric for marketing like CB/CPU-z scores and gaming FPS.

I was expecting worse from DDR5; there's a chance that for Zen4 will be ready to roll some good numbers. Over 100GB/s at 50ns on Alder Lake is quite a good start.

About PCIe5 more than peak bandwidth I expect it will benefit the consumer segment with density.
Only 8 lanes for the GPU, 2 lanes for the NVMe, 4 lanes for the Chipset that can properly support multiple USB4/TB4 connections.
There would make more sense than impressive bandwidth peaks.
Even it there's also DirectStorage coming which could give a sense to these super fast NVMe.

Overall, end of next year could be exciting


----------



## MyUsername

Audioboxer said:


> Yeah the gamble on what you buy is why I think I'm re-thinking why it's worth buying something binned at 1.55v with tight timings. For months I was on the "lowest voltage with low timings" train. Sure, I'm going guess it's absolutely possible there is a 4000 14-15-15-15 bin that can't do 3800 14-14-14-14. Heck, I briefly had a 3600 14-14-14-14 1.45v bin, a bin released alongside 4000 14-15-15-15 this year that could not do tRCDRD 14 at 3800. I was pretty damn surprised at that, seemed logical to me a 3600 bin at flat 14 could jump up to 3800 flat 14. Nope.
> 
> Instead, this bin can damn well run 3800 flat 14 at 1.44v!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I guess you can sum it up as you do get what you pay for, but, if you pay less you can roll the dice and possibly end up with the same performance whilst saving yourself some money. RNG!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> When I was messing around with 4000 14-14-14-14 I managed to pull in 49.3ns, but this was with 1 CCD disabled and ultimately an IF of 2000 I couldn't manage to stop USB issues with. What has me excited about the above though is this is running a normal voltage/normal timings and normal CPU curve. The above isn't with anything stupid like 2V on the DRAM, or a static CPU OC at a ridiculous voltage. It's what I would run if the IF was stable. So fingers crossed AMD sorts out the IF on the 3D cache chips.
> 
> So single CCD seems to remain king for latency, but given that that 2 CCD latency increase is _only _2~3ns, you arguably get far more benefits for your overall PC having something like a 5950x. As above if you're obsessed with latency benchmarks just disable a CCD on your 5950x 😂 Did take me a while to discover there was a setting for that in the MSI bios! Pretty cool though, so you can take those pictures of 48.x/49.x latency and feel part of the "low latency kids table" https://docs.google.com/spreadsheet...BfT1WkUU*N4j_JRj3KJNcsYnYfBNfhw#gid=321590489
> 
> @mongoled doing us proud with 50.4ns, which is funnily enough exactly what I can achieve with my daily 3800 profile and 1 CCD disabled
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> He sneaked up to 3866 though, but I feel comfortable enough saying that basically is the 3800 club
> 
> The above two results give an idea that tCL13 (13-8-14-12) at 3800 will not beat tCL14 (14-14-14-14) at 4000. The 4000 profile will achieve about 1.0ns less. Not only that there were a few secondary timings I ran a bit looser on my 4000 profile to hypothetically reduce the strain with stability testing/benchmarking at 2000 IF. Hypothetically could be scope to push that 49.3 down a little more.
> 
> So it just goes to show how desperate we'd all be for AMD to sort out at least the 2000 IF. Especially given most decent DDR4 kits will achieve 4000. Lets hope they do it, because all neutrals should be happy to admit Intel are back in the game! Main issue right now is DDR5 is not worth using IMO, but that will change over time.


Just for a laugh 1CCD








And cl12








59 read and write, 57 copy.




ManniX-ITA said:


> The new 3D chips could benefit from improved node fabrication. Otherwise I'd expect they would have big issues keeping the temperatures in check.
> Hopefully also the IMC and the IF substrate have been pimped up. But I wouldn't expect AMD has done anything about the FCLK. It's not a metric for marketing like CB/CPU-z scores and gaming FPS.
> 
> I was expecting worse from DDR5; there's a chance that for Zen4 will be ready to roll some good numbers. Over 100GB/s at 50ns on Alder Lake is quite a good start.
> 
> About PCIe5 more than peak bandwidth I expect it will benefit the consumer segment with density.
> Only 8 lanes for the GPU, 2 lanes for the NVMe, 4 lanes for the Chipset that can properly support multiple USB4/TB4 connections.
> There would make more sense than impressive bandwidth peaks.
> Even it there's also DirectStorage coming which could give a sense to these super fast NVMe.
> 
> Overall, end of next year could be exciting


We hope, but I think the 3D Fabric is still on 7nm just stacked. Does anyone outside AMD know how hot cpu cache gets?

Just going by Guru3d's review, DDR5 with 77.1ns doesn't get me excited and that's G.Skill 40 40 40 76 5800M/Ts.

In a year I can see the benefits when hardware catches up as PCIe 5 nvme is still a prototype. But, if Zen4 has 28 lanes then 16 GPU, 4 nvme and 4 to the chipset and 4 somewhere else or another nvme on the cpu. The chipset will benefit a little as those 4 lanes won't get flooded as much, but if you hang 2 PCIe 4 nvme off the chipset then it's the same problem again.

Yes directstorage is coming, but games have to be coded for it, so yippee something else to wait for. Will having a massive array of nvme or will one nvme at 7GB/s be enough?

Next year sounds expensive lol


----------



## Audioboxer

MyUsername said:


> Just for a laugh 1CCD
> View attachment 2532284
> 
> And cl12
> View attachment 2532286
> 
> 59 read and write, 57 copy.
> 
> 
> 
> We hope, but I think the 3D Fabric is still on 7nm just stacked. Does anyone outside AMD know how hot cpu cache gets?
> 
> Just going by Guru3d's review, DDR5 with 77.1ns doesn't get me excited and that's G.Skill 40 40 40 76 5800M/Ts.
> 
> In a year I can see the benefits when hardware catches up as PCIe 5 nvme is still a prototype. But, if Zen4 has 28 lanes then 16 GPU, 4 nvme and 4 to the chipset and 4 somewhere else or another nvme on the cpu. The chipset will benefit a little as those 4 lanes won't get flooded as much, but if you hang 2 PCIe 4 nvme off the chipset then it's the same problem again.
> 
> Yes directstorage is coming, but games have to be coded for it, so yippee something else to wait for. Will having a massive array of nvme or will one nvme at 7GB/s be enough?
> 
> Next year sounds expensive lol


Yeah 7% in Karhu seems to be the "TM5 666666666" within seconds. As in, if you crash at 7% in Karhu you are VERY unstable. Must be whatever stage of memory testing Karhu shifts to at around 7% is the first real test for the memory.

Only way I got further than 7% at tCL 12 was pumping 1.7v into the RAM. As others pointed out to me around that voltage it's likely maxmem has to be limited to even stand a chance of holding up.

Running 1 CCD is fun, it gives us an idea of where the memory would sit for all the other AMD CPUs. Your 50.2 is good, I'd say that is probably fair with XMP timings of 14-15-15-15. I was 14-14-14-14 and some pretty tight secondaries for 49.3.


----------



## Audioboxer

So I unlocked the cheat code for "run your memory at whatever timings you want" 😂👀

And yes, just to confirm, the memory testing is obviously still working, will error when VDIMM is too low










So around 1.7v looks like it's needed for tCL12. Shame B-die can't seem to handle 1.7v normally, so voltage capabilities get hit first before potential timing capabilities 👀

@Veii How does one bruteforce 1.7v through 32GB of B-die without the PCB crashing? 🤣 It calls itself DDR4 and it can't even handle a measly 1.7v! Unacceptable!

*edit *- Looks like we're in for a shout at 1.69v!


----------



## Blameless

ManniX-ITA said:


> The new 3D chips could benefit from improved node fabrication. Otherwise I'd expect they would have big issues keeping the temperatures in check.


SRAM is not logic and cache doesn't get anywhere near as hot as the cores.

The only concerns I have with the new Vcache parts is the silicon spacer they have to put over the rest of the CCD. The total die thickness should be the same, but the bonding does seem like it could be another point of failure and the interface could slightly hurt thermals.

I'm not expecting much in the way of FCLK improvements, but even with the same design on the IOD, Vermeer does have a strong tendency to clock higher than Matisse, so maybe we'll see another bump. Then again, the larger cache could just as easily become a limiting factor.


----------



## ManniX-ITA

Blameless said:


> SRAM is not logic and cache doesn't get anywhere near as hot as the cores.
> 
> The only concerns I have with the new Vcache parts is the silicon spacer they have to put over the rest of the CCD. The total die thickness should be the same, but the bonding does seem like it could be another point of failure and the interface could slightly hurt thermals.


Yeah not close as hot but still it does get warm.
It's like putting a thick duvet over someone already sweating in summer under the sun 
For sure it will reduce the thermal dissipation of the cores.
Considering some parts are already hitting over 100c, I wonder how well it'll be managed.
I'm inclined to think as well the improved process will counter balance the worse thermals and the FCLK will probably end up the same.


----------



## Audioboxer

Me for the last month or so: Yeah, I gave up on tRCDRD 13, just tCL 13 for me.

Me after discovering the new cheat code:












32GB of RAM? Who needs that










3.2GB is the new 32! Games love it!


----------



## Audioboxer

So, a slightly more serious look at maxmem










6GB










9.1GB










12GB

So 12GB brings in the quick errors. So while this is fun, it's clearly not going to be daily usable if 1.69v is going to crash the PCB at as low as 12GB out of 32GB.

Can anyone also explain how maxmem works? If you've got 2 sticks and 32GB is Windows using a total amount from both sticks or is it using all of the allowance on one stick first?


----------



## Audioboxer

Alright, last post of findings. So, 12GB really looks to be where issues start to arise. Using over 1.6V falls down quickly at 12GB. Ok, never mind, tC L12 is really just for fun at 3800. 1.69v seems impossible for a b-die PCB at normal operating quantity.

But I was also running tRCDRD 13, something I couldn't get working at 1.55v. Does this mean bruteforcing voltage was helping tRCDRD 13? 🤔

After some testing...










Seems like its maxmem that got tRCDRD 13 working. It just so happened I was at 1.69v earlier. Now I'm back down to 1.55v and it's holding out.

How did I come to this conclusion the above is holding out?










If I go up to 12GB I can repeatedly get it to crash around this same time, every time. It passes by the 9/10 minute mark fine, every time, at 9GB.

So what does this tell me? _Some_ of my memory is capable of tRCDRD 13? I did ask above if anyone can explain maxmem to me, it would help know if Windows uses both or prioritises one stick when under a single stick size limit.

Or is it my IMC, it cannot handle the data rate of tRCDRD 13 at 3800 when dealing with 12GB+? This could mean this kit of memory has a chance to do tRCDRD 13 on another CPU.

Good, interesting fun, anyway. Figured out that tCL really can be bruteforced with voltage. tCL 12 at 3800 will likely be good at 1.69v~1.7v. Also learned that high VDIMM really does nuke the PCB on b-die. Whether or not my ProcODT/Rtts/DrvStrs can do anything to help a bit to go higher than 1.55v, it seems trying to run like 1.7v on 32GB just isn't happening.

Also figured out that tRCDRD really is quite complex. Multiple things look like leading to it failing, but at the same time, it might _not_ be your actual memory that stops you running a lower tRCDRD. I need some more expert advice here on what I'm seeing above.

*edit *- For anyone who wants to know 12-18-13-12 2T 3800 @ 1.69v 1CCD gets you










50ns. That seems like a pretty fair result, but absolutely no one is going to pump 1.69v into their RAM just to get tCL12 when a tCL13 profile at around 1.55v~1.6v could be dailied and likely be around 50.4~6ns.

1T might drop that down to 49.x but my stupid issues continue with even tCLs at 1T with tPHYRDL and 28/26.


----------



## nick name

MyUsername said:


> -snip-
> On my 3900x I just about got 4400 on a 4000 cl16 kit at 2 volts I think on a Gigabyte Master, it wasn't even stable enough to save a picture, my 5950x can just about do 4333 and with my fclk @1:1. I think the crazy speeds and stupid tight timings on imc depends on the quality of the wafer they're made from, at stock 99% may be stable but you'll find the quality when you push it. I think the iod imc on my 3900x is better than on my 5950x.
> 
> -snip-


Wait, you could POST at nearly 2200 FCLK on a 3900X? And 21067 FCLK on your 5950X? I'm not sure I've seen anyone else that high.


----------



## nick name

I have a G.Skill TridentZ 4400C19 1.4V 2x8GB kit that does 3800 flat 14s. I haven't tested overnight though, but I will try to tonight.


----------



## MyUsername

nick name said:


> Wait, you could POST at nearly 2200 FCLK on a 3900X? And 21067 FCLK on your 5950X? I'm not sure I've seen anyone else that high.


That would be a golden sample, no lol. I found it, my 5950x can't do this.


----------



## nick name

MyUsername said:


> That would be a golden sample, no lol. I found it, my 5950x can't do this. -snip-


Ahhh. The 3900X I just had could POST 4600MHz but now I can't remember the timings. They were probably 18s at 2T. I can't remember my first 3900X exactly, but I wanna say it could do 4600MHz as well. This 5800X can also do it. I'll try to see how low I can get the primaries down to with this 5800X. All on the same 4400C19 1.4V 2x8GB kit.


----------



## MyUsername

nick name said:


> Ahhh. The 3900X I just had could POST 4600MHz but now I can't remember the timings. They were probably 18s at 2T. I can't remember my first 3900X exactly, but I wanna say it could do 4600MHz as well. This 5800X can also do it. I'll try to see how low I can get the primaries down to with this 5800X. All on the same 4400C19 1.4V 2x8GB kit.


And this one from six months ago, I just tried getting 2167 again and absolutely no, goes weird at 2100 now and that was stable before TM5 and benchmarks. I managed to get 5000M/Ts cl18 on this same kit on my 3900x


----------



## Blameless

Audioboxer said:


> Can anyone also explain how maxmem works? If you've got 2 sticks and 32GB is Windows using a total amount from both sticks or is it using all of the allowance on one stick first?


It's heavily interleaved, split per rank and per channel, based on the memory interleave size set by the firmware, which goes from 256 bytes to 2KiB.

This is transparent from the perspective of the OS and most software. You'd have to disable memory interleaving in the firmware to not have everything be as evenly distributed between ranks/channels as possible.


----------



## Audioboxer

Blameless said:


> It's heavily interleaved, split per rank and per channel, based on the memory interleave size set by the firmware, which goes from 256 bytes to 2KiB.
> 
> This is transparent from the perspective of the OS and most software. You'd have to disable memory interleaving in the firmware to not have everything be as evenly distributed between ranks/channels as possible.


Interesting, so it is indeed split. Good to know.

Not sure what to conclude from this about my tRCDRD 13 behaviour, almost makes me think it's the IMC rather than the memory.

As for high voltages working with maxmem I already know that's the PCB from others who use it to overclock to voltages like 2v.

What's interesting to note is it's around 12GB for both high voltage and tRCDRD I notice issues. So maybe it is just the memory can't handle tRCDRD 13 at 3800.

I guess I don't know enough about how tRCDRD works. Is it possible memory can run it lower with maxmem and fail at full capacity? Or is that a possible IMC issue?


----------



## Blameless

Using less than maximum capacity will probably result in lower memory temperatures and may be skipping an address range that contains weaker cells.


----------



## Audioboxer

Blameless said:


> Using less than maximum capacity will probably result in lower memory temperatures and may be skipping an address range that contains weaker cells.


I'm watercooled, my memory temps during TM5 and Karhu are like 31-33 degrees depending on ambient. Sometimes less.


----------



## howkey[cz]

Hey guys,

I am trying to stabilize FCLK 2000 with my 5800X, MSI B550 MEG UNIFY and G.SKILL F4-3200C14-8GTZ (2x8GB).

I am able to run it at FCLK 1900 without issues and the same timings. I am also able to boot with no issues with FCLK 1933 - 2000, no sound cracking, no other HW issues, no blue screens, just whea errors under some conditions (running aida L3 test) so I hope I am close to stabilize it 🙏

What helped me little bit (errors doesn't appear to often) was increasing VDDCR SOC Switching Frequency to 800Khz but higher values has no effects. Currently I have a plan to run it FCLK 1900 just to test if the memory at this frequency are running without issues and test 1:2 to test if the memory controller is causing the errors. But maybe I am just overlooking something? Any help will be appreciated  Thank you.


----------



## Audioboxer

Alright, so fun with 1.7v, tCL 12 and finding out tRCDRD 13 will run with maxmem aside, taking a look at 4000/2000 again. My prior look at it with semi-long mem testing was










The discovery being XMP settings will run fine and my overall PC despite lots of WHEA errors can run memory tests stable. Zero USB issues whilst memory is being tested. USB issues come when CPU is stability tested.










Just had a more proper look at 4000 14-14-14-14 there, still at 1.55v and confirmed something else I noticed a month ago, VDDG being too high hurts stability. Almost 1000 less WHEA errors same amount of time into the test with less CCD and IOD. This does nothing to help my USB issues when the CPU is getting hammered in OCCT or y-cruncher, but almost 1000 less WHEA 19, generally speaking, is a massive difference. I think it is VDDG CCD that makes the biggest difference, running it over 1v just seems to do far more _damage_ for FCLK 2000.

Also good to know while this bin is 4000 14-15-15-15 at 1.55v it could probably be sold as 4000 14-14-14-14 at 1.55v! I'm almost tempted to say **** it, and run this daily for a while and see if I get any USB issues during normal use. I've played some games briefly and it didn't result in USB issues despite the processor boosting. OCCT and y-cruncher weren't actually failing on CPU testing, I just ended up stopping them because when my USB ports went crazy it would keep screwing up my commander pro settings. Wasn't bothered about kb/m disconnecting, but the commander pro profile wiping is annoying.

Then again if I do run this I am breaking the #1 rule of overclocking, if it's not stable, it's not stable. USB flipping out is IF instability, no other way to cut it. Even if it does only end up happening under extreme CPU loads.


----------



## Audioboxer

Found something interesting! Finally a game on my Steam list which can quickly reproduce the mouse jerking issues I get when CPU stability testing, ESO. Elder Scrolls Online. They seemed to recently patch it for CPU multithreading support.

The interesting thing is not that I can reproduce the mouse jerking outwith CPU stability testing, it's what stopped it. Disabling a CCD  Yup, if I disable a CCD and pretend to be a 5900x, the jerking completely goes away. Tested for 25 minutes in game. Whereas with 2 CCDs the jerking can be reproduced as quickly as within 30 seconds of the gameplay starting.

Didn't seem to get any outright disconnects, but the mouse jerking obviously makes the system unusuable. As I'm using a wireless mouse I suspect its the first thing to be super sensitive to USB issues, possibly well before the point of mass USB disconnects.

Disabling a CCD doesn't stop mouse jerkiness during OCCT, but I presume that's just due to how hard OCCT hits the CPU. Difference with ESO is gaming is still quite a light workload, so dropping a CCD is probably enough for IF nonsense to stop messing with the USB.


----------



## howkey[cz]

howkey[cz] said:


> Hey guys,
> 
> I am trying to stabilize FCLK 2000 with my 5800X, MSI B550 MEG UNIFY and G.SKILL F4-3200C14-8GTZ (2x8GB).
> 
> I am able to run it at FCLK 1900 without issues and the same timings. I am also able to boot with no issues with FCLK 1933 - 2000, no sound cracking, no other HW issues, no blue screens, just whea errors under some conditions (running aida L3 test) so I hope I am close to stabilize it 🙏
> 
> What helped me little bit (errors doesn't appear to often) was increasing VDDCR SOC Switching Frequency to 800Khz but higher values has no effects. Currently I have a plan to run it FCLK 1900 just to test if the memory at this frequency are running without issues and test 1:2 to test if the memory controller is causing the errors. But maybe I am just overlooking something? Any help will be appreciated  Thank you.


So, FCLK 1900 with this timings seems to be stable so far. Running it 1:2 means less whea errors like 1/3


----------



## MyUsername

Audioboxer said:


> Found something interesting! Finally a game on my Steam list which can quickly reproduce the mouse jerking issues I get when CPU stability testing, ESO. Elder Scrolls Online. They seemed to recently patch it for CPU multithreading support.
> 
> The interesting thing is not that I can reproduce the mouse jerking outwith CPU stability testing, it's what stopped it. Disabling a CCD  Yup, if I disable a CCD and pretend to be a 5900x, the jerking completely goes away. Tested for 25 minutes in game. Whereas with 2 CCDs the jerking can be reproduced as quickly as within 30 seconds of the gameplay starting.
> 
> Didn't seem to get any outright disconnects, but the mouse jerking obviously makes the system unusuable. As I'm using a wireless mouse I suspect its the first thing to be super sensitive to USB issues, possibly well before the point of mass USB disconnects.
> 
> Disabling a CCD doesn't stop mouse jerkiness during OCCT, but I presume that's just due to how hard OCCT hits the CPU. Difference with ESO is gaming is still quite a light workload, so dropping a CCD is probably enough for IF nonsense to stop messing with the USB.


I find it strange we have almost identical systems yet they behave entirely different. 

I've disabled the whea suppressor and restarted before testing. This is the limit of what this pc can do, if I had better cooling on the cpu it can do 14000 on cpu-z. I really don't know what other knob to turn or button to flick to make it quicker.


----------



## nick name

Overnight run of 3800 14 14 1T GDM Off with a 2x8GB kit. 








Separately, BGS Alt versus BGS Enabled for those with 2x8GB kits. I recommend BGS Enabled for its performance. The bandwidth benefit is more obvious with a 3900X in Aida, but with benchmarks like the x265 Benchmark from HWBOT it really shines.


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## Audioboxer

MyUsername said:


> I find it strange we have almost identical systems yet they behave entirely different.
> 
> I've disabled the whea suppressor and restarted before testing. This is the limit of what this pc can do, if I had better cooling on the cpu it can do 14000 on cpu-z. I really don't know what other knob to turn or button to flick to make it quicker.
> 
> View attachment 2532380


That's just how it goes I guess, IF is a complete lottery per-chip. There will be some 5950x's that cannot even boot 2000 FCLK. I've never really used CPU-Z for benching, but here is how I can quickly illustrate an issue with FCLK 2000










FCLK 2000










FCLK 1900

Now I'm not familiar with this bench and I dunno if it's another like AIDA where background apps can eat into your score, but both of these are ran as-is, just with FCLK changing and some memory timings changing between 3800 and 4000.

Multi-thread is hammered on FCLK 2000, I guess because of WHEA performance regression/instability. I'd expect a VSOC of 1.2v at FCLK 2000 to eat into the power budget a bit, but not this much!!!

But hey you've given me something else to do at 1900, might need to look at my PBO settings given they're a fair bit behind yours! The assumption being at 1900/2000 this test should still be around the same? (meaning I should be capable of 700+ and around 13800 at 1900 FCLK?).

*edit* - Ran again at 1900 FCLK with some background apps closed and there maybe is a little bit of variance










But I'm still a good bit behind you. Windows 11 updates and the AMD chipset drivers were supposed to fix boosting and cache issues, so I doubt it's anything to do with that. I'll have a play with my PBO settings. Out of interest what do you run? Mines are just 270/160/190 at the moment.


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## jcpq

Windows 11


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## mongoled

Audioboxer said:


> That's just how it goes I guess, IF is a complete lottery per-chip. There will be some 5950x's that cannot even boot 2000 FCLK. I've never really used CPU-Z for benching, but here is how I can quickly illustrate an issue with FCLK 2000
> 
> View attachment 2532385
> 
> 
> FCLK 2000
> 
> View attachment 2532386
> 
> 
> FCLK 1900
> 
> Now I'm not familiar with this bench and I dunno if it's another like AIDA where background apps can eat into your score, but both of these are ran as-is, just with FCLK changing and some memory timings changing between 3800 and 4000.
> 
> Multi-thread is hammered on FCLK 2000, I guess because of WHEA performance regression/instability. I'd expect a VSOC of 1.2v at FCLK 2000 to eat into the power budget a bit, but not this much!!!
> 
> But hey you've given me something else to do at 1900, might need to look at my PBO settings given they're a fair bit behind yours! The assumption being at 1900/2000 this test should still be around the same? (meaning I should be capable of 700+ and around 13800 at 1900 FCLK?).
> 
> *edit* - Ran again at 1900 FCLK with some background apps closed and there maybe is a little bit of variance
> 
> View attachment 2532387
> 
> 
> But I'm still a good bit behind you. Windows 11 updates and the AMD chipset drivers were supposed to fix boosting and cache issues, so I doubt it's anything to do with that. I'll have a play with my PBO settings. Out of interest what do you run? Mines are just 270/160/190 at the moment.


Whats your PLL 1.8v reading ??

Sounds like you need to increase it.

Reckon if you run a LinpackXtreme test and compared the results you would see the same thing, i.e. performance tanks at 2000 FCLK.


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## Audioboxer

mongoled said:


> Whats your PLL 1.8v reading ??
> 
> Sounds like you need to increase it.
> 
> Reckon if you run a LinpackXtreme test and compared the results you would see the same thing, i.e. performance tanks at 2000 FCLK.


Uhhh, 1.86v IIRC, if that's the one MSI call "CPU 1P8" or whatever it is. Defaults to 1.8v.

Also have you messed about with maxmem before? [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread End up with some ridiculous timings. Biggest surprise was tRCDRD will run at 13 fine at 1.55v up to 9GB [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

Still scratching my head trying to understand why tRCDRD has been impacted by maxmem. Voltage I understand (PCB crashing), but not tRCDRD 13 running OK as long as half the memory is unused


----------



## mongoled

Audioboxer said:


> Uhhh, 1.86v IIRC, if that's the one MSI call "CPU 1P8" or whatever it is. Defaults to 1.8v.
> 
> Also have you messed about with maxmem before? [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread End up with some ridiculous timings. Biggest surprise was tRCDRD will run at 13 fine at 1.55v up to 9GB [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> Still scratching my head trying to understand why tRCDRD has been impacted by maxmem. Voltage I understand (PCB crashing), but not tRCDRD 13 running OK as long as half the memory is unused


Get it up to around 1.9v and see if the CPU-Z multicore test improves.

Nah, never played with it.

As to why, too many things are unknown to us to make a estimated guess, example we dont know how the reduced memory is allocated across the modules, example, is memory read sequentially across the total pool of available memory or does Windows somehow allocated the memory to say only 4 of the 8 ram modules ???


----------



## Audioboxer

mongoled said:


> Get it up to around 1.9v and see if the CPU-Z multicore test improves.
> 
> Nah, never played with it.
> 
> As to why, too many things are unknown to us to make a estimated guess, example we dont know how the reduced memory is allocated across the modules, example, is memory read sequentially across the total pool of available memory or does Windows somehow allocated the memory to say only 4 of the 8 ram modules ???


Yeah that's what I asked, a poster had a crack at answering that here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread



> It's heavily interleaved, split per rank and per channel, based on the memory interleave size set by the firmware, which goes from 256 bytes to 2KiB.
> 
> This is transparent from the perspective of the OS and most software. You'd have to disable memory interleaving in the firmware to not have everything be as evenly distributed between ranks/channels as possible.





> Using less than maximum capacity will probably result in lower memory temperatures and may be skipping an address range that contains weaker cells.


But obviously temperature is ruled out of the equation for me given being watercooled.

I guess my best guess would be one of my RAM modules can't handle tRCDRD 13 at 3800, but others can. Then again it was quite interesting to note high voltage tended to fail at around the same memory amount as running tRCDRD 13.

I'll play around with 1.9v and see. Funnily enough running the CPU-Z gets me that high pitched noise that sounds like VRMs having a hard time that I get from OCCT/y-cruncher with FCLK 2000. Well, it's my assumption it's VRMs, as I don't know what else would make a noise like that.


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## MyUsername

Audioboxer said:


> Out of interest what do you run? Mines are just 270/160/190 at the moment.


I've been playing with the CPU VDD SoC Current Optimization and got some interesting results. I use this to set the TDC and try and use this to limit total Amps allowed to the cpu cores. CPU load volts are about 1.3V, so 1.3V x 164ish Amps is about 214 Watts, any more and I hit 90'C fast and throttle. PPT and EDC are easy 1.3V x 200Amps(EDC+SoC) is 260Watts PPT, so I set cTDP and PLL the same 260Watts, I use these instead of PPT. The SoC full scale current is divided by 3 so it appears, so 90Amps would allow the SoC 30Watts, but setting to 30Amps(10 Amps actual)and using the telemetry to adjust up to what you want, I'm still monitoring it to see any benefits but it gives you control on the Amps you're allowing up to. You use the CPU telemetry the same, but keep an eye on the power reporting deviation. I use cinebench because this stresses the TDC and adjust the telemetry to get it to 100%ish. My PSU is reporting 306Watts on the 12V rail, minus 40Watts for the GPU looks about right.

Edit; PPT and EDC are TDC and SoC

I have no idea really what I'm doing and why it does this, but it works.


----------



## Audioboxer

MyUsername said:


> I've been playing with the CPU VDD SoC Current Optimization and got some interesting results. I use this to set the TDC and try and use this to limit total Amps allowed to the cpu cores. CPU load volts are about 1.3V, so 1.3V x 164ish Amps is about 214 Watts, any more and I hit 90'C fast and throttle. PPT and EDC are easy 1.3V x 200Amps(EDC+SoC) is 260Watts PPT, so I set cTDP and PLL the same 260Watts, I use these instead of PPT. The SoC full scale current is divided by 3 so it appears, so 90Amps would allow the SoC 30Watts, but setting to 30Amps(10 Amps actual)and using the telemetry to adjust up to what you want, I'm still monitoring it to see any benefits but it gives you control on the Amps you're allowing up to. You use the CPU telemetry the same, but keep an eye on the power reporting deviation. I use cinebench because this stresses the TDC and adjust the telemetry to get it to 100%ish. My PSU is reporting 306Watts on the 12V rail, minus 40Watts for the GPU looks about right.
> 
> I have no idea really what I'm doing and why it does this, but it works.
> 
> View attachment 2532395
> 
> View attachment 2532397
> 
> View attachment 2532398
> 
> View attachment 2532400


Oh boy, this is right up my street, a whole host of new BIOS settings I don't understand to mess about with!

Thanks for taking the time to explain what you do though, it is working, as apparent by your bench results. I assume you still have a curve setup?


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## MyUsername

Audioboxer said:


> Oh boy, this is right up my street, a whole host of new BIOS settings I don't understand to mess about with!
> 
> Thanks for taking the time to explain what you do though, it is working, as apparent by your bench results. I assume you still have a curve setup?


I'm done with the curve, one 16 core cycle is 8 hours. I stress both cores on heavyshort 4k-160k 30 minutes each. This has drove me nuts, why just why, got there now lol. Kind of glad I didn't get an all -30 cpu and gave me a challenge, I have a fast single core though 0 and 4. Not too bad.


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## Audioboxer

MyUsername said:


> I'm done with the curve, one 16 core cycle is 8 hours. I stress both cores on heavyshort 4k-160k 30 minutes each. This has drove me nuts, why just why, got there now lol. Kind of glad I didn't get an all -30 cpu and gave me a challenge, I have a fast single core though 0 and 4. Not too bad.
> View attachment 2532402
> 
> View attachment 2532403


Very similar to me, my four best cores range from 5 to 18. Most of the rest are OK at 30 or just below.


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## Dodgexander

Just had a stupid RR for the first time since I settled on stable settings, by this point I've changed so much I have no clue what it could be.

I enjoyed the ride but frankly it's getting a bit stupid now how you can test test test and yet a RR can hit you a month down the line. I just hope it keeps to once a month and not more.

Next time I'll be spending a bit more on proper QVL ram with a working XMP, heck I may even just not bother to overclock at all!


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## umea

What do you mean by RR?


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## Hibbing

umea said:


> What do you mean by RR?


Random Reboot.


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## Audioboxer

@MyUsername had a go with some of your settings and quite honestly results are about the same. Maybe MT a little higher into 135xx.

It's leading me to believe it's not so much my PBO settings, but possibly my curve. My allcore boost seems to get to 4.65ghz, which is decent for all cores on a 5950x, but I know some people get 4.7ghz. While my curve is 100% stable I was a bit lazy with it, as in, just find the lowest everything can go to and leave it there. If handled and benched core per core I dare say I might find the difference between a -30 and a -27 or a -17 and a -15 ends up with a better boost.

And there is always the chance you simply have a better binned chip!


----------



## mongoled

Using telemetry is a deep deep rabbit hole that changes almost every time there is change to the agesa.

Along with those changes, even if you manage to figure out some good settings, those settings may not run consistently when there is a change in ambient temperatures.

Also, when using telemetry, if you actually follow whats its doing and make comparisson between different telemetry settings you change you will find that where some settings look perfectly fine for benchmarks, if you load something that is AVX2 heavy, you may see that your all core overclock is reduced by 100-200 mhz when compared to no telemetry.

Finally got a new 3800/1900 24/7 config.









Think I may have another go at that leaderboard, for sure will not be able to hit the top spots with the stability tests ive run above, but seeing that almost every other entry in the table is no where near documenting the amount of stability I have with my previous entries will just post the most basic benchmarks as proof of stability ...


----------



## Audioboxer

mongoled said:


> Using telemetry is a deep deep rabbit hole that changes almost every time there is change to the agesa.
> 
> Along with those changes, even if you manage to figure out some good settings, those settings may not run consistently when there is a change in ambient temperatures.
> 
> Also, when using telemetry, if you actually follow whats its doing and make comparisson between different telemetry settings you change you will find that where some settings look perfectly fine for benchmarks, if you load something that is AVX2 heavy, you may see that your all core overclock is reduced by 100-200 mhz when compared to no telemetry.
> 
> Finally got a new 3800/1900 24/7 config.
> 
> View attachment 2532464
> 
> 
> Think I may have another go at that leaderboard, for sure will not be able to hit the top spots with the stability tests ive run above, but seeing that almost every other entry in the table is no where near documenting the amount of stability I have with my previous entries will just post the most basic benchmarks as proof of stability ...


Come catch me bro










Though it seems membench is quite like AIDA. I ran a bench before with these timings and it was 95.xx


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## mongoled

Audioboxer said:


> Come catch me bro
> 
> View attachment 2532465
> 
> 
> Though it seems membench is quite like AIDA. I ran a bench before with these timings and it was 95.xx


No chance! Not unless you turn your CPU into a 5600x and even then the clock speed difference ... 😆


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## PJVol

@Veii et al.
Managed to shave off 20mv from Vdimm and get VDDP back to 900mv.
But atm I found out that it's *critical* for the ClkDrvStr not to be below 60, otherwise #7's starts appearing from occasional to spamming, depending on ProcODT and Vdimm.
Changing Vdimm, ProcODT +/- one step alone less prone to cause instability. RRD's/FAW seem to have no significant impact either.
Can someone suggest RTT's applicable (if at all) ?


----------



## mongoled

So turned to BCLK again

 

maximum posting BCLK is 100.75 which is what the screenshot below is using, but if I disconnect the SATA drives in my system that limit will magically disappear.

Im thinking if I do a "black viper" on this benchOS that the 49.7ns can turn into 49.5ns, then a little tweaking of tRP/BCLK should be able to get to 49.3ns.

Not going to get the top spot but I aint using 2v for vDIMM

😂😂


----------



## nick name

Dodgexander said:


> Just had a stupid RR for the first time since I settled on stable settings, by this point I've changed so much I have no clue what it could be.
> 
> I enjoyed the ride but frankly it's getting a bit stupid now how you can test test test and yet a RR can hit you a month down the line. I just hope it keeps to once a month and not more.
> 
> Next time I'll be spending a bit more on proper QVL ram with a working XMP, heck I may even just not bother to overclock at all!


What settings are you running now?


----------



## Audioboxer

mongoled said:


> So turned to BCLK again
> 
> 
> 
> maximum posting BCLK is 100.75 which is what the screenshot below is using, but if I disconnect the SATA drives in my system that limit will magically disappear.
> 
> Im thinking if I do a "black viper" on this benchOS that the 49.7ns can turn into 49.5ns, then a little tweaking of tRP/BCLK should be able to get to 49.3ns.
> 
> Not going to get the top spot but I aint using 2v for vDIMM
> 
> 😂😂
> 
> View attachment 2532475


On this 1900/3800 profile the highest I can put BCLK is 100.25 lol. I have tested it with default BIOS config and 101, 102, etc work fine.

So I'm not sure if its the CPU/Memory or IF crapping out.


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## nick name

Audioboxer said:


> On this 1900/3800 profile the highest I can put BCLK is 100.25 lol. I have tested it with default BIOS config and 101, 102, etc work fine.
> 
> So I'm not sure if its the CPU/Memory or IF crapping out.


How close to the edge are you Curve Optimizer offsets?


----------



## mongoled

Audioboxer said:


> On this 1900/3800 profile the highest I can put BCLK is 100.25 lol. I have tested it with default BIOS config and 101, 102, etc work fine.
> 
> So I'm not sure if its the CPU/Memory or IF crapping out.


Hmm, i have not experienced that before, did you increase PLL 1.8v voltage ??

Last attempt for tonight, SuperPi 32M sub 6 mins


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## domdtxdissar

Some of my older scores from when i was running the (slower) 4x8gb set:








Like pretty much all benchmarks, cpu mhz is still king 😇


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## Dodgexander

nick name said:


> What settings are you running now?


These:
[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread | Page 696 | Overclock.net


----------



## domdtxdissar

domdtxdissar said:


> Some of my older scores from when i was running the (slower) 4x8gb set:
> View attachment 2532496
> 
> 
> Like pretty much all benchmarks, cpu mhz is still king 😇
> View attachment 2532499


New run from today with my regular gaming OS install


----------



## nick name

Dodgexander said:


> These:
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread | Page 696 | Overclock.net


I would try increasing one of these by 1 and see if you get the reboot. If it does then increase the other by 1 and wait for a reboot. 

tWTRS 3>4
tRTP 5>6

And if that doesn't work then try the SCLs 2>3.

I recommend tWTRS because I've found that when I forgot to set this to 4 when setting up my RAM it ends up causing problems.

I recommend tRTP because I don't recall seeing many (I really can't remember any) running that low at higher speeds and reporting 24/7 stability.

And the SCLs I recommended last because I've passed RAM tests with 2s set, but get weird pop-ins of player models in CSGO on Dust II at top-mid. Instead of seeing a player model run across the screen the model just appears. So 2s seem to test fine, but there are some things that don't like it that low.


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## MyUsername

Audioboxer said:


> @MyUsername had a go with some of your settings and quite honestly results are about the same. Maybe MT a little higher into 135xx.
> 
> It's leading me to believe it's not so much my PBO settings, but possibly my curve. My allcore boost seems to get to 4.65ghz, which is decent for all cores on a 5950x, but I know some people get 4.7ghz. While my curve is 100% stable I was a bit lazy with it, as in, just find the lowest everything can go to and leave it there. If handled and benched core per core I dare say I might find the difference between a -30 and a -27 or a -17 and a -15 ends up with a better boost.
> 
> And there is always the chance you simply have a better binned chip!


I've spent a lot of time messing around with the curve figuring out how it works, I've now pushed the core clocks as high as they'll go. Watching hwinfo while corecycler is running with two threads, CCD0 will boost worst to best core 4930 to 4990MHz, CCD1 4725-4810MHz. PBO gives me an extra 520-840 MT cpu-z points for an extra 100 Watt, 12980 CO stock PBO and 13828 CO+PBO fans 100% side panel off, fans on silent with the panel on I get 13600-650ish depending how warm my pc is, with an AC unit though I can get 14010 cpu-z and 12000 CB20. It's a lot of trial and error. I'm playing through Cyberpunk again, with afterburner the cpu clock is 4950MHz constant with a flicker of 5000MHzat about 180 Watts 64'C. CPU VDD optimization does push the cpu harder, I don't know why does it, all I know is the Volts, Amps and Watts and cpu temp look okay. My all core boost depending what on and temperature can vary 4500-4700MHz, my Noctua D15 has it's limits, good air cooler.


----------



## KedarWolf

MyUsername said:


> I've spent a lot of time messing around with the curve figuring out how it works, I've now pushed the core clocks as high as they'll go. Watching hwinfo while corecycler is running with two threads, CCD0 will boost worst to best core 4930 to 4990MHz, CCD1 4725-4810MHz. PBO gives me an extra 520-840 MT cpu-z points for an extra 100 Watt, 12980 CO stock PBO and 13828 CO+PBO fans 100% side panel off, fans on silent with the panel on I get 13600-650ish depending how warm my pc is, with an AC unit though I can get 14010 cpu-z and 12000 CB20. It's a lot of trial and error. I'm playing through Cyberpunk again, with afterburner the cpu clock is 4950MHz constant with a flicker of 5000MHzat about 180 Watts 64'C. CPU VDD optimization does push the cpu harder, I don't know why does it, all I know is the Volts, Amps and Watts and cpu temp look okay. My all core boost depending what on and temperature can vary 4500-4700MHz, my Noctua D15 has it's limits, good air cooler.
> View attachment 2532512


That is a really great score. I was happy to get 11865.

What's your EDC, PPT and Scaler etc?

All my cores are at 30 except the top two at 7 and 15.

Edit: Fun fact: This with a static CCX overclock a few months ago.


----------



## Dodgexander

nick name said:


> I would try increasing one of these by 1 and see if you get the reboot. If it does then increase the other by 1 and wait for a reboot.
> 
> tWTRS 3>4
> tRTP 5>6
> 
> And if that doesn't work then try the SCLs 2>3.
> 
> I recommend tWTRS because I've found that when I forgot to set this to 4 when setting up my RAM it ends up causing problems.
> 
> I recommend tRTP because I don't recall seeing many (I really can't remember any) running that low at higher speeds and reporting 24/7 stability.
> 
> And the SCLs I recommended last because I've passed RAM tests with 2s set, but get weird pop-ins of player models in CSGO on Dust II at top-mid. Instead of seeing a player model run across the screen the model just appears. So 2s seem to test fine, but there are some things that don't like it that low.


Thanks. I'll give this a go. Will take a long time since these don't seem to happen very often.


----------



## mongoled

domdtxdissar said:


> New run from today with my regular gaming OS install
> View attachment 2532508


Can you limit your boost to just 4900 mhz so we can get a direct comparison between your 3800/1900 vs my 4108/2054 timings.

My 5600x can only boost to 4900 mhz.

Going to need tCL @13 to be able to have a chance of reaching 49ns ....


----------



## Blameless

ManniX-ITA said:


> Yeah not close as hot but still it does get warm.
> It's like putting a thick duvet over someone already sweating in summer under the sun
> For sure it will reduce the thermal dissipation of the cores.
> Considering some parts are already hitting over 100c, I wonder how well it'll be managed.
> I'm inclined to think as well the improved process will counter balance the worse thermals and the FCLK will probably end up the same.


Not worried about cache temps at all. New version of HWiFO can read the L3 temp sensor and with the heaviest loads (Prime95 AVX2/FMA3 240K in-place FFTs) I can fit within the CCD's thermal limits (~172w) on my current cooling, the peak L3 of my 5800X is a full 31C colder than my coolest running core.









AMD should have a solid ~25C margin to play with when stacking cache.

Core temps, or at least relative thermal resistance for the cores, with the new parts are the big question.

On a side note, just lapping this CPU improved the clocks PBO would hold in Prime95 by 100MHz, and it was one of my flatter out-of-box samples.




Audioboxer said:


> That's just how it goes I guess, IF is a complete lottery per-chip. There will be some 5950x's that cannot even boot 2000 FCLK. I've never really used CPU-Z for benching, but here is how I can quickly illustrate an issue with FCLK 2000
> 
> View attachment 2532385
> 
> 
> FCLK 2000
> 
> View attachment 2532386
> 
> 
> FCLK 1900
> 
> Now I'm not familiar with this bench and I dunno if it's another like AIDA where background apps can eat into your score, but both of these are ran as-is, just with FCLK changing and some memory timings changing between 3800 and 4000.
> 
> Multi-thread is hammered on FCLK 2000, I guess because of WHEA performance regression/instability. I'd expect a VSOC of 1.2v at FCLK 2000 to eat into the power budget a bit, but not this much!!!
> 
> But hey you've given me something else to do at 1900, might need to look at my PBO settings given they're a fair bit behind yours! The assumption being at 1900/2000 this test should still be around the same? (meaning I should be capable of 700+ and around 13800 at 1900 FCLK?).
> 
> *edit* - Ran again at 1900 FCLK with some background apps closed and there maybe is a little bit of variance
> 
> View attachment 2532387
> 
> 
> But I'm still a good bit behind you. Windows 11 updates and the AMD chipset drivers were supposed to fix boosting and cache issues, so I doubt it's anything to do with that. I'll have a play with my PBO settings. Out of interest what do you run? Mines are just 270/160/190 at the moment.


CPU-Z bench is almost purely boost clock limited and thus super temperature dependent. SoC power doesn't matter a whole lot, unless PPT is your limiting factor...the IOD is far enough away and cool running enough that it almost never heats the cores appreciably.

Your results at 2000FCLK are pretty interesting as it hints at far more inter-core communication than I would have expected, or some sort of throttling that isn't explicitly visible.


----------



## blodflekk

I know the DRAM calcuator was made for ryzen 3000 and older, but how accurate are its voltage recommendations for Ryzen 5000 ? Are they a good starting point? are they safe?


----------



## mongoled

Flat 14s

 

Needs some tweaking (Linpack failing ..), hopefully its just Rtts that require adjustments as im heading into 1.75v vDIMM territory


----------



## Audioboxer

mongoled said:


> Flat 14s
> 
> 
> 
> Needs some tweaking (Linpack failing ..), hopefully its just Rtts that require adjustments as im heading into 1.75v vDIMM territory
> 
> View attachment 2532576


So no need to use maxmem at 1.75v? As I discussed earlier unless I limit to like 9GB I get Karhu failing at 1.75v.



Blameless said:


> Not worried about cache temps at all. New version of HWiFO can read the L3 temp sensor and with the heaviest loads (Prime95 AVX2/FMA3 240K in-place FFTs) I can fit within the CCD's thermal limits (~172w) on my current cooling, the peak L3 of my 5800X is a full 31C colder than my coolest running core.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> AMD should have a solid ~25C margin to play with when stacking cache.
> 
> Core temps, or at least relative thermal resistance for the cores, with the new parts are the big question.
> 
> On a side note, just lapping this CPU improved the clocks PBO would hold in Prime95 by 100MHz, and it was one of my flatter out-of-box samples.
> 
> 
> 
> 
> CPU-Z bench is almost purely boost clock limited and thus super temperature dependent. SoC power doesn't matter a whole lot, unless PPT is your limiting factor...the IOD is far enough away and cool running enough that it almost never heats the cores appreciably.
> 
> Your results at 2000FCLK are pretty interesting as it hints at far more inter-core communication than I would have expected, or some sort of throttling that isn't explicitly visible.


I get the weird whining noise at FCLK 2000 when running CPU-Z, something I haven't seen anyone else report on. It's a noise I get if the CPU is under heavy loads. Doesn't happen when playing a game but things like OCCT/y-cruncher or CPU-Z cause the noise.

My best guess is its the B550 VRM, but I wouldn't know why I'm getting such a noise at FCLK 2000 over 1900. I doubt it's a USB device, well, it's definitely not keyboard or mouse, noise is coming from inside the case. I guess I can check if it's the Corsair commander pro of all things. As my USB issues start with a heavy USB load I can't really rule that out till I open the back of my case and see if it's making the whining noise.

AMD look like they're gearing up for a new AGESA AMD Releases Updated Zen 3 CPU Microcode (November 2021) - Phoronix So lets hope it's not just security fixes...


----------



## ManniX-ITA

Blameless said:


> Not worried about cache temps at all. New version of HWiFO can read the L3 temp sensor and with the heaviest loads (Prime95 AVX2/FMA3 240K in-place FFTs) I can fit within the CCD's thermal limits (~172w) on my current cooling, the peak L3 of my 5800X is a full 31C colder than my coolest running core.


Juicy, didn't see the L3 temp sensor!
I hope it's not going to be a problem the cache stacking.
But I'm not so confident like you, the cache it's vertically stacked.
There's no positive 25c margin from how I see it, there's an hot 53c layer which will pile up to the core temperatures.
More likely a negative 53c margin


----------



## MyUsername

I had to disable most of my cpu to get to similar numbers, here it is

4 cores, 8 threads
















6 cores, 12 threads


----------



## Luggage

domdtxdissar said:


> New run from today with my regular gaming OS install
> View attachment 2532508


Bah! And here I was happy to beat your old score with my lowly 2T and 5800x 



http://imgur.com/a/CBoW2bm


Perhaps if I can get 1T benchable and load a <1200 agesa for higher boost


----------



## mongoled

Audioboxer said:


> So no need to use maxmem at 1.75v? As I discussed earlier unless I limit to like 9GB I get Karhu failing at 1.75v.
> 
> AMD look like they're gearing up for a new AGESA AMD Releases Updated Zen 3 CPU Microcode (November 2021) - Phoronix So lets hope it's not just security fixes...


Nah, not going to use any hacks just to get a "pass", so I have not tried it.



Was wondering regards agesa 1.2.0.4 as its gone AWOL, hopefully this time we see some meaningful positive changes!



MyUsername said:


> I had to disable most of my cpu to get to similar numbers, here it is
> 
> 4 cores, 8 threads
> View attachment 2532580
> 
> View attachment 2532582
> 
> 6 cores, 12 threads
> View attachment 2532581





Luggage said:


> Bah! And here I was happy to beat your old score with my lowly 2T and 5800x
> 
> 
> 
> http://imgur.com/a/CBoW2bm
> 
> 
> Perhaps if I can get 1T benchable and load a <1200 agesa for higher boost


Can any of you run these with CPU at max boost speed 4900 mhz and post the results ?


----------



## domdtxdissar

mongoled said:


> Nah, not going to use any hacks just to get a "pass", so I have not tried it.
> 
> 
> 
> Was wondering regards agesa 1.2.0.4 as its gone AWOL, hopefully this time we see some meaningful positive changes!
> 
> 
> 
> Can any of you run these with CPU at max boost speed 4900 mhz and post the results ?


will do a run @ 4900 when i get home from work


----------



## Audioboxer

lol, if I close iCUE it stops 15 processes. Junk software. This is _with_ disabling Corsair Gaming Audio Configuration Service, cause you know, when you install watercooling components you need Corsair headset services...

Even with some pruning on Windows 11 I still struggle to get down as low as 119 processes. I guess I would need to be more brave closing off services. Though I've already discovered that I can't use my office packages without click to run, running. What is it with MS and bloat... I shouldn't need a background service running to open Word, Excel and Powerpoint when I need them!


----------



## domdtxdissar

mongoled said:


> Can you limit your boost to just 4900 mhz so we can get a direct comparison between your 3800/1900 vs my 4108/2054 timings.
> 
> My 5600x can only boost to 4900 mhz.
> 
> Going to need tCL @13 to be able to have a chance of reaching 49ns ....
> 
> 
> 
> View attachment 2532573


With all memory enabled:


----------



## Blameless

ManniX-ITA said:


> There's no positive 25c margin from how I see it, there's an hot 53c layer which will pile up to the core temperatures.


It's the hottest, hardest to cool, highest thermal density, areas that are the limiting factor. That's not likely to be the cache, even with three or more vertically stacked layers.



mongoled said:


> Can any of you run these with CPU at max boost speed 4900 mhz and post the results ?


You guys should probably be using a fixed OC to compare memory/FCLK in SuperPi...PBO may well not boost the same way on different samples in different systems, even when capped to the same peak boost clock.


----------



## mongoled

Blameless said:


> You guys should probably be using a fixed OC to compare memory/FCLK in SuperPi...PBO may well not boost the same way on different samples in different systems, even when capped to the same peak boost clock.


Its just a rough comparison seeing we are using completely different MCLK/FCLK/Timings combinations.

I just wanted to see how much the difference is because of CPU frequency and yes its not an ideal way to compare, but there is no way on earth that a 5600x is going to boost to 5050-5100 on these newer BIOS's


----------



## mongoled

domdtxdissar said:


> With all memory enabled:
> View attachment 2532613


Thanks!

Thats great, the 5600x is in the ball park, good to confirm


----------



## Audioboxer

Never used SuperPI before, is there a reason the modded 1.5 is used over the website being at 1.9?










Looks like I have some work to do on my CPU! My memory is great, but my 5950x really seems to be lagging a bit behind others.


----------



## domdtxdissar

Luggage said:


> Bah! And here I was happy to beat your old score with my lowly 2T and 5800x
> 
> 
> 
> http://imgur.com/a/CBoW2bm
> 
> 
> Perhaps if I can get 1T benchable and load a <1200 agesa for higher boost


Since your hunting me i had to do a new run 








But it dont think windows11 is the best to do superpi runs in.. Win10 seems faster for Zen3


----------



## mongoled

Audioboxer said:


> Never used SuperPI before, is there a reason the modded 1.5 is used over the website being at 1.9?
> 
> View attachment 2532623
> 
> 
> Looks like I have some work to do on my CPU! My memory is great, but my 5950x really seems to be lagging a bit behind others.


What core is it pegging? Run it with Hwinfo64 open and see. It should be targeting your fastest core

ZenTimings screenshot? 

That time is abysmal

😬


----------



## MyUsername

mongoled said:


> Nah, not going to use any hacks just to get a "pass", so I have not tried it.
> 
> 
> 
> Was wondering regards agesa 1.2.0.4 as its gone AWOL, hopefully this time we see some meaningful positive changes!
> 
> 
> 
> Can any of you run these with CPU at max boost speed 4900 mhz and post the results ?


4900 OC, 6 cores. Brings superpi a bit closer to you. Linpack just locks up the pc.


----------



## Luggage

domdtxdissar said:


> Since your hunting me i had to do a new run
> View attachment 2532634
> 
> But it dont think windows11 is the best to do superpi runs in.. Win10 seems faster for Zen3





http://imgur.com/a/tZTbZzY


Well I can’t do 21Ghz stable


----------



## PJVol

Audioboxer said:


> Now I'm not familiar with this bench and I dunno if it's another like AIDA where background apps can eat into your score


Lower than expected single core in CPU-Z and other benchmarks usually points to heavy throttle*.
Here I made three runs of benches, one 1900 fclk and two 2000 fclk (vdd18 auto and 2V to prevent throttling)








Usually AIDA Photoworxx test or Corona is a good marker of performance regression due to fabric issues. Heavy throttling is mostly mitigated by pushing vdd18 to 2.0V in my config.
But the most annoying is on the edge case IF OC, the voltage training is becoming an issue:
1st set of results in Photoworxx, CB R15 and Corona were made when DF BIST was trained with clear throttle thresholds being set.
2nd scores were made by randomly changing any of the on-chip LDO Vref (i just switched CCD from 950 to 1000mv and back) for successive training.
So don't hesitate to check Photoworkxx score with IF OC'ed, its fast and mostly accurate in diagnosing fabric issues.

As a side note:
for me perssonally, this training hell is actually the main reason not to go higher than 1900 fclk 24/7 setup. Though, it may not be the case with another hw config, since sample quality and a certain MB design matters most. And IMHO the latter is even more important, specifically mb VRM design.
Since it's part of the whole PDN for the CPU you can only imagine, how it's slightest deviation from power delivery specs (i.e. voltage ramping speed, output voltage ripple or high switch delays that are typical for doubler-based VRM topology) can affect myriads of CLDOs and DLDOs inside Ryzen CPU package.

-----------------------------
* AFAIK, all throttling functionality in Ryzen implemented via the so called EDC-throttler, be it CPU cores or L3 cache or DF domain. They all have their own throttler and a corresponding thresholds set at BIST, so in edge OC cases it may be activated both statically and dynamically.
David Suggs et al, The AMD “Zen 2” Processor


> "To optimize performance, Zen2 builds an intelligent EDC manager which monitors activity over multiple clock cycles and throttles execution only when necessary"





Blameless said:


> It's the hottest, hardest to cool, highest thermal density, areas that are the limiting factor. That's not likely to be the cache, even with three or more vertically stacked layers.


Perhaps it's most likely SIMD FP/Vector units. Have seen it mentioned a couple of times as a clock-gated wide super-scalar execution units.


----------



## ManniX-ITA

PJVol said:


> It would be nice, if someone share this short article by Zen2's father in PDF (it's behind the paywall or institutional account)


It's just a matter of googling for scihub


----------



## Audioboxer

mongoled said:


> What core is it pegging? Run it with Hwinfo64 open and see. It should be targeting your fastest core
> 
> ZenTimings screenshot?
> 
> That time is abysmal
> 
> 😬












Memory profile hasn't changed for ages, it benches fine in AIDA64.

I tried turning off PBO, well, I set it to AUTO which IIRC goes to default and removes the curve and as expected the result is even worse lol










Before I turn PBO back on to check what core it is targetting is anyone else running Super PI with Windows 11?

I have read people say they're still getting poor performance and/or the newest AMD chipset drivers are worse on Windows 11 (the ones MSI/ASUS have released before AMD).



PJVol said:


> Lower than expected single core in CPU-Z and other benchmarks usually points to heavy throttle*.
> Here I made three runs of benches, one 1900 fclk and two 2000 fclk (vdd18 auto and 2V to prevent throttling)
> View attachment 2532665
> 
> Usually AIDA Photoworxx test or Corona is a good marker of performance regression due to fabric issues. Heavy throttling is mostly mitigated by pushing vdd18 to 2.0V in my config.
> But the most annoying is on the edge case IF OC, the voltage training is becoming an issue:
> 1st set of results in Photoworxx, CB R15 and Corona were made when DF BIST was trained with clear throttle thresholds being set.
> 2nd scores were made by randomly changing any of the on-chip LDO Vref (i just switched CCD from 950 to 1000mv and back) for successive training.
> So don't hesitate to check Photoworkxx score with IF OC'ed, its fast and mostly accurate in diagnosing fabric issues.
> 
> As a side note:
> for me perssonally, this training hell is actually the main reason not to go higher than 1900 fclk 24/7 setup. Though, it may not be the case with hw config, since sample quality and a certain MB design matters most. And IMHO the latter is even more important, specifically mb VRM design.
> Since it's part of the whole PDN for the CPU you can only imagine, how it's slightest deviation from power delivery specs (i.e. voltage ramping speed, output voltage ripple or high switch delays that are typical for doubler-based VRM topology) can affect myriads of CLDOs and DLDOs inside Ryzen CPU package.
> 
> -----------------------------
> * AFAIK, all throttling functionality in Ryzen implemented via the so called EDC-throttler, be it CPU cores or L3 cache or DF domain. They all have their own throttler and a corresponding thresholds set at BIST, so in edge OC cases it may be activated both statically and dynamically.
> It would be nice, if someone share this short article by Zen2's father in PDF (it's behind the paywall or institutional account)
> The AMD “Zen 2” Processor
> where it was refered as the "Intelligent EDC manager which monitors activity ...and throttles execution only when necessary"


Funnily enough it is my MT score which tanks with IF at 2000, not so much ST. I have tried up to around 2.0v on CPU 1.8. I just think while I can boot it and I don't get "too much" WHEA 19 spam, my CPU is just unstable as frick when under a heavy load with FCLK 2000.


----------



## PJVol

ManniX-ITA said:


> It's just a matter of googling for scihub


Couldn't find it in Scribd


Audioboxer said:


> Funnily enough it is my MT score which tanks with IF at 2000, not so much ST


ST didn't suffer much, due to it's low power nature, in my example drop was in a 1%, though noticable enough to pay attention.
As for MT - don't see how does it differ from what I described?
Vdd18 may not "work" at all in some cases (at least not at the same degree as in my case), especially on boards, having mostly true-phase or twin split vrm design. 
There is enough owners of 2ccd down-binned samples as well, run stable up to 2100 fclk.


----------



## Audioboxer

PJVol said:


> Couldn't find it in Scribd
> 
> ST didn't suffer much, due to it's low power nature, in my example drop was in a 1%, though noticable enough to pay attention.
> *As for MT - don't see how does it differ from what I described?*


Oh, it probably doesn't, I was just adding it's my MT score that tanks lol. The score I get is as if PBO is turned off. 117xx is around what I get without PBO, 13xxx is what I get with PBO on. It's as if when I have FCLK 2000 PBO just... breaks? You're probably 100% right in normal circumstances CPU 1.8 up to 2.0v will help most people, but it didn't seem to help me. I think my CPU just can't handle the IF at 2000 on heavy CPU loads 

@mongoled Interesting observation










Super PI seems to peg to Core 5 95% of the time. Core 2 is my best. Occassionally throughout the run it seemed as if it wanted to use Core 2, but it kept using Core 5.

Not sure what this tells me? Is it possible Windows 11 core scheduling is still broken? I'm going to revert to the AMD chipset drivers AMD have officially released and check. I would also ask does it mean Core 2 is unstable? But this core has had like 16 hours of corecycler lol. Never get any idle reboots or anything either.

@domdtxdissar Just noticed you are using Windows 11, what AMD chipset drivers are you using? 3.10.22.706?


----------



## PJVol

ManniX-ITA said:


> It's just a matter of googling for scihub


Oh, nice hub, haven't heard of it before  Found it there...


----------



## ManniX-ITA

Audioboxer said:


> Super PI seems to peg to Core 5 95% of the time. Core 2 is my best. Occassionally throughout the run it seemed as if it wanted to use Core 2, but it kept using Core 5.


I think with benchmate you can set the affinity.

Keep in mind that VDD18 over 1.9V on a 5950X is extremely heavy on thermals, mine starts throttling above it.
Did you check the temperatures?


----------



## domdtxdissar

Luggage said:


> http://imgur.com/a/tZTbZzY
> 
> 
> Well I can’t do 21Ghz stable


Standard (hwinfo) readout bug when more than 1 app tries to access SMU at the same time 



> @domdtxdissar Just noticed you are using Windows 11, what AMD chipset drivers are you using? 3.10.22.706?


Yes, gotten from Asus motherboard site


----------



## Audioboxer

ManniX-ITA said:


> I think with benchmate you can set the affinity.
> 
> Keep in mind that VDD18 over 1.9V on a 5950X is extremely heavy on thermals, mine starts throttling above it.
> Did you check the temperatures?


Of my CPU? Won't be that I've got a 4 rad loop and in the UK ambient temp is freezing right now lol. For example, I'm sitting at 32 degrees idle at the moment lol. Water temp 24 degrees, memory temp 25~26 degrees across both DIMMs.

I barely get into the 70s on heavy loads, most of the time I'm somewhere between 50~6x degrees. Prime95 stuff can hit about 80~82 degrees IIRC.

VDD18 is normally set at 1.83v, which because it's MSI and they love to add on voltage, registers at 1.86v in HWINFO. The only time I've gone to 1.9v and just over is when trying to stabilise 2000 FCLK.

I googled Benchmate and it looks pretty cool, will download the package!


----------



## ManniX-ITA

Audioboxer said:


> The only time I've gone to 1.9v and just over is when trying to stabilise 2000 FCLK.


Optimizing VDD18 it's very tricky; if you have the AMD PBS menu on MSI you can set also an offset with a 1 mV granularity.
For me at FCLK 2000 is best set at 1.81V and a negative offset of 30 mV which reads 1.844V in HWInfo.
While at FCLK 1900 was best set at 1.83V.
Going up was worse or same; there was a nice spot above 1.97V but at that point the temps were out of control in all-core.
Your sample really likes low voltages, very likely for VDD as well.
But if you want to test, you really need to check every step.


----------



## PJVol

domdtxdissar said:


> Standard readout bug when more than 1 app tries to access SMU at the same time


Regarding the current or effective clock readout, it may be due to constraints were not met described in PRR, even without explicitly concurrent SMU requests, since there are corresponding MSR's for that purpose.


----------



## Audioboxer

ManniX-ITA said:


> Optimizing VDD18 it's very tricky; if you have the AMD PBS menu on MSI you can set also an offset with a 1 mV granularity.
> For me at FCLK 2000 is best set at 1.81V and a negative offset of 30 mV which reads 1.844V in HWInfo.
> While at FCLK 1900 was best set at 1.83V.
> Going up was worse or same; there was a nice spot above 1.97V but at that point the temps were out of control in all-core.
> Your sample really likes low voltages, very likely for VDD as well.
> But if you want to test, you really need to check every step.


Thanks, I do have the unlocked BIOS but I had no idea there was that level of minimal increase.

I dare say there might be a combination which gets me going at FCLK 2000 outside of just being able to do memory benching, but it's obviously going to take a lot of effort.

My biggest concern is the whirring/whining noise I get that I haven't seen anyone else report. Only happens under heavy CPU loads. It's either VRMs or its something else I haven't diagnosed yet. The USB disconnects at least I know are common, but the noise isn't lol. Mouse jerking seems to be something other people have had as well, a symptom of USB issues and/or throttling.

Just for the record I've never heard any noise at 1900 FCLK no matter what benching or stability testing I've done. Might see if I can record it and upload for an opinion. It's quite high pitched.


----------



## Luggage

Audioboxer said:


> Thanks, I do have the unlocked BIOS but I had no idea there was that level of minimal increase.
> 
> I dare say there might be a combination which gets me going at FCLK 2000 outside of just being able to do memory benching, but it's obviously going to take a lot of effort.
> 
> My biggest concern is the whirring/whining noise I get that I haven't seen anyone else report. Only happens under heavy CPU loads. It's either VRMs or its something else I haven't diagnosed yet. The USB disconnects at least I know are common, but the noise isn't lol. Mouse jerking seems to be something other people have had as well, a symptom of USB issues and/or throttling.
> 
> Just for the record I've never heard any noise at 1900 FCLK no matter what benching or stability testing I've done. Might see if I can record it and upload for an opinion. It's quite high pitched.


Check unify-x thread… some coil whine reports


----------



## ManniX-ITA

Audioboxer said:


> Just for the record I've never heard any noise at 1900 FCLK no matter what benching or stability testing I've done.


It's weird if it's coil whine you should hear it at 1900 as well.
I have quite some and it's the same whatever FCLK is set.
About the USB for me is the opposite.
Recurring random issues at FCLK 1900 and close to perfect at 2000.


----------



## ManniX-ITA

Audioboxer said:


> Thanks, I do have the unlocked BIOS but I had no idea there was that level of minimal increase.


Ah, you have a Unify-X as well, I forgot.
I bet a cent that if you go back to A21O the USB will work perfectly


----------



## Audioboxer

Luggage said:


> Check unify-x thread… some coil whine reports


That's my thinking, but why I only get it at FCLK 2000 I don't know. I genuinely have no audible noise at all off the VRM at 1900. It was one of my biggest worries getting a B550 Unify X lol.

I presume the VRMs are getting worked harder at 2000 FCLK.



ManniX-ITA said:


> It's weird if it's coil whine you should hear it at 1900 as well.
> I have quite some and it's the same whatever FCLK is set.
> About the USB for me is the opposite.
> Recurring random issues at FCLK 1900 and close to perfect at 2000.


Yeah, I definitely don't hear it at 1900. My 2080Ti sounds like a damn bee with power 123% and an overclock. But this sound isn't like the buzzing of a graphics card, it's more like a high pitched whine or squeal.

And yeah, welcome to AMD I guess. Random USB issues all over the place with a lack of consistency and multiple failed attempts to fix them.


----------



## Audioboxer

ManniX-ITA said:


> Ah, you have a Unify-X as well, I forgot.
> I bet a cent that if you go back to A21O the USB will work perfectly


Don't tempt me lol

I'm holding out for the next AGESA as it is. If I go back that far I bet I have to redo my memory overclocking as well 🤣


----------



## MyUsername

Audioboxer said:


> My biggest concern is the whirring/whining noise I get that I haven't seen anyone else report. Only happens under heavy CPU loads. It's either VRMs or its something else I haven't diagnosed yet. The USB disconnects at least I know are common, but the noise isn't lol. Mouse jerking seems to be something other people have had as well, a symptom of USB issues and/or throttling.
> 
> Just for the record I've never heard any noise at 1900 FCLK no matter what benching or stability testing I've done. Might see if I can record it and upload for an opinion. It's quite high pitched.


Same here, up to 1900 it's fairly quiet you might hear a little chirp with Aida L3 cache benchmarks etc, but yeah, 2000Fclk it's noticeable. I'm sure it means scream if you want to go faster!


----------



## ManniX-ITA

MyUsername said:


> Same here, up to 1900 it's fairly quiet you might hear a little chirp with Aida L3 cache benchmarks etc, but yeah, 2000Fclk it's noticeable. I'm sure it means scream if you want to faster!


Thanks for the reports, didn't know it could change with FCLK speed.
My Unify-X squeaks always the same 

@Audioboxer did you try to enable CLKREQ# at FCLK 2000?


----------



## MyUsername

ManniX-ITA said:


> Thanks for the reports, didn't know it could change with FCLK speed.
> My Unify-X squeaks always the same
> 
> @Audioboxer did you try to enable CLKREQ# at FCLK 2000?


I've seen you mention CLKREQ# a few times. What is this suppose to help? I've looked it up, and it's a power saving feature on the PCIe linkstates L0 to L4, helpful with mobile devices to save battery or disconnected from mains power. For me I can't see power saving being helpful as my PCIe is fully loaded with four M.2s and a GPU @x8, all my 24 lanes are used.


----------



## ManniX-ITA

MyUsername said:


> I've seen you mention CLKREQ# a few times. What is this suppose to help? I've looked it up, and it's a power saving feature on the PCIe linkstates L0 to L4, helpful with mobile devices to save battery or disconnected from mains power. For me I can't see power saving being helpful as my PCIe is fully loaded with four M.2s and a GPU @x8, all my 24 lanes are used.


Can't say for sure what it does, AMD's use inside the die is for sure different than on PCIe 
It's an additional clock reference signal and it does help the fabric sync when there's high load.
When I've tested with the monero miner I found out, for the first time, there was a performance regression under peak load.
With CLKREQ# enabled no more regression, scaling up also with the miner.
The helping effect changes with different FCLK speeds and AGESA versions.


----------



## MyUsername

ManniX-ITA said:


> Can't say for sure what it does, AMD's use inside the die is for sure different than on PCIe
> It's an additional clock reference signal and it does help the fabric sync when there's high load.
> When I've tested with the monero miner I found out, for the first time, there was a performance regression under peak load.
> With CLKREQ# enabled no more regression, scaling up also with the miner.
> The helping effect changes with different FCLK speeds and AGESA versions.


There has to be an easier way than using a miner to see regression? What a faff setting that up, I never wanted to mine so bit of a learning curve here, but if you reckon that's the best way to see regression, I'll give it a go to get a number LOL


----------



## ManniX-ITA

MyUsername said:


> There has to be an easier way than using a miner to see regression? What a faff setting that up, I never wanted to mine so bit of a learning curve here, but if you reckon that's the best way to see regression, I'll give it a go to get a number LOL


That I know of no 
But I didn't really look hard since then.
It's a bit of a hassle to setup but once is done is done and it's really a reliable and comparable metric.
Not only to check FCLK regression but in general to see if the CPU is pumping out the correct IOPS under heavy load.


----------



## mongoled

MyUsername said:


> 4900 OC, 6 cores. Brings superpi a bit closer to you. Linpack just locks up the pc.
> 
> View attachment 2532653


You chopped the time it took to complete

😂 😂



Audioboxer said:


> View attachment 2532680
> 
> 
> Memory profile hasn't changed for ages, it benches fine in AIDA64.
> 
> I tried turning off PBO, well, I set it to AUTO which IIRC goes to default and removes the curve and as expected the result is even worse lol
> 
> View attachment 2532681
> 
> 
> Before I turn PBO back on to check what core it is targetting is anyone else running Super PI with Windows 11?
> 
> I have read people say they're still getting poor performance and/or the newest AMD chipset drivers are worse on Windows 11 (the ones MSI/ASUS have released before AMD).
> 
> 
> 
> Funnily enough it is my MT score which tanks with IF at 2000, not so much ST. I have tried up to around 2.0v on CPU 1.8. I just think while I can boot it and I don't get "too much" WHEA 19 spam, my CPU is just unstable as frick when under a heavy load with FCLK 2000.


I experienced a "funny" run just now, simply closed the superpi windows, re-opened it and it ran normally (screenshot coming soon)....

May be something completely unrelated to your issue though ...



Audioboxer said:


> Oh, it probably doesn't, I was just adding it's my MT score that tanks lol. The score I get is as if PBO is turned off. 117xx is around what I get without PBO, 13xxx is what I get with PBO on. It's as if when I have FCLK 2000 PBO just... breaks? You're probably 100% right in normal circumstances CPU 1.8 up to 2.0v will help most people, but it didn't seem to help me. I think my CPU just can't handle the IF at 2000 on heavy CPU loads
> 
> @mongoled Interesting observation
> 
> View attachment 2532684
> 
> 
> Super PI seems to peg to Core 5 95% of the time. Core 2 is my best. Occassionally throughout the run it seemed as if it wanted to use Core 2, but it kept using Core 5.
> 
> Not sure what this tells me? Is it possible Windows 11 core scheduling is still broken? I'm going to revert to the AMD chipset drivers AMD have officially released and check. I would also ask does it mean Core 2 is unstable? But this core has had like 16 hours of corecycler lol. Never get any idle reboots or anything either.
> 
> @domdtxdissar Just noticed you are using Windows 11, what AMD chipset drivers are you using? 3.10.22.706?


ManniX-ITA below has mentioned setting it via benchmate, may have to give that app a go, for those who use it does it add latency when its used ???



ManniX-ITA said:


> I think with benchmate you can set the affinity.
> 
> Keep in mind that VDD18 over 1.9V on a 5950X is extremely heavy on thermals, mine starts throttling above it.
> Did you check the temperatures?




And my latest attempt, so close to sub 49ns, but im running out of headroom!

If I wait for cold cold temperatures (which never come here in Cyprus) then for sure these settings are going sub 49ns



Going to try to eek out a few more mhz, may get me to 49ns .......

Membench threw some errors, needs to up vDIMM slightly


----------



## MyUsername

mongoled said:


> You chopped the time it took to complete
> 
> 😂 😂


🤣


----------



## Audioboxer

ManniX-ITA said:


> Thanks for the reports, didn't know it could change with FCLK speed.
> My Unify-X squeaks always the same
> 
> @Audioboxer did you try to enable CLKREQ# at FCLK 2000?


Yeah I turn that on for all FCLK 2000 testing lol. This weekend I'm going to give an older BIOS a good go, this one to be precise MSI B550 Unify / Unify-X Overclocking & Discussions...


----------



## Audioboxer

Had a bit of time so had a quick go with the older BIOS, still get USB issues when heavy CPU load testing is done. Along with the mouse pointer jerk issue.

I think it's safe to say my CPU simply can't handle IF 2000 without issues. Any sort of heavy load and it just loses it.

Have to set my commander pro up again now 🤣 Only thing I think I noticed was the VRM noise was maybe a little quieter with the older BIOS.

Either AMD release a magical AGESA update or I'm going to have to wait for the 3D cache revision for a chance at running my memory at 4000.

The method of flashing from within Windows works fine though, at least that is something I can confirm as a positive.


----------



## dk_mic

ManniX-ITA said:


> Optimizing VDD18 it's very tricky; if you have the AMD PBS menu on MSI you can set also an offset with a 1 mV granularity.
> For me at FCLK 2000 is best set at 1.81V and a negative offset of 30 mV which reads 1.844V in HWInfo.
> While at FCLK 1900 was best set at 1.83V.
> Going up was worse or same; there was a nice spot above 1.97V but at that point the temps were out of control in all-core.
> Your sample really likes low voltages, very likely for VDD as well.
> But if you want to test, you really need to check every step.


At which metric are you looking, when trying to optimize VDD18?
Just stability and temps or does this possibly improve performance or affect memory latency?


----------



## Mach3.2

Audioboxer said:


> Had a bit of time so had a quick go with the older BIOS, still get USB issues when heavy CPU load testing is done. Along with the mouse pointer jerk issue.
> 
> I think it's safe to say my CPU simply can't handle IF 2000 without issues. Any sort of heavy load and it just loses it.
> 
> Have to set my commander pro up again now 🤣 Only thing I think I noticed was the VRM noise was maybe a little quieter with the older BIOS.
> 
> Either AMD release a magical AGESA update or I'm going to have to wait for the 3D cache revision for a chance at running my memory at 4000.
> 
> The method of flashing from within Windows works fine though, at least that is something I can confirm as a positive.


I wouldn't hold my breath on AMD fixing WHEAs/USB dropout over 1900MHz IF.


----------



## PJVol

Mach3.2 said:


> I wouldn't hold my breath on AMD fixing WHEAs/USB dropout over 1900MHz IF


I would even say, wait for Zen4 for that, or buy mobile/pro part.


----------



## Audioboxer

Mach3.2 said:


> I wouldn't hold my breath on AMD fixing WHEAs/USB dropout over 1900MHz IF.


Oh don't worry, I expect nothing.

Heck, I will not be day 1 on the 3D cache revision despite the likelihood after it instantly sells out there will be months of shortages, again. Not risking it until it's been widespread tested if it does anything for IF.

At this point, IMO, better cache results and better benching isn't going to mean much unless you can take advantage of 4000+ memory.

If AMD can't fix issues on this gen hardware I'll be waiting on their next-gen offering and/or waiting on Intel's first revision. Intel CPUs look great now, but they've kind of bruteforced performance with very high wattage. A revision or two will help them hopefully bring that down a bit.

Memory on the AMD platform is now in a bit of tragic position, so ball is in AMD's court. We've got all these high end DDR4 bins coming out end of generation and basically no way to use them to their full extent on AMD platforms 💀


----------



## Mach3.2

Audioboxer said:


> Oh don't worry, I expect nothing.
> 
> Heck, I will not be day 1 on the 3D cache revision despite the likelihood after it instantly sells out there will be months of shortages, again. Not risking it until it's been widespread tested if it does anything for IF.
> 
> At this point, IMO, better cache results and better benching isn't going to mean much unless you can take advantage of 4000+ memory.
> 
> If AMD can't fix issues on this gen hardware I'll be waiting on their next-gen offering and/or waiting on Intel's first revision. Intel CPUs look great now, but they've kind of bruteforced performance with very high wattage. A revision or two will help them hopefully bring that down a bit.
> 
> Memory on the AMD platform is now in a bit of tragic position, so ball is in AMD's court. We've got all these high end DDR4 bins coming out end of generation and basically no way to use them to their full extent on AMD platforms 💀


Yeah, I'll just buy whatever that is better in 4 or 5 years time when it's time to retire my current rig. Just like you've said, it kinda tragic that RAM OC is kinda kneecapped on Zen 2/3.


----------



## ManniX-ITA

dk_mic said:


> Just stability and temps or does this possibly improve performance or affect memory latency?


Stability and performances. Temps are worse, like going from Scalar 1x to 10x.
Tweaking is improving Geekbench 5 scores, which is the result of a well mixed type of workloads.
Many posted also improvements on memory, I didn't get a boost on that side. Mostly CPU.


----------



## howkey[cz]

howkey[cz] said:


> So, FCLK 1900 with this timings seems to be stable so far. Running it 1:2 means less whea errors like 1/3


So I found that my memory timing was causing some problems, it's fixed now, but still can't run it FCLK 1933+ without whea errors. Any tips please?


----------



## PJVol

Audioboxer said:


> We've got all these high end DDR4 bins coming out end of generation and basically no way to use them to their full extent on AMD platforms


I wouldn't generalize to the whole Zen3 family. Just made a submission to a Zen RamOC Leaderboards.


----------



## PJVol

^^^ glitched


----------



## Audioboxer

PJVol said:


> I wouldn't generalize to the whole Zen3 family. Just made a submission to a Zen RamOC Leaderboards.


Of course not, but there's even some unlucky 5950x owners that can't run 1900 stable. A total pull a figure out of my ass and I'd guess maybe only 10~20% of Zen 3 owners can run 2000, properly, without extreme instability (USB or worse) or minor performance regression.

And because it's a total lottery and not as if AMD are selling 1900+ FCLK chips in retail for a price premium, it just means the end user is left with RNG. All OCing is obviously somewhat RNG, but as I said the ball is in AMD's court right now to see if they can get something out for this generation that can take advantage of EoL DDR4 bins without all this luck.

Just so happens DDR4 has had a pretty nice end to its life with some seriously tasty bins. Zen 3 made some improvements, but all eyes on 3D cache now.


----------



## PJVol

Audioboxer said:


> maybe only 10~20% of Zen 3 owners can run 2000, properly, without extreme instability (USB or worse) or minor performance regression.


I'd estimate rather 1-2%, that is tbf overly optimistic. But mind you, Zen3 is not just desktop X models.


----------



## Audioboxer

PJVol said:


> I'd estimate rather 1-2%, that is tbf overly optimistic. But mind you, Zen3 is not just desktop X models.


That low? Yikes lol. Oh well, that makes me feel better!


----------



## mongoled

PJVol said:


> Just made a submission to a Zen RamOC Leaderboards.


😍

@Audioboxer is going to have a heart attack

😂😂


----------



## Audioboxer

mongoled said:


> 😍
> 
> @Audioboxer is going to have a heart attack
> 
> 😂😂


Pfft, even I can run memory stability tests and benchmarks at 2000 FCLK


----------



## ManniX-ITA

Audioboxer said:


> Pfft, even I can run memory stability tests and benchmarks at 2000 FCLK


This one:


----------



## jvidia

Any opinions on the Gskill Royal F4-4400C17D-32GTRS ?
Will they do 3800 CL14 @1.5v ?


----------



## Taraquin

Tested a bit yesterday to see what requirements different fclk needs, vddp and ccd kept at 0.82v. I evaluate with aida latency as setting soc or iod a bit too low increases latency significantly. Trying 0.01v lower iod and soc than the below numbers increases latency by 0.5-1ns, using 0.02v below and it increases by 2-3ns.
3800\1900 1.06 soc, 0.98 iod
4000\2000 1.11 soc, 1.03 iod
4066\2033 1.15 soc, 1.05 iod
4133\2066 1.2 soc, 1.07 iod

Seems soc-scaling gets hopeless above 2000 fclk on my setup.


----------



## ManniX-ITA

jvidia said:


> Any opinions on the Gskill Royal F4-4400C17D-32GTRS ?
> Will they do 3800 CL14 @1.5v ?


I bought the Trident Royal Z 4266C17 and they were same as the Trident Z 4000C16.
Got more lucky with the 4000C14 kit.
Could be you can get CL14 flat at 3800 but it's unlikely.



Taraquin said:


> ccd kept at 0.82v.


CCD at 820mV? Isn't very low?


----------



## Mach3.2

Taraquin said:


> Tested a bit yesterday to see what requirements different fclk needs, vddp and ccd kept at 0.82v. I evaluate with aida latency as setting soc or iod a bit too low increases latency significantly. Trying 0.01v lower iod and soc than the below numbers increases latency by 0.5-1ns, using 0.02v below and it increases by 2-3ns.
> 3800\1900 1.06 soc, 0.98 iod
> 4000\2000 1.11 soc, 1.03 iod
> 4066\2033 1.15 soc, 1.05 iod
> 4133\2066 1.2 soc, 1.07 iod
> 
> Seems soc-scaling gets hopeless above 2000 fclk on my setup.


Probably had something to do with going above 1900MHz FCLK on a dual CCD chip, but pumping an extra 0.1V of vSoC(1.15V to 1.25V) didn't really did anything to lower the number of WHEAs at 1933MHz FCLK for me.


----------



## jcpq

Windows11


----------



## jcpq

domdtxdissar said:


> With all memory enabled:
> View attachment 2532613


Where can I get this new version of super pi?
In the lower right corner.


----------



## ManniX-ITA

jcpq said:


> Where can I get this new version of super pi?
> In the lower right corner.


Install Benchmate and it will download the right version for you.






BenchMate







benchmate.org


----------



## jcpq

ManniX-ITA said:


> Install Benchmate and it will download the right version for you.
> 
> 
> 
> 
> 
> 
> BenchMate
> 
> 
> 
> 
> 
> 
> 
> benchmate.org


thank you friend


----------



## domdtxdissar

jcpq said:


> Where can I get this new version of super pi?
> In the lower right corner.


Benchmate

Frequently Asked Questions


----------



## Audioboxer

jvidia said:


> Any opinions on the Gskill Royal F4-4400C17D-32GTRS ?
> Will they do 3800 CL14 @1.5v ?


If it's just CL14 you're after, probably. Though tCL can be bruteforced by voltage no matter what really. You will get 3800 tCL14 working, what voltage? It just depends. I can run it at 1.44v, but nearer 1.5v is probably more common.

If you're wanting "flat 14", aka tRCDRD to be at 14, it's complete luck.

I bought the 3600 14-14-14-14 1.45v bin first as I assumed 3800 14-14-14-14 must be a given, I couldn't run tRCDRD 14 at 3800. Really disappointing. Went with that bin originally to save a bit of money buying the 4000 14-15-15-15 bin. That is the one I now own... lol.

tRCDRD 14 seems to be complete luck other than if you spend a lot of money on the most expensive bins. Even then, I guess it's not guaranteed either. Hence G.SKILL still refusing to retail a 3800 14-14-14-14 bin.

You could buy a 3200 14-14-14-14 bin and manage to OC it to 3800 14-14-14-14, you could buy a 3600 14-14-14-14 bin like I originally did, and 3800 tRCRD 14 refuses to work.

My pull things out my ass take on it now, after becoming familiar with maxmem, is quite a few bins might be close to running tRCDRD 14, or even 13, but one chip or one part of the memory just can't quite make it. Given the average consumer isn't going to care much about 14 or 15, G.SKILL can just sell the bin at say 14-15-15-15 and still sell it for high value.



















I mean with maxmem limiting to 3~9GB here is me showing tRCDRD 13 running at 3800. I can of course* not *run tRCDRD 13 at 32GB. I've seen a few SR kits do it (2x8GB), I've yet to see DR sticks do it at 32GB whilst showing it has been properly stability tested. This to me makes it seem like "some" of my memory can run tRCDRD 13, but not all of it. Though I have to also ask could it be the IMC that can't handle the data rate at a full 32GB??? I don't have another Ryzen CPU to test.

Occasionally you're going to get bins that can run at tRCDRD 14 at 3800, but G.SKILL will only be testing it can run properly at 15 for mass production/sale, so the consumer wins the "silicon lottery". No one can guarantee it though, just advise if you buy a decent bin you _may_ have a better chance.


----------



## ManniX-ITA

Audioboxer said:


> tRCDRD 14 seems to be complete luck other than if you spend a lot of money on the most expensive bins. Even then, I guess it's not guaranteed either. Hence G.SKILL still refusing to retail a 3800 14-14-14-14 bin.


That's right and I'd also add that even a flat 14 kit would be just a joke.
Our 4000 14-15-15-15 kit XMP profile it's just trash; that's because to run tRCDRD at 15 almost all the other timings have to be massively nerfed.
Same would probably be for a 3800 flat 14 kit; set with tRCDRD at 15 would go much much better due to the other timings properly tightened.
Just like this one with tRCDRD at 16, it does fly; the XMP profile with 15 is so bad that you just can't believe it.


----------



## Audioboxer

ManniX-ITA said:


> That's right and I'd also add that even a flat 14 kit would be just a joke.
> Our 4000 14-15-15-15 kit XMP profile it's just trash; that's because to run tRCDRD at 15 almost all the other timings have to be massively nerfed.
> Same would probably be for a 3800 flat 14 kit; set with tRCDRD at 15 would go much much better due to the other timings properly tightened.
> Just like this one with tRCDRD at 16, it does fly; the XMP profile with 15 is so bad that you just can't believe it.


Interesting addition, I just sort of assumed ALL XMP profiles were basically the same trash. I never really considered that secondary timings on a 4000 14-15-15-15 XMP profile might be much worse than say a 3800 14-16-16-16 XMP profile. I think all XMP profiles are pretty loose for us OCers but I never really considered some kits might have much worse XMP secondaries than others.

I guess if they sell a flat 14 kit it at least proves that tRCDRD 14 will run at whatever frequency its rated for. That has to count for something even if the XMP secondary timings are awful.

But as my experience shows a 3600 14-14-14-14 kit while it has to be able to run those primaries at 3600, offers no guarantees at 3800. Mines simply would not run tRCDRD 14, even with loose secondary timings. My older 2016 3200 14-14-14-14 kit also couldn't run tRCDRD 14 at 3800. It even struggled a bit with tCL14.

The only kit of b-die I've owned to manage tRCDRD 14 at 3800 has been this one. But that is only a sample size of 3, and one of the bins was an older 2016 set.


----------



## ManniX-ITA

Audioboxer said:


> Interesting addition, I just sort of assumed ALL XMP profiles were basically the same trash. I never really considered that secondary timings on a 4000 14-15-15-15 XMP profile might be much worse than say a 3800 14-16-16-16 profile.


The XMP profile of this kit is the worst I've ever seen.
Just a little bit of tightening of any of the other timings and tRCDRD starts freaking out. It's working borderline at 15.
All other kits have a much much bigger headroom.
But the worse is that it does work really bad.
Usually all the XMP profiles are well balanced; slow of course because they have to be super safe.
But they are well tailored around the kit.
With this profile, my CPU-z ST score is crashing and AIDA latency is swinging 5-10 ns randomly.
Maybe it's my binning which was not the best. But it shouldn't happen.



Audioboxer said:


> But as my experience shows a 3600 14-14-14-14 kit while it has to be able to run those primaries at 3600, offers no guarantees at 3800. Mines simply would not run tRCDRD 14, even with loose secondary timings.


Indeed. 
And the same kit that others can run with flat 14 at 3800 but manufactured now it's probably not going to work with flat 14.
I've bought the same exact kit that Neody and others are running flat 14, 3200C14, and it was just like the 3600C14 and 3600C16.
No one of them, manufactured now, was able to run flat 14 at 3800.


----------



## Audioboxer

ManniX-ITA said:


> The XMP profile of this kit is the worst I've ever seen.
> Just a little bit of tightening of any of the other timings and tRCDRD starts freaking out. It's working borderline at 15.
> All other kits have a much much bigger headroom.
> But the worse is that it does work really bad.
> Usually all the XMP profiles are well balanced; slow of course because they have to be super safe.
> But they are well tailored around the kit.
> With this profile, my CPU-z ST score is crashing and AIDA latency is swinging 5-10 ns randomly.
> Maybe it's my binning which was not the best. But it shouldn't happen.
> 
> 
> 
> Indeed.
> And the same kit that others can run with flat 14 at 3800 but manufactured now it's probably not going to work with flat 14.
> I've bought the same exact kit that Neody and others are running flat 14, 3200C14, and it was just like the 3600C14 and 3600C16.
> No one of them, manufactured now, was able to run flat 14 at 3800.


Ultimately this gets us to the "best advice" is buy something and cross your fingers 🤞


----------



## PJVol

ManniX-ITA said:


> Usually all the XMP profiles are well balanced; slow of course because they have to be super safe.


That reminded me of my latest purchase, where I was inspired by xmp 1.4V for the 4000CL16, and how this inspiration was quickly ruined as soon as I found that xmp meant GDM is set, and with 1T they actually not much better (if at all) than my Galax HOF 3600CL17 kit. 
The only noticable advantage I see is lower allowed tRFC.


----------



## ManniX-ITA

PJVol said:


> The only noticable advantage I see is lower allowed tRFC.


It's my 2nd kit; not bad but indeed not much better than the 3200C14 and 3600C16 that I've tested later.
With tight timings not stable at 4000 MHz with tRCDRD 16 while the 4000C14 can run it.


----------



## Audioboxer

ManniX-ITA said:


> It's my 2nd kit; not bad but indeed not much better than the 3200C14 and 3600C16 that I've tested later.
> With tight timings not stable at 4000 MHz with tRCDRD 16 while the 4000C14 can run it.


A big thing I think the 4000C14 kit has going for it is 1.55v. I nearly bought the 400016 kit to save some money and thinking "at 1.4v, that must be a good OCing kit!". But I've somewhat changed my mind to think if a kit is retailing with a higher voltage, the likes of 1.55v, it must be chips with a good thermal overhead.

Heat is one of the big killers for b-die it seems, so if you're into OCing that is always worth keeping in mind.


----------



## ManniX-ITA

Audioboxer said:


> A big thing I think the 4000C14 kit has going for it is 1.55v. I nearly bought the 400016 kit to save some money and thinking "at 1.4v, that must be a good OCing kit!". But I've somewhat changed my mind to think if a kit is retailing with a higher voltage, the likes of 1.55v, it must be chips with a good thermal overhead.
> 
> Heat is one of the big killers for b-die it seems, so if you're into OCing that is always worth keeping in mind.


I honestly don't know 
Bought the 1.4V for that reason and the 1.55V for comparison; they seems to behave mostly the same.
At CL16 they can both run error free hammered for hours with TM5 up to 56c. The 4000C14 can do it with tRCDRD at 16, only obvious difference.
Both are dropping quickly errors at CL14 over 53c.
I suspect it all ends up as always on how lucky you get on the binning lottery


----------



## Audioboxer

ManniX-ITA said:


> I honestly don't know
> Bought the 1.4V for that reason and the 1.55V for comparison; they seems to behave mostly the same.
> At CL16 they can both run error free hammered for hours with TM5 up to 56c. The 4000C14 can do it with tRCDRD at 16, only obvious difference.
> Both are dropping quickly errors at CL14 over 53c.
> I suspect it all ends up as always on how lucky you get on the binning lottery


100%, but most B-die with tight timings will struggle above 50 degrees. With more of a thermal overhead I'm guessing in the 40s you might see the 4000C14 kit behave better. My 3600C14 kit really started to cry above 42 degrees running TM5 with tight secondaries. Had to keep my 120mm at 100% during TM5 to keep it to 40~42 degrees.

This 4000C14 kit seemed to have a bit more tolerance, then again, I switched very quickly to watercooling once getting it so I didn't do weeks of testing with it on air cooling.

It's also managed to do 3800 14-14-14-14 at 1.44v, but that might just be more to do with the quality of this bin than it being rated at 1.55v.

Speaking of thermal overhead I've finally figured out my 5950x overclocking which amounted to stability test a curve with PBO settings you seen online (270/160/190) left performance on the table. Went from 29571 to 30306 turning off AutoOC and using 270/165/210










A little bit more heat now with the jump from TDC 160 to 165 but like 800+ more points.

Goes to show folks don't skip properly OCing your CPU to rush to memory lol. Memory will take you months to learn, get your CPU done first!


----------



## mongoled

Audioboxer said:


> Goes to show folks don't skip properly OCing your CPU to rush to memory lol. Memory will take you months to learn, get your CPU done first!


CPU can also take months

😂😂


----------



## Audioboxer

mongoled said:


> CPU can also take months
> 
> 😂😂


Prior to 5xxx I'd agree, but the curve really simplifies things over all the manual OCing. Maybe a week or two if you are properly doing overnight corecycler runs and such.

I done this in about a week, copied someone else's PBO settings with minimal knowledge on wattage/amperage, set a silly -30 on all cores manual curve, ran corecycler, noted down each core that fails and take them down one by one. Though I knew the best 4 cores should be dropping by like 5~10 rather than 1~3 as anyone claiming their best cores are fully stable at -30 is _probably_ talking nonsense. My very best core is at like -5.

But I guess this is the cutting corners way, really I should also be noting down benchmark results and doing small changes here and there to PBO settings till every last drop of performance is squeezed out. Done a bit of that today but I do know getting 30700~31000+ can be achieved on a 5950x.

If you're going into WHEA 19 territory, then yeah, sure I fully agree. Good luck to anyone trying to stabilise above 1900 FCLK on their CPU. That is probably going to take months


----------



## Audioboxer

Alright, guess it is true what they say a manual overclock is almost always going to kick PBO's ass on CB lol.

1000 points more, but it comes with the price of 1.35v and during CB I was hitting 92~95 degrees with loop on idle fans. With fans at 100% I managed to curb it to 86~88 degrees. This has made me think I could go back and revisit TDC. I thought temps this high would throttle performance, but the manual overclock is powering through them. Unless PBO will throttle at like 88 degrees? Going to play with TDC anyway and see if I can get my PBO R23 score nearer 31k.

*edit -








*

I seriously doubt this is stable, but still, that was fun, 31388. CCD 2 rebooted CB when running at 4.7ghz, thats why it was dropped to 4.65ghz. It's a weaker CCD than CCD 1.










Back down to earth though and I think 30595 will do me just fine for PBO, without having to spend goodness knows how much time redoing my curve and fiddling about with all sorts of voltages.

Wish AMD had a way to juggle all core clock speeds vs single core boosting better, as it's like threading the eye of a needle trying to balance single core vs multicore. I guess this is what that ASUS Dark Hero mobo feature is supposed to do, run both manual overclock and PBO depending on the task.


----------



## Luggage

Audioboxer said:


> View attachment 2533031
> 
> 
> Alright, guess it is true what they say a manual overclock is almost always going to kick PBO's ass on CB lol.
> 
> 1000 points more, but it comes with the price of 1.35v and during CB I was hitting 92~95 degrees with loop on idle fans. With fans at 100% I managed to curb it to 86~88 degrees. This has made me think I could go back and revisit TDC. I thought temps this high would throttle performance, but the manual overclock is powering through them. Unless PBO will throttle at like 88 degrees? Going to play with TDC anyway and see if I can get my PBO R23 score nearer 31k.
> 
> *edit -
> 
> View attachment 2533059
> *
> 
> I seriously doubt this is stable, but still, that was fun, 31388. CCD 2 rebooted CB when running at 4.7ghz, thats why it was dropped to 4.65ghz. It's a weaker CCD than CCD 1.
> 
> View attachment 2533060
> 
> 
> Back down to earth though and I think 30595 will do me just fine for PBO, without having to spend goodness knows how much time redoing my curve and fiddling about with all sorts of voltages.
> 
> Wish AMD had a way to juggle all core clock speeds vs single core boosting better, as it's like threading the eye of a needle trying to balance single core vs multicore. I guess this is what that ASUS Dark Hero mobo feature is supposed to do, run both manual overclock and PBO depending on the task.


For a given load AC can always beat PBO, but can you run y- cruncher with that cb setting?
Edit and will it beat your super pi pb?


----------



## Audioboxer

Luggage said:


> For a given load AC can always beat PBO, but can you run y- cruncher with that cb setting?
> Edit and will it beat your super pi pb?


I seriously doubt it, not even 100% confident 4.7ghz will be stable at 1.35v under stress testing. I'll check it soon, I _lied_ earlier, tinkering away with PBO still lol










Super PI is a lot better, yeah, more in-line with what people were getting earlier. I'll edit in a run to this post shortly.

*edit *-










I removed my Auto OC so that has reduced single thread to 5050 max, but Auto OC was consistently lowering my CB23 scores.

I see dom's Super PI is right up to 5150mhz, but IIRC 5100mhz is the highest I've ever seen on my chip.

5m 47s is a hell of a lot better than this mess [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## mongoled

Any news on these AWOL agesa 1.2.0.4 BIOSs ??


----------



## kairi_zeroblade

mongoled said:


> Any news on these AWOL agesa 1.2.0.4 BIOSs ??


they got scared at ADL..devs were demotivated to work on them..lol


----------



## mongoled

kairi_zeroblade said:


> they got scared at ADL..devs were demotivated to work on them..lol


Hopefully not!

😂 😂

So....

The profile below is now ready for when winter arrives here in the Eastern Mediterranean, I believe with ambient temps 5C lower than 49ns should become sub 49ns


----------



## Audioboxer

Here is a quick question for you all










185/130/140 on PBT/TDC/EDC










270/168/220 on PBT/TDC/EDC

Both ran once on a fresh boot, no multiple runs. Memory profile same across both.

I'm guessing it's quite normal that you're either going to see ST take the lead or MT take the lead (as in most of us need to prioritise either maximising ST or MT)? Almost breaking 700 on ST with lower PBO settings, but increasing PBO settings results in 2600+ more points in CB.

Don't get me wrong I've seen people master a high ST _and_ MT score in CPU-Z, I'm not quite there yet, but it's just interesting to see ST score that much higher in CPU-Z with substantially lower PBO settings.

Secondary thing I might need to explore is more of my BIOS settings. I was reading someone say to disable DF C-States? Not the ordinary C-States variant but the DF one?


----------



## PJVol

Audioboxer said:


> it's just interesting to see ST score that much higher in CPU-Z with substantially lower PBO settings.


CPU-z is not good at benching single thread/core performance. Lower ST score is most likely caused by some concurrent load at core0, so if you wanna see proper ST score, just set #threads to 1 before start. PBO limits only affect multi-core workloads.


----------



## ManniX-ITA

Audioboxer said:


> Don't get me wrong I've seen people master a high ST _and_ MT score in CPU-Z, I'm not quite there yet, but it's just interesting to see ST score that much higher in CPU-Z with substantially lower PBO settings.


Yes, there are a number of things you can play with to compensate 
PBO Scalar and telemetry are a 2 factors you can use.
You should also try setting NUMA to NPS0.



Audioboxer said:


> Secondary thing I might need to explore is more of my BIOS settings. I was reading someone say to disable DF C-States? Not the ordinary C-States variant but the DF one?


It's broken and by default disabled.
I have to force it enabled otherwise when overlocked I get BSODs or random reboots.
Behavior seems to be specific for sample, like the AGESA. Some CPUs doesn't like a version, others does...

There are also some other options you should check like forcing APBDIS or NBIO LCLK DPM.



PJVol said:


> CPU-z is not good at benching single thread/core performance. What you see is perhaps some concurrent load at core0, an if you wanna see proper ST score, just set #threads to 1 before start.


Yes, by default is selecting Core0 which is bit dumb.
You can force it to a specific cpu core/thread with task manager but only after the test is started.
It's valuable to understand if something is wrong; if during the run the score goes up & down there's a problem.
For the actual score and correct tuning is better to relay on Geekbench 5.


----------



## Audioboxer

ManniX-ITA said:


> Yes, there are a number of things you can play with to compensate
> PBO Scalar and telemetry are a 2 factors you can use.
> You should also try setting NUMA to NPS0.
> 
> 
> 
> It's broken and by default disabled.
> I have to force it enabled otherwise when overlocked I get BSODs or random reboots.
> Behavior seems to be specific for sample, like the AGESA. Some CPUs doesn't like a version, others does...
> 
> There are also some other options you should check like forcing APBDIS or NBIO LCLK DPM.
> 
> 
> 
> Yes, by default is selecting Core0 which is bit dumb.
> You can force it to a specific cpu core/thread with task manager but only after the test is started.
> It's valuable to understand if something is wrong; if during the run the score goes up & down there's a problem.
> For the actual score and correct tuning is better to relay on Geekbench 5.


Ah right, it'll be disabled for me then as it's just on AUTO. I'll look at some of those settings you've mentioned 

While the MSI BIOS isn't as bad as the ASUS BIOS for duplicate settings everywhere, there is a few things I have turned on under the Overclocking CPU window, such as CPPC/preferred cores and low current idle for the PSU. But these options are also listed again under the Advanced menu. That is where I believe I've seen APBDIS and the others you mention.


----------



## PJVol

ManniX-ITA said:


> You can force it to a specific cpu core/thread with task manager but only after the test is started


It's much easier to set 1 thread if you need just ST score. This yields quite consistent results, esp. if windows background activity not settled down yet )


----------



## Audioboxer

PJVol said:


> It's much easier to set 1 thread if you need ST score. This yields quite consistent results, esp. if windows background activity not settled down yet )
> View attachment 2533394












lol, I still get a difference between them set to 1 thread. This is with the higher PBO settings.


----------



## ManniX-ITA

Audioboxer said:


> lol, I still get a difference between them set to 1 thread. This is with the higher PBO settings.


I think it's just cause since they both run on Core0 when testing ST the core is already hot.
I really don't know why they never switched to first ST...



PJVol said:


> It's much easier to set 1 thread if you need just ST score. This yields quite consistent results, esp. if windows background activity not settled down yet )


I mean testing a specific thread/core, not 1 thread.
I usually test both normally, where for ST is benched Core0, and my best which is Core4.
To get the score of the best one you need to set 1 thread and then once the MT test is almost done, 6-7 seconds, change affinity to the core/thread you want to test.


----------



## Audioboxer

ManniX-ITA said:


> I think it's just cause since they both run on Core0 when testing ST the core is already hot.
> I really don't know why they never switched to first ST...
> 
> 
> 
> I mean testing a specific thread/core, not 1 thread.
> I usually test both normally, where for ST is benched Core0, and my best which is Core4.
> To get the score of the best one you need to set 1 thread and then once the MT test is almost done, 6-7 seconds, change affinity to the core/thread you want to test.


Ah right, makes sense. I just set it to thread 0 so it will have hit the same core again.

This totally makes sense why my lower PBO settings get a higher ST as well, the CPU is cooler the second it switches from MT to ST! TDC at 130 is a hell of a lot cooler than TDC at 168.

I therefore agree it would make sense for CPU-Z to do ST first...


----------



## mongoled

Boy you people are getting harder to impress

😂😂

49ns and stable and no one blinks an eye....

Time to bring on tCL @12 benchmarks

🤣🤣


----------



## Audioboxer

mongoled said:


> Boy you people are getting harder to impress
> 
> 😂😂
> 
> 49ns and stable and no one blinks an eye....
> 
> Time to bring on tCL @12 benchmarks
> 
> 🤣🤣


Pfft, I did 49.x weeks ago [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

Just totally ignore my USB disconnects at FCLK 2000


----------



## mongoled

Audioboxer said:


> Pfft, I did 49.x weeks ago [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> Just totally ignore my USB disconnects at FCLK 2000


49.x pffff

Its all in the X

😂 😂

Wonder if we can go tCL 11 .........

Yeah its TM5 stable for 25 cycles, I have cars for sale ...


----------



## Audioboxer

mongoled said:


> 49.x pffff
> 
> Its all in the X
> 
> 😂 😂
> 
> Wonder if we can go tCL 11 .........
> 
> Yeah its TM5 stable for 25 cycles, I have cars for sale ...
> 
> View attachment 2533406


Isn't the problem with tCL 11 (other than voltage) tCWL?

Anyway, try running a TM5 lol










lol @ how quickly 3 cycles finishes when you need to use maxmem.


----------



## PJVol

@mongoled 
I saw your 59 in a google-doc, and even edited the "juicy" comment field, but it turned out, I wasn't allowed to


----------



## mongoled

PJVol said:


> @mongoled
> I saw your 59 in a google-doc, and even edited the "juicy" comment field, but it turned out, I wasn't allowed to


😍😂


----------



## Audioboxer

That's a bit more reasonable length wise, shame I can't stabilise 1.69v on the PCB with the full 32GB.


----------



## mongoled

Audioboxer said:


> View attachment 2533413
> 
> 
> That's a bit more reasonable length wise, shame I can't stabilise 1.69v on the PCB with the full 32GB.


You still at it with the maxmem

Some poor soul is going to find your screenshot with no idea you are using maxmem and will end up depressed

😂 😂


----------



## Audioboxer

mongoled said:


> You still at it with the maxmem
> 
> Some poor soul is going to find your screenshot with no idea you are using maxmem and will end up depressed
> 
> 😂 😂


LOL

It'll be interesting to see if it's purely PCB or IMC as well. I guess if I buy the 3D cache revision I might find out!


----------



## PJVol

@mongoled
Well, since some noteworthy results have been posted, let me join the party.
Not just for someone to eye-blink, but rather to share a funny experience I got trying to stabilize this:







The thing is i just almost gave up, while trying to understand to no avail, why random errors in random quantity appeared, whatever settings I changed. Until...

I thought, why the hell am i changing those cadbus ohms, knowing not a damn thing about what they really do? So made a final attempt and set those damned cadbus ohms *all to Auto - *i.e. 24-24-24-24.

You know what? Test finished with just one #1, that was gone after pushed Vdimm 20mv up.
That's the thing I've learned today: sometimes it's better to just let the CPU do it on its own, i.e. the way it "knows"


----------



## Mach3.2

PJVol said:


> @mongoled
> Well, since some noteworthy results have been posted, let me join the party.
> Not just for someone to eye-blink, but rather to share a funny experience I got trying to stabilize this:
> View attachment 2533420
> 
> The thing is i just almost gave up, while trying to understand to no avail, why random errors in random quantity appeared, whatever settings I changed. Until...
> 
> I thought, why the hell am i changing those cadbus ohms, knowing not a damn thing about what they really do? So made a final attempt and set those damned cadbus ohms *all to Auto - *i.e. 24-24-24-24.
> 
> You know what? Test finished with just one #1, that was gone after pushed Vdimm 20mv up.
> That's the thing I've learned today: sometimes it's better to just let the CPU do it on its own, i.e. the way it "knows"


I bet you had the look of that little girl in your wallpaper when 24-24-24-24 and +20mV vDIMM worked.. 🤣🤪


----------



## hazium233

Tried to catch up on this thread, and it looks like it touched on something I was interested in asking about. Namely tRCD on Vermeer.

There was an idea that desktop Zen anyway may have a practical limit around 7.5ns (ie 14t at 3733), although perhaps maybe restated it would be the average Zen3 wouldn't do below that.

Or is that not even a real limit, and the problem is ram samples and PCB not IMC? How many people have tested very good B-die on A0 with Ryzen?


----------



## Audioboxer

hazium233 said:


> Tried to catch up on this thread, and it looks like it touched on something I was interested in asking about. Namely tRCD on Vermeer.
> 
> There was an idea that desktop Zen anyway may have a practical limit around 7.5ns (ie 14t at 3733), although perhaps maybe restated it would be the average Zen3 wouldn't do below that.
> 
> Or is that not even a real limit, and the problem is ram samples and PCB not IMC? How many people have tested very good B-die on A0 with Ryzen?


Well, tRCDRD 14 at 3800 is clearly do-able with Zen 3 and it's totally down to your memory. tRCDRD 13 at 3800 seems like a much bigger issue. I've seen some Zen 3 processors manage it with SR, but I've yet to see a single case of DR passing stability tests at 13 with 3800.

Best I can manage is to use maxmem which I think shows me there is a practical limit/bandwidth issue with the IMC. I wish I had a G chip to test. In lieu of that waiting on the 3D cache revision to see if it both helps with IF and is a better IMC all round.

Seems to me the best b-die bins can be pushed further but Ryzen isn't really in a great position to take advantage.


----------



## hazium233

I might have been a little unclear, in that practical was also supposed to be "error free" for daily. So I agree maxmem results might show the absolute limit, would that apply to daily operation at full capacity?

Anyway I would have thought that even if the IMC in most Zen3 desktop couldn't reliably do 14t at 3800 that there could be the outliers that would given the right circumstances just from a probability standpoint. Two slot boards should have a little advantage here too.

I suppose it is neither here nor there. For a given sample and combo it does or it doesn't. 

I also would wonder when the 3D cache models come out if they start to look even less sensitive to changes in some ram timings.



Audioboxer said:


> Well, tRCDRD 14 at 3800 is clearly do-able with Zen 3 and it's totally down to your memory. tRCDRD 13 at 3800 seems like a much bigger issue. I've seen some Zen 3 processors manage it with SR, but I've yet to see a single case of DR passing stability tests at 13 with 3800.
> 
> Best I can manage is to use maxmem which I think shows me there is a practical limit/bandwidth issue with the IMC. I wish I had a G chip to test. In lieu of that waiting on the 3D cache revision to see if it both helps with IF and is a better IMC all round.
> 
> Seems to me the best b-die bins can be pushed further but Ryzen isn't really in a great position to take advantage.


----------



## iraff1

I'm trying out some samsung b-die how they compare to my ballistix max memories and to my surprise even though i have much lower timings accross the board my latency is worse at 61ms while on the much slower ballistix ram i have 59ms in aida extreme latency test.

Can you see what the fault might be and what i should be tweaking? I was at least expecting to get 55ms or lower with these samsungs at these timings... i must be missing something?

Ballistix is 4x single rank 16gb modules
Gskill is 4x single rank 8gb modules

Running same FLCK but timings are higher on the Ballistix
Gskill:









Ballistix max









If i run GDM disable on the gskill they throw errors even at xmp, is that giving this massive performance hit?


----------



## Luggage

iraff1 said:


> I'm trying out some samsung b-die how they compare to my ballistix max memories and to my surprise even though i have much lower timings accross the board my latency is worse at 61ms while on the much slower ballistix ram i have 59ms in aida extreme latency test.
> 
> Can you see what the fault might be and what i should be tweaking? I was at least expecting to get 55ms or lower with these samsungs at these timings... i must be missing something?
> 
> Ballistix is 4x single rank 16gb modules
> Gskill is 4x single rank 8gb modules
> 
> Running same FLCK but timings are higher on the Ballistix
> Gskill:
> View attachment 2533545
> 
> 
> Ballistix max
> View attachment 2533557
> 
> 
> If i run GDM disable on the gskill they throw errors even at xmp, is that giving this massive performance hit?


Probably my default 4x8 g-skill flare x 3200cl14 settings before I really started messing with ram timings and buying new kits.



http://imgur.com/a/UvUk67m


----------



## ManniX-ITA

iraff1 said:


> Can you see what the fault might be and what i should be tweaking? I was at least expecting to get 55ms or lower with these samsungs at these timings... i must be missing something?


Check for a good profile here:









Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com





Look at the image on the screenshot of proof column for the 4x8GB B-die configs.
There's usually a Zentimings ss.
You can get any at 3733 and above but don't go for the very aggressive ones, start with something not too exaggerated.
Consider tRCDRD at 14 could not hold with better timings and pick something with VDIMM at 1.5V or below.


----------



## TheBoy08

Hello. I recently got into overclocking, my ultimate goal is to get as many fps/performances I can get with what I'm currently running with.

So far here is what I'm running with:









I tried to get GDM disabled but it doesn't post at all when trying to do so. My kit gets really hot (43C Idle, 54C while gaming) and I think it crashes because of that but I ordered a fan that should be coming up on monday to fix that. Any tips on where I can improve?

Infos: 
CPU: Ryzen 5900x 
Mobo: x570 Dark Hero (latest BIOS) 
RAM: samsung bdie 2x8Go Trident Z RGB (4000Mhz C16 kit that I'm running at 3800Mhz and 1900 FCLK because I whea at 2000 FCLK)


----------



## MrHoof

@TheBoy08 no ramdom timeouts in tm5 with tras at 21? If yes I would suggest 14-8-15-14-26-40.

Also your VDDP is probably way to high lower it until u see tPHYRDL drop to 28 on one stick. This needs a forced memory training in some way like changing a timing like trdwr to auto. Changing VDDP alone else will only affect memory training on cold boot.


----------



## Audioboxer

TheBoy08 said:


> Hello. I recently got into overclocking, my ultimate goal is to get as many fps/performances I can get with what I'm currently running with.
> 
> So far here is what I'm running with:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I tried to get GDM disabled but it doesn't post at all when trying to do so. My kit gets really hot (43C Idle, 54C while gaming) and I think it crashes because of that but I ordered a fan that should be coming up on monday to fix that. Any tips on where I can improve?
> 
> Infos:
> CPU: Ryzen 5900x
> Mobo: x570 Dark Hero (latest BIOS)
> RAM: samsung bdie 2x8Go Trident Z RGB (4000Mhz C16 kit that I'm running at 3800Mhz and 1900 FCLK because I whea at 2000 FCLK)


tCWL to 14 and tRDWR to 8 or 9.

As for GDM disabled not posting, try 2T first and if that doesn't work GDM is currently masking issues with your timings. Loosen some things up to see what gets GDM 2T booting. SCLs to 4 is an easy go to, then tRAS to 24~28. Or tWTRS to 4.

2T will boot at some point. VDDP should be OK at 0.9v. VSOC being a bit higher might even help with GDM.


----------



## Thanh Nguyen

Anyone here using EVGA mobo? No idea why I can post in asus dark hero but no post with evga dark


----------



## o1dschoo1

Thanh Nguyen said:


> View attachment 2533670
> 
> Anyone here using EVGA mobo? No idea why I can post in asus dark hero but no post with evga dark


What kinda vdimm you running


----------



## Thanh Nguyen

o1dschoo1 said:


> What kinda vdimm you running


1.6v
Its weird even flck1900 mem3800 stock timming and it cant even post. The evga bios is different than asus so not sure I need to do something else.


----------



## jayfkay

What are some boards that you guys would recommend for RAM OC in medium price range? I was thinking something like B550i Aorus Pro or B550i Phantom ITX but I don't know much about AM4.
I plan on using 2x16 B-Die but 4x8 might be an option

Tips would be appreciated please, I figured for comp gaming with low settings Zen 3 currently takes the cake so I am ditching Intel after 10 years


----------



## o1dschoo1

jayfkay said:


> What are some boards that you guys would recommend for RAM OC in medium price range? I was thinking something like B550i Aorus Pro or B550i Phantom ITX but I don't know much about AM4.
> I plan on using 2x16 B-Die but 4x8 might be an option
> 
> Tips would be appreciated please, I figured for comp gaming with low settings Zen 3 currently takes the cake so I am ditching Intel after 10 years


B550 taichi


----------



## o1dschoo1

jayfkay said:


> What are some boards that you guys would recommend for RAM OC in medium price range? I was thinking something like B550i Aorus Pro or B550i Phantom ITX but I don't know much about AM4.
> I plan on using 2x16 B-Die but 4x8 might be an option
> 
> Tips would be appreciated please, I figured for comp gaming with low settings Zen 3 currently takes the cake so I am ditching Intel after 10 years


I'll actually expand on that I should've put some clarity In that. My x570 aorus wouldn't do cl14 4x8 bdie not would my x299 apex across 4 different CPUs and my taichi does it no issue with a 3800xt. Ryzen 5k has a better memory controller I wouldn't doubt 4k on this board.


----------



## Thanh Nguyen

Its so weird for EVGA dark. I boot up easily 4000/2000 cl14 but no post 3800/1900 stock timming.


----------



## iraff1

ManniX-ITA said:


> Check for a good profile here:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> Look at the image on the screenshot of proof column for the 4x8GB B-die configs.
> There's usually a Zentimings ss.
> You can get any at 3733 and above but don't go for the very aggressive ones, start with something not too exaggerated.
> Consider tRCDRD at 14 could not hold with better timings and pick something with VDIMM at 1.5V or below.


thanks! lots of stuff to test in this list.

I have a starting base now which is 100% stable passed 10 runs of memtest while i was sleeping:









Surprisingly even though (in my eyes) these timings look tight my latency i aida64 is still 60, i expected something like 50-55, so which timing exaclty is the most important one to actually get some points in the latency test?


----------



## ManniX-ITA

iraff1 said:


> Surprisingly even though (in my eyes) these timings look tight my latency i aida64 is still 60ms, i expected something like 50-55, so which timing exaclty is the most important one to actually get some points in the latency test?


At 3773 MHz probably best you can do is 55ms.
I'm not sure, 60ms seems a lot for this profile... there's a lot that can improve but probably you also need 1.5V on DIMM.
tFAW at 16 and lower tRFC, tRTP/tWR at 6/12, 7/14, 8/16 can help a lot latency.
Also tWTRS/tWTRL 4/10. tRRDL at 6. tRDRD 4/4 and tWRWR 6/6.
Lot of small stuff that can be improved.
But a good profile is a well balanced profile.
Not always going down with numbers is the best thing to do.

Also I forgot; it's more challenging but you can get better performances with GDM Off and 2T.
But if something is not well balanced it'll be slower than with GDM.


----------



## Audioboxer

iraff1 said:


> thanks! lots of stuff to test in this list.
> 
> I have a starting base now which is 100% stable passed 10 runs of memtest while i was sleeping:
> View attachment 2533699
> 
> 
> Surprisingly even though (in my eyes) these timings look tight my latency i aida64 is still 60, i expected something like 50-55, so which timing exaclty is the most important one to actually get some points in the latency test?


With a 5950x the lowest you're going to see at 3800, let alone 3733 is around 54ns. 2 CCD "tax". I would probably expect 3733 to be around 55~57 when fully optimised. As you're running 4x8GB you might find it a bit more of a challenge to get down to exactly where 2x8GB or even 2x16GB get.

The first thing you should be working on before worrying about latency is getting GDM disabled. Turn it off, go to 2T for now and see if you can begin your base there.


----------



## Mach3.2

Audioboxer said:


> With a 5950x the lowest you're going to see at 3800, let alone 3733 is around 54ns. 2 CCD "tax". I would probably expect 3733 to be around 55~57 when fully optimised. As you're running 4x8GB you might find it a bit more of a challenge to get down to exactly where 2x8GB or even 2x16GB get.
> 
> The first thing you should be working on before worrying about latency is getting GDM disabled. Turn it off, go to 2T for now and see if you can begin your base there.


Best I did on 2*8GB Patriot Viper Steels is about 54.7ns, but that was really with nothing running.


----------



## Audioboxer

Mach3.2 said:


> Best I did on 2*8GB Patriot Viper Steels is about 54.7ns, but that was really with nothing running.


That's without the 2 CCD "tax" as well. If you got that to a flat 14 or even 13-14-14-14 I guess you'd maybe see 53.x which on a 5950x would be nearer 55.x~56.x.


----------



## ManniX-ITA

Audioboxer said:


> That's without the 2 CCD "tax" as well. If you got that to a flat 14 or even 13-14-14-14 I guess you'd maybe see 53.x which on a 5950x would be nearer 55.x~56.x.


That's a 5900X so the tax is there. The latency is good cause it's a 1T profile. Hard to achieve with flat 14.


----------



## Audioboxer

ManniX-ITA said:


> That's a 5900X so the tax is there. The latency is good cause it's a 1T profile. Hard to achieve with flat 14.


Ah yeah, correct, I read that as 5800x for some reason. Forgot the 5900x existed


----------



## Requiem4u

Thanh Nguyen said:


> Its so weird for EVGA dark. I stock timming.


You say that with EVGA you can boot up easily 4000/2000 cl14 but no post 3800/1900. But with Dark Hero and the same prosessor you can boot up 3800/1900?
I think you can post 3733/1866 or 3770/1885 (little higher FSB). Your system has that hole at 1900. I think it is combination of BIOS and CPU. I have it now (3801 bios, Dark Hero), had not with stock bios.


----------



## TheBoy08

Audioboxer said:


> tCWL to 14 and tRDWR to 8 or 9.
> 
> As for GDM disabled not posting, try 2T first and if that doesn't work GDM is currently masking issues with your timings. Loosen some things up to see what gets GDM 2T booting. SCLs to 4 is an easy go to, then tRAS to 24~28. Or tWTRS to 4.
> 
> 2T will boot at some point. VDDP should be OK at 0.9v. VSOC being a bit higher might even help with GDM.


I've set everything as you said. GDM disabled (I even tried with higher VSOC) still doesn't post also I get this weird behavior where I set command rate to 2T, it accepts and and posts but when I check on Zen Timings it still says command rate 1.
Here's the updated screenshot:











MrHoof said:


> @TheBoy08 no ramdom timeouts in tm5 with tras at 21? If yes I would suggest 14-8-15-14-26-40.
> 
> Also your VDDP is probably way to high lower it until u see tPHYRDL drop to 28 on one stick. This needs a forced memory training in some way like changing a timing like trdwr to auto. Changing VDDP alone else will only affect memory training on cold boot.


No random timeouts in tm5 at tras 21.
I've tried what you said and it doesn't post at all.


----------



## Audioboxer

TheBoy08 said:


> I've set everything as you said. GDM disabled (I even tried with higher VSOC) still doesn't post also I get this weird behavior where I set command rate to 2T, it accepts and and posts but when I check on Zen Timings it still says command rate 1.
> Here's the updated screenshot:
> View attachment 2533736
> 
> 
> 
> No random timeouts in tm5 at tras 21.
> I've tried what you said and it doesn't post at all.


GDM isn't disabled. MSI mobo/bios here, but I'm guessing ASUS requires you to manually disable GDM rather than just switch to 2T?


----------



## TheBoy08

Audioboxer said:


> GDM isn't disabled. MSI mobo/bios here, but I'm guessing ASUS requires you to manually disable GDM rather than just switch to 2T?


Yes. Asus BIOS have both. You can choose wether or not to disable GDM and wether you wanna run command rate 1 or 2


----------



## Requiem4u

TheBoy08 said:


> Yes. Asus BIOS have both. You can choose wether or not to disable GDM and wether you wanna run command rate 1 or 2


Disable GDM and set 2T at the same time.


----------



## TheBoy08

Requiem4u said:


> Disable GDM and set 2T at the same time.


This is what I've done and it doesn't post


----------



## iraff1

ManniX-ITA said:


> At 3773 MHz probably best you can do is 55ms.
> I'm not sure, 60ms seems a lot for this profile... there's a lot that can improve but probably you also need 1.5V on DIMM.
> tFAW at 16 and lower tRFC, tRTP/tWR at 6/12, 7/14, 8/16 can help a lot latency.
> Also tWTRS/tWTRL 4/10. tRRDL at 6. tRDRD 4/4 and tWRWR 6/6.
> Lot of small stuff that can be improved.
> But a good profile is a well balanced profile.
> Not always going down with numbers is the best thing to do.
> 
> Also I forgot; it's more challenging but you can get better performances with GDM Off and 2T.
> But if something is not well balanced it'll be slower than with GDM.


Thanks for the tips, about GDM, the strange thing is i get a ton of errors in memtest with GDM off even at xmp profile 3600mhz and 1.48v so throwing more voltage doesn't seem to help with GDM at all, any ideas why this is? Perhaps one of the stock 14-14-14- timings are too low for to go without GDM or is there some other voltage that could potentially be tweaked to get GDM off to function at this low latency (other than vdimm that is)


----------



## ManniX-ITA

iraff1 said:


> Thanks for the tips, about GDM, the strange thing is i get a ton of errors in memtest with GDM off even at xmp profile 3600mhz and 1.48v so throwing more voltage doesn't seem to help with GDM at all, any ideas why this is? Perhaps one of the stock 14-14-14- timings are too low for to go without GDM or is there some other voltage that could potentially be tweaked to get GDM off to function at this low latency (other than vdimm that is)


Yes, could be GDM is making some other background adjustments.
And probably 1.5V is not enough for flat 14. Try if you get errors also setting tRCDRD to 16.
Maybe it's a matter of RTT.
I'm not an expert with Single Rank modules but I remember a different RTT for them, 7/3/1 seems weird. Is this Auto or manually set?


----------



## PJVol

@domdtxdissar
I saw you complained to a Zen RamOC Leaderboards  owner regarding "diluting" scoreboard with the APU results.
Would it be fair then to complain about results from the 5600X 2xCCD owners as well, since 2100 stable FCLK OC is only possible because of their unique architecture?
Does anyone else here have an opinion on this?


----------



## iraff1

ManniX-ITA said:


> Yes, could be GDM is making some other background adjustments.
> And probably 1.5V is not enough for flat 14. Try if you get errors also setting tRCDRD to 16.
> Maybe it's a matter of RTT.
> I'm not an expert with Single Rank modules but I remember a different RTT for them, 7/3/1 seems weird. Is this Auto or manually set?


Yes these are auto, maybe i should copy the ones that are from the Mem Caluclator even though they are not optimizer for ryzen 5000? But there is a template for 4x single rank @ 3600 in that calculator.

Mem calc gives me 
PROCOTD: 40
RTT_NOM RZQ/7(34)
RTT_WR OFF
RTT_PARK RZQ/5 (48) 

As recommended values.


----------



## ManniX-ITA

PJVol said:


> Does anyone else here have an opinion on this?


Then we should not mix single with dual CCD or dual CCD with only one enabled... or air cooling with water cooling?
You can always copy the spreadsheet and filter it.
I'm not keen in fragmentation, I would keep the APU in the same sheet.



iraff1 said:


> Yes these are auto, maybe i should copy the ones that are from the Mem Caluclator even though they are not optimizer for ryzen 5000? But there is a template for 4x single rank @ 3600 in that calculator.
> 
> Mem calc gives me
> PROCOTD: 40
> RTT_NOM RZQ/7(34)
> RTT_WR OFF
> RTT_PARK RZQ/5 (48)
> 
> As recommended values.


My bad, it's the correct RTT for 4xSR.
If you check the spreadsheet there are some alternatives but that's the default.


----------



## Audioboxer

TheBoy08 said:


> This is what I've done and it doesn't post


If you can't post 2T with 2x8GB SR then something is pretty _unstable_. In other words, GDM masking/fixing issues. To rule out voltages/resistance, drop that ClkDrvStr down to 30/40 and up your VSOC to 1.125v and try 2T again.

If it still doesn't post go flat 16 with primaries (16-16-16-16) and see if that gets it up and running.


----------



## Blameless

TheBoy08 said:


> I've set everything as you said. GDM disabled (I even tried with higher VSOC) still doesn't post also I get this weird behavior where I set command rate to 2T, it accepts and and posts but when I check on Zen Timings it still says command rate 1.


GDM is always listed as "1T" as all address/command signals are driven for two cycles with it enabled, perforce.

You may need to loosen other timings, or adjust other settings to get GDM disabled to work.

Depending on the system, GDM enabled may be the fastest option. Of all my AM4 setups only my Samsung B-die (and some of my ancient Micron stuff that can't scale past 2667 anyway) is actually faster with GDM disabled than what it can do with it enabled, and even then some of my boards don't like GDM off with higher memory densities.

That said, just two single-rank B-die DIMMs should take GDM disabled pretty easily. You might need more vSoC (it's a bit too close to VDDG IOD), or a looser tRTP, tWTR_L, or tWRRD. In a worst case scenario, loosening tRDRDSCL by one should get GDM disabled working, but if you have to do this it may cost more performance than it gets you.



iraff1 said:


> Thanks for the tips, about GDM, the strange thing is i get a ton of errors in memtest with GDM off even at xmp profile 3600mhz and 1.48v so throwing more voltage doesn't seem to help with GDM at all, any ideas why this is?


GDM is spec for DDR4 past 2666 and XMP usually won't disable it. Doing so is often going to require some additional work, especially if the board or IMC/PHY are weak, or you're running four DIMMs in a daisy chain board.


----------



## iraff1

ManniX-ITA said:


> tRDRD 4/4 and tWRWR 6/6.


regarding these, i cannot find them in my bios, are they split into 4 segments?
i see
trdrdsc
trdrdsd
trdrddd
trdrd_scl

and

twrwrsc
twrwrsd
twrwrdd
twrwr_scl

do i change all of these to the values you mention or am i missing something?

Its getting better! 1900flck is stable too but i had some issues previously where if the computer sleeps for over 1 hour whenever i resume it from sleep at flck1900 i get popping noises in my sound and weird usb hickups, this only occurs if the computer sleeps for long period at flck1900 but not at flck 1866, sorta strange, i am hoping new memories may have resolved it so testing 1900 for now


----------



## ManniX-ITA

iraff1 said:


> regarding these, i cannot find them in my bios, are they split into 4 segments?


Yes sorry, it's the duo SD/DD for both. Now are 4/5 and 6/7


----------



## Taraquin

ManniX-ITA said:


> I bought the Trident Royal Z 4266C17 and they were same as the Trident Z 4000C16.
> Got more lucky with the 4000C14 kit.
> Could be you can get CL14 flat at 3800 but it's unlikely.
> 
> 
> 
> CCD at 820mV? Isn't very low?


Yeah, but performance is identical at 820 and 900mv. I run the lowest stable without performance degradation since it uses less pwr budget from the IO-die. I know it can vary greatly depending on CPU, motherboard etc. Tested my 3600 on a Gigabyte B450M DS3H and a B550M DS3H. At the first I ran ccd at 825mv, on the latter it won't boot below 900mv.


----------



## ManniX-ITA

Taraquin said:


> Yeah, but performance is identical at 820 and 900mv. I run the lowest stable without performance degradation since it uses less pwr budget from the IO-die. I know it can vary greatly depending on CPU, motherboard etc. Tested my 3600 on a Gigabyte B450M DS3H and a B550M DS3H. At the first I ran ccd at 825mv, on the latter it won't boot below 900mv.


Wow it's really good.
I check the CCD voltage with Geekbench 5.
If it's too low some benchmarks are dropping scores, especially AES-XTS.
Give it a try.
My 5950x needs 1020, almost 200mV difference


----------



## Taraquin

ManniX-ITA said:


> Wow it's really good.
> I check the CCD voltage with Geekbench 5.
> If it's too low some benchmarks are dropping scores, especially AES-XTS.
> Give it a try.
> My 5950x needs 1020, almost 200mV difference


I can try the aes-xts, maybe it is too low  It seems like 2 ccds in general needs more ccd voltage than 1. I would guess 5800X would need more than 5600X aswell, but not sure.


----------



## Taraquin

TheBoy08 said:


> I've set everything as you said. GDM disabled (I even tried with higher VSOC) still doesn't post also I get this weird behavior where I set command rate to 2T, it accepts and and posts but when I check on Zen Timings it still says command rate 1.
> Here's the updated screenshot:
> View attachment 2533736
> 
> 
> 
> No random timeouts in tm5 at tras 21.
> I've tried what you said and it doesn't post at all.


Try 15 15 15
30 ras
45 rc
272 rfc
8 wtrl
12 wr

Disable gdm, 2T

Clkdrvstr 40, others to 20, 30, 20

Try 1.48V dimm. 

See if that boots and is stable. If it is you can try setting rfc to 264 or 256, you can try 10/5 wr/rtp and lower ras, but remember rc = ras + rp.


----------



## PJVol

ManniX-ITA said:


> If it's too low some benchmarks are dropping scores, especially AES-XTS.


With a 5600X, they (ccd/iod) don't matter much. I've them set at 0.95V currently and vsoc 1.00V, but 0.900 is fine also.
Here are GB5 results with VDDG's 900mv and 950mv respectively:





Test 2 - Geekbench Browser


Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.



browser.geekbench.com









Test 1 - Geekbench Browser


Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.



browser.geekbench.com


----------



## Taraquin

PJVol said:


> With a 5600X, they (ccd/iod) don't matter much. I've them set at 0.95V currently and vsoc 1.00V, but 0.900 is fine also.
> Here are GB5 results with VDDG's 900mv and 950mv respectively:
> 
> 
> 
> 
> 
> Test 2 - Geekbench Browser
> 
> 
> Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.
> 
> 
> 
> browser.geekbench.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Test 1 - Geekbench Browser
> 
> 
> Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.
> 
> 
> 
> browser.geekbench.com


Iod matter a lot for ram oc atleast on my setup. 3800 needs 980mv and 4000 needs 1030mv, below performance tanks. At 3600 sub 950mv iod is probably fine.


----------



## Audioboxer

I used to run my CCD and IOD at 0.975v when I first started out with memory overclocking, but in the later months I have just left my IOD at 1.05v at 3800 and it seems to be fine. CCD is still at 0.975v, I've had it as low as 0.925v, but never kept it there. My GB5 score from earlier as I presume memory helps with GB Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser

I've been browsing the GB site for 5950x results and it seems my multicore result is decent for PBO but single core could be higher. I guess my 5050mhz ceiling holds me back as I've seen some results at 5200mhz. Most times I play with AutoOC I tend to find it hurts my multicore performance.

I guess it's like threading the eye of a needle trying to balance multicore and single core on 5xxx processor. Combined with having the perfect BIOS settings.

*edit* - +50 is usually OK with AutoOC https://browser.geekbench.com/v5/cpu/11135330 Though it's not really doing anything for single core, MOE.

In other news










When you know winter is coming 🥶


----------



## Reknez

Hey everyone,

I was sent here by Veii to ask for old bookmarked links of him for DRAM OC help. He told me that it is being collected and bookmarked by someone from across the pages here. 

Thank you!


----------



## mongoled

PJVol said:


> @domdtxdissar
> I saw you complained to a Zen RamOC Leaderboards owner regarding "diluting" scoreboard with the APU results.
> Would it be fair then to complain about results from the 5600X 2xCCD owners as well, since 2100 stable FCLK OC is only possible because of their unique architecture?
> Does anyone else here have an opinion on this?


I think ideally each section of the "leaderboard" should be for CPUs that are architecturaily the same.

So in the case of Zen3 it would be, 1 CCD, 2 CCD, then APUs, obviously this will need more work and maintenance.

The main "issue" for peeps is that it is callled a "leaderboard" so obviously you want things to be like for like as much as possible ...


----------



## ManniX-ITA

PJVol said:


> With a 5600X, they (ccd/iod) don't matter much. I've them set at 0.95V currently and vsoc 1.00V, but 0.900 is fine also.
> Here are GB5 results with VDDG's 900mv and 950mv respectively:
> 
> 
> 
> 
> 
> Test 2 - Geekbench Browser
> 
> 
> Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.
> 
> 
> 
> browser.geekbench.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Test 1 - Geekbench Browser
> 
> 
> Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.
> 
> 
> 
> browser.geekbench.com


Depends a lot also on the AGESA/BIOS but indeed single CCD it's easier.
Some samples are more flexible others (often those that needs a very specific IOD voltage to avoid audio/USB issues) needs a very specific one.
My 3800X was working perfectly at CCD/IOD 900/950 with the first AGESA releases, now it needs 950/1050. 

You can send the URL with already the comparison with the baseline 



Test 2 vs Test 1 - Geekbench Browser



Seems Test 2 is slightly better 

I try to go as high and down as possible to find where the scores are dropping and then going for a 75%.
In the middle it can be enough for Geekbench 5 but then struggling with y-cruncher.


----------



## Blameless

I've noticed that, at least on my current 5800X sample, too low of a CLDO VDDG CCD voltage significantly harms the PBO curves I'm able to stabilize, especially on the last four cores.


----------



## ManniX-ITA

Blameless said:


> I've noticed that, at least on my current 5800X sample, too low of a CLDO VDDG CCD voltage significantly harms the PBO curves I'm able to stabilize, especially on the last four cores.


I guess you mean the CO counts?
Same on my 5950X, most of the cores. Also IOD voltage helped a lot.


----------



## iraff1

ManniX-ITA said:


> Depends a lot also on the AGESA/BIOS but indeed single CCD it's easier.
> Some samples are more flexible others (often those that needs a very specific IOD voltage to avoid audio/USB issues) needs a very specific one.
> My 3800X was working perfectly at CCD/IOD 900/950 with the first AGESA releases, now it needs 950/1050.


I find this interesting as it may tie into a particular strange issue i have that requries the following prerequisites to be able to recreate on my system

1. FLCK has to be 1900 or higher
2. Computer has to sleep for more than 1 hour, if it only sleeps for 10 minutes the problem does not occur.

The problem: When computer resumes from long sleep (1+ hour) at FLCK 1900+ i will have USB issues/WHEA Errors and popping/crackling sound from any sound output. A reboot resolves the problem.

Setting FLCK to 1866 or lower resuming from sleep works fine. No issues.

My voltages:








System is on AGESA ComboV2 1.2.0.3 B, Seasonic 850W Platinum rated psu, do you have any ideas to which voltage that may be issue here? Its really annoying because 1900 flck is 100% stable but consider i do a lot of work with my system i like to resume having all my stuff open at morning rather having to re-open everything from a cold boot.

Thanks for all your advice so far!


----------



## ManniX-ITA

iraff1 said:


> System is on AGESA ComboV2 1.2.0.3 B, Seasonic 850W Platinum rated psu, do you have any ideas to which voltage that may be issue here? Its really annoying because 1900 flck is 100% stable but consider i do a lot of work with my system i like to resume having all my stuff open at morning rather having to re-open everything from a cold boot.


There are many options which can influence this issue. And they influence each other so you need to find the right combo.
Unfortunately in some cases it's not possible to fix it with some boards.
It's really dependent on the BIOS quality and AGESA version/patch and.. luck with sample 

Also I've been quite lucky for a while but then at some point I started having the same issues out of the blue.
Now seems I've found a combination that works but I'm not 100% sure it works.
In general if my PC goes into standby for quite some time, I reboot ASAP.

These are the options to play with:

Power Supply Idle Control: Low or Typical (could have an impact on the ability of the cores to go to sleep in C state)
I was doing really good with Typical till it didn't work anymore... maybe Chipset drivers have an impact. Now it's working find only with Low Current Idle
You have to test which one works, best would be Low

Global C-state Control: Enabled
Sometimes it just doesn't work if Enabled but of course Disabled has multiple impacts, better to make it work with Enabled instead

AMD CBS NBIO
DF C-states: Enabled/Disabled
You have to try, my 5950x is unstable if Disabled. In Auto and in general Disabled is more stable

APBDIS: Auto
With Manual selection for me it's unstable at resume. Could be the opposite for others

NBIO LCLK DPM: Auto
Same an APBDIS for me


Settings
ERP Ready: Enabled
When Enabled the board is really shutting down completely (no USB is kept with power on). Disabled for me is unstable.


----------



## PJVol

iraff1 said:


> ... a particular strange issue i have...


Don't know will it help, but I strongly encourage you to read this post from an Anandtech user - he definitely had a weirdest experience I've ever seen  :





Page 59 - AMD Ryzen 5000 Builders Thread


Page 59 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.




forums.anandtech.com


----------



## ManniX-ITA

PJVol said:


> Don't know will it help, but I strongly encourage you to read this post from an Anandtech user:


Wow, Seasonic is going down the drain...
I've read about an impressive amount of users in the 3080ti/3090 threads having similar issues with old and brand new ones.
Once they got the new GPU it couldn't keep up and rebooting the system, 12V rails going down during stress test.


----------



## PJVol

ManniX-ITA said:


> I've read about an impressive amount of users in the 3080ti/3090 threads having similar issues


I heard of it a bit earlier, when people on OC UK forums complained about their Vega 56/64 crashing, lol


----------



## iraff1

ManniX-ITA said:


> There are many options which can influence this issue. And they influence each other so you need to find the right combo.
> Unfortunately in some cases it's not possible to fix it with some boards.
> It's really dependent on the BIOS quality and AGESA version/patch and.. luck with sample
> 
> Also I've been quite lucky for a while but then at some point I started having the same issues out of the blue.
> Now seems I've found a combination that works but I'm not 100% sure it works.
> In general if my PC goes into standby for quite some time, I reboot ASAP.
> 
> These are the options to play with:
> 
> Power Supply Idle Control: Low or Typical (could have an impact on the ability of the cores to go to sleep in C state)
> I was doing really good with Typical till it didn't work anymore... maybe Chipset drivers have an impact. Now it's working find only with Low Current Idle
> You have to test which one works, best would be Low
> 
> Global C-state Control: Enabled
> Sometimes it just doesn't work if Enabled but of course Disabled has multiple impacts, better to make it work with Enabled instead
> 
> AMD CBS NBIO
> DF C-states: Enabled/Disabled
> You have to try, my 5950x is unstable if Disabled. In Auto and in general Disabled is more stable
> 
> APBDIS: Auto
> With Manual selection for me it's unstable at resume. Could be the opposite for others
> 
> NBIO LCLK DPM: Auto
> Same an APBDIS for me
> 
> 
> Settings
> ERP Ready: Enabled
> When Enabled the board is really shutting down completely (no USB is kept with power on). Disabled for me is unstable.


So you have similar issues at some points with your 5950x too? Okay maybe this isn't as uncommon as i though then to us overlockers, thanks for a lot of different good stuff i can test, trial and error is the key but it will take time because i only get to make 1 test per night  Appreciate the infos!


----------



## mongoled

ManniX-ITA said:


> Wow, Seasonic is going down the drain...


That was a quick conclusion

😂 😂


----------



## iraff1

PJVol said:


> Don't know will it help, but I strongly encourage you to read this post from an Anandtech user - he definitely had a weirdest experience I've ever seen  :
> 
> 
> 
> 
> 
> Page 59 - AMD Ryzen 5000 Builders Thread
> 
> 
> Page 59 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.
> 
> 
> 
> 
> forums.anandtech.com


Thanks, damn... i had good trust in seasonic, but not because i am an expert in PSUs just that they have recieved praise in the past for having good components in their PSUs. I will try with the stuff ManniX-ITA gave me first then i might take a look at the PSU, i do have some other brand psus laying around that are technically much lower quality but could be worth trying if nothing else works.


----------



## ManniX-ITA

iraff1 said:


> So you have similar issues at some points with your 5950x too?


With the 3800x and the 3600xt as well... very common issue since ever sadly.
Happens also with stock settings but of course gets more tricky with OC.
I've tested latest DF C-State, APBDIS and DPM settings and it was a disaster 



mongoled said:


> That was a quick conclusion


Not really quick but also just my impression 
It was really really uncommon to see complaints about Seasonic till a while ago, now seems it happens very frequently...


----------



## mongoled

ManniX-ITA said:


> Not really quick but also just my impression





 impression - Google Search



So quick....."especially one formed without conscious thought or on the basis of little evidence "

😀 😀

I just retired my Seasonic X-750 Gold after 10 years of continuous use and overclocking and have just replaced it with a Seasonic Prime 850 Titanium.

After researching for a day regards "best" PSU I can say that my impression does not match yours.

Only issue I found was some of the older Prime units had an issue with 12v rail and these PSU could be exchanged via Seasonic for replacements or you did a quick trick by placing a small ferrite core on the 12v sense wire (think it was the 12v sense wire).

Oh and 12 year warranty for the Prime titanium.

Takes a whole lot more evidence in my World to say a company is going down the drain


----------



## ManniX-ITA

mongoled said:


> Takes a whole lot more evidence in my World to say a company is going down the drain


Of course it was an exaggeration 

I didn't see as many complaints in the last 10 years about Seasonic as much as in the last 3 months.
When you are on top of excellence these stark differences are very noticeable.
If it was about Gigabyte PSUs... normal routine 
Could be just a bad batch, happens also to the best.

I really hope it's nothing more cause it was a very good candidate for my next PSU...
This only if one day my lucky EVGA Supernova G2 will give up which doesn't seem likely to happen soon.


----------



## mongoled

ManniX-ITA said:


> This only if one day my lucky EVGA Supernova G2 will give up which doesn't seem likely to happen soon.


Hope you the best with this one!

My Seasonic is still alive and kicking, just thought it was a good idea after 10 years to retire it


----------



## ManniX-ITA

mongoled said:


> Hope you the best with this one!
> 
> My Seasonic is still alive and kicking, just thought it was a good idea after 10 years to retire it


Fingers crossed!

I really can't convince myself to spend 500 € for something that I don't really need... I tried 
Except maybe efficiency? Neither, it's 80+ Gold, a matter of few watts...
It's still perfect and I wouldn't gain anything more with a new one.
Today the prices for 1300W+ are crazy, I bought this one 8 years ago for peanuts, 181 €...


----------



## iraff1

interesting, it seems ERP has an effect on my memory overclocking , with it enable my memory wont clock as high (not passing memtest)... here i go thinking ERP would only affect things when you slept the system


----------



## Audioboxer

I know you guys don't mind a little bit of crossover with CPU stuff in here, especially if it relates to benching where memory is important, so just for feedback I'll also ask in this topic do any of you have any experience running telemetry on the CPU side?

In the past 24 hours I've gone from struggling to get above 308xx in CB23 to 313xx and also improved GB5 MT from 199xx to 201xx all by "simply" copying this










Screenshot thanks to KedarWolf.

But now it's led me to a new rabbit hole that is running the CPU out of spec Explaining the AMD Ryzen "Power Reporting Deviation" -metric in HWiNFO










So it's great to see sustained all core loads above 4.7ghz, resulting in better benchmarks and even games that use multicore are now running frequencies higher, but this whole thing reminds me a bit of the EDC bug.

Temps are absolutely fine but the PPT/TDC reported usage in HWINFO and even Ryzen Master seems to be totally wrong, leading you to wonder what is being pumped through your CPU to achieve much improved performance.

Given that a source of talking about this bias is aimed at mobo manufacturers, I'm even now wondering if some people get better benchmarks across mobo brands due to the way the manufacturers sign off internal values when handling AGESA...


----------



## Imprezzion

Well, I got bored and it's Black Friday sales here and couldn't resist the urge.. 

I bought a 5900X and a ASUS B550-XE board.

Going to be re-using my B-Die I am running in my Intel 10900KF rig now. They will be replaced by a 2x8GB Kingston Beast 3600C17's I could get cheap and that set goes to a buddy who still rocks a 2500K lol.

My sticks are G.Skill Trident-Z Neo 3600C16 which I have always run at 4400 17-17-27-38-328-2T @ 1.50v on Z490. I'm assuming 4400 isn't very efficient on AMD due to not running 1:1 IF so what should I shoot for? 3800C14? Any tips where to start lol? I have to completely learn both RAM and CPU OC again as I have not used any Ryzen CPU at all let alone clocked one..

It's under a full custom loop, hwlabs GTX 420 + 240 push pull, EK D5 + res, EK Supremacy EVO block (maybe buying a new block for it tho).

And what TIM should I use on a mirror lapped block. Does LM work on AMD? I have loads of Coollaboratory Liquid Ultra here for Intel direct die stuff or should I just use PK-3 / MX-5?


----------



## Leftezog

Hello to everybody. Having a VERY HARD time stabilizing 4 dimms consisting of 2 kits of F4-3600C16D-16GTZNC with my 3900x and Asus x370 pro. They are all Hynix CJR as they have the same code on them. Checked each dimm individually and all my motherboard slots individually and didn't produced any error in extreme anta777 in order to see if I had a problem with my motherboard as the 4 dimms altogether would not be stable even at 2133 at stock settings. When tested all these and reassured that my motherboard isn't faulty I started to oc the ram again. and we have the following SUPER weird results.

Memory anta stable at 2133


Spoiler: 2133















And now the weird things.

Memory stable 3200 anta at 250%(reduced time in config file) forgot to screenshot it with the TM5 on. Closed it accidentally and after I screenshoted.



Spoiler: 3200 anta 250% pass















Just restarted the computer to retest again because I couldn't believe my eyes that the test passed and voila the magic thing happens. First 20 minutes and 4 errors in extreme anta777(500% time in this one default config file)



Spoiler: 3200 anta fail at 500%















Now the other weird thing. Universal Lmhz config passed the test with the same settings.



Spoiler: uni 3200 pass















After that I started to test the memory in lower frequency on order to see maybe easier what the problem in the settings is. Chose the frequency 2733 for my testing. In this frequency I have the same problems too. Most of the time Lmhz config will pass the test and extreme anta 777 will mostly produce 2 erros in test 2 or 0 in cycle 2 or 3. Below you will see and excell file screenshot with what I tested so far. Most Lmhz tests are missing from the list because even if the passed the config wasn't extreme anta777 stable anyway. Also the fan collumn means that I have a fan blowing on ram. Max temps are 35 celcius. Also COLDBOOT means in these PROCODT settings when I restarted the computed passed the bios post but I had black screen after loading animation the one with the motherboards Logo just before entering windows desktop. So I was raising PROCODT in order to boot properly. For your information I am doing this 15 days now for about 6-8 hours a day and I am starting to get a little tired. :-/



Spoiler: Excell tests















Any help appreciated.


----------



## ManniX-ITA

Leftezog said:


> Hello to everybody. Having a VERY HARD time stabilizing 4 dimms consisting of 2 kits of F4-3600C16D-16GTZNC with my 3900x and Asus x370 pro. They are all Hynix CJR as they have the same code on them. Checked each dimm individually and all my motherboard slots individually and didn't produced any error in extreme anta777 in order to see if I had a problem with my motherboard as the 4 dimms altogether would not be stable even at 2133 at stock settings. When tested all these and reassured that my motherboard isn't faulty I started to oc the ram again. and we have the following SUPER weird results.


My DR kit was Hynix DJR not CJR. But they are very similar.

Is that the XMP profile?
It may not work really well with 4 DIMMs.

If you need help please use the 1usmus v3 config for TM5.
The errors have knowledge and documentation, courtesy of Veii.

I'd try:

Higher VSOC, it's very close to VDDG set it to 1.15V
Force CCD to 950mV and IOD to 1050mV if possible
Try witch ClkDrvStr set to 40/60
Try DrvStr 24/24/24/24
Force tCKE to 1
tWTRS/tWTRL to 4/12 or 5/14
Different tRDWR/tWRRD combinations; 10/2 11/2 8/4 9/4 8/3 9/3
This is my profile for the DR kit:










You can have give it a try but consider different tRDWR/tWRRD and SCL for SR probably best 3/3 or 5/5.


----------



## Leftezog

ManniX-ITA said:


> My DR kit was Hynix DJR not CJR. But they are very similar.
> 
> Is that the XMP profile?
> It may not work really well with 4 DIMMs.
> 
> If you need help please use the 1usmus v3 config for TM5.
> The errors have knowledge and documentation, courtesy of Veii.
> 
> I'd try:
> 
> Higher VSOC, it's very close to VDDG set it to 1.15V
> Force CCD to 950mV and IOD to 1050mV if possible
> Try witch ClkDrvStr set to 40/60
> Try DrvStr 24/24/24/24
> Force tCKE to 1
> tWTRS/tWTRL to 4/12 or 5/14
> Different tRDWR/tWRRD combinations; 10/2 11/2 8/4 9/4 8/3 9/3
> This is my profile for the DR kit:
> 
> View attachment 2533974
> 
> 
> You can have give it a try but consider different tRDWR/tWRRD and SCL for SR probably best 3/3 or 5/5.





ManniX-ITA said:


> My DR kit was Hynix DJR not CJR. But they are very similar.
> 
> Is that the XMP profile?
> It may not work really well with 4 DIMMs.
> 
> If you need help please use the 1usmus v3 config for TM5.
> The errors have knowledge and documentation, courtesy of Veii.
> 
> I'd try:
> 
> Higher VSOC, it's very close to VDDG set it to 1.15V
> Force CCD to 950mV and IOD to 1050mV if possible
> Try witch ClkDrvStr set to 40/60
> Try DrvStr 24/24/24/24
> Force tCKE to 1
> tWTRS/tWTRL to 4/12 or 5/14
> Different tRDWR/tWRRD combinations; 10/2 11/2 8/4 9/4 8/3 9/3
> This is my profile for the DR kit:
> 
> View attachment 2533974
> 
> 
> You can have give it a try but consider different tRDWR/tWRRD and SCL for SR probably best 3/3 or 5/5.


I know there is an error list for 1usmus config but from my testing many times I will pass 6 cycles in 1usmus config with no errors and after fail extreme anta777. So I don't use 1usmus config anymore because of this. I will try the rest of the thing you proposed and report back. Thank you for your answer.


----------



## ManniX-ITA

Leftezog said:


> I know there is an error list for 1usmus config but from my testing many times I will pass 6 cycles in 1usmus config with no errors and after fail extreme anta777. So I don't use 1usmus config anymore because of this. I will try the rest of the thing you proposed and report back. Thank you for your answer.


From my experience if you don't get an error with the 1usmus config it's only cause you did run it for not enough cycles.
You need to run it for at least 25 cycles for a good confidence. With 6 cycles you are definitely missing coverage.
There's also the option to extend the duration of each cycle.
You can run Karhu and anta configs to double check but the main troubleshooting if it's not done with 1usmus you can't get much help.


----------



## Audioboxer

Leftezog said:


> I know there is an error list for 1usmus config but from my testing many times I will pass 6 cycles in 1usmus config with no errors and after fail extreme anta777. So I don't use 1usmus config anymore because of this. I will try the rest of the thing you proposed and report back. Thank you for your answer.


6 cycles in 1usmus is nothing. Not sure it's even long enough for thermal equilibrium. The only thing being caught in 3-6 cycles is being very unstable.

If your thermals are on the edge of stability it may well take an hour or two before the first fail.

Running multiple configs is a good idea anyway, I personally found that 1usmus v3 was catching TM5 timeouts down to tRAS being too low. Anta 777 extreme missed this.


----------



## Leftezog

ManniX-ITA said:


> From my experience if you don't get an error with the 1usmus config it's only cause you did run it for not enough cycles.
> You need to run it for at least 25 cycles for a good confidence. With 6 cycles you are definitely missing coverage.
> There's also the option to extend the duration of each cycle.
> You can run Karhu and anta configs to double check but the main troubleshooting if it's not done with 1usmus you can't get much help.





Audioboxer said:


> 6 cycles in 1usmus is nothing. Not sure it's even long enough for thermal equilibrium. The only thing being caught in 3-6 cycles is being very unstable.
> 
> If your thermals are on the edge of stability it may well take an hour or two before the first fail.
> 
> Running multiple configs is a good idea anyway, I personally found that 1usmus v3 was catching TM5 timeouts down to tRAS being too low. Anta 777 extreme missed this.


Thank you for your suggestions. Didn't run 1usmus config for so many cycles. Also about my thermals I put an 120 fan blowing on ram in order to remove the possibility of overheating. Max ram tems are 35C. I will test all the thing you mentioned an report back. Thank you.


----------



## Audioboxer

Leftezog said:


> Thank you for your suggestions. Didn't run 1usmus config for so many cycles. Also about my thermals I put an 120 fan blowing on ram in order to remove the possibility of overheating. Max ram tems are 35C. I will test all the thing you mentioned an report back. Thank you.


Your thermals will definitely be fine then, with B-die I noticed very tight timings/tRFC tends to flag up issues around 42 degrees and beyond, so if you're in the 30s you're in a great position.

1usmus v3 should still be ran for 20~25 cycles though, 25 cycles being the favourite around here. It tests things slightly differently than Anta777 extreme, as seen by around 3 cycles of Anta being a similar length of time to 20~25 cycles of 1usmus v3.

At the end of the day you can't go wrong with using multiple profiles, 1usmus v3 is popular to start out with in here because Veii put in hours of work to try and identify what an error might mean tRFC mini Emphasis being on "what it might mean". But that is still hugely helpful, especially in the memory game where you can be staring down tens if not 100s of hours of stability testing 💀


----------



## PJVol

Audioboxer said:


> 6 cycles in 1usmus is nothing. Not sure it's even long enough for thermal equilibrium


More than enough in my case, temps stops rising after the 2nd cycle and stays there until finished as on screenshot.


----------



## umea

ManniX-ITA said:


> Of course it was an exaggeration
> 
> I didn't see as many complaints in the last 10 years about Seasonic as much as in the last 3 months.
> When you are on top of excellence these stark differences are very noticeable.
> If it was about Gigabyte PSUs... normal routine
> Could be just a bad batch, happens also to the best.
> 
> I really hope it's nothing more cause it was a very good candidate for my next PSU...
> This only if one day my lucky EVGA Supernova G2 will give up which doesn't seem likely to happen soon.


I think it's relatively safe to say that generally speaking it's at worst a bad batch. Remember that a couple of complaints out of millions of units sold is still an incredibly small minority. Generally speaking the amount of complaints I find about Seasonic PSUs are still unbelievably far and few between.

I use a Corsair SF750 Plat as I'm in SFF, but should I decide to change it or move to an ATX build I'll probably move over to a Seasonic Titanium unit (I probably won't need to though, because I have no need to upgrade GPU and I don't think CPUs will pull more than 300W this next gen at least). Even despite these few complaints I've seen recently about Seasonic PSUs, they're still so much less frequent than literally every other manufacturer.

Edit: didn't realize that this wasn't a one off thing adn that you said for 3090/3080ti users they were experiencing difficulties. Hopefully it's just a bad batch, if not it's concerning as seasonic is indeed generally the best PSU maker.


----------



## Audioboxer

PJVol said:


> More than enough in my case, temps stops rising after the 2nd cycle and stays there until finished as on screenshot.
> View attachment 2533986


That's fair, I'd just recommend those, especially without active cooling, keep in mind it might take a bit longer before temperature related errors pop up.


----------



## dk_mic

Could you have a look at these timings, if there is room for improvement / some timings are too loose or tight?
I can't run higher IF with current BIOS, so I want to optimize at 1900 MHz.
5950x with 2 x Dual Rank 16 GB G.SKILL 3600 CL16 B-Die.
DIMM Voltage is 1.49 V in BIOS, but HWInfo reads 1.52 V. I have a fan keeping them cool enough.
AIDA latency is 54.8 (pretty clean, but not stipped down win10 bench installation)
Seems I can't lower tRCDRD at all (can boot, but plenty of errors in TestMem5).


----------



## Audioboxer

dk_mic said:


> Could you have a look at these timings, if there is room for improvement / some timings are too loose or tight?
> I can't run higher IF with current BIOS, so I want to optimize at 1900 MHz.
> 5950x with 2 x Dual Rank 16 GB G.SKILL 3600 CL16 B-Die.
> DIMM Voltage is 1.49 V in BIOS, but HWInfo reads 1.52 V. I have a fan keeping them cool enough.
> AIDA latency is 54.8 (pretty clean, but not stipped down win10 bench installation)
> Seems I can't lower tRCDRD at all (can boot, but plenty of errors in TestMem5).
> View attachment 2534009


Around 54ns is basically the floor for a 5950x at 3800/1900. You might get into the 53.x range, but not like 53.1~2. So the question more likely shifts to your read/write/copy and if you can push more out of them. 54.8 can be improved though, when I say around 54ns is the floor I'm meaning 53.8~54.2.

You've modelled your timings around GDM 1T, so I'm not too sure what to recommend you try as GDM can interfere with timings. Instead, just so you can see what I mean, try switching to 2T/GDM disabled and see if you can run a 25 cycle TM5 as is.

48 ProcODT IMO is much higher than necessary on a 5xxx processor. 36.9 is usually where DR with a 5950x will sit around. Also to fix your tRFC2/4, the formula for calculating them is *tRFC2* = tRFC / 1.346 *tRFC4* = tRFC2 / 1.625.

Anta advised tRFC itself is best as multiples of 16, your nearest options if you take that advice would be 256 or 272. I would try aiming for 256.


----------



## VPII

mongoled said:


> Glad to see you have made some headway. I have Windows 11 installed on a separate drive but I'm not paying too much attention to it until MS release patches that are shown to fix the outstanding issues with Ryzen CPUs.


Hi @mongoled just wanted to share I manage to get my entire system working with the -20 all core vcurve optimizer, results maybe not as great but how I have done it is by doing a complete fresh install of Windows 11. Yup maybe a bad idea with the issues with AMD Ryzen but it appears to be resolved. Now I have done this with a vcore offset in the bios of -0.0875vcore which was not possible before but it brought down temps under CB23 from 87c ccd temp to 80c which is all I wanted. Here is my result. Funny though before I did the vcore offset my memory latency was around 55 which is great but too great for my memory speed and timings I think.


----------



## tcclaviger

Whelp, decided to inflict mental pain upon myself and ordered a second 2x16 kit, so running 4x16 on the updated strix x570-E II.

After a round of massive OC success with the new board, catching and taking quite a few top spots for non-ln2 single core benchmarks, the bliss had to end sometime. 

It's, going? I guess?!

3933/1966 C14 was fairly easy at 32gb.
3733/1866 won't post, even at 18s flat, 500 trfc, super loose seconds and thirds with 64gb.

Tried a massive assortment of voltage, RTT, CAD, etc values. To no avail.

Getting just this to post took about 4 hours. Have just started turning knobs on dialing the timings tighter, but I did verify 14-13-8-13-21-34 boots with trfc at 260/193/119. Tcwl 14

When people said going 32 to 64 was a big speed compromise, I somehow didn't fully internalize just how drastic it is!

The 48 GB setup, which is 2x16 GSkill 4000c16 and 2x8 Patriot viper 4000s was drastically easier to tune fast. Had 8gb stick in secondary slots, saw only a single memory divider decrease in MT/s and timings were almost identical. Probably going back to this config, the hit to speed for my IMC using 64 is just too much.









To boot this requires setups to be manually set to 0, auto won't post, but 56-0-0 will get into windows at 1t, but very unstable.

DrvStr pretty much have to be what they are.

RTT also have basically no wiggle, but this is what auto set. Tried other values, 7-3-3, 6-3-3, 7-off-1, 6-off-1, 7-3-1 works best.

TPHYRDL is 26 on all 4 DIMMS.

Board doesn't have a ram boot voltage option like crosshair. I suspect that's holding it back quite a bit. Also doesn't have Digi+VRM section for RAM like crosshair, also surely not helping since I can't bump the VRM frequency.

Temps are fairly cool, 19c idle, 21c TM5 (underwater).

The GVKA 4000-16 kit is great for 32, don't advise for 64 unless you want a rough time or have a CPU with a beast IMC.


----------



## ManniX-ITA

tcclaviger said:


> Whelp, decided to inflict mental pain upon myself and ordered a second 2x16 kit, so running 4x16 on the updated strix x570-E II.


Wow, you really did put yourself in a tight spot 
Kudos for the bravery!



tcclaviger said:


> Board doesn't have a ram boot voltage option like crosshair. I suspect that's holding it back quite a bit. Also doesn't have Digi+VRM section for RAM like crosshair, also surely not helping since I can't bump the VRM frequency.


Wow, this is really astonishing. Did you try another BIOS release?
For sure it's not normal at all. I've never seen an ASUS board without Digi+VRM section in the last years.
Bought a much cheaper B550 TUF Gaming and it does have it.



tcclaviger said:


> When people said going 32 to 64 was a big speed compromise, I somehow didn't fully internalize just how drastic it is!


Yes it's drastic... did you try with GDM On? What about higher VSOC and/or higher/lower VDDP?


----------



## mongoled

@tcclaviger 
So upping vSOC voltage did not help at all with posting @ 3733/1866 ?

Im sure you tried many combos, I would have set vSOC 1.2v, ClkDrvStr: 120 ohms, all other settings on AUTO to see if it posts, unsure what vDIMM you are using ...

If it did post would take note of all AUTO setitngs that are used and based on those AUTO settings would selectivly choose what to tweak ..


----------



## mongoled

VPII said:


> Hi @mongoled just wanted to share I manage to get my entire system working with the -20 all core vcurve optimizer, results maybe not as great but how I have done it is by doing a complete fresh install of Windows 11. Yup maybe a bad idea with the issues with AMD Ryzen but it appears to be resolved. Now I have done this with a vcore offset in the bios of -0.0875vcore which was not possible before but it brought down temps under CB23 from 87c ccd temp to 80c which is all I wanted. Here is my result. Funny though before I did the vcore offset my memory latency was around 55 which is great but too great for my memory speed and timings I think.
> 
> View attachment 2534127


If the decrease is definately related to vCORE offset I would revist that and tweak it so you are not getting that increased latency as the increased latency would be a sign that you are loosing performance in other scenarios ...


----------



## Taraquin

Imprezzion said:


> Well, I got bored and it's Black Friday sales here and couldn't resist the urge..
> 
> I bought a 5900X and a ASUS B550-XE board.
> 
> Going to be re-using my B-Die I am running in my Intel 10900KF rig now. They will be replaced by a 2x8GB Kingston Beast 3600C17's I could get cheap and that set goes to a buddy who still rocks a 2500K lol.
> 
> My sticks are G.Skill Trident-Z Neo 3600C16 which I have always run at 4400 17-17-27-38-328-2T @ 1.50v on Z490. I'm assuming 4400 isn't very efficient on AMD due to not running 1:1 IF so what should I shoot for? 3800C14? Any tips where to start lol? I have to completely learn both RAM and CPU OC again as I have not used any Ryzen CPU at all let alone clocked one..
> 
> It's under a full custom loop, hwlabs GTX 420 + 240 push pull, EK D5 + res, EK Supremacy EVO block (maybe buying a new block for it tho).
> 
> And what TIM should I use on a mirror lapped block. Does LM work on AMD? I have loads of Coollaboratory Liquid Ultra here for Intel direct die stuff or should I just use PK-3 / MX-5?


The highest you can get your IF running without whea 19 is the best. On 5900X 3800\1900 is usually the max, but you can be lucky and manage anything between 3800 and 4200. 3800cl14 is probably the best you can do, getting it at 1T with tweaked subs, depending on binning 1.5-1.55V. 

As for OC I strongly recommend curve optimizer as it gives you the best of both worlds with high single core boost, high allcore boost and low idle temp\consumption. Try -30 allcore as baseline, if unbootable, try -25 and so on and use core cycler to identify the cores that need lower neg value. Hopefully you will end up with some cores hitting -30, some around -20 and some maybe at 0. You could try setting +50-200 on PBO aswell, but it might require you to lower negative CO values which reduces allcore clockspeed so might not be worth it.


----------



## Audioboxer

Taraquin said:


> The highest you can get your IF running without whea 19 is the best. On 5900X 3800\1900 is usually the max, but you can be lucky and manage anything between 3800 and 4200. 3800cl14 is probably the best you can do, getting it at 1T with tweaked subs, depending on binning 1.5-1.55V.
> 
> As for OC I strongly recommend curve optimizer as it gives you the best of both worlds with high single core boost, high allcore boost and low idle temp\consumption.* Try -30 allcore as baseline, if unbootable, try -25 and so on and use core cycler to identify the cores that need lower neg value.* Hopefully you will end up with some cores hitting -30, some around -20 and some maybe at 0. You could try setting +50-200 on PBO aswell, but it might require you to lower negative CO values which reduces allcore clockspeed so might not be worth it.


Just a reminder for anyone doing this, there is a very good chance all core -30 will boot, let alone 20~25, but you must do stability tests, preferably with OCCT or corecycler that can hit one core at a time.

Most of my cores are -25~30, but my very best core taps out at -7, and the 2nd best is at like -15.

I doubt many people are actually stable when they just run a -20 all core, let alone a -25 or -30. You need to use per core, put some time into it. Only running stability testing that hits all cores at once is not ideal either, as your all core boost will be lower than anything an individual core manages to hit on its own. I've seen quite a few people go with like all core -30, claim stable, play games seemingly fine and then complain weeks later about random reboots on desktop.

Ironically, idle is actually the end game stability test for most Ryzen chips 










Take a look at this for example, while those boosts are soo small they're only for like half a second or something, if my best core, 2, isn't stable, one of these boosts could trigger a random reboot. It's normal for your best cores not to be able to achieve as big a negative value on the curve. More-so, it's actually expected they _should_ be running a lower negative value than the weaker cores.


----------



## tcclaviger

CO fully tuned, ranges from -4 to -28, ycruncher stable using core cycler, sse + avx + avx2 stable in occt using physical+virtual cycling, extreme and varying load.

I concur that flat -30 or -20 across the board is almost certainly not stable. For those that it is stable for, the majority it's only stable when prochot is limiting. Cool that chip down and let it boost to what the voltage table allows for and it'll almost guaranteed over post into a black screen rest (so sub 50c at full load, not achievable by most setups).

I'm running a chiller so...I get much higher effective clocks than typical, especially when I drop water under 10c.

DoS tuned at 48/47 with 1.281 get (for longevity reasons, it's stable at 49.25/48.5 with 1.36 get).

With 48/47 dos + co/pbo I get these roughly and consistently.
31700/1695 r23
1870/19200 GB5
8070/73000 GB4
722/13800 cpuz

I did try a bunch of soc voltages, but didn't try 120 ohm, will give that a shot.

At 3933 it was decent ram efficiency, 61,3xx 53.2ns for flat 14s, at 3666 it's 56,2xx and 55.7ns, bleh.

Going to try for another day or two for 3733, but if it doesn't shake out, just going 48gb triple rank setup, I know it'll do 1933 with tight timings. 

I do have a 1900fclk hole, sadly. To be honest, my 3900x dominates this 5950x regarding FCLK and IMC, such a shame to lose IMC lottery on the zen 3 chip, which has such good cores.

Fingers crossed for IMC update on vcache CPUs...


----------



## tcclaviger

Doing some telemetry trickery, got it to hold slightly higher at same temp, 5130-5150 effective clocks instead of 5110-5120:








The ram though, kills anything outside of static CPU benchmarks, things like Corona, Blender, any sort of gaming etc is all suffering. Lost 14fps in SOTR lowest 1080 and more proportionally in 3dmark tests :/ Thoroughly not worth it.

Also figured out an interesting relationship between EDC and boosting when cold, which allowed for this, but is otherwise totally irrelevant to any sort of normal ambient based cooling setup and more so one without DOS:





System manufacturer System Product Name - Geekbench Browser


Benchmark results for a System manufacturer System Product Name with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





These were essentially effective for this test, it held what I set it to hold (yes this was PBO).










ManniX-ITA said:


> Wow, you really did put yourself in a tight spot
> Kudos for the bravery!
> 
> 
> 
> Wow, this is really astonishing. Did you try another BIOS release?
> For sure it's not normal at all. I've never seen an ASUS board without Digi+VRM section in the last years.
> Bought a much cheaper B550 TUF Gaming and it does have it.
> 
> 
> 
> Yes it's drastic... did you try with GDM On? What about higher VSOC and/or higher/lower VDDP?


It has Digi+ but it doesn't have the RAM section of Digi+ like the Crosshair boards do. Artificial segmentation to drive sales of the more expensive boards. Sadly, they don't properly support the higher tier boards as well (I have a C6E and C7H, both still have launch day bugs...).


----------



## Audioboxer

tcclaviger said:


> Doing some telemetry trickery, got it to hold slightly higher at same temp, 5130-5150 effective clocks instead of 5110-5120:
> View attachment 2534136
> 
> 
> The ram though, kills anything outside of static CPU benchmarks, things like Corona, Blender, any sort of gaming etc is all suffering. Lost 14fps in SOTR lowest 1080 and more proportionally in 3dmark tests :/ Thoroughly not worth it.
> 
> Also figured out an interesting relationship between EDC and boosting when cold, which allowed for this, but is otherwise totally irrelevant to any sort of normal ambient based cooling setup and more so one without DOS:
> 
> 
> 
> 
> 
> System manufacturer System Product Name - Geekbench Browser
> 
> 
> Benchmark results for a System manufacturer System Product Name with an AMD Ryzen 9 5950X processor.
> 
> 
> 
> browser.geekbench.com
> 
> 
> 
> 
> 
> These were essentially effective for this test, it held what I set it to hold (yes this was PBO).
> View attachment 2534138
> 
> 
> 
> 
> It has Digi+ but it doesn't have the RAM section of Digi+ like the Crosshair boards do. Artificial segmentation to drive sales of the more expensive boards. Sadly, they don't properly support the higher tier boards as well (I have a C6E and C7H, both still have launch day bugs...).


Excellent! What were you telemetry values to achieve this?


----------



## ManniX-ITA

tcclaviger said:


> Doing some telemetry trickery, got it to hold slightly higher at same temp, 5130-5150 effective clocks instead of 5110-5120:


Nice, at which temperature the CPU was while running?


----------



## Mach3.2

Just received the 2*16GB 3600MHz 14-15-15-35 kit, I still can't POST with tCL of 15 or faster unless I turn on XMP and leave everything on default. Only then I manage to POST and boot into windows at 3600MHz 14-15-15 1T GDM on. AIDA latency is around 59.5ns at those settings, which seem to be way too high.

I starting to think my IMC just doesn't like dual rank B die sticks. I haven't really banged into the wall this many times when I was tuning single rank sticks. 🤕


----------



## Imprezzion

Taraquin said:


> The highest you can get your IF running without whea 19 is the best. On 5900X 3800\1900 is usually the max, but you can be lucky and manage anything between 3800 and 4200. 3800cl14 is probably the best you can do, getting it at 1T with tweaked subs, depending on binning 1.5-1.55V.
> 
> As for OC I strongly recommend curve optimizer as it gives you the best of both worlds with high single core boost, high allcore boost and low idle temp\consumption. Try -30 allcore as baseline, if unbootable, try -25 and so on and use core cycler to identify the cores that need lower neg value. Hopefully you will end up with some cores hitting -30, some around -20 and some maybe at 0. You could try setting +50-200 on PBO aswell, but it might require you to lower negative CO values which reduces allcore clockspeed so might not be worth it.


Thanks for the clear hints! I will probably just run XMP 3600 16-16-16-36 first just so I can focus fully on the CPU OC first.

Can you, or anyone else who wants to, give me a very short TL;DR version of what and how to stress test a 5900X with cycling cores and such when I go PBO2 + curve optimizer? 

My CPU, board, spare Hynix 3600C17 RAM just in case it won't play nice with DR B-Die, and the TechN block is in the mail. Should be here tomorrow. It will take me a while to actually swap the build over as the rads and tubing are extremely tight in my case and I have no room to manipulate stuff around so I hope I can squeeze the board in there behind the tubing without having to pull the GPU out of the loop.


----------



## Sam_Oslo

Hey guys. I got a few questions for you RAM gurus. 

I'm really happy with my current 2x8 3600Mhz 16 16 16 16 36 and considering to buy 2 more sticks. I found both 2x8 SR and 2x16 DR with the exact same 3600c16 timings and have these 3 setup options:

1- 2x8 SR + 2x16 DR for a total of 48GB
2- 4x8 SR for a total of 32GB
3- 2x16 DR for a total of 32GB (replacing the current sticks with 2x16)
And I prefer them in this order.

My motherboard (the Gigabyte Vision D) have proven to have a really good topology, and the 5700G did a good job for pushing the 2x8 sticks to 4600c18 without any problem. It didn't need any excessive voltages, but I'm not sure how it will cope with 4 sticks, especially with the option 1 for 48GB.

Which option do you guys suggest?


----------



## ManniX-ITA

Sam_Oslo said:


> Which option do you guys suggest?


You should read the posts in this page.
4 DIMMs is a challenge, if they are all SR.
They are probably not going at the same speed and timings that are working with only 2 DIMMs.
If they are 4 x DR it can be a nightmare.
Mixing SR and DR which needs very different bus and termination settings it's truly masochistic.
Depends on what's your favorite degree of pain; I'd recommend 2x16 DR.


----------



## Sam_Oslo

ManniX-ITA said:


> You should read the posts in this page.
> 4 DIMMs is a challenge, if they are all SR.
> They are probably not going at the same speed and timings that are working with only 2 DIMMs.
> If they are 4 x DR it can be a nightmare.
> Mixing SR and DR which needs very different bus and termination settings it's truly masochistic.
> Depends on what's your favorite degree of pain; I'd recommend 2x16 DR.


Thx for a good and clear warning about the nightmare . I had my fears but this sounds really harsh. 

Is this nightmare the same on all motherboards? I ask to find out if it's due to the limitations of IMC on X-series CPUs?. Then my 5700G may have a better chance with 4 sticks?. 
Anybody have experience with 4 sticks on G-series CPUs?


----------



## ManniX-ITA

Sam_Oslo said:


> I ask to find out if it's due to the limitations of IMC on X-series CPUs?. Then my 5700G may have a better chance with 4 sticks?.


It's probably much easier with an APU but the underlying issue remains.
Driving 4 sticks is more difficult, especially if they are DR.
Mixing SR and DR it's looking for troubles.
I've not seen a single successful mixing on DDR4 but maybe I've missed it.


----------



## dk_mic

Audioboxer said:


> Around 54ns is basically the floor for a 5950x at 3800/1900. You might get into the 53.x range, but not like 53.1~2. So the question more likely shifts to your read/write/copy and if you can push more out of them. 54.8 can be improved though, when I say around 54ns is the floor I'm meaning 53.8~54.2.
> 
> You've modelled your timings around GDM 1T, so I'm not too sure what to recommend you try as GDM can interfere with timings. Instead, just so you can see what I mean, try switching to 2T/GDM disabled and see if you can run a 25 cycle TM5 as is.
> 
> 48 ProcODT IMO is much higher than necessary on a 5xxx processor. 36.9 is usually where DR with a 5950x will sit around. Also to fix your tRFC2/4, the formula for calculating them is *tRFC2* = tRFC / 1.346 *tRFC4* = tRFC2 / 1.625.
> 
> Anta advised tRFC itself is best as multiples of 16, your nearest options if you take that advice would be 256 or 272. I would try aiming for 256.


You are right, 2T GDM off is not stable on TM5. I have now tried quite a bit to get it stable at 2T while keeping the primary timings (and looking at error codes and this https://www.overclock.net/cdn-cgi/i.../attachments/tm5_1usmus_download-jpg.2479357/)
- but no success. Kind of frustrating with so many variables to play with.
AIDA benchmarks show no real differences, so I am not sure what is there to gain. I don't think the DIMMs can have a stable 3800-14 1T profile at all -if that should be my ultimative goal.

Thanks for the advice on tRFC -I didnt realize earlier that MSI bios even supports the individual settings.
I have played with lower ProcODT, but seems unstable. Are there any downsides to have it at 48? IIRC i had to increase it step by step when initially tuning the profile to get it to pass TM5, a long time ago.


----------



## Sam_Oslo

ManniX-ITA said:


> It's probably much easier with an APU but the underlying issue remains.
> Driving 4 sticks is more difficult, especially if they are DR.
> Mixing SR and DR it's looking for troubles.
> I've not seen a single successful mixing on DDR4 but maybe I've missed it.


Yeah, the underlying issue should be the same. I had my fears, but now you have scared me enough to drop the plans for upgrading the RAM. 
I don't want to loose a good chunk of the 24/7-performance in exchange for the extra RAM that I won't need too often.


----------



## tcclaviger

Audioboxer said:


> Excellent! What were you telemetry values to achieve this?


I left soc telemetry alone. -10000 on CPU, not sure if that's what helped or refined curve values tbh. Still working on narrowing down the precise cause -effect of telemetry on this board and agesa.



ManniX-ITA said:


> Nice, at which temperature the CPU was while running?


I hold water at 50f usually, dew point in my office tends to be 46-48f, use conductonought, Optimus block, dual D5s, 1hp chiller. Core temps float from 46-48c under full single core boost on CCD1 and 54ish on CCD2 (it likes to use much higher VIDs).

I got bored, quick. Had my 980 Pro drive arrive which requires a system drain to install anyway, so reverted to 2x16 + 2x8 for 48gb. Sure as a bear sh*** in the woods, posted 1st try at 3933/1866 lol. 

Shockingly it actually posted and went into windows at 3800/1900, which I tried out of morbid curiosity, but crashed doing AIDA test.

48GB should be enough for my workflow anyways, I usually stay under 32, but sometimes do fill it (Blender Modeling with many...lol so many verts).

Lost about 6 hours of core CO refinement due to morning sleepiness when I went to save the bios profile.... So that's 1st on the list for today, get back to where it was on CPU, then start dialing timings down on memory.

Thankfully I did discover my cause of transient overboost spike crashes (scalar + MHz cap of +200 when over 40f water) by using the hwinfo graphing function. I also recall the Vcore offset of +0.0125 fills the defecit between VID and actual delivered voltage to CPU, so it's just CO at this point, which is close +/- 4 on each core, should be easy to get back.


----------



## tcclaviger

Sam_Oslo said:


> Hey guys. I got a few questions for you RAM gurus.
> 
> I'm really happy with my current 2x8 3600Mhz 16 16 16 16 36 and considering to buy 2 more sticks. I found both 2x8 SR and 2x16 DR with the exact same 3600c16 timings and have these 3 setup options:
> 
> 1- 2x8 SR + 2x16 DR for a total of 48GB
> 2- 4x8 SR for a total of 32GB
> 3- 2x16 DR for a total of 32GB (replacing the current sticks with 2x16)
> And I prefer them in this order.
> 
> My motherboard (the Gigabyte Vision D) have proven to have a really good topology, and the 5700G did a good job for pushing the 2x8 sticks to 4600c18 without any problem. It didn't need any excessive voltages, but I'm not sure how it will cope with 4 sticks, especially with the option 1 for 48GB.
> 
> Which option do you guys suggest?





Sam_Oslo said:


> Yeah, the underlying issue should be the same. I had my fears, but now you have scared me enough to drop the plans for upgrading the RAM.
> I don't want to loose a good chunk of the 24/7-performance in exchange for the extra RAM that I won't need too often.


I have run 2xSR 2xDR for 48gb before and just switched back to it from 4xDR.

4xDR b-die is kind of worst possible setup. Not as easy on the IMC to get speed as other ICs, I got stuck at 3666. Timings, well it's b-die, but those don't fix low raw speed.

2xSr 2x Dr b-die currently tuning on new board. Previously had working on C7H at 3933 C14. Expect I'll gtget 3933 or 3966 as limit this time.

2xDR b-die easy peasy, honestly...child's play. Easier to tune than 4xSr in my experience. 2xDR I used exactly the same config as 2xSR but added 0.3 vdimm. Done. Lol. Both able to achieve 4000 C14 on 5950x.


----------



## umea

Are 1ccd disabled dual ccd results being allowed onto the sheet? I'm messing around with a 16gb kit for fun, curious as to how it compares or if 1ccd is not comparable latency wise to just regular 1ccd CPUs.

@Audioboxer what do you use to disable 1ccd? and @domdtxdissar is your 51.2ns with 1ccd disabled?
Does 1ccd disabled allow for improvement on timings?


----------



## Sam_Oslo

tcclaviger said:


> 2xDR b-die easy peasy, honestly...child's play. Easier to tune than 4xSr in my experience. 2xDR I used exactly the same config as 2xSR but added 0.3 vdimm. Done. Lol. Both able to achieve 4000 C14 on 5950x.


Yeah, these are b-die, and your experience with 2x16GB DR creates a hope for a good 32GB 24/7-setup.
I'm currently running the 2x8GB SR @4600c18 1.48v. So I may be able to run the 2x16GB DR at the same settings with 1.50v, or so. In case, that would be a good 24/7-setp. ManniX-ITA recommended the 2xDR as the best option too*. *Now I'm tempted to give a shot.


----------



## domdtxdissar

umea said:


> Are 1ccd disabled dual ccd results being allowed onto the sheet? I'm messing around with a 16gb kit for fun, curious as to how it compares or if 1ccd is not comparable latency wise to just regular 1ccd CPUs.
> 
> @Audioboxer what do you use to disable 1ccd? and @domdtxdissar is your 51.2ns with 1ccd disabled?
> Does 1ccd disabled allow for improvement on timings?


My latest entry @ 51.2ns are with both CCD enabled, done in my everyday OS. (screnshot shows all 32 threads)


----------



## umea

domdtxdissar said:


> My latest entry @ 51.2ns are with both CCD enabled, done in my everyday OS. (screnshot shows all 32 threads)


thanks, gives me something to aim to beat w my 5900x.

just curious, what would be the difference between wirx's setup and mine?
I managed to stabilize the following timings (ran 20 of 1usmus), but I only manage 53.1 with the same CPU OC (4.8/4.675 manual OC).


Spoiler















wirx's:



Spoiler

















Does frequency increase (despite having similar timings) actually affect latency that much? My current understanding is that 3800C14 flat = 4000C15 flat all else equal, just with the higher frequency providing more bandwidth. Am I missing something here?


----------



## PJVol

umea said:


> Does frequency increase (despite having similar timings) actually affect latency that much?


lol, of course it does) 
I usually see mem latency down ~0.6ns with each MCLK step forward.


----------



## umea

PJVol said:


> lol, of course it does)
> I usually see mem latency down ~0.6ns with each MCLK step forward.


I see, thank you. I always thought that 3800C14 will have the same latency as 4000C15 just with less bandwidth. Guess it's back to the drawing board on how to improve this kit's OC as my 5900x cannot do anything above 1900fclk.


----------



## PJVol

umea said:


> as my 5900x cannot do anything above 1900fclk.


How did you know? Have you tried to boot fclk 2000 in 1:1 mode (mem loose timings for the start) and set vsoc to 1.2 and vdd18 to 2.1v ?
And, btw, static overclock, as well as disabled fabric power saving features worsen AIDA membench result, since it also depends on single core boost, specifically Core0.


----------



## umea

PJVol said:


> How did you know? Have you tried to boot fclk 2000 in 1:1 mode (mem loose timings for the start) and set vsoc to 1.2 and vdd18 to 2.1v ?


I've tried probably over a hundred diff times while messing with voltages but it always spits out WHEAs and or restarts while trying to stress test.

Just tried 4000/2000 with 2.1 VDD18 and almost an instant restart in y cruncher and tons of wheas when just simply running tm5.


----------



## PJVol

umea said:


> Just tried 4000/2000 with 2.1 VDD18 and almost an instant restart in y cruncher and tons of wheas when just simply running tm5


Yea, unfortunately they seem inevitable.
Idk, i've tried 3800 cl14 with 2xSR but did't see any noticable scaling from the flat 15.


----------



## umea

PJVol said:


> And, btw, static overclock, as well as disabled fabric power saving features worsen AIDA membench result, since it also depends on single core boost, specifically Core0.


I know that SMT disabled adds latency on AIDA membench result, what other options are there specifically that lower it?


----------



## PJVol

Does anyone know, what error #13 in a 1usmus tm5 config might mean?
I really doubt it is "overheating", unless lowering ProcODT actually results in more heat. Could it be so?


----------



## Taraquin

Audioboxer said:


> Just a reminder for anyone doing this, there is a very good chance all core -30 will boot, let alone 20~25, but you must do stability tests, preferably with OCCT or corecycler that can hit one core at a time.
> 
> Most of my cores are -25~30, but my very best core taps out at -7, and the 2nd best is at like -15.
> 
> I doubt many people are actually stable when they just run a -20 all core, let alone a -25 or -30. You need to use per core, put some time into it. Only running stability testing that hits all cores at once is not ideal either, as your all core boost will be lower than anything an individual core manages to hit on its own. I've seen quite a few people go with like all core -30, claim stable, play games seemingly fine and then complain weeks later about random reboots on desktop.
> 
> Ironically, idle is actually the end game stability test for most Ryzen chips
> 
> View attachment 2534135
> 
> 
> Take a look at this for example, while those boosts are soo small they're only for like half a second or something, if my best core, 2, isn't stable, one of these boosts could trigger a random reboot. It's normal for your best cores not to be able to achieve as big a negative value on the curve. More-so, it's actually expected they _should_ be running a lower negative value than the weaker cores.


At +200 PBO and -30 allcore core 0 failed after a few minutes in core cycler. I set it to -29 and all worked fine. My core 1 (Second best core) gave me 2 reboot a week. Changed that to -29 and all has been stable since. Corecycler finds most of the problems, but the small peaks in idle must be sorted out with event viewer.


----------



## Ridianod

guys hi. I took just error 6 on TM5. What should do the pass that? I found "Error 6 is purely related to the IMC , be if procODT, CLDO_VDDP or vSOC" Should I increase or decrease these values?


----------



## ManniX-ITA

Ridianod said:


> guys hi. I took just error 6 on TM5. What should do the pass that? I found "Error 6 is purely related to the IMC , be if procODT, CLDO_VDDP or vSOC" Should I increase or decrease these values?


Raise VDIMM one step at a time.
Flat 14 1T could need 1.55V or more.


----------



## PJVol

Forgot to add, why I'm asking of #13 and ProcODT.
In fact, only increasing it to 36.9Ohms helped to get rid of those annoying #13's and #10's. I just never set so high impendance before on these modules.


----------



## ManniX-ITA

PJVol said:


> Forgot to add, why I'm asking of #13 and ProcODT.
> In fact, only increasing it to 36.9Ohms helped to get rid of those annoying #13's and #10's. I just never set so high impendance before on these modules.


I think Veii's error list is covering the most common causes.
There could be less likely ones and also other scenarios which are setup specific.
Like error #2 & #10 combo for tRCDRD which is not documented.
I've found also that too low or high RRD/WTR can cause error #2/6/10 (I don't remember exactly).
Not sure if we should integrate the documentation or skip the rare cases.


----------



## Audioboxer

domdtxdissar said:


> My latest entry @ 51.2ns are with both CCD enabled, done in my everyday OS. (screnshot shows all 32 threads)


 Aren't you using 1usmus new tool which can prioritise CCDs or cores depending on the load?


----------



## ManniX-ITA

Audioboxer said:


> Aren't you using 1usmus new tool which can prioritise CCDs or cores depending on the load?


Yes, there's a column in the score which is telling it's a run with Hydra.
It's an important detail of course!


----------



## Audioboxer

ManniX-ITA said:


> Yes, there's a column in the score which is telling it's a run with Hydra.
> It's an important detail of course!


Ah right, fair enough.

Yeah just bringing it up in case there are any newbies in this topic (like me from months ago!) who just see 51.x achieved on a 5950x at 3800 and start tearing their heads out when they can't seem to get any lower than 53.x~54.x lol.


----------



## PJVol

ManniX-ITA said:


> Like error #2 & #10 combo for tRCDRD which is not documented.


I usually have #2 or spamming #6 right away if something is wrong with CadBus impendances. But #13 turns out to be ProcODT related for me.
Timings weren't changed throughout the whole testing, and tbf, except tRFC (when 320 -> 304 yields + ~200Mb/s Read and Copy bandwidth, and ~0.2ns lower latency) they didn't seem to have any noticeable impact either on stability or performance.


ManniX-ITA said:


> I think Veii's error list is covering the most common causes.


Yeah, but for the #13 it is too common in my view. The question is not even "HOW to remove heat" rather "WHAT is the cause of overheating"


----------



## Audioboxer

dk_mic said:


> You are right, 2T GDM off is not stable on TM5. I have now tried quite a bit to get it stable at 2T while keeping the primary timings (and looking at error codes and this https://www.overclock.net/cdn-cgi/i.../attachments/tm5_1usmus_download-jpg.2479357/)
> - but no success. Kind of frustrating with so many variables to play with.
> AIDA benchmarks show no real differences, so I am not sure what is there to gain. I don't think the DIMMs can have a stable 3800-14 1T profile at all -if that should be my ultimative goal.
> 
> Thanks for the advice on tRFC -I didnt realize earlier that MSI bios even supports the individual settings.
> I have played with lower ProcODT, but seems unstable. Are there any downsides to have it at 48? IIRC i had to increase it step by step when initially tuning the profile to get it to pass TM5, a long time ago.


2T GDM disabled should definitely be do-able, either a primary or secondary timing is causing issues. Or maybe a resistance issue.

As for what the end goal is, it's being in control of all your timings and voltages and knowing nothing is autocorrecting. That then gives you a base to seek the absolute floor with latency/read, write and copy.

Working with GDM is always going to put you in a position where you're getting some assistance with stability possibly at the cost of performance. But at the end of the day if you're happy where you are that is all that matters.


----------



## ManniX-ITA

PJVol said:


> I usually have #2 or spamming #6 right away if something is wrong with CadBus impendances. But #13 turns out to be ProcODT related for me.


I think I get #13 as well but only in extreme deviation from the sweet spot and only together with massive amounts of #0 and #6.
More likely together with #0 cause of too low VDIMM.
maybe the APU IMC behaves a little differently.


----------



## PJVol

ManniX-ITA said:


> maybe the APU IMC


Actually it's my 5600X


----------



## ManniX-ITA

PJVol said:


> Actually it's my 5600X


You are meddling the waters, sell this APU! Kidding 

Wondering, since if we have many stubborn hard core TM5 testers here...
Maybe we can setup group testing sessions to gather data.
Like, ProcODT: starting from your working profile, what errors do you get going down or up.


----------



## mongoled

ManniX-ITA said:


> Maybe we can setup group testing sessions to gather data.


😍 😍 😍 

TM5 Anonymous

😂😂


----------



## Audioboxer

A Kernel-Power error 41 caused by a BSOD can be GPU related can't it? Got one last night after pushing my GPU overclock higher, but simultaneously CPU boost clocks have also been pushed higher. They've been OK for days though, and corecycler/OCCT has been OK.

Reverted my GPU changes and things seem to be OK, it's just a lot of advice says online Kernel-Power 41 followed by a reboot or shutdown is often RAM/CPU.

Seeing as it happened during gaming that's why I think it's GPU. I've now been waiting over a year in the EVGA Europe step up queue for a 3080. At this rate it'll probably be another year before I can retire this 2080Ti 

I noticed 3DMark on sale again on Steam, I think I'll finally buy it. Stability testing a GPU has always been quite frustrating, Heaven is a bit outdated now. I'm not using Furmark, not risking "blowing up" my GPU after my last 2080Ti died


----------



## PJVol

mongoled said:


> TM5 Anonymous


Ok, with the following schedule for a *TM5 Support Group Meetings:*
Sunday: ProcODT anonymous​Monday: "Tighter timings time"​Tuesday: Fear of more Voltage​Wednesday: Errors anonymous​Thursday: Alcoholics anonymous (because they're always there)​...
gonna take one?



ManniX-ITA said:


> You are meddling the waters, sell this APU!


Here it is, and I like it more 
Funny that with basically identical timings, even 1T didn't give it any advantage in latency (actually 0.2ns slower),
though bandwidth's through the roof. Vermeer's boost and $L3 rules.


----------



## Audioboxer

Alright 3DMark seems quite nifty for testing the GPU. Should give the memory a good run out as well. I don't have too much free time for gaming these days so being able to loop a stability test essentially based on gaming is a nice addition to my arsenal.

First funny thing I noticed a couple of loops in is TimeSpy requesting up to 111% power draw despite me reducing the power limit to 100% for base testing 🤣

The New World phenomenon. Despite a power limit just spike way passed it lol. The word 'limit' doing some heavy lifting if you're going to overshoot an extra 11% lmao.

TimeSpy Extreme doesn't seem as heavy on the CPU, but hammering the GPU with 100% use should be a decent way to find issues. As I said above since reducing my power draw from 130% to 123% and dropping the core clocks a bit I've not had a kernel-power 41 error.










Is there any way to run more than 20 loops or is that just the limit? Extreme test seems to run in 4K as well, so for me that would be downsampled as I don't have a 4K output.

To a newbie 99.1% would seem concerning as well, but the message seems to suggest over 97% is acceptable.


----------



## ManniX-ITA

Audioboxer said:


> A Kernel-Power error 41 caused by a BSOD can be GPU related can't it?


Event 41 it's just a sudden reboot. Could be anything 



Audioboxer said:


> I noticed 3DMark on sale again on Steam, I think I'll finally buy it. Stability testing a GPU has always been quite frustrating, Heaven is a bit outdated now. I'm not using Furmark, not risking "blowing up" my GPU after my last 2080Ti died


It's hard to test for stability the latest GPUs.
3DMark it's one but if you pass it doesn't meant the profile is stable...
Superposition is quite a reference for bench and stress. You can define how many minutes to run.
Get also Metro Exodus EE for stability testing when it's on offer, the bench tool is very nice and easy.
If you want to stress heavy but not as much as Furmark, use Kombustor. The artifact scanner works most of the times.



Audioboxer said:


> Is there any way to run more than 20 loops or is that just the limit? Extreme test seems to run in 4K as well, so for me that would be downsampled as I don't have a 4K output.


I don't think you can do more cycles.


----------



## ManniX-ITA

Audioboxer said:


> To a newbie 99.1% would seem concerning as well, but the message seems to suggest over 97% is acceptable.


It is acceptable but I'm pretty sure you get a better result without G-Sync.


----------



## Audioboxer

ManniX-ITA said:


> Event 41 it's just a sudden reboot. Could be anything
> 
> 
> 
> It's hard to test for stability the latest GPUs.
> 3DMark it's one but if you pass it doesn't meant the profile is stable...
> Superposition is quite a reference for bench and stress. You can define how many minutes to run.
> Get also Metro Exodus EE for stability testing when it's on offer, the bench tool is very nice and easy.
> If you want to stress heavy but not as much as Furmark, use Kombustor. The artifact scanner works most of the times.
> 
> 
> 
> I don't think you can do more cycles.


Only two things changed to my setup recently were the CPU bias exploit and I bumped up my 2080Ti overclock a bit further and let it run in Heaven. Seemed OK but had that reboot during RDR2.

CPU was stability tested with corecycler and OCCT in last few days but obviously not ruling it out either as of now. Scaling back my GPU seems to have helped though so focussing on that first. I'm wondering if putting the slider up to 130% has resulted in spikes to 140%+ lol.

I've actually got that Metro Exodus EE, just haven't played it yet. Will look into it especially if it has a benchmark.


----------



## ManniX-ITA

Audioboxer said:


> I've actually got that Metro Exodus EE, just haven't played it yet. Will look into it especially if it has a benchmark.


Nice, look in the game folder for benchmark.exe, you can set the runs. 15 runs consecutive are usually good enough to test stability. The more is better 
Disable RT and enable DLSS to stress GPU boost clock and disable DLSS and enable RT to test vram OC.



Audioboxer said:


> Only two things changed to my setup recently were the CPU bias exploit and I bumped up my 2080Ti overclock a bit further and let it run in Heaven. Seemed OK but had that reboot during RDR2.


You changed telemetry recently right? Messing with telemetry can bring some weird and unexpected crashes that can look like GPU OC issues, trust me 
If it's not fixed with the GPU profile, revert telemetry to the previous config to check.


----------



## Audioboxer

Whacked power draw back up to 130% and managed to produce a reboot during normal TimeSpy. Ran it because I knew it would push frames much higher than the 4K one.

Testing again now with a lower power limit. Ironically, I think the card gets pushed more with a higher framerate than a lower stable framerate at 4K. Gsync off as well.

While the CPU doesn't get hit hard during TimeSpy its still boosting high, so keeping an eye on that. If I can reproduce reboots with the card either not OCed at all or with a much reduced OC I'll turn off the bias exploit and return to normal PBO.

At least I proved to myself 3DMark is capable of finding an issue!


----------



## ManniX-ITA

Audioboxer said:


> While the CPU doesn't get hit hard during TimeSpy its still boosting high, so keeping an eye on that. If I can reproduce reboots with the card either not OCed at all or with a much reduced OC I'll turn off the bias exploit and return to normal PBO.


Don't give up on telemetry 
I use 110/45 instead of 150/45.
In case give it a try.
Higher Amperage results in better scores but it's also unstable for me.
Plus I have SOC full scale at 1A.


----------



## Audioboxer

ManniX-ITA said:


> Don't give up on telemetry
> I use 110/45 instead of 150/45.
> In case give it a try.
> Higher Amperage results in better scores but it's also unstable for me.
> Plus I have SOC full scale at 1A.


I'll have a look if I can narrow it down to CPU. This TimeSpy test is about to pass with nothing changed so that's frustrating. Next step is going to be fully removing GPU OC and running TimeSpy over and over and over to see if I can produce a BSOD/reboot.

If it's CPU surprised Corecycler and OCCT didn't pick it up but I guess gaming has its own ways of using a CPU. I didn't modify my curve to use telemetry so I'm not sure if that can cause an issue, but then again Corecycler is normally the way I find an unstable curve.


----------



## ManniX-ITA

Audioboxer said:


> If it's CPU surprised Corecycler and OCCT didn't pick it up but I guess gaming has its own ways of using a CPU. I didn't modify my curve to use telemetry so I'm not sure if that can cause an issue, but then again Corecycler is normally the way I find an unstable curve.


If it's telemetry it could be weird and random.
More likely to happen while gaming, watching youtube or idling.


----------



## Audioboxer

ManniX-ITA said:


> If it's telemetry it could be weird and random.
> More likely to happen while gaming, watching youtube or idling.


Only happened during gaming and 3DMark so far.

What PBO settings do you use with telemetry btw? I find even when I'm using it I still need to pump my TDC and EDC quite high for the best scores. Guess this just depends on your chip and how much juice it wants for higher scores. I'm at 168/220.


----------



## ManniX-ITA

Audioboxer said:


> What PBO settings do you use with telemetry btw? I find even when I'm using it I still need to pump my TDC and EDC quite high for the best scores. Guess this just depends on your chip and how much juice it wants for higher scores. I'm at 168/220.


I'm not yet under water cooling so the behavior is different. Temperature constraint is my main factor.
PPT/TDC/EDC at 280/175/215 now.
Of course the specificity of the sample is crucial.

But these values are the best for me also cause of the other settings.
Scalar at 6x, boost clock at 100 MHz.
FCLK 2000 with IOD at 1140mV and VSOC at 1.25V.
vCore offset positive +0.125mV (if I remember correctly).

Eg. lower TDC it's degrading performances for me while with wc is often better below.
I get limited first by temperature; the limit matters on how I reach that point where it starts throttling.


----------



## Audioboxer

ManniX-ITA said:


> I'm not yet under water cooling so the behavior is different. Temperature constraint is my main factor.
> PPT/TDC/EDC at 280/175/215 now.
> Of course the specificity of the sample is crucial.
> 
> But these values are the best for me also cause of the other settings.
> Scalar at 6x, boost clock at 100 MHz.
> FCLK 2000 with IOD at 1140mV and VSOC at 1.25V.
> vCore offset positive +0.125mV (if I remember correctly).
> 
> Eg. lower TDC it's degrading performances for me while with wc is often better below.
> I get limited first by temperature; the limit matters on how I reach that point where it starts throttling.


Ahh, good point, I was forgetting about temperature being a limit first because of cooling.

I said to mongoled a few weeks back in here overclocking a CPU was much easier/faster than memory these days, well, I think I'm about to take the L on that comment 🤣

Sure, you can get a good OC fairly quickly, but pushing your individual CPU right to its limits is clearly a much longer process than PBO on and a quick curve!

That's before someone even looks at 1900+ FCLK. Apart from my USB issues I get terrible performance regression with multicore performance.

Now back to trying to get TimeSpy crashing without a GPU OC lol.


----------



## Audioboxer

Ok so, 2 runs now fine with GPU at default. But will keep going for now on the basis of reboots due to telemetry might be quite rare or random.

But I would like to ask again, because I don't really think I understood previously, does telemetry actually make your CPU draw more power or is it just tricking it to think it's drawing less so boost more?

The reason I'm asking is trying to figure out when I pump up my GPU power usage is the combined power output of my CPU and GPU causing issues? I'd hope not for an 850w power supply, it's an ROG Thor rebranded seasonic so I'd like to think it's not flipping out.

The highest wattage I've ever seen my CPU hit was 250w during CB23. GPU bios has a max wattage of like 330 IIRC. Or it might be 360. That's with the power slider at max. Power supply has max draw figure on an OLED screen and 5xx is usually where it is during heavy load or gaming.

Don't get me wrong if it's the GPU I'll be "delighted", as I'm enjoying my CPU performing better. Given I had an EVGA 2080Ti break on me before I probably should just be leaving it at default and being patient for a 3080 lol. It's the blower model turned watercooled card, so they likely never dumped their best silicon into this model.

Because let me tell you a 2080Ti blower is probably the worst thing I've ever heard in my life. 90 degrees using MSPaint and a single fan at 100% that is louder than a jet engine 🤣


----------



## Bix

ManniX-ITA said:


> But these values are the best for me also cause of the other settings.
> Scalar at 6x, boost clock at 100 MHz.
> FCLK 2000 with IOD at 1140mV and VSOC at 1.25V.
> vCore offset positive +0.125mV (if I remember correctly).


How critical were IOD and VSOC for you in terms of your CPU overclock? 
I'm also at FCLK2000 but with IOD at 1060mV and SOC at 1.1375V (set) since they were most stable and highest performing with my 5900x during FCLK testing. I'm now working on my PBO to maximise boosting - do I need to increase IOD and SOC in order to get the most out of my curve? Struggling a bit to get my head around all these voltages so any advice would be appreciated🙂


----------



## Audioboxer

Hours of running TimeSpy without a GPU OC and no issues, looks like my GPU is what was causing Kernel-Power 41. So, good news for the CPU overclock and not having any doubts about my memory, bad news for pushing my GPU any harder.

Mildly concerned some advice online suggests BSOD/reboot like that could be power supply and not getting enough power, but as I said with the power supply often tapping out around 5xx watts I'd be seriously disappointed if that was tripping OPP/OVP/OTP on a seasonic platinum 850w power supply.

I do know Nvidia has made a right mess of the latest drivers, and there is another hotfix today to try and fix black screen/gsync issues. Doubt any of that is related to reboots though.


----------



## ManniX-ITA

Bix said:


> How critical were IOD and VSOC for you in terms of your CPU overclock?
> I'm also at FCLK2000 but with IOD at 1060mV and SOC at 1.1375V (set) since they were most stable and highest performing with my 5900x during FCLK testing. I'm now working on my PBO to maximise boosting - do I need to increase IOD and SOC in order to get the most out of my curve? Struggling a bit to get my head around all these voltages so any advice would be appreciated


Absolutely critical 
The 5900x is far less demanding than the 5950x.
But consider that my 5950x is not a good binning, I've seen others needing much less voltage than mine.
SOC at 1.13V seems to me too good to be true but maybe you have a really good one.

My advice is to get a baseline at FCLK 1900.
Save the results of Geekbench 5, the monero miner (xmr-stak-rx, it's a pain to configure but it's worth), Linpack Xtreme, AIDA for memory.
Add all that you can then but these above are the basics; CPU-z, CB, Corona, Sandra, SOTR, etc

Start comparing with Geekbench 5; a lot of different workloads, you'll see if something is not right straight away.
Then compare the linpack scores and the monero miner hashrate.
You need to have same or better results with FLCK2000.

It's very easy to think it's all right but when you go nitpicking there's often something which is not running at the speed which is supposed to.


----------



## dk_mic

Audioboxer said:


> Seeing as it happened during gaming that's why I think it's GPU. I've now been waiting over a year in the EVGA Europe step up queue for a 3080. At this rate it'll probably be another year before I can retire this 2080Ti


sorry for off topic, but personally, I really wouldn't get ampere when you have a 2080 Ti. My best ambient air cooled 2080 Ti bench beats 66% of _all_ 25.5k entries from 5950x+3080 systems in timespy. 3080 only pulls away with raytracing in port royal.
I would rather look into re-applying thermal paste, because there are so many bad fabric paste applications. Not sure if possible with a blower style card, but eventually you can open the shroud and mount some custom fans or get a 3rd party cooler like a morpheus.


----------



## tcclaviger

So I swept the OCCT Benchmark spots for 5950x last night , I know though, many people aren't using it yet. There is way too much headroom left for me to think others are trying hard at this point.

The multi-avx test is a bit....variable, run 10 times in a row I can see high low score split of almost 200 points. The other 3 test are pretty consistent so I wouldn't use multiavx for checking the presence of clock stretching, but it is a phenomenal stability test! 

Also, it seems slightly AMD biased....

//////////////////////////////////////

Regarding triple rank 2x16+2x8, it has become ...weird. 

Can boot 3800/1900, about 3 times - then hangs on CPU initialization.

Can boot 3933/1866, an unpredictable number of times - gets into windows, is stable. Then randomly refuses to boot, something weird going on with FCLK and RAM training. Cold boots don't solve it. Eventually ends up in a cycle of failing to initialize CPU after training RAM properly. Needs some combination of booting at 3733/1866, adjusting stuff and then going to 3933/1866 because when it boots it doesn't retrain, just goes straight to boot.

I have a strong feeling that 16gb version of Patriot vipers would be better than these GSkill for the 48gb configuration, the vipers seem phenomenally easy to drive, and the GSkills not so much. Seperate they're both very good. Alas I've never seen them for sale.

////////////////////////////////

Strix E II: The closest thing to perfection I've found, on AM4. It would be great for 90% of owners, those who don't chase hish speed RAM OCs, but CPU performance M.2 performance, and GPU performance is all quite good, all beating my C7H. I'm running 3 NVME drives, 1 in PCIE_3 on an $9 adaptor card, scores nearly identical to M2_2, so 3 NVMEs is a non issue. M2_1 is fast as hell, 980 Pro clocks 7200/5200 speeds, 1/2 full in crystal disk mark.

It's missing critical RAM settings which holds it back to be a RAM OC board. A real shame, as Asus proves, yet again, they don't quite know the market their products fit into, watering down the ROG branding. IMHO the strix x570 series probably shouldn't exist, and stick with Prime, TUF, ROG as the tiers + Pro-Art for creators, introducing a C8H-Black that is Strix-E vrm and otherwise a DH bios set for $30 less than DH.

////////////////////

Regarding telemetry, did some cause-effect testing last night. Asus only give the AMP adjusting setting, not the current rail setting.

It's a placebo, at least at the temperatures I'm using. After an hour of trying values, I was unable to produce a result that stood out from margin of error.

What does actually improve boosting....CPU Voltage set to offset, and adjusting it so GET voltage is at or 1 step below VID. This should only be done after full CO work is done, as it will throw off CO tuning process.

For example, if VID is 1.4, and SVI2 GET is 1.382, adjust voltage offset to be +0.0125, this will deliver 1.396 get. As long as GET doesn't exceed VID, I see about a 20mhz bump vs auto or over doing the offset +.

////////////////////////

Regarding PBO power settings.

Reaching EDC fuse limit as Veii has discussed is critical to overall performance and consistency, however, when shooting for peak single core performance, it is not ideal, when running sub-ambient.

For daily setup I'm running 250PPT, 162 TDC, 201 EDC and DOS cross over at 90 Amps. This give best nT performance by boosting multi core loads very high while is waiting for DOS kick in (about .25 seconds - .5 seconds) then settling to DOS limits. Crossover occurs at 8 threads usually, workload depending.

For best single core, the lower EDC and TDC are, the more aggressively it will boost for a given temp. EG at 10c water, 200 EDC I see a lot of 5075-5092 boosting. Cut the EDC to 100 and TDC to 60 and I see a ton of 5170-5190. Same CO, same everything else. DOS allows you to then set transition point to 58 amps, and then will boost to DOS setting multithread, getting most of the performance back all core (98-99%).

This creates a strange area where you are "just" under the DOS transition point though, at like 56 amps, and the boosting becomes neutered by low EDC setting with 4-8 threads, this hurts gaming badly.

It's only really a benchmarking configuration, not suitable for daily overall performance, or for uses where 1thread performance is most valued (adobe/office stuff).

Thanks Veii for all your walls of text, they've really helped pick up this little tid bits I hadn't found on my own (like FUSE limit effects on cache and DrvStr settings). I found 200 or higher EDC worked best overall before I read your post on it, so was nice to see independent verification.

/////////////////


----------



## tcclaviger

Audioboxer said:


> Hours of running TimeSpy without a GPU OC and no issues, looks like my GPU is what was causing Kernel-Power 41. So, good news for the CPU overclock and not having any doubts about my memory, bad news for pushing my GPU any harder.
> 
> Mildly concerned some advice online suggests BSOD/reboot like that could be power supply and not getting enough power, but as I said with the power supply often tapping out around 5xx watts I'd be seriously disappointed if that was tripping OPP/OVP/OTP on a seasonic platinum 850w power supply.
> 
> I do know Nvidia has made a right mess of the latest drivers, and there is another hotfix today to try and fix black screen/gsync issues. Doubt any of that is related to reboots though.


I recently had an AX1200i fail in a sneaky way, use HWinfo and open the graph for 12v rail while testing on 2nd screen.

Would randomly crash the PC in a way that looked like CPU OC failing. 

At idle would hold 12.02v on 12v rail. 
On high CPU only load would see 11.9v. Oh high GPU only load, 11.3v, but no crash.
When loading both hard, hard power off like OCP tripping, only at 600-650 watt loads.

The sneaky part was load/unload quickly of CPU from 300w to 30w to 300w would also trigger it, exactly like 3dmark does sometimes.

Put in my Thor 1200, 12v never dips below 12.1, ever.

AX1200i is being RMAd, when new I remember it never falling under 11.98v, even at 1280 watt load (1680v2 @ 4.8ghz and 3x980 Matrix OCd).


----------



## ManniX-ITA

dk_mic said:


> sorry for off topic, but personally, I really wouldn't get ampere when you have a 2080 Ti. My best ambient air cooled 2080 Ti bench beats 66% of _all_ 25.5k entries from 5950x+3080 systems in timespy. 3080 only pulls away with raytracing in port royal.


Indeed the 3080 it's not a big step up from a 2080ti. Especially considering the shameless price you have to pay it...



dk_mic said:


> I would rather look into re-applying thermal paste, because there are so many bad fabric paste applications. Not sure if possible with a blower style card, but eventually you can open the shroud and mount some custom fans or get a 3rd party cooler like a morpheus.


There are also more crazy options like the Kraken G12 + AIO (if you have the space) 

I was also annoyed by the fan noise from my GTX 1070 that I recycled on my rig in Italy.
Just bought a G12 and an old Corsair H50 (can't fit a bigger one and it was cheap).
Couldn't resist also to replace the fans with a Noctua and a Corsair ML Pro...
Spent almost as much I would have to replace it with a 3060 but it's going to be fun 

I've seen the results on 2080ti and it's quite impressive, especially with a 240mm.


----------



## Bix

ManniX-ITA said:


> Absolutely critical
> The 5900x is far less demanding than the 5950x.
> But consider that my 5950x is not a good binning, I've seen others needing much less voltage than mine.
> SOC at 1.13V seems to me too good to be true but maybe you have a really good one.
> 
> My advice is to get a baseline at FCLK 1900.
> Save the results of Geekbench 5, the monero miner (xmr-stak-rx, it's a pain to configure but it's worth), Linpack Xtreme, AIDA for memory.
> Add all that you can then but these above are the basics; CPU-z, CB, Corona, Sandra, SOTR, etc
> 
> Start comparing with Geekbench 5; a lot of different workloads, you'll see if something is not right straight away.
> Then compare the linpack scores and the monero miner hashrate.
> You need to have same or better results with FLCK2000.
> 
> It's very easy to think it's all right but when you go nitpicking there's often something which is not running at the speed which is supposed to.


Thanks a lot, that's all really helpful.🙂 I did take baselines at FCLK1800 and1900 for comparison but definitely wasn't as thorough as I should have been (and I dodged the miner completely!) so will go back and check how everything looks.


----------



## tcclaviger

Will 2nd 2080ti to 3080 is more of RT boosting side grade.

My 2080ti crushes most 3080s. Shunt mod it and keep it cool and a 2080ti is a fing monster.

It's also the bottom of all 2080ti bins, EVGA Black non-a chip. Holds 2205 at 1.05v 100% stable, even at 520 watts, that's rock steady, no floating speed, 2205 flat line.


----------



## ManniX-ITA

Bix said:


> Thanks a lot, that's all really helpful.🙂 I did take baselines at FCLK1800 and1900 for comparison but definitely wasn't as thorough as I should have been (and I dodged the miner completely!) so will go back and check how everything looks.


Good luck and let us know the results!


----------



## KedarWolf

When I left for work I was over 7 hours in on Cycle 8 of Usmus but 1000% on 8 cycles instead of 100% with no errors. I know from the past it runs not much more than 7 hours.

Also, I'm running Windows 10 LTSC IOT 2021 and it seems to be a bit better in AIDA than regular Windows 10.

I DO have a ton of services disabled though, but L2 cache seemed to go up from around 4300 to 4700 and write and copy a bit faster as well.


----------



## KedarWolf

@ManniX-ITA is soon going to surpass me in total post counts, month after month they are one of the most active peeps on the forum if not the most active for the month. 'gasp'

But I'm an overclock.net casual, and for me it's not a competition.


----------



## ManniX-ITA

KedarWolf said:


> But I'm an overclock.net casual, and for me it's not a competition.


Are you trying to humiliate the casual peeps?  
You are definitely a regular here!
Not a competition for me either; quality of the posts matters more than the quantity


----------



## tcclaviger

ManniX-ITA said:


> Are you trying to humiliate the casual peeps?
> You are definitely a regular here!
> Not a competition for me either; quality of the posts matters more than the quantity


Heard anything back on WHEA 0 error bug in 11? Wondering if there's a lower level function we can disable to preclude the checking in the first place.

Will keep snooping, have been looking a bit but haven't found anything yet to disable it completely.


----------



## KedarWolf

tcclaviger said:


> Heard anything back on WHEA 0 error bug in 11? Wondering if there's a lower level function we can disable to preclude the checking in the first place.
> 
> Will keep snooping, have been looking a bit but haven't found anything yet to disable it completely.


I had to give up on Windows 11, would BSOD when gaming etc. when it never BSODs on Windows 10.

And I pass Core Cycler, TM5, even MemTest Pro and RamTest, so I dunno what exactly the issue is.

I Googled the error code and some suggested disabling the Page File, then my PC just freezes instead of BSODing.


----------



## tcclaviger

11 works fine for me. Boosts nT scores and performance a touch, drops sT performance a touch.

Much Ado about nothing imho.

That's, of course, after stripping the OS of all the trash it comes with. Out of the box it's hands down, the worst thing since Windows ME imho.

Doing some low temp benches today while turkey cooks, 12700ks need to be caught!


----------



## Audioboxer

dk_mic said:


> sorry for off topic, but personally, I really wouldn't get ampere when you have a 2080 Ti. My best ambient air cooled 2080 Ti bench beats 66% of _all_ 25.5k entries from 5950x+3080 systems in timespy. 3080 only pulls away with raytracing in port royal.
> I would rather look into re-applying thermal paste, because there are so many bad fabric paste applications. Not sure if possible with a blower style card, but eventually you can open the shroud and mount some custom fans or get a 3rd party cooler like a morpheus.


It's watercooled in my loop, the only reason I bought the blower was because it was a bit cheaper and I knew it would be getting watercooled. Ran it for a bit on the fan before watercooling it, that's how I know how terrible it was with the cooler lol.

Given some of the overclocks I've seen some people get I'm actually going to look into something else one of my mates questioned me on tonight, my riser cable. Just using a PCIe 3.0 cable that came with my phanteks universal mount, but the riser cable market seems to be a crapshoot of quality issues.

The 3080 I speak of is from the EVGA step up queue, so I won't be paying anything extra for it, but for whenever it comes I needed to buy a good quality PCIe 4.0 riser cable anyway. Going to get it early and do a swap with my current cable and see if it helps with the GPU OCing.

Always a chance my riser cable isn't delivering the full power it should be and when the card is requesting higher power loads this is leading to crashing.



tcclaviger said:


> I recently had an AX1200i fail in a sneaky way, use HWinfo and open the graph for 12v rail while testing on 2nd screen.
> 
> Would randomly crash the PC in a way that looked like CPU OC failing.
> 
> At idle would hold 12.02v on 12v rail.
> On high CPU only load would see 11.9v. Oh high GPU only load, 11.3v, but no crash.
> When loading both hard, hard power off like OCP tripping, only at 600-650 watt loads.
> 
> The sneaky part was load/unload quickly of CPU from 300w to 30w to 300w would also trigger it, exactly like 3dmark does sometimes.
> 
> Put in my Thor 1200, 12v never dips below 12.1, ever.
> 
> AX1200i is being RMAd, when new I remember it never falling under 11.98v, even at 1280 watt load (1680v2 @ 4.8ghz and 3x980 Matrix OCd).


Another good thing to check alongside my riser cable, I'll monitor my HWINFO for the 12v rail.

*Edit* - Is this the 12v rail?










This 5 hours of uptime has included all my TimeSpy runs.

This is a Thor 850w so like your 1200 it doesn't seem to have dipped below 12.1v.

I'm honestly thinking outside of having a dud 2080Ti for OCing, it may well be of interest to change my riser cable. Decent quality 4.0 cables aren't too expensive now.


----------



## tcclaviger

Good, can eliminate that as your issue.

I did also have a finicky LianLI riser for vertical mounting. Oddly simply moving it around, etc, seems to have fixed it.

I ended up doing a setup for the loop in a way that 1 of my hardlines slightly pushes on the GPU laterally and no more issues now.


----------



## PJVol

tcclaviger said:


> So I swept the OCCT Benchmark spots for 5950x last night , I know though, many people aren't using it yet. There is way too much headroom left for me to think others are trying hard at this point.
> 
> The multi-avx test is a bit....variable, run 10 times in a row I can see high low score split of almost 200 points. The other 3 test are pretty consistent so I wouldn't use multiavx for checking the presence of clock stretching, but it is a phenomenal stability test!


I used this bench along with a Blender Koro scene for a while, alternating their launch, usually 2-3 times (4-6 total runs) for the Curve stability testing.
But found an interesting phenomenon just yesterday - as it turned out, in about half of the cases the crashes weren't due to core magnitudes instability.
So I just put a HWInfo sensor panel next to the OCCT window (internal monitoring is off, as it can't poll SMU for the pm table) and clearly saw why it crashed (in both SSE and AVX multi).

Look at the screens. The clocks in the right pane in both screenshots were captured right before the crash occurred, the short pane at the left - clocks typical for the usual successful run.




















The thing is, right after the SEE or AVX single core test, for some unknown reason, the C_ac_ thresholds for the corresponding workload (EDC throttler) weren't switched/applied from light to heavy, and as a result SMU starts to generate frequencies typical for a generic workloads, which for obvious reasons ends up with a failed test. I haven't yet figured out why this was happened, but either OCCT code or SMU firmware is clearly bugged.

PS: roughly every 5-7th multicore run is bugged, regardless of type of workload.
PPS: one more thing to investigate is whether HWInfo polling might potentially affect it.


----------



## Audioboxer

tcclaviger said:


> Good, can eliminate that as your issue.
> 
> I did also have a finicky LianLI riser for vertical mounting. Oddly simply moving it around, etc, seems to have fixed it.
> 
> I ended up doing a setup for the loop in a way that 1 of my hardlines slightly pushes on the GPU laterally and no more issues now.


I'm not even fussed about having a vertical GPU it's just when planning my runs in this case with 4 radiators, a GPU block, CPU block and RAM block a vertical GPU helps out with ease using hard tubing. Not going vertical obviously avoids any issues with riser cables or needing to spend on a decent quality 4.0 cable if you have a 3xxx GPU.

It's my understanding something like 75w comes from the PCIe slot, and then the rest is from the power supply connectors. Well, this card only has two connectors direct to the power supply so while those will do most of the heavy lifting, up near 380w I'm sure the PCIe slot becomes important. If there is any chance this riser cable is dodgy I guess it could explain kernel power related crashes or BSODs.

And yeah I'm using separate runs to my power supply.


----------



## tcclaviger

On 1080ti and earlier I always modded PCIE slot power as well as the 8 pins.

On 2080ti I only modded the 8 pin shunts. 

Pulls all (260*1.24)1.625 (524 watts) worth of power without issue, but typically it'll sit at around 390 watts in most tasks due to the curve boosting I've set capping at 1.062vcore.

The riser, hasen't in my experience been an issue with power, but I know they're not all created equal.

What brand is yours?

Do you think you might be hitting 12v line limits during transients?


----------



## Audioboxer

tcclaviger said:


> On 1080ti and earlier I always modded PCIE slot power as well as the 8 pins.
> 
> On 2080ti I only modded the 8 pin shunts.
> 
> Pulls all (260*1.24)1.625 (524 watts) worth of power without issue, but typically it'll sit at around 390 watts in most tasks due to the curve boosting I've set capping at 1.062vcore.
> 
> The riser, hasen't in my experience been an issue with power, but I know they're not all created equal.
> 
> What brand is yours?
> 
> Do you think you might be hitting 12v line limits during transients?


It's the cable that came with the Phanteks vertical mount and while many people use them and this mount in a Lian Li case I could just be unlucky. I'm completely speculating at this point but given it seems kernel power errors/BSODs have came with increasing power usage percentage it's either the card, the cable or the power supply. Power supply looks healthy. Issues have stopped with the power percentage being reduced back to 100%. Will now creep back up to 120% testing along the way where it was before I went up to 130%.

Either way I need a 4.0 cable for the future so I might as well change it over early. Only nuisance is another loop drain, but that is easily done. Given this Europe Step Up Queue is practically dead I doubt I'll get a 3080 exchange before Summer next year lol.

I should add it is of course a modded BIOS to get up to 130%, the default BIOS for this card tops out at 12% extra EVGA RTX 2080 Ti VBIOS


----------



## ManniX-ITA

Audioboxer said:


> Is this the 12v rail?


From what I've seen the Thor 850W has 4 rails instead of a single rail (which is IMO not good).
Unless there's a newer version with single rail...
You have to check if HWInfo is displaying the GPU voltages, cause the rail you see there it's that connected to the board, not the GPU via the PCIe connectors).












Audioboxer said:


> It's watercooled in my loop, the only reason I bought the blower was because it was a bit cheaper and I knew it would be getting watercooled. Ran it for a bit on the fan before watercooling it, that's how I know how terrible it was with the cooler lol.


Maybe a bad mounting?
Even if it looks good it's very common.
You have to check what is the delta C from water temperature under load for the block.



Audioboxer said:


> Just using a PCIe 3.0 cable that came with my phanteks universal mount, but the riser cable market seems to be a crapshoot of quality issues.


That could be an issue indeed.
I've heard many complaints about the Phanteks riser cables .
Have it too and indeed I'm going to buy this one, which is highly recommended, instead:



Amazon.de


----------



## Audioboxer

ManniX-ITA said:


> From what I've seen the Thor 850W has 4 rails instead of a single rail (which is IMO not good).
> Unless there's a newer version with single rail...
> You have to check if HWInfo is displaying the GPU voltages, cause the rail you see there it's that connected to the board, not the GPU via the PCIe connectors).
> 
> View attachment 2534348
> 
> 
> 
> 
> Maybe a bad mounting?
> Even if it looks good it's very common.
> You have to check what is the delta C from water temperature under load for the block.
> 
> 
> 
> That could be an issue indeed.
> I've heard many complaints about the Phanteks riser cables .
> Have it too and indeed I'm going to buy this one, which is highly recommended, instead:
> 
> 
> 
> Amazon.de












There we go, that looks more problematic.Those minimum voltages below 12v. Above is 95% without an OC, last 5% was just me briefly testing 110% with a +50 core boost.

It's not a bad mount if you mean the water block, my temps are absolutely fine.










Thor 850w. Would need to open my case to see what I have my GPU hooked up to, can't remember if it's top or bottom lol.


----------



## ManniX-ITA

Audioboxer said:


> It's not a bad mount if you mean the water block, my temps are absolutely fine.


No it's indeed your PSU that needs RMA... my condolences.
And here's another Seasonic gone.
With all due respect to the brand, it's piling up 

(honestly, sell it and buy a single rail)


----------



## Audioboxer

ManniX-ITA said:


> No it's indeed your PSU that needs RMA... my condolences.
> And here's another Seasonic gone.
> With all due respect to the brand, it's piling up


Definitely not cables, either from the PSU or the riser before I request an RMA?


----------



## ManniX-ITA

Audioboxer said:


> Definitely not cables, either from the PSU or the riser before I request an RMA?


There's a little, very little chance.
The PCIe voltage drop could be caused by the PCIe riser cable.
Only one rail is dropping below 12V, could be that one of the 8pin cable is defective.
Not much hope.


----------



## PJVol

ManniX-ITA said:


> And here's another Seasonic gone.


What! It can't be!


----------



## ManniX-ITA

PJVol said:


> What! It can't be!


It's like more speak about it and more they fail


----------



## Audioboxer

ManniX-ITA said:


> There's a little, very little chance.
> The PCIe voltage drop could be caused by the PCIe riser cable.
> Only one rail is dropping below 12V, could be that one of the 8pin cable is defective.
> Not much hope.


So change the 8 pin cable, if it still drops below, it needs RMA'd anyway, irrespective of the riser cable maybe causing the PCIe voltage drop?


----------



## ManniX-ITA

Audioboxer said:


> So change the 8 pin cable, if it still drops below, it needs RMA'd anyway, irrespective of the riser cable maybe cauing the PCIe voltage drop?


Yes, right assumption.


----------



## Audioboxer

ManniX-ITA said:


> Yes, right assumption.


Ah well, at least we got to the bottom of this. I had to RMA recently with Corsair and the whole process was easy as can be. Likely going to find out ASUS is a nightmare.... If I can get it RMA'd I'll likely sell the replacement.

Also for a yikes moment I don't know how many of you remember but my Asus Strix mobo died a few months back, followed by my 2080Ti. I wonder if this power supply killed the motherboard  Never found out what killed it as the retailer I bought it from just refunded it.


----------



## tcclaviger

Oh interesting, I didn't even think of multirail 12v PSU. Been so long since I've used one, but I've looked at all the credible review crossloading tests and 12v isolated load testing, and it doesn't seem to have issues push 700+ to a "GPU" line.

I would operate under the assumption the PSU is healthy for now, and try to isolate the riser cable as the potential issue.

Would also suggest, reflash gpu bios, just to be sure it took properly.

Aside from that there's the windows things to check, GPU scheduling, game mode, Nvidia driver power setting. Maybe disable overlays (steam, Nvidia) etc to try and isolate the issue. Xbox BS turned off too.

If it's not window setting, it leaves driver, PSU, riser. 

EDIT: BAM just dawned on me. Which driver are you on? The 496 (current) Nvidia WHQL drivers caused TONS of crashes for me. Went to the most recent developer driver (studio) no more issues, might be worth trying. I think it's 472s studio.


----------



## ManniX-ITA

tcclaviger said:


> I would operate under the assumption the PSU is healthy for now, and try to isolate the riser cable as the potential issue.


The GPU 8-pin #1 went down to 11.9V; it's either the PSU or the cable.
Could be as well the riser cable but that's maybe on top.
The PCIe slots usually get the power from the additional PCIe power near the CPU, not the 24p ATX.
So the drop is not seen from the board +12V unless it has another specific reading.


----------



## PJVol

Nah... just run Hwinfo with a "snapshot polling" turned off, and on the second run, clocks in SSE multicore test jumped 4820 allcore, that is ridiculously high (previous run was at ~4710) and predictably failed.


----------



## ManniX-ITA

Audioboxer said:


> Ah well, at least we got to the bottom of this. I had to RMA recently with Corsair and the whole process was easy as can be. Likely going to find out ASUS is a nightmare.... If I can get it RMA'd I'll likely sell the replacement.


Since you are probably forced to shop for a new PSU:






PSU Tier List rev. 14.8


PSU Tier List 4.0 rev. 14.8 (END OF LIFE) Last Update: 27-07-2021 Legend : Gray - EoL/obsolete and/or otherwise not recommended for purchase. Green - small form-factor (gold and blue colors are disregarded due to scarcity of SFX PSUs) Gold - best units in the tier (includes requirements for blue ...




linustechtips.com





One I heard good things about (and not bad ones):






The Signature Titanium 1000 is the 80 PLUS Titanium Fully Modular PSU and best power supply with 1000W/135mm FDB Fan/LLC + DC to DC Design/Full Japanese Caps/10-Year Warranty - Antec


The Signature Titanium 1000 equipped with superior features that ensure peak performance for the enthusiast and gaming-oriented segment, the Signature power supply Series boasts unparalleled stability and 80 PLUS® Titanium-certified efficiencies. Advanced thermal control with the Zero RPM mode...




www.antec.com







PJVol said:


> Nah... just run Hwinfo with a "snapshot polling" turned off, and on the second run, clocks in SSE multicore test were 4820, that is absurdly high (previous run was at ~4710) and predictably failed.


I had this weird random failures with OCCT bench with the 3800x.
But I didn't check the clocks.


----------



## Audioboxer

ManniX-ITA said:


> Since you are probably forced to shop for a new PSU:
> 
> 
> 
> 
> 
> 
> PSU Tier List rev. 14.8
> 
> 
> PSU Tier List 4.0 rev. 14.8 (END OF LIFE) Last Update: 27-07-2021 Legend : Gray - EoL/obsolete and/or otherwise not recommended for purchase. Green - small form-factor (gold and blue colors are disregarded due to scarcity of SFX PSUs) Gold - best units in the tier (includes requirements for blue ...
> 
> 
> 
> 
> linustechtips.com
> 
> 
> 
> 
> 
> One I heard good things about (and not bad ones):
> 
> 
> 
> 
> 
> 
> The Signature Titanium 1000 is the 80 PLUS Titanium Fully Modular PSU and best power supply with 1000W/135mm FDB Fan/LLC + DC to DC Design/Full Japanese Caps/10-Year Warranty - Antec
> 
> 
> The Signature Titanium 1000 equipped with superior features that ensure peak performance for the enthusiast and gaming-oriented segment, the Signature power supply Series boasts unparalleled stability and 80 PLUS® Titanium-certified efficiencies. Advanced thermal control with the Zero RPM mode...
> 
> 
> 
> 
> www.antec.com
> 
> 
> 
> 
> 
> 
> 
> I had this weird random failures with OCCT bench with the 3800x.
> But I didn't check the clocks.


Thanks.

It seems like my riser cable is crap anyway as well, going as low as 11.8v is  I presume a good cable will have no issue maintaining 12v here.


----------



## ManniX-ITA

Audioboxer said:


> It seems like my riser cable is crap anyway as well, going as low as 11.8v is  I presume a good cable will have no issue maintaining 12v here.


Could be also just the PSU.
But I would buy a better one anyway...


----------



## Audioboxer

ManniX-ITA said:


> Could be also just the PSU.
> But I would buy a better one anyway...


There's soo many damn power supplies to choose from lol. But my new advice for today seems to be a single rail is better than a multirail?

Also reading people say online the 'spec' is +/- 5% on the rail, so no doubt ASUS are going to refuse RMA


----------



## PJVol

ManniX-ITA said:


> I had this weird random failures with OCCT bench with the 3800x.


Yeah, I almost put it into "must have" tier, but even that would hardly make me buy their per-year license, for the advertised "only a few dollars" )) $249 in fact, for the version with **** - data export to CSV file, goodness me, what a greedy mf's )


----------



## Audioboxer

Heaven Benchmark with an uncapped framerate (not limited to 144 in Nvidia control panel) is enough to drop the PCIe 12v input and GPU 8-pin #1 down below 12v.


----------



## tcclaviger

11.883 isn't necessarily an issue, it's well within atx spec, only a 1% drop, though it's not good. 

I am still confident this will fix your issue:








NVIDIA Studio Driver | 472.47 | Windows 10 64-bit, Windows 11 | NVIDIA


Download the English (US) NVIDIA Studio Driver for Windows 10 64-bit, Windows 11 systems. Released 2021.11.10



www.nvidia.com


----------



## Audioboxer

tcclaviger said:


> 11.883 isn't necessarily an issue, it's well within atx spec, only a 1% drop, though it's not good.
> 
> I am still confident this will fix your issue:
> 
> 
> 
> 
> 
> 
> 
> 
> NVIDIA Studio Driver | 472.47 | Windows 10 64-bit, Windows 11 | NVIDIA
> 
> 
> Download the English (US) NVIDIA Studio Driver for Windows 10 64-bit, Windows 11 systems. Released 2021.11.10
> 
> 
> 
> www.nvidia.com


I'll roll back the drivers but I'm worried about the voltage figures. I've emailed ASUS so I'll see what they say. Probably moan it's in spec lol.

I've got another 8 pin to test. Riser cable will need to wait till next week.

Are there any other tests or voltage readings I can look to for PSU issues?


----------



## KedarWolf

tcclaviger said:


> 11.883 isn't necessarily an issue, it's well within atx spec, only a 1% drop, though it's not good.
> 
> I am still confident this will fix your issue:
> 
> 
> 
> 
> 
> 
> 
> 
> NVIDIA Studio Driver | 472.47 | Windows 10 64-bit, Windows 11 | NVIDIA
> 
> 
> Download the English (US) NVIDIA Studio Driver for Windows 10 64-bit, Windows 11 systems. Released 2021.11.10
> 
> 
> 
> www.nvidia.com


I think it's a thing with Corsair, my AX1600i 12v rail goes below 11.8 when running 3DMark Port Royal.


----------



## Audioboxer

KedarWolf said:


> I think it's a thing with Corsair, my AX1600i 12v rail goes below 11.8 when running 3DMark Port Royal.


I've got an ASUS Thor 850w though, which is a rebranded Seasonic. Rails are all above 12v for me under light loads, heck, Heaven benchmark with a 144FPS cap stays above 12v. Heavy loads such as Heaven uncapped framerate is when the dip under 12v comes.

If I have my GPU up at 130% and this is trying to pull like 380W I guess this is what causes a reboot or shutdown and kernel power error. GPU must be struggling to get what it wants out of the power supply.

Thinking of just buying a Be Quiet Dark Power 12 and just throwing power at my components 🤣


----------



## KedarWolf

I thought you meant CPU 12v rail but here's my GPU while running Port Royal, so yes, I think it's a Corsair issue.


----------



## Audioboxer

KedarWolf said:


> I thought you meant CPU 12v rail but here's my GPU while running Port Royal, so yes, I think it's a Corsair issue.
> 
> View attachment 2534373


Nah we've been troubleshooting me getting a kernel power error yesterday. Ruled out the PBO bias exploit and instead figured out it was me increasing the GPU power percentage higher than I had it previously. Then it was about just an unstable OC versus a power delivery issue.

Me dipping below 12v on the PCIe and 1 8 pin had the recommendation it was the PSU and/or riser cable, but likely PSU isn't good enough anyway. Cue some bashing of Seasonic lol. I'm a total noob with power supplies, so I have to take a back seat here and let others advise.

Those figures you posted seem much lower than mine but I presume your card is working OK? I think I ran Port Royal earlier, I'll test it again at my end.

Unless ASUS just approve an RMA because they can't be bothered troubleshooting a PSU I'm going to guess 11.8v is going to be rejected and said within spec lol. Especially if Corsair are selling PSUs going to 11.6v.


----------



## KedarWolf

Audioboxer said:


> Nah we've been troubleshooting me getting a kernel power error yesterday. Ruled out the PBO bias exploit and instead figured out it was me increasing the GPU power percentage higher than I had it previously. Then it was about just an unstable OC versus a power delivery issue.
> 
> Me dipping below 12v on the PCIe and 1 8 pin had the recommendation it was the PSU and/or riser cable, but likely PSU isn't good enough anyway. Cue some bashing of Seasonic lol. I'm a total noob with power supplies, so I have to take a back seat here and let others advise.
> 
> Those figures you posted seem much lower than mine but I presume your card is working OK? I think I ran Port Royal earlier, I'll test it again at my end.
> 
> Unless ASUS just approve an RMA because they can't be bothered troubleshooting a PSU I'm going to guess 11.8v is going to be rejected and said within spec lol. Especially if Corsair are selling PSUs going to 11.6v.


Yeah, my PC and card are running fine.

And I installed the iCue software and changed my PSU from multi-rail to single-rail and it never helped at all. 

I've had no end of issues with Windows 11 BSODing that never happens on Windows 10, and this with CPU, card and memory stress-tested totally stable.


----------



## KedarWolf

You can use GPU-Z and it's actually better than HWInfo.


----------



## Audioboxer

KedarWolf said:


> Yeah, my PC and card are running fine.
> 
> And I installed the iCue software and changed my PSU from multi-rail to single-rail and it never helped at all.
> 
> I've had no end of issues with Windows 11 BSODing that never happens on Windows 10, and this with CPU, card and memory stress-tested totally stable.


Oh don't get me started on Windows 11, absolute mess. I don't even know if it's contributing to issues lol. Multiple updates now but still L3 cache is broken and AMD chipset drivers I don't even feel I can trust.

One thing I do think that has been broken for a while is the 496.xx drivers from Nvidia. Lots of complaints and failed attempts at hotfixes. I will be rolling them back tomorrow and putting my GPU power slider back up to 130% just to see what happens.

Last step is changing to another 2080Ti BIOS just to see if this one is causing any issues.

I'll grab GPU-Z as well for monitoring.

I am a bit confused about the Asus Thor though, Manni said it wasn't a single rail but online reviews say it is



> The ROG THOR 850W is advertised as being a single 12v rail power supply with a capacity up to 71A (or ~100% of the unit’s capacity) if necessary available to the 12v rail. The minor rails (5v and 3.3v) have a capacity of 20A each and the combined capacity of those two rails is 100W. Combined with these outputs, we find that this unit has 4 PCIe connectors, 10 SATA connectors, and 5 Molex connectors.


----------



## Veii

PJVol said:


> Does anyone know, what error #13 in a 1usmus tm5 config might mean?
> I really doubt it is "overheating", unless lowering ProcODT actually results in more heat. Could it be so?
> 
> 
> PJVol said:
> 
> 
> 
> Forgot to add, why I'm asking of #13 and ProcODT.
> In fact, only increasing it to 36.9Ohms helped to get rid of those annoying #13's and #10's. I just never set so high impendance before on these modules.
Click to expand...

While it is overheating - it mostly translates to a too noisy signal, fault by overheating and similar noise cases

i'm in the middle of redoing the error list and tCKE range for Dual Rank
They behave, different
#13 is what i close to always get or instantly #6, 10, 12's with #2's

#6 will be renamed to "catastrophic failure"
Be it by an unstable CPU, bad VDDG, too low primaries, too low tWTR, too low VDIMM,
too high ClkDrvStr , too high RTT_PARK, too high procODT
"Signal dropout catastrophic failure"

Less catastrophic is #4 but on a similar level ~ "signal dropout/crashing failure"
- focused on the PCB reason

Also less catastrophic but still powering related are,
#12 + #2 & #0 + #10

#13 are timing based issues
While it is purely overheat, it's mostly timing based ~ to cause a dropout
If you only get #13, it's that timings are too low
Dimms still overheating, but mostly related to
a "too noisy signal" ~ needs higher tertiaries or weaker powering
======
All i can say so far
Still working on 1T, but it will end up as "nearly impossible on these boards"
ASUS has tPHY training issues, MSI has tPHY training issues.
ASUS needs fast boot disabled and manually enforced limits, else the board doesn't know what to select. Anything on Auto and it doesn't train or misstrains ~ even when result-predictions are identical. FW issues
Timing predictions appear good, but powering predictions are completely broken. Not even being funny how bad it is for DR

DR remains an architectural issue ~ PCB design issue for DIMM PCB vs AMD Engineering design.
AddrCmd Drv & Delay are an issue
AddrCmd lane appears to be designed with too tight tolerances. Any wiggle degrades signal integrity too strong
X-20-X-X is fine for SR, X-24-X-X is needed ! for DR.
X-30-X-X is also needed but falls inside too low tolerances and ruins Signal Integrity fully.
Listing it as "nearly impossible to fix" ~ issue

30-24-30-20 so far works for DR
40-24-30-20 is needed, but signal integrity suffers too much and 14-14 timings just fail.
120-X-24-24 works and is required on low freq 13-13-13


Spoiler














But non 1DPC boards need a bump in AddrCmdDrv
Which completely ruins signal integrity


Spoiler: Something Amateur














 tRRD_ bump was required ~ 1.47v. Fails on 1.46 already. Also reaches 48c and #13 unless tRRD_ got a big bump for noise stability
tCKE is responsible for more than MCLK alignment and DR ranges are different. Soo redoing the range fully
For 1T signal integrity is horrible. Need to figure something out + prevent misstraining. Complicated

That's all for now
EDIT:
Forum "Only show this user" feature , is fantastic ~ thanks a bunch
EDIT2:
tRDWR, tWRRD, SCL are root causes for misstraining dimms
cLDO_VDDP & RTT are less, to nearly non.
If tRDWR & tWRRD allign, if tCL & tCWL align ~ it will never misstrain


----------



## ManniX-ITA

PJVol said:


> Yeah, I almost put it into "must have" tier, but even that would hardly make me buy their per-year license, for the advertised "only a few dollars" )) $249 in fact, for the version with **** - data export to CSV file, goodness me, what a greedy mf's )


Actually the guy is quite nice 
But indeed he got a bit too greedy lately.
Don't forget it was completely free for many many years.

The CSV export is a Pro feature... debatable in my opinion.
It does cost less than 35 € per year for personal.
Which is too much for this kind of software.
Before he got greedy, I've bought for few bucks a lifetime license.

Considering that the core of the software is Prime95... not very elegant to ask for all this money.


----------



## ManniX-ITA

Veii said:


> Forum "Only show this user" feature , is fantastic ~ thanks a bunch


Wow, didn't see it... I want to cry from joy


----------



## ManniX-ITA

Audioboxer said:


> Thinking of just buying a Be Quiet Dark Power 12 and just throwing power at my components


Don't do it, I've read too many people having same issues as with the Seasonic.
Better Corsair RMx, AX then. They fail sometimes but less.

Just tell ASUS your GPU is crashing under load don't reference the voltages reading.



Audioboxer said:


> I am a bit confused about the Asus Thor though, Manni said it wasn't a single rail but online reviews say it is


There could have been multiple revisions over the years.
You need to check the package if you have it or the label on the PSU itself, if visible.



KedarWolf said:


> I thought you meant CPU 12v rail but here's my GPU while running Port Royal, so yes, I think it's a Corsair issue.


This shouldn't happen, it's a miracle that it's not crashing like hell.

Here's what you should see after a Port Royal run:










The 8-pin input voltages never below 12.0V.

Even if the Intel ATX specs are saying that 11.4V is the minimum you need to account the massive transients nVidia GPUs have.
You can only see them with a decent oscilloscope.
Dropping below 12V for 500W load only on a 850W means something is wrong.

If the GPU sensors can detect below 12.0V under load then when there's a huge transient the voltage drops more than what you can see in HWInfo.
And then the GPU crashes.

If you read the posts in the 3080ti/3090 threads about GPU crashing they all had readings below 12V under load.
And all have fixed it replacing the PSU. Which doesn't go below 12V under load.


----------



## dk_mic

So, another Seasonic: Prime TX 750 .. after a bit of idle, timespy extreme, port royal and heaven with a power draw of up to 350W. Is this something to be concerned about then?


----------



## ManniX-ITA

Audioboxer said:


> I am a bit confused about the Asus Thor though, Manni said it wasn't a single rail but online reviews say it is


I have checked a few reviews and indeed seems to be a single rail.
Had headache yesterday and still have it... wonder where I ended up. Maybe I've read a review for another Thor PSU, dunno 

Anyway the reviews are pretty clear:









ASUS ROG THOR 850W Platinum Power Supply Review - KitGuru


Last year ASUS entered the power supply market. We reviewed their ROG Thor 1200W Power supply, a hea




www.kitguru.net





On the Kitguru review only in cross load at max load it goes below 12V, to be precise 11.98V.

This is a graph of the voltage under load:











I've read another review saying 0.5% drop on 12V.
While within the specs limits it's not normal this drop at 500W.



dk_mic said:


> So, another Seasonic: Prime TX 750 .. after a bit of idle, timespy extreme, port royal and heaven with a power draw of up to 350W. Is this something to be concerned about then?


I would but I'm surprised about Kedar readings 
Maybe if the PSU is really overkill it can hold better even if dropping well below 12V.

In general is acceptable 200mV drop under full load, voltage always goes down with load. 
But not below full load, at least for high quality PSUs.
Means the voltage regulators are not doing their job properly, regulating.

Either you have an old behemoth like mine which is running normally at 12.4V and drops more, for me is 200mV at 750W/1300W, probably close to 400mV at full load (never came close).
Or you have the new ones which are more sophisticated and are running at 12.1V/12.2V but they also drop much less voltage under load.

In any case the drop below 12V should be very close, around 11.9V and something and only when the PSU hits max load.
And if it's happening during Superposition or Port Royal which have very low CPU usage it's usually a big problem.
Gaming usually is stressing CPU as well so it gets even more problematic.

The nVidia GPU boosting introduced with the 2000 series it's brutal, there are massive transients lasting a bunch of milliseconds.
And during these spikes the voltage can drop much below 11.4V if the PSU is faltering and the result is that the GPU crashes.

Those with GPU crashing and readings so low, usually Seasonic 750/850 and beQuiet/Corsair 750-1000, fixed the crashing replacing the PSU.

Maybe if the PSU can hold a decent voltage even during these transients the GPU doesn't crash.
But if there's a big voltage drop below full load, something is wrong with PSU. 
The good ones all have reviews; better to compare what should be the reference.


----------



## KedarWolf

ManniX-ITA said:


> Don't do it, I've read too many people having same issues as with the Seasonic.
> Better Corsair RMx, AX then. They fail sometimes but less.
> 
> Just tell ASUS your GPU is crashing under load don't reference the voltages reading.
> 
> 
> 
> There could have been multiple revisions over the years.
> You need to check the package if you have it or the label on the PSU itself, if visible.
> 
> 
> 
> This shouldn't happen, it's a miracle that it's not crashing like hell.
> 
> Here's what you should see after a Port Royal run:
> 
> View attachment 2534388
> 
> 
> The 8-pin input voltages never below 12.0V.
> 
> It might be my cables. I use Cablemod Pro, which are supposed to be good, but I dunno. I can swap in the stock Corsair cables, see.
> 
> Even if the Intel ATX specs are saying that 11.4V is the minimum you need to account the massive transients nVidia GPUs have.
> You can only see them with a decent oscilloscope.
> Dropping below 12V for 500W load only on a 850W means something is wrong.
> 
> If the GPU sensors can detect below 12.0V under load then when there's a huge transient the voltage drops more than what you can see in HWInfo.
> And then the GPU crashes.
> 
> If you read the posts in the 3080ti/3090 threads about GPU crashing they all had readings below 12V under load.
> And all have fixed it replacing the PSU. Which doesn't go below 12V under load.


----------



## Audioboxer

ManniX-ITA said:


> Don't do it, I've read too many people having same issues as with the Seasonic.
> Better Corsair RMx, AX then. They fail sometimes but less.
> 
> Just tell ASUS your GPU is crashing under load don't reference the voltages reading.
> 
> 
> 
> There could have been multiple revisions over the years.
> You need to check the package if you have it or the label on the PSU itself, if visible.
> 
> 
> 
> This shouldn't happen, it's a miracle that it's not crashing like hell.
> 
> Here's what you should see after a Port Royal run:
> 
> View attachment 2534388
> 
> 
> The 8-pin input voltages never below 12.0V.
> 
> Even if the Intel ATX specs are saying that 11.4V is the minimum you need to account the massive transients nVidia GPUs have.
> You can only see them with a decent oscilloscope.
> Dropping below 12V for 500W load only on a 850W means something is wrong.
> 
> If the GPU sensors can detect below 12.0V under load then when there's a huge transient the voltage drops more than what you can see in HWInfo.
> And then the GPU crashes.
> 
> If you read the posts in the 3080ti/3090 threads about GPU crashing they all had readings below 12V under load.
> And all have fixed it replacing the PSU. Which doesn't go below 12V under load.


Seems like my PSU is probably within spec then but a poorer quality unit. Seems it's my PCIe voltage that is of more concern but I'm guessing that can be explained by the riser cable. Going to swap over an 8 pin cable in an hour or two and see if it helps at all.

If I'm going to replace even if ASUS RMA I take it the Corsair RMx is fine? Or is HX better?


----------



## ManniX-ITA

Audioboxer said:


> If I'm going to replace even if ASUS RMA I take it the Corsair RMx is fine? Or is HX better?


The HX is better indeed. Platinum instead of Gold, slight better efficiency in theory.
Should be less noisy and it does have the link control (can also switch from single to multi).
It's one step below the AXi.


----------



## KedarWolf

ManniX-ITA said:


> Don't do it, I've read too many people having same issues as with the Seasonic.
> Better Corsair RMx, AX then. They fail sometimes but less.
> 
> Just tell ASUS your GPU is crashing under load don't reference the voltages reading.
> 
> 
> 
> There could have been multiple revisions over the years.
> You need to check the package if you have it or the label on the PSU itself, if visible.
> 
> 
> 
> This shouldn't happen, it's a miracle that it's not crashing like hell.
> 
> Here's what you should see after a Port Royal run:
> 
> View attachment 2534388
> 
> 
> The 8-pin input voltages never below 12.0V.
> 
> Even if the Intel ATX specs are saying that 11.4V is the minimum you need to account the massive transients nVidia GPUs have.
> You can only see them with a decent oscilloscope.
> Dropping below 12V for 500W load only on a 850W means something is wrong.
> 
> If the GPU sensors can detect below 12.0V under load then when there's a huge transient the voltage drops more than what you can see in HWInfo.
> And then the GPU crashes.
> 
> If you read the posts in the 3080ti/3090 threads about GPU crashing they all had readings below 12V under load.
> And all have fixed it replacing the PSU. Which doesn't go below 12V under load.


Yeah, it was the CableMod cables. Now my 12v lanes don't go below 12.05v and my CPU 12v doesn't either with the stock Corsair cables.

That's a game-changer, I've going to have to run all my benches and stuff again. :/


----------



## ManniX-ITA

KedarWolf said:


> Yeah, it was the CableMod cables. Now my 12v lanes don't go below 12.05v and my CPU 12v doesn't either with the stock Corsair cables.
> 
> That's a game-changer, I've going to have to run all my benches and stuff again. :/


Well at least it's not the PSU!

The cables quality is a big issue...
From what I recall, the Antec is highly recommended also cause it should be the one with biggest cable section diameter for PCIe 8-pin.


----------



## Taraquin

Ridianod said:


> guys hi. I took just error 6 on TM5. What should do the pass that? I found "Error 6 is purely related to the IMC , be if procODT, CLDO_VDDP or vSOC" Should I increase or decrease these values?
> View attachment 2534255


WR should be RTP x 2 so either try RTP 5 or WR 14/7 RTP, could work better.


----------



## Audioboxer

ManniX-ITA said:


> The HX is better indeed. Platinum instead of Gold, slight better efficiency in theory.
> Should be less noisy and it does have the link control (can also switch from single to multi).
> It's one step below the AXi.


Last question, is there any genuine reason to buy something like 1000w with a single GPU? In theory 850w seems fine for my use but asking anyway.

I can get the RMx like half the cost of the Hx so I'll read some more reviews. Don't want to go from one PSU with issues to another.

First thing is first, making sure my 8 pin cable isn't dodgy. I'm operating under the assumption my riser cable just isn't good enough, so that will be replaced anyway.


----------



## ManniX-ITA

Audioboxer said:


> Last question, is there any genuine reason to buy something like 1000w with a single GPU? In theory 850w seems fine for my use but asking anyway.


Well, rumors are the 4000s will peak 600W...
I've bought the 1300W in 2013 and never regretted it.
Sure, you'll pay a few Watts more power consumption in idle.
But the additional headroom means reliability.
Better everything. Always spent more than needed on PSUs and not even once regretted it.



Audioboxer said:


> I can get the RMx like half the cost of the Hx so I'll read some more reviews. Don't want to go from one PSU with issues to another.


Yes the RMx is very cheap compared to the others.
Didn't read much about the HX.
Mostly people go for the cheap RM or top notch AX.
Read all the reviews you can and scout forums for people reporting issues.

Being the Thor Platinum a single rail... maybe it's worth to keep it?
You can always keep a cheap RM as backup, sell it or just send it back if ASUS is replacing the Thor quickly.



Audioboxer said:


> First thing is first, making sure my 8 pin cable isn't dodgy. I'm operating under the assumption my riser cable just isn't good enough, so that will be replaced anyway.


Indeed. Cables can be the issue.
I would replace the riser cable as well, in any case.
Read too many horror stories about them, especially those coming with Phanteks cases.
Have to mount the GPU vertical as well due to the water block and limited space.
Won't take any risk.


----------



## mongoled

ManniX-ITA said:


> Are you trying to humiliate the casual peeps?
> You are definitely a regular here!
> Not a competition for me either; quality of the posts matters more than the quantity


I dont get why Kedar even felt that needed saying, "hey lets draw attention to myself"

😂 😂



Audioboxer said:


> I needed to buy a good quality PCIe 4.0 riser cable anyway


So what would be a good quality riser cable ?



ManniX-ITA said:


> Could be also just the PSU.


Could be many things, unsure why you are on the seasonic hammer wagon

😂😂



tcclaviger said:


> 11.883 isn't necessarily an issue, it's well within atx spec, only a 1% drop, though it's not good.


Thank you, someone bringing a little sanity to the conversation.

Peeps, we are looking at reading via software!

At least stick a multimeter on the 12v rail and check the reading from there if you are worried for nothing



Now to start reading about riser cards and installation, fedup of waiting and that its going to be 2023 when we may see some change in graphics card prices im going to buy a Zotac barebone with a RTX 3070 and slap a block onto it.....


----------



## Audioboxer

mongoled said:


> I dont get why Kedar even felt that needed saying, "hey lets draw attention to myself"
> 
> 😂 😂
> 
> 
> So what would be a good quality riser cable ?
> 
> 
> Could be many things, unsure why you are on the seasonic hammer wagon
> 
> 😂😂
> 
> 
> Thank you, someone bringing a little sanity to the conversation.
> 
> Peeps, we are looking at reading via software!
> 
> At least stick a multimeter on the 12v rail and check the reading from there if you are worried for nothing
> 
> 
> 
> Now to start reading about riser cards and installation, fedup of waiting and that its going to be 2023 when we may see some change in graphics card prices im going to buy a Zotac barebone with a RTX 3070 and slap a block onto it.....


From my little reading on PCIe 4.0 it looks like LinkUp pretty much came out first and cornered the market.

CoolerMaster have now released a PCIe 4.0 riser cable that seems OK.

Basically if it's cheap and claims 4.0 avoid it. Stick with LinkUp is probably my advice.

4.0 cables are backward compatible with 3.0 so at this point I simply wouldn't invest in anything else. 3.0 cables might be cheaper but that seems to be the issue, the quality control on the market is awful. With 4.0 16x to 16x there is in theory a high standard that has to be met to even function.


----------



## mongoled

Audioboxer said:


> From my little reading on PCIe 4.0 it looks like LinkUp pretty much came out first and cornered the market.
> 
> CoolerMaster have now released a PCIe 4.0 riser cable that seems OK.
> 
> Basically if it's cheap and claims 4.0 avoid it. Stick with LinkUp is probably my advice.
> 
> 4.0 cables are backward compatible with 3.0 so at this point I simply wouldn't invest in anything else. 3.0 cables might be cheaper but that seems to be the issue, the quality control on the market is awful. With 4.0 16x to 16x there is in theory a high standard that has to be met to even function.


Great the LinkUp is on Amazon.de, bloomin expensive for a piece of cable!

Now to investigating if i even want to use a vertical mount ............


----------



## Audioboxer

Alright so ready to swap the cable around, but first thing is first reconfirming what input was dropping










Well, running this morning neither 8-pin was dropping under 12v, though one of them was worse off. Before letting this run longer I decided to ramp up to 130% power usage on the GPU (no mem or core freq increase, just the power slider).










Boom, everything drops, other than the #2 Input.

PCIe 12v performance is horrible all round, even without a power use increase, so this riser cable simply has to go. But its weird input 1 was holding out on 100% GPU use while yesterday it seemed to have an issue. With it running lower than input 2 though I'm now going to explore if swapping the cable around first of all swaps the behaviour, then if it does, exchanging for another PSU cable.

*edit* - Just before I do the above I thought I better get a screenshot with GPU-Z










Shows the same as HWINFO. That's at 100% power usage above, so running this a second time has edged input 1 below 12v.


----------



## tcclaviger

So after much twisting of knobs and pulling of UEFI levers....

with the 48gb setup
3733/1866 C14 1T is viable
3866/1933 C16 2T is viable (1T is being...stubborn)

The higher speed wins all benchmarks, not what I would have guessed, but benchmarks tell another tale.

VDIMM 1.52 SET (no idea on GET), starting up TM5 as I go to bed. Will throw more voltage at it tomorrow and try C14 3866.


----------



## ManniX-ITA

mongoled said:


> Could be many things, unsure why you are on the seasonic hammer wagon


I'm not hitting on Seasonic without reason 
Always loved the brand and was in my top 3 for a new PSU.
But it's very noticeable that lately many, too many, had issues.
It could be a bad batch of components but also not.
Considering the astronomical prices the PSUs have now and the potential damages, it's something that needs caution.



mongoled said:


> Thank you, someone bringing a little sanity to the conversation.
> 
> Peeps, we are looking at reading via software!


Yes but the GPU is moderately precise, not half rubbish like most board sensors.
Double check with a DMM is always good but not really necessary.
This kind of drop at half load it's not normal for a quality PSU.
If it was 50 € junk, well.. it's junk.
These PSUs they have 0.5-1.5% voltage drop and only at full load.
If it's not like that something is wrong, either the PSU or the cable.


----------



## tcclaviger

Grew curious, and figured this would probably be the closest comparison you'll get since were both on Thor PSU (though mine is the 1200) and both on 2080tis. PSU is about 1.5 years old, been sitting around for like 16 months, only been in use for a couple weeks:

Keep in mind 100% power = 429 watts not 260 for my card and 108 input power is actually 178.

Would definitely appear your Thor is on the way out.

Coincidentally that was a PB Port Royal run lmao, guess I hadn't run it since the AX1200i got replaced.


----------



## Audioboxer

Okay, really confused now. I swapped the inputs around, so, same cables, just switched 1 into 2 and vice versa.










First behaviour at 100%, Input 2 still seems to be a little bit ahead, but maybe not as much?










110% power, still holding up.










120% power, still holding up (my old OC was at 120%).










130%, still holding up.










Idle voltage still shows input 2 ahead of input 1 with cables swapped, but I wonder if its just normal one of the GPU inputs might draw more?

Bigger question to ask is how come thing seemed to hold up a little better? Will do more testing now. 130% on this BIOS is 330w max, I forgot I wasn't running a BIOS that tops out at 380w.

The riser cable definitely has to go, but could swapping the slots the cables were in really have done something?  I also noticed I don't actually have a spare cable as such, the third PCIe cable included by ASUS is one that is a splitter, or a 2 in 1. But surely if it was just used as a single connection for testing that wouldn't matter?

*edit* - Add an OC and leave it running for longer at 130% and we're dipping back under 12v on input 1 &2










Such a small amount sometimes GPU-Z doesn't register it as 11.9v, but I have seen it briefly change to 11.9v on both inputs.

Going to try another BIOS now, I don't think it's anything to do with cables. Other than the riser cable being crap.


----------



## ManniX-ITA

Audioboxer said:


> *edit* - Add an OC and leave it running for longer at 130% and we're dipping back under 12v on input 1


It's a weird behavior. But I'm smelling that the PSU is not working properly.
Anyway try first to change the riser cable.
Even if there's the mainboard in between could be it's messing with the whole +12V rail.


----------



## tcclaviger

Doing some more experimentation myself, I also see GPU 8pin #1 always pull a tiny bit more power than #2, consistent with yours, so it shows slightly more droop. Where I see our results meaningfully differ is how much the PCIE 12v sags under load, and since that is still locked to 75 watts for me, it tells me you have a lot more resistance between the 24 pin and GPU, so somewhere in the board (unlikely) or the riser cable.

What Motherboard are you on and do you have the PCIE additional power socket plugged in if you have one, Molex 4 pin on Asus board usually?

For the sake of saving money before buying new parts, is it viable to toss it directly in the slot to remove the riser as the potential failure point?

IRT someone mentioning the soaring price of PSUs... holy hell have they!! AX1600i is $609 now!!

Using the split cable, but only 1 half of it will not harm anything as you suspect, at least not temporarily for testing.


----------



## ManniX-ITA

tcclaviger said:


> Doing some more experimentation myself, I also see GPU 8pin #1 always pull a tiny bit more power than #2, consistent with yours. Where I see our results meaningfully differ is how much the PCIE 12v sags under load, and since that is still locked to 75 watts for me, it tells me you have a lot more resistance between the 24 pin and GPU, so somewhere in the board (unlikely) or the riser cable.


yes the balancing is always a bit different, it's not equally shared, plus is driven by the GPU bios limits.
You can check with ABE if it can read the rom file:

On this 3090 bios the 8-pin #2 is limited to 150W while the others to 175W:













tcclaviger said:


> IRT someone mentioning the soaring price of PSUs... holy hell have they!! AX1600i is $609 now!!


Wow... it's getting worse 
Indeed when I checked how much should I spent to replace mine with something better it was 500 €


----------



## Audioboxer

tcclaviger said:


> Doing some more experimentation myself, I also see GPU 8pin #1 always pull a tiny bit more power than #2, consistent with yours, so it shows slightly more droop. Where I see our results meaningfully differ is how much the PCIE 12v sags under load, and since that is still locked to 75 watts for me, it tells me you have a lot more resistance between the 24 pin and GPU, so somewhere in the board (unlikely) or the riser cable.
> 
> What Motherboard are you on and do you have the PCIE additional power socket plugged in if you have one, Molex 4 pin on Asus board usually?
> 
> For the sake of saving money before buying new parts, is it viable to toss it directly in the slot to remove the riser as the potential failure point?
> 
> IRT someone mentioning the soaring price of PSUs... holy hell have they!! AX1600i is $609 now!!
> 
> Using the split cable, but only 1 half of it will not harm anything as you suspect, at least not temporarily for testing.


B550 Unify X and no additional PCIe devices plugged in. Only other thing I have is my Corsair NVMe drive.

Given the behaviour of my PCIe 12v input I'm going to blame the riser cable and will get another one to quickly check that. ASUS will likely be a few days before they respond to my RMA claim anyway.

No easy way to plug in directly as the GPU is in my loop lol. Just time to buy a good quality PCIe 4.0 riser cable and see how it performs.

I can pickup an RM850x for around £80 which was why I was tempted to just replace the Thor. But in theory it should be a better power supply than something like the RM850x so I want to be assured it's actually broke, and then if it is, if ASUS will RMA it.

An HX1000 is around £150.


----------



## Audioboxer

Anyone know if a 15CM riser cable is enough for a Lian Li O11 XL? Seems the Phanteks I have just now is 22cm but it has to be bent a few times due to its length.



> I got the 20cm and it was longer than needed and bending caused it to break 15cm is perfect for an 011xl
> By Thomas DePaolo on June 19, 2021


Found this on Amazon so I think it _should_ be long enough.

Also I'm having a chuckle at reviews saying a riser cable helped fix WHEA issues  Who would have thought PCIe 4.0 graphics cards running on PCIe 3.0 riser cables would lead to our beloved WHEA.

Up next, my riser cable got me running flat 13 at 3800, with no maxmem!


----------



## ManniX-ITA

ManniX-ITA said:


> You can check with ABE if it can read the rom file:


Well ABE is only for Ampere but I remember there's something else for the previous cards 



Audioboxer said:


> I can pickup an RM850x for around £80 which was why I was tempted to just replace the Thor. But in theory it should be a better power supply than something like the RM850x so I want to be assured it's actually broke, and then if it is, if ASUS will RMA it.


In my opinion a spare PSU is always good to keep around... it's a good price.


----------



## mongoled

ManniX-ITA said:


> I'm not hitting on Seasonic without reason
> Always loved the brand and was in my top 3 for a new PSU.
> But it's very noticeable that lately many, too many, had issues.
> It could be a bad batch of components but also not.
> Considering the astronomical prices the PSUs have now and the potential damages, it's something that needs caution.


Everything is amplified, people love to have something to complain about, i see this more and more as I get older.

No doubt there has been issues, but nothing more than expected.

Now if we have a recall, then that would be the time to take this more seriously.

Most important thing is the warranty and how the company act and from what I have seem Seasonic is one of the best with regards to standing behind there products.

Your opinion is of course respected, just I dont agree



@Audioboxer
Looking at the lengths of riser cables im in the same position, im thinking 15cm is going to be OK for a Corsair Obsidian 750d ...


----------



## byDenoso

Anyone noticed a increase in bandwidth increasing cLDO_Vddp?


----------



## Audioboxer

Bought a 15cm cable as I'm 100% convinced it's fine after trying to cram my hands in behind my current setup with a piece of string and run it down to the bottom of the mount lmao.

Physics wasn't my strong point in school but for those who've been advising me so far what would be the basis for the PCIe 12v slot potentially impacting the rest of the rail? Simply because it's a single rail PSU and the riser cable is causing such a droop it potentially drags the others down?

I mean I'm crossing my fingers it's just the riser cable, RMA experiences with anyone other than Corsair, maybe EVGA and one or two others seems to be nightmare fuel online. I think ASUS offer advanced RMA at least.


----------



## PJVol

Veii said:


> Still working on 1T, but it will end up as "nearly impossible on these boards"


Man, it's been a while! 
Yeah, I find it far easier to reach the target [email protected] combo with 2T, not loosing much (if at all) latency-wise.
Btw, you're the first who I saw the same GVKA kits as mine, though DR. How did you find them overall? Or compared to an older kits?
I feel they're pretty solid performers for their price, and thinking will it worth buying 2nd kit for the 32G setup.
Do you think 2x16 is easier to handle than 4x8 on our b550 boards?
Of course taking in account, that 16G kit is + 108,31 € , and 32G one - 213,28 €


----------



## ManniX-ITA

mongoled said:


> Your opinion is of course respected, just I dont agree


Thanks, yours as well 



mongoled said:


> No doubt there has been issues, but nothing more than expected.


That's the point, for me it's more than expected.
It was very very rare to see someone complaining about a Seasonic PSU.
But really rare. And they are very popular.
Also about Antec but they are much less popular.
In the last months I've seen quite some people complaining, meaning this issue of system crashes under load.
It's more than all complains I've seen in the previous 10 years...
Not like it's common for people to complain against Seasonic like other brands (eg Gigabyte).



byDenoso said:


> Anyone noticed a increase in bandwidth increasing cLDO_Vddp?


Definitely not.
Unless for some reason is needed.
Which would be more a decrease in bandwidth due to VDDP too low.


----------



## Audioboxer

Veii said:


> While it is overheating - it mostly translates to a too noisy signal, fault by overheating and similar noise cases
> 
> i'm in the middle of redoing the error list and tCKE range for Dual Rank
> They behave, different
> #13 is what i close to always get or instantly #6, 10, 12's with #2's
> 
> #6 will be renamed to "catastrophic failure"
> Be it by an unstable CPU, bad VDDG, too low primaries, too low tWTR, too low VDIMM,
> too high ClkDrvStr , too high RTT_PARK, too high procODT
> "Signal dropout catastrophic failure"
> 
> Less catastrophic is #4 but on a similar level ~ "signal dropout/crashing failure"
> - focused on the PCB reason
> 
> Also less catastrophic but still powering related are,
> #12 + #2 & #0 + #10
> 
> #13 are timing based issues
> While it is purely overheat, it's mostly timing based ~ to cause a dropout
> If you only get #13, it's that timings are too low
> Dimms still overheating, but mostly related to
> a "too noisy signal" ~ needs higher tertiaries or weaker powering
> ======
> All i can say so far
> Still working on 1T, but it will end up as "nearly impossible on these boards"
> ASUS has tPHY training issues, MSI has tPHY training issues.
> ASUS needs fast boot disabled and manually enforced limits, else the board doesn't know what to select. Anything on Auto and it doesn't train or misstrains ~ even when result-predictions are identical. FW issues
> Timing predictions appear good, but powering predictions are completely broken. Not even being funny how bad it is for DR
> 
> DR remains an architectural issue ~ PCB design issue for DIMM PCB vs AMD Engineering design.
> AddrCmd Drv & Delay are an issue
> AddrCmd lane appears to be designed with too tight tolerances. Any wiggle degrades signal integrity too strong
> X-20-X-X is fine for SR, X-24-X-X is needed ! for DR.
> X-30-X-X is also needed but falls inside too low tolerances and ruins Signal Integrity fully.
> Listing it as "nearly impossible to fix" ~ issue
> 
> 30-24-30-20 so far works for DR
> 40-24-30-20 is needed, but signal integrity suffers too much and 14-14 timings just fail.
> 120-X-24-24 works and is required on low freq 13-13-13
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But non 1DPC boards need a bump in AddrCmdDrv
> Which completely ruins signal integrity
> 
> 
> Spoiler: Something Amateur
> 
> 
> 
> 
> View attachment 2534385
> 
> 
> 
> tRRD_ bump was required ~ 1.47v. Fails on 1.46 already. Also reaches 48c and #13 unless tRRD_ got a big bump for noise stability
> tCKE is responsible for more than MCLK alignment and DR ranges are different. Soo redoing the range fully
> For 1T signal integrity is horrible. Need to figure something out + prevent misstraining. Complicated
> 
> That's all for now
> EDIT:
> Forum "Only show this user" feature , is fantastic ~ thanks a bunch
> EDIT2:
> tRDWR, tWRRD, SCL are root causes for misstraining dimms
> cLDO_VDDP & RTT are less, to nearly non.
> If tRDWR & tWRRD allign, if tCL & tCWL align ~ it will never misstrain


Just noticed this post in amongst me clogging the topic up with PCIe power woes (sorry everyone!).

Yay, Veii working on DR! Glad you discovered MSI do appear to have tPHY training issues, things behave strange for me.

40/20/24/24 seems to be OK for me with DrvStr, but I'll keep an eye on your findings.


----------



## mongoled

Audioboxer said:


> Bought a 15cm cable as I'm 100% convinced it's fine after trying to cram my hands in behind my current setup with a piece of string and run it down to the bottom of the mount lmao.
> 
> Physics wasn't my strong point in school but for those who've been advising me so far what would be the basis for the PCIe 12v slot potentially impacting the rest of the rail? Simply because it's a single rail PSU and the riser cable is causing such a droop it potentially drags the others down?
> 
> I mean I'm crossing my fingers it's just the riser cable, RMA experiences with anyone other than Corsair, maybe EVGA and one or two others seems to be nightmare fuel online. I think ASUS offer advanced RMA at least.


Just measured my case and i think 15cm is too short so going with the 20cm one



"tPHY training issues" I bet this is by design!


----------



## Audioboxer

mongoled said:


> Just measured my case and i think 15cm is too short so going with the 20cm one
> 
> 
> 
> "tPHY training issues" I bet this is by design!


Yup, when in doubt size up a little.

Just managed to produce another Kernel-Power error 41 and reboot running TimeSpy, this time with my default card BIOS but it at its max power draw which is 112%.

Something is definitely on the way out whether it's the whole power supply, the riser cable or a combination. I think I'll stop benching and testing till the new riser cable arrives. Last thing I need is another dead GPU or mobo 

Reboots and crashes due to riser cables seems to litter the online search, so I think it dropping a good bit below 12v the second its under any load is a tell tale sign the cable is crap. Might even be what killed my last GPU 

It was running with a BIOS that allowed up to 380w lmao.

You know how the saying goes folks, you pay for what you get. While the Phanteks mount is great for a Lian Li O11 XL, the PCIe 3.0 cable is clearly hit or miss, more likely miss.


----------



## mongoled

If that is the same riser card you were using when you had the previous failures I would be weary, really weary !

😀


----------



## dk_mic

@Audioboxer can you test another GPU in your system and check the 12V readings or test the PSU in another system?


----------



## Audioboxer

mongoled said:


> If that is the same riser card you were using when you had the previous failures I would be weary, really weary !
> 
> 😀


Yeah it's the same cable, lol. Back then I had no idea to check 12v rail voltages. Just looked like a GPU died and ultimately EVGA took it back, accepted RMA and replaced. I think at a bare minimum they check for water damage or shorting, basically, anything the user could have done to void warranty.

It's all good, no heavy GPU use till next week now 










A basic render test will show the PCIe slot is working at 3.0 x16 and the voltage will stay above 12v for that, but any heavy load and it's right down to 11.8v.

From doing some reading online it seems it's possible some of the copper (?) wires inside the cable might be damaged, other than it being poor quality. Could be caused from having to bend it a bit to fit it in due to length. Therefore when under a heavy load it's not capable of supplying the full power it should be.

Cue reboots, crashes and kernel power errors, much like what people get when they try to run a PCIe 4.0 graphics card with a PCIe 3.0 riser cable.



dk_mic said:


> @Audioboxer can you test another GPU in your system and check the 12V readings or test the PSU in another system?


Nah, no other GPUs to test and given the complexity of this loop even if I went begging to borrow someone's GPU right now it would be a PITA getting it going.

Could test the PSU in another system. Might do that if ASUS get annoying about doing an RMA. For the moment will just test a riser cable replacement. I do need a 4.0 cable anyway for the future.


----------



## PJVol

ManniX-ITA said:


> Always loved the brand and was in my top 3 for a new PSU.
> But it's very noticeable that lately many, too many, had issues.


Lol, all these PSU ramblings made me check what my psu is, since i've been told that Seasonic has something to do with it.
Fortunately High Power turned out to be OEM for the Ion+ series ))


----------



## Audioboxer

PJVol said:


> Lol, all these PSU ramblings made me check what my psu is, since i've been told that Seasonic has something to do with it.
> Fortunately High Power turned out to be OEM for the Ion+ series ))


Funnily enough when I was planning my new rig, my first adventure with AMD coming from a pretty dated intel setup, the power supply was picked due to reviews. Being platinum rated and with the budget left over some bling. RGB on a power supply, think how fast it will go!

Subsequently ended up in a case where it's stuck in the back so the OLED screen is useless and I might have fallen victim to a dodgy Seasonic lol. But to be fair on me all the reviews for the Thor line tend to say it's good quality _because_ they're based on Seasonic before the ASUS RGB tax.

The more you know though, power supplies are probably something quite a few people get tricked on, if not don't research enough.


----------



## mongoled

Audioboxer said:


> Funnily enough when I was planning my new rig, my first adventure with AMD coming from a pretty dated intel setup, the power supply was picked due to reviews. Being platinum rated and with the budget left over some bling. RGB on a power supply, think how fast it will go!
> 
> Subsequently ended up in a case where it's stuck in the back so the OLED screen is useless and I might have fallen victim to a dodgy Seasonic lol. But to be fair on me all the reviews for the Thor line tend to say it's good quality _because_ they're based on Seasonic before the ASUS RGB tax.
> 
> The more you know though, power supplies are probably something quite a few people get tricked on, if not don't research enough.


Bear in mind, it was built in coordination with Asus as the "buyer" so can imagine the conversation went along something like this

Asus: Very nice, very nice, but what can we remove so that we can save money and add more bling to make even more money
Seasonic: Well.....you can pretty much do what you want, but dont touch this part of the circuitry as its very important for stability and makes up for most of the cost of the PSU
Asus: But, but, the RGB is more important and we make way more money as the margins in RGB is something re...d.i cu... l.....o... u....s
Seasonic: If you do that then you are going to increase your RMAs tenfold and we highly advise against it
Asus: RGB, RGB, RGB be done with the circuitry, RGB RGB RGB, pretty ................


----------



## Audioboxer

mongoled said:


> Bear in mind, it was built in coordination with Asus as the "buyer" so can imagine the conversation went along something like this
> 
> Asus: Very nice, very nice, but what can we remove so that we can save money and add more bling to make even more money
> Seasonic: Well.....you can pretty much do what you want, but dont touch this part of the circuitry as its very important for stability and makes up for most of the cost of the PSU
> Asus: But, but, the RGB is more important and we make way more money as the margins in RGB is something re...d.i cu... l.....o... u....s
> Seasonic: If you do that then you are going to increase your RMAs tenfold and we highly advise against it
> Asus: RGB, RGB, RGB be done with the circuitry, RGB RGB RGB, pretty ................


lol. Funnily enough one review did praise it for the pricing as apparently it was barely more expensive than the Seasonic model it's based on at launch and that was with the addition of... an OLED screen 










My riser cable is still definitely a problem, here is an example of needing to go down to 50% power usage in order to get PCIe 12v to stay above 12v.


----------



## mongoled

Audioboxer said:


> lol. Funnily enough one review did praise it for the pricing as apparently it was barely more expensive than the Seasonic model it's based on at launch and that was with the addition of... an OLED screen


lol, I was joking, but looks like I was right on the money

😀


----------



## Mach3.2

mongoled said:


> "tPHY training issues" I bet this is by design!


My IMC puking all over the mobo when I threw in 2 sticks of DR B-dies is probably also by design. 🤪

Gave up on DR B-dies and and back to my SR Micron Rev. Bs. I also took a 30-40USD hit to my wallet flipping those 12 hour old sticks to someone else. 😂😭


----------



## Mach3.2

I might be in danger as well, all these PSU talk had me take a closer look at the 12V in voltage read outs.

Voltage sits right at 12V with no load, and droops down to 11.7 - 11.8V with a ~280w load on the GPU.



Spoiler: screenshot


----------



## Audioboxer

Mach3.2 said:


> I might be in danger as well, all these PSU talk had me take a closer look at the 12V in voltage read outs.
> 
> Voltage sits right at 12V with no load, and droops down to 11.7 - 11.8V with a ~280w load on the GPU.
> 
> 
> 
> Spoiler: screenshot
> 
> 
> 
> 
> View attachment 2534468


The main three I think you need to look at are PCIe +12 and then Input 1 and 2. I don't think I'd personally worry about 11.95v+, quite often in GPU-Z that actually reads as 12.0v. It's easily within the margin of error for a piece of software reading such a figure.

I would say it's more concerning if the software is reading down to the likes of 11.7~8v across those 3. For example it's quite clear there is a major issue with my riser cable, out with any concerns about the power supply.

I'm pretty confident once I replace my riser cable my crashing will stop.


----------



## Imprezzion

Mach3.2 said:


> I might be in danger as well, all these PSU talk had me take a closer look at the 12V in voltage read outs.
> 
> Voltage sits right at 12V with no load, and droops down to 11.7 - 11.8V with a ~280w load on the GPU.
> 
> 
> 
> Spoiler: screenshot
> 
> 
> 
> 
> View attachment 2534468


Meh that's still acceptable. It ain't great but not out of spec bad at least.

I also had issues with my Seasonic but that was kinda my own fault. First I tried to run a 9900KS @ 5.1 all-core + 2080 Ti (A chip) with XOC 2000w BIOS pulling over 480w in Division 2 on a Focus Plus Gold 750w. Well you can guess how that ended. It didn't break but tripped OCP almost instantly...

I replaced it with a Prime Ultra Gold 1000w as I have full cablemod custom cables and this is one of the most powerful units still compatible with those cables.

It ran totally fine after that upgrade. 480-510w on the GPU no issues. No OCP trip, no kernel 41 random shutdowns.

Now I put a 10900KF in it with a 3080 and it CAN trip it under certain circumstances with how high the short peak power of a 3080 can be.

The 10900KF is going to a good friend now and I just got this in the mail:









5900X retail new and a B550-XE WiFi.
Going to use my old DR B-Die Trident-Z Neo's (3600C16 GTZN's).

Shame my TechN block hasn't showed up yet otherwise I could've drained my loop and started building lol.


----------



## Audioboxer

Imprezzion said:


> Meh that's still acceptable. It ain't great but not out of spec bad at least.
> 
> I also had issues with my Seasonic but that was kinda my own fault. First I tried to run a 9900KS @ 5.1 all-core + 2080 Ti (A chip) with XOC 2000w BIOS pulling over 480w in Division 2 on a Focus Plus Gold 750w. Well you can guess how that ended. It didn't break but tripped OCP almost instantly...
> 
> I replaced it with a Prime Ultra Gold 1000w as I have full cablemod custom cables and this is one of the most powerful units still compatible with those cables.
> 
> It ran totally fine after that upgrade. 480-510w on the GPU no issues. No OCP trip, no kernel 41 random shutdowns.
> 
> Now I put a 10900KF in it with a 3080 and it CAN trip it under certain circumstances with how high the short peak power of a 3080 can be.
> 
> The 10900KF is going to a good friend now and I just got this in the mail:
> View attachment 2534470
> 
> 
> 5900X retail new and a B550-XE WiFi.
> Going to use my old DR B-Die Trident-Z Neo's (3600C16 GTZN's).
> 
> Shame my TechN block hasn't showed up yet otherwise I could've drained my loop and started building lol.


The good thing about Ryzen processors is even with PBO they tend to be far more energy efficient than Intel. Potentially allowing you to squeeze a bit more out of the GPU. That's if you were power supply limited.


----------



## Luggage

ManniX-ITA said:


> Well, rumors are the 4000s will peak 600W...
> I've bought the 1300W in 2013 and never regretted it.
> Sure, you'll pay a few Watts more power consumption in idle.
> But the additional headroom means reliability.
> Better everything. Always spent more than needed on PSUs and not even once regretted it.
> 
> 
> 
> Yes the RMx is very cheap compared to the others.
> Didn't read much about the HX.
> Mostly people go for the cheap RM or top notch AX.
> Read all the reviews you can and scout forums for people reporting issues.
> 
> Being the Thor Platinum a single rail... maybe it's worth to keep it?
> You can always keep a cheap RM as backup, sell it or just send it back if ASUS is replacing the Thor quickly.
> 
> 
> 
> Indeed. Cables can be the issue.
> I would replace the riser cable as well, in any case.
> Read too many horror stories about them, especially those coming with Phanteks cases.
> Have to mount the GPU vertical as well due to the water block and limited space.
> Won't take any risk.


@Audioboxer 

RM850x (2018?) original cables no riser


http://imgur.com/a/krqFFPr


----------



## tcclaviger

So, just to address some small point so some people don't get the wrong idea.

The Thor series, is literally the seasonic design with a much better heatsink, RGB, OLED, and different fan speed curve. It's not a cut down design, it's identical, it is better than almost every other option on the market for quality of power delivery.

Here are the only active links for the designs I could find which I trust. Sadly the waybackmachine didn't archive the in totality, so the Seasonic 1200 Platinum archive page only has page 1. Essentially TLDR of the reviews....all glowing and phenomenal from highly respected reviewers, whith good objective results.






Corsair AX1600i 1600W Power Supply – Page 6 – JonnyGURU.com







web.archive.org













Asus ROG Thor 1200W PSU Review – a heavily modified Seasonic! - KitGuru


The moment has come - Asus have entered the PSU market for good, through its ROG sub-brand. Today we




www.kitguru.net










Seasonic PRIME 1200 Platinum Power Supply – JonnyGURU.com







web.archive.org










Seasonic PRIME Ultra 750 Titanium Power Supply – JonnyGURU.com







web.archive.org





Ripple is miniscule.
Sag is very small.
Cool and efficient.

There will always, without exception, be a drop in 12v output under load, in most scenarios the smallest being on an ax1600i/ax1200i (860 and 1500 were somewhat problematic) that is healthy. 

Going from a Thor to a Corsair anything, besides AXi, is at best a side grade, and in most cases a downgrade.

This is why the Axi series is so cherished for extreme OC by many, it uses digital control for the output control and compensates for the sag, holding the sag to the smallest possible level. Other PSUs just hold it within a margin of sag, instead of actively compensating.

HXi/RMi are a standard output section with Corsair link monitoring, it is absolutely not the same thing, though they're also good PSUs. 

Over hundreds of builds and almost 3 decades, nothing I've ever come across holds power as precisely as the AXis do. 

Johnnyguru, before he went to Corsair, when the site was still up, explained the details better than I ever could. The short of it was "AXi are as good as it gets".

Do keep in mind, when talking about such precise values of sag, there will be some drop due to cables and at that level the difference in cable AWG, length and crimp quality start to show.

I stand firmly by the Thor 850 audiboxer is using is almost certainly healthy. There are a plethora reasons for hard shutdown on Zen 3 platform, most have nothing to do with power delivered from PSU.

The 1% drop visible on the 12v is so far within spec that any review site would hail the PSU as phenomenal, amazing, worthy of ROG branding...blablabla.

And before the "does it matter" thing starts. Yes, it does matter for the exact audience of this thread. Precise power is very important when on a razors edge of stability, less so these days than it was 10 years ago due to all the automatic error correction etc now, but it is still vital for getting the last bit of OC.

For the audience that sets xmp and goes on with life, who don't know what TM5 or HWmpnitor are, no, it doesn't matter.


----------



## ManniX-ITA

Mach3.2 said:


> Voltage sits right at 12V with no load, and droops down to 11.7 - 11.8V with a ~280w load on the GPU.


Considering the CPU PPT and the board and other peripherals, you probably peaked a little over 600W.
The max 12V is pretty low at max and goes down 200-250mV under load.
The 3080 is also very demanding.
Could be it's in line with the expectations, the PSU it's not very high end.

Don't forget that you need to have some issue like Audioboxer's system crashing when raising the GPU TDP.
It's not good, means the PSU it's not the best but going below 12V it's not necessarily an issue by itself.
If there's an issue it manifests itself with the 2000/3000 GPUs while boosting up cause they have these short massive transients.
High end PSUs, they should not drop much at half load anyway cause they should be high end...



Luggage said:


> RM850x (2018?) original cables no riser


Uhm, I'd have expected better from an RM850x.
It should not drop more than 1% under full load in theory.
Not a brilliant one probably but it's also not an high end PSU.
Max voltage is here as well not very high.

Also remember to use a GPU test with low load on the CPU like Port Royal, Heaven, Superposition.
Timespy is using quite a lot the CPU.


----------



## tcclaviger

Just occured to me, audiboxer, you may be seeing the motherboard powering the system down. Not positive on your board, but I know on Asus boards they will OCP and turn off, hard shutdown. 

Consider this:
Riser is not good, so acts as a resistor more than it should.
GPU commands a high load, drawing more current during a transient than the MB is configured to allow from PCIE slot. It does so because the V has fallen too low.
Since V is too low, A must be increased to hit power target, so GPU draws more A.
MB trips OCP and kills power because now A exceeds OCP trigger point.

Would present exactly as yours is, a GPU fault or PSU fault.

Keep in mind, my 2080ti behaved all the way down to 11.3v, anecdotal, but it's a lot more sag than you're getting.


----------



## Audioboxer

tcclaviger said:


> So, just to address some small point so some people don't get the wrong idea.
> 
> The Thor series, is literally the seasonic design with a much better heatsink, RGB, OLED, and different fan speed curve. It's not a cut down design, it's identical, it is better than almost every other option on the market for quality of power delivery.
> 
> Here are the only active links for the designs I could find which I trust. Sadly the waybackmachine didn't archive the in totality, so the Seasonic 1200 Platinum archive page only has page 1. Essentially TLDR of the reviews....all glowing and phenomenal from highly respected reviewers, whith good objective results.
> 
> 
> 
> 
> 
> 
> Corsair AX1600i 1600W Power Supply – Page 6 – JonnyGURU.com
> 
> 
> 
> 
> 
> 
> 
> web.archive.org
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Asus ROG Thor 1200W PSU Review – a heavily modified Seasonic! - KitGuru
> 
> 
> The moment has come - Asus have entered the PSU market for good, through its ROG sub-brand. Today we
> 
> 
> 
> 
> www.kitguru.net
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Seasonic PRIME 1200 Platinum Power Supply – JonnyGURU.com
> 
> 
> 
> 
> 
> 
> 
> web.archive.org
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Seasonic PRIME Ultra 750 Titanium Power Supply – JonnyGURU.com
> 
> 
> 
> 
> 
> 
> 
> web.archive.org
> 
> 
> 
> 
> 
> Ripple is miniscule.
> Sag is very small.
> Cool and efficient.
> 
> There will always, without exception, be a drop in 12v output under load, in most scenarios the smallest being on an ax1600i/ax1200i (860 and 1500 were somewhat problematic) that is healthy.
> 
> Going from a Thor to a Corsair anything, besides AXi, is at best a side grade, and in most cases a downgrade.
> 
> This is why the Axi series is so cherished for extreme OC by many, it uses digital control for the output control and compensates for the sag, holding the sag to the smallest possible level. Other PSUs just hold it within a margin of sag, instead of actively compensating.
> 
> HXi/RMi are a standard output section with Corsair link monitoring, it is absolutely not the same thing, though they're also good PSUs.
> 
> Over hundreds of builds and almost 3 decades, nothing I've ever come across holds power as precisely as the AXis do.
> 
> Johnnyguru, before he went to Corsair, when the site was still up, explained the details better than I ever could. The short of it was "AXi are as good as it gets".
> 
> Do keep in mind, when talking about such precise values of sag, there will be some drop due to cables and at that level the difference in cable AWG, length and crimp quality start to show.
> 
> I stand firmly by the Thor 850 audiboxer is using is almost certainly healthy. There are a plethora reasons for hard shutdown on Zen 3 platform, most have nothing to do with power delivered from PSU.
> 
> The 1% drop visible on the 12v is so far within spec that any review site would hail the PSU as phenomenal, amazing, worthy of ROG branding...blablabla.
> 
> And before the "does it matter" thing starts. Yes, it does matter for the exact audience of this thread. Precise power is very important when on a razors edge of stability, less so these days than it was 10 years ago due to all the automatic error correction etc now, but it is still vital for getting the last bit of OC.
> 
> For the audience that sets xmp and goes on with life, who don't know what TM5 or HWmpnitor are, no, it doesn't matter.


I've gathered this much the more reading I do. Before I bought this PSU as little as I knew about some of the innards until now I didn't just blindly buy it. I did read reviews. I won't lie my original build planned on being a case where the power wattage would be readable, but one thing led to another and now I have a Lian Li where you can't event see the power supply lol.

Given some of the crashes I get under load and when pumping up the power I do think I have an issue with my riser cable. It's cheap quality and I have a LinkUp 4.0 cable on the way that should be better even using 3.0 until I get a 3080.

Windows 11 has been awful and I don't know what Nvidia have been doing recently with the 496.xx drivers, so I know there is a lot of other issues on top that could be contributing. But I think it's just a safe bet my riser cable has long needed replaced and I would put a bet on it now once I've changed it over I don't have kernel power reboots.

Whether or not I get a better OC, I doubt it, but you never know, I'll slap a 380w BIOS on the card and we'll see!



tcclaviger said:


> Just occured to me, audiboxer, you may be seeing the motherboard powering the system down. Not positive on your board, but I know on Asus boards they will OCP and turn off, hard shutdown.
> 
> Consider this:
> Riser is not good, so acts as a resistor more than it should.
> GPU commands a high load, drawing more current during a transient than the MB is configured to allow from PCIE slot. It does so because the V has fallen too low.
> Since V is too low, A must be increased to hit power target, so GPU draws more A.
> MB trips OCP and kills power because now A exceeds OCP trigger point.
> 
> Would present exactly as yours is, a GPU fault or PSU fault.


The MSI board does a complete shutdown when OCP is tripped. Reboots like what I'm seeing are far more in line with faulty riser cables or what happens if you run a 4.0 GPU on a 3.0 cable.

I've been able to trip a reboot on a fairly low overall power draw during bench tests or stability tests that don't push the CPU as hard as actual gaming.

Just putting the card power % higher and causing the 12v PCIe to drop to like 11.8v. Dunno if you seen earlier if I reduce the card to 50% power usage it managed to keep the 12v PCIe above 12v 🤣

Run your card at 50% power for maximum stability! The tip all OCers hate!


----------



## KedarWolf

Imprezzion said:


> Meh that's still acceptable. It ain't great but not out of spec bad at least.
> 
> I also had issues with my Seasonic but that was kinda my own fault. First I tried to run a 9900KS @ 5.1 all-core + 2080 Ti (A chip) with XOC 2000w BIOS pulling over 480w in Division 2 on a Focus Plus Gold 750w. Well you can guess how that ended. It didn't break but tripped OCP almost instantly...
> 
> I replaced it with a Prime Ultra Gold 1000w as I have full cablemod custom cables and this is one of the most powerful units still compatible with those cables.
> 
> It ran totally fine after that upgrade. 480-510w on the GPU no issues. No OCP trip, no kernel 41 random shutdowns.
> 
> Now I put a 10900KF in it with a 3080 and it CAN trip it under certain circumstances with how high the short peak power of a 3080 can be.
> 
> The 10900KF is going to a good friend now and I just got this in the mail:
> View attachment 2534470
> 
> 
> 5900X retail new and a B550-XE WiFi.
> Going to use my old DR B-Die Trident-Z Neo's (3600C16 GTZN's).
> 
> Shame my TechN block hasn't showed up yet otherwise I could've drained my loop and started building lol.


I was using CableMod Pro Cables, my 12v GPU rails and CPU rail would drop below 11.6v while running Port Royal on my AX1600i.

I popped in the stock cables that came with the power supply, now my 12v rails never drop below 12.05v. Never again, CableMod.


----------



## Audioboxer

KedarWolf said:


> I was using CableMod Pro Cables, my 12v GPU rails and CPU rail would drop below 11.6v while running Port Royal on my AX1600i.
> 
> I popped in the stock cables that came with the power supply, now my 12v rails never drop below 12.05v. Never again, CableMod.


That's the biggest win out of me taking over this topic with PSU spam for a few days. Finding this out! You might even get some better performance now. Pretty shocking custom mod cables do this poorly compared to OEM cables.

Speaking of doing poorly, it was brought to my attention the Phanteks riser cable has been known to fail testing https://hardwarecanucks.com/video-cards/theres-a-problem-with-riser-cables/


----------



## Luggage

ManniX-ITA said:


> Considering the CPU PPT and the board and other peripherals, you probably peaked a little over 600W.
> The max 12V is pretty low at max and goes down 200-250mV under load.
> The 3080 is also very demanding.
> Could be it's in line with the expectations, the PSU it's not very high end.
> 
> Don't forget that you need to have some issue like Audioboxer's system crashing when raising the GPU TDP.
> It's not good, means the PSU it's not the best but going below 12V it's not necessarily an issue by itself.
> If there's an issue it manifests itself with the 2000/3000 GPUs while boosting up cause they have these short massive transients.
> High end PSUs, they should not drop much at half load anyway cause they should be high end...
> 
> 
> 
> Uhm, I'd have expected better from an RM850x.
> It should not drop more than 1% under full load in theory.
> Not a brilliant one probably but it's also not an high end PSU.
> Max voltage is here as well not very high.
> 
> Also remember to use a GPU test with low load on the CPU like Port Royal, Heaven, Superposition.
> Timespy is using quite a lot the CPU.


That was PR 
As for full system load this is from a month back, didn’t have the rail voltages unhidden though. Pretty stable unless I fiddle with CO.



http://imgur.com/tCqREzX


(no a test usually run, was proving a point about loop temps for storm-chaser…)


----------



## ManniX-ITA

Luggage said:


> As for full system load this is from a month back, didn’t have the rail voltages unhidden though. Pretty stable unless I fiddle with CO.


Not a brilliant result for an RM850x but if it's not crashing with such load there's really nothing to worry about


----------



## Veii

KedarWolf said:


> I was using CableMod Pro Cables, my 12v GPU rails and CPU rail would drop below 11.6v while running Port Royal on my AX1600i.
> 
> I popped in the stock cables that came with the power supply, now my 12v rails never drop below 12.05v. Never again, CableMod.


Quite honestly
I have/had the same issue with the current build
But mostly thanks to 3 things
~ Swapped the thick PSU cable by accident while benching & moving
~ they where loose although in, when pressed strongly
(always put a come over the header, on one side the shinyness looks better, on the other it helps against too strong bents & lose contact that way)

That was the 5th so far sub par experience with a bequiet PSU , while the first 3 where by blown caps (although my fault, still questionable OCP by rail fault)
@Audioboxer yes that Thor unit is a focus plat platinum ~ with swapped heatsinks by ASUS , a different quiet fan and seem to be slight input filtering adjustment ~ with a weakness on the 3.3v rail
I am too funnily, in the looks for a 1000-1200W PSU for the next 6900XT build

The Thor was an option, it's generally a solid unit, but the better ones i want ~ are all out of stock and non sellable anymore
This includes super flower leadex plat/titanium units 
ROG just released (it should be out but not everywhere yet) the THOR2
It looks to be a superflower unit, but it's not clear. Could be another FSP design (while they do have great units, but only keep them for themself)

Corsair's AXi is surely fantastric, but the price is a bit high. It's higher priced for a reason, yet still a bit too high (like 100 too much) as there is a lack of rivalism
I'd suggest to wait for the Thor2.
EVGA released a P+ and and P6, but both are not superflower or seasonic units. The old P2 was great, tho the new successor to it is still not out
Silverstone Strider Titanium/Plat, got a Rev.02 , but it's subpaar compared to the rivals. Yet for the price it's fine.
Subpaar here still meaning it's very great, but still worse than their rivals
Yes, wait for the Thor2 or _"focus" _ on the higher tier Seasonic lineup. Don't _focus_ on the _focus _lineup 🤭 , at least not if you want to push it (40ish A per rail) or use 3rd party cables
They have Ultra platinum and Ultra titanium lineups, also Prime Ultra ~ which indeed are better although look pretty identical and are priced far higher
While Super Flower, doesn't appear to make units anymore (i miss them) ~ they still continue to supply other Vendors with their design


PJVol said:


> Man, it's been a while!


Still here lurking on weekly bases, just too busy with unfinished projects and torture by DR


PJVol said:


> Btw, you're the first who I saw the same GVKA kits as mine, though DR. How did you find them overall? Or compared to an older kits?


The problem is,
I can not write anything about them. Nothing positive or negative ~ as the issue is "around them"

Somebody didn't follow their spec and made their own design
Either it's ASUS (expected) or G.Skill indeed does follow Intel's spec and not AMDs for "non AMD designed" dimms
Something around this, MSI and ASUS AGESA + DR seems to be completely broken.
Soo i can not judge the dimms so far.

I needed around 1.56v for 3267 13-13-13 (RTT_PARK /6)
And minimum 1.47v for just barely holding 3600 14-14-14 with VTTMEM of 0.75 (1.5v) ~ vs (RTT_PARK /1)
The 1.56v set was colder, the 1.47v "failsafe" with "old known" powering , gets far to warm ~ 47-48c , which is questionable for only X1 mode

It's slightly unfair to judge them based on quality
When everything around them is more than problematic
Tho i have to say, the booted my 15-15-15 4200MT/s @ 1.68v set instantly , without an issue
Just reality is, GDM required. As even 2T causes issues right now.
This combined with PSU instability issues ~ i can't judge them now, it's unfair

I remember @domdtxdissar and @Audioboxer ? had both good / similar? DR sets
The 4000 C16-16
I think they are good, but so far it's been a struggle and a half with this build.
Redid slightly house-installation powering, changed couple of things as this StraightPower 11 Plat, PSU was completely unstable on 2 CPUs and 3 RAM kits
Now all is fine, but it's too early to judge them.
What i can judge, is that something with AddrCmd line is messed up. Well not only, but a signal integrity part is completely messed up
Me holding 48c on them with an 2000RPM ram-cooler (3200max but then it's too whiny) ~ doesn't help the whole cause








That is something inacceptable i can judge
But as for the rest ~ Neither G.Skill nor the Dimms deserve for now such harsh judgement 
I (client) could have gotten just bad luck dimms that require too much voltage for what i'd say "mediocre at best" settings
We'll see, let me comment on it with a more mature CPU when it arrives in 2-3 days. Batch 2143


Audioboxer said:


> Yay, Veii working on DR! Glad you discovered MSI do appear to have tPHY training issues, things behave strange for me.
> 
> 
> mongoled said:
> 
> 
> 
> "tPHY training issues" I bet this is by design!
Click to expand...

It is by design. A questionable design
So far MSI seems to have this resolved easier , but it remains questionable

They completely fail when you use DR, any voltage prediction is a mess
Any powering prediction is a mess
Not even downclocked XMP runs at 2T ~ and GDM "feature" is not enforcable as QVL compatible (shouldn't be)
Something is completely broken or both vendor's did follow spec, just asrock figured out how to get it to work

I still look into it, soo i'm gone for quite some time & still am 
We'll see, searching for a method to fix this. But when even 2T doesn't work out well on quite high timings or 3267 & 4000 show the same type of issue, then something is messed up
Unsure why signal integrity is soo bad ~ but that's all i can share for now.
Everything should be better with the brand new cpu batch 

EDIT:
The Prediction happens automatically
Why it misstrains, is either users powering fault, bios powering fault or simply questionable spec followed design
The unfortunate part is , that we can not do much against it and have to work around this prediction
We can not enforce anything related to tPHY.


----------



## Audioboxer

Veii said:


> Quite honestly
> I have/had the same issue with the current build
> But mostly thanks to 3 things
> ~ Swapped the thick PSU cable by accident while benching & moving
> ~ they where loose although in, when pressed strongly
> (always put a come over the header, on one side the shinyness looks better, on the other it helps against too strong bents & lose contact that way)
> 
> That was the 5th so far sub par experience with a bequiet PSU , while the first 3 where by blown caps (although my fault, still questionable OCP by rail fault)
> @Audioboxer yes that Thor unit is a focus plat platinum ~ with swapped heatsinks by ASUS , a different quiet fan and seem to be slight input filtering adjustment ~ with a weakness on the 3.3v rail
> I am too funnily, in the looks for a 1000-1200W PSU for the next 6900XT build
> 
> The Thor was an option, it's generally a solid unit, but the better ones i want ~ are all out of stock and non sellable anymore
> This includes super flower leadex plat/titanium units
> ROG just released (it should be out but not everywhere yet) the THOR2
> It looks to be a superflower unit, but it's not clear. Could be another FSP design (while they do have great units, but only keep them for themself)
> 
> Corsair's AXi is surely fantastric, but the price is a bit high. It's higher priced for a reason, yet still a bit too high (like 100 too much) as there is a lack of rivalism
> I'd suggest to wait for the Thor2.
> EVGA released a P+ and and P6, but both are not superflower or seasonic units. The old P2 was great, tho the new successor to it is still not out
> Silverstone Strider Titanium/Plat, got a Rev.02 , but it's subpaar compared to the rivals. Yet for the price it's fine.
> Subpaar here still meaning it's very great, but still worse than their rivals
> Yes, wait for the Thor2 or _"focus" _ on the higher tier Seasonic lineup. Don't _focus_ on the _focus _lineup 🤭 , at least not if you want to push it (40ish A per rail) or use 3rd party cables
> They have Ultra platinum and Ultra titanium lineups, also Prime Ultra ~ which indeed are better although look pretty identical and are priced far higher
> While Super Flower, doesn't appear to make units anymore (i miss them) ~ they still continue to supply other Vendors with their design
> 
> Still here lurking on weekly bases, just too busy with unfinished projects and torture by DR
> 
> The problem is,
> I can not write anything about them. Nothing positive or negative ~ as the issue is "around them"
> 
> Somebody didn't follow their spec and made their own design
> Either it's ASUS (expected) or G.Skill indeed does follow Intel's spec and not AMDs for "non AMD designed" dimms
> Something around this, MSI and ASUS AGESA + DR seems to be completely broken.
> Soo i can not judge the dimms so far.
> 
> I needed around 1.56v for 3267 13-13-13 (RTT_PARK /6)
> And minimum 1.47v for just barely holding 3600 14-14-14 with VTTMEM of 0.75 (1.5v) ~ vs (RTT_PARK /1)
> The 1.56v set was colder, the 1.47v "failsafe" with "old known" powering , gets far to warm ~ 47-48c , which is questionable for only X1 mode
> 
> It's slightly unfair to judge them based on quality
> When everything around them is more than problematic
> Tho i have to say, the booted my 15-15-15 4200MT/s @ 1.68v set instantly , without an issue
> Just reality is, GDM required. As even 2T causes issues right now.
> This combined with PSU instability issues ~ i can't judge them now, it's unfair
> 
> I remember @domdtxdissar and @Audioboxer ? had both good / similar? DR sets
> The 4000 C16-16
> I think they are good, but so far it's been a struggle and a half with this build.
> Redid slightly house-installation powering, changed couple of things as this StraightPower 11 Plat, PSU was completely unstable on 2 CPUs and 3 RAM kits
> Now all is fine, but it's too early to judge them.
> What i can judge, is that something with AddrCmd line is messed up. Well not only, but a signal integrity part is completely messed up
> Me holding 48c on them with an 2000RPM ram-cooler (3200max but then it's too whiny) ~ doesn't help the whole cause
> 
> 
> 
> 
> 
> 
> 
> 
> That is something inacceptable i can judge
> But as for the rest ~ Neither G.Skill nor the Dimms deserve for now such harsh judgement
> I (client) could have gotten just bad luck dimms that require too much voltage for what i'd say "mediocre at best" settings
> We'll see, let me comment on it with a more mature CPU when it arrives in 2-3 days. Batch 2143
> 
> It is by design. A questionable design
> So far MSI seems to have this resolved easier , but it remains questionable
> 
> They completely fail when you use DR, any voltage prediction is a mess
> Any powering prediction is a mess
> Not even downclocked XMP runs at 2T ~ and GDM "feature" is not enforcable as QVL compatible (shouldn't be)
> Something is completely broken or both vendor's did follow spec, just asrock figured out how to get it to work
> 
> I still look into it, soo i'm gone for quite some time & still am
> We'll see, searching for a method to fix this. But when even 2T doesn't work out well on quite high timings or 3267 & 4000 show the same type of issue, then something is messed up
> Unsure why signal integrity is soo bad ~ but that's all i can share for now.
> Everything should be better with the brand new cpu batch
> 
> EDIT:
> The Prediction happens automatically
> Why it misstrains, is either users powering fault, bios powering fault or simply questionable spec followed design





> And minimum 1.47v for just barely holding 3600 14-14-14 with VTTMEM of 0.75 (1.5v) ~ vs (RTT_PARK /1)


Yeah, that is rough










This 4000C14 set was doing 3800C14 at 1.44v.

Is it the 4000C16 set you are playing with? I've read a few complaints about it really underperforming.


----------



## Veii

Audioboxer said:


> Yeah, that is rough
> 
> View attachment 2534493
> 
> 
> This 4000C14 set was doing 3800C14 at 1.44v.
> 
> Is it the 4000C16 set you are playing with? I've read a few complaints about it really underperforming.


Yes








If you compare
I can't go more failsafe than that really (still causes #13 issue)
But neither tRRD nor tWTR does wiggle down
tWTR_L 10 alone was a pain to post, and is yet not stable at 3677
Still a lot of work to do ~ but i think just powering is messed up.
This combined with too high required voltage , and too warm dimms ~ snowballing issue

We'll see 
Probably also make a B2 thread, if this CPU with Zen3D silicon ends up behaving too different than early Vermeer
I'll only have it for 3-4 days. Soo i'm inactive on OCN and HWLUXX for now

EDIT:
@PJVol


Spoiler: Amusing





















This was 2136, most bugged CPU i've seen so far, yet good minimum voltage overclocker
Thought you'll find this funny
It went instantly back, but just so you know

Also found that this ASUS board too, does overvolt the CPU slightly too much (even with any cheatery disabled)
I really wish for finally a good experience with ASUS boards, but they keep coming back as issues stacked with other issues ~ compared to my little asrock ITX


----------



## ManniX-ITA

Veii said:


> While Super Flower, doesn't appear to make units anymore (i miss them) ~ they still continue to supply other Vendors with their design


Well I was just checking the news and surprise... 









Super Flower releases LEADEX VI PLATINUM PRO Platinum power supply


Power supply device with 80 PLUS PLATINUM certification that utilizes a "super connection" that is shared by the EPS, PCI-Express, and SATA modular connector systems. There are two variant...




www.guru3d.com


----------



## PJVol

Audioboxer said:


> I've read a few complaints about it really underperforming.


Where?


----------



## Veii

ManniX-ITA said:


> Well I was just checking the news and surprise...


1000W should work for a 5950X (300W) + 6900XT (550W), as long as it isn' t a multi-rail design
Just whenTM
Now that they left EU , getting anythign from them is even more of a struggle, than it was before :/
So far i wait for the Thor 2 , tho i think it will have a 399-400$ pricetag for the 1200W model 
Can't justify over 350€ for a PSU ~ for his build


----------



## ManniX-ITA

Veii said:


> Can't justify over 350 for a PSU ~ for his build


Pity... what do you think about the Antec Signature line? Know them?



https://www.computeruniverse.net/de/p/90804345



It's decently priced for a Titanium.


----------



## tcclaviger

Yeah PSU prices have gone bonkers. My ax1200i was 329 back in '15, and that was already a lot. At current pricing I'd never buy one. 

How I do PSU math:
(CPU max OC draw * 1.25)+ (GPU max OC draw * 1.5) + 200 watts = min acceptable output of PSU.

For a 5950 and 525 wattgpu this is around 1370, but the good 1200s can cover that just fine.
Remember AMD GPUs are well known to draw FAR over their TDP during transients, then again it would require both CPU and GPU to be max transient together + all 200 watt accessory buffer used to hit that 1370 (very unlikely).

Glad SLI/CF is essentially obsolete, the power draw at this point would be ungodly.

Regarding the tphyrdl going 26-28 or 28-30 mismatch, I haven't ever seen anything discussing what that value is or the impacts it has.

Would love if someone could post or link something covering it. Curious as to what influences it as I get 26 on all 4 DIMMS and don't want to change something that would impact that if it matters.

Overnight TM5 threw 2 error 15s. No idea what error 15 represents, very few Google results I could find regarding 15. Bit head scratchy, bumped a variety of voltages a bit and testing again at least stringent timings to establish error free 3866 baseline. 2 errors over 12 hours isn't that bad, but, still 2 errors.

Now at:
1.55 vdimm set (can't see get, but on C7H droop was about .3v, not sure on this board)
1.15 soc set (1.138get)
1.0 cldo VDDP
.975 vddg ccd
1.03 vddg iod
40ohm ProcODT
Tcke 10
7-3-1
DvrStr 0-0-0-0 (manual set)
Terminations 40-20-20-24
With 16s flat and 336 trfc

Hopefully this works so I can start from a known good point, it's pretty loose for a ~ 7.5ns cycle time.

@Veii at around what voltage does dimm damage become a significant risk using my resistances? I saw you mentioned having it occur in the past.


----------



## MrHoof

And then there is me running 1T no trouble 🤣 I am still wondering what exactly makes the diffrence. I think its motherboard or CPU but not the RAM else i got extremly lucky with my DR kit.
SR was running at 1T even at 20-20-20-24 cad BUS.


----------



## Veii

ManniX-ITA said:


> Pity... what do you think about the Antec Signature line? Know them?


I saw them, but i didn't find much about it either
It was an option. Same as FPS Hydro lineup appears to be solid
Both not on Seasonic Ultra Prime quality , but the really good rated old units are not buyable at all, anymore



tcclaviger said:


> @Veii at around what voltage does dimm damage become a significant risk using my resistances? I saw you mentioned having it occur in the past.


Up to nm node
IC damage the voltage is far higher in the 1.7 region / well there is no "damage" as ICs do not degrade, they die or function
PCB damage , the voltage is low

But voltage is not a key thing, amperage is
i think before DIMM PCB damage starts to become a question (which is the trace oxidation topic and cap's damage) such requires them to run at very bad exterior usages and for long time
Benching with high voltage , i saw leaves burn marks on the PCB - which to some extend you can clean up
But that's the only type of "time based degradation" that can happen , benching with 1.9v and higher. Well with 1.7+ honestly, later ICs can die too or rather anything around them first

Common usage is 1.51+ for A0 PCB
1.48v for 19nm & 18nm node
1.46 for 17nm node

Tho such are failure & failure-stability points and not "death" failures
Real "damage" you speak about was near 1.72v for Rev E A2 , near 1.68 for A0 PCB (which it depends again)
In such ranges, you can actually have oxidation and current burn issues on the PCB
But 1.65 is perfectly daily-able ,just don't run them at the same RTTs that you run your 1.42-1.5v' on. Weaken them , then everything is fine

There is no clear answer, as i lack what G.Skill engineers have researched
I also lack what Micron engineers have researched for their PCB design ~ to differentiate both custom designs
So far i can only put both as "equal" which they are not fully ~ soo the range likely is slightly higher in voltage, up to PCB design


> But 1.65 is perfectly daily-able ,just don't run them at the same RTTs that you run your 1.42-1.5v' on. Weaken them , then everything is fine


That's really all you have to worry
If you want to exceed 1.51, get creative with RTTs ~ as PCBs will be the stability failure point
Later you don't have to worry about heat, when RTTs are fine
As heat = noise = low signal integrity
RTTs will be different by heat , as signal integrity will be different by users-heat creation.
So also it wiill be slightly different (+/- 1) between board designs, between vendors mostly

When RTTs are fine, you don't have to worry about heat, as else RTTs wouldn't be fine in the first place
Just change the old shared ones by 1usmus up , as they are absolutely not fine on higher than 1.51v , 1.52 you start to have crashes, 1.56 you can even kill weak PCBs
(if it even allows you to post and run it for a longer time) ~ mostly it won't allow you to post stupid settings, soo there can not be any damage or burn marks. As time is critical for oxidation


----------



## Veii

MrHoof said:


> I am still wondering what exactly makes the diffrence. I think it motherboard or CPU


28ohm procODT is the difference + ITX board
Signal integrity is much cleaner ~ soo you have no issues 

I have to rely on 40ohm not even being close to 3800
That ruins a lot  likely needs a different approach 

how much vdimm ?


----------



## tcclaviger

Hard to argue with the I series boards for ram OC vs ATX, that's quite good, wish any of my boards could post there, let alone at those voltages.


----------



## Audioboxer

PJVol said:


> Where?


In this topic and site about struggling to run 3800 14-14-14-14. I'm sure someone was even struggling with flat 15.

Seemed to be quite voltage sensitive as well leading me to suggest at the time maybe thinking a 4000 flat 16 bin will be best cause it's binned at 1.4v might not tell the whole story.

Silicon lottery and all that jazz but if you search this topic you'll find a few comments on the 4000C16 bin.


----------



## tcclaviger

Veii said:


> 28ohm procODT is the difference + ITX board
> Signal integrity is much cleaner ~ soo you have no issues
> 
> I have to rely on 40ohm not even being close to 3800
> That ruins a lot  likely needs a different approach
> 
> how much vdimm ?


Thanks. Since I keep em under 23c at all times your answer gives me some confidence in 1.6 daily.

1.56 hasen't been an issue this far on my b-die, if they die c'est la vie, I have a full extra 48gb set lol.


----------



## MrHoof

Veii said:


> 28ohm procODT is the difference + ITX board
> Signal integrity is much cleaner ~ soo you have no issues
> 
> I have to rely on 40ohm not even being close to 3800
> That ruins a lot  likely needs a different approach
> 
> how much vdimm ?


1.55v not as lucky as audioboxers kit.


----------



## Veii

MrHoof said:


> 1.55v not as lucky as audioboxers kit.


Will try to copycat eeh "replicate", i mean 🤭
Ty~


----------



## MrHoof

For cad bus 40-20-24-24 or 40-20-24-30 works for me but i decided to go with 40-20-24-30 to play it safe since it mostly works with 1T+56 aswell.


----------



## Audioboxer

MrHoof said:


> 1.55v not as lucky as audioboxers kit.


I think there are 3 of us recently in this topic all with similar results on this bin. Seems a good chance the bin is quite normalised if we're talking running it at 3800.

Would be good to see how it can be pushed higher but with WHEA issues sadly I can't help with that. Well, I can memory test at 2000 FCLK but the CPU is horrendously unstable. 

The furthest I got was 4000 14-14-14-14 looked like it was a go.


----------



## MrHoof

Ye i decided to cheap out a bit with the 3600-14-15 kit but i doubt i would get much tighter by spending more at 3800mhz. I am fine with the 1.55v since most of my workload dont push much heat and my GPU is a 6600XT wich does not push any heat in the sytem at all.<

edit: seasonic focus 750w gold sfx btw


----------



## PJVol

Audioboxer said:


> In this topic and site about struggling to run 3800 14-14-14-14. I'm sure someone was even struggling with flat 15.


The only DR kit I've seen here is the one Veii showed, the other (mine) is 2x8 SR. Did you mean the DR that was struggling with flat 15?


----------



## tcclaviger

Audioboxer said:


> I think there are 3 of us recently in this topic all with similar results on this bin. Seems a good chance the bin is quite normalised if we're talking running it at 3800.
> 
> Would be good to see how it can be pushed higher but with WHEA issues sadly I can't help with that. Well, I can memory test at 2000 FCLK but the CPU is horrendously unstable.
> 
> The furthest I got was 4000 14-14-14-14 looked like it was a go.


Which kit part number? The 4000C16-GVKA or a different?


----------



## Luggage

I really should go back and try to get T1 running on my gvka 3600-14-14-14 but I sort of gave up after realising it’s likely binned at trcdrd >3800/15 and my imc refusing to boot over 1900…


----------



## Audioboxer

PJVol said:


> The only DR kit I've seen here is the one Veii showed, the other (mine) is 2x8 SR. Did you mean the DR that was struggling with flat 15?


Yeah DR, Veii is playing around with a DR set at the moment. 



tcclaviger said:


> Which kit part number? The 4000C16-GVKA or a different?


Nah it's the 4000C14 bin. Full part number is on last page in my screenshot. 4000 14-15-15-15 1.55v. There is a SR and DR variant.


----------



## umea

Every single person I've seen that has purchased the top bin DR kit (4000 14-15-15-35 1.55v) has managed to hit AT LEAST 3800 flat 14s with relative ease. tRCDRD 14 @ 3800 with dual rank seems to be one of the most difficult things to manage, especially on 2CCD CPUs.

I believe that Veii was testing the same bin that I have (4266 17-18-18-38), but ran into some problems with... something. @Veii Did you get a different DR kit?


----------



## Audioboxer

umea said:


> Every single person I've seen that has purchased the top bin DR kit (4000 14-15-15-35 1.55v) has managed to hit AT LEAST 3800 flat 14s with relative ease. tRCDRD 14 @ 3800 with dual rank seems to be one of the most difficult things to manage, especially on 2CCD CPUs.
> 
> I believe that Veii was testing the same bin that I have (4266 17-18-18-38), but ran into some problems with... something. @Veii Did you get a different DR kit?


Yes, he's working with the 4000C16 DR bin. I've seen a few people struggle with it but it has long been hyped up due to the 1.4v binning, so I dare say some people have got good sticks with it.

I think with SR you're almost always going to hit your goals, it's just DR that seems to be quite the challenge if your goal is 3800 flat 14. By challenge I mean luck, unless you stump up for the 4000C14 bin.


----------



## tcclaviger

Yeah the 4000-16 GVKA is what I'm working with, 3800+ at C14 wasn't an issue with it.

I suspect the few remaining errors I'm getting with the 48gb configuration are IMC not sticks, doing some desynced uclk/fclk/mclk tests now to verify the sticks are not to blame, pretty sure it's the 6 ranks + speed stressing it beyond breaking point.


----------



## umea

Audioboxer said:


> Yes, he's working with the 4000C16 DR bin. I've seen a few people struggle with it but it has long been hyped up due to the 1.4v binning, so I dare say some people have got good sticks with it.
> 
> I think with SR you're almost always going to hit your goals, it's just DR that seems to be quite the challenge if your goal is 3800 flat 14. By challenge I mean luck, unless you stump up for the 4000C14 bin.


Achieving flat 14s at 3800 on SR was laughably easy for me, it took about 6 hours of tweaking and testing to get a profile stable. The only thing you'll find difficulty with is just pushing down to try to compete with 1ccd latency levels on a 2ccd cpu. i.e. trying to achieve 13/12 flat at 3800 on a 5900x/5950x. Of course, I think that once you go above 3800, it becomes a lot more difficult. i.e. stabilizing 4200C15 is much harder than stabilizing 3800C13. Regardless, I'm going to work on tightening this and tweaking it as much as I can.



Spoiler: 3800 SR flat 14


----------



## umea

MrHoof said:


> And then there is me running 1T no trouble 🤣 I am still wondering what exactly makes the diffrence. I think its motherboard or CPU but not the RAM else i got extremly lucky with my DR kit.
> SR was running at 1T even at 20-20-20-24 cad BUS.
> View attachment 2534497
> View attachment 2534498
> View attachment 2534499


I think you're the third person I've seen to stabilize DR 3800 flat 14 pure 1T. Good job!


----------



## Imprezzion

umea said:


> I think you're the third person I've seen to stabilize DR 3800 flat 14 pure 1T. Good job!


I will give it my best shot with my horrible bin 3600C16 1.35v DR lol. Block should be here late tomorrow. Maybe I'll have it up and running by Sunday if I have time.


----------



## lunatik

umea said:


> I think you're the third person I've seen to stabilize DR 3800 flat 14 pure 1T. Good job!


I can't even do 3800 flat 14 2t on my DR ripjaws 4000c17.. trcd needs 15. But on the other hand i can do 4000 cl15 16.. without whea on my 5600x. Still, im wondering if it's actually completely stable for gaming. FPS is higher with my DR kit but latency felt odd sometimes in warzone (could just be my imagination)..I've been using vipers 2x8 3800 flat 14 1T just to be in the safe side. Is there a way to test latency somehow in games?


----------



## Veii

umea said:


> I believe that Veii was testing the same bin that I have (4266 17-18-18-38), but ran into some problems with... something. @Veii Did you get a different DR kit?


I get them borrowed for research & education
Or get boutique builds passed through my hands

First baby steps where on the 4266C17D-32GVKB right
I was soo unhappy/mad with them, that i packed them and never touched again ^^'
* as they where training and behaving like ECC dimms
Actually forgot they are still here  ~ _should send them back soon_

This makes me curious if they can run my 13-13's and at what voltage
Could easily swap 4000 for 4267 or mix even

I personally try to stay away from 1.45 or 1.5v XMP kits
These have barely any headroom in them for low voltage ~ and only potentially scaling after 1.68+
I packaged them away, as they had burn marks like the Viper4400's which usually where ment for me as replacement for the A0's

Sadly Vipers couldn't be cleaned, 4267's could but they behave too bizzare
Once powering on this board get's figured out & i buy some QDC Red/WD Green, then i'll head back to the 4267's and check how they behave now

15-15-15 always misstrains, but 14-15-15, tCWL 14 runs well. _Goal is still 14-14_
Well to the extend that it just loads Win11 after starting TM5 it even corrupts the BSOD screen and the bios if the board misstrains channels & tRDWR + tWRRD (key values to tame misstraining)
Soo 1T and generally the 2nd DR kit are pushed to the side when i make a bit more progress on the issue
Even 56-0-0 doesn't run , as signal integrity is like a dead mice ~ has left any attempt to be rescued 
Need to figure out what's making such big issues. Else for posting, both post a lot of stupid timings but nothing is stable

EDIT:
Have the luxury to train 2000 XMPs or even 4267 XMPs 1:1 but yet they are not even close to being stable on 2T XMP ~ stuck at 3600 so far. Testing takes 3:30h each attempt

Something else interesting,
On my sample now after this latest bios attempt
(bricked it often, the collection of issues, really are not funny anymore) xD
10 out of 10 error sources got active - yet/still WHEA 19 free at 2100:2100, or 2067:2067 with PCIe 4.0
2100:2100 afterwards works on my tiny ITX, but doesn't work on the ATX anymore

DPM Issues have to belong to reaching zero endpoint (likely), as both "fused away cores" are not fused at all.
They are active and Lowest-Pstate sleep, if they can not DF_C-State hibernate
They have no other P-States in them & without C6, they keep wasting power.
Likely something by the method of "disabling them" causes WHEA #19 ultimately
As all 16 links for me are active, tho now the 1st CCD is disabled. I don't have #19's still
Nevertheless if all sensors now are active and functioning


----------



## Veii

lunatik said:


> I've been using vipers 2x8 3800 flat 14 1T just to be in the safe side. Is there a way to test latency somehow in games?


3D Mark timespy CPU test showed positive and negative scaling with 3800 vs 4000
4200 was slower but that can mean many things including too strong eat into the powerbudget

Yes, Timespy is as close as it comes to games
probably also Unigine Superpostition custom all to extreme except resolution. No optimized resolution as such is less heavy

Bar Mode syncs CPU frame time to GPU frame time
Keep this in mind, especially for CoD titles
If your CPU is unstable , the GPU will get too - same reverse
This also counts for 3D Mark benchmarking


----------



## tcclaviger

Thanks @umea your comment reminded by that tCRDRD can be a pita and sometimes needs relaxing by 1 notch, and after that little memory, I've finally made progress! I've gotten this far, not done yet, but I've not made it this far without at least 1 error 6 coming up, which has not been even remotely possible with this config at C14 yet. Bumped SOC and raised procODT 1 to 43.6 and they seem to like the combination...

took a whopping 1.58vdimm SET to get this far








Still have much tuning to do, but this is a solid start for sure on a 48gb config at 3866 imho!


----------



## paih85

MrHoof said:


> And then there is me running 1T no trouble 🤣 I am still wondering what exactly makes the diffrence. I think its motherboard or CPU but not the RAM else i got extremly lucky with my DR kit.
> SR was running at 1T even at 20-20-20-24 cad BUS.
> View attachment 2534497
> View attachment 2534498
> View attachment 2534499


vdimm = ??


----------



## Veii

MrHoof said:


> For cad bus 40-20-24-24 or 40-20-24-30 works for me but i decided to go with 40-20-24-30 to play it safe since it mostly works with 1T+56 aswell.


I see 
Soo now this gets hilarious
I can not boot GDM at 3733+
I can not boot anything beyond 1.58v ~ PCB fails at 1.6VDIMM

1.56v with weak RTTs are unstable at the very start on 3600
If i had the time, i'd RMA them ~ this is not stable on anything , but sadly it's just the board or weak CPU of mine hating DR

Thought, eh why not just run 12-12-12 GDM at high voltage when nothing else works
But even 14-14 at such absurdly high VDIMM + GDM doesn't pass
It starts to get embarrassing~
I might settle for 4400 16-16-16 GDM, if it would allow me (believing they are not broken)

But the new B2 CPU has to do this, else idk what to do with these kits
I have high hopes and a high bar set for it ~ could be just my over sensitive CPU
Tho it likely arrives only after monday 

Oh i got procODT down to 28, but doesn't make any change
#2's #10's, #6's
Biggest downpuller is, the PCB failing already at such low peak VDIMM


----------



## tcclaviger

My Teamgroup Darks topped out at 1.565, anything over and they'd fail to post :/ Garbage PCBs, sorry to hear your running into it too on those.

Which sku b2 did you order? 

My theory is B2 is the prep step for vcache, essentially the small changes needed to accommodate it, despite them saying zen3 was designed for the vcache from the begining, that doesn't mean it was fully featured for it, e.g. unfilled vertical pathways etc.

AMD likes modular, so it's logical the B2 will be exactly the same as 3d cache, without the cache in place. No reason to use 2 different IOD, substrate, CCDs if they can get away with 1 design, unless there's a technical barrier.

If that supposition is correct, B2 will be good representation of FCLK/MCLK/UCLK capabilities of the vcache chips, even if functionally there's no other difference from the current chips as AMD claims.

EDIT: Just found the report of Shamino hitting 5150mhz, cooler and with less power draw as well as using 4100 ram. Bodes well for vcache chips.



404. That’s an error.



Original source: https://www.hd-tecnologia.com/el-am...ing-b2-tiene-menor-consumo-y-temperatura/?amp

Looking closely at the screenshot I suspect it's merely a PBO CO + Asus Force OC Mode Disabled + raised bclk single core 5150. In other words, nothing different to what could be done on B0 with a Crosshair 7, I've done the same on my chips.


----------



## ManniX-ITA

umea said:


> Every single person I've seen that has purchased the top bin DR kit (4000 14-15-15-35 1.55v) has managed to hit AT LEAST 3800 flat 14s with relative ease


Thanks for reminding me how lucky am I 
Mine doesn't work flat 14 at 3800, needs tRCDRD at 15.


----------



## tcclaviger

Thanks to all of you fine gents the goal is realized 

Seriously I wouldve settled with 32 instead since 48 was so much work to get right and some of it I would not have tried (like setting all Setups to 0 manually, Fing weird but it works).

48GB without giving up almost any performance vs 32GB.

3933 is TM5 stable, screen shots to follow. Running through various BMs to look for regression ATM.

Some settings are very strange and can not be tighter, I know, they look odd. procODT at 43.6 was a mistake, warm boot issues, 40 boots like clockwork.

tRAS - 24 causes instability
tRC - 40 causes post issues
tRRDL - 4 causes no post
tRTP - 6 boots into a bsod
tWTRL/tWTRS - 8/3, 10/3 are unstable
tWRRD - lower than 6 becomes erratic
tRFC - sadly, going down to 288 is boot loop city
1t - not going to happen until I get miiiiighty bored and start testing again lol.
1.58 SET (probably ~1.55 GET, but could be as low as 1.52 GET)

















Lol fun side effect, the machine is pulling a good bit more power in time spy now. 590 Test 1, 640watt in Test 2, 440 in CPU test.


----------



## mongoled

MrHoof said:


> And then there is me running 1T no trouble 🤣 I am still wondering what exactly makes the diffrence. I think its motherboard or CPU but not the RAM else i got extremly lucky with my DR kit.
> SR was running at 1T even at 20-20-20-24 cad BUS.
> View attachment 2534497
> View attachment 2534498
> View attachment 2534499


Because its a tiny motherboard


----------



## mongoled

tcclaviger said:


> Yeah the 4000-16 GVKA is what I'm working with, 3800+ at C14 wasn't an issue with it.
> 
> I suspect the few remaining errors I'm getting with the 48gb configuration are IMC not sticks, doing some desynced uclk/fclk/mclk tests now to verify the sticks are not to blame, pretty sure it's the 6 ranks + speed stressing it beyond breaking point.


Did you try playing with CPU NB LLC/Frequecy switching ??



umea said:


> Achieving flat 14s at 3800 on SR was laughably easy for me, it took about 6 hours of tweaking and testing to get a profile stable. The only thing you'll find difficulty with is just pushing down to try to compete with 1ccd latency levels on a 2ccd cpu. i.e. trying to achieve 13/12 flat at 3800 on a 5900x/5950x. Of course, I think that once you go above 3800, it becomes a lot more difficult. i.e. stabilizing 4200C15 is much harder than stabilizing 3800C13. Regardless, I'm going to work on tightening this and tweaking it as much as I can.
> 
> 
> 
> Spoiler: 3800 SR flat 14
> 
> 
> 
> 
> View attachment 2534522





umea said:


> I think you're the third person I've seen to stabilize DR 3800 flat 14 pure 1T. Good job!


Yes, common denominator is ITX board


----------



## Audioboxer

umea said:


> Achieving flat 14s at 3800 on SR was laughably easy for me, it took about 6 hours of tweaking and testing to get a profile stable. The only thing you'll find difficulty with is just pushing down to try to compete with 1ccd latency levels on a 2ccd cpu. i.e. trying to achieve 13/12 flat at 3800 on a 5900x/5950x. Of course, I think that once you go above 3800, it becomes a lot more difficult. i.e. stabilizing 4200C15 is much harder than stabilizing 3800C13. Regardless, I'm going to work on tightening this and tweaking it as much as I can.
> 
> 
> 
> Spoiler: 3800 SR flat 14
> 
> 
> 
> 
> View attachment 2534522


SR is almost always going to be easier than DR, heck, it's SR I've seen do flat 13 at 3800.

I need to use maxmem to achieve tRCDRD 13 



















Hey @Veii here is how you sort your DR issues, just limit Windows to 3~9GB of ram. Who needs more?


----------



## Imprezzion

Audioboxer said:


> SR is almost always going to be easier than DR, heck, it's SR I've seen do flat 13 at 3800.
> 
> I need to use maxmem to achieve tRCDRD 13
> 
> View attachment 2534603
> 
> 
> View attachment 2534604
> 
> 
> Hey @Veii here is how you sort your DR issues, just limit Windows to 3~9GB of ram. Who needs more?


Which ram test program are you using here? On Intel I always used MemTestHelper with HCI MemTest but I always see you guys use this tool which is clearly a different one lol.


----------



## Audioboxer

Imprezzion said:


> Which ram test program are you using here? On Intel I always used MemTestHelper with HCI MemTest but I always see you guys use this tool which is clearly a different one lol.


Karhu. It's not free like the others though.

I use TM5 as well, I find it's probably still the best though Karhu is a bit more friendly on the PC in so far as it doesn't make it near unusable like TM5 during use lol. It can be quite quick to pickup errors as well.

You can't go wrong using multiple tests and with TM5 using a few different profiles.


----------



## Imprezzion

Audioboxer said:


> Karhu. It's not free like the others though.
> 
> I use TM5 as well, I find it's probably still the best though Karhu is a bit more friendly on the PC in so far as it doesn't make it near unusable like TM5 during use lol. It can be quite quick to pickup errors as well.
> 
> You can't go wrong using multiple tests and with TM5 using a few different profiles.


Ah yeah TM5 with Anta777 Extreme / Absolut is what I have used a lot as well. I don't mind it being unusable, I just switch my monitor to my other input and watch some YouTube / series on my server lol. It's got a Xeon E3-1270V2 with a GTX760 for display out so it can decode any stream properly hehe.


----------



## PJVol

mongoled said:


> Yes, common denominator is ITX board


IMHO it's not just a form-factor, but the fact that many ITX boards are built on 6-8 layer PCB with overly powerful VRM design, especially those on B550.
My MSI office board is ITX as well, but it can hardly help anything.


----------



## tcclaviger

So doing my regression testing I managed to snag the top blender render spots in 2.93 on their benchmark database, guess I'll do the whole test lmao:









Whelp here's the whole test at a very daily friendly DoS setup, 1.225GET 47.75 CCD1 46.5 CCD2 (core 14 is a lazy ass)










3dMark results are equal or better than my higher speed ram 32 GB setup, can't explain that, same driver version. Lost 1 frame in SotTR 1080p Lowest vs 32gb setup, 257 avg vs 258. I can't seem to pickup the same minimum frame rate I was getting previously, I may have done some windows fsckery that I forgot about on the 258.
17520 in TimeSpy
37299 in Firestrike
10620 in Port Royal

Next BM database I'm after is corona 1.3 top 5950 spot, very close already


----------



## Audioboxer

Imprezzion said:


> Ah yeah TM5 with Anta777 Extreme / Absolut is what I have used a lot as well. I don't mind it being unusable, I just switch my monitor to my other input and watch some YouTube / series on my server lol. It's got a Xeon E3-1270V2 with a GTX760 for display out so it can decode any stream properly hehe.


Yeah I normally let tests run overnight if I have to.

Everyone above talking about PCBs not booting over 1.6v, I accidentally pushed 1.9v into these sticks and it booted into Windows  But what I do have is trouble getting 1.7v stable without maxmem. So I'd probably say around 1.6~1.65v is likely as high as I can go with a full 32GB.


----------



## tcclaviger

Yikes, I have too much mechanical/electronics empathy to push the very high voltages to my gear.

Probably from seeing the magic smoke released too often over the years 

Love seeing what can be done when pushed to those levels though!!


----------



## Audioboxer

tcclaviger said:


> Yikes, I have too much mechanical empathy to push the very high voltages to my gear.
> 
> Love seeing what can be done when pushed to those levels though!!


I was meaning to change CPU 1.8 to 1.9v and accidentally changed DRAM to 1.9v. Pure accident! TM5 rebooted the second it started and when going back into the BIOS on reboot I noticed my mistake!

Buildzoid ran 2v through the SR variant 




I'd guess running 2v through the DR variant is a much riskier proposition.


----------



## tcclaviger

Can't take a screenshot ATM, but it sure looks like Asus DOS has a 190 EDC limit programmed into it.

Might explain certain anomalies when comparing dos benchmarks to standard static ones.

Suppose it could also be junk data involved in the DoS trickery.


----------



## Imprezzion

Audioboxer said:


> Yeah I normally let tests run overnight if I have to.
> 
> Everyone above talking about PCBs not booting over 1.6v, I accidentally pushed 1.9v into these sticks and it booted into Windows  But what I do have is trouble getting 1.7v stable without maxmem. So I'd probably say around 1.6~1.65v is likely as high as I can go with a full 32GB.


These DR's I have have run 4533C18-18-18-38-340-2T @ 1.66v before and they handle it fine on Intel at least. Higher then 1.66v they get unstable very quickly tho and I have temp issues. 1.66v was already pushing 53c which is clearly isn't helping lol.


----------



## tcclaviger

Impressive...looking forward to this last link for AMD to improve, high speed memory.

They've come a long way pretty quick (lol zen 1 memory nightmares still haunt me) so hopefully Zen 4 can start getting closer to Intel RAM capability.


----------



## Audioboxer

Imprezzion said:


> These DR's I have have run 4533C18-18-18-38-340-2T @ 1.66v before and they handle it fine on Intel at least. Higher then 1.66v they get unstable very quickly tho and I have temp issues. 1.66v was already pushing 53c which is clearly isn't helping lol.


Yeah those temps won't be helping. I'm not thermal limited, I'm FCLK limited now.

I can run tCL13 at 1.55v at 3800 and the only other thing I can try at 3800 is tCL12. This needs 1.69v. I've struggled to get 1.69v stable without using maxmem.

If I could more reliably boot 1900 FCLK+ then I'd have more to experiment with voltage in-between 1.55v and 1.7v. 4000 14-14-14-14 seemed to be holding out at 1.55v, but I just can't daily 2000 FCLK. My multithread performance drops through the floor and nothing I've done has been able to stabilise that with my CPU. Apart from multithread performance cratering, I start to get USB disconnects.

Trying 4200/4400 would be really interesting on this kit. I can only hope AMD make strides with the 3D cache revision. So much memory performance left on the table due to WHEA/FCLK.


----------



## MrHoof

Veii said:


> Oh i got procODT down to 28, but doesn't make any change
> #2's #10's, #6's
> Biggest downpuller is, the PCB failing already at such low peak VDIMM


if its just rare 6´s but alot of 10/2 i would suspect your mem controller is garbage or 1 of the sticks cant do tight tcrdrd.
Did you try with 1 stick?




paih85 said:


> vdimm = ??


1.55v


edit: I am curious Audioboxer what kind of errors did you get without MAX mem at your trcdrd 12/13 tests?


----------



## tcclaviger

Found an odd thing.

Over 51f water temp, procODT - 40
Under 48f water temp, procODT - 43.6

It won't post when it's in the wrong setting for temp.

Weird that it's so sensitive, but it is, I wonder how much this type of behaviour extends up in temp and triggers random errors in TM5.


----------



## Audioboxer

MrHoof said:


> if its just rare 6´s but alot of 10/2 i would suspect your mem controller is garbage or 1 of the sticks cant do tight tcrdrd.
> Did you try with 1 stick?
> 
> 
> 
> 1.55v
> 
> 
> edit: I am curious Audioboxer what kind of errors did you get without MAX mem at your trcdrd 12/13 tests?


IIRC Karhu was the stop around 7% which usually indicates very unstable and TM5 was the spewing of 6s. At this point I've basically connected Karhu 7% is going to = TM5 6s on 1usmus lol.

PCB crashed I believe. I'm doing some more testing with tCL12 just now. Leaving tRCDRD at 14 though. tRCDRD 13 just seems like it might be too low for the data transfer rate at 3800 on DR, I'd probably say tRCDRD 13 will be for SR only at 3800, unless you use maxmem. tCL12 shows a tiny bit more promise



















Where I need some help due to inexperience is understanding what needs to change at such high voltages. With maxmem I can basically just leave resistances/drvstr where they always are, but with a full 32GB it becomes clear if I've to even stand a chance of pushing 1.69v through the PCB I'm going to need to play with resistance and drvstr.

But I'm just changing things randomly at the moment lol, I don't quite understand the relationship between high VDIMM and resistance. My total basic understanding is RttPark should probably be weakened and ProcODT might need to go... higher? Or is it lower? Both runs above have ProcODT higher than the 34.3 I normally run it.

@Veii or @mongoled if you want to chip in with high VDIMM it would be appreciated. I'm back in memory school!










DIMM temps at 1.69v barely go over 30 degrees so it's not temps.


----------



## MrHoof

Maybe worth trying diffrent cad bus settings? Like 60-20-24-30 or 60-20-30-24? I never went that high with vDIMM so just a wild guess.


----------



## tcclaviger

SUCCESS!!








You guys kick ass, never would have reached this score alone


----------



## Audioboxer

MrHoof said:


> Maybe worth trying diffrent cad bus settings? Like 60-20-24-30 or 60-20-30-24? I never went that high with vDIMM so just a wild guess.


I don't think a lot of people have with DR which is probably why there is a bit of a knowledge gap lol. But I think there are some "universals" with the VDIMM that if you want to try and go higher you're going to need to increase resistance somewhere in order not to crash the PCB.

Errors in TM5 for me end up being 2's which are either voltage or resistance. The basis of using 1.69v is because under maxmem that was running tCL12 fine. But I do accept that doesn't necessarily mean that will translate to having a chance at a full 32GB. I think it's resistance that is my problem though.










Switching over to TM5 for all runs as you can see it freaks out after a minute, Karhu above went as long as 12 minutes.


----------



## PJVol

tcclaviger said:


> Weird that it's so sensitive, but it is, I wonder how much this type of behaviour extends up in temp and triggers random errors in TM5.


Not sure about Dimm temp itself, but I've asked similar question here and in another forum, regarding ProcODT and S/N relationship.
Just in my case the behavior is kinda reversed, higher ProcODT helped to stabilize RAM at [email protected] and 1.6V.
Yet the question lingered.


----------



## Audioboxer

Defeated 💀 

Best I could manage was reducing the number of 2 errors, and occasionally getting by the first 2 check, then falling down not long after. It's looking like pumping 1.69v through a DR PCB is going to be incredibly difficult, unless...












Who needs 32GB when you can run 6GB!


----------



## Veii

Audioboxer said:


> Hey @Veii here is how you sort your DR issues, just limit Windows to 3~9GB of ram. Who needs more?


Warzone eats all 15.6 on 1440p
On 1080p it was fine, 1440p stutters without a standby cache cleaner as ram is overfilled


----------



## tcclaviger

PJVol said:


> Not sure about Dimm temp itself, but I've asked similar question here and in another forum, regarding ProcODT and S/N relationship.
> Just in my case the behavior is kinda reversed, higher ProcODT helped to stabilize RAM at [email protected] and 1.6V.
> Yet the question lingered.


When I get up tomorrow I'll try some warm boots, like 80f water and see if the trend extends upwards in temps, if so, it may be another data point to go in the table that scales along with the voltages.

Managed to snag #6 spot on passmark PT10 fastest desktop systems of all time but the website is refusing uploads ATM. 120xx overall score, 561xx CPU, 4148 memory, 1470 2d, 33k 3d. Much better than my previous best of 10300 overall.

Seriously I'm so thankful to the active posters over the last....300 pages or so that I've read through.


----------



## Audioboxer

Veii said:


> Warzone eats all 15.6 on 1440p
> On 1080p it was fine, 1440p stutters without a standby cache cleaner as ram is overfilled


I can give you up to 9GB max 

Any thoughts on maxmem? Is it the b-die DR PCB that can't handle high voltage? The IMC? A combination?


----------



## Imprezzion

Well, it booted.. but I lost my spare EK STC 10/16 fittings and had to rig it together with some old plastic barb fittings which didn't seal for anything and leaked all over the place...

I shortened the thread length as they bottomed out in the TechN block and put a new lubed washer on them and finally got them to seal. Looks horrible those black plastic cheapo barb fittings but it works temporarily..

At max pump speed (D5 Xylem @ 4850 RPM) idle 20c across all cores and with a load like CPU-Z Stress test 48-50c across all cores. Not bad. Only have XMP enabled rest all stock.


----------



## ioannis91

Hello guys! I am trying for 4000 on the memory and 2000 fclk but the system just freezes while I am in the bios. I have tried some stuff like procODT, drvstr and soc voltage but nothing changed. Any ideas? or is it that my system just can't do it?


----------



## tcclaviger

Bump PLL 1.8, some boards need over 2.1 @ 2000 some are fine at 1.8.


----------



## Veii

tcclaviger said:


> Can't take a screenshot ATM, but it sure looks like Asus DOS has a 190 EDC limit programmed into it.


It's not asus's fault


Audioboxer said:


> But I'm just changing things randomly at the moment lol, I don't quite understand the relationship between high VDIMM and resistance. My total basic understanding is RttPark should probably be weakened and ProcODT might need to go... higher? Or is it lower? Both runs above have ProcODT higher than the 34.3 I normally run it.


525 is fine over 1.61v
or 624 at the start


Audioboxer said:


> Any thoughts on maxmem? Is it the b-die DR PCB that can't handle high voltage? The IMC? A combination?


Uninteresting for me
Not doing XOC on the most crucial part of the system
Unstable ram crashes everything. Don't see a reason for such
Not even as for XOC to proof anything - as everything around it is unusable when DRAM is unstable

XOC CPU and GPU brings the industry further (better designed cards), and it will run shortly fast
XOC ram , idk which industry it brings forward
Even when DDR4 is not important anymore
Really no reason to spare time on unstable settings, you can't daily


Audioboxer said:


> Is it the b-die DR PCB that can't handle high voltage? The IMC? A combination?


A mixture of questionable DIMM PCB and questionable Mainboard PCB
One of both (can also be AMD) didn't follow the spec and "knew more" ~ soo it's completely unstable

That , and that this bequiet Plat PSU is not stable.
Gave multi rails another chance, and it's as it always for me "problematic"
My best outcome of hope is "to blame my CPU for not dealing well with the already bad signal integrity caused by the PSU, amplified by the design" and to hope Rev.B2 silicon is less sensitive to bad signal integrity and will run them easily

I can only blame AMD for being sensitive to memory
But i have to blame either G.Skill or ASUS for not following spec here
As this issue exists between MSI and ASUS ~ soo we can blame AMD FW
Yet both "knew more" or G.Skill just followed Intel's design spec

Somebody in the chain didn't follow the spec, that's for sure readable by the outcome
DIMM PCB also crashes at 3200 at higher voltage
Trace issue of Mainboard or DIMM-PCB , one of both
Because my ITX handles this ok'ish. DIMMs where bad but not as bad as i can see here on this daisy chain board

EDIT:
What i can blame ASUS for sure , or AMD + ASUS
Is the "non existing" correct values for powering of DR
timings prediction is ok, that kind of somehow works ~ questionable but works
Powering is "non existent" , as without manual input (of the same values so to speak) it refuses to post at all
It is stuck in it's own unknown training values ~ when it trains correctly (without fast boot mode)
Tho it mostly misstrains two different things for two identical dimms = endresult is a mess
(if it even posts, without manual user fix)
* this issue also exists on the B550 Strix-F even for 2x8GB dimms

What i can give them credit for, is the fast memory reset and that there is no "memory hole" on any frequency
But honestly, a problem that shouldn't exist in the first place ~ shouldn't be praised that it's not existing on this board. I don't know 

EDIT2:
Also MBIST is broken too *
Might explain half, why memory training is questionable at best, on this Patch-C release
* in the sense, that the feature is not functioning at all. Soo half of what belongs to memory training, is simply "unfunctional"
Not sure who to blame here, AMD's
_(between vendors different SMU & patches package on Patch-C)_
(An inconsistency between Vendors, which AMD does not enforce but has to enforce and take care about it)
Or ASUS's completely nonfunctional crucial feature inside AMD CBS + bugged PBO settings
(AMD CBS belongs to AMDs blame, but i am not sure at this point of the mess ~ who to push the blame on)


ioannis91 said:


> Hello guys! I am trying for 4000 on the memory and 2000 fclk but the system just freezes while I am in the bios. I have tried some stuff like procODT, drvstr and soc voltage but nothing changed. Any ideas? or is it that my system just can't do it?


"Some stuff" ?


----------



## Veii

Veii said:


> Not sure who to blame here, AMD's
> _(between vendors different SMU & patches package on Patch-C)_
> (An inconsistency between Vendors, which AMD does not enforce but has to enforce and take care about it)
> Or ASUS's completely nonfunctional crucial feature inside AMD CBS + bugged PBO settings
> (AMD CBS belongs to AMDs blame, but i am not sure at this point of the mess ~ who to push the blame on)


Maybe every Vendor has the same issue by AMD
And only ASRock seems to get this together and fix memory training by themself ~ yet hide more and more of AMD CBS
Likely can't give them credit for something good, when the reason why it functions "is hidden" and the user get's less and less options to pick from
Old ASRock followed an open AMD CBS & PBS design. Current ASRock does focus on following everything perfectly on AM4 ~ which in this case gives them no issues, but on every other case is just booring to work with.
Sure it "just works" but it's booring to play with.
I don't know here either  ~ it's their business model

Can only wish that either AMD (also for the all boards run the same AGESA and same patches ~ part / where is fixed 1204B/1205 ?) ,
and ASUS + MSI get their memory training together
It's more than a mess right now, even when DPM Dropout issues disappeared and NIC issues seem to have finally FW updates out, to also disappear as issues 

EDIT:
SoonTM















Likely mid December


----------



## PJVol

Veii said:


> Current ASRock does focus on following everything perfectly on AM4 ~ which in this case gives them no issues, but on every other case is just booring to work with


Even though I agree it can be boring for some, I like such business model 
Just curious, is it for the same reason 1.2.0.4 fw not being rolled out yet?


----------



## maksimin11

5600X 4000c16 DR 16g x2 straight with 1:1 DIMM 1.56v

























Last modify list
tRDRDSCL decreased 5 to 4
tWRWRSCL decreased 5 to 4
tWRRD match to 16 (tRDRDSCL x tWRRD = tRCDWR)
tRDWR(8) x 2 = 16 (tRCDRD)
tRRRDL increased 6 to 8

Before modify vDIMM 1.52v (TM5 50cyc pass)

















Is that rolled out good result?
but AIDA latency is same..
I trying reach HCI memtest at least 400%.


----------



## PJVol

maksimin11 said:


> 4000c16 DR 16g x2


Do you have two ccd's in your 5600X, or it's 4xx chipset board let it run whea-free.
My ordinary 5600x ran 2000 fclk without whea's on b450 as well.


----------



## PJVol

@Mach3.2
Yeah ) I've posted test results here a few months ago, some time after asrock finally dared to push 1.2.0.0 update )
(the reason for that anomaly is still unclear to me, to be honest, as it being at odds with a popular theory of the CPU-only limitation.
@Veii et al. has done some research but has yet to confirm the results )


----------



## umea

Are 2ccd 5600xs early models?


----------



## Taraquin

maksimin11 said:


> 5600X 4000c16 DR 16g x2 straight with 1:1 DIMM 1.56v
> 
> View attachment 2534778
> 
> View attachment 2534779
> 
> View attachment 2534780
> 
> Last modify list
> tRDRDSCL decreased 5 to 4
> tWRWRSCL decreased 5 to 4
> tWRRD match to 16 (tRDRDSCL x tWRRD = tRCDWR)
> tRDWR(8) x 2 = 16 (tRCDRD)
> tRRRDL increased 6 to 8
> 
> Before modify vDIMM 1.52v (TM5 50cyc pass)
> View attachment 2534781
> 
> View attachment 2534782
> 
> 
> Is that rolled out good result?
> but AIDA latency is same..
> I trying reach HCI memtest at least 400%.


Mostly good, but I don't think you need that high voltage to run 4000cl16 2T. I have 2x8 avg bin B-dies and run 4000cl16 1T at 1.46V, 2T at 1.45V. Try tFAW 16, tRFC 288 or 272. Unless you got a poor bin you should be able to do 1.45-1.5V even with my suggestions  

Vddp 900mv should work and ccd shouldn't need more than 1000mv.


----------



## umea

If I were to purchase AIDA64, would it count every new windows install as a new system? I reinstall windows somewhat often, so if I'm limited to only 3 installs then that would make me sad. Anyone know?


----------



## Veii

PJVol said:


> Even though I agree it can be boring for some, I like such business model
> Just curious, is it for the same reason 1.2.0.4 fw not being rolled out yet?


I do too. But it sometimes causes them Problems with being forced to end support for X370/X470 because AMD decided that way

They could just keep making it right, keep taking their 1 month for bios testing
And maybe just have slight bit of standing ground to enable AMD CBS back "for the users"
Tho, if that changes their relationship to AMD ~ they know what's good and what works.
What i'd at least wish, is the removal of this useless tripple CRC checks.
One is AMIs, 2nd is AMDs, and 3rd is ASRocks
AMIs can be disabled, AMD just enforces to use AMI tools, and ASRocks is just here to mock the userbase 

1204,
this is all i can re-share by HWLuxx








Patch is not 100% clear, as there where indeed dying Cezanne unis by FW flaws (on stock booting dangerous voltage)
But haven't gotten any reason or information for Renoir to need special treatment.
Maybe combined with the VDDG issue

ASUS 1203C is still SMU 56.53,
Same as ASRock's on the number part
But everyone as it was for 1100C and currently ~ still has a differential amount of patches applied between Vendors
At least you don't have to hope for X board to have the I/O issues fixed or not ~ on all this should be an issue of the past
Yet "memory hole", just training issues remain to exist & it's hard to work on a baseline, when AMD still needs to even out the hotfix & patch mess since 1100D+

Probably in their best intention, is to quiet down hotfixes
And just push one fixed ~ which i expected to be 1204A
But hey, 1205 is out since the 26th
Soo for us ASRock users, likely before or @ christmas
As for ASUS users, the Strix and Crosshair appear to be again the testing rabbits. We'll see if Gigabyte pushes something out before XT release, after already having 1204A out
As for MSI, so far i haven't seen any Chiphell _leaks_ of Beta versions to test.

If time remains and nothing moves on - i'll give it another try to transplant SMU over
Sadly it's again bigger than the space it fits in, and i'm not experienced enough to extend and location-shift modules without breaking the signature. We'll see
====================================
Slight progress on RTTs, this seems to function @ 1.47v
But only functions with procODT @ or bellow 30ohm. On 32 the PCBs crash








At least it's better than this hot set @ 240ohm Park
Well, to some extend.
My higher timings and method of work, still outperform it
But considering 2T was an allcore, while 1T-56 is back to PBO
Considering it's also Win11 and 1T-56 , is 26-28 trained
Result can be called "equal performing".
No important speed progress, but at least alternative suitable RTT+CAD_BUS
Soo babysteps forward. At least something from 2-3 days of messing with it
===========
Another interesting exploration,
If you follow Anta's tCL = tWR, then tWTR_L = tRTP has to be set
Else you error #11, and #13

#13 mostly comes for me, if procODT "was too high"
#10 comes if signal was too noisy (CAD_BUS), or VDIMM was not enough
#2 and #10's also come if tWTR_ & tRRD_ are not fine
===========
Another interesting part
While tCKE still remains MCLK scaling
SETUP times beyond 32 do not ?
3600 should've been 55-0-0
And while it works, it was also an error reason for #13 & #10
Somewhy , still unexplained 56-0-0 keeps working. It is awkward, yet still a lot to explore.
Just some tiny update and a book keeping/archive note

1.47v requirements didn't change
Dimms are just ~ subpaar, to plain bad

Work required to fix 26-28 missmatch is now either:
~ running tCL 13, tCWL 12
~ pushing tRDWR down to 7 (never worked)
~ pushing tWRRD up to 4 (messes up my timings)
~ running SCL 6-6 (gifts performance)
Or just not using setup timings and getting it that way to somehow work

*RTT 634 has to work *for everybody beyond 1.45v
*RTT 635 is* also a *possible* one, but it refuses on my side bellow 1.55+. Likely *better suited for 1DPC boards*


----------



## Veii

MrHoof said:


> if its just rare 6´s but alot of 10/2 i would suspect your mem controller is garbage or 1 of the sticks cant do tight tcrdrd.
> Did you try with 1 stick?


Last part, i don't want to know
MemController is great, sadly
Signal integrity with this PSU is not great, and dimms are not great. Dimms are "fine" on my ITX

Never tested only 1 dimm of anything
Wouldn't want to fixate myself on accepting "it just can't work"
It can, if you bruteforce it ~ and voltage does help.
Keeping stability up, is another question

When chip can do 4067 14-14-14 SR, it will do 3800 14-14-14 ^^'
There are other walls to climb and other problems to fight on.
The errors between 3200 14-14 and 3600 14-14 are pretty much identical.
A powering issue still, soo that's where to focus is now 


umea said:


> Are 2ccd 5600xs early models?


First batch 2036 models , 2nd batch had this oopsy fixed.
October, November models - all don't have this type of internal issue and go higher WHEA free
2nd batch November,December models got fixed and labs expanded to BG 20XX PGS
Also to central europe near February
This oopsy will likely never happen again
But fused cores are not really dead or disabled to begin with


maksimin11 said:


> I trying reach HCI memtest at least 400%.


HCI & Karhu "german" stability rating was 10 000%
1usmus_v3 is over 20 cycles minimum
Anta's people run between 3 and 9 cycles

Soo generally 1+ hour for 2x8
~3 hour for 2x16

German HCI & Karhu rule, was near the 8-10hour (they only go with %)
GSAT i think also near the 6+ hours.
Errors on these programms appear later
Soo people made a list after 1000%, 2500%, 5000%, and 10 000% is required stability rating

Please run them overnight for bit longer
And check if on 2T you have tPHYRDL missmatch between dimms
or tRDWR/tWRRD missmatch with 4 dimm Boards

EDIT:
Only beyond 45-48min contineous load, you reach thermal equilibrium on anything
Good memory tests have to take at least 1 hour, to be considered stable
It's not silicon, and capacitors + resistors change stability by operating temperature.
Not reaching at least thermal equilibrium is kind of, questionable 

I test with open window on cold (dimms stay near 40-41c) ~ to check timings
and later on the other day after cold boot, with normal usage warm room temp ~ to check PCB stability
If it fails, the reason is easier to figure out
But if it fails while you sleep, the issue is hard to figure out
Watch it active for 30min,
if then it remains fine - better test over 1 hour for 2x8 and over minimum 2 hours for 2x16.

EDIT 2:








Pick one:

you follow anta's rule, match tCL = tWR, match tRTP = tWTR_L
you don't follow anta's rule, and use tWR = tRTP*2 , then have no connection to tWTR_S & _L
* if you follow anta's rule, tFAW has to be 4* tRRD_S
*' if you follow anta's rule, tRAS has to be tRC-tRP
** if you follow my rule for tRTP*2 = tWR, tRAS doesn't matter if it's tRCD*2, or tRCD+tRTP, or tRCD*2+tCCD_L or tRCD*2+tBURST
tRC can then be anything, even the exploit of tRAS+1 ~ when you shift focus on tRRD_ (higher these). Same goes for tFAW, can be anything from bellow realistic burst refresh or 4* tRRD_S, or tCCD_L times tRRD_S

EDIT3:
I've tested this on my 15-15 set
There using tWR 15 (=tCL) vs using tWR 16 (=tRTP*2), shows quite a big difference.
_* also between tRRD_S *4 & tRRD_S * tCCD_L_
Sync difference ~ as 1Clk (tWR) can't result in over 800-1000MB/s bandwidth difference
Both are stable, but "the Methodic" is just different.
DRAM never has only "one way of optimisation" ~ hence anta and 1usmus can never agree with tWR results
set behaves just different ~ it makes no sense to fight over "rules". 

EDIT4:


Veii said:


> Both are stable, but "the Methodic" is just different.
> DRAM never has only "one way of optimisation" ~ hence anta and 1usmus can never agree with tWR results
> set behaves just different


Soo currently i explore more anta's method
Of course he is right how it has to run. But results show that it's very finicky and barely stable
When stable, sometimes faster, sometimes not (up to other timings around it)
Can't prefer one over the other yet, just know that it's easier to work with something you know how to work with 
Following his advices does indeed lead to more bandwidth, but barely is get-table stable
Else timing stability, i still keep having better results with my higher tertiaries, than his lower focused ones. Looking at the end result, not XOC


----------



## Taraquin

Veii said:


> Last part, i don't want to know
> MemController is great, sadly
> Signal integrity with this PSU is not great, and dimms are not great. Dimms are "fine" on my ITX
> 
> Never tested only 1 dimm of anything
> Wouldn't want to fixate myself on accepting "it just can't work"
> It can, if you bruteforce it ~ and voltage does help.
> Keeping stability up, is another question
> 
> When chip can do 4067 14-14-14 SR, it will do 3800 14-14-14 ^^'
> There are other walls to climb and other problems to fight on.
> The errors between 3200 14-14 and 3600 14-14 are pretty much identical.
> A powering issue still, soo that's where to focus is now
> 
> First batch 2036 models , 2nd batch had this oopsy fixed.
> October, November models - all don't have this type of internal issue and go higher WHEA free
> 2nd batch November,December models got fixed and labs expanded to BG 20XX PGS
> Also to central europe near February
> This oopsy will likely never happen again
> But fused cores are not really dead or disabled to begin with
> 
> HCI & Karhu "german" stability rating was 10 000%
> 1usmus_v3 is over 20 cycles minimum
> Anta's people run between 3 and 9 cycles
> 
> Soo generally 1+ hour for 2x8
> ~3 hour for 2x16
> 
> German HCI & Karhu rule, was near the 8-10hour (they only go with %)
> GSAT i think also near the 6+ hours.
> Errors on these programms appear later
> Soo people made a list after 1000%, 2500%, 5000%, and 10 000% is required stability rating
> 
> Please run them overnight for bit longer
> And check if on 2T you have tPHYRDL missmatch between dimms
> or tRDWR/tWRRD missmatch with 4 dimm Boards
> 
> EDIT:
> Only beyond 45-48min contineous load, you reach thermal equilibrium on anything
> Good memory tests have to take at least 1 hour, to be considered stable
> It's not silicon, and capacitors + resistors change stability by operating temperature.
> Not reaching at least thermal equilibrium is kind of, questionable
> 
> I test with open window on cold (dimms stay near 40-41c) ~ to check timings
> and later on the other day after cold boot, with normal usage warm room temp ~ to check PCB stability
> If it fails, the reason is easier to figure out
> But if it fails while you sleep, the issue is hard to figure out
> Watch it active for 30min,
> if then it remains fine - better test over 1 hour for 2x8 and over minimum 2 hours for 2x16.
> 
> EDIT 2:
> View attachment 2534858
> 
> Pick one:
> 
> you follow anta's rule, match tCL = tWR, match tRTP = tWTR_L
> you don't follow anta's rule, and use tWR = tRTP*2 , then have no connection to tWTR_S & _L
> * if you follow anta's rule, tFAW has to be 4* tRRD_S
> *' if you follow anta's rule, tRAS has to be tRC-tRP
> ** if you follow my rule for tRTP*2 = tWR, tRAS doesn't matter if it's tRCD*2, or tRCD+tRTP, or tRCD*2+tCCD_L or tRCD*2+tBURST
> tRC can then be anything, even the exploit of tRAS+1 ~ when you shift focus on tRRD_ (higher these). Same goes for tFAW, can be anything from bellow realistic burst refresh or 4* tRRD_S, or tCCD_L times tRRD_S
> 
> EDIT3:
> I've tested this on my 15-15 set
> There using tWR 15 (=tCL) vs using tWR 16 (=tRTP*2), shows quite a big difference.
> _* also between tRRD_S *4 & tRRD_S * tCCD_L_
> Sync difference ~ as 1Clk (tWR) can't result in over 800-1000MB/s bandwidth difference
> Both are stable, but "the Methodic" is just different.
> DRAM never has only "one way of optimisation" ~ hence anta and 1usmus can never agree with tWR results
> set behaves just different ~ it makes no sense to fight over "rules".
> 
> EDIT4:
> 
> Soo currently i explore more anta's method
> Of course he is right how it has to run. But results show that it's very finicky and barely stable
> When stable, sometimes faster, sometimes not (up to other timings around it)
> Can't prefer one over the other yet, just know that it's easier to work with something you know how to work with
> Following his advices does indeed lead to more bandwidth, but barely is get-table stable
> Else timing stability, i still keep having better results with my higher tertiaries, than his lower focused ones. Looking at the end result, not XOC


I was mostly able to follow anta's rules, but getting wtrl=rtp was impossible. Best I got was 9, 8 was always unstable, and since cl is 16 rules don't match up if I use 18 wr. Also getting the wrwrXX and rdrdXX according to rules was unstable, scls at 2 or 3 is impossible, but 4 works, 8gb dimms = rfc divideable by 8 and 16gb div by 16 works great. Also flat primaries. On uneven cl rules don't add up that good. My hoghest stable on 4000 is most by the rules, but 3800cl15 messes up a lot since wr 14 and rtp 7 is further away from wtrl 9.

My best results at 4000 is flat 16, 29 ras, 45 rc, 280 rfc, 3/9 wtr, 4/4/16 rrd/faw, 4 scls, 10/5 wr/rtp, 8 rdwr, 1 wrrd and rest on auto. Getting 51.5-52ns in aida with that and CO+200 pbo.


----------



## Akex

Hi Geek, I've been having fun for a few days with a Zen1 APU (Ryzen 2400G) and a Crucial 3600C16 2x8 Kit [C9BKV].

At 3600Mhz XMP profile is rock stable no worries, I pushed 3666Mhz the same, arrived 3733Mhz I had to start configured the RTT and review procODT, I managed to do more than 3 hours without error.
After having rebooted the PC and mounted 3800Mhz just for testing knowing that it was improbable, I returned to my 3733Mhz profile which spent 3 hours, except that since with exactly the same configuration I have errors which pop up after 2min and the various combinations RTT / ProcODT tested do nothing, I had better with RTTPark on 40 instead of 60 but nothing more.

Do you have any idea what can disturb the kit so much?
I put myself in real condition, that is to say with the IGPU OC because it requires a large vSOC, which may be the cause of my concern, except that no, after having transferred the OC iGPU and passed vSOC On 1.1v I always have the same result. I admit I dry a can.
Maybe DrvStr to review? or cLDO to review? These are the two that I have yet to try.

Your analysis is welcome, knowing that here it is Zen1 and not Zen3 attention ^^


----------



## Taraquin

Akex said:


> Hi Geek, I've been having fun for a few days with a Zen1 APU (Ryzen 2400G) and a Crucial 3600C16 2x8 Kit [C9BKV].
> 
> At 3600Mhz XMP profile is rock stable no worries, I pushed 3666Mhz the same, arrived 3733Mhz I had to start configured the RTT and review procODT, I managed to do more than 3 hours without error.
> After having rebooted the PC and mounted 3800Mhz just for testing knowing that it was improbable, I returned to my 3733Mhz profile which spent 3 hours, except that since with exactly the same configuration I have errors which pop up after 2min and the various combinations RTT / ProcODT tested do nothing, I had better with RTTPark on 40 instead of 60 but nothing more.
> 
> Do you have any idea what can disturb the kit so much?
> I put myself in real condition, that is to say with the IGPU OC because it requires a large vSOC, which may be the cause of my concern, except that no, after having transferred the OC iGPU and passed vSOC On 1.1v I always have the same result. I admit I dry a can.
> Maybe DrvStr to review? or cLDO to review? These are the two that I have yet to try.
> 
> Your analysis is welcome, knowing that here it is Zen1 and not Zen3 attention ^^
> 
> View attachment 2534892


You might be on the limits of IMC. I build a 2400G setup using rev E like you and 3533 was max bootable. Try upping tRCDRD to 19, that will probably fix it. 1.2v dimm? Seriously that is insanely low for those timings! As for other timings they will probably run fine at tRFC 560 or maybe lower, tRC 55-60, RP, RDD's and FAW tends to go low, as do WR/RTP and WTR's. Only tRCDRD, tRC and tRFC needs to be high. If I were you I'd rather tune timings at 3666.


----------



## Akex

Taraquin said:


> You might be on the limits of IMC. I build a 2400G setup using rev E like you and 3533 was max bootable. Try upping tRCDRD to 19, that will probably fix it. 1.2v dimm? Seriously that is insanely low for those timings! As for other timings they will probably run fine at tRFC 560 or maybe lower, tRC 55-60, RP, RDD's and FAW tends to go low, as do WR/RTP and WTR's. Only tRCDRD, tRC and tRFC needs to be high. If I were you I'd rather tune timings at 3666.



This is a Zentiming bug, vDIMM on 1.48v. I'll try your recommendations, knowing that I left the XMP timings at first, with only tRC and tRFC set to auto to adjust by itself.

For 3733Mhz I'm just looking to have fun and understand more the relationships between all these little people, RTT / ProcODT etc etc.
For H24 I will stick to 3666Mhz with optimized timings.


----------



## Audioboxer

> Thank you for contacting ASUS support
> 
> We are terribly sorry to be advised that you are experiencing issues with your ASUS product.
> 
> To arrange a return/RMA of the component, please contact your seller to arrange the return for repair, replacement or refund. Please note that the return can be arranged via the distribution chain only. As ASUS does not sell any products directly to end users we cannot be seen as the seller.
> 
> Our apologies for the inconveniences caused to you.


Amazon it is then if the PSU is faulty.

Gotta say that is a pretty weak cop out on ASUS' part. While Amazon is normally a good retailer to deal with over a year on, other retailers can be far worse. If a power supply has a 10 year guarantee and you buy it from a retailer who doesn't exist in 5 years, what does ASUS do then? 

As for the claim itself https://www.asus.com/uk/Motherboards-Components/Motherboards/All-series/filter?Spec=126657 That looks like selling products directly to end users 👀

So I guess I go back to EVGA and Corsair are the only two companies I've had good RMA experiences with in terms of them doing something for me rather than telling me to go to the retailer.

Think I'll avoid all ASUS products in the UK in the future, because at the end of the day it's always good to know if you have an issue with any retailer that the manufacturer will have your back.

Quite honestly I don't even know how ASUS can operate legally within the EU/UK with this kind of refusal to handle their own products. More so on products that have extended warranties outwith the usual 1 year.


----------



## Mach3.2

Audioboxer said:


> Amazon it is then if the PSU is faulty.
> 
> Gotta say that is a pretty weak cop out on ASUS' part. While Amazon is normally a good retailer to deal with over a year on, other retailers can be far worse. If a power supply has a 10 year guarantee and you buy it from a retailer who doesn't exist in 5 years, what does ASUS do then?
> 
> As for the claim itself https://www.asus.com/uk/Motherboards-Components/Motherboards/All-series/filter?Spec=126657 That looks like selling products directly to end users 👀
> 
> So I guess I go back to EVGA and Corsair are the only two companies I've had good RMA experiences with in terms of them doing something for me rather than telling me to go to the retailer.
> 
> Think I'll avoid all ASUS products in the UK in the future, because at the end of the day it's always good to know if you have an issue with any retailer that the manufacturer will have your back.
> 
> Quite honestly I don't even know how ASUS can operate legally within the EU/UK with this kind of refusal to handle their own products. More so on products that have extended warranties outwith the usual 1 year.


Where I'm located at, repairs/exchanges are required to go through the local distributor of the brand too. Basically the distributor brings in products on a larger scale and sell pallets to the individual retail stores where the consumer purchase from.

But granted this island that I call home is pretty small geographically, so it's not too much of a hassle to bring the product back to the distributor for any repairs/exchanges.

Does the UK not have something similar for Asus products?


----------



## blodflekk

On intel the floor for tRAS was 28, is this still true for AMD ?


----------



## ManniX-ITA

Audioboxer said:


> Gotta say that is a pretty weak cop out on ASUS' part. While Amazon is normally a good retailer to deal with over a year on, other retailers can be far worse. If a power supply has a 10 year guarantee and you buy it from a retailer who doesn't exist in 5 years, what does ASUS do then


Yes, they sell directly in Europe and could handle the RMA.
But normally almost everyone tries to avoid it.
Unless they have some presence and they want to keep a good relationship with the customers after sales.
ASUS is not one of those companies.

They have no obligations to process the RMA inside the 2 years of EU warranty.
You must go to the seller if they decline it.
After that, if they declared more than 2 years, they are obliged to.


----------



## Audioboxer

Mach3.2 said:


> Where I'm located at, repairs/exchanges are required to go through the local distributor of the brand too. Basically the distributor brings in products on a larger scale and sell pallets to the individual retail stores where the consumer purchase from.
> 
> But granted this island that I call home is pretty small geographically, so it's not too much of a hassle to bring the product back to the distributor for any repairs/exchanges.
> 
> Does the UK not have something similar for Asus products?


Of all the warranty claims I've ever had to do no manufacturer has ever turned me down like ASUS in the UK. I have often gone via the retailer, but that is usually if something is wrong within a short period of time, like the first 30 days. After that, more so if we're talking like a year or so on so I've had multiple things repaired or replaced by the manufacturer.

Recently I had a SMEG coffee machine break and instead of going to Wayfair I went directly to SMEG and they did a door-stop exchange. Even better than an advanced RMA. Corsair and EVGA do advanced RMAs, though EVGA pretty much shut it down because people were abusing it to get second graphics cards.

Just surprises me ASUS claim to not have any direct handling of their products, especially stuff like this power supply which is a 3 year warranty. A lot of retailers outwith the likes of Amazon will start getting weird if you're trying to return stuff after a year. Though maybe those that sell ASUS products know they have to take it back.

Still, as I said something as awkward as this will just turn me off future ASUS products. I think the PSU is the only ASUS thing I own at the moment tbf. Always better if a company just goes the extra mile to have your back, as some retailers can be quite annoying. Amazon is thankfully usually really good with returns/faults.


----------



## tcclaviger

Audioboxer said:


> Amazon it is then if the PSU is faulty.
> 
> Gotta say that is a pretty weak cop out on ASUS' part. While Amazon is normally a good retailer to deal with over a year on, other retailers can be far worse. If a power supply has a 10 year guarantee and you buy it from a retailer who doesn't exist in 5 years, what does ASUS do then?
> 
> As for the claim itself https://www.asus.com/uk/Motherboards-Components/Motherboards/All-series/filter?Spec=126657 That looks like selling products directly to end users 👀
> 
> So I guess I go back to EVGA and Corsair are the only two companies I've had good RMA experiences with in terms of them doing something for me rather than telling me to go to the retailer.
> 
> Think I'll avoid all ASUS products in the UK in the future, because at the end of the day it's always good to know if you have an issue with any retailer that the manufacturer will have your back.
> 
> Quite honestly I don't even know how ASUS can operate legally within the EU/UK with this kind of refusal to handle their own products. More so on products that have extended warranties outwith the usual 1 year.


I'm sadly not shocked. I have not had that experience with them for RMAs, but I know many people have. I think I'm starting to notice a diverging trend from many companies.

UK - Go through distributor.
US - Go through manufacturer.

There are certainly exceptions, in both ways, but I see the above scenarios most often, not just in PC stuff, 3d Printers, CNC machines etc. Really sucks, the brand that has their name on it should honor it...

EVGA - Had 2 2080ti RMAs with EVGA, zero drama.

Corsair - Both RMAs I've had with them they tried to offer me a lower SKU. When I refused, suddenly the same SKU became available, not a big deal really just very "Corsair" of them.


----------



## Audioboxer

tcclaviger said:


> I'm sadly not shocked. I have not had that experience with them for RMAs, but I know many people have. I think I'm starting to notice a diverging trend from many companies.
> 
> UK - Go through distributor.
> US - Go through manufacturer.
> 
> There are certainly exceptions, in both ways, but I see the above scenarios most often, not just in PC stuff, 3d Printers, CNC machines etc. Really sucks, the brand that has their name on it should honor it...
> 
> EVGA - Had 2 2080ti RMAs with EVGA, zero drama.
> 
> Corsair - Both RMAs I've had with them they tried to offer me a lower SKU. When I refused, suddenly the same SKU became available, not a big deal really just very "Corsair" of them.


When my 2080Ti died I was nervous about that, as EVGA are known, especially during this graphics card crisis, to have to swap you to an equivalent card. If you get something better, great, but the replacement for a 2080Ti is a 3070. That is NOT equivalent and secondly as my 2080Ti is watercooled that would be a huge PITA. I'd have to buy a 3070 waterblock. Thankfully they had another of my 2080Ti model. I think it was people returning things like a 2080Ti FTW model that were getting 3070s. 

My failure with Corsair was a commander pro fan port, so it's not like they can give another SKU of that lol.


----------



## ManniX-ITA

tcclaviger said:


> UK - Go through distributor.
> US - Go through manufacturer.


It's typical for EU, always has been like that.
We got an EU framework at some point but the reality is that Europe is a non homogeneous meta-country with 24 different languages and different national legislations.
The manufacturers they count on the distribution chain to handle after sales, otherwise the cost would drive the goods prices up.
In US the retailers are quickly disappearing, here still not.



tcclaviger said:


> Corsair - Both RMAs I've had with them they tried to offer me a lower SKU. When I refused, suddenly the same SKU became available, not a big deal really just very "Corsair" of them.


Corsair RMA in Europe is very nice usually.
They answer in English of course.
Always sent me free of charge anything I complained about; mostly broken or missing parts for cases.
Of course they have to handle much less requests from Europe as we usually go first to the seller.


----------



## Audioboxer

Oh, I forgot to add when I did my Corsair RMA the return address label in the UK was actually to Scan. Scan is a well known online retailer here. So in effect my commander pro was returned to Scan even although I bought it from Amazon lol.

I guess that is the kind of customer service Asus could offer. Even if a buyer comes to them directly, if they have a receipt, then the faulty product can be sent to whatever UK retailer handles their products for presumably shipping back to an EU location.

Might not seem like much but it's just an example of two different companies handling things differently for the end user.


----------



## Veii

blodflekk said:


> On intel the floor for tRAS was 28, is this still true for AMD ?


15 HEX = 21 decimal 








Technically 20, on reviewer bioses


----------



## Akex

Taraquin said:


> You might be on the limits of IMC. I build a 2400G setup using rev E like you and 3533 was max bootable. Try upping tRCDRD to 19, that will probably fix it. 1.2v dimm? Seriously that is insanely low for those timings! As for other timings they will probably run fine at tRFC 560 or maybe lower, tRC 55-60, RP, RDD's and FAW tends to go low, as do WR/RTP and WTR's. Only tRCDRD, tRC and tRFC needs to be high. If I were you I'd rather tune timings at 3666.


It didn't do anything, I don't understand how I was able to make 3h TM5 stable, save the profile, shut down the PC for 3800Mhz test, then reboot the next time by reloading the 3733Mhz profile, nothing stable anymore ....


----------



## nick name

Akex said:


> It didn't do anything, I don't understand how I was able to make 3h TM5 stable, save the profile, shut down the PC for 3800Mhz test, then reboot the next time by reloading the 3733Mhz profile, nothing stable anymore ....


Memory training is what I'd assume.


----------



## Akex

nick name said:


> Memory training is what I'd assume.


TM5 errors if I check Veii's doc indicates bad resistance. I also told myself that it was memory training but I'm not very sure or I don't understand how it could be possible even with very wide timings like 20-22-22-22-39


----------



## Imprezzion

Oof. I can't get my 5900X+B550 XE to POST with 3600C14. It just loops 0D post code and I have to CMOS CLR as it won't even trigger a RAM OC failed safe mode.

The dimms I use are Trident-Z Neo 2x16GB 3600C16 DR B-Die which I have run on Intel at 4200 15-16-16-33-280-2T @ 1.60v and 4400 17-17-17-38-340-2T @ 1.50v so I kinda expected them to easily run 3600C14 @ 1.50v ish but yeah kind of a surprise to see it not even attempt to POST. C15 with GDM disabled was fine but not stress tested.

What would you guys recommend me to chase first. 3800 or higher frequency 1:1 mode or just stay at 3600:1800 and push as low as possible timings. I don't wanna spend 100 hours testing RAM again like I have on Intel so I want one thing to focus on and get that stable and then just not touch it again.

Yes, it can boot and run games at 3800C16-16-16-36-302-1T 1.450v : 1900 IF @ 1.081v SoC but I haven't done any stress testing yet or tweaking of subtimings or anything else. Just Auto all except primary timings, voltage and frequencies.

EDIT: Fixed, ProcODT and resistances were way off. Now it boots fine even with slightly tweaked subtimings.











Time to stresstest it. First up: TM5 Anta777 Absolut.


----------



## LionAlonso

Imprezzion said:


> Oof. I can't get my 5900X+B550 XE to POST with 3600C14. It just loops 0D post code and I have to CMOS CLR as it won't even trigger a RAM OC failed safe mode.
> 
> The dimms I use are Trident-Z Neo 2x16GB 3600C16 DR B-Die which I have run on Intel at 4200 15-16-16-33-280-2T @ 1.60v and 4400 17-17-17-38-340-2T @ 1.50v so I kinda expected them to easily run 3600C14 @ 1.50v ish but yeah kind of a surprise to see it not even attempt to POST. C15 with GDM disabled was fine but not stress tested.
> 
> What would you guys recommend me to chase first. 3800 or higher frequency 1:1 mode or just stay at 3600:1800 and push as low as possible timings. I don't wanna spend 100 hours testing RAM again like I have on Intel so I want one thing to focus on and get that stable and then just not touch it again.
> 
> Yes, it can boot and run games at 3800C16-16-16-36-302-1T 1.450v : 1900 IF @ 1.081v SoC but I haven't done any stress testing yet or tweaking of subtimings or anything else. Just Auto all except primary timings, voltage and frequencies.
> 
> EDIT: Fixed, ProcODT and resistances were way off. Now it boots fine even with slightly tweaked subtimings.
> 
> View attachment 2534952
> 
> 
> 
> Time to stresstest it. First up: TM5 Anta777 Absolut.


1,5V vdimm?
Ill suggest to go for 3800 if ur FCLK runs it and u dont want to loose much time testing things.


----------



## Imprezzion

LionAlonso said:


> 1,5V vdimm?
> Ill suggest to go for 3800 if ur FCLK runs it and u dont want to loose much time testing things.


Nah 1.60v vDIMM. It failed after 28 minutes Absolut. Error #6 I believe. And straight up 8 of them. Not temp related, hotter dimm of the 2 was just at 39.8c.

Yes, it can boot 3800 : 1900 but it isn't very stable lol. That is probably as I have all the voltages on Auto except SoC (1.081v) but yeah.

I have to read up a bit on AMD RAM OC and what voltage does what and what ProcODT / resistances I should start at.


----------



## MrHoof

@Imprezzion
Switch to 2T GDM disabled, geardown mode does auto correct at times and u can not use odd tCL with it.
For 1T GDM disabled people often use a trick with AddrCmdSetup 56 to make it work but maybe you are a lucky one who does not need it.
I would suggest to make it stable at 2T and then move to 1T.

ProcODT normaly is good around 28.2-36.9 need to figure out what works for you.
Around 1.5-1.55v RTT 7/3/3, 6/3/3 or 6/2/4 should work.
And for Cad bus 32GB 40/20/30/24, 40/20/24/24 or 40/24/24/24 are often used.

Here this as example for you, thats my max daily able settings.
1.55v


----------



## Leftezog

Hello guys. What are your thoughts primarily on error 0 and 15? Timings are super loose for 2733 for this kit and they are on docp auto. I only changed ProcODT/RTT/CAD BUS things. Also this is a ss passing 2667 successfully


Spoiler: 2667 pass






















 Starting dropping errors after 2h40m mark.


----------



## Veii

Imprezzion said:


> Oof. I can't get my 5900X+B550 XE to POST with 3600C14. It just loops 0D post code and I have to CMOS CLR as it won't even trigger a RAM OC failed safe mode.
> 
> 
> Imprezzion said:
> 
> 
> 
> Nah 1.60v vDIMM. It failed after 28 minutes Absolut. Error #6 I believe
Click to expand...

Why don't you just
like
go back 1 page, before asking for hand delivery 








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
 

Current ASRock does focus on following everything perfectly on AM4 ~ which in this case gives them no issues, but on every other case is just booring to work with Even though I agree it can be boring for some, I like such business model :) Just curious, is it for the same reason 1.2.0.4 fw not...




www.overclock.net




You where even active at page 745 , 746 and on the same 747
Answer was right infront of you the last two posts of mine

These kits hard-crash at 1.6v (unstable beyond 1.57), and RTTs + CAD_BUS training is non existent on asus boards on the latest bios
Not bad or "broken" (well kinda), simply non existent for DR
You have to force every little value away from Auto - else it messes up on it's own and doesn't even try to train

1T-56 missmatches IOL's
GDM missmatches IOL's

With these Mosfets, you also might want to run Extreme mode, full phase digi+ mode
It's plenty for a 5900X
Loadline 4 for me was needed, for you likely 3
Such VID to TEL voltage difference (VID to SVI2) ~ mismatching you can configure with/on CTR free
* your loadlines


Leftezog said:


> I only changed ProcODT/RTT/CAD BUS things


Are you sure about that ?















^ wrong, vs correct
Either the board, or you did missjuggle SDs and DD's


Leftezog said:


> Starting dropping errors after 2h40m mark.


#15 in this case, can also mean unstable CPU ~ because #15 can mean anything
(Unit can have transient issues by going from full load to idle ~ while doing CRC checks on memory)
Keep it how you have, and let y-cruncher loop for 72min, soo 4 cycles or more
Key combination 1-7-0

#0 can mean lack of voltage
soo both together can mean, voltage stability issues by heat (faster discharge) *
Either by PSU or just unstable CPU to begin with
* such has to be fixed by 10mV more, if not ~ it's not the DIMMs but either the board or the PSU/CPU


----------



## Taraquin

Akex said:


> It didn't do anything, I don't understand how I was able to make 3h TM5 stable, save the profile, shut down the PC for 3800Mhz test, then reboot the next time by reloading the 3733Mhz profile, nothing stable anymore ....


My guess is that several timings were on auto and training good at 3800, then trained bad at 3733. You may need to find highest manual tune stable, then up speed. For safeing 3800 RCDRD 20, RC 60, RFC 600 is a good bet. Booting 3733 or 3800 on the slightly improved IMC of Raven ridge (it worse than Zen+) is an achievement by it's own  As I said earlier the 2400G I build with same ram as you stopped at 3533.


----------



## Akex

Taraquin said:


> My guess is that several timings were on auto and training good at 3800, then trained bad at 3733. You may need to find highest manual tune stable, then up speed. For safeing 3800 RCDRD 20, RC 60, RFC 600 is a good bet. Booting 3733 or 3800 on the slightly improved IMC of Raven ridge (it worse than Zen+) is an achievement by it's own  As I said earlier the 2400G I build with same ram as you stopped at 3533.


At 3800Mhz it was totally unstable, and after a quick test on the RTT resistors without success I went back to 3733Mhz on the profile recorded in the bios.

What I did, I try to reproduce the situation when TM5 was stable 3H +

XMP + 3666Mhz> Save and reboot> BIOS> 3733Mhz> Save and reboot> Windows> TM5.

I left it turned before going to bed, passing vDIMM on 1.4v vs 1.48, there was better compared to all the tests done during the day.










Now I still have to understand where error 2 comes from, I'm sure I'm not far from maintaining total stability, I still have to locate what is causing my problem.

If I look at @Veii Doc it's either vDIMM or bad resistor.

For resistances, I have practically all tried, if not all. For vDIMM I did from 1.4v to 1.5v the same no positive results.

RCDRD 20, RC 60, RFC 600 was tested too, same result, I don't think it's a timing issue, at least not the ones visible in the bios / zentiming.

As it stands, I still have the DrvStrs to try ...

@Veii you who did the google doc, what do you think if you have 5min to check?

Thank you @Taraquin for your interventions, I take note of all


----------



## Veii

Akex said:


> @Veii you who did the google doc, what do you think if you have 5min to check?


tCKE technically belongs to a voltage issue
#2 can be many things sadly
Timing isuses i can see ~ even without TM5 spilling an error
tFAW too high (4* tRRD_S or tRRD_S * tCCD_L), tRFC too high, tRRD_L too high, tCKE too high
tRAS too low or too high, 36 or 42, pick one
tRC too high ,likely rev.E needs value 3 or higher on tWRRD
oh yes indeed ~ tCWL = -2 of tCL. tRDWR will need +2 of the baseline value. The baseline value being 8 for 2x8 could be correct, but be entirely sure value 9 (+2 = 11) won't be the issue

"high timings" do not mean stable timings
High values can very well be the issue of an error
especially ones like tRDWR & tRRD_ can very well be unstable at higher values

#2 reads "something ends too quickly"
Meaning it is either a timing that is too long, a timing that get's timebroken and ends too early , or another timely based timing
Soo this is,
(tFAW, tCKE, tRC, RTT_NOM, RTT_WR, tWR, SETUP Timings)

EDIT:
I personally feel it's just tCKE, and that too strong RTT_PARK + too strong procODT
Neither procODT nor cLDO_VDDP ~ should be responsible for powering the dimms
RTT_PARK too strong, and zero ClkDrvStr powering
Swap them around and start with a lower tCKE or with value 1 if you don't know what to pick
Shenanigans testing sheet has some values for you to try on CKE
6-8 will work , not higher than 8 while 8 could be too high, i think


Veii said:


> too strong procODT


Usually yes, but i didn't see Zen1
This is fine for 14nm, not so much for 12nm
(haven't heard for AF G series, soo you should be fine sorry) ~ but the point stands

Use ClkDrvStr for powering,
Fix the far to high timings and find the correct tCKE or don't use it at all (1)

EDIT2:
What tCCD_L JEDEC rating did this kit get
Value 6 or Value 7?


----------



## Akex

Veii said:


> tCKE technically belongs to a voltage issue
> #2 can be many things sadly
> Timing isuses i can see ~ even without TM5 spilling an error
> tFAW too high (4* tRRD_S or tRRD_S * tCCD_L), tRFC too high, tRRD_L too high, tCKE too high
> tRAS too low or too high, 36 or 42, pick one
> tRC too high ,likely rev.E needs value 3 or higher on tWRRD
> oh yes indeed ~ tCWL = -2 of tCL. tRDWR will need +2 of the baseline value. The baseline value being 8 for 2x8 could be correct, but be entirely sure value 9 (+2 = 11) won't be the issue
> 
> "high timings" do not mean stable timings
> High values can very well be the issue of an error
> especially ones like tRDWR & tRRD_ can very well be unstable at higher values
> 
> #2 reads "something ends too quickly"
> Meaning it is either a timing that is too long, a timing that get's timebroken and ends too early , or another timely based timing
> Soo this is,
> (tFAW, tCKE, tRC, RTT_NOM, RTT_WR, tWR, SETUP Timings)
> 
> EDIT:
> I personally feel it's just tCKE, and that too strong RTT_PARK + too strong procODT
> Neither procODT nor cLDO_VDDP ~ should be responsible for powering the dimms
> RTT_PARK too strong, and zero ClkDrvStr powering
> Swap them around and start with a lower tCKE or with value 1 if you don't know what to pick
> Shenanigans testing sheet has some values for you to try on CKE
> 6-8 will work , not higher than 8 while 8 could be too high, i think
> 
> Usually yes, but i didn't see Zen1
> This is fine for 14nm, not so much for 12nm
> (haven't heard for AF G series, soo you should be fine sorry) ~ but the point stands
> 
> Use ClkDrvStr for powering,
> Fix the far to high timings and find the correct tCKE or don't use it at all (1)
> 
> EDIT2:
> What tCCD_L JEDEC rating did this kit get
> Value 6 or Value 7?


Thank you for your recommendation.
Bench in progress will see in a few hours.

For tCCD_L I have 7


----------



## sonixmon

Veii said:


> Why don't you just
> like
> go back 1 page, before asking for hand delivery
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Current ASRock does focus on following everything perfectly on AM4 ~ which in this case gives them no issues, but on every other case is just booring to work with Even though I agree it can be boring for some, I like such business model :) Just curious, is it for the same reason 1.2.0.4 fw not...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> You where even active at page 745 , 746 and on the same 747
> Answer was right infront of you the last two posts of mine
> 
> These kits hard-crash at 1.6v (unstable beyond 1.57), and RTTs + CAD_BUS training is non existent on asus boards on the latest bios
> Not bad or "broken" (well kinda), simply non existent for DR
> You have to force every little value away from Auto - else it messes up on it's own and doesn't even try to train
> 
> 1T-56 missmatches IOL's
> GDM missmatches IOL's
> 
> With these Mosfets, you also might want to run Extreme mode, full phase digi+ mode
> It's plenty for a 5900X
> Loadline 4 for me was needed, for you likely 3
> Such VID to TEL voltage difference (VID to SVI2) ~ mismatching you can configure with/on CTR free
> * your loadlines
> 
> Are you sure about that ?
> View attachment 2535042
> View attachment 2535043
> 
> ^ wrong, vs correct
> Either the board, or you did missjuggle SDs and DD's
> 
> #15 in this case, can also mean unstable CPU ~ because #15 can mean anything
> (Unit can have transient issues by going from full load to idle ~ while doing CRC checks on memory)
> Keep it how you have, and let y-cruncher loop for 72min, soo 4 cycles or more
> Key combination 1-7-0
> 
> #0 can mean lack of voltage
> soo both together can mean, voltage stability issues by heat (faster discharge) *
> Either by PSU or just unstable CPU to begin with
> * such has to be fixed by 10mV more, if not ~ it's not the DIMMs but either the board or the PSU/CPU


@Veii You mentioned 1T-56 missmatches IOL's so do you recommend 2T if 1T Pure is a no go? I have not had time to really dive in to serious ram testing so I currently have it 1 hr Aida64 and "gaming" stable. I'm thinking maybe I should move to 2T before continuing? TIA


----------



## Veii

Akex said:


> Thank you for your recommendation.
> Bench in progress will see in a few hours.
> 
> For tCCD_L I have 7


Soo tRAS = tRCD*2+ 7
tFAW = tRRS_S * tCCD_L

then later tCWL = tCL & you see how low you can drop tRDWR
That is your value for go-to and if you want to go tCWL = tCL -2, then tRDWR needs +2 

Important is tRC = tRP+tRAS 
and tRAS either tRCD*2, same thing but + 7, or just tRCD+tRTP
Just rev.E doesn't like it much, it requires everything to be perfect


----------



## Audioboxer

sonixmon said:


> @Veii You mentioned 1T-56 missmatches IOL's so do you recommend 2T if 1T Pure is a no go? I have not had time to really dive in to serious ram testing so I currently have it 1 hr Aida64 and "gaming" stable. I'm thinking maybe I should move to 2T before continuing? TIA
> 
> View attachment 2535057


What is your tPHYRDL on both sticks? Is it 28/28 or 28/26? If you're 28/28 that's fine, focus on timings now.

tRAS to 26 so you have tRC = tRAS + tRP. tCKE can probably run at 1 fine. tFAW should be 16. tRTP can come down to 7 so tWR = tRTP x 2. tWTRL to 10 or 12. tWTRS to 4. tRRDL can probably drop to 4. tRDRDSD and tRDRDDD to 4. tWRWRSD and tWRWRDD to 6.

Obviously maybe not do that all at once unless you want to have no clue what might not be stable lol. You could also work on the secondaries first at 2T before switching back to 1T.

*edit* - I missed it but please change that VSOC asap, absolutely crazy figure lol. 1.55v! 1.125~1.15v will be enough. I don't want to scare you but I would think a VSOC that high could even cause damage.


----------



## Veii

sonixmon said:


> @Veii You mentioned 1T-56 missmatches IOL's so do you recommend 2T if 1T Pure is a no go? I have not had time to really dive in to serious ram testing so I currently have it 1 hr Aida64 and "gaming" stable. I'm thinking maybe I should move to 2T before continuing? TIA
> 
> View attachment 2535057


Whatever remains stable for you and then optionally doesn't misstrain
I can just say this should not be stable, as tRC is too low

Such thing as gaming stable doesn't exist
Nor Aida stable
The CPU which you test with y-cruncer and OCCT, is another topic
There maybe Aida's stress tests are reasonable for something


----------



## Leftezog

Veii said:


> Are you sure about that ?
> View attachment 2535042
> View attachment 2535043
> 
> ^ wrong, vs correct
> Either the board, or you did missjuggle SDs and DD's
> 
> #15 in this case, can also mean unstable CPU ~ because #15 can mean anything
> (Unit can have transient issues by going from full load to idle ~ while doing CRC checks on memory)
> Keep it how you have, and let y-cruncher loop for 72min, soo 4 cycles or more
> Key combination 1-7-0
> 
> #0 can mean lack of voltage
> soo both together can mean, voltage stability issues by heat (faster discharge) *
> Either by PSU or just unstable CPU to begin with
> * such has to be fixed by 10mV more, if not ~ it's not the DIMMs but either the board or the PSU/CPU


The SDs and DD's are totally on auto I haven't touched them. Does that mean the motherboard sets them incorrectly on default? Must the SDs be higher or equall to DD's and not the opposite? In the 2667 frequency although they were the same as 2733 it passed 1usmus 30 cycles and anta extreme presets. Also did Ycruncher 4 passes as you told and passed.



Spoiler: ycruncher pass















I will reverse manually the SDs and DD's, raise the vdimm to 1.36v from 1.35v and try again. Thanks man for your reply.


----------



## tcclaviger

So I finally actually took a look at the online calculator after having a random error 4 and 14 creep in with TM5, but only on 1usmus v3 preset (and only after a large number of passes), changed a couple of values, got no more errors in testing. On a whim I wondered if it would now take 1966/3933 and low and behold:








@Veii thanks for the work you've done, really appreciate it. Going under TM5 now to text for errors here.


EDIT: 1966/3933 turned out to be flakey posting, so I grew even more curios, and it turns out it's true, once GDM off 2T is tuned just right, it transfers right over to 1T GDM off. I never thought this was possible tbh, just took a tiny bit more voltage here and there and setup values, VDIMM same at 1.57 SET.


----------



## sonixmon

Audioboxer said:


> What is your tPHYRDL on both sticks? Is it 28/28 or 28/26? If you're 28/28 that's fine, focus on timings now.
> 
> tRAS to 26 so you have tRC = tRAS + tRP. tCKE can probably run at 1 fine. tFAW should be 16. tRTP can come down to 7 so tWR = tRTP x 2. tWTRL to 10 or 12. tWTRS to 4. tRRDL can probably drop to 4. tRDRDSD and tRDRDDD to 4. tWRWRSD and tWRWRDD to 6.
> 
> Obviously maybe not do that all at once unless you want to have no clue what might not be stable lol. You could also work on the secondaries first at 2T before switching back to 1T.
> 
> *edit* - I missed it but please change that VSOC asap, absolutely crazy figure lol. 1.55v! 1.125~1.15v will be enough. I don't want to scare you but I would think a VSOC that high could even cause damage.


Thats what that burning smell was.. Just kidding, that must have been a misread on ZenTimings because I freaked out when I saw that and opended ZenTimings and it is 1.118 (set to 1.125). The 1.55 is my Ram voltage which doesn't show up in ZenTimings for some reason, guess it plugged it in wrong on that scan.

It is 28/28 I haven't seen the 28/26 bug on this system. I Did have 26/26 once but it was a while ago and no idea why it is always 28 now.

Thanks for the tips I will play with these settings soon. I have read 1900 should have tcke @9, it does run at 1 but read even if it works at 1 still better at 9? I have no idea so just following what was recommended.



Veii said:


> Whatever remains stable for you and then optionally doesn't misstrain
> I can just say this should not be stable, as tRC is too low
> 
> Such thing as gaming stable doesn't exist
> Nor Aida stable
> The CPU which you test with y-cruncer and OCCT, is another topic
> There maybe Aida's stress tests are reasonable for something


I agree it isnt really stable, but for me I have found if system passes 1 hour Aida64 I do not get any crashes gaming. I know that is lame and not really stable but I don't do anything mission critical on this PC and have not had the time I used to in order to properly test OC. I could go back to stock or just OC mhz for the time being but I am hoping to have a few days coming up to really start testing. I will make above recommended adjustments and use some real testing software you pros use. 🤣 

I do get occasional cold boot training but 90% it posts first time. Probably related to my mismatched timings mentioned. 

Thanks guys!


----------



## Audioboxer

sonixmon said:


> Thats what that burning smell was.. Just kidding, that must have been a misread on ZenTimings because I freaked out when I saw that and opended ZenTimings and it is 1.118 (set to 1.125). The 1.55 is my Ram voltage which doesn't show up in ZenTimings for some reason, guess it plugged it in wrong on that scan.
> 
> It is 28/28 I haven't seen the 28/26 bug on this system. I Did have 26/26 once but it was a while ago and no idea why it is always 28 now.
> 
> Thanks for the tips I will play with these settings soon. I have read 1900 should have tcke @9, it does run at 1 but read even if it works at 1 still better at 9? I have no idea so just following what was recommended.
> 
> 
> 
> I agree it isnt really stable, but for me I have found if system passes 1 hour Aida64 I do not get any crashes gaming. I know that is lame and not really stable but I don't do anything mission critical on this PC and have not had the time I used to in order to properly test OC. I could go back to stock or just OC mhz for the time being but I am hoping to have a few days coming up to really start testing. I will make above recommended adjustments and use some real testing software you pros use. 🤣
> 
> I do get occasional cold boot training but 90% it posts first time. Probably related to my mismatched timings mentioned.
> 
> Thanks guys!


That's ok then! I don't even know if a bios can actually set VSOC to 1.55v lol.

I guess you could try VDDP up to like 0.95v to see if that drops you to 26/26, but I wouldn't worry about it as long as it's 28/28. When I go with even tCL pretty much everything runs at 28/28 with DR. Odd tCL and it's 26/26. Don't ask me why, just MSI things.

tCKE at 1 can technically be "faster" I believe to help memory response time, but higher values seem to be more about stability. If it helps at a higher value, that's fine, but if it runs and is stable at 1, put it to 1 I guess. I think to notice performance issues you'd need to go "too high".


----------



## sonixmon

Audioboxer said:


> That's ok then! I don't even know if a bios can actually set VSOC to 1.55v lol.
> 
> I guess you could try VDDP up to like 0.95v to see if that drops you to 26/26, but I wouldn't worry about it as long as it's 28/28. When I go with even tCL pretty much everything runs at 28/28 with DR. Odd tCL and it's 26/26. Don't ask me why, just MSI things.
> 
> tCKE at 1 can technically be "faster" I believe to help memory response time, but higher values seem to be more about stability. If it helps at a higher value, that's fine, but if it runs and is stable at 1, put it to 1 I guess. I think to notice performance issues you'd need to go "too high".


I made all the adjustments you recommended except tcke, I might change that later and do a couple of test runs. So far system posts fine and quick aida64 test. Long term testing causes heat which then errors out, I believe to do with temps, if my ram hits 44-45 and I don't want to water cool them (already have a ram fan which helps). I think temp issue is related to trfc which I have been incrementing up lately. 

When I imported XMP file from my ram, DRAM Calc says trfc 370 safe or 304 fast. Kind of working my way up to those and retesting. Hopefully in a few weeks I will be able to dedicate some real time for testing!


----------



## Blameless

Audioboxer said:


> I guess you could try VDDP up to like 0.95v to see if that drops you to 26/26, but I wouldn't worry about it as long as it's 28/28. When I go with even tCL pretty much everything runs at 28/28 with DR. Odd tCL and it's 26/26. Don't ask me why, just MSI things.


My kit of OEM Kingston HyperX 2x32GiB (Micron 16Gb E-die ICs) will reliably do 26/26 at 3666, but needs at least 965mv VDDP to do so. Won't do any higher without dropping to 26/28 at any voltage, but since the 3950X I'm using it with can't reliably do more than 1833 FCLK anyway, it's not much of an issue.

Anyway, Samsung B-die is very different and sonixmon's setup probably won't see scaling that high, but it also shouldn't hurt to try up to ~1v or so, just to see if it does anything.


----------



## Blameless

Just spent all afternoon giving GDM disabled another go on my cheap Timetec CJR kit, which involved much CMOS jumper switch use on this ASRock ITX board that has the worst failed memory settings recovery I have ever seen.

This is GDM _enabled_, 24/7 stable settings, with 1.28 vDIMM:









_Edit_, updated image I ran with identical firmware, subs, and PBO curves as the 2T run below it:









This is the best I can do with 2T GDM _disabled,_ which needs 1.35 vDIMM and is probably too hot to be completely stable:









The GDM disabled settings are also slightly slower in most real-world, memory dependent apps. It's about 0.5 GFLOPs from matching the GDM enabled settings in 7-zip 21.06, for example.

With GDM _off_, tRDWR 8 will not POST at all and tWRWRSD 6 (matching the SD and DDs at 7 doesn't help performance). needs about 50mV extra (1.4v) to be stable, which is a complete no go for two temperature-sensitive bare DIMMs in adjacent slots inside a Lian-Li TU150 with a 375w, air cooled, 6800 XT right under them.


----------



## Taraquin

Blameless said:


> Just spent all afternoon giving GDM disabled another go on my cheap Timetec CJR kit, which involved much CMOS jumper switch use on this ASRock ITX board that has the worst failed memory settings recovery I have ever seen.
> 
> This is GDM _enabled_, 24/7 stable settings, with 1.28 vDIMM:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This is the best I can do with GDM _disabled,_ which needs 1.35 vDIMM and is probably too hot to be completely stable:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> The GDM disabled settings are also slightly slower in most real-world, memory dependent apps. It's about 0.5 GFLOPs from matching the GDM enabled settings in 7-zip 21.06, for example.
> 
> With GDM on, tRDWR 8 will not POST at all and tWRWRSD 6 (matching the SD and DDs at 7 doesn't help performance). needs about 50mV extra (1.4v) to be stable, which is a complete no go for two temperature-sensitive bare DIMMs in adjacent slots inside a Lian-Li TU150 with a 375w, air cooled, 6800 XT right under them.


Your 2T setup has wrwrsd at 7 and rdwr at 9 vs 6 and 8 on gdm. These 2 can explain the performance. Try if 2T can run them at 6 and 8? On 2T try 18/9 wr/rtp. Cwl at 18 might lower voltage requirements, try tRFC 480, 496 or 512, might work. 

Generally CJR is a pain to tweak due to weird voltage and tempscaling. I really prefer B-die, Micron rev E/H/B and Hynix DJR, they are easier to work with.


----------



## mongoled

PJVol said:


> IMHO it's not just a form-factor, but the fact that many ITX boards are built on 6-8 layer PCB with overly powerful VRM design, especially those on B550.
> My MSI office board is ITX as well, but it can hardly help anything.


Well yeah, its never going to be one thing



Im simply going on the "numbers" we see here at OC.net and at other online resources.

There are far more ITX boards pushing the flat 14s @3800/1900 then there are non ITX boards, and of course there are far more non ITX boards that are being used.

These basic facts point to ITX boards being more flat 14s friendly, never mind taking into account the physics when accounting for electrical signals travelling on shorter boards etc etc ...


----------



## Blameless

Taraquin said:


> Try if 2T can run them at 6 and 8?


I did and thought I mentioned it, but I typoed and said GDM on when I meant off. I'll correct that now. Thanks for the catch.

Anyway, rdwr 8 won't boot on 2T, while wrwrsd needs a major voltage bump.



Taraquin said:


> On 2T try 18/9 wr/rtp.


This is slower and doesn't significantly alter the voltage I can use.



Taraquin said:


> Cwl at 18 might lower voltage requirements, try tRFC 480, 496 or 512, might work.


I'll give tCWL 18 a shot later to see if that helps, but tRFC is already very near it's limit. 520 is fully stable, but I don't think 512 is, and below 500 won't boot.



Taraquin said:


> Generally CJR is a pain to tweak due to weird voltage and tempscaling. I really prefer B-die, Micron rev E/H/B and Hynix DJR, they are easier to work with.


Oh, I agree. However, this stuff isn't performing all that badly considering it was $120.

I have some Samsung 16Gb A-die DIMMs that are even worse in these regards. Temperature sensitive, weaker DIMM won't POST past 1.32v, stops scaling at all with GDM disabled past 3333MT/s, performs the same or better with GDM On than 2T, even when all other timings are completely identical.


----------



## Audioboxer

sonixmon said:


> I made all the adjustments you recommended except tcke, I might change that later and do a couple of test runs. So far system posts fine and quick aida64 test. Long term testing causes heat which then errors out, I believe to do with temps, if my ram hits 44-45 and I don't want to water cool them (already have a ram fan which helps). I think temp issue is related to trfc which I have been incrementing up lately.
> 
> When I imported XMP file from my ram, DRAM Calc says trfc 370 safe or 304 fast. Kind of working my way up to those and retesting. Hopefully in a few weeks I will be able to dedicate some real time for testing!


Going over 42 degrees is the point I could start seeing some errors with a low tRFC. Yup, that "low". I needed a 120mm fan at 100% RPM to keep my TM5 testing to 40~41 degrees before I went to watercooling. This was with RipJaws heatsinks mind you, the absolute worse heatsinks in existence on DDR4.


----------



## Veii

If you guys figure out more #2 error data ~ please let me know
There is close to zero holding point on that one specific

Same for lack on #10
While it is requiring more RTT_NOM , as CKE (ripple) issue on higher voltage
Soo to speak "burst voltage test" ~ it's lacking information on how to fix it as "standalone" issue
~ sadly mostly comes together with #0 or with #2. Also sadly #2 has no holding point to fix both

Generally updating Error logs slowly
@PJVol if you have more findings, also let me know. Added your #13 reason
Couldn't replicate yet, but it will be helpful to somebody for sure

Also PJVol, i listened on tRFC2/4 rounding issues
Reason is, that it was now replicable and matches DR JEDEC
~ still WIP, but there are specific scenarios where it matches and is needed
Still marked as WIP/DEBUG, because on the contra side ~ there are specific times where this does not match reality.
Anywho both options are there ~ ty for the finding, back then
==========
Sneak Peak













~ sub average sample, unlucky ~ BG 2143 SUS = guanteed Rev.02 (2139 is not)
~ likely lack of bios support, it's overvolted too much again

CTR & Hydra lack support for B2 ~ but that's fixed now, just not upstream yet
It's Microcode 00A20F*12h* not *10h*
Sadly requires new SMU ~ AMD OC commands/menu don't go through, mailbox do
Requires 1.2.0.5 and final microcode, not reviewer one but works since 1.1.0.0D








More data about DPM and WHEA , to follow
First having to figure out #2 error on DR & then check silicon voltage scaling
* If there are any significant behavior changes ~ i'll open a thread for B2 owners.
Have it only for 3 more days ~ can't promise much debugging


----------



## PJVol

*@Veii *
Can't say for #2's and #13's right now (will look into it), but it seems you were pretty spot on about #11 and wrong CAD BUS.
Here is what I did to get rid of them:








When RED's were set, got caught two #11's - in the 1st and 2nd cycle, then two #11's and two #6's in a 4th cycle after which I stopped tm5.
When auto'ed them - ran at least 5 cycles errorless.
Wondering, which of those three helped (Clk, AddrCmd, Cke) ?



Veii said:


> i listened on tRFC2/4 rounding issues


woulda go on more in detail? Cause I've heard those are not used by modern amd MC.


----------



## Audioboxer

Time to drain my loop and get this riser cable switched over, wish me luck. The cable needs changed anyway but I'm hoping this stops the PCIe voltage drops! Will come back with results when I can.


----------



## mongoled

Audioboxer said:


> Time to drain my loop and get this riser cable switched over, wish me luck. The cable needs changed anyway but I'm hoping this stops the PCIe voltage drops! Will come back with results when I can.


My PCIe 4.0 riser cable along with 3070 should be here soon also.

I'm going to run everything default first to get readings/scores before I move to the cable and waterblock

Good luck

😃


----------



## Audioboxer

Good news: Cable works fine and I haven't caused any leaks

Bad news: Air bubbles throughout the loop again and...










It's not the cable 

PCIe 12v input still dropping below 12v. I guess I'll overclock and see if I get any crashes, but looks like I'll need to tell Amazon my PSU is faulty.

Oh, and 15cm is the perfect size for a Lian Li O11 XL, at least that worked out!

Some interesting responses in here

__
https://www.reddit.com/r/overclocking/comments/mugpcw

and here 3080 + 3090 unstable, PCI-E voltage drop?

I'm essentially trying to figure out if it's the PSU or the board. Given the B550 Unify X has some monster VRMs I'd be reluctant to think it was the board? Unless I have something setup wrong in the BIOS. As I said previously the only other PCIe device I have connected is a SSD. Fair enough it's a fast one, Corsair MP600 Pro, but everyone needs storage connected to their computer lol, that shouldn't cause power delivery issues under load.

I'm going to test PBO off just to see what happens. The good news is my 8 pins seem to be holding up reasonably well.

*edit *- PBO on or off changes nothing.


----------



## Taraquin

mongoled said:


> Well yeah, its never going to be one thing
> 
> 
> 
> Im simply going on the "numbers" we see here at OC.net and at other online resources.
> 
> There are far more ITX boards pushing the flat 14s @3800/1900 then there are non ITX boards, and of course there are far more non ITX boards that are being used.
> 
> These basic facts point to ITX boards being more flat 14s friendly, never mind taking into account the physics when accounting for electrical signals travelling on shorter boards etc etc ...


Could it be also due to 2 dimm itself vs 4 dimm? All ITX has 2 dimms, and it is known to get higher speeds vs 4 dimms.


----------



## Imprezzion

Well, I got 3800 C15 2T to work fine for the first hour and a bit of TM5 Absolut.

I messed up quite a lot of settings in my haste of setting it up tho...
tRAS 28 doesn't make any sense.
VSOC is WAY too high.
Forgot to set up tWTR_S and L..
Oh well.
For some reason this ASUS board just simply does not have any vDIMM readout in both ZenTimings and HWINFO64 so probably not even a sensor for it. It's 1.500v. DIMM temps ~45c ish. Fans on very low speed. I have a 120mm aimed at the RAM but it was at like 520 RPM so doesn't do much at that point.










DIMM's can't do 1T GDM C14 so I have to either run 2T C15 or 1T GDM C16 and this benches higher numbers so.


----------



## hazium233

@Imprezzion


Can RDWR and WRRD come down? RDWR is pretty high, CL is only one t above CWL. Would imagine 9 or 10 there should work, as long RDWR isn't masking problems with primaries.

WRRD goes down as difference between CL and CWL grows, and so 2 to 4 should probably work.


----------



## Imprezzion

hazium233 said:


> @Imprezzion
> 
> 
> Can RDWR and WRRD come down? RDWR is pretty high, CL is only one t above CWL. Would imagine 9 or 10 there should work, as long RDWR isn't masking problems with primaries.
> 
> WRRD goes down as difference between CL and CWL grows, and so 2 to 4 should probably work.


Well. I messed up something adjusting those recommended values. Stuck on code 1F now and didn't save previous settings in a profile. Barf.
Well, time to clear CMOS and copy the settings from my screenshot again.. no clue which timing I set too low lol. Now let's actually remember to set a profile so I can at least recover the BIOS settings easier. This board does not really like faulty RAM OC and doesn't usually go into safe mode POST. Is there a way to force it to go into safe mode POST without clearing CMOS?

EDIT: fixed. Too low tWTR_L was the problem. It will not go under 14. _S on 4.

Btw, is 1usmus default V3 supposed to be such a short runtime? It completed the full TM5 test in like what, 18 minutes? 3 cycles? I'm used to Anta's configs which take like 50 minutes for 1 cycle.


----------



## Yuke

Anyone got the definitive answer to the question whether tRCDWR and tRCDRD are linked values or not? Like does it make sense to set WR to 8 or 10 or does it get autocorrected to the RD value anyways?

If i set WR to 8 i get errors (maybe autocorrect related)..10 is stable but is performing indentical to 16 (set value of RD)

thanks


----------



## PJVol

Taraquin said:


> All ITX has 2 dimms


Mine has four.



Yuke said:


> Anyone got the definitive answer


Hardly anyone can answer the 1st question, unless he wrote memory controller part of the firmware, but I already showed here, how it affects some benchmark results when set to its minimum (8), in my particular PC config (actually two PC's were involved).


----------



## Yuke

PJVol said:


> Hardly anyone can answer the 1st question, unless he wrote memory controller part of firmware, but I already showed here, how it affects some benchmark results when set to its minimum (8), in my particular PC config (actually two PC's were involved).


Hey, are those results posted far back? I went through your message feed but stopped at around 10 days, lol. What benchmark did you use to see differences between 8 and stock values?


----------



## PJVol

Yuke said:


> Hey, are those results posted far back?


The latest - not so far, maybe in a couple of months, lol. Don't remember which tests exactly - there were a bunch.


----------



## hazium233

Imprezzion said:


> Btw, is 1usmus default V3 supposed to be such a short runtime? It completed the full TM5 test in like what, 18 minutes? 3 cycles? I'm used to Anta's configs which take like 50 minutes for 1 cycle.


Most people on here will edit the config file so that it runs 20-25 cycles.

Alternatively, you could change the time field from 100 up to 400-500 or so. That will increase the time for each test / cycle.


----------



## TimeDrapery

Damn it Gigabutt!

1.5V set, 1.57V get

Otherwise this switch to a mini-ITX board is working out well... I'm the one that keeps buying Gigabyte products


----------



## Blameless

PJVol said:


> Wondering, which of those three helped (Clk, AddrCmd, Cke) ?


I'd be very surprised if it was Cke...with a tcke of zero being stable and power down disabled, cke probably isn't being trigger often, if at all.

A stronger clock drive strength (lower output impedance is a stronger drive, faster rise, but more potential for overshoot) seems likely to be beneficial at 2200MHz. AddrCmd being slightly weaker is also possibly beneficial. It could well be a combination of them, but if I had to pick one as being most likely, it would be Clk.



hazium233 said:


> Most people on here will edit the config file so that it runs 20-25 cycles.
> 
> Alternatively, you could change the time field from 100 up to 400-500 or so. That will increase the time for each test / cycle.


I prefer using more cycles rather than longer cycles as it doesn't seem to make the test appreciably less stressful while keeping a usefully fine granularity.


----------



## ManniX-ITA

Yuke said:


> Anyone got the definitive answer to the question whether tRCDWR and tRCDRD are linked values or not? Like does it make sense to set WR to 8 or 10 or does it get autocorrected to the RD value anyways?
> 
> If i set WR to 8 i get errors (maybe autocorrect related)..10 is stable but is performing indentical to 16 (set value of RD)


Same as @PJVol can confirm there are a number of benchmarks, don't recall which ones, where you can see the gains. I would try OCCT.
Of course we are talking about write or combined performances; that's why it's more difficult to observe, most benchmarks scores are based upon read performances.
I think GDM does auto-correct it, if an odd number.

From my experience if you get errors is because of tWRRD/SCL.
tWRRD * SCL <= tRCDRD; not sure in which conditions but this is true for tRCDWR as well
High tWR/tRP usually helps without cost.
I'm running tRCDWR at 8 now but with tWR 16 and tWRRD at 1 and SCL at 4.


----------



## Veii

TimeDrapery said:


> Otherwise this switch to a mini-ITX board is working out well... I'm the one that keeps buying Gigabyte products


You should go with an DMM on them.
I can recall clearly all the X399/B350/B450/X370/X470 - overvoltage issues, on vcore
* yes they where that many ~ out of this list 2-3 boards where unaffected
It so happened that instead of 1.2v vcore, you got 1.3v send. Same for SOC on HEDT

Soo pure blind trust on VDIMM i wouldn't really give.
I mean, PCB failures and DIMM/IC failure points ~ voltage wise appear to be pretty much on point, every single time (with a deviation of 20ish mV)
Soo just ignore VDIMM ~ like i've been starting doing and work around it

If for example you have a bad DIMM PCB that only runs 1.58 at very specific scenarios
The same PCB can run 1.65v at very specific RTT_WR & PARK scenarios
And ontop of that, the mainboard layering will differ between users (sadly still unenforced, only minimums are enforced) ~soo your voltage "values" barely help anybody
The only part where it might help is "how do you cool it, what heatsinks does the dimm have, how does powering look like"
VDIMM on it's own, unimportant 
even more, when for example







runs from 1.45-1.53
While
625 runs from 1.57-1.63? somewhere near 1.62 / stable & still match the same dimm temp

It really doesn't matter much, because either user will be able to run RTTs or his VDIMM was too low to begin with. Oor the Board PCB just leaky
Don't worry too much, but if you can find a DMM ~ clear us up


Yuke said:


> If i set WR to 8 i get errors (maybe autocorrect related)..10 is stable but is performing indentical to 16 (set value of RD)


The only thing you can clearly confirm is, that they are used ~ independent of what old forums have told
PJVol phrases it well

Only an engineer at AMD can confirm what at X time of moment is supported and what is not
Same goes for tRFC2/4 usage
As long as it spills out errors ~ it's used in some way / shape / or form
Yet i can see 2X & 4X being temp dependent are not used "yet".
remain tMRD and DIMM-Vendor values (the changes by missmatching tRFC2/4) in the hidden are used ~ else it wouldn't show events where it errors

Only downside @PJVol on this story is
They only follow JEDEC
People where "forced" bit back on intel platforms , to play with 2/4 , increase/decrease it's scaling & got performance out
But as tREFI is fixed-autocalculated, same for IOL's ~ i don't think it makes much sense to bring such big variable of instability into it
Soo following JEDEC at best does not do anything special ~ at worst does not introduce random errors by it being wrongly predicted by the bios

tCKE same thing
It's "not only" there for powerdown control ~ while PDM has 2 modes aggressive and normal (auto set by FW)
And it clearly is used as variable
If you don't want powerdown, instead of auto ~ disable it , soo Aggressive one is gone too
But it still doesn't make tCKE a non functional value ~ as of this current FW state (well honestly since november 2020 Vermeer it was a thing)
Things change, and only AMD will know ~ till something is clearly behaving different than it was before.
It makes more sense to complain about no changelogs 


Imprezzion said:


> Well. I messed up something adjusting those recommended values. Stuck on code 1F now and didn't save previous settings in a profile. Barf.


What too often happens for me, is forgetting tCWL 
when going from 14-14 , 14 tCWL , 8 tRDWR
To 15-15 , 14 tCWL. Then 8 tRDWR hardlocks and it refuses to post. It needed +1
Same event happens by forgetting tCWL for example staying "too high"
I've seen Asus boards bypass user input and fix it, but on ASRock's board they do not
Yet both follow what you put in. Soo if you put nonsense and forget tCWL ~ no Auto CMOS system will help you 

Bad tCL some bioses can recover
Bad tRDWR i've not seen a single system that can recover. It just hardlocks before even trying to post


PJVol said:


> woulda go on more in detail? Cause I've heard those are not used by modern amd MC.


According to specs i've read
tRFC is calculated "from" tRFC2 , not the opposite
tRFC 2/4 where/are used for tMRD, tMOD, tMODPDA calculation and changes. GDM does influence these values too
There where more but i don't remember anymore.
Only 2X 4X refresh is not used "yet". But as it keeps showing errors, in some shape/way/or form it is used. At least causes issues if you/the board puts in something stupid
==============================
WHEA at 3800 doesn't sound promising







Voltages scale different as it seems
900-960-1040-1100
Nor
900-980-1050-1125 it is
Silicon is buggy with CO's it overvolts. Without CO's it's balanced but slow , well and hot ^^'
Thermal density is quite high, unsure why. KPx + Alphacool Pro @ 2500RPM can not cool 200W for some reason.
==============================
FCLK_EFF_FREQ still jumps to 2000-2100 FCLK
Baseline is current FCLK. And only does it by going on the 2nd CCD
Something overdrives internally. Last sample jumped to 2600 FCLK but had other existence problems. 

Haven't found a way to disable this behavior yet ~ but 1CCD units shouldn't have this. At least mine didn't.
I can see tho how jumping to 2600FCLK and higher, can indeed cause random errors to pop up









This to Zero , forces cores to throttle strongly
This to 666 or -666 bugs it out and removes one throttler ~ yet not permanent and only forbits CPU_LATCH voltage to be influenced by FIT_PRE-V
FIT-PRE-V still will throttle PPT and by "FIT" reason, artificially
But CCA throttle is gone afterwards. Sadly again, doesn't stick on reboot, but so you know for personal OC tools
PPT throttle is not THM related nor cTDP or global package wattage.
It this time also isn't prochot related (kinda) ~ but THM and ProcHot are locked at 90c, without any ability to override any of both

CBS / PBO settings 4096-600-600 will run , yet here it might need to be EDC limited
It alone hard-throttles at 219A draw ~ while on stock having 190A as limits
some bioses are stuck at 550A TDC and 500A EDC. Soo they might not accept and refuse to accept values higher than that (reset/ignore user input)

Generally it lacks 1.2.0.5 AGESA for full functionality, soo i hope Vendors hurry up 
Speaking off,
You guys don't have any contact to ASUSTechMKTJJ (u/ASUSTechMKTJJ) - Reddit (well or shamino) ?
I lost contact to him , but would require an Alpha 1205 bios for this Rev.02 sample


----------



## mongoled

Audioboxer said:


> Good news: Cable works fine and I haven't caused any leaks
> 
> Bad news: Air bubbles throughout the loop again and...
> 
> View attachment 2535227
> 
> 
> It's not the cable
> 
> PCIe 12v input still dropping below 12v. I guess I'll overclock and see if I get any crashes, but looks like I'll need to tell Amazon my PSU is faulty.
> 
> Oh, and 15cm is the perfect size for a Lian Li O11 XL, at least that worked out!
> 
> Some interesting responses in here
> 
> __
> https://www.reddit.com/r/overclocking/comments/mugpcw
> 
> and here 3080 + 3090 unstable, PCI-E voltage drop?
> 
> I'm essentially trying to figure out if it's the PSU or the board. Given the B550 Unify X has some monster VRMs I'd be reluctant to think it was the board? Unless I have something setup wrong in the BIOS. As I said previously the only other PCIe device I have connected is a SSD. Fair enough it's a fast one, Corsair MP600 Pro, but everyone needs storage connected to their computer lol, that shouldn't cause power delivery issues under load.
> 
> I'm going to test PBO off just to see what happens. The good news is my 8 pins seem to be holding up reasonably well.
> 
> *edit *- PBO on or off changes nothing.


Did you test without the riser cable ??

As that should be the first test you run, gfx card inserted directly into the first PCIe slot and then run your tests ...


----------



## Imprezzion

What determines how high, or rather how low, tWTR_L can go on this platform? I seem to be stuck at 14 and I'm used to Intel and controlling them through tWRRD but I'm not sure the relationship is the same on AMD. I used to run 29/25 tWRRD on 4400C17 for 7/2 tWTR but on this platform I'm stuck on 14/4 so far. Don't know off the top of my head what tWRRD was set to tho.


----------



## Veii

Imprezzion said:


> What determines how high, or rather how low, tWTR_L can go on this platform?


They are different
IO-L here are autopredicted, and based upon tCL, tCWL, tRDWR, tWRRD
You can only balance these 4
* well and RTTs which belong to powering

tWTR_L is based on dimm density and tRTP
both are based on the same thing
Match them.

Else do not match them and follow patterns of
3-8, 4-8, 5-10, 4-12, 5-14
14 is the max sadly and 2 is the min, but they could've allowed 1 tbh.

tRAS 21 is min, but 20 runs on reviewer bioses, they could've allowed 20 tbh.
If you match tWR = tRTP *2 , then tWTR_ is "alone", not much influenced
But if you match tWR = tCL , then tWTR_L needs to be = tRTP


Veii said:


> FCLK_EFF_FREQ still jumps to 2000-2100 FCLK
> Baseline is current FCLK. And only does it by going on the 2nd CCD
> Something overdrives internally. Last sample jumped to 2600 FCLK but had other existence problems.


Yes there is something awkward to it

IF FCLK is bellow 1900, 2nd CCD furthest away overdrives effective FCLK , but first / main stands still
IF FCLK is over 1900 (1933 and higher) 1st CCD overdrives higher , while 2nd stays still
This is a DPM thing and you guys "should" check how it behaves with typical boost testers and on full load TM5
Full load should expected'ly result in firm FCLK = FCLK_EFF
And core test should result in either firm or overdriven Effective FCLK.
This same "overdriven" also happens to cores themself, but there it actually is bugging out.
Here it is by design, which might not be "optimally" designed ~ or only designed rated for 1800 FCLK as advertised.

















Old bugged 5900Xsample reminder







This for example i never had on my unit, but it shows very clear overdriving functionality to me
Haven't sadly found yet how to disable this
No WHEA's so far, except at boot
No #19 on individual core and IMC Data load
We'll see between CCD's load , likely that caused the error spike

But yes, please take a look and track "if it by any chance matches the reason why you get WHEA #19
Especially since AIDA64 is a core to core load, later with an CCD to CCD load

EDIT:
Okk so i think i know what it is now - but it's not the whole picture
Currently i can toggle between a state of getting WHEA 19 & 20, and a state of not getting WHEA 19 & 20 
But the whole picture is not drawn yet with the fix
should've kept the old broken sample, d*ng it 
Rev.B2 has no WHEA #19 fix ~ but i found a flaw that triggers #19 & #20
Was right from the beginning with DPM, but oversaw this thing. Yes it still is a sensor issue
At least it's toggle-able now between WHEA #19 and no WHEA #19 *🙈*


----------



## Taraquin

PJVol said:


> Mine has four.
> 
> 
> Hardly anyone can answer the 1st question, unless he wrote memory controller part of the firmware, but I already showed here, how it affects some benchmark results when set to its minimum (8), in my particular PC config (actually two PC's were involved).


4 dimm ITX on AM4?


----------



## Veii

Veii said:


> Okk so i think i know what it is now - but it's not the whole picture


So far i can make the toggle happy and not cause WHEA, but beyond P0 it doesn't function
@PJVol we have to find the name of the toggle and disable it, then you guys should be free from the errors
Currently i can please the toggle but it still overdrives on higher than P0. Soo that's not the whole fix
The reason for issues indeed is this ~ but the picture of flaws is bigger, it's not "only this"

If you force limit boosting freq, then it will not overshoot and it will not overdrive
When it didn't overdrive - i had no #19s anymore
But if you exceed P0, the limiter doesn't function and this thing overdrives again. Same goes for core clock overboost ~ same connected issue i feel
Testing now if allcores also cauuse the same issue ~ likely but want to see it read out

EDIT:








Nope, not fixable with any current available-bios option (CBS, LN2 modes, OC modes and similar, not fixable with what we have)
Only fixable by SMU mailbox and only temporary - not permanently
FCLK just does overdrive and causes that way WHEA (98% whole reason for #20 and #19)
It's not a fixed frequency limit ~ as it will overdrive differently by different base values and by different samples
My 5600X never did it, and when i tame frequency here, it also doesn't do it (surprisingly , didn't expect it at first)
If i let go FIT, and anything around it, including DF states ~ it overshoots too strongly
Also oops , i broke xGMI


----------



## Audioboxer

mongoled said:


> Did you test without the riser cable ??
> 
> As that should be the first test you run, gfx card inserted directly into the first PCIe slot and then run your tests ...


Nah, it's too much of a pain to run the GPU horizontally in this loop. Couldn't cool the CPU properly without creating new piping to allow the GPU to be setup horizontally and benching/testing done.

I mean, it's an expensive PCIe 4.0 cable, I can't get much better to run a GPU vertically. If this couldn't do it, what could? Other people have no issues with vertical GPUs so I doubt I would be some special case. The more reading of the web I do the more I see others with voltage droop under heavy load.

Going to RMA the PSU with Amazon, but I'm also going to try bugging a friend for their power supply just to do a quick test.










In other news, as part of my loop air bubbles process I normally leave my PC running 24 hours for a few days, so overnight is chance to do some memory testing. Dropped my VSOC from 1.15v to 1.125v and this.... Not heat related over time, as max temps memory got to was 33 degrees. So VSOC back up and another test tonight.

I mean, I hope it's just VSOC lmao. This profile has had a 9 cycle Anta777, but an error after 9 hours in Karhu is a bit of a "oh feck, here we go....".


----------



## Taraquin

Audioboxer said:


> Nah, it's too much of a pain to run the GPU horizontally in this loop. Couldn't cool the CPU properly without creating new piping to allow the GPU to be setup horizontally and benching/testing done.
> 
> I mean, it's an expensive PCIe 4.0 cable, I can't get much better to run a GPU vertically. If this couldn't do it, what could? Other people have no issues with vertical GPUs so I doubt I would be some special case. The more reading of the web I do the more I see others with voltage droop under heavy load.
> 
> Going to RMA the PSU with Amazon, but I'm also going to try bugging a friend for their power supply just to do a quick test.
> 
> View attachment 2535279
> 
> 
> In other news, as part of my loop air bubbles process I normally leave my PC running 24 hours for a few days, so overnight is chance to do some memory testing. Dropped my VSOC from 1.15v to 1.125v and this.... Not heat related over time, as max temps memory got to was 33 degrees. So VSOC back up and another test tonight.
> 
> I mean, I hope it's just VSOC lmao. This profile has had a 9 cycle Anta777, but an error after 9 hours in Karhu is a bit of a "oh feck, here we go....".


I would consider this stable myself if it also passes TM5 anta. If it doesn`t cause freezes, bsods etc in anything I say stick with it if performance is good.


----------



## Audioboxer

Taraquin said:


> I would consider this stable myself if it also passes TM5 anta. If it doesn`t cause freezes, bsods etc in anything I say stick with it if performance is good.


Nah, this is a no error zone lol. It's likely VSOC, I've had one or two issues before trying to drop my VSOC on this profile with TM5 (timeouts). Given how hard I push tRFC and being tCL13, I think it's just the case I'm not going to get away with a lower VSOC. Especially with how droopy VSOC can be on this MSI board.

1.15v is really 1.125v. Setting to 1.125v in the BIOS you're getting the equivalent drop under heavy load.

Will test again tonight. Karhu is something I've only recently added to my arsenal, and it was done after I was happy to claim TM5 profile stable. So another really long run tonight should be interesting with VSOC back to where it was when the other profile was locked in.

Usually takes a few days or a week or so to get all the air out of this loop when it's refilled so leaving the PC on overnight has its benefits right now lol.


----------



## Audioboxer

New chipset drivers

*AMD Chipset Drivers* :

Package : 3.11.17.521 WHQL [17/11/2021]






[DRIVERS] AMD Chipset/RAID (3xx/4xx/5xx/6xx/TRX40)


Hi everyone, - AMD Chipset Drivers : Package : 4.11.15.342 WHQL Download : Link - AMD RAID Drivers (Drivers Only) : Drivers - NVMe - 6xx/TRX40 : 9.3.2.158 WHQL



rog.asus.com













File on MEGA







mega.nz





Supplied by ASUS.

I presume another internal attempt at fixing Windows 11 issues. Between AGESA as of late and Windows 11 it's been a bit of a rough time for AMD.


----------



## mongoled

Audioboxer said:


> Nah, it's too much of a pain to run the GPU horizontally in this loop. Couldn't cool the CPU properly without creating new piping to allow the GPU to be setup horizontally and benching/testing done.


Dude!

Just for testing !

To see where your "issue" really lays ...


----------



## Audioboxer

mongoled said:


> Dude!
> 
> Just for testing !
> 
> To see where your "issue" really lays ...


But I can't just do testing unless I get my loop working horizontally. CPU would likely overheat within a minute lol.

If you're suggesting run the loop drained with the pump turned off.

I really doubt both a PCIe 3.0 and 4.0 cable could be faulty, more so a properly made 4.0 cable. 

In principle I agree with you, but I'd rather just replace the PSU now lol. I've told one of my friends they're tearing out their PSU for me to test lol. Though the benefit of Amazon is they'll likely just refund me or happily send out a replacement without any send it back, wait 3 weeks without a working PC.

Going to phone support later today, and explain the ASUS position. Usually get the best response over the phone rather than live chat. Especially as the PSU is over a year old now, but it does come with a longer warranty.

I have been running 3DMark for an hour or so now with an OCed GPU and no crashes yet.


----------



## mongoled

Just take the GPU out of the loop.....

You dont have any soft tubing to re-route ?

I can see the outcome, you get a new PSU and the 12v reading remain the same 

😃


----------



## Audioboxer

mongoled said:


> Just take the GPU out of the loop.....
> 
> You dont have any soft tubing to re-route ?
> 
> I can see the outcome, you get a new PSU and the 12v reading remain the same
> 
> 😃


Nah soft tubing free home lol.

Well, if it's not costing me for a new PSU then no harm done. Just points out that it's the mobo or GPU then I guess. Could even be PSU 12v cable, but I don't have another to try.

Possibly mobo given some reading I've done online with droop on the 12v line.

I've now changed to a 380w BIOS and testing is going fine so far. Previously had a 330w BIOS.


----------



## Yuke

ManniX-ITA said:


> Same as @PJVol can confirm there are a number of benchmarks, don't recall which ones, where you can see the gains. I would try OCCT.
> Of course we are talking about write or combined performances; that's why it's more difficult to observe, most benchmarks scores are based upon read performances.
> I think GDM does auto-correct it, if an odd number.
> 
> From my experience if you get errors is because of tWRRD/SCL.
> tWRRD * SCL <= tRCDRD; not sure in which conditions but this is true for tRCDWR as well
> High tWR/tRP usually helps without cost.
> I'm running tRCDWR at 8 now but with tWR 16 and tWRRD at 1 and SCL at 4.


To look at secondary timings helped me fix it it seems ( 42min karhu so far error free)

But changing tWR/tRTP alone was not enough i also had to change tRRDL and tWTRL (tWTRL alone was probably enough)

So there seems to be something going on between those 4 and tRCDWR...

Not sure if it was worth it performance wise though.

tWR went from 12 to 16
tRTP from 6 to 8
tRRDL from 4 to 6
tWTRL from 8 to 12

...so i can set tRDCWR to 8


----------



## Audioboxer

So I've been running a few TimeSpy runs now on a 380W BIOS and while 360W seems to be the max peak more importantly I want to ask what should the GPU PCIe 12v input be able to draw? 65w a normal figure? Obviously my card at the moment is a PCIe 3.0 card, so the slot must be running at PCIe 3.0. I'm going to try and push a big overclock now and see how it gets on.

But first I've got time to give Amazon a call just now, wish me luck!


----------



## Mach3.2

Audioboxer said:


> View attachment 2535301
> 
> 
> So I've been running a few TimeSpy runs now on a 380W BIOS and while 360W seems to be the max peak more importantly I want to ask what should the GPU PCIe 12v input be able to draw? 65w a normal figure? Obviously my card at the moment is a PCIe 3.0 card, so the slot must be running at PCIe 3.0. I'm going to try and push a big overclock now and see how it gets on.
> 
> But first I've got time to give Amazon a call just now, wish me luck!


65W power draw on the 12V rail seem about right. The whole 75W power budget per PCIe slot includes the power draw on the 5V (or 3.3V?) if I'm not wrong.


----------



## ManniX-ITA

Mach3.2 said:


> 65W power draw on the 12V rail seem about right. The whole 75W power budget per PCIe slot includes the power draw on the 5V (or 3.3V?) if I'm not wrong.


Yes correct, there's a 10W budget for 3.3V.
On the Unify-X there's an additional 6-pin power connector dedicated to the PCIe slots.
If it's connected in theory you can draw even more (up to 80-100W), eg. with resistors shunting, relatively safely.


----------



## Audioboxer

ManniX-ITA said:


> Yes correct, there's a 10W budget for 3.3V.
> On the Unify-X there's an additional 6-pin power connector dedicated to the PCIe slots.
> If it's connected in theory you can draw even more (up to 80-100W), eg. with resistors shunting, relatively safely.


Is that the CPU connector at the top left? I connected both/all of them even although it was stated that would really be for extreme CPU overclocking, like below zero. I'm guessing it's harmelss to have the "extra" CPU pin hooked up if it's not being used?

Good news about the power supply, great even, outside of Amazon's usual apologies and we can see you've been with us for many years, the rep said if I email over the ASUS response I got as soon as they can see it from my account email they'll request a refund. Amazon UK doesn't seem to be stocking the 850w THOR anymore, or at least it's all 3rd party market place sellers at the moment.

So it seems I'm getting a full refund with no need to return! Presumably because Amazon cannot exchange with no stock and I've basically never had any warranty claims with Amazon before. Maybe a few returns here or there over like 10 years.










Or wait, it's down the bottom, PCIE_PWR1.

Hmmm, I wonder if connecting that would do anything for the 12v rail??? Issue is it's impossible for me to reach without another loop drain due to vertical graphics card LOL.


----------



## ManniX-ITA

Audioboxer said:


> Is that the CPU connector at the top left? I connected both/all of them even although it was stated that would really be for extreme CPU overclocking, like below zero. I'm guessing it's harmelss to have the "extra" CPU pin hooked up if it's not being used?


You are talking about n.1 below, the PCIe dedicated is the n.2:











I have all of them connected just to be sure.
Even if indeed the CPU_PWR2 may be not so useful unless it's a 5950X massively OCed.


----------



## Audioboxer

ManniX-ITA said:


> You are talking about n.1 below, the PCIe dedicated is the n.2:
> 
> View attachment 2535308
> 
> 
> 
> I have all of them connected just to be sure.
> Even if indeed the CPU_PWR2 may be not so useful unless it's a 5950X massively OCed.


Yeah I just edited in above noticing that I had missed the bottom connector. Never thought to connect it.

Do you know if it can help with the 12v voltage, or is it simply a way to draw more than 65w? I mean, before I go and buy another PSU with this refund, I guess I should try this. But I don't think I can reach in and plug something in without removing the graphics card which means ANOTHER loop drain lol.

Don't think I have another 6 pin cable unless I use the 8 pin daisy chain cable and only plug in 6 pins (would this work?).


----------



## ManniX-ITA

Audioboxer said:


> Do you know if it can help with the 12v voltage, or is it simply a way to draw more than 65w? I mean before I go and buy another PSU with this refund, I guess I should try this. But I don't think I can reach in and plug something in without removing the graphics card which means ANOTHER loop drain lol.


Very unlikely it would help.
I would drain the loop for a new PSU... did you pick one?

(I'd think about something with 6 x 8-pin, 3 for the board and 3 for the GPU)


----------



## Audioboxer

ManniX-ITA said:


> Very unlikely it would help.
> I would drain the loop for a new PSU... did you pick one?


Ah well, I did see someone recommend a PCIe power booster to help with power issues/droop, but I guess that's if you can't draw what you need.

I don't need to drain the loop to replace the PSU. Nothing gets in the way of me removing PSU power cables and it's a Lian Li O11 XL so the PSU is in the back on its own.

Probably the 1000x or AX860i. Basically feel I'm pushed into Corsair (_Everyone_ is crapping on Seasonic/Be Quiet lol) and I've found out Corsair are a company that's really good with RMAs. Only slight concern is I've seen some Corsair PSUs down at 11.6~11.7v under load. I'm absolutely paranoid now about this 12v rail voltage.


----------



## ManniX-ITA

Audioboxer said:


> Probably the 1000x or AX860i. Basically feel I'm pushed into Corsair and I've found out Corsair are a company that's really good with RMAs.


I wouldn't go below 1000W with your setup and your inclination to OC 
Otherwise the next top tier GPU could be challenging...

The RM1000x is quite noisy...
If you want to go Corsair, I'd spend a little more and take the HX1000.
Better, more efficient and newer, less noisy.

Another option could be an Antec Signature 1000W from Amazon:









Antec Signature 1000W Modular Power Supply 80 Plus Platinum : Amazon.co.uk: Computers & Accessories


Buy



www.amazon.co.uk


----------



## Audioboxer

ManniX-ITA said:


> I wouldn't go below 1000W with your setup and your inclination to OC
> Otherwise the next top tier GPU could be challenging...
> 
> The RM1000x is quite noisy...
> If you want to go Corsair, I'd spend a little more and take the HX1000.
> Better, more efficient and newer, less noisy.
> 
> Another option could be an Antec Signature 1000W from Amazon:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Antec Signature 1000W Modular Power Supply 80 Plus Platinum : Amazon.co.uk: Computers & Accessories
> 
> 
> Buy
> 
> 
> 
> www.amazon.co.uk


HX1000i a good shout then? Although it says multi rail it can seemingly be switched to single rail.


----------



## ManniX-ITA

Audioboxer said:


> HX1000i a good shout then? Although it says multi rail it can seemingly be switched to single rail.


Yes, I think it can be switched only via software between single/multi rail.


----------



## Audioboxer

ManniX-ITA said:


> Yes, I think it can be switched only via software between single/multi rail.


I have to run iCUE anyway so if it loads up in that it's no problem lol.

Alright I'll buy it! Platinum rated and seems the i variant is a slight step up from the HX1000.

Antec Signature looks nice, a little cheaper as well, but I'll just stick with Corsair knowing how their warranty process goes.


----------



## ManniX-ITA

Audioboxer said:


> I have to run iCUE anyway so if it loads up in that it's no problem lol.


I feel sorry for you... I managed to ditch it on my niece's build using Argus Monitor


----------



## Audioboxer

ManniX-ITA said:


> I feel sorry for you... I managed to ditch it on my niece's build using Argus Monitor


I managed to shut down some services it uses that I don't need (like running a damn headphones service when I don't have Corsair headphones), but I have to admit for ease of use tinkering with the commander pro, fan curves and so on it... works.

But it's stupidly bloated.

Version 4.0 is a little bit better than when it launched because let me tell you the first few releases couldn't even be called alpha software. Absolutely dreadful.


----------



## TeslaHUN

Could you guys recommend me some "bestbuy" 2x 16gb RAM for my Ryzen 5900x ?
Currently i have 3200 cl16 but i move this kit to another computer , so i need to buy some new RAM .
I want 3600 cl16 or even 4000 !? Probably it wont matter ,since i play in 4K . It must be Dual Rank ofc. I cannot find any site that show wich RAM is DR or SR . ( I know the B-die finder site )
Ohh , and i never had luck with RAM OC ,so i dont want to waste weeks to stabilize it 
To summ :
Let me know if you know a 2x16 kit which is 100% DualRank /CL16 (can't check serial numb , I will order online) or more , out of the box ,and it does not cost a fortune 🙏
For example this 3600 / C16 -19-19-39 kit has reasonable price in Hungary .But no idea if its SR or DR.


----------



## ManniX-ITA

TeslaHUN said:


> Let me know if you know a 2x16 kit which is 100% DualRank /CL16 (can't check serial numb , I will order online) or more , out of the box ,and it does not cost a fortune 🙏


This one:






G.Skill DIMM 32 GB DDR4-3600 Kit, Arbeitsspeicher F4-3600C16D-32GTZN, Trident Z Neo, XMP


Das G.Skill F4-3600C16D-32GTZN ist ein Dual-Channel-Kit aus zwei 16-GB-DDR4-3600-Speichermodulen (PC4-28800) aus der Trident Z Neo Serie. Die Gesam...




www.alternate.de





The good ones are all costing a fortune


----------



## PJVol

Blameless said:


> if I had to pick one as being most likely, it would be Clk


Yeah, you're spot on with it )
With a 60 or 40 there were #10, #11, #12, two #2's and so on in a 2nd and 3rd cycle already.
Just setting it to 24 fixed them right away.











Taraquin said:


> 4 dimm ITX on AM4?


No, mine is m-atx, but it's a small one too


----------



## mongoled

** Completely off topic **
Are these RTX cards meant to boost way past the max boost GPU clock on default cooling/settings? 

Max boost on this Zotac 3070 is meant to be 1725 mhz and its hitting 1900+ in the Port Royal test.... 

Ambient temps are 26C


----------



## Mach3.2

mongoled said:


> ** Completely off topic **
> Are these RTX cards meant to boost way past the max boost GPU clock on default cooling/settings?
> 
> Max boost on this Zotac 3070 is meant to be 1725 mhz and its hitting 1900+ in the Port Royal test....
> 
> Ambient temps are 26C


Totally normal. As far as I knew that's how GPU boost clock works since Pascal (1000 series cards).


Consequently, the cooler you can get the GPU core, the more boost you get.


----------



## Audioboxer

mongoled said:


> ** Completely off topic **
> Are these RTX cards meant to boost way past the max boost GPU clock on default cooling/settings?
> 
> Max boost on this Zotac 3070 is meant to be 1725 mhz and its hitting 1900+ in the Port Royal test....
> 
> Ambient temps are 26C


Yeah, even my 2080Ti does that. On it's original BIOS which is supposed to be boost to 1545 it will go up to like 1900+ lol. Even on a BIOS with 1755 boost it will still do it.

If it has thermal overhead and isn't maxing out power it just seems to boost as much as it can.


----------



## domdtxdissar

@Audioboxer

Regarding 12volt rails.. I did some testing/benching on a other forum, but maybe the data will help you alittle in regards to what is "normal".

PSU: EVGA G3 1000w
GPU: MSI Suprme X 3090 @ EVGA 1000w rebar bios
















Peak powerusage in superpos = ~580w
Peak PCIe slot power usage = ~50w

12v 8pin #1 = 200w, minimum 11.9v
12v 8pin #2 = 190w, minimum 11.9v
12v 8pin #3 = 150w, minimum 11.9v

_edit_
Quick run in 3dmark port royal with my daily 24/7 asus 520w bios
(1000w bios idles @ ~100w)
(Suprme X is dual bios so its easy to switch between)









My rails are also dipping slightly below 12v but have never had any problems because of it, i think atleast


----------



## Audioboxer

domdtxdissar said:


> @Audioboxer
> 
> Regarding 12volt rails.. I did some testing/benching on a other forum, but maybe the data will help you alittle in regards to what is "normal".
> 
> PSU: EVGA G3 1000w
> GPU: MSI Suprme X 3090 @ EVGA 1000w rebar bios
> View attachment 2535323
> 
> View attachment 2535324
> 
> 
> Peak powerusage in superpos = ~580w
> Peak PCIe slot power usage = ~50w
> 
> 12v 8pin #1 = 200w, minimum 11.9v
> 12v 8pin #2 = 190w, minimum 11.9v
> 12v 8pin #3 = 150w, minimum 11.9v
> 
> _edit_
> Quick run in 3dmark port royal with my daily 24/7 asus 520w bios
> (1000w bios idles @ ~100w)
> (Suprme X is dual bios so its easy to switch between)
> View attachment 2535326
> 
> 
> My rails are also dipping slightly below 12v but have never had any problems because of it, i think atleast


Thanks for doing that. Seems there is fluctuations all round depending on hardware.

I'm getting a refund and I've bought a HX1000i anyway, so I'll have 2 PSUs and will be able to compare them now  I guess I might try selling my Thor lmao. But I don't want to give someone a duffer. 11.8v on the PCIe 12v slot is beginning to get a bit lower.

If this new PSU does exactly the same then I'll presume it's hardware related. I'm not getting any crashes just now doing stability testing.

It might be the case apart from the voltage dips I also had a faulty riser cable. Two separate things.


----------



## mongoled

These cards are just stupid

😃😃

Flashed to Asus TUF 3070 Gaming OC BIOS, MSI Afterburner, limiter to 112%, mem clock +500, gpu clock +125, didn't bat an eyelid

That's the last from me on this subject....

😂😂


----------



## Audioboxer

mongoled said:


> These cards are just stupid
> 
> 😃😃
> 
> Flashed to Asus TUF 3070 Gaming OC BIOS, MSI Afterburner, limiter to 112%, mem clock +500, gpu clock +125, didn't bat an eyelid
> 
> That's the last from me on this subject....
> 
> 😂😂


If it's Samsung memory similar to what went into some 2080Tis it can probably do like +900~1000 on the memory easily lol.


----------



## ManniX-ITA

Audioboxer said:


> If this new PSU does exactly the same then I'll presume it's hardware related. I'm not getting any crashes just now doing stability testing.
> 
> It might be the case apart from the voltage dips I also had a faulty riser cable. Two separate things.


From what I've seen a good PSU shouldn't drop more than 200mV under half load; better if less, 100-150mV.
It's important to check the delta between max and min with GPU-z/HWInfo.
Your Thor was dropping up to 350mV. Which is not good at all but if it works, I guess you can resell it 

The issue is when the GPU is crashing. Igor's lab did a check with an oscilloscope and there are transients up to 570W for about 360W power draw.
They are short bursts but if the PSU is already dropping to 11.6-11.8V at half load it could trigger the UVP/OCP circuit under higher load.
But if the PSU can hold the voltage even during those bursts then no crashes.


----------



## Audioboxer

ManniX-ITA said:


> From what I've seen a good PSU shouldn't drop more than 200mV under half load; better if less, 100-150mV.
> It's important to check the delta between max and min with GPU-z/HWInfo.
> Your Thor was dropping up to 350mV. Which is not good at all but if it works, I guess you can resell it
> 
> The issue is when the GPU is crashing. Igor's lab did a check with an oscilloscope and there are transients up to 570W for about 360W power draw.
> They are short bursts but if the PSU is already dropping to 11.6-11.8V at half load it could trigger the UVP/OCP circuit under higher load.
> But if the PSU can hold the voltage even during those bursts then no crashes.


Yeah I'm quite excited to find out if another PSU is totally different, given nothing else in this setup is going to change. Should be here in a few days so no need to borrow anyone's power supply! I would guess with another brand and model it's likely there would be change anyway, but more important will be seeing how that GPU PCIe 12v slot holds up.

As much as I hate iCUE seems pretty cool you can digitally control the i model via software. Time to setup a power supply fan curve!


----------



## Hookz

Any ideas on how to get tRCDRD 14? I've tried many different things but anything doesn't seem to work: D


----------



## Audioboxer

So I ran the TimeSpy benchmark rather than the stability test, I've ignored benchmarks up until now










Good news is seeing it hit 380w and even managing 70w on the GPU PCIe 12v input.

Bad news, look at those voltage dips.


----------



## ManniX-ITA

Audioboxer said:


> Bad news, look at those voltage dips.


How much total load? You should be able to see it via iCUE.
300mV drop is definitely not brilliant for a 1000W since it's probably 600-700W.
You should check only GPU with Port Royale what is the delta.


----------



## Audioboxer

ManniX-ITA said:


> How much total load? You should be able to see it via iCUE.
> 300mV drop is definitely not brilliant for a 1000W since it's probably 600-700W.
> You should check only GPU with Port Royale what is the delta.


My current PSU is 850w not 1000w. I'll check with Port Royal shortly.

Load as in GPU usage? I believe it was 100%.

This is my Thor btw lol, I've been trying out a 380w bios that is all.


----------



## ManniX-ITA

Audioboxer said:


> My current PSU is 850w not 1000w. I'll check with Port Royal shortly.
> 
> Load as in GPU usage? I believe it was 100%.
> 
> This is my Thor btw lol, I've been trying out a 380w bios that is all.


Sorry I thought you already got the Corsair, I did a bit of time warp 
I meant total load, including CPU PPT.


----------



## Imprezzion

Error #10 in 1usmus TM5, can that be caused by temperatures?

I had a 25 cycle run going while I was at work and for some reason my RAM fan decided to die on me so it completed the full 25 cycle 3 hour run with 2 errors, both error #10. DIMM's were sitting at a staggering 59 C and 59.3 C. I am very surprised it was only 2 errors at that temperature.. 

This is what I was running clock and timing wise @ 1.50v vDIMM. I mean, if this only has 2 error #10's in 3 hours at basically 60C it's pretty stable after all lol.
I will try to drop vSOC tho. This is Auto and pretty up there for 3800/1900 1:1.


----------



## domdtxdissar

AIDA64 6.50.5817 Beta fixes the L3 Cache Bandwidth Benchmark for AMD CPUs on Windows 11.

Available here 









Seems to be working, its just the L3 latency thats alittle high compared to win10 now


----------



## Worldwin

Could someone recommend me some settings to get at least CR2 to post for 3800 (Referring to RTT's, STR's and Setup).
5800x, Tomahawk X570, 2*16 4000 CL 16 16 16 36 Bdie


----------



## TimeDrapery

Worldwin said:


> Could someone recommend me some settings to get at least CR2 to post for 3800 (Referring to RTT's, STR's and Setup).
> 5800x, Tomahawk X570, 2*16 4000 CL 16 16 16 36 Bdie


You could look at the posts above yours

Considering you're looking to get your system to POST, clear CMOS and load Optimized Defaults before trying again... Who knows what settings are interfering with what when it comes to your OC

Then try something along the lines of:

VSOC1.15V - 1.2VCLDO VDDP900mV - 980mV (40mV stepping)VDDG CCD980mV -1020 mV (40mV stepping)VDDG IOD1060mV - 1100mV (40 mV stepping)VDIMM1.45V - 1.5VProcODT32.0Ω - 36.9ΩRttNom
RttWr
RttParkRZQ/6 - RZQ/7
RZQ/2 - RZQ/3
RZQ/1 - RZQ/7ClkDrvStr
AddrCmdDrvStr
CsOdtDrvStr
CkeDrvStr40.0Ω - 60.0Ω
20.0Ω - 24.0Ω
30.0Ω - 40.0Ω
20.0Ω - 24.0ΩAddrCmdSetup
CsOdtSetup
CkeSetup0 (Auto)
0 (Auto)
0 (Auto)


----------



## Imprezzion

You could try some of my settings from 3 posts up yeah. Your B-Die bin is much better then my below average 3600C16's so it _should_ have no problems with that.

Fans fixed, the connection at the hub came loose somehow. Resoldered it and it's fine now. Re-running TM5 1usmus now with 1.081v SOC (droops to 1.075v Auto LLC).

EDIT: It was temperature related, the 2 error #10's. I'll let it finish the full 25 cycles but it would've errored by now if it was something else. DIMM's sitting at 40-41c now as they should. Also vSOC seems to be fine so far at -0.100 offset 1.081v idle 1.075v load. VDIMM still 1.500v.










Anything timing wise I should be tweaking from here?
I already know the RAM doesn't like straight 14's for the mains but maybe I can get it to do it with some tweaks.

Latency in AIDA (latest beta from few posts up) still seems a bit high to me.


----------



## TimeDrapery

Imprezzion said:


> You could try some of my settings from 3 posts up yeah. Your B-Die bin is much better then my below average 3600C16's so it _should_ have no problems with that.
> 
> Fans fixed, the connection at the hub came loose somehow. Resoldered it and it's fine now. Re-running TM5 1usmus now with 1.081v SOC (droops to 1.075v Auto LLC).
> 
> EDIT: It was temperature related, the 2 error #10's. I'll let it finish the full 25 cycles but it would've errored by now if it was something else. DIMM's sitting at 40-41c now as they should. Also vSOC seems to be fine so far at -0.100 offset 1.081v idle 1.075v load. VDIMM still 1.500v.
> 
> View attachment 2535387
> 
> 
> Anything timing wise I should be tweaking from here?
> I already know the RAM doesn't like straight 14's for the mains but maybe I can get it to do it with some tweaks.
> 
> Latency in AIDA (latest beta from few posts up) still seems a bit high to me.
> 
> View attachment 2535388


Yeah, you can likely set your primaries to

*15-15-15-30-45*

rather than what you're at, your *SCLs* can likely go to *4*, your *tCWL* (...*9*?) should increase to *14* and then you should try dropping *tWRRD* to *2* and *tRDWR* to *9* (seems like you had a mix-up, 🤭)

Also, drop *tRFC* to *272*/*202*/*124* or *270*/*201*/*123*

Likely that'll all help your latency out a good bit

As an aside, drop *CLDO VDDP* to *940mV* from *1000mV* and play with *CCD*/_*IOD*_... I'd look at *1020mV* for *CCD* and *1100mV* for *IOD* with *VSOC* at *1.175V*

I'd also reduce *ProcODT* to *34.3Ω*/*36.9Ω* and set *RTTs* to something like *6*/*3*/*3*, *7*/*3*/*3*, *7*/_*3*_/_*1*_

As another aside you should play with *drive strengths*... Something like... *40.0Ω*/*20.0Ω*/_*20.0Ω*_/_*20.0Ω*_, *40.0Ω*/_*20.0Ω*_/*24.00Ω*/_*24.0Ω*_, or *40.0Ω*/*20.0Ω*/*30.0Ω*/*20.0Ω*

Mine's single rank but the timings aren't impossible and mostly apply to your B-die as well


----------



## PJVol

Veii said:


> Silicon is buggy with CO's it overvolts


What was it set to in that screenshot? I see two problematic cores there (3 and 5), I mean was it set as per hydra log?



Veii said:


> This to Zero , forces cores to throttle strongly
> This to 666 or -666 bugs it out and removes one throttler ~ yet not permanent


That's because you actually zeroed psm margins (hardware curve optimizer, lol) for all cores.
You seem to have missed my post, where i tried to get your attention to the fact, that actual commands sent are shifted 1 position upwards the dropdown list (not sure though, which position exactly this shifting is starts from), i.e. SetTJMax actually sets PPT limit and so on.








It is possibly due to an old agesa version which the tool is rely on.


----------



## TimeDrapery

PJVol said:


> What was it set to in that screenshot? I see two problematic cores there (3 and 5), I mean was it set as per hydra log?
> 
> 
> That's because you actually zeroed psm margins (hardware curve optimizer, lol) for all cores.
> You seem to have missed my post, where i tried to get your attention to the fact, that actual commands sent are shifted 1 position upwards the dropdown list (not sure though, which position exactly this shifting is starts from), i.e. SetTJMax actually sets PPT limit and so on.
> View attachment 2535401
> 
> It is possibly due to an old agesa version which the tool is rely on.


What else does PowerTableMonitor show? Fancy


----------



## KedarWolf

PJVol said:


> What was it set to in that screenshot? I see two problematic cores there (3 and 5), I mean was it set as per hydra log?
> 
> 
> That's because you actually zeroed psm margins (hardware curve optimizer, lol) for all cores.
> You seem to have missed my post, where i tried to get your attention to the fact, that actual commands sent are shifted 1 position upwards the dropdown list (not sure though, which position exactly this shifting is starts from), i.e. SetTJMax actually sets PPT limit and so on.
> View attachment 2535401
> 
> It is possibly due to an old agesa version which the tool is rely on.


Can you link these tools again, and what settings should I use for SMN Mailbox and any other thing for a 5950x with older dual rank b-die.

I saw they jump up one.


----------



## KedarWolf

I'm pretty happy with this for older 2x16GB Neo CL16 3600 b-die.

Edit: It passes TM5 and I get zero WHEAs.


----------



## Blameless

mongoled said:


> Are these RTX cards meant to boost way past the max boost GPU clock on default cooling/settings?
> 
> Max boost on this Zotac 3070 is meant to be 1725 mhz and its hitting 1900+ in the Port Royal test....


This is normal. Take a look at the F/V curve with MSI AB or something. The curve also has a temperature offset on it that tends to shift clocks by roughly one step (12.5MHz on older architectures, 15MHz on Ampere) every 10-15C. Do note that this can easily lead to overboosting at cooler temps, so it's prudent to test a range of temperatures and make sure your curve OC flattens out at a sane level.



Audioboxer said:


> Bad news, look at those voltage dips.


This is probably not the PSU's fault, and most of it may even be occuring at the input filtering stage of the card, depending on how that's been setup and how much current is being rammed through it.

Measure another +12v output and the PSU and GPU side of the GPU cables while the card is heavily loaded (near power limit). You'll likely see that the other +12v outputs barely move and that even the voltage at the connectors going into the PSU isn't a 300mV droop. If it's hugely different at the GPU side of the cable, thicker wires and better connectors will probably help. If not, the droop is probably happening on the GPU board itself.

If the PSU is actually losing 300mV at half load, it's broken and should be replaced.


----------



## PJVol

TimeDrapery said:


> What else does PowerTableMonitor show?


Exactly what its name suggests, i..e. power table values, nothing fancy, tbh )



KedarWolf said:


> Can you link these tools again, and what settings should I use for SMN Mailbox and any other thing for a 5950x with older dual rank b-die.


Actually, it's Veii's who post it here, if you mean "Tool", and I think he was talking about limiting Boost Frequency in context of whea's.
As for SMU Debug Tool, it's a custom build on request for my hw platform, so idk, if he has published release version. Anyway, you may look for it in Rusanov's repo yourself (zentimings developer).


----------



## umea

KedarWolf said:


> I'm pretty happy with this for older 2x16GB Neo CL16 3600 b-die.
> 
> Edit: It passes TM5 and I get zero WHEAs.
> 
> View attachment 2535421


Main timings seem strange, are you not able to run 15-15-15-30-45 with this kit?


----------



## Veii

PJVol said:


> What was it set to in that screenshot? I see two problematic cores there (3 and 5), I mean was it set as per hydra log?


Stock, with Hydra i'll end up working today
With CO's i did per hand and per Hydra
Both results are good but they can't be higher than the CO limits. Atm -30 CO is not enough for them, soo Hydra it is, till the bioses release



PJVol said:


> That's because you actually zeroed psm margins (hardware curve optimizer, lol) for all cores.
> You seem to have missed my post, where i tried to get your attention to the fact, that actual commands sent are shifted 1 position upwards the dropdown list (not sure though, which position exactly this shifting is starts from), i.e. SetTJMax actually sets PPT limit and so on.


I didn't miss the post, but i actually forgot.
Tho it's not for all options the case








Thjl9JKQx7.mp4


Watch "Thjl9JKQx7.mp4" on Streamable.




streamable.com




Currently it doesn't do anything on zero for me, soo likely the screenshot was running COs. 
Yes very likely the case


----------



## Veii

PJVol said:


> Actually, it's Veii's who post it here, if you mean "Tool", and I think he was talking about limiting Boost Frequency in context of whea's.


Yes the talk was that while VDD18 voltage seems to slightly limit the spikes - it is the spikes that seem to cause the WHEA's
It is not the full load that causes it & it is not any fixed post limit (which surely exist still near 2133-67)

While this never behaved that way on my sample - and likely it was just coincidence which CCD was disabled, one CCD does overdrive FCLK one does not
Well that and that Rev.B2 did not fix this ~ which i can still call "a DPM & sensorics" Problem
Out of all, i just did not expect that they actually be gone @ 1966, if this flag was satisfied and it didn't overdrive by itself.
Very valuable information i missed before (as 5600X sample did never do it, always held well behaving it's set freq), but clearly knew one sensoric value behaved different

Now the question remains

What CCD is disabled when people use the bios. Soo can they convert their dual CCD to one without problems
Do consumer/retail batches , single CCD units also have the same abstract behavior @ and beyond 1900 FCLK
What is this flag actually called and how to stop it from overdriving itself. It doesn't appear to be clockgating and clearly is not something the current CBS section of the bios gives access to



Veii said:


> it is the spikes that seem to cause the WHEA's


And this is now an issue
Because it makes WHEA Surpressor not the best option @ManniX-ITA
They are coming from real spikes.
On one hand it's fine, because AMD overdrives it till it reaches X limit and throttles back. Soo not a stability issue & they know their boosting system
On the other hand, it's still a real issue, but it's not sample based and it's purely on AMDs side

And meanwhile i get send this








Soo the hope that this get's fixed by AMD, is . . . well it's not that high, tbh 
I've asked around now about what it is, what feature does this st*pid overdriving and if it's disableable somehow
Likely it still needs RSMU access, but maybe it's interoperable in the hidden by some other tool which has access to it
A hotfix passing through that way, soo the users with an NDA don't get problems by doing changes "against AMDs policy"
Maybe it will resolve ~by itself~ after time, but the WHEA #19 & #20 issue i can now point to something both platforms retail and reviewer, do showcase & experience
And honestly , at this current state ~nothing we can do about it~ *
New batch might/maybe have a higher FCLK limit, but they are not free from this issue 😔

* Maybe with a new microcode and SMU ~ who knows. 
Someday they have to face the existence of this issue after all. Their Rev.02 did not fix anything on that part & silicon still can be bronze rated. Nothing directly special there


----------



## PJVol

Veii said:


> Tho it's not for all options the case


Sure its not. I just tested a 5 maybe 7 functions (from APML list)


----------



## Akex

What do you think is the maximum safe voltage for the Micron EDIE? Knowing that on my BDIE I have been running at 1.65v for 3 years without any problem with 4 DIMMs for a temperature lower than 44 ° in summer on a TM5 of more than 6 hours.
I ask the question because I know that BDIE is special, but I admit that I am not too comfortable with EDIE.
Is 1.6v - 1.65v dangerous if I keep a good temperature?


----------



## PJVol

Veii said:


> They are coming from real spikes.


So, let's make it clear. You're talking about FCLK spikes that somehow you were able to observe? (so I could check myself)



Veii said:


> What CCD is disabled when people use the bios. Soo can they convert their dual CCD to one without problems
> Do consumer/retail batches , single CCD units also have the same abstract behavior @ and beyond 1900 FCLK
> What is this flag actually called and how to stop it from overdriving itself. It doesn't appear to be clockgating and clearly is not something the current CBS section of the bios gives access to




1. I think it can be easily figured out by looking at any succeptable to change while being at load, core groups (16 entries) in a pm_table, i.e. C0 c-state residency.
2. TBD
3. It's still not clear to me, how you came to the conclusion that it even exists.

btw, the browser didn't let me watch your video, smth wrong with secure connection


----------



## Veii

PJVol said:


> Sure its not. I just tested a 5 maybe 7 functions (from APML list)


Couldn't know about PSM , but you are right 
If we only knew the layout of it now


PJVol said:


> So, let's make it clear. You're talking about FCLK spikes that somehow you were able to observe? (so I could check myself)


Correct
Run any boost tester, anything that affinity loads one core, and you can see which CCD does overdrive there
If it's both or just one CCD
This behavior exists beyond 1800+ FCLK and continues up
Rev.A0 & Rev.B2













I've tried,
LN2 flags
OCMode forcing/disabling
Branch prediction & C+D States disabling
CBS, OC, Main menu FCLK fixation and 1:1 mode enforcement
Even allcores, nothing limits this from overdriving itself
The only time i could limit it bellow P0 state, only then it was error free and didn't overdrive. But on 4.2 soo "boost state" hard limited ~ it did overdrive and caused WHEA's again

Actually quite easy testable
Run higher FCLK or i think even 1900 1:1 should show this behavior
And light load/boost test each core & it will overdrive higher + cause #19 & #20 errors. Both together with the same amount even


----------



## ManniX-ITA

Veii said:


> And this is now an issue
> Because it makes WHEA Surpressor not the best option @ManniX-ITA
> They are coming from real spikes.


Is this relevant only for the B2 sample or all?

I have never observed this on my 5950x.
My flood of #19 is when at idle or under very high load.
Never had any "specific" #19 flow on single/light thread boosts eg. using BoostTester.


----------



## Audioboxer

Oh dear, 7 hours 49 minutes into a Karhu last night and another error. This is with VSOC back to 1.15v.

Really interesting to find out now what causes TM5 to pass standard length stability testing but Karhu craps out around 8 hours in. With a single error that long into testing its got to be something minor.

Tonight's test will be going to 1.56v and I'll bump up tRFC a bit. Fair to say I haven't had any apps crash or reboots over the past few months, but a single error is unacceptable. Memory isn't stable unless it remains stable! Again it's not temps, unless we're having errors at like 32 degrees on b-die.

The only thing I've changed recently is to go to telemetry overclocking on my 5950x, and I know an unstable CPU can crash TM5. Will keep this in mind, but CPU stability testing has stated my CPU is fine right now lol.


----------



## ManniX-ITA

Audioboxer said:


> The only thing I've changed recently is to go to telemetry overclocking on my 5950x, and I know an unstable CPU can crash TM5. Will keep this in mind, but CPU stability testing has stated my CPU is fine right now lol.


If you have set CPU Cache and/or Stress FPU errors could be due to CPU/IF stability and hence influenced by telemetry.


----------



## Audioboxer

ManniX-ITA said:


> If you have set CPU Cache and/or Stress FPU errors could be due to CPU/IF stability and hence influenced by telemetry.


I have yes, I read earlier on that was the best way to test stability.

What I might now do first is remove telemetry and run with the same timings on the memory!

Only other thing I did in combination with telemetry was move to a +100 AutoOC. I never used to run an AutoOC. Another thing to try on the CPU end. Probably makes sense actually crashing this far into testing is hitting a minor CPU stability opposed to memory.

Would explain all the prior hours of TM5 testing around these settings with no issues.


----------



## ManniX-ITA

Audioboxer said:


> What I might now do first is remove telemetry and run with the same timings on the memory!


I would do the same indeed!
If it's coming from the CPU you could have missed it in a previous Kahru run.
If you still get it without telemetry before blaming the memory run it without the CPU cache.


----------



## Veii

PJVol said:


> 3. It's still not clear to me, how you came to the conclusion that it even exists.
> 
> btw, the browser didn't let me watch your video, smth wrong with secure connection


A flag to disable this overdriving ?
Out of the RX cards which are very similar to Vermeer
Nametags, and effective clock behavior, just with more access

Else that is clearly not normal behavior, at least not intentional
It was kind of a thing back when dynamic FCLK and Dynamic SOC existed
But AMD had hardlocked such from Matisse and keeps being silent about this thing.

Honestly, i can't imagine that we since Matisse still haven't been able to get WHEA under control. Like actually, it starts to be embarrassing
Now i saw an orientation point, of something that actually did "temporary fix" #19 & #20
~ on a board where all conditions are met, with a sample before that is a perfect comparison how it has to be
And we still likely will not fix it. I can't believe it.
All because resources are under NDA , and people who have a bit more low level knowhow get banned or trying to get silenced (PSP Tool & exploits) by AMD themself

I'm ranting  Excuse me
But what did you mean with "conclusion" ?
It certainly is something strange and awkward
Effective clock should never reach levels far higher than set clock * ~ as it was the same with core boost "overboost"
(which is neither a HWInfo nor a MUTEX readout issue)
* unless dynamic FCLK is not disabled correctly and set correctly. An engineers mistake


ManniX-ITA said:


> Is this relevant only for the B2 sample or all?
> 
> I have never observed this on my 5950x.
> My flood of #19 is when at idle or under very high load.
> Never had any "specific" #19 flow on single/light thread boosts eg. using BoostTester.


Yes all of us, please doublecheck with this tool if you have the same current behavior
I had in hopes and by what i heard , that memOC has to be better on this new silicon ~ but the end result is, maaybe it's more efficient, but it still is completely bugged

The only potential reason known to me, AMD had to redo (two) revisions ~ is a security and PSP-FW risk. An exploit
But i struggle to believe, they where incapable to fix this. When the issue for them was known since at least March ~ with an very known attempt to lock down FCLK like it was on Matisse.

On the bright side, Zen 1 & 1+ now overclock very well and the ABL restriction got lifted








This and the G series, is by a friend of mine ~ who is not much about praising with scores
Idk if i should even mention the name, but it's not mine 
And i don't think it's 24/7 stable but rather XOC ~ yet it is "possible" , which it wasn't before


----------



## ManniX-ITA

Veii said:


> Yes all of us, please doublecheck with this tool if you have the same current behavior


Which tool? Tool 1007?


----------



## PJVol

Veii said:


> Run any boost tester, anything that affinity loads one core, and you can see which CCD does overdrive there
> If it's both or just one CCD
> This behavior exists beyond 1800+ FCLK and continues up


Nah, nothing like that so far...
Tried boostTester first, then CBR23 cycling through physical cores. (assuming, I got the story right, didn't i? )

PS: Playing with "hydra", did she say you've got an unique CPU again, at the end?


----------



## Veii

PJVol said:


> Nah, nothing like that so far...
> Tried boostTester first, then CBR23 cycling through physical cores. I thought I got it, didn't I?
> 
> PS: When playing with "hydra", did she say you've got an unique CPU again?


Ok but you don't got issues on 2000 ?
The thing i want to figure out is, do retail 5600X, 5800X, and dual CCD's who struggle to reach beyond 1900 actually struggle because Effective_FCLK overdrives for some bizzare reason ?

One CCD of this new unit, is fine - the other is overdriving for some unknown reason


ManniX-ITA said:


> Which tool? Tool 1007?


ZenPTMonitor , but also Tool.exe did show it - old 1007 without boardID lock and new with asus crosshair board-ID lock





Bios Modding & OC - Google Drive







drive.google.com






PJVol said:


> PS: Playing with "hydra", did she say you've got an unique CPU again, at the end?


Yes'n








That's 1.0E
But 1.0E+ got it fixed ~ contacted Yuri
So far only 2 people have this sample , but he should push the hotfix out soon
Well, at least it's balanced ~ to some extend, although bronze








WIP ~ gave up on PBO, as i do not expect any 1.2.0.5 till Mid December, if not even end of december
Needs a microcode update and an SMU update. AMD CBS & AMD OVERCLOCKING is half half functional.
That's translated to Bios CO
-26
+5
-37
-23
0 (-0.5)
-31
-31
-27
-27
Hopefully 1205 is soon out and hopefully they fix their limited CO range finally. Or allow a direct TEL VID undervolt ~ post CO VID drop








Platin/Silver
vs
Silver/Bronze
~ CPPC/ACPI
Both Rev.02


----------



## PJVol

Veii said:


> Ok but you don't got issues on 2000 ?


Yep, here is one (just din't **** the fabric edc throttller  )
And the PIE was hammered down with vdd18 *2V* on the right :👹


----------



## Imprezzion

TimeDrapery said:


> Yeah, you can likely set your primaries to
> 
> *15-15-15-30-45*
> 
> rather than what you're at, your *SCLs* can likely go to *4*, your *tCWL* (...*9*?) should increase to *14* and then you should try dropping *tWRRD* to *2* and *tRDWR* to *9* (seems like you had a mix-up, 🤭)
> 
> Also, drop *tRFC* to *272*/*202*/*124* or *270*/*201*/*123*
> 
> Likely that'll all help your latency out a good bit
> 
> As an aside, drop *CLDO VDDP* to *940mV* from *1000mV* and play with *CCD*/_*IOD*_... I'd look at *1020mV* for *CCD* and *1100mV* for *IOD* with *VSOC* at *1.175V*
> 
> I'd also reduce *ProcODT* to *34.3Ω*/*36.9Ω* and set *RTTs* to something like *6*/*3*/*3*, *7*/*3*/*3*, *7*/_*3*_/_*1*_
> 
> As another aside you should play with *drive strengths*... Something like... *40.0Ω*/*20.0Ω*/_*20.0Ω*_/_*20.0Ω*_, *40.0Ω*/_*20.0Ω*_/*24.00Ω*/_*24.0Ω*_, or *40.0Ω*/*20.0Ω*/*30.0Ω*/*20.0Ω*
> 
> Mine's single rank but the timings aren't impossible and mostly apply to your B-die as well
> 
> View attachment 2535393


Does tuning of ProcODT, RTT and drive strength directly impact performance or only stability. I mean, it it passes with my current settings (which are mostly Auto btw) do I really have to change them and go down the rabbit hole of hours and hours of testing?

I did change the primaries, SCL, tRFC, tWRRD, tRDWR and tWR like you mentioned which yes, I did mix up. Oof 😅. Re-testing now but only for an hour or so I wanna play some BF2042 later tonight after dinner lol.


----------



## Veii

Imprezzion said:


> Does tuning of ProcODT, RTT and drive strength directly impact performance or only stability. I mean, it it passes with my current settings (which are mostly Auto btw) do I really have to change them and go down the rabbit hole of hours and hours of testing?


If you have no intention in continuing memOC
Then it is better, logical to not touch powering and just finish with it

But if you want to do more of this "go down the rabbit hole and do hours & hours of testing"
Then yes ~ you should consider this. Alone as thermals improve with weaker RTT_Park
And the CPU will thank you, by needing less procODT
Hence neither procODT nor cLDO_VDDP , should be used for dimm powering


----------



## Akex

Akex said:


> What do you think is the maximum safe voltage for the Micron EDIE? Knowing that on my BDIE I have been running at 1.65v for 3 years without any problem with 4 DIMMs for a temperature lower than 44 ° in summer on a TM5 of more than 6 hours.
> I ask the question because I know that BDIE is special, but I admit that I am not too comfortable with EDIE.
> Is 1.6v - 1.65v dangerous if I keep a good temperature?


Little up to my question, friends 😅


----------



## Imprezzion

Veii said:


> If you have no intention in continuing memOC
> Then it is better, logical to not touch powering and just finish with it
> 
> But if you want to do more of this "go down the rabbit hole and do hours & hours of testing"
> Then yes ~ you should consider this. Alone as thermals improve with weaker RTT_Park
> And the CPU will thank you, by needing less procODT
> Hence neither procODT nor cLDO_VDDP , should be used for dimm powering


At least it did the full hour with no issues after fixing the timings you mentioned even at 44c as I have my heater on lol. It's cold outside 
Imma go game now first, probably BF2042 and Forza Horizon 5. 
Will do ProcODT, CLDO, VDDP and such on a later date after the weekend when I have to work again.


----------



## Veii

Akex said:


> Is 1.6v - 1.65v dangerous if I keep a good temperature?


I run them at 1.68-1.72
PCB fails on B-die near 1.69
On Rev.E was after 1.72

Voltage means nothing, all up to RTTs
Stability wise

There is also not a "dangerous" part, unless you exceed this 1.7 wall
Or run A0 PCBs which are oversensitive to overcurrent (A)
Every brand is different, and custom PCB builds by them too
You'll figure by yourself out , after when the PCB starts to fail , as it's not the ICs "that can not do it"


----------



## Veii

Imprezzion said:


> At least it did the full hour with no issues after fixing the timings you mentioned even at 44c as I have my heater on lol. It's cold outside
> Imma go game now first, probably BF2042 and Forza Horizon 5.


No half work, full 20+ loops , same as full 4 loops of y-cruncher
72min y-cruncher plus how long it ever takes for your capacity of ram
16GB take ~1:30h, 32GB take around ~3h , normal

1h runs, just put your dimms at thermal equilibrium
Yet does not guarantee that things like tREFI or tRFC are fine by time
You "just figured out your temps" ~ with this 1h run , not much more 
Run it full, and have the confidence that they are stable ~ instead of having to waste next time another 3-4h , because you gifted away your 1h runtime

Else, after cold boot ~ it's still recommend to run it once more
Soo after 3h+ power-off time (just on the next day)
As memory training might have been fine now, but can not guarantee it will be fine on the next day again


----------



## Imprezzion

Veii said:


> No half work, full 20+ loops , same as full 4 loops of y-cruncher
> 72min y-cruncher plus how long it ever takes for your capacity of ram
> 16GB take ~1:30h, 32GB take around ~3h , normal
> 
> 1h runs, just put your dimms at thermal equilibrium
> Yet does not guarantee that things like tREFI or tRFC are fine by time
> You "just figured out your temps" ~ with this 1h run , not much more
> Run it full, and have the confidence that they are stable ~ instead of having to waste next time another 3-4h , because you gifted away your 1h runtime
> 
> Else, after cold boot ~ it's still recommend to run it once more
> Soo after 3h+ power-off time (just on the next day)
> As memory training might have been fine now, but can not guarantee it will be fine on the next day again


Meh. I saved the profile and went back to DOCP + PBO2 so I can play some games with my mates.

It didn't like gaming. Aka it WHEA_UNCORRECTABLE_ERROR BSOD'd after like 2 minutes lol. Raising vSOC did nothing to fix it so it ain't happy lol.

Will figure it out next week. I wanna play some stuff this weekend so DOCP PBO2 it is.


----------



## Veii

Imprezzion said:


> Will figure it out next week. I wanna play some stuff this weekend so DOCP PBO2 it is.


Start with y-cruncher and get your CPU to be rock stable
PBO on it's own only does negative things, unless you exactly know how to work with CO's
Releasing first stage limiters, only increases supplied voltage = cores throttle faster

That should be only done, if you use CO - soo the values remain correct
Else enabling PBO, will result in worse perf


----------



## tcclaviger

@Veii #2 error, for me, has only ever been too low SOC voltage. I've had it come up twice and both times resolved with soc, once by stepping up from 1.15 to 1.175, second time from LLC auto on SOC to LLC2 to prevent the lowest droops.

IRT behavior of FCLK based WHEA, my CPU behaves as yours. Idle I get nothing, hit it with a boosting load and 19s start showing up. Suggests similar cause, overdriven FCLK.


----------



## Veii

tcclaviger said:


> @Veii #2 error, for me, has only ever been too low SOC voltage. I've had it come up twice and both times resolved with soc, once by stepping up from 1.15 to 1.175, second time from LLC auto on SOC to LLC2 to prevent the lowest droops.
> 
> IRT behavior of FCLK based WHEA, my CPU behaves as yours. Idle I get nothing, hit it with a boosting load and 19s start showing up. Suggests similar cause, overdriven FCLK.


Can you figure out how CCD is labled and which one is affected

Also try please to see if the "correct" CCD the non broken one is kept up ~ or the bios always wipes the wrong one (by disabling one)
If this really is purely related to these random spikes how it shows for me ~ then potentially it makes sense to buy dual CCD units, just to disable one
A 5800X technically is anyways a better gaming CPU ~ access time wise
Just i haven't seen anybody "out of nowhere" have a higher memOC by disabling a CCD. Soo likely the bios doesn't disable the correct one

Something to add
My 5600X only runs on CCD2 , or the 2nd
Sadly i lack sample size on current finding, to know if it always is X CCD, if it's different and if single CCD problematic units, just experience this overdrive issue

It's quite logical that when you peak to 2600 FCLK (also on idle as it's the first CCD for me) , that you get random WHEA's


----------



## lunatik

Veii said:


> 3D Mark timespy CPU test showed positive and negative scaling with 3800 vs 4000
> 4200 was slower but that can mean many things including too strong eat into the powerbudget
> 
> Yes, Timespy is as close as it comes to games
> probably also Unigine Superpostition custom all to extreme except resolution. No optimized resolution as such is less heavy
> 
> Bar Mode syncs CPU frame time to GPU frame time
> Keep this in mind, especially for CoD titles
> If your CPU is unstable , the GPU will get too - same reverse
> This also counts for 3D Mark benchmarking


I think that latency being "weird" on my DR kit running 4000/2000 was because of a new win 11 install and some settings being wrong at that time. All good now again.
My daily: 1.48V on RAM









And TimeSpy: I scored 13 590 in Time Spy (this was at 4.75 ghz all core, on a 25 euro cpu cooler)

Edit: I knew my 4000 c16 profile had mismatched tPHYRDL 26/28 (vddp 1v) for a long time. Recently i thought to just try all kinds of VDDP voltages to see if i could get it correct. So at 1 point i changed it 0.8 or 0.7, cant remember exactly and it wouldn't boot anymore but after that when i changed it back to 1V it went 26/26 

Edit: Also, what soc/ccd/iod/vddp voltages are considered safe for daily usage? I know i could boot 4200/2100 with same timings on the 4400cl 19 2x SR Vipers with a ton of whea's..


----------



## Imprezzion

Right. I royally messed up again. I wanna go too fast because of the limited time I had last week. The crash in game wasn't RAM it was CPU all along so yeah I should listen to @Veii more lol.

-23 all core is a no-go in BF2042. Back to -20 with no offset and auto LLC as I at least tested that with corecycler properly and that seems to be running fine so far. It does get blimming hot tho even with my custom loop and TechN block. These CPU's are no joke to cool. I see as high as 75c on the hottest CCD.

I set the RAM back to the 3800 profile I tested earlier today and that runs fine with CPU at actually tested levels.

Is there a way to get a all-core OC without using PBO that still sleeps cores and has idle power saving?


----------



## Veii

lunatik said:


> Edit: Also, what soc/ccd/iod/vddp voltages are considered safe for daily usage? I know i could boot 4200/2100 with same timings on the 4400cl 19 2x SR Vipers with a ton of whea's..











AMD max overclocking voltage


Hello, I'm new to overclocking and I'm not shure about the max "safe" voltages on an amd 5000 platform. I have a 5950x a asus crossfire dark hero and a gskill 4000 cl16 kit. I have a kind of stable profile where i did only memory, soc, and fclk overclocking. memory voltage = 1.51 v, soc = 1.3 v...




www.overclock.net




IOD bellow 1.15, surely bellow 1.2 but bellow 1.15 to prevent damage
CCD bellow 1.1, rec near and bellow 1.05
cLDO_VDDP bellow 1.15, 1.2 can fry some IMCs

Else the post above for more common values


Imprezzion said:


> Is there a way to get a all-core OC without using PBO that still sleeps cores and has idle power saving?


per CCX OC with VID target, not vcore override - every bios should have this


----------



## tcclaviger

Veii said:


> Can you figure out how CCD is labled and which one is affected
> 
> Also try please to see if the "correct" CCD the non broken one is kept up ~ or the bios always wipes the wrong one (by disabling one)
> If this really is purely related to these random spikes how it shows for me ~ then potentially it makes sense to buy dual CCD units, just to disable one
> A 5800X technically is anyways a better gaming CPU ~ access time wise
> Just i haven't seen anybody "out of nowhere" have a higher memOC by disabling a CCD. Soo likely the bios doesn't disable the correct one
> 
> Something to add
> My 5600X only runs on CCD2 , or the 2nd
> Sadly i lack sample size on current finding, to know if it always is X CCD, if it's different and if single CCD problematic units, just experience this overdrive issue
> 
> It's quite logical that when you peak to 2600 FCLK (also on idle as it's the first CCD for me) , that you get random WHEA's


Will try running single CCD tomorrow and checking, would be quite interesting if I can run 5800x mode and not get WHEA 19s...Hydra pegged them as CCD1 gold CCD2 Silver. Core 14 is an absolute dog though, hopefully if it works, it works on CCD 1.


----------



## Lobstar

Thought I'd chime in and mention I've been using 1usmus' default B-Die timings for a few months and they have been a great daily driver on my 4x 8gb Patriot Viper Steel 4400 CL19 sticks. If anyone else is using these I'd recommend those settings. Like Ron Popiel set it and forget it.


----------



## Worldwin

Can someone direct me on what to change to get rid of the error?


----------



## umea

Worldwin said:


> View attachment 2535569
> 
> Can someone direct me on what to change to get rid of the error?


change tRC -> 45 (tRC=tRP+tRAS)
#0 usually is not enough vdimm iirc


----------



## Imprezzion

Copy paste from the Ryzen google calculator spreadsheet 

Error #0

"Processor controller : freq, voltage, CWL
- mirrormovie and mirrormovie128, in this case, 
the error itself will be detected at startup Refreshstable 
(the beginning of any SimpleTest)

Interface (""digital"" timings): 
tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE"

So yeah, can be many things lol.


----------



## Audioboxer

So another Karhu failed just over 6 hours with PBO disabled and telemetry disabled. Ran a "quick" TM5 25 cycle and it was fine.

This is going to be interesting trying to find out what is causing a Karhu error at like 6-8 hours. I looked back through this topic and the longest I had previously ran a Karhu run before now was like 4.5 hours. Guess that explains why it might have passed no problem.

Up next will be running Karhu without the CPU Cache option. If that doesn't help then I guess it's a slow backwards process of trying to find what timing it is. Or with testing going on that long and TM5 seeming to be fine I'm going to guess minor issue with voltage or resistance.


----------



## Dziarson

No stres i love my wife kids Unify-x and 5600X 
Dual ranked gskill 3800CL14 test mem want to boot CL14 change to 16 and "TA DA" 





















And then is oportunity absolutly unstable


----------



## Veii

Worldwin said:


> View attachment 2535569
> 
> Can someone direct me on what to change to get rid of the error?
> 
> 
> Imprezzion said:
> 
> 
> 
> Copy paste from the Ryzen google calculator spreadsheet
> 
> Error #0
> 
> "Processor controller : freq, voltage, CWL
> - mirrormovie and mirrormovie128, in this case,
> the error itself will be detected at startup Refreshstable
> (the beginning of any SimpleTest)
> 
> Interface (""digital"" timings):
> tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE"
> 
> So yeah, can be many things lol.
Click to expand...










Yes, powering related
Not always has to be voltage ~ depends on the amount, and when they came / the zero's
mostly just a too noisy signal , soo CAD_BUS related


Audioboxer said:


> and TM5 seeming to be fine I'm going to guess minor issue with voltage or resistance.


The fridge or stove got started


----------



## Audioboxer

Veii said:


> View attachment 2535590
> 
> Yes, powering related
> Not always has to be voltage ~ depends on the amount, and when they came / the zero's
> mostly just a too noisy signal , soo CAD_BUS related
> 
> The fridge or stove got started


lol unsure if that's a nod to claims of PC instability if home appliances are turned on whilst the PC is stability testing 😂

I'm a bit stumped but there should be clarity once CPU cache is set to default/disabled. If so I presume TM5 is more memory focussed whereas Karhu can hit IF/CPU harder.

I've never seemed to have any issues at 1900, no WHEA or reboots, so if it's something here hopefully just VDDG, VDDP or VSOC needs a small tweak. Even Corecycler/y-cruncher haven't picked up anything on the CPU end.

I guess it could show the value of having multiple stability testing apps!


----------



## Imprezzion

Well, it does kind of work, a per-ccx OC it's custom VID, but it needs so much juice to run like, 4.9 CCD1 4.825 CCD2. Something along the lines of 1.420v with LLC4 to even dream of passing a stress test which is both too high and too hot. Mid 80's in CB23. I mean, the score is amazing, well over 24k, but yeah.. let's not. 

How does the "performance bias" option affect RAM benches in AIDA? I had it set to off. Would that also contribute to me missing about 3ns of latency performance?


----------



## Audioboxer

AGESA 1.2.0.5 seems to be rolling out



> *ASUS ROG CROSSHAIR VIII Series 3903 BETA BIOS*
> 
> Changelog:
> 
> 
> Some bug fixes
> Update AGESA version to ComboV2PI 1205 (same 3902)
> *ASUS ROG CROSSHAIR VIII Series 3902 BETA BIOS*
> 
> Changelog:
> 
> 
> Improve system performance
> Update AGESA version to ComboV2PI 1205


Seems AMD looked at the mess they made with 1.2.0.4 and decided we best just skip it completely.

Interested to see what MSI do with SMU seeing as they rolled back the SMU version on their 1.2.0.3 releases compared to ASUS/others.


----------



## Imprezzion

This is where I'm at now. Looks good to me right?


----------



## Audioboxer

Imprezzion said:


> View attachment 2535594
> View attachment 2535595
> 
> 
> This is where I'm at now. Looks good to me right?


tWRRD to 3 is preferred for DR I think. tRDWR at 8 is worth testing. ProcODT can probably be set to 36.9 fine. If VSOC is on AUTO it might need set a bit higher to help with stability.

Once you're happy with timings and they are stable you can try for 1T. Almost certain to need a CmdSetup time of 55 or 56 and along with that ClkDrvStr of 40 or there abouts.


----------



## Blameless

Imprezzion said:


> This is where I'm at now. Looks good to me right?


If you need that VDDG IOD to be stable, you are going to want a ~15mv bump to loaded SoC voltage to make sure it never droops down far enough to reduce VDDG. If you don't need that much VDDG, turn it down to prevent jitter on it, as it's too close to vSoC.


----------



## Imprezzion

Blameless said:


> If you need that VDDG IOD to be stable, you are going to want a ~15mv bump to loaded SoC voltage to make sure it never droops down far enough to reduce VDDG. If you don't need that much VDDG, turn it down to prevent jitter on it, as it's too close to vSoC.


Oh I don't know tbh. This is Auto for VDDG and vSOC. I will play with it a bit. How much lower should I put it? Also 15mv or so?


----------



## Audioboxer

Imprezzion said:


> Oh I don't know tbh. This is Auto for VDDG and vSOC. I will play with it a bit. How much lower should I put it? Also 15mv or so?


Somewhat pulling this out of my arse but VSOC for 1900/3800 is probably best set around 1.125~1.15v and just rolling with that. With that set of memory you can probably push for tCL14, whether you settle on 14-15-15-15 or if you get lucky and tRCDRD 14 will work. The IMC is likely to need more voltage on VSOC to handle what is going on if you continue to push more out of your memory. I've seen people post at 3800/1900 with VSOC as low as 1.08~1.09v, but I just wouldn't trust that. Not if you're going to push secondaries as hard as you can as well.

This obviously depends on your VDIMM as well which I don't know and your cooling, because if your temps are higher flat 15 with a lower VDIMM might just be the way forward at 3800. VDDP can probably come down to 0.9~0.93v. Shouldn't need to be as high as 1v.


----------



## Blameless

Imprezzion said:


> Oh I don't know tbh. This is Auto for VDDG and vSOC. I will play with it a bit. How much lower should I put it? Also 15mv or so?


I would test 1.1 vSOC and 1.025-1.03 vDDG IOD, but what you need will be heavily dependent on sample. Regardless the gap between load vSoC and CLDO VDDG should be around 50mV.

Also, I second Audioboxer's recommendation of reducing VDDP. Keep CPU VDDP and CLDO VDDP the same and use the lowest value that reliably trains to tPHYRDL 26 on both channels. This will probably be somewhere between 850 and 950mV.


----------



## tcclaviger

@Veii
Doing 1CCD 5950x testing. Not sure if it's my MB, or all, but I can't select CCD2 as the active, only CCD1 when in 8 core config.

Interesting result that I think suggests the issue as lying in the IOD, in the interconnect between IOD and CCD, or voltage/resistance issues at power greater than X between CCD/IOD causing a timing missmatch.

Wait: Doesn't Ryzen have power circuitry on die, seem to remember it has some amount of it.

Will some more investigation on what X might be and see if limiting package power or SOC power can reduce WHEA occurrence.

EDIT: Actually, appears to be SMT related, testing more now.

Single core Tests: No WHEAs.
2 Active Cores: No WHEAs.
4 Active Cores: No WHEAs.
6 Active Cores: No WHEAs.
7 Active Cores 126w: No WHEA
14thread at 154w: Very slow WHEA generation.
8/16thread Active Cores 160w: Slowly creating error 19s, but only 19s, and the rate is far reduced from both CCDs active.

As far as 5800xs go, lol it becomes a pretty good one, at 160 watts:
In R23:
4850 PBO/CO all core 
4925 PBO/CO 7 core
4950 PBO/CO 6 or 4 core
5130 PBO/CO single


----------



## tcclaviger

It's wattage.

140 watt cap, no more WHEA 19s on single CCD mode.

16150 vs 16300 score, not a terrible loss.

Now I'm curious if I can create the same thing with 2CCD scenario.

EDIT: 2 CCD Tests for CPU work loads.

Loads tested EDC at 221 TDC at 160 in BIOS for all settings, same CO, voltage, RAM, SOC settings for all -
100 TDC, 175 EDC, 140PPT (PPT limited) - No WHEAS

120 TDC, 205 EDC, 170PPT (PPT limited) - No WHEAS

125 TDC, 213 EDC, 180PPT (PPT limited) - Very slow WHEA 19 generation, less than 1 a minute.

138 TDC, 221 EDC, 200PPT (PPT limited) - quick WHEA 19 generation during work, none at idle.

The instant I fire up a 3d app, Shadow of the tomb raider, spam of WHEA 19, but only while the app is starting then they stop. Roughly 55 interconnect errors each time the game loads up, then none.

Dynamic LCLK maybe?


----------



## KedarWolf

I'm using the AGESA 1.2.0.5 A45 MSI Unify-X BIOS.

it's stable but I lose 200 points in CPU-Z multi-core and 20 points in single-core over A21.

Single-core 688 vs 668.

I lose 150 points in CB23 multi-core as well.


----------



## Imprezzion

Audioboxer said:


> Somewhat pulling this out of my arse but VSOC for 1900/3800 is probably best set around 1.125~1.15v and just rolling with that. With that set of memory you can probably push for tCL14, whether you settle on 14-15-15-15 or if you get lucky and tRCDRD 14 will work. The IMC is likely to need more voltage on VSOC to handle what is going on if you continue to push more out of your memory. I've seen people post at 3800/1900 with VSOC as low as 1.08~1.09v, but I just wouldn't trust that. Not if you're going to push secondaries as hard as you can as well.
> 
> This obviously depends on your VDIMM as well which I don't know and your cooling, because if your temps are higher flat 15 with a lower VDIMM might just be the way forward at 3800. VDDP can probably come down to 0.9~0.93v. Shouldn't need to be as high as 1v.


1.50v vDIMM right now. I can get away temp wise with as high as 1.60v if I raise the RAM fan speed but I don't wanna go much higher then 1.55v if I don't have to due to higher ambients in the summer.

Trying to get C14 to boot at the moment.

K so both C14 and C15 with 1T do not POST with a "22" debug code. No idea how to fix that one.


----------



## tcclaviger

LCLK DPM disabled - no WHEA change
LCLK DPM auto detect gen 4 - no WHEA change
LCLK DPM locked at 300mhz - no WHEA change
LCLK DPM locked at 600mhz - no WHEA change

Starting to suspect SMU itself. If it were LCLK issue these should have made a difference, at least for the worse.

CPU when working totally within L3 it is fine.
CPU interconnect to RAM is fine.
As soon as activity hits CPU to GPU, WHEA in either 1CCD or 2CCD modes, but not always, GPUz render test for example doesn't trigger it.

EDIT: SotTR has Denuvo again right? Other 3d apps aren't triggering it. If SotTR is doing a Denuvo check as loading up, might be a clue (does Denuvo access SMU for CPU details?).

Gen 4 PCIE SSD connected to CPU or SB doesn't trigger.
Heavy ram loading while accessing Gen 4 SSDs don't trigger.

Something about GPU use is my last WHEA cause and the most reliable trigger, starting SotTR. Metro Exodus for example only trigger 2 WHEA events instead of 50+.


----------



## Robby37

Can anyone help me. I found this screen shot earlier on in my tuning I ended up dropping down to 3600 with slightly tweaked timings but I had 3733 stable as well. I updated my bios and forgot to backup so I lost my settings and only have these before I tweaked a little more. I cannot remember what I had to change but I know I had some sub timings wrong as far as the spreadsheets and stuff.


----------



## tcclaviger

Trcdrd 15
Trc 45
Trrds 4 
TrrdL 4 or 6
tFAW 16
ProcODT @ 40 
Drop IOD voltage to 1.05 or less
Raise SOC to 1.1-1.125
And fix trfc to method of choice is where I'd start on those.


----------



## Audioboxer

Imprezzion said:


> 1.50v vDIMM right now. I can get away temp wise with as high as 1.60v if I raise the RAM fan speed but I don't wanna go much higher then 1.55v if I don't have to due to higher ambients in the summer.
> 
> Trying to get C14 to boot at the moment.
> 
> K so both C14 and C15 with 1T do not POST with a "22" debug code. No idea how to fix that one.


Are you running the Setup time of 55 or 56? While I can boot 1T without setup times, it's unstable as all hell. Many sticks of DR won't even post without setup times with 1T/GDM disabled.


----------



## tcclaviger

@Veii what app is that zen PTmonitor? Searched didn't find anything, wanted to check for FCLK EFF overspeed as you've done to confirm it.

Private software?


----------



## Worldwin

Veii said:


> View attachment 2535590
> 
> Yes, powering related
> Not always has to be voltage ~ depends on the amount, and when they came / the zero's
> mostly just a too noisy signal , soo CAD_BUS related
> 
> The fridge or stove got started











Loosening TRRD/TFAW/TWTR has brought errors in test 15 while still being present.
It annoys me like crazy I can't POST while every secondary/tertiary is at auto so I can start basically fresh. I have to basically goosechase and figure out what the error is.
Also anyone else have the issue where TM5 just stops working? Like in my included image for the last 3 minutes no test were running.


----------



## Luggage

KedarWolf said:


> I'm using the AGESA 1.2.0.5 A45 MSI Unify-X BIOS.
> 
> it's stable but I lose 200 points in CPU-Z multi-core and 20 points in single-core over A21.
> 
> Single-core 688 vs 668.
> 
> I lose 150 points in CB23 multi-core as well.


1205test optimized default


http://imgur.com/a/Y6DP18j


1293C optimized default


http://imgur.com/a/dQBzTBn


Gonna try mem and pbo now...


----------



## PJVol

tcclaviger said:


> Starting to suspect SMU itself


Why suspect, if it's clearly said that the PIE raised an exception.
And there's a number of whea19 scenarios where gpu isn't involved at all.
i'd rather dig in a CCM-IOD direction, or TCDX0/TCDX2 as a possible source.


----------



## Veii

tcclaviger said:


> @Veii what app is that zen PTmonitor? Searched didn't find anything, wanted to check for FCLK EFF overspeed as you've done to confirm it.
> 
> Private software?


By XEHOPE3 ~ pre-alpha
Irusanov mentioned, that he has not updated Github code yet for it
Eff FCLK overdrive check , which will happen on only one CCD
Ty for the PPT check ~ it increases "reason" or "confirming" that it is load balanced and it's an overdrive feature

For some CPUs less for some more
Starting from 1800 FCLK and higher
You can just run MCLK at lower freq, and FCLK at higher @ 1.2v SOC
that's plenty for anything between 1933 & 2000
But as the overdrive happens on some at 1800 already, you should clearly see it doing something at 1900
And i think you will, else you wouldn't report such #19's
As for non affected users, package throttle exists, but it doesn't spill out such errors. it just crashes

It only spills out such errors if you do really stupid stuff like run 2167+, mostly 2200+

EDIT:
Important to me is
Which CCD does it for you, as all cores in the same CCD will do it
and which one does the bios disable + does it still do it, with the "wrongly?" disabled CCD

You should see overdriving on as low load as 12W ~ 17A , via boost tester
on all cores in the affected CCD
but "no overdrive" on the other CCD at any load
also no overdrive with TM5 running , although it's mem access
and no overdrive while Copy , Read, Write Aida64 is running or the same for L3
It's only on distant short burst latency checks, where it increases itself too high and errors

EDIT2:


Luggage said:


> 1205test optimized default


CO's behave differently with 1205, and there should be another layer of undervolting
Please don't use old COs on it, it will not perform well


----------



## Audioboxer

KedarWolf said:


> I'm using the AGESA 1.2.0.5 A45 MSI Unify-X BIOS.
> 
> it's stable but I lose 200 points in CPU-Z multi-core and 20 points in single-core over A21.
> 
> Single-core 688 vs 668.
> 
> I lose 150 points in CB23 multi-core as well.


Just noticed this, was surprised ASUS beat MSI, MSI are usually first!

Sucks on the result though, ASUS users were supposedly reporting better boosting and performance 

Will have to at least check WHEA/FCLK 2000 with this, but I suspect there will be zero change.


----------



## PJVol

Veii said:


> By PJVol


Lol, you're the 2nd who think its mine, but i remember you confused us before, oh those russians...

And btw, I think the overdrive that you see, is just the side-effect of the SMU unable to keep-up updating APERF registers for the fclk when the exception handled (i suspect in SMM), considering the requirements that should be met for the eff. CCLK calculation, such as no more than 3 MOV instructions, disabling interrupts, etc. between register writes, no matter who actually calculate them, smu or the user itself.


----------



## Luggage

Audioboxer said:


> Just noticed this, was surprised ASUS beat MSI, MSI are usually first!
> 
> Sucks on the result though, ASUS users were supposedly reporting better boosting and performance
> 
> Will have to at least check WHEA/FCLK 2000 with this, but I suspect there will be zero change.





Veii said:


> By PJVol ~ pre-alpha
> Irusanov mentioned, that PJVol has not updated Github code yet for it
> Eff FCLK overdrive check , which will happen on only one CCD
> Ty for the PPT check ~ it increases "reason" or "confirming" that it is load balanced and it's an overdrive feature
> 
> For some CPUs less for some more
> Starting from 1800 FCLK and higher
> You can just run MCLK at lower freq, and FCLK at higher @ 1.2v SOC
> that's plenty for anything between 1933 & 2000
> But as the overdrive happens on some at 1800 already, you should clearly see it doing something at 1900
> And i think you will, else you wouldn't report such #19's
> As for non affected users, package throttle exists, but it doesn't spill out such errors. it just crashes
> 
> It only spills out such errors if you do really stupid stuff like run 2167+, mostly 2200+
> 
> EDIT:
> Important to me is
> Which CCD does it for you, as all cores in the same CCD will do it
> and which one does the bios disable + does it still do it, with the "wrongly?" disabled CCD
> 
> You should see overdriving on as low load as 12W ~ 17A , via boost tester
> on all cores in the affected CCD
> but "no overdrive" on the other CCD at any load
> also no overdrive with TM5 running , although it's mem access
> and no overdrive while Copy , Read, Write Aida64 is running or the same for L3
> It's only on distant short burst latency checks, where it increases itself too high and errors
> 
> EDIT2:
> 
> CO's behave differently with 1205, and there should be another layer of undervolting
> Please don't use old COs on it, it will not perform well


yea lower voltage, lower power, lower temps, lower performance. :/

I guess too many complaints about hot chips?


----------



## Bix

ManniX-ITA said:


> Good luck and let us know the results!


OK, firstly apologies for the massive data splurge... I’m trying to do things properly this time! I’ve tested each FCLK/MCLK step with the same PBO settings and memory timings from 1800 up to 2033 with a variety of benchmarks to check for performance degradation and to try and find out which might be the most performative before I go any further tuning PBO and memory.










Testing:
I ran each benchmark 5 times at each FCLK/MCLK step to get an average, except for the miner, which I ran 3 times for 15mins. 

Caveats:
Auto voltages were used until too unstable to pass benchmarks (1967 FCLK and beyond), at which point I switched to the VDDP and VDDG voltage combination that seems to work best at my current 2000 FCLK (see below), and adjusted VSOC roughly for each step as required. Linpack seems to be the most temperamental when it comes to VSOC so once it passed all 5 runs I then proceeded with the other benchmarks. This obviously isn’t ideal for a totally fair test since the VDDP and VDDG voltages are not optimised for each step (this would have taken a LOT longer!) but hopefully this is adequate to get a rough idea of the overall picture. 
The 1T memory profile I used was also created at 2000 FCLK (hence tCKE 11). This worked as far as 2033 but won’t post any higher without loosening the timings so I stopped there. (I can post at 2100 FCLK with XMP and previously experimented with a variety of voltage combinations but struggled to find any kind of stability.)

Settings:

PBO: PPT 400W, TDC 160A, EDC 200A, Scalar x10, Boost override Auto, C/O 29,2,30,4,30,24,24,8,18,22,23,19 (all negative)
All LLC etc set to Auto. VSOC droop seems to be around 25mV.


FCLK1800​1833​1867​1900​1933​1967​2000​2033​VSOC (set)AutoAutoAutoAutoAuto1.1​1.1375​1.1625tPHYRDL26​26​28/2628/2628​28​28​28​WHEA 19?NoNoNoNoNoYesYesYes

For 1967 FCLK and above I used 0.9V VDDP, 0.94V CCD and 1.060V IOD.

Here's my memory profile:










Observations:
First off it’s a predictably messy picture – aside from AIDA which neatly scales with FCLK all of the other benchmarks seem to prefer different FCLKs. The miner seems to peak in performance at 1967 with an unusually poor hash rate at 1900 (I retested as it looked odd and got very similar results). Hash rates at 2000 and 2033 only drop slightly but not sure if this should be considered problematic.
I’ve never fully understood the Sandra Inter-core bandwidth test so not sure how to interpret these results. The highest score I ever got for this test was 166 but that was with XMP before doing anything with memory timings.
WHEA 19 warnings begin appearing at 1967 but only intermittently and tPHYDRL is mismatched at 1867 and 1900 but I’m finding it difficult to see in the results what impact these have on overall performance. 

Where would you go from here?? My (uneducated!) interpretation is that my sweet spot is probably at 1967, 2000 or 2033 and the next step should be to do some more work on finding optimal VSOC and Co. to see which one of these three comes out on top. Would be very grateful for a steer


----------



## Veii

PJVol said:


> Lol, you're the 2nd who think its mine, but i remember you confused us before, oh those russians...


This has to be a trauma from Hrenore's name. Trying not to write it, spell it or swear ~ soo forgetting things he published and the name itself
You know, i'm sorry :I

Also ty~


----------



## Luggage

@Veii so aside from having to redo CO... any idea why VID LIMIT dropped from 1.5 to 1.425 and how to get around it?


----------



## Worldwin

Lowering ClkDRVSTR from 40->30 seems to have gotten rid of error 0. Can't figure out error 15.


----------



## domdtxdissar

Luggage said:


> @Veii so aside from having to redo CO... any idea why VID LIMIT dropped from 1.5 to 1.425 and how to get around it?


EDC 140 and its back to 1500mv


----------



## Audioboxer

Luggage said:


> yea lower voltage, lower power, lower temps, lower performance. :/
> 
> I guess too many complaints about hot chips?


Not sounding good. So CO will need to be redone for what could be lower performance?

Might just stay on 1.2.0.4 unless anyone reports FCLK improvement.


----------



## Luggage

domdtxdissar said:


> EDC 140 and its back to 1500mv


Didn't see this and now I reverted. But anyway... that's too low edc


----------



## ManniX-ITA

Veii said:


> But as the overdrive happens on some at 1800 already, you should clearly see it doing something at 1900


Made a run with BoostTester and Tool1007.
My actual FCLK is quite solid at 2000, goes down to 199x not very often and I've seen a few times 2013-2017.
Doesn't seem to be in sync with WHEA 19.


----------



## ManniX-ITA

Bix said:


> Where would you go from here?? My (uneducated!) interpretation is that my sweet spot is probably at 1967, 2000 or 2033 and the next step should be to do some more work on finding optimal VSOC and Co. to see which one of these three comes out on top. Would be very grateful for a steer


Great job!
I would focus on getting the best out of FCLK 2000.
Fine tuning of CCD/IOD and VSOC should be enough considering where you are.


----------



## Imprezzion

Audioboxer said:


> Are you running the Setup time of 55 or 56? While I can boot 1T without setup times, it's unstable as all hell. Many sticks of DR won't even post without setup times with 1T/GDM disabled.


Yeah I tried both, both results in a hang on 22 post code. 

I did play BF2042 all evening with a few mates and the CPU and RAM run great. No weirdness at all at 3800C15 profile with the CPU at -20 curve +100 boost -0.08125 offset. Temps are fine, the two top cores just kissed 70c while the rest sat around 63-65c. RAM gets up to 45c but no instability at those temps. It was fine at 45c on Intel 4400C17 as well so not too worried.


----------



## tcclaviger

Veii said:


> By XEHOPE3 ~ pre-alpha
> Irusanov mentioned, that he has not updated Github code yet for it
> Eff FCLK overdrive check , which will happen on only one CCD
> Ty for the PPT check ~ it increases "reason" or "confirming" that it is load balanced and it's an overdrive feature
> 
> For some CPUs less for some more
> Starting from 1800 FCLK and higher
> You can just run MCLK at lower freq, and FCLK at higher @ 1.2v SOC
> that's plenty for anything between 1933 & 2000
> But as the overdrive happens on some at 1800 already, you should clearly see it doing something at 1900
> And i think you will, else you wouldn't report such #19's
> As for non affected users, package throttle exists, but it doesn't spill out such errors. it just crashes
> 
> It only spills out such errors if you do really stupid stuff like run 2167+, mostly 2200+
> 
> EDIT:
> Important to me is
> Which CCD does it for you, as all cores in the same CCD will do it
> and which one does the bios disable + does it still do it, with the "wrongly?" disabled CCD
> 
> You should see overdriving on as low load as 12W ~ 17A , via boost tester
> on all cores in the affected CCD
> but "no overdrive" on the other CCD at any load
> also no overdrive with TM5 running , although it's mem access
> and no overdrive while Copy , Read, Write Aida64 is running or the same for L3
> It's only on distant short burst latency checks, where it increases itself too high and errors
> 
> EDIT2:
> 
> CO's behave differently with 1205, and there should be another layer of undervolting
> Please don't use old COs on it, it will not perform well


Will do these testing in a few days, have a big project due on Monday, so tmrw is...no fun zone. Thanks for the file, was digging through Git today and couldn't fine it.

My CPU disables CCD2, the weaker of the two. Performance in everything is inline with a hyperactive 5800x as long as I leave EDC >200.

In other news, I ran the supposed 3.11 AMD driver package, said drivers are same as 3.10 package, I let it overwrite them anyways.

L3 performance wint to shi.... Removing and going back to 3.10, there's some funky about the 3.11 package.

I do think Jp is probably correct on cause of all the FCLK fckery, what I don't understand is why AMD is aggressively oppressing any info on it. Smells like a hardware level flaw they decided to live with and simply not talk about. Intel has done the same too many times to count.

The stonewall also makes me suspicious of an access flaw existing that revealing the root cause of the errors would give it away. Aside from that their position defies explanation imo.


----------



## tcclaviger

Also this happened today (remember I have essentially a zero warm up time):








Doing a complete teardown and rebuild over this week as well, might cycle my 3900x back in for a bit to check FCLK behavior on the StrixEII. I know on my C6E and C7H it ran fine at 1912ish FCLK, 1933 was a hole, and 1966 booted but was unstable, that wasany AGESA versions ago though .

Turns out, removing the inline filters I had installed was a bad idea and I picked up a few new ones.

So on hand I have this B-die
4x DR 4000C16 GSkill sticks
6x SR Patriot Viper 4266C16 sticks
4x SR Teamgroup Dark Pro 3600C14

Any suggestions on how to quickly "bin" them would be extremely helpful, if possible, to do without going through the whole tuning process 1 stick at a time.


----------



## Veii

Here is the issue illustrated








C0004


Watch "C0004" on Streamable.




streamable.com




It's bad it's shaky, but that's with the best possibility to record , for now

DPM LCLK can be tamed now, via HSMP command and ontop with disabling DPM LCLK
That combined with overriding bugged "old" DPM LCLK enforcement ranges - towards new one
Writeup here








[Übersicht] - Ultimative AM4 UEFI/BIOS/AGESA Übersicht


oder ein negativen Offset auf max Boost beim Boost override (-1000mhz) Heisst, damit kann man einen oberen Grenzwert für das normale Core Performance Boost setzen ?




www.hardwareluxx.de





Sample goes back tomorrow
Soo that's about the part/amount i could contribute
Followup is , comparing learned with "fixed" sample , and checking where they differ & why CSTATE_BOOST keeps overdriving
EFF_FCLK seems to be a "read" not a set, soo everything around it ~ it just "displays" issues, but is itself not the issue
Well still the main connection point, but it's not a trigger, while CSTATE_Boost belongs to "being a trigger" reason
yet not "only one" reason

LCLK at least is now fixed
CSTATE_BOOST halfway is surpressed but not fixed
Soo FCLK_EFF is now fine too and sample doesn't request 300A EDC on idle on just mouse movement. Good progress for now, but still not "fixed". Just going around the issue fixing tiny flaws of it







This has to be set, with balanced PP
Else you have issues ~ but again, not fixed just smoothed out to be less of an issue & no more idle or small load overboosts


----------



## tcclaviger

I saw a 5708 boost request on my strongest core yesterday when I was playing with Hydra, I chuckled. Shocked it didn't crash actually, as it was running a load when it happened, not just a simple boost check.

I am curious, is there any benefit to locking LCLK to 600 instead of 300?


----------



## Veii

tcclaviger said:


> I saw a 5708 boost request on my strongest core yesterday when I was playing with Hydra, I chuckled. Shocked it didn't crash actually, as it was running a load when it happened, not just a simple boost check.


As long as you don't see 1.68v VID request on OC_MODE (1.55v on PBO mode)
With 55-56ghz , you are fine 

Typical AMD gremlings, as @mongoled loves to call
But it seems overboost and FCLK_EFF overdrive , are connected
Sigh, only community has to fix it ~ at least it makes progress now , with a correct target & indication
~ no more unstable DPM links, no more unstable C6 "deep sleep" wakeup overboosts (for now) nvm
















Lovely, wonder till what range 

EDIT:
Sadly i have absolutely no clue about RTX DPM Link speed
And how you guys will override that one - if it doesn't out of luck end up fixed at exactly 593 Mhz peak, instead old 619 Mhz peak (which doesn't exist anymore)
* only stepping of 25mhz (-1 = set)

EDIT2:
Another global question,
~ Why do MP5_BUSY triggers, keep stacking. Faster with the overdrive issue, barely now with the softfix ~ but still keep increasing and increasing
~ Is there any CRC/Error after X Threshhold detector behind this, or for what does it stand 
Good Night/ Timezone 🛌👋


----------



## PJVol

Veii said:


> Lovely, wonder till what range


That's exactly how it was looked like when I tested it.



Bix said:


> Where would you go from here?


Nice, it must have taken a bit of time 
Can I ask you to make a couple of runs of Sandra's Processor Scientific Analysis tests, let's say for 1800 fclk and 2000, and share the results? The POI is the performance in a GEMM tests


----------



## KedarWolf

tcclaviger said:


> Will do these testing in a few days, have a big project due on Monday, so tmrw is...no fun zone. Thanks for the file, was digging through Git today and couldn't fine it.
> 
> My CPU disables CCD2, the weaker of the two. Performance in everything is inline with a hyperactive 5800x as long as I leave EDC >200.
> 
> In other news, I ran the supposed 3.11 AMD driver package, said drivers are same as 3.10 package, I let it overwrite them anyways.
> 
> L3 performance wint to shi.... Removing and going back to 3.10, there's some funky about the 3.11 package.
> 
> I do think Jp is probably correct on cause of all the FCLK fckery, what I don't understand is why AMD is aggressively oppressing any info on it. Smells like a hardware level flaw they decided to live with and simply not talk about. Intel has done the same too many times to count.
> 
> The stonewall also makes me suspicious of an access flaw existing that revealing the root cause of the errors would give it away. Aside from that their position defies explanation imo.


Before you go back to 3.10, try the AIDA64 latest beta. It has the L3 test cache fix.

My results with 3.11 are actually better in read/write/copy and main latency and L3 cache are not affected.


----------



## Audioboxer

So I was trying one last thing before turning off CPU cache, load an older BIOS profile that has had goodness knows how many hours of TM5 testing. This profile apart from not having telemetry has no AutoOC, a slightly more reserved curve than the one I was on and some of the c-state settings back on default rather than disabled from trying to push CB23 scores higher.

This time an error at nearly 11 hours.

I'm going to test now without CPU cache enabled, but in general, what the hell causes an error at 11 hours? Max temp reached, 30 degrees.

I think I'll also hit up a 50 cycle TM5 so it's doing it all in a row on this profile rather than all the individual 25 cycles I've ran. Need to get to the bottom of whether it's just Karhu tripping an error.


----------



## Bix

PJVol said:


> Can I ask you to make a couple of runs of Sandra's Processor Scientific Analysis tests, let's say for 1800 fclk and 2000, and share the results? The POI is the performance in a GEMM tests


Thanks for the reply Something's definitely wrong here... at 2000 FCLK I'm frequently getting hard reboots during the benchmark. Managed to pass a few times but only getting around 126 Gflops in the GEMMS test compared to 385 Gflops at 1800 FCLK. Does this suggest a problem with the VDDGs?


----------



## Veii

PJVol said:


> That's exactly how it was looked like when I tested it.


We'll get this 
I feel now slightly more comfortable working with Mailbox & SMU in general

Can you do me a little favor and check if only PPT_Limit (HSMP 13h 300000dec/0x493E0 = 300W) sensor logging is disabled ~ by disabling DPM LCLK from AMD OVERCLOCKING Tab
Or you also lose THM sensor like i did on the 5600X sample ?
13h is still accepting values, but after the change not used for power management and LCLK stands firm

Aside from fixing Win11 OS powerplan sheduler to battery forced (with balanced pp as loaded foundation)
Yes i'd need some more digging to do what MP5_BUSY does log & if there is any threshhold on it after when it reports "errors"
That and, still figure how to permanently disable the CSTATE_BOOST flag that causes all of this
Could also just be a "read/receive" sensor and not the main issue ~ unsure, i'll find information 
This WHEA nonsense has to be fixed before XT release. I don't expect that AMD does anything here, not even an attempt of acknowledge, at this point of time (the result by shown time)

More information likely will move to the WHEA thread
Although FCLK = RAM-OC

@ManniX-ITA do you have any more information or saved document for AMD 19h Lineup & MP5_BUSY sensor/logger ?
For example what


Code:


CMD:  0x03B10528
RSP:  0x03B10574
ARG:  0x03B10A60

&

CMD:  0x03B1052C
RSP:  0x03B10578
ARG:  0x03B10A80

 belong to ?
Collecting documents to see what we can do 
5900X B2 has to go today back - soo i'll export some SMU reports for comparison later


----------



## PJVol

Bix said:


> Does this suggest a problem with the VDDGs?


I think there are two unrelated issues you encountered. One is AVX2/FMA instability - this should be resolved first. Not sure what the exact cause is, but i can guess some of your cores have CO magnitudes set too agressive.
The other issue... Well, it's to be kinda expected. I just have a slightly different (and not very popular here) view of what cause the 1900+ fclk issue and how to reliably identify it.
So, the less stable fclk overclock, the more severe gemm performance regression is observed, depending on how well interconnect PHY responses to FCLK overclock, that in itself is affected by a number of contributing factors, rather just "one toggle" in bios or elsewhere.


----------



## PJVol

Veii said:


> check


Yep, ppt and thm gone from the top of the table, but it's there in other places and just it, meaning limits are still applying.



Veii said:


> i'd need some more digging to do what MP5_BUSY does log


How this might be linked to the IF issue in question, I mean did you find any oddities related to it? Cause I can only guess, given that it is reporting MCE on the per-CCD basis and the corresponding SYND registers description, it's kinda CCD cache or CCM controller.


----------



## Veii

PJVol said:


> How this might be linked to the IF issue in question, I mean did you find any oddities related to it?


Sadly yes
Normal reports how they have to be, are one two once a minute
When it was bugged and overdriving - i had over 30+ logs a sec on it
Now it's calm again, but it makes me wonder if there is a "set threshhold" to it - after X amount of logs for it to say "an error has been found ~ WHEA"


----------



## Imprezzion

At which frequency for memory and IF/MC would running out of sync be cancelled out by the memory speed and latency? 

I have my full 4400 17-17-17-38-340-2T profile I used to run on Intel still saved in screenshots with all secondaries and tertiaries but I wonder if it will be in any way faster on AMD.


----------



## Bix

PJVol said:


> I think there are two unrelated issues you encountered. One is AVX2/FMA instability - this should be resolved first. Not sure what the exact cause is, but i can guess some of your cores have CO magnitudes set too agressive.
> The other issue... Well, it's to be kinda expected. I just have a slightly different (and not very popular here) view of what cause the 1900+ fclk issue and how to reliably identify it.
> So, the less stable fclk overclock, the more severe gemm performance regression is observed, depending on how well interconnect PHY responses to FCLK overclock, that in itself is affected by a number of contributing factors, rather just "one toggle" in bios or elsewhere.


That's all really useful, thanks again. Will fix CO as a priority and see if that improves the GEMM performance at all. 
Although things would all be a lot more straightforward if AMD were more open about issues with their architecture I certainly wouldn't have learned so much interesting stuff from this debate!


----------



## PJVol

Veii said:


> When it was bugged and overdriving - i had over 30+ logs a sec on it


I don't get what logs you're about? Do you mean WHEA 19's source is MP5 and not PIE?
And i haven't been able to watch the video's you posted here (broken links or some sec. flaws)


----------



## Piers

Veii said:


> Last part, i don't want to know
> MemController is great, sadly
> Signal integrity with this PSU is not great, and dimms are not great. Dimms are "fine" on my ITX
> 
> Never tested only 1 dimm of anything
> Wouldn't want to fixate myself on accepting "it just can't work"
> It can, if you bruteforce it ~ and voltage does help.
> Keeping stability up, is another question
> 
> When chip can do 4067 14-14-14 SR, it will do 3800 14-14-14 ^^'
> There are other walls to climb and other problems to fight on.
> The errors between 3200 14-14 and 3600 14-14 are pretty much identical.
> A powering issue still, soo that's where to focus is now
> 
> First batch 2036 models , 2nd batch had this oopsy fixed.
> October, November models - all don't have this type of internal issue and go higher WHEA free
> 2nd batch November,December models got fixed and labs expanded to BG 20XX PGS
> Also to central europe near February
> This oopsy will likely never happen again
> But fused cores are not really dead or disabled to begin with
> 
> HCI & Karhu "german" stability rating was 10 000%
> 1usmus_v3 is over 20 cycles minimum
> Anta's people run between 3 and 9 cycles
> 
> Soo generally 1+ hour for 2x8
> ~3 hour for 2x16
> 
> German HCI & Karhu rule, was near the 8-10hour (they only go with %)
> GSAT i think also near the 6+ hours.
> Errors on these programms appear later
> Soo people made a list after 1000%, 2500%, 5000%, and 10 000% is required stability rating
> 
> Please run them overnight for bit longer
> And check if on 2T you have tPHYRDL missmatch between dimms
> or tRDWR/tWRRD missmatch with 4 dimm Boards
> 
> EDIT:
> Only beyond 45-48min contineous load, you reach thermal equilibrium on anything
> Good memory tests have to take at least 1 hour, to be considered stable
> It's not silicon, and capacitors + resistors change stability by operating temperature.
> Not reaching at least thermal equilibrium is kind of, questionable
> 
> I test with open window on cold (dimms stay near 40-41c) ~ to check timings
> and later on the other day after cold boot, with normal usage warm room temp ~ to check PCB stability
> If it fails, the reason is easier to figure out
> But if it fails while you sleep, the issue is hard to figure out
> Watch it active for 30min,
> if then it remains fine - better test over 1 hour for 2x8 and over minimum 2 hours for 2x16.
> 
> EDIT 2:
> View attachment 2534858
> 
> Pick one:
> 
> you follow anta's rule, match tCL = tWR, match tRTP = tWTR_L
> you don't follow anta's rule, and use tWR = tRTP*2 , then have no connection to tWTR_S & _L
> * if you follow anta's rule, tFAW has to be 4* tRRD_S
> *' if you follow anta's rule, tRAS has to be tRC-tRP
> ** if you follow my rule for tRTP*2 = tWR, tRAS doesn't matter if it's tRCD*2, or tRCD+tRTP, or tRCD*2+tCCD_L or tRCD*2+tBURST
> tRC can then be anything, even the exploit of tRAS+1 ~ when you shift focus on tRRD_ (higher these). Same goes for tFAW, can be anything from bellow realistic burst refresh or 4* tRRD_S, or tCCD_L times tRRD_S
> 
> EDIT3:
> I've tested this on my 15-15 set
> There using tWR 15 (=tCL) vs using tWR 16 (=tRTP*2), shows quite a big difference.
> _* also between tRRD_S *4 & tRRD_S * tCCD_L_
> Sync difference ~ as 1Clk (tWR) can't result in over 800-1000MB/s bandwidth difference
> Both are stable, but "the Methodic" is just different.
> DRAM never has only "one way of optimisation" ~ hence anta and 1usmus can never agree with tWR results
> set behaves just different ~ it makes no sense to fight over "rules".
> 
> EDIT4:
> 
> Soo currently i explore more anta's method
> Of course he is right how it has to run. But results show that it's very finicky and barely stable
> When stable, sometimes faster, sometimes not (up to other timings around it)
> Can't prefer one over the other yet, just know that it's easier to work with something you know how to work with
> Following his advices does indeed lead to more bandwidth, but barely is get-table stable
> Else timing stability, i still keep having better results with my higher tertiaries, than his lower focused ones. Looking at the end result, not XOC


Fascinating read. Does anyone have experience with the 'Optimised for Ryzen' Corsair memory (CMK32GX4M2Z3600C18)? Generally Micron, single rank, 3600 CL18.


----------



## nada324

Hello all, im getting error 2 at first cycle, just one:

What i did mainly tried:

Change TCKE to 9, to fix error 6

Increase ProcODT from 40 to 43.3 and decrease CPU VDDP18 from 1.8v to " 1.72v " to fix error 12

- Decrease RTT nom and Vdimm at same time to "fix" error 13

I read tm5 errors drive thing, and still cant see what thing is producing it, maybe CAD bus?

Thank you all

Viper 4133 (2x8 SR)


----------



## PJVol

Bix said:


> if AMD were more open about issues with their architecture


TBH, i personally wouldn't consider it really an issue, rather community's dissillusionment 
Running that high of fclk was never under any declared or advertised specs.


----------



## Veii

PJVol said:


> I don't get what logs you're about? Do you mean WHEA 19's source is MP5 and not PIE?
> And i haven't been able to watch the video's you posted here (broken links or some sec. flaws)


Nono, WHEA's logged only exist if FCLK_EFF spikes far to high . by whatever reason it spikes high

MP5_BUSY logging, only was mentioned as that logging slowed down big times after fixing LCLK overdrive beyond hard limits of 593mhz

Soo the question was,
Why does Mp5_BUSY slow down, and behaves now normal
And is it connected to any threshhold after X value would for example send out an report for WHEA something
Know now that #19 and #20 belong together and come at the same time, but don't know by what #20 where cased, as i had them randomly and rarely 

The video, this is an issue on your side - region lock maybe unsure
here it is reuploaded:


C0004.MP4 beim Filehorst - filehorst.de


----------



## Bix

PJVol said:


> Running that high of fclk was never under any declared or advertised specs


That's true. I guess there aren't many companies out there who make a point of telling their customers exactly what their product _can't _do...


----------



## Veii

PJVol said:


> TBH, i personally wouldn't consider it really an issue, rather community's disillusionment
> Running that high of fclk was never under any declared or advertised specs.



Giving no information to overclocking community about sensors that have to be followed and tracked when working with PBO (disregarding OC & XOC community that helps develop the platform further)
giving zero sensor logs to define after when time dLDO_Sensor throttles, alone giving no information about existence of this sensor or enabled change since 1.1.0.0C+/D
giving zero information about spi armor, and enforcing it without an opt-out ability by forcing vendors to do so
Restricting CO's down to -30 and removing higher than +200 FMAX , now 12 months later adding undervolt after removing fmax untervolt ability , yet still staying on low +200mhz
undisclosing Spectre.V5 patches, and rewrite of PM_Table + SMU ~ soo letting users have USB, PCI, HDA, PCH link dropout issues till they fix it with hotfixes on 3 days bases (confusing vendors too) & hurt public mindshare that way / especially gamers
marketing with BAR mode and negative CO as social media & marketing lie , forcing users to update to 1.1.0.0C with intentional ABL FCLK hardlock. Bootloader Hardlock ~ while undervolt and BAR-Mode existed since 1.1.0.0A
forcing vendors to not even release anything bellow SMU 56.34 (1.1.0.0C) with their new boards
undisclosing overboost bug connected to C6 states (known since Feb/March), but hotfixing it with chipset updates and modified powerplans. Undisclosing mc_update.dll in Windows for further OTA microcode hotfixes
using ROM ARMOR & Spectre patches, to implement a PCH Chipset ID check for X370. Forcing vendors to leak X370 as they are prohibited to follow & release them. Delaying X470 Updates at the same time although "it has to be supported". * now starting to release B350 Security-Hotfixes with intentional old AGESA while having the ability to give a newer better working one
disabling PCIe 4.0 from IO to CPU-X16 on X470, using ReDrivers as excuse although engineers have confirmed me that this is not a distance issue and not a PCB layer issue. It was enforced on them to be titled an issue. Only towards PCH it clearly is one
restricting Navi 21 XTX cards with 2150mhz mem lock on driver level, but releasing XTX-H series with a firmware & ID difference. There is no reason for the memory or frequency lock
It's been a great year with AMD *🤭*
But @Bix ment on his post purely about CO ranges and the lack of information (still) how to work with them. Not exactly the FCLK topic
Any information requires an NDA.
Adventurous and Questionable Year. I wish for a better change and not downlooking on the OC/XOC community
Plus not separating Vanguard Team from Rebels Team.
Alone not titling "people who share undisclosed information" as "Rebels", because AMD can not get "basic" information out for their main contributing scene
The Overclocking community

Be it disclosed through leaks or however support given.
Better than no tools at all.
This goes towards Vendors too. They can improve and need to stand a bit more with their position
They have the ability too, but everyone takes the easy way out of "agreeing with everything" ~ talking to Vendors and ODMs
=====================================================
Also hence the talk was once about RingBus vs not Ring Bus
@PJVol @ManniX-ITA


----------



## nick name

What is Hydra?

Never mind. I am dumb.


----------



## Veii

nick name said:


> What is Hydra?


Project Hydra, by 1usmus
Successor after CTR
Currently donationware, freeware 1.0 public-release ~ is soon to follow







* Optimal VID was 1406, but 1413mV is the highest limit before "negative" frequency loss occurs (1425mV is worse)
* Ignore EDC, DPM readout bug


----------



## tcclaviger

I'll lead with, I'm not dissatisfied with my 5950x performance but....

2000 FCLK was absolutely advertised, by Lisa herself during the key note, and in the AMD slides as an upper target, like 1900 was for Zen 2, can't find the pic ATM, but I watched it live, and it was said.

1800 was widely advertised as achievable by the majority of Zen 2 and nearly all Zen 3, that's simply not the case, unless they were including WHEA flooded samples in those "achievable" numbers.

@Audioboxer, I suspect kharu is catching a WHEA event and flagging it. I clear TM5 Anta777 Extreme, 1usmus v3, and OCCT ram test for hours and hours. Kharu catches 1 error with cache enabled at about 5000% and no errors with cache disabled.

My suspicion, it's tied to what Veii has been working on.

PC is stable as. Hours and hours of gaming, countless benchmark test, sits idle for hours overnight, no crashes. I wouldn't get tied in knots over the kharu cache enabled single error, I consider it a false positive at this point.


----------



## PJVol

tcclaviger said:


> 1800 was widely advertised as achievable by the majority of Zen 2 and nearly all Zen 3, that's simply not the case, unless they were including WHEA flooded samples in those "achievable" numbers.


Didn't see anybody complain about not running stable fclk 1800 with a zen2, let alone zen3.


tcclaviger said:


> 2000 FCLK was absolutely advertised


Reaching 2000 fclk on Zen3 was mentioned only in the context of the similar chances as for zen2 to reach 1900, so it hardly can be considered "absolutely advertised". Why make these exaggerations even more absurd.



Veii said:


> Also hence the talk was once about RingBus vs not Ring Bus
> @PJVol @ManniX-ITA


Lol, you confused me with someone else again (it seems to be Blameless this time) , but it's ok, I now know what "karma" is.


----------



## Esticbo

which one is better?


----------



## PJVol

Esticbo said:


> which one is better?


I like 2nd - more vibrant colors and it looks sharper.


----------



## Esticbo

PJVol said:


> I like 2nd - more vibrant colors and it looks sharper.


😂😂 The second is a Google Pixel photo


----------



## Mach3.2

First one for me, not a fan of "pictures of a screen".

Is it WHEA free?

Only way to know is bench and see which one is faster.


----------



## Audioboxer

Audioboxer said:


> View attachment 2535700
> 
> 
> So I was trying one last thing before turning off CPU cache, load an older BIOS profile that has had goodness knows how many hours of TM5 testing. This profile apart from not having telemetry has no AutoOC, a slightly more reserved curve than the one I was on and some of the c-state settings back on default rather than disabled from trying to push CB23 scores higher.
> 
> This time an error at nearly 11 hours.
> 
> I'm going to test now without CPU cache enabled, but in general, what the hell causes an error at 11 hours? Max temp reached, 30 degrees.
> 
> I think I'll also hit up a 50 cycle TM5 so it's doing it all in a row on this profile rather than all the individual 25 cycles I've ran. Need to get to the bottom of whether it's just Karhu tripping an error.


So I've basically spent the whole day today aiming for a 50 cycle TM5 and I can't even get 25 cycles done without TM5 timing out. No errors just the timeouts.

Not only have I turned off all CPU OCing, so it's back to default, but I've been loosening all sorts of memory secondaries, I'm back to tCL14 and tRFC is greatly increased. Nope, TM5 will still randomly timeout. Maybe on cycle 7, maybe on cycle 17 or maybe on cycle 21.

I have absolutely no idea what is going on. It's that bad I've got to the point of thinking is there something up with this Windows 11 installation now? I'm running the latest unreleased AMD chipset drivers from ASUS. I say unreleased but I just mean AMD haven't added them to their website yet.

It's got me thinking have they made changes to something on the CPU end that is triggering TM5 to timeout and Karhu CPU cache testing to randomly fail? But I'm certain others in this topic are running them.

Stay tuned because I have absolutely no idea what is going on. I guess I'm going to have to go back to AUTO/XMP just to see if I still get timeouts. My memory is pretty loose and it's still happening.


----------



## Veii

Esticbo said:


> which one is better?
> 
> 
> PJVol said:
> 
> 
> 
> I like 2nd - more vibrant colors and it looks sharper.
Click to expand...

I'll take the menu #1 , with a bit of ClkDrvStr sauce (near 40 grams) & GDM off, 2T ~ sorry i don't eat GDM.
If you feel extra fancy, you can also fix tRC to be tRP + tRAS.
That might make the dinner look a bit more tasty


Audioboxer said:


> I have absolutely no idea what is going on. It's that bad I've got to the point of thinking is there something up with this Windows 11 installation now? I'm running the latest unreleased AMD chipset drivers from ASUS. I say unreleased but I just mean AMD haven't added them to their website yet.


Which version ? 22000.3xx or 2xx
also change


----------



## Esticbo

Mach3.2 said:


> Is it WHEA free?


Yes, they are whea free



Mach3.2 said:


> Only way to know is bench and see which one is faster.


The first setting is the fastest



Veii said:


> I'll take the menu #1 , with a bit of ClkDrvStr sauce (near 40 grams) & GDM off, 2T ~ sorry i don't eat GDM.
> 
> If you feel extra fancy, you can also fix tRC to be tRP + tRAS.
> 
> That might make the dinner look a bit more tasty


👍🏻I will try your suggestions


----------



## Audioboxer

Veii said:


> I'll take the menu #1 , with a bit of ClkDrvStr sauce (near 40 grams) & GDM off, 2T ~ sorry i don't eat GDM.
> If you feel extra fancy, you can also fix tRC to be tRP + tRAS.
> That might make the dinner look a bit more tasty
> 
> Which version ? 22000.3xx or 2xx
> also change





















Windows and AMD chipset.

My prior experience a while back with TM5 timing out was either an unstable curve (I have no curve at the moment) or if tRFC was too low/tRP and tRAS were too low. I have tRFC at 272 despite leaving the memory at 1.55v and tRAS/tRC is 28/42. Never had to run them this high previously.... and this is still timing out.

Change to best power effeciency? I guess I'll try that before I end up removing my whole memory profile and running XMP/AUTO.


----------



## Luggage

Audioboxer said:


> View attachment 2535771
> 
> 
> View attachment 2535772
> 
> 
> Windows and AMD chipset.
> 
> My prior experience a while back with TM5 timing out was either an unstable curve (I have no curve at the moment) or if tRFC was too low/tRP and tRAS were too low. I have tRFC at 272 despite leaving the memory at 1.55v and tRAS/tRC is 28/42. Never had to run them this high previously.... and this is still timing out.
> 
> Change to best power effeciency? I guess I'll try that before I end up removing my whole memory profile and running XMP/AUTO.


Did you just disable curve or did you set every core back to 0 first? Hint hint nudge nudge


----------



## Audioboxer

Luggage said:


> Did you just disable curve or did you set every core back to 0 first? Hint hint nudge nudge


Disabled but PBO is turned off anyway (set to AUTO).


----------



## Veii

Audioboxer said:


> Change to best power effeciency? I guess I'll try that before I end up removing my whole memory profile and running XMP/AUTO.


That and debug with ZenPTMonitor
You might need to disable DPM LCLK from AMD OVERCLOCKING - for Windows 11
If you have overdriving LCLK and so overdriving FCLK issues
Win 11 behaves strange,well generally Vermeer behaves strange, right now


----------



## Audioboxer

Veii said:


> That and debug with ZenPTMonitor
> You might need to disable DPM LCLK from AMD OVERCLOCKING - for Windows 11
> If you have overdriving LCLK and so overdriving FCLK issues
> Win 11 behaves strange,well generally Vermeer behaves strange, right now


Set LCLK DPM to disabled, and power efficiency to best, will now try again.

I don't really know what is going on but it seems like I might be a victim of bad timing. Just because Karhu failed at 8~11 hours with CPU cache enabled it had me wanting to go back to do a 50 cycle TM5 but maybe Windows 11/Chipset drivers are also causing issues 😂

I'm over here just wanting confirmation if my damn memory profile is fine lol. The same once I tested stable like 2 months ago but now I'm paranoid isn't really stable...

I really do hate AMD and Microsoft. All the money in the world and they seem to keep messing up software.

I know the grass isn't always greener on the other side but once I decide to upgrade to the new gen with DDR5 I'm seriously going to consider going back to intel. AMD seem incredibly hostile to the community and half the time they seem to have no clue what they're doing with their own hardware when it comes to the BIOS/software.


----------



## Worldwin

Got this stable for 1600% HCL memtest. Turns out the error15 I was getting was from TRDRD/TWRWR not being able to go lower than 4.Don't know if they can individually go lower than 4 as I have always tested them with the same value.
Most likely going to get TRFC to 140ns and try to get TRCDWR/TRCDRD lower.


----------



## PJVol

Veii said:


> here it is reuploaded:


Just watched it. That 91000 mp5_busy readout was funny. You seem to be quite "lucky" with your samples, mate 
Afaik, those "busy sensors" are percentage values, idk what to say...)
Oh, almost forgot one, С-state boost seems ok as well, looking at it behavior when you moved the mouse.



Veii said:


> It's been a great year with AMD


I can say that without irony (well, if only a bit of, given that the EK's fullcover wb for a not-bought-yet 6800XT gathering dust in the corner for almost a year, LOL )
but for once, I ended up with a really good sample of 5600X, that was never the case before with a cpu's)


----------



## Audioboxer

@Veii TM5 timeout after 23 cycles. I'm going back to AUTO/XMP to see if it can pass.


----------



## Robby37

tcclaviger said:


> Trcdrd 15
> Trc 45
> Trrds 4
> TrrdL 4 or 6
> tFAW 16
> ProcODT @ 40
> Drop IOD voltage to 1.05 or less
> Raise SOC to 1.1-1.125
> And fix trfc to method of choice is where I'd start on those.


What is trfc method of choice ? The ram calc I have to look at the spreadsheet again last time I got real confused


----------



## Veii

PJVol said:


> Just watched it. That 91000 mp5_busy readout was funny. You seem to be quite "lucky" with your samples, mate


They come to support me on the WHEA hunt 
Looking at this B0 again , it actually peaked to 860mhz , while 770mhz is max













Actually, both
B0 White, and B2 Yellow
B2 to 870mhz 
It's painful, but hey that's how you find "errors"
Dual CCD 5600X was also completely unusable on stock
Currently B2 is completely unusable on 1203C 

Now for two people
Win11 doesn't help it much either
Just hope santa will bring me 1205 soon
But there is no hope that Santa will fix DPM and WHEA issues this year


Robby37 said:


> What is trfc method of choice ? The ram calc I have to look at the spreadsheet again last time I got real confused


Pick a value inside a range (multiples) of 16 (anta's)
Or pick a range inside a multiple of tRTP 
well or tRC /8 and use that as your multiple , works too
on 45 it would be 5.625 , or you move just in multiples of 45

tRFC mini is just not understood, but both work 
You can also move in multiples of tCL ~ but that anchor ended up as problematic
tRC anchor was so far the best option
Multiples of something at the very end
Whatever you pick, tRTP, tRC or just fixed value 8 or 16 or 32 ~ although i've played with 32 long time ago and changed my mind

There is no "correct" ramOC method. Dimms can be optimized for different usages ~ timings of them


----------



## Blameless

tcclaviger said:


> Wait: Doesn't Ryzen have power circuitry on die, seem to remember it has some amount of it.


It has on-CCD low-dropout regulators (LDOs) for each core (with input voltage equal to the highest voltage core, or a little more), as well on IOD LODs for the VDDG voltages (vSoC as the input voltage), and CLDO VDDP (vDIMM as the input voltage).



tcclaviger said:


> It's wattage.


Higher loads generating more errors makes sense. The lower wattage/current limits likely constrain peak loads enough to add stability/mask errors.


----------



## ManniX-ITA

Veii said:


> @ManniX-ITA do you have any more information or saved document for AMD 19h Lineup & MP5_BUSY sensor/logger ?


Nope, sorry


----------



## Veii

ManniX-ITA said:


> Nope, sorry


Morning' 🍵
I shouldn't have asked with "more"
If you have any pdf about Matisse or Vermeer or the EPYC Segment to read, please share. Every piece of information is good information (stolen leak or public leak)
Every piece of documentation for mailbox, is good documentation 
~ same goes for Blameless & everyone else

Well to what you guys feel comfortable sharing privately
Nobody will freely say that they are in the Vanguard Team, soo every little information is a good step towards fixing these issues
I won't give up on it, but more than asking around for support, i can't so far
It needs more data to look deeper into it ~ outside of DPM issues and questionable defaults


----------



## Audioboxer

Audioboxer said:


> @Veii TM5 timeout after 23 cycles. I'm going back to AUTO/XMP to see if it can pass.












lol, this is my memory at XMP/AUTO. As in 14-15-15-15 at 3800 1.55v, all the rest of the timings on AUTO/XMP and GDM... enabled. Only change being instead of running at 4000 it's at 3800.

On the one hand I'm relieved to know my old profiles are likely fine, on the other hand I now don't have a clue what is going on. I guess a clean install of Windows 11 might be needed. First I can possibly try out AGESA 1.2.0.5 just because I'm using AMD chipset drivers only released by ASUS (v3.11.17.521). Or I can try rolling back AMD chipset drivers to what AMD have released (3.10.08.506).


----------



## mongoled

Ive mentioned this before, though it does not mean that this is down to the chipset drivers, but they are possibly part of the reason.

Two OS.

One is my "WorkStationOS" the other is the "BenchOS"

BenchOS does not suffer from the timeout issue.
WorkStationOS does suffer from the timeout issue.

I thought that seeing as the WorkstationOS has more resources being used i.e. more RAM usage, the timeout issue occurs when the OS "pulls" RAM from TM5s memory allocation and this is the reason for the timeout.

Even using the same chipset drivers on both OS's the WorkStationOS will have the timeout issue more times than not on a 25 cycle run where as the BenchOS will not....


----------



## Audioboxer

mongoled said:


> Ive mentioned this before, though it does not mean that this is down to the chipset drivers, but they are possibly part of the reason.
> 
> Two OS.
> 
> One is my "WorkStationOS" the other is the "BenchOS"
> 
> BenchOS does not suffer from the timeout issue.
> WorkStationOS does suffer from the timeout issue.
> 
> I thought that seeing as the WorkstationOS has more resources being used i.e. more RAM usage, the timeout issue occurs when the OS "pulls" RAM from TM5s memory allocation and this is the reason for the timeout.
> 
> Even using the same chipset drivers on both OS's the WorkStationOS will have the timeout issue more times than not on a 25 cycle run where as the BenchOS will not....


I downloaded a cut down Windows 10 OS that KedarWolf made and I really should be installing it as a benchOS. The only thing I guess I could say is I rarely had TM5 timeouts with Windows 10 and when I did it was usually instability. Now I'm finding I can repeat it EVERY run on Windows 11 under my current environment where all I've been changing is RAM timings.

I should have counted yesterday, but I must have done nearly 10 TM5 runs and every one timed out at random places, though cycle 21 IIRC has been hit twice.


----------



## Veii

Audioboxer said:


> I downloaded a cut down Windows 10 OS that KedarWolf made and I really should be installing it as a benchOS.


Win 11 Ghost Spectre exists
But win 11 has other strange issues

Yes TM5 finishes a cycle for me in 1 minute if my cores crash
depends
But this is the fun i have atm - now board doesn't misstrain 26-28 anymore (still does on 1T-56)
But it keeps misstraining to 24-26 
Not 26-26 anymore

It's flawed
I have a suspicion, higher VDD18 (1.9+) does also mess up trace length prediction/calculation
I mean it's the positive , but 2nd channel does not go down to 24
Else tCWL 10 now posts and tests for a bit , near 1.55v ~ main profile target is 1.46-1.48v







But it's the same even with tCWL 10
Just noticed, new rabbit hole
tPHYWRL scales with SOC (not only, but it is influenced)







================
Else what also remains
Is setting this to background focused ~ soo win 11 thread scheduler won't suspend other apps that are not in the foreground


----------



## Audioboxer

Veii said:


> Win 11 Ghost Spectre exists
> But win 11 has other strange issues
> 
> Yes TM5 finishes a cycle for me in 1 minute if my cores crash
> depends
> But this is the fun i have atm - now board doesn't misstrain 26-28 anymore (still does on 1T-56)
> But it keeps misstraining to 24-26
> Not 26-26 anymore
> 
> It's flawed
> I have a suspicion, higher VDD18 (1.9+) does also mess up trace length prediction/calculation
> I mean it's the positive , but 2nd channel does not go down to 24
> Else tCWL 10 now posts and tests for a bit , near 1.55v ~ main profile target is 1.46-1.48v
> View attachment 2535845
> 
> But it's the same even with tCWL 10
> Just noticed, new rabbit hole
> tPHYWRL scales with SOC (not only, but it is influenced)
> View attachment 2535846
> 
> ================
> Else what also remains
> Is setting this to background focused ~ soo win 11 thread scheduler won't suspend other apps that are not in the foreground


Had never heard of that custom mod of Windows 11, looks interesting.

For my main OS though I tend to prefer installed as vanilla and then I optimize it as best as I can within the environment. I do a bit of work on my PC and sometimes I find if people are supplying lite versions of OS they can remove things I need or there are other complications. I want my Windows 11 properly activated and being able to use the Windows store/Windows update.

Going to try dual booting with Kedar's Windows 10 lite just to see if I can get TM5 passing again lol.


----------



## Veii

Audioboxer said:


> For my main OS though I tend to prefer installed as vanilla and then I optimize it as best as I can within the environment. I do a bit of work on my PC and sometimes I find if people are supplying lite versions of OS they can remove things I need or there are other complications. I want my Windows 11 properly activated and being able to use the Windows store/Windows update.


At this point the same
It's so far fine, but i had to reinstall it now, because microsoft update 3xx messed something up ~ store updates where disabled deeply, but on other notebook's system it was fine. Just up to update "steps/rows" not to skip things

It's not supplied with any KSM emulation and store is reinstallable
But i still question, if i should just make my own 11 or stick to this one
It takes too much time to get it to a similar behaving level
personal 10 iso is fine, but it takes much time to make one

I'll probably do it soon for the main system - now that L3 issues are minimal to nearly non existent
But i know what you mean.
Honestly i don't have a bench OS , just use my daily ~ but maintain that


----------



## Audioboxer

Veii said:


> Honestly i don't have a bench OS , just use my daily ~ but maintain that


I would like to just stay here as well but as of now can't figure out what is disturbing my TM5 runs and presumably crashing them 

I'm going to try AGESA 1.2.0.5 shortly.


----------



## Audioboxer

Just updated to the latest BIOS with AGESA 1.2.0.5. MSI have finally updated SMU. The above is just AUTO voltages.

But here's the major promising change so far, I no longer get mouse lag/the high pitched noise coming from my case when running CPU stability testing 👀  Of course event viewer still has WHEA 19s but this might have fixed my USB drop outs and performance regression. Looking into it now.

OCCT and even y-cruncher test 17 HNT are running fine from the point of view of no mouse jerk/no high pitched noise. Previously I couldn't go above FCLK 1900 without seeing these symptoms.


----------



## Audioboxer

Got a reboot 38 minutes into OCCT, just a kernel-power 41.

But that is OK, no one said stabilising FCLK 2000 is easy and the AUTO voltages above are whack. Time to go back to manual voltages. Great news though is no USB drop outs. It seems like changes have been made by AMD yet again to try and stabilise USB. Would be interesting to know what they've been doing other than "update SMU" as I think I had quite a severe case of USB issues above 1900.

Interesting addition to the new BIOS is you can now do VDDG voltages per CCD. I guess that might really help fine tune stability. At this moment in time I couldn't care less if CPU boosting is worse, this is looking like the first BIOS I _might_ have a chance to run above 1900!

Edit - Spoke too soon, my good friend y-cruncher test 17 can still nuke USB after about a minute. Commander pro disconnects. No mouse jerk though which is a step forward. Now I need to find out if I can stabilise FCLK with BIOS settings.


----------



## Dziarson

Why everyone have problem whit high Vsoc voltage ?
stable FCLK 2000 on my cpu need 1.18v-1.25V
@Audioboxer i think we have sasme boards what cpu you have?


----------



## Audioboxer

Dziarson said:


> Why everyone have problem whit high Vsoc voltage ?
> stable FCLK 2000 on my cpu need 1.18v-1.25V
> @Audioboxer i think we have sasme boards what cpu you have?


5950x, seems 2 CCDs can sometimes be a bit more problematic trying to stabilise above 1900. I'm trying my VSOC up to 1.25v to help with USB issues. So far y-cruncher test 17 is still killing me on 1933~2000.

Another thing I've noticed on AGESA 1.2.0.5 is what some other people have reported, max CPU VCORE is greatly reduced. Instead of a limit of around 1.5v, the current limit seems to be around 1.425v. That's going to hurt the small boosts. Not sure if this is another voltage bug or AMD has decided they don't want CPUs boosting to 1.5v even if it's for extremely light loads.


----------



## Dziarson

I think its work normally


----------



## Audioboxer

Dziarson said:


> I think its work normally
> View attachment 2535860


Is this BIOS A45 with SMU 56.65.0?


----------



## ManniX-ITA

Dziarson said:


> I think its work normally


From the screenshots looks like your VSOC is set at 1.25V.

@Audioboxer 
I understood this 1.2.0.5 has the same VDDG issue as before, it's going to be stuck at 1.1V for both CCD and IOD.
Did you check if you can change it manually?


----------



## Audioboxer

ManniX-ITA said:


> From the screenshots looks like your VSOC is set at 1.25V.
> 
> @Audioboxer
> I understood this 1.2.0.5 has the same VDDG issue as before, it's going to be stuck at 1.1V for both CCD and IOD.
> Did you check if you can change it manually?


No, the VDDG bug is fixed










I'm now speculating that Core VID might be restricted. There have been a few other reports of people saying they aren't seeing up to 1.5v any more. My CPU light boost loads aren't getting above 5,025mhz, on 1.2.0.3c I was able to see up to 5,150mhz. VID isn't going higher than around 1.45v which is restricting the light core boost opportunity.


----------



## Dziarson

@Audioboxer this is that MSI.ROM from Unify-x thrade ranemed .
@ManniX-ITA yes it is set to 1.25 for 2000FCLK stable


----------



## Audioboxer

Dziarson said:


> @Audioboxer this is that MSI.ROM from Unify-x thrade ranemed .
> @ManniX-ITA yes it is set to 1.25 for 2000FCLK stable


Interesting, thanks, going to do some more testing with PBO/telemetry. It's possible prior PBO/curve settings are going to upset VID.

Are you using PBO?










This is after running some benching, loading a game for 5 minutes and doing some web browsing. PBO is on, no telemetry.


----------



## Dziarson

I'am overclocker all manuál now i start PBO 1000W 250W 250W 200MHz not work this agesa wont work how i want going back to bios A30


----------



## Audioboxer

Audioboxer said:


> Interesting, thanks, going to do some more testing with PBO/telemetry. It's possible prior PBO/curve settings are going to upset VID.
> 
> Are you using PBO?
> 
> View attachment 2535865
> 
> 
> This is after running some benching, loading a game for 5 minutes and doing some web browsing. PBO is on, no telemetry.


1.2.0.3c, PBO, no telemetry










Maybe one of these days AMD will be able to release a BIOS where they don't break something...

It would be funny though if the voltage being restricted like this is what is helping a bit with FCLK above 1900


----------



## PJVol

Audioboxer said:


> Maybe one of these days AMD will be able to release a BIOS where they don't break something...


It's too early to blame AMD for that, given that the AGESA part not finalized yet, and too many things have been tuned by the mb vendors themselves, and its not the first time I see some weird thing happen with a MSI betas. Lets wait for all vendors to update their firmware.


----------



## Audioboxer

PJVol said:


> It's too early to blame AMD for that, too many things have been tuned by the mb vendors themselves, and its not the first time I see some weird thing happen with a MSI betas. Lets wait for all vendors to update their firmware.


AMD introduced the VDDG voltage bug (something now fixed on this release), this is on ASUS and MSI so far. Looks like another voltage bug unless AMD are going to announce they've decided to stop their chips being fed as much voltage.


----------



## Bix

Audioboxer said:


> It would be funny though if the voltage being restricted like this is what is helping a bit with FCLK above 1900


With my non-X version of your board the amount of coil whine seems to be directly linked to overall throughput. Lowering FCLK, CPU clock speeds or loosening memory timings always reduces the amount of noise my VRM (I assume!) makes. This might explain your increase in stability and reduction in noise.


----------



## Veii

ManniX-ITA said:


> I understood this 1.2.0.5 has the same VDDG issue as before, it's going to be stuck at 1.1V for both CCD and IOD.
> Did you check if you can change it manually?


The bug came by these unimplemented feature and B2 change















@Audioboxer you will need! , to redo your CO's with 1205
They behave different - well also the boosting system is slightly different
And also "need" to remake a new profile ~ importing the old profile , can cause issues

Just can you check if you overdrive LCLK on "idle" ~ on win 11
on mouse movement FCLK_EFF and LCLK are "fixed"
but on idle it does overshoot too strongly

"MSI Stock"





AGESA 1205 - Google Drive







drive.google.com




Bios Mods:


Code:


Ace - > https://cdn.discordapp.com/attachments/578340164187979796/916413943927427102/MEG_X570_ACE-1G5.zip
B550 Unify-X -> https://cdn.discordapp.com/attachments/578340164187979796/916409170360676402/B550UNIFY-XA45.zip
X570 Unify -> https://cdn.discordapp.com/attachments/578340164187979796/916410845972561950/X570UNIFYAB4.zip

^ source HardwareLuxx and MSI/HWLuxx Bios Modding Discord


----------



## Audioboxer

Bix said:


> With my non-X version of your board the amount of coil whine seems to be directly linked to overall throughput. Lowering FCLK, CPU clock speeds or loosening memory timings always reduces the amount of noise my VRM (I assume!) makes. This might explain your increase in stability and reduction in noise.


Spot on, I guess, I'm not bothered about the coil whine, it's the mouse not jerking any more that shows progress of sorts. Though I am now interested to know if this is solely down to voltage reductions or if there are other changes with AGESA 1.2.0.5 and the newest SMU that help USB stability.

I went as far back as early MSI bios when I was testing for FCLK 2000 stability, and even on the BIOS versions before AMD starting messing with "USB stability", my mouse would still jerk. This is the first BIOS I've tried where I don't get that.


----------



## Audioboxer

Veii said:


> The bug came by these unimplemented feature and B2 change
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> @Audioboxer you will need! , to redo your CO's with 1205
> They behave different - well also the boosting system is slightly different
> And also "need" to remake a new profile ~ importing the old profile , can cause issues
> 
> Just can you check if you overdrive LCLK on "idle" ~ on win 11
> on mouse movement FCLK_EFF and LCLK are "fixed"
> but on idle it does overshoot too strongly
> 
> "MSI Stock"
> 
> 
> 
> 
> 
> AGESA 1205 - Google Drive
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> Bios Mods:
> 
> 
> Code:
> 
> 
> Ace - > https://cdn.discordapp.com/attachments/578340164187979796/916413943927427102/MEG_X570_ACE-1G5.zip
> B550 Unify-X -> https://cdn.discordapp.com/attachments/578340164187979796/916409170360676402/B550UNIFY-XA45.zip
> X570 Unify -> https://cdn.discordapp.com/attachments/578340164187979796/916410845972561950/X570UNIFYAB4.zip
> 
> ^ source HardwareLuxx and MSI Modding Discord


Yeah I didn't import, MSI don't let you import old profiles. I redid it by copying old profile values. I can jump back on and remove the CO values just to see if voltage will boost any higher but I doubt it. There are a number of reports of CORE VID not going as high on 1.2.0.5 as it did on 1.2.0.3.

I downloaded the unlocked version which I think was shared from discord in the first place.



> on mouse movement FCLK_EFF and LCLK are "fixed"


I'm guessing this is what has fixed my mouse issues at 1933~2000? From the testing I did it still seems I can't get USB stable at 1933~2000, y-cruncher test 17 is the absolute best way to find USB issues IMO. Makes my commander pro freak out within a minute. OCCT on the other hand ran for 38 minutes before I got a reboot. No USB issues, just a kernel-reboot error.

So I might still be stuck at 1900, but if AMD has fixed whatever you suggested I'd rather run this 1.2.0.5 BIOS. Only thing stopping me is the reduced voltage for the CPU as it _is_ impacting performance/boosting. I'll go test if the curve settings are making it worse.










That is ZenPT for 1.2.0.3c with telemetry enabled. Not entirely sure what 95% of this is but this is an idle screenshot!

I'll check 1.2.0.5 shortly when I switch back over to it (without PBO curve/telemetry).


----------



## Bix

Audioboxer said:


> Spot on, I guess, I'm not bothered about the coil whine, it's the mouse not jerking any more that shows progress of sorts. Though I am now interested to know if this is solely down to voltage reductions or if there are other changes with AGESA 1.2.0.5 and the newest SMU that help USB stability.


Definitely sounds like a step in the right direction 
Interested to see how you get on with the new AGESA. Going to hold off trying it out until I've sorted out my newfound stability issues...



PJVol said:


> One is AVX2/FMA instability - this should be resolved first. Not sure what the exact cause is, but i can guess some of your cores have CO magnitudes set too agressive.


Would you mind telling me a bit more about what exactly the Sandra GEMMS test stresses so much that other AVX2 tests don't? It's the only thing that causes hard crashes (or any obvious instability) with my current settings but seems to be breaking the IF completely! I've been throwing everything I've got at it - overnight core cycler, 3 hours y-cruncher, prime95, OCCT but can't get any of my cores to throw an error.


----------



## Audioboxer

Just booted into windows on 1.2.0.5 and already over 1.48v. So it seems its either PBO values, CO or a combination of both that are non-transferrable to 1.2.0.5.

Glad we've cleared that up!

PBO is not enabled above, my whole BIOS is default other than manually entering memory timings.


----------



## ManniX-ITA

Audioboxer said:


> Just booted into windows on 1.2.0.5 and already over 1.48v. So it seems its either PBO values, CO or a combination of both that are non-transferrable to 1.2.0.5.


Yes but why almost all at 1.45V in idle?
Doesn't seem right...


----------



## Audioboxer

ManniX-ITA said:


> Yes but why almost all at 1.45V in idle?
> Doesn't seem right...


Just booted into Windows, things were still loading. Idling down to 0.963v just fine.

@Veii ZenPTMonitor for 1.2.0.5 but this is without PBO


----------



## Audioboxer

Looks like it's PBO that _could_ be broken?










PBO set to enabled, everything else AUTO.










PBO set to advanced, my prior values of 270/168/220 used. Both result in voltage not going over 1.413v.

No curve in use.

*edit* - Back to PBO Auto (disabled) and the voltages are fine, seems it's PBO that is broken with this bios.


----------



## mongoled

Hold your horses!

Nothing is OK unless you can get the same result over consecutive reboots

 

Here on my lowly 5600x VID is not moving above 1.275v !

Max frequency im getting for CPU Core (SV12 TFN) is no higher than 1.369v.

However its does not seem to be effecting performance, well at least not to the effect that such a reduction in voltage should show.

The hour or so playing with 1.2.0.5 im thinking similarily to @Veii, definitely something has changed with PBO and the boosting algorithm, I can no longer get 10.5ns in L3 cache using known settings from before and can neither get it using any combination of settings that ive played with (best is 10.7 ns)

Digital Plus settings are also acting differently, along with the scaler.

Boostester still boosts all core to 4850 mhz, but with such little voltage....


----------



## Audioboxer

mongoled said:


> Hold your horses!
> 
> Nothing is OK unless you can get the same result over consecutive reboots
> 
> 
> 
> Here on my lowly 5600x VID is not moving above 1.275v !
> 
> Max frequency im getting for CPU Core (SV12 TFN) is no higher than 1.369v.
> 
> However its does not seem to be effecting performance, well at least not to the effect that such a reduction in voltage should show.
> 
> The hour or so playing with 1.2.0.5 im thinking similarily to @Veii, definitely something has changed with PBO and the boosting algorithm, I can no longer get 10.5ns in L3 cache using known settings from before and can neither get it using any combination of settings that ive played with (best is 10.7 ns)
> 
> Digital Plus settings are also acting differently, along with the scaler.
> 
> Boostester still boosts all core to 4850 mhz, but with such little voltage....


My idle boosts appear better with default than they do PBO enabled. Enabling PBO is doing something strange. Performance shouldn't end up worse than default, it should be the same and then some if you have the thermal overhead/your chip can perform a bit better.

Will do more testing but at least in terms of HWINFO readouts I've repeated the same behaviour across reboots and even going back to 1.2.0.3 and reflashing 1.2.0.5 again.

Try turning PBO off yourself and see if voltages appear to "go back to normal".


----------



## PJVol

mongoled said:


> I can no longer get 10.5ns in L3 cache using known settings from before and can neither get it using any combination of settings that ive played with (best is 10.7 ns)


What a nice fix for those complaining about reduced performance of L3 as per AIDA. It's just the baseline is 10.7 now. ))


----------



## mongoled

PJVol said:


> What a nice fix for those complaining about reduced performance of L3 as per AIDA ))


Out of curiosity I'm heading back to A85 which is the last BIOS to have the 500mhz boost overdrive working

😂😂


----------



## mongoled

Audioboxer said:


> My idle boosts appear better with default than they do PBO enabled. Enabling PBO is doing something strange. Performance shouldn't end up worse than default, it should be the same and then some if you have the thermal overhead/your chip can perform a bit better.
> 
> Will do more testing but at least in terms of HWINFO readouts I've repeated the same behaviour across reboots and even going back to 1.2.0.3 and reflashing 1.2.0.5 again.
> 
> Try turning PBO off yourself and see if voltages appear to "go back to normal".


No difference on this 5600x between AUTO and manual tweaking with regards to VID


----------



## Audioboxer

mongoled said:


> No difference on this 5600x between AUTO and manual tweaking with regards to VID


Weird, turning on PBO in any shape or form nukes my max VID.

Default seems to be working quite decent for me anyway, will just stay here for now. Want to test TM5 again to see if I still get timeouts.


----------



## PJVol

mongoled said:


> Out of curiosity I'm heading back to A85 which is the last BIOS to have the 500mhz boost overdrive working


Yeah, that's a funny toy. I've got the same custom bios with a 1.1.9.0D agesa (kindly provided by asrock). 
You know, what I'm really missing on my board (don't know if other boards have it) is the rom space to flash two FW versions and be able to choose one at boot, that would be great.


----------



## mongoled

PJVol said:


> Yeah, that's a funny toy. I've got the same custom bios with a 1.1.9.0D agesa (kindly provided by asrock).
> You know, what I'm really missing on my board (don't know if other boards have it) is the rom space to flash two FW versions and be able to choose one at boot, that would be great.


For sure would be great but unfortunately mobo manufacturers would deem that as a premium XOC feature and add 200€ onto the cost of the motherboard

😂


----------



## nada324

Hey guys, do you know, what can trigger error #2? I check Vei's tm5 error but still dont know if its proc ODT or cad bus.

Here are my settings:


----------



## dk_mic

about agesa 1205 from MSI: are those even official versions?
afaik they all come from this source posted here
ROG CROSSHAIR VIII Series 3903 BETA BIOS WITH AGESA 1.2.0.5 - 电脑讨论 - Chiphell - 分享与交流用户体验
文件分享
(post #24)


----------



## Bix

PJVol said:


> I think there are two unrelated issues you encountered. One is AVX2/FMA instability - this should be resolved first. Not sure what the exact cause is, but i can guess some of your cores have CO magnitudes set too agressive.
> The other issue... Well, it's to be kinda expected. I just have a slightly different (and not very popular here) view of what cause the 1900+ fclk issue and how to reliably identify it.
> So, the less stable fclk overclock, the more severe gemm performance regression is observed, depending on how well interconnect PHY responses to FCLK overclock, that in itself is affected by a number of contributing factors, rather just "one toggle" in bios or elsewhere.


Not sure if you saw my last post but if you did, I think I've fixed the instability issue. Re-ran the Sandra tests today after other testing and it's passing fine now. I think that the voltage settings might not have updated properly when I was switching from 1800 FCLK back to 2000 and crashes were due to ****y MSI auto VDDP/VDDG voltages.

GEMM test results still show some regression though - now I'm getting around 320 Gflops at 2000 compared to around 380 Gflops at 1800. There's probably not a straight forward answer to this but would you consider that level of perf decrease problematic?

Edit: Aggregated Scientific Performance stays roughly the same and FFT improves (19 at 2000 compared to 16.5 at 1800)


----------



## Imprezzion

Well, I did my best to get 2000 F/MCLK to run and while it will boot pretty easily on 4000C16 for the RAM 1:1 I'm getting a shocking amount of interconnect errors even at 1.25v SOC with all sorts of VDDG / IOD combinations. Some make it better some make it worse but it won't stabilize at all. The best I've gotten it so far is 1.25 SOC, 1.05 CLDO, 0.95 CCD, 1.05 IOD. This is the setup at which it gets the least amount of errors but still 10 errors in like 5 minutes of just idle lol. I have no idea where to go with the voltages from here anymore..

It also seems SOC voltage has no impact on it at all. I can run 1933 + 3866 15-15-15 just fine in TM5 at just 1.081v SOC but bumping up to 1966 + 3933 won't show any signs of stabilizing even at 1.26v SOC. So maybe I'm doing things the wrong way and I shouldn't try to brute force it with more volts but maybe I have to actually lower some voltages here and there..


----------



## domdtxdissar

Audioboxer said:


> View attachment 2535872
> 
> 
> Just booted into windows on 1.2.0.5 and already over 1.48v. So it seems its either PBO values, CO or a combination of both that are non-transferrable to 1.2.0.5.
> 
> Glad we've cleared that up!
> 
> PBO is not enabled above, my whole BIOS is default other than manually entering memory timings.


5 pages ago in this thread


----------



## Audioboxer

domdtxdissar said:


> 5 pages ago in this thread
> View attachment 2535907


Yeah that works it seems and interestingly even going to 150 causes it to freak out again.

140 seems a bit on the low side for using PBO, but I guess it's something!

But with EDC this low my CB23 score with PBO enabled isn't too much better than with it off. Off is like 25k, on is like 28k.

All of that pales in comparison to 1.2.0.3c PBO performance up at 31k.


----------



## domdtxdissar

Audioboxer said:


> Yeah that works it seems and interestingly even going to 150 causes it to freak out again.
> 
> 140 seems a bit on the low side for using PBO, but I guess it's something!
> 
> But with EDC this low my CB23 score with PBO enabled isn't too much better than with it off. Off is like 25k, on is like 28k.
> 
> All of that pales in comparison to 1.2.0.3c PBO performance up at 31k.


If i were to take a guess, this will be the future from all the motherboard manufacturers in preparation for the Zen3 v-cache launching early next year..
3d stacked $ ontop of regular L3 $ can/will cause heat problems, so to remedy this, the max singlecore boost voltage is reduced from 1500mv to 1425mv

One thing hydra/ctr have shown us is that most efficient voltage range for zen3 is upto ~1375-1425mv... Above that you don't really gain much higher mhz for the watt/heat increase... Can even get negative scaling with less than stellar cooling (we see maybe 25-50mhz difference between 1400mv to 1500mv with todays silicon quality)

But it should also be said that i won't be surprised if Zen 3D clock higher @ 1425mv than regular Zen3 @ 1500mv thanks to improved manufacturing(silicon quality) on a mature 7nm node by now..


----------



## Imprezzion

3866 + 1933 FCLK / MCLK is fine. Did have to raise vSOC quite a bit as it kept dropping WHEA's all the way up to 1.15v but 1.175v fixed that.


----------



## PJVol

Bix said:


> Not sure if you saw my last post but if you did, I think I've fixed the instability issue


Nice. TBH, i saw your post, i just hadn't a definitive answer on "how to" cause it's particular config specific. Now, as you solved it, you can check, if it works from boot to boot. If so, then you can compare the results.


----------



## Audioboxer

domdtxdissar said:


> If i were to take a guess, this will be the future from all the motherboard manufacturers in preparation for the Zen3 v-cache launching early next year..
> 3d stacked $ ontop of regular L3 $ can/will cause heat problems, so to remedy this, the max singlecore boost voltage is reduced from 1500mv to 1425mv
> 
> One thing hydra/ctr have shown us is that most efficient voltage range for zen3 is upto ~1375-1425mv... Above that you don't really gain much higher mhz for the watt/heat increase... Can even get negative scaling with less than stellar cooling (we see maybe 25-50mhz difference between 1400mv to 1500mv with todays silicon quality)
> 
> But it should also be said that i won't be surprised if Zen 3D clock higher @ 1425mv than regular Zen3 @ 1500mv thanks to improved manufacturing(silicon quality) on a mature 7nm node by now..


That would still suck if AMD artificially throttled our voltage. Fair enough if the new chips don't need to go higher but we can still squeeze a bit more performance out of ours. I get the point of diminishing returns but if you do have really good cooling it should be up to you if you want to hammer your CPU for the last 50mhz.

There is always the chance the voltage reading is simply bugged when over 140 EDC. Would need to do extensive benchmarking to test this. From what little I seen my cores weren't boosting as high tapping out at 5050 on 1.2.0.5 while they were 5150 on 1.2.0.3c. But I do know due to some changes copying your old PBO and curve settings into 1.2.0.5 isn't recommended.

In case it is a bug I'll probably just wait it out until a proper public release. Unless AMD pull another 1.2.0.4 on us and never formally release this...


----------



## dk_mic

maybe, on 1805, a positive vcore offset, so you're back at 1.5V and completely re-tuned curve will improve scores compared to earlier agesa?
i would also wait for official beta versions, nothing has appeared on vendors homepages yet.. all of this is from forums and wechat, and i think 1205 is still work in progress?


----------



## Bix

PJVol said:


> Now, as you solved it, you can check, if it works from boot to boot. If so, then you can compare the results.


Will do, thanks. I want to look at how the results negatively scale with FCLK if they look consistent from boot to boot.


----------



## PJVol

Bix said:


> I want to look at how the results negatively scale with FCLK if they look consistent from boot to boot.


Mind you, that boot-to-boot inconsistencies may be specific for my config.
Some time ago, i compared the behavior of my 5600X @IF>1900 on two platforms (both in my signature), and it turns out, the cheaper MSI platform let it run up to 2000, without WHEA's and perf. regression, wheras on my home pc i have to push vdd18 voltage to 2.05-2.1v to not let it drop perf. in memory intensive tests.

Later i realized what was the reason for this difference. Basically, it all comes from a poor VRM design on the Asrock board. The vdroop on both rails is so massive, that even max. LLC is hardly able to minimize it. Cpu LLC1 helped only for the loads up to 108-110W for the PPT and with a EDC limited to 95-100A. The same goes for the Soc rail, where the #19 related issues rises from.

On the 1st screen I compared GEMM results at various FCLK, just with or without vdd18 bruteforcing for high FCLK.
The 2nd (made it yesterday) shows additional PPT/EDC limitation introduced (105/95) coupled with a "strong" LLC just for the 2000 fclk runs. The bottom result herein shows what happens with PPT>110 or EDC>100 or both, regardless of the VDD18 value. Running @IF1900 within the same restrictions yields ~ 190-195GFlops.

So, atm, i think the #19 issue is kinda EDC throttling related, that's getting worse, if vrm can't keep up with a fast transient loads. The throttler itself has thresholds for the different type of workloads, that made the whole thing even more confusing and thats why, i think, you won't see EDC exceeding ~220 amps for the 105W chips and ~125A for the 65W ones if cpu is not in OC mode.

UPD: Added screens from testing 5600X on a MSI B450 board comparing 1900, 2000 and 2033 FCLK. No vdd18 or PPT/EDC/LLC trickery.


----------



## defcoms

Piers said:


> Fascinating read. Does anyone have experience with the 'Optimised for Ryzen' Corsair memory (CMK32GX4M2Z3600C18)? Generally Micron, single rank, 3600 CL18.


Yeah I'm running that kit works great on my Asus dark hero. I'm running them @ 3800c16 DOCP worked great on my board. My sticks turned out to be MicronE Rev B0.


----------



## Piers

defcoms said:


> Yeah I'm running that kit works great on my Asus dark hero. I'm running them @ 3800c16 DOCP worked great on my board. My sticks turned out to be MicronE Rev B0.


Any chance you could share primary timings?


----------



## defcoms

Piers said:


> Any chance you could share primary timings?


Here you go. I just used the dram calculator didn't spend much time tweaking them any further.


----------



## 67091

Hi guys long time lurker not a big poster.
Any how i would like to know if many people have got 4 sticks working without gear down mode stable?


----------



## mongoled

angushades said:


> Hi guys long time lurker not a big poster.
> Any how i would like to know if many people have got 4 sticks working without gear down mode stable?


Look at my signature, that's affirmative 😃


----------



## Audioboxer

Good news, TM5 going through a 50 cycle on AGESA 1.2.0.5 without timing out.

Bad news, an error 










@Veii What is your opinion on a single 14? Try increasing CmdDrvStr to 24? Odt to 30?

It could also be added that me running the v3.11.17.521 chipset drivers shows they are being tested behind the scenes for AGESA 1.2.0.5 (as in timeouts could have been related to chipset drivers running on 1.2.0.3). That and it might simply be the case all the changes AMD has made with 1.2.0.5 is also going to throw off some old memory OC profiles.

Never ran the above on a 50 cycle before (just anta777 for longer runs), but it's been put through plenty of 25 cycles prior till now.


----------



## mongoled

Someone used the microwave ??

Or high speed particles causing bit flips

😃 😃


----------



## Frosted racquet

Just as a FYI, I've had TM5 timeouts with stock CPU configuration (memory stability was debatable) so that behavior at least isn't limited to unstable CPU OC.


----------



## Audioboxer

Frosted racquet said:


> Just as a FYI, I've had TM5 timeouts with stock CPU configuration (memory stability was debatable) so that behavior at least isn't limited to unstable CPU OC.


With the AGESA 1.2.0.3 and chipset v3.11.17.521 I repeated like 8 or 9 timeout runs in a row with CPU on AUTO (default). First run I do on 1.2.0.5 with CPU on AUTO and it's fine.

My new power supply is coming today though so immediate attention turns to it and then testing the 12v rail. The solitary error 14 will have to wait!


----------



## Mach3.2

Run Xeons and ECC DIMMs 🤣

I know you're in a error free zone but I don't think I can convince myself to fix that 1 error that occured in 50 cycles lol. That's at least a 5 hour+ validation cycle every time I try something new.


----------



## Audioboxer

Mach3.2 said:


> Run Xeons and ECC DIMMs 🤣
> 
> I know you're in a error free zone but I don't think I can convince myself to fix that 1 error that occured in 50 cycles lol. That's at least a 5 hour+ validation cycle every time I try something new.


Quite confident a minor tweak to resistances will fix it. Going to try CkeDrvStr to 30 first.


----------



## Audioboxer

Corsair PSU cables are absolutely horrible! Stiff as anything and some bright spark at Corsair seemed to think it was a good idea daisy chaining every PCIE cable supplied. So if you want to run separate cables to your GPU you've got a messy 2nd connection hanging loose.

Gotta say props to Asus/Seasonic for the soft cabling. I would buy 3rd party to replace the Corsair stuff but funnily enough a poster in this topic had 12v voltage drops because of Cablemate or is it Cablepro cables?

If the 12v rail is fine with these cables I'll try my Thor cables. Gotta test with full Corsair first.


----------



## Frosted racquet

Audioboxer said:


> If the 12v rail is fine with these cables I'll try my Thor cables.


PSU cables are not interchangeable between brands, you know that right?


----------



## ManniX-ITA

Audioboxer said:


> Gotta say props to Asus/Seasonic for the soft cabling. I would buy 3rd party to replace the Corsair stuff but funnily enough a poster in this topic had 12v voltage drops because of Cablemate or is it Cablepro cables?











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


I might be in danger as well, all these PSU talk had me take a closer look at the 12V in voltage read outs. Voltage sits right at 12V with no load, and droops down to 11.7 - 11.8V with a ~280w load on the GPU. Meh that's still acceptable. It ain't great but not out of spec bad at least. I...




www.overclock.net





Someone suggested good 3rd party cables but I don't recall...



Audioboxer said:


> Corsair PSU cables are absolutely horrible! Stiff as anything and some bright spark at Corsair seemed to think it was a good idea daisy chaining every PCIE cable supplied. So if you want to run separate cables to your GPU you've got a messy 2nd connection hanging loose.


I'm probably wrong but I can only associate more stiffness to a better cable 
The daisy chaining is pretty common... the Thor had all 8 cables separate?
Not the best indeed but connectors are the weakest part. Less you have and more reliable it is...



Audioboxer said:


> If the 12v rail is fine with these cables I'll try my Thor cables. Gotta test with full Corsair first.


As said by @Frosted racquet they are generally not exchangeable, be careful.


----------



## Audioboxer

Frosted racquet said:


> PSU cables are not interchangeable between brands, you know that right?


Nope, but I would have found that out shortly lmao.

@mongoled Thor had 1 daisy chain cable and the rest were seperate.


----------



## mongoled

Audioboxer said:


> Nope, but I would have found that out shortly lmao.
> 
> @mongoled Thor had 1 daisy chain cable and the rest were seperate.


Ammendment
@Frosted racquet @ManniX-ITA Thor had 1 daisy chain cable and the rest were seperate.

😃 😂


----------



## Audioboxer

This is no better/possibly even worse than the Thor. The iCUE reading reads 12v, but HWINFO is less.

These are also the absolute worst cables I've ever dealt with. What a mess. When you've got a commander pro, a fan hub, 2 RGB units and 17 fans it kind of makes it near impossible to do your cable routing at the back of an O11 XL with PSU cables this inflexible. I haven't even closed the case yet.

The only thing I think I can check now is trying to draw wall power from another source. I did change to Single OCP in iCUE.










Without the frame rate cap (144 in Nvidia control panel) looks dreadful in HWINFO. ICUE still reporting 12v. On idle it reports 12.10v










What do you believe then? Or could this be a GPU problem?


----------



## mongoled

Audioboxer said:


> View attachment 2536078
> 
> 
> This is no better/possibly even worse than the Thor. The iCUE reading reads 12v, but HWINFO is less.
> 
> These are also the absolute worst cables I've ever dealt with. What a mess. When you've got a commander pro, a fan hub, 2 RGB units and 17 fans it kind of makes it near impossible to do your cable routing at the back of an O11 XL with PSU cables this inflexible. I haven't even closed the case yet.
> 
> The only thing I think I can check now is trying to draw wall power from another source. I did change to Single OCP in iCUE.
> 
> View attachment 2536081
> 
> 
> Without the frame rate cap (144 in Nvidia control panel) looks dreadful in HWINFO. ICUE still reporting 12v. On idle it reports 12.10v
> 
> View attachment 2536083
> 
> 
> What do you believe then? Or could this be a GPU problem?





mongoled said:


> I can see the outcome, you get a new PSU and the 12v reading remain the same


😂😂

Well at least you got a free PSU, I should try that trick with Amazon.de in a years time, God do they deserve that type of treatment even though I am very much against such shenanigans


----------



## Audioboxer

mongoled said:


> 😂😂
> 
> Well at least you got a free PSU, should try that trick with Amazon.de in a years time, God do they deserve that type of treatment even though I am very much against such shenanigans


2 PSUs, different brands, exactly the same? There's gotta be another variable here. Whether it's the motherboard, GPU or maybe my power source which I am going to check shortly. Would also suggest Corsair are cheating if they don't report the 12V voltage dip below 12v.


----------



## ManniX-ITA

Audioboxer said:


> What do you believe then? Or could this be a GPU problem?


I'm baffled 



Audioboxer said:


> 2 PSUs, different brands, exactly the same? There's gotta be another variable here. Whether it's the motherboard, GPU or maybe my power source which I am going to check shortly. Would also suggest Corsair are cheating if they don't report the 12V voltage dip below 12v.


Very likely those voltage readings will never go below 3.30V, 5.00V and 12.00V 

But indeed there must be another variable... can't be both PSU are behaving so similarly bad.
At 344W that PSU shouldn't almost flinch from 12.10V.

It's really hard to disconnect stuff from such a build... try first with the minimal external devices, cutting all USB except K/M.
If you have a displayPort cable it's a good idea to test with an HDMI. Just to be sure.


----------



## mongoled

Audioboxer said:


> 2 PSUs, different brands, exactly the same? There's gotta be another variable here. Whether it's the motherboard, GPU or maybe my power source which I am going to check shortly. Would also suggest Corsair are cheating if they don't report the 12V voltage dip below 12v.


Its all Seasonics fault

😍😍

Seriously though, im sure you have understood me from before, but I feel you have been swayed by others regards the 12v rail, I saw it as a non issue as long as there was no instability.

And as you had an issue with instability I would not have been looking towards the PSU to diagnose it at least not in the initial stage ..

Though I dont have much experience in running high powered graphics cards ....


----------



## Frosted racquet

Maybe it's just the fact you're using a riser cable of any kind. Maybe those voltage dips are unrelated to GPU stability issues when OCing.


----------



## ManniX-ITA

mongoled said:


> Seriously though, im sure you have understood me from before, but I feel you have been swayed by others regards the 12v rail, I saw it as a non issue as long as there was no instability.


I would have done the same, replaced the PSU (especially since it was basically for free).
It's not normal for an high end PSU to drop so much with such low load.
But that it isn't the PSU, neither the cables that are usually the other culprit, it's really weird.
It's indeed Seasonic's fault 



Audioboxer said:


> Or could this be a GPU problem?


If you could find another nVidia GPU to plug-in and test would be better.


----------



## Audioboxer

ManniX-ITA said:


> I'm baffled
> 
> 
> 
> Very likely those voltage readings will never go below 3.30V, 5.00V and 12.00V
> 
> But indeed there must be another variable... can't be both PSU are behaving so similarly bad.
> At 344W that PSU shouldn't almost flinch from 12.10V.
> 
> It's really hard to disconnect stuff from such a build... try first with the minimal external devices, cutting all USB except K/M.
> If you have a displayPort cable it's a good idea to test with an HDMI. Just to be sure.


Going to try with HDMI cable and another power source.



mongoled said:


> Its all Seasonics fault
> 
> 😍😍
> 
> Seriously though, im sure you have understood me from before, but I feel you have been swayed by others regards the 12v rail, I saw it as a non issue as long as there was no instability.
> 
> And as you had an issue with instability I would not have been looking towards the PSU to diagnose it at least not in the initial stage ..
> 
> Though I dont have much experience in running high powered graphics cards ....


Crashing seems to have stopped with me reducing the core boost on the GPU, at least in terms of like 60 TimeSpy's passing without a kernel-power failure. That was on the Thor mind you.

Will need to test this PSU now. If it works fine it works fine, a 1000w PSU is better for future proof and it's quite handy having it integrated into iCUE.



ManniX-ITA said:


> I would have done the same, replaced the PSU (especially since it was basically for free).
> It's not normal for an high end PSU to drop so much with such low load.
> But that it isn't the PSU, neither the cables that are usually the other culprit, it's really weird.
> It's indeed Seasonic's fault
> 
> 
> 
> If you could find another nVidia GPU to plug-in and test would be better.


Spare GPUs, yeah, I'm sure they are easy to find right now 

This GPU is already an RMA seeing as my 2080Ti died on me. The fact it's an RMA might have some of you concerned it's a poor repair/RMA.

I'd guess right now the Corsair is actually dropping a bit lower than the Thor! I could try some of the other included PCIe cables, but I seriously doubt cables have anything to do with it.


----------



## ManniX-ITA

Audioboxer said:


> Spare GPUs, yeah, I'm sure they are easy to find right now
> 
> This GPU is already an RMA seeing as my 2080Ti died on me. The fact it's an RMA might have some of you concerned it's a poor repair/RMA.


Nowadays you can find GPUs in chips bags... pretty annoying when you are hungry!
Indeed if the GPU is an RMA the readings could be not so much reliable... 
I recall once you changed the riser cable the 12V board reading was fine.
I'd go for stability tests now just to be sure and wait for a new GPU to consider again this topic.
Corsair PSUs as well have a long warranty


----------



## Mach3.2

mongoled said:


> 😂😂
> 
> Well at least you got a free PSU, I should try that trick with Amazon.de in a years time, God do they deserve that type of treatment even though I am very much against such shenanigans


Eh just don't go overboard with the returns/refunds, I think I did when I returned 3 B-die kits in short order. They sent me a thinly veiled warning email on my next order.😶


----------



## mongoled

Mach3.2 said:


> Eh just don't go overboard with the returns/refunds, I think I did when I returned 3 B-die kits in short order. They sent me a thinly veiled warning email on my next order.😶


That's the thing I don't, but they deserve it due to their terrible customer support. I'm fuming with them right now, bought the Zotac MagnusOne barebone which was advertised coming with a Windows 10 Home edition OS, which of ofcourse it didn't, but instead of focusing on the mis advertised product they are attempting to pass the buck to Zotac, effing unbelievable....


----------



## Audioboxer

ManniX-ITA said:


> Nowadays you can find GPUs in chips bags... pretty annoying when you are hungry!
> Indeed if the GPU is an RMA the readings could be not so much reliable...
> I recall once you changed the riser cable the 12V board reading was fine.
> I'd go for stability tests now just to be sure and wait for a new GPU to consider again this topic.
> Corsair PSUs as well have a long warranty


The riser cable change seemed to help a bit with the Thor power supply (though under heavy load it could still drop under 12v).

This Corsair power supply seems to go even lower than the Seasonic 

Changing the power source didn't help. I guess only other thing I can do is change to HDMI, but I can't see how a DP cable could reduce voltage lol.

Chances are it's the GPU and maybe the Thor power supply is generally a bit better than this one. Though I'd rather run a 1000w power supply for futureproofing. Everyone dunking on the Thor and it was clearly holding its own!

I don't think my turn in the EVGA step up queue for Europe will be here before next Summer. It's that bad. They've only got to early October 2020 for the 3080. My step up was registered in November 2020.



mongoled said:


> That's the thing I don't, but they deserve it due to their terrible customer support. I'm fuming with them right now, bought the Zotac MagnusOne barebone which was advertised coming with a Windows 10 Home edition OS, which of ofcourse it didn't, but instead of focusing on the mis advertised product they are attempting to pass the buck to Zotac, effing unbelievable....


I honestly think they just refunded me because they had no stock, goodness knows how Amazon has to handle ASUS RMAs (probably paperwork if not Amazon just binning the PSU and sending you a replacement) and the fact I can't remember the last time I had a problem on Amazon. Been years. So "valued customer" and all that nonsense.

Though I just think it was the fact they've got no stock and got lucky on the phone with whomever I was speaking to.


----------



## Bix

PJVol said:


> Mind you, that boot-to-boot inconsistencies may be specific for my config.


Sadly not - after closer inspection today I still got considerable variance between reboots at 2000 FCLK with frequent crashes. When the test did pass I made three runs before rebooting and the results of each boot were similar (1800 FCLK results included for ref):












PJVol said:


> on my home pc i have to push vdd18 voltage to 2.05-2.1v to not let it drop perf. in memory intensive tests


VTT was on auto which is 1.83V on my MB - I tried upping this first but that just increased the instability. I then lowered it to 1.77V set in order to get 1.8V and results are looking a lot more consisent with no crashes as yet... I'm going to try fine-tuning this a bit more to see how that affects the scores/consistency before moving on to LLC. Both CPU and SOC are still on auto LLC which are both pretty droopy so interested to see if that improves things as well.



PJVol said:


> UPD: Added screens from testing 5600X on a MSI B450 board comparing 1900, 2000 and 2033 FCLK. No vdd18 or PPT/EDC/LLC trickery.


Interesting, thanks - so those results are with auto LLC?

EDIT: 


PJVol said:


> So, atm, i think the #19 issue is kinda EDC throttling related, that's getting worse, if vrm can't keep up with a fast transient loads. The throttler itself has thresholds for the different type of workloads, that made the whole thing even more confusing and thats why, i think, you won't see EDC exceeding ~220 amps for the 105W chips and ~125A for the 65W ones if cpu is not in OC mode.


TBH I'm finding PBO limits pretty confusing already! I've experimented a lot with different PPT, TDC and EDC values but hadn't even considered that EDC could relate to #19s...


----------



## mongoled

Audioboxer said:


> The riser cable change seemed to help a bit with the Thor power supply (though under heavy load it could still drop under 12v).
> 
> This Corsair power supply seems to go even lower than the Seasonic
> 
> Changing the power source didn't help. I guess only other thing I can do is change to HDMI, but I can't see how a DP cable could reduce voltage lol.
> 
> Chances are it's the GPU and maybe the Thor power supply is generally a bit better than this one. Though I'd rather run a 1000w power supply for futureproofing. Everyone dunking on the Thor and it was clearly holding its own!
> 
> I don't think my turn in the EVGA step up queue for Europe will be here before next Summer. It's that bad. They've only got to early October 2020 for the 3080. My step up was registered in November.
> 
> 
> 
> I honestly think they just refunded me because they had no stock, goodness knows how Amazon has to handle ASUS RMAs (probably paperwork if not Amazon just binning the PSU and sending you a replacement) and the fact I can't remember the last time I had a problem on Amazon. Been years. So "valued customer" and all that nonsense.
> 
> Though I just think it was the fact they've got no stock and got lucky on the phone with whomever I was speaking to.


The "Amazons" in each country have no correlation with regards to how they treat their customers. 

Just have a compare of .co.uk to .de on trustpilot 😉


----------



## mongoled

mongoled said:


> The "Amazons" in each country have no correlation with regards to how they treat their customers.
> 
> Just have a compare of .co.uk to .de on trustpilot 😉


Ehhhh, .co.uk used to be much better wtfeck all down hill.....


----------



## Audioboxer

mongoled said:


> The "Amazons" in each country have no correlation with regards to how they treat their customers.
> 
> Just have a compare of .co.uk to .de on trustpilot 😉


I could guess they're all shocking lol. Depends on the "complexity" of your query I guess. I'm surprised they didn't ask me to ship it back even if it was heading for a landfill, so as I said I might just have gotten lucky on the day.

Now I have 2 PSUs and the one I've replaced might be better


----------



## ManniX-ITA

Audioboxer said:


> Changing the power source didn't help. I guess only other thing I can do is change to HDMI, but I can't see how a DP cable could reduce voltage lol.


A bad DP cable can do unspeakable things, like blowing off the GPU and/or mainboard  



Audioboxer said:


> Chances are it's the GPU and maybe the Thor power supply is generally a bit better than this one. Though I'd rather run a 1000w power supply for futureproofing. Everyone dunking on the Thor and it was clearly holding its own!


More inclined to think it's the GPU or something else... What about the mainboard 12V sensor? Does it read like iCUE?


----------



## mongoled

ManniX-ITA said:


> I would have done the same, replaced the PSU (especially since it was basically for free).
> It's not normal for an high end PSU to drop so much with such low load.
> But that it isn't the PSU, neither the cables that are usually the other culprit, it's really weird.
> It's indeed Seasonic's fault
> 
> If you could find another nVidia GPU to plug-in and test would be better.


Yeah, we all have our own methods and depth of experiences, though I never would consider the drop Audioboxer was seeing as an "issue", so yeah Seasonic fault


----------



## Audioboxer

ManniX-ITA said:


> A bad DP cable can do unspeakable things, like blowing off the GPU and/or mainboard
> 
> 
> 
> More inclined to think it's the GPU or something else... What about the mainboard 12V sensor? Does it read like iCUE?


Really? Damn. I'll go dig out a spare HDMI cable and have a check.










Is that the reading from here? If so it drops from like 12.192v in idle to 12.096V under load. I guess this is where iCUE is taking its reading from. Cause it reads 12.1v on idle and 12v under load.

Only rail above that seems to dip a bit below under load is the 3.3V. But I guess 3.28v isn't too worrying.

If it's the GPU is it possible because this is a 1000w that it might read a bit lower than the 850w Thor on the GPU readings? Noob question I know, but just wondering if I had a 850w Corsair and it's the GPU that is performing poorly, if the 850w 12v figures would be similar between Thor/Corsair. Someone mentioned pages ago dipping under 12v becomes less of a concern if your power supply can maintain itself consistently and I'm just wondering if a 1000w power supply can potentially do that at a lower GPU voltage read?

Going to go run back to back TimeSpys stability tests for a bit anyway, that's a better test than me taking guesses on topics of electrical engineering where I have no real knowledge lol. But when in doubt, just blame the GPU. I've now replaced a riser cable, a PSU and the cables going from the PSU to the GPU 

Up next, HDMI cable and TimeSpy...


----------



## dk_mic

@Audioboxer 
I was curious, so i replaced my 2080 Ti with my old 980 Ti.. 
This is the 2080 Ti, and i was worried about my Seasonic Prime TX 750 was ****









Now this is the 980 Ti









so it really looks like its a GPU thing, not a PSU thing


----------



## mongoled

dk_mic said:


> @Audioboxer
> I was curious, so i replaced my 2080 Ti with my old 980 Ti..
> This is the 2080 Ti, and i was worried about my Seasonic Prime TX 750 was ****
> View attachment 2536103
> 
> 
> Now this is the 980 Ti
> View attachment 2536105
> 
> 
> so it really looks like its a GPU thing, not a PSU thing


Are they pulling similar amount of power?


----------



## ManniX-ITA

Audioboxer said:


> so it really looks like its a GPU thing, not a PSU thing


Could be the 2080ti are not so reliable... I had seen only reading from 3000s till now.



Audioboxer said:


> I guess this is where iCUE is taking its reading from. Cause it reads 12.1v on idle and 12v under load.


No, iCUE is reading directly from the PSU.
The board sensor it's on its own.
I'm starting to consider more likely that the GPU is not reliable 
Run stability tests.
Except the stiff cables the Corsair is indeed more future proof than the Thor.


----------



## dk_mic

mongoled said:


> Are they pulling similar amount of power?


well the 980 ti was running timespy extreme at 110% powerlimit
i don't know what i have run on the 2080 ti.

Just put the card back in the system, couldn't completely reproduce, but here it is at stock (timespy extreme + port royal) with maybe 20-30 W more than the 980 Ti and one with 130% powerlimit (port royal)

stock









130%


----------



## ManniX-ITA

dk_mic said:


> i don't know what i have run on the 2080 ti.


It's better to run Port Royale as it doesn't load the CPU, like Timespy.
Looks like the 2080Ti readings are made not exactly at the Input...
Anyway 200mV is still pretty good considering the peak was probably around 75%.


----------



## PJVol

Bix said:


> VTT was on auto which is 1.83V on my MB - I tried upping this first but that just increased the instability. I then lowered it to 1.77V set in order to get 1.8V and results are looking a lot more consisent with no crashes as yet...


Lol, it's funny 'cause AFAIK the HWInfo with a MSI boards wrongly reports VDD18 voltage as "VTT", and in the MSI BIOS it is under PLL1.8 setting, but I may be wrong here - there are many MSI owners here to correct. Just curious, did you actually tuned the VTT? 
In any case, I would not touch the PLL on MSI, as the owners here reported it doesn't have the same effect as on the asrock .


----------



## ManniX-ITA

PJVol said:


> Just curious, did you actually tuned the VTT?


Yes the HWInfo VTT reading changes when you set "CPU 1P8" in BIOS


----------



## Audioboxer

ManniX-ITA said:


> Could be the 2080ti are not so reliable... I had seen only reading from 3000s till now.
> 
> 
> 
> No, iCUE is reading directly from the PSU.
> The board sensor it's on its own.
> I'm starting to consider more likely that the GPU is not reliable
> Run stability tests.
> Except the stiff cables the Corsair is indeed more future proof than the Thor.


Been running back to back TimeSpy. Just starting an extreme now to hurt the card a bit more running at 4K even tho monitor is 1440p. No crashes so far.

I honestly think my kernel power crashes might have been pushing the core clock a bit high for this card. The card that died on me was happy around 2085-2100, this one seems to start struggling around 2075. Issue is any time I've OCed graphics cards before unstable core resulted in the game or app crashing. This is the first time I've experienced a kernel power 41.

Which then led me down this rabbit hole of checking the 12v readings because I came into this topic worried about kernel power crashing during TimeSpy lol. I presume an unstable core clock can indeed cause a reboot?

Chances are there is absolutely nothing wrong with my Thor power supply. I'm going to see instead of borrowing a friend's power supply if I can take it to them and ask them to hook it up to their machine. 

Still a bit unsure why the Corsair might dip a bit lower than the Thor, but as I was speculating on earlier it might just be because it's a 1000w. That or the dodgy GPU preferred the Seasonic 😂 If games don't crash though I guess I can't complain too much about a 2055 core and 8000 memory. That's about average for a 2 pin 2080Ti I'd think.


----------



## Bix

PJVol said:


> Lol, it's funny 'cause AFAIK the HWInfo with a MSI boards wrongly reports VDD18 voltage as "VTT", and in the MSI BIOS it is under PLL1.8 setting, but I may be wrong here - there are many MSI owners here to correct. Just curious, did you actually tuned the VTT?


No you're spot on, it's called PLL1.8 in the bios which shows as VTT in HWinfo, right? I think I've got it right


----------



## PJVol

@ManniX-ITA
Thanks, mate. Never been able to sort out this kind of terminology mess 



Bix said:


> I think I've got it right


So in the end, did i get it right that adjusting PLL to 1.77 got you back the consistent results in a GEMM tests, basically with no significant regression?



Bix said:


> Interesting, thanks - so those results are with auto LLC?


Yep, as I guess you've already noticed, how differently those two mb behave in such scenarios.


----------



## Audioboxer

Premium Individually Sleeved PSU Cables Pro Kit Type 4 Gen 4 – Black


The CORSAIR Premium Individually Sleeved Type 4 Gen 4 Pro Kit includes everything you need to fully upgrade your PSU cables to flexible paracord sleeve, available in seven different colors and patterns.




www.corsair.com





These are basically what Asus include in their Thor package, so thumbs down to Corsair still using the cheap crappy stiff cables in the HXi power supplies. Please don't tell me the AXi still uses them?

Bloody expensive as well for replacement cables, but I think I'll have to get them at some point. Don't trust 3rd party and I doubt they'll be any cheaper.


----------



## Bix

PJVol said:


> So in the end, did i get it right that adjusting PLL to 1.77 got you back the consistent results in a GEMM tests, basically with no significant regression?


Yes, that's right. Not sure if it's caused any issues elsewhere but Linpack scores still holding up and will have to do some more stability testing later.


----------



## ManniX-ITA

Audioboxer said:


> Please don't tell me the AXi still uses them?


I'm not saying anything 



Audioboxer said:


> Bloody expensive as well for replacement cables


Same for my EVGA but... they are even more expensive and they are not available. Like never available...


----------



## Audioboxer

ManniX-ITA said:


> I'm not saying anything
> 
> 
> 
> Same for my EVGA but... they are even more expensive and they are not available. Like never available...


Just noticed it's Type 3 I need due to my power connector being 24 pin, so that was almost a costly mistake lol. Type 4 is OOS directly from Corsair, but type 3 is in stock here.


----------



## Veii

Many many pages, please let me not mess up the name again
@Audioboxer ?, i think ... 🙈
The 1.4VID change is a good thing
I didn't expect it, just they should've known it clearly

But here AMD goes for efficiency yes
1.4v VID SVI2 after dld0 , was the hardcap after when CPUs start to throttle back by FIT
This was an unannounced range that always was applied
It didn't matter that FIT-PRE-V was for some units 1.45, for some 1.55v and so on
It always throttled on 1.4v

Problem,
Every sample i had so far, was overvolted by a huge margin 65-95mV too high for a V/F curve
And one of the key reasons why CO ranges even exist

If PBO actually forced or even better, bugs out
Requested VID by cores
Then it will always fall under it's threshold.
Soo the only remain throttle reason, will be package trottle and clock stretching ~ although "stretching" doesn't exist really

Dont focus too much on VID
What you see is a value from the past
It very likely can also be like a gate behaving, to fix it bellow threshold, and drop when there is load applied
Typical edc bug. Fix fit max and let it overdrive and throttle. Good old matisse days

I'm still waiting for santa to bring AGESA 1.2.0.5
But this could be a great change
Just the mindset needs to shift a bit away

The higher than 1.4VID you always saw, was nevee having any positive ground
It might have looked like more cores reach a higher strap
But they where constantly throttled into oblivion

This got made very clear to me after using two 5900X and refunded a great overvolted sample, to a really questionable bronze B2 sample. But it's not silver at least 

I finished my November project


Spoiler





















 and it arrived well as it seems
today was 4h sleep, and i should go to bed already
soo tomorrow i'll rebirth my little setup and continue with hydra a bit

Maximum effective voltage before fabric negative effects is 1413mV not 1425mV
optimally it loves 1413 strap with 1406mV TEL as boost
Anything slightly higher loses 50+ mhz or more boost. This goes away from PBO and is how AMD wants to design it

Its only unfortunate they will keep the voltage bumps for XT(reme) series
They can allow 1.65+ they can allow more than that but 🤫🤭

Anywho,
It made zero sense to waste COs ontop of 1.4v hardlock
Soo its an actually great change if this is a feature and not an leaked reviewer feature that will be "fixed" because everyone will demand higher voltage they anyways cant run
Just requested illusion 😛

I strongly hope that COs can be used for their actual benefit, and not be wasted just to find your baseline bellow 1.4v Effective

December project is now an arctic custom loop with a 5950X + 6900XTX-H
Target is to ruin some people's days on 3D mark
* of course nicely ment xD
And just again another warzone player

That might make me disappear again for a bit
But after tomorrow i should be "online" again
Good timezone for now 🥱

Oh also @Audioboxer
Please try to always swap the psu cable
I had huge problems with this bequiet sp11 , when changing powestrips, and simply cables and rails
* yes, start to dislike even more multi rail units than i've did before
Keep tripping them >.>
20A CPU is too weak when a 5900X can pull 32A
Or a 6800XT devil can pull 450W daily (24A each rail is not enough) QQ
Generally that snowflake was oversensitive to any cable change hence 12v EPS had to return

Another thing,
Only thing i'm sad about 1.2.0.5, is AMD is still underestimating us overclockers
There is more headrom in their samples than just +200Mhz fMax
*At absolute least give us -40/+40 CO ~200mV | +300Mhz*
Thats 250 Hydra ranges, at least something "reasonable"
FIT allows anyways a CPU Offset range of +200mV
*This is not unreasonable to demand and falls inside your silicon binning criteria (voltage) !*


----------



## Audioboxer

Veii said:


> Many many pages, please let me not mess up the name again
> @Audioboxer ?, i think ... 🙈
> The 1.4VID change is a good thing
> I didn't expect it, just they should've known it clearly
> 
> But here AMD goes for efficiency yes
> 1.4v VID SVI2 after dld0 , was the hardcap after when CPUs start to throttle back by FIT
> This was an unannounced range that always was applied
> It didn't matter that FIT-PRE-V was for some units 1.45, for some 1.55v and so on
> It always throttled on 1.4v
> 
> Problem,
> Every sample i had so far, was overvolted by a huge margin 65-95mV too high for a V/F curve
> And one of the key reasons why CO ranges even exist
> 
> If PBO actually forced or even better, bugs out
> Requested VID by cores
> Then it will always fall under it's threshold.
> Soo the only remain throttle reason, will be package trottle and clock stretching ~ although "stretching" doesn't exist really
> 
> Dont focus too much on VID
> What you see is a value from the past
> It very likely can also be like a gate behaving, to fix it bellow threshold, and drop when there is load applied
> Typical edc bug. Fix fit max and let it overdrive and throttle. Good old matisse days
> 
> I'm still waiting for santa to bring AGESA 1.2.0.5
> But this could be a great change
> Just the mindset needs to shift a bit away
> 
> The higher than 1.4VID you always saw, was nevee having any positive ground
> It might have looked like more cores reach a higher strap
> But they where constantly throttled into oblivion
> 
> This got made very clear to me after using two 5900X and refunded a great overvolted sample, to a really questionable bronze B2 sample. But it's not silver at least
> 
> I finished my November project
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> and it arrived well as it seems
> today was 4h sleep, and i should go to bed already
> soo tomorrow i'll rebirth my little setup and continue with hydra a bit
> 
> Maximum effective voltage before fabric negative effects is 1413mV not 1425mV
> optimally it loves 1413 strap with 1406mV TEL as boost
> Anything slightly higher loses 50+ mhz or more boost. This goes away from PBO and is how AMD wants to design it
> 
> Its only unfortunate they will keep the voltage bumps for XT(reme) series
> They can allow 1.65+ they can allow more than that but 🤫🤭
> 
> Anywho,
> It made zero sense to waste COs ontop of 1.4v hardlock
> Soo its an actually great change if this is a feature and not an leaked reviewer feature that will be "fixed" because everyone will demand higher voltage they anyways cant run
> Just requested illusion 😛
> 
> I strongly hope that COs can be used for their actual benefit, and not be wasted just to find your baseline bellow 1.4v Effective
> 
> December project is now an arctic custom loop with a 5950X + 6900XTX-H
> Target is to ruin some people's days on 3D mark
> * of course nicely ment xD
> And just again another warzone player
> 
> That might make me disappear again for a bit
> But after tomorrow i should be "online" again
> Good timezone for now 🥱
> 
> Oh also @Audioboxer
> Please try to always swap the psu cable
> I had huge problems with this bequiet sp11 , when changing powestrips, and simply cables and rails
> * yes, start to dislike even more multi rail units than i've did before
> Keep tripping them >.>
> 20A CPU is too weak when a 5900X can pull 32A
> Or a 6800XT devil can pull 450W daily (24A each rail is not enough) QQ
> Generally that snowflake was oversensitive to any cable change hence 12v EPS had to return
> 
> Another thing,
> Only thing i'm sad about 1.2.0.5, is AMD is still underestimating us overclockers
> There is more headrom in their samples than just +200Mhz fMax
> *At absolute least give us -40/+40 CO ~200mV | +300Mhz*
> Thats 250 Hydra ranges, at least something "reasonable"
> FIT allows anyways a CPU Offset range of +200mV
> *This is not unreasonable to demand and falls inside your silicon binning criteria (voltage) !*


I'm staying on AGESA 1.2.0.5 as it seems my TM5 timing out has stopped lol. Another test tonight to see if I can do a 50 run without the error on 14.

But I'm leaving CPU on AUTO, so PBO disabled. With voltages locking to 1.425v above 140 EDC I just feel like I'm unsure how I should approach 1.2.0.5. Will have to let others lead the way and I will follow. As of now my CB23 score is the 25k range and if I try to copy my AGESA 1.2.0.3 BIOS timings it doesn't quite bring it back up to over 31k. Seems everything needs a rethink on 1.2.0.5.

A higher EDC definitely helped with this 5950x on 1.2.0.3.

Who knows, I might give Hydra a go with 1.2.0.5 and see what happens!


----------



## Luggage

Veii said:


> Many many pages, please let me not mess up the name again
> @Audioboxer ?, i think ... 🙈
> The 1.4VID change is a good thing
> I didn't expect it, just they should've known it clearly
> 
> But here AMD goes for efficiency yes
> 1.4v VID SVI2 after dld0 , was the hardcap after when CPUs start to throttle back by FIT
> This was an unannounced range that always was applied
> It didn't matter that FIT-PRE-V was for some units 1.45, for some 1.55v and so on
> It always throttled on 1.4v
> 
> Problem,
> Every sample i had so far, was overvolted by a huge margin 65-95mV too high for a V/F curve
> And one of the key reasons why CO ranges even exist
> 
> If PBO actually forced or even better, bugs out
> Requested VID by cores
> Then it will always fall under it's threshold.
> Soo the only remain throttle reason, will be package trottle and clock stretching ~ although "stretching" doesn't exist really
> 
> Dont focus too much on VID
> What you see is a value from the past
> It very likely can also be like a gate behaving, to fix it bellow threshold, and drop when there is load applied
> Typical edc bug. Fix fit max and let it overdrive and throttle. Good old matisse days
> 
> I'm still waiting for santa to bring AGESA 1.2.0.5
> But this could be a great change
> Just the mindset needs to shift a bit away
> 
> The higher than 1.4VID you always saw, was nevee having any positive ground
> It might have looked like more cores reach a higher strap
> But they where constantly throttled into oblivion
> 
> This got made very clear to me after using two 5900X and refunded a great overvolted sample, to a really questionable bronze B2 sample. But it's not silver at least
> 
> I finished my November project
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> and it arrived well as it seems
> today was 4h sleep, and i should go to bed already
> soo tomorrow i'll rebirth my little setup and continue with hydra a bit
> 
> Maximum effective voltage before fabric negative effects is 1413mV not 1425mV
> optimally it loves 1413 strap with 1406mV TEL as boost
> Anything slightly higher loses 50+ mhz or more boost. This goes away from PBO and is how AMD wants to design it
> 
> Its only unfortunate they will keep the voltage bumps for XT(reme) series
> They can allow 1.65+ they can allow more than that but 🤫🤭
> 
> Anywho,
> It made zero sense to waste COs ontop of 1.4v hardlock
> Soo its an actually great change if this is a feature and not an leaked reviewer feature that will be "fixed" because everyone will demand higher voltage they anyways cant run
> Just requested illusion 😛
> 
> I strongly hope that COs can be used for their actual benefit, and not be wasted just to find your baseline bellow 1.4v Effective
> 
> December project is now an arctic custom loop with a 5950X + 6900XTX-H
> Target is to ruin some people's days on 3D mark
> * of course nicely ment xD
> And just again another warzone player
> 
> That might make me disappear again for a bit
> But after tomorrow i should be "online" again
> Good timezone for now 🥱
> 
> Oh also @Audioboxer
> Please try to always swap the psu cable
> I had huge problems with this bequiet sp11 , when changing powestrips, and simply cables and rails
> * yes, start to dislike even more multi rail units than i've did before
> Keep tripping them >.>
> 20A CPU is too weak when a 5900X can pull 32A
> Or a 6800XT devil can pull 450W daily (24A each rail is not enough) QQ
> Generally that snowflake was oversensitive to any cable change hence 12v EPS had to return
> 
> Another thing,
> Only thing i'm sad about 1.2.0.5, is AMD is still underestimating us overclockers
> There is more headrom in their samples than just +200Mhz fMax
> *At absolute least give us -40/+40 CO ~200mV | +300Mhz*
> Thats 250 Hydra ranges, at least something "reasonable"
> FIT allows anyways a CPU Offset range of +200mV
> *This is not unreasonable to demand and falls inside your silicon binning criteria (voltage) !*


But =<140 EDC -> 1.5VID, only >140 EDC -> 1.425VID. This feels… not right.
Especially after all the talk about auto vcore up to 1.5 being “as intended” by AMD.

or are you saying the ppt/cca- limit here is really vcore/vid-limit?



http://imgur.com/sOEc6G0


----------



## PJVol

Luggage said:


> or are you saying the ppt/cca- limit here is really vcore/vid-limit?


These are mislabled entries, so don't rely on them. For monitoring use xpeHope3's(lol) tool insead.


----------



## Luggage

PJVol said:


> These are mislabled entries, so don't rely on them. For monitoring use xpeHope3's(lol) tool insead.


Old screenshot from old discussion before “other”  tool, not at computer for a few days.


----------



## cirov

Would you be able to tell me if I've gotten the most out of my setup for daily use? Would tweaking it further only yield marginal gains?
Also that motherboard really hates 4x8. Only thing im thinking of doing at this point is lowering VDIMM from 1.53v a little bit.


----------



## 67091

mongoled said:


> Look at my signature, that's affirmative 😃


Ok Well, I was wondering if you could help me then. What do I need to change to get GDM off? I can't do anything higher than 3600 memory or IF, that's the best the CPU can do.
I have passed TM5 Extreme / Ram Test 1.1.0.0 and a default run of Prime95 for 21 hours on multiple bios updates so I know my machine is stable. Every time a bios is available to update I will run the test again just to be sure my PC is rock solid. Both kits of ram are 100% B-Die I brought them years ago, the model is G.Skill F4-3200C14-8GTZR Single rank with heatsinks off and will have a fan facing the ram if I want to run a memory test.
Thanks for your time


----------



## ManniX-ITA

angushades said:


> Ok Well, I was wondering if you could help me then. What do I need to change to get GDM off? I can't do anything higher than 3600 memory or IF, that's the best the CPU can do.


It can happen but it's unlikely a 5800X can't do more than IF 1800.
I'd start adjusting voltages.
VDDP is likely not helping at 1050. Try with 900-950 mV.
Set CCD lower than IOD, between 950 and 1000 mV. If it works at 950 mV is probably better.
Raise VSOC so that it reads a bit higher than 1.1V in Zentimings, between 1.125V and 1.15V.

For the memory timings there are a lot of people here with 4xSR than can help you, I don't know much.


----------



## Audioboxer

Audioboxer said:


> View attachment 2536042
> 
> 
> Good news, TM5 going through a 50 cycle on AGESA 1.2.0.5 without timing out.
> 
> Bad news, an error
> 
> View attachment 2536043
> 
> 
> @Veii What is your opinion on a single 14? Try increasing CmdDrvStr to 24? Odt to 30?
> 
> It could also be added that me running the v3.11.17.521 chipset drivers shows they are being tested behind the scenes for AGESA 1.2.0.5 (as in timeouts could have been related to chipset drivers running on 1.2.0.3). That and it might simply be the case all the changes AMD has made with 1.2.0.5 is also going to throw off some old memory OC profiles.
> 
> Never ran the above on a 50 cycle before (just anta777 for longer runs), but it's been put through plenty of 25 cycles prior till now.












CkeDrvStr changed to 30, SCLs changed to 4 (dom reported better benches with them at 4, I'm now going to test that). If I bench better with 2 will try another 50 run tonight. 50 cycle is my new friend, goodbye 25 cycle 

Only other change between the two runs is... the power supply, but I doubt that caused an error 14


----------



## mongoled

angushades said:


> Ok Well, I was wondering if you could help me then. What do I need to change to get GDM off? I can't do anything higher than 3600 memory or IF, that's the best the CPU can do.
> I have passed TM5 Extreme / Ram Test 1.1.0.0 and a default run of Prime95 for 21 hours on multiple bios updates so I know my machine is stable. Every time a bios is available to update I will run the test again just to be sure my PC is rock solid. Both kits of ram are 100% B-Die I brought them years ago, the model is G.Skill F4-3200C14-8GTZR Single rank with heatsinks off and will have a fan facing the ram if I want to run a memory test.
> Thanks for your time
> 
> View attachment 2536202


Hi!

Cmd2t: 2T
vSOC: 1.125v
vDDP: 0.860v
vDDG CCD: 1.000v
vDDG IOD: 1.040v
ProcODT: 28.2 ohms
RttNom: RZQ/6 (40ohms)
RttWr: RZQ/3 (80 ohms)
RttPark: RZQ/3 (80 ohms)

See if that allows you to post or not ...

If it does not change only vDDP to 0.900v


----------



## mongoled

Audioboxer said:


> View attachment 2536232
> 
> 
> CkeDrvStr changed to 30, SCLs changed to 4 (dom reported better benches with them at 4, I'm now going to test that). If I bench better with 2 will try another 50 run tonight. 50 cycle is my new friend, goodbye 25 cycle
> 
> Only other change between the two runs is... the power supply, but I doubt that caused an error 14


You know the drill, needs to pass over consecutive reboots


----------



## Audioboxer

mongoled said:


> You know the drill, needs to pass over consecutive reboots


Well, it's going again tonight for me to check SCL 2 🤞

Then comes trying Karhu on AGESA 1.2.0.5 to see if the random error 8~11 hours in is gone. It's 2/2 for TM5 not timing out whereas on AGESA 1.2.0.3 it was like 9/9 for it timing out.


----------



## mongoled

Audioboxer said:


> Well, it's going again tonight for me to check SCL 2 🤞
> 
> Then comes trying Karhu on AGESA 1.2.0.5 to see if the random error 8~11 hours in is gone. It's 2/2 for TM5 not timing out whereas on AGESA 1.2.0.3 it was like 9/9 for it timing out.


Looks like I'm going back to the last BIOS to support 500mhz boost overide frequency. Thankfully it also has resizable bar enabled as it's build around agesa 1.1.9.0.

Just doing a round of benchmarks comparing it to newer bios and so far it's better in both single/multicore benchmarks once tweaked correctly in comparison to agesa 1.2.0.x


----------



## Audioboxer

mongoled said:


> Looks like I'm going back to the last BIOS to support 500mhz boost overide frequency. Thankfully it also has resizable bar enabled as it's build around agesa 1.1.9.0.
> 
> Just doing a round of benchmarks comparing it to newer bios and so far it's better in both single/multicore benchmarks once tweaked correctly in comparison to agesa 1.2.0.x


Yeah all my CPU scores are down with AGESA 1.2.0.5 and if I copy my 1.2.0.3 curve, PBO and telemetry I can't get above 31k in CB23 whereas I managed it before. Not only that I have no idea if the voltage reading at 1.425v max when EDC is above 140 is correct or not. My CB23 scores are around 30,500~30,800, so PBO _is_ working but I'm not sure if that extra push to get over 31k is not happening due to voltage restrictions.

One thing that definitely is visible is with AutoOC, the CPU struggles to hit 5150mhz, capping at about 5050mhz. With PBO disabled, I can see 5050mhz hit. This suggests the 1.425v cap is real with PBO on/EDC above 140 which is stopping the micro-bursts to 5150mhz being obtainable. They no doubt need the full 1.5v.

AutoOC +100mhz hit 5150mhz easily on 1.2.0.3 for me. I'd suspect ST performance is therefore going to be lower on 1.2.0.5.


----------



## mongoled

Audioboxer said:


> Yeah all my CPU scores are down with AGESA 1.2.0.5 and if I copy my 1.2.0.3 curve, PBO and telemetry I can't get above 31k in CB23 whereas I managed it before. Not only that I have no idea if the voltage reading at 1.425v max when EDC is above 140 is correct or not. My CB23 scores are around 30,500~30,800, so PBO _is_ working but I'm not sure if that extra push to get over 31k is not happening due to voltage restrictions.
> 
> One thing that definitely is visible is with AutoOC, the CPU struggles to hit 5150mhz, capping at about 5050mhz. With PBO disabled, I can see 5050mhz hit. This suggests the 1.425v cap is real with PBO on/EDC above 140 which is stopping the micro-bursts to 5150mhz being obtainable. They no doubt need the full 1.5v.
> 
> AutoOC +100mhz hit 5150mhz easily on 1.2.0.3 for me. I'd suspect ST performance is therefore going to be lower on 1.2.0.5.


Yes this looks to be the way they are going on newer BIOS, to be honest with you the only reason I keep moving to a newer bios is in the hope that they will fix the fclk "issue"

Seeing that's never going to happen pretty much pointless using the newer bios seeing they seem primarily aimed at increasing stability rather than increasing performance.

On my lowly 5600x, at least on agesa 1.1.9.0 I can get all cores to boost to 5Ghz even with max cpu voltage restricted to 1.45v, if this artificial limit wasn't present I'm sure that the good cores could hold 5.1Ghz.

Moving to anything higher that restricts cpu boost overide frequency is pointless from a performance POV


----------



## Audioboxer

mongoled said:


> Yes this looks to be the way they are going on newer BIOS, to be honest with you the only reason I keep moving to a newer bios is in the hope that they will fix the fclk "issue"
> 
> Seeing that's never going to happen pretty much pointless using the newer bios seeing they seem primarily aimed at increasing stability rather than increasing performance.
> 
> On my lowly 5600x, at least on agesa 1.1.9.0 I can get all cores to boost to 5Ghz even with max cpu voltage restricted to 1.45v, if this artificial limit wasn't present I'm sure that the good cores could hold 5.1Ghz.
> 
> Moving to anything higher that restricts cpu boost overide frequency is pointless from a performance POV


I do have to add that with 1.2.0.5 my mouse issues are fixed with FCLK above 1900, so there is progress there for me. I can still produce USB disconnects though with y-cruncher test 17. I had these mouse issues on 1.2.0.3 even with the CPU set to AUTO. Seeing as with AUTO on 1.2.0.5 the voltage still goes up to 1.5v, I can't say it's a reduction in max voltage which has fixed the mouse issues. It has to be something else which has changed.

But the whole thing is a bit of a mess, if AMD wanted a 1.425v cap, why is it only introduced when EDC goes above 140? On Auto or PBO with EDC <=140 you can still see voltage go up to 1.5v. Effectively what this BIOS does right now is simply punish OCers with no real consistency. Which makes me think it's a bug. Maybe their new CPUs are going to have a lower voltage limit and as of now this beta BIOS doesn't have that properly implemented and it's conflicting with current CPUs?

Either you have a 1.425v cap or you don't. No point only bringing it in if the end user decides to go to 141+ EDC.


----------



## Veii

mongoled said:


> Thankfully it also has resizable bar enabled as it's build around agesa 1.1.9.0.


Don't let yourself being marketing fooled
BAR mode & negative CO, exists since 1.1.0.0A
SMU 56.30 ~ maybe one of both even at 56.26
Marketing department will force you to update to 1.1.0.0C which had an ABL 1900 FCLK Lock
"Just so people can utilize BAR mode or negative CO"
Nonsense, lies and nonsense 

Sadly i can't seem to find the post anymore from AMDRyzen Twitter
Only the 1.1.0.0D patch "with a new CO feature" is here, but maybe it remained into some more people's mind


Luggage said:


> But =<140 EDC -> 1.5VID, only >140 EDC -> 1.425VID. This feels… not right
> 
> 
> Audioboxer said:
> 
> 
> 
> Either you have a 1.425v cap or you don't. No point only bringing it in if the end user decides to go to 141+ EDC.
Click to expand...

Yes it indeed is odd

But 1.4v limit existed since the launch day
Just it wasn't made obvious at all
I don't think 1425 is correct.
This is what hydra says, but this is already a voltage where you start to lose perf
(Likely not good copy of homework)
1413 or 1406mV was the peak
Eh let's say <1400 , as LLC droop exists

Please test how L3 scales
EDC limiter was well used on Matisse exactly to limit supplied voltage without ways going down on the freq strap
But on Vermeer, limiting EDC also limited L3 cache
Soo zero first stage throttlers, let the real voltage through, which you could limit then correctly with CO

Else , it was load dependent, if COs are actually correct,
Hence limited EDC will let the cpu take less voltage on high load
But then COs wont be correct for other applications

I'll check likely end of December, if Santa ASRock releases it till then
They need longer to verify it being _"as rock stable_" as possible 🤭
And if it fails verification, they won't release it at all without saying anything
Likely to not gain into marketing fire. Been doing half good half unliked things for AMD
Slowly balancing their AMD reputation I guess 
* i wish them be slightly more rebel again, but that's me


----------



## sonixmon

Audioboxer said:


> 2 PSUs, different brands, exactly the same? There's gotta be another variable here. Whether it's the motherboard, GPU or maybe my power source which I am going to check shortly. Would also suggest Corsair are cheating if they don't report the 12V voltage dip below 12v.


Curious if you have done any actual voltage testing with a meter (carefully of course). 

Any crashes with the new PSU? I am no expert but I would think a slow dip with load might be ok up to a point, but quick fluctuations would cause the crashes. I had an old PSU that always read proper voltages but I was having random crash (black screen reboots). After testing everything I could, I broke down and got a new PSU. Voltages appeared almost the same under load but issues it stopped crashing.

You using a UPS on your PC? You can monitor your incoming voltages that way. I would think a good PSU would handle small voltage changes ok, I always use a UPS on my gaming rig, modem etc. I've lost power and finished a round in game before. 



ManniX-ITA said:


> A bad DP cable can do unspeakable things, like blowing off the GPU and/or mainboard
> 
> More inclined to think it's the GPU or something else... What about the mainboard 12V sensor? Does it read like iCUE?


I had a DP cable causing my RGB to stay lit when powering of PC (coincidently after replacing my PSU). PSU tech support asked me to disconnect DP cable, I did and lights went out. Ordered a certified DP cable and was shocked when it actually fixed the issue. Cheap DP cables in fact can do strange things and I imagine cause damage.


----------



## Audioboxer

sonixmon said:


> Curious if you have done any actual voltage testing with a meter (carefully of course).
> 
> Any crashes with the new PSU? I am no expert but I would think a slow dip with load might be ok up to a point, but quick fluctuations would cause the crashes. I had an old PSU that always read proper voltages but I was having random crash (black screen reboots). After testing everything I could, I broke down and got a new PSU. Voltages appeared almost the same under load but issues it stopped crashing.
> 
> You using a UPS on your PC? You can monitor your incoming voltages that way. I would think a good PSU would handle small voltage changes ok, I always use a UPS on my gaming rig, modem etc. I've lost power and finished a round in game before.
> 
> 
> I had a DP cable causing my RGB to stay lit when powering of PC (coincidently after replacing my PSU). PSU tech support asked me to disconnect DP cable, I did and lights went out. Ordered a certified DP cable and was shocked when it actually fixed the issue. Cheap DP cables in fact can do strange things and I imagine cause damage.


Nah, just relied on software readings. One of the things I was interested about with this Corsair PSU is the hookup to my commander pro so that it shows voltages and other info in iCUE. But they just seem to read direct from the PSU. The issue here is the voltage being read at the GPU input end.

No crashes or issues. My crashes seem to have been fixed by lowering my core clock. Even on the Thor PSU this seemed to fix the kernel-power 41 reboots. But given I wasn't 100% convinced lowering core clock had simply fixed it all I still wanted another PSU. This one appears to dip even more than the Thor!

But no crashes. I left a SP game on for 5 hours in a row today on a busy screen just to keep the GPU holding a high boost/utilisation. No crash when I came back. Did some testing in 3DMark yesterday as well, no crashes.

As this 2080Ti is an RMA I think I'll just chalk it up to being a poor performer and where I have OCed it to is as good as it gets. Once I get a 3080 I'll be able to more seriously look at voltage.


----------



## Veii

Soo Mindfactory (DE) continues to refuse working with ASUS
And @Alphacool refuses working with ASRock for their blocks
(Which at this point is just refusing sells by personal moral decision)

This brand "hate" makes me unhappy and unfortunately restrictive
Having to go out of my way to get ASUS boards , just so i can bughunt new AGESAs
And having to go out of my way, to deliver blocks from the other side of the world, just to cool a liked and actually great product

Resolve for both is sticking to MSI for leaked bioses and going DIY instead of sticking to alphacool
But this shouldn't be the resolve 😓


----------



## ManniX-ITA

sonixmon said:


> Any crashes with the new PSU? I am no expert but I would think a slow dip with load might be ok up to a point, but quick fluctuations would cause the crashes. I had an old PSU that always read proper voltages but I was having random crash (black screen reboots). After testing everything I could, I broke down and got a new PSU. Voltages appeared almost the same under load but issues it stopped crashing.


The major issue is usually transients; what you see as a power usage is always an average.

When the voltage readings are fine but the PSU fails under load is usually due to the OCP protection, the Over Current Protection.
For a brief moment there was a spike and the PSU couldn't hold it.

When the voltage readings are low on top you can have the UVP, the Under Voltage Protection, kicking in as well.
During the spike the voltage drops below 11.4V and the PSU will trip.

You need an oscilloscope to see that, a DMM is not enough.
The 2000 and 3000 series nVidia GPUs they suck an impressive amount of power to minimize micro stuttering when boosting.

Igor's Lab did the effort measure the transients with the 3090:










It's the reason why lately all the PSUs have extremely generous OCP tripping points.
Which is bad when the PSU is cheap as it ends up in flames like the Gigabyte unit tested by GN.

If you want to OC a big CPU and an nVidia GPU in the 3080/3090 class it's highly recommended to have at least 1000W of nominal wattage.


----------



## Blameless

Audioboxer said:


> if AMD wanted a 1.425v cap, why is it only introduced when EDC goes above 140?


Because voltage in isolation is mostly irrelevant. Capping EDC will allow higher peak voltages with the same reliability/longevity.

It does punish OCers, but may preserve AMD's bottom line by reducing the number of returns.


----------



## Audioboxer

Blameless said:


> Because voltage in isolation is mostly irrelevant. Capping EDC will allow higher peak voltages with the same reliability/longevity.
> 
> It does punish OCers, but may preserve AMD's bottom line by reducing the number of returns.


140 is incredibly low though, I was able to get good scaling in performance right up to 220. If high voltage is basically only used for micro-boosts then all AMD are doing is hurting potential ST performance just because you happen to have EDC above 140.

Doesn't really make any sense. There must be a more intelligent way to handle multicore voltage limits that aren't as clumsy as an outright hardcap depending on the EDC value.

As much as I want to say I'll trust the engineers, if midcycle you suddenly decide to take performance away from people who've been running settings for years that is NOT going to go down well. A completely new product introducing a new voltage limit is different from retroactively changing things on prior released hardware.


----------



## Imprezzion

ManniX-ITA said:


> The major issue is usually transients; what you see as a power usage is always an average.
> 
> When the voltage readings are fine but the PSU fails under load is usually due to the OCP protection, the Over Current Protection.
> For a brief moment there was a spike and the PSU couldn't hold it.
> 
> When the voltage readings are low on top you can have the UVP, the Under Voltage Protection, kicking in as well.
> During the spike the voltage drops below 11.4V and the PSU will trip.
> 
> You need an oscilloscope to see that, a DMM is not enough.
> The 2000 and 3000 series nVidia GPUs they suck an impressive amount of power to minimize micro stuttering when boosting.
> 
> Igor's Lab did the effort measure the transients with the 3090:
> 
> View attachment 2536271
> 
> 
> It's the reason why lately all the PSUs have extremely generous OCP tripping points.
> Which is bad when the PSU is cheap as it ends up in flames like the Gigabyte unit tested by GN.
> 
> If you want to OC a big CPU and an nVidia GPU in the 3080/3090 class it's highly recommended to have at least 1000W of nominal wattage.


Yeah well. My Focus + Gold 750w could not handle a 2080 Ti + 9900KS with a hard OC on both. Transients were way out of spec and it randomly tripped OCP in games / benchmarks.

Swapped it for a Prime Ultra Gold 1000w and that had no issues. It also runs my current 5900X + 3080 + full custom loop + 14 RGB fans and such just fine. No issues. Barely even has the fan spinning in Hybrid mode. And no OCP trips. I do wonder what would happen if I shunt the 3080 lol.. currently it has a 370w limit so..

Btw, my board, the ASUS B550-XE, will not POST at all with any bclk that isn't 100.00.. it just hangs on either "07" or a random different POST code.. weird..


----------



## Audioboxer

Imprezzion said:


> Yeah well. My Focus + Gold 750w could not handle a 2080 Ti + 9900KS with a hard OC on both. Transients were way out of spec and it randomly tripped OCP in games / benchmarks.
> 
> Swapped it for a Prime Ultra Gold 1000w and that had no issues. It also runs my current 5900X + 3080 + full custom loop + 14 RGB fans and such just fine. No issues. Barely even has the fan spinning in Hybrid mode. And no OCP trips. I do wonder what would happen if I shunt the 3080 lol.. currently it has a 370w limit so..
> 
> Btw, my board, the ASUS B550-XE, will not POST at all with any bclk that isn't 100.00.. it just hangs on either "07" or a random different POST code.. weird..


If you can play New World with a heavy OC you're all good. Yes, New World managed to trip OCP for me on a 850w a couple of times. That reminds me, should try it now on 1000w.

Stopped playing it because it was crap but an OCP test will be a good idea!

As of now I was playing Outer Wilds and that managed to pull a full 380w through my 2080Ti just to run at 144FPS  PSU in was like 550w and this is WITHOUT PBO.


----------



## Luggage

Blameless said:


> Because voltage in isolation is mostly irrelevant. Capping EDC will allow higher peak voltages with the same reliability/longevity.
> 
> It does punish OCers, but may preserve AMD's bottom line by reducing the number of returns.


But high EDC is beneficial for heavy multi core loads then voltage is far lower than 1.4, not light single core loads with high voltage. (Except for the L3 mega high edc behavior)

Even on 1203 (and before) it’s a stupid balancing there I get better single core performance by lowering limits from stock and better multi core performance by raising them.

Edit:
Well there are the strange all core light thermal load, high voltage high boost loads like mem testing - but are they a problem?



http://imgur.com/5fB2AGC

EDC 168


----------



## Worldwin

Got CR1 to Post. This is extremely unstable I.E BSOD at idle. Anyone got ideas for what changes i should try.


----------



## Audioboxer

Worldwin said:


> View attachment 2536352
> 
> Got CR1 to Post. This is extremely unstable I.E BSOD at idle. Anyone got ideas for what changes i should try.


Try using a CmdSetup time of 55 or 56. Some DR memory can do 1T without setup times but most will struggle unless you have a perfect combo of ram, mobo and your CPU IMC.

Remove that CkeSetup 5 when trying this.


----------



## Worldwin

Audioboxer said:


> Try using a CmdSetup time of 55 or 56. Some DR memory can do 1T without setup times but most will struggle unless you have a perfect combo of ram, mobo and your CPU IMC.
> 
> Remove that CkeSetup 5 when trying this.


Tried 55 and its got errors. 56 is more promising as its drastically reduced. Should I just try going up on CMDSetup until it either caps or stops erroring.


----------



## Audioboxer

Worldwin said:


> Tried 55 and its got errors. 56 is more promising as its drastically reduced. Should I just try going up on CMDSetup until it either caps or stops erroring.


No, change ClkDrvStr to 40. 40/20/24/24 is a good shout for the DrvStrs.


----------



## Audioboxer

Audioboxer said:


> View attachment 2536232
> 
> 
> CkeDrvStr changed to 30, SCLs changed to 4 (dom reported better benches with them at 4, I'm now going to test that). If I bench better with 2 will try another 50 run tonight. 50 cycle is my new friend, goodbye 25 cycle
> 
> Only other change between the two runs is... the power supply, but I doubt that caused an error 14












Alright, memory is all good again.

When I was getting TM5 timeouts and Karhu errors on 1.2.0.3c with AMD Chipset drivers 3.11.17.251 I had already tried SCLs at 4, including changing primaries and other secondaries. So it seems to me like AGESA 1.2.0.5 along with the latest chipset drivers being beta tested might cause memory profile problems. Especially if you run the newest chipset drivers on an older AGESA. Seeing as both MSI and ASUS have posted chipset drivers AMD still haven't officially released it must be a lot of beta testing for the new 3D cache chips. Wouldn't surprise me if the TM5 timeouts were caused by CPU boosting scheduler conflicts because a newer chipset driver expected AGESA 1.2.0.5 behaviour. AMD have clearly made a lot of changes between AGESA 1.2.0.3 and 1.2.0.5.

Ymmv. It seems though the one change I have needed to make on AGESA 1.2.0.5 is CkeDrvStr to 30. That cleared up the TM5 power down error.


----------



## ManniX-ITA

Audioboxer said:


> When I was getting TM5 timeouts and Karhu errors on 1.2.0.3c with AMD Chipset drivers 3.11.17.251 I had already tried SCLs at 4, including changing primaries and other secondaries. So it seems to me like AGESA 1.2.0.5 along with the latest chipset drivers being beta tested might cause memory profile problems. Especially if you run the newest chipset drivers on an older AGESA. Seeing as both MSI and ASUS have posted chipset drivers AMD still haven't officially released it must be a lot of beta testing for the new 3D cache chips. Wouldn't surprise me if the TM5 timeouts were caused by CPU boosting scheduler conflicts because a newer chipset driver expected AGESA 1.2.0.5 behaviour. AMD have clearly made a lot of changes between AGESA 1.2.0.3 and 1.2.0.5.


I have reverted yesterday to v3.10 after a sudden reboot in idle.
Got a lot of weird issues with v3.11 including games crashing and eating 80GB of memory till system became unresponsive.
So far so good but still too early to be sure.


----------



## Audioboxer

ManniX-ITA said:


> I have reverted yesterday to v3.10 after a sudden reboot in idle.
> Got a lot of weird issues with v3.11 including games crashing and eating 80GB of memory till system became unresponsive.
> So far so good but still too early to be sure.


Are you on AGESA 1.2.0.5? But yeah my general advice now is watch out when running 3.11.


----------



## ManniX-ITA

Audioboxer said:


> Are you on AGESA 1.2.0.5? But yeah my general advice now is watch out when running 3.11.


Nope, still on 1.2.0.1 AGESA.


----------



## Audioboxer

ManniX-ITA said:


> Nope, still on 1.2.0.1 AGESA.


Yeah, I think it's quite clear 3.11 is going to cause major issues on anything but 1.2.0.5.


----------



## mongoled

Audioboxer said:


> Yeah, I think it's quite clear 3.11 is going to cause major issues on anything but 1.2.0.5.


You become quite an authorative figure on the matter


----------



## Audioboxer

mongoled said:


> You become quite an authorative figure on the matter


I mean, if anyone else wants to do testing that would be cool! Just reporting my experiences. To go from running 8 or 9 TM5 runs in a row and have them ALL timeout, to running back to back 50 cycles with no timeouts is pretty conclusive. Same timings, no PBO, only change is going from 1.2.0.3c to 1.2.0.5. Not to mention to go from Karhu errors on multiple runs to seemingly it being OK as well now.

Veii pointed out something has changed with boosting on 1.2.0.5 so it's my speculating that with only ASUS releasing 3.11, and that being on their forum (not even mobo support pages), it's quite likely 3.11 is being tested in unison with the newest AGESA. Maybe for preparation of the 3D cache chips.


----------



## ManniX-ITA

Audioboxer said:


> to running back to back 50 cycles


Ehm, you'll probably keep the honor of testing for us all


----------



## mongoled

Audioboxer said:


> I mean, if anyone else wants to do testing that would be cool! Just reporting my experiences. To go from running 8 or 9 TM5 runs in a row and have them ALL timeout, to running back to back 50 cycles with no timeouts is pretty conclusive. Same timings, no PBO, only change is going from 1.2.0.3c to 1.2.0.5. Not to mention to go from Karhu errors on multiple runs to seemingly it being OK as well now.
> 
> Veii pointed out something has changed with boosting on 1.2.0.5 so it's my speculating that with only ASUS releasing 3.11, and that being on their forum (not even mobo support pages), it's quite likely 3.11 is being tested in unison with the newest AGESA. Maybe for preparation of the 3D cache chips.


Just messing with you, though as with all things it needs to be reproduced by others to be able to make an "authorative statement"

😋


----------



## Audioboxer

ManniX-ITA said:


> Ehm, you'll probably keep the honor of testing for us all


A 7-9 cycle of Anta777 still takes longer than a 1usmus v3 50 cycle lol. Is 5 hours 20 minutes really seen as _too long_? lol



mongoled said:


> Just messing with you, though as with all things it needs to reproduced by others to be able to make an "authorative statement"
> 
> 😋


Well, I'm more than happy for others to test! I don't mean for any of my statements to sound authoritative, just put them out there in case it helps anyone else


----------



## ManniX-ITA

Audioboxer said:


> A 7-9 cycle of Anta777 still takes longer than a 1usmus v3 50 cycle lol. Is 5 hours 20 minutes really seen as _too long_? lol


I think it's the 50 
Kidding, I've a shortcut for a 100 cycles but I did run it only twice so far to be honest!


----------



## Audioboxer

ManniX-ITA said:


> I think it's the 50
> Kidding, I've a shortcut for a 100 cycles but I did run it only twice so far to be honest!


I'm happy keeping things to a 25 for when you're changing a lot, but a 50 right at the end seems OK to do if you just run it overnight. Given Karhu keeps running until you stop it I've let it go from early evening to morning a few times.

I think it's probably normal to be a bit more paranoid about memory errors  I dunno when that error 14 popped up for me, could have been at like cycle 44 or something lol.


----------



## sonixmon

So I just got the tPHYRDL mismatch on a Zentimings Check. Not sure why this happened all of a sudden. I did tweak a few voltages before a Hydra run. Ignore the missing values sometimes Zentimings is glitchy switching back and forth between modules and I didnt catch it before saving. All other values did match.


















Also got some crazy Aida Cachemem scores, I assume these can't be right?? The first one was in OS with apps and services running, then the second after closing apps and running script to stop services (lower ns and lower R/W but crazy copy speed?).



















Prior scores:


----------



## Audioboxer

sonixmon said:


> So I just got the tPHYRDL mismatch on a Zentimings Check. Not sure why this happened all of a sudden. I did tweak a few voltages before a Hydra run. Ignore the missing values sometimes Zentimings is glitchy switching back and forth between modules and I didnt catch it before saving. All other values did match.
> 
> View attachment 2536431
> View attachment 2536432
> 
> 
> 
> Also got some crazy Aida Cachemem scores, I assume these can't be right?? The first one was in OS with apps and services running, then the second after closing apps and running script to stop services (lower ns and lower R/W but crazy copy speed?).
> 
> 
> View attachment 2536433
> View attachment 2536434
> 
> 
> 
> Prior scores:
> View attachment 2536435


Hydra screws up read write and memory figures. Also I'd say the mismatch could be your Rtts. Try a 7/3/3 instead. ProcODT try 34.3 or even 36.9.


----------



## sonixmon

Audioboxer said:


> Hydra screws up read write and memory figures. Also I'd say the mismatch could be your Rtts. Try a 7/3/3 instead. ProcODT try 34.3 or even 36.9.


Ok I will try those later today, been using the same settings for a while but I know voltages also have an impact on them.


----------



## Audioboxer

sonixmon said:


> Ok I will try those later today, been using the same settings for a while but I know voltages also have an impact on them.


Yeah it's often voltage but I have noticed myself a few times when slipping to 28/30 instead of 28/28 it can be a timing or resistance.


----------



## cirov

Do you guys think tRCDRD is a stick or a controller limitation?


----------



## Veii

cirov said:


> Do you guys think tRCDRD is a stick or a controller limitation?
> View attachment 2536484


Close to zero to do with the CPU
Has to do with powering, DIMM PCB, DIMM IC, DIMM Input-Voltage, Good signal integrity (good psu & low voltages), low procODT


----------



## cirov

Could be because the second daisy chain channel is really weak on this motherboard.


----------



## Worldwin

Going for CR1 and have ADDRCMDSetup @ 60. Unfortunately there is an error on test 0.
Any suggestions?
Edit: Ima try 40/20/24/24 as Audio suggested 1st.


----------



## Audioboxer

Worldwin said:


> View attachment 2536546
> 
> 
> Going for CR1 and have ADDRCMDSetup @ 60. Unfortunately there is an error on test 0.
> Any suggestions?
> Edit: Ima try 40/20/24/24 as Audio suggested 1st.


55 or 56 and try with ClkDrvStr at 40. 40 seems to be a sweet spot for most DR when it comes to trying to get 1T running at 3800. You're close.



Veii said:


> Close to zero to do with the CPU
> Has to do with powering, DIMM PCB, DIMM IC, DIMM Input-Voltage, Good signal integrity (good psu & low voltages), low procODT


You're teasing me again that I should have another go at tRCDRD 13 at 3800 👀 👀


----------



## Veii

Audioboxer said:


> You're teasing me again that I should have another go at tRCDRD 13 at 3800 👀 👀


Idk, you got good dimms
I can not relate
Just barely get 3600 C14-14 stable
It still is slightly faster than 3800 C15-15 but it's unfortunate 
If you can do 13-13 then go for it, maybe even lose 33-67mhz if needed, but beyond 100 , the frequency and fabric clock bump overexceeds the lower timings
It looks slower on memtests, but the FCLk internal is still giving a tiny bit of boost compared to lower FCLK

Interestinly, same things that fail beyond tRCDRD 14
easily run tCWL 10 . . . at the same voltage
Idk what to say. Just PCB things


----------



## Audioboxer

Veii said:


> Idk, you got good dimms
> I can not relate
> Just barely get 3600 C14-14 stable
> It still is slightly faster than 3800 C15-15 but it's unfortunate
> If you can do 13-13 then go for it, maybe even lose 33-67mhz if needed, but beyond 100 , the frequency and fabric clock bump overexceeds the lower timings
> It looks slower on memtests, but the FCLk internal is still giving a tiny bit of boost compared to lower FCLK
> 
> Interestinly, same things that fail beyond tRCDRD 14
> easily run tCWL 10 . . . at the same voltage
> Idk what to say. Just PCB things


Wish I could give you these dims for a spin lol.

My challenge with tRCDRD 13 at 3800 is it seems as if giving more VIDMM helps. But I'm up around 1.61v~1.65v and I think I'm beginning to struggle to stabilise the PCB at a high voltage.

I've noticed so far that errors on 6 happen quickly if ProcODT is too low. Errors on 2/12 can happen around the 1 minute mark if I can avoid 6s. About 3 minutes without an error is as long as I've gone, but then I was surprised with a 1/13. But I did drop ClkDrvStr to 30 on this attempt.

I'm try to rule out fighting with the PCB at voltage around 1.65v, but I'm a bit inexperienced with trying to run b-die at such a high voltage. Yourself and mongoled seem to have a bit of experience doing so.










Excuse the somewhat zombie profile based on my stable, but here is an example of managing to avoid an early 6/2/12 and instead getting a dump of 1's. A 1 is not something I'm very familiar with. My issue is when I fiddle with ClkDrvStr it seems to cause all hell to break loose lol.


----------



## Bix

PJVol said:


> So in the end, did i get it right that adjusting PLL to 1.77 got you back the consistent results in a GEMM tests, basically with no significant regression?


You were right that adjusting PLL probably wouldn't help... reducing it let me pass the GEMMS test without nuking the IF and produced relatively consistent results but it turns out also reduces performance with a lot of other workloads, including the miner. 

Is it possible that lowering PLL might just be masking a wider issue with my voltages by throttling just enough to keep the test stable?🙃


----------



## Frosted racquet

Hey guys, need a bit of input on impulsive purchasing decisions. Currently have some Hynix CJR DR RAM that's giving me trouble with XMP and tuned timings (look at my previous post for more info and my losing battle). 5600x with MSI B550I ITX.

1. Planning on purchasing F4-3200C14D-32GTZ(KW) for ~230 euro as a replacement for F4-3600C16D-32GVKC mentioned above, it's the only B-die that I can find in my region. Is it realistic to expect 3600Mb/s with straight 15 timings for ex. from that B-die kit?

2. The PC mentioned is currently back in my house where there's no heating over the winter since I'm in my apartment in the city. I'm keeping it on due to mining on the side, and can test via TeamViewer how 10 degree ambient temps affect my 5600x OC and as most of you have noticed the 65 degree "limit" for boost affects the performance a little on the 5600x. Currently have Mugen 5 and plan to get Liquid Freezer II 240 just to get a bit more out of that darn boost algorithm and maybe try out a allcore OC with fixed voltage as a backup profile. Is it worth it in your opinion? Over the summer the ambient temps can go up to 30+ degrees, limiting the boost even further.

Thanksfor your input.


----------



## Luggage

Frosted racquet said:


> Hey guys, need a bit of input on impulsive purchasing decisions. Currently have some Hynix CJR DR RAM that's giving me trouble with XMP and tuned timings (look at my previous post for more info and my losing battle). 5600x with MSI B550I ITX.
> 
> 1. Planning on purchasing F4-3200C14D-32GTZ(KW) for ~230 euro as a replacement for F4-3600C16D-32GVKC mentioned above, it's the only B-die that I can find in my region. Is it realistic to expect 3600Mb/s with straight 15 timings for ex. from that B-die kit?
> 
> 2. The PC mentioned is currently back in my house where there's no heating over the winter since I'm in my apartment in the city. I'm keeping it on due to mining on the side, and can test via TeamViewer how 10 degree ambient temps affect my 5600x OC and as most of you have noticed the 65 degree "limit" for boost affects the performance a little on the 5600x. Currently have Mugen 5 and plan to get Liquid Freezer II 240 just to get a bit more out of that darn boost algorithm and maybe try out a allcore OC with fixed voltage as a backup profile. Is it worth it in your opinion? Over the summer the ambient temps can go up to 30+ degrees, limiting the boost even further.
> 
> Thanksfor your input.


1. 3600cl16 is realistic at least. Cl 15 means gdm disabled and that means tuning ram for real…
2. Don’t ask me what’s worth it - I put a 1260mm rad on my balcony for thermals on a 5800x


----------



## sonixmon

Audioboxer said:


> Hydra screws up read write and memory figures. Also I'd say the mismatch could be your Rtts. Try a 7/3/3 instead. ProcODT try 34.3 or even 36.9.


Ok I will chaulk up the mem figures to Hydra.

Tried 7/3/3 and ProcODT 34.3 and that seemed to do it so far! Thanks, will have to do my in depth testing just not sure how I am going to handle it because I still have a temp issue even with Ram fan which helps but doesnt resolve. No RAM water cooling for me so will see what happens but gaming etc. is fine and stays under 42c. Currently 47 is my failure point and only stress tests ever get it over 42c.

















I haven't tried 3866 or 4000 on new Bios but others still reported WHEA though I think someone gained 66mhz if I remember. I might play with those this weekend for fun.


----------



## 67091

mongoled said:


> Hi!
> 
> Cmd2t: 2T
> vSOC: 1.125v
> vDDP: 0.860v
> vDDG CCD: 1.000v
> vDDG IOD: 1.040v
> ProcODT: 28.2 ohms
> RttNom: RZQ/6 (40ohms)
> RttWr: RZQ/3 (80 ohms)
> RttPark: RZQ/3 (80 ohms)
> 
> See if that allows you to post or not ...
> 
> If it does not change only vDDP to 0.900v


Hey mate posted and it's running fine but if I have to change it to 2T what would be the point of having GDM off. ?


----------



## Worldwin

Audioboxer said:


> 55 or 56 and try with ClkDrvStr at 40. 40 seems to be a sweet spot for most DR when it comes to trying to get 1T running at 3800. You're close.


Tried both 56/60 @ 40/20/24/24 and they both got errors. 56 errors on test 6 and 60 on test 12. Ima try with 60setup and 40/20/20/20

Edit: It appears 40 did the trick.


----------



## PJVol

Bix said:


> You were right that adjusting PLL probably wouldn't help... reducing it let me pass the GEMMS test without nuking the IF and produced relatively consistent results but it turns out also reduces performance with a lot of other workloads, including the miner.
> 
> Is it possible that lowering PLL might just be masking a wider issue with my voltages by throttling just enough to keep the test stable?🙃


Yep. I see something similar with a too low 1.8. I even found reproducible scenario, where running Cinebench R20 multicore hwinfo shows both max and effective clocks, let's say 4750 mhz allcore, that should correspond ~ 4780pts, but actual result is ~ 4450-4500.
I suspect higher than 1900 fclk somehow broke DFS (PLL based) functioning. I just don't get, how it could stretch duty cycle by 7-8% throughout the whole run without at least higher VID requested?
Anyway, I found this perf. drop can only be observed in AVX/FMA workloads, i.e. standard CPU-z benchmark is not affected.


----------



## Audioboxer

Just having a wee bit of fun. Going to see how low tRFC can go with a 1.75v budget. There seems to be scope to get flat 12 running around 1.7v, but where is the fun in that? Trying to get tRFC as close to under 100ns is where it is at 

And yes as I've said previously around 9GB is really as high as I can allow memory to be to stop the PCB crashing with high voltages.

Will supply some benches shortly for fun as well, one with 1CCD disabled.


----------



## Veii

Audioboxer said:


> And yes as I've said previously around 9GB is really as high as I can allow memory to be to stop the PCB crashing with high voltages.


Congrats, hey the good thing is
You can slowly extend and allow 1024 more and more, to finetune RTTs and CKE
This is valuable progress

But around 1.72v, the ICs start to fail ~ not the PCB
Maybe you can get it on slightly lower VDIMM and then extend the size


----------



## Audioboxer

Veii said:


> Congrats, hey the good thing is
> You can slowly extend and allow 1024 more and more, to finetune RTTs and CKE
> This is valuable progress
> 
> But around 1.72v, the ICs start to fail ~ not the PCB
> Maybe you can get it on slightly lower VDIMM and then extend the size


This is why I love you Veii, full of knowledge! I'd never have known that about 1.72v.










But it has been fun trying to push tRFC below 100 lol. Going on Antas use multiples of 16 I think this is probably the lowest I'm going to get it. I guess place your bets if I can pass at tRFC 178 

Around 9GB seems to be where I tested to before, but this might have been higher than 1.72v. I can try again. It seemed not bad to me considering most who use maxmem seem to go down to 2~3GB.

Edit - 178 can't even boot at 1.75v, so the above is as low as it can go using multiples of 16.


----------



## Veii

Audioboxer said:


> But it has been fun trying to push tRFC below 100 lol. Going on Antas use multiples of 16 I think this is probably the lowest I'm going to get it. I guess place your bets if I can pass at tRFC 178


Try multiple's of 9 & use v2.32 ~ the one towards roudup calculation for tRFC2/4
My dimm PCBs failed at 1.69 (samsung) & 1.72v (Rev.E)
But the samsung ICs do fail near that 1.72v range (+/- 15-20mv) , hence you have to use maxmem
~ architectural issue of 20nm B-Die


----------



## Bix

PJVol said:


> Yep. I see something similar with a too low 1.8. I even found reproducible scenario, where running Cinebench R20 multicore hwinfo shows both max and effective clocks, let's say 4750 mhz allcore, that should correspond ~ 4780pts, but actual result is ~ 4450-4500.
> I suspect higher than 1900 fclk somehow broke DFS (PLL based) functioning. I just don't get, how it could stretch duty cycle by 7-8% throughout the whole run without at least higher VID requested?
> Anyway, I found this perf. drop can only be observed in AVX/FMA workloads, i.e. standard CPU-z benchmark is not affected.


Thanks for confirming - having another go at tweaking voltages today. The boot to boot variance with AVX/FMA performance is such a pain... any change needs at least 9 runs of Sandra get useful results (3 - reboot - 3 - reboot - 3) so this will definitely take a while. Something seems to be training differently each time but it's not noticeable with other workloads so far as I can tell. Will keep an eye on HWInfo clock/score relationship in case of weirdness. 

I hope I'm not wasting my time here but since so many other workloads seem to be scaling well up to 2000 FCLK I still think it can be performative if I can just sort out this instability with AVX/FMA.


----------



## Audioboxer

Veii said:


> Try multiple's of 9 & use v2.32 ~ the one towards roudup calculation for tRFC2/4
> My dimm PCBs failed at 1.69 (samsung) & 1.72v (Rev.E)
> But the samsung ICs do fail near that 1.72v range (+/- 15-20mv) , hence you have to use maxmem
> ~ architectural issue of 20nm B-Die












Yeah around 9GB is clearly my limit, maybe even just a bit under 9GB. You can see here with 10GB just how quick everything falls apart.

tCL12 is pretty ridiculous anyway, just something to have fun with with maxmem. What intrigues me more is why tRCDRD 13 struggles at 3800. IIRC if I use maxmem at 1.55v it ends up passing fine. It's when full memory is used tRCDRD 13 begins having problems. Makes you think it's not VDIMM, is it just part of the DIMMs can't handle 13 at 3800?


----------



## Luggage

Audioboxer said:


> View attachment 2536702
> 
> 
> Yeah around 9GB is clearly my limit, maybe even just a bit under 9GB. You can see here with 10GB just how quick everything falls apart.
> 
> tCL12 is pretty ridiculous anyway, just something to have fun with with maxmem. What intrigues me more is why tRCDRD 13 struggles at 3800. IIRC if I use maxmem at 1.55v it ends up passing fine. It's when full memory is used tRCDRD 13 begins having problems. Makes you think it's not VDIMM, is it just part of the DIMMs can't handle 13 at 3800?


Wasn’t this the reasoning around the theoretical binning difference between the gvka3600-141414 (that I still run) and the gvk4000-141515(or was it 141414) you changed to?


----------



## Veii

Audioboxer said:


> It's when full memory is used tRCDRD 13 begins having problems. Makes you think it's not VDIMM, is it just part of the DIMMs can't handle 13 at 3800?


Low tRCD requires clean signal integrity
If it is the IC's then you can scale down to 3600 13-13 and it wouldn't run with full capacity
Or even 12-12 , if we calculate transfer time from virtual to realtime value
* the IC's would continue to fail at this transfer time

If they fail on higher freq, with the same transition-time "value", then it's rather the PCB and the "worse getting" signal integrity
Same for me with 3600 14-14
15-15 is fine, but 3800 15-15 is just tiny bit faster, but requires more tRRD_ ~ soo it wasn't worth it
14-14 is perfectly fine, but then dimm PCB fails at 1.58+ volts. A signal integrity thing

Now the guy who got the PC, used powerstrips and power extensions ~ although with a warning not to do it (as the PSU is oversensitive)
And he has #6 & #12's , while it was rock stable here

It's a signal integrity thing,
I'd suggest to try and use maxmem, to learn what RTTs correspond better
High VDIMM doesn't mean bad signal integrity, when procODT is low for example and PARK is low
Experiment with RTT_WR 2 for such








Such things

EDIT:
tRCD 13 @ 3335 = 7.79689683505965ns
tRCD 14 @ 3600 = 7.77777777777778ns
tRCD 15 @ 3800 = 7.89473684210526ns
it can do 15-15 (7.895ns) easily, and it could do 13-13 (7.797ns)
But on 7.78ns (7.778ns) ~ little steps higher , it started to fail
The difference is too small ~ soo it clearly is the PCB & soo signal integrity thing, and not the IC's


----------



## Audioboxer

Luggage said:


> Wasn’t this the reasoning around the theoretical binning difference between the gvka3600-141414 (that I still run) and the gvk4000-141515(or was it 141414) you changed to?


My 3600 14-14-14-14 set couldn't run tRCDRD 14 at 3800. Now my knowledge back then wasn't quite as good as it is now, but I wasn't doing anything crazy, I simply couldn't get tRCDRD 14 to pass a stability test even at 2T and very loose timings.

Seems I just got a stinking kit. One with basically no headroom. Given what I paid for the 3600 kit there was no way I was accepting that lol. The 4000 kit didn't cost too much more.



Veii said:


> Low tRCD requires clean signal integrity
> If it is the IC's then you can scale down to 3600 13-13 and it wouldn't run with full capacity
> Or even 12-12 , if we calculate transfer time from virtual to realtime value
> * the IC's would continue to fail at this transfer time
> 
> If they fail on higher freq, with the same transition-time "value", then it's rather the PCB and the "worse getting" signal integrity
> Same for me with 3600 14-14
> 15-15 is fine, but 3800 15-15 is just tiny bit faster, but requires more tRRD_ ~ soo it wasn't worth it
> 14-14 is perfectly fine, but then dimm PCB fails at 1.58+ volts. A signal integrity thing
> 
> Now the guy who got the PC, used powerstrips and power extensions ~ although with a warning not to do it (as the PSU is oversensitive)
> And he has #6 & #12's , while it was rock stable here
> 
> It's a signal integrity thing,
> I'd suggest to try and use maxmem, to learn what RTTs correspond better
> High VDIMM doesn't mean bad signal integrity, when procODT is low for example and PARK is low
> Experiment with RTT_WR 2 for such
> 
> 
> 
> 
> 
> 
> 
> 
> Such things
> 
> EDIT:
> tRCD 13 @ 3335 = 7.79689683505965ns
> tRCD 14 @ 3600 = 7.77777777777778ns
> tRCD 15 @ 3800 = 7.89473684210526ns
> it can do 15-15 (7.895ns) easily, and it could do 13-13 (7.797ns)
> But on 7.78ns (7.778ns) it started to fail
> The difference is too small ~ soo it clearly is the PCB , and not the IC's


Very interesting post and it offers some optimism too. I'm current experimenting with maxmem, voltage and tRCDRD 13. What I've noticed so far is even just going to 1.6v in combination with trying to run a higher memory amount causes issues.

For example, 11GB at 1.6v had errors within a few minutes. 11GB at 1.56v (I meant to do 1.55v but forgot MSI add 0.01v) is currently working its way through a 25 cycle.

I'm of the belief tRCDRD can run at 13 around 1.55v but it's the amount of memory I'm using which brings up an issue. From what you said if true that would appear to be ICs. Next step then testing at a lower frequency but full mem capacity.


----------



## Audioboxer

Around 9GB seems to be my answer for everything right now 

tRCDRD 13 was struggling at 11GB, got some errors late on. Back down to 9GB and away she goes.

@Veii would you look at 3600 tRCDRD 13 at 32GB first or would you edge up with maxmem as far as it goes then try playing with other timings/resistances/settings?


----------



## nada324

Hey guys, do you know any combination of cmd setup with clkdrvstr for SR (2x8)?
I have been trying to get TRCD to 15 down from 16 but i cant seem to get it, poor mobo
I get error 10 at first cicle, in the tm5 error it says that i have to increase RTT NOM to something stronger, does it mean from RTT 6 to 7 (weaker)? or stronger like RTT 6 to 4?

Thank you


----------



## nick name

nada324 said:


> Hey guys, do you know any combination of cmd setup with clkdrvstr for SR (2x8)?
> I have been trying to get TRCD to 15 down from 16 but i cant seem to get it, poor mobo
> I get error 10 at first cicle, in the tm5 error it says that i have to increase RTT NOM to something stronger, does it mean from RTT 6 to 7 (weaker)? or stronger like RTT 6 to 4?
> 
> Thank you


----------



## Veii

Audioboxer said:


> Around 9GB seems to be my answer for everything right now


9GB is soo fast 


nada324 said:


> Hey guys, do you know any combination of cmd setup with clkdrvstr for SR (2x8)?


3-3-15 for 3800MT/s , tCKE 9
4-4-18 for 4000MT/s , tCKE 11
=//= 4200MT/s, tCKE 13


----------



## Luggage

PJVol said:


> These are mislabled entries, so don't rely on them. For monitoring use xpeHope3's(lol) tool insead.


ok now I have 1203c ss to compare


http://imgur.com/a/Z2UdUWH




http://imgur.com/a/YrkeTCn


Going to give 1205 another try…


----------



## Audioboxer

Veii said:


> 9GB is soo fast
> 
> 3-3-15 for 3800MT/s , tCKE 9
> 4-4-18 for 4000MT/s , tCKE 11
> =//= 4200MT/s, tCKE 13


Let me introduce you to 3GB


----------



## Veii

Audioboxer said:


> Let me introduce you to 3GB
> 
> View attachment 2536737


Might want to spend the time getting tRCDRD+tRTP = tRAS , to run


----------



## Audioboxer

Veii said:


> Might want to spend the time getting tRCDRD+tRTP = tRAS , to run


Yeah, would do if I thought I could actually get tRCDRD 13 in with a shout. Testing just under 10GB at the moment. I'm trying to find close enough to my absolute maxmem limit.

25/37 would be absolutely fine. I've ran 24/36 before with no issues. I've had some issues dropping down to tRAS 22 before so don't go there now.

The formula you posted is what I tend to stick to.


----------



## Luggage

Audioboxer said:


> Yeah, would do if I thought I could actually get tRCDRD 13 in with a shout. Testing just under 10GB at the moment. I'm trying to find close enough to my absolute maxmem limit.
> 
> 25/37 would be absolutely fine. I've ran 24/36 before with no issues. I've had some issues dropping down to tRAS 22 before so don't go there now.
> 
> The formula you posted is what I tend to stick to.


How’s 16gb? That way you can compare to 2x8 and have only wasted half your kit


----------



## nada324

Veii said:


> 9GB is soo fast
> 
> 3-3-15 for 3800MT/s , tCKE 9
> 4-4-18 for 4000MT/s , tCKE 11
> =//= 4200MT/s, tCKE 13


Can i use those with any drvSTR or there is recommended one?


----------



## Audioboxer

Luggage said:


> How’s 16gb? That way you can compare to 2x8 and have only wasted half your kit


Struggle to get above 11GB without errors, whether it's running like 1.75v, or whether it's trying to get tRCDRD 13 stable at 3800 (no maxmem).

It's kind of funny both scenarios display nearly the exact same behaviour. Whether it's flat 12 at 1.75v at 3800 or it's flat 13 at 1.55v at 3800.

I'm trying to figure out if it's the same problem in both situations, PCB or IC/signal integrity issue. I would have thought tRCDRD 13 at 1.55v wouldn't be down to voltage, so it's likely this is something to do with signal integrity. I'm just not sure. As I joked with Veii, wish I could give him my kit and let a pro figure it all out 

Understanding the limitations and why is more interesting at the moment than running benches. I mean, getting to tRCDRD 13 instead of 14 at 3800 will do hardly anything. tCL12 is obviously never a daily, that's purely a bit of fun and to see where b-die could end up if it could handle such high voltages.

Speaking of SR, I have seen it handle tRCDRD 13 at 3800 full capacity, as in tCL/tRCDRD 13. I haven't seen anyone manage it with DR yet without using maxmem. Most extreme OCers tend to go for SR for obvious reasons. Plus the top end DR bins are just stupid expensive, especially in comparison to 2x8GB. Though it has to be said it is impressive G.SKILL have managed to bin DR to where they have.

But G.SKILL, please stop using RipJaws heatsinks. It is kind of embarrassing wanting a no-RGB option for expensive memory and getting this crap that doesn't even properly cover the memory


----------



## Veii

nada324 said:


> Can i use those with any drvSTR or there is recommended one?


You need x-20-20-20 CAD_BUS with these
X can be everything
Just check Zen RamOC Leaderboards
Still a valid place to find settings


----------



## Veii

Audioboxer said:


> As I joked with Veii, wish I could give him my kit and let a pro figure it all out


UK is not thaat far away 
But i don't know if my tiny ITX, will translate to your 2 DPC board
i recommend to also take a look at tCWL 10 
don't forget your fomula's tho, -2 tCWL = +2 tRDWR


----------



## Audioboxer

Veii said:


> UK is not thaat far away
> But i don't know if my tiny ITX, will translate to your 2 DPC board
> i recommend to also take a look at tCWL 10
> don't forget your fomula's tho, -2 tCWL = +2 tRDWR












I genuinely didn't think that would go any lower than 12! But it has and it booted. From 12 to 10, and tRDWR from 9 to 11. Something else to stability test and then bench!


----------



## domdtxdissar

Audioboxer said:


> View attachment 2536746
> 
> 
> I genuinely didn't think that would go any lower than 12! But it has and it booted. From 12 to 10, and tRDWR from 9 to 11. Something else to stability test and then bench!


Hmm do i need to stop my ram testing and also try this tCWL10 ? 
@ 7 hours and 30min running atm.. Lets us know if it work out for you 😇











Veii said:


> UK is not thaat far away
> But i don't know if my tiny ITX, will translate to your 2 DPC board


I'm running same settings as *Audioboxer *with my 4 DPC asus hero viii rev1 board.. Should be no problem with your ITX then


----------



## Veii

domdtxdissar said:


> Hmm do i need to stop my ram testing and also try this tCWL10 ?


idk what's up with it, but it "just run" 
not in clear if this is beneficial for bandwidth - but questionable DR dimm PCB , just accepted it
SR doesn't want to


----------



## nada324

Veii said:


> You need x-20-20-20 CAD_BUS with these
> X can be everything
> Just check Zen RamOC Leaderboards
> Still a valid place to find settings


Something is really wrong here, tested 30-20-20-20 same and 60-20-20-20 is a no go


----------



## Audioboxer

domdtxdissar said:


> Hmm do i need to stop my ram testing and also try this tCWL10 ?
> @ 7 hours and 30min running atm.. Lets us know if it work out for you 😇
> View attachment 2536750
> 
> 
> 
> I'm running same settings as *Audioboxer *with my 4 DPC asus hero viii rev1 board.. Should be no problem with your ITX then


Was wondering where my RAM buddy was, nothing separating us! (other than a few timings lol).

I always thought tRDWR going higher would impact performance more than tCWL dropping down but it's something we can test! 

10/10 doesn't post for me btw, so it seems we're sticking close to the formula of -2/+2.


----------



## nick name

nada324 said:


> Something is really wrong here, tested 30-20-20-20 same and 60-20-20-20 is a no go
> 
> View attachment 2536754


Have you tried leaving the DrvStr at Auto? Also, if you're gonna try 1T with GDM Disabled you should try AddrCmdSetup 56 and leave the others Auto. I'd also try a little more DDR voltage.


----------



## Veii

nada324 said:


> Something is really wrong here, tested 30-20-20-20 same and 60-20-20-20 is a no go
> 
> View attachment 2536754


RTT_PARK is too strong for SR 
up to /5 or higher
















In 13's case, decrease procODT, that's too much


----------



## nada324

Veii said:


> RTT_PARK is too strong for SR
> up to /5 or higher
> View attachment 2536768
> 
> View attachment 2536769
> 
> In 13's case, decrease procODT, that's too much


So i did lowered Vdimm and proc odt and almost all gone , but still error #11, maybe have to deal with clkdrvstr:











@nick name still dont know how to use multi quote, but that didnt work, it made it worse


----------



## PJVol

nada324 said:


> Something is really wrong


Yeah, its strange, that it even booted with the RDWR 8.


----------



## TeslaHUN

TeslaHUN said:


> For example this 3600 / C16 -19-19-39 kit has reasonable price in Hungary .But no idea if its SR or D


I bought the kit , I just came back to inform you it ; is dual rank ,and some kind of Hynix chip.


----------



## Akex

Veii said:


> You need x-20-20-20 CAD_BUS with these
> X can be everything
> Just check Zen RamOC Leaderboards
> Still a valid place to find settings


Sorry for asking the question, but how does the person who is ranked first deserve the place of first? I mean by that it uses maxmem 360 Mega only ... it's unfair to everyone else in the list even though it might just be a reference database .. The ranking needs to be without WHEA ... then why validated the maxmem ??


----------



## PJVol

Akex said:


> it's unfair to everyone


Oh... don't mind, it's not uncommon for the reddit community
But using 2.2G of system memory for benchmarking sure looks cheaty.
You may ask the doc owner directly btw, just talked to him recently.

Although i see no reasonable grounds under "no-whea" compliance either, since its RAM OC and stability dedicated rankings.



Bix said:


> The boot to boot variance with AVX/FMA performance is such a pain...


 Yeah, but you may try my way of preliminary checking with the AIDA photoworxx test, comparing it to a highest result at a certain fclk - this saves a lot of time. If result decreased by more than 500 of whatever, just rebot immediately.


----------



## domdtxdissar

_double post_


----------



## domdtxdissar

Audioboxer said:


> Was wondering where my RAM buddy was, nothing separating us! (other than a few timings lol).
> 
> I always thought tRDWR going higher would impact performance more than tCWL dropping down but it's something we can test!
> 
> 10/10 doesn't post for me btw, so it seems we're sticking close to the formula of -2/+2.


Not much to tweak nowadays, mostly feel like im "done" with my setup 😋
Have just been posting in the benchmark part of the forum lately 😇

Have a x570s Unify x max on backorder, but i don't think much will change until i get my hands on a "6950x v-$"


----------



## domdtxdissar

So i got intrigued by the tCWL10 and decided to test some different memory settings to see what really performed best in different memory benchmarks, little did i know how much time this would really take 😅

These are the settings i decided to have a showdown between:










A few words before we get into the data 

All benchmarks were run with a static OC @ a lowish 4600/4500mhz, so everyone with a 5950x should be able to compare numbers if they want
After each benchmark computer was restarted, and after each restart the computer was left idling for 1min so windows could start all processes in peace
Benchmarks was performed on a newly installed GHOSTSPECTRE SUPERLIGHT Win10 OS. (around 94 processes running after 1 min idling)
Difficulty for the Menero Miner XMR-stak-rx was "480045" for all runs
I have screenshots for every benchmark if requested



Spoiler: Benchmarks



start

*Benchmate wPrime 1.5.0.5*

Baseline:

Run1 = 34.700 sec
Run2 = 34.622 sec
Run3 = 34.761 sec
Average = 34.694 sec

Baseline -SCL2:

Run1 = 34.672 sec
Run2 = 34.677 sec
Run3 = 34.702 sec
Average = 34.683 sec

-2tCWL +2tRDWR:

Run1 = 34.773 sec
Run2 = 34.698 sec
Run3 = 34.767 sec
Average = 34.732 sec

-2tCWL +2tRDWR -2SCL:

Run1 = 34.763 sec
Run2 = 34.819 sec
Run3 = 34.686 sec
Average = 34.756 sec

Correct tRAS:

Run1 = 34.709 sec
Run2 = 34.773 sec
Run3 = 34.693 sec
Average = 34.725 sec

Flat tCL14 :

Run1 = 34.799 sec
Run2 = 34.834 sec
Run3 = 34.713 sec
Average = 34.782 sec

*Corona 1.3 Benchmark:*

Baseline:

Run1 = 11.812.500 Reys/sec
Run2 = 11.822.300 Reys/sec
Run3 = 11.853.700 Reys/sec
Average = 11.829.500 Reys/sec

Baseline -SCL2:

Run1 = 11.748.000 Reys/sec
Run2 = 11.749.700 Reys/sec
Run3 = 11.836.600 Reys/sec
Average = 11.778.100 Reys/sec

-2tCWL +2tRDWR:

Run1 = 11.735.800 Reys/sec
Run2 = 11.772.700 Reys/sec
Run3 = 11.767.900 Reys/sec
Average = 11.758.800 Reys/sec

-2tCWL +2tRDWR -2SCL:

Run1 = 11.783.300 Reys/sec
Run2 = 11.778.700 Reys/sec
Run3 = 11.786.400 Reys/sec
Average = 11.782.800 Reys/sec

Correct tRAS:

Run1 = 11.804.200 Reys/sec
Run2 = 11.813.100 Reys/sec
Run3 = 11.818.200 Reys/sec
Average = 11.811.833 Reys/sec

Flat tCL14:

Run1 = 11.786.700 Reys/sec
Run2 = 11.793.000 Reys/sec
Run3 = 11.792.200 Reys/sec
Average = 11.790.633 Reys/sec

*Linpack Xtreme 1.1.5*

Baseline:

Run1 = 673.6121 GFlops
Run2 = 672.5934 GFlops
Run3 = 672.7430 GFlops
Average = 672.9828 GFlops

Baseline -SCL2:

Run1 = 671.7620 GFlops
Run2 = 671.3653 GFlops
Run3 = 670.6409 GFlops
Average = 671.2561 GFlops

-2tCWL +2tRDWR:

Run1 = 672.5900 GFlops
Run2 = 672.1730 GFlops
Run3 = 672.1913 GFlops
Average = 672.3181 GFlops

-2tCWL +2tRDWR -2SCL:

Run1 = 670.3983 GFlops
Run2 = 669.1971 GFlops
Run3 = 669.5059 GFlops
Average = 669.7004 GFlops

Correct tRAS:

Run1 = 671.6125 GFlops
Run2 = 671.0436 GFlops
Run3 = 670.6122 GFlops
Average = 671.6122 GFlops

Flat tCL14:

Run1 = 668.8344 GFlops
Run2 = 668.2137 GFlops
Run3 = 668.1432 GFlops
Average = 668.3971 GFlops

*IntelBurnTest v2.54: Very high stresslevel*

Baseline:

Run1 = 234.9265 GFlops
Run2 = 235.5467 GFlops
Run3 = 235.8574 GFlops
Average = 235.4435 GFlops

Baseline -SCL2:

Run1 = 235.5185 GFlops
Run2 = 235.6311 GFlops
Run3 = 234.5461 GFlops
Average = 235.2319 GFlops

-2tCWL +2tRDWR:

Run1 = 234.5213 GFlops
Run2 = 234.4156 GFlops
Run3 = 234.4483 GFlops
Average = 234.4617 GFlops

-2tCWL +2tRDWR -2SCL:

Run1 = 234.0640 GFlops
Run2 = 234.2016 GFlops
Run3 = 235.6987 GFlops
Average = 234.6547 GFlops

Correct tRAS:

Run1 = 234.9590 GFlops
Run2 = 234.8467 GFlops
Run3 = 237.0151 GFlops <-- outliner
Average = 235.6069 GFlops

Flat tCL14:

Run1 = 233.8859 GFlops
Run2 = 234.8498 GFlops
Run3 = 235.7551 GFlops
Average = 234.8302 GFlops

*Menero Miner XMR-stak-rx *

Baseline:

Average after 15min = 19709.4 H/s
Highest = 19728.5 H/s

Baseline -SCL2:

Average after 15min = 19625.1 H/s
Highest = 19641.9 H/s

-2tCWL +2tRDWR:

Average after 15min = 19605.5 H/s
Highest = 19621.7 H/s

-2tCWL +2tRDWR -2SCL:

Average after 15min = 19655.7 H/s
Highest = 19677.9 H/s

Correct tRAS:

Average after 15min = 19571.3 H/s
Highest = 19585.1 H/s

Flat tCL14:

Average after 15min = 19509.0 H/s
Highest = 19521.3 H/s







End comments:

Like previously found, my "baseline" seems to be the fastest profile overall, for my system atleast.
SCL2 almost always seems to lower the performance on my 2x16GB dualrank setup. (in aida64 you see higher write but lower read)
tCWL10 didn't seem to make up from the performance loss from being forced to run tRDWR11 instead of 9. (or the bios is actually not running tCWL10 like it says it is)
"Flat tCL14" seems to be the slowest profile.
The Menero Miner seemingly really likes low tRAS+tRC, even when its below the "calculated minimum".
As with pretty much all "memory benchmarks", CPU clockspeed is king... Don't spend your power budget on SOC if that mean lower cpu boosting.


----------



## Veii

Akex said:


> Sorry for asking the question, but how does the person who is ranked first deserve the place of first? I mean by that it uses maxmem 360 Mega only ... it's unfair to everyone else in the list even though it might just be a reference database .. The ranking needs to be without WHEA ... then why validated the maxmem ??


He fights hard for the first place on everything, by any means possible
Let him stay, it's just ridiculous funny, what you need to come close to the result
Technically the fault, is the reddit google docs maker, not the score setter
20min is just not enough for TM5, 45min minimum to reach thermal equilibrium - likely 50ish

Don't mind, it's not impossible to get it back
But he slowly should've reached maximum peak voltage possible
Curious to see how far the person wants to go , maybe loosing a dimm even
EDIT:
Just need to finally get 2133 stable, and he would lose the chance permanently


----------



## Akex

Veii said:


> He fights hard for the first place on everything, by any means possible
> Let him stay, it's just ridiculous funny, what you need to come close to the result
> Technically the fault, is the reddit google docs maker, not the score setter
> 20min is just not enough for TM5, 45min minimum to reach thermal equilibrium - likely 50ish
> 
> Don't mind, it's not impossible to get it back
> But he slowly should've reached maximum peak voltage possible
> Curious to see how far the person wants to go , maybe loosing a dimm even
> EDIT:
> Just need to finally get 2133 stable, and he would lose the chance permanently


I admit wanting to see this, if it's possible without too much trouble for you


----------



## Veii

Akex said:


> I admit wanting to see this, if it's possible without too much trouble for you


Idk how long it has been
I think 2100 took 4 months at least, over 2067
but since the "last" result is 7 months ago (time fly's) 2100 probably got stabilized 9 months ago
yea that makes sense , as i got the chip in early november & around december 2067 was fine

2133 15.15 mem, i got stable, barely but it worked
2133 fabric technically can be called stable ~ in the autocorrection world
But signal integrity got just horrible when going back on 1:1 mode
soo i think i'm for 4-5 months already on it.

It can happen, my dimms are just weak
It doesn't need over 1.25v SOC
And VDDG IOD runs it at 1160, it should be all fine. VDD18 is also "just" at 1.93 ~ seen B2 like VDD18 at 1.96 for 1800 FCLK (bad DR dimms)

There's room left, just didn't have the patience or reason so far
These A0's are pretty maxed out already 
Got send two dimm sets to play with but both had burn marks on the PCB - soo where not really usable, neither 4400 ones neither 4267 DR one

EDIT:
Tempted to take a shoot on these
TeamGroup T-Create Expert OC10L 3600,CL14-15-15-35 (TTCED416G3600HC14CDC01)
The OC 10 layer lineup
But so far there wasn't really a reason to get them

still lacking a GPU to finish the 2nd build for recordings and stuff
Soo no real reason to invest 1//3rd of the budget into another ram kit


----------



## mongoled

Maxmem results are just wrong to be used on the 'Leaderboard'.

I never realised that was taking place and was in total admiration of the efforts taken to achieve that result, now the admiration has turned to anger.

I hope the author of the sheet removes them.

It really is a slap in the face for those who spend so many hours to post stable config with all mem used then someone to come along and poop all over that just to get '1st place'

🙄


----------



## Blameless

domdtxdissar said:


> The Menero Miner seemingly really likes low tRAS+tRC, even when its below the "calculated minimum".


The minimum useful tRAS for reads is at least as low as tRCDRD+BL (burst length) and may even be tRAS=tRCDRD. Writes take longer, and I've seen credible info that states tRCDWR+tWCL+tWR+BL as the minimum actual here. However tRAS is a flexible window so having it lower than the theoretical minimum time it takes for a full write access doesn't hurt.

With most memory, I just run the absolute lowest tRC and tRP I can make fully stable, then calculate tRAS(=tRC-tRP) from that. Only a few denser ICs types have a problem with this, in my experience.


----------



## Mach3.2

mongoled said:


> Maxmem results are just wrong to be used on the 'Leaderboard'.
> 
> I never realised that was taking place and was in total admiration of the efforts taken to achieve that result, now the admiration has turned to anger.
> 
> I hope the author of the sheet removes them.
> 
> It really is a slap in the face for those who spend so many hours to post stable config with all mem used then someone to come along and poop all over that just to get '1st place'
> 
> 🙄


Flip side of the coin is, no where on the sheet it says 24/7 config, so I guess it's fair game although I don't like the fact that he maxmem'd his way up there lol.


----------



## Audioboxer

mongoled said:


> Maxmem results are just wrong to be used on the 'Leaderboard'.
> 
> I never realised that was taking place and was in total admiration of the efforts taken to achieve that result, now the admiration has turned to anger.
> 
> I hope the author of the sheet removes them.
> 
> It really is a slap in the face for those who spend so many hours to post stable config with all mem used then someone to come along and poop all over that just to get '1st place'
> 
> 🙄


Gotta agree, I mean, you guys have seen the crazy timings I can run even up to 9GB using maxmem. Straight up flat 12 at 3800. On a single CCD processor that is one heck of score pusher.

Without maxmem I can't even get tRCDRD 13 stable at 3800.


----------



## mongoled

Mach3.2 said:


> Flip side of the coin is, no where on the sheet it says 24/7 config, so I guess it's fair game although I don't like the fact that he maxmem'd his way up there lol.


Does not have to be anything to do with 24/7 config, though your point is valid.

Why not use just 1 x 8GB stick or even 1 x 4GB stick, then that way its clear what the result is.

By using Maxmem you are simply circumventing the specs you have published.


----------



## PJVol

Veii said:


> He fights hard for the first place on everything, by any means possible


Hi! Not directly related to him, but it reminds me one person on a local foruum. He's posted several times AIDA cachemem screens of 5600X with a couple of s-ranks, running something like 3800-3933 cl15 with a latency of *48-48.5*ns. 
Idk how to take it. Personally, based on what i've seen so far it seems impossible for me to do it in a fair manner, but don't really know of the way to figure out without having direct access to hw.


----------



## Audioboxer

PJVol said:


> Hi! Not directly related to him, but it reminds me one person on a local foruum. He's posted several times AIDA cachemem screens of 5600X with a couple of s-ranks, running something like 3800-3933 cl15 with a latency of *48-48.5*ns.
> Idk how to take it. Personally, based on what i've seen so far it seems impossible for me to do it in a fair manner, but don't really know of the way to figure out without having direct access to hw.


I've never really been into competitive benching, chasing the thrill of an OC is fun, but I've never really fell down the hole of competitive score pushing. I guess I prefer watching others go to crazy lengths to do it whilst just being happy if I can learn to push more out of my own hardware. I even said earlier in this topic its passing stability tests that does it for me more than scores 😂

So I understand competitive benching doesn't mean daily stable. Usually if something is seriously unstable that also either hurts your scores or you can't even run bench tests without crashing. But maxmem is like cheating your way with your hardware. You get unrealistic stability whilst still retaining the benefits of B-die.

Those benefits of B-die are supposed to be balanced with its weaknesses one of which seems to be the PCB/IC struggle with higher voltages. More so than some other memory. 

Seems to me if you're going to use maxmem it should be on its own leaderboard. But the world of competitive overclocking has soo much drama this isn't a callout post lol. Just 2 cents from an outsider recently playing with maxmem!


----------



## PJVol

@Audioboxer yeah, I see your point, and nothing wrong with it as well (for science lol)
Just curious of some use cases where you can't be 100% sure (rather 99%) that someone is cheating, and assuring you that all is fair .
And basically i wanna hear your opinion guys here, in regards to if anyone think it's possible to get to the 48-ish ns with a 3800 cl 15 or 4000 cl 15 in a fair way. Just it.


----------



## Imprezzion

PJVol said:


> @Audioboxer yeah, I see your point, and nothing wrong with it as well (for science lol)
> Just curious of some use cases where you can't be 100% sure (rather 99%) that someone is cheating, and assuring you that all is fair .
> And basically i wanna hear your opinion guys here, in regards to if anyone think it's possible to get to the 48-ish ns with a 3800 cl 15 or 4000 cl 15 in a fair way. Just it.


Best I can get my DR's to do at 3800C15 is around 53.7ns. Barebones bench Windows, CPU on bench clocks.. and that sure ain't actually stable lol.


----------



## Luggage

Luggage said:


> ok now I have 1203c ss to compare
> 
> 
> http://imgur.com/a/Z2UdUWH
> 
> 
> 
> 
> http://imgur.com/a/YrkeTCn
> 
> 
> Going to give 1205 another try…


So thanks to @Eder posting unlocked 1205 bios MSI MEG X570 Unify Overclocking & Discussion Thread 

@Veii @domdtxdissar @mongoled @Audioboxer @ManniX-ITA @PJVol 

1.5V VID is back on the menu boys

First I tried with EDC at 140A for base line... then I kept upping it and VID did not get locked at 1.425 over 140A any more



http://imgur.com/a/daq6KEY


I guess it's time to re-tune CO and everything again.


----------



## Audioboxer

PJVol said:


> @Audioboxer yeah, I see your point, and nothing wrong with it as well (for science lol)
> Just curious of some use cases where you can't be 100% sure (rather 99%) that someone is cheating, and assuring you that all is fair .
> And basically i wanna hear your opinion guys here, in regards to if anyone think it's possible to get to the 48-ish ns with a 3800 cl 15 or 4000 cl 15 in a fair way. Just it.


Around 54ns is simply the floor IMO with a 5950x at 3800. The lowest I've ever benched is 53.7ns. Taking away a CCD and it'll go down to 50.x at best. To get under 50 I had to go up to 4000/2000.

3800 flat 12 might go down a bit lower, I can't remember if I benched it previously. I'd need to sort out my CPU before trying again as no PBO with AIDA64 and your latency benches suffer. But that would be using maxmem, which is the mild controversy above. 53.7 was achieved without maxmem.



Luggage said:


> So thanks to @Eder posting unlocked 1205 bios MSI MEG X570 Unify Overclocking & Discussion Thread
> 
> @Veii @domdtxdissar @mongoled @Audioboxer @ManniX-ITA
> 
> @PJVol
> 
> 1.5V VID is back on the menu boys
> 
> First I tried with EDC at 140A for base line... then I kept upping it and VID did not get locked at 1.425 over 140A any more
> 
> 
> 
> http://imgur.com/a/daq6KEY
> 
> 
> I guess it's time to re-tune CO and everything again.


Wait, HWINFO is wrong? Or how did you not get locked at 1.425v?


----------



## Luggage

Audioboxer said:


> Around 54ns is simply the floor IMO with a 5950x at 3800. The lowest I've ever benched is 53.7ns. Taking away a CCD and it'll go down to 50.x at best. To get under 50 I had to go up to 4000/2000.
> 
> 3800 flat 12 might go down a bit lower, I can't remember if I benched it previously. I'd need to sort out my CPU before trying again as no PBO with AIDA64 and your latency benches suffer. But that would be using maxmem, which is the mild controversy above. 53.7 was achieved without maxmem.
> 
> 
> 
> Wait, HWINFO is wrong? Or how did you not get locked at 1.425v?


Not the same bios file


----------



## Audioboxer

Luggage said:


> Not the same bios file


The B550 BIOS was supposed to be unlocked previously, or has Eder unlocked it differently than whoever did it when it first leaked?


----------



## Imprezzion

Well my boards dead for now... Tried to get 3600C14 1T GDM off to POST, almost got it but it hangs on "22" code and no safe mode trigger so I CLR CMOS, aaaaand code 00 and it's completely dead. Doesn't respond to power button long press to turn off, CMOS doesn't do anything, just code 00.

ASUS.. why do you have to make it so damn difficult to recover from a OC fail to POST... Now I probably have to USB flashback the entire BIOS again to even make it POST..


----------



## Luggage

Audioboxer said:


> The B550 BIOS was supposed to be unlocked previously, or has Eder unlocked it differently than whoever did it when it first leaked?


Or perhaps user error. Leave limits on auto in bios and set them “up to mb limits” in RM -> keep 1.5V VID.
Set high EDC in bios -> VID is locked to 1.425.

_groan_


----------



## Audioboxer

Luggage said:


> Or perhaps user error. Leave limits on auto in bios and set them “up to mb limits” in RM -> keep 1.5V VID.
> Set high EDC in bios -> VID is locked to 1.425.
> 
> _groan_


RM? You mean when you turn PBO on and use MB limits in the bios it doesn't limit voltage? Going to test! Will also flash Eders version of the B550 unlocked BIOS just in case lol.


----------



## Luggage

Audioboxer said:


> RM? You mean when you turn PBO on and use MB limits in the bios it doesn't limit voltage? Going to test! Will also flash Eders version of the B550 unlocked BIOS just in case lol.


No - auto limits in bios. Adjust with Ryzen master.


----------



## Audioboxer

Luggage said:


> No - auto limits in bios. Adjust with Ryzen master.


lol really, that works? It's gotta be a bug in the bios then 😂


----------



## Mach3.2

Audioboxer said:


> lol really, that works? It's gotta be a bug in the bios then 😂


AMD/MSI strikes again 🤪


----------



## Luggage

Audioboxer said:


> lol really, that works? It's gotta be a bug in the bios then 😂





http://imgur.com/a/QbnI2NT


----------



## Audioboxer

Luggage said:


> http://imgur.com/a/QbnI2NT


Hmm if I enable PBO in the bios and leave it on auto it wants to set my EDC to 215 which introduces the voltage limit. Is there any way to do your curve in RM? To get access to the curve PBO needs to be on in the BIOS.

Thinking being if the BIOS boots on AUTO (pbo off) it can be turned on in RM without limiting the voltage. But if I turn on PBO in the BIOS and don't touch the limits it's wanting the EDC at 215. Maybe if I just manually set my EDC 140 and then override it in Windows lmao.

What is your EDC if you put PBO to advanced?

*edit* - Got it, have to set it to Manual -> Auto, not just leave PBO limits at Auto.


----------



## Luggage

Audioboxer said:


> Hmm if I enable PBO in the bios and leave it on auto it wants to set my EDC to 215 which introduces the voltage limit. Is there any way to do your curve in RM? To get access to the curve PBO needs to be on in the BIOS.
> 
> Thinking being if the BIOS boots on AUTO (pbo off) it can be turned on in RM without limiting the voltage. But if I turn on PBO in the BIOS and don't touch the limits it's wanting the EDC at 215. Maybe if I just manually set my EDC 140 and then override it in Windows lmao.
> 
> What is your EDC if you put PBO to advanced?


MB limit is 210, with the settings above it boots at amd default 140. So i can change it up to my old daily 170 ( or 210, mb limit) in RM but I cant raise the limit to 700 like i used to do to play with veii's L3 boost settings.


----------



## Audioboxer

Luggage said:


> MB limit is 210, with the settings above it boots at amd default 140. So i can change it up to my old daily 170 ( or 210, mb limit) in RM but I cant raise the limit to 700 like i used to do to play with veii's L3 boost settings.


Yeah I fixed my issue, needed to go to manual -> auto, rather than just leaving it on auto.

Can confirm it is working.

I take it there is no way to start Ryzen Master on startup? Oh the joys of having to workaround what could be a buggy bios 

Prior curve and settings OK in so far as my CB23 score creeped over 31k again. This is with telemetry. But with everyone thinking boosting changed for this AGESA I'm going to run Corecycler again on this curve.


----------



## Audioboxer

Corecycler has been running through my 4 best cores now for just over an hour and seems OK at the moment. Apart from the voltages being fine one thing I have noticed is 4,974mhz is definitely not a frequency my weaker cores parked at previously. I'm going to guess telemetry is a bit out as well as possibly a curve with this new AGESA.

I know Core effective clocks are where it is actually at, but I always keep an eye on the normal core clock requests as they usually show the silly 0.01 second boosts that can be achieved. These struggle to get over 5,050mhz for me with a 1.425v cap. For what little that is actually worth. Probably just certain benching with single core priority. Real world usage in games is going to be about multicore effective clocks.


----------



## Imprezzion

Audioboxer said:


> View attachment 2536880
> 
> 
> Corecycler has been running through my 4 best cores now for just over an hour and seems OK at the moment. Apart from the voltages being fine one thing I have noticed is 4,974mhz is definitely not a frequency my weaker cores parked at previously. I'm going to guess telemetry is a bit out as well as possibly a curve with this new AGESA.
> 
> I know Core effective clocks are where it is actually at, but I always keep an eye on the normal core clock requests as they usually show the silly 0.01 second boosts that can be achieved. These struggle to get over 5,050mhz for me with a 1.425v cap. For what little that is actually worth. Probably just certain benching with single core priority. Real world usage in games is going to be about multicore effective clocks.


On the latest official B550-XE BIOS I run which is AGESA 1.2.0.3 C my 5900X runs those short boosts (with +100 max boost) at 5050 but it does request like, 1.525v VID for that even at -20 all-core curve. Actual SVI2 TFN is more like 1.488-1.496v but still. A lot. Full all-core load sits at around 4650-4675 (effective as well) with 231xx in CB23 and 102xx in CPU-Z with single core at 673 which are the 2 benches I use to quickly compare different EDC, curve and such to see if it gets better or worse. Voltage in all-core SVI2 TFN is around 1.331v at that point.

So far I noticed I kinda have to use 170 EDC as any higher tanks single core scores and any lower drops multi core so 170 is definitely the sweet spot. Single core sustained boost is 4950 btw.

I am curious to see how this all changes once a AGESA 1.2.0.5 BIOS gets released for the B550-XE.

Btw, does anyone know what I should change in the RAM config if it wont POST with code 22 (memory_initialization)? I am trying to get 1T GDM off to work but even on 3600 with pretty loose timings and with clkdrvstr 56 or more, at 40-20-20-20 or 40-20-24-30 it does the same. ProcODT was at 36.9 an I tried 40.8 as well, same result. I haven't done much tweaking to RTT's yet but maybe that'll help?


----------



## Audioboxer

Imprezzion said:


> On the latest official B550-XE BIOS I run which is AGESA 1.2.0.3 C my 5900X runs those short boosts (with +100 max boost) at 5050 but it does request like, 1.525v VID for that even at -20 all-core curve. Actual SVI2 TFN is more like 1.488-1.496v but still. A lot. Full all-core load sits at around 4650-4675 (effective as well) with 231xx in CB23 and 102xx in CPU-Z with single core at 673 which are the 2 benches I use to quickly compare different EDC, curve and such to see if it gets better or worse. Voltage in all-core SVI2 TFN is around 1.331v at that point.
> 
> So far I noticed I kinda have to use 170 EDC as any higher tanks single core scores and any lower drops multi core so 170 is definitely the sweet spot. Single core sustained boost is 4950 btw.
> 
> I am curious to see how this all changes once a AGESA 1.2.0.5 BIOS gets released for the B550-XE.
> 
> Btw, does anyone know what I should change in the RAM config if it wont POST with code 22 (memory_initialization)? I am trying to get 1T GDM off to work but even on 3600 with pretty loose timings and with clkdrvstr 56 or more, at 40-20-20-20 or 40-20-24-30 it does the same. ProcODT was at 36.9 an I tried 40.8 as well, same result. I haven't done much tweaking to RTT's yet but maybe that'll help?


I've gone back to running 270/168/220, just seems to be a good area for me. While I'm registering 1.488v above, it's probably a bit higher. Unsure if voltage reports correctly with telemetry, I think like PBO values, it reports lower than it actually is.

Here's hoping 1.2.0.5 final doesn't have an EDC voltage cap, would rather not have to have AMD Ryzen Master installed lol.

11 iterations of corecycler now, I'm going to guess my old curve will be stable. What remains now is to see if it's still the best curve to use.


----------



## Bix

PJVol said:


> Yeah, but you may try my way of preliminary checking with the AIDA photoworxx test, comparing it to a highest result at a certain fclk - this saves a lot of time. If result decreased by more than 500 of whatever, just rebot immediately.


That's more like it, thanks for the tip. All benchmarks should be 30 secs long!


----------



## Luggage

Bix said:


> That's more like it, thanks for the tip. All benchmarks should be 30 secs long!


OCCT is nice with every sub-test being 10 seconds but god damn it fluctuates with my 5800X, well most benchmarks do... y-cruncher and gb being among the more consistent among the short ones.


----------



## mirzet1976

I need some help with these 2 errors.
I replaced the 5600X with 5700G in the BIOS there is no more VDDG CCD / IOD option and VDIMM is at 1.62V.


----------



## Audioboxer

mirzet1976 said:


> I need some help with these 2 errors.
> I replaced the 5600X with 5700G in the BIOS there is no more VDDG CCD / IOD option and VDIMM is at 1.62V.
> View attachment 2536938
> 
> 
> View attachment 2536939


15 I've found could be tRFC, 1 I've only come across recently and it was when trying to push a high voltage through my memory without using maxmem.

But I was up at like 1.7v. Still, I guess your memory might be struggling at 1.62v.

Not sure that can help you much and unfortunately I don't have much experience running such high frequency/IF.


----------



## Imprezzion

Bah I got a WHEA interconnect error in event viewer when playing Halo Infinite campaign and shortly after even a BSOD with a WHEA uncorrectable error.. guess it didn't like 3866 memory 1:1 1933 F+U. It's been fine for an hour on 3800 1900 tho. Gotta do some more fine tuning I guess.


----------



## garf333

Have everything dialed in except for TFC2/4, ProcODT/RTTs, and the ClockDrv values. Anything else I can improve?

These are 4 sticks of Single Rank Micron Rev Bs on a 5900X, and is TM5 stable.

Thanks


----------



## Bix

Luggage said:


> god damn it fluctuates with my 5800X, well most benchmarks do...


I feel your pain! I've used y-cruncher a lot for stress testing but not much for benching so will give it a go, thanks🙂

Still finding it really hard to find the best voltage stepping... 900 VDDP, 940 CCD, 1060 IOD and 1.1375 SOC (with a lot of droop) seemed to be the most stable and performative at 2000 FCLK _before_ doing CPU and mem oc (stability testing with y-cruncher and latencymon, performance testing with lots of other benches) but now with PBO and memory tuned I'm struggling to find changes that actually improve things. Should I be concentrating on changing each voltage separately or increasing/decreasing the step size between all of them at once?? Brick wall is looming...


----------



## Luggage

Bix said:


> I feel your pain! I've used y-cruncher a lot for stress testing but not much for benching so will give it a go, thanks🙂
> 
> Still finding it really hard to find the best voltage stepping... 900 VDDP, 940 CCD, 1060 IOD and 1.1375 SOC (with a lot of droop) seemed to be the most stable and performative at 2000 FCLK _before_ doing CPU and mem oc (stability testing with y-cruncher and latencymon, performance testing with lots of other benches) but now with PBO and memory tuned I'm struggling to find changes that actually improve things. Should I be concentrating on changing each voltage separately or increasing/decreasing the step size between all of them at once?? Brick wall is looming...


Can't boot 1900+ :/ And after stabilizing ram I want soc as low as possible to not steeal power budget from core boost. Don't really know if the other voltages do that as well..


----------



## Audioboxer

Imprezzion said:


> Bah I got a WHEA interconnect error in event viewer when playing Halo Infinite campaign and shortly after even a BSOD with a WHEA uncorrectable error.. guess it didn't like 3866 memory 1:1 1933 F+U. It's been fine for an hour on 3800 1900 tho. Gotta do some more fine tuning I guess.


Best way to weed out FCLK issues is honestly y-cruncher test 17, let it loop, lol. It's pretty brutal on the CPU. If you can pass that for an hour or two without critical WHEA errors/reboots/USB disconnects I'd say you've got a good chance of running daily above 1900.


----------



## Imprezzion

Audioboxer said:


> Best way to weed out FCLK issues is honestly y-cruncher test 17, let it loop, lol. It's pretty brutal on the CPU. If you can pass that for an hour or two without critical WHEA errors/reboots/USB disconnects I'd say you've got a good chance of running daily above 1900.


Yeah no. I started y-cruncher test 17 and my keyboard backlight started flashing like mad l on 1967 IF lel.... USB ain't happy there haha. 

Gotta fix the training first. RAM and IF is stable just fine at 3800/1900 but it won't train tPHYRDL at all. 26/28 no matter what I do with the ProcODT, DrvStr's and such. Gotta somehow find a way to make it train or make CAS 14 work. Which so far is a total no-go..


----------



## Audioboxer

Imprezzion said:


> Yeah no. I started y-cruncher test 17 and my keyboard backlight started flashing like mad l on 1967 IF lel.... USB ain't happy there haha.
> 
> Gotta fix the training first. RAM and IF is stable just fine at 3800/1900 but it won't train tPHYRDL at all. 26/28 no matter what I do with the ProcODT, DrvStr's and such. Gotta somehow find a way to make it train or make CAS 14 work. Which so far is a total no-go..


Yup, welcome to my world lol.

I've had some issues with 28/26 before, but now get 28/28 at tCL14. Or as I run, 26/26 at tCL13. tCL15 would be 26/26. I've never got to the bottom of this, I just roll with it now. Even tCL will be 28/28, uneven tCL will be 26/26.

But yeah even getting 28/28 will be preferred over 28/26. IIRC there is about a 0.5ns penalty for mismatched tPHYRDL.


----------



## Imprezzion

Audioboxer said:


> Yup, welcome to my world lol.
> 
> I've had some issues with 28/26 before, but now get 28/28 at tCL14. Or as I run, 26/26 at tCL13. tCL15 would be 26/26. I've never got to the bottom of this, I just roll with it now. Even tCL will be 28/28, uneven tCL will be 26/26.
> 
> But yeah even getting 28/28 will be preferred over 28/26. IIRC there is about a 0.5ns penalty for mismatched tPHYRDL.


Yeah it's comparable to Intel running RTL/IO outside of + - 2 training. It was a disaster to get 4400C17 to train RTL 64/65 IO 6/6 on Intel. But at least on Z490 you can play with it yourself like, setting a RTL/IO Initial and Offset value to try and correct it. On AMD you really can't.. 

For me it's tCL 15 causing it. 16 trains 26/26 just fine. 15 is 26/28. 14 I can't boot reliable yet so I don't know what that would be..


----------



## Audioboxer

Imprezzion said:


> Yeah it's comparable to Intel running RTL/IO outside of + - 2 training. It was a disaster to get 4400C17 to train RTL 64/65 IO 6/6 on Intel. But at least on Z490 you can play with it yourself like, setting a RTL/IO Initial and Offset value to try and correct it. On AMD you really can't..
> 
> For me it's tCL 15 causing it. 16 trains 26/26 just fine. 15 is 26/28. 14 I can't boot reliable yet so I don't know what that would be..


Are you using Setup times? I can't remember if you've said.

They definitely play a role in modifying tPHYRDL behaviour, but I've not quite managed to understand what exactly. Moving around a bit from 56, to like 53 and up to 60, hasn't appeared to do anything to change behaviour.

What happens with 2T/no setup times at 15?


----------



## Imprezzion

Audioboxer said:


> Are you using Setup times? I can't remember if you've said.
> 
> They definitely play a role in modifying tPHYRDL behaviour, but I've not quite managed to understand what exactly. Moving around a bit from 56, to like 53 and up to 60, hasn't appeared to do anything to change behaviour.
> 
> What happens with 2T/no setup times at 15?


That is 2T with no setup times. With 56 it still does the same. I went to 14-15-8-15-28-2T and now it does do 26/26 but my dimms need like 1.60v to even dream of doing tCL 14 stable. Not a problem, I ran 1.650v on Intel at 4400 16-17-17 for ages, but they aren't as well cooled now as I had them back then so 1.60v probably causes them to go over 47c which causes a whole bunch of other problems again...

Also. No POST with tWRRD at 2 with tCL 14. On 15 it's fine..

Here, this is where I am at now. Everything tweaked, nothing on Auto including voltages, all manual. 
This is not tested with TM5 at all, just POST + Boot stable and vDIMM is 1.600v. It's 26/26 now. If this somehow is stable and won't melt the DIMM's i'll run with it lol. 

DIMM #1 slot A2:









DIMM #2 slot B2


----------



## Audioboxer

Imprezzion said:


> That is 2T with no setup times. With 56 it still does the same. I went to 14-15-8-15-28-2T and now it does do 26/26 but my dimms need like 1.60v to even dream of doing tCL 14 stable. Not a problem, I ran 1.650v on Intel at 4400 16-17-17 for ages, but they aren't as well cooled now as I had them back then so 1.60v probably causes them to go over 47c which causes a whole bunch of other problems again...
> 
> Also. No POST with tWRRD at 2 with tCL 14. On 15 it's fine..
> 
> Here, this is where I am at now. Everything tweaked, nothing on Auto including voltages, all manual.
> This is not tested with TM5 at all, just POST + Boot stable and vDIMM is 1.600v. It's 26/26 now. If this somehow is stable and won't melt the DIMM's i'll run with it lol.
> 
> DIMM #1 slot A2:
> View attachment 2537150
> 
> 
> DIMM #2 slot B2
> View attachment 2537149


Oooft, that's a tough one to crack. I thought you were going to tell me you get it working OK at 2T. I'm at a loss understanding tPHYRDL at times. Try your VSOC at 1.125~1.15v for me and let me know if tPHYRDL changes. Probably not.

You shouldn't need setup times with 2T by the way on your new profile, unless you're just testing at 2T and plan to switch over to 1T.

Surprised you're getting away with RttNom disabled, I'd probably just run it at 7.

Temp wise, 47 degrees is still fine for B-die, but as you pointed out things can get flaky. Usually tRFC, but 258 isn't too tight. Also good to keep in mind TM5 will likely always run your DIMMs hotter than say playing a game or something, but it is good to have the thermal overheard for summer and the likes. So I tend to think a daily should have to be stable temp wise on a TM5 run. Don't risk an error on a TM5 run if you know its temps on the basis you think you can hold like 42~44 degrees max under normal usage.

But yeah, if I were you I'd be desperate to make tCL14 work lol. Good luck! RttPark 4~5 _might_ help reduce temps a degree or two, but it also might not be stable.


----------



## Bix

Luggage said:


> Can't boot 1900+ :/ And after stabilizing ram I want soc as low as possible to not steeal power budget from core boost. Don't really know if the other voltages do that as well..


My 5900x appears to be a good sample but it's definitely being held back by its owner's incompetence😂 

I'd assumed that I'd need to go higher with voltages given what others here seem to need at 2000 FCLK but so far going lower seems to be getting better results.


----------



## Imprezzion

Audioboxer said:


> Oooft, that's a tough one to crack. I thought you were going to tell me you get it working OK at 2T. I'm at a loss understanding tPHYRDL at times. Try your VSOC at 1.125~1.15v for me and let me know if tPHYRDL changes. Probably not.
> 
> You shouldn't need setup times with 2T by the way on your new profile, unless you're just testing at 2T and plan to switch over to 1T.
> 
> Surprised you're getting away with RttNom disabled, I'd probably just run it at 7.
> 
> Temp wise, 47 degrees is still fine for B-die, but as you pointed out things can get flaky. Usually tRFC, but 258 isn't too tight. Also good to keep in mind TM5 will likely always run your DIMMs hotter than say playing a game or something, but it is good to have the thermal overheard for summer and the likes. So I tend to think a daily should have to be stable temp wise on a TM5 run. Don't risk an error on a TM5 run if you know its temps on the basis you think you can hold like 42~44 degrees max under normal usage.
> 
> But yeah, if I were you I'd be desperate to make tCL14 work lol. Good luck! RttPark 4~5 _might_ help reduce temps a degree or two, but it also might not be stable.


3 errors so far. 6, 10, 11. 6 is easy to fix, most likely just doesn't like 4 tWRRD or needs a slight adjustment on VDDP / VDDG / ProcODT. 10 is tWR on 10 and tRTP on 5 not playing very nice, 11 is pure heat. It only came after like 50 minutes when they really started to heat up past 48c. And no, TM5 ain't the worst. They get hotter when gaming as the loop heats up way more then and has more hot air from the front intake rad blowing on the DIMM's as the GPU also has 370w of heat into it then. tCL 14 ain't happening without extensive tweaks on 3800. So, I can basically choose between flat 15's with tPHYRDL mismatch or flat 16's with it matching at 26/26. 

Or, I have to somehow manage to get 2000 IF to run stable for 4000C16 but the problem with that is that it takes me a LOT of vSOC to get that to work which eats into the core boost budget again.. Sigh. I thought Z490 was a lot of work to tune RAM but..


----------



## Audioboxer

Imprezzion said:


> 3 errors so far. 6, 10, 11. 6 is easy to fix, most likely just doesn't like 4 tWRRD or needs a slight adjustment on VDDP / VDDG / ProcODT. 10 is tWR on 10 and tRTP on 5 not playing very nice, 11 is pure heat. It only came after like 50 minutes when they really started to heat up past 48c. And no, TM5 ain't the worst. They get hotter when gaming as the loop heats up way more then and has more hot air from the front intake rad blowing on the DIMM's as the GPU also has 370w of heat into it then. tCL 14 ain't happening without extensive tweaks on 3800. So, I can basically choose between flat 15's with tPHYRDL mismatch or flat 16's with it matching at 26/26.
> 
> Or, I have to somehow manage to get 2000 IF to run stable for 4000C16 but the problem with that is that it takes me a LOT of vSOC to get that to work which eats into the core boost budget again.. Sigh. I thought Z490 was a lot of work to tune RAM but..


Believe it or not the latency difference between 14-15-15-15 and 16-16-16-16, as long as your secondaries are tight, will probably not be too much at 3800. You could bench at 15-15-15-15 and see what your penalty is like. Just check the latency. And I'd hold out hope yet still finding a way to fix to 26/26 or even 28/28 at 15-15-15-15.

Sounds like temps matter quite a bit for you, so I'd set a voltage limit with a good thermal overhead and work to that. 3800 16-16-16-16 should really be doable at maybe even 1.4v depending on your silicon. 1.45v max if you want to drop tRFC a bit more. That'll bring down temps a fair bit from 1.6v.


----------



## Imprezzion

Audioboxer said:


> Believe it or not the latency difference between 14-15-15-15 and 16-16-16-16, as long as your secondaries are tight, will probably not be too much at 3800. You could bench at 15-15-15-15 and see what your penalty is like. Just check the latency. And I'd hold out hope yet still finding a way to fix to 26/26 or even 28/28 at 15-15-15-15.
> 
> Sounds like temps matter quite a bit for you, so I'd set a voltage limit with a good thermal overhead and work to that. 3800 16-16-16-16 should really be doable at maybe even 1.4v depending on your silicon. 1.45v max if you want to drop tRFC a bit more. That'll bring down temps a fair bit from 1.6v.


Yeah 15's with reasonably tight secondaries is 1.50v vDIMM which is around 46c in games at 22c ambients. That is doable 24/7. 

I will put some time into either getting tPHYRDL to match or just going either 14 or 16. Or maybe even a combination as in 14-16-16 to make it slightly more stable but also not run tCL 16.


----------



## nick name

Does anyone else lower VTTDDR? It seems that I can run .700V with 1.54V DRAM. Not entirely sure if there is a benefit to this.


----------



## ManniX-ITA

nick name said:


> Does anyone else lower VTTDDR? It seems that I can run .700V with 1.54V DRAM. Not entirely sure if there is a benefit to this.


Yes, I generally set it lower around 100mV.
But often more than 150mV can cause instability.
You can try also higher than VDIMM but so far I didn't find it helping.


----------



## Imprezzion

3800 15's with mismatched tPHYRDL is 593xx read 584xx write 566xx copy 57.6ns latency. 3800 16's with matched tPHYRDL is basically the same within margin of error for r/w/c but latency is actually higher at 58.3ns. That is kinda outside of margin of error even tho AIDA tests do have quite a lot of variance between runs on my not so clean Windows. 

For some weird reason taking my 3800 15 profile and just setting the primaries to 16 makes it not POST with a 22 code again so that is also not helping...

I wonder if 4400C17 with 1:2 IF would actually be faster even with 1:2. Anyone ever test this?


----------



## Veii

Imprezzion said:


> For some weird reason taking my 3800 15 profile and just setting the primaries to 16 makes it not POST with a 22 code again so that is also not helping...


tCL change needs tCWL change, needs tRDWR change
If tCWL ends up being -2 of tCL, tRDWR needs that +2
Never forget 








Stability is another thing, but it's fun i guess ^^
Wonder why tCWL can't be 8
was trying to get tPHYWRL smaller than 4  ~ changes with tRDWR & tCWL


----------



## TMavica

deleted


----------



## Taraquin

Veii said:


> tCL change needs tCWL change, needs tRDWR change
> If tCWL ends up being -2 of tCL, tRDWR needs that +2
> Never forget
> 
> View attachment 2537195
> 
> Stability is another thing, but it's fun i guess ^^
> Wonder why tCWL can't be 8
> was trying to get tPHYWRL smaller than 4  ~ changes with tRDWR & tCWL


Atleast on SR it seems like CL=CWL=RDWRx2 (+1 if odd CL) is a good and stable deal for most


----------



## Audioboxer

Even when I run something silly like tCL12, still can't squeeze under 50 at 3800 lol. Going to guess TERRO apart from using maxmem also benefits from a 1 CCD processor with an all core overclock and using SR.

Just goes to show you when you're around the FCLK limit at 3800, there is serious diminishing gains pumping voltages through your RAM, especially if DR, to try and get to like tCL13 or maybe even tCL14. I've seen some flat 15 benches be pretty damn close to what would be achieved at flat 14.

Big jumps in lower latency without sweating over small drops seems to be from achieving 4000/2000 on AMD.










My 2 CCD latency is literally no different from my tCL13 daily profile.


----------



## domdtxdissar

Audioboxer said:


> View attachment 2537240
> 
> 
> Even when I run something silly like tCL12, still can't squeeze under 50 at 3800 lol. Going to guess TERRO apart from using maxmem also benefits from a 1 CCD processor with an all core overclock and using SR.
> 
> Just goes to show you when you're around the FCLK limit at 3800, there is serious diminishing gains pumping voltages through your RAM, especially if DR, to try and get to like tCL13 or maybe even tCL14. I've seen some flat 15 benches be pretty damn close to what would be achieved at flat 14.
> 
> Big jumps in lower latency without sweating over small drops seems to be from achieving 4000/2000 on AMD.
> 
> View attachment 2537242
> 
> 
> My 2 CCD latency is literally no different from my tCL13 daily profile.


Would think you would see more differences in other real benchmarks other then Aida64.. Aida64 dont "measure the performance" like real benchmarks, it calculate it from some base values.

Hence my 85k mb/sec bandwidth numbers with Hydra.. Same can to be seen on Intel systems when running baseclock above 100mhz. (Aida calculate impossible latency numbers)

Can read these two threads if you want more background:

*How Low Can You Go? AIDA64 Memory Latency Challenge*

*How High Can You Fly? AIDA64 Memory Bandwidth Challenge*


----------



## Audioboxer

domdtxdissar said:


> Would think you would see more differences in other real benchmarks other then Aida64.. Aida64 dont "measure the performance" like real benchmarks, it calculate it from some base values.
> 
> Hence my 85k mb/sec bandwidth numbers with Hydra.. Same can to be on Intel systems when running baseclock above 100mhz. (calculate impossible latency numbers)
> 
> Can read these two threads if you want more background:
> 
> *How Low Can You Go? AIDA64 Memory Latency Challenge*
> 
> *How High Can You Fly? AIDA64 Memory Bandwidth Challenge*


True, I've liked using the membench in DRAM Calculator before, or whatever its called. _Everyone_ always asks for AIDA though 

And dom you should mess about with maxmem just to see what results you get. Your 5950x will be better tuned than mine.










Copy that and go to town with benching lol.


----------



## PJVol

Audioboxer said:


> And I'd hold out hope yet still finding a way to fix to 26/26 or even 28/28 at 15-15-15-15


You know of the way to fix this? )


----------



## Audioboxer

PJVol said:


> You know of the way to fix this? )
> View attachment 2537280


LOL, I've never seen that before. Only ever 26/28 or 28/30.

Um, two things, is it paired when you go to 3800/1900? Secondly, try adding a 55 or 56 AddrCmdSetup time for me and tell me if behaviour changes (yes, I know you are on SR, but just let me know if Setup timing changes behaviour).


----------



## PJVol

Audioboxer said:


> yes, I know you are on SR, but just let me know if Setup timing changes behaviour


AddrCmdSetup 56, well... *hardlocked *PC boot right away ))
CLR_CMOS needed to revive

To fix phy latency mismatch, pickin' up right VDDP/ODT combo do the trick, as below

PS: Forgot to add, VDDP 0.850 goes straight to 28/28


----------



## Audioboxer

PJVol said:


> AddrCmdSetup 56, well... *hardlocked *PC boot right away ))
> CLR_CMOS needed to revive
> 
> To fix phy latenciy mismatch, pickin' up right VDDP/ODT combo do the trick, as below


28/26 is more common for me, but I've never really got to the bottom of it. With the settings I have right now if I run tCL 12/14 at 1T/56 I get 28/28, so it's fine now. But in the past it has been 28/26. I'm not entirely sure what changed that shifted the other DIMM up to 28.

This is why I run tCL13 and it is 26/26


----------



## Veii

PJVol said:


> You know of the way to fix this? )
> View attachment 2537280
> 
> 
> 
> Audioboxer said:
> 
> 
> 
> 28/26 is more common for me, but I've never really got to the bottom of it.
Click to expand...

26-32 ? o . O
The most common for me was 24-26 on DR
Both ITX and ASUS Creator

For SR ITX stays firm at 26-26, very firm
Soo much, that i had suspected ZenTimings at first to not track it
It was just ASRock managing good memory training

tPHYRDL change i've seen on
~ tRDWR & tCWL
~ SCL
~ cLDO_VDDP
~ procODT
~ RTTs
~ tRRD funnily too
~ VDIMM
~ VDD18

Pretty much all are powering except tRRD & SCL + tRDRW being the awkward kid here
Sadly couldn't confirm or deny the requirements for CMOS reset, on tPHY recalculation
It does do a coldboot and fix it on MCLK stepup/downjump
It should do one on procODT change
But i am not sure if it really always updates ~ as i had Zentimings once caching results (SMU in such case) from a different set of dimms
Very sure tho, that it does update on a bios reload ~ after CMOS reset , BUT this on my side wipes AMD OVERCLOCKING fully
For ASUS boards i've seen the opposite. They remember the OVERCLOCKING tab, but forget AMD CBS on CMOS reset or "DirectBoot Bios" function , as the reset key


----------



## Asutz

Damn Guys, think i have killed Memory or Motherboard or maybe Psu with Oc, not 100% sure, cant really test other Hardware at the moment.Had to reflash the Board 4 or 5 Times and several ClearCmos to even get the System running.Bios defaults and just Docp, nearly instant crashing.

If its the Board, what would you recommend for just a bit oc.Dont wanna spend 300 Euro again like with the old Hero 7.
Think a good B550 is enough.Thanks


----------



## ManniX-ITA

Asutz said:


> Damn Guys, think i have killed Memory or Motherboard or maybe Psu with Oc, not 100% sure, cant really test other Hardware at the moment.Had to reflash the Board 4 or 5 Times and several ClearCmos to even get the System running.Bios defaults and just Docp, nearly instant crashing.
> 
> If its the Board, what would you recommend for just a bit oc.Dont wanna spend 300 Euro again like with the old Hero 7.
> Think a good B550 is enough.Thanks


Well a good B550 doesn't cost much less 

2 DIMM slots are enough?









MSI MEG B550 UNIFY-X ATX Gaming Mainboard, AMD AM4 Ryzen 5000, 14+2 Phasendesign 90A-Leistungsstufe, integrierte Kühlung, 2xDDR4-Dual-Channel, Gen4 M.2-Anschlüsse,Wi-Fi 6 2,5 Gbit/s LAN: Amazon.de: Computer & Zubehör


MSI MEG B550 UNIFY-X ATX Gaming Mainboard, AMD AM4 Ryzen 5000, 14+2 Phasendesign 90A-Leistungsstufe, integrierte Kühlung, 2xDDR4-Dual-Channel(64GB/5300MHz), Gen4 M.2-Anschlüsse,Wi-Fi 6 2,5 Gbit/s LAN - Kostenloser Versand ab 29€. Jetzt bei Amazon.de bestellen!



www.amazon.de





At this price the Unify-X it's a good deal.


----------



## Imprezzion

ManniX-ITA said:


> Well a good B550 doesn't cost much less
> 
> 2 DIMM slots are enough?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> MSI MEG B550 UNIFY-X ATX Gaming Mainboard, AMD AM4 Ryzen 5000, 14+2 Phasendesign 90A-Leistungsstufe, integrierte Kühlung, 2xDDR4-Dual-Channel, Gen4 M.2-Anschlüsse,Wi-Fi 6 2,5 Gbit/s LAN: Amazon.de: Computer & Zubehör
> 
> 
> MSI MEG B550 UNIFY-X ATX Gaming Mainboard, AMD AM4 Ryzen 5000, 14+2 Phasendesign 90A-Leistungsstufe, integrierte Kühlung, 2xDDR4-Dual-Channel(64GB/5300MHz), Gen4 M.2-Anschlüsse,Wi-Fi 6 2,5 Gbit/s LAN - Kostenloser Versand ab 29€. Jetzt bei Amazon.de bestellen!
> 
> 
> 
> www.amazon.de
> 
> 
> 
> 
> 
> At this price the Unify-X it's a good deal.


This or the board that I use if ya need 4 slots. The ASUS B550-XE (or normal -E). I love this board to death already lol. Has all the features I could ever want and VRM stays at barely 55c even with zero airflow. And no stupid X570 chipset fan hehe. The -XE WiFi is rather pricy tho. I got mine heavily discounted as it was missing the hyper m.2 card after it was send back to a shop as a 30 day return item (probably just to steal the m.2 card) so I had a great deal on it but still.

Only downside is the totally illogical BIOS lay-out with duplicate menu's and duplicate settings for PBO, memory and other OC related stuff that bug to hell if you don't set both correctly (or leave one set Auto and adjust the other).

I saw the B550-XE being called the baby Crosshair on reddit and I kinda agree with that name.


----------



## Asutz

****  expected that someone puts the Unify-X into the ring, looking forward to buy that if its cheap somewhere, was hoping for something like b550 tomahawk is fine too ^^
tested the memory for just 1hour yesterday, it was ok, no errors, so maybe at least that 1 dimm is ok, so psu or maybe motherboard is faulty, old 1080ti maybe too but no chance to get similar performance for a good price.

asus, unsure, its good, yes but for the ch7 it takes ages to get newer bios and the tripple oc settings in different categories, hat that, 1 or 2 wrong settings and another factor created for an unstable system. 

is it better on the msi side or a pure amd agesa thing?


----------



## Veii

Asutz said:


> is it better on the msi side or a pure amd agesa thing?


It's an AGESA hierarchy thing.
I see nothing wrong with it, they have different amount of access. Some deeper some not, some persistent in profiles others not

It's a vendors thing to decide which option to keep and hope AGESA doesn't break this method of PBO
or they let both options there, soo the user can pick if one is broken.
3 options if the Vendor leaves the untoched AMD CBS - but too many censor it away (not good)

As for CMOS ~ do not reset CMOS after a flashback or bios update
Doing so will wipe important NVRAM values that where updated, and can even wipe half of the bios ~ if sector/capsules where not transfered in time, or have for example a 2nd stage firmware update process after post
Very important. Not holding this can indeed softbrick boards.
Let it post once into the OS or just the bios ~ before doing any "restore defaults" or cmos wipe shenanigans.

The board will wipe what it has to wipe, by itself on a bios update
What you can do, is wipe CMOS before the update ~ soo the update won't freeze by user-caused instability


----------



## Imprezzion

Which voltages all effect M/F/UCLK stability in general? I'm still trying to push for 4000C16 with 1:1 IF but even at 1.275v SOC it does boot to windows but even with no load it has like 19 errors a minute lol.. 

I have no clue how VDDP / VDDG affects this or if any other voltage does like CPU 1.8v or VDDP Standby or whatever. Could someone give me some pointers? 

I had them set to 1.000v CLDO, 0.975v CCD, 1.025v IOD, 1.29375v SOC (1.275v after droop), 1.50v DRAM, rest all Auto.


----------



## Asutz

Thanks Veii, than i did it wrong, before flashback i always rebooted, went into bios and loaded defaults, fired the system up and booted once,cleared cmos after shutdown but not always and then ill started reflash, often clear csmos again after. problem often occured was that after flash and starting the pc, all i got was just a black screen and followed by error/status code 02.several times.so possible that was indeed not the best for the board. good to know.


----------



## Audioboxer

Veii said:


> 26-32 ? o . O
> The most common for me was 24-26 on DR
> Both ITX and ASUS Creator
> 
> For SR ITX stays firm at 26-26, very firm
> Soo much, that i had suspected ZenTimings at first to not track it
> It was just ASRock managing good memory training
> 
> tPHYRDL change i've seen on
> ~ tRDWR & tCWL
> ~ SCL
> ~ cLDO_VDDP
> ~ procODT
> ~ RTTs
> ~ tRRD funnily too
> ~ VDIMM
> ~ VDD18
> 
> Pretty much all are powering except tRRD & SCL + tRDRW being the awkward kid here
> Sadly couldn't confirm or deny the requirements for CMOS reset, on tPHY recalculation
> It does do a coldboot and fix it on MCLK stepup/downjump
> It should do one on procODT change
> But i am not sure if it really always updates ~ as i had Zentimings once caching results (SMU in such case) from a different set of dimms
> Very sure tho, that it does update on a bios reload ~ after CMOS reset , BUT this on my side wipes AMD OVERCLOCKING fully
> For ASUS boards i've seen the opposite. They remember the OVERCLOCKING tab, but forget AMD CBS on CMOS reset or "DirectBoot Bios" function , as the reset key


I actually managed to replicate 26/32 lmao, for the first time ever.

I took my current daily profile and changed to 3866 just so I could have a quick look at FCLK 1933. Not only did I still have USB issues (no surprise there), my memory actually trained at 26/32 instead of 26/26 lmao.

Going to guess that is maybe just to do with how on the edge my daily profile is at 3800, though I did bump my VDIMM up to 1.6v in advance just to give 13-8-14-12 a better chance at 3866.


----------



## Veii

Crash course, Powering:


----------



## Asutz

sry me again, loaded defaults, docp 1 stick 16gb, rest mostly untouched. screem goes black, status code d3 and still sound in the background. eventwvr, kernel power, event id 41
tried c-states on / off, low current idle set, soc uncore oc mode disabled / enabled tested, soc fix p0 state, the settings that help in the past if i remember correctly not rly helping. something is definitly broken as it seems.


----------



## Audioboxer

Veii said:


> Crash course, Powering:
> 
> View attachment 2537334


Gotta ask at this stage, what exactly does GDM handle, in full? Cause when GDM is running often you see profiles running all sorts of voltages/Rtts/DrvStrs and sometimes even ProcODT that you know if they had GDM disabled their stability tests would freak out. Often even with the same timings.

Does GDM handle a lot of this behind the scenes or something? I've always taken the assumption it does do some "autocorrecting" for lack of a better word.


----------



## domdtxdissar

@Veii

You already had a B2 stepping ? Have you verified its a 0A201204h ? What week ?

__ https://twitter.com/i/web/status/1470410350562791425


----------



## Imprezzion

tCL 14 is fixed, it works now. Literally just set 14-15-15-15 with the VSOC, VDDP and VDDG's you see here and set ProcODT, RTT's and DrvStr's and didn't touch any other timing. All sub timings Auto but at least it CAN run tCL 14 and trains tPHYRDL to 26/26 nowwhich it still refuses to do on tCL 15. DIMM's do get a bit toasty at 43c but this is running 1.545v vDIMM so not too bad. I am going to tune some sub timings and test again with 25 cycles overnight I guess but this is definitely "daily" material here.


----------



## KedarWolf

Imprezzion said:


> View attachment 2537374
> 
> 
> tCL 14 is fixed, it works now. Literally just set 14-15-15-15 with the VSOC, VDDP and VDDG's you see here and set ProcODT, RTT's and DrvStr's and didn't touch any other timing. All sub timings Auto but at least it CAN run tCL 14 and trains tPHYRDL to 26/26 nowwhich it still refuses to do on tCL 15. DIMM's do get a bit toasty at 43c but this is running 1.545v vDIMM so not too bad. I am going to tune some sub timings and test again with 25 cycles overnight I guess but this is definitely "daily" material here.


Is that b-die RAM, and if it is, your tRFC could be quite a bit lower. It'll help with latency. 

Edit: I think I have the same RAM. I'll show you what works for me, just try it with the 15's etc.


----------



## Luggage

domdtxdissar said:


> @Veii
> 
> You already had a B2 stepping ? Have you verified its a 0A201204h ? What week ?
> 
> __ https://twitter.com/i/web/status/1470410350562791425


This led me to 


https://skatterbencher.com/2021/09/19/skatterbencher-29-amd-ryzen-9-5900-b2-overclocked-to-5152-mhz/



Is it just me or is his stock results really low?


----------



## domdtxdissar

Luggage said:


> This led me to
> 
> 
> https://skatterbencher.com/2021/09/19/skatterbencher-29-amd-ryzen-9-5900-b2-overclocked-to-5152-mhz/
> 
> 
> 
> Is it just me or is his stock results really low?


Yes i also think stock ST maybe look alittle on the low side.. But then again, i dont have much experience with 5900 non-x (*65w and fmax 4700*) Maybe its normal for these OEM cpus..



> Cinebench R23 Single: 1,476 points
> [*]Cinebench R23 Multi: 18,847 points





> Here are the 3DMark CPU Profile scores at stock
> 
> CPU Profile 1 Thread: 939
> CPU Profile 2 Threads: 1,858
> CPU Profile 4 Threads: 3,505
> CPU Profile 8 Threads: 6,009
> CPU Profile 16 Threads: 7,746
> CPU Profile Max Threads: 8,434


----------



## MrHoof

Luggage said:


> This led me to
> 
> 
> https://skatterbencher.com/2021/09/19/skatterbencher-29-amd-ryzen-9-5900-b2-overclocked-to-5152-mhz/
> 
> 
> 
> Is it just me or is his stock results really low?


Saw that aswell and here is a video from that guy


Spoiler: video













Spoiler: picture






https://skatterbencher.com/wp-content/uploads/2021/09/1_pbo_avx-1024x555.png





connected to the bench reports. Stopped watching right there.


----------



## Imprezzion

KedarWolf said:


> Is that b-die RAM, and if it is, your tRFC could be quite a bit lower. It'll help with latency.
> 
> Edit: I think I have the same RAM. I'll show you what works for me, just try it with the 15's etc.
> 
> View attachment 2537376


Yeah this is B-Die. It's a relatively early production 2x16GB DR G.Skill Trident-Z Neo 3600C16 GTZN kit. Bought it way back for my 9900KS and have used it ever since.

I usually run tRFC at 252 with 42 tRC as well. It's running a new TM5 run now with quite optimistically tight subs but it still holds almost an hour in so far.

EDIT: 1 single #10 so far. That's fixable. According to the Google sheet that is probably my 10 tWR being a tad too tight or it doesn't like tRCDWR 8. 

By the way, is there a way to adjust tREFI on AMD? On intel we used to at least double or triple it and sometimes it could even be stable at 65xxx..


----------



## Veii

domdtxdissar said:


> @Veii
> 
> You already had a B2 stepping ? Have you verified its a 0A201204h ? What week ?
> 
> __ https://twitter.com/i/web/status/1470410350562791425


These are my pictures  ~ from HardwareLuxx
Maybe he didn't know and got it that way

But it needs newer SMU to work well
1204a is fine, but 1205 should be required
It works strange on 1203 and lower

Any sample at & beyond BG 2140 is B2
BG 2139 SUS is A0


----------



## Audioboxer

MrHoof said:


> Saw that aswell and here is a video from that guy
> 
> 
> Spoiler: video
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Spoiler: picture
> 
> 
> 
> 
> 
> 
> https://skatterbencher.com/wp-content/uploads/2021/09/1_pbo_avx-1024x555.png
> 
> 
> 
> 
> 
> connected to the bench reports. Stopped watching right there.


I could be wrong, and apologies to the guy if so, but IIRC when I was first starting out OCing my 5950x I believe that channel made a YouTube video overclocking it and just told the viewer to copy their per-core undervolt. As well as made some other BIOS changes that in retrospect with more knowledge were just silly to recommend without context/advising what they do. If it's the channel that does those "super quick guide to OCing this processor" type videos.

Even if I'm wrong I'll say to everyone, probably half the OCing videos on YouTube will be filled with either incorrect information, misguided information or be shared by people who genuinely don't properly know what they're doing but claim to. It's different being a forum poster and making mistakes, I'd say creating guides and content on the likes of YouTube and it's really your duty not to spread incorrect information.

I've fast learned there are only a few YouTubers I will tune into when it comes to discussing hardware/OCing. Outside of that I prefer scouring the internet for forums/social media content from usernames that fast become known for... knowing what they're talking about  This topic is a goldmine for example.


----------



## Audioboxer

Audioboxer said:


> This is why I love you Veii, full of knowledge! I'd never have known that about 1.72v.
> 
> View attachment 2536701
> 
> 
> But it has been fun trying to push tRFC below 100 lol. Going on Antas use multiples of 16 I think this is probably the lowest I'm going to get it. I guess place your bets if I can pass at tRFC 178
> 
> Around 9GB seems to be where I tested to before, but this might have been higher than 1.72v. I can try again. It seemed not bad to me considering most who use maxmem seem to go down to 2~3GB.
> 
> Edit - 178 can't even boot at 1.75v, so the above is as low as it can go using multiples of 16.












Wee bit more madness for a laugh. tRCDRD 11 really cranked up the challenge. 1.75v was not booting. 1.85v was booting fine, but I was struggling at 9GB. Dropping down to 3GB and going up to 1.9v helped. TM5 runs at 3GB are almost pointless, 25 cycles literally finishes in like 1~2 minutes.










tCL 11 would not boot at 1.75v, or 1.85v. 1.9v it booted but struggled to get into Windows. 1.95v it boots into Windows but is clearly really unstable.

Though it's still fun to actually see tCL 11 boot and get into the OS at 3800 lol, even down at 3GB and at 1.95v. I dare say if I was as knowledgeable about memory at high voltages as Veii, mongoled, Buildzoid and everyone else that makes up the memory OCing community I would be changing Rtts, Proc, DrvStr and secondary voltages on my mobo (some that are still on auto), to give myself some more breathing space to potentially pass some light stability testing. Or simply make 1.95v going through VDIMM have a better chance of not freaking out.

But all of this is just fun for me, and I still smiled booting tCL 11 and even tRCDRD 11, cause that's just not something that can could ever be ran on the daily!

Before I came to B-die and began to actually look at memory OCing I had a Corsair Vengeance pro DDR4 kit, and IIRC even trying to boot under tRCDRD 19 with that at 3600~3733, was a total no go  Micron E-die.


----------



## hazium233

Been trying to look at running 4x8GB of G.Skill B-die, two separate kits, that are all on A0 ("non-RGB" sometimes aka "A1"). They are different bins (3200C14 and 3600C15).

I am on 1202 AGESA. For whatever reason the board sets RTT to 7-3-3, and goes to ProcODT 60 sometimes (I think if board had already posted at SPD, otherwise it might do 36.9). I rolled with the 7-3-3 and redid Proc. CAD 24-20-24-24 is what it is setting.

With GDM enabled at 3800 or 3733 I am getting PHYRDL 28 for both dimms on Channel A, but 26 for both on Channel B. At 3600 all four are 26.

ProcODT steps didn't seem to affect that. SOC steps I checked from ~1.1 to 1.2 then went down to 1.06 just to see. Went to old 7-3-1 RTT.

Tried CLDO VDDP 880, 900, 905, 910, 950, "auto" which was "1.1"

Tried RDWR up a step, WRRD up a step. None of that seemed to do anything for 28 on A and 26 on B.

Interestingly, if I just switch GDM off and set 2T then all dimms are at 26. Turn GDM back on and Channel A goes back to 28.

I had subtimings pretty loose since it wasn't rebooting reliably originally, and I wanted to try to rule them out. I might go to something tighter, since I had already tested the 3200C14 to basically Veii's "test timing" CL16 set a long time ago so it should have been ok on VDIMM. I tested these loose timings with a bit of TM5 (extreme1).

I need to check VDDG IOD maybe, I was using old VDDG values from different older configs.

Questions:

I still don't understand when my motherboard decides to do a full train or not when I change settings. I thought it was in part when changing CLDO VDDP and switching SOC voltage modes, but apparently not. For CLDO VDDP to really change correctly, does the power need to click off and back on? I thought answer was yes, but double checking.

Can I actually get reliable data just entering bios and changing ProcODT only to test the steps? I have started to wonder if that doesn't work, and have been changing down MT/s and then back again when I want to look at a new one. Wastes some time.

The big one: why should the RDLs be easier to train to all 26 with GDM off?


----------



## goondam

Veii said:


> Can the proArt even fuel this chip ? The VRM is weak, i wouldn't pull more than 210A from it
> Strangely never have this, but being sure that i everytime disbale MyAsus and Asus Crate
> Both spyware dlls, which inject into system32 after you let it pass the bootloader
> 
> I should call it malware, but it's used for communication with useful programs
> Soo it's just spyware at its best, or bloatware at it's nicest | as they take resources


i learnt the hard way, it can't 😔
my cpu 100% usage is the fault of this mobo, most likely vrm causing problem. tried my friends perfect working 5950x and same issue. that my cpu is not the problem here..

so disappointed in asus skipping out on vrm for this board, would have been perfect otherwise. got my self x570s aorus master.. at least it'll have 700A+ juice for my 5950x


----------



## hazium233

I fixed the subtimings and checked the performance in GDM and it seemed to be decent, but cross checking the sheet I don't know.

One post that I read mentioned it may be ok for four dimms if the dimms within the channel are the same. Most are about two dimm configs, GDM off.

The community sheet is not helpful in this regard since some are too old to show tPHYRDL in ZenTimings, many or most are 2T or 1T, and those that are GDM don't show both channels. Ones with 26 on channel A could have plausibly been 26 across all dimms, or not. Same with 28 on A, it could have just been the channel, or maybe across the board.

One result was a 5950X with 4x8 and 26 on channel A which had similar latency to what I got. Better tRFC, much higher turn around. Since it is dual CCD, that would make me think my config is not correct. 300MHz clock deficit wasn't helping. Or the old SMU / AGESA was a faster. Or I didn't disable enough services to make it comparable.


----------



## mongoled

hazium233 said:


> I fixed the subtimings and checked the performance in GDM and it seemed to be decent, but cross checking the sheet I don't know.
> 
> One post that I read mentioned it may be ok for four dimms if the dimms within the channel are the same. Most are about two dimm configs, GDM off.
> 
> The community sheet is not helpful in this regard since some are too old to show tPHYRDL in ZenTimings, many or most are 2T or 1T, and those that are GDM don't show both channels. Ones with 26 on channel A could have plausibly been 26 across all dimms, or not. Same with 28 on A, it could have just been the channel, or maybe across the board.
> 
> One result was a 5950X with 4x8 and 26 on channel A which had similar latency to what I got. Better tRFC, much higher turn around. Since it is dual CCD, that would make me think my config is not correct. 300MHz clock deficit wasn't helping. Or the old SMU / AGESA was a faster. Or I didn't disable enough services to make it comparable.


Careful when following others results, some are using third party software such as hydra! When you find such outliers best to ignore it or find the person who result it is and ask them

I believe you are taking about @domdtxdissar result


----------



## domdtxdissar

mongoled said:


> Careful when following others results, some are using third party software such as hydra! When you find such outliers best to ignore it or find the person who result it is and ask them
> 
> I believe you are taking about @domdtxdissar result


The only entry i have on that doc is a old 4x8gb setup from 15.03.21 and the screenshot are quite clear in regards what settings was used.. Results were done on pure PBO CO and bios 3003 have ~0.7ns lower latency when running dual ccd's than today's bioses(Hydra wasn't even released back then)

My newer 2x16 setup which is faster in every way got deleted from that document for god knows what reason..
(second batch of screenshot belonging to that 2x16gb entry)

But i dont think its so important anymore, in my view the list got ruined by people using maxmem, others with easymode APU's who think they deserve being first place and some even hiding their WHEA errors with reduced performance in everything other then Aida64 🤣PS: first place are leading with a maxmem (my opinion) bugged out Aida run LOL. No way to get 48ns running 1900fclk @ "CL12", not even CL10 would be close to doing that in the real world.. Just ask @Audioboxer 


>


@hazium233
These are my old 1900fclk, cl14 T1, single ccd ~ST5150mhz, 4x8gb and win10 safemode numbers:








Your bandwidth numbers seems ~fine but your latency is too high... First guess would be bloated windows, what numbers do you get in safemode ?

_edit_
After my rant, i guess it all boils down to me thinking Aida64 is a bad metric to "measure and compare" real performance-numbers with, and lastly, way to easy to manipulate..


----------



## mongoled

domdtxdissar said:


> After my rant, i guess it all boils down to me thinking Aida64 is a bad metric to "measure and compare" real performance-numbers with, and lastly, way to easy to manipulate..


I didnt find that a rant, but very informative



@hazium233
Can you point us to the below config you reference


hazium233 said:


> One result was a 5950X with 4x8 and 26 on channel A which had similar latency to what I got. Better tRFC, much higher turn around. Since it is dual CCD, that would make me think my config is not correct.


----------



## hazium233

@mongoled @domdtxdissar

Should have specified, no it wasn't dom's it was Paddydapro with identical 54.8ns at somewhat similar primaries, but on 5950X. That config shows tPHYRDL 26 on channel A, and is also GDM - Enabled.

It could be Windows, but for some reason I am getting tPHYRDL trained at 28 for both dimms on channel A, and 26 for both on channel B with GDM - Enabled. So I am thinking if latency isn't right, this is part of it. Going 2T it magically changes to all 26 for the four dimms at the same timings.

I have 0 boost override, so the chip only boosts to stock 4.650 right now, so L3 works out to what I think is typical 11.2ns usually. I can try to look at latency in safe mode later today.

I think I will check more CAD and then maybe try IOD to see if I can get all dimms to show 26 in GDM.


----------



## domdtxdissar

hazium233 said:


> @mongoled @domdtxdissar
> 
> Should have specified, no it wasn't dom's it was Paddydapro with identical 54.8ns at somewhat similar primaries, but on 5950X. That config shows tPHYRDL 26 on channel A, and is also GDM - Enabled.
> 
> It could be Windows, but for some reason I am getting tPHYRDL trained at 28 for both dimms on channel A, and 26 for both on channel B with GDM - Enabled. So I am thinking if latency isn't right, this is part of it. Going 2T it magically changes to all 26 for the four dimms at the same timings.
> 
> I have 0 boost override, so the chip only boosts to stock 4.650 right now, so L3 works out to what I think is typical 11.2ns usually. I can try to look at latency in safe mode later today.
> 
> I think I will check more CAD and then maybe try IOD to see if I can get all dimms to show 26 in GDM.


Maybe a stupid question from me as i haven't been following the discussion, but why do you want to run with GDM then? Pure T2 is faster than GDM, especially if you have desync tPHYRDL with gear down mode enabled

T1 > T1 setuptime > T2 > "T1"GDM

Goal should be to stabilize T2 before moving to T1 / T1 setuptime
If your deadset on running with GDM enabled you can try to set tCWL 15(or*14*) and tRDWR+1 to "9" and see if that changes anything.. often forcing different tCL and tCWL changes tPHYRDL..


----------



## MrHoof

domdtxdissar said:


> If your deadset on running with GDM enabled you can try to set tCWL 15(or14) and tRDWR+1 to "9" and see if that changes anything.. often forcing different tCL and tCWL changes tPHYRDL..


tCWL can´t be odd with GDM so 15 wont work.


----------



## Audioboxer

domdtxdissar said:


> The only entry i have on that doc is a old 4x8gb setup from 15.03.21 and the screenshot are quite clear in regards what settings was used.. Results were done on pure PBO CO and bios 3003 have ~0.7ns lower latency when running dual ccd's than today's bioses(Hydra wasn't even released back then)
> 
> My newer 2x16 setup which is faster in every way got deleted from that document for god knows what reason..
> (second batch of screenshot belonging to that 2x16gb entry)
> 
> But i dont think its so important anymore, in my view the list got ruined by people using maxmem, others with easymode APU's who think they deserve being first place and some even hiding their WHEA errors with reduced performance in everything other then Aida64 🤣PS: first place are leading with a maxmem (my opinion) bugged out Aida run LOL. No way to get 48ns running 1900fclk @ "CL12", not even CL10 would be close to doing that in the real world.. Just ask @Audioboxer
> 
> @hazium233
> These are my old 1900fclk, cl14 T1, single ccd ~ST5150mhz, 4x8gb and win10 safemode numbers:
> View attachment 2537683
> 
> Your bandwidth numbers seems ~fine but your latency is too high... First guess would be bloated windows, what numbers do you get in safemode ?
> 
> _edit_
> After my rant, i guess it all boils down to me thinking Aida64 is a bad metric to "measure and compare" real performance-numbers with, and lastly, way to easy to manipulate..


I like how I've been stumbling around with maxmem shouting "I know this isn't daily guys but it's soooo funnnnn!" and all the experienced OCers like you and others are just like "Guys, just let him has his fun, it'll pass" 

And yeah, well, it did. Back to the normal daily profile lol.


----------



## domdtxdissar

MrHoof said:


> tCWL can´t be odd with GDM so 15 wont work.


You are of course correct, been so long ago since using GDM that i had forgotten odd number rule /faceplam 😳

tCWL14 it is then and maybe tRDWR+2 and alittle vdimm if needed


----------



## PJVol

domdtxdissar said:


> in my view the list got ruined by people using maxmem, others with easymode APU's who think they deserve being first place and some even hiding their WHEA errors with reduced performance in everything other then Aida64


In case you haven't noticed yet, the APU results have been moved to a its own tab for a couple of weeks already (since the doc owner's return from the vacation), that i agree was reasonable.
Btw, it'd be nice if you could make it clear what was meant under the “easymode APU's”, and, perhaps, point out the results that, in your opinion, do not deserve to be there (hidden whea's or whatever).
Thanks.


----------



## domdtxdissar

PJVol said:


> In case you haven't noticed yet, the APU results have been moved to a its own tab for a couple of weeks already (since the doc owner's return from the vacation), that i agree was reasonable.
> Btw, it'd be nice if you could make it clear what was meant under the “easymode APU's”, and, perhaps, point out the results that, in your opinion, do not deserve to be there (hidden whea's or whatever).
> Thanks.





> APU results have been moved to a its own tab for a couple of weeks already, that i agree was reasonable


Strange, that's not how i remember it.. I thought you were against the very motion of your APU results getting moved to a separate list, "arguing" against it both there and in the doc's comment section ?


PJVol said:


> @domdtxdissar
> I saw you complained to a Zen RamOC Leaderboards owner regarding "diluting" scoreboard with the APU results.
> Would it be fair then to complain about results from the 5600X 2xCCD owners as well, since 2100 stable FCLK OC is only possible because of their unique architecture?
> Does anyone else here have an opinion on this?


Did i misunderstand your intent ? (think you had more posts about it also, but don't want to spend time digging after it as it don't matter)



> it'd be nice if you could make it clear what was meant under the “easymode APU's”


When i was building a simple web-browser machine with leftover memory to my parents i spent like 10min in the bios and got this as a results:








I found that very easymode compared to a tweaking a regular 5000 series Zen3 cpu with mem controller on a seperate IO-die.
And that's the reason why i didn't even upload it to the Zen RamOC Leaderboards.

I think it would be in no way or shape fair for me to take @Veii's #2 spot (48.5ns 5600x) or anyone else's ranking on the leaderboard, something they had spent many months working on, with countless hours bruteforcing settings, with me coming with a different architecture (APU), having spent ridiculously little time and effort tweaking to achieve that 48.3ns, and take "their spot".



> not deserve to be there (hidden whea's or whatever)


Dont think i need to comment on top ranking and I kinda don't want to accuse anyone at all, but if i just have to pick a few results i find questionable:
citizenasdf's 51ns @ dual ccd 5950x running 2133:4267 on *AGESA 1.2.0.2*
wirx's 51.2ns @ dual ccd 5950x running 2033:4067 on 4x8gb on *AGESA 1.2.0.0*

imgur.com don't seem to be working for me atm, but i know a few of the other earlier entries don't show WHEA tab in hwinfo at all. (And if my memory is correct, some even said/admitted in this very thread some 6-9 months ago that their results were only for "show" and had heavy throttling in every real bench they tried to run)
Some other early guys on the leaderboard have only 20min TestMem5 run as proof of stability which i also think is to little... And some of the results are too XOC for my taste to be on that sheet.

What of my statements above do you object to ? Thanks


----------



## hazium233

domdtxdissar said:


> Maybe a stupid question from me as i haven't been following the discussion, but why do you want to run with GDM then? Pure T2 is faster than GDM, especially if you have desync tPHYRDL with gear down mode enabled
> 
> T1 > T1 setuptime > T2 > "T1"GDM
> 
> Goal should be to stabilize T2 before moving to T1 / T1 setuptime
> If your deadset on running with GDM enabled you can try to set tCWL 15(or*14*) and tRDWR+1 to "9" and see if that changes anything.. often forcing different tCL and tCWL changes tPHYRDL..


Mostly now I want to figure out what is going on since I thought it is weird that it seemingly trains easier with 2T than GDM. 

I also thought your real world benchmarks from a while back were showing 2T and GDM were margin of error type differences? Maybe I remember incorrectly.


----------



## hazium233

Another thing that I forgot to ask earlier.

Those that tested 2x8 vs 4x8 at same settings, what was the latency penalty you saw for two ranks per channel?


----------



## Veii

domdtxdissar said:


> I think it would be in no way or shape fair for me to take @Veii's #2 spot (48.5ns 5600x) or anyone else's ranking on the leaderboard, something they had spent many months working on, with countless hours bruteforcing settings, with me coming with a different architecture (APU), having spent ridiculously little time and effort tweaking to achieve that 48.3ns, and take "their spot".


mmm, up to 2067 was "easy" i could say
i wish soo much not to be on top 1

And i'm honestly quite sad, how AMD and the VanguardTeam around them handles Vermeer
Maybe many of the accusations would be resolved with 1.2.0.5 which they take around 3 months, for now
* which i am nearly confident it will be broken again ~ but let's see

I'm very sad, that the team rather decided to ignore the issue and resolve it with a purely new gen
While somewhy not having it resolved on B2
That was their option to resolve it, they could've and it was realistic
But then, they appear to still title it as beyond 1900 FCLK "issue" and very low priority
This is sad.
I really don't deserve that place up there, as memory timings are very lose. Just it is what this little kit can do ~ it's weak and i just lucky with a non issue sample

This top place guy, i got to know his mentality on the RX XOC "fun" we could spend
One of the people who started to cause a 3D Mark drama, but it's just his mentality beating every score with any method possible.
He probably deserves the top place a bit more then me, he fights stronger for it.
I ~ on the other hand don't do much more about this result. It's "fine", it's "usable" and it took too much time taming this not so good PCB of dimms
* probably far more time than taming Vermeer, i'd say more than double the time, if not tripple

I'm really more sad about every other user, who i'm sure can easily run 2000 FCLK, but can't do much about it ~ as AMD decided to ignore the snowballing DPM issue
* now that USB, PCI, PCH don't cause issues anymore. Damage prevention & not innovation


----------



## domdtxdissar

hazium233 said:


> Mostly now I want to figure out what is going on since I thought it is weird that it seemingly trains easier with 2T than GDM.
> 
> I also thought your real world benchmarks from a while back were showing 2T and GDM were margin of error type differences? Maybe I remember incorrectly.


Yeah in the grand scheme of thing, the performance difference T2 and GDM is pretty miniscule.. But faster is faster right ? If you can get something like lets say 3% faster results with T2, why not run it ?  Later when you have stabilized T2, maybe you can get 5% faster when running T1 over GDM ?
PS: and like ive said before, CPU clockspeed is king in pretty much every bench.



hazium233 said:


> Another thing that I forgot to ask earlier.
> Those that tested 2x8 vs 4x8 at same settings, what was the latency penalty you saw for two ranks per channel?


Practically there should be no latency difference between 2x8GB and 4x8GB keeping all the other settings the same.. (same with 2x16gb)

The limiting factor with these 32gigs set are normally that its harder to run them, as in strain on the memory controller increase with memory size.
And as a result it can be harder to achieve the same mem clockspeed as with 2x8gb. 

I also think singlerank b-die can take more vdimm and run tighter timings then dualrank b-die on "average", but have to little expertise with singlerank to say anything concrete about it.


----------



## ManniX-ITA

domdtxdissar said:


> Dont think i need to comment on top ranking and I kinda don't want to accuse anyone at all, but if i just have to pick a few results i find questionable:
> citizenasdf's 51ns @ dual ccd 5950x running 2133:4267 on *AGESA 1.2.0.2*
> wirx's 51.2ns @ dual ccd 5950x running 2033:4067 on 4x8gb on *AGESA 1.2.0.0*
> 
> imgur.com don't seem to be working for me atm, but i know a few of the other earlier entries don't show WHEA tab in hwinfo at all. (And if my memory is correct, some even said/admitted in this very thread some 6-9 months ago that their results were only for "show" and had heavy throttling in every real bench they tried to run)


I think being "WHEA free" is completely pointless; there were questionable results long before I had released WHEA Suppressor.
There are many ways to block reporting, eg. install Win 10 r1903 and upgrade.
It's too easy to hide and too complex to be sure there are no performance regressions.
Memory it's hardly a factor in WHEA or not WHEA. 
You can have the same exact configuration of someone and get them or not. Or be able to POST or not.
As you pointed out it's easy to spot the results which are obviously not WHEA free.
But still doesn't mean it's not a daily config; I'm not "WHEA free" with no performance regressions and use it daily.
Don't want to speak for others but a 5950X at 2100/2133 MHz there's a 99% chances is only usable for nothing more than a TM5 run 



domdtxdissar said:


> Some other early guys on the leaderboard have only 20min TestMem5 run as proof of stability which i also think is to little...


I agree, a requirement for a longer TM5 proof would be beneficial.
This really matters.



domdtxdissar said:


> And some of the results are too XOC for my taste to be on that sheet.


Yes indeed. 
But, as always, I'm not much in favor to split results over multiple sheets.
Maybe a new column with XOC or Daily tag?
There's always copy & filtering the sheet which is what everyone should do.
But even there we have to expect people declaring 1.95V profiles as daily...
And Maxmem as well should have its own column.


----------



## Veii

ManniX-ITA said:


> But even there we have to expect people declaring 1.95V profiles as daily...


BZ declared 1.55-1.6 as daily ~ to what i remember
I run 1.65-1.68v
People won't take you serious, likely

Also new thing:
New annoying thing








And even without DF_C-States and without Hydra, this "too low" enforced powerstate causes overboost
It's not fixable with the powerplan
Else it behaves so far the best on "energy efficient" instead "balanced" or "high performance"
This spike pushed Write Bandwidth beyond theoretical max, but has nothing to do with Aida.
Also seen 5.5ghz effective freq spikes on Hydra








EDIT:
313 ACPI should have been near a 10+ghz spike, as 4.85 was the 132-135 mark
It's 3 times P0 state, which is 3.65Ghz = 100% ACPI


----------



## Akex

ManniX-ITA said:


> I think being "WHEA free" is completely pointless; there were questionable results long before I had released WHEA Suppressor.
> There are many ways to block reporting, eg. install Win 10 r1903 and upgrade.
> It's too easy to hide and too complex to be sure there are no performance regressions.
> Memory it's hardly a factor in WHEA or not WHEA.
> You can have the same exact configuration of someone and get them or not. Or be able to POST or not.
> As you pointed out it's easy to spot the results which are obviously not WHEA free.
> But still doesn't mean it's not a daily config; I'm not "WHEA free" with no performance regressions and use it daily.
> Don't want to speak for others but a 5950X at 2100/2133 MHz there's a 99% chances is only usable for nothing more than a TM5 run
> 
> 
> 
> I agree, a requirement for a longer TM5 proof would be beneficial.
> This really matters.
> 
> 
> 
> Yes indeed.
> But, as always, I'm not much in favor to split results over multiple sheets.
> Maybe a new column with XOC or Daily tag?
> There's always copy & filtering the sheet which is what everyone should do.
> But even there we have to expect people declaring 1.95V profiles as daily...
> And Maxmem as well should have its own column.


technically, don't WHEAs lead to a decrease in performance? There is something that escapes me regarding WHEA, for a 24-hour use isn't that a risk?

For my part beyond 1900Mhz I have WHEA and I do not know how to interpret it because for me WHEA = stability problem = correction of the information somewhere.


----------



## ManniX-ITA

Akex said:


> technically, don't WHEAs lead to a decrease in performance? There is something that escapes me regarding WHEA, for a 24-hour use isn't that a risk?


You can check the WHEAService thread in my signature.

WHEA can lead to decrease but not necessarily.
If it's about a wrong/unexpected message sent over the bus it just consumes a very tiny fraction of the enormous available bandwidth.

Even if it's a corrected error you get performance degradation only when the benefits are outweighed.
Eg. if you get a 5% performance boost and a 0.5% performance degradation you are still positive for 4.5%.

From my experience, my advice is: run at FCLK 1900 if you are not 100% sure what you are doing.
If you get WHEAs, it's really hard to get it stable and without performance regressions, much more with 2 CCDs.
You need to use higher voltages all over and manage the increased temperatures.
There's a little advantage but it really matters only with extremely bandwidth hungry workloads.
It's a lot of fun indeed but it's safer and easier to run FCLK 1900 
You can get similar/better performances for "normal" workloads with CL13 at 1T with setup times.


----------



## mongoled

hazium233 said:


> Another thing that I forgot to ask earlier.
> 
> Those that tested 2x8 vs 4x8 at same settings, what was the latency penalty you saw for two ranks per channel?


No difference in my testing, just like what Dom said



ManniX-ITA said:


> eg. install Win 10 r1903 and upgrade.


I like the "bug" that after CMOS reset, load high FCLK config, the first boot is WHEA 19 free without using a supressor

😍



Akex said:


> technically, don't WHEAs lead to a decrease in performance?


Its not the WHEA as per se but whats triggering the WHEA and I am guess you are talking about 19s.

On a regular ATX board it needs a lot of tweaking not to loose performance and for most its not possible...


----------



## PJVol

domdtxdissar said:


> Did i misunderstand your intent?


Not that I was against, rather would like to point out that the table should not be entitled Zen3, otherwise there's nothing to complain, since Zen3 is the name of the arch gen. Then I wanted to know people's opinion here on the matter, nothing more.
But 2xCCD 5600X was mentioned specifically in response to your complain about mixing dt/mobile chips results



domdtxdissar said:


> I think it would be in no way or shape fair for me to take @Veii's #2 spot (48.5ns 5600x) or anyone else's ranking on the leaderboard, something they had spent many months working on, with countless hours bruteforcing settings,


I can tell you, that the user I know well from the local forum, with now 4th result (KMS) had 2xCCD 5600X as well, and it took him no more than a couple of days to achieve that result (I know two more people with the same "unique" processor having little to no problem running up to 2100 FCLK).
So I wouldn't oversimplify when comparing the efforts needed to OC memory on these Zen3 platforms (APU for example has its own pitfalls, which doesn't make it much easier in the end), and of course can't agree more, that the vanilla (ordinary) Vermeer is the most stubborn one in this regard.



Akex said:


> technically, don't WHEAs lead to a decrease in performance?


As many have pointed out, the main reason against 1900+ FCLK not the WHEA 19/20 itself. The underlying arch issues coupled with the some AGESA restrictions, makes CPU behave quite unpredictable. The most significant performance hit with 1900+ can be observed in a intensive Vector/FMU workloads, and where the EDC manager starts clock-gating some domains, supposedly CCLK and CCLKL3 at least.
I still stand by it's not being an "issue" but the hardware limit for the current generation of chiplet based Zen architecture.


----------



## hazium233

domdtxdissar said:


> Yeah in the grand scheme of thing, the performance difference T2 and GDM is pretty miniscule.. But faster is faster right ? If you can get something like lets say 3% faster results with T2, why not run it ?  Later when you have stabilized T2, maybe you can get 5% faster when running T1 over GDM ?
> PS: and like ive said before, CPU clockspeed is king in pretty much every bench.
> 
> 
> Practically there should be no latency difference between 2x8GB and 4x8GB keeping all the other settings the same.. (same with 2x16gb)
> 
> The limiting factor with these 32gigs set are normally that its harder to run them, as in strain on the memory controller increase with memory size.
> And as a result it can be harder to achieve the same mem clockspeed as with 2x8gb.
> 
> I also think singlerank b-die can take more vdimm and run tighter timings then dualrank b-die on "average", but have to little expertise with singlerank to say anything concrete about it.





mongoled said:


> No difference in my testing, just like what Dom said


That is similar to what I am actually seeing then. The two FlareX by themselves at 3800 16-16-16 with GDM was close, although Windows, audio driver and Nvidia driver are different since then. Also that config had a little looser tFAW but otherwise basically the same and was 54.7ns.

I asked because in other circles it was being said that 4x8GB was 1ns or so worse at same settings.

...

I did take a brief look at Normal Windows, Diagnostic and Safe mode:



Spoiler
































I haven't done much in Safe Mode, since I thought I had read boosting didn't work correctly there and Diagnostic Start was better. Minimum was 54.4 in Safe, or 54.6 in Diagnositc. But in Safe mode there was an oddity with the write bandwidth where it was either 30420 or 30382. Click back to back or whatever and it was basically either one or the other.

In the summer I sometimes saw too high write when testing VDDG steps, so could be those old values I plugged in don't work correctly for this config. Or is this some known quirk with Safe Mode?

...

Otherwise I looked at bumping CL to 18 keeping CWL at 16, and adjusting RDWR. Still trained 28 on A 26 on B for the tPHYRDL.

Changed tRCD and tRP to 17 each, adjusted tRAS and tRC and still same.

Bumped tRDWR and tWRRD to 18 and 7 like in some configs on the sheet, and still same.

CKE to Auto - no change

From my old results, one dimm per channel whether SR or DR would train 28 on A and B with GDM.

At 2T my SR and DR B-die were 26, but my old 2x16 DR Rev E might have been 28-28 (I wasn't savvy enough to look at both channels back then on Rev E, and screenshot shows 28 on A). I pulled the four dimms and put the 2x16 3466 set back in to recheck and it was like I remembered. 28/28 GDM. 26/26 at 2T 16-17-16-32-48. Played around a little to see if I could get it to do 26/26 with GDM.

Anyway if anybody with four dimms wants to look at GDM enabled at 3733 or 3800 and see what their tPHYRDL do may be interesting.

Here is how I have been testing the four dimms, maybe I need to swap them all around and see what happens:

A1 - weaker 36C15
A2 - weaker 32C14
B1 - better 36c15
B2 - better 32c14

"Better" vs "weaker" here was tested from booting something like 14-14-14 3200 "safe" down in voltage until it couldn't post or run some stability in linux at all.


----------



## Imprezzion

Made some progress. Kind of. I had a few errors in 25 cycles of 1usmus TM5 which I fixed now with a bit more vDIMM (1.5450 to 1.560) and it completed the tests without any errors and no meaningful temperature increase. Just about touched 43c on the hotter dimm.

So. I went and tried to get my primaries to run straight 14's in stead of 14-15-15 which it would not do at all, it boots but is woefully unstable. So I tried 14-14-15, errors, tried 14-15-14, totally fine. No idea how big if any the benefit is of running unsynced primaries at 14-15-14-28-252-2T but it did pass lol.

tWR 10 + tRTP 5 works but it needed the extra vDIMM to be stable otherwise it would throw a error #2 or #10 after ~15 cycles.

So it seems like the best I'm going to get out of this kit is 3800 14-15-14 which is fine I guess. Would've liked better or at least CAS14 at a better voltage but a low bin 3600C16 kit is probably not going to do any better.

I might be able to tweak a sub timing here and there but I'm really close to the max possible.

4000 is a no-go, this chip will not for the life of it run 2K FCLK without WHEA's. It can do 3866 1:1 1933 but that messes with the timings too much. 3800 is more efficient.


----------



## Akex

I need some information folks regarding RTT.
Basic on my kit, the bios configures 7/3/1 for 4x8 SR.
From what I understood from information from @Veii when I OC an EDIE Micron kit on a 2400G APU, reducing RTT Park relieves RAM. So I spent RTT Park RZQ/1 on RZQ/3 then RZQ/5 until I was sure to be stable. I noticed a drop in temperature on the 4 DIMMs of plus or minus 6 to 7 ° C.
For the moment it's running on stable 7/3/5, I first try to be certain that the 3800Mhz frequency is rock stable, then I would switch to GDM OFF then I would end with the timings. But the question is, reducing RTT Park while remaining stable is the right thing to do? When I go to try GDM OFF, is it possible that the RTTs may need to be reconfigured?
I would like some simple explanation on RTT to be sure I understood what I have been reading for a few years now.


----------



## hazium233

@Akex

The most common advice here was to start at 2T - GDM disabled to look for the RTT, then go back to GDM later if you wanted.

I am pretty sure what the auto values are depend in part on the bios version or SMU, or maybe the motherboard vendors also play with them. My motherboard seems to be doing 7-3-3 on SMU 56.50.00, AGESA ComboPI v2 1202. MSI B550 Gaming Edge Wifi. I do not know how much effort goes into these values by AMD or the vendor.

Sadly I am too much of an amateur to know a good way to get through the 336 permutations quickly. A large number won't boot, or then load into OS, so that cuts down a bit. Can try to assume that four dimm most likely needs RTT Wr of some value, so that takes out some. Probably realistically there are only a few values for each worth testing, except maybe for Park. Also IIRC per state table since Nom v Park depends on ODT pin, making them the same value doesn't seem like it should be different than Nom disabled if you have a value for all three.

If you make the config slightly unstable then you can try to look at error rate with the different RTT.


----------



## hazium233

Got sidetracked yesterday, but could at least get started on 2T before I fell asleep. I got a high Write bandwidth the first time I ran AIDA (~30405 or something). I was hoping maybe TM5 would just error, but it didn't have the decency to do that. Nor did 30min of OCCT large give an error or WHEA.

880 VDDP, 880 CCD, 1000 IOD, 1.1V SOC 36.9 7-3-3 30-20-30-20

I should have probably been looking in safe or diagnostic at some values and latency consistency, but to some extent I also just wanted to see what would happen with CCD at 880.

Read an old post that too high write could be subtiming like WTR_, although I think mine aren't extreme. Although maybe WTRS 4 is a little low for these here, I will look again at 5 maybe.

I am pretty sure the motherboard prefers RDWR 9, and that might be an AGESA thing for four dimm and CL=CWL, not sure. 8 passes pitiful testing, but maybe that is part of the write issue.

Spread spectrum was supposed to be disabled, I don't know how well that works. PLL is on default, but reads as VTT 1.834 on this motherboard (and is always offset ~35mV from set), so I don't know if MSI is really overvolting it or more likely the sensor reads this. Maybe I need to look at the steps again, but before I thought it did nothing except make things worse if > 1.84 here.


----------



## Reaxer

I'm noticing that when tRDWR is on auto, it's always one higher on my stick in A2 than the one on B2. Is that normal?
Whatever the other settings are doesn't seem to matter.


----------



## domdtxdissar

If anyone want to test and compare the performance of their memory and cpu settings/OC, @storm-chaser is hosting a friendly y-cruncher competition over at the benchmark part of this forum 

Nothing serious(we have hwbot for that), its just for fun


----------



## Akex

hazium233 said:


> @Akex
> 
> The most common advice here was to start at 2T - GDM disabled to look for the RTT, then go back to GDM later if you wanted.
> 
> I am pretty sure what the auto values are depend in part on the bios version or SMU, or maybe the motherboard vendors also play with them. My motherboard seems to be doing 7-3-3 on SMU 56.50.00, AGESA ComboPI v2 1202. MSI B550 Gaming Edge Wifi. I do not know how much effort goes into these values by AMD or the vendor.
> 
> Sadly I am too much of an amateur to know a good way to get through the 336 permutations quickly. A large number won't boot, or then load into OS, so that cuts down a bit. Can try to assume that four dimm most likely needs RTT Wr of some value, so that takes out some. Probably realistically there are only a few values for each worth testing, except maybe for Park. Also IIRC per state table since Nom v Park depends on ODT pin, making them the same value doesn't seem like it should be different than Nom disabled if you have a value for all three.
> 
> If you make the config slightly unstable then you can try to look at error rate with the different RTT.


Obviously the configuration of my RTTs is perfect, at least in terms of stability. Having then passed GDM OFF 2T did nothing wrong, everyone is still very stable.
For the moment I have done: tCL - tRCD - tRP - tRAS - tRC - tRRDS / L - tFAW - tWTRS / L - tWR - tRTP.
So I have all the rest to do, tRFC - SCL - tRDWR - tWRRD etc etc.
Validated TM5 6h









However, I noticed in passing tCL 13 that tPHYRDL on channel B went to 28 while on tCL 14 I have 26/26.
I saw several intervention on this subject but I did not remember if a workaround exists or that I could try.
If anyone has any information on it.


----------



## Imprezzion

Akex said:


> Obviously the configuration of my RTTs is perfect, at least in terms of stability. Having then passed GDM OFF 2T did nothing wrong, everyone is still very stable.
> For the moment I have done: tCL - tRCD - tRP - tRAS - tRC - tRRDS / L - tFAW - tWTRS / L - tWR - tRTP.
> So I have all the rest to do, tRFC - SCL - tRDWR - tWRRD etc etc.
> Validated TM5 6h
> 
> View attachment 2538133
> 
> 
> However, I noticed in passing tCL 13 that tPHYRDL on channel B went to 28 while on tCL 14 I have 26/26.
> I saw several intervention on this subject but I did not remember if a workaround exists or that I could try.
> If anyone has any information on it.


I can't even get close to those RTT or ProcODT or clkdrvstr values and I have basically the same board and similar ram and CPU. I do have the same issue that odd tCL gives me 26/28 as well on 15 or 13 but 14 is 26/26 every time. Which bios version are you on? 2423?


----------



## Akex

Imprezzion said:


> I can't even get close to those RTT or ProcODT or clkdrvstr values and I have basically the same board and similar ram and CPU. I do have the same issue that odd tCL gives me 26/28 as well on 15 or 13 but 14 is 26/26 every time. Which bios version are you on? 2423?


I will provide you later with my thaiphoon so that you can compare PCB so be aware that vDIMM = 1.66v. tWTRL 10 my request + 0.02v vs tWTRL 14 @ 1.64v. Having said that I did some research on tWTRL and I came across an old post from veii that says best for tWTRL = tRRDS * 2 if I understood correctly > [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

For the bios I'm on 2404, you can see it on the Zentiming screenshots

Edit: I put myself bad luck, tWTRL 10 gives me an error 6 in the end, I go to 12 for 1.64v and go for 80 TM5 cycles.

Thaiphoon Report > https://cdn.discordapp.com/attachme...1726608279216168/G.Skill_F4-3200C14-8GVK.html


----------



## Imprezzion

Akex said:


> I will provide you later with my thaiphoon so that you can compare PCB so be aware that vDIMM = 1.66v. tWTRL 10 my request + 0.02v vs tWTRL 14 @ 1.64v. Having said that I did some research on tWTRL and I came across an old post from veii that says best for tWTRL = tRRDS * 2 if I understood correctly > [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> For the bios I'm on 2404, you can see it on the Zentiming screenshots
> 
> Edit: I put myself bad luck, tWTRL 10 gives me an error 6 in the end, I go to 12 for 1.64v and go for 80 TM5 cycles.
> 
> Thaiphoon Report > https://cdn.discordapp.com/attachme...1726608279216168/G.Skill_F4-3200C14-8GVK.html
> 
> View attachment 2538158


Mine are Trident-Z Neo so different PCB and a worse bin (3600 16-16-16-36) so I need much more clkdrv to make it run. I'm not at home now, doing some IT stuff for a customer on the weekend, and it's running TM5 1usmus 25 cycles now. When I get back I'll hopefully have no errors lol.

tWR 10 needed + 0.0250 for vDIMM, I'm on 1.5650v now for 14-15-14-28-42-252-2T.

EDIT: So close. Only 1 single error #10 quite far into the tests.


----------



## Luggage

Luggage said:


> View attachment 2526236
> 
> 
> I guess so.
> 
> And now you made me order a ram-block. tsk tsk tsk


edit: 3 months later…


http://imgur.com/a/nY1CmU4


I know about logistics in the pandemic but did they have to send it by donkey cart?


----------



## nick name

Imprezzion said:


> Mine are Trident-Z Neo so different PCB and a worse bin (3600 16-16-16-36) so I need much more clkdrv to make it run. I'm not at home now, doing some IT stuff for a customer on the weekend, and it's running TM5 1usmus 25 cycles now. When I get back I'll hopefully have no errors lol.
> 
> tWR 10 needed + 0.0250 for vDIMM, I'm on 1.5650v now for 14-15-14-28-42-252-2T.
> 
> EDIT: So close. Only 1 single error #10 quite far into the tests.
> 
> View attachment 2538182


First, I would change tWTRS to 4. I always get an error when I forget to increase it from 3. Then I think you can run tRDRDSCL and tWRWRSCL at 3. tRTP to 6 (or 8 if needed). tWRRD to 2.


----------



## Veii

Luggage said:


> http://imgur.com/a/nY1CmU4
> 
> 
> I know about logistics in the pandemic but did they have to send it by donkey cart?


How long did you wait ?
Might need to order couple of watercooling components from them
Actually quite a big order


----------



## Luggage

Veii said:


> How long did you wait ?
> Might need to order couple of watercooling components from them
> Actually quite a big order


Original post 25th September... not any official site just the cheapest i could find on AliExpress... "AegirX MOD Store"


----------



## Veii

Luggage said:


> Original post 25th September... not any official site just the cheapest i could find on AliExpress... "AegirX MOD Store"


Aah ok
Well Aliexpress does indeed use free donkey shipping 
Nah, was afraid thanks to chinese or hongkong holiday ~ that shipping is delayed

Need couple frosted tubes, an OC Formula waterblock from Bykski and couple of fittings from barrow and aquatouch (early bitspower)


----------



## Imprezzion

nick name said:


> First, I would change tWTRS to 4. I always get an error when I forget to increase it from 3. Then I think you can run tRDRDSCL and tWRWRSCL at 3. tRTP to 6 (or 8 if needed). tWRRD to 2.


Did the changes, no POST. Hangs on 5A code. I never got SCL at 3 to POST before so probably that. Or twrrd.

Better yet, even after a CMOS CLR and full PSU power switch off reset it will not boot anymore. Completely dead with 5A code and VGA LED. This looks like I can reflash the BIOS again with USB flashback... If it didn't break / brick something completely.

EDIT: oh wow I did not expect this.. it POSTed once after another CLR CMOS and removing a stick of RAM to force it to say new memory installed and thus boot to safe mode for the BIOS, I tried to boot windows, it BSOD, then I put the other stick back in and now it's just stuck on code 22, it seems something just either died (CPU, ram or board) or the BIOS is so broken and corrupt now I have to reflash... Let me put a monitor on my server and make a BIOS USB flashback stick... If something died that would've been quite unexpected and short lived. This board and CPU are barely a month old.. the RAM is way older but I have no spare DDR4 to test at the moment..

EDIT2: yeah no she's gone. After a successful BIOS flashback it cycles POST codes a few times only to hang on 5A again. Which is a CPU code. Looks like the CPU is done for. I can't easily get my hands on another AMD chip on Sunday as none of my mates still run AMD.. maybe one but it's a 3700X.. I can loan that maybe? Or test my chip in his board. But it looks a lot like something just died. 

I will try to re seat the chip, the waterblock is easy enough to pull off without draining the loop so..


----------



## Audioboxer

Luggage said:


> http://imgur.com/a/nY1CmU4
> 
> 
> I know about logistics in the pandemic but did they have to send it by donkey cart?


Interesting thing about Barrow over Bykski is Barrow has fins, so in theory should be better cooling.

Given I run 4 rads and 3 blocks off 1 D5 I'll say restriction wise it might have been best I went Bykski. But I would be interested to see if Barrow can be a bit cooler!

When my max temps hit like 30-32 degrees under a heavy load I guess it doesn't matter too much. For people not worried about restrictiveness I'd recommend buying the Barrow over Bykski.

Also anyone doing DIMM watercooling, remember to thermal paste the top of the heat spreaders! Just in case you forget as not many people are used to watercooling memory lol.


----------



## Luggage

Audioboxer said:


> Interesting thing about Barrow over Bykski is Barrow has fins, so in theory should be better cooling.
> 
> Given I run 4 rads and 3 blocks off 1 D5 I'll say restriction wise it might have been best I went Bykski. But I would be interested to see if Barrow can be a bit cooler!
> 
> When my max temps hit like 30-32 degrees under a heavy load I guess it doesn't matter too much. For people not worried about restrictiveness I'd recommend buying the Barrow over Bykski.
> 
> Also anyone doing DIMM watercooling, remember to thermal paste the top of the heat spreaders! Just in case you forget as not many people are used to watercooling memory lol.


Well to add more hurt to my nerves I just ordered a Aquacomputer flow next, out of stock… so until that shows up I’m not redoing any loop.


----------



## Imprezzion

It's gone. Re seat CPU no difference, different GPU no difference, 1 DIMM in any slot cycles post code "36" and 2 DIMM's in any slots cycles "5A" with a white VGA LED, did a clean boot with no m.2, SATA, USB or anything connected literally 1 stick of ram, CPU, a GTX 760 and my keyboard. Still the exact same. This CPU is 99% sure dead.

EDIT: there's a bnib 5900x locally like 20 minutes from me for sale. Gonna try to pick that up tomorrow. I would've gone straight back to Intel (10900k/11900k/12900k DDR4) but my block is AMD only...


----------



## SpeedyIV

Imprezzion said:


> It's gone. Re seat CPU no difference, different GPU no difference, 1 DIMM in any slot cycles post code "36" and 2 DIMM's in any slots cycles "5A" with a white VGA LED, did a clean boot with no m.2, SATA, USB or anything connected literally 1 stick of ram, CPU, a GTX 760 and my keyboard. Still the exact same. This CPU is 99% sure dead.
> 
> EDIT: there's a bnib 5900x locally like 20 minutes from me for sale. Gonna try to pick that up tomorrow. I would've gone straight back to Intel (10900k/11900k/12900k DDR4) but my block is AMD only...


So your CPU just decided to die because you were working on overclocking your RAM? I have never heard of that happening before. Boot loops and BSOD's sure, but I don't see how a few too tight RAM timings would kill the CPU. Have you tried re-flashing the BIOS from the BIOS flash USB port? I think you can even do it with the CPU out of the socket. Maybe try that then reinstall the CPU? Good luck, whatever you do.


----------



## Veii

Imprezzion said:


> EDIT2: yeah no she's gone. After a successful BIOS flashback it cycles POST codes a few times only to hang on 5A again. Which is a CPU code. Looks like the CPU is done for. I can't easily get my hands on another AMD chip on Sunday as none of my mates still run AMD.. maybe one but it's a 3700X.. I can loan that maybe? Or test my chip in his board. But it looks a lot like something just died.
> 
> 
> SpeedyIV said:
> 
> 
> 
> So your CPU just decided to die because you were working on overclocking your RAM? I have never heard of that happening before. Boot loops and BSOD's sure, but I don't see how a few too tight RAM timings would kill the CPU. Have you tried re-flashing the BIOS from the BIOS flash USB port? I think you can even do it with the CPU out of the socket. Maybe try that then reinstall the CPU? Good luck, whatever you do.
Click to expand...

I would not give it up yet
This happens by 2 reasons:

actual oxidation (but i don't think you've pushed that high)
bugged out PSP-FW

In order to repair the 2nd, you'll need to board swap and make big AGESA jumps
That forces a reflash , also detected as "new CPU Installed"
Sometimes it can happen that TPM module also breaks - which after wiping, puts the bios back to chinese
I've had this in specific once, but the above twice
It messed up my X370 taichi and my 1700X

Worked then on an X570 board
But doesn't work on the Taichi again
(this was all far back before any ROM Armor got included or any PCH restrictions)

Usually the way to try and repair it, is SPI flash to the earlierst version - and keep the CPU outside
Soo after time it detects this as a new CPU
The issue can be a combination of both, but mostly it's bugged FW related

I can offer two options,
Put it into a completely different board (maybe even different chipset, with a friends ram)
disable and activate TPM and later Bios-CMOS reset and potentially upgrade the bios
Then downgrade your personal board to the earliest version and put it back
PSP-FW will detect a CPU swap and will detect and misscompatibility, soo reflash

I wish you would've had an whea-sensor report log before, but doing so also changes the amount of sensors reported
Once started with 4/5, then changed to 9/10, and now it's back to 10 out of 10 sensors reporting
2nd offer i can give, is to send it over and you'll get it within a week (EU)
I wouldn't mind checking on it (the same way above), as long as you pay the shipping (usually 10-12€)
~ but that's one time, i wouldn't do it often & you should definitely try it with a local friend first
I can not give you any guarantee of trust here, but could check on it once ~ if you agree

Yes, find a friend
Try their memory and Board combination ~ likely even cooler
Keep the CPU out of the board for a bit of time (inside there is an ARM chip, it takes a bit for the whole unit to lose charge)
_* if you don't see the post message "new CPU installed", then it wasn't long time enough outside_
and flash your board to AGESA 1.0.8.0 or the earliest near 1.1.0.0 you can find
Might also buy a WD Green or CRC Red. Hold the board upside down, spray into the socket and hairdryer blow it away.















_* do not buy the other color ones. They are oil based and will leave a sticky residue or bent the pins by too high pressure_
This will dissolve any potential corrosion/oxidation, but you have to let it drip it out

Good luck !


----------



## Frosted racquet

Frosted racquet said:


> I'm starting to lose my mind, need some help.
> 
> G.Skill RipjawsV 3600 running XMP profile, MSI B550I ITX, 5600X @stock. I'm getting random TM5 errors on XMP settings and I don't know *** is the reason.
> 1usmus cfg spits out error 5,8,0,13 seemingly at random. Happens on AGESA 1203 and beta 1204. Dirty contacts, temp issues?


@Veii finally managed to get some progress on my Hynix CJR DR kit from here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

It was a temp issue all along, the Ripjaws heatsinks are trash, at least for ITX systems. All it took to stabilize the "broken" XMP profile (posted below) was a below 10 C ambient temp.


----------



## PJVol

Frosted racquet said:


> It was a temp issue all along, the Ripjaws heatsinks are trash


What were the temps after reaching thermal equilibrium? Idk, if DR is any hotter, but my two SR's (gvka) with a small (60mm) fan, didn't exceed 40° during the TM5 1usmus, running at 1.62V ProcODT 43ohm.


----------



## Imprezzion

Veii said:


> I would not give it up yet
> This happens by 2 reasons:
> 
> actual oxidation (but i don't think you've pushed that high)
> bugged out PSP-FW
> 
> In order to repair the 2nd, you'll need to board swap and make big AGESA jumps
> That forces a reflash , also detected as "new CPU Installed"
> Sometimes it can happen that TPM module also breaks - which after wiping, puts the bios back to chinese
> I've had this in specific once, but the above twice
> It messed up my X370 taichi and my 1700X
> 
> Worked then on an X570 board
> But doesn't work on the Taichi again
> (this was all far back before any ROM Armor got included or any PCH restrictions)
> 
> Usually the way to try and repair it, is SPI flash to the earlierst version - and keep the CPU outside
> Soo after time it detects this as a new CPU
> The issue can be a combination of both, but mostly it's bugged FW related
> 
> I can offer two options,
> Put it into a completely different board (maybe even different chipset, with a friends ram)
> disable and activate TPM and later Bios-CMOS reset and potentially upgrade the bios
> Then downgrade your personal board to the earliest version and put it back
> PSP-FW will detect a CPU swap and will detect and misscompatibility, soo reflash
> 
> I wish you would've had an whea-sensor report log before, but doing so also changes the amount of sensors reported
> Once started with 4/5, then changed to 9/10, and now it's back to 10 out of 10 sensors reporting
> 2nd offer i can give, is to send it over and you'll get it within a week (EU)
> I wouldn't mind checking on it (the same way above), as long as you pay the shipping (usually 10-12€)
> ~ but that's one time, i wouldn't do it often & you should definitely try it with a local friend first
> I can not give you any guarantee of trust here, but could check on it once ~ if you agree
> 
> Yes, find a friend
> Try their memory and Board combination ~ likely even cooler
> Keep the CPU out of the board for a bit of time (inside there is an ARM chip, it takes a bit for the whole unit to lose charge)
> _* if you don't see the post message "new CPU installed", then it wasn't long time enough outside_
> and flash your board to AGESA 1.0.8.0 or the earliest near 1.1.0.0 you can find
> Might also buy a WD Green or CRC Red. Hold the board upside down, spray into the socket and hairdryer blow it away.
> View attachment 2538294
> View attachment 2538295
> 
> _* do not buy the other color ones. They are oil based and will leave a sticky residue or bent the pins by too high pressure_
> This will dissolve any potential corrosion/oxidation, but you have to let it drip it out
> 
> Good luck !


All I read online about 5A + white VGA LED on ASUS is dead CPU so..

So TL;DR what happened, had a TM5 session, had 1 error 10, went to BIOS and changed ProcODT from
30 to the next one, tWR and tRTP to 12/6, clkdrv to 40/20/24/20 again, it booted, I tried to start Division 2, it WHEA uncorrectable error BSOD and never booted again since.

CPU was only on -16 all core auto LLC EDC 165 TDC 140 so not exactly pushed very high. Never been above 81c and in TM5 it sits around like 51c. vSOC 1.08125, VDDP 0.900, VDDG IOD 1.025 CCD 0.950, vDIMM 1.5650v so nothing high or out of spec there either.

Trying older BIOS now as old as it goes for the B550-XE. If that or new CPU doesn't fix it I will RMA the board and CPU, test my RAM at mates 10900KF setup, and buy probably a 11900k or 12900k with a D4 board. I have had a lot of weird issues with Intel but never something of this level...


----------



## Frosted racquet

@PJVol 
There's no temp sensor on the sticks, don't have the equipment to measure manually


----------



## Veii

Imprezzion said:


> All I read online about 5A + white VGA LED on ASUS is dead CPU so..


Maybe the other parts can have some truth
but this is nonsense


Imprezzion said:


> Trying older BIOS now as old as it goes for the B550-XE. If that or new CPU doesn't fix it I will RMA the board and CPU, test my RAM at mates 10900KF setup, and buy probably a 11900k or 12900k with a D4 board. I have had a lot of weird issues with Intel but never something of this level...


Yes try to fix it, but it won't work on the same board - unless the CPU is a long time outside
RAM OC can do all kind of funky things
While the CPU can be blamed, but not AMDs direct fault.
Memory can corrupt bioses too , if you boot half stable settings and it crashes on a read operation. A bios is after all just a database that stores loaded values
The same can happen with Intel CPUs too ~ both are on APTIO V Bios, no difference

The luck required to make such an event, is higher than the amount of "common failure" on such rare bug
But it can certainly happen
Soo my offer is to try it on a fresh new board (i got 3 here)
And as it very likely will post, just send it back to you ~ soo the thing was reset

For now, keep it for one night out of the board
Let it be detected as "new CPU installed" and it likely will just work without doing much
Be sure to never wipe CMOS directly after a bios flash and just downgrade your board to the lowest version possible. AGESA 1.0.8.0 or higher
Soo once you put it back, it has to reflash itself and the issue should be fixed fully


----------



## Audioboxer

Luggage said:


> Well to add more hurt to my nerves I just ordered a Aquacomputer flow next, out of stock… so until that shows up I’m not redoing any loop.


I've done enough draining of this loop this year for a lifetime, so yeah, I'd recommend doing everything at once lol.

Speaking of a device that caused me a few drains my GPU has been behaving fine with this Corsair power supply despite its voltage values dropping even lower in HWINFO.

I seem to have found the source of my crashing and it was indeed my GPU core frequency setting. Coupled with using the + frequency slider independent of a manually set voltage curve. If I manually do a curve and set it at 2115 with 1.093v I am stable. Often drops to 2100 during games but that ends up 2100/8000 for core/memory.

A very decent 2080Ti overclock. No crashes during gaming or stability tests. Only start to get some issues if I try to push for 2135+ on the core.

I can't say I'm happy with the 12v values dipping in HWINFO but it appears it's all at the 2080Ti input end. Overclocking the card causes a bigger drop. So I'm just writing this saga off as it's the card causing drops under 12v and my initial problems with kernel power errors was an unstable core because the default frequency slider wasn't using a high enough voltage above around 2025-2040.

I would declare nothing wrong with the Asus Thor power supply. I'll likely just keep it as a spare now. Will be interesting to test once I get a 3080.


----------



## Imprezzion

Veii said:


> Maybe the other parts can have some truth
> but this is nonsense
> 
> Yes try to fix it, but it won't work on the same board - unless the CPU is a long time outside
> RAM OC can do all kind of funky things
> While the CPU can be blamed, but not AMDs direct fault.
> Memory can corrupt bioses too , if you boot half stable settings and it crashes on a read operation. A bios is after all just a database that stores loaded values
> The same can happen with Intel CPUs too ~ both are on APTIO V Bios, no difference
> 
> The luck required to make such an event, is higher than the amount of "common failure" on such rare bug
> But it can certainly happen
> Soo my offer is to try it on a fresh new board (i got 3 here)
> And as it very likely will post, just send it back to you ~ soo the thing was reset
> 
> For now, keep it for one night out of the board
> Let it be detected as "new CPU installed" and it likely will just work without doing much
> Be sure to never wipe CMOS directly after a bios flash and just downgrade your board to the lowest version possible. AGESA 1.0.8.0 or higher
> Soo once you put it back, it has to reflash itself and the issue should be fixed fully


Done that. BIOS 0430 which is like pre 1.1 AGESA, put the CPU back with just a 760, a different random 4gb stick of 2133 DDR4 and no storage installed, same thing. Loops post codes a few times then hangs on 5A. Flashed a later BIOS again with USB flashback, 36 and 5A. 

I mean. Even if you corrupt the BIOS, a USB flashbsck without the CPU installed should logically fix it, that's literally 50% of the reason USB flashback even exists the other half being upgrading bios for a newer CPU like 2000 to 3000 AMD while not having a 2000 CPU. But, it doesn't.

I broke the BIOS many a time on my Z490 Ace. But a simple re flash would always 100% fix it. 

I just can't be bothered to put the time into this right now. I just want a working rig for the holidays and my few days off in a year so I can play some battlefield and division with the boys. So I'm just going to grab that other 5900X locally and if even that won't boot a X570/B550 AM4 board isn't exactly hard to find either locally so.. yeah..

If that fails, /care and I'll just spend my 13th month Christmas bonus straight up on a 12900K + Z690 Edge DDR4.


----------



## Veii

Imprezzion said:


> I mean. Even if you corrupt the BIOS, a USB flashbsck without the CPU installed should logically fix it, that's literally 50% of the reason USB flashback even exists the other half being upgrading bios for a newer CPU like 2000 to 3000 AMD while not having a 2000 CPU. But, it doesn't.


If you corrupt the unit internally (has an ARM chip) then you can't do much 
A bios is just a database of SMU Mailbox commands ~ not much more

You should keep it outside as written for the 2nd time (now 3rd)
If you do not see this "New CPU Installed" message ~ then it didn't reset
Although if you see it, the sample is working ~ soo there's that


----------



## Imprezzion

Veii said:


> If you corrupt the unit internally (has an ARM chip) then you can't do much
> A bios is just a database of SMU Mailbox commands ~ not much more
> 
> You should keep it outside as written for the 2nd time (now 3rd)
> If you do not see this "New CPU Installed" message ~ then it didn't reset
> Although if you see it, the sample is working ~ soo there's that


I did keep it out all night plus between all flashes.

Only thing that changed is in stead of going straight to 5A it now cycles a whole bunch of q codes very fast, then 5F, then starts again and then goes to 5A. All this time there is no signal from either the 3080 in the main slot or a 760 in a different slot just to eliminate slot and GPU. 

The only thing I haven't changed yet outside of the board and chip is the PSU but that does measure fine at least on my old €100 ebay oscilloscope on all lines.


----------



## Veii

Imprezzion said:


> I did keep it out all night plus between all flashes.
> 
> Only thing that changed is in stead of going straight to 5A it now cycles a whole bunch of q codes very fast, then 5F, then starts again and then goes to 5A. All this time there is no signal from either the 3080 in the main slot or a 760 in a different slot just to eliminate slot and GPU.
> 
> The only thing I haven't changed yet outside of the board and chip is the PSU but that does measure fine at least on my old €100 ebay oscilloscope on all lines.


Yes idk any other option than what's been written
Hope you can find some resolve local


----------



## Imprezzion

Veii said:


> Yes idk any other option than what's been written
> Hope you can find some resolve local


New chip got delivered and it boots straight up. Zero issues. So yeah, the old 5900X is borked. This one is actually a different batch, 2143, so I will put my m.2's back in and see if it boots to windows and what stepping this is.

EDIT: Am I just imagining things or is this a B2 stepping chip?


----------



## 1s1mple

Frosted racquet said:


> @PJVol
> There's no temp sensor on the sticks, don't have the equipment to measure manually


Weird how your new sticks show VDIMM and mines doesnt.
We have the exact same kit.


----------



## Frosted racquet

It's a motherboard thing, I heard ASUS does that in conjunction with Zentimings


----------



## Mach3.2

1s1mple said:


> Weird how your new sticks show VDIMM and mines doesnt.
> We have the exact same kit.


ZenTimings can't read out VDIMM and MEM VTT for Asus boards. Something to do with driver access afaik.


----------



## 1s1mple

Mach3.2 said:


> ZenTimings can't read out VDIMM and MEM VTT for Asus boards. Something to do with driver access afaik.


Yeah i read about that but if you look at his screenshot it showed VDIMM. (unless its a bug)


----------



## Frosted racquet

I'm on MSI


----------



## Audioboxer

Imprezzion said:


> New chip got delivered and it boots straight up. Zero issues. So yeah, the old 5900X is borked. This one is actually a different batch, 2143, so I will put my m.2's back in and see if it boots to windows and what stepping this is.
> 
> EDIT: Am I just imagining things or is this a B2 stepping chip?
> 
> View attachment 2538371


It says 2 for stepping so I assume so. Not sure why your revision is blank though!


----------



## 1s1mple

Frosted racquet said:


> I'm on MSI


Missed that, disregard my comment above🤭


----------



## Imprezzion

Audioboxer said:


> It says 2 for stepping so I assume so. Not sure why your revision is blank though!
> 
> View attachment 2538408


I don't know either. Maybe CPU-Z isn't updated for B2 chips as the few screenshots online also have it missing.

This chip is both a beast and also not. Cores are much stronger then my dead one. They sustain way higher clocks and a much higher all-core PBO2 negative however the IF is a disaster. It will not even boot 3800 1:1 1900 on any voltage. 1800 seems to work with 3600 memory however it does get L2 and TLB errors with a low vSOC. I need to boost it pretty high (~1.15v) for it to kind of work. Temperatures are also ~5c lower overall.

So far no issues for the cores to run -20 all-core PBO2 - with +50 max clock and it sustains well over 4800Mhz for all cores. The old one would barely maintain 4625.


----------



## Asutz

is it worth to spend 100€ more for the c14 bin ?
after quick testing doesnt look like my 5600x will do 1900 fclk, at least not on the ch7, 3733 is working.

.want to buy F4-3600C16D-32GTZN but unsure if it tweaks well enough.and to not put to much time into it i could use just the xmp.thanks in advance

btw. could resolve the kernel 41 thingy, gpu/ cpu and too much fans killed something in the psu


----------



## Imprezzion

Asutz said:


> is it worth to spend 100€ more for the c14 bin ?
> after quick testing doesnt look like my 5600x will do 1900 fclk, at least not on the ch7, 3733 is working.
> 
> .want to buy F4-3600C16D-32GTZN but unsure if it tweaks well enough.and to not put to much time into it i could use just the xmp.thanks in advance
> 
> btw. could resolve the kernel 41 thingy, gpu/ cpu and too much fans killed something in the psu


What bin do you have now? Is it b-die or? I'd say no, it isn't worth it at all really for the tiny increase in performance. 

I took my 3600C16 on this new B2 chip quite conservatively now as it will also not do 1900 FCLK but this seems to be a good starting point for at least just a simple daily profile. vDIMM is at 1.500v btw. The VDDP, IOD and CCD are kinda on the low end of the voltage range but it seems to like it so far. It did need a bump in vSOC from Auto 1.08125v to 1.1250v otherwise it would get L2 and TLB errors during TM5. 

The cores on this B2 CPU do a hell of a lot better then the dead old B0 one. I mean, I just ran this test at -25 all-core PBO2 with +50 max clock with stock Auto LLC and voltages and it seems to at least survive TM5 constant load just fine at 4825-4850Mhz on all cores consistent load. I obviously will test way more with corecycler and such but I just wanted to see what it could possibly do or not do.










What are the tricks / voltages / settings in AMD CBS and such in general for getting 1900 FCLK to run 1:1 on a CPU with a bad memory controller? I kinda forgot lol.


----------



## Asutz

Nah i dont have B Die, just Crucials and for me its pain in the ass to tweak them right.
Sometimes it feels not very responsive if the timings arn't perfect.Trc / trcdrd / trfc weakness of the crucials, so maybe just 3600 xmp tridents will outperform my actual memory and overall less finicky.

does xmp work out of the box on your board or ist it unstable without tweaking? thanks

F4-3600C16D-32GTZN around 220€, better bins as i wrote 100 more. think will try c16 ones.


----------



## Imprezzion

Asutz said:


> Nah i dont have B Die, just Crucials and for me its pain in the ass to tweak them right.
> Sometimes it feels not very responsive if the timings arn't perfect.Trc / trcdrd / trfc weakness of the crucials, so maybe just 3600 xmp tridents will outperform my actual memory and overall less finicky.
> 
> does xmp work out of the box on your board or ist it unstable without tweaking? thanks
> 
> F4-3600C16D-32GTZN around 220€, better bins as i wrote 100 more. think will try c16 ones.


The DOCP / XMP on these 3600 16-16-16-36's works perfectly out of the box. Zero tweaking required. Only downside is it sets a super high tRFC (666) which really kills performance if you wanna min-max. The rest of the Auto timings aren't even that badly set up honestly for 1.350v vDIMM. So, the easy way would be just set DOCP 3600C16 an set tRFC manually to like 276 (46 tRC) or 288 (48 tRC) and see if it holds up to that on 1.35v otherwise go 1 bin up to tRC x7 which it almost certainly will run.

All I basically did now was set it to 1.500v vDIMM, primaries to 15-15-8-15-28-43-258-2T, set trrd, tfaw, twr, tcwl, trtp and ProcODT and just run it lol. It even trains tPHYRDL to 26/26 as it should lol.


----------



## Asutz

Sounds good, some Shops list them as 1.45v for their Xmp, 3600 c16 @ 1.35 is nice, should be still enough headroom if i like to tweak, was able to boot and bench 1900mhz fclk, managed to boot with different vddg's on the ch7 iod 1.060 / ccd 0.950 and vsoc slightli over 1.1, vddp 950mv and still running.thanks for all your input mate.


----------



## Mach3.2

Imprezzion said:


> I don't know either. Maybe CPU-Z isn't updated for B2 chips as the few screenshots online also have it missing.
> 
> This chip is both a beast and also not. Cores are much stronger then my dead one. They sustain way higher clocks and a much higher all-core PBO2 negative however the IF is a disaster. It will not even boot 3800 1:1 1900 on any voltage. 1800 seems to work with 3600 memory however it does get L2 and TLB errors with a low vSOC. I need to boost it pretty high (~1.15v) for it to kind of work. Temperatures are also ~5c lower overall.
> 
> So far no issues for the cores to run -20 all-core PBO2 - with +50 max clock and it sustains well over 4800Mhz for all cores. The old one would barely maintain 4625.


Sounds like my 5900X; I can do -30 CO on almost all cores, but can't post 1900MHz IF. Mine doesn't maintain boost that high though, usually around the ballpark of 4.6GHz for short bursty workloads. Could have something to do with higher ambient temps. You win some, you lose some I guess.


----------



## Luggage

Mach3.2 said:


> Sounds like my 5900X; I can do -30 CO on almost all cores, but can't post 1900MHz IF. Mine doesn't maintain boost that high though, usually around the ballpark of 4.6GHz for short bursty workloads. Could have something to do with higher ambient temps. You win some, you lose some I guess.


Yea if it doesn’t boost high enough because of temps it won’t crash from the aggressive CO values… so you might have to adjust the curve if ambient drops.


----------



## rocketgun

Veii said:


> Yes idk any other option than what's been written
> Hope you can find some resolve local


Hi, I learned what you said on several threads of the forum, and solved my computer cold restart and even hot then restart many times.
here are some scores of my Threadripper 3960X + Asus Prime TRX40 Pro-S + Corsair LPX 3600MHz 4*32GB (18-22-22-22-42)(micron B-die, 1.35v and now 1.40v), 
and now my TRCDRD and tCL cannot reduce anymore otherwise can't start.
please give some tips, thank you


----------



## Veii

Imprezzion said:


> New chip got delivered and it boots straight up. Zero issues. So yeah, the old 5900X is borked. This one is actually a different batch, 2143, so I will put my m.2's back in and see if it boots to windows and what stepping this is.
> 
> EDIT: Am I just imagining things or is this a B2 stepping chip?
> 
> View attachment 2538371


Congrats on the sample
Hmm current Hydra is not out for everybody
These samples work horrible on anything that's not 1205 AGESA
Also these samples are voltage sensitive - and draw less

You might want to drop cLDO_VDDP to 820-860mV , 820 should work 
CCD too & procODT too 
They don't like that much VDD18 voltage, but 1.86 is perfectly fine 
this should allow you to drop procODT a bit further.
You will need low procODT for running low VDDP and VDDG voltage

You currently need high SOC , as procODT is high for it
It kinda looks fine, but don't overjudge it yet ~ it's an entry sample and many software's do not recognize it

About your old B0 
Soo what is the plan with it ~ does it go back or ?


----------



## Veii

rocketgun said:


> please give some tips, thank you


Big setup 
I don't think i can give you much help, when there is no stability proof (TM5)
But you can increase SOC slightly - 15mV, just so with droop you have 1.1v GET
It will make you no issues except heat, if you go to 1150mV SOC 

Everything looks great, but i would start to redesign RTTs
RTT_WR /2 has to run for you, maybe 6-2-2 
ClkDrvStr can be between 60 and 120ohm for you, but it can happen that you need to lower procODT else PCBs can crash
Soo maybe 60-20-24-20 , with 723 or 622 or 623 RTTs
128gb will take 10hours to be tested with TM5 1usmus_v3. 
There is no way around skipping that


----------



## Imprezzion

Veii said:


> Congrats on the sample
> Hmm current Hydra is not out for everybody
> These samples work horrible on anything that's not 1205 AGESA
> Also these samples are voltage sensitive - and draw less
> 
> You might want to drop cLDO_VDDP to 820-860mV , 820 should work
> CCD too & procODT too
> They don't like that much VDD18 voltage, but 1.86 is perfectly fine
> this should allow you to drop procODT a bit further.
> You will need low procODT for running low VDDP and VDDG voltage
> 
> You currently need high SOC , as procODT is high for it
> It kinda looks fine, but don't overjudge it yet ~ it's an entry sample and many software's do not recognize it
> 
> About your old B0
> Soo what is the plan with it ~ does it go back or ?


Yeah it's getting RMA and I will probably sell the new one sealed as it's worth more that way unless that is a B2 as well lol. Then I might bin it against this one.

So, I need less ProcODT then 34.3 and less VDDP and VDDG? I'm at 0.950 CCD 1.025 IOD 0.900 CLDO, stock auto VDD1.8, offset +0.025 on vSOC (which is 1.125v with droop to ~1.13v load).

Still a shame this one has such a hard time even POSTing with 1900 IF. It just hangs on random q-codes and even if it does POST / boot it absolutely rains L2 and TLB errors.

Cores seem to handle -25 all core PBO2 quite well so far. The old B0 would only do -16 at 4625 in games while this one does -25 at 4850 in the same games so far. I obviously haven't stress tested it yet as it was more of a quick "can it do it" test but hey, 2 hours Division 2 with no crashes or WHEA's on -25. The B0 could only dream of that on -20 lol. And yes, it draws like 20-30w less PPT at the same EDC. 220-230w vs 195-210w for this one. Temps lower as well.


----------



## rocketgun

Veii said:


> Big setup
> I don't think i can give you much help, when there is no stability proof (TM5)
> But you can increase SOC slightly - 15mV, just so with droop you have 1.1v GET
> It will make you no issues except heat, if you go to 1150mV SOC
> 
> Everything looks great, but i would start to redesign RTTs
> RTT_WR /2 has to run for you, maybe 6-2-2
> ClkDrvStr can be between 60 and 120ohm for you, but it can happen that you need to lower procODT else PCBs can crash
> Soo maybe 60-20-24-20 , with 723 or 622 or 623 RTTs
> 128gb will take 10hours to be tested with TM5 1usmus_v3.
> There is no way around skipping that


Thank you very much.
by the way, I Passed TM5 basic preset.
and what is the mean of "1.1V GET"?
and did you mean try RTTNom:7, RTTWR:2, RTTPark:3?
Now my setting are:
*CLDO VDDP Voltage: 900mv
VDDG IOD Voltage: 1.0
VDDG CCD Voltage:0.95
SoC Voltage: 1.1
Memory Dimm Voltage:1.4V*


----------



## Dasa

Been playing around with speeds over 4000 since updating the BIOS but just cant get it stable.
Playing with V, RTT, DrvStr but cant find that sweat spot between lack of V and PCB crash or increased VDIMM just making it less stable possibly due to heat with these 30c days.

This CPU\MB is one that cant run 3800 without WHEA and on some BIOS wont even post over 3733.
At 4133 1:1 it is at the limits of where increased chipset V can stop the audio crackling.


----------



## domdtxdissar

Seems like Santa came a few days early this year 🎅








Had to order from Germany to find it in stock anywhere..

Will try to find the time to get it installed within a few days.. Anyone taking bets if it will let me run above 1900 fclk without reduced performance ?
(Crosshair VIII Hero currently limits me to 1900, and maximum 2033MT/s memspeed when decoupled from flck)


----------



## Asutz

Got an offer for 4x8gb 3600 c15 Tridents but my Board got Daisy Chain Layout. Still possible to Oc to like 3800 ?Thanks in Advance


----------



## Audioboxer

domdtxdissar said:


> Seems like Santa came a few days early this year 🎅
> View attachment 2538497
> 
> Had to order from Germany to find it in stock anywhere..
> 
> Will try to find the time to get it installed within a few days.. Anyone taking bets if it will let me run above 1900 fclk without reduced performance ?
> (Crosshair VIII Hero currently limits me to 1900, and maximum 2033MT/s memspeed when decoupled from flck)


Do you have a B550 as well? If so tell us how it compares!


----------



## domdtxdissar

Audioboxer said:


> Do you have a B550 as well? If so tell us how it compares!


i will report back how it goes! 
In the meantime, i'm trying something new 








It cant get worse, i hope atleast 
Stock heatsink on Trident Z are brushed aluminum, so i thought what the hell, lets just overdo it on the outside to try to compensate for little spacing between the sticks on this 2dimm board


----------



## Audioboxer

domdtxdissar said:


> i will report back how it goes!
> In the meantime, i'm trying something new
> View attachment 2538535
> 
> It cant get worse, i hope atleast
> Stock heatsink on Trident Z are brushed aluminum, so i thought what the hell, lets just overdo it on the outside to try to compensate for little spacing between the sticks on this 2dimm board
> 
> 
> View attachment 2538530
> View attachment 2538531
> View attachment 2538532
> View attachment 2538533
> View attachment 2538534


LOL, mad lad.

Yeah, the X570s Unify MAX is like gold dust in the UK, just non-existent, so I'll be interested to see if other than the full PCIe 4.0 support across all channels if there is any performance uplift.

Heck even the B550 is getting sparse here now, though one or two decent deals still out there.


----------



## Imprezzion

Veii said:


> Congrats on the sample
> Hmm current Hydra is not out for everybody
> These samples work horrible on anything that's not 1205 AGESA
> Also these samples are voltage sensitive - and draw less
> 
> You might want to drop cLDO_VDDP to 820-860mV , 820 should work
> CCD too & procODT too
> They don't like that much VDD18 voltage, but 1.86 is perfectly fine
> this should allow you to drop procODT a bit further.
> You will need low procODT for running low VDDP and VDDG voltage
> 
> You currently need high SOC , as procODT is high for it
> It kinda looks fine, but don't overjudge it yet ~ it's an entry sample and many software's do not recognize it


My board doesn't have 1205 AGESA available yet unless there's a beta BIOS I haven't found yet.

Btw, how low should I go on the VDDG CCD and IOD? I've been steadily dropping them and seeing if it boots to Windows at least and I got quite far already. Also ProcODT on 28.2 now.

Should I adjust the RTT's and resistances as well? I have 6/3/3 RTT now and 40/20/24/20 resistances but maybe I have to redo those as well now?

It still won't boot 1900 tho. 1867 at least posts but it doesn't run very stable in Windows...


----------



## KedarWolf

Audioboxer said:


> LOL, mad lad.
> 
> Yeah, the X570s Unify MAX is like gold dust in the UK, just non-existent, so I'll be interested to see if other than the full PCIe 4.0 support across all channels if there is any performance uplift.
> 
> Heck even the B550 is getting sparse here now, though one or two decent deals still out there.


Here in Canada, buying for sure.









MSI MEG X570S UNIFY-X MAX AM4 ATX AMD Motherboard - Newegg.com


Buy MSI MEG X570S UNIFY-X MAX AM4 AMD X570 SATA 6Gb/s ATX AMD Motherboard with fast shipping and top-rated customer service. Once you know, you Newegg!




www.newegg.ca


----------



## Imprezzion

Well, this works fine. I lowered ProcODT and VDDG / VDDP quite substantially thanks to @Veii 
1.500v vDIMM but RAM fan is set to low RPM to heat up the DIMM's on purpose to simulate higher ambients in the summer. 
They handle 47c just fine at these clocks and timings. It ain't the tightest at all but it's just a good baseline to save as a daily profile I know won't cause problems. 

Also, this is a decent CPU test as well and yes, it maintained 4800-4825 across all cores the entire test without issues at -25 PBO2 all-core.

I might change vSOC to something lower or change RTT's and resistances later but this is fine for now.


----------



## MrHoof

@Imprezzion watch out for WHEA 19 in the windows eventviewer for IOD voltage .95 might be little low thats where mine CPU starts acting up but .975 is fine. They can appear randomly and u wont notice them if you dont look for them. Just check your eventviewer every now and then.

edit: Oh you still at 3600 then probably the IOD is fine and 1v-1.05 VSOC would do it.


----------



## MrHoof

Anyone has played around with BGS on DR yet? I looked it up on the google but my results dont reflect what I found online. Wich is it would reduce Latency but increase bandwidth but my latency is untouched. The BGS Alt run is 0.1ns faster cause it was at 5ghz.



Spoiler: BGS ON

















Spoiler: BGS Alt
















EDIT: HYDRA is out. PROJECT HYDRA - OC Sandbox for ZEN3 CPUs | Freeware Download | igor'sLAB (igorslab.de)


----------



## nick name

MrHoof said:


> Anyone has played around with BGS on DR yet? I looked it up on the google but my results dont reflect what I found online. Wich is it would reduce Latency but increase bandwidth but my latency is untouched. The BGS Alt run is 0.1ns faster cause it was at 5ghz.
> 
> 
> 
> Spoiler: BGS ON
> 
> 
> 
> 
> View attachment 2538609
> 
> 
> 
> 
> 
> 
> Spoiler: BGS Alt
> 
> 
> 
> 
> View attachment 2538610
> 
> 
> 
> 
> 
> EDIT: HYDRA is out. PROJECT HYDRA - OC Sandbox for ZEN3 CPUs | Freeware Download | igor'sLAB (igorslab.de)


I prefer to run BGS on. I see better results in benchmarks.


----------



## domdtxdissar

domdtxdissar said:


> i will report back how it goes!
> In the meantime, i'm trying something new
> View attachment 2538535
> 
> It cant get worse, i hope atleast
> Stock heatsink on Trident Z are brushed aluminum, so i thought what the hell, lets just overdo it on the outside to try to compensate for little spacing between the sticks on this 2dimm board
> 
> 
> View attachment 2538530
> View attachment 2538531
> View attachment 2538532
> View attachment 2538533
> View attachment 2538534


Preliminary report 

Extra heatsinks on memory sticks seems to be working fine, eventho the memory are so close together and the heatsinks are just on one side.. Only a ~7 degree delta between idle and load after 1 hour Karhu ramtest @ 1.56vdimm









Motherboard is working really exemplary, it boot every setting known to man, no fuss, no nothing... Haven't had a failed post yet  (10x better then the Asus board in this regard)
And as you can see, I'm also back to my normal "CL13 1900 baseline memory settings"

CPU is the same 5950x as before, everything above 1900 flck spits out ~100 WHEA each Aida64 mem testrun
But one thing is new with this motherboard.. with the Crosshair VIII Hero i got clearly reduced performance @ 1933 and everything above, even in superlight things like Aida.. With this board i seems to see somewhat scaling to atleast 4000:2000, maybe  (haven't tried higher yet)

Hopefully this means there is hope for real performance scaling above 1900 when using the whea suppressor on this board.. 

Much testing left to be done and lots of new settings to be learned, but i'm happy with what this board have achieved on first day.. This will be a very good platform for Zen 3d-$ in the future


----------



## MrHoof

Not to **** one Asus completely, I love my 570-i. Not struggling with anything either.


----------



## Imprezzion

MrHoof said:


> @Imprezzion watch out for WHEA 19 in the windows eventviewer for IOD voltage .95 might be little low thats where mine CPU starts acting up but .975 is fine. They can appear randomly and u wont notice them if you dont look for them. Just check your eventviewer every now and then.
> 
> edit: Oh you still at 3600 then probably the IOD is fine and 1v-1.05 VSOC would do it.


Yeah still 3600 cause this chip hates life at 3800 1900 1:1. I played some Division 2 and world of tanks on these settings, event viewer and HWInfo64 error logging is still clean. No weirdness either. I will obviously try to push for C14 but this bin doesn't like straight 14's. It will run CAS at 14 but tRP and tRCD 14 is quite the ask for these poor DIMM's. Besides, when I change CAS to 14 the tPHYRDL wont train 26/26 it goes 24/26 so gotta fix that too.


----------



## umea

domdtxdissar said:


> i will report back how it goes!
> In the meantime, i'm trying something new
> View attachment 2538535
> 
> It cant get worse, i hope atleast
> Stock heatsink on Trident Z are brushed aluminum, so i thought what the hell, lets just overdo it on the outside to try to compensate for little spacing between the sticks on this 2dimm board
> 
> 
> View attachment 2538530
> View attachment 2538531
> View attachment 2538532
> View attachment 2538533
> View attachment 2538534


I actually had this exact same thought a little while ago, let us know how it works out!

edit: what is your room temperature? do you have a fan running on the dimms? 33c under load is very good


----------



## domdtxdissar

umea said:


> I actually had this exact same thought a little while ago, let us know how it works out!
> 
> edit: what is your room temperature? do you have a fan running on the dimms? 33c under load is very good


Roomtemp was around ~25 degrees.. idle mem temp is pretty much ambient on this cooling setup.
As shown in those pictures you have quoted, i use Alseye 2x40mm fans for the memory alone:









How it looks inside the case:


----------



## Audioboxer

Anta said tRFC should be multiples of 16 otherwise the ram will autocorrect anyway, but IIRC @Veii you said try multiples of 9 instead? Is that correct?

Going to have a bit of fun seeing how low I can drive tRFC around the 1.6v mark. I'm sure I tried this before and going from 224 to 208 was struggling. Just want to check if there is a point in-between which can be tested.


----------



## Veii

Audioboxer said:


> Anta said tRFC should be multiples of 16 otherwise the ram will autocorrect anyway, but IIRC @Veii you said try multiples of 9 instead? Is that correct?


Anta's conclusion i came too , before
32 being "a full cycle" ~ but this was not exactly correct.
Not wanting to put him words in the mouth, as it has a different reason being "8" or "16" for DR
But to my experience, it is completely different ~ soo i've moved away from this method

Move within multiples of 1/4th or 1/2 of your tRC
Hence tRAS = tRC-tRP , tRC and tRTP have to be correct
Using tRC as an anchor point skips a bit of math, compared to before focusing on tCL

My thought remains,
Clean single digit divider inside tRFC range (tRTP and tWR)
often nCK values divide better than tCK values ~ soo doing math in ns was correct
This guarantees a correct hit every time. And it wouldn't matter on what command rate, or refresh rate it runs, or if it does burst refresh "trickery" by AMD.
It also doesn't matter what tREFI AMDs-FW predicts, as this method will result in always a guaranteed hit in time

If you want to go full manual, get 1/8th of it and scale up
Up to 1/4th you should be able to get it "shifted"
But old method of just matching tRTP somewhere inside it, is fine ~ it does not cause any issues

You have to still remember your IC limits, your PCB limits and know that higher thermals will increase IC leakage factor
But if you know this, you can easily pick correct tRFC
A too low, will not do anything. A too high will be a bottleneck, but the difference is small
What you do lose on a more conservative tRFC, is thermal scaling & thermal stability helps lower other more important timings

Early on fear about data corruption was spread, but Zen units have ECC in them , and Vermeer is more than fantastic to correct it before any "silent" datacorruption can happen.
Take your tRC 54 for example, in scale within multiples of 27
Take your 36 and scale within multiples of 9 or 18
Take your 42 and scale within multiples of 21 ~ and so on
Or just turn your random value into ns, and see if tWRns or tRFCns work within it

If you check old shenanigans sheet, i've experimented with 32,16,8,4,2 before
But moved awayfrom this. This was very early times before the old non manual 1.0 mini was published

EDIT:
if the set is perfect,you can daily 112ns tRFC , instead the 120ns "apparently hardlimit" of b-die
But you should still know your PCB limits, else you can't expect " 6* " to work for it, when it results in just unrunnable tRFC

Resolve for this, would be to include a VDIMM to heat discharge metrics/prediction
And crosscompare results within IC's and PCBs known "ranges" ~ ala Hardwareluxx/Computerbase list
~ just such is unrealistic amount of work
And it still it doesn't change "my viewpoint" that you should not use real world ns values for your tRFC target.
Work in multiples and integers, not "fixes ns" targets (120,130,140ns) ~ that's a problematic viewpoint, but surely is easier that way

Also don't forget that GDM allows to run far lower tRFC than usually possible
For people still trying to get GDM away~


----------



## Audioboxer

Veii said:


> Anta's conclusion i came too , before
> 32 being "a full cycle" ~ but this was not exactly correct.
> Not wanting to put him words in the mouth, as it has a different reason being "8" or "16" for DR
> But to my experience, it is completely different ~ soo i've moved away from this method
> 
> Move within multiples of 1/4th or 1/2 of your tRC
> Hence tRAS = tRC-tRP , tRC and tRTP have to be correct
> Using tRC as an anchor point skips a bit of math, compared to before focusing on tCL
> 
> My thought remains,
> Clean single digit divider inside tRFC range (tRTP and tWR)
> often nCK values divide better than tCK values ~ soo doing math in ns was correct
> This guarantees a correct hit every time. And it wouldn't matter on what command rate, or refresh rate it runs, or if it does burst refresh "trickery" by AMD.
> It also doesn't matter what tREFI AMDs-FW predicts, as this method will result in always a guaranteed hit in time
> 
> If you want to go full manual, get 1/8th of it and scale up
> Up to 1/4th you should be able to get it "shifted"
> But old method of just matching tRTP somewhere inside it, is fine ~ it does not cause any issues
> 
> You have to still remember your IC limits, your PCB limits and know that higher thermals will increase IC leakage factor
> But if you know this, you can easily pick correct tRFC
> A too low, will not do anything. A too high will be a bottleneck, but the difference is small
> What you do lose on a more conservative tRFC, is thermal scaling & thermal stability helps lower other more important timings
> 
> Early on fear about data corruption was spread, but Zen units have ECC in them , and Vermeer is more than fantastic to correct it before any "silent" datacorruption can happen.
> Take your tRC 54 for example, in scale within multiples of 27
> Take your 36 and scale within multiples of 9 or 18
> Take your 42 and scale within multiples of 21 ~ and so on
> Or just turn your random value into ns, and see if tWRns or tRFCns work within it
> 
> If you check old shenanigans sheet, i've experimented with 32,16,8,4,2 before
> But moved awayfrom this. This was very early times before the old non manual 1.0 mini was published
> 
> EDIT:
> if the set is perfect,you can daily 112ns tRFC , instead the 120ns "apparently hardlimit" of b-die
> But you should still know your PCB limits, else you can't expect " 6* " to work for it, when it results in just unrunnable tRFC
> 
> Resolve for this, would be to include a VDIMM to heat discharge metrics/prediction
> And crosscompare results within IC's and PCBs known "ranges" ~ ala Hardwareluxx/Computerbase list
> ~ just such is unrealistic amount of work
> And it still it doesn't change "my viewpoint" that you should not use real world ns values for your tRFC target.
> Work in multiples and integers, not "fixes ns" targets (120,130,140ns) ~ that's a problematic viewpoint, but surely is easier that way
> 
> Also don't forget that GDM allows to run far lower tRFC than usually possible
> For people still trying to get GDM away~


Down at 208 it was an error 11 IIRC I used to get something like 14~19 cycles into TM5. So in line with your error sheet that would be correct, too low tRFC with an error after time. I'll try 216 and see how it gets on, I'm still a bit confused around calculating tRFC though the above helps a bit. Your calculator does suggest 216 would be a valid figure if running tRC 36.


----------



## domdtxdissar

So i have done some further testing..

*The good:*
This motherboard + memory combo have no problems booting up (atleast) 4400MT/sec memory speeds on dual rank 2x16GB running pretty tight timings (flat CL15).
Really wish for a good sample of 6950x v-$ which let me run high fclk🙏

Motherboard boots pretty much every settings i try, and when it don't, the recovery-system works flawlessly 

*The bad:*
I seem to get lower performance with this motherboard @ the same static clocks compared to my old asus motherboard.

If we take Cinebench r20 which don't care about memory for example:
Crosshair VIII Hero @ 4700/4600 static clocks = ~12.1k points in r20
Unify X MAX @ 4700/4600 static clocks = ~11.9k points in r20

Hopefully this comes down to the rather old AGESA on the only bios released for this motherboard atm, SMU 56.52.0 (1.2.0.3c)
Crossing my fingers this get fixed in new bios..

Some funkiness: (LLC lol scaling)
LLC 8 (weakest) = upto ~20% cpu vdroop
LLC 7 (second weakest) = ~3% cpu vdroop

My CPU is still the same 5950x, cant run above 1900fclk without reduced performance, and have pretty much given up trying at this point..

*The interesting:*







VS









When testing how high memory-speed this motherboard + memory combo would run decoupled from flck with the minimum fiddling in the bios, (second day i have this motherboard) i also decided to perform some basic benchmark comparisons @ a static 4500/4400mhz cpu clock against my standard synced flck 1900 CL profile..

Since the IO die on my 5950x is so bad limiting me to lowish 1900:1900:3800 when running synced, it really depend on what the benchmark I'm running for it to be faster than running 4400:1800:1100 asynced..








VS











*1600:1100:4400 asynced*
Linpack = 659 average gflops
y-cruncher = 60.990 seconds

*1900:1900:3800 synced*
Linpack = 661 average gflops
y-cruncher = 63.711 seconds

Even more testing needed..


----------



## Audioboxer

@Veii I remembered from your calculator at tCL13/tRC 38 228 was one of the options. I think I actually used to run this before Anta told me to change it, because an even 120 "looks nice" lol. Having a look at ProcODT and Park as well. General thought is run RttPark as weak as possible?


----------



## Imprezzion

I am on 270 tRFC now on 3600C15 daily simple foolproof profile as the tRC is 45 (15+30 tRAS) but I wonder if I can get away with x5 or 225. Probably not at the low vDIMM I run on this profile but k. 

I still wanna get 3800 1900 1:1 but anything over 1867 FCLK just refuses to POST on this B2 chip. Mind you, I don't have a AGESA 1.2.0.5 BIOS available yet and B2 chips seem to really want those but still. It's a bit weird that 1900 will not even attempt to POST even with plenty of vSOC, IOD, CCD and such while 1800 runs totally fine at very low IOD, CCD and moderate vSOC of 1.125v.

Maybe I should just have patience for 1.2.0.5 to hit the B550-XE and try again then and just settle for 3600 CAS whatever for now. C15 is obviously very loose but it's nice as it can run this at basically Amy DIMM temperature, had it as high as 56c, and it still doesn't error so if summer hits and my A/C bill gets a bit too high with the current every prices I can afford to run hot ambients of 32c with this BIOS profile as the RAM can sustain it just fine.

I'll try to go for like CAS13 tonight but I kinda doubt my 3600C16 DR's will like 13 all that much unless I go to 1.6v or above for vDIMM.


----------



## Akex

Imprezzion said:


> I am on 270 tRFC now on 3600C15 daily simple foolproof profile as the tRC is 45 (15+30 tRAS) but I wonder if I can get away with x5 or 225. Probably not at the low vDIMM I run on this profile but k.
> 
> I still wanna get 3800 1900 1:1 but anything over 1867 FCLK just refuses to POST on this B2 chip. Mind you, I don't have a AGESA 1.2.0.5 BIOS available yet and B2 chips seem to really want those but still. It's a bit weird that 1900 will not even attempt to POST even with plenty of vSOC, IOD, CCD and such while 1800 runs totally fine at very low IOD, CCD and moderate vSOC of 1.125v.
> 
> Maybe I should just have patience for 1.2.0.5 to hit the B550-XE and try again then and just settle for 3600 CAS whatever for now. C15 is obviously very loose but it's nice as it can run this at basically Amy DIMM temperature, had it as high as 56c, and it still doesn't error so if summer hits and my A/C bill gets a bit too high with the current every prices I can afford to run hot ambients of 32c with this BIOS profile as the RAM can sustain it just fine.
> 
> I'll try to go for like CAS13 tonight but I kinda doubt my 3600C16 DR's will like 13 all that much unless I go to 1.6v or above for vDIMM.



I don't think I'm too mistaken that you are going to need at least 1.64v for 13-15-13-13.


----------



## hazium233

Asutz said:


> Got an offer for 4x8gb 3600 c15 Tridents but my Board got Daisy Chain Layout. Still possible to Oc to like 3800 ?Thanks in Advance


Are you getting a good deal on these? If not then get decent bin 2x16GB DR.

One thing to keep in mind about that kit is that they were on A0 PCB for most of the run, then some of the later ones are on A2. You can easily tell if they are all the same if you can see the pictures of all four dimms.

Otherwise, unless you like tweaking the ram and / or have a very fast GPU and good cooling for the 5600X, then I don't know that it will necessarily be worth the money to go from 32GB Micron to B-die.


----------



## hazium233

I flashed 1.70 which is 1203b and 56.53.0. Off the bat I thought it was weird it trained tRDRDDD different channel A and B (5 and 6 on Auto for XMP).

Anyway Eder had mod bios versions beta 1.72 but also seems to have made one for beta 1.84 which is 1205 with 56.65. Wonder what that one is like, but I thought I read 1205 isn't ready for prime time.

As an aside, it is funny MSI hasn't seemed to release a 1.80 stable for 1203c despite the beta being available for months now.


----------



## amaire

Hey guys,

Having a strange issue here. I've been trying to get 4x16 quad rank to boot at 3800mhz for a while now and have been experimenting with some different voltages, but for some reason I can't boot if i set my VDDG CCD above 1.12v. My mb (asus dark hero) gets stuck at code 92, which according to google is a pci-e related error. Even if I try to boot at stock frequencies, stock timings, setting vddg ccd even .001 above 1.12 gets the computer stuck at boot at code 92 and I have to reset cmos.

I've tried loosening timings, setting voltages all the way up to SOC - 1.3, CLDO VDDP - 1.2, VDDG CCD - 1.12, IOD - 1.05, setting VTT to .82 and VPP to 2.7, and VDIMM to 1.6, but I still f9 trying to boot at 3800/1900. I've tested with 2 dimms and have been able to boot all the way up to 4000/2000, so I know its IMC related. 

Currently im running at 3666mhz, which is the highest I've been able to get stable, but I've seen a few people on these forums getting 3800mhz 4x16 quad rank. Might be possible that my IMC is just not as good as theirs, but would love to get some advice on making that happen and if anyone could help me with the VDDG CCD voltage issue i'm having.

My current timings/benchmarks (fully stable)


----------



## TMavica

My PC spec 5950x, Asus C8E mobo , G.skill F4-4000C14 GTES 16x2. I found my memory latency is too high compared to those member in forum. I have lowered my memory frequency to 3800 and FCLK 1900, there is no any crash / WHEA during the stress test, but the latency just stuck at 64 ns, maybe this is the problem of Windows 11? If not, any suggestion I can tune it lower?? Thanks!
By the way, I cant go 1T with GDM disabled, no POST and the DRAM voltage is set to 1.45v, but the zentimings Vdimm show 1.2v


----------



## Audioboxer

amaire said:


> Hey guys,
> 
> Having a strange issue here. I've been trying to get 4x16 quad rank to boot at 3800mhz for a while now and have been experimenting with some different voltages, but for some reason I can't boot if i set my VDDG CCD above 1.12v. My mb (asus dark hero) gets stuck at code 92, which according to google is a pci-e related error. Even if I try to boot at stock frequencies, stock timings, setting vddg ccd even .001 above 1.12 gets the computer stuck at boot at code 92 and I have to reset cmos.
> 
> I've tried loosening timings, setting voltages all the way up to SOC - 1.3, CLDO VDDP - 1.2, VDDG CCD - 1.12, IOD - 1.05, setting VTT to .82 and VPP to 2.7, and VDIMM to 1.6, but I still f9 trying to boot at 3800/1900. I've tested with 2 dimms and have been able to boot all the way up to 4000/2000, so I know its IMC related.
> 
> Currently im running at 3666mhz, which is the highest I've been able to get stable, but I've seen a few people on these forums getting 3800mhz 4x16 quad rank. Might be possible that my IMC is just not as good as theirs, but would love to get some advice on making that happen and if anyone could help me with the VDDG CCD voltage issue i'm having.
> 
> My current timings/benchmarks (fully stable)
> View attachment 2538841


Why are you trying to push CCD above 1.12v anyway? At 1900 FCLK it really doesn't need to be this high.

My first tip for you would be to try with 2x16GB and see if it boots 3800/1900 OK.


----------



## PJVol

@Veii
Well, based on some preliminary tests i can confirm - CO magnitude IS dldo psm margin, at least in an allcore variant, 0 to -10 values were perfectly matched the ones set in BIOS with the allcore option, i.e. the results were in a good agreement 
Not sure if the psm margins should fit -30 to 30 range )
As for per-core setting, it won't be a problem for you and others as well, it seems.
Still per-core is TBC, but anyway, this raises interesting questions


----------



## Imprezzion

I still cannot for the life of me boot 1900. Or 1867 for that matter. But they way at which it fails is quite weird to me. For example 1800 works totally fine on 1.125v vSOC and super low CCD, IOD and VDDP (0.82, 0.95, 0.86) and is totally stable. 1833 works pretty much the same at the same voltages and runs fine. 1867 however does POST but Windows won't even attempt to boot, ntoskrnl instantly brraks and throws me back to UEFI. 1900 just hangs on "07". 

What's weird is that no matter what I change on the voltages, even with super high voltages, nothing changes on 1867 and 1900 behavior. It's like voltages have no effect at all on stability which is kinda odd to me.

So basically all I can run is 3666Mhz max memory so I am trying to make it as fast as it'll go with reasonable vDIMM but so far that too isn't going very well lol. CR1 maybe?


----------



## nick name

Imprezzion said:


> I still cannot for the life of me boot 1900. Or 1867 for that matter. But they way at which it fails is quite weird to me. For example 1800 works totally fine on 1.125v vSOC and super low CCD, IOD and VDDP (0.82, 0.95, 0.86) and is totally stable. 1833 works pretty much the same at the same voltages and runs fine. 1867 however does POST but Windows won't even attempt to boot, ntoskrnl instantly brraks and throws me back to UEFI. 1900 just hangs on "07".
> 
> What's weird is that no matter what I change on the voltages, even with super high voltages, nothing changes on 1867 and 1900 behavior. It's like voltages have no effect at all on stability which is kinda odd to me.
> 
> So basically all I can run is 3666Mhz max memory so I am trying to make it as fast as it'll go with reasonable vDIMM but so far that too isn't going very well lol. CR1 maybe?


Something I found on a couple newer CPUs was that 1.2V SOC wouldn't POST. Also, everything liked 1.1V VDDP. I didn't see much change when increasing VDDG voltages.

Edit:
Any chance you're not using RAM slots A2 B2?


----------



## Imprezzion

nick name said:


> Something I found on a couple newer CPUs was that 1.2V SOC wouldn't POST. Also, everything liked 1.1V VDDP. I didn't see much change when increasing VDDG voltages.
> 
> Edit:
> Any chance you're not using RAM slots A2 B2?


It's A2 B2. I tried everything from 1.1v vSOC all the way to 1.3v and nothing even changes. VDDP as high as 1.150, IOD 1.175, CCD 1.125, zero difference. I'd expect it to at least give a different POST code, or boot to BIOS, or to Windows with WHEA's at some point or whatever but nothing. Just absolutely nothing.

It could be me running a B2 stepping chip on a board that doesn't have 1.2.0.5 AGESA available. This one runs 1.2.0.3 C.


----------



## Bix

Imprezzion said:


> I still cannot for the life of me boot 1900. Or 1867 for that matter. But they way at which it fails is quite weird to me. For example 1800 works totally fine on 1.125v vSOC and super low CCD, IOD and VDDP (0.82, 0.95, 0.86) and is totally stable. 1833 works pretty much the same at the same voltages and runs fine. 1867 however does POST but Windows won't even attempt to boot, ntoskrnl instantly brraks and throws me back to UEFI. 1900 just hangs on "07".
> 
> What's weird is that no matter what I change on the voltages, even with super high voltages, nothing changes on 1867 and 1900 behavior. It's like voltages have no effect at all on stability which is kinda odd to me.
> 
> So basically all I can run is 3666Mhz max memory so I am trying to make it as fast as it'll go with reasonable vDIMM but so far that too isn't going very well lol. CR1 maybe?


Out of interest have you tried going higher than 1900? Some chips seem to have FCLK holes around 1900 so might be worth checking to see if higher will POST...


----------



## Imprezzion

Bix said:


> Out of interest have you tried going higher than 1900? Some chips seem to have FCLK holes around 1900 so might be worth checking to see if higher will POST...


No honestly I haven't. I can try lol.
This is what i'm currently running TM5 for and is about the best most optimized I can get 3666 without going (too far) over 1.50v vDIMM. You can see how low my voltages are except maybe vSOC but it isn't very high either for 1833.









Well, time to try 4000 16-16-16 with 2000 FCLK lol.

EDIT: you're joking right. It booted 3933 C15 1:1 1966 right up no problems at all. It WHEA's like 8 a minute idle but it boots at least..


----------



## mongoled

Imprezzion said:


> It could be me running a B2 stepping chip on a board that doesn't have 1.2.0.5 AGESA available. This one runs 1.2.0.3 C.


I'm sure I read where @Veii said that B2 stepping needs agesa 1.2.0.5 to "behave"


----------



## Bix

Imprezzion said:


> EDIT: you're joking right. It booted 3933 C15 1:1 1966 right up no problems at all. It WHEA's like 8 a minute idle but it boots at least..


Nice. You should hopefully be able to get the WHEAs under control by tweaking the voltages. I still get them but we're talking 8 a day rather than 8 a minute.

(I'm on the older stepping and currently running 920 VDDP, 960 CCD, 1040 IOD and 1.1375 SOC)


----------



## Imprezzion

Bix said:


> Nice. You should hopefully be able to get the WHEAs under control by tweaking the voltages. I still get them but we're talking 8 a day rather than 8 a minute.
> 
> (I'm on the older stepping and currently running 920 VDDP, 960 CCD, 1040 IOD and 1.1375 SOC)


I'll try some voltages. I guess I'll need a lot more vSOC then that but the others might be fine.

I also noticed it has a lot harder time to POST / boot when ProcODT is set very low to like 28.2 with low VDDP/VDDG's. When I up ProcODT to like 43.6 and raise the VDDP and VDDG's it boots much easier. 

So far on 3866 + 1933 1:1 with 1.20 vSOC it passes Cinebench R23 without WHEA's but AIDA 64 RAM & Cache bench throws it on it's back and has 40 errors after 1 run...


----------



## Bix

Imprezzion said:


> I'll try some voltages. I guess I'll need a lot more vSOC then that but the others might be fine.
> 
> I also noticed it has a lot harder time to POST / boot when ProcODT is set very low to like 28.2 with low VDDP/VDDG's. When I up ProcODT to like 43.6 and raise the VDDP and VDDG's it boots much easier.
> 
> So far on 3866 + 1933 1:1 with 1.20 vSOC it passes Cinebench R23 without WHEA's but AIDA 64 RAM & Cache bench throws it on it's back and has 40 errors after 1 run...


Great! Make sure you stability test with 4 cycles of y-cruncher (all tests) once you've found something you think works. That and OCCT are really good at stressing the IF. 

Tried any higher??


----------



## Imprezzion

Bix said:


> Great! Make sure you stability test with 4 cycles of y-cruncher (all tests) once you've found something you think works. That and OCCT are really good at stressing the IF.
> 
> Tried any higher??


Not yet, baby steps lol. I'm just changing voltages up and down one at a time to see what voltage and what way up or down reduces the amount of WHEA's until I either give up or have no errors anymore.

It boots 1966 fine, 2000 as well but the errors are getting a bit out of hand at that point and anything over 2000 requires too high of a vSOC for me to be comfortable with. 2066 boots but it needs 1.28750v vSOC to stand a chance of getting to the desktop and that is way out of 24/7 territory.

EDIT: Fixed 3866 / 1933 for the worst of it. AIDA64 cache / memory bench is error free now. No 120 errors anymore in the copy benches lol.
Had to use quite "high" VDDG / VDDP voltages and high ProcODT but at least it's a start. L3 result is terrible but i'll blame AIDA for that lol. It's all over the place in 10 consecutive tests....

1.55v vDIMM and RAM timings are totally untested and kinda random just... slapped something in there I knew would boot. tPHYRDL does not train properly, 26/28, but that can be fixed.


----------



## Bix

Imprezzion said:


> Not yet, baby steps lol. I'm just changing voltages up and down one at a time to see what voltage and what way up or down reduces the amount of WHEA's until I either give up or have no errors anymore.
> 
> It boots 1966 fine, 2000 as well but the errors are getting a bit out of hand at that point and anything over 2000 requires too high of a vSOC for me to be comfortable with. 2066 boots but it needs 1.28750v vSOC to stand a chance of getting to the desktop and that is way out of 24/7 territory.


Sounds promising though🙂 Linpack benching is a good way of seeing what voltages your chip likes - my scores drop right off when things aren't stable whereas WHEAs can be a bit random.


----------



## Imprezzion

Bix said:


> Sounds promising though🙂 Linpack benching is a good way of seeing what voltages your chip likes - my scores drop right off when things aren't stable whereas WHEAs can be a bit random.


 It even does 1T at 3866 1933 1:1. My old B0 didn't even wanna POST 1T GDM off above 3600 but this one, all it needed was AddrCmdSetup 56 and it booted right up. Probably ain't TM5 stable yet but it's running a 1usmus 25 cycle now.


----------



## PJVol

@Veii @mongoled @ManniX-ITA etc.
I think i figured out the arg's bit fields for the THE TOOL SetDldoPsmMargin cmd ))
Oof... have to admit i went the wrong path initially, assuming that the core's Apic ID is passed in an arg's MSB (16-31 bits, as in a majority of SMU commands operating in a per-core context). So it took quite a bit of time to realize that it is a "physical" core number instead or rather its actual position in a CCX, i.e. in case you've got 5600x or 5900x, you have to know what cores exactly were deactivated. In my CPU active cores are 0,3,4,5,6 and 7, meaning that the "physical" cores 1 and 2 are "inactive".
Knowing this, we have the following arg structure:
[23:20] - physical core location number (which in case of 5800 and 5950 are the same as the usual core numbers)
[19:16] - see below
[15:0] - psm margin itself - SIGNED int.

For example, to set -10 for the Core 3 i have to pass 0x50FFF6 (enter decimal in tool's field), where 5 is actual core position, 0 presumably CCD and 0xfff6 is -10.

To verify, I just replicated my daily curve by setting psm margins (magnitudes) for each core, one-by-one, zeroing all magnitudes in the UEFI before boot.
Tuning CO on the fly is really fun  You can clearly see how PB works when tuning it while some workload is running.

One things remained to be clear is how to address the cores from the 2nd CCD. I suspect by passing the CCD number in the [19:16] field, but can't say for sure for the obvious reasons. Those having 5900/5950 though, could easily check themselves.
Don't forget that per-core command is actually called "SetAllDldoPsmMargin", whereas for the all-core you should use "DecreaseLatchupVoltageLow" command (it helps when you messed up with per-core settings and to reset the psm/F curve just exec it with 0 as an argument). Their names are shifted one item up the list.


----------



## Ezalor

TMavica said:


> My PC spec 5950x, Asus C8E mobo , G.skill F4-4000C14 GTES 16x2. I found my memory latency is too high compared to those member in forum. I have lowered my memory frequency to 3800 and FCLK 1900, there is no any crash / WHEA during the stress test, but the latency just stuck at 64 ns, maybe this is the problem of Windows 11? If not, any suggestion I can tune it lower?? Thanks!
> By the way, I cant go 1T with GDM disabled, no POST and the DRAM voltage is set to 1.45v, but the zentimings Vdimm show 1.2v
> 
> View attachment 2538909
> View attachment 2538908


Hello.
Your latency should defenately be better with your flat 14 timings, 53-55ns should be expected. Your L3 latency at 12.9ns is also quite telling that windows 11 might be the problem, 10.2 or therearound should be the level to be at with your gear.

I can not see anything obvious that would cause the high latency when it comes to your timings, but i have noted a few things of interest.

Your VDDP seems very high at 1.1v
Your VDIMM seems very low at 1.2v

Quite cool to be able to run flat 14 252 trfc at 3800 with only 1.2 volt.

Also, the sort of default standard is to do GDM off 2T, as flat 14 at 3800 with 1T is quite rare.


----------



## Audioboxer

Imprezzion said:


> Not yet, baby steps lol. I'm just changing voltages up and down one at a time to see what voltage and what way up or down reduces the amount of WHEA's until I either give up or have no errors anymore.
> 
> It boots 1966 fine, 2000 as well but the errors are getting a bit out of hand at that point and anything over 2000 requires too high of a vSOC for me to be comfortable with. 2066 boots but it needs 1.28750v vSOC to stand a chance of getting to the desktop and that is way out of 24/7 territory.
> 
> EDIT: Fixed 3866 / 1933 for the worst of it. AIDA64 cache / memory bench is error free now. No 120 errors anymore in the copy benches lol.
> Had to use quite "high" VDDG / VDDP voltages and high ProcODT but at least it's a start. L3 result is terrible but i'll blame AIDA for that lol. It's all over the place in 10 consecutive tests....
> 
> 1.55v vDIMM and RAM timings are totally untested and kinda random just... slapped something in there I knew would boot. tPHYRDL does not train properly, 26/28, but that can be fixed.
> View attachment 2539053


Funnily enough my 5950x seems to prefer 2000 to 1933/1966. Seems to be slightly more stable.

But I still haven't cracked getting it USB stable. y-cruncher test 17 just murders my CPU above 1900 FCLK lmao.


----------



## Imprezzion

Audioboxer said:


> Funnily enough my 5950x seems to prefer 2000 to 1933/1966. Seems to be slightly more stable.
> 
> But I still haven't cracked getting it USB stable. y-cruncher test 17 just murders my CPU above 1900 FCLK lmao.


1900 will not boot or post on my chip at all under any circumstance but 1933, 1966 and 2000 are totally fine. 2000 or more requires way too much vSOC however. I need at a bare minimum 1.28125 to even get to Windows without spitting 40 WHEA's during boot at 2000 lol.

1T with timings that are stable at 2T gave me 7 errors in TM5 35 cycles of 1usmus. Mostly "11" and "12" errors. I got some work to do but it will definitely do 1T on 3866 C15 1933 1:1. Probably a tad more vDIMM or a change in resistances needed. Or clkdrvstr 56 isn't enough and I need more.

I'm at around 56.x ns on 3866 15-15-8-15-30-45-270-1T on Windows 11 with L3 at 11.2 and I have gotten it to do 10.6 once but L3 bench is very inconsistent in AIDA..

EDIT: I got fed up with the slow boot times and bad latency in my dev channel old Windows 11 install so I did a fresh one with just 21H2 release channel build and decided to cut down significantly on the bloat I always tend to install like EQAPO, Peace, all the software for mouse, keyboard asf. It helped quite a lot lol. Feels much better. Latency is also much much lower. Like 2-3ns lower. And, it boots much faster.

Problem is.. I still cannot stabilize 1T. It boots fine even on 3866 1933 1:1 but it always throws random errors in TM5 no matter what I tweak so far. Anyone got any suggestions what settings to tweak to get 1T to stabilize?


----------



## Audioboxer

Something I surprisingly don't think I really looked at before is what frequency do I need to drop to, to get tRCDRD 13 stable at 32GB. Seems it'll be 3733, knowing that the rest of these timings are stable at 3800.

So 66mhz is just a step too far for tRCDRD 13 even on this kit 

Hope you all have a good Christmas and if any of you receive any new PC kit, or buy it for yourself, have fun!

*edit* - lol, ignore tRFC, its just done that because I didn't reconfigure it for a drop down in frequency.


----------



## K0N574N71N

got myself 2 b-die kits, and two unify-x boards (b550 and x570s) - will have fun


----------



## Audioboxer

K0N574N71N said:


> got myself 2 b-die kits, and two unify-x boards (b550 and x570s) - will have fun


Niiice.

Seems stock of the X570s is really good in Germany for whatever reason lol. That's two posters in this topic now that have had success in Germany!

Great boards for memory, probably the best.


----------



## Asutz

merry x max all!
phew 4x8gb dimms is tough
fiddled around severall hours and this is a result. not the best.

problem 1: lower cldo_vdpp resulted in tphyrdl missmatch it was 30/26 26/28 or 30/26 same if i changed trdwr to something lower, actually it is 26/26
problem 2: idk but maybe temps can be problematic, 8 mins tm5 was like 51°c, open case without a fan atm, that is fixable.

tested 3800 but couldnt get rid of error#1, tried the infos in the trfc calculator but no luck. some tips would be cool.thx


----------



## Owterspace

This is my 5600X.. its not really good for anything other than benching at this speed. But it will run TM5 at 2K..


----------



## PJVol

Owterspace said:


> But it will run TM5


What Vdimm it needs to pass at least 3 cycles of 1usmus config? Besides, hardly 4900mhz all core OC is doable for anything other than TM5 or aida membench.
Mind posting the AIDA Photoworxx bench result?


----------



## Owterspace

I cant do much with it at 4900, same with 2100 1:1. It is **** solid at 2K 1:1 though. I am about to order a new board, as I only have one right now and I am running my 5900X.


----------



## KedarWolf

Audioboxer said:


> Funnily enough my 5950x seems to prefer 2000 to 1933/1966. Seems to be slightly more stable.
> 
> But I still haven't cracked getting it USB stable. y-cruncher test 17 just murders my CPU above 1900 FCLK lmao.


This is TM5 1usmus_v3 25 rounds stable on the MSI B550 Unify-X A21O BIOS. I ran TM5 last night, neglected to take a screenshot though. I can't get Y-Cruncher stable on the A45 BIOS. 

I'm running really old CL16-16-16-36 3600MHz Neo RAM that I bought soon as it came out.

Edit: My MSI X570S Unify-X Max board will be here Wednesday. Apparently, according to buildzoid, they improved the memory tracing or something, but not 100% sure of that. Might be the PCB: 2oz 6-layer.


Likely, unless I can afford to get Cl14 4000 RAM, I'll only get the same timings on this RAM. :/


----------



## Imprezzion

KedarWolf said:


> This is TM5 1usmus_v3 25 rounds stable on the MSI B550 Unify-X A21O BIOS. I ran TM5 last night, neglected to take a screenshot though. I can't get Y-Cruncher stable on the A45 BIOS.
> 
> I'm running really old CL16-16-16-36 3600MHz Neo RAM that I bought soon as it came out.
> 
> Edit: My MSI X570S Unify-X Max board will be here Wednesday. Apparently, according to buildzoid, they improved the memory tracing or something, but not 100% sure of that. Might be the PCB: 2oz 6-layer.
> 
> 
> Likely, unless I can afford to get Cl14 4000 RAM, I'll only get the same timings on this RAM. :/
> View attachment 2539382
> 
> 
> View attachment 2539383


Same DIMM's I have. I wonder how you ever got tWRRD on 1 lol. I can't even dream of POST at 2 let alone 1. 4 is the best it's going to do and usually I have to run 5 or 6 for perfect stability.


----------



## KedarWolf

Imprezzion said:


> Same DIMM's I have. I wonder how you ever got tWRRD on 1 lol. I can't even dream of POST at 2 let alone 1. 4 is the best it's going to do and usually I have to run 5 or 6 for perfect stability.


Because I'm running tCWL at 12.


----------



## Taraquin

Help me identifying IC on ram? Helping a relative upgrading his pc. 
5600X
B450 Aorus pro agesa 1.2.0.3B
2x16 Kingston fury 3600cl18-22-22

Thaiphoon says Hynix A. Bios handles them as single rank, Zentimings say SR. 

After a lot if testing I ended up at lowest stable with a few exceptions noted:
3800/1900
16 21 21 19 37 (RAS might do lower)
RC 56 (might do lower)
RRD 5/7
FAW 20
RFC 560
CWL 16
WR/RTP 16/8 (might do lower)
RDWR 8
WRRD 3 (might do lower)
WTR 4/12 (might do lower)
GDM on (to make it easier) 

So I'm still confused, RFC seems Micron B since Hynix usually can do sub 500 at 3800, RP and FAW seems Hynix since Micron usually does 16 with ease. Improved dram calc test from 160sec to 124sec going from XMP 3600 to the above so not bad. I must test a bit further with RC, WTR and WR/RTP, but looks like I'm close to the limit.

Any idea what this kit actually is?


----------



## Imprezzion

Finally got 1T GDM Off to stabilize at 3600 straight 15's 1.50v vDIMM. Had to tweak the resistances and RTT's, run AddrCmdSetup at 56, and slightly higher ProcODT then I run at 2T but it works.
I will of course let it run the full 25 cycles but this is a nice improvement.

It will boot 1T as high as 3866 with 1:1 FCLK but it's very hard to stabilize at that point and will mostly throw errors after 30-40 minutes of TM5. Never earlier.
CPU has a FCLK hole at 1900 and cannot boot 1900 regardless of voltages or settings but 1933-1966 is no problem. It does still have 1-2 WHEA's in 24 hours of day to day usage but I can probably fix those with a slight tweak in CLDO IOD and CCD voltages or just.. ignore them 

I also have a problem with CAS 14 on 3600. The DIMM's can do it just fine but it will not train tPHYRDL no matter what I do. It's always 26/28 on 1T. On 2T it's fine 26/26.. Only uneven CAS will train so 17,15,13 is fine but 16,14 will not do 26/26..

I might try to get 13-15-15 or even 13-14-14 to run but that probably needs way too much vDIMM for me to be comfortable with. 15 already needs 1.50v at 1T so I can only imagine what 13 needs.. 1.65? And judging by my DIMM temps at 1.50 I can't get away with that high of a vDIMM..










EDIT: Well, I didn't expect that.. It CAN run CAS 13 quite easily lol.. Only 1.590v vDIMM and temps didn't go up at all even tho ambients went up slightly.
Lot's more to tweak but this is a great daily profile to save in the BIOS.










EDIT 2: I seem to have broken something lol while CAS 13 passes stress tests fine bench performance is totally terrible. AIDA latency is like 64ns, L3 cache is terrible, Cinebench lost like 400 points, CPU-Z is down 200 points.. what did I do lol.


----------



## Asutz

can only speak for my asus board, auto cldo_vdpp which resulted in 1.09x mv and mem trained 26/26 on all 4 banks, changing trdwr or twrrd other then auto missmatch starting, either 26/28 or 26/30 had a 30/26 or 26/30 too. so idk, maybe mem training is buggy or i am missing something, no expert.


----------



## Imprezzion

All I am seeing right now is non-existent scaling 13-15-15 with tighter subtimings has exactly the same scores, bandwidth and latency as for example 3600 15-15-15 with loose subs. Latency is just around 57.5ns and doesn't budge at all.


----------



## Asutz

quick tm5 default
errors 0,1,2,3,4,5
idk, timings arnt that tight, ideas?
more voltage did not help, lower rttpark or procodt changes ill get f9 after post

edit: gdm on and procodt change, tm5 quick with default 5 tests no error, cmd setup maybe not needed then


----------



## Imprezzion

Asutz said:


> quick tm5 default
> errors 0,1,2,3,4,5
> idk, timings arnt that tight, ideas?
> more voltage did not help, lower rttpark or procodt changes ill get f9 after post
> 
> edit: gdm on and procodt change, tm5 quick with default 5 tests no error, cmd setup maybe not needed then
> View attachment 2539453
> View attachment 2539455


Straight 15's on 1.46v for 3733? My 3600C16's need a lot more vDIMM then that on those clocks. More like 1.54v. Especially on 1T.


----------



## Asutz

3600c15 xmp is @1.35v, didnt test but maybe 1,4v is fine for 3733 too at least for gdm on , was in the assumption that 1,5v for gdm off 1t test should be more than enough, had like 100+ errors on a quick test and not sure if even more voltage will fix those.
another point, maybe 4 dimms really need much more cldo vddp, cant find much infos about that.


----------



## Imprezzion

Asutz said:


> 3600c15 xmp is @1.35v, didnt test but maybe 1,4v is fine for 3733 too at least for gdm on , was in the assumption that 1,5v for gdm off 1t test should be more than enough, had like 100+ errors on a quick test and not sure if even more voltage will fix those.
> another point, maybe 4 dimms really need much more cldo vddp, cant find much infos about that.


Wait, you run 4 DIMM's? That kinda changes things. And yes, your bin is much higher then mine lol. 
I can technically do 3600 13-15-15 at 1.59v but it doesn't perform any better in AIDA or Cinebench or CPU-Z or whatever then 3600 15-15-15 does on way less voltage. tCL doesn't scale at all for me beyond a certain point lol.


----------



## Asutz

yes 4 dimms so that sandwich is "hot" alone, dont think a much higher procodt will really help, didnt found the perfect combination, at least 7/0/5 24 20 24 24 works, cldo changes often bringing missmatches and dont know the "sweet spot" for 4 dimms, maybe will try 1.050 to not destroy something.


----------



## Imprezzion

This is the current daily profile. Not much room to tweak anymore.
I still wanna run 3866/3933 quite a lot even on 2T it's much faster bandwidth AND latency wise but I just can't seem to be able to stabilize it.. Even at timings I know are stable from my previous CPU.
















EDIT: What value in the setup below is most likely to trigger a #11 and #12 error in TM5 1usmus 25 cycle?


----------



## Audioboxer

KedarWolf said:


> This is TM5 1usmus_v3 25 rounds stable on the MSI B550 Unify-X A21O BIOS. I ran TM5 last night, neglected to take a screenshot though. I can't get Y-Cruncher stable on the A45 BIOS.
> 
> I'm running really old CL16-16-16-36 3600MHz Neo RAM that I bought soon as it came out.
> 
> Edit: My MSI X570S Unify-X Max board will be here Wednesday. Apparently, according to buildzoid, they improved the memory tracing or something, but not 100% sure of that. Might be the PCB: 2oz 6-layer.
> 
> 
> Likely, unless I can afford to get Cl14 4000 RAM, I'll only get the same timings on this RAM. :/
> View attachment 2539382
> 
> 
> View attachment 2539383


I can run TM5 and Karhu stable as well at FCLK 2000  No USB disconnects. Seems the memory testing apps don't stress the CPU enough to cause issues.

Once y-cruncher test 17 kicks off I'm done within a minute or two lol. It's not that test 17 actually fails, it's just the USB goes crazy which is as good as failing. Serious instability.


----------



## Asutz

@Imprezzion 
tRFC mini tm5 error discription


----------



## KedarWolf

Bit off-topic, but I'm pretty sure my BSOD issues with Windows 11 I never got with Window 10 were from a slightly unstable overclock

Once I got my 5950x and memory Core Cycler, TM5, stressapptest, Linpack Xtreme AND Y-Cruncher stable, no BSODs in 11. stressapptest and Y-Cruncher were the most important ones.

I need to game some to be sure, but it's been a day so far and I couldn't even go more than 5-6 hours without a BSOD.


----------



## domdtxdissar

domdtxdissar said:


> So i got intrigued by the tCWL10 and decided to test some different memory settings to see what really performed best in different memory benchmarks, little did i know how much time this would really take 😅
> 
> These are the settings i decided to have a showdown between:
> View attachment 2536836
> 
> 
> 
> A few words before we get into the data
> 
> All benchmarks were run with a static OC @ a lowish 4600/4500mhz, so everyone with a 5950x should be able to compare numbers if they want
> After each benchmark computer was restarted, and after each restart the computer was left idling for 1min so windows could start all processes in peace
> Benchmarks was performed on a newly installed GHOSTSPECTRE SUPERLIGHT Win10 OS. (around 94 processes running after 1 min idling)
> Difficulty for the Menero Miner XMR-stak-rx was "480045" for all runs
> I have screenshots for every benchmark if requested
> 
> 
> 
> Spoiler: Benchmarks
> 
> 
> 
> start
> 
> *Benchmate wPrime 1.5.0.5*
> 
> Baseline:
> 
> Run1 = 34.700 sec
> Run2 = 34.622 sec
> Run3 = 34.761 sec
> Average = 34.694 sec
> 
> Baseline -SCL2:
> 
> Run1 = 34.672 sec
> Run2 = 34.677 sec
> Run3 = 34.702 sec
> Average = 34.683 sec
> 
> -2tCWL +2tRDWR:
> 
> Run1 = 34.773 sec
> Run2 = 34.698 sec
> Run3 = 34.767 sec
> Average = 34.732 sec
> 
> -2tCWL +2tRDWR -2SCL:
> 
> Run1 = 34.763 sec
> Run2 = 34.819 sec
> Run3 = 34.686 sec
> Average = 34.756 sec
> 
> Correct tRAS:
> 
> Run1 = 34.709 sec
> Run2 = 34.773 sec
> Run3 = 34.693 sec
> Average = 34.725 sec
> 
> Flat tCL14 :
> 
> Run1 = 34.799 sec
> Run2 = 34.834 sec
> Run3 = 34.713 sec
> Average = 34.782 sec
> 
> *Corona 1.3 Benchmark:*
> 
> Baseline:
> 
> Run1 = 11.812.500 Reys/sec
> Run2 = 11.822.300 Reys/sec
> Run3 = 11.853.700 Reys/sec
> Average = 11.829.500 Reys/sec
> 
> Baseline -SCL2:
> 
> Run1 = 11.748.000 Reys/sec
> Run2 = 11.749.700 Reys/sec
> Run3 = 11.836.600 Reys/sec
> Average = 11.778.100 Reys/sec
> 
> -2tCWL +2tRDWR:
> 
> Run1 = 11.735.800 Reys/sec
> Run2 = 11.772.700 Reys/sec
> Run3 = 11.767.900 Reys/sec
> Average = 11.758.800 Reys/sec
> 
> -2tCWL +2tRDWR -2SCL:
> 
> Run1 = 11.783.300 Reys/sec
> Run2 = 11.778.700 Reys/sec
> Run3 = 11.786.400 Reys/sec
> Average = 11.782.800 Reys/sec
> 
> Correct tRAS:
> 
> Run1 = 11.804.200 Reys/sec
> Run2 = 11.813.100 Reys/sec
> Run3 = 11.818.200 Reys/sec
> Average = 11.811.833 Reys/sec
> 
> Flat tCL14:
> 
> Run1 = 11.786.700 Reys/sec
> Run2 = 11.793.000 Reys/sec
> Run3 = 11.792.200 Reys/sec
> Average = 11.790.633 Reys/sec
> 
> *Linpack Xtreme 1.1.5*
> 
> Baseline:
> 
> Run1 = 673.6121 GFlops
> Run2 = 672.5934 GFlops
> Run3 = 672.7430 GFlops
> Average = 672.9828 GFlops
> 
> Baseline -SCL2:
> 
> Run1 = 671.7620 GFlops
> Run2 = 671.3653 GFlops
> Run3 = 670.6409 GFlops
> Average = 671.2561 GFlops
> 
> -2tCWL +2tRDWR:
> 
> Run1 = 672.5900 GFlops
> Run2 = 672.1730 GFlops
> Run3 = 672.1913 GFlops
> Average = 672.3181 GFlops
> 
> -2tCWL +2tRDWR -2SCL:
> 
> Run1 = 670.3983 GFlops
> Run2 = 669.1971 GFlops
> Run3 = 669.5059 GFlops
> Average = 669.7004 GFlops
> 
> Correct tRAS:
> 
> Run1 = 671.6125 GFlops
> Run2 = 671.0436 GFlops
> Run3 = 670.6122 GFlops
> Average = 671.6122 GFlops
> 
> Flat tCL14:
> 
> Run1 = 668.8344 GFlops
> Run2 = 668.2137 GFlops
> Run3 = 668.1432 GFlops
> Average = 668.3971 GFlops
> 
> *IntelBurnTest v2.54: Very high stresslevel*
> 
> Baseline:
> 
> Run1 = 234.9265 GFlops
> Run2 = 235.5467 GFlops
> Run3 = 235.8574 GFlops
> Average = 235.4435 GFlops
> 
> Baseline -SCL2:
> 
> Run1 = 235.5185 GFlops
> Run2 = 235.6311 GFlops
> Run3 = 234.5461 GFlops
> Average = 235.2319 GFlops
> 
> -2tCWL +2tRDWR:
> 
> Run1 = 234.5213 GFlops
> Run2 = 234.4156 GFlops
> Run3 = 234.4483 GFlops
> Average = 234.4617 GFlops
> 
> -2tCWL +2tRDWR -2SCL:
> 
> Run1 = 234.0640 GFlops
> Run2 = 234.2016 GFlops
> Run3 = 235.6987 GFlops
> Average = 234.6547 GFlops
> 
> Correct tRAS:
> 
> Run1 = 234.9590 GFlops
> Run2 = 234.8467 GFlops
> Run3 = 237.0151 GFlops <-- outliner
> Average = 235.6069 GFlops
> 
> Flat tCL14:
> 
> Run1 = 233.8859 GFlops
> Run2 = 234.8498 GFlops
> Run3 = 235.7551 GFlops
> Average = 234.8302 GFlops
> 
> *Menero Miner XMR-stak-rx *
> 
> Baseline:
> 
> Average after 15min = 19709.4 H/s
> Highest = 19728.5 H/s
> 
> Baseline -SCL2:
> 
> Average after 15min = 19625.1 H/s
> Highest = 19641.9 H/s
> 
> -2tCWL +2tRDWR:
> 
> Average after 15min = 19605.5 H/s
> Highest = 19621.7 H/s
> 
> -2tCWL +2tRDWR -2SCL:
> 
> Average after 15min = 19655.7 H/s
> Highest = 19677.9 H/s
> 
> Correct tRAS:
> 
> Average after 15min = 19571.3 H/s
> Highest = 19585.1 H/s
> 
> Flat tCL14:
> 
> Average after 15min = 19509.0 H/s
> Highest = 19521.3 H/s
> 
> 
> 
> 
> 
> 
> 
> End comments:
> 
> Like previously found, my "baseline" seems to be the fastest profile overall, for my system atleast.
> SCL2 almost always seems to lower the performance on my 2x16GB dualrank setup. (in aida64 you see higher write but lower read)
> tCWL10 didn't seem to make up from the performance loss from being forced to run tRDWR11 instead of 9. (or the bios is actually not running tCWL10 like it says it is)
> "Flat tCL14" seems to be the slowest profile.
> The Menero Miner seemingly really likes low tRAS+tRC, even when its below the "calculated minimum".
> As with pretty much all "memory benchmarks", CPU clockspeed is king... Don't spend your power budget on SOC if that mean lower cpu boosting.


*MERRY (MSI UNIFY) X-MAX EVERYONE *🎅

Have continued the testing from above now that i finally have motherboard that can handle dualrank 2x16 all the way up to 4400MT/s (async)
In this session i was focusing on infinity fabric speeds above 1900 and the scaling in Linpack extreme (as we know can be worstcase)

All testing was performed at same (lax) memory settings and static cpu clockspeed @ 4600/4500mhz
WHEA suppressor = enabled

1833:3666 = 651.5784 average GFlops









1866:3733 = 655.2794 average GFlops (+3.701 GFlops)









1900:3800 = 657.5407 average GFlops (+2.261 GFlops)









1933:3866 = 357.5543 average GFlops









1966:3933 = 437.6164 average GFlops









2000:4000 = 204.0170 average GFlops









As we can see, there is only scaling in light "benchmarks" such as Aida64 above 1900 flck (for my system), but as soon as i hit it with a real heavy workload, the performance is out the window..
Seems like i'm stuck at 1900:3800 even with this new motherboard, until i get a new Zen3 v-$ CPU. (crossing fingers i will get a sample that can handler higher flck)

And what's even more funny, i even completed a full suite of worst of the worst stresstests @ 2000:4000 speeds and non of them failed.








1 hour OCCT large dataset -> completed
2 hours y-cruncher torture test with all enabled -> completed
100% runmemtestpro -> completed
1 hour karhu ram test -> completed

*So just a friendly advice to everyone who want to run high infinity fabric speeds.. You should test it in other performance benchmarks than Aida64 to see if its really worth it.*

_edit_
For a comparison, with my true and tested daily 24/7 memory-settings, at the same cpu clockspeed
1900:3800 = 671.2721 average GFlops







Should be able to break 700GFlops if pushed


----------



## domdtxdissar

PJVol said:


> Btw, it'd be nice if you could make it clear what was meant under the “easymode APU's”, and, perhaps, *point out the results that, in your opinion, do not deserve to be there (hidden whea's or whatever).*
> Thanks.


This is how easy it would have been for me to take a top ranking on the "Zen DDR4 OC Leaderboards" google doc with a "undeserving" run. (full WHEA throttling in all real performance benchmarks)
















And this is exactly the same settings as i completed all the stresstesting in my previous post also..
And it would have given me #1 with 2x16gb, #1 with dual CCD enabled and #10 for overall latency

And noone would be the wiser, without me coming out and actually telling the truth 

*Merry Christmas and happy new year everyone *


----------



## Imprezzion

Hmm. A error #10 and #13 right after each other after 13 cycles (1h17m). DIMM temps around 42.5c so not that hot yet. 

Both point, according to the excel sheet, to possibly too low RTT_NOM and/or too high vDIMM so I adjusted vDIMM from 1.5900 --> 1.5800 and RTT_NOM from RZQ/5 to RZQ/6 (if that's even the right way) and we test again lol.

I'm at 3866 1933 1:1 with 14-15-8-15-29-44-264-2T primaries. I did mess up and set tWR to 10 and tRTP to 6 in stead of 5. How much of a problem is that going to possibly be? If it is a real issue I'll stop the test and change it first otherwise I'll let it complete like 20 cycles first.


----------



## Taraquin

domdtxdissar said:


> *MERRY (MSI UNIFY) X-MAX EVERYONE *🎅
> 
> Have continued the testing from above now that i finally have motherboard that can handle dualrank 2x16 all the way up to 4400MT/s (async)
> In this session i was focusing on infinity fabric speeds above 1900 and the scaling in Linpack extreme (as we know can be worstcase)
> 
> All testing was performed at same (lax) memory settings and static cpu clockspeed @ 4600/4500mhz
> WHEA suppressor = enabled
> 
> 1833:3666 = 651.5784 average GFlops
> View attachment 2539494
> 
> 
> 1866:3733 = 655.2794 average GFlops (+3.701 GFlops)
> View attachment 2539495
> 
> 
> 1900:3800 = 657.5407 average GFlops (+2.261 GFlops)
> View attachment 2539496
> 
> 
> 1933:3866 = 357.5543 average GFlops
> View attachment 2539497
> 
> 
> 1966:3933 = 437.6164 average GFlops
> View attachment 2539498
> 
> 
> 2000:4000 = 204.0170 average GFlops
> View attachment 2539499
> 
> 
> As we can see, there is only scaling in light "benchmarks" such as Aida64 above 1900 flck (for my system), but as soon as i hit it with a real heavy workload, the performance is out the window..
> Seems like i'm stuck at 1900:3800 even with this new motherboard, until i get a new Zen3 v-$ CPU. (crossing fingers i will get a sample that can handler higher flck)
> 
> And what's even more funny, i even completed a full suite of worst of the worst stresstests @ 2000:4000 speeds and non of them failed.
> View attachment 2539500
> 
> 1 hour OCCT large dataset -> completed
> 2 hours y-cruncher torture test with all enabled -> completed
> 100% runmemtestpro -> completed
> 1 hour karhu ram test -> completed
> 
> *So just a friendly advice to everyone who want to run high infinity fabric speeds.. You should test it in other performance benchmarks than Aida64 to see if its really worth it.*
> 
> _edit_
> For a comparison, with my true and tested daily 24/7 memory-settings, at the same cpu clockspeed
> 1900:3800 = 671.2721 average GFlops
> View attachment 2539504
> 
> Should be able to break 700GFlops if pushed


Good job! For my setup I need 1060mv soc and 980mv iod to run 1900 IF WO perf regression, 2000 IF needs 1110mv soc and 1030 iod so perfect scaling with about 5% more soc/iod for 5% more IF. Vddp and ccd kept at 830mv. For 2033 and 2066 IF I need to increase soc by 0.05v and iod by 0.02v so not worth it at all. Going from 1900 to 2000 increases IO-die consumption by 1-2W, in CB, Y-cruncher etc translating to 25MHz allcore speed lost and scores about 1% lower. In SOTTR I get about 2% higher fps using 2000 IF vs 1900 (4000cl16 1T tuned vs 3800cl15 1T tuned).

My wrap up: If frequency/voltagescaling is linear then higher IF may be worth it if the app/game prefer mem BW over CPU speed, but you will lose a bit of frequency unless you run static OC or already max out CPU frequency like for instance running -30 CO and 0 pbo on a 5600X or 5800X.

On avg I think going above 1900 IF and voltage scaling is not linear then you will lose perf in most cases.


----------



## Audioboxer

domdtxdissar said:


> *MERRY (MSI UNIFY) X-MAX EVERYONE *🎅
> 
> Have continued the testing from above now that i finally have motherboard that can handle dualrank 2x16 all the way up to 4400MT/s (async)
> In this session i was focusing on infinity fabric speeds above 1900 and the scaling in Linpack extreme (as we know can be worstcase)
> 
> All testing was performed at same (lax) memory settings and static cpu clockspeed @ 4600/4500mhz
> WHEA suppressor = enabled
> 
> 1833:3666 = 651.5784 average GFlops
> View attachment 2539494
> 
> 
> 1866:3733 = 655.2794 average GFlops (+3.701 GFlops)
> View attachment 2539495
> 
> 
> 1900:3800 = 657.5407 average GFlops (+2.261 GFlops)
> View attachment 2539496
> 
> 
> 1933:3866 = 357.5543 average GFlops
> View attachment 2539497
> 
> 
> 1966:3933 = 437.6164 average GFlops
> View attachment 2539498
> 
> 
> 2000:4000 = 204.0170 average GFlops
> View attachment 2539499
> 
> 
> As we can see, there is only scaling in light "benchmarks" such as Aida64 above 1900 flck (for my system), but as soon as i hit it with a real heavy workload, the performance is out the window..
> Seems like i'm stuck at 1900:3800 even with this new motherboard, until i get a new Zen3 v-$ CPU. (crossing fingers i will get a sample that can handler higher flck)
> 
> And what's even more funny, i even completed a full suite of worst of the worst stresstests @ 2000:4000 speeds and non of them failed.
> View attachment 2539500
> 
> 1 hour OCCT large dataset -> completed
> 2 hours y-cruncher torture test with all enabled -> completed
> 100% runmemtestpro -> completed
> 1 hour karhu ram test -> completed
> 
> *So just a friendly advice to everyone who want to run high infinity fabric speeds.. You should test it in other performance benchmarks than Aida64 to see if its really worth it.*
> 
> _edit_
> For a comparison, with my true and tested daily 24/7 memory-settings, at the same cpu clockspeed
> 1900:3800 = 671.2721 average GFlops
> View attachment 2539504
> 
> Should be able to break 700GFlops if pushed


No USB issues whilst running y-cruncher? I'm guessing given the similarities of our setups that is 100% down to the CPUs capability above 1900.


----------



## PJVol

domdtxdissar said:


> This is how easy it would have been for me
> ...


It only would if you accept and okay with...


domdtxdissar said:


> (full WHEA throttling in all real performance benchmarks)


In fact, it's rather the opposite, assuming you're counting on somewhat positive perf. scaling.
My biggest challenge was the 4066/2033 result, since at the time firmware was not perfect, and it took me some couple of weeks to get there.
I finally managed to bring about settings that suffered only in selected heavy AVX2 benchmarks, which i didn't care much tbh.
The thing is that it wasn't the only issue, rather some config-specific ones, especially MB related, has kept me away at the end.



domdtxdissar said:


> And noone would be the wiser, without me coming out and actually telling the truth


You may not have noticed, but this shocking "discovery" is being made in this thread, I think, once in a month ... 
But thanks anyway for not letting anyone forget


----------



## domdtxdissar

Audioboxer said:


> No USB issues whilst running y-cruncher?


Was not using the computer while running the benchmarks, but when i got back to it everything was working normally. Do you only get usb problems while running y-cruncher or do you need to restart to computer after triggering it ?



PJVol said:


> In fact, it's rather the opposite, assuming you're counting on somewhat positive perf. scaling.
> My biggest challenge was the 4066/2033 result, since at the time firmware was not perfect, and it took me some couple of weeks to get there.
> I finally managed to bring about settings that suffered only in selected heavy AVX2 benchmarks, which i didn't care much tbh.


What are you talking about ? Maybe something got lost in translation, i'm not talking about any of your runs..
I'm trying to show why i dont find the google doc particularly useful when trying to find the "best/fastest memory settings" when its this easy to manipulate/hide problems.. (Well its actually Aida64 that is a bad proxy for "real performance" in my book)



PJVol said:


> You may not have noticed, but this shocking "discovery" is being made in this thread, I think, once in a month ...
> But thanks anyway for not letting anyone forget


Still dont know what your on about. ? It kinda seems like you feel targeted by my testing on scaling above 1900.. Why is that ?
I'm providing some hard numbers instead of just talk, on a problem i haven't been able to test/show before now. More data is always a good thing in my world, but it you act very defensive about this.. Hopefully i just "misunderstand your intent" again


----------



## Audioboxer

domdtxdissar said:


> Was not using the computer while running the benchmarks, but when i got back to it everything was working normally. Do you only get usb problems while running y-cruncher or do you need to restart to computer after triggering it ?
> 
> 
> What are you talking about ? Maybe something got lost in translation, i'm not talking about any of your runs..
> I'm trying to show why i dont find the google doc particularly useful when trying to find the "best/fastest settings" when its this easy to manipulate/hide problems.. (Well its actually Aida64 that is a bad proxy for "real performance" in my book)
> 
> 
> Still dont know what your on about. ? It kinda seems like you feel targeted by my testing on scaling above 1900.. Why is that ?


It's just USB disconnecting/reconnecting. If I let it keep going the test doesn't actually fail, the reason I normally stop it is because I have a commander pro that configures my watercooling pump speed/fan curves and if I allow it to keep disconnecting/reconnecting it really screws it up. All profiles get lost and the hub thinks it needs to do a firmware update to be usable again.

Run y-cruncher test 17 only and see if your keyboard/mouse disconnect/reconnect. If you've got RGB lights on the keyboard/mouse this is a good way to see if it's disconnecting/reconnecting really quickly. If you're away from the computer whilst y-cruncher is running I guess you might not notice anything, especially if you're like me and the actual CPU doesn't cause any errors/reboots, it's just USB issues.


----------



## domdtxdissar

Audioboxer said:


> It's just USB disconnecting/reconnecting. If I let it keep going the test doesn't actually fail, the reason I normally stop it is because I have a commander pro that configures my watercooling pump speed/fan curves and if I allow it to keep disconnecting/reconnecting it really screws it up. All profiles get lost and the hub thinks it needs to do a firmware update to be usable again.


Ah okai, i only have connected mouse/keyboard and headset on usb, so not much that can go wrong 🙃


Audioboxer said:


> Run y-cruncher test 17 only and see if your keyboard/mouse disconnect/reconnect. If you've got RGB lights on the keyboard/mouse this is a good way to see if it's disconnecting/reconnecting really quickly. If you're away from the computer whilst y-cruncher is running I guess you might not notice anything, especially if you're like me and the actual CPU doesn't cause any errors/reboots, it's just USB issues.


Well.. My system show massive performance throttling above 1900:3800 in all but the lightest workloads, so dont think there is much point for me to do anymore stresstests/benchmarks on settings that simple dont work for me / will never run

But if your really just curious on how other systems behave compared to your own, let me know and i will reconfigure all my settings again and do the test


----------



## Imprezzion

It doesn't USB disconnect for me but it does cause a WHEA every few minutes ish on 3866 RAM 1933 FCLK.

Let me grab my 3600 / 1800 profile and see if that stays clean.

Btw, is there something special I have to do in order to set up unsynced RAM? Like, what if I wanna test 4400 C17 for the RAM but I wanna run unsynced for the test. How do I set that up?


----------



## domdtxdissar

Imprezzion said:


> It doesn't USB disconnect for me but it does cause a WHEA every few minutes ish on 3866 RAM 1933 FCLK.
> 
> Let me grab my 3600 / 1800 profile and see if that stays clean.


Remove your WHEA's with the WHEA errors suppressor here.. Maybe improve your performance when your windows aint getting flooded by whea error messages
Credits *ManniX-ITA*


Imprezzion said:


> Btw, is there something special I have to do in order to set up unsynced RAM? Like, what if I wanna test 4400 C17 for the RAM but I wanna run unsynced for the test. How do I set that up?


Just set memory clockspeed at a other number than the infinity fabric and you are running async. For example, start at something like flck 3200 and memclock 3800, UCLK @ half MEMCLK and work your way up the memclock ladder..










Imprezzion said:


> Yeah but it refused to POST so I thought maybe I'd have to set a specific IF clock or whatever. But 4400 RAM + 1800 FCLK should work?


Yes it should work.. This is 4400:1900:1100 asynced


----------



## Imprezzion

domdtxdissar said:


> Remove your WHEA's with the WHEA errors suppressor here
> Credits *ManniX-ITA*
> 
> Just set memory clockspeed at a other number than the infinity fabric and you are running async


Yeah but it refused to POST so I thought maybe I'd have to set a specific IF clock or whatever. But 4400 RAM + 1800 FCLK should work?


----------



## Audioboxer

domdtxdissar said:


> Remove your WHEA's with the WHEA errors suppressor here.. Maybe improve your performance when your windows aint getting flooded by whea error messages
> Credits *ManniX-ITA*
> 
> Just set memory clockspeed at a other number than the infinity fabric and you are running async. For example, start at something like flck 3200 and memclock 3800, UCLK @ half MEMCLK and work your way up the memclock ladder..
> View attachment 2539549
> 
> 
> Yes it should work.. This is 4400:1900:1100 asynced
> View attachment 2539550


I'm going to guess even at 4400 the latency penalty still isn't worth it with 1900? 

Really sucks how much these kits are held back on AMD due to the memory controller.


----------



## domdtxdissar

Audioboxer said:


> I'm going to guess even at 4400 the latency penalty still isn't worth it with 1900?
> 
> Really sucks how much these kits are held back on AMD due to the memory controller.


Some workloads scale better with bandwidth than latency, for those workloads its actually worth it to run decoupled
Prime example is y-cruncher.. pretty much all it want is bandwidth like i wrote earlier
In other benchmarks/games latency is more important.. So it kinda depends on what speeds you can achieve synced vs asynced and what you plan using your computer for


















domdtxdissar said:


> Think the 5950x must be bandwidth limited or something else seeing how little performance increase there is going from stock clocks @ 142w to all out maxed cpu @ 4700/4600mhz sucking down ~300w
> *The time only decreased from 69 seconds to 62 seconds  (barely 11% faster)*


----------



## Asutz

can somebody explain me error #3 here? just for testing, took xmp and just switched off gdm and set it to 2t.
i've checked error description, gdm on runnning without error so it cant be rttnom or trrdl ? voltage is 1.36v, dont think its too low.cluesless as usual

edit:rttnom to 6 changed error #3 to #5
tRDWR/tWRRD while for bigger datasets tRP, tRFC is in the description, too high trdwr/twrrd can cause errors too ?!
but why does it run error free with gdm on ? the only change with gdm on is tcl 16 if i'm not wrong.


----------



## Imprezzion

domdtxdissar said:


> Some workloads scale better with bandwidth than latency, for those workloads its actually worth it to run decoupled
> Prime example is y-cruncher.. pretty much all it want is bandwidth like i wrote earlier
> In other benchmarks/games latency is more important.. So it kinda depends on what speeds you can achieve synced vs asynced and what you plan using your computer for
> View attachment 2539553
> 
> View attachment 2539554


How's synced 3666 1833 C15 1T vs unsynced 4400 1933 C17 2T for strictly gaming and nothing else?

I tried to get my 4400C17 timings I had on my 10900KF to boot but it failed POST and went into safe mode recovery. So I have to tweak some stuff to make it work.


----------



## PJVol

domdtxdissar said:


> What are you talking about ? Maybe something got lost in translation, i'm not talking about any of your runs..


Hmm... just replied to your post below? (unless someone else posted that)


domdtxdissar said:


> This is how easy it would have been for me to take a top ranking on the "Zen DDR4 OC Leaderboards" google doc with a "undeserving" run. (full WHEA throttling in all real performance benchmarks)


Maybe you missed the beginning, where I said it won't be easy, if you're not gonna sacrifice MT performance, and then shared my experience with it.


----------



## Luggage

@Audioboxer get rid of commander pro


----------



## Audioboxer

Luggage said:


> @Audioboxer get rid of commander pro


lol, after disabling some iCUE services and one of the startup processes, it's not too bad. At least I don't have 6 different pieces of RGB software, mobo apps and goodness knows what else some modern PCs probably have running. Everything is controlled from the one app.

I also tend to quit iCUE if nothing needs tweaked, so its just running off the settings saved to the commander memory.

At the end of the day USB disconnects mean unstable, so even if I didn't have a commander pro and it was just the keyboard/mouse freaking out, I just wouldn't feel right using such a setup daily. Chances are if I do some proper benching my CPU would see performance regression anyway.

Only thing that seems to see use on this rig above 1900 FCLK is memory stability testing and maybe some memory benching. Just have to cross my fingers the 3D cache chips aren't complete duds when it comes to FCLK.


----------



## Taraquin

domdtxdissar said:


> *MERRY (MSI UNIFY) X-MAX EVERYONE *🎅
> 
> Have continued the testing from above now that i finally have motherboard that can handle dualrank 2x16 all the way up to 4400MT/s (async)
> In this session i was focusing on infinity fabric speeds above 1900 and the scaling in Linpack extreme (as we know can be worstcase)
> 
> All testing was performed at same (lax) memory settings and static cpu clockspeed @ 4600/4500mhz
> WHEA suppressor = enabled
> 
> 1833:3666 = 651.5784 average GFlops
> View attachment 2539494
> 
> 
> 1866:3733 = 655.2794 average GFlops (+3.701 GFlops)
> View attachment 2539495
> 
> 
> 1900:3800 = 657.5407 average GFlops (+2.261 GFlops)
> View attachment 2539496
> 
> 
> 1933:3866 = 357.5543 average GFlops
> View attachment 2539497
> 
> 
> 1966:3933 = 437.6164 average GFlops
> View attachment 2539498
> 
> 
> 2000:4000 = 204.0170 average GFlops
> View attachment 2539499
> 
> 
> As we can see, there is only scaling in light "benchmarks" such as Aida64 above 1900 flck (for my system), but as soon as i hit it with a real heavy workload, the performance is out the window..
> Seems like i'm stuck at 1900:3800 even with this new motherboard, until i get a new Zen3 v-$ CPU. (crossing fingers i will get a sample that can handler higher flck)
> 
> And what's even more funny, i even completed a full suite of worst of the worst stresstests @ 2000:4000 speeds and non of them failed.
> View attachment 2539500
> 
> 1 hour OCCT large dataset -> completed
> 2 hours y-cruncher torture test with all enabled -> completed
> 100% runmemtestpro -> completed
> 1 hour karhu ram test -> completed
> 
> *So just a friendly advice to everyone who want to run high infinity fabric speeds.. You should test it in other performance benchmarks than Aida64 to see if its really worth it.*
> 
> _edit_
> For a comparison, with my true and tested daily 24/7 memory-settings, at the same cpu clockspeed
> 1900:3800 = 671.2721 average GFlops
> View attachment 2539504
> 
> Should be able to break 700GFlops if pushed


So I did a simliar test and got very different results from you with Linpack.

First up my daily setup, I never have WHEA 19.









Then same voltages, timings etc at 3800\1900:










Then tweaked voltages\timings on my 3800cl15 daily optional:










Result:
Very slight negative scaling past 3800\1900, I bet this is due to 4000\2000 requiring more power on settings hidden from me, I watched HWMonitor while running linpack and 3800 boosts slightly higher allcore.

3800cl15 with optimized voltages gets 1% better due to better powerbudget for CPU.

I agree that testing above 3800\1900 is required as some systems like yours get very bad scaling, while others like mine change very little.


----------



## Luggage

Taraquin said:


> So I did a simliar test and got very different results from you with Linpack.
> 
> First up my daily setup, I never have WHEA 19.
> View attachment 2539594
> 
> 
> Then same voltages, timings etc at 3800\1900:
> 
> View attachment 2539595
> 
> 
> Then tweaked voltages\timings on my 3800cl15 daily optional:
> 
> View attachment 2539596
> 
> 
> Result:
> Very slight negative scaling past 3800\1900, I bet this is due to 4000\2000 requiring more power on settings hidden from me, I watched HWMonitor while running linpack and 3800 boosts slightly higher allcore.
> 
> 3800cl15 with optimized voltages gets 1% better due to better powerbudget for CPU.
> 
> I agree that testing above 3800\1900 is required as some systems like yours get very bad scaling, while others like mine change very little.


Yea it’s the higher soc stealing power budget


----------



## hazium233

domdtxdissar said:


> This is how easy it would have been for me to take a top ranking on the "Zen DDR4 OC Leaderboards" google doc with a "undeserving" run. (full WHEA throttling in all real performance benchmarks)


My humble opinion is that sheet really needs to be broken into two sheets. One with an actual stability test length that makes sense for daily operation, and one that can be called "leaderboard" for more extreme OC. Right now it is all over the place with just the "20 minute" testing requirement, and some submissions don't even have this.



Asutz said:


> can somebody explain me error #3 here? just for testing, took xmp and just switched off gdm and set it to 2t.
> i've checked error description, gdm on runnning without error so it cant be rttnom or trrdl ? voltage is 1.36v, dont think its too low.cluesless as usual
> 
> edit:rttnom to 6 changed error #3 to #5
> tRDWR/tWRRD while for bigger datasets tRP, tRFC is in the description, too high trdwr/twrrd can cause errors too ?!
> but why does it run error free with gdm on ? the only change with gdm on is tcl 16 if i'm not wrong.
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2539560


GDM is pretty different from pure command rate.

BTW, which PCB do you have on your 3600C15 dimms and what is their production date?


----------



## Taraquin

So to more performance testing 3800cl15 vs 4000cl16:
PBO+200 and curve optimizer and 88W max limit on my 5600X.

4000cl16 SOTTR: 3 runs avg 257fps CPU game avg (263-255-253)









3800cl15 SOTTR: 3 runs avg 254fps CPU game avg (258-252-252)









Cinebench 4000cl16:









Cinebench 3800cl15:









So what is the wrap-up? Slightly better gaming performance and slightly lower productivity performance with 4000cl16 vs 3800cl15,


----------



## Luggage

Taraquin said:


> So to more performance testing 3800cl15 vs 4000cl16:
> PBO+200 and curve optimizer and 88W max limit on my 5600X.
> 
> 4000cl16 SOTTR: 3 runs avg 257fps CPU game avg (263-255-253)
> View attachment 2539600
> 
> 
> 3800cl15 SOTTR: 3 runs avg 254fps CPU game avg (258-252-252)
> View attachment 2539601
> 
> 
> Cinebench 4000cl16:
> View attachment 2539602
> 
> 
> Cinebench 3800cl15:
> View attachment 2539603
> 
> 
> So what is the wrap-up? Slightly better gaming performance and slightly lower productivity performance with 4000cl16 vs 3800cl15,


Cb don’t care about ram and 80 points is basically run to run variance.
Use some benchmarks that react to memory. TimeSpy cpu test or y-cruncher.


----------



## domdtxdissar

Taraquin said:


> So I did a simliar test *and got very different results from you with Linpack*.


Hmm it seems like we are reading the same data quite differently.. I think your numbers are perfectly inline with what i would expect from a 5600x

Your data show:

@ 1900 = 262.1755 GFlops
@ 1900 "optimized" = 264.3158 GFlops
@ 2000 = 256.8346 GFlops (and it seemed like numbers was on down trending trajectory with the temp going up.. What would the numbers had been after 5-10 runs? / 150w load ?)
Granted your numbers above 1900 fclk didn't facetank the same way as mine, single ccd greatly helps here, but there is still no performance scaling above 1900:3800 in your linpack data, just like with my system.

Also please note, i don't say it impossible for a Zen3 5000 series CPU to show positive scaling above flck 1900 in linpack, its just not seen so often, and for a dual ccd CPU its very very rare.

But i think we both agree in our "conclusions", don't get blindsided by Aida64 numbers and instead actually test the programs/games which settings is the fastest


domdtxdissar said:


> So just a friendly advice to everyone who want to run high infinity fabric speeds.. You should test it in other performance benchmarks than Aida64 to see if its really worth it.





Taraquin said:


> Very slight negative scaling past 3800\1900, I bet this is due to 4000\2000 requiring more power on settings hidden from me, I watched HWMonitor while running linpack and 3800 boosts slightly higher allcore.
> 
> 3800cl15 with optimized voltages gets 1% better due to better powerbudget for CPU.
> 
> I agree that testing above 3800\1900 is required as some systems like yours get very bad scaling, while others like mine change very little.


And this kinda brings me back to the "Zen DDR4 OC Leaderboards" google doc, don't get tricked by aida latency numbers on there as we know how easy it is to manipulate / hide problems  

Lastly, CPU clockspeed is king in pretty much all cases


----------



## Owterspace

I installed my 5600X and was playing around a little..



















During linpack it was running at around 4625-4650. Using 8GB load.


----------



## Taraquin

domdtxdissar said:


> Hmm it seems like we are reading the same data quite differently.. I think your numbers are perfectly inline with what i would expect from a 5600x
> 
> Your data show:
> 
> @ 1900 = 262.1755 GFlops
> @ 1900 "optimized" = 264.3158 GFlops
> @ 2000 = 256.8346 GFlops (and it seemed like numbers was on down trending trajectory with the temp going up.. What would the numbers had been after 5-10 runs? / 150w load ?)
> Granted your numbers above 1900 fclk didn't facetank the same way as mine, single ccd greatly helps here, but there is still no performance scaling above 1900:3800 in your linpack data, just like with my system.
> 
> Also please note, i don't say it impossible for a Zen3 5000 series CPU to show positive scaling above flck 1900 in linpack, its just not seen so often, and for a dual ccd CPU its very very rare.
> 
> But i think we both agree in our "conclusions", don't get blindsided by Aida64 numbers and instead actually test the programs/games which settings is the fastest
> 
> 
> And this kinda brings me back to the "Zen DDR4 OC Leaderboards" google doc, don't get tricked by aida latency numbers on there as we know how easy it is to manipulate / hide problems
> 
> Lastly, CPU clockspeed is king in pretty much all cases


Both 3800cl15 and 4000cl16 get worse linpack perf if I continiue as CPU-temp rises above 75C after a while. My curiosity was more how BW vs CPU speed affects diffrent apps/games. In general I would say 3800cl15 and 4000cl16 is pretty even except for CPU speed and BW in certain scenarios, but will test further with Y-cruncher etc later


----------



## domdtxdissar

hazium233 said:


> My humble opinion is that sheet really needs to be broken into two sheets. One with an actual stability test length that makes sense for daily operation, and one that can be called "leaderboard" for more extreme OC. Right now it is all over the place with just the "20 minute" testing requirement, and some submissions don't even have this.


How do you want to prove the stability from the " One with an actual stability test length that makes sense for daily operation"
Last page i completed the following with gimped performance: (massive whea throttling)

1 hour OCCT large dataset -> completed
2 hours y-cruncher torture test with all enabled -> completed
100% runmemtestpro -> completed
1 hour karhu ram test -> completed
And there is no way to tell from the screenshot that this is running at reduced performance








_edit_


Taraquin said:


> Both 3800cl15 and 4000cl16 get worse linpack perf if I continiue as CPU-temp rises above 75C after a while. My curiosity was more how BW vs CPU speed affects diffrent apps/games. In general I would say 3800cl15 and 4000cl16 is pretty even except for CPU speed and BW in certain scenarios, but will test further with Y-cruncher etc later


I recommend static CPU clocks to eliminate the PBO boosting factor in any further testing.
This way you can see if throttling is getting worse when IO/infinity fabric temps are increasing..


----------



## Taraquin

Luggage said:


> Cb don’t care about ram and 80 points is basically run to run variance.
> Use some benchmarks that react to memory. TimeSpy cpu test or y-cruncher.


Can try tomorrow


----------



## Taraquin

Owterspace said:


> I installed my 5600X and was playing around a little..
> 
> View attachment 2539611
> 
> 
> View attachment 2539612
> 
> 
> During linpack it was running at around 4625-4650. Using 8GB load.


My MB refuse to use more than 88W unless I run allcore static, linpack at 3800 ran ar 4400-4450, while 4000 ran about 25-50MHz slower.


----------



## Audioboxer

One thing I've noticed the past week is on days I forget to apply my Ryzen Master PBO settings to get around the AGESA 1.425v "bug" games and the likes still perform great with PBO on, PBO values on auto and just using telemetry.

Boosting high and across multiple cores within the auto PBO values. And whatever telemetry changes. It seems to be what makes the cores boost higher no matter the PBO values.

CB23 scores drop on PBO auto though, so manually applying the Ryzen Master 270/168/220 brings them back up to 31k.

The tldr basically being a lot of extra wattage and heat is _brute forced_ through PBO values just for a higher CB23 score. Obviously any all core tasks benefit as well, but on a 5950x there is hardly anything crunching all the cores at once for most users. Gaming doesn't even get there yet, single core still matters more in most games lol.

Though I have picked up Flight Simulator 2020 finally and that game simply kills the CPU! It's a fight just to keep a constant 60FPS in detailed areas without compromising on graphics. Again, it's very single core dependent, MS could probably do a better job of utilising more cores. DLSS would be a life saver too!


----------



## Asutz

@hazium233


----------



## Owterspace

Taraquin said:


> My MB refuse to use more than 88W unless I run allcore static, linpack at 3800 ran ar 4400-4450, while 4000 ran about 25-50MHz slower.


All good my man! This is not a competition


----------



## Imprezzion

Well, I tried to yeet the max boost to 5100 with CPPC and preferred cores off and they didn't all like that. Corecycler actually gave me a page fault bsod lol.

I guess 5000 without CPPC is the max while I can get away with 5100 on the preferred ones with CPPC enabled single thread. But I like it without as it (maybe a bit placebo) seems to be smoother in gaming. Less stutter in Division 2 and Halo Infinite. 

Y cruncher did indeed give me a couple of WHEA's at 1933 FCLK but as I only game on this rig and it isn't showing any WHEA's in gaming I find it acceptable.

Latency is around 55.4ns now with bandwidths around 59-60GB/s in AIDA. Did have to raise EDC from 165 to 170 to combat the extra power vSOC draws now at the higher voltage compared to 1800 FCLK.

RAM is at 3866 14-15-8-15-30-44-264-2T 1.59v vDIMM and is TM5 stable at 43.8c for the hottest DIMM in 25 cycles 1usmus.


----------



## Asutz

could u fix your errors with just vdimm or did u tried something else? still problems getting 3800 gdm on 1t stable with c16 timings and vdimm around 1.43v
i have no fan and the hot gpu backplate sends nice hot **** to the dimms.


----------



## Imprezzion

Asutz said:


> could u fix your errors with just vdimm or did u tried something else? still problems getting 3800 gdm on 1t stable with c16 timings and vdimm around 1.43v
> i have no fan and the hot gpu backplate sends nice hot **** to the dimms.


1 step higher ProcODT (34.3 --> 36.9)
1 step "higher" RTT_NOM (RZQ/5 --> RZQ/6)
vDIMM 1.580 --> 1.590

That fixed it. Could've done it with 1.580 on tWR 12 tRTP 6 but I wanted 10 5 so yeah..

I'd rather run tCL 15 on much much lower vDIMM (1.510) but it won't train tPHYRDL at 15 while it does at 14 so yeah.. I'll take the extra vDIMM then.


----------



## Owterspace

154w PPT is a new record for me on my 5600X lol.. I had to open a window to do it


----------



## hazium233

domdtxdissar said:


> How do you want to prove the stability from the " One with an actual stability test length that makes sense for daily operation"
> Last page i completed the following with gimped performance: (massive whea throttling)
> 
> 1 hour OCCT large dataset -> completed
> 2 hours y-cruncher torture test with all enabled -> completed
> 100% runmemtestpro -> completed
> 1 hour karhu ram test -> completed
> And there is no way to tell from the screenshot that this is running at reduced performance
> View attachment 2539614
> 
> 
> ...


Can't prove stability, it is unfortunately impossible. So I guess my comment is as much nonsense as 20min stability 

Fabric doesn't even have any real tests, but your posts and other previous ones have a partial answer. L3 latency column would be more useful as avg linpack gflop even if simple 5 loop LinX.

Ram timings are not even adequately tested in 3hr of TM5, but for the sake of community access and involvement longer probably would be a not be realistic.

So do you think there should be no community sheet whatsoever, or what? Any sheet with community submissions will be 100% on the honor system regardless of what the nominal requirements are.



Asutz said:


> @hazium233
> View attachment 2539621


Thaiphoon isn't really reliable for PCB type. Also I don't believe G.Skill really ever used A1 on any decent kits, what was often called A1 with G.Skill B-die kits is really A0. They used them on non-RGB kits up through 4400MT/s.

If they are 2020 or newer they may very well be A2. Mine are older and A0. You can tell from the spacing of the chips under the heatspreader. A0 practically evenly spaced under the heatspreader. A2 are in two groups of four to the left and right, and are also closer to the gold contacts.

I do not know if new kits would happen to read A2, I don't believe that the PCB revision is ever really programmed, and as such thaiphoon must guess.

I asked in part mostly for my curiousity and following along with your results to compare RTT. Won't be worth it for you to pull them to satisfy my curiousity.

edit

Here is an example I pulled from ebay (in spoiler):



Spoiler















The layout of the capacitors is more consistent with their A0 than the A2, and is exactly how my A0 3600C15 looks.


----------



## Taraquin

Owterspace said:


> All good my man! This is not a competition


No, not trying to compete, just stating that you are lucky


----------



## Imprezzion

Seeing as how I will be receiving a RMA for my old dead 5900x I wanna use that one with my current board (and maybe RAM) and I wanna get a better (read: not ASUS) board for my personal setup.

I have my eyes on the X570S lineup especially from MSI but they have like 8 models of that lol.. which one would you guys recommend based on VRM's, build quality, features.. like would a Tomahawk or Edge be enough to max PBO2 a 5900X or do I need a Unify-X or Ace for that. Back with the 10900K I needed the Ace / Unify as any less would just blow up the VRM lol.


----------



## Leftezog

Hello everyone Merry Christmas. Any suggestions in what to change to get rid of these errors? I know timings are all on auto only changed Tcke to 8 because with 0, 1, 10 and 9 I had too many errors. Also the ram is not overheating it's still under 40c cause I have a 120mm fan blowing on them. The ram consists of 2 kits of F4-3600C16D-16GTZNC 3600MHz CL16-19-19-39.


----------



## Taraquin

Luggage said:


> Cb don’t care about ram and 80 points is basically run to run variance.
> Use some benchmarks that react to memory. TimeSpy cpu test or y-cruncher.


Don`t have timespy, but ran Y-cruncher test 7:
3800cl15:









4000cl16:









Don`t know how to interpret results but seems 3800cl15 was slightly faster, but less efficient than 4000cl16?


----------



## Luggage

Taraquin said:


> Don`t have timespy, but ran Y-cruncher test 7:
> 3800cl15:
> View attachment 2539663
> 
> 
> 4000cl16:
> View attachment 2539664
> 
> 
> Don`t know how to interpret results but seems 3800cl15 was slightly faster, but less efficient than 4000cl16?


Benchmate is easier to compare Punish it with y-cruncher


----------



## Imprezzion

Leftezog said:


> Hello everyone Merry Christmas. Any suggestions in what to change to get rid of these errors? I know timings are all on auto only changed Tcke to 8 because with 0, 1, 10 and 9 I had too many errors. Also the ram is not overheating it's still under 40c cause I have a 120mm fan blowing on them. The ram consists of 2 kits of F4-3600C16D-16GTZNC 3600MHz CL16-19-19-39.
> View attachment 2539661


First of all, fix the primaries. This high does not help as it has such a high primary with a way too low tCWL, tWR and tRRD. That doesn't help at all. Just set 16-18-18 or whatever you want. 

For error #3: Drop RTT_NOM to 5 or 6, Set RTT_WR to 3.
For error #5 set tWRRD to something not 1. 2 or 4 preferred. 
For error #13, should not be there anymore when you fix the others. If it remains, bit more vDIMM.


----------



## evilhf




----------



## Taraquin

Luggage said:


> Benchmate is easier to compare Punish it with y-cruncher


Where do I downliad the 2.5b version?


----------



## Imprezzion

Why does my latency in AIDA or my GFLOPS in LinX / IBT not change at all between 1T GDM Off and 2T GDM Off.. hell in AIDA 2T actually has better latency lol..

Testing at 3733 14-15-8-15-30-45-270 1T GDM Off and 2T GDM Off.

1T:









2T:









So weird..

It does show that 1T has slightly better bandwidth scores slightly outside of margin of error but latency is basically the same..


----------



## domdtxdissar

Taraquin said:


> Where do I downliad the 2.5b version?


2.5b is included in benchmate








Option "7" which u ran in standalone y-cruncher is also happens to be "2.5b"

_edit_
Btw not sure you saw my previous post


Taraquin said:


> Both 3800cl15 and 4000cl16 get worse linpack perf if I continiue as CPU-temp rises above 75C after a while. My curiosity was more how BW vs CPU speed affects diffrent apps/games. In general I would say 3800cl15 and 4000cl16 is pretty even except for CPU speed and BW in certain scenarios, but will test further with Y-cruncher etc later


_I recommend static CPU clocks to eliminate the PBO boosting factor in any further testing.
This way you can see if throttling is getting worse when IO/infinity fabric temps are increasing.._


----------



## Imprezzion

Changing SCL's to 3 from 4's made tPHYRDL go 26/28 again but latency and bandwidth is still way better then 26/26 on 4 SCL.

So, I'm really starting to kinda doubt how important tPHYRDL on equal numbers really is.. no benchmark I run, y-cruncher, Aida, Cinebench, LinX / IBT, game benches.. show any negative effects of running 26/28 that I can measure / reproduce..


----------



## Audioboxer

So using @Veii calculator for tRFC found a few interesting things in an hour. First off, 228 is what I use on my daily, manages it at 1.55v. Going on this spreadsheet trying 209 would be next...

While 209 boots at 1.55v, can't make it into Windows. At 1.6v I get into Windows, but managed to get a reboot on the desktop. So I then tried 1.65v and I got an error on 11 after 4 minutes. Now, could it be tRFC, yes, but










Drop to 1.63v and it shows some promise.

Therefore, it seems that 1.65v is around the point where ProcODT/Rtts and maybe even DrvStrs likely cause some issues. Trying to daily 1.65v is likely hard as it is without IC crashes, but I've got a feeling the ProcODT and RttNom above also can't handle it. Probably need a Stronger Nom, weaker Proc and maybe even to look at Park.

Good news though is 110ns _might_ be achievable just under 1.65v. Veii mentioned a week ago or something 110ns might be thought to be the theoretical floor for B-die. Would be cool if this can be achieved at a "reasonable" voltage.

Not sure if going from 1.55v to 1.63v for a 10ns drop is exactly worth it for a daily profile, but still, I'll test tRFC 209 longer now.

*edit* - I should add "theoretical floor" can obviously be smashed by using a very high voltage and maxmem, but that is its own thing










I would say managing to get 110ns at full capacity with a daily voltage would be an actual achievement.


----------



## Imprezzion

Audioboxer said:


> View attachment 2539675
> 
> 
> So using @Veii calculator for tRFC found a few interesting things in an hour. First off, 228 is what I use on my daily, manages it at 1.55v. Going on this spreadsheet trying 209 would be next...
> 
> While 209 boots at 1.55v, can't make it into Windows. At 1.6v I get into Windows, but managed to get a reboot on the desktop. So I then tried 1.65v and I got an error on 11 after 4 minutes. Now, could it be tRFC, yes, but
> 
> View attachment 2539676
> 
> 
> Drop to 1.63v and it shows some promise.
> 
> Therefore, it seems that 1.65v is around the point where ProcODT/Rtts and maybe even DrvStrs likely cause some issues. Trying to daily 1.65v is likely hard as it is without IC crashes, but I've got a feeling the ProcODT and RttNom above also can't handle it. Probably need a Stronger Nom, weaker Proc and maybe even to look at Park.
> 
> Good news though is 110ns _might_ be achievable just under 1.65v. Veii mentioned a week ago or something 110ns might be thought to be the theoretical floor for B-die. Would be cool if this can be achieved at a "reasonable" voltage.
> 
> Not sure if going from 1.55v to 1.63v for a 10ns drop is exactly worth it for a daily profile, but still, I'll test tRFC 209 longer now.
> 
> *edit* - I should add "theoretical floor" can obviously be smashed by using a very high voltage and maxmem, but that is its own thing
> 
> View attachment 2539677
> 
> 
> I would say managing to get 110ns at full capacity with a daily voltage would be an actual achievement.


On reasonable vDIMM, 1.60-1.61 or lower for me due to temps, mine bottoms out around 135ns. Any lower gets real unstable real fast lel. 

I'm running a 25 cycle run now at 3733 as I want a WHEA free profile I can rely on as a daily and 1900+ FCLK just isn't reliable. Thanks for the test 17 tip of y-cruncher btw cause that exposed the WHEA's for me quite rapidly lol. 1933 seemed fine at first in Cinebench and TM5 but test 17 rained WHEA's. Like 15 in 20 minutes... 

3733 with 1866 however seems to run fine in test 17 even at quite low vSOC VDDG's, VDDP and ProcODT so it's promising. 

This profile runs 138ns now on tRFC (43 TRC x6) at 1.55v vDIMM. We shall see. She's on pass 9 52 minutes in no errors yet.


----------



## Audioboxer

Imprezzion said:


> On reasonable vDIMM, 1.60-1.61 or lower for me due to temps, mine bottoms out around 135ns. Any lower gets real unstable real fast lel.
> 
> I'm running a 25 cycle run now at 3733 as I want a WHEA free profile I can rely on as a daily and 1900+ FCLK just isn't reliable. Thanks for the test 17 tip of y-cruncher btw cause that exposed the WHEA's for me quite rapidly lol. 1933 seemed fine at first in Cinebench and TM5 but test 17 rained WHEA's. Like 15 in 20 minutes...
> 
> 3733 with 1866 however seems to run fine in test 17 even at quite low vSOC VDDG's, VDDP and ProcODT so it's promising.
> 
> This profile runs 138ns now on tRFC (43 TRC x6) at 1.55v vDIMM. We shall see. She's on pass 9 52 minutes in no errors yet.


All CPU testing or heavy usage will increase WHEA amount, it's whether you also see performance regression or like what I see with y-cruncher test 17, USB drop outs.

15 in 20 minutes is nothing by the way lol, I can get this chip spitting out a WHEA every few seconds at 2000 xD


----------



## Taraquin

Imprezzion said:


> On reasonable vDIMM, 1.60-1.61 or lower for me due to temps, mine bottoms out around 135ns. Any lower gets real unstable real fast lel.
> 
> I'm running a 25 cycle run now at 3733 as I want a WHEA free profile I can rely on as a daily and 1900+ FCLK just isn't reliable. Thanks for the test 17 tip of y-cruncher btw cause that exposed the WHEA's for me quite rapidly lol. 1933 seemed fine at first in Cinebench and TM5 but test 17 rained WHEA's. Like 15 in 20 minutes...
> 
> 3733 with 1866 however seems to run fine in test 17 even at quite low vSOC VDDG's, VDDP and ProcODT so it's promising.
> 
> This profile runs 138ns now on tRFC (43 TRC x6) at 1.55v vDIMM. We shall see. She's on pass 9 52 minutes in no errors yet.


Where is test 17?


----------



## Imprezzion

Taraquin said:


> Where is test 17?


Use stress mode, so option 1, then deselect all tests 11 to 19 except 17. Start test.

CPU load is extremely high even at EDC 170 and gets HOT 🔥. But it's a great test for PBO offsets and FCLK stability. My CPU clocks between 4550 and 4700 at 80-82c in this test.

And yes @Audioboxer my keyboard backlight flickers on and off the whole time indicating USB issues on 1933 or 1966. 1866 is fine tho.

EDIT: 1 error #2 after 1h30m. What could this be...


----------



## Audioboxer

Imprezzion said:


> Use stress mode, so option 1, then deselect all tests 11 to 19 except 17. Start test.
> 
> CPU load is extremely high even at EDC 170 and gets HOT 🔥. But it's a great test for PBO offsets and FCLK stability. My CPU clocks between 4550 and 4700 at 80-82c in this test.
> 
> And yes @Audioboxer my keyboard backlight flickers on and off the whole time indicating USB issues on 1933 or 1966. 1866 is fine tho.
> 
> EDIT: 1 error #2 after 1h30m. What could this be...
> View attachment 2539680


Yup, keyboard flickering is USB issues 

As for your error, I wouldn't run a ProcODT that low whilst profile testing. Just stick to 34.3~36.9. Especially with DR.

Your ClkDrvStr might end up preferring 40 as well for 1T.










Dropped Proc and increased Nom, even for 1.63v, and this looks promising. 25 cycle next.


----------



## Taraquin

Imprezzion said:


> Use stress mode, so option 1, then deselect all tests 11 to 19 except 17. Start test.
> 
> CPU load is extremely high even at EDC 170 and gets HOT 🔥. But it's a great test for PBO offsets and FCLK stability. My CPU clocks between 4550 and 4700 at 80-82c in this test.
> 
> And yes @Audioboxer my keyboard backlight flickers on and off the whole time indicating USB issues on 1933 or 1966. 1866 is fine tho.
> 
> EDIT: 1 error #2 after 1h30m. What could this be...
> View attachment 2539680


It was hard for my cooler, sitting at 84-85C and max rpm. Wattage around 90W (102W peak) on 3800cl15 and 95W (106W peak) on 4000cl16. No WHEA 18 or 19 after 20 mins so looks good, though noisy and hot  I get my D15 chromax black in a few days, that will be better times.


----------



## domdtxdissar

Managed to tighten tRDWR and tWRRD one tick each 








Seems like it gave me ~100-150mb/sec in copy speed with 2/8 instead of 3/9


----------



## Taraquin

domdtxdissar said:


> Managed to tighten tRDWR and tWRRD one tick each
> View attachment 2539695
> 
> Seems like it gave me ~100-150mb/sec in copy speed with 2/8 instead of 3/9


From my experience especially RDWR can have a significant perf impact.


----------



## Audioboxer

Audioboxer said:


> Yup, keyboard flickering is USB issues
> 
> As for your error, I wouldn't run a ProcODT that low whilst profile testing. Just stick to 34.3~36.9. Especially with DR.
> 
> Your ClkDrvStr might end up preferring 40 as well for 1T.
> 
> View attachment 2539683
> 
> 
> Dropped Proc and increased Nom, even for 1.63v, and this looks promising. 25 cycle next.


Single error 7 on cycle 8 on the next run, so likely voltage related for tRFC. Tried 1.64v but this like 1.65v seems to be where PCB/IC crashes start to come in trying to run a full 32GB. A complete overhaul might be needed of resistances to stand a chance.

So the journey towards getting 110ns looks like a tough one. Will keep going though. ClkDrvStr might be worth dropping to 30 at this high a voltage in case it's contributing towards crashes.



domdtxdissar said:


> Managed to tighten tRDWR and tWRRD one tick each
> View attachment 2539695
> 
> Seems like it gave me ~100-150mb/sec in copy speed with 2/8 instead of 3/9


Nice! Something else for me to try on the daily profile rather than chasing 110ns lol. Dunno why I've never really had a go at 12/8 before now. I think it was to be compliant with Veiis formula of -2 on tCWL = +1 on tRDWR. So 14/8 becomes 12/9.


----------



## Taraquin

So I ran Linpack at [email protected] fixed:

3800cl16:









4000cl16:










So about 3800 is 2% faster with 3800 just like with curve optimizer, temp was a few degrees higher with 4000cl16 so that might affect performance and be the reason.


----------



## Audioboxer

@domdtxdissar were you able to run 12/8 straight away or did it require some tweaking? Sadly I can't post it. Interesting thing is it's the CPU boot light I get stuck on.

This could be where us memory buddies depart! Who knows, might even be the X570s Unify Max helping out here.

tWRRD I can run at 2.


----------



## Imprezzion

@Audioboxer 
Totally correct there. ClkDrvStr 40 and ProcODT 34.3 and I haven't seen the error again so far. Please don't jinx it.. hehe. 

Any ideas how to fix tCL 14 not wanting to do tPHYRDL 26/26 on 1T? On 2T it's fine but on 1T always 26/28 no matter what else I change.


----------



## PJVol

Taraquin said:


> so that might affect performance and be the reason


Tight power budget, higher temps... what else?
This Linpack regression is solely due to internal throttling, none of the above matters


----------



## Audioboxer

Imprezzion said:


> @Audioboxer
> Totally correct there. ClkDrvStr 40 and ProcODT 34.3 and I haven't seen the error again so far. Please don't jinx it.. hehe.
> 
> Any ideas how to fix tCL 14 not wanting to do tPHYRDL 26/26 on 1T? On 2T it's fine but on 1T always 26/28 no matter what else I change.


I gave up on that a while back, if I go to tCL14 just now it at least trains to 28/28. Months back it was doing 28/26.

This is the reason I shot for tCL13 lol. I think the setup timing plays a part, but it's simply needed for most DR kits to do 1T.


----------



## Imprezzion

Audioboxer said:


> I gave up on that a while back, if I go to tCL14 just now it at least trains to 28/28. Months back it was doing 28/26.
> 
> This is the reason I shot for tCL13 lol. I think the setup timing plays a part, but it's simply needed for most DR kits to do 1T.


Yeah I can't go without 56 on 1T. If I don't set that it barely even POST's.

Problem is, tCL 14 mismatched is nothing faster then tCL 15 matched. So there's no reason to go 14. If I go 13 I need way too much vDIMM. On 3600 it needs 1.590v for tCL 13 I can only imagine what it needs at 3733... But hey, I can always try lol.


----------



## Audioboxer

Imprezzion said:


> Yeah I can't go without 56 on 1T. If I don't set that it barely even POST's.
> 
> Problem is, tCL 14 mismatched is nothing faster then tCL 15 matched. So there's no reason to go 14. If I go 13 I need way too much vDIMM. On 3600 it needs 1.590v for tCL 13 I can only imagine what it needs at 3733... But hey, I can always try lol.


You pretty much summed it up for us, this is why tCL14 is useless for quite a few of us with tPHYRDL issues. As I said mine is at least training at 28/28 now, because if you have a mismatch the latency penalty is like 0.5ns. 28/28 will perform better than 28/26.

If I couldn't run tCL13 and I couldn't get tPHYRDL matching at tCL14 I'd probably just run tCL15. As much as it feels like defeat you're likely going to get better latency. Keep working at trying to shift it to 28/28.

At this point I think there has to be some AMD bios junk going on with tPHYRDL. Multiple people with issues at even tCL lol.


----------



## Taraquin

PJVol said:


> Tight power budget, higher temps... what else?
> This Linpack regression is solely due to internal throttling, none of the above matters


Powerbudget for CPU is the same, pwr budget for IO-die is higher with 4000cl16 even at same soc, iod volt etc, hence higher temps, 3800 maxed out at 82C, 4000 at 85C, cores seemed to use the same, but overall consumption was a few watts higher for 4000. For me it seems thermal throttling of IO-die might be a reason. Whats your take?


----------



## domdtxdissar

Audioboxer said:


> @domdtxdissar were you able to run 12/8 straight away or did it require some tweaking? Sadly I can't post it. Interesting thing is it's the CPU boot light I get stuck on.
> 
> This could be where us memory buddies depart! Who knows, might even be the X570s Unify Max helping out here.
> 
> tWRRD I can run at 2.


Ran straight away..
2/9 = boot
1/9 = no boot
2/8 = boot
2/7 = no boot


----------



## PJVol

Taraquin said:


> Whats your take?


I've tested 3800 vs 4000 in linpack with loosen power limits so as to not reach them over the test, and the results were inline with yours.
But you may be right regarding throttling, not sure though if it IOD or what type of throttling it is (thermals weren't an issue in my tests either).


----------



## TheBoy08

Where can I improve?
I tried increasing voltages up to 1.60v to get tRCDRD to 14 but it errors in tm5.


----------



## Taraquin

PJVol said:


> I've tested 3800 vs 4000 in linpack with loosen power limits so as to not reach them over the test, and the results were inline with yours.
> But you may be right regarding throttling, not sure though if it IOD or what type of throttling it is (thermals weren't an issue in my tests either).


It seems like even on the systems that don`t have WHEA 19-issues above 1900 flck performance doesn`t scale except for pure bandwith-scenarios like aida, some games and a few apps. Rest of apps\games see same performance or slight regression it seems.

For some user the bogging effects of WHEA 19- maybe even with supressor might tank performance like in domdtxdissars case? I have seen poor aida-results at a friend of mines 5600X, he had up to a WHEA 19s every second when he ran 2000 fclk. Performance improved when running 1900 fclk WHEA 19- free.


----------



## Taraquin

TheBoy08 said:


> View attachment 2539735
> 
> Where can I improve?
> I tried increasing voltages up to 1.60v to get tRCDRD to 14 but it errors in tm5.


Try getting 2T gdm off stable and maybe 1t, but then you must alter DrvStr etc. As for teh rest of the timings most is good, but try RAS 27 since RC= RP+RAS, WR 12 unless you can do 2t since RTP should be half of WR and GDM don`t allow odd RTP, try RFC 248 since it should be divideable by 8, RDWR should be 10 since it`s generally half of RCDRD on SR-kits, but you must add 1 for each -2 on CWL you do.


----------



## Imprezzion

TheBoy08 said:


> View attachment 2539735
> 
> Where can I improve?
> I tried increasing voltages up to 1.60v to get tRCDRD to 14 but it errors in tm5.


tRTP should be 5 right with tWR 10. So, that.
And if you select the other DIMM from the drop down in the bottom left does it have tPHYRDL at 26 as well? Otherwise that requires some attention.

Edit: oh yeah GDM and uneven numbers.. I forgot hehe.


----------



## PJVol

Taraquin said:


> It seems like even on the systems that don`t have WHEA 19-issues above 1900 flck performance doesn`t scale except for pure bandwith-scenarios like aida, some games and a few apps. Rest of apps\games see same performance or slight regression it seems.


When i tested my CPU on a msi b450 board, there were no whea-19 nor perf. regression at 2000 fclk.
With Asrock i need PLL power pushed to its limit (2.1V) to even get close to the scaling seen on a msi pc.
I think it has something to do with the CPU's own PDN being very sensitive to the external power delivery, to the way it is designed.
Ryzen's PDN is very complicated.


----------



## Audioboxer

Latest findings chasing 110ns, so, 228 and even 224, 120ns and 118ns can pass at 1.55v, but going below that seems to seriously hit diminishing returns with voltage. I think 110ns needs about 1.64~1.65v and then the difficulty is stabilising the PCB/ICs.

Using Veii's calculator with tRC 38 meant my choice was 120ns or 110ns. So, I switched back to 36










I can run tRAS 24 and tRC 36, but went with 26/38 on the daily so that tRAS = tRCDRD + tRP. tRAS 22 I've had issues with in the past with TM5 timeouts. So, 113.6ns










It was unstable at 1.55~1.56v, but 1.6v seems to do the trick. A jump of 0.05v just to go from 118ns to what is pretty much 114ns. At least I also proved 1.6v is no issue at all for the PCB/ICs, but this much is known. I think TEAMGROUP actually sell a 1.6v rated B-die kit. Seems to be when you go above 1.6v that is when things can begin to get trickier for a daily profile.

Fun to chase the floor with tRFC, but ultimately seems near pointless to run 1.6v daily for such a small gain. It might pass at 1.57~1.59v, I guess.


----------



## domdtxdissar

Managed to break 701GFlops average in Linpack Xtreme 🎅
Only took 327W PPT 🥵🥵


----------



## Audioboxer

__





MEG X570 UNIFY | Motherboard | MSI Global


Best AMD AM4 X570 ATX gaming motherboard, lightning PCIe 4.0, three lightning M.2, Frozr heatsink, WiFi 6, aluminum cove with extended heatsink, USB 3.2 Gen 2, M.2 heatsink, excellent overclocking, pre-install I/O, MSI GAMING




www.msi.com





AGESA 1.2.0.5 final BIOS dropping for x570 boards. Will be interesting to see if there is still a CPU voltage cap when increasing EDC.


----------



## Imprezzion

I'm not sure when it drops for my board I even wanna upgrade it. I mean, everything runs fine as it is CPU wise now on 1.2.0.3c..

Or, maybe I will ditch this board all together for a X570S Unify or Carbon... Hehe.


----------



## overpower

So, I tried tcwl 14 or 3866/1933 or gdm disabled but nothing boots. Seems i've reached my limit. What should I change to achieve better results?


----------



## RonLazer

Hello guys. I haven't been checking in on this thread in a while, but reading through the latest posts I'm glad people have adopted Linpack as a realistic memory performance test instead of the old Aida64 latency chasing 

I wrote a guide a while back on FCLK overclocking which summarized my own testing and collective wisdom of many different sources. I recently found the time to go through and clean it up and update it a bit. Thought it might be be a useful, or at least interesting read for some of you. Also happy to have any feedback, suggestions, or contributions:









Infinity Fabric Overclocking on Zen2/3


Infinity Fabric Overclocking on Zen2/3 WARNING: DO NOT TREAT AS OFFICIAL GUIDANCE. OVERCLOCKING OF ANY SORT IS NOT COVERED BY YOUR WARRANTY.I AM NOT RESPONSIBLE IF YOU FRY YOUR CPU. 3000/5000 Ryzen chips are officially compatible up to 3200MHz memory speeds, which is equal to a 1600MHz infin...




docs.google.com


----------



## Taraquin

RonLazer said:


> Hello guys. I haven't been checking in on this thread in a while, but reading through the latest posts I'm glad people have adopted Linpack as a realistic memory performance test instead of the old Aida64 latency chasing
> 
> I wrote a guide a while back on FCLK overclocking which summarized my own testing and collective wisdom of many different sources. I recently found the time to go through and clean it up and update it a bit. Thought it might be be a useful, or at least interesting read for some of you. Also happy to have any feedback, suggestions, or contributions:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Infinity Fabric Overclocking on Zen2/3
> 
> 
> Infinity Fabric Overclocking on Zen2/3 WARNING: DO NOT TREAT AS OFFICIAL GUIDANCE. OVERCLOCKING OF ANY SORT IS NOT COVERED BY YOUR WARRANTY.I AM NOT RESPONSIBLE IF YOU FRY YOUR CPU. 3000/5000 Ryzen chips are officially compatible up to 3200MHz memory speeds, which is equal to a 1600MHz infin...
> 
> 
> 
> 
> docs.google.com


Good guide! A few corrections: GDM also rounds up WR and RTP and report it. Setting 5 or 9 gives you 6 and 10  

Even though linpack might get same results or slight regression above 1900 (2% going to 2000 on my setup), you may get better perf in BW sensitive apps/games like SOTTR (1-2% going from 3800cl15 to 4000cl16 tuned) like I showed earlier.


----------



## Taraquin

PJVol said:


> When i tested my CPU on a msi b450 board, there were no whea-19 nor perf. regression at 2000 fclk.
> With Asrock i need PLL power pushed to its limit (2.1V) to even get close to the scaling seen on a msi pc.
> I think it has something to do with the CPU's own PDN being very sensitive to the external power delivery, to the way it is designed.
> Ryzen's PDN is very complicated.


Yeah, it seems like that :/ Build a rig a few days ago on a B450 aorus pro with 1.2.0.3b with 5600X and everything above 3733+1866 spews out WHEA 19s. I bet a good ITX or mATX B450 with 2 dimms only might be a good candidate for possible scaling above 1900 fclk. It seems like for B550\X570 ITX and 2 dimm boards have much higher chance of avoiding WHEA 19s above 1900 fclk.


----------



## mongoled

Owterspace said:


> 154w PPT is a new record for me on my 5600X lol.. I had to open a window to do it
> 
> View attachment 2539643


I am a little confused with what you have posted here.

This looks like you are using PBO, but then your effective clocks look like you are using a static overclock of 4.7 Ghz.

Has something changed in BIOS development that I have not noticed ?

PBO is automatically disabled/non-functional when using a static overclock.

I am assuming that you are using a static overclock as your max effective frequency is locked to 4.7Ghz, this is not something I have ever seen before when using PBO and running LinpackXtreme, my effective clocks range from 4.46 Ghz to 4.85 Ghz when running the stress test.


----------



## mongoled

Taraquin said:


> So I ran Linpack at [email protected] fixed:
> 
> 3800cl16:
> View attachment 2539701
> 
> 
> 4000cl16:
> 
> View attachment 2539702
> 
> 
> So about 3800 is 2% faster with 3800 just like with curve optimizer, temp was a few degrees higher with 4000cl16 so that might affect performance and be the reason.


You could probably improve the 2000 FCLK result by playing with 1.8v PLL voltage, however its not really worth it IMHO, apart from benching etc, not for a 24/7 system.


----------



## Veii

Audioboxer said:


> So using @Veii calculator for tRFC found a few interesting things in an hour. First off, 228 is what I use on my daily, manages it at 1.55v. Going on this spreadsheet trying 209 would be next...
> 
> While 209 boots at 1.55v, can't make it into Windows.











Top right
Please do not use this old logic
It can cause issues
But boot issues are because of too low CsOdtDrvStr
40-20-30-24 works for people so far
be it even 40-20-30-30 for you

You should also switch to RTT_NOM /6 beyond 1.58v
DR PCBs have the bad characteristic, of crashing near 1.6v
Probably 634 RTT for it


----------



## Imprezzion

Serious question but.. how low should I even attempt to go on CLDO and CCD / IOD. I am just doing some tests dropping them further and further and i'm like, quite low now and it still doesn't show any signs of instability in stress tests lol.. No WHEA's in y-cruncher either as of yet on the below voltages. If this passes my normal tests like 25 cycles of 1usmus and some CPU tests, is there a point in going even lower?

EDIT: Quite promising. I will obviously let it finish the full 25 cycles but so far it seems to work kinda fine on these low voltages.










EDIT2: Also not too low on VDDP / VDDG to lose any bandwidth or latency performance yet.


----------



## Audioboxer

Veii said:


> View attachment 2539824
> 
> Top right
> Please do not use this old logic
> It can cause issues
> But boot issues are because of too low CsOdtDrvStr
> 40-20-30-24 works for people so far
> be it even 40-20-30-30 for you
> 
> You should also switch to RTT_NOM /6 beyond 1.58v
> DR PCBs have the bad characteristic, of crashing near 1.6v
> Probably 634 RTT for it


Just to confirm, you're saying use one of the values from tRFC Calculator V2? tRC * 10, tRC / (tCL/2) or tRC / (tCL/2-1)? Is there any play in-between the values like -/+ 8 or 16?










This passed a 25 cycle, I accidentally hit enter twice on the login screen which cleared the TM5 message lol. Yesterday it was passed at 1.6v. But 216 is based on tRC * 6 which I'm assuming you're saying not to use. It does work out a multiple of 8 though...

I'm just searching for the lowest tRFC I can achieve, preferably below 1.6v so I don't need to try and redo all the resistances. But you've given me some advice there.










For example, going with tRC 36 and using V2 then you would suggest I'd be trying to go with one of these values? 198 is likely to be a challenge, over 1.6v needed again. That's why I'm asking is adding +8 or something to 198 OK to do?

*edit* - tRFC 198 requires 1.66v to get to the desktop and a TM5 running and even then I got a BSOD at the end of cycle 1. 1.67v starts to bring PCB/IC crashing. So, knowing if +8 or +16 can be added to 198 will be helpful.... lol.


----------



## Audioboxer

206 needed 1.62v to show promise, much more manageable than 198 needing 1.67v+.

But I'm not sure if that's even a "valid" tRFC number. It's just 198 + 8. @Veii when you have some more time more guidance would be appreciated. If 198 is out of reach is there a middle ground between 198 and 234 at tRC 36?

tRFC getting a bit confusing. Anta was mentioning multiples of 16, some people say multiples of 8 and we have your V2 calculator.

*edit* - Guess there is always going back to tRC 38 and running 209


----------



## Taraquin

Audioboxer said:


> View attachment 2539831
> 
> 
> 206 needed 1.62v to show promise, much more manageable than 198 needing 1.67v+.
> 
> But I'm not sure if that's even a "valid" tRFC number. It's just 198 + 8. @Veii when you have some more time more guidance would be appreciated. If 198 is out of reach is there a middle ground between 198 and 234 at tRC 36?
> 
> tRFC getting a bit confusing. Anta was mentioning multiples of 16, some people say multiples of 8 and we have your V2 calculator.
> 
> *edit* - Guess there is always going back to tRC 38 and running 209
> 
> View attachment 2539833


If I remember correctly Anta said divideable by 8 for 8GB dimms, 16 for 16GB dimms etc.


----------



## Audioboxer

Taraquin said:


> If I remember correctly Anta said divideable by 8 for 8GB dimms, 16 for 16GB dimms etc.


Yeah, something like that. That conflicts with some of Veii's V2 calculator figures though.

Veii is calculating based on tCL and tRC.


----------



## Redwoodz

Hey guys, looking for a little guidance. I have this TeamGroup RGB kit I am trying to optimize but I am having issues with the Ryzen DRAM calculator from 1usmus and Taiphoon Burner. It says the IC's are SKHynix CJR/DJR, but when I use the timings from the calculator I get nothing. I can run XMP timings for 4000Mz at 3333Mhz no problem, but I know I can do better. By fiddling around and using the Samsung S die settings I have managed to get 3400 CL14 fairly stable. Any advice?


----------



## Taraquin

Audioboxer said:


> Yeah, something like that. That conflicts with some of Veii's V2 calculator figures though.
> 
> Veii is calculating based on tCL and tRC.


Veii must answear for this, but if I remember correct he said Anta`s recommendations were good. Timings is a count of something\a clockcycle. Values above Antas recommendations would work fine aswell, but yield no benefit to performance as you need to get into an earlier clockcycle to do that. For instance I use 280 RFC at 4000 on 2x8. Following Anta`s "rules" then 280 and 273 would give same performance, but 280 is better since it requires less voltage. 272 would be on an earlier clockcycle and get better perf so Veii`s rules can work fine, but if the stray but may require a bit more voltage for same perf or slightly miss an earlier clockcycle. Veii\Anta knows this better than me


----------



## Taraquin

Redwoodz said:


> Hey guys, looking for a little guidance. I have this TeamGroup RGB kit I am trying to optimize but I am having issues with the Ryzen DRAM calculator from 1usmus and Taiphoon Burner. It says the IC's are SKHynix CJR/DJR, but when I use the timings from the calculator I get nothing. I can run XMP timings for 4000Mz at 3333Mhz no problem, but I know I can do better. By fiddling around and using the Samsung S die settings I have managed to get 3400 CL14 fairly stable. Any advice?
> 
> View attachment 2539851


DJR er quite a bit better than CJR. Try for instance 1.4V at 3800\1900 and 16\20\20\20 36 rc 56, should work if DJR, might work if CJR. If CJR try rrd 6\8 faw 24, rfc 520, wr 16, rtp 8, scl`s 4, cwl 16, rdwr 8, wrrd 1, wtr 4\12, rest on auto.

If DJR you should be able to run rrd 5\7, faw 20, rfc 480, maybe rrd 4\6 and faw 16 might work, wtr 3\8 also might work.


----------



## Audioboxer

Taraquin said:


> Veii must answear for this, but if I remember correct he said Anta`s recommendations were good. Timings is a count of something\a clockcycle. Values above Antas recommendations would work fine aswell, but yield no benefit to performance as you need to get into an earlier clockcycle to do that. For instance I use 280 RFC at 4000 on 2x8. Following Anta`s "rules" then 280 and 273 would give same performance, but 280 is better since it requires less voltage. 272 would be on an earlier clockcycle and get better perf so Veii`s rules can work fine, but if the stray but may require a bit more voltage for same perf or slightly miss an earlier clockcycle. Veii\Anta knows this better than me


Trying to make sense of it myself as well. Veiis figures for 36/38 tRFC going by the last column only are quite hard to hit. Looking like I might need 1.61v for tRFC 209. As I mentioned last night I've found out under about 120ns the increase in voltage needed skyrockets. 224 at 1.55v as per Antas formula of multiples of 16 is like the absolute edge of voltage vs performance being optimal.

But I want to hear more from Veii on his calculator and as I asked earlier is there any scope for adding to the value it produces between the larger gap of each option calculated. 

It's not that I would be against going 1.61v on a daily, I can cool it, I also just want to learn a bit more about tRFC. The differences between two knowledgeable people and how they suggest calculating it. Multiples of 16 is obviously independent of tRC, but Veii seems to be calculating tRFC values strictly based on it. As well as tCL.


----------



## Reaxer

I just got some new memory, this 3600C14 kit was on sale, so I got it. CMW32GX4M2Z3600C14 
I started with trying to boot GDM off 2T, but it wouldn't post with whatever settings i tried. RTT 6/3/4, 7/3/3 and Cmd 40/20/24/24 - 40/20/30/30 even higher clickdrivestrengths 60/24/30/30 and things like that. Tried some setup timings as well. tried procODT's between 30-40, and also on auto. Any tips?

This is a fast not that tight oc with GDM on


----------



## Audioboxer

Something else interesting I've noticed which I think is to do with tRFC is how the last part of a cycle behaves in TM5. It usually takes me about 6 minutes to do a cycle, sometimes a bit lower or higher depending on free memory tested.

With some timing settings the last part of the cycle might finish around 5 min 30 and then there is 30 seconds of idle before memory refreshes and the next cycle starts. On the tRFC settings I'm using just now the testing appears to go right to like 5 minutes 55 and then the refresh of the memory happend in a few seconds. Both completing in like 6 minutes but visually the cycle ending/refreshing differently.

Hope I'm explaining that OK. Will try to add some pictures of what I mean. I've been wondering if this is to do with how clock cycles work and an indication of potentially using incorrect tRFC values. TM5 doesn't fail or anything, it's just an observation I've made a few times now on how the end of a cycle can behave before it moves onto the next cycle.


----------



## Imprezzion

I got bored. Now that 3733 15-15-8-15-30-45-270-1T is fully stable at 1.55v vDIMM I decided to see what it would take to make the DIMM's do tCL 13 due to even not training tPHYRDL.

1.550v wouldn't even POST. 1.60v made it to Windows only to BSOD with memory_management. 1.640v so far runs TM5 right now. Let's see if these early PCB B-Die but bad bin can handle 1.640v.

Temps are fine, I run no side panel now and a 120mm @ 1000 RPM with fresh air on the RAM. I'd be very surprised if they go over 41c on 1.640.

38.8c, 3 errors. 6,10,12 in the first 10 minutes. It ain't going to happen lol.

EDIT: is there any benefit to run tRAS lower than tCL+tRP? I kinda wanna do that so I can drop tRC and tRFC as well but yeah if it doesn't scale there's not much point to it.


----------



## Audioboxer

Imprezzion said:


> I got bored. Now that 3733 15-15-8-15-30-45-270-1T is fully stable at 1.55v vDIMM I decided to see what it would take to make the DIMM's do tCL 13 due to even not training tPHYRDL.
> 
> 1.550v wouldn't even POST. 1.60v made it to Windows only to BSOD with memory_management. 1.640v so far runs TM5 right now. Let's see if these early PCB B-Die but bad bin can handle 1.640v.
> 
> Temps are fine, I run no side panel now and a 120mm @ 1000 RPM with fresh air on the RAM. I'd be very surprised if they go over 41c on 1.640.
> 
> 38.8c, 3 errors. 6,10,12 in the first 10 minutes. It ain't going to happen lol.


Join the boredom club lol. If you can get it going at 1.64v you might stand a chance. On DR it's around 1.66~1.68v+ I really start to have problems running at full capacity. For example










I can get tCL12 booting into Windows at 1.65v, but it's super unstable. Needs to be nearer 1.68v to stand a chance, but then crashes on 10/2 can be quite common. Sticks just struggle to handle such high VDIMM at full capacity.










Messing around with the right hand side can sometimes get me past that early 10, but it usually fails shortly after. Haven't managed to complete a full cycle at a voltage as high as 1.68v.


----------



## domdtxdissar

Imprezzion said:


> EDIT: is there any benefit to run tRAS lower than tCL+tRP? I kinda wanna do that so I can drop tRC and tRFC as well but yeah if it doesn't scale there's not much point to it.


Memory timings testing 








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Was wondering where my RAM buddy was, nothing separating us! (other than a few timings lol). I always thought tRDWR going higher would impact performance more than tCWL dropping down but it's something we can test! 10/10 doesn't post for me btw, so it seems we're sticking close to the formula...




www.overclock.net


----------



## TheBoy08

Taraquin said:


> Try getting 2T gdm off stable and maybe 1t, but then you must alter DrvStr etc. As for teh rest of the timings most is good, but try RAS 27 since RC= RP+RAS, WR 12 unless you can do 2t since RTP should be half of WR and GDM don`t allow odd RTP, try RFC 248 since it should be divideable by 8, RDWR should be 10 since it`s generally half of RCDRD on SR-kits, but you must add 1 for each -2 on CWL you do.


Everything you told me works and is stable except CR 2T or GDM off, I can't post whenever I try it. I tried flat 14 but it doesn't post either. No idea what I should modify to get it to work tbh (limited knowledge)


----------



## Taraquin

TheBoy08 said:


> Everything you told me works and is stable except CR 2T or GDM off, I can't post whenever I try it. I tried flat 14 but it doesn't post either. No idea what I should modify to get it to work tbh (limited knowledge)


Try cwl 14, rp 14, rdwr 8, 1.53 or 1.54v dimm if you have good cooling, drvstr 40 20 30 24 and 2T.


----------



## Imprezzion

domdtxdissar said:


> Memory timings testing
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Was wondering where my RAM buddy was, nothing separating us! (other than a few timings lol). I always thought tRDWR going higher would impact performance more than tCWL dropping down but it's something we can test! 10/10 doesn't post for me btw, so it seems we're sticking close to the formula...
> 
> 
> 
> 
> www.overclock.net


Aight so, SCL 2 which I do run right now is not recommended on my DR's and tRAS + tRC under the "correct" value will scale just fine as will a trap or tRCD lower than tCL. Nice to know. Thanks bro.


----------



## Owterspace

mongoled said:


> I am a little confused with what you have posted here.
> 
> This looks like you are using PBO, but then your effective clocks look like you are using a static overclock of 4.7 Ghz.
> 
> Has something changed in BIOS development that I have not noticed ?
> 
> PBO is automatically disabled/non-functional when using a static overclock.
> 
> I am assuming that you are using a static overclock as your max effective frequency is locked to 4.7Ghz, this is not something I have ever seen before when using PBO and running LinpackXtreme, my effective clocks range from 4.46 Ghz to 4.85 Ghz when running the stress test.


That is just a static oc.. 1 clock 1 voltage.


----------



## TheBoy08

Taraquin said:


> Try cwl 14, rp 14, rdwr 8, 1.53 or 1.54v dimm if you have good cooling, drvstr 40 20 30 24 and 2T.


Tried it, it doesn't post but it is "weird" because it let's me get back into the bios instead of just having everything on with no monitor signal like it usually does. Not sure if that is relevant but here it is lol


----------



## Imprezzion

While it won't drop tCL to 13 or tRCD to 14 it will drop tRP to 13 without any extra voltage. Allowing me to match tRAS with tCL+tRP and such as well. 
It passed the full 25 cycles but I forgot to make a new snipping tool screenshot and clicked it away  Did make this one an hour in before dinner tho. 

I tried running with tWTR 3/8 or 3/7 as well but that gave a Error #8 (= Error 1) quite late into the tests so I find it hard to test for that timing as it usually takes at least 1-1.5 hours to actually show that error. 

Also, I can't get tWRRD to go anything under 4 under any circumstance. What other timings affect that one? I know tCWL has an effect on tRDWR for example but what determines how low tWRRD can go?

Next up, trying to bench and test for lower tRAS = tRC + tRFC and see how low it can go. Probably going for 25 tRAS + 40 tRC + 240 tRFC first and see what that does.


----------



## Taraquin

TheBoy08 said:


> Tried it, it doesn't post but it is "weird" because it let's me get back into the bios instead of just having everything on with no monitor signal like it usually does. Not sure if that is relevant but here it is lol


Okay, you could try 15-15-15-30-45 on primaries and 2t, see if it boots and then try tweaking it down.


----------



## Luggage

Audioboxer said:


> __
> 
> 
> 
> 
> 
> MEG X570 UNIFY | Motherboard | MSI Global
> 
> 
> Best AMD AM4 X570 ATX gaming motherboard, lightning PCIe 4.0, three lightning M.2, Frozr heatsink, WiFi 6, aluminum cove with extended heatsink, USB 3.2 Gen 2, M.2 heatsink, excellent overclocking, pre-install I/O, MSI GAMING
> 
> 
> 
> 
> www.msi.com
> 
> 
> 
> 
> 
> AGESA 1.2.0.5 final BIOS dropping for x570 boards. Will be interesting to see if there is still a CPU voltage cap when increasing EDC.


Will check as soon as hydra has finished diagnostics.


----------



## Reaxer

Reaxer said:


> I just got some new memory, this 3600C14 kit was on sale, so I got it. CMW32GX4M2Z3600C14
> I started with trying to boot GDM off 2T, but it wouldn't post with whatever settings i tried. RTT 6/3/4, 7/3/3 and Cmd 40/20/24/24 - 40/20/30/30 even higher clickdrivestrengths 60/24/30/30 and things like that. Tried some setup timings as well. tried procODT's between 30-40, and also on auto. Any tips?
> 
> This is a fast not that tight oc with GDM on
> View attachment 2539859


Okay! I got GDM off to post! 60/20/20/24 and 40/20/20/24 seem to work. BUT the RTT's still cause it not to boot, 6/3/4 and 7/3/3 both fail to post, tried procODT 30 and 36.9 with both. 
Could someone point me in the right direction to get better RTT's or should I just use the one's my mobo autosets?

EDIT. 40/20/24/24 and 40/20/30/30 also post fine, RTT's were the problem then.


----------



## Imprezzion

Well, it actually runs totally fine with lower tRP. tRAS and tRFC on 1.550v vDIMM so far. Got sub 130ns now.
This also gave me slightly higher write speeds and 0.8ns lower latency in AIDA and scales nicely in LinX and y-cruncher and x265 so I doubt I have any mismatches anywhere.

EDIT: 2 hours is long enough. It's fine. Stable enough. This is probably about as tight as I can go on 1.550v vDIMM. And i'm happy it works with a low VDDG, VDDP and vSOC. Saves me some power and temp budget for the PBO2 OC hehe.


----------



## Snipie-PT

Hey guys, running 4DIMM's SR with 1.552V, so far tPHYRDL is 26 across all 4 sticks, any way to improve L3 values a bit more, what should be the procedure?
If anyone got a suggestion on the timings used (maybe I've done something wrong) please do tell.

Thanks everyone!


----------



## Imprezzion

Snipie-PT said:


> Hey guys, running 4DIMM's SR with 1.552V, so far tPHYRDL is 26 across all 4 sticks, any way to improve L3 values a bit more, what should be the procedure?
> If anyone got a suggestion on the timings used (maybe I've done something wrong) please do tell.
> 
> Thanks everyone!
> 
> View attachment 2539928


tRRD_L 4 maybe. tRAS a tad lower. tWRWRDD 6.
L3 seems fine to me. Better latency then I get lol even tho write is a tad low but that can be AIDA as well.

Oh and your IOD voltage is a tad high.


----------



## mongoled

Owterspace said:


> That is just a static oc.. 1 clock 1 voltage.


Thanks for the confirmation.

Somehow I must be remebering incorrectly, when I use static overclock I thought all the PBO values in HWInfo64 disappeared, hence the reason for my confusion.



Imprezzion said:


> Well, it actually runs totally fine with lower tRP. tRAS and tRFC on 1.550v vDIMM so far. Got sub 130ns now.
> This also gave me slightly higher write speeds and 0.8ns lower latency in AIDA and scales nicely in LinX and y-cruncher and x265 so I doubt I have any mismatches anywhere.
> 
> EDIT: 2 hours is long enough. It's fine. Stable enough. This is probably about as tight as I can go on 1.550v vDIMM. And i'm happy it works with a low VDDG, VDDP and vSOC. Saves me some power and temp budget for the PBO2 OC hehe.
> 
> View attachment 2539927


Nah, you need to get to 25 cycles, so many times ive seen errors happen at 19, 20 ...


----------



## Audioboxer

mongoled said:


> Thanks for the confirmation.
> 
> Somehow I must be remebering incorrectly, when I use static overclock I thought all the PBO values in HWInfo64 disappeared, hence the reason for my confusion.
> 
> 
> Nah, you need to get to 25 cycles, so many times ive seen errors happen at 19, 20 ...












Or during cycle 4x 

#Team50Cycles


----------



## 67091

Hey guys as I've stated before I can't for the life of me get the IF higher than 1800 is there anything that I could do settings wise to maybe get it higher? 
I've had 3700X 3900X and a 3800X and they all got to 1900 IF but since I've brought this CPU on release I couldn't get anything higher than 1800 even with all settings on auto.
Kind Regards


----------



## Imprezzion

There is a point at which running any test long enough on anything that isn't totally stock will produce an error. 

For me personally I just don't really care that much about it. If it's stable enough to do 2 hours of TM5 and several other tests it won't crash in gaming. And if it roes it'll be so rare I don't really care at that point. Take Battlefield 2042 for example. I have never even once had a single crash in multiplayer in that game while several of my mates with totally stock systems with no OC at all have constant crashes. 



angushades said:


> Hey guys as I've stated before I can't for the life of me get the IF higher than 1800 is there anything that I could do settings wise to maybe get it higher?
> I've had 3700X 3900X and a 3800X and they all got to 1900 IF but since I've brought this CPU on release I couldn't get anything higher than 1800 even with all settings on auto.
> Kind Regards
> View attachment 2540035


Set voltages like this: 

CLDO_VDDP 0.900
CCD 0.950
IOD 1.050-1.110
vSOC 1.150-1.200

Try to run 1933 or 1966 in case you have a IF hole like my chip. 1900 will not POST under any circumstances but 1933 is fine.

Also, ProcODT 34.3/36.9, RTT's at 6/3/3 or disabled/3/1, up the ClkDrvStr a bit to like 40, add AddrCmdSetup 56-60 if it wont POST 1T at 38xx. 

Those settings got basically any combination of clocks, timings and infinity fabric to boot for me. Won't say it's stable but it can "force" it to POST / boot basically any setting. 

Thanks to a lot of people here teaching me all these small intricacies of AMD


----------



## Audioboxer

Imprezzion said:


> There is a point at which running any test long enough on anything that isn't totally stock will produce an error.
> 
> For me personally I just don't really care that much about it. If it's stable enough to do 2 hours of TM5 and several other tests it won't crash in gaming. And if it roes it'll be so rare I don't really care at that point. Take Battlefield 2042 for example. I have never even once had a single crash in multiplayer in that game while several of my mates with totally stock systems with no OC at all have constant crashes.


Not a good way to view memory, because instability/crashes with memory can result in corruption. It's not like an unstable GPU which will just crash the display and that's it.

Think of how many hours your PC will be running, likely thousands, and consider what errors every few hours _could_ result in. Memory is either stable or it's not, the only thing one has to sometimes watch for is temp related instability. But that's partly why we run stability tests for hours.

As much as I was joking with @mongoled above, that 50 cycle did actually bring up a powerdown error I had never gotten before. Changing CkeDrvStr to 30 cleared it










And for shrugging off 25 cycles, let alone 50, the Anta777 profile is ran by many for like 7~9 hours and then Karhu for even longer










They say when you go to the gym don't skip leg day, overclockers would say don't skip _memory stability day_. For all the time it takes it's not worth cutting corners.


----------



## TheBoy08

Taraquin said:


> Okay, you could try 15-15-15-30-45 on primaries and 2t, see if it boots and then try tweaking it down.


It doesn't boot


----------



## Imprezzion

Audioboxer said:


> Not a good way to view memory, because instability/crashes with memory can result in corruption. It's not like an unstable GPU which will just crash the display and that's it.
> 
> Think of how many hours your PC will be running, likely thousands, and consider what errors every few hours _could_ result in. Memory is either stable or it's not, the only thing one has to sometimes watch for is temp related instability. But that's partly why we run stability tests for hours.
> 
> As much as I was joking with @mongoled above, that 50 cycle did actually bring up a powerdown error I had never gotten before. Changing CkeDrvStr to 30 cleared it
> 
> View attachment 2540039
> 
> 
> And for shrugging off 25 cycles, let alone 50, the Anta777 profile is ran by many for like 7~9 hours and then Karhu for even longer
> 
> View attachment 2540041
> 
> 
> They say when you go to the gym don't skip leg day, overclockers would say don't skip _memory stability day_. For all the time it takes it's not worth cutting corners.


On Intel I did test my 4400 C17 profile with anta extreme for a full 14 hours and that was fine but yeah. 

I have now done 3 separate 2 hour (20 cycles) 1usmus runs, overnight Corecycler, overnight y-cruncher and some gaming stuff with the same memory timings just slightly lower VDDG/VDDP/vSOC so I can safely say the memory is fine. Whether the other voltages are too low or not for my IF clock that is.. questionable. But so far no WHEA's or weird errors. 

I finally have a week off now between Xmas and new year and I am not wasting my entire week off just stress testing. I wanna actually play some games. This is good enough to run a week's worth of games.


----------



## Audioboxer

Imprezzion said:


> On Intel I did test my 4400 C17 profile with anta extreme for a full 14 hours and that was fine but yeah.
> 
> I have now done 3 separate 2 hour (20 cycles) 1usmus runs, overnight Corecycler, overnight y-cruncher and some gaming stuff with the same memory timings just slightly lower VDDG/VDDP/vSOC so I can safely say the memory is fine. Whether the other voltages are too low or not for my IF clock that is.. questionable. But so far no WHEA's or weird errors.
> 
> I finally have a week off now between Xmas and new year and I am not wasting my entire week off just stress testing. I wanna actually play some games. This is good enough to run a week's worth of games.


I run most of my longer tests overnight lol. That way you get the excitement of waking up hoping it's passed!


----------



## Owterspace

I use Anta extreme, last few passes were with absolute.. what do you guys like?


----------



## KedarWolf

Thos on the AGESA 1.2.0.3c BIOS for my Unify-X.










My X570S Unify-X Max was supposed to be delivered today. Now tracking says Jan. 6th.

Friggin' Newegg used Canada Post instead of Purolator, and I paid $24.99 for shipping.

Edit: Called Newegg, they said if I don't receive it by Jan. 4th, they'll fully refund the shipping.


----------



## TheBoy08

KedarWolf said:


> Thos on the AGESA 1.2.0.3c BIOS for my Unify-X.
> 
> View attachment 2540065
> 
> 
> My X570S Unify-X Max was supposed to be delivered today. Now tracking says Jan. 6th.
> 
> Friggin' Newegg used Canada Post instead of Purolator, and I paid $24.99 for shipping.
> 
> Edit: Called Newegg, they said if I don't receive it by Jan. 4th, they'll fully refund the shipping.


You think you're gonna get better results on the x570-S?


----------



## KedarWolf

TheBoy08 said:


> You think you're gonna get better results on the x570-S?


To be honest, no. Not until I can afford CL14 4000 G.Skill RAM.


----------



## TheBoy08

KedarWolf said:


> To be honest, no. Not until I can afford CL14 4000 G.Skill RAM.


What makes you say that?
I went from a x570 Dark Hero to a B550 Unify-X and benchmarks scored lower. I might just send back my B550 Unify-X and get the x570S Unify-X


----------



## KedarWolf

TheBoy08 said:


> What makes you say that?
> I went from a x570 Dark Hero to a B550 Unify-X and benchmarks scored lower. I might just send back my B550 Unify-X and get the x570S Unify-X


It might be a bit better on the CPU overclocking, but the memory will likely not change.


----------



## TheBoy08

KedarWolf said:


> It might be a bit better on the CPU overclocking


Yes, 100%. I could clock higher on the Dark Hero. Ram timings were basically the same... **** it I'll pull the plug and buy it, my B550 has a coil whine issue anyway


----------



## 67091

Imprezzion said:


> There is a point at which running any test long enough on anything that isn't totally stock will produce an error.
> 
> For me personally I just don't really care that much about it. If it's stable enough to do 2 hours of TM5 and several other tests it won't crash in gaming. And if it roes it'll be so rare I don't really care at that point. Take Battlefield 2042 for example. I have never even once had a single crash in multiplayer in that game while several of my mates with totally stock systems with no OC at all have constant crashes.
> 
> 
> 
> Set voltages like this:
> 
> CLDO_VDDP 0.900
> CCD 0.950
> IOD 1.050-1.110
> vSOC 1.150-1.200
> 
> Try to run 1933 or 1966 in case you have a IF hole like my chip. 1900 will not POST under any circumstances but 1933 is fine.
> 
> Also, ProcODT 34.3/36.9, RTT's at 6/3/3 or disabled/3/1, up the ClkDrvStr a bit to like 40, add AddrCmdSetup 56-60 if it wont POST 1T at 38xx.
> 
> Those settings got basically any combination of clocks, timings and infinity fabric to boot for me. Won't say it's stable but it can "force" it to POST / boot basically any setting.
> 
> Thanks to a lot of people here teaching me all these small intricacies of AMD


You are right I can post past 1800 but I get heaps of WHEA errors. If I'm getting heaps of WHEA errors is that because it's kinda the limit on the IF or can I clear that up with more voltage as I've tried adding more volts to each setting but it only lowers the WHEA errors a little and on another note even though I'm setting my timing up like 15.15.15.30 in bios my MSI X570 ACE is automatically making the timing 16.15.15.30 why is that?


----------



## domdtxdissar

TheBoy08 said:


> What makes you say that?
> I went from a x570 Dark Hero to a B550 Unify-X and benchmarks scored lower. I might just send back my B550 Unify-X and get the x570S Unify-X


Unify x max also scores lower (in cinebench) then regular hero 8.. Hoping its down to the bios atm (bios v1 1203C)
But if this is the case after bios 1205 get released for this motherboard i'm not sure what i will do..

Ram OC is better without doubt on the MSI tho


----------



## Imprezzion

angushades said:


> You are right I can post past 1800 but I get heaps of WHEA errors. If I'm getting heaps of WHEA errors is that because it's kinda the limit on the IF or can I clear that up with more voltage as I've tried adding more volts to each setting but it only lowers the WHEA errors a little and on another note even though I'm setting my timing up like 15.15.15.30 in bios my MSI X570 ACE is automatically making the timing 16.15.15.30 why is that?


Is GDM still on? That would sort of explain the timings shifting.

You can get rid of the WHEA's but not always. 1933 for me takes a lot of tweaking but I can get it 98% WHEA free. Only very extreme loads like y-cruncher can give 1 or 2 still but never in normal usage. 

More voltage isn't always the answer for this problem tho. IOD and vSOC and a bit more CPU 1.8v can fix a lot. Try 0.950 CLDO, 0.980 CCD, 1.100 IOD, 1.200 SOC, 1.850 CPU 1.8v and also a relatively high ProcODT (36.9 or 40) with, at 1T at least, AddrCmdSetup 56.


----------



## 67091

Imprezzion said:


> Is GDM still on? That would sort of explain the timings shifting.
> 
> You can get rid of the WHEA's but not always. 1933 for me takes a lot of tweaking but I can get it 98% WHEA free. Only very extreme loads like y-cruncher can give 1 or 2 still but never in normal usage.
> 
> More voltage isn't always the answer for this problem tho. IOD and vSOC and a bit more CPU 1.8v can fix a lot. Try 0.950 CLDO, 0.980 CCD, 1.100 IOD, 1.200 SOC, 1.850 CPU 1.8v and also a relatively high ProcODT (36.9 or 40) with, at 1T at least, AddrCmdSetup 56.


 Yes gear mode is on and I don’t think it’s possible to run it off without it. Ok well I can easily do 3733 without no problems and same timing as I had with my 3600. Would be great to be able to have no GDM on though


----------



## Imprezzion

angushades said:


> Yes gear mode is on and I don’t think it’s possible to run it off without it. Ok well I can easily do 3733 without no problems and same timing as I had with my 3600. Would be great to be able to have no GDM on though


1T GDM Off needs a lot of tweaking with the setup timings, resistances and RTT's. 2T GDM Off is pretty easy and should just work out of the box. Otherwise, just do what I run, 3733 with IF 1866 with as tight as possible timings. If you wanna run GDM on that will probably be 14-14-14-28-42-252-1T GDM if you have enough temperature headroom on the RAM modules to run 1.5-1.55v on them. tWR 12, tRTP 6, tCWL 14 and so forth.


----------



## 67091

Imprezzion said:


> 1T GDM Off needs a lot of tweaking with the setup timings, resistances and RTT's. 2T GDM Off is pretty easy and should just work out of the box. Otherwise, just do what I run, 3733 with IF 1866 with as tight as possible timings. If you wanna run GDM on that will probably be 14-14-14-28-42-252-1T GDM if you have enough temperature headroom on the RAM modules to run 1.5-1.55v on them. tWR 12, tRTP 6, tCWL 14 and so forth.


Yea bro I’ve got bdie good stuff could I get your full list on zen timing and I’ll tweak from there please.


----------



## Taraquin

TheBoy08 said:


> It doesn't boot


Okay, go with the best you can get from GDM on then. GDM fixes a lot if instabilities, but is a bit slower than 2T and especially 1T, but seems worth it for you.


----------



## ultraex2003_9978

My setup 5800x 16 giga @ 3800 cas 15 GDM disable


----------



## Taraquin

TheBoy08 said:


> Everything you told me works and is stable except CR 2T or GDM off, I can't post whenever I try it. I tried flat 14 but it doesn't post either. No idea what I should modify to get it to work tbh (limited knowledge)


I would try 14 CWL and 8 RDWR, that will probably increase perf  You could try RFC 240 or 232, but you might not have enough voltage.


----------



## Taraquin

ultraex2003_9978 said:


> My setup 5800x 16 giga @ 3800 cas 15 GDM disable
> View attachment 2540148


RDWR 8, RTP 7, WRRD 1, SCL's 4, RFC 264 if you use 1.45V on dimm, 256 or 248 if using 1.5V.


----------



## Taraquin

angushades said:


> Yea bro I’ve got bdie good stuff could I get your full list on zen timing and I’ll tweak from there please.


Just try 2T gdm off first and see if it boots  1T can work with 40 20 30 24 on DrvStr, but might not. You may need higher voltage and other ProcODT.


----------



## TMavica

I can boot into windows using 1T gdm off and 14-15-15-15-35(default docp), others setting is also auto by docp. When I want to adjust to 14-14-14-14-34, tm5 always give me error 6 and 12, whenever I add voltage or adjust the resistance. Any suggestion?


----------



## Taraquin

TMavica said:


> I can boot into windows using 1T gdm off and 14-15-15-15-35(default docp), others setting is also auto by docp. When I want to adjust to 14-14-14-14-34, tm5 always give me error 6 and 12, whenever I add voltage or adjust the resistance. Any suggestion?


Try DrvStr 40 20 30 24, experiment with ProcODT 28-36.9 if you have 2x8 or 36.9 to 48 if you have 2x16 dual rank.


----------



## MurderBurger

Hey guys have a 5800x with some steel viper 4400mhz cl19 ram.. was wondering if any had a 2000mhz loose timings starting point timings for me to work off of?


----------



## Taraquin

MurderBurger said:


> Hey guys have a 5800x with some steel viper 4400mhz cl19 ram.. was wondering if any had a 2000mhz loose timings starting point timings for me to work off of?


I have that kit, recommend finding out if you can run 2000 fclk without WHEA 19s first, just run xmp and set ram to 4000, fclk to 2000. If that work try:
1.45V
16 16 16 32 48
Rrd 4/6
Faw 16
Wr 16
Rtp 8
Wtr 4/12
Scl's 4
Cwl 16
Rfc 288
Rdwr 8
Wrrd 1

Use geardown mode

Rest on auto

Set soc to 1.12v, vddg iod to 1.04v, vddg ccd to 0.92v and vdfp to 0.88. You may need a bit more on the first 2, try 1.14v soc and 1.06 iod if this gives you poor aida etc. 

If you get WHEA 19s on 4000/2000 try 3933, 3866 or 3800, see which is highest you can run WHEA 19 free. 

If it's 3800/1900 try same timings, but try rfc 272. Lower soc and iod by 0.04v each.Tell us how it goes and you can try further. 

If you get 4000 stable at the above timings you should see around 100sec in dram calc test and 52-54ns in aida.


----------



## TMavica

Taraquin said:


> Try DrvStr 40 20 30 24, experiment with ProcODT 28-36.9 if you have 2x8 or 36.9 to 48 if you have 2x16 dual rank.


I am using 16x2 F4000CL14. Tried both setting, still get error 6 and 12…my soc is 1.15, vdimm 1.55, ProcODT 48, others is auto, zentiming show VLLP is 1.1 in auto. Maybe need some adjustment in external digi? VDDSOC already in LL4 and 130%..or something i missed? It is possible stuck in default docp TRCD..?


----------



## Taraquin

TMavica said:


> I am using 16x2 F4000CL14. Tried both setting, still get error 6 and 12…my soc is 1.15, vdimm 1.55, ProcODT 48, others is auto, zentiming show VLLP is 1.1 in auto. Maybe need some adjustment in external digi? VDDSOC already in LL4 and 130%..or something i missed? It is possible stuck in default docp TRCD..?


It may be that you are on the limits of the kit. Try working with subtimings instead, rc, faw, rfc and some others generally matters more for performance than the 3 primaries if left on auto. At 4000 auto rfc is usually around 700, with your vdimm you can probably do 256 and maybe 240 which will improve performance by 5-10% in some games. Post your zentimings and I can suggest some tweaks.


----------



## TMavica

Taraquin said:


> It may be that you are on the limits of the kit. Try working with subtimings instead, rc, faw, rfc and some others generally matters more for performance than the 3 primaries if left on auto. At 4000 auto rfc is usually around 700, with your vdimm you can probably do 256 and maybe 240 which will improve performance by 5-10% in some games. Post your zentimings and I can suggest some tweaks.


I think so. Because I am free of WHEA in 3800, but everytime adjust the TRCD/TRAS, the errors came out…It is ridiculous of a pair expensive ram kit G.skill F4000CL14GTES. Here is my zentiming until now, all put in auto now except tRFC and TRC, also I need 56 56 56 Addrcmdsetup and prevent error 6 and 12 came out
PS: Vdimm is 1.55 and VTT is 0.77. This is a problem with ROG extreme motherboard.


----------



## Taraquin

TMavica said:


> I think so. Because I am free of WHEA in 3800, but everytime adjust the TRCD/TRAS, the errors came out…It is ridiculous of a pair expensive ram kit G.skill F4000CL14GTES. Here is my zentiming until now, all put in auto now except tRFC and TRC, also I need 56 56 56 Addrcmdsetup and prevent error 6 and 12 came out
> PS: Vdimm is 1.55 and VTT is 0.77. This is a problem with ROG extreme motherboard.
> View attachment 2540172


Set vddp to 900, 1100 is way too high  Try ras 29, rc 44, rfc 272, rrds 4, rrdl 6, faw 16, wtrs 4, wtrl 12, wr 14, scl`s 4, cwl 14, rdwr 9, rtp 7, wrrd 3, see how that goes? Test for instance dram calc membench before and after.


----------



## Audioboxer

TMavica said:


> I think so. Because I am free of WHEA in 3800, but everytime adjust the TRCD/TRAS, the errors came out…It is ridiculous of a pair expensive ram kit G.skill F4000CL14GTES. Here is my zentiming until now, all put in auto now except tRFC and TRC, also I need 56 56 56 Addrcmdsetup and prevent error 6 and 12 came out
> PS: Vdimm is 1.55 and VTT is 0.77. This is a problem with ROG extreme motherboard.
> View attachment 2540172


While copying someone else's settings isn't the way to do memory OCing, here is something to aim for with that kit










dom has some settings even lower than mine, but the above is _probably_ obtainable on most of these 4000 14-15-15-15 1.55v rated kits. Ymmv though.


----------



## TMavica

Audioboxer said:


> While copying someone else's settings isn't the way to do memory OCing, here is something to aim for with that kit
> 
> View attachment 2540177
> 
> 
> dom has some settings even lower than mine, but the above is _probably_ obtainable on most of these 4000 14-15-15-15 1.55v rated kits. Ymmv though.


When i change the trcd trp tras, it just gave me error 6 and 12 in tm5. I have increased many voltage and resistance, result still the same…I dont know why. I just thinking, do I need change other settings in bios too. All my timing is auto DOCP, no any modification, just change trcd trp tras only, add voltage/resistance, result is the same


----------



## TMavica

deleted


----------



## TimeDrapery

Here's some free chicken... This is on an old set of G.Skill DIMMs


----------



## Imprezzion

What is the benefit, or downside, of running RTT_nom at 6 or 7 compared to just disabled. My RAM really wants it disabled above 3600. Any other setting above disabled won't be anywhere near as stable above that.


----------



## 67091

Hey guys so this is my setup now and it’s posting great and I can play oxygen not included lol and windows feels more snappy anyhow I’m getting errors about 1min when running TM5 where can I get the other profile to understand where the errors are coming from.computer post and runs fine though lol


----------



## Imprezzion

angushades said:


> Hey guys so this is my setup now and it’s posting great and I can play oxygen not included lol and windows feels more snappy anyhow I’m getting errors about 1min when running TM5 where can I get the other profile to understand where the errors are coming from.computer post and runs fine though lol
> View attachment 2540240


Quote from the Ryzen Google sheet for error #0.

"Voltage cutoff choke, suspect tRRD & tWTR
Nearly always tRRD & tWTR but can also be too low tRP 
or tiny bit too low tRC (if user used > -3 on tRC)

Start by adding VDIMM
6x Error 0 = BSOD

2,0,0,0,0 = not enough VDIMM
0,0,0,6,6,6 = too low SCL, bad tWRRD" 

So yeah, more vDIMM.


----------



## MurderBurger

Taraquin said:


> I have that kit, recommend finding out if you can run 2000 fclk without WHEA 19s first, just run xmp and set ram to 4000, fclk to 2000. If that work try:
> 1.45V
> 16 16 16 32 48
> Rrd 4/6
> Faw 16
> Wr 16
> Rtp 8
> Wtr 4/12
> Scl's 4
> Cwl 16
> Rfc 288
> Rdwr 8
> Wrrd 1
> 
> Use geardown mode
> 
> Rest on auto
> 
> Set soc to 1.12v, vddg iod to 1.04v, vddg ccd to 0.92v and vdfp to 0.88. You may need a bit more on the first 2, try 1.14v soc and 1.06 iod if this gives you poor aida etc.
> 
> If you get WHEA 19s on 4000/2000 try 3933, 3866 or 3800, see which is highest you can run WHEA 19 free.
> 
> If it's 3800/1900 try same timings, but try rfc 272. Lower soc and iod by 0.04v each.Tell us how it goes and you can try further.
> 
> If you get 4000 stable at the above timings you should see around 100sec in dram calc test and 52-54ns in aida.


Its going through tm5 ATM with the 4000/2000.. I swapped to a b550 asrock extreme4 from a Asus impact viii x570 which wouldn't even boot this ram with every part being the same besides the motherboard above 3800/1900. 450motherboard getting outshined by a 130dollar Christmas deal board lol


----------



## Imprezzion

MurderBurger said:


> Its going through tm5 ATM with the 4000/2000.. I swapped to a b550 asrock extreme4 from a Asus impact viii x570 which wouldn't even boot this ram with every part being the same besides the motherboard above 3800/1900. 450motherboard getting outshined by a 130dollar Christmas deal board lol


Kinda makes me wonder if somehow B550 in general clocks better with IF and memory compared to non S X570's? 

I am really curious what my DIMM's will do in one of my mates systems.. might ask him if I can try that once. He has a X570 Strix-F with a 5800X but with cheap 2x8 3200C16 RAM he's been wanting to upgrade to 32GB B-Die. Might do a little pre-test of his IF and such with my RAM before he buys a kit. Probably going to be Patriot Viper 4400C19's as they are basically the cheapest b-die kit you can get here at the moment.


----------



## MurderBurger

Imprezzion said:


> Kinda makes me wonder if somehow B550 in general clocks better with IF and memory compared to non S X570's?
> 
> I am really curious what my DIMM's will do in one of my mates systems.. might ask him if I can try that once. He has a X570 Strix-F with a 5800X but with cheap 2x8 3200C16 RAM he's been wanting to upgrade to 32GB B-Die. Might do a little pre-test of his IF and such with my RAM before he buys a kit. Probably going to be Patriot Viper 4400C19's as they are basically the cheapest b-die kit you can get here at the moment.


So your timings worked fine 1.47v on my kit with gaming / streaming at the same time. 4000/2000mhz and passed 3 hours of tm5 v3 1usmus.. I tried I think it was 4033/2066mhz hit 51latency but need to actually run tm5 on it


----------



## blodflekk

Just trying to get the finishing touches on my daily 24/7 profile @ 3600 CL14. Passed 25 cycles of tm5 no WHEA, wanted to run 50 cycles to verify it further. Got 2 errors, test #1 and test #10.


Still no WHEA though. Running vDIMM 1.48 on latest bios 3904


----------



## Spectre73

blodflekk said:


> Just trying to get the finishing touches on my daily 24/7 profile @ 3600 CL14. Passed 25 cycles of tm5 no WHEA, wanted to run 50 cycles to verify it further. Got 2 errors, test #1 and test #10.
> 
> 
> Still no WHEA though. Running vDIMM 1.48 on latest bios 3904
> 
> View attachment 2540294


You can lookup the errors here: Ryzen Google Calculator!
I would increase tRCDRD to 15 an probably tWR 12. SCL 2 are not needed, 4 is perfectly fine and IMHO not slower on Zen 3


----------



## blodflekk

Is it necessary to loosen timings so much at 3600? I feel like I'm missing something with voltages, drive strengths, setup times or resistances.


----------



## Taraquin

blodflekk said:


> Is it necessary to loosen timings so much at 3600? I feel like I'm missing something with voltages, drive strengths, setup times or resistances.


Try 1.49V, it could be that simple, and try scls at 4, more stable and often better performance. I would try 3800cl15 if it was my setup, probably a bit faster due to better bandwith and might work at same voltages, maybe you need a bit more soc/iod, maybe not.


----------



## Mappi75

Anyone here with Threadripper 3970X & 256GB RAM?
(G.Skill 3600 CL16)
Searching for Infos how to tune the latencies..thanks!


----------



## Reaxer

Mappi75 said:


> Anyone here with Threadripper 3970X & 256GB RAM?
> (G.Skill 3600 CL16)
> Searching for Infos how to tune the latencies..thanks!
> View attachment 2540310
> 
> 
> View attachment 2540311


Do you know which IC your kit is using?, you can check with the 042 code on the sticks, or maybe with Thaiphoon (which is sometimes wrong)


----------



## Mappi75

I added a thumbnail in my last post. Some kind of Hynix they are..


----------



## Owterspace

These are my daily settings with my 5900X, nothing too crazy, but it works well. It will do 2K with 2 sticks, but it streams WHEA's live and in prime time lol. I did set it to 25 passes, but I want to use the machine now.


----------



## Audioboxer

blodflekk said:


> Just trying to get the finishing touches on my daily 24/7 profile @ 3600 CL14. Passed 25 cycles of tm5 no WHEA, wanted to run 50 cycles to verify it further. Got 2 errors, test #1 and test #10.
> 
> 
> Still no WHEA though. Running vDIMM 1.48 on latest bios 3904
> 
> View attachment 2540294


1 and 10 suggest resistances if the errors are coming after 25 cycles. Your ProcODT should be around 34.3~36.9 to be optimal with a 5950x and 1T/GDM disabled is going to be tough on the memory at ClkDrvStr 24. Try 30 or 40.


----------



## Taraquin

Mappi75 said:


> Anyone here with Threadripper 3970X & 256GB RAM?
> (G.Skill 3600 CL16)
> Searching for Infos how to tune the latencies..thanks!
> View attachment 2540310
> 
> 
> View attachment 2540311
> 
> 
> View attachment 2540315





Mappi75 said:


> Anyone here with Threadripper 3970X & 256GB RAM?
> (G.Skill 3600 CL16)
> Searching for Infos how to tune the latencies..thanks!
> View attachment 2540310
> 
> 
> View attachment 2540311
> 
> 
> View attachment 2540315


8x32gb modules? Set your soc to 1.1v, 1.0v is probably too low, try iod at 1.05v. As for the rest you can try and change one row at a time:

rcd 21, rp 21, ras 37, rc 58, if it doesn`t work try rcd 22, rp 22, ras 38, rc 60, if that doesn`t work try ras 40, rc 62 or work upwards always increasing ras and rc 2 each time
rrds 6, rrdl 8, faw 24, if it works try rrds 5, rrdl 7, faw 20, if that works try 4\6\16
wtrs 4, wtrl 12, if that works try lowering wtrs to 3 and wtrl in steps by 1 to 8
wr 16, rtp 8
rfc 640 or 608 or 576 or 544, if that works you can go down 32 and see how far you get
rdwr 10 or 11 or 12
wrrd 3
scl`s 4


----------



## Mappi75

@Taraquin wow thank you this gives me a lot to work for  Yes, 8x32GB modules..

Usually i use SOC only at 1,00v since month an no problems so far. But this time i got an Aida64 Stresstest Hardware failure so i went up to 1,00625v.
For testing i will raise the voltage...

but the first test is slower den faster ^^ 21-21-37-58









Second run with 1,05V SoC









Next: tRRDS 6 / tRRDL 8 / tFAW 24


----------



## Taraquin

dw


Mappi75 said:


> @Taraquin wow thank you this gives me a lot to work for  Yes, 8x32GB modules..
> 
> Usually i use SOC only at 1,00v since month an no problems so far. But this time i got an Aida64 Stresstest Hardware failure so i went up to 1,00625v.
> For testing i will raise the voltage...
> 
> but the first test is slower den faster ^^ 21-21-37-58
> 
> View attachment 2540346


Try a bit higher, aida usually gives bad latency if soc is too low. iod is derived from soc so actual iod is max 0.96v which is also quite low. You can try soc at 1.05v and iod at 1.00v first to see how that goes.


----------



## MurderBurger

Taraquin said:


> I have that kit, recommend finding out if you can run 2000 fclk without WHEA 19s first, just run xmp and set ram to 4000, fclk to 2000. If that work try:
> 1.45V
> 16 16 16 32 48
> Rrd 4/6
> Faw 16
> Wr 16
> Rtp 8
> Wtr 4/12
> Scl's 4
> Cwl 16
> Rfc 288
> Rdwr 8
> Wrrd 1
> 
> Use geardown mode
> 
> Rest on auto
> 
> Set soc to 1.12v, vddg iod to 1.04v, vddg ccd to 0.92v and vdfp to 0.88. You may need a bit more on the first 2, try 1.14v soc and 1.06 iod if this gives you poor aida etc.
> 
> If you get WHEA 19s on 4000/2000 try 3933, 3866 or 3800, see which is highest you can run WHEA 19 free.
> 
> If it's 3800/1900 try same timings, but try rfc 272. Lower soc and iod by 0.04v each.Tell us how it goes and you can try further.
> 
> If you get 4000 stable at the above timings you should see around 100sec in dram calc test and 52-54ns in aida.


Let this go today Dram is 1.47v atm..... Think I can tweak this further?


----------



## blodflekk

Audioboxer said:


> 1 and 10 suggest resistances if the errors are coming after 25 cycles. Your ProcODT should be around 34.3~36.9 to be optimal with a 5950x and 1T/GDM disabled is going to be tough on the memory at ClkDrvStr 24. Try 30 or 40.


The bump in vdimm did actually clear all the errors and I made a successful 50 cycle run. I still have one whea same as last time and I'd like to clear that if I can. I also can't find the page that was talking about how to correct mismatched training of tPHYRDL


----------



## Taraquin

MurderBurger said:


> Let this go today Dram is 1.47v atm..... Think I can tweak this further?
> View attachment 2540397


Rtp 8, that is important  are you WHEA 19 free? Further tweaks: try gdm off, 2t, rcdwr 8, rrdl 4, wtrs 3, wtrl 9 or 8, rfc 280 or 272, wr 12/rtp 6 (change these 2 at the same time). See if that works and I can try to help you get 1T stable. Change them one by one except wr/rtp which you do at the same time.


----------



## Taraquin

Mappi75 said:


> @Taraquin wow thank you this gives me a lot to work for  Yes, 8x32GB modules..
> 
> Usually i use SOC only at 1,00v since month an no problems so far. But this time i got an Aida64 Stresstest Hardware failure so i went up to 1,00625v.
> For testing i will raise the voltage...
> 
> but the first test is slower den faster ^^ 21-21-37-58
> 
> View attachment 2540346
> 
> 
> Second run with 1,05V SoC
> 
> View attachment 2540347
> 
> 
> Next: tRRDS 6 / tRRDL 8 / tFAW 24
> View attachment 2540349


It seems a bit higher soc helped, also rrd/faw greatly improved first bench in aida


----------



## 67091

So why does everybody run 1usmus_v3 instead of [email protected] in TestMem 5 , what's the difference?


----------



## Audioboxer

angushades said:


> So why does everybody run 1usmus_v3 instead of [email protected] in TestMem 5 , what's the difference?


@Veii did hours of work diagnosing what the errors might mean tRFC mini - Google Drive Go to the TM5 error description tab if it doesn't autoload.

Might not be perfect but it's very useful, especially when you're starting out overclocking your memory.


----------



## Ssdj3nt

I have Ryzen 5600X on a MSI B550 Mortar with 32(4x8)Gb at 3733mhz, cpu and ram are overclocked ad i use tight timings at 1.5v (b-die ic).
I would like to tweak a little bit my system, so i was searching for these.
My system on default values is stable with anta777 config on TM5 ( rtt_wr = 80ohm, rtt_park= 80ohm, rtt_nom= 34ohm)
What should i use or test? (Guideline for my 4x8 b-die ic)
What can potentially increase performance and reduce heat etc?

Can i set a low procODT such as 30ohm with 3733mhz? (yes it's stable but idk)


----------



## Imprezzion

Aight so my RMA has been processed for my broken 5900X and I'm getting a new one sent to me.

Now. I wanna take this opportunity to maybe switch my own board. Not that there's much wrong with the B550-XE but it has its problems and weaknesses.

How would you guys feel about the MSI X570S Edge Max WiFi? I am a real big fan of MSI in general and this is basically the only X570S board with more then 2 M.2's that isn't Gigabyte.


----------



## KedarWolf

Imprezzion said:


> Aight so my RMA has been processed for my broken 5900X and I'm getting a new one sent to me.
> 
> Now. I wanna take this opportunity to maybe switch my own board. Not that there's much wrong with the B550-XE but it has its problems and weaknesses.
> 
> How would you guys feel about the MSI X570S Edge Max WiFi? I am a real big fan of MSI in general and this is basically the only X570S board with more then 2 M.2's that isn't Gigabyte.


You might want to get the X570S Unify-X Max. Four DIMMs are not good as they are Daisy Chain and two DIMM slot boards overclock memory better.


----------



## msmeenge

Hey guys,

I'm new here and I'm busy fine-tuning my 3600c14 g skill neo kit @ 3800c14 in combination with a 5900X.
I saw everyone is using TM5 for stability testing and different configs being used. Which config is everybody using to quickly test stability (1-2h duration test for example) and what specific changes do people make in the config file according to "cycles" and "time"?
I see most people run 25 cycles, but what about the amount of time per cycle?

Thanks in advance


----------



## MurderBurger

KedarWolf said:


> You might want to get the X570S Unify-X Max. Four DIMMs are not good as they are Daisy Chain and two DIMM slot boards overclock memory better.


Sadly I am probably that one off situation because my Asus Crosshair Viii impact x570 struggles to do what my B550 Asrock Extreme4 can do with my ram.


----------



## TheBoy08

Taraquin said:


> I would try 14 CWL and 8 RDWR, that will probably increase perf  You could try RFC 240 or 232, but you might not have enough voltage.











Here's where I'm at currently. That is stable. Thanks for the advices btw


----------



## Taraquin

TheBoy08 said:


> View attachment 2540700
> 
> Here's where I'm at currently. That is stable. Thanks for the advices btw


remember that WR should be RTP x 2 so you should use 12 WR, that will work better. If you could do 2T you could do 5 RTP, but that is impossible with gear down mode.


----------



## 67091

Yea suggestions guys cause I’m about to pull my hair out .


----------



## Imprezzion

KedarWolf said:


> You might want to get the X570S Unify-X Max. Four DIMMs are not good as they are Daisy Chain and two DIMM slot boards overclock memory better.


Can't get that (yet) in the Netherlands. Plus, my DIMM's will hold me back anyway. The bin just isn't good enough to warrant that kind of extra cash. It costs nearly 150 more then a Edge or Carbon.


----------



## Audioboxer

angushades said:


> Yea suggestions guys cause I’m about to pull my hair out .
> View attachment 2540718


Not sure SR memory needs 56 setup time, even 4x8GB.

ClkDrvStr 40 might be needed. I'd probably try and aim for a flat 15 profile first with 4x8GB.

Those Rtts are commonly used with DR, SR setups I normally see different. I don't have any experience with SR though so someone else will have to advise on commonly used Rtts.


----------



## Taraquin

angushades said:


> Yea suggestions guys cause I’m about to pull my hair out .
> View attachment 2540718


First of all, can you do 3800\1900 at cl15? That would yield a bit better performance and require about the same voltages. As for the errors I would try 40-20-30-24 on DrvStr and set RTP to 6 as it should be half of WR. What ram voltage are you running? You may need RDWR to be 9, but in theory 8 could work.Rest looks fine, but RFC could be lower unless you are at 1.4V dimm which I doubt if you can do 3600cl14 flat 1t mostly stable. If you stick with 3600 try 272 or 256.


----------



## 67091

I got a error 10 just before and no I can’t do 3800 but I can do 3733 at cl15. I’ll change it .Thanks for the help guys.


----------



## KedarWolf

angushades said:


> View attachment 2540730
> 
> I got a error 10 just before and no I can’t do 3800 but I can do 3733 at cl15. I’ll change it .Thanks for the help guys.


Try tRCDRD at 16.


----------



## 67091

SPECS








I'm running 4X8 GB sticks not 2X16GB 
VDIMM 1.50 in bios but gives it about 0.20 extra so it's 1.520 in windows
SOC 1.050
CLDO 0.900
VDDG 0.900
VDDG IOD 1.050
Everything else is default


----------



## msmeenge

Can someone tell me what you guys edit in the config file of TM5?
How much "time" do u set besides 25 cycles to consider something stable?


----------



## KedarWolf

msmeenge said:


> Can someone tell me what you guys edit in the config file of TM5?
> How much "time" do u set besides 25 cycles to consider something stable?


I like to do 1000%, 8 cycles, then on my 5950x let it run overnight for about seven hours.

I think longer cycles is better than say let run 75 100% cycles run overnight, it'll find errors the second won't.


----------



## msmeenge

KedarWolf said:


> I like to do 1000%, 8 cycles, then on my 5950x let it run overnight for about seven hours.
> 
> I think longer cycles is better than say let run 75 100% cycles run overnight, it'll find errors the second won't.


Alright thanks for your explaination.
So how much time does 100% specifically stand for? And do less+longer cycles find more errors due to the cycles having more time to search for errors?


----------



## Imprezzion

msmeenge said:


> Alright thanks for your explaination.
> So how much time does 100% specifically stand for? And do less+longer cycles find more errors due to the cycles having more time to search for errors?


100% is about 8 minutes. Well, kind of yes. But I usually run 1usmus at the stock 100% for 20-25 cycles and then Anta777 Absolut or Extreme1 for longer as that already has much longer cycle times.


----------



## TMavica

i use anta777 extreme , 5 cycles


----------



## Taraquin

angushades said:


> SPECS
> View attachment 2540731
> 
> I'm running 4X8 GB sticks not 2X16GB
> VDIMM 1.50 in bios but gives it about 0.20 extra so it's 1.520 in windows
> SOC 1.050
> CLDO 0.900
> VDDG 0.900
> VDDG IOD 1.050
> Everything else is default


Is this errorfree? I would suggest setting soc a bit higher. Check aida latency, if it's above 55ns try soc 1.08v, that might work. You can also try rfc at 264 or 256, wtrl at 10, 9 or 8 might also work.


----------



## Reaxer

Reaxer said:


> Okay! I got GDM off to post! 60/20/20/24 and 40/20/20/24 seem to work. BUT the RTT's still cause it not to boot, 6/3/4 and 7/3/3 both fail to post, tried procODT 30 and 36.9 with both.
> Could someone point me in the right direction to get better RTT's or should I just use the one's my mobo autosets?
> 
> EDIT. 40/20/24/24 and 40/20/30/30 also post fine, RTT's were the problem then.











So, 6/3/4 boots fine at 3200 MT/s. @3600 6/3/4 doesn't boot, but 7/3/3 boots fine. @3800, both don't boot, 7/3/1 boots though, but i'm not sure if that's better than 0/3/1.



















































So this worked fine, but had an error 0 the second hour or something. Next day, cold boot, it wouldn't boot at all. So I tried again to get 3800 to boot consistently

It looks like CPU VDDP -0.020 and Termination voltage -0.020 both are needed for a consistent boot, not that sure yet.
I also figured out that 24/20/20/20 boots and tests just fine on 2T, interesting, so I let that test overnight. This time I got a fan and put it over the sticks, it shaved off about 8-10 degrees and turning of the RGB also made about 2-3 degrees difference.










Then I woke up to this today.
The errors came after more than ~1.5 hour.
Voltages are all higher cause I wanted to rule them out of the boot issues.

I've tested RttNom 7 and CkeDrvStr for half an hour this morning, that tested fine, but yea not sure if that's the fix.

Do you guys have any suggestions?

PS. I'm trying to get flat 14 stable, but I get error 6's pretty fast, suggestions for that?
Lower ProcODT's also work fine now, should I use a different one?

EDIT.
Hmmm 6/2/4 does boot and looks to be working fine. I've also been playing with getting CL13 stable, Looks to need a bit more than 1.6 Volts.
My IMC doesn't seem to like tRCDRD 14, looks like I need to keep that at 15 then 🤷‍♀️








This seems to be pretty stable, [email protected]% gives me this temperature, maybe that helped stability?


----------



## TheBoy08

Taraquin said:


> remember that WR should be RTP x 2 so you should use 12 WR, that will work better. If you could do 2T you could do 5 RTP, but that is impossible with gear down mode.


|








I gave it another shot because I thought it was weird how I couldn't run 2T GDM disable with flat 15, look what it can post with now.... I went auto on secondaries and tertiaries to avoid not being able to post and it worked! 
I'll slowly input back timings and test to see what was conflicting, so far 232 RFC worked


----------



## msmeenge

Is there a specific value you need to set your tRFC at? I see loads of people put in a certain value.
Any sum or something u have to apply on deciding your tRFC value? And how imporant is it to change ur tRFC2/tRFC4 values or do you leave these on auto?


----------



## Audioboxer

Out of sheer boredom for things to tinker with I bought myself one of those flow meters. I know they aren't very accurate but they're still aesthetically pleasing. Will mean another loop drain lol.

I think the 3D cache chips might be getting announced this week, so we'll see what price/release date is and what "promises" AMD make this time around FCLK. If there is no improvement on the FCLK front and just a performance uplift on benches/cache, I think I'll just skip them and plan a change to DDR5/Intel in 2023.

Unless AMD sort their BIOS/software side of things out the OCer in me wants to go back to Intel. Hopefully revisions to come this year or next will lead to less power hungry Intel chips. They're sort of brute forcing performance a bit right now, IMO. It's working, but they've got to get more efficient. AMD has mastered efficiency in terms of power usage. But this ride with the way AMD treats memory/their BIOS has been a bit of a disaster, IMO.


----------



## Reaxer

This seems promising
















I lowered the IMC voltages (no performance difference) and tightened it mostly all up. Also used a more silent speed on the ram fan
tRAS and tRC -2 gives errors 0/1 and 11. tRCDRD -1 gives error 6

I'm gonna let this test overnight and see if it's stable 

EDIT. CPU is stock here


----------



## TheBoy08

I just changed tRP and tRAS and got 1 error at the very end of the test


----------



## Audioboxer

Reaxer said:


> This seems promising
> View attachment 2540873
> 
> View attachment 2540874
> 
> I lowered the IMC voltages (no performance difference) and tightened it mostly all up. Also used a more silent speed on the ram fan
> tRAS and tRC -2 gives errors 0/1 and 11. tRCDRD -1 gives error 6
> 
> I'm gonna let this test overnight and see if it's stable
> 
> EDIT. CPU is stock here


1.62v wouldn't be too bad a return for tCL13. 

And yeah an error 6 on tRCDRD is pretty much RIP


----------



## Imprezzion

In what way does a 2 DIMM board improve RAM OC in general. Like, does it only allow for higher frequencies, lower voltages or does it actually affect the timings that can be ran stable. 

I really wanna swap my B550-XE for either a B550 Unify-X or a X570S Unify-X if it ever becomes actually available in the Netherlands but I am afraid my bad bin will just hold me back and it won't actually allow for any better memory clocks.

Right now I'm at 3733 C15 @ 1.55v and while C14 is possible on this 4 DIMM board it needs a lot of voltage (1.62-1.63 ish) and won't train tPHYRDL in any way. On Intel I used to run this kit at 4200 15-17-17 @ 1.63v and/or 4400 17-17-17 @ 1.51v neither of which are exactly great. 

My new from RMA second 5900X will show up tomorrow and I wanna throw my board with that chip and some cheap 16GB 3600C16-18-18 RAM on the used market and get one of the above boards from that cash. And a Corsair 7000D Airflow + a 360 Nemesis GTX to improve my loop a bit.


----------



## Taraquin

Imprezzion said:


> In what way does a 2 DIMM board improve RAM OC in general. Like, does it only allow for higher frequencies, lower voltages or does it actually affect the timings that can be ran stable.
> 
> I really wanna swap my B550-XE for either a B550 Unify-X or a X570S Unify-X if it ever becomes actually available in the Netherlands but I am afraid my bad bin will just hold me back and it won't actually allow for any better memory clocks.
> 
> Right now I'm at 3733 C15 @ 1.55v and while C14 is possible on this 4 DIMM board it needs a lot of voltage (1.62-1.63 ish) and won't train tPHYRDL in any way. On Intel I used to run this kit at 4200 15-17-17 @ 1.63v and/or 4400 17-17-17 @ 1.51v neither of which are exactly great.
> 
> My new from RMA second 5900X will show up tomorrow and I wanna throw my board with that chip and some cheap 16GB 3600C16-18-18 RAM on the used market and get one of the above boards from that cash. And a Corsair 7000D Airflow + a 360 Nemesis GTX to improve my loop a bit.


In general you can achieve higher speeds with 2 dimm boards, typically 4600+ vs sub 4500 for most of the 4 dimm boards. For AMD the biggest gain on 2 dimm boards is that they seem much more likely to run infinity fabric WHEA 19 free above 3800/1900. The vast majority of people I have read of/talked to that can do 1933+ fclk WHEA 19 free have only 2 dimms and usually 5600X or 5800X. Quality of isn't nesessarily important since I have one of the cheapest B550 out there and it only has 2 dimms and I can run 2066 fclk WHEA 19 free.


----------



## tekokk

Audioboxer said:


> Out of sheer boredom for things to tinker with I bought myself one of those flow meters. I know they aren't very accurate but they're still aesthetically pleasing. Will mean another loop drain lol.
> 
> I think the 3D cache chips might be getting announced this week, so we'll see what price/release date is and what "promises" AMD make this time around FCLK. If there is no improvement on the FCLK front and just a performance uplift on benches/cache, I think I'll just skip them and plan a change to DDR5/Intel in 2023.
> 
> Unless AMD sort their BIOS/software side of things out the OCer in me wants to go back to Intel. Hopefully revisions to come this year or next will lead to less power hungry Intel chips. They're sort of brute forcing performance a bit right now, IMO. It's working, but they've got to get more efficient. AMD has mastered efficiency in terms of power usage. But this ride with the way AMD treats memory/their BIOS has been a bit of a disaster, IMO.


exactly how I feel. From 3D Cache -> FCLK > Intel tryharding > AMD being efficient in terms of power usage. Spot on mate.


----------



## Reaxer

Audioboxer said:


> 1.62v wouldn't be too bad a return for tCL13.
> 
> And yeah an error 6 on tRCDRD is pretty much RIP


Yeah I thought so, I need about 1.55v for CL14, so I thought 1.62v was pretty good for CL13 and would be fine for daily


----------



## Imprezzion

Taraquin said:


> In general you can achieve higher speeds with 2 dimm boards, typically 4600+ vs sub 4500 for most of the 4 dimm boards. For AMD the biggest gain on 2 dimm boards is that they seem much more likely to run infinity fabric WHEA 19 free above 3800/1900. The vast majority of people I have read of/talked to that can do 1933+ fclk WHEA 19 free have only 2 dimms and usually 5600X or 5800X. Quality of isn't nesessarily important since I have one of the cheapest B550 out there and it only has 2 dimms and I can run 2066 fclk WHEA 19 free.


For me, tbh, not worth having to completely drain and disassemble my entire build and loop just for the off chance of running that. I'll stick with my now properly working B550-XE then. No real complaints with the board anyway except it only has 2 M.2 slots but yeah. I could always slap in a PCI-E adapter if I ever buy a 3rd or just get a bigger one and replace the 512gb one. Case I have is fine but I'm a bit tired of it and it's modded and cut to heck to make it all fit and breathe properly lol.


----------



## hazium233

angushades said:


> SPECS
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2540731
> 
> 
> 
> I'm running 4X8 GB sticks not 2X16GB
> VDIMM 1.50 in bios but gives it about 0.20 extra so it's 1.520 in windows
> SOC 1.050
> CLDO 0.900
> VDDG 0.900
> VDDG IOD 1.050
> Everything else is default


I have 4 x 8 that I have been working with a little. They are A0 from G.Skill.

When I tried RTT 6-3-3 with 40-20-30-20 on CAD I had error free runs on the first boot. But then on cold post it gave me 235 errors in four loops of mt86 test 8 (random number test).

I mostly worked with 7-3-3 after that and went to 34.3 proc and 30-20-24-24 which seems to post more reliably and seemed to be error free on cold post.

I need 1.1250 for 4x8 at least at 3800C16 or else LinX gflops starts to drop, although 1.1125 is really close.

You could try the old RTT combos 7-3-1, 7-2-1, 6-3-1, 6-2-1 or vary park slightly. Since you have GTR, they should be A2 RGB pcb.


----------



## 67091

Got this stable last night on extreme test for 7.5 hours now I’m working on primary timings. Something like 15.15.16.15 . Any suggestions for I’m already at 1.52 volts. I’m actually very happy with it.


----------



## hazium233

When testing with y-cruncher, how much to the first few small data tests look at voltage settings for FCLK? Can you skip to the larger data sets for FCLK testing, or is CCD found in the more cache based tests?

...

I didn't do a lot until after the holiday, but I think I mostly got the "daily" type timings working with the mismatched 4 x 8. But there is one oddity that I have seen and it might be fringe instability.

When I was running Realbench benchmark, I noticed a couple times when transitioning from Image Editing to H.264 Video Encoding, it didn't change to all cores and continued running h.264 only on Core 0 instead of all core. hwinfo (and actually Firefox) were running the first time it did this.

Has anybody seen this program do this? I know it is pretty old now, and I actually only opened it because I wanted to run the stress since it has GPU and CPU load (passed that, no WHEA).

I don't know if I completely trust the turn arounds and DD timings. The board wants to train very high DD (6 and 9, ***). tWRWRDD 9 to 7 is like +1 glfop in LinX I think.

These settings were tested with Karhu 10k, 5k on cold post, y-cruncher 4 loops and the realbench stress. Slightly different termination was in TM5 1usmus and OCCT Large AVX 2 1 hr.


----------



## Taraquin

Imprezzion said:


> For me, tbh, not worth having to completely drain and disassemble my entire build and loop just for the off chance of running that. I'll stick with my now properly working B550-XE then. No real complaints with the board anyway except it only has 2 M.2 slots but yeah. I could always slap in a PCI-E adapter if I ever buy a 3rd or just get a bigger one and replace the 512gb one. Case I have is fine but I'm a bit tired of it and it's modded and cut to heck to make it all fit and breathe properly lol.


As I've showed earlier, going above 3800/1900 to 4000/2000 gives marginal boost at best and only in bandwithsensitive apps/games like SOTTR, dram calc test and the very theoretical aida64 boosting perf by about 2%, but you lose a bit of perf (2%) in linpack and a few other apps.


----------



## nikoli707

Hynix CJR
5900x - Asrock b550i pg - 2 x 16gb Gskill 3600 16-19-19-19-39-59 xmp(stock)

I tightened the timings below, running at 1.35v, it is totally stable like this.








As soon as i push 3666/1833, 3733/1866, 3800/1900, i get a ton of WHEA errors in hwinfo64. I can pass TM5 and Memtest, they dont spit out errors, gaming or OCCT spit out WHEA's, either a little or a lot. Even at 3800/[email protected] everything seems fine, no crashes, games fine. I have played with soc/vddp/vddgs, nothing will stop the WHEA's from coming in unless i back down to 3600/1800. I must be missing something unless i have a very bad 5900x.

I dont think it should make a difference, but its 200mhz, 10xScale, -15 curves across the board.


----------



## Imprezzion

nikoli707 said:


> Hynix CJR
> 5900x - Asrock b550i pg - 2 x 16gb Gskill 3600 16-19-19-19-39-59 xmp(stock)
> 
> I tightened the timings below, running at 1.35v, it is totally stable like this.
> View attachment 2540970
> 
> As soon as i push 3666/1833, 3733/1866, 3800/1900, i get a ton of WHEA errors in hwinfo64. I can pass TM5 and Memtest, they dont spit out errors, gaming or OCCT spit out WHEA's, either a little or a lot. Even at 3800/[email protected] everything seems fine, no crashes, games fine. I have played with soc/vddp/vddgs, nothing will stop the WHEA's from coming in unless i back down to 3600/1800. I must be missing something unless i have a very bad 5900x.
> 
> I dont think it should make a difference, but its 200mhz, 10xScale, -15 curves across the board.


Easy enough to test right. Disable PBO for a sec and test without just to be sure. Are they all 19's those WHEA's or another code?


----------



## Taraquin

nikoli707 said:


> Hynix CJR
> 5900x - Asrock b550i pg - 2 x 16gb Gskill 3600 16-19-19-19-39-59 xmp(stock)
> 
> I tightened the timings below, running at 1.35v, it is totally stable like this.
> View attachment 2540970
> 
> As soon as i push 3666/1833, 3733/1866, 3800/1900, i get a ton of WHEA errors in hwinfo64. I can pass TM5 and Memtest, they dont spit out errors, gaming or OCCT spit out WHEA's, either a little or a lot. Even at 3800/[email protected] everything seems fine, no crashes, games fine. I have played with soc/vddp/vddgs, nothing will stop the WHEA's from coming in unless i back down to 3600/1800. I must be missing something unless i have a very bad 5900x.
> 
> I dont think it should make a difference, but its 200mhz, 10xScale, -15 curves across the board.


What agesa are you on? I recommend 1.2.0.3b or c, if below that updating, might help WHEA. Looks very good for CJR. A few advices: rtp half of wr so 8, rfc might do a bit lower if you are lucky. Try 496 or 512 as they macth up better with dual rank (divideable by 16), maybe 480 or even 464 can work if you are lucky with binning  A few times setting ccd and vddp higher can resolve WHEA 19s if that is what you get? Check event viewer. If it's 18 it can be caused by too low volt on curve optimizer, but should be present at all fclks.


----------



## blodflekk

Safe daily voltages for soc/iod ? currently at 1.2 and 1.07 and still getting a lot of WHEAs in linpack xtreme. I am trying to get 1933 WHEA free.


----------



## Audioboxer

Reaxer said:


> Yeah I thought so, I need about 1.55v for CL14, so I thought 1.62v was pretty good for CL13 and would be fine for daily


From my testing around 1.66v is where the B-die ICs start to crap out, so if you can cool 1.62v then it should be absolutely fine for daily. TEAMGROUP even sell a 1.6v rated b-die kit so I've been told.



blodflekk said:


> Safe daily voltages for soc/iod ? currently at 1.2 and 1.07 and still getting a lot of WHEAs in linpack xtreme. I am trying to get 1933 WHEA free.


99.9999999999% sure you won't get it WHEA free, just the way it is for nearly every non-G AMD CPU variant above 1900 FCLK. Especially the higher powered chips like 5900x/5950x.


----------



## Reaxer

Audioboxer said:


> From my testing around 1.66v is where the B-die ICs start to crap out, so if you can cool 1.62v then it should be absolutely fine for daily. TEAMGROUP even sell a 1.6v rated b-die kit so I've been told.


Thanks! I found that kit https://pcpartpicker.com/product/Xv...8-gb-ddr4-4800-cl17-memory-f4-4800c17d-16gtrs .
1.62v seems to get about ~43.8 degrees at the hottest (EDIT. 1.56 seems to get about max 43.3, so not much difference). At what degree does B-die's IC's overheat?
Test tonight didn't turn out so well, I think I need a little more voltage. I tested that and some other things out but got all kinds of different errors. 36.9 gives me error 11 (overheating?), tCKE 1 gives me error 4(PCB crash) and some other ones, then I just went to sleep.
I'm testing a tiny bit looser CL14 1.56v now, it's been running for 1:15 hour now, just gonna let it finish the 25 cycle.

does 1.62v or more need different RTTs or CADbus? I'm a little confused on those and what exactly they do. I've tried reading up on them a little in this thread and also the hardwareluxx ryzen thread, but it didn't get much clearer haha


----------



## Audioboxer

Reaxer said:


> Thanks! I found that kit https://pcpartpicker.com/product/Xv...8-gb-ddr4-4800-cl17-memory-f4-4800c17d-16gtrs .
> 1.62v seems to get about ~43.8 degrees at the hottest. Test tonight didn't turn out so well, I think I need a little more voltage. I tested that and some other things out but got all kinds of different errors. 36.9 gives me error 11 (overheating?), tCKE 1 gives me error 4(PCB crash) and some other ones, then I just went to sleep.
> I'm testing a tiny bit looser CL14 1.56v now, it's been running for 1:15 hour now, just gonna let it finish the 25 cycle.
> 
> does 1.62v or more need different RTTs or CADbus? I'm a little confused on those and what exactly they do. I've tried reading up on them a little in this thread and also the hardwareluxx ryzen thread, but it didn't get much clearer haha


It can do, but I've found 6/3/3 can hold out to around 1.65v as long as nothing else is unstable. 6/3/4 or 6/3/5 might be worth testing though. I've found everything over 1.6v can begin to get tricky, it just depends is it worth it and can you make it stable.

I've got tCL13 stable at 1.55v, but that's just because of this stupidly expensive bin (4000 14-15-15-15 1.55v). My testing above 1.6v has mostly been about chasing the absolute lowest tRFC or for a while trying to stabilise tRCDRD 13. 

You'll probably find tCL14 just works easier. Might be able to drop to 1.5~1.55v.


----------



## Reaxer

Audioboxer said:


> It can do, but I've found 6/3/3 can hold out to around 1.65v as long as nothing else is unstable. 6/3/4 or 6/3/5 might be worth testing though. I've found everything over 1.6v can begin to get tricky, it just depends is it worth it and can you make it stable.
> 
> I've got tCL13 stable at 1.55v, but that's just because of this stupidly expensive bin (4000 14-15-15-15 1.55v). My testing above 1.6v has mostly been about chasing the absolute lowest tRFC or for a while trying to stabilise tRCDRD 13.
> 
> You'll probably find tCL14 just works easier. Might be able to drop to 1.5~1.55v.


Yeah 6/3/3 and 6/3/4 just don't boot on my kit. They did boot on my DR Rev E kit, but yeah. I can maybe try 6/3/5 yeah, thanks!
If this test completes fine, I'm just gonna stick with this stable baseline for a while, but I'm gonna try to get CL13 stable later 

1.56 seems to get about max 43.3 degree, so not that much difference from 1.62 which went to ~44. At what degree does B-die's IC's overheat?
Thanks for the help man!


----------



## Reaxer

Reaxer said:


> Yeah 6/3/3 and 6/3/4 just don't boot on my kit. They did boot on my DR Rev E kit, but yeah. I can maybe try 6/3/5 yeah, thanks!
> If this test completes fine, I'm just gonna stick with this stable baseline for a while, but I'm gonna try to get CL13 stable later
> 
> 1.56 seems to get about max 43.3 degree, so not that much difference from 1.62 which went to ~44. At what degree does B-die's IC's overheat?
> Thanks for the help man!


It is interesting that 2T works fine with ClkDrvStr 24 (CAD 24/20/20/24). 1T should maybe only need 56 AddrCmdSetup? I did try that before, but my ClkDrvStr was 40 then.









I think? these are the PCBs of the Corsair Vengeance RGB Pro, not exactly sure, but the design is a bit weird due to the RGB.








This is the picture from corsair itself (I did visually check my DIMMs and they look to be on the A2/B2 layout.
I'm wondering if the weird behaviour with the "standard" RTTs not booting and the low ClkDrvStr needed are due to a weird PCB design?


----------



## blodflekk

Audioboxer said:


> 99.9999999999% sure you won't get it WHEA free, just the way it is for nearly every non-G AMD CPU variant above 1900 FCLK. Especially the higher powered chips like 5900x/5950x.


So are you suggesting I give up on running 1933? Or just look for passing stability tests and ignoring WHEAs?


----------



## Reaxer

blodflekk said:


> So are you suggesting I give up on running 1933? Or just look for passing stability tests and ignoring WHEAs?


You could try running the WHEA suppressor and see if you get performance regression at 1933 (test with linpack or something, AIDA isn't a good test here).
But most likely you still do get performance regression and you should give up on 1933 :/. It is what it is, performance at 1900 or 1866 isn't that much different


----------



## blodflekk

I was running 1800 reasonably tight and then decided to see where I could go. Found 1933 to be the limit but have been passing linpack and occt mem. Have been testing with pbo off and mem at 3200 to make sure infinity fabric is the limiting factor for stability


----------



## Reaxer

blodflekk said:


> I was running 1800 reasonably tight and then decided to see where I could go. Found 1933 to be the limit but have been passing linpack and occt mem. Have been testing with pbo off and mem at 3200 to make sure infinity fabric is the limiting factor for stability


And is the linpack performance better at 1933 or 1900/1866?

EDIT. here's two tests about the performance regression
https://www.overclock.net/threads/o...memory-stability-thread.1628751/post-28918315








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


No difference on this 5600x between AUTO and manual tweaking with regards to VID Weird, turning on PBO in any shape or form nukes my max VID. Default seems to be working quite decent for me anyway, will just stay here for now. Want to test TM5 again to see if I still get timeouts.




www.overclock.net


----------



## Reaxer

Audioboxer said:


> It can do, but I've found 6/3/3 can hold out to around 1.65v as long as nothing else is unstable. 6/3/4 or 6/3/5 might be worth testing though. I've found everything over 1.6v can begin to get tricky, it just depends is it worth it and can you make it stable.
> 
> I've got tCL13 stable at 1.55v, but that's just because of this stupidly expensive bin (4000 14-15-15-15 1.55v). My testing above 1.6v has mostly been about chasing the absolute lowest tRFC or for a while trying to stabilise tRCDRD 13.
> 
> You'll probably find tCL14 just works easier. Might be able to drop to 1.5~1.55v.


So it's stable!


















I'm gonna do a overnight test, and another test after a cold boot, but I'm pretty happy with this.


----------



## Imprezzion

Reaxer said:


> So it's stable!
> View attachment 2541039
> 
> 
> View attachment 2541040
> 
> 
> I'm gonna do a overnight test, and another test after a cold boot, but I'm pretty happy with this.


I might be missing something here but why is the write in AIDA so slow and the read and copy aren't exactly good either for 3800. Latency is great but..

At much worse timings I see 60 read 58.5 write 57 copy at 55.x ns..


----------



## Frosted racquet

5600x and 5800x are single CCD/X CPUs that don't have the full memory address path that the dual CCD/X CPUs have which affects write performance in AIDA.


----------



## Sam_Oslo

Reaxer said:


> Interesting that they are only talking about a 5800X3D, is that the only 3D cache zen3 CPU coming soon?


Yeh, that's the only SKU with _3D_ V-Cache. And according to AMD's benching handouts, it's just enough to take the gaming crown from Intel 12900k. 
It seams to be a short time salutation. The real deal will be with the launch of AM5 in second half of 2022.


----------



## Frosted racquet

Sam_Oslo said:


> Yeh, that's the only SKU with _3D_ V-Cache.


For now


----------



## Sam_Oslo

Frosted racquet said:


> For now


People have asked AMD whether they’d be bringing more CPUs with _3D_ V-Cache, but they said this is the only one – for now. On the official presentation poster there was only one 5800X3D too.
Of course they can change their plan later, but they have no plans for other ones, for now. I don't think they will release another one, unless Intel can somehow push them, but that seams unlikely.

EDIT: You should take notice that AMD has revealed the whole plan for 2022, and there is only one 5800X3D with _3D_ V-Cache on it.


----------



## Imprezzion

For a pure dedicated gaming rig, if it is as fast as claimed, it would for me personally still warrant upgrading my 5900X to the 5800X3D. I don't see DDR5 getting any cheaper not for AM5 launch either. So, if the 5800X3D is a slot-in upgrade on current B550/X570 boards, why not. 

I would've liked to see a dual CCD 59xxX3D but yeah.


----------



## Sam_Oslo

Imprezzion said:


> I don't see DDR5 getting any cheaper not for AM5 launch either.


Thta's a good point. The DDR5 can create a big problem for a long time. But the chip-shortage and supply-chain problems are still expanding, it wouldn't be surprising to see shortage in other chips/components too, at least in USA and Europe.



Imprezzion said:


> I would've liked to see a dual CCD 59xxX3D but yeah.


That would be great, but AMD has the crunching-crown already and doesn't need to release a 59xxX3D. That would cannibalize AMD's own 59xxX, actually.
AMD is trying to take the gaming-crown from Intel 12900k and this 5800X3D seams to be just enough to mange it, unless Intel can make a new move and push AMD to counter it.


----------



## Imprezzion

Sam_Oslo said:


> Thta's a good point. The DDR5 can create a big problem for a long time. But the chip-shortage and supply-chain problems are still expanding, it wouldn't be surprising to see shortage in other chips/components too, at least in USA and Europe.
> 
> 
> That would be great, but AMD has the crunching-crown already and doesn't need to release a 59xxX3D. That would cannibalize AMD's own 59xxX, actually.
> AMD is trying to take the gaming-crown from Intel 12900k and this 5800X3D seams to be just enough to mange it, unless Intel can make a new move and push AMD to counter it.


True but when comparing 5800X vs 5900X for gaming, the gap is small but still there. It all depends on the launch price of the 5800X3D. If it is around the €400 mark, worth it for a 5800/5900X dedicated game rig owner. If it's €450 or more, probably not worth it. 

Back to memory, I'm still fighting with this dumb thing. I have a daily profile with 3733 15-15-8-13-25-40-240-1T GDM Off which is TM5 both 1usmus and anta stable for who knows how many hours by now. But, I wanna compare scores, scaling and performance between that and higher FCLK, 1900 does not boot, CPU has a FCLK hole there, so I have to do 1933 or 1966. The latter is impossible to get WHEA's under control somewhat, the former I can, with enough voltages on VDDG IOD, CCD and vSOC and running very high resistances. 

The problem is, on 3866 1933 1:1 the tPHYRDL will not in any way form or circumstances train straight with an *uneven* tCL. It is totally fine at 14 or 16 but 15 or 13 will not do 26/26 or even 28/28... I can leave the tRP and tRCD uneven just fine like 14-15-15, then it trains good. The biggest problem with this is that my DIMM's really really do not wanna run tCL 14 on 3866 lol.. I am trying to brute force it with vDIMM + relatively loose subtimings now but... Not much luck so far..

Why is it that at 3733 a uneven tCL is fine at 26/26 but at 3866 it's always 26/28 unless I use a even tCL.


----------



## nikoli707

Imprezzion said:


> Easy enough to test right. Disable PBO for a sec and test without just to be sure. Are they all 19's those WHEA's or another code?


it appears to be bus/interconnect errors


----------



## Audioboxer

lol, so much for the "We might see FCLK improvements with a chip refresh before Zen 4". What a bust.

Not going to be overly dramatic and say "My next rig is definitely intel", but if I change "gen" in early 2023 I'll see where both companies are. I'm not going anywhere again that has as much problems as AMD seem to have with memory controllers.

So Zen 4 better have none of this nonsense. USB devices failing to work, memory pretty much capped at 3800, etc.


----------



## Mach3.2

Audioboxer said:


> lol, so much for the "We might see FCLK improvements with a chip refresh before Zen 4". What a bust.
> 
> Not going to be overly dramatic and say "My next rig is definitely intel", but if I change "gen" in early 2023 I'll see where both companies are. I'm not going anywhere again that has as much problems as AMD seem to have with memory controllers.
> 
> So Zen 4 better have none of this nonsense. USB devices failing to work, memory pretty much capped at 3800, etc.


If Intel have decent offerings while still maintaining comparable prices with high end AMD parts, I'd say my next rig is probably gonna be Intel. But the next build is probably in 2024 for me.

But a positive point for AMD is that they didn't lock memory overclocking to only Z series board like Intel does.

With AMD you're pretty much paying for the number of cores you get with feature parity between SKUs whereas you can't exactly say the same for Intel SKUs.


----------



## Audioboxer

Mach3.2 said:


> If Intel have decent offerings, I'd say my next rig is gonna be Intel too. But the next build is probably in 2024 for me.


Just need intel to mature a bit on power consumption. Simply blasting 250w+ through a chip in order to squeak ahead of AMD in some benchmarks isn't impressive in isolation. It's great to see Intel recover from that awful last launch of _this generation_, but I'd like to see how they mature this year/early next.

Plus DDR5 is a total joke right now in pricing and performance. It needs to mature as well.

So I'm not in any rush either, I'm just moaning because I hyped myself up to think AMD were going to release a 5950x with 3D cache and that _might_ do something for FCLK. If they had I'd probably be thinking 2024 or heck, not even really planning anything for the foreseeable as end of the gen DDR4 has gotten pretty damn good. Some seriously fast bins.

When I do play games they're in 1440p Ultrawide, so I don't even care about 4K or anything yet. My performance in terms of FPS and so on will be good for years.


----------



## nikoli707

nikoli707 said:


> it appears to be bus/interconnect errors


1.2.0.3 Patch C is my agesa

Event Viewer shows all Event ID "20"


----------



## Sam_Oslo

Imprezzion said:


> True but when comparing 5800X vs 5900X for gaming, the gap is small but still there. It all depends on the launch price of the 5800X3D. If it is around the €400 mark, worth it for a 5800/5900X dedicated game rig owner. If it's €450 or more, probably not worth it.
> 
> Back to memory, I'm still fighting with this dumb thing. I have a daily profile with 3733 15-15-8-13-25-40-240-1T GDM Off which is TM5 both 1usmus and anta stable for who knows how many hours by now. But, I wanna compare scores, scaling and performance between that and higher FCLK, 1900 does not boot, CPU has a FCLK hole there, so I have to do 1933 or 1966. The latter is impossible to get WHEA's under control somewhat, the former I can, with enough voltages on VDDG IOD, CCD and vSOC and running very high resistances.
> 
> The problem is, on 3866 1933 1:1 the tPHYRDL will not in any way form or circumstances train straight with an *uneven* tCL. It is totally fine at 14 or 16 but 15 or 13 will not do 26/26 or even 28/28... I can leave the tRP and tRCD uneven just fine like 14-15-15, then it trains good. The biggest problem with this is that my DIMM's really really do not wanna run tCL 14 on 3866 lol.. I am trying to brute force it with vDIMM + relatively loose subtimings now but... Not much luck so far..
> 
> Why is it that at 3733 a uneven tCL is fine at 26/26 but at 3866 it's always 26/28 unless I use a even tCL.


In this round the fight is not about the top-dog CPU, but it's rather in the mid-range and gaming-crown. The mid-range has always been more about the price-war, so we can expect a very good price on 5800X3D and Intel's eventual counter-moves too. If Intel can keep the current trend of performance increase of 1200-series, we are going to see really good and cheap CPUs from both camps in 2022 and beyond, and this war will get really aggressive when AM5 hits the marked. 

I haven't seen similar FCLK/IMC issues and can't comment on them, mostely because AMD has manged to solve most of them in G-series. We can expect a better bug-fixes on 5800X3D and AM5 too, but we have to wait and see. I believe a good deal of these bugs are in BIOS and software. 

AMD has always been sloppy with BIOS and software, compered to Intel. If they want to keep this current hardware-advantages they need to work on the BIOS and Software.


----------



## Imprezzion

Sam_Oslo said:


> In this round the fight is not about the top-dog CPU, but it's rather in the mid-range and gaming-crown. The mid-range has always been more about the price-war, so we can expect a very good price on 5800X3D and Intel's eventual counter-moves too. If Intel can keep the current trend of performance increase of 1200-series, we are going to see really good and cheap CPUs from both camps in 2022 and beyond, and this war will get really aggressive when AM5 hits the marked.
> 
> I haven't seen similar FCLK/IMC issues and can't comment on them, mostely because AMD has manged to solve most of them in G-series. We can expect a better bug-fixes on 5800X3D and AM5 too, but we have to wait and see. I believe a good deal of these bugs are in BIOS and software.
> 
> AMD has always been sloppy with BIOS and software, compered to Intel. If they want to keep this current hardware-advantages they need to work on the BIOS and Software.


I have to be honest, as much as I hated my 10900KF for it's insane power draw and heat output, memory OC is so much easier on Z490/Z590.. Just yeet the vDIMM, set a high frequency (I mostly ran 4400 on these same DIMM's but at 17-17-17-36-340-2T), and let's go. And if it fails to train properly? No problem, at least on Intel you can manually setup the training parameters and apply offsets to force it to train.. 

But yeah, I decided to ignore the tPHYRDL mismatch as even with it at 26/28 performance is still way above 3733 in both bandwidth and latency so.. 
Now all I gotta do is fix this error #12 and check if I wanna run this high of a IOD / CCD + resistances 24/7. If I don't run them this high, any of them, it will WHEA like crazy in y-cruncher for example.

vDIMM = 1.5100, thanks ASUS for still not having vDIMM readout..


----------



## AYTOKPATOP

Hello to the honorable members of the forum.
I was ready to RMA my memory but...
The problem is with my 4 sticks of memory
F4-3600C16Q-64GTZNC. My system was stable before by just enabling XMP, Then my system start having instability issues like freeze in games and hard reset with no blue screen. I run memtest86 with all the sticks one by one with no error, but when I have 4 dimms populated I had error in test 7 after few pass.
I tried disable XMP but the problem with 4 dimms it's still there test 7!

My system is:
5900X
Aorus X570 Master
F4-3600C16Q-64GTZNC
Aorus 6800XT
PSU Corsair 1000W
Thank you for reading


----------



## Sam_Oslo

Imprezzion said:


> I have to be honest, as much as I hated my 10900KF for it's insane power draw and heat output, memory OC is so much easier on Z490/Z590..


Yeah, I have overclocked Intel-CPUs since the down of time.  This 5700Gis actually my first AMD overclocking attempt.
Intel has always been good with BIOS, and ASUS has always been best of the bunch for refining the BIOS on Intel platform too. But I hear that ASUS has never been good with refining the AMD-BIOS.


That ERROR 12 is usually a timeout issue. Somewhere something ends too quickly, or it's the lack of voltage and cells are not recharged in time of
a sync.
With other words, the first culprit is voltage somewhere or resistance somewhere


----------



## Sam_Oslo

Imprezzion said:


> Now all I gotta do is fix this error #12 and check if I wanna run this high of a IOD / CCD + resistances 24/7. If I don't run them this high, any of them, it will WHEA like crazy in y-cruncher for example.


We have actually the same sticks, and we have almost the same sub-timings too, with slightly difference in tRTP, tRDWR, tWRRD and such. I run these sticks at 4600c18 1.48v with the same sub-timing, but I have made a 4000Mhz-profile too, as below:









But of course you have to tweak the resistances (Rrt's , Str's and such) for 32GB, but our sub-timings are so close that it's worth seeing it.


These sticks are really scalable and I was so happy with them that I have bought the 32GB kit at Black-Friday too, but I didn't have time to install them yet. Will hopefully get to them soon.


----------



## Audioboxer

Sam_Oslo said:


> Yeah, I have overclocked Intel-CPUs since the down of time.  This 5700Gis actually my first AMD overclocking attempt.
> Intel has always been good with BIOS, and ASUS has always been best of the bunch for refining the BIOS on Intel platform too. But I hear that ASUS has never been good with refining the AMD-BIOS.
> 
> 
> That ERROR 12 is usually a timeout issue. Somewhere something ends too quickly, or it's the lack of voltage and cells are not recharged in time of
> a sync.
> With other words, the first culprit is voltage somewhere or resistance somewhere


Tbf AMD bios seem to be a total crapshoot across the board because AMD seem to have absolutely no idea what they are doing and cause ridiculous bugs with AGESA. Right now we seem to have a voltage bug tied to EDC. I'm not saying motherboard manufacturers haven't messed up as well, but lets be honest, if what AMD is serving you is garbage there is probably a higher chance you also make mistakes weeding through the AMD mess.

Even just the USB drop out nonsense and how AMD handled that was embarrassing. Some evidence to suggest it's not even properly fixed.

Many pro OCers and those who know what they're talking about, like Veii and others, have repeatedly implied AMD have no idea what they're doing when it comes to making fundamental changes with the BIOS and being hostile towards the end user. Locking things out, shutting things down and then making a mess of trying to fix how their CPUs interface with other components.

All of it is putting me off remaining with AMD, despite the fact they do still make good hardware and were there for the power user scene when Intel were getting high and releasing really poor CPUs on the hardware front. A good BIOS cannot make up for seriously underperforming CPUs.

It's why I personally never get too attached to brand loyalty, competition is good, especially when it means choice is there for when one hardware manufacturer is making a mess of their own products. Intel coming back strong this new gen is probably the best thing that could have happened, AMD seem to be getting complacent/arrogant. Even the 3D cache announcement was a bit of a mess, they might as well just have announced Zen 4 and told everyone to wait till the end of this year. 3D cache seems to be even more half-assed than the XT range of chips.

Then we have to hope Zen 4 isn't rushed.


----------



## Frosted racquet

Audioboxer said:


> Right now we seem to have a voltage bug tied to EDC.


What was the issue exactly, I forgot. Changing EDC limits voltage?


----------



## Imprezzion

Sam_Oslo said:


> We have actually the same sticks, and we have almost the same sub-timings too, with slightly difference in tRTP, tRDWR, tWRRD and such. I run these sticks at 4600c18 1.48v with the same sub-timing, but I have made a 4000Mhz-profile too, as below:
> 
> View attachment 2541104
> 
> 
> But of course you have to tweak the resistances (Rrt's , Str's and such) for 32GB, but our sub-timings are so close that it's worth seeing it.
> 
> 
> These sticks are really scalable and I was so happy with them that I have bought the 32GB kit at Black-Friday too, but I didn't have time to install them yet. Will hopefully get to them soon.


I have had these sticks since my 9900KS build when that released hehe. They have seen their fair share of abuse. 4400 17-17-17-36-320-2T was daily but I pushed it as high as 4533 17-19-19-38-340-2T @ 1.62v and they also did that just fine as long as I had the side panel open. Hot radiator air doesn't cool well lol.

They could boot at 4800C19 but never got it stable obviously. 

It is kinda weird how with this AMD they struggle so hard to do C14 or even 15 on 3866 when I could get away with 4200 15-17-17 @ 1.60v on Intel.

Oh well, I was only at 1.51v in that error pass so I guess I'll go to like 1.53v ish and check again.


----------



## Audioboxer

Frosted racquet said:


> What was the issue exactly, I forgot. Changing EDC limits voltage?


Going above 140 EDC introduced a voltage cap at 1.425v. It's not too big a deal for most multicore performance, but for the very light load workload boosts it'll stop you getting to 5.1+ghz. My 5950x has no issues hitting 5.125mhz on a few cores, but if voltage capped it struggles to go much beyond 5.025mhz.

It's maybe not a lot of performance past 1.425v, but Ryzen Master setting PBO values within Windows gets around the cap and for years now we've been told it's fine to hit 1.5v. Even by AMD. No reason to cap us now unless it's yet another AMD bios bug.

Motherboard manufacturers are pushing out 1.2.0.5 AGESA final BIOS with this behaviour. Someone has to find out if it's a bug or AMD just randomly deciding to attack OCers again for no reason. With proper cooling EDC can happily scale past 140. It even helps with CB23 MT for many of us.

I was running 270/168/220 on the last BIOS to crack 31300 on my 5950x. I know others who've managed above 31k a bit lower at like 190 EDC. Voltages above 1.425v probably aren't in play for this kind of MT action but the point is EDC is needed above 140 to get here so we're gimping our light workload boosts now. Unless we install Ryzen Master and change PBO values every Windows boot.

Getting sick of this kind of BIOS jank from AMD. Especially when there is no transparent patch notes to tell us they purposefully changed EDC and voltage behaviour. It's a guessing game and OCers left fighting amongst themselves to defend the change or speculate whether it's a bug or not.

The failed AGESA 1.2.0.4 that never seen the light of day officially capped VDDG voltages at 1.0v max for no reason. AMD engineers are either totally careless idiots or they have no idea what they're doing with their own BIOS rollouts. Continually breaking things or limiting the performance possibilities of their own hardware.


----------



## Imprezzion

Audioboxer said:


> Going above 140 EDC introduced a voltage cap at 1.425v. It's not too big a deal for most multicore performance, but for the very light load workload boosts it'll stop you getting to 5.1+ghz. My 5950x has no issues hitting 5.125mhz on a few cores, but if voltage capped it struggles to go much beyond 5.025mhz.
> 
> It's maybe not a lot of performance past 1.425v, but Ryzen Master setting PBO values within Windows gets around the cap and for years now we've been told it's fine to hit 1.5v. Even by AMD. No reason to cap us now unless it's yet another AMD bios bug.
> 
> Motherboard manufacturers are pushing out 1.2.0.5 AGESA final BIOS with this behaviour. Someone has to find out if it's a bug or AMD just randomly deciding to attack OCers again for no reason. With proper cooling EDC can happily scale past 140. It even helps with CB23 MT for many of us.


As you can see in my TM5 screenshot, my chip with CPPC and preferred cores disabled runs basically all cores at 4800-4875 at 170 EDC with 1.400 -1.450v. In light loads it does boost to 5Ghz on random cores which they can all handle fine but it does go up to 1.512v from time to time. This is with 1.2.0.3c. If 1.2.0.5 has the 1.425v cap there's no chance in heck I'll ever reach 5Ghz on the weaker cores lol. So, I hope the bug is fixed by then or I just won't upgrade the BIOS..


----------



## TimeDrapery

Imprezzion said:


> What is the benefit, or downside, of running RTT_nom at 6 or 7 compared to just disabled. My RAM really wants it disabled above 3600. Any other setting above disabled won't be anywhere near as stable above that.


Here's a good example

















🤦🤦‍♀️🤦‍♂️🤦‍♀️🤦, of course it errored two minutes after that

It looks like adding RttPark makes it want a little more VDIMM, 1.52V instead of 1.51V

I was wrong again









Once I work this out I'll likely drop tCL to 14, set tRFC to 272 / 202 / 124 and retest for stability... I expect not to have to exceed 1.55V but we'll see


----------



## mongoled

Reaxer said:


> So it's stable!
> View attachment 2541039
> 
> 
> View attachment 2541040
> 
> 
> I'm gonna do a overnight test, and another test after a cold boot, but I'm pretty happy with this.


A couple of things, how much memory is in use when you run your TM5 test ?

If your OS is not loaded with many running services/apps then this time is a little slow for the settings you are pushing.

If it is then the time it took to complete the 25 cycle is OK.

If your OS is loaded with apps/services then the first thing I would is set a static overclock of lets say 4.5Ghz and run a LinpackXtreme benchmark and note the score, I would then raise vSOC to 1.125v and do the same test again and compare the score, as long as the score is similar than your vSOC voltage is OK and its not the cause for the slow time.

Also, you should run some Y-Cruncher full batch of tests (did not check to see if you have done that) as TM5 alone is not enough to delcare you are stable.


----------



## Reaxer

mongoled said:


> A couple of things, how much memory is in use when you run your TM5 test ?
> 
> If your OS is not loaded with many running services/apps then this time is a little slow for the settings you are pushing.
> 
> If it is then the time it took to complete the 25 cycle is OK.


Thanks for the info!
This is the same screenshot again, but it was still running when I took the screenshot. ~1.9Gb x 16 is ~30.4 Gb Which I think is okay?
The 25th cycle wasn't yet finished here, but the slower speed could be explained by the stock CPU probably? The cooling for the CPU also isn't the best it got about ~66-68 degrees running only TM5. I remember that Prime95 on PBO made it hit 85+ I think? I wanted to improve the fan curve and add one intake and one exhaust fan.









And well **** haha (TM5 window is a bit bugged cause I started the test on remote desktop, which was setting the resolution to 1024x768 for some reason).








This was 10 cycles of 1000% 1usmusv3. Not sure exactly what I should be changing then, but I think the resistances 🤷‍♂️



mongoled said:


> If your OS is loaded with apps/services then the first thing I would is set a static overclock of lets say 4.5Ghz and run a LinpackXtreme benchmark and note the score, I would then raise vSOC to 1.125v and do the same test again and compare the score, as long as the score is similar than your vSOC voltage is OK and its not the cause for the slow time.
> 
> Also, you should run some Y-Cruncher full batch of tests (did not check to see if you have done that) as TM5 alone is not enough to delcare you are stable.


My OS is a bit old and bloated (I do have a lot of startup programs disabled while I am playing with the memory, but no services disabled and stuff).
I'm planing to do a fresh install of windows 11 when all the overclocking is locked in and W11 is a little more updated.

I'll try the Linpack and y-cruncher tests. I did some small benchmarks without a static overclock and there didn't seem to be a difference. But best to be sure. How exactly do I run the tests in y-cruncher, it's not in Benchmate right?



Imprezzion said:


> I might be missing something here but why is the write in AIDA so slow and the read and copy aren't exactly good either for 3800. Latency is great but..
> 
> At much worse timings I see 60 read 58.5 write 57 copy at 55.x ns..


When comparing with the Zen DDR4 OC leaderboard the scores seem about similar though?


----------



## mongoled

Reaxer said:


> Thanks for the info!
> This is the same screenshot again, but it was still running when I took the screenshot. ~1.9Gb x 16 is ~30.4 Gb Which I think is okay?
> The 25th cycle wasn't yet finished here, but the slower speed could be explained by the stock CPU probably? The cooling for the CPU also isn't the best it got about ~66-68 degrees running only TM5. I remember that Prime95 on PBO made it hit 85+ I think? I wanted to improve the fan curve and add one intake and one exhaust fan.
> View attachment 2541202
> 
> 
> And well **** haha (TM5 window is a bit bugged cause I started the test on remote desktop, which was setting the resolution to 1024x768 for some reason).
> View attachment 2541200
> 
> This was 10 cycles of 1000% 1usmusv3. Not sure exactly what I should be changing then, but I think the resistances 🤷‍♂️
> 
> 
> 
> My OS is a bit old and bloated (I do have a lot of startup programs disabled while I am playing with the memory, but no services disabled and stuff).
> I'm planing to do a fresh install of windows 11 when all the overclocking is locked in and W11 is a little more updated.
> 
> I'll try the Linpack and y-cruncher tests. I did some small benchmarks without a static overclock and there didn't seem to be a difference. But best to be sure. How exactly do I run the tests in y-cruncher, it's not in Benchmate right?
> 
> 
> When comparing with the Zen DDR4 OC leaderboard the scores seem about similar though?


From what you have written the time is OK



Regards LinpackXtreme, I advised running a fixed 4.5 Ghz clock and change vSOC just so you could compare the two results with 4.5Ghz and different vSOC, but seeing that the time you posted is "OK" there is no need to do this.

Regarding Y-Cruncher, just press

1 ----> Enter
7 ----> Enter
0 ----> Enter

That will run the full batch of tests for an infinite amount of time unless you stop it or it finds an error then will stop


----------



## Reaxer

mongoled said:


> From what you have written the time is OK
> 
> 
> 
> Regards LinpackXtreme, I advised running a fixed 4.5 Ghz clock and change vSOC just so you could compare the two results with 4.5Ghz and different vSOC, but seeing that the time you posted is "OK" there is no need to do this.
> 
> Regarding Y-Cruncher, just press
> 
> 1 ----> Enter
> 7 ----> Enter
> 0 ----> Enter
> 
> That will run the full batch of tests for an infinite amount of time unless you stop it or it finds an error then will stop


Sounds good! I probably will want to get the memory actually stable first

A bit unrelated but I tried some more RTT testing at 1.5V 3800 18-18-18 ProcODT 36.9 40/20/20/24
5/3/2, 6/3/2, 7/3/2, work fine
Any higher RttPark and they refuse to boot
5/2/4, 6/2/4, 7/2/4 all work fine
Any higher RttPark and they refuse to boot
6/1/6 and 7/1/6 boot,
7/1/7 and 6/1/7 don't boot.
7/1/2 and 7/2/1 boot fine, 7/1/1 and 6/1/1 don't boot.
I tried 60/20/40/20 and ProcODT's from 28.2-43.6 too, all boot fine on 7/1/6. Tested 28.2 and 43.6 with both CAD values and they don't boot on 7/1/7

It seems to me like on my kit RttWr and RttPark multiplied can't be more than 6 and less than 1? But maybe that's just my brain making a weird connection. 
EDIT4. 2*4 is not 6. and 6/2/4 boots fine. 

Do you guys have any suggestion what I should run? EDIT4. I'm thinking RttWr and Park 2/4 or 3/2. Or how I should test the "best" RTT's and "best" CAD and ProcODT values?

EDIT. I previously tested some too, so at 3200MT/s 6/3/4 post fine, and at 3600MT/s 6/3/3 and 7/3/3 post fine. So that's also interesting
EDIT2. Hmm on the Zen DDR4 OC Leaderboard Veii says
RZQ/5 on 1.68V+ VDIMM
RZQ/6 has a scaling near 1.58-1.65

Maybe it's different for DR, I could try 5/2/4 or or 5/3/2 at ~1.62 VDIMM. Or maybe 6/3/2
Now to find correct CAD en ProcODT values
EDIT3. so RZQ/6 has a scaling near 1.58-1.65 and I was using it at ~1.56 (but my mobo adds .1-.2 volts so debatable). But this could be one of the issues.


----------



## Veii

Sneak Peak, past work for the weeks of missing & having fun
Been some time. Missing this thread, just it's a lot ~ but i wanted to share


Spoiler: A0 B-Die [Maxed]

















Spoiler: A2 Rev.E Max



A2 Rev.E Max




























Spoiler: GK107 ~ by hand unlock




















GALAX GTX 650 VBIOS


1024 MB GDDR5, 1111 MHz GPU, 1500 MHz Memory




www.techpowerup.com
















Spoiler: AsusBiosScraper




















GitHub - hahagu/AsusBiosScraper: Brute force scans a URL range from Asus's bios database for potentially hidden bioses


Brute force scans a URL range from Asus's bios database for potentially hidden bioses - GitHub - hahagu/AsusBiosScraper: Brute force scans a URL range from Asus's bios database for potentia...




github.com










Spoiler: DDR4 XMP Editor and Flasher [not my project]












GitHub - integralfx/DDR4XMPEditor: Editor for DDR4 SPD and XMP


Editor for DDR4 SPD and XMP. Contribute to integralfx/DDR4XMPEditor development by creating an account on GitHub.




github.com
























Spoiler: Project Hydra Shenanigans & Overboost issue
























Spoiler: Other fun stuff



























^ worked on WHEA overboost bug, FCLK_EFF and LCLK are affected





Spoiler: More fun stuff




















Guys could have mentioned the source ~ eh it's fine 


Been surely away for a month, happy new year ! 
Back to being busy again~

Likely near mid-end of January we'll have more fun together
I try to hop on the SpringX3D wagon, but we will see how time turns
Oh also i need to find an APU to put Reous down from his APU throne 💜


----------



## Imprezzion

Is there a trick to make a Asus B550 boot with 1:2 FCLK? I set the option to 1:2 but it just hangs on 22 post code even at a very low memory clock and auto FCLK.. I must be missing something.. I wanted to run my old Intel clocks at 1:2 and compare those (4400 17-17-17) to 3733 15-15-15 with 1:1 but it ain't happy with it.


----------



## hazium233

Gee, what is wrong here:










I had 90 loops of LinX yesterday, and it had to do that in the last set of five, ha. I then ran TM5 1usmus 25c again afterwards.

I had thought maybe the Realbench problem with Image Editing and H.264 Video Editing could either be because I was greedy with too low vdimm (1.380) or maybe a misbehaving subtiming. When I first set vdimm up to 1.40, I also changed the _DD to Auto and motherboard set / trained tRDRDDD to 6 and tWRWRDD to 7. That had 381.3902 avg gflops, but made the transition from Image Editing to h.264 even worse, where Image stalled for a long time at the end.

On the next reboot though it switched _DD to 5 and 9 respectively. And it held that combo for a lot of boots as I varied VDDG IOD steps because I was interested to see if that might do anything. Looked from 1060 down through 960 mostly in 10's with LinX. Really the gflops didn't go completely to crap until 975, which was a little higher than the drop that I saw testing on the weekend. Realbench more reliably switched between the benches, but still had low Image score every once and a while.

But getting back to above, I had shut down and cleared CMOS to reload profile. I set CKE manually to 1, but _DD trained to above. But that first cold post had ~378 gflops on average. Reboot into above session and gflop up to above, which is 381.3075 avg.

I think wrong residual could be more related to resistances, but can also be subtimings maybe? Back to the drawing board, but maybe I just hit it with the vdimm hammer and see if it gets even worse.

The best average I have seen since the weekend is 381.8983, which is different than the numbers from linpack extreme for whatever reason (implemented differently, and extreme may even be broken). May have wasted my time looking at VDDG with linpack, but that is another story.


----------



## Audioboxer

Going to have a bit of fun uncoupled to "live the dream" of not being in AMD FCLK hell lol.

First thing I noticed quite quickly was while I can knock 4000 14-15-15-15 down to 14-14-14-14, tRDCRD 14 doesn't really stretch much higher than 4000, even with a 1.65v buffer.

Next step is just seeing what frequency I can get to within 1.65v with good primaries and then to top it off I might run a 25 cycle.


----------



## Veii

Audioboxer said:


> Going to have a bit of fun uncoupled to "live the dream" of not being in AMD FCLK hell lol.


Hardly noticeable, but maybe it was
cLDO_VDDP beyond 4400MT/s need to jump and move near 975-1020mV. 4200 was fine for me till 900mV
4600 needs it near 1040-1060
5000 near 1.08








Sadly ASRock get's messed up once you select 4967 or 5000 strap. it starts to add own timings and ignore everything.
Bugs out tCWL , soo you have to force it down, Bugs out IOL and it was more of a dream, than really stable. Soo didn't include

Can show that procODT is not needed , and cLDO_VDDP keeps scaling upwards.
4000 A0's had a hardlimit of 4600MT/s, they refuse to post anything else.
Also can show that tCKE is perfect upwards. Only DR have slightly missaligned ones.
Probably -1.
3600 = 6, 3800 = 8, 4600 = 16


----------



## Audioboxer

Veii said:


> Hardly noticeable, but maybe it was
> cLDO_VDDP beyond 4400MT/s need to jump and move near 975-1020mV. 4200 was fine for me till 900mV
> 4600 needs it near 1040-1060
> 5000 near 1.08
> View attachment 2541250
> 
> Sadly ASRock get's messed up once you select 4967 or 5000 strap. it starts to add own timings and ignore everything.
> Bugs out tCWL , soo you have to force it down, Bugs out IOL and it was more of a dream, than really stable. Soo didn't include
> 
> Can show that procODT is not needed , and cLDO_VDDP keeps scaling upwards.
> 4000 A0's had a hardlimit of 4600MT/s, they refuse to post anything else.
> Also can show that tCKE is perfect upwards. Only DR have slightly missaligned ones.
> Probably -1.
> 3600 = 6, 3800 = 8, 4600 = 16


Perfect timing! I've just spent the last 20 minutes or so tearing my hair out because I couldn't get anything past 4400 to boot LOL. Bootloop then MSI memory OCing failure message. I was loosening everything like a mad man and freaking out thinking 4400 must be the frequency limit for this memory (which would be disappointing considering GSKILL sell some 4800 bins ~ though they are SR I think).










This is as far as I got. 4400 seems to need 1.67~1.68v to have a chance at stabilising tCL14, but anything above 1.65v and I start to get IC crashing  Or whatever it is that causes crashes at full 32GB of memory.

Should it/could it be possible to use above 1.65v with full capacity Veii with the right settings?


----------



## Reaxer

Reaxer said:


> EDIT2. Hmm on the Zen DDR4 OC Leaderboard Veii says
> RZQ/5 on 1.68V+ VDIMM
> RZQ/6 has a scaling near 1.58-1.65


You could try that Audioboxer?


----------



## Veii

Audioboxer said:


> Perfect timing! I've just spent the last 20 minutes or so tearing my hair out because I couldn't get anything past 4400 to boot LOL. Bootloop then MSI memory OCing failure message. I was loosening everything like a mad man and freaking out thinking 4400 must be the frequency limit for this memory (which would be disappointing considering GSKILL sell some 4800 bins).
> 
> View attachment 2541252
> 
> 
> This is as far as I got. 4400 seems to need 1.67~1.68v to have a chance at stabilising tCL14, but anything above 1.65v and I start to get IC crashing  Or whatever it is that causes crashes at full 32GB of memory.
> 
> Should it/could it be possible to use above 1.65v with full capacity Veii with the right settings?


I had crashes near 1.58 with DR
Every kit is different, but once it's fine beyond 1.6 ~ up to 1.68 makes no issue
Just keep scalling +1 tRCD, + 1 tCL (and check tCWL) ~ for every 200MT/s

Then you don't have to touch voltage
But yes, very likely the issue is just cLDO_VDDP

Oh b-die didn't want to post on anything other than 30ohm,
tCKE change, no boot, tCWL change, no boot, tRDWR change (higher even), no boot
procODT or CAD_BUS change, no boot 
Mostly is cLDO_VDDP , whichyou have to push and then adapt with tCKE by the MCLK range. As cLDO_VDDP is only there for MCLK push


----------



## Audioboxer

Veii said:


> I had crashes near 1.58 with DR
> Every kit is different, but once it's fine beyond 1.6 ~ up to 1.68 makes no issue
> Just keep scalling +1 tRCD, + 1 tCL (and check tCWL) ~ for every 200MT/s
> 
> Then you don't have to touch voltage
> But yes, very likely the issue is just cLDO_VDDP
> 
> Oh b-die didn't want to post on anything other than 30ohm,
> tCKE change, no boot, tCWL change, no boot, tRDWR change (higher even), no boot
> procODT or CAD_BUS change, no boot
> Mostly is cLDO_VDDP , whichyou have to push and then adapt with tCKE by the MCLK range. As cLDO_VDDP is only there for MCLK push


Thanks, will crack on, this is fun even if it's depressing how big a latency hit there is for running out of sync. This flat 15 at 4400 is returning like 57.7ns. Thats awful.

Read/write/copy is great though lol. Read is over 68,000, write nearly 61,000 and copy 65,000.










Ran this twice, no time to run this profile like 10 times for an average. Onwards to 4600 hopefully.


----------



## Audioboxer

Damn, really struggling to go above 4400 @Veii even with your advice. The error code before bootloop begins is F9.

This is at 4466. Possible DR struggles to go higher? Could it be my CPU at this point? Or do I need to find some perfect set of BIOS settings to go from 4400 to 4466?


----------



## Imprezzion

Oof that latency hit.. my 10900KF @ 5.3 all core + 4.7 cache with mem at 4400 17-17-17 could get into the 35ns range. Painful.

I had some weirdness.. I got 1 single error last run I did, the error was a 12 I believe which is basically add voltage according to the sheet. So I did that, 1.510 --> 1.530, and now it has 19 errors.. like wut. What is so unhappy with that extra 200mv.. DIMM's never got above 33c even so it ain't temps. Had the heat off today as I wasn't home anyway for work so it's like 12c in my office.

Probably messed up something big in the RTT's or resistances but where to begin looking. That is always the hard part haha.


----------



## Audioboxer

Imprezzion said:


> Oof that latency hit.. my 10900KF @ 5.3 all core + 4.7 cache with mem at 4400 17-17-17 could get into the 35ns range. Painful.
> 
> I had some weirdness.. I got 1 single error last run I did, the error was a 12 I believe which is basically add voltage according to the sheet. So I did that, 1.510 --> 1.530, and now it has 19 errors.. like wut. What is so unhappy with that extra 200mv.. DIMM's never got above 33c even so it ain't temps. Had the heat off today as I wasn't home anyway for work so it's like 12c in my office.
> 
> Probably messed up something big in the RTT's or resistances but where to begin looking. That is always the hard part haha.


Yeah this past week has basically been me on a rager declaring I'm going Intel and throwing my AMD CPU out a window 

It is a brutal latency hit, I'm going to guess I would need to be at RAM frequency of like 4800+ to even get back down to near 54ns which would bring me back in line with what is achieved at 3800 in sync. Around 53.7ns is as low as I tend to get things with my 5950x. Disable 1 CCD and it's 50.x.

So to be at 57.7ns is killer if we're talking games performance or something. Simply no point in running out of sync, even though the read/write/copy is nice. It's why I'd like to see the results for 4600~4800, but I simply can't find a way to boot over 4400 just now


----------



## domdtxdissar

I can see we have jumped back half a month in regards to async testing 
(and here)








4400MT/s is also the max for me and Proc 37/40 is needed.
Managed to train memory one time at 4466 but massively unstable. (4400 is rock solid)

In other news, i have 3 new 5950x's incoming next week, will report back how they behave.
(crossing fingers for atleast one is b2 stepping)


----------



## Audioboxer

domdtxdissar said:


> I can see we have jumped back half a month in regards to async testing
> View attachment 2541271
> 
> 4400MT/s is also the max for me and Proc 37/40 is needed.
> Managed to train memory one time at 4466 but massively unstable. (4400 is rock solid)
> 
> In other news, i have 3 other new 5950x's incoming next week, will report back how they behave.
> (crossing fingers for atleast one is b2 stepping)


Sorry, my head was likely somewhere else back then. Probably moaning about something else lol.

"Glad" to see clarification from you that your kit also craps out at 4400. Must just be SR that has a chance to go right up to 4800? Unless we're both unlucky? Or maybe it's the 5950x choking out.

Given some of the variation between me and you at 4400, I'd maybe point the finger at our 5950x? IMC struggling at the data rate?

Also, how come your VDIMM is missing on an MSI board in ZenTimings? Thought that was just ASUS lol. What voltage were you running at?


----------



## jcpq

Hello friends.
I bought the 32GB kit
F4-4000C16D-32GTRSA
As I come from Single Rank, I am in doubt in some timings in Dual Rank.
Could you give a help on the most suitable for Dual Rank..
Thanks


----------



## Imprezzion

I can't wait for 5800X3D but I do have some serious doubts whether the FCLK performance will be any better. And I'm also really curious to see whether a 5800X3D which has less core clock speeds even compared to a normal 5800X can use it's cache to make up the difference in gaming with the 5900/5950X or not. 

I fixed the 19 errors lol. I went down with vDIMM to 1.500 in stead of up and changed some stuff with the resistances and RTT's, no real logic behind it, just said "previous values didn't work, let's just grab something that is not that." So it was kinda random, but I'm at 1h now and cycle 11 and it hasn't errored yet.. 3866 15-15-15 1T GDM Off 1:1 IF.


----------



## Audioboxer

Imprezzion said:


> I can't wait for 5800X3D but I do have some serious doubts whether the FCLK performance will be any better. And I'm also really curious to see whether a 5800X3D which has less core clock speeds even compared to a normal 5800X can use it's cache to make up the difference in gaming with the 5900/5950X or not.
> 
> I fixed the 19 errors lol. I went down with vDIMM to 1.500 in stead of up and changed some stuff with the resistances and RTT's, no real logic behind it, just said "previous values didn't work, let's just grab something that is not that." So it was kinda random, but I'm at 1h now and cycle 11 and it hasn't errored yet.. 3866 15-15-15 1T GDM Off 1:1 IF.


5800X3D is a stupid shareholders cashgrab, expect absolutely nothing in regards to FCLK. It's simply "we need to sell something and keep our shareholders happy before Zen 4 launches". Kind of like the stupid XT launch, but maybe a bit better than those chips.

Zen 4 which I wouldn't be surprised if it got pushed to Jan/Feb next year.

I've only done some reading, but I fully expect a 5950x and maybe even a 5900x to handle the 5800X3D single core performance just fine. I could be wrong here though, I just rolled my eyes at the general announcement and left it there.


----------



## domdtxdissar

Audioboxer said:


> Sorry, my head was likely somewhere else back then. Probably moaning about something else lol.
> 
> "Glad" to see clarification from you that your kit also craps out at 4400. Must just be SR that has a chance to go right up to 4800? Unless we're both unlucky? Or maybe it's the 5950x choking out.
> 
> Given some of the variation between me and you at 4400, I'd maybe point the finger at our 5950x? IMC struggling at the data rate?
> 
> Also, how come your VDIMM is missing on an MSI board in ZenTimings? Thought that was just ASUS lol. What voltage were you running at?


Yeah seeing we both are stuck at 4400MT/s i would say we are experiencing some kind of MSI bios limitation on dualrank memory..

I also did some lengthy testing on Linpack Xtreme VS aida64 scaling above 1900flck for my system back then incase if you also missed that one 

Will be fun to see the results next week, with 4 different 5950x's above 1900..

_edit_
hmm i still have my old 2x8GB memory laying on the desk next to me.. Could maybe try them out 😇 need to change to 60mm noctua fans on the alseye ram cooler anyway..


----------



## hazium233

Everyone will be annoyed when 5800X3D has lower than Vermeer average FCLK.


----------



## Audioboxer

domdtxdissar said:


> Yeah seeing we both are stuck at 4400MT/s i would say we are experiencing some kind of MSI bios limitation on dualrank memory..
> 
> I also did some lengthy testing on Linpack Xtreme VS aida64 scaling above 1900flck for my system back then incase if you also missed that one
> 
> Will be fun to see the results next week, with 4 different 5950x's above 1900..
> 
> _edit_
> hmm i still have my old 2x8GB memory laying on the desk next to me.. Could maybe try them out 😇 need to change to 60mm noctua fans on the alseye ram cooler anyway..


I tend to avoid IF 1933+ benches as I get jealous  My dear 5950x simply cannot handle anything above 1900. If it were just performance regression I could at least play around with benching/stability testing, but the USB disconnecting causes total havoc for me.

It was interesting to see AGESA 1.2.0.5 fix my weird mouse pointer jerking I got when doing OCCT CPU/y-crucher, but absolutely no improvement on fixing USB disconnects.

Interesting thought on it possibly being an MSI BIOS issue with DR memory. I guess we should find out if anyone on an AMD system has ran DR higher than 4400!


----------



## Imprezzion

Fixed. I have to use quite high VDDG's to stop it from spitting WHEA's and some weird RTT / resistance combination to stop it from throwing a error 12 or 8 all the time but this is a very nice baseline for memory and IF. It's real hard on the CPU and the RAM to get 1T GDM Off at 3866 to properly work and be stable but it can be done. Weird values or not, if it works it works lel. 1.50v vDIMM btw. Now, save this in the BIOS as a baseline profile and go down the rabbit hole of changing the secondary timings... hehe.


----------



## Audioboxer

Seems if not chasing tCL14 there is absolutely no need to stay as high as 1.65v. Guess for fun I'll allow this to now do a 25 cycle and see what comes back.

Few things I have noticed, tWTRS 3 is simply out of the equation at this frequency. Runs at 3 at 3800, won't boot at 3 at 4400. SCL 2 & 3 boot, but seem they might not be stable. tRTP 5 and tWR 10 seem to be too tight. Doesn't appear as if any major changes are needed with the other voltages/resistances, other than me increasing RttNom to 6 per Veii advice.

And lastly, 1T/56 will boot, but it's very unstable. Buildzoid mentioned a few times once you go for high frequency with DDR4 you're best just to forget ever running it at 1T.


----------



## Luggage

Audioboxer said:


> I tend to avoid IF 1933+ benches as I get jealous  My dear 5950x simply cannot handle anything above 1900. If it were just performance regression I could at least play around with benching/stability testing, but the USB disconnecting causes total havoc for me.
> 
> It was interesting to see AGESA 1.2.0.5 fix my weird mouse pointer jerking I got when doing OCCT CPU/y-crucher, but absolutely no improvement on fixing USB disconnects.
> 
> Interesting thought on it possibly being an MSI BIOS issue with DR memory. I guess we should find out if anyone on an AMD system has ran DR higher than 4400!


Just a thought, have you tested if there is any difference between the cpu and the chipset USB ports?


----------



## Audioboxer

Luggage said:


> Just a thought, have you tested if there is any difference between the cpu and the chipset USB ports?


Biggest annoyance is the commander pro, it plugs into the motherboard USB connectors. As in the ones on the bottom of the mainboard.

When USB disconnects happen it causes the commander pro to reset all my fan profiles and sometimes it totally flips out and forces itself to do a firmware update before it works again.

But devices plugged into front case USB and back of the motherboard USB ports will disconnect/reconnect as well. It's basically all my USB sources that freak out.

Got another question I'll probably be slapped for asking in a memory OCing topic but what are the main benefits from running a higher frequency? As in, what does the read/write/copy help most? Obviously I hear latency is king, especially for gaming. Just speculating on when it can ever be of some benefit to consider running on AMD out of sync.


----------



## Luggage

Audioboxer said:


> Biggest annoyance is the commander pro, it plugs into the motherboard USB connectors. As in the ones on the bottom of the mainboard.
> 
> When USB disconnects happen it causes the commander pro to reset all my fan profiles and sometimes it totally flips out and forces itself to do a firmware update before it works again.
> 
> But devices plugged into front case USB and back of the motherboard USB ports will disconnect/reconnect as well. It's basically all my USB sources that freak out.
> 
> Got another question I'll probably be slapped for asking in a memory OCing topic but what are the main benefits from running a higher frequency? As in, what does the read/write/copy help most? Obviously I hear latency is king, especially for gaming. Just speculating on when it can ever be of some benefit to consider running on AMD out of sync.


Y-cruncher loves bandwidth - check competition thread.


----------



## domdtxdissar

Audioboxer said:


> It is a brutal latency hit, I'm going to guess I would need to be at RAM frequency of like 4800+ to even get back down to near 54ns which would bring me back in line with what is achieved at 3800 in sync. Around 53.7ns is as low as I tend to get things with my 5950x. Disable 1 CCD and it's 50.x.
> 
> So to be at 57.7ns is killer if we're talking games performance or something. Simply no point in running out of sync, even though the read/write/copy is nice. It's why I'd like to see the results for 4600~4800, but I simply can't find a way to boot over 4400 just now





domdtxdissar said:


> hmm i still have my old 2x8GB memory laying on the desk next to me.. Could maybe try them out 😇 need to change to 60mm noctua fans on the alseye ram cooler anyway..


Yeah this is 100% down to us running dualrank
Vdimm @ 1.6v
















Sadly i had a hard lockup at 4866 which nearly bricked my windows, and lost all the bios profiles for my 2x16sticks "#!¤%#&
Pretty sure i can go higher if i spend time finetuning voltages.

Also completed the ramcooler fan swap
















Will maybe try to play around alittle with these 2x8gb sticks before the new cpus show up...
New baseline settings thrown together in 1 min and pure T1 suddenly is child's play with single rank 😅


----------



## Imprezzion

@Audioboxer yeah I have never ran 1T on Intel above 4000 either. A few people in the Intel memory topic on 2 dimm Apex boards had 4400-4500 on 1T but not doable on my old Z490 Ace. I could also not run twr 10. 12 was fine up to 4533.

I kinda wanna try this setup I have now and only change to tCL 14 to get tPHYRDL to match. It doesn't right now. 26/28. Latency is mid 54's now. It will only ever match with a even tCL on 3866. Wanna see if I can get deep into the 53's with tCL 14 and matching tPHYRDL.


----------



## Audioboxer

domdtxdissar said:


> Yeah this is 100% down to us running dualrank
> Vdimm @ 1.6v
> View attachment 2541294
> 
> View attachment 2541295
> 
> 
> Sadly i had a hard lockup at 4866 which nearly bricked my windows, and lost all the bios profiles for my 2x16sticks "#!¤%#&
> Pretty sure i can go higher if i spend time finetuning voltages.
> 
> Also completed the ramcooler fan swap
> View attachment 2541297
> View attachment 2541298
> 
> 
> Will maybe try to play around alittle with these 2x8gb sticks before the new cpus show up...
> New baseline settings thrown together in 1 min and pure T1 suddenly is child's play with single rank 😅
> View attachment 2541299


Thanks for checking that, there is no better way to do it than swap other memory into your setup lol.

Also frick me, even at 4800 it's not enough to get the latency back down to in sync levels.

My question now is what causes this limitation? As in what part in the chain is failing or not capable of handling DR at such a data rate?

Something interesting I've also found is 1.6v is where I see tPHYRDL go to 28/32. Yes, 32 lol. TM5 was running OK but that's not acceptable. Up to 1.61v and it's 28/28 again.


----------



## domdtxdissar

Audioboxer said:


> Thanks for checking that, there is no better way to do it than swap other memory into your setup lol.
> 
> Also frick me, even at 4800 it's not enough to get the latency back down to in sync levels.
> 
> My question now is what causes this limitation? As in what part in the chain is failing or not capable of handling DR at such a data rate?
> 
> Something interesting I've also found is 1.6v is where I see tPHYRDL go to 28/32. Yes, 32 lol. TM5 was running OK but that's not acceptable. Up to 1.61v and it's 28/28 again.


I think bios optimization.. very few even try to run dualrank at these speeds. (we are just testing stuff for fun since we all know synced is best 90% of the time)


----------



## Audioboxer

domdtxdissar said:


> I think bios optimization.. very few even try to run dualrank at these speeds. (we are just testing stuff for fun since we all know synced is best 90% of the time)


Interesting if so. If it's down to the BIOS that would suggest it could be done.

I spoke to someone else and they struggle to get above 4200 on their DR kit, 4266 is their limit and that is hard to stabilise to even bench. That might just be the DR bin as well.

We've both got MSI boards, albeit it supposedly the best memory OCing boards out there. Would be interesting to get more input from people running ASUS and Gigabyte boards with DR.


----------



## Luggage

domdtxdissar said:


> Yeah this is 100% down to us running dualrank
> Vdimm @ 1.6v
> View attachment 2541294
> 
> View attachment 2541295
> 
> 
> Sadly i had a hard lockup at 4866 which nearly bricked my windows, and lost all the bios profiles for my 2x16sticks "#!¤%#&
> Pretty sure i can go higher if i spend time finetuning voltages.
> 
> Also completed the ramcooler fan swap
> View attachment 2541297
> View attachment 2541298
> 
> 
> Will maybe try to play around alittle with these 2x8gb sticks before the new cpus show up...
> New baseline settings thrown together in 1 min and pure T1 suddenly is child's play with single rank 😅
> View attachment 2541299


Save at least a stable version to usb stick. I,ve also found some hard locks clears rom saves on cmos with MSI :/


----------



## domdtxdissar

Audioboxer said:


> Interesting if so. If it's down to the BIOS that would suggest it could be done.
> 
> I spoke to someone else and they struggle to get above 4200 on their DR kit, 4266 is their limit and that is hard to stabilise to even bench. That might just be the DR bin as well.
> 
> We've both got MSI boards, albeit it supposedly the best memory OCing boards out there. Would be interesting to get more input from people running ASUS and Gigabyte boards with DR.


My ROG Crosshair VIII Hero stopped booting at 4066 MT/s max when running the exactly same dual rank memory. MSI Unify X Max can boot all the way up to 4400 MT/s

_edit_ typo


----------



## Audioboxer

domdtxdissar said:


> My ROG Crosshair VIII Hero stopped boosting at 4066 MT/s max when running the exactly same dual rank memory. MSI Unify X Max can boot all the way up to 4400 MT/s


Oooft, just goes to show you the benefit of the MSI boards when it comes to memory.


----------



## nikoli707

CJR 1.35v dram. This is the best i can do. Aida64 read/write/copy/latency 55,563/55,351/53,082/58.2ns.

I get WHEA's after 3666/1833/3733/1866/3800/1900. there is absolutely no voltage combination on the Dram/Soc/Vddp/Vddg's that will not spit out whea's, ive tried 0.025v increments across the board up to 1.45v Dram 1.20v Soc and 1.1v Iod 1.05v Ccd, 1.0v Vddp. Either my chip sucks or the board is funky. My only other thought is that there is some special Asrock setting that is playing with my voltages without me knowing. Tried with PBO disabled, ram at 2133 jdec confirmed in software, unpaired the fclk, still will spit whea errors anything past 1800flck. But it will pass memtest tm5 etc. and never any random restarts or bsod's.


----------



## Audioboxer

I can't even boot 2200 FCLK </3 lol.

But it's still cool to know what this bin could be doing in another timeline where memory OCing on AMD wasn't working out how it currently is.


----------



## 67091

This is my daily for now guys is there anything else I could change without going crazy on voltages. My system is very cool at the moment and id like to keep it like that.


----------



## Worldwin

Lowering TRCDWR to 14 from 15 manifested some errors. Anyone got any ideas?


----------



## Taraquin

Audioboxer said:


> Oooft, just goes to show you the benefit of the MSI boards when it comes to memory.


Isn't it party 2 dimm slots vs 4?


----------



## Taraquin

nikoli707 said:


> View attachment 2541351
> 
> CJR 1.35v dram. This is the best i can do. Aida64 read/write/copy/latency 55,563/55,351/53,082/58.2ns.
> 
> I get WHEA's after 3666/1833/3733/1866/3800/1900. there is absolutely no voltage combination on the Dram/Soc/Vddp/Vddg's that will not spit out whea's, ive tried 0.025v increments across the board up to 1.45v Dram 1.20v Soc and 1.1v Iod 1.05v Ccd, 1.0v Vddp. Either my chip sucks or the board is funky. My only other thought is that there is some special Asrock setting that is playing with my voltages without me knowing. Tried with PBO disabled, ram at 2133 jdec confirmed in software, unpaired the fclk, still will spit whea errors anything past 1800flck. But it will pass memtest tm5 etc. and never any random restarts or bsod's.


What bios you on? Agesa? WR should be double RTP, that will probably increase performance, 16-8, 14-7, 12-6 or 10-5, lowest stable is best.


----------



## Audioboxer

Audioboxer said:


> View attachment 2541337
> 
> 
> I can't even boot 2200 FCLK </3 lol.
> 
> But it's still cool to know what this bin could be doing in another timeline where memory OCing on AMD wasn't working out how it currently is.












Forgot to post this, into 56.x which I guess on paper isn't too bad for DDR4. It's only frustrating when you know you're capable of 53.x if you run in sync at 3800.

Given the impact latency can have on your 1% FPS lows if you play games, it's understandable why latency is simply king. I think if DR memory could get pushed higher, up to the likes of 4800, this bin with its propensity to enjoy low primaries might just be able to squeak out 54.x. At that stage it could be worthwhile running out of sync, overall.

But something causes a hard-wall at 4400, and this is likely just the end of the road. In terms of pushing latency a tiny bit lower, nothing else left on the bone really. tCL14 wants 1.67~1.68v and I really struggle to stabilise such a high VDIMM at 32GB. tRFC is incredibly challenging the closer you get to 110ns, the voltage need skyrockets and again you meet the same fate as tCL14, trying to stabilise really high VDIMM at 32GB.

I've gone flat 15 so I might be able to drop tRCDWR and tRP still, but IIRC they're more likely to contribute to read/write/copy than latency. If I've got time I'll try it.

1T is just out of the equation, boots, but is as unstable as it gets.

Fun... over 👨‍⚖️


----------



## jcpq

Hey guys.
A dual rank help.
For a dual rank kit, what are the best values for:
tRDWR; tCKE; RttNom; RttWr; RttPark and ClkDrvStr; AddCmdDrvStr; CsOdtDrvStr; CkeDrvStr.
Thanks.


----------



## blodflekk

What settings are you using for SOC loadline and switching frequency ? I took those settings from the Dram calculator. A good idea? Or best left on auto ?


----------



## umea

Audioboxer said:


> Spoiler
> 
> 
> 
> 
> View attachment 2541385
> 
> 
> Forgot to post this, into 56.x which I guess on paper isn't too bad for DDR4. It's only frustrating when you know you're capable of 53.x if you run in sync at 3800.
> 
> Given the impact latency can have on your 1% FPS lows if you play games, it's understandable why latency is simply king. I think if DR memory could get pushed higher, up to the likes of 4800, this bin with its propensity to enjoy low primaries might just be able to squeak out 54.x. At that stage it could be worthwhile running out of sync, overall.
> 
> But something causes a hard-wall at 4400, and this is likely just the end of the road. In terms of pushing latency a tiny bit lower, nothing else left on the bone really. tCL14 wants 1.67~1.68v and I really struggle to stabilise such a high VDIMM at 32GB. tRFC is incredibly challenging the closer you get to 110ns, the voltage need skyrockets and again you meet the same fate as tCL14, trying to stabilise really high VDIMM at 32GB.
> 
> I've gone flat 15 so I might be able to drop tRCDWR and tRP still, but IIRC they're more likely to contribute to read/write/copy than latency. If I've got time I'll try it.
> 
> 1T is just out of the equation, boots, but is as unstable as it gets.
> 
> Fun... over 👨‍⚖️


God what a beauty of a kit, haven't been around much but great work as always. I wonder what my kit can do unsynced, and although there's a penatly I wonder if there's an actual increase in FPS at all or if descynced adds not only a latency penalty but also an FPS one.


----------



## Audioboxer

Audioboxer said:


> View attachment 2541337
> 
> 
> I can't even boot 2200 FCLK </3 lol.
> 
> But it's still cool to know what this bin could be doing in another timeline where memory OCing on AMD wasn't working out how it currently is.


As a follow up here is a good illustration of the potential capability of b-die, but where it falls short itself due to voltage limitations.

So, tCL14, I knew it required around 1.68v, how? Well, 1.62~1.64v result in BSOD in Windows, self-explanatory. 1.65v~1.66v produced error 0 in TM5. Error 0 if it happens quickly and you're pushing tCL is a lack of VDIMM. Noticed this with tCL13 at 3800. 1.54v, can get error 0. 1.55v, no error 0s. 1.67v produced an error 0 a little later than 1.65v~1.66v, but it still happened within cycle 1.










Enter, 1.68v. Now, the above might look horrendous, but notice no errors on 0.










Enter, maxmem, 9GB. 3 minutes might not seem like a lot, but it's still 3 cycles of 9GB. If tCL was unstable it would still produce error 0s, they happen quickly. Potentially ALL those errors at 32GB are caused by the ICs losing their **** due to 1.68v at 32GB.

Here we find the crossroad between what the memory _could_ be capable of timing wise, and where it just seems impossible to stabilise a b-die kit at full capacity. 32GB at 1.68v just seems impossible. Or at least I have nowhere near the level of expertise to try and somehow stabilise such a high VDIMM at 32GB. It may well be impossible, I don't know, would need someone with far more expertise with b-die, let alone DR (an area that seems lacking, most pro-OCers understandably buy SR) to make a definitive statement on where b-die simply cannot go in regards to VDIMM.

IMO, it seems the cut off is about 1.65v before your full 32GB starts to cry, and even then my testing seems to show 1.64v might be a safer bet.


----------



## Imprezzion

Well, tCL 14 on my 15 stable profile with 1.56v vDIMM still gave an error at 36 minutes. I don't wanna go higher in vDIMM with temperatures and the benefit of just tCL 14 vs 15 is almost immeasurable. Latency is maybe 0.3ns lower but bandwidth is exactly the same and it ain't worth that much more vDIMM as 15 is fine at 1.50v. 

I'll just stick to straight 15's and tweak some of the secondaries.

How low of a tRAS + tRC + tRFC do you guys think I should go on 1.50v?


----------



## Audioboxer

So is this how you bench with y-cruncher and is this supposed to be a representation of memory or CPU? Or both? Someone earlier said a high frequency on memory is something y-cruncher likes compared to most things like gaming preferring latency.

And VDIMM should be 1.62v above, I just frequently forget when setting VDIMM with this MSI bios you need to deduct -0.01v for the real number lol. So I set 1.62v in BIOS and it reads 1.63v in Windows 

I guess final question is if the above is mostly about memory is 62.623 good? Keeping in mind I don't have a bench OS up and running, above is just my normal Windows.

*Edit* - was kindly sent a link to this topic so discussion prob move over there Punish it with y-cruncher

*Edit2* - Above compared to my 3800 profile










So yes, can confirm y-cruncher likes memory bandwidth!


----------



## Mach3.2

Anyone played with the SPD editor Veii shared yesterday? I added my daily profile onto the blank XMP profile 2 slot but my MSI board only seem to show profile 1.

I remembered the Patriot Viper Steel 4400MHz sticks correctly showing 2 distinctly different XMP profiles in the BIOS when I had them, so what gives?








_Modded SPD on the left, original SPD on the right_


Taiphoon Burner can read the modded SPD so I'm pretty sure the edited SPD was successfully flashed onto the RAM's SPD chip.


----------



## Audioboxer

Mach3.2 said:


> Anyone played with the SPD editor Veii shared yesterday? I added my daily profile onto the blank XMP profile 2 slot but my MSI board only seem to show profile 1.
> 
> I remembered the Patriot Viper Steel 4400MHz sticks correctly showing 2 distinctly different XMP profiles in the BIOS when I had them, so what gives?
> View attachment 2541430
> 
> _Modded SPD on the left, original SPD on the right_
> 
> 
> Taiphoon Burner can read the modded SPD so I'm pretty sure the edited SPD was successfully flashed onto the RAM's SPD chip.


My BIOS shows two profiles just now, they're just both the exact same. I guess I could use this tool to edit my daily profile onto slot 2!


----------



## KedarWolf

Audioboxer said:


> My BIOS shows two profiles just now, they're just both the exact same. I guess I could use this tool to edit my daily profile onto slot 2!


How do I get the .spd or .bin file for DDR4XMPEditor?


----------



## Audioboxer

KedarWolf said:


> How do I get the .spd or .bin file for DDR4XMPEditor?


Oh, I have no idea. I was just replying to the poster above saying they only have 1 profile in their BIOS.

I have two by default even though they are both the same lol.

I presume their BIOS probably had two as well until they tried to use the tool.


----------



## Mach3.2

KedarWolf said:


> How do I get the .spd or .bin file for DDR4XMPEditor?


In the github page, there's a link provided to download a zip file containing spd_checker(?) and spd_writer. Use the first executable to dump the SPD binary, which you edit using the DDR4XMPEditor, before writing the modded SPD binary dump using spd_writer. I used an elevated command prompt, not sure if a normal command prompt window will work.



Audioboxer said:


> Oh, I have no idea. I was just replying to the poster above saying they only have 1 profile in their BIOS.
> 
> I have two by default even though they are both the same lol.
> 
> I presume their BIOS probably had two as well until they tried to use the tool.


Ah I could have been clearer in my previous post; I could see both XMP profile 1 and 2 menu options in the BIOS, but both BIOS menu options are reading the same XMP profile 1(3600MHz profile) off the SPD chip, despite the RAM having a modded SPD with 2 XMP profiles.

Before the SPD mod, both BIOS menu options for XMP profile 1 and 2 were also showing the 3600MHz profile since there was only 1 XMP profile programmed by default for my Crucial kit.

If my memory didn't fail me, I remembered the BIOS menu options for profile 1 and 2 were correctly showing 4400MHz and 4233MHz profiles respectively for the Patriot Viper Steel 4400MHz kit I toyed with months ago.


----------



## Audioboxer

If I want to try and benchmark the difference between my 3800 in sync and 4400 out of sync for gaming performance how would I do this?

3D Mark? Like I want to see proper numbers, not just load a game and eyeball it lol.

The increase in bandwidth is quite a bit bigger than the cost of latency. Will be interesting to see the difference if I can find a good way to bench both profiles.

Also @domdtxdissar I managed to find a review of a DR kit rated for 4600 Neo Forza Faye DDR4-4600 2x 16GB Review Timings might be awful but it's still interesting to see reviewer couldn't go above 4400 on AMD either. Wonder if it's more a general AMD problem.


----------



## hazium233

Fixed _DD to 4 and 6, CKE 1, and rechecked termination:



Spoiler















TM5 25c and y-cruncher four loops with the top config



Spoiler










































But I started to take a look at dropping primaries, but I don't think this RTT is going to work for higher vdimm and 15's.

It was an awkward set with 16-15-15, and at 1.42 dimm TM5 went: 10, 1, 10, 13, 2, 13 over only 5 cycles, where first cycle had 10 and 1. So if RTT Nom is too weak I guess it could do early 10 and a couple 13. But I may also need better cooling, the middle dimm temps are not great.


----------



## Worldwin

Lowering TWR from 12->10 got 1 error in test 1. Any suggestions to get rid of this error?


----------



## domdtxdissar

Audioboxer said:


> If I want to try and benchmark the difference between my 3800 in sync and 4400 out of sync for gaming performance how would I do this?
> 
> 3D Mark? Like I want to see proper numbers, not just load a game and eyeball it lol.
> 
> The increase in bandwidth is quite a bit bigger than the cost of latency. Will be interesting to see the difference if I can find a good way to bench both profiles.
> 
> Also @domdtxdissar I managed to find a review of a DR kit rated for 4600 Neo Forza Faye DDR4-4600 2x 16GB Review Timings might be awful but it's still interesting to see reviewer couldn't go above 4400 on AMD either. Wonder if it's more a general AMD problem.


Use CPU game average in SotTR 1080p lowest to compare gaming performance








For me, async is alittle slower then my normal 1900:3800 CL13 settings, but the difference is not all that large..


----------



## Taraquin

Since 4000cl16 only gave me a slight benefit in aida, dram calc, SOTTR and a few other BW-loving games I decided to tune my 3800cl15 settings since the lower SOC and IOD-voltage gives me about 50MHz higher allcore speeds on CPU, yey! After upgrading to a D15 black cooler my ram disappeared, fortune of a 2-dimm MB is that it fits between the front fan of the cooler and sits in the ram clearance space of the cooler  I wonder how this affects the temp on the ram since dimm2 now gets partially in the way of one fan an air gets drawn from the second fan from the first dimm.


----------



## Audioboxer

Just a reminder for any new AGESA 1.2.0.5 recruits to check your curves. I knew my best cores were right on the edge for 1.2.0.3, as in, like 1~2 points ahead of where they were crashing in corecycler, and I've had to deduct a few points from each on 1.2.0.5.

Unstable cores can cause TM5 or even Karhu to fail, so when you update to 1.2.0.5 do a corecycler run.


----------



## Luggage

So this is very old news by now but the RIPJAWS V heatsinks are a joke 



http://imgur.com/a/nIK1es7


Half of the chips had half-chip contact with the thermal tape.

Installed the Barrow ram block, time to test temps...

Changed flow meter to HighFlow NeXT while messing with stuff.


----------



## Audioboxer

Luggage said:


> So this is very old news by now but the RIPJAWS V heatsinks are a joke
> 
> 
> 
> http://imgur.com/a/nIK1es7
> 
> 
> Half of the chips had half-chip contact with the thermal tape.
> 
> Installed the Barrow ram block, time to test temps...
> 
> Changed flow meter to HighFlow NeXT while messing with stuff.


Yes, they are terrible, should be using the Trident Z non RGB heatsinks. I mean, look at the price of my memory bin and these are the heatsinks they put on it lol....


----------



## Audioboxer

Audioboxer said:


> View attachment 2541337
> 
> 
> I can't even boot 2200 FCLK </3 lol.
> 
> But it's still cool to know what this bin could be doing in another timeline where memory OCing on AMD wasn't working out how it currently is.


Just noticed I made a mistake above, surprised no other eagle eyes clocked it. For a multiple of 16 tRFC should be set to 256 not 258. Not only that I have no idea what my tRFC2 and tRFC4 figures are about, they're wrong, even for 258.

Set to 256 and tPHYRDL loses its marbles. Instead of 28/28 it goes to 28/34. Yes, 34. Switching back to 258 changes it back to 28/28. A voltage bump doesn't help. Not that I have much voltage overhead to play with, struggles start at 1.65v for memory crashing at full capacity.

I guess this shows the above must be on the absolute edge of stability with tRFC. I know from past testing when you go under around 117-120ns the voltage needed skyrockets and then you meet the problem of not being able to run at full capacity.

Guess I'll need to go to 272 and retest the profile. Which should be absolutely fine because it's an increase in tRFC, but still, no cutting corners, I'll test it anyway.


----------



## Owterspace

I was playing around with some lower voltages, I didn't think it would last the night, but it did.


----------



## Reaxer

Owterspace said:


> I was playing around with some lower voltages, I didn't think it would last the night, but it did.
> 
> View attachment 2541596
> View attachment 2541596


That's nice  What's your VDIMM at?
Some timings look a bit weird though. tFAW should be able to be 16.
tWR should be able to do 12 with tRTP 6 maybe even 10 and 5
tCWL is uneven, which some mobo's find hard and also 4 lower than tCL
Your tRDRDSD ,DD and tWRWRSD and DD also look a bit weird, aren't they normally the same or SD one higher than DD?
Did your mobo train that tCKE? Veii's list would say that for SR it has to be 8 @3733
But hey it works 🤷‍♂️

For an overnight test do you guys prefer Anta777 extreme or his newer Absolut?


----------



## Owterspace

Reaxer said:


> That's nice  What's your VDIMM at?
> Some timings look a bit weird though. tFAW should be able to be 16.
> tWR should be able to do 12 with tRTP 6 maybe even 10 and 5
> tCWL is uneven, which some mobo's find hard and also 4 lower than tCL
> Your tRDRDSD ,DD and tWRWRSD and DD also look a bit weird, aren't they normally the same or SD one higher than DD?
> Did your mobo train that tCKE? Veii's list would say that for SR it has to be 8 @3733
> But hey it works 🤷‍♂️
> 
> For an overnight test do you guys prefer Anta777 extreme or his newer Absolut?


These are actually just the board defaults for 2133 lol.. I just changed the frequency. This board is not really made for memory tuning I think, I can tune as you say, but my results are not much better. It feels... "optimized". Like they want you to buy the nicer one.

Edit:

Whoops vdimm at 1.45v

Edit again:

I normally use the Extreme, but I am liking the Absolute..


----------



## Audioboxer

Audioboxer said:


> Just noticed I made a mistake above, surprised no other eagle eyes clocked it. For a multiple of 16 tRFC should be set to 256 not 258. Not only that I have no idea what my tRFC2 and tRFC4 figures are about, they're wrong, even for 258.
> 
> Set to 256 and tPHYRDL loses its marbles. Instead of 28/28 it goes to 28/34. Yes, 34. Switching back to 258 changes it back to 28/28. A voltage bump doesn't help. Not that I have much voltage overhead to play with, struggles start at 1.65v for memory crashing at full capacity.
> 
> I guess this shows the above must be on the absolute edge of stability with tRFC. I know from past testing when you go under around 117-120ns the voltage needed skyrockets and then you meet the problem of not being able to run at full capacity.
> 
> Guess I'll need to go to 272 and retest the profile. Which should be absolutely fine because it's an increase in tRFC, but still, no cutting corners, I'll test it anyway.


Okay, this is driving me nuts, since trying to change the tRFC to better follow some sort of pattern, whether it's multiples of 16, or Veii's newer calculator I'm now getting a single error on #1 during the first cycle.










Seems strange to me setting a tRFC of 258 could allow 25 cycles of TM5 to pass, but trying to change it to 256 first throws off tPHYRDL, but then using 272 ends up with a single error #1.

Can tRFC mask issues elsewhere depending on what value it uses? I guess I'll look at tRRDS/L and tWTRS/L in case 258 was somehow masking them having issues as tight as they are at 4400.


----------



## hazium233

What anta777 wrote was tRFC multiple of 8 for 8Gbit, or multiple 16 for 16Gbit chips. S8B being 8Gbit. 264?


----------



## Audioboxer

hazium233 said:


> What anta777 wrote was tRFC multiple of 8 for 8Gbit, or multiple 16 for 16Gbit chips. S8B being 8Gbit. 264?


Oops, that'll teach me for not paying attention, here I've been running around for months going on about "multiples of 16" as if it was that effectively because of 2x16GB rather than 2x8GB.

So it's based off the die density/count???


----------



## Sam_Oslo

hazium233 said:


> What anta777 wrote was tRFC multiple of 8 for 8Gbit, or multiple 16 for 16Gbit chips. S8B being 8Gbit. 264?


That can't be the issue, because both 256 and 272 are both multiplier of 16(and 8). Both of them follows both rules and should be OK, especially when 258 is passing 25 cycles.


----------



## Audioboxer

Sam_Oslo said:


> That can't be the issue, because both 256 and 272 are both multiplier of 16(and 8). Both of them follows both rules and should be OK, especially when 258 is passing 25 cycles.


Possibly not but I still needed to be corrected. Any time I've been playing with tRFC I've been adding 16 on or deducting 16. This means there has been values in-between, aka adding or reducing by 8 I've missed out on.

I'll do some more testing shortly, either way 256 was causing tPHYRDL to train at 28/34. Trying 264 will hopefully fix that and I'll see if I clear errors on 1.


----------



## Audioboxer

Seems to be holding up fine at 264. It's 28/28 and no error 1s on two cycles so far. It might just be training issues at 4400? I'll have a look at that MBIST setting I think it's called that Veii mentioned once. Takes BIOS longer to boot or something but can help training accuracy.

ProcODT 36.9 for example won't even boot. Things are that sketchy up at 4400.

I likely won't daily 4400 anyway, 3800 still beats it with latency. Maybe if any games end up being bandwidth monsters due to the DDR5 generation I'll give this a revisit. Most for now especially below 4K tend to prefer latency.


----------



## hazium233

Audioboxer said:


> Oops, that'll teach me for not paying attention, here I've been running around for months going on about "multiples of 16" as if it was that effectively because of 2x16GB rather than 2x8GB.
> 
> So it's based off the die density/count???
> 
> View attachment 2541605


I think so. It was min stable +8 though, IIRC, to cover for uncertainty with the internal refresh timing.


----------



## Audioboxer

hazium233 said:


> I think so. It was min stable +8 though, IIRC, to cover for uncertainty with the internal refresh timing.


It's working anyway










This will be tonights 25 cycle, as I've got work to do just now. Completed another 3 cycle before this just with change to tRFC, but on this one changed another few things

VDDP 0.9v -> 0.92v. It's entirely possible sticking to 0.9v here might be right on the edge and the first 25 cycle was a bit lucky. Veii made it clear going to frequencies like 4400+ are more likely to want more VDDP.

VDIMM 1.62v -> 1.63v. Like above, just wondering if this was right on the edge. 1.61v causes tPHYRDL issues and 1.6v spits out lots of 0s. Voltage headroom can go to about 1.64~1.65v before issues.

CkeDrvStr 30 -> 24. On my 3800 profile I went to 30 because a 50 cycle TM5 run had 1 error that suggested it could be related to powering down. This cleared it. Might not be needed here and/or detrimental.

Will see how it goes!


----------



## Audioboxer

Quick point of interest for where the voltage cut off points seem to be for dropping tRFC from 217 (224) at 1.55v. tRFC 216 likely needs around 1.58v. tRFC 208 likely needs around 1.62v.

tRFC 200 fails to complete a 3 cycle up to 1.65v.

As I mentioned before once you are under 120ns the voltage requirement really hits diminishing returns. A drop from 117ns to 109ns requiring a voltage increase from 1.55v to 1.62v will likely yield next to no performance improvement. Considering the rest of the timings are basically near bottomed out, not as if the VDIMM bump can aid with anything else.

I guess it's still a milestone to get under 110ns if the above can withstand a full cycle.


----------



## Imprezzion

I mean, I have Trident-Z Neo heatsinks and judging by the temps around 34-35c at 1.50v vDIMM with a 900 RPM 120mm blowing fresh air on them they aren't absolutely garbage. I have to have my case open for that tho. Closed side and blowing hot front intake radiator air doesn't do much good for temps and they sit in the low to mid 40's usually. So yeah, I not only have to test for general stability but also without the fan running and case closed to see if they can handle my set clocks and latencies at like 56c.. which we all know B-Die hates.

I used to use those Akasa / Arctic stick-on heatsinks back in the DDR 2/3 time. That worked quite well even tho DIMM's didn't really have temp sensors back then.


----------



## Veii

Luggage said:


> So this is very old news by now but the RIPJAWS V heatsinks are a joke


Good timing 








They are indeed a joke
Freezer and then hot air (hairdyer)

1.55v just checking functionality, RTT & heat (350RPM fan)







On clients build, with a CMDAF2
they still reach 48-52c @ 2500RPM
Here they held near low 50s
much better without this superglue, but dangerous ~ as i've seen now couple of people rip away the ICs


----------



## Imprezzion

Veii said:


> Good timing
> 
> 
> 
> 
> 
> 
> 
> 
> They are indeed a joke
> Freezer and then hot air (hairdyer)
> 
> 1.55v just checking functionality, RTT & heat (350RPM fan)
> View attachment 2541625
> 
> On clients build, with a CMDAF2
> they still reach 48-52c @ 2500RPM
> Here they held near low 50s
> much better without this superglue, but dangerous ~ as i've seen now couple of people rip away the ICs


Are there still those clamp on style heatsinks available for DDR4? I wonder what those would do with some high-end thermal pad like the GP Extreme for example.

Edit, yes Alphacool seems to have something along those lines.


----------



## Audioboxer

Imprezzion said:


> Are there still those clamp on style heatsinks available for DDR4? I wonder what those would do with some high-end thermal pad like the GP Extreme for example.


I'm using GP Extreme, seems to be good!



















Some benches for tRFC down at 208, no real difference at all.

Only thing I noticed from last time I did benching on this profile is increasing the SCLs from 2 to 4 does hurt latency a little, but as dom found out it produces a nice uplift in memory read/write/copy.

IIRC my membench with SCLs on 2 (ableit it ran in Windows 10 instead of 11) was like 95.

Next I need to grab Tomb Raider and do some 1080p FPS comparisons between 3800 and 4400 to see how small the latency performance hit is.

*edit* - Membench seems to like 4400 lol


----------



## Veii

Imprezzion said:


> Edit, yes Alphacool seems to have something along those lines.


Rather prefer barrow or byksi , as alphacools seem to be slightly too short
WIP and work in check to see if thermal putty is fine for dimms
It seems to boil for normal usage

Also checking if LM is fine ontop of putty


----------



## Audioboxer

+1 for Bykski, but I noticed after I had installed mine the Barrow version while it looks identical actually has fins. The Bykski doesn't. Fins should theoretically help cooling. My temps are great so it's fine and I guess fins = more restriction. I'm already running 4 rads and 3 waterblocks off 1 pump lol.

Also been doing a bit of testing this last hour and it seems all the funky tPHYRDL behaviour at 4400 comes exclusively from tRFC. I have no idea how 258 did 28/28 and a full 25 cycles. I can only guess the memory decided to "auto correct" the value. Didn't Anta suggest poorly set tRFC values might get automatically corrected or changed?

If I keep my tRFC a bit higher memory always trains at 28/28 at 4400. If I try and go low, like around 256/264 it rarely manages to train at 28/28. Guess this is just the cost of running at the absolute ceiling for your IMC/mobo/RAM in terms of DR frequency.

Pumping memory to 4400 is definitely fun for benchmark purposes, Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser 20439 for GB5.

Or under 60s in y-cruncher https://www.overclock.net/attachments/untitled-png.2541457/

Though y-cruncher required a static OC I shall not be doing again with that kind of voltage!

Just a shame about the latency penalty, but I'm getting more tempted to run this daily if it can pass Karhu tonight!


----------



## Veii

Audioboxer said:


> Just a shame about the latency penalty, but I'm getting more tempted to run this daily if it can pass Karhu tonight!


I think the target is near 4800+
i set 5000 as target as 4800 wasn't directly faster
4600 2:1 wasn't compared to 4200 2:1 , even with identical harsh timings at identical voltage

4800 likely, but it didn't want to run or even post on anything other than 30ohm procODT


----------



## Audioboxer

Veii said:


> I think the target is near 4800+
> i set 5000 as target as 4800 wasn't directly faster
> 4600 2:1 wasn't compared to 4200 2:1 , even with identical harsh timings at identical voltage
> 
> 4800 likely, but it didn't want to run or even post on anything other than 30ohm procODT


Dom has got near 4800 on his SR as well on the Unify MAX 2 DIMM. Just a shame DR can't seem to go higher. I posted in this topic last night that there is actually a 4600 rated DR kit Neo Forza Faye DDR4-4600 2x 16GB Review

Might be a cheaper brand name but what is interesting to see is the reviewer also couldn't post higher than 4400 on AMD. Meaning it's likely a BIOS or AMD CPU IMC limitation for DR???

I still haven't seen anyone online say they got DR to like 4600-4800. We need more DR experts 😜 Someone supply Veii with a stack of DR!


----------



## Luggage

Imprezzion said:


> Are there still those clamp on style heatsinks available for DDR4? I wonder what those would do with some high-end thermal pad like the GP Extreme for example.
> 
> Edit, yes Alphacool seems to have something along those lines.


My Barrow.


http://imgur.com/a/nY1CmU4


You can buy without the water block.
Just don’t use the same AliExpress shop I did if you feel like getting any before summer U_U


----------



## domdtxdissar

_edit_
nevermind, "checking functionality"


----------



## Veii

Audioboxer said:


> We need more DR experts 😜 Someone supply Veii with a stack of DR!


These ones are
But the annoying type 
Haven't gotten to them, best success was already running XMP without failure (4267 XMP ~ 4200 set)


----------



## Audioboxer

Veii said:


> These ones are
> But the annoying type
> Haven't gotten to them, best success was already running XMP without failure (4267 XMP ~ 4200 set)


Wait, you got DR booting at 4600~4800?! What CPU was it?


----------



## Owterspace

Reaxer said:


> Some timings look a bit weird though


You are right, I should have been in the 130s.. I thought that was a bit off.


----------



## Audioboxer

Just a heads up for anyone with money to burn, it seems like G.SKILL are saying the 4000C14 bins are pretty much going to go extinct. It's a post on Reddit from CS saying don't expect more 4000C14 as I presume everything will be shifting to DDR5.

I can already barely find the F4-4000C14D-32GVK let alone the other variants. SR seems to be in stock but DR seems like gold dust.

On the one hand maybe not a great time to spend a lot of money on DDR4, on the other hand who knows how long these shortages will go on for with DDR5.

That being said there are plenty of good DR bins that probably perform just as good as these 4000C14 due to FCLK issues with most Ryzen CPUs.

I bought mine from Amazon for 424 euros (I know....), but they haven't been in stock here for ages G.SKILL F4-4000C14D-32GVK Ripjaws V DDR4-4000MHz 1.55V 32GB: Amazon.de: Computer & Zubehör


----------



## Dziarson

Question for veryone what temp you have on B-die 2x16 in 1.7-1.8-1.9V i have still 35-38° sensor issue?


----------



## Veii

hazium233 said:


> The best average I have seen since the weekend is 381.8983, which is different than the numbers from linpack extreme for whatever reason (implemented differently, and extreme may even be broken). May have wasted my time looking at VDDG with linpack, but that is another story.


I *personally , still think that LinX will not show big improvements, even with FCLK jumps
As AVX2 doesn't seem to show any or micro improvements with FCLK or MEM-OC 

This was also for the GEMM test on sisandra
The inter core or inter latency named test, does show cache access differences , and L3 slightly shows them
But i don't think AVX2 accelerators will wiggle
Only if the sample package throttles, or therm throttles


----------



## Audioboxer

Dziarson said:


> Question for veryone what temp you have on B-die 2x16 in 1.7-1.8-1.9V i have still 35-38° sensor issue?


In use? High voltage on its own without a hard work out won't raise temps too much. Depends on your cooling as well. I was running up to 1.95v but above 1.7v I was using maxmem and I'm watercooled. Temps don't rise much for me regardless of VDIMM. Water temp has the biggest impact.


----------



## Veii

Audioboxer said:


> Wait, you got DR booting at 4600~4800?! What CPU was it?


Nono reread please
4200 works, i think higher works too 
(Untested as 4200 never run on them)
But anything other than 30ohm refuses to post
Well procODT shouldn't be increased for MCLK and cLDO_VDDP shouldn't be touched for FCLK or powering

Now VDDP should be touched for MCLK, but thats the only value
I think DR tCKE is fine, if you use the same scale just -1
But this likely needs rework with a good kit as baseline
Not one that trains over 1 minute 
I'll get to it, now thermals are better. 45c is workable with, without a heatsink
Might buy one for myself too from china (or couple, if this DR set ends up as useable ~ soo i'll sell it later)
But right now, there is a gold white custom loop to finish for last & this month

OptimusPC doesn't ship things soo i haven't gotten to buy other stuff from Barrow, Bitspower and Bykski



Audioboxer said:


> I can already barely find the F4-4000C14D-32GVK let alone the other variants. SR seems to be in stock but DR seems like gold dust


Right now have the TeamGroup OC10L lineup in my target
SR and DR
3600 14-15-15 is decent , but want to try one first
They market them as 10layer unbinned


----------



## Luggage

Audioboxer said:


> Just a heads up for anyone with money to burn, it seems like G.SKILL are saying the 4000C14 bins are pretty much going to go extinct. It's a post on Reddit from CS saying don't expect more 4000C14 as I presume everything will be shifting to DDR5.
> 
> I can already barely find the F4-4000C14D-32GVK let alone the other variants. SR seems to be in stock but DR seems like gold dust.
> 
> On the one hand maybe not a great time to spend a lot of money on DDR4, on the other hand who knows how long these shortages will go on for with DDR5.
> 
> That being said there are plenty of good DR bins that probably perform just as good as these 4000C14 due to FCLK issues with most Ryzen CPUs.
> 
> I bought mine from Amazon for 424 euros (I know....), but they haven't been in stock here for ages G.SKILL F4-4000C14D-32GVK Ripjaws V DDR4-4000MHz 1.55V 32GB: Amazon.de: Computer & Zubehör


The only shop you can order from here have no set delivery time and they are almost twice as much as I payed for the 3600c14-gvka - so yea, no... thx


----------



## Audioboxer

Veii said:


> Nono reread please
> 4200 works, i think higher works too
> (Untested as 4200 never run on them)
> But anything other than 30ohm refuses to post
> Well procODT shouldn't be increased for MCLK and cLDO_VDDP shouldn't be touched for FCLK or powering
> 
> Now VDDP should be touched for MCLK, but thats the only value
> I think DR tCKE is fine, if you use the same scale just -1
> But this likely needs rework with a good kit as baseline
> Not one that trains over 1 minute
> I'll get to it, now thermals are better. 45c is workable with, without a heatsink
> Might buy one for myself too from china (or couple, if this DR set ends up as useable ~ soo i'll sell it later)
> But right now, there is a gold white custom loop to finish for last & this month
> 
> OptimusPC doesn't ship things soo i haven't gotten to buy other stuff from Barrow, Bitspower and Bykski
> 
> 
> Right now have the TeamGroup OC10L lineup in my target
> SR and DR
> 3600 14-15-15 is decent , but want to try one first
> They market them as 10layer unbinned


Ah ok, I got confused.

Stay tuned, I might be able to send you my old 3200C14 DR kit if you're willing to pay postage (shouldn't be much for economy airmail). The friend I gave them to decided to watercool, began the process and then also decided to switch to a 4x8GB SR kit so a 4x waterblock can be used.... Don't ask lol.

Anyway, I think I'm getting this kit back. I would have considered just selling it but to make matters worse the idiot removed one of the heatsinks on the DR before deciding to bail on the project. So... that voids warranty on one stick lol.

If I get them back next week and if you want them for testing we can sort something out. Sacrificial DR kit, beat the hell out of them and see if anything can be learned!



Luggage said:


> The only shop you can order from here have no set delivery time and they are almost twice as much as I payed for the 3600c14-gvka - so yea, no... thx


Yeah it seems like the 400014 DR bins will just go extinct. Reddit CS post said expect 400016 to be the normal going forward. That's still a good bin.


----------



## Audioboxer

Audioboxer said:


> View attachment 2541337
> 
> 
> I can't even boot 2200 FCLK </3 lol.
> 
> But it's still cool to know what this bin could be doing in another timeline where memory OCing on AMD wasn't working out how it currently is.


Having a hell of a time replicating this after discovering my tRFC was junk










@Veii need a memory doctor in the house, I keep getting timeouts in TM5 like the above, randomly. Sometimes as early as cycle 9.

I've been playing around with a few settings to learn more. Firstly, ProcODT below 34.3 seems to mess up tPHYRDL. tRFC too low does the same. I wish I could remember on the 258 run if it was 28/28. I'm sure it was because I always check it, but running the correct figure of 256 produces like 28/34.

To try and combat timeouts I've increased VSOC from 1.15v to 1.175v. With droop 1.175v runs at about 1.15v real-time. The above run I tried tWTRL to 10 and tWRRD to 4. tRDWR to 9. VDIMM to 1.63v as well.

When I've had TM5 timeouts in the past it's usually been related to the CPU/PBO. All CPU overclocking is turned off just now. Gotta say what appears to be TM5 timeouts due to memory is somewhere I am struggling.

I am getting no errors in TM5, this is on about 5 runs now. It's always a timeout. Gotta say diagnosing things with an error is much easier than this 

@domdtxdissar did you do any stability testing at 4400 or just benching? IIRC you said to me many months ago you increased voltage across the board to fix a timeout, so I guess I should look at VDDP and VDDGs just in case. I suppose the CPU IMC might just be wheezing a bit dealing with memory at 4400!


----------



## domdtxdissar

Audioboxer said:


> @domdtxdissar did you do any stability testing at 4400 or just benching? IIRC you said to me many months ago you increased voltage across the board to fix a timeout, so I guess I should look at VDDP and VDDGs just in case. I suppose the CPU IMC might just be wheezing a bit dealing with memory at 4400!


Haven't done any stability testing at 4400, but everything seemed pretty fine.
If i remember correctly, increasing voltages from ~900/960/1040mv to 920/1000/1080mv fixed the timeouts problems for me, but every cpu is different as we know..


----------



## Veii

Audioboxer said:


> @Veii need a memory doctor in the house, I keep getting timeouts in TM5 like the above, randomly. Sometimes as early as cycle 9.


That's a windows 11 or chipset driver issue
We are investigating
Likely received OTA update, as i have this issue but only with 64gb

This is a core crashing, but why
You cant go back with AGESA


----------



## Audioboxer

Veii said:


> That's a windows 11 or chipset driver issue
> We are investigating
> Likely received OTA update, as i have this issue but only with 64gb
> 
> This is a core crashing, but why
> You cant go back with AGESA


You sure? I've had 3800 runs pass fine in Windows 11. In saying that, I've also had a 4400 run pass... once. lol.

I guess as long as I am not getting TM5 errors I'll stay positive. I guess I'll maybe run an OCCT mem test see what it fires out.

What do you mean I can't go back? I was actually considering going back to 1.2.0.3c to avoid the 1.425v cap without using Ryzen Master.

I'm on that Asus released chipset driver, 3.11 IIRC. I might roll that back to AMDs 3.10 or MSIs slightly newer 3.10 release.


----------



## hazium233

Owterspace said:


> You are right, I should have been in the 130s.. I thought that was a bit off.
> 
> View attachment 2541758
> 
> 
> View attachment 2541758


You don't have a fan directly on the dimms, right?

It is just TY143 on the Frost Commander and Noctua Industrials as the case fans?

Sadly I don't think the SW3 in front and the A15 on the cooler are enough to keep four dimms cool in my Mesh C.


----------



## jcpq

Here's what I got with my first 2x16Gb kit.


----------



## Audioboxer

jcpq said:


> Here's what I got with my first 2x16Gb kit.
> 
> View attachment 2541814
> View attachment 2541815


Try SCLs on 4 and see if your read gets a nice boost. Me and Dom have found that on DR. Usually with hardly any change to latency if any.


----------



## jcpq

Audioboxer said:


> Try SCLs on 4 and see if your read gets a nice boost. Me and Dom have found that on DR. Usually with hardly any change to latency if any.


Didn't know, I'll test it.


----------



## jcpq

Audioboxer said:


> Try SCLs on 4 and see if your read gets a nice boost. Me and Dom have found that on DR. Usually with hardly any change to latency if any.


Thank you friend, that's it.


----------



## Audioboxer

Never really used OCCT for memory before, but I guess even if it's not the best an hour of testing at 4400 and no issues scream at me. Maybe Veii is onto something with boost issues (timeouts) and TM5 with Windows 11/chipset drivers. Is it possible if you stress the IMC more they have more chance of cropping up?

OCCT doesn't seem to stress the CPU as heavy as TM5 during mem testing.

Going to now roll back from 3.11 to 3.10 and see how I get on. Only ASUS has released the 3.11 chipset drivers.


----------



## Audioboxer

-double post-


----------



## Veii

Audioboxer said:


> What do you mean I can't go back?


If something on the sample changed, for example acting differently to VDDG voltages, procODT and similar
Then that change is permanent
Usually also cores/CO being different or DPM behaving different. It depends

Asking hence 















This keeps happening on 22000.376
Soo the question was also , what chipset driver you run
But even 3.10.xxx.506 didn't resolve it
He has 2x32gb Hynix MJR , but there are zero orientation points
Does do the same issue on two identical spec'd system, with XMP without and even down to 3200 instead 3800MT/s


----------



## Audioboxer

Veii said:


> If something on the sample changed, for example acting differently to VDDG voltages, procODT and similar
> Then that change is permanent
> Usually also cores/CO being different or DPM behaving different. It depends
> 
> Asking hence
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This keeps happening on 22000.376
> Soo the question was also , what chipset driver you run
> But even 3.10.xxx.506 didn't resolve it
> He has 2x32gb Hynix MJR , but there are zero orientation points
> Does do the same issue on two identical spec'd system, with XMP without and even down to 3200 instead 3800MT/s


Gotcha. Yeah I'm on 22000.376. Most people will be, its the latest "stable".

I've returned to 3.10.22.706 from 3.11.17.521 so I'll see if that does anything at all.

Might even try setting a 4.5ghz all core clock or something, just to see if manually set cores changes anything. From what I've gathered the timeouts tend to happen at the end of a cycle, the memory goes back up for a refresh or whatever TM5 does, but then it's never reassigned for testing.


----------



## Veii

Audioboxer said:


> 3.10.22.706


that one is bugged too, this thread decided already it is
3.10.xxx.506


----------



## Comalive

I was running my system with a certain config (includung RAM OC) perfectly fine for many months, about 2 months ago I started getting regular booting failures again (they looked the same as when my RAM OC made issues during my tuning phase). Since I didn't change the settings, how come there are suddenly issues?


----------



## nick name

Audioboxer said:


> View attachment 2541823
> 
> 
> Never really used OCCT for memory before, but I guess even if it's not the best an hour of testing at 4400 and no issues scream at me. Maybe Veii is onto something with boost issues (timeouts) and TM5 with Windows 11/chipset drivers. Is it possible if you stress the IMC more they have more chance of cropping up?
> 
> OCCT doesn't seem to stress the CPU as heavy as TM5 during mem testing.
> 
> Going to now roll back from 3.11 to 3.10 and see how I get on. Only ASUS has released the 3.11 chipset drivers.


Damn, what cooling are you using?


----------



## nick name

Veii said:


> that one is bugged too, this thread decided already it is
> 3.10.xxx.506


That's the best one?


----------



## Audioboxer

nick name said:


> Damn, what cooling are you using?


I've got everything on a loop including the memory. 4 radiators so it stays pretty cool.

I used to think a 120mm fan would do the trick with memory, but once you watercool it there is no looking back. Still, it's probably the one component with the most diminishing returns from watercooling. 

But if you've got the space and the rads then a RAM block is really cheap. Just have to be happy voiding your warranty.


----------



## nick name

Audioboxer said:


> I've got everything on a loop including the memory. 4 radiators so it stays pretty cool.
> 
> I used to think a 120mm fan would do the trick with memory, but once you watercool it there is no looking back. Still, it's probably the one component with the most diminishing returns from watercooling.
> 
> But if you've got the space and the rads then a RAM block is really cheap. Just have to be happy voiding your warranty.


Oh, I didn't even look at the RAM temps. Your CPU temps are what blew me away.


----------



## Audioboxer

nick name said:


> Oh, I didn't even look at the RAM temps. Your CPU temps are what blew me away.


Oh right, lol, I think that's just because the OCCT ram test doesn't hit the CPU too hard. But at the same time the loop does tend to keep the CPU cool. Ambient is cool here as well just now with it being winter.

Ram temps aren't even listed above I don't think, so I should have clicked you meant CPU. Everything's in the same loop anyway, including RAM.


----------



## nick name

Audioboxer said:


> Oh right, lol, I think that's just because the OCCT ram test doesn't hit the CPU too hard. But at the same time the loop does tend to keep the CPU cool. Ambient is cool here as well just now with it being winter.
> 
> Ram temps aren't even listed above I don't think, so I should have clicked you meant CPU. Everything's in the same loop anyway, including RAM.


Ahhh, I've never used the RAM test in OCCT. I assumed it was the CPU test and didn't look at which test was actually run. 

What temps do you see running the CPU test?


----------



## Imprezzion

I wish my 5900X would run a bit cooler but yeah. Even with a 420 + 240 Nemesis GTX rad and a TechN block I still see CCD temps in the 70's with core temps in the high 60's in gaming. I am pushing the CPU quite hard tho. -25 all core PBO2 with +50 max clock at EDC 170 which equates to all-core boost in games around 4800-4875Mhz at 1.400-1.456v. 

In TM5 it's usually around the high 50's for the cores.


----------



## jcpq

nick name said:


> Ahhh, I've never used the RAM test in OCCT. I assumed it was the CPU test and didn't look at which test was actually run.
> 
> What temps do you see running the CPU test?


I always use it's more real life.


----------



## Owterspace

hazium233 said:


> You don't have a fan directly on the dimms, right?
> 
> It is just TY143 on the Frost Commander and Noctua Industrials as the case fans?
> 
> Sadly I don't think the SW3 in front and the A15 on the cooler are enough to keep four dimms cool in my Mesh C.


No sir, no fan on the dimms. Yes, I am running TY-143 and NF-F12 on the cooler, and two NF-A14s in the front of the case. I also have TL-C12 Pro at the front bottom position, and TL-D14X on the floor. No exhaust fans and no pci covers.. no filters or mesh either 

The top of the case is completely sealed and "noise damped".. I don't think it works because the computer is in the basement and when the fans are running full speed I can hear it upstairs in the main floor bathroom.. which is like 190 steps away lol..

Edit:

Just for fun! Not stable


----------



## Veii

Audioboxer said:


> Maybe Veii is onto something with boost issues (timeouts) and TM5 with Windows 11/chipset drivers. Is it possible if you stress the IMC more they have more chance of cropping up?


Soo that means I'd have to run a 200 cycle TM5 when the issue appears after 8-11 hours
I dont want to :'( but have no real holding point so far
Something is simply odd with 11 and TM5


----------



## Audioboxer

I decided to run a Hydra diagnostic test as something on 1.2.0.5 does impact boosting/old curves and this result is pretty lol.

So core 5 (how its named in BIOS) needs a positive curve? IIRC it's currently at like -5 in the bios, so it's always been one of the lower ones. Corecycler seems fine with this, so I'm interested to know how Hydra assumes it needs to be positive.

Still, I'll try these figures in Corecycler just to see what happens!


----------



## Luggage

Audioboxer said:


> View attachment 2541899
> 
> 
> I decided to run a Hydra diagnostic test as something on 1.2.0.5 does impact boosting/old curves and this result is pretty lol.
> 
> So core 5 (how its named in BIOS) needs a positive curve? IIRC it's currently at like -5 in the bios, so it's always been one of the lower ones. Corecycler seems fine with this, so I'm interested to know how Hydra assumes it needs to be positive.
> 
> Still, I'll try these figures in Corecycler just to see what happens!


More to the mystery, why is safe 1 and fast 2…


----------



## Audioboxer

Luggage said:


> More to the mystery, why is safe 1 and fast 2…


I could be wrong but my understanding is the impact of the curve is also felt by those core values around it. So if you get more aggressive with the cores around C06 it's possible that can change its proposed value.


----------



## Imprezzion

I'm going to enable CPPC and preferred cores again just to see if the stuttering is still there and to see how high my best cores can go lol. Currently I have them all capped at 5Ghz as my worst cores can't do above 5Ghz am without CPPC Windows 11 scheduler lets basically all my cores except 1 or 2 run the full 5Ghz. I tried 5050 but that gave me a nice page fault bsod in Corecycler so yeah.

I wonder if CPPC + preferred cores enabled vs disabled has any impact on WHEA's and the amount of them.


----------



## Reaxer

So I got this stable!
3800CL14 2T 34.3 6/2/4 24/20/20/24








Things I've noticed are that lower procODT sometimes have a hard time to boot, and normal CAD resistances like 40/20/20/24, 40/20/24/24 are not stable.
Also the first 2 tests I had tRP 12, tRAS 26, tRC 38 and tRDWR 9. they were stable for about ~15-20 cycles but then suddenly gave me unexpected kernel mode trap BSOD. I'm leaning towards tRDWR, has that happened to anyone before?



Spoiler: Bigger Screenshot 50 Cycle 1usmus














And after a coldboot (6-7 hours) it also remained stable 


Spoiler: 10 Cycle Anta Absolute












Looks like Anta Absolute is about ~2 degrees colder than 1usmus.





Spoiler: AIDA














This was all tested with PBO with curve on negative 15/30/30/23/30/30/30/30 and +75MHz. I got the safe values from Hydra and tested them with corecycler and occt core cycler. It sustained about 4.8GHz on TM5 and got me about ~16000 points in Cinebench R23.

One thing however is that I noticed while gaming the DRAM voltage goes a bit lower and higher than was seen while testing with TM5








The minimum was 1.524 here and max 1.572, while in TM5 testing it was min 1.536 and max 1.560.
Is this something I should look out for is it just the reading that's a bit wrong? And how would I be even able to test for this.

I'm not sure, but I think the DRAM voltage can actually go a bit lower. But next thing I'm gonna focus on is CL13!

EDIT. Ah Linpack also shows the same lower 1.524V, y-cruncher would probably do the same thing then. I still have to run y-cruncher test that mon told me about. First that then!


----------



## Audioboxer

Audioboxer said:


> View attachment 2541899
> 
> 
> I decided to run a Hydra diagnostic test as something on 1.2.0.5 does impact boosting/old curves and this result is pretty lol.
> 
> So core 5 (how its named in BIOS) needs a positive curve? IIRC it's currently at like -5 in the bios, so it's always been one of the lower ones. Corecycler seems fine with this, so I'm interested to know how Hydra assumes it needs to be positive.
> 
> Still, I'll try these figures in Corecycler just to see what happens!












Took Corecycler like half of one cycle to crash Hyrdra's fast figure










And medium....










Wooo, safe not failing right away.

Core 11 in the BIOS/Corecycler is Core 12 per Hydra's readouts (it doesn't start at 0). So that's a drop from -30 to -28 to -23. Testing above is skipping all weakest cores, I know if I hit the 4 fastest first it can be quick to produce errors in CoreCycler, rather than waiting 6 minutes a pop to cycle slower cores. My own curve testing on slower cores had most of them near or at -30.

I'm going to guess Hydra does some sort of testing to support it's SAFE column but MID and FAST are purely speculative???


----------



## Reaxer

Audioboxer said:


> I'm going to guess Hydra does some sort of testing to support it's SAFE column but MID and FAST are purely speculative???


Could be yeah, but I think corecycler is also the heaviest load (prime95), and not everyone wants to be that stable. MID and FAST would maybe be stable in all but the heaviest cpu loads


----------



## Audioboxer

Reaxer said:


> Could be yeah, but I think corecycler is also the heaviest load (prime95), and not everyone wants to be that stable. MID and FAST would maybe be stable in all but the heaviest cpu loads


On the contrary, the loads likely to get you a reboot with an unstable curve would be light loads. It's one of the minor challenges to core cycle testing apps. Corecycler isn't the heaviest Prime95 either, it's one of the lighter loads, on purpose, to try and cause Core boosting to go as high as possible under some sort of stress.

This is why desktop light loads can reboot people's PC's when they think their cores are stable. You get those micro jumps to like 5.05~5.15ghz and that causes a core to freak out that needs more voltage to hit said boosts. It's why many call "desktop stability" the real end game 

Another example of this is people who just set -25 or -30 all core and play a game for a few hours before jumping online to go "I'm stable at all core -30", and then a few days later they get a random reboot on their desktop.

Anyway, my current curve before running Hydra, updated for AGESA 1.2.0.5 was

-30 (0)
-30 (1)
-17 (2)
-30 (3)
-30 (4)
-5 (5)
-30 (6)
-28 (7)
-30 (8)
-30 (9)
-30 (10)
-22 (11)
-30 (12)
-30 (13)
-22 (14)
-30 (15)

Core 11 for me was at -22, so Hydra having it at -23 on the SAFE option is more like it.

The standout for me is I was running Core 5 at -5, Hydra has it at +1. Probably core 2 as well, I had it at -17, Hydra -6.


----------



## Reaxer

Audioboxer said:


> On the contrary, the loads likely to get you a reboot with an unstable curve would be light loads. It's one of the minor challenges to core cycle testing apps. Corecycler isn't the heaviest Prime95 either, it's one of the lighter loads, on purpose, to try and cause Core boosting to go as high as possible under some sort of stress.
> 
> This is why desktop light loads can reboot people's PC's when they think their cores are stable. You get those micro jumps to like 5.05~5.15ghz and that causes a core to freak out that needs more voltage to hit said boosts. It's why many call "desktop stability" the real end game
> 
> Another example of this is people who just set -25 or -30 all core and play a game for a few hours before jumping online to go "I'm stable at all core -30", and then a few days later they get a random reboot on their desktop.
> 
> Anyway, my current curve before running Hydra, updated for AGESA 1.2.0.5 was
> 
> -30 (0)
> -30 (1)
> -17 (2)
> -30 (3)
> -30 (4)
> -5 (5)
> -30 (6)
> -28 (7)
> -30 (8)
> -30 (9)
> -30 (10)
> -22 (11)
> -30 (12)
> -30 (13)
> -22 (14)
> -30 (15)
> 
> Core 11 for me was at -22, so Hydra having it at -23 on the SAFE option is more like it.
> 
> The standout for me is I was running Core 5 at -5, Hydra has it at +1. Probably core 2 as well, I had it at -17, Hydra -6.


Ah thanks for the info! That makes a bit more sense now. I've only tested with the safe values and even those were only stable with the llc I used with hydra (high on my gigabyte board), they weren't stable on auto llc


----------



## Audioboxer

Reaxer said:


> Ah thanks for the info! That makes a bit more sense now. I've only tested with the safe values and even those were only stable with the llc I used with hydra (high on my gigabyte board), they weren't stable on auto llc


No problem, it trips a few people up because the thought is obviously "heavy load testing!" when it comes to the idea of "undervolting". But due to the way Ryzen works and the boosting, it's the very light load boosting that can be the final hurdle lol. Which is why Corecycler does its best to put a load on 1 core at a time and try and get it boosting as high as possible. Usually if something is stable in Corecycler you're good to go, but even then, a boost on desktop might still cause you to need to lower a curve by like 1 point or something if you get a reboot and a kernel/WHEA error in event management.

Speaking of the curve, my own curve performs better than Hydra. Not bashing Hydra, for something that looks to automate the process it got quite close to what I already had. Although, some strange numbers on a few cores, notably 2 of my best, seem to be holding back performance.

Given that a lot of people like to cut corners and wouldn't put the time in to do the curve manually, I'd say it's decent for getting people to better performance than stock. Though I'd be wary of anyone using the MID or FAST profiles without more testing. SAFE only I'd say for plug n play.


----------



## Speed Potato

I don't know if this is the best thread for that but I just bought a 5900X with fabrication date 2141 and it was not B2 stepping, still B0.


----------



## TMavica

Some help pls! Thanks

my stable ram timing and passed test









After change the tRCDRD to 14, I got those error as below, any suggestions to fix that? Thanks. PS: DIMM: 1.5v


----------



## jvidia

TMavica said:


> Some help pls! Thanks
> 
> my stable ram timing and passed test
> View attachment 2541930
> 
> 
> After change the tRCDRD to 14, I got those error as below, any suggestions to fix that? Thanks. PS: DIMM: 1.5v
> View attachment 2541931


Stable at 1.2 vDimm ????


----------



## TMavica

jvidia said:


> Stable at 1.2 vDimm ????


no. this is 1.5v


----------



## jvidia

TMavica said:


> no. this is 1.5v


Ok.
So Zen Timmings print screen is wrong then....


----------



## TMavica

jvidia said:


> Ok.
> So Zen Timmings print screen is wrong then....












Looks ok after I changed the ProcODT to Auto (43.6), need run more cycles to ensure everythings is right


----------



## Audioboxer

TMavica said:


> no. this is 1.5v


Try reconfiguring your Rtts, they aren't great looking for 1T.

Alternatively switch back to 2T just now and see if tRCDRD 14 is ok there.

If you disable NOM it shifts to ProcODT IIRC. Issue with running ProcODT that high on a 5xxx is you might introduce issues elsewhere.

I guess if it works, it works, but try running 34.3-36.9 and 6/3/3 or 7/3/3 first.


----------



## TMavica

TMavica said:


> View attachment 2541935
> 
> 
> Looks ok after I changed the ProcODT to Auto (43.6), need run more cycles to ensure everythings is right


 re test again, got error 10 and 2 again


----------



## TMavica

Audioboxer said:


> Try reconfiguring your Rtts, they aren't great looking for 1T.
> 
> Alternatively switch back to 2T just now and see if tRCDRD 14 is ok there.
> 
> If you disable NOM it shifts to ProcODT IIRC. Issue with running ProcODT that high on a 5xxx is you might introduce issues elsewhere.
> 
> I guess if it works, it works, but try running 34.3-36.9 and 6/3/3 or 7/3/3 first.


ok. Tried 36.9 7/3/3 give me error 10 in 2 cycles. maybe need tried other combo too


----------



## Audioboxer

Ok @Veii definitely something weird going on with TM5 and timeouts.










This timed out for me 6 cycles into TM5, running along fine here on Karhu (properly testing tRFC 208 at 1.62v).

Last time I did a lot of TM5 testing was on an older version of Windows, back in November.

22000.376 was released on the 14 December 2021.

Second thing to consider, while this passed with no timeouts a couple of days ago https://www.overclock.net/attachments/screenshot-2022-01-06-012116-png.2541337/ it was ran without PBO enabled. Created its own BIOS profile for messing about with 4400 and never entered any curve or PBO values. I have however since tried with PBO alongside 4400 and have been having issues with timeouts.

So my speculating is possibly the newest version of Windows 11 coupled with using PBO is causing core crashes somehow? Maybe AGESA 1.2.0.5 changing things has also aggravated this timeout issue?

My next test tonight is the profile above, but instead of 1usmus v3 I'm going to try running Anta777 extreme for like 8 or 9 cycles overnight, see if it times out. I know tRFC can cause issues later in testing, but so far my TM5 timeouts have no consistency, some as early as 5~6 cycles, others at like cycle 19. All have happened when PBO has been enabled. All on AGESA 1.2.0.5 and Windows 11 22000.376.


----------



## Frosted racquet

Or maybe TM5 is buggy, simple as that. The timeouts are very random in my experience, happened with stock settings and across multiple machines. 1usmus config produces more frequent timeouts than Universal2


----------



## Audioboxer

Frosted racquet said:


> Or maybe TM5 is buggy, simple as that. The timeouts are very random in my experience, happened with stock settings and across multiple machines. 1usmus config produces more frequent timeouts than Universal2


Reluctant to say timeouts are just related to TM5 being buggy, as I've seen first hand how an unstable curve core can cause TM5 to timeout. At times when memory is on the very edge of stability you can get a timeout rather than an error, like with tRFC.

But sure if you have multiple stability apps in your arsenal you can always use another for peace of mind.

Telemetry is another variable thrown into the mix. Lot of people running it these days because it does work and leads to CPUs boosting higher and even remaining stable under stress testing. But it is entirely possible TM5 might not like it.

When I have PBO on, I have telemetry on.


----------



## Reaxer

mongoled said:


> Regarding Y-Cruncher, just press
> 
> 1 ----> Enter
> 7 ----> Enter
> 0 ----> Enter
> 
> That will run the full batch of tests for an infinite amount of time unless you stop it or it finds an error then will stop


Thanks! I ran that with these settings.


Reaxer said:


> So I got this stable!
> 3800CL14 2T 34.3 6/2/4 24/20/20/24
> View attachment 2541910
> 
> Things I've noticed are that lower procODT sometimes have a hard time to boot, and normal CAD resistances like 40/20/20/24, 40/20/24/24 are not stable.
> Also the first 2 tests I had tRP 12, tRAS 26, tRC 38 and tRDWR 9. they were stable for about ~15-20 cycles but then suddenly gave me unexpected kernel mode trap BSOD. I'm leaning towards tRDWR, has that happened to anyone before?
> 
> 
> 
> Spoiler: Bigger Screenshot 50 Cycle 1usmus
> 
> 
> 
> 
> View attachment 2541909
> 
> 
> 
> And after a coldboot (6-7 hours) it also remained stable
> 
> 
> Spoiler: 10 Cycle Anta Absolute
> 
> 
> 
> 
> View attachment 2541911
> 
> Looks like Anta Absolute is about ~2 degrees colder than 1usmus.
> 
> 
> 
> 
> 
> Spoiler: AIDA
> 
> 
> 
> 
> View attachment 2541912
> 
> 
> 
> This was all tested with PBO with curve on negative 15/30/30/23/30/30/30/30 and +75MHz. I got the safe values from Hydra and tested them with corecycler and occt core cycler. It sustained about 4.8GHz on TM5 and got me about ~16000 points in Cinebench R23.
> 
> One thing however is that I noticed while gaming the DRAM voltage goes a bit lower and higher than was seen while testing with TM5
> View attachment 2541913
> 
> The minimum was 1.524 here and max 1.572, while in testing it was min 1.536 and max 1.560.
> Is this something I should look out for is it just the reading that's a bit wrong? And how would I be even able to test for this.
> 
> I'm not sure, but I think the DRAM voltage can actually go a bit lower. But next thing I'm gonna focus on is CL13!
> 
> EDIT. Ah Linpack also shows the same lower 1.524V, y-cruncher would probably do the same thing then. I still have to run y-cruncher test that mon told me about. First that then!


And they did fine , Stable!


Spoiler: y-cruncher stress test ~110 min














My temps on the second test are a bit of an issue though, others ran at about ~80. 
EDIT. Ah yeah I should change the PPT, TDC and EDC values, I haven't really done that yet.

The voltages also dropped to the lower value of 1.524, but didn't increase to the 1.572.
I'm still not sure what I should do about that. Did anyone else have this problem before?


----------



## Veii

Audioboxer said:


> So core 5 (how its named in BIOS) needs a positive curve? IIRC it's currently at like -5 in the bios, so it's always been one of the lower ones. Corecycler seems fine with this, so I'm interested to know how Hydra assumes it needs to be positive.


Per CCD voltage balance - average of peak and minimum CO range, average of average as dLDO exists
Between CCD voltage balance , the same thing
Good cores can be allowed to take more , but bad cores are overvolted and request too high VID
Soo take away voltage that belongs to other cores. Same for good cores introducing too deep dips and can force straps to move down and take others in the same CCD with them.
A balance thing


Audioboxer said:


> I'm going to guess Hydra does some sort of testing to support it's SAFE column but MID and FAST are purely speculative???


Correct, based on CO to Freq straps
+25 fMax, = -2 CO on everything
or +50 fMax = +25 Hydra value


----------



## Reaxer

Was looking around the Tool 1007 Veii linked and got some interesting results 😂 -infinity!















HWinfo64 running was the problem
















Looks more like it.


----------



## Owterspace

Just messing around a little more with my 5600X...


----------



## Imprezzion

Speed Potato said:


> I don't know if this is the best thread for that but I just bought a 5900X with fabrication date 2141 and it was not B2 stepping, still B0.


Yeah you need 2143 or higher afaik for B2.
See photo. Mine's a B2.


----------



## 1s1mple

Owterspace said:


> Just messing around a little more with my 5600X...
> 
> View attachment 2541982
> View attachment 2541982
> 
> 
> View attachment 2541983
> View attachment 2541983
> 
> 
> View attachment 2541984
> View attachment 2541984
> 
> 
> View attachment 2541985
> View attachment 2541985
> 
> 
> View attachment 2541986
> View attachment 2541986


Whats your PBO2 settings?


----------



## PJVol

Audioboxer said:


> So core 5 (how its named in BIOS) needs a positive curve? IIRC it's currently at like -5 in the bios, so it's always been one of the lower ones. Corecycler seems fine with this, so I'm interested to know how Hydra assumes it needs to be positive


You may check two things.

Is Core5 driving the global frequency?
Is Core5 stable at that CO value in light MC/SC workloads (though this step is not always necessarily)
If 1st is true, there's no reason to increase it's value further.


----------



## KedarWolf

Reaxer said:


> Was looking around the Tool 1007 Veii linked and got some interesting results 😂 -infinity!
> View attachment 2541978
> View attachment 2541979
> 
> HWinfo64 running was the problem
> View attachment 2541980
> View attachment 2541981
> 
> 
> Looks more like it.


----------



## tekokk

Imprezzion said:


> Yeah you need 2143 or higher afaik for B2.
> See photo. Mine's a B2.
> View attachment 2541991


how can you check this?


----------



## KedarWolf

KedarWolf said:


>


This is Core Cycler and Y-Cruncher stable. Passes TM5 as well, 8 Cycles at 1000% Usmus 7+ hour run.


----------



## mongoled

If I remember correctly "sil" should be checked when you are NOT applying any CO offsets, otherwise the results shown are not "correct".......


----------



## Audioboxer

Booo! At least there were no timeouts!

I'll try 1.63v tonight, I already knew 1.61v was a no go after errors quite early at 208 tRFC. Might just be it still needs a tiny bit more voltage. The above error must have came later on, like 4 cycles were complete when I left it.


----------



## jcpq

Good morning friends.
Can anyone explain what the CR 1.5T means?


----------



## Reaxer

jcpq said:


> Good morning friends.
> Can anyone explain what the CR 1.5T means?


People use that term when GDM is enabled with 1T command rate


----------



## Imprezzion

tekokk said:


> how can you check this?


CPU-Z main CPU tab shows stepping. Otherwise like this on the IHS or on the box if it wasn't a tray CPU.


----------



## TimeDrapery

Woohoo! Here's a rather low voltage timing set that's been stability tested... I like the way the 15-15-15-35 set _looks_ because I'm a nerd 😂😂😂😂😂

Also, VDIMM for this set is 1.4V "set" but something like 1.465 "get" according to HWiNFO64... ****ing Gigabyte


----------



## Taraquin

TimeDrapery said:


> Woohoo! Here's a rather low voltage timing set that's been stability tested... I like the way the 15-15-15-35 set _looks_ because I'm a nerd 😂😂😂😂😂
> 
> Also, VDIMM for this set is 1.4V "set" but something like 1.465 "get" according to HWiNFO64... ****ing Gigabyte
> 
> View attachment 2542117


Same here bout the overvolting of the ram on gigabyte boards. I get 0.02-0.03V higher readouts on hwmonitor than what I set in bios. Tried above 3800? You got a compact 2 dimm board and single CCD-cpu, might get 4000+ WHEA 19 free


----------



## TimeDrapery

Taraquin said:


> Same here bout the overvolting of the ram on gigabyte boards. I get 0.02-0.03V higher readouts on hwmonitor than what I set in bios. Tried above 3800? You got a compact 2 dimm board and single CCD-cpu, might get 4000+ WHEA 19 free


A few times, I've been working to get a low VDIMM set stable to rule out the timings as a source of any potential issues during my next go around... We'll see what happens!


----------



## binder87

so im sure most of you have stumbled upon the fact that at least on the b550 unify, cldo vddp and vddg's are set quiet high when on auto (1.1v vddp, around soc level for the vddg's). i have 4X8 SR b dies....
the thing is, cldo [email protected] 1.1v actually gives me consistently better aida results including lower latency, and this is not margin of error stuff. also tphyrdl is always trained at a lower value once cldo vddp is 1.08V and above. on one hand, i really like the slight performance\latency benefit. on the other hand, i hear so many claims [email protected] can be risky\detrimental....can anyone help me with this?


----------



## Veii

binder87 said:


> on the other hand, i hear so many claims [email protected] can be risky\detrimental....can anyone help me with this?


i think! IMC dies near 1.15
but 1.1v is already 2500-2600 MCLK (5000-5200MT/s theritory) ~ just so you know the "voltages" you play with. 5K likely needs less than 1.1v
Neither cLDO_VDDP nor procODT should be used for DIMM or FCLK powering.
Lower the better, on both. cLDO_VDDP is purely for MCLK (IMC) and nothing else
FCLK limits have no connection to MCLK, hence MCLK can already run at such high freq in desync


----------



## binder87

Veii said:


> i think! IMC dies near 1.15
> but 1.1v is already 2500-2600 MCLK (5000-5200MT/s theritory) ~ just so you know the "voltages" you play with. 5K likely needs less than 1.1v
> Neither cLDO_VDDP nor procODT should be used for DIMM or FCLK powering.
> Lower the better, on both. cLDO_VDDP is purely for MCLK (IMC) and nothing else
> FCLK limits have no connection to MCLK, hence MCLK can already run at such high freq in desync


I get what you're saying....but than why MSI, across several bios versions, in one of their higher end boards, is making auto voltages once x.m.p is enabled that high? 1.1v cldo vddp, above 1.1v for the vddg's....i mean, if i was less of an enthusiast, i would enable x.m.p and forget about it, and by doing so could potentially fry my CPU....why would MSI risk it so that it could potentially so easily kill many users CPUs? Either something is seriously wrong with their bios version testing, or that AMD changed something in the microcode or something of that sort to enable those voltages on default on purpose when ocing the memory....
Btw, before i noticed it, i ran those voltages for a little over 2weeks. I guess im lucky nothing got damaged.


----------



## Veii

binder87 said:


> I get what you're saying....but than why MSI, across several bios versions, in one of their higher end boards, is making auto voltages once x.m.p is enabled that high? 1.1v cldo vddp, above 1.1v for the vddg's....i mean, if i was less of an enthusiast, i would enable x.m.p and forget about it, and by doing so could potentially fry my CPU


Has happened
See combination of issues with cLDO_VDDP 1.15, plus VDDG 1.2 & SOC 1.3v under procODT 60ohm
Happens with XMP on 3600 ~ well , "happened"

Also a reminder of dead Cezanne's by using AGESA 1.2.0.4 (pre patch-A) , which pushed 1.6v onto them. I think it was slightly more
Never trust Auto values 
AMD covers their mistakes, and current bioses stop overvolting VDDG 
But procODT 60ohm "bug" or failsafe plus bug, have not been fixed. Only the dangerous part of overvoltage plus high impedance, was removed.
Bioses remain IC unaware, and base their predictions of the XMP profile. Soo often a lot of mess comes out which is bruteforce trained on, till one of the presets posts.


----------



## domdtxdissar

So i'm back to my regular 2x16GB dual rank 1900/3900 CL13 setup 









Did also spend some time to verify 100% stability new tighten *tRDWR 8* and *tWRRD 2* timings, and for that i needed a minor change from RttNom "6" to "7" in the end (gives + ~100-150mb/sec in copy speeds compared to 9/3)








In this stresstest screenshot we have the following:

200% RunMemtestPro
25 cycles 1usmus TestMem
*6 hours Y-cruncher all tests*
*20000% Karhu ram test (10 hours)*
Linpack Xtreme running 24/7 PBO CO settings = ~673 Gflops (@ ~260 PPT)
Don't think i will do anymore benching/stability testing until i get the new cpus to play around with 😇


----------



## park1999

I'm trying the timing of cl15 4200 15-15-30-45 timing.
4266 cl16181818 passed the test.
4200 cl15 15 30 45 is too difficult.
(There was an error around the 11th cycle.)
I ask for advice.(no whea)
































4200 cl 15 15 15 30 45
4 4 4 8 tfaw 16 trtp 6 twr 12
trfc252 twcl 14 trdwr 10 twrrd 2 tcke 14 clk 60 add 20 cs 40 cke 20
rtt 36.9 707 vdimm 1.66 vsco 1.225 cldo vddp 1.0 ccd 1.07 iod 1.12


----------



## Imprezzion

Hooking in to the discussion a few posts up, how high of a VDDG's is generally accepted as "safe"?

I run CLDO VDDP at like 0.92 as it doesn't affect stability at all at 3866 but I do need 1.120v IOD and 0.980 CCD to stop the WHEA's and some errors in TM5. ProcODT 34.3.


----------



## park1999

I've been using a clock of 4000mhz or more for several month


----------



## TMavica

Currently running 3800C4 1T, tm5 test is passed and without whea error. However if i run aida64 memory benchmark, there whea error came out, I need to raise the vddp from 0.9 to 0.95 to get rid of it...


----------



## mil777

Why is it that IF on 5800X clocks so much lower compared to 5600X while both being single CCD cpus?

Looking at the spreadsheet even the R9 59x0 cpus sometimes achieve higher clocks than the 5800X.

Why is that?


----------



## Audioboxer

domdtxdissar said:


> So i'm back to my regular 2x16GB dual rank 1900/3900 CL13 setup
> View attachment 2542101
> 
> 
> Did also spend some time to verify 100% stability new tighten *tRDWR 8* and *tWRRD 2* timings, and for that i needed a minor change from RttNom "6" to "7" in the end (gives + ~100-150mb/sec in copy speeds compared to 9/3)
> View attachment 2542102
> 
> In this stresstest screenshot we have the following:
> 
> 200% RunMemtestPro
> 25 cycles 1usmus TestMem
> *6 hours Y-cruncher all tests*
> *20000% Karhu ram test (10 hours)*
> Linpack Xtreme running 24/7 PBO CO settings = ~673 Gflops (@ ~260 PPT)
> Don't think i will do anymore benching/stability testing until i get the new cpus to play around with 😇


Wonder if 12/8 is down to the memory or IMC or both. No go for me! Same with tWRRD IIRC. Though I guess I'll try a different Proc and more voltage but I believe I tried that before.

Just goes to show even with the stupid expensive bins they're not all made equally! Unless the CPU is playing a part here. My 5950x is sadly a bit weaker than others it seems.

*edit *- It's 12/8 I can't do, tWRRD 2 will boot.


----------



## Audioboxer

Got an email in from NewEgg about 10% off codes for G.SKILL 32GB memory

But the stock is low Are you a human? There is barely nothing left in terms of DR lol, and even then, I don't think I can see any B-die. I guess pretty much all production is shifting to DDR5 and who knows what Samsung are doing.

I think there will likely be a slow slide upwards with DDR4 pricing, especially for B-die. I guess you can check NewEgg regional for your country, but they usually display the same stock and just ship worldwide.


----------



## Mach3.2

Audioboxer said:


> Got an email in from NewEgg about 10% off codes for G.SKILL 32GB memory
> 
> But the stock is low Are you a human? There is barely nothing left in terms of DR lol, and even then, I don't think I can see any B-die. I guess pretty much all production is shifting to DDR5 and who knows what Samsung are doing.
> 
> I think there will likely be a slow slide upwards with DDR4 pricing, especially for B-die. I guess you can check NewEgg regional for your country, but they usually display the same stock and just ship worldwide.


The 3600 14-15-15 bin is still in stock, though the price is back at the usual price. Just for reference, I bought a set for 240 USD last Black Friday.


----------



## Audioboxer

Mach3.2 said:


> The 3600 14-15-15 bin is still in stock, though the price is back at the usual price. Just for reference, I bought a set for 240 USD last Black Friday.


Ah, just double checked my email title










Just RipJaws mentioned so ymmv on other bins 

Of course all the good RipJaws bins seem to be long OOS. I bought my 3600 14-14-14-14 bin from NewEgg.

*edit* - No wait, it's still in stock G.SKILL Ripjaws V Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 3600 (PC4 28800) Intel XMP 2.0 Desktop Memory Model F4-3600C14D-32GVKA - Newegg.com Just NewEgg being deceptive with their title. Not clear what bins.


----------



## Mach3.2

Those titles are really a dumpster fire, it's even better when you're trying to look for the 3600 16-16-16 bin, good luck! 😂


----------



## PJVol

mil777 said:


> Why is that?


Design specifities.


----------



## Audioboxer

mil777 said:


> Why is it that IF on 5800X clocks so much lower compared to 5600X while both being single CCD cpus?
> 
> Looking at the spreadsheet even the R9 59x0 cpus sometimes achieve higher clocks than the 5800X.
> 
> Why is that?


Single CCDs run the hottest and the 5800x is 8 core vs the 6 cores of the 5600x. The 5800x will get hotter by design, therefore, lower clocks by default. IIRC it also has a bit more cache but I'm not sure if that contributes to thermals or not.

Ironically, the dual CCDs can thermal manage better, leading to potential for higher clocks as default.


----------



## Reaxer

I've been testing this for a bit. for 3800C14-15 I just need 1.5V so that's nice. CL13 is being really hard to stabilize so I dropped that for a bit. 








It seems you were right @Audioboxer that SCLs to 2 lowers Aida's read and copy a bit. I'm getting 52.6ns latency with this.
Have you guys tested the performance difference between lower tCWL (-4 here) or lower tRDWR? And what about tWRRD?
Are tWRRD and tRDWR related? It seems I can run [email protected] just fine, but I'm not sure if that limits me lowering tRDWR.


----------



## Audioboxer

Reaxer said:


> I've been testing this for a bit. for 3800C14-15 I just need 1.5V so that's nice. CL13 is being really hard to stabilize so I dropped that for a bit.
> View attachment 2542234
> 
> It seems you were right @Audioboxer that SCLs to 2 lowers Aida's read and copy a bit. I'm getting 52.6ns latency with this.
> Have you guys tested the performance difference between lower tCWL (-4 here) or lower tRDWR? And what about tWRRD?
> Are tWRRD and tRDWR related? It seems I can run [email protected] just fine, but I'm not sure if that limits me lowering tRDWR.


I find it better just to match tCWL to TCL and keep tRDWR as low as possible. Only time you can't match tCWL is if you are running an uneven tCL. I'd try running 14/8 and see how you get on. 14/7 rarely boots on some sticks.

If your tWRRD is stable at 1 I guess it can just be left there. If you're going to aim for 1T keep in mind this might hold that back. I'm unsure. I'd probably leave it at Veii's recommended 3 for DR until it's the absolute last thing you want to try lowering.

tCWL and tRDWR are related, think tWRRD is more standalone, but not 100% sure here.


----------



## Reaxer

Audioboxer said:


> I find it better just to match tCWL to TCL and keep tRDWR as low as possible. Only time you can't match tCWL is if you are running an uneven tCL. I'd try running 14/8 and see how you get on. 14/7 rarely boots on some sticks.
> 
> If your tWRRD is stable at 1 I guess it can just be left there. If you're going to aim for 1T keep in mind this might hold that back. I'm unsure. I'd probably leave it at Veii's recommended 3 for DR until it's the absolute last thing you want to try lowering.
> 
> tCWL and tRDWR are related, think tWRRD is more standalone, but not 100% sure here.


Cool, thanks will change back then! Next week I'll probably do some performance testing in some games and see if there's a difference.


----------



## blodflekk

Am I the only one that come here daily and reads through all the posts, but doesn't comment because I don't feel qualified to? 😅


----------



## KedarWolf

blodflekk said:


> Am I the only one that come here daily and reads through all the posts, but doesn't comment because I don't feel qualified to? 😅


I'm addicted to overclock.net, read it obsessively. Many threads. But from time to time I do comment on something if I feel it's relevant. My overclocking skills are decent and if I find out something new or see I can help someone, I will.

I might have a few posts here since I joined several years ago.


----------



## domdtxdissar

Audioboxer said:


> I find it better just to match tCWL to TCL and keep tRDWR as low as possible. Only time you can't match tCWL is if you are running an uneven tCL. I'd try running 14/8 and see how you get on. 14/7 rarely boots on some sticks.
> 
> If your tWRRD is stable at 1 I guess it can just be left there. If you're going to aim for 1T keep in mind this might hold that back. I'm unsure. I'd probably leave it at Veii's recommended 3 for DR until it's the absolute last thing you want to try lowering.
> 
> tCWL and tRDWR are related, think tWRRD is more standalone, but not 100% sure here.


I my findings, its tRDWR and tWRRD thats very much related while tCWL only should be matched with tCL..

*tCWL*: _CAS Write Latency. The delay between when the IMC activates a column of memory and when a write command is executed._ Although not in the timing abbreviation, tCL specifically controls read operations; this timing, then, is just tCL but for write operations. According to AMD, this timing greatly impacts stability, which again makes sense, as it is related to the famous tCL.

_Overclocking guidelines?_ : According to the previously linked AMD “Let’s Talk DRAM!” post, *tCWL should be set to tCL or tCL - 1*, and is much more stable at even values. My kit has this stable as low as 10 (with CL13), but any lower absolutely refused to POST.

*tRDWR*: _Read Write Command Spacing. The amount of turn-around clocks between a read command and a write command on the same rank._ I’m not entirely sure what a turn-around clock is, but I believe it refers to tRDRD/WRWR timings. Anyway, this is the amount of those cycles that must pass after a read command is sent to a memory address before the IMC can send a write command to a different address on the same rank of a DIMM. According to AMD this timing has a large effect on throughput.

_Overclocking guidelines?_ : According to some users (and myself), this timing is somewhat tied to tWRRD, in that only one of the two can be set to a very low value, while the other must be set to a higher value. *One approach to tightening these two timings is to set one to auto, lower one all the way, and then take the other off auto and manually tighten it.

tWRRD*: _Write Read Command Spacing. The amount of turn-around clocks between a write command and a read command on the same rank._ This is basically tRDWR, but after a write command and before a read command instead of vice versa. According to AMD this timing has a large effect on throughput.

_Overclocking guidelines?_ : See tRDWR.


----------



## blodflekk

KedarWolf said:


> I'm addicted to overclock.net, read it obsessively. Many threads. But from time to time I do comment on something if I feel it's relevant. My overclocking skills are decent and if I find out something new or see I can help someone, I will.
> 
> I might have a few posts here since I joined several years ago.


I have done that in the past on other threads, however I am brand new to amd, this is my first AMD and as much as I'm reading I am finding it quite hard to learn and mem OC is SO different to intel. I miss how easy everything on intel is 😅 

I can't seem to make sense of tPHYRDL. Occasionally I will boot with 26/26 but 98.5% of the time its always 26/28 and I don't know what I should be doing to correct this. Happens for me at 3600 and 3800


----------



## Reaxer

blodflekk said:


> I have done that in the past on other threads, however I am brand new to amd, this is my first AMD and as much as I'm reading I am finding it quite hard to learn and mem OC is SO different to intel. I miss how easy everything on intel is 😅
> 
> I can't seem to make sense of tPHYRDL. Occasionally I will boot with 26/26 but 98.5% of the time its always 26/28 and I don't know what I should be doing to correct this. Happens for me at 3600 and 3800


I've noticed that for my imc, tPHYRDL always trains at 26/26 when cldo vddp is 0.880v


----------



## Audioboxer

domdtxdissar said:


> I my findings, its tRDWR and tWRRD thats very much related while tCWL only should be matched with tCL..
> 
> *tCWL*: _CAS Write Latency. The delay between when the IMC activates a column of memory and when a write command is executed._ Although not in the timing abbreviation, tCL specifically controls read operations; this timing, then, is just tCL but for write operations. According to AMD, this timing greatly impacts stability, which again makes sense, as it is related to the famous tCL.
> 
> _Overclocking guidelines?_ : According to the previously linked AMD “Let’s Talk DRAM!” post, *tCWL should be set to tCL or tCL - 1*, and is much more stable at even values. My kit has this stable as low as 10 (with CL13), but any lower absolutely refused to POST.
> 
> *tRDWR*: _Read Write Command Spacing. The amount of turn-around clocks between a read command and a write command on the same rank._ I’m not entirely sure what a turn-around clock is, but I believe it refers to tRDRD/WRWR timings. Anyway, this is the amount of those cycles that must pass after a read command is sent to a memory address before the IMC can send a write command to a different address on the same rank of a DIMM. According to AMD this timing has a large effect on throughput.
> 
> _Overclocking guidelines?_ : According to some users (and myself), this timing is somewhat tied to tWRRD, in that only one of the two can be set to a very low value, while the other must be set to a higher value. *One approach to tightening these two timings is to set one to auto, lower one all the way, and then take the other off auto and manually tighten it.
> 
> tWRRD*: _Write Read Command Spacing. The amount of turn-around clocks between a write command and a read command on the same rank._ This is basically tRDWR, but after a write command and before a read command instead of vice versa. According to AMD this timing has a large effect on throughput.
> 
> _Overclocking guidelines?_ : See tRDWR.


Interesting, I'll try a higher tWRRD later just to see if tRDWR 7 can actually boot. Failing that I'll just stick tWRRD to 2 and stability test it, as I know it can boot.


----------



## blodflekk

Reaxer said:


> I've noticed that for my imc, tPHYRDL always trains at 26/26 when cldo vddp is 0.880v


 Just tried that now and it didn't work for me. Doesn't this need to be higher ? 










This is what I'm running. It is stable in tm5 1usmus


----------



## MrHoof

Audioboxer said:


> Interesting, I'll try a higher tWRRD later just to see if tRDWR 7 can actually boot. Failing that I'll just stick tWRRD to 2 and stability test it, as I know it can boot.


GL didnt see anyone else running tRDWR 7 so far. But I am pretty sure my tWRRD does not go below 3 even on tRDWR 8 gonna test that again later this week.(not in mood for cmos reset now)


----------



## hazium233

tRDWR and tWRRD are only related in that they both depend on the difference of tCL and tCWL.

If you just raise tRDWR for whatever reason, that doesn't mean you can necessarily drop tWRRD. And vice versa.

...

anta777 had a formula earlier:

tWRRD >= tCWL - tCL + WBL/2 + tRPRE

WBL/2 would be 2t with BC4 and tRPRE = 1t, or 3 for those added together.

Actually anta777 had 4 instead of WBL/2, so that would be like BL8.

Also if you worked out a timing a diagram with WBL/2 = 2 (as in BC4, four bits) and tCL=tCWL where you try tWRRD of 2t, the problem would be that WPST would overlap with RPRE, and I am not sure how that could work. Would like correction on this if it is wrong.

..

Interesting this thread has turned back to this because I was looking at the 3600C16 2x16GB Neos I got recently and the tPHYRDL mismatch with GDM. Which is starting at 3600. But the funny thing is that on channel A with tPHYRDL at 28 it set tRDWR and tWRRD to 9 and 2. B was 8 and 3 with 26. That seemed to work.

Changing to 2T the tPHYRDL dropped to 26 on A, but it left the tRDWR and tWRRD alone. That resulted in ~2000 errors in mt86 test 8 in the first loop. Set to 9 and 3, those errors disappeared and it also passed 25 cycles TM5.

If tPHYRDL +2 is actually treated like tCL+1 as some of you have suggested earlier in the thread, then it is possible this is why GDM was working despite tWRRD set to 2t. But this is chicken and egg, I don't know if it wants to train the tRDWR and tWRRD this way due to the tPHYRDL, or the other way around, or if this is coincidental or both a symptom of something else.

With locked timings 3200 through 3533 are 26/26, 3600 and 3733 are 28/26, and 3800 went to 28/28. So far I am not sure I can affect this with GDM enabled, it didn't seem to respond to the timing changes I tried, VDDP steps, ProcODT, etc.

DRAM Latency Enhance didn't seem to affect it either.

edit: actually if left completely to its own devices, what it wants to do is switch tCWL to 14t, in which case Channel A does 11 and 1 for tRDWR and tWRRD. But I bet this would pass 2T (assuming the tCWL is stable) because 14-16+2+1 <= 1

edit2:

Here's the formulas for within a rank from Micron 8Gbit sheet, tRDWR ends up being higher than this at frequency:










The extra +1 in for read to write is because of the difference in alignment. (ie reads are edge aligned and writes are center aligned)


----------



## domdtxdissar

In my view, both anta777 and that sheet above, among others, are recommending safe settings -> which can also can be interpreted as "slow settings".

The same way some people are recommending "flat primary timings", while we know running RCDWR at 8 or the lowest you can nets a real performance gain. (very easy to see this in y-cruncher bench which is extremely sensitive to this)
The same way some people are recommending "correctly calculated" RAS and RC values when its proven to be slower then tighter settings

Its the same way with TDWR/WRRD, tighter spread gives higher throughput, which easy to see in memory copy benchmarks

This is overlock.net, i would enable XMP if i wanted to run safe settings recommended by memory manufacturers specsheet guidelines 
(and our memory should be dead a long time ago according to what's considered "safe")

i follow, or atleast try to go where my own tested performance numbers take me instead of "listening blindly" to others 
(and i get some pushback because of it also)


----------



## Audioboxer

domdtxdissar said:


> In my view, both anta777 and that sheet above, among others, are recommending safe settings -> which can also can be interpreted as "slow settings".
> 
> The same way some people are recommending "flat primary timings", while we know running RCDWR at 8 or the lowest you can nets a real performance gain. (very easy to see this in y-cruncher bench which is extremely sensitive to this)
> The same way some people are recommending "correctly calculated" RAS and RC values when its proven to be slower then tighter settings
> 
> Its the same way with TDWR/WRRD, tighter spread gives higher throughput, which easy to see in memory copy benchmarks
> 
> This is overlock.net, i would enable XMP if i wanted to run safe settings recommended by memory manufacturers specsheet guidelines
> (and our memory should be dead a long time ago according to what's considered "safe")
> 
> i follow, or atleast try to go where my own tested performance numbers take me instead of "listening blindly" to others
> (and i get some pushback because of it also)


I broadly agree, I think the only counterpoint I can probably add is with the number of people out there not willing to read, learn and listen sometimes the safer settings are a way to handle that lol.

Plus, with some of the timings we're talking about it can require the "super bins" of say B-die to work well without the "safe expectations". We do have to remember not every kit of DDR4 can pull off some of the ridiculously low timings B-die can. Therefore, general expectations are probably best set from some sort of "good practice" baseline. That's usually the formulas or calculations Veii, Anta and others post.

And finally, apart from people not reading or listening, many won't properly test memory for the hours needed and some of these timings do need tested for a proper number of cycles or time. But that's not applicable for us or most of this topic properly testing for hours.










For example, I need to use the PC so a quick test of tWRRD at 2 shows promise and your findings that it does indeed help throughput! But I'll never daily after 6 cycles. Some folks do run things like that and think it's "daily stable". So for their own sake some of the "expected safe formulas" are probably best followed...

Or you have you and I with the same bin, but I cannot boot tRDWR 8. Again an example of how B-die can get stupid low and maybe smash the expected formulas, but it's still partly down to your bin, CPU, mobo and so on. Not a given you can operate outside "safe expectations", but operating within them should be do-able for 90%+ of people starting out OCing memory.

BUT, the final point, this IS OC.net and you are right that we're here to push our hardware and often that might be specific to us if we hit the "silicon jackpot". If others won't read, listen and learn it's their own _funeral_ if they end up with OS corruption


----------



## Taraquin

Sometimes a low cwl seems to reduce the ability to run tight rdwr. Rdwr seems more important for performance than cwl. I usually run cwl at even number at same or one below cl. Rdwr usually works fine at rcdrd/2 or +1-2 if dual rank. Wrrd is usually easy to run at 1 on SR, but easier on 3 on DR.


----------



## hazium233

domdtxdissar said:


> In my view, both anta777 and that sheet above, among others, are recommending safe settings -> which can also can be interpreted as "slow settings".
> 
> The same way some people are recommending "flat primary timings", while we know running RCDWR at 8 or the lowest you can nets a real performance gain. (very easy to see this in y-cruncher bench which is extremely sensitive to this)


The main point of tRDWR and tWRRD is to prevent the bursts from running into each other since the bus is unidirectional and has to flip between them.

The tRDWR if anything actually underestimates what is possible to run on Ryzen, probably partly due to the controller.

Ignoring the burst and preamble, they will always be relative to difference between tCL and tCWL + some offset.

tRDWR >= tCL-tCWL + x

tWRRD >= tCWL - tCL + y

That is basically immutable once you find X or Y on the setup. At ~3800 this works out to 8 and 3 nearly every time it seems like, at least with decent dimms. Rarely some setups seem like they might do x=7.

If 2t is valid for tWRRD on a dual rank setup where tCL=tCWL, would be interesting to see it demonstrated *(with 2T, since I think GDM is taking too many liberties with timings and that is the problem). 1t is absolutely impossible because otherwise the bursts run into each other. Min burst length for DDR4 is 2t (4 bits) for read or write.

edit: if tWRRD is an offset value rather than absolute, then that changes the range for a calculation obviously.


----------



## nick name

hazium233 said:


> The main point of tRDWR and tWRRD is to prevent the bursts from running into each other since the bus is unidirectional and has to flip between them.
> 
> The tRDWR if anything actually underestimates what is possible to run on Ryzen, probably partly due to the controller.
> 
> Ignoring the burst and preamble, they will always be relative to difference between tCL and tCWL + some offset.
> 
> tRDWR >= tCL-tCWL + x
> 
> tWRRD >= tCWL - tCL + y
> 
> That is basically immutable once you find X or Y on the setup. At ~3800 this works out to 8 and 3 nearly every time it seems like, at least with decent dimms. Rarely some setups seem like they might do x=7.
> 
> If 2t is valid for tWRRD on a dual rank setup where tCL=tCWL, would be interesting to see it demonstrated *(with 2T, since I think GDM is taking too many liberties with timings and that is the problem). 1t is absolutely impossible because otherwise the bursts run into each other. Min burst length for DDR4 is 2t (4 bits) for read or write.
> 
> edit: if tWRRD is an offset value rather than absolute, then that changes the range for a calculation obviously.


I miss how ASUS BIOS versions, from a while ago, used to set tRDWR and tWRRD per channel when left to Auto. Now when they are left to Auto they get set very high and the same on each channel. Something around 18 and 7 on both channels.


----------



## hazium233

nick name said:


> I miss how ASUS BIOS versions, from a while ago, used to set tRDWR and tWRRD per channel when left to Auto. Now when they are left to Auto they get set very high and the same on each channel. Something around 18 and 7 on both channels.


I don't know where these numbers come from, if it is upstream from AMD and their training, or how much motherboard vendors are making their tweaks to the system. When I tried my 2700X on this motherboard, it would do the 18 and 7 thing though, but that was a much older bios. I think it was sort of using the Matisse image, so maybe that is part of it?

My anecdote about the tWRRD going to 2 was in part my frustration trying to get this motherboard to train things with some consistency, but it seems I really should have completely ignored GDM since as dom suggested a long while ago.


----------



## hazium233

If DQS_t / DQS_c allow post and preamble overlap somehow, or if tWRRD is an offset then my posts are pretty useless, but at least I got to us paint.

This is a Write to Read diagram from the Micron 8Gb sheet, I left the page number in case anyone wanted to see it in there:



Spoiler















Different bank group, same rank, it is using tWTRS (2t). It has the standard burst length of 8 bit or 4t, but since tCL=11 and tCWL=9 the math is as if you are using BC4 (4bit, 2t) but with tCL=tCWL.

Since tWTR_ has to expire before the read can be issued to the rank, the actual write command to read command delay here is 15t (= tCWL+WBL/2+tWTRS). For this it shouldn't matter if tWRRD is set to nearly anything since it still is waiting on tWTR_.

If different rank then tWRRD should matter, set to 1 or 2t:



Spoiler















If CWL=11 but WBL was 2, then the burst still ends at T13



Spoiler















This should be valid for at least mundane frequencies (would eventually have to go up).

It is somewhat similar for the read to write (tRDWR), but have to account for the write sticking forward half a clock.

I don't see how raising one will really allow you to drop another, if they are both at their true minimum.


----------



## KedarWolf

hazium233 said:


> If DQS_t / DQS_c allow post and preamble overlap somehow, or if tWRRD is an offset then my posts are pretty useless, but at least I got to us paint.
> 
> This is a Write to Read diagram from the Micron 8Gb sheet, I left the page number in case anyone wanted to see it in there:
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2542445
> 
> 
> 
> 
> Different bank group, same rank, it is using tWTRS (2t). It has the standard burst length of 8 bit or 4t, but since tCL=11 and tCWL=9 the math is as if you are using BC4 (4bit, 2t) but with tCL=tCWL.
> 
> Since tWTR_ has to expire before the read can be issued to the rank, the actual write command to read command delay here is 15t (= tCWL+WBL/2+tWTRS). For this it shouldn't matter if tWRRD is set to nearly anything since it still is waiting on tWTR_.
> 
> If different rank then tWRRD should matter, set to 1 or 2t:
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2542446
> 
> 
> 
> 
> If CWL=11 but WBL was 2, then the burst still ends at T13
> 
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2542447
> 
> 
> 
> 
> This should be valid for at least mundane frequencies (would eventually have to go up).
> 
> It is somewhat similar for the read to write (tRDWR), but have to account for the write sticking forward half a clock.
> 
> I don't see how raising one will really allow you to drop another, if they are both at their true minimum.


If I run the below timings with tCWL at 12, I can run 10-1 on tRDWR and tWRRD.

Running it at 1 helps a bit with latency and bandwidth. I've tried other tWRRDs and 1 with this configuration seems best.

Edit: tCWL at 12 helps a bit rather than 14 too.


----------



## MrHoof

MrHoof said:


> I am pretty sure my tWRRD does not go below 3 even on tRDWR 8 gonna test that again later this week.(not in mood for cmos reset now)


Just tried it not even 11/2 does get me to Bios but 7/3 works fine. I dont get it.


----------



## Comalive

Did the 1900 fclk hole get fixed for anyone with the new AGESA 1.2.0.5 (?) version?


----------



## jcpq

My ram config 1T vs 2T

1T:
















2T:


----------



## domdtxdissar

So i have received the first of my 3 new 5950x's 
Sadly the first one missed the new B2 stepping by a few weeks, but i can share preliminary silicon quality stats:

All tests was run at stock bios settings --> PBO disabled and "auto" LLC which is pretty weak on this MSI UNIFY X MAX motherboard. (upto 10% vdroop under heavy load)
All stock diagnostic voltages in hydra.



Spoiler: My original 5950x stats -> BG 2046 SUS 



Asus tool = "116 silicon quality" and "4381mhz max heavy load"

Hydra: CCD quality
CCD #1 = 4525mhz --> 4.05 rating = *Golden CCD*
CCD #1 = 4325mhz --> 3.87 rating = *Bronze CCD*

1T-2T:
CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
CCD #2 = AVX1 = 4725mhz / FMA3 = 4600mhz

3T-4T:
CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz

9T-12T:
CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz

13T-16T:
CCD #1 = AVX1 = 4675mhz / FMA3 = 4550mhz
CCD #2 = AVX1 = 4500mhz / FMA3 = 4375mhz

All threads:
CCD #1 = AVX1 = 4475mhz / AVX2 = 4400mhz / FMA3 = 4125mhz
CCD #2 = AVX1 = 4325mhz / AVX2 = 4250mhz / FMA3 = 3975mhz

Game profile:
CCD #1 = 4725mhz
CCD #2 = 4550mhz

Highest ST clockspeed for 4 highest rated cores: (1375mv set)
#1 = core1 @ 4925mhz (212 rating)
#2 = core3 @ 4900mhz (208 rating)
#3 = core5 @ 4875mhz (212 rating)
#4 = core7 @ 4875mhz (203 rating)

Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set (upto 10% vdroop)
CCD #1 = 4700mhz
CCD #2 = 4600mhz

Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
1900:3800 = 642.98 Gflops
1933:3866 = ~400 Glops (whea's and massive throttling)
2000:4000 = not even attempted






Spoiler: My 5950x #1 out of 3 -> BG 2141 SUS



Asus tool = "117.5 silicon quality" and "4394mhz max heavy load"

Hydra: CCD quality
CCD #1 = 4575mhz --> 4.11 rating = *Platinum CCD*
CCD #1 = 4475mhz --> 4.02 rating = *Golden** CCD*

1T-2T:
CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz

3T-4T:
CCD #1 = AVX1 = 4725mhz / FMA3 = 4600mhz
CCD #2 = AVX1 = 4675mhz / FMA3 = 4550mhz

9T-12T:
CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
CCD #2 = AVX1 = 4650mhz / FMA3 = 4525mhz

13T-16T:
CCD #1 = AVX1 = 4700mhz / FMA3 = 4575mhz
CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz

All threads:
CCD #1 = AVX1 = 4525mhz / AVX2 = 4450mhz / FMA3 = 4175mhz
CCD #2 = AVX1 = 4450mhz / AVX2 = 4375mhz / FMA3 = 4100mhz

Game profile:
CCD #1 = 4750mhz
CCD #2 = 4600mhz

Highest ST clockspeed for 4 highest rated cores: (1375mv set)
#1 = core3 @ 4975mhz (208 rating)
#2 = core7 @ 4950mhz (212 rating)
#3 = core8 @ 4875mhz (212 rating)
#4 = core1 @ 4850mhz (203 rating)

Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set (upto 10% vdroop)
CCD #1 = 4800mhz
CCD #2 = 4650mhz

Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
1900:3800 = 643.93 Gflops
1933:3866 = ~616.5 Glops (some whea's)
2000:4000 = 199 Gflops (whea's and massive throttling)



Few takeaways:

Still limited to 1900 flck
Second CCD on new 5950x is much stronger than my old 5950x
My old 5950x have higher peak ST clockspeeds but worse average CCD quality. (few cores are worse which limits the average)
*Main drawback*: Best 212 cores on this #1 5950x are core 7 and 8. This is bad for a few reasons.. The two last cores on a full CCD always have around 6 degrees higher temps. Some benchmarks/application always ignore CPPC (such as CPU-Z) and forces workload to core1, this is very bad since core1 is the worst one in entire CCD on this cpu. (you always wish for your best 212 cores to be core1)










Running a full hydra diagnostic with elevated voltages now, can post a comparison between these cpus with higher PPT budget later/tomorrow.
Really hope my two last cpus are better than this.. Not happy with current sample i got.

Hopefully i get the two last ones from other vendor on Friday


----------



## MrHoof

domdtxdissar said:


> Main drawback: Best 212 cores on this #1 5950x are core 7 and 8. This is bad for a few reasons.. The two last cores on a full CCD always have around 6 degrees higher temps. Some benchmarks/application always ignore CPPC (such as CPU-Z) and forces workload to core1, this is very bad since core1 is the worst one in entire CCD on this cpu. (you always wish for your best 212 cores to be core1)


On my 5800x 1 full CCD the highest temps i see on core 3-6, remounted my U12A already once with fresh paste but the result is the same.


----------



## domdtxdissar

MrHoof said:


> On my 5800x 1 full CCD the highest temps i see on core 3-6, remounted my U12A already once with fresh paste but the result is the same.


Hmm by the hundreds of logs we have seen/talked about on the hydra discord, its always the last two. Dont know why you have Frankenstein CCD 🤣
I'm ofcoure talking about recorded temps when you run something like core cycler or hydra ST CO diagnostic which puts equal load on all cores *one by one*. (not hwinfo after a normal days usage)


----------



## MrHoof

domdtxdissar said:


> Hmm by the hundreds of logs we have seen/talked about on the hydra discord, its always the last two. Dont know why you have Frankenstein CCD 🤣


Maybe 🤣 I like the sample tho. CB23









edit: CPPC order best to worst 4/1/3/6/0/7/5/2 rather 4/1 are both rated #1 by CPCC and 4 is better then 1 by hardware-fused rating.








edit2: also core 0 and 1 have the highest -offset of -12 while others are between -14 and -28.


----------



## MrHoof

domdtxdissar said:


> Hmm by the hundreds of logs we have seen/talked about on the hydra discord, its always the last two. Dont know why you have Frankenstein CCD 🤣
> I'm ofcoure talking about recorded temps when you run something like core cycler or hydra ST CO diagnostic which puts equal load on all cores *one by one*. (not hwinfo after a normal days usage)


If u really want a ONE BY ONE comparision u can get it at weekend but result gonna be the same.


----------



## Veii

hazium233 said:


> The main point of tRDWR and tWRRD is to prevent the bursts from running into each other since the bus is unidirectional and has to flip between them.


If too high, it overlapps. If too high it requires IOL delay to be added
if too low, it causes training issues and can not recover

All these, tCWL, tRDWR, tPHY ~ depend on the ODM
AMD enforces every board to behave identical, but there are still issues existing
According to Buildzoid's experience, some boards hate specific values.
According to Veii's experiences, some boards beyond tCL 20 or tCWL 20 rather ~ simply give up

tCWL 22 does not function (on the examples i've tested)
It completely messes up memory training.
That takes for account that memory training, rather IOL training actually is correct.








In the absolute best case, once it switches away from 28-28, to 30-30
(soo if Board Vendor do indeed put in changes in AMD CBS and then lock it away ~ looking at ASRock)
If they do it correctly ~ it still fails miserably beyond tCWL 20. It just doesn't know what to use


hazium233 said:


> I don't see how raising one will really allow you to drop another, if they are both at their true minimum.


Soo at this post, while tRDWR could be lower, it doesn't function as tCWL is broken
Lowering one, to increase the other works even in cases where they are minimum values
I do think it does try to balance things ~ but user can not correct t()PRE by themself
And except trial and error, there seems to be no direct method of calculation.
Because while there are options, your JEDEC and Veii's unorthodox guides ~ but end up to the same trial and error and watching the result

There are couple of issues here:
~ AMD FW completely goes haywire with predictions on 4966+ strap
~ the lack of user influence in shifting "faulty" tPHY predictions
~ the bios being IC unaware in it's predictions but rather follows XMP to some extend, or better PCB capability (tCCD_) but not IC capability
~ AMD does not follow JEDEC
Last part is very important, but you maybe haven't noticed it

AMD doesn't follow JEDEC on many things
This includes tREFI behavior and this also includes tPHY values (not fully)

Arshia and i had a (many) nice talks , but tREFI so also tRFC is not 8 or 9x postponable
It's dependent on UrgRefSet value , how many it allows ~ soo tREFI is enforced on the user and tRFC has to adjust (4-6x peak)
The range is huge, soo it's not a big deal, but it still has to set a point that AMD (on many parts) does what they want and define for correct.
It does not follow JEDEC, not fully.

I'm happy that you understand and can quote it,
soo i suggest also to grab the current JEDEC specs from my drive (if link gets found)
but i also suggest not to 100% shape your experience based on what you read ~ but based on what you see. 
Good writeup


----------



## Veii

domdtxdissar said:


> Sadly the first one missed the new B2 stepping by a few weeks, but i can share preliminary silicon quality stats:


Good writeup
2141 is still B2 silicon
but not marked as such ~ or has B2 V/F tuning, but runs under wrong microcode


Spoiler: EDIT



If you see something like this under 1203C, then it clearly is a new substrate
Even if it says B0 on the box










B2 should've come since first October
which is 2141 and up
2143 is just "guaranteed" B2 ~ but buggy without running on either 1.2.0.4A or 1.2.0.5


domdtxdissar said:


> Still limited to 1900 flck


This is unfortunate
They had the ability to fix their DPM issue ~ even hardware bound
But either where/are clueless or just forgot it and abandoned it


----------



## Luggage

domdtxdissar said:


> Hmm by the hundreds of logs we have seen/talked about on the hydra discord, its always the last two. Dont know why you have Frankenstein CCD 🤣
> I'm ofcoure talking about recorded temps when you run something like core cycler or hydra ST CO diagnostic which puts equal load on all cores *one by one*. (not hwinfo after a normal days usage)





http://imgur.com/l59VdWl


Though it’s probably skewed a bit by the co curve of course. 

Hmm yea ok 0 and 5 have much lower co values since they are “best” so of course they are hotter.


----------



## Audioboxer

tWRRD 2 seems fine! Also took dom's advice of "this is OC.net" and reduced my tRAS/tRC again lol.

Good news rolling back the chipset drivers and no signs of any TM5 timeouts again. Will shift back to working on 4400 and hopefully there will be no more TM5 timeouts leading to confusion around stability.


----------



## domdtxdissar

domdtxdissar said:


> So i have received the first of my 3 new 5950x's
> Sadly the first one missed the new B2 stepping by a few weeks, but i can share preliminary silicon quality stats:
> 
> All tests was run at stock bios settings --> PBO disabled and "auto" LLC which is pretty weak on this MSI UNIFY X MAX motherboard. (upto 10% vdroop under heavy load)
> All stock diagnostic voltages in hydra.
> 
> 
> 
> Spoiler: My original 5950x stats -> BG 2046 SUS
> 
> 
> 
> Asus tool = "116 silicon quality" and "4381mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4525mhz --> 4.05 rating = *Golden CCD*
> CCD #1 = 4325mhz --> 3.87 rating = *Bronze CCD*
> 
> 1T-2T:
> CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
> CCD #2 = AVX1 = 4725mhz / FMA3 = 4600mhz
> 
> 3T-4T:
> CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
> CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz
> 
> 9T-12T:
> CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
> CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz
> 
> 13T-16T:
> CCD #1 = AVX1 = 4675mhz / FMA3 = 4550mhz
> CCD #2 = AVX1 = 4500mhz / FMA3 = 4375mhz
> 
> All threads:
> CCD #1 = AVX1 = 4475mhz / AVX2 = 4400mhz / FMA3 = 4125mhz
> CCD #2 = AVX1 = 4325mhz / AVX2 = 4250mhz / FMA3 = 3975mhz
> 
> Game profile:
> CCD #1 = 4725mhz
> CCD #2 = 4550mhz
> 
> Highest ST clockspeed for 4 highest rated cores: (1375mv set)
> #1 = core1 @ 4925mhz (212 rating)
> #2 = core3 @ 4900mhz (208 rating)
> #3 = core5 @ 4875mhz (212 rating)
> #4 = core7 @ 4875mhz (203 rating)
> 
> Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set (upto 10% vdroop)
> CCD #1 = 4700mhz
> CCD #2 = 4600mhz
> 
> Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
> 1900:3800 = 642.98 Gflops
> 1933:3866 = ~400 Glops (whea's and massive throttling)
> 2000:4000 = not even attempted
> 
> 
> 
> 
> 
> 
> Spoiler: My 5950x #1 out of 3 -> BG 2141 SUS
> 
> 
> 
> Asus tool = "117.5 silicon quality" and "4394mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4575mhz --> 4.11 rating = *Platinum CCD*
> CCD #1 = 4475mhz --> 4.02 rating = *Golden** CCD*
> 
> 1T-2T:
> CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
> CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz
> 
> 3T-4T:
> CCD #1 = AVX1 = 4725mhz / FMA3 = 4600mhz
> CCD #2 = AVX1 = 4675mhz / FMA3 = 4550mhz
> 
> 9T-12T:
> CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
> CCD #2 = AVX1 = 4650mhz / FMA3 = 4525mhz
> 
> 13T-16T:
> CCD #1 = AVX1 = 4700mhz / FMA3 = 4575mhz
> CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz
> 
> All threads:
> CCD #1 = AVX1 = 4525mhz / AVX2 = 4450mhz / FMA3 = 4175mhz
> CCD #2 = AVX1 = 4450mhz / AVX2 = 4375mhz / FMA3 = 4100mhz
> 
> Game profile:
> CCD #1 = 4750mhz
> CCD #2 = 4600mhz
> 
> Highest ST clockspeed for 4 highest rated cores: (1375mv set)
> #1 = core3 @ 4975mhz (208 rating)
> #2 = core7 @ 4950mhz (212 rating)
> #3 = core8 @ 4875mhz (212 rating)
> #4 = core1 @ 4850mhz (203 rating)
> 
> Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set (upto 10% vdroop)
> CCD #1 = 4800mhz
> CCD #2 = 4650mhz
> 
> Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
> 1900:3800 = 643.93 Gflops
> 1933:3866 = ~616.5 Glops (some whea's)
> 2000:4000 = 199 Gflops (whea's and massive throttling)
> 
> 
> 
> Few takeaways:
> 
> Still limited to 1900 flck
> Second CCD on new 5950x is much stronger than my old 5950x
> My old 5950x have higher peak ST clockspeeds but worse average CCD quality. (few cores are worse which limits the average)
> *Main drawback*: Best 212 cores on this #1 5950x are core 7 and 8. This is bad for a few reasons.. The two last cores on a full CCD always have around 6 degrees higher temps. Some benchmarks/application always ignore CPPC (such as CPU-Z) and forces workload to core1, this is very bad since core1 is the worst one in entire CCD on this cpu. (you always wish for your best 212 cores to be core1)
> 
> View attachment 2542457
> 
> 
> Running a full hydra diagnostic with elevated voltages now, can post a comparison between these cpus with higher PPT budget later/tomorrow.
> Really hope my two last cpus are better than this.. Not happy with current sample i got.
> 
> Hopefully i get the two last ones from other vendor on Friday


Hydra diagnostic with higher voltages.

BG 2046 SUS









BG 2141 SUS










Veii said:


> Good writeup
> 2141 is still B2 silicon
> but not marked as such ~ or has B2 V/F tuning, but runs under wrong microcode
> 
> 
> Spoiler: EDIT
> 
> 
> 
> If you see something like this under 1203C, then it clearly is a new substrate
> Even if it says B0 on the box
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> B2 should've come since first October
> which is 2141 and up
> 2143 is just "guaranteed" B2 ~ but buggy without running on either 1.2.0.4A or 1.2.0.5


My recommend PBO CO numbers looks nothing like that, see pic above 

_edit_
goddamnit, shipment of two next cpus delayed to next week


----------



## Taraquin

Veii said:


> Good writeup
> 2141 is still B2 silicon
> but not marked as such ~ or has B2 V/F tuning, but runs under wrong microcode
> 
> 
> Spoiler: EDIT
> 
> 
> 
> If you see something like this under 1203C, then it clearly is a new substrate
> Even if it says B0 on the box
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> B2 should've come since first October
> which is 2141 and up
> 2143 is just "guaranteed" B2 ~ but buggy without running on either 1.2.0.4A or 1.2.0.5
> 
> This is unfortunate
> They had the ability to fix their DPM issue ~ even hardware bound
> But either where/are clueless or just forgot it and abandoned it


Does it matter that fclk above 1900 is a problem? It seems scaling is very limited above 1900, aida, dram calc test and a few games (SOTTR for instance) show some positive scaling, but y-cruncher, CB, linpack etc shows slight negative scaling (1-2% from 1900 to 2000) atleast on my WHEA 19 free setup, and terrible negative scaling on some setups like domdtxdissar's setup.


----------



## hazium233

KedarWolf said:


> If I run the below timings with tCWL at 12, I can run 10-1 on tRDWR and tWRRD.
> 
> Running it at 1 helps a bit with latency and bandwidth. I've tried other tWRRDs and 1 with this configuration seems best.
> 
> Edit: tCWL at 12 helps a bit rather than 14 too.


Right, you have a two clock difference between tCL and tCWL.

If you change your timing set tCWL = tCL = 14, you would need to have tWRRD = 3t for the same spacing between the bursts.

What I was wondering about is if anybody had managed tWRRD=2t while tCL=tCWL, with command 2T (or 1T) because I think I only found a couple examples with GDM on and since GDM cheats I don't think it counts. 

I think the only reason I could get it to post the other night was because Channel B was still using 3t.



Veii said:


> If too high, it overlapps. If too high it requires IOL delay to be added
> if too low, it causes training issues and can not recover
> 
> All these, tCWL, tRDWR, tPHY ~ depend on the ODM
> AMD enforces every board to behave identical, but there are still issues existing
> According to Buildzoid's experience, some boards hate specific values.
> According to Veii's experiences, some boards beyond tCL 20 or tCWL 20 rather ~ simply give up
> 
> tCWL 22 does not function (on the examples i've tested)
> It completely messes up memory training.
> That takes for account that memory training, rather IOL training actually is correct.
> 
> 
> 
> 
> 
> 
> 
> 
> In the absolute best case, once it switches away from 28-28, to 30-30
> (soo if Board Vendor do indeed put in changes in AMD CBS and then lock it away ~ looking at ASRock)
> If they do it correctly ~ it still fails miserably beyond tCWL 20. It just doesn't know what to use
> 
> Soo at this post, while tRDWR could be lower, it doesn't function as tCWL is broken
> Lowering one, to increase the other works even in cases where they are minimum values
> I do think it does try to balance things ~ but user can not correct t()PRE by themself
> And except trial and error, there seems to be no direct method of calculation.
> Because while there are options, your JEDEC and Veii's unorthodox guides ~ but end up to the same trial and error and watching the result
> 
> There are couple of issues here:
> ~ AMD FW completely goes haywire with predictions on 4966+ strap
> ~ the lack of user influence in shifting "faulty" tPHY predictions
> ~ the bios being IC unaware in it's predictions but rather follows XMP to some extend, or better PCB capability (tCCD_) but not IC capability
> ~ AMD does not follow JEDEC
> Last part is very important, but you maybe haven't noticed it
> 
> AMD doesn't follow JEDEC on many things
> This includes tREFI behavior and this also includes tPHY values (not fully)
> 
> Arshia and i had a (many) nice talks , but tREFI so also tRFC is not 8 or 9x postponable
> It's dependent on UrgRefSet value , how many it allows ~ soo tREFI is enforced on the user and tRFC has to adjust (4-6x peak)
> The range is huge, soo it's not a big deal, but it still has to set a point that AMD (on many parts) does what they want and define for correct.
> It does not follow JEDEC, not fully.
> 
> I'm happy that you understand and can quote it,
> soo i suggest also to grab the current JEDEC specs from my drive (if link gets found)
> but i also suggest not to 100% shape your experience based on what you read ~ but based on what you see.
> Good writeup


I don't understand it, that's the problem.  My background is not in engineering.

It seems also the motherboard switches to 2t more likely on warm repost, but I don't know if this is due to the DFE Training Read and Write enabled. It seems often this motherboard does not fully retrain despite Memory Clear - Enabled. If I do 3733, then back to 3600 it leaves tWRRD 3t until reboot, then it tries 2t again.

edit: I also do not know if it really expects to change tCWL = 14 for this XMP (CL=16), in which case the 2t on A or 3t on B is definitely fine and probably safe. It will do that if CWL is on Auto, but I had enforced 16t.

I found something about DQS alignment, but don't know when it is allowed to cheat forward or back, it was just a diagram, and I am not sure that the examples were supposed to show valid or just the example of how DQS training causes proper alignment.

At least in GDM. But I am losing my desire to check GDM because setting 2T magically aligns tPHYRDL 26/26 for all these speed steps.



Audioboxer said:


> tWRRD 2 seems fine! Also took dom's advice of "this is OC.net" and reduced my tRAS/tRC again lol.


Right, 2t is fine for you because tCL > tCWL by 1 clock. tCWL 13t is impossible, so can't check when they are equal in this case.


----------



## Audioboxer

My next project for a bit of fun, I'll name it "Help, I live in a desert and have no air conditioning".

Going to see the best that can be done under 1.35v. Just checking quick potential for primaries.

*edit* - And maybe one for the "extra warm" days in the 1.2xv range


----------



## Audioboxer

Audioboxer said:


> View attachment 2542536
> 
> 
> My next project for a bit of fun, I'll name it "Help, I live in a desert and have no air conditioning".
> 
> Going to see the best that can be done under 1.35v. Just checking quick potential for primaries.
> 
> *edit* - And maybe one for the "extra warm" days in the 1.2xv range
> 
> View attachment 2542543












No idea where tRFC is going to need to land at 1.28v but this kit has some crazy thermal capabilities lol. Will 25 cycle next but it's looking like reasonably tight timings might be OK even this low.


----------



## Taraquin

Audioboxer said:


> View attachment 2542536
> 
> 
> My next project for a bit of fun, I'll name it "Help, I live in a desert and have no air conditioning".
> 
> Going to see the best that can be done under 1.35v. Just checking quick potential for primaries.
> 
> *edit* - And maybe one for the "extra warm" days in the 1.2xv range
> 
> View attachment 2542543


Omg that binning. I need 1.47V for 15 flat 1T on 3800, maybe I could manage a bit lower if I set a lower rfc.


----------



## Audioboxer

Preliminary findings:

I ran this profile first with tRTP at 5 and tWR at 10 with voltage 1.28v. Got a single error 6 on like cycle 7. Veii's notes suggest on its own likely just +0.01v needed. I did that and changed tRTP to 6 and tWR to 12. We've got a pass. It's very likely 1.28v is just sadly not going to work, but I will try it again with the change to tRTP/tWR.

Other thing I find interesting is how many secondary timings will happily scale down even at voltage this low. Suggests a lot of them are purely on silicon. Those that struggle include, tWTRL, needs to be at 10, 8 boots but is very unstable. tWTRS, not budging from 4 unless it's at higher voltage. Then, finally, tWRRD, doesn't boot at 2. Clearly needs a higher voltage, 2 works at 1.55v.

Obviously tRFC scales with voltage as well, I'm quite impressed 172 was okay at 1.29v. Will try and creep under 170.

1T no problem at all, just the stupid 28/28 on an even tCL.

There might even be a chance tRCDRD will drop to 15, but I've never liked how it looks running it lower than tCL lol.

Once I've got this profile 100% locked in, I'll jump back up to 1.34v and make sure tCL 15 is OK.


----------



## Reaxer

Audioboxer said:


> Then, finally, tWRRD, doesn't boot at 2. Clearly needs a higher voltage, 2 works at 1.55v.


It could also be what hazium233 said a couple posts back 


hazium233 said:


> If you change your timing set tCWL = tCL = 14, you would need to have tWRRD = 3t for the same spacing between the bursts.
> 
> What I was wondering about is if anybody had managed tWRRD=2t while tCL=tCWL, with command 2T (or 1T) because I think I only found a couple examples with GDM on and since GDM cheats I don't think it counts.


----------



## Veii

Audioboxer said:


> 1T no problem at all, just the stupid 28/28 on an even tCL.


I'm rushing with new news, considering there is much to do
*But figured out (on DR) how to work with tPHY, finally.*

I need a testing rabbit. 1T is not perfectly nailed, hence this kit struggles to even run XMP ~ but playing with setup timings. *tCKE rang*e seems to be nailed too, but with an *
(*use -1 of the current SR scale*)






What i play with atm (ignore SOC & VDDG ^^)
Also what i got today







No new updates till likely 20th of January. RL issues with postal service who lost two packages insured as 3800€  & business travel in/for couple of days
Bit busy, but figured yesterday this out

*For DR it does not wiggle on higher than 32ohm procODT, or 30ohm lowest* (get your procODT at 30 or 32 if you want high MCLK)
This was at 1.62v
WR/1 won't post bellow 1.57

The issue is board design (firmware). My board won't post if IOL is predicted as 32, but will always if i keep prediction bellow or peaking 30
It posts at best 28-30, and *you can tame it back by decreasing cLDO_VDDP by 5-10mV or drop ClkDrvStr fully , sometimes it needs a drop to 20ohm even*
It's in *investigation*, *if 120ohm ClkDrvStr with 880mV* (or lower cLDO_VDDP) , *oor higher cLDO_VDDP for potentially higher MCLK boot, but with 20ohm ClkDrvStr makes more sense*
^ both change up to VDD18 and this also changes procODT range of what "can post". More to it when i have more time , but want a testing rabbit too proof control ability of tPHY 
Also "you *do not need a cold boot*" ~ but the board will cold boot if it needs to change tPHY. Sometimes it will not need a cold boot and accept it perfectly.
Meaning = ZenTimings is perfect in it's function, and it's the powering. *It only increases tPHY/IOL to help stabilize the dimm on "overcurrent"*. While it's a trace and ODM design thing, it has nothing to do with boards layout or layering (technically does but not fully, only the FW department is to blame. Not the HW department)


Taraquin said:


> Does it matter that fclk above 1900 is a problem? It seems scaling is very limited above 1900, aida, dram calc test and a few games (SOTTR for instance) show some positive scaling, but y-cruncher, CB, linpack etc shows slight negative scaling (1-2% from 1900 to 2000) atleast on my WHEA 19 free setup, and terrible negative scaling on some setups like domdtxdissar's setup.


Let me reuse this picture. I forgot the source sadly, but it was on this thread








Still think it's slightly flawed, but can not tame the heat of my CPU to proof it and remake a better one. Soon ~ have to build a loop for me later, by the MSI 1080ti EK, i got (also learn nickel and black nickel plating)
ManniX-ITA (maker of the one bellow) ~ showed scaling in an AVX and Cache intensive benchmark. While difficulty of monero keeps increasing, it's not skyrocketing that much per day









Tho all that, i still think that AVX2 accelerators do not scale by FCLK ~ but couldn't test
Soo neither LinX nor SiSandra (some of the tests) are likely a good option to show it.
It does wiggle slightly by memory timings ~ which BuildZoid could also see.
But i personally can not take them for serious. We will see. Can't give out good charts so far either. (Timespy did show scaling)ä
========================================
Buut also *found a potentially new method to fix CO's*















EDIT:








(overboost)

But i'm leaking a bit much, for a post that should be a teaser
More information later when i fix RL issues with the PC parts. We maybe need to put a lawyer into this process. Austria's post service is embarrassing itself, another of the dozens times already
Soo more information later.

*I think we nailed down the TM5 timeout issue to be purely windows 11 related now*
Neither storage, or page files
No sun eruptions that flip random bits
No heat or sleeping issues (they exist but are irrelevant)
no overboost or instability issues, as Intel DDR3 is affected too.

Purely scheduler based and Win11 exclusive


Code:


Enable idle: (less responsive, lowers temperature)
powercfg -setacvalueindex scheme_current sub_processor 5d76a2ca-e8c0-402f-a133-2158492d58ad 0
powercfg -setactive scheme_current

Disable idle: (more responsive, raises temperature)
powercfg -setacvalueindex scheme_current sub_processor 5d76a2ca-e8c0-402f-a133-2158492d58ad 1
powercfg -setactive scheme_current

Use this mid testing, to enforce a 100% load without any load active. This will force dlDO to balance things and enforce the CPU to run at it's highest allcore strap (can be used to see what dLDO does)
*This is not healthy* for gaming, even tho DPC latency improves a lot (down to 18-20ys) instead 100ish as known that "ryzen is not for gaming" ~ soo similar to what CPPC off brings
This trick *will resolve any timeout issues with TM5 ~ but be sure to re'set it back*. It *needs no reboot but task manager or hydra become useless* with it 
*Temporary workaround* till found what service or part of Win11 is causing this timeout issue ~ as it's AMD independent.

EDIT 2:
Also with this trick Aida64 Memory, is perfectly stable. Does not wiggle even 0.1ns
Same for cache on Windows 11 seem to be fixed (still on energy efficient mode, balanced powerplan ~ but modified with this)
Sadly the downsides are, very high continuously set voltage ~ as it imagines a constant SSE allcore load and pushes VID up.
Yet great for shaping CO curve between CCDs and between cores inside same CCD. Good to reshape already stable CO, and see what dLDO really does 
Just it's i thin not healthy, as constant set voltage is kind of high without wiggle room. Would be very cautious on dual CCD units, because AVX2/FMA3 loads on 1.32+ volts is not healthy


----------



## Audioboxer

Looks like mission complete for tCL16, I doubt anything is getting tighter than that at 1.29v. Decent showing from tRFC, I guess I could try 312.

@Veii Trying doing some testing in Windows 11 diagnostic startup. It pretty much stops every background service it can. Just to see if timeouts stop. Then you know its a service!


----------



## Veii

Audioboxer said:


> @Veii Trying doing some testing in Windows 11 diagnostic startup. It pretty much stops every background service it can. Just to see if timeouts stop. Then you know its a service!


What we've found is, that it appears to be putting it to idle states (forcing) ~ after a very long period of time
It doesn't react to Page File sizes, but seems to be between the hard-drive and the CPU
Something with the scheduler is messed up and it enforces energy savings after 5-6 hours

That, or something in the cosmic space is odd and we all keep getting sunflares and have flipped bits
I doubt the later, and it's neither OTA microcode updates, nor storage or house installation
As DDR3 Sandy Bridge does it on XMP, mates dual PC (wife's) with XMP and his personal timings do it.
And it's not capacity related, so also not powerplan related.

The only time he had success, is by loading the CPU (miner) and preventing it to go to idle after some time
Soo it looks like some energy consumption mechanism or the tool itself (memory leak) happens after some time
But since it happens on 4GB and 64GB , it doesn't look to be config related (else it wouldn't pass ever, period) and it is not architecture, house installation or time base related (no sun flares xD)

Whatever it is, this trick fixes it - but i'd say it's more of an exploit that was discovered by accident and was rather for intel based units.
Ryzens need suspension and idle states, to function on higher voltage than Intel's counterparts
I test right now dailing it, but it's not a good idea to pretty much bypass idle states and run something near the lines of an EDC bug ~ daily
With CO's i'm sitting near 1.32-1.35v
But i wouldn't happily run y-cruncher with this, unless AVX2 does pull with their offset it down to 1.2v range


----------



## byDenoso

Anyone know how to stop throttling using EDC bug?


----------



## UnchiuNarcis

Hello everybody!
I just bought a G skill kit *G-Skill Trident Z Royal 3600C16Q-32GTRS 4x8 *
I have a crosshair viii formula and a ryzen 5900x
At the moment I am on 3800 mhz safe preset fclk 1900 dram 1.5v soc 1.2v pll 2.0v vtt ddr 0.75v 
The problem is that I can't get it stable no matter what, there must be something that I am doing wrong maybe? I still do not understand where should I put trfc alt because I see TRFC2 and TRFC 4 and I read somewhere that it is wrong to put it there.
I have also tried 3600 mhz fast preset from DRAM Calculator, but it's still not working, doesn't even boot.


----------



## Veii

byDenoso said:


> Anyone know how to stop throttling using EDC bug?


can't
package throttle is by design
an exploit doesn't transfer over between generations


UnchiuNarcis said:


> where should I put trfc alt


Alternative tRFC
DRAM calculator people can use tRFC(1) for everything

Either,/Or
Alternative value


----------



## UnchiuNarcis

Veii said:


> can't
> package throttle is by design
> an exploit doesn't transfer over between generations
> 
> Alternative tRFC
> DRAM calculator people can use tRFC(1) for everything
> 
> Either,/Or
> Alternative value


thank you
can you help me please to make the memory more stable? there still are some things in the dram calculator in the advanced tab that I do not know where to enter in my bios and I searched for them everywhere ( example VREF CHA CHB or memory interleaving tweaks / PMU trainig ) and maybe that is why I'm not stable?


----------



## Veii

UnchiuNarcis said:


> thank you
> can you help me please to make the memory more stable? there still are some things in the dram calculator in the advanced tab that I do not know where to enter in my bios and I searched for them everywhere ( example VREF CHA CHB or memory interleaving tweaks / PMU trainig ) and maybe that is why I'm not stable?


DRAM Calculator is for Matisse (3000 series)
CPU voltages do not work anymore
Presets either run or don't run
Modifying them slightly, breaks their tested good efficiency
It makes very little sense to copy them and very little sense to apply them

NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking... this is it's thread
Not [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread 
Zen DDR4 OC Leaderboards only thing i can potentially recommend as an "orientation point". User results

Options are ASUS Crosshair specific and miss on other boards
AMD CBS (most options) is lacking for consumers ~ but always is configured correctly on the latest bioses
Tool is outdated since around ~2 years. Used 2017-2019, we have 2022, outdated since mid-end of 2020 when Vermeer (5000 series) came out.
We sit in a pandemic since 2019. Time flies


----------



## Luggage

Agesa 1206 incoming 









ASUS ROG X570 Crosshair VIII Overclocking &amp...


After installing the above mentioned driver I gained about 100p in cb23 Mt (win11), st unchanged. Post 10000?! Which driver ?




www.overclock.net


----------



## Audioboxer

Luggage said:


> Agesa 1206 incoming
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ASUS ROG X570 Crosshair VIII Overclocking &amp...
> 
> 
> After installing the above mentioned driver I gained about 100p in cb23 Mt (win11), st unchanged. Post 10000?! Which driver ?
> 
> 
> 
> 
> www.overclock.net


That was quick, hopefully the voltage bug is gone.


----------



## Taraquin

Any idea what ram this is? I`m helped my nephew building a gaming rig, he had some parts from earlier:
5600X
GB B450 aorus pro
2x16 Kingston fury 3600cl18 (KF436C18BBK2/32)
Updated to agesa 1.2.0.3b

Thaiphoon reports them as Hynix A single rank. I didn`t think that existed? 
At 3800 2T they do, lower wr\rtp, wtr, rc and rdwr may work, but get a few error 5 and 10 i TM5 at round 2 using usmus1:
16 21 19 35 56
5\7 rrds
20 faw
16\8 wr\rtp
4\12 wtr
560 rfc
rdwr 10
wrrd 3
1.43V

They sort of behave like some Hynix-kits as they don`t like low rp, but rfc is higher than Hynix tends to do (440-520 on CJR\DJR at 3800), they also seem similar to Samsung D and Micron E since they don`t like low rfc and rcdrd. Could it be Samsung A or Hynix MJR? MJR is not suposed to do rfc sub 600 at 3800 so I doubt that.


----------



## Audioboxer

lol, it's mad how a tCL16 profile at 1.28v isn't too far off a tCL13 profile at 1.55v.

*edit* - tRFC still showing signs of life as low as 160ns










*edit2* - 296 seems to be where more obvious issues start occurring. Probably likely a longer 304 test fails, but I'll try and 25 cycle it.


----------



## Taraquin

Audioboxer said:


> View attachment 2542703
> 
> 
> lol, it's mad how a tCL16 profile at 1.28v isn't too far off a tCL13 profile at 1.55v.
> 
> *edit* - tRFC still showing signs of life as low as 160ns
> 
> View attachment 2542708
> 
> 
> *edit2* - 296 seems to be where more obvious issues start occurring. Probably likely a longer 304 test fails, but I'll try and 25 cycle it.


Tip: RP requires a bit of voltage, try 15 or 16 and you may be able tobdo 1.27V or 1.26V


----------



## umea

where did GSKill confirm that the 4000c14 bin is no longer being made? it's tempting me to get it since it's actually on sale for 560CAD right now... but i dont really need it and the performance gains are so marginal.... and next gen cpus probably won't accept ddr4 at all.... urgh


----------



## Audioboxer

Taraquin said:


> Tip: RP requires a bit of voltage, try 15 or 16 and you may be able tobdo 1.27V or 1.26V


I somewhat worked in reverse on these, first thing was 3 cycling primaries only with everything else on auto to see what had potential. 1.27v caused errors within a 3 cycle with 16-16-16-16. 1.28v passed. I later found out during a 25 cycle I got a single error on 6. Lined up with Veii's notes about needing 0.01v added.

1.29v cleared up that single error and at this point I then tried dropping tRP. So in my estimation it's really tCL that predominantly needs 1.29v and the rest just fell into place.



umea said:


> where did GSKill confirm that the 4000c14 bin is no longer being made? it's tempting me to get it since it's actually on sale for 560CAD right now... but i dont really need it and the performance gains are so marginal.... and next gen cpus probably won't accept ddr4 at all.... urgh


I'll need to find it again but there was a G.SKILL customer service response posted to Reddit saying to expect 4000C16 to be the bin getting produced going forward due to what appeared to be an explanation that Samsung isn't either binning for 4000C14 again or they're using what they can from those bins now for DDR5.

Wouldn't surprise me given shortages and the tech world drifting to focussing on DDR5 now. I can't find the DR in stock anywhere, just the SR.

Shame, the DR would be a nice bin to see come down in price a bit as more moved to DDR5 and there was less demand for DDR4.


----------



## umea

Audioboxer said:


> I somewhat worked in reverse on these, first thing was 3 cycling primaries only with everything else on auto to see what had potential. 1.27v caused errors within a 3 cycle with 16-16-16-16. 1.28v passed. I later found out during a 25 cycle I got a single error on 6. Lined up with Veii's notes about needing 0.01v added.
> 
> 1.29v cleared up that single error and at this point I then tried dropping tRP. So in my estimation it's really tCL that predominantly needs 1.29v and the rest just fell into place.
> 
> 
> 
> I'll need to find it again but there was a G.SKILL customer service response posted to Reddit saying to expect 4000C16 to be the bin getting produced going forward due to what appeared to be an explanation that Samsung isn't either binning for 4000C14 again or they're using what they can from those bins now for DDR5.
> 
> Wouldn't surprise me given shortages and the tech world drifting to focussing on DDR5 now. I can't find the DR in stock anywhere, just the SR.


I see, I definitely believe you as I've seen the stock quickly dwindling on every site that I could find to the point that I can literally only find it in stock on canada's newegg. I just don't know if I can justify the price for such marginal increases, especially since it seems like AM5 + next gen intel will be going DDR5 only. If I hadn't already spent a good amount on my current bin (which btw, has dropped 100 dollars since I bought it >.>) I definitely would be more open to it. Just sucks that the 4266 17-18-18-38 bin is so weird and can't hit 14 flat.


----------



## Audioboxer

umea said:


> I see, I definitely believe you as I've seen the stock quickly dwindling on every site that I could find to the point that I can literally only find it in stock on canada's newegg. I just don't know if I can justify the price for such marginal increases, especially since it seems like AM5 + next gen intel will be going DDR5 only. If I hadn't already spent a good amount on my current bin (which btw, has dropped 100 dollars since I bought it >.>) I definitely would be more open to it. Just sucks that the 4266 17-18-18-38 bin is so weird and can't hit 14 flat.


I'm going mad right now trying to find the Reddit post again, I've convinced myself it wasn't on r/Overclocking and it might have been r/AMD or even r/PCGaming. I was just browsing, seen it along with the chat log from CS and thought oh, that's interesting.

CS obviously isn't an official statement or anything, but it's clear DR stock has dried up and I guess G.SKILL are always going to be at the mercy of what Samsung are doing. Binning for this 4000 14-15-15-15 kit must be expensive.

And speaking of being expensive, unless you have money to burn I wouldn't buy it now. 3D cache is a total bust so WHEA issues with FCLK are never going to be fixed. We're stuck where we are until AM5 and that will really be the time for DDR5. If 3D cache was coming to a 5900x or 5950x and AMD had improved their IMC I'd say this bin could be nice for sticking with AM4 for another few years.

Now though, I'd say firesale price and that's unlikely to ever happen due to scarcity.


----------



## umea

Audioboxer said:


> I'm going mad right now trying to find the Reddit post again, I've convinced myself it wasn't on r/Overclocking and it might have been r/AMD or even r/PCGaming. I was just browsing, seen it along with the chat log from CS and thought oh, that's interesting.
> 
> CS obviously isn't an official statement or anything, but it's clear DR stock has dried up and I guess G.SKILL are always going to be at the mercy of what Samsung are doing. Binning for this 4000 14-15-15-15 kit must be expensive.
> 
> And speaking of being expensive, unless you have money to burn I wouldn't buy it now. 3D cache is a total bust so WHEA issues with FCLK are never going to be fixed. We're stuck where we are until AM5 and that will really be the time for DDR5. If 3D cache was coming to a 5900x or 5950x and AMD had improved their IMC I'd say this bin could be nice for sticking with AM4 for another few years.
> 
> Now though, I'd say firesale price and that's unlikely to ever happen due to scarcity.


Yeah if it dropped to like 400CAD I would buy it in a heartbeat, since I could definitely sell my mangled kit for 250-300CAD probably. But for 560 it's still a bit too pricey. I agree with you there btw, if there was a 3d update coming to the 5950x or 5900x I would have grabbed it because the performance increase on it would have been pretty ridiculous. Sadly though since I already have a 5900x there's no reason for me to bother with a 5800x3d. Only way I can see it _maybe_ being worth it is using it with a 12900KS...


----------



## Audioboxer

umea said:


> Yeah if it dropped to like 400CAD I would buy it in a heartbeat, since I could definitely sell my mangled kit for 250-300CAD probably. But for 560 it's still a bit too pricey. I agree with you there btw, if there was a 3d update coming to the 5950x or 5900x I would have grabbed it because the performance increase on it would have been pretty ridiculous. Sadly though since I already have a 5900x there's no reason for me to bother with a 5800x3d. Only way I can see it _maybe_ being worth it is using it with a 12900KS...


Yeah, it's proper luxury pricing at the moment and it's stock just dropped in value due to a terrible 3D cache announcement. I thought 3D cache was going to save me as well lol...

By the time the new AMD CPUs launch and are easily available, so probably some point in 2023, DDR5 will likely have matured a bit as well. This just makes it a bad idea to dump a lot of money into DDR4 at the moment unless you really want to or you were buying a new system knowing you'll be happy staying on 5xxx and DDR4 for a few years.

In other news, the AGESA 1.2.0.6 betas starting to float around still have the 1.425v voltage cap above 140 EDC. Looks like AMDs parting gift to us this generation is to try and gimp OCing performance for absolutely no reason...


----------



## Audioboxer

Seriously doubted this run would pull through, but it managed it, that's a tRFC of 160ns at 1.29v  👀


----------



## KedarWolf

Audioboxer said:


> View attachment 2542727
> 
> 
> Seriously doubted this run would pull through, but it managed it, that's a tRFC of 160ns at 1.29v  👀


Could you show an AIDA run?

Edit: And is it OCCT WHEA free?


----------



## Audioboxer

KedarWolf said:


> Could you show an AIDA run?
> 
> Edit: And is it OCCT WHEA free?


There is an AIDA here with the slightly higher tRFC [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

Will re-run it again for 160ns, but I don't expect much difference in benching.

Working on tCL 15 at 1.35v just now.

And no WHEA, can memory cause WHEA?

*edit* - This will probably be the tCL 15 profile I try to 25 cycle










Advice on tWRRD was right  When tCWL ≠ tCL, it seems tWRRD can be dropped from 3 to 2 on DR.


----------



## Audioboxer

Oh well, that went smoothly, tCL15 done at 1.35v. tRFC could maybe go a bit lower, but I think that's me had my fun with low voltage profiles!

As noted above tWRRD will happily go to 2 if tCL and tCWL are different. tWTRL 8 at least boots at 1.35v, but it's unstable. I'd guess 1.37~1.4v might be needed.

I found Anta's comment about tRFC



> Samsung B-Die tRFC(approximately):
> 1.20V-211ns
> 1.30V-178ns
> 1.35V-160ns
> 1.40V-150ns
> 1.45V-140ns
> 1.50V-136ns
> 1.55V-120ns
> 1.60V-110ns


So 1.29 at 160s and 1.35 at 147ns are doing great!


----------



## hazium233

Taraquin said:


> Any idea what ram this is? I`m helped my nephew building a gaming rig, he had some parts from earlier:
> 5600X
> GB B450 aorus pro
> 2x16 Kingston fury 3600cl18 (KF436C18BBK2/32)
> Updated to agesa 1.2.0.3b
> 
> Thaiphoon reports them as Hynix A single rank. I didn`t think that existed?
> At 3800 2T they do, lower wr\rtp, wtr, rc and rdwr may work, but get a few error 5 and 10 i TM5 at round 2 using usmus1:
> 16 21 19 35 56
> 5\7 rrds
> 20 faw
> 16\8 wr\rtp
> 4\12 wtr
> 560 rfc
> rdwr 10
> wrrd 3
> 1.43V
> 
> They sort of behave like some Hynix-kits as they don`t like low rp, but rfc is higher than Hynix tends to do (440-520 on CJR\DJR at 3800), they also seem similar to Samsung D and Micron E since they don`t like low rfc and rcdrd. Could it be Samsung A or Hynix MJR? MJR is not suposed to do rfc sub 600 at 3800 so I doubt that.


Could be Hynix 16Gbit AJR.

They are up to 16Gbit CJR though, sometimes thaiphoon doesn't show revision correctly because that is rarely programmed in the dimms.


----------



## FHWL_

Thanks to this amazing thread, I've reached a stable 3800/1900 @1.41V OC on my BL16G32C16U4BL E-Die 3200 kit.
I've struggled for a couple days (and nights) to get it working. 










This OC gave me _one _WHEA #19 error when using AIDA'64 stresstest (CPU, FPU, Cache, Memory & GPU). But HCI passed 350%, OCCT no error's, TM5 anta777 for 2h no errors. So I guess it's stable?

One thing I'm unsure about is my VDDG IOD timings at 1.06V (trying to lower them to 1.046 - but no clue what is regarded as safe 24/7).

Suggestions (also on improving the OC)?


----------



## Audioboxer

FHWL_ said:


> Thanks to this amazing thread, I've reached a stable 3800/1900 @1.41V OC on my BL16G32C16U4BL E-Die 3200 kit.
> I've struggled for a couple days (and nights) to get it working.
> View attachment 2542780
> 
> 
> 
> This OC gave me _one _WHEA #19 error when using AIDA'64 stresstest (CPU, FPU, Cache, Memory & GPU). But HCI passed 350%, OCCT no error's, TM5 anta777 for 2h no errors. So I guess it's stable?
> 
> One thing I'm unsure about is my VDDG IOD timings at 1.06V (trying to lower them to 1.046 - but no clue what is regarded as safe 24/7).
> 
> Suggestions (also on improving the OC)?


IOD is absolutely fine, bump your VSOC to 1.125-1.15v and that will likely stabilise FCLK. CCD to 0.95v as well even.


----------



## FHWL_

So after a night of stresstesting w/ the old setup (ram at 1.41V) I got this:









Slightly better latency (run w/ HWInfo in the background on - so might be tighter). Only the L3 cache speeds are down a little.
tRCDRD 18 does boot if I set all tertiary timings on auto, but can't get it stable with these settings. Also with these settings lowering tRFC to 540 didn't post.
Does increasing the soc voltage improve this? (Read somewhere that it takes out of the powerbudget for the CPU + that the X570-F strix doesn't like soc above 1.1 here: Leserartikel - AMD Ryzen - RAM OC Community)

Are there still (obvious) latency gains to be made here?


----------



## Taraquin

FHWL_ said:


> Thanks to this amazing thread, I've reached a stable 3800/1900 @1.41V OC on my BL16G32C16U4BL E-Die 3200 kit.
> I've struggled for a couple days (and nights) to get it working.
> View attachment 2542780
> 
> 
> 
> This OC gave me _one _WHEA #19 error when using AIDA'64 stresstest (CPU, FPU, Cache, Memory & GPU). But HCI passed 350%, OCCT no error's, TM5 anta777 for 2h no errors. So I guess it's stable?
> 
> One thing I'm unsure about is my VDDG IOD timings at 1.06V (trying to lower them to 1.046 - but no clue what is regarded as safe 24/7).
> 
> Suggestions (also on improving the OC)?


You can try 5/7/20 on rrd/faw or 4/6/16. Wr/rtp might do 12/6 and wtr might do 3/8 or 3/6, rfc 544. You may get away with a bit lower soc/iod voltage.


----------



## Reaxer

FHWL_ said:


> So after a night of stresstesting w/ the old setup (ram at 1.41V) I got this:
> View attachment 2542824
> 
> 
> Slightly better latency (run w/ HWInfo in the background on - so might be tighter). Only the L3 cache speeds are down a little.
> tRCDRD 18 does boot if I set all tertiary timings on auto, but can't get it stable with these settings. Also with these settings lowering tRFC to 540 didn't post.
> Does increasing the soc voltage improve this? (Read somewhere that it takes out of the powerbudget for the CPU + that the X570-F strix doesn't like soc above 1.1 here: Leserartikel - AMD Ryzen - RAM OC Community)
> 
> Are there still (obvious) latency gains to be made here?


















This is what I managed with that kit, was not fully optimized yet, but I got some B-die to play with haha
Voltages could probably go lower.








1T GDM off without setup timings ran fine on that kit for me. tRP + tRAS aren't tRC here though


----------



## nada324

Hey guys, finally i did replaced my old X470 aorus gaming 7 for the X570 asus dark hero, what PROC ODT do you guys use on this one?

Using Vermer CPU


----------



## Taraquin

nada324 said:


> Hey guys, finally i did replaced my old X470 aorus gaming 7 for the X570 asus dark hero, what PROC ODT do you guys use on this one?
> 
> Using Vermer CPU


If single rank 28-37, if dual rank usually 32-48. Some ram kits like Hynux CJRbprefers higher compared to B-die.


----------



## sonixmon

blodflekk said:


> Am I the only one that come here daily and reads through all the posts, but doesn't comment because I don't feel qualified to? 😅


Oh, I comment but am definitely not qualified! 🤣 

Have gained a tremendous amount of information (some turned into knowledge LOL). Much respect for the smart folks here that really help us novices when it comes to RAM OC.


----------



## Veii

FHWL_ said:


> Does increasing the soc voltage improve this? (Read somewhere that it takes out of the powerbudget for the CPU + that the X570-F strix doesn't like soc above 1.1 here: Leserartikel - AMD Ryzen - RAM OC Community)


Artificial limits are set for bellow 1.1v SOC @ 3600MT/s
Everything beyond it is called overclocking and will eat into the boosting budget
SOC eats into to EDC budget, and cache boost is controlled by such 

The artificial limit exists, to make ryzen more efficient, hence maximum "allowed to request VID" is lower with low EDC limit
Its an electric current limit, not like PPT a powersuply and TDP limit

Meaning,
If you want to OC, extend your first stage limiters
Most of it was written in the core cycler thread
If you want to build your CO's, also do such on a free limiter
Else you limit already limited voltage


----------



## Bix

Speaking of novices, a bit of help please... Just updated to the new AGESA 1.2.0.5 and noticed that I'm getting around 0.6-0.7ns slower AIDA latency on average. I've since run TM5 3 times - first produced one error 5 at cycle 11, second passed with no errors and third produced another single error 5 at cycle 9. 2 runs of Karhu errored first at 1009% then second at 910%.

Any ideas how best to proceed? This profile was rock solid with 1.2.0.3b - I retested multiple times with both TM5 and Karhu when testing performance with different CPU voltages. Could just reflash 1.2.0.3b but @Veii mentioned that the CPU microcode can't be rolled back so not sure if that would fix it.

Edit: CPU currently at stock with PBO disabled and LLC etc on Auto.


----------



## Veii

Bix said:


> Could just reflash 1.2.0.3b but @Veii mentioned that the CPU microcode can't be rolled back so not sure if that would fix it.


CPU microcode can be flashed back
But CPU boosting table changes and voltage behavior changes. Soo if internal FIT module updates, it's permanent and very had to bug out and force reflash/recovery

Nobody knows if AGESA blob had psp-fw or fit changes with it
It can happen at any agesa update, at any time
But the problem likely is, if you run things on auto

Unstable memory can mean many things
This includes unstable cores
Soo start with checking loadline's and see if you are over 4 loops y-cruncher, stable
Then later work on your memory

They changed the boosting table, so it can be on very bad samples, that they need 5-10mV positive vcore offset


----------



## Bix

Veii said:


> CPU microcode can be flashed back
> But CPU boosting table changes and voltage behavior changes. Soo if internal FIT module updates, it's permanent and very had to bug out and force reflash/recovery


Right, thanks. Are those those voltage behaviour changes likely to mean a change of VDDP/VDDG/VSOC is needed or should I focus on my RTTs/CAD BUS? Apologies for the need for spoon-feeding🙂

Edit: OK, currently running y-cruncher. Passed 4 iterations ok earlier today but will re-run a few times with reboots to be sure. Thanks again!


----------



## hazium233

It seems maybe I can get 26/26 with GDM via high cldo vddp. I am not sure why this didn't work the first time (maybe I forgot to set MRC Fast Boot, don't know).

Requires 995 it seems:










2T does 26/26 at much much lower vddp, as I already knew. Makes little sense to me.

I had already seen 1.39v dram increased Channel B to 28 for 28/28. Dram voltage down didn't seem to work (to 1.26). CAD, Proc, high timings...


----------



## MrHoof

Just changing VDDP trying to fix a missmatch wont work. You have to force a retraining in some way or it wont do anything.
I used to do this, TRDWR autos to 8 but I normaly run 7, setting it to auto from 7 will always cause a retrain for me.


----------



## domdtxdissar

domdtxdissar said:


> So i have received the first of my 3 new 5950x's
> Sadly the first one missed the new B2 stepping by a few weeks, but i can share preliminary silicon quality stats:
> 
> All tests was run at stock bios settings --> PBO disabled and "auto" LLC which is pretty weak on this MSI UNIFY X MAX motherboard. (upto 10% vdroop under heavy load)
> All stock diagnostic voltages in hydra.
> 
> 
> 
> Spoiler: My original 5950x stats -> BG 2046 SUS
> 
> 
> 
> Asus tool = "116 silicon quality" and "4381mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4525mhz --> 4.05 rating = *Golden CCD*
> CCD #1 = 4325mhz --> 3.87 rating = *Bronze CCD*
> 
> 1T-2T:
> CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
> CCD #2 = AVX1 = 4725mhz / FMA3 = 4600mhz
> 
> 3T-4T:
> CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
> CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz
> 
> 9T-12T:
> CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
> CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz
> 
> 13T-16T:
> CCD #1 = AVX1 = 4675mhz / FMA3 = 4550mhz
> CCD #2 = AVX1 = 4500mhz / FMA3 = 4375mhz
> 
> All threads:
> CCD #1 = AVX1 = 4475mhz / AVX2 = 4400mhz / FMA3 = 4125mhz
> CCD #2 = AVX1 = 4325mhz / AVX2 = 4250mhz / FMA3 = 3975mhz
> 
> Game profile:
> CCD #1 = 4725mhz
> CCD #2 = 4550mhz
> 
> Highest ST clockspeed for 4 highest rated cores: (1375mv set)
> #1 = core1 @ 4925mhz (212 rating)
> #2 = core3 @ 4900mhz (208 rating)
> #3 = core5 @ 4875mhz (212 rating)
> #4 = core7 @ 4875mhz (203 rating)
> 
> Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set (upto 10% vdroop)
> CCD #1 = 4700mhz
> CCD #2 = 4600mhz
> 
> Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
> 1900:3800 = 642.98 Gflops
> 1933:3866 = ~400 Glops (whea's and massive throttling)
> 2000:4000 = not even attempted
> 
> 
> 
> 
> 
> 
> Spoiler: My 5950x #1 out of 3 -> BG 2141 SUS
> 
> 
> 
> Asus tool = "117.5 silicon quality" and "4394mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4575mhz --> 4.11 rating = *Platinum CCD*
> CCD #1 = 4475mhz --> 4.02 rating = *Golden** CCD*
> 
> 1T-2T:
> CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
> CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz
> 
> 3T-4T:
> CCD #1 = AVX1 = 4725mhz / FMA3 = 4600mhz
> CCD #2 = AVX1 = 4675mhz / FMA3 = 4550mhz
> 
> 9T-12T:
> CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
> CCD #2 = AVX1 = 4650mhz / FMA3 = 4525mhz
> 
> 13T-16T:
> CCD #1 = AVX1 = 4700mhz / FMA3 = 4575mhz
> CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz
> 
> All threads:
> CCD #1 = AVX1 = 4525mhz / AVX2 = 4450mhz / FMA3 = 4175mhz
> CCD #2 = AVX1 = 4450mhz / AVX2 = 4375mhz / FMA3 = 4100mhz
> 
> Game profile:
> CCD #1 = 4750mhz
> CCD #2 = 4600mhz
> 
> Highest ST clockspeed for 4 highest rated cores: (1375mv set)
> #1 = core3 @ 4975mhz (208 rating)
> #2 = core7 @ 4950mhz (212 rating)
> #3 = core8 @ 4875mhz (212 rating)
> #4 = core1 @ 4850mhz (203 rating)
> 
> Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set (upto 10% vdroop)
> CCD #1 = 4800mhz
> CCD #2 = 4650mhz
> 
> Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
> 1900:3800 = 643.93 Gflops
> 1933:3866 = ~616.5 Glops (some whea's)
> 2000:4000 = 199 Gflops (whea's and massive throttling)
> 
> 
> 
> Few takeaways:
> 
> Still limited to 1900 flck
> Second CCD on new 5950x is much stronger than my old 5950x
> My old 5950x have higher peak ST clockspeeds but worse average CCD quality. (few cores are worse which limits the average)
> *Main drawback*: Best 212 cores on this #1 5950x are core 7 and 8. This is bad for a few reasons.. The two last cores on a full CCD always have around 6 degrees higher temps. Some benchmarks/application always ignore CPPC (such as CPU-Z) and forces workload to core1, this is very bad since core1 is the worst one in entire CCD on this cpu. (you always wish for your best 212 cores to be core1)
> 
> View attachment 2542457
> 
> 
> Running a full hydra diagnostic with elevated voltages now, can post a comparison between these cpus with higher PPT budget later/tomorrow.
> Really hope my two last cpus are better than this.. Not happy with current sample i got.
> 
> Hopefully i get the two last ones from other vendor on Friday


Have received the last two cpus and done preliminary silicon quality tests on these also, both were a older batch from week 30 2021.
First one was decent but nothing special, last one was a pretty good platinum/almost platinum sample i'm happy with 
Best sample can run 3x Cinebench r20 runs back to back @ 4825/4700mhz with only 1237mv under load, in normal ambient temp.. Together with high ST boosting on the correct cores this is a keeper. (core1)
Sadly i still cant make any headway in Linpack Xtreme in regards to scaling above 1900flck with these 4 dual CCD cpus ive tested, but i'm seeing close to perfect scaling in Aida and other light applications... Also don't get any WHEA in windows before i starts benchmarks when above 1900:3800.. (~around 100 errors per linpack run @ 2000:4000)

All tests below was run at stock bios settings --> PBO disabled and "auto" LLC which is pretty weak on this MSI UNIFY X MAX motherboard. (upto 10% vdroop under heavy load)
All stock diagnostic voltages in hydra.



Spoiler: My original 5950x stats -> BG 2046 SUS 



Asus tool = "116 silicon quality" and "4381mhz max heavy load"

Hydra: CCD quality
CCD #1 = 4525mhz --> 4.05 rating = *Golden CCD*
CCD #1 = 4325mhz --> 3.87 rating = *Bronze CCD*

1T-2T:
CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
CCD #2 = AVX1 = 4725mhz / FMA3 = 4600mhz

3T-4T:
CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz

9T-12T:
CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz

13T-16T:
CCD #1 = AVX1 = 4675mhz / FMA3 = 4550mhz
CCD #2 = AVX1 = 4500mhz / FMA3 = 4375mhz

All threads:
CCD #1 = AVX1 = 4475mhz / AVX2 = 4400mhz / FMA3 = 4125mhz
CCD #2 = AVX1 = 4325mhz / AVX2 = 4250mhz / FMA3 = 3975mhz

Game profile:
CCD #1 = 4725mhz
CCD #2 = 4550mhz

Highest ST clockspeed for 4 highest rated cores: (1375mv set)
#1 = core1 @ 4925mhz (212 rating)
#2 = core3 @ 4900mhz (208 rating)
#3 = core5 @ 4875mhz (212 rating)
#4 = core7 @ 4875mhz (203 rating)

Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set (upto 10% vdroop)
CCD #1 = 4700mhz
CCD #2 = 4600mhz

Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
1900:3800 = 642.98 Gflops
1933:3866 = ~400 Glops (whea's and massive throttling)
2000:4000 = not even attempted





Spoiler: My 5950x #1 out of 3 -> BG 2141 SUS



Asus tool = "117.5 silicon quality" and "4394mhz max heavy load"

Hydra: CCD quality
CCD #1 = 4575mhz --> 4.11 rating = *Platinum CCD*
CCD #1 = 4475mhz --> 4.02 rating = *Golden CCD*

1T-2T:
CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz

3T-4T:
CCD #1 = AVX1 = 4725mhz / FMA3 = 4600mhz
CCD #2 = AVX1 = 4675mhz / FMA3 = 4550mhz

9T-12T:
CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
CCD #2 = AVX1 = 4650mhz / FMA3 = 4525mhz

13T-16T:
CCD #1 = AVX1 = 4700mhz / FMA3 = 4575mhz
CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz

All threads:
CCD #1 = AVX1 = 4525mhz / AVX2 = 4450mhz / FMA3 = 4175mhz
CCD #2 = AVX1 = 4450mhz / AVX2 = 4375mhz / FMA3 = 4100mhz

Game profile:
CCD #1 = 4750mhz
CCD #2 = 4600mhz

Highest ST clockspeed for 4 highest rated cores: (1375mv set)
#1 = core3 @ 4975mhz (208 rating)
#2 = core7 @ 4950mhz (212 rating)
#3 = core8 @ 4875mhz (212 rating)
#4 = core1 @ 4850mhz (203 rating)

Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set (upto 10% vdroop)
CCD #1 = 4800mhz
CCD #2 = 4650mhz

Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
1900:3800 = 643.93 Gflops
1933:3866 = ~616.5 Glops (some whea's)
2000:4000 = 199 Gflops (whea's and massive throttling)





Spoiler: My 5950x #2 out of 3 -> BG 2130 SUS



Asus tool = "116.5 silicon quality" and "4386mhz max heavy load"

Hydra: CCD quality
CCD #1 = 4575mhz --> 4.09 rating = *Golden CCD*
CCD #1 = 4475mhz --> 4 rating = *Golden CCD*

1T-2T:
CCD #1 = AVX1 = 4725mhz / FMA3 = 4600mhz
CCD #2 = AVX1 = 4725mhz / FMA3 = 4600mhz

3T-4T:
CCD #1 = AVX1 = 4700mhz / FMA3 = 4575mhz
CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz

9T-12T:
CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
CCD #2 = AVX1 = 4650mhz / FMA3 = 4525mhz

13T-16T:
CCD #1 = AVX1 = 4700mhz / FMA3 = 4575mhz
CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz

All threads:
CCD #1 = AVX1 = 4525mhz / AVX2 = 4450mhz / FMA3 = 4175mhz
CCD #2 = AVX1 = 4450mhz / AVX2 = 4375mhz / FMA3 = 4125mhz

Game profile:
CCD #1 = 4725mhz
CCD #2 = 4600mhz

Highest ST clockspeed for 4 highest rated cores: (1375mv set)
#1 = core3 @ 4925mhz (212 rating)
#2 = core5 @ 4900mhz (208 rating)
#3 = core2 @ 4875mhz (203 rating)
#4 = core1 @ 4875mhz (212 rating)

Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set = *1237mv under load*
CCD #1 = 4800mhz
CCD #2 = 4650mhz

Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
1900:3800 = 643flops
1933:3866 = ~624 Glops
2000:4000 = 387 Gflops
"Perfect" scaling in aida64



This will serves as my new 5950x


Spoiler: My 5950x #3 out of 3 -> BG 2130 SUS



Asus tool = "116 silicon quality" and "4382mhz max heavy load"

Hydra: CCD quality
CCD #1 = 4625mhz --> 4.14 rating = *Platinum CCD*
CCD #1 = 4500mhz --> 4.03 rating = *Golden CCD*

1T-2T:
CCD #1 = AVX1 = 4825mhz / FMA3 = 4700mhz
CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz

3T-4T:
CCD #1 = AVX1 = 4800mhz / FMA3 = 4675mhz
CCD #2 = AVX1 = 4675mhz / FMA3 = 4550mhz

9T-12T:
CCD #1 = AVX1 = 4825mhz / FMA3 = 4700mhz
CCD #2 = AVX1 = 4650mhz / FMA3 = 4525mhz

13T-16T:
CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz

All threads:
CCD #1 = AVX1 = 4575mhz / AVX2 = 4500mhz / FMA3 = 4200mhz
CCD #2 = AVX1 = 4450mhz / AVX2 = 4375mhz / FMA3 = 4150mhz

Game profile:
CCD #1 = 4775mhz
CCD #2 = 4625mhz

Highest ST clockspeed for 4 highest rated cores: (1375mv set)
#1 = core5 @ 4950mhz (208 rating)
#2 = core3 @ 4950mhz (203 rating)
#3 = core8 @ 4925mhz (212 rating)
#4 = core1 @ 4925mhz (212 rating)

Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set = *1237mv under load*
CCD #1 = 4825mhz
CCD #2 = 4700mhz

Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
1900:3800 = 643.93 Gflops
1933:3866 = ~560 Glops
2000:4000 = 375 Gflops
"Perfect" scaling in aida64



Don't seem like the cpu rating from the asus tool have any correlation with real silicon quality..
Running a full hydra diagnostic with elevated voltages now, can post a comparison between these cpus with higher PPT budget later/tomorrow.
This can serve as a sneak peak =)


----------



## blodflekk

Perhaps someone could help me shed some light on this

.


















I had passed 50 cycles of tm5 1usmus overnight with just primaries, trc, trfc and tcke all else auto. I've now set the secondaries and teritarys loose and I'm spewing errors. I started at 1.52 vDIMM and I'm not at 1.56 vDIMM and no change in error count. This doesn't make sense. FCLK running a baseline to isolate it.


----------



## TMavica

blodflekk said:


> Perhaps someone could help me shed some light on this
> 
> .
> View attachment 2543033
> 
> 
> View attachment 2543034
> 
> 
> I had passed 50 cycles of tm5 1usmus overnight with just primaries, trc, trfc and tcke all else auto. I've now set the secondaries and teritarys loose and I'm spewing errors. I started at 1.52 vDIMM and I'm not at 1.56 vDIMM and no change in error count. This doesn't make sense. FCLK running a baseline to isolate it.


FCLK, MCLK, UCLK are not 1:1:1??


----------



## Imprezzion

blodflekk said:


> Perhaps someone could help me shed some light on this
> 
> .
> View attachment 2543033
> 
> 
> View attachment 2543034
> 
> 
> I had passed 50 cycles of tm5 1usmus overnight with just primaries, trc, trfc and tcke all else auto. I've now set the secondaries and teritarys loose and I'm spewing errors. I started at 1.52 vDIMM and I'm not at 1.56 vDIMM and no change in error count. This doesn't make sense. FCLK running a baseline to isolate it.


Yeah fix the FCLK:UCLK:MCLK first. You're also going to need more vSOC for this. And then change the tRP back to something that makes actual sense for a test. tRDWR is extremely high as well. As for the rest, it doesn't look bad. Most other secondaries have pretty valid values for the speed and voltage so. Try a different resistance setup and RTT setup. Disabled 3 1 for example with 30-20-24-24 or whatever with ProcODT 34.3.


----------



## blodflekk

Yes I know its out of sync. I already stabilized FCLK on another profile at 1900, I wanted to lock in the 3800 profile before running linked.


----------



## Audioboxer

blodflekk said:


> Perhaps someone could help me shed some light on this
> 
> .
> View attachment 2543033


Shi*ts f*cked, mate.


----------



## FHWL_

Taraquin said:


> You can try 5/7/20 on rrd/faw or 4/6/16. Wr/rtp might do 12/6 and wtr might do 3/8 or 3/6, rfc 544. You may get away with a bit lower soc/iod voltage.


Thanks! The tRFC at lower than 560 I couldn't get to work. Is it related to the procODT and Rtt values perhaps? I notice mine are higher than what I see other people use with these kits (but often it won't boot if I lower them).

I've now tightened the timings more - and got it stable (4h aida stresstest with GPU enabled, full anta777 TM5, y-cruncher 4h) with no errors except again _one _WHEA #19.
I did notice some variance in the L3 cache while benchmarking it under safe-mode. Not sure what to make of it?













Reaxer said:


> View attachment 2542828
> View attachment 2542829
> 
> This is what I managed with that kit, was not fully optimized yet, but I got some B-die to play with haha
> Voltages could probably go lower.
> View attachment 2542830
> 
> 1T GDM off without setup timings ran fine on that kit for me. tRP + tRAS aren't tRC here though


Hell, I'd sign for these timings! I've tried them - but most won't boot. I saw more setups that have this very low tRCDWR of 9, 10 or you with 8.
But I can't seem to make that boot stable. Tried 1.45V and increasing the SoC/IOD more, but no luck. Do you perhaps remember some important setting for that to work?


----------



## umea

blodflekk said:


> Yes I know its out of sync. I already stabilized FCLK on another profile at 1900, I wanted to lock in the 3800 profile before running linked.


There is no point to run unsynced. Running higher FCLK means things may need to be tweaked differently. Even if you got a 3800mts profile "stable" at unsynced it may not be stable at synced.


----------



## domdtxdissar

domdtxdissar said:


> Have received the last two cpus and done preliminary silicon quality tests on these also, both were a older batch from week 30 2021.
> First one was decent but nothing special, last one was a pretty good platinum/almost platinum sample i'm happy with
> Best sample can run 3x Cinebench r20 runs back to back @ 4825/4700mhz with only 1237mv under load, in normal ambient temp.. Together with high ST boosting on the correct cores this is a keeper. (core1)
> Sadly i still cant make any headway in Linpack Xtreme in regards to scaling above 1900flck with these 4 dual CCD cpus ive tested, but i'm seeing close to perfect scaling in Aida and other light applications... Also don't get any WHEA in windows before i starts benchmarks when above 1900:3800.. (~around 100 errors per linpack run @ 2000:4000)
> 
> All tests below was run at stock bios settings --> PBO disabled and "auto" LLC which is pretty weak on this MSI UNIFY X MAX motherboard. (upto 10% vdroop under heavy load)
> All stock diagnostic voltages in hydra.
> 
> 
> 
> Spoiler: My original 5950x stats -> BG 2046 SUS
> 
> 
> 
> Asus tool = "116 silicon quality" and "4381mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4525mhz --> 4.05 rating = *Golden CCD*
> CCD #1 = 4325mhz --> 3.87 rating = *Bronze CCD*
> 
> 1T-2T:
> CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
> CCD #2 = AVX1 = 4725mhz / FMA3 = 4600mhz
> 
> 3T-4T:
> CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
> CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz
> 
> 9T-12T:
> CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
> CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz
> 
> 13T-16T:
> CCD #1 = AVX1 = 4675mhz / FMA3 = 4550mhz
> CCD #2 = AVX1 = 4500mhz / FMA3 = 4375mhz
> 
> All threads:
> CCD #1 = AVX1 = 4475mhz / AVX2 = 4400mhz / FMA3 = 4125mhz
> CCD #2 = AVX1 = 4325mhz / AVX2 = 4250mhz / FMA3 = 3975mhz
> 
> Game profile:
> CCD #1 = 4725mhz
> CCD #2 = 4550mhz
> 
> Highest ST clockspeed for 4 highest rated cores: (1375mv set)
> #1 = core1 @ 4925mhz (212 rating)
> #2 = core3 @ 4900mhz (208 rating)
> #3 = core5 @ 4875mhz (212 rating)
> #4 = core7 @ 4875mhz (203 rating)
> 
> Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set (upto 10% vdroop)
> CCD #1 = 4700mhz
> CCD #2 = 4600mhz
> 
> Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
> 1900:3800 = 642.98 Gflops
> 1933:3866 = ~400 Glops (whea's and massive throttling)
> 2000:4000 = not even attempted
> 
> 
> 
> 
> 
> Spoiler: My 5950x #1 out of 3 -> BG 2141 SUS
> 
> 
> 
> Asus tool = "117.5 silicon quality" and "4394mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4575mhz --> 4.11 rating = *Platinum CCD*
> CCD #1 = 4475mhz --> 4.02 rating = *Golden CCD*
> 
> 1T-2T:
> CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
> CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz
> 
> 3T-4T:
> CCD #1 = AVX1 = 4725mhz / FMA3 = 4600mhz
> CCD #2 = AVX1 = 4675mhz / FMA3 = 4550mhz
> 
> 9T-12T:
> CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
> CCD #2 = AVX1 = 4650mhz / FMA3 = 4525mhz
> 
> 13T-16T:
> CCD #1 = AVX1 = 4700mhz / FMA3 = 4575mhz
> CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz
> 
> All threads:
> CCD #1 = AVX1 = 4525mhz / AVX2 = 4450mhz / FMA3 = 4175mhz
> CCD #2 = AVX1 = 4450mhz / AVX2 = 4375mhz / FMA3 = 4100mhz
> 
> Game profile:
> CCD #1 = 4750mhz
> CCD #2 = 4600mhz
> 
> Highest ST clockspeed for 4 highest rated cores: (1375mv set)
> #1 = core3 @ 4975mhz (208 rating)
> #2 = core7 @ 4950mhz (212 rating)
> #3 = core8 @ 4875mhz (212 rating)
> #4 = core1 @ 4850mhz (203 rating)
> 
> Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set (upto 10% vdroop)
> CCD #1 = 4800mhz
> CCD #2 = 4650mhz
> 
> Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
> 1900:3800 = 643.93 Gflops
> 1933:3866 = ~616.5 Glops (some whea's)
> 2000:4000 = 199 Gflops (whea's and massive throttling)
> 
> 
> 
> 
> 
> Spoiler: My 5950x #2 out of 3 -> BG 2130 SUS
> 
> 
> 
> Asus tool = "116.5 silicon quality" and "4386mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4575mhz --> 4.09 rating = *Golden CCD*
> CCD #1 = 4475mhz --> 4 rating = *Golden CCD*
> 
> 1T-2T:
> CCD #1 = AVX1 = 4725mhz / FMA3 = 4600mhz
> CCD #2 = AVX1 = 4725mhz / FMA3 = 4600mhz
> 
> 3T-4T:
> CCD #1 = AVX1 = 4700mhz / FMA3 = 4575mhz
> CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz
> 
> 9T-12T:
> CCD #1 = AVX1 = 4775mhz / FMA3 = 4650mhz
> CCD #2 = AVX1 = 4650mhz / FMA3 = 4525mhz
> 
> 13T-16T:
> CCD #1 = AVX1 = 4700mhz / FMA3 = 4575mhz
> CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz
> 
> All threads:
> CCD #1 = AVX1 = 4525mhz / AVX2 = 4450mhz / FMA3 = 4175mhz
> CCD #2 = AVX1 = 4450mhz / AVX2 = 4375mhz / FMA3 = 4125mhz
> 
> Game profile:
> CCD #1 = 4725mhz
> CCD #2 = 4600mhz
> 
> Highest ST clockspeed for 4 highest rated cores: (1375mv set)
> #1 = core3 @ 4925mhz (212 rating)
> #2 = core5 @ 4900mhz (208 rating)
> #3 = core2 @ 4875mhz (203 rating)
> #4 = core1 @ 4875mhz (212 rating)
> 
> Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set = *1237mv under load*
> CCD #1 = 4800mhz
> CCD #2 = 4650mhz
> 
> Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
> 1900:3800 = 643flops
> 1933:3866 = ~624 Glops
> 2000:4000 = 387 Gflops
> "Perfect" scaling in aida64
> 
> 
> 
> This will serves as my new 5950x
> 
> 
> Spoiler: My 5950x #3 out of 3 -> BG 2130 SUS
> 
> 
> 
> Asus tool = "116 silicon quality" and "4382mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4625mhz --> 4.14 rating = *Platinum CCD*
> CCD #1 = 4500mhz --> 4.03 rating = *Golden CCD*
> 
> 1T-2T:
> CCD #1 = AVX1 = 4825mhz / FMA3 = 4700mhz
> CCD #2 = AVX1 = 4700mhz / FMA3 = 4575mhz
> 
> 3T-4T:
> CCD #1 = AVX1 = 4800mhz / FMA3 = 4675mhz
> CCD #2 = AVX1 = 4675mhz / FMA3 = 4550mhz
> 
> 9T-12T:
> CCD #1 = AVX1 = 4825mhz / FMA3 = 4700mhz
> CCD #2 = AVX1 = 4650mhz / FMA3 = 4525mhz
> 
> 13T-16T:
> CCD #1 = AVX1 = 4750mhz / FMA3 = 4625mhz
> CCD #2 = AVX1 = 4575mhz / FMA3 = 4450mhz
> 
> All threads:
> CCD #1 = AVX1 = 4575mhz / AVX2 = 4500mhz / FMA3 = 4200mhz
> CCD #2 = AVX1 = 4450mhz / AVX2 = 4375mhz / FMA3 = 4150mhz
> 
> Game profile:
> CCD #1 = 4775mhz
> CCD #2 = 4625mhz
> 
> Highest ST clockspeed for 4 highest rated cores: (1375mv set)
> #1 = core5 @ 4950mhz (208 rating)
> #2 = core3 @ 4950mhz (203 rating)
> #3 = core8 @ 4925mhz (212 rating)
> #4 = core1 @ 4925mhz (212 rating)
> 
> Highest clockspeed possible to complete Cinebench r20 3 times in a row @ 1375mv set = *1237mv under load*
> CCD #1 = 4825mhz
> CCD #2 = 4700mhz
> 
> Linpack Xtreme @ static 4500/4400mhz (slow "safe" memory-timings)
> 1900:3800 = 643.93 Gflops
> 1933:3866 = ~560 Glops
> 2000:4000 = 375 Gflops
> "Perfect" scaling in aida64
> 
> 
> 
> Don't seem like the cpu rating from the asus tool have any correlation with real silicon quality..
> Running a full hydra diagnostic with elevated voltages now, can post a comparison between these cpus with higher PPT budget later/tomorrow.
> This can serve as a sneak peak =)
> View attachment 2542992


Pretty good numbers in hydra boost test 








Full completed hydra diagnostic:







Have to admit, think this is among the best 5950x's ive ever seen 😁


----------



## Reaxer

FHWL_ said:


> Thanks! The tRFC at lower than 560 I couldn't get to work. Is it related to the procODT and Rtt values perhaps? I notice mine are higher than what I see other people use with these kits (but often it won't boot if I lower them).


Yeah lower than I think 560 also didn't boot for me.
Your tFAW on 12 doesn't really make sense btw, it effectively can't be lower than tRRDS * 4, so 16


FHWL_ said:


> Hell, I'd sign for these timings! I've tried them - but most won't boot. I saw more setups that have this very low tRCDWR of 9, 10 or you with 8.
> But I can't seem to make that boot stable. Tried 1.45V and increasing the SoC/IOD more, but no luck. Do you perhaps remember some important setting for that to work?


Did you try that with GDM off 2T and the procODT, Rtts and CAD resistances I used? These could all be different because MB/kit differences, but you could try if it works.


----------



## Bix

Veii said:


> Unstable memory can mean many things
> This includes unstable cores
> Soo start with checking loadline's and see if you are over 4 loops y-cruncher, stable
> Then later work on your memory


I've run y-cruncher 3 times (4 iterations each and rebooting in between) and passed no problem so loadlines seem ok. Any suggestions what to try next? Vcore offset?


----------



## sealxohd

So.. I dichted the Steel Legend and bought a X570 Master. I finally can do 1T GDM off stable at more then 3600. tPHY is 26/26 which is quite nice I guess. I will try to lower tWR next. This timings was bitching on my old board when VDIMM was higher than 1.52 V.











I nearly have 3800 13-13 stable. 1 Error at 8000%... Any ideas how I could get that stable? RTTs and CADs are optimal I think.










I also did some 2:1 testing and 4533 looks good but its not stable


----------



## Veii

MrHoof said:


> Just changing VDDP trying to fix a missmatch wont work. You have to force a retraining in some way or it wont do anything.


My reality tends to disagree 
Memory retrains also on a warm boot
It only needs a cold boot if both channels mismatch
(Which is done/decided by itself)
If one mismatches, the change is shown immediately

Changing cLDO_VDDP, has a more granular effect then working with ClkDrvStr
Both lead to the same path, but cLDO_VDDP shouldn't be used for memory powering
Yet can be a reason of "overpowering"

Changing it too broad can cause a no boot scenario without it being a lack of VDDP for the IMC , reason
Then changing it too high, will force training of values 32+
Which for some boards do not post at all
It's vendor dependent, but the reasoning should be the same
At least that's for DualRank
On SR you can pump VDDP voltage and run high MCLK without issues
On DR, if nothing is perfect it will refuse to train near 4200MT/s


----------



## PJVol

Bix said:


> Any suggestions what to try next? Vcore offset?


Flash the 1.2.0.3c bios back and let it breathe queitly )
Vcore offset is evil, unless you have it manually OC'ed, so better not to touch it, the same way the LLC goes.
Both mb features are just "tricking" your CPU power/perf management.


----------



## Taraquin

FHWL_ said:


> Thanks! The tRFC at lower than 560 I couldn't get to work. Is it related to the procODT and Rtt values perhaps? I notice mine are higher than what I see other people use with these kits (but often it won't boot if I lower them).
> 
> I've now tightened the timings more - and got it stable (4h aida stresstest with GPU enabled, full anta777 TM5, y-cruncher 4h) with no errors except again _one _WHEA #19.
> I did notice some variance in the L3 cache while benchmarking it under safe-mode. Not sure what to make of it?
> 
> View attachment 2543056
> 
> 
> 
> 
> 
> Hell, I'd sign for these timings! I've tried them - but most won't boot. I saw more setups that have this very low tRCDWR of 9, 10 or you with 8.
> But I can't seem to make that boot stable. Tried 1.45V and increasing the SoC/IOD more, but no luck. Do you perhaps remember some important setting for that to work?


Your kit can't handle lower rfc, nothing you can do. Set rtp to 6 since wr=2 x rtp. Try 58 or 56 rc, remember that rc is ras+rtp so rc 60=ras 44, rc 58=ras 42, rc 56=ras 40 etc. Set wrrd to 3 and try rdwr 9 or 10 instead.


----------



## MrHoof

Veii said:


> My reality tends to disagree
> Memory retrains also on a warm boot
> It only needs a cold boot if both channels mismatch
> (Which is done/decided by itself)
> If one mismatches, the change is shown immediately


Just changing VDDP from .9 to .875 without forcing retraining, no missmatch. 








Setting tRDWR to auto (8) forces retraining and results in missmatch can 100% replicate that behavoir.


----------



## Veii

MrHoof said:


> Setting tRDWR to auto (8) forces retraining and results in missmatch can 100% replicate that behavoir.


It will
Yes
Same for changing tCWL
But unless you have memory clear disabled, it will also retrain on post

A higher value can still result in it being stable, but it's more prevention based (the reason)
Drop ClkDrvStr to 30
Or keep 40 and slowly drop cLDO_VDDP 
By 2-5mV 

The line is thin between post and no post, especially on DR
If it tries to train 24, it wont post
If it tries to train 32, it wont post
(MSI Boards seem to be an exception)


----------



## nick name

Does 5600X and 5800X bandwidth not scale when running with increased RAM speeds and FCLK=/=MCLK?


----------



## Veii

nick name said:


> Does 5600X and 5800X bandwidth not scale when running with increased RAM speeds and FCLK=/=MCLK?


?
Everything scales, but has a big drop by going 2:1
FCLK = Write bandwidth

Wouldn't see benefits bellow 4800MT/s
And even then, on XMP it was worse
On tight timings still was worse, but you need to be around there to see slight benefits
I target 5000+, but A0 is maxed at 4600
(Should've been maxed at 4167)
A2 was fine near 4800+, but boards are messed up at 4933-4967
Soo didn't bother further, was fun ~ but benchmarking on Win11 is an issue


----------



## Audioboxer

sealxohd said:


> So.. I dichted the Steel Legend and bought a X570 Master. I finally can do 1T GDM off stable at more then 3600. tPHY is 26/26 which is quite nice I guess. I will try to lower tWR next. This timings was bitching on my old board when VDIMM was higher than 1.52 V.
> 
> View attachment 2543081
> 
> 
> 
> I nearly have 3800 13-13 stable. 1 Error at 8000%... Any ideas how I could get that stable? RTTs and CADs are optimal I think.
> 
> View attachment 2543082
> 
> 
> I also did some 2:1 testing and 4533 looks good but its not stable
> 
> View attachment 2543083


Good luck getting that first profile stable, I don't think I've seen anyone achieve tRCDRD 13 at 3800 with DR before.

Other than pictures of people running GDM 1T 14-13-x-x for like an hour and calling it stable lol.

Obviously a great kit/mobo and CPU combo, especially booting above 4400 on DR. This is where I wonder if it's more on the IMC or the memory itself. Given you're also booting above 4400 on DR, I'm actually thinking it _could_ be IMC.

@domdtxdissar have you played about with memory with those 5950x samples? See if you can get booting above 4400 continually and/or running tRCDRD 13?


----------



## Bix

PJVol said:


> Flash the 1.2.0.3c bios back and let it breathe queitly )
> Vcore offset is evil, unless you have it manually OC'ed, so better not to touch it, the same way the LLC goes.
> Both mb features are just "tricking" your CPU power/perf management.


Good plan. No idea what was going on with 1.2.0.5 but it didn't look good. Back on 1.2.0.3 with some nice and soothing TM5 🙂


----------



## nick name

Veii said:


> ?
> Everything scales, but has a big drop by going 2:1
> FCLK = Write bandwidth
> 
> Wouldn't see benefits bellow 4800MT/s
> And even then, on XMP it was worse
> On tight timings still was worse, but you need to be around there to see slight benefits
> I target 5000+, but A0 is maxed at 4600
> (Should've been maxed at 4167)
> A2 was fine near 4800+, but boards are messed up at 4933-4967
> Soo didn't bother further, was fun ~ but benchmarking on Win11 is an issue


With my 3900X I always saw an increase in bandwidth when IF wasn't 1:1. With the 5800X I see a drop in bandwidth when IF isn't 1:1 at higher RAM speeds. I see others with a 5900X or 5950X that behave like my 3900X did so I'm assuming it's the 1 CCD vs 2 CCD.


----------



## sealxohd

Audioboxer said:


> Good luck getting that first profile stable, I don't think I've seen anyone achieve tRCDRD 13 at 3800 with DR before.
> 
> Other than pictures of people running GDM 1T 14-13-x-x for like an hour and calling it stable lol.
> 
> Obviously a great kit/mobo and CPU combo, especially booting above 4400 on DR. This is where I wonder if it's more on the IMC or the memory itself. Given you're also booting above 4400 on DR, I'm actually thinking it _could_ be IMC.
> 
> @domdtxdissar have you played about with memory with those 5950x samples? See if you can get booting above 4400 continually and/or running tRCDRD 13?


I actually can run tRCD 13 with GDM..... but its GDM so it doesnt count🤣

Have you tried to increase the 2.5 V voltage? Should not do anything on paper but it helped me quite a bit.
With 2.7 V I can boot 4400 1T gdm off and it isnt super unstable as well. I might play with that profile a bit more.
I really think that the IMC limits here. On Intel 4600 with DR B-die is easy. Atleast with 10th Gen


----------



## Veii

nick name said:


> With my 3900X I always saw an increase in bandwidth when IF wasn't 1:1. With the 5800X I see a drop in bandwidth when IF isn't 1:1 at higher RAM speeds. I see others with a 5900X or 5950X that behave like my 3900X did so I'm assuming it's the 1 CCD vs 2 CCD.


Aah
Probably an (lack of) interleaving bottleneck
But sadly i don't know much, but it doesn't help it
Always expected APUs to be faster, but then they are cut on cache too

Likely because interleaving, while snowballing on bandwidth, it also snowballs on heat
Hence we can't have quad channel memory on consumer chips
100% bandwidth, 80% heat increase
Well effective is not perfectly double


----------



## FHWL_

Reaxer said:


> View attachment 2542828
> View attachment 2542829
> 
> This is what I managed with that kit, was not fully optimized yet, but I got some B-die to play with haha
> Voltages could probably go lower.
> View attachment 2542830
> 
> 1T GDM off without setup timings ran fine on that kit for me. tRP + tRAS aren't tRC here though


I've tried this again - and got it booting!!








(Increased tRCDWR to 10 from 8, to see if it made a difference. It didn't. VDIMM = 1.45, MEM VTT = 0.725)

However, as soon as I start an AIDA64 stresstest (w/ everything except disk) - I get BSOD/reboots. Tried playing around with the ProcODT/CAD_BUS values and increasing soc/VDDP from 1.12 to 1.15 and 0.88 to 0.95. No luck.
I assume it's in the voltages somewhere, as it works for you and (now) for me too. Just not stable. But I'm too inexperienced to have a hunch where/which voltages and what values. Any tips?



Reaxer said:


> Yeah lower than I think 560 also didn't boot for me.
> Your tFAW on 12 doesn't really make sense btw, it effectively can't be lower than tRRDS * 4, so 16
> 
> Did you try that with GDM off 2T and the procODT, Rtts and CAD resistances I used? These could all be different because MB/kit differences, but you could try if it works.





Taraquin said:


> Your kit can't handle lower rfc, nothing you can do. Set rtp to 6 since wr=2 x rtp. Try 58 or 56 rc, remember that rc is ras+rtp so rc 60=ras 44, rc 58=ras 42, rc 56=ras 40 etc. Set wrrd to 3 and try rdwr 9 or 10 instead.



Regarding those timings: Having it set "wrong", does it degrade performance, or is it "not optimal"/leaving performance on the table? I can imagine that if incorrect values are given, the bios sets these values itself to something valid - rendering "my" settings ineffective. But not degrading performance beyond not optimal settings.
The reason I'm asking is, I tried changing the faw, rtp, rc and wrrd/rdwr - but it gives me new WHEA 19's. So I'm considering leaving it be (for now, my brain kinda hurts lol).


----------



## Reaxer

FHWL_ said:


> I've tried this again - and got it booting!!
> View attachment 2543159
> 
> (Increased tRCDWR to 10 from 8, to see if it made a difference. It didn't. VDIMM = 1.45, MEM VTT = 0.725)
> 
> However, as soon as I start an AIDA64 stresstest (w/ everything except disk) - I get BSOD/reboots. Tried playing around with the ProcODT/CAD_BUS values and increasing soc/VDDP from 1.12 to 1.15 and 0.88 to 0.95. No luck.
> I assume it's in the voltages somewhere, as it works for you and (now) for me too. Just not stable. But I'm too inexperienced to have a hunch where/which voltages and what values. Any tips?


Ah hahaha you copied everything, but yeah you're on a different board, could that the CAD values need to be different. 
I'd test first if 2T has the same problems, If that also gives you problems you should try changing the CADs. If it works you could try 1T with AddrCmdSetup 56. 
If could be that some timings like tWTRS and tWTRL are too tight, not sure if every kit can handle that.


----------



## Bix

Bix said:


> Good plan. No idea what was going on with 1.2.0.5 but it didn't look good. Back on 1.2.0.3 with some nice and soothing TM5 🙂


Oh ****. After reflashing 1.2.0.3 was concerned to see AIDA latency wasn't back down to where it should be and, lo and behold, first run of TM5 threw a single error 6 on cycle 25😔 with settings I know for sure were previously fine. Need to test more to confirm but it looks as though whatever has changed in the CPU is indeed permanent. Really hope that I've not just nerfed the thing and will have to scrap my 2000/4000 1t profile!

Anyone else here running 1.2.0.5 with >1900 FCLK?? Would have probably been a good idea to check this earlier...


----------



## TMavica

I got 2 wheas which is related to L1 cache error in hwinfo during about 2-3 aida64 test, but my memory is passed the stress test without wheaa..Maybe is due to CPU problem? However, I just simple use PBO with dynamic OC


----------



## Taraquin

FHWL_ said:


> I've tried this again - and got it booting!!
> View attachment 2543159
> 
> (Increased tRCDWR to 10 from 8, to see if it made a difference. It didn't. VDIMM = 1.45, MEM VTT = 0.725)
> 
> However, as soon as I start an AIDA64 stresstest (w/ everything except disk) - I get BSOD/reboots. Tried playing around with the ProcODT/CAD_BUS values and increasing soc/VDDP from 1.12 to 1.15 and 0.88 to 0.95. No luck.
> I assume it's in the voltages somewhere, as it works for you and (now) for me too. Just not stable. But I'm too inexperienced to have a hunch where/which voltages and what values. Any tips?
> 
> 
> 
> 
> 
> 
> Regarding those timings: Having it set "wrong", does it degrade performance, or is it "not optimal"/leaving performance on the table? I can imagine that if incorrect values are given, the bios sets these values itself to something valid - rendering "my" settings ineffective. But not degrading performance beyond not optimal settings.
> The reason I'm asking is, I tried changing the faw, rtp, rc and wrrd/rdwr - but it gives me new WHEA 19's. So I'm considering leaving it be (for now, my brain kinda hurts lol).


1t gdm off is much harder to run than 2t or 1t gdm on. Timings not adding up could degrade performance, but might be fine. For 1t gdm off to work try a bit higher ProcODT, for dual rank 37-48 is often better, DrvStr might be fine, rdwr 9 or 10 to see if this resolves the problems in aida etc. Wtrs 2 and wtrl 6 is extremely low, I would try 3 on wtrs, maybe 7 or 8 on wtrl to see if this helps stability.


----------



## FHWL_

Reaxer said:


> Ah hahaha you copied everything, but yeah you're on a different board, could that the CAD values need to be different.
> I'd test first if 2T has the same problems, If that also gives you problems you should try changing the CADs. If it works you could try 1T with AddrCmdSetup 56.
> If could be that some timings like tWTRS and tWTRL are too tight, not sure if every kit can handle that.


Epic!! This seems to work haha.
I've got these settings now - and it's no longer BSODing (but only tested for 10min aida stresstest).













Taraquin said:


> 1t gdm off is much harder to run than 2t or 1t gdm on. Timings not adding up could degrade performance, but might be fine. For 1t gdm off to work try a bit higher ProcODT, for dual rank 37-48 is often better, DrvStr might be fine, rdwr 9 or 10 to see if this resolves the problems in aida etc. Wtrs 2 and wtrl 6 is extremely low, I would try 3 on wtrs, maybe 7 or 8 on wtrl to see if this helps stability.


Do you have more info on those timings not adding up degrading performance (and do you mean physically - or system performance)? I'm aiming for a 24/7 stable build 😅

I'll do one more config run and then let it test overnight (HCI is best for this?)
Thanks for your input guys!


----------



## domdtxdissar

Audioboxer said:


> Good luck getting that first profile stable, I don't think I've seen anyone achieve tRCDRD 13 at 3800 with DR before.
> 
> Other than pictures of people running GDM 1T 14-13-x-x for like an hour and calling it stable lol.
> 
> Obviously a great kit/mobo and CPU combo, especially booting above 4400 on DR. This is where I wonder if it's more on the IMC or the memory itself. Given you're also booting above 4400 on DR, I'm actually thinking it _could_ be IMC.
> 
> @domdtxdissar have you played about with memory with those 5950x samples? See if you can get booting above 4400 continually and/or running tRCDRD 13?


Playing around with CPU clockspeeds atm, will turn to memory OC next..


----------



## Taraquin

FHWL_ said:


> Epic!! This seems to work haha.
> I've got these settings now - and it's no longer BSODing (but only tested for 10min aida stresstest).
> 
> View attachment 2543183
> 
> 
> 
> 
> 
> Do you have more info on those timings not adding up degrading performance (and do you mean physically - or system performance)? I'm aiming for a 24/7 stable build 😅
> 
> I'll do one more config run and then let it test overnight (HCI is best for this?)
> Thanks for your input guys!


In some cases wrong timings can lead to counts not adding up and you get slight worse performance. Sometimes wrong timing requires higher voltage, but gives you no benefit, example rrds of 4 and faw of 28. Faw=rrd x 4, and rrds 4 is harder to run than rrds 7 which is correct for faw 28.

Have you tried the tips I have for stabilizing 1t gdm off? If you still get errors try 2t.


----------



## FHWL_

Taraquin said:


> In some cases wrong timings can lead to counts not adding up and you get slight worse performance. Sometimes wrong timing requires higher voltage, but gives you no benefit, example rrds of 4 and faw of 28. Faw=rrd x 4, and rrds 4 is harder to run than rrds 7 which is correct for faw 28.
> 
> Have you tried the tips I have for stabilizing 1t gdm off? If you still get errors try 2t.


Yes, thanks! I've got 1T gdm off now tested overnight with HCI (800% to 1000%), no errors, no WHEA. Also AIDA64 stabilitytest stable for ~30min (no WHEA either).









Now going to test your suggested rdwr and wtrl (seems stable too, and slightly faster). Not touching procODT yet because I'm a bit scared for the BSOD's and potentially corrupting windows (I did backup the most important, but still not looking forward to reinstalling )









(Here tighter FAW, RDWR, WTRL).

Now that 1T seems stable, GDM would not offer a benefit correct? (I understand GDM to be some kind of 1.5T, between 1T and 2T).


----------



## Taraquin

FHWL_ said:


> Yes, thanks! I've got 1T gdm off now tested overnight with HCI (800% to 1000%), no errors, no WHEA. Also AIDA64 stabilitytest stable for ~30min (no WHEA either).
> View attachment 2543233
> 
> 
> Now going to test your suggested rdwr and wtrl (seems stable too, and slightly faster). Not touching procODT yet because I'm a bit scared for the BSOD's and potentially corrupting windows (I did backup the most important, but still not looking forward to reinstalling )
> 
> View attachment 2543235
> 
> (Here tighter FAW, RDWR, WTRL).
> 
> Now that 1T seems stable, GDM would not offer a benefit correct? (I understand GDM to be some kind of 1.5T, between 1T and 2T).


Nice. Remember wr=2x rtp, so 16/8, 14/7, 12/6 is good. Wrrd of 3 is usually better. Gdm masks some instabilities, but in general 2T gdm off is faster on my 5600X, while 1T gdm off is best. I think you are very close to the potential of your ram now


----------



## GrumpyCalabi314

Hi all! I was able to reach this results (Ryzen 5600X, MSI B550M Mortar with the latest stable BIOS, i.e. AGESA 1.2.0.5, 2x8GB Crucial Ballistix Elite, i.e. Micron Rev. E):










I would like to try to OC my RAM @ 3800 with GDM disabled. However, i'm not able to pass a stress test, even loosen some timings. Some tips?


----------



## Blameless

TMavica said:


> I got 2 wheas which is related to L1 cache error in hwinfo during about 2-3 aida64 test, but my memory is passed the stress test without wheaa..Maybe is due to CPU problem? However, I just simple use PBO with dynamic OC


If it's actually an L1 error, that is almost certainly CPU related, quite possibly incorrect PBO curves.


----------



## hazium233

MrHoof said:


> Just changing VDDP trying to fix a missmatch wont work. You have to force a retraining in some way or it wont do anything.
> I used to do this, TRDWR autos to 8 but I normaly run 7, setting it to auto from 7 will always cause a retrain for me.


I might have been using Auto to the same value as auto. Or I somehow forgot to fix MRC Fastboot Disabled I don't know. Regardless it was some error I made in testing apparently.

I may waste more time to see if CLDO VDDP can actually be lowered for GDM by altering the resistances or SOC.

As an aside, it looks like these do 15-15-15 at lower voltage than my 3600C15 sticks, or more accurately than the bad stick.


----------



## nada324

I dont know why my latency looks that high but there is no proccess at background, cant get TRCDRD down to 15, tried bunch of stuff but seems like this 4133 c19 kits from patriot doesnt like it.

So, what would you guys improve of subtimings?


----------



## PJVol

Updated BIOS with the agesa 1.2.0.5 to see what all this noise was about.
And, well... just look at this, ain't it funny?


----------



## Veii

PJVol said:


> Updated BIOS with the agesa 1.2.0.5 to see what all this noise was about.
> And, well... just look at this, ain't it funny?
> View attachment 2543304


Before reading your post i got worry vibes (bad feeling goosebumps) ^^''
Can you post 2002 MCLK ?
with BLKC probably ?

EDIT:
1375 is a good range for a 5600X
But COs need to drop (to -40) and fMAX needs to increase to 300+
Else scaling is up to 1413 (substrate, well FIT rather)
Needs further undervolt range and stronger overclock range.
Also needs ProcHot fix !
(both , general for this platform/model)

EDIT2:
Does FIT even allow you to post 1225mV SOC ?


----------



## Luggage

PJVol said:


> Updated BIOS with the agesa 1.2.0.5 to see what all this noise was about.
> And, well... just look at this, ain't it funny?
> View attachment 2543304


Did you change PBO limits or did AMD change defaults?


----------



## sealxohd

Audioboxer said:


> Good luck getting that first profile stable, I don't think I've seen anyone achieve tRCDRD 13 at 3800 with DR before.
> 
> Other than pictures of people running GDM 1T 14-13-x-x for like an hour and calling it stable lol.
> 
> Obviously a great kit/mobo and CPU combo, especially booting above 4400 on DR. This is where I wonder if it's more on the IMC or the memory itself. Given you're also booting above 4400 on DR, I'm actually thinking it _could_ be IMC.
> 
> @domdtxdissar have you played about with memory with those 5950x samples? See if you can get booting above 4400 continually and/or running tRCDRD 13?


I actually managed to get rid of these consistent errors at 8000%. I increased PM_CLDO12 and PM_1VSOC a bit. Seems like that helped the IMC. I think tRCD 13 and GDM off is just an IMC thing if your kit can do it with GDM on.


----------



## PJVol

Veii said:


> Can you post 2002 MCLK ?





Veii said:


> Does FIT even allow you to post 1225mV SOC ?


Yeah. Booted first with a [email protected] mem preset without vdd18 tuned, and... got rebooted during the AIDA cachemem bm.
After setting vdd18 back to ususal for that fclk 2.05V, everything's got back to normal operation.
I have negative experience with a BCLK before so i'd prefer not to touch it.


Spoiler: some aida, etc...








































Spoiler: 2002 MCLK (bclk 101.2...)













I'm not sure what is behind "FIT allowed to post Vsoc 1225", though if you mean if pc boot with that Vsoc at all, I could check.


Luggage said:


> Did you change PBO limits or did AMD change defaults?


If you mean those in agesa 1205 screen, yes, I've changed them. Defaults are not changed. First I was curious, why EDC is bumping in a ~115A wall, until i figured out that the VID limit is changed.

Tbh, I haven't figured out yet, what is driving the throttling train, EDC or VID limit. The FIT limiting isn't noticeable since temps lower as well due to lower EDC.
Though it is clear, the EDC is some 10 amps lower at the same workloads, such as СB or Cpu-z, compared to the previous 1.2.0.3c based version, so the benefits of high EDC limit are now even less obvious.
Basically the best performance can be achieved keeping it in a 95-110A range. Previously (1203c) the optimal range for me was ~ 110-120A. (IIRC pre 1.2.0.0 agesa bioses didn't exhibit this behavior at all)

UPD: One more odd thing is that both VDDG voltages were set in BIOS to 0.95V (Vsoc 1.1V), but the board/cpu has autocorrected or rather FIXED them (lol).
Zentimings and HWInfo have reported them at 0.9976V, regardless of Vsoc value (honestly, couldn't care less about both since Zen3, and could never understand what's the use of them).

UPD2: Booted fine with Vsoc at 1.225, though nothing special here, besides ~16-17W power it consumes.


----------



## Audioboxer

sealxohd said:


> I actually managed to get rid of these consistent errors at 8000%. I increased PM_CLDO12 and PM_1VSOC a bit. Seems like that helped the IMC. I think tRCD 13 and GDM off is just an IMC thing if your kit can do it with GDM on.
> 
> View attachment 2543331


Nice, I think this is the first tRCDRD 13 I've seen stable on DR at 3800. What were all the voltages you changed then? I've not really played with anything other than what ZenTimings shows.

tRCDRD 13 will run for me with GDM and tCL14 and it works with GDM disabled and maxmem in use. Here's hoping it might be my IMC needing some help.


----------



## FHWL_

Think I've found my stable OC now. No occasional WHEA 19's anymore, and vastly improved timings over stock 3200-16-18-18-36 D.O.C.P.
Huge thanks @*Taraquin *and *@Reaxer* for your help!

For completeness (and in the future maybe others trying to do the same):










2x 16GB Micron E-die DR BL16G32C16U4BL.16FE B083VMZX6F C9BJZ - Crucial Ballistix RGB Black DDR3200 32GB kit, Asus X570-F strix 4021
Running stable at: 3800MHz 16-8-20-20-38 @1.42V


----------



## sealxohd

Audioboxer said:


> Nice, I think this is the first tRCDRD 13 I've seen stable on DR at 3800. What were all the voltages you changed then? I've not really played with anything other than what ZenTimings shows.
> 
> tRCDRD 13 will run for me with GDM and tCL14 and it works with GDM disabled and maxmem in use. Here's hoping it might be my IMC needing some help.


I changed besides the voltages shown in ZenTimings these two. 










CLDO12 to 1.25 V and 1VSOC to 1.1 V. According to Gigabyte 1.25 V and 1.2 V is the maximum for daily operation.
The pdf contains their OC "Guide". I dont know how much they help, since I got pretty far already without touching these voltages.


----------



## Audioboxer

sealxohd said:


> I changed besides the voltages shown in ZenTimings this two. CLDO12 to 1.25 V and 1VSOC to 1.1 V. According to Gigabyte 1.25 V and 1.2 V is the maximum for daily operation.
> The pdf contains their OC "Guide". I dont know how much they help, since I got pretty far without touching these voltages already.
> 
> View attachment 2543435


Thanks, will have a look and see if these are called the same thing in the MSI BIOS.

Did you only increase the 2.5v for pushing up the frequency?


----------



## sealxohd

Audioboxer said:


> Thanks, will have a look and see if these are called the same thing in the MSI BIOS.
> 
> Did you only increase the 2.5v for pushing up the frequency?


Yes. I touch the 2.5 V voltage only for high frequencies. I think that an increase is even harmful for stability at lower speeds.


----------



## Audioboxer

sealxohd said:


> Yes. I touch the 2.5 V voltage only for high frequencies. I think that an increase is even harmful for stability at lower speeds.


Quick look and I don't know if the MSI BIOS has those two voltages, or they're called something else. Will do some more digging later, have work to do!


----------



## PJVol

Bix said:


> Anyone else here running 1.2.0.5 with >1900 FCLK?? Would have probably been a good idea to check this earlier...


Have you got fTPM module disabled in BIOS before update, since starting from 1.2.0.3C (or earlier) boards are enabling it by default?
I've heard of numerous issues people have with it enabled, not sure does it hurt the performance, but personally have it always disabled in saved uefi profiles.


----------



## Audioboxer

Anyone know what these voltages would be called in an MSI bios?

CLDO12
1VSOC


----------



## Veii

PJVol said:


> I'm not sure what is behind "FIT allowed to post Vsoc 1225", though if you mean if pc boot with that Vsoc at all, I could check.


Yes pretty much that (last part)
There where "days" (let's call it like that) ~ "issues"
where there where boot issues by exceeding 1.1v SOC
Also issues with the OC Mode flag (i keep disabled atm)


PJVol said:


> UPD: One more odd thing is that both VDDG voltages were set in BIOS to 0.95V (Vsoc 1.1V), but the board/cpu has autocorrected or rather FIXED them (lol).
> Zentimings and HWInfo have reported them at 0.9976V, regardless of Vsoc value


This reminds me of Matisse and the same flag written above
Without it enabled or without following minimum distance differences, it always autocorrected and managed them by themself
Hence on the AMD Maximum Voltage thread, both VDDGs where written as SET only ~ as both where adjusting by themself up to needs (and GET readout rarely made sense)

Am not surprised to find new oddness and new behavior again. Common experience on AM4
Hence rules from old gens very rarely to never match up.

EDIT:
Playing with bioses atm
Either i make something or i brick my board again
(1205 & 1206 are not very different)
We'll see


----------



## Bix

PJVol said:


> Have you got fTPM module disabled in BIOS before update, since starting from 1.2.0.3C (or earlier) boards are enabling it by default?
> I've heard of numerous issues people have with it enabled, not sure does it hurt the performance, but personally have it always disabled in saved uefi profiles.


That's a good point - TPM was disabled on 1.2.0.3b by default but just found it's enabled for me on 1.2.0.5. Running TM5 again now with TPM disabled and everything crossed!


----------



## Worldwin

Lowered TWR to 10 from 12 got me a single error in test 1. Any suggestion what to change to fix this?


----------



## KedarWolf

Worldwin said:


> View attachment 2543505
> 
> Lowered TWR to 10 from 12 got me a single error in test 1. Any suggestion what to change to fix this?


VDIMM higher maybe, can try VSOC at 1.1 too. VDDP might be better at .900, I find higher can cause instability.

Edit: Might want to try 40-20-24-24.


----------



## Worldwin

KedarWolf said:


> VDIMM higher maybe, can try VSOC at 1.1 too. VDDP might be better at .900, I find higher can cause instability.
> 
> Edit: Might want to try 40-20-24-24.


Considering its a single error I feel like its possible to address without messing with the voltages. I'll try 40-20-24-24. 
Edit: Passed TM5 with them settings but failed HCL memtest HARD. 8 errors @ 25%.


----------



## domdtxdissar

Wrote about it in the motherboard thread, but can share it here also.. After changing motherboard from ROG Crosshair VIII Hero to Unify X MAX without reinstalling windows i was struggling with lower than expect performance numbers in a few different benchmarks.. I thought it was down to to the old 1.203c bios, but when i swapped from spectre win10 to spectre win11 earlier today the performance was suddenly back again 

Just a tip if anyone else is experiencing lower performance than they think they should have.. Try to reinstall windows


----------



## KedarWolf

domdtxdissar said:


> Wrote about it in the motherboard thread, but can share it here also.. After changing motherboard from ROG Crosshair VIII Hero to Unify X MAX without reinstalling windows i was struggling with lower than expect performance numbers in a few different benchmarks.. I thought it was down to to the old 1.203c bios, but when i swapped from spectre win10 to spectre win11 earlier today the performance was suddenly back again
> 
> Just a tip if anyone else is experiencing lower performance than they think they should have.. Try to reinstall windows
> View attachment 2543531
> 
> View attachment 2543532


What EDC, PPT, Scaler settings and all that you using?

You are getting the best numbers I've ever seen for CB23 etc.

Oh wait, you are using a fixed CCX overclock and manual voltages?

If that is Core Cycler and Y-Cruncher stable, I'd be amazed.


----------



## Veii

Once again for people that still doubt it
65c prochot throttle does exist


Spoiler






Code:


***HYDRA 1.1A PRO by 1usmus***
01/18/2022 23:07:14
Microsoft Windows NT 6.2.9200.0
AMD Ryzen 5 5600X 6-Core Processor
ASRock B550 Phantom Gaming-ITX/ax
BIOS ver. P2.20 SMU ver. 56.53.00
TABLE ver. 3672069
DRAM speed 4266 MHz


2 CCD's detected!


23:07:53: Boost testing started!
23:08:07: Boost testing finished!


HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4839    V 1.403    W 12.36    T 66.89
C02    F 4850    V 1.404    W 12.26    T 65.73
C03    F 4846    V 1.394    W 11.94    T 67.08
C04    F 4842    V 1.403    W 12    T 67.33
C05    F 4832    V 1.394    W 11.9    T 67.8
C06    F 4830    V 1.38    W 12.18    T 68.09


23:37:30: Boost testing started!
23:37:44: Boost testing finished!


HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4850    V 1.333    W 10.26    T 51.13
C02    F 4850    V 1.342    W 10.64    T 52.82
C03    F 4850    V 1.328    W 10.04    T 51.5
C04    F 4850    V 1.332    W 10.12    T 52.16
C05    F 4850    V 1.334    W 10.32    T 53.05
C06    F 4850    V 1.333    W 10.26    T 53.66


23:39:59: Boost testing started!
23:40:12: Boost testing finished!


HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4850    V 1.352    W 11.06    T 54.93
C02    F 4850    V 1.347    W 10.67    T 53.92
C03    F 4850    V 1.337    W 10.23    T 53.29
C04    F 4850    V 1.348    W 10.65    T 55.28
C05    F 4850    V 1.349    W 10.64    T 55.77
C06    F 4850    V 1.345    W 10.57    T 56.39




Went outside to let the room cool down to 40c idle
last was 42c idle
Still running the load powerplan tweak (100% usage 0% load)
















Sadly win still buggy on the latest update ~ but 0.4ns are "close". Target is still 10.4ns for 4.85Ghz










Microsoft Update Catalog




Microsoft Update Catalog


Update step by step, with a restart in between

Trying to port SMU 56.67 to the public
ASUS has a slightly different arrangement of SMU on AGESA 1206
But they are perfectly transplantable on bioses that have 1205
Trying to get it down to 1203C * without having to be affected by the voltage limiter (if it isn't already too late for people who updated)
* slight size issue here, maybe doable there is a lot of placeholder space in between, but might break hash and fail boot


----------



## MrHoof

KedarWolf said:


> You are getting the best numbers I've ever seen for CB23 etc.


Well... Yea... 5950x - R23 - 33058 pts - 4.9GHz all core OC on ALF 420 AIO and 3C ambient : overclocking (reddit.com)
u/Millosh_R

getting close tho probably doable for dom aswell at low enough temp.


----------



## Nighthog

New motherboard...

Ballistix MAX *4400CL19* 2x8GB stable @ *5100Mts* on first try when it booted.

Was just trying to see if it could even work on the board. 3 tries only after I verified 5000Mts booted first.


----------



## domdtxdissar

KedarWolf said:


> What EDC, PPT, Scaler settings and all that you using?
> 
> You are getting the best numbers I've ever seen for CB23 etc.
> 
> Oh wait, you are using a fixed CCX overclock and manual voltages?
> 
> If that is Core Cycler and Y-Cruncher stable, I'd be amazed.


Getting ~12k in r20 and ~32k in r23 with my everyday PBO CO settings which is stable in corecycler/y-cruncher (and i dont sacrifice my singlethread performance to do so )
PBO CO settings:

TDC = 180
EDC = 220
PPT = 350
Scalar = 10x


MrHoof said:


> Well... Yea... 5950x - R23 - 33058 pts - 4.9GHz all core OC on ALF 420 AIO and 3C ambient : overclocking (reddit.com)
> u/Millosh_R
> 
> getting close tho probably doable for dom aswell at low enough temp.


Have already been over 33k in R32 with max-bench static OC in ~20 degrees ambient..
But think i will do a real coldair bench in a few days, waiting until then to share max-bench static OC results 

That Millosh_R guy is such a sore loser.. He was reporting and got removed all my y-cruncher runs that was faster than his on hwbot because i was showing memory timings/stats with zentimings instead of useless CPU-Z memory tab.. Had to rerun everything to smash him lol 🤣

_edit_
btw, this is my ~1 year old previous PBO CO (coldair) record which was done on my much much worse binned 5950x (golden/bronze vs my new platinum/golden)









_edit2_
Run above is actually from *2021-01-23*


----------



## KedarWolf

domdtxdissar said:


> Getting ~12k in r20 and ~32k in r23 with my everyday PBO CO settings which is stable in corecycler/y-cruncher (and i dont sacrifice my singlethread performance to do so )
> PBO CO settings:
> 
> TDC = 180
> EDC = 220
> PPT = 350
> Scalar = 10x
> 
> Have already been over 33k in R32 with max-bench static OC in ~20 degrees ambient..
> But think i will do a real coldair bench in a few days, waiting until then to share max-bench static OC results
> 
> That Millosh_R guy is such a sore loser.. He was reporting and got removed all my y-cruncher runs that was faster than his on hwbot because i was showing memory timings/stats with zentimings instead of useless CPU-Z memory tab.. Had to rerun everything to smash him lol 🤣
> 
> _edit_
> btw, this is my ~1 year old previous PBO CO (coldair) record which was done on my much much worse binned 5950x (golden/bronze vs my new platinum/golden)
> View attachment 2543575


What do you have your voltages set at for CPU?


----------



## domdtxdissar

KedarWolf said:


> What do you have your voltages set at for CPU?


MSI LLC auto which is quite weak: ~over 10% vdroop when above 250 PPT
CPU voltages = think its called something like "AMD optimized " or "overclock optimized" in the MSI bios.. Cant remember and i'm at work now. It's basically stock voltages. (dont use any cpu voltage offsets atm)



> If that is Core Cycler and Y-Cruncher stable, I'd be amazed.


Can do a screenshot of 24/7 daily settings when i get home


----------



## KedarWolf

domdtxdissar said:


> MSI LLC auto which is quite weak: ~over 10% vdroop when above 250 PPT
> CPU voltages = think its called something like "AMD optimized " or "overclock optimized" in the MSI bios.. Cant remember and i'm at work now. It's basically stock voltages. (dont use any cpu voltage offsets atm)
> 
> 
> Can do a screenshot of 24/7 daily settings when i get home


Yes, BIOS screenshots when you can, please.


----------



## Reaxer

Seems like AGESA 1.2.0.5 (non beta) bioses are released for the Gigabyte boards. 
Would you guys recommend upgrading?


----------



## Veii

Reaxer said:


> Seems like AGESA 1.2.0.5 (non beta) bioses are released for the Gigabyte boards.
> Would you guys recommend upgrading?


As long as you don't have a B2 sample (as microcode is suspicious), idk
You have permanent voltage behavior changes from now on ~ and have to redo CPU & memOC







Asking here too
Anybody found
cpu00A20*F10*_ver0A20101*7*_2021-*07-19* Microcode ?


----------



## kim nk

cl13 trcrd13 We used the gskill cl17 4800 kit to achieve this. Above all, the kit yield was important to enable trcdrd13 to be achieved according to the RAM yield. And the board was the most important factor. The dark hero board helps you overclock memory better than the unity-x. There are many cases, but I'll show you some pictures first. And if it exceeds 4,200 clocks, there is a phenomenon of latency lagging. I think it's time for a board that can handle more than 4200 clocks, so I wonder what you think.


















4200 cl14 1.62v Memory used cl17 4800 G-skill Silver



























5600X 4200 14-15-8-12-21/리얼1T 48.3ns & TM5 20주기


먼저 이 씨퓨의 테스트 기회를 주신 두분 회원님께 깊이 감사드립니다멤컨 킹왕짱 5600X (2136SUS주차…




quasarzone.com








It's someone else's data that I haven't achieved.
Until the 4200 clock, latency is normal? He comes out as an enemy, but after 4,200 clocks, the latency increases.
But there's nothing more than tm5.

The difference between x570 dark hero vs unity-x is that unity-x has one step higher clock boot count. But I'm sure that the x570 dark hero board is a really good board. It was an opportunity to achieve cl144200 only with board differences. Unify-x 4200 cl14 failure ---> dark hero cl14 4200 success, but from 4266 all latency is stretched.

-----------------------------------------
Additional contents BCLK = 100.75 4231 clock latency 47.9ns. 
5600X 4231 14-15-8-12-22/리얼1T 47.9ns & TM5 (BCLK오버)


----------



## Audioboxer

Reaxer said:


> Seems like AGESA 1.2.0.5 (non beta) bioses are released for the Gigabyte boards.
> Would you guys recommend upgrading?


Actually, no, if you don't have any issues currently. AMD seem determined to hurt CPU overclocking on this new AGESA.

@domdtxdissar Do you have any idea what the MSI equivalent is for Gigabytes

CLDO12
1VSOC

You've probably seen the posts in here already but they helped another poster get tRCDRD 13 working at 3800 with DR.


----------



## KedarWolf

Reaxer said:


> Seems like AGESA 1.2.0.5 (non beta) bioses are released for the Gigabyte boards.
> Would you guys recommend upgrading?


1.2.0.5 has a voltage bug 1.2.0.3c doesn't.


----------



## Frosted racquet

KedarWolf said:


> 1.2.0.5 has a voltage bug 1.2.0.3c doesn't.


Both 1205 and 1206 have this "bug", hence it is more likely by design going forward.


----------



## Bix

Bix said:


> That's a good point - TPM was disabled on 1.2.0.3b by default but just found it's enabled for me on 1.2.0.5. Running TM5 again now with TPM disabled and everything crossed!


Think I'm getting to the bottom of my loss of stability switching from 1.2.0.3b to 1.2.0.5 now - disabling TPM in bios didn't make a difference (at least for me) but lowering VDDG CCD from 0.95 to 0.9V seems to have fixed things. 2x 25 cycles of TM5 passed now without errors and benchmark performance is back to where it should be. 

Symptoms for me were really random occasional TM5 errors without any kind of replicable pattern and WHEA 18 crashes in games and Geekbench 5. Bizarrely Y-cruncher was still passing fine, which it rarely did on 1.2.0.3 if the voltages weren't quite right.


----------



## Imprezzion

Well, these posts above seal the deal for me. I'm sticking to 2423 1.2.0.3c BIOS on the B550-XE. Everything is running stable and fast with very high PBO2 - offset (-25 all core) and running basically any game well over 4.8Ghz on all cores of the 5900X and memory 3866C15 1:1 with zero issues in any stress test so ain't touching it again. 

I do get a occasional WHEA but that's like 1 every 3-4 days so I can't be bothered to fix it. It's purely related to 1933 FCLK and it doesn't really affect real world performance with the very limited amount of times they occur.


----------



## Veii

Imprezzion said:


> I do get a occasional WHEA but that's like 1 every 3-4 days so I can't be bothered to fix it. It's purely related to 1933 FCLK and it doesn't really affect real world performance with the very limited amount of times they occur.










Can you check the value of this thing ?
It resets on a reboot
if it doesn't raise to 1000+ or you get 20-30 ones a sec
You are fine (optimally you get maybe 5 a day or 1h , not a sec)
WHEA #20 "should" mean, the error got corrected

I'm hoping with their voltage lock, they will try to combat overboost and all other strange issues
But knowing that this will also restrict how high you generally can clock (this includes hydra) ~ it's questionable
1.45v is technically fine, but 1.375 for a 5600X is rather questionable.

Somewhere it's fine, as good samples just need that much to run 5ghz on all cores
But on the other hand, there are many bad samples (5600X after all) which peak often to 1.4v (usually higher)
I think (see) AMD has no clue about it themself, and experiments what is fine and what to disable


Veii said:


> Asking here too
> Anybody found
> cpu00A20*F10*_ver0A20101*7*_2021-*07-19* Microcode ?


As this (version 16) already behaves the same way. I didn't see it, but it is
Think it has something to do with TPM but block is a bit too big for single features.
Will experiment with lower microcodes and try to make my own. Surely do not want a voltage restriction by updating
Even when it should be well minded
Voltage restriction without fmax increase and CO increase, is just a result in either equal perf on quality silicon or degraded performance on already unfortunate silicon
Not a good tradeoff tbh.
At least no FCLK boot lock

What they can do, is work on SOC clock for Vermeer too, not only Vermeer-S and Rembrand








Knowing how their Navi's behave:








Vclk, Fclk, Dclk,Phyclk had to get a slight increase ~ to prevent clock "choking" . While SOC Clk could decrease down to save power








Would like to see, if this really is a good resolve, as even higher LCLK would destabilize Freq and FCLK even further (while they had it up to 700mhz but limited down to 593 without notice)
We will see 
A bump on Vermeer would surely be a good change , if it hasn't happen already without noticing


----------



## domdtxdissar

When trying to extract the maximum performance = 100.25mhz baseclock lol








Working on adjusting PBO CO curve to accommodate new clockspeeds atm, seems like 1-2 CO ticks are needed across the board.


Audioboxer said:


> @domdtxdissar Do you have any idea what the MSI equivalent is for Gigabytes
> CLDO12
> 1VSOC


Pretty sure its these two








"Chipset soc voltage" and "chipset CLDO voltage"

Made no difference in regards to whea for me, haven't tried tRCDRD 13


----------



## Veii

domdtxdissar said:


> "Chipset soc voltage" and "chipset CLDO voltage"
> 
> Made no difference in regards to whea for me, haven't tried tRCDRD 13


Can see it helping for people who have issues with LCLK & PCH link instability
But then, there is just CBS -> NBIO -> SMU DPM LCLK levels for such 🤔

Maaybe against USB/Audio issues, that's also an unstable LCLK link
Should've been resolved now with 1205 or even 1203C


----------



## Audioboxer

domdtxdissar said:


> When trying to extract the maximum performance = 100.25mhz baseclock lol
> View attachment 2543761
> 
> Working on adjusting PBO CO curve to accommodate new clockspeeds atm, seems like 1-2 CO ticks are needed across the board.
> 
> Pretty sure its these two
> View attachment 2543760
> 
> "Chipset soc voltage" and "chipset CLDO voltage"
> 
> Made no difference in regards to whea for me, haven't tried tRCDRD 13


Hmm, interesting, I don't have that CHIPSET CLDO Voltage option










Try and have a play around with them Dom and see if you can get tRCDRD 13 working.


----------



## Mach3.2

Veii said:


> View attachment 2543714
> 
> Can you check the value of this thing ?
> It resets on a reboot
> if it doesn't raise to 1000+ or you get 20-30 ones a sec
> You are fine (optimally you get maybe 5 a day or 1h , not a sec)
> WHEA #20 "should" mean, the error got corrected


What's the significances of MP5_BUSY? 

Mine is currently at 171307.000, my PC has been on for 2 days and 21 hours.


----------



## Veii

Mach3.2 said:


> What's the significances of MP5_BUSY?
> 
> Mine is currently at 171307.000, my PC has been on for 2 days and 21 hours.


It logs errors, and will report such as WHEA after some threshhold
I barely exceed 50 for 24h, often it's in the 40s

I'm not over 90% confident on what exactly it logs
but it logs errors for sure & resets on a reboot


----------



## kompira

domdtxdissar said:


> When trying to extract the maximum performance = 100.25mhz baseclock lol


Yep, 101MHz baseclock on my old Zen1


----------



## PJVol

Veii said:


> it logs errors


How the connection of MP5 and WHEA was established? Does WHEA has any indication of mp5 as a source?


----------



## nada324

Hey, almost stable, now i get only error 11

Vdimm: 1.52v

SR viper 2x8











Checked Error 11 in Vei's thing but its not heating issue,neither TFAW.

Maybe cad bus are wrong?


----------



## domdtxdissar

MrHoof said:


> Well... Yea... 5950x - R23 - 33058 pts - 4.9GHz all core OC on ALF 420 AIO and 3C ambient : overclocking (reddit.com)
> u/Millosh_R
> 
> getting close tho probably doable for dom aswell at low enough temp.


Easy 😇








Not cherry picked runs ran by by one, with settings only tweaked for either ST or MT performance like some  
TechN AM4 block with LM on custom watercooling


----------



## KedarWolf

domdtxdissar said:


> Getting ~12k in r20 and ~32k in r23 with my everyday PBO CO settings which is stable in corecycler/y-cruncher (and i dont sacrifice my singlethread performance to do so )
> PBO CO settings:
> 
> TDC = 180
> EDC = 220
> PPT = 350
> Scalar = 10x
> 
> Have already been over 33k in R32 with max-bench static OC in ~20 degrees ambient..
> But think i will do a real coldair bench in a few days, waiting until then to share max-bench static OC results
> 
> That Millosh_R guy is such a sore loser.. He was reporting and got removed all my y-cruncher runs that was faster than his on hwbot because i was showing memory timings/stats with zentimings instead of useless CPU-Z memory tab.. Had to rerun everything to smash him lol 🤣
> 
> _edit_
> btw, this is my ~1 year old previous PBO CO (coldair) record which was done on my much much worse binned 5950x (golden/bronze vs my new platinum/golden)
> View attachment 2543575
> 
> 
> _edit2_
> Run above is actually from *2021-01-23*


Can you post BIOS screenshots of your voltage settings for CPU, your CPU ratio at the top, and your EDC and Scaler etc.?


----------



## sealxohd

Since I have my 3800 setting stable now, I want to aim for high FCLK. Im at 2033 and MP5_BUSY is at 36. I get one WHEA every 2 minutes but every 2.5 minutes a 101 WHEA stack. LCLK is going crazy but I cant find the function to disable the LCLK downclock on the Master. Any ideas how I could fix these 101 WHEA stacks? VDDG voltages are pretty optimized.


----------



## Luggage

domdtxdissar said:


> Easy 😇
> View attachment 2543887
> 
> Not cherry picked runs ran by by one, with settings only tweaked for either ST or MT performance like some
> TechN AM4 block with LM on custom watercooling


Yea but you still need to use the winter air some day with this chip 
+1 for TechN and LM


----------



## domdtxdissar

KedarWolf said:


> Can you post BIOS screenshots of your voltage settings for CPU, your CPU ratio at the top, and your EDC and Scaler etc.?


Sure i can  but there is nothing special to see
_edit_
(This are my daily 24/7 settings, not the one used to break 33.7k in cinebench r23)



Spoiler: pictures














































Luggage said:


> Yea but you still need to use the winter air some day with this chip
> +1 for TechN and LM


Runs above were with cold air 
~60 degrees loadtemp in Cinebench r23 multithread


----------



## blodflekk

TheRamGuide-WIP-/Advanced Timings.md at main · RAMGuide/TheRamGuide-WIP-


This repo is for info regarding computer DRAM. Contribute to RAMGuide/TheRamGuide-WIP- development by creating an account on GitHub.




github.com





I was given this guide by someone offering me assistance in understanding timings, it contradicts a lot of what is said in this thread. I'm curious the thoughts of those that have a good understanding of DDR4


----------



## Audioboxer

blodflekk said:


> TheRamGuide-WIP-/Advanced Timings.md at main · RAMGuide/TheRamGuide-WIP-
> 
> 
> This repo is for info regarding computer DRAM. Contribute to RAMGuide/TheRamGuide-WIP- development by creating an account on GitHub.
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> I was given this guide by someone offering me assistance in understanding timings, it contradicts a lot of what is said in this thread. I'm curious the thoughts of those that have a good understanding of DDR4


Certainly interesting skimming that, but I'm not going out on a limb to call out anyone here. There seems to have long been a lot of fighting and fallouts in the OCing community over memory, I'll just hang on the sidelines and do benching, because if a bench produces a good result and the memory is stable, I'm happy.

Still, this is interesting



> Common myths: tRFC should be a multiplue of tRC, in most cases 7 or 8. This rule is completely incorrect.


But the author doesn't really expand on what they're claiming is valid, unless they just imply any value at all that proves stable.


----------



## ManniX-ITA

blodflekk said:


> I was given this guide by someone offering me assistance in understanding timings, it contradicts a lot of what is said in this thread. I'm curious the thoughts of those that have a good understanding of DDR4


I only have an average understanding but maybe using a car analogy can be enlightening 
Most of this stuff it's based on JEDEC specifications.
It's like engineering an engine for a commercial car that can certified to run on public streets and comply with eco regulations.
Here those JEDEC rules are broken and bended, like tuning a supercar engine for track racing.
It's a different world.


----------



## domdtxdissar

blodflekk said:


> TheRamGuide-WIP-/Advanced Timings.md at main · RAMGuide/TheRamGuide-WIP-
> 
> 
> This repo is for info regarding computer DRAM. Contribute to RAMGuide/TheRamGuide-WIP- development by creating an account on GitHub.
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> I was given this guide by someone offering me assistance in understanding timings, it contradicts a lot of what is said in this thread. I'm curious the thoughts of those that have a good understanding of DDR4


Dont really see any contradictions with a quick look through the guide.. (?)
Think it describes exactly how i tune my memory and what i have benchmark'ed to be the fastest ?


----------



## sealxohd

domdtxdissar said:


> Dont really see any contradictions with a quick look through the guide.. (?)
> Think it describes exactly how i tune my memory and what i have benchmark'ed to be the fastest ?
> View attachment 2544020


How do you get your latency so low with 2 CCDs active? Im brickwalling at 54.X ns. With only one CCD active I can do sub 50.


----------



## domdtxdissar

sealxohd said:


> How do you get your latency so low with 2 CCDs active? Im brickwalling at 54.X ns. With only one CCD active I can do sub 50.


Forcing affinity in Hydra/CTR
Aida64 dont measure anything, it tries to "calculate" what your numbers should be


----------



## blodflekk

The big one for me was explaining tRAS, I've always been told it is tRAS=tCL+tRCDRD right back since DDR4 launched.


----------



## ManniX-ITA

blodflekk said:


> The big one for me was explaining tRAS, I've always been told it is tRAS=tCL+tRCDRD right back since DDR4 launched.


That's actually the most interesting part but also the one I think highly questionable...

Let me quote:



> Common 'rules' for a minimum tRAS I have heard are the following:
> 
> CL + tRCD = tRAS
> 
> CL + tRCD + 2 = tRAS
> 
> CL + tRCD + tRP = tRAS
> 
> CL + tRCD + tRTP = tRAS
> 
> tRAS + CL + tRCD = tRAS
> 
> CL + TRCD + TRRD + TRP = tRAS
> 
> These are just a few examples of the many incorrect rules people have made up, usually from misunderstanding the basics of this timing. *The objective fact is every single one of these 'rules' for what you should either set tRAS to or use as a minimum tRAS value are entirely false and hold no truth to them at all*.


And then immediately after:



> If your system allows you to set it to something very low such as 2 or 3 *and you do not need a tRAS limit for stability*, those values will work just fine.


Of course the above "incorrect rules" are all about a way to find a tRAS value that works, is fast and is stable.
Seems to be the whole paragraph is just about "demystifying"...

What is the answer given at the end?



> Thus, if tRAS is below or equal to tRCDWR + tCWL + BC + tWR or tRCD + tRTP (*whichever is highest*) the tRAS timing has absolutely no effect on anything.


This is what is written in the JEDEC specs...
Which is not even remotely close to what is for real the minimum tRAS value (except maybe for very cheap memory kits).

For my 16-16-16-32-48 profile that would be 48 instead of 32.

And of course tRAS min can be and does have an effect even below.

But you need to test it and run hours of TM5 to know it...
Maybe I'm wrong but seems to be, again, a theoretical dissertation from someone that didn't really spent much time on memory OC, if not at all.


----------



## sealxohd

domdtxdissar said:


> Forcing affinity in Hydra/CTR
> Aida64 dont measure anything, it tries to "calculate" what your numbers should be


Sorry but im stupid How do you force affinity in Hydra? I never used it and google doesnt help me.


----------



## nada324

Hey all, ̶F̶i̶n̶a̶l̶l̶y̶ ̶g̶o̶t̶ ̶F̶C̶L̶K̶ ̶2̶0̶0̶0̶ ̶w̶i̶t̶h̶o̶u̶t̶ ̶N̶o̶ ̶W̶h̶e̶a̶, false alarm; 










@ManniX-ITA i get no perfomance impact, can i use your tool?

Also might test @Veii bios settings to help to reduce them.

Vipers 2x8 SR

With @Veii recommended setup times / cad bus and RTT for SR and for 4000mhz (TCKE 11, 4-4-18)

Got error #11 and #13 before in tm5 with @1.51vdimm but fixed it with less vdimm @1.48v

Now maybe i should try to get to 4000 15-15 flat but maybe lot of Vdimm is needed and should focus on secundaries now.

When the ram Fans arrive i would try to get 4000 15.....











Having bit hard time of making secundaries tighter, error #10 only one after 30min of testing

TWR seems fine

EDIT: TRDWR 8 ->9 fixed it.


----------



## pietro3d81

Hi, finish all diagnostic tests in Hydra. Set all core game profile. But my 5950x stay at 4800 mhz for one seconds then all core go back to 4300. Someone know how?
Maybe a setting in bios? Pbo in bios is disable. My motherboard is asus b550-f
Help me.


----------



## Veii

PJVol said:


> How the connection of MP5 and WHEA was established?
> 
> 
> Veii said:
> 
> 
> 
> I'm not over 90% confident on what exactly it logs
> but it logs errors for sure & resets on a reboot
Click to expand...

Observation
WHEA are a packaged report of an/multiple issue, not the issue itself


blodflekk said:


> TheRamGuide-WIP-/Advanced Timings.md at main · RAMGuide/TheRamGuide-WIP-
> 
> 
> This repo is for info regarding computer DRAM. Contribute to RAMGuide/TheRamGuide-WIP- development by creating an account on GitHub.
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> 
> 
> tREFI is the average periodic refresh interval for the DRAM. Meaning on average every tREFI there will be a refresh command addressed. Refresh commands however can be postponed up to 8 times on DDR3 & DDR4 and 4 times on DDR5. These refreshes are postponed, not cancelled.
> 
> This timing can be very performance impactful in situations where tREFI is at Jedec or low such as when using a Ryzen system as Ryzen systems do not allow for tREFI to be modified from Jedec spec.
> 
> Common myths: tRFC should be a multiplue of tRC, in most cases 7 or 8. This rule is completely incorrect.
Click to expand...

From someone who tries to translate JEDEC, that leans out of the window to show "understanding" of how AMD calculates tREFI
(which is half correct ~ as it's 6x on AMD down to 4 ~dynamic~. AMD does not hold to JEDEC for tREFI)
Gets quite secure to also lean even further and write an assumption understanding how tRFC mini module works
tRC is an anchor point for something else. As it was tCL at first. tRFC recommended is an result based on charge loss prediction, that "happens to fit" perfectly with tRTP.
Hence tRC is a product of tRP and tRAS ~ it requires tRP and tRAS to be stable on their own.
This requires tRTP to be correct on their own
If user extends all 5 chains, puzzle pieces fit together.

If user struggles with thermal discharge, user increases tRP ~ hence increases tRC
If user struggles with rank transition, well capacity so to speak ~ user increases tRTP = increases tRAS = tRC has to increase

In general, for it to function it requires tRC to be "correct" and expects tRAS to be correct.
Although observation on tRAS min differ and tRCD+tRTP works only under specific circumstances depending on tRDWR, (tRRD_ & tWTR) _L state
Soo there are exploits where tRC can be +1 tCK.
This same exploit for tFAW (1x) depend on tRAS and tRC (together). Both valid, both functional, but not understood by guide writer.
Yet apparently understood/imagined & judged ~ based on a formula he made up about tRFC mini (discharge mini) Tool 

tRFC "recommendations" , remain up to IC different and so up to IC will tRCD,tRAS,tRC,tRTP be different
It "happens" to fit all very correctly together (soo calculation steps are skipped [result = result] and shorter route was taken)
Sadly as tCL is too voltage dependent ~ it can not be correctly used for the actual goal of the tRFC result & got as sideoption/side-anchor only.
The "calculator" name is then finished by being sure tRFC result is correct (as -1 nCK means error) ~ independent of which anchor point was used for discharge prediction *
It "also happens" to have no need for VDIMM specification ~ making it more user friendly. Independent of engineers understanding the connection or not.
* the only goal was to get a correct tRFC ↹ tRFCns module, as fix for DRAM Calculator having a rounding issue.
(the rest was a bonus ~ but would also work if user input VDIMM and target tRFC of +/- 32 value. My approach is different for the same result) 

Only fools judge, and remain fools ~ without getting into contact with me to understand the reason for the anchors. Blind made up judgement, is bad judgement
There is no mirrored connection. There is an out-of-the box connection and anchor will change once i can create the timing (i need for discharge calculation) out of thin air.
(aka understand transitions perfectly and can simulate when tREFI is enough ~ without it being an "open average")

That's all there is to say about it. A borrowed module that happen to fit all calculations nicely together and can skip them entirely.
Only needs for user to get tRC correct (tRAS+tRP) the rest of the puzzles or requirements for prediction, fall together without needing calculations and so potential rounding-error points
* oh i should remind, that it works perfectly on DDR3 too, where tRC doesn't exist ~ if you do the math in the head & doesn't post if value is 1 off. But what do i know 😇







Maybe it was a mistake, sharing unfinished project ~ which half-way Arshia only starts to understand.
While being a fool at first too, speaking bad without getting in touch with me ~ then excused himself
Maybe i am a fool, for helping a community of already "non-self thinking" engineers, that can only quote documents without alternative attempts and observations

EDIT:
Don't forget, tRC is a made up virtual value
Soo using a virtual value as virtual anchor ~ really should have put some thought in critique writers mind. DDR doesn't "need" tRC to function and do it's transitions
Soo "discharge mini" tool, doesn't need tRC anchor to function
But it's much more simple than using VDIMM and tCL.
When you can skip calculation steps as [result equals result] , skip calculation steps 📑

EDIT2:
Guide writer also forgot that tRC has to elapse.
It can't be time broken, unless maybe DDR5 can.
Soo quote


> *At what value does tRC start to do nothing?*
> tRC like tRAS has a value at which the timing stops doing anything. This value for tRC is: tRAS + tRP


Can not be true, as tRC can not be time-broken once specified and has to elapse.
This is a state where DRAM ~waits~ for action.
A too high value higher than tRAS+tRP, will so also "hide" errors
Unlike tFAW, which can ! , be time-broken if value is too high. But "shouldn't" (i hope) , be made-up and extended out of thin air ~ if too short. Not in DDR4 at least


----------



## Veii

Posting something more positive, although too early
Maybe only "slightly" positive, not more.








This is Dual Rank.
AMD "forgot" to follow again JEDEC - or rather got too lazy and forgot to extend memory training
Anything beyond JEDEC 1800 MCLK strap, misses logic how to work with Hi-Z. It simply refuses to post even 1mhz higher
Slightly lazy  but big times sad.
It could've been great.
_(Can't expect AMD to be overclocker friendly. Can't put out such demand. They follow their specs, and not more than that)_

Sticking my nose now on Setup Timings, as tCKE range seems to be perfect & finished now ~ for Dual Rank
Also a warning ! Do not use high VDIMM with this !
3600 15-15 barely needs 1.25vDIMM 
14-14 around 1.36ish

Also have a suspicion that thanks to Dynamic ODT,
On-Dimm CRC (feature indepedent of ECC) , actually get's used and adds quite some latency
If RTT_WR is enabled
















Also lovely buggy firmware prediction
(tertiaries auto)








The more i dig into it, the more problems appear of what AMD "forgot" to implement ~ or rather "extend" beyond 3600MT/s JEDEC
This starts with tRFC2/4 only being correct till 3600MT/s & corresponding temp dependent operation mode being half-functional


----------



## PJVol

Veii said:


> Observation
> WHEA are a packaged report of an/multiple issue, not the issue itself


I see. But doesn't whea has strict description of the data block it provides?
I'm asking because i've been parsed #19 events before, which always were generated in response to the MCA exception raised by PIE in my case (mca bank 27), and it was clearly stated in the data block. So i assumed that the error data were in banks 15 for threads 0 and/or 1 if it was mp5.
Can you post the error data for it?


----------



## T884G63

Hello everyone, been awhile since I posted.

I finally took some time the last few days to see what my Unicorn of a 5950x that defies all logic (posted and booted all fclk @ 1:1 up to 2133 across every bios update on auto voltage and less than 1.2 vsoc with sub 1v iod sub 900mv ccd vddp) can actually do....

Is this the first Vermeer to break past 2133 fclk?









(Ignore timings there from a 4666 profile)


----------



## kim nk

T884G63 said:


> 안녕하세요 여러분, 오랜만에 포스팅을 합니다.
> 
> 마침내 지난 며칠 동안 모든 논리





T884G63 said:


> Hello everyone, been awhile since I posted.
> 
> I finally took some time the last few days to see what my Unicorn of a 5950x that defies all logic (posted and booted all fclk @ 1:1 up to 2133 across every bios update on auto voltage and less than 1.2 vsoc with sub 1v iod sub 900mv ccd vddp) can actually do....
> 
> Is this the first Vermeer to break past 2133 fclk?


As expected, dark hero is a great board. The 4298 clock cl14 point, which I know now, was booted up to 4466 clock, but the latency was stretched. The latency in the early and mid 47s should come out, but it's struggling.
First of all, the highest booting on the 550 Unify-x was 4466 clocks, and the x570 dark hero board had 4400 clocks at the highest booting point. However, the dark hero has better performance, but it feels like the 4-slot bodra latency is not as good as the 2-slot board. My acquaintance is suffering from a normal bandwidth at the 4298 clock, but the latency is increasing.


----------



## kim nk

This is a collection of links that caught more than 4000 "WHEA" errors with the x570 dark hero board. Most errors were caught only when PLL1.8 voltage was touched. Other boards raise this value and the list of boards that have been effective is 550 UNTFY-X, 550 ROG XE, but not as much as Dark Hero.









5800x 4066클럭 CL14 / WHEA No Errors / 레이턴시 49.8


사용한 하드웨어CPU : AMD RYZEN 5800x 47.75배수 / 1.375v / LLC4 130%C…




quasarzone.com














(8GBx4 풀뱅) 5800X 4000 14-15-8-12-22/리얼1T


5800X(2133SUS주차)에 지스킬 4800CL17(1.60V, 8GBx2) 두셋트로 풀뱅크 구성입니다풀…




quasarzone.com













5600x 4133 cl14 no whea 오류 성공후기


4000이상 올라갈수록 건들어야 할게 많아지네요..cpu 는 오버 안했습니다. cpu까지 오버하면 힘들어져서…




quasarzone.com













5800X 수동49.5배수, 4200 CL15 / 레이턴시 48.1ns


어느 고수분의 소개로 젠3 램오버 결과를 올려볼 수 있는 링크를 알게 되었습니다.https://docs.go…




quasarzone.com






There are more links, but all are on dark hero boards, and both pll1.8 voltage and soc ,vddg ,cldo_vddp should be touched, but touching pll1.8 voltage was the best effect to eliminate the "WHEA" error.
These are CPUs with a "WHEA" error. However, it was removed through PLL and SOC VDDG control in the 4000 clock section. There are CPUs that do not make this error from the beginning, but cases that catch errors can only be eliminated if the board is good, but the limitation of dark heroes is 4,200 clocks, but if you go up, the latency It's too loose. .


----------



## T884G63

Trying out some Asynchronous


----------



## T884G63

kim nk said:


> This is a collection of links that caught more than 4000 "WHEA" errors with the x570 dark hero board. Most errors were caught only when PLL1.8 voltage was touched. Other boards raise this value and the list of boards that have been effective is 550 UNTFY-X, 550 ROG XE, but not as much as Dark Hero.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 5800x 4066클럭 CL14 / WHEA No Errors / 레이턴시 49.8
> 
> 
> 사용한 하드웨어CPU : AMD RYZEN 5800x 47.75배수 / 1.375v / LLC4 130%C…
> 
> 
> 
> 
> quasarzone.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> (8GBx4 풀뱅) 5800X 4000 14-15-8-12-22/리얼1T
> 
> 
> 5800X(2133SUS주차)에 지스킬 4800CL17(1.60V, 8GBx2) 두셋트로 풀뱅크 구성입니다풀…
> 
> 
> 
> 
> quasarzone.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 5600x 4133 cl14 no whea 오류 성공후기
> 
> 
> 4000이상 올라갈수록 건들어야 할게 많아지네요..cpu 는 오버 안했습니다. cpu까지 오버하면 힘들어져서…
> 
> 
> 
> 
> quasarzone.com
> 
> 
> 
> 
> 
> There are more links, but all are on dark hero boards, and both pll1.8 voltage and soc ,vddg ,cldo_vddp should be touched, but touching pll1.8 voltage was the best effect to eliminate the "WHEA" error.



Ya I noticed that early on after the original Dark Hero launch that my board was automatically increasing PLL 1.8 when I was overclocking fclk and was topping out at 1.9v on earlier bios versions.

Current bios is now upping to 2v when on auto I bumped it to 2.03 when hitting 2167 fclk to get past posting and to boot into windows.


----------



## kim nk

T884G63 said:


> Ya I noticed that early on after the original Dark Hero launch that my board was automatically increasing PLL 1.8 when I was overclocking fclk and was topping out at 1.9v on earlier bios versions.
> 
> Current bios is now upping to 2v when on auto I bumped it to 2.03 when hitting 2167 fclk to get past posting and to boot into windows.


I've seen a lot of cases where auto prices block booting. manually adjusted and PLL1.8 voltage without boot values and errors This seems to have different bootable values depending on the memory controller yield. Some cpu may be caught by raising it to catch a "WHEA" error, some cpu may be caught by lowering it, and the PLL voltage value required for booting and eliminating errors seem to be different.


----------



## T884G63

The main thing is with the "Clock Stretching" L1,L2,L3 Cache Latency change I'm just not sure if it is really detrimental as we can see that with Cezanne L1,L2,L3 Cache Latency is higher overall
and they are consistently hitting 2300-2400 fclk...


----------



## blodflekk

Currently sitting here. vDIMM 1.53v I was able to pass 50cycles of tm5 1usmus and no issues with y-cruncher either. Was aiming for 1000% HCI memtest before calling it stable. Is this a voltage issue or drive strengths? PBO disabled. Boots 1T with addrcmdsetup 56 but isn't stable and trains tPHYRDL at 26/32


----------



## T884G63

From my personal experience on your motherboard for 3800C14 1:1 I would first try 
lowering your IOD 1.020v CLDO to 0.890 and raise CCD to 0.930 put RTT's on auto
put it in 1T and turn on GDM


----------



## blodflekk

I have lowered IOD and raised CCD, will test over night. I found I needed that CLDO bump earlier in my testing


----------



## T884G63

blodflekk said:


> I have lowered IOD and raised CCD, will test over night. I found I needed that CLDO bump earlier in my testing


Right but CLDO should either be the same or lower than CCD and 1T GDM on is easier and faster.


----------



## blodflekk

I don't want to use GDM, I don't want to lose the performance benefit of the tighter odd timings by having them rounded up to even


----------



## PJVol

T884G63 said:


> The main thing is with the "Clock Stretching" L1,L2,L3 Cache Latency change I'm just not sure if it is really detrimental


CKS easily mitigated by decreasing load-line resistance (more agressive llc) on my board, though it may be vrm specific. Cache latencies usually changes due to EDC throttling, so it might have sense to play with EDC limits (for both vdd and vsoc), since afaik L2/L3 dldo's are powered from vdd as well (not vddm).
I see the most problematic side-effect of high fclk is throttling somewhere down the ccm -> iod path, that can cripple performace in a certain scenarios.


----------



## T884G63

I'm not sure it's VRM related since the only board's I know that have better VRM's than the Dark Hero are the Extreme and the EVGA

So far opening up LLC's and and limits has had zero change on the latency at higher fclk but I will try putting it in LN2 mode for good measure.


----------



## PJVol

1) I said LLC help to minimize CKS, not a L3 latency, and the vrm quality doesn't nesessarily matter here
2) I mean try to decrease EDC limit to avoid throttling, not just "open" it.


----------



## jcpq




----------



## rossi594

I saw this kit poping up in a sale and was suprised by the 1.6v XMP profile (it is listed as Samsung B-Die and has low TRCD, I know that some Hynix can go up to 1.6v as well)








F4-4800C17D-16GTRS - Specification - G.SKILL International Enterprise Co., Ltd.


Trident Z Royal DDR4-4800 CL17-19-19-39 1.60V 16GB (2x8GB)




www.gskill.com





I would like to know how much voltage tolerance varies with Samsung B-Die (because the recommendation usually is not to exceed 1.5v daily).
Did you guys ever "kill" Samsung B-Die when adiquatly cooled and if so at which voltage?


----------



## MrHoof

rossi594 said:


> I saw this kit poping up in a sale and was suprised by the 1.6v XMP profile (it is listed as Samsung B-Die and has low TRCD, I know that some Hynix can go up to 1.6v as well)
> 
> 
> 
> 
> 
> 
> 
> 
> F4-4800C17D-16GTRS - Specification - G.SKILL International Enterprise Co., Ltd.
> 
> 
> Trident Z Royal DDR4-4800 CL17-19-19-39 1.60V 16GB (2x8GB)
> 
> 
> 
> 
> www.gskill.com
> 
> 
> 
> 
> 
> I would like to know how much voltage tolerance varies with Samsung B-Die (because the recommendation usually is not to exceed 1.5v daily).
> Did you guys ever "kill" Samsung B-Die when adiquatly cooled and if so at which voltage?


Most of us run over 1.5v daily here, myself 1.55v. After 1.5v you should probably add a fan tho or have really good airflow over your ram anyway.


----------



## T884G63

PJVol said:


> 1) I said LLC help to minimize CKS, not a L3 latency, and the vrm quality doesn't nesessarily matter here
> 2) I mean try to decrease EDC limit to avoid throttling, not just "open" it.


Whats the theory behind the too high or too low limit's causing throttling? 

Are we talking internal die regulators dialing back due to too much circuit throughput? Or artificial software limiting?


----------



## T884G63

rossi594 said:


> I saw this kit poping up in a sale and was suprised by the 1.6v XMP profile (it is listed as Samsung B-Die and has low TRCD, I know that some Hynix can go up to 1.6v as well)
> 
> 
> 
> 
> 
> 
> 
> 
> F4-4800C17D-16GTRS - Specification - G.SKILL International Enterprise Co., Ltd.
> 
> 
> Trident Z Royal DDR4-4800 CL17-19-19-39 1.60V 16GB (2x8GB)
> 
> 
> 
> 
> www.gskill.com
> 
> 
> 
> 
> 
> I would like to know how much voltage tolerance varies with Samsung B-Die (because the recommendation usually is not to exceed 1.5v daily).
> Did you guys ever "kill" Samsung B-Die when adiquatly cooled and if so at which voltage?


If the kit has been rated for 1.6v then it's good for at least 1.65-1.7v

Generally almost all of the custom A2 pcb's will do 2v will with decent cooling.

And as always just because a few of a certain kit model # has been reviewed or seen with B-Die doesn't
guarantee that the model # will remain as B-Die throughout the model # life.

Though generally G.Skill is remaining the highest consistent B-Die throughout there product lines.


----------



## blodflekk

Still getting errors in HCI memtest. 28 at 1000%. Does this mean its more likely IF since its passing tm5 50 cycles ?


----------



## andremoreira6215

Hey guys my first post here I think, I have learned and the past year a bit of ram oc in some fóruns and with some help i got a nice result. Any advices and tips for improve has welcome.


----------



## PJVol

T884G63 said:


> Whats the theory behind the too high or too low limit's causing throttling?


Why theory? It's been known for a while, amd has implemented "smart" EDC manager in their CPUs since Zen2, that helps to combat Cac spikes (and hence skyrocket EDC) due to its fp/avx engine is now twice as wide (256 bit).
Of course, too low EDC limit will decrease perf. either, but in this case, it would be clock-gated by the CKS.


T884G63 said:


> Are we talking internal die regulators dialing back due to too much circuit throughput?


Partly yes. Zen2/Zen3 PDN is quite complex and power-gating used along with a clock-gating, apart from the usual power-saving ACPI features. And we didn't even start to look at the bigger picture, when fabric (SDF/SCF) and the huge complexity phy underlying it, IOHC, ddr phy, etc. should be factored in.


----------



## T884G63

PJVol said:


> Why theory? It's been known for a while, amd has implemented "smart" EDC manager in their CPUs since Zen2, that helps to combat Cac spikes (and hence skyrocket EDC) due to its fp/avx engine is now twice as wide (256 bit).
> Of course, too low EDC limit will decrease perf. either, but in this case, it would be clock-gated by the CKS.
> 
> Partly yes. Zen2/Zen3 PDN is quite complex and power-gating used along with a clock-gating, apart from the usual power-saving ACPI features. And we didn't even start to look at the bigger picture, when fabric (SDF/SCF) and the huge complexity phy underlying it, IOHC, ddr phy, etc. should be factored in.


Was an honest question as zen 3 is my first time back on AMD since the K7 Athlon and it has been quite a learning experience overclocking all 4 Vermeer sku's
and the never ending balancing of settings moving up in clocks compared decades of overclocking intel where we just overpower everything and sub ambient cool it.


----------



## PJVol

T884G63 said:


> Was an honest question as zen 3 is my first time back on AMD since the K7 Athlon


Yeah. I still remember Barton XP 2600 in a 2004 iirc, that was turned into the XP 3200 in a couple of seconds by raising multiplier, lol. Though, first amd chip was K6 (then P3). Good old days )


----------



## toljan2884

скажите мне, что может сказать мне, что можно изменить? память не хочет начинаться с 1T с отключенным GDM


----------



## andremoreira6215

andremoreira6215 said:


> View attachment 2544450


Change tRTP = 6 and tWR = 12

Any advice to improve my b die g.skill 3600 cl16?


----------



## rossi594

andremoreira6215 said:


> Change tRTP = 6 and tWR = 12
> 
> Any advice to improve my b die g.skill 3600 cl16?


GDM off, but good luck on that one. Maybe try gdm off t2 first.

Or go dual ranked. Much easier =)


----------



## Audioboxer

Thanks to @domdtxdissar tip about running DrvStr at all 20, I've finally managed to boot above 4400










But it's booted at 28/32 on tPHYRDL which isn't great :/

I presume with some tweaking of timings/Rtts/Proc/voltage that might be able to be fixed.

@Veii Any tips on what might help lower DIMM B to 28 above?


----------



## Audioboxer

What a weird hour of testing this has been. So 28/32 wasn't budging at all with voltage changes or "traditional" Rtts. The best I managed to achieve was 28/30 if using something like 7/2/4. It seems reducing RttPark has a direct impact on tPHYRDL at this frequency. Thing is, 7/2/5 and even 7/2/6 wasn't shifting off 28/30.

The only way I've managed to get 28/28 to work is Disabled/1/6. I have absolutely no idea how safe this combination is, RttWr seems really high at 240 ohms. Disabled/2/6 has issues booting cleanly.

Not tried stability testing yet, very good chance it's unstable as hell. Also worried if running Rtts like that_ could_ be dangerous under high load. But really interesting to see what I seemed to need to do, to achieve 28/28.

Lastly, this is the first time my memory has ever booted tWRRD 1. Usually doesn't post below 2. It's on auto above, so picked 1 itself


----------



## Audioboxer

Ignore the tRFC freaking out because it was using 4467 settings, and the 28/30, uhhh, @domdtxdissar and @Veii, 4533 booting on DR. Seems its down to Rtts and/or DrvStr? 4600 is proving a bit trickier, but who knows with more tinkering...

edit -



















Boots at 30/30 with tRFC dropped down... No way tCL15 will be stable at 4533 though lol.

edit 2 - more findings










Dropping the DrvStr to all 20s might help boot above 4400 when Rtts stay the same, but as you can see above if Rtts radically change, DrvStrs are not an issue any more. Reason I am testing this is a few goes at 4466 and 4533 are showing some positivity but TM5 errors on 14. 20/20/20/20 is likely to be too weak on ClkDrvStr and CkeDrvStr and result in powerdown issues.

@domdtxdissar As above DrvStrs don't *need* to be all 20's. But messing with DrvStrs can also bring about tPHYRDL issues again  I've had 30/28 at 4533. Yes, 30 on A, 28 on B. It's holding at 30/30 just now.


----------



## Audioboxer

Last post for tonight, more of a proof of concept than anything serious, nearly everything on AUTO got 4600 booting.

Takeaway for this evening seems to be it's ProcODT/Rtts that stop DR going above 4400, or hitting a wall around there. Next step is the bigger challenge, can anything be stable at disabled/1/6? And is it even safe? I don't know enough about Rtts to make a comment.

Going to need your help @domdtxdissar and @Veii to figure this out!


----------



## Veii

Sorry,
Soo i've been collecting a long answer for some days , but going on on mobile and checking ~ literally wipes the written, cached post.
Not good experience, OCN :/


PJVol said:


> I see. But doesn't whea has strict description of the data block it provides?
> I'm asking because i've been parsed #19 events before, which always were generated in response to the MCA exception raised by PIE in my case (mca bank 27), and it was clearly stated in the data block. So i assumed that the error data were in banks 15 for threads 0 and/or 1 if it was mp5.
> Can you post the error data for it?


Sorry , i don't know if i can help you
While i do understand how to work in patterns, and give logic to code ~ without having to understand the code
~ i am no programmer
Haven't seen the shortcuts you tell me, and can not make out anything out of it.

Can not understand you 🙇‍♂️


Audioboxer said:


> @Veii Any tips on what might help lower DIMM B to 28 above?
> 
> 
> Audioboxer said:
> 
> 
> 
> The best I managed to achieve was 28/30 if using something like 7/2/4. It seems reducing RttPark has a direct impact on tPHYRDL at this frequency. Thing is, 7/2/5 and even 7/2/6 wasn't shifting off 28/30.
Click to expand...

Correct
tPHY changes upwards, if dimms are overpowered too
This is in-line with running stronger PARK ~ but will happen if VDIMM is too high or ClkDrvStr, or cLDO_VDDP is too high
You can balance this down by wiggling with ClkDrvStr and cLDO_VDDP - both together (at the same time)


Audioboxer said:


> 4533 booting on DR. Seems its down to Rtts and/or DrvStr?


98% correct
Don't forget procODT. It has to be as low as possible
Too high will refuse to post higher MCLK. And higher MCLK by itself will require 975mV cLDO_VDDP ~ around there, till 2400 MCLK


Audioboxer said:


> But messing with DrvStrs can also bring about tPHYRDL issues again


Correct


Audioboxer said:


> Going to need your help @domdtxdissar and @Veii to figure this out!


Let's skip a bit less steps
What is the RTT combination you have settled on . The RTT_WR plus CKE one
Will you use tCKE at all ?
Have you figured out your peak VDIMM limit without going to maxmem ?

Can we stay on 1-4-4-1-6-6 SD, DD's , to keep R&W PRE even ?
Can we stay on tRDWR & tWRRD on auto ?
And leave tRFC plus SCL on Auto
IOD & CCD + procODT are solid already ?

I suggest to start with CAD_BUS 40-20-30-24 , in order to find RTT_WR
Should be today free to go around this ~ if you have time

WR /3 can work around Park 1-3
WR /2 can work around Park 2-4
for WR /1 i'd move at least above 3 to 5 if not 6
Hi-Z is bugged, but we can try if you can post at all beyond 1800 strap (far later)

If you have the time, might i use you as proof-of-concept testing rabbit ?
PoC for knowing how to handle tPHY now 
Else your first work is to put away most of variables, settle on fixed CAD_BUS, fixed procODT & fixed RTT_WR
Only work with cLDO_VDDP and ClkDrvStr

EDIT:
On Dual Rank, RTT_WR has a different function and NOM/PARK are assigned by Rank, not globally
This is only for many rank setups
Also RTT_WR will enable in-dimm CRC, that it independent of ECC. It's a DDR4 feature. For us irrelevant atm, but just so you keep it in mind

I'd also suggest, to check & take the DR tCKE patterns








* SETUP timings, are not needed and still WIP for DR.
Skip them. Would open too many rabbit holes at once

^ You'd need them (tCKE) when working with RTT_WR.
PDM is not soo important, but keep it on Auto. By default it should disable the normal powerdown, but remain to have an ability, turning on Aggressive PDM ~ if it decides, it needs it


----------



## Audioboxer

Veii said:


> Sorry,
> Soo i've been collecting a long answer for some days , but going on on mobile and checking ~ literally wipes the written, cached post.
> Not good experience, OCN :/
> 
> Sorry , i don't know if i can help you
> While i do understand how to work in patterns, and give logic to code ~ without having to understand the code
> ~ i am no programmer
> Haven't seen the shortcuts you tell me, and can not make out anything out of it.
> 
> Can not understand you 🙇‍♂️
> 
> Correct
> tPHY changes upwards, if dimms are overpowered too
> This is in-line with running stronger PARK ~ but will happen if VDIMM is too high or ClkDrvStr, or cLDO_VDDP is too high
> You can balance this down by wiggling with ClkDrvStr and cLDO_VDDP - both together (at the same time)
> 
> 98% correct
> Don't forget procODT. It has to be as low as possible
> Too high will refuse to post higher MCLK. And higher MCLK by itself will require 975mV cLDO_VDDP ~ around there, till 2400 MCLK
> 
> Correct
> 
> Let's skip a bit less steps
> What is the RTT combination you have settled on . The RTT_WR plus CKE one
> Will you use tCKE at all ?
> Have you figured out your peak VDIMM limit without going to maxmem ?
> 
> Can we stay on 1-4-4-1-6-6 SD, DD's , to keep R&W PRE even ?
> Can we stay on tRDWR & tWRRD on auto ?
> And leave tRFC plus SCL on Auto
> IOD & CCD + procODT are solid already ?
> 
> I suggest to start with CAD_BUS 40-20-30-24 , in order to find RTT_WR
> Should be today free to go around this ~ if you have time
> 
> WR /3 can work around Park 1-3
> WR /2 can work around Park 2-4
> for WR /1 i'd move at least above 3 to 5 if not 6
> Hi-Z is bugged, but we can try if you can post at all beyond 1800 strap (far later)
> 
> If you have the time, might i use you as proof-of-concept testing rabbit ?
> PoC for knowing how to handle tPHY now
> Else your first work is to put away most of variables, settle on fixed CAD_BUS, fixed procODT & fixed RTT_WR
> Only work with cLDO_VDDP and ClkDrvStr
> 
> EDIT:
> On Dual Rank, RTT_WR has a different function and NOM/PARK are assigned by Rank, not globally
> This is only for many rank setups
> Also RTT_WR will enable in-dimm CRC, that it independent of ECC. It's a DDR4 feature. For us irrelevant atm, but just so you keep it in mind
> 
> I'd also suggest, to check & take the DR tCKE patterns
> 
> 
> 
> 
> 
> 
> 
> 
> * SETUP timings, are not needed and still WIP for DR.
> Skip them. Would open too many rabbit holes at once
> 
> ^ You'd need them (tCKE) when working with RTT_WR.
> PDM is not soo important, but keep it on Auto. By default it should disable the normal powerdown, but remain to have an ability, turning on Aggressive PDM ~ if it decides, it needs it


Thanks Veii, I knew you'd be able to bring some advice! Working from home today so I will have time to play around with memory. Not able to run 25 cycles or anything, I need to use the PC and be able to use the internet/apps, but the odd 3 cycle or more importantly, 5 mins here or there to test booting settings will be fine.










I took my previous 4400 profile and slotted in these Rtts, it fixed all tPHYRDL issues I was having before booting like 28/32 or 28/30. Rock solid 28/28, even from cold boots. Switched to 40/20/30/24 and set tWRRD to auto. For whatever reason with these Rtts it likes booting at 1 now.

I can now get 4400~4533 booting every single time, from cold boots too. 4600 has been booted, but I get a lot of the boots on 2nd attempt, or fails to boot twice, memory overclocking error. This could be to do with what you're explaining about ProcODT and more importantly, VDDP at this high a frequency.

Disabled/1/6 seems to be something my memory likes, trying to boot RttPark 7 has resulted in difficulties, I think 6 might be as high as I can safely go. RttWr reduced to 2 started to bring some booting issues above 4400 last night, but I can try it just now at 4400. I was getting 4400 consistently booting at 7/3/3 but with tPHYRDL issues.

Max VDIMM is around 1.65v from prior testing, though I'm not sure if changing Rtts up like this could give any more headroom? Either way, I'd say around 1.65v is as high as it will go without maxmem.

*edit* - RttWr 2 resulted in two F9s, failure to boot. Bringing RttPark down to 3~4 resulted in it booting once, but it wasn't a clean boot. F9'd once, then booted second attempt. This is without any changes to Proc/voltages. It seems Disabled/1/6 so far has just been the way for me to 100% clean boot first time, every time, and get tPHYRDL training equally. At least around 4400.

ProcODT can be dropped from 34.3 above with Disabled/1/6, it boots as low as 28.2 just fine. No idea about stability though, the only 25 cycle I've ever ran at 4400 was with 34.3.

As for tCKE, if it works at 1, should it be left there? Or at 2200 would you be suggesting to run 15? I think AUTO likes to run 0 for whatever reason


----------



## sealxohd

Audioboxer said:


> View attachment 2544771
> 
> 
> Last post for tonight, more of a proof of concept than anything serious, nearly everything on AUTO got 4600 booting.
> 
> Takeaway for this evening seems to be it's ProcODT/Rtts that stop DR going above 4400, or hitting a wall around there. Next step is the bigger challenge, can anything be stable at disabled/1/6? And is it even safe? I don't know enough about Rtts to make a comment.
> 
> Going to need your help @domdtxdissar and @Veii to figure this out!


Wow 4600 is nice! I would say that tWR 1 is safe. I ran 1.65 V daily with 4/1/6 on my old board for a few months without any issues. But I think that the new 2x16 4000 14 kits have a slighty changed PCB compared to my 2x16 4000 16-16-16 kit. Even if it is somewhat newer as well. But since it has a higher XMP voltage I dont think it got worse and your tWR doesnt seem to roll over at high VDIMM too


----------



## Veii

Audioboxer said:


> Rock solid 28/28, even from cold boots. Switched to 40/20/30/24 and set tWRRD to auto. For whatever reason with these Rtts it likes booting at 1 now.


But is that only because you run 15-14
or is that because powering is fine 

I would take your known stable preset and increase primaries +1 every 100MCLK
It's a bit less than 100MCLK (if we check actual transfer time), but less strain has hurt nobody


Audioboxer said:


> Disabled/1/6 seems to be something my memory likes, trying to boot RttPark 7 has resulted in difficulties, I think 6 might be as high as I can safely go. RttWr reduced to 2 started to bring some booting issues above 4400 last night, but I can try it just now at 4400. I was getting 4400 consistently booting at 7/3/3 but with tPHYRDL issues.
> 
> Max VDIMM is around 1.65v from prior testing, though I'm not sure if changing Rtts up like this could give any more headroom? Either way, I'd say around 1.65v is as high as it will go without maxmem.


Yes, let's settle on one, till you can confirm 100% stability with stronger RTT_WR
It completely changes powering and values that are recommended. Pick one , and when you've finished, go stronger. Then check after how much strain the PCB crashes


Audioboxer said:


> *edit* - RttWr 2 resulted in two F9s, failure to boot. Bringing RttPark down to 3~4 resulted in it booting once, but it wasn't a clean boot. F9'd once, then booted second attempt. This is without any changes to Proc/voltages. It seems Disabled/1/6 so far has just been the way for me to 100% clean boot first time, every time, and get tPHYRDL training equally. At least around 4400.


First reboot is by the change of RTT
2nd reboot is by the change of tPHYRDL

MSI boards in specific train beyond tPHYRDL 28 ~ somehow
I would at first still put both tRDWR & tWRRD on auto, soo it can shift these down between dimms:
Example:
My current mess working on random #2's ~ figuring out a pattern somehow (gave up DR again, Dimm-PCB is just a mess)











Audioboxer said:


> ProcODT can be dropped from 34.3 above with Disabled/1/6, it boots as low as 28.2 just fine. No idea about stability though, the only 25 cycle I've ever ran at 4400 was with 34.3.


30 is a good value for this gen - independent of dimm strain
28.8 was hard. At least my sample doesn't like it.
if i go 32 or 28, 4600+ won't post & only work on 30ohm
We might need to figure this out ~ but this will require 2:22min of y-cruncher plus OCCT extreme (together) ~ to verify it being "fine"
As it's independent of MCLK


Audioboxer said:


> As for tCKE, if it works at 1, should it be left there? Or at 2200 would you be suggesting to run 15? I think AUTO likes to run 0 for whatever reason


17min is not that bad, please try to follow tCKE sheet. Signal integrity will thank you
Else when adjusting ClkDrvStr and cLDO_VDDP , both have to be adjusted at the same time ~ later i mean

Also please start with an even set, just to be sure - tPHY is not only "fine" because of tCWL change

EDIT:
Only change RTT_WR, or PARK
if you change VDIMM ~ else just scale up








Independently of tRFC - you can let it on auto sit in the 350ns JEDEC range (up to which point AGESA breaks and "starts to ignore JEDEC")
If everything is fine, it should keep following ~350ns, and get tRFC2/4 correct by itself. If something is wrong, it might be "soo stupid" and don't even post ~ as it has no idea what to use 
* use tRFC mini manual option, if bios is stupid and introduces rounding errors on 2/4 (+/- 1 value) . If it doesn't generate them at all then use own tRFC (failsafe option likely)

As less new rabbit holes, as possible
Using old known preset, and scale up ~ no voltage change, no RTT change
Be sure it's stable ~ then try to check if tPHY is preventing you from posting
And only then when that part is stable and even
Check if procODT or cLDO_VDDP (being too low) prevented you from posting.

Zero VDIMM change. VDIMM change, will completely mess everything up 
But you might need to lower VDIMM slightly, if you increase cLDO_VDDP too much (like beyond 20mV)


----------



## Audioboxer

Veii said:


> But is that only because you run 15-14
> or is that because powering is fine
> 
> I would take your known stable preset and increase primaries +1 every 100MCLK
> It's a bit less than 100MCLK (if we check actual transfer time), but less strain has hurt nobody
> 
> Yes, let's settle on one, till you can confirm 100% stability with stronger RTT_WR
> It completely changes powering and values that are recommended. Pick one , and when you've finished, go stronger. Then check after how much strain the PCB crashes
> 
> First reboot is by the change of RTT
> 2nd reboot is by the change of tPHYRDL
> 
> MSI boards in specific train beyond tPHYRDL 28 ~ somehow
> I would at first still put both tRDWR & tWRRD on auto, soo it can shift these down between dimms:
> Example:
> My current mess working on random #2's ~ figuring out a pattern somehow (gave up DR again, Dimm-PCB is just a mess)
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 30 is a good value for this gen - independent of dimm strain
> 28.8 was hard. At least my sample doesn't like it.
> if i go 32 or 28, 4600+ won't post & only work on 30ohm
> We might need to figure this out ~ but this will require 2:22min of y-cruncher plus OCCT extreme (together) ~ to verify it being "fine"
> As it's independent of MCLK
> 
> 17min is not that bad, please try to follow tCKE sheet. Signal integrity will thank you
> Else when adjusting ClkDrvStr and cLDO_VDDP , both have to be adjusted at the same time ~ later i mean
> 
> Also please start with an even set, just to be sure - tPHY is not only "fine" because of tCWL change


So, continue with Disabled/1/6, try ProcODT at 30, tRDWR and tWRRD on auto and run flat 16 for now instead of 15? Try and see if that can do a 25 cycle at 4400? tCKE 15 boots fine, so try that instead of 1 or AUTO (0)?

Voltages just leave them where they are for now (VSOC, VDDP, VDDG)? Other than possible changes if TM5 errors say so?


----------



## Veii

Audioboxer said:


> So, continue with Disabled/1/6, try ProcODT at 30, tRDWR and tWRRD on auto and run flat 16 for now instead of 15? Try and see if that can do a 25 cycle at 4400? tCKE 15 boots fine, so try that instead of 1 or AUTO (0)?
> 
> Voltages just leave them where they are for now (VSOC, VDDP, VDDG)? Other than possible changes if TM5 errors say so?


Rather tCKE 14 for DR @ 2200 MCLK ~ left column is for SR

I think i would let procODT down to what it was for you ~ because changes on VDDP and procODT will mess up CO's & destabilize the CPU
(takes too long to verify procODT 30 is fine for you)
Changes on VDD18 will mess with VDDG, VDIMM and mess up both CO and DRAM-OC (also cause issues with VDIMM)
RTT_WR change, will increase strain, even with lowered RTT_PARK ~ it will snowball and mess up VDIMM range (need to use less VDIMM on stronger _WR)

As least steps as possible, issues stack quite fast
Scale up your main preset with the primaries
And keep delivering TM5 stable results please.
I would run over 6 cycles, but this might take ages. (i mean i would run 25, but you know ~ time and stuff xD)

Else yes
Verify your preset and old powering was "fine" with using tCKE
It very well can show issues with tRRD_, tWTR_, and R&W-PRE value (soo tRDWR, tWRRD,SD & DD's)
In general all of them can mess with tPHY values
Too many rabbit holes ~ soo better start simple.

No change in VDIMM
no change in powering
no change in CPU related values and impedance's
Just scale up timings till you find your wall & can verify tCKE works out for you (is timed correctly)
* higher tRFC (coming from fixed preset) ~ should not cause any issue at all. Might just be postponed but that's irrelevant for now 

EDIT:








^ what the board has to predict ~ if it's not buggy

Also @PJVol roundup method failed ~ appeared good, but at the end failed
Unless DR is slightly delivering different results ~ mainboards show/seem to follow my initial resolve.








Bottom was "round up"
Unsure if IMC-FW by itself is wrong or my math was flawed, but when it get's it right & doesn't bug out (self predict) it seems to follow initial values, not round-up ones

Would be good to get more data from different vendors and AGESA's @ and sub 3600MT/s
But i think i have to roll-back , the "round-up" change for now. To prevent confusion


----------



## Audioboxer

Veii said:


> Rather tCKE 14 for DR @ 2200 MCLK ~ left column is for SR
> 
> I think i would let procODT down to what it was for you ~ because changes on VDDP and procODT will mess up CO's & destabilize the CPU
> (takes too long to verify procODT 30 is fine for you)
> Changes on VDD18 will mess with VDDG, VDIMM and mess up both CO and DRAM-OC (also cause issues with VDIMM)
> RTT_WR change, will increase strain, even with lowered RTT_PARK ~ it will snowball and mess up VDIMM range (need to use less VDIMM on stronger _WR)
> 
> As least steps as possible, issues stack quite fast
> Scale up your main preset with the primaries
> And keep delivering TM5 stable results please.
> I would run over 6 cycles, but this might take ages. (i mean i would run 25, but you know ~ time and stuff xD)
> 
> Else yes
> Verify your preset and old powering was "fine" with using tCKE
> It very well can show issues with tRRD_, tWTR_, and R&W-PRE value (soo tRDWR, tWRRD,SD & DD's)
> In general all of them can mess with tPHY values
> Too many rabbit holes ~ soo better start simple.
> 
> No change in VDIMM
> no change in powering
> no change in CPU related values and impedance's
> Just scale up timings till you find your wall & can verify tCKE works out for you (is timed correctly)
> * higher tRFC (coming from fixed preset) ~ should not cause any issue at all. Might just be postponed but that's irrelevant for now












lol, just went and ran this. As I said I don't have time for 25 cycles for now, but I'll tweak the above to what you suggest. I changed most of the right side to AUTO, but I forgot that means SDs go to 5/7. Should I manually change them back to 4/6?

Interesting to see tWRRD auto to 2 at tCL16. Not sure why 15 pushed it down to 1.

tRDWR autos to 9, up from being manually set at 8.

VDIMM I dropped to 1.6v, just because of changing from tCL15 to 16. In theory, it shouldn't need as high as 1.62v for tCL16. In theory.

And verdict on ProcODT for later, try and carry on with 30, or go back to 34.3 for now?


----------



## Veii

Audioboxer said:


> Interesting to see tWRRD auto to 2 at tCL16. Not sure why 15 pushed it down to 1.
> 
> VDIMM I dropped to 1.6v, just because of changing from tCL15 to 16. In theory, it shouldn't need as high as 1.62v for tCL16. In theory.


tWRRD & tRDWR is because of SD, DD change
My bad. Keep them at 1-4-4-1-6-6
tRDWR prediction seems to work out. We just want them open , to catch such changes









I wouldn't touch VDIMM, because this will mess with the balance of (ClkDrvSt + RTT + cLDO_VDDP + procODT)
All of them affect VDIMM
No touch to your confirmed preset, just scale up in frequency, primaries and tCKE range
No touch on tRRD_ and tWTR_ either


Audioboxer said:


> And verdict on ProcODT for late, try and carry on with 30, or go back to 34.3 for now?


Go back to 34, because you have no idea if your CO's didn't break and VDDG voltages broke on lower procODT
Verification of such takes 2:22h
procODT messes with RTTs too, and messes with cLDO_VDDP.
Don't cause imbalance of known to be stable values. Unless you want to spend 25cycles to verify "new alternative" stable values
I do, but unless you really want to spend 4h for each attempt  no touch, till you can confirm, that is what prevented you reaching higher MCLK !
And only when you confirm that - you have to confirm that y-cruncher and OCCT is still stable  soo no touch, for now


Veii said:


> I wouldn't touch VDIMM, because this will mess with the balance of (ClkDrvSt + RTT + cLDO_VDDP + procODT)
> All of them affect VDIMM


Only have to touch VDIMM, when you change RTT_WR or you change one of the above written. But then also only a 10-20mV change, not more


----------



## Audioboxer

Veii said:


> tWRRD & tRDWR is because of SD, DD change
> My bad. Keep them at 1-4-4-1-6-6
> tRDWR prediction seems to work out. We just want them open , to catch such changes
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I wouldn't touch VDIMM, because this will mess with the balance of (ClkDrvSt + RTT + cLDO_VDDP + procODT)
> All of them affect VDIMM
> No touch to your confirmed preset, just scale up in frequency, primaries and tCKE range


Gotcha, will do some testing just now with frequency/primaries and tCKE and leave a full stability run at 4400 till later.


----------



## Veii

Audioboxer said:


> Gotcha, will do some testing just now with frequency/primaries and tCKE and leave a full stability run at 4400 till later.
> 
> 
> Audioboxer said:
Click to expand...

Still believe, tCKE 14 is the one you where looking for
Check again with








Oh you don't need memory clear option in the bios
Can put it back to auto, if you've changed it
tPHY changes should then show immediately
But check both columns








tRDWR/tWRRD "imbalance" is normal for now ~ tPHY values or tMOD ones are not really changeable


----------



## Audioboxer

Veii said:


> Still believe, tCKE 14 is the one you where looking for
> Check again with
> View attachment 2544839
> 
> Oh you don't need memory clear option in the bios
> Can put it back to auto, if you've changed it
> tPHY changes should then show immediately
> But check both columns
> View attachment 2544840
> 
> tRDWR/tWRRD "imbalance" is normal for now ~ tPHY values or tMOD ones are not really changeable





















4467 ~ 4533 boot clean and train fine for tPHYRDL.

But I hit a wall at 4600, double F9s, OCing failure. This is even with trying 18-18-18-18, so I don't think it's primaries causing a failed boot.










If I Iook at what I got to boot last night, this firstly wasn't a clean boot, one F9 and went on second, and most of timings are on AUTO. Only manual entry was 18-18-18-18 and 36/52.

1.64v instead of 1.62v and VSOC is a bit higher here. But it's super unstable and as I said, I wasn't able to clean boot it. Happy to try again though if you can think of any pointers for what to change on the 4533 profile to get it possibly working at 4600.


----------



## Veii

Audioboxer said:


> 4467 ~ 4533 boot clean and train fine for tPHYRDL.
> 
> But I hit a wall at 4600, double F9s, OCing failure.


You did adapt tCKE ?
But there are too many options
Proof stability on what you can boot
Then increase cLDO_VDDP and proof again stability (well , to what you can deliver by TM5)

Then change cLDO_VDDP to 1v or identical to VDDG CCD, and check if it was that
Doing so will need a change on ClkDrvStr ~ soo you likely have to jump down, check tPHY and balance them , by lowering ClkDrvStr
Too high VDDP won't post, too high ClkDrvStr won't post
Too high procODT won't post ^^'

But i think you can figure it out
Just don't skip steps here


Audioboxer said:


> 4467 ~ 4533 boot clean and train fine for tPHYRDL.


Soo increase cLDO_VDDP to 1v and confirm no #6 on 4533
Then we have to check
MSI boards behave different ~ but for me, if it ever hit tPHYRDL 30, it refused to post at all.
It just didn't know what to do with it ~ soo you might need to keep that in mind
===================








Not buggy system, nono 








Funnily, it holds to allowed vcore (fit-pre-v)
but it doesn't hold to allowed SOC and defaults to 1.25v for 2100 FCLK
(i mean technically it tries it's best to restore and remember things, but somewhy it's attempt is not good enough)
Either it always defaults to 1.25v, or it still defaults to 1.25v because of old 2100FCLK base (failed boot, 60ohm procODT default under 900-900-900mV)


----------



## Audioboxer

Veii said:


> You did adapt tCKE ?
> But there are too many options
> Proof stability on what you can boot
> Then increase cLDO_VDDP and proof again stability (well , to what you can deliver by TM5)
> 
> Then change cLDO_VDDP to 1v or identical to VDDG CCD, and check if it was that
> Doing so will need a change on ClkDrvStr ~ soo you likely have to jump down, check tPHY and balance them , by lowering ClkDrvStr
> Too high VDDP won't post, too high ClkDrvStr won't post
> Too high procODT won't post ^^'
> 
> But i think you can figure it out
> Just don't skip steps here
> 
> Soo increase cLDO_VDDP to 1v and confirm no #6 on 4533
> Then we have to check
> MSI boards behave different ~ but for me, if it ever hit tPHYRDL 30, it refused to post at all.
> It just didn't know what to do with it ~ soo you might need to keep that in mind


Yes I increased tCKE to 16 per the table for 2300. I tried dropping ProcODT down to 30 but it still didn't boot. I didn't want to mess with anything else until asking for your advice.

I'm running a 3 cycle on 4533 just now, just to see if it can pass that at 1.62v.


----------



## Veii

Audioboxer said:


> Yes I increased tCKE to 16 per the table for 2300. I tried dropping ProcODT down to 30 but it still didn't boot. I didn't want to mess with anything else until asking for your advice.
> 
> I'm running a 3 cycle on 4533 just now, just to see if it can pass that at 1.62v.


High VDIMM shouldn't cause a crash
it's balanced down already by RTT
You will only notice it on longer runs, but not instantly
Instantly are only boot issues.

If you ever get it to loop-reboot
Try couple of times. Before everything was "balanced" , i needed 6 reboots to hit 1900 FCLK - and only 1/6 actually posted.
Today experience is better ~ but i think you just need more cLDO_VDDP on it


Audioboxer said:


> Yes I increased tCKE to 16 per the table for 2300. I tried dropping ProcODT down to 30 but it still didn't boot. I didn't want to mess with anything else until asking for your advice.
> 
> 
> Veii said:
Click to expand...

I know i used too much, but didn't know it better
975mV should be enough for 2300 MCLK
Mirroring to CCD voltage is fine. Somewhy it always was fine on Vermeer. But IOD needs some distance

I wonder if you have tPHY issues, instead of normal IMC underpowering issue
But yes, you i think showed well ~ that cLDO_VDDP needs no change even till 4533.
People should leave it at 900mV ~ it causes the least issues and we can use voltage presets from everyone else
Drop to 880mV already changes how CAD_BUS functions (stability) and 920 caused missmatch issues for me
(although DR is already a missmatch issue on it's own ~ FW-Design issue, else 1T would work)


----------



## Audioboxer

Ooft, 4533 was like opening pandora's box @Veii

So with timings a couple of posts above I got an error on 7/9 within 3 cycles. Looked to simply be not enough VDIMM for 4533, okay, seems reasonable. 1.63/1.64v started introducing errors on 2, PCB crashes but possibly also related to Proc/Clk/Cke. Spent a fair bit of time there trying what felt like everything.

ProcODT at 30/32 introduced tPHYRDL training at 28/30. 34.3 trains at 28/28 every time.

I tried lowering VDDP closer to 0.9v, but this introduced my first unclean boot at 4533, F9 and then boot on second time.

Tearing my hair out at this point I reset everything back to what it was a few posts ago but decided if it is voltage issues, what else could it be other than VDIMM? VSOC. You'd think maybe increase it, but no, the first 3 cycle has passed with it *decreased *to 1.15v. This is what I run at 3800.

Data a bit inconclusive just now, but _maybe _my VSOC was too high???

This definitely needs a 6 cycle minimum, more like a 25. Just to see if I've been a bit lucky with 1.62v passing this time, irrespective of VSOC being lowered.

Not had a chance to look at 4600 again, all this time was spent working and trying to figure out 4533


----------



## Veii

Audioboxer said:


> ProcODT at 30/32 introduced tPHYRDL training at 28/30. 34.3 trains at 28/28 every time.
> 
> I tried lowering VDDP closer to 0.9v, but this introduced my first unclean boot at 4533, F9 and then boot on second time.
> 
> Tearing my hair out at this point I reset everything back to what it was a few posts ago but decided if it is voltage issues, what else could it be other than VDIMM? VSOC. You'd think maybe increase it, but no, the first 3 cycle has passed with it *decreased *to 1.15v. This is what I run at 3800.


Painful haha
I thought , something was going on
Usually you do not post bad results 

But we could've worked on tPHYRDL missmatch
Eh, it was expected ~ hence you shouldn't change something that is known to be stable.
Far to many rabbit holes exist & they get even more, the higher you go without being half-confident on the balance part

Also yes, procODT and SOC go hand in hand 😋
Good job !

EDIT:
Soo it seems like #2 leans more towards overcurrent or bad data-eye 
Still trying to figure out what it means. It mostly comes in pairs and has no meaning alone.
Need more data about #2


----------



## Audioboxer

Veii said:


> Painful haha
> I thought , something was going on
> Usually you do not post bad results
> 
> But we could've worked on tPHYRDL missmatch
> Eh, it was expected ~ hence you shouldn't change something that is known to be stable.
> Far to many rabbit holes exist & they get even more, the higher you go without being half-confident on the balance part
> 
> Also yes, procODT and SOC go hand in hand 😋
> Good job !
> 
> EDIT:
> Soo it seems like #2 leans more towards overcurrent or bad data-eye
> Still trying to figure out what it means. It mostly comes in pairs and has no meaning alone.
> Need more data about #2


I was getting it alone and also once it came with an error 0.

By alone though I mean within 3 cycles which is simply not long enough for conclusive data. Very likely if I let it run longer I would get more data. I will try letting this 4533 profile run for at least 6 cycles later. Failing that a 25 cycle overnight.

Will try and do a bit of work on 4600 again now when I can fit it in.


----------



## Veii

Audioboxer said:


> Will try and do a bit of work on 4600 again now when I can fit it in.


I think ,you can abuse the tPHYRDL missmatch on lower procODT and start to decrease slightly ClkDrvStr, or ignore and touch cLDO_VDDP
On both 32 and 30 ohm, you should not get a missmatch ~ unless memory depends on procODT for powering

I have fun too atm
















1.42v ~ voltage/powering issue, not discharge/heat related
There is zero way to get _WR /1 to work 
I just can't drop RTT_PARK further. It refuses to post on overcurrent
~ and absolutely zero way to run Hi-Z on A0 dimms (for now)


----------



## Audioboxer

Veii said:


> I think ,you can abuse the tPHYRDL missmatch on lower procODT and start to decrease slightly ClkDrvStr, or ignore and touch cLDO_VDDP
> On both 32 and 30 ohm, you should not get a missmatch ~ unless memory depends on procODT for powering
> 
> I have fun too atm
> View attachment 2544859
> 
> View attachment 2544860
> 
> 1.42v ~ voltage/powering issue, not discharge/heat related
> There is zero way to get _WR /1 to work
> I just can't drop RTT_PARK further. It refuses to post on overcurrent
> ~ and absolutely zero way to run Hi-Z on A0 dimms (for now)


I'll try! Need to try and narrow down what is causing failure to post. Wondering if some secondary timings are upset at 4600 or if it's down to resistances, voltage and Proc.


----------



## Veii

Audioboxer said:


> I'll try! Need to try and narrow down what is causing failure to post. Wondering if some secondary timings are upset at 4600 or if it's down to resistances, voltage and Proc.


A refuse to post, mostly is timing independent ~ at least if you follow the advice to scale up from something you know that's been stable on lower clock
It very likely is either

Overcurrent [RAM] and refuse to post
Underpowered [CPU/IMC] and refuse to post
Non MSI boards (to what i've seen so far) have option 3.

tPHY reaches value 30 and AGESA is braindead incapable to handle it (refuses to post) Same to tCL 12 on higher Freq, tCWL 10, or tRDWR 21+. Well or odd tCWL at all 🤭









Progress, soo overcurrent #11= drop on ClkDrvStr and we are back being fine again 😇
Seems like _WR /2 is much stronger to /3 ~ than expected
I think it should run 12-12 at least , but i drop to 1600 MCLK just to test if DIMM-PCB is the issue, or bios is derping with tPHY predictions/missmatches

Also seems like A0 can not run anything above _WR 120ohm. Can't go less with PARK than "nothing" ~ oor it requires high VDIMM, i have to check
Well ultimately, it "creates" it by itself thanks to Dynamic-ODT ~ but it didn't seem to be able with RTT_NOM. It needed "something" there.

In general, tCKE range is flawless~ i'm happy
But i need to see how 4 dimms (many dimm-setup) behave & find the alternative values that work
Then check if 32gb Dimms, just are -2 or it actually was rank dependent, than it was capacity dependent
SETUP timings also need much more work and are slightly depressing ~ especially when DR 1T is such an issue that shouldn't be one (issue with ODMs ~ well AMD actually, but still)

Also issue is the lack of tPHY & tXP control for the user. This shouldn't be that way.
At least allow us to work with it, not hold us for dumb. 
JEDEC requesting 350ns on 8x1024 SR is also a slight overestimate  but it's finee ~ Just "the AMD experience". Adventurous bug-hunt platform. Never get's boring


----------



## Audioboxer

This booted in on a second attempt after one F9, then I noticed I had forgot to reset tRFC. Trained at 28/28 at least.










After trying 288 and failing over and over and over, went up to 296 and increased VDIMM 0.01 and VDDP slightly. Still failed a few times, then this boot sneaked in. Still 28/28.

@Veii So the problem I have at 4600 is boot failures, but occasionally it makes it in.

But, some progress, this is the first boot at 4600 I've had with decent timings.... And speaking of that, I forgot to set tCKE to 16 lmao.


----------



## Audioboxer

@Veii this booted first time, that's never happened at 4600 for me before, all the above is lucky 2nd strikes. But I got a reboot on desktop.










Increased VDIMM, but this booted on 2nd attempt. Sitting on desktop for now. Might not just be VDIMM that caused the reboot, 4600 is likely starting to get tough for flat 16.

Preliminary results seem to suggest reliance on VDDP exponentially increased when hitting 4600. Still training at 28/28 with 0.98v on VDDP.


----------



## Veii

Audioboxer said:


> After trying 288 and failing over and over and over, went up to 296 and increased VDIMM 0.01 and VDDP slightly. Still failed a few times, then this boot sneaked in. Still 28/28.


Oh , well
I mean tRFC "range" changes by Freq
Soo me using fixed multiplier, result always was dynamic up to MCLK
But hence nobody seems to understand it - just let it do it's thing. JEDEC ~350ns.
A good firmware design, will get it near 350ns without you having to interact with it.
Unless it completely misses logic and refuses that way to post. But normaly, let it be 
Or make up your own 350ns value and use that. Although i saw on some MCLK, tRFC1 becomes a decimal ~ soo just leave it be 
I am less confident on tRFC2/4 being the same value as 1. But for accuracy sake, get it correct. And when you can't, just ignore it fully ~ no manual tRFC.

Potentially tWR 12 will get tight on such high clock, but i mean you demonstrate by yourself "it's fine"
Soo , "it's fine" 

Later i would start to check if RTT_NOM "really" is fine, with such high VDIMM - buut all good as it seems
Surprising that you can boot it at 930mV VDDP
You generally have a good IMC, good memory and good skillset 
================
We also have good news here
Just 6:30min per cycle is painful. 1600 MCLK is so slow. Else it takes 3:36min a cycle


----------



## Audioboxer

Veii said:


> Oh , well
> I mean tRFC "range" changes by Freq
> Soo me using fixed multiplier, result always was dynamic up to MCLK
> But hence nobody seems to understand it - just let it do it's thing. JEDEC ~350ns.
> A good firmware design, will get it near 350ns without you having to interact with it.
> Unless it completely misses logic and refuses that way to post. But normaly, let it be
> Or make up your own 350ns value and use that. Although i saw on some MCLK, tRFC1 becomes a decimal ~ soo just leave it be
> I am less confident on tRFC2/4 being the same value as 1. But for accuracy sake, get it correct. And when you can't, just ignore it fully ~ no manual tRFC.
> 
> Potentially tWR 12 will get tight on such high clock, but i mean you demonstrate by yourself "it's fine"
> Soo , "it's fine"
> 
> Later i would start to check if RTT_NOM "really" is fine, with such high VDIMM - buut all good as it seems
> Surprising that you can boot it at 930mV VDDP
> You generally have a good IMC, good memory and good skillset
> ================
> We also have good news here
> Just 6:30min per cycle is painful. 1600 MCLK is so slow. Else it takes 3:36min a cycle


It's not really good though as I can't seem to reproduce clean boots at 4600. Just when I think I've got it back to F9s. Very random and I can't seem to nail it. Higher VDDP seems to be helping but it's not consistently allowing a clean boot.


----------



## Veii

Audioboxer said:


> 4600 is likely starting to get tough for flat 16.


Oh it absolutely is 
That's running 3800 12-12 , well 3733.333~ bit higher than that. naer 3766ish
4200 C15-15 is hard
4200C14-14 is quite insane ^^'
Mine only run 4027C14-14. 4133 haven't been able to do yet, and yours is DR ontop


----------



## Veii

Audioboxer said:


> It's not really good though as I can't seem to reproduce clean boots at 4600. Just when I think I've got it back to F9s. Very random and I can't seem to nail it. Higher VDDP seems to be helping but it's not consistently allowing a clean boot.


Likely CsOdtDrvStr and VDD18 issue
try to run CsOdt to 40 and CkeDrvStr to 20, and VDD18 as -10mV

else reserve
CsOdt 30, CkeDrv 24 and VDD18 slightly up


----------



## Audioboxer

Veii said:


> Likely CsOdtDrvStr and VDD18 issue
> try to run CsOdt to 40 and CkeDrvStr to 20, and VDD18 as -10mV
> 
> else reserve
> CsOdt 30, CkeDrv 24 and VDD18 slightly up


Yeah, I'm struggling, can't make sense of 4600 and the failed boots. One minute it works, next it can fail 10+ times with the same settings. Tried quite a lot now and failing to draw any consistent pattern. Have to make sure when it does boot I don't just think "Oh that means the last thing I did has fixed it!". I thought a high VDDP was directly helping, I'm not even sure now...










I'm going to work with this. Another quick 3 cycle done at 4533 just to make sure the one earlier wasn't total luck. I'll now see if I can test this profile properly and see what potential it has for being a "daily". tCL15 might be too much at 4533, it's marginally faster than 3800 tCL13. 16 however is marginally slower. Still, let's see if flat 16 is even fine first, then go from there.


----------



## Spooky Asparagus

Hi everyone ! I'm new to this forum and i'm trying to tweak my RAM on my new setup. For context : I'm a long term Mac user (yes, I know... I needed it for work...). My last desktop setup and overclock experience was with a Phenom II X4 and DDR3 so quite old but I'm not new to OC and the associated risks.
I recently bought my new PC and I want to tweak it a bit for several reasons : I like fiddling and understand things and use my equipment to 110% of its capabilities.

So, enough stories, let's get to the technical stuff ! What I have :

CPU : Ryzen 7 5800X (B0 stepping)
MB : Asus X570-CREATOR WIFI (BIOS v0504, AGESA V2 1.2.0.5)
RAM : Corsair Vengeance LPX 32Go 4000Mhz C19 (SKU CMK32GX4M2G4000C19)
ICs seems to be Micron 8Gb Rev E




















What I read/watched :

www.reddit.com/r/overclocking/comments/ahs5a2/demystifying_memory_overclocking_on_ryzen_oc/
MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper
www.reddit.com/r/overclocking/comments/poenn1/tuning_trdwr_and_twrrd_at_very_tight_timings/
Some others posts that I don't remember
What I used for stability testing :

TestMem5 with Extreme profile from anta777
Memtest86
OCCT Linpack
Where I am now :

















Not showing in the screenshots, the DRAM voltage is 1,425V. I'm not sure if it's a good idea to increase it more.
I'm sure that I have some timings wrongly configured or probably not tight enough. Do you see any possible improvements ?


----------



## Veii

Veii said:


> Oh it absolutely is
> That's running 3800 12-12 , well 3733.333~ bit higher than that. naer 3766ish
> 4200 C15-15 is hard
> 4200C14-14 is quite insane ^^'
> (equivalent to 4600 16-16)
> Mine only run 4027C14-14. 4133 haven't been able to do yet, and yours is DR ontop
> 
> 
> Audioboxer said:
> 
> 
> 
> tCL15 might be too much at 4533, it's marginally faster than 3800 tCL13. 16 however is marginally slower. Still, let's see if flat 16 is even fine first, then go from there.
Click to expand...

If you compare that it's faster than 1:1 , then not bad ~ it has to be quite a bit faster on MCLK
But MCLK to MCLK related ~ independent of 1:1 acceleration (Gear 1) , we compare rather 3800 C12-12 (slightly lower), but higher than 3733C12-12 ~ to your current 16-16 set


Audioboxer said:


> Yeah, I'm struggling, can't make sense of 4600 and the failed boots. One minute it works, next it can fail 10+ times with the same settings. Tried quite a lot now and failing to draw any consistent pattern. Have to make sure when it does boot I don't just think "Oh that means the last thing I did has fixed it!". I thought a high VDDP was directly helping, I'm not even sure now...
> 
> View attachment 2544887
> 
> 
> I'm going to work with this. Another quick 3 cycle done at 4533 just to make sure the one earlier wasn't total luck. I'll now see if I can test this profile properly and see what potential it has for being a "daily". tCL15 might be too much at 4533, it's marginally faster than 3800 tCL13. 16 however is marginally slower. Still, let's see if flat 16 is even fine first, then go from there.


I think you just want a bit too much from it  ~ because 4600 16-16 is quite fantastic binning
920mV cLDO_VDDP is usually "not enough"
Up to 1v then we'll see
But before that, you might want to invest time to balance tPHY missmatch on lower procODT , then come back to 34.3
It's just ~ because you seem to still be too dependent on it (powering) for your dimms. tPHY should not wiggle if you change procODT ~ only if it was "too much", but not if it was "not enough"
Maybe abuse while you can run this MCLK, settle down for it as a daily (confirm with Geekbench too)

Also VTT_MEM or Vref should be equal or higher than VDIMM , on DDR4
It was equal or lower on DDR3 , not DDR4.
I feel there is a miscommunication spread there too


Spoiler: Aand [A0] RTT_WR /2 is stable



It's just 4600 20-20-20 equivalent, but PCB is stable. Now to checking how it likes voltage and if it can run 3800 14-14, then 13-13 then 4200 15-15
And bed time too 🥱


----------



## Audioboxer

Veii said:


> If you compare that it's faster than 1:1 , then not bad ~ it has to be quite a bit faster on MCLK
> But MCLK to MCLK related ~ independent of 1:1 acceleration (Gear 1) , we compare rather 3800 C12-12 (slightly lower), but higher than 3733C12-12 ~ to your current 16-16 set
> 
> I think you just want a bit too much from it  ~ because 4600 16-16 is quite fantastic binning
> 920mV cLDO_VDDP is usually "not enough"
> Up to 1v then we'll see
> But before that, you might want to invest time to balance tPHY missmatch on lower procODT , then come back to 34.3
> It's just ~ because you seem to still be too dependent on it (powering) for your dimms. tPHY should not wiggle if you change procODT ~ only if it was "too much", but not if it was "not enough"
> Maybe abuse while you can run this MCLK, settle down for it as a daily (confirm with Geekbench too)
> 
> Also VTT_MEM or Vref should be equal or higher than VDIMM , on DDR4
> It was equal or lower on DDR3 , not DDR4.
> I feel there is a miscommunication spread there too
> 
> 
> Spoiler: Aand [A0] RTT_WR /2 is stable
> 
> 
> 
> It's just 4600 20-20-20 equivalent, but PCB is stable. Now to checking how it likes voltage and if it can run 3800 14-14, then 13-13 then 4200 15-15


MEM VTT? It always displays as half on MSI boards via Zentimings unless you take it off AUTO and set it manually.

I gave 18-18-18-18 a go at 4600 as well, still couldn't get consistent boots.

And yeah, I'll see if I can find out why tPHYRDL mismatches happen under 34.3 even at 4533. First I just want to see what comes back from a 25 cycle


----------



## Audioboxer

@Veii speaking about expecting too much



















34.3 trains at 30/28
32 trains at 30/30

Rare to see the powering issue on A1 instead of B1 lol (at 34.3).

Soooo, think I'll stick to tCL16!


----------



## Veii

Audioboxer said:


> @Veii speaking about expecting too much
> 
> View attachment 2544899
> 
> 
> View attachment 2544900
> 
> 
> 34.3 trains at 30/28
> 32 trains at 30/30
> 
> Rare to see the powering issue on A1 instead of B1 lol (at 34.3).
> 
> Soooo, think I'll stick to tCL16!


Ah , fix them first - 32 then showed underpowering
34 shows just a balance issue
fix it, then you can up it if you want

on 30/28 , check if anything else missmatches - like tWRRD
then try to decrease ClkDrvStr and increase cLDO_VDDP
Or simply increase cLDO_VDDP and see what happens

It can't be more obvious at this point, that you have to touch cLDO_VDDP to something. Up or down. Same for ClkDrvStr


----------



## Audioboxer

Veii said:


> Ah , fix them first - 32 then showed underpowering
> 34 shows just a balance issue
> fix it, then you can up it if you want
> 
> on 30/28 , check if anything else missmatches - like tWRRD
> then try to decrease ClkDrvStr and increase cLDO_VDDP
> Or simply increase cLDO_VDDP and see what happens
> 
> It can't be more obvious at this point, that you have to touch cLDO_VDDP to something. Up or down. Same for ClkDrvStr












Will focus on this first, looking promising. At tCL16 VDIMM seems like it can come down a bit.


----------



## hazium233

Audioboxer said:


> View attachment 2544830





Veii said:


> But is that only because you run 15-14
> or is that because powering is fine


Or it is the proportion tPHYRDL to tPHYWRL is essentially adding the extra command spacing.



Audioboxer said:


> View attachment 2544837
> 
> 
> 
> Interesting to see tWRRD auto to 2 at tCL16. Not sure why 15 pushed it down to 1.
> 
> tRDWR autos to 9, up from being manually set at 8.


Yeah that is what it seems to do to me when the tPHYRDL / tPHYWRL goes to 28 v 11. It is an extra clock of read to write spacing, which adds on to tRDWR but subtracts from tWRRD.


----------



## Veii

hazium233 said:


> Or it is the proportion tPHYRDL to tPHYWRL is essentially adding the extra command spacing.
> 
> 
> Yeah that is what it seems to do to me when the tPHYRDL / tPHYWRL goes to 28 v 11. It is an extra clock of read to write spacing, which adds on to tRDWR but subtracts from tWRRD.


Does this add up ?
~ 1.5v








tCWL and tCL are combined.
tRDWR & tWRRD rather would "cause issues" on tWPRE, tRPRE missmatch
Although they should have something to do with SD, DD's ~ they do not show such behavior.
Nevertheless if 1-4-4-1-6-6, 1-5-4-1-7-6, or the current 1-5-5-1-7-7
They do not change the outcome, of one dimm being a lower auto predicted value.

Most is on Auto to catch per channel differences
Except for tCKE, SD,DD's, tWTR_ & tRRD_, tWR & tRTP
Well and powering logically ~ as that's the goal of this scaling work 


Audioboxer said:


> View attachment 2544904
> 
> 
> Will focus on this first, looking promising. At tCL16 VDIMM seems like it can come down a bit.


Looks good 
Well, "we'll see" ~ i mean
We both seem to make progress, i hope








That's been yesterdays fun ~ bit creepy face, for a creepy experience till the late night
Many 1's (200), couple zero's, couple 14's, couple 5's
Lower ClkDrvStr by one, higher VDIMM from 1.44 to 1.5, stronger RTT_NOM as exchange
Error free.
Scaling continues on RTT_WR/2

Hope to see same good progress on your side too~
Good morning


----------



## Veii

Spooky Asparagus said:


> I'm a long term Mac user (yes, I know... I needed it for work...)


Hackintosh your Ryzen 😋


Spooky Asparagus said:


> I like fiddling and understand things and use my equipment to 110% of its capabilities.


Understanding things with memory will be annoying for you ~ but i hope you can find what you're looking for


Spooky Asparagus said:


> Where I am now :
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Spooky Asparagus said:
> 
> 
> 
> the DRAM voltage is 1,425V. I'm not sure if it's a good idea to increase it more.
> I'm sure that I have some timings wrongly configured or probably not tight enough. Do you see any possible improvements ?
Click to expand...

Rev.E scales up to 1.72v , but it depends on the PCB
Soo likely 1.68v peak
That is tho under different RTT circumstances, because voltage by itself means nothing. Ohm's law 

It would be easy for you, to press on








The options field, and sort the posts by users
Hazium233 (i think)
Blameless (more confident here)
and one more person , had worked with Rev.e (am bad with names) *EDIT*: Nighthog was it
Soo you can surely find some "done" results from us, else Zen DDR4 OC Leaderboards will have some

[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread You can find here couple Rev.E presets ~ just scale down primaries
(-1 tCL , -1 tRCD, every 100MCLK)
Easiest for Rev.E where
tRCDmax (_RD*2) + tCCD_L (6-7)
~ for tRAS, always worked.
Micron Rev.B tRCDRD is slightly better, but they are pretty equal (2020+ Rev.B as 2048MB chips. 2019 or earlier 1024MB chips where worse than HynixMFR)
Usually you find Rev.B inside 16gb micron dimms ~ but you are on dual rank 16x1024M


----------



## PJVol

Veii said:


> 1375 is a good range for a 5600X
> But COs need to drop (to -40) and fMAX needs to increase to 300+
> Else scaling is up to 1413 (substrate, well FIT rather)
> Needs further undervolt range and stronger overclock range.


Actually, 1375 is not even close to enough for my chip. We're talking here of different 5600X though. CO stability and behavior is not changed (it'd be strange if it does), so any deviation from the 1.2.0.3C stable curve leads to core crash. I rolled back to 1.2.0.3c bios and here are two runs of CBR23 made with ~ same settings and temps.


----------



## Veii

PJVol said:


> I rolled back to 1.2.0.3c bios and here are two runs of CBR23 made with ~ same settings and temps.


You see no permanent changes, or sideeffects after the rollback ?


----------



## rossi594

Veii said:


> Does this add up ?
> ~ 1.5v
> View attachment 2544975
> 
> tCWL and tCL are combined.
> tRDWR & tWRRD rather would "cause issues" on tWPRE, tRPRE missmatch
> Although they should have something to do with SD, DD's ~ they do not show such behavior.
> Nevertheless if 1-4-4-1-6-6, 1-5-4-1-7-6, or the current 1-5-5-1-7-7
> They do not change the outcome, of one dimm being a lower auto predicted value.
> 
> Most is on Auto to catch per channel differences
> Except for tCKE, SD,DD's, tWTR_ & tRRD_, tWR & tRTP
> Well and powering logically ~ as that's the goal of this scaling work
> 
> Looks good
> Well, "we'll see" ~ i mean
> We both seem to make progress, i hope
> View attachment 2544976
> 
> That's been yesterdays fun ~ bit creepy face, for a creepy experience till the late night
> Many 1's (200), couple zero's, couple 14's, couple 5's
> Lower ClkDrvStr by one, higher VDIMM from 1.44 to 1.5, stronger RTT_NOM as exchange
> Error free.
> Scaling continues on RTT_WR/2
> 
> Hope to see same good progress on your side too~
> Good morning


Did you run >1.2v vsoc because your soc die is bad? Or does it help stabilize the overclock? Or just because it's easier to just punch it in and lower it later? It seems excessive in the context of my soc xD


----------



## PJVol

No, or should i?


----------



## Veii

PJVol said:


> No, or should i?


I've read reports of more things changing, hence PSP-FW update was done "apparantly"
Soo also patches from microcode where removed and filled by placeholders ~ after 1204C onwards

This should've included a boosting table change after 1204A , which means CO's would be wrong on 1205 too
unsure yet what changed on 1206, hence SMU is the same size ~ but on a PSP-FW update, i'd expect residues and changed behavior (permanent changes)
~ like it usually always was the case. Either different voltage behavior, different procODT behavior, different voltage limits ~ such things
^ and why i focus to port things instead of "just updating" ~ too risky. I don't trust AMD knowing the history of the updates so far


rossi594 said:


> Did you run >1.2v vsoc because your soc die is bad? Or does it help stabilize the overclock? Or just because it's easier to just punch it in and lower it later? It seems excessive in the context of my soc xD


1.25v SOC is the requirement for 2100 FCLK
Well 1.215ish ~ but i've changed things around since the public result and changed a bit voltages around to generally lower procODT as a whole down.

And hence it "just runs" , well enough ~ i don't want to touch it
Far to many variables to watch on, don't want to destabilize neither CO nor VDDG or VDD18 voltages ~ soo no touch there 
Scaled down, just to scale up








This has single error #1's so far, but RTT_NOM up or down creates a mixture of 0,1,14,5's all together
Else currently it's a single error for 30min ~ soo balance things 
Uses 1.56v which is slightly much, but the whole picture was to work with RTT_WR /2 or the highest possible ~ then see how DIMM-PCB behaves
That's the target on all of this, not timings or bandwidth.

Need to someday get back to win 10 again, and improve timings ~ but so far, i try to milk out more of this A0 Kit , soo work on my foundation ~ the powering
Same time as Audioboxer
Usually main intention was to get Hi-Z to work on SingleRank ~ with new gathered knowledge, but that showed as impossible 
New information is just for dual rank, tho still check if it's worth it all the trouble on running _WR 120ohm, instead of 60ohm

EDIT:








Haha, ty google
Yes Vermeer maximum SOC is 1.3v - likely damaging then is 1.35v 
1.25v is what the firmware defaulted to , and all values till 2133 where filled out ~ just that samples struggle with it. Else they where set in stone , in case anybody can run it


----------



## rossi594

Veii said:


> I've read reports of more things changing, hence PSP-FW update was done "apparantly"
> Soo also patches from microcode where removed and filled by placeholders ~ after 1204C onwards
> 
> This should've included a boosting table change after 1204A , which means CO's would be wrong on 1205 too
> unsure yet what changed on 1206, hence SMU is the same size ~ but on a PSP-FW update, i'd expect residues and changed behavior (permanent changes)
> ~ like it usually always was the case. Either different voltage behavior, different procODT behavior, different voltage limits ~ such things
> ^ and why i focus to port things instead of "just updating" ~ too risky. I don't trust AMD knowing the history of the updates so far
> 
> 1.25v SOC is the requirement for 2100 FCLK
> Well 1.215ish ~ but i've changed things around since the public result and changed a bit voltages around to generally lower procODT as a whole down.
> 
> And hence it "just runs" , well enough ~ i don't want to touch it
> Far to many variables to watch on, don't want to destabilize neither CO nor VDDG or VDD18 voltages ~ soo no touch there
> Scaled down, just to scale up
> View attachment 2545007
> 
> This has single error #1's so far, but RTT_NOM up or down creates a mixture of 0,1,14,5's all together
> Else currently it's a single error for 30min ~ soo balance things
> Uses 1.56v which is slightly much, but the whole picture was to work with RTT_WR /2 or the highest possible ~ then see how DIMM-PCB behaves
> That's the target on all of this, not timings or bandwidth.
> 
> Need to someday get back to win 10 again, and improve timings ~ but so far, i try to milk out more of this A0 Kit , soo work on my foundation ~ the powering
> Same time as Audioboxer
> Usually main intention was to get Hi-Z to work on SingleRank ~ with new gathered knowledge, but that showed as impossible


I have to agree that tras is magic. Don't break it =D


----------



## Veii

Hmmm
This topic will get quite annoying, i feel
Who or what to trust now
Thought i've spend more than "excessive amount" of work
and it still has math issues ~ yet my results should be correct
I don't understand

Who to blame 
The math should be fine, but even with the rounding advice ~ it wasn't fine

EDIT:
Can you guys check, what you get out on single rank 3800 , auto tRFC ?
It should "default" to near 350ns or @ 350ns
Somebody somewhere messed something up ~ either it's me, or it's AMDs FW design team


----------



## rossi594

Veii said:


> Hmmm
> This topic will get quite annoying, i feel
> Who or what to trust now
> Thought i've spend more than "excessive amount" of work
> and it still has math issues ~ yet my results should be correct
> I don't understand
> 
> Who to blame
> The math should be fine, but even with the rounding advice ~ it wasn't fine
> 
> EDIT:
> Can you guys check, what you get out on single rank 3800 , auto tRFC ?
> It should "default" to near 350ns or @ 350ns
> Somebody somewhere messed something up ~ either it's me, or it's AMDs FW design team


Reading your posts I would assume it was AMD. Do you think it makes senso to create a spreadsheet with all the "math". Would make tuning a lot easier if you just checked how far you can go on the values and the dependencies would show on it's own.

How much formulas are there really? 

tCL + tRCD = tRAS
tRP + tRAS = tRC

How many more am I missing?


----------



## PJVol

Veii said:


> I've read reports of more things changing, hence PSP-FW update was done "apparantly"
> Soo also patches from microcode where removed and filled by placeholders ~ after 1204C onwards
> 
> This should've included a boosting table change after 1204A , which means CO's would be wrong on 1205 too


idk, I thought main changes in PSP FW related to some recently found vulnerabilities and B2 revision support in SMU 56.65, I mean this annoying VID limitation. Can't say the performance decrease overall is a concern for majority, but for us, enthusiasts, its definitely a regress.
The boosting isn't change much, apart from the cases where VID limit is involved.

Btw, do you (or anyone else) wanna check my simple utility for CO and PBO limits tuning?
I wrote it, while learning C# and VS at the same time (special thanks to Rusanov), so pls don't be too rude on me for this first experience.

So far, the only significant limitation is it can't read CO values from BIOS, so I've made it so it keeps user settings in a local storage.





Debug.7z







drive.google.com











Just want to be sure, it works correctly on all Vermeers.

*P.S.*
If you experience some error on application start, it may be due to corrupted config, that may happen if sudden reboot occur, try to delete this folder:
c:\Users\<your name>\AppData\Local\pjvol
before you launch an app.


----------



## Veii

rossi594 said:


> Reading your posts I would assume it was AMD. Do you think it makes senso to create a spreadsheet with all the "math". Would make tuning a lot easier if you just checked how far you can go on the values and the dependencies would show on it's own.
> 
> How much formulas are there really?
> 
> tCL + tRCD = tRAS
> tRP + tRAS = tRC
> 
> How many more am I missing?





> There is far more, but ones are estimates
> Other ones are estimates based on experience
> some are rules based on stability but not minimum rulesets
> Some are minimum rulesets that have no information which factors have to be met
> and sadly the main problem:
> "memory tuning has not a correct answer, and performance tuning will depend by application and size of the dataset, or generally the size of data that has to be pushed & moved"


most rules follow JEDEC, but JEDEC doesn't follow reality. JEDEC follows design guide and behavior that has to work ~ not peak limits and not minimum limits. It's "optimal limits before it's tagged as defect"
Single IC has over 1.3million cells in it, and some of them can not follow the JEDEC ruleset yet be within margin to be accepted as "functional" and not "defective"

tRC rule, while being correct ~ will not match with reality.
A good IC engineer here on OCN here had explained it well, how fascinating he himself find his work and JEDEC as a whole. Having to create an IC with that many cells, on nano-scale and all follow the same discharge pattern of all 1.3millions of them

In general, it is not possible
My plan was initially , 2ish years ago to start and make a pure simulation of it. From start to end, then check that way what timing is a bottleneck or too slow
Generally a quite big draft i've started a long time. This module of tRFC was taken out of it, because it was pretty much done.
But i missed crucial timings and zero information or support how to make them up from thin air. Soo the project is on hold & i shifted priority

Sadly, too many people who trust fully on JEDEC as their maximum values - forget above
There can't be "one correct" rule that covers minimum,
And there can't be one always correct answer to a fully dynamic system, that is based on outer sources.
(Like EMI, Gravity, moisture, heat ~ well pretty much discharge prediction. The same thing that tRFC mini or generally the whole project was focused about. Judging OCers do not see the whole picture.)

Soo while google calculator, made by the community ~ exists








Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com




Which kept beeing broken the whole time. The same is for my sheet. People do not want it to exist and make the life hard

It is still not a perfect writeout as once was done for DDR3
And even if it exists still somewhere (DDR3) , people break it and it's listed to private.
You know, people don't want to have helpful things and will do everything to destroy it ~ if it's against their moral.
That's why we "don't have nice things"
=====================================
Just the main reason with what i want to answer you, is:
It can't be done
It can't be done correctly.
Either we accept all of them, or we accept non of them ~ because reality is different than book writing

I as trying to be a contributor to this, accept all ~ and see which work with reality. Not which maybe are correct by book, for a company.
Overclocker do not move with "basics" but extend limits. That's OCers work. Push industry forward, not follow a holy book that nobody can agree on what really is correct or is not correct


----------



## Nighthog

PJVol said:


> Btw, do you (or anyone else) wanna check my simple utility for CO and PBO limits tuning?
> I wrote it, while learning C# and VS at the same time (special thanks to Rusanov), so pls don't be too rude on me for this first experience.
> 
> So far, the only significant limitation is it can't read CO values from BIOS, so I've made it so it keeps user settings in a local storage.
> 
> 
> 
> 
> 
> Debug.7z
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> View attachment 2545010
> 
> Just want to be sure, it works correctly on all Vermeers.
> 
> TRFC default
> View attachment 2545011


Fails with a 5700G & X570 Xtreme motherboard.


----------



## Audioboxer

Veii said:


> Does this add up ?
> ~ 1.5v
> View attachment 2544975
> 
> tCWL and tCL are combined.
> tRDWR & tWRRD rather would "cause issues" on tWPRE, tRPRE missmatch
> Although they should have something to do with SD, DD's ~ they do not show such behavior.
> Nevertheless if 1-4-4-1-6-6, 1-5-4-1-7-6, or the current 1-5-5-1-7-7
> They do not change the outcome, of one dimm being a lower auto predicted value.
> 
> Most is on Auto to catch per channel differences
> Except for tCKE, SD,DD's, tWTR_ & tRRD_, tWR & tRTP
> Well and powering logically ~ as that's the goal of this scaling work
> 
> Looks good
> Well, "we'll see" ~ i mean
> We both seem to make progress, i hope
> View attachment 2544976
> 
> That's been yesterdays fun ~ bit creepy face, for a creepy experience till the late night
> Many 1's (200), couple zero's, couple 14's, couple 5's
> Lower ClkDrvStr by one, higher VDIMM from 1.44 to 1.5, stronger RTT_NOM as exchange
> Error free.
> Scaling continues on RTT_WR/2
> 
> Hope to see same good progress on your side too~
> Good morning












Been getting an error on 7 I'm struggling to clear. Tends to come later on in testing, likes of around 5~7 cycles on, hence why you've seen me pass a few 6 cycles now. Started with loosening up some more timings, though I haven't tried tFAW yet (IIRC I've seen a few people run 24 or around there instead of 16 at high frequencies).

Failing it being timings, I guess I'm going to have to look at resistances and DrvStr.

In terms of Rtts, I can re-enable RttNom, doesn't interfere with tPHYRDL. RttWr 1 is pretty much locked in though, along with RttPark 6. If I change away from RttWr 1 instant F9 issues and failures to boot. Just seems like 1/6 is the "magic" combo at these frequencies for me.

So I'm hoping tFAW or DrvStrs can help clear up the error 7. We're soo close to being able to get 4566 stable and time for benchmarking


----------



## Veii

PJVol said:


> Just want to be sure, it works correctly on all Vermeers.


Sorry










Audioboxer said:


> View attachment 2545019
> 
> 
> Been getting an error on 7 I'm struggling to clear. Tends to come later on in testing, likes of around 5~7 cycles on, hence why you've seen me pass a few 6 cycles now. Started with loosening up some more timings, though I haven't tried tFAW yet (IIRC I've seen a few people run 24 or around there instead of 16 at high frequencies).
> 
> Failing it being timings, I guess I'm going to have to look at resistances and DrvStr.
> 
> In terms of Rtts, I can re-enable RttNom, doesn't interfere with tPHYRDL. RttWr 1 is pretty much locked in though, along with RttPark 6. If I change away from RttWr instant F9 issues and failures to boot. Just seems like 1/6 is the "magic" combo at these frequencies for me.











Is this WIP sheet invisible ?
It's purely voltage related

2Mb tests are burst tests,
It's either a timing issue with tRFC (very unlikely) , an overcurrent issue with VDIMM (more likely)
Or an RTT issue with RTT_NOM or PARK (well or just bad tCKE value or bad SETUP Timing) value
A timing (accuracy, not tCK value) issue ~ just pretty much everything points to voltage, literally zero to Timing


----------



## Audioboxer

Veii said:


> Sorry
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Is this WIP sheet invisible ?
> It's purely voltage related
> 
> 2Mb tests are burst tests,
> It's either a timing issue with tRFC (very unlikely) , an overcurrent issue with VDIMM (more likely)
> Or an RTT issue with RTT_NOM or PARK (well or just bad tCKE value or bad SETUP Timing) value
> A timing issue ~ just pretty much everything points to voltage, literally zero to Timing


What would cause an over current with VDIMM? Because in my eyes it must be something working in conjuction with VDIMM, not my VDIMM value itself. 1.6~1.62v has been fine on other profiles.

As I said I can re-enable RTT_NOM for testing, IIRC Park 5 can boot, but RttWr 1 seems to prefer Park 6. This profile seems to be hugely reliant on RttWr 1.

tCKE is at 15, I wouldn't know what else to try playing with. I guess trying 1 or AUTO (0)? As you've educated me on though at these frequencies we likely need a cleaner signal and that's why we're using something like tCKE 15. If I wanted to test around that would it be trying 14 or 16?

Setup timings aren't in use so can't be them, unless you suggest trying to start using them? IIRC this wouldn't mean using 56, but trying a combo that works well with tCKE 15? Would that be like 6 or 7?

I'm sure I'll get there, this is the fun part of pushing something 🤝


----------



## Melan

Veii said:


> Which kept beeing broken the whole time. The same is for my sheet. People do not want it to exist and make the life hard


It's really more about people being a-holes on the internet because they can. And some just legit do not know that you can copy the calculator to your own drive and mess with it all you want.



Veii said:


> A good IC engineer here on OCN here had explained it well


Got a link for that?


----------



## Veii

Melan said:


> Got a link for that?


Funnily, actually found it.








How to calculate tRC timing in cycles?


Hi. I was looking for some additional ram for my aging desktop PC and tried to find modules that match the timings perfectly. At first I thought I found a perfect match with some Kingston modules, but on a closer look things are a bit weird. Wikipedia, among other sources states that tRC =...




www.overclock.net






> Anyway, to vastly simplify the way that these capacitors are produced, various chemicals (Argon, Phosphorous, Dielectrics) are deposited onto silicon in plasma form at extremely high temperatures. This production process has literally hundreds of steps. It's not only one person's jobs but _hundreds_ of people's jobs at each of these companies _just _to optimize the number of processing steps and the order of these steps. Each step has the opportunity to introduce variation onto the wafer.
> 
> each DRAM die is a unique snowflake. Half of the capacitors might need to be refreshed every N cycles, while the other half absolutely need to be refreshed in N - 3 cycles. A little "chunk" of the die (usually in a semicircle pattern) might have sense amplifiers that can detect bits within 3 cycles while the rest of the die needs 8 cycles. All this is to say that any formulas that you see that relate DRAM timings together is based on theoretically ideal conditions of a single capacitive memory device operating in isolation. You have billions and billions of memory devices, in the case of 16 GiB of memory 137,438,953,472 memory devices (that's not a typo).
> 
> The result is that you often have a die in which some timing, like precharge time, can be pushed very hard, because all of the process steps related to producing the sense amplifiers was perfect. However, cycle time must be relaxed because one third of the capacitors hold 12% less charge than the other two thirds.
> 
> So again, every die is a unique snowflake. You can use theoretical relationships between timings to determine the optimum conditions for the _best _DRAM cell of your 137,438,953,472 memory cells (and they all have to work!), but each timing will find some limitation based on the worst performing component (sense amplifier, addressing logic) related to some individual cell or some collection of cells. The slowest subcomponent in any stage of the DRAM pipeline limits the timing of that pipeline stage.


I might call it "cycle" but it's "pipeline"
And i misstook millions with billions - different measuring system, not used to imperial

He is a nice guy, but it seems his time was rather 2011-2012, active time


Audioboxer said:


> If I wanted to test around that would it be trying 14 or 16?


Go on 
Usually it shows itself as #6 or #0 issue, the misstimed tCKE.
My tCKE range should be perfect, but i'd like to see it not be.
Especially when there are also alternative values that align 


Audioboxer said:


> Setup timings aren't in use so can't be them, unless you suggest trying to start using them?


Absolutely no xD
Just asks for issues right now.


Audioboxer said:


> Setup timings aren't in use so can't be them, unless you suggest trying to start using them? IIRC this wouldn't mean using 56, but trying a combo that works well with tCKE 15? Would that be like 6 or 7?


They + RTT_WR + tCKE work independent, but affect each other
Dynamic ODT does shift it by itself and manages the CKE signal (clock pulse)
SETUP timings delays the trace length and the commands send from the IMC (i think ~ but it's rather trace and MCLK focused , not dimm focused)
tCKE i actually am not sure, AMD system operates unique and doesn't follow JEDEC.

tCKE should not only change the timing of the clock signal from IMC towards DIMM ~ up to MCLK
But should also increase the density of it , and ontop of that also control powerdown or not powerdown

I think it has even more work/options - like all of the above have caviats, for example:
SETUP timings changing behavior and reversing behavior after value 32 ~ being more GDM like, or it's just the sideproduct of the change not the change itself. idk
RTTs changing behavior and being unique between ranks if dimm has more than one rank.
Dynamic ODT actually doing error correction if enabled. Changing behavior of NOM & PARK, which change behavior by rank. And also shifting the dataeye slightly to align it and increase it's size

All these 3 do much more work than usually written between pages
Everyone seems to write more or less about it. Micron has it different. Siemens has it different for DDR4. JEDEC has it different. And AMD does also what they want.
It's complicated.
Soo tCKE doing more than just being powerdown related ~ was clear since the launch and i should've made it public.
(if anybody on the "bigger media OC guys" would actually listen to me)
There is not one JEDEC, and there is not one memory controller company. Every memory controller designer has own rules. JEDEC have close to zero to do with what we get these days out. Everything is on custom PCBs with vendors doing their own "vendor related timings" that are hard-fused in the controllers of these dimms. Following JEDEC blindly makes no sense 


Audioboxer said:


> I'm sure I'll get there, this is the fun part of pushing something 🤝


Soo one single 7 ?
when ?
did you let it run longer ?
It is not thermal discharge related ~ aka "when" and how many ?

Can you post what fails ?
* what you run and when it fails, to give suggestions


Veii said:


> They + RTT_WR + tCKE work independent, but affect each other


tCKE + RTT_WR , fine
tCKE + SETUP Timings, fine
SETUP timings + RTT_WR , fine

All 3 together, purely trouble
Somehow dynamic ODT (being dynamic, realtime) 
And SETUP timings being MCLK related, but fixed 
~ bother

tCKE is MCLK related but fixed, 
SETUP timings is MCLK related, but fixed
All 3 just asks for trouble and i can't get them correct.


----------



## PJVol

Veii said:


> Sorry


I'm sorry )) it was wrong build. I fixed the link in the original post, check pls.


Nighthog said:


> Fails with a 5700G & X570 Xtreme motherboard.


I know, so far only Vermeer support. But when i get to the office (tomorrow or monday), i'll check on my 5700g and think i can add cezanne support.
Cezanne and Vermeer SMU fw are too much different, but fortunately mailboxes and pm_tables are well studied by the community.


----------



## Veii

PJVol said:


> I'm sorry )) it was wrong build. I fixed the link in the original post, check pls.












Soo i should fill out and apply the bios curves , soo it generates and remembers them ?
EDIT:
Huh ?








What ??








Peak CCLK only applies the lower you go
4800 did nothing, because i started with 4750
But 4750 was odd and jumped higher to 4790ish
4725 then went back to 4.725 but reality is ~ sample exceeds it and then goes back to my 4.85 ?!?
... this makes no sense ^^#


----------



## PJVol

Veii said:


> Soo i should fill out and apply the bios curves , soo it generates and remembers them ?


Yeah. Forgot to add, at first launch, better to clear all CO values set from bios at boot time, by clicking "Reset" to start from the scratch, or you can fill in your bios values and then click "Apply" to remember them.
IMPORTANT: App "remembers" in an application local storage, not in BIOS. For being persistent, you have to enter them in BIOS manually.




Veii said:


> Peak CCLK only applies the lower you go
> 4800 did nothing, because i started with 4750
> But 4750 was odd and jumped higher to 4790ish
> 4725 then went back to 4.725 but reality is ~ sample exceeds it and then goes back to my 4.85 ?!?
> ... this makes no sense ^^#


There's at least three hard max. frequency limiters i know of. The one in BIOS has higher priority. There's also limits set through MP1, HSMP and SB-RMI (APML). Not sure, though, if some are duplicated, most likely APML is actually performing MP1 requests. HSMP is different.
I use HSMP limit, which isn't showed in a pm table, but it "just works" 

PS: )) more bad news for you is +30 / -30 range is restricted in SMU fw itself, perhaps somewhere in a mailbox interface part of MP1, and not in vendor BIOS part. I've tried values below -30 : they do nothing and just have been cut out on (-30,30) boundaries.


----------



## Audioboxer

Veii said:


> Funnily, actually found it.
> 
> 
> 
> 
> 
> 
> 
> 
> How to calculate tRC timing in cycles?
> 
> 
> Hi. I was looking for some additional ram for my aging desktop PC and tried to find modules that match the timings perfectly. At first I thought I found a perfect match with some Kingston modules, but on a closer look things are a bit weird. Wikipedia, among other sources states that tRC =...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> I might call it "cycle" but it's "pipeline"
> And i misstook millions with billions - different measuring system, not used to imperial
> 
> He is a nice guy, but it seems his time was rather 2011-2012, active time
> 
> Go on
> Usually it shows itself as #6 or #0 issue, the misstimed tCKE.
> My tCKE range should be perfect, but i'd like to see it not be.
> Especially when there are also alternative values that align
> 
> Absolutely no xD
> Just asks for issues right now.
> 
> They + RTT_WR + tCKE work independent, but affect each other
> Dynamic ODT does shift it by itself and manages the CKE signal (clock pulse)
> SETUP timings delays the trace length and the commands send from the IMC (i think ~ but it's rather trace and MCLK focused , not dimm focused)
> tCKE i actually am not sure, AMD system operates unique and doesn't follow JEDEC.
> 
> tCKE should not only change the timing of the clock signal from IMC towards DIMM ~ up to MCLK
> But should also increase the density of it , and ontop of that also control powerdown or not powerdown
> 
> I think it has even more work/options - like all of the above have caviats, for example:
> SETUP timings changing behavior and reversing behavior after value 32 ~ being more GDM like, or it's just the sideproduct of the change not the change itself. idk
> RTTs changing behavior and being unique between ranks if dimm has more than one rank.
> Dynamic ODT actually doing error correction if enabled. Changing behavior of NOM & PARK, which change behavior by rank. And also shifting the dataeye slightly to align it and increase it's size
> 
> All these 3 do much more work than usually written between pages
> Everyone seems to write more or less about it. Micron has it different. Siemens has it different for DDR4. JEDEC has it different. And AMD does also what they want.
> It's complicated.
> Soo tCKE doing more than just being powerdown related ~ was clear since the launch and i should've made it public.
> (if anybody on the "bigger media OC guys" would actually listen to me)
> There is not one JEDEC, and there is not one memory controller company. Every memory controller designer has own rules. JEDEC have close to zero to do with what we get these days out. Everything is on custom PCBs with vendors doing their own "vendor related timings" that are hard-fused in the controllers of these dimms. Following JEDEC blindly makes no sense
> 
> Soo one single 7 ?
> when ?
> did you let it run longer ?
> It is not thermal discharge related ~ aka "when" and how many ?
> 
> Can you post what fails ?
> * what you run and when it fails, to give suggestions
> 
> tCKE + RTT_WR , fine
> tCKE + SETUP Timings, fine
> SETUP timings + RTT_WR , fine
> 
> All 3 together, purely trouble
> Somehow dynamic ODT (being dynamic, realtime)
> And SETUP timings being MCLK related, but fixed
> ~ bother
> 
> tCKE is MCLK related but fixed,
> SETUP timings is MCLK related, but fixed
> All 3 just asks for trouble and i can't get them correct.












I just got a timeout on cycle 9, problem is I'm using your disable idle script, so it must be memory issues.










Going to give Karhu a go just because I haven't tried it with 4533. Thermals aren't an issue, during TM5 no higher than 30~31 degrees.


----------



## Veii

PJVol said:


> PS: )) more bad news for you is +30 / -30 range is restricted in SMU fw itself, perhaps somewhere in a mailbox interface part of MP1, and not in vendor BIOS part. I've tried values below -30 : they do nothing and just have been cut out on (-30,30) boundaries.


MP1 i need to learn further
Yuri seems to be able to work around it, as he can use Hydra values beyond 188
(1 Bios CO = 6.25 Hydra CO)
HSPM seem to change and get updated. The old data missed information ~ needed PPR Q3 2021.

But Hydra uses RSMU mostly, haven't seen him do anything HSPM related


PJVol said:


> There's also limits set through MP1, HSMP and SB-RMI (APML). Not sure, though, if some are duplicated, most likely APML is actually performing MP1 requests


I wonder if it makes sense "on this platform" to make a thread about potential non official values for ryzen control
Been censored once , which was not connected to moral or behavior ~ it was more about critique but the post is gone.

Hence TOS here would also state that illegal sharing or things is prohibited (which is good)
I am somewhy sure, that post with AMD data would also be removed.
Questioning, if it makes sense to make a thread for this especially ~ just OCN can wipe everything away, if AMD gets mad
-
CMD: 0x03B10528
RSP: 0x03B10574
ARG: 0x03B10A60
-
CMD: 0x03B1052C
RSP: 0x03B10578
ARG: 0x03B10A80
-
Do you know what these are for ?
Funnily, if RSMU is in use - it can't be found and remains hidden
That way access is capped to it


Audioboxer said:


> I just got a timeout on cycle 9, problem is I'm using your disable idle script, so it must be memory issues.


I haven't fully confirmed it resolves it, but it should - because that way cores can not idle
Yet the OS deep sleeps on me after TM5 is finished








Be sure that this thing is also gone, if you ever get it
Although i think it was rather with the old crimson driver
Funnily while Win11 is a broken mess for AMD, (still)
I don't have such infinity timeout issues

The only other thing you can try, is disabling NX protection - under CPU features


----------



## PJVol

Veii said:


> Do you know what these are for ?


0x03B10528 ... and 0x3b10524 ... seem to be duplicated rsmu interfaces. 0x6C returns FIT scalar value from both.

0x03B1052C has two commands, first - set IPC boost +100%, 2nd - call for a hooker in Vienna for free.
Idk, what this port is for to be honest



Veii said:


> Yuri seems to be able to work around it, as he can use Hydra values beyond 188


I thought he's not using dldo's and just "emulate" offsets by software.


----------



## Veii

PJVol said:


> 0x03B10528 ... and 0x3b10524 ... seem to be duplicated rsmu interfaces. 0x6C returns FIT scalar value from both.


I'd need to try 
Sending something while RSMU is busy
maybe if XPREHOPE3 changes target for MUTEX calls

the readout tool can run ontop of hydra and similar
If this really is an alternative "port"







Sharing fuels development
There are interesting things about SETUP timings and general creation of timings
And things we haven't heard of yet should be interesting to be visible in the bios








============================
Zero'd CO's








High voltage requests, very overvolted sample
I'll try and see what we can do with this

You can set CO's (modify) after setting CO's , right ?
There won't be any stack issue, or requirement to reboot or anything odd ?
EDIT:
@PJVol 








There are very fascinating things to it
SOC "limit" and MAX_SOC Voltage limit changed lower than usual, working "with this method"
Bios OC seems to limit it up to 1.3090v (SOC) ~ independent of scalar
Without doing anything, FIT limit for me was higher, and FIT Value actually was higher

Doing "this method" SOC limit got lower
Apparently SOC throttles now
And FIT value barely spikes up in usage
Generally odd behavior ~ but COs work out
Erasing and writing new ones

Just comes with some caveats, soo potentially fine for 99% of the users together with core cycler 
Good job !


----------



## Audioboxer

Problem with Karhu is absolutely no indicator about what is wrong. Worth a go anyway.

Back to the drawing board with TM5, IMO clear the timeout wasn't Windows 11, have to find out what is on the edge of stability.


----------



## Veii

Audioboxer said:


> View attachment 2545054
> 
> 
> Problem with Karhu is absolutely no indicator about what is wrong. Worth a go anyway.
> 
> Back to the drawing board with TM5, IMO clear the timeout wasn't Windows 11, have to find out what is on the edge of stability.


Good confirmation
Hmm i'd say give 30-20-30-30 a try , if it does "anything" 
but this needs then a VDIMM bump

I wonder if we've changed RTT's
If no, voltage should not cause issues
If yes, then that's why you need to change VDIMM too. Voltage by itself is "halfway irrelevant"

Tbh i'm still sitting on error #1 , or #11 as single digit ones
something cad bus, something voltage, something nothing works
A combination of all of them  
Sadly no progress so far ~ maybe tonight or tomorrow


----------



## Audioboxer

Veii said:


> Good confirmation
> Hmm i'd say give 30-20-30-30 a try , if it does "anything"
> but this needs then a VDIMM bump
> 
> I wonder if we've changed RTT's
> If no, voltage should not cause issues
> If yes, then that's why you need to change VDIMM too. Voltage by itself is "halfway irrelevant"


Rtts are a struggle, either full-stop or without a complete re-think. RttWr 1 is basically mandatory as things stand to boot. Then that likes RttPark 6. As I mentioned earlier I can re-enable RttNom without an issue. That's about it unless you want to try a complete re-think. This 1/6 has resulted in perfect boots every time though.

Might start with DrvStrs first. I don't think VSOC coming down to 1.15v should be an issue, but maybe worth playing with it again as well. Even dom runs his VSOC higher than 1.15v at 3800.


----------



## hazium233

Veii said:


> Does this add up ?
> ~ 1.5v
> View attachment 2544975
> 
> tCWL and tCL are combined.
> tRDWR & tWRRD rather would "cause issues" on tWPRE, tRPRE missmatch
> Although they should have something to do with SD, DD's ~ they do not show such behavior.
> Nevertheless if 1-4-4-1-6-6, 1-5-4-1-7-6, or the current 1-5-5-1-7-7
> They do not change the outcome, of one dimm being a lower auto predicted value.
> 
> Most is on Auto to catch per channel differences
> Except for tCKE, SD,DD's, tWTR_ & tRRD_, tWR & tRTP
> Well and powering logically ~ as that's the goal of this scaling work


The interesting part is still that it is channel A that is increasing tRDWR.

I can't say as I understand the whole picture, but before you said to go with what I observe and that is what I observe on my MSI motherboard. Like with my weird GDM example earlier where the channel went to 28, trained 9 - 2 for RDWR WRRD and was stable. But if change so PHY goes to 26, the tWRRD is hugely unstable. _shrug_

One of the mistakes I made earlier was simplifying "read latency" and "write latency" into just CL and CWL, where they can't be done when there is all manner of latency added in IO and return trip.

The rest will be long and I don't know if anyone would read these ramblings

...

In my bios there is the value "Tphy_rdlat" which seems to correspond to what is reported in ZenTimings as tPHYRDL. Unlike tPHYRDL which is pretty mysterious if googled, tphy_rdlat is mentioned in a lot of DDR controller discussions. Similarly there is tphy_wrlat mentioned, which is for writes. The write part seems somewhat more straightforward, considering what I see.

tphy_wrlat was listed as "approximately" as the write latency minus a couple values, one of which is tPHY_WRDATA.

In ZT there are both tPHYWRL, which may be ~ tphy_wrlat and also tPHYWRD which lists as 2, and is probably tPHY_WRDATA.

Just generally, tPHYWRL seems to usually be CWL - 5 on Zen3, and so moves around when CWL is changed. That makes sense to me. Maybe there are examples where it is slightly different. But I played around with them at 3200, skimmed the leaderboards, etc. There were basically no results for very high values, so I checked CWL 18 to 12 myself. It also doesn't seem that clock speed is adding any more to the value. Your own 4200 result is same 14-5 = 9

...

tphy_rdlat or tPHYRDL doesn't seem to make much sense. In one place it was described generally as being sum of RL + IO latency + "board latency", where RL is read latency in mem clocks (so CL + any AL). Other place had a more strange formula but I don't know if that was specific for that DDR3.

I can't see it as depending on CL in a normal way for Zen 3. It seems more to do with accuracy of the settings similar to what you said before, and some on clock stage. Or memory controller grumpiness, whatever. For instance at 3200 it did not go higher than 26 even with CL up through 28t.

I thought it had to partly represent added latency to CL. Which is why when you get PHYRDL bump it seems to make CL 15 to test similar to CL16 or whatever the case.

Anyway the other value in bios under Tphy_rdlat is "DFI MaxReadLatency." DFI being DDR PHY Interface I assume. Relationship seems to be for me:

Tphy_rdlat - DFI MaxReadLatency

22 - 5
24 - 6
26 - 7
28 - 8
..

When I did the seemingly "simple" timing checks I didn't get entirely expected result though. I used 3200 because I thought anybody could do same tests at this stage, tRDWR - tWRRD training was entirely as expected based on CL and CWL difference, even if it had good train at tPHYRDL 24 or worse at 26. So could be either above speculation was wrong, or the 24 to 26 is not worth the same difference as 26 to 28, or 28 to 30 or whatever.

Channel A was still the one with higher RDL if mismatch, so there is something about the channel.



Spoiler





























CL18 - CWL16









CL18 - CWL18










CL18 - CWL14










CL17 - CWL16










CL16 - CWL16










CL16 CWL 14 - first one that trained 24/24










CL15 - CWL14 - back to 26










CL15 - CWL14 - RDWR 10 (manual)










CL14 - CWL14










CL14 - CWL14 - 24/24










CL14 - CWL12 - ChA - boot1











CL14 - CWL12 - ChB - boot1










CL14 - CWL12 - ChA - boot2










CL14 - CWL12 - ChB - boot2










Grumpy PHY settings I guess

CL18 - CWL 18 - boot from above, kept RDL










CL24 - CWL18 - ChA










CL24 - CWL18 - ChB










CL28 - CWL18 - ChA










CL28 - CWL18 - ChB












Most everything on right was just "auto" for 3200, which probably explains most the variation for tPHYRDL, rather than CL.

Probably should have done 3600, maybe I will quickly check that later. I don't know, seems like I only get more questions not answers, heh.


----------



## Veii

hazium233 said:


> Probably should have done 3600, maybe I will quickly check that later. I don't know, seems like I only get more questions not answers, heh.


These values i can look up (calculation formula's)
If we have the name, they make sense

It's odd that my board fully refuses to post tPHYRDL 30, at all
And hardcaps that way
It's also odd that when i select 4966, it loads own strange timings and procODT ~ which all make no sense and can't boot


Spoiler: Data






Spoiler: RxDatChnDly












^ memory training channel delay





Spoiler: MRL & DFI MRL




























DFI_RdData_EN & _VALID








^ memory training & Clock Gating for UMC





Spoiler: Vref on DDR4 & LPDDR4












^ on DDR4 it's always beyond half. DDR3 was less or equal than half
Shown is a control and anchor for control, but the work is identical


Notes & Tutorial


Spoiler: FIFO Meaning & Illustration ~ just learned














Spoiler: Illustration































Soo hence FIFO's are consistently checked and control operations.
Hence AMDs PHY controller already supplies and changes DFI-Clock, where both Read latancies and general latencies are set
Both MP0 and MP1 would only control & delay the time X (in some DWORD value) , till each of the read and write operation on FIFO
(which is controlling data in and data out ~ before it's spread to cells or to banks or ranks)

The only potential usecase i can see by purely guessing a new learned thing/controller
~ is to either increase it, in matching dynamic MCLK switching (alignment of UMC to DFICLOCK, soo UCLK to MCLK alignment ~ guessing)
~ or to delay it (value = 2tCK, two memclk value, transfer time) if memory is unstable between ICs or ranks.
Soo potentially any usecase for very high voltage, to prevent cells from crashing ~ probably potentially only useful for XOC. But also probably potentially should not be touched at all 





This took time to learn and write, excuse me
Still out of my head, but i can slowly see / and probably understand why they want to align MCLK and UCLK soo much - or half it
Instead of running higher MCLK UCLK, than FCLK
Although documents say, it potentially could work

Good to know at least, that memory training is fine ~ a lot of thought has been pushed into it
And very good to know that MSI pretty much supplied a pattern/preset to extend the bios with all the new headers and informations ~ if bios modder would have correct descriptions
* they can just create new options and put new options in place, as formatting preset already exists. Very comfortable

Information is slightly jumping between Vermeer and Cezanne, soo also Renoir
But you can gather most
Hmmm, in theory somebody could make a fully open bios with full access ~ for memory OC
In practical theory, it would be possible and nothing preventing it 

But in realistic practical theory, that would require ~somebody~ , to have the same access, have the same time, know more about the bios and start to do bios mods for everything
Then also sign them
This practical theory ~ then shows to be less practical reality 
But probably can be a thing~


----------



## Veii

Audioboxer said:


> Rtts are a struggle, either full-stop or without a complete re-think. RttWr 1 is basically mandatory as things stand to boot. Then that likes RttPark 6. As I mentioned earlier I can re-enable RttNom without an issue. That's about it unless you want to try a complete re-think. This 1/6 has resulted in perfect boots every time though.
> 
> Might start with DrvStrs first. I don't think VSOC coming down to 1.15v should be an issue, but maybe worth playing with it again as well. Even dom runs his VSOC higher than 1.15v at 3800.


There will be nothing preventing trial and error now
But to not waste time ~ i'd like you to test one thing

Go down to 3600MT/s, somethign 13-13 or 14-14, whatever you like
Start with 1.42v, and try to run Hi-Z on RTT_NOM








For example 
tRRD_ , tWTR_, tRTP, tWR , tRFC all on auto

You need some PARK for many rank dimms, else it doesn't function ~ NOM is not needed on sub 1.45v. I think it should run for you at 1.2-1.25v (follow tCKE for DR!)
Try this and check if you can even boot 1mhz higher than 1800 strap
Curious to see if ASRock or AMD where lazy ~ one of both 
tPHYRDL was a missmatch , ignore it, but please try Hi-Z for me
Pretty much the same SD, DD, procODT, CAD_BUS
(low voltage ~ it's amplifying it too much and dimms will be hot)


----------



## Audioboxer

Veii said:


> There will be nothing preventing trial and error now
> But to not waste time ~ i'd like you to test one thing
> 
> Go down to 3600MT/s, somethign 13-13 or 14-14, whatever you like
> Start with 1.42v, and try to run Hi-Z on RTT_NOM
> View attachment 2545095
> 
> For example
> tRRD_ , tWTR_, tRTP, tWR , tRFC all on auto
> 
> You need some PARK for many rank dimms, else it doesn't function ~ NOM is not needed on sub 1.45v. I think it should run for you at 1.2-1.25v (follow tCKE for DR!)
> Try this and check if you can even boot 1mhz higher than 1800 strap
> Curious to see if ASRock or AMD where lazy ~ one of both
> tPHYRDL was a missmatch , ignore it, but please try Hi-Z for me
> Pretty much the same SD, DD, procODT, CAD_BUS
> (low voltage ~ it's amplifying it too much and dimms will be hot)


Some more data for you first










I decided to be lazy and change 4 things at once (I know, bad). VSOC and VDIMM +1 notch, and your 30/20/30/30. Boom, error on 7 super fast.










I then decided to scale back to what I should have done from the Karhu run, left voltages the same, just swap to 30/20/30/30. It took till cycle 20 to spit out a 7 followed by 10.

It seems as if I'm super voltage sensitive right now and you're right about over current crashing the PCB. I guess I could try dropping VSOC and VDIMM one more notch and seeing how TM5 behaves on another run at 30/20/30/30. I'm guessing the Rtt values I'm using contribute to a lot of stress at high voltages, but obviously running flat 16 at 4533 is going to require some voltage to juice it. Like threading the eye of a needle balancing this.

We're soo close! I want to test what you've just laid out but I'm also crying at how I got to 20 cycles with the above lmao.


----------



## Veii

Audioboxer said:


> We're soo close! I want to test what you've just laid out but I'm also crying at how I got to 20 cycles with the above lmao.


Haha
I am absolutely not confident on 30-20-30-30
Still fighting and reach nothing
~ higher AddrCmdDrvStr (to elivate using SETUP timings) hardcrash
~ higher AddrCmd and weak ClkDrvStr, still hardcrash
~ higher CkeDrvStr, hardcrash
~ 20ohm low CkeDrv ~ hardcrash 
~ higher NOM , hardcrash
~ weaker NOM, hardcrash

It's sadly common occurrence
High PARK or High WR , completely overpowers the dimm PCBs
But just pumping voltage didn't work.
I can be happy that so far my range is 1.68ish , instead of 1.5 or lower
That's i feel well earned progress, compared to old Matisse and DRAM Calculator research
Especially when voltage is irrelevant to heat - but very relevant to timings

Stronger WR instead stronger Park feels more natural, and dynamic data-eye correction is a free bonus
But somewhy Park 7 or Park disabled is still too strong
Then dropping ClkDrvStr down, messes up everything including procODT.
It's a pain 

Want to get it to work, even with worse thermals and worse results, just to have something to jump back to ~ alternative mode
Then maybe higher latency thanks to DynamicODT has to be outweight, but for now ~ it's fighting against the PCB and trace design 
We'll get it, but DR is certainly more annoying
I'd prefer your great Dimms, and you can get my sensitive snowflakes 

EDIT:








This works soo well, for SR
But i can't move higher than 1.67-1.68v.
Can't do anything, it's maxed

WR_/2 , Park Zero would be interesting, but so far nothing (it's much stronger than WR 60, Park 40.)
Maybe requires me to go procODT 28 , install win 10 and redo voltages from scratch again zZZ
And for DR, Hi-Z plus PARK 7 was quite strong too. 1.25v dimms reached 48° 
AMD has no NOM Hi-Z like initially planed, soo idk 😣


----------



## Audioboxer

Veii said:


> Haha
> I am absolutely not confident on 30-20-30-30
> Still fighting and reach nothing
> * higher AddrCmdDrvStr (to elivate using SETUP timings) hardcrash
> 
> 
> higher AddrCmd and weak ClkDrvStr, still hardcrash
> higher CkeDrvStr, hardcrash
> 20ohm low CkeDrv ~ hardcrash
> 
> 
> It's sadly common occurrence
> High PARK or High WR , completely overpowers the dimm PCBs
> But just pumping voltage didn't work.
> I can be happy that so far my range is 1.68ish , instead of 1.5 or lower
> That's i feel well earned progress.
> Especially when voltage is irrelevant to heat - but very relevant to timings
> 
> Stronger WR instead stronger Park feels more natural, and dynamic data-eye correction is a free bonus
> But somewhy Park 7 or Park disabled is still too strong
> Then dropping ClkDrvStr down, messes up everything including procODT.
> It's a pain
> 
> Want to get it to work, even with worse thermals and worse results, just to have something to jump back to ~ alternative mode
> Then maybe higher latency thanks to DynamicODT has to be outweight, but for now ~ it's fighting against the PCB and trace design
> We'll get it, but DR is certainly more annoying
> I'd prefer your great Dimms, and you can get my sensitive snowflakes


From my tests at 3800 this kit did seem to like CkeDrvStr 30. Might be too early to say but that may be helping. The sweet spot for ClkDrvStr at 3800 was 40, but that was with 1T. I've never really ran CsODtDrvStr 30, so I'm a bit in the dark with this one. Just trusting it might help at frequency this high.

I'm struggling with RttPark 7, issues booting. 6 seems to be the highest I can do on this profile. As mentioned earlier I struggle to get off RttWr 1 at this high a frequency. Up to 4400 it doesn't seem to bother much, but above 4400 1 seems to be mandatory for me to get it to boot, let alone boot first time.










Error on 1 very quickly dropping VSOC and VDIMM by one notch. I'll check each one individually now.

This seems to be my main problem right now, trying to balance voltage. Go too low and I introduce VDIMM not being high enough errors, seemingly go higher and begin over current PCB crashes.

I also wonder if reintroducing RttNom could help, but that is another variable and so far the closest I've come to at least a 25 cycle is with it disabled.

At this point I don't think I'd trust a 25 cycle at this frequency lol. Probably need a 25 and an overnight with Karhu.

Edit - Error 1 seemed to be caused by the VDOC drop, it's happy back at 1.15v. At least we've figured out VSOC is going to have to stay at a minimum of 1.15v. 1.6v on VDIMM in testing now, will see how far it gets.


----------



## Veii

Audioboxer said:


> Error on 1 very quickly dropping VSOC


There is no need to touch VSOC 
You are not changing procODT
At least you should be increasing SOC if you drop ClkDrvStr
But in general, there is no need to touch SOC at all ~ you will destabilize only your CPU

What you haven't done till now, is increase cLDO_VDDP
If dimms start to lack voltage, even when i strongly recommend against using this as powering
You have to increase cLDO_VDDP on higher MCLK. That's, well it's fact. Results have shown it up till 2500MCLK
It's the voltage for the IMC, and MCLK belongs to the IMC too. FCLK does not, soo has nothing to do with FCLK.

if you increase VDDP too much, high VDIMM will overpower the dimms ~ but you have to increase it, no way around it
You have a lot of range till at least 1.0v, if not higher
#11 is fine








#1 is sadly both  timings and voltage (increase your tRFC value by 24, and if it doesn't go away, it's not that one & revert it back)
#11 was random access 16mb , that's voltage
but fixed access can very well be a timing problem

You should check if this #1 disappears on one step lower MCLK
If it was tCKE's fault or not
It might as well be your tRRD_, and tWTR_ (at the very end)


----------



## ManniX-ITA

@Veii

I'm testing the B550 Unify-X A45 modded with AGESA 1.2.0.5...

Can do stuff with memory that were just impossible before.
Like finally having RTT 7-3-3 stable.
Like flat 3800 C14 working (till the DIMM overheats eheh, but now takes 3 x TM5 cycles to get #13 instead of failing at 1st cycle with #2/10).
Or same 3800 C14 T1 profile with setup timing profile and tRCDRD 15 working up to 4000 MHz.
Till 1.2.0.3 my kit at 4000 CL14 wouldn't even boot into Windows and tRCDRD was limited to 16.

Boost strategy is completely different... much more conservative.
CB23 MT was starting at 4550 MHz now at 4400 MHz. But ends 50 MHz higher... almost same score.
The monero miner runs like hell at 3800 MHz, same as 4000 MHz.
This BIOS is not friendly with high FCLK sadly.

The whole 2nd CCD is now a B class citizen... from 40 to 90 MHz less boost.
I've managed to get the good cores on the 1st CCD almost on par.
But in general the boost is lower, around 10 to 40 MHz.
With the exception of the very good Core 6 which was boosting like hell and now is going 60 MHz slower.
That's because it was already at -28 before.
Now the VID is much lower in general and on this one it's 120mV the delta.

All the cores are running lower, around 50 to 70mV on average.
But I really wonder if these reported values are for real.

I managed to get the same speed and the same scores (more or less).
But the power consumption is slightly higher and temperatures as well...

Anyway, wanted to test mainly the VDDG per CCD.
Still have to test thoroughly but I have the feeling either it doesn't work or it doesn't help...

And I have audio crackling now...

The CPU Core VID limited to 1.425V is a non issue; the VIDs (apparently) doesn't even go closer to 1.4V like before.
It doesn't limit the single die Core VID; adding a 0.1V offset on vCore brings back things to normal.
The CPU Core Voltage goes again up to 1.5-1.52V instead of 1.45-1.47V and the VIDs are again unrestricted.


----------



## Audioboxer

Veii said:


> There is no need to touch VSOC
> You are not changing procODT
> At least you should be increasing SOC if you drop ClkDrvStr
> But in general, there is no need to touch SOC at all ~ you will destabilize only your CPU
> 
> What you haven't done till now, is increase cLDO_VDDP
> If dimms start to lack voltage, even when i strongly recommend against using this as powering
> You have to increase cLDO_VDDP on higher MCLK. That's, well it's fact. Results have showed it
> It's the voltage for the IMC, and MCLK belongs to the IMC too. FCLK does not, soo has nothing to do with FCLK.
> 
> if you increase VDDP too much, high VDIMM will overpower the dimms ~ but you have to increase it, no way around it
> You have a lot of range till at least 1.0v, if not higher
> #11 is fine
> 
> 
> 
> 
> 
> 
> 
> 
> #1 is sadly both  timings and voltage (increase your tRFC value by 24, and if it doesn't go away, it's not that one & revert it back)
> #11 was random access 16mb , that's voltage
> but fixed access can very well be a timing problem
> 
> You should check if this #1 disappears on one step lower MCLK
> If it was tCKE's fault or not
> It might as well be your tRRD_, and tWTR_ (at the very end)


Thanks for the tips with VSOC, I won't touch it again. And yeah, probably time I have a look at VDDP again. I think my concern with touching VDDP was thinking if error 7 ends up being over current more voltage could make things even worse lol.

I'm also going to take a look at that error 10 which followed 7 at 20 cycles. I've left tWRRD on AUTO till now but presumably it could be struggling at 2? Will try 3. I guess tRDWR could be tried at 10 as well.


----------



## Veii

Audioboxer said:


> I'm also going to take a look at that error 10 which followed 7 at 20 cycles. I've left tWRRD on AUTO till now but presumably it could be struggling at 2? Will try 3. I guess tRDWR could be tried at 10 as well.


It shouldn't struggle
You can leave them on Auto , but you can try with tWRRD only

#10 is "maaybe timings" , but more towards "maaybe, likely voltage"















~ = maybe, ? = question
X = surely
! = guaranteed
/ = guaranteed not
Voltage on #10 is surely, but maybe only ?
Timings on #10 is maaybe , but rather not ?

Unclear 















But this is clear , it's voltage related ~ voltage/powering, same thing


----------



## Audioboxer

Veii said:


> It shouldn't struggle
> You can leave them on Auto , but you can try with tWRRD only
> 
> #10 is "maaybe timings" , but more towards "maaybe, likely voltage"
> View attachment 2545124
> View attachment 2545125
> 
> ~ = maybe, ? = question
> X = surely
> ! = guaranteed
> Voltage on #10 is surely, but maybe only ?
> Timings on #10 is maaybe , but rather not ?
> 
> Unclear
> 
> 
> 
> 
> 
> 
> 
> 
> But this is clear , it's voltage related ~ voltage/powering, same thing


Yes, tRDWR is on AUTO as well, so BIOS is picking 9 for it like 2 for tWRRD.

I'm going to leave VSOC and VDIMM where they were during that 20 cycle. I'll start slowly playing with VDDP in 0.05v increments. Might take time for all these runs but will be interesting to see if most make it near 20 cycles again. I truly think it's best to take it in such a small increment due to how fine this balancing act seems to be.

ClkDrvStr 30 is the only thing I'm concerned about but I won't change it for now on the basis that the furthest I've got is to 20 cycles with that. Did you recommend 30 because CkeDrvStr was also going up, or would 40/20/30/30 be possible to try?


----------



## hazium233

Veii said:


> These values i can look up (calculation formula's)
> If we have the name, they make sense
> 
> It's odd that my board fully refuses to post tPHYRDL 30, at all
> And hardcaps that way
> It's also odd that when i select 4966, it loads own strange timings and procODT ~ which all make no sense and can't boot
> 
> 
> Spoiler: Data
> 
> 
> 
> 
> 
> 
> Spoiler: RxDatChnDly
> 
> 
> 
> 
> View attachment 2545068
> 
> ^ memory training channel delay
> 
> 
> 
> 
> 
> Spoiler: MRL & DFI MRL
> 
> 
> 
> 
> View attachment 2545069
> 
> View attachment 2545070
> 
> View attachment 2545080
> 
> DFI_RdData_EN & _VALID
> View attachment 2545082
> 
> ^ memory training & Clock Gating for UMC
> 
> 
> 
> 
> 
> Spoiler: Vref on DDR4 & LPDDR4
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ^ on DDR4 it's always beyond half. DDR3 was less or equal than half
> Shown is a control and anchor for control, but the work is identical
> 
> 
> Notes & Tutorial
> 
> 
> Spoiler: FIFO Meaning & Illustration ~ just learned
> 
> 
> 
> 
> View attachment 2545089
> 
> 
> 
> Spoiler: Illustration
> 
> 
> 
> 
> View attachment 2545088
> 
> View attachment 2545087
> 
> 
> 
> 
> View attachment 2545090
> 
> Soo hence FIFO's are consistently checked and control operations.
> Hence AMDs PHY controller already supplies and changes DFI-Clock, where both Read latancies and general latencies are set
> Both MP0 and MP1 would only control & delay the time X (in some DWORD value) , till each of the read and write operation on FIFO
> (which is controlling data in and data out ~ before it's spread to cells or to banks or ranks)
> 
> The only potential usecase i can see by purely guessing a new learned thing/controller
> ~ is to either increase it, in matching dynamic MCLK switching (alignment of UMC to DFICLOCK, soo UCLK to MCLK alignment ~ guessing)
> ~ or to delay it (value = 2tCK, two memclk value, transfer time) if memory is unstable between ICs or ranks.
> Soo potentially any usecase for very high voltage, to prevent cells from crashing ~ probably potentially only useful for XOC. But also probably potentially should not be touched at all
> 
> 
> 
> 
> 
> This took time to learn and write, excuse me
> Still out of my head, but i can slowly see / and probably understand why they want to align MCLK and UCLK soo much - or half it
> Instead of running higher MCLK UCLK, than FCLK
> Although documents say, it potentially could work
> 
> Good to know at least, that memory training is fine ~ a lot of thought has been pushed into it
> And very good to know that MSI pretty much supplied a pattern/preset to extend the bios with all the new headers and informations ~ if bios modder would have correct descriptions
> * they can just create new options and put new options in place, as formatting preset already exists. Very comfortable
> 
> Information is slightly jumping between Vermeer and Cezanne, soo also Renoir
> But you can gather most
> Hmmm, in theory somebody could make a fully open bios with full access ~ for memory OC
> In practical theory, it would be possible and nothing preventing it
> 
> But in realistic practical theory, that would require ~somebody~ , to have the same access, have the same time, know more about the bios and start to do bios mods for everything
> Then also sign them
> This practical theory ~ then shows to be less practical reality
> But probably can be a thing~


Thank you, very helpful.

Sadly though I think that even though the DFI MRL Margin, et al are exposed I am not entirely sure they work for my bios. Maybe they work on the Unify, and this is a remnant of MSI bios work on another motherboard. I haven't really tried them extensively, will look again maybe with more sensible values based on above.


----------



## Veii

Audioboxer said:


> ClkDrvStr 30 is the only thing I'm concerned about but I won't change it for now on the basis that the furthest I've got is to 20 cycles with that. Did you recommend 30 because CkeDrvStr was also going up, or would 40/20/30/30 be possible to try?


I had to drop it, because i was getting #11 errors and many many #1's
https://www.overclock.net/threads/o...memory-stability-thread.1628751/post-28936492
[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread and this post


Veii said:


> That's been yesterdays fun ~ bit creepy face, for a creepy experience till the late night
> Many 1's (200), couple zero's, couple 14's, couple 5's
> Lower ClkDrvStr by one, higher VDIMM from 1.44 to 1.5, stronger RTT_NOM as exchange
> Error free.
> Scaling continues on RTT_WR/2


Sadly didn't achieve much today with 3800 but #1's needed a voltage increase, just this destabilized and needed a ClkDrvStr decrease
Then voltage increase needed bit more NOM as i was moving already in the 1.5v range
Now up to 1.56-1.58v for 3800

At least learned something new, guess day wasn't completely useless
Rest well and much success ! 🥱
Step by step~


----------



## PJVol

Veii said:


> You can set CO's (modify) after setting CO's , right ?
> There won't be any stack issue, or requirement to reboot or anything odd ?


Sorry, not sure what you meant here. If you ask, if setting CO from the app override BIOS settings, then yes, just those set from bios values, not the ones in the PBO menu. And there should be no issues as well.


----------



## Audioboxer

@Veii I got these errors at cycle 24~25, it was clean at 23  

Bit stumped what it could be this late on, might try reducing CkeDrvStr. The above has 3 changes from the 20 cycle failure, tWRRD 3, tRDWR 10 and more importantly, a +0.05V to VDDP. No 7's this time, but a 0/13 seemingly out of nowhere and very late on. IIRC I've not faced a 0 or 13 before with this profile.

Maybe I need to think about reintroducing RttNom? I'm going to guess a bump to VDDP as small as it was helped, maybe even just increasing it another 0.05v could help even more, that would be 0.93v. 0/13 seem to imply voltage issues, but likely too much or RttNom needing to be stronger. My ProcODT at 34.3 might be haunting me a little, but it's getting 28/28 consistently and we're really close.

But unless I'm wrong RttNom 7 or 6 might allow CkeDrvStr to stay at 30 as well as be able to handle 1.62-1.65v? It's that or I presume I might have to get ProcODT lower and try and fix tPHYRDL. The 0/13 is just throwing me right now.

Heck, just goes to show how 20 cycles is not enough. I'm even doubting 25 now given how close that was to passing. This is why multiple runs or multiple apps to test memory is a good idea!

I'm quite confident if I can get this stable quite a few of the secondaries will come down, it's just the process of elimination loosening them in case something helps or is needed at 4533.

The amount of hours of testing going into this 😍 It has to be fixable though, surely no way we can get to 20+ cycles and have to abandon! I think the next step, even if it's a total failure as is, is to try and run RttNom 7 and see what kind of errors TM5 throws out.

*edit* - Increased VDDP to 0.93v and now










15/2 in the end cycles. Seems errors are just coming after 1.5~2 hours.


----------



## kim nk

5600x B2 stepping 
2145sus B0










2150sus start








However, there are reviews that the 5600x b2 is still unstable with the 1.2.0.5 BIOS. For example, 3800 clock boot failure is mostly the hole clock, but there are cases where 3866 ~ does not boot. The hole clock existed in b0, but again b2 does not have this improvement at all and it seems rather strange


----------



## Mach3.2

PJVol said:


> Btw, do you (or anyone else) wanna check my simple utility for CO and PBO limits tuning?
> I wrote it, while learning C# and VS at the same time (special thanks to Rusanov), so pls don't be too rude on me for this first experience.
> 
> So far, the only significant limitation is it can't read CO values from BIOS, so I've made it so it keeps user settings in a local storage.
> 
> 
> 
> 
> 
> Debug.7z
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> View attachment 2545010
> 
> Just want to be sure, it works correctly on all Vermeers.


Works fine on my B0 5900X + X570 Tomahawk Wifi (SMU 56.53) setup.

This is excellent, makes it easier to tune CO values and PBO2 limits without constantly rebooting into the BIOS. I wonder why AMD didn't have it in their Ryzen Master tool if it's possible to change those values from within Windows.. 🙃


----------



## Veii

Audioboxer said:


> 15/2 in the end cycles. Seems errors are just coming after 1.5~2 hours.


Poor you, unknown errors


Audioboxer said:


> @Veii I got these errors at cycle 24~25, it was clean at 23
> 
> Bit stumped what it could be this late on, might try reducing CkeDrvStr.


0,13 also are kind of everything. Heat, voltage
Problem is - there are still some that say tRRD_ and tWTR_ are bad
CAD_BUS values should show quite fast, if they are bad
After such time it's only a heat and noise issue. Soo discharge issue

I'd trow all in the bag as "the same issue", and work either on timings or on RTTs
Wouldn't change something that runs over 1h stable ~ as thermal equilibrium still is around 45min. Even for big rads and watercooled dimms
Both make little sense. But either it's tRFC that errors after such long time, or it's something to do with heat and noise.

CAD_BUS should be fine. It only needs changes if you do changes somewhere else, to counter balance.
Or if you have issues at the start
In our state, any little change there does have drastic effects - soo rather do not touch it, unless you try to shift balance slightly
Try tRFC +24 should do it's job. If it's not that, revert and try tRRD_ or tWTR_
And if it's not that , you can revert it and try RTT_NOM

You need cLDO_VDDP scaling upwards, else you'll be limited by MCLK quite fast (i mean you already are)
Soo it introducing errors, should not be ignored. The only errors it can maybe give, is dimm overpowering - when the value is higher. But then you can balance it away with RTT and CAD_BUS
RTT_PARK , mostly hangs together with VDIMM. Change there, will need change in VDIMM (within a range). Soo weaken PARK further can very well request 40mV more VDIMM to reach the same heat and same stability
Same goes for CkDrvStr, weaken there aside from causing issues on procODT , will lower amperage received to dimms. Soo more voltage as balance or stronger PARK - is the balance step.
Stronger Park then will destabilize the PCB fast, soo VDIMM has to fall ~ but VDIMM being lower is no option, as that limits minimum timings 
Lower heat and stability on High VDIMM is the target. So you can run absurd timings and daily high voltage


PJVol said:


> Sorry, not sure what you meant here. If you ask, if setting CO from the app override BIOS settings, then yes, just those set from bios values, not the ones in the PBO menu. And there should be no issues as well.


I ment, that once you erase CO settings, and set your own
Then on reboot the tool loads what you set. Soo if you modify, it should not cause to bug out but replace the values ?
You don't have to erase again and load new ones.
It depends how it loads the CO's, if code would swap them , or cause a bug where they stack
Because if it would cause no issues - you wouldn't have any need to "erase" them at all and it will just replace bios values

Oh also the SOC limit and FIT load behavior change "feature" is a thing
It limits it down to 1.2v and scales down by FIT threshold (like it does on max-voltage) - if you use the tools method
I needed to erase, reboot, then send MSG_ColdResetEntry via asus tool 1007
And it still had the FIT limit in there
Loading my old bios profile from far back 1200 something - replaced something and it's back to normal

powercfg -setacvalueindex scheme_current sub_processor 5d76a2ca-e8c0-402f-a133-2158492d58ad 1
powercfg -setactive scheme_current
~ boost enforce








and Idle
powercfg -setacvalueindex scheme_current sub_processor 5d76a2ca-e8c0-402f-a133-2158492d58ad 0









Usually SOC peaks to near 1.3080 ~ but i think something to take a look at, is SOC "allowed to be set" voltage
your tool forced it down to 1.2v peak, and max SOC voltage "loaded" was always bellow that - hardcapped. Independent if i run 1.25 or higher
Something is odd.

Another thing that could be odd,
Do you want to try my 2100 bios profile on your asrock board ?
i know it changes more things than current bios allows to be shown, but ~ could lead to some interesting results.
Maybe if you can replicate what i see


----------



## Audioboxer

Veii said:


> Poor you, unknown errors
> 
> 0,13 also are kind of everything. Heat, voltage
> Problem is - there are still some that say tRRD_ and tWTR_ are bad
> CAD_BUS values should show quite fast, if they are bad
> After such time it's only a heat and noise issue. Soo discharge issue
> 
> I'd trow all in the bag as "the same issue", and work either on timings or on RTTs
> Wouldn't change something that runs over 1h stable ~ as thermal equilibrium still is around 45min. Even for big rads and watercooled dimms
> Both make little sense. But either it's tRFC that errors after such long time, or it's something to do with heat and noise.
> 
> CAD_BUS should be fine. It only needs changes if you do changes somewhere else, to counter balance.
> Or if you have issues at the start
> In our state, any little change there does have drastic effects - soo rather do not touch it, unless you try to shift balance slightly
> Try tRFC +24 should do it's job. If it's not that, revert and try tRRD_ or tWTR_
> And if it's not that , you can revert it and try RTT_NOM
> 
> You need cLDO_VDDP scaling upwards, else you'll be limited by MCLK quite fast (i mean you already are)
> Soo it introducing errors, should not be ignored. The only errors it can maybe give, is dimm overpowering - when the value is higher. But then you can balance it away with RTT and CAD_BUS
> RTT_PARK , mostly hangs together with VDIMM. Change there, will need change in VDIMM (within a range). Soo weaken PARK further can very well request 40mV more VDIMM to reach the same heat and same stability
> Same goes for CkDrvStr, weaken there aside from causing issues on procODT , will lower amperage received to dimms. Soo more voltage as balance or stronger PARK - is the balance step.
> Stronger Park then will destabilize the PCB fast, soo VDIMM has to fall ~ but VDIMM being lower is no option, as that limits minimum timings
> Lower heat and stability on High VDIMM is the target. So you can run absurd timings and daily high voltage
> 
> I ment, that once you erase CO settings, and set your own
> Then on reboot the tool loads what you set. Soo if you modify, it should not cause to bug out but replace the values ?
> You don't have to erase again and load new ones.
> It depends how it loads the CO's, if code would swap them , or cause a bug where they stack
> Because if it would cause no issues - you wouldn't have any need to "erase" them at all and it will just replace bios values


Good advice, I was thinking to myself getting different errors at around the same time 20+ cycles was both weird and a case of can it be the case there are multiple issues that only show up after hours???

tRFC is one I normally wouldn't have thought of here given I run 117ns at 1.55v at 3800. But I'm guessing at high frequency mixed with drastically different Rtts and DrvStr it can be the case tRFC needs to be thought about differently and not just "it scales with VDIMM"? Because in terms of my DIMM temps you've seen I'm at like 30 degrees.

But that then ties into what I presume is heat and noise discharge also behaving differently at these timings and settings.

I will try looking at tRFC first then. The increase to VDDP while it was only 0.05v from 0.92v to 0.925v seems to have cleared up error 7s. Whether going to 0.93v and beyond will also help I'm unsure. But sticking with 0.925v for now seems like the best option if the 7s don't come back whilst I test tRFC.

Will then try RttNom before looking at some of those other secondary timings and finally DrvStrs again.

There has to be something that will help given how long I'm holding out multiple times now before the first error!


----------



## Audioboxer

Ah hah, first error I've received well before we get to around 20+ cycles. Only change here from before is increasing tRFC.










tRDWR and tWRRD have been manually set by me now to 10/3, I wonder if I should put them back on AUTO? Thing is, this is the first time I've seen an error 5.

@Veii Any tips? I'm guessing tRFC might have brought this out, but understanding what to change to help it has me a bit stumped.


----------



## Veii

Audioboxer said:


> Ah hah, first error I've received well before we get to around 20+ cycles. Only change here from before is increasing tRFC.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRDWR and tWRRD have been manually set by me now to 10/3, I wonder if I should put them back on AUTO? Thing is, this is the first time I've seen an error 5.
> 
> @Veii Any tips? I'm guessing tRFC might have brought this out, but understanding what to change to help it has me a bit stumped.


I'm slightly surprised too
This is against anta's explanation on tRFC and it should've been correct
can you check for me what happens if you run 336-250-154, tRFC ?

The only explanation to this (i can imagine) would be,
that tRFC refresh report is faster than other timings can error out 
tRFC by itself (high value) should not cause issues
odd value might, but if above causes the same issues ~ something is wrong with your timings


----------



## Veii

@ENTERPRISE happens slightly too often ^^'
post #16309 above , can't edit submit or paste anything.
Works on a new post, but creates spam. Something in punctuation is causing an issue. Can't understand but have it for now at least 6 times, if not more
Also since the change of the compression format (can't see the change anymore)
Every upload has a big space above and under the picture. Happens on downscaling
Was hoping it would be noticed ~ but now that i'm bothering you with bugs, guess i can include that one too








How it has to look















How it really looks
Just wastes thread space and looks odd, with these ghost-linebreaks
=================
@Audioboxer [Part 2/2]







Usual known, old, average ~ wanted to make sure it's still stable
But it's not even a rounding error for your value


----------



## Audioboxer

Veii said:


> I'm slightly surprised too
> This is against anta's explanation on tRFC and it should've been correct
> can you check for me what happens if you run 336-250-154, tRFC ?
> 
> The only explanation to this (i can imagine) would be,
> that tRFC refresh report is faster than other timings can error out
> tRFC by itself (high value) should not cause issues
> odd value might, but if above causes the same issues ~ something is wrong with your timings


Well, a tRFC value of 312 (137ns) is currently on cycle 17 so far without an error. Will report on how it manages. Only other change here is I put tRDWR and tWRRD back on auto. This shifts them to 9 and 2 from my manually selected 10 and 3.

I probably should never have taken them off auto, it's just 10/3 was my first cycle to get to 20+ and I guess I thought best just leave them at that instead of changing anything.


----------



## Audioboxer

Okay, who cast a curse on me?  A single error on 3 on the 24th cycle. Yes, 24. I just sat and watched it in real time.



















Sorry for phone picture, I'm changing my keyboard switches and doing lubing on main PC so keyboard unplugged.

@Veii With an error 3 on these settings at cycle 24 what do I even do? lol... Time to look at tWTRS? If so, change it to what? 6?

edit - Just noticed I uploaded a picture without the error, wrong one, but it doesn't matter it came shortly after that on cycle 24.


----------



## FantasmaN3D

PJVol said:


> idk, I thought main changes in PSP FW related to some recently found vulnerabilities and B2 revision support in SMU 56.65, I mean this annoying VID limitation. Can't say the performance decrease overall is a concern for majority, but for us, enthusiasts, its definitely a regress.
> The boosting isn't change much, apart from the cases where VID limit is involved.
> 
> Btw, do you (or anyone else) wanna check my simple utility for CO and PBO limits tuning?
> I wrote it, while learning C# and VS at the same time (special thanks to Rusanov), so pls don't be too rude on me for this first experience.
> 
> So far, the only significant limitation is it can't read CO values from BIOS, so I've made it so it keeps user settings in a local storage.
> 
> 
> 
> 
> 
> Debug.7z
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> View attachment 2545010
> 
> Just want to be sure, it works correctly on all Vermeers.
> 
> TRFC default
> View attachment 2545011


Hi, I am new here (but not unknown to oc world), I just wanted to give a bit of feedback about your small app. First of all, I think it is amazing to be able to change the CO values "on the fly" to test stability. It is certainly a lot faster than going to the bios every time to change them. It is also great to take a look at the changes in voltage/freq. with every CO step.

I just tested it with a 5900X+MSI B550 Gaming Edge and it works fine. I can change PPT/TDC/EDC/FIT (I got only a message saying something about decimal numbers, which I do not use, but it applies the settings anyway) with no problems. About the temp. limit, it cannot be changed over the standard 90°C limit.

About maximum frequency, I could change it also "on the fly" if the value that I set is within bios maximum limits. For example, with Freq. offset in bios of Auto (+0Mhz), the maximum I can apply is 4950Mhz (putting a higher number does effectively nothing); if I put +200Mhz in bios, then I can change it up to 5150Mhz. I can change it up and down if I am within those margins. What I found strange is that if you limit the frequency to something lower than what the cores can pull off (for example limiting to 4300Mhz when the cores can do 4500Mhz), the monitoring of the CCLK_LIMIT from the ZenPTMonitor bugs out and shows something in the range of 5.1xx Ghz, which, of course, is not real. I measured the performance with CB R23 and the real speed was what I limited with the app.

I used the CO settings with the CO values set at 0 in bios. I was not sure if they could affect the working conditions of the PBO2 Tuner. Resetting and then applying the COs in the app worked with no problems. The only thing that I observed is that, when a restart was forced due to instabilities, the app remembers the latest CO settings. However, in my case they were not really applied. I just pressed Reset, restarted the system and put the latest CO values in PBO2 Tuner when entering windows again.

So, in general, a very very useful tool. I think that would be a huge contribution to the oc community, or at least, I was looking for something like this for a long time.

Greetings


----------



## Veii

Audioboxer said:


> edit - Just noticed I uploaded a picture without the error, wrong one, but it doesn't matter it came shortly after that on cycle 24.


One change
Does your board allow BGS mode ?
You might want to give that a try
I mean later stuff can be lowered, soo there is not a big deal in running higher timings

Timings written and explained
Will interest @hazium233








On stock tPHY gaps are 2 and 4 , not 5
problem with JEDEC tCCD_ is, that i am not sure if it reads programmed value , which varries by XMP or it generates it
RDRD/WRWR SC values would point to generation, but hence we all always run them at 1 ~ i think it's just AL (added latency) part, not much more

tFAW by itself has two more timings that manage tFAW
But the interesting is tWTR_S & RRD_S which change up to BGS behavior & that on AMD tRC will either elapse and has to elapse, OR it can be tiny, and will like tRFC keep on triggering and looping = work as an "auto refresh command"
This likely is part of the reason why you can run tRC = tRAS+1 , and i've tried to run something stupid like 15-23-15-15-30-22 (worked)
tRC can be bellow tRAS and act as looping auto refresh, but i'm not sure if this makes "any sense" to use it that way, at all 

DRAM PL , DRAM CL seem to be Vendor timings ~ there is zero about them (unsure)
But tRCD nLatency add, is something else 

Bank Ban'ing then is a whole new can of worms, but also pre-configured and readable out on MemTweakIt
MemTweakIt_12-22.exe in case it was missed, vendor independent

EDIT:
tSTAG is also interesting, although preconfigured and no access without a bios mod
It pretty much controls if 1X, 2X, 4X, or Dynamic Mode should be enabled ~ together with tRC_PAGE
~ dimm thermal dependent downclock-mode ala tRFC 2/4 mode
This is what it loads for me ~ might help about the read&write latencys/delays


----------



## Audioboxer

Veii said:


> One change
> Does your board allow BGS mode ?
> You might want to give that a try
> I mean later stuff can be lowered, soo there is not a big deal in running higher timings
> 
> Timings written and explained
> Will interest @hazium233
> View attachment 2545292
> 
> On stock tPHY gaps are 2 and 4 , not 5
> problem with JEDEC tCCD_ is, that i am not sure if it reads programmed value , which varries by XMP or it generates it
> RDRD/WRWR SC values would point to generation, but hence we all always run them at 1 ~ i think it's just AL (added latency) part, not much more
> 
> tFAW by itself has two more timings that manage tFAW
> But the interesting is tWTR_S & RRD_S which change up to BGS behavior & that on AMD tRC will either elapse and has to elapse, OR it can be tiny, and will like tRFC keep on triggering and looping = work as an "auto refresh command"
> This likely is part of the reason why you can run tRC = tRAS+1 , and i've tried to run something stupid like 15-23-15-15-30-22 (worked)
> tRC can be bellow tRAS and act as looping auto refresh, but i'm not sure if this makes "any sense" to use it that way, at all
> 
> DRAM PL , DRAM CL seem to be Vendor timings ~ there is zero about them (unsure)
> But tRCD nLatency add, is something else
> 
> Bank Ban'ing then is a whole new can of worms, but also pre-configured and readable out on MemTweakIt
> MemTweakIt_12-22.exe in case it was missed, vendor independent


Yes it does. I can try that. As this lubing switches process is time consuming I've plugged in a temp second keyboard just to get into BIOS to try tWTRS at 6 and I'll see how this run goes.

With these errors as late as they are though I think I'll need a 50 cycle to be confident once a 25 passes. I guess whoever came up with 25 cycles rather than 20 is a genius because most of my errors are from 21-24 lmao.


----------



## Veii

Audioboxer said:


> Yes it does. I can try that. As this lubing switches process is time consuming I've plugged in a temp second keyboard just to get into BIOS to try tWTRS at 6 and I'll see how this run goes.


5-14 on tWTR_


Audioboxer said:


> I guess whoever came up with 25 cycles rather than 20 is a genius because most of my errors are from 21-24 lmao.


I didn't like 20 , it needed more to catch tRFC errors 
But usually it shouldn't be timings at this point. Only tRFC can cause issues that late.
Usually at and bellow 20 is timings dependent, but DR needs a lot of time ~ soo maybe DR shouldn't be timings dependent after 90min (exception tRFC)


----------



## hazium233

Veii said:


> DRAM PL , DRAM CL seem to be Vendor timings ~ there is zero about them (unsure)
> But tRCD nLatency add, is something else


phys latency?

I know in classic activate then read or write, timing is like:

activate - wait trcd - read/write - cl / cwl time...

But can also just issue read/write at next valid space after activate with AL

activate - wait 1 (or 2 ... next valid space) - read/write - wait AL + CL (or CWL)...

Where AL = 0, CL-1 (or CL-2 for GDM)

So one or other could be like AL here?

Ha, but looking at all these sheets makes my head hurt.

***

edit: scratch that, PL is apparently "parity latency," at least in some references.

but the tRCDnLatAdd looks a lot like AL because AMD's formula for read and write latency is practically the same otherwise as what is in the Micron sheets for Read and Write latency.

***

...


_SCL is even listed as surrogate for CCDL, but strictly speaking XMP doesn't actually have this programmed, no? I thought that is is usually whim of motherboard vendor for XMP button behavior. It is in SPD bins, but doesn't seem to be inherited normally as some other subtimings.

For instance normal G.Skill 3200c14 the top SPD is 2133 and has CCDL 6. But if you had Flare X it has SPD 2400 with CCDL 7... but both still set _SCL 5t when load XMP. Well they do for me anyway on my motherboard, iirc

* edit2... actually that was the wrong example, it was the Micron that had 2666 SPD and CCDL 7, but the motherboard still set _SCL 5.


----------



## Audioboxer

Veii said:


> 5-14 on tWTR_
> 
> I didn't like 20 , it needed more to catch tRFC errors
> But usually it shouldn't be timings at this point. Only tRFC can cause issues that late.
> Usually at and bellow 20 is timings dependent, but DR needs a lot of time ~ soo maybe DR shouldn't be timings dependent after 90min (exception tRFC)












Increase tRRDS, tRRDL and tWTRS... get an error within 4 minutes lol










Try decreasing tWR? I mean, it was holding out at 14 with tighter tRRDx and tWTRS and now this  

Thought I'd slacken them all off when you mentioned timings can be dropped later.


----------



## Audioboxer

Changing all 3 of those at once has definitely mucked something, getting errors early now that I haven't been getting before. Going to go back to the profile that made it to 24 cycles and rethink where to go next. Maybe BGS enabled or reintroduce RttNom just to see what impact it has.










That didn't go well  Complaining about tWR/voltage again with 9.

Will try with 1.62v with the reintroducing of RttNom.


----------



## andremoreira6215

Hey guys hope everyone was fine. What you guys do to not have whea 19 errors? My kit it's a b die kit 3600 cl16 and I got 3800cl14 without errors on TM5 and on hci, but after 3800MHz system was stable but I got whea 19 on event viewer. How I can get it past 3800 without whea error? The only way its to buy a new premium mobo? I have a b450 tomahawk max II and I don't have any problems with pbo + Co in my system or any other problems the only thing it's whea errors. Can anyone tell me what's the trick?


----------



## Audioboxer

@Veii We finally done it! 

And what did it take? Reducing VDIMM to 1.6v. I decided to try that as I increased from 1.61v to 1.62v and all hell broke loose, making me think my main issue was simply VDIMM. Maybe tRFC as well, but it was increased from 280 earlier.

It seems this combination of Proc/Rtts and DrvStr can't handle above 1.6v. Might end up being a shortcoming of these settings, but that might be the price this kit needs to pay to try and stabilise 4533. Just means no higher VDIMM to try and help with something like tCL15 or above 4600 if using the same Proc/Rtt/DrvStr.

Does that make sense to you? It could just have been too much VDIMM?

Now the real fun begins, retesting this profile, again, before figuring out what secondaries might be able to come down. You're damn right I will daily this if it's properly stable, all this time put into it, the bandwidth will be nice even with latency still marginally trailing 3800.

*edit *- Disabled/1/6 at least posts on my 3800 profile










Maybe a tip for anyone to try if they can post something like this first before trying to push frequency. It seems to me at least on DR, a configuration like this might be necessary to post high frequencies.


----------



## Veii

Audioboxer said:


> Does that make sense to you? It could just have been too much VDIMM?
> 
> Now the real fun begins, retesting this profile, again, before figuring out what secondaries might be able to come down. You're damn right I will daily this if it's properly stable, all this time put into it, the bandwidth will be nice even with latency still marginally trailing 3800.
> 
> *edit *- Disabled/1/6 at least posts on my 3800 profile


My DR dimms capped at 1.6v too, sadly ~ weak PCB
I expected yours to be better
But then you still can drop PARK once more - and potentially get a bit more VDIMM out
Good to know , success !


----------



## Audioboxer

Veii said:


> My DR dimms capped at 1.6v too, sadly ~ weak PCB
> I expected yours to be better
> But then you still can drop PARK once more - and potentially get a bit more VDIMM out
> Good to know , success !


I've ran up to 1.65v at more traditional Rtts, like 7/3/3 or 6/3/3. Above that I was getting issues with crashes. Above 4400 I can't boot 7/3/3 or 6/3/3, simply wants RttWr 1.

4600 looks to be out of the question anyway. I know I said that about going above 4400 but I've only booted 4600 once and it was a mess to get into it lol. So if 1.6v achieves 4533CL16 I'd say that's a good result! I might now test 1.59v just to see.

4533CL15 is out of the question at 1.6v, I'd estimate it likely needs 1.65v+ to even stand a chance. Even then, going on the latency calculation I believe 4533CL15 would in theory take me lower than 3800CL13 so it's just very unlikely.


----------



## Audioboxer

@Veii Is this where we find out I was simply pumping far too much VDIMM into the memory versus what it actually needs for 4533CL16? lol....


----------



## andremoreira6215

andremoreira6215 said:


> Hey guys hope everyone was fine. What you guys do to not have whea 19 errors? My kit it's a b die kit 3600 cl16 and I got 3800cl14 without errors on TM5 and on hci, but after 3800MHz system was stable but I got whea 19 on event viewer. How I can get it past 3800 without whea error? The only way its to buy a new premium mobo? I have a b450 tomahawk max II and I don't have any problems with pbo + Co in my system or any other problems the only thing it's whea errors. Can anyone tell me what's the trick?


@Veii @Audioboxer can you give a little help on this?


----------



## Audioboxer

andremoreira6215 said:


> @Veii @Audioboxer can you give a little help on this?


Getting above 1900FCLK without WHEA is next to impossible, very few people will manage it. Having an AMD G chip seems to increase the chances you can exponentially because the G chips have better internal memory controllers.

If you are WHEA free just stay there and run 3800. Or try what I'm doing and stay at 1900 and push frequency lol. Just keep in mind running out of sync hurts memory latency.










@Veii Dropping down to 1.55v needs ClkDrvStr to go back up to 40 to boot clean, but you'd probably expect this. As VDIMM comes down, ClkDrvStr might need to go back up. Leaving it at 30 ends up with some F9 - reboot - Boot into Windows. As in, 2nd time around. ClkDrvStr 40 cleans that up to always first time post.

Guess I'll let 1.55v have a go!


----------



## Veii

Audioboxer said:


> Above 4400 I can't boot 7/3/3 or 6/3/3, simply wants RttWr 1.


733 with ClkDrvStr 120 maybe ?



Audioboxer said:


> 4600 looks to be out of the question anyway. I know I said that about going above 4400 but I've only booted 4600 once and it was a mess to get into it lol.


well you still have 2 goals in order to reach goal 3
redo VDDG & SOC - soo you can run 30ohm procODT at your 1:1 ratio with same powering

Stresstest that, and then stresstest again 4533 with 30ohm procODT and the new voltages
will need a lot of benchmarking and scores comparing
Timespy, geekbench 3 & 5, Aida64, Corona benchmark 

Then try 3600 , on WR = Hi-Z, Park /7 


Audioboxer said:


> Guess I'll let 1.55v have a go!


You can once try to push cLDO_VDDP to 1v and see if anything changes
But your target still is procODT 30 or at least 32, likely 30


----------



## Audioboxer

Veii said:


> 733 with ClkDrvStr 120 maybe ?
> 
> 
> well you still have 2 goals in order to reach goal 3
> redo VDDG & SOC - soo you can run 30ohm procODT at your 1:1 ratio with same powering
> 
> Stresstest that, and then stresstest again 4533 with 30ohm procODT and the new voltages
> will need a lot of benchmarking and scores comparing
> Timespy, geekbench 3 & 5, Aida64, Corona benchmark
> 
> Then try 3600 , on WR = Hi-Z, Park /7
> 
> You can once try to push cLDO_VDDP to 1v and see if anything changes
> But your target still is procODT 30 or at least 32, likely 30


I would never have thought it was OK to run ClkDrvStr that high lol. I'll try it!

Why is it soo crucial to run ProcODT that low if VDIMM can be brought down? I'll give it a go, just asking for knowledge sake. I understand with higher voltages trying to reduce ProcODT.

But if I can manage it, it will be good. IIRC I don't have tPHYRDL issues on 3800CL13 with ProcODT even as low as 28.2. I just kind of stuck to 34.3. So would it be best then to try and run 3800CL13 at 30? I'll definitely run it through a stability test.


----------



## Veii

Audioboxer said:


> Why is it soo crucial to run ProcODT that low if VDIMM can be brought down? I'll give it a go, just asking for knowledge sake. I understand with higher voltages trying to reduce ProcODT.


You will have issues posting higher MCLK with high procODT


----------



## Veii

Audioboxer said:


> But if I can manage it, it will be good.


The interesting part, likely is figuring out if AMD "forgot" to do straps beyond 3600MT/s for Hi-Z - or ASRock "forgot" it
One of both , and you seem to be starting to get familiar ~ with RTTs, slightly


----------



## Audioboxer

Veii said:


> The interesting part, likely is figuring out if AMD "forgot" to do straps beyond 3600MT/s for Hi-Z - or ASRock "forgot" it
> One of both , and you seem to be starting to get familiar ~ with RTTs, slightly


Yeah I'm excited to try some more things now, first will be your HiZ request.

But TM5 is still running error free at 1.55v at the moment lol. Don't want to stop it.


----------



## ManniX-ITA

Audioboxer said:


> We finally done it!


Nice achievement!
By the way I've tried the same as we have same config and my kit doesn't want to boot anything above 4266 MHz...
You got a lucky bin indeed.


----------



## Audioboxer

ManniX-ITA said:


> Nice achievement!
> By the way I've tried the same as we have same config and my kit doesn't want to boot anything above 4266 MHz...
> You got a lucky bin indeed.


Maybe not so lucky, seems like a false alarm










So TM5 has no problem running for hours but Karhu be like, give me 7 minutes 

No more time for testing just now but my initial thought is Karhu hits the CPU harder and maybe the IMC can't handle this as well as a moderate to high CPU load. I'll test OCCT tomorrow as well.

*edit* - I knew something weird was up [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread I ran Karhu a day ago and lasted 1 hour 40 odd minutes with basically the same timings. Only differences were VDDP is a bit higher now, VDIMM is at 1.6v, CkeDrvStr at 30 and ClkDrvStr is at 30. Hmmm, Karhu could be more sensitive to ClkDrvStr, to go from 1 hour 40+ minutes to 7 minutes is... lol. Will have to investigate. Might be worth trying to drop CkeDrvStr back down to 24 as well. It really looks like most of the TM5 failures were coming from running above 1.6v.


----------



## PJVol

Veii said:


> Usually SOC peaks to near 1.3080 ~ but i think something to take a look at, is SOC "allowed to be set" voltage
> your tool forced it down to 1.2v peak, and max SOC voltage "loaded" was always bellow that - hardcapped. Independent if i run 1.25 or higher
> Something is odd.


Are you talking about MAX_SOC_VOLTAGE entry? If you are, "tool forced it down to 1.2v peak" ? Could you be more clear, what preceded this?
I tried changing CO and limits and max_sov_voltage were always peaking at ~ 1.29V (set to 1.1V in BIOS)



Veii said:


> Another thing that could be odd,
> Do you want to try my 2100 bios profile on your asrock board ?
> i know it changes more things than current bios allows to be shown, but ~ could lead to some interesting results.
> Maybe if you can replicate what i see


Lol, after reading this ^^ I somehow am not surprised about that SOC voltage "issues". Just I always forget about the stunningly unique sample you own )
Of course i'd try (if you assure me there won't be any unwanted and permanent changes in SPI flash mem )
-----------------------------
And, btw,
*@FantasmaN3D, 
@Mach3.2 *
many thanks guys for the feedback, much appreciated!



Veii said:


> Then on reboot the tool loads what you set. Soo if you modify, it should not cause to bug out but replace the values ?





FantasmaN3D said:


> The only thing that I observed is that, when a restart was forced due to instabilities, the app remembers the latest CO settings. However, in my case they were not really applied


The app doesn't load autosaved values to the CPU on startup, so after a sudden reboot, the actual settings will be those you set in the BIOS.
So you're suggesting applying the CO settings at startup automatically?


----------



## FantasmaN3D

PJVol said:


> The app doesn't load autosaved values to the CPU on startup, so after a sudden reboot, the actual settings will be those you set in the BIOS.
> So you're suggesting applying the CO settings at startup automatically?


In my opinion, I would not do that, as if very aggressive CO values are set, they may reboot the system every time they are automatically applied. I would leave it as "foolproof" as possible and I think that the current approach (not to apply the last settings) is fine. However, when you open the program and you see CO values that cannot be applied without pressing "reset" and putting the values again manually, it can be confusing as you, as user, are not sure if the values are applied in the first place or not.

A possible idea to circumvent this would be to output a text/log file with the last applied settings every time a new set of CO values are applied so, after a restart or after closing the program, they are readily accessible (with the current approach I was making screenshots before resetting the CO to remember which values were there so it would be even easier to get access to them); while forcing a reset to all CO values to 0 every time the program is opened. Then, the user knows for sure that no CO values are applied and that he/she must type them in. Maybe a hint in the program telling the name of the file where the last known settings are stored would be more than enough for most people.

Of course, these are just suggestions, for me it is already functional and I thank you for that.

Greetings


----------



## ManniX-ITA

Audioboxer said:


> Karhu hits the CPU harder and maybe the IMC can't handle this


Did you disable CPU Cache in Advanced?

I would also try with a small bump in VSOC and/or a stronger SOC LLC.


----------



## Audioboxer

ManniX-ITA said:


> Did you disable CPU Cache in Advanced?
> 
> I would also try with a small bump in VSOC and/or a stronger SOC LLC.


No, I'll try disabling CPU cache first. I'll look at VSOC as well and then also the DrvStrs. Just goes to show what looks stable in one app might not be in another! There is no doubt though Karhu hits the CPU harder than TM5.

*edit* - Went with a single notch bump to VSOC first










Disabling the cache makes Karhu go super slow lol, it's weird. Would rather play around with cache enabled for a bit (above is enabled).

Still convinced it's to do with the CPU/IMC now, it does make sense running this frequency would be harder on the CPU than 3800. Just surprised at how Karhu seems to be doing a much better job than TM5 in this instance.

Fixable? I hope so! Couldn't care less if 50 cycles of TM5 pass, if Karhu is failing we ain't stable.


----------



## TMavica

Everytime I stuck at cycle 19 in TM5 test, Windows 11


----------



## Guzmanus

After a long and arduous road i managed to get what I think is the most i can get from my memory kit (samsung B-Die). I haven't tested it still for long-term (2 TM5 cycles and 200% of MemTest coverage) but i'll do that once i settle on the final settings.

But I want to ask you experienced guys if you see any timing that could be lowered. Some things about the settings:

-VDIMM is low for Samsung B-Dies because for some reason my motherboard sensor reads 0.06V higher than what I set on the BIOS (which is the setting that ZenTimings shows). I have not dared to double check with a multimeter the correcto voltage, as my setup is in a very-crammed ITX case and I could cause quite a mess, and I don't want to risk pushing 1.56V just in case. *Anybody has gotten the same problem with a gigabyte board and knows if I should trust the BIOS setting or the rensor reading?*
-1866FCLK is the maximum i'm able to get. I've tried and tried pushing it past 1900 and even though I manage to boot even at 1966, it is just a mess of WHEA errors and bluescreens.* Any tips on how may I be able to push FCLK higher?*
-With my kit i've been able to run at 4200c18, but of course decoupling MCLK and FCLK. I may try pushing it higher once I find a 3733 setting that i'm happy with and i get bored of not overclocking.










Thank you very much!


----------



## Veii

PJVol said:


> Are you talking about MAX_SOC_VOLTAGE entry? If you are, "tool forced it down to 1.2v peak" ? Could you be more clear, what preceded this?
> I tried changing CO and limits and max_sov_voltage were always peaking at ~ 1.29V (set to 1.1V in BIOS)


Not confident, because usually SOC or EDC throttle was clearly visible by other means. 
We didn't have the tool, but going with logic, it's the same as maximum vcore limit, sample backed and allowed by FIT
Hence i asked if you ever seen any SOC limiters on the new AGESA. 

I remember Matisse well, they did the same there too. Not only was 1.15v SOC (having side effects) which i'm not sure about the reason or it was wrongly spread fear
But you often had boot locks running beyond 1.1 SOC there.
This time doing with 1.2 wouldn't surprise me at all ~ but it would eliminate any possibility beyond 2033 FCLK , if it would exist.
Being cautious you know ^^' Since the 2nd attempt to FCLK lock us down, i lost trust in AMDs Blob Firmware updates. 


PJVol said:


> Lol, after reading this ^^ I somehow am not surprised about that SOC voltage "issues". Just I always forget about the stunningly unique sample you own )
> Of course i'd try (if you assure me there won't be any unwanted and permanent changes in SPI flash mem )


Potentially AMD CBS stuff from older bioses gets applied , and you likely have to change one DPM level back - as it loads it too high (which it ignores later)
But in general, it shouldn't do anything.

Real patches are pre-microcode loading strings, and modify the microcode before it's loaded
If it misses any patch "strings", then it will fall back to ROMs microcode. Else it won't load ROMs supplied microcode but an own supplied one 
Shouldn't make you issues i think. I see no reason to ~ only thing maybe to worry is high VDIMM , but that's all

Mainly interesting is, if ASRock profiles are board independent compatible ~ or i'd need one extract from you, to hex edit it compatible 
The order should be identical i feel. No reason to do 10 times the work for each board
Attached, 7z file
Looks to be very barebones except top descriptor ~ which lists the board and the bios version
Other ones should be dates and options ~ in case it won't be loaded


----------



## Audioboxer

Heading in the right direction, all the time I have for testing this morning.

VSOC 1.15v > 1.175v
VDDG CCD 0.95v > 1.0v
VDDG IOD 1.07xv > 1.08v
VDIMM 1.6v > 1.59v

I know VDIMM can come down, it's just about being careful with ClkDrvStr. Lower I bring it down the more likely it seems to be I might need to go from 30 > 40. Just trying to reduce number of variables at the moment that might cause an error. Karhu errors seem to be around CPU/IMC, so trying to focus on that at the moment, VDIMM dropping to 1.55~1.56v can come later.

@Veii What was it again you wanted me to test at 3600, Hi-Z and? Any specific timings? Will try that next when I have time.


----------



## Veii

Audioboxer said:


> @Veii What was it again you wanted me to test at 3600, Hi-Z and? Any specific timings? Will try that next when I have time.


That's all 
Hi-Z with Park 7 likely
Hi-Z needs some PARK, can't run it on disable

Then just scale up in freq "if you even can" 
Just a confirmation that it actually works, or rather "doesn't work"

I'm having a fun time
4600 C17-17 profile didn't boot at all, but got lower on tWTR (4-10) ~ stable
Generic - Geekbench Browser hit 10k mem ~ but no comparison tables

Swapped dimms around, 4600 C17-17 boots, but one bluescreen & usb controller didn't work. Great
Next reboot, loading the same profile after CMOS reset and PSU off (after swapping the dimms) ~ now it boots and runs fine although 9-10ns slower
Loading 4200 profile again, (in case of CBS changes) changing variables to same 4600 C17-17 profile...and nothing boots.

Changing to 4200 1:1 profile, posts
changing to 4600 2:1 profile, posts
Running anything higher than fast 4200 1:1 on the same profile , soo going 2:1 ~ doesn't post
i, am confused


----------



## Audioboxer

Veii said:


> That's all
> Hi-Z with Park 7 likely
> Hi-Z needs some PARK, can't run it on disable
> 
> Then just scale up in freq "if you even can"
> Just a confirmation that it actually works, or rather "doesn't work"
> 
> I'm having a fun time
> 4600 C17-17 profile didn't boot at all, but got lower on tWTR (4-10) ~ stable
> Generic - Geekbench Browser hit 10k mem ~ but no comparison tables
> 
> Swapped dimms around, 4600 C17-17 boots, but one bluescreen & usb controller didn't work. Great
> Next reboot, loading the same profile after CMOS reset and PSU off (after swapping the dimms) ~ now it boots and runs fine although 9-10ns slower
> Loading 4200 profile again, (in case of CBS changes) changing variables to same 4600 C17-17 profile...and nothing boots.
> 
> Changing to 4200 1:1 profile, posts
> changing to 4600 2:1 profile, posts
> Running anything higher than fast 4200 1:1 profile , soo going 2:1 ~ doesn't post
> i, am confused












Something like that? tPHYRDL is 26/26.

What is Hi-Z? lol


----------



## Veii

Audioboxer said:


> View attachment 2545486
> 
> 
> Something like that? tPHYRDL is 26/26.
> 
> What is Hi-Z? lol


Soo ASRock was lazy, or MSI did more work  
Cautious with that VDIMM 
Hi-Z is very strong


----------



## Audioboxer

Veii said:


> Soo ASRock was lazy, or MSI did more work
> Cautious with that VDIMM
> Hi-Z is very strong


Oh don't worry I won't run it through any testing, I'm not even sure what it is. Stronger than RttWr 1?


----------



## Veii

Audioboxer said:


> Oh don't worry I won't run it through any testing, I'm not even sure what it is. Stronger than RttWr 1?


I don't know how much
Hence on Hex while WR 1 = 240, Hi-Z is 255
But 255 can equally mean maxed out number ~ unsure how much it really is

It was enough to push my dimms at 1.25v near 48°
Instead running 1.56ish at 47-48°

1.2v was enough for 3200 14-14
1.25v was enough for 3600 14-14


----------



## Veii

This overboost (boot?) bug, makes comparing things hard


4200 C15-15 / 6-8-36,5-14 vs Generic - Geekbench Browser


All of them (on Aida) are above max value
























That aida can bug out is known, but not on more stress tests
Strongly doubt that AES single out of nowhere improves 40%


----------



## Audioboxer

An idea of where AIDA sits at the moment. I was seeing a low of 56.7ns at 4400C15, this is about the same. Bit of scope left in this profile to bring down tRCDWR and some secondaries if stable enough to do so.

So, running out of sync even at 4533 is going to still result in a 2ns+ penalty over running in sync at 3800.


----------



## MrHoof

So I gave off/1/6 a go at my daily settings 3800 c14 1.55v I only changed the RTT and it seems stable Karhu gonna follow.
But the suprising part is off/1/6 is more temp resilent then 7/3/3.
7/3/3 would error out at 47°C+. The higher temp comes from lower Fanspeed.


----------



## Audioboxer

TMavica said:


> Everytime I stuck at cycle 19 in TM5 test, Windows 11
> View attachment 2545464


Just noticed this, your Rtts and Proc might need some work. TM5 can timeout on Windows 11 due to a CPU boosting bug but it can still also be memory instability.

Try running 36.9/34.3 and 7/3/3 or 6/3/3 and see how you get on.


----------



## ManniX-ITA

Audioboxer said:


> Disabling the cache makes Karhu go super slow lol, it's weird. Would rather play around with cache enabled for a bit (above is enabled).


It's weird... shouldn't be the case.
I'm running it with 14 threads now to check and did 7% in 2:15s which looks normal.


----------



## Audioboxer

ManniX-ITA said:


> It's weird... shouldn't be the case.
> I'm running it with 14 threads now to check and did 7% in 2:15s which looks normal.


Yeah that's slow for me, 7% is done super quick on my end lol. Have you tried between cache enabled and disabled to check your own speed difference?


----------



## ManniX-ITA

Audioboxer said:


> Yeah that's slow for me, 7% is done super quick on my end lol. Have you tried between cache enabled and disabled to check your own speed difference?


Indeed I didn't recall it was so quick 
Generally I test without Cache as not only IMC can raise errors but the error detection is quite poor.


----------



## PJVol

Veii said:


> Mainly interesting is, if ASRock profiles are board independent compatible


No, it seems.


----------



## Veii

PJVol said:


> No, it seems.


Attempt v.01
Might need v2 

As always, i depend on you
Not sure what i modify, just use logic & work in patterns

It has to load:
4200:2100 , +10mV core offset, loadline 2, 1.65v VDIMM, 870mV VDDP, 900-1020-1120-1250mV.
procODT 30ohm, Soc loadline i think 1 ? i forgot


----------



## PJVol

Veii said:


> It has to load:
> 4200:2100 , +10mV core offset, loadline 2, 1.65v VDIMM, 870mV VDDP, 900-1020-1120-1250mV.
> procODT 30ohm, Soc loadline i think 1 ? i forgot


None of the above setting is applied, despite BIOS reports - "profile loaded".
So it basically saying "I loaded it", but "would you **** with this mess" ))



Mach3.2 said:


> I wonder why AMD didn't have it in their Ryzen Master tool if it's possible to change those values from within Windows..


Of course we can only guess, but from a purely technical standpoint, there might be a reason.
AFAIK some operating points defined at boot during the various BTC procedures (boot time calibration), including PSM counts, i.e. "default" curve settings (fused at production) which depends on ambient temperature and I think the calibration itself is still not accurate enough despite being carried out at V_inversion_ (t° inversion voltage).
The same goes for power limits(though at less degree), so you should have this in mind, when applying temp-dependent settings on-the-fly. The good practice would be calling BTC from windows, right after the changes is done, so that they were not erased, but I'm not sure this is possible at all.


----------



## TMavica

Audioboxer said:


> Just noticed this, your Rtts and Proc might need some work. TM5 can timeout on Windows 11 due to a CPU boosting bug but it can still also be memory instability.
> 
> Try running 36.9/34.3 and 7/3/3 or 6/3/3 and see how you get on.


 it stopped at cycle 11


----------



## Veii

PJVol said:


> None of the above setting is applied, despite BIOS reports - "profile loaded".
> So it basically saying "I loaded it", but "would you **** with this mess" ))


Our layout is identical, ok one more try in a bit (30min)

Good is that it loaded 
But i wasn't sure about one option
EDIT:
I really don't have high hopes on this
~ let me know)


----------



## Audioboxer

TMavica said:


> it stopped at cycle 11
> View attachment 2545537


Try bumping your tRFC up by 8 or 16. What VDIMM are you running at? Also, CkeDrvStr 30 might help.


----------



## TMavica

Audioboxer said:


> Try bumping your tRFC up by 8 or 16. What VDIMM are you running at? Also, CkeDrvStr 30 might help.


Ok. And my vdimm is 1.5


----------



## Audioboxer

TMavica said:


> Ok. And my vdimm is 1.5


tRFC is probably a bit low for that voltage. Either increase your tRFC a bit or increase VDIMM to 1.51-1.53v.


----------



## TMavica

Audioboxer said:


> tRFC is probably a bit low for that voltage. Either increase your tRFC a bit or increase VDIMM to 1.51-1.53v.


Thats strange. Doing cycle 12, my PC reboot itself, there is no any tm5 error / whea error
tRFC 256 and Cke 30


----------



## Veii

TMavica said:


> tRFC 256 and* tCKE 30*


Why ?


----------



## TMavica

Veii said:


> Why ?


CkeDrvStr


----------



## MrHoof

@Veii How does RTTNom work when its disabled I forgot was it using procODT instead?
Seems like off/1/7 works too at 3800









edit: Just noticed tWRRD changed to 4 thats a new one, i always have it on auto and it was always 3.
edit2: not karhu stable.


----------



## Veii

MrHoof said:


> @Veii How does RTTNom work when its disabled I forgot was it using procODT instead?
> Seems like off/1/7 works too at 3800
> View attachment 2545581


If DynamicODT is enabled
It will generate the Ceiling limits by itself , dynamically
But it seems to only be able to do one of both
PARK floor, or NOM ceiling

Dual Rank (if NOM would be Hi-Z , which it cant't ~ ty AMD)
In general, on dynamicODT mode - for dual rank it adjusts by rank
But requires one of both to be balanced
Hi-Z is slightly complicated by it's implementation, soo you can't call it "one fixed impedance"

This is one part of the explanation








DDR4 is a complex interface to verify — assistance needed! - Semiwiki


The design of parallel interfaces is supposed to be (comparatively) easy -- e.g., follow a few printed circuit board routing guidelines; pay attention to data/clock/strobe signal lengths and shielding; ensure good current return paths (avoid discontinuities); match the terminating resistances to...




semiwiki.com




Sadly i couldn't find any behavior described in AMDs documents
Soo they seem to follow 3rd party specs

EDIT:
There is a bit about LPDDR4 vs DDR4 
But they behave pretty similar according to the Bios implementation 
It's just what "it loads" , but "technically" anybody could solder LPDDR4 on the board and the CPU would recognize it instantly.
They (the PCB designer) wouldn't even need to run a different bios for it


----------



## MrHoof

Park 7 does train tWRRD 4 every time, going back to Park 6 brings it back to 3. Any idea?
Like how are they connected.


----------



## Veii

MrHoof said:


> Park 7 does train tWRRD 4 every time, going back to Park 6 brings it back to 3. Any idea?
> Like how are they connected.


Coincidence 
RTT's are only controlling powering ~ barely signal delay
Does anything else change ?
Or maybe between dimms ?


----------



## MrHoof

Oh ye was just coincidence true. Forced a retraining and were back to 3 but that also means that last 25 cycle tm5 was pointless 😐


----------



## Veii

MrHoof said:


> Oh ye was just coincidence true. Forced a retraining and were back to 3 but that also means that last 25 cycle tm5 was pointless 😐


Why ?
You proofed stability on some loaded timings
(well to the extend of what TM5 can "proof")


----------



## MrHoof

Well gonna redo the run with tWRRD 3 tomorrow and karhu overnight. Pointless in the sense of I am not gonna run tWRRD 4.


----------



## Audioboxer

Veii said:


> If DynamicODT is enabled
> It will generate the Ceiling limits by itself , dynamically
> But it seems to only be able to do one of both
> PARK floor, or NOM ceiling
> 
> Dual Rank (if NOM would be Hi-Z , which it cant't ~ ty AMD)
> In general, on dynamicODT mode - for dual rank it adjusts by rank
> But requires one of both to be balanced
> Hi-Z is slightly complicated by it's implementation, soo you can't call it "one fixed impedance"
> 
> This is one part of the explanation
> 
> 
> 
> 
> 
> 
> 
> 
> DDR4 is a complex interface to verify — assistance needed! - Semiwiki
> 
> 
> The design of parallel interfaces is supposed to be (comparatively) easy -- e.g., follow a few printed circuit board routing guidelines; pay attention to data/clock/strobe signal lengths and shielding; ensure good current return paths (avoid discontinuities); match the terminating resistances to...
> 
> 
> 
> 
> semiwiki.com
> 
> 
> 
> 
> Sadly i couldn't find any behavior described in AMDs documents
> Soo they seem to follow 3rd party specs
> 
> EDIT:
> There is a bit about LPDDR4 vs DDR4
> But they behave pretty similar according to the Bios implementation
> It's just what "it loads" , but "technically" anybody could solder LPDDR4 on the board and the CPU would recognize it instantly.
> They (the PCB designer) wouldn't even need to run a different bios for it


I'm going to be the dunce in the room and ask the simple question, if it can be run like MrHoof is proving should we run it?

Like going from 7/3/3 at 3800 to disabled/1/6? Less stressful on the memory? More stressful? Cleaner signal? No benefit or difference?

Still happy to see MrHoof doing this testing as I've got my hands full with 4533 lol.

It's at least got me thinking if I should revisit RttPark at 3800. 7/3/4 and 7/3/5 boot, but I haven't really tested them.


----------



## MrHoof

Well i like the fact that i can now run 50°C stable and i dindt figure out what is the max yet. But thats alot better then 47°C since my case has really not the best airflow.
Temps are the same as 7/3/3 at the same Fanspeed, I didnt find a anything going against it yet.


----------



## Veii

Audioboxer said:


> I'm going to be the dunce in the room and ask the simple question, if it can be run like MrHoof is proving should we run it?
> 
> Like going from 7/3/3 at 3800 to disabled/1/6? Less stressful on the memory? More stressful? Cleaner signal? No benefit or difference?
> 
> Still happy to see MrHoof doing this testing as I've got my hands full with 4533 lol.
> 
> It's at least got me thinking if I should revisit RttPark at 3800. 7/3/4 and 7/3/5 boot, but I haven't really tested them.


Weaker PARK is always good
But you have to check how much the added latency penalty is with it
For hard to power B2's , that one is surely great. Doesn't ruin signal integrity that much and corrects
But it's more strain to the PCB

Can't say. But generally it's a stronger signal and you don't have to rely that much on the board (CAD_BUS)
Although data-eye is smaller, soo potentially can & will limit maximum OC
I don't think it matters for now on our FCLK limits.
Hi-Z would be great, but that might be overdone & might even need 24 ClkDrvStr

In general, the weaker procODT (how ever you tune it) , the better
Weaker procODT, allows for lower voltages = better signal integrity overall 
However you achieve it  
Just double & tripplecheck (maybe even with Geekbench3 & timespy CPU) , if you lose score and the sample starts auto-correcting on low voltage


----------



## Audioboxer

@Veii I was able to reintroduce RttNom and run a more "traditional" tCKE 1. AUTO results in tCKE 0, but I have no experience with 0. Just playing around. ClkDrvStr 40 and RttNom seem to help stability when running a lower voltage and also wanting to run a higher VSOC. Will keep testing with voltages.

If I can find multiple ways to run 4533 then it gives a little optimism for 4600, but it definitely feels like 4533 will be the highest I can get stable. Not interested in eventually forcing a boot, I'm all about daily stable not "bench stable" 👀


----------



## MrHoof

MrHoof said:


> @Veii
> Seems like off/1/7 works too at 3800


Not karhu stable Error after 3h. This night i will try off/1/6 instead and at the moment i am trying 7/2/6.


----------



## Audioboxer

Taking a break from 4533 for now as testing requires lots of full 25 cycles at this point for stability. Will resume work on secondaries some point next week. A quick look at 3800 again










In order to boot RttPark 7, I need to use RttWr 1 or Hi-Z. After 5 minutes with all loop fans off and just water flow rate for cooling, 33 degrees.










RttWr 3 will allow RttPark to boot at 5. 33.2 degrees. However, 5 minutes is nowhere near long enough for thermal equilibrium, though watercooling is quite consistent with temps, probably a bit earlier than aircooling is.

I'm more inclined to see the highest park I can run stable at RttWr 3 than change my 3800 profile to RttWr 1. Something else I should look at is ProcODT, I can go as low as 28.2 without tPHYRDL complaining.

*edit* - 6 can boot with RttWr 2


----------



## Audioboxer

Looking positive. 7/3/5 introduces some powering issues which impact tPHYRDL. I guess it's not too surprising running both RttWr and RttPark weak.


----------



## Veii

Good improvements 
I'm not sleeping either, but you guys make much better progress
* it passed TM5, but i forgot to make a screenshot together








That's +700 read, + 400 Copy, +0.1ns








Still incline if 736 really is better or 637 
Both run

Probably the only improvement from my side, was removing the dimms till 4600 17-17 set boots again and swapping the order of them
Needed 3 reseats and little dusting.
Soo can be just improvement out of nowhere, without own work
That's Win 11, but i still miss 0.2ns L3 . . .


https://cdn.discordapp.com/attachments/771895615893798913/937028491143172138/C0011.mp4


Recording for a discord server ~ shows well how prochot throttle looks like
And why it makes no sense to benchmark on CPU heavy tests ~ that's AVX2 Handbreak








Without an AIO or waterblock, this CPU will always score bad. And benchmarking with 4.7 on things like LinX or Corona is really not a good idea


----------



## MrHoof

My 5h karhu is done with 7/2/6 error free. Testing my new temp limit now.


----------



## ManniX-ITA

@MrHoof 
Are you sure tRAS/tRC at 26/40 is improving?
Cause I've a similar profile and I recall it was actually worse than 28/42.
Around 200-300 MB/s bandwidth less in AIDA and worse scores in all Prime benchmarks.


----------



## MrHoof

Aida show basicly no diffrence just margin of error but dram calc bench is 0.5sec faster on avg.


Spoiler: 28-42

















Spoiler: 26-40


----------



## Audioboxer

@Veii Whilst this needs a 25 cycle as pretty much any single change on this profile will need now, that's my DrvStrs now back where they are at 3800 as well as tCKE. CsOdtDrvStr has been dropped from 30 to 24. RttNom decreased to 7 from the 6 25 cycle.

Out of interest, what is the significance of tCKE being at 0? Is that it disabled?

Still struggling with 4600, but someone with a G chip advised me they can't get DR above 4600 either, so if a chip with the best IMC from AMD cannot do it I'm going to guess this may well be my ceiling.


----------



## ManniX-ITA

MrHoof said:


> Aida show basicly no diffrence just margin of error but dram calc bench is 0.5sec faster on avg.


Thanks for checking, I'll do another round.
I'm not really confident on dram calc bench...

Better to use Benchmate:






BenchMate







benchmate.org





Comes with Superpi, wprime, y-cruncher and you can save easily scores with F6.
Much more reliable stuff to compare profile changes.


----------



## MrHoof

Can do some more benches later. Got some stuff to do for now.


----------



## Audioboxer

Finally broke 70k, but I'll need to test this profile fully. Sadly dropping secondaries isn't doing much for latency now, looks like I'll be stuck around 56.5ns at 4533.


----------



## Luggage

Veii said:


> Good improvements
> I'm not sleeping either, but you guys make much better progress
> * it passed TM5, but i forgot to make a screenshot together
> 
> 
> 
> 
> 
> 
> 
> 
> That's +700 read, + 400 Copy, +0.1ns
> 
> 
> 
> 
> 
> 
> 
> 
> Still incline if 736 really is better or 637
> Both run
> 
> Probably the only improvement from my side, was removing the dimms till 4600 17-17 set boots again and swapping the order of them
> Needed 3 reseats and little dusting.
> Soo can be just improvement out of nowhere, without own work
> That's Win 11, but i still miss 0.2ns L3 . . .
> 
> 
> https://cdn.discordapp.com/attachments/771895615893798913/937028491143172138/C0011.mp4
> 
> 
> Recording for a discord server ~ shows well how prochot throttle looks like
> And why it makes no sense to benchmark on CPU heavy tests ~ that's AVX2 Handbreak
> 
> 
> 
> 
> 
> 
> 
> 
> Without an AIO or waterblock, this CPU will always score bad. And benchmarking with 4.7 on things like LinX or Corona is really not a good idea


With Cooling Img 3905.mkv



http://imgur.com/a/uJSPuiB


----------



## MrHoof

ManniX-ITA said:


> Thanks for checking, I'll do another round.
> I'm not really confident on dram calc bench...
> 
> Better to use Benchmate:


Here you go still everything margin of error area. But you might be right there is not much point in running it that low.


Spoiler: SuperPi

















Spoiler: ycrunsher















edit: just checked those would be top20 on hwbot for 5800x 🤣

edit2: advantage of 7/2/6 over 7/3/3 is huge! if stable
RAM fan off, stopped it there but normaly a few seconds over 47°C would throw a error at 7/3/3.


Spoiler: 58°C


----------



## Audioboxer

MrHoof said:


> Here you go still everything margin of error area. But you might be right there is not much point in running it that low.
> 
> 
> Spoiler: SuperPi
> 
> 
> 
> 
> View attachment 2545811
> 
> 
> 
> 
> 
> 
> Spoiler: ycrunsher
> 
> 
> 
> 
> View attachment 2545812
> 
> 
> 
> 
> edit: just checked those would be top20 on hwbot for 5800x 🤣
> 
> edit2: advantage of 7/2/6 over 7/3/3 is huge! if stable
> RAM fan off, stopped it there but normaly a few seconds over 47°C would throw a error at 7/3/3.
> 
> 
> Spoiler: 58°C


@Veii any technical reasons why Rtts could increase thermal capacity as drastically as this?


----------



## MrHoof

Trying to figure out the fanspeed to keep them in mid 50s atm for a full 25 cycle run.


----------



## Veii

Audioboxer said:


> @Veii any technical reasons why Rtts could increase thermal capacity as drastically as this?


Unless there are thing's i'm missing about dynamic ODT
This result wasn't targeted or expected
Either has a logic to it, it is just a stabilising side product by the way RTT_WR works against noisy signal

Edit:
I don't think even Arshia/Anta knows how or why exactly thermals are managed by the dimm's
I can't fully understand it, but it seems to have an requirement for an on-dimm sensor first existing & 2nd being reported on the same expectation address ~ in order for slowing down or 2x/4x refresh mode to function

It probably can be tested by supplying very low tRFC 2
Which then is trained and configured on boot
If it really is thermal aware, tMOD and tSTAG will change
And tRC_PAGE should've been generated correctly

But you have to tell me, so far
I haven't read anything on the boards having any thermal tracking abilities
There seems to be no sensor at or under the dimm slots
And there is no guarantee that manufactures expose their thermal sensor on the correct address ~ in order for dimm-thermalmanagement to function
Can't say out of nowhere really

Either side effect/byproduct of how dynamicODT functions
Or actual dynamic thermal mode and dynamic tRFC adaptiveness
One of both


----------



## MrHoof

Would think its down to signal integrity, since the the SR kit(7/3/6 20/20/20/24) I used to run at 1.55v without a fan was stable at 57° max too. Small Motherboard + 8layers(x570i) probably help with that.

edit: probalby also not huge for everoyone but for me in ITX case with a air cooler I am amazed. 
not much space for airflow over the RAM.


----------



## blodflekk

This is what I've finally got stable. Using 1.55v. Latency in aida is terrible at 64ns. Wanting to push voltage further and get things tighter as some of those secondaries are terrible. Do I need to change resistances as I go beyond 1.55 ?


----------



## Taraquin

Veii and others: Any idea why performance in certain apps get negative performance scaling above 3800/1900 without whea 19? Y-cruncher and linpack for example. When I keep soc, iod etc the same so IO-die should consume the same I get 1-2% lower perf, but aida, dram calc and SOTTR scales fine and gets a few percent faster even with higher soc, iod and slower ram timibgs going from 3800cl15 to 4000cl16.


----------



## Audioboxer

Audioboxer said:


> View attachment 2545783
> 
> 
> View attachment 2545784
> 
> 
> Finally broke 70k, but I'll need to test this profile fully. Sadly dropping secondaries isn't doing much for latency now, looks like I'll be stuck around 56.5ns at 4533.


Had some issues with this on the secondary timings around the hour mark. What I'm finding out at 4533 is taking things like tWTRL/tWR for granted is a no go. Just because they can go to like 8/10 at 3800, or 10/12 at 4400, doesn't mean either result stands a chance at 4533. Even with more voltage.

Having to further test the SCLs as well, again, something that can go as low as 2 at 3800, might not be OK doing 4 at 4533.

Guess it makes sense though at higher frequencies it's more stressful on the memory to try and run really low timings.

Trying my hardest to finish this profile over 70k read, but the balancing act that goes on between timings and voltage at 4533 is a right challenge.


----------



## ManniX-ITA

MrHoof said:


> edit2: advantage of 7/2/6 over 7/3/3 is huge! if stable
> RAM fan off, stopped it there but normaly a few seconds over 47°C would throw a error at 7/3/3.


I like this RTT... testing with tRCDRD at 14 which is always failing for me above 49-50c.
Now I can get up to 53-54c without #2/#10. Still failing after a while of course but better.
Definitely easier, seems I get as well much more headroom compared to 7/3/3.



blodflekk said:


> This is what I've finally got stable. Using 1.55v. Latency in aida is terrible at 64ns. Wanting to push voltage further and get things tighter as some of those secondaries are terrible. Do I need to change resistances as I go beyond 1.55


Doesn't really make sense 64ns... even with those secondaries.
Maybe tCKE at 8 is messing up, set it to 1.
Try to set tRDWR/tWRRD in Auto and see what is set.
If it doesn't boot try with 8/3 or 9/3.


----------



## Audioboxer

ManniX-ITA said:


> I like this RTT... testing with tRCDRD at 14 which is always failing for me above 49-50c.
> Now I can get up to 53-54c without #2/#10. Still failing after a while of course but better.
> Definitely easier, seems I get as well much more headroom compared to 7/3/3.
> 
> 
> 
> Doesn't really make sense 64ns... even with those secondaries.
> Maybe tCKE at 8 is messing up, set it to 1.
> Try to set tRDWR/tWRRD in Auto and see what is set.
> If it doesn't boot try with 8/3 or 9/3.


Yup, it's why I asked Veii if there was a more technical consensus on why these Rtts are enabling greater thermal overhead for us.

Either way, it's a good discovery it seems! More so for anyone air-cooling. Some testing with tRFC should be done as well to see if its thermal capacity increases or not, because it's super temp sensitive.

It would also be good to pinpoint if its a combination of RttWr and RttPark or one or the other helping most. I can do 7/3/5, but it's not stable. 7/3/4 is likely my limit. But then again I'm a bad test candidate for this due to watercooling.


----------



## Veii

blodflekk said:


> Do I need to change resistances as I go beyond 1.55 ?


You already did
731 or 031 was the old
I'm happy to see board partners slowly (very slowly !) but finally, start to listen to me
~ and implement this as basic changes

733 usually now is the "better" default
731 was an issue with voltages above 1.46v ~ 733 should be fine near 1.54, likely 633 is fine till 1.62v
* need to check after which VDIMM you have to increase RTT_NOM

RTT_WR 120ohm, is a too big change and will fail between DIMM PCBs
But _WR 60, & _PARK 80 or lower impedance value ~ is fine.

Only caveat,
733 or 633 works much better on 1 DPC boards
Daisy chain will be fine for our "low" MCLK limits, but it's not perfect on 2DPC boards.
Well it's certainly much better for signal integrity than strong _PARK 240ohm


----------



## blodflekk

ManniX-ITA said:


> I like this RTT... testing with tRCDRD at 14 which is always failing for me above 49-50c.
> Now I can get up to 53-54c without #2/#10. Still failing after a while of course but better.
> Definitely easier, seems I get as well much more headroom compared to 7/3/3.
> 
> 
> 
> Doesn't really make sense 64ns... even with those secondaries.
> Maybe tCKE at 8 is messing up, set it to 1.
> Try to set tRDWR/tWRRD in Auto and see what is set.
> If it doesn't boot try with 8/3 or 9/3.


I did start out with auto for tRDWR which trains at 18, tWRRD is also very loose, I forget the exact tick. 
I set tCKE to 8 per @Veii's recommend, setting to 1 doesn't seem to make a difference.
8/3 won't post, 9/3 wasn't stable. 

Going to mash vDIMM and see where I land


----------



## Audioboxer

Veii said:


> You already did
> 731 or 031 was the old
> I'm happy to see board partners slowly (very slowly !) but finally, start to listen to me
> ~ and implement this as basic changes
> 
> 733 usually now is the "better" default
> 731 was an issue with voltages above 1.46v ~ 733 should be fine near 1.54, likely 633 is fine till 1.62v
> * need to check after which VDIMM you have to increase RTT_NOM
> 
> RTT_WR 120ohm, is a too big change and will fail between DIMM PCBs
> But _WR 60, & _PARK 80 or lower impedance value ~ is fine.
> 
> Only caveat,
> 733 or 633 works much better on 1 DPC boards
> Daisy chain will be fine for our "low" MCLK limits, but it's not perfect on 2DPC boards.
> Well it's certainly much better for signal integrity than strong _PARK 240ohm


I think the question some of us have now though is if you can run 7/3/3 and maybe even 7/3/4, but also run 7/2/6, what is "better"?










Is there a "better"? It definitely seems like running 7/2/6 has helped those air-cooling have a higher thermal ceiling, for example.

I guess I'll try revisiting tRFC. I tried getting to around 110ns/below 110ns, but it was proving a challenge, even watercooled. That's a side issue though, probably just the reality of the tRFC ceiling with B-die.


----------



## PJVol

Veii said:


> Recording for a discord server ~ shows well how prochot throttle looks like
> And why it makes no sense to benchmark on CPU heavy tests ~ that's AVX2 Handbreak


 I'll try again )


----------



## Luggage

PJVol said:


> I'll try again )
> View attachment 2546004


HTFMAX?!?









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


@MrHoof Are you sure tRAS/tRC at 26/40 is improving? Cause I've a similar profile and I recall it was actually worse than 28/42. Around 200-300 MB/s bandwidth less in AIDA and worse scores in all Prime benchmarks.




www.overclock.net


----------



## PJVol

Luggage said:


> HTFMAX?!?


Idk what this monitor is showing, it'd better to look at the pm_table dump from ZenTimings made during the test

Or, if you don't mind, can you post the same screenshots while running linpack 8gb? (actually two - with a EDC limit set to 90A and 400A)


----------



## sealxohd

Right now im playing with 4400 1T. PHY is 30/30










Lets see where this goes.


----------



## MrHoof

I would love to also do some high frequency testing but I can not boot over 4200mhz reliable even at cl20... tried already everything from procODT,2t,vddp up to 1v and diffrent RTTs.


----------



## Veii

PJVol said:


> I'll try again )


hm ?


----------



## PJVol

Can you make the screens I asked Luggage for in a prev. post, please?


----------



## sealxohd

meh


----------



## blodflekk

Whelp, that was a fail. Went to 1.6 vDIMM and still couldn't budge anything, tWR/tRTP still 14/7 tRCDRD still 15 =( 

Maybe its heat? I don't have temp sensors on my dimms so I can't say where I'm at


----------



## TimeDrapery

@PJVol 

Great tool! On my 5600X and my 5800X (B550i Pro AX and B550 Master) it works wonderfully and has given me no issues until...

I induced a (freeze and then) crash on the 5800X by setting a CO value too low and now when I go to open the tool the cores aren't displayed and I'm presented with an error message stating that something's missing

So far I have just cleared my event log, deleted the directory, and decompressed another copy of your tool but I'm still presented with the same error message when opening the tool


































Of course I didn't screenshot the error message 😂😂😂😂😂

I can when I'm home next if it's helpful


----------



## PJVol

TimeDrapery said:


> something's missing


It seems crash corrupted settings file.
Just deleting folder c:/Users/<your name>/AppData/Local/pjvol should help.


----------



## TimeDrapery

PJVol said:


> It seems crash corrupted settings file.
> Just deleting folder c:/Users/<your name>/AppData/Local/pjvol should help.


Bam! Fixed! Great work and thank you a ton for sharing!!!


----------



## Jonnycat99

I am trying to get CJR (2x16) to use 1T, but whenever I do tPHYRDL goes from 26/26 to 28/28, negating any improvement (2T has a lower latency than 1T with 28/28). 

I've tried changing ProcODT to values between 36 and 48, but no dice. I tried increasing tCWL to 16, but no dice. Before I continue trying to reinvent the wheel, do you have any suggestions of what other timings I should try to modify?


----------



## blodflekk

Jonnycat99 said:


> I am trying to get CJR (2x16) to use 1T, but whenever I do tPHYRDL goes from 26/26 to 28/28, negating any improvement (2T has a lower latency than 1T with 28/28).
> 
> I've tried changing ProcODT to values between 36 and 48, but no dice. I tried increasing tCWL to 16, but no dice. Before I continue trying to reinvent the wheel, do you have any suggestions of what other timings I should try to modify?
> 
> View attachment 2546083


tWR is too tight, try 12 or 14


----------



## Jonnycat99

blodflekk said:


> tWR is too tight, try 12 or 14


Thanks flekk, sadly no joy.


----------



## blodflekk

I also can't get 1T on my kit at 3800, not without tPHYRDL 26/28, but i got there with addcmdsetup 56


----------



## byDenoso

Jonnycat99 said:


> I am trying to get CJR (2x16) to use 1T, but whenever I do tPHYRDL goes from 26/26 to 28/28, negating any improvement (2T has a lower latency than 1T with 28/28).
> 
> I've tried changing ProcODT to values between 36 and 48, but no dice. I tried increasing tCWL to 16, but no dice. Before I continue trying to reinvent the wheel, do you have any suggestions of what other timings I should try to modify?
> 
> View attachment 2546083


Drop Cldo_Vddp to less than 875mv and try again


----------



## Jonnycat99

blodflekk said:


> I also can't get 1T on my kit at 3800, not without tPHYRDL 26/28, but i got there with addcmdsetup 56


I'll look into the Setups, thanks.



byDenoso said:


> Drop Cldo_Vddp to less than 875mv and try again


Been meaning to do that, sadly still at 28/28.


----------



## Luggage

PJVol said:


> Can you make the screens I asked Luggage for in a prev. post, please?


When I get home this evening


----------



## TMavica

Mine is G.Skill F4000C14-15-15-35 16x2 GTES, thats my timing so far. I can do tRCDWR to 8 without error too, but seem not much different, I want to ask is there anyway to train the tPHYRDL to 26/26? now is 28/28


----------



## Taraquin

PJVol said:


> Updated BIOS with the agesa 1.2.0.5 to see what all this noise was about.
> And, well... just look at this, ain't it funny?
> View attachment 2543304


Looks like it increased all limits except lowering max voltage. On my setup max voltage using +200 pbo and -29x2, -30x4 is 1.34v, I guess this will an be important perflimit if using low CO or Hydra?


----------



## Taraquin

TMavica said:


> Mine is G.Skill F4000C14-15-15-35 16x2 GTES, thats my timing so far. I can do tRCDWR to 8 without error too, but seem not much different, I want to ask is there anyway to train the tPHYRDL to 26/26? now is 28/28
> 
> View attachment 2546202


Phyl is a weird timing, it usually sets to 26/26 at my setup at 1t, dunno why.

Tip for improvement: Try 14 14 14 ras 26 rc 40, that will probably work since at stock 1.55v(?) you have top bin, except for that, awesome timings


----------



## TMavica

Taraquin said:


> Phyl is a weird timing, it usually sets to 26/26 at my setup at 1t, dunno why.
> 
> Tip for improvement: Try 14 14 14 ras 26 rc 40, that will probably work since at stock 1.55v(?) you have top bin, except for that, awesome timings


I cant go tRCDRD to 14, there is error even I set vdimm to 1.55. My vdimm is 1.5v now, if I set tRP to 14 and tRAS to 28/29, the tPHYRDL is 26/28


----------



## PJVol

Taraquin said:


> Looks like it increased all limits except lowering max voltage


If you're about ppt, etc ... I did that when testing.


----------



## Audioboxer

TMavica said:


> Mine is G.Skill F4000C14-15-15-35 16x2 GTES, thats my timing so far. I can do tRCDWR to 8 without error too, but seem not much different, I want to ask is there anyway to train the tPHYRDL to 26/26? now is 28/28
> 
> View attachment 2546202


Change to 2T and I bet you it trains at 26/26 lol. Or boot tCL13 1T if you can, even if unstable, and I bet it changes to 26/26. At 3800 running tCL14 1T always trains 28/28 for me no matter what. Only 2T goes to 26/26. For my daily profile I run tCL13, something you should be able to manage on that kit at around 1.55v and it runs 26/26.



















In other news, just testing running 7/3/4 here instead of 7/2/6. Looks promising. This appears to be the weakest forms of all the Rtts I can run without trouble. 7/3/5 starts to introduce tPHYRDL issues, which is likely just general powering. But if increasing RttWr to help with powering might as well run 7/2/6 instead of 7/2/5.

Given I'm watercooled using RttWr for a higher thermal tolerance probably isn't necessary for me, I think I'm best just to stick with 7/3/4 rather than 7/2/6? I don't really know though, seems all this movement with DR in the past week in regards to Rtts and RttWr is quite "fresh" for the OCing community. Just gotta test things yourself and if stable make your own decisions.

Though it does seem to be generally accepted whatever RttNom and RttWr you run, try and run RttPark as low as you can.


----------



## Noxion

I can turn gear down mode off but it fails on a cold boot :/ it’s totally stable otherwise except for not being able to turn GDM off.


----------



## Audioboxer

Noxion said:


> I can turn gear down mode off but it fails on a cold boot :/ it’s totally stable otherwise except for not being able to turn GDM off.
> 
> View attachment 2546250


ClkDrvStr to 30 or 40. Powering 1T GDM disabled is harder.


----------



## Taraquin

PJVol said:


> If you're about ppt, etc ... I did that when testing.


You adjusted limit or were thre default limits?


----------



## PJVol

I've made that screenshots to focus people's attention on a chaged VID limit, just it, and the rest doesn't matter. All other default limits are the same.


----------



## bfollett

First, how do you know when you've reached the upper limit of your CPU's memory controller? I have a Ryzen 2600x and I thought I was stuck at 3466MHz (paired with my 3600 CL16 Hynix 2X8GB ram), but with lots of reading and experimenting with the Termination and Cad Bus settings, I first got 3533 and then 3600 stable. I've been trying for 3666 and 3733 but having no luck. The settings that worked for 3533 and 3600 had little in common with the Dram Calculator suggestions. Unfortunately, I have little understanding of the settings I've been adjusting and there are 3 I've made no attempt at (AddrCmdSetup, CSOdtSetup and CkeSetup). So, I thought I'd ask some experts if they think I have a shot at higher than 3600MHz and what settings to try to adjust. I will loosen the timing related bios settings while trying to figure out the Termination and Cad Bus settings. Below are the settings that worked at 3600. The 3533 settings were actually quite different than the 3600 settings but I don't have a screenshot handy for that.


----------



## Audioboxer

bfollett said:


> First, how do you know when you've reached the upper limit of your CPU's memory controller? I have a Ryzen 2600x and I thought I was stuck at 3466MHz (paired with my 3600 CL16 Hynix 2X8GB ram), but with lots of reading and experimenting with the Termination and Cad Bus settings, I first got 3533 and then 3600 stable. I've been trying for 3666 and 3733 but having no luck. The settings that worked for 3533 and 3600 had little in common with the Dram Calculator suggestions. Unfortunately, I have little understanding of the settings I've been adjusting and there are 3 I've made no attempt at (AddrCmdSetup, CSOdtSetup and CkeSetup). So, I thought I'd ask some experts if they think I have a shot at higher than 3600MHz and what settings to try to adjust. I will loosen the timing related bios settings while trying to figure out the Termination and Cad Bus settings. Below are the settings that worked at 3600. The 3533 settings were actually quite different than the 3600 settings but I don't have a screenshot handy for that.
> View attachment 2546254


Unless you can shift your FCLK above 1800 (unlikely with your processor), I wouldn't worry about it. Running out of sync hammers latency and unless you're getting your memory to like 4200 or something, the penalty is arguably too steep.

Best thing to do is be happy running in sync, so 3600, and now working on the tightest timings you can.


----------



## bfollett

I'm pretty happy with the 3600 but seeing all the 3000 and 5000 Ryzen chips now exceeding 4000MHz, I just wanted to try to reach as high as I could with my aging Zen+ cpu. I've seen posts of others that have reached 3733 with Zen+ and just wanted to see if I could as well, so any suggestions welcome... Otherwise 3600 it is.


----------



## ManniX-ITA

@Audioboxer 

You missed the asterisk 










For 32GB full coverage is around 11000%, I usually go over 14000%.


----------



## ManniX-ITA

I've managed to get FCLK 2000 stable with the AGESA 1.2.0.5; temperatures are higher and this hurts all long running MT tests like Corona, Linpack and the monero miner.
Some others doesn't like CPU-z and CB23, results are inline with the AGESA 1.2.0.1.

On others like Geekbench the new memeory profile thanks to the improved memory controller gives a small boost.
I wasn't able to reach 19500 in GB5 MT earlier. 
The new RTT 7/2/6 really helps and memory runs 1c lower when under TM5 reach thermal equilibrium.

















I need VDDP at 1000mV to run 4000CL14 with these timings, otherwise 3 beeps and memory overclocking failed message.
Previous AGESA would boot with 900mV but it wouldn't get stable and tRCDRD lowest possible was 16 (although I didn't try 7/2/6).


----------



## Luggage

PJVol said:


> Idk what this monitor is showing, it'd better to look at the pm_table dump from ZenTimings made during the test
> 
> Or, if you don't mind, can you post the same screenshots while running linpack 8gb? (actually two - with a EDC limit set to 90A and 400A)





http://imgur.com/a/cqMnYXh



like this?

Edit ok the load is shifting, I’ll time it better in a minute.

Edit2: no same result - with edc 90 it stays under 61.5C (i think the limimt was from my testing last fall) so THM does not trigger...


----------



## Veii

PJVol said:


> Idk what this monitor is showing, it'd better to look at the pm_table dump from ZenTimings made during the test
> 
> Or, if you don't mind, can you post the same screenshots while running linpack 8gb? (actually two - with a EDC limit set to 90A and 400A)


I'm not exactly sure about the reason , as it's clear like starry night (and sunny day ^^)
But here you go:

I'll double upload, seems like streamable . com, is region locked for you
_* or skip them entirely, as they do not like above 10min footage_








Wormhole - Simple, private file sharing


Wormhole lets you share files with end-to-end encryption and a link that automatically expires.




wormhole.app




ZenPTMonitor_s6TkY1g260 this was old that showed how it "improves" after the window is open and slowly slowly fixes itself mid recording load
Usually an "recording" is an allcore load and sometimes it get's hot enough







LinX takes at least a good minute to really start pushing load onto the unit
Sadly everything lags out, but at least the music stayed
(didn't notice my screenshot software recorded the music with it ~ soo i guess here it is.
Credits belong to Shingo Nakamura & the corresponding Lable, Monstercat, ~ for supplying the background music) 🤭

Also happy lunar new year ! 
More subtle improvements from me







tFAW 28, causes some #4's and #6's but i'll resolve that later
Some odd PCB crash on burst refresh. Likely RTTs or 10mV lacking VDIMM
EDIT:
3D Mark owner , it might be too late for you
But i guess why not ~ Steam Achievement, unique once a year
It was "legendary score" but they nerved it ~ booring


----------



## Subut

Hello all venerable members of this thread. I know little about overclocking memory but lately I've been really trying. I'm stuck and need advice. I'm using Viper Steel B-die memory on an msi x570 tomahawk board with the 5800x. I was running 4sticks of 8gb with the following settings (sorry for potato quality). The settings were satisfactory and was I chilling there, usually running 24hrs for a few months. (I'm testing performance with linpack and stability with memtest)









Last week while playing god of war 2018, a stick of ram suddenly decided to die which was unfortunate. I RMA'd the kit hoping for the best. Now that I'm left with a pair of single rank sticks I taught it would be a good opportunity to try clocking SR with b-die for the first time. You know, glass half full kinda deal. Anyway, so I've been working on this for a while now and I'm absolutely stuck. From here (2nd image) I tried lower primaries, lower tWTR's, lower tWR, lower SCL's, lower tRTP, lower tRDWR and lower tCKE all of which resulted in inferior performance or major instability. The only thing I haven't tried lowering yet is the tRFC which I left for later.










So, seeing that many of my times are a long way away from what I've got with DR it seems there's a problem. After reading many pages from this thread I think my problem is that I don't know jack about the impedances. I don't know how to tune the ohm values there and I have a strong suspicion that there's my problem. I haven't any clue what lowering or increasing those values actually do and how to utilize them. Please help me out for I'm frustrated.

Edit: i've been benching tRTP:12T, tWR:24T, tRFC1/2/4:288/214/132T while typing out this message, result is that the performance dropped slightly compared to the 2nd screenshot.


----------



## sealxohd

Veii said:


> It was "legendary score" but they nerved it ~ booring


I think they nerved just the tooltip 🤣 

I had to rerun the bench with slighty more VRAM clock for a legendary score to get the achivement.

I have a potato 5700XT


----------



## ManniX-ITA

Couldn't resist, ordered these 









Custom RAM copper heatsinks for DDR5 / DDR4 - Bartxstore


Custom made copper RAM heatsinks for memory extreme overclocking using dry ice or LN2. Designed for DDR4 and DDR5 memory




bartxstore.com


----------



## Veii

sealxohd said:


> I think they nerved just the tooltip 🤣













ManniX-ITA said:


> Couldn't resist, ordered these
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Custom RAM copper heatsinks for DDR5 / DDR4 - Bartxstore
> 
> 
> Custom made copper RAM heatsinks for memory extreme overclocking using dry ice or LN2. Designed for DDR4 and DDR5 memory
> 
> 
> 
> 
> bartxstore.com


They once where for 60€ (quote me on that, but i am nearly confident)
Now that demand increased he increased prices
But copper prices increased too~~


----------



## Veii

Subut said:


> Last week while playing god of war 2018, a stick of ram suddenly decided to die which was unfortunate. I RMA'd the kit hoping for the best. Now that I'm left with a pair of single rank sticks I taught it would be a good opportunity to try clocking SR with b-die for the first time. You know, glass half full kinda deal


It would've been interesting to use the experience and learn what you run to kill A0 Vipers
All of my main scores are on A0 (many, not all)
You have RTTs ready to use and powering as a whole


Subut said:


> So, seeing that many of my times are a long way away from what I've got with DR it seems there's a problem. After reading many pages from this thread I think my problem is that I don't know jack about the impedances. I don't know how to tune the ohm values there and I have a strong suspicion that there's my problem.


Maybe


----------



## ManniX-ITA

Veii said:


> They once where for 60€ (quote me on that, but i am nearly confident)
> Now that demand increased he increased prices
> But copper prices increased too~~


If I knew before, I'd have buy it for 60 € 
Think you are right, more demand and copper price going up. Deadly combo...


----------



## andremoreira6215

Hey guys this is my last improvements, since with Google ram calculator from veil, it show me some desyncronized timings. After a little changes I got some improvements. This passed tm5 usmus config 25 passes. 









Do you guys any recommendations? I will give another pass on tm5 to screenshot to put it on zen4 oc leaderboards








Vddp: 0.900v
IOD : 1.060v
Ccd: 0.940v


----------



## Subut

Veii said:


> It would've been interesting to use the experience and learn what you run to kill A0 Vipers


You mean like it would have been smart to investigate the dead stick?

edit: thanks for the reply, okay now I think i get what you mean. as in investigate the settings I ran.


----------



## Veii

Subut said:


> edit: thanks for the reply, okay now I think i get what you mean. as in investigate the settings I ran.


That , and a hint to copy my settings - as we have the same dimms
The work has been done already for you
Zen DDR4 OC Leaderboards here included, couple of presets
But current found powering is better


----------



## Bloax

andremoreira6215 said:


> Do you guys any recommendations? I will give another pass on tm5 to screenshot to put it on zen4 oc leaderboards
> View attachment 2546302
> 
> Vddp: 0.900v
> IOD : 1.060v
> Ccd: 0.940v


Personally then I'm curious if RTT Nom/6, Wr/3 and Park/6 would run, alongside 1.9v on the 1.8v line to run procODT 30* like a Cool Kid and enjoy the RRDL 4-5 + WTRL 8-10 Experience on single-rank sticks.

* - bear in mind that doing either, or both, of these will likely result in vDIMM requirements lowering a little

Bruteforcing SOC/IOD/CCD voltages to minimize fabric corrections would also be an option, though that is a _very_ boring multi-hour Watch Paint Dry session.


----------



## PJVol

Luggage said:


> like this?


Yeah, thanks. I just wished you didn't forget to push TDC limit back, so half of your data actually showed it hit, otherwise it would be FIT (i.e. VOLTAGE). And by capping the EDC, it's mostly CCA that drives the global frequency, that seemed to suggest it is, in turn, EDC driven.


----------



## Luggage

PJVol said:


> Yeah, thanks. I just wished you didn't forget to push TDC limit back, so half of your data actually showed it hit, otherwise it would be FIT (i.e. VOLTAGE). And by capping the EDC, it's mostly CCA that drives the global frequency, that seemed to suggest it is, in turn, EDC driven.
> View attachment 2546325





http://imgur.com/a/wWjlnX2


Didn't think about that - just adjusted my high EDC profile.
This should be better.


----------



## PJVol

Luggage said:


> Didn't think about that - just adjusted my high EDC profile.
> This should be better.


Yeah, it is. But still CCA throttle predominates. What if you set EDC limit, let's say to ~125-130A ?

Btw, (i saw MSI board on your screenshot somewhere) have you got something like "relax EDC throttle" option there in a bios, and what it is set to atm?


----------



## Bloax

blodflekk said:


> Whelp, that was a fail. Went to 1.6 vDIMM and still couldn't budge anything, tWR/tRTP still 14/7


Minimum (sometimes, also _maximum_ for Troll-tastic memory) tRTP and tWR are purely PCB-related, so I wouldn't worry about that.


----------



## Luggage

PJVol said:


> Yeah, it is. But still CCA throttle predominates. What if you set EDC limit, let's say to ~125-130A ?
> 
> Btw, (i saw MSI board on your screenshot somewhere) have you got something like "relax EDC throttle" option there in a bios, and what it is set to atm?


"relax edc throttle" - Not that I know of.



http://imgur.com/a/sVHmrAA

130-170 edc

PPL is 350W and vcore offset + 0.0125V. Otherwise I'd say pretty normal PBO with CO.


----------



## Bloax

Pardon the question - I haven't been following this thread closely, and _it's a very large one_ -
But are you people discovering something new, or rediscovering the fact that PB/PBO are always EDC-capped and that only static frequencies can bypass it?








Because yes, that's a thing, and it is a rather annoying Thing if you wish to get any performance out of FCLKs beyond 1900 or just plain-old high CPU frequency.

Since as you may guess, not all workloads can handle the same voltage/frequency - particularly towards the maximum frequency the CPU wants to run at ambient temperatures.


----------



## Audioboxer

ManniX-ITA said:


> I've managed to get FCLK 2000 stable with the AGESA 1.2.0.5; temperatures are higher and this hurts all long running MT tests like Corona, Linpack and the monero miner.
> Some others doesn't like CPU-z and CB23, results are inline with the AGESA 1.2.0.1.
> 
> On others like Geekbench the new memeory profile thanks to the improved memory controller gives a small boost.
> I wasn't able to reach 19500 in GB5 MT earlier.
> The new RTT 7/2/6 really helps and memory runs 1c lower when under TM5 reach thermal equilibrium.
> 
> View attachment 2546264
> View attachment 2546265
> 
> 
> I need VDDP at 1000mV to run 4000CL14 with these timings, otherwise 3 beeps and memory overclocking failed message.
> Previous AGESA would boot with 900mV but it wouldn't get stable and tRCDRD lowest possible was 16 (although I didn't try 7/2/6).


Is that 1.25v VSOC with droop?

Might have a play with FCLK 2000. Never been able to stop my USB disconnects though.

AGESA 1.2.0.5 stopped the weird mouse pointer lag I used to get when the CPU stability tests were running, but a USB disconnect would still happen.


----------



## Veii

Bloax said:


> Pardon the question - I haven't been following this thread closely, and _it's a very large one_ -
> But are you people discovering something new, or rediscovering the fact that PB/PBO are always EDC-capped and that only static frequencies can bypass it?
> View attachment 2546339
> 
> 
> Because yes, that's a thing, and it is a rather annoying Thing if you wish to get any performance out of FCLKs beyond 1900 or just plain-old high CPU frequency.
> 
> Since as you may guess, not all workloads can handle the same voltage/frequency - particularly towards the maximum frequency the CPU wants to run at ambient temperatures.


Half half
EDC hardcap doesn't exist as an amperage value anymore
Anything around it was made to "accidentally" reach the same amperage value

Most of the throttle is either voltage max throttle (hitting higher requested value for a short period of time than allowed maximum limits)
Some is then powerlimit that goes into lowering max voltage, soo point 1 get's applied again
Or another one on 5600X is, hitting 65° for a fraction of a sec lower than 10ms, and point 1 get's applied again and throttles back
* as maximum voltage "allowed" shrinks and shrinks by external reasons

What user can do, is undervolt as best as possible, soo this first case won't happen
But the worse a sample is, the higher voltage FIT will think it likes to request ~ and soo the worse the problem
Then add to this story that every +25mhz Boost override = -2 CO to balance it down , hence higher V/F strap amplifies the VID request
Aand we have the same thing working against you.

It's pretty much the same thing you said, but in modified phrasing
User has to work against PB2 , to tame voltage requests as best as they can, hence voltage limits are fixed & everything will do it's best to lower these maximum limits, soo you'll suffer by lower frequency
Well metaphorically exaggerated. But all on all, about what's happening 🤭 
"Do anything to prevent the boosting system from throttling your maximum allowed voltage. It matching an EDC Peak limit, is pure coincidence. One that is always the case, but a coincidence."
Also welcome to the forum Bloax ! 😇









EDIT:
Forgot to add another one,
Changed voltage limits on 1205, which are unique between 5600X,5800X,5900X
Generally all goes again to point 1
Preventing to be either thermal base, throttled on maximum allowed freq (by max-voltage throttle), or power-based throttle with the same outcome

EDIT 2:
We have not added to the FCLK problem, autocorrection and similar type of throttles ~ independent of core freq 
High FCLK just has a sideproduct issue, of eating a lot in the powerbudget & so ruining people's boost stronger with limiters
But without limiters, some bad samples can not tame the voltage request (throttle) and perf is worse


----------



## Bloax

Audioboxer said:


> Is that 1.25v VSOC with droop?
> 
> Might have a play with FCLK 2000. Never been able to stop my USB disconnects though.


My favorite way to approach it is to run y-cruncher FFT on four threads (even better if four cores with SMT off) alongside running a LatencyMon measurement for 5-8 minutes for a given voltage loadout,
then keep track of these bits from the Stats tab:


Code:


Highest measured interrupt to process latency (µs):   [preferrably below 500]
Average measured interrupt to process latency (µs):   [usually the lowest is the best-performing, not always though!]

Highest measured interrupt to DPC latency (µs):       [preferrably below 500]
Average measured interrupt to DPC latency (µs):       [higher is usually not better, but don't get discouraged - it might improve again a few steps further up/down]


REPORTED DPCs
_________________________________________________________________________________________________________
DPC routines are part of the interrupt servicing dispatch mechanism and disable the possibility for a process to utilize the CPU while it is interrupted until the DPC has finished execution.

Highest DPC routine execution time (µs):              94.755570
Driver with highest DPC routine execution time:       dxgkrnl.sys - DirectX Graphics Kernel, Microsoft Corporation

Highest reported total DPC routine time (%):          0.051902
Driver with highest DPC total execution time:         Wdf01000.sys - Kernel Mode Driver Framework Runtime, Microsoft Corporation

Total time spent in DPCs (%)                          0.057306

DPC count (execution time <250 µs):                   19769
DPC count (execution time 250-500 µs):                X           <-
DPC count (execution time 500-1000 µs):               Y        <-- Also
DPC count (execution time 1000-2000 µs):              Z    <---- Keep track of those
DPC count (execution time 2000-4000 µs):              0              they are important, even if the exact Number is chaotic - lower major spikes is a sign of improvement
DPC count (execution time >=4000 µs):                 0                   and no massive fabric dropouts should be possible









(I don't have a better screenie on hand, as I post this from a 12700k system I built from an accounting error to lrn2vroom that platform :' ))


You can use fft-bat.txt as a .bat file in the same folder as y-cruncher.exe, then use a shortcut to it on your desktop for convenience.
Just make sure to dump FFT-fclk-test-cfg into the same folder, and probably call it FFT-fclk-test.cfg instead, or just change the name in the .bat file.

Launching LatencyMon each reboot and pressing Start isn't a big hassle, so it's not particularly worth trying to automate (as copying the Stats bits is, still, manual labour)


The truly annoying part is having to do this with a bazillion reboots - as setting IOD/CCD voltage in-OS isn't a thing, and even vSOC is not necessarily adjustable outside of the BIOS.
So you're potentially staring down going through CCD 1.0-->0.8v in 0.01v steps, IOD 1.15<--1.05-->1.0v in 0.01v steps, and vSOC 1.3<-1.1->1.05v in likewise small steps.. Individually, and then together with promising combinations!

🤡ha 🤡hah🤡 ha🤡

good times


----------



## blodflekk

Are there any guides for DDR4 on zen 3? I'm really struggling to make sense of how to get the performance I want. As I go higher in frequency, I'm unable to run timings that were stable at lower frequencies even with significantly more vDIMM (1.48v vs 1.65v) (3600vs3800) which to my caveman level of understanding means I'm not being limited by voltage. I don't actually understand how resistances, proc, drive strengths actually work and when to adjust and in which direction to adjust. I've taken lots of advice on settings that "should" be suitable for my kit, read the OC leaderboard and I am feeling really lost.


----------



## ManniX-ITA

Audioboxer said:


> Is that 1.25v VSOC with droop?


That's 1.2125V set in BIOS with Override Mode.
LLC Auto and PWM 1000 kHz.


----------



## ManniX-ITA

Audioboxer said:


> Might have a play with FCLK 2000. Never been able to stop my USB disconnects though.


I can send you the settings I'm using with A45, could be a start.
But FCLK 2000 on AGESA 1.2.0.5 it's not really reliable.
I'm going to test with 1.2.0.3 now and if it's not as good as 1.2.0.1 then I'll go back to A21O.


----------



## Audioboxer

ManniX-ITA said:


> I can send you the settings I'm using with A45, could be a start.
> But FCLK 2000 on AGESA 1.2.0.5 it's not really reliable.
> I'm going to test with 1.2.0.3 now and if it's not as good as 1.2.0.1 then I'll go back to A21O.


The problem for me on anything other than AGESA 1.2.0.5 is the mouse pointer jerk/lag/unresponsiveness. Other thing I noticed is the very loud VRM noise I'd get under load, on AGESA 1.2.0.5 I don't hear the VRMs.

This is when running OCCT or y-cruncher and doing CPU stability tests.

I have absolutely no idea why AGESA 1.2.0.5 performs better for me on those two issues, but it does, whatever AMD changed. Anything below 1.2.0.5 is basically unusable for be above 1900 FCLK, even 1933. 1.2.0.5 shows some promise but I couldn't quite get there, still seeing USB disconnects under heavy load.


----------



## Audioboxer

ManniX-ITA said:


> @Audioboxer
> 
> You missed the asterisk
> 
> View attachment 2546263
> 
> 
> For 32GB full coverage is around 11000%, I usually go over 14000%.












Rather than running 7/2/6, I think I'm quite happy running 7/3/4.


----------



## Taraquin

ManniX-ITA said:


> I've managed to get FCLK 2000 stable with the AGESA 1.2.0.5; temperatures are higher and this hurts all long running MT tests like Corona, Linpack and the monero miner.
> Some others doesn't like CPU-z and CB23, results are inline with the AGESA 1.2.0.1.
> 
> On others like Geekbench the new memeory profile thanks to the improved memory controller gives a small boost.
> I wasn't able to reach 19500 in GB5 MT earlier.
> The new RTT 7/2/6 really helps and memory runs 1c lower when under TM5 reach thermal equilibrium.
> 
> View attachment 2546264
> View attachment 2546265
> 
> 
> I need VDDP at 1000mV to run 4000CL14 with these timings, otherwise 3 beeps and memory overclocking failed message.
> Previous AGESA would boot with 900mV but it wouldn't get stable and tRCDRD lowest possible was 16 (although I didn't try 7/2/6).


Still WHEA 19 or did 1.2.0.5 resolve that?  Does linpack\y-cruncher scale above 3800\1900 or do you get lower perf above 3800\1900 like me? (1-2%).


----------



## Kha

Veii said:


> If you guys figure out more #2 error data ~ please let me know
> There is close to zero holding point on that one specific
> 
> Same for lack on #10
> While it is requiring more RTT_NOM , as CKE (ripple) issue on higher voltage
> Soo to speak "burst voltage test" ~ it's lacking information on how to fix it as "standalone" issue
> ~ sadly mostly comes together with #0 or with #2. Also sadly #2 has no holding point to fix both
> 
> Generally updating Error logs slowly
> @PJVol if you have more findings, also let me know. Added your #13 reason
> Couldn't replicate yet, but it will be helpful to somebody for sure
> 
> Also PJVol, i listened on tRFC2/4 rounding issues
> Reason is, that it was now replicable and matches DR JEDEC
> ~ still WIP, but there are specific scenarios where it matches and is needed
> Still marked as WIP/DEBUG, because on the contra side ~ there are specific times where this does not match reality.
> Anywho both options are there ~ ty for the finding, back then
> ==========
> Sneak Peak
> View attachment 2535189
> View attachment 2535191
> 
> ~ sub average sample, unlucky ~ BG 2143 SUS = guanteed Rev.02 (2139 is not)
> ~ likely lack of bios support, it's overvolted too much again
> 
> CTR & Hydra lack support for B2 ~ but that's fixed now, just not upstream yet
> It's Microcode 00A20F*12h* not *10h*
> Sadly requires new SMU ~ AMD OC commands/menu don't go through, mailbox do
> Requires 1.2.0.5 and final microcode, not reviewer one but works since 1.1.0.0D
> View attachment 2535190
> 
> More data about DPM and WHEA , to follow
> First having to figure out #2 error on DR & then check silicon voltage scaling
> * If there are any significant behavior changes ~ i'll open a thread for B2 owners.
> Have it only for 3 more days ~ can't promise much debugging


Veii, what about BG 2142 SUS ? Do you know if it's B2 or not ?


----------



## Taraquin

blodflekk said:


> Are there any guides for DDR4 on zen 3? I'm really struggling to make sense of how to get the performance I want. As I go higher in frequency, I'm unable to run timings that were stable at lower frequencies even with significantly more vDIMM (1.48v vs 1.65v) (3600vs3800) which to my caveman level of understanding means I'm not being limited by voltage. I don't actually understand how resistances, proc, drive strengths actually work and when to adjust and in which direction to adjust. I've taken lots of advice on settings that "should" be suitable for my kit, read the OC leaderboard and I am feeling really lost.


It depends on binning of your ram mostly. For me the DrvStr and ProcODT I need for 1T no gdm works fine at both 3600, 3800 and 4000, but I must relax some timings going up. Generally on B-die you must loosen the 3 primaeris by 1 for each 200MHz you raise speed if you want to stay on same voltage. 3600flat 14 works at 1.48V, 3800cl15 works at 1.47v and 4000cl16 works at 1.46v on my setup.RC and RFC must be loosened percentagewise similar so if RC 42 and RFC 264 works at 3800, then you need RFC 280 and RC 44\45 on 4000. Since the prims and RC\RFC scales with voltage you can often run same timings up to a certain point if you rasie voltage, but depending on binning it might not work. Some people can`t get RCDRD below 16 at 3800 no matter what volt they use, others can do 14 at 1.5V.

They only timings I have to raise going from 3600 to 4000 is CL (CWL since it`s derived from CL), RCDRD, RP, RC, RFC and WTRL for some reason (8 works on 3800, but 4000 needs 9), all others are kept the same, but I must keep voltage below 1.5V due to insufficient cooling of ram.


----------



## ManniX-ITA

Taraquin said:


> Still WHEA 19 or did 1.2.0.5 resolve that?  Does linpack\y-cruncher scale above 3800\1900 or do you get lower perf above 3800\1900 like me? (1-2%).


No changes in WHEA.
I get lower perf in almost anything which is topping CPU temperature, even with 1.2.0.1.
With 1.2.0.5 is worse as the temperatures are higher.
Still running this with air cooling.
y-cruncher short Pi are scaling up but that's more about memory latency than bandwidth.


----------



## blodflekk

Taraquin said:


> It depends on binning of your ram mostly. For me the DrvStr and ProcODT I need for 1T no gdm works fine at both 3600, 3800 and 4000, but I must relax some timings going up. Generally on B-die you must loosen the 3 primaeris by 1 for each 200MHz you raise speed if you want to stay on same voltage. 3600flat 14 works at 1.48V, 3800cl15 works at 1.47v and 4000cl16 works at 1.46v on my setup.RC and RFC must be loosened percentagewise similar so if RC 42 and RFC 264 works at 3800, then you need RFC 280 and RC 44\45 on 4000. Since the prims and RC\RFC scales with voltage you can often run same timings up to a certain point if you rasie voltage, but depending on binning it might not work. Some people can`t get RCDRD below 16 at 3800 no matter what volt they use, others can do 14 at 1.5V.
> 
> They only timings I have to raise going from 3600 to 4000 is CL (CWL since it`s derived from CL), RCDRD, RP, RC, RFC and WTRL for some reason (8 works on 3800, but 4000 needs 9), all others are kept the same, but I must keep voltage below 1.5V due to insufficient cooling of ram.


And this backs up what I've heard that most timings should remain possible as frequency increases, however on my 2x16gb b die, I'm not getting the same results. Hence my question about proc, rtt, drive strengths. Is there a method you should follow for determining what these values need to be for your system ?


----------



## ManniX-ITA

Audioboxer said:


> I have absolutely no idea why AGESA 1.2.0.5 performs better for me on those two issues, but it does, whatever AMD changed. Anything below 1.2.0.5 is basically unusable for be above 1900 FCLK, even 1933. 1.2.0.5 shows some promise but I couldn't quite get there, still seeing USB disconnects under heavy load.


From what I see most recent production works better with AGESA 1.2.0.5.
Same for B2 stepping.
Mine is one of the first production batch and works better with 1.2.0.1.
I'm testing now with 1.2.0.3a and despite performances are almost there both my CCDs are idling at 37-38C instead of 33-34C...
Which of course has a small negative impact on single core boosting. Puzzling!


----------



## ManniX-ITA

blodflekk said:


> And this backs up what I've heard that most timings should remain possible as frequency increases, however on my 2x16gb b die, I'm not getting the same results. Hence my question about proc, rtt, drive strengths. Is there a method you should follow for determining what these values need to be for your system ?


AFAIK nope.. hundreds of reboots testing all the possible combinations seems to be the only way.
There's a pretty defined set of RTTs and ranges in termination to try first but it can be very specific.


----------



## Taraquin

blodflekk said:


> And this backs up what I've heard that most timings should remain possible as frequency increases, however on my 2x16gb b die, I'm not getting the same results. Hence my question about proc, rtt, drive strengths. Is there a method you should follow for determining what these values need to be for your system ?


Unfortunately no. High end motherboards can sometimes work it out good on auto, budgetboards like mine has default values like ProcODT 40 and DrvStr 24-24-24-24 which gave me loads of errors running 1T, but worked fine at 2T and GDM. Changing to ProcODT 28 and 40-20-30-24 made 1t totally stable for me. 

For me they do not change going from 3600 to 4000, for others they change. For some it seems a bit higher ProcODT can help when going higher. Are you sure your ram just won`t budge on for instance RCDRD? That is usually the timings that must be raised when passing certain speeds. RP can also be a timing that just won`t go lower on certain speeds, and for me WTRL is a ***** above 3800.

For many it seems DrvStr 40 20 24\30 and 20\24 seems to work good with 1T, On dual rank you must often mess with Rtts aswell complicating things, SR usually likes 28-37 ProcODT while DR likes a bit higher ProcODT, but a few select can run 28 even with 3800 and tight DR.

Post your current Zentimings and we can try to give suggestions? Also TM5 with usmus somewhat sorts out what is the problem (though a bit inaccurate, but it is usually good at telling if volt is too low, rfc is too low and a few others).


----------



## blodflekk

ManniX-ITA said:


> AFAIK nope.. hundreds of reboots testing all the possible combinations seems to be the only way.
> There's a pretty defined set of RTTs and ranges in termination to try first but it can be very specific.


Has anyone taken the time to document this process so I have a starting point to work from ?


----------



## Audioboxer

ManniX-ITA said:


> From what I see most recent production works better with AGESA 1.2.0.5.
> Same for B2 stepping.
> Mine is one of the first production batch and works better with 1.2.0.1.
> I'm testing now with 1.2.0.3a and despite performances are almost there both my CCDs are idling at 37-38C instead of 33-34C...
> Which of course has a small negative impact on single core boosting. Puzzling!


I've got a B0 chip!

I tried nearly all the AGESA prior to 1.2.0.5, every single one of them had the same issue for me above 1900 FCLK, no matter what voltages or BIOS settings were used. Any time a CPU stress stability app was in action, the mouse pointer would become unresponsive and the VRMs would sing. Followed very quickly by USB going crazy.

1.2.0.5 fixes the mouse pointer issues and quietens the VRMs, and some OCCT testing did have the USB disconnects taking a bit alonger, but y-cruncher can still get them coming out in less than a minute. Often less than 20~30 seconds.


----------



## blodflekk

Taraquin said:


> Unfortunately no. For me they do not change. For some it seems a bit higher ProcODT can help when going higher. Are you sure your ram just won`t budge on for instance RCDRD? That is usually the timings that must be raised when passing certain speeds.
> 
> For many it seems DrvStr 40 20 24\30 and 20\24 seems to work good with 1T, On dual rank you must often mess with Rtts aswell complicating things, SR usually likes 28-37 ProcODT while DR likes a bit higher ProcODT, but a few select can run 28 even with 3800 and tight DR.


Ok, seems like back to the drawing board for me then. Yes tRCDRD is stuck at 15 on 3800, but there are other secondaries that aren't as tight as they should be. 1T is a pipe dream at the moment, trying to get everything else sorted on 2T gdm off first, which that alone would satisfy me.


----------



## ManniX-ITA

Oh really nice, **** you AMD.
Seems AGESA 1.2.0.5 permanently "damaged" my 5950X.
I'm back at 1.2.0.1, loaded my saved profile from USB and still have 5C more in idle.
If it wasn't as bad as AMD or even worse, I'd go back to Intel.


----------



## Taraquin

blodflekk said:


> Ok, seems like back to the drawing board for me then. Yes tRCDRD is stuck at 15 on 3800, but there are other secondaries that aren't as tight as they should be. 1T is a pipe dream at the moment, trying to get everything else sorted on 2T gdm off first, which that alone would satisfy me.


Why not try getting 1t stable at relaxed timings, then tighten up? Try 16-16-16-32-48, 288 rfc, 4-6-16 rrd\faw, 12\6 wr\rtp, 4\12 wtr, 9 rdwr, 3 wrrd, scl`s 4.


----------



## blodflekk

Taraquin said:


> Why not try getting 1t stable at relaxed timings, then tighten up? Try 16-16-16-32-48, 288 rfc, 4-6-16 rrd\faw, 12\6 wr\rtp, 4\12 wtr, 9 rdwr, 3 wrrd, scl`s 4.


I've done most of that, I have established a stable baseline, I'm trying to tighten now. wr\rtp is stuck at 14/7 wrrd is at 12.


----------



## Subut

Veii said:


> But current found powering is better


I didn't quite catch that. Meaning the powerings included in the leaderboard are better than mine or meaning there now are better powerings than those in the leaderboard.


----------



## Audioboxer

ManniX-ITA said:


> Oh really nice, **** you AMD.
> Seems AGESA 1.2.0.5 permanently "damaged" my 5950X.
> I'm back at 1.2.0.1, loaded my saved profile from USB and still have 5C more in idle.
> If it wasn't as bad as AMD or even worse, I'd go back to Intel.


Can that even happen?! 

I do recall @Veii suggesting something about once the microcode? is updated it cannot be reversed. So maybe going to 1.2.0.5 permanently changes something in the chip FW that will result in different boosting behaviour even if you rollback firmware.

But I do agree AMD is an absolute mess when it comes to AGESA, chipset drivers and anything to do with software.


----------



## ManniX-ITA

Audioboxer said:


> Can that even happen?!


Yes it can...
I've seen more than a few testing the new AGESA and no one reported permanent changes.
Guess it's a matter of luck.



Audioboxer said:


> I do recall @Veii suggesting something about once the microcode? is updated it cannot be reversed. So maybe going to 1.2.0.5 permanently changes something in the chip FW that will result in different boosting behaviour even if you rollback firmware.


Not the microcode but other stuff like the PSP FW.

Oh my... the CCD temperatures going up and down it was nothing.
It's a ****ing mega-memory-saster.
Couldn't believe it so I've loaded again the original USB profile but no, it's true.
Now my DIMMs are topping 62C under test with TM5.
Sixty-two-celsius-degrees damn.
This exact profile the day before yesterday was topping 56.6C in over one hour.
Had to check the fans with my own eyes but they are all running...

I'll probably have to go back to the nice AGESA 1.2.0.5


----------



## Mach3.2

Audioboxer said:


> Can that even happen?!
> 
> I do recall @Veii suggesting something about once the microcode? is updated it cannot be reversed. So maybe going to 1.2.0.5 permanently changes something in the chip FW that will result in different boosting behaviour even if you rollback firmware.
> 
> But I do agree AMD is an absolute mess when it comes to AGESA, chipset drivers and anything to do with software.


I believe something popped on my 5900X too after I POSTed 3733 pure 1T 15-15-15 on those dual rank 3200 CL14 B-die sticks. Granted it's was quite unstable and it immidiately shut off the moment I ran AIDA, but I can never get to post that setting anymore even on better binned 3600 14-15-15 with setup timings added.


AMD definitely need to throw more money into their software like Intel and Nvidia. Powerful hardware isn't of much use if the software interfacing with the hardware isn't up to snuff.


----------



## ManniX-ITA

ManniX-ITA said:


> It's a ****ing mega-memory-saster.
> Couldn't believe it so I've loaded again the original USB profile but no, it's true.
> Now my DIMMs are topping 62C under test with TM5.
> Sixty-two-celsius-degrees damn.
> This exact profile the day before yesterday was topping 56.6C in over one hour.
> Had to check the fans with my own eyes but they are all running...


Well at least the high memory temperature was my own doing...
Instead of saving a screenshot in the DigitALL menu, which I noticed was missing, I've changed the 12V OCP Expander.
It's one of those options promising miracles and instead creating a mess.
Of course I saved the profile on USB after taking the screenshots... lesson learned. Do it first 

But for the CCD temperatures no fix.
They keep bouncing like crazy between the highest core temperature and +5C, continuously up & down.


----------



## Bloax

Personally then I'm optimistic for AM5, as the fundament of the platform will not have been developed in the nadir of the company's financial history, on a hearthy diet of shoestring and old shoe leather.

i.e. It will be less rushed (WE'RE GOING OUT OF BUSINESS LOL), and they can afford more people testing it for silly things.
And it was developed after AM4 has revealed all its shortcomings, which might help too!

Thus you should be hopeful that most of them are addressed!










blodflekk said:


> Has anyone taken the time to document this process so I have a starting point to work from ?


From experience I can tell you that:

1) A high memory frequency (~3800 dual-rank,~4000 single-rank) is best for revealing "good" RTTs*, as truly suboptimal ones _won't POST at all_. Which means about 40 sec per attempt.
Just make sure to write down working combinations on a piece of paper or something. 
* (This is true of AM4 and LGA1700)

2) The exact RTTs the sticks can run at all, depends on the motherboard - if you're particularly unfortunate, your board may not be able to run the settings the sticks demand.
(the Unfortunate Scenario I've only seen trying to help a friend on a z370 Gigglebyte board that _doesn't even expose procODT_)

For example, the same dual-rank tridentz non-rgb 3200 14-14-14 sticks would want Nom/6, Wr/3, Park/3 on a crystal-oscillator-between-CPU-and-DIMMs Asscock x570 ITX board - but could go beyond Park/3 on a b550 Unify-X;








3) Sometimes Mystery Errors on tm5_1usmus3 #10 (and others I can't recall) are related to RTT Wr, others for Nom/Park, it's a weird spidey-sense thing you might develop from bruteforcing RTTs.

And again I'd like to remind that RTP/tWR are purely down to the RAM PCB - concepts like "RTP 5, tWR 10" being "extreme" are misconceptions, as I have a kit that has a _maximum_ RTP/tWR of 5/10 and refuses to work properly with anything higher.


----------



## Veii

ManniX-ITA said:


> Oh really nice, **** you AMD.
> Seems AGESA 1.2.0.5 permanently "damaged" my 5950X.
> I'm back at 1.2.0.1, loaded my saved profile from USB and still have 5C more in idle.
> If it wasn't as bad as AMD or even worse, I'd go back to Intel.


Outch~
I don't trust them exactly about such changes
But it very well can be an MSI bios issue


ManniX-ITA said:


> I've seen more than a few testing the new AGESA and no one reported permanent changes.


I haven't heard that most people think this is a thing at all.
You potentially can force PSP-FW to revert back by big AGESA jumps, but i've only managed it once ~ and only because i corrupted it by memOC & couple failed initialization attempts ^^''


ManniX-ITA said:


> I'll probably have to go back to the nice AGESA 1.2.0.5


Before doing so, can you drop a screenshot of ZenPTMonitor
Do you have an HW-ROM Flasher next to you ?
If possible and your bios profiles are not valuable or already gone, can you update from 1203C to 1205 with AFUWIN
This one in specific













Aptio_V_AMI_Firmware_Update_Utility.zip







drive.google.com






ManniX-ITA said:


> Instead of saving a screenshot in the DigitALL menu, which I noticed was missing, I've changed the 12V OCP Expander.
> It's one of those options promising miracles and instead creating a mess.
> Of course I saved the profile on USB after taking the screenshots... lesson learned. Do it first


Can you expand a bit ?
The option is missing on the new bioses, or it has different behavior ?
Same goes for VDD18 ?

If anything of both changes, RTTs will "again" be wrong fully ~ same as procODT behavior
Here it's more a matter of "what" changed ~ now PSP-FW aside (that's encrypted and maybe OrangeCSM's tools, can only decode it)

I'm more writing you here, to ask if you're willing to be a testing rabbit for newer SMU on AGESA 1206
Hence you've already updated, it shouldn't cause such a big mess & maybe can even fix couple of things
Makes me wonder why the MSI modding community hasn't done it yet ~ but it should be 1:1 transplantable
I can try, but want you to have a fallback recovery option - as it might not post. 


Kha said:


> Veii, what about BG 2142 SUS ? Do you know if it's B2 or not ?


Soo it seems information changed again slightly
I can't say.
Early on it was easier to guarantee new batches ~ but now it appears that AMD pushed B0's out till 2149
Yet all of them had odd voltage behaviors in them
What i can see, is that either they have shipment issues (substrate missing) or they intentionally didn't put the B2 mark on them, soo it would sell faster (to gather more debug data)#
All on all, it seems like there are couple "new" samples out there, marked still as B0 ~ soo i can not guarantee anymore that it's a new one.
"Technically" they shouldn't even be allowed to be sold , but hence couple of people got them by accident, the restriction lifted
And AGESA 1.2.0.5 was pushed too early and needs patching.

I think, we users who got them, pushed AMD a bit too much with it. They shouldn't have released that early, although everything manufactured after the start of October ~ should be on the new substrate
Add one more month global delivery time ~ and usually it was 2140+
Tho had as written above 2141 samples which showed the same voltage behavior as B2, but marked B0
And seen now people get 2149 samples which are not B2 , for 5800X and onwards
Soo i can not tell anymore. Something with supply happened it seems like


----------



## PJVol

Veii said:


> But it very well can be an MSI bios issue


So it should be **** you MSI then? 
Just flashed MSI B450M with a 1205 and then back to 1203C to compare, on my 5700G.
VID limit is not changed, 1.465V as before.
Performance is ~ the same.


----------



## Veii

PJVol said:


> So it should be **** you MSI then?


The 12V OCP Expander Part
But rather the part where MSI pushed early on testing bioses, community modded them, newer "public" beta was then different than old chiphell "leaks" that got modded
This "maybe an msi issue" part
But i can't understand the problem fully from the post. Something changed, maybe , likely even
But what is the difference after downgrading. Can't understand the post and asked about more information


----------



## Kha

Veii said:


> Soo it seems information changed again slightly
> I can't say.
> Early on it was easier to guarantee new batches ~ but now it appears that AMD pushed B0's out till 2149


I can get a 5900x BG 2143SUS and I see everyone reports it as a B2, any change might be a B0, what do you think ?


----------



## Kha

Veii said:


> BG 2143 SUS = guanteed Rev.02


So, are we still sure of this BG 2143SUS being B2 or no more ?


----------



## Veii

Kha said:


> So, are we still sure of this BG 2143SUS being B2 or no more ?


No more, as explained
While substrate changes seem to happen (have happened) on anything past october
The "branding" of the same can still be B0 on newer ones
A 5900X 2143SUS "should" be the new batch.
But things have shifted around and supply "appears" to be lacking

Or whatever the reason it is AMD brands some new samples still as B0
Anywho, i can't guarantee it anymore. Things changed as it seems
Sadly also the BG2143SUS i had, was a lemon sample. Well silver/bronze, but compared to the other platin/gold, this one was a failure and did not run well on AGESA 1203C
1205 didnt exist at this time

Maybe just wait it out
2-3 weeks more to increase your chance
I/we needed 3 weeks and a lot of business calls to get something that now appears as "wasnt allowed to be sold"
* since October the attempt's

Just wait out or try your luck and return it
I wouldn't gamble anything bellow 2143
Although now 2149 ones can be B0 too, for whatever reason


----------



## domdtxdissar

domdtxdissar said:


> i will report back how it goes!
> In the meantime, i'm trying something new
> 
> 
> 
> 
> 
> 
> 
> 
> 
> It cant get worse, i hope atleast
> Stock heatsink on Trident Z are brushed aluminum, so i thought what the hell, lets just overdo it on the outside to try to compensate for little spacing between the sticks on this 2dimm board


Project ram cooling version 2, *overkill edition* 🤣

Replaced the stock Trident Z heatsinks with EK RAM Monarch + W/mK=12.5 pads
Aaaaand a bunch of extra heatsinks 









































Starting testmem5 1usmus burn-in to check temperature delta between idle and load on this cooling setup 😎


----------



## dk_mic

domdtxdissar said:


> Project ram cooling version 2, *overkill edition* 🤣


love it

about B2: for what it's worth, i have a 5950x B2 received directly from AMD (Netherlands) as RMA return, its 202201 SUS.
posted about my findings in the Dual CCD oc thread. 








OFFICIAL 5900X and 5950X two chiplet Zen 3 CPUs...


The baseline would be the Windows drivers. Testing and following the chipset driver versions can be time-consuming, in my opinion. If the cpu perform well with the Windows drivers, and it does over a long period of time. I just remember, when I got the chip in December 2020, I had a serious...




www.overclock.net




still not 100% sure how to treat it right, but 1.2.0.5 seems better for it.


----------



## Veii

dk_mic said:


> , i have a 5950x B2 received directly from AMD (Netherlands) as RMA return, its 202201 SUS.


BG 2201 SUS ? 
PGS or maybe not even BG anymore ?
Ty for posting~


----------



## nada324

Hey all, just got error #6 after few cycles, mean TRFC is wrong??

Vdimm @1.52v


----------



## Kha

Veii said:


> BG 2201 SUS ?
> PGS or maybe not even BG anymore ?
> Ty for posting~


Maybe misstype ?


----------



## Bloax

nada324 said:


> Hey all, just got error #6 after few cycles, mean TRFC is wrong??
> 
> Vdimm @1.52v
> 
> View attachment 2546435


It's either because tRFC is not a multiple of 2, or because tWR is not 2 * RTP, or because it actually wants tWR 14 RTP 7, or both : - )


----------



## dk_mic

Veii said:


> BG 2201 SUS ?
> PGS or maybe not even BG anymore ?
> Ty for posting~


----------



## deadfelllow

can you link that pbo2 app? Is it free? 


TimeDrapery said:


> @PJVol
> 
> Great tool! On my 5600X and my 5800X (B550i Pro AX and B550 Master) it works wonderfully and has given me no issues until...
> 
> I induced a (freeze and then) crash on the 5800X by setting a CO value too low and now when I go to open the tool the cores aren't displayed and I'm presented with an error message stating that something's missing
> 
> So far I have just cleared my event log, deleted the directory, and decompressed another copy of your tool but I'm still presented with the same error message when opening the tool
> 
> View attachment 2546073
> 
> View attachment 2546071
> 
> View attachment 2546072
> 
> View attachment 2546070
> 
> 
> Of course I didn't screenshot the error message 😂😂😂😂😂
> 
> I can when I'm home next if it's helpful


----------



## ManniX-ITA

Veii said:


> Outch~
> I don't trust them exactly about such changes
> But it very well can be an MSI bios issue


Honestly doubt can be an MSI issue...
Made a lot of testing switching different BIOSes. 
Temp in idle is normal with 1.2.0.4 and 1.2.0.5, fluctuate with 1.2.0.1 and 1.2.0.3.
But the worse is that my best cores are now unstable with 1.2.0.1 at the same speed as before.
Same counts that still work on 1.2.0.4 but since the VDDG is locked at 1000mV, despite the right clock, they go slower.
I've lost about 50 MHz on my best cores, nice gift.



Veii said:


> The 12V OCP Expander Part
> But rather the part where MSI pushed early on testing bioses, community modded them, newer "public" beta was then different than old chiphell "leaks" that got modded
> This "maybe an msi issue" part


The OCP Expander part is just that instead of taking a screenshot with F12 (I go too fast), I've enabled it.
And when it's enabled all weird things happens. Including +5c on the memory as I just found out.
Then I saved the profile and when I went back to the old BIOS thought it was another gift from the new AGESA.



Veii said:


> I can try, but want you to have a fallback recovery option - as it might not post.


Seems MSI's USB Flashback often doesn't work if the BIOS is corrupted.
I wouldn't risk so much... I'm thinking about a new board



Veii said:


> Before doing so, can you drop a screenshot of ZenPTMonitor
> Do you have an HW-ROM Flasher next to you ?
> If possible and your bios profiles are not valuable or already gone, can you update from 1203C to 1205 with AFUWIN


I'm already back to 1.2.0.5 but I'll probably give a try again with 1.2.0.1 tomorrow.
My ROM flasher is very very old  and the flash is not socketed here (there was just yesterday a discussion about it in the Unify-X thread)
I'm always using Afuwin since I've almost lost the board last time with flashrom
Also using only modded BIOS


----------



## nada324

dk_mic said:


> love it
> 
> about B2: for what it's worth, i have a 5950x B2 received directly from AMD (Netherlands) as RMA return, its 202201 SUS.
> posted about my findings in the Dual CCD oc thread.
> 
> 
> 
> 
> 
> 
> 
> 
> OFFICIAL 5900X and 5950X two chiplet Zen 3 CPUs...
> 
> 
> The baseline would be the Windows drivers. Testing and following the chipset driver versions can be time-consuming, in my opinion. If the cpu perform well with the Windows drivers, and it does over a long period of time. I just remember, when I got the chip in December 2020, I had a serious...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> still not 100% sure how to treat it right, but 1.2.0.5 seems better for it.


I received, 2130 SUS 5600x and seems better bin than my old 2050SUS 5600X at least i can get +200 PBO with CO -20 All core Stable avx2 and core cycler


----------



## domdtxdissar

nada324 said:


> I received, 2130 SUS 5600x and seems better bin than my old 2050SUS 5600X at least i can get +200 PBO with CO -20 All core Stable avx2 and core cycler


One of my 2130 5950x's also turned out pretty nice, good week for the fab


----------



## blodflekk

Event tracing fatal error bosd, can't make it into windows at all. Did I corrupt windows or did something actually die ?


----------



## TimeDrapery

Spoiler






deadfelllow said:


> can you link that pbo2 app? Is it free?






All credit and gratitude to @PJVol , even if he won't write a tuning guide with me and he's lost all passion for life and just wants to create cool tools and share them with the community

@deadfelllow

Here you go, just remove the .txt appended to the filename


----------



## Taraquin

blodflekk said:


> I've done most of that, I have established a stable baseline, I'm trying to tighten now. wr\rtp is stuck at 14/7 wrrd is at 12.


14/7 wr/rtp is okay  wrrd 12 is a bit high, maybe 11 or 10 could work?


----------



## blodflekk

Taraquin said:


> 14/7 wr/rtp is okay  wrrd 12 is a bit high, maybe 11 or 10 could work?


I did start wrrd at 8 and worked back til I stopped getting errors, for me that was 12.


----------



## Taraquin

blodflekk said:


> I did start wrrd at 8 and worked back til I stopped getting errors, for me that was 12.


Okay, a bit unlucky with rdwr then. Post a new zentimings so we might help you further?


----------



## blodflekk

It will be a few hours, all this work broke windows so I'm still setting up my clean install. I would also like to mention I'm not using tm5, I was passing really good timings at reasonable voltages but then switched back to hci memtest and was flooded with errors.

*edit*
I did try to auto proc and rtt's and my motherboard chose 43.6, disabled, 3, 1


----------



## Taraquin

blodflekk said:


> It will be a few hours, all this work broke windows so I'm still setting up my clean install. I would also like to mention I'm not using tm5, I was passing really good timings at reasonable voltages but then switched back to hci memtest and was flooded with errors.
> 
> *edit*
> I did try to auto proc and rtt's and my motherboard chose 43.6, disabled, 3, 1


Okay, did auto make a difference to errors?


----------



## Kha

5900x BG 2142SUS is a B0. Infinity Fabric 1900 appears to work like a charm, anything higher spews Wheas.

Soon going test 5900x BG 2143SUS, lets see if thats B2 or not.


----------



## blodflekk

Taraquin said:


> Okay, did auto make a difference to errors?


It didn't stop them but it seemed to slow them. Didn't get far before the corruption however.


----------



## GrumpyCalabi314

Hi all! I reached this results (5600x, B550M Mortar on AGESA 1.2.0.5, 2x8 Crucial Ballistix Elite i.e. Micron Rev. E). I also run about 7 times OCCT gpu stress test (ram reached 52/54 during this tests, it stays at 43/45C when only Karhu is running). tm5 and windows 11 seems not to work great in my case... Any tips on what i can improve? How i can find optimal resistances and voltages?


----------



## rossi594

Just a quick question:

TM5 keeps using up all the memory all the time and makes me doubt if the graphics driver / explorer run out of memory sometimes or if I have instabilities that result in those crashes but no tm5 errors.

I changed the Testing Window Size without and luck. Then the Reserved Memory for Windows, but it keeps resetting the config (is there a max value for that?).


----------



## Luggage

ManniX-ITA said:


> Honestly doubt can be an MSI issue...
> Made a lot of testing switching different BIOSes.
> Temp in idle is normal with 1.2.0.4 and 1.2.0.5, fluctuate with 1.2.0.1 and 1.2.0.3.
> But the worse is that my best cores are now unstable with 1.2.0.1 at the same speed as before.
> Same counts that still work on 1.2.0.4 but since the VDDG is locked at 1000mV, despite the right clock, they go slower.
> I've lost about 50 MHz on my best cores, nice gift.
> 
> 
> 
> The OCP Expander part is just that instead of taking a screenshot with F12 (I go too fast), I've enabled it.
> And when it's enabled all weird things happens. Including +5c on the memory as I just found out.
> Then I saved the profile and when I went back to the old BIOS thought it was another gift from the new AGESA.
> 
> 
> 
> Seems MSI's USB Flashback often doesn't work if the BIOS is corrupted.
> I wouldn't risk so much... I'm thinking about a new board
> 
> 
> 
> I'm already back to 1.2.0.5 but I'll probably give a try again with 1.2.0.1 tomorrow.
> My ROM flasher is very very old  and the flash is not socketed here (there was just yesterday a discussion about it in the Unify-X thread)
> I'm always using Afuwin since I've almost lost the board last time with flashrom
> Also using only modded BIOS


Sus about the boost of my best core as well after 1205 and 1203 back and forth. Having to retune co values after going back to 1203, but -50mhz seems likely  (unless I also forgot about some change)

But also sus about it not liked running y-cruncher with 1.5V vcore for hwbot benches 

My second best is still happily boosting to cap though.


----------



## ManniX-ITA

rossi594 said:


> TM5 keeps using up all the memory all the time and makes me doubt if the graphics driver / explorer run out of memory sometimes or if I have instabilities that result in those crashes but no tm5 errors.


Which kind of crashes?
Shouldn't be a problem if you have the paging file active.
Once it's started the memory is locked.
It's best not to use the PC at all while running TM5.



rossi594 said:


> I changed the Testing Window Size without and luck. Then the Reserved Memory for Windows, but it keeps resetting the config (is there a max value for that?).


Did you erase the cfg.link file first?


----------



## rossi594

Can someone recommend me setup times to take this to t1 pure? (It's dual rank).


----------



## ManniX-ITA

Luggage said:


> but -50mhz seems likely


Yep, I had to reduce 2 counts to get it stable (hopefully, just a quick testing).
About 50 MHz less in max clock with boosttester and 25MHz less with Hydra.
The 2nd best lost around 25 MHz in boosttester and same in Hydra.


----------



## rossi594

ManniX-ITA said:


> Which kind of crashes?
> Shouldn't be a problem if you have the paging file active.
> Once it's started the memory is locked.
> It's best not to use the PC at all while running TM5.
> 
> Did you erase the cfg.link file first?


Page files are for casuals xD mine is off  (I thought about changing that back while ocing).
I did not erase the file. But I realized that 1024mb works for windows reserved while values above that will reset that config.

From what I can see erasing the file just resets the config, should be the same as loading it again.


----------



## Bloax

Taraquin said:


> Okay, a bit unlucky with rdwr then. Post a new zentimings so we might help you further?


The only dual-rank b-die kits which do low RDWR are top bins on ridiculous PCBs which go for 200% the price of an "ordinary" dual-rank b-die kit.

So nothing unfortunate there!


----------



## Taraquin

Bloax said:


> The only dual-rank b-die kits which do low RDWR are top bins on ridiculous PCBs which go for 200% the price of an "ordinary" dual-rank b-die kit.
> 
> So nothing unfortunate there!


12 is a bit high, I've seen average ones do 10 when running 15 or 16 flat 3800, super bins do 8 or 9. Some kits are weird on certain timings, mine is avg on most, but do rdwr tight but hate wtrl.


----------



## rossi594

Bloax said:


> The only dual-rank b-die kits which do low RDWR are top bins on ridiculous PCBs which go for 200% the price of an "ordinary" dual-rank b-die kit.
> 
> So nothing unfortunate there!


Hmm? Am I getting something wrong? I can do the 8 RDWR @ 4066 1.5v without one of those kits (I am running two kits of cheap Patriot Viper Steel).

Did you mean even lower ones? Like 5?
Or were you talking about DR on two sticks?


----------



## ManniX-ITA

rossi594 said:


> Page files are for casuals xD mine is off  (I thought about changing that back while ocing).


eheh unfortunately TM5 can crash easily without paging, anything Windows decides to run in background can kill the workers



rossi594 said:


> From what I can see erasing the file just resets the config, should be the same as loading it again.


erasing the file makes TM5 reload the cfg file at next start
I stopped used the button cause it was doing funny stuff sometimes
but it's probably since 0.12 that I don't use the button, maybe now works


----------



## rossi594

ManniX-ITA said:


> eheh unfortunately TM5 can crash easily without paging, anything Windows decides to run in background can kill the workers
> 
> 
> 
> erasing the file makes TM5 reload the cfg file at next start
> I stopped used the button cause it was doing funny stuff sometimes
> but it's probably since 0.12 that I don't use the button, maybe now works


Thanks for sharing. I turned the pagefile back on for now it works smoothly. Still weird tho that it won’t follow the config limits.

Would be nice if the system was not totally unusable while you run 20 cycles.


----------



## Audioboxer

Would have been great if Samsung had found a way to get the VDIMM max higher for B-die at full capacity. tCL12 starts booting at 1.65v, seems to show some promise nearer 1.7v, but that just can't be sustained at 32GB.

Still, I made it over 100%, clearly 100% = stable


----------



## ManniX-ITA

rossi594 said:


> Would be nice if the system was not totally unusable while you run 20 cycles.


Unfortunately, it's the best way to test memory
I bought Kahru for when I want to test but really need to use my pc
It's nowhere near as reliable as TM5 in error detection but it's decent and a good cross check
You just need to set a couple of threads less than max and you can use your PC, it doesn't crash
At least with light tasks, you can't do gaming or rendering of course


----------



## domdtxdissar

Kha said:


> 5900x BG 2142SUS is a B0. Infinity Fabric 1900 appears to work like a charm, anything higher spews Wheas.
> 
> Soon going test 5900x BG 2143SUS, lets see if thats B2 or not.


Good luck, non of my 4 5950x would go above 1900fclk without whea and/or reduced performance in Linpack Xtreme / Y-cruncher


Spoiler: Here are stats from my BG 2130 SUS super platinum / platinum sample





















Efficiently rating @ *4.22* / 4.11


----------



## rossi594

domdtxdissar said:


> Good luck, non of my 4 5950x would go above 1900fclk without whea and/or reduced performance in Linpack Xtreme / Y-cruncher
> Here are stats from my BG 2130 SUS super platinum / platinum sample
> View attachment 2546546
> 
> View attachment 2546548
> 
> 
> Efficiently rating @ *4.22* / 4.11
> View attachment 2546549


I remember @Veii mentioning that you have to stabilize a certain voltage to get the performance improvements out of really high fclk clocks.


----------



## dk_mic

domdtxdissar said:


> Good luck, non of my 4 5950x would go above 1900fclk without whea and/or reduced performance in Linpack Xtreme / Y-cruncher
> Here are stats from my BG 2130 SUS super platinum / platinum sample
> View attachment 2546546
> 
> View attachment 2546548
> 
> 
> Efficiently rating @ *4.22* / 4.11
> View attachment 2546549


AGESA + bios settings?


----------



## rossi594

rossi594 said:


> I remember @Veii mentioning that you have to stabilize a certain voltage to get the performance improvements out of really high fclk clocks.


VDD18 was the one.


----------



## Veii

rossi594 said:


> VDD18 was the one.


VDD18, procODT, SOC
But that is to combat throttling, yet not to combat WHEA
If WHEA arise by odd DPM design, and powermanagement issue internally - then you can't do anything
You can try if "disable CCD" will disable the correct one - but mostly you can not do anything. Issue is AMD not the voltages we have access to

What you can try to do, is differentiate between throttling and reported issues
@Bloax method will show spikes once throttling kicks in, but in order to track that one - you would need to take care of the first issue. That is the error spam
The spam by itself creates too many DPC spikes and even pulls performance down. Later if you mask and ignore them , you can try to focus on the main issue ~ which is package throttle
^ that's VDD18, procODT and likely SOC's work

procODT, SOC and VDD18 have no connection to MCLK ~ barely to non
Same as cLDO_VDDP has no connection to FCLK targets, but will influence memory stability
Both will influence memory stability with them. A change there without being sure memory remains stable, is not a good idea
But also, a change there to hope WHEAs are gone, is also not a good idea.
WHEAs are just reports, error reports, same as #20 are "error corrected" reports.
The reports by themself will cause inconsistent performance and throttle (if they appear, and even more if 20 a sec do appear)
Soo in order to actually diagnose "correct" voltages without throttle spikes ~ one has to disable the reports all together, or at least keep that in mind


----------



## domdtxdissar

rossi594 said:


> I remember @Veii mentioning that you have to stabilize a certain voltage to get the performance improvements out of really high fclk clocks.


After over 1 year active in this thread there have not been a single normal dual ccd cpu which can show scaling above 1900 flck in Linpack and/or Y-cruncher.
The best you can hope for is ~matching your 1900 performance, and with a single ccd at that.








I can show perfect scaling in light apps/benchmarks @ 1966, but only getting ~same gflops in linpack as 1900 settings at the same 4500/4400 static cpu clocks, and y-cruncher is ~5 sec slower








For these benchmarks its actually better to run async compared to above: (gaming is slower tho because more latency bound)








In featherweight benchmarks like aida64 etc i can show scaling all the way up to 2000:4000 and above.

*But real performance without throttling in the heaviest benchmarks above 1900:3800 is a pipedream..*



dk_mic said:


> AGESA + bios settings?


Info here
(can follow the posts backwards)


----------



## dk_mic

@domdtxdissar yes, there you show lower hydra ratings at "elevated voltages", so i am just curious if the frequencies hydra finds in the post right up there are at bone stock, or what voltage/LLC tweaks you habe done? Is this AGESA 1203 or 1205?


----------



## Kha

Ok so I am confirming the BG 2143SUS is indeed B2, however no WHEA free FCLK over 1900.


----------



## domdtxdissar

dk_mic said:


> @domdtxdissar yes, there you show lower hydra ratings at "elevated voltages", so i am just curious if the frequencies hydra finds in the post right up there are at bone stock, or what voltage/LLC tweaks you habe done? Is this AGESA 1203 or 1205?


Lower hydra rating was because regular paste in a warmish room, now iam using LM in colder room (~20-22 degrees)
(and finetuned voltage settings)
Using LLC auto -> higher vdroop = higher rating in hydra (LLC auto give ~10% vdroop at ~250ppt)
1203c because it perform the best with PBO CO (capped vcore at above 140edc)


----------



## dk_mic

so the screenshots where CCD0 is almost completely >5000 MHz is with a voltage offset? or what do you mean by fine-tuned voltages? SoC and VDDGs? 
Sorry for the questions, but I am running hydra right now at stock settings and just want to see if it's even comparable


----------



## Bloax

rossi594 said:


> Hmm? Am I getting something wrong? I can do the 8 RDWR @ 4066 1.5v without one of those kits (I am running two kits of cheap Patriot Viper Steel).
> 
> Did you mean even lower ones? Like 5?
> Or were you talking about DR on two sticks?


When I say "dual rank", I mean dual-rank sticks; 16 chips on a DIMM.

It's very normal for single-rank sticks with 8 chips to run lower RDWRs, even in a 4x8 config.

From what I've seen, it's a bit of a crapshoot between 7-9 RDWR on single-rank, and 11-14 RDWR on dual-rank sticks.
Only top-end dual-rank sticks do RDWR 9, and one of them (ripjaws v 4266 17-18-18 1.5v) is a troll PCB that doesn't want to work stable. 

(and yes, the F4-4000C14-16GVK are indeed one of those "top-end" dual-rank sticks)


----------



## MrHoof

Bloax said:


> From what I've seen, it's a bit of a crapshoot between 7-9 RDWR on single-rank, and 11-14 RDWR on dual-rank sticks.
> Only top-end dual-rank sticks do RDWR 9, and one of them (ripjaws v 4266 17-18-18 1.5v) is a troll PCB that doesn't want to work stable.
> 
> (and yes, the F4-4000C14-16GVK are indeed one of those "top-end" dual-rank sticks)


tRDWR 7 no idea why it works but it does. 3600 14-15-15 kit.


----------



## Bloax

If it does WTR 3 (and especially) WTRL 8 at 3800 as a dual-rank kit, it's a good PCB 

Like most of them, they're mysteriously not listed anywhere anymore :^))



> After over 1 year active in this thread there have not been a single normal dual ccd cpu which can show scaling above 1900 flck in Linpack and/or Y-cruncher.
> The best you can hope for is ~matching your 1900 performance, and with a single ccd at that.


If there is indeed some "hidden" global power limit (even worse than EDC!), into which memory, CCD + SOC power, eat into - then yes, 2-CCD CPUs will hit it before 1-CCD CPUs.


----------



## MrHoof

tRDWR 7 is more impressive then wtr3 wtrl8 I think. I cant recall seeing a other screenshot of tRDWR 7 here.


----------



## 1s1mple

Jonnycat99 said:


> I am trying to get CJR (2x16) to use 1T, but whenever I do tPHYRDL goes from 26/26 to 28/28, negating any improvement (2T has a lower latency than 1T with 28/28).
> 
> I've tried changing ProcODT to values between 36 and 48, but no dice. I tried increasing tCWL to 16, but no dice. Before I continue trying to reinvent the wheel, do you have any suggestions of what other timings I should try to modify?
> 
> View attachment 2546083


 I cant even 3800Mhz on same kit as you.
Best i got


----------



## Veii

domdtxdissar said:


> there have not been a single normal dual ccd cpu which can show scaling above 1900 flck in Linpack and/or Y-cruncher.


Is AVX2 the only "real world" performance , that can be titled ?
We match on memory pretty equally ~ which showed scaling on tRRD too (as an example, but that's for another topic)







====================================================================
Soo i took my 2 hours of sitting in 10° Ambient and Benchmarking ~ for you & the OCN community
(mind you, this is about the maximum of hassle i'd do for anybody ~ and that is once a month at best)
To remove confusion and justify my time & freezing, let's get couple of things straight at first:
We have to level the ground and show differences
*~* This are not real world scenarios. It is XOC showing anything i can from all my capabilities do, to level ground with you ~ which still is not remotely possible
*~* Any positive and well looking results are under 10° Ambient, with a highly conductive paste, on a lapped 5600X, on a 50$ Aluminum Cooler, with 90$ memory on a near 300$ CPU
*~* I can not use Liquid Metal. Can not hold CPU in the 25° range. Do not have a waterblock. Do not have a CPU that is allowed to run beyond 65°. Max out at 4.85Ghz Boost. Do not use Hydra to bypass thermal or voltage limits & only own a 50$ GPU for the type of games i need to play (soo no game comparisons either, but i see scaling) 
*~* Results will be split in "runnable" aka "no throttle" & "irrelevant" aka "throttling" = +65°, with their corresponding held clockspeeds on each of the tests
*~* I am not capable to improve anything on the thermal-side anymore for the next months. It is everything i can do with the limited amount of budget i own & situation won't change as something as simple as a 50$ radiator or 2-3 fans, need ~2 months of saving penny by penny. With zero income, it is what it is.
*~* Please know your position before judging others. I will never be able to level ground with your cooling or your 5900/5950X, comparisons are irrelevant

Soo without further ado, here are the results you've been asking for months


Spoiler: Runnable / Held clockspeed of 4.85 & THM bellow 65° / Usable for comparison ✔ 






Spoiler: Geekbench 3 & 5






Spoiler: Thermalcheck Geekbench












Slight throttle as spikes down to 4.815-4.83Ghz, but they are tiny & both Geekbenches. I'd say it's a "pass"





Spoiler: Results






Spoiler: Geekbench 3












Memory shows no changes between thermals.
Load appears to be low IPC, soo clock speed is held


10° Room Temp vs 4200 C15-15 / tRRD_ 6-6-36 , tWTR_ 4-10 - Geekbench Browser


40% AES Perf. is an overboost bug





Spoiler: Geekbench 5














10° RoomTemp vs Generic - Geekbench Browser














Spoiler: Hydra PBO Boost Check / AVX2 per Core

















Spoiler: Aida64 Win11

















Spoiler: SuperPi 1.5XS 4.85Ghz PB2 - Benchmate

















Spoiler: Cinebench'es 4.85Ghz Single Core [IPC] / Benchmate




















Spoiler: Not comparable / Throttling between 4.59-4.61 ouf of 4.85Ghz / Thermal issue only ~ useless results ❌ 






Spoiler: Corona Benchmark






Spoiler: Thermal Failure

















Spoiler: Result ~ 4.8Ghz / 69-70°




















Spoiler: Y-Cruncher / Benchmate






Spoiler: Thermal Failure & Benchmate set-affinity Failure ~ 79° Held




















Spoiler: Cinebench'es / SSE, AXV, AVX2






Spoiler: Thermal Failure's

























Spoiler: Result's




















Spoiler: 7-Zip / Benchmate ~ Forgot to capture the result, but failure nevertheless

















Spoiler: LinpackXtreme-1.1.5 [AVX 2]






Spoiler: Catastrophic Thermal Failure / Benchmark 8GB & Stresstest 8GB












4.64ish lower than base-boost clock ~ 1.289V, only Cores








4.59-4.6Ghz, 1.265v





Spoiler: Result's












^ Benchmark Mode, Cores only ~ 4.64ish Ghz. Performance falls and falls [heats up]








^ 4.598ish to 4.61Ghz Peak ~ picture says everything





Spoiler: 10° Ambient Idle Check [29°]




















This should say everything
While there are tests i can run and have no issue running, most of what are titled "memory tests" are simply put core frequency tests
This includes many of SiSoftware Sandra's, although also sadly Corona Benchmark / LinX / Aida64 & Geekbench.
The last two being more tolerable, as the spikes are short and bearable ~ yet will always be a factor of potential inconsistency between runs [thermals].

I would like to compete with you , but logic simply states that comparisons are not possible.
Reality shows that we are on different grounds, and it makes no sense to judge the other or even the community as a whole [such is just selfish !] 
Reality also shows that nothing is black & white and you should start to investigate "why" there is no scaling for you (not globally).

Potentially @PJVol can be a comparison target for me, same as other 5600X users ~ who have to deal with the same ProcHot issue (unless run Hydra, which again makes it dynamic and not comparable)
But as long as i have to live out of thin air with a budget setup, your comparison wish will never be justified (i'll never be able to reach your demand) ~ unless you get yourself a 5600X first batch with no FCLK issues.
What can be justified, is a recommendation:
~ Lower expectations & start to understand that rarely anybody can level ground with you.
~ Very low % of people have the resources to invest in fantastic cooling & match your great CPUs.

I'm non of both,
~ soo please stop mocking people about FCLK on something you are not able to provide clear evidence, hence you have nobody that can match your ground & don't own such CPUs
The only person that you can compare results with, is yourself (same also for me) Either get a sample that can run beyond 1900 FCLK ~ or stop defining a global baseline.
The result & statement again is not black & white, and LinX is not a magical tool either that tests memory ~ even when the OC scene is used to it thanks to intel
** nobody could confirm that AVX2 scales with FCLK, but just that FCLK till X range is a bottleneck for Frequency.*
This answer you should've gotten, if you check how RDNA2 cards function with infinity cache. Very obvious for me, soo i don't make such bold statements
Also AVX2 does not equal to real world performance, but is something a fraction of users use.
* Still have to be stable & high clocking, but if low clocking it doesn't diminish the fact that AVX1 is mostly used for applications.

In general, fantastic sample results. Freq-Straps Hydra shows are AVX2
But that's all i can give you credit for. Maybe also the consistent testing (although i question your MCLK testing, hence timings didn't scale up or down to match differences between MCLK/FCLK)
Also in general (again), please stop with the mocking. You have no right to do so. Present something on your own exotic cooling conditions, but rarely anybody can match ground with you

That's all,
Can also give credit that you can talk & argue normally with people on this forum. It deserves credit, seeing how rare it is. 
Hopefully my results can be anyhow helpful ~ and we'll need to find an low IPC load, in order to test memory better.
Everything else is just showing too much deviations. It is not helpful at all. Soo maybe try to listen to me ~for once~ 😞


----------



## PJVol

Bloax said:


> If there is indeed some "hidden" global power limit (even worse than EDC!), into which memory, CCD + SOC power, eat into


Yeah, there is - it's called datalink layer's overhead, packet retransmission, and other bandwidth limitation related issues manifested as PIE controller's MCE interrupt and as WHEA event id 19 in Windows.


Veii said:


> Soo i took my 2 hours of sitting in 10° Ambient and Benchmarking


Decent work. Just don't get cold, pls


----------



## blodflekk

Taraquin said:


> Okay, a bit unlucky with rdwr then. Post a new zentimings so we might help you further?


These settings passed 900% hci memtest last night. vDIMM 1.55


----------



## domdtxdissar

Veii said:


> Is AVX2 the only "real world" performance , that can be titled ?
> We match on memory pretty equally ~ which showed scaling on tRRD too (as an example, but that's for another topic)
> View attachment 2546600
> 
> ====================================================================
> Soo i took my 2 hours of sitting in 10° Ambient and Benchmarking ~ for you & the OCN community
> (mind you, this is about the maximum of hassle i'd do for anybody ~ and that is once a month at best)
> To remove confusion and justify my time & freezing, let's get couple of things straight at first:
> We have to level the ground and show differences
> *~* This are not real world scenarios. It is XOC showing anything i can from all my capabilities do, to level ground with you ~ which still is not remotely possible
> *~* Any positive and well looking results are under 10° Ambient, with a highly conductive paste, on a lapped 5600X, on a 50$ Aluminum Cooler, with 90$ memory on a near 300$ CPU
> *~* I can not use Liquid Metal. Can not hold CPU in the 25° range. Do not have a waterblock. Do not have a CPU that is allowed to run beyond 65°. Max out at 4.85Ghz Boost. Do not use Hydra to bypass thermal or voltage limits & only own a 50$ GPU for the type of games i need to play (soo no game comparisons either, but i see scaling)
> *~* Results will be split in "runnable" aka "no throttle" & "irrelevant" aka "throttling" = +65°, with their corresponding held clockspeeds on each of the tests
> *~* I am not capable to improve anything on the thermal-side anymore for the next months. It is everything i can do with the limited amount of budget i own & situation won't change as something as simple as a 50$ radiator or 2-3 fans, need ~2 months of saving penny by penny. With zero income, it is what it is.
> *~* Please know your position before judging others. I will never be able to level ground with your cooling or your 5900/5950X, comparisons are irrelevant
> 
> Soo without further ado, here are the results you've been asking for months
> 
> 
> Spoiler: Runnable / Held clockspeed of 4.85 & THM bellow 65° / Usable for comparison ✔
> 
> 
> 
> 
> 
> 
> Spoiler: Geekbench 3 & 5
> 
> 
> 
> 
> 
> 
> Spoiler: Thermalcheck Geekbench
> 
> 
> 
> 
> View attachment 2546650
> 
> Slight throttle as spikes down to 4.815-4.83Ghz, but they are tiny & both Geekbenches. I'd say it's a "pass"
> 
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> Spoiler: Results
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> Spoiler: Geekbench 3
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> Memory shows no changes between thermals.
> Load appears to be low IPC, soo clock speed is held
> 
> 
> 10° Room Temp vs 4200 C15-15 / tRRD_ 6-6-36 , tWTR_ 4-10 - Geekbench Browser
> 
> 
> 40% AES Perf. is an overboost bug
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> Spoiler: Geekbench 5
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> 10° RoomTemp vs Generic - Geekbench Browser
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> Spoiler: Hydra PBO Boost Check / AVX2 per Core
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> View attachment 2546654
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> Spoiler: Aida64 Win11
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> View attachment 2546655
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> Spoiler: SuperPi 1.5XS 4.85Ghz PB2 - Benchmate
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> View attachment 2546656
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> Spoiler: Cinebench'es 4.85Ghz Single Core [IPC] / Benchmate
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> View attachment 2546657
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> Spoiler: Not comparable / Throttling between 4.59-4.61 ouf of 4.85Ghz / Thermal issue only ~ useless results ❌
> 
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> Spoiler: Corona Benchmark
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> Spoiler: Thermal Failure
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> View attachment 2546658
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> Spoiler: Result ~ 4.8Ghz / 69-70°
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> View attachment 2546659
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> Spoiler: Y-Cruncher / Benchmate
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> Spoiler: Thermal Failure & Benchmate set-affinity Failure ~ 79° Held
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> View attachment 2546660
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> Spoiler: Cinebench'es / SSE, AXV, AVX2
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> Spoiler: Thermal Failure's
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> View attachment 2546661
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> Spoiler: Result's
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> View attachment 2546664
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> Spoiler: 7-Zip / Benchmate ~ Forgot to capture the result, but failure nevertheless
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> View attachment 2546665
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> Spoiler: LinpackXtreme-1.1.5 [AVX 2]
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> Spoiler: Catastrophic Thermal Failure / Benchmark 8GB & Stresstest 8GB
> 
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> View attachment 2546668
> 
> 4.64ish lower than base-boost clock ~ 1.289V, only Cores
> View attachment 2546669
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> 4.59-4.6Ghz, 1.265v
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> Spoiler: Result's
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> View attachment 2546670
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> ^ Benchmark Mode, Cores only ~ 4.64ish Ghz. Performance falls and falls [heats up]
> View attachment 2546671
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> ^ 4.598ish to 4.61Ghz Peak ~ picture says everything
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> Spoiler: 10° Ambient Idle Check [29°]
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> View attachment 2546666
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> 
> This should say everything
> While there are tests i can run and have no issue running, most of what are titled "memory tests" are simply put core frequency tests
> This includes many of SiSoftware Sandra's, although also sadly Corona Benchmark / LinX / Aida64 & Geekbench.
> The last two being more tolerable, as the spikes are short and bearable ~ yet will always be a factor of potential inconsistency between runs [thermals].
> 
> I would like to compete with you , but logic simply states that comparisons are not possible.
> Reality shows that we are on different grounds, and it makes no sense to judge the other or even the community as a whole [such is just selfish !]
> Reality also shows that nothing is black & white and you should start to investigate "why" there is no scaling for you (not globally).
> 
> Potentially @PJVol can be a comparison target for me, same as other 5600X users ~ who have to deal with the same ProcHot issue (unless run Hydra, which again makes it dynamic and not comparable)
> But as long as i have to live out of thin air with a budget setup, your comparison wish will never be justified (i'll never be able to reach your demand) ~ unless you get yourself a 5600X first batch with no FCLK issues.
> What can be justified, is a recommendation:
> ~ Lower expectations & start to understand that rarely anybody can level ground with you.
> ~ Very low % of people have the resources to invest in fantastic cooling & match your great CPUs.
> 
> I'm non of both,
> ~ soo please stop mocking people about FCLK on something you are not able to provide clear evidence, hence you have nobody that can match your ground & don't own such CPUs
> The only person that you can compare results with, is yourself (same also for me) Either get a sample that can run beyond 1900 FCLK ~ or stop defining a global baseline.
> The result & statement again is not black & white, and LinX is not a magical tool either that tests memory ~ even when the OC scene is used to it thanks to intel
> ** nobody could confirm that AVX2 scales with FCLK, but just that FCLK till X range is a bottleneck for Frequency.*
> This answer you should've gotten, if you check how RDNA2 cards function with infinity cache. Very obvious for me, soo i don't make such bold statements
> Also AVX2 does not equal to real world performance, but is something a fraction of users use.
> * Still have to be stable & high clocking, but if low clocking it doesn't diminish the fact that AVX1 is mostly used for applications.
> 
> In general, fantastic sample results. Freq-Straps Hydra shows are AVX2
> But that's all i can give you credit for. Maybe also the consistent testing (although i question your MCLK testing, hence timings didn't scale up or down to match differences between MCLK/FCLK)
> Also in general (again), please stop with the mocking. You have no right to do so. Present something on your own exotic cooling conditions, but rarely anybody can match ground with you
> 
> That's all,
> Can also give credit that you can talk & argue normally with people on this forum. It deserves credit, seeing how rare it is.
> Hopefully my results can be anyhow helpful ~ and we'll need to find an low IPC load, in order to test memory better.
> Everything else is just showing too much deviations. It is not helpful at all. Soo maybe try to listen to me ~for once~ 😞


Thanks for the testing Veii, i can see you have put much time and though into this and i dont want to argue with you. We have been over this many times already, and i dont think it will come anything new from it this time either 

But i would like to point out a few things:


> there have not been a single *normal dual ccd cpu* which can show scaling above 1900 flck in *Linpack and/or Y-cruncher*.


I was talking about normal dual ccd cpus, such as 5900x and 5950x's --> not your unicorn dual ccd 5600x. But even when your very rare sample dont show "real scaling" above 1900fclk in *Linpack and/or Y-cruncher,* which that comment was about, i would dare to say it is correct.

Also please note that even said so myself that "i can show 100% scaling in light benchmarks" such as Geekbench, Aida SuperPI etc, but that was not the point.. In some benchmarks/programs you can indeed get increased performance above 1900, but not all benchmarks. And i think we see eye to eye here, no ?

This is the ddr4 24/7 stability thread and i would like my ram settings to be totally stable and performance predictable in everything i launch, hence throttling performance (in some applications) above fclk 1900 is not a option for me, and that's why i wrote the following: (and please note the "heaviest benchmarks" marker)
*



But real performance without throttling in the heaviest benchmarks above 1900:3800 is a pipedream..

Click to expand...

*And i still stand by those words  And i have to say that i find it alittle puzzling some people in this thread are deadset on running the karhu ramtest to 20000% or whatever how many hours to "prove 100% stability" can just turn around and run unstable infinity fabric clockspeeds. 


> Do not have a CPU that is allowed to run beyond 65°. Max out at 4.85Ghz Boost. Do not use Hydra to bypass thermal or voltage limits & only own a 50$ GPU for the type of games i need to play (soo no game comparisons either, but i see scaling)
> *~* Results will be split in "runnable" aka "no throttle" & "irrelevant" aka "throttling" = +65°, with their corresponding held clockspeeds on each of the tests
> .
> .
> While there are tests i can run and have no issue running, most of what are titled "memory tests" are simply put core frequency tests
> This includes many of SiSoftware Sandra's, although also sadly Corona Benchmark / LinX / Aida64 & Geekbench.


For exactly this reason i use a (low) static cpu OC set in CTR for all my comparisons, its free and very easy to use. I recommend everyone to do the same as PBO CO should not be used for any serious comparisons.



> I would like to compete with you , but logic simply states that comparisons are not possible.
> Reality shows that we are on different grounds, and it makes no sense to judge the other or even the community as a whole [such is just selfish !]


I'm not trying to compete with anyone.. I'm comparing memory performance and trying to share the results/data at what i would call low static cpu frequencies (4500/4400 is very slow for my sample)


> Also in general (again), please stop with the mocking. You have no right to do so. Present something on your own exotic cooling conditions, but rarely anybody can match ground with you


 This i really dont understand.. Mocking ? We haven't spoken nor written a single word to each other for weeks i believe (?) I was responding to rossi594 which was responding to me, but i'm sorry you feel that way for whatever reason.



domdtxdissar said:


> After over 1 year active in this thread there have not been a single normal dual ccd cpu which can show scaling above 1900 flck in Linpack and/or Y-cruncher.
> The best you can hope for is ~matching your 1900 performance, and with a single ccd at that.


Still stands, *eventho i wish it wasn't so*.. I even setout to buy 3 new cpus for a chance of B2 silicon which would MAYBE run higher IF speeds without throttling. (sadly it turns out it dont)


----------



## Audioboxer

AMD is the real enemy in here, not each other. The mess of AGESA and chipset drivers is 🤮

I truly believe if they knew what they were doing some of these better binned chips should be able to run FCLK between 1900~2000. Especially the chips that can run 1900 stable at pretty low voltages.

It is what it is though, AMD are a nightmare when it comes to software and firmware. None of us can overcome that and from what I've read AMD are awful at interacting with the OCing community or releasing anything meaningful about their hardware to help the scene.

We barely even get BIOS changelogs lol.

For me all the more reason why Intel making a comeback is a good thing.


----------



## rossi594

Audioboxer said:


> AMD is the real enemy in here, not each other. The mess of AGESA and chipset drivers is 🤮
> 
> I truly believe if they knew what they were doing some of these better binned chips should be able to run FCLK between 1900~2000. Especially the chips that can run 1900 stable at pretty low voltages.
> 
> It is what it is though, AMD are a nightmare when it comes to software and firmware. None of us can overcome that and from what I've read AMD ar awful at interacting with the OCing community or releasing anything meaningful about their hardware to help the scene.
> 
> We barely even get BIOS changelogs lol.


He's got a point. Every new Agesa breaks something (and there is never a real changelog). The removal of the fmax_offset setting without any justification is just an insult to all people that oc.
It just feels janky compared to Intel / Nvidia.


----------



## Veii

PJVol said:


> Decent work. Just don't get cold, pls


Ty for carrying.
I'm done with testing & had to strengthen my point (viewpoint or forced decision) that i can not take LinX serious, or any other AVX2 load
But there was also some talk on elmor's discord about it and how Buildzoid or Madness777 run it.
(Very big nummer) many, people use it and focus a lot on it. Yet it's what i feel happens, that's the reason of the comment and having to finally share something, even when i know it makes no sense


domdtxdissar said:


> *But real performance without throttling in the heaviest benchmarks above 1900:3800 is a pipedream.. *
> 
> 
> 
> And i still stand by those words  And i have to say that i find it alittle puzzling some people in this thread are deadset on running the karhu ramtest to 20000% or whatever how many hours to "prove 100% stability" can just turn around and run unstable infinity fabric clockspeeds.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I would like to compete with you , but logic simply states that comparisons are not possible.
> Reality shows that we are on different grounds, and it makes no sense to judge the other or even the community as a whole [such is just selfish !]
> 
> Click to expand...
> 
> 
> 
> Click to expand...
> 
> I'm not trying to compete with anyone.. I'm comparing memory performance and trying to share the results/data at what i would call low static cpu frequencies (4500/4400 is very slow for my sample)
> 
> 
> 
> 
> 
> 
> Also in general (again), please stop with the mocking. You have no right to do so. Present something on your own exotic cooling conditions, but rarely anybody can match ground with you
> 
> Click to expand...
> 
> 
> 
> Click to expand...
> 
> This i really dont understand.. Mocking ? We haven't spoken nor written a single word to each other for weeks i believe (?) I was responding to rossi594 which was responding to me, but i'm sorry you feel that way for whatever reason.
> 
> Click to expand...
Click to expand...

And that is part of the let's call it "grudge".
I wish for a load that can test memory performance ~ aida is maybe fun for bandwidth checks ~ but that's all. It only can test personal consistency but not more

The grudge is on 3 parts:
- AMDs beyond my understanding 65° hardcap that still seems to be debated with me, but i can't proof it wrong yet did everything i can do (free) that makes the issue smaller
[frustration that for me it's soo clear and can see it throttle or not throttle ~ but yet i'm argued about my own reading. Not even theory but real world readable issue. Yet it's denied to be a thing]
^ the same thing for other 5900X samples too, but there it's a voltage limiter and not a prochot limiter like here.
- The Part where AVX2 is set as the only mattering workload and used to deny the usefulness of lower timings or higher FCLK.
^ We don't even have enough Data to know FCLK influences anything AVX2 ~ and it's simply not clock speed, heat and powerbudget (which all skyrocket once you exceed 1.1v SOC)
- and the last one, that i haven't seen dom invest much more time to figure out why he doesn't see performance scaling on some things but does see performance scaling on other

Actually all 3 Parts are the reason i had to finally publish the same results i knew i would get, but that people still judged me for not delivering
since old days and it read today the same too ~ soo it was needed.

I'm annoyed on these parts, and even when communication is calm and respect exists between everyone here (hopefully)
I can not accept that AVX2 is titled as major important ~ and is used to nullify FCLK scaling or MCLK scaling.
We need a better test, something low IPC workload.
We need more testing, that one for sure.

Dom needs to get lucky and find a sample that runs high FCLK & i need to create presets with lowered memory timings (3800 13-13, 3600 12-12) to confirm and show scaling.
* after somehow cooling this chip down
On both parts, it needs more data to "decide" that there is no FCLK scaling and to figure out if AVX2 even cares about FCLK.
Currently @domdtxdissar states that on tests that he use (all are AVX2) , there is negative FCLK scaling. Ok maybe, load is very high. I wouldn't even wonder if this is the case of instabiltity.
But i refuse to accept that AVX2 is "real world" and refuse to accept that scaling fully is irrelevant.

No games are AVX2 (nothing i know, maybe CPU Ray-Traced)
And no normal programms use it.
To define that either
A.) It doesn't matter the effort and we should stick to AMDs limits 1900 FCLK, because scientific programs show no scaling but rather issues
B.) AVX2 is the only one to care, and i refuse to acknowledge scaling exist even on my good samples, soo nobody should bother
Last part is unlikely the case and unlikely reality ~ but that's how it reads @domdtxdissar
Neither i can proof that scaling is perfectly linear , because there is no way how i can cool that
Neither you can proof that scaling doesn't exist, because you don't even own samples that can run it issue free.

Soo making bold statements, just can not be correct.
Even when your experience shows no scaling & people can not find a sample that can run it.


domdtxdissar said:


> For exactly this reason i use a (low) static cpu OC set in CTR for all my comparisons, its free and very easy to use. I recommend everyone to do the same as PBO CO should not be used for any serious comparisons.


I have a problem with that method,
We know (maybe) that an allcore is slower than PB2. But "why" is it slower ?
If AVX2 let's say actually utilizes cache frequency and so interconnect frequency matters [FCLK]
~ how would we even confirm that it's not something as simple as a bottleneck of FCLK.

On intel it was known after when Ringbus or Cache Multiplier do not matter
Why should it be different on AMD ~ which is even more dependent on FCLK frequency ?

Writing you that i've had "good enough" experience on Navi21 and seen that SOC or FCLK frequency (internally) only matters after specific high frequency ~ but does nothing at low frequency
Aka "it only matters if frequency is high enough soo fabric and cache become a bottleneck"
~ why should it be on Ryzen CPUs different, when nearly the exact same algorithm is used ?

*I can not decline that AVX2 has no FCLK scaling, even when running high FCLK
How can you ? When you can't even run high FCLK ?
It makes no sense to me, giving such bold statements.*

Then we add to this, that a fixed clock, lowers fully cache frequency and interconnect speed
Aand we add also to this that FIT is not disabled in OC_Mode and still will package throttle on high FCLK

*How can anybody even be sure that AVX2 is bottlenecked, or not bottlenecked*
I can only see that it can be bottlenecked by frequency ~ if you increase FCLK.
High FCLK has many ! issues, to even get correct, and when you test it with low core clock ~ you won't see scaling. Cache is too slow
Then when we test it with high core clock, people can not even hold the core clock and too many push it to the issue being FCLK, but not simple package throttle (for whatever reason it throttles)
^ to this people also counts Buildzoid , with all the respect i have to him ~ same thing. Why the strong focus on LinX ?

*Last point to add more to this confusion,
Can anybody even guarantee that AMD doesn't have fixed AVX2 throttler's set in place ~ as it is common on Intel*
AVX2 has a fixed loadline droop, a fixed voltage droop ~ and we should expect still perfectly linear scaling and no throttle
How does this work ?

There are just too many issues that speak against your post, and this has been ongoing since too long
I had to comment, even when nobody mentioned it now ~ because the reason is still the same.
"How can we even make such bold statements, when nobody knows ?"
I certainly know that i can't proof anything now, it's simply impossible by my cooling abilities. Even when everything is ice cold ~ SOC & FCLK heat up too much
Soo why do we even judge ?
That's my intention here. We can not judge. It's not possible.
I can not deliver you a correct answer that you are wrong. And you can not deliver me a correct statement that it's not instability or other throttle.
Please someday find such sample, and i will try to someday meet demand for AVX2 testing.

In the current state, this is impossible and we shouldn't make such statements about FCLK. It simply can't be tested correctly. Far to many variables
I do also think we shouldn't focus on AVX2 loads too much, but i can't change your viewpoint as it seems.
We certainly need more apps for memory testing. I can't find anything, maaybe TimeSpy CPU is reasonable, but it doesn't test IPC that well


----------



## Bloax

I'm very thankful to AMD for all the fun times figuring out Zen3 and waking up Intel :- )



> I'm done with testing & had to strengthen my point (viewpoint or forced decision) that i can not take LinX serious, or any other AVX2 load
> But there was also some talk on elmor's discord about it and how Buildzoid or Madness777 run it.
> (Very big nummer) many, people use it and focus a lot on it. Yet it's what i feel happens, that's the reason of the comment and having to finally share something, even when i know it makes no sense


The most *practical application* of memory/fabric overclocking is for the purpose of maximizing minimum FPS/minimizing FPS dips in competitive videogames.

These tasks are not as heavy as xXXtreme AVX2 y-cruncher workloads, therefore it doesn't really matter that _1900+ FCLK doesn't work *there*_.
I don't know if 2-CCD CPUs can do the same EDC-bypassing through manual CPU clocks and still reap the rewards - as I haven't had a chance to test it - but it is pretty likely that they can.


As for the prevalence of wacky, weird, synthetic benchmarks over what it's actually useful for - I seem to be in the _disappearing minority_ when it comes to being someone that is very interested in making memory go fast, but also counting as a body-double for a professional FPS player.
Most seem to be people who like making thing go fast, or push thing until it go boom? Not really people who actually get practical benefits out of making thing go fast.


----------



## Veii

Bloax said:


> The most *practical application* of memory/fabric overclocking is for the purpose of maximizing minimum FPS/minimizing FPS dips in competitive videogames.
> 
> These tasks are not as heavy as xXXtreme AVX2 y-cruncher workloads, therefore it doesn't really matter that _1900+ FCLK doesn't work *there*_.
> I don't know if 2-CCD CPUs can do the same EDC-bypassing through manual CPU clocks and still reap the rewards - as I haven't had a chance to test it - but it is pretty likely that they can.


5900X i had, where on many parts frequency throttled. But close to all ended being voltage throttle by high VID request
EDC "limits" where just matching with voltage

The problem is, and i've tested this last year already,
You lose cache perf, if you fixate clock. Yet FIT is active
FIT throttles FCLK and i haven't found any method, to this date ~ to prevent that.
It will always happen independent of PB2 or Fixed Freq.
Sadly this same goes for the XOC scene ~ which i feel is not even aware of that.
Frequency "performance" throttle will happen, on the same frequency by FIT ~ independent what frequency is read out or how it is set.
Clock stretching does exist, with a slightly modified form. It's not the frequency strap / effective frequency stretching it was titled to be before.
Such is just logical, you watch effective frequency and the issue is gone ~ but that's not the "clock stretching" that i mean.

On my CPU based games, i see scaling and this is for FCLK + weak MCLK timings > Low timings, low MCLK
(contradicting your experience too, on the tRRD & tWTR topic)  :')
The FCLK benefit to my sample always was bigger than the Memory Timings benefit ~ but when i can't even hold 4.85, what does FCLK give me at all. Zero difference

"Sadly" even Aida64 showed the same
On not high frequency, let's say 1800 FCLK ~ between 4.65 and 4.75 the result is tiny
On 2100 FCLK the result between 4.65 and 4.85 is 2.5-3ns & about 300GB/s cache bandwidth
It snowballs, but only shows to me ~ when cache is slow, or frequency is low ~ FCLK doesn't care
Yet when frequency is high FCLK does care, tho we miss reports of such.

I can't deny AVX2 instruction set even carrying about FCLK
But i can not proof it either ~ it's uncoolable, SOC by itself is the issue having a delta of 20° to ambient "on idle @ 900mV Core"
FCLK and SOC push thermals of it far to high, but for my "real world not benching" usage , it's fine. I hold the clock

My games mostly are CPU focused and framesync'd
Something like "stutter" is noticeable on Rhythm Games and on other shooters
Wish i could deliver better data, but it's just not possible to cool this down. 145-150W is the tiny R23 test, Hydra without limits extend to 200W doesn't even run.
There is no way a cheap (while good) slow heatpipe cooler keeps it always under 60°. Not possible

Except @PJVol , idk who would even be able to compare PB2 AVX2 loads between FCLKs
There is no way to make statements about FCLK + AVX2.


----------



## VPII

So I just sold my two sets of G-Skill Flare X DDR4 3200 CL14 thus 4 x 8GB for 32GB which worked really well at 3800 CL16 on my old 3950X and now 5950X. The reason for doing this is to get 2 x 16GB set as in Trident Z Royal Elite which is 3600 CL14 14 14 34. THis way I can later upgrade to 64GB when needed.


----------



## Taraquin

blodflekk said:


> These settings passed 900% hci memtest last night. vDIMM 1.55
> View attachment 2546686


Mostly good  Try rfc 288, 272 or 256


----------



## Taraquin

Veii said:


> 5900X i had, where on many parts frequency throttled. But close to all ended being voltage throttle by high VID request
> EDC "limits" where just matching with voltage
> 
> The problem is, and i've tested this last year already,
> You lose cache perf, if you fixate clock. Yet FIT is active
> FIT throttles FCLK and i haven't found any method, to this date ~ to prevent that.
> It will always happen independent of PB2 or Fixed Freq.
> Sadly this same goes for the XOC scene ~ which i feel is not even aware of that.
> Frequency "performance" throttle will happen, on the same frequency by FIT ~ independent what frequency is read out or how it is set.
> Clock stretching does exist, with a slightly modified form. It's not the frequency strap / effective frequency stretching it was titled to be before.
> Such is just logical, you watch effective frequency and the issue is gone ~ but that's not the "clock stretching" that i mean.
> 
> On my CPU based games, i see scaling and this is for FCLK + weak MCLK timings > Low timings, low MCLK
> (contradicting your experience too, on the tRRD & tWTR topic)  :')
> The FCLK benefit to my sample always was bigger than the Memory Timings benefit ~ but when i can't even hold 4.85, what does FCLK give me at all. Zero difference
> 
> "Sadly" even Aida64 showed the same
> On not high frequency, let's say 1800 FCLK ~ between 4.65 and 4.75 the result is tiny
> On 2100 FCLK the result between 4.65 and 4.85 is 2.5-3ns & about 300GB/s cache bandwidth
> It snowballs, but only shows to me ~ when cache is slow, or frequency is low ~ FCLK doesn't care
> Yet when frequency is high FCLK does care, tho we miss reports of such.
> 
> I can't deny AVX2 instruction set even carrying about FCLK
> But i can not proof it either ~ it's uncoolable, SOC by itself is the issue having a delta of 20° to ambient "on idle @ 900mV Core"
> FCLK and SOC push thermals of it far to high, but for my "real world not benching" usage , it's fine. I hold the clock
> 
> My games mostly are CPU focused and framesync'd
> Something like "stutter" is noticeable on Rhythm Games and on other shooters
> Wish i could deliver better data, but it's just not possible to cool this down. 145-150W is the tiny R23 test, Hydra without limits extend to 200W doesn't even run.
> There is no way a cheap (while good) slow heatpipe cooler keeps it always under 60°. Not possible
> 
> Except @PJVol , idk who would even be able to compare PB2 AVX2 loads between FCLKs
> There is no way to make statements about FCLK + AVX2.


Why would you guess avx2 on most systems show neg scaling above 1900fclk? On my 5600X aida, dram calc, SOTTR and a few others scale positive (1-3%) going from 3800cl15 to 4000cl16), but y-cruncher and linpack scales negatively (1-2%). Even with fixed clockspeeds, same timings and voltages and only 100MHz higher fclk I get similar neg scaling. Dom gets severe neg scaling, I get very little. I would guess that the WHEA 19 flood on his part contributes, I have no WHEA 19 even at 2066fclk which is highest bootable.

Do you have advice on adjustments I could make to get positive scaling?


----------



## ManniX-ITA

domdtxdissar said:


> After over 1 year active in this thread there have not been a single normal dual ccd cpu which can show scaling above 1900 flck in Linpack and/or Y-cruncher.
> The best you can hope for is ~matching your 1900 performance, and with a single ccd at that.


Sorry, I don't want to convince you otherwise as you have your faith but my experience running at FCLK 2000 for over 1 year is very different
My 5950X is pretty average and can show matching and exceeding performances over FCLK 1900 in every benchmark.
Except some of those where I'm thermal constrained; FCLK 2000 is more demanding in thermals and needs a lot more voltage.

If you are unable to achieve that is partly cause almost all dual CCDs are not stable above FCLK 1900.
Partly cause doesn't seem like you really put a lot of effort on it, except running the always appreciated sets of benchmarks.
But seems your goal is always more about proving your point on this topic than being objective (my opinion).

If you could get your FCLK 2000 stable, use similar memory timings and compare with the monero miner then I'm pretty sure the picture would be different.
You used the tCL 13 profile for FCLK 1900 which is very special... 
And 5 seconds against FCLK 1933? It's so obvious something is wrong
Plus y-cruncher is using intensively memory write operations, any small change in write related timings has a huge impact.

For my 5950X which is throttling at 90c, a "normal" score for y-cruncher pi 2.5b is around 66 seconds.
If your platinum 5950X which is topping 79c is scoring 68 seconds then it's screaming "fix me" 

As said multiple times; *monitor the DRAM Bandwidth while running the benchmark with HWInfo*.

xmr-stak-rx ReadBW; Average 40, Max 41.4
Linpack Xtreme ReadBW; Average 27, Max 42
y-cruncher 2.5b ReadBW; Average 24, Max 37

If you want to check for any improvement with higher FCLK you need the monero miner.
Or anything else which is actually using the additional FCLK bandwidth.
Otherwise it's just a hunt for instabilities.

And last of course the benchmarks in de-sync.
Higher GFlops in Linpack and 59 seconds for y-cruncher.
Much better than FCLK1900 in sync...
I don't think there's a better proof than this one, that you produced yourself, that is meaningless to use these particular benchmarks to validate/score FCLK changes.



domdtxdissar said:


> But real performance without throttling in the heaviest benchmarks above 1900:3800 is a pipedream..


I live every day in the pipedream


----------



## TMavica

Really confused. I run tm5 and it timeout randomly when over cycle 10, it is not timeout during the test, it happened after going to next cycle, ( Finished a cycle and ready to run next cycle) , I cant do a 25 cycles test…i have done OCCT test with few hours without error, but just dont know why tm5 not working in my PC.


----------



## Taraquin

ManniX-ITA said:


> Sorry, I don't want to convince you otherwise as you have your faith but my experience running at FCLK 2000 for over 1 year is very different
> My 5950X is pretty average and can show matching and exceeding performances over FCLK 1900 in every benchmark.
> Except some of those where I'm thermal constrained; FCLK 2000 is more demanding in thermals and needs a lot more voltage.
> 
> If you are unable to achieve that is partly cause almost all dual CCDs are not stable above FCLK 1900.
> Partly cause doesn't seem like you really put a lot of effort on it, except running the always appreciated sets of benchmarks.
> But seems your goal is always more about proving your point on this topic than being objective (my opinion).
> 
> If you could get your FCLK 2000 stable, use similar memory timings and compare with the monero miner then I'm pretty sure the picture would be different.
> You used the tCL 13 profile for FCLK 1900 which is very special...
> And 5 seconds against FCLK 1933? It's so obvious something is wrong
> Plus y-cruncher is using intensively memory write operations, any small change in write related timings has a huge impact.
> 
> For my 5950X which is throttling at 90c, a "normal" score for y-cruncher pi 2.5b is around 66 seconds.
> If your platinum 5950X which is topping 79c is scoring 68 seconds then it's screaming "fix me"
> 
> As said multiple times; *monitor the DRAM Bandwidth while running the benchmark with HWInfo*.
> 
> xmr-stak-rx ReadBW; Average 40, Max 41.4
> Linpack Xtreme ReadBW; Average 27, Max 42
> y-cruncher 2.5b ReadBW; Average 24, Max 37
> 
> If you want to check for any improvement with higher FCLK you need the monero miner.
> Or anything else which is actually using the additional FCLK bandwidth.
> Otherwise it's just a hunt for instabilities.
> 
> And last of course the benchmarks in de-sync.
> Higher GFlops in Linpack and 59 seconds for y-cruncher.
> Much better than FCLK1900 in sync...
> I don't think there's a better proof than this one, that you produced yourself, that is meaningless to use these particular benchmarks to validate/score FCLK changes.
> 
> 
> 
> I live every day in the pipedream


What did you change except iod/soc going above 1900fclk? I need 1.07/0.98v soc/iod for 1900 and 1.11/1.03v soc/iod for 2000fclk. Problem with the latter is that allcore speed is around 50MHz lower due to IO-die using more pwr and eating from core budget. Also I must up prim timings by 1, ras/rc by 3, rfc by 16 and wtrl by 1, but refi is 800 higher at 2000 so that may help slightly. With same volt/timings I still see a bit neg scaling in y-cruncher/linpack, but SOTTR, dram calc test etc scales fine. Could the VDD18 volt be a factor worth testing? Think I tried earlier to no prevail.

For 2 setups I built for friends the enormous amount if WHEA 19 could explain inferior performance above 1900, but I have only had 2 WHEA 19 since April last year when I built my rig and that was from trying 60 DrvStr one time and agesa 1.1.0.0 the other.


----------



## ManniX-ITA

Taraquin said:


> What did you change except iod/soc going above 1900fclk? I need 1.07/0.98v soc/iod for 1900 and 1.11/1.03v soc/iod for 2000fclk. Problem with the latter is that allcore speed is around 50MHz lower due to IO-die using more pwr and eating from core budget. Also I must up prim timings by 1, ras/rc by 3, rfc by 16 and wtrl by 1, but refi is 800 higher at 2000 so that may help slightly. With same volt/timings I still see a bit neg scaling in y-cruncher/linpack, but SOTTR, dram calc test etc scales fine. Could the VDD18 volt be a factor worth testing? Think I tried earlier to no prevail.


You may need the AMD PBS menu unlocked in your BIOS; there's an option to change the IF sync which is CLKREQ# and I need it Enabled.
Depends on the CPU, the BIOS/AGESA and the FCLK.
On some BIOS releases I don't need it for 1933/1966 but always for 2000.
Above it doesn't help.

You need to be generous with VSOC, likely between 1.20V and 1.25V.
I don't think you can get anywhere with 1.11V.
But it depends on you CPU. Below you are probably going to get lower or unreliable scores
Same for CCD & IOD, be generous, set it to the max before the performances are dropping.
I need around 50mV more on all compared to the best voltages for FCLK 1900.
Not sure the same metric can be used on a single CCD.

Unfortunately the single CCD power budget is very constrained.
I'm not sure the higher FCLK can compensate.

The memory timings changes are not very significant, the lower latency and bandwidth should compensate plenty.

My advice is to take a baseline with the best settings you can get at FCLK 1900 with Geekbench 5.
Once you upload to the online browser set it as Baseline with the button on the right.
Then you can test the changes with FCLK and compare.
The main ST and MT scores are important but relative.
You need to watch closely all the single tests to see the effect of your changes.

AES-XTS scores, especially MT, will tell you what is the best VDDG CCD voltage.
The other tests mostly which is the best VDDG IOD.
Then you can move on fine-tuning the rest.

VDD18 is very important. Next in line.
Still depends on CPU and AGESA.
Before running AGESA 1.2.0.5 my best voltage at FCLK 2000 was 1.810V, now it's 1.900V...
At FCLK 1900 best was 1.840V, now I don't know yet.

Other things to check are:

Scalar: depending on other settings could be best 10x or 1x/4x
vCore offset: a small positive bump can help (0.0125-0.0250V)
I used to get it more stable and performant with 0.0125V, after AGESA 1.2.0.5 can't use any or the cores will get unstable

DF C-State: Depends on CPU/AGESA as well.
Had to use Enabled before AGESA 1.2.0.5, now seems working fine also Disable

Once you have some consistent results with GB5, run CB23 and CPU-z bench to validate you get same/better scores.
Then if you are really confident more benchmarks.
I would suggest that you spend some time configuring the monero minero xmr-stak-rx.
You are not going to see scaling up with a 5600X.
Only with more than 10 cores there's scaling up.
But you must get the same or slightly better hashrate.

EDIT:

Forgot a very important part; the VRM and LLC settings.
Depends on the motherboard how behaves.
But obviously if you have a cheap board it's better to avoid high FCLK.
Behavior of LLC and OCP/OVP Protection are different for brand/models/bios releases.

On my MSI usually works best OVP 400mV and OCP Enhanced.
On the Gigabyte Master OVP 400mV and OCP Medium to High.

CPU LLC on MSI always Auto (manual is borked, will always go slower...), Gigabyte likes Manual with High or a notch above, not the highest because it's overshooting a lot
SOC LLC on MSI doesn't really change for me unless is very weak, usually Auto, Gigabyte likes more Medium.

PWM Switching frequency it's crucial; that's where an high end board really makes all the difference.
You need to stick to the Highest or just below; depends on the CO and RAM settings.

On my MSI to stretch to the limit the CO counts I need CPU PWM set to 900 or 1000 kHz.
Otherwise the cores will fail under CoreCycler like hell.
About the SOC PWM you need it high if you are stretching the timings.
On my MSI FCLK 2000 at CL16 works perfectly fine at 800 kHz.
But for CL14 the SOC PWM needs to be set at 1000 kHz.

Best way to test the PWM frequency is the monero miner.
The VRM on my Unify-X, if the settings are wrong, starts squeaking like a mouse being butchered.
The hashrate per core instead of 580 is between 10 and 200; optionally the system will reset or shutdown brutally.


----------



## Audioboxer

rossi594 said:


> He's got a point. Every new Agesa breaks something (and there is never a real changelog). The removal of the fmax_offset setting without any justification is just an insult to all people that oc.
> It just feels janky compared to Intel / Nvidia.


I can somewhat shrug off secretive changelogs, they're not great, but some companies just do that. I cannot however understand AMD's hostility towards the OCing scene. Not only do knowledgeable people in this scene help others make their hardware more attractive by pushing performance and teaching people how to properly stability test, it ultimately ends up with AMD dominating in user share.

But this is why it's important for Intel to get their act together as it will either force AMD to change or if Intel simply keep creating quality hardware the OCing scene will shift predominantly [back] to Intel. The vast majority of people don't get too bogged down in brand loyalty, if a piece of hardware is dominating the OCing charts and the scene is lively around it, people will buy it.


----------



## Subut

Progress report time. After reading this thread I've changed methodology and swapped to the testmem5 software. I'm yet to touch WTR's, WR and RTP in this screenshot, they're on auto. Big thanks to veii for the hints and the leaderboard spreadsheet. It seems like the imc on my chip is good too because I'm getting 2000FCLK at a decent Vsoc and isn't even minimized. Going slow and steady is good, otherwise it's just frustration. Also no longer potato quality screenshots  



Spoiler: Screenshot


----------



## PJVol

ManniX-ITA said:


> Still depends on CPU and AGESA.


I'd put it - CPU, MB, ... and AGESA.


----------



## rossi594

Veii said:


> High FCLK has many ! issues, to even get correct, and when you test it with low core clock ~ you won't see scaling. Cache is too slow


I agree, but I think a lot of that is down to the fact that there are barely any guides beyond X.M.P, use DRAM calc or go completely crazy (sometimes for months ) and get lost in termination resistances etc.



Veii said:


> In the current state, this is impossible and we shouldn't make such statements about FCLK. It simply can't be tested correctly. Far to many variables


In general there are tons variables between different Agesa Versions, all the power saving features and different approaches to overclocking Zen3. I find it very hard to compary results from someone else to mine.



Veii said:


> On my CPU based games, i see scaling and this is for FCLK + weak MCLK timings > Low timings, low MCLK


I can definitly confirm this. I play mostly CPU limited games and there is a measurable benefit to running higher fclk (even with CS GO which scales well with lower timings). I see better scaling with fclk >1900 than with PB2. Between ~8x5025mhz with PBO and stock (PBO off) is barely a 5% difference. Even the step from 1900 flck to 2000 flck provides a bigger performance boost.
So yes, if you want to max out your CPU for those kind of games you should at least try if they scale beyond 1900 fclk.

Lastly about the thermals:
From my experience the heatspreader cooler connection / the ccd heatspreader connection are the bottleneck to cool my 5800X. As many people here I do run a Mo-Ra3 and waterblock on it, but at some stage water temperature and cpu temps just decouple. (my 6900XT with the XTXH stays far cooler at the same water temperature than my 5800X).

Maybe I buy a cooler with an offset design (more aligned to the ryzen hotspots) and a nickel base + liquid metal in the summer and give an update on this topic.


----------



## rossi594

Audioboxer said:


> I can somewhat shrug off secretive changelogs, they're not great, but some companies just do that. I cannot however understand AMD's hostility towards the OCing scene. Not only do knowledgeable people in this scene help others make their hardware more attractive by pushing performance and teaching people how to properly stability test, it ultimately ends up with AMD dominating in user share.
> 
> But this is why it's important for Intel to get their act together as it will either force AMD to change or if Intel simply keep creating quality hardware the OCing scene will shift predominantly [back] to Intel. The vast majority of people don't get too bogged down in brand loyalty, if a piece of hardware is dominating the OCing charts and the scene is lively around it, people will buy it.


I think most OCers hate AMD already because this plattform is suck a pain in the a** to overclock (maybe because it's barely stable at stock with all the power saving features, see USB / PCIe 4 issues). There is not one recipe just read all the arguments between PB and all Core or all the hate about the Whea 19s. It's just not fun to wonder if you choose the right approach and so much work to try all combinations and compare them.


----------



## rossi594

ManniX-ITA said:


> You need to be generous with VSOC, likely between 1.20V and 1.25V.
> I don't think you can get anywhere with 1.11V.
> But it depends on you CPU. Below you are probably going to get lower or unreliable scores
> Same for CCD & IOD, be generous, set it to the max before the performances are dropping.
> I need around 50mV more on all compared to the best voltages for FCLK 1900.
> Not sure the same metric can be used on a single CCD.


I can not comfirm this. I was able to do 2000 flck on 1.040vsoc adding 20mv improved stability I saw no further benefit after that. for the 2033 I was running yesterday I just punched in ~1.15vsoc to make it easier. Maybe I just go exceptionally lucky on my soc, but not all of them need that much voltage. I feel like it's more about the terminations and timings.


----------



## Bloax

rossi594 said:


> I can not comfirm this. I was able to do 2000 flck on 1.040vsoc adding 20mv improved stability I saw no further benefit after that. for the 2033 I was running yesterday I just punched in ~1.15vsoc to make it easier. Maybe I just go exceptionally lucky on my soc, but not all of them need that much voltage. I feel like it's more about the terminations and timings.


I had a funny experience on a b550 Unify-X; the same voltages that performed the best at 2000 FCLK....
..Were the same voltages that 1900 FCLK was stable/errored once every 60+ minutes with








Mind you that this is the same chip that was doing 2000 FCLK just fine on a barely-functioning ITX board:








Mysterious!


----------



## rossi594

Bloax said:


> I had a funny experience on a b550 Unify-X; the same voltages that performed the best at 2000 FCLK....
> ..Were the same voltages that 1900 FCLK was stable/errored once every 60+ minutes with
> View attachment 2546743
> 
> 
> Mind you that this is the same chip that was doing 2000 FCLK just fine on a barely-functioning ITX board:
> View attachment 2546744
> 
> 
> Mysterious!


Not at all, those fclk „holes“ are / were very common. Especially on older Agesa Versions. On 1.2.0.2 I could not even run 1900/1933/1966 but 2000 was smooth and possible at low vsoc.


----------



## byDenoso

What's the max safe SOC voltage for Zen2 (Ryzen 3000) for 24/7?
1,2v?


----------



## ManniX-ITA

*TL;DR
Don't use any BIOS with AGESA 1.2.0.4 and above if you are fine running AGESA 1.2.0.3 and below; it can permanently change your CPU and it's probably going to be worse*

I guess the fact my 5950X was one of the very first production batches is likely the reason of these changes
Except the CO counts, the other changes made my CPU more similar to the later production batches behavior

CO counts:

Had to change +4 positive on Core 4 (my best core 1#1) and +2 on Cores 0,7,8,15
In general all lost something except the 15 (nice & useless)
Max Boost clocks
Core 0: -10 MHz
Core 1: -25 MHz
Core 2: -40 MHz
Core 3: -30 MHz
Core 4: -50 MHz
Core 5: -5 MHz
Core 6: -35 MHz
Core 7: -5 MHz
Core 8: -35 MHz
Core 9: -45 MHz
Core 10: -35 MHz
Core 11: -50 MHz
Core 12: -45 MHz
Core 13: -35 MHz
Core 14: -25 MHz
Core 15: +40 MHz


DF C-State:

Doesn't seem Disabled is unstable like before (but I didn't test much)
Now as I have seen happening to others my boost clock is hard capped at 5050 MHz if Disabled, wasn't the case before
vCore offset:

Could use a small positive bump to stabilize CO and get better performances, now almost all cores gets unstable with CoreCycler
PLL VDD18 / 1P8:

Always been a no-go for my CPU, dropping performances above 1.84V and sinking after 1.87V
Now I can voltage up and I need it, cause i can't use a vCore offset anymore and it helps recovering lost performances
Benchmarks:

It's a hit and miss, some are similar while others a bit worse
I have lost a bit in GB5 ST (around 20 points) and have similar results in MT but more reproducible (probably thanks to the higher VDD18)
CB23 is roughly the same as before, probably cause it's AVX2
Corona is roughly the same, more consistent probably thanks to the higher VDD18
Linpack probably due to the higher VDD18 starts with the same GFlops was settling before in the 3rd run
The monero miner hashrate increased dramtically at FCLK 1900 (like with AGESA 1.2.0.5)


----------



## ManniX-ITA

@Taraquin 
I've updated my post with PWM and LLC stuff



rossi594 said:


> I can not comfirm this. I was able to do 2000 flck on 1.040vsoc adding 20mv improved stability I saw no further benefit after that. for the 2033 I was running yesterday I just punched in ~1.15vsoc to make it easier. Maybe I just go exceptionally lucky on my soc, but not all of them need that much voltage. I feel like it's more about the terminations and timings.


It depends on the CPU, some samples are less needy and single CCD much less.
RAM timings are a key factor for VSOC, if you are running very relaxed memory timings (but why?  better not), less is required
From 1.15V and above can be doable but you need to check the performances.
I can run FCLK 2000 stable at 1.17V with relaxed RAM timings but half of the benchmarks will score less or fluctuating


----------



## Taraquin

ManniX-ITA said:


> You may need the AMD PBS menu unlocked in your BIOS; there's an option to change the IF sync which is CLKREQ# and I need it Enabled.
> Depends on the CPU, the BIOS/AGESA and the FCLK.
> On some BIOS releases I don't need it for 1933/1966 but always for 2000.
> Above it doesn't help.
> 
> You need to be generous with VSOC, likely between 1.20V and 1.25V.
> I don't think you can get anywhere with 1.11V.
> But it depends on you CPU. Below you are probably going to get lower or unreliable scores
> Same for CCD & IOD, be generous, set it to the max before the performances are dropping.
> I need around 50mV more on all compared to the best voltages for FCLK 1900.
> Not sure the same metric can be used on a single CCD.
> 
> Unfortunately the single CCD power budget is very constrained.
> I'm not sure the higher FCLK can compensate.
> 
> The memory timings changes are not very significant, the lower latency and bandwidth should compensate plenty.
> 
> My advice is to take a baseline with the best settings you can get at FCLK 1900 with Geekbench 5.
> Once you upload to the online browser set it as Baseline with the button on the right.
> Then you can test the changes with FCLK and compare.
> The main ST and MT scores are important but relative.
> You need to watch closely all the single tests to see the effect of your changes.
> 
> AES-XTS scores, especially MT, will tell you what is the best VDDG CCD voltage.
> The other tests mostly which is the best VDDG IOD.
> Then you can move on fine-tuning the rest.
> 
> VDD18 is very important. Next in line.
> Still depends on CPU and AGESA.
> Before running AGESA 1.2.0.5 my best voltage at FCLK 2000 was 1.810V, now it's 1.900V...
> At FCLK 1900 best was 1.840V, now I don't know yet.
> 
> Other things to check are:
> 
> Scalar: depending on other settings could be best 10x or 1x/4x
> vCore offset: a small positive bump can help (0.0125-0.0250V)
> I used to get it more stable and performant with 0.0125V, after AGESA 1.2.0.5 can't use any or the cores will get unstable
> 
> DF C-State: Depends on CPU/AGESA as well.
> Had to use Enabled before AGESA 1.2.0.5, now seems working fine also Disable
> 
> Once you have some consistent results with GB5, run CB23 and CPU-z bench to validate you get same/better scores.
> Then if you are really confident more benchmarks.
> I would suggest that you spend some time configuring the monero minero xmr-stak-rx.
> You are not going to see scaling up with a 5600X.
> Only with more than 10 cores there's scaling up.
> But you must get the same or slightly better hashrate.


Thx! In aida, dram calc test and SOTTR I see no perf benefit above 1.11v soc/1.03v iod, below everything is stable, but I get slightly worse performance.


ManniX-ITA said:


> @Taraquin
> I've updated my post with PWM and LLC stuff
> 
> 
> 
> It depends on the CPU, some samples are less needy and single CCD much less.
> RAM timings are a key factor for VSOC, if you are running very relaxed memory timings (but why?  better not), less is required
> From 1.15V and above can be doable but you need to check the performances.
> I can run FCLK 2000 stable at 1.17V with relaxed RAM timings but half of the benchmarks will score less or fluctuating


I'm at 16 flat 29 ras, 45 rc, 280 rfc, others quite tight at 4000 and 1t gdm off. If I raise soc and iod to 1.15v and 1.06v I get no benefit in aida and a few others, haven't tried linpack though.


----------



## rossi594

ManniX-ITA said:


> @Taraquin
> I've updated my post with PWM and LLC stuff
> 
> 
> 
> It depends on the CPU, some samples are less needy and single CCD much less.
> RAM timings are a key factor for VSOC, if you are running very relaxed memory timings (but why?  better not), less is required
> From 1.15V and above can be doable but you need to check the performances.
> I can run FCLK 2000 stable at 1.17V with relaxed RAM timings but half of the benchmarks will score less or fluctuating


I was running 4000cl16 with 1,060 vsoc (because auf gdm). I never saw any vsoc making any difference for my timings.

I tryed 1.24 vsoc with cl14, but maybe I was to conservative on vdimm.


----------



## byDenoso

ManniX-ITA said:


> *TL;DR
> Don't use any BIOS with AGESA 1.2.0.4 and above if you are fine running AGESA 1.2.0.3 and below; it can permanently change your CPU and it's probably going to be worse*
> 
> I guess the fact my 5950X was one of the very first production batches is likely the reason of these changes
> Except the CO counts, the other changes made my CPU more similar to the later production batches behavior
> 
> CO counts:
> 
> Had to change +4 positive on Core 4 (my best core 1#1) and +2 on Cores 0,7,8,15
> In general all lost something except the 15 (nice & useless)
> Max Boost clocks
> Core 0: -10 MHz
> Core 1: -25 MHz
> Core 2: -40 MHz
> Core 3: -30 MHz
> Core 4: -50 MHz
> Core 5: -5 MHz
> Core 6: -35 MHz
> Core 7: -5 MHz
> Core 8: -35 MHz
> Core 9: -45 MHz
> Core 10: -35 MHz
> Core 11: -50 MHz
> Core 12: -45 MHz
> Core 13: -35 MHz
> Core 14: -25 MHz
> Core 15: +40 MHz
> 
> 
> DF C-State:
> 
> Doesn't seem Disabled is unstable like before (but I didn't test much)
> Now as I have seen happening to others my boost clock is hard capped at 5050 MHz if Disabled, wasn't the case before
> vCore offset:
> 
> Could use a small positive bump to stabilize CO and get better performances, now almost all cores gets unstable with CoreCycler
> PLL VDD18 / 1P8:
> 
> Always been a no-go for my CPU, dropping performances above 1.84V and sinking after 1.87V
> Now I can voltage up and I need it, cause i can't use a vCore offset anymore and it helps recovering lost performances
> Benchmarks:
> 
> It's a hit and miss, some are similar while others a bit worse
> I have lost a bit in GB5 ST (around 20 points) and have similar results in MT but more reproducible (probably thanks to the higher VDD18)
> CB23 is roughly the same as before, probably cause it's AVX2
> Corona is roughly the same, more consistent probably thanks to the higher VDD18
> Linpack probably due to the higher VDD18 starts with the same GFlops was settling before in the 3rd run
> The monero miner hashrate increased dramtically at FCLK 1900 (like with AGESA 1.2.0.5)



Only on Ryzen 5000? or Ryzen 3000 too?
I'm on AGESA 1.2.0.4


----------



## ManniX-ITA

Taraquin said:


> I'm at 16 flat 29 ras, 45 rc, 280 rfc, others quite tight at 4000 and 1t gdm off. If I raise soc and iod to 1.15v and 1.06v I get no benefit in aida and a few others, haven't tried linpack though.


You need to test with the monero miner, GB5, CB23, CPU-z and also Linpack Extreme (and anything you can throw at it)
Otherwise everything looks good but under the hood maybe isn't



byDenoso said:


> Only on Ryzen 5000? or Ryzen 3000 too?
> I'm on AGESA 1.2.0.4


Didn't notice any change on my 3600XT and I've tested 1.2.0.4
I'd say only limited to 5000s but I can't be sure


----------



## ManniX-ITA

Audioboxer said:


> Any time a CPU stress stability app was in action, the mouse pointer would become unresponsive and the VRMs would sing.


Do you remember which PWM switching frequency did you set for CPU and SOC?


----------



## Audioboxer

ManniX-ITA said:


> Do you remember which PWM switching frequency did you set for CPU and SOC?


I've always used AUTO until I tried 1000 on the CPU the other day because you mentioned it, didn't help the USB disconnects. So prior to AGESA 1.2.0.5 they would have been on AUTO.

Back to testing my 4533 profile again and one thing I've noticed is the VDDGs become a lot more important at this frequency. Running them at the same as I run them with 3800 produces errors. That being 0.975v CCD and 1.05v IOD.

I'm guessing handling the higher data rate simply results in these needing to be higher. Interesting anyway, something for anyone else to be mindful of if they're pushing high memory frequencies on AMD. Don't ignore your VDDG or assume it will be happy where it was at 3800!


----------



## domdtxdissar

ManniX-ITA said:


> Sorry, I don't want to convince you otherwise as you have your faith but my experience running at FCLK 2000 for over 1 year is very different
> My 5950X is pretty average and can show matching and exceeding performances over FCLK 1900 in every benchmark.
> Except some of those where I'm thermal constrained; FCLK 2000 is more demanding in thermals and needs a lot more voltage.





ManniX-ITA said:


> I live every day in the pipedream


Then just show me and silence me forever 

Its easy, just show me screenshot of linpack + y-cruncher at static *low* cpu clockspeeds (please no excuse about throttling) with zentimings up
First at 2000:4000 then at 1900:3800.. it should not take more than ~6 min
*(if you have temp issues run at 4300/4200 @ 1000mv or whatever, it dont matter as long as all benchmarks are done at same cpu clockspeed)*

Then i can replicate both cpu clockspeed and timings on my system at 1900:3800 and compare the results..Either your 1900:3800 score is below par, or your system can actually show scaling in said heaviest benchmarks from above.

Its so easy to prove me wrong on this, but still 1 year later we are having this very discussion again, WHY ?


----------



## ManniX-ITA

domdtxdissar said:


> Its easy, just show me screenshot of linpack + y-cruncher at static *low* cpu clockspeeds (please no excuse about throttling) with zentimings up


Well, that would be difficult cause I'm throttling at 4500/4400 as well 
It's a Dark Rock Pro 4 cooler, silent but limited.

And again why Linpack and y-cruncher?
It seems that you are just wiping your mind from the RAM bandwidth usage topic 
They are not the right tests for FCLK.

You can test yourself with xmr-stak-rx, the monero miner. 
That's a good test that can show FCLK scaling.
It works for me even if it's topping 90c, for sure it's even more obvious for you.

If we can find another benchmark which is really using the FCLK bandwidth (at least constant 40 Gbps in HWInfo), it's not AVX2 and doesn't put too much thermal stress on the CPU I'm in.

Otherwise, I have to wait to move to water cooling (which I should have done 6 months ago but I'm lazy and prioritized other stuff) and get a new decent AGESA.
With 1.2.0.5 can run same exact CL14 settings at 3800 and 4000 MHz.
On 1.2.0.1 is not possible sadly.


----------



## Audioboxer

7/1/7 looks like it will be OK, but given I'm watercooled I'll probably just run 7/3/4.

7/2/6 I might consider, running RttWr on 1 just to reach Park 7 seems a bit excessive.


----------



## Bloax

Unless there's a practical benefit to it - such as being able to run a 8-16-8-16 GB config with Park /5-/6-/5-/6 (A1-A2-B1-B2) on z690 with a kit that keeps up in voltage/timing requirements in A1/B1 (heh) - then there's no point to running the krazyest park termination you can shove into the sticks.

Well, that or if it can do better max-performance settings with it, of course.

By the way - does tFAW 12 (4x lowest RRD/WTR ) offer any improvements?


----------



## Audioboxer

Bloax said:


> Unless there's a practical benefit to it - such as being able to run a 8-16-8-16 GB config with Park /5-/6-/5-/6 (A1-A2-B1-B2) on z690 with a kit that keeps up in voltage/timing requirements in A1/B1 (heh) - then there's no point to running the krazyest park termination you can shove into the sticks.
> 
> Well, that or if it can do better max-performance settings with it, of course.
> 
> By the way - does tFAW 12 (4x lowest RRD/WTR ) offer any improvements?












Never even knew tFAW 12 could boot, guess I can test it!


----------



## nick name

Audioboxer said:


> View attachment 2546770
> 
> 
> Never even knew tFAW 12 could boot, guess I can test it!


I think it's been discussed before and that the conclusion was that anything less than 16 doesn't actually do anything. I've booted with super low tFAW before and it had no impact.


----------



## Audioboxer

nick name said:


> I think it's been discussed before and that the conclusion was that anything less than 16 doesn't actually do anything. I've booted with super low tFAW before and it had no impact.


@Veii will probably know. Wouldn't be surprised if it's not doing anything










Even in an hour I'd expect an unstable prominent secondary timing to trip Karhu.


----------



## MrHoof

Yes 4x tRRDS is the lowest anything lower will be auto corrected i am pretty sure. Dont think has anything to do with tWTRS.

edit: from old veii post.
Four Activate Window or sometimes also called Fifth Activate Window is a timing restriction. tFAW specifies a window within which only four activate commands can be issued. So, you can issue ACTIVATE commands back-to-back with tRRD_S between them, but once you have completed 4 activates you cannot issue another one until the tFAW window expires.


----------



## Audioboxer

Looks like 1.57v is needed for tRFC of 216. 1.55~1.56v are unstable.

Will let it go longer though given it's tRFC.


----------



## PJVol

nick name said:


> anything less than 16 doesn't actually do anything


Yep. Nothing is changed going from tFAW 1
6(min) to 16.


----------



## Audioboxer

Audioboxer said:


> View attachment 2546793
> 
> 
> Looks like 1.57v is needed for tRFC of 216. 1.55~1.56v are unstable.
> 
> Will let it go longer though given it's tRFC.












And this is why you test for a long time!










1.58v is needed for 216.

So as I discovered before with some brief testing, below 120ns the voltage requirements climb very quickly!


----------



## ManniX-ITA

@domdtxdissar

After spending some time looking for a CL14 profile that would work both at 3800 & 4000 MHz, I decided to look for a low static CPU clock & voltage to run this test.
Ended up choosing 4.2 GHz for both CCDs and 1.2V vCore; I can get almost same all-core scores as PBO without going over 91c. Good enough to not kill my CPU too quickly 

*I think this is proof that there's at least one dual CCD that can run FCLK 2000, even while logging lots of WHEA 19, without performance degradation in all benchmarks (including y-cruncher and Linpack xTreme).
More than that, it can perform better than FCLK 1900 at same memory timings and take advantage of the increased memory bandwidth and latency.*
But I'll wait you can reproduce the same and your considerations before I say it's final and conclusive 

What I can't test yet is if this advantage can be kept with higher clocks.
But I have good faith with the right voltages tweaking and proper thermals it works just as well.
At least the above can confirm that just running FCLK 2000 is not an issue.
Maybe here you can help running first the same at 4.2 GHz and then with higher static clocks until your setup can hold.
I love your benching sessions 

About stability you have to trust me.
I've run more or less this FCLK 2000 config with PBO for 6 months and enjoyed the most stable and performing system since I switched to Ryzen.
It is stable at FCLK 1900 as well but with quite a few USB disconnection issues that are reduced to almost never at FCLK 2000.
So the latter wins.

Maybe it's not obvious for everyone so I'll state again: voltage settings are really important and can be very different between specific setups.
They also change within the same setup depending on PBO configuration and can be again different between PBO and a Static OC based on the clock you run at.

I've made some tests with the voltages working best for PBO and some "safe" low voltages and some quickly scouted best settings for 4.2 Static.
Unfortunately some BIOS screenshots for voltage changes didn't get saved on the USB stick.
Next time I'll double check the file is really saved, seems an MSI bug. I'm 100% sure I did it every time....
Luckily, I saved Zentimings screenshot for every config and remember the changes so I could deduce the BIOS settings.

I've run the monero miner for 15 minutes only on the first FCLK2000_PBO config; it's so stable and consistent at 4.2 GHz (unless the voltages are not enough) that the scores are the same after few minutes or 15.


CONFIGVSOC SETCCDIODVDD 1P8XMR-STAK-RXy-CRUNCHERLINPACKGB5 ST / MTCPU-Z ST / MTFCLK2000_PBO1.2375​1080​1140​1.870​*18808 / 18833*​*64.971 s*​*629*​*1528* / 18979​586 / 12267​FCLK2000_OPTSAFE1.2000​1050​1120​Auto​18629 / 18685​66.735 s​615​1524 / *19007*​586 / 12271​FCLK2000_SAFE1.1250​1000​1000​Auto​6083 / 6907​Crash​Not run​1509 / 18509​586 / *12288*​FCLK1900_PBO1.1875​1050​1080​1.850​17793 / 17801​67.618 s​620​1514 / 18563​586 / 12270​FCLK1900_PBO2K1.2375​1080​1140​1.870​17889 / 17892​67.377 s​619​1515 / 18511​586 / 12262​FCLK1900_SAFE1.1250​1000​1000​Auto​18428 / 18456​66.354 s​620​1522 / 18716​586 / 12278​

Considerations about the configs:

*FCLK2000_PBO*
This configuration is based on the best voltages settings (although preliminary yet, thanks to the "new old" after AGESA 1.2.0.5) for PBO
Overall best scores, except GB5 MT which is in the margin of error

*FLCK2000_OPTSAFE*
With this configuration I tried to find best low voltages for 4.2 GHz, could have been improved but it was too much time consuming. Something between this and the PBO settings would be the best for static 4.2

*FCLK2000_SAFE*
These are same "low voltages" for FCLK1900_SAFE config, obviously non enough. VRM was literally screaming like a trapped mouse running the miner and y-cruncher (until black screen and reset)

*FCLK1900_PBO*
Based on the best voltages for PBO which are probably not the best for a Static OC 4.2 but good enough for Linpack. Other benchmarks are suffering

*FCLK1900_PBO2K*
Same settings for PBO FCLK2000, definitely too much and counter productive

*FCLK1900_SAFE*
Safe low voltages, tried some small variations but didn't get much more than this. Linpack wouldn't budge from 620, GB5 MT and the miner would drop performances. y-cruncher always above 66s.

Clearly for FCLK 2000, to get the best results in all benchmarks, voltages needs to be higher and very fine-tuned.
FCLK 1900 it's easy-peasy and lower voltages just works better, higher are counter productive very quickly.

If you find better settings for you CPU, I can try to reproduce with mine.

(In the settings there's APBDIS set to Mission Mode; it was probably a sloppy finger when I took the screenshots. I don't usually set it to 0 as it ruins PBO boost but doesn't have an effect on Static OC)

*Looking at these scores made me thinking about someone, I don't remember who, that claimed to know every and all throttle limiters in Ryzen CPUs.*
And insisted stubbornly that IOPS are always a 1:1 result of the effective clock whatever PBO or a static OC is being used.
Probably anyone that spent some time doing OC knows this is not even remotely true but it's so evident here that why not mark it again.

These all-core results are very close to what I get with PBO due to thermal constraints.
With the obvious and gigantic difference that PBO runs these benchmarks mostly at 4.3-4.6 GHz clocks in all-core.
The monero miner runs at 4.325 MHz (which is 2 GHz higher for 16 core and 4 GHz higher for 32 threads) but the hashrate is about the same.

This a an HWInfo logging for a GB5 MT run with PBO:










As you can see the CPU spent much more time between an average of 4.4 and 4.6 GHz than 4.2 GHz.
Yet the IOPS advantage was just barely 400 points more than running at static 4.2 GHz.

But wait, it's not the case to start screaming again at AMD that they are liars (they know they are ahah).

Here's the timeline:











There are some crucial differences that makes the IOPS throttling more than worthwhile:

You still get better performances overall
Specific workloads can run steady between 4.4 and 4.6 GHz
Maximum temperature is 5c lower with PBO
There are some operations where the IOPS is purely based on clock speed and there PBO wins big time
Even if the reported clocks are "a bit misleading", it's still a big advantage, not a cheap marketing trick.

And a few other considerations from this;

PBO is always doing thermal throttling above 50c.
At first is very very subtle but after 60c starts being more evident.
It's not only about clock gating but it quietly reduces IOPS in a fine balance to keep thermals on the target.

You really need to take every metric give by any Ryzen counter about clocks, voltages, power, etc with a grain of salt.
Always assume the worst, it's either a lie or hiding something 
All metrics are "rounded", "calibrated" or "mitigated".

Eg. there's a very easy check to verify the CCD and Core temperatures are conveniently reporting an average (or just "forgetting" some sensors data).
You need your best core reporting 60-70c under load and already at max stable CO count.
PBO thermal throttling is set to 90c by Auto default. Now go to PBO settings and change the thermal throttling limit to 110c.
Mine almost regularly crashes under Geekbench 5 ST.

Why would it crash if was peaking 70c?
Because it wasn't.
The truth is that internally it's peaking to 90c and throttled.
By raising the limit to 110c it just goes over 90c and gets unstable.
Lowering the throttling limit is clear that it goes up to 100-105c internally before crashing.
But this very high temperature is not reported by the Core/CCD temperature sensors.
Those are reporting only what AMD wants us to see...

Anyway, have a nice Sunday that's all 🤟

*Here's the zip containing all the BIOS settings and runs screenshots:*





__





dom_comparison_static_42.zip







drive.google.com


----------



## rossi594

Audioboxer said:


> View attachment 2546867
> 
> 
> And this is why you test for a long time!
> 
> View attachment 2546868
> 
> 
> 1.58v is needed for 216.
> 
> So as I discovered before with some brief testing, below 120ns the voltage requirements climb very quickly!


You are righ but ....

If you wait long enough everything will error. You heatsoak the cooler first then the case / board then the room and all goes boooooom.
When I am pushing 600w I can see the room temp rising on my ambient sensors xD.


----------



## rossi594

domdtxdissar said:


> Then just show me and silence me forever


@ManniX-ITA I think you did it


----------



## ManniX-ITA

rossi594 said:


> @ManniX-ITA I think you did it.


Hope not... I love discussing, arguing and bitching with dom on this topic & all the others


----------



## Audioboxer

rossi594 said:


> You are righ but ....
> 
> If you wait long enough everything will error. You heatsoak the cooler first then the case / board then the room and all goes boooooom.
> When I am pushing 600w I can see the room temp rising on my ambient sensors xD.


I'm watercooled, temps remain consistent during testing and therefore errors coming hours in are to do with instability, not thermals.

I've done some brief testing with super low tRFC previously and found these same results, the closer you get to 110ns the voltage requirements skyrocket.










Currently testing 109ns and to even get it booting into Windows requires above 1.6v.

This is the first time I've done proper longer term testing, just proving the earlier findings and now showing what is required for stability.


----------



## rossi594

Audioboxer said:


> I'm watercooled, temps remain consistent during testing and therefore errors coming hours in are to do with instability, not thermals.
> 
> I've done some brief testing with super low tRFC previously and found these same results, the closer you get to 110ns the voltage requirements skyrocket.
> 
> View attachment 2546872
> 
> 
> Currently testing 109ns and to even get it booting into Windows requires above 1.6v.
> 
> This is the first time I've done proper longer term testing, just proving the earlier findings and now showing what is required for stability.


I am watercooled too. That does only slow overheating down until you heat soak your room. (GPU, CPU, Dimms and even my Optane drive are all water cooled with an external Mo-Ra3 360x360mm with 9 Noctua NF-F12s ~550rpm on it).

As I said I can literally see the temp on the ambient temperature sensor climbing after the loop has been heatsoaked.

If you want I can log it for you and show you a chart.


----------



## ManniX-ITA

rossi594 said:


> As I said I can literally see the temp on the ambient temperature sensor climbing after the loop has been heatsoaked.


Time to hang the MoRA outside the window?
Kidding 

You both have valid points; Audioboxer is right that these errors are not due to thermals. His temperature is steady, they come from the settings.

You are right as well; when you are under load the temperature can raise and the memory starts erroring.
But these are different errors from the above.

I usually test with steady temperatures and then I just fire OCCT GPU before running TM5.
My 3090 will quickly terraform my case in an hellish volcano.

But the best and less boring stability test is always a long gaming session.


----------



## Audioboxer

rossi594 said:


> I am watercooled too. That does only slow overheating down until you heat soak your room. (GPU, CPU, Dimms and even my Optane drive are all water cooled with an external Mo-Ra3 360x360mm with 9 Noctua NF-F12s ~550rpm on it).
> 
> As I said I can literally see the temp on the ambient temperature sensor climbing after the loop has been heatsoaked.
> 
> If you want I can log it for you and show you a chart.


My max temps reach around 30~34 degrees depending on voltage, errors aren't being produced at those temps due to thermals. It'll be timings.










1.62v will need a bit longer than 30 minutes for a full soak, but after even an hour or two those temps above will be around the same. My fans aren't even spinning right now as water temp is only 28.5 degrees. Fans kick in at 30 degrees. Memory stability testing doesn't tend to trigger that.

While tRFC is temp sensitive and it's entirely possible super low tRFC needs lower temps than the rough average where temps can hurt low tRFC on aircooling (around 42 degrees), Karhu should have no problem passing 10~12 hours.

If your Karhu is erroring out hours in I'd consider it not stable.


----------



## rossi594

Audioboxer said:


> My max temps reach around 30~34 degrees depending on voltage, errors aren't being produced at those temps due to thermals. It'll be timings.
> 
> View attachment 2546875
> 
> 
> 1.62v will need a bit longer than 30 minutes for a full soak, but after even an hour or two those temps above will be around the same. My fans aren't even spinning right now as water temp is only 28.5 degrees. Fans kick in at 30 degrees. Memory stability testing doesn't tend to trigger that.
> 
> While tRFC is temp sensitive and it's entirely possible super low tRFC needs lower temps than the rough average where temps can hurt low tRFC on aircooling (around 42 degrees), Karhu should have no problem passing 10~12 hours.
> 
> If your Karhu is erroring out hours in I'd consider it not stable.


I am not saying that that's a temp error. I am just saying if you test for 20h in a small room like mine you might error just because of that. In your case I would run the gpu on full load just in case maybe you thermals look very different when you do that.

What cooling setup are you running?
I took a screenshot yesterday, because I was really suprised that with GDM off the Dimms got measurably hotter than the water temperature. (~2°C).

At 1.50v I have ~6°C difference between room temperature and Ram temperature. So I would break 40°C on the Dimms at ~34°C room temperature (so a hot summer day).
Does yours perform better than that? And if yes did you use expensive thermal pads on the memory?

The screenshot for reference:


----------



## Audioboxer

rossi594 said:


> I am not saying that that's a temp error. I am just saying if you test for 20h in a small room like mine you might error just because of that. In your case I would run the gpu on full load just in case maybe you thermals look very different when you do that.
> 
> What cooling setup are you running?
> I took a screenshot yesterday, because I was really suprised that with GDM off the Dimms got measurably hotter than the water temperature. (~2°C).
> 
> At 1.50v I have ~6°C difference between room temperature and Ram temperature. So I would break 40°C on the Dimms at ~34°C room temperature (so a hot summer day).
> Does yours perform better than that? And if yes did you use expensive thermal pads on the memory?
> 
> The screenshot for reference:
> View attachment 2546877


4 rads, 3x360 and 1x120 and 17 fans in total lol. When the fans kick in my water temps tend to stay around 30~31 degrees even with a 2080Ti dumping in 373w of heat. Memory temps are higher under that load, but it tends to be a degree or two. At 1.55v this means memory temps of around 35 degrees.

1.62v may result in a degree higher, I would need to test.

I live in the UK so hot days are quite rare!

Memory thermal pads are GELID GP-Ultimate so they were a bit pricey. But £20 odd or whatever it was, was a small price to pay in comparison to what this memory kit cost lol.

I get you now, but my memory temps are never crossing 40 degrees which is where most thermal errors begin. As I said that might drop a bit lower at a tRFC this low, we'll see.


----------



## rossi594

Audioboxer said:


> 4 rads, 3x360 and 1x120 and 17 fans in total lol. When the fans kick in my water temps tend to stay around 30~31 degrees even with a 2080Ti dumping in 373w of heat. Memory temps are higher under that load, but it tends to be a degree or two. At 1.55v this means memory temps of around 35 degrees.
> 
> 1.62v may result in a degree higher, I would need to test.
> 
> I live in the UK so hot days are quite rare!
> 
> Memory thermal pads are GELID GP-Ultimate so they were a bit pricey. But £20 odd or whatever it was, was a small price to pay in comparison to what this memory kit cost lol.
> 
> I get you now, but my memory temps are never crossing 40 degrees which is where most thermal errors begin. As I said that might drop a bit lower at a tRFC this low, we'll see.


It's all about deltas (those should stay roughly the same at elevated room temps because the component temperatures of cpu and gpu are much higher). My radiator setup is similar to yours (360x360x50mm) other than you running more fans. If I turned mine up my water temp is very close to room temperature, it's just unnecessary and load to do so xD. 
I was just curious if your dimms get hotter than the water temperature, because I calculated the heat flux and decided to cheap out of on the memory thermal pads (I used the included ek ones which are like 1.5-1.7W/mk). Or maybe your waterblock is better - I use the EK Monarch.


----------



## Audioboxer

rossi594 said:


> It's all about deltas (those should stay roughly the same at elevated room temps because the component temperatures of cpu and gpu are much higher). My radiator setup is similar to yours (360x360x50mm) other than you running more fans. If I turned mine up my water temp is very close to room temperature, it's just unnecessary and load to do so xD. I was just curious if your dimms get hotter than the water temperature, because I calculated the heat flux and decided to cheap out of on the memory thermal pads (I used the included ek ones which are like 1.5-1.7W/mk).


Yeah they are, right now



















Ambient is measured from a commander pro temp sensor that is outside the case at the back.

I know people don't trust those flow meters, but they tend to be fine for temps. So 28.5 degrees in the reservoir, 27.9 degrees at one point in the loop under a Karhu load. Pretty normal.

Flow rate of 1.6 is at a D5 running at 75%. Running at 100% shows 2.2~2.4. D5 is a bit noisier at 100% than 75%, so I like it here and haven't really noticed any thermal degradation under 100%. At least not at this flow rate. IIRC anything above 1L is good, but that is relying on the reading of the flow meter above which is likely not accurate, so ymmv and do testing.


----------



## rossi594

Audioboxer said:


> Yeah they are, right now
> 
> View attachment 2546880
> 
> 
> View attachment 2546881
> 
> 
> Ambient is measured from a commander pro temp sensor that is outside the case at the back.
> 
> I know people don't trust those flow meters, but they tend to be fine for temps. So 28.5 degrees in the reservoir, 27.9 degrees at one point in the loop under a Karhu load. Pretty normal.
> 
> Flow rate of 1.6 is at a D5 running at 75%. Running at 100% shows 2.2~2.4. D5 is a bit noisier at 100% than 75%, so I like it here and haven't really noticed any thermal degradation under 100%. At least not at this flow rate. IIRC anything above 1L is good, but that is relying on the reading of the flow meter above which is likely not accurate, so ymmv and do testing.


Thank you.

I think that confirms my thesis & calculations that you won't get any real benefit from expensive thermal pads on memory. (I really did not want to take all the cooler apart again xD, but 8 high quality pads are almost as expensive as my memory). Those things are fine for temps but their flow rates are all over the place. But that doesn't really matter that much. Some people on hardwareluxx go crazy with 3-4 pumps in series just to flow more but I don't really see the point of that.


----------



## Audioboxer

rossi594 said:


> Thank you.
> 
> I think that confirms my thesis & calculations that you won't get any real benefit from expensive thermal pads on memory. (I really did not want to take all the cooler apart again xD, but 8 high quality pads are almost as expensive as my memory). Those things are fine for temps but their flow rates are all over the place. But that doesn't really matter that much. Some people on hardwareluxx go crazy with 3-4 pumps in series just to flow more but I don't really see the point of that.


Considering 3 of my rads are Corsair XR5s which are rebranded HWLabs and super restrictive, 2 pumps is total overkill. My flow meter spinner in my GPU block and the one I have later in the loop spin fast AF at 75% so we're all good lol.

My fourth rad is a EK SE Slim, but this is because in order to get a radiator AND fans in the back portion of the Lian Li O11 XL, a 30mm radiator is a few mm too big. 27mm JUST fits.

And this is with the 3 blocks, CPU, GPU and memory.

I guess the one thing I have done is spent time doing my hard pipe bends, no right angle pieces which I know also reduce flow a little. I guess if someone has like 5~10 of these and everything I had above, flow would come down a bit.

But still, a D5 at 100% and it's doing 99.5% of people's loops out there. When I was planning for watercooling there was some really bad advice, widespread, on Reddit, that you should be _scared_ running more than like 2~3 rads and 2 blocks on 1 D5. Absolute nonsense IMO. The Corsair XD5 is just a normal D5 with a reservoir.

As for thermal pads, you're likely spot on. As long as they aren't total trash it's very likely there is no need to spend stupid money on them. The only thing I'd question is my 2 DIMM block from Bykski has no fins. Good for flow, possibly not as good for thermals. The Barrow 2 DIMM block actually has fins in it. Was tempted to change to it to see, but given the temps my memory runs at there is just no point. If I can stay around 35 degrees nothing is erroring out at that temp, within reason.


----------



## ManniX-ITA

rossi594 said:


> cheap out of on the memory thermal pads


I wouldn't have done that.
DIMMs really don't need a lot of thermal pads and it makes a difference.
True the absolute delta is not that much; but 2-3c degrees can be game changing.
You have to consider the thermal sensor is not on-die but on-PCB.
Means a 2-3c delta on-pcb is lower than the real delta inside the IC which is probably 4-5c.


----------



## rossi594

Audioboxer said:


> Yeah they are, right now
> 
> View attachment 2546880
> 
> 
> View attachment 2546881
> 
> 
> Ambient is measured from a commander pro temp sensor that is outside the case at the back.
> 
> I know people don't trust those flow meters, but they tend to be fine for temps. So 28.5 degrees in the reservoir, 27.9 degrees at one point in the loop under a Karhu load. Pretty normal.
> 
> Flow rate of 1.6 is at a D5 running at 75%. Running at 100% shows 2.2~2.4. D5 is a bit noisier at 100% than 75%, so I like it here and haven't really noticed any thermal degradation under 100%. At least not at this flow rate. IIRC anything above 1L is good, but that is relying on the reading of the flow meter above which is likely not accurate, so ymmv and do testing.


it depends on your coolers most CPU coolers (with jet plates) benefit from higher flow rates.
Memory temps will definitely not.

I am running ~130L/h (2,17L/m) to lower the CPU temps. I did not notice the ddc getting quieter at lower speeds (this is about 70% speed) and the delta between CPU temperatures and water was getting smaller.


----------



## ManniX-ITA

Audioboxer said:


> The Barrow 2 DIMM block actually has fins in it.


Fins are really unnecessary... with the drawback of maybe getting clogged over time.
You need to consider the heat transfer surface between the DIMM heat-spreader and the bottom of the block.
It's a very small surface, even with four DIMMs.
The whole block internal surface where the water flows is way bigger and more than adequate.

My opinion is that is better to focus on good thermal pads & paste and materials.
Copper instead of aluminum considering the small surfaces can be very helpful.


----------



## Audioboxer

rossi594 said:


> it depends on your coolers most CPU coolers (with jet plates) benefit from higher flow rates.
> Memory temps will definitely not.
> 
> I am running ~130L/h (2,17L/m) to lower the CPU temps. I did not notice the ddc getting quieter at lower speeds (this is about 70% speed) and the delta between CPU temperatures and water was getting smaller.


When gaming my CPU tends to go between 60~70 depending on the game. This is with PBO settings of 270/168/220 and telemetry pushing it even harder.

You probably are right with the pump at 100% it would/could be a few degrees lower, but these temps are fine for those PBO settings and a 5950x. It's my GPU temps I watch the most, keeping the 2080Ti under 45 degrees results in better boosting. It's normally around 40~42 degrees depending on the game. This is with a 373w BIOS and running at max allowed voltage. Memory overclock of +1050 as well.

I'm quite sensitive to noise, more so pitches/frequency. So while I wouldn't say my D5 is terribly noisy at 100%, I have noticed there is quite a substantial pitch change in noise at different speeds. There is a period between like 50% and 75% which is pretty awful. It's funny, a higher speed results in a more pleasant noise! Though once over 80% it introduces another change to the pitch when all my fans are off I can make out. Hence enjoying 75% for when PC is on desktop/idle/work use and fans are off.

Should probably make a curve for the pump to go to 100% when fans are on (usually gaming) lol. I might just do that when I have 5 mins!


----------



## rossi594

Audioboxer said:


> The only thing I'd question is my 2 DIMM block from Bykski has no fins. Good for flow, possibly not as good for thermals. The Barrow 2 DIMM block actually has fins in it. Was tempted to change to it to see, but given the temps my memory runs at there is just no point. If I can stay around 35 degrees nothing is erroring out at that temp, within reason.


The EK-Monarch also has no fins. Even older CPU blocks don't have fins. The surface area between the adapters and the block is bigger than your cpu heatspreader and there is much less heat I would doubt you can measure any difference when adding fins.



ManniX-ITA said:


> DIMMs really don't need a lot of thermal pads and it makes a difference.
> True the absolute delta is not that much; but 2-3c degrees can be game changing.


Is there data on that? Because from @Audioboxer und my measurements and my calculations there does not seem to be a difference there.



ManniX-ITA said:


> You have to consider the thermal sensor is not on-die but on-PCB.
> Means a 2-3c delta on-pcb is lower than the real delta inside the IC which is probably 4-5c.


I know, I added the sensor (my dimms don't ship with one). But the aluminium of the memory adapters and the SI of the memory chips are both highly heat conductive (>100W/mk) so the only limiting factor can be the thermal pad.

If the sensor position (on the pcb) makes any difference then it should read a slightly higher on dual sided dimms and slightly lower on single sided ones. (but PCBs really good at conducting heat, significantly better than even the best thermal pads that you could use on memory doesn't include graphene pads for cpus).


----------



## Audioboxer

rossi594 said:


> The EK-Monarch also has no fins. Even older CPU blocks don't have fins. The surface area between the adapters and the block is bigger than your cpu heatspreader and there is much less heat I would doubt you can measure any difference when adding fins.
> 
> 
> Is there data on that? Because from @Audioboxer und my measurements and my calculations there does not seem to be a difference there.
> 
> 
> I know, I added the sensor (my dimms don't ship with one). But the aluminium of the memory adapters and the SI of the memory chips are both highly heat conductive (>100W/mk) so the only limiting factor can be the thermal pad.
> 
> If the sensor position (on the pcb) makes any difference then it should read a slightly higher on dual sided dimms and slightly lower on single sided ones. (but PCBs really good at conducting heat, significantly better than even the best thermal pads).


Yeah, yourself and Manni have confirmed to me there is no point in a RAM block with fins! lol. The Bykski block was nice and cheap as well, so it's all good. Between Bykski and Barrow there is a lot of money to be saved! More so on fittings. I think when it comes to CPU/GPU blocks and your rads, it is better to pay a bit more from the best rated brands.

My CPU block is a Corsair XC7. I've seen they released their Pro range late last year claiming up to a 4 degree reduction in some cases, but meh, don't feel the need to upgrade.

The conundrum I have incoming is when my EVGA step up finally comes, Corsair sadly don't make a 3080FTW3 waterblock, so I'll need to source from another brand. Shame, I really like the Corsair GPU blocks, the 2080Ti one looks really industrial.










Here is an hour at 1.63v. I got an error at 1.62v after 33 minutes. So it seems a tRFC of 109ns needs even more voltage!

So we're potentially looking at a 0.08v increase from 1.55v/117ns to 1.63v/109ns. Quite the increase just to push tRFC down.

IIRC Anta said around 1.6v for 110ns, so I'm a bit behind here. 1.55v managing 117ns is the real win though, that's a great result. Still a while to go though before being confident to say 1.63v for 109ns.

I can maybe see myself running 1.58v for 113ns, but 1.63v just to get to 109ns seems overkill. Any performance is probably MOE stuff here, even between 113ns and 117ns. So basically just running a much higher VDIMM for... bragging rights?  Though, pushing RAM for science is always fun, just to see where it can go. Even if it's not to a daily profile!

I guess if a higher VDIMM also helped other timings come down, but the rest of my timings are basically at ground floor level lol. tWTRS 2 will boot, but its super unstable. Same with tWTRL at 7. This is at 1.55v mind you. Guess I can try them again at 1.63v. Just throwing voltage at timings though is not something that always works!


----------



## rossi594

ManniX-ITA said:


> Fins are really unnecessary... with the drawback of maybe getting clogged over time.


Totally right on that. You were even faster than me 



ManniX-ITA said:


> Copper instead of aluminum considering the small surfaces can be very helpful.


This doesn't make any sense.










If you assume you would only use one side of the adapter (just to make sure there is no arguing about single vs dual side) and that the lowest tickness is ~1mm you would get at least 120*1 = 120mm² just for comparison a AMD Zen 3 CCD measures at 83.736mm² and outputs at least tripple the heat of a single memory module.

Copper blocks make sense avoid galvanic corrosion. Aluminium adapters are not in contact with water.
About the termal conductivity: (there were a lot of discussions about this back when there were aluminium coolers).










About this topic:
EKWB
Gamers Nexus

I updates this posts for easier reference.


----------



## Audioboxer

Fans at 75%, just shows the cost of silence lol.

edit - Fans at 100%










The aeroplane is now leaving the runway, but it brings with it a nice reduction of 6+ degrees!










Oooft, 1.63v not enough for 109ns. 1.62v error'd after 30 minutes, 1.63v at 2 hours. If this is like the tRFC of 113ns then one more bump in VDIMM will do it.

It's that and/or RttNom might be having an issue now at a high voltage. Will test! 1.64v is basically my VDIMM limit before memory starts to complain running at full capacity.


----------



## rossi594

I'm starting to feel like the 1.5v daily limit is bs. lots of people here run 1.55v there are X.M.P profiles with 1.6v for B-Die out there and some people run even more for longer.

I asked a few days ago if anybody killed their sticks yet, I had no replies ... I think I will start opening mine up a bit more =D


----------



## Audioboxer

rossi594 said:


> I'm starting to feel like the 1.5v daily limit is bs. lots of people here run 1.55v there are X.M.P profiles with 1.6v for B-Die out there and some people run even more for longer.
> 
> I asked a few days ago if anybody killed their sticks yet, I had no replies ... I think I will start opening mine up a bit more =D


1.5v is definitely not a limit at all. I think it was mostly "born in OCing communities" from knowing where thermals will get toasty for people not active cooling. If you have a fan pointed at your memory it will definitely let you get to 1.55v, let alone pushing towards 1.6v.

B-die is fine with that, you just have to be mindful over like 42 degrees tRFC can start to complain. So it could be a trade off in performance if your memory temps are reaching 50 degrees and beyond.

Some posters in this topic the last few pages have been discovering running something like 7/2/5 or 7/2/6 on Rtts helps thermal overhead. So there is that as well.

1.55v rated DR kits are sold. 1.6v rated SR kits are sold. 1.6v is fine on DR, it's just under retail circumstances with no active cooling 1.6v might even cause trouble at XMP.


----------



## rossi594

Audioboxer said:


> 1.5v is definitely not a limit at all. I think it was mostly "born in OCing communities" from knowing where thermals will get toasty for people not active cooling. If you have a fan pointed at your memory it will definitely let you get to 1.55v, let alone pushing towards 1.6v.
> 
> B-die is fine with that, you just have to be mindful over like 42 degrees tRFC can start to complain. So it could be a trade off in performance if your memory temps are reaching 50 degrees and beyond.
> 
> Some posters in this topic the last few pages have been discovering running something like 7/2/5 or 7/2/6 on Rtts helps thermal overhead. So there is that as well.
> 
> 1.55v rated DR kits are sold. 1.6v rated SR kits are sold. 1.6v is fine on DR, it's just under retail circumstances with no active cooling 1.6v might even cause trouble at XMP.


I thought people read the B-Die specs and didn't understand that 1.5v max peak voltage is part of the jedec DDR4 spec ... and thought it was something specific from B-Die or that it is daily safe because of that or the daily safe limit ...


----------



## Audioboxer

Past the point of error from before, letsss gooooo. Seems 109ns will be my floor anyway, can't go above 1.65v at full capacity.


----------



## ManniX-ITA

rossi594 said:


> I'm starting to feel like the 1.5v daily limit is bs. lots of people here run 1.55v there are X.M.P profiles with 1.6v for B-Die out there and some people run even more for longer.
> 
> I asked a few days ago if anybody killed their sticks yet, I had no replies ... I think I will start opening mine up a bit more =D


Always ran my b-die kits over 1.5V daily, mostly at 0/7/1 RRT, and so far so good 
Pump it up, you are watercooled!

Here's what I'm running now and it's not even with direct air cooling (actually with the 3090 blowing over them, no issues):













rossi594 said:


> Is there data on that? Because from @Audioboxer und my measurements and my calculations there does not seem to be a difference there.


No data, is my opinion based on deductions.
I guess when I'll move to water we can gather some data with Audioboxer, since we have a very similar setup, and yours.

Don't get me wrong, I didn't say it's a game changer for "normal" OC.
A small deltaT improvement can make a big difference for memory with high OC and keep it stable also under whole system load.
If you are not pushing it seriously doesn't matter; the profile above runs up to 59c!




rossi594 said:


> If you assume you would only use one side of the adapter (just to make sure there is no arguing about single vs dual side) and that the lowest tickness is ~1mm you would get at least 120*1 = 120mm² just for comparison a AMD Zen 3 CCD measures at 83.736mm² and outputs at least tripple of a single memory module.


I wouldn't compare a CPU with RAM.
They are too different in almost everything.

The amount of heat they need to dissipate; let's say 10W for one DIMM and 120W for a CCD.
The DIMM going over 40c starts blabbing nonsense, the CPU tops 90c with a deltaT of 40-60c.
The memory IC package for an SR kit is roughly 600 mm2 and there's no integrated heat-spreader.
A Zen3 CPU does have a massive copper heat-spreader over the dies which is roughly 1200mm2.

They have different needs and 1-2c less deltaT on a CPU hardly matters.
While on RAM it can be really something.



rossi594 said:


> Copper blocks make sense to not have galvanic corrosion aluminium adapters are not in contact with water.
> About the termal conductivity: (there were a lot of discussions about this back when there were aluminium coolers).





rossi594 said:


> This doesn't make any sense.


I think Copper or Aluminium does matter.
The goal is to reduce the deltaT against water and at the same time absorb thermal variations.

There are not many factors you can act on to reduce the deltaT on a commoners' custom loop.
You can improve the heat dissipation increasing the pump and/or the fans speed.
Or increase the heat dissipation efficiency of the block.
Considering that we all agree the first option is a no-go, the 2nd becomes more attractive.

Of course there's a cost to it...
Good thermal pads and paste for me it's a no brainer.
I've spent I think 20-25€ on excellent ones.
It's not like buying 200€ of Fujipoly for the GPU... you really think about that.

Copper is another option but it's hardly economically justifiable.
I've spent 30€ for the EK DIMM heat-spreaders and they are expensive.
For the Copper ones almost 90€...

But the much better Copper thermal properties and it does matter, much more on this specific use case than others.

Comparing "stuff" made with Copper or Aluminum like in the GN video is something different.
There are many different factors and constraints which are not pertinent here.

The EKWB blog post you can disregard it. Marketing stuff to justify an all Aluminum product series.

Our memory waterblocks are all Copper if I'm not wrong (EKWB, Alphacool and Barrows are all Copper nickel-plated).
Most if not all decent to high-end CPU and GPU blocks are Copper.

Galvanic oxidation only happens when different materials are in contact and not through water.
There's no electron flowing in the water unless you use some sort of metallic addictive.
In all blocks with mixed materials, like brass for the inlets/outlets, the Copper is insulated via a plastic material.
And the Copper is always nickel plated where is in contact with water; unless you buy a block which isn't cause Copper has a nice color.
But that's a cosmetic issue... just don't.

Copper everywhere because it's better of course.
The thermal conductivity of Aluminum is just 60% of Copper.
This already justifies all the effort 
Let's consider the low temperatures for RAM, 30-35c, and the deltaT of 5c.
If you can get close to that 40% improvement (which the block above can support since it's Copper) then 1-2c less is very likely achievable.

For this use case (but not only) there's another interesting characteristic.
Which I think is very important (still probably not worth the 60€ on top if you are not a freak but I'm looking at me here...) in this use case. 

Copper vs Aluminum means a massive increase in heat storage capacity.

I've learned about it while experimenting with TECs and trying to cooldown the hot side and the controller.
When you have a dynamic thermal load with a huge deltaT, that's where Aluminum starts to fail miserably.
You put a lot of sudden heat on and the temperature will sky rocket in a matter of seconds.
I've quickly moved for testing from a massive Alu heatsink with fans attached to a simple thick copper plate with a fan blowing over.
A controller can work for 10 minutes on a Copper plate before throttling, 1 minute on an Aluminum heatsink.

Aluminum mass is half of Copper and weights only 30%.
This means the amount of heat the HS can hold before its temperature will raise is huge.
Together with the much better heat capacity means the Copper HS can keep the same temperature much longer if there's an increase in heat transfer.
It does have more time to dissipate it and dissipate better than Aluminum.

Your cooling when reacting to load will raise the fan speeds and it will need time to bring down the water temp.
In this gap time the memory temp will raise quite a bit (eg. I'm looking at the 32c max temp on @Audioboxer screenshot) with an Alu HS.
The Copper HS will have all the time to compensate and the memory will probably stay steady in 1-2c range before the improved loop cooling efficiency kicks in.
Same for sudden high thermal loads from the CPU socket or the GPU warming up the whole case.
The Copper HS will hardly notice it while the Alu one will immediately transfer that heat back to the memory ICs.

At least that's what I thought when I spent these 90€ on the Copper HS


----------



## rossi594

ManniX-ITA said:


> No data, is my opinion based on deductions.
> I guess when I'll move to water we can gather some data with Audioboxer, since we have a very similar setup, and yours.


Sounds great, please let's do that.



ManniX-ITA said:


> I wouldn't compare a CPU with RAM.
> They are too different in almost everything.
> 
> The amount of heat they need to dissipate; let's say 10W for one DIMM and 120W for a CCD.
> The DIMM going over 40c starts blabbing nonsense, the CPU tops 90c with a deltaT of 40-60c.
> The memory IC package for an SR kit is roughly 600 mm2 and there's no integrated heat-spreader.
> A Zen3 CPU does have a massive copper heat-spreader over the dies which is roughly 1200mm2.
> 
> They have different needs and 1-2c less deltaT on a CPU hardly matters.
> While on RAM it can be really something.


Yes they are different but with cooling we are talking about thermodynamics. Even memory can't violate those. The ccd and the heatspreader have a certain contact patch. The HEAT-SPREADER spread this heat to allow the thermal paste to do a better job. It does not allow you to conduct more heat from the ccd to the heatspreader. (You can run into that limit on Ryzen single Die chips).

Either you can conduct the heat away from the component or you can't.



ManniX-ITA said:


> I think Copper or Aluminium does matter.


Please show me that wen you did the testing. Because even on higher heat loads with smaller areas the thermal paste / thermal pads are always the limiting factor, so as long as your conductivity exeeds that you should be good. If you take your calculation of 600 mm² for a stick of dual sided memory with the best fujipoly pads you can't conduct more heat to the aluminium than it can conduct (you have 5x the surface area but only ~1/10th of the thermal conductivity with the pads vs the aluminium).



ManniX-ITA said:


> Galvanic oxidation only happens when different materials are in contact and not through water.
> There's no electron flowing in the water unless you use some sort of metallic addictive.


A quick google search will show proove this as untrue.



ManniX-ITA said:


> In all blocks with mixed materials, like brass for the inlets/outlets, the Copper is insulated via a plastic material.


No there are cpu blocks where the brass of the threads touches the copper.



ManniX-ITA said:


> And the Copper is always nickel plated where is in contact with water; unless you buy a block which isn't cause Copper has a nice color.
> But that's a cosmetic issue... just don't.


No not all copper blocks are nickel plated. Go to any vendor they will sell one.



ManniX-ITA said:


> Copper everywhere because it's better of course.


Copper is everywhere because if you mix aluminium and copper you get galvanic corrosion and for gpus copper makes a difference.



ManniX-ITA said:


> This already justifies all the effort


I understand your thinking, as I said go try it and show us the results.



ManniX-ITA said:


> I've learned about it while experimenting with TECs and trying to cooldown the hot side and the controller.
> When you have a dynamic thermal load with a huge deltaT, that's where Aluminum starts to fail miserably.


The bigger the delta T the higher the conductivity of most materials. Aluminium is more conductive at higher temperatures. That's why you were struggeling with your TEC.

If you've seen the video you know that the AIOs are identical other than the cold plate. So it literally tests the difference in thermal conductivity between one and the other. If you want you can argue about testing methodology etc. either aluminium is conductive enough for it not to make a difference or not. They are using a much higher heat load than your memory would create. If they can barely measure it I'm confident you won't be able to either. 

It's the same with the block a passive cooler or a radiator. You can barely measure a difference. Even under high heat loads. How would there be a significant one under max 80w? My calculation even only includes one side. Do you think a dual sided stick could draw as much power as two ccds? I don't think you could get there with liquid nitrogen / helium.


----------



## Audioboxer

Happy to call it now, 1.64v for 109ns. Won't be able to go any lower with the VDIMM limitations. At least not to the tune of dropping it to 200. Given Anta's recommendation of multiples of 8 I don't think there is any point trying like 204.

Getting under 110ns at full capacity was nice 🤝


----------



## Audioboxer

Hmm, watch this space, possible benefit to running 1.64v is forcing tWTRS down to 2. Errors quickly on 2 at 1.55v 👀


----------



## Audioboxer

Probably happy to call this already, although I will now try and find out what voltage is needed above 1.55v to actually get tWTRS down to 2.


----------



## nada324

Hello, if i want to bump more Vdimm to DRAM what should i increase/decrease? Talking about RTTs, Cad bus & Proc ODT stuff

Really confused of what go up or weaker when changing Vdimm

Currently Running SR @1.52v Vdimm


----------



## MrHoof

@nada324
RTT Cad bus and ProcODT looks fine the way your running atm but do you have a fan on those?

The only thing I see improving with high volts is trfc and tRCDRD maybe but tRFC could also be capped cause of temperature
and pushing more voltage wont help in that regard. 


ProcODT might go lower but dont think it will make much diffrence.


----------



## nada324

MrHoof said:


> @nada324
> RTT Cad bus and ProcODT looks fine the way your running atm but do you have a fan on those?
> 
> The only thing I see improving with high volts is trfc and tRCDRD maybe but tRFC could also be capped cause of temperature
> and pushing more voltage wont help in that regard.
> 
> 
> ProcODT might go lower but dont think it will make much diffrence.


Yeah im using this fan: 










Although never got success with TRCDRD to 15, i guess not worth to push it more


----------



## domdtxdissar

ManniX-ITA said:


> @domdtxdissar
> 
> After spending some time looking for a CL14 profile that would work both at 3800 & 4000 MHz, I decided to look for a low static CPU clock & voltage to run this test.
> Ended up choosing 4.2 GHz for both CCDs and 1.2V vCore; I can get almost same all-core scores as PBO without going over 91c. Good enough to not kill my CPU too quickly
> 
> *I think this is proof that there's at least one dual CCD that can run FCLK 2000, even while logging lots of WHEA 19, without performance degradation in all benchmarks (including y-cruncher and Linpack xTreme).
> More than that, it can perform better than FCLK 1900 at same memory timings and take advantage of the increased memory bandwidth and latency.*
> But I'll wait you can reproduce the same and your considerations before I say it's final and conclusive
> 
> What I can't test yet is if this advantage can be kept with higher clocks.
> But I have good faith with the right voltages tweaking and proper thermals it works just as well.
> At least the above can confirm that just running FCLK 2000 is not an issue.
> Maybe here you can help running first the same at 4.2 GHz and then with higher static clocks until your setup can hold.
> I love your benching sessions
> 
> About stability you have to trust me.
> I've run more or less this FCLK 2000 config with PBO for 6 months and enjoyed the most stable and performing system since I switched to Ryzen.
> It is stable at FCLK 1900 as well but with quite a few USB disconnection issues that are reduced to almost never at FCLK 2000.
> So the latter wins.
> 
> Maybe it's not obvious for everyone so I'll state again: voltage settings are really important and can be very different between specific setups.
> They also change within the same setup depending on PBO configuration and can be again different between PBO and a Static OC based on the clock you run at.
> 
> I've made some tests with the voltages working best for PBO and some "safe" low voltages and some quickly scouted best settings for 4.2 Static.
> Unfortunately some BIOS screenshots for voltage changes didn't get saved on the USB stick.
> Next time I'll double check the file is really saved, seems an MSI bug. I'm 100% sure I did it every time....
> Luckily, I saved Zentimings screenshot for every config and remember the changes so I could deduce the BIOS settings.
> 
> I've run the monero miner for 15 minutes only on the first FCLK2000_PBO config; it's so stable and consistent at 4.2 GHz (unless the voltages are not enough) that the scores are the same after few minutes or 15.
> 
> 
> CONFIGVSOC SETCCDIODVDD 1P8XMR-STAK-RXy-CRUNCHERLINPACKGB5 ST / MTCPU-Z ST / MTFCLK2000_PBO1.2375​1080​1140​1.870​*18808 / 18833*​*64.971 s*​*629*​*1528* / 18979​586 / 12267​FCLK2000_OPTSAFE1.2000​1050​1120​Auto​18629 / 18685​66.735 s​615​1524 / *19007*​586 / 12271​FCLK2000_SAFE1.1250​1000​1000​Auto​6083 / 6907​Crash​Not run​1509 / 18509​586 / *12288*​FCLK1900_PBO1.1875​1050​1080​1.850​17793 / 17801​67.618 s​620​1514 / 18563​586 / 12270​FCLK1900_PBO2K1.2375​1080​1140​1.870​17889 / 17892​67.377 s​619​1515 / 18511​586 / 12262​FCLK1900_SAFE1.1250​1000​1000​Auto​18428 / 18456​66.354 s​620​1522 / 18716​586 / 12278​
> 
> Considerations about the configs:
> 
> *FCLK2000_PBO*
> This configuration is based on the best voltages settings (although preliminary yet, thanks to the "new old" after AGESA 1.2.0.5) for PBO
> Overall best scores, except GB5 MT which is in the margin of error
> 
> *FLCK2000_OPTSAFE*
> With this configuration I tried to find best low voltages for 4.2 GHz, could have been improved but it was too much time consuming. Something between this and the PBO settings would be the best for static 4.2
> 
> *FCLK2000_SAFE*
> These are same "low voltages" for FCLK1900_SAFE config, obviously non enough. VRM was literally screaming like a trapped mouse running the miner and y-cruncher (until black screen and reset)
> 
> *FCLK1900_PBO*
> Based on the best voltages for PBO which are probably not the best for a Static OC 4.2 but good enough for Linpack. Other benchmarks are suffering
> 
> *FCLK1900_PBO2K*
> Same settings for PBO FCLK2000, definitely too much and counter productive
> 
> *FCLK1900_SAFE*
> Safe low voltages, tried some small variations but didn't get much more than this. Linpack wouldn't budge from 620, GB5 MT and the miner would drop performances. y-cruncher always above 66s.
> 
> Clearly for FCLK 2000, to get the best results in all benchmarks, voltages needs to be higher and very fine-tuned.
> FCLK 1900 it's easy-peasy and lower voltages just works better, higher are counter productive very quickly.
> 
> If you find better settings for you CPU, I can try to reproduce with mine.
> 
> (In the settings there's APBDIS set to Mission Mode; it was probably a sloppy finger when I took the screenshots. I don't usually set it to 0 as it ruins PBO boost but doesn't have an effect on Static OC)
> 
> *Looking at these scores made me thinking about someone, I don't remember who, that claimed to know every and all throttle limiters in Ryzen CPUs.*
> And insisted stubbornly that IOPS are always a 1:1 result of the effective clock whatever PBO or a static OC is being used.
> Probably anyone that spent some time doing OC knows this is not even remotely true but it's so evident here that why not mark it again.
> 
> These all-core results are very close to what I get with PBO due to thermal constraints.
> With the obvious and gigantic difference that PBO runs these benchmarks mostly at 4.3-4.6 GHz clocks in all-core.
> The monero miner runs at 4.325 MHz (which is 2 GHz higher for 16 core and 4 GHz higher for 32 threads) but the hashrate is about the same.
> 
> This a an HWInfo logging for a GB5 MT run with PBO:
> 
> View attachment 2546863
> 
> 
> As you can see the CPU spent much more time between an average of 4.4 and 4.6 GHz than 4.2 GHz.
> Yet the IOPS advantage was just barely 400 points more than running at static 4.2 GHz.
> 
> But wait, it's not the case to start screaming again at AMD that they are liars (they know they are ahah).
> 
> Here's the timeline:
> 
> View attachment 2546864
> 
> 
> 
> There are some crucial differences that makes the IOPS throttling more than worthwhile:
> 
> You still get better performances overall
> Specific workloads can run steady between 4.4 and 4.6 GHz
> Maximum temperature is 5c lower with PBO
> There are some operations where the IOPS is purely based on clock speed and there PBO wins big time
> Even if the reported clocks are "a bit misleading", it's still a big advantage, not a cheap marketing trick.
> 
> And a few other considerations from this;
> 
> PBO is always doing thermal throttling above 50c.
> At first is very very subtle but after 60c starts being more evident.
> It's not only about clock gating but it quietly reduces IOPS in a fine balance to keep thermals on the target.
> 
> You really need to take every metric give by any Ryzen counter about clocks, voltages, power, etc with a grain of salt.
> Always assume the worst, it's either a lie or hiding something
> All metrics are "rounded", "calibrated" or "mitigated".
> 
> Eg. there's a very easy check to verify the CCD and Core temperatures are conveniently reporting an average (or just "forgetting" some sensors data).
> You need your best core reporting 60-70c under load and already at max stable CO count.
> PBO thermal throttling is set to 90c by Auto default. Now go to PBO settings and change the thermal throttling limit to 110c.
> Mine almost regularly crashes under Geekbench 5 ST.
> 
> Why would it crash if was peaking 70c?
> Because it wasn't.
> The truth is that internally it's peaking to 90c and throttled.
> By raising the limit to 110c it just goes over 90c and gets unstable.
> Lowering the throttling limit is clear that it goes up to 100-105c internally before crashing.
> But this very high temperature is not reported by the Core/CCD temperature sensors.
> Those are reporting only what AMD wants us to see...
> 
> Anyway, have a nice Sunday that's all 🤟
> 
> *Here's the zip containing all the BIOS settings and runs screenshots:*
> 
> 
> 
> 
> 
> __
> 
> 
> 
> 
> 
> dom_comparison_static_42.zip
> 
> 
> 
> 
> 
> 
> 
> drive.google.com


Wow that's a lot more testing then the 6 minutes i requested! 

Had to abort my own 4500/4400 low vsoc (1.069mv @ 1900) testing to give this a spin..
















I have copied your memory timings and cpu clockspeed and done my own testing except it seems like you were running tRFC @ 350ns for the 1900:3800 profiles and tRFC @ 126ns for the 2000:4000 profiles (?)

I kept tRFC timings the same at all profiles: 1900:3800 = 132ns and 2000:4000 = 126ns

@ 1900:3800 our scores are very close and right where they should be 
Linpack Xtreme = ~624 gflops
Y-cruncher = 66.310 s







Your magic is happening at 2000:4000.. I can show scaling in linpack, but never at y-cruncher at the same time.
Its a "either or" in relations for voltage tuning to get performance in these two different benchmarks for me. (and belive me, ive spent many weeks trying to bruteforce different voltages)

2000:4000
Linpack Xtreme = ~629 gflops
Y-cruncher = 86.665 s (heavy throttling)







I have tried higher voltages all the way up to, and above your "flck2000_pbo" profile, but nothing seem to work.. Maybe custom tweaked bios with more unlocked options is the only hope for the Unify X MAX. (i'm running official bios atm)


ManniX-ITA said:


> *I think this is proof that there's at least one dual CCD that can run FCLK 2000, even while logging lots of WHEA 19, without performance degradation in all benchmarks (including y-cruncher and Linpack xTreme).
> More than that, it can perform better than FCLK 1900 at same memory timings and take advantage of the increased memory bandwidth and latency.*
> But I'll wait you can reproduce the same and your considerations before I say it's final and conclusive


Proof is in in the pudding and i take my hat off for you  It is conclusive.
You are the first one after over 1 year that can show true scaling at infinity fabric clockspeeds above 1900:3800. (even in the heaviest benchmarks such as Linpack and y-cruncher)
Featherweight and light benchmarks were never in contention as we all know its very easy to show high aida numbers

Hereby I give you the domdtxdissar's stamp of "*CERTIFIED SCALING ABOVE 1900 FCLK*" 

One other piece of information we learned from this testing is that y-cruncher actually scales with flck's above 1900, eventho a certain someone say it doesn't 
Lastly i gave the same benchmarks as spin with my other memory profiles at the same static 4200/4200mhz cpu OC

Daily 1900:3800
Linpack Xtreme = ~631 gflops
Y-cruncher = 64.432 s







Async 1900:4466
Linpack Xtreme = ~632 gflops
Y-cruncher = 61.066 s







Think maybe i could get higher scores by running the benchmarks one by one and/or with a reboot in-between them.


----------



## Veii

Bloax said:


> By the way - does tFAW 12 (4x lowest RRD/WTR ) offer any improvements?


Can't say clear no ~ learning about multiple refresh types (it's an exploit, going down to tRRD_L equal refresh) 
Learning about Refresh Control & Bank Level Parallelism
Don't fixate me on that yet, just 3x are odd - 1x , 6x or 4x


Spoiler: Information pieces, irrelevant to tFAW



Want to see when i'll be bored of data and ignore it again.
It's interesting right now & i think there might be a need of rethinking how to balance timings & work in imaginations, not in data (hence dimm controller mode & scheduling can not be read out)

Understand Anta's points slightly more, but i might lean out of the window to say that maybe even he misstook something about tRFC behavior
tRFC & tRC thing will remain to exist ~ it makes sense now, but it likely will need a slight redo defining/focusing on different refresh types/shedules

tRFC by itself is voltage base ~ we know that
RTT values , hence controlling RTT_NOM and PARK ~ which will change the state of
"when" cells need to recharge,
"when" it is combined and interleaved between banks
how low "tRP initial cell charge" can be before ACTivate command is issued (all cells are recharged at the very start, it's how you time it afterwards ~ where tRP is the delay that follows after everything already was recharged, and the delay that will be pushed in, to cover recharge of the row before it's accessed ~ it's an "added! put in place delay" to an already active discharge and recharge loop)
& how dynamic ODT might or might not schedule CAS & RAS "high" or low timings , meaning it controlling when clock signal will fall on tCL delay (column access) or tRAS delay (row access).
Soo this means more simplistic written, that RTT values will mess up the timings between primaries ! They will mess up the delays between tRP , tCL , tRAS & directly affect tRFC that needs to be supplied to cover this whole mess of delays 

Soo tRFC by itself is dynamic, and yes my little thing still makes sense just outside of the box 
The higher the tRFC delay is - the easier it would be for timings to be lowered ~ but the more of it exists, the less time can be spend for actual operations & bandwidth is lost, as DIMM (up to refresh state selected by itself or vendor hardcapped) will not do anything while cells recharge and usually also nothing while data is copied over "before" ACTivate command is issued.
(excluding that tRP and VDIMM go hand in hand, but will show faster or slower leakage by PCB layering and so can be lower independent of VDIMM by IC architecture or binning)
Data of one row usually needs to shift over, if this whole row needs to be read out. It is a destructive procedure, soo dimms sometimes have to send halt'ing singals where nothing can happen and nothing can move ~ till command has completed & data has been "moved" to somewhere it won't be lost
This, is an issue but the core design of cheap dram 

User Overclocker has to time timings correctly, else independent of what he supplies ~ DRAM will ignore it (signal being low) and halt/stall everything till data integrity has been met, another bank can be accessed or whole copy, discharge, recharge loop has been completed.
































I will write a better guide someday. But information is flaky (i'm an amateuer) and matching experience with information is still hard
(even more when it's split across multiple presentations and papers)
~ hence we/i've been abusing refresh cycle stacking and parallelization, without having a clear foundation why. Just going by the result with slight timing advice's from technical papers before *
* i would need to drop my tRC ~ tRFC trickery , drop tRAS trickery and go back to the core ~ in order to figure this bandwidth balancing out & why my high timings where faster
 (will take time till the next conclusive post & correct answer why it doesn't do anything and how to handle/balance tRFC and other primaries)

In general, longer delay won't cause issues and can increase effective bandwidth (tFAW)
But too low values will not show any benefits, as they are stalled everywhere else.
1x thing is an exploit within already running tRFC "exploits" without knowing it fully

Somebody needs to figure out (or me by time) if Micron utilizes Refresh scheduling aka tRFC "pausing" , like LPDDR4 and onwards use. I think DDR4 is capable, but it's about the vendors to implement or disallow 
* hence there would be no reason to ever drop bellow 350ns tRFC on them (Microns)


domdtxdissar said:


> One other piece of information we learned from this testing is that y-cruncher actually scales with flck's above 1900, eventho a certain someone say it doesn't
> 
> 
> Veii said:
> 
> 
> 
> *I can not decline that AVX2 has no FCLK scaling, even when running high FCLK
> How can you ? When you can't even run high FCLK ?
> It makes no sense to me, giving such bold statements.*
> 
> 
> Veii said:
> 
> 
> 
> *Last point to add more to this confusion,
> Can anybody even guarantee that AMD doesn't have fixed AVX2 throttler's set in place ~ as it is common on Intel*
> AVX2 has a fixed loadline droop, a fixed voltage droop ~ and we should expect still perfectly linear scaling and no throttle
> How does this work ?
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...

Unsure who this somebody is


----------



## ManniX-ITA

rossi594 said:


> Yes they are different but with cooling we are talking about thermodynamics. Even memory can't violate those. The ccd and the heatspreader have a certain contact patch. The HEAT-SPREADER spread this heat to allow the thermal paste to do a better job. It does not allow you to conduct more heat from the ccd to the heatspreader. (You can run into that limit on Ryzen single Die chips).
> 
> Either you can conduct the heat away from the component or you can't.


I'd be billionaire if I could violate thermodynamics laws...
But I don't think I ever suggested that 
Just that they are very different and I wouldn't compare them.

Sorry but maybe I got lost at some point, I was interrupted many times during a few hours before I could post this reply 

It was about "Copper instead of aluminum considering the small surfaces can be very helpful. "



rossi594 said:


> This doesn't make any sense.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> If you assume you would only use one side of the adapter (just to make sure there is no arguing about single vs dual side) and that the lowest tickness is ~1mm you would get at least 120*1 = 120mm² just for comparison a AMD Zen 3 CCD measures at 83.736mm² and outputs at least tripple the heat of a single memory module.


Now that I read again your answer I don't really understand the comparison with the CCD... and what is supposed to be 120mm2 with 1mm thickness?

What I meant is that I wouldn't compare them.
But maybe I misunderstood the your point totally.

What I meant is that despite the relatively small contact area between the WB base and the HS top, Copper can have benefits against Aluminium.
For the reasons I explained later.



rossi594 said:


> A quick google search will show proove this as untrue.


Google Is (Not Always) Your Friend 
I have raised this point about galvanic corrosion mixing Alu and Cu (Yes, I googled as well) to the Aquacomputer guy and he brutally shouted at me that I didn't know anything.
And he was right of course.
There's a lot of pseudo scientific stuff online about it and it's all BS.
The bluish/greenish stuff that grows on the raw Copper parts in a waterblock is oxidation but not galvanic corrosion.
Unless there's a direct contact between the two materials. Not if they are in contact through water.



rossi594 said:


> The bigger the delta T the higher the conductivity of most materials. Aluminium is more conductive at higher temperatures. That's why you were struggeling with your TEC.


No that's not what I meant.
Aluminum is slightly more conductive.
But that's not the point; it did struggle because of the very low heat storage and transfer capacity.
The Copper plate can hold much more and this keep a steady temperature.
Which makes easier to remove the heat.



rossi594 said:


> If you've seen the video you know that the AIOs are identical other than the cold plate. So it literally tests the difference in thermal conductivity between one and the other. If you want you can argue about testing methodology etc. either aluminium is conductive enough for it not to make a difference or not. They are using a much higher heat load than your memory would create. If they can barely measure it I'm confident you won't be able to either.


As said before it's a completely different problem.
You put such a high load on a very small copper plate on an AIO that has a very limited cooling capacity.
I don't really see how it's supposed to make any major difference...
But of course it's a big difference if it's a serious and big waterblock in a custom loop.

Memory is a different problem cause of the lower thermal load.
And I think Copper can be helpful exactly cause of that.



rossi594 said:


> It's the same with the block a passive cooler or a radiator. You can barely measure a difference. Even under high heat loads. How would there be a significant one under max 80w? My calculation even only includes one side. Do you think a dual sided stick could draw as much power as two ccds? I don't think you could get there with liquid nitrogen / helium.


The answer is low thermal load and high heat storage.
I have ordered these expensive Copper blocks so we'll see if they make a difference or not...


----------



## Veii

Audioboxer said:


> Happy to call it now, 1.64v for 109ns. Won't be able to go any lower with the VDIMM limitations. At least not to the tune of dropping it to 200. Given @anta777 recommendation of multiples of 8 I don't think there is any point trying like 204.
> 
> Getting under 110ns at full capacity was nice 🤝


Additive to post #16615 above, although it's messy written
Neither
Such things as "elastic refresh" based on Burst Length or predicted based on rank idle
or
Refresh pausing

Or even DARP, being dynamic with a counter ~ do exist on any specifications i got about AM4 or JEDEC
Maybe Dynamic Access Refresh Parallelization, method can be used with RC_PAGE together, as that seems to function
But above , i can not see or read or find anything that points to "elastic refresh" ~ tRFC, being a thing on AM4 at all
Nothing in JEDEC nothing on couple of AM4 technical & bios developement papers

But,
There are methods how we can utilize 2x and 4x fine granular refresh and other "trickeries" which i'm reading into
(it's not existing is wrong, it does exist, but mode registers do not set it [unless dynamic] & tSTAG does not factor it in [unless dynamic] ~ yet everyone should get their tRFC2/4 correct independent if it's used on post or not)
First shaping foundation, and understand why my methods work ~ hence nobody to this date could explain it to me 
Just likely


Veii said:


> * i would need to drop my tRC ~ tRFC trickery , drop tRAS trickery and go back to the core ~ in order to figure this bandwidth balancing out & why my high timings where faster
> (will take time till the next conclusive post & correct answer why it doesn't do anything and how to handle/balance tRFC and other primaries)


will be reality, and we need to start differentiating presets with asserted/kept in mind tRP and ones which are starting without, like this








I still think "all written rules" are correct - but they are for a different balance. It's not for "the whole picture"

This is what we can utilize and work out























That including to start utilizing tRC_PAGE ~ after fixing ourself on a "common tRAS, tCAS, tRC" rule
That's possible ~ but tRFC set, has to elapse
There is no way around that. The only way is to increase it and utilize parallelism , or decrease it and abuse discharge leakage. 
(but increasing it will hardcap potential maximum utilizable bandwidth)
Lower yet, would not mean "better" performance ~ as all depends on internal scheduling & set mode registers by either Dimm Vendor or by AMDs open/not open CBS options

We should start to remember, that RTTs are completely different behaving between Single Rank & Dual Rank dimms ~ soo will incluence tCAS, tRAS, tRC, tRCD
And this includes tRRD & tWTR timings ~ will behave different between ranks, up to what bios defaults as BankGroupEn mode (more often only _L ones mattes for the PCB, not _S)
Aka, we need a bios that shows all options that are readable through firmware, from the UMC ~ or a Zentimings version that auto refreshes and can be fixed in place , soo changes are seen in there
A lot of work i think, but unless this is a JEDEC thing my documents do not cover ~ it will be only an Intel thing and not an AMD behavior ~ soo Anta is not correct 
(he can't know that it's not existing here)


----------



## Veii

ManniX-ITA said:


> The bluish/greenish stuff that grows on the raw Copper parts in a waterblock is oxidation but not galvanic corrosion.
> Unless there's a direct contact between the two materials. Not if they are in contact through water.


Correct 
It does oxidize to air, pure fresh copper without having an oily preservation "skin/layer" or being a different grade of copper
EK blocks do oxidize to water, if nickel thing plates away & more often these things "burn" away















Soo the copper get's a gray'ish dark tint ~ while before it's mostly salmon colored
Actually here it's better visible








The "shades of copper"
* block is now fully copper clean & permanently submerged till plated
just this was an example of a "bad state of copper"

What works to preserve this is fluidy flux, or some oil like olive oil or surely machinery oil too
What also works, is to never make it leave distilled water, else it will oxidize to air

I'm a newby on watercooling and block above is a "gift" ~ which i consider plating again
But aluminium by itself should be faster in "pushing away" heat ~ while slower in soaking in heat
Copper is faster in soaking in heat, but i think it's slightly slower but twice the price of aluminium, in heat dissipation
~ to what i remember

Yet not every coppy oxidizes to air (unless i'm mistaken)
But every copper is treated to prevent oxidation to air ~ with some type of waxy or oily layer

EDIT:
I forgot
Every fluid will turn electrolytic in a loop after some time
It's by rubbing and passing through the fins, that it generates charge.
Galvanic corrosion will happen at any time, but it's about the metals you use and PH level the fluid is at.
If you maintain that, then it's unlikely to turn electrolytic

EDIT2:
Same for audio gear where "gold or silver" plated cables do not ! sound better , but prevent air oxidation of copper
In PC tech it's the same. Hence galvanic corrosion depends on the purity and "noble" of metal used, so also matters the layer of plating
A "high purity OCC copper" or "high purity silver" ~ with whatever N rating, example 5N rating soo 99.9999X purity
Once plated, will always ! lose it's purity , and for audio cables which are on the same "problem", they barely are sellable as 1N cables.
Everything ever plated, will ruin it's purity and so conductivity. (gold based contacts prevent oxidation and fading away by usage, but do nothing for conductivity)
I wouldn't wonder if this is also true for thermal conductivity based/measured on material purity

Soo a nickel plated "thing" never will have the properties of it's true "nickel" base or nickel block ~ only it's outer source element interaction (durability) with material property tradeoffs by loosing purity
Sadly this is now also done to GPU blocks, which are nickel plated aluminium (rare cases)
In general, aluminium or steel is plated first with a copper layer (many), before attaching a nickel layer on it.
(which i see is not done, to save cost these days)

Just again, amateur here ~ but that's usually the way tings go
Anything plated, that is sold for conductivity or purity ~ is marketing and lying.
This might not matter for short audio cable strands too, but does indeed matter, where 5N maaybe is on the edge of placebo. Yet 6N is too much, tho bellow 1N has measurable conductivity differences (anything plated)
Eh topic jump but this should not be different in the watercooling world, where purity matters
It only wouldn't matter, if purity does not change material properties - but i think it does, although plating things was revolutionary for us & the industry as a whole


----------



## SaarN

Planning on swapping my trusty ol' Ryzen 3600 with a beefier CPU (might be the X3D when it comes out and benchmarks are available).
So I just switched from a 3600CL18 DJR kit (? Corsair LPX ver. 3.55, unrecognized IC by Thaiphoon Burner) to a 4000CL16 B-die kit, to "be prepared" for something with more cores.
The DJR kit offered a lot of value for the amount of money I spent on it, as the B-die is twice~ more expansive.
I'm quite busy and don't have much time OC-ing, so instead of doing it manually, like I did with the DJR kit, I pretty much used the Excel top scores spreadsheet as a reference.
Passed 1 cycle of Memtest86 and 3 cycles of TM5 (anta777) without any errors. 1.5V DIMM voltage with max temp 50c.
Got a single corrected WHEA warning yesterday until I upped my VSOC voltage, and it seems fine for now, but who knows if that's actually stable or not.
Left is my DJR (obviously) and right is the b-die.
Left is also OC-ed with a 42.5x multiplier while the right one is just 42x. And I now have lots of crap running in the background (****ty services from Corsair, Razer and Asus, CPU is doing some light work even when "idle").
Anything worth trying until I upgrade the CPU or should I leave it as is?


----------



## ManniX-ITA

Veii said:


> Copper is faster in soaking in heat, but i think it's slightly slower but twice the price of aluminium, in heat dissipation
> ~ to what i remember


No difference in soaking in or out 
You get this impression cause it can store much more heat and you need more energy to change its temperature.



Veii said:


> It's by rubbing and passing through the fins, that it generates charge.
> Galvanic corrosion will happen at any time, but it's about the metals you use and PH level the fluid is at.
> If you maintain that, then it's unlikely to turn electrolytic


I had to call my cousin for that cause my chem knowledge is almost 30 years old and I wasn't that deep into.
He's one of the top world material chemists; Professor of Material Science and Technology (358 research works with 16490 citations).
Yes I was pretty embarrassed asking him about this kind of silly stuff and he probably thought I'm an idiot 
But I can fix his computer issues when he's lost so... 

If you don't have anything metallic in the coolant fluid there will never be galvanic corrosion.
Water doesn't move electrons and you need electrons shift to create galvanic corrosion.
It does happen in presence of water but only if the different materials are in direct physical contact.
I thought since water has electrical conductivity it could be a medium but nope, it's not like that.

There's a chance that you get galvanic corrosion if you put something in the water which is metallic.
Like a car anti-freeze additive, color additive or some synthetic oils.
Then it can happen also between different blocks like a CPU Copper block and the Res which is usually Aluminium.

Brass inlets/outlets if in contact with Aluminum can cause galvanic corrosion but they are usually insulated by a film, rubber or plating.
With Copper is not really an issue because they are at the same nobleness level.

In short is better to buy high quality blocks, if made in Copper with nickel-plating and avoid weird stuff in your coolant fluid.

I use Aqua DP Ultra in my test loop and so far all good:





__





Double Protect Ultra 5l Kanister


Double Protect Ultra 5l Kanister: DP Ultra ist das Ergebnis umfangreicher Tests und enthält speziell aufeinander abgestimmte Wirkstoffe, die einen optimalen Schutz vor Korrosion und eine optimale Kühlleistung garantieren. Die Herstellung erfolgt unter hohen Qualitätsstandards und der Verwendung...




shop.aquacomputer.de





Colored fluids are nice but you'll always pay the price...



Veii said:


> Anything plated, that is sold for conductivity or purity ~ is marketing and lying.


Yes, same as for audio cables.
The nickel plating is just there to prevent oxidation; which makes sense because once oxidation starts the drop in thermal performances is heavy (reduced flow and conductivity).
The concept is the same as the thermal paste between the CPU and the HS; it's a very thin layer.
Plating is really thin, not sure which is the usual thickness.
But it's so thin to make the weak thermal conductivity of nickel irrelevant.
The disadvantages are less than the advantages.


----------



## ManniX-ITA

SaarN said:


> Anything worth trying until I upgrade the CPU or should I leave it as is?


Better to post a Zentimings screenshot.

Is it a 32GB DR kit? I see in DRAM Calc rank is set to 2.
Then maybe SCL to 4 can help a bit.
I'd also set tRDWR/tWRRD to 8/3 or 8/4 if possible.
Is that 12/1 from Auto?

I would also try tRAS/tRC 26/40 or change tRP to 14 and 28/42.


----------



## SaarN

ManniX-ITA said:


> Better to post a Zentimings screenshot.


My bad. It is indeed a DR 2x16GB kit. It's an ITX so I got to get the most out of the 2 slots I got, heh.
I'll add the Zen Timings of the 2 kits. I assume I have more headroom with this kit, as the performance uplift isn't that great considering I moved from 3800 CL 16 to 3800 CL 14 (GDM on, though), and cut the TRFC by half. But it's 1k write the copy boost combined with a 2 ns reduction in latency, so I can't really complain.
My concern was that I'd invest a lot in it, then swap the CPU just to find out the memory controller is all different and it's not going to like the settings I had spent hours tuning and stress testing. So this was a sub-hour OC while the other one took me days of running Memtest86 (to avoid corrupting my OS) and then running hours of TM5.
Would have loved to see 60k read speed and another -1ns taken off, if possible, but y'know. Would have been easier to shave off a few nanoseconds with some overclocking, but my cpu doesn't like going out of spec, which I totally respect.


----------



## ManniX-ITA

domdtxdissar said:


> Wow that's a lot more testing then the 6 minutes i requested!


Couldn't resist the temptations of benchmarking 
Had to do so much other stuff... but that was fun!



domdtxdissar said:


> Had to abort my own 4500/4400 low vsoc (1.069mv @ 1900) testing to give this a spin..


Wow, 1.069mV?
I'll give it a try but I think my 5950X doesn't even post at the clock and voltage...



domdtxdissar said:


> I have copied your memory timings and cpu clockspeed and done my own testing except it seems like you were running tRFC @ 350ns for the 1900:3800 profiles and tRFC @ 126ns for the 2000:4000 profiles (?)
> 
> I kept tRFC timings the same at all profiles: 1900:3800 = 132ns and 2000:4000 = 126ns


Unbelievable... only the last FCLK 1900 SAFE run has the correct tRFC...
I didn't notice it when I took the screenshots, I was focusing on the voltages.
It's a very old bug it was really long time since I saw it last.
Should have done a shut down before the actual run.

Should have suspected something wrong with memory settings looking at that 1 seconds less in y-cruncher.
I'll have to run it again and update the results 



domdtxdissar said:


> @ 1900:3800 our scores are very close and right where they should be
> Linpack Xtreme = ~624 gflops
> Y-cruncher = 66.310 s


Similar but not the same... probably that 1c over 90c it's triggering throttling.
Annoying but ok, it doesn't change the final result 



domdtxdissar said:


> Your magic is happening at 2000:4000.. I can show scaling in linpack, but never at y-cruncher at the same time.
> Its a "either or" in relations for voltage tuning to get performance in these two different benchmarks for me. (and belive me, ive spent many weeks trying to bruteforce different voltages)
> 
> 2000:4000
> Linpack Xtreme = ~629 gflops
> Y-cruncher = 86.665 s (heavy throttling)





domdtxdissar said:


> I have tried higher voltages all the way up to, and above your "flck2000_pbo" profile, but nothing seem to work.. Maybe custom tweaked bios with more unlocked options is the only hope for the Unify X MAX. (i'm running official bios atm)


Sad 
But indeed you may need the AMD PBS menu and enabled CLKREQ#.
Without it my CPU crashes running Prime and the monero miner rate sinks.

Tried a similar FCLK 2000 config on another 5950X with an X570 Unify and it didn't work even with CLKREQ#.
Some CPUs just can't do it no matter what.

But on mine, depending on which BIOS I'm running, I don't need CLKREQ# at all FCLK.
So far always needed for 2033 and 2000 but often it's not for 1933 and 1966.
Did you try with 1966?

Hope you can soon run a modded BIOS 
Just flash it with Amiflash and forget flashrom.

But I don't see you running the monero miner....
That's a big mistake in my opinion.
It really helps a lot, sometimes more easily and quicker than GB5, to tweak voltages.
I can send you an easy-peasy config file if you don't want to spend time on it!



domdtxdissar said:


> Proof is in in the pudding and i take my hat off for you  It is conclusive.
> You are the first one after over 1 year that can show true scaling at infinity fabric clockspeeds above 1900:3800. (even in the heaviest benchmarks such as Linpack and y-cruncher)
> Featherweight and light benchmarks were never in contention as we all know its very easy to show high aida numbers
> 
> Hereby I give you the domdtxdissar's stamp of "*CERTIFIED SCALING ABOVE 1900 FCLK*"


Respect man 🤟

I'll proudly bear the stamp!
(I have added it to my signature as well ahah)



domdtxdissar said:


> One other piece of information we learned from this testing is that y-cruncher actually scales with flck's above 1900, eventho a certain someone say it doesn't
> Lastly i gave the same benchmarks as spin with my other memory profiles at the same static 4200/4200mhz cpu OC


Makes sense cause it's increased memory bw and latency that you can actually take advantage of.
The FCLK advantage (I have more bandwidth on the Infinity Fabric and I gain by using it) can be seen only if you use a massive amount of RAM bandwidth.
Like the monero miner; the miner is also latency sensitive so it's hard to compare against FCLK 1900.

I have some ideas about that.... let me test.

The problem of AVX/AVX2 throttling can be real.
Running at 4.2 GHz could just be enough to avoid it.
My doubt is that running at 4.4 GHz and above, even with static OC, the throttling will start negating the FCLK advantage.

Thanks for the cross-check and the stamp, have a nice Sunday!


----------



## Audioboxer

Seems like the bump to 1.58v was likely enough to drop tWTRS to 2.

No need to run 1.64v then, 1.58v for 113ns is a much better "trade off".


----------



## ManniX-ITA

SaarN said:


> My concern was that I'd invest a lot in it, then swap the CPU just to find out the memory controller is all different and it's not going to like the settings I had spent hours tuning and stress testing. So this was a sub-hour OC while the other one took me days of running Memtest86 (to avoid corrupting my OS) and then running hours of TM5.


Yes you'll need to re-test but I don't see any problem with it. A few TM5 runs for 1h30m will probably be enough.
The 5000 will be much more performant and these settings are expected to work.



SaarN said:


> Would have loved to see 60k read speed and another -1ns taken off, if possible, but y'know.


Not with this CPU and at 3800 MHz.
Hard to go over 60K at 3800, I think my best was 59.8K.

You also need to fix the tRFC, either use 252 or 256.
I'm using 252/187/115.
better to set tRFC2/tRFC4 as well or the latency will fluctuate.


----------



## ManniX-ITA

Audioboxer said:


> No need to run 1.64v then, 1.58v for 113ns is a much better "trade off".


Really nice for 1.58V!
How does it goes with Aida and y-cruncher pi25b?


----------



## Audioboxer

ManniX-ITA said:


> Really nice for 1.58V!
> How does it goes with Aida and y-cruncher pi25b?





















AIDA numbers are pretty much the same as what they are on the 1.55v profile, seems it's really down to my 5950x now in terms of latency results.

Speaking of that, my y-cruncher results on AGESA 1.2.0.3c were better. 1.2.0.5 has really buggered up CPU overclocking for me. My curve has been tested for stability, but between the voltage cap issues with EDC and all the boosting changes, I think I need to rework the whole thing.

But I cba doing it on AGESA 1.2.0.5 because who knows what 1.2.0.6 will bring. Fixes? More like, more bugs. Performance is fine just now for gaming and what not, just pushing numbers in benchmarks I'm not happy where the CPU is.


----------



## PJVol

ManniX-ITA said:


> I had to call my cousin for that cause my chem knowledge is almost 30 years old and I wasn't that deep into.
> He's one of the top world material chemists; Professor of Material Science and Technology (358 research works with 16490 citations).
> Yes I was pretty embarrassed asking him about this kind of silly stuff and he probably thought I'm an idiot
> But I can fix his computer issues when he's lost so...
> 
> If you don't have anything metallic in the coolant fluid there will never be galvanic corrosion.
> Water doesn't move electrons and you need electrons shift to create galvanic corrosion.
> It does happen in presence of water but only if the different materials are in direct physical contact.
> I thought since water has electrical conductivity it could be a medium but nope, it's not like that.


I certainly am not among the top world chemists, but it was my first hobby (hence the PJ - initials of famous danish chemist ).
AFAIR, the term "metallic" here is not correct, actually fluid has to have any electrolytic substance dissolved to be conductive, for example it may be an acid, or a ammonia water, etc.
(water is also very weak current conductor, according to its [H3O+] concentration 10E-14 mol/L).
I think more important is whether waterblock and radiator has electrical contact, for example through the case.



ManniX-ITA said:


> My doubt is that running at 4.4 GHz and above, even with static OC, the throttling will start negating the FCLK advantage.


I am pretty sure it will at some point. IIRC we've tested this scenario here in the first rounds of "fighting for the 1900+ performance scaling", when the 1200 agesa just rolled out.


----------



## Audioboxer

Sign me up for the tFAW under 16 does nothing camp, but lets stability test it anyway lol. I read what Veii said to me.

But just for fun, on the basis of 4xtWTRS.










Doesn't appear to hurt stability, but also probably doesn't do anything.


----------



## SaarN

ManniX-ITA said:


> Yes you'll need to re-test but I don't see any problem with it. A few TM5 runs for 1h30m will probably be enough.
> The 5000 will be much more performant and these settings are expected to work.
> 
> 
> 
> Not with this CPU and at 3800 MHz.
> Hard to go over 60K at 3800, I think my best was 59.8K.
> 
> You also need to fix the tRFC, either use 252 or 256.
> I'm using 252/187/115.
> better to set tRFC2/tRFC4 as well or the latency will fluctuate.


I tried your suggestions, but it seems like they haven't really done anything (?).
I managed to get an increase in performance by switching the interleaving thingy from 1 to 512, and I got an increase of 300mb read speeds.
Maybe there's a bottleneck somewhere else in my settings that makes this happen?
Tried scl 3 and 4, trdwr and twrrd both 8/3 and 8/4. It's all the same.
Tras and trc 26/40 booted fine, but still no performance increase. I'll try to add pics from my phone because my PC isn't responsive due to TM5.








Interleaving 1








Interleaving 512








Interleaving 512


----------



## domdtxdissar

Audioboxer said:


> View attachment 2547067
> 
> 
> Seems like the bump to 1.58v was likely enough to drop tWTRS to 2.
> 
> No need to run 1.64v then, 1.58v for 113ns is a much better "trade off".


I need 1.6 vdimm to run the same tWTRS 2 on my sticks, but i'm also running alittle tighter tRAS+tRC and tRDWR timings.











ManniX-ITA said:


> Did you try with 1966?


Seems to be worse then 2000 for me


ManniX-ITA said:


> But I don't see you running the monero miner....
> That's a big mistake in my opinion.
> It really helps a lot, sometimes more easily and quicker than GB5, to tweak voltages.












Here are a miner run at tight 1900:3800 profile from above, still running cpu at static 4200mhz so its a valid comparison to your testing









*19314 H/s* after 15min seems to indicate this "benchmark" also scales pretty good with low timings 








Soc power draw is 20w under load at these settings. What is your soc powerdraw at your 2000:4000 profile while running the miner ?
(under karhu ramtest soc power draw is ~21w @ PBO CO 4.8ghz as screenshot above show)

The good thing is that i know my 1900:3800 always will scale and never throttle when i push high cpu clockspeed, which give me alittle peace of mind since it one less thing to worry about when trying to get rankings on hwbot 

Just let me know if you want to see higher cpu clocks in anything 
_edit_
Async 1900:4466 run
*18940 H/s* after 15min
Alittle surprised this wasn't faster, but just goes to show that the miner aint all bandwidth hungry


----------



## rossi594

@ManniX-ITA I was typing my last reply very fast (had to get out of the house) and just scimmed / misread the copper part.

Copper is the default because it does not need to be plated, yes the surface color will change but it is a precious metal and will not easily react with other components / the liquid / electrolyte (we all don't want it to be one but it's almost impossible to completle avoid) in the loop. Most watercooling parts have a nickel electroplating, which is often not thick anough to be a chemical diffusion barrier or are not of high enough quality to come off. That's how things like in that ek block happen.









I was talking about this part of the adapter which has the smallest cross-sectional area and still does have to conduct some / half of the heat of the chips (if dual sided or not) that area is >120mm long and ~1mm thick (I did not measure mine but the pcb is >1mm and it looks very close on pictures).

BTW I use thermal pads on the pcb in between the memory modules as well, I would strongly recommend that.




Veii said:


> Copper is faster in soaking in heat, but i think it's slightly slower but twice the price of aluminium, in heat dissipation
> ~ to what i remember


There're two things at play here one is the specific heat capacity (of much heat / energy a certain weight of the material can hold). This only matters until your parts are heat soaked.
And the thermal conductivity which is how fast the material conducts heat. This is the big one. The good part is that we all know that energy doesn't come from nothing, so all the heat that goes into the copper / aluminum has to come trough the thermal pad / paste. (Air is a thermal insulator so I would ignore that marginal ammount). 

The thermal conductivity of those thermal pads / pastes is often stated. So as long as the copper / aluminum exeeds those specifications (you have to account for the surface area in this). It will be able to conduct the heat to the water / the cold from the water to the part quicker than more energy can be transfered into the metal. That should keep the metal at the water temperature in your loop.

(Do not use thermal pads between the ram adapters and the block, use thermal paste which is far more conductive).

The surface area on top of the ram modules is ~half as big as the chip area on a dual sided dimm, so you would not benefit from better pads on the memory if you don't have ~double the thermal conductivity on the pad / paste on top of the adapter. (Luckily most thermal pastes are ~70 W/mk while the best pads are 24/7 W/mk).

Maybe this is why @Veii noticed a difference between copper and aluminiums specific heat capacity. (btw. depending on the temperature copper can have a slightly higher heat capacity per volume because it is soo much heavier than aluminum).

Aluminums thermal properties depend a lot on the temperature








We are talking about the red area on the curve.

Copper outperforms aluminium on every point of the temperature range that we operate memory at.

(interesting read: http://nvlpubs.nist.gov/nistpubs/Legacy/NSRDS/nbsnsrds8.pdf)


----------



## ccxmonster

Hi there @Veii , i've researched many of your posts in this thread for being able to push my dual rank micron e-die(C9BLM,pcb revision b2,3600MHz xmp) to 4200+ MHz speed
and i noticed besides actual dram and related voltages i also need to tweak CPU_VDDP and CPU VDD voltage but those are not existing/not showing in my BIOS.

My processor is R5 5600X and mobo is MSI X570S Torpedo MAX.

can you or anyone provide me latest bios with unlocked cpu_vddp and cpu vdd in bios ?

i would be so so thankful .... 

other than this im also confused with ProcODT value, RTT values, CAD BUS Strengths and CAD BUS Setup values

i can currently run *unstable* 4200 MHz with gdm disabled CR2T ProcODT 40, RTT 0/3/1, 60-20-20-20 Strengths and tCKE 13 AddrCmdSetup:5 CsOdtSetup:5 CKESetup:20
powerdown and bgs disabled, bgs alt enabled, spread spectrum also disabled in bios, and nb/soc LLC set to mode 4.
voltage values are:

VDDP 0.9
VDDG_CCD 0.94
VDDG_IOD 1.060
VDIMM 1.5
VSOC 1.2125

maybe a unlocked and correctly changed cpu_vddp and cpu vdd voltages will solve stability issue.or issue is related to my proc odt / rtt / cad bus values .. i really dont know.

EDIT:Here is the current timings/voltages of my ram kits and all other stuff.


----------



## ArkSez

Hi Guys I've just got a replacement 5900x after the first one I had was a dud.

Now trying to push it and even at 3600DRAM/1800IF it's proving almost impossible for me. I have a Viper Steel 4400 which in theory should make this piss easy.

I've used the DRAM calculator and have spent a whole day yesterday tweaking and even copying other people with similar RAM + CPU with me at 3600MHZ CL16 to no avail.

I'm consistently getting error 2 and 5 with testmem using Extreme Anta. Is this a voltage issue? 1.46v is already too high for such conservative timings, even the tRFC is pretty loose for a B Die. The only thing I can think of is ProcODT? Do I have a dud RAM and should I get a new one instead? It's getting quite frustrating


----------



## Frosted racquet

@ArkSez for starters set Command Rate @2T and check RAM temperature.


----------



## ArkSez

Frosted racquet said:


> @ArkSez for starters set Command Rate @2T and check RAM temperature.


2T would impact performance no? And this thing doesn't have a built in temperature sensor.

I think I quit, just spent the last hour going nowhere as I already dropped the voltage to 1.43. My temperature gun shows 38C during the test.

Can you recommend a better RAM?


----------



## Frosted racquet

ArkSez said:


> 2T would impact performance no?


Yes, 1T command rate is sometimes difficult or impossible to stabilize. Change to 2T and put a fan overtop the RAM to ensure it's not overheating.


----------



## sonixmon

Frosted racquet said:


> Yes, 1T command rate is sometimes difficult or impossible to stabilize. Change to 2T and put a fan overtop the RAM to ensure it's not overheating.


Agree, at least test and eliminate the issue. You should get much better speeds and timings if it is decent B-Die. Also confirm correct ram slots are used if you haven't.


----------



## PJVol

ArkSez said:


> Do I have a dud RAM and should I get a new one instead?


They should work effortlessly with literally these settings:








Try to boot PC without RAM first (to reset possibly stuck settings), then insert modules in A2 / B2 and try again. You can also test modules one by one, to make sure they are fully functional and of the same bin.


----------



## ccxmonster

ccxmonster said:


> Hi there @Veii , i've researched many of your posts in this thread for being able to push my dual rank micron e-die(C9BLM,pcb revision b2,3600MHz xmp) to 4200+ MHz speed
> and i noticed besides actual dram and related voltages i also need to tweak CPU_VDDP and CPU VDD voltage but those are not existing/not showing in my BIOS.
> 
> My processor is R5 5600X and mobo is MSI X570S Torpedo MAX.
> 
> can you or anyone provide me latest bios with unlocked cpu_vddp and cpu vdd in bios ?
> 
> i would be so so thankful ....
> 
> other than this im also confused with ProcODT value, RTT values, CAD BUS Strengths and CAD BUS Setup values
> 
> i can currently run *unstable* 4200 MHz with gdm disabled CR2T ProcODT 40, RTT 0/3/1, 60-20-20-20 Strengths and tCKE 13 AddrCmdSetup:5 CsOdtSetup:5 CKESetup:20
> powerdown and bgs disabled, bgs alt enabled, spread spectrum also disabled in bios, and nb/soc LLC set to mode 4.
> voltage values are:
> 
> VDDP 0.9
> VDDG_CCD 0.94
> VDDG_IOD 1.060
> VDIMM 1.5
> VSOC 1.2125
> 
> maybe a unlocked and correctly changed cpu_vddp and cpu vdd voltages will solve stability issue.or issue is related to my proc odt / rtt / cad bus values .. i really dont know.
> 
> EDIT:Here is the current timings/voltages of my ram kits and all other stuff.
> View attachment 2547129
> 
> View attachment 2547130


Can anyone help me at this situation ? i think the problem is caused by too high cpu_vddp and too low cpu vdd for the desired memory clock and sadly i can't change them at the moment.
or could it be wrong ProcODT value ? or could it be wrong RTT and CAD BUS Strengths ? .. im totally confused now .. 
what i do mean by "unstable" is my system goes into black screen and then reboots (after some time of usage)


----------



## PJVol

ccxmonster said:


> what i do mean by "unstable" is my system goes into black screen and then


Tbh, I don't see the point in running fclk at 2100 unless you have got a 2-ccd sample. If not, then it's unlikely you can run it stable without insane voltages.
Have you tried them running at least @2000/4000 without performance regression in bandwidth+computational heavy tests?
And there's no need to touch cpu vddp, and some misterious "cpu vdd" (that is actually CPU Vcore and should be set to auto).


----------



## ccxmonster

PJVol said:


> Tbh, I don't see the point in running fclk at 2100 unless you have got a 2-ccd sample. If not, then it's unlikely you can run it stable with reasonable voltages.
> Have you tried them running at least @2000/4000 without performance regression in bandwidth+computational heavy tests?


yes i have tried 2000/4000 and it passed the test of tm5/Extreme config by anta777
at that time timings and all other stuff were like this:









i remember, after running this test i was reduced tRC to 58 and tRFC to 580 and it was also passed the test without single error.
sadly my cpu is not a 2-ccd one. so what memory clock should i try maximum ? should i stick to 4000 or is 4133 also doable ?


----------



## ArkSez

PJVol said:


> They should work effortlessly with literally these settings:
> View attachment 2547143
> 
> Try to boot PC without RAM first (to reset possibly stuck settings), then insert modules in A2 / B2 and try again. You can also test modules one by one, to make sure they are fully functional and of the same bin.


Thanks a lot for these settings. I can report back that the number of errors just increased by a boot tonne. I think my RAM is dead, I'll buy another pair and RMA this one in the meantime. I'll report back here if the new RAM will help at all.


----------



## ManniX-ITA

@domdtxdissar 

I've ran a very long and funny benchmarking session today 
Prolific, interesting and also surprising!

My goal was to discover why I was missing 4 GFlops in Linpack at FCLK 1900 and reproduce the scenario where Linpack was running at 629 GFlops but pi25b was throttling at FCLK 2000

TL;DR

*You didn't use exactly my settings; there's a chance this is why pi25b was throttling*
The different settings are; PrcODT, RTT, Setup, VDDP, CPU vCore, VSOC, VDDG CCD & IOD
*The loss at FCLK 1900 was due to ProcODT at 28 Ohm; mine was set conservative at 36.9*
I could use your memory setup including VDDP and get 623-624 GFlops as well at FCLK 1900 but they are unstable for me (TM5 fails at 6th cycle)
It's quite nice to discover Linpack can be used at FCLK 1900 4.2 Static to test the impact of ProcODT! 
Guess FCLK 2000 needs more frequency to show a difference since pumps same 629 GFlops with both PrcODT


*You used CPU vCore voltage at 1.1V instead of 1.2V*
I did select a generous vCore specifically to avoid it could become a problem, even if it was topping 91c
Your 5950X is a monster obviously but running at FCLK2000 is not the same, it's more demanding
All the benchmarks at FCLK 1900 with vCore 1.1v are running perfectly fine for me as well; *except y-cruncher pi25b*
I have validated that on my poor 5950X works fine at FCLK 2000 down to 1.15V
*Please test again with vCore 1.15V and 1.20V*

*In your FCLK 2000 screenshot CCD, IOD and VSOC are extremely low*
Maybe you made more tests and also tried the values in my runs but would be better if you try again with the higher vCore
I've tried your settings and I couldn't even run a few seconds Linpack or y-cruncher without getting a BSOD
Couldn't replicate your scenario with Linpack working fine and pi25b throttling
*I could replicate pi25b throttling (72s) due to low voltages; VSOC 1.2V CCD 1000 IOD 1080*
VDD18 helps with performances (2-3 GFlops in Linpack and 1 second in pi25b) but it doesn't throttle pi25b or cause crashes in Auto
Give a try with the settings in my first run VSOC 1.2375V CCD 1080 IOD 1140
Also test with the lowest voltages I've found working for mine; VSOC 1.2125V CCD 1080 IOD 1100
If they work, scale down until you drop performances or pi25b/Linpack scores are going down

*While trying to replicate your scenario I've discovered that very surprisingly my CLKREQ# behavior changed!*
This is another change in the CPU that came out from running with AGESA 1.2.0.5
Both at Static 4.2 GHz and with PBO now I don't get the same massive performance hit in Linpack and the monero miner
Actually now with Linpack I get better GFlops without CLKREQ#... about 5 GFlops more
Seems to be related to the thermal throttling at 90c; without CLKREQ# it reacts better, the opposite of before

I could run all the benchmarks of the run at the same speed with and without CLKREQ#
*Unfortunately when I've tested it with PBO after a while I've found a benchmark that showed that I still need it*
At the end of the usual round I've tested OCCT CPU and my scores were all below average 5950X
Enabled again CLKREQ# and all the scores with OCCT CPU
*OCCT CPU benchmark can show if there's an issue with FCLK, even better than the monero miner in this case*






domdtxdissar said:


> *19314 H/s* after 15min seems to indicate this "benchmark" also scales pretty good with low timings





domdtxdissar said:


> Async 1900:4466 run
> *18940 H/s* after 15min
> Alittle surprised this wasn't faster, but just goes to show that the miner aint all bandwidth hungry


Yes scales really well with both latency and bandwidth; that's why I decided to first find a working tCL 14 profile for both FCLK.
I've tried with tCL16 and the hashrate is higher than FCLK 1900 at tCL14 but only by a small margin.

Could you please monitor the HWInfo RAM bandwidth running the miner in de-sync?
I'm not sure it's not BW hungry, I suspect more that the bottle neck could be the latency or the Cores taxing the Infinity Fabric to access the RAM.



domdtxdissar said:


> Soc power draw is 20w under load at these settings. What is your soc powerdraw at your 2000:4000 profile while running the miner ?





domdtxdissar said:


> Just let me know if you want to see higher cpu clocks in anything


I'd like to see 4500/4400 Static with the monero miner and Linpack/pi25b.
That's for sure a target I want to test when I switch to water.



rossi594 said:


> I was talking about this part of the adapter which has the smallest cross-sectional area and still does have to conduct some / half of the heat of the chips (if dual sided or not) that area is >120mm long and ~1mm thick (I did not measure mine but the pcb is >1mm and it looks very close on pictures).





rossi594 said:


> I was talking about this part of the adapter which has the smallest cross-sectional area and still does have to conduct some / half of the heat of the chips (if dual sided or not) that area is >120mm long and ~1mm thick (I did not measure mine but the pcb is >1mm and it looks very close on pictures).



Ahhh now I get it.
Yes that's indeed another bottleneck...



rossi594 said:


> BTW I use thermal pads on the pcb in between the memory modules as well, I would strongly recommend that.


I didn't have any at the time when I mounted the EK blocks but I will use thermal putty with the Copper HS.
Another thingy that I forgot about the Copper HS is that it doesn't use thermal pads.
It's made to use thermal paste for DDR4 DR. Sweet!



rossi594 said:


> The surface area on top of the ram modules is ~half as big as the chip area on a dual sided dimm, so you would not benefit from better pads on the memory if you don't have ~double the thermal conductivity on the pad / paste on top of the adapter. (Luckily most thermal pastes are ~70 W/mk while the best pads are 24/7 W/mk).


The surface are on top is 800 x 40 mm more or less on the Alphacool, 3200 mm2
It's exceeding the die area of the memory ICs, they are 10 x 15 mm x 8 x 2 sides = 2400 mm2
Am I missing something?

Most thermal pastes are in the range of 7 to 15 W/mK.
The very expensive Kryonaut Extreme:

*14,2 W/m*K Wärmeleitfähigkeit*
Between 50 and 90 W/mK is the range for liquid metal.
Conductnaut LM is 73 W/mK.

What really matters is the thickness.
The goal of a layer of thermal paste is to replace the air in the gap between the surfaces.

It's not that using a layer of Kryonaut between two Copper surfaces you reduce the thermal transfer from 389 to 14.2 W/mK.
The paste will be a bottleneck but the heat transfer it's still very close to direct contact.

Otherwise it wouldn't matter using Aluminium or Copper, you could use Steel or Iron and would be the same.
That's why, despite the massive higher thermal conductivity, LM against a high-end thermal paste gives you a 2 to 5c advantage.

With thermal pads the thickness really matters because the bottleneck is much more important.
I don't remember how to calculate the loss; but going from a 0.5 mm vs 1.0 mm pad is a huge loss, not 1:1.



rossi594 said:


> Maybe this is why @Veii noticed a difference between copper and aluminiums specific heat capacity. (btw. depending on the temperature copper can have a slightly higher heat capacity per volume because it is soo much heavier than aluminum).





rossi594 said:


> Aluminums thermal properties depend a lot on the temperature


Copper heat capacity is much higher than Aluminum, over 40%!
And it almost doesn't change with temperature, Aluminum does.
But in "our" temperature range these changes are almost negligible.









How does heat capacity of copper (or aluminum) change with temperature, when the temperature is in the region of 0°C to 80°C and why?


Answer: The heat capacity of metals varies with temperature according to the Debye theory. Although this graph is universal for all metals, it has normalized parameters on the x and y axes. The graph is a little hard to interpret without knowing details about the metal in question. You need to k...




www.quora.com


----------



## ManniX-ITA

Audioboxer said:


> who knows what 1.2.0.6 will bring. Fixes? More like, more bugs.


Same as 1.2.0.6, EDC over 140A will cause Core VID lock.
I think I'll wait for 1.2.0.7 or later.. but since we are already in February I'm starting to think that before I see a better AGESA there'll be already on sale the Zen4...



Audioboxer said:


> Speaking of that, my y-cruncher results on AGESA 1.2.0.3c were better. 1.2.0.5 has really buggered up CPU overclocking for me. My curve has been tested for stability, but between the voltage cap issues with EDC and all the boosting changes, I think I need to rework the whole thing.


Yes I can confirm you need to redo the whole thing.
At le least for me most CO offsets were between 5-10 lower.



PJVol said:


> I certainly am not among the top world chemists, but it was my first hobby (hence the PJ - initials of famous danish chemist ).
> AFAIR, the term "metallic" here is not correct, actually fluid has to have any electrolytic substance dissolved to be conductive, for example it may be an acid, or a ammonia water, etc.


Ah for me it was not even an hobby 
Can they transfer electrons?
That was the whole point.
I don't remember clearly the discussion so maybe it was metallic and something else... not sure.


----------



## ManniX-ITA

@domdtxdissar 

In case you decide to experiment with the modded bios...
maybe you know already, it was released the 25th of Jan:






MSI X570S UNIFY-X MAX - Google Drive







drive.google.com


----------



## PJVol

ManniX-ITA said:


> Can they transfer electrons?


Ah, nvm  (aqueous solutions - yes)
I tried 2.5b y-cruncher test, and so far nothing can help it run faster @2000 fclk/pbo. The best result was ~ 135s, while @ 1900 - 118s.
Linpack ~ the same.


----------



## Worldwin

Recently went from 1.2.0.3c to 1.2.0.5 and my ram settings are no longer stable. What a **** show.


----------



## rossi594

ManniX-ITA said:


> The surface are on top is 800 x 40 mm more or less on the Alphacool, 3200 mm2
> It's exceeding the die area of the memory ICs, they are 10 x 15 mm x 8 x 2 sides = 2400 mm2
> Am I missing something?


I was talking about the tops of the adapters. 800mm are 80cm ... don't know if we are talking about the same thing.
80mm seems short to me. I assume the top surface is ~120x5mm = 600mm² but it might as well be 8mm width (I think it's definitly not more than that). But it would still be smaller than the contact patch on the ICs. So it should be the bottleneck when you are using thermal paste / putty.

The surface area of the ICs (not accounting for the PCB in between). Is 7.5mm x 11mm = 82.5mm² for one IC / 660mm² for one side / 1320mm² for a dual sided DIMM.



ManniX-ITA said:


> Most thermal pastes are in the range of 7 to 15 W/mK.
> The very expensive Kryonaut Extreme:
> 
> *14,2 W/m*K Wärmeleitfähigkeit*
> Between 50 and 90 W/mK is the range for liquid metal.
> Conductnaut LM is 73 W/mK.


You are right, I should have double checked. Google spit out that number (don't trust Google). I tryed to find the spec on MX-4. Even less reason to spent more on pads, when the termal paste on top can't deal with it =D



ManniX-ITA said:


> Copper heat capacity is much higher than Aluminum, over 40%!
> And it almost doesn't change with temperature, Aluminum does.
> But in "our" temperature range these changes are almost negligible.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> How does heat capacity of copper (or aluminum) change with temperature, when the temperature is in the region of 0°C to 80°C and why?
> 
> 
> Answer: The heat capacity of metals varies with temperature according to the Debye theory. Although this graph is universal for all metals, it has normalized parameters on the x and y axes. The graph is a little hard to interpret without knowing details about the metal in question. You need to k...
> 
> 
> 
> 
> www.quora.com


I think you are talking about the molar heat capacity. If you look at Cp,s copper should be ~1/3 of aluminum but it's also ~3x as dense. So it is roughly equal.


----------



## Audioboxer

domdtxdissar said:


> I need 1.6 vdimm to run the same tWTRS 2 on my sticks, but i'm also running alittle tighter tRAS+tRC and tRDWR timings.
> View attachment 2547100
> 
> 
> 
> Seems to be worse then 2000 for me
> 
> View attachment 2547128
> 
> 
> Here are a miner run at tight 1900:3800 profile from above, still running cpu at static 4200mhz so its a valid comparison to your testing
> View attachment 2547120
> 
> 
> *19314 H/s* after 15min seems to indicate this "benchmark" also scales pretty good with low timings
> View attachment 2547098
> 
> Soc power draw is 20w under load at these settings. What is your soc powerdraw at your 2000:4000 profile while running the miner ?
> (under karhu ramtest soc power draw is ~21w @ PBO CO 4.8ghz as screenshot above show)
> 
> The good thing is that i know my 1900:3800 always will scale and never throttle when i push high cpu clockspeed, which give me alittle peace of mind since it one less thing to worry about when trying to get rankings on hwbot
> 
> Just let me know if you want to see higher cpu clocks in anything
> _edit_
> Async 1900:4466 run
> *18940 H/s* after 15min
> Alittle surprised this wasn't faster, but just goes to show that the miner aint all bandwidth hungry
> View attachment 2547122


I can't boot tRDWR 8 so you win some you lose some


----------



## ManniX-ITA

@domdtxdissar 

SOC Power in idle is 24.5W, miner 30.6W and Kahru 32.2W



PJVol said:


> I tried 2.5b y-cruncher test, and so far nothing can help it run faster @2000 fclk/pbo. The best result was ~ 135s, while @ 1900 - 118s.
> Linpack ~ the same.


Unfortunately I've already said everything I think could be helpful...
Some CPUs they just can't do it.



rossi594 said:


> I was talking about the tops of the adapters. 800mm are 80cm ... don't know if we are talking about the same thing.


Yeah, I don't know how I didn't realize the *10 and why I thought about 8cm 
The top of the adapter is about 12,5 cm but there are the holes for the screws and the width is 4mm.
Doing the right math, we could say 120 mm by 4 mm so it's 480 mm2.

It's definitely the bottleneck and a very performant thermal paste may be very important...



rossi594 said:


> I think you are talking about the molar heat capacity. If you look at Cp,s copper should be ~1/3 of aluminum but it's also ~3x as dense. So it is roughly equal.


I was talking about the volumetric heat capacity, it takes in consideration the volume of the material (per cubic meter):






Table of specific heat capacities - Wikipedia







en.wikipedia.org





Aluminum is 2.422 and Copper 3.47.
I'm not a super expert but I think this is the right one to look 
Made the ratio between these two.

I've read a lot of material on this stuff and the massive heat storage capacity of Copper it's like a mantra...
Plus I've tested by myself first hand, there's really a huge difference.


----------



## MrHoof

ManniX-ITA said:


> @domdtxdissar
> SOC Power in idle is 24.5W, miner 30.6W and Kahru 32.2W


oof thats alot what the hell. 13.7w on a 1 CCD at 1900 tho.


----------



## ArkSez

PJVol said:


> They should work effortlessly with literally these settings:
> Try to boot PC without RAM first (to reset possibly stuck settings), then insert modules in A2 / B2 and try again. You can also test modules one by one, to make sure they are fully functional and of the same bin.


Another Update. I did one final change before I called it quits which was to change Cmd2T to Auto (let the motherboard decide). So the motherboard defaulted to 1T as before, and the only thing it changed as well was it enabled Gear Down Mode. By selecting 1T earlier manually it disabled GDM (how does disabling that cause these errors?). I have no idea why that would make any difference to stability, but I just completed two complete 3-cycle tests in TestMem5 for the last 2 hours and I had zero errors. I am elated! Thank you so much for your timings and voltage and RTT settings, they've worked!

Now I wonder if I can try 3800 MHz/1900 IF with these settings by just upping the DIMM voltage a little bit? (I'll try it next weekend and enjoy my week actually being able to use my PC)


----------



## MrHoof

@ArkSez 1T is not guaranteed for anyone without fine tuning RTT/DrvStr to the best possible values and even then alot people have to add Setup timings to make it work.
This is more related to the Motherboard and maybe even CPU than the RAM.

edit: Geardown mode is not real 1T look it up if you want to know more about it.


----------



## ArkSez

That makes sense. I had a 3900x before and did not come across this issue at this speed and didn't even really tinker much then. I am tempted to buy another motherboard with an x570 to see if that unlocks the 1900IF better (I can boot up to 2000IF on this CPU, but anything over 1600 I get signs of instability) but given we're less than a year before the next batch of new CPUs and Motherboards, I think I'll just have to settle with this mediocre setting.


----------



## MrHoof

You can still figure out how good your memory is by running 2T. The same timings will works if the rest allows it.


----------



## PJVol

ArkSez said:


> I am tempted to buy another motherboard


I wouldn't be so quick until you can exclude the bios/win11 factor. Since the release of this service pack #11, many mb vendors turned bios update in a hell of a mess (luckily, asrock was slow enough not to mess up, as expected, lol)

You can see people complain about it everywhere, even on this page, so at least rolling back to the 1.2.0.3C version is worth trying.


----------



## Imprezzion

Well, it crapped out at 3866/1933 lol. Was tested stable for over 20 hours of several tests including 8 hours of TM5. Then I got weird crashes in Dying Light 2 with ray tracing on max which according to the event viewer were memory related. And lo and behold, the unchanged stable profile now errors within the first 10 minutes of TM5. So, I went exploring. Remembered I tested in a cold room, heater off (ambients are like 4c here with the room being maybe at 12c), side panel open and was now gaming with the side panel closed and the heat at 19c. In the long TM5 test DIMM's maxed out at 40.8c. However I now find them running at 49.xc in game. Opened the side panel and allowed the room to cool to 14c, tested TM5 again, it's fine. So yeah, I can't handle the temps at 3866 with the voltage I have to run (1.59v).

I loaded my 3733C15 1T @1.55v setup and tested again with the heat on and the side panel closed. No errors at 46.xc and with this being under 1900 FCLK I can run way way way lower vSOC and VDDP and such which allows the CPU to pick up 25-50Mhz extra boost clocks and overall performance in games is actually better at 3733C15 1T compared to 3866C15 2T with the higher boost it can run.

So yeah, 3733 1T it is and still on 1.2.0.3c. Not moving from it either as I run 170 EDC.


----------



## ArkSez

MrHoof said:


> You can still figure out how good your memory is by running 2T. The same timings will works if the rest allows it.


Thanks both, I will do further testing and gaming this week first with the working 3600 settings and if it's all stable I will play around with a higher IF next weekend for more fun!

And yes, I recently updated to the latest BIOS and Win 11 coinciding with me getting my 5900x back. At least I've got a stable setting I can default to now and if all else fails wait for the next set of updates.


----------



## Luggage

ManniX-ITA said:


> @domdtxdissar
> 
> SOC Power in idle is 24.5W, miner 30.6W and Kahru 32.2W
> 
> 
> 
> Unfortunately I've already said everything I think could be helpful...
> Some CPUs they just can't do it.
> 
> 
> 
> Yeah, I don't know how I didn't realize the *10 and why I thought about 8cm
> The top of the adapter is about 12,5 cm but there are the holes for the screws and the width is 4mm.
> Doing the right math, we could say 120 mm by 4 mm so it's 480 mm2.
> 
> It's definitely the bottleneck and a very performant thermal paste may be very important...
> 
> 
> 
> I was talking about the volumetric heat capacity, it takes in consideration the volume of the material (per cubic meter):
> 
> 
> 
> 
> 
> 
> Table of specific heat capacities - Wikipedia
> 
> 
> 
> 
> 
> 
> 
> en.wikipedia.org
> 
> 
> 
> 
> 
> Aluminum is 2.422 and Copper 3.47.
> I'm not a super expert but I think this is the right one to look
> Made the ratio between these two.
> 
> I've read a lot of material on this stuff and the massive heat storage capacity of Copper it's like a mantra...
> Plus I've tested by myself first hand, there's really a huge difference.


Dammit - all this talk made me realise I forgot to put paste on the clamp mating surface.



http://imgur.com/a/afYUlaF


----------



## domdtxdissar

ManniX-ITA said:


> @domdtxdissar
> I've ran a very long and funny benchmarking session today
> Prolific, interesting and also surprising!
> 
> My goal was to discover why I was missing 4 GFlops in Linpack at FCLK 1900 and reproduce the scenario where Linpack was running at 629 GFlops but pi25b was throttling at FCLK 2000
> 
> TL;DR
> 
> *You didn't use exactly my settings; there's a chance this is why pi25b was throttling*
> The different settings are; PrcODT, RTT, Setup, VDDP, CPU vCore, VSOC, VDDG CCD & IOD
> *The loss at FCLK 1900 was due to ProcODT at 28 Ohm; mine was set conservative at 36.9*
> I could use your memory setup including VDDP and get 623-624 GFlops as well at FCLK 1900 but they are unstable for me (TM5 fails at 6th cycle)
> It's quite nice to discover Linpack can be used at FCLK 1900 4.2 Static to test the impact of ProcODT!
> Guess FCLK 2000 needs more frequency to show a difference since pumps same 629 GFlops with both PrcODT
> 
> 
> *You used CPU vCore voltage at 1.1V instead of 1.2V*
> I did select a generous vCore specifically to avoid it could become a problem, even if it was topping 91c
> Your 5950X is a monster obviously but running at FCLK2000 is not the same, it's more demanding
> All the benchmarks at FCLK 1900 with vCore 1.1v are running perfectly fine for me as well; *except y-cruncher pi25b*
> I have validated that on my poor 5950X works fine at FCLK 2000 down to 1.15V
> *Please test again with vCore 1.15V and 1.20V*
> 
> *In your FCLK 2000 screenshot CCD, IOD and VSOC are extremely low*
> Maybe you made more tests and also tried the values in my runs but would be better if you try again with the higher vCore
> I've tried your settings and I couldn't even run a few seconds Linpack or y-cruncher without getting a BSOD
> Couldn't replicate your scenario with Linpack working fine and pi25b throttling
> *I could replicate pi25b throttling (72s) due to low voltages; VSOC 1.2V CCD 1000 IOD 1080*
> VDD18 helps with performances (2-3 GFlops in Linpack and 1 second in pi25b) but it doesn't throttle pi25b or cause crashes in Auto
> Give a try with the settings in my first run VSOC 1.2375V CCD 1080 IOD 1140
> Also test with the lowest voltages I've found working for mine; VSOC 1.2125V CCD 1080 IOD 1100
> If they work, scale down until you drop performances or pi25b/Linpack scores are going down
> 
> *While trying to replicate your scenario I've discovered that very surprisingly my CLKREQ# behavior changed!*
> This is another change in the CPU that came out from running with AGESA 1.2.0.5
> Both at Static 4.2 GHz and with PBO now I don't get the same massive performance hit in Linpack and the monero miner
> Actually now with Linpack I get better GFlops without CLKREQ#... about 5 GFlops more
> Seems to be related to the thermal throttling at 90c; without CLKREQ# it reacts better, the opposite of before
> 
> I could run all the benchmarks of the run at the same speed with and without CLKREQ#
> *Unfortunately when I've tested it with PBO after a while I've found a benchmark that showed that I still need it*
> At the end of the usual round I've tested OCCT CPU and my scores were all below average 5950X
> Enabled again CLKREQ# and all the scores with OCCT CPU
> *OCCT CPU benchmark can show if there's an issue with FCLK, even better than the monero miner in this case*
> 
> 
> 
> Yes scales really well with both latency and bandwidth; that's why I decided to first find a working tCL 14 profile for both FCLK.
> I've tried with tCL16 and the hashrate is higher than FCLK 1900 at tCL14 but only by a small margin.
> 
> Could you please monitor the HWInfo RAM bandwidth running the miner in de-sync?
> I'm not sure it's not BW hungry, I suspect more that the bottle neck could be the latency or the Cores taxing the Infinity Fabric to access the RAM.
> 
> I'd like to see 4500/4400 Static with the monero miner and Linpack/pi25b.
> That's for sure a target I want to test when I switch to water.


Bah had to cut shot my stability testing again.. Guess this just have to do for now:










ManniX-ITA said:


> The different settings are; PrcODT, RTT, Setup, VDDP, CPU vCore, VSOC, VDDG CCD & IOD





ManniX-ITA said:


> Give a try with the settings in my first run VSOC 1.2375V CCD 1080 IOD 1140
> Also test with the lowest voltages I've found working for mine; VSOC 1.2125V CCD 1080 IOD 1100


Higher voltages are not the solution for this sample.. Elevated values actually makes it worse:
Soc 1.15, VDDP 0.95, CCD 1 and IOD 1.08
Linpack = ~536 gflops
Y-cruncher = 160sec








Soc 1.20 VDDP 1, CCD 1.08 and IOD 1.10
Linpack = ~585 gflops
Y-cruncher = 116sec








Soc 1.20 VDDP 1, CCD 1.08 and IOD 1.10
Linpack = ~569 gflops
Y-cruncher = 125sec








I have already spent many weeks trying to finetune voltages, the following works best for my sample when trying to run 2000:4000
Vcore dont matter as long as it runs
Soc = dont really matter as long as set above 1120mv
VDDP = ~925mv
CCD = ~985mv
IOD = ~1085mv

Linpack = ~629 gflops
Y-cruncher = 86sec









ManniX-ITA said:


> I'd like to see 4500/4400 Static with the monero miner and Linpack/pi25b.
> That's for sure a target I want to test when I switch to water.


Sure 
Linpack = ~663 gflops
Y-cruncher = 63.222sec
XMR-STAK = 19804 H/s








DRAM read bandwidth while running miner is ~44Gbps @ ~20w vsoc


----------



## domdtxdissar

Luggage said:


> Dammit - all this talk made me realise I forgot to put paste on the clamp mating surface.
> 
> 
> 
> http://imgur.com/a/afYUlaF


My lol solution for air cooled monarch:


----------



## ccxmonster

after some more research i've decided to run this setup:









lastly i want to push it to 4133MHz but i got a question related to tRC and tRFC. since tRC and tRFC are linked if i raise my memory speed 4133MHz i have to raise tRFC to minimum 290ns equivalent of timing value which is 599.(because 290ns is maximum low ns i can reach//below it system doesnt boot) but since those two are linked i think i also need to increase tRC to 60.

am i wrong with the tRC increasement idea ? can it stay at 58 when i use 4133MHz speed with 599 tRFC ??

why am i asking this question is if i raise tRC to 60, latency is also increasing in aida64 test.


----------



## ManniX-ITA

domdtxdissar said:


> Higher voltages are not the solution for this sample.. Elevated values actually makes it worse:


I see, these voltages are insanely low.
So far, everyone with a dual CCD running well at low voltages has the worst performances at FCLK 2000.
There's still the option of CLKREQ but with these results it's probably not going to help.
Worse I could throttle pi25b was 80s something.



domdtxdissar said:


> I have already spent many weeks trying to finetune voltages, the following works best for my sample when trying to run 2000:4000
> Vcore dont matter as long as it runs
> Soc = dont really matter as long as set above 1120mv
> VDDP = ~925mv
> CCD = ~985mv
> IOD = ~1085mv


Did you try this with a 1.15V vCore?



domdtxdissar said:


> DRAM read bandwidth while running miner is ~44Gbps @ ~20w vsoc


Thanks a lot.
Getting back this 10-12 W delta vs FCLK1900 it's going to be a challenge.

Especially since my "new old" 5950X updated by AGESA 1.2.0.5 now doesn't like telemetry.
The moment I switch to Custom, even leaving all options to Auto, will bring down the performances.
Couldn't find any single or combination value to regain the loss.
It's like now it's sensing that is enabled and throttles down.
The miner from 19100 something goes down to 18800.


----------



## Baio73

Hi there,
This is the values I've managed to set with the RAM in sign using GITHub guide (100& stable under Karhu RAM Test):









Only VDIMM set to 1.49v, no other value touched in BIOS.

My goal is to set 3800 CAS 14 GDM OFF 1T, someone has some advice for me?
I tried to load BIOS defaults and set GDM OFF, 1T and VDIMM 1.50v but failed Windows boot.
Is there any quick way to see if my RAM can run 1T GDM OFF?
Thanks!

Baio


----------



## Audioboxer

domdtxdissar said:


> Bah had to cut shot my stability testing again.. Guess this just have to do for now:
> View attachment 2547196
> 
> 
> 
> 
> Higher voltages are not the solution for this sample.. Elevated values actually makes it worse:
> Soc 1.15, VDDP 0.95, CCD 1 and IOD 1.08
> Linpack = ~536 gflops
> Y-cruncher = 160sec
> View attachment 2547197
> 
> 
> Soc 1.20 VDDP 1, CCD 1.08 and IOD 1.10
> Linpack = ~585 gflops
> Y-cruncher = 116sec
> View attachment 2547198
> 
> 
> Soc 1.20 VDDP 1, CCD 1.08 and IOD 1.10
> Linpack = ~569 gflops
> Y-cruncher = 125sec
> View attachment 2547199
> 
> 
> I have already spent many weeks trying to finetune voltages, the following works best for my sample when trying to run 2000:4000
> Vcore dont matter as long as it runs
> Soc = dont really matter as long as set above 1120mv
> VDDP = ~925mv
> CCD = ~985mv
> IOD = ~1085mv
> 
> Linpack = ~629 gflops
> Y-cruncher = 86sec
> View attachment 2547204
> 
> 
> Sure
> Linpack = ~663 gflops
> Y-cruncher = 63.222sec
> XMR-STAK = 19804 H/s
> View attachment 2547200
> 
> DRAM read bandwidth while running miner is ~44Gbps @ ~20w vsoc


Yikes, that's some low VSOC, on AUTO?

Do you think lower ProcODT is helping lower it?

Some more testing for me I guess! I haven't really shifted VSOC from 1.15v after it was set there months ago.










Promising so far on AUTO, but VSOC errors can pop up quite late.










Did a loop clean yesterday and changed my bottom to intake, what a difference with temps. I followed advice on Reddit when initially doing this build for side and back intake, bottom and top exhaust, that proved to be stupid.

Side/bottom intake and top/back exhaust is the way! All are rads, back has a wee 120 rad. Side, bottom and top 360.

Bit of cable management to do but this is my current loop! There is an Arctic fan at the back of the case, externally, so the 120 is a push/pull. The side/bottom is push/pull too. Allows the crappy QL120 fans to exist for "RGB makes you go fast" without relying on their terrible air performance. Top is Arctic P12's only due to space.

RAM to CPU and CPU to back radiator were the biggest assholes. GPU to bottom rad surprisingly went on first take. Pure luck mind you. Hard pipe bending is still such a drag, especially when you make a mistake!


----------



## Mach3.2

ccxmonster said:


> yes i have tried 2000/4000 and it passed the test of tm5/Extreme config by anta777
> at that time timings and all other stuff were like this:
> View attachment 2547150
> 
> 
> i remember, after running this test i was reduced tRC to 58 and tRFC to 580 and it was also passed the test without single error.
> sadly my cpu is not a 2-ccd one. so what memory clock should i try maximum ? should i stick to 4000 or is 4133 also doable ?


Are you running AIDA with minimal background processes?

56+ns seem kinda high for single CCD 2000MHz 1:1 sync for Micron ICs. I managed 56.0ns on my dual CCD 5900X with single rank Rev B at 1866MHz IF 1:1 sync.


Spoiler: Screenshot















To answer your question, 1900MHz IF is good enough, 1866MHz if you can't do 1900MHz due to 1900MHz IF hole.



ccxmonster said:


> after some more research i've decided to run this setup:
> View attachment 2547206
> 
> 
> lastly i want to push it to 4133MHz but i got a question related to tRC and tRFC. since tRC and tRFC are linked if i raise my memory speed 4133MHz i have to raise tRFC to minimum 290ns equivalent of timing value which is 599.(because 290ns is maximum low ns i can reach//below it system doesnt boot) but since those two are linked i think i also need to increase tRC to 60.
> 
> am i wrong with the tRC increasement idea ? can it stay at 58 when i use 4133MHz speed with 599 tRFC ??
> 
> why am i asking this question is if i raise tRC to 60, latency is also increasing in aida64 test.


tRC = tRAS+ tRP; try 56.


----------



## Audioboxer

Beginning to look like a decrease in ProcODT may well help a decrease in VSOC. Would this be the case @Veii ?

I'm just running VSOC on AUTO which seems to be 1.1v, then droop to 1.0750v under load.










Going to leave it here for now, will do a 25 cycle TM5 later.


----------



## ccxmonster

Mach3.2 said:


> Are you running AIDA with minimal background processes?
> 
> 56+ns seem kinda high for single CCD 2000MHz 1:1 sync for Micron ICs. I managed 56.0ns on my dual CCD 5900X with single rank Rev B at 1866MHz IF 1:1 sync.
> 
> 
> Spoiler: Screenshot
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> To answer your question, 1900MHz IF is good enough, 1866MHz if you can't do 1900MHz due to 1900MHz IF hole.
> 
> 
> tRC = tRAS+ tRP; try 56.


Thanks for your answer .yep it was only running AIDA64 at that time and im also aware of the high latency issue of my system. I still dont know what causes it.
other than that i think i just cant decrase tRC below 58 by any chance. i've made some research in forum and found this useful post 









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


@Veii Thanks for your tips, but after trying 536 same error 13, also tried to lower vdimm -10 to 1.490v from 1.5, and rtt to 436 and same issue, for error #11 tried trc 45, same issue; I read on the calculator that it can be tras +1, tried it but no luck. Also tried puting on it more vdimm to...




www.overclock.net





so our chips are very similiar and anything under tRC 58 and tRFC 580 was fail for him. thats why i set 58 tRC minimum.
But i still dont know if i have to increase it to 60 or let it stay there if i increase mem clock to 4133.


----------



## Mach3.2

ccxmonster said:


> Thanks for your answer .yep it was only running AIDA64 at that time and im also aware of the high latency issue of my system. I still dont know what causes it.
> other than that i think i just cant decrase tRC below 58 by any chance. i've made some research in forum and found this useful post
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> @Veii Thanks for your tips, but after trying 536 same error 13, also tried to lower vdimm -10 to 1.490v from 1.5, and rtt to 436 and same issue, for error #11 tried trc 45, same issue; I read on the calculator that it can be tras +1, tried it but no luck. Also tried puting on it more vdimm to...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> so our chips are very similiar and anything under tRC 58 and tRFC 580 was fail for him. thats why i set 58 tRC minimum.
> But i still dont know if i have to increase it to 60 or let it stay there if i increase mem clock to 4133.


Different DRAM sticks have DRAM ICs of varying silicon quality, it's more productive to be finding the limits for your own setup than to copy settings from other people.

If you don't try anything tighter than 58 you'll never know if you can tighten it further.


----------



## VPII

Good day, I want to ask some advice regarding secondary timings. I had two sets of 2 x 8GB G-Skill Flare x DDR4 3200 CL14, but I decided to get a set of G-Skill Trident Z Royal Elite DDR4 3600 CL14 as I figured it would run with my current timings for 3800 CL16. AT first I loaded DOCP for the 3600mhz at CL14 14 14 34 but kept my old secondary timings which was as per the attached picture. But this would fail when running Karhu memtest within the first 6 or 7 seconds. I'll even get a Blue Screen when running Aida64 memory test. Please any help would be appreciated. Even T1 command fails


----------



## Taraquin

ccxmonster said:


> Thanks for your answer .yep it was only running AIDA64 at that time and im also aware of the high latency issue of my system. I still dont know what causes it.
> other than that i think i just cant decrase tRC below 58 by any chance. i've made some research in forum and found this useful post
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> @Veii Thanks for your tips, but after trying 536 same error 13, also tried to lower vdimm -10 to 1.490v from 1.5, and rtt to 436 and same issue, for error #11 tried trc 45, same issue; I read on the calculator that it can be tras +1, tried it but no luck. Also tried puting on it more vdimm to...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> so our chips are very similiar and anything under tRC 58 and tRFC 580 was fail for him. thats why i set 58 tRC minimum.
> But i still dont know if i have to increase it to 60 or let it stay there if i increase mem clock to 4133.


Rev E hates rcdrd, rc and rfc, except for that they rock. On my rev E sticks I need 51 for 3500 and 58 for 3800 so unless your bin rocks I bet you need 60-65. CL, RP, RRD/FAW, WR/RTP and WTRS/L can go really low and help some on latency.


----------



## rossi594

Audioboxer said:


> Yikes, that's some low VSOC, on AUTO?
> 
> Do you think lower ProcODT is helping lower it?
> 
> Some more testing for me I guess! I haven't really shifted VSOC from 1.15v after it was set there months ago.
> 
> View attachment 2547231
> 
> 
> Promising so far on AUTO, but VSOC errors can pop up quite late.
> 
> View attachment 2547232
> 
> 
> Did a loop clean yesterday and changed my bottom to intake, what a difference with temps. I followed advice on Reddit when initially doing this build for side and back intake, bottom and top exhaust, that proved to be stupid.
> 
> Side/bottom intake and top/back exhaust is the way! All are rads, back has a wee 120 rad. Side, bottom and top 360.
> 
> Bit of cable management to do but this is my current loop! There is an Arctic fan at the back of the case, externally, so the 120 is a push/pull. The side/bottom is push/pull too. Allows the crappy QL120 fans to exist for "RGB makes you go fast" without relying on their terrible air performance. Top is Arctic P12's only due to space.
> 
> RAM to CPU and CPU to back radiator were the biggest assholes. GPU to bottom rad surprisingly went on first take. Pure luck mind you. Hard pipe bending is still such a drag, especially when you make a mistake!


She's a beauty.

But I'm not suprised that you are flowing less than me. With all of the 90s and bends.

Mine for comparison: It makes a huge difference how you layout your loop.

It looks nicer now - I tightened the straight a bit more and gave the pump flow sensor connection a bit more tube. (I wish I would have gone glass hard tube, this Norprene tubing is impossible to work with).


----------



## Audioboxer

rossi594 said:


> She's a beauty.
> 
> But I'm not suprised that you are flowing less than me. With all of the 90s and bends.
> 
> Mine for comparison: It makes a huge difference how you layout your loop.
> 
> It looks nicer now - I tightened the straight a bit more and gave the pump flow sensor connection a bit more tube. (I wish I would have gone glass hard tube, this Norprene tubing is impossible to work with).
> 
> View attachment 2547251


I've been meaning to get rid of the 90 out the reservoir and from the graphics card, but I'm waiting till I get a 3080 and see what its block is like. Some GPU blocks seem to insist on a back intake with a vertical mount. It would be easier for me if I could get a 3080 FTW3 block that doesn't care. I _think_ the EK block is like that.

Removing the 90 outlet from the GPU will require a 3 bend run  But yeah, the less 90 degree fittings the better. A 90 degree tube bend is better than a fitting. Though obviously a front plate resevoir with straight runs is peak optimal. I quite like having the pump/reservoir combo though!

Yours is looking clean. I'm always impressed when people manage to make softer tubing look clean. Bending hard tube might take most folks hours and end in some painful failures, but you can see how scabby some people's soft tubing looks if they don't take care with it.










Reservoir at that height also allows the back rad to quite easily connect to the inlet.

These pictures remind me I need to give the pipes/reservoir a wipe down, fingerprints everywhere lol. I was tempted to try and "satin" my tubing, but I'd probably make a mess of it 






Only downside to clear water in clear hard tube is depending on light it shows up all fingerprints/small scuffs.


----------



## rossi594

Audioboxer said:


> I've been meaning to get rid of the 90 out the reservoir and from the graphics card, but I'm waiting till I get a 3080 and see what its block is like.
> 
> Removing the 90 outlet from the GPU will require a 3 bend run  But yeah, the less 90 degree fittings the better. A 90 degree tube bend is better than a fitting.
> 
> Yours is looking clean. I'm always impressed when people manage to make softer tubing look clean. Bending hard tube might take most folks hours and end in some painful failures, but you can see how scabby some people's soft tubing looks if they don't take care with it.


Thanks, I planned the loop like 3-4 times before I started building. This tubing is really hard to bend, so it was a necessity to get it just right, otherwise I would have needed tons of 90°s and 45°s I still ended up using a lot of those, but it would not have been possible with less.










This is the cleanest thing I can come up with for you loop. (It would have you switch the 120mm for a X-Flow one or trough it out and maybe you would have to make a passtrough hole in the vertical PCIe bracket).

Last off-topic post I swear.


----------



## Bloax

ArkSez said:


> Another Update. I did one final change before I called it quits which was to change Cmd2T to Auto (let the motherboard decide). So the motherboard defaulted to 1T as before, and the only thing it changed as well was it enabled Gear Down Mode. By selecting 1T earlier manually it disabled GDM (how does disabling that cause these errors?). I have no idea why that would make any difference to stability, but I just completed two complete 3-cycle tests in TestMem5 for the last 2 hours and I had zero errors. I am elated! Thank you so much for your timings and voltage and RTT settings, they've worked!
> 
> Now I wonder if I can try 3800 MHz/1900 IF with these settings by just upping the DIMM voltage a little bit? (I'll try it next weekend and enjoy my week actually being able to use my PC)
> 
> View attachment 2547177


Unfortunately I can't tell you the quirks of those sticks on AM4, but I _can_ tell you that this picture from somebody else ("mongoled") was very close to "the mark" as far as LGA1700 went:









ProcODT and tRTP/tWR demands have been completely identical between the two platforms, and on this board these sticks demanded rather soundly procODT 28.2 with a raised 1.8v voltage. (1.9v)

Even the RTT's displayed in the image (nom /6 (40), wr/3 (80), park/5 (48)) are the same as they are on this LGA1700 board 🤡

The only oddity is that he's running RRDL 8, which may be a symptom of not running procODT 28.2 with the 1.8v line cranked up a little - as otherwise they do RRD 4/4 and WTR 4/10 (familiar huh?) over here too.

Doctor's Prognosis is that 3800 15-15-15-30-45 with tRFC 270-201-124 is going to run _somewhere_ around 1.5v +/- 0.04v (in 0.01v increments) with the same CADBus (40-20-30-30) being adequate for running 2T GDM Off.
No clue about whether it wants rdrd/wrwr SCL 4 or 5, no clue whether 1T even works on those sticks without major ass-pain.
I'd like to have a clue, but my sticks are rather occupied at the moment. :' )


tl;dr

sticks want 28.2 procODT, low procODT values want higher 1.8v
sticks want tWR 14 and RTP 7
sticks want RTT 6/3/5

the system might want CADBus 40-20-30-30 ??

sticks _can_ do RRD 4/4 and WTR 4/10 (@ 4200 mt/s), probably WTR 4/8 at 3800

the rest, is down to your patience and memory cooling-jutsu
gl hf don't die


----------



## Audioboxer

Random TM5 timeouts when testing low VSOC (AUTO). I think I remember having this issue way back. 

Not sure why Karhu doesn't seem to care, but I'm going to guess it's something to do with differences in the way the CPU is used between Karhu and TM5.

I was under the impression a lower VSOC leaves more of a power budget for the CPU but is it more complicated than that? I'm assuming it's my CPU crashing TM5 and not the memory. So raising VSOC can also help the CPU???


----------



## ManniX-ITA

Audioboxer said:


> Random TM5 timeouts when testing low VSOC (AUTO). I think I remember having this issue way back.


VSOC Auto at 1.1V is too close to IOD; keep it at least with a gap of 60mV (under load, check with HWInfo how low it gets).
I had random errors as well below that threshold.
Low VSOC yes leave a bit more power budget but if you need it to go faster then at lower voltage you don't need more power budget...


----------



## Audioboxer

ManniX-ITA said:


> VSOC Auto at 1.1V is too close to IOD; keep it at least with a gap of 60mV (under load, check with HWInfo how low it gets).
> I had random errors as well below that threshold.
> Low VSOC yes leave a bit more power budget but if you need it to go faster then at lower voltage you don't need more power budget...


Spot on, drop the IOD and we're all good


----------



## Audioboxer

Audioboxer said:


> Spot on, drop the IOD and we're all good
> 
> View attachment 2547494












All good, has me wondering though if I should try my CCD a bit lower, like 0.95v...


----------



## Taraquin

Mannix-ITA: I checked scaling using different ProcODT, VDD18 etc and now get same perf in linpack vs regression of 1-2% before  All timings, soc, etc kept equal, but using VDD18 of 1.88V and 34 ProcODT on 4000cl16 1t:

3800cl16:









4000cl16:









Zentimings:









VDD18 and ProcODT did the trick. Tried higher SOC\IOD but did not help.


----------



## Audioboxer

If I'm going to test low voltages for VDDG, what is best to look for? Issues in y-cruncher? I think I remember Veii saying CCD can perform quite well at lower voltages if it's stable, but IOD likes to be a bit higher?


----------



## Subut

Hey hey! I'd like to ask if there are any tricks to stabilizing higher FCLK? I managed to boot into windows with up to 2067 FCLK with horrible stability. On FCLK 2000 the best I got to was 50 minutes in TM5 without whea errors. I've played around with Vsoc~1.15V, Vddp~0.89V, Vddg's~0.94/1.08V and ProcODT 34.4-60 to get as far as 50 minutes. Should I give up already or is there anything else worth trying.


----------



## Taraquin

Audioboxer said:


> View attachment 2547535
> 
> 
> If I'm going to test low voltages for VDDG, what is best to look for? Issues in y-cruncher? I think I remember Veii saying CCD can perform quite well at lower voltages if it's stable, but IOD likes to be a bit higher?


Aida latency. Example: 4000cl16 1030mv iod fine, 1020mv iod 2ns higher latency, 1010mv 5ns higher latency.


----------



## Audioboxer

Taraquin said:


> Aida latency. Example: 4000cl16 1030mv iod fine, 1020mv iod 2ns higher latency, 1010mv 5ns higher latency.


My latency is the same, even at 0.98v. I think running at FCLK 2000 is probably why your IOD is more sensitive. I'll keep an eye on latency though when stability testing these voltages.


----------



## ManniX-ITA

Audioboxer said:


> My latency is the same, even at 0.98v. I think running at FCLK 2000 is probably why your IOD is more sensitive. I'll keep an eye on latency though when stability testing these voltages.


Geekbench 5 mainly.
You can spot the differences very easily.
AES-XTS for CCD, rest of the tests for IOD.


----------



## domdtxdissar

Reading a other thread i saw something that piqued my interest.. 


storm-chaser said:


> Seems like there are more alternatives for exactly how you want AIDA64 to measure your memory latency. Please right click the latency box and choose "Full Random". I need to see if this method is more viable than the default method, "Page Random", (the same test that was giving us bad results a few months ago.) It was primarily giving us bad results with FSB overclocks on multiple platforms.











What numbers are you guys getting ? I seem to be getting ~7ns higher latency


----------



## MrHoof

@domdtxdissar exactly +6ns for me 57.5.


----------



## storm-chaser

domdtxdissar said:


> Reading a other thread i saw something that piqued my interest..
> 
> View attachment 2547554
> 
> What numbers are you guys getting ? I seem to be getting ~7ns higher latency


Yup that's about what I am seeing as well, between 5-7ns difference. I see a decent explanation as to the increase in total latency @ anandtech (though not completely direct)

Memory Subsystems Compared - Latency - The Samsung Galaxy S10+ Snapdragon & Exynos Review: Almost Perfect, Yet So Flawed (anandtech.com) 










*EDIT 
*It's possible this will be more accurate than the default "page random" method*, I've conducted some preliminary FSB/ref overclocking and the results appear to be stable and consistent. No errant rounds thus far. And that's what was triggering the majority of bad results.


----------



## Audioboxer

Tested 0.9 CCD/0.98 IOD and 0.95 CCD/1.0v IOD, no difference in scores outwith MOE in GB5.

More pressing matter I need to work on though is my curve. Dilemma is do I spend the time to redo the whole thing on AGESA 1.2.0.5 or wait and see what AMD craps out next... Proper curve work can take weeks! 

If AMD weren't lazy morons and actually explained their changelogs we'd know if voltage and boosting changes were on purpose or monkeys in coding creating more bugs.

Might also give Hydra a proper go. Find it a bit complicated to understand. It did give me hugely different curve values than what I use, one core even with a positive curve!


----------



## storm-chaser

Audioboxer said:


> Tested 0.9 CCD/0.98 IOD and 0.95 CCD/1.0v IOD, no difference in scores outwith MOE in GB5.


....think I'm going to need a Navajo code-talker for this one. (intel guy)

😂😂😂


----------



## Audioboxer

storm-chaser said:


> ....think I'm going to need a Navajo code-talker for this one. (intel guy)
> 
> 😂😂😂


MOE = margin of error

GB5 = Geekbench 5

As I was advised above when you lower VDDG voltages it seems to be a good idea to run GB5 runs and check some of the numbers to see if performance is dropping.

The VDDG voltages might be AMD only, they are about the CPU and Infinity Fabric.


----------



## PJVol

storm-chaser said:


> It's possible this will be more accurate than the default "page random" method


Wow, it barely took ten years to add this "usefull" feature...
They'd rather quit ignoring the CPPC core rating in a mem latency test.


----------



## hazium233

To add on to some things about 1205.

I tried bios 1.80 for my MSI B550 Gaming Edge Wifi over the weekend. The most interesting thing was that DRAM voltage was being reported as 0.02V higher than set, which it had never done before. I tried to talk to MSI support, but haven't heard anything back. Actually flashed Eder's version first, then official, but it was the same either way.

I didn't have a great way to explorer whether this was some change to sensors or a real voltage change. Ended up flashing back to an old version. Hopefully that bios didn't do anything permanent to my 5600X.


----------



## MrHoof

I am glad that asus didnt push anything newer then 1203c for my board yet with all those reports, gonna stay here unless I have to upgrade for some reason.


----------



## Imprezzion

MrHoof said:


> I am glad that asus didnt push anything newer then 1203c for my board yet with all those reports, gonna stay here unless I have to upgrade for some reason.


I honestly see no reason to upgrade to anything higher then 1203c even on a B2 5900X. It runs perfectly stable on a very agressive CO negative curve (-25 all cores PPT 300 EDC 170) with a nice 4800+ all-core under load and 5Ghz on all but the 1 worst core under light loads (CPPC and preferred cores disabled), RAM behaves properly at 3733C15 1T GDM Off 1866 IF 1:1, no WHEA's even at very low vSOC and VDDG's, no other issues with onboard devices or whatever either so.. why should I...


----------



## dk10438

hazium233 said:


> To add on to some things about 1205.
> 
> I tried bios 1.80 for my junk MSI B550 Gaming Edge Wifi over the weekend. The most interesting thing was that DRAM voltage was being reported as 0.02V higher than set, which it had never done before. I tried to talk to MSI support, but haven't heard anything back. Actually flashed Eder's version first, then official, but it was the same either way.
> 
> I didn't have a great way to explorer whether this was some change to sensors or a real voltage change. Ended up flashing back to an old version. Hopefully that bios didn't do anything permanent to my 5600X.


FWIW
I have the same issue with the most recent Gigabyte Bios, Dram Voltages 0.02 higher than what was set in BIOS


----------



## Frosted racquet

Is there anything notable between 1203b and patch c? MSI never published a final 1203c for my board and I'm planning on flashing 1203b back from 1205.


----------



## MrHoof

Imprezzion said:


> I honestly see no reason to upgrade to anything higher then 1203c even on a B2 5900X. It runs perfectly stable on a very agressive CO negative curve (-25 all cores PPT 300 EDC 170) with a nice 4800+ all-core under load and 5Ghz on all but the 1 worst core under light loads (CPPC and preferred cores disabled), RAM behaves properly at 3733C15 1T GDM Off 1866 IF 1:1, no WHEA's even at very low vSOC and VDDG's, no other issues with onboard devices or whatever either so.. why should I...


yes and i am not even done testing vddg IOD and SOC but i rather longterm test those for random hickups before moving on.
I am not using auto OC at all i dont like how it pushes up the max vid and it i dont get much benifit from it using a u12a in a nr200.
But i am around 4.65-4.8 all core depending on the ambient temperature in benches.(rather 4.65 on normal ambient)
142/95/140 stock ppt/tdc/edc 5800x.


Spoiler: CO/Zentimings



























'
now 7/2/6 tho but only did 5h so far.


edit: notice how great my board is not even reporting Vdimm under Memory Frequency in bios, Zentimings or HWinfo


----------



## MrHoof

Frosted racquet said:


> Is there anything notable between 1203b and patch c? MSI never published a final 1203c for my board and I'm planning on flashing 1203b back from 1205.


Only Usb fixes if i remember corect, so if you have some might be worth it.
Wait msi never released 1203c?


----------



## ccxmonster

guys is it logical to use lower tRCDWR values like 8,9,10 instead of 16-18 ?
im using a dual rank micron e-die.


----------



## Bix

Another big thumbs down to 1.2.0.5 here. My 5900x now crashes on core 1 with optimised defaults, even after flashing back to 1.2.0.3b (no final patch c for my board either). Decided to RMA rather than make do with a positive offset. I guess whatever the blob 'upgrade' did was enough to push it over the edge into instability at stock, which seems plausible given others here reporting lower negative C/O following the update. 

Obviously hoping for some better silicon this time but still disappointed since my old 5900x seemed to scale _mostly _well at higher FCLK, bar a few scenarios, in spite of not being a great sample. 

Just out of interest, has anyone here got a Zen 3 CPU that clocks well AND scales well beyond 1900 FCLK??


----------



## ManniX-ITA

PJVol said:


> Wow, it barely took ten years to add this "usefull" feature...


It's nothing new, it's there since ages. Maybe 3-4 years?

My take is there's a reason why a pattern is used instead of full random.
You don't usually want to compare something really random, it'll never been an apples to apples comparison.
It's normal to use a pre-defined pseudo-random pattern to improve repeatability.

I guess the normalization as well, that is being affected by Hydra, is there to minimize the architectural differences to have comparable results.

Can't say if it's the best or correct way to do it but I certainly couldn't do better


----------



## MrHoof

ccxmonster said:


> guys is it logical to use lower tRCDWR values like 8,9,10 instead of 16-18 ?
> im using a dual rank micron e-die.


Well benchmarks show improvements for me and others. No expert on micron ram tho dunno how low it can go on those.


----------



## Frosted racquet

MrHoof said:


> Wait msi never released 1203c?


There was a 1203c beta, which turned into 1205 "final"... go figure.


----------



## hazium233

Hmmm. AIDA's L1 and L2 bandwidth isn't right in normal Windows, if I do "Run Cache Tests," single click can sometimes get expected. It shows multiplier as 45.25 as well in the AIDA Window, but it still could boost to 4.65. XMP or 2133 (defaults) the same. But bandwidth values are more or less my expected values with Diagnostic startup.

Maybe I need to kill chipset drivers, or try the older ones? Fun stuff.



Spoiler



Normal Windows










Diagnostic












edit: yeah looks like chipset drivers were too new for this old bios maybe.

I don't know if I will stay on 1202 (modded) or go back to something like 1203b. The modded bios for 1203b is based on beta 1.72 (not sure how different that was from "stable" 1.70).

I am wondering if MSI will ever give any answer about DRAM voltage in 1.80.


----------



## VPII

Okay, I have sold my good old G-Skill Flare X DDR4 3200 CL14 set to get 2 x 16GB G-Skill Trident Z Royal Elite DDR4 3600 CL14. WHen I looked at the timings I figured it would be Samsung B-Die but when opening Thaiphoon under Die Density / Count it states 8Gb / 1die not B-die. But when looking at the B-die finder website I saw the set I have there and obviously Samsung B-die. Any ideas why Thaiphoon not stating it as Samsung B-Die. At present Running Karhu memtest which failed with my secondary timings many times, but now with memory set to 3800 CL16 GDM enabled and 1T command rate it seems to be okay as at present 1350% and still going.


----------



## Baio73

Baio73 said:


> Hi there,
> This is the values I've managed to set with the RAM in sign using GITHub guide (100& stable under Karhu RAM Test):
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Only VDIMM set to 1.49v, no other value touched in BIOS.
> 
> My goal is to set 3800 CAS 14 GDM OFF 1T, someone has some advice for me?
> I tried to load BIOS defaults and set GDM OFF, 1T and VDIMM 1.50v but failed Windows boot.
> Is there any quick way to see if my RAM can run 1T GDM OFF?
> Thanks!
> 
> Baio


No one?

Baio


----------



## TimeDrapery

Spoiler






Baio73 said:


> No one?
> 
> Baio






@Baio73 

Yes, utilize the page selection feature at the top of this page to go back in time about 250 pages and start reading

When you arrive back at this post you'll have answered your own questions as well as so many more that you don't even know you have yet!

Good luck!


----------



## ManniX-ITA

TimeDrapery said:


> Yes, utilize the page selection feature at the top of this page to go back in time about 250 pages and start reading


LoL 
Reading the last 250 pages could cause a neural edema...

@Baio73 
Indeed, go over at the very least the last 100 pages and looks at answers from @Veii.
Plus the long testing sessions from @Audioboxer, @TimeDrapery and others.
No need to read every bit but if you learn which post to pick for reading you'll know much more in a couple of hours.

I'm not really the best to give advice but I'll start from this:










You didn't say the VDIMM. With decently high VDIMM you could get tRCDRD at 14.
Set tRTP half of tWR.
Find what you get for tRDWR/tWRRD with Auto; shouldn't be that high.

Use the tRFC Mini calculator:









tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com





Take a look at the Ryzen Calculator, there are updated TM5 error messages:









Ryzen Google Calculator!


Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c




docs.google.com





You can also take inspiration from the Zen3 Leaderboard:









Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com





Just remember these timings are not always 100% stable


----------



## Imprezzion

Bix said:


> Just out of interest, has anyone here got a Zen 3 CPU that clocks well AND scales well beyond 1900 FCLK??


Unfortunately I don't. My old B1 was great with FCLK at 2000 no WHEA's but the cores were terrible. That chip randomly died and just wouldn't POST from one day to another. RMA chip was this B2 one and that has incredible cores which do very low CO offsets and really high clocks but the FCLK is terrible. 1866 is the most I can pull out of it. It has a hole at 1900 and will not in any way POST 1900. Above is fine like 1933/1966 but it's a WHEA mess and if I brute force it with enough voltage it still gives random WHEA's a few times per day even if stress tests don't show these repeatable and I have had some random crash to desktops and freezes and even page fault BSOD's. So I just run 1866 at low voltages which is at least stable and allows for higher budget for the cores.


----------



## ManniX-ITA

Frosted racquet said:


> Is there anything notable between 1203b and patch c? MSI never published a final 1203c for my board and I'm planning on flashing 1203b back from 1205.


I don't remember but almost sure nothing notable.
I went back to 1.2.0.1 and I don't miss anything.

Really matters more about the quality of the specific release than the AGESA.

Did you try both beta?








[Übersicht] - Ultimative AM4 UEFI/BIOS/AGESA Übersicht


Inhaltsverzeichnis: UEFI Collection | Hersteller Support Links | UEFI Mods | Weiterführende Links Keine weiteren Updates mehr geplant! AM5 UEFI/BIOS/AGESA Übersicht ASRock ASUS Biostar Gigabyte MSI EVGA NZXT B350 B450 B550 X370 X470 X570 B350 B450 B550 X370 X470 X570 B350 B450...




www.hardwareluxx.de







Bix said:


> Just out of interest, has anyone here got a Zen 3 CPU that clocks well AND scales well beyond 1900 FCLK??


I don't know what you mean for clocks well...
This was my 5950X before getting hammered by AGESA 1.2.0.5:










The 2 best cores were going over 5100 MHz and Core 0 at 5040 MHz.
Nothing to complain about.


----------



## ManniX-ITA

domdtxdissar said:


> What numbers are you guys getting ? I seem to be getting ~7ns higher latency


It does change also the Lx cache latencies test:
















Not visible on L1/L2 except the longer testing time.

This is the profile:










Bix said:


> Just out of interest, has anyone here got a Zen 3 CPU that clocks well AND scales well beyond 1900 FCLK??


I have just re-run Boosttester and that's where I stand now after hours of optimizations to recover the losses:















Overall not so bad but would probably have been even better without the AGESA changes.

Linpack runs decently before getting choked by the temperature:









The miner as well runs fine:









At the end in regards to benchmark scores the biggest loss is a few points on CPU-z ST.


----------



## TMavica

Finally figured out why I got timeout in TM5, I need to raise the Vsoc. 1.1.25 still got timeout...However Vsoc 1.15 seem a little bit high? Tried lower IOD to 1.00 and Vsoc 1.125 still got TM5 timeout
PS: Vdimm 1.55


----------



## TMavica

Deleted


----------



## Bix

Imprezzion said:


> Unfortunately I don't. My old B1 was great with FCLK at 2000 no WHEA's but the cores were terrible. That chip randomly died and just wouldn't POST from one day to another. RMA chip was this B2 one and that has incredible cores which do very low CO offsets and really high clocks but the FCLK is terrible. 1866 is the most I can pull out of it. It has a hole at 1900 and will not in any way POST 1900. Above is fine like 1933/1966 but it's a WHEA mess and if I brute force it with enough voltage it still gives random WHEA's a few times per day even if stress tests don't show these repeatable and I have had some random crash to desktops and freezes and even page fault BSOD's. So I just run 1866 at low voltages which is at least stable and allows for higher budget for the cores.


That makes sense, especially if you were getting random crashing. I was suppressing the few WHEAs I had at 2000 using @ManniX-ITA 's tool but only because they didn't seem to be affecting stability (pre 1.2.0.5 at least).



ManniX-ITA said:


> The 2 best cores were going over 5100 MHz and Core 0 at 5040 MHz.
> Nothing to complain about.


No, nothing to complain about there  Is FCLK capability on the CPU side of things solely down to the IMC in that case (assuming the MB is suitable)? Having followed this thread for a while I thought I was beginning to see a pattern whereby chips with lower quality cores had more success at higher FCLK but I'm probably imagining things!


----------



## Veii

Audioboxer said:


> These pictures remind me I need to give the pipes/reservoir a wipe down, fingerprints everywhere lol. I was tempted to try and "satin" my tubing, but I'd probably make a mess of it
> Only downside to clear water in clear hard tube is depending on light it shows up all fingerprints/small scuffs.


I funnily wanted to ask you, if you aren't gonna go with the frosted tubes look 
It surely will fit, because Frosted Tubing "soaks" in and reflects light ~ soo your tubes will mainly appear white ~ with red smooth accents
The video you linked even, is quite good


Subut said:


> On FCLK 2000 the best I got to was 50 minutes in TM5 without whea errors. I've played around with Vsoc~1.15V, Vddp~0.89V, Vddg's~0.94/1.08V and ProcODT 34.4-60 to get as far as 50 minutes. Should I give up already or is there anything else worth trying.


2000 FCLK , will require higher SOC in the range of 1175-1250
And likely higher IOD , in the range of 1050-1125


storm-chaser said:


> Yup that's about what I am seeing as well, between 5-7ns difference. I see a decent explanation as to the increase in total latency @ anandtech (though not completely direct)
> 
> Memory Subsystems Compared - Latency - The Samsung Galaxy S10+ Snapdragon & Exynos Review: Almost Perfect, Yet So Flawed (anandtech.com)
> 
> 
> 
> 
> 
> 
> 
> 
> *EDIT
> *It's possible this will be more accurate than the default "page random" method*, I've conducted some preliminary FSB/ref overclocking and the results appear to be stable and consistent. No errant rounds thus far. And that's what was triggering the majority of bad results.
> 
> 
> PJVol said:
> 
> 
> 
> Wow, it barely took ten years to add this "usefull" feature...
> They'd rather quit ignoring the CPPC core rating in a mem latency test.
Click to expand...










It's alright
I've seen it 2 years ago, but i wouldn't put 100% trust into it
It is more affected by autocorrection and DPM throttle, than the normal method
It messes with L3 cache slightly (some results) & i get a deviation of +/+ 0.3ns, while normal one is +/- 0.1ns
Could be just aggravating the other issues of Win11 ~ but to my eyes, it looks more dynamic by core freq. So is also SiSandra Inter-core.
Yea it's "alright" but hence nobody uses it , and it is more affected by core clock than normal mode ~ unsure what to think about it


ccxmonster said:


> guys is it logical to use lower tRCDWR values like 8,9,10 instead of 16-18 ?
> im using a dual rank micron e-die.


Questionable, and in debate
I can't see it scaling better than what i usually run and it rather loses bandwidth for me
Strongly in debate, but considerable.
Lower timings are not always better, same goes for tRAS & have to likely up it again
Lower timings often are too low and waste tRC & tRFC cycles = limit potential time of memory to function, as it has to stop doing anything, when tRFC is needed and wait it out
Also has to stop doing anything on any read or recharge. Cells have to be recharged fully first, before anything can be done and tRP inserted before any action.
Too low timings can very well be negative ~ but same would go for too low tRC
In research and in debate ~ don't fixate yourself on this 


TMavica said:


> Vsoc 1.15 seem a little bit high?


Range to 1.3v on Vermeer, optimally bellow 1.25v. 1.35v for XOC
Cezanne/Lucienne, up to 1.35 peak 1.4 ~ but 1.45 is already dangerous sub ambient. Personally would never leave the 1.3vSOC mark, same goes for Navi ~ peak 1.35 but it's rather stupid to use it
==================================
Something off-quote, in-topic








Text:








@Audioboxer Yes, correct. ProcODT lower will lower voltage requirements, but very well can destabilize memory (if mainly used for powering) & will change VDDG voltages.
Same goes for VDD18, no memory but will change VDDG & VDDP behavior = memory


----------



## Taraquin

Mannix-ITA: Tested a bit more. At ProcODT 28 and VDD18 1840mv I get identical score/margin of error (265-266Gflops) with 3800cl16 and 4000cl16 in linpack, all voltages/timings kept equal. Y-cruncher also margin of error. 

Geekbench:
3800cl16: 1741 9611
3800cl15: 1744 9616
4000cl16: 1743 9711

So to wrap it up going from 3800cl15 to 4000cl16 and upping VDD18:
Positive scaling:
SOTTR (1-2% higher fps when CPU-bound) 
aida (3-4%)
Dram calc test (2%)
Geekbench multi (1%)

No scaling (same/margin if error below 0.5%):
Y-cruncher
Linpack

Negative scaling:
Cinebench (1-2% multi) if I use 76W pwr limit since cores run a bit slower due to IO-die using more power running 4000.

A friend of mine got negative scaling above 3800 on his 5600X, but he had extreme numbers of WHEA 19s which contributed to this.

My advice: If you see net positive scaling of the things you use and don't need very high SOC/IOD volt raise (since it steals from core budget due to power/temp), run above 3800/1900, but if you have loads of WHEA 19 try supressor and see if it scales then.

Edit: Tested CCD voltage aswell, 840mv is rock solid, tried 920mv and lost 50 points in geekbench, probably due to less pwr to core budget.


----------



## Taraquin

Veii said:


> I funnily wanted to ask you, if you aren't gonna go with the frosted tubes look
> It surely will fit, because Frosted Tubing "soaks" in and reflects light ~ soo your tubes will mainly appear white ~ with red smooth accents
> The video you linked even, is quite good
> 
> 2000 FCLK , will require higher SOC in the range of 1175-1250
> And likely higher IOD , in the range of 1050-1125
> 
> View attachment 2547659
> 
> It's alright
> I've seen it 2 years ago, but i wouldn't put 100% trust into it
> It is more affected by autocorrection and DPM throttle, than the normal method
> It messes with L3 cache slightly (some results) & i get a deviation of +/+ 0.3ns, while normal one is +/- 0.1ns
> Could be just aggravating the other issues of Win11 ~ but to my eyes, it looks more dynamic by core freq. So is also SiSandra Inter-core.
> Yea it's "alright" but hence nobody uses it , and it is more affected by core clock than normal mode ~ unsure what to think about it
> 
> Questionable, and in debate
> I can't see it scaling better than what i usually run and it rather loses bandwidth for me
> Strongly in debate, but considerable.
> Lower timings are not always better, same goes for tRAS & have to likely up it again
> Lower timings often are too low and waste tRC & tRFC cycles = limit potential time of memory to function, as it has to stop doing anything, when tRFC is needed and wait it out
> Also has to stop doing anything on any read or recharge. Cells have to be recharged fully first, before anything can be done and tRP inserted before any action.
> Too low timings can very well be negative ~ but same would go for too low tRC
> In research and in debate ~ don't fixate yourself on this
> 
> Range to 1.3v on Vermeer, optimally bellow 1.25v. 1.35v for XOC
> Cezanne/Lucienne, up to 1.35 peak 1.4 ~ but 1.45 is already dangerous sub ambient. Personally would never leave the 1.3vSOC mark, same goes for Navi ~ peak 1.35 but it's rather stupid to use it
> ==================================
> Something off-quote, in-topic
> View attachment 2547663
> 
> Text:
> View attachment 2547664
> 
> 
> @Audioboxer Yes, correct. ProcODT lower will lower voltage requirements, but very well can destabilize memory (if mainly used for powering) & will change VDDG voltages.
> Same goes for VDD18, no memory but will change VDDG & VDDP behavior = memory


I must disagree a bit Veii, for some you might need 1175/1050+ soc/iod for fclk 2000, but I get no benefit going above 1120/1040. I thought 1110/1030 was the lowest at full speed, but after a lot of testing I seem to get 0.3ns better aida with 1120/1040. I have tried 1130/1050 and 1160/1080, but get no benefit, allcore apps run slower since it steals from core budget.


----------



## Audioboxer

Veii said:


> I funnily wanted to ask you, if you aren't gonna go with the frosted tubes look
> It surely will fit, because Frosted Tubing "soaks" in and reflects light ~ soo your tubes will mainly appear white ~ with red smooth accents
> The video you linked even, is quite good
> 
> 2000 FCLK , will require higher SOC in the range of 1175-1250
> And likely higher IOD , in the range of 1050-1125
> 
> View attachment 2547659
> 
> It's alright
> I've seen it 2 years ago, but i wouldn't put 100% trust into it
> It is more affected by autocorrection and DPM throttle, than the normal method
> It messes with L3 cache slightly (some results) & i get a deviation of +/+ 0.3ns, while normal one is +/- 0.1ns
> Could be just aggravating the other issues of Win11 ~ but to my eyes, it looks more dynamic by core freq. So is also SiSandra Inter-core.
> Yea it's "alright" but hence nobody uses it , and it is more affected by core clock than normal mode ~ unsure what to think about it
> 
> Questionable, and in debate
> I can't see it scaling better than what i usually run and it rather loses bandwidth for me
> Strongly in debate, but considerable.
> Lower timings are not always better, same goes for tRAS & have to likely up it again
> Lower timings often are too low and waste tRC & tRFC cycles = limit potential time of memory to function, as it has to stop doing anything, when tRFC is needed and wait it out
> Also has to stop doing anything on any read or recharge. Cells have to be recharged fully first, before anything can be done and tRP inserted before any action.
> Too low timings can very well be negative ~ but same would go for too low tRC
> In research and in debate ~ don't fixate yourself on this
> 
> Range to 1.3v on Vermeer, optimally bellow 1.25v. 1.35v for XOC
> Cezanne/Lucienne, up to 1.35 peak 1.4 ~ but 1.45 is already dangerous sub ambient. Personally would never leave the 1.3vSOC mark, same goes for Navi ~ peak 1.35 but it's rather stupid to use it
> ==================================
> Something off-quote, in-topic
> View attachment 2547663
> 
> Text:
> View attachment 2547664
> 
> 
> @Audioboxer Yes, correct. ProcODT lower will lower voltage requirements, but very well can destabilize memory (if mainly used for powering) & will change VDDG voltages.
> Same goes for VDD18, no memory but will change VDDG & VDDP behavior = memory


Yeah I'll give frosted a go next time I do a loop drain, hopefully in a month or so if my EVGA step up finally comes in...

Tested it on some scrap tubing with very light sandpaper and it seems to be quite easy to get going, but as the video shows likely just take a bit longer and care to get a "retail finish". It does look nice though!! There's no way I'm buying frosted tubing and redoing all these bends, so it'll be DIY frosted 👀


----------



## ccxmonster

I got another question confusing my mind. would using CR2T command rate let us lower the voltages further ? or not even a little bit ?
im asking because i passed tm5//[email protected] test with this setup:









in bios entered voltage values are:
vSoc 1.1125
VDDP 0.865
VDDG_CCD 0.92
VDDG IOD 1.040
VDIMM 1.47

Actually im not only passed tm5//[email protected] test but also y-cruncher(16,5minute with config from memtest github guide), linkpack inside occt(2019 version,20 minute) and normal occt cpu stress test (extreme,steady,large,avx2 and 20 minute).
All passed without single error.

also im using WHEAService program.. because i always get these WHEA errors(it was CPU Bus/Interconnect error or smth like this) over 3800 FCLK 

EDIT: Found the test SS


----------



## ManniX-ITA

Taraquin said:


> Geekbench:
> 3800cl16: 1741 9611
> 3800cl15: 1744 9616
> 4000cl16: 1743 9711


Nice testing!

If you can get a 4000 CL14 profile working you'll get a substantial boost over CL16.
Bit on ST but more on MT.



Taraquin said:


> Negative scaling:
> Cinebench (1-2% multi) if I use 76W pwr limit since cores run a bit slower due to IO-die using more power running 4000.


Cinebench is very special.
It could be affected by VRM, PWM and LLC settings.



Bix said:


> No, nothing to complain about there  Is FCLK capability on the CPU side of things solely down to the IMC in that case (assuming the MB is suitable)? Having followed this thread for a while I thought I was beginning to see a pattern whereby chips with lower quality cores had more success at higher FCLK but I'm probably imagining things!


The pattern I see, which is once again confirmed by @domdtxdissar testing with his platinum 5950X, is not solely down to the IMC.
In general high quality samples runs better at low voltages.
And this is generally bad for high FCLK.
Much less of a problem with a single CCD but seems crucial for dual CCD.
Higher the best voltages for SOC & VDDG and better are the chances high FCLK works better.


----------



## Taraquin

ManniX-ITA said:


> Nice testing!
> 
> If you can get a 4000 CL14 profile working you'll get a substantial boost over CL16.
> Bit on ST but more on MT.
> 
> 
> 
> Cinebench is very special.
> It could be affected by VRM, PWM and LLC settings.
> 
> 
> 
> The pattern I see, which is once again confirmed by @domdtxdissar testing with his platinum 5950X, is not solely down to the IMC.
> In general high quality samples runs better at low voltages.
> And this is generally bad for high FCLK.
> Much less of a problem with a single CCD but seems crucial for dual CCD.
> Higher the best voltages for SOC & VDDG and better are the chances high FCLK works better.


My ram bin is average, I need 1.46V for flat 16 on 4000 1t. I tried cl15, but I get errors even at 1.57v :/ Ram is currently stuck between cooler block and front fan of D15-cooler so there is no way to improve airflow :/


----------



## Baio73

TimeDrapery said:


> @Baio73
> 
> Yes, utilize the page selection feature at the top of this page to go back in time about 250 pages and start reading
> 
> When you arrive back at this post you'll have answered your own questions as well as so many more that you don't even know you have yet!
> 
> Good luck!


Maybe sometimes it's better reading what other users write, instead of trying (and not being successfull) to be humorous.
I'm not overclocking my RAM from zero, I've already followed GitHub guide and reached a good result.
I was just asking if there is something different to do to disable GDM and keep 1T on, as the guide does not say anything specific about it.
Thanks anyway for your kindness and for the time you wasted to reply to my post.

Baio


----------



## Baio73

ManniX-ITA said:


> LoL
> Reading the last 250 pages could cause a neural edema...
> 
> @Baio73
> Indeed, go over at the very least the last 100 pages and looks at answers from @Veii.
> Plus the long testing sessions from @Audioboxer, @TimeDrapery and others.
> No need to read every bit but if you learn which post to pick for reading you'll know much more in a couple of hours.
> 
> I'm not really the best to give advice but I'll start from this:
> 
> View attachment 2547639
> 
> 
> You didn't say the VDIMM. With decently high VDIMM you could get tRCDRD at 14.
> Set tRTP half of tWR.
> Find what you get for tRDWR/tWRRD with Auto; shouldn't be that high.
> 
> Use the tRFC Mini calculator:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> Take a look at the Ryzen Calculator, there are updated TM5 error messages:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> You can also take inspiration from the Zen3 Leaderboard:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> Just remember these timings are not always 100% stable


Thanks for your reply, I'll try to use the links you posted.
So are you saying I should try to raise the values you marked in red and THEN lower to 1T?
As I said, VDIMM I tried was up to 1.50v, the Zen settings I posted are 100% stable with 1.49v.

Baio


----------



## ManniX-ITA

Taraquin said:


> My ram bin is average, I need 1.46V for flat 16 on 4000 1t. I tried cl15, but I get errors even at 1.57v :/ Ram is currently stuck between cooler block and front fan of D15-cooler so there is no way to improve airflow :/


CL15 at 4000 it's a mess also for my good bin.
And I have a Dark Rock Pro 4 right now, same situation 

Did you try something like this?










If you find the right termination settings can be doable also for your kit.
Start with very high tRFC and tRCDRD at 17.
Scale down tRFC once you are sure it works and go back to tRCDRD at 16.
You may even be able to run tRCDRD at 15 but it's unlikely.
This is going to be anyway faster than CL16.

Not sure what max temp your DIMM can support but this config runs error free 2 hours TM5 at 59-61c


----------



## ManniX-ITA

Baio73 said:


> So are you saying I should try to raise the values you marked in red and THEN lower to 1T?


No, first make it work at 2T and maybe one day try 1T.
2T is going to be faster than 1T GDM.
If you want to attempt something later either be 1T GDM Off or same with Setup times.

I didn't read about the 1.5V DIMM.
Depends on the DIMM but you'll probably need more for tRCDRD 14.

What you can run and at what voltage really depends on your setup and the termination settings.
You have to do a lot of tests and run TM5 for very long hours...


----------



## Taraquin

ManniX-ITA said:


> CL15 at 4000 it's a mess also for my good bin.
> And I have a Dark Rock Pro 4 right now, same situation
> 
> Did you try something like this?
> 
> View attachment 2547700
> 
> 
> If you find the right termination settings can be doable also for your kit.
> Start with very high tRFC and tRCDRD at 17.
> Scale down tRFC once you are sure it works and go back to tRCDRD at 16.
> You may even be able to run tRCDRD at 15 but it's unlikely.
> This is going to be anyway faster than CL16.
> 
> Not sure what max temp your DIMM can support but this config runs error free 2 hours TM5 at 59-61c


I have SR so need different Rtts than you, in 1t I must have 40 20 30 24 or I get errors or no boot. I haven't tested more on ProcODT, but even at 1.55v I got some errors in TM5 with rcdrd 17 and 280 rfc, probably related to heat, but I don't gave tempsensor. My kit don't seem to budge.


----------



## Bix

ManniX-ITA said:


> The pattern I see, which is once again confirmed by @domdtxdissar testing with his platinum 5950X, is not solely down to the IMC.
> In general high quality samples runs better at low voltages.
> And this is generally bad for high FCLK.
> Much less of a problem with a single CCD but seems crucial for dual CCD.
> Higher the best voltages for SOC & VDDG and better are the chances high FCLK works better.


That makes a lot of sense, thanks. It's a nice bonus for those that don't win the silicon lottery that at least some of that performance loss can potentially be regained by pushing FCLK, even if it does take a lot of extra work!


----------



## ManniX-ITA

Taraquin said:


> I have SR so need different Rtts than you, in 1t I must have 40 20 30 24 or I get errors or no boot. I haven't tested more on ProcODT, but even at 1.55v I got some errors in TM5 with rcdrd 17 and 280 rfc, probably related to heat, but I don't gave tempsensor. My kit don't seem to budge.


I didn't think you were running 4000 CL16 at 1T. 
Give a try at CL14 2T, it may be faster.
About tRFC, start with 700 and go down later after you are sure there are no errors.
I can't do CL14 1T at all, even with Setup times it's really hard to get rid of all erroring.
But performance wise, at least with dual CCD, it doesn't go much faster than 2T.
A few hundreds MB/s in bandwidth and almost same latency.


----------



## Baio73

ManniX-ITA said:


> No, first make it work at 2T and maybe one day try 1T.
> 2T is going to be faster than 1T GDM.
> If you want to attempt something later either be 1T GDM Off or same with Setup times.
> 
> I didn't read about the 1.5V DIMM.
> Depends on the DIMM but you'll probably need more for tRCDRD 14.
> 
> What you can run and at what voltage really depends on your setup and the termination settings.
> You have to do a lot of tests and run TM5 for very long hours...


Thaks again.
I used DRAM Calculator (it always gave me higher values, so I gave it up for GitHub guide) and set SOC, VDDG CCD, VDDG IOD and CLDO VDDP voltages as calculated (with my current settings I only need to set SOC and VDIMM, the other 3 are ok in Auto even if they are automatically set to lower values then Calculator says), then I tried to raise the values you marked in red, but stress test stops quite immediately with errors (even with tCL 16 instead of 14) when testing GDM OFF and 2T.

These RAM are very strange, they are well binned (Samsung B-Die A0) but it seems they can't be stable without GDM on.

Baio


----------



## TimeDrapery

Spoiler






Baio73 said:


> Maybe sometimes it's better reading what other users write, instead of trying (and not being successfull) to be humorous.
> I'm not overclocking my RAM from zero, I've already followed GitHub guide and reached a good result.
> I was just asking if there is something different to do to disable GDM and keep 1T on, as the guide does not say anything specific about it.
> Thanks anyway for your kindness and for the time you wasted to reply to my post.
> 
> Baio






@Baio73 

Here, I fixed this for you...

"Maybe sometimes it's better _reading what other users write_, instead of trying (and not being successfull[sic]) to demand that a bunch of strangers on the internet do the hard work of learning something new for me"

I'm not trying to be humorous... What I recommended you do is likely the absolute best way you're going to answer your questions and attain your goals, do with it what you will 😂😂😂😂😂


----------



## Baio73

TimeDrapery said:


> @Baio73
> 
> Here, I fixed this for you...
> 
> "Maybe sometimes it's better _reading what other users write_, instead of trying (and not being successfull[sic]) to demand that *a bunch of strangers on the internet do the hard work of learning something new for me*"
> 
> I'm not trying to be humorous... What I recommended you do is likely the absolute best way you're going to answer your questions and attain your goals, do with it what you will 😂😂😂😂😂


And this is not what I was asking, but you keep not reading my posts.
Save the effort to answer, you are now in my IL.
Bye

Baio


----------



## TimeDrapery

Spoiler






Baio73 said:


> And this is not what I was asking, but you keep not reading my posts.
> Save the effort to answer, you are now in my IL.
> Bye
> 
> Baio






Excellent, @Baio73 , you're not on my ignore list because I wanna read more of the stupid **** you post...

"Duh, I read a guide and then gave up... Hurry strangers! Spoon feed me settings that will work to accomplish the arbitrary ass goals I've established"


----------



## Audioboxer

AGESA 1.2.0.6b still has the voltage bug 🤡


----------



## ManniX-ITA

Baio73 said:


> sed DRAM Calculator (it always gave me higher values, so I gave it up for GitHub guide) and set SOC, VDDG CCD, VDDG IOD and CLDO VDDP voltages as calculated (with my current settings I only need to set SOC and VDIMM, the other 3 are ok in Auto even if they are automatically set to lower values then Calculator says),


This could be an issue, DRAM Calc is pretty old and not updated.
The voltages suggested are for Zen2 not Zen3.
Can you post Zentimings screenshot with the 2T settings you are trying to run?

Use TM5 with 1usums v3 config.
It's easier to understand where the issue could be.


----------



## ManniX-ITA

Audioboxer said:


> AGESA 1.2.0.6b still has the voltage bug 🤡


CPU vCore VID at EDC > 140A or again the VDDG?


----------



## Audioboxer

ManniX-ITA said:


> CPU vCore VID at EDC > 140A or again the VDDG?


The EDC voltage cap if you go over 140.










Just giving OCCT a spin of this as well. Passing all testing apps now.


----------



## Luggage

ManniX-ITA said:


> CPU vCore VID at EDC > 140A or again the VDDG?


Any bets he’s allowed to give an answer?








ASUS ROG X570 Crosshair VIII Overclocking &amp...


Same voltage restriction trash @safedisk. Back to 3801 once again.




www.overclock.net


----------



## Veii

Taraquin said:


> I must disagree a bit Veii, for some you might need 1175/1050+ soc/iod for fclk 2000, but I get no benefit going above 1120/1040. I thought 1110/1030 was the lowest at full speed, but after a lot of testing I seem to get 0.3ns better aida with 1120/1040. I have tried 1130/1050 and 1160/1080, but get no benefit, allcore apps run slower since it steals from core budget.


Yep , you have a better sample 
It might sound strange, but mine is really bellow average



Audioboxer said:


> Yeah I'll give frosted a go next time I do a loop drain, hopefully in a month or so if my EVGA step up finally comes in...
> 
> Tested it on some scrap tubing with very light sandpaper and it seems to be quite easy to get going, but as the video shows likely just take a bit longer and care to get a "retail finish". It does look nice though!! There's no way I'm buying frosted tubing and redoing all these bends, so it'll be DIY frosted 👀


I forgot if he or another guy mentioned, but you should sand them after bending , as the heat will "ruin" the finish
My current project awaits some. Yet your bents are well made !
The red was surprisingly not overdone , tamed by a lot of white.
It makes me wonder why you don't use the flow rpm thing, to check flowspeed ~ when we know flowmeters are not accurate

Hearing for the first time that bents will do thaat much to flowrate
Usually just the different type of parts, rads and blocks show a difference
I was about to attempt a spiral too


ccxmonster said:


> I got another question confusing my mind. would using CR2T command rate let us lower the voltages further ?


Compared to 1T, maybe
compared to GDM, well no

A "correct" GDM preset will run on the same VDIMM, with 2T mode
soo the check "can you run 2T" is easy to check whereever half-strain on the PCB thanks to GDM, really hid issues
and as it's barely slower, and allows you to run odd timings ~ it gives more control and peace of mind that the preset really is "ok"
1T is a whole new league and dual rank usually rarely can run it ~ nearly always needs SETUP timings that slow down align the signal correctly.
Something is strange with dual rank and 1T


Audioboxer said:


> AGESA 1.2.0.6b still has the voltage bug 🤡


"Feature"

@ManniX-ITA please add Geekbench 3 for memory timings testing
AES on Geekbench (both) can overshoot to over 40% increase, if it overboosts consistently


----------



## Audioboxer

Veii said:


> Yep , you have a better sample
> It might sound strange, but mine is really bellow average
> 
> 
> I forgot if he or another guy mentioned, but you should sand them after bending , as the heat will "ruin" the finish
> My current project awaits some. Yet your bents are well made !
> The red was surprisingly not overdone , tamed by a lot of white.
> It makes me wonder why you don't use the flow rpm thing, to check flowspeed ~ when we know flowmeters are not accurate
> 
> Hearing for the first time that bents will do thaat much to flowrate
> Usually just the different type of parts, rads and blocks show a difference
> I was about to attempt a spiral too
> 
> Compared to 1T, maybe
> compared to GDM, well no
> 
> A "correct" GDM preset will run on the same VDIMM, with 2T mode
> soo the check "can you run 2T" is easy to check whereever half-strain on the PCB thanks to GDM, really hid issues
> and as it's barely slower, and allows you to run odd timings ~ it gives more control and peace of mind that the preset really is "ok"
> 1T is a whole new league and dual rank usually rarely can run it ~ nearly always needs SETUP timings that slow down align the signal correctly.
> Something is strange with dual rank and 1T
> 
> "Feature"
> 
> @ManniX-ITA please add Geekbench 3 for memory timings testing
> AES on Geekbench (both) can overshoot to over 40% increase, if it overboosts consistently


With 4 rads, 3 blocks and only 1 D5 Pump the flow meter was really just for visual appeal as I'll be near the efficiency limit for a single pump. As long as my temps stay cool it's fine, and since putting my bottom rad to intake my temps have been great. Pump speed between 75% and 100% I don't notice much difference if any with cooling. 75% is very quiet, 100% has a slightly louder sound.

The flow spinner in the GPU block and the one in the loop spin fast as well so  Investing in a proper flow meter would just be "pointless" at this point, other than wanting to accurately know what the rate is.


----------



## Veii

Audioboxer said:


> The flow spinner in the GPU block and the one in the loop spin fast as well so  Investing in a proper flow meter would just be "pointless" at this point, other than wanting to accurately know what the rate is.


High speed cam , it's just an RPM indicator, for water instead of air 
Should be more accurate than the digital ones , i think


----------



## ManniX-ITA

Veii said:


> @ManniX-ITA please add Geekbench 3 for memory timings testing


Always, when I finish a round of optimizations 





__





Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





Problem is GB3 once is open it's running some background thread heating the CPU.
Single thread results are depending on how quickly I can start it.


----------



## Audioboxer

Veii said:


> High speed cam , it's just an RPM indicator, for water instead of air
> Should be more accurate than the digital ones , i think


The temp sensor is at least accurate in the Bykski, but a temp sensor is easy to do lol.

Btw Veii does VDDP scale at all below 0.9v or best just to leave it there?










I'm already surprised that CCD is happy at 0.9v!


----------



## ManniX-ITA

Audioboxer said:


> I'm already surprised that CCD is happy at 0.9v!


Did you run Geekbench 5 with the new CCD voltage?


----------



## Audioboxer

ManniX-ITA said:


> Did you run Geekbench 5 with the new CCD voltage?


Yes, scores are the same. Well, not exactly the same number, but MOE and no regression on the figures you mentioned to look at.


----------



## Veii

Audioboxer said:


> Btw Veii does VDDP scale at all below 0.9v or best just to leave it there?


Actually, i think it's beneficial
but hence it's only MCLK related ~ it will differ
Dual rank will be completely different than Single Rank

The only reason it might not be, is global procODT
but then VDD18 messes that up, soo idk sadly

Some good samples can run 870 some good samples can run 820 on 1900/1900 MCLK
But hence tPHY balancing depends on VDIMM, CLKDrvStr, RTT and this cLDO_VDDP
You likely can need to adjust it +/- 5mV, if it starts to switch over to unbalanced tPHY


ManniX-ITA said:


> Always, when I finish a round of optimizations


I havee zero metrics for this, but couple of Buildzoid's twitch user do run it
soo i wonder if 10k on 1 CCD is even good , and with what it scales
only recently broke 9900 mark with memory timings

His chat-userbase mentioned 10k being normal/the target for dual CCD ones
unsure with what it scales, if FCLK = write bandwidth or access latency or intercore latency/cache speed


----------



## Luggage

Audioboxer said:


> The temp sensor is at least accurate in the Bykski, but a temp sensor is easy to do lol.
> 
> Btw Veii does VDDP scale at all below 0.9v or best just to leave it there?
> 
> View attachment 2547789
> 
> 
> I'm already surprised that CCD is happy at 0.9v!


I got suckered by igors review of the AC high flow next.









Aqua Computer high flow NEXT Review - Much more than just an accurate flow meter. Only it can’t speak yet. | igor'sLAB


With the Aqua Computer high flow NEXT, the Swiss Army Knife for custom loops with lots of functions and accuracy has been available since this year for just under 70 Euros. Does anyone remember the…




www.igorslab.de





Partly since I use an octo for fan and pump control though.


----------



## ManniX-ITA

Audioboxer said:


> Yes, scores are the same. Well, not exactly the same number, but MOE and no regression on the figures you mentioned to look at.


I was curious to compare with mine, can you share it?





__





Micro-Star International Co., Ltd. MS-7D13 F2000 Baseline - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





I've noticed there are some tests which are were way faster with AGESA 1.2.0.5 and I'd like to see if yours as well is doing the same.
Of course the MT can't be compared...


----------



## Veii

Funny 
Geekbench 3




__





Micro-Star International Co., Ltd. MS-7D13 vs 10° Room Temp - Geekbench Browser






browser.geekbench.com




Geekbench 5




__





10° RoomTemp vs Micro-Star International Co., Ltd. MS-7D13 F2000 Baseline - Geekbench Browser






browser.geekbench.com





I can never beat you , but on some little things ~ it's quite close to a 5950X @ManniX-ITA
Mostly in floating point perf & maaybe 1% in memory perf 
Just stream scale needs to be figured out - maybe that's indeed write perf


----------



## Audioboxer

ManniX-ITA said:


> I was curious to compare with mine, can you share it?
> 
> 
> 
> 
> 
> __
> 
> 
> 
> 
> 
> Micro-Star International Co., Ltd. MS-7D13 F2000 Baseline - Geekbench Browser
> 
> 
> Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.
> 
> 
> 
> browser.geekbench.com
> 
> 
> 
> 
> 
> I've noticed there are some tests which are were way faster with AGESA 1.2.0.5 and I'd like to see if yours as well is doing the same.
> Of course the MT can't be compared...
















__





Micro-Star International Co., Ltd. MS-7D13  - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





I broke 20k last year but have been struggling to get over 20k on AGESA 1.2.0.5. I can't remember if it was Windows 10 as well, I'll go find the post.

*edit* - Over 20k Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser It was Windows 11, but AGESA 1.2.0.3c. I really need to work on my curve/PBO settings with 1.2.0.5... My single core is suffering.


----------



## Luggage

Veii said:


> Actually, i think it's beneficial
> but hence it's only MCLK related ~ it will differ
> Dual rank will be completely different than Single Rank
> 
> The only reason it might not be, is global procODT
> but then VDD18 messes that up, soo idk sadly
> 
> Some good samples can run 870 some good samples can run 820 on 1900/1900 MCLK
> But hence tPHY balancing depends on VDIMM, CLKDrvStr, RTT and this cLDO_VDDP
> You likely can need to adjust it +/- 5mV, if it starts to switch over to unbalanced tPHY
> 
> I havee zero metrics for this, but couple of Buildzoid's twitch user do run it
> soo i wonder if 10k on 1 CCD is even good , and with what it scales
> only recently broke 9900 mark with memory timings
> 
> His chat-userbase mentioned 10k being normal/the target for dual CCD ones
> unsure with what it scales, if FCLK = write bandwidth or access latency or intercore latency/cache speed


With zen timings 









Luggage`s Geekbench3 - Multi Core score: 49388 points with a Ryzen 7 5800X


The Ryzen 7 5800X @ 5050.4MHzscores getScoreFormatted in the Geekbench3 - Multi Core benchmark. Luggageranks #null worldwide and #null in the hardware class. Find out more at HWBOT.




hwbot.org













Luggage`s Geekbench3 - Single Core score: 7149 points with a Ryzen 7 5800X


The Ryzen 7 5800X @ 5050.4MHzscores getScoreFormatted in the Geekbench3 - Single Core benchmark. Luggageranks #null worldwide and #null in the hardware class. Find out more at HWBOT.




hwbot.org


----------



## ManniX-ITA

Veii said:


> I can never beat you , but on some little things ~ it's quite close to a 5950X @ManniX-ITA


Goliath vs David 
Don't know why I've always had a weak HTML5 ST score... maybe it's very sensible to temperature.

Still quite close and priced a 3rd!



Audioboxer said:


> I broke 20k last year but have been struggling to get over 20k on AGESA 1.2.0.5. I can't remember if it was Windows 10 as well, I'll go find the post.


If you didn't, you should update to 5.4.4 some tests are giving slightly different score.

As with the scores when I've run A4 the Camera, Ray Tracing and and Machine Learning tests are scoring higher.

But your CCD voltage is too low; try going up in small steps.
Probably around 930mV is the best.

You AES-XTS score in ST should be around 4500-4600.
And in MT much higher than mine, 9900 is low.
You should have between 10300 and 10500.
Which is probably the reason in Machine Learning MT your score is lower, the CCDs can't keep up.
Same as ST it should be considerably higher than mine due to the AGESA.


----------



## Audioboxer

ManniX-ITA said:


> Goliath vs David
> Don't know why I've always had a weak HTML5 ST score... maybe it's very sensible to temperature.
> 
> Still quite close and priced a 3rd!
> 
> 
> 
> If you didn't, you should update to 5.4.4 some tests are giving slightly different score.
> 
> As with the scores when I've run A4 the Camera, Ray Tracing and and Machine Learning tests are scoring higher.
> 
> But your CCD voltage is too low; try going up in small steps.
> Probably around 930mV is the best.
> 
> You AES-XTS score in ST should be around 4500-4600.
> And in MT much higher than mine, 9900 is low.
> You should have between 10300 and 10500.
> Which is probably the reason in Machine Learning MT your score is lower, the CCDs can't keep up.
> Same as ST it should be considerably higher than mine due to the AGESA.


I'll check that out now. I forgot when AUTO OC is enabled it's always hurt my ST score in GB5. I had it on +25mhz. Turning that off brings ST back up to a better number





__





Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





Will update to 5.4.4 as well. I'm on 5.4.3.


----------



## Veii

ManniX-ITA said:


> Goliath vs David
> Don't know why I've always had a weak HTML5 ST score... maybe it's very sensible to temperature.
> 
> Still quite close and priced a 3rd!


Eh, just disable 10 cores 

Would be funny, if i'll ever get the 2nd CCD to "not" be suppressed
a 14 core ryzen 

I'm actually happy with the result, only the tiny memory part is bothering me
Makes me more wonder why you don't score that much higher, feels like it doesn't even hold 4.85 on some of the tests
I expected like Audioboxer's to completely crush it ~ +200%
Cache, and everything ~ ontop of that 2000 + 200mhz higher boost vs 2100 FCLK

Eh if you really hold 4.85+ on everything, then i guess it shows that FCLK keeps scaling
Although i can not cool it correctly to show it's true perf
It's all more of a dream and ideal scenario than reality


----------



## ManniX-ITA

Veii said:


> Makes me more wonder why you don't score that much higher, feels like it doesn't even hold 4.85 on some of the tests


It doesn't indeed 

Running OCCT, depends on the config, on the best core the clocks varies from 4550 to 4850 MHz.
Medium workloads runs around 4900 MHz, only very light ones and shorts bursts runs at 5 GHz and higher.


----------



## Luggage

Audioboxer said:


> I'll check that out now. I forgot when AUTO OC is enabled it's always hurt my ST score in GB5. I had it on +25mhz. Turning that off brings ST back up to a better number
> 
> 
> 
> 
> 
> __
> 
> 
> 
> 
> 
> Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser
> 
> 
> Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.
> 
> 
> 
> browser.geekbench.com
> 
> 
> 
> 
> 
> Will update to 5.4.4 as well. I'm on 5.4.3.


You are only boosting to 5.02-5.03.




__





Geekbench Browser






browser.geekbench.com




You should turn it up 






Micro-Star International Co., Ltd. MS-7C35 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7C35 with an AMD Ryzen 7 5800X processor.



browser.geekbench.com







Edit: *** I’m not boosting that much higher…





__





Geekbench Browser






browser.geekbench.com





Oh but perhaps more consistent


----------



## Audioboxer

ManniX-ITA said:


> Goliath vs David
> Don't know why I've always had a weak HTML5 ST score... maybe it's very sensible to temperature.
> 
> Still quite close and priced a 3rd!
> 
> 
> 
> If you didn't, you should update to 5.4.4 some tests are giving slightly different score.
> 
> As with the scores when I've run A4 the Camera, Ray Tracing and and Machine Learning tests are scoring higher.
> 
> But your CCD voltage is too low; try going up in small steps.
> Probably around 930mV is the best.
> 
> You AES-XTS score in ST should be around 4500-4600.
> And in MT much higher than mine, 9900 is low.
> You should have between 10300 and 10500.
> Which is probably the reason in Machine Learning MT your score is lower, the CCDs can't keep up.
> Same as ST it should be considerably higher than mine due to the AGESA.


Can't replicate those numbers, right up to 0.975v on CCD. I just barely got over 10k on MT at 0.975v.

How big an issue are PBO settings?

When I broke 20k my AES-XTS figures were bad compared to what you suggest they should be






Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





PBO on the profile above and now is the same, even if AGESA is different. 270/168/220. What PBO values are you using?

CCD at 1v, just touching 10k again Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser

Are there any BIOS settings that could hurt AES-XTS?

*edit* - I've been browsing the 5950x scores for GB5 on its site and anything around 10k on MT seems about normal? Haven't found any MT AES-XTS scores at like 10,500. I did notice it seems my ST scores suffer, so I tried changing my PBO to 250/160/190, and that bumps it up a bit





__





Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





MT is still just about at 10k. So it seems like PBO values can definitely impact AES-XTS. TDC/EDC at 168/220 was clearly favouring MT and hurting ST a little, but that's the balance with PBO between ST and MT I guess. If I run CB23 now my score will be lower with 160/190.

*edit2* - 260/165/195





__





Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





4422 on ST now, MT still just about 10k

*edit3* - I was at 4425 posts ago on ST with 270/168/220 









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Yep , you have a better sample :) It might sound strange, but mine is really bellow average I forgot if he or another guy mentioned, but you should sand them after bending , as the heat will "ruin" the finish My current project awaits some. Yet your bents are well made ! The red was...




www.overclock.net





These scores are just varying wildly between runs.


----------



## MrHoof

Well reading this i thought compare some geekbench5 myself. This is Air cooled by u12a. 
Blue vSoc 1.0625v IOD 0.98v CCD 0.9v VS Grey vSoc 1.1v IOD 1.05v CCD 0.94v
System manufacturer System Product Name vs System manufacturer System Product Name - Geekbench Browser
and here 2 diffrent runs at 1.0625v IOD 0.98v CCD 0.9v
System manufacturer System Product Name vs System manufacturer System Product Name - Geekbench Browser


----------



## domdtxdissar

*Sample size of 1 per run*

1900:3800

















2000:4000

















1900:4460


----------



## ManniX-ITA

Audioboxer said:


> How big an issue are PBO settings?


What could be limiting is VSOC.

Weird... 
I've always seen it scaling up solely based on silicon quality and CCD voltage.
But it's also dependent on clock frequency that you can sustain.
Maybe the AGESA 1.2.0.5 is really hurting your clocks.

At least looking at the other scores it should be higher.

I think @domdtxdissar is scoring much higher.
Oh yeah he posted 
Didn't realize FCLK would have such a big influence.
Guess we can take dom scores at 1900:3800 as a best reference.

Also raising VDD18 can also help. But it shouldn't be necessary.

Maybe it's like my HTML5 score which is always lower than anyone else.
For you could be AES-XTS.

I'm using PBO 300/175/215 with Scalar 8x and Boost clock 100 MHz.


----------



## Audioboxer

Yeah, seems to me like CB23 all over again. You run it on Tuesday instead of Thursday and you magically have 100 points more 

Or you run it on your test bench instead of your normal Windows installation. I'm just firing my runs through normal Windows, not even closing anything.

ST is consistently 44xx now, MT is 99xx, occassionally just over 10k. That'll do.

@Veii IIRC dom has his VSOC down at AUTO/1.1v as well now. Unless those above runs are back at his old values.


----------



## ManniX-ITA

Audioboxer said:


> Or you run it on your test bench instead of your normal Windows installation. I'm just firing my runs through normal Windows, not even closing anything.
> 
> ST is consistently 44xx now, MT is 99xx, occassionally just over 10k. That'll do.


Yes that could be


----------



## Audioboxer

ManniX-ITA said:


> Yes that could be


Wish benching apps weren't so sensitive to this lol. I have a reasonably lean Windows and it's still a PITA doing AIDA runs in diagnostic mode just to score in relation to everyone else lol.

CB23 is the worst though, open a window and +400 points.


----------



## Veii

An Overboost bug increase of 40% , on AES
The rest is just "cold" scaling , to prevent throttle


----------



## Audioboxer

Veii said:


> An Overboost bug increase of 40% , on AES
> The rest is just "cold" scaling , to prevent throttle


What is the overboost bug? If I hear the word bug I just assume something AMD has broken or done wrong 😂

Speaking of scalar you mentioned above, this is something I've never used. I thought the general advice was just leave it on AUTO or 2x at most. Is there performance to be gained from increasing it?


----------



## Luggage

Audioboxer said:


> Yeah, seems to me like CB23 all over again. You run it on Tuesday instead of Thursday and you magically have 100 points more
> 
> Or you run it on your test bench instead of your normal Windows installation. I'm just firing my runs through normal Windows, not even closing anything.
> 
> ST is consistently 44xx now, MT is 99xx, occassionally just over 10k. That'll do.
> 
> @Veii IIRC dom has his VSOC down at AUTO/1.1v as well now. Unless those above runs are back at his old values.


Windows + Ryzen boost behavior + thermals -> any benchmark is like Aida, run 5 times and throw away the outliers (or post the top one on hwbot  )

“This change gained/lost me 100 cb r23 points” - oh really or did you open the door to your room while windows wasn’t having a hiccup?



http://imgur.com/5La5PBl


And all that I can throw away and wait for colder weather 



http://imgur.com/xG593sl


----------



## Audioboxer

lol, talk about me answering my own question @Veii , +100mhz and scalar 10x















Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





Although my overall scores are a bit pants. +100mhz might be the issue, GB5 has never liked AUTO OC for me. Guessing scalar 10x might have helped AES-XTS MT.

Away to turn off AUTO OC and see if AES-XTS maintains.

*Edit* - Above seems to be a bugged run?

Scalar 10x on its own






Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





Scalar 10x +100mhz AUTO OC (2nd run)






Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





Back down under 10k. I have no idea what is going on to produce that 10772...

If in doubt, blame AGESA/chipset drivers/Windows 11 😂

*edit 2* - Scalar x10 +200mhz AUTO OC






Micro-Star International Co., Ltd. MS-7D13 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7D13 with an AMD Ryzen 9 5950X processor.



browser.geekbench.com





Still, just below 10k.


----------



## domdtxdissar

Gremlings everywhere


----------



## PJVol

Veii said:


> it's quite close to a 5950X


Wow, that's a hell of a throttling here ))








My best so far with a 1203c agesa:





BIOS 2.10 DDR 4000 CL15-15-15-30-45-288 - Geekbench Browser


Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.



browser.geekbench.com


----------



## Audioboxer

@domdtxdissar are your GB5 runs using Hydra or just PBO?

Wondering if Hydra does a better job of maintaining a multicore clock speed during the necessary MT testing.

Then above if it's not a GB5 bug I possibly got lucky with scalar 10x and whatever cores the windows scheduler decided to use/maintain... 

Struggling to think of any other reason for that single result.

Boosting seems like a total crapshoot anyway since AGESA 1.2.0.5 and whatever the hell AMD are doing with Windows 11 chipset drivers. There's like 3 different manufacturer WHQL releases and AMDs website is still stuck on an early November release.

AMD has to be the most incompetent software developer I've seen apart from when MS decide to cripple their own OS.

Corsair a good runner up for iCUE, though all the peripheral manufacturers do not have the kinds of resources AMD and MS have. The bugs AMD has put out with AGESA alone are shockingly incompetent.


----------



## domdtxdissar

Audioboxer said:


> @domdtxdissar are your GB5 runs using Hydra or just PBO?


PBO CO
In my testing hydra is to slow switching profiles in burstly workloads like geekbench 3-4-5


----------



## Audioboxer

domdtxdissar said:


> PBO CO
> In my testing hydra is to slow switching profiles in burstly workloads like geekbench 3-4-5


Good point!

Do you use the scalar function?


----------



## PJVol

Audioboxer said:


> AMD has to be the most incompetent software developer I've seen apart from when MS decide to cripple their own OS.


Try to write something before judge, wth...


----------



## Audioboxer

PJVol said:


> Try to write something before judge, wth...


We aren't talking about someone writing code on GitHub, this is a company worth billions releasing bios that nukes USB devices, then locks VDDG voltage to 1v max and now locks their own VCORE voltage after telling everyone up to 1.5v is fine. Chipset drivers released with bits missing and scheduler/performance issues.

Heck, on 3xxx 1usmus and others created their own powerplans to fix poor performance.

Then we've got AMD Ryzen Master that can't even start with Windows and could be better.

We've got enthusiast OCers on this forum digging as deep as they can into AMD hardware and some of the software and telling everyone what they're doing wrong.

So yeah, I guess some of the OCer community is "writing code" for AMD.

I ain't one for brand loyalty, so I call it as I see it. They make some good hardware then let themselves down constantly causing issues with software.


----------



## MrHoof

Can only agree on audioboxer when asus puts this disclaimer under the new bioses.
Feels like rather pushed by request from reddit etc. that asus is not putting out updates yet but others do...
"Update AMD AM4 AGESA V2 PI 1.2.0.6b
Please note that this is a beta BIOS version of the motherboard which is still undergoing final testing before its official release. The UEFI, its firmware and all content found on it are provided on an “as is” and “as available” basis. ASUS does not give any warranties, whether express or limited, as to the suitability, compatibility, or usability of the UEFI, its firmware or any of its content. Except as provided in the Product warranty and to the maximum extent permitted by law, *ASUS is not responsible for direct, special, incidental or consequential damages resulting from using this beta BIOS*."


----------



## Audioboxer

MrHoof said:


> Can only agree on audioboxer when asus puts this disclaimer under the new bioses.
> Feels like rather pushed by request from reddit etc. that asus is not putting out updates yet but others do...
> "Update AMD AM4 AGESA V2 PI 1.2.0.6b
> Please note that this is a beta BIOS version of the motherboard which is still undergoing final testing before its official release. The UEFI, its firmware and all content found on it are provided on an “as is” and “as available” basis. ASUS does not give any warranties, whether express or limited, as to the suitability, compatibility, or usability of the UEFI, its firmware or any of its content. Except as provided in the Product warranty and to the maximum extent permitted by law, *ASUS is not responsible for direct, special, incidental or consequential damages resulting from using this beta BIOS*."


MSI are normally fairly quick to pump out the betas as well, but so far they've ignored 1.2.0.6 completely.

ASUS dropped 1.2.0.6 a few weeks back, now 1.2.0.6b with this updated "warning" lol.

Combined with whatever is going on with chipset drivers I wonder if things are a bit of a mess behind the scenes. Not sure if any of this is tied up with AM5 experimentations.


----------



## PJVol

Audioboxer said:


> We've got enthusiast OCers on this forum digging as deep as they can into AMD hardware and some of the software and telling everyone what they're doing wrong.


I just want people not to jump to conclusions based on one or two opinions here and there. Here was a long post by @Veii with a list of what's wrong on his opinion.
With all the respect, I can say 2/3 claims from that list is at least questionable.

Regarding firmware, it's clear almost for everyone here that 1205 bios is bugged, asrock still has no release status on latest fw. So what's the need to update then?

Here's one more opinion on the matter:
aside from usb bug (which I experienced most of the time as "PC sometimes hangs until usb device is pulled out" on a certain usb ports) and then fixed 3000 series CPU scheduler issues, I can't see a single flaw anywhere in the platform, so calling such a big software engineer team incompetent looks reckless to say the least.


----------



## lafonte

Hi, I have a 5950x on a gigabyte x570 aorus pro rev 1.2 with a gskill 8GB x 4 3200c14 Samsung b-die on Linux. If I run the kit with the following settings

VDram 1.45
Vsoc 1.045
CPU Vddp 720
Vddp 760
Vddg ccd 760
Vddg iod 960
IF 1900 
dram 3800
Tcl 16
Trcdrd 16
Trcdwr 16
Trp 16
Tras 30
Trc 42
Twr 10
Tcwl 16
Trrd_s 4
Trrd_l 4
Twtr_s 4
Twtr_l 8
Trfc 300
Trtp 8
Tfaw 16
Trdwr 8
Twrrd 3
Trdrdsc_l 5
Trdrdsc 1
Trdrdsd 4
Trdrddd 5
Twrwrsc_l 5
Twrwrsc 1
Twrwrsd 6
Twrwrdd 7
Power down mode off
Command rate 1T
Gdm off

the system pass 1000% memtest deluxe and also multiple runs of y-cruncher without issues but if I run a large fft workload with y-cruncher or prime 95 I get errors in the best case after 20min at times in the first 5 minutes. I tried almost everything different proc odt, higher voltage for the dram, the vsoc, the CPU Vddp, the vddp, both the vddg, loose subtiming, gdm on, different combinations of Rtt and drvstr, nothing help the only solution I've found is set the primary timing to 18 18 18 18 32 50 or run in T2 . Does someone has any ideas to what can cause the problem and how I can try to solve it without increase the primary timing? Thanks


----------



## domdtxdissar

Audioboxer said:


> Good point!
> 
> Do you use the scalar function?


yes, 10x


----------



## Baio73

ManniX-ITA said:


> This could be an issue, DRAM Calc is pretty old and not updated.
> The voltages suggested are for Zen2 not Zen3.
> Can you post Zentimings screenshot with the 2T settings you are trying to run?
> 
> Use TM5 with 1usums v3 config.
> It's easier to understand where the issue could be.


Thanks as always for your time.
These are the settings I'm testing (VRAM 1.49v):



And this is TM5's logt:

========= TestMem5 Log File =========
Customize: Default @1usmus_v3
Start testing at 7:33, 464Mb x24
Error in test #12 through 16 sec.
Error in test #12 through 2m 50s.
Error in test #2 through 2m 54s.
Error in test #10 through 3m 7s.
Error in test #11 through 4m 41s.
Error in test #11 through 4m 45s.
Error in test #6 through 4m 59s.
Error in test #12 through 5m 5s.
Error in test #12 through 5m 5s.
Error in test #2 through 5m 16s.
Error in test #2 through 5m 22s.
Error in test #13 through 6m 11s.
Error in test #9 through 6m 18s.
Error in test #8 through 6m 31s.
Testing is completed through 7m 3s,
detected 347 error(s).

I don't see anything useful in the log, should I look elsewhere?

Baio


----------



## Veii

PJVol said:


> Wow, that's a hell of a throttling here ))
> View attachment 2547875
> 
> My best so far with a 1203c agesa:
> 
> 
> 
> 
> 
> BIOS 2.10 DDR 4000 CL15-15-15-30-45-288 - Geekbench Browser
> 
> 
> Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.
> 
> 
> 
> browser.geekbench.com


Ty for giving a metric. I'll try to meet it
Still worry about 1205+ much. CPU was unstable at the very beginning
Its not like i'm not used to defaulting to COs, aka adjusting
CPU was fine till 5ghz too near 1.375


PJVol said:


> I just want people not to jump to conclusions based on one or two opinions here and there. Here was a long post by @Veii with a list of what's wrong on his opinion.
> With all the respect, I can say 2/3 claims from that list is at least questionable.


Sadly my intention turned, which was at first the goal to make AMD better and support ODMs. Give vendors a preset and show how it can be done.
The intention that let it research deeply into every caveat i can find. Well and holding my promise~

In the current state as platform user, i feel enough of being a testing rabbit.
The testing rabbit part is fine, but AMD's policy feels ruthless.
~ The permissions and hoop's Vendors and Bios engineers have to go through to meet ever changing security protocols
~ The way "these digging OC engineers" are treated and stamped as "rebels". Pretty much the same behaviour NVIDIA * did to HardwareUnboxed YTber
* i shouldn't even start how serious OCer are taken on the Navi side of things. Locking not only frequency peaks, but pro actively designing a bios and mainboard bios modules + drivers, that ensure the OC Engineer scene has as hard of a time as possible, bypassing their overclocking limit's.
~ Same 1.) Part, the outweight of outcry vs the keeping-investor face, and using " for security" as their justification to temporarily ruin the experience for their "actually using the product" userbase | which cover's the EPYC part too
And last but not least:
~ Aside from being an update-based platform, even denying Vendors changelogs & running an only "request for feature, we might approve" waiting-delay-loop, where at the very end only we the users have to eat it. The waiting time.
The vendors will sell their boards and they have to keep a very clear distance from arising issues and hotfixes (which will take weeks to be approved and happen)

Don't get my judgement and intention wrong
I am very cautious when i blame somebody in the industry, or write about this topic in general
(Unless i'm completely p*ssed in how "security" is used to justify self-destructive acts, and run the "fine i'll just fix it myself" mood)

Moving recently more in the LN2 scene and between Engineers and Vendors
I have nothing but respect for all of them, as they are in the middle-fire between AMDs protocols and the users demanding changes on slow/hidden/unfinished changes & unfortunate events that happen throughout the update-time of this platform.

While i do pin-point judge any of the vendor's sometimes quite harsh,
Everyone of my contacts deserves nothing but respect for at least "trying" to find a thin line between '"for consumers" vs "for AMD and not breaking protocol's"
Although quite honestly speaking, even ODMs have to get as creative as we are & chain little open doors somehow together with new revisions, finding a balance to implement "features" which never could exist in AMDs allowed moving range.

It's, complicated
But i can see it is probably not felt from my posts here
The bigger picture of my intention even bothering with AMD and not just changing ships
I mean, on the Vendor treatment side ~ Intel is not somebody to praise
But sometimes the "not carrying" part and letting their Bios engineers finetune it
Is a much smoother experience, than the SunTsu approach of AMD.

Well,
Again its complicated. I understand the core intention, but i will never understand why you are soo ruthless on the security part, that you have to destroy yourself and the public face
Not only to the user base but also to the investing part
Its not like "use AMD" in the mobile sector, has a great taste to it since past Intel+Nvidia bully history.

Yea that's all
Post looks already too big, on the phone.
I hope maybe i'm slightly better understood ~ but can understans well Audioboxer or for example Mongoled on the reports or way of commenting

All on all,
The "group" that has the hardest time, are our actual Vendors & BIOS developer's
We overclockers can afford the use of firely comments, as there is rarely anybody under us that we have to keep face at.
But it is hard, when they fight on two fronts which dislike it other
The userbase that has to eat everything, and AMD who enforces everything, vendor's somehow have to smooth out for the customers
Complicated. . .

Yes,
I'll continue this another day, its already too fiery and slightly negative to read 
Mr. Hallock surely went through a similar loop, but decided to be strictly for AMD.
I shouldn't speak about VanguardGroup and how treatment is usually done. "Requirement's and judgement towards own people, because they where forced to be against the codex"

Ah long long post
If it was for me, the ODMs need more access.
Resolve this signed loop of security wait-for-confirmation, loop which makes crucial hotfixes, get delayed weeks till months.
And maybe let's try to read between the lines of Vendor's, when they refuse support or comment or any sign of life 
They are in the same treatment board, as we users are

EDIT:
Even when the last section sounds very advertisie,
There are *many* contacts in the industry who go already against the protocols. Sometimes it really is needed.
Vendors are at least here, on the communities side ~ to the extend of treatment they can allow to slip through
This includes many of the engineers at the fabs. Which so appear to be rather on the consumer side of things and hiddenly supply sample changes before shipment.

But i should also not comment here further,
Just want to state that the situation is complicated and often the amount "how far a vendor can lean out for us" is not big
Unlike Mr.Hallock, they are not "for AMD only" and try their best *
* here on AM4 at least
Just current protocols are rather "disgusting & self-destructive", if you can excuse my wording here please 😇


----------



## Taraquin

PJVol said:


> Wow, that's a hell of a throttling here ))
> View attachment 2547875
> 
> My best so far with a 1203c agesa:
> 
> 
> 
> 
> 
> BIOS 2.10 DDR 4000 CL15-15-15-30-45-288 - Geekbench Browser
> 
> 
> Benchmark results for a Generic with an AMD Ryzen 5 5600X processor.
> 
> 
> 
> browser.geekbench.com


Nice breaking the 10k barrier, best so far for me at 4000cl16 1t is 9711, but 76W PPT and a bit worse timings is probably what holds me back.


----------



## rossi594

Bix said:


> Another big thumbs down to 1.2.0.5 here. My 5900x now crashes on core 1 with optimised defaults, even after flashing back to 1.2.0.3b (no final patch c for my board either). Decided to RMA rather than make do with a positive offset. I guess whatever the blob 'upgrade' did was enough to push it over the edge into instability at stock, which seems plausible given others here reporting lower negative C/O following the update.
> 
> Obviously hoping for some better silicon this time but still disappointed since my old 5900x seemed to scale _mostly _well at higher FCLK, bar a few scenarios, in spite of not being a great sample.
> 
> Just out of interest, has anyone here got a Zen 3 CPU that clocks well AND scales well beyond 1900 FCLK??


How do you define clocks well?

I can get all 8 of my cores to boost beyond 5.050 without any hazzle and run 2033 flck without tinkering (That's without using a high skalar, without clock streching and all core load, so I think I could probably go beyond 5.100 and 2066 with more effort / voltage). I think I can figure out the limits after this semesters exams when we are hopefully going back to uni. (Right now I kind of depend on the system). The flck scales well in games. I run 1440p 240Hz with a 6900XT, most of my games are cpu limited so I can see the see the differences in the fps counters and feel them.

It's a late B1 revision. It's usally best to get a really really early chip or the latest one of the best revision, either before they focus on yield and essentially only really high silicone quality makes it though or when they are really have the process down and yields are great. (That's the same with almost anything btw. even with Teslas).

I'm kind of still praying for a whea 19 fix.


----------



## Audioboxer

PJVol said:


> I just want people not to jump to conclusions based on one or two opinions here and there. Here was a long post by @Veii with a list of what's wrong on his opinion.
> With all the respect, I can say 2/3 claims from that list is at least questionable.
> 
> Regarding firmware, it's clear almost for everyone here that 1205 bios is bugged, asrock still has no release status on latest fw. So what's the need to update then?
> 
> Here's one more opinion on the matter:
> aside from usb bug (which I experienced most of the time as "PC sometimes hangs until usb device is pulled out" on a certain usb ports) and then fixed 3000 series CPU scheduler issues, I can't see a single flaw anywhere in the platform, so calling such a big software engineer team incompetent looks reckless to say the least.


They don't even release changelogs for what they do with AGESA so the end user has no idea if things are even bugs. If you visit the ASUS mobo topics on this forum we have end users begging an account I presume has contact with people in AMD to go ask if the VCORE bug is... a bug, as we're now seeing it in AGESA 1.2.0.6b.

Communication from AMD is awful and only seems to be teased out if streamers and the tech media kick up a stink. That's not a healthy place to be in, causes resentment and frustration from places like this, the tech communities that have spent the last 5+ years getting lots of people to buy AMD CPUs instead of Intel.

The least AMD could do is better communication about what is bugs and what is them messing about with core functionality communities like this use to take advantage of their hardware.

Don't want to speak about contributors to this forum other than say if it wasn't for people around here I wouldn't have learned how to harness my hardware and all of that advice and info was supplied for free. If people more knowledgeable than me are complaining about AMD bugs and communication I'll listen.


----------



## Veii

Audioboxer said:


> *Edit* - Above seems to be a bugged run?
> 
> 
> Audioboxer said:
> 
> 
> 
> Back down under 10k. I have no idea what is going on to produce that 10772...
> 
> If in doubt, blame AGESA/chipset drivers/Windows 11 😂
Click to expand...

Too small of a difference
A bugged run is 35-40% faster , which is impossible with a single change on similar temps
Bugged run reported over the maximum on write bandwidth / aida - too soo the followup to confirm it being buggy, was geekbench
Next reboot the issue is gone, but anybody can use this is as "fantastic" result


Audioboxer said:


> What is the overboost bug? If I hear the word bug I just assume something AMD has broken or done wrong 😂


Overboost bug happens when cores deep sleep , not idle or soft-suspend at 550mhz
They deepsleep and then are woken up by the powerplan. The wakeup part has higher priority than the throttle down part, soo on wakeup it bypasses it's p-states and goes into boost mode
The slingshot that is causing this, seems to have no direct limiter. Soo it can very well happen that the CPU will request up to state either 1.55v VID or 1.68v VID & actually set a 10+ ghz strap

I can't understand how this was overlooked, but it feels that many of AMDs sample links do overdrive beyond null point ~ and seems to be one of the reasons why samples WHEA on many things
The overboost bug as an own thing always happens, because cores do not have a peak boost target and the boosting system will try to squeeze every little frequency out of it that's possible (by default)

That is, if FIT wouldn't limit voltage in the first place
Soo the bug happens by it deepsleeping, waking up and then bypassing it's powerstates. The slingshot is soo high that it can very well peak far higher than the allowed limits, before even FIT catches it.
Well hence there are no peak limiters.
I think AGESA 1205 has to change this, but AMD looks very conservative on the "amount" of voltage they allow now
It would make more sense to redo the boosting system and redo how CO's function ~ but such is much more work
Also likely outweight, it will create more RMA's by badly "damaged" CPUs , hence ones affected by the voltage caps and changes , are only ones that are low binning to begin with.
Likely the outweight was to mess up some samples and lose a bit of frequency, vs to fully make bronze/wood samples not function at all on stock and increase RMA
^ although last part would rather be the correct way to fix the half-done work that was made

I don't think they can anyways patch it out unless they push an AGESA with low enough access,
But this AGESA will be found, and exploited as security risk ~ and we know what is done to justify security (PCH instability, AGESA 1.1.8.X) 🙃

Edited & Rephrased:
In general, if it was me to decide
Either we just live with it (we = AMD) and like matisse keep our overvolted samples. Soo eat the cost on bad batches but fix the bigger majory
Compared to , try to smooth out our problem, hide it under a carpet and ignore these rare not good samples that will suffer by AGESA 1205 change ~ as we AMD take care a lot about security. We mention it on every of our presentation how important it is, that we will not risk delivering to users and exploitable AGESA that potentially fixes most of users complains on our messup ~ as that will hurt security
* or something like this 

Well no, it likely won't be ever fixed
AMD has to accept a loss and deal with their problem ~ and as long as they won't, they deserve well my mocking & any information i'm willing to share about them
(As long as it doesn't hurt industry friends and makes them lose their job)
AMD does here and there dirty to the industry , soo they will get the same back.
"You enforce already st*pidly restrictive security, all your security data will leak and security be broken"
That's about how it goes, if you are behaving bad towards the industry & treat helping OC Engineers as "Rebels"

AMD will never fix WHEA and likely never allow back higher than +200 boost.
They will probably never fix the overboost bug either
(but i have hopes 1205/6 works on it ~ at least on the efficiency side, by being able to undervolt further the overvolted supplied samples)
Soo as long as AMD won't finally change their industry practices and behaviors towards ODM's/Vendors ~ stop being a bully after getting bullied for 4-5 years
As long as they won't change their industry practices, they will not stop having issues discovered or exploits created.
Hence AMD bullied couple of contacts away from their favorite place to work/be ~ and keeps bullying the industry "for security" , they very well deserve my judgement
I'm just too lazy to make a good list of issues supplied to tech-media , well and actually well-hearted (i hope) , waiting for fixes and giving them a chance after the unstable DPM link fiasco connected to Spectre and other exploits
_(as that was a weekly high priority patch-fest, which they where forced to fix ~ but no user would forget the inconsistency of patches between vendors even
AMD worked hard to mitigate this, soo i'm giving them a bit more of a chance)_

I have sincerely some hopes left that they do not need the grudge and can fix it themself
Than having to be again under release stress, or community pressure ~ repeating the same early release issues that Zen 1 and Zen 2 had
Soo in favor of friends and AMD as a whole ~ i try to support and help where i can, without doing anything for me ~ except maybe getting in more bad-pr fire that i don't need.
Although again this might be read wrong by the "lessen" amounts of post here on OCN *
* and the recently more direct hot takes & posts

I really do have high hopes that they will fix it ~ but currently they abuse the term "for security" too much. . .


----------



## Audioboxer

Veii said:


> Too small of a difference
> A bugged run is 35-40% faster , which is impossible with a single change on similar temps
> Bugged run reported over the maximum on write bandwidth / aida - too soo the followup to confirm it being buggy, was geekbench
> Next reboot the issue is gone, but anybody can use this is as "fantastic" result
> 
> Overboost bug happens when cores deep sleep , not idle or soft-suspend at 550mhz
> They deepsleep and then are woken up by the powerplan. The wakeup part has higher priority than the throttle down part, soo on wakeup it bypasses it's p-states and goes into boost mode
> The slingshot that is causing this, seems to have no direct limiter. Soo it can very well happen that the CPU will request up to state either 1.55v VID or 1.68v VID & actually set a 10+ ghz strap
> 
> I can't understand how this was overlooked, but it feels that many of AMDs sample links do overdrive beyond null point ~ and seems to be one of the reasons why samples WHEA on many things
> The overboost bug as an own thing always happens, because cores do not have a peak boost target and the boosting system will try to squeeze every little frequency out of it that's possible (by default)
> 
> That is, if FIT wouldn't limit voltage in the first place
> Soo the bug happens by it deepsleeping, waking up and then bypassing it's powerstates. The slingshot is soo high that it can very well peak far higher than the allowed limits, before even FIT catches it.
> Well hence there are no peak limiters.
> I think AGESA 1205 has to change this, but AMD looks very conservative on the "amount" of voltage they allow now
> It would make more sense to redo the boosting system and redo how CO's function ~ but such is much more work
> Also likely outweight, it will create more RMA's by badly "damaged" CPUs , hence ones affected by the voltage caps and changes , are only ones that are low binning to begin with.
> Likely the outweight was to mess up some samples and lose a bit of frequency, vs to fully make bronze/wood samples not function at all on stock and increase RMA
> ^ although last part would rather be the correct way to fix the half-done work that was made
> 
> I don't think they can anyways patch it out unless they push an AGESA with low enough access,
> But this AGESA will be found, and exploited as security risk ~ and we know what is done to justify security (PCH instability, AGESA 1.2.0.X) 🙃
> 
> In general, if it was me to decide
> Either we just live with it (we = AMD) and like matisse keep our overvolted samples. Soo eat the cost on bad batches but fix the bigger majory
> Compared to , try to smooth out our problem, hide it under a carpet and ignore these rare not good samples that will suffer by AGESA 1205 change ~ as we AMD take care a lot about security. We mention it on every of our presentation how important it is, that we will not risk delivering to users and exploitable AGESA that potentially fixes most of users complains on our messup ~ as that will hurt security
> * or something like this
> 
> Well no, it likely won't be ever fixed
> AMD has to accept a loss and deal with their problem ~ and as long as they won't, they deserve well my mocking.
> They will never fix WHEA and likely never allow back higher than +200 boost.
> They will probably never fix the overboost bug either (but i have hopes 1205/6 works on it ~ at least on the efficiency side, by being able to undervolt further the overvolted supplied samples)


The funny thing is even if this is action to try and quickly stop RMAs due to such a bug Ryzen Master completely bypasses the voltage limit and if you search for help OCing your CPU you will find this answer here, on Reddit and other websites.

Our complaints are mostly about effeciency, setting PBO limits in the BIOS and forgetting them. Having to remember to load Ryzen Master every Windows boot and apply your PBO settings just introduces an annoyance that wasn't once there. This is why we need communication to know if this is a bug or "feature".

I'm going to see if I can in any way replicate that 107xx score. Will turn off all c-states and experiment. Something caused it to happen and the scores of the other tests in that run line up with other runs.


----------



## rossi594

Luggage said:


> I got suckered by igors review of the AC high flow next.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Aqua Computer high flow NEXT Review - Much more than just an accurate flow meter. Only it can’t speak yet. | igor'sLAB
> 
> 
> With the Aqua Computer high flow NEXT, the Swiss Army Knife for custom loops with lots of functions and accuracy has been available since this year for just under 70 Euros. Does anyone remember the…
> 
> 
> 
> 
> www.igorslab.de
> 
> 
> 
> 
> 
> Partly since I use an octo for fan and pump control though.


My Octo keeps crapping out from time to time and when it does so the fans ramp to 100%, so I just run my fans on static ~550rpm (can not hear them at that speed).
But I prefer the poweradjust and pump combination to the pwm pumps. It's a bit sad that Aquasuite does not allow you to regulate the pump by the flowmeter of the Hi-Flow Next.

So overall is it worth it to spend ~180€ on monitoring? Kinda. The virtual software sensors in Aquasuite are neat and much easier to set up than complex monitoring tools. The Hi-Flow Next does a good job, just skip the Quadro / Octo in my opinion.


----------



## Bix

rossi594 said:


> How do you define clocks well?
> 
> I can get all 8 of my cores to boost beyond 5.050 without any hazzle and run 2033 flck without tinkering (That's without using a high skalar, without clock streching and all core load


I think yours definitely fits the bill! Fingers crossed for my new 5900x which should arrive this week...


----------



## Taraquin

ManniX-ITA said:


> I didn't think you were running 4000 CL16 at 1T.
> Give a try at CL14 2T, it may be faster.
> About tRFC, start with 700 and go down later after you are sure there are no errors.
> I can't do CL14 1T at all, even with Setup times it's really hard to get rid of all erroring.
> But performance wise, at least with dual CCD, it doesn't go much faster than 2T.
> A few hundreds MB/s in bandwidth and almost same latency.


I give up, no matter what I try ram overheats when I set voltage above 1.5V and I need a bit over 1.5V to get below cl16 even at 2t, rcdrd 17, faw 20, rfc 300+. I need a better bin ram or another CPU-cooler if I want to get faster scores, but I`m satisfied with the performance I have and probably need at top bin B-die to run 4000cl15 or tighter at 1.5V or below.


----------



## Taraquin

Veii said:


> Yep , you have a better sample
> It might sound strange, but mine is really bellow average
> 
> 
> I forgot if he or another guy mentioned, but you should sand them after bending , as the heat will "ruin" the finish
> My current project awaits some. Yet your bents are well made !
> The red was surprisingly not overdone , tamed by a lot of white.
> It makes me wonder why you don't use the flow rpm thing, to check flowspeed ~ when we know flowmeters are not accurate
> 
> Hearing for the first time that bents will do thaat much to flowrate
> Usually just the different type of parts, rads and blocks show a difference
> I was about to attempt a spiral too
> 
> Compared to 1T, maybe
> compared to GDM, well no
> 
> A "correct" GDM preset will run on the same VDIMM, with 2T mode
> soo the check "can you run 2T" is easy to check whereever half-strain on the PCB thanks to GDM, really hid issues
> and as it's barely slower, and allows you to run odd timings ~ it gives more control and peace of mind that the preset really is "ok"
> 1T is a whole new league and dual rank usually rarely can run it ~ nearly always needs SETUP timings that slow down align the signal correctly.
> Something is strange with dual rank and 1T
> 
> "Feature"
> 
> @ManniX-ITA please add Geekbench 3 for memory timings testing
> AES on Geekbench (both) can overshoot to over 40% increase, if it overboosts consistently


There is probably a bit more soc\iod voltage required if you run DR vs SR like I do  Maybe more if you use dual CCDs aswell?


----------



## Veii

Audioboxer said:


> The funny thing is even if this is action to try and quickly stop RMAs due to such a bug Ryzen Master completely bypasses the voltage limit and if you search for help OCing your CPU you will find this answer here, on Reddit and other websites.
> 
> Our complaints are mostly about effeciency, setting PBO limits in the BIOS and forgetting them. Having to remember to load Ryzen Master every Windows boot and apply your PBO settings just introduces an annoyance that wasn't once there. This is why we need communication to know if this is a bug or "feature".
> 
> I'm going to see if I can in any way replicate that 107xx score. Will turn off all c-states and experiment. Something caused it to happen and the scores of the other tests in that run line up with other runs.


The outcome is unsatisfactory.
1206b sounds interesting ~ i'll try to check if anything changed compared to 1206
Was still in the process to port it down, but am still afraid of these changes. Like actually afraid of the health on my mediocre but rare sample.
Potentially it can make it better ~ but it can very well have a tradeoff on something with FCLK.
Reading VDD18 behavior changed , 98% sure memory and RTT behavior changed again.

It's soo much work to be on even (fixes) ground with current updates and give current recommendations
Who knows what is broken again, i've never really seen a bugfree AGESA ~ maybe only ones that aren't even allowed to be supplied. AGESA 1.1.0.0 Patch B or earlier
SMU 56.30 and earlier. Oh and ones made by The Stilt 
Hence the Spectre patch fiasko & the dLDO enable toggle ~ there is nothing but problems.
They enabled it too early and the security exploits didn't help them, and made bad timings
Now the early pushed B2 samples do not help them either. They are delayed and back behind with patches and supply. AGESA 1205 took too long and still feels unfinished.
Soo B2 supply to the world was far earlier than they'd like to have it be.

It's on soo many sides and parts "complicated"
They don't need more pressure, but i wanted to comment that Vendors themself are bullied down.
Don't get too mad about them, the issue is AMD themself and their "for security" practices.
On core they surely mean it well, but the result and the moral having to bully back everyone after being a victim for 4-5 years and driven to nearly ruin
They need to throttle back, and stop with this.
I don't know how else to phrase it.
Acknowledge your flaws , and actively work with the OC scene. Not be against everyone that judges you and enforce your own rules to everybody. Or kick out people who can not follow. H*ck even design some kind of cult in discord with selected people that have to change their behavior viewpoint and betray their friends "for the codex , for security" . . . .

They need to better up and work with the OC scene. Like really !
They need to trust more ODMs and Vendors, that Vendors see the issues communicate with people that report the issues ~ but have close to zero ability to help users, as "there are protocols bla bla bla"
it's annoying . . .

A change needs to happen, the more tame way or the media pressure way
Soo i'll wait out what this 4-5 months worken on AGESA really does to our samples
Give it a try and if everything is lost, push everything out to tech-media, to hopefully like @Bloax mentioned ~ change their practices after not being is existence-issues the last 4-5 years & can start correctly with AM5 
Hopefully also with actual documentations about anything their "very flexible firmware designs" ~ offer








Which let's not forget it ~ every OC-Engineer had to dig them out by themself by only leak-shared documents. Zero support AMD throughout 3+ years. Bad move
Well also kind of well selected words by Mr. Hallock who supported at first this project (early CTR) but now has chosen the Vanguard Codex and can only talk with the words "of AMD"


----------



## rossi594

ManniX-ITA said:


> What could be limiting is VSOC.
> 
> Weird...
> I've always seen it scaling up solely based on silicon quality and CCD voltage.
> But it's also dependent on clock frequency that you can sustain.
> Maybe the AGESA 1.2.0.5 is really hurting your clocks.
> 
> At least looking at the other scores it should be higher.
> 
> I think @domdtxdissar is scoring much higher.
> Oh yeah he posted
> Didn't realize FCLK would have such a big influence.
> Guess we can take dom scores at 1900:3800 as a best reference.
> 
> Also raising VDD18 can also help. But it shouldn't be necessary.
> 
> Maybe it's like my HTML5 score which is always lower than anyone else.
> For you could be AES-XTS.
> 
> I'm using PBO 300/175/215 with Scalar 8x and Boost clock 100 MHz.


Hmm. I always so saw it all about throttleing. Maybe that's because I am not using Liquid metal / an offset mount / offset designed waterblock.

But I saw higher effective clocks with more conservative PBO Amp settings.


----------



## Audioboxer

Veii said:


> The outcome is unsatisfactory.
> 1206b sounds interesting ~ i'll try to check if anything changed compared to 1206
> Was still in the process to port it down, but am still afraid of these changes. Like actually afraid of the health on my mediocre but rare sample.
> Potentially it can make it better ~ but it can very well have a tradeoff on something with FCLK.
> Reading VDD18 behavior changed , 98% sure memory and RTT behavior changed again.
> 
> It's soo much work to be on even (fixes) ground with current updates and give current recommendations
> Who knows what is broken again, i've never really seen a bugfree AGESA ~ maybe only ones that aren't even allowed to be supplied. AGESA 1.1.0.0 Patch B or earlier
> SMU 56.30 and earlier. Oh and ones made by The Stilt
> Hence the Spectre patch fiasko & the dLDO enable toggle ~ there is nothing but problems.
> They enabled it too early and the security exploits didn't help them, and made bad timings
> Now the early pushed B2 samples do not help them either. They are delayed and back behind with patches and supply. AGESA 1205 took too long and still feels unfinished.
> Soo B2 supply to the world was far earlier than they'd like to have it be.
> 
> It's on soo many sides and parts "complicated"
> They don't need more pressure, but i wanted to comment that Vendors themself are bullied down.
> Don't get too mad about them, the issue is AMD themself and their "for security" practices.
> On core they surely mean it well, but the result and the moral having to bully back everyone after being a victim for 4-5 years and driven to nearly ruin
> They need to throttle back, and stop with this.
> I don't know how else to phrase it.
> Acknowledge your flaws , and actively work with the OC scene. Not be against everyone that judges you and enforce your own rules to everybody. Or kick out people who can not follow. H*ck even design some kind of cult in discord with selected people that have to change their behavior viewpoint and betray their friends "for the codex , for security" . . . .
> 
> They need to better up and work with the OC scene. Like really !
> They need to trust more ODMs and Vendors, that Vendors see the issues communicate with people that report the issues ~ but have close to zero ability to help users, as "there are protocols bla bla bla"
> it's annoying . . .
> 
> A change needs to happen, the more tame way or the media pressure way
> Soo i'll wait out what this 4-5 months worken on AGESA really does to our samples
> Give it a try and if everything is lost, push everything out to tech-media, to hopefully like @Bloax mentioned ~ change their practices after not being is existence-issues the last 4-5 years & can start correctly with AM5
> Hopefully also with actual documentations about anything their "very flexible firmware designs" ~ offer
> 
> 
> 
> 
> 
> 
> 
> 
> Which let's not forget it ~ every OC-Engineer had to dig them out by themself by only leak-shared documents. Zero support AMD throughout 3+ years. Bad move
> Well also kind of well selected words by Mr. Hallock who supported at first this project (early CTR) but now has chosen the Vanguard Codex and can only talk with the words "of AMD"





> They need to throttle back, and stop with this.
> I don't know how else to phrase it.


This is why I welcome Intel making moves to be more competitive in the market, even if their first outing this new gen is relying a bit on bruteforcing performance with high power draw.

Surely if AMD begin to worry their marketshare is at risk they'll rethink some of their actions towards a specific part of the community that are the ones who buy all the top end CPUs and spend time encouraging regular users to go with AMD...

Intel being quite price aggressive also ups the pressure.

As I said a few posts ago I don't really have much brand loyalty, I'm more someone who will end up going where a large chunk of the OCing community goes. I like to tinker with things and I get frustrated when the manufacturers make that difficult or are hostile towards it.


----------



## rossi594

Bix said:


> I think yours definitely fits the bill! Fingers crossed for my new 5900x which should arrive this week...


I knew I got really lucky on my SOC when I could reach 2033 flck easily on agesa 1.2.0.1 / 1.2.0.2 (at very low soc voltages). The last time I overclocked memory was with DDR2.
When I saw how high / consistant my effective clocks were without skalar. I knew I got lucky on my CCD.

I kind of build the system around the chip at that point, (returned the cheap mainboard and grabbed the vision-d), spent a lot on liquid cooling and babyied the chip.

I would be really curious what someone who really knows all the tricks like @Veii could get out of this chip / system.


----------



## Veii

Taraquin said:


> I give up, no matter what I try ram overheats when I set voltage above 1.5V and I need a bit over 1.5V to get below cl16 even at 2t, rcdrd 17, faw 20, rfc 300+. I need a better bin ram or another CPU-cooler if I want to get faster scores, but I`m satisfied with the performance I have and probably need at top bin B-die to run 4000cl15 or tighter at 1.5V or below.


28 ohm procODT at 2000 FCLK is still amazing. Nothing else how to put it 
But haven't you tried different RTT's on it ?
005 is strong, and if you really end up having A0 DIMM-PCB ~ higher voltage will cause you big issues, till you change your approach
* don't forget, i have one of the cheapest b-dies out there on weak A0 PCB. If i can do it you can too, with ease~

Usually A1 did move near 1.54ish volts before showing PCB failure issues
And A2 near 1.58-1.6v
A0 mostly capped out at 1.48 , where 1.52 was barely holding stable and 1.54 did result in a lost memory channel and nearly dead dimm.

Can it be that you are indeed at A0's ?
Or is it a missfortunate combination of low procODT and low voltage yet strong RTTs
~ soo failures are rather overcurrent = crash, and not overheat

Oh 005 is indeed very strong for SR, same as 031 is extremely strong for DR
We got other options, but i would suggest to try at the start 706, or even 607 with over 1.52v

Well i would also suggest, to maybe make a picture with straight-shining light , of the dimms
Soo traces reflect light and can be seen = PCB can be identified without removing the heatspreader


rossi594 said:


> I kind of build the system around the chip at that point, (returned the cheap mainboard and grabbed the vision-d), spent a lot on liquid cooling and babyied the chip.
> 
> I would be really curious what someone who really knows all the tricks like @Veii could get out of this chip / system.


You'll get there, just takes time - because you fight on 2 or 3 fronts. Memory on higher timings need first to be stable on 2:1 mode
~ before even attempting to fight against the package throttler and all other throttlers

You can do it !
Starting with 16-16-16 till 4200 is not a bad idea
Probably orient on the RamOC sheet and try things out.
Maybe even spend time to go up till 4600 MCLK on 2:1 - just so you know if procODT is correct and what voltages you need to run for low procODT requirements.
This will help you run higher FCLK later, as it's mostly IOD and SOC related.
But procODT and dimm powering has to be correct, soo it's very recommendable to just go desync like i did with 2100:5000, and figure out what really prevents you running higher MCLK
FCLK barely bothers with cLDO_VDDP and barely bothers with procODT
But procODT bothers a lot on memory, VDDG voltages and generally signal integrity ~ soo tick that box first before trying higher FCLK 

* Aida64 on 1 CCD has to show perfect half maximum bandwidth of the FCLK
Soo for 2033 FLCLK = 32533.3333~ MB/s or 32532MB/s
for 2067 FCLK = 33072 , or one down 33071 (minimal OS loss)
2100 then is 33600 MB/s, but in reality it's 33599 MB/s . . . and so on~
33598 is accceptable, but 33540ish , is for example not

You will instantly notice FCLK based throttle , if write bandwidth is messed up - independent if 2:1 or 1:1 mode


----------



## Taraquin

Veii said:


> 28 ohm procODT at 2000 FCLK is still amazing. Nothing else how to put it
> But haven't you tried different RTT's on it ?
> 005 is strong, and if you really end up having A0 DIMM-PCB ~ higher voltage will cause you big issues, till you change your approach
> * don't forget, i have one of the cheapest b-dies out there on weak A0 PCB. If i can do it you can too, with ease~
> 
> Usually A1 did move near 1.54ish volts before showing PCB failure issues
> And A2 near 1.58-1.6v
> A0 mostly capped out at 1.48 , where 1.52 was barely holding stable and 1.54 did result in a lost memory channel and nearly dead dimm.
> 
> Can it be that you are indeed at A0's ?
> Or is it a missfortunate combination of low procODT and low voltage yet strong RTTs
> ~ soo failures are rather overcurrent = crash, and not overheat
> 
> Oh 005 is indeed very strong for SR, same as 031 is extremely strong for DR
> We got other options, but i would suggest to try at the start 706, or even 607 with over 1.52v
> 
> Well i would also suggest, to maybe make a picture with straight-shining light , of the dimms
> Soo traces reflect light and can be seen = PCB can be identified without removing the heatspreader
> 
> You'll get there, just takes time - because you fight on 2 or 3 fronts. Memory on higher timings need first to be stable on 2:1 mode
> ~ before even attempting to fight against the package throttler and all other throttlers
> 
> You can do it !
> Starting with 16-16-16 till 4200 is not a bad idea
> Probably orient on the RamOC sheet and try things out.
> Maybe even spend time to go up till 4600 MCLK on 2:1 - just so you know if procODT is correct and what voltages you need to run for low procODT requirements.
> This will help you run higher FCLK later, as it's mostly IOD and SOC related.
> But procODT and dimm powering has to be correct, soo it's very recommendable to just go desync like i did with 2100:5000, and figure out what really prevents you running higher MCLK
> FCLK barely bothers with cLDO_VDDP and barely bothers with procODT
> But procODT bothers a lot on memory, VDDG voltages and generally signal integrity ~ soo tick that box first before trying higher FCLK
> 
> * Aida64 on 1 CCD has to show perfect half maximum bandwidth of the FCLK
> Soo for 2033 FLCLK = 32533.3333~ MB/s or 32532MB/s
> for 2067 FCLK = 33072 , or one down 33071 (minimal OS loss)
> 2100 then is 33600 MB/s, but in reality it's 33599 MB/s . . . and so on~
> 33598 is accceptable, but 33540ish , is for example not
> 
> You will instantly notice FCLK based throttle , if write bandwidth is messed up - independent if 2:1 or 1:1 mode


I can try different Rtts  I think ram is A2, Patriot viper 4400cl19, but not sure. Thanks for tip! Is it better to use higher ProcODT? Certain combos of Proc+Rtt I should try? I think it overheats since I can pass round one, then I get a few errors at round 2, then it gets more and more.


----------



## ManniX-ITA

Veii said:


> Overboost bug happens


My overboosting is completely gone after the AGESA 1.2.0.5 updates.
Of course the price I had to pay is a constant underboosting comparing to before...



rossi594 said:


> My Octo keeps crapping out from time to time and when it does so the fans ramp to 100%, so I just run my fans on static ~550rpm (can not hear them at that speed).


I know it's painful but you should RMA it.
Mine is not doing it (even if I don't use it regularly yet).
I've read about similar issues on the Aqua forum after a firmware upgrade...



Veii said:


> Don't get too mad about them, the issue is AMD themself and their "for security" practices.


It's an industry issue... NDAs have become the most important risks and showstoppers in any project.
20 years ago it was a matter of weeks.
10 years ago to sign an NDA between a major silicon provider and the company I work for it took 18 months.
Now it's just total craziness.
If I need to ship a platform with Widevine developers keys out to a partner I need them to sign a Loan agreement.
It takes weeks to amend the original agreement and put them in with their references, 4 company legal teams involved.
It's nuts and it's all like this everywhere!



PJVol said:


> aside from usb bug (which I experienced most of the time as "PC sometimes hangs until usb device is pulled out" on a certain usb ports) and then fixed 3000 series CPU scheduler issues, I can't see a single flaw anywhere in the platform, so calling such a big software engineer team incompetent looks reckless to say the least.


@Audioboxer could have been a little harsh in his judgment but I can perfectly understand his sentiment considering the customer's point of view.
You have way more deep technical knowledge and I don't really understand how you can be so overly optimistic. Looks way more reckless to me, sorry 

AMD has massive management, development and quality issues.
There's a reference benchmark which is Intel.

Zen2/Zen3 is the first and only x86 platform where a "default optimized" BIOS settings reset will not guarantee 99% that your system will work as expected and reliably.
This is a major and macroscopic flaw in the platform.
None of my Ryzen, 3600XT & 3800X & 5950X, did work reliably at default settings when I bought them.
Took months and I mostly wasn't and early adopter except the 5950X which I bought not so early.
It's so widespread that is just embarrassing. And every new AGESA is a new roll of dices; you could win or loose.

AMD is not a customer centric company, it's a dividend centric company.
Which is sadly pretty common for companies which went through deep financial crises.
But this is not an excuse to release unpolished products and then immediately diverge the resources to the next one.
Brand damaging becomes a secondary issue because, who cares, dividends are paid faster and that's what matters.

The development issues are obvious, AGESA releases are too slow and bug fixing, when it comes, it's late.
Yeah, my 5950X now doesn't overboost. How much did it take? Almost 18 months... Are we serious?

And of course quality; it's abysmal.
From anything which is Auto which is a Russian roulette, Overboosting, weak DDR4 training, etc
The list is too long to be considered normal.
There's a thing called Minimum Viable Product in this Agile world.
AMD's MVP is way too lax to be considered acceptable.
If you really want to introduce quickly a new product in the market to stay competitive then you must have the right speed of development to support it.
Right now they don't.

AMD's Engineering team is talented and innovative.
We wouldn't have these awesome processors otherwise and Intel would still be in its cryogenic sleep.
But I don't let my enthusiasm blindfold me, these problems are real.
If they don't start making an effort to fix it, Intel will crush them again.

They *may not be* incompetent but surely *they look* incompetent.

Of course, as always just my opinion, no offense 



domdtxdissar said:


> Gremlings everywhere


Wow 

Was finally able to break max cpu render 1000 fps with latest settings, not bad considering is all air cooling


----------



## Audioboxer

ManniX-ITA said:


> My overboosting is completely gone after the AGESA 1.2.0.5 updates.
> Of course the price I had to pay is a constant underboosting comparing to before...
> 
> 
> 
> I know it's painful but you should RMA it.
> Mine is not doing it (even if I don't use it regularly yet).
> I've read about similar issues on the Aqua forum after a firmware upgrade...
> 
> 
> 
> It's an industry issue... NDAs have become the most important risks and showstoppers in any project.
> 20 years ago it was a matter of weeks.
> 10 years ago to sign an NDA between a major silicon provider and the company I work for it took 18 months.
> Now it's just total craziness.
> If I need to ship a platform with Widevine developers keys out to a partner I need them to sign a Loan agreement.
> It takes weeks to amend the original agreement and put them in with their references, 4 company legal teams involved.
> It's nuts and it's all like this everywhere!
> 
> 
> 
> @Audioboxer could have been a little harsh in his judgment but I can perfectly understand his sentiment considering the customer's point of view.
> You have way more deep technical knowledge and I don't really understand how you can be so overly optimistic. Looks way more reckless to me, sorry
> 
> AMD has massive management, development and quality issues.
> There's a reference benchmark which is Intel.
> 
> Zen2/Zen3 is the first and only x86 platform where a "default optimized" BIOS settings reset will not guarantee 99% that your system will work as expected and reliably.
> This is a major and macroscopic flaw in the platform.
> None of my Ryzen, 3600XT & 3800X & 5950X, did work reliably at default settings when I bought them.
> Took months and I mostly wasn't and early adopter except the 5950X which I bought not so early.
> It's so widespread that is just embarrassing. And every new AGESA is a new roll of dices; you could win or loose.
> 
> AMD is not a customer centric company, it's a dividend centric company.
> Which is sadly pretty common for companies which went through deep financial crises.
> But this is not an excuse to release unpolished products and then immediately diverge the resources to the next one.
> Brand damaging becomes a secondary issue because, who cares, dividends are paid faster and that's what matters.
> 
> The development issues are obvious, AGESA releases are too slow and bug fixing, when it comes, it's late.
> Yeah, my 5950X now doesn't overboost. How much did it take? Almost 18 months... Are we serious?
> 
> And of course quality; it's abysmal.
> From anything which is Auto which is a Russian roulette, Overboosting, weak DDR4 training, etc
> The list is too long to be considered normal.
> There's a thing called Minimum Viable Product in this Agile world.
> AMD's MVP is way too lax to be considered acceptable.
> If you really want to introduce quickly a new product in the market to stay competitive then you must have the right speed of development to support it.
> Right now they don't.
> 
> AMD's Engineering team is talented and innovative.
> We wouldn't have these awesome processors otherwise and Intel would still be in its cryogenic sleep.
> But I don't let my enthusiasm blindfold me, these problems are real.
> If they don't start making an effort to fix it, Intel will crush them again.
> 
> They *may not be* incompetent but surely *they look* incompetent.
> 
> Of course, as always just my opinion, no offense
> 
> 
> 
> Wow
> 
> Was finally able to break max cpu render 1000 fps with latest settings, not bad considering is all air cooling
> 
> View attachment 2547945


Fair way of putting it, I do not have the technical knowledge to be "calmer" with my posts, though I dare say my posts are reasonably polite, just a little hyperbolic on calling a whole company incompetent. I did say AMD make great hardware, I stand by that. Though as an end user I do have to question what went on with some of the IMC controller stuff and/or mass spam of WHEA/USB issues just because a higher FCLK is selected. That's compounded by looking at the way Intel handles memory, but the blows traded in favour of AMD is the overall performance of AMD CPUs compared to Intel for years now.

That's because I'm not sure myself if these issues are on hardware design choices, or if it's the way the software/BIOS interacts with the hardware. From reading Veii posts it appears a lot of it is software inflicted and AMD doing quick and dirty "patches" which end up breaking other things and/or not being the optimal way to fix issues. The so called "security issue patches".

So that then causes annoyance for the end user because you're sitting on a great piece of hardware but it appears the "software development team" are not putting the the care and effort to reward the "hardware design team". I understand that is not really how black and white things are, but to an end user with only surface level understanding of the hardware, the brain thinks of it as "two teams", with one team letting the other down because the hardware is clearly powerful and its impressive the power draw/performance AMD has been cranking out in their CPUs for years compared to Intel.

Plus, when one AGESA has you seeing great performance/OCing and then the next gimps that for seemingly no reason, it's hard not to get upset. Especially when there is no changelog and you have no idea if AMD are making fundamental changes to how their hardware works or... it's a bug that is going to last 5~6 months before maybe being looked at.

You have to come to an OCing communuity for guesswork as to what the hell is going on. That's not good, as much as I love this community and the advice you get here. It should be coming straight from AMD if they're making fundamental changes to the way your hardware works and why.


----------



## ManniX-ITA

rossi594 said:


> But I saw higher effective clocks with more conservative PBO Amp settings.


Conservative PBO limits will let ST runs faster but will kill MT.
It's a fine balance, you need to decide what you care most.
Almost all 5950X runs ST much faster with EDC 170-180A but MT will be cut down by 10-20%.



Baio73 said:


> I don't see anything useful in the log, should I look elsewhere?


All you need is in this log 

If you check the links I've sent you there's some advice about the TM5 1usmus config errors.
You need to change settings following that advice and see if it's helping.



Baio73 said:


> These are the settings I'm testing (VRAM 1.49v):
> 
> 
> 
> And this is TM5's logt:
> 
> ========= TestMem5 Log File =========
> Customize: Default @1usmus_v3
> Start testing at 7:33, 464Mb x24
> Error in test #12 through 16 sec.
> Error in test #12 through 2m 50s.
> Error in test #2 through 2m 54s.
> Error in test #10 through 3m 7s.
> Error in test #11 through 4m 41s.
> Error in test #11 through 4m 45s.
> Error in test #6 through 4m 59s.
> Error in test #12 through 5m 5s.
> Error in test #12 through 5m 5s.
> Error in test #2 through 5m 16s.
> Error in test #2 through 5m 22s.
> Error in test #13 through 6m 11s.
> Error in test #9 through 6m 18s.
> Error in test #8 through 6m 31s.
> Testing is completed through 7m 3s,
> detected 347 error(s).


The DIMM is crashing (#13) and starving voltage (#6).
Usually #2 and #10 are a signal tRCDRD is too low for your VDIMM.
Overall seems also your termination settings are wrong.

ProcODT is definitely too high, set it to 36.9.
Try DrvStr 40-20-24-24 or 40-20-24-30

Set tRCDRD to 16 and RW to 8.

VDDP voltage is way too high, set it to 900mV.

Test with this VDIMM but you may need to raise it +0.1V.
Guess something like this should be able to work with 1.52V or less.

I would also take a step back and set RP/RAS/RC to 16/32/48.
If you can pass this way CL14/CWL14.
And then if pass go back to RP/RAS/RC to 14/28/42.

Then you can start lowering tRCDRD to 15 and 14 to see if it holds.
Last you can fix the tRFC with something appropriate with the VDIMM.
Depends on where you get with VDIMM.


----------



## Baio73

ManniX-ITA said:


> Conservative PBO limits will let ST runs faster but will kill MT.
> It's a fine balance, you need to decide what you care most.
> Almost all 5950X runs ST much faster with EDC 170-180A but MT will be cut down by 10-20%.
> 
> 
> 
> All you need is in this log
> 
> If you check the links I've sent you there's some advice about the TM5 1usmus config errors.
> You need to change settings following that advice and see if it's helping.
> 
> 
> 
> The DIMM is crashing (#13) and starving voltage (#6).
> Usually #2 and #10 are a signal tRCDRD is too low for your VDIMM.
> Overall seems also your termination settings are wrong.
> 
> ProcODT is definitely too high, set it to 36.9.
> Try DrvStr 40-20-24-24 or 40-20-24-30
> 
> Set tRCDRD to 16 and RW to 8.
> 
> VDDP voltage is way too high, set it to 900mV.
> 
> Test with this VDIMM but you may need to raise it +0.1V.
> Guess something like this should be able to work with 1.52V or less.
> 
> I would also take a step back and set RP/RAS/RC to 16/32/48.
> If you can pass this way CL14/CWL14.
> And then if pass go back to RP/RAS/RC to 14/28/42.
> 
> Then you can start lowering tRCDRD to 15 and 14 to see if it holds.
> Last you can fix the tRFC with something appropriate with the VDIMM.
> Depends on where you get with VDIMM.


Just one question before I start testing... I used to test with Karhu RAM Test and I'm not so used to TM5... how many cycles must I run?
And where can I find a table with the error codes? I searched the web but found nothing...

Baio


----------



## domdtxdissar

ManniX-ITA said:


> Wow
> 
> Was finally able to break max cpu render 1000 fps with latest settings, not bad considering is all air cooling
> 
> View attachment 2547945


Very nice 
This is my legit run with no dx trick


----------



## Audioboxer

Baio73 said:


> Just one question before I start testing... I used to test with Karhu RAM Test and I'm not so used to TM5... how many cycles must I run?
> And where can I find a table with the error codes? I searched the web but found nothing...
> 
> Baio


25 cycles is a good idea, some errors with power down/tRFC/voltage can come between 20~25 cycles of 1usmusv3.

Veii's error table is here tRFC mini Just keep in mind it's a best guess in some situations, not meant to be taken as perfect.


----------



## rossi594

Veii said:


> You will instantly notice FCLK based throttle , if write bandwidth is messed up - independent if 2:1 or 1:1 mode


Thank you so much for the post it's increadibly helpful.

Does FCLK based throttle mean I need to adjust my voltages (vsoc, vddg iod, vddg ccd, vdd18, vddp)?
Or does it urcur because your soc is not so stable on that speed (for example fclk hole or limit of the soc)?



Taraquin said:


> I can try different Rtts  I think ram is A2, Patriot viper 4400cl19, but not sure.


Thanks, very kind. Does it make a big difference what board I am running and that I am 4x8gb?



ManniX-ITA said:


> I know it's painful but you should RMA it.
> Mine is not doing it (even if I don't use it regularly yet).
> I've read about similar issues on the Aqua forum after a firmware upgrade...


I think I will do that after my exams ... so bad that I put it in case that opens from the side that i used to zip tie it the Mo-Ra tubes. One of the Aquacomputer Reps told me on Hardwareluxx that they never had that issue, so I thought it was maybe down to the XLR extension I use.

It's nice to know this is more common than I thought and can be fixed by RMAing it, let's hope they let me RMA it. I don't think this issue is easy to reproduce.



ManniX-ITA said:


> Conservative PBO limits will let ST runs faster but will kill MT.
> It's a fine balance, you need to decide what you care most.


That was no true for me. Both effective single and multi frequencies were throtteling with higher limits and hurting my performance. (EDC seemed to make the biggest impact from my observations).

I assume you would call my final limits conservative (they were under the normal single ccd recommendations).

I will buy an TechN waterblock today and Liquid Metal the CPU (after my exams roughly week 1 of april) just to see if that helps.


----------



## ManniX-ITA

Baio73 said:


> Just one question before I start testing... I used to test with Karhu RAM Test and I'm not so used to TM5... how many cycles must I run?
> And where can I find a table with the error codes? I searched the web but found nothing...


12 for quick testing, 25 cycles to be sure, final 50 cycles.
@Audioboxer is using 32GB DR, you 16GB SR so double 

Look at my answer to you:








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


guys is it logical to use lower tRCDWR values like 8,9,10 instead of 16-18 ? im using a dual rank micron e-die.




www.overclock.net







ManniX-ITA said:


> Take a look at the Ryzen Calculator, *there are updated TM5 error messages:*
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Ryzen Google Calculator!
> 
> 
> Change Note 0.7b 10-8-2021,- v0.7b.6c TM5 -,#ADD anta777_ABSOLUT 7-13-2021,- v0.7b.6b Layout -,#CHANGE some position and color TM5 -,#ADD some ex Voltage -,#CHANGE "VDDG CCD" multiplier min value to 0 5-1-2021,- v0.7b.6a tRFC -,#FIX "N/A" Error, when shoud show "tRTP_ERROR #2" 4-30-2021,- v0.7b.5c
> 
> 
> 
> 
> docs.google.com





rossi594 said:


> It's nice to know this is more common than I thought and can be fixed by RMAing it, let's hope they let me RMA it. I don't think this issue is easy to reproduce.


My advice is to use your phone or a webcam to record until it happens. With the video the RMA is guaranteed.


----------



## Taraquin

Veii said:


> 28 ohm procODT at 2000 FCLK is still amazing. Nothing else how to put it
> But haven't you tried different RTT's on it ?
> 005 is strong, and if you really end up having A0 DIMM-PCB ~ higher voltage will cause you big issues, till you change your approach
> * don't forget, i have one of the cheapest b-dies out there on weak A0 PCB. If i can do it you can too, with ease~
> 
> Usually A1 did move near 1.54ish volts before showing PCB failure issues
> And A2 near 1.58-1.6v
> A0 mostly capped out at 1.48 , where 1.52 was barely holding stable and 1.54 did result in a lost memory channel and nearly dead dimm.
> 
> Can it be that you are indeed at A0's ?
> Or is it a missfortunate combination of low procODT and low voltage yet strong RTTs
> ~ soo failures are rather overcurrent = crash, and not overheat
> 
> Oh 005 is indeed very strong for SR, same as 031 is extremely strong for DR
> We got other options, but i would suggest to try at the start 706, or even 607 with over 1.52v
> 
> Well i would also suggest, to maybe make a picture with straight-shining light , of the dimms
> Soo traces reflect light and can be seen = PCB can be identified without removing the heatspreader
> 
> You'll get there, just takes time - because you fight on 2 or 3 fronts. Memory on higher timings need first to be stable on 2:1 mode
> ~ before even attempting to fight against the package throttler and all other throttlers
> 
> You can do it !
> Starting with 16-16-16 till 4200 is not a bad idea
> Probably orient on the RamOC sheet and try things out.
> Maybe even spend time to go up till 4600 MCLK on 2:1 - just so you know if procODT is correct and what voltages you need to run for low procODT requirements.
> This will help you run higher FCLK later, as it's mostly IOD and SOC related.
> But procODT and dimm powering has to be correct, soo it's very recommendable to just go desync like i did with 2100:5000, and figure out what really prevents you running higher MCLK
> FCLK barely bothers with cLDO_VDDP and barely bothers with procODT
> But procODT bothers a lot on memory, VDDG voltages and generally signal integrity ~ soo tick that box first before trying higher FCLK
> 
> * Aida64 on 1 CCD has to show perfect half maximum bandwidth of the FCLK
> Soo for 2033 FLCLK = 32533.3333~ MB/s or 32532MB/s
> for 2067 FCLK = 33072 , or one down 33071 (minimal OS loss)
> 2100 then is 33600 MB/s, but in reality it's 33599 MB/s . . . and so on~
> 33598 is accceptable, but 33540ish , is for example not
> 
> You will instantly notice FCLK based throttle , if write bandwidth is messed up - independent if 2:1 or 1:1 mode


Okay, tried 706 and 32 Proc, even 15-16-15 starts spewing errors after a few minutes of TM5 and errorcount increases as time goes so that looks like overheat. I could run rfc, faw, wtr etc a fair bit slower, but that reduces perf so my net gain will be very limited, seems I'm stuck at 4000cl16 1t, but I'm satisfied with performance  Good CPU and IMC, average bin ram. Good bin ram costs too much, not worth it for me


----------



## Taraquin

rossi594 said:


> Thank you so much for the post it's increadibly helpful.
> 
> Does FCLK based throttle mean I need to adjust my voltages (vsoc, vddg iod, vddg ccd, vdd18, vddp)?
> Or does it urcur because your soc is not so stable on that speed (for example fclk hole or limit of the soc)?
> 
> 
> Thanks, very kind. Does it make a big difference what board I am running and that I am 4x8gb?
> 
> 
> I think I will do that after my exams ... so bad that I put it in case that opens from the side that i used to zip tie it the Mo-Ra tubes. One of the Aquacomputer Reps told me on Hardwareluxx that they never had that issue, so I thought it was maybe down to the XLR extension I use.
> 
> It's nice to know this is more common than I thought and can be fixed by RMAing it, let's hope they let me RMA it. I don't think this issue is easy to reproduce.
> 
> 
> That was no true for me. Both effective single and multi frequencies were throtteling with higher limits and hurting my performance. (EDC seemed to make the biggest impact from my observations).
> 
> I assume you would call my final limits conservative (they were under the normal single ccd recommendations).
> 
> I will buy an TechN waterblock today and Liquid Metal the CPU (after my exams roughly week 1 of april) just to see if that helps.


My board only has 2 dimm slots, that makes it easier running 1900+ fclk, using 4 sticks is harder than 2, but you have dual rank, I don't so that makes up for a bit if it


----------



## ManniX-ITA

Got the insanely expensive Copper HS delivery


----------



## Audioboxer

ManniX-ITA said:


> Got the insanely expensive Copper HS delivery
> 
> View attachment 2547963


Damn that looks nice.

Think I'll just stick to my $37 Bykski block though lol.

Going to be aircooling or watercooling these?


----------



## ManniX-ITA

Audioboxer said:


> Damn that looks nice.
> 
> Think I'll just stick to my $37 Bykski block though lol.
> 
> Going to be aircooling or watercooling these?


At first air then water.
I've got an HWInfo CSV logging with 5 minutes TM5 heating up and 15 minutes cooling down to compare.
Not sure on air will be any difference but curious.

Than I'll move to water but I have to check if my Alphacool block fits with the holes... hope so


----------



## rossi594

ManniX-ITA said:


> Got the insanely expensive Copper HS delivery
> 
> View attachment 2547963


Sexy af, who even makes those. Did you order them from a machine shop? Are the top holes threaded or self tapping? Self tapping could be bad if you remount them a few times.


----------



## ManniX-ITA

rossi594 said:


> Sexy af, who even makes those. Did you order them from a machine shop?


From Bartxstore:









Custom RAM copper heatsinks for DDR5 / DDR4 - Bartxstore


Custom made copper RAM heatsinks for memory extreme overclocking using dry ice or LN2. Designed for DDR4 and DDR5 memory




bartxstore.com


----------



## rossi594

ManniX-ITA said:


> At first air then water.
> I've got an HWInfo CSV logging with 5 minutes TM5 heating up and 15 minutes cooling down to compare.
> Not sure on air will be any difference but curious.
> 
> Than I'll move to water but I have to check if my Alphacool block fits with the holes... hope so


The Alphacool hole spacing is the same as they EK and Bykski as far as i know.


----------



## Audioboxer

ManniX-ITA said:


> At first air then water.
> I've got an HWInfo CSV logging with 5 minutes TM5 heating up and 15 minutes cooling down to compare.
> Not sure on air will be any difference but curious.
> 
> Than I'll move to water but I have to check if my Alphacool block fits with the holes... hope so


Living the dream, add it to a watercooled build using copper pipe.



> For double sided DDR4 – thermal paste on IC from both sideds


Interesting, 0.5mm was OK in my Bykski block both sides for DR. Wonder if these are thicker?

Or is it just thermal paste would be better for copper than pads?


----------



## rossi594

ManniX-ITA said:


> From Bartxstore:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Custom RAM copper heatsinks for DDR5 / DDR4 - Bartxstore
> 
> 
> Custom made copper RAM heatsinks for memory extreme overclocking using dry ice or LN2. Designed for DDR4 and DDR5 memory
> 
> 
> 
> 
> bartxstore.com


Thanks I think I will make my own, if I ever want that =)


----------



## ManniX-ITA

Audioboxer said:


> Living the dream, add it to a watercooled build using copper pipe.


 Ah I love Copper but pipes no, I have a life


----------



## ManniX-ITA

rossi594 said:


> Thanks I think I will make my own, if I ever want that =)


For sure less expensive... I buy 4 times more Copper for 20 €


----------



## Audioboxer

ManniX-ITA said:


> For sure less expensive... I buy 4 times more Copper for 20 €











Custom RAM copper heatsinks for B-Die based RAM - Bartxstore


Custom made copper RAM heatsinks for memory extreme overclocking using dry ice or LN2. Designed for DDR4 chips - Samsung B-Die.




bartxstore.com





10 euros cheaper for this, but I presume you bought the DDR5 listed ones for future compatibility? Wonder what's different between the ones you got and these in terms of construction?

They look the exact same in the pictures.


----------



## ManniX-ITA

Audioboxer said:


> Or is it just thermal paste would be better for copper than pads?


No it's just the 0 tolerance.
That's why it's specifying Samsung B-die.
Other ICs could be taller and the two sides wouldn't close properly and not touch.
But what else DDR4 would you mount this stuff on? 
Paste is better in any case due to the layer thinness.



Audioboxer said:


> 10 euros cheaper for this, but I presume you bought the DDR5 listed ones for future compatibility? Wonder what's different between the ones you got and these in terms of construction?


Yes indeed.
The difference is that window inward in the middle to account for the DDR5 PMIC.

I love that all the screws have bolts.
Which is obvious as copper is very soft and threads can be easily destroyed.
But is also the usual weak point of cheap heatsinks (like the Alphacool).

Whatever you do, you can't damage it.
Just replace the bolt.

And screws and bolts all look very high quality stainless steel, not cheap stuff.


----------



## Veii

rossi594 said:


> Does FCLK based throttle mean I need to adjust my voltages (vsoc, vddg iod, vddg ccd, vdd18, vddp)?


Yes VDDG IOD, SOC, VDD18 
Low procODT is always preferred, but it will mess with your CO's and so will also VDDG CCD mess with your CO's
I think you'll understand what i mean, after you torture it with y-cruncher and OCCT (after getting an Aida64 report that's reasonable)


----------



## rossi594

ManniX-ITA said:


> No it's just the 0 tolerance.
> That's why it's specifying Samsung B-die.
> Other ICs could be taller and the two sides wouldn't close properly and not touch.
> But what else DDR4 would you mount this stuff on?
> Paste is better in any case due to the layer thinness.
> 
> 
> 
> Yes indeed.
> The difference is that window inward in the middle to account for the DDR5 PMIC.
> 
> I love that all the screws have bolts.
> Which is obvious as copper is very soft and threads can be easily destroyed.
> But is also the usual weak point of cheap heatsinks (like the Alphacool).
> 
> Whatever you do, you can't damage it.
> Just replace the bolt.
> 
> And screws and bolts all look very high quality stainless steel, not cheap stuff.


Ah you mean nuts not bolts. Bolts are just screws without tips (metal screws).... xD now i get it =D


----------



## ManniX-ITA

rossi594 said:


> Ah you mean nuts not bolts. Bolts are just screws without tips (metal screws).... xD now i get it =D


Oh yes sorry 
Not native English, I'm listening in conference calls since hours...


----------



## Audioboxer

Given all we were discussing in the last 24 hours, here is more fuel for the fire






[DRIVERS] AMD Chipset/RAID (3xx/4xx/5xx/6xx/TRX40)


Hi everyone, - AMD Chipset Drivers : Package : 4.11.15.342 WHQL Download : Link - AMD RAID Drivers (Drivers Only) : Drivers - NVMe - 6xx : 9.3.2.158 WHQL



rog.asus.com





ASUS employees have now removed Chipset drivers 3.11.17.521 WHQL [17/11/2021] for download. Evidence that post once had them






[DRIVERS] AMD Chipset/RAID (3xx/4xx/5xx/6xx/TRX40) - Page 6


Hi everyone, - AMD Chipset Drivers : Package : 4.11.15.342 WHQL Download : Link - AMD RAID Drivers (Drivers Only) : Drivers - NVMe - 6xx : 9.3.2.158 WHQL



rog.asus.com













File on MEGA







mega.nz





MEGA link is dead as well.

Now they are listing the same 3.10.22.706 that MSI have put on their website.

So for over a month ASUS mobo users will have been downloading and installing 3.11.17.521, and they're posted over the web, yet ASUS have quietly removed the link from their own forum.

Why? Who knows. Either broken or AMD clapped back at ASUS for releasing them... The ****show continues.

Last time I checked the AMD website still isn't even listing 3.10.22.706.


----------



## ManniX-ITA

Audioboxer said:


> Why? Who knows. Either broken or AMD clapped back at ASUS for releasing them...


Because it's bugged 
I'm surprised it took so much time for them to remove it.
Got a lot of issues and BSODs with that version.


----------



## Audioboxer

ManniX-ITA said:


> Because it's bugged
> I'm surprised it took so much time for them to remove it.
> Got a lot of issues and BSODs with that version.


Yeah Veii told me to avoid it when I was having some TM5 timeout issues.

There were two 3.11 releases though, one part of the package was forgotten to be included, then 3.11.17.521 that ASUS had up for quite a while.


----------



## ManniX-ITA

Audioboxer said:


> Yeah Veii told me to avoid it when I was having some TM5 timeout issues.


Yeah he told me as well when I was wondering about these random issues and indeed he was right


----------



## Luggage

ManniX-ITA said:


> Got the insanely expensive Copper HS delivery
> 
> View attachment 2547963


 Very sexy 


Only ones more sexy that I’ve seen are @Carillo s super cool blocks *Official* Intel DDR5 OC and 24/7 daily Memory Stability...


----------



## Asutz

There was a 3.12.08.456 Driver Set too, had no issues with it but missing Changelogs as usual just sucks.First time had wdt ( watch dogs timer ) driver install in the package.What it does? no infos whatsoever.

Not 100% sure but MoKiChU isnt an Asus Employer, just a reguler guy helping with drivers because asus itself lacking with support.


----------



## Audioboxer

Asutz said:


> There was a 3.12.08.456 Driver Set too, had no issues with it but missing Changelogs as usual just sucks.First time had wdt ( watch dogs timer ) driver install in the package.What it does? no infos whatsoever.
> 
> Not 100% sure but MoKiChU isnt an Asus Employer, just a reguler guy helping with drivers because asus itself lacking with support.


Thanks for pointing that out, don't want anyone sending them crap.

This mess is on AMD anyway, not the manufacturers.


----------



## lafonte

Asutz said:


> What it does? no infos whatsoever.


It's an hardware timer used by the kernel to try to recover from a system fault. In desktop is not really necessary and it can also slightly reduce performance.


----------



## Baio73

Audioboxer said:


> Thanks for pointing that out, don't want anyone sending them crap.
> 
> This mess is on AMD anyway, not the manufacturers.


Installed v3.12.08.456 a couple of days ago, it gave me 4-5 times an error but the installation was finalized. So far no issues.

Very strange things are happening around chipset drivers, never saw such a situation in AMD history...

Baio


----------



## Asutz

Baio73 said:


> Installed v3.12.08.456 a couple of days ago, it gave me 4-5 times an error but the installation was finalized. So far no issues.
> 
> Very strange things are happening around chipset drivers, never saw such a situation in AMD history...
> 
> Baio


On Windows 11 Insider 22543 at least here on my system, no difference at all, doesnt matter if i install them, something less to stress about, hope its getting better with am5 but not confident, whole am4 time was just to finicky for me, started with zen1 on b450, r3 1200 instability at the beginning, switched over to 2700x but that msi b450 gpc couldnt handle it well, switch to x470, at least 5600x is running without major instabilities, sound still occasional crap with crackling noises or vrm sounds, idk.internal soundcard helped at least, bluetooth headset usage not ideal.didnt cound, maybe 100 or more "load defaults" situation and every reset was different and special, not even performance or either stabilitywas the same,across all agesas and still not finished, maybe before next zen release.

being an early adopter for half a year is one thing but for me or my opinion using am4 it felt like being an early adopter for the whole time.is the blue side less stressful?


----------



## Luggage

Asutz said:


> On Windows 11 Insider 22543 at least here on my system, no difference at all, doesnt matter if i install them, something less to stress about, hope its getting better with am5 but not confident, whole am4 time was just to finicky for me, started with zen1 on b450, r3 1200 instability at the beginning, switched over to 2700x but that msi b450 gpc couldnt handle it well, switch to x470, at least 5600x is running without major instabilities, sound still occasional crap with crackling noises or vrm sounds, idk.internal soundcard helped at least, bluetooth headset usage not ideal.didnt cound, maybe 100 or more "load defaults" situation and every reset was different and special, not even performance or either stabilitywas the same,across all agesas and still not finished, maybe before next zen release.
> 
> being an early adopter for half a year is one thing but for me or my opinion using am4 it felt like being an early adopter for the whole time.is the blue side less stressful?


I’ve been reading the 12th gen threads and there seems to be some early adapter tax on the blue side as well now that they finally moved on from 14+++, at least for OC minded people.


----------



## Bloax

Asutz said:


> being an early adopter for half a year is one thing but for me or my opinion using am4 it felt like being an early adopter for the whole time.is the blue side less stressful?


Besides memory overclocking being _*very funny*_ at times, and most Features™ being borderline useless besides Benchmark dick-measuring* or outright broken, it has been very nice actually.

*: There are "adaptive frequency" multipliers for X Core Workloads, but a game like Overwatch that would be making heavy use of 1-3 core boosting on Matisse/Vermeer, is 100% stuck in 8 Core Workload land.
So it's certainly useful for dick-measuring contests, but not actually useful for vidya unless it's one of them funny *actually single-threaded* indie programs or software designed to run in 2000-2005


The most useful ADL feature is per-core HT control, as you could use it to disable HT on your hottest core(s) and maintain higher overall clocks.
This feature is also completely broken right now, and if you don't boot-loop your system by using anything but Per-Core frequency multipliers, performance in vidya still tanks to Ryzen 3600 levels for _some reason_.

Besides that, THERMAL VELOCITY BOOST RATIO CLIPPINGS (ooh aah), or "manual thermal throttling control" as it is really called, is by far the most useful feature as not every task runs the same static allcore frequency.


_The best feature_ in my eyes, is the lack of having to reboot 50+ times to bruteforce SOC/IOD/CCD voltage combinations into that one godforsaken lottery ticket that stops audio popping ahhhhhhhhhhhhhhhh help


----------



## Luggage

Bloax said:


> Besides memory overclocking being _*very funny*_ at times, and most Features™ being borderline useless besides Benchmark dick-measuring* or outright broken, it has been very nice actually.
> 
> *: There are "adaptive frequency" multipliers for X Core Workloads, but a game like Overwatch that would be making heavy use of 1-3 core boosting on Matisse/Vermeer, is 100% stuck in 8 Core Workload land.
> So it's certainly useful for dick-measuring contests, but not actually useful for vidya unless it's one of them funny *actually single-threaded* indie programs or software designed to run in 2000-2005
> 
> 
> The most useful ADL feature is per-core HT control, as you could use it to disable HT on your hottest core(s) and maintain higher overall clocks.
> This feature is also completely broken right now, and if you don't boot-loop your system by using anything but Per-Core frequency multipliers, performance in vidya still tanks to Ryzen 3600 levels for _some reason_.
> 
> Besides that, THERMAL VELOCITY BOOST RATIO CLIPPINGS (ooh aah), or "manual thermal throttling control" as it is really called, is by far the most useful feature as not every task runs the same static allcore frequency.
> 
> 
> _The best feature_ in my eyes, is the lack of having to reboot 50+ times to bruteforce SOC/IOD/CCD voltage combinations into that one godforsaken lottery ticket that stops audio popping ahhhhhhhhhhhhhhhh help


TVB getting closer and closer to AMD/GPU boost behavior by the generation


----------



## ManniX-ITA

Well the Copper heatsinks are definitely a tad better, around 56c max temperature in TM5 instead of 59c.
The DIMMs gets over 50c in about 9 minutes while before it was 5 minutes.
Heating them with the GPU didn't show any improvement.
Guess I'll have to wait with water but it's already a nice start


----------



## Audioboxer

ManniX-ITA said:


> Well the Copper heatsinks are definitely a tad better, around 56c max temperature in TM5 instead of 59c.
> The DIMMs gets over 50c in about 9 minutes while before it was 5 minutes.
> Heating them with the GPU didn't show any improvement.
> Guess I'll have to wait with water but it's already a nice start


Heat transfer was always going to be your next main issue.

Watercooling is when they'll really shine.

I guess watercooling memory was always a meme, but with B-die it's genuinely advantageous. Especially on the tRFC front. Or if your bin is going to want 1.6v+ to do what some of the other bins might manage a bit lower.


----------



## PJVol

ManniX-ITA said:


> I don't really understand how you can be so overly optimistic. Looks way more reckless to me, sorry
> 
> AMD has massive management, development and quality issues.


I don't think I am. We were talking about software developement, aren't we?
But l'd separate different problems, at least to the extent how i see things, the one which is purely on amd side and the other arising from some co-developement issues with mb vendors, and from the choice of VRM model, made at the design stage.
Since it's not FIVR, there *has to be* issues. And I see it as huge variance in the way how different mb vendors' vrm design functioning. Why i even talk about it, - because i think it's very important part for the reliable cpu operating.

So they should be considered as a management ones (imho).

As soon as they move to FIVR, i think half of the problems will be solved. I've heard they gonna do this in zen5 or even earlier (zen4). Should have another look to am5 specs though.



ManniX-ITA said:


> If I need to ship a platform with Widevine developers keys out to a partner I need them to sign a Loan agreement.


Lol, we've tried to come to agreement with google to get keyboxes for the amlogic bootloader, to have a L1 level certification but to no avail, the communication was abruptly canceled by their side, as soon as they knew what devices they have to deal with 

PS:


ManniX-ITA said:


> Zen2/Zen3 is the first and only x86 platform where a "default optimized" BIOS settings reset will not guarantee 99% that your system will work as expected and reliably.


Again, if it was the case for every platform, then it surely would be unacceptable, but I went through the 1600, 3600x, 5600x and 5700g, (the last two are still working) on asrock x370 taichi, b550 extreme4 and MSI b450m mortar, which was tested with all CPUs, except 1600. And i can assure you, there were never the case when loading default settings caused any problem for me.

With that being said i have to ask, is your bad experience with this really the result of purely amd's fault?

Of course, in no way all of the above said imply I'm fine with everything else, and there are many things I personally don't like, for example almost non-existent low level documentation aside from PRRs, i.e. BKDG (for the reasons unknown for me), or their recent changes in AGESA, though still have hope they won't let the current state of things to be validated for the next release version.


----------



## Taraquin

Did some further testing of ProcODT and VDD18 at 2000fclk, avg of 3 runs:

ProcODT 32 VDD18 1.8V:
Aida 51.8-52ns L3 10.7ns
Dram calc test 98sec
Linpack 3gb 263Gflops
SOTTR CPU game avg 264

ProcODT 28 VDD18 1.8V:
Aida 52-52.2ns 10.9ns
Dram calc test 98.5sec
Linpack 3gb 261Gflops
SOTTR CPU game avg 262

ProcODT 28 VDD18 1.88V:
Aida 51.7-51.9ns 10.8ns
Dram calc test 97.5sec
Linpack 3gb 265Gflops
SOTTR CPU game avg 267

I also tested ProcODT 32 and VDD18 1.88V, but got same results as VDD18 1.8V. VDD18 at 1.84V or 1.92V gave slightly lower perf than 1.88V. Running 1900fclk I saw no benefit from raising VDD18.

So ProcODT actually slightly affects performance and 32 is superior to 28, but upping VDD18 by 80mv makes 28 faster than 32, but for 32 I saw no benefit of raising VDD18.

The difference is not huge, but it is interesting to see up to 2% better perf by upping VDD18 by 80mv at ProcODT 28. I recommend those of you running above 1900fclk to check this out, might be a 1-2% to gain


----------



## umea

ManniX-ITA said:


> Well the Copper heatsinks are definitely a tad better, around 56c max temperature in TM5 instead of 59c.
> The DIMMs gets over 50c in about 9 minutes while before it was 5 minutes.
> Heating them with the GPU didn't show any improvement.
> Guess I'll have to wait with water but it's already a nice start


Have you tested bare dimms?
I tried copper heatsinks as well, but temps were 3-4 degrees higher than running a fan on the bare dimms. This may also be because of it being an ITX board though, and being in an ITX case means there's a lot less room to do funky cooling setups.

I still have 2 sets of copper heatsinks sitting around unused sadly.

If anyone is in NA and would like to purchase them shoot me a DM. They're Bartxstore's heatsinks for DR B-Die (SR work as well)


----------



## RARAYYYY

Hi, can anyone suggest where I can improve?


----------



## kim nk

RARAYYYY said:


> Hi, can anyone suggest where I can improve?
> 
> View attachment 2548030












Twtrs 3~4, gdm-disable 1T 2T TPHYRDL 26 Use REAL 1T TPHYRDL 28 If you use TPHYRDL 28 If you use this, use 2T (board performance problem) Trdwr This is a solo 7 and try booting if it is not booted. Try to reduce the twrd to 3 to 1 by catching the trdwr boot minimum first, and upload it from the clkdrvstr tm5 1 cycle to 30 40 60 when an error occurs. (When the voltage is sufficient) tm5 is often in two categories: one cycle to three cycle error trcdrd yield deficit or memory voltage deficit. Procodt This is better if it is lower, but please hold the procodt value that is maintained at less than 0.2 ns in latency without changing the aida64 write speed. The rest of the cldo vddp, vddg iod ccd, especially cldo vddp, please give me this as a low-water value. The rest of the iod is about 1.05, but you can tighten to 1.0, give ccd 0.95, and go down to 0.9. Soc is not llc 5 level now, but 1.0875v due to descent. It's just enough in 3733, so it looks fine.


----------



## ManniX-ITA

PJVol said:


> As soon as they move to FIVR, i think half of the problems will be solved. I've heard they gonna do this in zen5 or even earlier (zen4). Should have another look to am5 specs though.


Let's hope... 
Yes we were talking about software but also about the AM4 platform & Zen 2/3 (it's hard to split) with a special focus on what we see, the AGESA.



PJVol said:


> Lol, we've tried to come to agreement with google to get keyboxes for the amlogic bootloader, to have a L1 level certification but to no avail, the communication was abruptly canceled by their side, as soon as they knew what devices they have to deal with


Oh you need to be really Zen to work with Google.
They always want dates and they never delivery in time...
Half employees are brilliant, the other half looks lobotomized 

What do you mean with what devices they have to deal with? Cause it's AMLogic? Or the use case?
They are pushing AMLogic like hell cause they hate the guts with Broadcom.
Maybe they didn't trust the security of the BSL.
Without a CAS vendor you need a strong OEM to take responsibility.



PJVol said:


> And i can assure you, there were never the case when loading default settings caused any problem for me.


I'm not speaking particularly for myself. Yes I went through lots of issues.
It's about the massive amount of people that had the same issue here on OCN and elsewhere.
Really too many, probably 10-30% of the total. Incredibly common.
If you compare with Intel, where a similar issue is very rare and probably impacting a 1-2%, it's a major issue.


----------



## ManniX-ITA

umea said:


> Have you tested bare dimms?


No, I meant to compare Aluminum with Copper.
Not really interested in bare DIMMs, I'll put them under water


----------



## ManniX-ITA

Taraquin said:


> I recommend those of you running above 1900fclk to check this out


Where I see the GFlops difference on my 5950X is at FCLK 1900.
But with Static OC, can't see it with PBO.
With PBO still you can see the latency difference in AIDA.


----------



## Taraquin

ManniX-ITA said:


> Where I see the GFlops difference on my 5950X is at FCLK 1900.
> But with Static OC, can't see it with PBO.
> With PBO still you can see the latency difference in AIDA.


Got about same (264-266Gflops) with pbo at 1900 and 2000 in linpack 3gb. You got slight positive scaling using static above 2000fclk with higher VDD18 if I remember correct? 

I still don't understand what the mechanism behind loss of scaling/neg scaling is above 1900 among most except for WHEA19 flood and slight temp rise. VDD18 is a mystery to me aswell, why does it improve perf at low ProcODT, but not high?


----------



## Taraquin

Veii said:


> 28 ohm procODT at 2000 FCLK is still amazing. Nothing else how to put it
> But haven't you tried different RTT's on it ?
> 005 is strong, and if you really end up having A0 DIMM-PCB ~ higher voltage will cause you big issues, till you change your approach
> * don't forget, i have one of the cheapest b-dies out there on weak A0 PCB. If i can do it you can too, with ease~
> 
> Usually A1 did move near 1.54ish volts before showing PCB failure issues
> And A2 near 1.58-1.6v
> A0 mostly capped out at 1.48 , where 1.52 was barely holding stable and 1.54 did result in a lost memory channel and nearly dead dimm.
> 
> Can it be that you are indeed at A0's ?
> Or is it a missfortunate combination of low procODT and low voltage yet strong RTTs
> ~ soo failures are rather overcurrent = crash, and not overheat
> 
> Oh 005 is indeed very strong for SR, same as 031 is extremely strong for DR
> We got other options, but i would suggest to try at the start 706, or even 607 with over 1.52v
> 
> Well i would also suggest, to maybe make a picture with straight-shining light , of the dimms
> Soo traces reflect light and can be seen = PCB can be identified without removing the heatspreader
> 
> You'll get there, just takes time - because you fight on 2 or 3 fronts. Memory on higher timings need first to be stable on 2:1 mode
> ~ before even attempting to fight against the package throttler and all other throttlers
> 
> You can do it !
> Starting with 16-16-16 till 4200 is not a bad idea
> Probably orient on the RamOC sheet and try things out.
> Maybe even spend time to go up till 4600 MCLK on 2:1 - just so you know if procODT is correct and what voltages you need to run for low procODT requirements.
> This will help you run higher FCLK later, as it's mostly IOD and SOC related.
> But procODT and dimm powering has to be correct, soo it's very recommendable to just go desync like i did with 2100:5000, and figure out what really prevents you running higher MCLK
> FCLK barely bothers with cLDO_VDDP and barely bothers with procODT
> But procODT bothers a lot on memory, VDDG voltages and generally signal integrity ~ soo tick that box first before trying higher FCLK
> 
> * Aida64 on 1 CCD has to show perfect half maximum bandwidth of the FCLK
> Soo for 2033 FLCLK = 32533.3333~ MB/s or 32532MB/s
> for 2067 FCLK = 33072 , or one down 33071 (minimal OS loss)
> 2100 then is 33600 MB/s, but in reality it's 33599 MB/s . . . and so on~
> 33598 is accceptable, but 33540ish , is for example not
> 
> You will instantly notice FCLK based throttle , if write bandwidth is messed up - independent if 2:1 or 1:1 mode


Checking ram is a bit difficult, they are stuck in the D15 cooler, block on one side, fan on other  Probably must remove cooler to check. They are Patriot viper 4400cl19 bought febryary 2021. I read that Patriot has used both A0 and A2, later samples seem more likely A2.


----------



## Veii

Taraquin said:


> Did some further testing of ProcODT and VDD18 at 2000fclk, avg of 3 runs:
> 
> ProcODT 32 VDD18 1.8V:
> Aida 51.8-52ns L3 10.7ns
> Dram calc test 98sec
> Linpack 3gb 263Gflops
> SOTTR CPU game avg 264
> 
> ProcODT 28 VDD18 1.8V:
> Aida 52-52.2ns 10.9ns
> Dram calc test 98.5sec
> Linpack 3gb 261Gflops
> SOTTR CPU game avg 262
> 
> ProcODT 28 VDD18 1.88V:
> Aida 51.7-51.9ns 10.8ns
> Dram calc test 97.5sec
> Linpack 3gb 265Gflops
> SOTTR CPU game avg 267
> 
> I also tested ProcODT 32 and VDD18 1.88V, but got same results as VDD18 1.8V. VDD18 at 1.84V or 1.92V gave slightly lower perf than 1.88V. Running 1900fclk I saw no benefit from raising VDD18.
> 
> So ProcODT actually slightly affects performance and 32 is superior to 28, but upping VDD18 by 80mv makes 28 faster than 32, but for 32 I saw no benefit of raising VDD18.


There is a factor of "too much VDD18" too
Glad you didn't see it, but lower procODT is superior for the bigger picture
Hence 1.8-2.0V ~ VDD 1.8v rail , does not really do much and is a quite broad range
Very likely the lower termination impedance is the way to go , but harder to setup

My sample (well my lazy something) didn't figure out nice scaling with 28ohm, only 30ohm
Likely need to do more work there, but then 4800+ didn't post on 28 nor 32ohm ~ soo likely i'm fine with 30ohm, yet not sure if it was a VDD18 reason
Currently i run it at i think 1.94 , mmm VTT reports 1.93 for me


Taraquin said:


> Checking ram is a bit difficult, they are stuck in the D15 cooler, block on one side, fan on other  Probably must remove cooler to check. They are Patriot viper 4400cl19 bought febryary 2021. I read that Patriot has used both A0 and A2, later samples seem more likely A2.


Usually 4400 19-19 vipers where on custom A2, some A1 mixture 
Maybe try checking it with Thaiphoon Burner ~ if it reports A2 

I would quite matter, to prevent you accidentally killing this snowflake of A0 PCB 
A2's then need a lot of current to even start operating correctly ~ soo the whole opposite of A0
Hence you struggle with 005 that early already, it likely is A0 ~ but guessing sadly doesn't help much


----------



## Taraquin

Veii said:


> There is a factor of "too much VDD18" too
> Glad you didn't see it, but lower procODT is superior for the bigger picture
> Hence 1.8-2.0V ~ VDD 1.8v rail , does not really do much and is a quite broad range
> Very likely the lower termination impedance is the way to go , but harder to setup
> 
> My sample (well my lazy something) didn't figure out nice scaling with 28ohm, only 30ohm
> Likely need to do more work there, but then 4800+ didn't post on 28 nor 32ohm ~ soo likely i'm fine with 30ohm, yet not sure if it was a VDD18 reason
> Currently i run it at i think 1.94 , mmm VTT reports 1.93 for me
> 
> Usually 4400 19-19 vipers where on custom A2, some A1 mixture
> Maybe try checking it with Thaiphoon Burner ~ if it reports A2
> 
> I would quite matter, to prevent you accidentally killing this snowflake of A0 PCB
> A2's then need a lot of current to even start operating correctly ~ soo the whole opposite of A0
> Hence you struggle with 005 that early already, it likely is A0 ~ but guessing sadly doesn't help much


Don't you have DR? I thought DR needed higher ProcODT? At 28 Proc 1.84v and 1.92v VDD18 was a bit faster than 1.8V, but 1.88V was fastest (I can only change in 49mv increments). I see that 1.88V eats a bit pwr budget and get 0.1ns higher L3 in aida vs 1.8V.

I can check thaiphoon. Is my settings safe for A0 lobg therm? 1.46V (1.46-1.475V actual). If I have A0 and other settings are safer I can change.


----------



## ManniX-ITA

Taraquin said:


> You got slight positive scaling using static above 2000fclk with higher VDD18 if I remember correct?


I get positive scaling at FCLK 1900, not 2000, with ProcODT on Linpack, independent of VDD18, using Static.
At FCLK 2000 no differences in Linpack, it was capable to hold 629 GFlops.
There are small performance improvements, like half second less in y-cruncher.
Where it makes a difference is in PBO, there the improvements are much more substantial and visible also in Linpack.

I don't think there's a "model" we can define.
It's different by sample, I think depending on what are the optimal voltages.
Plus is for sure different by CPU model, especially if they are dual CCD.
Raising VDD18, especially on dual CCD, has a huge thermal impact on top of the power budget.



Taraquin said:


> I still don't understand what the mechanism behind loss of scaling/neg scaling is above 1900 among most except for WHEA19 flood and slight temp rise. VDD18 is a mystery to me aswell, why does it improve perf at low ProcODT, but not high?


VDD18 should be the PLL voltage, like for Intel CPU.
The function should be to keep in sync the BCLK and to keep it in sync with all the other signals which are connected (I/O, PCIe, etc).
Guess on Ryzen means also sync with the IF which makes it very important for high FCLK.

When you OC it goes over spec and needs a bump up to keep doing its job.
On my old i4770k couldn't go past 4.6 GHz without a PLL bump, otherwise Prime would crash miserably...

Suppose the same here, when under load some desyncing kicks in and the performances drops.
You can't probably see the difference with low ProcODT cause your 5600X it's already bottlenecking somewhere else.
On a 5900X/5950X you can see the perf improvement anyway (I couldn't see much till my 5950X got updated).

VDD18 has a noticeably thermal impact on my 5950X, about 5-6c, same as FCLK 2000 compared to FCLK 1900.
But in both cases since I'm not bottlenecked somewhere else I can get a perf improvement.

The loss with FCLK 2000 can be due to many factors. WHEA 19s are just a byproduct.
Going over FCLK 1900 changes the sync method on the IF. That's why you immediately see a massive change from 1933.
I can fix it with CLKREQ# but it seems it's not enough for most.

Plus there are many other factors besides the sync which can introduce a perf loss.
A weak VDD18 can be one, the CPU will struggle to pump IOPS.

Higher thermals and power consumption are for sure another.
With same voltages at FCLK 2000 my CPU gets hotter in full load compared to FCLK 1900.

Then there's PBO which could start acting weird cause of thermals, power budget, higher throughput.
If PBO gets too much enthusiast then it starts being too optimistic which will cause a big throttle when it realizes it.
Something like this happens when you set motherboard limits for PBO.

Plus there's the dynamic nature of the HyperTransport protocol which is the foundation of the Infinity Fabric.
Once it's detecting high power consumption or thermals it will fluctuate data rate and bit width to compensate.
Therefore when you expect to start utilizing the 100 MHz gap advantage between 1900 and 2000 you get instead worse throughput.

Plus probably much more that we don't know and we'll never know


----------



## Audioboxer

Ambient around 14~15 degrees? (my windows are closed, it's just that cold in the UK right now!)










Time to run CB23! lol

Part of me thinks I should be able to score a bit higher, but I guess either my PBO settings or my chip silicon isn't quite enough to break into 4.725/4.75 all core like I've seen a few people manage to get nearer 32k points.

Max wattage seems a little low, I've seen people pull higher than 208w. No idea if that is PBO/BIOS settings.


----------



## ManniX-ITA

Audioboxer said:


> Part of me thinks I should be able to score a bit higher, but I guess either my PBO settings or my chip silicon isn't quite enough to break into 4.725/4.75 all core like I've seen a few people manage to get nearer 32k points.


Yes you need better and more stressful settings.

This is a PBO result:









millosh_r`s Cinebench - R23 Multi Core with BenchMate score: 32021 cb with a Ryzen 9 5950X


The Ryzen 9 5950X @ 5150.4MHzscores getScoreFormatted in the Cinebench - R23 Multi Core with BenchMate benchmark. millosh_rranks #null worldwide and #null in the hardware class. Find out more at HWBOT.




hwbot.org





80 MHz more for an additional 15 Watt, tops 69c.
You should be able to get there.
Pity that BM preview version doesn't show the CPU temperature, I prefer the stable one.

Also consider that those runs on HWBot are usually done with the CO offsets just stable enough to finish CB, not daily.


----------



## Audioboxer

ManniX-ITA said:


> Yes you need better and more stressful settings.
> 
> This is a PBO result:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> millosh_r`s Cinebench - R23 Multi Core with BenchMate score: 32021 cb with a Ryzen 9 5950X
> 
> 
> The Ryzen 9 5950X @ 5150.4MHzscores getScoreFormatted in the Cinebench - R23 Multi Core with BenchMate benchmark. millosh_rranks #null worldwide and #null in the hardware class. Find out more at HWBOT.
> 
> 
> 
> 
> hwbot.org
> 
> 
> 
> 
> 
> 80 MHz more for an additional 15 Watt, tops 69c.
> You should be able to get there.
> Pity that BM preview version doesn't show the CPU temperature, I prefer the stable one.
> 
> Also consider that those runs on HWBot are usually done with the CO offsets just stable enough to finish CB, not daily.


Yeah I spoke to Millosh about his CB23 runs lol, his temps are even cooler.

But I _should_ still be able to get a bit higher with better settings. I guess it's possibly CO offsets, mine are stable.

On AGESA 1.2.0.5 one of my best cores is only at -1 for example.


----------



## ManniX-ITA

Audioboxer said:


> But I _should_ still be able to get a bit higher with better settings. I guess it's possibly CO offsets, mine are stable.


Limits, Scalar, VDD18, LLC/PWM settings the nice VRM Over Temp, maybe a small positive vCore offset, everything can impact CB23


----------



## Veii

ManniX-ITA said:


> Going over FCLK 1900 changes the sync method on the IF. That's why you immediately see a massive change from 1933.
> I can fix it with CLKREQ# but it seems it's not enough for most.


This is all i can give you , about the topic CLKREQ#








I suggest to back-it up and sit together with Eder ~ to check what this renamed ClkReq# option really is.
Then i can help you more ~ likely when i know what to look out for and translate 
(have to be cautious on quoting based on copyright infringement. Fair use for critique and education purposes only works if snippets are made. Two of the handles for fair use acceptance "as less shared information from the source as possible" and "used in an criticizing argument")
Anything connected to it,, appears to be in connection with LCLK and in general PCIe delay & management

Hence i had no issues on this board even with PCIe 4.0 and 2100 (although it needed two or 3 boots, before it allowed anything higher than 2067 to run on 4.0 lanes)
And hence we have no CLKREQ# or whatever the real name of it is ~ option
I do feel, it's an unique problem to your setup , but i can be an unique-resolved example while unique-issue = every other sample
Anywho, ASRock doesn't expose it and it's likely not enabled for me. Only DPM LCLK links had to be set to my old 2-1-1-2-2-1-1-2 recommendation.
While AMD OVERCLOCKING PCIe 4.0 toggle, did nothing to the fluctuating LCLK issue on some both 5900X i had = the option does nothing at all or didn't function , compared to my 2-1-1-2 toggles

Also if @domdtxdissar wants to give MSI CLKREQ# toggle a try ~ i can figure out where it is, soo he doesn't need a custom bios and RU_TOOL can just change it permanently
(in hex ~ such thing is easy to override once you know the offset of it)
^ also for this ManniX-ITA can confirm the flag location too
All on all, it's testable, if you choose so ~ dom


----------



## Luggage

Audioboxer said:


> Yeah I spoke to Millosh about his CB23 runs lol, his temps are even cooler.
> 
> But I _should_ still be able to get a bit higher with better settings. I guess it's possibly CO offsets, mine are stable.
> 
> On AGESA 1.2.0.5 one of my best cores is only at -1 for example.


Dont go too high - cb still loves cold more than amps compared to say y-cruncher.
I had to dial down boost over ride and pbo limits compare to my daily to get my best result. edit and scalar x1
Not sure how to translate these to 5950X though.



http://imgur.com/xG593sl


(oh and run an unstable -30 all core co)

compared to daily stable



http://imgur.com/u8xQdJr


----------



## Veii

Luggage said:


> (oh and run an unstable -30 all core co)


This is sometimes really not a good idea
We can't trust FIT being correct, and we can't trust CPPC being correct
But trusting FIT report CPPC correct as in the distance between the cores ~ has higher chance of being correct vs trusting FIT determining core quality ~ yet later also FIT throttling because what cores request, was far beyond what FIT allows

Please give me your CPPC rating from something like Hydra (free version works too)
Or just run hydra without CO's , and let it figure out the real quality of cores (igorslab source)

I'd like you to test something for me, if you want
The problem with -30 methodology i've used 5-6 months ago is,
That cores inside same CCD , will pull other cores down in frequency ~ as the frequency delta should not exceed 100mhz
(soo in reality you don't do much except shift the missmatch voltage-delta, to higher usable frequency without actually resolving the issue in the first place)
In reality and to specs it's lower than that, and this is where clock stretching takes over
But you really do want all cores in each CCD to reach the a maximum freq-strap delta of 25mhz and not more.
Higher will not only pull current away from cores, but also cause constant throttling.

A key feature of Hydra (one of many) is the balance of CO's between CCDs ~ which is a very important feature
Hence you only can shift with a magnitude of -30/+30 CO, yet have to account for balance between CCDs ~ it is a half-through of design implementation
While user can get all cores to behave equally and gaming systems will thank you for that (the best i got a 5900X was 5ghz not higher)


Spoiler: Good

















Spoiler: Bad

















Spoiler: Still bad but acceptable:














AMD's design Team here focused too much on "potential dangerous allowed positive CO" vs "giving the user the ability to run CO's per CCD

An Overclocker, should be granted a -40/+30 penalty (within 150mV allowed offset), and not a -30/+30 , then split dLDO behavior between cores
Currently other CCD does pull first CCD down and while it shouldn't ~ sadly it does
Likely AGESA 1205 did start to change it ~ like again, i do have hopes. But i don't think this is even considered hence all they allow is +200mhz , as higher fMax override did reach voltages they don't want to stand behind / although stable

They outweight that user lack the knowledge of how CO's and fMAX functions (although never provided documents or any explanation about CO by itself)
Compared to just making the eco-system overclocking friendly.
The substrate and hardware engineer team, is very talented ~ but the software-engineer team rather the firmware one, seems to rather be low paid (seems, assumption) or simply have a low % of willpower to do anything except half-based work


----------



## Audioboxer

Luggage said:


> Dont go too high - cb still loves cold more than amps compared to say y-cruncher.
> I had to dial down boost over ride and pbo limits compare to my daily to get my best result. edit and scalar x1
> Not sure how to translate these to 5950X though.
> 
> 
> 
> http://imgur.com/xG593sl
> 
> 
> (oh and run an unstable -30 all core co)
> 
> compared to daily stable
> 
> 
> 
> http://imgur.com/u8xQdJr


Yeah I ain't really interested in pushing CB23 through (knowingly) unstable settings. I had some brief fun in the y-cruncher 2.5b challenge topic with dom pushing unstable manual OC frequencies and chasing the lowest numbers possible, but in general I'd rather have results reflecting my stable system.

I of course say that with no offence intended towards any OCers pushing benchmark numbers whilst knowing it's "bench stable" settings. I get stressed out enough getting my system stable, I don't think I could truly handle the world of benchmark number chasing  It's ruthless.

People sawing the roof off their house, covering the room in ice packs and doing CB23 runs upside down in order for 100 more points. I can't be dealing with that


----------



## Luggage

Audioboxer said:


> Yeah I ain't really interested in pushing CB23 through (knowingly) unstable settings. I had some brief fun in the y-cruncher 2.5b challenge topic with dom pushing unstable manual OC frequencies and chasing the lowest numbers possible, but in general I'd rather have results reflecting my stable system.
> 
> I of course say that with no offence intended towards any OCers pushing benchmark numbers whilst knowing it's "bench stable" settings. I get stressed out enough getting my system stable, I don't think I could truly handle the world of benchmark number chasing  It's ruthless.
> 
> People sawing the roof off their house, covering the room in ice packs and doing CB23 runs upside down in order for 100 more points. I can't be dealing with that


My point was mainly the low pbo limits compared to what i use normally - not that you should go unstable.


----------



## Luggage

Veii said:


> This is sometimes really not a good idea
> We can't trust FIT being correct, and we can't trust CPPC being correct
> But trusting FIT report CPPC correct as in the distance between the cores ~ has higher chance of being correct vs trusting FIT determining core quality ~ yet later also FIT throttling because what cores request, was far beyond what FIT allows
> 
> Please give me your CPPC rating from something like Hydra (free version works too)
> Or just run hydra without CO's , and let it figure out the real quality of cores (igorslab source)
> 
> I'd like you to test something for me, if you want
> The problem with -30 methodology i've used 5-6 months ago is,
> That cores inside same CCD , will pull other cores down in frequency ~ as the frequency delta should not exceed 100mhz
> (soo in reality you don't do much except shift the missmatch voltage-delta, to higher usable frequency without actually resolving the issue in the first place)
> In reality and to specs it's lower than that, and this is where clock stretching takes over
> But you really do want all cores in each CCD to reach the a maximum freq-strap delta of 25mhz and not more.
> Higher will not only pull current away from cores, but also cause constant throttling.
> 
> A key feature of Hydra (one of many) is the balance of CO's between CCDs ~ which is a very important feature
> Hence you only can shift with a magnitude of -30/+30 CO, yet have to account for balance between CCDs ~ it is a half-through of design implementation
> While user can get all cores to behave equally and gaming systems will thank you for that (the best i got a 5900X was 5ghz not higher)
> 
> 
> Spoiler: Good
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Spoiler: Bad
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Spoiler: Still bad but acceptable:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> AMD's design Team here focused too much on "potential dangerous allowed positive CO" vs "giving the user the ability to run CO's per CCD
> 
> An Overclocker, should be granted a -40/+30 penalty (within 150mV allowed offset), and not a -30/+30 , then split dLDO behavior between cores
> Currently other CCD does pull first CCD down and while it shouldn't ~ sadly it does
> Likely AGESA 1205 did start to change it ~ like again, i do have hopes. But i don't think this is even considered hence all they allow is +200mhz , as higher fMax override did reach voltages they don't want to stand behind / although stable
> 
> They outweight that user lack the knowledge of how CO's and fMAX functions (although never provided documents or any explanation about CO by itself)
> Compared to just making the eco-system overclocking friendly.
> The substrate and hardware engineer team, is very talented ~ but the software-engineer team rather the firmware one, seems to rather be low paid (seems, assumption) or simply have a low % of willpower to do anything except half-based work


not sure if you want 


http://imgur.com/a/uXUCAEy


or



Code:


***HYDRA 1.0F by 1usmus***
01/21/2022 09:04:43
Microsoft Windows NT 6.2.9200.0
AMD Ryzen 7 5800X 8-Core Processor
MSI MEG X570 UNIFY (MS-7C35)
BIOS ver. A.B3 SMU ver. 56.52.00
TABLE ver. 3672325
DRAM speed 3800 MHz




09:05:04: Boost testing started!
09:05:22: Boost testing finished!


HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 5020    V 1.486    W 13.58    T 37.31
C02    F 5040    V 1.461    W 13.2    T 35.42
C03    F 5012    V 1.486    W 13.55    T 37.39
C04    F 5034    V 1.465    W 13.67    T 37.72
C05    F 5050    V 1.44    W 12.66    T 33.75
C06    F 5038    V 1.466    W 13.32    T 34.96
C07    F 5037    V 1.481    W 14.18    T 38.5
C08    F 5018    V 1.481    W 13.53    T 37.12

or test something new?


----------



## Veii

Luggage said:


> not sure if you want


Ah ok, you have one CCD
My bad, there was no signature and i can't remember everyone's system - sorry

Hydra values are complicated,
CO values change by -2 , every +25mhz fMAX youset
1 CO value = 6.25 Hydra value, and while Hydra provides value ~ older "early" public hydra does not try to redo frequency testing if "predicted CO for testing" was wrong
Soo either it gives perfect results, or it misses them and makes the sample look worse

Soo suggested CO values are not always optimal, and side-product of this is, that "best cores" are also not always optimal
Yuri and I, have a different viewpoint but try to work with each others experience ~ soo it improves
I personally, would trust more CPPC , although it has been shown that they are wrong in what is "a good" and "a bad" core
I would use CPPCs distance between cores, hence the average of CPPC by CCD is always equal on a by-SKU base
Soo 5600X will have the same average CPPC rating, 5800X will all have the same average and target binning, and so on

It's also important to keep in mind that Hydra results will differ ! , between 0 fMAX, between Auto board-partner-cheatery +100 fMax , and between +200fMax
So also will the result of the "quality based on allcore efficiency" differ by the used scalar changing option
And also FIT will interfere in how high Hydra can boost cores up ~ because this "sometimes annoying thing" ~ is not disabled neither in PB2 nor in OC_MODE , and also not in XOC mode (not fully)

Potentially the best way to make a hydra debug run ~ is with X1 scalar or X6 scalar (enforced)
With fully open limits as for example 400W-400A-400A. With fully open cTDP and package throttle wattage targets & with currently running memOC + LN2 toggles
LN2 toggles will lift couple of peak-voltage restrictions, but board-power limiters have to be set between vendors on different places (sometimes CBS sometimes AMD OVERCLOCKING)

Opening Board limits will not only increase heat, but also change how COs are, as FIT will fully overvolt cores (well to the values they usually "should" be)
Only then it makes sense to start limiting CO's with magnitutes, like everything -1 , everything -2 and so on
But you have to fix the distance delta issues, because that (cores holding freq strap bigger than 25mhz distance) is what will put other cores down
Soo while you will see that cores VID is lower ~ sometimes it is an indicator of "too much negative voltage drop" . . . aka balance between cores inside same CCD is important, and average VID balance between CCD00 & CCD01 is important too 









please start with *
C0 [150] ~ 0
C1 [143] ~ -4
C2 [135] ~ -8
C3 [146] ~ -2
C4 [139 ?] ~ -6
C5 [150] ~ 0
C6 [131] ~ -10
C7 [127] ~ -12
^ your delta in AMD defined quality rating
* then go -1 on everything together, till on 0MHz FMax you find all cores reaching the same held frequency in either TM5 or boost tester , something SSE load based
Afterwards when you "just reached" this point and cores get unstable in lower CO, you can increase FMax by 25Mhz , but have at the same time put -2 CO on everything to combat V/F curve increased VID just by running higher strap. And repeat the process (lower till unstable), then again increase FMax +25Mhz ***

4 CPPC rating = 2 CO rating
150 to 146 CPPC = -2 CO rating (distance)
That is, if CPPC is correct to begin with ~ but it's the scaling by AMD#
When you work with CO's, only the delta & distance interests you , not how low you can go
How low you can go and what VID Average reports , is only interesting to prevent FIT throttle ~ but else irrelevant
Only relevant for dLDO_Injector (digital low dropout regulator, voltage) is the delta between cores inside same CCD
And hence strap-stretching exists, dLDO exists too , it started to exist since 1.1.8.X AGESA
*** Result will be "on stock"


Code:


0Mhz FMAX
C0 [150] ~ 0
C1 [143] ~ -4
C2 [135] ~ -8
C3 [146] ~ -2
C4 [139 ?] ~ -6
C5 [150] ~ 0
C6 [131] ~ -10
C7 [127] ~ -12

50MHz FMAX
C0 [150] ~ -4
C1 [143] ~ -8
C2 [135] ~ -12
C3 [146] ~ -6
C4 [139 ?] ~ -10
C5 [150] ~ -4
C6 [131] ~ -14
C7 [127] ~ -16

^ baseline CO, likely still will be throttled by FIT based on "overvoltage" , soo you need to shift them downwards (-1) till one of the 8 get's unstable
And this post belongs in two different threads ~ but while we are on-topic, i'll use this to relink it towards Hydra thread or CoreCycler thread
Core Cycler thread has a well written post of me and shouldn't need this reminder here.
Yet just so it's known

The range you should stop increasing FMAX is , after you see basestrap frequency of all cores, being higher than +/- 25Mhz
usually the best experience is gotten when all cores are on same perfect identical frequency strap , but if numbers interest you more ~ this is about the limit of what is tollerable
While 100mhz delta is the limit of frequency-strap (clock) stretching before cores are forcefully put on lower frequency-strap (as the delta is too big)

EDIT:
Major Disclaimer,
This methodical way is not "the only correct" one, and it's key focus is* to combat FIT voltage throttling ~ soo equalize VID-Requested per-core*'s within AMDs target
*It will not cover for potentially left core-potential and will not be something you can just calculate and be done with it. It will need lowering till you find instability*
Once instability is found, it should be referred to CoreCycler - tool for testing Curve Optimizer settings for further instructions how to work on "X core is unstable" scenario (how to shift delta balance)
"Keeping up the balance" ~ is more important, than pushing only miniscule amount of cores to peak frequency. Independent if CPPC preferred cores exist or not

Above method is to build your balance foundation, before you start working with CO's
In general short rules:


Code:


4 CPPC rating = 2 CO rating
150 to 146 CPPC = -2 CO rating (distance)
+25MHz FMax = -2 CO to equalize to the same delta
-1 AMD CO = +6.25 Hydra CO

Should help you in your CO figuring out path


----------



## alexcheveau

Veii said:


> nearly always needs SETUP timings that slow down align the signal correctly.


Do you guys have some advice about this Setup timings ?
Like what I'm really losing with 40 AddrCmdSetup.
And what can I change to set it to zero?
With CR1, GDM OFF I can't post without 40 AddrCmdSetup

It's a Crucial Rev.E 
VDIMM is 1.38V
VSOC is 1.1125


----------



## Luggage

Veii said:


> Ah ok, you have one CCD
> My bad, there was no signature and i can't remember everyone's system - sorry
> 
> Hydra values are complicated,
> CO values change by -2 , every +25mhz fMAX youset
> 1 CO value = 6.25 Hydra value, and while Hydra provides value ~ older "early" public hydra does not try to redo frequency testing if "predicted CO for testing" was wrong
> Soo either it gives perfect results, or it misses them and makes the sample look worse
> 
> Soo suggested CO values are not always optimal, and side-product of this is, that "best cores" are also not always optimal
> Yuri and I, have a different viewpoint but try to work with each others experience ~ soo it improves
> I personally, would trust more CPPC , although it has been shown that they are wrong in what is "a good" and "a bad" core
> I would use CPPCs distance between cores, hence the average of CPPC by CCD is always equal on a by-SKU base
> Soo 5600X will have the same average CPPC rating, 5800X will all have the same average and target binning, and so on
> 
> It's also important to keep in mind that Hydra results will differ ! , between 0 fMAX, between Auto board-partner-cheatery +100 fMax , and between +200fMax
> So also will the result of the "quality based on allcore efficiency" differ by the used scalar changing option
> And also FIT will interfere in how high Hydra can boost cores up ~ because this "sometimes annoying thing" ~ is not disabled neither in PB2 nor in OC_MODE , and also not in XOC mode (not fully)
> 
> Potentially the best way to make a hydra debug run ~ is with X1 scalar or X6 scalar (enforced)
> With fully open limits as for example 400W-400A-400A. With fully open cTDP and package throttle wattage targets & with currently running memOC + LN2 toggles
> LN2 toggles will lift couple of peak-voltage restrictions, but board-power limiters have to be set between vendors on different places (sometimes CBS sometimes AMD OVERCLOCKING)
> 
> Opening Board limits will not only increase heat, but also change how COs are, as FIT will fully overvolt cores (well to the values they usually "should" be)
> Only then it makes sense to start limiting CO's with magnitutes, like everything -1 , everything -2 and so on
> But you have to fix the distance delta issues, because that (cores holding freq strap bigger than 25mhz distance) is what will put other cores down
> Soo while you will see that cores VID is lower ~ sometimes it is an indicator of "too much negative voltage drop" . . . aka balance between cores inside same CCD is important, and average VID balance between CCD00 & CCD01 is important too
> View attachment 2548088
> 
> 
> please start with *
> C0 [150] ~ 0
> C1 [143] ~ -4
> C2 [135] ~ -8
> C3 [146] ~ -2
> C4 [139 ?] ~ -6
> C5 [150] ~ 0
> C6 [131] ~ -10
> C7 [127] ~ -12
> ^ your delta in AMD defined quality rating
> * then go -1 on everything together, till on 0MHz FMax you find all cores reaching the same held frequency in either TM5 or boost tester , something SSE load based
> Afterwards when you "just reached" this point and cores get unstable in lower CO, you can increase FMax by 25Mhz , but have at the same time put -2 CO on everything to combat V/F curve increased VID just by running higher strap. And repeat the process (lower till unstable), then again increase FMax +25Mhz ***
> 
> 4 CPPC rating = 2 CO rating
> 150 to 146 CPPC = -2 CO rating (distance)
> That is, if CPPC is correct to begin with ~ but it's the scaling by AMD#
> When you work with CO's, only the delta & distance interests you , not how low you can go
> How low you can go and what VID Average reports , is only interesting to prevent FIT throttle ~ but else irrelevant
> Only relevant for dLDO_Injector (digital low dropout regulator, voltage) is the delta between cores inside same CCD
> And hence strap-stretching exists, dLDO exists too , it started to exist since 1.1.8.X AGESA
> *** Result will be "on stock"
> 
> 
> Code:
> 
> 
> 0Mhz FMAX
> C0 [150] ~ 0
> C1 [143] ~ -4
> C2 [135] ~ -8
> C3 [146] ~ -2
> C4 [139 ?] ~ -6
> C5 [150] ~ 0
> C6 [131] ~ -10
> C7 [127] ~ -12
> 
> 50MHz FMAX
> C0 [150] ~ -4
> C1 [143] ~ -8
> C2 [135] ~ -12
> C3 [146] ~ -6
> C4 [139 ?] ~ -10
> C5 [150] ~ -4
> C6 [131] ~ -14
> C7 [127] ~ -16
> 
> ^ baseline CO, likely still will be throttled by FIT based on "overvoltage" , soo you need to shift them downwards (-1) till one of the 8 get's unstable
> And this post belongs in two different threads ~ but while we are on-topic, i'll use this to relink it towards Hydra thread or CoreCycler thread
> Core Cycler thread has a well written post of me and shouldn't need this reminder here.
> Yet just so it's known
> 
> The range you should stop increasing FMAX is , after you see basestrap frequency of all cores, being higher than +/- 25Mhz
> usually the best experience is gotten when all cores are on same perfect identical frequency strap , but if numbers interest you more ~ this is about the limit of what is tollerable
> While 100mhz delta is the limit of frequency-strap (clock) stretching before cores are forcefully put on lower frequency-strap (as the delta is too big)
> 
> EDIT:
> Major Disclaimer,
> This methodical way is not "the only correct" one, and it's key focus is* to combat FIT voltage throttling ~ soo equalize VID-Requested per-core*'s within AMDs target
> *It will not cover for potentially left core-potential and will not be something you can just calculate and be done with it. It will need lowering till you find instability*
> Once instability is found, it should be referred to CoreCycler - tool for testing Curve Optimizer settings for further instructions how to work on "X core is unstable" scenario (how to shift delta balance)
> "Keeping up the balance" ~ is more important, than pushing only miniscule amount of cores to peak frequency. Independent if CPPC preferred cores exist or not
> 
> Above method is to build your balance foundation, before you start working with CO's
> In general short rules:
> 
> 
> Code:
> 
> 
> 4 CPPC rating = 2 CO rating
> 150 to 146 CPPC = -2 CO rating (distance)
> +25MHz FMax = -2 CO to equalize to the same delta
> -1 AMD CO = +6.25 Hydra CO
> 
> Should help you in your CO figuring out path


I'll jump the gun a bit on that, because I rather not start from 0 again, to what I'm currently dailying - it's not quite as aggressive in regards to the curve as it was before I tested agesa 1205 and it runs a bit hot.

What I should do is test everything on +150 again for gains.



http://imgur.com/a/dfuNd5B


The PBO limits 208-135-170 means I'm just above throttle on anything I've tested. y-cruncher. small fft, linx. 98<99% in hwinfo
For some things I run EDC at 700A for the L3 speed and another time I throttle down the limits for better performance in cb and cpu-z, ts - things that dont like unlimited.
Still feel c0 ran better before.

edit


Code:


+25MHz FMax = -2 CO to equalize to the same delta

so I'll test +150 and +4 CO...


----------



## Veii

alexcheveau said:


> Do you guys have some advice about this Setup timings ?
> Like what I'm really losing with 40 AddrCmdSetup.
> And what can I change to set it to zero?
> With CR1, GDM OFF I can't post without 40 AddrCmdSetup


Rev.E orientation Preset:








3800 = tCKE 9
cLDO_VDDP is only required for 2400MCLK, shouldn't need to touch higher than 900mV, on 1900 MCLK
VDDG are sample specific, irrelevant 
Distance between 4800 and 3800 = 5 steps of "every 200MT/s = +1 tCL , +1 tRCD"
Soo result is primaries -5

17-17-17-17-40-57
tCWL will be then 16, and tRDWR = 9-3
SCL will be 5

Or same thing with
18-18-18-18-44-62 
^ tCWL 18, tRDWR 7 , tWRRD 4
SCL 4 ~ on lower VDIMM near 1.56v

This 17-17 (23-23) was on 1.65vDIMM
Which is perfectly fine with these RTTs (voltage heat is generated by resistance, impedance = amperage [Ohm's Law] - soo voltage by itself means nothing and will not result in heat)
But you will have to see if 1.65v will be needed for tRCD 17 on 3800 , hence Rev.E usually runs tRCD 18 on it
Technically, if you copy RTT's, VDIMM , CAD_BUS and procODT ~ it has to be "fine" on your sample
Only SOC and VDDG needs to be adjusted down ~ and for such it might make sense to follow ManniX-ITA advice = 60mV distance between VDDG IOD & SOC
Soo for you that's 1.125v SOC and old 1.05v IOD


----------



## alexcheveau

Veii said:


> Rev.E orientation Preset:
> 
> 
> 
> 
> 
> 
> 
> 
> 3800 = tCKE 9
> cLDO_VDDP is only required for 2400MCLK, shouldn't need to touch 900mV on 1900 MCLK
> VDDG are sample specific, irrelevant
> Distance between 4800 and 3800 = 5 steps of "every 200MT/s = +1 tCL , +1 tRCD"
> Soo result is primaries -5
> 
> 17-17-17-17-40-57
> tCWL will be then 16, and tRDWR = 9-3
> SCL will be 5
> 
> This was on 1.65vDIMM
> Which is perfectly fine with these RTTs (voltage heat is generated by resistance, impedance = amperage - soo voltage by itself means nothing and will not result in heat)
> But you will have to see if 1.65v will be needed for tRCD 17 on 3800 , hence Rev.E usually runs tRCD 18 on it
> Technically, if you copy RTT's, VDIMM , CAD_BUS and procODT ~ it has to be "fine" on your sample
> Only SOC and VDDG needs to be adjusted down ~ and for such it might make sense to follow ManniX-ITA advice = 60mV distance between VDDG IOD & SOC
> Soo for you that's 1.125v SOC and old 1.05v IOD


I'd surprise with tRCDRD at 17 on 3800
On 20>19 started to spit errors in TM5


----------



## Baio73

ManniX-ITA said:


> 12 for quick testing, 25 cycles to be sure, final 50 cycles.
> @Audioboxer is using 32GB DR, you 16GB SR so double


Thanks to both (also to @Audioboxer , don't know why I can't multi-replay).

So, after a couple of days of testing, here is the current situation:



But tRCDRD was 16, not 15.

To this point I made 50+ TM5 runs, had a #15 error and read it's temperature-related... I have a very conservative fan curve, but as soon as I ramped the fans up, the error has gone away. This result was achieved with VDIMM 1.52v (1.50v read under Windows).

Now I'm having errors trying tRCDRD=15 and VDIMM=1.53v (1.52v read under Windows), but log file does not list the error type, it just says:

========= TestMem5 Log File =========
Customize: Default @1usmus_v3
Start testing at 14:26, 496Mb x24
Testing is completed through 7m 53s,
*detected 3 error(s).*

What does it mean? Less important or errors are errors anyway?
Should I give VDIMM another step up? Max RAM temperature was 70C.
I fear 3800 CAS 14 GDM OFF 1T is out of my range...

Baio


----------



## PJVol

Veii said:


> That is, if CPPC is correct to begin with ~ but it's the scaling by AMD#


Mind you, that according to the specs


> the OSPM *must make no assumption* about the exact meaning of the performance values
> presented by the platform, and all functional decisions and interaction with the platform still happen
> using the abstract performance scale


The platform provides *relative* performance data for all CPUs and cores inside the platform within a common scale.


----------



## Veii

alexcheveau said:


> It's a Crucial Rev.E
> VDIMM is 1.38V
> VSOC is 1.1125
> 
> 
> alexcheveau said:
> 
> 
> 
> I'd surprise with tRCDRD at 17 on 3800
> On 20>19 started to spit errors in TM5
Click to expand...

Balance thing, but also voltage based
If powering is weak, timings won't be able to go lower, including 1T will not function
Hence Setup timings, delay it and over value 32 they work similar to GDM (in the slow-down sense)

Try to replicate the preset with 2T first, before you move to 1T pure
2x8GB can do it, just need to find the right balance of powering for the DIMM-PCB
And some "powering presets" simply require higher voltage to begin with 
Some DIMM-PCBs, like A2 or A3 (micron) will require much more current to begin with 

Also same PCBs (micron) , will rarely go lower than 350ns tRFC
I still haven't figured out if they use a pausing tRFC method, hence it was enforced to be this minimum range ~ or it's something else why Micron dimms can't lower it further
But it's not important really, just limits the time where dimms can operate and not recharge = limits maximum bandwidth a bit.
Tho hence they already are "faster" than B-Die by different Vendor design, it's not big deal having tRFC nearly double of B-Die

I also read 1.1125v SOC just now
Either you need to work on your SOC loadline, hence GET SOC was bellow 1.1v
Or just run 1.125v SOC and we should be fine here

IDK, try 
Voltage is not as dangerous as some companies or forum threads make it to be
It's all about "can you cool it" and "is it ok for this type of PCB & this type of IC"
Rev.E is perfectly fine till 1.72v on full capacity (2x8) and B-Die is perfectly fine till 1.68v on full capacity (2x8)
Then both on dual rank cap out at 1.6v (2x16) but likely that's not the end goal, and just half-done research from our side 

There is nothing wrong running at first beyond 1.6v VDIMM on 3800 
After all you can lower it later up to IC luck and PCB quality luck
But it's easier to start from some foundation , that has been shown to be stable
My Rev.E-MAX dimms, are not even good compared to "better" Micron Rev.B units out there since 2020+


----------



## Veii

PJVol said:


> the OSPM must make no assumption about the exact meaning of the performance values presented by the platform,
> and all functional decisions and interaction with the platform still happen using the abstract performance scale


OS PowerManagement ?
It's only about FIT who does overvolt cores by them having higher voltage
Method does not depend on core quality by itself, neither on VID provided

User has to figure out by how much he can drop CO's step by step
I can not understand which part this quote is from, in the way it's cut out and copy-pasted
It will help me zero understand what you try to say ~ although the way of writing already is complicated enough.


> the OSPM presented by the platform & all functional decisions and interaction with the platform


What is OSPM
What is "the platform"
What are "the functional decisions"


> "using the abstract performance scale"


What performance scale ?
What is even the topic you quote me about this thing 
* is it CPPC, is it FIT, is it Windows scheduler for core quality, is it CO values, is it VID ?!?
There is no way how i can even remotely imagine, what you want to tell me  let alone "understand or learn"


----------



## ManniX-ITA

Baio73 said:


> ========= TestMem5 Log File =========
> Customize: Default @1usmus_v3
> Start testing at 14:26, 496Mb x24
> Testing is completed through 7m 53s,
> *detected 3 error(s).*


Cam happen, look at the which test window has a red background:












Baio73 said:


> What does it mean? Less important or errors are errors anyway?
> Should I give VDIMM another step up? Max RAM temperature was 70C.
> I fear 3800 CAS 14 GDM OFF 1T is out of my range...


Errors are errors, the only good result is that without errors! 

70c is really really high... I wouldn't step up VDIMM.
Can't you improve the case airflow?
I'm in almost the worst case now and I don't go above 60c with 1.57V.

I would change the SOC and VDDG voltages.
Sure you can't run with something lower?

Run Geekbench 5 and set it as baseline in the online browser.
Than test again with different voltages.
Try to lower the CCD voltage especially.

My 5950X is really voltage hungry and doesn't need more than 1050mV CCD.
I would test 1000/1020/1050.

IOD as well is pretty high. Would try 1050mV instead of 1080.

VSOC is too low.
Not sure what you have set in BIOS but 1.125V in Zentimings means under load could go below.
And not under load is 45mV from CCD/IOD. Below 60mV gap you get issues.

Either lower CCD and IOD and keep it like this or add another 25mV.

At the end test tRFC, when you are sure all is working fine and you passed 25 cycles at least.
With 1.52V you should be able to run 252/187/115.


----------



## PJVol

Veii said:


> There is no way how i can even remotely imagine, what you want to tell me





Veii said:


> 4 CPPC rating = 2 CO rating
> 150 to 146 CPPC = -2 CO rating (distance)


???
You are using CPPC "ratings" in your calculations, so I just reminded you what their absolute values mean according to specs ( - nothing) and that it's generally not a good idea to rely upon them at all.


----------



## domdtxdissar

You can change your CPPC rating "on the fly"
With a dual ccd cpu: disable 1 ccd --> lower temps -> enable ccd = higher CPPC rating across all cores
(permanent change until "hard retrain cpu" )
Example:









Pretty sure you can do the same with single CCD cpu's also, just need to do a "hard retrain cpu" when cold (such as disable cores/SMT)


----------



## Luggage

PJVol said:


> ???
> You are using CPPC "ratings" in your calculations, so I just reminded you what their absolute values mean according to specs ( - nothing) and that it's generally not a good idea to rely upon them at all.


I’m pretty sure he’s using them relatively. But might still be a problem if they scale arbitrary.


----------



## ManniX-ITA

Veii said:


> And hence we have no CLKREQ# or whatever the real name of it is ~ option
> I do feel, it's an unique problem to your setup , but i can be an unique-resolved example while unique-issue = every other sample


I think it's adding an additional sync clock which helps stabilizing the BCLK.
The behavior depends on the CPU sample, the AGESA and also how much "updated" is your CPU.
Now that my CPU went through AGESA 1.2.0.5 it behaves differently.
I also have different results enabling CLKREQ# on different BIOS releases at different FCLK speeds.

It's definitely not specific to my setup.
I could replicate the same fix on another MSI board with a 5950X.
But the guy was not comfortable running with high SOC and IOD 

While on another MSI there it didn't help.
But like dom sample the CPU was not happy running with high voltages.



Veii said:


> Also if @domdtxdissar wants to give MSI CLKREQ# toggle a try ~ i can figure out where it is, soo he doesn't need a custom bios and RU_TOOL can just change it permanently
> (in hex ~ such thing is easy to override once you know the offset of it)
> ^ also for this ManniX-ITA can confirm the flag location too
> All on all, it's testable, if you choose so ~ dom


Ah I forgot about the tool... 
but dom is running with X570S Unify-X, I'm running the B550 Unify-X, isn't the flag in another location?

Anyway custom bios are being released for his board too now.


----------



## Sector-z

Hi all sorry for my english in advance.

Need alot of Help 😅 and good setting to start somewhere with a 4X16GB DR B-Die at 3800Mhz Cas 14. (It My first time with AMD and all terms)

5900x
MSI X570 Ace
F4-3600C16-16GTZR X4

I was stable 25 cycle TM5 1usmus_V3 but after many bios flash and troubleshooting bref it no longuer stable on the new bios.

Thanks in advance 🙂


----------



## Veii

PJVol said:


> ???
> You are using CPPC "ratings" in your calculations, so I just reminded you what their absolute values mean according to specs ( - nothing) and that it's generally not a good idea to rely upon them at all.


If you have to comment this, you didn't understand "why" i use them ~ likely didn't read my post
I don't care how high of a value it reports ~ it's something else 


domdtxdissar said:


> You can change your CPPC rating "on the fly"
> With a dual ccd cpu: disable 1 ccd --> lower temps -> enable ccd = higher CPPC rating across all cores
> (permanent change until "hard retrain cpu" )
> Example:
> View attachment 2548115
> 
> 
> Pretty sure you can do the same with single CCD cpu's also, just need to do a "hard retrain cpu" when cold (such as disable cores/SMT)


I will have to test this. The delta stayed the same, although the value changes by conditions
It was assigned by delta based on algorithm
If result is completely different , then my comment is nullified
But hence i've never seen this, i'll try


----------



## domdtxdissar

Veii said:


> Also if @domdtxdissar wants to give MSI CLKREQ# toggle a try ~ i can figure out where it is, soo he doesn't need a custom bios and RU_TOOL can just change it permanently
> (in hex ~ such thing is easy to override once you know the offset of it)
> ^ also for this ManniX-ITA can confirm the flag location too
> All on all, it's testable, if you choose so ~ dom





ManniX-ITA said:


> but dom is running with X570S Unify-X, I'm running the B550 Unify-X, isn't the flag in another location?
> 
> Anyway custom bios are being released for his board too now.


Can you link me to custom bios for the unify x max ?
Since this board is dual bios its pretty easy to switch back and forth.
Will try the CLKREQ# when i get the time..

_edit_
Nevermind, i found the bios page


----------



## ManniX-ITA

domdtxdissar said:


> Can you link me to custom bios for the unify x max ?
> Since this board is dual bios its pretty easy to switch back and forth.
> Will try the CLKREQ# when i get the time..


Here!









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


what i do mean by "unstable" is my system goes into black screen and then Tbh, I don't see the point in running fclk at 2100 unless you have got a 2-ccd sample. If not, then it's unlikely you can run it stable without insane voltages. Have you tried them running at least @2000/4000 without...




www.overclock.net


----------



## PJVol

Veii said:


> I don't care how high of a value it reports ~ it's something else


So you are saying, delta between them may have some meaning? I just want to understand have you found them having the real "value" for the purpose of tuning psm counts?



Veii said:


> It's only about FIT who does overvolt cores by them having higher voltage


And what "FIT does overvolts cores" mean in this context?



Veii said:


> If you have to comment this, you didn't understand "why" i use them


Yeah, I didn't. I read your post, and thats why i asking.


----------



## domdtxdissar

ManniX-ITA said:


> Here!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> what i do mean by "unstable" is my system goes into black screen and then Tbh, I don't see the point in running fclk at 2100 unless you have got a 2-ccd sample. If not, then it's unlikely you can run it stable without insane voltages. Have you tried them running at least @2000/4000 without...
> 
> 
> 
> 
> www.overclock.net


So i need to enable this one correct ?


----------



## ManniX-ITA

domdtxdissar said:


> So i need to enable this one correct ?


Yes!


----------



## ccxmonster

loll !! i just found out the my CPU1P8 voltage was CPU VDD18 !! haha 
so lets play around it. can i get any benefits by raising it ? currently running 2000FCLK


----------



## ManniX-ITA

ccxmonster said:


> can i get any benefits by raising it ? currently running 2000FCLK


Yes you probably can but you need to find the right voltage.
Too high and it will degrade performances.


----------



## ccxmonster

ManniX-ITA said:


> Yes you probably can but you need to find the right voltage.
> Too high and it will degrade performances.


i've increased it to 1.88, showns as 1.896 at hwinfo and i see after increasing it L3 cache performance is increased a lot while memory latency range between 54.5 and 55.7.(i saw 54.5 for the first time though)


----------



## Audioboxer

Yeah watch HWINFO for real voltages.

My MSI board seems to overvolt just about everything. VDIMM set to 1.55v in BIOS, actually runs at 1.56v. CPU1P8 at 1.8/AUTO, actually runs at 1.83v.


----------



## ManniX-ITA

ccxmonster said:


> i've increased it to 1.88, showns as 1.896 at hwinfo and i see after increasing it L3 cache performance is increased a lot while memory latency range between 54.5 and 55.7


Run a lot of different benchmarks to double check the results.
CB23, GB5, Corona, Linpack, CPU-z


----------



## PJVol

@Veii
Btw, have you seen this with your cpu? As if something is switches when crossing the 350A EDC boundary.
L3 latency stays firmly at 10.7ns throughout the 110A - 348A EDC range, and 10.4ns above 350A - (till 540A board's upper limit)

And ask Yuriy pls, what the hell CCA is exactly stands for


----------



## Mach3.2

ManniX-ITA said:


> For sure less expensive... I buy 4 times more Copper for 20 €


Did you factor in machining time? I'm sure it will still be cheaper to do it on your own, though I'm just curious how much of the 80 euros is actually for machine time and labour.


----------



## ManniX-ITA

Mach3.2 said:


> Did you factor in machining time? I'm sure it will still be cheaper to do it on your own, though I'm just curious how much of the 80 euros is actually for machine time and labour.


Not really here in Frankfurt there's a hacker zone with a free CNC on request 
No idea how much would cost the machine time!
Labor cost is pretty low, I don't think it takes much time. 
Including printing the two paper leaflets, picking up the screws and packaging.
Anyway I always gladly pay for not doing something by myself in my free time 
Also happy there's someone willing to do what other big companies don't, a reward is due!
The price is high but considering the small company size and product's niche it's perfectly normal.


----------



## Veii

PJVol said:


> @Veii
> Btw, have you seen this with your cpu? As if something is switches when crossing the 350A EDC boundary.
> L3 latency stays firmly at 10.7ns throughout the 110A - 348A EDC range, and 10.4ns above 350A - (till 540A board's upper limit)
> 
> And ask Yuri pls, what the hell CCA is exactly stands for


I'm seeing this for the first time
My blind guess would be something along the lines of LN2 mode
But the thing is, i've always had 10.4ns and you should've too, when all cores reach that 4.85 boundry
* the only time i didn't have it, is if one core was throttling down or system used resources for something in the hidden

Hmm i wonder,
it's been over 9 months already, i can't remember what values i've used in the past
Only remember strongly that FIT will ignore it, if it's too high.
Can't remember clearly, if i used 1000-250-250 , 1000-300-300 or 1000-400-400

I think i'll try if 350 instead of 400 improves anything, but sadly no ~ it's awkward and odd, but sadly no
Yuri mentioned at the very start that it has to do with Package Throttle and EDC. Mostly EDC
I can ask again, as there was not much information about it


Veii said:


> My blind guess would be something along the lines of LN2 mode


Which is what i'll have to stick my nose into more , too
I know FIT buggs out samples towards 1.55v
On OC_Mode this changes to 1.68v before it enforces an emergency shutdown near the 1.72 range
And i know that Hydra (FIT rather) will bother Hydra and also do emergency shutdowns or frequency "Limit" shutdowns that shouldn't be there

Just XOC guys have given me examples of running 1.8v on 7nm
Which is going against everything i've seen
I wait atm for another big update on Hydra before testing more things
Need to figure out what exactly do the LN2 flag(s) lift

EDIT:
I've seen ASUS release 1206B now for all B550 boards
Wonder if i should try it 
A CPU boardswap would 100% update PSP-FW, if it accidentally wouldn't do in the first place


----------



## Luggage

Veii said:


> I'm seeing this for the first time
> My blind guess would be something along the lines of LN2 mode
> But the thing is, i've always had 10.4ns and you should've too, when all cores reach that 4.85 boundry
> * the only time i didn't have it, is if one core was throttling down or system used resources for something in the hidden
> 
> Hmm i wonder,
> it's been over 9 months already, i can't remember what values i've used in the past
> Only remember strongly that FIT will ignore it, if it's too high.
> Can't remember clearly, if i used 1000-250-250 , 1000-300-300 or 1000-400-400
> 
> I think i'll try if 350 instead of 400 improves anything, but sadly no ~ it's awkward and odd, but sadly no
> Yuri mentioned at the very start that it has to do with Package Throttle and EDC. Mostly EDC
> I can ask again, as there was not much information about it
> 
> Which is what i'll have to stick my nose into more , too
> I know FIT buggs out samples towards 1.55v
> On OC_Mode this changes to 1.68v before it enforces an emergency shutdown near the 1.72 range
> And i know that Hydra (FIT rather) will bother Hydra and also do emergency shutdowns or frequency "Limit" shutdowns that shouldn't be there
> 
> Just XOC guys have given me examples of running 1.8v on 7nm
> Which is going against everything i've seen
> I wait atm for another big update on Hydra before testing more things
> Need to figure out what exactly do the LN2 flag(s) lift
> 
> EDIT:
> I've seen ASUS release 1206B now for all B550 boards
> Wonder if i should try it
> A CPU boardswap would 100% update PSP-FW, if it accidentally wouldn't do in the first place


Would boardswap update psp-fw backwards from potential 1205 changes if I put the 5800X back in the x570gpc that has been sitting in a box with my old 3800x since xmas 2020?

Quite a bit of work with the loop and all :/


----------



## Audioboxer

Playing around with the CPU1P8 voltage, AUTO OC and scalar (just set it to 10x like some others).

What's the highest frequency some of you have seen in HWINFO? 5150mhz has come up for me, but no higher so far irrespective of AUTO OC setting. So that's +100 over default.

Don't think any of this is hurting RAM stability but if I'm going to use AUTO OC and scalar on daily I will of course test RAM again.


----------



## Luggage

Audioboxer said:


> Playing around with the CPU1P8 voltage, AUTO OC and scalar (just set it to 10x like some others).
> 
> What's the highest frequency some of you have seen in HWINFO? 5150mhz has come up for me, but no higher so far irrespective of AUTO OC setting. So that's +100 over default.
> 
> Don't think any of this is hurting RAM stability but if I'm going to use AUTO OC and scalar on daily I will of course test RAM again.


5050 is limit for 5800X, 5150 should be limit for 5900x, 5250 ? should be limit for 5950?









Is it possible to stop Zen 3 from boosting outside of...


Yes, that's the main question! To my opinion there is no sense in limiting or reducing the CPU boost You may not see sense in it, but I'm merely asking if it's possible to have the boost behaviour operate at clocks AMD specifies on its website.




www.overclock.net





Should be easy to check with BoostTesterMannix.exe from coresycler thread.


----------



## Audioboxer

Luggage said:


> 5050 is limit for 5800X, 5150 should be limit for 5900x, 5250 ? should be limit for 5950?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Is it possible to stop Zen 3 from boosting outside of...
> 
> 
> Yes, that's the main question! To my opinion there is no sense in limiting or reducing the CPU boost You may not see sense in it, but I'm merely asking if it's possible to have the boost behaviour operate at clocks AMD specifies on its website.
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> Should be easy to check with BoostTesterMannix.exe from coresycler thread.


I understand adding +200 should be a hypothetical 5250 ceiling, just wondering if anyone has seen beyond 5150. I'm sure they have, but so far that seems to be _my_ limit.


----------



## ManniX-ITA

Audioboxer said:


> I understand adding +200 should be a hypothetical 5250 ceiling, just wondering if anyone has seen beyond 5150. I'm sure they have, but so far that seems to be _my_ limit.


That's my daily limit as well 
Could set an unstable CO count and get my best cores up to 5200 MHz.


----------



## ManniX-ITA

Audioboxer said:


> Don't think any of this is hurting RAM stability but if I'm going to use AUTO OC and scalar on daily I will of course test RAM again.


I don't think is necessary.
You need to test with CoreCycler for errors and running GB5 if it's black screen rebooting during ST tests.



Luggage said:


> Should be easy to check with BoostTesterMannix.exe from coresycler thread.


Well said 
Best way to gather the max clock speeds is to run HWInfo without the screen in foreground (the big X icon bottom right to close the window, will keep it in the system tray).
Settings are best with SMART and Storage disabled.
I usually let it run a few times with 500ms interval and then a few times again with 250ms.


----------



## Audioboxer

ManniX-ITA said:


> That's my daily limit as well
> Could set an unstable CO count and get my best cores up to 5200 MHz.


Ah, so it's likely the CO that can push it a little more? Either way I think I'll settle on +100 then, and be happy if it's squeezing out a tiny bit more









I love how telemetry causes some weird voltage readings lol.


----------



## ManniX-ITA

Audioboxer said:


> Ah, so it's likely the CO that can push it a little more? Either way I think I'll settle on +100 then, and be happy if it's squeezing out a tiny bit more


You need to check the effective clocks, not the core clocks.
Such an amazing sample... mine is trash in comparison 

Above 100 MHz is very often causing instability.
But depending on the quality and the other settings up to 150 MHz is doable.



Audioboxer said:


> I love how telemetry causes some weird voltage readings lol.


What are you using now?


----------



## Audioboxer

ManniX-ITA said:


> You need to check the effective clocks, not the core clocks.
> Such an amazing sample... mine is trash in comparison
> 
> Above 100 MHz is very often causing instability.
> But depending on the quality and the other settings up to 150 MHz is doable.
> 
> 
> 
> What are you using now?


Effective after a game last night was 5,090, so I will keep an eye on that. Only just starting to properly play with AUTO OC so need to do more testing.

Telemetry is 150 and 45 for the two settings once VDD current is taken off auto.


----------



## ManniX-ITA

Audioboxer said:


> Telemetry is 150 and 45 for the two settings once VDD current is taken off auto.


Were my best settings as well before the update...
Could even go faster with 50/55 offset but my best cores would error with CoreCycler.
Going below 140A on Full Scale would kill my scores.

Yesterday it was really hot here and I went through again with telemetry.
Found out now I get better performances going lower than 120A.
Ended up with 90A/40mA and SoC Full Scale at 1A.

Got back finally some more points on CPU-z for the Core 4 which was stuck at 692/695 with better ambient cooling:

































But mainly the MT score wouldn't budge from 13200 instead of dropping steadily down to 13060-13080.

Linpack now drops much less with temp:










Without telemetry was going down to 630 in the last run...

I was literally sweating here when I ran these benchmarks, it was really hot.
The comparisons were all ran with much colder ambient temp.

Better scores with CB23 and GB5 as well.


----------



## Baio73

ManniX-ITA said:


> Cam happen, look at the which test window has a red background:
> 
> View attachment 2548112


Ok



> Errors are errors, the only good result is that without errors!


I suspected that was the truth... 



> 70c is really really high... I wouldn't step up VDIMM.
> Can't you improve the case airflow?
> I'm in almost the worst case now and I don't go above 60c with 1.57V.


I have the case (Lian Li O11 Dynamic XL with 13 fans) on my desk, so I set a very quiet curve.
Pushing the 6 intake fans to max RPM lowers RAM temperature by 20C.
I know 70C is very high, but it's also a scenario I'm going not to experience in normal use... anyway I'm gonna raise intake fans RPM as long as I'm testing, just to exclude temperature issues.



> I would change the SOC and VDDG voltages.
> Sure you can't run with something lower?


I set VSOC, CCD and IOD basing on DRAM Calculator but, as you said, it's not reliable for Ryzen 5xxx
This are the voltages I kept before setting them manually (which means Auto for CCD and IOD and manual input for VSOC):





> Run Geekbench 5 and set it as baseline in the online browser.
> Than test again with different voltages.
> Try to lower the CCD voltage especially.
> 
> My 5950X is really voltage hungry and doesn't need more than 1050mV CCD.
> *I would test 1000/1020/1050.*
> 
> IOD as well is pretty high. Would try 1050mV instead of 1080.


Gonna try this.



> VSOC is too low.
> Not sure what you have set in BIOS but 1.125V in Zentimings means under load could go below.
> And not under load is 45mV from CCD/IOD. Below 60mV gap you get issues.


I'm not seeing this drop, HWiNFO reads 1.125v stable while testing with TM5.
Strange thing, if I open HWiNFO after waking the pc from sleep, it reads 1.131v (both idle and under load).



> Either lower CCD and IOD and keep it like this or add another 25mV.
> 
> At the end test tRFC, when you are sure all is working fine and you passed 25 cycles at least.
> With 1.52V you should be able to run 252/187/115.


I keep this advice for next step, thank you.

Baio


----------



## Audioboxer

ManniX-ITA said:


> Were my best settings as well before the update...
> Could even go faster with 50/55 offset but my best cores would error with CoreCycler.
> Going below 140A on Full Scale would kill my scores.
> 
> Yesterday it was really hot here and I went through again with telemetry.
> Found out now I get better performances going lower than 120A.
> Ended up with 90A/40mA and SoC Full Scale at 1A.
> 
> Got back finally some more points on CPU-z for the Core 4 which was stuck at 692/695 with better ambient cooling:
> 
> View attachment 2548191
> View attachment 2548195
> 
> 
> View attachment 2548196
> View attachment 2548194
> 
> 
> But mainly the MT score wouldn't budge from 13200 instead of dropping steadily down to 13060-13080.
> 
> Linpack now drops much less with temp:
> 
> View attachment 2548192
> 
> 
> Without telemetry was going down to 630 in the last run...
> 
> I was literally sweating here when I ran these benchmarks, it was really hot.
> The comparisons were all ran with much colder ambient temp.
> 
> Better scores with CB23 and GB5 as well.


Definitely got my work cut out for me, I'm just about done with a new curve, but I'll be following your testing above next to actually see what scores I'm getting versus just going "Oh, the pretty boosting numbers in HWINFO core clocks!" 

I have seen some posters shift to 155 / 50 with the new AGESA.


----------



## ManniX-ITA

Baio73 said:


> I have the case (Lian Li O11 Dynamic XL with 13 fans) on my desk, so I set a very quiet curve.
> Pushing the 6 intake fans to max RPM lowers RAM temperature by 20C.
> I know 70C is very high, but it's also a scenario I'm going not to experience in normal use... anyway I'm gonna raise intake fans RPM as long as I'm testing, just to exclude temperature issues.


Wow it's even worse than I thought... 
If you got it from Amazon and you are in the 30 days send them back.
Otherwise... not the best but you can live with it.

Mine as well doesn't get to 60c in a normal use.
But they run 10c less running TM5 with a much higher VDIMM and tighter timings and higher frequency, plus they are DR and not SR.

For comparison I have a 5950X with a Dark Rock Pro 4 with the first CPU fan going over the DIMMs.
There's an ASUS Strix 3090 blowing hot air directly on them.
And it's all packed inside a Corsair 750D Airflow with 5 x 140mm intake and 1 x 140mm out.
Plus since the Unify-X doesn't have a thermal sensor while running TM5 all the fans are at about 60% RPM.

Looks really wrong!

I wonder if that weird (for me at least, I don't have much experience with SR) tRDWR/tWRRD at 18/7 could cause something weird like this.
But in theory should slow down a lot and help with temps not the opposite...



Baio73 said:


> Gonna try this.


Looks for the AES-XTS test score to finetune the CCD voltage.



Baio73 said:


> I'm not seeing this drop, HWiNFO reads 1.125v stable while testing with TM5.


Not while running TM5, it can drop while gaming or more stressful load for the CPU.
Depends on the board and its LLC setting/behavior.



Baio73 said:


> This are the voltages I kept before setting them manually (which means Auto for CCD and IOD and manual input for VSOC):


These are already looking good.



Audioboxer said:


> I have seen some posters shift to 155 / 50 with the new AGESA.


The offset is pushing a lot (or a bit, depends on your CPU "version") ST, while the full scale MT.
Give a try to 120A and 90A in full scale and see if your MT scores gets better or drops.


----------



## nada324

My setup, running pbo +200, with CO, one core -17 and rest -25; (5600X)


----------



## Audioboxer

@ManniX-ITA This is with 150/45, will try others later


----------



## ManniX-ITA

Audioboxer said:


> @ManniX-ITA This is with 150/45, will try others later


Nice!

Of course, I guess you did, better to close HWInfo while running CPU-z.

My one thread CPU-z benchmark is a run on the best core.
Seems a bit low the score, should be above 700.
Maybe you didn't set the affinity or too many programs in background?

I'll repeat the instructions on how to run it with affinity, just in case.

You can run it with Benchmate and set the affinity.
But Benchmate itself running could take away a point or two 

There's an easy and overhead free method with Task Manager.

After you have set 1 thread you need to open Task manager and go to Details.
Right click on cpuz.exe and click set affinity.










Click on <All Processors> to deselect all CPUs.
Then just select 1 thread of your best Core (in your case it's Core 2).








Multiply by 2 since you have SMT enabled and there are 2 threads per CPU: select only CPU 4 in Task Manager window










*Now don't click OK to set the affinity.*
As soon as you click the Bench button on CPU-z the affinity will be reset.

Leave the processor affinity window open and click on CPU-z Bench (1 thread already set).
Now count 6 seconds while the CPU Multi Thread benchmark is running.
At the sixth seconds click OK on the processor affinity window and close the Task Manger.

The MT bench takes 8-10 seconds to finish.
The whole ST bench will run on the Core you selected without any penalty.


----------



## dk_mic

Audioboxer said:


> @ManniX-ITA This is with 150/45, will try others later


Look at effective clocks. I think youre clockstretching..


----------



## Audioboxer

ManniX-ITA said:


> Nice!
> 
> Of course, I guess you did, better to close HWInfo while running CPU-z.
> 
> My one thread CPU-z benchmark is a run on the best core.
> Seems a bit low the score, should be above 700.
> Maybe you didn't set the affinity or too many programs in background?
> 
> I'll repeat the instructions on how to run it with affinity, just in case.
> 
> You can run it with Benchmate and set the affinity.
> But Benchmate itself running could take away a point or two
> 
> There's an easy and overhead free method with Task Manager.
> 
> After you have set 1 thread you need to open Task manager and go to Details.
> Right click on cpuz.exe and click set affinity.
> 
> View attachment 2548216
> 
> 
> Click on <All Processors> to deselect all CPUs.
> Then just select 1 thread of your best Core (in your case it's Core 2).
> View attachment 2548217
> 
> Multiply by 2 since you have SMT enabled and there are 2 threads per CPU: select only CPU 4 in Task Manager window
> 
> View attachment 2548219
> 
> 
> *Now don't click OK to set the affinity.*
> As soon as you click the Bench button on CPU-z the affinity will be reset.
> 
> Leave the processor affinity window open and click on CPU-z Bench (1 thread already set).
> Now count 6 seconds while the CPU Multi Thread benchmark is running.
> At the sixth seconds click OK on the processor affinity window and close the Task Manger.
> 
> The MT bench takes 8-10 seconds to finish.
> The whole ST bench will run on the Core you selected without any penalty.


Thanks, yeah, I never do any of that I just run things lol. All background stuff opened as well.

I'll do this and get some better 150/45 readings.


----------



## PJVol

Veii said:


> But the thing is, i've always had 10.4ns and you should've too, when all cores reach that 4.85 boundry
> * the only time i didn't have it, is if one core was throttling down or system used resources for something in the hidden


I see, I never had it 10.4 with the default limits and so are most of the 5000 owners here. I had always push EDC limit above 300. Now as I finally saw the pattern, such a short transition interval between 10.4 and 10.7 looks suspicious at the very least ))
That reminds me the behavior of my 1900Mhz FCLK config, which is hard to break, no matter how ridiculous are the settings you throw at it, and how it turns into an unstable mess only by raising FCLK one step? 
In a table below I've ran through the usual EDC range and have found that the transition boundary is shifted ~ 10 A upwards. Seemingly due to the temp difference of ~ 4°C between two tests (22-23° for the L3), so the checkpoint is 360A here.


----------



## Veii

@PJVol as always ty for your consistent testing
ManniX knows my thanks, but i haven't mentioned it often to you
Keep up the accurate work 

Just please teach in translated terms. I struggle sometimes to understand you or follow. The goal of this thread should be to deliver people a preset and teaching, that everyone can understand and replicate

It indeed is odd,
But considering i never noticed it being that extreme
It can maybe be stamped as 1205+ oddness
Although if i use my correction CO
(Which is still surprisingly accurate based on CPPC, but we'll clear that topic someday too)
On stock
Then early on pre dLDO days, it maybe peaked to 11.1ns without, and consistent 10.9 with

Although what i could spot, where people on the "leaderboards" often having high fmax boost but horrible multi ~ which showed on L3$ Latency
It was also one of the reasons to check why these load spikes are throttled
(Reason was actual high edc load-spikes)

@ManniX-ITA sadly and strangely, Benchmate's affinity toggles do nothing for me. They don't function ^^'


----------



## PJVol

Veii said:


> A CPU boardswap would 100% update PSP-FW, if it accidentally wouldn't do in the first place


IIRC asrock boards show detailed info about main agesa components, somewhere in a cbs may be. At least you can reliably track the changes occured.
Just curious, if asus expose this info as well.



Veii said:


> Hmm i wonder,
> it's been over 9 months already, i can't remember what values i've used in the past
> Only remember strongly that FIT will ignore it, if it's too high.
> Can't remember clearly, if i used 1000-250-250 , 1000-300-300 or 1000-400-400


I don't think it ignores them, 'cause FIT itself has nothing to do with power limits, so the voltage and temps are the only metrics the FIT control functionality needs, which is obtained from the PSM's and thermal network.
The funny thing is despite you'll never see the EDC exceeds some threshold in any monitoring tools while operating under PB ( aka Core Performance Boost), it is clear as night and day that the L3 EDC limit continues to change accordingly.
The maximum value that my board has allowed me to set is 540 amps - this effectively sets L3 EDC limit to max possible 74 amps, and I'm sure that's the reason why we sometimes can see better performance in a certain workloads when set EDC way above the ceiling observed in HWInfo64 or some other tools.


----------



## Audioboxer

ManniX-ITA said:


> Nice!
> 
> Of course, I guess you did, better to close HWInfo while running CPU-z.
> 
> My one thread CPU-z benchmark is a run on the best core.
> Seems a bit low the score, should be above 700.
> Maybe you didn't set the affinity or too many programs in background?
> 
> I'll repeat the instructions on how to run it with affinity, just in case.
> 
> You can run it with Benchmate and set the affinity.
> But Benchmate itself running could take away a point or two
> 
> There's an easy and overhead free method with Task Manager.
> 
> After you have set 1 thread you need to open Task manager and go to Details.
> Right click on cpuz.exe and click set affinity.
> 
> View attachment 2548216
> 
> 
> Click on <All Processors> to deselect all CPUs.
> Then just select 1 thread of your best Core (in your case it's Core 2).
> View attachment 2548217
> 
> Multiply by 2 since you have SMT enabled and there are 2 threads per CPU: select only CPU 4 in Task Manager window
> 
> View attachment 2548219
> 
> 
> *Now don't click OK to set the affinity.*
> As soon as you click the Bench button on CPU-z the affinity will be reset.
> 
> Leave the processor affinity window open and click on CPU-z Bench (1 thread already set).
> Now count 6 seconds while the CPU Multi Thread benchmark is running.
> At the sixth seconds click OK on the processor affinity window and close the Task Manger.
> 
> The MT bench takes 8-10 seconds to finish.
> The whole ST bench will run on the Core you selected without any penalty.












A little bit better, but not over 700. I'm certain I did it right.

First thing I'm going to try is turning off AUTO OC.


----------



## ManniX-ITA

Veii said:


> @ManniX-ITA sadly and strangely, Benchmate's affinity toggles do nothing for me. They don't function ^^'


Weird!
Are you maybe using BM preview?
I'm on the normal release.



Audioboxer said:


> A little bit better, but not over 700. I'm certain I did it right.
> 
> First thing I'm going to try is turning off AUTO OC.


Wow, shouldn't be the case... with Auto OC you mean Boost Clock?
Probably going to drop big time.

You should check the effective clocks with BoostTester, they are probably much lower than the reference clock.


----------



## Audioboxer

ManniX-ITA said:


> Weird!
> Are you maybe using BM preview?
> I'm on the normal release.
> 
> 
> 
> Wow, shouldn't be the case... with Auto OC you mean Boost Clock?
> Probably going to drop big time.
> 
> You should check the effective clocks with BoostTester, they are probably much lower than the reference clock.












This is with AUTO OC disabled just to get a baseline. Not all T0 cores reaching 5050.










This is AUTO OC +100. Effective clock definitely seems to increase.


----------



## PJVol

Audioboxer said:


> Effective clock definitely seems to increase.


Make it a rule - to check "snapshot CPU polling" checkbox in a settings window that pops up right at the first HWInfo64 launch. Otherwise you wont be able to track effective clocks correcrtly.


----------



## Audioboxer

PJVol said:


> Make it a rule - to check "snapshot CPU polling" checkbox in a settings window that pops up right at the first HWInfo64 launch. Otherwise you wont be able to track effective clocks correcrtly.


Thanks, turned that on, will take a look at it all again!










+100 AUTO OC with some cycles. I guess I can say 5150 is almost hit on one core.

Which now brings me back how to interpret this, as Manni seems convinced I should be capable of hitting 700+ in CPU-Z.

Will have a look and see what my curve offsets are for some of these cores. I don't really have any room to play with though, unless we're talking reducing the curve.


----------



## ManniX-ITA

Audioboxer said:


> Which now brings me back how to interpret this, as Manni seems convinced I should be capable of hitting 700+ in CPU-Z.


Well your Core 2 is maybe not the best booster... hard to say as HWInfo sometimes is missing the max peak.
Maybe you can still add a -2 to its CO count.

But I would try Core 1 seems promising.
You should be able to peak at least 697.
Maybe it's the BenchOS or the FCLK 2000 but in general with that max clock and your cooling I'd expect 700+.


----------



## PJVol

Audioboxer said:


> Which now brings me back how to interpret this, as Manni seems convinced I should be capable of hitting 700+ in CPU-Z.


You should take a closer look at your core2 and core5 - under correct settings they have to reach max boost in a "boosttester" easily. If thats not the case, then either your PB settings are not optimal or your CPU has reached its limits within a current power and temperature restrictions - then you possibly need to back off Boost Override one step.

Btw, AFAIR, based on my early experiments with the "turbo" BIOS (maxboost wasn't locked yet), 5025Mhz would be enough for the 700+ in cpu-z:


----------



## Audioboxer

PJVol said:


> You should take a closer look at your core2 and core5 - under correct settings they have to reach max boost in a "boosttester" easily. If thats not the case, then either your PB settings are not optimal or your CPU has reached its limits within a current power and temperature restrictions - then you possibly need to back off Boost Override one step.
> 
> Btw, AFAIR, based on my experiments with the unlocked maxboost BIOS, 5025Mhz would be enough for the 700+ in cpu-z:


Core 5 used to be at -5 but on AGESA 1.2.0.5 I have had to scale this back to -1.

Core 2 used to be at -17, Hydra told me to bring it down to -6 on AGESA 1.2.0.5. So far I haven't tested increasing it again.

So there is possibly a fair bit of potential for it to go lower. 

Still, if AUTO OC disabled should be able to get over 700 that's a concern.

It could be me putting the affinity to core 2 with it only being at -6 which is the cause of a lowish reading. I guess my next move is to see how close I can get back to the -17 it was fine with on AGESA 1.2.0.3c.


----------



## Luggage

Audioboxer said:


> Thanks, turned that on, will take a look at it all again!
> 
> View attachment 2548229
> 
> 
> +100 AUTO OC with some cycles. I guess I can say 5150 is almost hit on one core.
> 
> Which now brings me back how to interpret this, as Manni seems convinced I should be capable of hitting 700+ in CPU-Z.
> 
> Will have a look and see what my curve offsets are for some of these cores. I don't really have any room to play with though, unless we're talking reducing the curve.


You should but cpu-z extremely temp sensitive and really don’t like high PBO limits because it’s so light.
Manual 5Ghz gives a sc around 690.
PBO with 5050 I hower around 698-699, 700 once or twice. Even a small blck difference playes a role.
Even with my cooling throttling edc gives slightly better cpu-z mc that not.
Todays testing gave best clocks with 132-80-138(? from memory) while with unlimited edc it will use up to almost 160A)

Manual 5G ref.


http://imgur.com/c29nlBe


----------



## Audioboxer

Luggage said:


> You should but cpu-z extremely temp sensitive and really don’t like high PBO limits because it’s so light.
> Manual 5Ghz gives a sc around 690.
> PBO with 5050 I hower around 698-699, 700 once or twice. Even a small blck difference playes a role.
> Even with my cooling throttling edc gives slightly better cpu-z mc that not.
> Todays testing gave best clocks with 132-80-138(? from memory) while with unlimited edc it will use up to almost 160A)
> 
> Manual 5G ref.
> 
> 
> http://imgur.com/c29nlBe












I reduced my AUTO OC to 50 and I put core 2 up to -15. One or the other, or both, seem to be helping.

My assumption is probably curve optimiser doing the most. Just have to check stability now.

*edit* - Ran it again with AUTO OC 100










Seems it's the curve then? Or at the very least AUTO OC 100 might not be hurting and above is just MOE between runs?


----------



## Veii

Luggage said:


> Would boardswap update psp-fw backwards from potential 1205 changes if I put the 5800X back in the x570gpc that has been sitting in a box with my old 3800x since xmas 2020?
> 
> Quite a bit of work with the loop and all :/


Sadly no, not exactly
You would need to not only let it detect as "new CPU" but also to erase TPM
Then this is still not a guarantee, as the old AGESA 1.0.8.0 for example doesn't even exist for boards. They only "where allowed" to supply AGESA 1.1.0.0C, which had a Bootloader FCLK lock (SMU 56.34)
But you'd need something that is earlier than SMU 56.30 (AGESA 1.1.0.0a)

Yet even that is not a guarantee that it will work
Pretty much downgrade can (to my information) only be enforced, if you corrupt it
And hence mostly unstable FCLK and MCLK only can corrupt it on boot reboots (as coretex chip doesn't need to function aside from on boot, you wouldn't be able to corrupt it)
It very likely won't "request" a reflash by itself and stay compatible with older bioses


----------



## ManniX-ITA

Audioboxer said:


> Seems it's the curve then? Or at the very least AUTO OC 100 might not be hurting and above is just MOE between runs?


The curve is the main factor.

You probably have a lot of wasted potential.
Would be worth to spend some time with CoreCycler to find the right CO counts 
Send me a PM if you want to try.


----------



## Audioboxer

ManniX-ITA said:


> The curve is the main factor.
> 
> You probably have a lot of wasted potential.
> Would be worth to spend some time with CoreCycler to find the right CO counts
> Send me a PM if you want to try.


I already did it with 1.2.0.3c, the change to 1.2.0.5 simply meant the curve had to be redone. More-so the better cores. I've been working on that, but not 100% done yet.


----------



## ManniX-ITA

Audioboxer said:


> I already did it with 1.2.0.3c, the change to 1.2.0.5 simply meant the curve had to be redone. More-so the better cores. I've been working on that, but not 100% done yet.


If you want to shorten the time make a first round with SSE and FFT size 720-720 runtimePerCore 6m as suggested by @KedarWolf 
Then move to runtimePerCore Auto (all FFT) with FFT 16000-27000.
When you pass this round as well you can set FFTSize to All and spend the night!


----------



## Luggage

Veii said:


> Sadly no, not exactly
> You would need to not only let it detect as "new CPU" but also to erase TPM
> Then this is still not a guarantee, as the old AGESA 1.0.8.0 for example doesn't even exist for boards. They only "where allowed" to supply AGESA 1.1.0.0C, which had a Bootloader FCLK lock (SMU 56.34)
> But you'd need something that is earlier than SMU 56.30 (AGESA 1.1.0.0a)
> 
> Yet even that is not a guarantee that it will work
> Pretty much downgrade can (to my information) only be enforced, if you corrupt it
> And hence mostly unstable FCLK and MCLK only can corrupt it on boot reboots (as coretex chip doesn't need to function aside from on boot, you wouldn't be able to corrupt it)
> It very likely won't "request" a reflash by itself and stay compatible with older bioses


F—- how I hate that MSI don’t have agesa information with all bios txt blurbs.
I have copys of most bios from 1003a to 1100c for gpc.
And 1004b to current unify.

edit:


Code:


------------------------------------------------------------------
MPG X570 GAMING PRO CARBON WIFI (MS-7B93) V1.9 BIOS Release
------------------------------------------------------------------

1. This is AMI BIOS release

2. This BIOS fixes the following problem of the previous version:
- Updated AMD AGESA ComboAm4v2PI 1.0.8.1

when did they add zen3 support?


----------



## Audioboxer

ManniX-ITA said:


> If you want to shorten the time make a first round with SSE and FFT size 720-720 runtimePerCore 6m as suggested by @KedarWolf
> Then move to runtimePerCore Auto (all FFT) with FFT 16000-27000.
> When you pass this round as well you can set FFTSize to All and spend the night!


Yeah it takes ages, last time it took me weeks for a curve I was happy to call stable lol.

It also taught me anyone going on about running -30 all core stable is talking ****, to put it politely.

"Bench and game stable, good enough for daily!"


----------



## Luggage

Audioboxer said:


> Yeah it takes ages, last time it took me weeks for a curve I was happy to call stable lol.
> 
> It also taught me anyone going on about running -30 all core stable is talking ****, to put it politely.
> 
> "Bench and game stable, good enough for daily!"


as for pbo limits just run hwinfo and play with pbo2 tuner while watching eff core speeds... (hwinfo is stealing some perf so ignore score for now)


http://imgur.com/a/VYcSpIy

i only did mc this morning for some dumb (r/amd) reason


----------



## Audioboxer

Luggage said:


> as for pbo limits just run hwinfo and play with pbo2 tuner while watching eff core speeds... (hwinfo is stealing some perf so ignore score for now)
> 
> 
> http://imgur.com/a/VYcSpIy
> 
> i only did mc this morning for some dumb (r/amd) reason


Where can I download that?


----------



## PJVol

Audioboxer said:


> Yeah it takes ages, last time it took me weeks for a curve I was happy to call stable lol.


It was before, now it may took something like a couple of hours at most.


----------



## Luggage

Audioboxer said:


> Where can I download that?


from him ^^^^








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Or it is the proportion tPHYRDL to tPHYWRL is essentially adding the extra command spacing. Yeah that is what it seems to do to me when the tPHYRDL / tPHYWRL goes to 28 v 11. It is an extra clock of read to write spacing, which adds on to tRDWR but subtracts from tWRRD. Does this add up ? ~...




www.overclock.net


----------



## Mach3.2

Audioboxer said:


> Where can I download that?











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Or it is the proportion tPHYRDL to tPHYWRL is essentially adding the extra command spacing. Yeah that is what it seems to do to me when the tPHYRDL / tPHYWRL goes to 28 v 11. It is an extra clock of read to write spacing, which adds on to tRDWR but subtracts from tWRRD. Does this add up ? ~...




www.overclock.net


----------



## Luggage

PJVol said:


> It was before, now it may took something like a couple of hours at most.


Whats the MO now?


----------



## Audioboxer

Luggage said:


> from him ^^^^
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Or it is the proportion tPHYRDL to tPHYWRL is essentially adding the extra command spacing. Yeah that is what it seems to do to me when the tPHYRDL / tPHYWRL goes to 28 v 11. It is an extra clock of read to write spacing, which adds on to tRDWR but subtracts from tWRRD. Does this add up ? ~...
> 
> 
> 
> 
> www.overclock.net





Mach3.2 said:


> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Or it is the proportion tPHYRDL to tPHYWRL is essentially adding the extra command spacing. Yeah that is what it seems to do to me when the tPHYRDL / tPHYWRL goes to 28 v 11. It is an extra clock of read to write spacing, which adds on to tRDWR but subtracts from tWRRD. Does this add up ? ~...
> 
> 
> 
> 
> www.overclock.net


So let me get this straight, if I set the CO values in there it allows me to do it within Windows? Only thing it can't do is read from the BIOS, so just manually enter them all in this app, click apply, then tweak from Windows as needed?

Damn nifty app, saves a lot of time from the looks of things! Or at least a lot of reboots lol.


----------



## PJVol

Luggage said:


> only did mc this morning


Each time seeing your screenshots, I can't help thinking that you might be a big fan of various rgb stuff.

Oh, and what "MO" means btw?


----------



## Worldwin

Testing some old settings and got this. Am thinking that increasing CLKDRV to 40 should fix this error. Any thoughts?


----------



## Audioboxer

Worldwin said:


> View attachment 2548244
> 
> Testing some old settings and got this. Am thinking that increasing CLKDRV to 40 should fix this error. Any thoughts?


ClkDrvStr 40 and/or CkeDrvStr 24.


----------



## Luggage

PJVol said:


> Each time seeing your screenshots, I can't help thinking that you might be a big fan of various rgb stuff.
> 
> Oh, and what "MO" means btw?


These days I do run some lights, a constant light on the techn block and two diods to illuminate the res and bottom of case. Just for blockage, flow and leaks…
edit: wow it looks horrible in photo . really is more subdued.


http://imgur.com/a/xUI5DuJ



“Modus Operandi” - how it’s done. Modus operandi - Wikipedia

They use in the detective shows on TV


----------



## Worldwin

Audioboxer said:


> ClkDrvStr 40 and/or CkeDrvStr 24.


Will try.


----------



## PJVol

Luggage said:


> “Modus Operandi” - how it’s done. Modus operandi - Wikipedia
> 
> They use in the detective shows on TV


Ahh.. so it's basically some person's psych profile in forensic science?


----------



## Luggage

PJVol said:


> Ahh.. so it's basically some person's psych profile in forensic science?


Yea but anyway how do you set and stress CO in a couple of hours? I still get errors 6-7 hours into a cs run



Code:


*start*
[Sat Feb 12 08:24:44 2022]
*cut*
[Sat Feb 12 14:22:43 2022]
FATAL ERROR: Rounding was 0.5, expected less than 0.4
Hardware failure detected running 24576K FFT size, consult stress.txt file.

ok 4h this time...


----------



## ccxmonster

Does CPU Telemetry values affect cpu performance (including pbo and co enabled) ?? if it affects which values should i set for my 5600X ?


----------



## Veii

Luggage said:


> did they add zen3 support?


1.0.8.0 
Mentioned~
Its SMU 56.26 i think, i'll check in 1h and correct message if it was wrong
* hardwareluxx [Reous] had a list
But 1081 should be fine enough
I remember ASRock's X570 lineup had a slightly higher (minimum) BIOS version.
You'll figure it out


ccxmonster said:


> Does CPU Telemetry values affect cpu performance (including pbo and co enabled) ?? if it affects which values should i set for my 5600X ?


Well it affects the read out, hence it's telemetry "faking"
It works on offset's, but while says mA, it was tested to me in Amps
It's odd to begin with and FIT does autocorrect , if it notices it reporting too low values (zero tracking)
Soo ignores it

Edit
@ManniX-ITA normal freshly installed BM from their main page
Didnt see any preview/beta options to download


----------



## Mach3.2

Audioboxer said:


> So let me get this straight, if I set the CO values in there it allows me to do it within Windows? Only thing it can't do is read from the BIOS, so just manually enter them all in this app, click apply, then tweak from Windows as needed?
> 
> Damn nifty app, saves a lot of time from the looks of things! Or at least a lot of reboots lol.


Yup, exactly what you said.

The power limiters options(PPT, EDC, TDC) can't exceed the limit set in the BIOS though, so you can only apply a value that's lower than what is set in the BIOS. I think Ryzen Master have the same behavior when it comes to power limiter settings.


----------



## Audioboxer

Mach3.2 said:


> Yup, exactly what you said.
> 
> The power limiters options(PPT, EDC, TDC) can't exceed the limit set in the BIOS though, so you can only apply a value that's lower than what is set in the BIOS. I think Ryzen Master have the same behavior when it comes to power limiter settings.


Ryzen Master definitely doesn't, that's how we get around the voltage "bug" with EDC at the moment. You leave the BIOS on manual PBO, but PPT/TDC/EDC set to auto, and then once Windows boots Ryzen Master can be used to increase from the AUTO PBO values.

Will need to test this tool and see if it can work the same!


----------



## Luggage

Audioboxer said:


> Ryzen Master definitely doesn't, that's how we get around the voltage "bug" with EDC at the moment. You leave the BIOS on manual PBO, but PPT/TDC/EDC set to auto, and then once Windows boots Ryzen Master can be used to increase from the AUTO PBO values.
> 
> Will need to test this tool and see if it can work the same!


If you set limits in bios rm is limited by these.
If you set auto in bios rm is limited by mb limits.
This is why you can’t set edc 500A on 1205 any way on x570 unify. (Mb limit is 220)


----------



## Audioboxer

Luggage said:


> If you set limits in bios rm is limited by these.
> If you set auto in bios rm is limited by mb limits.
> This is why you can’t set edc 500A on 1205 any way on x570 unify. (Mb limit is 220)


Ahhh, I got you, and yes, I can confirm I noticed I couldn't go above 220 EDC lol! Funnily enough 220 is where I wanted it set anyway so I just shrugged it off.

AMD and their damn AGESA bugs. See you in November for when they might decide if the voltage cap is a bug or a "masterclass" in software development.


----------



## Veii

Well i figured something out
Option is between "Bad news" & "Worse news"
Pick one ^^''

@PJVol have fun 
LCLK DPM disable does not cause the MP5 , and does not cause WHEA spam ~ which i got to have, persistent through reboot
LN2 Flag created it , took some attempts to wipe it

I start to think i know something, but i can't follow it.
Speaking about seeking for information ~ have you had any success loading my Bios profiles ?
I'd suggest to concentrate on the SOC and MP5 part in the pictures ~ or the overboosting FCLK_EFF & LCLK_EFF

(Slightly) Bad news is, i started to get WHEA 19's and can replicate the issue
Worse news is, i have absolutely no idea how to resolve this for everybody else, except for me
After fixing it and having as usual two reboots on drastic changes after CMOS ~ this time i saw a blue loading bar on a black screen for a fraction of a sec (need to try to record it)
Aand it fixed itself ~ no more WHEA, like before after trying your PBO tool and everything went haywire with the limiters


Spoiler: Sneak-peaks [Experiments]




















I think that's all i "should be able" to share







Bad sample  , well mediocre
* 4th core needs bit more work, failed 4950 AVX2 on diagnose
"Energy Efficiency CCD#1 3.94 | SILVER sample"


----------



## Luggage

Veii said:


> View attachment 2548258
> View attachment 2548259
> 
> Well i figured something out
> Option is between "Bad news" & "Worse news"
> Pick one ^^''
> 
> @PJVol have fun
> LCLK DPM disable does not cause the MP5 , and does not cause WHEA spam ~ which i got to have, persistent through reboot
> LN2 Flag created it , took some attempts to wipe it
> 
> I start to think i know something, but i can't follow it.
> Speaking about seeking for information ~ have you had any success loading my Bios profiles ?
> I'd suggest to concentrate on the SOC and MP5 part in the pictures ~ or the overboosting FCLK_EFF & LCLK_EFF
> 
> (Slightly) Bad news is, i started to get WHEA 19's and can replicate the issue
> Worse news is, i have absolutely no idea how to resolve this for everybody else, except for me
> After fixing it and having as usual two reboots on drastic changes after CMOS ~ this time i saw a blue loading bar on a black screen for a fraction of a sec (need to try to record it)
> Aand it fixed itself ~ no more WHEA, like before after trying your PBO tool and everything went haywire with the limiters
> 
> 
> Spoiler: Sneak-peaks [Experiments]
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> View attachment 2548262
> 
> I think that's all i "should be able" to share
> View attachment 2548263
> 
> Bad sample  , well mediocre
> * 4th core needs bit more work, failed 4950 AVX2 on diagnose
> "Energy Efficiency CCD#1 3.94 | SILVER sample"


Experiments looks really interesting 🧐


----------



## Veii

Luggage said:


> Experiments looks really interesting 🧐


I feel tho FIT emergency shutdowns , as i'm (hard)capped at 5.1Ghz // it's been a reason before reaching higher clock, reason has been worked on and it feels better now, but still
And FIT does interfere with Hydra still ~ although result is much better than early runs.
Early on it barely reached 4.825 on my buggy sample. Today only one core causes a reboot (progress yay, haha)

It's still a bit slow on switching, but been worken on
I think rules (AMD) are enforced, by my odd sample is going around them ~ rather my old profiles i can load
It's FW related for sure, hence i couldn't even post 2100 on LN2 mode, well ok i saw why ~ i got WHEA spam on 2000 with the changes and the typical voltage locks feature "bugs"
* once SMU loaded what it "should" load with the toggle, everything broke

VID on HWinfo is just showing V/F curve scaling, but i'm affraid that FIT is triggering an emergency shutdown, even when VID by itself is meaningless
5.1+ lists as +1.6v and insta crashes. At any core. I do feel it's not core frequency related and it's not enforced voltage (1.375) related
~ but that's another topic 

Sadly, i have no idea what to do with this information
i can't transplant the behavior of this unit over, and it seems while bios profiles potentially fix something buggy (which can be created for ASUS and now ASRock)
It is on Firmware level and potentially change would not stick for everyone else.
For me, by lucky accident it "bugs out" on "normal" behavior, but i can revert it back to old "odd but fixed" behavior ~ tho can not use PJVol's tool at all. His commands break my presets
Seems to be a collection of things that have to align, in order for high FCLK to function

EDIT:
Outside question,
Is HUBCLK_EFFective , for you guys modular too ?
Between idle, between loads and so on
Like does it ever jump to 90+ or mostly sit in the 34 region on ZenPTMonitor // like it did when it runs "normal", the bad normal
This thing ~ is it loadbalanced for everybody ?


----------



## TMavica

TMavica said:


> Finally figured out why I got timeout in TM5, I need to raise the Vsoc. 1.1.25 still got timeout...However Vsoc 1.15 seem a little bit high? Tried lower IOD to 1.00 and Vsoc 1.125 still got TM5 timeout
> PS: Vdimm 1.55
> 
> View attachment 2547657


Got error 0 and 12 in cycles 14 after updated to 1.2.0.6b...whats should i do?


----------



## Luggage

Veii said:


> I feel tho FIT emergency shutdowns , as i'm (hard)capped at 5.1Ghz // it's been a reason before reaching higher clock, reason has been worked on and it feels better now, but still
> And FIT does interfere with Hydra still ~ although result is much better than early runs.
> Early on it barely reached 4.825 on my buggy sample. Today only one core causes a reboot (progress yay, haha)
> 
> It's still a bit slow on switching, but been worken on
> I think rules (AMD) are enforced, by my odd sample is going around them ~ rather my old profiles i can load
> It's FW related for sure, hence i couldn't even post 2100 on LN2 mode, well ok i saw why ~ i got WHEA spam on 2000 with the changes and the typical voltage locks feature "bugs"
> * once SMU loaded what it "should" load with the toggle, everything broke
> 
> VID on HWinfo is just showing V/F curve scaling, but i'm affraid that FIT is triggering an emergency shutdown, even when VID by itself is meaningless
> 5.1+ lists as +1.6v and insta crashes. At any core. I do feel it's not core frequency related and it's not enforced voltage (1.375) related
> ~ but that's another topic
> 
> Sadly, i have no idea what to do with this information
> i can't transplant the behavior of this unit over, and it seems while bios profiles potentially fix something buggy (which can be created for ASUS and now ASRock)
> It is on Firmware level and potentially change would not stick for everyone else.
> For me, by lucky accident it "bugs out" on "normal" behavior, but i can revert it back to old "odd but fixed" behavior ~ tho can not use PJVol's tool at all. His commands break my presets
> Seems to be a collection of things that have to align, in order for high FCLK to function
> 
> EDIT:
> Outside question,
> Is HUBCLK_EFFective , for you guys modular too ?
> Between idle, between loads and so on
> Like does it ever jump to 90+ or mostly sit in the 34 region on ZenPTMonitor // like it did when it runs "normal", the bad normal
> This thing ~ is it loadbalanced for everybody ?


Hubclk: saw it jump to 500 once while opening cpu-z. Apart from that it stays around 32 no matter what - that I can see…

Edit: having Aida open makes it bounce around 50-60… at idle moving the mouse around.

Edit2: and it’s definitely more lively with lower PBO limits, perhaps mostly edc?

edit3: opening opera


http://imgur.com/a/HVVpZKV


----------



## Luggage

Ok so I just realized you can freeze the Zenptmonitor with the mouse, right click left click. Much easier to catch a screenshot.


----------



## Veii

Luggage said:


> edit3: opening opera


Ty, soo everything is normal ~ was just curious if it's load-balanced for anybody, as it has to be

The only instant warning sign i saw, was the 5 digit spam of MP5_BUSY logs
Whatever is connected to it, if it begins to spam and doesn't stay firm ~ something is off
Be it problems resolving, or throttling on something


TMavica said:


> Got error 0 and 12 in cycles 14 after updated to 1.2.0.6b...whats should i do?


TM5 sheet doc says, to decrease procODT or to weaken VDD18 line
If it's right at the start, it is overcurrent crash ~ well you'd pretty much confirm as single sample ? , that RTTs have to be redone or something now after 1205+


----------



## TMavica

Veii said:


> Ty, soo everything is normal ~ was just curious if it's load-balanced for anybody, as it has to be
> 
> The only instant warning sign i saw, was the 5 digit spam of MP5_BUSY logs
> Whatever is connected to it, if it begins to spam and doesn't stay firm ~ something is off
> Be it problems resolving, or throttling on something
> 
> TM5 sheet doc says, to decrease procODT or to weaken VDD18 line
> If it's right at the start, it is overcurrent crash ~ well you'd pretty much confirm as single sample ? , that RTTs have to be redone or something now after 1205+


Sorry, what means single sample? any suggestion if new RTT ? Trying procODT 34.3 and see what going


----------



## Baio73

ManniX-ITA said:


> Wow it's even worse than I thought...
> If you got it from Amazon and you are in the 30 days send *them *back.
> Otherwise... not the best but you can live with it.


Are you speaking of the RAM or what else?



> Mine as well doesn't get to 60c in a normal use.
> But they run 10c less running TM5 with a much higher VDIMM and tighter timings and higher frequency, plus they are DR and not SR.
> 
> For comparison I have a 5950X with a Dark Rock Pro 4 with the first CPU fan going over the DIMMs.
> There's an ASUS Strix 3090 blowing hot air directly on them.
> And it's all packed inside a Corsair 750D Airflow with 5 x 140mm intake and 1 x 140mm out.
> Plus since the Unify-X doesn't have a thermal sensor while running TM5 all the fans are at about 60% RPM.
> 
> Looks really wrong!


As I said, I set a very conservative fan curve for all the fans based on AIO's liquid T, minimum RPM until it ramps quite high.
The case you are using a Corsair Airflow case, surely better than Lian Li.
Anyway, with this custom cruve of the fans RAM sit around 40C in normal use.



> I wonder if that weird (for me at least, I don't have much experience with SR) tRDWR/tWRRD at 18/7 could cause something weird like this.
> But in theory should slow down a lot and help with temps not the opposite...


I set those 2 values following GitHub guide, they are the lower I could do... do you advice to try something else?



> Looks for the AES-XTS test score to finetune the CCD voltage.


Ok



> Not while running TM5, it can drop while gaming or more stressful load for the CPU.
> Depends on the board and its LLC setting/behavior.


Didn't touch LLC setting in the BIOS, I'm gonna look if it drops in normal use.



> These are already looking good.


Ok, starting test them with a 25 TM5 cycles.

Baio


----------



## ManniX-ITA

Baio73 said:


> Are you speaking of the RAM or what else?


Yes I as suggesting to send back the RAM if it's brand new.



Baio73 said:


> The case you are using a Corsair Airflow case, surely better than Lian Li.
> Anyway, with this custom cruve of the fans RAM sit around 40C in normal use.


I don't know the O11, first time will be in a month helping a colleague with his new build.
But it doesn't look like the 750D is much better...
I also have a very conservative fan curve and only added 3 top 140mm fans quite recently.
Before I only had a 140mm blowing over the RAM but then I added the 3090.
Had similar temps before as well.
Maybe it's really your silent fan curve.
40C is in idle/browsing web or gaming?



Baio73 said:


> I set those 2 values following GitHub guide, they are the lower I could do... do you advice to try something else?


Unfortunately not much.
Maybe you can try setting the SCL to 4/5 and see it they can go down this way.
Start first with tWRRD and if you find a lower value try tRDWR.


----------



## Taraquin

Veii said:


> There is a factor of "too much VDD18" too
> Glad you didn't see it, but lower procODT is superior for the bigger picture
> Hence 1.8-2.0V ~ VDD 1.8v rail , does not really do much and is a quite broad range
> Very likely the lower termination impedance is the way to go , but harder to setup
> 
> My sample (well my lazy something) didn't figure out nice scaling with 28ohm, only 30ohm
> Likely need to do more work there, but then 4800+ didn't post on 28 nor 32ohm ~ soo likely i'm fine with 30ohm, yet not sure if it was a VDD18 reason
> Currently i run it at i think 1.94 , mmm VTT reports 1.93 for me
> 
> Usually 4400 19-19 vipers where on custom A2, some A1 mixture
> Maybe try checking it with Thaiphoon Burner ~ if it reports A2
> 
> I would quite matter, to prevent you accidentally killing this snowflake of A0 PCB
> A2's then need a lot of current to even start operating correctly ~ soo the whole opposite of A0
> Hence you struggle with 005 that early already, it likely is A0 ~ but guessing sadly doesn't help much


Thaiphoon reads A0. Managed to remove a stick. If this is A0, is the current settings I run safe?


----------



## Veii

Taraquin said:


> Thaiphoon reads A0. Managed to remove a stick. If this is A0, is the current settings I run safe?
> View attachment 2548327


It is A2
Sadly it needed light-reflecting traces ~ but A0 is completely different
Also sadly A3 is barely noticeable
without opening it, as it seems
Only in the corners its slightly different









TMavica said:


> Sorry, what means single sample?


Single person that reported such issue being 1205+ fault. In this case 1206+
If this really is the truth, then we have to redo everything again for everyone that updates


----------



## Veii

Baio73 said:


> As I said, I set a very conservative fan curve for all the fans based on AIO's liquid T, minimum RPM until it ramps quite high.


Can i imagine that you use an AIO and do not have actively air pushing into the case ?
Der8auer did reverse the airflow on it too - once
Potentially a thing you can do, if the AIO reaches towards the side mount

Just get the back as intake - that will cool VRM
bottom as intake and top as exhaust
"Front" ~ soo side as exhaust too ~ will create negative pressure but might work out.
Would love it to be positive or equal pressure ,but doing top intake is asking for dust
~ only possible if you vacuum clean your room every 4-5th day , or minimum once a week

^ @Audioboxer seems to have figured out a good tradeoff with his 011 XL
Reversing back exhaust as intake - especially for VRM (and memory) cooling , is what i've done couple of times
Works out, just need to adjust the rest as usually Air cooled GPUs pump the heat up
You potentially can push it that way to the front or top front ~ of the case, away from memory


----------



## Audioboxer

Veii said:


> Can i imagine that you use an AIO and do not have actively air pushing into the case ?
> Der8auer did reverse the airflow on it too - once
> Potentially a thing you can do, if the AIO reaches towards the side mount
> 
> Just get the back as intake - that will cool VRM
> bottom as intake and top as exhaust
> "Front" ~ soo side as exhaust too ~ will create negative pressure but might work out.
> Would love it to be positive or equal pressure ,but doing top intake is asking for dust
> ~ only possible if you vacuum clean your room every 4-5th day , or minimum once a week
> 
> ^ @Audioboxer seems to have figured out a good tradeoff with his 011 XL
> Reversing back exhaust as intake - especially for VRM (and memory) cooling , is what i've done couple of times
> Works out, just need to adjust the rest as usually Air cooled GPUs pump the heat up
> You potentially can push it that way to the front or top front ~ of the case, away from memory


I've actually changed to bottom/side intake and rear/top exhaust and it's even better now!


----------



## Luggage

Luggage said:


> I'll jump the gun a bit on that, because I rather not start from 0 again, to what I'm currently dailying - it's not quite as aggressive in regards to the curve as it was before I tested agesa 1205 and it runs a bit hot.
> 
> What I should do is test everything on +150 again for gains.
> 
> 
> 
> http://imgur.com/a/dfuNd5B
> 
> 
> The PBO limits 208-135-170 means I'm just above throttle on anything I've tested. y-cruncher. small fft, linx. 98<99% in hwinfo
> For some things I run EDC at 700A for the L3 speed and another time I throttle down the limits for better performance in cb and cpu-z, ts - things that dont like unlimited.
> Still feel c0 ran better before.
> 
> edit
> 
> 
> Code:
> 
> 
> +25MHz FMax = -2 CO to equalize to the same delta
> 
> so I'll test +150 and +4 CO...


@Veii @PJVol 
Is hydra accurate enough in boost testing to get meaningful results just from testing PBO limits?



Code:


***HYDRA 1.0F by 1usmus***
02/13/2022 01:39:40
Microsoft Windows NT 6.2.9200.0
AMD Ryzen 7 5800X 8-Core Processor
MSI MEG X570 UNIFY (MS-7C35)
BIOS ver. A.B3 SMU ver. 56.52.00
TABLE ver. 3672325
DRAM speed 3800 MHz

01:40:02: Boost testing started!
01:40:20: Boost testing finished!

// all +150, X10, +0.0125V offset (because...) //

// PBO 208 135 170 //

HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4996    V 1.462    W 13.17    T 39.38
C02    F 5000    V 1.366    W 11.44    T 34.33
C03    F 4984    V 1.492    W 14.14    T 40.98
C04    F 4996    V 1.451    W 13.33    T 38.09
C05    F 5000    V 1.374    W 12.03    T 36.16
C06    F 5000    V 1.418    W 12.45    T 35.95
C07    F 4998    V 1.416    W 12.77    T 39.41
C08    F 5000    V 1.437    W 13.16    T 39.33

01:41:30: Boost testing started!
01:41:48: Boost testing finished!

// PBO 160 100 140 //

HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4993    V 1.464    W 13.78    T 39.59
C02    F 5000    V 1.366    W 11.39    T 34.63
C03    F 4985    V 1.488    W 14.17    T 40.92
C04    F 4994    V 1.467    W 14.25    T 41.08
C05    F 5000    V 1.366    W 11.24    T 33.54
C06    F 4998    V 1.440    W 13.55    T 39.96
C07    F 4999    V 1.410    W 12.60    T 38.81
C08    F 5000    V 1.426    W 12.94    T 38.34

01:43:17: Boost testing started!
01:43:35: Boost testing finished!

// PBO 132 88 130 //

HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4998    V 1.465    W 13.82    T 39.96
C02    F 5000    V 1.378    W 11.82    T 34.62
C03    F 4960    V 1.477    W 16.39    T 42.88
C04    F 4990    V 1.472    W 14.28    T 41.72
C05    F 5000    V 1.377    W 11.59    T 33.93
C06    F 5000    V 1.428    W 12.88    T 38.34
C07    F 5000    V 1.403    W 12.08    T 37.75
C08    F 5000    V 1.425    W 12.80    T 38.02

01:45:43: Boost testing started!
01:46:01: Boost testing finished!
 
// PBO 250 200 700 //

HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4988    V 1.465    W 13.49    T 39.97
C02    F 5000    V 1.366    W 11.37    T 34.42
C03    F 4973    V 1.490    W 13.92    T 40.83
C04    F 4988    V 1.463    W 14.00    T 40.41
C05    F 5000    V 1.367    W 11.49    T 34.36
C06    F 5000    V 1.425    W 12.61    T 36.44
C07    F 5000    V 1.414    W 12.27    T 38.81
C08    F 4992    V 1.458    W 14.93    T 43.08


----------



## Veii

Luggage said:


> Is hydra accurate enough in boost testing to get meaningful results just from testing PBO limits?


Yes'n
You test AVX1 boost in his setting
It's slightly bit "too fast" jumping cores, soo you need to run couple more to realy verify X core doesn't boost up
After couple runs then VID requested will be also kind of accurate (too)
Soo i'd say yes * but with caveats

Don't think tho it is reliable on the powerlimit part (enforcing it)
it only works to hold it on Hydra-Boost mode, but not to enforce it on PB2 mode

EDIT:
Using higher scalar "should" also increase the VID request of each core
I found x6 to x7 to be the peak
Elmor i think had a similar result near December 2020

EDIT 2:
To me it looks like Core #3/Bios-02 bothers here with it's CO
Needs a stronger CO drop, or everything around it a more positive CO / balance issue
Although it can be just 1.45v VID limited ~ please test

EDIT 3:
3D-Mark CPU is not bad for a CPU frequency hold-test, or Hydra stability test check


----------



## Luggage

Veii said:


> Yes'n
> You test AVX1 boost in his setting
> It's slightly bit "too fast" jumping cores, soo you need to run couple more to realy verify X core doesn't boost up
> After couple runs then VID requested will be also kind of accurate (too)
> Soo i'd say yes * but with caveats
> 
> Don't think tho it is reliable on the powerlimit part (enforcing it)
> it only works to hold it on Hydra-Boost mode, but not to enforce it on PB2 mode
> 
> EDIT:
> Using higher scalar "should" also increase the VID request of each core
> I found x6 to x7 to be the peak
> Elmor i think had a similar result near December 2020
> 
> EDIT 2:
> To me it looks like Core #3/Bios-02 bothers here with it's CO
> Needs a stronger CO drop, or everything around it a more positive CO / balance issue
> Although it can be just 1.45v VID limited ~ please test
> 
> EDIT 3:
> 3D-Mark CPU is not bad for a CPU frequency hold-test, or Hydra stability test check


Pushed #2 (3 f—starting at 1!)
Now #0 (at limit just ran 10h cs) #2 and #3 are clearly 1 bin below.
Decrease the rest?


----------



## Veii

Luggage said:


> Pushed #2 (3 f—starting at 1!)
> Now #0 (at limit just ran 10h cs) #2 and #3 are clearly 1 bin below.
> Decrease the rest?


Sorry, i can't make sense of what you wrote


----------



## Luggage

Veii said:


> Sorry, i can't make sense of what you wrote


Changed 2/3 2co values down, more negative.
Now 0/1, 2/3 and 3/4 show the same 20-25Mhz lower boost. 
I can’t give a more negative value to 0/1…
So instead I should raise, less negative, the rest of the cores - to get them all within the same boost bin ( <25MHz difference ) - even though they can run with more negative co value?


----------



## Veii

Luggage said:


> I can’t give a more negative value to 0/1…
> So instead I should raise, less negative, the rest of the cores - to get them all within the same boost bin ( <25MHz difference ) - even though they can run with more negative co value?


Do you have any result pictures ?
01, 04, 05, 06, 07 ~ are fine
00, 02 , 03 need work

I can#t imagine voltage differences without reading voltage differences
Needs pictures

Good cores that can hold the clock, can use positive CO they do not need negative CO
Issue starts to arrise, when bad cores request too much VID , raise global average VID
Then can not hold boost (limited by FIT), lower to slower strap and push every other good core with them down

Key work, is to lower VID on the bad cores as much as possible
Because they request too much 
Good cores will not request too much and shouldn't show issues
Instability is another topic


----------



## Luggage

Veii said:


> Do you have any result pictures ?
> 01, 04, 05, 06, 07 ~ are fine
> 00, 02 , 03 need work
> 
> I can#t imagine voltage differences without reading voltage differences
> Needs pictures
> 
> Good cores that can hold the clock, can use positive CO they do not need negative CO
> Issue starts to arrise, when bad cores request too much VID , raise global average VID
> Then can not hold boost (limited by FIT), lower to slower strap and push every other good core with them down
> 
> Key work, is to lower VID on the bad cores as much as possible
> Because they request too much
> Good cores will not request too much and shouldn't show issues
> Instability is another topic





Code:


***HYDRA 1.0F by 1usmus***
02/13/2022 17:55:22
Microsoft Windows NT 6.2.9200.0
AMD Ryzen 7 5800X 8-Core Processor
MSI MEG X570 UNIFY (MS-7C35)
BIOS ver. A.B3 SMU ver. 56.52.00
TABLE ver. 3672325
DRAM speed 3800 MHz

HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4991    V 1.478    W 13.86    T 41.54
C02    F 5000    V 1.39    W 12    T 36.8
C03    F 4991    V 1.477    W 13.91    T 41.22
C04    F 4994    V 1.468    W 14.22    T 42.39
C05    F 5000    V 1.388    W 11.86    T 36.56
C06    F 5000    V 1.442    W 13.45    T 39.1
C07    F 5000    V 1.442    W 13.24    T 41.21
C08    F 4998    V 1.444    W 13.09    T 40.14

HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4985    V 1.482    W 14.25    T 42.35
C02    F 5000    V 1.404    W 12.27    T 37.32
C03    F 4988    V 1.478    W 13.86    T 41.55
C04    F 4994    V 1.472    W 14.38    T 42.8
C05    F 5000    V 1.403    W 12.4    T 37.01
C06    F 4998    V 1.452    W 13.81    T 40.16
C07    F 4998    V 1.44    W 13.16    T 41.46
C08    F 4999    V 1.453    W 14.14    T 40.96

HYDRA BOOST TESTER RESULTS
CORE / FREQUENCY / VID / POWER / TEMP
C01    F 4980    V 1.479    W 16.01    T 42.72
C02    F 5000    V 1.394    W 12.32    T 37.35
C03    F 4988    V 1.472    W 13.63    T 40.38
C04    F 4976    V 1.47    W 16.08    T 45.25
C05    F 5000    V 1.4    W 12.16    T 36.34
C06    F 5000    V 1.454    W 13.62    T 39.35
C07    F 5000    V 1.444    W 13.5    T 41.68
C08    F 5000    V 1.449    W 13.51    T 39.76


----------



## Baio73

ManniX-ITA said:


> Yes I as suggesting to send back the RAM if it's brand new.


No, I bought them a while ago... I thought about swtiching to another kit but with Corsair it's always a lottery, there is a high probability not to get another Samsung B-Die.
Consider they are RGB and I also have a Light Enhancement kit... this raises temperatures for sure.
And last but not least, one of the tubes of the AIO touches one module... I know I should route it another way, but it's aestethically better this way...



> I don't know the O11, first time will be in a month helping a colleague with his new build.
> But it doesn't look like the 750D is much better...
> I also have a very conservative fan curve and only added 3 top 140mm fans quite recently.
> Before I only had a 140mm blowing over the RAM but then I added the 3090.
> Had similar temps before as well.


It's a case more oriented to aestethic than airflow, but I like it so much... it's been challenging building this rig, cable management can be a pain (especially with Corsair fans), but it's so funny to me. 



> Maybe it's really your silent fan curve.


I'm sure it is.



> 40C is in idle/browsing web or gaming?


Idle/browsing and light gaming (the only ones I can do at the moment), 40-45C range.



> Unfortunately not much.
> Maybe you can try setting the SCL to 4/5 and see it they can go down this way.
> Start first with tWRRD and if you find a lower value try tRDWR.


I'll do ASA I finish testing new voltages. At the moment lowering SOC, CCD and IOD made me gain 2C of max RAM T and 3-4 average during testing.

Baio

PS. I must say TM5 is better in finding errors (especially because it tells you what kind of error), but on the other side it needs the user to be constantly at the keyboard launching it again and again without the possibility to do quite anything... the author should really consider a batch version...


----------



## Baio73

Veii said:


> Can i imagine that you use an AIO and do not have actively air pushing into the case ?
> Der8auer did reverse the airflow on it too - once
> Potentially a thing you can do, if the AIO reaches towards the side mount
> 
> Just get the back as intake - that will cool VRM
> bottom as intake and top as exhaust
> "Front" ~ soo side as exhaust too ~ will create negative pressure but might work out.
> Would love it to be positive or equal pressure ,but doing top intake is asking for dust
> ~ only possible if you vacuum clean your room every 4-5th day , or minimum once a week
> 
> ^ @Audioboxer seems to have figured out a good tradeoff with his 011 XL
> Reversing back exhaust as intake - especially for VRM (and memory) cooling , is what i've done couple of times
> Works out, just need to adjust the rest as usually Air cooled GPUs pump the heat up
> You potentially can push it that way to the front or top front ~ of the case, away from memory


Thanks for your advice.
I have tha AIO top-mounted push/pull as exhaust, back also exhaust (and I can here fresh air coming from it in normal use), bottom and side all as intake.
I've experienced the AIO side-mounted but didn't notice a great improvement in temperatures... besides negative pressure is a no go to me, I do not have time to clean it once a week.
I saw many tutorials before buying this case, I remember one trying 6 different fans layout, but at the end you must choose between higher CPU but lower GPU T, or the other way round.
Maybe when I decide to try PBO+CO, I'll see if a different solution fits better with CPU OC.

Baio


----------



## drkCrix

Good day all,

Any ideas on what I can change to drop may latency? Hoping to get under 60ns











Cheers,

Chris


----------



## Veii

Luggage said:


> Code:
> 
> 
> ***HYDRA 1.0F by 1usmus***
> 02/13/2022 17:55:22
> Microsoft Windows NT 6.2.9200.0
> AMD Ryzen 7 5800X 8-Core Processor
> MSI MEG X570 UNIFY (MS-7C35)
> BIOS ver. A.B3 SMU ver. 56.52.00
> TABLE ver. 3672325
> DRAM speed 3800 MHz
> 
> HYDRA BOOST TESTER RESULTS
> CORE / FREQUENCY / VID / POWER / TEMP
> C01    F 4991    V 1.478    W 13.86    T 41.54
> C02    F 5000    V 1.39    W 12    T 36.8
> C03    F 4991    V 1.477    W 13.91    T 41.22
> C04    F 4994    V 1.468    W 14.22    T 42.39
> C05    F 5000    V 1.388    W 11.86    T 36.56
> C06    F 5000    V 1.442    W 13.45    T 39.1
> C07    F 5000    V 1.442    W 13.24    T 41.21
> C08    F 4998    V 1.444    W 13.09    T 40.14
> 
> HYDRA BOOST TESTER RESULTS
> CORE / FREQUENCY / VID / POWER / TEMP
> C01    F 4985    V 1.482    W 14.25    T 42.35
> C02    F 5000    V 1.404    W 12.27    T 37.32
> C03    F 4988    V 1.478    W 13.86    T 41.55
> C04    F 4994    V 1.472    W 14.38    T 42.8
> C05    F 5000    V 1.403    W 12.4    T 37.01
> C06    F 4998    V 1.452    W 13.81    T 40.16
> C07    F 4998    V 1.44    W 13.16    T 41.46
> C08    F 4999    V 1.453    W 14.14    T 40.96
> 
> HYDRA BOOST TESTER RESULTS
> CORE / FREQUENCY / VID / POWER / TEMP
> C01    F 4980    V 1.479    W 16.01    T 42.72
> C02    F 5000    V 1.394    W 12.32    T 37.35
> C03    F 4988    V 1.472    W 13.63    T 40.38
> C04    F 4976    V 1.47    W 16.08    T 45.25
> C05    F 5000    V 1.4    W 12.16    T 36.34
> C06    F 5000    V 1.454    W 13.62    T 39.35
> C07    F 5000    V 1.444    W 13.5    T 41.68
> C08    F 5000    V 1.449    W 13.51    T 39.76
> 
> 
> 
> 
> Veii said:
> 
> 
> 
> EDIT:
> Using higher scalar "should" also increase the VID request of each core
> I found x6 to x7 to be the peak
> Elmor i think had a similar result near December 2020
> 
> EDIT 2:
> To me it looks like Core #3/Bios-02 bothers here with it's CO
> Needs a stronger CO drop, or everything around it a more positive CO / balance issue
> Although it can be just 1.45v VID limited ~ please test
> 
> EDIT 3:
> 3D-Mark CPU is not bad for a CPU frequency hold-test, or Hydra stability test check
Click to expand...

Maybe answer overlapping
This was the work required


----------



## Baio73

Audioboxer said:


> I've actually changed to bottom/side intake and rear/top exhaust and it's even better now!


That’s my current layout and I can confirm this.
Baio


----------



## Veii

drkCrix said:


> Good day all,
> 
> Any ideas on what I can change to drop may latency? Hoping to get under 60ns
> 
> 
> View attachment 2548367
> 
> 
> Cheers,
> 
> Chris


CommandRate 2T
GDM off , tRC = tRP + tRAS


----------



## Luggage

Veii said:


> Maybe answer overlapping
> This was the work required


Great 👍 
Now I just have to find it again because touching ln2mode hard locked and had to reset bios with no save 😩😂


----------



## Veii

Luggage said:


> Great 👍
> Now I just have to find it again because touching ln2mode hard locked and had to reset bios with no save 😩😂


LN2 mode does "fix" rather "ruin" mine/our no Whea samples
Don't use it


----------



## drkCrix

Made the changes, not sure where to go next


----------



## ManniX-ITA

drkCrix said:


> Made the changes, not sure where to go next


You VSOC is too low, raise it at least to 1.15V.


----------



## drkCrix

Out of curiosity, what would that change allow for?

Just trying to learn as I go

Thanks,

Chris


----------



## Requiem4u

drkCrix said:


> Made the changes, not sure where to go next
> 
> View attachment 2548372


Run aida once in windows safe mode. Just to know how much your software slows it down.


----------



## Audioboxer

ManniX-ITA said:


> You VSOC is too low, raise it at least to 1.15V.


Not necessarily, my VSOC is absolutely fine on AUTO at 3800. This is 1.1v.


----------



## Luggage

Audioboxer said:


> Not necessarily, my VSOC is absolutely fine on AUTO at 3800. This is 1.1v.


Yea I run 1.1 - droops to ~1.087.
Ran 1.085 for a while dropping to ~1.067 but I suspected it not be totally stable while testing CO curve (p95), ram was rock stable though (anta extreme, occt)


----------



## MrHoof

Pretty sure @ManniX-ITA was pointing out that IOD 1.06 is to close to Soc 1.1(1.085 droop) not that Soc it self is to low.

edit: atleast on matisse it was suggested to alteast guarantee +40mv between iod and soc would think same counts for vermeer.


----------



## Taraquin

drkCrix said:


> Made the changes, not sure where to go next
> 
> View attachment 2548372


Either one or more voltages are too low or you have a lot of bloatware. Soc and/or iod is the usual suspects.


----------



## drkCrix

Right now I have it set to 1.100v for SoC in bios, vddp at .900v, vddg ccd at .940v and iod at 1.060v.

Due to vdroop should I have SoC up a touch more?

I will run in safe mode and see what it looks like.

Cheers

Chris


----------



## Audioboxer

MrHoof said:


> Pretty sure @ManniX-ITA was pointing out that IOD 1.06 is to close to Soc 1.1(1.085 droop) not that Soc it self is to low.
> 
> edit: atleast on matisse it was suggested to alteast guarantee +40mv between iod and soc would think same counts for vermeer.


Well spotted


----------



## Veii

drkCrix said:


> Made the changes, not sure where to go next
> 
> View attachment 2548372


Latency is 1.5ns higher
soo very likely just unstable (very likely because tRRD is low, but you'll know better or the guides that where followed)
Neither old nor current readout had an attached TM5 (25 loops) test to it
Nobody can know that this is stable , except clearly seeing that you are autocorrecting for errors ~ hence latency is higher


----------



## drkCrix

Here is the AIDA run in safe mode. Seems to look better latency wise.

Is there a specific TM5 profile to run? (Its been ages since I last played around with it)










Cheers,

Chris


----------



## Asterion

*Ryzen 7 3700X / 16GB Corsair Vengeance RGB 3600MHz (16-16-16-30 1T 1.36v)*:


----------



## ManniX-ITA

drkCrix said:


> Due to vdroop should I have SoC up a touch more?


Yes, I had stability issues below 60mV gap. Better to keep at least that distance with Vdroop.
Consider also the under load the Vdroop will be higher than what is reported by Zentimings.



drkCrix said:


> Here is the AIDA run in safe mode. Seems to look better latency wise.


It's better indeed but maybe you still have something auto-correcting as said by @Veii 
Did you set tRRD_L to 6?

If you want less latency you need more VDIMM.
Then you can try tCL 14 and/or tighter tRFC.



drkCrix said:


> Is there a specific TM5 profile to run? (Its been ages since I last played around with it)


1usmus_v3






TM5.zip







drive.google.com





You need to run at least 25 cycles to be sure it's rock solid.


----------



## Taraquin

Veii said:


> It is A2
> Sadly it needed light-reflecting traces ~ but A0 is completely different
> Also sadly A3 is barely noticeable
> without opening it, as it seems
> Only in the corners its slightly different
> View attachment 2548341
> 
> 
> Single person that reported such issue being 1205+ fault. In this case 1206+
> If this really is the truth, then we have to redo everything again for everyone that updates











This is the best I can do  









Not much room for better cooling, ram is stuck below D15 behind the front fan  

I conclude that errors above 1.5V is probably due to pverheat since I can pass a cycle or 2 in TM5, then I get some errors and in round 3 they pile up and act totally random with 2, 4, 5, 6, 8, 10, 12, 14, 15...


----------



## Taraquin

drkCrix said:


> Right now I have it set to 1.100v for SoC in bios, vddp at .900v, vddg ccd at .940v and iod at 1.060v.
> 
> Due to vdroop should I have SoC up a touch more?
> 
> I will run in safe mode and see what it looks like.
> 
> Cheers
> 
> Chris


You may need 1.12-1.15v soc and up to 1.05v iod. If one of these are below requirements performance drops. I need 1.04v iod for 51.7ns, if I set 0.98v which still boots and seem stable I get around 70ns.


----------



## Subut

I landed this sweet overclock 🥳. many thanks to veii, its amazing how good you are at this.


----------



## Taraquin

Subut said:


> I landed this sweet overclock 🥳. many thanks to veii, its amazing how good you are at this.
> View attachment 2548470


Good and very similar to mine, one of us lucky few without whea19 above 1900 fclk, but you should be able to get rfc lower. 304, 288 or maybe 272 should work  rrds 4, rrdl 6, faw 16, scks at 4 is better. Wr 12, rtp 6, wtrs 4, wtrl 12 is also better.


----------



## Audioboxer

Just a reminder for how long it can take for a core to spit out an error lol

Relevant to memory because while TM5 can behave weird with Windows 11 at times when it comes to core boosting, an unstable curve also 100% can lead to TM5 timeouts.


----------



## Audioboxer

Another thing I've noticed is with the default PBO settings AUTO uses 142/95/140 games tend to boost some cores more often between 5050~5100.

When using custom PBO numbers like 270/168/220, it's more often 4900~5000 going over Rivatuner and watching the cores.

Pretty much no FPS difference though, but that'll just be because the 5950x is more than powerful enough for gaming at the resolution I use. More likely my 2080Ti causes lower frames on higher settings than the CPU helping.

Is this just the trade off between ST and MT orientated PBO numbers? Increasing PBO will improve the scores in CB23 by thousands and get you better MT scores, but ST drops just a little to facilitate that?


----------



## ManniX-ITA

Audioboxer said:


> Is this just the trade off between ST and MT orientated PBO numbers? Increasing PBO will improve the scores in CB23 by thousands and get you better MT scores, but ST drops just a little to facilitate that?


Yes it's mainly TDC and EDC.
Lower the limits are and better ST and light threaded are boosting.


----------



## Audioboxer

ManniX-ITA said:


> Yes it's mainly TDC and EDC.
> Lower the limits are and better ST and light threaded are boosting.


Great, thought so. Makes more sense to me now what Hydra is trying to do when it has its "game mode".


----------



## vegetagaru

Hello all ive been reading a lot here and been finding a lot of useful info, but im on a point that im trying to understand whats happening and cant find the problem.
im sitting on a new 5900x (stepping 2) and some new ram too (F4-4400c17D-32GVK) funny thing is that the label and in thaiphoon says "F4-4400C17-16GVK" (i bought this coz was an amazing deal and still with warranty from shop)

anyway atm on cpu i have no clock almost everything is on auto (i had curve but since im having a problem i placed all on auto)
in tearms of ram i had to set VDDG CCD/IOD to 1(at least) atm is on 1.05 or else wouldn't post (when setting freq and FCLK at same speeds)
also in tearms of ram i set up the 16/16/16/16/34/50 timmings and tRFC to be a higher value and since i read somewhere that needs to be a multiple of tRC i placed 450










now my problem..... i "dont have any problem" in some games it keeps crashing into windows(with no errors or BSOD) when i had my old 2700x on a 3200 cl4, if this would happen i knew it was ram clock problem, but now im trying to mess a lot with it and still didnt found solution, i even tried to place everything(timings) on auto and still same problem.

in tearms of WHEA error dunno if considered as error but it appears as warming very occasionally (not when game crashes into windows):









if someone could try help me i would appreciate it, and thank you in advance.


----------



## Audioboxer

vegetagaru said:


> Hello all ive been reading a lot here and been finding a lot of useful info, but im on a point that im trying to understand whats happening and cant find the problem.
> im sitting on a new 5900x (stepping 2) and some new ram too (F4-4400c17D-32GVK) funny thing is that the label and in thaiphoon says "F4-4400C17-16GVK" (i bought this coz was an amazing deal and still with warranty from shop)
> 
> anyway atm on cpu i have no clock almost everything is on auto (i had curve but since im having a problem i placed all on auto)
> in tearms of ram i had to set VDDG CCD/IOD to 1(at least) atm is on 1.05 or else wouldn't post (when setting freq and FCLK at same speeds)
> also in tearms of ram i set up the 16/16/16/16/34/50 timmings and tRFC to be a higher value and since i read somewhere that needs to be a multiple of tRC i placed 450
> 
> View attachment 2548496
> 
> 
> now my problem..... i "dont have any problem" in some games it keeps crashing into windows(with no errors or BSOD) when i had my old 2700x on a 3200 cl4, if this would happen i knew it was ram clock problem, but now im trying to mess a lot with it and still didnt found solution, i even tried to place everything(timings) on auto and still same problem.
> 
> in tearms of WHEA error dunno if considered as error but it appears as warming very occasionally (not when game crashes into windows):
> View attachment 2548497
> 
> 
> if someone could try help me i would appreciate it, and thank you in advance.


That's a WHEA error due to FCLK.

First thing I'd try is actually reducing your voltages a bit. Try dropping CCD to 0.975v. VDDP to 0.9v. See if you still get those WHEA.

More voltage = WHEA fixed isn't always quite right IMO.


----------



## vegetagaru

Audioboxer said:


> That's a WHEA error due to FCLK.
> 
> First thing I'd try is actually reducing your voltages a bit. Try dropping CCD to 0.975v. VDDP to 0.9v. See if you still get those WHEA.
> 
> More voltage = WHEA fixed isn't always quite right IMO.


Thank you  i will do it and report back

btw sometimes i run like 30m/1h mem test and got no whea warming but then on a daily basis i go to the logs and see them there, is there a more efficient way to test those out ?


----------



## ManniX-ITA

vegetagaru said:


> btw sometimes i run like 30m/1h mem test and got no whea warming but then on a daily basis i go to the logs and see them there, is there a more efficient way to test those out ?


y-cruncher stress test



y-cruncher - A Multi-Threaded Pi Program



Select stress test, enable all tests

There's one or two specific that usually triggers more easily WHEA but I don't remember right now...
Better to run them all for 4-12 cycles to be sure system is stable


----------



## Veii

Audioboxer said:


> That's a WHEA error due to FCLK.
> 
> First thing I'd try is actually reducing your voltages a bit. Try dropping CCD to 0.975v. VDDP to 0.9v. See if you still get those WHEA.
> 
> More voltage = WHEA fixed isn't always quite right IMO.


+1 @vegetagaru 
ProcODT was too high, it will request higher voltage
Dual rank should be fine at 34ohm
If not, even 32ohm while starting to redo voltages


----------



## vegetagaru

Veii said:


> +1 @vegetagaru
> ProcODT was too high, it will request higher voltage
> Dual rank should be fine at 34ohm
> If not, even 32ohm while starting to redo voltages


curiosity how you know it was dual rank ? xD my memorys are all a mystery to me they r 32Gb(16x2) but in label,box and thaipoon it says 16Gb(8x2) (in invoice says 32Gb)

so you say that i should also place procODT at 32/34 while also decreasing the voltages right ?


----------



## Taraquin

vegetagaru said:


> Thank you  i will do it and report back
> 
> btw sometimes i run like 30m/1h mem test and got no whea warming but then on a daily basis i go to the logs and see them there, is there a more efficient way to test those out ?


Are you using curve optimizer? I get that error when undervolt is too low, whea 18, not 19.


----------



## PJVol

Luggage said:


> Yea but anyway how do you set and stress CO in a couple of hours? I still get errors 6-7 hours into a cs run


I don't think I fully understand what your question is, but as far as i could:

there's no need to "stress CO" or whatever you meant, because i believe it makes absolutely no sense to set CO at the edge of stability values, otherwise you don't realize what the meaning of term "margin" is, in context of the curve optimizing.

ps: still got no clue what "cs" mean (Counter Strike?  )


----------



## vegetagaru

Taraquin said:


> Are you using curve optimizer? I get that error when undervolt is too low, whea 18, not 19.


i was using curve, but i removed the curve and till now no WHEA.(i didnt change yet the voltages as im "working" and cant restart yet)


----------



## drkCrix

Here is my TM5 with 25 cycles


----------



## Nighthog

I've been trying to get 5200Mts fully stable but gotten bad luck with the settings I've been trying out mostly just getting worse stability.
Only 1-3 Error for 20-25 cycle TM5 runs. But not better than that.

I tested out some of the unknown settings for the MSI X570S Unify-X and might have found a setting that has a large effect on stability but not on performance numbers. Was something named "ARdPtrInitValMP1" not seen before but it's a value 0-127 available.

Tested long @ 16 but then tested 0, was much worse... Now 31 is 99,5% stable 
A little more, only...
AUTO was fine but wanted to test Manual to see it's effects. Had more effect than I thought.


----------



## ManniX-ITA

Nighthog said:


> Was something named strangely not seen before but it's a value 0-127 available.


Is this a riddle?


----------



## Nighthog

ManniX-ITA said:


> Is this a riddle?


Edited. Had to get into BIOS to find what it was as you don't remember such a name that easy.


----------



## ManniX-ITA

Nighthog said:


> Edited. Had to get into BIOS to find what it was as you don't remember such a name that easy.


Ah okay 
Yes I've tried to mess up with it as well but looking for performance improvements, not stability.
Good to know, I'll check it out!


----------



## PJVol

Mach3.2 said:


> The power limiters options(PPT, EDC, TDC) can't exceed the limit set in the BIOS though, so you can only apply a value that's lower than what is set in the BIOS.


This is only true for the "Boost Override" setting ("max boost frequency"), which indeed can't be set above the current value in BIOS. All other limits can be set in a range that your motherboard allows (i.e. values you see in PBO menu Advanced->Motherboard).
Sorry for the illustrations, but in the light of my recent discussions I am compelled to add them as attachments.

PS: updated 7z linked in the post with fixed reporting TDC value. For some reason power table reported values below 100 as, for example, 95.000010 instead of 95.000000, so additional math.round/truncate needed.


----------



## Veii

Subut said:


> I landed this sweet overclock 🥳. many thanks to veii, its amazing how good you are at this.
> View attachment 2548470


I'm not sure what i helped, but thanks belongs to the whole community here
I personally don't like it too much

Comment on your result:








BurstChop of half tBL = (8/2) == 4 can only be used if your little loop is split between read and split between write
(chop on DDR3/4 can only be used to time between the "loops" between read or between write ~ else full tBURST time is more recommendable to elapse)
If you split it , soo in your case do not hold tFAW that open and have such low tRAS
It needs well timing between tRTP and charge loss by heat (unknown value, trial and error ~ or blind trust in tRFC mini)

And yet this does not always guarantee that it will be efficient
Either it will stop doing anything and wait till cells are recharged , or it will be equal but offsetted by long tRFC delay (in doing nothing)

Soo often "flat" timings, typical (tRAS = tRCD '2) and also typical tRC = tRP + tRAS
or rather how Arshia likes to call it , tRAS = random picked tRC minus tRP for recharge time = tRAS value
^ are more recommendable and should be your comparison baseline (as you work blind against vendor timings)

ROW access, RAS
And Collumn access, tCAS (tCL)
Are individual and independent
tRCD is important, but depends on both ~ ((RP+tRAS) time and tCAS time
 (the only reason why tRCD+tCAS+BL came up, is to factor a JEDEC specified refresh method, but there are at least 4 different one which the dimms decide by thermself up to user timing & vendor implemented "capable ! features" ~ that are not always guaranteed to exist) 
// soo while rule is correct, it's kind of missleading as RAS & CAS are independent
then how tRC refreshes (there are many types and methods of refresh, most common is tCAS before tRAS, but currently people run tRAS before CAS)
will determine the stabilty and the bandwidth

At the end, if this first section is not smooth - all falls back to tRFC, which while it elapses ~ wastes potential maximum bandwidth and everything is on hold
While it is good to keep it low, it not always is "bad" being high. As rarely there are perfect loops (neither on my side as it's still complicated)
Everyone tries to run low timings, and then nothing can stack and is focused on fullfilling read to reads , or only reads or only writes
In the hidden, by Vendor timings it takes times to recharge the cells and you don't really notice the delay that you waste / until it's actually seen as readout
Complicated~~

EDIT:
Recommendable changes,
tRDWR to 8-1, tRAS to 24 or to 29 (with tRTP drop ~ tRCD+tRTP = tRAS, tRC then tRAS+1 on SR)
If it works, fantastic - but your tRAS is too low. Minimum 1 value too low
Eh TM5 should show issues, but Write and Copy are important too ~ for aida
tWRWR_SCL covers Copy
tRDRD_SCL covers Read and Copy
They work independent of each , while low tWRWR can work - as Write to Write can be dropped , (normal tRCD WR can be dropped after all, but i wouldnt)
Read to Read are full loops, and dropping that is hard. Starting with low value will mess up primaries and tertiaries. Also visible on needed tRDWR delay
That one has to stay high , but also desync'ing / splitting SCLs between action needs to have the baseline perfect ~ this often means "slower, stable foundation"
Then you can outweight if change on SCL,change on tRAS or wherever you want to tighten it (change on tRRD_L & WTR_L)

But "just doing it" without a foundation
is not a good advice and i hope this wasn't coming over through all the presets shared
You need a stable foundation, and then maximize throughput ~ latency is just a nice extra


----------



## Nighthog

^Above with regard to tFAW

*8* RDDS with *8* tFAW is much slower than *8* RDDS with *32* tFAW.

On my system 8 RRDS with 32tFAW or 24 tFAW takes ~4m30s per TM5 1usmus_v3 cycle.
While 8/8 RRDS/tFAW takes *3 minutes more* ~7m30s.


----------



## Veii

Nighthog said:


> ^Above with regard to tFAW
> 
> *8* RDDS with *8* tFAW is much slower than *8* RDDS with *32* tFAW.
> 
> On my system 8 RRDS with 32tFAW or 24 tFAW takes ~4m30s per TM5 1usmus_v3 cycle.
> While 8/8 RRDS/tFAW takes *3 minutes more* ~7m30s.


3min more is quite some thing
For me it was faster , but "it just doesn't work out of nowhere"
It needs perfect balance ~ else tFAW ACTivates fast, quits fasts opens fast but has nothing to cover and closes fast

Before READ, data has to be copied elsewhere, because ACTivating a row - is a destructive procedure
Soo you waste more time copying "securing" data back and forth, and later recharging cells ~ before the real "read" and real "write" command queue's up
It needs very careful balance, and i don't run it anymore ~ but it worked 

tRC can be any value, if value is too low
It will be missed, and looped ~ same goes for high tFAW
can be high and loops, or can be low and be missed (tRC can not be time broken like on intel !, but tFAW can be time broken if too high)
Just low tFAW is a bit more problematic than low tRC
Well, you can't get tRC thaat low, soo doubling the value you put , wastes latency, but it's not thaat extreme

tRFC by itself, either as low as possible (to allow for potential more bandwidth, and less wasted overhead), or factoring tRC timings (if tRC is even correct to begin with)
or just high tRFC and hope vendor has implemented tRFC pausing , to queue up reads (potentially on micron, haven't seen such on b-die, but still learning)
As while tRP elapses (well tRP is the readout of the time after cells recharge and before tRAS can be used) ~ the added put in !, delay
soo while tRP elapses and while tRFC elapses ~ nothing can happen

and while tRC elapses nothing can happen, but in reality you don't notice it elapsing, unless it's missed
Then it will loop and elapse again, to queue up your read "loop"
^ soo a too high tRC will hide issues, it has to be tRP and then tRAS coverage , not lower unless exploited by something else. If not exploited, it will be missed then repeated and you waste bandwidth

EDIT:
Independent of what you put tRC on
it has to cover minimum of tRAS , and "hope" that cells are charged before tRAS can do it's job (as tRP before that never happened, or the time window was too tight before read begins again)
if cells lack charge and sensoring units will notice this ~ then tRC will loop and do nothing, because tRAS won't do anything to prevent data loss
meaning, in order for tRAS to do "anything" (there is no autocorrection, there is just a skip) ~ cells have to be charged and in ready state , well the row to be more clear

If your exploit doesn't guarantee correct charge stacking, then tRAS will never happen till cells have correct charge
and tRC will be looped as "auto-repeat" delay
same for tFAW will be looped as auto-repeat delay, till it is actually used and then time-broken if remaining delay of it is too long
Time breaking things, takes efford and any "extra action" limits maximum throughput
Soo while these things are not correct , it rarely makes sense to lower tRFC.
Lower tRFC will give potentially higher throughput and more free to use bandwidth ~ but that is irrelevant if the error is somewhere else


----------



## Veii

Ahh i want to write more to this topic, but its already soo much to digest & i'm also still learning
Anywho happy namesday to me, or something like this 

Soo about tRFC , extra advice
The nature of it, is to refresh every row, bank and generally every cell,
soo everything on the first action is fully charged ~ as normally expected (tRP should be under tRAS in the sorting but whatever)

The potential maximum throughput, depends on many actions and vendor design
Usually everything falls back to how the Vendor designed the dimm , similar to how our vendors design the board layouts. Paths and terminations
A high tRFC value, will eat from the "usable time of the dimm , till tREFI has elapsed and got repeated"
But a high tRFC value, will not do anything bad except just eat away potential usable bandwidth (lower maximum efficiency peak & so maximum bandwidth reachable by timings)
Also a high tRFC delay, will function with any low voltage ~ because dimms & cells generally lose charge. You can't count on the recharge to perfectly happen (before tRAS) soo memory controller (on dimm) will issue a "fake" read and to trigger a fake recharge of everything , cycling between rows (tRC is not ignored in tRFC but no direct "procedure" connection)
If cells wouldn't recharge the whole time, even on pure idle ~ they will lose charge because memory is volatile

Soo a high tRFC timing there, potentially will delay the usable time of memory - mid action, and from standby to action. That's all the harm it does, well and that it eats away maximum bandwidth
A low tRFC has couple of issues ~ with a single benefit of increasing "usable time of memory" and resulting in faster pulse times. Faster time-to-action, times
~ it is heat dependent, and cells will lose faster charge by heat (well facts, but it increases the chance)
~ it is noise dependent, because charging never is perfectly linear and ripple exists
~ it can be missed (not long enough), and then it loops // time-breaking or pausing doesn't exist on AM4 IMC to what i searched ~ soo dimm vendors have to have it preconfigured , aka it rarerly is a thing to begin with 

There are couple more negative sides
But in practical theory ~ it only will show "anything"
That is more bandwidth or lower latency ~ IF it is the bottleneck to begin with
Often enough, users timing loops are too tight, have autocorrection (such thing doesn't exist, but you know "repeating missed loops") in them, and lowering tRFC by 10ns will not show any amount of increased bandwidth
Soo many XOCers (to what i've seen) judge it as irrelevant , which to some extend is true ~ but as "not important", where they are wrong

I think it is important, but the balance is thin ~ and from my perspective, having it "correct" is more important, than having it "too low"
A good preset should show no error issues with low tRFC ~ like @Audioboxer is a good example
But i can not confidently say, that his preset is perfect either ~ well neither of ours is, hence i still try to learn the logic of "what is correct"
It can be that Audioboxer's preset is correct in the integrity anti-error side, but not on the "good efficiency" side ~ if there are no performance changes to be seen (haven't tested i think)

At the very end,

keep tRFC reasonable, and test how low you can push it ~ till it's not a bottleneck anymore
do not tighten down tRC too low, it will be missed and loop-repeat / you'll waste 0.3-1.2ns random access latency
maybe explore tRCD+tRTP = tRAS trick and see what is required to have higher bandwidth than tRCD*2 "normal" foundation / what is required to skip tRP added latency or lower it (no vdimm added)
test if you can make anything out of getting tWRWR_SCL lower than 2, while having tRDRD_SCL high / my board allows for 1 but 1 never posted
test what is required (without losing tight tRCD) for tWTR_S & tRRD_S to be extremely low , value 2 or 3 or even 1 / _L ones have to stay high up to DIMM-PCB
micron users in specific but everyone ~ keep tRP+tRAS = tRC , always and forever. tRAS is not ! what gives more bandwidth, it is a byproduct of the result. Never let tRC be over this value as it hides issues and loses bandwidth

Yes about that is left to figure out, including working with tRC_PAGE  // which is important for usable maximum bandwidth and important for tRFC & temperature range
* tRFC & tRAS will scale by voltage, both depend on discharge and left-charge.
Don't get blinded by such. tRAS is an individual timing and having tCAS higher, can allow for tRCD to be lower. just don't get blinded by the voltage behaviors of it~


Spoiler: Pics


































Address Bus & Data Bus (DQS - Data bus [data] strobe/clock-pulse) depend on VDIMM state & RTT's , ala termination state 
Soo while they will allow lower tCAS and tRAS values, tRCD depends on other things, which is passed Row-Address-Decoder
*tRCD* is the only value that *barely scales with VDIMM* and *the only important value with the ICs*.
tRP is before (tRAS finishes latching, finding, checking for charge, activating, using) ~ soo also voltage dependent
and all of them depend on what tCAS selects as the collumn + bank, and what tRAS selects as correct row, before anything can happen. // they can miss-select the row, it's normal
Soo this time of "search" can be influenced by tCAS and tRAS value ~ but at the end tRCD is important, then tRC to finish it off and tertiary's to trigger consecutive loops of such.
The result is what is shown as access bandwidth , as bandwidth for MCLK always exists ~ just is throttled by the active allowed time for memory to function , see DRAM refresh pic ~ a loop is often bellow 50ns, depends on tRC really.
If main "loop" for identical read identical write, or faster read interleaved write ~ is not correct, your tRFC values do not matter , as tRC "package" is far smaller than tRFC time in between


----------



## PJVol

Veii said:


> Comment on your result:


Wondering why pics you attached are in that strange format "AVIF"? Some image processing software refuse to even load that.


----------



## Kha

Veii said:


> Anywho happy namesday to me, or something like this


Well, happy namesday then. Didn't know you're a Val )


----------



## Veii

PJVol said:


> Wondering why pics you attached are in that strange format "AVIF"? Some image processing software refuse to even load that.


That's OCN + Cloudflare for you
Whatever they decided to use, it's not optimally implemented as you have big linebreaks before the images and between the images
Sources are little screenshots of couple presentation papers. Notes for me, but fitted the post
Someday i'll have to make an easy to read topic about this, but still learning. Information is too split and mostly misleading, as many are just expecting one type of operation
Dimms ~ on tRC can refresh and stack refresh at least in 4+ different methods. Timings never are "only one way" correct. So are not rules either.

LPDDR4 utilizes tRFC pausing and another type of stacked refresh. I think DDR4 can use bank interleaving trick but i don't think it can do per-bank refresh (bypassing tRFC penalty) ~ it's complicated. Still researching & trying to match it with experience data
Will take a bit of time, then tRFC mini can get an update and be called "final" ~ we will see
https://medium.com/@mitali.soni04/decoding-dram-timings-part-ii-9541e0f72aca
Miss Mitali Sony, now works for Nvidia and helps the design of mobile DRAM & GPU VRAM bandwidth efficiency
https://users.ece.cmu.edu/~omutlu/pub/dram-access-refresh-parallelization_hpca14.pdf
^ not everything in this paper is usable for us, but DIMM will switch operations if it recognizes support for it ~ needs exploration
_~learning~_


Kha said:


> Well, happy namesday then. Didn't know you're a Val )


Valentines day, yes 
ty~


----------



## PJVol

Veii said:


> That's OCN + Cloudflare for you
> Whatever they decided to use, it's not optimally implemented


Yeah, it's strange. Mobile browser offered me to save pic as jpeg or png, whereas the pc firefox - some weird AVIF (wth is avif?  )


----------



## blodflekk

Audioboxer said:


> View attachment 2548476
> 
> 
> Just a reminder for how long it can take for a core to spit out an error lol
> 
> Relevant to memory because while TM5 can behave weird with Windows 11 at times when it comes to core boosting, an unstable curve also 100% can lead to TM5 timeouts.



Yes it takes a frustratingly long time. I ran corecycler for 10 hours last night, passed with no errors. Load up a game and one hour in and I'm getting an auto restart.


----------



## Veii

Veii said:


> tRCD is important, but depends on both ~ ((RP+tRAS) time and tCAS time
> (the only reason why tRCD+tCAS+BL came up, is to factor a JEDEC specified refresh method, but there are at least 4 different one which the dimms decide by thermself up to user timing & vendor implemented "capable ! features" ~ that are not always guaranteed to exist)
> // soo while rule is correct, it's kind of missleading as RAS & CAS are independent
> then how tRC refreshes (there are many types and methods of refresh, most common is tCAS before tRAS, but currently people run tRAS before CAS)
> will determine the stability and the bandwidth










Proof of visual concept ~ and to strengthen ongoing work & wording
Yet not even close to stable. No VDIMM change ~ same 1.65v
tRCD 13 can function if tCL and tRAS are delayed
It's unstable and i've been experimenting recently with more things

But "it can post"
it only can not post lower than tCL 15 ^^''
We will figure it out, there is still a lot to do ~ although DDR5 AM5 boards are soon to be released


----------



## dk10438

blodflekk said:


> Yes it takes a frustratingly long time. I ran corecycler for 10 hours last night, passed with no errors. Load up a game and one hour in and I'm getting an auto restart.


so pardon my ignorance on this topic. I'm new to memory OC'ing but why does everyone recommend multiple tests with TM5, HCI Memtest, memtest86, etc???? Seems like gaming stresses out the memory more and gets the computer hotter where memory is going to start showing instability. All these stress tests take a lot of time and aren't 100% reliable...


----------



## blodflekk

dk10438 said:


> so pardon my ignorance on this topic. I'm new to memory OC'ing but why does everyone recommend multiple tests with TM5, HCI Memtest, memtest86, etc???? Seems like gaming stresses out the memory more and gets the computer hotter where memory is going to start showing instability. All these stress tests take a lot of time and aren't 100% reliable...


I was speaking on CO values for PBO not memory OC. Running a game without crashes doesn't mean your memory is stable and isn't producing errors. I also find the mem OC needs to be EXTREMELY unstable to cause a game crash. I don't feel confident in any mem OC unless it can pass 1000% HCI memtest


----------



## Veii

dk10438 said:


> so pardon my ignorance on this topic. I'm new to memory OC'ing but why does everyone recommend multiple tests with TM5, HCI Memtest, memtest86, etc???? Seems like gaming stresses out the memory more and gets the computer hotter where memory is going to start showing instability. All these stress tests take a lot of time and aren't 100% reliable...


TM5 anta's test, has high voltage error flaws, but is a correctly written test config for "normal low voltage memory or XMP"
1usmus test is accurate, but has slight flaw to miss some errors ~ yet TM5 is very low IPC and rarely ever fails by CPU reasons, also is very fast
HCI, Karhu ~ will error also on CPU issues , because memOC destabilizes CPU OC ~ soo can missreport , yet is a good "2nd stage" check without having oddness in userprofile code issues (often requirements are 10 000% which is 6-8 hours not 2-4h)

Gaming does not stress memory, gaming does stress heat
GPUs are 300+ Watt packages that dump their air in the case
memory is always forgotten to cool down and always ignored, soo gaming does not show memory instability, but heat/airflow instability& issues

TM5 is just fast and we have some "kind of usable" error-reason detector
HCI, Karhu are 2nd stage check but take minimum twice as long
Gaming is irrelevant , kinda

Memory is always autocorrecting itself (the platform corrects memory errors, ryzen does error-correction)
You need to test memory over 1hour to have any reasonable heat-testing capabilities, because memory are capacitors and they lose charge faster by heat. Soo timings will be incorrect when charge is lost
Reaching thermal equilibrium takes around 40+ minutes up to room and case and watercooling often 2-3 hours, but usually 40-45minutes

Then comes tREFi which is fixed for us on AMD (good, soo everyone is consistent) ~ but will also fail faster on lower thermals.
Meaning test has to be long to even show any signs of tRFC or tREFI issues. Hence such only refresh very very late and rounding issues show minimum after 1h if not 2h ~ up to capacity
Memory is generally annoying to test, and shows it's timing out errors only very late
Soo different tools are not a bad idea ~ but not always required
It's more, that ryzen CPU stability will suffer by memOC ~ soo more tools need to be used to confirm again stability


----------



## PJVol

blodflekk said:


> Yes it takes a frustratingly long time. I ran corecycler for 10 hours last night, passed with no errors. Load up a game and one hour in and I'm getting an auto restart.


Yeah, never could understand what makes people wasting so much time with all these "corecyclers" or some other stupid "cycler". Be it just misunderstanding of the basic principles of how avfs implementation in Zen works or something else, I'm still in the dark.


----------



## MrHoof

Veii said:


> View attachment 2548570
> 
> Proof of visual concept ~ and to strengthen ongoing work & wording
> Yet not even close to stable. No VDIMM change ~ same 1.65v
> tRCD 13 can function if tCL and tRAS are delayed
> It's unstable and i've been experimenting recently with more things


Well booting isnt the problem but for me its 12/2 errors 0/6 i can get rid off with more voltage.
This is at 1.55v


Spoiler: tRCDRD13














Also doing some low soc testing and so far seems stable. Any recomandations on what tests to run?
Geekbench5 shows no diffrence and ycrunsher 1 1/2h stable so far.


Spoiler: soc 1.05











'


----------



## Audioboxer

Veii said:


> Ahh i want to write more to this topic, but its already soo much to digest & i'm also still learning
> Anywho happy namesday to me, or something like this
> 
> Soo about tRFC , extra advice
> The nature of it, is to refresh every row, bank and generally every cell,
> soo everything on the first action is fully charged ~ as normally expected (tRP should be under tRAS in the sorting but whatever)
> 
> The potential maximum throughput, depends on many actions and vendor design
> Usually everything falls back to how the Vendor designed the dimm , similar to how our vendors design the board layouts. Paths and terminations
> A high tRFC value, will eat from the "usable time of the dimm , till tREFI has elapsed and got repeated"
> But a high tRFC value, will not do anything bad except just eat away potential usable bandwidth (lower maximum efficiency peak & so maximum bandwidth reachable by timings)
> Also a high tRFC delay, will function with any low voltage ~ because dimms & cells generally lose charge. You can't count on the recharge to perfectly happen (before tRAS) soo memory controller (on dimm) will issue a "fake" read and to trigger a fake recharge of everything , cycling between rows (tRC is not ignored in tRFC but no direct "procedure" connection)
> If cells wouldn't recharge the whole time, even on pure idle ~ they will lose charge because memory is volatile
> 
> Soo a high tRFC timing there, potentially will delay the usable time of memory - mid action, and from standby to action. That's all the harm it does, well and that it eats away maximum bandwidth
> A low tRFC has couple of issues ~ with a single benefit of increasing "usable time of memory" and resulting in faster pulse times. Faster time-to-action, times
> ~ it is heat dependent, and cells will lose faster charge by heat (well facts, but it increases the chance)
> ~ it is noise dependent, because charging never is perfectly linear and ripple exists
> ~ it can be missed (not long enough), and then it loops // time-breaking or pausing doesn't exist on AM4 IMC to what i searched ~ soo dimm vendors have to have it preconfigured , aka it rarerly is a thing to begin with
> 
> There are couple more negative sides
> But in practical theory ~ it only will show "anything"
> That is more bandwidth or lower latency ~ IF it is the bottleneck to begin with
> Often enough, users timing loops are too tight, have autocorrection (such thing doesn't exist, but you know "repeating missed loops") in them, and lowering tRFC by 10ns will not show any amount of increased bandwidth
> Soo many XOCers (to what i've seen) judge it as irrelevant , which to some extend is true ~ but as "not important", where they are wrong
> 
> I think it is important, but the balance is thin ~ and from my perspective, having it "correct" is more important, than having it "too low"
> A good preset should show no error issues with low tRFC ~ like @Audioboxer is a good example
> But i can not confidently say, that his preset is perfect either ~ well neither of ours is, hence i still try to learn the logic of "what is correct"
> It can be that Audioboxer's preset is correct in the integrity anti-error side, but not on the "good efficiency" side ~ if there are no performance changes to be seen (haven't tested i think)
> 
> At the very end,
> 
> keep tRFC reasonable, and test how low you can push it ~ till it's not a bottleneck anymore
> do not tighten down tRC too low, it will be missed and loop-repeat / you'll waste 0.3-1.2ns random access latency
> maybe explore tRCD+tRTP = tRAS trick and see what is required to have higher bandwidth than tRCD*2 "normal" foundation / what is required to skip tRP added latency or lower it (no vdimm added)
> test if you can make anything out of getting tWRWR_SCL lower than 2, while having tRDRD_SCL high / my board allows for 1 but 1 never posted
> test what is required (without losing tight tRCD) for tWTR_S & tRRD_S to be extremely low , value 2 or 3 or even 1 / _L ones have to stay high up to DIMM-PCB
> micron users in specific but everyone ~ keep tRP+tRAS = tRC , always and forever. tRAS is not ! what gives more bandwidth, it is a byproduct of the result. Never let tRC be over this value as it hides issues and loses bandwidth
> 
> Yes about that is left to figure out, including working with tRC_PAGE  // which is important for usable maximum bandwidth and important for tRFC & temperature range
> * tRFC & tRAS will scale by voltage, both depend on discharge and left-charge.
> Don't get blinded by such. tRAS is an individual timing and having tCAS higher, can allow for tRCD to be lower. just don't get blinded by the voltage behaviors of it~
> 
> 
> Spoiler: Pics
> 
> 
> 
> 
> View attachment 2548561
> View attachment 2548562
> 
> View attachment 2548563
> View attachment 2548565
> 
> Address Bus & Data Bus (DQS - Data bus [data] strobe/clock-pulse) depend on VDIMM state & RTT's , ala termination state
> Soo while they will allow lower tCAS and tRAS values, tRCD depends on other things, which is passed Row-Address-Decoder
> *tRCD* is the only value that *barely scales with VDIMM* and *the only important value with the ICs*.
> tRP is before (tRAS finishes latching, finding, checking for charge, activating, using) ~ soo also voltage dependent
> and all of them depend on what tCAS selects as the collumn + bank, and what tRAS selects as correct row, before anything can happen. // they can miss-select the row, it's normal
> Soo this time of "search" can be influenced by tCAS and tRAS value ~ but at the end tRCD is important, then tRC to finish it off and tertiary's to trigger consecutive loops of such.
> The result is what is shown as access bandwidth , as bandwidth for MCLK always exists ~ just is throttled by the active allowed time for memory to function , see DRAM refresh pic ~ a loop is often bellow 50ns, depends on tRC really.
> If main "loop" for identical read identical write, or faster read interleaved write ~ is not correct, your tRFC values do not matter , as tRC "package" is far smaller than tRFC time in between


My memory has been performing well but I'll no doubt go back to it soon for some more testing, benchmarks and I'll look more closely at tRFC.

Working heavily on the CPU/PBO right now!


----------



## Luggage

PJVol said:


> I don't think I fully understand what your question is, but as far as i could:
> 
> there's no need to "stress CO" or whatever you meant, because i believe it makes absolutely no sense to set CO at the edge of stability values, otherwise you don't realize what the meaning of term "margin" is, in context of the curve optimizing.
> 
> ps: still got no clue what "cs" mean (Counter Strike?  )


That still doesn't really give me a clue as to how you figure out a curve - I'd say even less than before.


ah - thats because I spell it wrong >_>
coresycler
CoreCycler is CC of course...









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


You VSOC is too low, raise it at least to 1.15V. Not necessarily, my VSOC is absolutely fine on AUTO at 3800. This is 1.1v.




www.overclock.net


----------



## Mach3.2

PJVol said:


> This is only true for the "Boost Override" setting ("max boost frequency"), which indeed can't be set above the current value in BIOS. All other limits can be set in a range that your motherboard allows (i.e. values you see in PBO menu Advanced->Motherboard).
> Sorry for the illustrations, but in the light of my recent discussions I am compelled to add them as attachments.
> 
> PS: updated 7z linked in the post with fixed reporting TDC value. For some reason power table reported values below 100 as, for example, 95.000010 instead of 95.000000, so additional math.round/truncate needed.
> View attachment 2548566


Weird, I can't set anything above mobo limits on my setup.

I'm still on 1.2.0.3b SMU 56.53.

PBO limits in BIOS are set to manual; PPT: 145W, TDC: 105A, EDC: 180A


----------



## Taraquin

Veii said:


> TM5 anta's test, has high voltage error flaws, but is a correctly written test config for "normal low voltage memory or XMP"
> 1usmus test is accurate, but has slight flaw to miss some errors ~ yet TM5 is very low IPC and rarely ever fails by CPU reasons, also is very fast
> HCI, Karhu ~ will error also on CPU issues , because memOC destabilizes CPU OC ~ soo can missreport , yet is a good "2nd stage" check without having oddness in userprofile code issues (often requirements are 10 000% which is 6-8 hours not 2-4h)
> 
> Gaming does not stress memory, gaming does stress heat
> GPUs are 300+ Watt packages that dump their air in the case
> memory is always forgotten to cool down and always ignored, soo gaming does not show memory instability, but heat/airflow instability& issues
> 
> TM5 is just fast and we have some "kind of usable" error-reason detector
> HCI, Karhu are 2nd stage check but take minimum twice as long
> Gaming is irrelevant , kinda
> 
> Memory is always autocorrecting itself (the platform corrects memory errors, ryzen does error-correction)
> You need to test memory over 1hour to have any reasonable heat-testing capabilities, because memory are capacitors and they lose charge faster by heat. Soo timings will be incorrect when charge is lost
> Reaching thermal equilibrium takes around 40+ minutes up to room and case and watercooling often 2-3 hours, but usually 40-45minutes
> 
> Then comes tREFi which is fixed for us on AMD (good, soo everyone is consistent) ~ but will also fail faster on lower thermals.
> Meaning test has to be long to even show any signs of tRFC or tREFI issues. Hence such only refresh very very late and rounding issues show minimum after 1h if not 2h ~ up to capacity
> Memory is generally annoying to test, and shows it's timing out errors only very late
> Soo different tools are not a bad idea ~ but not always required
> It's more, that ryzen CPU stability will suffer by memOC ~ soo more tools need to be used to confirm again stability


Anta's 'rules' seemed to work quite well, but a few 'rulebreaking' tweaks often improved performance in certain cases like running WR/RTP below, or RAS below. Some of the rules were impossible to implement (wtrl below 9 at 4000 is no go). The rfc 8 steppings for 8gb sticks and 16 for 16gb sticks seems to work well, but dunno if there may be further improvements there.


----------



## Taraquin

Not DDR4 specific, but after tuning fan curve on the D15-cooler I now get same CB23 score with 4000cl16 and 3800cl15. As long as temp don`t go over 70-71C corespeed is 4.6-4.625GHz at 76W PPT. Using 4000 temp is slightly higher before adjusting curve, and temp often rose to 75C which drops allcore speed by 50MHz. I thought it was the CPU-budget due to higher IO-die usage, but if temp is normalized corespeed is identical on both 4000 and 3800


----------



## Luggage

Taraquin said:


> Not DDR4 specific, but after tuning fan curve on the D15-cooler I now get same CB23 score with 4000cl16 and 3800cl15. As long as temp don`t go over 70-71C corespeed is 4.6-4.625GHz at 76W PPT. Using 4000 temp is slightly higher before adjusting curve, and temp often rose to 75C which drops allcore speed by 50MHz. I thought it was the CPU-budget due to higher IO-die usage, but if temp is normalized corespeed is identical on both 4000 and 3800


What vsoc for 3800/4000?


----------



## vegetagaru

Audioboxer said:


> That's a WHEA error due to FCLK.
> 
> First thing I'd try is actually reducing your voltages a bit. Try dropping CCD to 0.975v. VDDP to 0.9v. See if you still get those WHEA.
> 
> More voltage = WHEA fixed isn't always quite right IMO.


so i changed the voltages and also droped the procODT to 32 i ran y-cruncher and at the end of the BBP test i started having WHEA:









went to windows event viewer and was the same as before event ID: 19 / Processor APIC ID: 0

Update: So i droped a bit more the CCD to 0.91 and ran one complete iteration and till now no errors:









i will do at least 4-6 and report back


----------



## Taraquin

Luggage said:


> What vsoc for 3800/4000?


soc\iod 3800 1070mv\980mv VDD18 1.8v
soc\iod 4000 1120mv\1040mv VDD18 1.88v


----------



## Veii

vegetagaru said:


> so i changed the voltages and also droped the procODT to 32 i ran y-cruncher and at the end of the BBP test i started having WHEA:
> View attachment 2548628
> 
> 
> went to windows event viewer and was the same as before event ID: 19 / Processor APIC ID: 0


Maybe yours is one of these LCLK buggy samples that spikes to 2600 FCLK randomly

Rename, extract and run this
Then probably record your screen
LCLK DPM value will change if you move your mouse and if you stay idle.
Record it with your phone or DSLR , as "allcore load" on screen recording software will influence it








If you see something like this, you have a messed up sample
Fixable, but it's an unique one. Anywho ~ this will trigger WHEA #19 even at 1800 FCLK. That's some of the indicators.
So far had two 5900X that behaved like this, but one jumped to 900MHz LCLK and 2600 FCLK 








* gif of gif, as host took it down
After couple of changes, it's still buggy
But far more reasonable within margin ~ the rest did fix increasing VDD18
But you should not increase this voltage (or VTT called) , as it can indeed do harm to the CPU

Ah found the old extreme example







Will never be forgotten ~ AMD 
Get your stuff together and stop ignoring DPM issues

2600 peak = B0 sample with B2 characteristics [BG 2139] & +300 fMAX (capable)
2100 peak = B2 sample pure, but still a mess on 1203C [BG 2143]
* different samples also noticeable on different disabled cores (erased & forced to idle state, not really disabled)


----------



## vegetagaru

Veii said:


> Maybe yours is one of these LCLK buggy samples that spikes to 2600 FCLK randomly
> 
> Rename, extract and run this
> Then probably record your screen
> LCLK DPM value will change if you move your mouse and if you stay idle.
> Record it with your phone or DSLR , as "allcore load" on screen recording software will influence it
> View attachment 2548633
> 
> If you see something like this, you have a messed up sample
> Fixable, but it's an unique one. Anywho ~ this will trigger WHEA #19 even at 1800 FCLK. That's some of the indicators.
> So far had two 5900X that behaved like this, but one jumped to 900MHz LCLK and 2600 FCLK


i did a edit on my comment, but i will do this anyway 

edit: i tried and made a short video (didn't know how much time was supposed to do)
VID_20220215_092235.mp4 (you need to download to see full quality i think)


----------



## Veii

vegetagaru said:


> i did a edit on my comment, but i will do this anyway
> 
> edit: i tried and made a short video (didn't know how much time was supposed to do)
> VID_20220215_092235.mp4 (you need to download to see full quality i think)


Not buggy, just slightly unstable at 1900 FCLK
That's resolvable for you

ManniX-ITA explained it well
Well all advice's where good.
Use y-cruncher , key combination 1-7-0 soo it tests all tests, 4 loops = 72min minimum for core stability
Longer is better but it will generate a lot of heat and is a bit more extreme than p95

You can start with low voltages, maybe increase the VDD18 voltage to 1.86v (up to 2v is fine, but i wouldn't go over 1.96 at absolute worst)
* our ASRock boards default that to 1.83v not 1.8v
Then be sure to pass all tests. After that is done, grab OCCT and run it on AVX2 EXTREME preset. That one will take 1h for the free version (that's enough)
It shouldn't fail ~ but if any of both fail, it can be unstable memory too ~ depends on what it fails 

Keep playing with voltages and keep a minimum of 40mV between each of the voltages
Dual CCD samples seem to like +60mV distance as minimum (between IOD & SOC)
But in general, cLDO_VDDP + 40mV = VDDG CCD , or cLDO_VDDP can match VDDG CCD (but there is no need to increase cLDO_VDDP beyond 900mV on this low MCLK)
IOD to SOC then have to keep minimum of 40mV, often 60mV
AMD max overclocking voltage here where some ranges before, they still are a thing - but you can need bit more or bit less than recommended
* that "intention bugs on 2133 FCLK" where plain simple package throttle, new annoyance introduced, not noticed by only having 1 month the sample

Just so you aren't fearing too much the voltages 
People on reddit for example are too fast to create panic


----------



## vegetagaru

Veii said:


> Not buggy, just slightly unstable at 1900 FCLK
> That's resolvable for you
> 
> ManniX-ITA explained it well
> Well all advice's where good.
> Use y-cruncher , key combination 1-7-0 soo it tests all tests, 4 loops = 72min minimum for core stability
> Longer is better but it will generate a lot of heat and is a bit more extreme than p95
> 
> You can start with low voltages, maybe increase the VDD18 voltage to 1.86v (up to 2v is fine, but i wouldn't go over 1.96 at absolute worst)
> * our ASRock boards default that to 1.83v not 1.8v
> Then be sure to pass all tests. After that is done, grab OCCT and run it on AVX2 EXTREME preset. That one will take 1h for the free version (that's enough)
> It shouldn't fail ~ but if any of both fail, it can be unstable memory too ~ depends on what it fails
> 
> Keep playing with voltages and keep a minimum of 40mV between each of the voltages
> Dual CCD samples seem to like +60mV distance as minimum (between IOD & SOC)
> But in general, cLDO_VDDP + 40mV = VDDG CCD , or cLDO_VDDP can match VDDG CCD
> IOD to SOC then have to keep minimum of 40mV, often 60mV
> AMD max overclocking voltage here where some ranges before, they still are a thing - but you can need bit more or bit less than recommended
> * that "intention bugs on 2133 FCLK" where plain simple package throttle, new annoyance introduced, not noticed by only having 1 month the sample
> 
> Just so you aren't fearing too much the voltages
> People on reddit for example are too fast to create panic


thank you very much, dunno if i will make it today but as soon as possible i will try those and report back


----------



## vegetagaru

Veii said:


> Not buggy, just slightly unstable at 1900 FCLK
> That's resolvable for you
> 
> ManniX-ITA explained it well
> Well all advice's where good.
> Use y-cruncher , key combination 1-7-0 soo it tests all tests, 4 loops = 72min minimum for core stability
> Longer is better but it will generate a lot of heat and is a bit more extreme than p95
> 
> You can start with low voltages, maybe increase the VDD18 voltage to 1.86v (up to 2v is fine, but i wouldn't go over 1.96 at absolute worst)
> * our ASRock boards default that to 1.83v not 1.8v
> Then be sure to pass all tests. After that is done, grab OCCT and run it on AVX2 EXTREME preset. That one will take 1h for the free version (that's enough)
> It shouldn't fail ~ but if any of both fail, it can be unstable memory too ~ depends on what it fails
> 
> Keep playing with voltages and keep a minimum of 40mV between each of the voltages
> Dual CCD samples seem to like +60mV distance as minimum (between IOD & SOC)
> But in general, cLDO_VDDP + 40mV = VDDG CCD , or cLDO_VDDP can match VDDG CCD (but there is no need to increase cLDO_VDDP beyond 900mV on this low MCLK)
> IOD to SOC then have to keep minimum of 40mV, often 60mV
> AMD max overclocking voltage here where some ranges before, they still are a thing - but you can need bit more or bit less than recommended
> * that "intention bugs on 2133 FCLK" where plain simple package throttle, new annoyance introduced, not noticed by only having 1 month the sample
> 
> Just so you aren't fearing too much the voltages
> People on reddit for example are too fast to create panic


btw on asus the VDD18 its called "1.8V PLL Voltage" no ? or its a different thing ? if yes the default value is indeed 1.83 aswell


----------



## Taraquin

vegetagaru said:


> btw on asus the VDD18 its called "1.8V PLL Voltage" no ? or its a different thing ? if yes the default value is indeed 1.83 aswell


Check scaling when you begin to mess with that voltage. At 1900 fclk I've tried 1.76, 1.8, 1.84 and linpack/aida is within margin of error. At 2000fclk I suddenly see scaling in linpack where I get 1% better result with 1.84 and 1.92 vs 1.8, and 2% better with 1.88v. Above or below scaling is negative.


----------



## Audioboxer

Nighthog said:


> I've been trying to get 5200Mts fully stable but gotten bad luck with the settings I've been trying out mostly just getting worse stability.
> Only 1-3 Error for 20-25 cycle TM5 runs. But not better than that.
> 
> I tested out some of the unknown settings for the MSI X570S Unify-X and might have found a setting that has a large effect on stability but not on performance numbers. Was something named "ARdPtrInitValMP1" not seen before but it's a value 0-127 available.
> 
> Tested long @ 16 but then tested 0, was much worse... Now 31 is 99,5% stable
> A little more, only...
> AUTO was fine but wanted to test Manual to see it's effects. Had more effect than I thought.


I've got a ARdPtrInitValMP1 and ARdPtrInitValMP0 setting, both on AUTO. I presume everyone will have them. Firing random numbers into ARdPtrInitValMP1










Longest tRCDRD 13 has ran for me, but I'm going to guess it's just placebo and I was simply lucky 13 went a few minutes rather than 1 or 2 minutes.

Would be good if anyone knows what ARdPtrInitValMP does.


----------



## PJVol

Mach3.2 said:


> Weird, I can't set anything above mobo limits on my setup.
> 
> I'm still on 1.2.0.3b SMU 56.53.
> 
> PBO limits in BIOS are set to manual; PPT: 145W, TDC: 105A, EDC: 180A


Yeah, weird indeed ))
Can you try to follow these steps:

boot with the above limits set in a bios
run Veii's tool (how did he managed to get that? I'm sure he stole it from some clumsy dumb asus employee)
go to CPU -> AMD (new window should open)
go to SMN mailbox tab there
enter values exactly as in the screenshot
push the top "Apply" button
and check for the current TDC limit again.









Hard to beleive this is something particular SMU version related, since I've tested this on both AGESAs 1203b (or c, what a fkn mess with all these 56.52 / 56.53) and 1205 (56.65)


----------



## TMavica

Audioboxer said:


> View attachment 2548476
> 
> 
> Just a reminder for how long it can take for a core to spit out an error lol
> 
> Relevant to memory because while TM5 can behave weird with Windows 11 at times when it comes to core boosting, an unstable curve also 100% can lead to TM5 timeouts.


I have ran the test in 10 cycles, there is no error. Then I tried to increase the CO per core more, still got tm5 timeout randomly, really dont know whats the cause…TM5 normally free up 26000 mb then do the next cycles, if timeout happened, it free up to max, then cycle stopped


----------



## nick name

What is Tool1007?






Tool1007.7z







drive.google.com


----------



## Audioboxer

TMavica said:


> I have ran the test in 10 cycles, there is no error. Then I tried to increase the CO per core more, still got tm5 timeout randomly, really dont know whats the cause…TM5 normally free up 26000 mb then do the next cycles, if timeout happened, it free up to max, then cycle stopped


Timeouts tend to be one of the following IMO


Unfortunate jank with Windows 11/chipset drivers/AGESA (should be rare if you are stable and not using broken chipset drivers)
Memory instability (usually powerdown issues (resistances/tCKE), minor voltage issues or tRFC ~ not serious enough to trip an error code, very minor but still unstable)
CPU instability (a core is crashing, so CO settings)


----------



## TMavica

Audioboxer said:


> Timeouts tend to be one of the following IMO
> 
> 
> Unfortunate jank with Windows 11/chipset drivers/AGESA (should be rare if you are stable and not using broken chipset drivers)
> Memory instability (usually powerdown issues (resistances/tCKE), minor voltage issues or tRFC ~ not serious enough to trip an error code, very minor but still unstable)
> CPU instability (a core is crashing, so CO settings)


if core crashing, there should have some whea i think? i find nth


----------



## Veii

PJVol said:


> run Veii's tool (how did he managed to get that? I'm sure he stole it from some clumsy dumb asus employee)


Hahaha
But jokes aside, it doesn't fit to me stealing anything. . .
The only fault to blame me, is linking it here to be public
Soo the new update is restricted and has couple hardware checks, which only are now for the crosshair lineup
~ although tool works on a lot of asus boards. The ProArt series included

Tool1007 was made by i think Shamino and the Asus XOC team
It was published on HWBot and just accidentally worked on many board's.
XOC team was slightly careless (in a good sense) and forgot to lock it down (as it usually does) 

It seems like it got too much attention and the version would need some ghidra decompile, as RoG-XOC only team prefers their expensive boards
Eh, not my soup to eat 🤭 ~ just it could be a more open shared dinner

But anywho,
I don't deserve credit for this tool 
Shamino and remain team, are far more talented and can create thing's out of thin air
I can't even javascript code~


----------



## TMavica

Audioboxer said:


> Timeouts tend to be one of the following IMO
> 
> 
> Unfortunate jank with Windows 11/chipset drivers/AGESA (should be rare if you are stable and not using broken chipset drivers)
> Memory instability (usually powerdown issues (resistances/tCKE), minor voltage issues or tRFC ~ not serious enough to trip an error code, very minor but still unstable)
> CPU instability (a core is crashing, so CO settings)


Thats what I did, no error in Karku test, just random timeout in TM5
SOC 1.125
VDIMM 1.55


----------



## Audioboxer

TMavica said:


> Thats what I did, no error in Karku test, just random timeout in TM5
> SOC 1.125
> VDIMM 1.55
> 
> View attachment 2548655


Karhu needs a lot longer than that with DR, like around 9,000~10,000%. In all my testing Karhu doesn't 'time out', it will just eventually error.

TM5 is what times out, and in this case it seems to be quicker than Karhu for finding such errors. I've had Karhu error out after like 4~5 hours due to the described issues.

Given what you are facing, TM5 25 cycles first. If it ain't passing there is no point using Karhu.

A quick way to look at the CPU is disable your curve, disable PBO and run CPU on default.


----------



## blodflekk

Taraquin said:


> Anta's 'rules' seemed to work quite well, but a few 'rulebreaking' tweaks often improved performance in certain cases like running WR/RTP below, or RAS below. Some of the rules were impossible to implement (wtrl below 9 at 4000 is no go). The rfc 8 steppings for 8gb sticks and 16 for 16gb sticks seems to work well, but dunno if there may be further improvements there.


Are Anta's rules written anywhere? Has he done a guide? I'd love to read it.


----------



## Taraquin

blodflekk said:


> Are Anta's rules written anywhere? Has he done a guide? I'd love to read it.


It's a post here a few months ago, can write what I remember:
Cl=cwl(-1 if odd cl) 
Rcdrd=rp
Ras+rp=rc
Wr=2xrtp
Wr=cl
Wtrs=3 or 4
Wtrl=rtp or lower
Rrds/l=4 and faw=4x rrds
Rfc=divideable by 8 for 8gb stick, by 16 for 16gb sticks
Scls=2 or 4

He has rules for others aswell, but don't remember  I can't run wtrl rule, but others work. Lower wr/rtp works a bit better for me.


----------



## Mach3.2

PJVol said:


> Yeah, weird indeed ))
> Can you try to follow these steps:
> 
> boot with the above limits set in a bios
> run Veii's tool (how did he managed to get that? I'm sure he stole it from some clumsy dumb asus employee)
> go to CPU -> AMD (new window should open)
> go to SMN mailbox tab there
> enter values exactly as in the screenshot
> push the top "Apply" button
> and check for the current TDC limit again.
> 
> View attachment 2548647
> 
> 
> Hard to beleive this is something particular SMU version related, since I've tested this on both AGESAs 1203b (or c, what a fkn mess with all these 56.52 / 56.53) and 1205 (56.65)


Nope, no dice. Power limits still refuses to budge.


Spoiler: picture dump


----------



## Veii

Mach3.2 said:


> Nope, no dice. Power limits still refuses to budge.
> 
> 
> Spoiler: picture dump
> 
> 
> 
> 
> View attachment 2548663
> 
> 
> View attachment 2548664
> 
> 
> View attachment 2548665
> 
> 
> View attachment 2548666


Reason likely is, because MSI has translated and linked AMD CBS options
they are lower level and have higher priority, than AMD OVERCLOCKING ones
Tool only changes AMD OVERCLOCKING limits, but if they are lower than what it can set ~ they will never stick

Potentially you should have under the normal advanced menu (not OC menu) a normal AMD OVERCLOCKING
There free up the limiters


----------



## Mach3.2

Veii said:


> Reason likely is, because MSI has translated and linked AMD CBS options
> they are lower level and have higher priority, than AMD OVERCLOCKING ones
> Tool only changes AMD OVERCLOCKING limits, but if they are lower than what it can set ~ they will never stick
> 
> Potentially you should have under the normal advanced menu (not OC menu) a normal AMD OVERCLOCKING
> There free up the limiters


This make sense. I'll try again tomorrow when I'm back from school.


----------



## PJVol

Veii said:


> Reason likely is, because MSI has translated and linked AMD CBS options
> they are lower level and have higher priority, than AMD OVERCLOCKING ones


I can't help thinking that something is different in a way how msi and other vendors firmware behave, especially after @ManniX-ITA experience with a 1205 agesa (gonna post some observations with msi a bit later)
Can you please check, do this limitation exist on asus board as well? I mean does limits apply on proart as they do on asrock boards?
Anyone with the Asus or GB boards here - your feedback would be helpful as well.


----------



## Luggage

PJVol said:


> I can't help thinking that something is different in a way how msi and other vendors firmware behave, especially after @ManniX-ITA experience with a 1205 agesa (gonna post some observations with msi a bit later)
> Can you please check, do this limitation exist on asus board as well? I mean does limits apply on proart as they do on asrock boards?
> Anyone with the Asus or GB boards here - your feedback would be helpful as well.


On MSI x570 unify - yea I can set PBO limits up to what I've set in bios but not above and guess if you don't set them above they will top out at mb limits.
With edc 700 in bios I can use PBO2 tuner up to that limit but not above.



Code:


Aida L3
140a 649 648 708 10.5
170a 708 656 693 10.4
220a 701 628 648 10.4
350a 743 737 701 10.4
400a 748 744 718 10.4
500a 746 750 712 10.4
700a 742 753 731 10.2
800a wont set

Run to run variance is big (+-30ish) for write, copy, read but latency is +-0.1


----------



## Kha

Somebody please explain this:

My 5900x does -15 on all cores IF I go trfc > 450 @ stock 1.35 vdim.

If I lower trfc, core 8 fails cycler. However if I raise vdim, is perfectly fine (stability also happens if I go -10 on it).

Dafuq is this ?!


----------



## MrHoof

PJVol said:


> Can you please check, do this limitation exist on asus board as well? I mean does limits apply on proart as they do on asrock boards?
> Anyone with the Asus or GB boards here - your feedback would be helpful as well.


Works fine on my asus x570i. BIOS set 200 EDC resulted in karhu pulling 155A used your tool to limit to 145A.








edit: nvm didnt read all the comments gimme a sec.








How u confirm they got set? Cause even at 190A board limit it will max pull 160A.


----------



## PJVol

MrHoof said:


> comments


To check if just entered values applied, you don't need to run hwinfo or whatever. Just restart tool and look at the limits tab. The tool read actual PBO limits from SMU, not the ones you've entered.


----------



## MrHoof

Ok then it caps up to board limit. It kept changing until hitting 190A.


----------



## blodflekk

Taraquin said:


> It's a post here a few months ago, can write what I remember:
> Cl=cwl(-1 if odd cl)
> Rcdrd=rp
> Ras+rp=rc
> Wr=2xrtp
> Wr=cl
> Wtrs=3 or 4
> Wtrl=rtp or lower
> Rrds/l=4 and faw=4x rrds
> Rfc=divideable by 8 for 8gb stick, by 16 for 16gb sticks
> Scls=2 or 4
> 
> He has rules for others aswell, but don't remember  I can't run wtrl rule, but others work. Lower wr/rtp works a bit better for me.


This is mostly what I am doing. Although I have found I can run tRP lower than tRCDRD. Need tWTR_L to be higher than tRTP also.


----------



## TMavica

Audioboxer said:


> Karhu needs a lot longer than that with DR, like around 9,000~10,000%. In all my testing Karhu doesn't 'time out', it will just eventually error.
> 
> TM5 is what times out, and in this case it seems to be quicker than Karhu for finding such errors. I've had Karhu error out after like 4~5 hours due to the described issues.
> 
> Given what you are facing, TM5 25 cycles first. If it ain't passing there is no point using Karhu.
> 
> A quick way to look at the CPU is disable your curve, disable PBO and run CPU on default.


Disabled PBO still nil help, cycles 21 stopped. Going to try adjust the trfc to 272 see


----------



## Taraquin

PJVol said:


> I can't help thinking that something is different in a way how msi and other vendors firmware behave, especially after @ManniX-ITA experience with a 1205 agesa (gonna post some observations with msi a bit later)
> Can you please check, do this limitation exist on asus board as well? I mean does limits apply on proart as they do on asrock boards?
> Anyone with the Asus or GB boards here - your feedback would be helpful as well.


On my GB board I can set no limit, but unless I do a allcore OC limits gets applied. On 5600X I think they are 88W PPT, 65A and 100A. Doing a 4.8GHz allcore I can override.


----------



## Taraquin

blodflekk said:


> This is mostly what I am doing. Although I have found I can run tRP lower than tRCDRD. Need tWTR_L to be higher than tRTP also.


Yeah, lower RP, lower WR/RTP can improve performance, not by much though. Anta's rules is more of a making things stable guideline, but there can be exceptions. My rev E kit can do 3800cl15-20 and 11rp, anta would say rp 20, but performance would suffer. Most Hynix kits are terrible at rp, some need higher rp than rcdrd, then the rule would be counterproductive, if you can do 3800 16-18-20, but follow rule you must do 16-20-20 instead. Cool nickname btw, do you have norwegian acestry or something?


----------



## PJVol

Taraquin said:


> On my GB board I can set no limit, but unless I do a allcore OC limits gets applied. On 5600X I think they are 88W PPT, 65A and 100A. Doing a 4.8GHz allcore I can override.


Could you pls clarify, what did you mean by "set no limit"?
Did i get it right, and you CAN override the limits set in the BIOS?
If allcore OC engaged ("OC mode") CPU just ignores any PBO limits, so my request only applies to "Auto mode".


----------



## Taraquin

PJVol said:


> Could you pls clarify, what did you mean by "set no limit"?
> Did i get it right, and you CAN override the limits set in the BIOS?
> If allcore OC engaged ("OC mode") CPU just ignores any PBO limits, so my request only applies to "Auto mode".


Sorry, meant MB limits. Readout as 500Ax2 and 200W PPT if I remember correctly, but when I test I can't get my 5600X to use more than 88W if running stock, pbo or pbo+co. If I set allcore 4.8GHz it can use 115W+.


----------



## PJVol

Taraquin said:


> Sorry, meant MB limits. Readout as 500Ax2 and 200W PPT if I remember correctly, but when I test I can't get my 5600X to use more than 88W if running stock, pbo or pbo+co. If I set allcore 4.8GHz it can use 115W+.


You mean even with loosen PBO limits (for example 120W / 80A / 120A) reported PPT value in HWinfo doesn't exceed 88W in CB R23 ?
If so, doesn't the "Power Reporting Deviation" reported by HWInfo look abnormally low while running CB R23 MT, i.e. something like ~ 50-70% ?


----------



## Kha

Kha said:


> Somebody please explain this:
> 
> My 5900x does -15 on all cores IF I go trfc > 450 @ stock 1.35 vdim.
> 
> If I lower trfc, core 8 fails cycler. However if I raise vdim, is perfectly fine (stability also happens if I go -10 on it).
> 
> Dafuq is this ?!


@ManniX-ITA @Veii can you guys make some light here ? Would be much appreciated.


----------



## ManniX-ITA

PJVol said:


> If allcore OC engaged ("OC mode") CPU just ignores any PBO limits, so my request only applies to "Auto mode".


Actually not entirely true.
On my AORUS Master, limits set in PBO Advanced are enforced also in OC Mode.
Didn't try with the Unify-X.



Kha said:


> @ManniX-ITA @Veii can you guys make some light here ? Would be much appreciated.


tRFC needs VDIMM, I guess if you test with TM5 long enough you'll see memory errors.
The errors with CoreCycler are coming up cause RAM is unstable.


----------



## blodflekk

Taraquin said:


> Yeah, lower RP, lower WR/RTP can improve performance, not by much though. Anta's rules is more of a making things stable guideline, but there can be exceptions. My rev E kit can do 3800cl15-20 and 11rp, anta would say rp 20, but performance would suffer. Most Hynix kits are terrible at rp, some need higher rp than rcdrd, then the rule would be counterproductive, if you can do 3800 16-18-20, but follow rule you must do 16-20-20 instead. Cool nickname btw, do you have norwegian acestry or something?


Nope, none at all. It was just something I came up with about 15 years ago and never ended up changing 😂


----------



## Taraquin

PJVol said:


> You mean even with loosen PBO limits (for example 120W / 80A / 120A) reported PPT value in HWinfo doesn't exceed 88W in CB R23 ?
> If so, doesn't the "Power Reporting Deviation" reported by HWInfo look abnormally low while running CB R23 MT, i.e. something like ~ 50-70% ?


Yeah, looks like that unless I run allcore oc, then 115W+ is no problems. Haven't looked at it in hwmon but can check.


----------



## vegetagaru

Veii said:


> Not buggy, just slightly unstable at 1900 FCLK
> That's resolvable for you
> 
> ManniX-ITA explained it well
> Well all advice's where good.
> Use y-cruncher , key combination 1-7-0 soo it tests all tests, 4 loops = 72min minimum for core stability
> Longer is better but it will generate a lot of heat and is a bit more extreme than p95
> 
> You can start with low voltages, maybe increase the VDD18 voltage to 1.86v (up to 2v is fine, but i wouldn't go over 1.96 at absolute worst)
> * our ASRock boards default that to 1.83v not 1.8v
> Then be sure to pass all tests. After that is done, grab OCCT and run it on AVX2 EXTREME preset. That one will take 1h for the free version (that's enough)
> It shouldn't fail ~ but if any of both fail, it can be unstable memory too ~ depends on what it fails
> 
> Keep playing with voltages and keep a minimum of 40mV between each of the voltages
> Dual CCD samples seem to like +60mV distance as minimum (between IOD & SOC)
> But in general, cLDO_VDDP + 40mV = VDDG CCD , or cLDO_VDDP can match VDDG CCD (but there is no need to increase cLDO_VDDP beyond 900mV on this low MCLK)
> IOD to SOC then have to keep minimum of 40mV, often 60mV
> AMD max overclocking voltage here where some ranges before, they still are a thing - but you can need bit more or bit less than recommended
> * that "intention bugs on 2133 FCLK" where plain simple package throttle, new annoyance introduced, not noticed by only having 1 month the sample
> 
> Just so you aren't fearing too much the voltages
> People on reddit for example are too fast to create panic


i didnt had the time yet to do the stress testing yet, but im still having the whea warmings just went to event viewer and saw it, i also uped a bit the vdd18 to 1.86 and also lowered my soc to 1.05 still whea warming


----------



## Veii

vegetagaru said:


> i also uped a bit the vdd18 to 1.86 and also lowered my soc to 1.05 still whea warming


You can go up to 1.25 easily
You'll figure it out, 3800 is not "easy" but at this point nearly every CPU should be able to do that
Dual Rank 3800 is harder, that for sure
My samples both barely run 3733 , but that was rather the memory's fault


----------



## vegetagaru

Veii said:


> You can go up to 1.25 easily
> You'll figure it out, 3800 is not "easy" but at this point nearly every CPU should be able to do that
> Dual Rank 3800 is harder, that for sure
> My samples both barely run 3733 , but that was rather the memory's fault


1.25 what, the soc ?

its been hard for sure XD im already stomping my head into walls xD


----------



## PJVol

ManniX-ITA said:


> Actually not entirely true.
> On my AORUS Master, limits set in PBO Advanced are enforced also in OC Mode.


Are you sure this was not a bug in fw? And what "enforced" means?
I just don't get, what's the point of keeping control over CPU operating conditions in OC mode?



Veii said:


> Reason likely is, because MSI has translated and linked AMD CBS options
> they are lower level and have higher priority, than AMD OVERCLOCKING ones
> Tool only changes AMD OVERCLOCKING limits, but if they are lower than what it can set ~ they will never stick


I think there's no higher or lower priority or level. 
The only way I know of when you cannot override BIOS limits is if they're set at boot via APML (that is very likely), while my tool uses rsmu, and the SMU choose the most constraining out of two. So it seem to depend on how mb vendor implemented initial setting at bootstrap init.


----------



## ManniX-ITA

PJVol said:


> Are you sure this was not a bug in fw? And what "enforced" means?
> I just don't get, what's the point of keeping control over CPU operating conditions in OC mode?


Not sure it was specific to the Master but it was working like that over a few BIOS releases.
This was with the 3800X. Eg. Enforced means TDC/EDC limited to the set Amp (I don't remember about PPT).
The point is, at least useful for me, to avoid overheating.
I used it to throttle the processor under full load.


----------



## Veii

PJVol said:


> I just don't get, what's the point of keeping control over CPU operating conditions in OC mode?


Close to zero, but FIT is active and does limit maximum voltage too ~ except when in LN2 mode
Unclear, i haven't tested the performance penalty (if there is even any) with limits and no limits on OC mode - but the readouts all are stuck at X value
Same on the ASRock and ASUS

PBO2 tool on ASUS i can't test yet
Don't have another 3/5xxx unit here and lack a 2nd PSU for now
(selling things, saving up to finish the build and later buying back what i needed for 2nd pc or just going AM5)

Probably will be able in 2-3 weeks, next Sunday i'll get a bigger package of gear for a client + 6900XTXH
Can test if the tool functions or it's just AMD CBS having higher priority


----------



## Mach3.2

Veii said:


> Reason likely is, because MSI has translated and linked AMD CBS options
> they are lower level and have higher priority, than AMD OVERCLOCKING ones
> Tool only changes AMD OVERCLOCKING limits, but if they are lower than what it can set ~ they will never stick
> 
> Potentially you should have under the normal advanced menu (not OC menu) a normal AMD OVERCLOCKING
> There free up the limiters


Doesn't seem to work, I cleared out the PBO power limits under the OC menu and set it all to Auto, went into advanced > AMD Overclocking and set the limits there but still can't set anything above the limit.


No PBO power limit options under AMD CBS/PBS too.(It might exist within these menus, I just can't find it in my quick search.)


----------



## Luggage

Mach3.2 said:


> Doesn't seem to work, I cleared out the PBO power limits under the OC menu and set it all to Auto, went into advanced > AMD Overclocking and set the limits there but still can't set anything above the limit.
> 
> 
> No PBO power limit options under AMD CBS/PBS too.(It might exist within these menus, I just can't find it in my quick search.)


Strange as might be - just set bios much higher than you will ever want to try with the tool…


----------



## PJVol

Mach3.2 said:


> Doesn't seem to work


IIRC my office pc (B450 Mortar Titanium) has one PBO is in the "CPU advanced" options in a 2nd tab, and another PBO is in the 1st tab in the "AMD overclocking" menu. There's no PBO in CBS, as far as i remember.


ManniX-ITA said:


> I used it to throttle the processor under full load.


Still can't wrap my head around what exactly CPU supposed to do when one of the limits is reached while being in the manually set P-state, i.e. VID, FID, DID? Throttle to what - transitioned to a P1?


----------



## Mach3.2

Luggage said:


> Strange as might be - just set bios much higher than you will ever want to try with the tool…


I know, but it was possible on PJVol's setup so I was doing a bit of experimentation based on the ideas thrown against the wall.


I'd do exactly as you've suggested if I'm tuning my power limits since there's no point starting low. 




PJVol said:


> IIRC my office pc (B450 Mortar Titanium) has one PBO is in the "CPU advanced" options in a 2nd tab, and another PBO is in the 1st tab in the "AMD overclocking" menu. There's no PBO in CBS, as far as i remember.


Yup, tried both AMD Overclocking menus, no dice. Could be an MSI thing.


----------



## Luggage

ManniX-ITA said:


> Not sure it was specific to the Master but it was working like that over a few BIOS releases.
> This was with the 3800X. Eg. Enforced means TDC/EDC limited to the set Amp (I don't remember about PPT).
> The point is, at least useful for me, to avoid overheating.
> I used it to throttle the processor under full load.


Well it should be easy to check.
Run y-cruncher/linx with PBO xyz, check hwinfo.
Run y-cruncher/linx with manOC freq/volt same as PBO results.
Change PBO limits to xyz/2.
Run y-cruncher/linx with same manOC freq/volt as earlier and see if it throttle.


----------



## ManniX-ITA

Mach3.2 said:


> No PBO power limit options under AMD CBS/PBS too.


AMD CBS > NBIO > XFR Enhancement?

You could try to use a modded BIOS (preparing first the USB stick to recover).






MSI X570 TOMAHAWK WIFI - Google Drive







drive.google.com





But it's not really new the latest here...


----------



## Veii

Mach3.2 said:


> Doesn't seem to work, I cleared out the PBO power limits under the OC menu and set it all to Auto, went into advanced > AMD Overclocking and set the limits there but still can't set anything above the limit.
> No PBO power limit options under AMD CBS/PBS too.(It might exist within these menus, I just can't find it in my quick search.)


Oh above shouldn't work
Depends on how PJVol's tool functions ~ i don't think it does anything RSMU related but only uses HSPM *
* to what i saw
You can find the AMD CBS , PBO menu in NBIO
. . .


ManniX-ITA said:


> AMD CBS > NBIO > XFR Enhancement?
> 
> You could try to use a modded BIOS (preparing first the USB stick to recover).
> 
> 
> 
> 
> 
> 
> MSI X570 TOMAHAWK WIFI - Google Drive
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> 
> But it's not really new the latest here...


well nvm, this is the answer 
EDIT:
It's just trusty old AGESA 1.2.0.3C


----------



## ManniX-ITA

Luggage said:


> Well it should be easy to check.
> Run y-cruncher/linx with PBO xyz, check hwinfo.
> Run y-cruncher/linx with manOC freq/volt same as PBO results.
> Change PBO limits to xyz/2.
> Run y-cruncher/linx with same manOC freq/volt as earlier and see if it throttle.


I think you need CTR/Hydra, static OC in BIOS is not the same


----------



## Mach3.2

ManniX-ITA said:


> AMD CBS > NBIO > XFR Enhancement?
> 
> You could try to use a modded BIOS (preparing first the USB stick to recover).
> 
> 
> 
> 
> 
> 
> MSI X570 TOMAHAWK WIFI - Google Drive
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> 
> But it's not really new the latest here...


We have a winner here, that's it.

I'm was already running the unlocked v1.70 BIOS, but thanks for the link.


----------



## Luggage

ManniX-ITA said:


> I think you need CTR/Hydra, static OC in BIOS is not the same


Huh, weren’t we talking about static OC?


----------



## Veii

ManniX-ITA said:


> I think you need CTR/Hydra, static OC in BIOS is not the same


+1
CTR Static OC, 1.55v bugs showed, that it's on OC_Mode (bugs happened when user was in offset mode)
1.68v bugs showed that Hydra is not in OC_Mode , yet on both shows that FIT is active
~ around 6 months old screenshot








It is a mixture of many bugs, that include overboot-bug, but 1.68v is the max you should see on any CPU ~ what FIT allows
(depending if FIT bugged out on OC_Mode or on PB2 mode)


Luggage said:


> Huh, weren’t we talking about static OC?


But static OC also will "show" the limits set, in what HWInfo SMU can read out
It doesn't have to mean the limits are applied, but it can mean that they can be throttled
Nobody tested that so far ~ if CPU is package throttled with supplied limits , independent of what readout tells


----------



## Luggage

Veii said:


> +1
> CTR Static OC, 1.55v bugs showed, that it's on OC_Mode (bugs happened when user was in offset mode)
> 1.68v bugs showed that Hydra is not in OC_Mode , yet on both shows that FIT is active
> ~ around 6 months old screenshot
> 
> 
> 
> 
> 
> 
> 
> 
> It is a mixture of many bugs, that include overboot-bug, but 1.68v is the max you should see on any CPU ~ what FIT allows
> (depending if FIT bugged out on OC_Mode or on PB2 mode)
> 
> But static OC also will "show" the limits set, in what HWInfo SMU can read out
> It doesn't have to mean the limits are applied, but it can mean that they can be throttled
> Nobody tested that so far ~ if CPU is package throttled with supplied limits , independent of what readout tells


From earlier when it was cold.

PBO limits higher than benchmark will use, fit and thermal limited Luggage`s y-cruncher - Pi-2.5b score: 1min 30sec 450ms with a Ryzen 7 5800X
180W

ManOC, will crash with 25MHz more
Luggage`s y-cruncher - Pi-2.5b score: 1min 30sec 75ms with a Ryzen 7 5800X
236W

I think that PBO limits were 208W PPT before I set static OC but it could have been 250W :/

No HWinfo64 unfortunately since I was benching, only benchmate, so no tdc, edc readouts.


----------



## PJVol

Veii said:


> Oh above shouldn't work
> Depends on how PJVol's tool functions ~ i don't think it does anything RSMU related but only uses HSPM *


I set them via rsmu in tool, except boost override (hsmp), but this don't make any difference on my Asrock board - they all (except BO) override BIOS settings regardless of what mailbox was used - Rsmu, MP1, HSMP. I've asked Macho and he tried to set TDC through MP1 already. 
The only unknown so far is - will setting limits via APML solve this annoying glitch. I'll try asap, need to add SB interface to the core part.



Veii said:


> Hydra is not in OC_Mode


I believe it's still OC mode, just per-core - not the regularly used all-core OC.


----------



## Veii

I see , ty
It was an assumption, soo ty for the clearup @PJVol
But i have to ask you an uncomfortable question, because some questionable nonsense is spread around your tool

Who made it exactly ?
How much did irusanov help ~ was he co-coder or just teacher ?
What connection do you have to ASUS here "with PBO2 Tuner" ?

Sorry for the questions, it just needs a bit of clearup , because nonsense is spread
Soo hence i don't want to point to people or create drama about missreports or some making up things, i ask you directly
Please don't mind


----------



## PJVol

Veii said:


> But i have to ask you an uncomfortable question


Funnily you even assume that (uncomfortable) 
I wrote it myself, no one helped me (it'd strange if someone would have)) ) and used Ivan's library ZenStates-Core (lots of thanks to him for time saved) for the low level api (which I currently trying to extend with SBI).
And that's it 
I told you before that I've been learning the C#, but I didn't mean it's new to me, 'cause I was programming C++ long before, just doing it on linux platform in a Qt framework (member of developers and support team for the middleware on our amlogic TV STB platform)


----------



## ManniX-ITA

PJVol said:


> Funnily you even assume that
> I wrote it myself and used Ivan's library ZenStates-Core for the low level api (which I currently trying to extend with SBI).
> That's it
> I told you before that I've been learning the C#, but I was programming C++ long before, just doing it on linux platform in a Qt framework (memeber of developing and supporting team for the middleware on our amlogic TV STB platform)


Did the same for my tool, all credits to Ivan's excellent ZenStates work


----------



## PJVol

ManniX-ITA said:


> Did the same for my tool, all credits to Ivan's excellent ZenStates work


With all the respect for the work he's done, there are other contributors to what we've got atm. You can see those people mentioned in the bottom of Rusanov's README, and they've done no less for the community.


----------



## ManniX-ITA

PJVol said:


> With all the respect for the work he's done, there are other contributors to what we've got atm. You can see those people mentioned in the bottom of Rusanov's README, and they've done no less for the community.


Oh yes there's a lot of people behind his work too 
But making all that work easily accessible via C# it's mainly his doing.


----------



## PJVol

ManniX-ITA said:


> But making all that work easily accessible via C# it's mainly his doing.


Yeah, but honestly while learning C# i always had a feeling of actually coding in javascript with elements of C++ ))
Such a weird experience, how they even managed to mix such strongly typed ++ with an almost "typeless" JS


----------



## ManniX-ITA

PJVol said:


> Yeah, but honestly while learning C# i always had a feeling of actually coding in javascript with elements of C++ ))
> Such a weird experience, how they even managed to mix such strongly typed ++ with an almost "typeless" JS


Being a non professional developer I don't really feel the pain 
But in C/C++, for which I have some basic to decent knowledge, there are a few ways to do things right (generalizing).
In C# there are trillions of different ways to do the same thing and seems no one is never really the best...


----------



## KedarWolf

Here are some scripts that'll only work with HCI MemTest Pro 7, the MTPclassic.exe. The scripts are great as they allocate a single running instance of the HCI to its own separate logical core, like the first one on thread 1, the second one on thread 2. It's the best way to run HCI.

By default, any other HCI Helper or manually running the program runs each instance on every thread, which isn't ideal.


----------



## Veii

PJVol said:


> Funnily you even assume that (uncomfortable)
> I wrote it myself, no one helped me (it'd strange if someone would have)) ) and used Ivan's library ZenStates-Core (lots of thanks to him for time saved) for the low level api (which I currently trying to extend with SBI).
> And that's it
> I told you before that I've been learning the C#, but I didn't mean it's new to me, 'cause I was programming C++ long before, just doing it on linux platform in a Qt framework (member of developers and support team for the middleware on our amlogic TV STB platform)


I wrote it first out of respect (normal behavior)
And 2nd, because the topic is a bit unhappy, yet you don't deserve this type of questions or police way of asking // unless you didn't tell me the truth xD
Soo please excuse my harsh questions, i don't want to be rude 

There are open theories in the room
ASUS stole the work, or PJVol has a contract with ASUS and that's why it appears on ROG XOC tool now
I asked and got a confirmation about other theories spread around your tool ~ soo needed only at last your answer, before being sure what i write

As said, i'm very cautious before i judge people or companies 


Spoiler: Data, PBO2 Tuner





















It gets inspected and de'compiled in the current moment ~ not by me and not by my force ^^#
It seems your little tool got a lot of attention *
* i wish community would like each other a bit more, this sounds like leeching hyenas who betray other, for a tiny bit of credit ~puke~

Technically speaking, an NDA wouldn't allow the person to talk about the connection and the creation of NDA.
Soo i want to ask *if ASUS insisted on anything PBO2 Tuner related ?*
~ Either you knew about a trade and can not answer, or you don't know and can deny ~ if NDA really exists

If you don't know about this, and it still happened ~ we have to blame ROG XOC team who ever is in charge (i'll figure this out)
But right now people send me strange quotes and pieces that (knowing you a bit here) make zero sense to me
Soo i have to ask this uncomfortable question, although i hope that i know you.
It's just to have a 100% confirm what is truth and what is behind the scenes drama making ~ soo drama can stop.

I "think" elmor got bullied away from ASUS, and i "think !", to The Stilt was done the same
Hence similar things where done to my name ~ i want to clear this up , while i can

~ Is anything you answered me the truth ?
~ Is it a surprise to you, that you hear about ASUS and XOC ToolXXXX version ?
If somebody again wanted to steal code or move around credits (although they belong to you) ~ i would like to know and clear it up, with the people i talk 
Soo nobody can make up such nonsense~


----------



## Audioboxer

_enters topic to have a moan about the adventures of getting tRCDRD 13 stable at 3800_



_goes back to miserably failing at getting tRCDRD 13 to pass 5+ minutes_


----------



## MrHoof

Its not worth the time @Audioboxer 
if its even possbile, I spend to many hours on it myself.


----------



## Audioboxer

MrHoof said:


> Its not worth the time @Audioboxer
> if its even possbile, I spend to many hours on it myself.


One guy seemed to manage it in here on DR unless he was fudging screenshots, there is hope!

That hope possibly being strictly down to silicon and the miniscule number of DR kits that can do it 

I seem to need to drop to 3733 to manage it!


----------



## Veii

Audioboxer said:


> _enters topic to have a moan about the adventures of getting tRCDRD 13 stable at 3800_
> 
> 
> 
> _goes back to miserably failing at getting tRCDRD 13 to pass 5+ minutes_


Never give up !
Don't compare yourself to other results, your system is your own uniqueness ~ only fight against your own enemy (you)
and don't think that anything you use behaves the way it is designed to behave  because things misbehave once you start to OC outside of the borders

EDIT:
Don't think RTTs would even be bothered to get figured out, if we'd just follow 1usmus long Matisse research (although they still aren't, i'm too weak to understand everything)
Close to nobody, even on Intel even bothers touching these.
Part because every LGA board is tuned unique by Vendor (allowed to do so) ~ but also part because *everyone trust things to "just work blindy"
They never do, haha*
Throughout all my Zen 1 and further years ~ nothing ever works as it was said to be. Don't make your hopes up, but do not give up and question everything 
It's only on you to get it to work~~


----------



## Luggage

Veii said:


> +1
> CTR Static OC, 1.55v bugs showed, that it's on OC_Mode (bugs happened when user was in offset mode)
> 1.68v bugs showed that Hydra is not in OC_Mode , yet on both shows that FIT is active
> ~ around 6 months old screenshot
> 
> 
> 
> 
> 
> 
> 
> 
> It is a mixture of many bugs, that include overboot-bug, but 1.68v is the max you should see on any CPU ~ what FIT allows
> (depending if FIT bugged out on OC_Mode or on PB2 mode)
> 
> But static OC also will "show" the limits set, in what HWInfo SMU can read out
> It doesn't have to mean the limits are applied, but it can mean that they can be throttled
> Nobody tested that so far ~ if CPU is package throttled with supplied limits , independent of what readout tells


Yea not sure what to make of it. Limits def affect what tdc and edc values hwinfo show, but doesn't correspond to values, I don't think I trust them.
Power and results where consistent though. (for normal priority, normal run to run variance)
PBO 180W 31-32s
PBO 90W 36.5s
MOC 205-208W 31.4-31.7 s no matter what PBO limits where.



http://imgur.com/a/YyqMndt


----------



## Audioboxer

Veii said:


> Never give up !
> Don't compare yourself to other results, your system is your own uniqueness ~ only fight against your own enemy (you)
> and don't think that anything you use behaves the way it is designed to behave  because things misbehave once you start to OC outside of the borders
> 
> EDIT:
> Don't think RTTs would even be bothered to get figured out, if we'd just follow 1usmus long Matisse research
> Close to nobody, even on Intel even bothers touching these.
> Part because every LGA board is tuned unique by Vendor (allowed to do so) ~ but also part because everyone trust things to "just work blind"
> They never do, haha
> Throughout all my Zen 1 and further years ~ nothing ever works as it was said to be. Don't make your hopes up, but do not give up and question everything


I get jealous though [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

 

Fair reminder it _could_ be the IMC.


----------



## MrHoof

tRDWR/tWRRD 9/5 and tWR 18 is kinda outstanding(wrong word) suspicious on those timings might be worth looking at it again but not today for me.


----------



## Kha

Question: for a quite big period of time, 1usmus and many others recommended 40 ohms proc odt, yet lately I am seeing almost everyone sporting much lower values. 

Why so ?


----------



## MrHoof

Most 1usmus guides were written at times of 1st and 2nd gen Ryzens but even those tell you set the lowest thats stable. 
3rd gen and 4th are very similiar but 4th is a little better and both need alot less procODT to be stable at higher RAM frequencys.


----------



## Veii

Kha said:


> Question: for a quite big period of time, 1usmus and many others recommended 40 ohms proc odt, yet lately I am seeing almost everyone sporting much lower values.
> 
> Why so ?


1usmus hasn't touched anything Vermeer related, only Matisse 
He is very busy with Hydra , other developments and has to stay safe when Russia makes problems with Ukraine ~ soo also RL busy

The Stilt & 1usmus took over Matisse
Well a lot of people, elmor helped a lot too
Veii gave promise to take over Vermeer ~ and i hope held the promise for around 14 months

"Why so ?"
We have to rethink couple of quotes from before *
Neither procODT nor cLDO_VDDP should be used for FCLK related values or memOC

cLDO_VDDP belongs to only MCLK, will affect memory stability but it is MCLK related
procODT is fabric related but has no connection to memOC. It will affect it, but should not be used for memOC

Low procODT always was the key to success, since 1700(X) days
It affecting more things is known, but it should not be used "for such".
memOC , memory timings change ~ should not be used together with cLDO_VDDP or procODT

* soo some of the rules "not well known" before, need to be rewritten here 
Simply stated, old information for another generation. This one is different & on a different substrate
Same goes to voltages
** we maybe will need another redo for Revision.B2 
, because that one is again on a different type of substrate (color change) & nobody knows anything about the memcontroller or every change except security


----------



## Audioboxer

MrHoof said:


> tRDWR/tWRRD 9/5 and tWR 18 is kinda outstanding(wrong word) suspicious on those timings might be worth looking at it again but not today for me.


Oh I've already tried copying and it didn't help me lol. You can give it a go.

Unless I'm remembering wrong I think Veii said a looser tWR could help with tRCDRD 13.

I think it's just silicon for me whether it's memory or IMC or both. 3733 seems to be my limit, outside of using maxmem at 3800.


----------



## Veii

Audioboxer said:


> Unless I'm remembering wrong I think Veii said a looser tWR could help with tRCDRD 13.
> I think it's just silicon for me whether it's memory or IMC or both. 3733 seems to be my limit, outside of using maxmem at 3800.


I don't remember fully
But do remember that to this day still am not "satisfied" with the quote "it's all just IMC don't care about it"
Can't be pleased with this way of saying "ah it's out of my control i just give up" 
But that's just me~~


----------



## Audioboxer

Veii said:


> I don't remember fully
> But do remember that to this day still am not "satisfied" with the quote "it's all just IMC don't care about it"
> *Can't be pleased with this way of saying "ah it's out of my control i just give up" *
> But that's just me~~




Yeah, that is me!










The good thing about tRCDRD 13 testing at 3800 is it always dies after a few minutes for me so it's quick to mess around


----------



## Veii

Audioboxer said:


> Yeah, that is me!
> 
> View attachment 2548804
> 
> 
> The good thing about tRCDRD 13 testing at 3800 is it always dies after a few minutes for me so it's quick to mess around


tRCD 13 doesn't need 1T to function, neither SETUP timings
Sometimes it's good to plan less street-turns, ahead of your journey
Neither do DIMM-PCBs crash "less frequently" on 2T mode ~ well half half, but pretty much is what it is. (you have to start somewhere)
Dimm timings, will be mostly bottle-necked by the DIMM-PCB design. Sometimes you have to change your RTT tactics , to find success

Another reminder, is that often tRRD and tWTR have to pushed up, to offset PCB strain in chaining many commands together.
I think i should i call it "many loops" together
Low tRCD to my testing, always won over higher tertiaries ~ although too high will be just a waste

3rd reminder, is that tWRRD and tRDWR values can overlap. High values there will make issues, same as too low ones will make issues


----------



## Audioboxer

Veii said:


> tRCD 13 doesn't need 1T to function, neither SETUP timings
> Sometimes it's good to plan less street-turns, ahead of your journey
> Neither do DIMM-PCBs crash "less frequently" on 2T mode ~ well half half, but pretty much is what it is. (you have to start somewhere)
> Dimm timings, will be mostly bottle-necked by the DIMM-PCB design. Sometimes you have to change your RTT tactics , to find success
> 
> Another reminder, is that often tRRD and tWTR have to pushed up, to offset PCB strain in chaining many commands together.
> I think i should i call it "many loops" together
> Low tRCD to my testing, always won over higher tertiaries ~ although too high will be just a waste
> 
> 3rd reminder, is that tWRRD and tRDWR values can overlap. High values there will make issues, same as too low ones will make issues












I put everything on AUTO apart from manually setting the first 4 timings to 14-13-14-14 and away it goes, but that is probably GDM for you...

Still, I guess I can try and work "backwards" from here and see if I can get something working on 2T or if it's GDM enabled only.


----------



## Veii

Audioboxer said:


> but that is probably GDM for you...


I didn't mean to use THAT cheatery thing , hahaha


----------



## MrHoof

well I gave it a quick go myself with timings trtp/twr 8/16 rrd 4/6 twrt 5/14 and tWRRD/tRDWR 9/3 but didnt make a big diffrennce, just one error 2 instead of a spam but still some 10s and 5s.
1.61v is needed for me to push past error 6 tho wich i wouldnt daily anyway still gonna try a little more at the weekend.


----------



## Veii

Oh,


Audioboxer said:


> I get jealous though [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Oh i don't know fully the current situation with Gigabyte Boards
Sometimes the same is said to MSI
You might want to be very questionable on the 1.65vDIMM
It could be easily either 1.75 or 1.66v 
* although i haven't seen dual rank that doesn't crash at 1.7v so far. The ones i know crash at 1.6v already (PCB Crash)


----------



## Audioboxer

Veii said:


> I didn't mean to use THAT cheatery thing , hahaha












Change to 2T and ProcODT drops, tPHYRDL "fixes itself" but yeah, back to an error after a few minutes.

GDM really does mess things up!



Veii said:


> Oh,
> 
> Oh i don't know fully the current situation with Gigabyte Boards
> Sometimes the same is said to MSI
> You might want to be very questionable on the 1.65vDIMM
> It could be easily either 1.75 or 1.66v
> * although i haven't seen dual rank that doesn't crash at 1.7v so far. The ones i know crash at 1.6v already (PCB Crash)


1.65v is the highest I can go and even then it's a struggle. 1.64v is "safer".


----------



## Audioboxer

MrHoof said:


> well I gave it a quick go myself with timings trtp/twr 8/16 rrd 4/6 twrt 5/14 and tWRRD/tRDWR 9/3 but didnt make a big diffrennce, just one error 2 instead of a spam but still some 10s and 5s.
> 1.61v is needed for me to push past error 6 tho wich i wouldnt daily anyway still gonna try a little more at the weekend.


Getting passed early 2/6s just tends to be a bit more voltage.

TM5 always dies for me 1+ minutes in










I know what error 10 could usually mean, but this is the case playing around with all sorts of Rtts/DrvStr.


----------



## PJVol

Veii said:


> ~ Is anything you answered me the truth ?
> ~ Is it a surprise to you, that you hear about ASUS and XOC ToolXXXX version ?


Lol, you made my day with it 
I just wonder where this "asus" thing is even come from. I never ever mentioned this name aside from joking about the origin of that tool1007.

Anyway, I wanted to ask you something while roaming the ddr specs.
1. It was stated (in samsung docs) that ODT pin is ignored if RTT_NOM is set to disabled. Does it mean ODT value itself is ignored in this case or i misinterpret it?
2. Among the numerous DDR tuning tutorials in the net I found one (curious, do you know the author... or maybe it was you by a chance  ) where he suggested the way to find optimal ODT value using memtest86 - can you say anything about how reliable it is (if at all)?


----------



## Veii

PJVol said:


> Lol, you make my day with it
> I just wonder where this "asus" thing is even come from. I never ever mentioned this name aside from joking about the origin of that tool1007.


It's because of this








I get told nonsense , well that people tell my friends this nonsense
first two parts i cleared up ~ elmor has zero connection to this and confirmed "zero connection"
(different chat now)








Only thing remaining is to get a clear answer from you,
but you dodge twice now the question 

Either XOC Team stole it, or you are aware that it appeared there, and sold/traded it
It would be good to know whatever the reason is ~ if you are aware that it appeared on ROG XOC tool under the AMD section (well now you are aware, but the question is "why")
To judge if people are trolling and creating drama, or it was an exchange
~ which is fine too, but honesty is more important))


PJVol said:


> 1. It was stated (in samsung docs) that ODT pin is ignored if RTT_NOM is set to disabled. Does it mean ODT value itself is ignored in this case or i misinterpret it?





> The ODT feature is designed to improve signal integ-rity of the memory channel by allowing the DRAM controller to independently change termination resistance *for any or all DRAM devices*.


Problem is, this is not entirely the whole story
It is dependent between banks on dual rank
It depends how Hi-Z is used, because Hi-Z will be supplied on NOM , independent if it was specified or not
And RTTs change their behavior on Dual Rank and single rank


Code:


NOTE :
1. When read command is executed, DRAM termination state will be Hi-Z for defined period independent of ODT pin and MR setting of RTT_PARK/RTT_NOM.
2. If RTT_WR is enabled, RTT_WR will be activated by Write command for defined period time independent of ODT pin and MR setting of RTT_PARK /RTT_NOM.
3. If RTT_NOM MRS is disabled, ODT receiver power will be turned off to save power.

From the same place, but it doesn't again tell the whole story 
*If _WR is enabled, it has the highest priority and changes how NOM & PARK behave*. If one of both is absent it does automatically calculate the correct timing ~ but that is slow
If _WR is turned to Hi-Z , CRC checks will be used as a feature of DDR4 and loop goes first through CRC "module" before it continues the operation (simultaneous with a wait-out on the result)

If RTT_NOM is disabled, it will not turn ODT off ~ only in specific cases it will
This specific case depends how DynamicODT functions
You can run many of them on disabled, but ODT changes are factored in in board-design ~ by trace "ripple" design and trace neighbors design. It's only here as assisting and additive, but it can function without them @ 1.2vDIMM ~ same for HI-Z mode, 1.2v is where it doesn't die in itself
They are only needed by design, but boards often take over the "minimum" requirements ~ and only list "tested" values. The same goes for LLC things. The "modes" they list are only "tested conditions that pass data-eye requirements" . They never list all options

*Soo answer is, that it depends on RTT_WR state*
You can set NOM to disable, and it will follow board design if _WR is absent too
But boards need at least one of the 3 to control CKE pulse movement - up or down
PARK is floor, NOM is ceiling
Yet PARK, NOM, WR change their behavior on dual rank and on single rank & on dimm amount or rather BGS feature (they change between banks)

HI-Z turned on mode (automatically) is still something i learn, but topic is hard
because there are too many "it depends" , yet Vendors have it MSR chip preconfigured with what it can do (they rarely cut away features)
Yet still, dimms decide in realtime what to do and what not do
Soo for example tRC behavior will be different up type of refresh it decides to do by itself or by the PCB-Vendor enforced. The ICs do not have much speak here, it's the PCB maker that is responsible here.
Soo these docs mostly go for barebones samsung OEM sticks only. Micron ones then are completely different ~ and what AMD decides or enforces is also completely different than JEDEC on the core.


PJVol said:


> 2. Among the numerous DDR tuning tutorials in the net I found one (curious, do you know the author... or is it you  ) where he suggested the way to find optimal ODT value using memtest86 - can you say anything about how reliable is it (if at all)?


I'm not , my japanese is not that great ~ i wish, but i am lazy never had a reason to keep learning, yet would love to continue practicing as i'm used to the pitch of the language
(Female-RL killed my motivation to continue practicing korean, japanese & artist stuff~ but looking at my future, i should continue learning if i ever want to move away from this place . _ . )
(soo currently i rather wait for a job offer, to have a reason to move over somewhere down to Asia, as i'm only doing freelancer work)
Interestingly i know the logo from somewhere, yet it doesn't seem? to be a mainstream japanese media or forum.
I will have to have a clear read through it and test, can't comment on it yet 
Always dodged memtest, but i think the same can be called to anta's absolute ~ config. It should test discharge behavior very well // but it has a bug over 1.55v sadly at any frequency
Maybe can be useful, to prevent Zen CPU from doing too much autocorrection ~ i wonder


----------



## PJVol

Veii said:


> but you dodge twice now the question


Thanks for the answers. 
As for the question - didn't intend to evade it, perhaps I should have been more clear: 
I got no ****ing clue what all this talking is about, and what does that (including asus) have to do with me. Case closed.


----------



## ManniX-ITA

Veii said:


> Either XOC Team stole it, or you are aware that it appeared there, and sold/traded it


Gosh... are these people for real?
Seems like the plot of one of these series for teenagers on TV


----------



## Veii

Yikes,
At any point - i can clear it up
If it was taken without agreement, i can force it being erased.
Making their tool use-protected is an evil move but in ROG-XOC's Team right. Stealing other people's work, is not in their right.
Am curious if there is any mention about PJVol there at all ~ still wait for it to be linked to me or the guy created lies out of thin air for attention towards the company

Whatever,
Only don't like how people are treated, lies are told or drama is created. It shouldn't be that way 
I'll clear it up, if anything malice was attempted~


----------



## Audioboxer

@Veii Is there any testing you would want me to do with HI-Z? I can boot it fine at 3800.


----------



## Veii

Veii said:


> Yikes,
> At any point - i can clear it up
> If it was taken without agreement, i can force it being erased.
> Making their tool use-protected is an evil move but in ROG-XOC's Team right. Stealing other people's work, is not in their right.
> Am curious if there is any mention about PJVol there at all ~ still wait for it to be linked to me or the guy created lies out of thin air for attention towards the company
> 
> Whatever,
> Only don't like how people are treated, lies are told or drama is created. It shouldn't be that way
> I'll clear it up, if anything malice was attempted~


Soo update:
Good to see a happy ending @ManniX-ITA @PJVol

It was not in there or ever planed to be there
Only Set_DldoPsmMargin existed
It was a bad phrase by some person and another language issue by 2nd person & 3rd person again translates message wrongly
Soo bad-phone message came over differently than source intended to say.
...wow

Ah glad it's not that way ~ case closed.
All sounded that ROG-XOC team stole code, but it indeed is not that way
Irusanov confirmed too that he knows the codes required for PBO2 Tuner to function but both PJVol and Irusanov worked on it
Nobody stole anything and everything is fine ~ glad.
I expected it to be nonsense, but how it sounded was . . . how to say it.
"It was known practice in the OC industry and can happen"

Glad nobody needs to be blamed and everything is fine~~


----------



## Veii

Audioboxer said:


> @Veii Is there any testing you would want me to do with HI-Z? I can boot it fine at 3800.


Didn't you do already ?

RTT_WR = Hi-Z is interesting to explore
But the amount of strain it creates is big. 
PARK can not be that low , to cover it ~ and VDIMM used is amplified too much

For me, 1.2 - 1.25vDIMM was enough for most things. Higher than 1.3 created uncoolable temps
And you/we tested & confirmed that WR_/2 was better for thermals
It's still not _WR /1 , but _WR = Hi-Z is different between banks and different between SR and DR

You can only test if on the finished Hi-Z test, you get any difference once you enable normal BGS mode, instead of alternative BGS mode
And you can test if your low tWTR_S & tRRD_S values stability changes, once you go away from BGS Alt mode to "normal" BGS enabled, mode


----------



## byDenoso

What's the safe SOC voltage to 24/7 for Matisse?
1,2v?


----------



## Veii

byDenoso said:


> What's the safe SOC voltage to 24/7 for Matisse?
> 1,2v?


1.1 , 1.15 peak
Afterwards you got negative scaling (that's the reason of fear on Vermeer, from old Matisse information)
peak likely is 1.2 then, where peak here on Vermeer is 1.3v, but after 1.25v you get diminishing returns or even negative scaling
(peak peak would be 1.35 on Vermeer, but that's sub zero & different procODT)

Answer is, stay bellow 1.15v on Matisse to prevent negative scaling
1.2v is already too much but won't kill your chip ~ shouldn't
Matisse was low power bin, with Vermeer Boosting mechanics ~ just substrate was too weak to handle it, only very efficient
(as that PB2 was done on Matisse launch and integrated ~ there are two split teams at AMD that research at the same time)

EDIT:
Soo B0 was leaky high voltage performance focused
B2 & ZenX3D then again is lower power enhanced substrate
Soo also likely will need different min-max voltages again


----------



## byDenoso

Veii said:


> 1.1 , 1.15 peak
> Afterwards you got negative scaling (that's the reason of fear on Vermeer, from old Matisse information)
> peak likely is 1.2 then, where peak here on Vermeer is 1.3v, but after 1.25v you get diminishing returns or even negative scaling
> (peak peak would be 1.35 on Vermeer, but that's sub zero & different procODT)
> 
> Answer is, stay bellow 1.15v on Matisse to prevent negative scaling
> 1.2v is already too much but won't kill your chip ~ shouldn't
> Matisse was low power bin, with Vermeer Boosting mechanics ~ just substrate was too weak to handle it, only very efficient
> (as that PB2 was done on Matisse launch and integrated ~ there are two split teams at AMD that research at the same time)
> 
> EDIT:
> Soo B0 was leaky high voltage performance focused
> B2 & ZenX3D then again is lower power enhanced substrate
> Soo also likely will need different min-max voltages again


What you mean with "negative scaling"
My Matisse can run very low VDDG CCD Voltages but VDDG IOD must be higher than 1085mv or i get random reboots.


----------



## Veii

byDenoso said:


> What you mean with "negative scaling"
> My Matisse can run very low VDDG CCD Voltages but VDDG IOD must be higher than 1085mv or i get random reboots.


Matisse VDDG was auto balanced independent of what you put in
The "split of voltages" , in such case the balancing focus ~ came later. Yet by design i don't "think" it can even split both. Same as Cezanne or Renoir can not.
APU's have a different reason for not being able to, but Matisse i don't remember was ever able to supply different voltages there. This came later with Vermeer

Negative scaling means, that instead of having diminishing returns - you worsen the situation and increase chance of instability ~ as it's overvolted
Matisse has same FIT module like Vermeer, but design is slightly different (up to firmware) ~ yet substrate is majorly different and internal clocks are different (lower)


----------



## Audioboxer

Veii said:


> Didn't you do already ?
> 
> RTT_WR = Hi-Z is interesting to explore
> But the amount of strain it creates is big.
> PARK can not be that low , to cover it ~ and VDIMM used is amplified too much
> 
> For me, 1.2 - 1.25vDIMM was enough for most things. Higher than 1.3 created uncoolable temps
> And you/we tested & confirmed that WR_/2 was better for thermals
> It's still not _WR /1 , but _WR = Hi-Z is different between banks and different between SR and DR
> 
> You can only test if on the finished Hi-Z test, you get any difference once you enable normal BGS mode, instead of alternative BGS mode
> And you can test if your low tWTR_S & tRRD_S values stability changes, once you go away from BGS Alt mode to "normal" BGS enabled, mode


You had me check it was booting but I didn't actually test anything or run any stability tests. Will have a look at it!


----------



## byDenoso

Veii said:


> Matisse VDDG was auto balanced independent of what you put in
> The "split of voltages" , in such case the balancing focus ~ came later. Yet by design i don't "think" it can even split both. Same as Cezanne or Renoir can not.
> APU's have a different reason for not being able to, but Matisse i don't remember was ever able to supply different voltages there. This came later with Vermeer
> 
> Negative scaling means, that instead of having diminishing returns - you worsen the situation and increase chance of instability ~ as it's overvolted
> Matisse has same FIT module like Vermeer, but design is slightly different (up to firmware) ~ yet substrate is majorly different and internal clocks are different (lower)


So how i fix the random reboots issue?
Puting the same voltages to vddg_ccd and vddg_iod?


----------



## fqqf

Hello, Friends. I recently started overclocking memory and wanted to know if the results are good? It passed tm5 anta. My Memory is a Patriot Viper 4 Blackout [PVB416G413C8K]. 3800mhz and 1900fclk does not start with the current settings that are in the screenshot. Thanks


----------



## Veii

byDenoso said:


> So how i fix the random reboots issue?
> Puting the same voltages to vddg_ccd and vddg_iod?


Random idle reboots are complicated

Try enabling in AMD OVERCLOCKING, UncoreOC mode
- that will allow for VDDG voltages to actually do anything, not be ignored by FIT  Matisse shenanigans
Keep distance of voltages at least 50mV apart, sometimes 75mV ~ this was very important on Matisse days

Set Powersuply idle control to typical current and enable Global C-States
Cores idling and suspending is important, as budget was very tight and signal integrity on this platform very weak
It loved 28ohm procODT, sometimes 30 max
And it required sleepy cores, else it never reached their advertised boost

1usmus made a quite good powerplan for it , as it was fully powerplan depedent ~ yet ryzen supplied ones where questionable
1usmus Custom Power Plan for Ryzen 3000 Download v1.1
The normal one not the "works for all CPUs"
Download is version 1.1 but will say 1.0

I think this is all you can do so far
If random reboots still exist (which are idle reboots)
then maybe you have to do more ~ but for now try this out

OC'ing T-Force 4133 cl18 this old post had voltage scaling information for Matisse
But i didn't contribute too much to it
1usmus did far more work here for OCN
Well The Stilt also & gupsterg was very helpful
~ more, i forgot 

* rares guy was a good overclocker, just bit rude to people / Bloax reminds me a lot about him (please don't bann Bloax, lol)
I miss him . _ . sadly was too toxic with his jokes
But maybe you can find a lot of information within his posts , if not deleted. He contributed a lot too


fqqf said:


> Hello, Friends. I recently started overclocking memory and wanted to know if the results are good? It passed tm5 anta. My Memory is a Patriot Viper 4 Blackout [PVB416G413C8K]. 3800mhz and 1900fclk does not start with the current settings that are in the screenshot. Thanks
> View attachment 2548834


You did quite well !
Only procODT is very high , you surely can lower it to 34 ohm, without loosing stability

Aren't these dimms on A0 PCB ?
I remember the4000 and 4133 (some not all 4133) where b-dies but on very sensitive A0 PCB
On that you had negative scaling above 1.48v & can kill them at 1.56v , with these RTT's and it required clean signal integrity = very low voltages and weak powering

If you have issues with low procODT (in the 32 range for example), change CAD_BUS to 40-20-30-24 & it has to start
1900 FCLK requires low procODT
but low procODT stability requires a lot of work ~ soo start with 34ohm, TM5 screenshot it stable (25 cycles), run y-cruncher for 4 loops (72min, keycombination 1-7-0)
and then drop to 32ohm and do the same
TM5 25 loops, y-cruncher 4 loops = 72min , and maybe at the end OCCT extreme AVX2 (by default free version stops after 1h, that's enough)

Good luck !
But you shouldn't need it


----------



## Luggage

@ManniX-ITA 
You got better temp like this?
Or am I still missing the point about ctr/hydra?



Luggage said:


> Yea not sure what to make of it. Limits def affect what tdc and edc values hwinfo show, but doesn't correspond to values, I don't think I trust them.
> Power and results where consistent though. (for normal priority, normal run to run variance)
> PBO 180W 31-32s
> PBO 90W 36.5s
> MOC 205-208W 31.4-31.7 s no matter what PBO limits where.
> 
> 
> 
> http://imgur.com/a/YyqMndt





ManniX-ITA said:


> Not sure it was specific to the Master but it was working like that over a few BIOS releases.
> This was with the 3800X. Eg. Enforced means TDC/EDC limited to the set Amp (I don't remember about PPT).
> The point is, at least useful for me, to avoid overheating.
> I used it to throttle the processor under full load.





ManniX-ITA said:


> I think you need CTR/Hydra, static OC in BIOS is not the same


----------



## ManniX-ITA

Luggage said:


> You got better temp like this?


Something similar yes.
It's early morning I'm still confused, will check it better later 



Luggage said:


> Or am I still missing the point about ctr/hydra?


The point about software OC Mode is that not all board manufacturers are doing the same thing with static clocks.
Sometimes they use their own "special tricks", per CCD multiplier especially, and the behavior in OC Mode is different than when you enter from PBO.


----------



## kim nk

To do 3800 trcd 13 we need to increase tfaw and the room to reduce is depending on the RAM yield; clkdrvstr, more memory voltage is needed . Memory voltage also differs widely depending on yield; timing yields separate memory voltage yields. I've done a lot of research now and I've found that ddr4 is the favorite of the cl14 4000 royal elite.Cl14 4000 oloy, cl14 4000 jiskill, cl17 4800 jiskill yield is all the same. However, the voltage requirement for timing shows that the cl14 4000 royal elite has a superior yield.










cl16 4400 oloy , dram voltage 1.56v










gskill cl18 4800 Royal , dram voltage 1.57v










cl17 4800 royal 1.56v









The remaining cl14 4000 oloy kits and cl174800 royal kits are similar in 1.56-1.58v.

However, cl14 4000 Royal Elite is different. Trcdrd14 is lucky to draw at 4000cl14, but the average voltage yield is much better than the timing of the royal elite.


cl14 4000 Royal Elite 3800 cl13 trfc 216 1.58v.









cl14 4000 Royal elite Memory voltage is 1.52v.











There's a 0.5v~ difference. Of course, when the timing is tightened on the 3800 3866 3933 clock, this difference in memory voltage occurs even when compared to 1t. The same cpu. Same main board.

In conclusion, I think it would be the best kit in ddr4 if we could get a better trcdrd yield by pulling out the cl14 4000 royal elite memory kit.
Unify-x board is... 4000 clock cl14. To do real 1t... Board performance is insufficient. 
But if you go to the dark hero board... 4000 clock cl14 Real 1t can be easily successful.


----------



## TMavica

kim nk said:


> To do 3800 trcd 13 we need to increase tfaw and the room to reduce is depending on the RAM yield; clkdrvstr, more memory voltage is needed . Memory voltage also differs widely depending on yield; timing yields separate memory voltage yields. I've done a lot of research now and I've found that ddr4 is the favorite of the cl14 4000 royal elite.Cl14 4000 oloy, cl14 4000 jiskill, cl17 4800 jiskill yield is all the same. However, the voltage requirement for timing shows that the cl14 4000 royal elite has a superior yield.
> 
> View attachment 2548857
> 
> 
> cl16 4400 oloy , dram voltage 1.56v
> 
> View attachment 2548858
> 
> 
> gskill cl18 4800 Royal , dram voltage 1.57v
> 
> View attachment 2548859
> 
> 
> cl17 4800 royal 1.56v
> View attachment 2548862
> 
> 
> The remaining cl14 4000 oloy kits and cl174800 royal kits are similar in 1.56-1.58v.
> 
> However, cl14 4000 Royal Elite is different. Trcdrd14 is lucky to draw at 4000cl14, but the average voltage yield is much better than the timing of the royal elite.
> 
> 
> cl14 4000 Royal Elite 3800 cl13 trfc 216 1.58v.
> View attachment 2548860
> 
> 
> cl14 4000 Royal elite Memory voltage is 1.52v.
> 
> View attachment 2548861
> 
> 
> 
> There's a 0.5v~ difference. Of course, when the timing is tightened on the 3800 3866 3933 clock, this difference in memory voltage occurs even when compared to 1t. The same cpu. Same main board.
> 
> In conclusion, I think it would be the best kit in ddr4 if we could get a better trcdrd yield by pulling out the cl14 4000 royal elite memory kit.
> Unify-x board is... 4000 clock cl14. To do real 1t... Board performance is insufficient.
> But if you go to the dark hero board... 4000 clock cl14 Real 1t can be easily successful.


I got same kit as you 4000C14 16X2 GTES, if i do 25 test, it timeout randomly


----------



## vegetagaru

vegetagaru said:


> 1.25 what, the soc ?
> 
> its been hard for sure XD im already stomping my head into walls xD


Still regarding this subject i have a question if someone could point me the right way xD

so on zentimings my "Mem VTT" says N/A, if i go to bios the voltage its locked, and it appears as 600 (i have some kind of option to increase by step,but dunno how it works i will later post a screenshot of it). could this be a problem related with my Whea warmings ?


----------



## Audioboxer

kim nk said:


> To do 3800 trcd 13 we need to increase tfaw and the room to reduce is depending on the RAM yield; clkdrvstr, more memory voltage is needed . Memory voltage also differs widely depending on yield; timing yields separate memory voltage yields. I've done a lot of research now and I've found that ddr4 is the favorite of the cl14 4000 royal elite.Cl14 4000 oloy, cl14 4000 jiskill, cl17 4800 jiskill yield is all the same. However, the voltage requirement for timing shows that the cl14 4000 royal elite has a superior yield.
> 
> View attachment 2548857
> 
> 
> cl16 4400 oloy , dram voltage 1.56v
> 
> View attachment 2548858
> 
> 
> gskill cl18 4800 Royal , dram voltage 1.57v
> 
> View attachment 2548859
> 
> 
> cl17 4800 royal 1.56v
> View attachment 2548862
> 
> 
> The remaining cl14 4000 oloy kits and cl174800 royal kits are similar in 1.56-1.58v.
> 
> However, cl14 4000 Royal Elite is different. Trcdrd14 is lucky to draw at 4000cl14, but the average voltage yield is much better than the timing of the royal elite.
> 
> 
> cl14 4000 Royal Elite 3800 cl13 trfc 216 1.58v.
> View attachment 2548860
> 
> 
> cl14 4000 Royal elite Memory voltage is 1.52v.
> 
> View attachment 2548861
> 
> 
> 
> There's a 0.5v~ difference. Of course, when the timing is tightened on the 3800 3866 3933 clock, this difference in memory voltage occurs even when compared to 1t. The same cpu. Same main board.
> 
> In conclusion, I think it would be the best kit in ddr4 if we could get a better trcdrd yield by pulling out the cl14 4000 royal elite memory kit.
> Unify-x board is... 4000 clock cl14. To do real 1t... Board performance is insufficient.
> But if you go to the dark hero board... 4000 clock cl14 Real 1t can be easily successful.


The challenge we're after right now is tRCDRD 13 on DR, it appears to be much harder than with SR. Very few people seem to have managed to do it stable. One person in this topic as far as I can see.


----------



## Taraquin

kim nk said:


> To do 3800 trcd 13 we need to increase tfaw and the room to reduce is depending on the RAM yield; clkdrvstr, more memory voltage is needed . Memory voltage also differs widely depending on yield; timing yields separate memory voltage yields. I've done a lot of research now and I've found that ddr4 is the favorite of the cl14 4000 royal elite.Cl14 4000 oloy, cl14 4000 jiskill, cl17 4800 jiskill yield is all the same. However, the voltage requirement for timing shows that the cl14 4000 royal elite has a superior yield.
> 
> View attachment 2548857
> 
> 
> cl16 4400 oloy , dram voltage 1.56v
> 
> View attachment 2548858
> 
> 
> gskill cl18 4800 Royal , dram voltage 1.57v
> 
> View attachment 2548859
> 
> 
> cl17 4800 royal 1.56v
> View attachment 2548862
> 
> 
> The remaining cl14 4000 oloy kits and cl174800 royal kits are similar in 1.56-1.58v.
> 
> However, cl14 4000 Royal Elite is different. Trcdrd14 is lucky to draw at 4000cl14, but the average voltage yield is much better than the timing of the royal elite.
> 
> 
> cl14 4000 Royal Elite 3800 cl13 trfc 216 1.58v.
> View attachment 2548860
> 
> 
> cl14 4000 Royal elite Memory voltage is 1.52v.
> 
> View attachment 2548861
> 
> 
> 
> There's a 0.5v~ difference. Of course, when the timing is tightened on the 3800 3866 3933 clock, this difference in memory voltage occurs even when compared to 1t. The same cpu. Same main board.
> 
> In conclusion, I think it would be the best kit in ddr4 if we could get a better trcdrd yield by pulling out the cl14 4000 royal elite memory kit.
> Unify-x board is... 4000 clock cl14. To do real 1t... Board performance is insufficient.
> But if you go to the dark hero board... 4000 clock cl14 Real 1t can be easily successful.


Testing 3500cl13-18-18 on rev E with my 12400F I can confirm that FAW and RCDRD can interefere. If I set RCDRD to 19 I could do 4-4-16 on RRD\FAW, setting RCDRD to 18 I got loads of errors with 4-4-16, but no errors at 5-5-20, you may not need 40 FAW, try something like 5-5-20 or 6-6-24 first  

Audioboxer: Try this you aswell for you 13-13-13 setup to maybe work


----------



## Audioboxer

@Veii First thing I've found going back to Hi-Z isn't quite related to that but given your advice on RttPark with Hi-Z I thought I'll switch it to 7 and at 28.2 ProcODT, it wouldn't boot. 30~32 it didn't clean boot, would boot second time. 34.3 it boots clean.

Something you probably already know but for everyone else it seems if you're trying to run a weaker RttPark it is also tied up in what ProcODT is running at.

Now going to test some memory temps running with Hi-Z through stability apps.


----------



## rossi594

Luggage said:


> Yea but anyway how do you set and stress CO in a couple of hours? I still get errors 6-7 hours into a cs run
> 
> 
> 
> Code:
> 
> 
> *start*
> [Sat Feb 12 08:24:44 2022]
> *cut*
> [Sat Feb 12 14:22:43 2022]
> FATAL ERROR: Rounding was 0.5, expected less than 0.4
> Hardware failure detected running 24576K FFT size, consult stress.txt file.
> 
> ok 4h this time...


I did mine running prime 95 and checking HWinfo for effective clocks (clock streching) and then running core cycler from occt.


----------



## Audioboxer

@Veii After an hour of Hi-Z at 1.58v I can't really say I notice any thermal increase. Might just be a reality of being watercooled?










1 hour 30 minutes, still no real increase.


----------



## Luggage

rossi594 said:


> I did mine running prime 95 and checking HWinfo for effective clocks (clock streching) and then running core cycler from occt.


The question was how to do it quickly when I and @Audioboxer get errors after _many_ hours of corecycler.


----------



## rossi594

Luggage said:


> The question was how to do it quickly when I and @Audioboxer get errors after _many_ hours of corecycler.


Are you using OCCT to cycle the cores? I tested for 2h for each setting with that, after I was done with all the offsets I ran it for 8+h without any errors (so 2h of core cycling with OCCT was enough for me). Some of it might be related to heat buildup over time? You are both on air cooling are you?


----------



## rossi594

The full approach was:

All core negative curve optimizer offset (start at -30 until you can run Prime95 and HWinfo shows Current Effective Clock = Core Clock = Maximum Effective Clock) then run OCCT core cycling for a few hours. (Just to be sure)

Then go to by core and start with -30 and always half the difference. So if you best all core curve optimizer is -10 you start with -30 if that fails you go to -20 then if that passes go to -25 if it failes go to -15 etc. first find the first setting without clock streching. Then test for stability (2h were enough for me on each setting) and if necessary go reduce the negative offset until stable.

Then final testing for a few hours. If you have errors. Note down the numbers and put co to 0 for each core individually until you found the one that errors and tune that core again.


----------



## Luggage

rossi594 said:


> Are you using OCCT to cycle the cores? I tested for 2h for each setting with that, after I was done with all the offsets I ran it for 8+h without any errors (so 2h of core cycling with OCCT was enough for me). Some of it might be related to heat buildup over time? You are both on air cooling are you?











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


You VSOC is too low, raise it at least to 1.15V. Not necessarily, my VSOC is absolutely fine on AUTO at 3800. This is 1.1v.




www.overclock.net





Audioboxer and me are booth on rather over kill custom loops.

Edit: and heat leads to lower clocks and less errors, running over night can trigger errors if ambient drops enough that your cores run faster…


corecycler cycles a p95 load (as default, you can also run Aida or y-cruncher loads)

now I also check with y-cruncher all core and blender and occt thought, because this is y-cruncher erroring within an hour after corecycler ran over night with no errors.



http://imgur.com/a/ZMnaGHQ


Edit: the good thing about corecycler over occt is that it tells you what core crashed so you don’t have to search for it.


----------



## rossi594

Luggage said:


> Edit: the good thing about corecycler over occt is that it tells you what core crashed so you don’t have to search for it.


I'm setting all the other cores to the stable setting while I find the individual max setting. So I know it's the core that I'm currently tuning / testing.

So trying OCCT like I did could help you ...

To paraphrase:
"How to test them faster?" Try OCCT core cycling for 2h it worked for me.


----------



## ManniX-ITA

Luggage said:


> because this is y-cruncher erroring within an hour after corecycler ran over night with no errors.


If CoreCycler running over a single Core doesn't fail but y-cruncher all is probably due to voltages and/or VRM/PWM/LLC settings.
More likely candidates too low VSOC, VDDG IOD or too weak LLC/PWM Frequency


----------



## ManniX-ITA

Luggage said:


> Edit: the good thing about corecycler over occt is that it tells you what core crashed so you don’t have to search for it.


Also 28 iterations of what? 

SSE Large?

It's a lot of wasted time probably.

You need to test all FFT sizes, at least with SSE.
Better with AVX and AVX2 too if you have the time.

If you spend a bit of time messing with the ini it'll save a lot of testing time...

Do a quick run with:

runtimePerCore = 6m
FFTSize = 720-720

3-4 cycles and you have a first quick check, very unstable cores will fail in 1-2 minutes.

Then a more through check with higher max frequency:

runtimePerCore = auto
FFTSize = 16000-27000

This will take about 5 minutes per Core.
Between 5-10 cycles and you have almost all unstable Core already in the net.

After you passed it you need to go over all FFTs, this is a nighttime test.

runtimePerCore = auto
FFTSize = All

Now you can be pretty confident all cores stable.
But not 100% sure.

If you want to be sure do it again changing to:

mode = AVX

And then with:

mode = AVX2


----------



## ManniX-ITA

rossi594 said:


> "How to test them faster?" Try OCCT core cycling for 2h it worked for me.


It's okay but I like more CoreCyler.
OCCT is running an old Prime95 version in background.
But you don't know exactly which FFT sizes are tested.

I find the latest versions a bit underwhelming for single Core testing.
He changed something in the FFT sizes, they are clearly all much smaller than before.
Even with Large testing a Single Core the clock never really boost that high and this is bad for testing the CO count.
CoreCycler can top 5060 MHz with large FFT sizes on my best Cores, OCCT rarely goes over 4850 MHz.


----------



## Luggage

ManniX-ITA said:


> Also 28 iterations of what?
> 
> SSE Large?
> 
> It's a lot of wasted time probably.
> 
> You need to test all FFT sizes, at least with SSE.
> Better with AVX and AVX2 too if you have the time.
> 
> If you spend a bit of time messing with the ini it'll save a lot of testing time...
> 
> Do a quick run with:
> 
> runtimePerCore = 6m
> FFTSize = 720-720
> 
> 3-4 cycles and you have a first quick check, very unstable cores will fail in 1-2 minutes.
> 
> Then a more through check with higher max frequency:
> 
> runtimePerCore = auto
> FFTSize = 16000-27000
> 
> This will take about 5 minutes per Core.
> Between 5-10 cycles and you have almost all unstable Core already in the net.
> 
> After you passed it you need to go over all FFTs, this is a nighttime test.
> 
> runtimePerCore = auto
> FFTSize = All
> 
> Now you can be pretty confident all cores stable.
> But not 100% sure.
> 
> If you want to be sure do it again changing to:
> 
> mode = AVX
> 
> And then with:
> 
> mode = AVX2


Yea that sounds more effective but a single pass is still 45-58 minutes (for me with 8 cores) so a far stretch over “a couple of hours” (to tune a curve)


----------



## rossi594

ManniX-ITA said:


> It's okay but I like more CoreCyler.
> OCCT is running an old Prime95 version in background.
> But you don't know exactly which FFT sizes are tested.
> 
> I find the latest versions a bit underwhelming for single Core testing.
> He changed something in the FFT sizes, they are clearly all much smaller than before.
> Even with Large testing a Single Core the clock never really boost that high and this is bad for testing the CO count.
> CoreCycler can top 5060 MHz with large FFT sizes on my best Cores, OCCT rarely goes over 4850 MHz.


I can understand that. For me OCCT was just faster and most of the errors happened on low load. I use prime95 first to see the effective clocks anyway. If it failed during high load it would fail right there.


----------



## ManniX-ITA

Luggage said:


> Yea that sounds more effective but a single pass is still 45-58 minutes so a far stretch over “a couple of hours”


Yep but if you go over the first two steps you go there with CO counts very likely already stable so you don't likely need to repeat it again and again


----------



## PJVol

Mach3.2 said:


> Yup, tried both AMD Overclocking menus, no dice. Could be an MSI thing.


Just checked this on MSI board with a 5700G, and indeed, preset limits can't be exceeded with MP1 requests (i suspect this is true for any mailbox type other than APML)
Though it should have already been clear for me, since the mobile based "tuners", such as "ryzen controller", showed exactly the same behavior. It just slipped my mind.


----------



## Taraquin

Audioboxer said:


> View attachment 2548892
> 
> 
> @Veii After an hour of Hi-Z at 1.58v I can't really say I notice any thermal increase. Might just be a reality of being watercooled?
> 
> View attachment 2548896
> 
> 
> 1 hour 30 minutes, still no real increase.


Try the following: 13 13 13, but set ras to 26, rc to 39, rrd/faw to 6/6/24, if it works try a bit lower ras/rc or 5/5/20  Both RC and FAW can impact RCDRD tuning


----------



## Audioboxer

Taraquin said:


> Try the following: 13 13 13, but set ras to 26, rc to 39, rrd/faw to 6/6/24, if it works try a bit lower ras/rc or 5/5/20  Both RC and FAW can impact RCDRD tuning


Seeing as it fails with everything on AUTO, I doubt it lol


----------



## endursa

After countless hours of testing and reading in this thread I think i got my kit dialed as far as it goes 
V-Dimm in bios is set to 1.5V but HWinfo reads 1.52V
CL 14 is out of reach, up to 1.55 V in bios (1.565 in windows) nothing i can do to get it stable.

A few things i do not really get, tRP 14? i can run fine in 12, but is there a real benefit? tRC could be 41 with tRP 12 i guess?
Will try that, if it makes a difference
I am not 100% sure if my tRdWR and tWRRD are best possible, but i cannot go to 8/1 9/1 or 8/2 only 9/2 is stable so far.

with parks up to 1.48 in bios (1.5 in windows) i ran with 0/0/5, just resently changed to 706 for 1.5(1.52V)

Kit should be A1 pcb.

Any further hints what i could try to get cl14? @Veii @anta777 
This is stable 10000% Karhu, Anta Absolut 3 cycles and universal2 as seen in screenshot









next, lets see where PBO and CO will lead me with this 5800x


----------



## Taraquin

Audioboxer said:


> Seeing as it fails with everything on AUTO, I doubt it lol
> 
> View attachment 2548914


2 things: cwl should be 12, 14 can cause issues, also rdwr 9 might help, try those, if no go, then no go


----------



## Melan

I'm getting myself another kit of PVB416G360C7K tomorrow (unless patriot bamboozles me). Was wondering do I need to run 2T with 4 DIMMs? After latest bios update from MSI with agesa 1.2.0.5, 1T became whea-free for me, before it was only GDM or whea error once or twice a week.








This is what I'm running right now. I recon that I'll only need to adjust RttNom, but figured I'd ask if 1T is even going to work.


----------



## Taraquin

Melan said:


> I'm getting myself another kit of PVB416G360C7K tomorrow (unless patriot bamboozles me). Was wondering do I need to run 2T with 4 DIMMs? After latest bios update from MSI with agesa 1.2.0.5, 1T became whea-free for me, before it was only GDM or whea error once or twice a week.
> View attachment 2548915
> 
> This is what I'm running right now. I recon that I'll only need to adjust RttNom, but figured I'd ask if 1T is even going to work.


It may work, but it's harder. You may need to up rdwr by 1. Try 3800?


----------



## Melan

Taraquin said:


> Try 3800?


3800 will not post. Ever.
3733 is error town which I don't want to deal with.


----------



## Taraquin

Melan said:


> 3800 will not post. Ever.
> 3733 is error town which I don't want to deal with.


Okay, what agesa you on? Try 1.2.0.3 b or c. 3666 working?


----------



## Melan

There is no point downgrading agesa because 1.2.0.5 makes 3600 1T stable.
3666 might work with some fiddling but I won't be pushing beyond 3600 until I get 5600x or 5800x3d if it's even worth it.


----------



## Mach3.2

PJVol said:


> Just checked this on MSI board with a 5700G, and indeed, preset limits can't be exceeded with MP1 requests (i suspect this is true for any mailbox type other than APML)
> Though it should have already been clear for me, since the mobile based "tuners", such as "ryzen controller", showed exactly the same behavior. It just slipped my mind.


The power limit can be raised higher than the set point if the limiter under AMD CBS > NBIO > XFR Enhancement is used, that I can confirm. However this requires an unlocked BIOS since MSI doesn't expose the AMD CBS menus on their official BIOS.



Mach3.2 said:


> ManniX-ITA said:
> 
> 
> 
> AMD CBS > NBIO > XFR Enhancement?
> 
> You could try to use a modded BIOS (preparing first the USB stick to recover).
> 
> 
> 
> 
> 
> 
> MSI X570 TOMAHAWK WIFI - Google Drive
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> 
> But it's not really new the latest here...
> 
> 
> 
> We have a winner here, that's it.
> 
> I'm was already running the unlocked v1.70 BIOS, but thanks for the link.
Click to expand...


----------



## PJVol

Mach3.2 said:


> if the limiter under AMD CBS > NBIO > XFR


Really?  I've got PBO settings at two places already, and it turns out there's a 3rd.)


----------



## Mach3.2

PJVol said:


> Really?  I've got PBO settings at two places already, and it turns out there's a 3rd.)


Yup, I think it confirms Veii's theory that MSI's link to the PBO2 power limiters (_Advance > AMD Overclocking_ *and* _Overclocking > Advanced CPU Configuration > AMD Overclocking_) have precedences over AMD's own menus within AMD CBS > NBIO > XFR Enhancements.

Huge thanks to ManniX-ITA and Veii for helping with this mystery. Luggage rightfully pointed out that it doesn't really matter, but it's just triggering my ADHD mind once PJVol comes in with the revelation that the limits can indeed be set above the BIOS setpoints...


----------



## TMavica

Look like something interrupted my tm5 test and cause timeout. I tried run in safe mode, it works perfectly . Is it ok to run tm5 in safe mode?


----------



## Luggage

Mach3.2 said:


> Yup, I think it confirms Veii's theory that MSI's link to the PBO2 power limiters (_Advance > AMD Overclocking_ *and* _Overclocking > Advanced CPU Configuration > AMD Overclocking_) have precedences over AMD's own menus within AMD CBS > NBIO > XFR Enhancements.
> 
> Huge thanks to ManniX-ITA and Veii for helping with this mystery. Luggage rightfully pointed out that it doesn't really matter, but it's just triggering my ADHD mind once PJVol comes in with the revelation that the limits can indeed be set above the BIOS setpoints...


@PJVol @Veii
As an curiosity - can you raise PBO limits above what’s set in bios with Ryzen Master on other brand motherboards (not MSI)?


----------



## Luggage

ManniX-ITA said:


> Also 28 iterations of what?
> 
> SSE Large?
> 
> It's a lot of wasted time probably.
> 
> You need to test all FFT sizes, at least with SSE.
> Better with AVX and AVX2 too if you have the time.
> 
> If you spend a bit of time messing with the ini it'll save a lot of testing time...
> 
> Do a quick run with:
> 
> runtimePerCore = 6m
> FFTSize = 720-720
> 
> 3-4 cycles and you have a first quick check, very unstable cores will fail in 1-2 minutes.
> 
> Then a more through check with higher max frequency:
> 
> runtimePerCore = auto
> FFTSize = 16000-27000
> 
> This will take about 5 minutes per Core.
> Between 5-10 cycles and you have almost all unstable Core already in the net.
> 
> After you passed it you need to go over all FFTs, this is a nighttime test.
> 
> runtimePerCore = auto
> FFTSize = All
> 
> Now you can be pretty confident all cores stable.
> But not 100% sure.
> 
> If you want to be sure do it again changing to:
> 
> mode = AVX
> 
> And then with:
> 
> mode = AVX2


Just checked - that was 22h of "# Huge: 8960K to MAX" boosting to 5035-5050


----------



## ManniX-ITA

Luggage said:


> Just checked - that was 22h of "# Huge: 8960K to MAX" boosting to 5035-5050


Yes, not very useful indeed.

Prime95 doesn't run FFTs in sequence.

*# - Prime95 "Huge": 8960K to MAX - [SSE] ~13-19 Minutes *<|> [AVX] ~27-40 Minutes <|> [AVX2] ~33-51 Minutes

Limited to 6 minutes per Core it did test only half to a fourth of the FFTs, randomly between 8960K and the Max.

Every FFT size poses a different challenge to the CPU.
You need to test them all to be sure it's stable.

Much better to test the 720-720 continuously first, it's a specific challenge and then manual stripes with Auto to be sure the whole range is tested.


----------



## Luggage

ManniX-ITA said:


> Yes, not very useful indeed.
> 
> Prime95 doesn't run FFTs in sequence.
> 
> *# - Prime95 "Huge": 8960K to MAX - [SSE] ~13-19 Minutes *<|> [AVX] ~27-40 Minutes <|> [AVX2] ~33-51 Minutes
> 
> Limited to 6 minutes per Core it did test only half to a fourth of the FFTs, randomly between 8960K and the Max.
> 
> Every FFT size poses a different challenge to the CPU.
> You need to test them all to be sure it's stable.
> 
> Much better to test the 720-720 continuously first, it's a specific challenge and then manual stripes with Auto to be sure the whole range is tested.


Trying your way now, 720 boosts to 4915-4970 eff with silent pumps 

Saw someone mention a corecycler:y-cruncher setting that gave quick results - but can't remember what thread and searching this whole forum is a pain :/


----------



## Bloax

endursa said:


> Any further hints what i could try to get cl14?
> View attachment 2548913
> 
> 
> next, lets see where PBO and CO will lead me with this 5800x


Judging by the L3 latency at 4850 Mhz, you're losing performance from too much SOC/IOD/CCD voltage - exactly how much voltage on each rail, is anyone's guess. 🤡








Unfortunately the exact screenshot I'm looking for got lost in the sands of time - but 4750 Mhz at 1900 FCLK outputs 10.5 ns with fully dialed-in voltages, which I only remember because going from 1900->2000 on that board resulted in +0.02ns on L3

The only reliable method for bruteforcing the voltages I found is described here: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


As for tCL 14 - there's tRP 12->14 ..
There's also trying out raising 1.8v (VDD18, CPU 1.8v, many names) to something higher to see if procODT 30 runs -
that certainly let me run RRD 4/6 and WTR 4/12 again instead of 6/12, which was a weird quirky result of updating to AGESA 1202 (1203?) where the stable procODT at 1.8v = 1.8v went from 32->34.3, as well as requiring upping RRD 4/6->6/12 and WTR_s 4->6



Besides trying that, I would be surprised if single-rank b-die sticks wouldn't run RRD_L 4, they usually tend to hold that even at 4000+ MT/s


Ah!
And I've got bad news in regards to PBO - it requires CPPC (& Preferred Cores) enabled, which has an even greater impact on overall "system responsiveness" than SMT :- )
So the primary benefit of cranking cores very hard - some sort of "improvement" in "responsiveness" - is only possible if you eat a latency penalty that is never gained back.

ergo if you just want a speedy system, you keep CPPC disabled and run the best per-CCX frequency your CPU does in whatever you want the speedy system to run
(which Curve Offsets _can_ help with through equalizing the VID of all the cores)


----------



## Frosted racquet

Luggage said:


> Trying your way now, 720 boosts to 4915-4970 eff with silent pumps
> 
> Saw someone mention a corecycler:y-cruncher setting that gave quick results - but can't remember what thread and searching this whole forum is a pain :/


I don't know if we saw the same post with the suggestion, but it's:
mode = 19-ZN2 ~ Kagari (under the section # y-Cruncher specific settings)
The user suggested numberOfThreads = 2 as well but I haven't verified if it's actually beneficial to run SMT, as it may reduce effective clocks. Compare and see.


----------



## PJVol

Luggage said:


> can you raise PBO limits above what’s set in bios with Ryzen Master


I'm pretty sure RM uses rsmu or mp1 mailbox and this shouldn't change anything, but i gonna try nevertheless, despite it's not a good idea to install rm in my pc all this time.


----------



## Luggage

Bloax said:


> Judging by the L3 latency at 4850 Mhz, you're losing performance from too much SOC/IOD/CCD voltage - exactly how much voltage on each rail, is anyone's guess. 🤡
> 
> View attachment 2548972
> 
> Unfortunately the exact screenshot I'm looking for got lost in the sands of time - but 4750 Mhz at 1900 FCLK outputs 10.5 ns with fully dialed-in voltages, which I only remember because going from 1900->2000 on that board resulted in +0.02ns on L3
> 
> The only reliable method for bruteforcing the voltages I found is described here: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> As for tCL 14 - there's tRP 12->14 ..
> There's also trying out raising 1.8v (VDD18, CPU 1.8v, many names) to something higher to see if procODT 30 runs -
> that certainly let me run RRD 4/6 and WTR 4/12 again instead of 6/12, which was a weird quirky result of updating to AGESA 1202 (1203?) where the stable procODT at 1.8v = 1.8v went from 32->34.3, as well as requiring upping RRD 4/6->6/12 and WTR_s 4->6
> 
> 
> 
> Besides trying that, I would be surprised if single-rank b-die sticks wouldn't run RRD_L 4, they usually tend to hold that even at 4000+ MT/s
> 
> 
> Ah!
> And I've got bad news in regards to PBO - it requires CPPC (& Preferred Cores) enabled, which has an even greater impact on overall "system responsiveness" than SMT :- )
> So the primary benefit of cranking cores very hard - some sort of "improvement" in "responsiveness" - is only possible if you eat a latency penalty that is never gained back.
> 
> ergo if you just want a speedy system, you keep CPPC disabled and run the best per-CCX frequency your CPU does in whatever you want the speedy system to run
> (which Curve Offsets _can_ help with through equalizing the VID of all the cores)


High L3 latency can also just be low EDC or some back ground service - like rgb or sensor software, in my case aquasuite...



http://imgur.com/a/tD7HmIm











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Cam happen, look at the which test window has a red background: Ok Errors are errors, the only good result is that without errors! :D I suspected that was the truth... 70c is really really high... I wouldn't step up VDIMM. Can't you improve the case airflow? I'm in almost the worst...




www.overclock.net


----------



## MrHoof

@Luggage tRDWR 8, tWR 12 and tWTRL 8/9 not stable? How unlucky is that kit


----------



## Luggage

MrHoof said:


> @Luggage tRDWR 8, tWR 12 and tWTRL 8/9 not stable? How unlucky is that kit


Don't know - got bummed about tRCDRD not liking 14. So just set something from Antas comments that was stable and performed ok and didn't tune more...


----------



## Luggage

ManniX-ITA said:


> Yes, not very useful indeed.
> 
> Prime95 doesn't run FFTs in sequence.
> 
> *# - Prime95 "Huge": 8960K to MAX - [SSE] ~13-19 Minutes *<|> [AVX] ~27-40 Minutes <|> [AVX2] ~33-51 Minutes
> 
> Limited to 6 minutes per Core it did test only half to a fourth of the FFTs, randomly between 8960K and the Max.
> 
> Every FFT size poses a different challenge to the CPU.
> You need to test them all to be sure it's stable.
> 
> Much better to test the 720-720 continuously first, it's a specific challenge and then manual stripes with Auto to be sure the whole range is tested.


Yea so that took 2,5h  



Code:


Starting the CoreCycler...
--------------------------------------------------------------------------------
-------------- CoreCycler v0.8.2.4 started at 2022-02-17 21:06:41 --------------
--------------------------------------------------------------------------------
Log Level set to: ......... 2 [Writing debug messages to log file]
Stress test program: ...... PRIME95
Selected test mode: ....... SSE
Logical/Physical cores: ... 16 logical / 8 physical cores
Hyperthreading / SMT is: .. ON
Selected number of threads: 1
Runtime per core: ......... 6 MINUTES
Suspend periodically: ..... ENABLED
Restart for each core: .... OFF
Test order of cores: ...... DEFAQULT
Number of iterations: ..... 10000
Selected FFT size: ........ 720-720 (720K - 720K)

***cut***

ERROR: 23:34:00
ERROR: Prime95 seems to have stopped with an error!
ERROR: At Core 0 (CPU 0)
ERROR MESSAGE: FATAL ERROR: Rounding was 0.5, expected less than 0.4
ERROR: The error likely happened at FFT size 720K

23:35:57 - Terminating the script...
------ Summary ------
The script ran for 02 hours, 29 minutes, 20 seconds
The following cores have thrown an error:
 - 0

Gonna try OCCT now without fixing the core...


----------



## MrHoof

Well that are my results you have some headroom left dont think all of the gains are from trcdrd being 1 tick lower.

















Also dont think anta recommended trfc at 247 thats neither multiple of 8 or 16 and dont think he either suggested tRC=tRAS+tRP+2 (not sure on this one).


----------



## Luggage

MrHoof said:


> Well that are my results you have some headroom left dont think all of the gains are from trcdrd being 1 tick lower.
> View attachment 2548977
> View attachment 2548978
> 
> 
> 
> Also dont think anta recommended trfc at 247 thats neither multiple of 8 or 16 and dont think he either suggested tRC=tRAS+tRP+2 (not sure on this one).


Had to check - apparently I had made some changes since whose old screenshots.
How much does your performance drop if you just change to 2T?
Might go back to ram after I reset my CO curve...


----------



## MrHoof

Nvm for 2T results are pretty similiar just copy has still a edge. Maybe worth to try 1T with setup timings Msi does not like to run 1T without.


----------



## PJVol

@Luggage
Well, RM... all in the screens at the bottom (nothing to add actually to what's already said).
The new to me was that it's polling SMU (via rsmp mailbox) with a 1 sec. interval to obtain current scalar, max boost and pm_table supposedly to get other metrics remained.
Uhh, was happy to uninstall it). Actually, I think most of the rsmu commands discovered were obtained by tinkering with RyzenMaster while polling the SMU CMD registrer, which is retaining the last issued cmd code until the next one is received.

Regarding your question about my way of dealing with the CO (considering recent experiments and findings with my X and G cpus):

To date, I'm almost 100% sure that running some scripts or tools that set affinity for one core or cycling through all cores under quite heavy load (FP/SIMD), makes _little to no sense _for setting up CO, let alone wasted time itself.
Basically I came to conclusion, that with this scenario (each core stressed with affinity set) the stability of each core individually not nesessarily mean СPU stability as a whole, i.e. in multicore loads or partially multicore, where some cores may be put into C1/C6.

Much more important is that the reverse is also true, i.e. "CO" tuned so that it is stable 24/7 in any real-world applications, although in per-core stress test some cores crashes (I could have provide some experimental data to back it up later on). So except for the best of two cores of a CCX, with such per-core workload CO magnitude affects its operation differrently than with a regular workload, and functioning CPPC2 preferred cores.
Summing all up, finding the least stable values make sense only for the best pair of cores in each ССD, how to deal with the rest I'll describe below.
Of course, despite my confidence I'm willing to consider any objections on the merits.

And lastly, while setting up the CO, I prefer the method by PJVol, that he posted more than half a year in a local russian forum (pretty long post with spoilers), though i'd have make some adjustments to it by now.
TL;DR based on psm readings in some workload (I used CBR23) I calculate approximate (draft) curve, then using the minimum stable counts for the two best cores, found beforehand, I adjust other counts so as their psm voltages preferably not to exceed much those of the best two in the same type of workload. Thats it.


----------



## Luggage

Luggage said:


> Yea so that took 2,5h
> 
> 
> 
> Code:
> 
> 
> Starting the CoreCycler...
> --------------------------------------------------------------------------------
> -------------- CoreCycler v0.8.2.4 started at 2022-02-17 21:06:41 --------------
> --------------------------------------------------------------------------------
> Log Level set to: ......... 2 [Writing debug messages to log file]
> Stress test program: ...... PRIME95
> Selected test mode: ....... SSE
> Logical/Physical cores: ... 16 logical / 8 physical cores
> Hyperthreading / SMT is: .. ON
> Selected number of threads: 1
> Runtime per core: ......... 6 MINUTES
> Suspend periodically: ..... ENABLED
> Restart for each core: .... OFF
> Test order of cores: ...... DEFAQULT
> Number of iterations: ..... 10000
> Selected FFT size: ........ 720-720 (720K - 720K)
> 
> ***cut***
> 
> ERROR: 23:34:00
> ERROR: Prime95 seems to have stopped with an error!
> ERROR: At Core 0 (CPU 0)
> ERROR MESSAGE: FATAL ERROR: Rounding was 0.5, expected less than 0.4
> ERROR: The error likely happened at FFT size 720K
> 
> 23:35:57 - Terminating the script...
> ------ Summary ------
> The script ran for 02 hours, 29 minutes, 20 seconds
> The following cores have thrown an error:
> - 0
> 
> Gonna try OCCT now without fixing the core...


@rossi594 @ManniX-ITA so far corecycler was faster. Though there might be some other occt settings that works wonders?










As for stable after 2h test?...


----------



## KedarWolf

In the last few weeks I ran Core Cycler 720-720 FFTs 6m 18 hours single thread, then ran it again last night 2 threads, no errors. But I had to completely redo my curve.

I still get around 30400 in Cinebench R23, but lowered several cores some to be fully stable. Windows 11 is super sensitive to borderline unstable overclocks and until I did this, I'd get BSODs often.

It's TM5 usmus 1000% 8 cycles overnight 7 hours stable as well.

brb, I'll take screenshots of what I settled on, actually, I'll Spoiler ALL my major BIOS settings. 

Well, that's frigging annoying, if I choose multiple pictures in the order I want, overclock.net decides to randomize the order when I submit the post. I need to manually add them one at a time. Fix these things, overclock.net. I even bulk renamed them to 1.jpg, 2.jpg, 3.jpg etc and Ctrl clicked each on in the order I want, and it's all messed up. 

The VSOC is misleading, it's actually the below with what it's set at.














Spoiler: BIOS Screenshots In Spoiler


----------



## Taraquin

Bloax said:


> Judging by the L3 latency at 4850 Mhz, you're losing performance from too much SOC/IOD/CCD voltage - exactly how much voltage on each rail, is anyone's guess. 🤡
> 
> View attachment 2548972
> 
> Unfortunately the exact screenshot I'm looking for got lost in the sands of time - but 4750 Mhz at 1900 FCLK outputs 10.5 ns with fully dialed-in voltages, which I only remember because going from 1900->2000 on that board resulted in +0.02ns on L3
> 
> The only reliable method for bruteforcing the voltages I found is described here: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> As for tCL 14 - there's tRP 12->14 ..
> There's also trying out raising 1.8v (VDD18, CPU 1.8v, many names) to something higher to see if procODT 30 runs -
> that certainly let me run RRD 4/6 and WTR 4/12 again instead of 6/12, which was a weird quirky result of updating to AGESA 1202 (1203?) where the stable procODT at 1.8v = 1.8v went from 32->34.3, as well as requiring upping RRD 4/6->6/12 and WTR_s 4->6
> 
> 
> 
> Besides trying that, I would be surprised if single-rank b-die sticks wouldn't run RRD_L 4, they usually tend to hold that even at 4000+ MT/s
> 
> 
> Ah!
> And I've got bad news in regards to PBO - it requires CPPC (& Preferred Cores) enabled, which has an even greater impact on overall "system responsiveness" than SMT :- )
> So the primary benefit of cranking cores very hard - some sort of "improvement" in "responsiveness" - is only possible if you eat a latency penalty that is never gained back.
> 
> ergo if you just want a speedy system, you keep CPPC disabled and run the best per-CCX frequency your CPU does in whatever you want the speedy system to run
> (which Curve Offsets _can_ help with through equalizing the VID of all the cores)


Actually, I can get 10.7n L3 on both 3800cl15 and 4000cl16 even though soc and iod sits 50mv higher at the latter and I use 76W PPT. How? Temp+80mv on VDD18. As long as temp is is similar, then corespeed will be similar, going from 60 to 80C can make you lose 200MHz allcore. I upgraded cooler to D15 and tuned fancurve and now I get exactly same aida L3 and CB23 MC vs 0.1ns L3 in favour of 3800 and 2-300 points CB. Fan runs a tad noisier, that is all, but with low noise adapters I don't mind 100% at 65C+  Before I made the adjustments I lost 50-75MHZ in CB MC, but temp was around 5C higher due to IO-die using more energy. VDD18 should be tuned above 1900fclk.


----------



## Taraquin

MrHoof said:


> Well that are my results you have some headroom left dont think all of the gains are from trcdrd being 1 tick lower.
> View attachment 2548977
> View attachment 2548978
> 
> 
> 
> Also dont think anta recommended trfc at 247 thats neither multiple of 8 or 16 and dont think he either suggested tRC=tRAS+tRP+2 (not sure on this one).


240 is a good value, divideable by 15=16 so perfect for you, he said rc=ras+rp


----------



## Taraquin

KedarWolf said:


> In the last few weeks I ran Core Cycler 720-720 FFTs 6m 18 hours single thread, then ran it again last night 2 threads, no errors. But I had to completely redo my curve.
> 
> I still get around 30400 in Cinebench R23, but lowered several cores some to be fully stable. Windows 11 is super sensitive to borderline unstable overclocks and until I did this, I'd get BSODs often.
> 
> It's TM5 usmus 1000% 8 cycles overnight 7 hours stable as well.
> 
> brb, I'll take screenshots of what I settled on, actually, I'll Spoiler ALL my major BIOS settings.
> 
> Well, that's frigging annoying, if I choose multiple pictures in the order I want, overclock.net decides to randomize the order when I submit the post. I need to manually add them one at a time. Fix these things, overclock.net. I even bulk renamed them to 1.jpg, 2.jpg, 3.jpg etc and Ctrl clicked each on in the order I want, and it's all messed up.
> 
> The VSOC is misleading, it's actually the below with what it's set at.
> 
> View attachment 2549152
> 
> 
> 
> 
> 
> 
> Spoiler: BIOS Screenshots In Spoiler
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Why 19 rp? That's really high, on B-die you should never need rp above cl  set wr to 12 or rtp to 5


----------



## Taraquin

Luggage said:


> Had to check - apparently I had made some changes since whose old screenshots.
> How much does your performance drop if you just change to 2T?
> Might go back to ram after I reset my CO curve...
> 
> View attachment 2548980


It's smart to fully tune ram before messing with CO. On some setups CO is the same no matter how you tune ram, on others it's vety sensitive to ram oc/tuning.


----------



## Audioboxer

If this is true tech journos really need to start asking AMD what the hell they are doing?

It does line up with AGESA 1.2.0.5 trying to screw OCing via voltage limits.

AMD trying to make sure _everyone_ goes Intel it seems.


----------



## PJVol

Audioboxer said:


> If this is true


Wow, how dare they did that...
Until you check it out for yourself, and oops...








y  Paul Alcorn  published December 26, 2020









by Dr. Ian Cutress & Andrei Frumusanu _on November 5, 2020 9:01 AM EST_

As for the rest, I'm curious is this a news for anyone here?


----------



## dk_mic




----------



## Luggage

Audioboxer said:


> View attachment 2549194
> 
> 
> If this is true tech journos really need to start asking AMD what the hell they are doing?
> 
> It does line up with AGESA 1.2.0.5 trying to screw OCing via voltage limits.
> 
> AMD trying to make sure _everyone_ goes Intel it seems.


We have been over this before - less than a week ago. 








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


So i need to enable this one correct ? Yes!




www.overclock.net


----------



## Audioboxer

PJVol said:


> Wow, how dare they did that...
> Until you check it out for yourself, and oops...
> View attachment 2549201
> 
> y  Paul Alcorn  published December 26, 2020
> 
> View attachment 2549203
> 
> by Dr. Ian Cutress & Andrei Frumusanu _on November 5, 2020 9:01 AM EST_
> 
> As for the rest, I'm curious is this a news for anyone here?


So 1usmus talking crap then if it's always said 4800?

AGESA 1.2.0.5 does hurt performance though if you go above 140 EDC, that we do know.


----------



## Luggage

Audioboxer said:


> So 1usmus talking crap then if it's always said 4800?
> 
> AGESA 1.2.0.5 does hurt performance though if you go above 140 EDC, that we do know.


Yes but not boost limit - you just have to use easy benchmarks that don't like high edc, like cpu-z and cb r23


----------



## Audioboxer

Luggage said:


> Yes but not boost limit - you just have to use easy benchmarks that don't like high edc, like cpu-z and cb r23


Sure lol, but it's something AMD are doing they haven't been for years prior for seemingly no reason and there is no changelog to even make it clear if it's intentional.


----------



## Bloax

The on-paper boost frequencies of Zen3 were lower than the in-action observed frequencies, as a response to the Zen2 ""under-achiever"" boost numbers that were a hypothetical peak value rather than an achievable number.

So if they actually clock up to what it says on paper, rather than Stated Boost Value +50, then that is indeed a reduction of over-delivering on what is promised.


The rest of what he's "talking crap" about is entirely true though!


----------



## Veii

Yes it depends,
If peak now is 5.0 instead 5.05 then it has ground (alone that we lost +500 fMAX for no direct reason except hiding V/F curve exceeding 1.5(5) volts and rather taking 1.6+ for it)








if you go even further to 5.15 it requests 1.6+ volts, soo it makes sense to prohibit it ~ else users would cry about overvoltage

Although if stock is 4.8 instead 4.85 , it also makes sense what he said
but it could be just being confused, as he always had a 5950X - i wonder

Navi part is sadly very true
The amount of work put in to limit it on driver level, on bios module level, and on vbios level (3 locks) ~ is overdone, while they struggled to get correctly running drivers out
Some practices indeed are questionable


----------



## Luggage

Bloax said:


> The on-paper boost frequencies of Zen3 were lower than the in-action observed frequencies, as a response to the Zen2 ""under-achiever"" boost numbers that were a hypothetical peak value rather than an achievable number.
> 
> So if they actually clock up to what it says on paper, rather than Stated Boost Value +50, then that is indeed a reduction of over-delivering on what is promised.
> 
> 
> The rest of what he's "talking crap" about is entirely true though!
> View attachment 2549236


Only 5600x is +50 over advertised.
5800X, 5900X and 5950X are +150 over advertised.


----------



## Veii

Luggage said:


> Only 5600x is +50 over advertised.
> 5800X, 5900X and 5950X are +150 over advertised.


Hm ?
5800X boosts instead of 4.7 to 4.75
There are some "newer" batches that are on stock @ 4.8 , and boost to 4.85 (then +200)
But these are "hidden" new batches even on B0 sample


----------



## Luggage

Veii said:


> Hm ?
> 5800X boosts instead of 4.7 to 4.75
> There are some "newer" batches that are on stock @ 4.8 , and boost to 4.85 (then +200)
> But these are "hidden" new batches even on B0 sample


Please. We are locked at +200. We reach 5050. Ergo the stock limit is 4850.



http://imgur.com/mmdm5f6

stock jedec 1203c bg 2050 sus


----------



## kim nk

Audioboxer said:


> The challenge we're after right now is tRCDRD 13 on DR, it appears to be much harder than with SR. Very few people seem to have managed to do it stable. One person in this topic as far as I can see.


The DR kit is going to get a penalty of TWRRD and ADDRCMDSETUP, so TRCDRD 13 I do not know if it exists or not even if it is better to try this. The CL14 4000 ROYAL elite memory has a good voltage yield compared to the overall tightening timing, but the DR kit is very few people who test this at the CL14 4000 to the 14-14-14 timing, which is almost impossible to succeed. Usually, 14-14-14-14 timing is only possible to 3933 clocks .. 2T to ADDRCMDSETUP, but it is difficult to get TFAW 40, but I can not help but see the yield problem. Royal Elite Rams think that if the TRCDRD 14 is not errorless at the 14-14-14-14 timing at 4000 clocks with the SR kit, the TRRDS 4 TRRDL 4 TFAW 16 TRFC 252-187-115 TRDWR 7 TWRRD 1 is a very good RAM with enough timing to pass the TM5 test with memory voltage of 1.50-1.52V ... If this is about 1.52V, it can be finished at 14-15-15-15 timing on 4200 clocks and the voltage is 1.55 ~ 1.58V. But I hope the dual yields are better. The DR kit TRCDRD 13 you're trying to do is not possible at this rate.


----------



## Melan

Taraquin said:


> It may work, but it's harder. You may need to up rdwr by 1.


So, I've tried RDWR 11, but it seems mobo is deadset on WRRD at 4. Auto values for RDWR and WRRD are 9 and 4 respectively.
Should I stick to 9/4 or do 11/4?
This is what I have currently


----------



## Veii

Luggage said:


> Please. We are locked at +200. We reach 5050. Ergo the stock limit is 4850.
> 
> 
> 
> http://imgur.com/mmdm5f6
> 
> stock jedec 1203c bg 2050 sus


Not every 5800X starts at 4.85 boost
Not every 5950X starts at 4.95 boost

Vendor supplied +100 FMax cheatery & X2 scalar on stock ~ excluded


----------



## Luggage

Veii said:


> Not every 5800X starts at 4.85 boost
> Not every 5950X starts at 4.95 boost
> 
> Vendor supplied +100 FMax cheatery & X2 scalar on stock ~ excluded


With cooling and light test load like mannix boost tester?
I only have 1 CPU and two MSI mb so i cant disprove you but the other way is easy. You won’t find anyone going above 5050 since 1201(?) without doing real “shady things”.


----------



## Bloax

My stance on high-frequency Zen3 remains the same;


> I've got bad news in regards to PBO - it requires CPPC (& Preferred Cores) enabled, which has an even greater impact on overall "system responsiveness" than SMT :- )
> So the primary benefit of cranking cores very hard - some sort of "improvement" in "responsiveness" - is only possible if you eat a latency penalty that is never gained back.
> 
> ergo if you just want a speedy system, you keep CPPC disabled and run the best per-CCX frequency your CPU does in whatever you want the speedy system to run
> (which Curve Offsets _can_ help with through equalizing the VID of all the cores)


Unfortunately nothing more than dick-measuring contests.😳

Maybe you'd see proper performance scaling beyond 4700 Mhz (4700->4900 barely shows improvement compared to 4500->4700) with the strict power limits lifted, and an extra 64 MB of L3 to reduce stalling - but with _How Things Are Going on AM4_ that seems unlikely. 🤡🤡


----------



## MrHoof

Luggage said:


> With cooling and light test load like mannix boost tester?
> I only have 1 CPU and two MSI mb so i cant disprove you but the other way is easy. You won’t find anyone going above 5050 since 1201(?) without doing real “shady things”.


Can confirm same for my sample. This is a realease sample bought in the first month yes i overpayed alot.... 








No boost clock overwrite or auto oc or whatever its called. I am not a fan of it cant cool even +25mhz the vid increase is just dumb.


----------



## PJVol

Veii said:


> Not every 5800X starts at 4.85 boost


They have CCLK max set to 4850 by default.


----------



## Luggage

Bloax said:


> My stance on high-frequency Zen3 remains the same;
> 
> Unfortunately nothing more than dick-measuring contests.😳
> 
> Maybe you'd see proper performance scaling beyond 4700 Mhz (4700->4900 barely shows improvement compared to 4500->4700) with the strict power limits lifted, and an extra 64 MB of L3 to reduce stalling - but with _How Things Are Going on AM4_ that seems unlikely. 🤡🤡


Umm, you can turn off CPPC and still run PBO.


----------



## Audioboxer

kim nk said:


> The DR kit is going to get a penalty of TWRRD and ADDRCMDSETUP, so TRCDRD 13 I do not know if it exists or not even if it is better to try this. The CL14 4000 ROYAL elite memory has a good voltage yield compared to the overall tightening timing, but the DR kit is very few people who test this at the CL14 4000 to the 14-14-14 timing, which is almost impossible to succeed. Usually, 14-14-14-14 timing is only possible to 3933 clocks .. 2T to ADDRCMDSETUP, but it is difficult to get TFAW 40, but I can not help but see the yield problem. Royal Elite Rams think that if the TRCDRD 14 is not errorless at the 14-14-14-14 timing at 4000 clocks with the SR kit, the TRRDS 4 TRRDL 4 TFAW 16 TRFC 252-187-115 TRDWR 7 TWRRD 1 is a very good RAM with enough timing to pass the TM5 test with memory voltage of 1.50-1.52V ... If this is about 1.52V, it can be finished at 14-15-15-15 timing on 4200 clocks and the voltage is 1.55 ~ 1.58V. But I hope the dual yields are better. The DR kit TRCDRD 13 you're trying to do is not possible at this rate.


What do you think of this? [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

Just lucky or something dodgy going on to get tRCDRD 13 running at 3800 with DR?

Memory kit is 4000 16-16-16-16 1.4v which is technically a bit lower binned than the 4000 14-15-15-15 1.55v I'm running. No one in this topic running the 4000 14-15-15-15 has been able to do tRCDRD 13 at 3800.


----------



## KedarWolf

Totally off-topic, but you peeps are in my most active forum.

A Samsung Odyssey Neo G9 monitor was on sale for $800 off at a local store, yesterday was the last day of the sale. 5120x1440 49' ultrawide, HDR 2000 GSync/FreeSync, 240Hz screen.

However I don't get my tax refund for another week or so, and they wouldn't hold it that long at the sale price. My sis, who often helps me, couldn't lend me $2000 CAD to get it.

Another store had it on backorder and would lock it in at the sale price for a $200 deposit. So I contacted Memory Express, told them this, the guy talked to the manager and agreed to hold it at the sale price for $200 down. They had one left in stock.

I'm sooooo happy, I'd never be able to get it at the full price which was close to $3000. 

I have a water-cooled Strix OC RTX 3090 to drive it. That resolution works out in total pixels to be about 89% of 4K total pixels.


----------



## KedarWolf

Audioboxer said:


> What do you think of this? [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> Just lucky or something dodgy going on to get tRCDRD 13 running at 3800 with DR?
> 
> Memory kit is 4000 16-16-16-16 1.4v which is technically a bit lower binned than the 4000 14-15-15-15 1.55v I'm running. No one in this topic running the 4000 14-15-15-15 has been able to do tRCDRD 13 at 3800.


I don't think I'd ever run VDIMM at 1.65v, except for brief periods for benching. And that person has an excellent IMC on their CPU, they've posted before. I'm buying the Elite CL14 4000 kit soon, but I doubt it'll be much more than a minor improvement of my CL16 3600 kit as my IMC on my 5950x is average. :/


----------



## PJVol

Bloax said:


> Maybe you'd see proper performance scaling beyond 4700 Mhz (4700->4900 barely shows improvement compared to 4500->4700)


It depends.
AFAIK this scaling derives from the two things: process node characteristics, i.e. performance and density scaling (leakage varies from sample to sample, even between the cores - exposed as the FIT limit) and how well AMD handled Cac distribution among the various IPs throughout the package (switching, purely design dependent + how effective the current power and clock gating implementation is - the good example is the recent sneak peek to a rembrandt architecture, slides from some amd event).
Aside from some minor caveats, if proper cooling applied, I see my sample perf. scaled almost linearly up to 4850, of course as much as EDC manager allows.

PS: Have to agree though, that quick saturation of ccd-iod bandwidth with just two cores accessing the memory still seems to be an arch issue.


----------



## Veii

PJVol said:


> They have CCLK max set to 4850 by default.


Lucky, can't find it
Wonder if Bloax still has the old screenshots before AGESA 1.2.0.0

I'll leave it be ~ can be again one of those odd samples (as i've seen only such)
Certainly was surprised to see it running 4.85 instead of 4.75
Guess it remains in memory & i'll agree with you ~ for now
Google shows me more than enough examples of 4.85 stock, as it seems


----------



## Kha

Veii said:


> Yes it depends,
> If peak now is 5.0 instead 5.05 then it has ground (alone that we lost +500 fMAX for no direct reason except hiding V/F curve exceeding 1.5(5) volts and rather taking 1.6+ for it)
> 
> 
> 
> 
> 
> 
> 
> 
> if you go even further to 5.15 it requests 1.6+ volts, soo it makes sense to prohibit it ~ else users would cry about overvoltage
> 
> Although if stock is 4.8 instead 4.85 , it also makes sense what he said
> but it could be just being confused, as he always had a 5950X - i wonder
> 
> Navi part is sadly very true
> The amount of work put in to limit it on driver level, on bios module level, and on vbios level (3 locks) ~ is overdone, while they struggled to get correctly running drivers out
> Some practices indeed are questionable


I think there are only 2 variants here. Either AMD is afraid that higher boosts will degrade their chips, or they really don't want people with smaller / cheaper products to reach higher boosts as their bigger brothers do.


----------



## Audioboxer

KedarWolf said:


> I don't think I'd ever run VDIMM at 1.65v, except for brief periods for benching. And that person has an excellent IMC on their CPU, they've posted before. I'm buying the Elite CL14 4000 kit soon, but I doubt it'll be much more than a minor improvement of my CL16 3600 kit as my IMC on my 5950x is average. :/


I wonder if it's the IMC that really helps out here! 

And congrats on the monitor, once you go UW you never go back!

My next move will likely be 34" UW to 38" UW to get a bit more vertical space.


----------



## KedarWolf

Audioboxer said:


> I wonder if it's the IMC that really helps out here!
> 
> And congrats on the monitor, once you go UW you never go back!
> 
> My next move will likely be 34" UW to 38" UW to get a bit more vertical space.


I sold my 49" Samsung 3840x1080 for $900 CAD today.


----------



## Kha

Audioboxer said:


> My next move will likely be 34" UW to 38" UW to get a bit more vertical space.


Would kill for a good 38 inch but they don't exist...


----------



## Audioboxer

Kha said:


> Would kill for a good 38 inch but they don't exist...


Alienware 38 Curved Gaming Monitor - AW3821DW | Dell USA is pretty good.

And there is a 38" LG that is rated highly.


----------



## dk_mic

Audioboxer said:


> Alienware 38 Curved Gaming Monitor - AW3821DW | Dell USA is pretty good.
> 
> And there is a 38" LG that is rated highly.


I have that AW and really like it. The LG 38GN950-B has the same panel. Differences are gsync ultimate on the Dell, up to 144 Hz and freesync premium pro on the LG up to 160 Hz. Warranty and build quality are eventually better on the AW. Was quite surprised how well my 2080 Ti still pushes enough frames.
Screen size feels perfect for working and gaming. Considered Samsung G9, but really like the vertical space on 38"


----------



## kim nk

Audioboxer said:


> What do you think of this? [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> Just lucky or something dodgy going on to get tRCDRD 13 running at 3800 with DR?
> 
> Memory kit is 4000 16-16-16-16 1.4v which is technically a bit lower binned than the 4000 14-15-15-15 1.55v I'm running. No one in this topic running the 4000 14-15-15-15 has been able to do tRCDRD 13 at 3800.


Yes. It's lucky draw. At 4000 clocks, the clkdrvstr value is low and the 14-14-14-14 real 1t timing must pass the tm5 test without addrcmdsetup penalty to pass 3800 cl13 -13-13-13 tfaw 32~48. The higher the yield, the higher the tfaw value It gets lower.








was able to lower the kit with the lowest tfaw to 32 in the 13-13-13-13 timing. (cpu, motherboard same) Another kit had a limit of tfaw 40, and another kit had a limit of 48, and each RAM had a different limit. In the end, it was luck


----------



## Bloax

Luggage said:


> Umm, you can turn off CPPC and still run PBO.


If you can turn off CPPC and run PBO, then CPPC is not turned off.

PBO power limits, which are still respected regardless of whether you run PBO or not, can still be changed with CPPC disabled -
but PB(O) relies upon the CPPC metadata, the book-keeping of which causes the aforementioned increase in Processor Latency, to do its boosting decisions.

Which is to say - if you disable CPPC, the processor is stuck at its base frequency until you tell it otherwise with a Manual Frequency override (per-ccx clock).


----------



## gameinn

I have a dual rank 3600C16 1.35v B-Die kit from G. Skill. F4-3600C16D-32GTZN

I know it's not the best bin but I was hoping to get my aida64 latency down to high 58ns on my 5950x with some manual tuning. XMP has it at ~60.8ns so always being below 60ns would be a decent target.

Is there like a universally safe profile to dial in values for such a kit? I know my CPU is safe at 1800 fclk so I don't want to go higher and I doubt I need to in order to ensure under 60ns. I'm thinking some 3600C14 profile should do it around 1.45v?


----------



## Luggage

Bloax said:


> If you can turn off CPPC and run PBO, then CPPC is not turned off.
> 
> PBO power limits, which are still respected regardless of whether you run PBO or not, can still be changed with CPPC disabled -
> but PB(O) relies upon the CPPC metadata, the book-keeping of which causes the aforementioned increase in Processor Latency, to do its boosting decisions.
> 
> Which is to say - if you disable CPPC, the processor is stuck at its base frequency until you tell it otherwise with a Manual Frequency override (per-ccx clock).


So how do you turn OFF cppc?
Disable - pbo still works. boost still works, sc get sent to the wrong cores, (edit) hwinfo cant read cppc value.





http://imgur.com/a/KWhQxpL


----------



## KedarWolf

My MSI X570S Unify-X Max. 2x16GB CL16 3600 RAM.

But I'm getting CL14 4000 Royal Elite soon. I honestly don't think my CPU IMC is good enough for other new RAM to really make a big difference though. 

That was 1000%, 8 cycles overnight.


----------



## KedarWolf

gameinn said:


> I have a dual rank 3600C16 1.35v B-Die kit from G. Skill. F4-3600C16D-32GTZN
> 
> I know it's not the best bin but I was hoping to get my aida64 latency down to high 58ns on my 5950x with some manual tuning. XMP has it at ~60.8ns so always being below 60ns would be a decent target.
> 
> Is there like a universally safe profile to dial in values for such a kit? I know my CPU is safe at 1800 fclk so I don't want to go higher and I doubt I need to in order to ensure under 60ns. I'm thinking some 3600C14 profile should do it around 1.45v?


I have the same RAM and a 5950x. See here. I get 54.5ns with Windows 10, 55ns with Windows 11, but Windows 11 always does worse on benchmarks for me. I like the HDR options in it though, so I use it.









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


I wonder if it's the IMC that really helps out here! And congrats on the monitor, once you go UW you never go back! My next move will likely be 34" UW to 38" UW to get a bit more vertical space. I sold my 49" Samsung 3840x1080 for $900 CAD today. :)




www.overclock.net





Edit: See here for important BIOS settings to get that. VSOC in BIOS is now at 1.21 though.









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


@Luggage tRDWR 8, tWR 12 and tWTRL 8/9 not stable? How unlucky is that kit :oops:




www.overclock.net


----------



## KedarWolf




----------



## Bloax

Luggage said:


> So how do you turn OFF cppc?
> Disable - pbo still works. boost still works, sc get sent to the wrong cores, (edit) hwinfo cant read cppc value.


Looks like MSI doesn't want to turn it off - maybe if you turn off various boosting-related things (like Core Performance Boost) it'll finally get the hint.

It was super simple on the Asrock board I previously used, so I guess that explains the results I got in LatencyMon while dialing in the not-actually-used Unify-X system.


----------



## gameinn

@KedarWolf Does your 5950x also take a ridiculously long time to complete the memory section benchmark? I didn't observe this behavior on single ccd. My memory read number takes like 50 seconds to be displayed after clicking start benchmark. Memory write displays at 1 minute 12 seconds. 2 minutes 5 seconds for copy and latency finishes at 2 minutes 18 seconds.


----------



## Luggage

Bloax said:


> Looks like MSI doesn't want to turn it off - maybe if you turn off various boosting-related things (like Core Performance Boost) it'll finally get the hint.
> 
> It was super simple on the Asrock board I previously used, so I guess that explains the results I got in LatencyMon while dialing in the not-actually-used Unify-X system.


How do you check that cppc is off?

Of course if you turn off core performance boost you get stuck at base speed - that's what _that_ setting does.

Edit: cppc disabled


Code:


Processor 0 in group 0 exposes the following power management capabilities:

Idle state type: ACPI Idle (C) States (2 state(s))

Performance state type: ACPI Performance (P) / Throttle (T) States
Nominal Frequency (MHz): 3800
Maximum performance percentage: 100
Minimum performance percentage: 57
Minimum throttle percentage: 57

Processor 2 in group 0 exposes the following power management capabilities:

Idle state type: ACPI Idle (C) States (2 state(s))

Performance state type: ACPI Performance (P) / Throttle (T) States
Nominal Frequency (MHz): 3800
Maximum performance percentage: 100
Minimum performance percentage: 57
Minimum throttle percentage: 57

Processor 4 in group 0 exposes the following power management capabilities:

Idle state type: ACPI Idle (C) States (2 state(s))

Performance state type: ACPI Performance (P) / Throttle (T) States
Nominal Frequency (MHz): 3800
Maximum performance percentage: 100
Minimum performance percentage: 57
Minimum throttle percentage: 57

Processor 6 in group 0 exposes the following power management capabilities:

Idle state type: ACPI Idle (C) States (2 state(s))

Performance state type: ACPI Performance (P) / Throttle (T) States
Nominal Frequency (MHz): 3800
Maximum performance percentage: 100
Minimum performance percentage: 57
Minimum throttle percentage: 57

Processor 8 in group 0 exposes the following power management capabilities:

Idle state type: ACPI Idle (C) States (2 state(s))

Performance state type: ACPI Performance (P) / Throttle (T) States
Nominal Frequency (MHz): 3800
Maximum performance percentage: 100
Minimum performance percentage: 57
Minimum throttle percentage: 57

Processor 10 in group 0 exposes the following power management capabilities:

Idle state type: ACPI Idle (C) States (2 state(s))

Performance state type: ACPI Performance (P) / Throttle (T) States
Nominal Frequency (MHz): 3800
Maximum performance percentage: 100
Minimum performance percentage: 57
Minimum throttle percentage: 57

Processor 12 in group 0 exposes the following power management capabilities:

Idle state type: ACPI Idle (C) States (2 state(s))

Performance state type: ACPI Performance (P) / Throttle (T) States
Nominal Frequency (MHz): 3800
Maximum performance percentage: 100
Minimum performance percentage: 57
Minimum throttle percentage: 57

Processor 14 in group 0 exposes the following power management capabilities:

Idle state type: ACPI Idle (C) States (2 state(s))

Performance state type: ACPI Performance (P) / Throttle (T) States
Nominal Frequency (MHz): 3800
Maximum performance percentage: 100
Minimum performance percentage: 57
Minimum throttle percentage: 57


----------



## KedarWolf

gameinn said:


> @KedarWolf Does your 5950x also take a ridiculously long time to complete the memory section benchmark? I didn't observe this behavior on single ccd. My memory read number takes like 50 seconds to be displayed after clicking start benchmark. Memory write displays at 1 minute 12 seconds. 2 minutes 5 seconds for copy and latency finishes at 2 minutes 18 seconds.


50s, 1:10 for the first two, I had an online stopwatch running but I don't remember the last two.


----------



## KedarWolf

KedarWolf said:


> 50s, 1:10 for the first two, I had an online stopwatch running but I don't remember the last two.


48, 1:08, 1:50, 2:08.


----------



## Audioboxer

kim nk said:


> Yes. It's lucky draw. At 4000 clocks, the clkdrvstr value is low and the 14-14-14-14 real 1t timing must pass the tm5 test without addrcmdsetup penalty to pass 3800 cl13 -13-13-13 tfaw 32~48. The higher the yield, the higher the tfaw value It gets lower.
> View attachment 2549322
> 
> was able to lower the kit with the lowest tfaw to 32 in the 13-13-13-13 timing. (cpu, motherboard same) Another kit had a limit of tfaw 40, and another kit had a limit of 48, and each RAM had a different limit. In the end, it was luck


That DR ram is at tFAW 16 AND it's using setup times 😱


----------



## kim nk

Audioboxer said:


> That DR ram is at tFAW 16 AND it's using setup times 😱


Although it is Intel, there is also a Royal Elite Ram that can clock 14-14-14-14 DR 4000 clock. It would be nice if ERAM came to Ryzen, but it is RAM from an acquaintance, but I can't take it


----------



## Kha

Audioboxer said:


> Alienware 38 Curved Gaming Monitor - AW3821DW | Dell USA is pretty good.
> 
> And there is a 38" LG that is rated highly.


They don't have usable local dimming (just some terrible edge-lit band zones, 12 in case of LG, 32 in case of AW, flickering like crazy in many given scenarios and rendering HDR pretty much useless).

Since they are using same LG panel, their contrast is also insanely poor (around 900 :1 in case of LG, a bit worse in case of AW). On top of that, they have severe IPS glow and because of no DSC, their refresh is limited at 120hz if you go 10 bit.

Each to his own, but in my book neither of them worth more than 700-800 usd, let alone the 1500-1800 usd premium that most etailers are selling them for.


----------



## PJVol

Luggage said:


> So how do you turn OFF cppc?


He seem to confused CPPC with CPB.
I just realized what he was talking about before 


Bloax said:


> If you can turn off CPPC


Please, don't misuse these terms, it's hard to understand your thoughts otherwise. CPPC is АСPI feature. CPB is part of amd's Application Power Management (APM or PB) along with the modern infrastructure limit based restricting


----------



## Noxion

With bios 4002 I boot into efi shell and do dmpstore -all -d which clears all settings and then set all my settings again and I’m getting 625 gflops in linpackxtreme instead of 620 and 29990 cinebench r23 instead of 29600 there must be some settings in efi that aren’t cleared. Or maybe it could be attributed to changing CPU/SOC LLC to 1 and global c-states to auto.


----------



## PJVol

Noxion said:


> I boot into efi shell and do dmpstore


Oh... we should wait for @ManniX-ITA to try it. May be this could get his CPU perf. back to 1203c level (and @Veii too, in attempt to revive his two lost cores)


----------



## ManniX-ITA

PJVol said:


> Oh... we should wait for @ManniX-ITA to try it.


Try what?  
Now I'm curious...


----------



## Audioboxer

Kha said:


> They don't have usable local dimming (terrible edge lit band zones, 12 in case of LG, 32 in case of AW, both flickering like crazy in given scenarios and rendering HDR useless).
> Because they are using same LG panel, the contrast is also insanely poor (around 900 :1 in case of LG, a bit worse in case of AW).
> On top of that, they have severe IPS glow and because of no DSC, the refresh is limited at 120hz if you go 10 bit.
> 
> Each to his own, but in my book neither of them worth more than 700-800 usd, let alone the 1500-1800 usd premium that most etailers are selling them for.


Yeah the IPS lottery is why I ultimately ended up with a VA 34" UW. It has basically no light bleed and _amazing_ contrast. Viewing angles worse and maybe not colours that pop as much as IPS but I'm super sensitive to light bleed/glow and prioritised not worrying about it over the colour accuracy of IPS. I don't play super twitchy FPS games and I honestly don't notice smearing/blur with VA. 144hz panel.

My name drop of that monitor and the LG was really more a case of "If you want a 38" UW, these are really your only two decent options".

Probably going to stick to this monitor until the monitor industry really has a change from the long fought battle of IPS vs VA. We really need to crack the OLED for screens this size, whatever the name of the tech ends up being (I know there are some monitors coming through now). Then wait patiently for reasonable consumer prices lol.

Actual HDR monitors are a rip off and a few of them need damn fans to cool them, if not all of them. Out of everything in the PC industry that truly needs an overhaul, it's monitors. Nearly all other components have had big steps forward in the past 5 years+. Monitors still lingering with older tech "patched up" to try and push refresh rate and for what you get tech wise, very overpriced (at the top end).



kim nk said:


> Although it is Intel, there is also a Royal Elite Ram that can clock 14-14-14-14 DR 4000 clock. It would be nice if ERAM came to Ryzen, but it is RAM from an acquaintance, but I can't take it
> 
> View attachment 2549357


IIRC my kit was showing promise for 4000 14-14-14-14 but I didn't spend too long on it because I can't get FCLK 2000 properly stable.

I guess I could run it out of sync and play with it at 4000, seeing as I've already done that for 4533.

4400 15-15-15-15 works as well which is decent. 4533 needs 16-16-16-16.


----------



## Luggage

ManniX-ITA said:


> Try what?
> Now I'm curious...


This i guess









Asus Crosshair VIII DARK Hero.... Official Thread!?


Offficial page has beta 4002 now. ROG CROSSHAIR VIII DARK HERO BIOS 4002 "1.Update AMD AM4 AGESA V2 PI 1.2.0.6b




www.overclock.net


----------



## Taraquin

KedarWolf said:


> My MSI X570S Unify-X Max. 2x16GB CL16 3600 RAM.
> 
> But I'm getting CL14 4000 Royal Elite soon. I honestly don't think my CPU IMC is good enough for other new RAM to really make a big difference though.
> 
> That was 1000%, 8 cycles overnight.
> 
> View attachment 2549345


I pointed out earlier that some of your RP is way off, rfc should be 256 or 240, WR should be 2 x RTP so fix one of them. I bet you get a performance boost if you fix this. Getting a new kit won`t help if your timings are weird


----------



## Noxion

I used the instructions here to get efi shell working. https://superuser.com/questions/1057446/how-do-i-boot-to-uefi-shell


----------



## gameinn

@KedarWolf I don't know how much I want to get into RAM OC so I am just thinking of getting a 3600C14 XMP kit. What type of latency and numbers are you seeing in aida64 if you just set 3600 14-14-14-34 like XMP would? My kit doesn't run this.


----------



## Bloax

PJVol said:


> He seem to confused CPPC with CPB.
> I just realized what he was talking about before
> 
> Please, don't misuse these terms, it's hard to understand your thoughts otherwise. CPPC is АСPI feature. CPB is part of amd's Application Power Management (APM or PB) along with the modern infrastructure limit based restricting


I don't misuse the terms or talk about CPB - I am merely describing what I witnessed with my own eyes on an Asscock board.

It is entirely possible that what "disabling CPPC + CPPC Preferred Cores" on said Asrock board did, actually changed much more than just those settings.
Recreating it is a matter of throwing **** at the wall, and seeing whether it sticks. That is all that disabling CPB is - I have no clue if that would do it, testing it would be a massive pain (in my situation).

All I can tell you is that it broke boosting (CPU sits at base frequency), and had a noticeable impact on everyone's favorite Le Meme Mouse Input Responsiveness(tm) metric - just as disabling SMT does.

As I am just as bewildered as you that disabling something _so seemingly innocuous_ would result in such drastic improvements.


----------



## domdtxdissar

@PJVol

Your tool is suddenly implemented into hydra..


----------



## PJVol

@domdtxdissar
If you're communicating, tell him "не прошло и года..." 
(it's hard to say in english)


----------



## Luggage

Bloax said:


> I don't misuse the terms or talk about CPB - I am merely describing what I witnessed with my own eyes on an Asscock board.
> 
> It is entirely possible that what "disabling CPPC + CPPC Preferred Cores" on said Asrock board did, actually changed much more than just those settings.
> Recreating it is a matter of throwing **** at the wall, and seeing whether it sticks. That is all that disabling CPB is - I have no clue if that would do it, testing it would be a massive pain (in my situation).
> 
> All I can tell you is that it broke boosting (CPU sits at base frequency), and had a noticeable impact on everyone's favorite Le Meme Mouse Input Responsiveness(tm) metric - just as disabling SMT does.
> 
> As I am just as bewildered as you that disabling something _so seemingly innocuous_ would result in such drastic improvements.


Asrock doing asrock things


Turn off CPPC (core rankings)
CPU stops boosting at all.


----------



## Audioboxer

domdtxdissar said:


> @PJVol
> 
> Your tool is suddenly implemented into hydra..
> View attachment 2549367
> 
> 
> View attachment 2549365


So 1usmus looked at PJVol's app/code?

I really wish this scene wasn't so backstabby at times.

Funny thing is chances are if people communicate most work together anyway! But given Hydra Pro is paid software that's where it also gets more complicated. Given many in the community _work for free_ or strictly donation only.

Nothing wrong with paid software in of itself, but if you do take from others without permission and then charge for it, that can be in bad taste.


----------



## PJVol

Audioboxer said:


> So 1usmus looked at PJVol's app/code?


I don't think he really need to, 'cause i'm sure he knows well the implementation details himself. 
Just his window of opportunity for the project promotion boost.


----------



## mirzet1976

domdtxdissar said:


> @PJVol
> 
> Your tool is suddenly implemented into hydra..
> View attachment 2549367
> 
> 
> View attachment 2549365


I don't see a 1.1D hydra on the patreon for download.


----------



## Bloax

Now, if only in-OS IOD/CCD voltage adjustment was a thing...


----------



## Luggage

MrHoof said:


> Nvm for 2T results are pretty similiar just copy has still a edge. Maybe worth to try 1T with setup timings Msi does not like to run 1T without.
> 
> View attachment 2548982


Well I had to try such small tweaks 
Slight improvements in read and copy so basically same as yours.
Doubt I have the patience to try 1t again...



http://imgur.com/zQgf7mI


did 25 cycles of v3 but I'll test some more over night


----------



## Audioboxer

PJVol said:


> I don't think he really need to, 'cause i'm sure he knows well the implementation details himself.
> Just his window of opportunity for the project promotion boost.


I suppose that's not quite as bad then, just opportunistic rather than taking your code or something.


----------



## 1usmus

domdtxdissar said:


> @PJVol
> 
> Your tool is suddenly implemented into hydra..
> View attachment 2549367
> 
> 
> View attachment 2549365



There is no need to make a hype out of it. Information about communicating with SMU is present in a number of GitHub projects and even in ASUS tool 1007. I have NDA documents available to me which contain information about it. The HYDRA project is the successor to CTR, it didn't appear after the forum members you want to engage in discussion. I respect the enthusiasts' author projects, but the communication with SMU is AMD's property. And most importantly it will be available to everyone.This feature, the screenshot of which you posted, will not become the domain of "special enthusiasts".

In particular, I am grateful to PjVol for stimulating the competition. I'll be sure to mention this guy when I release this update.


----------



## Veii

PJVol said:


> Oh... we should wait for @ManniX-ITA to try it. May be this could get his CPU perf. back to 1203c level (and @Veii too, in attempt to revive his two lost cores)


There's no direct way
Ones that are on 550mhz, are empty vassels
They lack brain cells, lack MSR addressing, lack anything
The only thing they know , is that lowest idle state and (i think but not 100% confident) - also to stay on 900mV or whatever dLDO supplies (IF dLDO even factors them in)
Hence they do not wiggle and not do anything - unless other funny things like this one








* it's still in question if SMU commands received can even be corrupted and wrong ~ or everything you receive is correct accuracy although delayed 

But no, there is no way for X user to fix what AMD locked ~ via normal operation
On bios boot, up to SKU a microcode patch is loaded ontop of current microcode.
And only if this patch is non existent, ROM based (bios) microcode is loaded afterwards.

In order to ever "fix" this , or rather unlock
You would need to track back the usage traces on the CPU itself, and reflash the coretex firmware on it
Two of my CPUs have usage traces, but are too minuscule for me to bother and potentially hardbrick my sample ~ if i hit wrong pins 
The answer is pretty much, no 
Locks sit on the ARM chip, and on MSR level.

Unless something completely different is ment with "revive lost cores"
The chance to "revert" the 16 to 6c patch and get it back as unknown 14 core CPU , is far higher than to put brain cells into permanently erased vessels (cores)
Yet both are minuscule tiny chance and surely won't be possible without ARM chip reflash 
(unless PSP-TOOL still functions, but PSPTool doesn't have such low access and would need to white-list flash something modified to PSP-FW ~ chance , lower than figuring out chip pinnout)


----------



## Veii

PJVol said:


> Oh... we should wait for @ManniX-ITA to try it. May be this could get his CPU perf. back to 1203c level (and @Veii too, in attempt to revive his two lost cores)


Something else i wanted to talk about , but have to see Yuri's implementation of the PSM thing
It has issues ~ same with your tool although likely is slightly different, hence @1usmus is on an MSI board , where we did have issues with PBO2 Tuner on MSI

Your tool set an SOC voltage limit which was very hard to clear away after being set
By whatever the sideeffects of it where ~ it was how it was
Sadly only personal sample seem to show such signs of "higher than allowed voltage" ~ soo likely this can not be tracked or replicated by others

But hence it did throttle SOC down to 1.2v instead allowing me my maximum range of 1.28xx
















i'm rather worried to use it ~ well also because i saw how annoyingly hard it was, to remove it's traces afterwards
After CMOS reset, after erase and cold boot commands issued. The change still was sticking.

I don't think it will be trackable unless Hydra does a "write once" change. Then maybe i can check again with zenptmonitor
And it's unfortunate timing ~ but i've mentioned once, that your tool and asus tool got recently a bit much attention (from more sides)
Hence my embarrassing misunderstanding and questioning, needs to be excused (3 different ears = different meaning of sentence)

At the very end, i hope it stays open to the community
or at least both dev's help each other. That's all my outside viewpoint can hope for
For anything else, i can't comment than to test his and your tool & see which one is "less broken"


PJVol said:


> (and @Veii too, in attempt to revive his two lost cores)


Or wipe away his firmware preset that allows the 5600X to run 2100 FCLK  it shouldn't have access, but you never know
I know the "defaults" are stuck in firmware ~ as thats the only way i can restore away from such odd enforced changes via SMU or other buggy bios nonsense


----------



## Audioboxer

At least these awful last few AGESA releases are starting to get a bit more press https://www.tomshardware.com/news/agesa-1205-bugs-amd-ryzen

Doubt AMD will care though.


----------



## Veii

Audioboxer said:


> At least these awful last few AGESA releases are starting to get a bit more press https://www.tomshardware.com/news/agesa-1205-bugs-amd-ryzen
> 
> Doubt AMD will care though.





> Thankfully it appears some motherboard manufacturers are acting proactively. According to ComputerBase,
> Asus completely halted official BIOS updates to AGESA 1.2.0.5 and will be skipping it in favor of AGESA 1.2.0.6b.
> 
> However, most motherboard manufacturers, including Biostar, Gigabyte, and MSI, still have official AGESA 1.2.0.5 BIOS updates available on their respective websites.
> If you are an AMD Ryzen owner, we would highly recommend staying away from both AGESA 1.2.0.4 and 1.2.0.5 BIOS updates if at all possible.
> 
> For now, it appears that 1.2.0.3c is the latest stable AGESA code until AGESA 1.2.0.6b patches arrive which should hopefully fix all these problems.


AGESA 1206a/b has the same core functionality like 1205, and downgrading wouldn't even help haha
But they have hopes 


Veii said:


> i'm rather worried to use it ~ well also because i saw how annoyingly hard it was, to remove it's traces afterwards


Hydra's PBO version functions without a bug
Soo SOC bug is PJVol's Tool, method to blame only 








Colorsheme is not mine, but it's everyone's own
I'd expect it to be in the free public version & changes stick on closing ~ but still hope that we have two/3 options out there for this.
Generally (OC) industry moves forward that way


----------



## PJVol

Veii said:


> It has issues ~ same with your tool although likely is slightly different, hence @1usmus is on an MSI board , where we did have issues with PBO2 Tuner on MSI
> 
> Your tool set an SOC voltage limit which was very hard to clear away after being set
> By whatever the sideeffects of it where ~ it was how it was
> Sadly only personal sample seem to show such signs of "higher than allowed voltage" ~ soo likely this can not be tracked or replicated by others
> 
> But hence it did throttle SOC down to 1.2v instead allowing me my maximum range of 1.28xx





Veii said:


> Soo SOC bug is PJVol's Tool, method to blame only


I think you did managed to find the issue where there isn't any.
What you see as "SOC_SET_VOLTAGE" is the value set in BIOS under "SOC/Uncore OC Voltage(VID)" and AFAIK not used in Zen2/Zen3.
As a hint, please take a closer look at the screenshots attached (Auto set value is 1.1V)

And please provide an evidence of the impact this setting has on any of the CPU operating points and the way to reproduce it before *calling it a bug* (W.T.F. ...)


----------



## Veii

PJVol said:


> I think you did managed to find the issue where there isn't any.
> What you see as "SOC_SET_VOLTAGE" is the value set in BIOS under "SOC/Uncore OC Voltage(VID)" and AFAIK not used in Zen2/Zen3.
> As a hint, please take a closer look at the screenshots attached (Auto set value is 1.1V)
> 
> And please provide an evidence of the impact this setting has on any of the CPU operating points and the way to reproduce it before *calling it a bug* (W.T.F. ...)


I did , early posts, this is a summary
It is a change that was not intentional to happen and was not changed to happen
"a bug" ~ in it's correct wording and correct form

UncoreOC is for me disabled everywhere


Spoiler: Bios






























Why do you have to be like this ?


Spoiler: The meaning of "a bug"












Collection of explanation of the englisch language from 5 different lectures, vocabularies and between US and UK



The evidence of impact is irrelevant to the factor of bug appearing
A function that changes something along it's action, which was not supplied and not intentional to do so = a bug
Hydra's "apparently identical implementation" does not have this "feature" supplied with it ~ and hence noted on the "uses MSI board for testing" ~ post , it seems that it's not a 1:1 copy

Then, "when it seems to not be a 1:1 copy" ~ i wished for both devs to work together and fix this "feature that shouldn't exist" ~ in your tool.
There was nothing but a well intention request for you to work together and fix this

Now find me another reason to blame me for:

not understanding English language
not explaining to you how to resolve this "bug", which was not my work to do so // as i've reported the "issue/feature" already to you. Am in no fault that you had to figure it out by yourself
and imagining things that do not exist, when it's clear and infront of me how things behave and do not behave

Please don't be like this,
Don't push me into defensive side with blames that you have no ground on to argue
It's purely irrelevant how much of a % it's an issue that SOC_MAX is X value or Y value ~ fact is that your tool changed it and it was a pain to revert back

You only complain to me that this is no bug and a made up story ~ then trow in something completely irrelevant (performance metrics) to the bug/feature report i've given
On both parts it's incorrect . . .
What a waste of time even supplying information when all developer can do, is defend his product and blame the user ~ but not acknowledge a potential issue 
========================================================
Indepedent if 1usmus used your tool as inspiration or copied something
The copy is not 1:1 , hence the outcome is different
And i've asked nicely if you can work together
^ now dare you find me a blame here that i was maaybe nice, while you peeing p*ssed about somebody else

What is fact tho,
is that the tool does things it is not supposed to do
Or if it is supposed to do, it would be better that it won't do it. // there should be no SOC interaction on CO or power throttle
Yet all on all, the only pure acknowledgement i can read ~ was attacking the user for having bad user experience.
And to top it off, being angry about the user that he didn't share you what the resolve is.
How should i even know that UncoreOC toggle does the change ~ and even then , it's still irrelevant to me, i'm not the dev

But outside all of that missunderstanding and having a bad day
It's to argue with me that i am in fault for your product , and in fault for either "not reporting" in time or "using another nearly identical" option to proof that your tool does something it is not supposed to do
"a bug" ~ yes

"Bugging" your bug hunting userbase, and mocking them ~ is the least a developer should focus on doing
But that's on you . It just shows what a waste of time it was reporting something missbehaving, to be attacked on the way of report. Good Job !

EDIT 2:
Don't think i do not acknowledge the work you've put in figuring this toggle out
But this doesn't change the serving that was delivered now ~ attacking the bughunter and expecting him to play developer and performance checker , aand maybe being trustful to your tool and not testing Hydra
. . . oor something similar to this . I can't imagine why you'd be pissed *at me* here, but written is written ~ soo please do not do this. You have no ground to bug  your testing userbase for own flaws and faults
Just pushes me away from even trying to deal with potential arising issues on your tool, hence i'm treated that way.
Even if we ignored the hassle of things changing that shouldn't change // which i now seem to make up , lol.
// Just waiting for the claim where i photoshop my pictures too "& not only make up stories". Would fit on this absurdness quite well *🤭*


----------



## Melan

I've settled with these settings and spent entire day testing them. No memory/whea errors after tm5 absolut, OCCT and y-cruncher runs.


Spoiler














Today I got greeted by ntoskrnl.exe corruption on cold boot. I reset the timings and frequency to auto, windows started up. I go back to bios, set the timings and frequency back... and windows boots again no problem?? Ntoskrnl corruption screen didn't pop up after several restarts, so I decided to run tm5 1usmus_v3 for 20 runs which produced no errors and later did 6 iterations (BKT, FFT, N32, N64, VST, C17) in y-cruncher which also had no problems.
I've marked the settings which were left on auto. Could any of these cause such issue on cold boot?


----------



## Luggage

Melan said:


> I've settled with these settings and spend entire day testing them. No memory/whea errors after tm5 absolut, OCCT and y-cruncher runs.
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2549427
> 
> 
> 
> Today I got greeted by ntoskrnl.exe corruption on cold boot. I reset the timings and frequency to auto, windows started up. I go back to bios, set the timings and frequency back... and windows boots again no problem?? Ntoskrnl corruption screen didn't pop up after several restarts, so I decided to run tm5 1usmus_v3 for 20 runs which produced no errors and later did 6 iterations (BKT, FFT, N32, N64, VST, C17) in y-cruncher which also had no problems.
> I've marked the settings which were left on auto. Could any of these cause such issue on cold boot?


Yes - if they are stable now, lock them all in.


----------



## KedarWolf

Disabled Virtualization, Windows 11.


----------



## Melan

Luggage said:


> Yes - if they are stable now, lock them all in.


Went back to bios to do just that, 1st reboot worked, 2nd reboot gave corruption error again. :\
I guess I'll try 2T.


----------



## 99belle99

Anything I can change here. I may have a setting or two or three wrong. It's stable which is the main thing.


----------



## PJVol

Let's put it straight.


Veii said:


> I did , early posts, this is a summary


It's not clear from your early posts what the exact sequence of steps exposed the "bug".


Veii said:


> The evidence of impact is irrelevant to the factor of bug appearing
> A function that changes something along it's action, which was not supplied and not intentional to do so = a bug


So this conclusion was made based on:
1) something is changing somewhere inside CPU, that we have no idea of what it means, i.e. is it normal or not, and you don't like it.
2) there's no evidence of negative impact of the above menitioned change on the CPU in any way
3) there's no way to reproduce this "bug" outside of the scope of your CPU sample.

Nice... no further questions.


----------



## T884G63

@KedarWolf @Audioboxer

Once you go OLED you never go back currently running a LG CX

But this has me drooling as 48" is a tad too big and the specs are better...

Not Crazy Expensive: Alienware's 34-Inch Quantum Dot OLED Monitor Gets $1,299 Price


----------



## kim nk

Audioboxer said:


> Yeah the IPS lottery is why I ultimately ended up with a VA 34" UW. It has basically no light bleed and _amazing_ contrast. Viewing angles worse and maybe not colours that pop as much as IPS but I'm super sensitive to light bleed/glow and prioritised not worrying about it over the colour accuracy of IPS. I don't play super twitchy FPS games and I honestly don't notice smearing/blur with VA. 144hz panel.
> 
> My name drop of that monitor and the LG was really more a case of "If you want a 38" UW, these are really your only two decent options".
> 
> Probably going to stick to this monitor until the monitor industry really has a change from the long fought battle of IPS vs VA. We really need to crack the OLED for screens this size, whatever the name of the tech ends up being (I know there are some monitors coming through now). Then wait patiently for reasonable consumer prices lol.
> 
> Actual HDR monitors are a rip off and a few of them need damn fans to cool them, if not all of them. Out of everything in the PC industry that truly needs an overhaul, it's monitors. Nearly all other components have had big steps forward in the past 5 years+. Monitors still lingering with older tech "patched up" to try and push refresh rate and for what you get tech wise, very overpriced (at the top end).
> 
> 
> 
> IIRC my kit was showing promise for 4000 14-14-14-14 but I didn't spend too long on it because I can't get FCLK 2000 properly stable.
> 
> I guess I could run it out of sync and play with it at 4000, seeing as I've already done that for 4533.
> 
> 4400 15-15-15-15 works as well which is decent. 4533 needs 16-16-16-16.


In the 1:1 case, the situation is different. At 4300 clocks, trcdrd 15 was impossible. 1t to 16 must pass tm5, but 1t to tphyrdl 28. The memory kit I'm using now is a memory kit in which 14-14-14 at 4000 clocks pass through tm5 at the clkdrvstr24 level.


----------



## 99belle99

@kim nk You have some good RAM and great IF with that 5600X.


----------



## Bloax

I wonder what CPU Revision that is - 2150 FCLK without WHEA reports and no L3 latency penalty, unusually good. :- )


----------



## KedarWolf

kim nk said:


> In the 1:1 case, the situation is different. At 4300 clocks, trcdrd 15 was impossible. 1t to 16 must pass tm5, but 1t to tphyrdl 28. The memory kit I'm using now is a memory kit in which 14-14-14 at 4000 clocks pass through tm5 at the clkdrvstr24 level.
> View attachment 2549457
> 
> View attachment 2549456
> 
> 
> 
> View attachment 2549455
> 
> View attachment 2549454


VSOC at 1.325v, big nope for me.


----------



## kim nk

Bloax said:


> I wonder what CPU Revision that is - 2150 FCLK without WHEA reports and no L3 latency penalty, unusually good. :- )


2136SUS 
BCLK 100.75 ~100.8125


----------



## kim nk

KedarWolf said:


> VSOC at 1.325v, big nope for me.


4200 CL14 -8-15-12-21-40 TRFC 240-178-110 REAL 1T SOC 1.2813V
4301 CL 14-12-16-14-26-40 TRFC 240-178-110 REAL 2T SOC 1.3250V 
The SOC had to be increased to that extent for CL14 timing.


----------



## ManniX-ITA

PJVol said:


> It's not clear from your early posts what the exact sequence of steps exposed the "bug".





PJVol said:


> What you see as "SOC_SET_VOLTAGE" is the value set in BIOS under "SOC/Uncore OC Voltage(VID)" and AFAIK not used in Zen2/Zen3.


Smells really like the 1.55V CTR bug...

I'll check out your code but I'll bet 2 cents you don't have a sleep between issuing a command and the next 
This is the sort of stuff that happens without.
If for @Veii is the SOC, for someone else could be the vCore, VDDG or else.

If you put a 50ms interval in between every commands you can be pretty sure this doesn't happen.
For some "heavy commands" (they take time to complete), like changing CPU/CCD clock frequency, you need more time before you re-issue the same or another "heavy" one.
I went for 200ms and never had an issue since then.
Guess the command to change CO is one of those.

SET SOC Voltage is used on Zen2/Zen3, behavior depends on the board manufacturer:

0B0 on MSI is the SET BIOS Voltage:




























This depends on the mode if it's Override or AMD Overclocking, in MSI's case.

@Veii is helping me testing a new creation  and indeed his SOC voltage was set that high (!!!!):










Ah and it told me it was my fault  

Please don't dramatize or underscore guys, we "know" each other since long time now 



PJVol said:


> As for how I set CO, I prefer the method by PJVol, that he posted more than half a year in a local russian forum (pretty long post with spoilers), though i'd have make some adjustments to it by now.
> TL;DR based on psm readings in some workload (I used CBR23) I calculate approximate (draft) curve, then using the minimum stable counts for the two best cores, found beforehand, I adjust other counts so as their psm voltages preferably not to exceed much those of the best two in the same type of workload. Thats it.


I tried it on my 5950X and it was no good for me 
@Veii spent quite some time with me calculating the CO counts (thanks man 🙏 ).
The result was awful, worse performances both in ST & MT, big time.

I guess it works till you don't have any big delta between Core VIDs.
Which is more easy with 6 cores, less with 16.

I have 2 of my best cores very different from each other.
One can do 5150 MHz with over 1.4V the other needs just a bit more than 1.3V.
Balancing the between them would have mean loosing 150 MHz on one or 75 MHz on both...
The average ones on 2nd CCD they need low voltages, they run super slow with higher voltages.
The bad ones they need very high voltages or they crash.
I'm not sure how is possible to balance them, they are all very different...

But it's a very interesting strategy that clearly works if there are the right prerequisites.
I want to do something "automated" to optimize and test CO counts (related to my new thing above) and I'd like to have this strategy in if you can help.



PJVol said:


> Basically I came to conclusion, that with this scenario (each core stressed with affinity set) the stability of each core individually not nesessarily mean СPU stability as a whole, i.e. in multicore loads or partially multicore, where some cores may be put into C1/C6. The reverse is pretty much true either. (Perhaps I could have provide some experimental data to back it up later on).
> I'd say i am confident enough atm, but don't mind convincingly proving me wrong.





PJVol said:


> To date, I'm almost 100% sure that running some scripts or tools that set affinity for one core or cycling through all cores under quite heavy load (FP/SIMD), makes _little to no sense _for setting up CO, let alone wasted time itself.


I'm not sure about this...
I can tell from my experience that it helps.

I've run unstable Cores (as found by CoreCycler) to see if you can just go away with errors on not good cores.
Doesn't work 
From Visual Studio hanging, games crashing, sudden black screen reboots, etc seems that testing per Core this way works.
If the CO counts are stable with CoreCycler, zero issues.

I agree that single core testing is not enough if not paired with a lot of y-cruncher stress test cycles.
But this doesn't means that makes no sense or it's wasted time.
What do you have in mind to test for CO counts stability?


----------



## ManniX-ITA

@1usmus  @PJVol


----------



## ManniX-ITA

@PJVol

Yes, you need to put a lot of sleep timers 



Code:


foreach (KeyValuePair<string, SettingsForm.PBO_setting> ps in this.pbo_settings)
        {
            uint[] args = new uint[6];
            uint cmd = ps.Value.cmd;
            bool flag = ps.Value.isChanged == 0;
            if (!flag)
            {
                ps.Value.isChanged = 0;
                uint arg;
                this.TryConvertToUint(ps.Value.CurrentValue, out arg);
                args[0] = ((ps.Key == "EDC" || ps.Key == "TDC" || ps.Key == "PPT") ? (arg * 1000U) : ((ps.Key == "FIT") ? (arg * 100U) : arg));
                Mailbox mbox = (ps.Key == "Boost") ? this.cpu.smu.Hsmp : this.cpu.smu.Rsmu;
                status = this.cpu.SendSmuCommand(mbox, cmd, ref args);
                this.ConsoleLog("Setting " + ps.Value.Tag + " to " + ps.Value.CurrentValue);
            }
        }

Like in this foreach, set a sleep timer after the SendSmuCommand for at least 50 ms. I'd go for 200ms just to be sure.

Set always a sleep timer after any command or powertable refresh to avoid being too quick when you call two functions one after each other:



Code:


        this.PBO_Limits_Apply();
        this.GetCurrentLimits();

Even if the powertable can be refreshed quickly, wait at least 50ms after any command:



Code:


       SMU.Status status = this.cpu.SendSmuCommand(this.cpu.smu.Hsmp, cmd, ref args);
        this.MaxBoost_freqCurrent.Text = Convert.ToString(args[0]);
        status = this.cpu.RefreshPowerTable();

Also check with @infraredbg if the Zenstates core DLL you are using has the waiting on the PCI Mutex implemented.
Otherwise you need to implement it yourself (it's very easy).

Without this any user's "too fast clicking" on Apply or concurrency with Libre/CTR/Hydra/HWInfo/etc can cause these issues and more.

EDIT:
I forgot, concurrency with Ryzen Master or the RM Monitoring SDK.
Which is unbelievably the worst implementation ever in dealing with SMU... and it's from AMD.
Whatever you run with RM running can cause severe issues (except HWInfo, AMD must have shared some "secret sauce" with Martin on how to avoid concurrency issues).
Just how big companies are always evangelizing good practices but never doing it on their own...


----------



## Taraquin

kim nk said:


> In the 1:1 case, the situation is different. At 4300 clocks, trcdrd 15 was impossible. 1t to 16 must pass tm5, but 1t to tphyrdl 28. The memory kit I'm using now is a memory kit in which 14-14-14 at 4000 clocks pass through tm5 at the clkdrvstr24 level.
> View attachment 2549457
> 
> View attachment 2549456
> 
> 
> 
> View attachment 2549455
> 
> View attachment 2549454


Awesome! Did you increase VDD18 voltage going beyond 1900?


----------



## kim nk

Taraquin said:


> Awesome! Did you increase VDD18 voltage going beyond 1900?


cpu with no wHEA errors. This sample is pll1.8 voltage -auto and vdd18-Auto .
No need to manually raise it, that's fine.


----------



## PJVol

I'll look into it, but before let me ask you the same two questions:


ManniX-ITA said:


> Smells really like the 1.55V CTR bug...





ManniX-ITA said:


> If for @Veii is the SOC, for someone else could be the vCore, VDDG or else.


1) are you saying that you (or anyone else) can reproduce this issue?



ManniX-ITA said:


> SET SOC Voltage is used on Zen2/Zen3, behavior depends on the board manufacturer:


2) How exactly? Or what is the evidence of it's been used?

Thanks.


----------



## ManniX-ITA

PJVol said:


> 1) are you saying that you (or anyone else) can reproduce this issue?


I'm saying I saw weird stuff happening to vCore, SOC and VDDG voltages while developing OCMaestro.
That till I've implemented sleep times between commands.
At the time I didn't know about the PCI mutex or the bug in Libre library but still didn't have any issue.
Tomorrow someone could find out its vCore or VDDG is running at a very high voltage.
Or just reproduce the vSOC issue like Veii, it's random.



PJVol said:


> 2) How exactly? Or what is the evidence of it's been used?


The screenshots above are not enough?
Am I missing something?


----------



## PJVol

ManniX-ITA said:


> I'm saying I saw weird stuff happening to vCore, SOC and VDDG voltages while developing OCMaestro.


Did you implemented something like this in your code:


C++:


    /* Clear the response */
    smn_reg_write(smu->nb, smu->rep, 0x0);
    /* Pass arguments */
    smn_reg_write(smu->nb, C2PMSG_ARGx_ADDR(smu->arg_base, 0), args->arg0);
    ...
    smn_reg_write(smu->nb, C2PMSG_ARGx_ADDR(smu->arg_base, 5), args->arg5);
    /* Send message ID */
    smn_reg_write(smu->nb, smu->msg, id);
    /* Wait until reponse changed */
    while(response == 0x0) {
        response = smn_reg_read(smu->nb, smu->rep);
    }
    /* Read back arguments */
    args->arg0 = smn_reg_read(smu->nb, C2PMSG_ARGx_ADDR(smu->arg_base, 0));
    ...
    args->arg5 = smn_reg_read(smu->nb, C2PMSG_ARGx_ADDR(smu->arg_base, 5));

Regarding the "bug", so far this doesn't sound very convincing, to say the least.


ManniX-ITA said:


> The screenshots above are not enough?


Actually yes, they aren't.


ManniX-ITA said:


> Am I missing something?


If you ever had to deal with the big projects, the fact that when some metric is changed doesn't mean it is actually used shouldn't be a surprise for you.


----------



## Taraquin

kim nk said:


> cpu with no wHEA errors. This sample is pll1.8 voltage -auto and vdd18-Auto .
> No need to manually raise it, that's fine.


I don't get WHEA19 above 1900 fclk either, but I need to raise VDD18 voltage to avoid perf regression in linpack, CB and y-cruncher.


----------



## ManniX-ITA

PJVol said:


> Actually yes, they aren't.


What do you need more?
Please be specific 

You said SOC_SET_VOLTAGE is not used right?



PJVol said:


> What you see as "SOC_SET_VOLTAGE" is the value set in BIOS under "SOC/Uncore OC Voltage(VID)" and AFAIK not used in Zen2/Zen3.
> As a hint, please take a closer look at the screenshots attached (Auto set value is 1.1V)


Maybe I misunderstood?










These are my 00B0/00B4:










Which means SOC_SET_VOLTAGE it is used.

It's the SET voltage I have in BIOS:









While the telemetry voltage at 0B4 is the SVI2:










What it's not clear to me is how this is related to the issue 

@Veii said that you did set the SOC voltage with the App but of course it's not that.
I don't think you set it anywhere and you wouldn't set 1.45V on purpose 

The very high voltage it's a byproduct of accessing the SMU in the "wrong" way, so to say.
It's just the SMU doing funny stuff and messing up the CPU.
I had it once my 3800X completely dead for 15 minutes.
(Also Veii should have mentioned that he was testing Hydra while using your App)



PJVol said:


> If you ever had to deal with the big projects, the fact that when some metric is changed doesn't mean it is actually used shouldn't be a surprise for you.


Every day but I'm not sure I understand


----------



## Luggage

Taraquin said:


> It's smart to fully tune ram before messing with CO. On some setups CO is the same no matter how you tune ram, on others it's vety sensitive to ram oc/tuning.


Yep - that new memory setting 



http://imgur.com/zQgf7mI


compared to older



http://imgur.com/NLCGgUx


New one: tm5 v3 25 cycles, extreme 9 cycles ok - y-cruncher -> crash or error, weha 18 on three different cores, two reboots. suspect vsoc or vdim. Don't really think it's the co values. perhaps procodt that I stole from your settings?


----------



## kim nk

Taraquin said:


> I don't get WHEA19 above 1900 fclk either, but I need to raise VDD18 voltage to avoid perf regression in linpack, CB and y-cruncher.


Is it okay if I upload more than about 1900?


----------



## Audioboxer

kim nk said:


> In the 1:1 case, the situation is different. At 4300 clocks, trcdrd 15 was impossible. 1t to 16 must pass tm5, but 1t to tphyrdl 28. The memory kit I'm using now is a memory kit in which 14-14-14 at 4000 clocks pass through tm5 at the clkdrvstr24 level.
> View attachment 2549457
> 
> View attachment 2549456
> 
> 
> 
> View attachment 2549455
> 
> View attachment 2549454


tRCDRD 15 at 4400 wasn't actually a problem for me










Then again I was doing this out of sync.


----------



## PJVol

ManniX-ITA said:


> Which means SOC_SET_VOLTAGE it is used.


Ok, i'm not sure you understand what I mean under "used" term, sorry 
Let's put it straight then, is this value "USED" in your opinion?


----------



## ManniX-ITA

PJVol said:


> Let's put it straight then, is this value "USED" in your opinion?


I don't know what it is... how should I know if it's used somewhere? 

Veii complained about the SOC voltage limit and you told him it's not being used.
I'm just telling that it is used.
Not sure if/how was being a limiting factor but I guess Veii had his reasons to tell, not a newbie.

Aside the specific SOC voltage issue (he also had it reported at 1.45V but maybe it was just the reading messed up in that case), the problem is how the App is accessing the SMU.
This kind of funny stuff will probably pop up more and more without using the PCI mutex and the sleep between calls.
Also for CTR it went unnoticed for quite a while and it had a very decent user base.


----------



## PJVol

ManniX-ITA said:


> I don't know what it is... how should I know if it's used somewhere?


If I tell you it's fused Core 1 temperature reading, does this change anything?

Look, if I set the Soc voltage in BIOS I *know *that it is actually used (shown as SOC_TELEMETRY_VOLTAGE, i.e. SVI2), because i can see how it changes the CPU behavior, as opposed to setting the Soc/Uncore OC Voltage VID that changes the SET_SOC_VOLTAGE metric in power table and actually do nothing, i.e. doesn't affect CPU behavior in any way.



ManniX-ITA said:


> Veii complained about the SOC voltage limit and you told him it's not being used.
> I'm just telling that it is used.


Neither you, nor Veii showed any evidence of it's been *actually *used (is it that hard or there actually aren't any?). And furthermore, he didn't even provide the steps were made which exposed the "bug". I can only assume, taking your considerations into account, it might be the "Reset" function, which causes the sequence of 6 smu_write commands in a row, but it's just my wild guess so far.

Anyway, without being able to reproduce the bug, and even being told the exact sequence of actions that has lead to it, it's hard to fix smth.


----------



## ManniX-ITA

PJVol said:


> setting the Soc/Uncore OC Voltage VID that changes the SET_SOC_VOLTAGE metric in power table and actually do nothing, i.e. doesn't affect CPU behavior in any way.


But this may be true for your specific board/setup, not in general.
On my Unify-X it does have an effect, it's the set voltage in BIOS.
Quite a big one


----------



## PJVol

ManniX-ITA said:


> But this may be true for your specific board/setup, not in general.


Fair point.



ManniX-ITA said:


> On my Unify-X it does have an effect, it's the set voltage in BIOS.


You mean what you set in BIOS as the Soc voltage is the one shown as SET_SOC_VOLTAGE in pt?
Or in other words, is there a setting in your BIOS that appear as SOC_TELEMETRY_VOLTAGE in a power table?

This is all I've got in a mb sensors group.
SOC/Uncore OC VID set to Auto and 1.222 respectively:


----------



## kim nk

Audioboxer said:


> tRCDRD 15 at 4400 wasn't actually a problem for me
> 
> View attachment 2549491
> 
> 
> Then again I was doing this out of sync.


Hmm.. I think I'll have to loosen the cl from 14 to 15 once and loosen the timing a bit. And I think I'll have to do trcdrd15. cl14 was actually difficult. I'll check to see if this interfered with trcdrd 15, or missed 2t because I was focused on 1t, or if it interfered with trcdrd 15 because of cl14. Thank you


----------



## ManniX-ITA

PJVol said:


> You mean what you set in BIOS as the Soc voltage is the one shown as SET_SOC_VOLTAGE in pt?


Yes indeed:











What I set in BIOS is is reflectd in SET_SOC_VOLTAGE.
This is with MSI Override option and I think it was the same with Gigabyte.

Zentimings:














PJVol said:


> Or in other words, is there a setting in your BIOS that appear as SOC_TELEMETRY_VOLTAGE in a power table?


No, what I get on SOC_TELEMETRY_VOLTAGE is what is reported at GET SOC voltage, the SVI2 TFN










While the actual board SET SOC Voltage reported by HWInfo is higher.
Always like this when Override mode is selected instead of AMD Overclocking, it's an MSI specific thingy:


----------



## PJVol

ManniX-ITA said:


> While the actual board SET SOC Voltage reported by HWInfo is higher.
> Always like this when Override mode is selected instead of AMD Overclocking, it's an MSI specific thingy:


Well, that makes things even more confused 
(You now know what I meant when saying that IMO most of the time it's an AMD <-> vendors communication issues that people tend to blame amd for)
Actually the way how it is reported on your board seem to me more logical. At least SET voltage (in pt) do correspond to the actual value set by user, as oppesed to that bull**** reported in my case )
This leads me to believe that my recent assumptions are not far from truth about the difference in a way Asrock and other vendors access SMU at boot time (i mean using or not APML)

Anyway, at least on my board (not sure about Veii's though) it's not used. Just tested Auto and 1.290V and Soc power consumption were the same in both cases.
What's left is to find out, if this change potentially (or rather actually) may happen on your board and how to reproduce it ))


----------



## ManniX-ITA

PJVol said:


> (You now know what I meant when saying that IMO most of the time it's an AMD <-> vendors communication issues that people tend to blame amd for)


I agree, maybe not most of the time but probably it's a fifty-fifty share 
But I blame AMD for not being able to establish a proper vendor relationship with board manufacturers.
Intel, while still trying to be the sole owner of the x86 platform, made a much better job in a shorter time.


----------



## Luggage

MSI does some shady **** sometime, bclk (not so much these days?) scalar, overvolting.
Asus does some brilliant or very shady ****, fmax enhancer, dynamic OC switcher.
Gigabyte likes VRM but - f*cks up?

And then I see you wonderful people.... all on Asrock getting very strange behaviors


----------



## ManniX-ITA

Luggage said:


> MSI does some shady **** sometime, bclk (not so much these days?) scalar, overvolting.
> Asus does some brilliant or very shady ****, fmax enhancer, dynamic OC switcher.
> Gigabyte likes VRM but - f*cks up?
> 
> And then I see you wonderful people.... all on Asrock getting very strange behaviors


It's like Sauron finally got his ring to rule them all and brought them over the dark side


----------



## PJVol

ManniX-ITA said:


> Also check with @infraredbg if the Zenstates core DLL you are using has the waiting on the PCI Mutex implemented.


You mean this part? If so then yes, it's implemented.


Spoiler: from ZenStates-core Ring0.cs






C#:


            if (Ring0.WaitPciBusMutex(10))
            {
                ushort timeout = SMU_TIMEOUT;
                uint[] cmdArgs = MakeCmdArgs(args);

                // Clear response register
                bool temp;
                do
                    temp = SmuWriteReg(mailbox.SMU_ADDR_RSP, 0);
                while ((!temp) && --timeout > 0);

                if (timeout == 0)
                {
                    SmuReadReg(mailbox.SMU_ADDR_RSP, ref status);
                    Ring0.ReleasePciBusMutex();
                    return (SMU.Status)status;
                }

                // Write data
                for (int i = 0; i < cmdArgs.Length; ++i)
                    SmuWriteReg(mailbox.SMU_ADDR_ARG + (uint)(i * 4), cmdArgs[i]);

                // Send message
                SmuWriteReg(mailbox.SMU_ADDR_MSG, msg);

                // Wait done
                if (!SmuWaitDone(mailbox))
                {
                    SmuReadReg(mailbox.SMU_ADDR_RSP, ref status);
                    Ring0.ReleasePciBusMutex();
                    return (SMU.Status)status;
                }

                // Read back args
                for (int i = 0; i < args.Length; ++i)
                    SmuReadReg(mailbox.SMU_ADDR_ARG + (uint)(i * 4), ref args[i]);

                SmuReadReg(mailbox.SMU_ADDR_RSP, ref status);
                Ring0.ReleasePciBusMutex();
            }


----------



## ManniX-ITA

PJVol said:


> You mean this part? If so then yes, it's implemented.


Yes this one!
I had little doubt but I didn't check myself..


----------



## PJVol

ManniX-ITA said:


> Yes this one!


I thought every programmer here and his dog knows about this specifics since, well, about a couple of years? 
What is not completely clear to me is this comment from the ryzen_smu source by Leonardo Gates


C++:


// Both mutexes are defined separately because the SMN address space can be used
//  independently from the SMU but the SMU requires access to the SMN to execute commands.
static DEFINE_MUTEX(amd_pci_mutex);
static DEFINE_MUTEX(amd_smu_mutex);

So he lock the 2nd mutex in SMU cmd then lock/unlock pci one at every read/write to SMN. Not sure if it's implemented in Openlibsys


----------



## Taraquin

kim nk said:


> Is it okay if I upload more than about 1900?


I don't understand what you mean?  Many get WHEA19 above 3800 ram/1900 fclk, some like you and me don't, but performance might not scale.


----------



## Taraquin

Luggage said:


> Yep - that new memory setting
> 
> 
> 
> http://imgur.com/zQgf7mI
> 
> 
> compared to older
> 
> 
> 
> http://imgur.com/NLCGgUx
> 
> 
> New one: tm5 v3 25 cycles, extreme 9 cycles ok - y-cruncher -> crash or error, weha 18 on three different cores, two reboots. suspect vsoc or vdim. Don't really think it's the co values. perhaps procodt that I stole from your settings?


I use 28 ProcODT, you mean Rtts? You may need other Rtts than me. Try experimrnting with higher CCD and IOD


----------



## kim nk

Audioboxer said:


> tRCDRD 15 at 4400 wasn't actually a problem for me
> 
> View attachment 2549491
> 
> 
> Then again I was doing this out of sync.


Once again, flck ulck these numbers are 2:1 to trcdrd 15. If this number is 1:1 properly, trcdrd 15 is different and impossible. For example, this is easy for me..








When both flck ulck are 2200, they are completely different.

Going back to the 4300 1:1 clock, mclk, fclk, and uclk all 2150 real 1t or 2t trcdrd 15 is impossible


----------



## ManniX-ITA

PJVol said:


> I though every programmer here and his dog knows about this specifics since, well, about a couple of years?


Well apparently not in AMD 
RM is not locking the PCI Mutex.

Honestly I don't even know if it's really the right thing to do.
Locking of the whole PCI bus shouldn't be needed in my understanding.
Unless there's a very good reason (like a real time transfer which needs the whole bus).

I guess it's only the most convenient workaround to avoid concurrency.
Either AMD didn't implement anything or doesn't want to publicly disclose it.
I tend for the latter, they are weird.



PJVol said:


> So he lock the 2nd mutex in SMU cmd then lock/unlock pci one at every read/write to SMN. Not sure if it's implemented in Openlibsys


My understanding is that they are using 4 different mutex:



Code:


enum SMU_MUTEX_LOCK {
    SMU_MUTEX_SMN,
    SMU_MUTEX_CMD,
    SMU_MUTEX_PM,
    SMU_MUTEX_COUNT
};

Which should allow concurrent usage while the main PCI mutex is locked.


----------



## Audioboxer

kim nk said:


> Once again, flck ulck these numbers are 2:1 to trcdrd 15. If this number is 1:1 properly, trcdrd 15 is different and impossible. For example, this is easy for me..
> View attachment 2549512
> 
> When both flck ulck are 2200, they are completely different.
> 
> Going back to the 4300 1:1 clock, mclk, fclk, and uclk all 2150 real 1t or 2t trcdrd 15 is impossible


Sadly I can't test my FCLK that high, I've struggled to even get 2000 stable. Good to see you have proven something though, running tRCDRD 15 out of sync is easier for the CPU/IMC.


----------



## kim nk

Audioboxer said:


> Sadly I can't test my FCLK that high, I've struggled to even get 2000 stable. Good to see you have proven something though, running tRCDRD 15 out of sync is easier for the CPU/IMC.


Yes, I realized once again that the input value of soc trcdrd in the 1:1 state and the value in the 2:1 state are completely different flows. I'm going to challenge the 4400 2t once with 15-16-15 timings caught with 1:1 fclk tphyrdl 26. Have a nice day~


----------



## Luggage

Taraquin said:


> I use 28 ProcODT, you mean Rtts? You may need other Rtts than me. Try experimrnting with higher CCD and IOD


After some more testing I think it's actually yc being much better at crashing cores.


Frosted racquet said:


> I don't know if we saw the same post with the suggestion, but it's:
> mode = 19-ZN2 ~ Kagari (under the section # y-Cruncher specific settings)
> The user suggested numberOfThreads = 2 as well but I haven't verified if it's actually beneficial to run SMT, as it may reduce effective clocks. Compare and see.


This made me change co 5-6 values on cores that survived all night with the 720 and 16k-27k tests from 


ManniX-ITA said:


> Also 28 iterations of what?
> 
> SSE Large?
> 
> It's a lot of wasted time probably.
> 
> You need to test all FFT sizes, at least with SSE.
> Better with AVX and AVX2 too if you have the time.
> 
> If you spend a bit of time messing with the ini it'll save a lot of testing time...
> 
> Do a quick run with:
> 
> runtimePerCore = 6m
> FFTSize = 720-720
> 
> 3-4 cycles and you have a first quick check, very unstable cores will fail in 1-2 minutes.
> 
> Then a more through check with higher max frequency:
> 
> runtimePerCore = auto
> FFTSize = 16000-27000
> 
> This will take about 5 minutes per Core.
> Between 5-10 cycles and you have almost all unstable Core already in the net.
> 
> After you passed it you need to go over all FFTs, this is a nighttime test.
> 
> runtimePerCore = auto
> FFTSize = All
> 
> Now you can be pretty confident all cores stable.
> But not 100% sure.
> 
> If you want to be sure do it again changing to:
> 
> mode = AVX
> 
> And then with:
> 
> mode = AVX2



Admittedly didn't run all ffts but the yc test found errors on the first cycle on cores i haven't touched in weeks


----------



## ManniX-ITA

Luggage said:


> Admittedly didn't run all ffts but the yc test found errors on the first cycle on cores i haven't touched in weeks


I will check as well when I have time, it's very very interesting if it's faster than P95!
Maybe matched with the 00-x86 which is getting very high max clocks (it's the only one I have tested with y-c & cc).
But I'm a bit scared will find some other core to bring down LoL


----------



## CyrIng

PJVol said:


> I thought every programmer here and his dog knows about this specifics since, well, about a couple of years?
> What is not completely clear to me is this comment from the ryzen_smu source by Leonardo Gates
> 
> 
> C++:
> 
> 
> // Both mutexes are defined separately because the SMN address space can be used
> //  independently from the SMU but the SMU requires access to the SMN to execute commands.
> static DEFINE_MUTEX(amd_pci_mutex);
> static DEFINE_MUTEX(amd_smu_mutex);
> 
> So he lock the 2nd mutex in SMU cmd then lock/unlock pci one at every read/write to SMN. Not sure if it's implemented in Openlibsys


Reasons I'm rewriting the whole SMU stuff in assembly:
PCI_AMD_SMN_Read is *attempting* first to lock an atomic address before giving up. Mutex is a nightmare and can lead can the Kernel into deadlock.
The drawback is that k10temp and CoreFreq must not run simultaneously.


----------



## PJVol

@ManniX-ITA 
Wait, I don't get, all these "public/private" things in github doesn't work? 
My source is actually visible for everyone?


----------



## ManniX-ITA

PJVol said:


> My source is actually visible for everyone?


It's not Github, it's the CLR. Welcome to C# 
Unless you pay for a good obfuscator the code is in plain text from the executable.
You just need dnSpy:









GitHub - dnSpy/dnSpy: .NET debugger and assembly editor


.NET debugger and assembly editor. Contribute to dnSpy/dnSpy development by creating an account on GitHub.




github.com


----------



## ManniX-ITA

@PJVol
BTW Did you find a way to read the CO values set in the BIOS?



CyrIng said:


> PCI_AMD_SMN_Read is *attempting* first to lock an atomic address before giving up. Mutex is a nightmare and can lead can the Kernel into deadlock.


Sorry probably is a dumb question for you, but I'm curious 
Is it really a common practice to lock the PCI bus with a mutex or it's just a workaround for AMD's SMU?


----------



## MrHoof

ManniX-ITA said:


> I will check as well when I have time, it's very very interesting if it's faster than P95!
> Maybe matched with the 00-x86 which is getting very high max clocks (it's the only one I have tested with y-c & cc).
> But I'm a bit scared will find some other core to bring down LoL


Same for my core 7 it wont crash at -16 singlecore loaded but if I run all core y-crunsher there it needs -14 else i will get a hard shutdown with whea18. 
And is even with the cpu heavy task disabled and only the mixed ones used. CPU heavy task in y crunsher lead to scary temps 85-90°C.


----------



## ManniX-ITA

MrHoof said:


> Same for my core 7 it wont crash at -16 singlecore loaded but if I run all core y-crunsher there it needs -14 else i will get a hard shutdown with whea18.
> And is even with the cpu heavy task disabled and only the mixed ones used. CPU heavy task in y crunsher lead to scary temps 85-90°C.


But I think Luggage tested with single core load not all core.
y-c all core is a must whatever test with single core you have ran already!


----------



## MrHoof

Ye never ran y-crunsher with core cycler yet, will take a look at it for sure. Just was pointing out even all core y-crunsher can be pretty effective if it manages to produce a WHEA 18 wich tells wich core crashed. Had also situations with hard shutdowns without a WHEA logged then corecycler was needed to figure out wich.

edit: used the occt one in the past but now swtiched to the powershell script just not long ago.


----------



## Silvio1

Hello, not long ago I have bought myself Ballistix 2x8 3600 CL16 (few weeks ago from amazon.de, 55€), Micron Rev E, I'm running R5 5600X(4.5ghz at 1.25v) with B550M Pro4f. Since I'm like almost only gaming (1080p, in some games even running as low as 1440x1080) I would like my timings tightest as possible. Currently I'm running 3600 CL14-14-17-14-52-30-1T at 1.48v memory and 1.1v soc ofc with FCLK at 1800, I didnt do bunch of testing but didnt get single error in 2021 anta777 testmem (tho it didnt finish since dont have time), I probably still have some space to go down to maybe 1.45v at memory and 1.07v at soc. Also, did not find alot of help on reddit/forums so would like to see if its possible to tighten something else. I guess I still have space to throw tRAS down to like ~21 and possible something else, do not know what tho. Aida64 latency is at 58.3ns. Thanks in advance


----------



## Luggage

ManniX-ITA said:


> But I think Luggage tested with single core load not all core.
> y-c all core is a must whatever test with single core you have ran already!


Yes, because what you said about yc ac and voltages I wanted to avoid messing with vsoc etc as well.
I’ve never had yo crash on the hot’n’heavy tests BBP etc (because they throttle down?) while tuning co so I figured I’d try with corecycler first. And since it’s cooler than ac might find more instability even…


----------



## PJVol

Luggage said:


> And then I see you wonderful people.... all on Asrock getting very strange behaviors


You might be surprised, but so far it's quite the opposite, and with zen2/zen3 particulary, when the majority of guinea pig whining comes from asus and msi bios beta testers, which mostly are the top board owners


----------



## Luggage

PJVol said:


> You might be surprised, but so far it's quite the opposite, and with zen2/zen3 particulary, when the majority of guinea pig noise is from asus and msi bios beta testers, which mostly are the top board owners


It’s just an impression 




Bloax said:


> I don't misuse the terms or talk about CPB - I am merely describing what I witnessed with my own eyes on an Asscock board.
> 
> It is entirely possible that what "disabling CPPC + CPPC Preferred Cores" on said Asrock board did, actually changed much more than just those settings.
> Recreating it is a matter of throwing **** at the wall, and seeing whether it sticks. That is all that disabling CPB is - I have no clue if that would do it, testing it would be a massive pain (in my situation).
> 
> All I can tell you is that it broke boosting (CPU sits at base frequency), and had a noticeable impact on everyone's favorite Le Meme Mouse Input Responsiveness(tm) metric - just as disabling SMT does.
> 
> As I am just as bewildered as you that disabling something _so seemingly innocuous_ would result in such drastic improvements.





PJVol said:


> Well, that makes things even more confused
> (You now know what I meant when saying that IMO most of the time it's an AMD <-> vendors communication issues that people tend to blame amd for)
> Actually the way how it is reported on your board seem to me more logical. At least SET voltage (in pt) do correspond to the actual value set by user, as oppesed to that bull**** reported in my case )
> This leads me to believe that my recent assumptions are not far from truth about the difference in a way Asrock and other vendors access SMU at boot time (i mean using or not APML)
> 
> Anyway, at least on my board (not sure about Veii's though) it's not used. Just tested Auto and 1.290V and Soc power consumption were the same in both cases.
> What's left is to find out, if this change potentially (or rather actually) may happen on your board and how to reproduce it ))


edit: and enforcing PBO limits set in bios etc…


----------



## ManniX-ITA

PJVol said:


> Actually the way how it is reported on your board seem to me more logical. At least SET voltage (in pt) do correspond to the actual value set by user, as oppesed to that bull**** reported in my case )
> This leads me to believe that my recent assumptions are not far from truth about the difference in a way Asrock and other vendors access SMU at boot time (i mean using or not APML)
> 
> Anyway, at least on my board (not sure about Veii's though) it's not used. Just tested Auto and 1.290V and Soc power consumption were the same in both cases.
> What's left is to find out, if this change potentially (or rather actually) may happen on your board and how to reproduce it ))


Didn't see this part, sorry.
My guess is that if you ran RM & ZenPTMonitor & Tool1007 and click apply frenetically on your tool something like this will happen very quickly 
I had once my VDDG set to 1200mV from 1000mV... it's just random what will happen.
But mostly if something goes wrong with the command to change the clocks the vCore will be set to 1.55V.
Usually exiting OC mode is enough to bring it back to normal but not always.


----------



## CyrIng

ManniX-ITA said:


> @PJVol
> BTW Did you find a way to read the CO values set in the BIOS?
> 
> 
> 
> Sorry probably is a dumb question for you, but I'm curious
> Is it really a common practice to lock the PCI bus with a mutex or it's just a workaround for AMD's SMU?


Up to now I would admit I was not aware of a PCI Bus lock involved in SMU accesses, at least using index/data mechanism.
Do you have any specs or lines of code to look at ?


----------



## PJVol

Luggage said:


> It’s just an impression


Not quite.


Luggage said:


> enforcing PBO limits set in bios etc…


So it's a bad thing in your opinion? Huh...
Actually I absolutely don't mind what I was saying in post you've quoted, 'cause that metric is not used in zen2/zen3 on my board. More important, for example, is that I didn't ever experienced board vendor's restrictions for me as a user do downgrade to the previous BIOS version or some settings (undesireable) stuck or became persistent as a result of upgrade-downgrade cycle.
As for the first quote, there's always a bungling factor unfortunately.


----------



## ManniX-ITA

CyrIng said:


> Up to now I would admit I was not aware of a PCI Bus lock involved in SMU accesses, at least using index/data mechanism.
> Do you have any specs or lines of code to look at ?


Here:









ryzen_smu/smu.c at 913683d4e17bafe07e83087a5656fd16730c94e6 · leogx9r/ryzen_smu


A Linux kernel driver that exposes access to the SMU (System Management Unit) for certain AMD Ryzen Processors. Read only mirror of https://gitlab.com/leogx9r/ryzen_smu - ryzen_smu/smu.c at 913683d...




github.com





My guess is that is implemented as a workaround to avoid concurrency.


----------



## CyrIng

ManniX-ITA said:


> Here:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ryzen_smu/smu.c at 913683d4e17bafe07e83087a5656fd16730c94e6 · leogx9r/ryzen_smu
> 
> 
> A Linux kernel driver that exposes access to the SMU (System Management Unit) for certain AMD Ryzen Processors. Read only mirror of https://gitlab.com/leogx9r/ryzen_smu - ryzen_smu/smu.c at 913683d...
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> My guess is that is implemented as a workaround to avoid concurrency.


Those mutexes are not applying to Bus, like an atomic instruction can with a lock prefix opcode.

DEFINE_MUTEX(amd_pci_mutex)

... is just a kernel space lock.

SMU access is a weak implemtation: you write on index to select a SMU register and then read/write on data to get/put the value

So what will happen if more than one thread are concurrently selecting different SMU registers on index.
Or getting/putting values on data in middle of the other thread operation.

Yes Kernel created them for concurrency purpose.

AMD would have better provided an atomic mailbox protocol at first.


----------



## Luggage

PJVol said:


> Not quite.
> 
> So it's a bad thing in your opinion? Huh...
> Actually I absolutely don't mind what I was saying in post you've quoted, 'cause that metric is not used in zen2/zen3 on my board. More important, for example, is that I didn't ever experienced board vendor's restrictions for me as a user do downgrade to the previous BIOS version or some settings (undesireable) stuck or became persistent as a result of upgrade-downgrade cycle.
> As for the first quote, there's always a bungling factor unfortunately.


This part.
“Actually the way how it is reported on your board seem to me more logical. At least SET voltage (in pt) do correspond to the actual value set by user, as oppesed to that bull**** reported in my case )”

As for limits - yes I think that limits set in bios should have precedence over any change you can do via software. But that’s just a personal preference of a safe guard against… ex RM doing stupid s***.


----------



## ManniX-ITA

CyrIng said:


> AMD would have better provided an atomic mailbox protocol at first.


Yes indeed it's just a kernel mutex.
At least they should have provided drivers with its own mutex for this purpose.
Sure the average time blocking the PCI bus for everything else is not much but I don't see why...
It's not atomic, it's not transactional.


----------



## PJVol

@CyrIng
Btw, i saw in your repo you have archived your apml (sb-rmi) implementation. Did you ever tested it? I mean does MP1 mailbox interface via sb-rmi work?
Just curious, because I haven't seen anyone from the community had implemented it, and actually I was going to steal your code if only i knew it works 



Luggage said:


> As for limits - yes I think that limits set in bios should have precedence over any change you can do via software.


They don't actually, as I wrote here many times, there just more than one registers for the same limit, and SMU always choose the most restrictive out of them.
To override the values set from msi or asus bios you just need to set them via apml (presumably).


----------



## CyrIng

PJVol said:


> @CyrIng
> Btw, i saw in your code you have archived your apml (sb-rmi) implementation. Did you ever tested it? I mean does it actually work?


I tried but that ACPI/i2c cuisine is a pain. That code is postponed.


----------



## Luggage

PJVol said:


> @CyrIng
> Btw, i saw in your repo you have archived your apml (sb-rmi) implementation. Did you ever tested it? I mean does MP1 mailbox interface via sb-rmi work?
> Just curious, because I haven't seen anyone from the community had implemented it, and actually I was going to steal your code if only i knew it works
> 
> 
> They don't actually, as I wrote here many times, there just more than one registers for the same limit, and SMU always choose the most restrictive out of them.
> To override the values set from msi or asus bios you just need to set them via apml (presumably).


Out of interest, what’s the mb limits on your extreme? My google foo fails me…


----------



## PJVol

Luggage said:


> Out of interest, what’s the mb limits on your extreme?


Those supplied by renesas 229004, i think,
1000w/500a/540a


CyrIng said:


> cuisine


 funny word, is it french? sounds like "cousine" ...


----------



## Luggage

PJVol said:


> Those supplied by renesas 229004, i think,
> 1000w/500a/540a


Can you set edc 600A with your tool?


----------



## PJVol

Luggage said:


> Can you set edc 600A with your tool?


I don't understand where you fit in, sorry.


PJVol said:


> 540a


----------



## Luggage

PJVol said:


> I don't understand where you fit in.


My mb limit is 220. If I set edc to 700 in bios I can use your tool up to 700, if I leave bios on auto I can use your tool up to 220.

Same as RM.

You say you can set it above bios limit on Asrock but I’ve never seen you set it really high. (Or did you with the L3 latency graph?)

Just trying to make sure we don’t have a communication error.


----------



## PJVol

Luggage said:


> My mb limit is 220


Are you sure you're not confusing motherboard limits, i.e. those seen when you set PBO->Advanced and Limits->Motherboard, with those, set manually when you choose Limits->Manual?


----------



## Luggage

PJVol said:


> Are you sure you're not confusing motherboard limits, i.e. those seen when you set PBO->Advanced and Limits->Motherboard, with those, set manually when you choose Limits->Manual?


I’m pretty sure >advanced and limits -> motherboard is what most of us are referring to as mb limits. (This is the limit you can raise to in rm if you leave them on auto)

Manual I think I can set 999 (not at computer atm)


----------



## PJVol

Luggage said:


> This is the limit you can raise to in rm if you leave them on auto


What's the point in raising it then, if it will never apply?
I mean (if I get it right from your post) your BIOS allowed EDC limit to be manually set to max 220 amps, and that it's way below the actual mb limit?


Luggage said:


> This is the limit you can raise to in rm if you leave them on auto


Limits "Auto" are equal to the default CPU limits on my board, i.e. 78/60/90


----------



## Luggage

PJVol said:


> What's the point in raising it then, if it will never apply?
> I mean (if I get it right from your post) your BIOS allowed EDC limit to be manually set to max 220 amps, and that it's way below the actual mb limit?
> 
> Limits "Auto" are equal to the default CPU limits on my board, i.e. 78/60/90


Auto = 142-95-140 
I can use software, RM or your tool to raise it up to
Motherboard = 500? 200? 220
Manual = X y z
I can use software, rm or your tool to change it to whatever lower than xyz

setting still apply (though only thing I can test with is L3 bandwidth and latency)




Luggage said:


> On MSI x570 unify - yea I can set PBO limits up to what I've set in bios but not above and guess if you don't set them above they will top out at mb limits.
> With edc 700 in bios I can use PBO2 tuner up to that limit but not above.
> 
> 
> 
> Code:
> 
> 
> Aida L3
> 140a 649 648 708 10.5
> 170a 708 656 693 10.4
> 220a 701 628 648 10.4
> 350a 743 737 701 10.4
> 400a 748 744 718 10.4
> 500a 746 750 712 10.4
> 700a 742 753 731 10.2
> 800a wont set
> 
> Run to run variance is big (+-30ish) for write, copy, read but latency is +-0.1


----------



## PJVol

What a mess tbh  msi is msi. How can 220A be a mb limit for the EDC on a x570 board? nonsence.
Mb limit is the one that can be actually set, or in other words, according to specs the max peak current of your board's VRM design for the VDDCR_CPU rail, i.e. the 1st vrm loop in your pwm controller.
That 220A looks more like the limit that is set when I choose PBO enabled on my board.


----------



## Taraquin

Man I have to say pbo+200 and co is quite noisy. In general gaming using D15 and fan at 80% abive 65C I often get temps and hence noise up to 70C. Tuning back to +50+co and temp maxes at 60C with same fan profile, performance is very similar (263 vs 267fps SOTTR cpu game avg). L3 in aida is 11.1 vs 10.8 and mem latency is 0.3ns higher, but I consider sticking with +50 now due to noise.


----------



## Taraquin

Silvio1 said:


> Hello, not long ago I have bought myself Ballistix 2x8 3600 CL16 (few weeks ago from amazon.de, 55€), Micron Rev E, I'm running R5 5600X(4.5ghz at 1.25v) with B550M Pro4f. Since I'm like almost only gaming (1080p, in some games even running as low as 1440x1080) I would like my timings tightest as possible. Currently I'm running 3600 CL14-14-17-14-52-30-1T at 1.48v memory and 1.1v soc ofc with FCLK at 1800, I didnt do bunch of testing but didnt get single error in 2021 anta777 testmem (tho it didnt finish since dont have time), I probably still have some space to go down to maybe 1.45v at memory and 1.07v at soc. Also, did not find alot of help on reddit/forums so would like to see if its possible to tighten something else. I guess I still have space to throw tRAS down to like ~21 and possible something else, do not know what tho. Aida64 latency is at 58.3ns. Thanks in advance
> View attachment 2549525


I have a rev E kit on my 12400F and RC need to be 53 and rfc 528 for 3600 to be stable, you may have better bin than me though. Try changing scls to 4, easier to get stable, also try wtrs 4, wtrl 8. I would consider trying hogher speed, 3800 will probably work, but you should try 15 15 18/19 15 ras 43 rc 58 rfc 560 then and turn of gear down mode and set 2t, rest can be kept the same.


----------



## Silvinjo

Taraquin said:


> I have a rev E kit on my 12400F and RC need to be 53 and rfc 528 for 3600 to be stable, you may have better bin than me though. Try changing scls to 4, easier to get stable, also try wtrs 4, wtrl 8. I would consider trying hogher speed, 3800 will probably work, but you should try 15 15 18/19 15 ras 43 rc 58 rfc 560 then and turn of gear down mode and set 2t, rest can be kept the same.


Yesterday I managed to get full test done ( hour and 30ish mins in anta777 2021) and had no errors so this should be 100% stable. Tho I just remembered I have GDM enabled, so tehnically my timings are higher than I'm seeing, right ? I'm gonna mess with GDM off today and try those what you wrote.


----------



## Taraquin

Silvinjo said:


> Yesterday I managed to get full test done ( hour and 30ish mins in anta777 2021) and had no errors so this should be 100% stable. Tho I just remembered I have GDM enabled, so tehnically my timings are higher than I'm seeing, right ? I'm gonna mess with GDM off today and try those what you wrote.


Timings aren't necisarily higher, but GDM tends to smooth things out at a slight speed penalty. If you have a good bin you might be able to run lower RC and RFC. My sticks need RCDRD/RC/RFC at 19/53/528 on 3600 and 20/57/560 on 3800. Another kit did the same, but could run RFC 30 lower.


----------



## Silvinjo

Taraquin said:


> Timings aren't necisarily higher, but GDM tends to smooth things out at a slight speed penalty. If you have a good bin you might be able to run lower RC and RFC. My sticks need RCDRD/RC/RFC at 19/53/528 on 3600 and 20/57/560 on 3800. Another kit did the same, but could run RFC 30 lower.


K I have tried something like 15-15-18-15-43 with 2T and GDM off (ohm set to 120 or smh, I've seen that I need to do that) and my latency actually went up to like 60.5


----------



## Taraquin

Silvinjo said:


> K I have tried something like 15-15-18-15-43 with 2T and GDM off (ohm set to 120 or smh, I've seen that I need to do that) and my latency actually went up to like 60.5


If you don't raise speed from 3600 then cl14 gdm will be faster than 3600 cl15 2t. Try 3800 and 15-15-18-15 2t. 120 ohm sounds high, 60 don't work?


----------



## Luggage

PJVol said:


> What a mess tbh  msi is msi. How can 220A be a mb limit for the EDC on a x570 board? nonsence.
> Mb limit is the one that can be actually set, or in other words, according to specs the max peak current of your board's VRM design for the VDDCR_CPU rail, i.e. the 1st vrm loop in your pwm controller.
> That 220A looks more like the limit that is set when I choose PBO enabled on my board.


Just for reference.
Manual maxed out vs “motherboard” vs auto


http://imgur.com/a/Q93lFy7


----------



## PJVol

Luggage said:


> Just for reference


Thanks for clear it up )
My mb limits are 1000/500/540. They're the maximum values allowed to set as well.

=================
BTW someone check pls the updated PBO2 tuner
(removed user settings, since now CO counts should read directly)





Debug.7z







drive.google.com


----------



## ManniX-ITA

PJVol said:


> BTW someone check pls the updated PBO2 tuner
> (removed user settings, since now CO counts should read directly)


You are great man! 
Works like a charm:


----------



## Audioboxer

Can confirm, works great.

Now I just need to dig up the posts from earlier in this topic that gave advice on how to speed up the corecycler process lol. Something to do with changing the FTT size?

Wish I hadn't bothered spending time with AGESA 1.2.0.5 mind you, seems like whatever is to come next will likely change everything again. I'd advise everyone stays on 1.2.0.3c until AMD fix their broken BIOS, again.

On that note Gigabyte seems to releasing 1.2.0.6b now, so this time around it's MSI turn to be incredibly slow. And yes, going over 140 EDC still limits voltage...


----------



## lafonte

Audioboxer said:


> View attachment 2549651
> 
> On that note Gigabyte seems to releasing 1.2.0.6b now, so this time around it's MSI turn to be incredibly slow. And yes, going over 140 EDC still limits voltage...


Can you confirm if the vddg bug as been fixed please?


----------



## Audioboxer

lafonte said:


> Can you confirm if the vddg bug as been fixed please?


VDDG bug was fixed a while back, so yes.

IIRC it was only 1.2.0.4 beta releases that had it (1.2.0.4 final never came).


----------



## FantasmaN3D

PJVol said:


> Thanks for clear it up )
> My mb limits are 1000/500/540. They're the maximum values allowed to set as well.
> 
> =================
> BTW someone check pls the updated PBO2 tuner
> (removed user settings, since now CO counts should read directly)
> 
> 
> 
> 
> 
> Debug.7z
> 
> 
> 
> 
> 
> 
> 
> drive.google.com


It works for me too. However, now there is no way to know what was the last tried setting (if there is a restart due to instabilities), right?

Greetings


----------



## ManniX-ITA

Audioboxer said:


> Now I just need to dig up the posts from earlier in this topic that gave advice on how to speed up the corecycler process lol. Something to do with changing the FTT size?


Here:








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


To do 3800 trcd 13 we need to increase tfaw and the room to reduce is depending on the RAM yield; clkdrvstr, more memory voltage is needed . Memory voltage also differs widely depending on yield; timing yields separate memory voltage yields. I've done a lot of research now and I've found that...




www.overclock.net





But since you are starting a new cycle give a try at y-cruncher with CoreCycler.
I would start with 10 minutes per Core.

You just need to change:

stressTestProgram = YCRUNCHER

And comment the line with PRIME95.

As testmode start first with ""19-ZN2 ~ Kagari" which was reported faster than Prime to spot errors.
Then with 00-x86, it'll push the max clock achievable.

# "00-x86" should produce the highest boost clock on most tests
# "19-ZN2 ~ Kagari" is optimized for Zen2/3, but produces more heat and a lower boost clock on most tests
# Default: 00-x86
mode = 00-x86



FantasmaN3D said:


> It works for me too. However, now there is no way to know what was the last tried setting (if there is a restart due to instabilities), right?


Greenshot is your friend 






Greenshot


Greenshot - a free screenshot tool optimized for productivity




getgreenshot.org





Take a screenshot and save it.


----------



## Luggage

Audioboxer said:


> View attachment 2549651
> 
> 
> Can confirm, works great.
> 
> Now I just need to dig up the posts from earlier in this topic that gave advice on how to speed up the corecycler process lol. Something to do with changing the FTT size?
> 
> Wish I hadn't bothered spending time with AGESA 1.2.0.5 mind you, seems like whatever is to come next will likely change everything again. I'd advise everyone stays on 1.2.0.3c until AMD fix their broken BIOS, again.
> 
> On that note Gigabyte seems to releasing 1.2.0.6b now, so this time around it's MSI turn to be incredibly slow. And yes, going over 140 EDC still limits voltage...











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


To do 3800 trcd 13 we need to increase tfaw and the room to reduce is depending on the RAM yield; clkdrvstr, more memory voltage is needed . Memory voltage also differs widely depending on yield; timing yields separate memory voltage yields. I've done a lot of research now and I've found that...




www.overclock.net





and









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Try the following: 13 13 13, but set ras to 26, rc to 39, rrd/faw to 6/6/24, if it works try a bit lower ras/rc or 5/5/20 :) Both RC and FAW can impact RCDRD tuning :) Seeing as it fails with everything on AUTO, I doubt it lol




www.overclock.net










Luggage said:


> After some more testing I think it's actually yc being much better at crashing cores.
> 
> 
> This made me change co 5-6 values on cores that survived all night with the 720 and 16k-27k tests from
> 
> 
> 
> Admittedly didn't run all ffts but the yc test found errors on the first cycle on cores i haven't touched in weeks


----------



## FantasmaN3D

ManniX-ITA said:


> Greenshot is your friend
> 
> 
> 
> 
> 
> 
> Greenshot
> 
> 
> Greenshot - a free screenshot tool optimized for productivity
> 
> 
> 
> 
> getgreenshot.org
> 
> 
> 
> 
> 
> Take a screenshot and save it.


Thanks for the program. I just thought that for oc, it was more convenient before:

Instead of dozens of screenshots (screenshot per setting change), you could just change a lot of values until it crashed and then, when coming back, screenshot, reset, and copy the values. (Unless a very hard reset, where you lose everything and the program does not work until removing the corresponding folder in AppData).
If you are trying to fit the VIDs of different cores in multithreading (in order not to waste time in too negative CO values that will not be used anyway), taking a screenshot every time is a bit annoying and slow, but much better that going into bios every time, for sure.
If you are tuning the CO values, probably, what you set in bios is not so important. It is usually the case that you insert the CO values in bios when the fitting is completely ready.

The information is good if you just start and do not remember what settings you had before or to type your settings in the forum while looking at them in the program but, in my opinion, not so useful for the oc process.

I hope it is not taken as a big criticism to the development of the program (I already wrote that this is the most useful program for CO that the community really needed and I love it). It is just that, from my point of view, I found it more practical for the oc process before.

Greetings


----------



## lafonte

Audioboxer said:


> VDDG bug was fixed a while back, so yes.


 Actually the the X570 pro had it also with the F35 1.2.0.5 the last bios without the vddg bug for me is the F34 1.2.0.3, anyway thanks for the feedback I'll give a shot to this new release


----------



## Audioboxer

lafonte said:


> Actually the the X570 pro had it also with the F35 1.2.0.5 the last bios without the vddg bug for me is the F34 1.2.0.3, anyway thanks for the feedback I'll give a shot to this new release


Interesting, I don't know how they managed that seeing as 1.2.0.5 fixed the VDDG bug lol.

You're not mixing it up with the VCORE bug that caps voltage at 1.425v? That is still present.

AMD gracing us with all sorts of AGESA bugs and jank recently.


----------



## endursa

Asus just released Bios 4004 with AGESA 1.2.0.6b for the Crosshair VIII series.

I just dialed everything (ram, POB/CO) in with 1.2.0.5 (Bios 3904) 
Maybe I'll update in the evening and see if the stress tests will still funktion over night  

or has someone else reports on 1.2.0.6b fclk PBO/co stability changes?


----------



## lafonte

Audioboxer said:


> Interesting, I don't know how they managed that seeing as 1.2.0.5 fixed the VDDG bug lol.
> 
> You're not mixing it up with the VCORE bug that caps voltage at 1.425v? That is still present.


No I'm not mixing it, I'm talking about the vddg settings that doesn't set the voltage but stick on auto setting. That has always been present with all F35 betas and F35 final for me. The vcore cap too has always been present with the last 2 agesa. That one looks like another issue of the motherboard manufacturers and not of agesa if the fit algorithm has some kind of limit to the vcore voltage for EDC over 140 that should be true also when the EDC is increased via software, but since if set via software all works has usual most likely also that "bug" is another not well implement setting. Will be nice to know if this issues happens 'cause the boards manufacturers don't care or if is amd that doesn't give to them the tools to implement the settings properly, or both of them.


----------



## ManniX-ITA

Audioboxer said:


> Interesting, I don't know how they managed that seeing as 1.2.0.5 fixed the VDDG bug lol.


There are different 1.2.0.5 releases... on the Unify-X it was fixed but could be other boards it's not the same.
Seems that it is fixed in 1.2.0.6, all rels.


----------



## Melan

Melan said:


> Today I got greeted by ntoskrnl.exe corruption on cold boot. yada yada...


Apparently the settings were stable all along. The only reason why I get corruption errors on boot is Memory Fast Boot on MSI. I usually disable it for the duration of testing, but with 4 DIMMs it should be off all the time. Weird it didn't complain with 2 DIMMs.


----------



## dk_mic

ManniX-ITA said:


> Here:
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> To do 3800 trcd 13 we need to increase tfaw and the room to reduce is depending on the RAM yield; clkdrvstr, more memory voltage is needed . Memory voltage also differs widely depending on yield; timing yields separate memory voltage yields. I've done a lot of research now and I've found that...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> But since you are starting a new cycle give a try at y-cruncher with CoreCycler.
> I would start with 10 minutes per Core.
> 
> You just need to change:
> 
> stressTestProgram = YCRUNCHER
> 
> And comment the line with PRIME95.
> 
> As testmode start first with ""19-ZN2 ~ Kagari" which was reported faster than Prime to spot errors.


This is madness, makes cores drop that have been stable for many cycles of p95 with various fft sizes in corecycler.
I noticed that especially the N32 caused reboots for me.

You can actually adjust which y-cruncher tests are used in the powershell script


Code:


#    $configEntries = @(
#        '{'
#        '    Action : "StressTest"'
#        '    StressTest : {'
#        '        AllocateLocally : "true"'
#        $coresLine
#        $memoryLine
#        '        SecondsPerTest : 60'
#        '        SecondsTotal : 0'
#        '        StopOnError : "true"'
#        '        Tests : ['
#        '            "BKT"'
#        '            "BBP"'
#        '            "SFT"'
#        '            "FFT"'
#        '            "N32"'
#        '            "N64"'
#        '            "HNT"'
#        '            "VST"'
#        '        ]'
#        '    }'
#        '}'
#    )

Gonna re-test my curve running only N32 now. Wonder if this kind of stability is even needed in normal operation..


----------



## ManniX-ITA

dk_mic said:


> This is madness, makes cores drop that have been stable for many cycles of p95 with various fft sizes in corecycler.
> I noticed that especially the N32 caused reboots for me.


Oh god, now I'm really scared to test it


----------



## endursa

So I just upgraded to the new asus Crosshair VIII Impact bios 4004 with 1.2.0.6b
So far the bench results are the same, stability needs to be tested over night 

1.2.0.5










1.2.0.6b


----------



## ManniX-ITA

dk_mic said:


> Gonna re-test my curve running only N32 now. Wonder if this kind of stability is even needed in normal operation..


Did you test all with Prime95?
Cause Kagari is AVX2 so to be comparable to P95 you should have tested all AVX2 FFTs.


----------



## dk_mic

nope, didn't test avx2, only lots of SSE, maybe that is why. But i had to go from like -25 to -16 on one core and I just started 😱


----------



## PJVol

dk_mic said:


> Wonder if this kind of stability is even needed in normal operation..


No, because these conditions are far from being close to real, and SMU just won't let it happen in normal type of workload, when and if CPPC2 isn't ignored or broken, as it was untill recent cppc2 driver update.


----------



## ManniX-ITA

dk_mic said:


> nope, didn't test avx2, only lots of SSE, maybe that is why. But i had to go from like -25 to -16 on one core and I just started 😱


Ouch... I'm testing with 10 minutes and so far my 3 best cores passed.


----------



## Audioboxer

Never even noticed Corecycler came with y-cruncher till the replies I got earlier lol.

So ycruncher and 19-ZN2 is killing core settings? Let me check my 4 best cores with that then 

I normally just run ycruncher itself with 1/0/7.

The number of people out there that must have unstable curves


----------



## Luggage

Audioboxer said:


> Never even noticed Corecycler came with y-cruncher till the replies I got earlier lol.
> 
> So ycruncher and 19-ZN2 is killing core settings? Let me check my 4 best cores with that then
> 
> I normally just run ycruncher itself with 1/0/7.
> 
> The number of people out there that must have unstable curves


My best ones was ok after p95 testing. Y-cruncher crashed other cores…


----------



## Audioboxer

Luggage said:


> My best ones was ok after p95 testing. Y-cruncher crashed other cores…


Do you run ycruncher normally like I do before calling stable? Or is this test using ycruncher in a different way from the standard stability test option?










Started anyway on my 4 best cores so I'll see how it goes!


----------



## Luggage

@Veii do you know how low L3 latency scales with edc?
Got 10.1-10.0 with “stupid 4096 edc”…




Luggage said:


> Just for reference.
> Manual maxed out vs “motherboard” vs auto
> 
> 
> http://imgur.com/a/Q93lFy7


----------



## Luggage

Audioboxer said:


> Do you run ycruncher normally like I do before calling stable? Or is this test using ycruncher in a different way from the standard stability test option?


Yea but only all core… single core with corecycler boost higher 🥵


----------



## Audioboxer

Luggage said:


> Yea but only all core… single core with corecycler boost higher 🥵


Yeah that makes sense, I was forgetting doing it the normal way is an all core boost.

Running 19-ZN2 ~ Kagari now, fingers crossed!


----------



## MrHoof

If you look at the ycrunsher window u can see the test running. Everything but test 19.









edit: But as PJVol said


PJVol said:


> No, because these conditions are far from being close to real, and SMU just won't let it happen in normal type of workload, when and if CPPC2 isn't ignored or broken, as it was untill recent cppc2 driver update.


Under normal conditions the thread will switch cores before it crashes.


----------



## ManniX-ITA

PJVol said:


> No, because these conditions are far from being close to real, and SMU just won't let it happen in normal type of workload, when and if CPPC2 isn't ignored.


Yes but of course with exceptions...
I tried on purpose to run with slightly unstable cores on my 2nd CCD cause I was curious.
Doesn't work, you'll get random reboots in idle. Not funny 

The catch is the instruction set. You can probably get away with AVX2 unstable.
It's pretty uncommon, extremely rare, in "normal" use (eg Office, browsing, gaming) to run software which is using AVX2 and doesn't run following CPPC or at all-core.

Not the same for AVX and definitely not for SSE.
If you have any Core unstable with SSE you'll get a random reboot every now or then.

That's due first to the windows scheduler and second to specific multi threaded optimizations.
The scheduler runs low load threads on low CPPC tags cores when the good ones are loaded.
Or switches the threads to them when they are detected as low loads.
This mostly works except when they suddenly becomes high load...

At this point if the spike is very quick the scheduler could lag enough time before moving them.
And if the core is unstable it will crash and bam reboot.
This will happen also if the good cores are loaded, the scheduler will keep the high load where it is.

With a dual CCD this happens very frequently.
A bad core on a 2nd CCD, like on my average sample, doesn't boost more than around 4850 MHz.
With plenty of power budget available, even if 3 of the best cores are loaded on CCD1, it can spike to the max with SSE instructions.
And if it's even remotely unstable bam reboot.

Then there's a lot of software with specific multi threaded optimizations to distribute load.
They often completely bypass the windows scheduler and thus CPPC.
I think one of these is Chrome.
Like almost everyone else, it's a workload where I get a sudden reboot "in idle" in 5-10 minutes, usually watching a Youtube video.
Chrome is firing background tasks on my 2nd CCD cores very often.
And when they get loaded, reboot.
A background task is not supposed to get loaded normally but it can happen.
Maybe it's a maintenance task packing and optimizing a database and it got very big.
You can't be ever really sure that a low load task doesn't get run at full speed on a bad core.

Another software which is doing this is the Microsoft C# CLR 
The ubiquitous Linq library, which you need for lists and almost 90% of the cool C# stuff, is now parallelized.
It's called PLINQ and you can execute queries with the AsParallel method.
The CLR will distribute automatically the queries over the cores.
And it will totally disregard the CPPC and the scheduler.
Once a a thread affinity is set it will hardly be shifted unless there's a big change in the queries load.

I've made a simple test from the Microsoft example to see how it was distributing the load.
Wonder where the highest load is put on my CPU?









These are my CPPC tags:









Despite the quality index at 172 the Core 9 is the worst in CCD#2.

Any C# software using Linq parallel queries (many) could cause reboots on my PC if SSE wasn't stable.
My recommendation is also to test AVX fully but if you really don't want at least the best cores.
I wouldn't skip it anyway, at least one cycle full FFTs per Core.
With AVX2 it's a different story.
I didn't really had to make major changes but for many, getting it stable, meant really a big hit in CO counts.
You can't be 100% sure the CPU will never crash but let's say 99% of the time will not happen.
It's a personal choice on what is the risk you are willing to accept


----------



## Audioboxer

ManniX-ITA said:


> Yes but of course with exceptions...
> I tried on purpose to run with slightly unstable cores on my 2nd CCD cause I was curious.
> Doesn't work, you'll get random reboots in idle. Not funny
> 
> The catch is the instruction set. You can probably get away with AVX2 unstable.
> It's pretty uncommon, extremely rare, in "normal" use (eg Office, browsing, gaming) to run software which is using AVX2 and doesn't run following CPPC or at all-core.
> 
> Not the same for AVX and definitely not for SSE.
> If you have any Core unstable with SSE you'll get a random reboot every now or then.
> 
> That's due first to the windows scheduler and second to specific multi threaded optimizations.
> The scheduler runs low load threads on low CPPC tags cores when the good ones are loaded.
> Or switches the threads to them when they are detected as low loads.
> This mostly works except when they suddenly becomes high load...
> 
> At this point if the spike is very quick the scheduler could lag enough time before moving them.
> And if the core is unstable it will crash and bam reboot.
> This will happen also if the good cores are loaded, the scheduler will keep the high load where it is.
> 
> With a dual CCD this happens very frequently.
> A bad core on a 2nd CCD, like on my average sample, doesn't boost more than around 4850 MHz.
> With plenty of power budget available, even if 3 of the best cores are loaded on CCD1, it can spike to the max with SSE instructions.
> And if it's even remotely unstable bam reboot.
> 
> Then there's a lot of software with specific multi threaded optimizations to distribute load.
> They often completely bypass the windows scheduler and thus CPPC.
> I think one of these is Chrome.
> Like almost everyone else, it's a workload where I get a sudden reboot "in idle" in 5-10 minutes, usually watching a Youtube video.
> Chrome is firing background tasks on my 2nd CCD cores very often.
> And when they get loaded, reboot.
> A background task is not supposed to get loaded normally but it can happen.
> Maybe it's a maintenance task packing and optimizing a database and it got very big.
> You can't be ever really sure that a low load task doesn't get run at full speed on a bad core.
> 
> Another software which is doing this is the Microsoft C# CLR
> The ubiquitous Linq library, which you need for lists and almost 90% of the cool C# stuff, is now parallelized.
> It's called PLINQ and you can execute queries with the AsParallel method.
> The CLR will distribute automatically the queries over the cores.
> And it will totally disregard the CPPC and the scheduler.
> Once a a thread affinity is set it will hardly be shifted unless there's a big change in the queries load.
> 
> I've made a simple test from the Microsoft example to see how it was distributing the load.
> Wonder where the highest load is put on my CPU?
> View attachment 2549699
> 
> 
> These are my CPPC tags:
> View attachment 2549700
> 
> 
> Despite the quality index at 172 the Core 9 is the worst in CCD#2.
> 
> Any C# software using Linq parallel queries (many) could cause reboots on my PC if SSE wasn't stable.
> My recommendation is also to test AVX fully but if you really don't want at least the best cores.
> I wouldn't skip it anyway, at least one cycle full FFTs per Core.
> With AVX2 it's a different story.
> I didn't really had to make major changes but for many, getting it stable, meant really a big hit in CO counts.
> You can't be 100% sure the CPU will never crash but let's say 99% of the time will not happen.
> It's a personal choice on what is the risk you are willing to accept


So that ycruncher test is SSE?










Seems to be going OK for me so far on my 4 best cores.

*edit* - Just noticed your post above, it's AVX2


----------



## ManniX-ITA

Audioboxer said:


> So that ycruncher test is SSE?


No it's mostly AVX2, you can see it at the beginning.










The "00-x86" test mode is using legacy instruction sets, not SSE.

Not sure yet which mode is the best to run SSE on Ryzen.


----------



## Audioboxer

ManniX-ITA said:


> No it's mostly AVX2, you can see it at the beginning.
> 
> View attachment 2549704
> 
> 
> The "00-x86" test mode is using legacy instruction sets, not SSE.
> 
> Not sure yet which mode is the best to run SSE on Ryzen.


Yeah I noticed just before you quoted me.

Haven't failed anything so far but I'd be gutted if I did considering all the hours I put into testing this curve. I was interested though due to the feedback people who passed the standard corecycler runs were seeing fails quickly with y-cruncher.

Never had a reboot/crash of an app either, but that's never a good metric for stability. They can sometimes take weeks/months. Unless you are comically unstable!


----------



## PJVol

ManniX-ITA said:


> Yes but of course with exceptions...
> I tried on purpose to run with slightly unstable cores on my 2nd CCD cause I was curious.
> Doesn't work, you'll get random reboots in idle. Not funny


Well, those for the most part are fair points.
Except i'd argue a little about the causes of random/idle reboots.
My stance on it is 80% for either the faulty CPU or the power supply issues and 20% for the wrong scheduling.
I'm pretty sure, that ideally, if all power delivery specs are fully met and the firmware has no crytical bugs, there shouldnt be sudden reboots at all,
especially in idle - that is just obviously hardware flaw to my mind.
Did you ever tracked down the hw error source in such cases?



ManniX-ITA said:


> With a dual CCD this happens very frequently.
> A bad core on a 2nd CCD, like on my average sample, doesn't boost more than around 4850 MHz.
> With plenty of power budget available, even if 3 of the best cores are loaded on CCD1, it can spike to the max with SSE instructions.


I've got similar "bad" core in my only CCD, and it's indeed the worst core, and yes, scheduler often loads it amongst the best ones, that is clear when you running hwinfo sensor panel open - it mostly sitting on that bad core. But I noticed that that and the 2nd best are the most power hungry out of six, and from my experience, they are the ones that in 99% cases crushes in an heavy all-core loads.
Unfortunately they are at the same time mostly defines max. all-core boost.


----------



## ManniX-ITA

PJVol said:


> My stance on it is 80% for either the faulty CPU or the power supply issues. I'm pretty sure, that ideally, if all power delivery specs are fully met and the firmware has no crytical bugs, there shouldnt be sudden reboots at all,
> especially in idle - that is just obviously hardware flaw to my mind.
> Did you ever tracked down the hw error source in such cases?


I'm talking about unstable CO counts.
With the correct count (or no CO enabled at all), it doesn't happen.
Most of my reboots at idle were coming from the CO count on Core 9, 11 and 15.
Even a -1 too much can create mayhem.

And especially the bastard Core 9 it has been very hard to catch unstable.
It passed multiple cycles without erroring.
Found out it was unstable cause I was running OCCT.
Worst thing is that I got completely crazy cause my best Cores on CCD1 started to fail randomly with CoreCycler.
And I knew they were stable and they were passing one day 10 cycles and the next failing in 2 minutes.
It was all about the Core 9 which was one count too low...


----------



## Audioboxer

The boost here is like 4,934mhz (4,950mhz seems to be highest I've eye-balled beyond screenshot) on core 5, so reasonably decent for checking for errors, I guess. Though under even lighter loads as we can see my core 5 has managed 5,055mhz.

Though I guess this might depend on what y-cruncher test is running?


----------



## ManniX-ITA

Audioboxer said:


> The boost here is like 4,934mhz on core 5, so reasonably decent for checking for errors, I guess. Though under even lighter loads as we can see my core 5 has managed 5,055mhz.


Yes the peak is probably the test #1 BKT which is not AVX2.
Anyway I passed a full cycle of 10 minutes just now


----------



## Audioboxer

ManniX-ITA said:


> Yes the peak is probably the test #1 BKT which is not AVX2.
> Anyway I passed a full cycle of 10 minutes just now


Yeah I'm just getting a bit confused. I was thinking 19-ZN2 ~ Kagari is a specific test that gets looped but it seems like what is happening is a number of the standard y-cruncher tests are running but just on one core? Is that right?


----------



## ManniX-ITA

Audioboxer said:


> Yeah I'm just getting a bit confused. I was thinking 19-ZN2 ~ Kagari is a specific test that gets looped but it seems like what is happening is a number of the standard y-cruncher tests are running but just on one core? Is that right?


Kagari is the optimized binary for Zen2+:

*Tuning: Windows/19-ZN2 ~ Kagari - Zen 2 Matisse (x64 ADX)*

It's the same which is auto selected when you run normally y-cruncher.

The script is changing CPU affinity to run it over a different core(s)


----------



## Audioboxer

ManniX-ITA said:


> Kagari is the optimized binary for Zen2+:
> 
> *Tuning: Windows/19-ZN2 ~ Kagari - Zen 2 Matisse (x64 ADX)*
> 
> It's the same which is auto selected when you run normally y-cruncher.
> 
> The script is changing CPU affinity to run it over a different core(s)


Ahhh, I fully get it now!










Getting close to saying my 4 best cores are probably fine. They've had plenty of hours of normal corecycler with P95 as well.

Time to test the rest overnight.

The downsides of a 5950x when it comes to testing time, 2 CCDs


----------



## PJVol

ManniX-ITA said:


> Most of my reboots at idle were coming from the CO count on Core 9, 11 and 15.


Are they power hungry, or unusually hot compared to the rest while heavily loaded?

PS: Do you know what the #15 test is stressing the most? Is it purely FPU or other uncore parts as well?


----------



## lafonte

dk_mic said:


> N32


N64 is the best for find co instability, also 60sec is enough to find instability cause the bench has a really variable load and it stress a lot the transient response prime is a pretty steady test probably better for find thermal instability in small fft and for test the memory and the memory controller in large fft but definitely not a great bench for tune the curve optimizer.


----------



## ManniX-ITA

PJVol said:


> Are they power hungry, or unusually hot compared to the rest while heavily loaded?


Not unusually 
They are power hungry considering the low speed.

The whole CCD#2 cores are slower but runs about 100mV higher than CCD#1.

This is after a CB23 run:









This is while running CB23:









This is while running the monero miner benchmark:









Sometimes when they boost they consume almost like the good ones on CCD#1.
They need same or more voltage for 200-300 MHz less


----------



## ManniX-ITA

lafonte said:


> N64 is the best for find co instability, also 60sec is enough to find instability cause the bench has a really variable load and it stress a lot the transient response prime is a pretty steady test probably better for find thermal instability in small fft and for test the memory and the memory controller in large fft but definitely not a great bench for tune the curve optimizer.


Well I don't go deep in the mathematics but y-cruncher is more or less like Prime95... another pi calculation program 
N64 is a Small FFT algorithm:



Large Multiplication


----------



## dk_mic

30 18 30 30 30 30 15 30 25 29 30 26 30 30 23 22 (p95 SSE stable)
30 18 29 29 30 30 15 23 16 26 22 21 30 30 22 11 (3 min y-cruncher 19-ZN2 N32 stable)

203 212 208 190 199 185 212 194 176 158 167 172 154 149 163 181 (ratings)

I had to adjust many cores, just so they would make it through the N32 test for 3 minutes.

I guess the big differences is due to the curve was never dialed in AVX2 prime95, only SSE.
Also, the Initial curve was made on 1.2.0.5 with high EDC limits, so VCore is was restricted.
Currently and I am probably keeping it like this, I am running default AMD powerlimits on 1.2.0.5, auto oc (positive, auto ~ 50 Mhz) and seeing VCore close to 1.5V.
Hydra on 100% stock bios says its a platinum/silver sample. Its a B2 from 2022
Gonna give N64 a shot next, as suggested


----------



## KedarWolf

dk_mic said:


> 30 18 30 30 30 30 15 30 25 29 30 26 30 30 23 22 (p95 SSE stable)
> 30 18 29 29 30 30 15 23 16 26 22 21 30 30 22 11 (3 min y-cruncher 19-ZN2 N32 stable)
> 
> 203 212 208 190 199 185 212 194 176 158 167 172 154 149 163 181 (ratings)
> 
> I had to adjust many cores, just so they would make it through the N32 test for 3 minutes.
> 
> I guess the big differences is due to the curve was never dialed in AVX2 prime95, only SSE.
> Also, the Initial curve was made on 1.2.0.5 with high EDC limits, so VCore is was restricted.
> Currently and I am probably keeping it like this, I am running default AMD powerlimits on 1.2.0.5, auto oc (positive, auto ~ 50 Mhz) and seeing VCore close to 1.5V.
> Hydra on 100% stock bios says its a platinum/silver sample. Its a B2 from 2022
> Gonna give N64 a shot next, as suggested


This is what I run Core Cycler and Y-Cruncher all tests stable. I run Core Cycler at 720-720 6 minutes for 18 hours single thread and 2 threads. I find it finds errors quick.


----------



## ManniX-ITA

dk_mic said:


> I guess the big differences is due to the curve was never dialed in AVX2 prime95, only SSE.
> Also, the Initial curve was made on 1.2.0.5 with high EDC limits, so VCore is was restricted.
> Currently and I am probably keeping it like this, I am running default AMD powerlimits on 1.2.0.5, auto oc (positive, auto ~ 50 Mhz) and seeing VCore close to 1.5V.


Would be nice if after this setup cycle you could run full FFTs in AVX2 on the cores you had to drop the most CO count.
Like 7 and 15/16.
This way we would know if running y-c Kagari with N32/N64 is enough or a full P95 sweep is more reliable.


----------



## ManniX-ITA

KedarWolf said:


> This is what I run Core Cycler and Y-Cruncher all tests stable. I run Core Cycler at 720-720 6 minutes for 18 hours single thread and 2 threads. I find it finds errors quick.


Just 720-720 isn't enough. It's good for a quick first round and minimize the time you need later.
But afterwards running all FFTs is the only way to be sure.


----------



## KedarWolf

ManniX-ITA said:


> Just 720-720 isn't enough. It's good for a quick first round and minimize the time you need later.
> But afterwards running all FFTs is the only way to be sure.


I ran Heavy on Auto, all FFTs in the cycle, and I never found errors until I ran 720-720. Had to lower more cores quite a bit.

Edit: I think because it switches FFTs so much on Auto, it really doesn't run any single one long enough to find errors, why 720-720 is more effective.


----------



## Lobstar

Anyone have any tips on where to start? I've got this kit (CMK128GX4M4A2400C16) on my 3950x/Crosshair 8 Hero combo. I've got the 4x32GB running at 3600/1800 but it's at auto timings and I've not touched any voltages. Also, I have zero clue what voltage these would want to run at. I've only every had Samsung B-die on Ryzen, never Micron so I'm not familiar with it.


----------



## ManniX-ITA

KedarWolf said:


> I ran Heavy on Auto, all FFTs in the cycle, and I never found errors until I ran 720-720. Had to lower more cores quite a bit.


Finding a good FFT size is not trivial indeed 
The size matters, also in this case...
Fitting wholly in L1 or L2 or L3 is a big difference.

Hammering one FFT only it seems to be quite a challenge of its own.
720K doesn't fit in L1 512K but does fit in L2.
It's small enough to be run mostly in L1 (which will generate a lot of heat and limit the max and sustained clock) if you don't have background tasks hitting the processor.
But at the same time is testing L2 too.
L3 is probably used as well but not that much.

I tried to dive in on Prime calculation but I gave up.
Despite some decent foundations on math analysis and signal processing from 30 years ago, it's really too much for me.
But there's a reason why Prime95 Small FFTs is called "Torture test".

Here's a decent brief:
_Prime Factor Algorithm provides an unified derivation of the Cooley-Tukey FFT and the Winograd Fourier Transform Algorithm (WFTA) FFT. In this method of reduction, arithmetic is used as an index mapping (a change of variables) to change the one-dimensional DFT into a two or higher dimensional DFTs. _*This is done in order to change a large problem into several easier smaller ones which makes its computing quicker and simpler and thereby reducing the computational time and does not require any butterfly structures.*

Basically Small FFTs are "harder" to compute than large FFTs.
Because the original problem is split in smaller units with large FFTs.
This means that you can fully utilize the parallelization and branching algorithms in modern CPUs.
The advantage scales up linearly if the CPU has big Lx caches at its disposal.

That's why it's important to test Large FFTs as well.
The CPU will be used in a different manner and the caches too.

The Small FFT makes a big difference on all-core regarding power and temperatures but almost none when tested on one core.
It's more or less the same power and temp per core; power it's always low around 18-20W and temp around 65c for me.
But behind the scenes the CPU is stressed in a different way.

With Large FFTs the easier calculation will use less cycles and will be better predicted and parallelized.
The clock will boost much higher; some Large FFTs will boost the clock 100-200 MHz higher than a Small FFT.
If you are using PBO and extending the max boost clock it's crucial to test Large FFTs.
And of course also the L3 cache will start to play an important role bigger is the FFT.

That's also why running a single FFT size it's a challenge of its own.
When P95 does not switch the FFT size in the next round of calculation the CPU will profit from what was done in the previous one.
While if it's changing FFT size it's a new slate.


----------



## Audioboxer

Managed to produce a reboot on Core 10 which is at -27! 

So can confirm the y-cruncher setup seems to be good at triggering issues in cores that seem to sail past P95.


----------



## ManniX-ITA

Audioboxer said:


> So can confirm the y-cruncher setup seems to be good at triggering issues in cores that seem to sail past P95.


Do you know exactly which test failed (N32,N64,etc)?
Were you running Kagari bin?


----------



## Audioboxer

ManniX-ITA said:


> Do you know exactly which test failed (N32,N64,etc)?
> Were you running Kagari bin?


Kagari. The logs in the Corecycler folder sadly don't seem to tell you what test was running, just shows the last core in use before reboot which was Core 10.

Should be quite easy to reproduce if I just stick 10 on a loop only right now and watch it.


----------



## Taraquin

Lobstar said:


> Anyone have any tips on where to start? I've got this kit (CMK128GX4M4A2400C16) on my 3950x/Crosshair 8 Hero combo. I've got the 4x32GB running at 3600/1800 but it's at auto timings and I've not touched any voltages. Also, I have zero clue what voltage these would want to run at. I've only every had Samsung B-die on Ryzen, never Micron so I'm not familiar with it.
> 
> View attachment 2549754
> View attachment 2549755


My advice: Find highest stable speed first. Try 3800 with all timings at auto, if you can`t boot, get loads of WHEA 19 or get random reboots drop to 3733, if that fails try 3666. 3800 or 3733 might work. Keep ProcODT, voltages at auto, your current settings are really good for auto-values. Once you have found your highest stable speed, set ram voltage to 1.45V and try 1 by one timing:
CL 18, then CL16, if it works try
RCDRD\RW 22, then 21 and so on
Keep RP same as RCDRD
RAS= RCDRD+RP
RC= RAS+RP

Next up, most important timings:
RRDS\L and FAW 6\8\24, if it works try 5\7\20, if that works try 4\6\16
WR=CL and RTP half of WR
RFC: Try 640, if it works try 608, if that works lower by 32, if it fails try 32 higher
RDWR: 12, try 11 if 12 works, and 10 if that works
WRRD: 3

Less important:
WTRS\L=4\12, work your way down to 3\8 if you can, lower one by one
SCL`s= try 4

Expected results depending on binning:
Best case:
3800 16-19-19-19-38-57 rrd\faw:4\4\16 rfc 576

Worst case:
3600 18-22-22-22-44-66 rrd\faw 6\8\24 rfc 704

It will be way faster than what you currently run no matter what


----------



## ManniX-ITA

You can also run only one test modifying the script script-corecycler.ps1, look for the block below.

Just put an # at the beginning of the line of the test you want disabled.

Below will run only N64:



Code:


    $configEntries = @(
        '{'
        '    Action : "StressTest"'
        '    StressTest : {'
        '        AllocateLocally : "true"'
        $coresLine
        $memoryLine
        '        SecondsPerTest : 60'
        '        SecondsTotal : 0'
        '        StopOnError : "true"'
        '        Tests : ['
#        '            "BKT"'
#        '            "BBP"'
#        '            "SFT"'
#        '            "FFT"'
#        '            "N32"'
        '            "N64"'
#        '            "HNT"'
#        '            "VST"'
        '        ]'
        '    }'
        '}'
    )


----------



## Audioboxer

Had to drop it down to -22 to pass a single iteration!










I had it at -26, but heck, my Hydra "guaranteed" claimed it should be -27!

Going on what I'm discovering here the number of people out there with unstable cores must be


----------



## ManniX-ITA

Audioboxer said:


> I had it at -26, but heck, my Hydra "guaranteed" claimed it should be -27!


There's no warranty that a CO count is stable with AVX2 ST unless you test the way you are doing it now 
Hydra is doing a quick check, isn't spending hundreds of hours on it like we do!
Plus it's really really unlikely that you get a such high AVX2 ST load on Core 10.
As said by PJVol earlier in "normal" usage you probably will never notice if any core which is not one of the best isn't stable with AVX2.


----------



## Audioboxer

ManniX-ITA said:


> There's no warranty that a CO count is stable with AVX2 ST unless you test the way you are doing it now
> Hydra is doing a quick check, isn't spending hundreds of hours on it like we do!
> Plus it's really really unlikely that you get a such high AVX2 ST load on Core 10.
> As said by PJVol earlier in "normal" usage you probably will never notice if any core which is not one of the best isn't stable with AVX2.


True, but for me it's not stable unless it can pass everything 

I mean, at default with no PBO or PBO with curve disabled it would pass, so I think it's reasonable to say unless it passes with your curve it isn't truly stable.

But I'd rather not get into big arguments over what stable is or isn't lol. I'll just go by my own desire of having all my cores pass this y-cruncher test!

Unstable cores seem to trip really quickly with it as well, as soon as the first cycle it seems, so it's easy to test.

So far it just seems to be this one core that won't pass with the old settings, so it's not like I'm having to redo my whole curve.


----------



## ManniX-ITA

Audioboxer said:


> But I'd rather not get into big arguments over what stable is or isn't lol. I'll just go by my own desire of having all my cores pass this y-cruncher test!


Me too, it'd bother me knowing that something could have crashed or lagged cause it's not 100% stable in AVX2, even if unlikely


----------



## Audioboxer

ManniX-ITA said:


> Me too, it'd bother me knowing that something could have crashed or lagged cause it's not 100% stable in AVX2, even if unlikely


It seems I've managed to squeeze it back up to -23 anyway, so a drop of 3 points is barely anything. -25 rebooted, -24 rebooted and then I dropped to -22 skipping -23. But gone back up to it and it's passing multiple iterations so far.

What should be next? I've done hours and hours of the standard P95 setup. 720-720?


----------



## ManniX-ITA

Audioboxer said:


> What should be next? I've done hours and hours of the standard P95 setup. 720-720?


A round of 6-10m 720-720 is a good idea.
Then if you feel masochistic and didn't already a full FFT round with P95 AVX2.


----------



## Audioboxer

ManniX-ITA said:


> A round of 6-10m 720-720 is a good idea.
> Then if you feel masochistic and didn't already a full FFT round with P95 AVX2.


Up next, AGESA 1.2.0.6 changes the way the curve works, again


----------



## dk_mic

Audioboxer said:


> It seems I've managed to squeeze it back up to -23 anyway, so a drop of 3 points is barely anything. -25 rebooted, -24 rebooted and then I dropped to -22 skipping -23. But gone back up to it and it's passing multiple iterations so far.
> 
> What should be next? I've done hours and hours of the standard P95 setup. 720-720?


My previous 5950x would fail very soon at stock using 12800-13440 on SSE, so that's what i was also using when running core cycler with prime.
But try to modify the powershell script as Manni pointed out and get each core a couple of times through just N32 or N64.
Well my curve wasnt tested with AVX2 before, and I didn't see any instabilities at all, but damn this test is hard.
Its just annoying as it rarely shows errors in the logs, instead its just reboots / whea 18 and you have to use the apic id in the eventviewer.


Audioboxer said:


> Up next, AGESA 1.2.0.6 changes the way the curve works, again


You bet, it's already totally different from 1.2.0.3 and 1.2.0.5

Makes me wonder if one should just set -5 or -10 and call it a day.

Also, I wonder how much powerlimits can effect the curve and power plans, especially the energy saving slider. AUTO OC also has an effect as it changes VIDs i think

N64 seems way harder 😳


----------



## PJVol

dk_mic said:


> Its just annoying as it rarely shows errors in the logs, instead its just reboots / whea 18 and you have to use the apic id in the eventviewer.


I tend to partially agree with @lafonte here, regarding the transient loads. I've posted here my thoughts about OCCT bencmark, where i figured out what makes it fail sometimes.

To put it simple, Zen2/3 has some kind of internal limiter for the intensive SIMD workloads, clock-gating the FPU critical pathways based on EDC. And sometimes in OCCT bench, after switching ST>MT it "forgot" to turn on that gating which leads to ~100-150mhz higher clocks in a SSE/AVX MT benches, and as a result failed to pass it.
That is 100% reproducible in a way that if EDC manager has "stuck" benchmark is always failed.

I think something similar happenes when the CPU crashes in a N32/64 bench, as if it doesn't keep up with a rapidly changing workload type by gating the clocks (or may be power) accordingly.

What I dont agree with him, is cause of the instability he assumed. I'm pretty sure, the CO itself is just the result of the wrong target frequency set for a certain workload, and it is a fw/hw bug without any doubt.


----------



## domdtxdissar

Testing hydra diagnostic on my lucky sample 5950x, with new improved cooling 
(have 3x bigboy rads, 2xpumps and a TechN block now)


http://imgur.com/a/6ovsyya

Managed 730 GFlops in Linpack Xtreme in the end, which i think is close to the max for my current setup/cpu 








Some profiler bench numbers:


----------



## Lobstar

Taraquin said:


> My advice: Find highest stable speed first. Try 3800 with all timings at auto, if you can`t boot, get loads of WHEA 19 or get random reboots drop to 3733, if that fails try 3666. 3800 or 3733 might work. Keep ProcODT, voltages at auto, your current settings are really good for auto-values. Once you have found your highest stable speed, set ram voltage to 1.45V and try 1 by one timing:
> CL 18, then CL16, if it works try
> RCDRD\RW 22, then 21 and so on
> Keep RP same as RCDRD
> RAS= RCDRD+RP
> RC= RAS+RP
> 
> Next up, most important timings:
> RRDS\L and FAW 6\8\24, if it works try 5\7\20, if that works try 4\6\16
> WR=CL and RTP half of WR
> RFC: Try 640, if it works try 608, if that works lower by 32, if it fails try 32 higher
> RDWR: 12, try 11 if 12 works, and 10 if that works
> WRRD: 3
> 
> Less important:
> WTRS\L=4\12, work your way down to 3\8 if you can, lower one by one
> SCL`s= try 4
> 
> Expected results depending on binning:
> Best case:
> 3800 16-19-19-19-38-57 rrd\faw:4\4\16 rfc 576
> 
> Worst case:
> 3600 18-22-22-22-44-66 rrd\faw 6\8\24 rfc 704
> 
> It will be way faster than what you currently run no matter what


Thank you very much for your thoughtful response. I'll play with it over the week and hopefully improve


----------



## lafonte

PJVol said:


> What I dont agree with him, is cause of the instability he assumed. I'm pretty sure, the CO itself is just the result of the wrong target frequency set for a certain workload, and it is a fw/hw bug without any doubt


It may be, unfortunately all this software is closed source and we can just observe and try to understand what's happening. I did observe different test with profiling and monitoring software and definitely y-cruncher n64 is not just a loop but more a workload subdivided in phases. At the same time the tuning of the co is extremely difficult and basically it's almost impossible find a co and be sure that's stable at 100%
There are questions that are very difficult if not impossible to answer like will this co be stable at all operational temperature? Is this test the worst case scenario? Will this test fail if I continue to run it for more time? Is the voltage frequency curve stable at all the possible voltage/frequency point? And so on... And apparently since there are reports of RMA of CPU that require a positive offset to run this kind of tests at stock probably also at AMD they still figuring out.


----------



## Audioboxer

Just about to finish 3 full iterations of every core being tested at once and I'll leave it overnight.

Seems like I've only had to change 2 of my curve values and not by a lot to be stable under this test. I guess it raises the debate are you truly stable unless you can pass this? There is likely a LOT of curves out there that have done 24+ hours of Corecycler P95, but maybe one or two of the curves will fail at this. Guess it opens the can of worms of "what is a realistic scenario?" seeing as this kind of load likely won't fall on your weaker cores normally.

Still, I'm not happy until anything can be passed, so glad I caught 2 cores needing tweaked and we'll see if there is any others that drop by tomorrow. It does seem like this test catches errors quite quickly.

Who says OCing memory is the dark arts? The curve optimiser holds its own


----------



## TMavica

Need some help please. Anyway to get rid of error #4? even i raised trfc to 240, still came out when at cycles 1x.
Error 4 = PCB Crash ! Too strong RTT values, too high CAD_BUS ClkDrvStr ,wrong tCKE or too high VDIMM

PS: Vdimm 1.568 in hwinfo


----------



## KedarWolf

TMavica said:


> Need some help please. Anyway to get rid of error #4? even i raised trfc to 240, still came out when at cycles 1x.
> Error 4 = PCB Crash ! Too strong RTT values, too high CAD_BUS ClkDrvStr ,wrong tCKE or too high VDIMM
> 
> View attachment 2549862


Your VDIMM is really low. Try between 1.45 and 1.5. Make the VTT's half of the VDIMM. Also, lower VSOC to between 1.1 and 1.15, maybe 1.2.

Oh, I read VSOC wrong, try 1.15.


----------



## TMavica

KedarWolf said:


> Your VDIMM is really low. Try between 1.45 and 1.5. Make the VTT's half of the VDIMM. Also, lower VSOC to between 1.1 and 1.15, maybe 1.2.
> 
> Oh, I read VSOC wrong, try 1.15.


my vdimm is 1.57, hwinfo show 1.568,zentiming read error only .u mean raise vsoc to 1.15?i tried before, same error 4 came out


----------



## The_King

Hi guys, Got some great info from this thread. Decided to signup and post some results I recently got with my 1700X and B450M Mortar MAX and some Crucial Rev. E


----------



## KedarWolf

TMavica said:


> my vdimm is 1.57, hwinfo show 1.568,zentiming read error only .u mean raise vsoc to 1.15?i tried before, same error 4 came out


More VDIMM isn't always better, try like 1.54v.


----------



## TMavica

KedarWolf said:


> More VDIMM isn't always better, try like 1.54v.


it cant post


----------



## Audioboxer

TMavica said:


> Need some help please. Anyway to get rid of error #4? even i raised trfc to 240, still came out when at cycles 1x.
> Error 4 = PCB Crash ! Too strong RTT values, too high CAD_BUS ClkDrvStr ,wrong tCKE or too high VDIMM
> 
> PS: Vdimm 1.568 in hwinfo
> 
> View attachment 2549862


Try RttNom 6. Also what are your memory temps?


----------



## TMavica

Audioboxer said:


> Try RttNom 6. Also what are your memory temps?


temp is below 50


----------



## Audioboxer

Audioboxer said:


> View attachment 2549834
> 
> 
> Just about to finish 3 full iterations of every core being tested at once and I'll leave it overnight.
> 
> Seems like I've only had to change 2 of my curve values and not by a lot to be stable under this test. I guess it raises the debate are you truly stable unless you can pass this? There is likely a LOT of curves out there that have done 24+ hours of Corecycler P95, but maybe one or two of the curves will fail at this. Guess it opens the can of worms of "what is a realistic scenario?" seeing as this kind of load likely won't fall on your weaker cores normally.
> 
> Still, I'm not happy until anything can be passed, so glad I caught 2 cores needing tweaked and we'll see if there is any others that drop by tomorrow. It does seem like this test catches errors quite quickly.
> 
> Who says OCing memory is the dark arts? The curve optimiser holds its own












Core 10 popped up again some point during the night. So -23 is too much. Back to -22 to try it longer term!



TMavica said:


> temp is below 50


Over 42 degrees can start to cause some issues with b-die, more so with tRFC. Try turning the RGB off if you're using it just now to save a few degrees until you figure out what is unstable.


----------



## Taraquin

The_King said:


> Hi guys, Got some great info from this thread. Decided to signup and post some results I recently got with my 1700X and B450M Mortar MAX and some Crucial Rev. E
> View attachment 2549864
> View attachment 2549865


Very good frequency for a ryzen first gen, but you should be able to tighten up timings a lot!
Try 16-20-20-20 
ras 40 
rc 60
rrds\l\faw 4\6\16, safe 6\8\24
wtrs\l 4\12
wr\rtp
rfc 600, maybe 560 might work
scls at 4

You only use one stick? Try 2, it`s much faster.


----------



## TMavica

Audioboxer said:


> View attachment 2549886
> 
> 
> Core 10 popped up again some point during the night. So -23 is too much. Back to -22 to try it longer term!
> 
> 
> 
> Over 42 degrees can start to cause some issues with b-die, more so with tRFC. Try turning the RGB off if you're using it just now to save a few degrees until you figure out what is unstable.


I did tm5 in safe mode, because normal mode always cause tm5 timeout randomly. Rttnom 6 give me error 4 more early. Now I changed ProcODT to 36.9, error 4 came out in cycles 22 then error 0. Now i going to raise more trfc and see what happen


----------



## Audioboxer

TMavica said:


> I did tm5 in safe mode, because normal mode always cause tm5 timeout randomly. I changed ProcODT to 36.9, error 4 came out in cycles 22 then error 0. Now i going to raise more trfc and see what happen


Is your CPU overclocked? CPU instability can cause those timeouts. Background apps in normal Windows might be causing CPU boosts at random which could be triggering core crashes.

ProcODT is unlikely to be the cause, chances are you can go as low as 28.2 and tPHYRDL will still train at 26/26.


----------



## The_King

Taraquin said:


> Very good frequency for a ryzen first gen, but you should be able to tighten up timings a lot!
> Try 16-20-20-20
> ras 40
> rc 60
> rrds\l\faw 4\6\16, safe 6\8\24
> wtrs\l 4\12
> wr\rtp
> rfc 600, maybe 560 might work
> scls at 4
> 
> You only use one stick? Try 2, it`s much faster.


I ordered 3 sticks of RAM from Amazon they only delivered 1. I am still waiting for the other two. Will try to get at least 3800 with two sticks if possible.
I was able to boot into BIOS with 3933 so close to 4000. My timings with 3800 was better than the 3866 but its not 100% stable.It may need 1.5V or more.


----------



## TMavica

Audioboxer said:


> Is your CPU overclocked? CPU instability can cause those timeouts. Background apps in normal Windows might be causing CPU boosts at random which could be triggering core crashes.
> 
> ProcODT is unlikely to be the cause, chances are you can go as low as 28.2 and tPHYRDL will still train at 26/26.


Yes, with CO curve, but it tested with corecycle 20 cycle without error. Now running tm5 in safe mode, and raised trfc and see whats going. If passed the test, then try lower the ProcODT to 28.2


----------



## Taraquin

The_King said:


> I ordered 3 sticks of RAM from Amazon they only delivered 1. I am still waiting for the other two. Will try to get at least 3800 with two sticks if possible.
> I was able to boot into BIOS with 3933 so close to 4000. My timings with 3800 was better than the 3866 but its not 100% stable.It may need 1.5V or more.
> View attachment 2549888
> View attachment 2549889


3800 sounds like a better deal then  Try 40 ras, 59 rc, 4\6\16 rrds\l\faw, 16\8 wr\rtp, wtrs\l 4\12, 600 rfc, rdrdscl\wrwrscl 4, that shold improve performance a lot


----------



## Subut

Veii said:


> I'm not sure what i helped, but thanks belongs to the whole community here


Modest person you are  but yes many thanks to the community.



Veii said:


> BurstChop of half tBL = (8/2) == 4


What's this burstchop business.



Veii said:


> But "just doing it" without a foundation


I've been 'just doing it' you got me there.



Veii said:


> You need a stable foundation, and then maximize throughput


Honestly, all I've got is persistence and luck, going in blindly is what I've been doing most of the time. I do want to know more but it feels overwhelming . Please do guide me on this stable foundation. What I really want is something not on the edge of stability but rather a solid foundation all along but by going blindly and seeing what sticks is no way to get a solid foundation.



Veii said:


> Ahh i want to write more to this topic


Please do  it's been a blessing tbh


Edit: This is where I'm standing atm. Got back up to 4sticks of 8gb viper steels. Gone back down to 3800 since stabilizing 4000 was a nightmare (although I got into windows with ease at up to 2067FCLK). Anyway, any recommendations on how to get rid of that one pesky error? Thanks in advance.


----------



## Audioboxer

Subut said:


> Modest person you are  but yes many thanks to the community.
> 
> 
> What's this burstchop business.
> 
> 
> I've been 'just doing it' you got me there.
> 
> 
> Honestly, all I've got is persistence and luck, going in blindly is what I've been doing most of the time. I do want to know more but it feels overwhelming most of the time. Please do guide me on this stable foundation. What I really want is something not on the edge of stability but rather a solid foundation all along but by going blindly and seeing what sticks is no way to get a solid foundation.
> 
> 
> Please do  it's been a blessing tbh
> 
> 
> Edit: This is where I'm standing atm. Got back up to 4sticks of 8gb viper steels. Gone back down to 3800 since stabilizing 4000 was a nightmare (although I got into windows with ease at up to 2067FCLK). Anyway, any recommendations on how to get rid of that one pesky error? Thanks in advance.
> View attachment 2549911


CkeDrvStr to 24.


----------



## blodflekk

Just last night I updated to bios 4004 on dark hero. core vid is now only 1.41. On beta bios 4002 I was getting 1.469.


----------



## KedarWolf

blodflekk said:


> Just last night I updated to bios 4004 on dark hero. core vid is now only 1.41. On beta bios 4002 I was getting 1.469.


I read on the newer AGESAs having EDC above 140 limits your VID.


----------



## gameinn

If I have 3600C16 XMP stable on a 5950X what's the chances of being able to run 3600C14?


----------



## SaarN

gameinn said:


> If I have 3600C16 XMP stable on a 5950X what's the chances of being able to run 3600C14?


I've yet to see a Zen2\3 cpu that fails to run ram at 3600MHz


----------



## blodflekk

KedarWolf said:


> I read on the newer AGESAs having EDC above 140 limits your VID.


Yes, I'm running motherboard limits. However my point was on previous beta I wasn't vid limited despite being same agesa 1.2.0.6c


----------



## TMavica

Whats should i do next? any recommendation? if trfc below 240, error #4 / #5 
Vdimm: 1.57


----------



## Subut

Audioboxer said:


> CkeDrvStr to 24.


1 pesky error turns into 3 pesky errors with this


----------



## The_King

Update on my Progress towards DDR4000 on my First Gen RYZEN. I had to reduce MEM VTT from 0.7500V to 0.7000V and was able to boot into Windows.
This RAM is different from my previous post. This is C9BLM and the previous post was with C9BJZ


----------



## Audioboxer

TMavica said:


> Whats should i do next? any recommendation? if trfc below 240, error #4 / #5
> Vdimm: 1.57
> 
> 
> View attachment 2549993
> 
> 
> 
> View attachment 2549992


Use RttNom. Don't run disabled at 3800 on DR.


----------



## TMavica

Audioboxer said:


> Use RttNom. Don't run disabled at 3800 on DR.


i tried different combination, included 733 still the same


----------



## Audioboxer

Here is something interesting, Core 5 was reduced to -1 because of Prime95 errors with the standard Corecycler settings on AGESA 1.2.0.5, here it is after 12 hours with ycruncher Kagari.

Will go back and test P95 now, but in advance I wonder is it possible for a core to fail due to other cores being unstable? Ycruncher has caused me to need to reduce two of my CCD2 cores....

Or what is more likely, this just proves you need to run P95 tests AND ycruncher tests. As in, I wouldn't be surprised if P95 fails again on core 5.

*edit *-










Hmm, going to be very interesting to look into this, Core 5 now holding up at -10. Either I've discovered a weakness of ycruncher with this single core, or changing other parts of this curve has somehow helped Core 5 be more stable??? Moving back to P95 testing just now, it often failed quite quickly in P95 with values above -5.


----------



## lafonte

TMavica said:


> Whats should i do next? any recommendation? if trfc below 240, error #4 / #5
> Vdimm: 1.57
> 
> 
> View attachment 2549993
> 
> 
> 
> View attachment 2549992


Trrdl 6 (at times 4 cause performance regression)
Twtrl 9 (at times 8 cause performance regression with Twtrs 3)
Trp 13 may work
Twrrd 2 may work


----------



## Audioboxer

Audioboxer said:


> View attachment 2550000
> 
> 
> Here is something interesting, Core 5 was reduced to -1 because of Prime95 errors with the standard Corecycler settings on AGESA 1.2.0.5, here it is after 12 hours with ycruncher Kagari.
> 
> Will go back and test P95 now, but in advance I wonder is it possible for a core to fail due to other cores being unstable? Ycruncher has caused me to need to reduce two of my CCD2 cores....
> 
> Or what is more likely, this just proves you need to run P95 tests AND ycruncher tests. As in, I wouldn't be surprised if P95 fails again on core 5.
> 
> *edit *-
> 
> View attachment 2550002
> 
> 
> Hmm, going to be very interesting to look into this, Core 5 now holding up at -10. Either I've discovered a weakness of ycruncher with this single core, or changing other parts of this curve has somehow helped Core 5 be more stable??? Moving back to P95 testing just now, it often failed quite quickly in P95 with values above -5.












Failed in a minute with P95 720-720.

So that's pretty clear proof to me y-cruncher will not catch everything. Actually a bit shocked at that!


----------



## blodflekk

Audioboxer said:


> View attachment 2550003
> 
> 
> Failed in a minute with P95 720-720.
> 
> So that's pretty clear proof to me y-cruncher will not catch everything. Actually a bit shocked at that!


I'm finding the same thing. I'm trying to work on a good method to find perfect CO. I've tried various settings in y-cruncher seems easy to pass, I've tried single core stressing in OCCT seems easy to pass, even used affinty on linpack to set to one core and still passed that easily. On'y thing to give me grief is p95, which I still haven't settled on the ideal settings for reasonable test time.


----------



## Audioboxer

blodflekk said:


> I'm finding the same thing. I'm trying to work on a good method to find perfect CO. I've tried various settings in y-cruncher seems easy to pass, I've tried single core stressing in OCCT seems easy to pass, even used affinty on linpack to set to one core and still passed that easily. On'y thing to give me grief is p95, which I still haven't settled on the ideal settings for reasonable test time.


Funny, P95 was what I was passing fine, then I discovered the ycruncher method and it nuked two of my weaker cores lol. Just seems like the best answer is use them all.

The above fail is at -10, I'll retest -5 which was what ran for 12+ hours in y-cruncher. After switching to AGESA 1.2.0.5 -5 is what failed for me with P95, but IIRC it was like 3~4 hours in. Ended up having to be dropped to -1 after -2 failed like 8 hours in. But I was OK with this as it is well known AGESA 1.2.0.5 changed how the curve/boosting works, so -5 was seemingly only stable on 1.2.0.3c.

edit - Would you look at that!










-5 crashes 3 minutes in with 720-720, but it lasted 12+ hours with y-cruncher!

That's pretty mental if anyone thought y-cruncher was going to replace P95


----------



## Bloax

The most important metric isn't whether it's stable in y-cruncher or prime95, but whether it's perfectly stable in what you're actually going to be running for many hours.

They're great tools for testing (different flavours of) extreme load conditions, but every Overclock is either Purpose-Tailored (perfectly stable for X, crashes in Y) or A Compromise (not as fast, but doesn't crash in either X or Y).

It's good to have a fallback compromise profile, but it is also important to not forget that if it's perfectly stable for what you actually do - it is only ever your spare wheel in case of a puncture.


----------



## gameinn

SaarN said:


> I've yet to see a Zen2\3 cpu that fails to run ram at 3600MHz


Oh I know 3600 is safe but with how fast that 3600 is I would think it might cause problems or am I wrong? Is like 3600C18 as easy to run as 3600C14?


----------



## Audioboxer

Bloax said:


> The most important metric isn't whether it's stable in y-cruncher or prime95, but whether it's perfectly stable in what you're actually going to be running for many hours.
> 
> They're great tools for testing (different flavours of) extreme load conditions, but every Overclock is either Purpose-Tailored (perfectly stable for X, crashes in Y) or A Compromise (not as fast, but doesn't crash in either X or Y).
> 
> It's good to have a fallback compromise profile, but it is also important to not forget that if it's perfectly stable for what you actually do - it is only ever your spare wheel in case of a puncture.


I don't view it that way because "what you are running daily" can wildly vary and for a PC to be stable it has to be stable under "worst case scenario". You might play 100 games that aren't too heavy on the CPU, or run 100 apps that aren't too heavy on the CPU and then there is something you try 7 months down the line that does things different and you get a reboot/WHEA.

A retail CPU out of the box with no OCing enabled should be running these heavy tests no problem. That's stability. Therefore, an OCed CPU should be held to the same standard a retail box CPU should be. IMO.










-3 crashing after 48 minutes with 720-720, so back down to -1 we go. Experiment over. Quite clear testing should be done with BOTH P95 *and* ycruncher.

Someone more intelligent with me might be able to explain why -5 might last 12 hours with AVX2 but will crash in 3 minutes with SSE.

Core 5 has always been a strange one for me, it's not my best core, 2nd best. The best core is at -16 on CCD 1 lol. Best core 5 ever achieved was -5 on AGESA 1.2.0.3c.


----------



## domdtxdissar

Audioboxer said:


> I don't view it that way because "what you are running daily" can wildly vary and for a PC to be stable it has to be stable under "worst case scenario". You might play 100 games that aren't too heavy on the CPU, or run 100 apps that aren't too heavy on the CPU and then there is something you try 7 months down the line that does things different and you get a reboot/WHEA.


While i 100% understand where your coming from, the drawback is that you leave performance left on the table for "6.99 months" to have stability in that 1 program you use one time each 7 months..

I use different cpu performance-profiles for different apps/programs/games to always run as close as possible at "peak performance" in any given task..
(easy to switch profiles in hydra/CTR without rebooting and/or with PBO2 turner)

It all comes down to point of view i guess


----------



## ManniX-ITA

Audioboxer said:


> -3 crashing after 48 minutes with 720-720, so back down to -1 we go. Experiment over. Quite clear testing should be done with BOTH P95 *and* ycruncher.
> 
> Someone more intelligent with me might be able to explain why -5 might last 12 hours with AVX2 but will crash in 3 minutes with SSE.











CoreCycler - tool for testing Curve Optimizer settings


What's the safe max VCORE a core should see during these tests? e.g. Y Cruncher, P95.




www.overclock.net





When you get weird results, it's likely a Core unstable that you didn't catch yet.
Only y-cruncher is not enough.
When you make big changes, sometimes also small, you need to test again everything.
AVX will run at lower clocks, SSE at higher. AVX2 lower than both.
They also use different die parts and depends on which test is going to run, integer or float.
That's why testing with small FFTs ranges and y-c N32 Kagari is convenient.
You can run them in cycles and only run the full FFTs at the end.


----------



## Audioboxer

domdtxdissar said:


> While i 100% understand where your coming from, the drawback is that you leave performance left on the table for "6.99 months" to have stability in that 1 program you use one time each 7 months..
> 
> I use different cpu performance-profiles for different apps/programs/games to always run as close as possible at "peak performance" in any given task..
> (easy to switch profiles in hydra/CTR without rebooting and/or with PBO2 turner)
> 
> It all comes down to point of view i guess


Yeah, I know it does, I've watched Core 5 boost to 5025 at -1 but even just going to -5 and it's boosting to 5075.

Given I don't really competitively OC I guess my performance comes down to something like gaming, and quite clearly -1 on the curve instead of -5 will make pretty much 0 difference gaming on a 5950x.

So I'll take the "passes every stability test" curve lol.

Hydra I can understand more because of the ease of switching profiles and what not. I'm just looking for a set it and forget it. One reason I'm pissed AMD is making me load Ryzen Master every fresh boot due to the voltage cap bug.


----------



## PJVol

Audioboxer said:


> Core 5 has always been a strange one for me, it's not my best core, 2nd best. The best core is at -16 on CCD 1 lol. Best core 5 ever achieved was -5 on AGESA 1.2.0.3c.


Maybe we should bear in mind the following (at least, how i see it):
1) the counts you set in CO are not the absolute values, rather you adjusting +/- those fused on ATE.
2) hardly anyone know for certain the exact type of workloads ATE utilized in "Final Test" and how different it might be from what you currently are testing.
3) so called "V/F curve" your CPU currently rely upon while boosting, may change from boot to boot, depending on starting temperature (mostly compensated on BTC) and infrastructure limits (EDC and Vmax).


----------



## Luggage

PJVol said:


> Maybe we should bear in mind the following (at least, how i see it):
> 1) the counts you set in CO are not the absolute values, rather you adjusting +/- those fused on ATE.
> 2) hardly anyone know for certain the exact type of workloads ATE utilized in "Final Test" and how different it might be from what you currently are testing.
> 3) so called "V/F curve" your CPU currently rely upon while boosting, may change from boot to boot, depending on starting temperature (mostly compensated on BTC) and infrastructure limits (EDC and Vmax).


3) Can you expand on this? I guess lower boot temp is “better”? In my case with rad outside and pc inside I could get a different result running cooling on full tilt idle to cool things down and do a reboot compared to original boot with everything at room temp? ( and in most normal cases a reboot after a long hot gaming session will result in different result than their original “cold boot” ) ?


----------



## Audioboxer

How does the positive VCORE offset function? It's not something I've ever used before, but out of interest with testing it, it seems to enable Core 5 to remain stable longer with a higher curve value.

But would adding a positive VCORE offset not effectively null a curve? In other words, how does a positive VCORE offset impact a curve? Do they work against each other?


----------



## Luggage

Audioboxer said:


> How does the positive VCORE offset function? It's not something I've ever used before, but out of interest with testing it, it seems to enable Core 5 to remain stable longer with a higher curve value.
> 
> But would adding a positive VCORE offset not effectively null a curve? In other words, how does a positive VCORE offset impact a curve? Do they work against each other?


The co is not static like the offset. The co lowers the vcore more for a given fhz at low speeds.


----------



## ManniX-ITA

Luggage said:


> 3) Can you expand on this? I guess lower boot temp is “better”? In my case with rad outside and pc inside I could get a different result running cooling on full tilt idle to cool things down and do a reboot compared to original boot with everything at room temp? ( and in most normal cases a reboot after a long hot gaming session will result in different result than their original “cold boot” ) ?


Yes it could but AMD progressively reduced the impact of it while developing AGESA.
Now each Core is more dynamically calibrated during usage. Settled while booting the OS.
In the early days with my 3800X a normal reboot would cause my two best cores to be swapped very frequently as the CPPC tag value was changed as well.
Very confusing...



Audioboxer said:


> How does the positive VCORE offset function? It's not something I've ever used before, but out of interest with testing it, it seems to enable Core 5 to remain stable longer with a higher curve value.
> 
> But would adding a positive VCORE offset not effectively null a curve? In other words, how does a positive VCORE offset impact a curve? Do they work against each other?


Yes & no.
The offset will raise the vCore by the margin you set but then what you set will be pushed on the Core VIDs differently.
Almost all when it's all-core usage and just a fraction on single core.
Which means that if it's not too much can get you stability without loss of clock or performances.
Too much and it will hit negatively the ST performances.


----------



## Audioboxer

Luggage said:


> The co is not static like the offset. The co lowers the vcore more for a given fhz at low speeds.


So the VCORE offset is enabled at all times at all frequencies?


----------



## mike7877

Audioboxer said:


> View attachment 2550002
> 
> 
> Hmm, going to be very interesting to look into this, Core 5 now holding up at -10. Either I've discovered a weakness of ycruncher with this single core, or changing other parts of this curve has somehow helped Core 5 be more stable??? Moving back to P95 testing just now, it often failed quite quickly in P95 with values above -5.


I think I have the answer and solution for you - it came to me while tweaking my 9600K to infinity. I think I might make a thread about it in the future, but for now I'll go over things so you can find the lowest possible voltage you can give your CPU at your chosen overclock for equal to stock stability and error free operation. You probably already have a decent starting point, and it's not too different from what you're already doing so don't think it's a tonne of work and just skip over my post which I spent a lot of time on 

First, to answer the question about your problematic core - if the cores physically adjacent to it are being extremely heavily loaded, Core 5 could end up getting less voltage than usual, getting hotter than usual, or (most likely) a nasty combination of both. Very fortunately, what's happening isn't something you need to be concerned with. Only if you routinely assigned heavy AVX workloads to specific cores while using your computer would it be a problem (and even then, you'd almost have to be trying to screw things up by sending work to just physically adjacent cores. Fortunately load balancing is done by operating systems, and you're not maliciously assigning work.

Moving on to the method: (interjection: I tried making general directions, but they were hard to follow with the required associated commentary, so I'm going to use my 9600K as an example for my ease of writing and your ease of understanding.

First thing you need to do is find out your weakest cores using Prime 95. This doesn't have to be at your chosen overclock speed, but the closer you can get to it at the beginning simplifies things later. For a 6 core chip you're going to use your 2 weakest cores, (3 with an 8 core, 4/12,16).

To find the weakest cores in my 9600K I had to set it to 4.8GHz on all cores, and LOWER the voltage to below 1.2. Any higher frequency or voltage and I ran into thermal throttling after just a few seconds. So it's impossible to test for stability! Not quite!!

What you do, armed with the knowledge of your weakest cores: you pick a reasonable voltage for your overclock and run Prime 95 (small FFT) on just them, gradually increasing voltage until you are error free for at least 15 minutes. I chose 5200MHz and 1.32V for my 9600K. Immediately after opening Prime 95 you need use Task Manager to set Prime 95's (core) Affinity to your weakest cores (Task Manager (tab): Details > right click Prime 95 > Set affinity > _Uncheck all boxes but the ones for your weakest cores along with their virtual multithreading cores too_). This ensures that when you make your 2 or 3 or 4 or 5 "Workers", they run on the correct cores. So at 1.32V my 9600K booted at 5200MHz, but the cores I was checking errored out almost immediately. So I restarted, went into the BIOS, Increased to 1.33V, and repeated the above. Errors! 1.34V No Errors!!! You increase a further two 0.01V steps - 1.36V (this is specific to this method, you'll see why very shortly).
Now that you're at *your*1.36V, what you want to do is get a program which can show your maximum, average, and minimum sensor readings (I like HWiNFO64 - it's free and good). Reason being, you want to find out how much power your CPU takes during your heaviest "real world" workloads. Transcode a video without GPU acceleration and record the value in the maximum column for instantaneous CPU package power consumption, do the same after a game or two you know to be CPU intensive. Compile something, scan for viruses, open a large project, update windows. Do ANYTHING and everything but do NOT run a synthetic benchmark or a stress test of any kind. If you have graphics benchmarks designed to measure GPU performance, sure check the CPU power peak after, but absolutely do not do any included tests which are specifically designed to stress out your CPU. The reason being, it will only push up your final "required voltage for a stable overclock" which is what we're aiming to do the opposite of.

OK, we're getting close to your perfect overclock!
So, two threads of Prime 95 on my 9600K @ 5.2GHz/1.36V?
80 watts.
Yes, 80 watts! This isn't bad news though, because the peak power consumptions I recorded running all my CPU intensive applications were between 90 and 110 watts.

So what do you do with this information to find the most perfect VCore voltage for your use case?
You run 2 threads Prime 95/small FFT on Cores 1 and 3 of your 9600K, observing power consumption rising to 80 watts. Next, you open and start a few instances of freeware program called "CPU Burn-in", just enough to raise CPU package power consumption to ~10% greater than (in this case) 110 watts.
120 watts!
Then you wait up to 36 hours for an error. You'll probably get one, but if you don't, you can go down to 1.35V, and if there's no error there, you can leave it at 1.36V. If there is, increase to 1.37V.
So yeah, if you get an error at 1.36V, you increase to 1.37. If you get no error there, you increase VCore again to 1.38V and leave it there. You keep increasing the voltage until you're stable or the voltage becomes too great and for peace of mind you subtract 50-100MHz from your overclock instead and begin subtracting volts until instability. Then you move it up a bit, set it, and forget it! (This last part like most other methods).

My 9600K ended up needing 1.39V. I could probably get away with 1.385, but whatever. Think you'll try it?


----------



## Taraquin

As for curve optimizer: What worked for me was running 3 rounds of corecycler, it found 1 unstable core at - 30, seemed to work at - 29. After running 3 months I had 1 sudden reboot at high or light loads, used event viewer and foynd the core responsible. End result was core 0: -27 1:-29 and rest -30. On another setup I built after 3 runs of corcycler he still got reboots at low loads and we had to adjust more. In my experience corecycler finds 90% of the issues right away, but event viewer shows you the rest after a few weeks/months.


----------



## TMavica

Hi everyone. Whats ur digi vrm setting of dram vsoc in bios mostly? They affect the memory overclock much?


----------



## Gegu

Can someone explain to me what the Anta777Extreme errors 0 and 2 are related to (what parameters)?


----------



## Luggage

Taraquin said:


> As for curve optimizer: What worked for me was running 3 rounds of corecycler, it found 1 unstable core at - 30, seemed to work at - 29. After running 3 months I had 1 sudden reboot at high or light loads, used event viewer and foynd the core responsible. End result was core 0: -27 1:-29 and rest -30. On another setup I built after 3 runs of corcycler he still got reboots at low loads and we had to adjust more. In my experience corecycler finds 90% of the issues right away, but event viewer shows you the rest after a few weeks/months.


Do you want to be crash free or error free?
I can bench r23 and yc benchmark at -30 all cores.
Error free seems to be between -9 to -29 but I’m still testing after finding these last settings.


----------



## Taraquin

Luggage said:


> Do you want to be crash free or error free?
> I can bench r23 and yc benchmark at -30 all cores.
> Error free seems to be between -9 to -29 but I’m still testing after finding these last settings.


I never get errors in y-cruncher etc, just rare reboots at idle/very low loads. Only corecycler has reported errors. Depends on where the instability is, corecycler finds mine at high loads. What errors do you get in YC etc?


----------



## Luggage

PJVol said:


> Thanks for clear it up )
> My mb limits are 1000/500/540. They're the maximum values allowed to set as well.
> 
> =================
> BTW someone check pls the updated PBO2 tuner
> (removed user settings, since now CO counts should read directly)
> 
> 
> 
> 
> 
> Debug.7z
> 
> 
> 
> 
> 
> 
> 
> drive.google.com


late to the party but max boost dont seem to stick for me.


http://imgur.com/a/dIAyLl1


----------



## TMavica

lafonte said:


> Trrdl 6 (at times 4 cause performance regression)
> Twtrl 9 (at times 8 cause performance regression with Twtrs 3)
> Trp 13 may work
> Twrrd 2 may work


Look like some value cause error 4 , ever tried orginal config 14-15-15-30, error 4 still came out, trfc already set to 256, dont want to set higher, i will try ur advice to see. With agesa 1.2.0.5, there is no such issue, after update to 1.2.0.6b, error 4 came out.


----------



## Luggage

Taraquin said:


> I never get errors in y-cruncher etc, just rare reboots at idle/very low loads. Only corecycler has reported errors. Depends on where the instability is, corecycler finds mine at high loads. What errors do you get in YC etc?


Never get reboots or crashes.
Though this was good a goof curve for a long time, ran corecycler default over night etc.



http://imgur.com/wMIgwqA


Got error in yc once or twice and started looking at vsoc...



http://imgur.com/a/LUbAHQI


But in the end with new settings for corecycler (720-720, yc kagari ) ended up at the same vsoc but lower curve values.



http://imgur.com/a/ogI09yn


----------



## Luggage

mike7877 said:


> I think I have the answer and solution for you - it came to me while tweaking my 9600K to infinity. I think I might make a thread about it in the future, but for now I'll go over things so you can find the lowest possible voltage you can give your CPU at your chosen overclock for equal to stock stability and error free operation. You probably already have a decent starting point, and it's not too different from what you're already doing so don't think it's a tonne of work and just skip over my post which I spent a lot of time on
> 
> First, to answer the question about your problematic core - if the cores physically adjacent to it are being extremely heavily loaded, Core 5 could end up getting less voltage than usual, getting hotter than usual, or (most likely) a nasty combination of both. Very fortunately, what's happening isn't something you need to be concerned with. Only if you routinely assigned heavy AVX workloads to specific cores while using your computer would it be a problem (and even then, you'd almost have to be trying to screw things up by sending work to just physically adjacent cores. Fortunately load balancing is done by operating systems, and you're not maliciously assigning work.
> 
> Moving on to the method: (interjection: I tried making general directions, but they were hard to follow with the required associated commentary, so I'm going to use my 9600K as an example for my ease of writing and your ease of understanding.
> 
> First thing you need to do is find out your weakest cores using Prime 95. This doesn't have to be at your chosen overclock speed, but the closer you can get to it at the beginning simplifies things later. For a 6 core chip you're going to use your 2 weakest cores, (3 with an 8 core, 4/12,16).
> 
> To find the weakest cores in my 9600K I had to set it to 4.8GHz on all cores, and LOWER the voltage to below 1.2. Any higher frequency or voltage and I ran into thermal throttling after just a few seconds. So it's impossible to test for stability! Not quite!!
> 
> What you do, armed with the knowledge of your weakest cores: you pick a reasonable voltage for your overclock and run Prime 95 (small FFT) on just them, gradually increasing voltage until you are error free for at least 15 minutes. I chose 5200MHz and 1.32V for my 9600K. Immediately after opening Prime 95 you need use Task Manager to set Prime 95's (core) Affinity to your weakest cores (Task Manager (tab): Details > right click Prime 95 > Set affinity > _Uncheck all boxes but the ones for your weakest cores along with their virtual multithreading cores too_). This ensures that when you make your 2 or 3 or 4 or 5 "Workers", they run on the correct cores. So at 1.32V my 9600K booted at 5200MHz, but the cores I was checking errored out almost immediately. So I restarted, went into the BIOS, Increased to 1.33V, and repeated the above. Errors! 1.34V No Errors!!! You increase a further two 0.01V steps - 1.36V (this is specific to this method, you'll see why very shortly).
> Now that you're at *your*1.36V, what you want to do is get a program which can show your maximum, average, and minimum sensor readings (I like HWiNFO64 - it's free and good). Reason being, you want to find out how much power your CPU takes during your heaviest "real world" workloads. Transcode a video without GPU acceleration and record the value in the maximum column for instantaneous CPU package power consumption, do the same after a game or two you know to be CPU intensive. Compile something, scan for viruses, open a large project, update windows. Do ANYTHING and everything but do NOT run a synthetic benchmark or a stress test of any kind. If you have graphics benchmarks designed to measure GPU performance, sure check the CPU power peak after, but absolutely do not do any included tests which are specifically designed to stress out your CPU. The reason being, it will only push up your final "required voltage for a stable overclock" which is what we're aiming to do the opposite of.
> 
> OK, we're getting close to your perfect overclock!
> So, two threads of Prime 95 on my 9600K @ 5.2GHz/1.36V?
> 80 watts.
> Yes, 80 watts! This isn't bad news though, because the peak power consumptions I recorded running all my CPU intensive applications were between 90 and 110 watts.
> 
> So what do you do with this information to find the most perfect VCore voltage for your use case?
> You run 2 threads Prime 95/small FFT on Cores 1 and 3 of your 9600K, observing power consumption rising to 80 watts. Next, you open and start a few instances of freeware program called "CPU Burn-in", just enough to raise CPU package power consumption to ~10% greater than (in this case) 110 watts.
> 120 watts!
> Then you wait up to 36 hours for an error. You'll probably get one, but if you don't, you can go down to 1.35V, and if there's no error there, you can leave it at 1.36V. If there is, increase to 1.37V.
> So yeah, if you get an error at 1.36V, you increase to 1.37. If you get no error there, you increase VCore again to 1.38V and leave it there. You keep increasing the voltage until you're stable or the voltage becomes too great and for peace of mind you subtract 50-100MHz from your overclock instead and begin subtracting volts until instability. Then you move it up a bit, set it, and forget it! (This last part like most other methods).
> 
> My 9600K ended up needing 1.39V. I could probably get away with 1.385, but whatever. Think you'll try it?


Ryzen dynamic boost, vcore and core allocation (PBO) is very different than how intel works though, it's more like GPU OC for 6-8-12-16 GPUs/cores but the curves are hidden, temperature bin steps are alluded at and power limits are more like suggestions.


----------



## PJVol

Luggage said:


> late to the party but max boost dont seem to stick for me.


Were you running Hydra at the same time ? It seem to function with OC Mode enabled, where PBO limits are basically ignored.


----------



## Luggage

PJVol said:


> Were you running Hydra at the same time ? It seem to function with OC Mode enabled, where PBO limits are basically ignored.


start tuner - change limit. start hydra - run boost test.

Hmm ok it works without hydra... but doesn't change frequency limit global? or hwinfo doesnt update it's reading?


http://imgur.com/gvUJTPq




http://imgur.com/N4gUwZh


----------



## PJVol

Luggage said:


> but doesn't change frequency limit global?


There are more than one clock limits.


----------



## Luggage

PJVol said:


> There are more than one clock limits.


Yea that's interesting.
If I change max boost override in bios all the limits go down with peak_cclk_freq.
Changing boost limit with tuner only peak_cclk_freq goes down.
I wonder if we can "fool" the fit limits as well with this? Limiting boost to 5000 or 5900 but keeping all the other limits aiming for 5050 (in my case with 5800X)

(and yes hydra ignores/changes everything...)

Edit:
it seems you can... (or i'm fubbing something up...)


http://imgur.com/a/eUpAVPW


----------



## Mach3.2

Luggage said:


> Yea that's interesting.
> If I change max boost override in bios all the limits go down with peak_cclk_freq.
> Changing boost limit with tuner only peak_cclk_freq goes down.
> I wonder if we can "fool" the fit limits as well with this? Limiting boost to 5000 or 5900 but keeping all the other limits aiming for 5050 (in my case with 5800X)
> 
> (and yes hydra ignores/changes everything...)
> 
> Edit:
> it seems you can... (or i'm fubbing something up...)
> 
> 
> http://imgur.com/a/eUpAVPW


Do you or @PJVol have a link for the newer version of Zen PT Monitor? I can only find the pre-alpha version posted by PJVol someone(?) back in October 2021. 🙃


----------



## Luggage

Mach3.2 said:


> Do you or @PJVol have a link for the newer version of Zen PT Monitor? I can only find the pre-alpha version posted by PJVol someone(?) back in October 2021. 🙃











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


This is the limit you can raise to in rm if you leave them on auto What's the point in raising it then, if it will never apply? I mean (if I get it right from your post) your BIOS allowed EDC limit to be manually set to max 220 amps, and that it's way below the actual mb limit? This is the...




www.overclock.net


----------



## Mach3.2

Luggage said:


> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> This is the limit you can raise to in rm if you leave them on auto What's the point in raising it then, if it will never apply? I mean (if I get it right from your post) your BIOS allowed EDC limit to be manually set to max 220 amps, and that it's way below the actual mb limit? This is the...
> 
> 
> 
> 
> www.overclock.net


I saw the newer PBO2 Tuner PJVol posted, but I can't seem to find any recent versions of the Zen power table monitor.

The version I have is pre-alpha, and looked quite different from what you have.


----------



## Luggage

Mach3.2 said:


> I saw the newer PBO2 Tuner PJVol posted, but I can't seem to find any recent versions of the Zen power table monitor.
> 
> The version I have is pre-alpha, and looked quite different from what you have.
> View attachment 2550168


Link from here should be the latest I think.









Making sense of AMD and The Stilt's information...


Chain-Post #3 ~ excuse me TL;DR to above: Everything you read is correct. The Stilt is right, but VMAX is independent of the issue you saw at first & independent of the VID request you saw Frequency Straps are dynamic. They do not align with real effective clock, and depend on CO + cores inside...




www.overclock.net





I hade an conversation with XPEHOPE3 and changed the config to my liking


[QUOTE="XPEHOPE3*"*]If you are interested, you can try ZenPTMonitor.exe configs\config-one-ccd.json for a better layout. File is at the same link. Also you can try setting "h": 42 for optimal height [/QUOTE]


----------



## PJVol

Luggage said:


> I wonder if we can "fool" the fit limits as well with this? Limiting boost to 5000 or 5900 but keeping all the other limits aiming for 5050 (in my case with 5800X)


Not sure i fully understand, what you mean.
These are infrastructure limits, not FIT, which is about keeping voltage threshold to ensure silicon reliability.
Peak_cclk looks like kinda "soft" clock limit, applied after the global one is calculated. So this might be the reason why it doesn't exceed cclk max.


----------



## Mach3.2

Luggage said:


> Link from here should be the latest I think.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Making sense of AMD and The Stilt's information...
> 
> 
> Chain-Post #3 ~ excuse me TL;DR to above: Everything you read is correct. The Stilt is right, but VMAX is independent of the issue you saw at first & independent of the VID request you saw Frequency Straps are dynamic. They do not align with real effective clock, and depend on CO + cores inside...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> I hade an conversation with XPEHOPE3 and changed the config to my liking
> 
> 
> [QUOTE="XPEHOPE3*"*]If you are interested, you can try ZenPTMonitor.exe configs\config-one-ccd.json for a better layout. File is at the same link. Also you can try setting "h": 42 for optimal height


Thanks!


----------



## gameinn

So I was going to try and oc my 3600C16 1.35v B-Die 2x16GB kit (F4-3600C16D-32GTZN). I thought it would be a good idea to get some temperature baselines from pure XMP.

When playing Elden Ring (not even pushing much GPU power draw on my 3070) the DIMM temps were 44c in hwinfo64. I thought "meh that's pretty good considering a GPU is putting about 100 watts of heat into the case".

I then try the anta profile and after 15 minutes it's went to 47c. This isn't normal right? I have a 4000D Airflow which should be decent for cooling and it's cold here in the UK. I can't imagine what this would be doing somewhere hot. Think the heatspreaders haven't been properly attached? Can anyone else tell me what temps their XMP kit gets to in tm5?

I'm not erroring btw but if I'm getting 46c at 1.35v XMP can you imagine what 1.45v+ will do plus tighter timings than XMP...


----------



## Frosted racquet

You didn't say which kit you're using


----------



## Anhphe93

May i ask why when i overclock bclk my cpu clock is locked at 3.7ghz? is there any way to make it work properly?
Cpu: 5600x
Ram: 4000c15 - 2x8gb
Vga: 6900xt
Ssd: 970plus
Main: B550F-Gaming


----------



## Taraquin

Anhphe93 said:


> May i ask why when i overclock bclk my cpu clock is locked at 3.7ghz? is there any way to make it work properly?
> Cpu: 5600x
> Ram: 4000c15 - 2x8gb
> Vga: 6900xt
> Ssd: 970plus
> Main: B550F-Gaming


Don`t do bclk, do curve optimizer or run stock.


----------



## Olevider

Hello everybody on this thread.I have been reading for over a year and still find something new here.
But i register for help and advice. Yesterday i had accidently killed 3 rams sticks (while being drunk and with bad mood) because most of time my ram is unstable while they pass all test and but after 1 day to 1 month they can became unstable and just that. The ram was 2 kits of 2 F4-3200C14D-16GFX. First pair are June bought while other pair was December Gift i got.









this image is of only 1 alive
on two sticks i broke cap(resister? realy don't know how to call it properly)
on 3rd the same cap but on otherside in middle
4th stick didn't want but but after just little preheat and it worked
The first two worked even but and pass tm5 but after while became unstable on for cpu
3rd even not booting
So i was thinking is it possible to salvage from 3rd stick cap and put it on best of two stick?

The question that everybody gonna ask why i did dismantle heatspreader? Ask when i gona be drunk again i will give 100% answer.

2nd Question is i will need new RAM for sure but i need advice will those work for me? F4-3600C14D-32GVK*A.*
My setup is CPU Ryzen 3600 GPU /MSI 1080 Gaming X /MB Gigabyte X570 Aorus Pro v1.0 / PSU Seasonic PRIME PX-1000.My setup done for future upgrade was thinking going after 2 generetion of GPU and maybe maybe new Ryzen 5800X3D for future in 1-3 years.
So my question will those work out of box on my R. 3600? or i need them downclock from 3600Mhz to 3200Mhz?
Yes and even then i will fine tune them a little.


----------



## gameinn

Frosted racquet said:


> You didn't say which kit you're using


Updated my post. F4-3600C16D-32GTZN


----------



## Frosted racquet

From what I could gather reading other posts here, voltages aren't the only factor in increased RAM temps but resistances that you can set in BIOS as well. Only one way to find out is to test it. IME, temps don't increase too much unless you give them a lot of voltage. Heatsinks on that kit is adequate, unlike the one on RippjawsV...


----------



## The_King

My second stick of RAM arrived today BL8G32C16U4B (C9BJZ)
I am happy with the results 3600 CL14 @ 1.4V


----------



## Aretak

Welp, I finally managed to kill a memory stick. Fancy Dominator Platinum 3600/CL14 stuff too. I was attempting to push 1900MHz on the FCLK and having zero luck, so thought I'd try 1.2V on the SoC as a final throw of the dice (which as I've read is a perfectly safe voltage, albeit the upper limit). Booted, was even more unstable than at lower voltages, restarted the PC and noticed I was down to 16GB. I initially thought I'd killed the IMC or the board, but nope, it's one of the sticks. Not recognized at all in either of my systems. Old RAM kit back in and working fine in the same system. The RGB lighting still works, but it seems dead as a doornail other than that. I wasn't even pushing any decent amount of voltage through the RAM itself (1.45V, which is the XMP voltage), so I'm baffled really. I'd been running my Ballistix kit at 1.5V for years, including a year on this same 5800X/X570 ACE.

It's not really a problem as I've only had it a week and bought from Amazon, so it'll just go back. Never thought I'd have a stick just up and die like that though. Especially not when running it at its stock voltage.


----------



## ManniX-ITA

Aretak said:


> Never thought I'd have a stick just up and die like that though. Especially not when running it at its stock voltage.


Not related to VSOC or anything else probably.
Just defective from start, you have been lucky that it died quickly.


----------



## ManniX-ITA

Olevider said:


> So i was thinking is it possible to salvage from 3rd stick cap and put it on best of two stick?


That looks like a resistor, somewhere on it there should be a very little tiny code.
You need to find someone that can do SMD soldering to put it back.



Olevider said:


> 2nd Question is i will need new RAM for sure but i need advice will those work for me? F4-3600C14D-32GVK*A.*


Yes they'll work but don't mix them with your old ones which are SR, they are Dual Rank.


----------



## KedarWolf

ManniX-ITA said:


> Not related to VSOC or anything else probably.
> Just defective from start, you have been lucky that it died quickly.


Yeah, I agree. I've been running VSOC at 1.2v now ever since I got my 5950x a few months after the release date, it was a preorder, with 1.5v on RAM with zero issues to my CPU or RAM.

I can go lower but with my CO Curve, if I do, get reboots in CB23 and CB20. 

I think it's CPU related, not memory, as it'll pass TM5 lower.


----------



## KedarWolf

Oh, I get my tax refund money Thursday and am getting a Samsung Odyssey Neo G9 monitor and some G.Skill Royal Elite CL14 4000 RAM that was binned from three different kits. 😎

Edit: Ordered already Mainframe Customs Corsair AX1600i PSU cables and an Optimus Water Cooling Strix RTX 3090 water block and backplate.

Waiting for them to be fulfilled and delivered.


----------



## TMavica

KedarWolf said:


> Oh, I get my tax refund money Thursday and am getting a Samsung Odyssey Neo G9 monitor and some G.Skill Royal Elite CL14 4000 RAM that was binned from three different kits. 😎
> 
> Edit: Ordered already Mainframe Customs Corsair AX1600i PSU cables and an Optimus Water Cooling Strix RTX 3090 water block and backplate.
> 
> Waiting for them to be fulfilled and delivered.


i got the same mermory kit as you. I found it is difficult to tune. I now stuck at 14-15-15-30 with vdimm 1.5. I can go CL13 but it came with error in TM5, let see how urs! Thanks


----------



## nick name

KedarWolf said:


> Oh, I get my tax refund money Thursday and am getting a Samsung Odyssey Neo G9 monitor and some G.Skill Royal Elite CL14 4000 RAM that was binned from three different kits. 😎
> 
> Edit: Ordered already Mainframe Customs Corsair AX1600i PSU cables and an Optimus Water Cooling Strix RTX 3090 water block and backplate.
> 
> Waiting for them to be fulfilled and delivered.


Have you ever considered buying good components? 

I'm definitely jealous.


----------



## PJVol

@ManniX-ITA and everyone who wish to talk on the merits of the matter.

Hi! Not sure if you remember my concerns in our recent discussion about "y-cruncher n32/64 all-core" instability due to "unstable" curve. It all seemed suspicious to me then.
So I've put together some facts/observations (below) and now I am even more inclined to beleive the cause of those crashes is in fact some omission or a bug in firmware, and not the unstable (suddenly) psm counts. And I'm sure that reducing CO counts just compensate the critical Vdroop, that shouldn't actually happen.

1) Observations made by a OCN user here, that workloads in N32 and N64 dynamically switching. In my case I need almost all counts to be reduced by 4-5 (that is nonsense) to pass all-core N32/64.

2) The "weird behavior" of EDC manager I found on my platform, when experimenting with OCCT benchmark. Tldr: bench goes SC-MC-SC-MC. Sometimes after SC test, it "forgot" to activate clock-gating, that inevitably leads to crash in this MC test (SSE or AVX, doesn't matter, this "amnesia" may occur in both tests). The fact, that the crash is following this "stuck" frequency is 100% reproducible on my PC.

3) Looked through the D.Suggs et al. publication from the Hot Chips 2020 (April), and here is what they said about it:









If EDC manager needs several clocks to respond by clock/power-gating activation, won't it be too late, especially if the external power supply may add it's own delay, or simply respond with too big Vdroop?
The highlighted part is what really prompted me to share my thoughts with the community. Interesting to hear some opinions on the matter.


----------



## ManniX-ITA

@PJVol

It's a very interesting topic indeed 
My opinion is: yes & no.

I've sent back to RMA my beloved 5950X 
Always had stability problems running with SVM enabled and it got worse since it was updated by the latest AGESA.
Couldn't run anything in Virtualbox.
So I decided to roll the dices and see if I can get a better bin.
For the meantime I bought a 5800X which runs really hot, for being an 8 cores only, but it does 5050 MHz sustained on BoostTester.
Quite a decent bin, even if at FCLK 2000 spits lots of WHEA.
But works fine. I have yet to optimize the voltages.

Anyway before sending back the 5950X, I did run some torture tests with N32/N64.
N32 is for sure the fastest test to catch instabilities.
But it's not remotely enough to test alone, I could pass hours on an unstable count.
It does catch very quickly an highly unstable core but at the same time can pass flawlessly with a slight unstable one.

I've spent a bit more than a nighttime with N32/N64 on all 16 cores.
The result is that I didn't have to bring down any count.

I've tested every single core alone on all FFTs with Prime95 AAW/AVX/AVX2 using Corecycler and a few rounds as well with y-c.
Plus of course the all-core y-cruncher stress test.

From what I've seen if you have tested properly, N32/N64 will not fail.

If it's failing so blatantly that requires a huge drop in counts, there might be other explanations.

Yes I think as well the EDC manager is "bugged"; more than a bug I think it's limited.
From the behavior seems more a pattern based algorithm.
As said by AMD, it needs to be rather simple.
Cause it has to act with throttling in a millisecond and at the same time release the throttling as much fast.
Otherwise it would be too conservative and hurts performances.
It has its short history, which is a requirement for a pattern based algorithm.
But I don't think it's the problem here.

The Kagari binary is highly optimized and it uses AVX2, it's definitely one of the heaviest thing you can throw at it.
But it's also known to AMD, I don't think the EDC manager is failing detection there.
I couldn't replicate the unstable counts on my 5950X.

Where I've seen as well the EDC manager failing is with OCCT.
I thought something had changed in recent versions cause I had lost 100-150 MHz on single core testing.
But then I've tested the old versions as well and realized that what changed in between was my 5950X.
Which was upgraded by the AGESA and clearly got a more "wiser" EDC manager.
My new 5950X, with all settings optimized, couldn't do anymore 4925-4975 MHz on OCCT single core.
It was suddenly limited to a very steady 4825 MHz. And the 5800X seems limited to 4775 MHz.

My 5950X, probably because was one of the earliest batches, could always do that high.
No need to switch between ST-MT to trigger it.

Part of this big gain was due to telemetry settings.
The updated 5950X did change its behavior responding to fake telemetry dramatically.
It gained awareness, sadly, and wouldn't be fooled that easily.

But the other half that was pushing higher than stock were all the other settings.
I'm talking about voltages, LLC, PWM frequency, OCP and OVP limits.
The updated 5950X was able to constraint itself in a more conservative way than before.
Again a more painful self awareness.

This is an even more delicate point than the pattern recognition for the EDC manager.
Cause it's board dependent; what the board can really give, what is telling the CPU and what is faking to it.
All PBO decisions are based primarily on "what I can do".

From my testing you can't lower CO counts without proper "infrastructure" support.
Especially going up with the Boost clock.
The Boost clock will alter massively the V/F curve.
Even for heavy AVX2 workloads which runs sustained at a lower clock than the base FMax.
An unstable +200 MHz doesn't fail only running SSE at FMax+200.
It fails as well on AVX2 running below FMax.

I could run CCD at 950mV with the 5950X.
I would pass benchmarks and maybe basic tests.
But not with low negative CO counts.
The cores would fail even SSE ST testing with CoreCycler.
Adding +25 MHz max boost clock would make them fail faster or not even boot in Windows.

Passing this kind of stress tests, especially in ST mode, needs "more".
My CO counts that were passing N32/N64 would also need PWM at 900 kHz frequency to pass Prime95 SSE.
And so on and so on.

Higher CCD and IOD voltages, higher VSOC.
Relaxed OCP/OVP limits, strong LLC on VSOC.
The highest PWM settings that the board can support.
Stock hardly matters but PBO, even with a 6 cores, for ST boosting needs a good VRM.

My advice is to double check all the other settings.
Otherwise you can't go lower with the CO counts.

You can do almost everything with low voltages and conservative settings.
But you can't pass something harsh like Kagari N32 with a low count.
The core will try to churn IPC without much constraints at a high clock and will fail.

Will this increase in voltages and strong settings eat in your CPU power budget?
Yes sure but it's a non issue.
If your cores are running slower without, you don't need a higher power budget.
You are consuming it for what is really needed.

That's what we have benchmarks for.
If at the end of the day you get same or better scores, you are on a good OC path


----------



## Audioboxer

KedarWolf said:


> Oh, I get my tax refund money Thursday and am getting a Samsung Odyssey Neo G9 monitor and some G.Skill Royal Elite CL14 4000 RAM that was binned from three different kits. 😎
> 
> Edit: Ordered already Mainframe Customs Corsair AX1600i PSU cables and an Optimus Water Cooling Strix RTX 3090 water block and backplate.
> 
> Waiting for them to be fulfilled and delivered.


The EVGA step up queue for the 3080 in Europe is finally on the 2/11/2020. I'm the 11/11/2020. So in probably a few more weeks I'll finally have my 3080 and be part of this shiny new toys group.

How is that for patience? 😂 Not even a huge upgrade over a 2080Ti now but I've waited soo long I'll take it with nothing to pay but shipping.

That monitor is sexy as, but I think I'm going to wait for the QLED revolution. Mini-LED is better but QLED will hopefully bring down prices of the inflated monitor market. Wait, whatever DELL are calling their OLED monitor lol. I thought it was QLED but its probably QOLED or something. QLED is LCD IIRC.

Apart from a 3080 waterblock my other addition to the family is an XR7 radiator. I'm finally putting a chonky boy at the bottom of my case to replace the current XR5.

All quiet on the memory front, I'm basically done with memory now. Unless AMD sort out FCLK 2000 I have nowhere else to go. Speaking of that, MSI seem to be finally rolling out AGESA 1.2.0.6b, but to some random boards. Unify line seems to be absent so far.

Sadly AGESA 1.2.0.6b seems to be hardly any different from 1.2.0.5. I really don't know what AMD are doing just now, but with Intel getting their act together and having better CPUs for cheaper than AMD, AMD continuing to drop the ball for their current customers at the end of life for AM4 is pretty tragic.

It's as if they want to let Intel waltz in and steal their crown...


----------



## lafonte

PJVol said:


> @ManniX-ITA and everyone who wish to talk on the merits of the matter.
> 
> Hi! Not sure if you remember my concerns in our recent discussion about "y-cruncher n32/64 all-core" instability due to "unstable" curve. It all seemed suspicious to me then.
> So I've put together some facts/observations (below) and now I am even more inclined to beleive the cause of those crashes is in fact some omission or a bug in firmware, and not the unstable (suddenly) psm counts. And I'm sure that reducing CO counts just compensate the critical Vdroop, that shouldn't actually happen.
> 
> 1) Observations made by a OCN user here, that workloads in N32 and N64 dynamically switching. In my case I need almost all counts to be reduced by 4-5 (that is nonsense) to pass all-core N32/64.
> 
> 2) The "weird behavior" of EDC manager I found on my platform, when experimenting with OCCT benchmark. Tldr: bench goes SC-MC-SC-MC. Sometimes after SC test, it "forgot" to activate clock-gating, that inevitably leads to crash in this MC test (SSE or AVX, doesn't matter, this "amnesia" may occur in both tests). The fact, that the crash is following this "stuck" frequency is 100% reproducible on my PC.
> 
> 3) Looked through the D.Suggs et al. publication from the Hot Chips 2020 (April), and here is what they said about it:
> View attachment 2550505
> 
> 
> If EDC manager needs several clocks to respond by clock/power-gating activation, won't it be too late, especially if the external power supply may add it's own delay, or simply respond with too big Vdroop?
> The highlighted part is what really prompted me to share my thoughts with the community. Interesting to hear some opinions on the matter.


Really interesting, and I will not be surpriced it may be that the processor doen't react fast enoght, but the llc and/or positive voltage offset don't help in my case, I never got why edc exists and if has a job definity the description is wrong, after all the edc bug was the best feature of zen 2, I miss it...



ManniX-ITA said:


> Higher CCD and IOD voltages, higher VSOC.
> Relaxed OCP/OVP limits, strong LLC on VSOC.
> The highest PWM settings that the board can support.
> Stock hardly matters but PBO, even with a 6 cores, for ST boosting needs a good VRM.


Actually nothing help in my case on a x570 aorus pro rev 1.2 for n32 and n64 but at this point I will consider another test to tune the co that looks pretty bad (only one core -30 on the best ccd) probably for this reason compared to what I see around and I'll see if this settings change the result.


----------



## PJVol

ManniX-ITA said:


> For the meantime I bought a 5800X which runs really hot, for being an 8 cores only


Well, if we take CBR20, at 3800 IF/mem uncore consumes ~ 25W for both 5600 and 5800, with fused limits we've got ~14.6W per your core and ~ 8.5W per mine. So, yeah, looks pretty hot 

But back to the topic, since there are a couple more facts about my setup I wanted you to know:

1) none of the remaining y-cruncher test exhibited any instability (all passed), as well as OCCT any combination, Blender, Linpack, etc.

2) daily preset: {-9, -13, -16, -10, -5, -17}
N32/64 stable: {-3, -10, -12, -7, -2, -14}
PPT 130W, TDC 85A , EDC 140A, FIT x2, MaxBoost 4850

3) It's not for nothing I mentioned big Vdroop, as a possible factor. I meant the same as what you do saying "it's board dependent".

4) I realize that raising the max boost (above 4850 with beta bios) require a similar to above n32/64 curve. ST boost has never be a problem for me, same goes for idle/light reboots.

5) LLC CPU is always auto (in AVX2 droop exceeds 100mv), LLC SOC max. That's basiically all control i have over vrm 



lafonte said:


> the llc and/or positive voltage offset don't help in my case


Yeah. I've checked them out first, though didn't have high hopes on it.


lafonte said:


> I never got why edc exists and if has a job definity the description is wrong


It's very important metric. To put things simple
TDC and EDC are basically currents that make up static(~ leakage) and dynamic (~ C_ac * _F) power. So the EDC value meaning is how fast and how much total amount of capacity is currently switching.


----------



## lafonte

PJVol said:


> It's very important metric. To put things simple
> TDC and EDC are basically currents that make up static(~ leakage) and dynamic (~ C_ac * _F) power. So the EDC value meaning is how fast and how much total amount of capacity is currently switching.


I definitely agree it's really important, but in an electric system the "peak current"/"dynamic current" is something that should affect the system just for a short period of time and not during a sustained steady load, like a switch for an engine if you try to turn on an electrical motor with a switch that allows just the current the motor is using when is working the motor will never turn on cause at the beginning the motor will pull much more than that so we need a switch that allows the motor to pull much more current for a short period of time. Instead the EDC change completely how the processor works not only for short time but during sustained loads and has also really weird behaviour like:
If the EDC < 2 * TCD my 5950x acts as a big little with a difference in clock and temperature per CCD that increases more you decrease the EDC (can be up 500MHz and up 10°)
if I increase the EDC I get lower clock in light workloads
For every given workload exists an EDC value that provides the best performance/watt ratio so basically I can use it to tune the CPU for a specific or preferred workload
All this behaviours seems more about how the current is used and not about how much of it is available.
With the old EDC bug I don't really know what was happening precisely but the EDC was like auto limited to different values for different workloads and the fit was always at 100% under load now instead if I run a program of a while empty loop the processor has really nothing to do or almost but the fit is at 5/10% with a core temp of 40° and there are 50mV spare before the limit of 1.5V


----------



## KedarWolf

nick name said:


> Have you ever considered buying good components?
> 
> I'm definitely jealous.


Honestly though, because I'm awful at building custom water cooling loops, I took the easier softer way. I have an Optimus Foundation block I put on an EKWB Predator 360 AIO and my GPU is the Optimus block and backplate on an EKWB Phoenix 360 AIO. Also, the GPU has quick disconnects for assembling and disassembling easier. This restricts flow a bit. Really, the block is serious overkill for my video card setup and loop. I might add another 360 RAD to the GPU loop.

I DID buy Kritical 20 wm/k thermal pads for the waterblock and backplate for the Optimus block. They are actually tested and rated for 20 wm/k. I've read great things about them on Reddit.

I think the stock pads that come with the block are only 1.5 wm/k or maybe 6 wm/k.

Kritical 20 wm/k pads.


----------



## ManniX-ITA

KedarWolf said:


> I DID buy Kritical 20 wm/k thermal pads for the waterblock and backplate for the Optimus block. They are actually tested and rated for 20 wm/k. I've read great things about them on Reddit.
> 
> I think the stock pads that come with the block are only 1.5 wm/k or maybe 6 wm/k.


The Optimus Absolute backplate uses a full sheet of FujiPoly rated at 2.8 W/m-K.
You should really stick with it. 
It's more than enough and is proven to work better than any active backplate to cool the memory.

The front pads are FujiPoly 6.0 W/m-K.
Yes it doesn't look that much but the main point is that they are FujiPoly...
Which means they are truly what they say and more.
There are many very good reasons why Fujipoly is considered the reference in this segment.

If you make a controlled 1:1 test of a Fujipoly pad against any Chinese OEM rated 3x times the Fujipoly wins big time.

There are tons of other factors to consider, starting from the compression force.
One of the main performance factor of a pad is how well will work when compressed.
The cheap ones will lost most of the conductivity when compressed. The good ones not.
Then there's how well they perform at different temperatures and how they pair or not with different materials.

The cheap pads they only perform well in the hot wire ideal test conditions to give a nice marketing number for sales.
But under real working conditions there's no match for a Fujipoly or Laird.
And Laird already sucks in comparison to Fujipoly despite being almost as much expensive.

Not having a real datasheet means you just get the information they want you to see without context.
Which test standard has been used to get this magic W/m-K number?

There are many standards... the number you have seen for FujiPoly is taken using the ASTM D2356.
But what about the others? Do they tell?
t-Global does because they have a proper datasheet.
Their thermal conductivity is measured with the ASTM D5470 method.

Let's see how the Fujipoly 6.0 W/m-K is mapped to this standard:










The ISO/CD 22007-2 is ISO standard for ASTM D2356.
*Now it's magically a 11 W/m-K pad* 

Kritical Pads? How the heck are they?
Yes I have seen someone reporting they are fine.
Better than pads advertised for almost half the W/m-K like the Thermal Grizzly?
Not really, I've read more or less the same.

They are probably okay but definitely not even close the 20W/m-K they claim to be.
An high performance silicone pad it's much more expensive than that.
You can check Digikey or Mouser or any other professional reseller.






TG-A1660-100-100-1.0 t-Global Technology | Fans, Thermal Management | DigiKey


Order today, ships today. TG-A1660-100-100-1.0 – Thermal Pad Gray 100.00mm x 100.00mm Square from t-Global Technology. Pricing and Availability on millions of electronic components from Digi-Key Electronics.




www.digikey.de





This one from t-Global is 50% more expensive what they sell and is only 16.6 W/m-K.

I don't think it just happened they found the best OEM in the world which gave only them the highest performance pad existing at half the price.
It just doesn't add up.
They are good pads in the range of the Thermal Grizzly/Right & similar, nothing more in my opinion.

What I think it's worth to replace the front Fujipoly pads is the t-Global Thermal Putty:






TG-PP10-50 t-Global Technology | Fans, Thermal Management | DigiKey


Order today, ships today. TG-PP10-50 – Thermal Silicone Putty 50 gram Container from t-Global Technology. Pricing and Availability on millions of electronic components from Digi-Key Electronics.




www.digikey.de





It's a real 10 W/m-K (ASTM D5470) and it's confirmed it works better than higher rated "common" pads.
It needs to be applied very carefully with the Absolute block.
The real killer feature of this block is the precise machinery.
The GPU die if properly mounted will have a perfect full contact.
That's why they recommend KPx or liquid metal.

Using the thermal putty can really improve the contact and thermal transfer with the power stages and the PCB.
But even an half millimeter too much and the GPU die will have a higher deltaT.


----------



## KedarWolf

ManniX-ITA said:


> The Optimus Absolute backplate uses a full sheet of FujiPoly rated at 2.8 W/m-K.
> You should really stick with it.
> It's more than enough and is proven to work better than any active backplate to cool the memory.
> 
> The front pads are FujiPoly 6.0 W/m-K.
> Yes it doesn't look that much but the main point is that they are FujiPoly...
> Which means they are truly what they say and more.
> There are many very good reasons why Fujipoly is considered the reference in this segment.
> 
> If you make a controlled 1:1 test of a Fujipoly pad against any Chinese OEM rated 3x times the Fujipoly wins big time.
> 
> There are tons of other factors to consider, starting from the compression force.
> One of the main performance factor of a pad is how well will work when compressed.
> The cheap ones will lost most of the conductivity when compressed. The good ones not.
> Then there's how well they perform at different temperatures and how they pair or not with different materials.
> 
> The cheap pads they only perform well in the hot wire ideal test conditions to give a nice marketing number for sales.
> But under real working conditions there's no match for a Fujipoly or Laird.
> And Laird already sucks in comparison to Fujipoly despite being almost as much expensive.
> 
> Not having a real datasheet means you just get the information they want you to see without context.
> Which test standard has been used to get this magic W/m-K number?
> 
> There are many standards... the number you have seen for FujiPoly is taken using the ASTM D2356.
> But what about the others? Do they tell?
> t-Global does because they have a proper datasheet.
> Their thermal conductivity is measured with the ASTM D5470 method.
> 
> Let's see how the Fujipoly 6.0 W/m-K is mapped to this standard:
> 
> View attachment 2550544
> 
> 
> The ISO/CD 22007-2 is ISO standard for ASTM D2356.
> *Now it's magically a 11 W/m-K pad*
> 
> Kritical Pads? How the heck are they?
> Yes I have seen someone reporting they are fine.
> Better than pads advertised for almost half the W/m-K like the Thermal Grizzly?
> Not really, I've read more or less the same.
> 
> They are probably okay but definitely not even close the 20W/m-K they claim to be.
> An high performance silicone pad it's much more expensive than that.
> You can check Digikey or Mouser or any other professional reseller.
> 
> 
> 
> 
> 
> 
> TG-A1660-100-100-1.0 t-Global Technology | Fans, Thermal Management | DigiKey
> 
> 
> Order today, ships today. TG-A1660-100-100-1.0 – Thermal Pad Gray 100.00mm x 100.00mm Square from t-Global Technology. Pricing and Availability on millions of electronic components from Digi-Key Electronics.
> 
> 
> 
> 
> www.digikey.de
> 
> 
> 
> 
> 
> This one from t-Global is 50% more expensive what they sell and is only 16.6 W/m-K.
> 
> I don't think it just happened they found the best OEM in the world which gave only them the highest performance pad existing at half the price.
> It just doesn't add up.
> They are good pads in the range of the Thermal Grizzly/Right & similar, nothing more in my opinion.
> 
> What I think it's worth to replace the front Fujipoly pads is the t-Global Thermal Putty:
> 
> 
> 
> 
> 
> 
> TG-PP10-50 t-Global Technology | Fans, Thermal Management | DigiKey
> 
> 
> Order today, ships today. TG-PP10-50 – Thermal Silicone Putty 50 gram Container from t-Global Technology. Pricing and Availability on millions of electronic components from Digi-Key Electronics.
> 
> 
> 
> 
> www.digikey.de
> 
> 
> 
> 
> 
> It's a real 10 W/m-K (ASTM D5470) and it's confirmed it works better than higher rated "common" pads.
> It needs to be applied very carefully with the Absolute block.
> The real killer feature of this block is the precise machinery.
> The GPU die if properly mounted will have a perfect full contact.
> That's why they recommend KPx or liquid metal.
> 
> Using the thermal putty can really improve the contact and thermal transfer with the power stages and the PCB.
> But even an half millimeter too much and the GPU die will have a higher deltaT.


The Fuji pads on my GPU vertical mount are known to really leak a lot of nonconductive oil, is an issue with them.

And I emailed Kritical to see if they'll custom cut 0.5 waterblock pads and a full coverage 3.0mm backplate pad for my Optimus block. I'll willing to pay extra for the service. They'll include punched out holes for the backplate screws.

They make precut pads for various cards, so I hope they'll do that for me.

I also contacted Optimus Water Cooling support to get the exact size and dimensions of their replacement pads.


Custom thermal pad sets made to the exact dimensions required by the ASUS, Gigabyte, EVGA, and NVIDIA RTX 3080, RTX 3080Ti and RTX 3090. These sets have all that you need for 1 GPU.
Full thermal pad sheets (100x100mm, 0.5/1.0/1.25/1.5/2.0/3.0/4.0 mm thicknesses) available
20 W/m-K thermal conductivity for all pads (GPU sets as well as sheets).

Yes, it is verified (manufacturing report says 20.17 W/mK at 50°C)
Yes, it is possible with silicon-ceramic compounds.


__
https://www.reddit.com/r/hardwareswap/comments/t1jym5

Edit: The Kritical pads are reported to be soft, so I hope the die contact would be decent.


----------



## ManniX-ITA

PJVol said:


> 5) LLC CPU is always auto (in AVX2 droop exceeds 100mv), LLC SOC max. That's basiically all control i have over vrm


Yes my suspect is exactly that your board doesn't have enough juice to keep also N32/N64 stable.



PJVol said:


> 1) none of the remaining y-cruncher test exhibited any instability (all passed), as well as OCCT any combination, Blender, Linpack, etc.


From my testing with enough time (a lot) Prime95 AVX2 ST will fail, the rest of y-cruncher tests also but needs more time and a longer runtime than the standard 120 seconds.



PJVol said:


> TDC and EDC are basically currents that make up static(~ leakage) and dynamic (~ C_ac * _F) power. So the EDC value meaning is how fast and how much total amount of capacity is currently switching.


EDC is not only the dynamic current but more importantly *localized*.
To be short what it's trying to handle and prevent is electrons leakage; electro migration degradation on the copper interconnect pathways.
One of the pillars in the EDC manager is for sure the Black's equation to predict how long a copper pathway can live with a given Amperage at a given temperature.

The die is like a very optimized urban road map.
Think about the tiny low node copper interconnects like bridges that can support only a given load otherwise they break if too much trucks are going through at the same time.
They are delicate, especially when the temperature gets really high.
While there are many feeding VDD pins on the socket many die parts have to share the same feeding lanes.
When two die parts running concurrently needs eg. 30A each and it comes from different pathways that's fine.
But if they both needs to be fed by the same lane and the temperature is high the maximum Amperage on a single pathway could be calculated at eg. 40A.
That's when the EDC manager will act and throttle both die parts to eg. 20A each to prevent degradation.

Same as the throttle temperature I've talked earlier, *EDC is an average metric.*
It's not telling you the highest localized current peak but an average of the highest currents consumption in the zone with the highest load.
You can check it with indirect observation.
Same as the throttle temperature; you set higher than 90C and you'll see a CPU reset even with peak reported Core temperatures below 90C.

If you set EDC to motherboard limit you'll get an X score in a benchmark at Y EDC consumption.
Now set that Y EDC consumption (or slightly higher) as limit and you'll likely see a different (usually better) score with the same benchmark.
Why is that?
Cause the EDC consumption you got using motherboard limits was an average; normalized & mitigated.
There were peaks you couldn't see and those peaks with the Y EDC limit were throttled by the EDC manager.



KedarWolf said:


> The Fuji pads on my GPU vertical mount are known to really leak a lot of nonconductive oil, is an issue with them.


It's an issue with any silicone thermal pad.
Means they have been compressed too much.

Found out when the Laird thermal pads on my Gigabyte Master leaked tons of oil.
They were not properly mounted.

This is from the Fujipoly's handling notes 










The Optimus guys should have calculated and documented the correct force to apply.
With a controlled force screwdriver this would have been an easy problem to fix.
You'll probably have the same issue with the Kritical pads, don't tight too firmly the screws.
With a full coverage pad the issue can manifest orders of magnitudes faster than with small pads.


----------



## ManniX-ITA

KedarWolf said:


> And I emailed Kritical to see if they'll custom cut 0.5 waterblock pads and a full coverage 3.0mm backplate pad for my Optimus block. I'll willing to pay extra for the service. They'll include punched out holes for the backplate screws.


It's indeed an interesting offer, even if they are not really 20W/m-K.
I'll ask the guy some more info on Reddit.


----------



## lafonte

ManniX-ITA said:


> If you set EDC to motherboard limit you'll get an X score in a benchmark at Y EDC consumption.
> Now set that Y EDC consumption (or slightly higher) as limit and you'll likely see a different (usually better) score with the same benchmark.
> Why is that?
> Cause the EDC consumption you got using motherboard limits was an average; normalized & mitigated.
> There were peaks you couldn't see and those peaks with the Y EDC limit were throttled by the EDC manager.


If that was the case then the behaviour should be that for every workload increase the EDC will increase the performance till the fit/EDC manager decide that more current will be dangerous for the processor and increasing the EDC should result in the same performance, instead what we've got is a regression in performance after a certain value, that doesn't make sense cause the only reason I can think about that explains it is that the algorithm is broken and with that I mean that since we give the availability for more EDC the algorithm use it but actually that extra current cause the action of another protection system that reduce the overall performance.


----------



## ManniX-ITA

lafonte said:


> If that was the case then the behaviour should be that for every workload increase the EDC will increase the performance till the fit/EDC manager decide that more current will be dangerous for the processor and increasing the EDC should result in the same performance, instead what we've got is a regression in performance after a certain value, that doesn't make sense cause the only reason I can think about that explains it is that the algorithm is broken and with that I mean that since we give the availability for more EDC the algorithm use it but actually that extra current cause the action of another protection system that reduce the overall performance.


No it doesn't work linearly for every workload that more EDC will increase the performances.
You don't get more performances with a higher EDC limit sorting a small array in memory...

It's of course a specific test case which I was talking about.
You get a regression after a specific value, depending on the workload, cause it's not only about the EDC manager but the whole PBO boosting algorithm.
Which is by far much more complex and depending on many more input sources and considers and enact many more throttling systems for protection.

The algorithm is not "broken", more like it's not perfect. In some cases works fine, in others less.
It's well known that crafted limits are performing usually better than open limits.
There are many good reasons for it.

If it wasn't like this, PBO would be extremely conservative and opportunities for OC much less likely.
There are so many things that can happen with limits too relaxed.
Starting from excessive current going through pathways that can throttle due to high temperatures.
Boards that can't deliver what they are expected to and will cause throttling due to insufficient power delivery.
Too much optimistic predictions from PBO resulting in drop of IPC eg CPU-z crunching high at start and then dropping lower and lower instead of stabilizing steady.

The V/F curve it's not a straight line of course.
It's more like a multi dimensional matrix.
Which is considering some static data like FIT and other important settings like limits, boost clock, scalar, etc.
Plus some massive amount of dynamic data coming from current, load and temperature sensors.

What maybe it's not clear is that *it defines also the acceleration from one point of the curve to the next*.
This is extremely important and that's where how good is the board power delivery makes a huge difference.
If PBO while going to the next point of the curve senses a vdroop too high, higher than what was predicted, the CPU will throttle.
Or any other telemetry data from the board VRM that doesn't adds up. Throttling.
vdroop is compensation; if the board can't deliver the right vCore when PBO is trying to go up thousands of Hz in clock it will scale back.
Same for an LLC too high, if it senses overshooting it will stop boosting too fast up and down.

Crafted limits will define a curve which will fit the capabilities of your cooling, the FIT, the board power delivery.
This means the predicted acceleration will be in line with what will happen and you'll get better performances.
Open limits are a roll of dices, if the system can keep up they'll work better but you need the right setup in all of its aspects.


----------



## PJVol

ManniX-ITA said:


> Same as the throttle temperature I've talked earlier, *EDC is an average metric.*
> It's not telling you the highest localized current peak but an average of the highest currents consumption in the zone with the highest load.


I beleive you somehow confused the EDC itself with a principles behind amd's EDC throttler implementation.
EDC is a VRM characteristic.


----------



## ManniX-ITA

PJVol said:


> EDC is a VRM characteristic.


No confusion 
It's both a VRM characteristic, for feeding, and CPU, for consumption.
The EDC manager is not throttling by telling the VRM to cap the current but by limiting the request from the CPU.


----------



## PJVol

ManniX-ITA said:


> The EDC manager is not throttling by telling the VRM to cap the current but by limiting the request from the CPU.


Of course not, but at the same time power gating need lower VID request.
EDC is still defined by the VRM, though the time window seems to be determined by amd themselves:


> Voltage regulators of computing devices enforce an electrical design current (EDC) limit defining a maximum amount of current that can be drawn within a short time window (e.g., 1-4 ms). When this limit is reached, the voltage regulator implements overcurrent protection to reduce the drawn current, including stalling or deactivating one or more components.








US Patent Application for ELECTRICAL DESIGN CURRENT THROTTLING Patent Application (Application #20210004068 issued January 7, 2021) - Justia Patents Search


Electrical design current throttling, including: applying an electrical design current (EDC) threshold for each control processing unit component of a plurality of the central processing unit components responsive to the corresponding priority of each central processing unit component, the...




patents.justia.com


----------



## ManniX-ITA

PJVol said:


> EDC is still defined by the VRM, though the time window seems to be defined by amd themselves:


I think this is describing how the motherboard is implementing its throttling when the EDC hard limit is reached.
It's from the feeding side, I don't think there's much relation with the EDC manager in the CPU.


----------



## PJVol

ManniX-ITA said:


> It's from the feeding side, I don't think there's much relation with the EDC manager in the CPU.


Actually, the patent is about EDC manager in a CPU, it's continuation in part of earlier provisional application (not published).
Just check it out.


----------



## ManniX-ITA

PJVol said:


> Yes, the patent is about EDC manager in CPU, it's continuation in part of earlier provisional application (not published)


What I mean is that what you describe and quoted is the problem the patent is aiming to solve:

*BACKGROUND*
_Voltage regulators of computing devices enforce an electrical design current (EDC) limit defining a maximum amount of current that can be drawn within a short time window (e.g., 1-4 ms). When this limit is reached, the voltage regulator implements overcurrent protection to reduce the drawn current, including stalling or deactivating one or more components. This results in a decrease in computer performance_

This is the problem to solve not the solution; your CPU reach the EDC limit and the VRM will implements OCP protections. Which will probably hard reset the CPU or slow it down, etc.

The solution is below in the patent:

*The throttling module 114 is implemented by one or more software modules (e.g., firmware and/or other types of software) and/or one or more hardware components (e.g., components affixed to or in communication with a central processing unit (CPU).*

Which is the EDC manager in Ryzen, described in a simplistic way.
The main goal is to prevent you reach the EDC limit from the feeding side as it will "_reduce the drawn current, including stalling or deactivating one or more components"._
And we don't want that of course 
Plus all the other goodies about avoiding interconnects degradation and whoever knows what more.


----------



## Luggage

ManniX-ITA said:


> No it doesn't work linearly for every workload that more EDC will increase the performances.
> You don't get more performances with a higher EDC limit sorting a small array in memory...
> 
> It's of course a specific test case which I was talking about.
> You get a regression after a specific value, depending on the workload, cause it's not only about the EDC manager but the whole PBO boosting algorithm.
> Which is by far much more complex and depending on many more input sources and considers and enact many more throttling systems for protection.
> 
> The algorithm is not "broken", more like it's not perfect. In some cases works fine, in others less.
> It's well known that crafted limits are performing usually better than open limits.
> There are many good reasons for it.
> 
> If it wasn't like this, PBO would be extremely conservative and opportunities for OC much less likely.
> There are so many things that can happen with limits too relaxed.
> Starting from excessive current going through pathways that can throttle due to high temperatures.
> Boards that can't deliver what they are expected to and will cause throttling due to insufficient power delivery.
> Too much optimistic predictions from PBO resulting in drop of IPC eg CPU-z crunching high at start and then dropping lower and lower instead of stabilizing steady.
> 
> The V/F curve it's not a straight line of course.
> It's more like a multi dimensional matrix.
> Which is considering some static data like FIT and other important settings like limits, boost clock, scalar, etc.
> Plus some massive amount of dynamic data coming from current, load and temperature sensors.
> 
> What maybe it's not clear is that *it defines also the acceleration from one point of the curve to the next*.
> This is extremely important and that's where how good is the board power delivery makes a huge difference.
> If PBO while going to the next point of the curve senses a vdroop too high, higher than what was predicted, the CPU will throttle.
> Or any other telemetry data from the board VRM that doesn't adds up. Throttling.
> vdroop is compensation; if the board can't deliver the right vCore when PBO is trying to go up thousands of Hz in clock it will scale back.
> Same for an LLC too high, if it senses overshooting it will stop boosting too fast up and down.
> 
> Crafted limits will define a curve which will fit the capabilities of your cooling, the FIT, the board power delivery.
> This means the predicted acceleration will be in line with what will happen and you'll get better performances.
> Open limits are a roll of dices, if the system can keep up they'll work better but you need the right setup in all of its aspects.


Quite a few workloads don't like high EDC and I'm still not sure if it's only a thermal give and take :/
With my cooling now during winter I can set limits so that they never reach 100% - but that's only "good" for very heavy workloadsl like yc 2.5b.
L3 cache seems to be the thing that loves EDC.

And that single core boost gets worse with high limits is just crap.

From earlier in january.








Making sense of AMD and The Stilt's information...


If you can think of an application that always pushes single core performance to the absolute top in terms of VID and clocks Isn't corecycler what you are after?




www.overclock.net





Easy test for low pbo limits is to try and optimize for CPU-Z, best sc and mc is with lower than stock.


----------



## lafonte

ManniX-ITA said:


> No it doesn't work linearly for every workload that more EDC will increase the performances.


If you consider the EDC in the range 1-600 actually it does, I can show you that drawing a graph of the time that the a program needs to complete a task X times will look like a curve that increases till a value of EDC and after gradually decreases.



ManniX-ITA said:


> This is extremely important and that's where how good is the board power delivery makes a huge difference.


Personally I had a 3700x on a MSI b450m pro after I switched it with a GB x570 pro planning to upgrade the CPU too, now the 2 boards have a vrm of a complete different league but the pbo behaviour with the same agesa was exactly the same. Same clocks for all the core in st and Mt same negative offset before the X core crashed same goes with static overclock not even 25Mhz more if the difference there is is so small that doesn't really make a difference in real world


----------



## ManniX-ITA

Luggage said:


> Easy test for low pbo limits is to try and optimize for CPU-Z, best sc and mc is with lower than stock.


Maybe with a 5800X?
I'm running one now but I didn't test it.
For a 5950X all mc scores are hammered down with stock or below stock limits.
And ST with stock limit is slightly higher.
But with a careful tuning it can come close to stock even with very high PBO limits.

CPU-z is quite peculiar and a single workload.
It has its own purpose but alone it's limited.
I prefer Geekbench 5 cause it's a wide variety of different workloads.
You can see which one is more dependent on clock, memory or number of cores.

This is the 5800X against the 5950X:



Micro-Star International Co., Ltd. MS-7D13 vs Micro-Star International Co., Ltd. MS-7D13 F2000 Baseline - Geekbench Browser



Only a few scores are at 50%, many MT scores are only slightly lower with the 5800X.


----------



## ManniX-ITA

lafonte said:


> If you consider the EDC in the range 1-600 actually it does, I can show you that drawing a graph of the time that the a program needs to complete a task X times will look like a curve that increases till a value of EDC and after gradually decreases.


I mean that if the workload can take advantage of it, yes you'll see a linear increase.
But not with everything.
If it does, it will probably start to decrease after the higher limit will become an issue instead of an advantage.



lafonte said:


> Personally I had a 3700x on a MSI b450m pro after I switched it with a GB x570 pro planning to upgrade the CPU too, now the 2 boards have a vrm of a complete different league but the pbo behaviour with the same agesa was exactly the same. Same clocks for all the core in st and Mt same negative offset before the X core crashed same goes with static overclock not even 25Mhz more if the difference there is is so small that doesn't really make a difference in real world


That's not the league I was talking about 









Elenco X570 con VRM


Foglio1 AMD,Creato da R3d3x Tech qp,Usa la visualizzazione filtrata per confrontare le schede madri! Come? Chipset X570,<a href="https://www.youtube.com/c/TechqpR3d3x">https://www.youtube.com/c/TechqpR3d3x</a>,1) Clicca sulla riga 8 2) In alto a sinistra vicino all'icona della st...




docs.google.com





The AORUS X570 Pro VRM is just enough decent. You can't expect any visible difference.
Doubler with 6+2 phases and 40A MOSFET it's okay. Means it can run a 5950X with mild OC.

The good stuff is expensive for a reason, the AORUS Master and Extreme VRM are in the league that can make a difference.


----------



## PJVol

ManniX-ITA said:


> This is the problem to solve not the solution


It was quoteted just in context of clearing out what EDC is, not the EDC limit or some functionality based on its monitoring. The current EDC throttler is described earlier in the series.
Here, for example:





US20190146567A1 - Processor throttling based on accumulated combined current measurements - Google Patents


A processor is throttled based on accumulated combined current measurements from a plurality of processor cores. The processor monitors activity current levels at each processor core, either directly or indirectly by monitoring specified events at the processor cores. The processor combines...



patents.google.com


----------



## Audioboxer

Damn those intel cpus are power hungry mofos lol

As bad as AMD software jank is, and the unfortunate conclusions with FCLK to end the generation, it's mighty impressive the power draw of AMD CPUs for the performance they can provide.

This alone would make me want to wait on AM5 and/or Intel refining this generation a bit.

Really hope AMD can sort their memory controller out for AM5. I guess it will be totally different with it supporting DDR5.


----------



## ManniX-ITA

PJVol said:


> It was quoteted just in context of clearing out what EDC is, not the EDC limit or some functionality based on its monitoring. The current EDC throttler is described earlier in the series.


I feel like we are going back in circles 



PJVol said:


> I beleive you somehow confused the EDC itself with a principles behind amd's EDC throttler implementation.
> EDC is a VRM characteristic.


Maybe I misunderstood what you said here.



ManniX-ITA said:


> Same as the throttle temperature I've talked earlier, *EDC is an average metric.*


Which was a comment about the sentence above.
Maybe it wasn't clear, I was talking about the EDC value which is reported by the CPU.


----------



## Luggage

ManniX-ITA said:


> Maybe with a 5800X?
> I'm running one now but I didn't test it.
> For a 5950X all mc scores are hammered down with stock or below stock limits.
> And ST with stock limit is slightly higher.
> But with a careful tuning it can come close to stock even with very high PBO limits.
> 
> CPU-z is quite peculiar and a single workload.
> It has its own purpose but alone it's limited.
> I prefer Geekbench 5 cause it's a wide variety of different workloads.
> You can see which one is more dependent on clock, memory or number of cores.
> 
> This is the 5800X against the 5950X:
> 
> 
> 
> Micro-Star International Co., Ltd. MS-7D13 vs Micro-Star International Co., Ltd. MS-7D13 F2000 Baseline - Geekbench Browser
> 
> 
> 
> Only a few scores are at 50%, many MT scores are only slightly lower with the 5800X.


My main problem with geekbech is that all the sub-test are so very short. I’m not sure they are long enough to reach “steady state”. 
Same problem as the boost tester in Hydra.


----------



## ManniX-ITA

Luggage said:


> My main problem with geekbech is that all the sub-test are so very short. I’m not sure they are long enough to reach “steady state”.
> Same problem as the boost tester in Hydra.


Yes that's my main concern as well with GeekBench.
I really would have loved an extended test with more runtime per each test.
But the short runtime is actually very helpful to diagnose and characterize issues with PBO boosting.
A longer execution time would mitigate any issue, the sustained clock would normalize scores toward the bottom.
It would be another use case, very useful for sustained clock but less for boosting.


----------



## lafonte

ManniX-ITA said:


> The AORUS X570 Pro VRM is just enough decent. You can't expect any visible difference.
> Doubler with 6+2 phases and 40A MOSFET it's okay. Means it can run a 5950X with mild OC.
> 
> The good stuff is expensive for a reason, the AORUS Master and Extreme VRM are in the league that can make a difference


Actually the rev 1.2 I own has 60A power stages without doublers, but you're right about the phase count, considering that the power stage has a peak efficiency at 20A X 12 power stages = 240A of current that the motherboard can supply without any issues and with pretty low vrm temperature probably temperature and power delivery will start to be an issue after 300A but there is no way to check it cause already I cannot pull 240A, about the EDC we are talking about 720A what can be a "problem" is the transient response but no one in the community has been able to provide proof that high phase count vrm actually improve the overclocking capability of a board in real world, if you know someone please share it.



ManniX-ITA said:


> I mean that if the workload can take advantage of it, yes you'll see a linear increase.
> But not with everything.


Please trust me, it always make a difference and doesn't matter the workload it behaves always in the same way only the EDC "best" value changes, programming is my hobby and many times I run bench of software or pieces of code to see how it performs and if a method is better than another one and I tested the EDC as well when one day I realized that by keeping the stock ppt and tdc while increasing the EDC to 190 I've got +5% in code compilation of different projects while the temperature and the power consumption of the CPU was the same.


----------



## Sam_Oslo

Is it a bad idea to mix to different kits?

I have a 2x8 3660c16 kit and can get a 2x8 3200c14 kit too. Both are B-Die. Will it create complications for overclocking?


----------



## lafonte

Sam_Oslo said:


> Is it a bad idea to mix to different kits?
> 
> I have a 2x8 3660c16 kit and can get a 2x8 3200c14 kit too. Both are B-Die. Will it create complications for overclocking?


If the PCB is the same is not ideal but not so bad, if the PCB is different is a bad idea.


----------



## nick name

Sam_Oslo said:


> Is it a bad idea to mix to different kits?
> 
> I have a 2x8 3660c16 kit and can get a 2x8 3200c14 kit too. Both are B-Die. Will it create complications for overclocking?


Those kits seem to end up in the same place when overclocked so I would assume you'd be alright. Of course when you combine them you'll also have to account for the higher capacity and extra dimms so expect to use more voltage and/or slightly looser timings.


----------



## nick name

lafonte said:


> If the PCB is the same is not ideal but not so bad, if the PCB is different is a bad idea.


I've mixed PCB revisions without issue. I wouldn't worry about that.


----------



## ManniX-ITA

lafonte said:


> Please trust me, it always make a difference and doesn't matter the workload the workload it behaves always in the same way only the EDC "best" value changes, programming is my hobby and many times I run bench of software or pieces of code to see how it performs and if a method is better than another one and I tested the EDC as well when one day I realized that by keeping the stock ppt and tdc while increasing the EDC to 190 I've got +5% in code compilation of different projects while the temperature and the power consumption of the CPU was the same.


I do the same but I couldn't replicate this behavior.
Code compilation is definitely something that is expected to scale up.
What about something that doesn't get close to the limit?
Anyway I'll check again, I'm writing my own bench suite and it'll be fun to test these cases 



lafonte said:


> no one in the community has been able to provide proof that high phase count vrm actually improve the overclocking capability of a board in real world, if you know someone please share it.


I can only speak from my experience and there's no proof to share... either you trust me or don't 

I've moved my old 3800X from the AORUS Master to my niece's cheap ASUS B550 TUF Gaming.
There's no match, not even close, in what could be pushed with the Master.
A strong VRM makes a big difference but if you don't spend a lot of time tuning it before and after you can hardly understand.
You would see a lot of people setting records in HWBot with cheap boards if that was the case but it isn't.

The 5950X is of course much more needy and I can tell you that without maximizing the PWM frequency you just can't do some stuff.
To avoid black screens and reboots under ST load with a low negative count and +100 MHz on boost clock you need high PWM frequency.
If you are limited in what you can set, you'll get limited options.
No OVP or OCP protection settings on vCore?
You have to reduce the counts.

Now I'm not sure I remember correctly all the details but I have a friend that got a nicely binned 5900X with an AORUS X570 Pro.
It couldn't push much the boost clock and the counts cause some settings were missing in the VRM section.
I was surprised that the section was so poorly populated...
Bought an AORUS B550 Master and he could push it much higher without reboots under GB5 ST.

Same for another one with an X570 Unify, very nice binning 5950X.
But still pretty limited in stability cause the VRM is quite undersized compared to the Unify-X.

I don't know how much true phases makes a difference or not, the theory says it does.
There are also ASUS boards with "fake" dual/tri phases without doublers that works pretty well.
But for sure the PWM frequency, the OCP/OVP control and how good is LLC have a big sizeable impact in what you can do.


----------



## Luggage

lafonte said:


> Actually the rev 1.2 I own has 60A power stages without doublers, but you're right about the phase count, considering that the power stage has a peak efficiency at 20A X 12 power stages = 240A of current that the motherboard can supply without any issues and with pretty low vrm temperature probably temperature and power delivery will start to be an issue after 300A but there is no way to check it cause already I cannot pull 240A, about the EDC we are talking about 720A what can be a "problem" is the transient response but no one in the community has been able to provide proof that high phase count vrm actually improve the overclocking capability of a board in real world, if you know someone please share it.
> 
> 
> Please trust me, it always make a difference and doesn't matter the workload it behaves always in the same way only the EDC "best" value changes, programming is my hobby and many times I run bench of software or pieces of code to see how it performs and if a method is better than another one and I tested the EDC as well when one day I realized that by keeping the stock ppt and tdc while increasing the EDC to 190 I've got +5% in code compilation of different projects while the temperature and the power consumption of the CPU was the same.


And @ManniX-ITA 

Just a quick boost test - ignore the score, cpu-z calculation of the score ****s up after a little bit. I ran it a long time first to stabilize water temp.

"Unlimited" cpu-z tops out under 150-90-165

Scales with EDC only to 110-120, best was 112 for the given PPT and TDC.

Last one I tuned PPT and TDC as well, did not redo EDC from 112. Best was well under stock limits.



http://imgur.com/a/5QD8amF


----------



## ManniX-ITA

Luggage said:


> Just a quick boost test - ignore the score, cpu-z calculation of the score ****s up after a little bit. I ran it a long time first to stabilize water temp.
> 
> "Unlimited" cpu-z tops out under 150-90-165
> 
> Scales with EDC only to 110-120, best was 112 for the given PPT and TDC.


Sorry I'm lost 
What should I look at?


----------



## Sam_Oslo

Thx both for the answer 



nick name said:


> Those kits seem to end up in the same place when overclocked so I would assume you'd be alright. Of course when you combine them you'll also have to account for the higher capacity and extra dimms so expect to use more voltage and/or slightly looser timings.


I don't know about the PCB of 3200c14 kit, but both kits are G.Skill Trident Z, so they may even have the same PCB too.

Yeah they should end up in the same place when overclocked. I will give it a try


----------



## Luggage

ManniX-ITA said:


> Sorry I'm lost
> What should I look at?


Effective clock vs EDC


----------



## PJVol

Luggage said:


> Effective clock vs EDC


Why the scores themselves as if they're from single core test?


----------



## Sam_Oslo

Audioboxer said:


> Damn those intel cpus are power hungry mofos lol
> 
> As bad as AMD software jank is, and the unfortunate conclusions with FCLK to end the generation, it's mighty impressive the power draw of AMD CPUs for the performance they can provide.
> 
> This alone would make me want to wait on AM5 and/or Intel refining this generation a bit.
> 
> Really hope AMD can sort their memory controller out for AM5. I guess it will be totally different with it supporting DDR5.


Wow, those Intel CPUs are really power hungry. Even with 1.21v it's at 270w


----------



## Luggage

PJVol said:


> Why the scores themselves as if they're from single core test?


score is ****ed after running for an hour


----------



## ManniX-ITA

Luggage said:


> Effective clock vs EDC


I really don't know what's happening with your setup, it doesn't work as expected 

Can't replicate that massive effective clock with low EDC.

It just drops down massively for me at 80A and gets lower with a very high EDC.


----------



## dk_mic

an observation when revisiting CO and y-cruncher N64 single core
Just for testing: Had a core running at -30 without issues, but only tested with SSE in corecycler.
To pass N64 in y-cruncher, it needed -21.

So i set it to -26 and y-cruncher crashes immediately, as expected.
Then i changed settings, in order to run it stable:

increase VSOC to 1.2 V
increase VDDG CCD to 1.05 V
remove auto oc (there is an automatic setting on AGESA 1.2.0.5 at MSI, had it to positive and that results in +25 MHz)
scalar 10
OCP and OVP, high VSOC loadline (running max switching frequency already)

Nothing of this helped.

Then i changed PBO limits from disabled, as I want to run it rather on the efficient side (which means on MSI: default AMD specification, 142,95,140 iirc)
to Motherboard (500,168,215 iirc) and it happily keeps calculating y-cruncher N64 on this core at -26

what gives?


----------



## Luggage

ManniX-ITA said:


> I really don't know what's happening with your setup, it doesn't work as expected
> 
> Can't replicate that massive effective clock with low EDC.
> 
> It just drops down massively for me at 80A and gets lower with a very high EDC.
> 
> View attachment 2550576
> 
> 
> View attachment 2550577
> 
> 
> View attachment 2550578


Looks like you replicated it perfectly - 112a is higher clocks than 80 and 180? Now just 112 might not be ideal for you but... I bet it's under 140.


----------



## Audioboxer

dk_mic said:


> an observation when revisiting CO and y-cruncher N64 single core
> Just for testing: Had a core running at -30 without issues, but only tested with SSE in corecycler.
> To pass N64 in y-cruncher, it needed -21.
> 
> So i set it to -26 and y-cruncher crashes immediately, as expected.
> Then i changed settings, in order to run it stable:
> 
> increase VSOC to 1.2 V
> increase VDDG CCD to 1.05 V
> remove auto oc (there is an automatic setting on AGESA 1.2.0.5 at MSI, had it to positive and that results in +25 MHz)
> scalar 10
> OCP and OVP, high VSOC loadline (running max switching frequency already)
> 
> Nothing of this helped.
> 
> Then i changed PBO limits from disabled, as I want to run it rather on the efficient side (which means on MSI: default AMD specification, 142,95,140 iirc)
> to Motherboard (500,168,215 iirc) and it happily keeps calculating y-cruncher N64 on this core at -26
> 
> what gives?


PBO values suited for MT often cause ST to boost a little lower, it's the trade off with PBO. You can either aim for highest ST/light load boosting possible, best MT or what most people do, strike a balance.

142/95/140 is perfect for ST boosting. So under these PBO values y-cruncher will boost the core higher.

500/168/215 pushed TDC/EDC much higher which may help MT a bit, but it will lower a ST boost.

You're testing ST boosting with Corecycler so it will be going to a lower frequency which means _potentially_ more stable at a higher negative curve.

Motherboard limits is a really ineffecient way to run PBO, chances are such values are past the point of optimal even for your best MT boosting so all you really end up with is excess heat and possibly even LOWER MT scores than if you tweak the PBO values properly.

tldr; PBO values impact your curve so you can get different results in stability tests depending on what they are.


----------



## dk_mic

ok, time to go back re-tuning the curve with y-cruncher and high limits.
I think i still could achieve quite good SC scores in CPUZ with higher limits, something like only max 5 points difference some time ago


----------



## dk_mic

well, i think Unify X Mobo limits are actually quite close to optimal


----------



## Luggage

dk_mic said:


> well, i think Unify X Mobo limits are actually quite close to optimal


PPT is far too high even for 5950X, not sure about TDC and EDC.

Any limit that puts usage under 95% is mainly wasting power. (Except high edc for Aida L3 cache?)

With 5800X and 10C water I top out at 208-135-169 with any heavy workload. P95, yc, linx. 5950X should be a bit higher but not 500W.


----------



## ManniX-ITA

Luggage said:


> Looks like you replicated it perfectly - 112a is higher clocks than 80 and 180? Now just 112 might not be ideal for you but... I bet it's under 140.


I mean I can't replicate those very high effective clocks at 80A limit.
That doesn't seem normal.
Yes my best is 140A.

I'm set at 135/90/140 which are very close to what was best for the 3800X.


----------



## dk_mic

isn't PPT just a function of TDC/EDC and never really touched when set to like 250 or so?


----------



## ManniX-ITA

dk_mic said:


> to Motherboard (500,168,215 iirc) and it happily keeps calculating y-cruncher N64 on this core at -26


Those are not the motherboard limits.
Better to set the PPT to 280W or around that.

What about VDDG IOD?


----------



## Audioboxer

dk_mic said:


> well, i think Unify X Mobo limits are actually quite close to optimal


I've ran 270/168/220 to push my highest CB23 score, but outside of CB23 basically nothing I run or use has any need for such heavy MT use on my 5950x lol.

Ended up reducing to push more frequency for gaming/light loads.

I've seen CB23 hit 250w on my 5950x, but that's about it. Absolutely no need to set PPT much higher. Just a bit above the max.


----------



## ManniX-ITA

dk_mic said:


> isn't PPT just a function of TDC/EDC and never really touched when set to like 250 or so?


No, it's set package power limit in Watt.


----------



## Luggage

ManniX-ITA said:


> I mean I can't replicate those very high effective clocks at 80A limit.
> That doesn't seem normal.
> Yes my best is 140A.
> 
> I'm set at 135/90/140 which are very close to what was best for the 3800X.


Well my overall clocks are higher because of my cooling. 80a is the worst of my test examples…

Edit: well might be my 0.0125v offset?


----------



## Audioboxer

If I run 142/95/140 with a +50 AUTO OC everything just about squeezes over 5ghz with a light load, but it becomes clear the 2nd CCD is a bit weaker than the 1st. Though I think that is the case for the vast majority of 2 CCD AMD processors.

Core 5 is my problematic core, claims its the 2nd best but it's stuck at a -1 on the curve. If I put it to even -5 boosting goes up to like 5,075mhz, but it fails Corecycler.

On Agesa 1.2.0.3c it was at -5. Agesa 1.2.0.5 pushed it down to -1.


----------



## ManniX-ITA

Luggage said:


> Well my overall clocks are higher because of my cooling. 80a is the worst of my test examples…


Yes higher but I'm talking about this:










At 80A my 5800X with CPU-z is constrained by the EDC and drops the effective clocks:










Which doesn't seem to happen with yours.
It's not a temperature constraint as going higher with EDC mines are a bit lower but not that much.



Luggage said:


> Edit: well might be my 0.0125v offset?


Maybe it's really the offset I'll try


----------



## dk_mic

@Audioboxer, can you confrirm that you are less stable with default limits at y-cruncher N32/64, maybe on that borderline stable core?
@ManniX-ITA you are right

















I thought its 500/168/215.. could they be changed, depending on other settings or BIOS/AGESA version?
Didn't change VDDG IOD in order to make y-cruncher CoreCycler stable. Its at 1.060 in BIOS I think.

Ok, then obivously motherboard limits are bad.
I did test those limits now.









I guess, I'll settle to 168/220. MT tanks so hard, and there are little gains in SC when lowering limits. At AMD defaults i easily beat 700 CPUZ SC though and my core 0 is far from the best.


----------



## PJVol

dk_mic said:


> an observation when revisiting CO and y-cruncher N64 single core


Does it pass the usual multicore test?


----------



## dk_mic

PJVol said:


> Does it pass the usual multicore test?


Need to test. Do you mean at -21 (confirmed single core y-cruncher stable at stock amd powerlimits), or -26 (quick test and seemingly stable with increased powerlimits) or at -30 (stable with SSE p95) ?


----------



## PJVol

@dk_mic
With whatever your daily setup is. The single pass is 2 min long, which is enough for me.


----------



## dk_mic

PJVol said:


> @dk_mic
> With whatever your daily setup is. The single pass is 2 min long, which is enough for me.


so this is the curve and limits i need to pass single core N64 (which at least according to my observation is harder than N32).
I have realized, i can run considerable lower CO values, if i increase limits, probably due to reduced ST boosting.









So right now, I am considering adjusting this to N64 single core stable with extended powerlimits, which should be a cosiderably better curve.
I also like to try to just run -30 all core, which I can bench all day long and see how far i get using that daily..


----------



## KedarWolf

dk_mic said:


> so this is the curve and limits i need to pass single core N64 (which at least according to my observation is harder than N32).
> I have realized, i can run considerable lower CO values, if i increase limits, probably due to reduced ST boosting.
> View attachment 2550599
> 
> 
> So right now, I am considering adjusting this to N64 single core stable with extended powerlimits, which should be a cosiderably better curve.
> I also like to try to just run -30 all core, which I can bench all day long and see how far i get using that daily..


What's your .cfg file for running N64 single-core and test all the cores?


----------



## dk_mic

well for MT its just y-cruncher and then 1-8-16-0
for testing single cores only with N64 using corecycler you gotta modify the script-corecycler.ps1 file and edit this section (can just uncomment)

$configEntries = @(
'{'
' Action : "StressTest"'
' StressTest : {'
' AllocateLocally : "true"'
$coresLine
$memoryLine
' SecondsPerTest : 60'
' SecondsTotal : 0'
' StopOnError : "true"'
' Tests : ['
' "N64"'
' ]'
' }'
'}'
)

otherwise, corecycler settings are obvious,
stressTestProgram = YCRUNCHER
mode = 19-ZN2 ~ Kagari

2 minutes / core is enough for a start to see the worst instabilities. I usually get reboots/whea 18 very soon, if CO is too low


----------



## lafonte

@ManniX-ITA Since you where talking about sorting arrays here a sorting algorithm with of an array of 1000000 random generated numbers sorted with a simple insertion sort algorithm compiled with openmp O3 and zver3 flags









































here the code #include <stdlib.h>#include <omp.h>#define ITEMS 1000000voidsort(int - Pastebin.com


----------



## Blameless

Anyone have any information, anecdotes, test results, magic eight-ball queries, or semi-educated guesses as to the binning differences between Team's new T-create Expert dual-rank B-die kits? They have a 3200 straight 14 @ 1.35v and a 3600 14-15-15 @ 1.45v. Appear to be identical otherwise.

It's been forever since I've used Team memory and I'm not sure how aggressively they bin stuff. If it's not an agressive bin, I may as well save myself 50 bucks and start with the 3200 stuff.


----------



## KedarWolf

Blameless said:


> Anyone have any information, anecdotes, test results, magic eight-ball queries, or semi-educated guesses as to the binning differences between Team's new T-create Expert dual-rank B-die kits? They have a 3200 straight 14 @ 1.35v and a 3600 14-15-15 @ 1.45v. Appear to be identical otherwise.
> 
> It's been forever since I've used Team memory and I'm not sure how aggressively they bin stuff. If it's not an agressive bin, I may as well save myself 50 bucks and start with the 3200 stuff.


Or, you can be like me, only spend $800 CAD on binned Cl14 4000 G.Skill with your tax refund money. I mean doesn't everyone do that? 

Edit: Check out the Corsair b-die CL14 3600 and CL16 4000, they are not too expensive and are supposed to be highly binned.


----------



## Blameless

KedarWolf said:


> Or, you can be like me, only spend $800 CAD on binned Cl14 4000 G.Skill with your tax refund money. I mean doesn't everyone do that?


I don't want to remove all of the mystery...or spend too much on the last hurrah of this platform at this point.



KedarWolf said:


> Edit: Check out the Corsair b-die CL14 3600 and CL16 4000, they are not too expensive and are supposed to be highly binned.


Do you have an exact part number for the 2x16GiB kits?

Edit: CMT32GX4M2Z4000C16?


----------



## KedarWolf

Blameless said:


> I don't want to remove all of the mystery...or spend too much on the last hurrah of this platform at this point.
> 
> 
> 
> Do you have an exact part number for the 2x16GiB kits?


The 4000 is supposed to be higher binned but costs a bit more.

According to the b-die finder website, they ARE b-die. And they might be comparable to like the G.Skill CL14 4000 etc. They don't rate their sticks as aggressively as G.Skill for the CL rating.



https://www.corsair.com/us/en/Categories/Products/Memory/DOMINATOR-PLATINUM-RGB/p/CMT32GX4M2Z3600C14





https://www.corsair.com/us/en/Categories/Products/Memory/DOMINATOR-PLATINUM-RGB/p/CMT32GX4M2Z4000C16


----------



## KedarWolf

Deleted


----------



## Gegu

Thanks to our buddy @Audioboxer on Reddit I've managed to get rock stable 3800mhz CL14 super tighten timings (20 cycles of 1usmus error-free in last run). GDM off, 1T, 1.5V. Now will be attacking stable CL13, I think it's possible on my kit  tRFC is safe, should run without problem around ~230


----------



## Taraquin

Anyone gotten a B2-stepping sample yet? Would be interesting to see ram oc capabilities, changes in voltages etc


----------



## Taraquin

Gegu said:


> Thanks to our buddy @Audioboxer on Reddit I've managed to get rock stable 3800mhz CL14 super tighten timings (20 cycles of 1usmus error-free in last run). GDM off, 1T, 1.5V. Now will be attacking stable CL13, I think it's possible on my kit  tRFC is safe, should run without problem around ~230
> 
> View attachment 2550637


Remember WR=2xRTP and RFC probably works best by being divideable by 16 so try 240 or 256, should perform better than 258. 230 will probably perform same as 240 since they are on same clock cycle, 224 is next step down


----------



## Gegu

Taraquin said:


> Remember WR=2xRTP and RFC probably works best by being divideable by 16 so try 240 or 256, should perform better than 258. 230 will probably perform same as 240 since they are on same clock cycle, 224 is next step down


So TWR will be better at 12? Thanks, good to know 
Will work also with tRFC - thx!


----------



## ManniX-ITA

lafonte said:


> Since you where talking about sorting arrays here a sorting algorithm with of an array of 1000000 random generated numbers sorted with a simple insertion sort algorithm compiled with openmp O3 and zver3 flags


Thanks, this is a nice example.

Your result for 190A is a bit surprising, maybe something in background messed up with the benchmark?
Seems to me it was executed slower and wouldn't make sense.

I did modified a bit the code to compile it with Visual Studio and add print of runtime.
Works either way but in my understanding the calloc parameters should be switched as the array elements should be ITEMS and not sizeof(int).
Unless I got it wrong 



Spoiler: Source






C++:


#include <stdio.h>
#include <stdlib.h>
#include <windows.h>
#include <omp.h>

#define ITEMS 3000000

volatile ULONGLONG dwStart;
volatile ULONGLONG dwEnd;

using namespace std;

void sort(int array[], int size) {

    int k, j;

    for (int i = 1; i < size; i++) {
        k = array[i];
        j = i - 1;
        while (j >= 0 && array[j] > k) {
            array[j + 1] = array[j];
            j = j - 1;
        }
        array[j + 1] = k;
    }
}

int main() {


    int* a, b = 10;
    a = (int*)calloc(ITEMS, sizeof(int));

    if (a == NULL)
        exit(1);

    dwStart = GetTickCount64();

    printf("Start sorting...\n");

    for (int i = 0; i < ITEMS; i++)
        a[i] = rand();

#pragma omp parallel
    sort(a, ITEMS);


    dwEnd = GetTickCount64() - dwStart;
    
    int dwMilliseconds = (int)(dwEnd % 1000);
    dwEnd /= 1000;
    int dwSeconds = (int)(dwEnd % 60);
    dwEnd /= 60;
    int dwMinutes = (int)(dwEnd % 60);
    
    printf_s("For %d items %02d:%02d.%03d\n", ITEMS, dwMinutes, dwSeconds, dwMilliseconds);

    system("pause");

    return 0;
}





If someone else want to compare here's the binary:






BenchOMP.7z







drive.google.com





As expected, something simple like this doesn't go faster or slower with different EDC limits.
The only change in throughput happens when you go too close the actual TDC and therefore triggering hard throttling.
Otherwise the runtime change is always well below the margin of error, about 1 second over 133 seconds.

Before something this simple can get advantage of a higher EDC limit it will be limited by something else.
Being the CPU architecture, thermals, TDC, PPT, etc.

I've tested both with PPT 280W / TDC 160A and PPT 135W / TDC 90A at EDC 210/170/140/110 A.
Despite this workload can max the EDC at about 160A it doesn't go slower with 140 or 110.

A much heavier complex and optimized workload will benefit from higher EDC.
You can't test it on Linux but TM5 is the perfect example.
I guess some heavy code compiling like the Linux kernel should show the same.

TM5 will max as well 160A but once limited to 110A the first cycle will need a whooping 9 seconds more to complete.



Spoiler: 135/90





































Throttling at 80A:














Spoiler: 280/160


----------



## Taraquin

Gegu said:


> So TWR will be better at 12? Thanks, good to know
> Will work also with tRFC - thx!


You can do 5 rtp also


----------



## lafonte

ManniX-ITA said:


> Your result for 190A is a bit surprising, maybe something in background messed up with the benchmark?
> Seems to me it was executed slower and wouldn't make sense.


It may be and also the rand function may affect the results with different runs cause that part is sc and on linux we don't have the preferred core so the kernel may assign that part to a slower core but the point was to show the effective clock difference that in 99% of the cases is a good parameter to evaluate the performance. About the calloc it may be I wrote it without double check everything but should work anyway also if inverted, and I didn't add print function just cause where too many items. Of course we are talking about small regression of 50/100Mhz so differences are minimal also considering that the algorithms don't scale linearly with the clock, but the point is that a performance regression exists and is always reproducible, also the fact that with "low" EDC the 2 ccd have a clock difference to me doesn't make much sense at list if I see the EDC for what it should be, is evident that the EDC act pretty different compared to the ppt and tdc that instead act in a predictable way. About the "optimal" value of EDC I notice that is about if the algorithm use more or less memory, like a memcpy algorithm with a big memory allocation will benefit from a lower EDC the array with that size is kind in a middle ground.


----------



## ManniX-ITA

lafonte said:


> that in 99% of the cases is a good parameter to evaluate the performance


Not really with Ryzen... more 90% of the times 
There are many throttling mechanism and some are probably choking the branching pipeline, the prediction, the caches, etc.
It's very common to get same IOPS with slightly lower effective clocks and also much lower IOPS with higher clocks in case of extreme throttling.
On the 3000 playing with the EDC bug it was quite common the effective clocks would be kept high but IOPS tank down to abysmal values.



lafonte said:


> but the point is that a performance regression exists and is always reproducible, also the fact that with "low" EDC the 2 ccd have a clock difference to me doesn't make much sense


140A is already too low to feed 16 cores, EDC is throttling. At 100A you are too close to TDC.
The low clocks on the 2nd CCD is a normal throttling method for a dual CCD from PBO.



lafonte said:


> if I see the EDC for what it should be, is evident that the EDC act pretty different compared to the ppt and tdc that instead act in a predictable way


I don't know what you think EDC should be, it's not clear to me how to interpret it 
For sure it's not a real "Amperes consumption" metric despite is expressed with this unit.
Otherwise while it's jumping from a steady 100 to 200 Amperes the actual power consumption should double or close to but it isn't.
Seems more to me like a FIT metric which is expressing what the CPU think/senses about the EDC load.


----------



## lafonte

ManniX-ITA said:


> On the 3000 playing with the EDC bug it was quite common the effective clocks would be kept high but IOPS tank down to abysmal values


My 3700x with EDC bug was always performing better compared to other pbo settings in real world workloads



ManniX-ITA said:


> The low clocks on the 2nd CCD is a normal throttling method for a dual CCD from PBO.


 It's not really throttling cause the clock of the first ccd is higher, looks more like an imbalance between the ccd I don't know if I balance the ccd with co the problem is that the SMU as little no no documentation and on linux is really difficult balance the ccd cause I don't have a way to access to the core ranking.



ManniX-ITA said:


> I don't know what you think EDC should be, it's not clear to me how to interpret it


It should do what it's name means. And actually to be truthfully with you I don't even know why at AMD they decided to expose 3 parameters when probably a simple programmable package power limit was much more simple predictable and we weren't here trying to understand why pbo works this way or at least give to the CPUs appropriate stock power limit instead to produce an 8 cores with the same limits of a 16 cores . Anyway we agree somehow in one thing since you said that it is not a real current consumption.


----------



## ManniX-ITA

lafonte said:


> My 3700x with EDC bug was always performing better compared to other pbo settings in real world workloads


Yes my 3800X as well, with the correct setup 
But playing with the settings, vcore offset, LLC, EDC values not optimal, you could re-create this condition



lafonte said:


> It's not really throttling cause the clock of the first ccd is higher, looks more like an imbalance between the ccd I don't know if I balance the ccd with co the problem is that the SMU as little no no documentation and on linux is really difficult balance the ccd cause I don't have a way to access to the core ranking.


It's a throttling method from PBO, it will favor the first CCD when throttling. Does the same on Windows as well.



lafonte said:


> It should do what it's name means. And actually to be truthfully with you I don't even know why at AMD they decided to expose 3 parameters when probably a simple programmable package power limit was much more simple predictable and we weren't here trying to understand why pbo works this way or at least give to the CPUs appropriate stock power limit instead to produce an 8 cores with the same limits of a 16 cores . Anyway we agree somehow in one thing since you said that it is not a real current consumption.


I don't complain too much, it's a way to give control over PBO.
It's better to have 3 knobs than only one


----------



## ManniX-ITA

I may be able soon to test again with the 5950X 
Just got this:

_ Your return AMD product has successfully passed the inspection and your
replacement product is now approved.

Please expect a follow up email shortly confirming your replacement
product shipment._


----------



## PJVol

lafonte said:


> It should do what it's name means. And actually to be truthfully with you I don't even know why at AMD they decided to expose 3 parameters when probably a simple programmable package power limit was much more simple predictable and we weren't here trying to understand why pbo works this way or at least give to the CPUs appropriate stock power limit instead to produce an 8 cores with the same limits of a 16 cores . Anyway we agree somehow in one thing since you said that it is not a real current consumption.


One package limit is not enough to extract more performance in a certain scenarios. Take a look at this patent, it very likely has answers on all your questions.
Particularly, FIG.3 illustrating the weakness of the typical limiter approach.


----------



## lafonte

PJVol said:


> One package limit is not enough to extract more performance in a certain scenarios. Take a look at this patent, it very likely has answers on all your questions.
> Particularly, FIG.3 illustrating the weakness of the typical limiter approach.


I cannot see the patent you're referring to, anyway if an epic CPU can have just a package limit that is a server CPU where in some cases really it has to run the same workload continually I still thinking that for a consumer pc with a mixed workload a package limit will be enough if well implement, at times less is more I'm a Mies Van Der Rohe fan , with the EDC bug must likely the boost algorithm was working without considering a parameter and the CPU was performing even better in all the workloads, was running out of spec? I don't know, pbo after all is already doing so, the system was rock stable and I didn't see any performance degradation after more than one year of use, after of course I have a mixed use of my pc since the most demanding think I do with it is compiling, at times for 10h straight I prioritize that workload and if all I can do is tune pbo for that workload, that is the only tool I've got that I use. (I know there is also a static overclock but is just not convenient since I want an always stable system)


----------



## mike7877

Luggage said:


> Ryzen dynamic boost, vcore and core allocation (PBO) is very different than how intel works though, it's more like GPU OC for 6-8-12-16 GPUs/cores but the curves are hidden, temperature bin steps are alluded at and power limits are more like suggestions.


I assumed he was going for a constant overclock - no boost, just a steady, high clock rate. And if he was going to use boost, I thought he'd use the voltage - it'd still be the safest long term voltage for his overclock. I didn't state that clearly though. After typing all the directions and reasoning, I lost steam. So much misdirected work on my part... Anyway - I do think the method I described should work for AMD processors too. I'm not very versed with AMD's stuff, but I do have a 3700x which I've tweaked a bit. I didn't get a great chip though, so I haven't spent a lot of time.

Are you saying AMD platforms don't follow the power limits you set in the BIOS?

What I did with my 3700x is I doubled its TDP and set the clock to 4.35GHz. The hidden curves you speak of is a big part of the reason. And not being able to change my base clock from 3.6GHz to something like 4 or 4.1GHz. 
My chip would boost higher, but 4.35 performs better : during daily tasks, the time it takes for the chip to boost takes more away than the extra 100mhz during boost gives. And the average clock rate of the chip under multi-threaded loads is always 4.35GHz, not 4.05-4.15 or lower. Right now I just have the stock cooler, but even when the chip is dissipating 130 watts it hovers in the high 80s/low90s. All my real workloads are 80-95 watts and the chip stays low to mid 70s


----------



## PJVol

lafonte said:


> I cannot see the patent you're referring to


Sorry, forgot to add a link. Here it is





US20190146567A1 - Processor throttling based on accumulated combined current measurements - Google Patents


A processor is throttled based on accumulated combined current measurements from a plurality of processor cores. The processor monitors activity current levels at each processor core, either directly or indirectly by monitoring specified events at the processor cores. The processor combines...



patents.google.com




TLDR; EDC is refered to as combined activity current (CCV) herein, which depends on switching activity capacitance (Cac) and its frequency (F).


Also very informative and useful reading on this topic:
ch. 5. Trends in Low-Power VLSI Design" from the "VLSI Systems. Electrical Engineering Handbook (Ed. WAI-KAI CHEN )"


----------



## ManniX-ITA

LoL, about the topic "do I need to test AVX2 for stability?"...










Even an RGB control software is using AVX2 instructions


----------



## Blameless

500MB for RGB control software. That's like the size of _Daggerfall_.


----------



## ManniX-ITA

Blameless said:


> 500MB for RGB control software. That's like the size of _Daggerfall_.


It's not a native application unfortunately, it's using node.js


----------



## Audioboxer

Gegu said:


> Thanks to our buddy @Audioboxer on Reddit I've managed to get rock stable 3800mhz CL14 super tighten timings (20 cycles of 1usmus error-free in last run). GDM off, 1T, 1.5V. Now will be attacking stable CL13, I think it's possible on my kit  tRFC is safe, should run without problem around ~230
> 
> View attachment 2550637


Unless you are going to give tCL13 a go again (do this absolute last, stick with tCL14 for now for thermals) I'd put tCWL to 14 and put tRDWR on AUTO. It will likely train at 8.

tWRRD on AUTO as well, it will likely jump between 2 and 3 depending on rest of the timings.

tRTP will probably go to 5 as well.

tRP might be OK at 12.

tRAS can come down lower, try 24.

tRC = tRAS + tRP. If you can get tRP stable at 12 this will mean 36.

ProcODT shouldn't need to be as high as 40, aim for 34.3/36.9 for now. This bin has every chance at going as low as 28.2 at 3800, though your motherboard traces/DIMM setup might come into play trying to go this low.

CCD/IOD I guess I wouldn't worry about for now, but they can likely be lowered after you work some more on timings.


----------



## Gegu

Taraquin said:


> Remember WR=2xRTP and RFC probably works best by being divideable by 16 so try 240 or 256, should perform better than 258. 230 will probably perform same as 240 since they are on same clock cycle, 224 is next step down


I've changed TWR to 12 and tRFC to 240 - made TM5 1 hour run - error free  probably lower tRFC will be still possible, already got Corsair ram cooler so temps are fine (39-40C during TM5 run)


----------



## Gegu

Audioboxer said:


> Unless you are going to give tCL13 a go again (do this absolute last, stick with tCL14 for now for thermals) I'd put tCWL to 14 and put tRDWR on AUTO. It will likely train at 8.
> 
> tWRRD on AUTO as well, it will likely jump between 2 and 3 depending on rest of the timings.
> 
> tRTP will probably go to 5 as well.
> 
> tRP might be OK at 12.
> 
> tRAS can come down lower, try 24.
> 
> tRC = tRAS + tRP. If you can get tRP stable at 12 this will mean 36.
> 
> ProcODT shouldn't need to be as high as 40, aim for 34.3/36.9 for now. This bin has every chance at going as low as 28.2 at 3800, though your motherboard traces/DIMM setup might come into play trying to go this low.
> 
> CCD/IOD I guess I wouldn't worry about for now, but they can likely be lowered after you work some more on timings.


ProcODT 36.9 or 34.3 was causing me some instability. TRTP 5 I think did too, but I need to check that again along with TWR 10 on current settings.


----------



## DeepOcean

This seems to be my final stable result, don't know if I can tickle something out of it. Any ideas? tRCD seems a bit clunky. Bandwith is low cause I disabled BGS alt, but i think it makes the system quite a bit snappier, also in games.


----------



## Taraquin

DeepOcean said:


> This seems to be my final stable result, don't know if I can tickle something out of it. Any ideas? tRCD seems a bit clunky. Bandwith is low cause I disabled BGS alt, but i think it makes the system quite a bit snappier, also in games.


1.5v ram? 
Suggestion: Try 15 15 14 30 44 maybe easier to run than 14 16 14 and should give very similar performance
Rtp 7
Rfc 304, 288, 272, 256. If you are at 1.5v maybe 256 or 240 can work.


----------



## DeepOcean

Taraquin said:


> 1.5v ram?
> Suggestion: Try 15 15 14 30 44 maybe easier to run than 14 16 14 and should give very similar performance
> Rtp 7
> Rfc 304, 288, 272, 256. If you are at 1.5v maybe 256 or 240 can work.


it's 1.53V, below unstable. Testing that now! It's mixed kits btw., maybe that's part of the struggle.. same serial tho


----------



## Gegu

Audioboxer said:


> Unless you are going to give tCL13 a go again (do this absolute last, stick with tCL14 for now for thermals) I'd put tCWL to 14 and put tRDWR on AUTO. It will likely train at 8.
> 
> tWRRD on AUTO as well, it will likely jump between 2 and 3 depending on rest of the timings.
> 
> tRTP will probably go to 5 as well.
> 
> tRP might be OK at 12.
> 
> tRAS can come down lower, try 24.
> 
> tRC = tRAS + tRP. If you can get tRP stable at 12 this will mean 36.
> 
> ProcODT shouldn't need to be as high as 40, aim for 34.3/36.9 for now. This bin has every chance at going as low as 28.2 at 3800, though your motherboard traces/DIMM setup might come into play trying to go this low.
> 
> CCD/IOD I guess I wouldn't worry about for now, but they can likely be lowered after you work some more on timings.


I've tested TRTP 5 and TWR 10 on my actual settings mate and after 1.2hour 12 TM5 runs it's fkn stable - finally  these ProcODT and Addr adjustments are good.

Once on Reddit I tried tRDWR on auto (but without changing TCWL at the same time) and it set me to 18. I guess it can't be below 10 because the computer won't boot. But I will check along with TCWL. And tell me, isn't it sometimes the case that too low a TRAS/TRC causes a performance degradation?


----------



## kim nk

Hello, 3800 cl13 seems to show that tfaw 16 is possible at the timing of 13-13-12-26-38.










Usually, TPHYRDL 24 sections at this point, but the mainboard performance is not good, resulting in memory voltage loss and various performance constraints. For this reason, the importance of the mainboard is once again the point of feeling the need for the latest board dark hero, away from the really old X570. I feel more when I reduce timing at the higher clocks, not just at this point, but also at the higher clocks, where the memory voltage difference is about 0.1V










The first picture is the impact board and the second picture is the same kit when it is Unifi x. Only the cpu board is different. The difference between memory voltage and 1t and 2t x570 spherical board is really bad.



















Look at the memory voltage difference and TPHYRDL. The board difference is too severe. The memory kit has no yield difference and is wrong.


----------



## Audioboxer

kim nk said:


> Hello, 3800 cl13 seems to show that tfaw 16 is possible at the timing of 13-13-12-26-38.
> View attachment 2550857
> 
> 
> 
> Usually, TPHYRDL 24 sections at this point, but the mainboard performance is not good, resulting in memory voltage loss and various performance constraints. For this reason, the importance of the mainboard is once again the point of feeling the need for the latest board dark hero, away from the really old X570. I feel more when I reduce timing at the higher clocks, not just at this point, but also at the higher clocks, where the memory voltage difference is about 0.1V
> 
> View attachment 2550858
> 
> 
> The first picture is the impact board and the second picture is the same kit when it is Unifi x. Only the cpu board is different. The difference between memory voltage and 1t and 2t x570 spherical board is really bad.
> 
> View attachment 2550859
> 
> 
> View attachment 2550860
> 
> 
> Look at the memory voltage difference and TPHYRDL. The board difference is too severe. The memory kit has no yield difference and is wrong.


TPHYRDL 24 at 3800? What is this black magic?!

Someone needs to provide you a DR kit with your CPU/mobo combo so you can try tRCDRD 13 at 3800 










On DR it's just all over the place. Here I managed to squeak through 1 cycle with a single error on 13. Timings and resistances are a bit of a mess, but it's very difficult to calculate what actually helps or makes a difference on 2T/3800. It's soo sensitive to tRCDRD 13. Common errors being 0/2/6 very quickly.

Even getting through a single cycle with only 1 error with tRCDRD 13, 3800 and DR is a hell of a challenge.


----------



## kim nk

Audioboxer said:


> TPHYRDL 24 at 3800? What is this black magic?!
> 
> Someone needs to provide you a DR kit with your CPU/mobo combo so you can try tRCDRD 13 at 3800


The difference is the main board. From the TRFC-224 point, the dark hero main board shows TPHYRDL 24.
Another example.


----------



## kim nk

The UniFy x motherboard tested the point of stretching to TPHYRDL 28 when 16 giga and 32 gigabytes were used. When TPHYRDL26 1T is 2T, TPHYRDL28 This is the same point where 8X2=16 giga, 16X2=32 giga, and TPHYRDL is 28. Usually, the TPHYRDL limit point of the mainboard is changed from 2T to 1T at 4000 point of CL14 to TPHYRDL26->28.



























In conclusion, TPHYRDL26 REAL1T needs to be replaced with a better board than UniFi X. DARK HERO..


----------



## Audioboxer

kim nk said:


> The UniFy x motherboard tested the point of stretching to TPHYRDL 28 when 16 giga and 32 gigabytes were used. When TPHYRDL26 1T is 2T, TPHYRDL28 This is the same point where 8X2=16 giga, 16X2=32 giga, and TPHYRDL is 28. Usually, the TPHYRDL limit point of the mainboard is changed from 2T to 1T at 4000 point of CL14 to TPHYRDL26->28.
> 
> View attachment 2551067
> 
> 
> View attachment 2551064
> 
> View attachment 2551065
> 
> 
> In conclusion, TPHYRDL26 REAL1T needs to be replaced with a better board than UniFi X. DARK HERO..


MSI seem to have really weird behaviour with tPHYRDL and 1T/2T, noticed it early with my B550 UnifyX.

1T tCL13 3800 will run 26/26.
1T tCL14 3800 will run 28/28.


----------



## ManniX-ITA

kim nk said:


> In conclusion, TPHYRDL26 REAL1T needs to be replaced with a better board than UniFi X. DARK HERO..


Do you mean the Dark Hero can run 4000 CL14 with 1T Setup Times at PHYRDL 26?
Or that it can run it without Setup Times?

I've seen mixed opinions on how good or bad is the Dark Hero on memory OC, do you think it's good?


----------



## kim nk

ManniX-ITA said:


> Do you mean the Dark Hero can run 4000 CL14 with 1T Setup Times at PHYRDL 26?
> Or that it can run it without Setup Times?
> 
> I've seen mixed opinions on how good or bad is the Dark Hero on memory OC, do you think it's good?


Yes, I see that. UniFY X limit is TPHYRDL 26 when 2T is performed at 4000CL14, but 1T is just the Maji route point where TPHYRDL 28 is changed. Dark Hero Board is better than Unipy X at this TPHYRDL 26 point.


















This point is the latency of TPHYRDL 281T and TPHYRDL 26 2T. On average, if you change 2T to a dark hero board from 50.3NS to 50.6NS, you will get TPHYRDL26, which is a constant 50.3NS 1T.


----------



## Mach3.2

Seem like it's an MSI thing;
odd tCL + 1T = tPHYRDL 26/26
even tCL + 1T = tPHYRDL 26/28 or 28/28(?)

odd tCL + 2T = tPHYRDL 26/28 or 28/28(?)
even tCL + 2T = tPHYRDL 26/26


----------



## QyXyy

hi all , my config is
R7 1700 Pro 2017 batch , 3.9 SMT OFF @ 1.42Vcore LinX stable
Samsung CTD-TB1 T-Die(OEM GREEN PCB 2666 CL19) 8x2 (Dual Rank)
b450 S2H gigabyte Bios F50
Win10 21h2
on current config it passes: absolut,extreme1,1usmus(Tm5) , RunMemTestPro 2.5 , 3000% Coverage , all with GPU miner(70c card) for ram heat, ram with hyperx heatsinks and fan on it
voltage is 1.43VDiMM
how can i get stable 3466 clock on this setup, any suggestions?








P.S. i already tried 3466 with 16-20-38-1T timings, and its pasess tm5 absolut, but then i start this test again ,and its gives me some errors on 35min.
this ram can do: 3466 16-20-20-20-38-1T (intel)
3733 17-22-22-41-2T(intel) too


----------



## Audioboxer

Finally, that only took like a year and 5 months lol.

Fun and games begins now though, I got my waterblock in and realised the 3080 is bigger than the 2080Ti in both height and width. Going to have to redo my loop. Might even be forced to do the card horizontally rather than vertically if I want to keep my rear radiator.


----------



## Audioboxer

MSI still haven't released 1.2.0.6b for most of their boards and 1.2.0.7 is already on the way to fix yet more AMD bios jank



https://www.tomshardware.com/news/amd-issues-fix-and-workaround-for-ftpm-stuttering-issues


----------



## Boofeyblitz

Audioboxer said:


> View attachment 2551156
> 
> 
> Finally, that only took like a year and 5 months lol.
> 
> Fun and games begins now though, I got my waterblock in and realised the 3080 is bigger than the 2080Ti in both height and width. Going to have to redo my loop. Might even be forced to do the card horizontally rather than vertically if I want to keep my rear radiator.


Congrats!!! It took me about 6 months after the 3080 came out to get mine.


----------



## ManniX-ITA

Well, I've just sent an RMA request to send back the new 5950X that I got back from RMA...

B2 stepping BG 2201 SUS.

Pretty awful binning, was almost decent with CO tuning.
But the best Core 3 is also faulty.
Fails P95 SSE at 0 CO.
Started failing at -10, then -6,-4,-2, now at 0.
And I was still trying with only FFT 720-720.

@PJVol 
This one was showing pretty easily the OCCT bug.
Just switching from one core to the other in ST the clock from steady 4825 MHz was jumping to 4925-4975 MHz.


----------



## domdtxdissar

ManniX-ITA said:


> Well, I've just sent an RMA request to send back the new 5950X that I got back from RMA...
> 
> B2 stepping BG 2201 SUS.
> 
> Pretty awful binning, was almost decent with CO tuning.
> But the best Core 3 is also faulty.
> Fails P95 SSE at 0 CO.
> Started failing at -10, then -6,-4,-2, now at 0.
> And I was still trying with only FFT 720-720.
> 
> @PJVol
> This one was showing pretty easily the OCCT bug.
> Just switching from one core to the other in ST the clock from steady 4825 MHz was jumping to 4925-4975 MHz.


Can you run 2000:4000 without reduced performance on this cpu with your motherboard/memory combo, or was your last (first) 5950x one of a kind in this regard ?


----------



## ManniX-ITA

domdtxdissar said:


> Can you run 2000:4000 without reduced performance on this cpu, or was your last 5950x one of a kind ?


With my old settings y-c pi was taking over 75 seconds even with CLKREQ#, very similar to yours.
But unlikely yours this one is very voltage hungry.
Upped VDD18 (1.940V+ don't remember exactly) and got it back to 65s.

Unfortunately useless effort


----------



## Audioboxer

Boofeyblitz said:


> Congrats!!! It took me about 6 months after the 3080 came out to get mine.


The EU queue was totally neglected compared to America lol, waiting times of over 1 year are normal here. It's starting to pick up a little though.

Coming from a 2080Ti I'm not going to get big gains, though a little bump in performance with RT will be nice seeing as it still murders a 2080Ti.

11GB to 10GB is unlikely to make a difference, especially at 1440p, though the original 3080 should probably still have launched with 12GB.


----------



## Taraquin

ManniX-ITA said:


> Well, I've just sent an RMA request to send back the new 5950X that I got back from RMA...
> 
> B2 stepping BG 2201 SUS.
> 
> Pretty awful binning, was almost decent with CO tuning.
> But the best Core 3 is also faulty.
> Fails P95 SSE at 0 CO.
> Started failing at -10, then -6,-4,-2, now at 0.
> And I was still trying with only FFT 720-720.
> 
> @PJVol
> This one was showing pretty easily the OCCT bug.
> Just switching from one core to the other in ST the clock from steady 4825 MHz was jumping to 4925-4975 MHz.


Too bad :/ Still whea19 above 1900fclk?


----------



## ManniX-ITA

Taraquin said:


> Too bad :/ Still whea19 above 1900fclk?


Still WHEA at FCLK 2000, bit less than B0. But different settings.
Didn't check at FCLK 1933 which was running very smooth.


----------



## Audioboxer

I'm not saying it's not possible, but I've yet to see anyone actually post proof they have ZERO WHEA at 2000 FCLK on something like a 5900x/5950x.

I guess a secondary challenge in today's internet world is being able to disable WHEA spam for screenshots.

I understand you CAN stabilise higher FCLK even with some WHEA, but that's a different discussion than actually have no WHEA errors at all at something like 2000 FCLK.


----------



## kim nk

Audioboxer said:


> I'm not saying it's not possible, but I've yet to see anyone actually post proof they have ZERO WHEA at 2000 FCLK on something like a 5900x/5950x.
> 
> I guess a secondary challenge in today's internet world is being able to disable WHEA spam for screenshots.
> 
> I understand you CAN stabilise higher FCLK even with some WHEA, but that's a different discussion than actually have no WHEA errors at all at something like 2000 FCLK.


I think I saw only one in b0



































5900x 4200mhz 2t 오버 해봤습니다


클릭하시면 크게 보실수 있습니다연휴라서 시간이 나서 한번 시도해보았습니다whea 에러는 기본 1.8v에서도 …




quasarzone.com


----------



## Audioboxer

kim nk said:


> I think I saw only one in b0
> View attachment 2551273
> 
> View attachment 2551275
> 
> 
> 
> View attachment 2551276
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 5900x 4200mhz 2t 오버 해봤습니다
> 
> 
> 클릭하시면 크게 보실수 있습니다연휴라서 시간이 나서 한번 시도해보았습니다whea 에러는 기본 1.8v에서도 …
> 
> 
> 
> 
> quasarzone.com


Nice, at 2100 though I'd just have to take it in good faith WHEA reporting isn't turned off, because if you do turn it off HWINFO will report 0.

I can pass TM5 fine even with WHEA errors.


----------



## ManniX-ITA

Audioboxer said:


> Nice, at 2100 though I'd just have to take it in good faith WHEA reporting isn't turned off, because if you do turn it off HWINFO will report 0.
> 
> I can pass TM5 fine even with WHEA errors.


You don't even have to turn it off if you install Win 10 b1935 and upgrade from that. It will not install the error sources and will never be added.

It's just nice to know if and how many WHEA 19 are dropped at high FCLK but it's a completely useless information regarding reliability or performances.
Doesn't make sense to "ask" for it with FCLK 1900+.

If there are WHEA 19 at FCLK 1900 and below there's something wrong.
Above 1900 it's usually just by chance that they are not reported.

And even in the very few cases where they are not reported doesn't mean there aren't hidden reliability issues or performance degradation.
You just need to check yourself by other means because WHEA 19s are not usable in that context.
Trusting all is good at 1900+ because you don't get WHEA 19s isn't a good idea.

And you can have 100% reliability and performance uplift even with tons of WHEA 19s in the background.


----------



## Bloax

> And you can have 100% reliability and performance uplift even with tons of WHEA 19s in the background.


All I can say in regards to this is that fabric errors from incorrect SOC/IOD/CCD voltages would manifest themselves on a WHEA-non-reporting board as Interrupt to Process (or any of the others) latency spikes in LatencyMon.

If _any_ correction is for some reason reported as WHEA 19 regardless of size - then that would explain this behaviour.
As the spikes were +30 microseconds, +90 microseconds, +250 microseconds, +500 microseconds, +1500 microseconds .. :- )
If you get ****loads of +30 microseconds, that's not a big deal compared to getting less numerous - but still constant >= +500 spikes.


----------



## ManniX-ITA

Bloax said:


> All I can say in regards to this is that fabric errors from incorrect SOC/IOD/CCD voltages would manifest themselves on a WHEA-non-reporting board as Interrupt to Process (or any of the others) latency spikes in LatencyMon.


It's another way to spot reliability issues but it's not exhaustive.
Very often at idle or low load everything looks good but then under full load performance regression or instabilities can come out.
In this case checking IPC latency doesn't help. 

Since I was messing with settings anyway I took some screenshots.
There's no sensible difference in Latencymon running FCLK 1900 or FCLK 2000 with performance regression or not.



Spoiler: FCLK 1900

















Spoiler: FCLK 2000 BAD

















Spoiler: FCLK 2000 GOOD















The only reliable method to test is comparing y-cruncher Pi-2.5b time and the xmr-stak-rx miner hashrate.
If you get better results in both, you can be pretty sure there's no issue.

@domdtxdissar 

Considering the B2 stepping only works properly with newer AGESA releases seems AMD actively killed running over FCLK 1900 with the new CPUs.
I have tested it with AGESA 1.2.0.5 and there's no way to run it reliably even at FCLK 1933.
My old B0 stepping was working at FCLK 2000 also on AGESA 1.2.0.5.
Odds they'll go back with this "nerfing" in the future are probably close to none.


----------



## Bloax

ManniX-ITA said:


> There's no sensible difference in Latencymon running FCLK 1900 or FCLK 2000 with performance regression or not.
> 
> ...
> Odds they'll go back with this "nerfing" in the future are probably close to none.


It is indeed making prophecies out of cow dung :- )
In this case, the 2000 GOOD reveals that it _may be_ better through a lower maximum observed latency.

However, if 2.5 billion digits of Pi do the work faster and more reliably - that is good!


as for the performance nerfings...
_well, how else are we supposed to make Zen 4 look as good as possible???????
upgrade now pay piggy!!!_


----------



## ManniX-ITA

Bloax said:


> In this case, the 2000 GOOD reveals that it _may be_ better through a lower maximum observed latency.


If there's something really wrong you can see it with latency spikes, but if it's subtle... good luck 



Bloax said:


> However, if 2.5 billion digits of Pi do the work faster and more reliably - that is good!


That and the miner, in some cases it's not enough to get a good Pi result.
With this B2 I can get a better score on Pi but awful hashrate with the miner if VDD18 is not enough.



Bloax said:


> as for the performance nerfings...
> _well, how else are we supposed to make Zen 4 look as good as possible???????
> upgrade now pay piggy!!!_[/I]


Yeah... what else to say?
We are lucky if in another year they fix something, just something.
All hands on deck to make more money with the new puppy, the old one was already obsolete 6 months ago.
I'm pissed that the 5000 is not a big arch revolution compared to the 3000 and yet after almost 1 year and a half it's still not mature.
At least Alder Lake is really a major arch change, big.LITTLE, DDR5 & so on.
In that case I can understand more the early adopters issues.


----------



## TimeDrapery

I'm revisiting my memory OC on my AORUS B550i / 5600X desktop PC running an older set of two (2) G.SKILL DIMMs...

The quick (1× cycle / 1000%) TM5 revealed no errors but MemTest is showing that I'm all jacked up

OCCT Pro has been running the Memory test with AVX2 instructions for two hours now without error... Most of the time I've seen that if I throw errors in the other two tests then OCCT Pro will throw an error within a minute of the test starting

Weird 😂😂😂😂😂


----------



## Taraquin

ManniX-ITA said:


> It's another way to spot reliability issues but it's not exhaustive.
> Very often at idle or low load everything looks good but then under full load performance regression or instabilities can come out.
> In this case checking IPC latency doesn't help.
> 
> Since I was messing with settings anyway I took some screenshots.
> There's no sensible difference in Latencymon running FCLK 1900 or FCLK 2000 with performance regression or not.
> 
> 
> 
> Spoiler: FCLK 1900
> 
> 
> 
> 
> View attachment 2551293
> 
> 
> 
> 
> 
> 
> Spoiler: FCLK 2000 BAD
> 
> 
> 
> 
> View attachment 2551294
> 
> 
> 
> 
> 
> 
> Spoiler: FCLK 2000 GOOD
> 
> 
> 
> 
> View attachment 2551295
> 
> 
> 
> 
> The only reliable method to test is comparing y-cruncher Pi-2.5b time and the xmr-stak-rx miner hashrate.
> If you get better results in both, you can be pretty sure there's no issue.
> 
> @domdtxdissar
> 
> Considering the B2 stepping only works properly with newer AGESA releases seems AMD actively killed running over FCLK 1900 with the new CPUs.
> I have tested it with AGESA 1.2.0.5 and there's no way to run it reliably even at FCLK 1933.
> My old B0 stepping was working at FCLK 2000 also on AGESA 1.2.0.5.
> Odds they'll go back with this "nerfing" in the future are probably close to none.


Not possible to use 1.2.0.3b/c on B2? I somewhat disagree with you on how to find a nerf for not. Before I upped VDD18 from 1.8 to 1.88v I got 1-2% regression in y-cruncher/linpack at 4000cl16 vs 3800cl15, but SOTTR was still 2% faster, dram calc test also. After raising VDD18 perf in y-cruncher/linpack was equal, but dram calc/SOTTR is now 3% faster vs 3800cl15. If you mainly game etc then you might get better perf even if heavy use is impaired


----------



## ManniX-ITA

Taraquin said:


> Not possible to use 1.2.0.3b/c on B2? I somewhat disagree with you on how to find a nerf for not. Before I upped VDD18 from 1.8 to 1.88v I got 1-2% regression in y-cruncher/linpack at 4000cl16 vs 3800cl15, but SOTTR was still 2% faster, dram calc test also. After raising VDD18 perf in y-cruncher/linpack was equal, but dram calc/SOTTR is now 3% faster vs 3800cl15. If you mainly game etc then you might get better perf even if heavy use is impaired


It's possible to use earlier AGESAs but it's known to cause issues/degraded performances.
I have some weird issues with LLC and ST/MT scores but I'm not sure if it's cause AGESA or this sample just faulty.

Yes of course you could find the nerfing acceptable if you have specific use cases.
But if you want it running full speed whatever you need to do, just like my old B0, it seems impossible.
Also I didn't test much with 1.2.0.5 but even 1933 MHz was running terribly.
Not sure the B2 with newer AGESAs will be able to keep up even only with gaming at high FCLK.


----------



## Taraquin

ManniX-ITA said:


> It's possible to use earlier AGESAs but it's known to cause issues/degraded performances.
> I have some weird issues with LLC and ST/MT scores but I'm not sure if it's cause AGESA or this sample just faulty.
> 
> Yes of course you could find the nerfing acceptable if you have specific use cases.
> But if you want it running full speed whatever you need to do, just like my old B0, it seems impossible.
> Also I didn't test much with 1.2.0.5 but even 1933 MHz was running terribly.
> Not sure the B2 with newer AGESAs will be able to keep up even only with gaming at high FCLK.


Okay. Too bad B2 didn't improve ram performance, atleast on 2 ccds. Read that some single ccds B2 running 2000fclk+ apparently without problems, but until someone here posts results I'm not too optimistic.


----------



## ManniX-ITA

Taraquin said:


> Okay. Too bad B2 didn't improve ram performance, atleast on 2 ccds. Read that some single ccds B2 running 2000fclk+ apparently without problems, but until someone here posts results I'm not too optimistic.


I bought a 5800X for the RMA, which I have now to put it back, and works really nicely at FCLK 2000.
Drops WHEA of course but seems to work absolutely fine.
Quite a boss, boosting like hell with almost all cores maxing 5050 MHz and sustained 5000 MHz.


----------



## Audioboxer

Audioboxer said:


> Spot on, drop the IOD and we're all good
> 
> View attachment 2547494





Audioboxer said:


> View attachment 2547524
> 
> 
> All good, has me wondering though if I should try my CCD a bit lower, like 0.95v...


So yesterday I had a fair bit of paperwork to do so I thought I'd stick a TM5 run on for old times sake and to my absolute shock an error on 14 popped up some time around 1 hour 40 minutes and 2 hours 10 minutes with the settings above.










So, powerdown most likely.










So I stuck AddrCmdDrvStr to 24 and that passed first time. But I think I'll need to do a 50 hour TM5 again and see what comes up.

Been running the PC for like a month now with these timings (20 on AddrCmdDrvStr) and no crashes or anything.

Can powerdown issues be that hard to tease out they can survive hours of testing until... they can't?


----------



## Blameless

Bloax said:


> The most important metric isn't whether it's stable in y-cruncher or prime95, but whether it's perfectly stable in what you're actually going to be running for many hours.


If the only things one does are tolerant of errors (meaning the odd error here or there doesn't change one's experience and has no meaningful adverse consequences) that's one thing, but it's essentially impossible to evaluate low error rates in any reasonable period of time, without tests that are considerably more likely to fail than what you're actually going to be running.

A 1% chance of a single bit flip per hour would be considered a phenomenally high and utterly unacceptable error rate in some settings, but could easily result in dozens or even hundred of hours between errors. If I have something that I can expect to load one of my systems for a week straight, I'd need many months of error free operation to have reasonable confidence that it wouldn't throw an error the next time I ran it for a week...or I can just use tests I know are likely to prompt errors much sooner and achieve the same level of confidence in a few days.



domdtxdissar said:


> While i 100% understand where your coming from, the drawback is that you leave performance left on the table for "6.99 months" to have stability in that 1 program you use one time each 7 months..


A tiny amount of lost performance goes largely unnoticed outside of benchmarks, but any error can potentially require a project be started from scratch, or silently corrupt data that can take enormous effort to fix. There is a lot of stuff I do on my systems that are utterly intolerant of errors. Even if I don't notice them at the time (most errors don't cause crashes, but it would much better if they did), it could call into question the validity of data years down the line.

This is why I'm always looking for better tests (ones that fail sooner, at lower speeds), because I do want as much performance as I can get, but not at the cost of errors. And since I don't really trust stock to be error free (a significant fraction of stock systems I test will fail) I may as well try to get all the performance I can out of any given system, because I'm going to test the snot out of it before I use it for anything important anyway.



Audioboxer said:


> Quite clear testing should be done with BOTH P95 *and* ycruncher.


Currently, my go to tests are OCCT, y-cruncher, Prime 95 (via core cycler and independently), ADIA64's memory stress test (which will fail immediately where almost no other test will on some systems, while never failing even on other very flaky systems), and TM5 (usually with a customized 1usmus profile). Every one of these tests will find errors all the others I likely to miss, or take prohibitively long to find. I also tend to do a few runs of Memtest86 (tests 6,7, and 8), and a bit of Prime95 and/or stressapptest from Linux before booting into Windows and doing more comprehensive testing.

Have to do combination testing as well, with some GPU and I/O heavy loads thrown into the mix to make sure worst case power and temperature scenarios don't hurt stability. If I know the GPU itself is stable, custom FurMark to target just below the power limits I have set will droop the +12v rail, throw some transients back into the PSU, and dump a lot of heat into the case.

Since the boost curves are highly temperature dependent, I've also made it a habit to run abbreviated tests at the absolute lowest (5-10C) and highest (~40C) ambient temps I expect my systems to see. Warmer is usually fine as long as memory temperature doesn't get too critical, but cold will often reveal sketchy CO or boost override values pretty quickly due to overboosting.


----------



## Bloax

Blameless said:


> If the only things one does are tolerant of errors (meaning the odd error here or there doesn't change one's experience and has no meaningful adverse consequences) that's one thing, but it's essentially impossible to evaluate low error rates in any reasonable period of time, without tests that are considerably more likely to fail than what you're actually going to be running.
> 
> A 1% chance of a single bit flip per hour would be considered a phenomenally high and utterly unacceptable error rate in some settings, but could easily result in dozens or even hundred of hours between errors. If I have something that I can expect to load one of my systems for a week straight, I'd need many months of error free operation to have reasonable confidence that it wouldn't throw an error the next time I ran it for a week...or I can just use tests I know are likely to prompt errors much sooner and achieve the same level of confidence in a few days.


Memory, and all kinds of overclocking in general, gets considerably hazier once you go well over 24 hours of stable operation.

I do not speak of that scenario at all - I speak of not getting lost in _passing all the tests_ when the Big Test is the Practical Application of the overclock in question.
If the Practical Application is doing heavy computations for 480+ hours on with 0.00% error tolerance, then you're really in the wrong branch of business doing non-ECC RAM OC.
:- )

Whereas I can tell you from experience that certain videogames will run on an otherwise hilariously unstable system, just fine - for hours each day, many weeks in with no crashes.
You'd still want to make it stable to improve performance, but _that_ is the big point of Purpose-Specific Overclocking - you can run "unstable" settings and find them Perfectly Stable for the task.
There are also occasional whispers of the opposite scenario, where something passes "all the tests" but fails spectacularly In Practice.

Tests are wonderful, but they are also only tests. If the engine runs fine, the brakes work flawlessly, and the tyres don't spontaneously fall off - who cares about failing some mystery test you never face?
The important part is how much Fiddle With PC to run X tolerance you have, as that determines the performance ceiling! 💪🤡


----------



## Audioboxer

Blameless said:


> If the only things one does are tolerant of errors (meaning the odd error here or there doesn't change one's experience and has no meaningful adverse consequences) that's one thing, but it's essentially impossible to evaluate low error rates in any reasonable period of time, without tests that are considerably more likely to fail than what you're actually going to be running.
> 
> A 1% chance of a single bit flip per hour would be considered a phenomenally high and utterly unacceptable error rate in some settings, but could easily result in dozens or even hundred of hours between errors. If I have something that I can expect to load one of my systems for a week straight, I'd need many months of error free operation to have reasonable confidence that it wouldn't throw an error the next time I ran it for a week...or I can just use tests I know are likely to prompt errors much sooner and achieve the same level of confidence in a few days.
> 
> 
> 
> A tiny amount of lost performance goes largely unnoticed outside of benchmarks, but any error can potentially require a project be started from scratch, or silently corrupt data that can take enormous effort to fix. There is a lot of stuff I do on my systems that are utterly intolerant of errors. Even if I don't notice them at the time (most errors don't cause crashes, but it would much better if they did), it could call into question the validity of data years down the line.
> 
> This is why I'm always looking for better tests (ones that fail sooner, at lower speeds), because I do want as much performance as I can get, but not at the cost of errors. And since I don't really trust stock to be error free (a significant fraction of stock systems I test will fail) I may as well try to get all the performance I can out of any given system, because I'm going to test the snot out of it before I use it for anything important anyway.
> 
> 
> 
> Currently, my go to tests are OCCT, y-cruncher, Prime 95 (via core cycler and independently), ADIA64's memory stress test (which will fail immediately where almost no other test will on some systems, while never failing even on other very flaky systems), and TM5 (usually with a customized 1usmus profile). Every one of these tests will find errors all the others I likely to miss, or take prohibitively long to find. I also tend to do a few runs of Memtest86 (tests 6,7, and 8), and a bit of Prime95 and/or stressapptest from Linux before booting into Windows and doing more comprehensive testing.
> 
> Have to do combination testing as well, with some GPU and I/O heavy loads thrown into the mix to make sure worst case power and temperature scenarios don't hurt stability. If I know the GPU itself is stable, custom FurMark to target just below the power limits I have set will droop the +12v rail, throw some transients back into the PSU, and dump a lot of heat into the case.
> 
> Since the boost curves are highly temperature dependent, I've also made it a habit to run abbreviated tests at the absolute lowest (5-10C) and highest (~40C) ambient temps I expect my systems to see. Warmer is usually fine as long as memory temperature doesn't get too critical, but cold will often reveal sketchy CO or boost override values pretty quickly due to overboosting.


Yeah I like to run an hour of OCCT as well after all the other apps. I actually forgot AIDA64 has a stability test. When doing CPU and memory at the same time the one thing I notice with it is the CPU doesn't boost frequency as high as TM5 or Karhu. Must just be the way it's testing the CPU at the same time as the memory. Heavier load I presume.

As I'm all on a loop my temps remain pretty stable all the way, and my ambient doesn't fluctuate too much in the UK. Although it can get reasonably warm in the summer.

I think my testing methodology is if out of the box with default BIOS settings can pass X then OCed should pass X. Happy to concede there are people with more knowledge than me who can make arguments for why some error 17 hours in might not matter much but to keep myself right I'll just go on what I want to run daily should pass the tests it would out of the box with no OCing.


----------



## Blameless

Bloax said:


> If the Practical Application is doing heavy computations for 480+ hours on with 0.00% error tolerance, then you're really in the wrong branch of business doing non-ECC RAM OC.
> :- )


Not if I can achieve those error rates with cheaper consumer components...and I usually can. The rates of SEU's in modern DRAM are generally overstated (having fallen precipitously due to the use of high purity packaging materials), while multi-bit errors generally cannot be corrected by ECC, and most any error source that isn't due to particle interactions can be mitigated without ECC. ECC is there as a fallback, not to compensate for unstable configurations. Even on systems I've built using ECC, I consider triggering ECC a test failure.



Bloax said:


> Whereas I can tell you from experience that certain videogames will run on an otherwise hilariously unstable system, just fine - for hours each day, many weeks in with no crashes.


I have similar experiences. These are the error tolerant applications I was referring to.



Bloax said:


> You'd still want to make it stable to improve performance, but _that_ is the big point of Purpose-Specific Overclocking - you can run "unstable" settings and find them Perfectly Stable for the task.


Sure, but I have no systems that _never_ handle important data. Even my most heavily gaming oriented box can and does handle other tasks ranging from my personal finances, to manipulating archives (that I expect to be able to read twenty or thirty years from now), to doing RNA phylogeny work in BLAST or mothur (being able to chop up and do my wife's lab work on her home office, my gaming box, and our HTPC, rather than have to schedule time on the university's cluster has saved a lot of time).

Even the risk of corrupting Windows and having to load a back up generally isn't worth it, to me, for one or two percent more performance than I'd have over as close to unconditionally stable as I can practically achieve.

So, my baseline is always going to be targeting that unconditional stability. Maybe if I think I can get away with pushing things further for some specific case (like benchmarking), I'll do so, but this is very rare, because the difference in performance is essentially imperceptible.



Bloax said:


> There are also occasional whispers of the opposite scenario, where something passes "all the tests" but fails spectacularly In Practice.


Also something I've encountered, forcing me to refine an obviously flawed test methodology. If it fails, it probably failed for a reason, and there will almost certainly be a test that will fail for the same reason much faster than whatever the 'in practice' use case was. And I will find that test.


----------



## Audioboxer

Audioboxer said:


> So yesterday I had a fair bit of paperwork to do so I thought I'd stick a TM5 run on for old times sake and to my absolute shock an error on 14 popped up some time around 1 hour 40 minutes and 2 hours 10 minutes with the settings above.
> 
> View attachment 2551422
> 
> 
> So, powerdown most likely.
> 
> View attachment 2551423
> 
> 
> So I stuck AddrCmdDrvStr to 24 and that passed first time. But I think I'll need to do a 50 hour TM5 again and see what comes up.
> 
> Been running the PC for like a month now with these timings (20 on AddrCmdDrvStr) and no crashes or anything.
> 
> Can powerdown issues be that hard to tease out they can survive hours of testing until... they can't?


With it looking like AddrCmdDrvStr 24 helped just wanted to retest tRFC 208










1.63v, previously I thought it needed 1.64v. So a 0.05v increase to drop from 216 to 208. Unfortunately, 1.65v isn't enough for 200.

So it looks like as before 109.4ns is the absolute lowest that I can achieve at 3800.










AIDA is pretty good. Just normal PBO, no Hydra or affinity shenanigans.

What's annoying now is 1.65v actually puts in a good shift with tRFC 200. It's very likely 1.66v might have a chance of doing it. Sadly all my attempts to throw 1.66v at this bin so far just results in failure.

This is all adhering to the tRFC multiples of 8 principle. I'm sure if I dropped to 204 or something I'd squeeze more out


----------



## Audioboxer

lol if anyone was wondering if the EDC voltage cap was on purpose or not


__ https://twitter.com/i/web/status/1501588190775607298
Looks like there might be no OCing at all with the 3D cache release.


----------



## Blameless

Audioboxer said:


> Looks like there might be no OCing at all with the 3D cache release.


Apparently AMD had to request that limitation be added to firmware by board makers:








AMD Asks Motherboard Makers to Remove Overclocking Options for Ryzen 7 5800X3D


TechPowerUp has verified a rumour posted over on VideoCardz that is quite puzzling, as AMD has asked motherboard makers to remove support for overclocking in the UEFI/BIOS for the Ryzen 7 5800X3D. When we asked for a reason as to why this was the case, we were told that AMD was keeping that...




www.techpowerup.com





If I still get one, I'm going to try it with an AGESA 1.2.0.3c BIOS from before any official support to see what the results are.


----------



## Bloax

Don't forget the unlocked AGESA to enable the 1 3D stack option buried somewhere. :- )


----------



## ManniX-ITA

Audioboxer said:


> lol if anyone was wondering if the EDC voltage cap was on purpose or not


I think it's pretty obvious something like this was made on purpose.
Hopefully someone with a couple of neurons still working will override such a dumb call.
It'll keep so many running old BIOS releases that it could become a massive security risk.
Especially now with so many hacks and exploits on the wild.

I did foresee long ago the thermal issues that the 5800X3D was going to face.
But this is really ridiculous.
I'm really getting worried about Zen4, they keep doing one mistake after another....


----------



## Audioboxer

ManniX-ITA said:


> I think it's pretty obvious something like this was made on purpose.
> Hopefully someone with a couple of neurons still working will override such a dumb call.
> It'll keep so many running old BIOS releases that it could become a massive security risk.
> Especially now with so many hacks and exploits on the wild.
> 
> I did foresee long ago the thermal issues that the 5800X3D was going to face.
> But this is really ridiculous.
> I'm really getting worried about Zen4, they keep doing one mistake after another....


I'd be somewhat open minded to listening if the construction of the "3D cache" in an AM4 body somehow restricts OCing, but adding this to what AMD have done with AGESA for current AM4 and I'm left more sceptical of AMD's intentions.

There is a fair bit of MT performance which can be achieved over 140 EDC and hurting light core boosting when doing this just makes no sense. So who knows what AMD is thinking for new releases!


----------



## ManniX-ITA

Audioboxer said:


> I'd be somewhat open minded to listening if the construction of the "3D cache" in an AM4 body somehow restricts OCing, but adding this to what AMD have done with AGESA for current AM4 and I'm left more sceptical of AMD's intentions.
> 
> There is a fair bit of MT performance which can be achieved over 140 EDC and hurting light core boosting when doing this just makes no sense. So who knows what AMD is thinking for new releases!


It runs already with advertised base clock 400 MHz and boost 200 MHz below the normal 5800X.
Which is huge.
On top of that not restricted but disabled OC.
I don't think it can compete with any Alder Lake or even with a normal 5800X.
Mine can boost 5050 MHz on all cores...
We'll see but I'm very skeptical the bigger cache can compensate this monstrous gap.

The VID limit over 140A is really the most trivial and blunt throttling they could come up with.
There are so many other fine ways to throttle that just doesn't make any sense.
It's suicidal.
Why not directly gifting an Alder Lake to all Ryzen owners?


----------



## domdtxdissar

Pretty sure its the stacked 3d memory that cant run faster than 4.5ghz..Remember L3 run at same clockspeed as the cpu itself..
(3dstacked memory was originally developed for Milan X, which also happen to cap out at 4.5ghz max boosting)

Only solution for _Vermeer X_ was to limit the clockspeed to 4.5ghz maximum and remove all overclocking options 

See no other logical explanation for this


----------



## ManniX-ITA

domdtxdissar said:


> Pretty sure its the stacked 3d memory that cant run faster than 4.5ghz..Remember it L3 run at same clockspeed as the cpu itself..


The GPU Infinity Cache is derived as well from the 3D stacked L3 made for Milan-x.
And its clock is not linked to the GPU die, it's independent.
I was expecting something similar considering they were considering it also for the 5900X/5950X...
What they were thinking, to run them too at 4.5 GHz?
I'm starting to think they could had this insane idea as well...


----------



## ArchStanton

ManniX-ITA said:


> I'm starting to think they could had this insane idea as well...


And when they realized it wouldn't be enough to catch Alder Lake in single thread they pulled the plug?


----------



## Taraquin

I hope negative CO and ram OC works as usual!


----------



## ManniX-ITA

ArchStanton said:


> And when they realized it wouldn't be enough to catch Alder Lake in single thread they pulled the plug?


I think they pulled the plug when they realized the cut of clocks was unacceptable.
With the core count going up the clocks would go down and the cache advantage diminishing.


----------



## Audioboxer

ManniX-ITA said:


> It runs already with advertised base clock 400 MHz and boost 200 MHz below the normal 5800X.
> Which is huge.
> On top of that not restricted but disabled OC.
> I don't think it can compete with any Alder Lake or even with a normal 5800X.
> Mine can boost 5050 MHz on all cores...
> We'll see but I'm very skeptical the bigger cache can compensate this monstrous gap.
> 
> The VID limit over 140A is really the most trivial and blunt throttling they could come up with.
> There are so many other fine ways to throttle that just doesn't make any sense.
> It's suicidal.
> Why not directly gifting an Alder Lake to all Ryzen owners?


When companies are on top they often love the fall back down lol.

Rumours of AM5 possibly sliding to 2023 as well. If it's not ready fair enough, but everything going on at AMD right now seems a bit of a mess.


----------



## ArchStanton

Taraquin said:


> I hope negative CO and ram OC works as usual!


My interpretation of the news would cause me to assume there will be no CO/PBO2 for 5800X3D. DOCP would presumably still work 🤷‍♂️.


----------



## Audioboxer

ArchStanton said:


> My interpretation of the news would cause me to assume there will be no CO/PBO2 for 5800X3D. DOCP would presumably still work 🤷‍♂️.


Correct I'd say AMD Asks Motherboard Makers to Remove Overclocking Options for Ryzen 7 5800X3D

I remember months back I was speculating about a 3D cache 5950x that might run higher FCLK 😂

Instead we have what looks like beta testing for AM5.


----------



## ManniX-ITA

Audioboxer said:


> Rumours of AM5 possibly sliding to 2023 as well. If it's not ready fair enough, but everything going on at AMD right now seems a bit of a mess.


Really hope they don't rush it out. Better late than disappointing.
Hopefully they'll spend some effort to raise the NPS of the 5000 series to avoid hemorrhaging customers to Intel...
On the competitive side if Zen4 is just 20% faster than Zen3 it doesn't make sense.
Alder Lake is already 20% faster and the next one will be even faster... they'll go back again chasing endlessly.


----------



## Bloax

it's ok guys the reduction in micro-stalling makes the cores run too hot for the am4 packaging to cool at >20W per core just wait for am5 it's gonna be pure kino


btw there seems to be some funny business with ADL requiring much less memory controller voltage to actually run memory at [Hard Settings] than it requires for training it
hehe


----------



## ManniX-ITA

Wondering about the quality of B2 5950X silicon could be?

Got a BSOD today powering up from cold boot.
Switched off, booted in Windows.
Got a filesystem corruption notification on M.2 C: drive.
Rebooted, fixing filesystem. Reboot, file system fixed. Bam. This:










I hope my Windows install is still alive...
I'm going to swap back to the 5800X.


----------



## Kha

ManniX-ITA said:


> Wondering about the quality of B2 5950X silicon could be?


Hey, you didnt say much about your new B2 5950x, so how is it ?


----------



## ManniX-ITA

Kha said:


> Hey, you didnt say much about your new B2 5950x, so how is it ?


As above, it's a terrible binning and faulty 
I'm waiting AMD to accept the new RMA...


----------



## Kha

ManniX-ITA said:


> As above, it's a terrible binning and faulty
> I'm waiting AMD to accept the new RMA...


Incredible, I actually tested a B2 5900x too which was worse binned than a B0. I settled with the B0, of course.


----------



## Bloax

Personally then I find it more likely that there's a bad batch of questionably sourced capacitors/micro-SMD's that ****s with the CPU - more likely than you might hope in the current conditions - than the CPU silicon die itself being absolute peepee poo poo.
Either way ur cpu ***kd lol 🤡


----------



## chucky27

Hi everyone, just received a fresh 5950x (B2, BG 2201 SUS). What would you recommend for testing stock stability and bin quality?


----------



## Blameless

ManniX-ITA said:


> The GPU Infinity Cache is derived as well from the 3D stacked L3 made for Milan-x.
> And its clock is not linked to the GPU die, it's independent.
> I was expecting something similar considering they were considering it also for the 5900X/5950X...
> What they were thinking, to run them too at 4.5 GHz?
> I'm starting to think they could had this insane idea as well...


Can't run the ring bus or L3 on on Zen 3 any slower than the fastest active core and the extra cache is just an extension of each slice of base cache.

Decoupling the L3 from the core clocks would have been a much more radical change and would also likely have significantly increased L3 latency.


----------



## Audioboxer

Anyone want to see what a tight fit looks like? lol

That's an XR7 radiator and two sets of fans literally just squeezing under a vertical GPU mount. My challenge isn't this though, just proven it can be done.

It's the size of the damn 3080 cards. I've got my waterblock in for it and the headache I think I will have is the rear 120mm radiator and clearance. My 2080Ti waterblock was much shorter. I definitely can't run a push/pull on the 120mm in vertical now. Internal Corsair fan would have to be sacrificed.

If it's going to fit it's going to be stupidly tight. Need to wait a few days till EVGA ship out my Step Up and get the block on the card. If it fails it's back to a horizontal mount. Might even be best just to do this to keep the RGB fan at the back inside, we'll see.

Bought an XC7 Pro as well, noticed Corsair increased their fin count from 60 or something in the XC7 I have to like 110 in the XC7 Pro. See if it knocks a couple of degrees off the CPU.


----------



## nick name

ManniX-ITA said:


> Wondering about the quality of B2 5950X silicon could be?
> 
> Got a BSOD today powering up from cold boot.
> Switched off, booted in Windows.
> Got a filesystem corruption notification on M.2 C: drive.
> Rebooted, fixing filesystem. Reboot, file system fixed. Bam. This:
> 
> View attachment 2551532
> 
> 
> I hope my Windows install is still alive...
> I'm going to swap back to the 5800X.








Use the System File Checker tool to repair missing or corrupted system files - Microsoft Support


Describes how to use the System File Checker tool to troubleshoot missing or corrupted system files in Windows 8.1, Windows 8, Windows 7 or Windows Vista.




support.microsoft.com


----------



## PJVol

Blameless said:


> Decoupling the L3 from the core clocks would have been a much more radical change and would also likely have significantly increased L3 latency


Not to mention the lack of any sense in it.


----------



## ManniX-ITA

chucky27 said:


> Hi everyone, just received a fresh 5950x (B2, BG 2201 SUS). What would you recommend for testing stock stability and bin quality?


Good luck. Backup your data 
Use y-cruncher to test all core and CoreCycler for single core test.



Blameless said:


> Can't run the ring bus or L3 on on Zen 3 any slower than the fastest active core and the extra cache is just an extension of each slice of base cache.
> 
> Decoupling the L3 from the core clocks would have been a much more radical change and would also likely have significantly increased L3 latency.


I thought they came up with something brilliant, not the case 
I wonder how they got to the point to claim in public it was possible a 5900X/5950X with 3D stacked cache.
Seems the thermal and clock limitations are exactly the same as the Milan-x.
Guess someone didn't get promoted...



nick name said:


> Use the System File Checker tool to repair missing or corrupted system files - Microsoft Support
> 
> 
> Describes how to use the System File Checker tool to troubleshoot missing or corrupted system files in Windows 8.1, Windows 8, Windows 7 or Windows Vista.
> 
> 
> 
> 
> support.microsoft.com


Thanks but the whole disk was corrupted, the installation ****ed up.
Now I'm at the second 3 hours restore but from yesterday's backup.


----------



## Blameless

ManniX-ITA said:


> I wonder how they got to the point to claim in public it was possible a 5900X/5950X with 3D stacked cache.


It probably is. But it's also probably not economical. I'm sure if they binned hard enough they could stick two very high clocking v-cache CCDs on an AM4 package and sell them.

But who would buy it if they sold it for the same margins they are going to be getting with Milan-X? I'm not spending $1500+ to probably not even have an i9-12900KS equivalent on AM4. I could gut my system, get a stronger PSU, better cooling, a new motherboard, and DDR5, for less.

For the things the cache matters for, it might still make the 5800X3D a passable drop in replacement for those not looking to build a new system, even if it turns out that 4.5GHz is all that can be had from it (and I'm not quite convinced this will be the case). There is no such niche for a dual-CCD part that would have to costs three or four times as much.


----------



## blodflekk

Just launched a new bios for dark hero 4006. Same AGESA 1.2.0.6b Supposedly added compatibility and stability. Anyone here tried it ?


----------



## ManniX-ITA

Blameless said:


> It probably is. But it's also probably not economical. I'm sure if they binned hard enough they could stick two very high clocking v-cache CCDs on an AM4 package and sell them.


Well the cost factor is critical of course 
If you can't sell it, doesn't matter if it's theoretically possible. 
Probably as you said they greatly overestimated their binning quality.
This B2 5950X they've sent me, if we just for a moment forget it's broken, is an awful binning.
Which is perplexing considering that you usually get better bins after 6-12 months.
Maybe they are using the inner rings of the wafers for the GPUs now...



Blameless said:


> For the things the cache matters for, it might still make the 5800X3D a passable drop in replacement for those not looking to build a new system, even if it turns out that 4.5GHz is all that can be had from it (and I'm not quite convinced this will be the case). There is no such niche for a dual-CCD part that would have to costs three or four times as much.


I'm curious but I'm not convinced as well.
This claim it'd be faster than a 12900K in gaming it's too bold, smells fishy.
I was planning to get one but now with the 2nd 5950X RMA I'm probably stuck with a normal 5800X.
I'm going to exceed the 30 day return window and I'll have to keep it.


----------



## Taraquin

ManniX-ITA said:


> Well the cost factor is critical of course
> If you can't sell it, doesn't matter if it's theoretically possible.
> Probably as you said they greatly overestimated their binning quality.
> This B2 5950X they've sent me, if we just for a moment forget it's broken, is an awful binning.
> Which is perplexing considering that you usually get better bins after 6-12 months.
> Maybe they are using the inner rings of the wafers for the GPUs now...
> 
> 
> 
> I'm curious but I'm not convinced as well.
> This claim it'd be faster than a 12900K in gaming it's too bold, smells fishy.
> I was planning to get one but now with the 2nd 5950X RMA I'm probably stuck with a normal 5800X.
> I'm going to exceed the 30 day return window and I'll have to keep it.


You would expect more maturety by age, but a friend of mine got his 5600X december 21, he gets flooded with WHEA19 above 3666 and no CO so far has been stable. Corecycler ended up with -5 to -25 on best core, but get lots of reboots in games, so had to disable it. My 5600X bought in April 21 is awesome and do -30 CO+50pbo and 4133/2066 w/o WHEA19. Maybe even 4200+ if I disable pcie 4.0.


----------



## ManniX-ITA

Taraquin said:


> You would expect more maturety by age, but a friend of mine got his 5600X december 21, he gets flooded with WHEA19 above 3666 and no CO so far has been stable. Corecycler ended up with -5 to -25 on best core, but get lots of reboots in games, so had to disable it. My 5600X bought in April 21 is awesome and do -30 CO+50pbo and 4133/2066 w/o WHEA19. Maybe even 4200+ if I disable pcie 4.0.


And the discussion with the AMD rep is getting heated:

_If you are still facing issues with the BIOS defaults settings, I will assist you with a second RMA *as a one-time exception*._

I guess he didn't understood I've switched back to the 5800X once my Windows install was corrupted...

I really had to take deep breaths to avoid becoming unpolite:

_I hope you are kidding about the one-time exception.
I want a working 5950X back.
Didn't pay 900 euro for scrap metal.
If the next one you'll send me it's a dud as well there'll be another exception.
Until I get a working CPU that doesn't destroy my PC and let me work._

I have enough juice to get them to court and win if they send me another broken CPU and refuse the RMA.
Maybe they're not clear how powerful are customers rights in Europe, especially in Germany where the protection is particularly strong.


----------



## Taraquin

ManniX-ITA said:


> And the discussion with the AMD rep is getting heated:
> 
> _If you are still facing issues with the BIOS defaults settings, I will assist you with a second RMA *as a one-time exception*._
> 
> I guess he didn't understood I've switched back to the 5800X once my Windows install was corrupted...
> 
> I really had to take deep breaths to avoid becoming unpolite:
> 
> _I hope you are kidding about the one-time exception.
> I want a working 5950X back.
> Didn't pay 900 euro for scrap metal.
> If the next one you'll send me it's a dud as well there'll be another exception.
> Until I get a working CPU that doesn't destroy my PC and let me work._
> 
> I have enough juice to get them to court and win if they send me another broken CPU and refuse the RMA.
> Maybe they're not clear how powerful are customers rights in Europe, especially in Germany where the protection is particularly strong.


It`s somewhat understandable that AMD don`t like people mishandling their CPUs and run insane allcore OC at 1.4V+ and expect all to be well in the long run, but that is not the case with you. I thinks it`s fair that some samples are ****ty bins and perhaps only can run ram at 3600 w\o WHEA19, that some cores might only do -3 CO and no pbo etc, BUT if a CPU can`t run stable stock it is faulty. It does not matter that it works if you overvolt core 5 by +5 on CO or set at positive +25mv offsett on allcore voltage, the product is faulty as it cannot run at it`s stock spec.

The poor bin my friend got of his 5600X still works fine, it might be able to do a very low negative CO stable and ram runs fine at 3666 so there is no issue. For a overclocker\tweaker like me his sample is a disaster, but not like your 5950X which can`t even run stock. You could as domdtxdissar if he would sell you one of his very good samples?


----------



## ManniX-ITA

Taraquin said:


> For a overclocker\tweaker like me his sample is a disaster, but not like your 5950X which can`t even run stock. You could as domdtxdissar if he would sell you one of his very good samples?


I was willing to accept a poor bin but not one faulty at stock... 
I'm already planning to switch to a 7000 (not so sure now) or Raptor Lake in 6-9 months 

What I'm pissed off is that, despite the detailed description and explanations of the setup and tests done, they didn't apologize.
I wasted money, time and effort and what, should I beg for a 2nd RMA?
Like I think it's funny to waste time swapping CPU for nothing.

He didn't even really read what I've spent my time writing.
Just assumed I'm dumb and it was my fault.
All my work is around customers' satisfaction; as we say in our pillars we must be "customer obsessed".
These reps they handle you like an annoyance and not the RMA being an annoyance to you.
I guess their performances are not evaluated by NPS like us.


----------



## Blameless

ManniX-ITA said:


> I'm curious but I'm not convinced as well.
> This claim it'd be faster than a 12900K in gaming it's too bold, smells fishy.
> I was planning to get one but now with the 2nd 5950X RMA I'm probably stuck with a normal 5800X.
> I'm going to exceed the 30 day return window and I'll have to keep it.


The 12900K is not so much faster (in gaming) than current Zen 3 parts that the claim the 5800X3D could match or beat it is too far fetched, even with a small clock speed penalty vs current parts.

At this point I'll see how thinks look at launch, with both AGESA 1.2.0.3c and AGESA 1.2.0.7. If turns out that there really is no OCing, or no practical stable OC, I'll just try to get a discount 5900X and faster RAM.


----------



## ManniX-ITA

Blameless said:


> The 12900K is not so much faster (in gaming) than current Zen 3 parts


Unfortunately never could test it in person.
The benchmarks scores, especially in GeekBench 5 and CPU-Z, are impressive.
3DMark CPU profile as well, especially 4 and 8 threads.
But benchmarks results are often far from real world performances.



Blameless said:


> If turns out that there really is no OCing, or no practical stable OC, I'll just try to get a discount 5900X and faster RAM.


To be honest for gaming the vanilla 5800X seems to be really awesome.
If it's a decent silicon the boost is magnificent with CO and +200.
But I don't know the 5900X so I can't compare.


----------



## Audioboxer

PCI-E additional 3 pin connector on a mobo, these aren't really needed for a 3080 and 5950x under normal operation are they?

Just discovered with a fat radiator at the bottom I can't quite fit it in with the 3 pin connector at the bottom left hand side of this mobo.


----------



## ManniX-ITA

Audioboxer said:


> PCI-E additional 3 pin connector on a mobo, these aren't really needed for a 3080 and 5950x under normal operation are they?
> 
> Just discovered with a fat radiator at the bottom I can't quite fit it in with the 3 pin connector at the bottom left hand side of this mobo.


That's for the PCIe 12V if I remember correctly.
Not really necessary.
It does offload a bit of power load from the other 2 near the VRM which are already oversized...
I think not even with a shunt modded GPU consuming over spec from PCIe does make a difference.


----------



## Audioboxer

ManniX-ITA said:


> That's for the PCIe 12V if I remember correctly.
> Not really necessary.
> It does offload a bit of power load from the other 2 near the VRM which are already oversized...
> I think not even with a shunt modded GPU consuming over spec from PCIe does make a difference.


Thanks. This 3080 is a 3 connector as well, so it really should be getting fed enough power as is.

I dare say there might be some right angle down connector adapter that I can buy from somewhere to allow me to plug 'up' into the connector rather than head on, but I'll just disconnect it.


----------



## ManniX-ITA

Audioboxer said:


> Thanks. This 3080 is a 3 connector as well, so it really should be getting fed enough power as is.
> 
> I dare say there might be some right angle down connector adapter that I can buy from somewhere to allow me to plug 'up' into the connector rather than head on, but I'll just disconnect it.


The PCIe slot is limited to 75W (by spec, with shunt mod can get close to 100W).
You should have more than enough juice from the ATX 24p and the others 2 PCIe on top...


----------



## Audioboxer

ManniX-ITA said:


> The PCIe slot is limited to 75W (by spec, with shunt mod can get close to 100W).
> You should have more than enough juice from the ATX 24p and the others 2 PCIe on top...


Yeah I never needed it before, I just plugged it in last time I did a tear down because I noticed I had it after someone else mentioned it on this forum lol. At the time it was mentioned it's more likely to be used with extreme OCing or if running more than 1 GPU.


----------



## Taraquin

Blameless said:


> The 12900K is not so much faster (in gaming) than current Zen 3 parts that the claim the 5800X3D could match or beat it is too far fetched, even with a small clock speed penalty vs current parts.
> 
> At this point I'll see how thinks look at launch, with both AGESA 1.2.0.3c and AGESA 1.2.0.7. If turns out that there really is no OCing, or no practical stable OC, I'll just try to get a discount 5900X and faster RAM.











With good tuning the difference is quite large, 12700K is 22% faster avg than 5800X. I don't think that 5800X3D can beat 12700K and 12900K on avg, but might win in a few games. Also the larger cache makes ram tuning matter a bit less like we saw on zen 2 vs 3 where you often got a bit more improvement going from stock 3200 to tuned 3800 on zen 2.


----------



## ManniX-ITA

Taraquin said:


> With good tuning the difference is quite large, 12700K is 22% faster avg than 5800X. I don't think that 5800X3D can beat 12700K and 12900K on avg, but might win in a few games.


Interesting.
Do you know what games they tested and at which resolution/quality?
I play at 1440p with a 3090 so usually quality maxed out.
Not sure I would see that 22% in these conditions.


----------



## Blameless

ManniX-ITA said:


> To be honest for gaming the vanilla 5800X seems to be really awesome.
> If it's a decent silicon the boost is magnificent with CO and +200.
> But I don't know the 5900X so I can't compare.


I'm on my third 5800X. Not one of them was even close to unconditionally stable at +200 without really poor curves that just degraded performance.



Taraquin said:


> View attachment 2551641
> 
> With good tuning the difference is quite large, 12700K is 22% faster avg than 5800X. I don't think that 5800X3D can beat 12700K and 12900K on avg, but might win in a few games.


What game is that? Or is that a composite?

I'm also limited by my power and cooling (my gaming box is an ITX system), so more than about 150-200w for the CPU would be a no go.



Taraquin said:


> Also the larger cache makes ram tuning matter a bit less like we saw on zen 2 vs 3 where you often got a bit more improvement going from stock 3200 to tuned 3800 on zen 2.


I probably wouldn't swap out my budget CRJ stuff if I got the 5800X3D for just that reason.



ManniX-ITA said:


> I play at 1440p with a 3090 so usually quality maxed out.
> Not sure I would see that 22% in these conditions.


Not many people looking for a CPU upgrade in GPU limited scenarios.

Gaming wise, it's all these poorly optimized less-than-AAA UE4 titles I play that are providing to be problematic on my 5800X.


----------



## beluoc2

Does anyone have any tips on tightening the timings for my ram? It's been a frustrating few days. The default xmp profiles do not work on my motherboard. It seems to be extremely voltage sensitive. I tried one of the calculators here to no avail. The type of die is unknown to me. It has a DWDR1023xa1 printed on the ic along with a qr code. Here are the specs I can read and the timings that seem to be stable so far. I believe the VDDG CCD is .00V


----------



## Kha

Truth to be told, I am also thinking of upgrading my 5900x to something else. 
I however feel that going to 5800x3d will be a donwgrade, even if it will prolly behave better in 1080p. 
Could also go 5950x, but seeing @ManniX-ITA strugle so much with his sample(s), suddenly the urge stops. 

Anybody knows if the Z690 boards will be able to support Raptor Lake too ? Toying somehow with the idea of jumping the gun and go 12900k.


----------



## ManniX-ITA

Blameless said:


> Gaming wise, it's all these poorly optimized less-than-AAA UE4 titles I play that are providing to be problematic on my 5800X.


Like what? I'm curious to see if I can reproduce it.

Got the RMA and scheduled the pick up of the 5950X today so I have still probably a week to test this 5800X.



Blameless said:


> I'm on my third 5800X. Not one of them was even close to unconditionally stable at +200 without really poor curves that just degraded performance.


Wow, maybe I've been extremely lucky then...



Blameless said:


> I probably wouldn't swap out my budget CRJ stuff if I got the 5800X3D for just that reason.


Could be it's you memory killing the 5800X performances?
I didn't test it specifically but I've run the B2 5950X at stock 2400 MHz and XMP 3800 MHz.
Just switching to the XMP profile at 3800 meant a loss of 20% hashrate with the monero miner.



Kha said:


> Could also go 5950x, but seeing @ManniX-ITA strugle so much with his sample(s), suddenly the urge stops.


If you have a return window it's not a bad purchase now that's only 600 euro...
But I'm not sure it's a worthy upgrade from a 5900X unless you need so many cores.



Kha said:


> Anybody knows if the Z690 boards will be able to support Raptor Lake too ? Toying somehow with the idea of jumping the gun and go 12900k.


Leaked info is suggesting they use the same socket.
But it's Intel... they could force a board upgrade also if the previous is perfectly fine.
And of course it'll probably be only DDR5.


----------



## ManniX-ITA

Blameless said:


> I'm on my third 5800X. Not one of them was even close to unconditionally stable at +200 without really poor curves that just degraded performance.


Made a video on how I started the CO tuning.
You don't get close to this with BoostTester and CPU-z?


----------



## nick name

ManniX-ITA said:


> And the discussion with the AMD rep is getting heated:
> 
> _If you are still facing issues with the BIOS defaults settings, I will assist you with a second RMA *as a one-time exception*._
> 
> I guess he didn't understood I've switched back to the 5800X once my Windows install was corrupted...
> 
> I really had to take deep breaths to avoid becoming unpolite:
> 
> _I hope you are kidding about the one-time exception.
> I want a working 5950X back.
> Didn't pay 900 euro for scrap metal.
> If the next one you'll send me it's a dud as well there'll be another exception.
> Until I get a working CPU that doesn't destroy my PC and let me work._
> 
> I have enough juice to get them to court and win if they send me another broken CPU and refuse the RMA.
> Maybe they're not clear how powerful are customers rights in Europe, especially in Germany where the protection is particularly strong.


I had no problems with my multiple RMAs here in the states. Sucks that you're getting pushback.


----------



## ArchStanton

Just wanted to add another data point for @ManniX-ITA as he fights the good fight. I purchased my first 5950X around 11/15/2021. It was a B0 stepping. It would fail CoreCycler on its best core at stock settings (no DOCP, no PBO2, etc.) I got no "pushback" when I applied for RMA. While waiting for the RMA to be approved and the replacement shipped to me, I purchased an additional 5950X in case I damaged or destroyed one through ignorance as I tweaked and tested. I have since had time to test both the replacement chip (surprisingly also B0 stepping) I received through the RMA process and the additional unit I purchased separately (B2). Given sufficient time, all three chips will/would fail CoreCycler 720-720 on the "best" core at totally stock settings. At this point, I suspect that the "latter day" Ryzen 5000 series CPUs are not the cream available earlier in the product's life cycle, but the slag left over after binning has harvested the best CCD's for other AMD products.


----------



## Taraquin

ManniX-ITA said:


> Interesting.
> Do you know what games they tested and at which resolution/quality?
> I play at 1440p with a 3090 so usually quality maxed out.
> Not sure I would see that 22% in these conditions.


Check out i2hard on youtube or i2hard.ru  Cyberpunk, SOTTR and a few others. 22% at 1080p with mostly CPU bound.


----------



## Taraquin

Blameless said:


> I'm on my third 5800X. Not one of them was even close to unconditionally stable at +200 without really poor curves that just degraded performance.
> 
> 
> 
> What game is that? Or is that a composite?
> 
> I'm also limited by my power and cooling (my gaming box is an ITX system), so more than about 150-200w for the CPU would be a no go.
> 
> 
> 
> I probably wouldn't swap out my budget CRJ stuff if I got the 5800X3D for just that reason.
> 
> 
> 
> Not many people looking for a CPU upgrade in GPU limited scenarios.
> 
> Gaming wise, it's all these poorly optimized less-than-AAA UE4 titles I play that are providing to be problematic on my 5800X.


Check out i2hard on youtube, think they test 7 games, Cyberpunk, SOTTR etc.


----------



## ManniX-ITA

ArchStanton said:


> Given sufficient time, all three chips will/would fail CoreCycler 720-720 on the "best" core at totally stock settings.


Wow, worrying... my early batches B0 wouldn't fail it on any core even the best ones boosting up to 5150 MHz.
Anyway my B2 replacement was completely messed up. I had stability issues, eg Visual Studio corrupting the symbols cache
And of course at the end the majestic system corruption.
Let's hope the next one is not another tragedy... the courier already cam for the pickup.


----------



## Blameless

ManniX-ITA said:


> Like what? I'm curious to see if I can reproduce it.


Space Hulk - Deathwing, especially multiplayer, and MechWarrior 5 are prime offenders. Deathwing in particular is almost completely CPU limited with large numbers of enemies on screen.



ManniX-ITA said:


> Could be it's you memory killing the 5800X performances?


I doubt it. My dual-rank CJR stuff is almost as fast as my single-rank B-die, both fully tuned, in both synthetic and real-world tests. I'm considering getting a dual-rank kit of decent binned B-die, but the performance uplift would be pretty minor, even more so on a 5800X3D.



ManniX-ITA said:


> Made a video on how I started the CO tuning.
> You don't get close to this with BoostTester and CPU-z?


I get exactly the clocks I expect to get, based on the boost clock override setting.

The issue is that past +100MHz (or 4.95GHz maximum boost) I can find instabilities at any curve settings that actually perform better than any higher override. So, I use +100MHz.

Clocks in games are typically in the 4.7GHz ballpark.


----------



## ManniX-ITA

Blameless said:


> Space Hulk - Deathwing, especially multiplayer, and MechWarrior 5 are prime offenders. Deathwing in particular is almost completely CPU limited with large numbers of enemies on screen.


I have MW5 and maybe also Space Hulk.
Thanks, I'll check.



Blameless said:


> The issue is that past +100MHz (or 4.95GHz maximum boost) I can find instabilities at any curve settings that actually perform better than any higher override. So, I use +100MHz.


Well I didn't test yet very well so I'm not sure if it's fully stable at +200.
But I'm at FCLK 2000 with a lot of voltage juice 
And the cooling is air, Dark Rock Pro 4.

So far I could get Linpack Xtreme at 357 GFlops, GB5 1811/12248, CB23 16162.
CPU-z on best core 695, ST/MT 678/7006.
Not sure how it is, CPU-z MT should be around 7200 at least but all-core it's jumping over 90c.
So I guess it's normal that all MT scores are capped.
But it does start between 7300-7400.

What I've found out causing instability issues is the OVP protection.
Never had this issue with the 5950X.
On MSI there are 2 settings; Auto and Enhanced, one for CPU and the other for SOC.
I had to set Auto for the SOC.
Fortunately the CPU can be left on Enhanced, set to Auto had a big impact on single core boosting.


----------



## Blameless

ManniX-ITA said:


> Well I didn't test yet very well so I'm not sure if it's fully stable at +200.


The tests I've typically had the hardest time passing were very long runs of CoreCycler or y-cruncher HNT.



ManniX-ITA said:


> So far I could get Linpack Xtreme at 357 GFlops, GB5 1811/12248, CB23 16162.
> CPU-z on best core 695, ST/MT 678/7006.


Haven't run GeekBench, but with my 'unconditionally stable' settings, this 5800X sample gets ~347 GFLOPS in Linpack Xtreme, ~684/6710 in the standard CPU-Z bench (core 0 is this sample's actual best core), and ~15700 in Cinebech 23.

More aggressive, superficially stable, curves with a higher boost override were modestly faster, but I would eventually find something that threw an error with them.


----------



## Audioboxer

MSI seem to be rolling out AGESA 1.2.0.6c









MSI Rolls Out AGESA 1.2.0.6C BIOS FirmwareFor 500-Series Motherboards: Offers AMD Ryzen 7 5800X3D CPU Support, Performance Improvements


MSI has rolled out its first wave of AGESA 1.2.0.6C BIOS firmware for 500-series motherboards & adds support for AMD Ryzen 7 5800X3D CPU.




wccftech.com





Yet again Unify X boards lagging behind....


----------



## ManniX-ITA

Blameless said:


> The tests I've typically had the hardest time passing were very long runs of CoreCycler or y-cruncher HNT.


Well, I'll give a go only if I can pass CoreCyler with all FFTs SSE/AVX/AVX2 
For all-core testing all tests stress test y-cruncher 12 cycles never gave me a false positive.
I also add a few hours of OCCT Extreme Variable SSE.



Blameless said:


> Haven't run GeekBench, but with my 'unconditionally stable' settings, this 5800X sample gets ~347 GFLOPS in Linpack Xtreme, ~684/6710 in the standard CPU-Z bench (core 0 is this sample's actual best core), and ~15700 in Cinebech 23.


Looks very similar to what I was getting with CO disabled.
I would give a check with higher voltages and beefed up VRM, if you didn't already.
There's maybe a lot of potential left on the table, I'm sad 
But indeed testing again thoroughly it's a burden and maybe not worth for this delta...



Audioboxer said:


> Yet again Unify X boards lagging behind....


Let's see first if there are fixed bugs or shiny new bug before we complain


----------



## MrHoof

Blameless said:


> Haven't run GeekBench, but with my 'unconditionally stable' settings, this 5800X sample gets ~347 GFLOPS in Linpack Xtreme, ~684/6710 in the standard CPU-Z bench (core 0 is this sample's actual best core), and ~15700 in Cinebech 23.
> 
> More aggressive, superficially stable, curves with a higher boost override were modestly faster, but I would eventually find something that threw an error with them.


For some more comparision.
Dunno about linpack but mine scores at +0mhz 675/7100 CPU-Z bench and about 16200-300 CB23. 
B0 nov 2020.


----------



## ManniX-ITA

MrHoof said:


> Dunno about linpack but mine scores at +0mhz 675/7100 CPU-Z bench and about 16200-300 CB23.


Yeah I'm limited by cooling in all core, it gets really hot very quickly and throttle at 90c.
Can you run geekbench 5?
I'm curious about the scores in ST.


----------



## MrHoof

Same also Cooling limited thats why i dont use boost override I am using a noctua U12A but in a single CB23 run I´ll max at 80c. 
Only time ive seen 90c is running ycrunsher loops and here from not to long ago SOC testing geekbench 5.


----------



## ManniX-ITA

MrHoof said:


> Same also Cooling limited thats why i dont use boost override I am using a noctua U12A but in a single CB23 run I´ll max at 80c.


Well I top 83c with CB23, not that far.
Have still to try different PPT/TDC, now I'm at 160/100.
When I've tested it before getting the B2 5950X I was using 135/90.
Have to check.
But with +200 CPU-z ST score on the best Core is 695, not bad.
And gaming, didn't do much, the cores were boosting continuously up to 5050 MHz.
For comparison with the old 5950X it was more around 4750 with much less frequent boosting to 4950.


----------



## MrHoof

That exactly what my TDC and EDC are set too. 
100/160 and ppt is at 162w.


----------



## ManniX-ITA

MrHoof said:


> That exactly what my TDC and EDC are set too.
> 100/160 and ppt is at 162w.


Okay, I'm at 160/100/140.
Will check later.
I think last time at 160A got better scores in MT but lower in ST.
Didn't take any screenshot unfortunately


----------



## MrHoof

ManniX-ITA said:


> Well I didn't test yet very well so I'm not sure if it's fully stable at +200.
> But I'm at FCLK 2000 with a lot of voltage juice


How much is alot voltage juice? 
Curious what wattage hwinfo is reporting under full load for CPU SoC Power(SV12 TFN)
Mine is running 1900fclk at 1.0625v 13.6W for SoC.
edit:
CCD 0.9
IOD 0.98 (lower will throw WHEA19 at random)


----------



## ManniX-ITA

MrHoof said:


> Curious what wattage hwinfo is reporting under full load for CPU SoC Power(SV12 TFN)


15.7W with a peak of 22.3W.
If I have time I'll test it also at FCLK 1866 and see how low I can go with voltages.


----------



## ManniX-ITA

MrHoof said:


> edit:
> CCD 0.9
> IOD 0.98 (lower will throw WHEA19 at random)


Wow going lower voltages at FCLK 1867 and without boost clock it's killing it 
I sued CCD/IOD 950/1000 and VSOC 1.1V.
I remember at 900mV doesn't POST

CPU-z 650/6925


----------



## MrHoof

CPU-Z should always hit around 675 single core if your core boosts to 4.85ghz.


Spoiler: some benches















edit: damn took a random aida screenshot from my folder and its with boost overwrite 😅


Spoiler: aida 4.85ghz from just now


----------



## Blameless

ManniX-ITA said:


> I would give a check with higher voltages


Higher voltages don't help as I'm already temperature limited.


----------



## ManniX-ITA

Blameless said:


> Higher voltages don't help as I'm already temperature limited.


I'm temperature limited too but this sample loves voltage.
Sometimes a small bump doesn't raise much temps but gives a huge boost.

Mine in MT doesn't want to get even close to @MrHoof sample.
Maybe it's the silicon or the board/AGESA.
Still have to do some testing but seems to hard stop at some point.

I've tested quickly MW5 and seems to run pretty well.
Around 75-120 fps at 1440p with one thread the Core at 75% clocked usually at 4850 MHz.
But it was a long time last time I played it so I don't recall how was going with the 5950X.


----------



## Blameless

ManniX-ITA said:


> I've tested quickly MW5 and seems to run pretty well.
> Around 75-120 fps at 1440p with one thread the Core at 75% clocked usually at 4850 MHz.
> But it was a long time last time I played it so I don't recall how was going with the 5950X.


Frame rate seems a bit low, unless you're running ray tracing. What's GPU utilization look like?


----------



## ManniX-ITA

MrHoof said:


> CPU-Z should always hit around 675 single core if your core boosts to 4.85ghz.


Yes with low voltages the single core boosting is failing miserably.

We are not that far, I thought worse.
You MT is probably better due to the newer AGESA.
Also the 5950X was scoring better with lower clocks.












Blameless said:


> Frame rate seems a bit low, unless you're running ray tracing. What's GPU utilization look like?


I forgot to check the settings... but I think RT was disabled.
Didn't notice the GPU utilization.
Have to reboot back into the main install.


----------



## ManniX-ITA

Blameless said:


> Frame rate seems a bit low, unless you're running ray tracing. What's GPU utilization look like?


The Cores are more utilized that I thought, they are almost all at 75%.
It's a big map with 3 bases but the fps goes down very quickly in a closed range fight.
GPU utilization max was maybe 80%.
Usually between 50-60%, dropped down to 40% in closed combat.
All settings maxed out at 1440p without RT.


----------



## MrHoof

I am running 1.2.0.3c never updated to a later one and not planning to. But to mention maybe I am running DR 1T no setup timings aswell board is a asus rog x570i.

edit: But your aida score destroys mine so i doubt 1T no setup makes a diffrence.


----------



## KedarWolf

MrHoof said:


> I am running 1.2.0.3c never updated to a later one and not planning to. But to mention maybe I am running DR 1T no setup timings aswell board is a asus rog x570i.
> 
> edit: But your aida score destroys mine so i doubt 1T no setup makes a diffrence.


Early reports say 1.2.0.6c as good as or better than 1.2.0.3c.

But remains to be seen if it still has that EDC VID bug, that would be a deal-breaker for me.


----------



## Blameless

ManniX-ITA said:


> GPU utilization max was maybe 80%.
> Usually between 50-60%, dropped down to 40% in closed combat.


This is definitely a CPU limitation, if you aren't capping frame rate.

I'm playing in DX12, 1440p, maximum settings, no RT; just played a mission and the average frame rate was ~142. GPU (a 6800 XT) utilization is normally maxed out, but when mechs spawn, or firefights get heated, the GPU utilization will dip down as low as 60-70%.


----------



## Kha

ManniX-ITA said:


> If you have a return window it's not a bad purchase now that's only 600 euro...
> But I'm not sure it's a worthy upgrade from a 5900X unless you need so many cores.


Exactly my thought, especially since my curve is very stable with all cores doing -20 apart of C0 and C1 who go -10 and -15. Looks a keeper to me.


----------



## byDenoso

Veii said:


> LN2 toggles will lift couple of peak-voltage restrictions, but board-power limiters have to be set between vendors on different places (sometimes CBS sometimes AMD OVERCLOCKING)


What LN2 option do?
Will it improve anything on CPU/FCLK Overclocking?


----------



## fqqf

hi guys, i have 2 questions
1) Is my RAM working correctly? (error below CRC ERR SMBus 0...)
2) are these real b-die? and 1.5 dram voltage safe for this ram? ram: patriot viper blackout 4133c18xmp PVB416G413C8K
thanks<3


----------



## ManniX-ITA

Blameless said:


> I'm playing in DX12, 1440p, maximum settings, no RT; just played a mission and the average frame rate was ~142. GPU (a 6800 XT) utilization is normally maxed out, but when mechs spawn, or firefights get heated, the GPU utilization will dip down as low as 60-70%.


I'm not sure but I think that map is small, have to try another one. This one is the biggest size in the game.



fqqf said:


> 1) Is my RAM working correctly? (error below CRC ERR SMBus 0...)


It shouldn't be a big problem, it's only an error reading the XMP data.



fqqf said:


> 2) are these real b-die? and 1.5 dram voltage safe for this ram? ram: patriot viper blackout 4133c18xmp PVB416G413C8K


B-die finder doesn't find the exact SKU but it's suggesting a similar one which is B-die.
1.5V is not an issue if it's B-die


----------



## badger2k

Hello everyone,

i just got my new gskill Kit and so far it seems like a good bin. I was running Karhu overnight and got a pesky error at 30462% .

Does someone have a recommedation how to tackle this error. My first thought was to increase vDimm about 0,02v.
What do you guys think?

cld0_vddp 0.960 is needed to get tPHYRDL to train 26/26










Thanks in advance for any suggestions!


----------



## ManniX-ITA

badger2k said:


> Does someone have a recommedation how to tackle this error. My first thought was to increase vDimm about 0,02v.
> What do you guys think?


I don't think it's VDIMM, you would have get the error much earlier.
I think you should raise VSOC.
It may be too close to IOD with vdroop.
Add 20mV and test again.


----------



## ManniX-ITA

Taraquin said:


> Check out i2hard on youtube, think they test 7 games, Cyberpunk, SOTTR etc.


Thanks, I like their testing very nice!

At the end the real gap is much less.
The 5800X configuration is almost stock.
And they also exclude Total War which is too much biased on Intel.










5% AVG difference on same DDR4 which I guess it can be reduced with a more optimized config.
DDR5 seems to really help on gaming.
The big difference is on 1%/0.1% which can be over 15% better, less stuttering is really a big advantage.

They also test OC with again the 5800X set pretty basic but with CO.









I guess here too with a better config the gap could be less but it's probably still double than without OC.
And the better 1%/0.1% are even better.

Just looking at the gameplay recordings it's obvious the 12700K with DDR5 is definitely superior.

Thought temps and power of the 12700K OC would be worst there's probably more headroom.
I'm really curious to see some DDR5 in action...


----------



## badger2k

ManniX-ITA said:


> I don't think it's VDIMM, you would have get the error much earlier.
> I think you should raise VSOC.
> It may be too close to IOD with vdroop.
> Add 20mV and test again.


Alright, i'm now at 1.12 VSOC in BIOS.

Gets me 1.125 as SET and switches between 1.104 to 1.1063 under load










i will run another overnight test and report back.

Thanks


----------



## ManniX-ITA

badger2k said:


> Gets me 1.125 as SET and switches between 1.104 to 1.1063 under load


Looks good, 60mV gap is safe enough to be sure that's not a problem.


----------



## Taraquin

ManniX-ITA said:


> Thanks, I like their testing very nice!
> 
> At the end the real gap is much less.
> The 5800X configuration is almost stock.
> And they also exclude Total War which is too much biased on Intel.
> 
> View attachment 2551754
> 
> 
> 5% AVG difference on same DDR4 which I guess it can be reduced with a more optimized config.
> DDR5 seems to really help on gaming.
> The big difference is on 1%/0.1% which can be over 15% better, less stuttering is really a big advantage.
> 
> They also test OC with again the 5800X set pretty basic but with CO.
> View attachment 2551755
> 
> 
> I guess here too with a better config the gap could be less but it's probably still double than without OC.
> And the better 1%/0.1% are even better.
> 
> Just looking at the gameplay recordings it's obvious the 12700K with DDR5 is definitely superior.
> 
> Thought temps and power of the 12700K OC would be worst there's probably more headroom.
> I'm really curious to see some DDR5 in action...


Yeah, it's often not ADL itself, but DDR5 really shines in Cyberpunk for instance. I general newer games seems to often prefer BW and ADL with faster ram (DDR4 4000-4300 AND DDR5 6000+) shines then.


----------



## Audioboxer

badger2k said:


> Hello everyone,
> 
> i just got my new gskill Kit and so far it seems like a good bin. I was running Karhu overnight and got a pesky error at 30462% .
> 
> Does someone have a recommedation how to tackle this error. My first thought was to increase vDimm about 0,02v.
> What do you guys think?
> 
> cld0_vddp 0.960 is needed to get tPHYRDL to train 26/26
> 
> View attachment 2551751
> 
> 
> Thanks in advance for any suggestions!


Happening that late I would guess powerdown issues, likely resistances.

I'd say increase ClkDrvStr to 30 or 40, and maybe also try CkeDrvStr at 30.

Try your IOD nearer 1v as well so it's a bit further away from the VSOC value.


----------



## Blameless

beluoc2 said:


> Does anyone have any tips on tightening the timings for my ram? It's been a frustrating few days. The default xmp profiles do not work on my motherboard. It seems to be extremely voltage sensitive. I tried one of the calculators here to no avail. The type of die is unknown to me. It has a DWDR1023xa1 printed on the ic along with a qr code. Here are the specs I can read and the timings that seem to be stable so far. I believe the VDDG CCD is .00V
> View attachment 2551653
> View attachment 2551654


SoC voltage is too low and CLDO VDDG IOD is too high. You want the former ~50mV above the latter.

That's Hynix CJR or DJR, probably DJR. Timings need some work, but fix the basic voltages first. Also, with GDM enabled, those odd primaries are getting rounded up to the next even number.



ManniX-ITA said:


> I'm not sure but I think that map is small, have to try another one. This one is the biggest size in the game.


I'll fire up an instant action game in a larger map and see how my setup behaves.


----------



## Blameless

@ManniX-ITA

Tried a couple of huge maps, and frame rates are a bit lower, but I am much _more_ consistently GPU limited...pretty much 95-99% the entire time. CPU utilization is generally quite low, and only spikes when enemies spawn or there are craptons of missiles in the sky, but because the frame rate is lower, it's barely enough to cause a CPU limitation.

The CPU utilization and frame rates you reported seeing make me think you're running the D3D11 renderer.


----------



## ManniX-ITA

Blameless said:


> The CPU utilization and frame rates you reported seeing make me think you're running the D3D11 renderer.


Not sure how to tell... I had AF telling me but I don't see it now.

Did also a quick google search and it seems common with nVidia 3080 and up to get 50-60% GPU utilization.
I get 99% only inside the dropship...
Loaded another map and it's around 50-60% for 120-140 fps.
PGI really sucks...

Here my settings for Display, do you have smooth fps enabled?



Spoiler: Display


----------



## Blameless

ManniX-ITA said:


> Not sure how to tell... I had AF telling me but I don't see it now.
> 
> Did also a quick google search and it seems common with nVidia 3080 and up to get 50-60% GPU utilization.
> I get 99% only inside the dropship...
> Loaded another map and it's around 50-60% for 120-140 fps.
> PGI really sucks...
> 
> Here my settings for Display, do you have smooth fps enabled?
> 
> 
> 
> Spoiler: Display
> 
> 
> 
> 
> View attachment 2551811
> 
> View attachment 2551812
> 
> View attachment 2551813


No smooth frame rate or fidelity FX sharpening enabled for me.

I thought the most recent version of the game had a D3D12 toggle somewhere, but I'm not seeing it. I've been forcing it via command line arguments.

"\MW5Mercs\Binaries\Win64\MechWarrior-Win64-Shipping.exe" -d3d12 -notexturestreaming -preferredprocessor=1 -useallavailablecores -malloc=system

You should only really need to add "-d3d12", but -notexturestreaming did impove smoothness a bit for me and -preferredprocessor being set to my best core also seems to have helped slightly, though that could be placebo.

Also turns out I have some custom Engine.ini settings to fix problems I perceieved with the temporal AA implementation and the amount of blurring it was causing, which might skew frame rates somewhat, but shouldn't do much of anything to CPU limitation.


----------



## ManniX-ITA

ManniX-ITA said:


> do you have smooth fps enabled?


Ok it caps to 60 fps...
Goes a bit better with small maps and DLSS Quality enabled.
50-60% GPU usage also on dogfights and 120-160 fps.

I had forgot the reason I stopped playing was that with the new version my mods were not compatible.
So a bit of the mess was from them, loaded another map and it was crashing...



Blameless said:


> Also turns out I have some custom Engine.ini settings to fix problems I perceieved with the temporal AA implementation and the amount of blurring it was causing, which might skew frame rates somewhat, but shouldn't do much of anything to CPU limitation.


Yes I just added some stuff in the ini files but it didn't change the GPU utilization.



Blameless said:


> "\MW5Mercs\Binaries\Win64\MechWarrior-Win64-Shipping.exe" -d3d12 -notexturestreaming -preferredprocessor=1 -useallavailablecores -malloc=system


Tried and doesn't change much, bit smoother maybe.
But with -d3d12 the fps tanks to 40-80 fps... they definitely messed up with nVidia.
The CPU is barely used, from the power usage per core they are about 25%-50% usage all, mostly 3-8W.


----------



## KedarWolf

badger2k said:


> Hello everyone,
> 
> i just got my new gskill Kit and so far it seems like a good bin. I was running Karhu overnight and got a pesky error at 30462% .
> 
> Does someone have a recommedation how to tackle this error. My first thought was to increase vDimm about 0,02v.
> What do you guys think?
> 
> cld0_vddp 0.960 is needed to get tPHYRDL to train 26/26
> 
> View attachment 2551751
> 
> 
> Thanks in advance for any suggestions!


Getting an error that far in is likely a temperature issue. Try putting a RAM fan over the RAM.


----------



## badger2k

KedarWolf said:


> Getting an error that far in is likely a temperature issue. Try putting a RAM fan over the RAM.


I have two Noctua 40mm blowing over my Sticks . Max temp was 40.6°C.


----------



## ManniX-ITA

badger2k said:


> I have two Noctua 40mm blowing over my Sticks . Max temp was 40.6°C.


If raising VSOC doesn't work try with a bump in VDIMM as planned.
tRFC 252 is very borderline at 1.5V and could case sporadic errors after a long time testing.


----------



## vegetagaru

vegetagaru said:


> Hello all ive been reading a lot here and been finding a lot of useful info, but im on a point that im trying to understand whats happening and cant find the problem.
> im sitting on a new 5900x (stepping 2) and some new ram too (F4-4400c17D-32GVK) funny thing is that the label and in thaiphoon says "F4-4400C17-16GVK" (i bought this coz was an amazing deal and still with warranty from shop)
> 
> anyway atm on cpu i have no clock almost everything is on auto (i had curve but since im having a problem i placed all on auto)
> in tearms of ram i had to set VDDG CCD/IOD to 1(at least) atm is on 1.05 or else wouldn't post (when setting freq and FCLK at same speeds)
> also in tearms of ram i set up the 16/16/16/16/34/50 timmings and tRFC to be a higher value and since i read somewhere that needs to be a multiple of tRC i placed 450
> 
> View attachment 2548496
> 
> 
> now my problem..... i "dont have any problem" in some games it keeps crashing into windows(with no errors or BSOD) when i had my old 2700x on a 3200 cl4, if this would happen i knew it was ram clock problem, but now im trying to mess a lot with it and still didnt found solution, i even tried to place everything(timings) on auto and still same problem.
> 
> in tearms of WHEA error dunno if considered as error but it appears as warming very occasionally (not when game crashes into windows):
> View attachment 2548497
> 
> 
> if someone could try help me i would appreciate it, and thank you in advance.


a update on my warnings:

so i tried a lot of stuff and couldn't get rid of the warnings

this week i saw that there was a update for my CH7 from "V2 PI 1.2.0.3 Patch C" to "V2 PI 1.2.0.6b"

and all my "problems" went away no more warnings

this is my current settings: (far from optimized but i will mess with it and post the results)


----------



## ManniX-ITA

vegetagaru said:


> this is my current settings: (far from optimized but i will mess with it and post the results)


You memory profile is a punch in the eye...
Just tell which VDIMM you want to run and ask for a 3800 MHz profile here.

Raise the VSOC, is too low, set it at least to 1.1V.
I don't think it's already at 1.1V cause otherwise the LLC droop would be massive.
Set VDDP to 0.900.

Then you should be at the right ram bandwidth and around 54ns for latency.
It'll be tons better.


----------



## vegetagaru

ManniX-ITA said:


> You memory profile is a punch in the eye...
> 
> Just tell which VDIMM you want to run and ask for a 3800 MHz profile here.
> 
> 
> Raise the VSOC, is too low, set it at least to 1.1V.
> 
> I don't think it's already at 1.1V cause otherwise the LLC droop would be massive.
> 
> Set VDDP to 0.900.
> 
> 
> Then you should be at the right ram bandwidth and around 54ns for latency.
> 
> It'll be tons better.


thank you for your help
i would think that would be a punch in the eye thats why i asked for help "earlier" xD

from what you guys told earlier i taught 1.05 soc voltage would be ok (i was runing 1.15 earlier) but now i realize that my values on CCD/IOD are not the ones i was thinking that was using (i taught i was on 0.9 not 1)
also i set the vddp to auto and just noticed that is to high

i need to pay more attention to stuff.

again thanks for help, regarding the the vddim that i want to run its simple awnser i guess max performance without sacrificing hardware longevity and stable XD

-----------
i see that in screenshot ccd and iod seems to be at 1 but on bios they are set to be 0.95/0.9 cant figure why its showing 1

i set the vddp as you said and the soc to 1.1 heres the result:


----------



## ManniX-ITA

vegetagaru said:


> i see that in screenshot ccd and iod seems to be at 1 but on bios they are set to be 0.95/0.9 cant figure why its showing 1


Probably you are using a BIOS with AGESA 1.2.0.5 which has the VDDG bug, fixed at 1000mV.

For the RAM any profile at 1.5V should be more than safe.
My 4000CL14 kit which is also a Ripjaws is stock 1.55V.


----------



## ManniX-ITA

vegetagaru said:


> "V2 PI 1.2.0.6b"


I now see it should be 1.2.0.6b, really weird...
It's not supposed to have this bug, only the VID cap.


----------



## vegetagaru

ManniX-ITA said:


> Probably you are using a BIOS with AGESA 1.2.0.5 which has the VDDG bug, fixed at 1000mV.
> 
> For the RAM any profile at 1.5V should be more than safe.
> My 4000CL14 kit which is also a Ripjaws is stock 1.55V.


im using the 1.2.0.6b as i was having problems with the 1.2.0.3c

my 4400 kit advertises as 1.5v so yeah i can assume its safe X) could you point me a profile ? i was thinkin on following the dram calc as when i load the XMP into it for the freq im using it sugests to change alot of stuff:


----------



## Taraquin

vegetagaru said:


> thank you for your help
> i would think that would be a punch in the eye thats why i asked for help "earlier" xD
> 
> from what you guys told earlier i taught 1.05 soc voltage would be ok (i was runing 1.15 earlier) but now i realize that my values on CCD/IOD are not the ones i was thinking that was using (i taught i was on 0.9 not 1)
> also i set the vddp to auto and just noticed that is to high
> 
> i need to pay more attention to stuff.
> 
> again thanks for help, regarding the the vddim that i want to run its simple awnser i guess max performance without sacrificing hardware longevity and stable XD
> 
> -----------
> i see that in screenshot ccd and iod seems to be at 1 but on bios they are set to be 0.95/0.9 cant figure why its showing 1
> 
> i set the vddp as you said and the soc to 1.1 heres the result:
> 
> View attachment 2551843


Can you set vddg iod higher? Try 1.05v. Set scls to 4, rrdl to 6, wr to 12, rtp to 6, wtrs/l to 4/12, rfc to 272.


----------



## ManniX-ITA

vegetagaru said:


> could you point me a profile ?


I don't have a 1.5V profile... all higher

Can suggest you something relatively safe


----------



## vegetagaru

ManniX-ITA said:


> I don't have a 1.5V profile... all higher
> 
> Can suggest you something relatively safe
> 
> View attachment 2551848


thank you for your time.

its not posting with those, and if it manages to show bios info, it freezes. i would say that this occurs when i try to disable GDM


----------



## ManniX-ITA

vegetagaru said:


> thank you for your time.
> 
> its not posting with those, and if it manages to show bios info, it freezes. i would say that this occurs when i try to disable GDM


Weird it should work...
Set tRDWR and tWRRD in Auto to see if they are set to 9/2 or something different.
If it's different set it manually
If doesn't work try with 1.52V


----------



## Bloax

If this 4400 17-18-18 1.5v (?) kit requires 1.5v to run 3800 16-16-16 I'm gonna laugh real hard -








this dumbass cursed 2x16 4266 17-18-18 1.5v kit I have here requires 0.06v per 100 MCLK (+200 MT/s) and still complains about overvoltage at 4000 15-15-15 1.42v

RCDRD is usually the most voltage-demanding setting, and even that is +/- 0.09v per tick. So if those kits are similar, you'd be looking at 3800 16-16-16 running around 1.28v-1.32v


----------



## vegetagaru

ManniX-ITA said:


> Weird it should work...
> Set tRDWR and tWRRD in Auto to see if they are set to 9/2 or something different.
> If it's different set it manually
> If doesn't work try with 1.52V


ok so i placed it on auto and 18/7 poped, then i placed manually the 18/7 and booted:


----------



## ManniX-ITA

vegetagaru said:


> ok so i placed it on auto and 18/7 poped, then i placed manually the 18/7 and booted:


It's already a much brighter picture.
Not sure why the latency is still so high.
Could be something in background.

Now if you want to squeeze more is better you know how to test.

Start with 25 cycles of TM5 1usmus config:





TM5_1usmusv3_25cycles.zip







drive.google.com


----------



## ManniX-ITA

Bloax said:


> If this 4400 17-18-18 1.5v (?) kit requires 1.5v to run 3800 16-16-16 I'm gonna laugh real hard


I'd be surprised as well 
It's just to establish a baseline.

Once is tested with TM5 it can be improved further.
I was hoping someone would jump in with a good profile at 1.5V.


----------



## Audioboxer

Bloax said:


> If this 4400 17-18-18 1.5v (?) kit requires 1.5v to run 3800 16-16-16 I'm gonna laugh real hard -
> View attachment 2551864
> 
> this dumbass cursed 2x16 4266 17-18-18 1.5v kit I have here requires 0.06v per 100 MCLK (+200 MT/s) and still complains about overvoltage at 4000 15-15-15 1.42v
> 
> RCDRD is usually the most voltage-demanding setting, and even that is +/- 0.09v per tick. So if those kits are similar, you'd be looking at 3800 16-16-16 running around 1.28v-1.32v


Ooft, I'd hope not. A couple of months back when I was playing around with profiles I managed tCL16 at 1.29v lol


----------



## badger2k

ManniX-ITA said:


> If raising VSOC doesn't work try with a bump in VDIMM as planned.
> tRFC 252 is very borderline at 1.5V and could case sporadic errors after a long time testing.


Well, right around time :/
I will try ClkDrvStr 30 now, i guess.

Cpu seems happy with the VSOC bump tho, runs snappy


----------



## Audioboxer

badger2k said:


> Well, right around time :/
> I will try ClkDrvStr 30 now, i guess.
> 
> Cpu seems happy with the VSOC bump tho, runs snappy
> 
> View attachment 2551891


Higher VSOC can actually eat into your CPU power budget but you're not likely to be high enough to do that. Still, at 3733 VSOC should happily run on AUTO for you. Meaning, it should be IOD you drop a bit.

Errors that late in are either heat or powerdown. tRFC through heat, but your temps seem fine. 42 degrees and above is usually where tRFC being low starts to freak out. ClkDrvStr to 30 or 40 is a good idea with 1T GDM disabled.

Then try CkeDrvStr at 30 and finally lowering ProcODT.

Your SCLs are likely best at 4 for better read/write/copy performance. Nearly every time I see someone running 2 these days I tell them benchmark at 4 and they get a better AIDA result.










598xx is the highest I've ever gotten in AIDA, that drops a few hundred points with SCLs at 2.


----------



## badger2k

Audioboxer said:


> Higher VSOC can actually eat into your CPU power budget but you're not likely to be high enough to do that. Still, at 3733 VSOC should happily run on AUTO for you. Meaning, it should be IOD you drop a bit.
> 
> Errors that late in are either heat or powerdown. tRFC through heat, but your temps seem fine. 42 degrees and above is usually where tRFC being low starts to freak out. ClkDrvStr to 30 or 40 is a good idea with 1T GDM disabled.
> 
> Then try CkeDrvStr at 30 and finally lowering ProcODT.
> 
> Your SCLs are likely best at 4 for better read/write/copy performance. Nearly every time I see someone running 2 these days I tell them benchmark at 4 and they get a better AIDA result.
> 
> View attachment 2551893
> 
> 
> 598xx is the highest I've ever gotten in AIDA, that drops a few hundred points with SCLs at 2.


SCL's at 4 results in around 100MB/s less read, maybe a tad more in Copy and 0,1ns less latency. Maybe SCL at 4 is better with Dual Rank.
Thinking about keeping SCLs at 4.

Lowering VDDG_IOD results quickly in sluggish mouse input and a tiny bit less scores in yCruncher and Aida. Also games feel not as responsive.
Sadly my CPU has the infamous "FCLK HOLE" at 1900 and anything above that throws WHEA's quick.
1867 FCLK really feels like the edge of stability here, as it is also very power hungry. At least above average with 1050 IOD needed.

But I will try different combinations of VSOC and FCLK again and try to lower them a bit.
cld0_vddp 0.960 is needed to train tPHYRDL at 26/26 at 3733cl14 and 3666cl14. CL 13/15 train fine with vddp at 0.900 

PBO on AGESA 1203 igot around +150 with negative CO 10/5/20/20/20/5. I havent optimized on AGESA past 1205, yet.
Chip seems decent but the IMC is a bit "frustrating" to work with.

Also, how much should i worry about SOC voltage stepping?


----------



## chucky27

ManniX-ITA said:


> Good luck. Backup your data
> Use y-cruncher to test all core and CoreCycler for single core test.


Thanks. So far I seem to be relatively lucky. B2 5950x @ stock seems to be stable (running 32GB 3400CL16 ECC RAM).
Probably not the best bin (bronze-silverish, can't confirm as CTR is not working saying CPU is not supported for some reason), but have CO running -10 on CCD1 and -15 on CCD2 which bumped CB scores a bit. Doing individual core tuning is too much for me, esp knowing that I would have to redo it with new AGESAs. Default/Auto voltages seemed to be high [email protected], [email protected], so I've set them to manual closer to what I had on 3700x VSOC at 1.05 VDDP 0.91 VDDG 0.96.


----------



## vegetagaru

ManniX-ITA said:


> It's already a much brighter picture.
> Not sure why the latency is still so high.
> Could be something in background.
> 
> Now if you want to squeeze more is better you know how to test.
> 
> Start with 25 cycles of TM5 1usmus config:
> 
> 
> 
> 
> 
> TM5_1usmusv3_25cycles.zip
> 
> 
> 
> 
> 
> 
> 
> drive.google.com


regarding latency yeah dont know either dont have much background stuff running but i will try to turn off to test it out again

thanks i will try and mess with it a bit


----------



## Blameless

ManniX-ITA said:


> I'm temperature limited too but this sample loves voltage.
> Sometimes a small bump doesn't raise much temps but gives a huge boost.


Did some more experimenting with a positive voltage offset, and I'm having good results, mostly in conjunction with disabling CPPC. I've tried to leave CPPC on in the past as is seemed to help with lightly threaded tests, but there are clearly some scheduling issues going on with some of my CPU limited games where the fused CPPC order is used in preference to the actual performance of my 5800X sample's cores, resulting in my actual best core not having anything scheduled to it half the time.

Anyway, a +20mV offset allows my CPPC disabled single core results to match the CPPC enabled ones, while provided a moderate boost to multi-core scores at the same time and more run to run consistency in benches. With CPPC enabled, the positive offset was much less consistently beneficial.


----------



## ManniX-ITA

Blameless said:


> Anyway, a +20mV offset allows my CPPC disabled single core results to match the CPPC enabled ones, while provided a moderate boost to multi-core scores at the same time and more run to run consistency in benches. With CPPC enabled, the positive offset was much less consistently beneficial.


I've played a bit with offset on mine but didn't get better results.
Negative offset is bad, positive didn't change anything, got worse at some point going up.

Didn't check together with CPPC.
Will see what happens


----------



## PJVol

Blameless said:


> where the fused CPPC order is used in preference to the actual performance of my 5800X sample's cores, resulting in my actual best core not having anything scheduled to it half the time


Just out of curiosity, what did you mean under "actual best core" and "actual performance" ?


----------



## ManniX-ITA

chucky27 said:


> Thanks. So far I seem to be relatively lucky. B2 5950x @ stock seems to be stable (running 32GB 3400CL16 ECC RAM).
> Probably not the best bin (bronze-silverish, can't confirm as CTR is not working saying CPU is not supported for some reason), but have CO running -10 on CCD1 and -15 on CCD2 which bumped CB scores a bit. Doing individual core tuning is too much for me, esp knowing that I would have to redo it with new AGESAs. Default/Auto voltages seemed to be high [email protected], [email protected], so I've set them to manual closer to what I had on 3700x VSOC at 1.05 VDDP 0.91 VDDG 0.96.


Nice!
I'm still waiting my replacement.
And still bitching with the AMD Rep telling me that if the next RMA doesn't work it's my fault...

If it's working with -10 on CCD1 it's already a good sign.

The voltages are really low.
Could be your sample is not hungry.

But I would check comparing Geekbench 5 scores.
Run it at higher voltages and see if there's a difference.


----------



## Taraquin

chucky27 said:


> Thanks. So far I seem to be relatively lucky. B2 5950x @ stock seems to be stable (running 32GB 3400CL16 ECC RAM).
> Probably not the best bin (bronze-silverish, can't confirm as CTR is not working saying CPU is not supported for some reason), but have CO running -10 on CCD1 and -15 on CCD2 which bumped CB scores a bit. Doing individual core tuning is too much for me, esp knowing that I would have to redo it with new AGESAs. Default/Auto voltages seemed to be high [email protected], [email protected], so I've set them to manual closer to what I had on 3700x VSOC at 1.05 VDDP 0.91 VDDG 0.96.


You may not need to redo much with new agesas, it's usually +/-1-2 on some cores. They biggest issue with CO is if your CPU has trouble with low idle voltages, load voltages can be found in most cases with core cycler, occt etc. I bet some of your cores can do -30 and if you find a good agesa, why update? I don't think there will be new features that we need  I'm on 1.2.0.3b and so far I have had no incentive to update to 1.2.0.4/5/6b.


----------



## Audioboxer

__
https://www.reddit.com/r/overclocking/comments/t82ldy


__
https://www.reddit.com/r/overclocking/comments/tcfcfi

These topics were definitely interesting!


----------



## ManniX-ITA

Audioboxer said:


> These topics were definitely interesting!


Oh I'm definitely going to do it


----------



## Audioboxer

ManniX-ITA said:


> Oh I'm definitely going to do it


I would probably somehow short my board or make a mess of it so I was hoping some of you would do it first lol

Seeing as 4533 is the highest I can boot stable I am interested.


----------



## Taraquin

ManniX-ITA said:


> Oh I'm definitely going to do it


Maybe it will block whea19 from leaking out?


----------



## ManniX-ITA

Taraquin said:


> Maybe it will block whea19 from leaking out?


Highly doubt it 
But who knows, maybe less occurrences...


----------



## Blameless

ManniX-ITA said:


> Negative offset is bad, positive didn't change anything, got worse at some point going up.


+25mV was starting to hit diminishing returns or regress, so I left mine at +20mv. Seemed to be about 3% faster in 7-zip's benchmark (a moderate all-core load) than auto/zero and gained about 100 points in the multi-threaded CPU-Z bench.



PJVol said:


> Just out of curiosity, what did you mean under "actual best core" and "actual performance" ?


The core that holds the highest load clocks and delivers the actual best performance in testing (across a variety of loads), because it takes a much higher negative CO offset than any other. It also happens to be dead last in both the default fused ordering and in the CPPC preferred core ordering.

I was under the impression that Windows would actually be able to measure performance and use that to effectively schedule threads, but the "Maximum performance percentage" reported by "ACPI Collaborative Processor Performance Control" through "Microsoft-Windows-Kernel-Processor-Power" doesn't change with COs and seems to take precedence over actual performance. This problem is that the stock ordering is almost completely backwards on my sample, once my COs are fully tuned. My 'worst' core, according to CPPC, takes a -28 CO, but my 'best' core takes a -3, second best core -2, and third best core +3.

Leaving CPPC disabled entirely results in core 0 (my actual fastest core) being most commonly loaded first, and others filled almost randomly (which is still better than them being filled according to CPPC).

Also, inactive cores appear to downclock more reliably with CPPC disabled, probably because "Microsoft-Windows-Kernel-Processor-Power" isn't reporting a weirdly distorted scale for the min power state. With CPPC enabled, they sit around 2.8-3.6GHz when unloaded or lightly loaded. With CPPC disabled, they all fall down to 2.2GHz. This is with the same minimum processor power state of zero set in the advanced Power Management settings.


----------



## chucky27

ManniX-ITA said:


> The voltages are really low.
> Could be your sample is not hungry.
> But I would check comparing Geekbench 5 scores.
> Run it at higher voltages and see if there's a difference.


I presume you are talking about vsoc and vddx voltages. I usually test with CB and with too low vsoc voltages on 3700x the scores dropped and with current vsoc and CO scores went higher both for single and multi-core. But I will test with GB5 to make sure, thanks for suggestion. maybe it's because it's not that high @3400 and timings are relatively relaxed due to being low-mid tier b-die and ecc. So far with current CO idle is fine, no reboots and no WHEAs.


----------



## domdtxdissar

Audioboxer said:


> __
> https://www.reddit.com/r/overclocking/comments/t82ldy
> 
> 
> __
> https://www.reddit.com/r/overclocking/comments/tcfcfi
> 
> These topics were definitely interesting!


Something very wrong with that setup, all the numbers are way too low to be running at real 5100MT/s
Cant say i'm impressed when he cant even match regular 3600MT/s bandwidth numbers..

"5100"









vs 3600








We also have one guy in the x570s unify-x max thread which is allegedly running "5200MT/s" out of the box without any mods on the unify-x max motherboard together with a 3800x, which also is under-performing..

Think this all boils down to a agesa bug or something, fantasy numbers that dont match the performance..


----------



## ManniX-ITA

chucky27 said:


> I presume you are talking about vsoc and vddx voltages. I usually test with CB and with too low vsoc voltages on 3700x the scores dropped and with current vsoc and CO scores went higher both for single and multi-core. But I will test with GB5 to make sure, thanks for suggestion. maybe it's because it's not that high @3400 and timings are relatively relaxed due to being low-mid tier b-die and ecc. So far with current CO idle is fine, no reboots and no WHEAs.


Yes the difference is going to be more subtle but check if there's a gain. 
CB is a workload too much specific.
With GB5 you can see the effect of different VDDG voltages.
In particular AES-XTS test for CCD, the rest more IOD.



Blameless said:


> +25mV was starting to hit diminishing returns or regress, so I left mine at +20mv. Seemed to be about 3% faster in 7-zip's benchmark (a moderate all-core load) than auto/zero and gained about 100 points in the multi-threaded CPU-Z bench.


I was hoping to gain those extra 100 points on CPU-z MT but it's like there's a hard ceiling...



Blameless said:


> I was under the impression that Windows would actually be able to measure performance and use that to effectively schedule threads


No it follows strictly the CPPC tags.



Blameless said:


> doesn't change with COs and seems to take precedence over actual performance. This problem is that the stock ordering is almost completely backwards on my sample, once my COs are fully tuned. My 'worst' core, according to CPPC, takes a -28 CO, but my 'best' core takes a -3, second best core -2, and third best core +3.


The CO count by itself is telling you nothing about the performances.
The best core at -3 is supposed to be better than any other core at -30. Ideally...
Unfortunately if something went wrong during test & serialization it's a big problem.
You can only fix it with Hydra Pro which is overriding affinities.



Blameless said:


> Leaving CPPC disabled entirely results in core 0 (my actual fastest core) being most commonly loaded first, and others filled almost randomly (which is still better than them being filled according to CPPC).


This is generally bad, even if it's the best core.
Core 0 has to run a lot of workloads that can't be moved to other cores, like legacy IPC.
But if the situation is so bad, maybe it's better.



Blameless said:


> Also, inactive cores appear to downclock more reliably with CPPC disabled, probably because "Microsoft-Windows-Kernel-Processor-Power" isn't reporting a weirdly distorted scale for the min power state. With CPPC enabled, they sit around 2.8-3.6GHz when unloaded or lightly loaded. With CPPC disabled, they all fall down to 2.2GHz. This is with the same minimum processor power state of zero set in the advanced Power Management settings.


That's probably cause it reverts to the Windows scheduler software throttling.
In general is worse cause the cores are not really sleeping.
Did you check with HWInfo if they go into C6 mode when idling?
Check also the minimum power usage per core; if they are not sleeping it'll be higher.



domdtxdissar said:


> Something very wrong with that setup, all the numbers are vay too low to be running at real 5100MT/s
> Cant say i'm impressed when he cant even match regular 3600MT/s numbers.. (?)


Yes, he should have run something a bit more higher clock than it was possible before instead.
But the fact that he can even boot into that with the Unify-X is interesting.
Anyway it's a mod that can be reverted pretty easy if it doesn't work


----------



## Blameless

ManniX-ITA said:


> The best core at -3 is supposed to be better than any other core at -30. Ideally...
> Unfortunately if something went wrong during test & serialization it's a big problem.


It takes maybe a 15 point CO differential for my worst core to consistently out clock my best one.



ManniX-ITA said:


> In general is worse cause the cores are not really sleeping.
> Did you check with HWInfo if they go into C6 mode when idling?
> Check also the minimum power usage per core; if they are not sleeping it'll be higher.


When actually idle they still enter C6, drop to 0.225v reported VID and consume less than 3-5mW, according to HWiNFO.

Edit, have been testing stuff all morning, this is HWiFO after about two hours of mixed use:


----------



## ManniX-ITA

Blameless said:


> When actually idle they still enter C6, drop to 0.225v reported VID and consume less than 3-5mW, according to HWiNFO.


Yes, they definitely go into sleep mode and pretty well.
I'll check what happens with mine.

On the 5950X if the cores were going down too much they were too slow to boost up and the system was a bit sluggish.
CPU-z score was starting low and going up gradually.
Which Power Plan are you using?


----------



## Audioboxer

domdtxdissar said:


> Something very wrong with that setup, all the numbers are vay too low to be running at real 5100MT/s
> Cant say i'm impressed when he cant even match regular 3600MT/s bandwidth numbers..
> 
> "5100"
> View attachment 2551978
> 
> 
> vs 3600
> View attachment 2551979
> 
> We also have one guy in the x570s unify-x max thread which is allegedly running "5200MT/s" out of the box without any mods on the unify-x max motherboard together with a 3800x, which also is under-performing..
> 
> Think this all boils down to a agesa bug or something, fantasy numbers that dont match the performance..


You would know better than me, but yeah, I was disappointed in those numbers lol.

At 4533 I was down at 56.3ns.


----------



## Blameless

ManniX-ITA said:


> Which Power Plan are you using?


At the moment I'm using Ultimate Performance with the minimum processor state manually set to 0%.

I was using Balanced the other day, with very similar results.


----------



## byDenoso

Veii said:


> Random idle reboots are complicated
> 
> Try enabling in AMD OVERCLOCKING, UncoreOC mode
> - that will allow for VDDG voltages to actually do anything, not be ignored by FIT  Matisse shenanigans
> Keep distance of voltages at least 50mV apart, sometimes 75mV ~ this was very important on Matisse days


I Finally Fixed the Random Reboots tweaking vddg/vddp voltages
cldo_VDDP: 1060mv (I know its high, but it give me better scores both in AIDA and SI SANDRA benchs)
Vddg CCD: 938mv (Anything higher than that causes random reboots)
VDDG IOD: 1080mv (i'm trying to lower, its a bit high in my opinion, lowering that i'll be able to lower SOC voltage too)
VSOC: 1,125v


----------



## PJVol

Blameless said:


> The core that holds the highest load clocks and delivers the actual best performance in testing (across a variety of loads), because it takes a much higher negative CO offset than any other. It also happens to be dead last in both the default fused ordering and in the CPPC preferred core ordering.


Wow 
I have a feeling something isn't right with your setup or CPU (higjly unlikely).
Have you got some tests data for per-core loads similar to this?
CPPC rating is 3 2 4 1 1 5 (from core #0 to #5) and СО set to default.







i did a quick OCCT runs cycling cores with a small/extreme/steady SSE, AVX2 and AVX presets, and additional per-core CBR23 MT run, as a moderate workload.

Changing the core counts can balance their static power differences, but hardly affect its dynamic part, that is mostly what CPPC rating based on.
In other words, lowering CO count is pure overclocking, which raises the dynamic power per frequency increased, followed by raised temp. This is where the core quality matters.

It's hard to beleive your worst core can perform better than CPPC best rated one, unless something is broken.


----------



## chucky27

ManniX-ITA said:


> Nice!
> I'm still waiting my replacement.
> And still bitching with the AMD Rep telling me that if the next RMA doesn't work it's my fault...
> 
> If it's working with -10 on CCD1 it's already a good sign.
> 
> The voltages are really low.
> Could be your sample is not hungry.
> 
> But I would check comparing Geekbench 5 scores.
> Run it at higher voltages and see if there's a difference.


Tried GB 5.4.4 with both default/auto and custom voltages. Results are mixed, some scores got better, some got worse... AES got better on single core (but probably due to different cores being used) but worse on multi-core... results attached. Balanced plan was used in both runs with everything closed and no bg activity.


----------



## ManniX-ITA

chucky27 said:


> Tried GB 5.4.4 with both default/auto and custom voltages. Results are mixed, some scores got better, some got worse... AES got better on single core (but probably due to different cores being used) but worse on multi-core... results attached. Balanced plan was used in both runs with everything closed and no bg activity.


CCD at 1000mV is definitely too high.
IOD seems to be better at 1000mV.

MT scores are severely bottlenecked, I think you said your PBO limits are stock.
Normal AES-XTS score is 9500+.


----------



## ManniX-ITA

Blameless said:


> At the moment I'm using Ultimate Performance with the minimum processor state manually set to 0%.


Forgot I can't test without CPPC...
This MSI board disables all boosting and max clock is 3800 MHz.


----------



## chucky27

ManniX-ITA said:


> CCD at 1000mV is definitely too high.
> IOD seems to be better at 1000mV.
> 
> MT scores are severely bottlenecked, I think you said your PBO limits are stock.
> Normal AES-XTS score is 9500+.


hm... yes, I'm running stock PBO limits. My target is "no OC with maximum efficiency".
"Normal AES-XTS 9500+" - is it with stock settings and can slower memory affect it?


----------



## ManniX-ITA

chucky27 said:


> hm... yes, I'm running stock PBO limits. My target is "no OC with maximum efficiency".
> "Normal AES-XTS 9500+" - is it with stock settings and can slower memory affect it?


Not sure if/how much is affected by memory.
9500+ is for higher than stock limits, I'm not sure at stock what is the expect result
But if you want to fine tune the VDDG you can also set higher limits, like 280/165/215, test and then put back stock


----------



## Blameless

PJVol said:


> I did a quick OCCT run cycling cores with a small/extreme/steady SSE, AVX2 and AVX presets, and additional per-core CBR23 MT run, as a moderate workload.


I just did the OCCT core cycling run with AVX2 and SSE, with both stock PBO and my custom curves. I'll just post the SSE test as it shows a similar overall pattern to the AVX2 one.

Default PBO (approximate VID / core Clock / peak power) in physical order:
1.4v / 4.65GHz / 18.4w
1.42 / 4.675 / 19.3
1.42 / 4.725 / 18.9
1.41 / 4.7 / 18.4
1.43 / 4.725 / 20.2
1.4 / 4.7 / 18.7
1.43 / 4.675 / 20.2
1.39 / 4.6 / 18.4

Custom PBO:
1.45 / 4.875 / 21.5
1.41 / 4.725 / 18.6
1.4 / 4.725 / 19
1.4 / 4.75 / 19
1.44 / 4.8 / 20.4
1.39 / 4.7 / 18.7
1.42 / 4.7 / 20.3
1.39 / 4.625 / 18

CPPC order of the cores is 7, 2, 3, 6, 1, 5, 1, 4. The curves I use for my custom PBO settings at +100MHz maximum boost are -28, +3, -10, -18, -3, -10, -2, -3.

VID is only approximate as it was bouncing around. I used the core clock displayed during the middle of each 60 second loop, after it had stabilized, rather than peak reported core clocks as those often occurred outside the test entirely. I rounded power to the nearest tenth of a watt. They should be accurate enough, but something that produced a benchmark score that could be run on specific cores would surely be more precise.

Physical core #6 (in the 0-7 range) was consistently the hottest, but the rest seemed to track pretty closely with power.



PJVol said:


> In other words, lowering CO count is pure overclocking, which raises the dynamic power per frequency increased, followed by raised temp.


Yes, and my Core 0 (#7/8 according to AMD) overclocks better than any of the others.



PJVol said:


> It's hard to beleive your worst core can perform better than CPPC best rated one, unless something is broken.


CPPC numbering doesn't necessarily imply much about actual core quality. Every 5800X has a preferential order and would still have a preferential order, even if all the cores were so close as to be functionally identical. They probably try to match clocking ability to CPPC ordering, while also taking into account thermal factors (both in terms of leakage and relative location on the die), but they probably don't care much beyond making sure the part is stable at stock and largely fungible with regard to out-of-box performance vs. every other 5800X.

Regardless, on this sample, the -28 curve offset that I'm able to run stably on core #0 is evidently more than enough to overcome the default CPPC ordering.


----------



## chucky27

ManniX-ITA said:


> Not sure if/how much is affected by memory.
> 9500+ is for higher than stock limits, I'm not sure at stock what is the expect result
> But if you want to fine tune the VDDG you can also set higher limits, like 280/165/215, test and then put back stock


lowered vddg CCD to 0.95 , IOD left at stock 1v, vsoc @ 1.125V (zentiming shows as 1.09).
Benchmarks seem to be the same. Also noticed that geekbench is not consistent, one run its 7648 in AES, next run in a couple of min it's 8350, one run n-physics is 10901, next run it's 17888... cooling is adequate (U12A, 67C as max temp during bench).


----------



## ManniX-ITA

chucky27 said:


> Also noticed that geekbench is not consistent, one run its 7648 in AES, next run in a couple of min it's 8350, one run n-physics is 10901, next run it's 17888... cooling is adequate (U12A, 67C as max temp during bench).


There's something wrong then... yes the tests are very short and there's a margin of error from run to run.
But not 10900 to 17900, smells like something is working really bad.
Try with higher PBO limits maybe it's the throttling that is acting weird.
But I've never seen something like this even with stock limits.
Don't remember the scores but I've run it and it was pretty consistent.


----------



## chucky27

ManniX-ITA said:


> There's something wrong then... yes the tests are very short and there's a margin of error from run to run.
> But not 10900 to 17900, smells like something is working really bad.
> Try with higher PBO limits maybe it's the throttling that is acting weird.
> But I've never seen something like this even with stock limits.
> Don't remember the scores but I've run it and it was pretty consistent.


just ran couple more times and physics is staying at proper 17XXX,
maybe it was a cold run issue or windows activated some some scheduled tasks.
Looks ok now, so will leave it at that. Bumped vsoc in bios to 1.13, so it shows 1.10 in ZenTimings now.


----------



## PJVol

Blameless said:


> Default PBO (approximate VID / core Clock / peak power) in physical order:
> 1.4v / 4.65GHz / 18.4w
> 1.42 / 4.675 / 19.3
> 1.42 / 4.725 / 18.9
> 1.41 / 4.7 / 18.4
> 1.43 / 4.725 / 20.2
> 1.4 / 4.7 / 18.7
> 1.43 / 4.675 / 20.2
> 1.39 / 4.6 / 18.4


Have you really monitored "real" Core VID's? What is "approximate VID"? Core VID's should not fluctuate more than +/- 3mv



Blameless said:


> just post the SSE test as it shows a similar overall pattern to the AVX2 one.


My AVX2 result is a bit different from the rest, including predefined rankings (though not by much, so it might be just error) :
cppc: 4 3 5 1 2 6 
fuse: 4 3 5 2 1 6
----- experimental -------
SSE : 3 4 5 2 1 6
AVX : 4 3 5 1 2 6
AVX2: *2* 3 5 1 *4* 6
CB23: 3 4 5 2 1 6


Blameless said:


> CPPC order of the cores is 7, 2, 3, 6, 1, 5, 1, 4.


Yeah. If we believe your SSE results are accurate enough (assuming you tracked the *effective* *clocks* and *per-core VID's* (top sensors group) in HWInfo "*snapshot polling*" mode), the CPPC rating is a mess then. Does reported "fuse" rating differes from the CPPC one?


----------



## Blameless

PJVol said:


> Have you really monitored "real" Core VID's? What is "approximate VID"? Core VID's should not fluctuate more than +/- 3mv


The VIDs (top sensor group) being reported during the test were all over the place, at least +/-25mV. The active cores were evidently requesting very different voltages across the duration of the test. I picked the middle-ish figure during the most stable portion of each test.



PJVol said:


> My AVX2 result actually misfits the rest ones including predefined :
> cppc: 4 3 5 1 2 6
> fuse: 4 3 5 2 1 6
> ----- experimental -------
> SSE : 3 4 5 2 1 6
> AVX : 4 3 5 1 2 6
> AVX2: *2* 3 5 1 *4* 6
> CB23: 3 4 5 2 1 6


From your charts, that looks like it could have something to do with temperature.



PJVol said:


> Does reported "fuse" rating differes from the CPPC one?


Other than not duplicating the "1" entry, no.

*Edit:* I was reading that entry wrong. It's labled 1-8 in the order from most to least preferred core, not listing the cores in order with a perf #.
However, I just noticed that my core performance order in HWiNFO's main window doesn't match either my CPPC preferred or fused core order:


----------



## PJVol

Blameless said:


> The VIDs (top sensor group) being reported during the test were all over the place, at least +/-25mV


That's because you didn't tell hwinfo to poll SMU, otherwise god only knows what these reported values supposed to mean, and obviously are influenced by the "observer" effect.
Just check "Snapshot CPU Polling" checkbox before start sensors panel.


----------



## Blameless

PJVol said:


> That's because you didn't tell hwinfo to poll SMU, otherwise god only knows what these reported values supposed to mean, and obviously are influenced by the "observer" effect.
> Just check "Snapshot CPU Polling" checkbox before start sensors panel.
> View attachment 2552038


Well, that certainly makes the VID's easier to read, but my fastest core with my best stable CO settings is still my least prefered (#7/8) core according to the fused and CPPC entries:









Image take at the beginning of the second OCCT SSE loop as it cycled back to the first core.

Testing AVX2 now.

Edit:









AVX2 is getting a bit toasty and the clocks on the second cycle a bit lower than the first and the ordering changed a bit, but core 0 was still fastest.


----------



## blodflekk

I updated my dark hero to bios 4006, up from 4004 and I'm no longer VID capped at 1.4v which is great. So I went to run core cycler again to see what had changed and I'm not getting an error, unable to set affinity to core 16. Can anyone help me fix this ?


----------



## ArchStanton

blodflekk said:


> core 16


Do you mean core 15, since Core 0 exists?


----------



## Owterspace

Its been nice using my 5600X again. For testing I have a custom curve set for my fans, but when I am not testing, I can run them on the silent profile and it is blissful because they stay quiet 

5900X is a beast.


----------



## blodflekk

ArchStanton said:


> Do you mean core 15, since Core 0 exists?


Yes I just realized my mistake. I copied CPPC cores from hwinfo not realizing they were mislaelled


----------



## PJVol

Blameless said:


> AVX2 is getting a bit toasty and the clocks on the second cycle a bit lower than the first and the ordering changed a bit, but core 0 was still fastest.


Considering its count -28, that's not a big surprise, rather the low count itself is alarming a bit. Are you sure CPU is stable with #[email protected] in *allcore* workloads, such as y-cruncher stress test suite?

I unfortunately can't gather meaningful per-core data, since even in AVX2 test, 4 out of 6 cores are limited by Fmax, such that the core VID dropped way below what its count suggested.


----------



## Blameless

PJVol said:


> Considering its count -28, that's not a big surprise, rather the low count itself is alarming a bit. Are you sure CPU is stable with #[email protected] in *allcore* workloads, such as y-cruncher stress test suite?


Yes. I've tested these curves exhaustively and y-cruncher is one of the tests I use most heavily. Stability is always my first priority.

If I increase the boost override past +100MHz, I do have to reduce the negative offset on core 0, but not as fast as I have to increase the positive offset on core 1, or reduce some of the other negative offsets.



PJVol said:


> I unfortunately can't gather meaningful per-core data, since even in AVX2 test, 4 out of 6 cores are limited by Fmax, such that the core VID dropped way below what its count suggested.
> View attachment 2552044


One of the downsides of the lower base boost, and something that concerns me with regard to the 5800X3D, even if OCing is possible on it.

If you're curious enough you could go back to AGESA 1.1.9.0 era firmware for the higher boost values.


----------



## KedarWolf

32GB G.Skill DDR4 TridentZ RGB 4000Mhz PC4-32000 CL14 1.55V Dual Kit (2x16GB)

Can get this kit from eBay. It's not Royal Elite but from what I understand the TridentZ and the Royal Elite use the exact same PCB.

Should I bite?

Edit: It's from MemoryC and they have 30-day returns if it's not any better than my CL16 3600 Neo.

Second Edit: Or I can get this much cheaper, but I'm sure it's a lower bin. 

32GB G.Skill DDR4 TridentZ RGB 4266Mhz PC4-34100 CL17 Dual Channel Kit (2x 16GB)

Third Edit:

G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 4400 (PC4 35200) Intel XMP 2.0 Desktop Memory Model F4-4400C17D-32GTRS

This is b-die, might bite.


----------



## ManniX-ITA

KedarWolf said:


> 32GB G.Skill DDR4 TridentZ RGB 4000Mhz PC4-32000 CL14 1.55V Dual Kit (2x16GB)
> 
> Can get this kit from eBay. It's not Royal Elite but from what I understand the TridentZ and the Royal Elite use the exact same PCB.
> 
> Should I bite?
> 
> Edit: It's from MemoryC and they have 30-day returns if it's not any better than my CL16 3600 Neo.


Why not?

It's possibly the one I have.
Not much better than the 4000CL16 1.4V kit but it is better.
Which is more than the Royal Elite that I've tested.


----------



## blodflekk

While monitoring my CO that I'm retesting on new BIOS which now allows 1.49VID, I'm seeing my effective clocks are 400MHz lower than core clocks. How do I adjust this? Is this a limits issue? scalar ? boost override ?


----------



## KedarWolf

ManniX-ITA said:


> Why not?
> 
> It's possibly the one I have.
> Not much better than the 4000CL16 1.4V kit but it is better.
> Which is more than the Royal Elite that I've tested.


What about these. Intel I know, but I can make them work. On b-die finder they are rated 7.5ns and 7.7ns, not straight 7 like the CL14 4000.

32GB G.Skill DDR4 TridentZ RGB 4266Mhz PC4-34100 CL16 Dual Channel Kit (2x 16GB)

G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 4400 (PC4 35200) Intel XMP 2.0 Desktop Memory Model F4-4400C17D-32GTRS

This is b-die, might bite.


----------



## ManniX-ITA

KedarWolf said:


> 32GB G.Skill DDR4 TridentZ RGB 4266Mhz PC4-34100 CL17 Dual Channel Kit (2x 16GB)


This is the one I bought, worse than the 4000CL14 1.55V.
The other one, not sure.
Honestly after some point is just a binning lottery...
Buy & send back till you get something good.


----------



## KedarWolf

KedarWolf said:


> What about these. Intel I know, but I can make them work. On b-die finder they are rated 7.5ns and 7.7ns, not straight 7 like the CL14 4000.
> 
> 32GB G.Skill DDR4 TridentZ RGB 4266Mhz PC4-34100 CL16 Dual Channel Kit (2x 16GB)
> 
> G.SKILL Trident Z Royal Series 32GB (2 x 16GB) 288-Pin DDR4 SDRAM DDR4 4400 (PC4 35200) Intel XMP 2.0 Desktop Memory Model F4-4400C17D-32GTRS
> 
> This is b-die, might bite.


The CL14 4000 on eBay just went out of stock.


----------



## mtrai

@ManniX-ITA and really everyone.

First thanks for all the information. I can finally use my PC again after almost 3 1/2 years. I mean sit at and do things but can still on very lightly game or type. Gonna have my first orthopedic appointment in a couple of months to deal with my carpal and cubital tunnel syndrome.

Been finally tuning my ram thanks to all the post here. I am down to just a couple of things in voltage now. Though I did order a 2 x 16 kit a bit over a month ago that is either c or d hynix. I went back to my 2 x 8 b-die 4133 cl19 from years ago. As it just performs better. Think I can tighten one or two more timings. Will post my results and ask.


----------



## KedarWolf

I just bought from Newegg.ca CL14 3600 Royal Elite.

Here's hoping.


----------



## Blameless

blodflekk said:


> While monitoring my CO that I'm retesting on new BIOS which now allows 1.49VID, I'm seeing my effective clocks are 400MHz lower than core clocks. How do I adjust this? Is this a limits issue? scalar ? boost override ?


Can you be more specific as to the settings used and test you're seeing this clock stretching in? It usually happens when the voltage supplied is insufficient for the clocks being requested. I haven't seen it much outside of botched power limits, or too much vdroop from bad LLC settings.


----------



## blodflekk

Blameless said:


> Can you be more specific as to the settings used and test you're seeing this clock stretching in? It usually happens when the voltage supplied is insufficient for the clocks being requested. I haven't seen it much outside of botched power limits, or too much vdroop from bad LLC settings.


I am seeing this in any load, but right now under @ManniX-ITA boost tester and in core cycler. I am using motherboard limits, scalar 10x, cpu LLC auto. CO is -20 all core except core 0 and 3 at -10


----------



## ManniX-ITA

blodflekk said:


> I am seeing this in any load, but right now under @ManniX-ITA boost tester and in core cycler. I am using motherboard limits, scalar 10x, cpu LLC auto. CO is -20 all core except core 0 and 3 at -10


Sounds bad... can you try with PBO limits 280/165/215?


----------



## ManniX-ITA

blodflekk said:


> I am seeing this in any load, but right now under @ManniX-ITA boost tester and in core cycler. I am using motherboard limits, scalar 10x, cpu LLC auto. CO is -20 all core except core 0 and 3 at -10


Another issue could be the VID capping, if you are using an AGESA higher than 1.2.0.4 set EDC to 140A.
If it's working properly... I would downgrade the BIOS version.


----------



## blodflekk

I am on the latest bios for dark hero 4006 and vid is is reaching 1.5v, I'm not capped. Limits you suggested is that ppt/tdc/edc ? or did I get the order wrong ?


----------



## ManniX-ITA

blodflekk said:


> I am on the latest bios for dark hero 4006 and vid is is reaching 1.5v, I'm not capped. Limits you suggested is that ppt/tdc/edc ? or did I get the order wrong ?


Yes that' the order.
Which AGESA is this one which is not capped? 1.2.0.6b?


----------



## blodflekk

Would like to add I only care about ST and gaming performance with PBO. since I have the dark hero, I will be setting a static OC for MT


----------



## ManniX-ITA

blodflekk said:


> Would like to add I only care about ST and gaming performance with PBO. since I have the dark hero, I will be setting a static OC for MT


Then you may try with much lower limits to improve ST, something like 200/120/140.


----------



## blodflekk

Yes, I am not capped on 1.2.0.6.b


----------



## ManniX-ITA

blodflekk said:


> Yes, I am not capped on 1.2.0.6.b


I remember someone else was capped with the latest BIOS but maybe was earlier than 4006 or I'm wrong 
You don't have either the VDDG bug fixed at 1000mV right?


----------



## blodflekk

Correct, I don't have either bug. I was capped with bios 4004. 4006 is only a few days old. Those limits you suggested raised my boost so I have all cores above 5.0 with core 0 hitting 5.2. However effective clocks are still 4.1 - 4.7


----------



## ManniX-ITA

blodflekk said:


> Correct, I don't have either bug. I was capped with bios 4004. 4006 is only a few days old. Those limits you suggested raised my boost so I have all cores above 5.0 with core 0 hitting 5.2. However effective clocks are still 4.1 - 4.7


Do you have ASUS Fmax or Performance Enhancer enabled?
They can create similar problems.


----------



## blodflekk

I do have fmax enhancer enabled. I'll disable that and try again


----------



## Taraquin

ManniX-ITA said:


> Why not?
> 
> It's possibly the one I have.
> Not much better than the 4000CL16 1.4V kit but it is better.
> Which is more than the Royal Elite that I've tested.


Isn't really 4000cl16 1.4V and 4000cl14 1.55V very similar binned? I rough guestimate is you need 0.07-0.1 more voltage going down on 1 by the three prims. 

There seem to be 3 different bins on B-die given you have A2 at 1.35V 
Bottom: 3200cl15-4000cl19 (Ripjaws, Viper 4000) 
Avg: 3200cl14-4266cl19 (FlareX, Viper 4400 xmp2) 
Top: 3600cl15 (Trident Z) 

Other high end runs 1.4-1.55V and generally 1-2 primes lower, but this is primarily due to higher voltage/temptolerance.


----------



## blodflekk

disabling fmax enhancer did a couple of things. It capped me at 1.4 again, highest boost I'm seeing now is 4.9 and the effective clocks are now only 100mhz behind


----------



## ManniX-ITA

Taraquin said:


> Isn't really 4000cl16 1.4V and 4000cl14 1.55V very similar binned?


Tad better the 2nd.
Anything else I bought to test, from 3200 to 3600 where binned exactly as the 4000CL16


----------



## ManniX-ITA

blodflekk said:


> disabling fmax enhancer did a couple of things. It capped me at 1.4 again, highest boost I'm seeing now is 4.9 and the effective clocks are now only 100mhz behind


Interesting, so it's the FMax which kills the VID cap...

Post in a spoiler the HWInfo main screen for the CPU and some relevant screenshots from the BIOS, where you have set PBO, VRM, main settings.

You shouldn't have 100 MHz delta in any case, something else is off besides FMax
If you are capped the EDC is above 140A.


----------



## blodflekk

ManniX-ITA said:


> Interesting, so it's the FMax which kills the VID cap...
> 
> Post in a spoiler the HWInfo main screen for the CPU and some relevant screenshots from the BIOS, where you have set PBO, VRM, main settings.
> 
> You shouldn't have 100 MHz delta in any case, something else is off besides FMax
> If you are capped the EDC is above 140A.





Spoiler


----------



## ManniX-ITA

@blodflekk 

The PBO limits are not set, in HWInfo you can see the stock limits are set.

Can't you set them in Extreme Tweaker instead of Advanced\AMD OC?

Better to scale back some settings.

Set Global C-State enabled.
Set the DIGI+ all to Auto, LLC, thermal control, switching frequencies.
PBO set Scalar to 1x, boost clock to 100 MHz, thermal throttle limit to Auto.


----------



## blodflekk

I set everything to auto as you suggested, booted into windows. hwinfo64 still reporting those stock limits


Spoiler


----------



## ManniX-ITA

blodflekk said:


> I set everything to auto as you suggested, booted into windows. hwinfo64 still reporting those stock limits


Were you able to set them in Tweaker?
I remember there's a way to do it, not 100% sure.
Clearly those set in AMD OC are not considered.
How's going with the delta between core and effective clock?


----------



## blodflekk

Yes I was able to set them in tweaker. Just have to set PBO to advanced instead of enabled. Delta is still there


Spoiler















With regard to limts not being seen correctly in hwinfo, could it be the fault of the software or do I have a potentially faulty board?
I also noticed under effective clocks, core0 has T1 but not T0 like all other cores


----------



## gameinn

Can someone explain this to me?

Is it better to go with a lower voltage B-Die kit for OC or a higher voltage kit? Example you have 2 sets of RAM:

1: 3600 16-16-16-36 1.35v (2x16GB)
2: 3600 14-15-15-35 1.45v (2x16GB)

Now most people will OC the 1.35v kit to 1.45v for tight 3600C14 operation but since the second kit is already 1.45v, you can't really go anywhere. Are you just supposed to use the same voltage as XMP on the 1.45v kit to achieve tighter C14 timings or what?


----------



## ManniX-ITA

blodflekk said:


> With regard to limts not being seen correctly in hwinfo, could it be the fault of the software or do I have a potentially faulty board?


I don't know it's so weird... but hardly a board faulty. More likely a BIOS issue...
I'd switch back to 3801 to check.



blodflekk said:


> I also noticed under effective clocks, core0 has T1 but not T0 like all other cores


I see, it's super weird... maybe do a BIOS load optimized defaults, could be something is corrupted.


----------



## ManniX-ITA

gameinn said:


> Now most people will OC the 1.35v kit to 1.45v for tight 3600C14 operation but since the second kit is already 1.45v, you can't really go anywhere. Are you just supposed to use the same voltage as XMP on the 1.45v kit to achieve tighter C14 timings or what?


All the b-die kits have more or less the same voltage limits plus a delta for binning.
At exactly same timings lower voltage should be better.
Supposedly lower voltages are better.
But my 4000C16 at 1.4V is a tad worse than my 4000CL14 1.55V kit.


----------



## Audioboxer

Looks like my 3080 is shipping today, finally this step up is complete. Maybe by the time I get it in a few days MSI will have decided to roll out AGESA 1.2.0.6c to motherboards people actually bought...

Because, you know, releasing it for all your most unpopular boards first is a big brain move. So much so not a single person has been able to report if voltage is still capped with EDC. It likely is, but still...

New AMD chipset drivers out as well https://www.amd.com/en/support/chipsets/amd-socket-am4/x570 4.03.03.431


----------



## blodflekk

Bios update is a job for another day. I've also posted in the dark hero thread to see if anyone else has seen anything similar.


----------



## Blameless

blodflekk said:


> View attachment 2552073


If you aren't using snapshot polling, you can only compare effective vs. reported clocks during a fairly steady load. Without snapshot polling the maximum reported boost clocks will almost always read higher as even momentary transients are recorded.


----------



## Audioboxer

__ https://twitter.com/i/web/status/1503683280289292291
_Everything_ was an upcoming AGESA update.

Up next, AGESA 1.2.0.8 breaks support for 5xx motherboards whilst AMD add in support for 3xx.

I mean, this is good news, but there is no way AMD manage this without breaking something.


----------



## ManniX-ITA

Audioboxer said:


> I mean, this is good news, but there is no way AMD manage this without breaking something.


Not necessarily the board vendors they did it already.
It's mostly a matter of what you'll sacrifice to make space for the new CPUs.

What is worrying is that they'll waste effort to sell the new cheap CPUs and will delay again fixing the top tier...


----------



## blodflekk

Blameless said:


> If you aren't using snapshot polling, you can only compare effective vs. reported clocks during a fairly steady load. Without snapshot polling the maximum reported boost clocks will almost always read higher as even momentary transients are recorded.


I can't use snapshot polling, as soon as I enable that, all CPU information disappears from hwinfo


----------



## Taraquin

gameinn said:


> Can someone explain this to me?
> 
> Is it better to go with a lower voltage B-Die kit for OC or a higher voltage kit? Example you have 2 sets of RAM:
> 
> 1: 3600 16-16-16-36 1.35v (2x16GB)
> 2: 3600 14-15-15-35 1.45v (2x16GB)
> 
> Now most people will OC the 1.35v kit to 1.45v for tight 3600C14 operation but since the second kit is already 1.45v, you can't really go anywhere. Are you just supposed to use the same voltage as XMP on the 1.45v kit to achieve tighter C14 timings or what?


They have about the same binning, I would buy the cheapest kit if I where you. Often you can run timings one lower at same voltage, most kits have some slack. For instance my average binned Patriot Viper 4400cl19 runs 1.45V. You can generally lower prims by 1 for each 200MHz you reduce so my kit should run 4000cl17 1.45. However it runs 4000cl16 at 1.47v or 3800cl15 at 1.48v, both at 1t gdm off.


----------



## Audioboxer

ManniX-ITA said:


> Not necessarily the board vendors they did it already.
> It's mostly a matter of what you'll sacrifice to make space for the new CPUs.
> 
> What is worrying is that they'll waste effort to sell the new cheap CPUs and will delay again fixing the top tier...


The board manufacturers for how much of a mixed bag they can be have repeatedly shown they are better at handling the AMD bios than AMD are themselves.

Quite honestly the top-tier is never getting properly fixed, so I would be reluctant to blame this on anyone rocking a 3xx board desperately wanting to get a cheapish 5xxx chip. Fair play if they can, universally.

AMD on the other hand should have been capable well before now of transparently explaining both voltage limits/CPU boosting/WHEA/IF and releasing proper changelogs with AGESA changes to let us know what on earth they are trying to achieve.

The spectre stuff looks like an incoming mess as well, there is already misinformation about what the performance hit is and what its impacting.


----------



## blodflekk

I believe something is corrupted with my dark hero and will probably have to rma it. flash bios 3801 and still the same issue, delta between clock and effective clock, limits not applied. Also seeing this in pbo tuner


Spoiler


----------



## FleischmannTV

blodflekk said:


> I can't use snapshot polling, as soon as I enable that, all CPU information disappears from hwinfo


You have to go to the layout settings and reset them.


----------



## ManniX-ITA

Taraquin said:


> They have about the same binning, I would buy the cheapest kit if I where you. Often you can run timings one lower at same voltage, most kits have some slack. For instance my average binned Patriot Viper 4400cl19 runs 1.45V. You can generally lower prims by 1 for each 200MHz you reduce so my kit should run 4000cl17 1.45. However it runs 4000cl16 at 1.47v or 3800cl15 at 1.48v, both at 1t gdm off.


I can tell you my experience; my 4000CL16 kit doesn't support flat 14 at 3800 and only tRCDRD 16 at 4000.

Bought the same kit at 3200CL14 that could do flat 14 for someone else and what could do max was exactly the same as the 4000CL16.
Then I bought another 3600C16 kit that was known reported able to do flat 14 and again same.
Bought the 4266C17 Royal Gold, still exactly the same.

Ultimately went for the 4000CL14 and finally it was better.
I think with decent cooling, can't do it now, can do flat 14.
And it can do 4000 with tRCDRD at 15 which the others couldn't.



blodflekk said:


> I believe something is corrupted with my dark hero and will probably have to rma it. flash bios 3801 and still the same issue, delta between clock and effective clock, limits not applied. Also seeing this in pbo tuner


Unfortunately I don't much experience with the Dark Hero.
The 0s in PBO2 Tuner means that PBO is not enabled with custom limits.
This delta is quite worrying indeed...


----------



## Bix

I received a new 5900x after RMA-ing the last one because of core 1 crashing at stock and... drum roll... I'm getting the same issue with the new one. 
It's B2 rather than B0 stepping this time and weirdly I'm now getting CPU Core VID (Effective) consistently going up to 1.55V. Screenshot in the spoiler was taken after a couple of rounds of BoostTester followed by a single iteration of CoreCycler with P95 720FFTs which causes core 1 (supposedly by best according to CPPC) to error pretty much straight away. AGESA 1.2.0.5 with optimised defaults. I can stabilise core 1 with a positive CO of 2 but that really limits the boosting. Any suggestions before I start another RMA? Could the board be at fault here?


Spoiler


----------



## ManniX-ITA

Bix said:


> Any suggestions before I start another RMA? Could the board be at fault here?


Oh my, exactly the same behavior as the B2 that they sent me and I've sent back....
Same horrible boosting and same high temperatures.
What the heck AMD is doing?
I'm scared now about the one I'll get back.
The chances will be the same are high.


----------



## PJVol

ManniX-ITA said:


> What the heck AMD is doing?


Sending your ex cpu over again until it settled at someone who don't know anything about corecycler.


----------



## Bix

ManniX-ITA said:


> Oh my, exactly the same behavior as the B2 that they sent me and I've sent back....
> Same horrible boosting and same high temperatures.
> What the heck AMD is doing?
> I'm scared now about the one I'll get back.
> The chances will be the same are high.


It's definitely not a good look for AMD, especially with what are supposed to be their flagship models. I dread to think how many defective CPUs there actually are out there considering how many probably go unnoticed... Good luck with your next one!


----------



## ManniX-ITA

Bix said:


> Good luck with your next one!


Good luck you too, fingers crossed!



PJVol said:


> Sending your ex cpu over again until it settled at someone who don't know anything about corecycler.


Actually mine on top of that destroyed my Windows install in a couple of days.
I'm really looking forward to see another unlucky 5950X owner going bonkers with it... they'll have fun hearing the screams.


----------



## MrHoof

ManniX-ITA said:


> Good luck you too, fingers crossed!
> 
> 
> 
> Actually mine on top of that destroyed my Windows install in a couple of days.
> I'm really looking forward to see another unlucky 5950X owner going bonkers with it... they'll have fun hearing the screams.


Hopefully they dont have important data, not everyone is smart enough to do backups like you .


----------



## Bix

MrHoof said:


> Hopefully they dont have important data, not everyone is smart enough to do backups like you .


...and hopefully everyone else isn't just happily backing up a load of corrupted data!


----------



## gameinn

@Bix Isn't it just because 1.2.0.5 is bad? I had a weird issue like yours too on that BIOS. I'd definitely go back to 1.2.0.3c and see what happens. Also might be worth doing a fresh Windows install with ethernet unplugged if you didn't do that already. If you don't windows update installs some bad amd drivers on first boot up that can cause weirdness like that.


----------



## Audioboxer

The more I hear about B2 I am glad I have a B0 😂

No doubt these crappy AGESA releases aren't helping.


----------



## Bix

gameinn said:


> @Bix Isn't it just because 1.2.0.5 is bad? I had a weird issue like yours too on that BIOS. I'd definitely go back to 1.2.0.3c and see what happens. Also might be worth doing a fresh Windows install with ethernet unplugged if you didn't do that already. If you don't windows update installs some bad amd drivers on first boot up that can cause weirdness like that.


I tried it with 1.2.0.3b first and had the same issue sadly. Updated to 1.2.0.5 just to see if it made any difference (IIRC a few on here suggested that B2 chips could be a bit buggy with older AGESAs) and tried 3 different versions of the chipset drivers with no luck so far. 

Was really trying to avoid a fresh install but I guess it'll give me something to do while I'm waiting for them to process the RMA😂


----------



## Taraquin

B0=Beta 0
B2=Beta 2


----------



## Imprezzion

Am I the only one who has a B2 5900X on a 1.2.0.3c board with zero issues lol? I refuse to update the BIOS/AGESA because everything works as intended and is stable plus scores very very well in benchmarks so why would I ever update and risk losing all stability. 

5900X B2 @ -25 CO all core, +50Mhz max boost, CPPC / Preferred Cores disabled
EDC 170 TDC 155 PPT 300
RAM 3733 15-15-8-13-27-252-1T GDM Off 1.550v
FCLK 1:1 1866 @ 1.087v vSOC
ASUS performance bias set to "Geekbench/AIDA".

I can hit around 23700 in CBR23 at 4675 boost all core, 10600 in CPU-Z all core at 4700 boost and 673 single core at 5ghz. Max temps 72c. TechN block + 420+240 Nemesis GTX + 4800RPM D5 loop.

Gaming performance is exceptional as it almost always clocks well above 4800Mhz multicore in most games.


----------



## Baio73

Imprezzion said:


> Am I the only one who has a B2 5900X on a 1.2.0.3c board with zero issues lol? I refuse to update the BIOS/AGESA because everything works as intended and is stable plus scores very very well in benchmarks so why would I ever update and risk losing all stability.
> 
> 5900X B2 @ -25 CO all core, +50Mhz max boost, CPPC / Preferred Cores disabled
> EDC 170 TDC 155 PPT 300
> RAM 3733 15-15-8-13-27-252-1T GDM Off 1.550v
> FCLK 1:1 1866 @ 1.087v vSOC
> ASUS performance bias set to "Geekbench/AIDA".
> 
> I can hit around 23700 in CBR23 at 4675 boost all core, 10600 in CPU-Z all core at 4700 boost and 673 single core at 5ghz. Max temps 72c. TechN block + 420+240 Nemesis GTX + 4800RPM D5 loop.
> 
> Gaming performance is exceptional as it almost always clocks well above 4800Mhz multicore in most games.


Did you try FCLK higher than 1866? 1900 should be an easy achievement, maybe B2 can also do 2000...

Baio


----------



## Imprezzion

Baio73 said:


> Did you try FCLK higher than 1866? 1900 should be an easy achievement, maby B2 can also do 2000...
> 
> Baio


Yes, it has a FCLK hole at 1900 so can't post 1900, 1933 and 1966 is fine at 1.15v vSOC and slightly tweaked VDDG/VDDP but my RAM hates 3866/3933. 2000 can be done but it's a WHEA mess if not tweaked to perfection. vSOC at minimum has to be 1.240v, VDDP and G have to be set exactly right, 0.005v off and it gets worse, it can only run it with the RAM at 4000C15 2T or 4000C16 1T GDM On, 1T GDM Off is a no-go, it has to have ProcODT and RTT's on very specific values and then still it gives 1-2 WHEA's per hour of y-cruncher or TestMem5.


----------



## Baio73

Imprezzion said:


> Yes, it has a FCLK hole at 1900 so can't post 1900, 1933 and 1966 is fine at 1.15v vSOC and slightly tweaked VDDG/VDDP but my RAM hates 3866/3933. 2000 can be done but it's a WHEA mess if not tweaked to perfection. vSOC at minimum has to be 1.240v, VDDP and G have to be set exactly right, 0.005v off and it gets worse, it can only run it with the RAM at 4000C15 2T or 4000C16 1T GDM On, 1T GDM Off is a no-go, it has to have ProcODT and RTT's on very specific values and then still it gives 1-2 WHEA's per hour of y-cruncher or TestMem5.


Ouch! Quite disappointing let's say..

Baio


----------



## Imprezzion

Baio73 said:


> Ouch! Quite disappointing let's say..
> 
> Baio


Kind of. I mean, the cores are exceptional doing -25 on all cores (even tho that limits me to 5Ghz flat) at great temps but the FCLK is not that great. Then again, 3733 is a nice sweet spot for my RAM (Trident-Z Neo 3600C16 B-Die) where it runs very tight subtimings. It can do straight 14's just fine but that won't train tPHYRDL 26/26 on 1T GDM Off so performs worse then 15's with proper trained tPHYRDL.


----------



## gameinn

Is Aida latency something that has big swings in variance or what? My 3600C14 profile was giving me like 58.7ns. Next benchmark it gives me 61.6ns. Try again and it's back to 58ns. Huh?


----------



## SneakySloth

gameinn said:


> Is Aida latency something that has big swings in variance or what? My 3600C14 profile was giving me like 58.7ns. Next benchmark it gives me 61.6ns. Try again and it's back to 58ns. Huh?


Yes, AIDA is fairly unreliable that way. It depends significantly on what else is running on your windows installation at that time.


----------



## Audioboxer

gameinn said:


> Is Aida latency something that has big swings in variance or what? My 3600C14 profile was giving me like 58.7ns. Next benchmark it gives me 61.6ns. Try again and it's back to 58ns. Huh?


It's at the point where I'd say AIDA latency is just a "poor" way to test memory. Far too many variables across machines, unless you get everyone running in safe mode/diagnostic mode or with a cut down Windows. Then there is how much your CPU boosting/OC can actually impact latency. On top of that there are ways to play around with affinity/core use in order to priortise a more favourable AIDA run.

There seems to be a lack of memory benchmark tools, or well, the overall OCing scene has just heavily leaned on using AIDA. Everyone wants to see your AIDA screenshot.

I wouldn't say it's useless, it gives a reasonable indiciation of how your memory is doing, more so if you have a proper testing environment set up and don't have many variables changing between runs. How you compare to other people though depends on their setups and testing variables.

Many pro OCers definitely know all the tricks in the trade to get favourable benchmark screenshots, lets just put it that way 

I quite like doing a membench run in DRAM Calculator, but that's not been updated for ages and I don't know if there is a better way to run membench independent of DRAM Calculator? From what I can see with membench if you can get into the 9x.xx seconds you're doing well, really well if you can get like 93.xx~95.xx seconds. This is with me testing at 3800.


----------



## KedarWolf

The guy that was going to sell me the CL14 4000 G.Skill for way too much money backed out.

I have CL16 3600 Neo that performs decently, but ordered from newegg.ca some CL14 3600 Royal Elite which is supposed to be a decent bin.

Can't find CL14 4000 anywhere, not even eBay.


----------



## MrHoof

check pm @KedarWolf


----------



## KedarWolf

MrHoof said:


> check pm @KedarWolf


ty


----------



## 1s1mple

Anyone try the new AMD chipset driver v4.03.03.431?


----------



## Audioboxer

KedarWolf said:


> The guy that was going to sell me the CL14 4000 G.Skill for way too much money backed out.
> 
> I have CL16 3600 Neo that performs decently, but ordered from newegg.ca some CL14 3600 Royal Elite which is supposed to be a decent bin.
> 
> Can't find CL14 4000 anywhere, not even eBay.


Sadly G.SKILL customer support confirmed a month or two back 4000C16 was likely as good as it was going to get going forward for DR.

I presume the binning requirement for 4000C14 died on its arse quickly and focus has shifted to DDR5.

I wonder how few DR kits were actually released?

SR 4000C14 kits are still kicking around a bit I think. Quite a few on eBay.


----------



## gameinn

Audioboxer said:


> Sadly G.SKILL customer support confirmed a month or two back 4000C16 was likely as good as it was going to get going forward for DR.
> 
> I presume the binning requirement for 4000C14 died on its arse quickly and focus has shifted to DDR5.
> 
> I wonder how few DR kits were actually released?
> 
> SR 4000C14 kits are still kicking around a bit I think. Quite a few on eBay.


I'm actually surprised during the pandemic they increased the range they offer for even tighter memory. Pre covid they had a 3600C14 bin at 1.40v but that was discontinued for some reason.


----------



## Audioboxer

gameinn said:


> I'm actually surprised during the pandemic they increased the range they offer for even tighter memory. Pre covid they had a 3600C14 bin at 1.40v but that was discontinued for some reason.


Was that 14-15-15-15? When they released the 4000C14 kit they also released a 3600 14-14-14-14 1.45v kit.

I actually had that kit first, but believe it or not mine couldn't run tRCDRD 14 at 3800. 

I'm guessing G.SKILL got in a big batch of Samsung's most mature B-die sticks and the best were 4000C14 binned and just under that 3600C14 (flat 14). Hence the 4000C14 bin costing the most.

At the same time I'm guessing the 4000C14 DR kits must have been a low yield and ultimately there is more luck binning 4000C16 or 3600C14 or 3600C16. Or at best 4000C14 SR.

That plus with DDR5 coming out the price it cost for 4000C14 just becomes less enticing because the kind of people who spend stupid money on memory are likely looking to move to DDR5 now.

It cost me £277 for the 3600C14 DR kit and £355 for the 4000C14 DR kit. Stupid money. I paid full blown retail for the 3600 kit and got the 4000C14 kit a bit cheaper than most of the standard UK RRP at the time.

I fully expected the 3600 14-14-14-14 kit to do 3800 14-14-14-14 no bother, even if it needed 1.5v or something. That was a huge disappointment. The 4000C14 kit blew it away, that thing does 3800 14-14-14-14 for me at 1.44v. Less than the damn 3600 14-14-14-14 XMP spec lmao.


----------



## blodflekk

After all the testing and work put in to sort my PBO issues and also effective clock delta with the help of @ManniX-ITA (thank you so much for helping) I have come to the conclusion the board is borked, so I RMA'd it today. I also, for the first time ever managed to drop the 5950x while taking it out, bending one pin, getting thermal paste on the pins and in the socket. Did my best to clean it, result was still terrible and sent it back anyway, will likely be getting back nothing and will have to purchase new again


----------



## ManniX-ITA

blodflekk said:


> I also, for the first time ever managed to drop the 5950x while taking it out, bending one pin, getting thermal paste on the pins and in the socket. Did my best to clean it, result was still terrible and sent it back anyway, will likely be getting back nothing and will have to purchase new again


Oh man, I'm so sorry 😢


----------



## gameinn

Audioboxer said:


> Was that 14-15-15-15? When they released the 4000C14 kit they also released a 3600 14-14-14-14 1.45v kit.
> 
> I actually had that kit first, but believe it or not mine couldn't run tRCDRD 14 at 3800.
> 
> I'm guessing G.SKILL got in a big batch of Samsung's most mature B-die sticks and the best were 4000C14 binned and just under that 3600C14 (flat 14). Hence the 4000C14 bin costing the most.
> 
> At the same time I'm guessing the 4000C14 DR kits must have been a low yield and ultimately there is more luck binning 4000C16 or 3600C14 or 3600C16. Or at best 4000C14 SR.
> 
> That plus with DDR5 coming out the price it cost for 4000C14 just becomes less enticing because the kind of people who spend stupid money on memory are likely looking to move to DDR5 now.
> 
> It cost me £277 for the 3600C14 DR kit and £355 for the 4000C14 DR kit. Stupid money. I paid full blown retail for the 3600 kit and got the 4000C14 kit a bit cheaper than most of the standard UK RRP at the time.
> 
> I fully expected the 3600 14-14-14-14 kit to do 3800 14-14-14-14 no bother, even if it needed 1.5v or something. That was a huge disappointment. The 4000C14 kit blew it away, that thing does 3800 14-14-14-14 for me at 1.44v. Less than the damn 3600 14-14-14-14 XMP spec lmao.


Yeah it was 14-15-15-35. I still think it would beat most kits since 1.40v is pretty decent headroom.

I'm shocked the 3600 14-14-14-34 kit couldn't do 3800 flat 14 that's kind of insane tbh. I was gonna get it but after reading that no way.

I actually wonder if TeamGroup is the B-Die kits to get these days, DR wise anyway. That 8 Pack 2x16GB 3600C16 kit has had numerous reports of running 4000C16 at 1.40v and flat 3800C14. If it's on sale again I might pick that up tbh. It was on offer for £150 at one point. Was stupid not to pick it up for that price tbh.


----------



## Audioboxer

gameinn said:


> Yeah it was 14-15-15-35. I still think it would beat most kits since 1.40v is pretty decent headroom.
> 
> I'm shocked the 3600 14-14-14-34 kit couldn't do 3800 flat 14 that's kind of insane tbh. I was gonna get it but after reading that no way.
> 
> I actually wonder if TeamGroup is the B-Die kits to get these days, DR wise anyway. That 8 Pack 2x16GB 3600C16 kit has had numerous reports of running 4000C16 at 1.40v and flat 3800C14. If it's on sale again I might pick that up tbh. It was on offer for £150 at one point. Was stupid not to pick it up for that price tbh.


Lower voltage bins are generally worse (in terms of super tight timings), even G.SKILL has confirmed that. The concept of 'headroom' actually comes in with higher voltage XMP. Higher voltage means the memory has to be less sensitive to VDIMM and that is often what gives you more overhead to play around with it.

The 4000C16 kit at 1.4v has actually ended up disappointing for many people. It's still luck of the draw, but I've seen quite a few reports on OCing issues and given XMP is rated for 1.4v it means the kit is in no way _factory tested_ at voltages like 1.5~1.55v. While all B-die will run at that voltage it's about how sensitive it becomes in combination with trying to run super low timings.

My advice now would be buy the highest rated voltage kit with the tightest timings you can afford. If you buy something like 4000C16 1.4v, just be prepared for the chance something like 3800 14-14-14-14 could be a struggle, or you might have to try and push higher VDIMM than some other kits. But as I said I bought 3600 14-14-14-14 at 1.45v and it just flat out refused to run tRCDRD 14 at 3800. Sometimes you just snag a stinker.

The whole "keep it under 1.5v" that has saturated memory OCing advice for years is just flat out wrong. In principle I get where it's coming from, air cooling over 1.5v can be a challenge, but it's not based in any reality around failure rates or being unsafe. In terms of B-die running right up to 1.65v where the memory can then struggle to run at full capacity is totally fine. Hence bins sold with an XMP of 1.6v.

For £150 though that kit is definitely worth rolling the dice on. As always, anything outside of XMP is total chance, when it comes to memory all you're doing is increasing your chances if you cherry pick bins or pay more money. If companies could easily sell a 3800 14-14-14-14 kit they would, but as we can see, it's never been done lol. Only 3800 14-15-15-15.

Even cracking 3600 14-14-14-14 took years, a bin that is ideal for baseline Ryzen 1:1 FCLK compatibility given 1800 is something nearly everyone should now be hitting fine.


----------



## Taraquin

blodflekk said:


> After all the testing and work put in to sort my PBO issues and also effective clock delta with the help of @ManniX-ITA (thank you so much for helping) I have come to the conclusion the board is borked, so I RMA'd it today. I also, for the first time ever managed to drop the 5950x while taking it out, bending one pin, getting thermal paste on the pins and in the socket. Did my best to clean it, result was still terrible and sent it back anyway, will likely be getting back nothing and will have to purchase new again


I got paste on my 3600 pins, clean toothbrush and isopropanol worked wonders. Bent pins are a different beat though :/ 

If you don't get the RMA through I would consider a 5600 or 5700X if you mostly game when they arrive, a lot easier to tune with CO, often ram oc than 59X0.


----------



## gameinn

Audioboxer said:


> Lower voltage bins are generally worse, even G.SKILL has confirmed that. The concept of 'headroom' actually comes in with higher voltage XMP. Higher voltage means the memory has to be less sensitive to VDIMM and that is often what gives you more overhead to play around with it.


So you would definitely take a 14-15-15-35 1.45v bin over a 3600 16-16-16-36 1.35v bin? I guess it makes sense about the higher voltage. The only thing that doesn't make sense to me is like if you want to target something realtively safe like a tuned 3600C14 preset then likely most people are running that around 1.45v anyway. If you already have a 1.45v bin and lowering secondary timings, then you are hoping that you have a good 1.45v bin that can keep the same voltage while lowering timings by alot.


----------



## Taraquin

gameinn said:


> So you would definitely take a 14-15-15-35 1.45v bin over a 3600 16-16-16-36 1.35v bin? I guess it makes sense about the higher voltage. The only thing that doesn't make sense to me is like if you want to target something realtively safe like a tuned 3600C14 preset then likely most people are running that around 1.45v anyway. If you already have a 1.45v bin and lowering secondary timings, then you are hoping that you have a good 1.45v bin that can keep the same voltage while lowering timings by alot.


It depends a bit, generally you need 0.07-0.1v to lower prims by 1, but some 1.35V kits are A0 which don't like high voltages as much as A2.


----------



## Audioboxer

gameinn said:


> So you would definitely take a 14-15-15-35 1.45v bin over a 3600 16-16-16-36 1.35v bin? I guess it makes sense about the higher voltage. The only thing that doesn't make sense to me is like if you want to target something realtively safe like a tuned 3600C14 preset then likely most people are running that around 1.45v anyway. If you already have a 1.45v bin and lowering secondary timings, then you are hoping that you have a good 1.45v bin that can keep the same voltage while lowering timings by alot.


100% if pricing isn't an issue. If you're getting the 3600C16 bin for a good chunk of change less, then like with all "silicon lotteries" it's entirely possible what you're seeking to achieve you might end up being able to pull off. For example if that's 3800 14-14-14-14, there is nothing at face value that stops a 3600C16 bin of being capable of achieving that. In theory, your chances might just be a bit lower than if you paid more for the 3600C14 bin.

But I proved even buying the 3600 14-14-14-14 kit is no guarantee you're easily getting tRCDRD 14 at 3800.

The bigger question is how much of a performance difference is there going to be? The thrill of OCing memory and getting super tight timings is fun, but in terms of the raw numbers something like tRCDRD 15 at 3800 really isn't going to hold your PC back over managing to pull off 14.

In terms of the XMP voltage, think about it like this, whatever XMP is, there needs to be some headroom. Otherwise there would be an increase in RMAs if the memory was binned soo closely to XMP there was a chance some kits would freak out at 1.45v for 14-15-15-15 and end up needing maybe 1.46v or 1.47v. So chances are for a large number of the kits sold at retail you'll find you can run XMP LOWER than the rated voltage. Maybe 1.43/1.44v or in some instances if you get lucky a stupid drop like going down to 1.4v or something.

This is why if you buy a high rated voltage kit that has really good primary timings at XMP you can end up finding out that kit can run even tighter timings at impressive voltages. Coupled with it being proven at the point of purchase it's more than happy to gobble down 1.55v or 1.6v. Thermal tolerance plays a huge rule in getting DDR4 to really low timings.

All of this theory crafting sums up why 4000 14-15-15-15 at 1.55v is a stupidly good kit. You've got high frequency at XMP, really low primary timings and a kit that has no problem chomping down 1.55v.


----------



## blodflekk

ManniX-ITA said:


> Oh man, I'm so sorry 😢


Yeah. It made a bad situation much worse. Built 100s of systems and never once done this. If I do have to buy new, I might just go back to intel, AMD hasn't been a pleasant experience.


----------



## Audioboxer

blodflekk said:


> Yeah. It made a bad situation much worse. Built 100s of systems and never once done this. If I do have to buy new, I might just go back to intel, AMD hasn't been a pleasant experience.


I'll probably be going Intel next time around unless AM5 is something special.

The incompetence and lack of transparency from AMD with AGESA and their chipset drivers is beyond nonsense at this point. Not to mention the swing into hurting the OCing community.

Waiting till the end of the generation to really put the boot in and give the middle finger to the community that has spent years spending top dollar on your hardware and promoting you everywhere is certainly a bold move from the marketing department.


----------



## gameinn

Audioboxer said:


> The bigger question is how much of a performance difference is there going to be? The thrill of OCing memory and getting super tight timings is fun, but in terms of the raw numbers something like tRCDRD 15 at 3800 really isn't going to hold your PC back over managing to pull off 14.


True. I only really want to go for a decent C14 profile at 3600 that can constantly give me sub 60 ns on my 5950x. I've looked at DRAM Calc and it's just silly. It's saying stuff like "oh flat 14 timings with a 288 tRFC with recommended 1.37v and a max of 1.40v"... like huh? Is there even a b die kit in the world that could pull that off?


----------



## Audioboxer

gameinn said:


> True. I only really want to go for a decent C14 profile at 3600 that can constantly give me sub 60 ns on my 5950x. I've looked at DRAM Calc and it's just silly. It's saying stuff like "oh flat 14 timings with a 288 tRFC with recommended 1.37v and a max of 1.40v"... like huh? Is there even a b die kit in the world that could pull that off?


DRAM Calculator is pretty outdated outside of some very generic framework for memory.

I was 1.44v for 3800 14-14-14-14. I've not tested 3600, but it might be doable around 1.4v or less, to be fair. Actually quite confident this super bin of DDR4 might pull it off in high 1.3x range. I can run 3800 16-16-16-16 at 1.29v.

Once I get my PC back up and running I'll test 3600 14-14-14-14 just to see what I can do. But generally, I wouldn't pay too much attention to any voltage claims in DRAM Calculator.


----------



## gameinn

One thing I don't get about these XMP profiles.

This is ZenTimings for a 3600C14 kit: 










Now here's the XMP profile:










It automatically set tRRDS to 6 when the profile is 9? Huh? I've never seen a board set a lower timing than the profile.


----------



## ManniX-ITA

gameinn said:


> It automatically set tRRDS to 6 when the profile is 9? Huh? I've never seen a board set a lower timing than the profile.


Yes they do it very frequently.
Usually you can select profile 1 or 2, even if there's only one XMP profile on the DIMM.
My MSI does change the tRFC to a lower settings with 2 but the GigaByte Master was also reducing tRC.


----------



## Imprezzion

I prefer to just set everything manually even when not overclocking RAM. I don't have full confidence in XMP lol. Or it just sets only the primary timings leaving the secondary timings so loose (on my 10900KF + Z490 Ace for example) it still performs horrible. tWR of 24, trfc of like 600, tfaw 49 for some reason..


----------



## Owterspace

The only time I use my 3200C14 xmp profile is when running my ram at 2K or higher with my 5600X. It’s way to sloppy for slow mems.


----------



## Mach3.2

Audioboxer said:


> I'll probably be going Intel next time around unless AM5 is something special.
> 
> The incompetence and lack of transparency from AMD with AGESA and their chipset drivers is beyond nonsense at this point. Not to mention the swing into hurting the OCing community.
> 
> Waiting till the end of the generation to really put the boot in and give the middle finger to the community that has spent years spending top dollar on your hardware and promoting you everywhere is certainly a bold move from the marketing department.


I'm on your boat too.
The 5600X (2047SUS) I sold off was pretty turd. It can barely hold any -ve CO values and can't do 1900IF. My current 5900X (2113SUS) have pretty good silicon but I still can't do 1900IF.

Honestly my PC works for the most part but between the 1900 FCLK hole and AMD _still_ sending out defective CPUs as RMA replacements, I can't honestly say I'd be willing to support this dumpster fire for my next upgrade unless they pour more money into software. Not to mention they got to stop sending out defective silicon.

This is my 2nd time building my own PC and so far AMD hasn't really left any good impressions. Tally is at 1-0 in favour of Intel.


----------



## Baio73

Mach3.2 said:


> I'm on your boat too.
> The 5600X (2047SUS) I sold off was pretty turd. It can barely hold any -ve CO values and can't do 1900IF. My current 5900X (2113SUS) have pretty good silicon but I still can't do 1900IF.
> 
> Honestly my PC works for the most part but between the 1900 FCLK hole and AMD _still_ sending out defective CPUs as RMA replacements, I can't honestly say I'd be willing to support this dumpster fire for my next upgrade unless they pour more money into software. Not to mention they got to stop sending out defective silicon.
> 
> This is my 2nd time building my own PC and so far AMD hasn't really left any good impressions. Tally is at 1-0 in favour of Intel.


Are you saying that your CPUs were defective becasue they didn't work with [email protected]?

Baio


----------



## Mach3.2

Baio73 said:


> Are you saying that your CPUs were defective becasue they didn't work with [email protected]?
> 
> Baio


No, defective CPUs as in the earlier part of this thread and ManniX-ITA's RMA experience. The 1900MHz FCLK hole on both my samples was a let down but I've long gotten over it; it's not really a pain point for me but it I'd be lying if I were to say it hasn't left a sour taste in my mouth. _It is what it is._ 

Let's just put it this way: My PC works _for the most part_ and AMD made me salty over some small issues.

What really irks me is really the fact that they don't spend nearly as much as they should on their software and _it shows (GPU drivers, AGESA, Ryzen Master lol)_.


----------



## ManniX-ITA

Mach3.2 said:


> ManniX-ITA's RMA experience


My new 5950X is on the way... fingers crossed.


----------



## ManniX-ITA

Mach3.2 said:


> What really irks me is really the fact that they don't spend nearly as much as they should on their software and _it shows (GPU drivers, AGESA, Ryzen Master lol)_.


This and the 3D fiasco.

Hope I'm wrong but I consider it already a fiasco...
I'm really concerned about how they announced it in such grandeur with a 5900X and then had to admit it's not mature and there'll be only a 5800X3D.
Today on top of confirming they will hard lock OC, for something which is already miserably clocked, they shared that the VID is limited to 1.35V.
What else tomorrow I wonder? 

It shows there are some catastrophic miscommunication issues or/and poor QA or/and too recklessly competitive managers.
I'm very often thinking about switching back to Intel for DDR5...


----------



## Audioboxer

Mach3.2 said:


> I'm on your boat too.
> The 5600X (2047SUS) I sold off was pretty turd. It can barely hold any -ve CO values and can't do 1900IF. My current 5900X (2113SUS) have pretty good silicon but I still can't do 1900IF.
> 
> Honestly my PC works for the most part but between the 1900 FCLK hole and AMD _still_ sending out defective CPUs as RMA replacements, I can't honestly say I'd be willing to support this dumpster fire for my next upgrade unless they pour more money into software. Not to mention they got to stop sending out defective silicon.
> 
> This is my 2nd time building my own PC and so far AMD hasn't really left any good impressions. Tally is at 1-0 in favour of Intel.


Intel needs to sort out their power usage, that's the one thing AMD absolutely spank them on.


----------



## mongoled

Got to laugh at some of the stuff coming out here.

As if everything is nice and rosy on the Intel side

😂 😂

As if Intel or AMD really give a rats arse about what we think.

It is unfortunate that we are not getting what we want, i.e. prime silicon, overclocking headroom, perfectly working software etc etc which makes things extremely frustrating at times but you got to keep things in perspective!

I'm happy that I have not got bombs dropping on my head and that Intel have brought some competition back to the market.

So come on guys, do your best not to moan about things that are not really important in the grand scheme of things and just be happy we have the choice to buy and choose what we see fit


----------



## ManniX-ITA

mongoled said:


> As if everything is nice and rosy on the Intel side


I don't think there are many Intel fanboys here 

Guess most of us suffered the pain inflicted by Intel for years.
But we have a choice now as you said, it's beautiful and also powerful.
If we are disappointed by a player we can choose to switch side.

Clearly Alder Lake has its pains.
But Intel delivered this time, that thing is fast as they promised.
Yes it runs hot and sucks a lot of power.
But Raptor Lake is coming with the new 700 boards...
Same socket, platform evolution, more mature and much more performant.

On the other side there's AMD with Ryzen 7000 with AM5 and DDR5.
A new platform, new memory arch, not mature at all.
Early adopters again and seeing the track records so far with the 5000 probably for a very long time.
If the leaks are right will be a tad faster than Alder Lake and slower than Raptor Lake.

I'm not sure I'm willing to spend 1000-1500 € for it.

Yes the AM5 socket will be there for long time while Meteor Lake will probably need a new one...
But would I run today a 5950X on an X370 board?
Definitely not.
The first wave of AM5 boards will probably get quickly obsolete.

I really like easy OC and the degree of access via SMU that AMD is offering but they are starting to close and limit that as well.
That is something that would definitely give me any reason other than the raw performances in my choices.
And I would weight in it the huge disappointment.

I think they got really too much excited by the good sales with Ryzen and forgot Intel still has 80% of the market.
Let's see what the future will bring.
If they stop doing stupid things and the 7000 will show good numbers, I'm in.
Otherwise... we have a choice.



mongoled said:


> I'm happy that I have not got bombs dropping on my head and that Intel have brought some competition back to the market.


Yes, just trying to forget that we are very lucky. Yet.
Let's hope stays like this.
Sadly took only 70 years for the world to forget the horrors we brought in the previous 3000...


----------



## Audioboxer

I couldn't care less what name is on something, I've never really fallen down the brand loyalty slide when it comes to PC components. I buy what reviews well, is priced well and what has a decent community around it.

But given this is an AMD topic and currently I have an AMD CPU and mobo, I enjoy moaning about what I currently own 

And cmon, the AGESA bugs recently have been effing wild. From straight up locking VDDG voltages by accident, to capping CPU voltage for no reason, to USB issues and now we've got performance regression due to fTPM modules.

On my 3900xt it was horrendous power plans the community had to fix and even now on 5950x chipset drivers randomly come and go because parts of them end up missing, or when Windows 11 launched there was weeks of the memory latency issues.

Perfectly fine reasons to grumble about the Q&A processes at AMD that keep allowing really buggy BIOS releases and broken software.

Heck, AMD Ryzen Master is in a pretty rough state and no effort has been put in to clean it up.

That doesn't mean everything is all rosy on the Intel side, but AMD have made a hell of a lot of money being the market leader in many metrics on CPUs for years, how about listening to some feedback?


----------



## sonixmon

Audioboxer said:


> I'll probably be going Intel next time around unless AM5 is something special.
> 
> The incompetence and lack of transparency from AMD with AGESA and their chipset drivers is beyond nonsense at this point. Not to mention the swing into hurting the OCing community.
> 
> Waiting till the end of the generation to really put the boot in and give the middle finger to the community that has spent years spending top dollar on your hardware and promoting you everywhere is certainly a bold move from the marketing department.


I agree and this was my first AMD build. Ive always been Intel fan and a few friends when AMD in the past and my system was faster and more stable even though 2x the cost. It also was easier (IMO) to OC on intel. Yes it was power hog and heater but if your OCing thats to be expected.

Depending on the next release or two from both I may switch back to Intel but I am happy for a while with the performance.

AMD took the gaming crown for a short while and it went to their head LOL.


----------



## gameinn

Audioboxer said:


> Intel needs to sort out their power usage, that's the one thing AMD absolutely spank them on.


I used to think this too but isn't it just a myth? Igor did a very good review of Alder on launch about power stuff: Intel Core i9-12900K(F), Core i7-12700K and Core i5-12600K Review - Gaming in really fast and really frugal | Part 1 | Page 5 | igor'sLAB

I mean I guess in terms of gaming Alder is better but I guess in something like blender it's a whole other story.


----------



## ManniX-ITA

gameinn said:


> I used to think this too but isn't it just a myth? Igor did a very good review of Alder on launch about power stuff: Intel Core i9-12900K(F), Core i7-12700K and Core i5-12600K Review - Gaming in really fast and really frugal | Part 1 | Page 5 | igor'sLAB
> 
> I mean I guess in terms of gaming Alder is better but I guess in something like blender it's a whole other story.


I really don't know if Igor messed up or everyone else 

But it's the only review where I've seen these incredibly good numbers.
Maybe a matter of settings optimized for energy saving?
Or could be cause he used a chiller instead of normal cooling.
Not sure.

In general all the others are similar to these in the video below.
On top of Blender and other apps there is also the power consumption numbers while gaming.
Alder Lake is consistently higher than Ryzen in gaming.



Spoiler: Stock















With advantage of DDR5 the power consumption between a 12700K and a 5800X gets more close but depends on what.
Only Starcraft and CS:Go have a lower power consumption there.
There are a number of titles which are Intel optimized and consume less on Alder Lake but it's a minority.

And of course I wouldn't even consider stock...
When overclocked Alder Lake goes off the rails.
And this is where I guess it matters more.



Spoiler: OC















I generally consider Igor's reviews very reliable but there are a few questionable.
This one for me is completely wrong.
The 12700K consuming always lower than a 5800X at stock both with DDR4 and even with peaks of 50% less...
There's no other review or comparison that I've found that even come close.
It wouldn't be possible even if all titles where hand picked as optimized for Intel.
Not even Intel itself is claiming something like this and we know which kind of fraudsters they are with benchmarks


----------



## mongoled

ManniX-ITA said:


> I don't think there are many Intel fanboys here
> 
> Guess most of us suffered the pain inflicted by Intel for years.
> But we have a choice now as you said, it's beautiful and also powerful.
> If we are disappointed by a player we can choose to switch side.
> 
> Clearly Alder Lake has its pains.
> But Intel delivered this time, that thing is fast as they promised.
> Yes it runs hot and sucks a lot of power.
> But Raptor Lake is coming with the new 700 boards...
> Same socket, platform evolution, more mature and much more performant.
> 
> On the other side there's AMD with Ryzen 7000 with AM5 and DDR5.
> A new platform, new memory arch, not mature at all.
> Early adopters again and seeing the track records so far with the 5000 probably for a very long time.
> If the leaks are right will be a tad faster than Alder Lake and slower than Raptor Lake.
> 
> I'm not sure I'm willing to spend 1000-1500 € for it.
> 
> Yes the AM5 socket will be there for long time while Meteor Lake will probably need a new one...
> But would I run today a 5950X on an X370 board?
> Definitely not.
> The first wave of AM5 boards will probably get quickly obsolete.
> 
> I really like easy OC and the degree of access via SMU that AMD is offering but they are starting to close and limit that as well.
> That is something that would definitely give me any reason other than the raw performances in my choices.
> And I would weight in it the huge disappointment.
> 
> I think they got really too much excited by the good sales with Ryzen and forgot Intel still has 80% of the market.
> Let's see what the future will bring.
> If they stop doing stupid things and the 7000 will show good numbers, I'm in.
> Otherwise... we have a choice.
> 
> Yes, just trying to forget that we are very lucky. Yet.
> Let's hope stays like this.
> Sadly took only 70 years for the world to forget the horrors we brought in the previous 3000...


I think Its human nature to relax when you are on top, "human" in the terms that you have empathy aka "humanity" etc,

now.....

if as a human being you lack the brain component that gives the emotion of empathy (amygdala), i.e. you are a psychopath (which my translation from Greek would be "an ailment of the soul") or as they call it nowadays sociopathy then the likelihood is that you would never relax as the fulfilment for the sociopath is to enrich their own self worth.

With saying that, im glad that AMD are erring to the side of being "human" rather then being solely run by a bunch of sociopaths, which if you read the history of Intel, you can come to your own conclusions on Intels management

😂😂



Audioboxer said:


> I couldn't care less what name is on something, I've never really fallen down the brand loyalty slide when it comes to PC components. I buy what reviews well, is priced well and what has a decent community around it.
> 
> But given this is an AMD topic and currently I have an AMD CPU and mobo, I enjoy moaning about what I currently own
> 
> And cmon, the AGESA bugs recently have been effing wild. From straight up locking VDDG voltages by accident, to capping CPU voltage for no reason, to USB issues and now we've got performance regression due to fTPM modules.
> 
> On my 3900xt it was horrendous power plans the community had to fix and even now on 5950x chipset drivers randomly come and go because parts of them end up missing, or when Windows 11 launched there was weeks of the memory latency issues.
> 
> Perfectly fine reasons to grumble about the Q&A processes at AMD that keep allowing really buggy BIOS releases and broken software.
> 
> Heck, AMD Ryzen Master is in a pretty rough state and no effort has been put in to clean it up.
> 
> That doesn't mean everything is all rosy on the Intel side, but AMD have made a hell of a lot of money being the market leader in many metrics on CPUs for years, how about listening to some feedback?


Expectation, expectations, yes AMD have not given us enthusiasts what we want consistently, but keep in mind that is "what we want", its not what the "market wants", so all this doo da that is going on with agesa, is part of our own bubble.

And if you have read enough info you will know that in cutting edge technology, most time things are not working like clock work each and every time.

I think the majority of people forget basic things, such as the complexity of the whole system that entails the hobby we participate in.

It is such a multifaceted puzzle that when one piece is not working correctly eveything else does not perform as its should, for example the relation of software with hardware.

And because of this complexity and the pressures of bringing products to market, then many times, things are rushed and the results we are seeing are all a consequence of these actions.

In a perfect World AMD would not be under pressure to perfect every single facet of the chain and we would get perfectly working products (if such a thing could ever exist), but this is not the reality of the current World and never will be ......

So from my mindset, this is why I laugh at the "whining" as not too far in the past I was also one of those "whiners" until experience and age along with maturity (to some extent 😂😂 ) caught up with me ...

A prime example is all the crying that is going on with regards to the upcoming 5800X3D V-cache model.

Im quoting a post below from another forum from a user called "Saylick" and it sums up things perfectly for me



Saylick said:


> AMD has said that they've locked down the 5800X3D because V-cache is new to the market and so they don't have enough data to validate whether or not there's heat/electrical issues with V-cache.
> 
> They could have delayed the launch of V-cache until all of it was sorted out, but instead of doing that they decided it was easier to simply back off the clocks a bit to cover their butt so that they could get the product out to market sooner.
> 
> They chose to give V-cache to the masses sooner rather than later and something had to give; that something was OC support. That's their argument. Take it or leave it. If you don't believe their reasoning because you believe you are some kind of semiconductor guru and that you know more than AMD about their own products, then that's on you.
> 
> If you think AMD releasing this product sooner means they are releasing it as a beta product, you are more than welcome to wait for the next generation of V-cache products that have overclocking/undervolting support.
> 
> There's no "ADF" here. The same people who rag on this product would likely be the same people who'd rag on it if it came out 6 months later with OC support because it was "too little, too late, Zen 4 and Raptorlake are already out".


----------



## Imprezzion

I like how AMD handled this. The chip has a good competitive price point (if performance lives up to the claims) and they give people basically what they want and are very transparent with the reasoning why OC is disabled for the cores. They even did the effort of allowing and enabling / keeping enabled the FCLK and memory OC functionality so. No complaints here. I might even get one just for the hell of it if it actually does outperform a 5900X in gaming by a good margin. 

I did find the minimum vSOC I can run at 1866 FCLK by process of elimination lol. I had it set to 1.100v which was totally fine but decided to see how low I could go without WHEA's or memory instability to give my cores ever so slightly more power budget and temp headroom and I ended up at 1.062v. It does run 1.050v fine without crashing or hard locking however it did give me a few WHEA's running TM5 which it doesn't do at 1.062 so that's my bottom limit for vSOC.

Is there a point to trying to lower VDDP/VDDG's?


----------



## Audioboxer

gameinn said:


> I used to think this too but isn't it just a myth? Igor did a very good review of Alder on launch about power stuff: Intel Core i9-12900K(F), Core i7-12700K and Core i5-12600K Review - Gaming in really fast and really frugal | Part 1 | Page 5 | igor'sLAB
> 
> I mean I guess in terms of gaming Alder is better but I guess in something like blender it's a whole other story.


Nah, it's pretty well established Intel have achieved some of their performance boost over AMD through bruteforcing power draw. There is nothing wrong with that, it's not as if our power supplies can't handle a CPU chugging down 250-300w+. Heck, I can get my 5950x to 250w in CB23.

Just saying AMD have created effeciency beasts when it comes to their CPU power draw versus performance. Intel need to improve there.



mongoled said:


> I think Its human nature to relax when you are on top, "human" in the terms that you have empathy aka "humanity" etc,
> 
> now.....
> 
> if as a human being you lack the brain component that gives the emotion of empathy (amygdala), i.e. you are a psychopath (which my translation from Greek would be "an ailment of the soul") or as they call it nowadays sociopathy then the likelihood is that you would never relax as the fulfilment for the sociopath is to enrich their own self worth.
> 
> With saying that, im glad that AMD are erring to the side of being "human" rather then being solely run by a bunch of sociopaths, which if you read the history of Intel, you can come to your own conclusions on Intels management
> 
> 😂😂
> 
> 
> Expectation, expectations, yes AMD have not given us enthusiasts what we want consistently, but keep in mind that is "what we want", its not what the "market wants", so all this doo da that is going on with agesa, is part of our own bubble.
> 
> And if you have read enough info you will know that in cutting edge technology, most time things are not working like clock work each and every time.
> 
> I think the majority of people forget basic things, such as the complexity of the whole system that entails the hobby we participate in.
> 
> It is such a multifaceted puzzle that when one piece is not working correctly eveything else does not perform as its should, for example the relation of software with hardware.
> 
> And because of this complexity and the pressures of bringing products to market, then many times, things are rushed and the results we are seeing are all a consequence of these actions.
> 
> In a perfect World AMD would not be under pressure to perfect every single facet of the chain and we would get perfectly working products (if such a thing could ever exist), but this is not the reality of the current World and never will be ......
> 
> So from my mindset, this is why I laugh at the "whining" as not too far in the past I was also one of those "whiners" until experience and age along with maturity (to some extent 😂😂 ) caught up with me ...
> 
> A prime example is all the crying that is going on with regards to the upcoming 5800X3D V-cache model.
> 
> Im quoting a post below from another forum from a user called "Saylick" and it sums up things perfectly for me


I'm not whinging about 3D cache though. Months back I was optimistic it might mean a 3D cache 5900/5950 and we might see something working above 1900 FCLK. I've totally accepted due to the way AMD designed AM4 memory is what it is. If you want to run memory above 3800 with proper performance you simply need to go Intel. End of.

The things AMD are awful with is general stability with software and communication about what they're doing with their own hardware when they suddenly seem to decide what you were able to do yesterday with your CPU, we're stopping you doing that tomorrow. Years after the CPU released...

Is it a bug? Is it a change? Nobody knows. Please wait 4-5 months for BIOS updates and then scramble online each time one comes out to ask the community if anything has been fixed. Whilst you also ask "Is there anything new broken?".

As for boiling it down to "simple folks in the wider market" versus "students of Veii and Buildzoid who know the black arts of OCing". Can't say I agree. The people buying the most expensive AMD hardware at launch and even generally throughout the life of the product are us. YouTube has made it easier than ever to try and get into OCing. If AMD keep pissing off those who drop the most money on their hardware it will shift the needle in terms of all the advertising and word of mouth they get. Arrogance can quite quickly lead to your reign at the top ending.

Intel have been a bit of a joke with CPUs for years, but they're clearly making moves to sort that out. AMD has been at the top of their game in terms of hardware for years, they seem to be trying to do everything possible to send parts of the market back to Intel.


----------



## Taraquin

Audioboxer said:


> I couldn't care less what name is on something, I've never really fallen down the brand loyalty slide when it comes to PC components. I buy what reviews well, is priced well and what has a decent community around it.
> 
> But given this is an AMD topic and currently I have an AMD CPU and mobo, I enjoy moaning about what I currently own
> 
> And cmon, the AGESA bugs recently have been effing wild. From straight up locking VDDG voltages by accident, to capping CPU voltage for no reason, to USB issues and now we've got performance regression due to fTPM modules.
> 
> On my 3900xt it was horrendous power plans the community had to fix and even now on 5950x chipset drivers randomly come and go because parts of them end up missing, or when Windows 11 launched there was weeks of the memory latency issues.
> 
> Perfectly fine reasons to grumble about the Q&A processes at AMD that keep allowing really buggy BIOS releases and broken software.
> 
> Heck, AMD Ryzen Master is in a pretty rough state and no effort has been put in to clean it up.
> 
> That doesn't mean everything is all rosy on the Intel side, but AMD have made a hell of a lot of money being the market leader in many metrics on CPUs for years, how about listening to some feedback?


I have had viritually no issues with both my 3600 and 5600X, the first was a poor bin, but ran stock fine and stable and could do 3733 fine. 5600X is awesome. 

My 12400F on the other hand has been a nightmare woth lots of bsod, file corruption etc. Now on a beta bios it seems stable. ADL has been a bumby road, bios mess, DDR4 ram support on locked cpus and DDR5 has had major isdues, but it's beginning to improve. 

One major differemce is that while AMD now supports 4 gens of CPUs over 5 years, Intel only allows for 2 gens. This makes compability a lot easier for Intel. 

For the high end entusiasts I think Intel is the champ, but for me, a budget gamer/overclocker that can get top notch perf on a 100usd MB and 140usd ram I like AMD. On Intel I would have to buy a 300usd+ MB to get the most of it and a K-cpu (except for the blooper with bclk OC on some B660 and locked CPUs.) 

The complexity adds to the problems with AMD, I decided early on that I would get a single CCD cpu and a simple 2 dimm MB and it sure payed off  On Intel I would have made a different and much more expensive approach.


----------



## Taraquin

Imprezzion said:


> I like how AMD handled this. The chip has a good competitive price point (if performance lives up to the claims) and they give people basically what they want and are very transparent with the reasoning why OC is disabled for the cores. They even did the effort of allowing and enabling / keeping enabled the FCLK and memory OC functionality so. No complaints here. I might even get one just for the hell of it if it actually does outperform a 5900X in gaming by a good margin.
> 
> I did find the minimum vSOC I can run at 1866 FCLK by process of elimination lol. I had it set to 1.100v which was totally fine but decided to see how low I could go without WHEA's or memory instability to give my cores ever so slightly more power budget and temp headroom and I ended up at 1.062v. It does run 1.050v fine without crashing or hard locking however it did give me a few WHEA's running TM5 which it doesn't do at 1.062 so that's my bottom limit for vSOC.
> 
> Is there a point to trying to lower VDDP/VDDG's?


It is good to run soc, vddg and vddp as low as possible w/o perf reduction/stability issues since it eats from your pwr budget. If you run unlimited PPT it doesn't matter that much, but lower voltages will lower consumption and temp. 

A basic check on my setup:
Running CCD at 950 vs 840mv made IOD use 1-2W more which lowered allcore clocks by 25MHz at 76W PPT. 
Running soc at 1.15v, iod at 1.05v, ccd at 1v and vddp at 0.9v made IO-die use over 5W extra which lowered allcore clocks by 75-100MHz vs 1.12v soc, 1.04v iod and 0.84v ccd and vddp at 76W PPT.


----------



## Taraquin

Audioboxer said:


> Nah, it's pretty well established Intel have achieved some of their performance boost over AMD through bruteforcing power draw. There is nothing wrong with that, it's not as if our power supplies can't handle a CPU chugging down 250-300w+. Heck, I can get my 5950x to 250w in CB23.
> 
> Just saying AMD have created effeciency beasts when it comes to their CPU power draw versus performance. Intel need to improve there.
> 
> 
> 
> I'm not whinging about 3D cache though. Months back I was optimistic it might mean a 3D cache 5900/5950 and we might see something working above 1900 FCLK. I've totally accepted due to the way AMD designed AM4 memory is what it is. If you want to run memory above 3800 with proper performance you simply need to go Intel. End of.
> 
> The things AMD are awful with is general stability with software and communication about what they're doing with their own hardware when they suddenly seem to decide what you were able to do yesterday with your CPU, we're stopping you doing that tomorrow. Years after the CPU released...
> 
> Is it a bug? Is it a change? Nobody knows. Please wait 4-5 months for BIOS updates and then scramble online each time one comes out to ask the community if anything has been fixed. Whilst you also ask "Is there anything new broken?".
> 
> As for boiling it down to "simple folks in the wider market" versus "students of Veii and Buildzoid who know the black arts of OCing". Can't say I agree. The people buying the most expensive AMD hardware at launch and even generally throughout the life of the product are us. YouTube has made it easier than ever to try and get into OCing. If AMD keep pissing off those who drop the most money on their hardware it will shift the needle in terms of all the advertising and word of mouth they get. Arrogance can quite quickly lead to your reign at the top ending.
> 
> Intel have been a bit of a joke with CPUs for years, but they're clearly making moves to sort that out. AMD has been at the top of their game in terms of hardware for years, they seem to be trying to do everything possible to send parts of the market back to Intel.


As for ram oc, look at the ADL ddr4 tread. If you have a locked CPU best to expect is 3400-3600 in gear 1 due to locked SA voltage. If you have a K cpu you can get 3800-4300 in gear 1. As for Ryzen 5k it seems 90% of the CPUs do 3733 or 3800 fine, and a few 5600X/5800X on 2 dimm MBs (like me and Veii) do 4000+ with better perf vs 3800 but Intel is not that much better. Comet (and Renoir/Cezanne) lake were the last good IMC which could run gear 1 ram at 4400+.

Most gamers run things stock, many don't enable xmp, on ADL running DDR4 stock and xmp on 3600+ sets ram to gear 2. User is unaware of the turd performance. I think only 10% of gamers overclock and of those maybe 2% fine tune like us. 

As for hardware test 95% of reviewers only test stock and a basic allcore oc. Very few test ram oc, cache oc etc but i2hard, gamers nexus, tech yes city and a few others do sometimes. 

As for what to exoect I see many people with ADL struggling with 5GHz oc or getting ram in gear 1 abover 3900. Like us struggling with CO or getting ram above 3733. It's not so different, but agesa makes cheap boards good and expensive boards turds vs Intel where cheap is bad and expensive is good.


----------



## Taraquin

Mannix-ITA: I'm an Intel fanboy, but I'm also an AMD fanboy, it comes down to bang for bucks. Between 2011 and 2017 I was a fan of neither. AMD had good prices, but **** perf, Intel had the opposite. After Ryzen gen 1 everything changed. 

I have to say that my B660+12400F has been much more of a pain than my 3600 and 5600X, but being a ADL betatester I knew what I had coming.


----------



## Audioboxer

Taraquin said:


> As for ram oc, look at the ADL ddr4 tread. If you have a locked CPU best to expect is 3400-3600 in gear 1 due to locked SA voltage. If you have a K cpu you can get 3800-4300 in gear 1. As for Ryzen 5k it seems 90% of the CPUs do 3733 or 3800 fine, and a few 5600X/5800X on 2 dimm MBs (like me and Veii) do 4000+ with better perf vs 3800 but Intel is not that much better. Comet (and Renoir/Cezanne) lake were the last good IMC which could run gear 1 ram at 4400+.
> 
> Most gamers run things stock, many don't enable xmp, on ADL running DDR4 stock and xmp on 3600+ sets ram to gear 2. User is unaware of the turd performance. I think only 10% of gamers overclock and of those maybe 2% fine tune like us.
> 
> As for hardware test 95% of reviewers only test stock and a basic allcore oc. Very few test ram oc, cache oc etc but i2hard, gamers nexus, tech yes city and a few others do sometimes.
> 
> As for what to exoect I see many people with ADL struggling with 5GHz oc or getting ram in gear 1 abover 3900. Like us struggling with CO or getting ram above 3733. It's not so different, but agesa makes cheap boards good and expensive boards turds vs Intel where cheap is bad and expensive is good.


Who in this topic would be buying a locked Intel CPU though? lol

Again, I'm not painting everything as rosy on the Intel side, I just don't think the most basic and polite criticism of how AMD has been handling software/the BIOS is somehow unfair on AMD or requires me to compromise.

Heck, you want me to criticse outside of AMD/Intel, sure, lets talk about MS' awful launch of Windows 8 and Windows 11. I've got a Samsung mobile, I'll happily talk about how bad touchwizz was and how Samsung still bloat the hell out of Android.

Lots of companies are awful with software at times, but this is an AMD topic in the AMD section of OC.net and the last 4~6 months especially have been pretty comical with AGESA/chipset. As I mentioned earlier even when I had a 3900XT it needed the community to fix the powerplans.

Veii has gone into more depth than I ever could about how AMD makes life pretty hellish for the platform providers. Them left trying to fix AMD's jank.


----------



## ManniX-ITA

mongoled said:


> With saying that, im glad that AMD are erring to the side of being "human" rather then being solely run by a bunch of sociopaths, which if you read the history of Intel, you can come to your own conclusions on Intels management


  



mongoled said:


> In a perfect World AMD would not be under pressure to perfect every single facet of the chain and we would get perfectly working products (if such a thing could ever exist), but this is not the reality of the current World and never will be ......


Maturity is not perfection 
We are not wishing for something unrealistic, just the average industry standard.
I think it's the right time for moaning 
Have to decide where to spend a lot of money when I'm going DDR5... pardon me but I need to think thoroughly about it.
Especially after this extremely disappointing RMA process with AMD.



mongoled said:


> Im quoting a post below from another forum from a user called "Saylick" and it sums up things perfectly for me


No I don't agree at all with this analysis.
You do all this stuff *before *going public with your CEO boasting this tech on video.

_"too little, too late, Zen 4 and Raptorlake are already out"_
Yes, if you are not ready don't announce it
And maybe think twice before selling it

_If you think AMD releasing this product sooner means they are releasing it as a beta product, you are more than welcome to wait for the next generation of V-cache products that have overclocking/undervolting support._
This is not the point.
Of course we have the choice to not buy it
And AMD is a private company, they can do whatever they want.
Certainly doesn't need our approval. 

It's a matter of *confidence and strategy*
Both for the investors and the consumers

I'm not an investor so I'm not concerned about how much money I can make with my stocks
But it matters cause if the investors doesn't have confidence in what the execs are doing there'll be less money for the company
Their strategy will change and they'll start keeping the company on a leash

As a consumer of course I'm worried about it if I intend to spend money for years on their products
Wasted effort on a too early and not remunerative product is a problem for me as well
Means the effort I was expecting they would put on my 5950X will be redirected on the, single, 3D product
Which will probably not bring any money back to AMD which will have to cut the effort on supporting legacy and focus on the new ones, those that will make money
Investors confidence goes down, mine as well
Which means I'll stop recommending AMD to my friends or relatives, change of strategy

Today is all about NPS (and sales figures of course)









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Converting an enthusiast into a detractor is a tragedy
It's 100 times more difficult the opposite conversion
The negative impact of a detractor is 10 times more than the positive impact of an enthusiast
That's why all companies are so willing to spend money and effort into luring influencers in their orbits
One powerful influencer can nullify thousands of detractors with a single tweet
it's not _that irrelevant_ what is the general mood within the OC community...


----------



## Taraquin

Audioboxer said:


> Who in this topic would be buying a locked Intel CPU though? lol
> 
> Again, I'm not painting everything as rosy on the Intel side, I just don't think the most basic and polite criticism of how AMD has been handling software/the BIOS is somehow unfair on AMD or requires me to compromise.
> 
> Heck, you want me to criticse outside of AMD/Intel, sure, lets talk about MS' awful launch of Windows 8 and Windows 11. I've got a Samsung mobile, I'll happily talk about how bad touchwizz was and how Samsung still bloat the hell out of Android.
> 
> Lots of companies are awful with software at times, but this is an AMD topic in the AMD section of OC.net and the last 4~6 months especially have been pretty comical with AGESA/chipset. As I mentioned earlier even when I had a 3900XT it needed the community to fix the powerplans.
> 
> Veii has gone into more depth than I ever could about how AMD makes life pretty hellish for the platform providers. Them left trying to fix AMD's jank.


Bought it for my kids expecting to run 3800 gear 1 easy, but Intel sabotaged that with locked SA voltage  

A lot of companies do a lot of awful. AMDs agesa approach is a nightmare for many entusiasts, but awesome for those running stock/do light tweaks. ADL has been a pain for many just running xmp, similar to Ryzen gen 1.


----------



## ManniX-ITA

Taraquin said:


> Mannix-ITA: I'm an Intel fanboy, but I'm also an AMD fanboy, it comes down to bang for bucks. Between 2011 and 2017 I was a fan of neither. AMD had good prices, but **** perf, Intel had the opposite. After Ryzen gen 1 everything changed.
> 
> I have to say that my B660+12400F has been much more of a pain than my 3600 and 5600X, but being a ADL betatester I knew what I had coming.


This makes you even 

Yes, I've read about a lot of problems with AL.
In my experience, I've seen a few and were all running fine, except the horrid temperatures.

I didn't even remotely considered Zen1 to be honest.
Except the good price it wasn't providing respectable performances for me.

AMD did a good job with Zen2 and Zen3.
Really good and innovative.
But I fear they are steering into a wrong direction now that they are again under pressure.

Alder Lake was of course an early adopters bet.
And it shows all the goodies and downsides of it.
No thanks 

I'll think about Raptor Lake with 7xx boards as an option.
If there's some decent maturity and it's really crushing the 7000...


----------



## Audioboxer

Taraquin said:


> Bought it for my kids expecting to run 3800 gear 1 easy, but Intel sabotaged that with locked SA voltage
> 
> A lot of companies do a lot of awful. AMDs agesa approach is a nightmare for many entusiasts, but awesome for those running stock/do light tweaks. ADL has been a pain for many just running xmp, similar to Ryzen gen 1.


Biggest difference with Intel is how latency works though. That mattered less when Intel were releasing total dud CPUs for years. This generation has finally caught up to the performance of AMD and I presume latency on memory isn't hampered in the same way it is with the AM4 architecture.

Not saying AMD has done anything wrong here (memory architecture), it's just another pointer to why because you're the king for years it doesn't mean you never get challenged on your throne. I'm happy with this kind of battle, it's what causes the industry to be healthy. Competition is good.

The software side of things is less easy to forgive because often it's bugs and mistakes. When it's not bugs it's no communication so we have no idea if the voltage cap with EDC is AMD deciding to hurt the OCing community at the end of the generation. Why? Who knows, maybe you lot RMAimg CPUs non-stop 😂😜

The added joke on top of this in true AMD fashion is the piece of their own software they've ignored for years, AMD Ryzen Master, can skip the EDC voltage lock and allow you to set EDC to whatever you want in Windows.... Most "normal folks" that don't do much OCing are likely setting PBO values with Ryzen Master after watching a YT video. So much for limiting voltage to protect said "normal folks" lol.

All this sort of feedback now and in the year prior is the kind of noise AMD should be listening to for AM5. Because if they bollocks the launch of that up then more people will look to Intel. Which again, there is nothing wrong with that, but it would be nice if we've got two big chip providers on their game at the same time.


----------



## Veii

Audioboxer said:


> As for boiling it down to "simple folks in the wider market" versus "students of Veii and Buildzoid who know the black arts of OCing".


I whine too much too, when can of issues overflows
But i try to keep whining in the scale of remembering past issues and resolves, not in repeating and begging for the same issue to be fixed
* subtle difference

Sadly, issue one, digging deeper into it , exposes issue 2 and 3
Too often people aren't aware of an issue at all (which is a good thing in this case)
~ but the bad thing is, it will unlikely get ever fixed

It's not good practice either, to compare overclocker with a semiconductor title
We move in the similar realm, but QC checks do not cover exotic usages with non optimal laboratory defaults
~ such as thermal headroom , EMI (wireless) and plain simply humidity or fingerprints
Also overclocking by the core doesn't always mean bettering up the foundation for the same "daily" principle *
* yet is for everyone to decide which path to take, what kind of exotic scenario the hardware is exposed and tries to cover outside of laboratory QC

As for X3D,
Mr Hallock delivered a very unprofessional but humane interview.
It is fine, took the more humane side with a living room earphones shaky cam interview ~ it fits to him i think
~ but approach vs delivery differed.

There is a problem,
Half of the interview although with snippets of information, was propaganda about what "other rivals do wrong"
Vs the quality of their own products
Too many of the sentences i skimmed over where
"take a look at the lack of powermanagement on Intel"
"our benchmarks for maximum performance only are not suitable enough, it doesn't show the other picture why we are better than our competitors"
yada yada yada

What mostly was interesting, is X3D's approach tho,
He for once could comment that their decision was enforced on Vendors and it's their decision
The samples do hold to 1.3-1.35v , are limited as such and the decision has been made to pro-actively lock it down on the core design
Fully focusing on locking down Vermeer in a soft and firmware state, pro-actively messing with Vermeer consumer too

I've been pausing activity on this forum to control overwhelming amount of goals and work,
Soo some things have been focused being HWLUXX exclusive , with snippets of sharing in PM
The Problem is not the secureness of the platform and stability
(although it seems according to public face, Mr Hallock still expects such from us)
The idea of giving any sort of guidance was trown away, as we consumer do not understand their platform.
That's the stand they took and on what i am absolutely not happy about.

Well,
It wasn't hard to "just let people who's focus is to push the platform ~ just kill their CPUs"
~ but it was rather outweight including to what i continue to read // that we OCers are irrelevant, we understand nothing, we are not semiconductors , how dare we even try and explore their platform

Mr. Hallock was very proud to pose with how locked their new architecture is
"it's locked-locked, there is no way. We decided it and so it will be" 
Very, how to say it ~ warfocused approach, psychological approach but honestly so was most of the interview from his side
Although i find sympathy for the humane direction chosen, it was hard to watch with all these competitor comparisons

I work on X3D , slightly
From several points and sources ~ as by accident figured something out and the rest felt in pace

Curve optimizer and another method of undervolting functions
FCLK OC functions
* these are personal experiences
FCLK is interesting but that's all to say here

The reason for abandoning 2nd CCD was powerdraw and heat density
They are very hard to cool, for a CPU that might just move in the 4.7ish realm (no fixed peak)
It remains to be the same B2/V architecture, with the same type of powermanagement and same type of voltage and package throttle algorithms.
It's not a new platform, not a new microcode and doesn't require to be on 1206 or newer security patched AGESA's

I have 4 methods for it to get working
the most easiest of all functions, soo i stopped with the snippets shared
[Übersicht] - Ultimative AM4 UEFI/BIOS/AGESA Übersicht startign here but in personal-german written. Translations are very rough

There are two more options to get it working:
~ one is doing bios mods for 162 boards, and re-injecting fields that proactively where removed (45min per bios)
~ using AMI tools, to enforce specific settings to stick independent of what bios exposes (my main focus)
yet leaking them, getting copyright striked & making issues to the platform hosting them
* both are bad outcomes, just because AMD decided, we are not capable working with our own products

Hydra, PBO Tuner, ZenTimings, ZenPTMonitor ~ all will function
It's up to Vengeance Team reading over our threads to decide how much of our left freedom will be limited by shadow updates
Soo even tho i decided to limit shared information till 1207 is out, it's annoying to see people experiencing lockdown bugs for platforms that should be independent of X3D
(well you can't, when your focus on locking a CPU , accidentally breaks the whole Vermeer , Cezanne and Renoir lineup. . .)
~ but so was the decision made & the OC restriction for vermeer consumer lift on 1206C (but hardlocked X3D)

For what:
~ So we lack the ability to more advancedly undervolt utilizing AMD's powermanagement
~ We do not mess up cache with "by them unknown architectural limits"
~ AMD stays ignorant about potential contributions the amateur OC group could deliver
~ And to protect their AM5 product stack on something that pushed us creating e-waste, as Gen-X being the last architecture shared

I don't understand how you can be soo close minded with your engineers.
The same engineers that decided to ignore your interests and just share HW-Modified samples to the public from their fabs ~ as substrate is more than capable
Ah, it's a rant again.
Well , we will see 

I have something in work
Either it fails miserably, publicly embarrasses me as i lost and forgot some new introduced lockdown
Or i win, and embarrass Mr Hallock and their team
Two outcomes i'm unsatisfied with ~ but the challenge is fun, soo let's see if they'll win again

Short reminder, Navi and MPT
SOCCLK, fabric clock and powerdraw management *🤭*


----------



## Audioboxer

Veii said:


> I whine too much too, when can of issues overflows
> But i try to keep whining in the scale of remembering past issues and resolves, not in repeating and begging for the same issue to be fixed
> * subtle difference
> 
> Sadly, issue one, digging deeper into it , exposes issue 2 and 3
> Too often people aren't aware of an issue at all (which is a good thing in this case)
> ~ but the bad thing is, it will unlikely get ever fixed
> 
> It's not good practice either, to compare overclocker with a semiconductor title
> We move in the similar realm, but QC checks do not cover exotic usages with non optimal laboratory defaults
> ~ such as thermal headroom , EMI (wireless) and plain simply humidity or fingerprints
> Also overclocking by the core doesn't always mean bettering up the foundation for the same "daily" principle *
> * yet is for everyone to decide which path to take, what kind of exotic scenario the hardware is exposed and tries to cover outside of laboratory QC
> 
> As for X3D,
> Mr Hallock delivered a very unprofessional but humane interview.
> It is fine, took the more humane side with a living room earphones shaky cam interview ~ it fits to him i think
> ~ but approach vs delivery differed.
> 
> There is a problem,
> Half of the interview although with snippets of information, was propaganda about what "other rivals do wrong"
> Vs the quality of their own products
> Too many of the sentences i skimmed over where
> "take a look at the lack of powermanagement on Intel"
> "our benchmarks for maximum performance only are not suitable enough, it doesn't show the other picture why we are better than our competitors"
> yada yada yada
> 
> What mostly was interesting, is X3D's approach tho,
> He for once could comment that their decision was enforced on Vendors and it's their decision
> The samples do hold to 1.3-1.35v , are limited as such and the decision has been made to pro-actively lock it down on the core design
> Fully focusing on locking down Vermeer in a soft and firmware state, pro-actively messing with Vermeer consumer too
> 
> I've been pausing activity on this forum to control overwhelming amount of goals and work,
> Soo some things have been focused being HWLUXX exclusive , with snippets of sharing in PM
> The Problem is not the secureness of the platform and stability
> (although it seems according to public face, Mr Hallock still expects such from us)
> The idea of giving any sort of guidance was trown away, as we consumer do not understand their platform.
> That's the stand they took and on what i am absolutely not happy about.
> 
> Well,
> It wasn't hard to "just let people who's focus is to push the platform ~ just kill their CPUs"
> ~ but it was rather outweight including to what i continue to read // that we OCers are irrelevant, we understand nothing, we are not semiconductors , how dare we even try and explore their platform
> 
> Mr. Hallock was very proud to pose with how locked their new architecture is
> "it's locked-locked, there is no way. We decided it and so it will be"
> Very, how to say it ~ warfocused approach, psychological approach but honestly so was most of the interview from his side
> Although i find sympathy for the humane direction chosen, it was hard to watch with all these competitor comparisons
> 
> I work on X3D , slightly
> From several points and sources ~ as by accident figured something out and the rest felt in pace
> 
> Curve optimizer and another method of undervolting functions
> FCLK OC functions
> * these are personal experiences
> FCLK is interesting but that's all to say here
> 
> The reason for abandoning 2nd CCD was powerdraw and heat density
> They are very hard to cool, for a CPU that might just move in the 4.7ish realm (no fixed peak)
> It remains to be the same B2/V architecture, with the same type of powermanagement and same type of voltage and package throttle algorithms.
> It's not a new platform, not a new microcode and doesn't require to be on 1206 or newer security patched AGESA's
> 
> I have 4 methods for it to get working
> the most easiest of all functions, soo i stopped with the snippets shared
> [Übersicht] - Ultimative AM4 UEFI/BIOS/AGESA Übersicht startign here but in personal-german written. Translations are very rough
> 
> There are two more options to get it working:
> ~ one is doing bios mods for 162 boards, and re-injecting fields that proactively where removed (45min per bios)
> ~ using AMI tools, to enforce specific settings to stick independent of what bios exposes (my main focus)
> yet leaking them, getting copyright striked & making issues to the platform hosting them
> * both are bad outcomes, just because AMD decided, we are not capable working with our own products
> 
> Hydra, PBO Tuner, ZenTimings, ZenPTMonitor ~ all will function
> It's up to Vengeance Team reading over our threads to decide how much of our left freedom will be limited by shadow updates
> Soo even tho i decided to limit shared information till 1207 is out, it's annoying to see people experiencing lockdown bugs for platforms that should be independent of X3D
> (well you can't, when your focus on locking a CPU , accidentally breaks the whole Vermeer , Cezanne and Renoir lineup. . .)
> ~ but so was the decision made & the OC restriction for vermeer consumer lift on 1206C (but hardlocked X3D)
> 
> For what:
> ~ So we lack the ability to more advancedly undervolt utilizing AMD's powermanagement
> ~ We do not mess up cache with "by them unknown architectural limits"
> ~ AMD stays ignorant about potential contributions the amateur OC group could deliver
> ~ And to protect their AM5 product stack on something that pushed us creating e-waste, as Gen-X being the last architecture shared
> 
> I don't understand how you can be soo close minded with your engineers.
> The same engineers that decided to ignore your interests and just share HW-Modified samples to the public from their fabs ~ as substrate is more than capable
> Ah, it's a rant again.
> Well , we will see
> 
> I have something in work
> Either it fails miserably, publicly embarrasses me as i lost and forgot some new introduced lockdown
> Or i win, and embarrass Mr Hallock and their team
> Two outcomes i'm unsatisfied with ~ but the challenge is fun, soo let's see if they'll win again
> 
> Short reminder, Navi and MPT
> SOCCLK, fabric clock and powerdraw management *🤭*


Definitely agree on the lockdown bugs for platforms that aren't using the 3D cache. I personally want to class them as bugs because it's not something we had 6 months ago, but due to a lack of communication from AMD we're left not knowing if they're choosing to lock us down or AGESA is just bugged and incorrectly targeting us instead of just the X3D.

Here is my funny question, how will Ryzen Master handle the X3D chips? 😂 Even AMD must be aware you can get around their current 1.425v voltage cap with EDC if you just change your EDC in Ryzen Master rather than the BIOS lol.


----------



## Farih

I went from 2 sticks of RAM to 4 sticks.
All the same sticks ofc.

G.Skill F4-3600C16-8GVK (8GB, SR)
(Samsung B-Die)

Had them slightly OC'ed from 3600 CL16 to 3800 CL16 with some tighter sub-timings.

When going from 2 to 4 sticks the PC not post.
Reset to stock to get into BIOS.

To get them to post on 3800mhz CL16 i had to change Rttnom from "Off" to "RZQ/7"
This wasn't fully stable in Windows yet.
Then changed tRFC from 272 to 304. (including lowering tRFC2 to 226 and tRFC3 to 139)
I can run Memtest5 without errors now.

But whenever i restart or cold boot the PC will not boot.
It takes 3-5 try's to boot.
Once its booted its seems to run stable.

Upping voltage from 1.425 to 1.46V did not work.

Anything i can do so my PC can boot/restart normally?


----------



## Veii

Audioboxer said:


> Definitely agree on the lockdown bugs for platforms that aren't using the 3D cache. I personally want to class them as bugs because it's not something we had 6 months ago, but due to a lack of communication from AMD we're left not knowing if they're choosing to lock us down or AGESA is just bugged and incorrectly targeting us instead of just the X3D.
> 
> Here is my funny question, how will Ryzen Master handle the X3D chips? 😂 Even AMD must be aware you can get around their current 1.425v voltage cap with EDC if you just change your EDC in Ryzen Master rather than the BIOS lol.


X3D samples were/are SMU locked
PBO OC, VDDG OC, SOC Uncore OC ~ all class as SMU based interactions

If you proactively disable that link, nothing passes through and the chips fall to their own fab state
Low SOC voltage, low VDDG voltage and PBO + CO not functioning at all - even tho is enabled
* it's a surprise BAR mode functioned, but such is a fully split bios module

They "can" lock 2nd batch of X3D down to being substrate voltage limited.
It also likely will be done now that some snippets of information was shared & a fix accidentally was leaked
But they can not patch first batch away, without users installing their PSP-FW patch "by accident"
Be it chipset updates, just new AGESA or the microcode OTA update-modules in Win/Sys32 & SysWoW

Because neither of the tools where allowed to communicate and HSMP + RSMU where restricted, Ryzen Master will not do anything
HSMP "was" restricted on stock, meaning nothing CO related does pass and powerlimits of X3D where enforced without the ability of change

To have them functioning on pre AGESA 1204 bioses, you have to gamble that it won't lock itself down when you install it
Or boots to windows, or gets online . . .
Too many proactive measures to focus on locking it down ~ yet no proactive measure to focus on Vermeer's [by FIT] overvolting setup "on stock" // except for the attempt of overdoing it and increasing RMA rate

I would like to ask their engineer department, what bad dream of night it was ~ to change their mindset from:
~ It works how it was, our substrate by our own engineers was marked as capable, we designed it did not HW-Lock it down as there was no need, it already shipped out last month
to:
~ We are afraid consumers messing up their CPU, we disabled the APU part, we published already AGESAs with split Core & APU CO // but trow all that effort out, just because we do not trust our OC userbase to know how to use their own products ~ yet can not deliver even a guidance how to work with them.

It makes me wonder what kind of bad dream happened, to 180° change their minds in the last minute and invest even more resources on prohibiting OCers using AMD's own API to modify APIs "supported" products and working with "AMDs respected powermanagement"

Meanwhile, we're pushed to,;
~ abandon their powermanagement
~ use their under NDA proprietary API against their decisions
~ and hardwaremod the samples with high risk of fully breaking or frying them
~ ontop of that rely to AMI who AMD has to compile with, in enforcing a change & do damage to AMI by giving the userbase their propriatary tools
(as AMD can not make up their mind on which side they want to be // the ignorant side, or the intelligent side in abusing & copying our free research for them)

*EDIT:*
At least we'll have a bit of fun with memory OC
To the extend we can, as on UCLK dividers no work was done ~ soo why again should somebody prefer AMD over Intel here when we aren't even given 2/3rd of the memory options* either ?
* all sitting in AMD CBS, or not there either

1206B for X3D although with locked SMU mailbox ~ better than 1206C with patched SMU Mailbox
Potentially better even 1204A with by hand unlock, but 1206 has newer CO features (irrelevant)
And memoryOC is a bit better as it seems
Also VDD18 is pushed to 1.68v down now, on some boards
We'll see, just remember that there is nothing that "gives support" to Gen-X when B2 is supported already

Maybe AMD & Vanguard Team will rethink on AGESA 1.2.0.8 that their core reason 1.1.0.0D had lifted FCLK boot-limits // was the outcry of their communities research ~ which they backstab, now again

There is a difference between
"not being able to make changes, by architectural limits"
vs
"thinking for everyone and taking away the core ability, in researching"
Who should even bother creating tools & learning your API, when you trow it away and put it out as worthless, after a bad dream
Who should value the efforts that where put in the micro-powermanagement, when researchers have to abandon it by AMDs own rogue choices


----------



## Veii

Farih said:


> But whenever i restart or cold boot the PC will not boot.
> It takes 3-5 try's to boot.
> Once its booted its seems to run stable.
> 
> Upping voltage from 1.425 to 1.46V did not work.
> 
> Anything i can do so my PC can boot/restart normally?


Increase CsOdtDrvStr [3rd CADBUS value] or try CAD_BUS 30-20-30-24
Potentially even 40-20-30-20 ~ if you drop cLDO_VDDP back to 900mV & lower procODT by 1

Doublecheck memory stability & grab y-cruncher
Run it as key combination 1 enter 7 enter 0 enter for 72min minimum
That is 4 loops of the same 9 tests


----------



## Audioboxer

Veii said:


> X3D samples were/are SMU locked
> PBO OC, VDDG OC, SOC Uncore OC ~ all class as SMU based interactions
> 
> If you proactively disable that link, nothing passes through and the chips fall to their own fab state
> Low SOC voltage, low VDDG voltage and PBO + CO not functioning at all - even tho is enabled
> * it's a surprise BAR mode functioned, but such is a fully split bios module
> 
> They "can" lock 2nd batch of X3D down to being substrate voltage limited.
> It also likely will be done now that some snippets of information was shared & a fix accidentally was leaked
> But they can not patch first batch away, without users installing their PSP-FW patch "by accident"
> Be it chipset updates, just new AGESA or the microcode OTA update-modules in Win/Sys32 & SysWoW
> 
> Because neither of the tools where allowed to communicate and HSMP + RSMU where restricted, Ryzen Master will not do anything
> HSMP "was" restricted on stock, meaning nothing CO related does pass and powerlimits of X3D where enforced without the ability of change
> 
> To have them functioning on pre AGESA 1204 bioses, you have to gamble that it won't lock itself down when you install it
> Or boots to windows, or gets online . . .
> Too many proactive measures to focus on locking it down ~ yet no proactive measure to focus on Vermeer's [by FIT] overvolting setup "on stock" // except for the attempt of overdoing it and increasing RMA rate
> 
> I would like to ask their engineer department, what bad dream of night it was ~ to change their mindset from:
> ~ It works how it was, our substrate by our own engineers was marked as capable, we designed it did not HW-Lock it down as there was no need, it already shipped out last month
> to:
> ~ We are afraid consumers messing up their CPU, we disabled the APU part, we published already AGESAs with split Core & APU CO // but trow all that effort out, just because we do not trust our OC userbase to know how to use their own products ~ yet can not deliver even a guidance how to work with them.
> 
> It makes me wonder what kind of bad dream happened, to 180° change their minds in the last minute and invest even more resources on prohibiting OCers using AMD's own API to modify APIs "supported" products and working with "AMDs respected powermanagement"
> 
> Meanwhile, we're pushed to,;
> ~ abandon their powermanagement
> ~ use their under NDA proprietary API against their decisions
> ~ and hardwaremod the samples with high risk of fully breaking or frying them
> ~ ontop of that rely to AMI who AMD has to compile with, in enforcing a change & do damage to AMI by giving the userbase their propriatary tools
> (as AMD can not make up their mind on which side they want to be // the ignorant side, or the intelligent side in abusing & copying our free research for them)
> 
> *EDIT:*
> At least we'll have a bit of fun with memory OC
> To the extend we can, as on UCLK dividers no work was done ~ soo why again should somebody prefer AMD over Intel here when we aren't even given 2/3rd of the memory options* either ?
> * all sitting in AMD CBS, or not there either
> 
> 1206B for X3D although with locked SMU mailbox ~ better than 1206C with patched SMU Mailbox
> Potentially better even 1204A with by hand unlock, but 1206 has newer CO features (irrelevant)
> And memoryOC is a bit better as it seems
> Also VDD18 is pushed to 1.68v down now, on some boards
> We'll see, just remember that there is nothing that "gives support" to Gen-X when B2 is supported already
> 
> Maybe AMD & Vanguard Team will rethink on AGESA 1.2.0.8 that their core reason 1.1.0.0D had lifted FCLK boot-limits // was the outcry of their communities research ~ which they backstab, now again
> 
> There is a difference between
> "not being able to make changes, by architectural limits"
> vs
> "thinking for everyone and taking away the core ability, in researching"
> Who should even bother creating tools & learning your API, when you trow it away and put it out as worthless, after a bad dream
> Who should value the efforts that where put in the micro-powermanagement, when researchers have to abandon it by AMDs own rogue choices


I accept the market for the 3D cache experiment has ultimately ended up a gamer who wants to plug and play and go, but the worry is the mindset AMD is morphing into overall. Or as you've highlighted, regressing back to.

Makes me worried for AM5. But then again, that's why it's good Intel seems to be sorting itself out after years of disappointing CPU releases.

Right now I'm just pissed off the hardware I currently own is getting hurt by AMD for whatever vision they want for upcoming releases. Leave us alone where we are. For future hardware I will just go to Intel if AMD is making a mess. I bought this 5950x though when AMD was widely credited with doing things well, they learned from the 3xxx crappy powerplans and they introduced the curve and improved ST performance.

That's why I was excited to step up to 59xx in the first place. Why AMD is hurting that perception at the end of the generation is just dumb. There is no need to. I refuse to even believe there is some sort of RMA pandemic with 59xx chips. Most people RMAing in this topic probably just want better silicon 😜

Though there maybe are some suggestions B2 chips are a bit of a mixed bag. That's on whatever AMD has changed with the manufacturing process if you ask me. Not our fault.


----------



## Farih

Veii said:


> Increase CsOdtDrvStr [3rd CADBUS value] or try CAD_BUS 30-20-30-24
> Potentially even 40-20-30-20 ~ if you drop cLDO_VDDP back to 900mV & lower procODT by 1
> 
> Doublecheck memory stability & grab y-cruncher
> Run it as key combination 1 enter 7 enter 0 enter for 72min minimum
> That is 4 loops of the same 9 tests


Thanks for help.

Tryed CsOdtDrvStr to 30, no change.
Then Tryed 30-20-30-24, more succesfull boots/restart but sometimes still didn't post and had RAM led lid up.
Then tryed 40-20-30-20 with cLDO_VDDP back to 900mV, maybe a little bit better as 30-20-30-24 but sometimes still didn't post.


----------



## Audioboxer

Farih said:


> Thanks for help.
> 
> Tryed CsOdtDrvStr to 30, no change.
> Then Tryed 30-20-30-24, more succesfull boots/restart but sometimes still didn't post and had RAM led lid up.
> Then tryed 40-20-30-20 with cLDO_VDDP back to 900mV, maybe a little bit better as 30-20-30-24 but sometimes still didn't post.


Rtts can play a role in not posting cleanly in my experience but I'm not familiar enough with SR to know what to recommend to you. Try playing around with them though.


----------



## Taraquin

ManniX-ITA said:


> This makes you even
> 
> Yes, I've read about a lot of problems with AL.
> In my experience, I've seen a few and were all running fine, except the horrid temperatures.
> 
> I didn't even remotely considered Zen1 to be honest.
> Except the good price it wasn't providing respectable performances for me.
> 
> AMD did a good job with Zen2 and Zen3.
> Really good and innovative.
> But I fear they are steering into a wrong direction now that they are again under pressure.
> 
> Alder Lake was of course an early adopters bet.
> And it shows all the goodies and downsides of it.
> No thanks
> 
> I'll think about Raptor Lake with 7xx boards as an option.
> If there's some decent maturity and it's really crushing the 7000...


Zen+ and Zen 2 had fever issues than Zen 3 it seems, but one agesa 2 rule them all might explain that


----------



## Farih

Audioboxer said:


> Rtts can play a role in not posting cleanly in my experience but I'm not familiar enough with SR to know what to recommend to you. Try playing around with them though.


Yh, playing around with resistances atm.

Btw, if you increase resistances should you then also up the voltage's?


----------



## ManniX-ITA

Taraquin said:


> Zen+ and Zen 2 had fever issues than Zen 3 it seems, but one agesa 2 rule them all might explain that


Or maybe it's 5 people doing the job of 300, I don't know, it's common these days


----------



## Audioboxer

Farih said:


> Yh, playing around with resistances atm.
> 
> Btw, if you increase resistances should you then also up the voltage's?


Not necessarily. I know being able to reduce ProcODT and not having powering issues can sometimes mean reducing VDIMM, but at the voltages you will be running a bit more than needed is unlikely to cause instability.


----------



## ManniX-ITA

Farih said:


> Anything i can do so my PC can boot/restart normally?


Did you try with tRDWR/tWRRD in Auto?

I would also check tRP = tWR/2 and tWR = tRP*2


----------



## gameinn

@Audioboxer What do you think of this teamgroup kit vs the g. skill offerings? This review has some oc all at 1.5v:









Team Group T-Force XTREEM ARGB 32GB Review - Overclockers


Team Group's new 2 x 16 GB dual-rank T-Force XTREEM ARGB is rated for 3600 MHz at shockingly low primary timings of CL14-15-15.




www.overclockers.com


----------



## Farih

Audioboxer said:


> Not necessarily. I know being able to reduce ProcODT and not having powering issues can sometimes mean reducing VDIMM, but at the voltages you will be running a bit more than needed is unlikely to cause instability.


Ok thanks.



ManniX-ITA said:


> Did you try with tRDWR/tWRRD in Auto?
> 
> I would also check tRP = tWR/2 and tWR = tRP*2


Not tryed auto settings.

If tRP = tWR/2 and tWR = tRP*2 then seems i never had the "right" setting.
tRP = 16 and tWR is 12.
So my tRP should be 24 if tWR is 12 or tWR should be 8 if tRP is 16?

Its booting most of the time now... 7 out of 10 times more or less.
Stable in Memtest5, not done y-cruncher yet.

Thought with going 4 sticks instead of 2 i just maybe had to apply some voltage... i was wrong


----------



## ManniX-ITA

Farih said:


> So my tRP should be 24 if tWR is 12 or tWR should be 8 if tRP is 16?


No if tWR is 16 then tRP should be 8.
Try some, it depends on the DIMM and on the other settings what's right.
Wrong tRP, being too high or too low, can have weird consequences.

I have seen once also VDDP needing to be 1000mV for 4 sticks but in general it's not needed.


----------



## Veii

Audioboxer said:


> That's why I was excited to step up to 59xx in the first place. Why AMD is hurting that perception at the end of the generation is just dumb. There is no need to. I refuse to even believe there is some sort of RMA pandemic with 59xx chips. Most people RMAing in this topic probably just want better silicon 😜
> 
> Though there maybe are some suggestions B2 chips are a bit of a mixed bag. That's on whatever AMD has changed with the manufacturing process if you ask me. Not our fault.


They changed their approach for whatever reason and wanted to downgrade voltage strain
Likely because what AMD thought, vs what fabs push out (by silicon capability) differed in behavior. To secure their statements and not get sued

There are many things that are brickling, but it's Team Vanguard's own fault that it is how it is
The Vendors are in the best position possible for us, if AMD wouldn't mess with them and the security
The problem, everyone "only" can blame AMD - the whole chain of what is called "it's AMD"
And social media "faces" that where picked, one of them being Mr Hallock ~ is problematic to talk with
Not because he is problematic. I've been following him for quite some time (his character is fun to communicate with, but because Team Vanguard under AMDs blessing ~ pushed him and shaped him to be that way.

It's bothersome
We "the not semiconductors" , see and experience many of the issues
But the problem ~ who communicates with us at all ?
People who kind of communicate with AMD such as Yuri and couple more "friends" // still are treated like rebels and not even bothered to listen to

If we can not rely on talking with Mr Hallock, and can not rely on the information shared towards AMD even making it to AMD
Who should even fix the platform.
Vendors can't.
Vendors can as my friends "try" and talk with AMD, "try and let them know" about something.
But based on the hierarchy AMD themselves build up, nothing moves forward.
At absolute best, we can hope that in 1-2 months Vendors get permission to make a change, and then hope our communication with people who aren't always "ok" with English, accept the issue and we have it resolved

The reality of it is tho,
It won't be, not till 2-3 big AGESA Packages have passed, which is an ETA of 2-5 months, before "one" issue get's fixed
This is problematic but who can you even turn towards ?
Vendors do their absolute best already in translating user-experience issues towards AMD. But AMD has to be selfish on 6 fronts
Social Media Department, Vendor Bios Department, Bug hunting department, Discord cult Vanguard Team department for media outlet response, Radeon Hardware & Radeon Driver team, Fab communication department, 3rd party semiconductor department (7 already)

Can a company even handle us the actual users of their product ?
It's already bothersome even communicating with AMD , as consumer or as Vendor , not to speak even as ODM.
ODMs and Vendors have taken over the position of communicating with XOC guys, but when they find something (which is part of their work)
Nobody can talk with them and Vendors can't talk with AMD.

Soo who can we even blame here that nothing moves forward.
AMD is to blame for themself with the chosen communication model
Buidling a cult in discord was already questionable, but so be it
On Intels side at least some direct talk is done with the Overclockers and XOCers // on AMD , zero ~ issue by their own communication model

Of course nothing moves forward , they are just tonedef by design 


Audioboxer said:


> Though there maybe are some suggestions B2 chips are a bit of a mixed bag. That's on whatever AMD has changed with the manufacturing process if you ask me. Not our fault.


B2 are on a more mature powersaving node.
But still have equal voltage scaling characteristics , nearly identical. Just scale further down with lower strain
They could be equally called XT lineup, but we know how much they already struggle to differentiate a product lineup ~ heh (or maybe XL, for "Xtreme Lowpower" ~ maybe 5800XL was a good idea)

Soo hence they "tried" to downscale maximum used voltage and changed V/F curve
Some of the wood samples where falling bellow the accepted threshhold and became "defective" crashing on stock

I mean, my average sample was the same
Completely unstable on stock ~ now it's better
AMD has to fix their communication methodic and Team Vanguard rethink their position.
Staying in hidden, going against own members & pushing shadow updates with shady methods ~ is anarchistic behavior
Own fault if you get disliked, well deserved
But it shouldn't be that way ~ and it makes me sad from somebody who has been working with Zen since at least 2017
Yet still, 5 years later (AMD) got more and more greedy and distanced from the community. At least their/your bellowed rival, greedy or not ~ tries to utilize the free research they gather from the OC scene.
AMD is too fine, to even bother writing a guidance for their OC scene ~ but shows the worried side in "stupid consumers" messing up their CPU.
Marketing, but questionable to say the least

Also sadly, their products are complex and it's fun to dig and learn everyday something new
Although nobody cares about us "own working rebels" & Vendor's hands are full bothering with the "normal consumers" who have basic stability issues


Farih said:


> Thought with going 4 sticks instead of 2 i just maybe had to apply some voltage... i was wrong


You should see 4 dimms as dual rank behavior - nearly identical to dual rank, with little exceptions
CAD_BUS presets that work well are
60-20-40-20
60-20-20-24
40-20-40-20
40-20-30-24
24-20-24-24
3rd value bellow 30 causes training issues for Vermeer, but has to be when procODT is high
24-20-24-24 or 24-20-20-24 only works with wasted high procODT
But neither procODT nor cLDO_VDDP have to be pushed for FCLK and not for memory timings stability or post stability
^ doing so degrades signal integrity too much. Using CAD_BUS is the right way


----------



## Audioboxer

gameinn said:


> @Audioboxer What do you think of this teamgroup kit vs the g. skill offerings? This review has some oc all at 1.5v:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Team Group T-Force XTREEM ARGB 32GB Review - Overclockers
> 
> 
> Team Group's new 2 x 16 GB dual-rank T-Force XTREEM ARGB is rated for 3600 MHz at shockingly low primary timings of CL14-15-15.
> 
> 
> 
> 
> www.overclockers.com


That's a good bin, yes.

G.SKILL do a 3600 14-14-14-14 at 1.45v so price compare it to that.


----------



## Piers

Audioboxer said:


> Waiting till the end of the generation to really put the boot in and give the middle finger to the community that has spent years spending top dollar on your hardware and promoting you everywhere is certainly a bold move from the marketing department.


What's AMD done recently? I'm intrigued.


----------



## Veii

Farih said:


> Yh, playing around with resistances atm.
> 
> Btw, if you increase resistances should you then also up the voltage's?


Termination impedances
higher value (ohm) , lower voltage (dimm)

resistance output,still impedance on it's core
and impedance on it's function = a multiplier of voltage

RTTs stronger impedance, lower waterflow hose (tigher waterflow throughput, more power ~ amperage)
CKE clock signal bounces faster up down in the little gate, and ends up stronger and faster ~ but also noisier

Termination impedance for procODT , kind of the same
Impedance as a multiplier , but also multiplier of noise

Multiplier of cLDO_VDDP voltage, multiplier of memory to voltage , in general higher amperage to the dimms

CAD_BUS are purely impedances ~ soo again the same thing
ClkDrvStr , multiplier of voltage = amperage to dimms
stronger ClkDrvStr will lower minimum procODT required
procODT required depends on IOD and VDD18 , so also lower VDDG voltages overall

Low procODT only works with good signal integrity and such only is because of low voltages
High voltages and low procODT causes issues, but all ends up as a signal integrity thing


----------



## byDenoso

Veii said:


> Low procODT only works with good signal integrity and such only is because of low voltages
> High voltages and low procODT causes issues, but all ends up as a signal integrity thing


My Matisse doesn work well with less than 1070mv on vddg iod (Random Reboots)
Because of that i had to increase SOC to 1,14v and procODT do 36.9ohm.
but that affected my previously stable RAM OC (Lot of error 1).


----------



## Audioboxer

Piers said:


> What's AMD done recently? I'm intrigued.


Changing how boosting works and also limiting voltage if you go over 140 EDC in the bios leading to light thread workloads being negatively impacted. I've had EDC scale as far as 220 and produce good results in CB23 with MT.

In other news I got my 3080 in today as part of the step up queue and after hours of getting the block on it and trying to get it installed vertically it's time to... go horitzontal.

Believe it or not it was my RAM waterblock giving me issues vertically due to the height of the waterblock on a 3080. Squeezing it in left the card slightly tilted downward at one end putting pressure on the vertical mount and just looking untidy. OCD alliance assemble.

So, we're going horizontal and I'll have to redo a lot of my runs.

The EK waterblock looks quite nice vertically but tough, horizontal it is. I got a silver nickel backplate which is quite smart, so that's cool enough.

I guess this also means no more risks with riser cables, though the more expensive PCIe 4.0 riser cable I bought seems solid.


----------



## Veii

byDenoso said:


> My Matisse doesn work well with less than 1070mv on vddg iod (Random Reboots)
> Because of that i had to increase SOC to 1,14v and procODT do 36.9ohm.
> but that affected my previously stable RAM OC (Lot of error 1).


Matisse procODT should be 28.2, it's requirements are lower than Vermeer by design
And SOC beyond 1.15 had negative effects
1900FCLK run at 1.075v SOC and around 950mV VDDG
Have to check the zen ram OC sheet. I remember we run very low voltages and only then 28.2ohm procODT run
Higher procODT requires high voltages

If you've based ram stability on procODT or clDO_VDDP, then that's sadly the design fault
it should not be used for dimm powering


----------



## Blameless

Have been conflicted over which dual-rank Samsung B-die DIMMs to get (I already have four single-rank sticks of Patriot 4400 stuff that are pretty good, but aren't suitable for my two-slot-only ITX board). Since giant heatspreaders and RGB annoy the snot out of me, I was leaning toward the Team T-Create stuff, but in the end I just decided to buy a big stack of OEM Samsung B-die from Amazon and bin it myself. Unless they all clock quite well, I'll probably return the worst (honestly stating they are no longer needed), and find some use for the best ones. Even if the best pair aren't as good a the pre-binned stuff I was considering, I'll have more fun this way and feel like I was ripped-off less.


----------



## Veii

@Blameless if you still haven't pressed the "buy" button
Check

TeamGroup T-Create Expert OC10L DIMM Kit 32GB, DDR4-3600, CL14-15-15-35 ~ 1.45v
TTCED432G3600HC14CDC01
&
TeamGroup T-Create Expert OC10L DIMM Kit 32GB, DDR4-3200, CL14-14-14-34 ~ 1.35v
TTCED432G3200HC14BDC01

They are on a 10layer PCB , a new series 
16gb dimms are a bit better, but the 32gb ones should be ok too
Low profile, potentially A/B3 ~ but i think that's a custom A/B2 // no PCB change between freq bins
3600 is the highest bin too, aren't that harsh binned just low voltage or higher voltage bin







Patriot Vipers, got 4000 C16-16-16 kits out too, but nothing 32gb i think
Nothing "good"


----------



## Blameless

Veii said:


> @Blameless if you still haven't pressed the "buy" button
> Check
> 
> TeamGroup T-Create Expert OC10L DIMM Kit 32GB, DDR4-3600, CL14-15-15-35 ~ 1.45v
> TTCED432G3600HC14CDC01
> &
> TeamGroup T-Create Expert OC10L DIMM Kit 32GB, DDR4-3200, CL14-14-14-34 ~ 1.35v
> TTCED432G3200HC14BDC01
> 
> They are on a 10layer PCB , a new series
> 16gb dimms are a bit better, but the 32gb ones should be ok too
> Low profile, potentially A/B3 ~ but i think that's a custom A/B2 // no PCB change between freq bins
> View attachment 2552461
> 
> Patriot Vipers, got 4000 C16-16-16 kits out too, but nothing 32gb i think
> Nothing "good"


Those are precisely the kits I was looking at.

However, I couldn't resist the temptation of getting a bunch of Samsung M378A2K43BB1-CPB DIMMs for $59 each.


----------



## Veii

Blameless said:


> Those are precisely the kits I was looking at.
> 
> However, I couldn't resist the temptation of getting a bunch of Samsung M378A2K43BB1-CPB DIMMs for $59 each.


Hehe
Yea the PCB difference was that mattered
Good luck !


----------



## PJVol

Veii said:


> B2 are on a more mature powersaving node.
> But still have equal voltage scaling characteristics , nearly identical. Just scale further down with lower strain


Hi! How are things?
Even if we assume the new revision silicon is worse than the previous, what stops them from calibrating voltages at boot time just based on revision ID from CPU ID ? Both BTC (AC and DC) should handle most of the static and dynamic variance easily. Let alone voltage margins fused at ATE.
If the failure rate for B2 chips is noticeably higher(as some might think, reading this forum), it could mean defective batches somehow slipped through to the retail, hence the urgent agesa patches (my conspiracy view).


----------



## Piers

Audioboxer said:


> Changing how boosting works and also limiting voltage if you go over 140 EDC in the bios leading to light thread workloads being negatively impacted. I've had EDC scale as far as 220 and produce good results in CB23 with MT.


Ah, yes. I've seen people regretting going from 1.2.0.3b to (especially) 1.2.0.5 and newer due to the change to 1.425V (or something like that). It seems odd for AMD to change specification of the product without giving a reason, but not unexpected as AMD charges premium prices but lacks competency (not fanboy behaviour - I have a 5900X and find performance excellent). On the plus side, I was surprised to see AMD announcing that all 300 series motherboards - even A320 - will get full support for the Ryzen 5000 series, and providing the updated AGESA to motherboard vendors (leaving it up to them).


----------



## Audioboxer

Piers said:


> Ah, yes. I've seen people regretting going from 1.2.0.3b to (especially) 1.2.0.5 and newer due to the change to 1.425V (or something like that). It seems odd for AMD to change specification of the product without giving a reason, but not unexpected as AMD charges premium prices but lacks competency (not fanboy behaviour - I have a 5900X and find performance excellent). On the plus side, I was surprised to see AMD announcing that all 300 series motherboards - even A320 - will get full support for the Ryzen 5000 series, and providing the updated AGESA to motherboard vendors (leaving it up to them).


It's either a bug which they're just being lazy to fix or as Veii pointed out as part of their new outlook to totally lockdown the 3D cache chips they're desperately wanting to lock down existing chips as much as they can.

There would probably be some actual outrage if they removed the curve/turned off PBO on older chips, so next best thing is finding a way to semi-lockdown OCing. As pointed out many times now if it is something like this jokes on them that their neglected Ryzen Master software will completely skip the voltage cap and that is likely how most "non-tech obsessed" regular users change their PBO.

So all you end up doing is annoying geeky folk like us who do nearly everything in the BIOS. If it's a bug it's yet again careless AMD leading the way, allowing changes aimed at a yet unreleased CPU to screw up CPUs currently on the market.

Sadly, the fact that no motherboard provider has fixed the EDC voltage bug by now makes me think it's done on purpose by AMD.


----------



## Farih

Been trying to get 4 sticks of RAM be able to boot but had no luck 

Instead of adjusting settings i used when i was running 2 sticks i decided to just start over.

Now they boot on every restart or cold boot.
Sadly the timings are not that great 

What i noticed in "new" settings is that RttWr is on RZQ/3 while i normally always had it set to off.
What does this setting do? does it play any role in 2 vs 4 sticks of RAM?

Previous settings that bench stable but gave problems restarting/cold boot:









New settings that have no problems with restarts/cold boot:


----------



## mongoled

Farih said:


> Been trying to get 4 sticks of RAM be able to boot but had no luck
> 
> Instead of adjusting settings i used when i was running 2 sticks i decided to just start over.
> 
> Now they boot on every restart or cold boot.
> Sadly the timings are not that great
> 
> What i noticed in "new" settings is that RttWr is on RZQ/3 while i normally always had it set to off.
> What does this setting do? does it play any role in 2 vs 4 sticks of RAM?
> 
> Previous settings that bench stable but gave problems restarting/cold boot:
> View attachment 2552506
> 
> 
> New settings that have no problems with restarts/cold boot:
> View attachment 2552507


Im sure its been mentioned by others,

but you need to work out what the sticks do with GDM disabled.

Otherwise you will be going round and round in circles .....


----------



## mongoled

ManniX-ITA said:


> Maturity is not perfection
> We are not wishing for something unrealistic, just the average industry standard.
> I think it's the right time for moaning
> Have to decide where to spend a lot of money when I'm going DDR5... pardon me but I need to think thoroughly about it.
> Especially after this extremely disappointing RMA process with AMD.


No issue with moaning, issue is the incessant moaning by peeps in whatever thread they can lay their hands on, even when it makes them look completely emotion driven, immature and a little stupid they keep going

😂 😂



ManniX-ITA said:


> No I don't agree at all with this analysis.
> You do all this stuff *before *going public with your CEO boasting this tech on video.
> 
> _"too little, too late, Zen 4 and Raptorlake are already out"_
> Yes, if you are not ready don't announce it
> And maybe think twice before selling it
> 
> _If you think AMD releasing this product sooner means they are releasing it as a beta product, you are more than welcome to wait for the next generation of V-cache products that have overclocking/undervolting support._
> This is not the point.
> Of course we have the choice to not buy it
> And AMD is a private company, they can do whatever they want.
> Certainly doesn't need our approval.


Perfectly fine POV, we just dont agree





ManniX-ITA said:


> It's a matter of *confidence and strategy*
> Both for the investors and the consumers
> 
> I'm not an investor so I'm not concerned about how much money I can make with my stocks
> But it matters cause if the investors doesn't have confidence in what the execs are doing there'll be less money for the company
> Their strategy will change and they'll start keeping the company on a leash
> 
> As a consumer of course I'm worried about it if I intend to spend money for years on their products
> Wasted effort on a too early and not remunerative product is a problem for me as well
> Means the effort I was expecting they would put on my 5950X will be redirected on the, single, 3D product
> Which will probably not bring any money back to AMD which will have to cut the effort on supporting legacy and focus on the new ones, those that will make money
> Investors confidence goes down, mine as well
> Which means I'll stop recommending AMD to my friends or relatives, change of strategy
> 
> Today is all about NPS (and sales figures of course)
> 
> 
> 
> 
> 
> 
> 
> 
> 
> What is NPS? Ultimate Guide to Net Promoter Score in 2023
> 
> 
> What is NPS? ✓ Learn everything you need to know about Net Promoter Score, how to calculate NPS scores, and how it's used to measure customer experience.
> 
> 
> 
> 
> www.qualtrics.com
> 
> 
> 
> 
> 
> Converting an enthusiast into a detractor is a tragedy
> It's 100 times more difficult the opposite conversion
> The negative impact of a detractor is 10 times more than the positive impact of an enthusiast
> That's why all companies are so willing to spend money and effort into luring influencers in their orbits
> One powerful influencer can nullify thousands of detractors with a single tweet
> it's not _that irrelevant_ what is the general mood within the OC community...


I highly highly highly doubt the impact from overclockers is going to have any sort of effect on those who investing in stocks be it consumers/investors.

Any effect it may have will be far outweighed by the gains they will have in other areas.

Otherwise things would not be this way.

I dont wish to continue such conversations as there are far too many things that one needs to take into context and I am not in a position to pass the wealth of knowledge in my brain regards to "everything" that is needed to "understand" the bigger picture for two main reasons, #1 the time it would take to get this all written down and #2 two different people will have a different understanding of the same thing !

So all in all, its down to each person to make up their own minds.


----------



## mongoled

Blameless said:


> Those are precisely the kits I was looking at.
> 
> However, I couldn't resist the temptation of getting a bunch of Samsung M378A2K43BB1-CPB DIMMs for $59 each.


and scan.co.uk sells 1 dimm for £150+ 

😂😂


----------



## ManniX-ITA

mongoled said:


> I highly highly highly doubt the impact from overclockers is going to have any sort of effect on those who investing in stocks be it consumers/investors.


Sorry I probably wasn't clear in my moaning 

Doubt the investors even know what's the meaning of "overclock".
What is going to impact the strategy of investors is the bloody mess they made with the 3D PR stunt.
That's stuff they look at it and the poor handling and management of it will have consequences.

They also look at sales figures and NPS score.
There, on the NPS score, the community has a very sensible impact.
When the NPS score goes down, the board members they get calls.
And they summon execs asking for explanations.
In this case must have been embarrassing any attempt of justification...



mongoled said:


> I dont wish to continue such conversations as there are far too many things that one needs to take into context and I am not in a position to pass the wealth of knowledge in my brain regards to "everything" that is needed to "understand" the bigger picture for two main reasons, #1 the time it would take to get this all written down and #2 two different people will have a different understanding of the same thing !
> 
> So all in all, its down to each person to make up their own minds.


I agree.
I'm also speculating the 5800X3D will be a flop but maybe it's going to be awesome and a sales monster...
Doubt it but let's see what happens!


----------



## Imprezzion

I'm bored. What could I possibly improve on this setup timing wise so I have something to do and to test? I cannot do 3800Mhz or higher 1:1 due to WHEA issues so 3733 / 1866 is all I can get frequency wise.


----------



## Farih

Imprezzion said:


> I'm bored. What could I possibly improve on this setup timing wise so I have something to do and to test? I cannot do 3800Mhz or higher 1:1 due to WHEA issues so 3733 / 1866 is all I can get frequency wise.
> 
> View attachment 2552509


Both SCl's to 3
tWRWRSD and DD to 5
tRFC to 241, tRFC2 to 179, tRFC3 to 110

Not a pro, not actual advice ;-)

Edit:
Yay \o/ 5000th post!


----------



## byDenoso

Veii said:


> Matisse procODT should be 28.2, it's requirements are lower than Vermeer by design
> And SOC beyond 1.15 had negative effects
> 1900FCLK run at 1.075v SOC and around 950mV VDDG
> Have to check the zen ram OC sheet. I remember we run very low voltages and only then 28.2ohm procODT run
> Higher procODT requires high voltages
> 
> If you've based ram stability on procODT or clDO_VDDP, then that's sadly the design fault
> it should not be used for dimm powering


So i'll have to lower the voltages (Vddg, VDDP), or my R5 3600 is faulty and i have to run on these voltages?


----------



## byDenoso

Imprezzion said:


> I'm bored. What could I possibly improve on this setup timing wise so I have something to do and to test? I cannot do 3800Mhz or higher 1:1 due to WHEA issues so 3733 / 1866 is all I can get frequency wise.
> 
> View attachment 2552509



Raise cldo_Vddp to 900mv, Vddg IOD to 1100mv and VDDG CCD to 950
Raise SOC too, just for test, you can lower these voltages later.


----------



## Blameless

ManniX-ITA said:


> Means the effort I was expecting they would put on my 5950X will be redirected on the, single, 3D product


What effort? The 5950X already exists. There is no more effort that needs to go into supporting it that another product on the same platform could really detract from.



ManniX-ITA said:


> I'm also speculating the 5800X3D will be a flop but maybe it's going to be awesome and a sales monster...
> Doubt it but let's see what happens!


The only thing the 5800X3D needs to do to justify it's existence from AMD's perspective is win, or at least not decisively lose, in a very narrow niche of benchmarks vs. Alder Lake.

It's actual sales figures won't be relevant. No one actually needs to buy it for it to serve it's purpose (a marketing ploy, a paper tiger, a 'CPU in being') and selling everyone they make won't really change the company's financials. It's not going to be a high volume part. It's almost certainly binning rejects from the EPYC line up that were otherwise going to be tossed, placed in a very mature and relatively inexpensive AM4 package.

If it's good enough that AMD can pretend it matches the 12900K in gaming (they'll almost certainly have to omit comparisons to the 12900KS, but a loss to that part will be easier to spin), and they get some in situ reliability data from selling and servicing it, that's a win.


----------



## ManniX-ITA

Blameless said:


> What effort? The 5950X already exists. There is no more effort that needs to go into supporting it that another product on the same platform could really detract from.


The effort to finally deliver an AGESA without bugs or terrible ideas like VID capping.
I can only imagine what could have been done with the effort they had to spend in nerfing the 3D due to their very late find about the thermal constraints...



Blameless said:


> It's actual sales figures won't be relevant. No one actually needs to buy it for it to serve it's purpose (a marketing ploy, a paper tiger, a 'CPU in being') and selling everyone they make won't really change the company's financials. It's not going to be a high volume part. It's almost certainly binning rejects from the EPYC line up that were otherwise going to be tossed, placed in a very mature and relatively inexpensive AM4 package.


Not sure the sales figures will be not relevant if disastrous.
On top of the PR snafu, it could become an issue and tarnish the confidence on the management.
But I hope I'm wrong.
Done it properly, in the future, stacked caches could be really awesome.


----------



## Blameless

ManniX-ITA said:


> The effort to finally deliver an AGESA without bugs or terrible ideas like VID capping.
> I can only imagine what could have been done with the effort they had to spend in nerfing the 3D due to their very late find about the thermal constraints...


Most of the work that would apply to the 5800X3D will apply to every other Zen 3 based part and vice versa.

The VID capping is going to be completely unnoticed by the overwhelming majority of end users, and will probably significantly reduce return rates.

Enthusiasts always get the short end of the stick, because when it comes to the bottom line, we don't really matter.


----------



## PJVol

ManniX-ITA said:


> The effort to finally deliver an AGESA without bugs or terrible ideas like VID capping.
> I can only imagine what could have been done with the effort they had to spend in nerfing the 3D due to their very late find about the thermal constraints...


I'm still in the dark on what these bugs are, aside from well known since zen2 usb port dropout (which i honestly doubt will be fixed ever).
Even more perplexing, what makes people update bios every time the new agesa version released. IMHO, for the Vermeer/Cezanne CPU owners it makes sense to settle on whichever is AGESA 1.2.0.3c based - the most stable to date, and not wasting time on beta-testing firmware for the to-be-released products.


----------



## ManniX-ITA

PJVol said:


> I'm still in the dark on what these bugs are, aside from well known since zen2 usb port dropout (which i honestly doubt will be fixed ever).


I'm mainly referring about the VDDG bug and the VID cap over 140A.
But also the horrible performances of B0 stepping; mine after the "upgrade" was still performing better with 1.2.0.1 than 1.2.0.4/1.2.0.5.
There are good reasons to upgrade lately, especially now with all these security issues and bugs with Win11 (like the latest fTPM bug)



Blameless said:


> The VID capping is going to be completely unnoticed by the overwhelming majority of end users, and will probably significantly reduce return rates.
> 
> Enthusiasts always get the short end of the stick, because when it comes to the bottom line, we don't really matter.


You are probably right, they don't give a ****.
But I paid over 900 € for my 5950X.
Without a VID cap.
Not going to let them steal a slice of my pie without paying for it.


----------



## Taraquin

5800X3D seems like a proof of concept, like Radeon VII (terrible gaming card, superb compute/miningcard). 

If they allow for negative CO 5800X3D atleast has some more potential.


----------



## Blameless

ManniX-ITA said:


> But I paid over 900 € for my 5950X.
> Without a VID cap.
> Not going to let them steal a slice of my pie without paying for it.


I put all of my AM4 boards back to 1.2.0.3b/c firmware, which is where they will likely stay, unless the VID/EDC and VDDG caps disappear. Knowing whether the 5800X3D will work with this version will be a factor in if I get one or not.



Taraquin said:


> If they allow for negative CO 5800X3D atleast has some more potential.


4.5GHz is low enough that I a ~1.3v might be able to swing it for fixed all-core clocks.

I'm really curious as to how that would fare, as it's only about 4% lower than the clocks my 5800X typically sits at, while gaming.


----------



## PJVol

ManniX-ITA said:


> I'm mainly referring about the VDDG bug and the VID cap over 140A.


Yeah I see, and that's why i stand on not to upgrade to anything post-1.2.0.3c, aside from some "security" concerns, ftpm things, etc (shoved in users throats by MS, let's be honest).

I just watched the interview with R.Hallock (hot hw), the 5800 3d discussion part, where he clearly stated that the OC will be disabled for this chip, and explained the reasons behind it. Nowhere was it mentioned in relation to PBO/2, so considering its target application is mostly gaming, there are few reasons to be concerned i think.


----------



## Lobstar

I'm on 4006. How can I replicate this VID issue on my 3950x/C8H?


----------



## Taraquin

PJVol said:


> Yeah I see, and that's why i stand on not to upgrade to anything post-1.2.0.3c, aside from some "security" concerns, ftpm things, etc (shoved in users throats by MS, let's be honest).
> 
> I just watched the interview with R.Hallock (hot hw), the 5800 3d discussion part, where he clearly stated that the OC will be disabled for this chip, and explained the reasons behind it. Nowhere was it mentioned in relation to PBO/2, so considering its target application is mostly gaming, there are few reasons to be concerned i think.


Still a negative CO would be nice, it does not dmg chip in any way, but can guve a boost if 5%+ in certain scenarios.


----------



## Krisztias

Hello!

Is here somebody with 4x Flare X 3200C14 RAM? I would like to get it run 3600MHz. I have B450 chipset and 5800X. What Resistances ara you using?
Thanks in advance.


----------



## Imprezzion

Farih said:


> Both SCl's to 3
> tWRWRSD and DD to 5
> tRFC to 241, tRFC2 to 179, tRFC3 to 110
> 
> Not a pro, not actual advice ;-)
> 
> Edit:
> Yay \o/ 5000th post!


Doesn't even post. Just loops random post codes. 
SCL + tRFC only posts, tWRWR's don't.


----------



## Blameless

Imprezzion said:


> I'm bored. What could I possibly improve on this setup timing wise so I have something to do and to test? I cannot do 3800Mhz or higher 1:1 due to WHEA issues so 3733 / 1866 is all I can get frequency wise.
> 
> View attachment 2552509


tRAS and tRC should be able to be tightened.

tRDWR might take 8.


----------



## Veii

Taraquin said:


> If they allow for negative CO 5800X3D atleast has some more potential.


It does work 
As long as user do not mess it up by themself, with Win update, mc_update.dll OTA microcode update
or vendors hiddenly changed 1206C as 1206B release // then CO works
Oh , maybe it works on 1206C too ~ as it worked independent of the SMU lock. So did also ZenPTMonitor


PJVol said:


> Hi! How are things?
> Even if we assume the new revision silicon is worse than the previous, what stops them from calibrating voltages at boot time just based on revision ID from CPU ID ? Both BTC (AC and DC) should handle most of the static and dynamic variance easily. Let alone voltage margins fused at ATE.
> If the failure rate for B2 chips is noticeably higher(as some might think, reading this forum), it could mean defective batches somehow slipped through to the retail, hence the urgent agesa patches (my conspiracy view).


Funnily , busy
Finally actually. it's been getting booring.
I focus on too many little projects and now X3D is a major one i'd have to deliver

New revisions, B2 ~ wasn't directly worse
My experience saw a generally better bin on average, but also had worse lemons.
Soo while more of them can reach patin efficiency , there are a lot that barely hold Bronze.
The binning difference is bigger between good ones and really unlucky ones.

It was mostly the older samples that after the CO changes, started to be unstable on stock
But while 1204(A) was a redo, 1206 is another full redo ~ soo i hope they did it well this time, or just reset who knows

They split graphics CO with Core CO
And they split dual CCD CO,with single CCD CO ~ as separate fields
ASUS "by accident" provided a full database of target ID's for up to 64 cores (CO) ~ whatever that means
But they changed IDs and so 1206B on stock had enforced disable SMU ID , disabled some links while PBO was in-design
Target was X3D but vermeer is vermeer soo that was affected too
1204 was only buggy by the same reason.


PJVol said:


> what stops them from calibrating voltages at boot time just based on revision ID from CPU ID ?


They could, but what stops us from playing with the same tools they play 

I'm slightly unhappy about how microcodes are used as placeholders, and pushed into FW
ROM Microcodes are never really loaded, and most of the changes are pushed via PSP-FW or system PSP Firmware driver
Soo patches are injected later before boot. It only falls down to MC if there are no patches for X new CPU
Meaning on boot of a new thing, generally PSP-FW is reflashed, or microcode support is checked

AMD at any point could fuse away peak voltage limits ~ hardcode
It still can not push such change over AGESA, as it's read only and people will notice backdoor to gain write access
Also It can not patch out the first revision that is long time in spread and bunked on retailers shelf's
But considering how proud Mr Hallock was posing with their "it's locked locked" statement
I expect them to fab-patch it away on revision 2, unless they wake up from their bad dream.

X3D get's quite hot, that's true
But many of us run exotic cooling.
The ability to finetune undervolt things AMD might not consider as "needed" ~ like Navi
Or things that have to be pushed to hold higher FLCK ~ locking them , locking Vermeer designed units from Vermeer API
Is not a good tradeoff
We will see , i look forward , hopefully can get the first batch ~ loop awaits for it


Spoiler: New Toys


































^ used 120€ for mini streambox










Honestly was waiting for better APUs ,, but they disabled the APU unit on current non X releases
Renoir-X then is booring too, soo unsure if it will be two times X3D or some 5600/5700G for the mini PC


----------



## Audioboxer

Speaking of exotic cooling I finally got my loop back up and running yesterday with my 3080. First thing I noticed is better flow rate, likely because I removed the 120mm XR5 (could actually add this back now due to switching GPU to horiztonal) and one of my 360mm XR5s has been replaced with a 360mm XR7. Believe it or not the thick rad is less restrictive.

I changed to an XC7 pro which has about double the fins over the XC7. My CPU was idling in the 20s at points, which is super good, but I did notice some heavy spiking. Keeping an eye on it. Just used the preapplied Corsair paste. Not sure how good it is or if their weird paste apply design is all that good.

But the funny part of the story, after a leak test for a few hours on first boot I started y-cruncher and went away and left it. Getting some heat in the loop often helps with air bubbles. When I came back screen was black. Assumed it might be a crash. Rebooted, D6 bios error code!

Instant panic. D6 is what I got when my 2080Ti died. So first thought was have I killed this 3080 with a leak or something. Tried other cables, no go. Drained loop, took it out, opened it all back up. No signs of water on the card.

Put it back it without loop in action, PC booted. Relief. RMAs to Germany take about a week all in and while EVGA is great for warranties signs of water damage and RIP. 

What caused all of this? My new run. As in, the tubes. A little bit too much pressure on the run from the reservoir to the GPU was causing it to pop out from the PCIe slot ever so slightly. Just had to shorten the tube a little more. D6 seems to just be a fairly general no graphics card detected.

Long and the short, I hate watercooling 😂 If it's not time consuming bending hard pipe it's all the little things that can go wrong and many which then require draining of the loop to troubleshoot.

I'll take a picture of the run later to show what I mean. With me being horizontal again it's required a complete rework.



http://imgur.com/lCJhMy5


Timespy seems decent but I need to take a better look at OCing this now and finding what is stable. I'm already paranoid my 450w power draw isn't working as card is mostly staying around 400w max, but I believe it's due to running at 3440x1400, not 4K and most things I've ran so far just not needing more power at current clocks.

CPU above is just with default PBO values, hadn't changed them in Ryzen Master on boot. No idea if Time spy prefers ST boosting or uses MT.


----------



## Audioboxer

Pulling 400w is fine, seems one shouldn't worry about "must hit 450w on a 450w bios!".

Now, less spamming this topic with GPU stuff and back to memory










I noticed that if run tRFC 209 then the ns is 110ns exactly. We've done this song and dance previously, but @Veii just to confirm as per Anta advice to run multiples of 8 is this the _definitive_ advice for tRFC?


----------



## Taraquin

Audioboxer said:


> View attachment 2552603
> 
> 
> View attachment 2552604
> 
> 
> Pulling 400w is fine, seems one shouldn't worry about "must hit 450w on a 450w bios!".
> 
> Now, less spamming this topic with GPU stuff and back to memory
> 
> View attachment 2552605
> 
> 
> I noticed that if run tRFC 209 then the ns is 110ns exactly. We've done this song and dance previously, but @Veii just to confirm as per Anta advice to run multiples of 8 is this the _definitive_ advice for tRFC?


For 16gb sticks I think he saod divideable by 16  208 would be perfection then


----------



## Audioboxer

Taraquin said:


> For 16gb sticks I think he saod divideable by 16  208 would be perfection then


Yup, just wanting to reopen the debate and figure out is it performance that is the concern when that "rule" isn't adhered to. Only reason I'm asking again is going from 208 to 209 literally seems to drop my VDIMM requirement to 1.62v. Will even test 1.61v.

tRFC is that on the edge around 110ns that even a tiny change to the ns value can end up with +/- 0.01v very easily.

Not that I can't cool 1.63v, easy to do so. Just messing about with my SUPER DUPER 100% FINAL PROFILE FOR REAL THIS TIME final profile for my memory 😂


----------



## Imprezzion

Blameless said:


> tRAS and tRC should be able to be tightened.
> 
> tRDWR might take 8.


tRDWR 8 loops code 15 regardless of voltages and goes to BIOS safe mode. tRAS and tRC do wanna go down quite a bit still but it's pretty hard to test those imho. I have had it pass 800% TM5 and crash within 10 minutes of starting shadow of the tomb raider with too low tRFC.

I did some testing and some benching and I still want to run a higher frequency as 3733 is kinda gimping my bandwidth and is too high to run CAS 13 on with my DIMM's but with the FCLK hole at 1900 at this chip my only next choice that is possible to get WHEA free and POSTing reliably with quite extensive tweaking to RTT's, ProcODT, VDDG, VDDP and such is 1933 so 3866Mhz. This is nice but it does mean I cannot run certain subtimings as tight and will probably need a lot more vDIMM for straight 15's at low tRC / tRFC.

I got this to boot and run 1h of TM5 at least. No WHEA's either in HWInfo64 so far. 
tPHYRDL 26/26 so that's good, and it put down some seriously good bench numbers but I really really doubt this is going to be long-term TM5 stable lol. We'll see.


----------



## Audioboxer

I've never really noticed OCCT has a benchmark tool till now lol. What sort of figures do you guys get with this?


----------



## Teussi

Is there anything that doesn't look right? Something to tighten maybe? Vdimm 1,45 - could raise it up if needed to 1.5v.
Samsung B Dies


----------



## domdtxdissar

Not much left to tweak on this platform atm, so i'm just preparing for ddr5 on AM5 nowadays.
Copper heatsinks for memory and a new TechN block ready for action later this year 









Have also been upgrading my waterloop with a mo-ra3 420 and 2x6m tubing so i can put the radiator on a different floor..
"Standalone" unit consist of radiator + integrated PSU with one on/off switch and two DDC waterpumps on the inlet and outlets  Not so pretty to look at, but the temps are very good








Some more pictures can be seen here:


http://imgur.com/a/rlI8N18

The tubing is connected to the rest of my loop with leak-proof quick-connects so its easy to service/upgrade this setup at a later stange 

After this upgrade i had a spare Monsta Full Copper 400mm laying around which i plan to use for a separate loop for for sub ambient benchmarking with its own quick-connects.
Spring water is pretty much always ~2-5 degrees in northern Norway, even in the summertime and its abundant so i dont need to feel bad about "wasting" clean drinking water
When i want to bench something i will disconnect the mo-ra3 and connect the monsta rad instead, which will be left under running spring-water to cool down the rest of my loop 😇
Should work the same way as putting a rad inside a "ice water bucket", only that i control how cold springwater i use to avoid condensation inside the computer.
(main watercooling loop inside computer consist of dual d5 pumps, cpu+gpu block and a 70mm thick 360mm rad in push/pull)

Sorry for offtopic 🤣


----------



## Audioboxer

domdtxdissar said:


> Not much let to tweak on this platform atm, so i'm just preparing for ddr5 on AM5 nowadays.
> Copper heatsinks for memory and a new TechN block ready for action later this year
> View attachment 2552609
> 
> 
> Have also been upgrading my waterloop with a mo-ra3 420 and 2x6m tubing so i can put the radiator on a different floor..
> "Standalone" unit consist of radiator + integrated PSU with one on/off switch and two DDC waterpumps on the inlet and outlets  Not so pretty to look at, but the temps are very good
> View attachment 2552610
> 
> Some more pictures can be seen here:
> 
> 
> http://imgur.com/a/rlI8N18
> 
> The tubing is connected to the rest of my loop with leak-proof quick-connects so its easy to service/upgrade this setup at a later stange
> 
> After this upgrade i had a spare Monsta Full Copper 400mm laying around which i plan to use for a separate loop for for sub ambient benchmarking with its own quick-connects.
> Spring water is pretty much always ~2-5 degrees in northern Norway, even in the summertime and its abundant so i dont need to feel bad about "wasting" clean drinking water
> When i want to bench something i will disconnect the mo-ra3 and connect the monsta rad instead, which will be left under running spring-water to cool down the rest of my loop 😇
> Should work the same way as putting a rad inside a "ice water bucket", only that i control how cold springwater i use to avoid condensation inside the computer.
> (main watercooling loop inside computer consist of dual d5 pumps, cpu+gpu block and a 70mm thick 360mm rad in push/pull)
> 
> Sorry for offtopic 🤣


Lmao, that thing is ridiculous. I bet temps are amazing tho!


----------



## eighty20

Hi, I have been lurking around, learned a lot from you guys. I recently traded G.Skill 3600C18 Neo C die for Crucial Ballistix (white) 3600C16 Micron E. I have gotten them to 4133 pass some stress testing, got some number in bench marks. Then, I got another Crucial Ballistix 3600C16 ( black) which I think it's the same PCB, same Die, even same design just different color. And I thought why not try quad channel for performance. So.. it's way harder than I thought, I can't get them boot pass 3600. Atm, 2T C16-18-18-38 at 3600MHz , ProcODT 36.9, RTT 6/3/3, CAD 40 20 24 30 is setting I use for 4x8GB and it seems ok. Can you guys please give me some tips so I can get them boot and figure out the baseline so I can play around w?


Crucial Ballistix 3600MHz C16-18-18-38 1.35v ( White)

















Crucial Ballistix 3600MHz C16-18-18-38 1.35v ( Black) - I tested the black w the bios setting that been tested for the white version. Boot to windows, benchmark and stress test so far no error.









Edit: Added photo of the ram


----------



## Taraquin

eighty20 said:


> Hi, I have been lurking around, learned a lot from you guys. I recently traded G.Skill 3600C18 Neo C die for Crucial Ballistix (white) 3600C16 Micron E. I have gotten them to 4133 pass some stress testing, got some number in bench marks. Then, I got another Crucial Ballistix 3600C16 ( black) which I think it's the same PCB, same Die, even same design just different color. And I thought why not try quad channel for performance. So.. it's way harder than I thought, I can't get them boot pass 3600. Atm, 2T C16-18-18-38 at 3600MHz , ProcODT 36.9, RTT 6/3/3, CAD 40 20 24 30 is setting I use for 4x8GB and it seems ok. Can you guys please give me some tips so I can get them boot and figure out the baseline so I can play around w?
> 
> 
> Crucial Ballistix 3600MHz C16-18-18-38 1.35v ( White)
> View attachment 2552665
> 
> View attachment 2552666
> 
> 
> 
> Crucial Ballistix 3600MHz C16-18-18-38 1.35v ( Black) - I tested the black w the bios setting that been tested for the white version. Boot to windows, benchmark and stress test so far no error.
> View attachment 2552669


Set volt to 1.45v, try with same settings. If not try 16-19-19, rev E don't like low rcdrd, rp can go lower though.


----------



## eighty20

Taraquin said:


> Set volt to 1.45v, try with same settings. If not try 16-19-19, rev E don't like low rcdrd, rp can go lower though.


Ok. Thanks. How abt CAD preset, RTT setting?


----------



## domdtxdissar

Audioboxer said:


> View attachment 2552613
> 
> 
> I've never really noticed OCCT has a benchmark tool till now lol. What sort of figures do you guys get with this?





Audioboxer said:


> Lmao, that thing is ridiculous. I bet temps are amazing tho!


Getting around *70degrees* max temp at Cinebench r23 (31k score) @ *260w load* in normal ambient temp (ram sticks are 27 idle)
In OOCT i pretty much match your numbers exactly, after 62 hours uptime without closing other programs/hwinfo.
Everyday PBO CO settings


----------



## Audioboxer

domdtxdissar said:


> Getting around *70degrees* max temp at Cinebench r23 (31k score) @ *260w load* in normal ambient temp (ram sticks are 27 idle)
> In OOCT i pretty much match your numbers exactly, after 62 hours uptime without closing other programs/hwinfo.
> Everyday PBO CO settings
> View attachment 2552674


Damn, that's cool. I can still hit mid to high 70s under such loads, and that's with really cold ambient. I guess a monster rad/fan setup like that does have its benefits  (not to mention this is under like 80% fan load lmao)










Still a bit unsure if I have this CPU clamped down properly and/or if the thermal paste is crappy. Temps on idle remain great, but a fair bit of erratic spiking during use. Don't remember it being quite as jumpy as this with the XC7. IIRC good idle but erratic on load could be spots with poor paste coverage.

CCD1 hitting a 10 degree high over CCD2, but this is _probably_ normal.

Probably should have removed Corsair's thermal paste and used my own lol. This can wait, I'm not doing another drain/tear down right now. Had enough of it!

I'd say it's been worth replacing an XR5 radiator with an XR7. Temps marginally better I think, or at least, the same as with 4 rads. Water flow is quite a bit better now though. Probably the combination of removing the 120mm XR5 and replacing the 360mm XR5 with an XR7.

Got quite a few right angle bends on this new loop so if I can ever be bothered getting rid of one or two of them, might bump up flow a bit more. Sitting at 3.0l a minute. That's 180l an hour, which I think is a fairly reasonable figure.


----------



## Blameless

Imprezzion said:


> tRDWR 8 loops code 15 regardless of voltages and goes to BIOS safe mode. tRAS and tRC do wanna go down quite a bit still but it's pretty hard to test those imho. I have had it pass 800% TM5 and crash within 10 minutes of starting shadow of the tomb raider with too low tRFC.


Regardless of what tRAS + tRC settings you actually use, having tRAS less than tRC - tRP likely won't improve anything. It should also be easier to test than tRFC.

Personally, I like to make sure settings will pass y-cruncher HNT + a solid GPU load overnight, before starting TM5.



domdtxdissar said:


> Copper heatsinks for memory and a new TechN block ready for action later this year
> View attachment 2552609


I've been considering a set of those DIMM heatsinks, but they cost as much as most of my memory.


----------



## eighty20

I managed to boot to window @3800 but not stable


----------



## Bloax

You could try tCKE 9 instead of 1 at 1900 MCLK








as judging by this random screenshot I stole from someone, tCKE still exists on Cezanne


----------



## Taraquin

eighty20 said:


> Ok. Thanks. How abt CAD preset, RTT setting?


40 20 30 24 works best for me, 40 20 24 24 and 30 20 24 24 also seems to work well for many.


----------



## Imprezzion

Blameless said:


> Regardless of what tRAS + tRC settings you actually use, having tRAS less than tRC - tRP likely won't improve anything. It should also be easier to test than tRFC.
> 
> Personally, I like to make sure settings will pass y-cruncher HNT + a solid GPU load overnight, before starting TM5.


Yeah that's why I have it scaling as 15 tRP, 25 tRAS and thus 40 tRC right now. I put tRFC to 240 because I know I can run ~130ns at 1.550v just fine and it is a round multiple of 16 as I use 16GB sticks and somehow that seems to be the general calculation people use for tRFC. Multiples of stick size / rank size?
All in all it passed all 25 runs just fine and I even did another test with Anta777 Absolut for 1 hour which it also passed fine so it seems like in these initial shorter tests this is actually stable lol.


----------



## Bloax

Well you could always set tRFC2 to 178 and tRFC4 to 110, and see if that does anything 🤡


----------



## eighty20

@Bloax i haven't try tCKE=9 yet, what is it for?

@Taraquin so I manage to boot at 3933 after set everything to the minimum and ProcODT=40, RTT 7/3/7 . TM5 1usmusv3_25cycles show error 1 so i'm trying different CAD, 24 20 20 20 atm. Would VDDP 0.95 is too high? Also, which CAD bus timing should i use?


----------



## OCmember

Decided to test my IF again today with my gaming rig 5800X. For the longest time 1:1, 1900/3800, wasn't stable and would throw errors and WHEA error; I passed some "mild" testing, y-cruncher 2 cycles, and TM5 Extreme1 anta777. I'd like to push a little more with some other tests, I'll use some different testing with TM5 and run y-cruncher a little longer but what other testing would stress the IF & Memory? Occt medium data set AVX2? Any other configurations, or test apps?

Thanks

EDIT: Using Ryzen Calculators DRAM PCB revision A3/A2/B2 timing suggestions. This brings around 54ns memory latency with AIDA64 Extreme v660

EDIT2: CS:GO threw a WHEA error, and the latest OCCT test threw a WHEA error.


----------



## Audioboxer

New chipset drivers seem fine for me after some hours, don't seem to have negatively impacted memory or CPU.

Now if MSI would just hurry up and release the 1.2.0.6c for their Unify line. The whole line has been abandoned even though it's one of their most popular. 🤡


----------



## Bloax

eighty20 said:


> @Bloax i haven't try tCKE=9 yet, what is it for?


What exactly tCKE does keeps slipping from my mind, despite me seeing a pretty good explanation for it. 🤡

What does stick though, is that it's an important timing for memory signal alignment - and that it tends to follow a +2 per +100 MCLK trajectory, up to a point I haven't explored yet, as I never toyed with memory (controllers) that went beyond 4200 MT/s (2100 MCLK).









It's even the same value on LGA1700 as it is on AM4! (tCKE 9 at 1900 MCLK, 11 at 2000, 13 at 2100)

Wrong tCKE values tend to produce timeout errors (1usmus_v3 #1, #2, #12, #9 ??) and occasional crashes (#4) due to the signal being out of sync with the mechanism that reads the values of the signal, or something like that - I don't care _that_ much about the voodoo specifics.

You can avoid it by using various other mechanisms to offset the signal into the correct position (classic examples being a higher tFAW, or CAD setup times on AM4), but it's a little silly.


----------



## eighty20

@Bloax i tried it plus all the recommend CAD from @Taraquin and some from @Veii . Combine w procodt from 36.9 to 60ohm, rtt 7/3/1, 7/3/7, 7/2/1. So far the highest clock i can boot is 3933 C16181838, TM5 error 2 most the time, changed vDIMM from 1.45 to 1.5 doesn't work, VDDP 1V and vSOC 1.2 also don't work. I think I'm gonna lurk around to find someone has the similar setup and copy.

Both of the ram kit work great individually. 4133C17 boot smoothly. Meanwhile i have something to work on, appreciate any advice. So tWR=16, tRTP=8 is not stable for me, y-cruncher crash after 3 iteration, same w tRRDL=4. tRP=11 doesn't boot, 12 crash and 13 seem stable. My question is that which any of these timings scale w voltage?


----------



## Taraquin

eighty20 said:


> @Bloax i tried it plus all the recommend CAD from @Taraquin and some from @Veii . Combine w procodt from 36.9 to 60ohm, rtt 7/3/1, 7/3/7, 7/2/1. So far the highest clock i can boot is 3933 C16181838, TM5 error 2 most the time, changed vDIMM from 1.45 to 1.5 doesn't work, VDDP 1V and vSOC 1.2 also don't work. I think I'm gonna lurk around to find someone has the similar setup and copy.
> 
> Both of the ram kit work great individually. 4133C17 boot smoothly. Meanwhile i have something to work on, appreciate any advice. So tWR=16, tRTP=8 is not stable for me, y-cruncher crash after 3 iteration, same w tRRDL=4. tRP=11 doesn't boot, 12 crash and 13 seem stable. My question is that which any of these timings scale w voltage?
> View attachment 2552702


Cwl is terrible, set it to 16, wr 16, rtp 8, rdwr 10, cmddrvstr 20


----------



## Bloax

Minimum tRTP and tWR is a PCB-dependent thing (and if it isn't technically, then it may as well be in practice), not related to voltage.
As far as I know, late-DDR4 Micron chip voltage scaling is mostly in tCL/CWL and tRP.
A funny story I can tell about secondary (RRD/WTR) timing scaling, is this:







--->







With AGESA 1203b, I suddenly found my memory config to demand RRD 6/12 and WTR 6/12 instead of 4/6 + 4/12 ..
I thought that was that, so it was to be; but as it turned out later, by increasing "VDD18" or "CPU 1.8v" and cranking procODT down to 30, RRD 4/6 + WTR 4/12 worked fine again.
So the secondary timings scale (to some degree) with increased 1.8v + lower procODT 💪🤡

in fact this behaviour even exists on Alder Lake, where I am currently running CPU AUX (1.8v) at 1.9v with - procODT being somewhere around 28 ohm, as the Patriot Viper Steel 4400 19-19-19 sticks demand it 🤡🤡🤡


---

If what you're saying is that you're having trouble running 4x8 at high speeds, whereas 2x8 on both kits works great - then that comes down to whether the sticks _like_ being in the daisy-bad slots.
These viper 4400 sticks for example, really like being in those slots - seemingly performing _better_ in them than in the daisy-good slots.
In contrast to that, the old Ripjaws 3200 14-14-14 sticks I currently have in my daisy-good slots, only go up to 3400 before exploding in the daisy-bad slots.


----------



## Blameless

I normally ignore tCKE as it seems to do very little unless memory power down is enabled (and I always disable it). Might still be used in training/POST, but I can't remember the last time I needed to increase it from 0 or 1 to anything higher.

It's part of the basic JEDEC spec going back to at least DDR2, so it should exist on every platform.



Imprezzion said:


> it is a round multiple of 16 as I use 16GB sticks and somehow that seems to be the general calculation people use for tRFC. Multiples of stick size / rank size?


I've heard plausible arguments that the memory controller is rounding tRFC to multiples of 8/16, but it shouldn't have anything to do with stick/rank size...only IC density. Regardless, it's a convenience, as even if it's not rounded-off trying to test performance and stability of more granular settings is largely impractical.


----------



## eighty20

Taraquin said:


> Cwl is terrible, set it to 16, wr 16, rtp 8, rdwr 10, cmddrvstr 20


Oh so it's the other way around. I always thought lower CWL first then RDWR and WRRD. Is it better? I'm thinking to tighten tRP, rdwr and RFC again. 
Edit: I'll be damn, RCD boot at 17. Looks like the black version perform better.










@Bloax that seems like my case. I'm up PLL to 1.81, what's VDD18? is it default at 2.5V?


----------



## Blameless

New OEM B-die is here. All of them are week 27-50 of 2016. Standard 8-layer B1 PCB.

About to start testing them on a pretty good 3900X sample in a low-end board. If any can do 3733 CL14 on that setup, I'll test those in my ASRock ITX + 5800X setup.


----------



## eighty20

So i managed to get tCL 15, tRP 12, Rcd 18 ( crash at 17). Strangely enough, there's not much gaining, latency was a bit faster ~52. TM5 puking tons of error even Vdimm at 1.55V. I think this crucial ballistix black version can set timing lower than the white version but performance overall is the same or a bit less.


----------



## SaarN

Is it normal to get better latency with static OC instead of any of the boosting algorithms?
With PBO on my R3600 would sit at around 1.4v~ idle instead of 1.265v of a static overclock, so it runs hotter, I get same read and write performance, but with PBO my latency increases by 1.2ns~.
Using Asus' motherboard defined parameters and not by actually typing the limits myself.
PBO:








Static:










Anything worth changing, by the way? Timings-wise, I mean.
VDimm is 1.47v, if I'm not mistaken, to prevent the sticks from getting any hotter as they currently reach 48c during stress testing.


----------



## Taraquin

eighty20 said:


> So i managed to get tCL 15, tRP 12, Rcd 18 ( crash at 17). Strangely enough, there's not much gaining, latency was a bit faster ~52. TM5 puking tons of error even Vdimm at 1.55V. I think this crucial ballistix black version can set timing lower than the white version but performance overall is the same or a bit less.
> 
> View attachment 2552723


Try 16, 8, 18, 16, ras 42, rc 60, rfc 600, cwl 16, see if that makes errors go away? If it works try rdwr 10, 9 or 8.


----------



## Imprezzion

That's kinda interesting lol. My last profile passed 2h TM5 fine, also y-cruncher a hour or 2 fine without WHEA's so it should be sort of stable. 

I played world of tanks and division 2 all evening, totally fine, great performance as well. Then just now idle when watching some YouTube it just randomly BSOD (technically it's a GSOD now) with PFN_LIST_CORRUPT. Haven't had that one before lol. 

Now I gotta find out what caused that one again..


----------



## SneakySloth

SaarN said:


> Is it normal to get better latency with static OC instead of any of the boosting algorithms?
> With PBO on my R3600 would sit at around 1.4v~ idle instead of 1.265v of a static overclock, so it runs hotter, I get same read and write performance, but with PBO my latency increases by 1.2ns~.
> Using Asus' motherboard defined parameters and not by actually typing the limits myself.
> PBO:
> View attachment 2552721
> 
> Static:
> 
> View attachment 2552722
> 
> 
> Anything worth changing, by the way? Timings-wise, I mean.
> VDimm is 1.47v, if I'm not mistaken, to prevent the sticks from getting any hotter as they currently reach 48c during stress testing.


This is expected. A static OC always gives more consistent/better results in AIDA's tests. As for the timings, I run timings that are almost identical to these. You can always work to reduce your primaries and trfc but that usually requires more voltage and after a certain point there isn't much tangible benefit.


----------



## eighty20

Taraquin said:


> Try 16, 8, 18, 16, ras 42, rc 60, rfc 600, cwl 16, see if that makes errors go away? If it works try rdwr 10, 9 or 8.


Still have way too many error instantly + 1 bluescreen from 1.55 to 1.6V. I don't dare to go further.


----------



## SaarN

SneakySloth said:


> This is expected. A static OC always gives more consistent/better results in AIDA's tests. As for the timings, I run timings that are almost identical to these. You can always work to reduce your primaries and trfc but that usually requires more voltage and after a certain point there isn't much tangible benefit.


I'm thinking of going down a step to lower the FCLK strain, because my imc is just 'barely there'.
It would give me an interconnect error here and there during stress tests, not always, but it happens unless I get those voltages just right.
Made a rough draft, passed MemTest86 once, and it ran fairly close to my regular timings while being 2 degrees cooler. If it ends up being more stable, then I'll take it for now, until the fan I ordered arrives and I'll be able to push the sticks further.
In case you've tried going down a step yourself and since you're running a simliar build, got any tips I oculd use? I only eyeballed my current settings and I've used some of the 'voltage headroom' by taking down the 'big ones' and around 20~ in TRFC. Not sure how much there's left out of those 1.48v


----------



## eighty20

Guys, can I ask some opinion about B-Die? So i return both E Die, now i have the option to get one of these 

TEAMGROUP T-Force Xtreem ARGB 3600MHz CL14 16GB Kit (2x8GB) PC4-28800 Dual Channel DDR4 DRAM Desktop Gaming Memory Ram (Blue) - TF10D416G3600HC14CDC01 
Patriot Viper Steel DDR4 16GB (2 x 8GB) 4000MHz Performance Memory Kit - PVS416G400C9K  
TEAMGROUP T-Force Xtreem DDR4 16GB (2x8GB) 4300MHz (PC4-34400) CL18 Desktop Memory Module ram - Black - TXKD416G4300HC18EDC01  

Which kit should i get, i have tested my FCLK is walled at 2300.


----------



## kairi_zeroblade

eighty20 said:


> Which kit should i get, i have tested my FCLK is walled at 2300.


without WHEA?? synchronous with your IF Clock?? if so, then that is wild!!

if that is the case, go with the 4300mhz CL18..else the Patriot Vipers are good, I have 1 kit running 4200 CL16 on my son's 5600G rig


----------



## eighty20

kairi_zeroblade said:


> without WHEA?? synchronous with your IF Clock?? if so, then that is wild!!
> 
> if that is the case, go with the 4300mhz CL18..else the Patriot Vipers are good, I have 1 kit running 4200 CL16 on my son's 5600G rig


I followed this guide then did an hour y-cruncher test all and prime large FFT for an hour, don't have the ram rn so i forgot which clock it was at, i recalled testing two clock right before 2300 at 1.25 and 1.27 vSOC so i think it's stable. I just need to figure the safe voltage for daily use for now. 
Yeah i think will buy the teamgroup 4300C18, seeing them have some good review. I also have another option which is thermaltake tough ram 4400C19.


----------



## Mach3.2

Blameless said:


> New OEM B-die is here. All of them are week 27-50 of 2016. Standard 8-layer B1 PCB.
> 
> About to start testing them on a pretty good 3900X sample in a low-end board. If any can do 3733 CL14 on that setup, I'll test those in my ASRock ITX + 5800X setup.


How many sticks did you actually buy for your binning process?



Imprezzion said:


> That's kinda interesting lol. My last profile passed 2h TM5 fine, also y-cruncher a hour or 2 fine without WHEA's so it should be sort of stable.
> 
> I played world of tanks and division 2 all evening, totally fine, great performance as well. Then just now idle when watching some YouTube it just randomly BSOD (technically it's a GSOD now) with PFN_LIST_CORRUPT. Haven't had that one before lol.
> 
> Now I gotta find out what caused that one again..


Totally anecdotal, but PFN_LIST_CORRUPT = unstable RAM timings on my setup, basically RAM related. But you also passed 2h of TM5....

Could it be the beta windows that you're running?


----------



## Blameless

Mach3.2 said:


> How many sticks did you actually buy for your binning process?


Only eight. Didn't want to get too carried away.

Unfortunately, only one of the batch seems decent. Half of them are pretty much junk...completely incapable of anything below CL14 at anything above stock clocks (and stock is 2133MT/s on the CPB), need 16-18-18 and loose subs to hold 3200+, and don't scale well with voltage. The best four (which all do at least 3600) I will probably find a use for, but without another one that matches the top stick, it's not going in my main system.

Could buy more, but it's a bit too much of a crapshoot. Not terribly surprising really. I knew they were going to be all over the place, but I did hope that more of them would make it far enough to be really interesting.


----------



## Taraquin

eighty20 said:


> Still have way too many error instantly + 1 bluescreen from 1.55 to 1.6V. I don't dare to go further.


Try what I said but raise rcdrd to 20.


----------



## eighty20

Taraquin said:


> Try what I said but raise rcdrd to 20.


Before i returned the ram, i tried c16 20 20 40, 22 22 42. Also let others on auto. Still puke errors instantly. Anyway, waiting for my B-die now  Ty.


----------



## Taraquin

eighty20 said:


> Before i returned the ram, i tried c16 20 20 40, 22 22 42. Also let others on auto. Still puke errors instantly. Anyway, waiting for my B-die now  Ty.


B-die is a different level  Hope you went for 2 sticks, not 4.


----------



## Imprezzion

Mach3.2 said:


> How many sticks did you actually buy for your binning process?
> 
> 
> Totally anecdotal, but PFN_LIST_CORRUPT = unstable RAM timings on my setup, basically RAM related. But you also passed 2h of TM5....
> 
> Could it be the beta windows that you're running?


I think pushing my tRAS 25, tRC 40 and tRFC 240 at 1.550v 3866 is a tad too much. It has tested fully 15h stable at 30 45 270 before but I decided to test this and it was promising but maybe a bit too much of the goodness. Besides, there was barely, if any, performance gain. Bandwidth identical and maybe 0.1-0.2 ns better (53.6 vs 53.8 average 10 runs) but we all know how inconsistent AIDA is so..

Question wasn't for me but still, I personally had 3 Trident-Z 3600C16 kits for binning as I knew I had to build 3 systems anyway (2 for buddies) and I kept the best kit myself lol. The other ones did almost the same. The only difference was that my kit needed consistently 0.05v less for the same clocks and timings then the other 2 but all of them would do 3866C15 AMD and 4400C17 Intel just fine. Only mine did it at 1.55v while the other 2 needed 1.60v ish. One of the kits is now running on a Z490 10900KF at 4533 17-18-18-35-320-2T at 1.58v and it has for the past year and a half ish. Been solid ever since. The other kit is just at 16-16-16 at 3800 on a X570 5800X at 1.50v and it also has been solid. 

I used to run mine on a 10900K at 4400 17-17-17 1.52v or if cold enough 4400 15-17-17 at 1.61v and it's been fine.


----------



## mongoled

Just a quick offtopic.

Its been cold in Cyprus for the last few weeks.

After changing case and some loop components I have some nice improvements in CB23 scores for my trusty 5600x.

BIOS is using agesa 1.1.9.0, have stopped a long time ago updating the BIOS to new versions as ive seen no reason to.

Before highest score achievable was around 122xx, now its knocking on the 124xx door (hwinfo64 screenshot is from a regular run)


----------



## Taraquin

mongoled said:


> Just a quick offtopic.
> 
> Its been cold in Cyprus for the last few weeks.
> 
> After changing case and some loop components I have some nice improvements in CB23 scores for my trusty 5600x.
> 
> BIOS is using agesa 1.1.9.0, have stopped a long time ago updating the BIOS to new versions as ive seen no reason to.
> 
> Before highest score achievable was around 122xx, now its knocking on the 124xx door (hwinfo64 screenshot is from a regular run)
> 
> 
> 
> View attachment 2552777
> View attachment 2552778


You should try agesa 1.2.0.3b/c, for me that made 1900+ fclk possible  Maybe you can do 2000 fclk+ whea19 free like me and get perf scaling? Unify X is 2 dimm? That makes it easier.

My best using pbo+co is 12050  But board won't run more than [email protected]
4.675-4.7 allcore.

My 12400F gets [email protected]


----------



## PJVol

SaarN said:


> Is it normal to get better latency with static OC instead of any of the boosting algorithms?


no, not normal because boosting on 3xxx cpus was travailing in birth. Vermeer showed exactly the opposite.



mongoled said:


> Before highest score achievable was around 122xx, now its knocking on the 124xx door (hwinfo64 screenshot is from a regular run)


There's a big chance to kick that door down by lowering EDC to 100-110A.


----------



## Veii

Blameless said:


> in fact this behaviour even exists on Alder Lake, where I am currently running CPU AUX (1.8v) at 1.9v with - procODT being somewhere around 28 ohm, as the Patriot Viper Steel 4400 19-19-19 sticks demand it 🤡🤡🤡


Fascinating , ty 
Do you go down to 20ohm proc, or near 22 ?


Bloax said:


> I thought that was that, so it was to be; but as it turned out later, by increasing "VDD18" or "CPU 1.8v" and cranking procODT down to 30, RRD 4/6 + WTR 4/12 worked fine again.
> So the secondary timings scale (to some degree) with increased 1.8v + lower procODT 💪🤡


2nd one should be just better signal integrity (as low procODT requires to move away from it powering your dimms), but good to know
VDD18/VTT_NonMem ~ usually was a CPU related thing, potentially memory controller but rarely the dimms
I still wonder what it exactly controls , for it's snowballing effect to reach board topology and so influence RTTs too 

Advice from me,
VDD18 at 2.13v is the highest likely even dangerous peak a user should use for XOC.
It doesn't die from it , but beyond 2.08 you start to have other funky issues and crashes
(your main voltages then being too high, this includes CAD_BUS & procODt)
^ 2.03 and lower is fine, 2.08v resolves 2133FCLK throttle but i try to lower it
Another one,
cLDO_VDDP at 1.1v [2400-2500+ MCLK] not only messes with the IMC, so also procODT ~ but directly with the dimms
They get overpowered and require ClkDrvStr drop to 20.
It can be a visible indicator if somebody relies on procODT or cLDO_VDDP for dimm powering, when they are fine at 20 or 24 ClkDrvStr + low procODT
(it's either high procODT or high ClkDrvStr, for dimms powering ~ yet procODT shouldn't be used for such)



Blameless said:


> I've heard plausible arguments that the memory controller is rounding tRFC to multiples of 8/16, but it shouldn't have anything to do with stick/rank size...only IC density. Regardless, it's a convenience, as even if it's not rounded-off trying to test performance and stability of more granular settings is largely impractical.


I know anta shared it, but i've been through it and it makes no direct sense
(math doesn't add up, soo moved away from 8s as multiple to different more specific values)
The other side ,
tRFC postponing or pausing and postponing, is not a feature AMDs IMC supports ~ unlike intel
These rulesets can not work here (for now)
Either tRFC is enough and recharges in time, it's too long and has to elapse fully, or is too short and get repeated "at best" but decision for such is taken in realtime
tRFC by itself, like tRC will keep looping and repeating as Autorefresh delay, independent if timings fall on curve or do not.
Such thing as (inserting delay and shifting) does not function on AMD. I couldn't find anything about this topic on any Vendor design or Engineers Document. It's just not a thing, but tRFC2 and 4 is a thing up to preprogrammed tSTAG state (on post)
* GDM being one of theses features that changes how/when & if tRFC2/4 state plays a role or not [in realtime] ~ soo changes if and how temperature aware it is (which it has options to be aware, but can not be on dimms without a temp sensor) ~ logically

Soo with other shorter words,
tRFC continues to matter if you are "on curve" or not
If you are not and both are just long ~ it doesn't matter. You only limit maximum potential bandwidth which probably can not be utilized with high timings = result is minimal or zero improvement
If timings are low, waiting on tRFC results in a bottleneck
But if tRFC is too low, it can (in the best case) be looped and everything halted. Then you notice an latency increase

My advice would remain the project i still hold up functional
Drop in dividers of tRC,
on 48 being 24,12,6,3
on 16-16-16-32-48, being 32-16-8
~ and so on
It not always is value 32, for 8/16/32 tCK postpones
^ but such is irrelevant for us on AMD for now. Most bioses unlike ASUS C8Extreme








Miss these timings.
No tMOD or tXS change - no tRFC2/4 importance , yet as it's still used for math, it's good to keep it as correct as you think it can be

Drop tRFC to the extend you can afford, and bellow your multiples of 8 value - doublecheck if it does anything at all
So be it 0.2ns decrease in latency or slight bandwidth increase if it's a bottleneck
If you drop it too low, you will notice a bigger spike in latency (0.6ns+) and a drop in effective bandwidth
========================================
Ah right,;
if tRFC is not on curve, but still results in increased bandwidth
That is because voltage was high enough before and tRP long enough to put the selected row in a charged state
Soo tRP didn't need to happen , tRAS (row access strobe) can happen and technically up to capacity tRFC wouldn't need to happen that early.
While tRFC happens, nothing can be done as it's work is to recharge everything. Everything will have to wait for it to finish and elapse
While tRC happens, commands from different banks & ranks can pass through,
but,
If you waste a lot of delay on tRC (it not being X value minus tRP = tRAS)
You will have to wait for tRC to elapse too. Yet if tRC is too low, it will elapse, be detected too short and repeated on it's full value again.
Dropping tRC is not a good idea in general

For value tRAS it's similar
for RowAccessStrobe to be "allowed" to happen, first data needs to be moved as reading is a destructive process and discharges cells (in the row)
Before such, cells have to be in charged state ~ which means, before tRAS,
tRP (which is what user sees as inserted delay!)
Sometimes, tRP doesn't have to equal tRCD state. Usually time timing on both is perfect ~ ICs discharging the same amount of time that they need to be read out fully
Yet again, sometimes on high voltage the buffer of recharge is let's say 10 instead of 14 tCK.
Soo if user doesn't notice this and doesn't drops tRP (adjusts the rest logically)
The inserted delay = tRP before tRAS will also happen and can not be time broken = Added Latency (AL) before read or before write

^ Meaning
Sometimes tRAS can be lower than typical tRCD read plus tRCD write (2x tRCD = tRAS)
This ruleset only guaranteed "equilibrium" where everything is easier to time and such alone results in better latency
But if you split them, then it's tRCD Read + tRTP = tRAS as minimum value
Yet you have to waste delay somewhere. Before there will be no time for tRP to happen. Soo have to hope on other things to recharge them in time
It's debatable "what do drop & what to increase" for best efficiency ~ even more when it matters on the usecase of memory

But this paragraph above about tRAS,
Should explain why tRC = Row Cycle Time (for each bank)
is ~ tRAS access strobe value + before that tRP for row recharge added delay
And the opposite, tRAS = tRC - tRP

tRAS can be a lot of things, it's just an row access strobe delay ~ like tCAS (tCL) is a column access strobe delay
What really matters on primaries is;
~ how much time is given to find correct row in registry catalogue of data (columns)
~ how much time the reader is given (tRCD) to read & transfer the readen data ~ move it
~ how much time is given the registry/database to boot up and start working on searching something (tRP)
~ and how much time for everything is taken (tRC) between
trigger search + do black copy of data + trigger locate & find correct row/collumn + move over // and repeate (tRC)

Soo Notes:
~ Pushing tRC lower than tRAS + tRP would only result in timed "finding" issues ~ as sometimes cells are not charged before RAS access or CAS access
~ Pushing tRAS lower than tRCD + tRP is questionable, as you have to recharge cells in time. It can be lower but it's an per-user unique thing that needs testing. It will result in errors and not repeat
(tRAS can not be repeat that way as it's actions are unique between read and between write, tRC can)
~ increasing tRC beyond tRAS+tRP time is wasteful and hides issues in tertiaries and so on
(soo since it hides voltage & recharge delays, logically it hides powering issues or too low tRRD & tWTR ~ between read between write, delays)

^ there will always be more specific rules, and all of them are correct @Subut
Such that you utilize Burst lengths between read & between writes , split them into chops (half) and do that way math with a bigger looked picture:
tRAS being tRCD_Write+tCWL+tBurst-chop+tWR
RCDWR is data transfer time, CWL is CAS added in extra latency for column locate, Burst is hard to explain now, WR is write recovery after full loop elapsed
^ that rule is "predicting" a read, and just matching Writes in time (stacking thing)
(it utilizes an ability of DDR4 which can push writes without delay while something is read out *)
* what people use as drop tRCD_WR, but i shy away from doing it, as it debalances everything & minimum delay is too high. Minimum tRCD_WR value is 8, double that on miss [repeated row lookup] it's value 16. tRCD can be lower than value 16 
=================
EDIT ~ Wow huge post
Bit of added theory - can be skipped over for everyone knowing how to work with their dimms 
But part of the reason @KedarWolf (early not known) experiment with tRP focus ~ functions so well
Just adds up well, but i am not sure if it still is the right way to do it ~ it's certainly the easiest one
Pushing tCAS down without pushing tRAS down is a bit debatable
I decided to stop doing it, (flat primaries)
but aren't able to preset a RAS before CAS refresh example yet ~ still learning.







We all use CAS bef RAS refresh , but it's not the only way to do it


----------



## Imprezzion

Man what a incredibly detailed post!

So, basically, on my setup that I'm testing now (is in no way actually tested stable, just testing stuff) 3866 15-8-15-15 1T GDM Off a setup of 25 tRAS, 40 tRC and 240 tRFC should, in theory, make sense. As would my previous stable tested 30 tRAS, 45 tRC and 272 tRFC.

The problem I'm beginning to have is that testing 3866 1:1 IF is pretty hard as my IF has a very hard time being actually stable at 1933. It might not spit WHEA's anymore but that doesn't make it stable per sè and I have to run pretty high / odd VDDP and VDDG values to even make it run anywhere near stability. I need at the very least 1.02v CCD and 1.12v IOD to allow it to run any stress test for any length of time with the current ProcODT and RTT's.










This setup completed the 25 1usmus runs + 8 runs of Anta777 Absolut however it did still give me a PFN_LIST_CORRUPT GSOD when in idle even tho a gaming load didn't seem to be a problem. To me this kinda points to either of these 3 timings being off as I only lowered tRAS, tRC, tRFC and tRDWR and added a slight bit of vDIMM compared to a profile that has been tested way more and is stable.

I still don't trust the stability of my IF either on 1933 either but it's hard to test. Y-cruncher test 17 doesn't trip it up nearly as bad as it has before tweaking VDDP and VDDG and in 3 hours it only had 1 single WHEA which should be manageable.


----------



## Audioboxer

Reconfigured loop with no more 120mm rad at the back and the fat boy rad down the bottom. Some cleaning and cable management to tidy up and I'll be done.

On the bucket list of "do in like a year" is working out some of those bends into pure pipe, no extension pieces/right angle pieces. Heck, the reason I installed two flow spinners is to reduce complexity in bends lol. I simply couldn't be bothered spending days doing this reconfigured loop and probably needing to buy another 3m of pipe for all the mistakes.

Only other thing I'm waiting on is a Barrow FBFT05-B, it's a better quality flow meter that doesn't break the bank. When I was tearing down this rig I accidentally pulled out the connection to the bottom of the Bykski flow meter. It's a cheap solder job, unlike the slightly better quality flow meters that have removable connections. Managed to just about solder the tiny two points back, but it's a bit temperamental.

As for why the GPU struggled to go vertical, the RAM waterblock bottom connection was causing all sorts of issues. Ah well, at least I can sell my LinkUP PCIE 4.0 cable for around £40.


----------



## mongoled

Taraquin said:


> You should try agesa 1.2.0.3b/c, for me that made 1900+ fclk possible  Maybe you can do 2000 fclk+ whea19 free like me and get perf scaling? Unify X is 2 dimm? That makes it easier.
> 
> My best using pbo+co is 12050  But board won't run more than [email protected]
> 4.675-4.7 allcore.
> 
> My 12400F gets [email protected]


Been there done that

😂 😂 

The only time I will update my BIOS is when I see a confirmed fix for WHEA "warnings" which in all honesty is never going to happen, or, somehow AMD remove the restriction stopping my CPU from using anything more that 1.45v for CPU vcore, which again is never going to happen


----------



## Blameless

I'm not sure what caused this change--perhaps the new chipset drivers--but enabling CPPC, without enabling CPPC preferred cores. now causes all of my cores to be flagged as #1:









I was testing with CPPC again, because it's _supposed_ to dynamically measure core performance and use that info to prioritize threads, but didn't seem to in the past, and definitely didn't with preferred cores enabled because the AMD order is wrong for my custom curves.

Seems to be working find now (CPPC enable, CPPC prefered cores disabled, however.

This is a clean, normal (not safe mode), boot, with no individual running of tests, on my 5800X + Timetec CRJ setup:









L3 scores are fairly consistent, and the highest I've seen on this part at these clocks, after the new drivers plus the CPPC change. 7-zip also consistently scores 108/120.

That's also what I was hoping to beat with at least a pair of my OEM B-die, but it didn't pan out. Even my good B-die (which will do straight 14s T2 @ 3800) isn't actually any faster than this CJR because it's single-rank and needs slightly looser subs.

Will probably bite the bullet and grab that Team 3600 C14 kit.


----------



## Tebore

I got the following settings fully stable on a Gigabyte AB350M-D3H.
Crucial Ballistix PC3000 15-16-16-36 Rev-E
What I'm trying to do next is turn off GDM. I Can boot to windows with the same settings and GDM off but I get errors in OCCT.

Any tips on what to tweak next to try to stabilize it with GDM off?


----------



## oobymach

Tebore said:


> I got the following settings fully stable on a Gigabyte AB350M-D3H.
> Crucial Ballistix PC3000 15-16-16-36 Rev-E
> What I'm trying to do next is turn off GDM. I Can boot to windows with the same settings and GDM off but I get errors in OCCT.
> 
> Any tips on what to tweak next to try to stabilize it with GDM off?


Lower TRC to 52, set secondary timings to auto.

ODT to 60 ohms and all 4 Str to 24ohms, and TFAW 48, may help with stability.


----------



## Blameless

Tebore said:


> Any tips on what to tweak next to try to stabilize it with GDM off?


Use all of your Rtts, try increasing clock drive strength (reduce output impedance to 24-40), and increase tRCDRD (it's already at 20 due to GDM being enabled). tRP and tRDWR might need to go up. 2T command rate will probably be required.


----------



## Imprezzion

Well, that's one problem.. I did the TM5 run on low ambients (like 14c) with the side panel open but I got the panel closed now, 21c ambient and while gaming and thus the front rad blowing hot air into the case my front DIMM is sitting at 47.8c with the other one at 45.3c. Even with a 120mm blowing (probably hot) air on them. It didn't get unstable yet but almost 48c is quite high for B-Die at the edge of stability..

Edit: it just yoinked me back to desktop in Max Payne 3 with a 0xc05 in event viewer.. it got to like 51c on 1 DIMM and said nope. 

This voltage and terrible case setup isn't going to work for 3866. I'll just go back to my stable at basically any temperature but pretty loose 3733 setup and try to maybe tweak one or two things on that.


----------



## Bloax

just have a single exhaust as intake for the RAMFAN for proper memeory temps, who needs a front or side panel anyway 🤡 🤡 🤡


----------



## KedarWolf

I'm an expert overclocker and a techie by trade.

All you need to do if you're getting poor overclocking on your CPU and RAM, is grab a five-pound sledgehammer, whack your PC repeatedly, then build a new one.

I help as I can.


----------



## Audioboxer

KedarWolf said:


> I'm an expert overclocker and a techie by trade.
> 
> All you need to do if you're getting poor overclocking on your CPU and RAM, is grab a five-pound sledgehammer, whack your PC repeatedly, then build a new one.
> 
> I help as I can.


Put your PC outside and run a long video cable/USB cable inside for monitor/peripherals. Don't worry if it rains, free watercooling that helps you overclock faster.


----------



## mongoled

Audioboxer said:


> Put your OC outside and run a long video cable/USB cable inside for monitor/peripherals. Don't worry if it rains, free watercooling that helps you overclock faster.


Nah, just stick it in a cold bath

😂😂


----------



## Imprezzion

I mean, it's my own fault for shoving a Nemesis GTX 420 + 240 and a massive EK tube res in a Evolv X and push pulling both of them. It's seriously cramped and the front 420 blows it's hot air directly on the RAM lol. GPU and CPU are nice and cool tho.. hehe.

Maybe I should waterblock my RAM.. I got the cooling capacity and I got plenty of tubing left. All I need is a RAM block and 2 fittings.. tempting..

Or, you know, just remove the side panel permanently..


----------



## Taraquin

Tebore said:


> I got the following settings fully stable on a Gigabyte AB350M-D3H.
> Crucial Ballistix PC3000 15-16-16-36 Rev-E
> What I'm trying to do next is turn off GDM. I Can boot to windows with the same settings and GDM off but I get errors in OCCT.
> 
> Any tips on what to tweak next to try to stabilize it with GDM off?


I had these 2 sets of 2x8 of sticks on my 3600. Mine was stable at 1t at 16-8-20-12 
Ras 46
Rc 58 (lower gave errors) 
Rfc 560 (2x8 of them did 536 fine) 
Rrd s/l 4/4
Faw 16
Wr 10
Rdwr 10
Wrrd 1
Rtp 5 (atleast try 6 if wr is 12)

60 20 30 24 worked fine at 40 ProcODT. 

I needed 1.08v soc, 1.04v iod, 1v ccd and 0.92v vddp.


----------



## Taraquin

oobymach said:


> Lower TRC to 52, set secondary timings to auto.
> 
> ODT to 60 ohms and all 4 Str to 24ohms, and TFAW 48, may help with stability.


I have these bins and they hate that low RC. At 3600 they could do 53, at 3733 they could do 56, lower and they spew errors.


----------



## Taraquin

Blameless said:


> Use all of your Rtts, try increasing clock drive strength (reduce output impedance to 24-40), and increase tRCDRD (it's already at 20 due to GDM being enabled). tRP and tRDWR might need to go up. 2T command rate will probably be required.


GDM only affects CL, CWL, WR and RTP making them even. Rev E can run rrally low RP, 11 was 100% stable at 3733, 12 at 3800. Rev E hates tight RCDRD, RC and RFC, except for that they are similar to my B-dies at all timings, and a bit better at RP and WTRS/L.


----------



## TMavica

any idea to fix error 2? Vdimm is 1.5v, maybe add vdimm to 1.51? or some resistance need to change?
PS: still only 1x error 2 at the end of 25 cycles


----------



## Taraquin

TMavica said:


> any idea to fix error 2? Vdimm is 1.5v, maybe add vdimm to 1.51? or some resistance need to change?
> PS: still only 1x error 2 at the end of 25 cycles
> View attachment 2552888
> 
> 
> View attachment 2552887


Try 1.51v dimm first, could be that easy


----------



## Audioboxer

TMavica said:


> any idea to fix error 2? Vdimm is 1.5v, maybe add vdimm to 1.51? or some resistance need to change?
> PS: still only 1x error 2 at the end of 25 cycles
> View attachment 2552888
> 
> 
> View attachment 2552887


What temps are your sticks hitting? I got this bin running 3800 flat 14 at 1.44v, so having to go higher than 1.5v for 14-15-15-15 would be disappointing.

My other suggestion is your IOD has caused the issue. It's too near VSOC. Reduce your IOD to 1.0v. I run CCD 0.975v and IOD 1.0v.

I'm almost certain the error is because of IOD, but let me know your temps anyway.


----------



## gameinn

If you're targeting 3600 speeds is it even worth trying to change voltages for vsoc and such or just the vdimm? I know if I was trying say 3,733+ then it would be done but leave them at auto for <= 3,600?


----------



## TMavica

Audioboxer said:


> What temps are your sticks hitting? I got this bin running 3800 flat 14 at 1.44v, so having to go higher than 1.5v for 14-15-15-15 would be disappointing.
> 
> My other suggestion is your IOD has caused the issue. It's too near VSOC. Reduce your IOD to 1.0v. I run CCD 0.975v and IOD 1.0v.
> 
> I'm almost certain the error is because of IOD, but let me know your temps anyway.


I havent try below 1.5...maybe this is problem?
Temp is around 45-50


----------



## Audioboxer

TMavica said:


> I havent try below 1.5...maybe this is problem?
> Temp is around 45-50


Over 42 degrees tRFC can start to get problematic (if it's really tight). I don't really know "cut off" stages other than to recommend if you're above 42 degrees, especially up at around 50 at times, try loosening tRFC as well.

Loosen your tRFC a bit and drop your IOD voltage and do a run.

Don't change VDIMM from 1.5v just now, that's just adding another variable. You're almost stable at 1.5v, work out what is causing the error at 1.5v. Using more VDIMM than needed isn't necessarily an issue, as long as you're cooling OK.

If you get a 25 cycle pass with the above recommendation, _then_ you can begin to see if VDIMM can come down.










This is from 5 months ago, so there are quite a few timings/resistances I wouldn't be running like this now at 3800C14. Including the SCLs. But it gives you an idea in terms of primaries what this kit might be capable of.


----------



## TMavica

Audioboxer said:


> Over 42 degrees tRFC can start to get problematic (if it's really tight). I don't really know "cut off" stages other than to recommend if you're above 42 degrees, especially up at around 50 at times, try loosening tRFC as well.
> 
> Loosen your tRFC a bit and drop your IOD voltage and do a run.
> 
> Don't change VDIMM from 1.5v just now, that's just adding another variable. You're almost stable at 1.5v, work out what is causing the error at 1.5v. Using more VDIMM than needed isn't necessarily an issue, as long as you're cooling OK.
> 
> If you get a 25 cycle pass with the above recommendation, _then_ you can begin to see if VDIMM can come down.
> 
> View attachment 2552896
> 
> 
> This is from 5 months ago, so there are quite a few timings/resistances I wouldn't be running like this now at 3800C14. Including the SCLs. But it gives you an idea in terms of primaries what this kit might be capable of.


I dont want TRFC higher than 256...maybe I try to adjust the IOD and CCD first, and see what happen


----------



## Audioboxer

TMavica said:


> I dont want TRFC higher than 256...maybe I try to adjust the IOD and CCD first, and see what happen


My tRFC is higher above because it scales with voltage and running something like 1.44v you have to be mindful that tRFC might need decreased. Just FYI I plucked 272 out of thin air back then just to be safe. Entirely possible something like 256 could be usable around 1.45v.

But yes, look at IOD first. Have it at least 0.06v below VSOC.


----------



## Imprezzion

What I've noticed is 42c as @Audioboxer said and also 48c is a cut-off on mine at least. 240 works below 48c, above I need 252.

I still have to find the magic timing / setting that will finally allow me to run 3733 CAS 14 1T GDM Off without mismatching tPHYRDL 26/28.

Btw, now that I think of it, if I run GDM enabled but use only even numbers, does GDM even do anything at that point? Since just having it enabled will fix tPHYRDL for me on CAS 14 maybe that would work..


----------



## Veii

Imprezzion said:


> The problem I'm beginning to have is that testing 3866 1:1 IF is pretty hard as my IF has a very hard time being actually stable at 1933. It might not spit WHEA's anymore but that doesn't make it stable per sè and I have to run pretty high / odd VDDP and VDDG values to even make it run anywhere near stability.











I mean, i'm not really running them much lower
But usually offsetting through lower procODT, should be your goal
Will allow you to use potentially lower voltages too ~ but will destabilize dimms again








Is it possible to positive increase CO on these cores and also potentially lower Core 10 further into the negatives ?
At least, so it switches to 4975 strap. At best 5000 but up to left CO range
Can assist it by pulling anything around it, upwards


Audioboxer said:


> View attachment 2552788
> 
> 
> Reconfigured loop with no more 120mm rad at the back and the fat boy rad down the bottom. Some cleaning and cable management to tidy up and I'll be done.


Beautiful system ! 
I was told that curved pipes influencing waterflow , are one of the oldest holding myths in watercooling setups
On a prime loop where there is no air, i also don't think that it should make a difference ~ as pressure of water should not change by the flow direction or by it's gravity
It's gravity i mean won't change, soo a coil or whatever you want to draw in an enclosed loop with equal build up thermal pressure ~ should not cause a gravity decrease and so no water density difference
Meaning , it logically to me ~ can not be a thing of straights or not, influencing waterflow
It just doesnt make sense, as water integrity doesn't change, when there is no air inside

EDIT:
There can be a subtle difference in the distance of pipe - water has to travel
That can potentially influence the pressure in a loop and show slower waterflow
But honestly , i doubt. Lakes deep or not with same wideness, have equal flowrate of water (to some extend, up to depth which increase pressure)
But here the mass of water stays the same, soo the potentially only byproduct showing a difference ~ is more water = more heatsoaking , slower temperature difference and so slightly different water-pressure by heat

But that's equally happening on a bigger rad or more rads
A coil, or a straight should not change water pressure the pump has to assert into , so water moves
A primed system always will move at the same speed, soo also block order doesn't matter because of such  Pressure is pretty much equalized across the loop & so is temperature then too
* but i can see that it makes sense increasing the pump curve on a slightly warmer liquid temp ~ if you want to keep perfectly same flowrate on differing pressure
** i can also see where this could come from, on open air pipes which even differ in height (gravity) for houses , or other hose's (garden-hose)
Size of the tube & corners weakening reflection pressure will influence build up pressure, but on a closed primed loop (with no air) the pressure and thermals equalized and the same force is used up to fluid density ~ there is no air + gravity to dampen it. Gravity is only outside and will compress water equally slightly
Soo you can use huge diameter tubes in a closed system and the flowrate will be nearly the same


----------



## Audioboxer

lol at the discrepancy with these flow meters. Replaced my cheaper Bykski with the latest Barrow model and it's reporting 4.68l/min. The Bkyski was 3.0l/min.

At least this one has a proper detachable fan header cable, no molex power. I accidentally ripped the tiny soldered on connection off my Bykski and had a hell of a time soldering it back on.

A D5 pump with three rads and three blocks at 100% doing 4.68l/min, I guess someone more knowledgeable than me with these pumps would need to decide what "flow meter" is more accurate!

The Barrow at least seems to have a proper propeller, not the cheap noisy crap thing the Bykski has.


----------



## Tebore

Taraquin said:


> GDM only affects CL, CWL, WR and RTP making them even. Rev E can run rrally low RP, 11 was 100% stable at 3733, 12 at 3800. Rev E hates tight RCDRD, RC and RFC, except for that they are similar to my B-dies at all timings, and a bit better at RP and WTRS/L.


Thanks.
No offence to the others who tried to help but the advice didn't seem like they had enough experience with Rev-E and this particular combo.
Your posts summarized my findings and hours of testing
What makes this a bit more difficult is these are DR 16GB sticks
My TRFC won't go lower than 305ns so rounded up I have them at 592, no errors it either boots or it doesn't. Even loosening at 350ns (666)

I will play with some of the timings you mentioned.


----------



## Blameless

Taraquin said:


> GDM only affects CL, CWL, WR and RTP making them even.


That's the JEDEC spec, but I've been reasonably sure it affects a lot more on this platform.

I don't recall ever seeing any AM4 system I've had show clear benefit from odd numbered values on _any_ primary timings while GDM was enabled.

I'll test it again though.

_Edit:_ testing the differences between 18-22-22, 18-21-21, and 18-20-20 on the system I'm using now. 18-20-20 is clearly faster, but 18-22-22 and 18-21-21 are within margin of error, and not always in favor of the 21s.

I'm pretty sure it's just rounding up the 21 values to 22, in practice.


----------



## Taraquin

Tebore said:


> Thanks.
> No offence to the others who tried to help but the advice didn't seem like they had enough experience with Rev-E and this particular combo.
> Your posts summarized my findings and hours of testing
> What makes this a bit more difficult is these are DR 16GB sticks
> My TRFC won't go lower than 305ns so rounded up I have them at 592, no errors it either boots or it doesn't. Even loosening at 350ns (666)
> 
> I will play with some of the timings you mentioned.


On dual rank I would consider higher rfc and maybe 2t  use 592 then  rcdrd of 20, rc of 56-62 I think is the main key to stability.


----------



## Taraquin

Blameless said:


> That's the JEDEC spec, but I've been reasonably sure it affects a lot more on this platform.
> 
> I don't recall ever seeing any AM4 system I've had show clear benefit from odd numbered values on _any_ primary timings while GDM was enabled.
> 
> I'll test it again though.
> 
> _Edit:_ testing the differences between 18-22-22, 18-21-21, and 18-20-20 on the system I'm using now. 18-20-20 is clearly faster, but 18-22-22 and 18-21-21 are within margin of error, and not always in favor of the 21s.
> 
> I'm pretty sure it's just rounding up the 21 values to 22, in practice.


Gdm affects more, Veii has indepth info, but timingwise it's only supposed to round up the 4 mentioned


----------



## Blameless

Taraquin said:


> Gdm affects more, Veii has indepth info, but timingwise it's only supposed to round up the 4 mentioned


What it's supposed to do comes a very distant second to what it actually does.

I still can't produce any performance benefits from odd tRCD or tRP with GDM enabled, but I did just get a decoding error in 7-zip that I cannot reproduce with the next higher even-numbered timings.

So, maybe it is actually trying to set odd values here. However, if it doesn't actually improve performance, they probably shouldn't be used.

@Tebore should test to verify that the odd tRCD is actually helping performance. If it's not, it should be left at the next step up, as it may be harming stability for no advantage.


----------



## Taraquin

Blameless said:


> What it's supposed to do comes a very distant second to what it actually does.
> 
> I still can't produce any performance benefits from odd tRCD or tRP with GDM enabled, but I did just get a decoding error in 7-zip that I cannot reproduce with the next higher even-numbered timings.
> 
> So, maybe it is actually trying to set odd values here. However, if it doesn't actually improve performance, they probably shouldn't be used.
> 
> @Tebore should test to verify that the odd tRCD is actually helping performance. If it's not, it should be left at the next step up, as it may be harming stability for no advantage.


Remember that for instance rcdrd can have a relation to rdwr so if you change one and not the other it can have an effect. I got positive scaling on my rev E going from rcdrd 20 to 19 with gdm, but there are many factors.


----------



## Blameless

Taraquin said:


> Remember that for instance rcdrd can have a relation to rdwr so if you change one and not the other it can have an effect. I got positive scaling on my rev E going from rcdrd 20 to 19 with gdm, but there are many factors.


I'm trying to isolate the timings as much as possible. In my case, tRDWR is low enough (8) that it shouldn't hurt anything at tRCDRD 19 or 20...I can't tRDWR any further and raising it to 9 or 10 sure doesn't help performance.

That said, if you see a consistent difference, I don't doubt it.


----------



## Tebore

Taraquin said:


> On dual rank I would consider higher rfc and maybe 2t  use 592 then  rcdrd of 20, rc of 56-62 I think is the main key to stability.


I'd rather Keep GDM on and a lower RCDRD than take 2T and RCDRD 20. I gave VDDP a little bump because I think Heard some audio pop and got 1 WHEA during testing. 
Anyway here's what I got stable with OCCT and some gaming. I will put it thru the lengthier torture tests tonight.


----------



## Taraquin

Tebore said:


> I'd rather Keep GDM on and a lower RCDRD than take 2T and RCDRD 20. I gave VDDP a little bump because I think Heard some audio pop and got 1 WHEA during testing.
> Anyway here's what I got stable with OCCT and some gaming. I will put it thru the lengthier torture tests tonight.
> 
> View attachment 2552928


Most looks good now. Try rtp 6 (should be half wr), wrrd 3 might work.


----------



## mongoled

Audioboxer said:


> View attachment 2552905
> 
> 
> lol at the discrepancy with these flow meters. Replaced my cheaper Bykski with the latest Barrow model and it's reporting 4.68l/min. The Bkyski was 3.0l/min.
> 
> At least this one has a proper detachable fan header cable, no molex power. I accidentally ripped the tiny soldered on connection off my Bykski and had a hell of a time soldering it back on.
> 
> A D5 pump with three rads and three blocks at 100% doing 4.68l/min, I guess someone more knowledgeable than me with these pumps would need to decide what "flow meter" is more accurate!
> 
> The Barrow at least seems to have a proper propeller, not the cheap noisy crap thing the Bykski has.


Is this what you had before ?









Considering that I am using the Aquacomputer Ultitop Dual D5 top and I cant for the life of me find some excellent testing data someone had done with different dual pump setups I would say that the flowrate on the Barrow is completely out of whack.

With both pumps running at max rpm (arnd 4700rpm) my flowmeter shows around 4.0 to 4.1 l/min

When I was using one D5 the flowrate was around 3.1 to 3.2 l/min but since then ive changed the loop with only one change of component (out came the Alphacool NexXxoS UT60 280mm and in went an EK-CoolStream XE 360).


----------



## Audioboxer

mongoled said:


> Is this what you had before ?
> 
> View attachment 2552933
> 
> 
> Considering that I am using the Aquacomputer Ultitop Dual D5 top and I cant for the life of me find some excellent testing data someone had done with different dual pump setups I would say that the flowrate on the Barrow is completely out of whack.
> 
> With both pumps running at max rpm (arnd 4700rpm) my flowmeter shows around 4.0 to 4.1 l/min
> 
> When I was using one D5 the flowrate was around 3.1 to 3.2 l/min but since then ive changed the loop with only one change of component (out came the Alphacool NexXxoS UT60 280mm and in went an EK-CoolStream XE 360).


Yes, that's the Bykski. The Barrow I'm using now reports 3.83l/min at 75% pump speed and 5.31l/min at 100%.

Under load I'm doing some testing between 75%~100% as in theory if you have something like 3.83l/min and go to 5.31l/min a temperature drop might not even happen due to sufficient flow.

So far water temp seems to be remaining the same at 75% or 100%.

I'm going to guess the Bykski under-reports because its propeller is pretty crap, but the Barrow might be over-reporting even with a better propeller.

There are a number of versions of the Barrow, I'm using the latest FBFT05.


----------



## Tebore

Taraquin said:


> Most looks good now. Try rtp 6 (should be half wr), wrrd 3 might work.


I'll play with those a bit later. 
I remember when I was getting to 1900FCLK I couldn't drop those too much.
According to AIDA my read took about a 250-400MB hit going to RCDRD 20 from 19. 
But I shaved about 0.7ns on Latency turning GDM off.


----------



## mongoled

Audioboxer said:


> Yes, that's the Bykski. The Barrow I'm using now reports 3.83l/min at 75% pump speed and 5.31l/min at 100%.
> 
> Under load I'm doing some testing between 75%~100% as in theory if you have something like 3.83l/min and go to 5.31l/min a temperature drop might not even happen due to sufficient flow.
> 
> So far water temp seems to be remaining the same at 75% or 100%.
> 
> I'm going to guess the Bykski under-reports because its propeller is pretty crap, but the Barrow might be over-reporting even with a better propeller.
> 
> There are a number of versions of the Barrow, I'm using the latest FBFT05.


Nope,

Ive found the thread/post

 









OCN Community Water Cooling Test Thread


Fast Fate, Good day to you and thank you for that information. I did not know @gaggeg authored that. It was actually a deciding factor resulting in working on a way to mount that beast on an S8. Very cool. A follow up question please. Basically am I on the right path and if not ideas to get...




www.overclock.net





According to that persons findings a single "Aquacomputer Ultitop D5" at 100% power (4828 rpm) would have a flowate of 4.4 l/min on their test bench that comprises of one 360mm radiator in a loop with the pump and flowmeter.

So if we take into account that we both have two radiators, one cpu, one gpu and one ram waterblock I think its safe to say that the Barrow is most definately out of whack.

My readings of 3.1-3.2 l/min seem more inline of what to expect, though I do believe that this reading is a little high.

You are right about the impeller, its a crappy thing

😂😂 

Moving onto the dual D5 data, at 100% power their data shows 5.5 l/min, so my reading of 4.0-4.1 l/min is, just like the single results, a little high.

At least that is how I am reading the data


----------



## Audioboxer

mongoled said:


> Nope,
> 
> Ive found the thread/post
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> OCN Community Water Cooling Test Thread
> 
> 
> Fast Fate, Good day to you and thank you for that information. I did not know @gaggeg authored that. It was actually a deciding factor resulting in working on a way to mount that beast on an S8. Very cool. A follow up question please. Basically am I on the right path and if not ideas to get...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> According to that persons findings a single "Aquacomputer Ultitop D5" at 100% power (4828 rpm) would have a flowate of 4.4 l/min on their test bench that comprises of one 360mm radiator in a loop with the pump and flowmeter.
> 
> So if we take into account that we both have two radiators, one cpu, one gpu and one ram waterblock I think its safe to say that the Barrow is most definately out of whack.
> 
> My readings of 3.1-3.2 l/min seem more inline of what to expect, though I do believe that this reading is a little high.
> 
> You are right about the impeller, its a crappy thing
> 
> 😂😂
> 
> Moving onto the dual D5 data, at 100% power their data shows 5.5 l/min, so my reading of 4.0-4.1 l/min is, just like the single results, a little high.
> 
> At least that is how I am reading the data


Probably means the Bykski is closer to the reality then! lol

It can be noisy though which is annoying. At least the Barrow is silent.


----------



## mongoled

Audioboxer said:


> Probably means the Bykski is closer to the reality then! lol
> 
> It can be noisy though which is annoying. At least the Barrow is silent.


I got lucky then, mine starts to make a little noise just after 4 l/min

😃😃


----------



## Tebore

Blameless said:


> What it's supposed to do comes a very distant second to what it actually does.
> 
> I still can't produce any performance benefits from odd tRCD or tRP with GDM enabled, but I did just get a decoding error in 7-zip that I cannot reproduce with the next higher even-numbered timings.
> 
> So, maybe it is actually trying to set odd values here. However, if it doesn't actually improve performance, they probably shouldn't be used.
> 
> @Tebore should test to verify that the odd tRCD is actually helping performance. If it's not, it should be left at the next step up, as it may be harming stability for no advantage.


I'd have to find the white paper where I read this. But basically GDM will round up some odd timings to even. Like CL17 to CL18 because it's not physically capable of doing a half cycle as it's already doing the second command at half the cycle.

However with certain timings it's setting a minimum delay to an action as long as the minimum passes it can still action as it's not impacted by a second sending of commands, where some timings are dependent on each other.

Engineering DRAM isn't my specialty so I'll leave it to someone else to explain.

With GDM on and a given FCLK:
What I did notice when I'm setting TRCDRD on Rev E is there is a performance impact but not as much as a stability impact when raising TRCDRD. Eg PC3600 TRCD18 gives me X score, but it's not completely stable moving it to 19 removes all errors while being within range of X-5% Score vs moving to 20, I gain nothing in stability but X-10%. Moving it to 19 allowed me to go to 3800.

I should mention at this point I can't bring TWR any lower without errors. I guess it's a draw back of having 2x16 DR vs 2x8 SR.


----------



## Blameless

Tebore said:


> I'd have to find the white paper where I read this. But basically GDM will round up some odd timings to even. Like CL17 to CL18 because it's not physically capable of doing a half cycle as it's already doing the second command at half the cycle.
> 
> However with certain timings it's setting a minimum delay to an action as long as the minimum passes it can still action as it's not impacted by a second sending of commands, where some timings are dependent on each other.
> 
> Engineering DRAM isn't my specialty so I'll leave it to someone else to explain.


The JEDEC definition and spec are repeated in essentially every DDR4 DRAM datasheet. It's only explicitly described as affected a handful of timings.

However, there always seem to be effects beyond those explicitly stated, like this example: What is DDR4 Memory Gear-Down Mode? | FuturePlus Systems



Tebore said:


> With GDM on and a given FCLK:
> What I did notice when I'm setting TRCDRD on Rev E is there is a performance impact but not as much as a stability impact when raising TRCDRD. Eg PC3600 TRCD18 gives me X score, but it's not completely stable moving it to 19 removes all errors while being within range of X-5% Score vs moving to 20, I gain nothing in stability but X-10%. Moving it to 19 allowed me to go to 3800.


I've tested on three of my systems, so far (all with very different memory configurations), and between any given even tRCDRD and the next lower (odd) value, I cannot reproduce any consistent performance impact. Not sure I can reproduce any stability difference either. Adjusting tRP does seem to impact stability, even when accounting for the changes to tRC by increasing tRAS by one to maintain the same tRC, so I at least know that's doing, or trying to do, something.

I'm testing with AIDA64, 7-zip, and y-cruncher, on lean Windows 10 setups that tend to produce very consistent results.

Boot-to-boot training variance, and run-to-run bench variance are about a tenth of a percent in y-cruncher in either direction. The difference I see when only adjusting tRCD by one with GDM enabled is indistinguishable from this.

Where are you seeing such a large change in score? A 5-10% difference from just one point of tRCD is incredible, in every sense of the word.


----------



## TMavica

Audioboxer said:


> My tRFC is higher above because it scales with voltage and running something like 1.44v you have to be mindful that tRFC might need decreased. Just FYI I plucked 272 out of thin air back then just to be safe. Entirely possible something like 256 could be usable around 1.45v.
> 
> But yes, look at IOD first. Have it at least 0.06v below VSOC.


I just raised the SOC to 1.1.25, so it doesnt close to IOD, but got reboot when during tm5 test. I found that my memory kit got around 55 degree or higher during tm5 test. The reason i think is I using C8E mobo and installed a M2 expansion card, it just sit next to my memory, the expansion card has blocked the airflow of those inlet fan, so the airflow cant reach to my memory...so my memory got high temp...I decided to raise the TRFC to 272 , Vdimm 1.45, TM5 now error free but the temp still can reach 52 degree. I guess I need stuck at these setting. By the way, my kit can go CL13, but havent test yet, maybe I should try CL13 with TRFC stuck at 272. The problem mainly I guess is the memory kit is too hot due insufficient airflow ..I cant get rid of the M2 Dimm , because I need it


----------



## Taraquin

Rev E handles heat well. Reboot during TM5 could be for instance fclk stability if it was instant or rfc/rc if you got bsod.


----------



## TMavica

Taraquin said:


> Rev E handles heat well. Reboot during TM5 could be for instance fclk stability if it was instant or rfc/rc if you got bsod.


never BSOD or whea. I think it is because of heat, too low TRFC cause the issue, now I raise the TRFC to 272 and lower vdimm to 1.45, no more issue. My memory is lack of airflow, as the airflow cant reach to the memory and cause overheating


----------



## Taraquin

TMavica said:


> never BSOD or whea. I think it is because of heat, too low TRFC cause the issue, now I raise the TRFC to 272 and lower vdimm to 1.45, no more issue. My memory is lack of airflow, as the airflow cant reach to the memory and cause overheating


Sorry, mixed you with another, B-die hates heat and becomes more sensitive when running tught rfc. Good you found a solution


----------



## Audioboxer

TMavica said:


> I just raised the SOC to 1.1.25, so it doesnt close to IOD, but got reboot when during tm5 test. I found that my memory kit got around 55 degree or higher during tm5 test. The reason i think is I using C8E mobo and installed a M2 expansion card, it just sit next to my memory, the expansion card has blocked the airflow of those inlet fan, so the airflow cant reach to my memory...so my memory got high temp...I decided to raise the TRFC to 272 , Vdimm 1.45, TM5 now error free but the temp still can reach 52 degree. I guess I need stuck at these setting. By the way, my kit can go CL13, but havent test yet, maybe I should try CL13 with TRFC stuck at 272. The problem mainly I guess is the memory kit is too hot due insufficient airflow ..I cant get rid of the M2 Dimm , because I need it


That's one way to do it, but I find it more effecient I guess to run things like VSOC and VDDG as low as they can be without any performance hit. 

But yeah heat is likely hurting you now at those temps. Just increase tRFC a bit. With B-die you're still getting much better tRFC values than you would on other kits.


----------



## Imprezzion

That's weird. With all even timings (subs as well) and GDM Off it boots 3733 14-8-14-14 with 26 tRAS, 40 tRC and 240 tRFC just fine but when I enable GDM to get tPHYRDL to train it won't boot. Page fault BSOD.

Is there any other trick to getting tPHYRDL to train 26/26 in stead of 26/28 without touching VDDP/VDDG's? It only trains 26/26 on uneven CAS with GDM Off. As soon as I use a even CAS, 14 or 16, it goes to 26/28.


----------



## Farih

How is this for 4x8GB sticks?

Vdimm = 1.435V









Sadly couldn't do CL14 at 3800, couldn't even do CL14 at 3600mzh :-(
tFAW at 16 gave errors to :-(

This is prolly where i max out on 4 sticks before going into high voltages right?


----------



## Audioboxer

Imprezzion said:


> That's weird. With all even timings (subs as well) and GDM Off it boots 3733 14-8-14-14 with 26 tRAS, 40 tRC and 240 tRFC just fine but when I enable GDM to get tPHYRDL to train it won't boot. Page fault BSOD.
> 
> Is there any other trick to getting tPHYRDL to train 26/26 in stead of 26/28 without touching VDDP/VDDG's? It only trains 26/26 on uneven CAS with GDM Off. As soon as I use a even CAS, 14 or 16, it goes to 26/28.


2T or 1T?

ProcODT can be used for powering but as Veii often says its not good to rely on it.


----------



## Taraquin

Farih said:


> How is this for 4x8GB sticks?
> 
> Vdimm = 1.435V
> View attachment 2552989
> 
> 
> Sadly couldn't do CL14 at 3800, couldn't even do CL14 at 3600mzh :-(
> tFAW at 16 gave errors to :-(
> 
> This is prolly where i max out on 4 sticks before going into high voltages right?


Voltage on ram? 1.45v is safe, 1.5v is doable with some airflow. I would try 1.45v, 15 15 15 30 45, gdm off, 2t.

If faw 16 is tricky, try 5/7 rrds/l and 20 faw. Scl 4 is easier to run and performs similar. Rdwr might do 9 or 8, wrrd can do 3.


----------



## Taraquin

Audioboxer said:


> That's one way to do it, but I find it more effecient I guess to run things like VSOC and VDDG as low as they can be without any performance hit.
> 
> But yeah heat is likely hurting you now at those temps. Just increase tRFC a bit. With B-die you're still getting much better tRFC values than you would on other kits.


This! 

If you run at PPT limit high soc, iod etc will eat from your pwrbudget. 

Going from 1.14 soc, 1.06 iod, 0.94 ccd and 0.9 vvdp to 1.12, 1.04 and 0.84 ccd/vddp boosted allcore by around 100MHz on my 76W PPT.


----------



## TMavica

Audioboxer said:


> That's one way to do it, but I find it more effecient I guess to run things like VSOC and VDDG as low as they can be without any performance hit.
> 
> But yeah heat is likely hurting you now at those temps. Just increase tRFC a bit. With B-die you're still getting much better tRFC values than you would on other kits.


Yes. my kit is fine with trfc 272 now. However feel little waste, my kit is 4000c14 royal elite, also no way for me to improve the airflow to the memory


----------



## TMavica

Taraquin said:


> This!
> 
> If you run at PPT limit high soc, iod etc will eat from your pwrbudget.
> 
> Going from 1.14 soc, 1.06 iod, 0.94 ccd and 0.9 vvdp to 1.12, 1.04 and 0.84 ccd/vddp boosted allcore by around 100MHz on my 76W PPT.


Maybe i misunderstand, so you also recommend use lower vsoc and iod for better cpu boost?
My ppt tdc edc is 200 120 140 agesa 1.2.0.6b, and dynamic oc 4500Mhz.


----------



## Taraquin

TMavica said:


> Maybe i misunderstand, so you also recommend use lower vsoc and iod for better cpu boost?
> My ppt tdc edc is 200 120 140 agesa 1.2.0.6b, and dynamic oc 4500Mhz.


Find lowest stable that does not reduce performance or stability. Dual rank ram and 2 CCD CPUs tend to need a bit more SOC, CCD and IOD though so you might not be able to go much lower, but worth exploring. VDDP and CCD might work as low as 850mv, IOD and SOC may be as low as they go. For 3800 on SR I need 1.06V SOC and 0.98V IOD for max speed\stability.

As for timings you can probably lower RAS and RC some more. Maybe RP 1 down? For instance 14 RP, 28 RAS, 42 RC, maybe lower? Might work and improve performance a bit. Lower RP may need more voltage, but RAS\RC can often be lowered without increasing voltage. Just keep the RAS+RP=RC rule


----------



## domdtxdissar

Taraquin said:


> This!
> 
> If you run at PPT limit high soc, iod etc will eat from your pwrbudget.
> 
> Going from 1.14 soc, 1.06 iod, 0.94 ccd and 0.9 vvdp to 1.12, 1.04 and 0.84 ccd/vddp boosted allcore by around 100MHz on my 76W PPT.


Indeed, this is from a other forum where i tried to run as efficient as i could in Cinebench r23:
5950x @ 51w PPT -> 20681 points in Cinebench r23 = "405 score per watt"




Soc was sucking down a massive ~2.6w under full load in Cinebench


----------



## TMavica

Taraquin said:


> Find lowest stable that does not reduce performance or stability. Dual rank ram and 2 CCD CPUs tend to need a bit more SOC, CCD and IOD though so you might not be able to go much lower, but worth exploring. VDDP and CCD might work as low as 850mv, IOD and SOC may be as low as they go. For 3800 on SR I need 1.06V SOC and 0.98V IOD for max speed\stability.
> 
> As for timings you can probably lower RAS and RC some more. Maybe RP 1 down? For instance 14 RP, 28 RAS, 42 RC, maybe lower? Might work and improve performance a bit. Lower RP may need more voltage, but RAS\RC can often be lowered without increasing voltage. Just keep the RAS+RP=RC rule


Trfc stuck at 272, i also thinking about to tune the others, but more voltage , result in more heat….so maynot be success, lack of airflow, this is the big problem


----------



## Taraquin

domdtxdissar said:


> Indeed, this is from a other forum where i tried to run as efficient as i could in Cinebench r23:
> 5950x @ 51w PPT -> 20681 points in Cinebench r23 = "405 score per watt"
> 
> 
> 
> 
> Soc was sucking down a massive ~2.6w under full load in Cinebench


Running slow ram to get very low soc?  Very impressive!


----------



## Taraquin

TMavica said:


> Trfc stuck at 272, i also thinking about to tune the others, but more voltage , result in more heat….so maynot be success, lack of airflow, this is the big problem


As I said you can probably run RAS and RC lower without more voltage or heat  It will improve performance a bit. Lowering RP may need more volt, but it may not, worth checking out.


----------



## domdtxdissar

Taraquin said:


> Running slow ram to get very low soc?  Very impressive!


Yes memory dont matter in cinebench 😇
But pretty low voltages also, vsoc at 850mv and vcore at ~700mv


----------



## Imprezzion

Audioboxer said:


> 2T or 1T?
> 
> ProcODT can be used for powering but as Veii often says its not good to rely on it.


1T. I am pretty much in the middle of ProcODT at 34.3Ohm but with relatively low vddp/vddg/vsoc and I wanna keep those low so I have more power and temp budget for the CPU cores.

If I run 3733 14-8-15-13 now with mismatched tPHYRDL it actually performs slightly worse then 15-8-15-13 with matched tPHYRDL so unless I can make it work it's better to stay with CAS 15.

I did think about just buying a better bin then I have now for the RAM but if it can't train CAS14 that wouldn't make much sense. Unless I manage to find DIMM's that will do C13 on 3733 but that is quite tight even for a good bin.


----------



## Audioboxer

TMavica said:


> Trfc stuck at 272, i also thinking about to tune the others, but more voltage , result in more heat….so maynot be success, lack of airflow, this is the big problem


I wouldn't worry too much about tRFC when it's that low, performance will still be really good. You can try dropping VDIMM a bit and see if it's stable with tCL14 at like 1.45~1.46v.



Imprezzion said:


> 1T. I am pretty much in the middle of ProcODT at 34.3Ohm but with relatively low vddp/vddg/vsoc and I wanna keep those low so I have more power and temp budget for the CPU cores.
> 
> If I run 3733 14-8-15-13 now with mismatched tPHYRDL it actually performs slightly worse then 15-8-15-13 with matched tPHYRDL so unless I can make it work it's better to stay with CAS 15.
> 
> I did think about just buying a better bin then I have now for the RAM but if it can't train CAS14 that wouldn't make much sense. Unless I manage to find DIMM's that will do C13 on 3733 but that is quite tight even for a good bin.


Report back on what your tPHYRDL trains at with 2T.

In other news, summer weather hitting the UK, that means ambient temps going up  No more CB23 runs for a while! 










GPU temps on idle are great still, they're tracking just above ambient. Cooler than the actual water temp  Guess this shows the importance of fans at the bottom of the case drawing air in, it also cools the GPU.


----------



## Audioboxer

MSI finally rolled out 1.2.0.6c to the B550 boards






MSI MEG B550 UNIFY X Motherboard


MSI MEG B550 UNIFY X Motherboard




uk.msi.com







> Description:
> 
> Update to AMD ComboAm4v2PI 1.2.0.6c
> Support AMD Ryzen 7 5800X3D


Here we go again, I guess. Time to see if the curve needs to be done again and if there are any issues with memory.


----------



## Audioboxer

Audioboxer said:


> MSI finally rolled out 1.2.0.6c to the B550 boards
> 
> 
> 
> 
> 
> 
> MSI MEG B550 UNIFY X Motherboard
> 
> 
> MSI MEG B550 UNIFY X Motherboard
> 
> 
> 
> 
> uk.msi.com
> 
> 
> 
> 
> 
> 
> 
> Here we go again, I guess. Time to see if the curve needs to be done again and if there are any issues with memory.


Holy **** AMD has actually made this worse. It seems like EDC over 140 caps you at like 1.2v. With PBO on, but figures on AUTO, voltage seems to struggle to go much higher than around 1.32v.

I've ran CB23s and can't get it going higher, even with the old trick of setting PBO values in Ryzen Master.

Also turned off telemetry to make sure it wasn't screwing with anything.

What is AMD doing with these processers? Anyone want to come defend this _now_?


----------



## Imprezzion

I was about to ask if they "fixed" the 1.425v lock but nah they made it worse lol.. Yet another reason to cherish my 1.2.0.3c BIOS and never ever update it or the chipset drivers for that matter.


----------



## Audioboxer

Imprezzion said:


> I was about to ask if they "fixed" the 1.425v lock but nah they made it worse lol.. Yet another reason to cherish my 1.2.0.3c BIOS and never ever update it or the chipset drivers for that matter.












1.195v max voltage

1.32v is max with PBO values on AUTO.

CB23 scores are rough, barely breaking 30k now when I was at like 314xx on AGESA 1.2.0.5.

Absolute shambles of a company. No defending this now.

Edit -









One core has slithered its way up to 1.208v. Absolutely anaemic.


----------



## ArchStanton

Audioboxer said:


> Absolutely anaemic.


I keep wondering why the, at this point I assume intentional on AMD's part, reduction in voltages. Are they being lazy and setting up *everything* to be safe with the 5800X3D's or have they seen some degradation in their in-house testing that they are trying to prevent or were they aware of the possibility of degradation from the get-go but wanted those big numbers from reviewers and early adopters in the DIY community or is it something else entirely? Whatever their motivations are, I share your frustration with their lack of communication.


----------



## Audioboxer

ArchStanton said:


> I keep wondering why the, at this point I assume intentional on AMD's part, reduction in voltages. Are they being lazy and setting up *everything* to be safe with the 5800X3D's or have they seen some degradation in their in-house testing that they are trying to prevent or were they aware of the possibility of degradation from the get-go but wanted those big numbers from reviewers and early adopters in the DIY community or is it something else entirely? Whatever their motivations are, I share your frustration with their lack of communication.


Dropping us to 1.425v was bad enough with zero communication, so no one knows if it's a bug or not. Reducing everyone to 1.2v is just madness. 

Gone back to 1.2.0.5 which has thankfully reversed these changes. Always worried when you flash a bios something changes permanently.

Now it's up to the bloggers, tech media and youtubers to... ask AMD what the hell is going on?


----------



## Farih

Taraquin said:


> Voltage on ram? 1.45v is safe, 1.5v is doable with some airflow. I would try 1.45v, 15 15 15 30 45, gdm off, 2t.
> 
> If faw 16 is tricky, try 5/7 rrds/l and 20 faw. Scl 4 is easier to run and performs similar. Rdwr might do 9 or 8, wrrd can do 3.


Tried 1.45v, 15 15 15 30 45, gdm off, 2t. No boot.
Then Tried with 1.465V.... No boot.

"If faw 16 is tricky, try 5/7 rrds/l and 20 faw. Scl 4 is easier to run and performs similar. Rdwr might do 9 or 8, wrrd can do 3."
Tried this but also no boot.
Setting Rdwr back to 10 made it boot up again.
SCL's back to 3 and still booted.
This gave error 6 in testmem5.
Upped SoC voltage from 1.1V to 1.125V in BIOS

Seems stable now and latency went from 63.7 in Aida to 63.5

Thanks!


----------



## Taraquin

Farih said:


> Tried 1.45v, 15 15 15 30 45, gdm off, 2t. No boot.
> Then Tried with 1.465V.... No boot.
> 
> "If faw 16 is tricky, try 5/7 rrds/l and 20 faw. Scl 4 is easier to run and performs similar. Rdwr might do 9 or 8, wrrd can do 3."
> Tried this but also no boot.
> Setting Rdwr back to 10 made it boot up again.
> SCL's back to 3 and still booted.
> This gave error 6 in testmem5.
> Upped SoC voltage from 1.1V to 1.125V in BIOS
> 
> Seems stable now and latency went from 63.7 in Aida to 63.5
> 
> Thanks!
> 
> View attachment 2553004


Okay, you can try 15 15 15 30 45 and 1.5v on ram, works fine if you have some airflow. 

Set DrvStr to 40 20 30 24, maybe that works.


----------



## Imprezzion

Audioboxer said:


> Dropping us to 1.425v was bad enough with zero communication, so no one knows if it's a bug or not. Reducing everyone to 1.2v is just madness.
> 
> Gone back to 1.2.0.5 which has thankfully reversed these changes. Always worried when you flash a bios something changes permanently.
> 
> Now it's up to the bloggers, tech media and youtubers to... ask AMD what the hell is going on?


Get Steve (Gamers Nexus) in on this. Maybe he can do a Newegg style video  .


----------



## ArchStanton

Imprezzion said:


> Get Steve


Rumor has it that Tech Jesus currently spends most of his time starring longingly at his newly acquired fan tester nursing a semi .


----------



## Audioboxer

Imprezzion said:


> Get Steve (Gamers Nexus) in on this. Maybe he can do a Newegg style video  .


Just need ANYONE with any sort of ability to contact AMD to ask them what they're doing. Could try asking the motherboard manufacturers but Veii made it sound like most of them have their lips sealed by AMD.


----------



## Veii

Audioboxer said:


> Now it's up to the bloggers, tech media and youtubers to... ask AMD what the hell is going on?


Hahaha
I warned  and i'm sorry for laughing. It's a tragedy
it's for preparation to ZenX3D
You can't lock Vermeer down without locking Vermeer down

i would downgrade, but then you have Vermeer CO issues
CO is the same between both B and C
but C hardlocks OCing for Vermeer-X


Audioboxer said:


> Veii made it sound like most of them have their lips sealed by AMD.


Reality 

i know it's very rough translated, but want to give/advice page 116 and 117 to read








[Übersicht] - Ultimative AM4 UEFI/BIOS/AGESA Übersicht


na sagen wir mal so, solange AMD noch an der AGESA bastelt und fixt, wäre es schön, wenn Asrock das auch begleitet und ggf ein letztes Bios mit letzter AGesa bringt. Zeit ist mir egal, drängt nicht, aber ein B450, welchen alle erhältlichen CPUs unterstützt, sollte auch die letzte AGESA bekommen...




www.hardwareluxx.de




if you don't care much about upgrading to Gen-X CPUs , there is no need to update and you can wait for 1207 AGESA
fTPM issues are more materialized/prevalent on these two 1206 AGESA's
Sadly downgrading is no option now, well maybe
Your CPU V/F curve got changed with 1206B/C permanently ~ and SMU firmware patched

Vermeer should not get negative effects out of the SMU lock on Gen-X
but they have to push it somehow through, Patch-C is this "somehow"
Patch-B just has overclocking disabled, but it's no permanent change but an erased bios toggle
You still can OC via API & can enforce AMD CBS options via NVRAM edits


----------



## Audioboxer

Veii said:


> Hahaha
> I warned  and i'm sorry for laughing. It's a tragedy
> it's for preparation to ZenX3D
> You can't lock Vermeer down without locking Vermeer down
> 
> i would downgrade, but then you have Vermeer CO issues
> CO is the same between both B and C
> but C hardlocks OCing for Vermeer-X
> 
> Reality
> 
> i know it's very rough translated, but want to give/advice page 116 and 117 to read
> 
> 
> 
> 
> 
> 
> 
> 
> [Übersicht] - Ultimative AM4 UEFI/BIOS/AGESA Übersicht
> 
> 
> na sagen wir mal so, solange AMD noch an der AGESA bastelt und fixt, wäre es schön, wenn Asrock das auch begleitet und ggf ein letztes Bios mit letzter AGesa bringt. Zeit ist mir egal, drängt nicht, aber ein B450, welchen alle erhältlichen CPUs unterstützt, sollte auch die letzte AGESA bekommen...
> 
> 
> 
> 
> www.hardwareluxx.de
> 
> 
> 
> 
> if you don't care much about upgrading to Gen-X CPUs , there is no need to update and you can wait for 1207 AGESA
> fTPM issues are more materialized/prevalent on these two 1206 AGESA's
> Sadly downgrading is no option now, well maybe
> Your CPU V/F curve got changed with 1206B/C permanently ~ and SMU firmware patched
> 
> Vermeer should not get negative effects out of the SMU lock on Gen-X
> but they have to push it somehow through, Patch-C is this "somehow"
> Patch-B just has overclocking disabled, but it's no permanent change but an erased bios toggle
> You still can OC via API & can enforce AMD CBS options via NVRAM edits


This should easily be a bigger scandal than it currently is, the bigger names in the industry should thrive off of this sort of investigative work to chase a company and ask them what on earth they are doing to their hardware?

The 1.425v lock is, I guess, less of a   , but now, a voltage cap of around 1.2v is seriously hurting boost performance. You basically end up with a processor not as advertised. Though AMD will argue PBO is OCing and they don't support it... What a mess.

I went back to 1.2.0.5 and it seems my voltages are back to normal. I guess I'll have to do Corecycler testing again now to see if as you implied anything has permanently changed to my curve.


----------



## Veii

I've prepared quite a bit for Steve, if he wants to make a coverage
He asked long time ago if the users USB dropout issues are really gone or still a thing
But i wanted to wait for 1205
Which , well let's face it 1204-1206 had the same focus
Soo i think i need to wait till 1207 with a report
Till the time X3D is out, my trickeries hopefully push through (they did, but let's see what AMD will get up with)
And only then give him data to make a long discussion topic

Then i think my work for covering Vermeer fully is done 
Yuri will take over Zen4 as it seems, just X3D will be a questionable thing ~ if fun to work with or not
Entry price for Zen4 is too expensive for me, Vermeer was an exception & to hold promise


----------



## Audioboxer

Veii said:


> I've prepared quite a bit for Steve, if he wants to make a coverage
> He asked long time ago if the users USB dropout issues are really gone or still a thing
> But i wanted to wait for 1205
> Which , well let's face it 1204-1206 had the same focus
> Soo i think i need to wait till 1207 with a report
> Till the time X3D is out, my trickeries hopefully push through (they did, but let's see what AMD will get up with)
> And only then give him data to make a long discussion topic
> 
> Then i think my work for covering Vermeer fully is done
> Yuri will take over Zen4 as it seems, just X3D will be a questionable thing ~ if fun to work with or not
> Entry price for Zen4 is too expensive for me, Vermeer was an exception & to hold promise


Mate, if this is the future for Zen 4 I'd advise _everyone_ goes Intel


----------



## SneakySloth

Audioboxer said:


> Dropping us to 1.425v was bad enough with zero communication, so no one knows if it's a bug or not. Reducing everyone to 1.2v is just madness.
> 
> Gone back to 1.2.0.5 which has thankfully reversed these changes. Always worried when you flash a bios something changes permanently.
> 
> Now it's up to the bloggers, tech media and youtubers to... ask AMD what the hell is going on?


Could be a bug related to the bios on your specific motherboard though. I don't think we need to panic and reach conclusions without a consensus on what is happening. I'm guessing you've already tried re-flashing the bios?


----------



## Audioboxer

SneakySloth said:


> Could be a bug related to the bios on your specific motherboard though. I don't think we need to panic and reach conclusions without a consensus on what is happening. I'm guessing you've already tried re-flashing the bios?


Fair point, but given the move to begin clamping us down with 1.2.0.5, coupled with the public announcements from AMD that X3D will have no OCing/PBO at all, I think it's pretty clear where they are heading.

Someone else can report in on 1.2.0.6c as and when they want to try it, it's basically out for all MSI boards now.

Given that Veii is convinced when you flash to it you permanently change some things with your CPU, I'd rather make a PSA quickly and let people decide if they want to risk that


----------



## Veii

I certainly do not trust Patch-C
But i also do now trust less that ASUS Patch-B really is patch B and not masked patch-C, from testing i heard by @blodflekk and his Dark Hero 4004 bios, vs 4002 and 4006
Since his vermeer lockdown and PBO functioning again issues, where resolved ~ it means the SMU OC disable flag , got lifted back to Auto and then wiped from the bios
Else he should still have the same voltage lock issues ~ as real 1206 Patch-B had PBO and overclocking disabled
Soo i really do not think that ASUS marketed update 1206B , really is B but rather C

Only C should have removed the issue from Vermeer, but at the same time inject a patch against X3D (if it can even stick, as Vermeer = Vermeer)
Patch B was locked for Vermeer, Cezanne & Gen-X, but potentially the best bios for modders, as it's just a flag, not a hardlock.
It also had full support for new CurveOptimizer , new boosting system and new APU curve optimizer.
Sure it disabled overclocking, but i could push things through (also on X3D)

Yet given the report, i don't think that this is a legit Patch-B bios ASUS supplies to all their boards now
* a real 1206*B* will have the same voltage bugs and other locks that do not function with it. A Patch-*C* should not have them, but come with other new fun issues
Yet hides the 4002 which is downloadable from the servers (we backed up the bioses)
Just if "we" have to bios mod and fix this for everyone ~ it needs to make 162 bioses with at least 45min each

I'm sitting back, not leaking more information and wait how things develop till launch
They still after all chipset update attempts and bios attempts, left backdoors and their same tools can be used against them
I just sit and wait for the launch and the new bios, without reporting new trickeries.
I hope we don't "have to" bios mod for soo many boards ~ waiting is better then updating to questionable bioses now

New CO is interesting, but it doesn't bring anything for Vermeer consumer
Nothing 1204A dd not already inject, to people who updated
Powerlimit locks are annoying, surely and fully
But telemetry trickery also exists 

There are ways to circumvent their annoyances, just wait a bit
At worst, use PJVol's PBO tool , to reset and then ASUS tool 1007 to trigger an SMU reset (cold boot) + CMOS reset before anything
That should wipe potential NVRAM left nonsense from newer bioses or other SMU commands that try to stick


Veii said:


> New CO is interesting, but it doesn't bring anything for Vermeer consumer
> Nothing 1204A dd not already inject, to people who updated
> Powerlimit locks are annoying, surely and fully


Once my AMI tools method works , outside of bios modding - all 1206B iissues should resolve or generally voltage lock issues
The problem is, that there are settings predefined that block overclocking and cause all thees funny bugs
Soo give it time ~ i work on something, settings push and change, but do not stick fully yet. Something is missing

Everything is AMD CBS at the very end, and bios options are only placeholder values
Soo if menupoints or placeholder values are wiped - user still can overclock, but certainly not the easy way
Aka something else is worken on , that potentially doesn't care if AMD locks patch C or 1207 or whatever odd bios locks they want to insert or remove fully
^ and we don't have to run bios mods, which are already an annoyance by themself with the multiple signing checks ~ introduced for security

CO is on a new ID since 1206 , honestly still 1204+
Soo CO values behave a bit different now & why you should be cautious if you want to update or not - as changes are permanent as we all know
To the day,SPI pinout on the bottom of the CPUs is figured out and we can flash away their permanent changes 

EDIT:
Oh 1.1.0.0 Path *C* also *C*ensored our FCLK OC abiility with an introduced AGESA bootloader lock @ 1900FCLK
The same thing that existed on Matisse for 1.5-2 years before now old and current CPUs got it removed in 1100D ~ back to how it should be, unlocked
Current Patch-C is again such an annoying one

Actually... 
1.2.0.3 *C* also likely removed the ability for +500Mhz fMAX
(tho it was a bit earlier than that, i sadly forgot if it was pre 1200 era. Remember only that 1180 and up had the ability just got wiped instantly afterwards)
But for once was a slightly positive Patch, and fixed USB Dropdown issues
An exception to their history , haha


----------



## Blameless

Made another run at GDM disabled with my cheap CJR stuff. No luck. I did manage to get the same SCLs working, but the only way to even get it to post is to increase tRDWR to 9 from 8. Unfortunately, tRDWR is pretty big for performance, so the best timings I can do with GDM disabled at 1.4 vDIMM are slower than what I can do with GDM enabled with 1.3 vDIMM.

Sent back the worst of my OEM B-die and stuffed the best sticks in my HTPC, as they're significantly better than the old Hynix M-die that was in it.

Bit the bullet and ordered the Team T-Create 3600 CL 14 for my main system.



Veii said:


> Your CPU V/F curve got changed with 1206B/C permanently ~ and SMU firmware patched


I tested the 2.30 firmware with AGESA 1.2.0.6b on my ASRock B550 Phantom Gaming ITX-ax, didn't like it, and reverted to 1.2.0.3c.

As far as I can tell, my CO settings behave the same way and I'm still on the old 56.53.0 SMU revision.

Something has changed very recently with my CPPC core performance order, but I'm not sure that happened before or after the flash to AGESA 1.2.0.6b. I put it down to the new chipset drivers or something I simply hadn't noticed before when running CPPC enabled, but prefered cores disabled.


----------



## Audioboxer

AMD "We can't let you overclock on 5800X3D"

Also AMD "We will now stop you OCing on every other processor we've released to level the playing field" 



But it would be good if any other MSI bros can bite the bullet and confirm my findings. 1.2.0.6b definitely just follows the 1.2.0.5 behaviour.


----------



## Veii

Audioboxer said:


> Also AMD "We will now stop you OCing on every other processor we've released to level the playing field"


Can't lock Vermeer without locking Vermeer 
@Audioboxer are you on an MSI board ?
If yes, do you want to try some custom 1206B and see if your voltage lock issues are gone ?


----------



## Audioboxer

Veii said:


> @Audioboxer are you on an MSI board ?
> If yes, do you want to try some custom 1206B and see if your voltage lock issues are gone ?


MSI never released 1.2.0.6b as far as I'm aware. Unless you have something not released to the public? lol

But yes, MSI B550 Unify X.


----------



## PJVol

Veii said:


> new APU curve optimizer.


What's this?


----------



## domdtxdissar

*Basic AMD ComboAm4v2PI 1.2.0.6c testing:*

Motherboard limits: 1000w 320a 640a = way to high power limits, getting very low boosting numbers








Manual limits: 1000 180a 220a = Seems to behave like all newer amd agesa, boosting vcore limited to 1425mv max








Auto limits: 1000 320a 215a = Seems to behave like all newer amd agesa, boosting vcore limited to 1425mv max. Getting higher numbers than with manual limits above.








Auto limits + 50mv offset: 1000 320a 215a = higher ST boosting, lower MT








Auto limits + 100mv offset: 1000 320a 215a = ~same ST, even lower MT








*Compared to my daily ComboAm4v2PI 1.2.0.3c settings*

Auto limits: 1000 320a 215a = back to normal 1500mv max vcore. Getting higher ST and MT numbers in all benchmarks








Very happy this motherboard have dual bios so its easy to switch back and fourth to try new bios


----------



## Blameless

Audioboxer said:


> But it would be good if any other MSI bros can bite the bullet and confirm my findings. 1.2.0.6b definitely just follows the 1.2.0.5 behaviour.


I'm pretty sure my MSI B550 Gaming Edge Wifi and MSI B550M PRO-VDH Wifi both did, at least with regard to the CPU VID and VDDG issues.

*EDIT:* I didn't check for any 1.2v issue, just the 1425-1450mV thing at EDC over 140A.



Audioboxer said:


> MSI never released 1.2.0.6b as far as I'm aware. Unless you have something not released to the public? lol
> 
> But yes, MSI B550 Unify X.


MSI regularly releases beta firmware that they then pull...I'm sure someone archives them.

I still have one of the AGESA 1.2.0.6b firmwares for my B550M PRO-VDH.



> -------------------------------------------------------------------------------------------------------------------------------------
> B550M PRO-VDH WIFI / B550M PRO-VDH / B550M PRO-VDH WIFI6 (MS-7C95) V2.A1 BIOS Release
> -------------------------------------------------------------------------------------------------------------------------------------
> 
> 1. This is AMI BIOS release
> 
> 2. This BIOS fixes the following problem of the previous version:
> 
> Supporting upcoming CPU.
> Update to AMD ComboAm4v2PI 1.2.0.6b
> 
> 3. 2022/02/24
> 
> [Below information is Chinese language]
> 
> A. AMI BIOS ¥¿¦¡µo¦æ
> 
> B. ¦¹ª©¥»×¥¿¤U¦C°ÝÃD:
> 
> ¤ä´©·sª© CPU
> §ó·s AMD ComboAm4v2PI 1.2.0.6b
> 
> C. §ó·s¤é´Á: ¤½¤¸2022¦~2¤ë24¸¹


----------



## Audioboxer

domdtxdissar said:


> *Basic AMD ComboAm4v2PI 1.2.0.6c testing:*
> 
> Motherboard limits: 1000w 320a 640a = way to high power limits, getting very low boosting voltages, seems to match @Audioboxer's ~1200mv numbers
> View attachment 2553021
> 
> 
> Manual limits: 1000 180a 220a = Seems to behave like all newer amd agesa, boosting vcore limited to 1425mv max
> View attachment 2553022
> 
> 
> Auto limits: 1000 320a 215a = Seems to behave like all newer amd agesa, boosting vcore limited to 1425mv max. Getting higher numbers than with manual limits above.
> View attachment 2553023
> 
> 
> Auto limits + 50mv offset: 1000 320a 215a = higher ST boosting, lower MT
> View attachment 2553025
> 
> 
> Auto limits + 100mv offset: 1000 320a 215a = ~same ST, even lower MT
> View attachment 2553026
> 
> 
> *Compared to my daily ComboAm4v2PI 1.2.0.3c settings*
> 
> Auto limits: 1000 320a 215a = back to normal 1500mv max vcore. Getting higher ST and MT numbers in all benchmarks
> View attachment 2553027
> 
> Very happy this motherboard have dual bios so its easy to switch back and fourth to try new bios


Hmm, what is going on with me getting that 1.2v limit at 270/168/220? Really need someone else with a B550 to try this out.


----------



## PJVol

Blameless said:


> As far as I can tell, my CO settings behave the same way and I'm still on the old 56.53.0 SMU revision.


Can confirm, no noticeable changes between 1.2.0.3c and 1.2.0.5 on my extreme4, aside from max VID limit. Rolling back to 1.2.0.3c restored original boost behavior.
Can't say the same though about MSI B450 board. I feel something might have changed indeed after flashing 1.2.0.4 and back to 1.2.0.3c. To me it looks like the target VID for an individual core now is set too low in some specific workloads, such as those having high switching activity (i.e. FPU intensive), and hence results in loss of stability.
On the other hand, i've seen it only when core affinity is manually set, i.e. what various "core cyclers" do.
On a positive side, max.VID is the same 1.462V for 5700G on a 1.2.0.4 bios.


----------



## Audioboxer

This is me on stock, as in, 1.2.0.6c, no CPU changes in BIOS. Only thing I did was setup memory.

Voltages still terrible. Above is after a CB23 run and a CPU-Z run.

Either the B550 bios is completely messed up or I don't have an answer. Haven't found anyone else running a B550 Unify X to test.

*edit* - Oh dear, it's snapshot CPU profiling that does this. No one told me it changes how voltage is read out in HWINFO 










That being said, on 1.2.0.5 my voltage readings in HWINFO are higher with snapshot CPU profiling enabled? And dom above confirms at least something has changed for the worse.

I mean, my CB23 runs on 1.2.0.6c were like just over 30k.

Going to turn PBO on now, above 140 EDC and see what is reported.










Ooops, looks like I need to take the L on this one. Snapshot CPU polling turned off and voltages read out like how 99% of people will be running HWINFO.

So yes, 1.425v cap same as before?

My CB23 scores are definitely worse, but it appears there is not a new 1.2v cap. Although, it's quite funny dom seems to have been able to reproduce such a low voltage with really high PBO numbers.

And I still can't explain why snapshot CPU polling is showing me at like 1.2v max whereas on 1.2.0.5 the same HWINFO window is showing like 1.38v???

Nor why when I loaded a game it wasn't boosting higher than 4.7~4.8ghz on the cores whereas on 1.2.0.5 the same game happily maxes out at 5.1ghz.


----------



## Audioboxer

Ok, seems I royally screwed up on this one! Behaviour does appear to be similar to 1.2.0.5 with voltage, with the caveat that my performance is indeed worse. With snapshot CPU profiling turned on I am definitely getting a lower voltage readout than on 1.2.0.5. But with it off, it's showing the usual 1.425v max if EDC is above 140 and if not, going above that.

Oh well, I'll still blame AMD! They're making all these changes with zero communication  Perfect storm really. Me being an idiot and thinking when I turned on snapshot CPU profiling it was just about frequency and AGESA 1.2.0.6c performing worse for me, anyway.

So, I'm going back to 1.2.0.5, but feel free to test 1.2.0.6c without thinking you're getting hard locked to 1.2v.


----------



## Veii

Audioboxer said:


> MSI never released 1.2.0.6b as far as I'm aware. Unless you have something not released to the public? lol
> 
> But yes, MSI B550 Unify X.


I didn't expect, as there are bioses out for the godlike and torpedo ~ but ii'll ask around
Please reflash this and see if it boots ~ it's 1206 patch-C, sadly
I browsed but could not find any beta or unsubmitted one. Unfortunate

If it still causes you pbo or voltage issues (on stock limits and unlimited defaulting) limits
Then downgrade back
might give it another attempt, but you are sadly right


Audioboxer said:


> So yes, 1.425v cap same as before?


Maybe it's now gone after this change


Audioboxer said:


> With snapshot CPU profiling turned on I am definitely getting a lower voltage readout than on 1.2.0.5


It should be enabled from an SMU readout perspective, and core frequency perspective

Please have another usb for flashback to 1203
There can be even a rare issue where it refuses to post and hangs on debug code by the change ~ please let me know
i am not sure if M-Flash would even allow you to flash this, or flashback would
soo hence no version change to prevent potentially breaking signature - start from 1203C, to see if you can get it flashed


PJVol said:


> What's this?



















Value 0 to 30


----------



## Audioboxer

Veii said:


> I didn't expect, as there are bioses out for the godlike and torpedo ~ but ii'll ask around
> Please reflash this and see if it boots ~ it's 1206 patch-C, sadly
> I browsed but could not find any beta or unsubmitted one. Unfortunate
> 
> If it still causes you pbo or voltage issues (on stock limits and unlimited defaulting) limits
> Then downgrade back
> might give it another attempt, but you are sadly right
> 
> Maybe it's now gone after this change
> 
> It should be enabled from an SMU readout perspective, and core frequency perspective
> 
> Please have another usb for flashback to 1203
> There can be even a rare issue where it refuses to post and hangs on debug code by the change ~ please let me know
> i am not sure if M-Flash would even allow you to flash this, or flashback would
> soo hence no version change to prevent potentially breaking signature - start from 1203C, to see if you can get it flashed


Any chance of this bricking permanently or something or should flashback have me covered?


----------



## TMavica

I am using dynamic oc, 4625 4550 all core, and PBO with CO in PPT TDC EDC 200 120 140. PBO with CO I can pass the 20x ycruncher 1-7-0 test, but only got 4250 all core...If I use all core 4625 4550 only to run ycruncher, my PC got shutdown at once..but it is stable in 2 hours CB23 test and OCCT test.


----------



## Veii

Audioboxer said:


> Any chance of this bricking permanently or something or should flashback have me covered?


Flashback will have you covered
but it might not pass post or mess with memory calibration
soo have some flashback ability by hand just to be sure

Start with 1203C , to be sure you see a 1206C change
else flashback doesn't show if it refuses to flash the rom

Maybe even AFUWIN will let you update, with NVRAM erased option ~ as it usually does on MSI boards
But have something in hand to flash back


----------



## Audioboxer

Veii said:


> Flashback will have you covered
> but it might not pass post or mess with memory calibration
> soo have some flashback ability by hand just to be sure
> 
> Start with 1203C , to be sure you see a 1206C change
> else flashback doesn't show if it refuses to flash the rom
> 
> Maybe even AFUWIN will let you update, with NVRAM erased option ~ as it usually does on MSI boards
> But have something in hand to flash back


Alright, official BIOS is like 32mb by the way, the file I downloaded above is 15.6mb.

edit - My bad, just noticed its a .7z extension once .txt is removed.


----------



## Audioboxer

@Veii That file flashed OK through M-Flash. Still have the 1.425v cap though it seems!


----------



## KedarWolf




----------



## PJVol

Veii said:


> Value 0 to 30


Ah...
It was there since ... didn't recall exactly when, on my mortar titanium, (below screen is from 1.2.0.3C AG.4 and it certainly was here on AG.3 either)


----------



## Blameless

KedarWolf said:


> View attachment 2553045
> 
> 
> View attachment 2553046
> 
> 
> View attachment 2553047


Should be well-binned stuff, but damn if those heatsinks aren't the pinnacle of garishness.


----------



## KedarWolf

Blameless said:


> Should be well-binned stuff, but damn if those heatsinks aren't the pinnacle of garishness.


The silver kit was like $100 more for some reason. But I read the Royal Elite are well binned.


----------



## Audioboxer

KedarWolf said:


> The silver kit was like $100 more for some reason. But I read the Royal Elite are well binned.


More popular than gold lol

Literally the only reason to buy the RipJaws version is if you are going to watercool. The heatsinks on them are trash. I'd take gold Royal Elite over them any day if you were keeping stock heatsinks and retaining your warranty.

Check if you can do tRCDRD 14 at 3800 first. Sadly, my 3600C14 RipJaws kit could not do it. I think I was super unlucky with it.

Also @Veii I forgot to say earlier your modded BIOS had weird boosting behaviour. Seemed to lock frequency at 5.0ghz max. In case that helps you troubleshoot!


----------



## ArchStanton

KedarWolf said:


> The silver kit was like $100 more for some reason. But I read the Royal Elite are well binned.


I guess the stickers on the sticks themselves would have to be compared for us to be sure, but are they the RipJaws with more bling?








Err, @Audioboxer may have already answered my question as I was typing this.


----------



## KedarWolf

ArchStanton said:


> I guess the stickers on the sticks themselves would have to be compared for us to be sure, but are they the RipJaws with more bling?
> View attachment 2553056
> 
> Err, @Audioboxer may have already answered my question as I was typing this.


Since the time I ordered and now, the silver is $9 CAD cheaper now. But they were like $569 vs. $469 CAD 10 days ago.


----------



## Audioboxer

KedarWolf said:


> Since the time I ordered and now, the silver is $9 CAD cheaper now. But they were like $569 vs. $469 CAD 10 days ago.


Supply and demand, I guess lol. Send the gold back after a quick binning check if you would prefer silver


----------



## Farih

Slowly getting better with the help of you guys 

Vdimm = 1.525V
IOD = 1.01V
GCD = 1.00V










3 cycle's testmem5 without errors.
Will test for 5 cycle's now and 1 cycle y-cruncher.
If stable ill try to lower voltages and then test proper long cycle's and be done with this OC.

Unless you guys see more options to tighten things up?
(tFAW 16 wont boot, tRDWR lower then 10 doesn't boot either)

Edit:
Got error 10 in testmen5, upped tWRRD to 5.
Then got error 6 instantly on next test, increased SoC voltage one step and upped VDDP from 900mV to 925mV.

So far so good... Wish me luck!


----------



## Audioboxer

@Veii or anyone else who wants to, for the last piece of my "memory OCing education", from DRAM VPP Voltage down can anyone give the tldr for what each of these actually are/do?

In others news, as is always the case when I get a loop back up and running, I'm thinking about immediately disturbing it and adding my 120mm XR5 back into the action at the back here










Just invovles re-routing the outlet of the CPU to the XR5 on the rear, then from the XR5 it goes along the top into the same rear radiator the CPU outlet currently goes to.










I like how my Barrow flow meter seems to lie to me and make me feel good about my current 3x360 rads have a flow rate of 5.31l/min. So adding back the 4th 120mm XR5 should be fine 

To be fair I obviously ran the 4 of them before, the only difference now is I changed out 1 XR5 360 for an XR7 360. Which is supposed to be less restrictive.

Temps are great just now, but anyone who watercools knows what it's like, it's hard to stop tinkering. I originally removed the 120 XR5 because I wanted to try and do the GPU vertically and it would not work with spacing. Ultimately, it was my memory block that forced me to have to go horizontally with the GPU. That bottom outlet on the memory block was just too low down for the height of a 3080 waterblock.

I guess the good thing about a horizontal GPU is it allows me to throw in Agent 47 for a laugh. I actually got that as a freebie from a Eurogamer Expo a few years back.


----------



## Subut

Hello dear community, lately I’ve been trying to go for a relatively mild but rock solid overclock and have been running into halting issues. I come back to find the TM5 software has stopped running after a while without any errors. In the config I’m going for 44loops of 1usmus, with some memory settings dialed in. It sometimes succeeds in going through 44 loops and spits out the usual message but it sometimes stops running at around 20 loops for example and there’s no message box of any sort. The TM5 timer keeps proceeding but the system is idle with about 30gigs of ram available. I did not find a way to fix this and continued on as if it wasn’t happening since I was not even sure if it was a problem of my settings or a problem of the software. Probably that was a mistake for I’ve been greeted by this here message by TM5 for the first time and honestly I’m lost. What’s this even mean and what am I doing wrong. It feels like I’m chasing my own tail atm.


----------



## Audioboxer

Subut said:


> Hello dear community, lately I’ve been trying to go for a relatively mild but rock solid overclock and have been running into halting issues. I come back to find the TM5 software has stopped running after a while without any errors. In the config I’m going for 44loops of 1usmus, with some memory settings dialed in. It sometimes succeeds in going through 44 loops and spits out the usual message but it sometimes stops running at around 20 loops for example and there’s no message box of any sort. The TM5 timer keeps proceeding but the system is idle with about 30gigs of ram available. I did not find a way to fix this and continued on as if it wasn’t happening since I was not even sure if it was a problem of my settings or a problem of the software. Probably that was a mistake for I’ve been greeted by this here message by TM5 for the first time and honestly I’m lost. What’s this even mean and what am I doing wrong. It feels like I’m chasing my own tail atm.
> View attachment 2553118


Timeouts are often caused by very minor instability somewhere. First thing I'd do is if you are overclocking your CPU, turn off PBO/curve and do a TM5 run on default with the CPU.

TM5 is very sensitive to CPU boosting, if even one of your cores are unstable, TM5 will continually trigger that resulting in a core crash which then suspends TM5 in a neverending state.

If it's not the CPU then we move onto memory timings. Often tRFC is a culprit, but powerdown issues can be with voltage/resistances as well. Some of your timings look a little suspect. I'm no SR expert but there are a few I'd be changing. Still, I'd look at your CPU first if you are using PBO/OCing it.


----------



## Farih

Keep getting error 6 in Testmem5 now.
(So close to 3800mhz CL14 stable 😭)

Tried ODT from 36,9 to 40 to 43,6 ohm, no difference.

Tried SoC voltages between 1.0875 and 1.15V
Tried VDDP from 900mV to 1000mV
Tried IOD from 950mV to 1.05V

Always results in error 6. 😭

Any tips to clear up this error?


----------



## Audioboxer

Farih said:


> Keep getting error 6 in Testmem5 now.
> (So close to 3800mhz CL14 stable 😭)
> 
> Tried ODT from 36,9 to 40 to 43,6 ohm, no difference.
> 
> Tried SoC voltages between 1.0875 and 1.15V
> Tried VDDP from 900mV to 1000mV
> Tried IOD from 950mV to 1.05V
> 
> Always results in error 6. 😭
> 
> Any tips to clear up this error?


Flat 14?

Bump tRCDRD to 15 and check if that error goes away. Sadly, a 6 is often tRCDRD.


----------



## Farih

Audioboxer said:


> Flat 14?
> 
> Bump tRCDRD to 15 and check if that error goes away. Sadly, a 6 is often tRCDRD.


Thanks for the tip, it seemed to have helped.
Have set tRCDRD to 16, setting it to 15 with GDM on would have made it 16 anyways right?

Also, is it correct to say tCWl = CL minus 2?

Edit:
Ouch, tCWL at -2 CL gives dozens of errors...


----------



## Blameless

Audioboxer said:


> View attachment 2553114
> 
> 
> @Veii or anyone else who wants to, for the last piece of my "memory OCing education", from DRAM VPP Voltage down can anyone give the tldr for what each of these actually are/do?


DDR4 separated the wordline boost voltage from the main supply voltage to save power, that's what VPP is. It defaults to 2.5v and usually doesn't benefit from being changed much. I've had some memory where it helped get lower tRFC or, on Intel platforms tRFCI, but that was pretty hit or miss and pushing it too high usually just causes problems. Try up to 2.6v to see if it does anything (up to 2.75v+ should be perfectly safe, just probably not helpful).

Termination and reference voltages are normally half of vDIMM. They basically demarcate the difference between the charge level that represents a 0 and a 1 (the center of the data eye). Usually they should be left at auto or manually set to half of vDIMM. Reference voltage is trained and adjusted on the fly, so leaving it at default is usually the best bet, but some memory likes different termination voltages, especially when running near their limit.

The chipset voltages are just that. They power the X570/B550/whatever is on your board and should be left alone unless you experience an issue that might be relevant. PHY might help if you are increasing the reference/base/PCI-E clock and the main chipset voltage can sometime need a bump if you have USB issues.


----------



## Bloax

Subut said:


> Hello dear community, lately I’ve been trying to go for a relatively mild but rock solid overclock and have been running into halting issues.


The halting is most likely due to tRFC not being a multiple of 2; 352 or 350
well that, or a CPU crash due to too high a frequency

However, I'd recommend running tRAS as tCL + tRCD, tRC as tRAS + tRP, or just tRAS 30 tRC 45 in this simple case of flat 15-15-15
Then running tRFC as a multiple of tRC:
8x: tRFC: 360 tRFC2: 267 tRFC4: 165
6x: tRFC: 270 tRFC2: 201 tRFC4: 123

tCKE might also want to be 9

RRD is rather high, but that can be handled later


----------



## Audioboxer

Farih said:


> Thanks for the tip, it seemed to have helped.
> Have set tRCDRD to 16, setting it to 15 with GDM on would have made it 16 anyways right?
> 
> Also, is it correct to say tCWl = CL minus 2?
> 
> Edit:
> Ouch, tCWL at -2 CL gives dozens of errors...


It's just tCL that is impacted by GDM.

tCWL is just best matched with tCL. So set it to 14. Put tRDWR on AUTO and see what it trains at with tCWL at 14.


----------



## Farih

Audioboxer said:


> It's just tCL that is impacted by GDM.
> 
> tCWL is just best matched with tCL. So set it to 14. Put tRDWR on AUTO and see what it trains at with tCWL at 14.


Fixed error 10, then got error 6 and you helped me fix that...
Longer tests gave error 2.
Tried changing SoC, VDDP, loosening timings and everything i did resulted in a lot of error 6 again.

Went back to settings after you first helped me clear error 6 and just upped Vdim to 1.55V
No more errors, sort of stable (3 cycle testmem5, 1 cycle y-cruncher)

Do i just maybe have 1 or more very badly binned dimms? (running 4 sticks)
I mean 1.55V for 3800mhz CL14 seem excessive if i compare to other B die's


----------



## dk_mic

Audioboxer said:


> I like how my Barrow flow meter seems to lie to me and make me feel good about my current 3x360 rads have a flow rate of 5.31l/min. So adding back the 4th 120mm XR5 should be fine


I wouldn't trust the absolute readout
have you seen this? its a different model, but still..
Aqua Computer high flow NEXT Review - Much more than just an accurate flow meter. Only it can’t speak yet. | Page 3 | igor'sLAB

still very useful to have a flowmeter to just monitor it and compare flows when you change something

do you have 2 D5 pumps?


----------



## Audioboxer

dk_mic said:


> I wouldn't trust the absolute readout
> have you seen this? its a different model, but still..
> Aqua Computer high flow NEXT Review - Much more than just an accurate flow meter. Only it can’t speak yet. | Page 3 | igor'sLAB
> 
> still very useful to have a flowmeter to just monitor it and compare flows when you change something
> 
> do you have 2 D5 pumps?


Oh I don't trust it at all. My Bykski with 4 rads had me down at like 2.5l/min, 3.0l/min when I dropped to 3 rads.

Just reinstalled my 4th rad










Pending some bleeding of air it's showing 4.68l/min now.

The inside construction of the Barrow is much better than the Bykski, but that doesn't necessarily mean more accurate. It costs 2x the price of the Bykski, so I would expect, on paper, some sort of improvement with materials used.

I've ran 4 rads before off this 1 D5 pump and it was absolutely fine. I now have an XR7 instead of one of the XR5s which is less restrictive and this EK 3080 waterblock seems to have less restrictive fins than the 2080Ti Corsair waterblock I was running.

In other words, flow is fine. Temps are great. So yeah, just using it as an indication.

The Aquacomputer flow meter is like 2x the price of the Barrow and I don't think it's as aesthetically pleasing as these smaller Bykski/Barrow ones. But it is of course accurate 

Also taken the 3 Corsair MP120 Pros I bought for the roof radiator out, what a waste of money they were. They are better built than the Arctic P12s, heavier and look the part... But the noise the motor gives off is horrible above like 600~700RPM. Arctics are much more pleasing noise wise. It's mostly just air flow you can hear. At least on mine.

*Edit *- Having the 4th rad back in even with it only being a 120 definitely still knocks a few degrees off component temps.


----------



## Imprezzion

If I ever get to buying a different case I'll see if I can add a 3rd rad to my setup + a RAM block. I'd need a case that can hold a 420 top or front, a 240 somewhere else like PSU shroud or whatever, and a 360/420 on the other top/front depending where I put my current 420.

I'll ditch the push pull setup and go for single side fans so I don't have to buy new ones for the 3rd rad. Those things are expensive.. (Alpenfohn Wing Boost 3)


----------



## Audioboxer

Imprezzion said:


> If I ever get to buying a different case I'll see if I can add a 3rd rad to my setup + a RAM block. I'd need a case that can hold a 420 top or front, a 240 somewhere else like PSU shroud or whatever, and a 360/420 on the other top/front depending where I put my current 420.
> 
> I'll ditch the push pull setup and go for single side fans so I don't have to buy new ones for the 3rd rad. Those things are expensive.. (Alpenfohn Wing Boost 3)


While I have 7 QL120 fans which are totally crap and just for bling, the rest is like 10 Arctic P12's. The Arctics are soo cheap lol.

I only bought the MP 120 Pros on the basis I thought they might be a bit better than the Arctics and I'd have them as the 3 on the roof of the case as they're visible. That was a mistake. Must be the so called "magnetic bearing". Total waste of time. They are nicely made and have some weight to them, so it's a shame the noise they give off.


----------



## Imprezzion

Audioboxer said:


> While I have 7 QL120 fans which are totally crap and just for bling, the rest is like 10 Arctic P12's. The Arctics are soo cheap lol.
> 
> I only bought the MP 120 Pros on the basis I thought they might be a bit better than the Arctics and I'd have them as the 3 on the roof of the case as they're visible. That was a mistake. Must be the so called "magnetic bearing". Total waste of time. They are nicely made and have some weight to them, so it's a shame the noise they give off.


This build I run was a full ARGB rainbow barf show build for LAN's / shows for my gaming community stand / crew area but that all got cancelled due to COVID-19. I bought these fans purely because they are by far the best ARGB fans for radiators in terms of noise and static pressure. It was either these or the Lian Li ones but those cost even more and they probably wouldn't fit with the interconnect mechanism.

If I would go no RGB it would be Arctic all the way. Cheap, can get them straight from Arctic as their webshop is German and I'm dutch so fast and cheap delivery..

I tweaked my 3866 profile to actually boot 14-15-14-27 at 1.55v vDIMM and be stable enough to start TM5 without instantly BSODing so.. imma eat and see how many errors it spits out lol.

tPHYRDL is 28/28 now so at least it's the same.


----------



## TMavica

Audioboxer said:


> Timeouts are often caused by very minor instability somewhere. First thing I'd do is if you are overclocking your CPU, turn off PBO/curve and do a TM5 run on default with the CPU.
> 
> TM5 is very sensitive to CPU boosting, if even one of your cores are unstable, TM5 will continually trigger that resulting in a core crash which then suspends TM5 in a neverending state.
> 
> If it's not the CPU then we move onto memory timings. Often tRFC is a culprit, but powerdown issues can be with voltage/resistances as well. Some of your timings look a little suspect. I'm no SR expert but there are a few I'd be changing. Still, I'd look at your CPU first if you are using PBO/OCing it.


I have found out if using Asus product and installed Armoury crate, that casue timeout issue randomly, I doubt my CPU and memory is fine. I cant get rid of armoury crate, so I always do TM5 in safe mode...Also more Asus product in armoury crate, more latency penalty, for me is 7-8 ns penalty...


----------



## Imprezzion

Ok, it could've been worse? 1h25m run, 2 error 8, 1 error 10, 1 error 2. I honestly expected much worse lol. Upped vDIMM 1.55v > 1.59v, let's try again.


----------



## gameinn

If you're targeting 3600 speeds is it even worth trying to change voltages for vsoc and such or just the vdimm? I know if I was trying say 3,733+ then it would be done but leave them at auto for <= 3,600?


----------



## Imprezzion

gameinn said:


> If you're targeting 3600 speeds is it even worth trying to change voltages for vsoc and such or just the vdimm? I know if I was trying say 3,733+ then it would be done but leave them at auto for <= 3,600?


I'd even tend to say lowering them would be good at that point. On 3600 I can drop vSOC quite a lot and same goes for VDDG's. I really only need to start raising them above 3800. Even on 3733 I run lower then Auto.


----------



## dygibzygi

Hello guyz.
Here is my settings. If anyone have advice, pls let me now, thx


----------



## sonixmon

Veii said:


> I've prepared quite a bit for Steve, if he wants to make a coverage
> He asked long time ago if the users USB dropout issues are really gone or still a thing
> But i wanted to wait for 1205
> Which , well let's face it 1204-1206 had the same focus
> Soo i think i need to wait till 1207 with a report
> Till the time X3D is out, my trickeries hopefully push through (they did, but let's see what AMD will get up with)
> And only then give him data to make a long discussion topic
> 
> Then i think my work for covering Vermeer fully is done
> Yuri will take over Zen4 as it seems, just X3D will be a questionable thing ~ if fun to work with or not
> Entry price for Zen4 is too expensive for me, Vermeer was an exception & to hold promise


I never had USB drop outs but just started a few weeks ago. Mainly when at desktop/low power mode. Not much when gaming unless in spec?? I assume this is because I finally got a new vid card and it is PCI-e 4.0 (about a month ago) not sure.

Disappointed that this issue has not been resolved after all this time. Between the buggy fw and latest voltage shenanigans by AMD I believe I will be going back to team blue next time. Mainly because I feel it will be less buggy and will be Gen 2 of their big little so hopefully things are sorted and there will be good support for it by then. Unless AM5 is leaps and bounds above I don't think I will risk another situation in bug city!


----------



## Blameless

Testing my new Team TTCED432G3600HC14CDC01 stuff:









Needs a little more voltage than I'd like, but I'm pleased that tRDWR 8 will probably be stable at 3800.

The above is with 1.55v and is way too hot to be long term stable in my current setup (worst case memory temps are going to crack 60C). Since it's not practical to add much DIMM cooling to this SFF box, I'm going to try to knock off about 100mV of vDIMM while losing as little performance as possible.

Not very pleased with the heatspreaders either. I knew they were very basic, but they taper from the top and the thermal tape doesn't make full contact with the ICs. I could replace them, but that's another fair bit of work and I'd like to keep the warranty, if I can.


----------



## Subut

Audioboxer said:


> Timeouts are often caused by very minor instability somewhere. First thing I'd do is if you are overclocking your CPU, turn off PBO/curve and do a TM5 run on default with the CPU.
> 
> TM5 is very sensitive to CPU boosting, if even one of your cores are unstable, TM5 will continually trigger that resulting in a core crash which then suspends TM5 in a neverending state.
> 
> If it's not the CPU then we move onto memory timings. Often tRFC is a culprit, but powerdown issues can be with voltage/resistances as well. Some of your timings look a little suspect. I'm no SR expert but there are a few I'd be changing. Still, I'd look at your CPU first if you are using PBO/OCing it.


yes I'm running manual pbo with 300-230-230 which was coppied and pasted but I've set individual core CO offsets by testing it out myself. ill do that, reverting back to stock on pbo/co. what timings do you find suspicious? thanks.

edit:
hello, ran some stuff. found that, with or without pbo and co TM5 still sometimes stops and sometimes completes without error.


----------



## Subut

Bloax said:


> The halting is most likely due to tRFC not being a multiple of 2; 352 or 350
> well that, or a CPU crash due to too high a frequency
> 
> However, I'd recommend running tRAS as tCL + tRCD, tRC as tRAS + tRP, or just tRAS 30 tRC 45 in this simple case of flat 15-15-15
> Then running tRFC as a multiple of tRC:
> 8x: tRFC: 360 tRFC2: 267 tRFC4: 165
> 6x: tRFC: 270 tRFC2: 201 tRFC4: 123
> 
> tCKE might also want to be 9
> 
> RRD is rather high, but that can be handled later


will try these thank you. 15's 30 and 45. and trfc=8x trc. tcke is weird ive no idea


----------



## Imprezzion

I still have a lot of weirdness with 3866/1933 1:1. It _seems_ stable in stress testing for hours but then it will also totally randomly BSOD on a cold boot with a page fault out of nowhere for example. Or just lock up applications randomly. Like Chrome suddenly becoming unresponsive or a game C2D's with a 0xc05 in event viewer.. No WHEA's logged either.

This doesn't happen on 3733/1866 with the same PBO settings and the CPU survived 50h combined of Corecycler on 3733/1866 in this curve so that should be fine..


----------



## Farih

Been trying to get Dram voltage down while keeping 3800mhz CL14.

Loosened and tightened a few timings and got this in the end:










Vdimm = 1.54V
VDDG GCD = 1.00V
Dimm2 gets 45c degrees, other dimms between 38.5 and 42c.
(no active cooling, will get 2x 40mm or 2x 60mm fans for it soon)

tRRDS to 4 and then tFAW to 16 doesnt boot, not with 1.58V either.
tCWL to 12 or 13 gives errors.
Lower tRDWR gives error 12 in testmen5.

Any tips and tricks (especially if it could make me run lower Vdimm) or am i pretty much done now?


----------



## Phlereous

I am pretty new to OC so I've had many issues so far. It's a masochistic practice but I keep coming back to it.
At first I was running 3800/1900 but I got thousands of WHEA 19 errors. I got some advice and updated BIOS. WHEA's were gone but now I can't boot the PC with 1900 FCLCK. I can do 3800 with the ram still. If that is something that can be fixed, I would love to know how. 
For now I gave up on higher frequencies and started working on timings, using the famous guide on github. I couldn't do tCL 14 @1.4 VDIMM but I got it on 1.5.
I lowered tRCDs next and I boot but TM5 anta7777 extreme gives hundreds of errors. I read on a reddit post that someone had the same problem and solved it by increasing SOC to 1.15 from 1.1 so I tried that but it didn't work.
So that is where I am at now.


----------



## Blameless

Spent all night eating brownies and tuning memory...down from 1.55v here to 1.47v on this Team T-Create:

























Not quite the full 100mV reduction I was looking for, but I'll take it.

Already passed 10 loops (~3.5 hours) of a custom 1usmus_v3 TM5 run, with case fans at 2/3rds normal RPM and the GPU mining to dump heat on the DIMMs. Going to run a bit more y-cruncher HNT (tough on memory and less than perfect COs) before cycling through some other tests. Will probably finish off with a 24 hour TM5 run + FurMark (capped to 350w).

Changes from my previous, less stable, much hotter, settings:

Applied some more finesse, rather than brute force, with the drive strengths, RttNom, and ProcODT.
Loosened tRAS (tRCDWR + tWR + tCWL seems to work well for me, as a baseline) and tRC, which actually took more voltage to stabilize, but performs more consistently than my previous settings; they were probably so tight that they were closing their respective windows before bursts could finish. Will reevaluate tRAS again later.
Loosened all primaries by one. Tried getting away with just tRDC and tRP, then just tCL, but all three needed to be 15 for me to hit the voltage (under 1.5v) and stability (unconditional/absolute) targets I was looking for.
Tightened the subs that still had low-hanging fruit, which compensated for most of the lost performance, without harming stability.
Bumped CLDO VDDP back up to 880mV to consistently train 26/26 tPHYRDL.

Performance wise vs. my old CJR stuff, which is now my test bench's default, I've gained about ~3% in 7-zip, ~1.5% in y-cruncher, and a rather significant ~8% in WinRAR. Will take a look at gaming performance later; not expecting miracles, but every little bit helps.



Farih said:


> Been trying to get Dram voltage down while keeping 3800mhz CL14.
> 
> ...
> 
> Any tips and tricks (especially if it could make me run lower Vdimm) or am i pretty much done now?


I was in the same position, but the best option turned out to be tightening subs and loosening CL.

You may also want to give GDM disabled 2T another shot. I'm having much more success with it on my moderately well-binned stuff than I did with cheaper memory.



Phlereous said:


> View attachment 2553262
> 
> 
> 
> I am pretty new to OC so I've had many issues so far. It's a masochistic practice but I keep coming back to it.
> At first I was running 3800/1900 but I got thousands of WHEA 19 errors. I got some advice and updated BIOS. WHEA's were gone but now I can't boot the PC with 1900 FCLCK. I can do 3800 with the ram still. If that is something that can be fixed, I would love to know how.
> For now I gave up on higher frequencies and started working on timings, using the famous guide on github. I couldn't do tCL 14 @1.4 VDIMM but I got it on 1.5.
> I lowered tRCDs next and I boot but TM5 anta7777 extreme gives hundreds of errors. I read on a reddit post that someone had the same problem and solved it by increasing SOC to 1.15 from 1.1 so I tried that but it didn't work.
> So that is where I am at now.


FCLK issues might be resolved with CLDO VDDG tuning, but if you were getting huge numbers of errors at 1900MHz, your chip probably just doesn't want to do it.

tRC is way too high (should always be tRAS+tRP, and if it can't be, it's a clue that tRAS is too low). tRRDL might be too tight. tWR is usually best left at double tRTP. tRTP itself can probably be tightened. tWRRD might benefit from being loosened to 3 or 4.

Rtts and drive strengths would probably benefit from some work. I like to boot into Memtest86 at the lowest vDIMM practical and use test #8 to quickly evaluate these. In general, you want as few errors as possible, and those errors to be failing higher and lower than the "expected" result at roughly equal proportions.


----------



## Imprezzion

I tried literally every timing, RTT's, ProcODT tweaks, drive strengths and such to get tPHYRDL to train on 3733 CAS14 1T GDM Off but nothing works. Whatever I do it's always 26/28 on an even CAS number. Uneven always trains 26/26. So weird...


----------



## Blameless

Imprezzion said:


> I tried literally every timing, RTT's, ProcODT tweaks, drive strengths and such to get tPHYRDL to train on 3733 CAS14 1T GDM Off but nothing works. Whatever I do it's always 26/28 on an even CAS number. Uneven always trains 26/26. So weird...


CLDO VDDP (and perhaps CPU VDDP, which usually likes to be set to the same value) can influence tPHYRDL.

Board can also play a large part. Lower/matching values have been much easier for me to reliably achieve on my two-slot only boards and my cheapest four-slot boards are especially bad.


----------



## Phlereous

Blameless said:


> tRC is way too high (should always be tRAS+tRP, and if it can't be, it's a clue that tRAS is too low). tRRDL might be too tight. tWR is usually best left at double tRTP. tRTP itself can probably be tightened. tWRRD might benefit from being loosened to 3 or 4.
> 
> Rtts and drive strengths would probably benefit from some work. I like to boot into Memtest86 at the lowest vDIMM practical and use test #8 to quickly evaluate these. In general, you want as few errors as possible, and those errors to be failing higher and lower than the "expected" result at roughly equal proportions.


Thank you. I will try your suggestions. Are they going to help with tRCD problems or just what to tighten in general?
I have no idea how to even start working on Rtts and the drive strengths. Is there a guide or something I can learn from?


----------



## Blameless

Phlereous said:


> Are they going to help with tRCD problems or just what to tighten in general?


More along the lines of general suggestions. tRCDRD below 14 is quite demanding, but tRCDWR should tighten to 8-10 without issue.



Phlereous said:


> I have no idea how to even start working on Rtts and the drive strengths. Is there a guide or something I can learn from?


I find that 6/3/3 for Rtts (40/80/80 ohm) and 40/24/30/24 for the drive strengths is usually a good place to start for dual-rank B-die, but optimal settings, especially for the latter, will vary considerably.

@Veii has some good advice for drive strength tuning: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## Farih

Blameless said:


> I was in the same position, but the best option turned out to be tightening subs and loosening CL.
> 
> You may also want to give GDM disabled 2T another shot. I'm having much more success with it on my moderately well-binned stuff than I did with cheaper memory.


I can do 3800mhz CL16 flat with tighter subtimings at just 1.42V but i just want me Cl14! 

Just need to get a fan or 2 to cool them (hottest dimm gets to 45c)
If i can get them under 40c i dont mind running 1.55V 24/7 tbh, might even go for 1.6V if i can keep them cool.

Btw, your latency is a good chunk lower then mine (mine is 63.4) is that purely the difference between a 3700x and 5800x?


----------



## Blameless

Farih said:


> Btw, your latency is a good chunk lower then mine (mine is 63.4) is that purely the difference between a 3700x and 5800x?


Precise memory timings and background tasks can have an impact, but yes, it's mostly the difference between Matisse and Vermeer.


----------



## Phlereous

Blameless said:


> I find that 6/3/3 for Rtts (40/80/80 ohm) and 40/24/30/24 for the drive strengths is usually a good place to start for dual-rank B-die, but optimal settings, especially for the latter, will vary considerably.


Tyvm. I checked the post you linked as well. I will give them a try today. How do I know if they are working better or worse though? From what I gather they are useful to stabilize OC so I should be able to lower a timing I was failing TM5 with before? 
In other words, how do I know if it works or makes a difference at all after changing?


----------



## Bloax

In my experience, then the biggest impact RTT/CADBus settings have is making the memory very deterministic in how performance scales.

e.g. each tCL or 100 MCLK step becoming +/- 0.06v*, tRCD being +/- 0.09v*, up until the memory or the memory controller can't handle it.
and yes, there's a difference in "can't handle it" between "passes a 2-minute benchmark, sometimes" handle it - and "doesn't error for 6 hours" handle it

* this varies, whether from individual stick to individual stick (i.e. pure silicon lottery), or PCB to PCB (same scaling within the same product line, lottery for Base Voltage/Max Performance), I don't have enough samples to tell you


----------



## Blameless

Hot testing, one hour in:











Phlereous said:


> How do I know if they are working better or worse though? From what I gather they are useful to stabilize OC so I should be able to lower a timing I was failing TM5 with before?
> In other words, how do I know if it works or makes a difference at all after changing?


Once you have settled on a competent preset for your memory, CPU, and desired settings, test it.

Personally, I like to use Memtest86 to get a relatively quick idea of what termination and drive strength values are likely to be optimal, without risking corrupting the OS. Test #8, or tests #7 & #8, are good for this.

Fire up the tests, and if there are no errors, reduce vDIMM until you start to encounter some. Note the 'expected' vs. 'actual' result. If you are consistently seeing errors where 'actual' are predominantly lower or higher than 'expected' it's a sign your drive strengths may be incorrect, or not matched to termination. With correct drive strengths, errors should be almost an even mix, at least over the long run, of higher and lower than 'expected'...the main exception being if tRFC is too low or temps are way too high. Other than that, keep an eye on error rate...tune settings until errors are eliminated at a given voltage, then reduce voltage until they appear again. Once you can't eliminate the last errors, bump voltage one notch and test a few more times, with cold and warm boots between. Assuming you still have no errors, bump voltage once more, then boot into Windows for more intensive testing. You may well need to increase voltage again, as Memtest86 is not the most strenuous test, but you should be able to quickly dial in solid drive strengths and termination resistances.

Once you get some experience it's generally possible to infer which way things need to go. Keep in mind that drive strengths are output impedance; the lower the resistance, the stronger they are...this drives more current, which causes voltage to spike faster, but can also result in overshoot. Working against this are the termination values (they are listed as 240 ohm divided by _n_); higher resistance here absorbs more energy, dampening reflections, but that energy has to go some where, so it becomes heat. Too much termination resistance require more current draw than needed and can result in signals bottoming out. It's a balancing act that depends a lot on the properties of the ICs being used.


----------



## Farih

Blameless said:


> Hot testing, one hour in:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Once you have settled on a competent preset for your memory, CPU, and desired settings, test it.
> 
> Personally, I like to use Memtest86 to get a relatively quick idea of what termination and drive strength values are likely to be optimal, without risking corrupting the OS. Test #8, or tests #7 & #8, are good for this.
> 
> Fire up the tests, and if there are no errors, reduce vDIMM until you start to encounter some. Note the 'expected' vs. 'actual' result. If you are consistently seeing errors where 'actual' are predominantly lower or higher than 'expected' it's a sign your drive strengths may be incorrect, or not matched to termination. With correct drive strengths, errors should be almost an even mix, at least over the long run, of higher and lower than 'expected'...the main exception being if tRFC is too low or temps are way too high. Other than that, keep an eye on error rate...tune settings until errors are eliminated at a given voltage, then reduce voltage until they appear again. Once you can't eliminate the last errors, bump voltage one notch and test a few more times, with cold and warm boots between. Assuming you still have no errors, bump voltage once more, then boot into Windows for more intensive testing. You may well need to increase voltage again, as Memtest86 is not the most strenuous test, but you should be able to quickly dial in solid drive strengths and termination resistances.
> 
> Once you get some experience it's generally possible to infer which way things need to go. Keep in mind that drive strengths are output impedance; the lower the resistance, the stronger they are...this drives more current, which causes voltage to spike faster, but can also result in overshoot. Working against this are the termination values (they are listed as 240 ohm divided by _n_); higher resistance here absorbs more energy, dampening reflections, but that energy has to go some where, so it becomes heat. Too much termination resistance require more current draw than needed and can result in signals bottoming out. It's a balancing act that depends a lot on the properties of the ICs being used.


What is your RAM voltage at? and how hot do your dims get?


----------



## Phlereous

Blameless said:


> Personally, I like to use Memtest86 to get a relatively quick idea of what termination and drive strength values are likely to be optimal, without risking corrupting the OS. Test #8, or tests #7 & #8, are good for this.
> 
> Fire up the tests, and if there are no errors, reduce vDIMM until you start to encounter some. Note the 'expected' vs. 'actual' result. If you are consistently seeing errors where 'actual' are predominantly lower or higher than 'expected' it's a sign your drive strengths may be incorrect, or not matched to termination. With correct drive strengths, errors should be almost an even mix, at least over the long run, of higher and lower than 'expected'...the main exception being if tRFC is too low or temps are way too high. Other than that, keep an eye on error rate...tune settings until errors are eliminated at a given voltage, then reduce voltage until they appear again. Once you can't eliminate the last errors, bump voltage one notch and test a few more times, with cold and warm boots between. Assuming you still have no errors, bump voltage once more, then boot into Windows for more intensive testing. You may well need to increase voltage again, as Memtest86 is not the most strenuous test, but you should be able to quickly dial in solid drive strengths and termination resistances.
> 
> Once you get some experience it's generally possible to infer which way things need to go. Keep in mind that drive strengths are output impedance; the lower the resistance, the stronger they are...this drives more current, which causes voltage to spike faster, but can also result in overshoot. Working against this are the termination values (they are listed as 240 ohm divided by _n_); higher resistance here absorbs more energy, dampening reflections, but that energy has to go some where, so it becomes heat. Too much termination resistance require more current draw than needed and can result in signals bottoming out. It's a balancing act that depends a lot on the properties of the ICs being used.


So I should be able to boot whatever frequency and timings I want w/o messing with RTT/CAD bus and then use them to stabilize and clear errors? 
Sorry if I am not understanding, as I said, this is my first time trying this so I am trying to ELI5 it for myself.


----------



## Audioboxer

Phlereous said:


> Tyvm. I checked the post you linked as well. I will give them a try today. How do I know if they are working better or worse though? From what I gather they are useful to stabilize OC so I should be able to lower a timing I was failing TM5 with before?
> In other words, how do I know if it works or makes a difference at all after changing?


If things are stable then they're working fine, it's kind of that basic.

I used to run 7/3/3 on DR but thanks to Veii discovered 4 on RttPark was fine. Generally speaking it seems running Park as weak as you can may help with thermals. So I run 7/3/4 now.

DrvStr has been a bit more static for me. 40 is basically mandatory on ClkDrvStr to get 1T working. The others have varied a bit. Doing a 50 cycle of TM5 produced 1 error for me related to powerdown that got cleaned up changing CkeDrvStr from 24 to 30. That may not be needed for you though, most people seem to be fine running 24.

It's a bit of trial and error. Your own individual memory and motherboard are likely to cause some minor variance between what someone online tells you to try. So the long and short of it is if it works, it works. You'll find wherever you settle is likely similar to advice online, but when it comes to resistances don't take it as guaranteed what other DR users state will work for you.

That's the fun of memory OCing, you have to put the work in to find out what your kit likes 😜

For example right now I'm trying my hardest to see if I can stabilise above 1.65v at full capacity. I've had a go before and failed. Back to playing with all the resistances in combinations that are not usually used. Takes a lot of time to try, as many errors come a reasonable amount of time into a run. I'll probably still fail again, but if you don't try you don't have a chance!

But there are times you just have to accept no combination is going to brute force something you're aiming for. Limitations do sadly exist. tRCDRD, I'm looking at you 💀


----------



## Blameless

Farih said:


> What is your RAM voltage at? and how hot do your dims get?


vDIMM is 1.47.

No temp sensor on these, but inferring from the hottest part of the heat spreader, the ICs have to be reaching ~65C.


----------



## Imprezzion

Blameless said:


> CLDO VDDP (and perhaps CPU VDDP, which usually likes to be set to the same value) can influence tPHYRDL.
> 
> Board can also play a large part. Lower/matching values have been much easier for me to reliably achieve on my two-slot only boards and my cheapest four-slot boards are especially bad.


Tried both on like 15 different values and combinations but nothing.

This board + RAM just only does tPHYRDL training properly on 3733 on either even timings GDM on or uneven GDM Off. CAS 15 is fine, 14 is 26/28, 13 is fine again. And it really doesn't matter what I change, as long as it's 1T GDM Off it will not in any way train a even CAS. Even as loose as 3733C18 does 28/30 just to spite me.

If only I could run 3800 flat.. which I can't cause this CPU has a dumb FCLK hole at 1900 and can't POST 1900.. 1933 works fine but on 3866 I can't run CAS 14 anymore at voltages that are reasonable.

Only other option I have is 3666C13 but I'm afraid that costs too much bandwidth.

EDIT: even booting 3733 13-15-13 to Windows without issues requires 1.640v vDIMM. There's no way I will ever get that stable..

My only other maybe option is 3933c15. If I can get the CPU to run 1966 FCLK properly. Which is also a major question mark.


----------



## Audioboxer

Imprezzion said:


> Tried both on like 15 different values and combinations but nothing.
> 
> This board + RAM just only does tPHYRDL training properly on 3733 on either even timings GDM on or uneven GDM Off. CAS 15 is fine, 14 is 26/28, 13 is fine again. And it really doesn't matter what I change, as long as it's 1T GDM Off it will not in any way train a even CAS. Even as loose as 3733C18 does 28/30 just to spite me.
> 
> If only I could run 3800 flat.. which I can't cause this CPU has a dumb FCLK hole at 1900 and can't POST 1900.. 1933 works fine but on 3866 I can't run CAS 14 anymore at voltages that are reasonable.
> 
> Only other option I have is 3666C13 but I'm afraid that costs too much bandwidth.
> 
> EDIT: even booting 3733 13-15-13 to Windows without issues requires 1.640v vDIMM. There's no way I will ever get that stable..
> 
> My only other maybe option is 3933c15. If I can get the CPU to run 1966 FCLK properly. Which is also a major question mark.


My MSI board does weird tPHYRDL things as well. I'm at 1T/3800 just now and it's 26/26 with tCL13. If I change to tCL14, it ends up 28/26.

Basically, if I want to run 1T I need an uneven tCL. If I run an even tCL it prefers 2T.

Never found a way to really figure this out, just ends up being what it is. SetupTiming definitely seems to play a role, but DR basically needs that to survive 1T/GDM disabled.


----------



## Imprezzion

Audioboxer said:


> My MSI board does weird tPHYRDL things as well. I'm at 1T/3800 just now and it's 26/26 with tCL13. If I change to tCL14, it ends up 28/26.
> 
> Basically, if I want to run 1T I need an uneven tCL. If I run an even tCL it prefers 2T.
> 
> Never found a way to really figure this out, just ends up being what it is. SetupTiming definitely seems to play a role, but DR basically needs that to survive 1T/GDM disabled.


Yeah I have to run 56 setup otherwise no chance.
It behaves exactly the same for me as you described but for me it's on 3733. 

3933/1966 straight 15's boots fine but it absolutely rains WHEA's. 22 in just 1 AIDA 64 memory and cache run and that isn't something a bit of voltage tweaks will magically solve so. Guess I'm stuck at whatever frequency with a uneven tCL and so far the most efficient combination was definitely 3866 C15 as I simply cannot run C13 even on 3733.


----------



## Taraquin

After a bit of testing I found that lowering TDC from 60 to 50 and EDC from 90 to 75 and set scalar to 1x performance is the same in CB/gaming using stock 76W PPT, but temp and noise became significantly better. CPU still boost to allcore 4.65GHz in CB (below 70C, 4.6GHz if 71-72C) but uses about 30mv less at single and allcore boost. In SC loads temp dropped by 5C, in allcore 2C using same fancurve.


----------



## Farih

Angled one of the fans from my CPU cooler towards the RAM and now my temperature's don't go above 38c in stress tests and not above 35c in gaming 

Was able to tighten timings a little bit more.
Sadly bandwidth and latency stays the same, think i have reach the limit of what this CPU can handle 😭

Lowering tWR to 14/12 and PC wont boot anymore.
Setting tRDWR/tWRRD to 8/2 or 8/4 results in everlasting boot loops.
Lowering tRFC to 256 works but lowering to 252 and PC wont boot anymore, so i kept it at 264. (6x tRC)

Anything else i can do to push latency down and/or make then need less voltage? (without loosing performance)

Vdimm = 1.55V
4x 8GB G.Skill Ripjaws 3600 cl16


----------



## Audioboxer

Farih said:


> Angled one of the fans from my CPU cooler towards the RAM and now my temperature's don't go above 38c in stress tests and not above 35c in gaming
> 
> Was able to tighten timings a little bit more.
> Sadly bandwidth and latency stays the same, think i have reach the limit of what this CPU can handle 😭
> 
> Lowering tWR to 14/12 and PC wont boot anymore.
> Setting tRDWR/tWRRD to 8/2 or 8/4 results in everlasting boot loops.
> Lowering tRFC to 256 works but lowering to 252 and PC wont boot anymore, so i kept it at 264. (6x tRC)
> 
> Anything else i can do to push latency down and/or make then need less voltage? (without loosing performance)
> 
> Vdimm = 1.55V
> 4x 8GB G.Skill Ripjaws 3600 cl16
> View attachment 2553437


Run SCLs at 4. Change tCWL to 14 and put tRDWR on AUTO.

I would advise turning off GDM, but that might require a rework of your whole profile.


----------



## Farih

Audioboxer said:


> Run SCLs at 4. Change tCWL to 14 and put tRDWR on AUTO.
> 
> I would advise turning off GDM, but that might require a rework of your whole profile.


Ill give those settings a try later tonight.

I tried with GDM off when i was still running 2 dims.
Then i could only do 3600mhz cl14 and 3800mhz cl16.
Now with 4 dims i don't think it would be any better.


----------



## Blameless

Making some more progress on my timings for this T-Create B-die.

Relative to my prior settings:

Reduced procODT to 28.2 and output impedance/drive strengths to 60/30/30/30 without problems.

Attempted RttPark of /4 (60 ohm), but that was extremely unstable. Reverted back to /3.

1T command rate looks like it will work, but only with AddrCmdSetup delay of ~56. It does improve performance though, so I'll probably use it.

I tested tRP again after dialing in my Rtts and drive strengths and I can lower it to 12 at 2T or 13 at 1T. Very minor, but consistent performance improvement.

SCLs of 2 and 3 work, but 3 does nothing at all, and 2 helps a small handful of tests slightly, but hurts others. Leaving this at 4.

tRRD_L at 4 works, but does almost nothing for performance and requires more voltage/cooling than 6.

tWTR_L of 10 vs 12, same deal as tRRD_L.

tWRRD at 2 seems fine.

tRFC below 256 is a no go without a significant voltage increase.

tRCDRD needs a moderate voltage increase to be stable at 14, while tCL needs a large voltage increase. Not practical for me to run either without better cooling.

Looks like I'm probably going to wind up using 3800MT/s 15-15/8-13-35-48-1T(56 addrcmd) with tight subs at 1.46v.

Testing stability now.


----------



## Blameless

Had to tear apart my furnace and clean the flame sensor to get stable enough temps to continue testing (temperature dropped about 30C over the weekend and my furnace was alternating between not running, and trying to raise temps too much in one go), but I think I'm very near dialing in final settings at this point.

Decided to use the lower tRRD_L and tWTR_L after all, as I do have temperature headroom at 1.46 vDIMM...just not when my furnace is blasting ~50C air directly into my case while it's fans are at minimum speed.

This is what I'm at now (w/ 1.46 vDIMM):









Still testing stability.

Also, first time I've cracked 42k in WinRAR on an eight-core:









That's a full ~12% faster than my CJR kit.


----------



## MrHoof

You could also give RTTs 7/2/6 a try gave me a little thermal headroom before errors start to show over 7/3/3 but both are 100% stable at lower then 47°C form me.


----------



## Blameless

Ran into what was almost certainly a temperature related error a few hours into TM5. Trying the looser _L settings and 10mV more vDIMM.



MrHoof said:


> You could also give RTTs 7/2/6 a try gave me a little thermal headroom before errors start to show over 7/3/3 but both are 100% stable at lower then 47°C form me.


7/2/6 won't POST for me. Indeed, any RttPark in excess of 4 fails to start and 4 is flaky enough to not always pass training.


----------



## MrHoof

Ye Park is somehow related to WR.
7/3/4 no post for me but dropping WR to 2 allows for me park 6 maybe try park 5 as is 7/2/5.

edit:


Spoiler: my timings


----------



## Blameless

MrHoof said:


> Ye Park is somehow related to WR.
> 7/3/4 no post for me but dropping WR to 2 allows for me park 6 maybe try park 5 as is 7/2/5.
> 
> edit:
> 
> 
> Spoiler: my timings
> 
> 
> 
> 
> View attachment 2553474


What vDIMM is that?

I'm functionally limited to sub-1.5v (temperature scales rapidly after this point) and whatever timings I use still have to work at 60-70C.

This is an SFF system with a ~400w 6800 XT in it that has no room for watercooling, no dedicated memory air flow, that has to work in ~35C ambients.

Edit: If all else fails, I'll try less output impedance on Clk and AddrCmd to see if that lets me increase RttPark.

Right now I'm trying up to 1.49 vDIMM and hoping the stability provided by extra voltage outpaces the increase in temperature. I've found my thermal limit at 1.47v and would like to get a little more margin.


----------



## Grift

Hi guys I recently added 2x8GB to my existing 2x8GB, any suggestion on how to fix my current setup?

4x DIMM F4-3600C19-8GSXWB (Two different batches but same thaiphoon readout)
TM5 with 1usmus profile @ 10 cycles (Takes around 1hr 20min)


RoundRound 11247541218Round 2512378121314781Round 3121219854612571213147814310Round 478512211378121071414



Spoiler: Taiphoon

















Spoiler: ZenTimings


----------



## Blameless

Ended up reverting my ProcODT to 32 ohm and my AddrCmdDrvStr to 24 ohm. This improved training consistency a bit and _dramatically_ increased the temperature tolerance of this kit. I don't want to jinx it, but the room I'm in is almost too hot for me to tolerate, I've got a solid GPU load going, fans are below the speed I normally allow them to ramp up to, and TM5 is still chugging away after two hours, so far.



Grift said:


> Hi guys I recently added 2x8GB to my existing 2x8GB, any suggestion on how to fix my current setup?
> 
> 4x DIMM F4-3600C19-8GSXWB (Two different batches but same thaiphoon readout)
> TM5 with 1usmus profile @ 10 cycles (Takes around 1hr 20min)
> 
> 
> RoundRound 11247541218Round 2512378121314781Round 3121219854612571213147814310Round 478512211378121071414
> 
> 
> 
> Spoiler: Taiphoon
> 
> 
> 
> 
> View attachment 2553484
> 
> 
> 
> 
> 
> 
> Spoiler: ZenTimings
> 
> 
> 
> 
> View attachment 2553485


I would try somewhat lower voltage. 1.42v is about where most CJR stops scaling and some like less. Try 1.35v or so. Also, Rtts and DrivStr might benefit from some adjustment. Try enabling RttWr (/3 to start) and if that doesn't help, combine it with RttPark of 2-4. Drive strengths of 30/24/30/30, 40/30/30/30, or even 60/30/30/30 might help, but I don't have a lot of experience with quad single rank 8Gb CJR setups, so that's mostly a guess.


----------



## Farih

Audioboxer said:


> Run SCLs at 4. Change tCWL to 14 and put tRDWR on AUTO.
> 
> I would advise turning off GDM, but that might require a rework of your whole profile.


Doing this then tRDWR on auto gives a value of 18.
Was able to then manually set tRDWR to 8 and tWRRD to 4

Gives slightly higher bandwidth (from 56850 to 57000) but also slightly worse latency. (from 63.3 to 63.4)

Ill keep SCL's at 4 and see if i can get tCWL down as well.


----------



## Audioboxer

Farih said:


> Doing this then tRDWR on auto gives a value of 18.
> Was able to then manually set tRDWR to 8 and tWRRD to 4
> 
> Gives slightly higher bandwidth (from 56850 to 57000) but also slightly worse latency. (from 63.3 to 63.4)
> 
> Ill keep SCL's at 4 and see if i can get tCWL down as well.


tCWL going down really isn't worth it. Best to have tRDWR as low as it can go.


----------



## Taraquin

Audioboxer said:


> tCWL going down really isn't worth it. Best to have tRDWR as low as it can go.


Dxtdomdissar tested this a while back, if I remember correct RDWR has more impact on perf than CWL, but lower CWL might make it hard to run RDWR as low, can't have them both  

If CL is 14 and CWL is 14 you may do RDWR 8, but if you lower CWL to 12, you may need to raise RDWR to 9. The first option generally performs best.


----------



## Farih

Setting back tCWL from 12 to 14 gave me more headroom to play with other settings.
Problem is just that its really hard to see what's performing better and i think its because my CPU just cant handle more/faster memory.
Is there anything more accurate (and about just as quick) then Aida64?

So far i got 3 cycle's error free in TM5 with these settings:

1.55V
Temps on hottest dim never exceed more then 38c.









Not to shabby for 4x SR dims.


----------



## Taraquin

Farih said:


> Setting back tCWL from 12 to 14 gave me more headroom to play with other settings.
> Problem is just that its really hard to see what's performing better and i think its because my CPU just cant handle more/faster memory.
> Is there anything more accurate (and about just as quick) then Aida64?
> 
> So far i got 3 cycle's error free in TM5 with these settings:
> 
> 1.55V
> Temps on hottest dim never exceed more then 38c.
> View attachment 2553508
> 
> 
> Not to shabby for 4x SR dims.


Rtp should be half wr so 6, and scls tends to be more stable and perform better at 4. Maybe you can run rcdrd 15 then?


----------



## Farih

Taraquin said:


> Rtp should be half wr so 6, and scls tends to be more stable and perform better at 4. Maybe you can run rcdrd 15 then?


Trying tRTP at 6 now.










BRB. testing for stability.


----------



## Grift

Blameless said:


> Ended up reverting my ProcODT to 32 ohm and my AddrCmdDrvStr to 24 ohm. This improved training consistency a bit and _dramatically_ increased the temperature tolerance of this kit. I don't want to jinx it, but the room I'm in is almost too hot for me to tolerate, I've got a solid GPU load going, fans are below the speed I normally allow them to ramp up to, and TM5 is still chugging away after two hours, so far.
> 
> 
> 
> I would try somewhat lower voltage. 1.42v is about where most CJR stops scaling and some like less. Try 1.35v or so. Also, Rtts and DrivStr might benefit from some adjustment. Try enabling RttWr (/3 to start) and if that doesn't help, combine it with RttPark of 2-4. Drive strengths of 30/24/30/30, 40/30/30/30, or even 60/30/30/30 might help, but I don't have a lot of experience with quad single rank 8Gb CJR setups, so that's mostly a guess.


30c ambient on my side  not much luck with 1.35v, even when I was running 3600 2x8 I was on 1.37v 24/24/24/24 0/0/5. All clobbered together from various sources but it worked. Currently have a 140mm fan pointed on the sticks as well.


----------



## Imprezzion

Even with a 120mm at 1000rpm pointed at my sticks they get to like, 46c cause my front intake rad hot air blows directly into them and also feeds the fan. If I turn the fan off it goes straight to 60c so.. 

@Blameless you're basically on my exact primary timings. I run 3866 15-8-15-13 but with different tRAS tRC and tRFC. 30-45-270. I had good luck for stability and training with ProcODT 34.3 and RTT's at Off/2/3. That is by far the most stable setup I can get. 

My tCWL is 14 and rdwr 9. Would tCWL 15 allow me to run 8 maybe?


----------



## Farih

Think I'm gonna stop tweaking memory now.
Everything i do/change doesn't show any difference in benchmark and i think its because my CPU just cant keep up.
Got some room to up Vdim voltage some more but its kinda pointless if i dont see any changes in results 

Hopefully i can get a 5800x3d or 5900x in 1-2 months and see how far i can really get this kit.


----------



## MrHoof

Blameless said:


> What vDIMM is that?
> 
> I'm functionally limited to sub-1.5v (temperature scales rapidly after this point) and whatever timings I use still have to work at 60-70C.
> 
> This is an SFF system with a ~400w 6800 XT in it that has no room for watercooling, no dedicated memory air flow, that has to work in ~35C ambients.


Thats 1.55v also in a "SSF" case but a bigger one NR200 so I had space for 120mm fan pointing at the RAM and my GPU is only a 6600xt max 150w and avg while gaming 80-90w.


----------



## kim nk

Audioboxer said:


> My MSI board does weird tPHYRDL things as well. I'm at 1T/3800 just now and it's 26/26 with tCL13. If I change to tCL14, it ends up 28/26.
> 
> Basically, if I want to run 1T I need an uneven tCL. If I run an even tCL it prefers 2T.
> 
> Never found a way to really figure this out, just ends up being what it is. SetupTiming definitely seems to play a role, but DR basically needs that to survive 1T/GDM disabled.


It seems to be a feature of double-sided memory, not just an msi problem.
Asus motherboards also operate as tphyrdl 28 for even cl. Again, if it is changed to 2t, it is tphyrdl 26/26 , and as you said, real 1t is changed to tphyrdl 26 when an odd number cl is used

2t cl14 tphyrdl 26/26








1t cl14 tphyrdl28/26








1t cl13 tphyrdl 26/26









Also, when trdwr is lowered to 8, an increase in tphyrdl of 30/28 is also observed.


----------



## Imprezzion

kim nk said:


> It seems to be a feature of double-sided memory, not just an msi problem.
> Asus motherboards also operate as tphyrdl 28 for even cl. Again, if it is changed to 2t, it is tphyrdl 26/26 , and as you said, real 1t is changed to tphyrdl 26 when an odd number cl is used
> 
> 2t cl14 tphyrdl 26/26
> View attachment 2553521
> 
> 1t cl14 tphyrdl28/26
> View attachment 2553520
> 
> 1t cl13 tphyrdl 26/26
> View attachment 2553522


So I'm not the only one with this lol. I use ASUS btw. A B550-XE. Such a shame. tCL 14 is exactly the sweet spot for most B-Die kits at 3800.. I mean, I can push tCL 13 at 3733, my bin is pretty bad so no way it'll do 13 on 3866, but that needs like 1.64v vDIMM and I can barely cool 1.55v as it is.


----------



## Audioboxer

kim nk said:


> It seems to be a feature of double-sided memory, not just an msi problem.
> Asus motherboards also operate as tphyrdl 28 for even cl. Again, if it is changed to 2t, it is tphyrdl 26/26 , and as you said, real 1t is changed to tphyrdl 26 when an odd number cl is used
> 
> 2t cl14 tphyrdl 26/26
> View attachment 2553526
> 
> 1t cl14 tphyrdl28/26
> View attachment 2553527
> 
> 1t cl13 tphyrdl 26/26
> View attachment 2553522
> 
> 
> Also, when trdwr is lowered to 8, an increase in tphyrdl of 30/28 is also observed.
> View attachment 2553525


The question then becomes is this a manufacturer/BIOS design issue, or just something that will happen with all DR memory?

It makes absolutely no sense to me why 3800tCL13 will do 26/26 with ease, but 3800tCL14 it's a challenge to get it to 28/28 rather than 26/28.


----------



## kim nk

Imprezzion said:


> So I'm not the only one with this lol. I use ASUS btw. A B550-XE. Such a shame. tCL 14 is exactly the sweet spot for most B-Die kits at 3800.. I mean, I can push tCL 13 at 3733, my bin is pretty bad so no way it'll do 13 on 3866, but that needs like 1.64v vDIMM and I can barely cool 1.55v as it is.


Timing yield and voltage yield are usually different, even with the same b-die, there is a difference of more than 0.1v. The board difference was also reduced to 1.59v when the timing that was 1.62v in UniFy-x was transferred to the Dark Hero board. The board difference doesn't seem to be overlooked either. Of course, the memory voltage yield is also different from the timing yield, and it seems to be a lucky draw .. ㅠㅠ


----------



## kim nk

Audioboxer said:


> The question then becomes is this a manufacturer/BIOS design issue, or just something that will happen with all DR memory?
> 
> It makes absolutely no sense to me why 3800tCL13 will do 26/26 with ease, but 3800tCL14 it's a challenge to get it to 28/28 rather than 26/28.


It seems like both sides of the ram are like that. In terms of latency, real cl14 1t 28/26 with tight timing and cl14 real 2t with tight timing, real 2t shows more constant and lower latency, but real 1t with tphyrdl 28/26 is not constant and has a higher latency than 2t. Similar, but slightly behind

Cl14 Tphyrdl26/26 real 2t








Cl14 tphyrdl 28/26 real 1t









This is the average latency returned 10 times.

The read and copy bandwidth of 1t seems to be much higher, but the latency result is definitely 50.3ns for 2t, but 1t 28/26 is unstable at 50.3~50.7ns, and the latency is rather increased

And if you configure the timing like this, it becomes 28/28. Decrease tcwl and increase trdwr .. I thought that tphyrdl 26/26 would be possible if tcwl was an odd number instead of cl, so the result was a failure
Tphyrdl 28/28


----------



## Imprezzion

We need someone with a Gigabyte or EVGA board to test this as well.

I could do it, I can loan a Gigabyte X570 Ultra from a buddy, but I can't be bothered to strip my entire loop for this haha. 

Maybe I can grab my RAM and put it in his X570 Ultra + 5800X and see if that behaves..


----------



## Taraquin

Imprezzion said:


> We need someone with a Gigabyte or EVGA board to test this as well.
> 
> I could do it, I can loan a Gigabyte X570 Ultra from a buddy, but I can't be bothered to strip my entire loop for this haha.
> 
> Maybe I can grab my RAM and put it in his X570 Ultra + 5800X and see if that behaves..


I have never get my board to train above 26 on 3800cl15 1t, 4000cl16 1t or 1t gdm. Always 26.


----------



## Imprezzion

Taraquin said:


> I have never get my board to train above 26 on 3800cl15 1t, 4000cl16 1t or 1t gdm. Always 26.


The thing is, is is 26/28 or 26/26. The problem we're having is GDM Off 1T at an even tCL is always 26/28. And that costs performance. I run tCL 15 which is fine at 26/26 but as soon as I go to tCL 14 it's always 26/28 and will not train no matter what.


----------



## kim nk

This is another 64gb 16x4 , to achieve both tphyrdl 26 you have to upload this procodt to know for sure


----------



## Mach3.2

kim nk said:


> It seems to be a feature of double-sided memory, not just an msi problem.
> Asus motherboards also operate as tphyrdl 28 for even cl. Again, if it is changed to 2t, it is tphyrdl 26/26 , and as you said, real 1t is changed to tphyrdl 26 when an odd number cl is used
> 
> 2t cl14 tphyrdl 26/26
> View attachment 2553526
> 
> 1t cl14 tphyrdl28/26
> View attachment 2553527
> 
> 1t cl13 tphyrdl 26/26
> View attachment 2553522
> 
> 
> Also, when trdwr is lowered to 8, an increase in tphyrdl of 30/28 is also observed.
> View attachment 2553525


Same behavior on my single rank 16Gb Micron Rev. Bs as well.



Mach3.2 said:


> Seem like it's an MSI thing;
> odd tCL + 1T = tPHYRDL 26/26
> even tCL + 1T = tPHYRDL 26/28 or 28/28(?)
> 
> odd tCL + 2T = tPHYRDL 26/28 or 28/28(?)
> even tCL + 2T = tPHYRDL 26/26


----------



## Taraquin

Imprezzion said:


> The thing is, is is 26/28 or 26/26. The problem we're having is GDM Off 1T at an even tCL is always 26/28. And that costs performance. I run tCL 15 which is fine at 26/26 but as soon as I go to tCL 14 it's always 26/28 and will not train no matter what.


I have 4000cl16 gdm off 1t now  My ram is incapable of running cl14 at 3800 so can't check that.


----------



## Imprezzion

Taraquin said:


> I have 4000cl16 gdm off 1t now  My ram is incapable of running cl14 at 3800 so can't check that.


So, gigabyte doesn't seem to have this issue based on sample size of 1


----------



## Taraquin

Imprezzion said:


> So, gigabyte doesn't seem to have this issue based on sample size of 1




















Atleast some GB-boards don`t it seems. I have SR and this is a 2dimm motherboard. Can anyone else with SR B-die compare? Any with ITX\other 2dimm MBs?


----------



## Blameless

Hot testing with new settings on this Team kit @ 1.47 vDIMM passed:









VRM and SSD temps paint a pretty good picture of board temp, and the coldest HDD is 3-5C above case/intake ambient.

Temps several C lower than those peaks were failing in about an hour at ProcODT 28.2.



Imprezzion said:


> My tCWL is 14 and rdwr 9. Would tCWL 15 allow me to run 8 maybe?


For whatever reason, I can't POST with odd tCWL, on this setup, irrespective of GDM. If you can run 15 it's probably worth a shot as tRDWR has a much larger performance impact than tCWL.



Mach3.2 said:


> Same behavior on my single rank 16Gb Micron Rev. Bs as well.





kim nk said:


> It seems to be a feature of double-sided memory, not just an msi problem.


Almost all the dual-rank memory I've used that could reach 3800 would also reliably train to 26/26, virtually irrespective of CL. My current Team B-die stuff does it on CL 14 and 15 just fine. My cheap Timetec CJR did it at CL 18 just fine. Even my 2x32GiB dual-rank HyperX with 16Gb Micron B-die...26/26. Tested mainly in my ASRock B550 Phantom Gaming ITX, but also in my Gigabyte X570 Elite. ProODT doesn't seem to matter for PHY training on my ASRock board either.

My MSI B550M PRO-VDH does like to train to 28/28 or 28/26 and I've never seen 26/26 on it past 3600 or so. However, I'm not sure if this is an 'MSI thing' or the fact that this is a ~90USD four-layer board with a dubious memory VRM. It also only allows weirdly bad tRFC and is generally a poor memory OCer, so I put it down to the physical properties of the board itself, but I suppose it could be firmware.

I do have another MSI board, but it's got a 3700X in it that won't do 1800 FCLK and can't really be disassembled for testing.


----------



## MrHoof

Well my ASUS Strix 570i (2dimm itx) also does not have this even tCL problem only time I encounter it is if vddp is to low as in below 0.9v. But increasing vddp does not help others as tested in the past so I dunno whats going on here. 
But also I seem to be the only one able to run tRDWR 7.


Spoiler: true 1T 26/26 3800 tCL 14


----------



## Blameless

MrHoof said:


> Well my ASUS Strix 570i (2dimm itx) also does not have this even tCL problem only time I encounter it is if vddp is to low as in below 0.9v. But increasing vddp does not help others as tested in the past so I dunno whats going on here.
> But also I seem to be the only one able to run tRDWR 7.
> 
> 
> Spoiler: true 1T 26/26 3800 tCL 14
> 
> 
> 
> 
> View attachment 2553550


Could be the kit, could be the board, or a combination of the two.

I had an ASUS Crosshair VIII Impact that died more than a year ago, but while it was running it could do almost magical things with memory. Took some major adjustments, and usually a performance regression, to get the same memory stable in other boards.

Currently, my ASRock ITX will train 26/26 reliably with 870 or 880mV VDDP, but I cannot run tRDWR 7 or 1T without AddrCmdSetup, not at any sane voltage anyway.


----------



## mongoled

Well here are my single rank dimm results, these are my 24/7 settings, if it helps anyone









@Blameless, that Team kit sure looks nice

😃 😃


----------



## Audioboxer

Mach3.2 said:


> Same behavior on my single rank 16Gb Micron Rev. Bs as well.


Definitely blaming MSI.

I have a B550, so 2 DIMM, prior to X570s Unify ranked one of the best boards for memory, and 4000C14 DR, one of the best DR kits, still does 28/26 at 3800 tCL14/1T.

Though with enough tinkering I've managed to force it to 28/28 some times.

Never seen 26/26 at tCL14. Whereas at tCL13/1T it will run 26/26 no matter what. Even down at AUTO VSOC, 0.9v VDDP and ProcODT 28.2 lmao.

So the harder to run tCL doesn't even break a sweat. Even with some of the weakest powering on the resistances/voltages.

From a "newbies" perspective, that makes ZERO sense.


----------



## Blameless

mongoled said:


> Well here are my single rank dimm results, these are my 24/7 settings, if it helps anyone
> 
> View attachment 2553562
> 
> 
> @Blameless, that Team kit sure looks nice
> 
> 😃 😃


I've got a pair of the same Patriot Vipers in one of my Zen 2 systems. Haven't really been able to push them.

This Team kit is proving to be solid for the money, though I wish they'd either have used more functional heatsinks or left them off entirely. At leat they aren't tall enough to get in the way of anything.


----------



## Imprezzion

Blameless said:


> I've got a pair of the same Patriot Vipers in one of my Zen 2 systems. Haven't really been able to push them.
> 
> This Team kit is proving to be solid for the money, though I wish they'd either have used more functional heatsinks or left them off entirely. At leat they aren't tall enough to get in the way of anything.


You could always slap on a couple of alpha cool heat spreaders or something.

I also need AddrCmdSetup 56 to run true 1T but it's super solid that way. I'll try to see if I can post uneven tCWL, haven't tried yet. 

There is one kit I kinda wanna try to get my hands on if I can somehow find it.

CMT32GX4M2Z4000C16 Dominator dual-rank. I love the look of the Domi's but they are hard to find in stock and if they are they go for like €325 so. Not very well priced..


----------



## Blameless

Imprezzion said:


> There is one kit I kinda wanna try to get my hands on if I can somehow find it.
> 
> CMT32GX4M2Z4000C16 Dominator dual-rank. I love the look of the Domi's but they are hard to find in stock and if they are they go for like €325 so. Not very well priced..


These were in stock (on both Newegg and Amazon in the US, IIRC) around the same price as this Team stuff when I was trying to decide what kit to get. I was tempted by it, but the heatspreaders are tall enough to block a fair portion of the intake air flow to my CPU cooler and I suspect the Team is similarly binned.


----------



## kim nk

For double-sided memory, it is better to use 26/26 2t than tphyrdl 26/28 1t in terms of performance. Also, the stability is 2t consistent and there is no latency fluctuation. 1t tphyrdl 28/26 gave 50.3ns but this 50.3ns is more consistent and more consistent at 2t and 1t stretches to 50.7ns.


















Tphyrdl 26/26 2t









4200 tphyrdl 28 2t









This is a single-sided 16 gigabyte tphyrdl 24/26

Simplex memory is easy with tphyrdl 24/26.

The way to do double-sided memory tphyrdl 26/26 seems to be the odd cl and 2t right now


----------



## KedarWolf

kim nk said:


> For double-sided memory, it is better to use 26/26 2t than tphyrdl 26/28 1t in terms of performance. Also, the stability is 2t consistent and there is no latency fluctuation. 1t tphyrdl 28/26 gave 50.3ns but this 50.3ns is more consistent and more consistent at 2t and 1t stretches to 50.7ns.
> 
> View attachment 2553621
> 
> View attachment 2553620
> 
> 
> Tphyrdl 26/26 2t
> View attachment 2553622
> 
> 
> 4200 tphyrdl 28 2t
> View attachment 2553623
> 
> 
> This is a single-sided 16 gigabyte tphyrdl 24/26
> 
> Simplex memory is easy with tphyrdl 24/26.
> 
> The way to do double-sided memory tphyrdl 26/26 seems to be the odd cl and 2t right now
> View attachment 2553624


How do you check both values are at 26/26. I only see tPHYRDL in Zen Timings.


----------



## kim nk

KedarWolf said:


> How do you check both values are at 26/26. I only see tPHYRDL in Zen Timings.


check like this


----------



## KedarWolf

kim nk said:


> check like this
> View attachment 2553626


Thank you. I have 26/26, but I'm pretty sure my BIOS settings I use trick it into that. Never mind the BIOS settings. It's 26/26 no matter what latency enhance settings I use.

And I get better AIDA64 with Latency Enhance disabled and below it on Auto.


----------



## Blackfyre

I recently saw someone mention in this forum that it's useless to have the value of *tFAW* below 16, since it should be 4 x the value of *tRRDS* and *tRRDL.*

I previously had:
tRRDS at 4, 
tRRDL at 6, 
and tFAW at 14

*Changed them to 4, 4, and 16* after reading that advice. Are there any other RAM timings that are linked in that way? Here are my ZTimings below, any advice regarding what else to tighten or shift?

FYI tRFC, tRFC2, and tRFC4 at pretty much the lowest I can go with my 4 x Micron-E Die running overclocked at 3800Mhz 14CL (default is 3600Mhz CL16).


----------



## Taraquin

Blackfyre said:


> I recently saw someone mention in this forum that it's useless to have the value of *tFAW* below 16, since it should be 4 x the value of *tRRDS* and *tRRDL.*
> 
> I previously had:
> tRRDS at 4,
> tRRDL at 6,
> and tFAW at 14
> 
> *Changed them to 4, 4, and 16* after reading that advice. Are there any other RAM timings that are linked in that way? Here are my ZTimings below, any advice regarding what else to tighten or shift?
> 
> FYI tRFC, tRFC2, and tRFC4 at pretty much the lowest I can go with my 4 x Micron-E Die running overclocked at 3800Mhz 14CL (default is 3600Mhz CL16).
> View attachment 2553632


Rtp x 2=wr
Ras+rp=rc
Rfc should be divideable by 8 on 8gb kits, by 16 on 16gb kits, for you 544 or 536 are good values, 540 also work, but will perform equal to 544, but harder to run. 528 can give a bit better perf, but might not run. 

I would set rtp to 7, try lower rc if possible, 54-56 may work, and adjust ras so that ras+rp=rc. 

I have a 3000cl15 rev E kit on my 12400F. Can't run above 3600, but 15-19-19-34 rc 53 520 rc works.


----------



## Blackfyre

Taraquin said:


> Rtp x 2=wr
> Ras+rp=rc
> Rfc should be divideable by 8 on 8gb kits, by 16 on 16gb kits, for you 544 or 536 are good values, 540 also work, but will perform equal to 544, but harder to run. 528 can give a bit better perf, but might not run.
> 
> I would set rtp to 7, try lower rc if possible, 54-56 may work, and adjust ras so that ras+rp=rc.
> 
> I have a 3000cl15 rev E kit on my 12400F. Can't run above 3600, but 15-19-19-34 rc 53 520 rc works.


Thank you! And if not too much trouble, please use the full names. *I figured rtp x 2 = wr* is (tRPT x 2 = tWR). So mine should be *12* x 2 = *24*

I can't figure out Ras + rp = rc Nevermind, I got it. Thanks.

rfc I figured, so they should be divisible by 8. I don't think 528 would work, as anything lower than 540 I tried in the past crashed. But maybe once I've fixed other timings I will have more leeway.

Would appreciate if you could use the names from ZTimings, case sensitive, so I can find them easier.


----------



## Taraquin

Blackfyre said:


> Thank you! And if not too much trouble, please use the full names. *I figured rtp x 2 = wr* is (tRPT x 2 = tWR). So mine should be *12* x 2 = *24*
> 
> I can't figure out Ras + rp = rc
> 
> rfc I figured, so they should be divisible by 8. I don't think 528 would work, as anything lower than 540 I tried in the past crashed. But maybe once I've fixed other timings I will have more leeway.
> 
> Would appreciate if you could use the names from ZTimings, case sensitive, so I can find them easier.


WR should be equal to or below CL so lower RTP, not WR  Try 14/7. Try RFC 536 or go up to 544.

Try RAS 42 + RP 12 = RC 56, if it doesn't work try RAS and RC 1 or 2 up, lower might also work.


----------



## Blackfyre

Taraquin said:


> WR should be equal to or below CL so lower RTP, not WR  Try 14/7. Try RFC 536 or go up to 544.
> 
> Try RAS 42 + RP 12 = RC 56, if it doesn't work try RAS and RC 1 or 2 up, lower might also work.


Haven't stress tested yet, just booted. But Yeah 536 worked and I think I done RAS + RP = RC correctly now. And 14/7 for rtp & wr


----------



## Taraquin

Blackfyre said:


> Haven't stress tested yet, just booted. But Yeah 536 worked and I think I done RAS + RP = RC correctly now. And 14/7 for rtp & wr
> 
> View attachment 2553635


Sorry, my mistake, RAS 44  You can also try RAS+RP=RC 
43+12=55 
42+12=54

Test with testmem5. On my rev E typically one RC value is stable, 1-2 lower gives lots of errors, 1 lower than that won't boot, example:
3600 ram 53 is fine, 52 gives errors, 51 won't boot. 

Run new tests to see if performance is better. 

You should also try disabling gear down mode, but this might require some tuning. 

You SOC voltage is a bit high, your IOD voltage is a bit low, I would consider raising IOD to 1.0v and lowering SOC to 1.12v.


----------



## Blackfyre

Taraquin said:


> Sorry, my mistake, RAS 44  You can also try RAS+RP=RC
> 43+12=55
> 42+12=54
> 
> Test with testmem5. On my rev E typically one RC value is stable, 1-2 lower gives lots of errors, 1 lower than that won't boot, example:
> 3600 ram 53 is fine, 52 gives errors, 51 won't boot.
> 
> Run new tests to see if performance is better.
> 
> You should also try disabling gear down mode, but this might require some tuning.
> 
> You SOC voltage is a bit high, your IOD voltage is a bit low, I would consider raising IOD to 1.0v and lowering SOC to 1.12v.


Alright thanks will change IOD and SOC.

So for example:

There are zero benefits to doing (tRP = 12) *+* (tRAS = 36) *=* (tRC +56). Even though RAS is much lower and it works, there are no benefits at all?


----------



## Taraquin

Blackfyre said:


> Alright thanks will change IOD and SOC.
> 
> So for example:
> 
> There are zero benefits to doing (tRP = 12) *+* (tRAS = 36) *=* (tRC +56). Even though RAS is much lower and it works, there are no benefits at all?


From what I have read there is none, possible worse performance if they are not matched since RC is defined by RAS+RP.


----------



## Blackfyre

Taraquin said:


> From what I have read there is none, possible worse performance if they are not matched since RC is defined by RAS+RP.


Alright thank you, any other recommendations you would make? I done 12 + 41 = 53 and booted fine. I tried to lower tRFC from 536 to 528 and it didn't boot.


----------



## Taraquin

Blackfyre said:


> Alright thank you, any other recommendations you would make? I done 12 + 41 = 53 and booted fine. I tried to lower tRFC from 536 to 528 and it didn't boot.
> View attachment 2553636


Looks very good now, you can try WR 12/RTP 6 or 10/5, but may not be faster, and is harder to run  My rev E could only do 15-20-11 rc 58 and rfc at 536 at 3800 so you have a better bin than me. Test again with aida and see if scores are better?


----------



## ManniX-ITA

Well, I have put in the 2nd brand new B2 5950X in.
It's even worse than the previous one.
The only good aspect so far is that it doesn't seem broken and didn't destroyed my Windows install.

Compared to the previous one it shares almost all the aspects of the poor binning.

The best/2nd best cores are 0 & 1 *and core 1 doesn't pass CC 720K at Stock.*
Not even the others can pass reliably the 10 minutes run, I had to set a positive vCore offset of 25mV.
But Core 1 was failing between immediately and 2 minutes.
Had to set a positive offset +2 to make it pass.

Limited boost clock overall, especially on the good cores.
In general low performances, had to struggle a lot to get it close to the old B0.

Compared to the previous B2 it doesn't like any change to VDD18.
And it doesn't run FCLK 2000 without a 1 second regression on y-c pi25b.
Score are also generally lower than the previous B2.

I guess that's why AMD dropped the price, it's garbage now.

Compared to the 5800X that can run FCLK2000 it's massively inferior up to 8/12 threads.

B0 vs B2
















And this is with almost everything still to test with CoreCycler.
The B0 was fully tested.

I will not even bother to send it back even if it doesn't pass at stock.
It's so similarly bad binned as the previous one that I'm pretty sure I'll never get something much better.
Plus I'm fed up of this bitching and swapping.
Next good thing comes out, probably from Intel, and I'll sell it.


----------



## ArchStanton

@ManniX-ITA I am sorry to hear of your findings, but I cannot claim to be surprised. My own experience with 5950X (3) was very similar. I was late to acquiring the X570 platform, and the Silicon Lottery Faries punished me for my slothful ways. I don't know what AMD is currently doing with the "best" Zen3 cores, but I am convinced they are no longer installing them in "vanilla" Ryzen 5000.

edited for grammar


----------



## Bix

ManniX-ITA said:


> It's even worse than the previous one.


That's so frustrating, it's such a ****show I can't blame you for not bothering with another RMA. They've just received my 5900x and I'm holding out very little hope for the replacement.


----------



## ManniX-ITA

ArchStanton said:


> I am sorry to hear of your findings, but I cannot claim to be surprised. My own experience with 5950X (3) was very similar. I was late to acquiring the X570 platform, and the Silicon Lottery Faries punished me for my slothful ways. I don't know what AMD is currently doing with the "best" Zen3 cores, but I am convinced they are no longer installing them in "vanilla" Ryzen 5000.


It's honestly the first time that I see so widespread worse binning on something that is in production for so long.
Especially for a top tier product which is expected to be better and improving over its lifetime.
There's only one explanation and is that instead of using the good parts of the wafer, the inner layers, they are now using the outer layers.
I guess they are favoring the GPU dies from where they can make a lot of money.
But even considering this, the worsening is so bad that I guess nothing has been done to optimize the process and thus nothing changed on B2.
Which is very uncommon and scary. They are not doings things right.


----------



## ArchStanton

ManniX-ITA said:


> There's only one explanation and is that instead of using the good parts of the wafer, the inner layers, they are now using the outer layers.
> I guess they are favoring the GPU dies from where they can make a lot of money.


As the owner of a 6900 XT that is a total beast, I find this perfectly consistent with my experience to date.


----------



## dk_mic

Well I had a 2046 SUS B0 5950X which I used for a year or so, unstable at stock. RMA'ed into a 2201 SUS B2 and it has a platinum/silver rating by Hydra. I think, it's still just silicon lottery, and the stepping really has nothing to say.


----------



## ManniX-ITA

dk_mic said:


> 2201 SUS B2 and it has a platinum/silver rating by Hydra. I think, it's still just silicon lottery, and the stepping really has nothing to say.


Rating from Hydra is a bit different topic.
Got for the same sample a Platinum rating on a board and Bronze on another.
More interested in the boost clocks and the CO counts to judge the quality.

There's always a silicon lottery.
But the new cuts are usually including all the design and fabrication node optimizations from the learning of the previous one.
Which should result in a more consistent better binning and performances.
Seems that for the B2 this hasn't been done.
My guess is they have been working 100% on the next thing and 0% on the current one.
Fair, their company.
But I'm considering putting 0% of my money on their next thing


----------



## The_King

Hey Guys need some help with a new B-Die Kit I bought today. Patriot Viper 4400Mhz. So first off I have run several different Crucial E Die kits and they all hit 3600 CL14 easily even though my system is a first gen Ryzen 1700X running on a B450M Mortar MAX.

So I expected this B-die kit to do at least 3600 CL14 or even 16-16-16 but no. lol. This is my first B-die kit and compared to REV. E its driving me crazy.
By some fluke when I first installed the RAM it did boot 3600 CL14 and I only did two AIDA64 runs one at stock CPU clocks and one OC'd.
















Now the RAM will not boot 3600 at any voltage or any timings. It only does 3400 CL14 anything above this now fails to post.









I have never changed *Drvstr etc I always left those on AUTO. Any help to get this B-Die Kit to 3600 CL14 or CL16 to boot will be highly appreciated.


----------



## Rexbag

The_King said:


> Hey Guys need some help with a new B-Die Kit I bought today. Patriot Viper 4400Mhz. So first off I have run several different Crucial E Die kits and they all hit 3600 CL14 easily even though my system is a first gen Ryzen 1700X running on a B450M Mortar MAX.
> 
> So I expected this B-die kit to do at least 3600 CL14 or even 16-16-16 but no. lol. This is my first B-die kit and compared to REV. E its driving me crazy.
> By some fluke when I first installed the RAM it did boot 3600 CL14 and I only did two AIDA64 runs one at stock CPU clocks and one OC'd.


You've got the money to be upgrading your perfectly good RAM but not to upgrade your CPU from the 1700 to something more recent?

I'd guess you'd see far more improvement with even a 5600 and your old RAM versus the 1700x and the new RAM, even considering you figure out how to get it running at a tighter 3600MT/s profile. That's assuming there's a bios for your motherboard to support Zen 3. I'd assume on a B450 the answer would be Yes, but I don't know it as a fact.


----------



## emreesvs

Hi everyone I overclocked my memory and my Igpu with some help but I'm new and I just want to know are this values okay for daily use and gaming. I already complete a couple TM5 Absolut test without error, ı'm using pc with this settings almost 2 week. Last night I started and stress test in aida (but I forgot it) after 2 hours my cpu was saw 80 degrees max. I have ID cooling se224xt.


----------



## Audioboxer

ManniX-ITA said:


> Well, I have put in the 2nd brand new B2 5950X in.
> It's even worse than the previous one.
> The only good aspect so far is that it doesn't seem broken and didn't destroyed my Windows install.
> 
> Compared to the previous one it shares almost all the aspects of the poor binning.
> 
> The best/2nd best cores are 0 & 1 *and core 1 doesn't pass CC 720K at Stock.*
> Not even the others can pass reliably the 10 minutes run, I had to set a positive vCore offset of 25mV.
> But Core 1 was failing between immediately and 2 minutes.
> Had to set a positive offset +2 to make it pass.
> 
> Limited boost clock overall, especially on the good cores.
> In general low performances, had to struggle a lot to get it close to the old B0.
> 
> Compared to the previous B2 it doesn't like any change to VDD18.
> And it doesn't run FCLK 2000 without a 1 second regression on y-c pi25b.
> Score are also generally lower than the previous B2.
> 
> I guess that's why AMD dropped the price, it's garbage now.
> 
> Compared to the 5800X that can run FCLK2000 it's massively inferior up to 8/12 threads.
> 
> B0 vs B2
> View attachment 2553664
> View attachment 2553665
> 
> 
> And this is with almost everything still to test with CoreCycler.
> The B0 was fully tested.
> 
> I will not even bother to send it back even if it doesn't pass at stock.
> It's so similarly bad binned as the previous one that I'm pretty sure I'll never get something much better.
> Plus I'm fed up of this bitching and swapping.
> Next good thing comes out, probably from Intel, and I'll sell it.


The more I hear about B2 the more I hug my B0 lol.


----------



## The_King

Rexbag said:


> You've got the money to be upgrading your perfectly good RAM but not to upgrade your CPU from the 1700 to something more recent?
> 
> I'd guess you'd see far more improvement with even a 5600 and your old RAM versus the 1700x and the new RAM, even considering you figure out how to get it running at a tighter 3600MT/s profile. That's assuming there's a bios for your motherboard to support Zen 3. I'd assume on a B450 the answer would be Yes, but I don't know it as a fact.


There is absolutely no reason for me to upgrade my 1700X its still way overkill for my daily usage and gaming needs. The B-Die Kit was on sale and usually way overpriced in my country.
No point in upgrading to 5600X now when the 5700X and other newer AMD CPUs are around the corner. The IMC on my 1700X is pretty good compared to most, I was even able to boot 3933Mhz single channel and 3667Mhz Dual channel that was with all my Rev E Kits. Even a Dual Rank 32GB Kit runs 3600 CL14 which is not bad for a 1700X























My motherboard fully supports all Zen 3 CPUs it will even support the newer AMD CPUs launching next month.
Anyway I was looking for someone with expert knowledge on B-Die kits to help with getting 3600 to work / post not financial advice .


----------



## VPII

Look I won't say that I know everything or am an expert with regards to memory on an AMD Ryzen platform. So a month or two ago I decided to sell my two sets of 2 x 8GB G-Skill Flare X DDR4 3200 CL14 kits for about half of the price of a new set of G-Skill Trident Z Royal 2 x 16GB DDR4 3600 CL14 as in 14 14 14 34. Now this memory works well without an issue, but the subtimings I used with my previous set will not work or is not stable. At present I am running it 3800, as with my previous sets at 16 16 16 34, but I cannot do this without Gear Down disabled which was possible with the previous sets. I am okay with the performance but I am not sure if I may be missing something. So that is why I am posting it here for maybe some advice. Below is my numbers at present, I had the timings latency is the 59 mark with this memory before but Aida is somewhat behhh at times. Anyways, some help would be appreciated even if it does not work. Thanks you.


----------



## ArchStanton

@VPII I run a very similar kit with these settings.



















I plagiarized these settings from another poster here on OCN. They are not truly "tuned" to my system, but I have thoroughly tested them, and they run without error. I'm on my phone, so I won't be able to go into detail.


----------



## Anhphe93

Before that i was able to run stable TRRDS-TRRDL-TFAW as: 4-4-16 on my old 5600x with bus 4000
Unfortunately my new 5900x couldn't stabilize at FCLK 2000 so I had to drop to 3800.
If TFAW 16 I always get 0 error on TM5 immediately, I tried everything to fix it but no success. Can someone give me advice on what to do? TFAW below 32 will give me error 0 in TM5.


----------



## ArchStanton

@Anhphe93 what is your vDIMM? Also, can you actively cool your RAM? I ask because I remember reading somewhere that increasing vDIMM was the most common solution to TM5 error 0. I'm a total newb with RAM tuning though, so I apologize if my suggestion is incorrect.


----------



## Anhphe93

ArchStanton said:


> @Anhphe93 what is your vDIMM? Also, can you actively cool your RAM? I ask because I remember reading somewhere that increasing vDIMM was the most common solution to TM5 error 0. I'm a total newb with RAM tuning though, so I apologize if my suggestion is incorrect.


I used 1.45vdim i tried going higher but the error still occurs. only when TFAW is 32 or higher there is no more error 0. that's weird


----------



## The_King

I sorted some of my issues out. Turns out this Kit it fuzzy about what voltage you use. It would not post 3600 CL16 @ 1.45V but posted no issues with 1.4V.


----------



## Blackfyre

@Taraquin I passed 3 and 10 cycles of 1usmus_v3 on TestMem yesterday and assumed it was stable. Overnight I put it on 20 cycles and woke up to the PC restarted. So it must have crashed between 10 and 20. 

I loosened a few of the timings (tRAS = 42 & tRC = 54, and RFC settings + 8 on each) and decreased the voltage to 1.48 instead of 1.52 (in case it was a heat issue over time), will do more tests tonight. Might run 40 cycles of 1usmus_v3 just to be sure, that should be fine yeah? I've never run more than 10 cycles before to check for stability of RAM.


----------



## Taraquin

Blackfyre said:


> @Taraquin I passed 3 and 10 cycles of 1usmus_v3 on TestMem yesterday and assumed it was stable. Overnight I put it on 20 cycles and woke up to the PC restarted. So it must have crashed between 10 and 20.
> 
> I loosened a few of the timings (tRAS = 42 & tRC = 54, and RFC settings + 8 on each) and decreased the voltage to 1.48 instead of 1.52 (in case it was a heat issue over time), will do more tests tonight. Might run 40 cycles of 1usmus_v3 just to be sure, that should be fine yeah? I've never run more than 10 cycles before to check for stability of RAM.
> View attachment 2553758


Rare reboots is usually RFC. Hopefully 544 will be stable


----------



## dk_mic

ManniX-ITA said:


> Rating from Hydra is a bit different topic.
> Got for the same sample a Platinum rating on a board and Bronze on another.
> More interested in the boost clocks and the CO counts to judge the quality.
> 
> There's always a silicon lottery.
> But the new cuts are usually including all the design and fabrication node optimizations from the learning of the previous one.
> Which should result in a more consistent better binning and performances.
> Seems that for the B2 this hasn't been done.
> My guess is they have been working 100% on the next thing and 0% on the current one.
> Fair, their company.
> But I'm considering putting 0% of my money on their next thing


Yeah, but AMD did mention that "the revision does not bring improvements in terms of functionality or performance"








AMD confirms B2 stepping for Ryzen 5000 series brings no functionality or performance improvements - VideoCardz.com


AMD Ryzen 5000 “Vermeer” on B2 stepping is only to improve production and availability Yesterday it was reported that AMD is developing a new stepping of its Vermeer processors. Meanwhile, the Polish website Benchmark.pl has reached out to AMD for a comment on this matter. The site received an...




videocardz.com





There were some hyped benchmarks of cherrypicked B2 samples, but apparently B2 quality is all over the place.
I think the AGESA changes since 1.2.0.4/5 with the lower VCore is just to tame them and increase stability at stock, but I don't know.

I agree on Hydra ratings, should be similar/consistent only on the same board under same cooling/ambient and bios. But I can also see the difference between my new and old CPU on the voltage needed for static overclocks, CO and max boost.

I think you were really unlucky and shouldnt accept a non stable CPU. if you still have a replacement AM4 CPU, RMA it 
Don't feel Intel's current offering is attractive, but next gen is going to interesting on both sides. But let's not go into that discussion


----------



## Blackfyre

Taraquin said:


> Rare reboots is usually RFC. Hopefully 544 will be stable


Yeah most likely. 

1.48v crashed within cycle 1, I just upped it to 1.495v and increased tRCDWR to 12 from 10, to match tRP.


----------



## ManniX-ITA

dk_mic said:


> Yeah, but AMD did mention that "the revision does not bring improvements in terms of functionality or performance"


They always do, nobody wants to have old stock sitting on the shelf 
But a unless it's a new stepping to fix a bug, there's usually an improvement here and there.
Especially on the quality of the binning.
It's surprising for me that it's so easy to get an average/bad one.
My old B0 was not a good bin but still better than almost all B2 that I've seen.



dk_mic said:


> I think you were really unlucky and shouldnt accept a non stable CPU. if you still have a replacement AM4 CPU, RMA it


I have it cause with 2 swaps the 30 days return window passed.
Anyway it's a decent 5800X, I'm the best uncle and I'll gift it to my niece 
But I'm going back to Italy end of the week, no time to swap again before I leave.

I'm just fed up wasting time for nothing. I have so much stuff to do, this is a complete loss.
And I really missed the 16 cores using the 5800X...


----------



## Taraquin

ManniX-ITA said:


> They always do, nobody wants to have old stock sitting on the shelf
> But a unless it's a new stepping to fix a bug, there's usually an improvement here and there.
> Especially on the quality of the binning.
> It's surprising for me that it's so easy to get an average/bad one.
> My old B0 was not a good bin but still better than almost all B2 that I've seen.
> 
> 
> 
> I have it cause with 2 swaps the 30 days return window passed.
> Anyway it's a decent 5800X, I'm the best uncle and I'll gift it to my niece
> But I'm going back to Italy end of the week, no time to swap again before I leave.
> 
> I'm just fed up wasting time for nothing. I have so much stuff to do, this is a complete loss.
> And I really missed the 16 cores using the 5800X...


What do you do most on your pc? For gaming it seems 5800X often can match 59X0X due to a bit better latency(intercore). 5800X is a too hot, I even find my 5600X a bit hot compared to my previous 3600, i5 8400 and i5 12400F. 

One thing I've noticed is that the heat buildup increases exponentially around 1.2V and above. I tracked the voltage behavior on my 5600X and compared to temp using 0 to +200 pbo
-30 CO: [email protected] 64C
-30 CO: [email protected] 65C
-29x1, - 30x5 CO: [email protected] 67C
-29x1, - 30x5 CO: [email protected] 70C
-26x1, - 29x1- 30x4 CO: [email protected] 73C

Aida using 0 got me 52.4ns, +200 gives 51.7. In SOTTR I get [email protected]+0 and [email protected]+200.

Single core pwr consumption is about 15% higher at +200 pbo vs 0.

Seems 1.2v+/- is the sweetspot for perf vs consumption vs temp.


----------



## ManniX-ITA

Taraquin said:


> What do you do most on your pc?


I mostly do coding lately and difference with the 5950X is really big... 5800X is awesome for gaming.
It runs hot yes but it delivers performances, if it's a decent binning.


----------



## Taraquin

ManniX-ITA said:


> I mostly do coding lately and difference with the 5950X is really big... 5800X is awesome for gaming.
> It runs hot yes but it delivers performances, if it's a decent binning.


Then I understand why you prefer it  Ask Dxtdomdissar if he can send you one of his awesome 5950X?


----------



## domdtxdissar

ManniX-ITA said:


> Rating from Hydra is a bit different topic.
> Got for the same sample a Platinum rating on a board and Bronze on another.
> More interested in the boost clocks and the CO counts to judge the quality.
> 
> There's always a silicon lottery.


Vdroop is *very* important for the hydra rating, so if you want to compare hydra cpu ratings you should always use the same motherboard.. (higher vdroop = better CCD rating, but lower frequencies overall)

Seeing the silicon quality your going through with your RMA prosess, i guess i should be very happy with my end result 


http://imgur.com/a/6ovsyya


----------



## Taraquin

The_King said:


> I sorted some of my issues out. Turns out this Kit it fuzzy about what voltage you use. It would not post 3600 CL16 @ 1.45V but posted no issues with 1.4V.
> View attachment 2553756
> View attachment 2553777


Some older B-dies dislikes voltage close to 1.45v, I've heard of a few others, mostly A0. Really good fclk for first gen  Try lowering RFC, 296, 288 or 280 is better values and might work. Avg bins of B-die can do [email protected] I would consider raising CWL to 16 and lower RDWR to 8, this will likely work and perform better. RTP should be half WR so try 6. If it doesn't work I would consider WR 16, RTP 8. Rest looks really good, WTRL might go a bit lower, but doesn't affect performance that much.


----------



## Bloax

Taraquin said:


> Some older B-dies dislikes voltage close to 1.45v, I've heard of a few others, mostly A0. Really good fclk for first gen  Try lowering RFC, 296, 288 or 280 is better values and might work. Avg bins of B-die can do [email protected] I would consider raising CWL to 16 and lower RDWR to 8, this will likely work and perform better. RTP should be half WR so try 6. If it doesn't work I would consider WR 16, RTP 8. Rest looks really good, WTRL might go a bit lower, but doesn't affect performance that much.


The Patriot Viper 4400 sticks have no problems with 1.4v+, in fact here they are at 1.62v







The trouble with those sticks is that they _really_ want a very low procODT (preferrably 28.2 ohm), and they also appreciate RTP 7 tWR 14


And yes, there is such a thing as Too Much Voltage - I'd expect 3600 16-16-16 to be around 1.35v on those sticks


----------



## Taraquin

Bloax said:


> The Patriot Viper 4400 sticks have no problems with 1.4v+, in fact here they are at 1.62v
> View attachment 2553801
> 
> The trouble with those sticks is that they _really_ want a very low procODT (preferrably 28.2 ohm), and they also appreciate RTP 7 tWR 14
> 
> 
> And yes, there is such a thing as Too Much Voltage - I'd expect 3600 16-16-16 to be around 1.35v on those sticks


Viper 4400 like I have comeswith 1 45v as xmp-profile so we know they like voltage. Some older/low end B-dies comes with 1.35V xmp, and some of them hates voltages above 1.4V.

Did notice he had those sticks until now. Must be his IMC cause sticks trive at 1.45V


----------



## mongoled

Blameless said:


> I've got a pair of the same Patriot Vipers in one of my Zen 2 systems. Haven't really been able to push them.
> 
> This Team kit is proving to be solid for the money, though I wish they'd either have used more functional heatsinks or left them off entirely. At leat they aren't tall enough to get in the way of anything.


Yeah, ive been through a few kits to get ones that I am happy with, which reminds me I need to sell at least one pair of them !

Maybe they would play better on your Zen3 system ?


----------



## VPII

ArchStanton said:


> @VPII I run a very similar kit with these settings.
> 
> View attachment 2553745
> 
> 
> View attachment 2553746
> 
> 
> I plagiarized these settings from another poster here on OCN. They are not truly "tuned" to my system, but I have thoroughly tested them, and they run without error. I'm on my phone, so I won't be able to go into detail.


Great thanks will try them out.


----------



## The_King

Taraquin said:


> Viper 4400 like I have comeswith 1 45v as xmp-profile so we know they like voltage. Some older/low end B-dies comes with 1.35V xmp, and some of them hates voltages above 1.4V.
> 
> Did notice he had those sticks until now. Must be his IMC cause sticks trive at 1.45V


The behavior of the PV 4400 Kit I have is weird because it will post at 3200MT/s with any voltage 1.45V or even 1.5V but 3600MT/s will not boot above 1.41V.
Now I ran into another issue after testing with TM5 its throwing errors at everything setting at 3600MT/s even with auto/high TCL and TRFC but passes 3200 CL14 and 3400CL14 with lower TRFCs with no problems. I am beginning to love my Micron REV. E much and more now.  So far B-Die is pooh as far as my 1700X is concerned. 

















My Micron REV.E is 16GBX2 Dual RANK! 3600 CL14 no issues. But the Viper 4400 is not able to do 3600 without getting ERRORS in TM5.


----------



## Taraquin

The_King said:


> The behavior of the PV 4400 Kit I have is weird because it will post at 3200MT/s with any voltage 1.45V or even 1.5V but 3600MT/s will not boot above 1.41V.
> Now I ran into another issue after testing with TM5 its throwing errors at everything setting at 3600MT/s even with auto/high TCL and TRFC but passes 3200 CL14 and 3400CL14 with lower TRFCs with no problems. I am beginning to love my Micron REV. E much and more now.  So far B-Die is pooh as far as my 1700X is concerned.
> 
> View attachment 2553807
> View attachment 2553810
> 
> 
> My Micron REV.E is 16GBX2 Dual RANK! 3600 CL14 no issues. But the Viper 4400 is not able to do 3600 without getting ERRORS in TM5.
> View attachment 2553808


B-die is much harder to run for the memory controller, mostly due to low rcdrd and rfc. Use the kit that gets you best performance


----------



## The_King

Taraquin said:


> B-die is much harder to run for the memory controller, mostly due to low rcdrd and rfc. Use the kit that gets you best performance


3600 CL20 with RFC 631 should not be a strain I would think. 
I'm sure its more to do with MSI optimisming their BIOS better for REV.E KITS compared to B-DIE. Will see how this B-DIE Kit does with a 5700X or 5800X3D next month.


----------



## Mach3.2

Audioboxer said:


> The more I hear about B2 the more I hug my B0 lol.


Yeah, if I filter out my 1900MHz FCLK hole and wooden 5600X moanings, my 5900X(2113SUS) actually have pretty decent silicon quality. I mean giving credit where it's due right?


----------



## Taraquin

The_King said:


> 3600 CL20 with RFC 631 should not be a strain I would think.
> I'm sure its more to do with MSI optimisming their BIOS better for REV.E KITS compared to B-DIE. Will see how this B-DIE Kit does with a 5700X or 5800X3D next month.


Ah, sorry, missed that you tried with more relaxed timings. Could try different bioses and see if some are better?


----------



## The_King

Taraquin said:


> Ah, sorry, missed that you tried with more relaxed timings. Could try different bioses and see if some are better?


MSi just released 1.2.0.6c today updated and tried still getting errors.


----------



## Taraquin

The_King said:


> MSi just released 1.2.0.6c today updated and tried still getting errors.
> View attachment 2553811


I would downgrade to agesa 1.2.0.3b/c if available unless you use win11.


----------



## The_King

Taraquin said:


> I would downgrade to agesa 1.2.0.3b/c if available unless you use win11.


I just upgraded from 1.2.0.3C to 1.2.0.6C today. Will probably keep the new version has it has the support for AMD new CPUS being release next month.









1.2.0.3C is great for Micron RAM and the one I would also recommend others to use as well over 1.2.0.5.

Never going to use W11


----------



## Blameless

Tried tightening up tRAS and tRC to 27/40...got one error in the last test of the last pass (of 10) in my subsequent TM5 run.

Loosened them to 29/42 and got the best WinRAR score (I do quick benches with this because it's both a real world app that I use and because it's phenomenally sensitive to memory timings) I've seen on this CPU:











mongoled said:


> Maybe they would play better on your Zen3 system ?


They do, but I've never really spent the time to push them on this board, as it's is a two-slot setup and 2x8GiB of single rank stuff is both too low on capacity and didn't offer enough of a real performance advantage over my dual-rank CJR.

Will probably swap this 5800X over to my other system with the Patriot in it when I put a 5800X3D or 5950X in my main one.


----------



## Tobiman

ManniX-ITA said:


> Well, I have put in the 2nd brand new B2 5950X in.
> It's even worse than the previous one.
> The only good aspect so far is that it doesn't seem broken and didn't destroyed my Windows install.
> 
> Compared to the previous one it shares almost all the aspects of the poor binning.
> 
> The best/2nd best cores are 0 & 1 *and core 1 doesn't pass CC 720K at Stock.*
> Not even the others can pass reliably the 10 minutes run, I had to set a positive vCore offset of 25mV.
> But Core 1 was failing between immediately and 2 minutes.
> Had to set a positive offset +2 to make it pass.
> 
> Limited boost clock overall, especially on the good cores.
> In general low performances, had to struggle a lot to get it close to the old B0.
> 
> Compared to the previous B2 it doesn't like any change to VDD18.
> And it doesn't run FCLK 2000 without a 1 second regression on y-c pi25b.
> Score are also generally lower than the previous B2.
> 
> I guess that's why AMD dropped the price, it's garbage now.
> 
> Compared to the 5800X that can run FCLK2000 it's massively inferior up to 8/12 threads.
> 
> B0 vs B2
> View attachment 2553664
> View attachment 2553665
> 
> 
> And this is with almost everything still to test with CoreCycler.
> The B0 was fully tested.
> 
> I will not even bother to send it back even if it doesn't pass at stock.
> It's so similarly bad binned as the previous one that I'm pretty sure I'll never get something much better.
> Plus I'm fed up of this bitching and swapping.
> Next good thing comes out, probably from Intel, and I'll sell it.


My B0 stepping 5950x needs more than 1.5v to hit similar clocks. I bought and tested 3 5950x. This was the best and it was rated as a bronze sample. I paid almost $1000 each for two of them and they were all bronze BNIB.


----------



## Blameless

Tobiman said:


> My B0 stepping 5950x needs more than 1.5v to hit similar clocks. I bought and tested 3 5950x. This was the best and it was rated as a bronze sample. I paid almost $1000 each for two of them and they were all bronze BNIB.


What was the batch number (assembly/diffusion code) on these?


----------



## Tobiman

Blameless said:


> What was the batch number (assembly/diffusion code) on these?


----------



## Bloax

The_King said:


> MSi just released 1.2.0.6c today updated and tried still getting errors.
> View attachment 2553811


Memory does not work in such a way that you can max out all the values, and expect it to run more stable.

The values have to fit together, and some of them have relationships we do not explore due to it being unnecessary (e.g. what happens if you run really high RDWR/WRRD values, too high tWR/RTP)
I don't know if Zen 1 has a buggy procODT, and thus you're doomed to be unable to run it properly until you get a new CPU, but my experience with this kit of memory is no different from @mongoled 's (Left image is newest, both his configs :- )):








Which is that this kit of memory _really wants_ a super low procODT to run best, and for that to run - you need to raise "CPU 1.8v", or "CPU 1P8" from 1.8v to 1.85-1.93+
(This setting seems to have many names, never mentioning that it is VCCIN - DRAM input voltage - but it is usually the only one which _says_ that it defaults to 1.80v, and that is the clearest way to identify it)

If I had to _blindly guess_ based on my silly past experience, then the lower procODT on the left is what lets him run RRDL 6 instead of 8 - as on my LGA1700 system, they are good for RRDL 4 even at 4200 MT/s

These sticks also highly appreciate RTT Nom/6 (40), Wr/3 (80), Park/5 (48) - not setting those is playing with fire.

Now that I am soon getting some Viper 4000 16-16-16 1.45v sticks to explore, I might whip out my 5800x system again to see how the 4400 19-19-19 sticks behave on it.


p.s. i am pretty sick lately and having MEMORY PROBLEMS so sorry if i repeat myself haha xd


----------



## KedarWolf

Taraquin said:


> I would downgrade to agesa 1.2.0.3b/c if available unless you use win11.


You don't need a newer BIOS for Win 11. Just enable fTPM in the older one when you install it, or even better yet, use the below script to remove all fTPM and any requirement from your Win 11 install ISO.









Win 11 Boot And Upgrade FiX KiT


Win 11 Boot And Upgrade FiX KiT v3.0 Name: Win_11_Boot_And_Upgrade_FiX_KiT_v3.0.zip Mirror1: Win_11_Boot_And_Upgrade_FiX_KiT_v3.0.zip Mirror2:...




forums.mydigitallife.net


----------



## The_King

Bloax said:


> Memory does not work in such a way that you can max out all the values, and expect it to run more stable.
> 
> The values have to fit together, and some of them have relationships we do not explore due to it being unnecessary (e.g. what happens if you run really high RDWR/WRRD values, too high tWR/RTP)
> I don't know if Zen 1 has a buggy procODT, and thus you're doomed to be unable to run it properly until you get a new CPU, but my experience with this kit of memory is no different from @mongoled 's (Left image is newest, both his configs :- )):
> View attachment 2553903
> 
> Which is that this kit of memory _really wants_ a super low procODT to run best, and for that to run - you need to raise "CPU 1.8v", or "CPU 1P8" from 1.8v to 1.85-1.93+
> (This setting seems to have many names, never mentioning that it is VCCIN - DRAM input voltage - but it is usually the only one which _says_ that it defaults to 1.80v, and that is the clearest way to identify it)
> 
> If I had to _blindly guess_ based on my silly past experience, then the lower procODT on the left is what lets him run RRDL 6 instead of 8 - as on my LGA1700 system, they are good for RRDL 4 even at 4200 MT/s
> 
> These sticks also highly appreciate RTT Nom/6 (40), Wr/3 (80), Park/5 (48) - not setting those is playing with fire.
> 
> Now that I am soon getting some Viper 4000 16-16-16 1.45v sticks to explore, I might whip out my 5800x system again to see how the 4400 19-19-19 sticks behave on it.
> 
> 
> p.s. i am pretty sick lately and having MEMORY PROBLEMS so sorry if i repeat myself haha xd


Thanks for the reply i have tried with low ProcODT even all 20s for *DrvStr however my memory issues is a hardware compatibility one and nothing really to do with any settings on the Patriot Viper 4400. The Maxed out settings are from XMP Auto profile in the BIOS although these settings were not the reason behind the errors i was getting.

The RAM kit is actually pretty good IMO at the closer to my CPU supported frequency 3400 CL14. I'm sure this KIT would work far better on a ZEN2 or ZEN3 CPU. After further testing I did get some good results that I am happy with.










PS I am also just recovering from being sick myself. Hope you are feeling better today.


----------



## gameinn

I got F4-3600C14D-32GTZNA

This was default XMP:










and the XMP table from Thaiphoon:










I'm verifying stability right now (tm5 anta extreme) at pure XMP but after doing this should I do the following based on second screenshot:

1: Lower tRC to 48 (from 85)
2: Set tRRDS to 4 (from 7)
3: Set tRRDL to 9 (from 10)

Then rerun tm5?


----------



## ManniX-ITA

Tobiman said:


> My B0 stepping 5950x needs more than 1.5v to hit similar clocks. I bought and tested 3 5950x. This was the best and it was rated as a bronze sample. I paid almost $1000 each for two of them and they were all bronze BNIB.


Yeah bad luck in binning was there also with B0...
But I heard about a lot of lucky draws.
So far I don't remember many, maybe one, about the 5950X B2.

Anyway I'm probably going to send it back when I come back end of April.
Comes out there's another issue; coil whine.
I'm not even very sensible but once I'm running in debugging mode in Visual Studio there's a pretty loud hiss which is monstrously unnerving.
Never happened before with the others CPU...

In the meantime I'm going forward with my bench tool and have partially implemented direct Zen sensors reading.
Which means reading Effective Clocks and reporting clock stretching 










And about the goodness of the 5800X and how relative are clocks with PBO...

This is the slow B2 at FCLK 2000, not really performing:









This is at FCLK1900, better and worse depending on threads:









This the 5800X at FCLK2000 at +200 boost clock:









For sure there are better 5950X out there... but it's just blowing away the 5950X up to 8 threads. No mercy.
At the same clock pumps more IPC.
Memory settings are slightly better on the 5950X with tRCDRD at 15 instead of 16.

Even at +0 boost clock, limited at 4850 MHz:









It's beating or toe to toe with the 5950X at 100 MHz lower clock.


----------



## Blameless

I think this is the best I can do with this kit at 1.47 vDIMM:









Taking a break from the testing for a while to play some games that really leverage this well-tuned system...
_fires up DOXBox to play crap from the early 1990s_



ManniX-ITA said:


> It's beating or toe to toe with the 5950X at 100 MHz lower clock.


What happens when you force affinities to keep everything eight threads or below on the same (best) CCX/CCD?


----------



## ManniX-ITA

Blameless said:


> What happens when you force affinities to keep everything eight threads or below on the same (best) CCX/CCD?


That's it, the first 8 threads are always on the CCD1 cores on T0 per CPPC order.


----------



## domdtxdissar

ManniX-ITA said:


> Yeah bad luck in binning was there also with B0...
> But I heard about a lot of lucky draws.
> So far I don't remember many, maybe one, about the 5950X B2.
> 
> Anyway I'm probably going to send it back when I come back end of April.
> Comes out there's another issue; coil whine.
> I'm not even very sensible but once I'm running in debugging mode in Visual Studio there's a pretty loud hiss which is monstrously unnerving.
> Never happened before with the others CPU...
> 
> In the meantime I'm going forward with my bench tool and have partially implemented direct Zen sensors reading.
> Which means reading Effective Clocks and reporting clock stretching
> 
> View attachment 2553970
> 
> 
> And about the goodness of the 5800X and how relative are clocks with PBO...
> 
> This is the slow B2 at FCLK 2000, not really performing:
> View attachment 2553975
> 
> 
> This is at FCLK1900, better and worse depending on threads:
> View attachment 2553976
> 
> 
> This the 5800X at FCLK2000 at +200 boost clock:
> View attachment 2553978
> 
> 
> For sure there are better 5950X out there... but it's just blowing away the 5950X up to 8 threads. No mercy.
> At the same clock pumps more IPC.
> Memory settings are slightly better on the 5950X with tRCDRD at 15 instead of 16.
> 
> Even at +0 boost clock, limited at 4850 MHz:
> View attachment 2553980
> 
> 
> It's beating or toe to toe with the 5950X at 100 MHz lower clock.


If you share that benchmark if can give it a run when i get back home from work later today


----------



## ManniX-ITA

domdtxdissar said:


> If you share that benchmark if can give it a run when i get back home for work later today


That's a very old build I have on the BenchOS


----------



## The_King

Hey Guys. Just wanted to share more info on my testing of my Patriot 4400Mhz B-Die Kit.

I was fine tuning my timings by lowering RDRDSD and RDRDDD from 5s to 4s and WRWRSD and WRWRDD from 7s to 6s. I got errors in TM5 so I went into the BIOS and set them to Auto. The AUTO set 6s for RDRDSD and RDRDDD etc and 7s WRWRSD and WRWRDD.

While running TM5 I get a black screen. So one may think black screen maybe an issue with tRFC being too low but turns out setting RDRDSD and RDRDDD back to 5s its fully stable again.

This Kit is definitely very fuzzy when it comes several settings. So keep that in mind a black screen or reboot can be caused by different wrong settings when tuning this RAM.


----------



## ManniX-ITA

The_King said:


> This Kit is definitely very fuzzy when it comes several settings. So keep that in mind a black screen or reboot can be caused by different wrong settings when tuning this RAM.


Black screen while testing with TM5 sometimes is also due to VSOC.
Maybe it's not enough for the tight timings you are using.


----------



## The_King

ManniX-ITA said:


> Black screen while testing with TM5 sometimes is also due to VSOC.
> Maybe it's not enough for the tight timings you are using.


Yes that can also cause reboots and black screens as well, I test VSOC by running y-cruncher 2.5B usually if the VSOC is too low it will fail/reboot 100% of the time.
My VSOC is usually set at 1.2V perfectly safe on my CPU have been running this for years. (1700X) But is current on AUTO at the moment.

Considering that with lower timings the ram was stable it probably was not an issue with my VSOC in this case.


----------



## Taraquin

A bit off-topic, but is it usual that cores degrade slightly and require higher voltage as they age? 

On my 5600X -30 CO and +50 pbo has been rock solid since last summer, -28x1, -29x1, -30x4 and +200 has also been stable since last summer. Last weeks I got reboots due to core 0 on both profiles. [email protected]+50 and [email protected]+200 is now stable. I have same bios, same chipset drivers etc, only a few updates for win10 lately. I reduced EDC and TDC to 75 and 50 as it improved temps a bit while giving me identical perf, could change in EDC/TDC be the reason or is it degradation by age? At load voltage on +200 maxes out at 1.34v and +50 at 1.22v, temp is never above 73C, usually it stays at 50-60C during gaming with short spikes to around 65C on +50 and around 70C on +200 on loadingscreens.


----------



## The_King

Taraquin said:


> A bit off-topic, but is it usual that cores degrade slightly and require higher voltage as they age?
> 
> On my 5600X -30 CO and +50 pbo has been rock solid since last summer, -28x1, -29x1, -30x4 and +200 has also been stable since last summer. Last weeks I got reboots due to core 0 on both profiles. [email protected]+50 and [email protected]+200 is now stable. I have same bios, same chipset drivers etc, only a few updates for win10 lately. I reduced EDC and TDC to 75 and 50 as it improved temps a bit while giving me identical perf, could change in EDC/TDC be the reason or is it degradation by age? At load voltage on +200 maxes out at 1.34v and +50 at 1.22v, temp is never above 73C, usually it stays at 50-60C during gaming with short spikes to around 65C on +50 and around 70C on +200 on loadingscreens.


According to this test it can degrade at higher voltages


----------



## Taraquin

The_King said:


> Yes that can also cause reboots and black screens as well, I test VSOC by running y-cruncher 2.5B usually if the VSOC is too low it will fail/reboot 100% of the time.
> My VSOC is usually set at 1.2V perfectly safe on my CPU have been running this for years. (1700X) But is current on AUTO at the moment.
> 
> Considering that with lower timings the ram was stable it probably was not an issue with my VSOC in this case.
> View attachment 2554079


I don't think tighter timings makes vsoc req higher, never experienced that myself. If you try going higher I would consider setting scl's to 4, this should be more stable and perform the same. Another tip for better stability is running rrdl at 6, barely affects performance. Set your rtp to 6, should be half wr.


----------



## Taraquin

The_King said:


> According to this test it can degrade at higher voltages


Yeah, I know, but even at +200 pbo 1.34v in some single loads are below the 1.4v+ the chips does at stock with no CO.


----------



## The_King

Taraquin said:


> I don't think tighter timings makes vsoc req higher, never experienced that myself. If you try going higher I would consider setting scl's to 4, this should be more stable and perform the same. Another tip for better stability is running rrdl at 6, barely affects performance. Set your rtp to 6, should be half wr.


My issue was with the higher timings I got the black screen and by lowering the timings I got it stable. lol

Will give rtp to 6 and test now. Thanks


----------



## Audioboxer

They called me an idiot for watercooling my memory.... jokes on them, I'm now about to watercool my NVMe!!! 

Main reason for the order is I want to put that fat boy 60mm radiator in the rear, rather than the 30mm Corsair. Some of the other options for 120mm thick begin getting 4mm+ wider than the XR5 and you have to be careful for fit. XR5 is 120mm wide, Bykski is 122mm, so it should fit fine with just 1mm extra each side.


----------



## Taraquin

The_King said:


> My issue was with the higher timings I got the black screen and by lowering the timings I got it stable. lol
> 
> Will give rtp to 6 and test now. Thanks


One tip for you if you want Ryzen gen 1 running really fast ram is switching to a motherboard with only 2 dimm-slots, some mATX-boards and all ITX-boards (expensive though) have only 2 dimms which greatly improves memory tracing compared to most 4 dimm boards. There are some cheap boards out there, for instance the predecessor to my board, Gigabyte B450m S2H which I have talked to some running for instance 3000G at 3800MHz ram  Even on Ryzen 5000 almost all of us that can run ram at above 3800 without problems have 2 dimm boards (and single ccd CPU except Veii).


----------



## The_King

Taraquin said:


> One tip for you if you want Ryzen gen 1 running really fast ram is switching to a motherboard with only 2 dimm-slots, some mATX-boards and all ITX-boards (expensive though) have only 2 dimms which greatly improves memory tracing compared to most 4 dimm boards. There are some cheap boards out there, for instance the predecessor to my board, Gigabyte B450m S2H which I have talked to some running for instance 3000G at 3800MHz ram  Even on Ryzen 5000 almost all of us that can run ram at above 3800 without problems have 2 dimm boards (and single ccd CPU except Veii).


Usually here in my country the "good" two DIMM slot boards are too expensive. Overclocking RAM is more a hobby for me and my current results are pretty good.
VRM performance is more important to me than RAM OC has you can get more peformance from CPU OC than with RAM OC's

I actually just bough another B450M Mortar MAX board less than a month ago. Its really impressive for a B450 board and has one of the best VRMS temps ever seen.

I'm looking at getting one 5700X and one 5800X3D next month for each board. Waiting for official pricing though.


RTP 6 is working great. I overlooked that somehow.


----------



## Bloax

The_King said:


> VRM performance is more important to me than RAM OC as you can get more peformance from CPU OC than with RAM OC's


Depends very much on how memory-bound the task is, and a lot of things are becoming *more* memory-bound as CPUs become _crazy fast_ - and memory performance is being stagnant until EUV DDR5 chips start becoming mainstream, which is not really helping.









here's my favorite little image, but there are plenty of cases where _High Frequency + low RRD/WTR/tFAW = $ ++Massive Performance $_ is a thing.
cpu/cache frequency for this processor has very little impact on the numbers shown in this particular graph, 4.3 core/3.8 cache Ghz performs not that much worse than 5.2/4.5 ... cpu fast, memory slow



As for AM4 boards specifically - I haven't really heard of boards that struggle to run memory around 3666-3800 MT/s, and getting benefits from going past that seems to be _against AMD's policy_ 🤡
The better your memory performance is, the better the CPU voltage/frequency you can run for the same effective performance - so a super beefy VRM is not super necessary, when 90% of Peak Performance can be extracted at 50% of Peak Power. :- )



> RTP 6 is working great. I overlooked that somehow.


----------



## PJVol

Taraquin said:


> A bit off-topic, but is it usual that cores degrade slightly and require higher voltage as they age?


Interesting. In your case it seems more like the ageing (assuming EDC limits were unchanged throughout the lifetime)
The question is if its something like ring oscillator's aging or that of core logic itsellf.


----------



## The_King

@Bloax I agree, ideally you would want a board the does both CPU and RAM OC well. I think my B450M Mortar MAX board does a great job on both.

Also the fact that's very cheap (95USD) and support up to 4200MT/s with new BIOS it more than ticks all the boxes for any Desktop Ryzen CPU the awesome VRM puts most
high end boards to shame.

If you can tune 3800 CL14 or CL16 I also don't see a need to really go higher myself but that wont stop me from trying for FCLK 1900/2000 with my new Zen3 CPUs. 

I already got 1900/1933 FCLK with my Ryzen 1700X. Single channel though and not TM5 stable but still cool.😎


----------



## dk_mic

Taraquin said:


> A bit off-topic, but is it usual that cores degrade slightly and require higher voltage as they age?
> 
> On my 5600X -30 CO and +50 pbo has been rock solid since last summer, -28x1, -29x1, -30x4 and +200 has also been stable since last summer. Last weeks I got reboots due to core 0 on both profiles. [email protected]+50 and [email protected]+200 is now stable. I have same bios, same chipset drivers etc, only a few updates for win10 lately. I reduced EDC and TDC to 75 and 50 as it improved temps a bit while giving me identical perf, could change in EDC/TDC be the reason or is it degradation by age? At load voltage on +200 maxes out at 1.34v and +50 at 1.22v, temp is never above 73C, usually it stays at 50-60C during gaming with short spikes to around 65C on +50 and around 70C on +200 on loadingscreens.


could it be that you have switched bios/agesa back and forth and that changed some tables or microcode or so?


----------



## ArchStanton

@Audioboxer Do you have room for a 120mm "Big Mac"?









Credit: @geriatricpollywog (who is apparently banned at the moment 🤷‍♂️)

I think half of the "big mac" is usually mounted externally of the case. Yes, it's expensive. Yes, it's inefficient. However, the pictures he provided of his version just looked freakin' "metal" IMO.


----------



## Taraquin

PJVol said:


> Interesting. In your case it seems more like the ageing (assuming EDC limits were unchanged throughout the lifetime)
> The question is if its something like ring oscillator's aging or that of core logic itsellf.
> View attachment 2554105


I lowered EDC and TDC a few days prior to this so part of my question was if that could affect it?


----------



## Taraquin

dk_mic said:


> could it be that you have switched bios/agesa back and forth and that changed some tables or microcode or so?


No, I have had agesa 1.2.0.3b since it released and kept it ever since  Only thing I did was lower TDC to 50 and EDC to 75 to improve temps a few weeks ago.


----------



## Bloax

The recent, super-dense nodes, do age much faster than the almost timeless monolith nodes of times past - regardless of operating voltage or current.

Software reports on voltage, frequency and temperature all live in the distant past - Matisse/Vermeer boosting lives within the realm of single milliseconds.
Core 0 having the most wear makes sense, as it is by default the core responsible for handling all the interrupt requests - very quick, simple workloads.
Workloads which will easily trigger PBO boosting to its maximum frequency at its maximum voltage, and long since be back down by the time you attempt to do a readout of the values.

And over the span of an entire year full of such shenanigans, it has achieved 5-8 mV worth of degradation! 💪🤡
Within fifteen years, you might even see it degrade by a full 200 mV!

Which is relevant for replacements of systems which are still running 60 years later, but probably not a big concern for your expendable workhorse desktop PC.




The_King said:


> that wont stop me from trying for FCLK 1900/2000 with my new Zen3 CPUs.


You can try and see if you can bruteforce a set of voltages on the AGESA 1202 BIOS that make 1900+ behave well enough to be beneficial, but supposedly blowing out EDC doesn't help on 1.2.0.5+ ?

good luck in the future


----------



## Bloax

The_King said:


> that wont stop me from trying for FCLK 1900/2000 with my new Zen3 CPUs.


You can try and see if you can bruteforce a set of voltages on the AGESA 1202 BIOS that make 1900+ behave well enough to be beneficial, but supposedly blowing out EDC doesn't help on 1.2.0.5+ ?

good luck in the future


----------



## PJVol

Taraquin said:


> I lowered EDC and TDC a few days


So, are changes in CO stability manifested with the same EDC limit, regardless of what it was set to before.


Bloax said:


> Core 0 having the most wear makes sense, as it is by default the core responsible for handling all the interrupt requests


You can add to this - core0 is the bootstrap core by default.


----------



## Audioboxer

ArchStanton said:


> @Audioboxer Do you have room for a 120mm "Big Mac"?
> 
> View attachment 2554107
> 
> Credit: @geriatricpollywog (who is apparently banned at the moment 🤷‍♂️)
> 
> I think half of the "big mac" is usually mounted externally of the case. Yes, it's expensive. Yes, it's inefficient. However, the pictures he provided of his version just looked freakin' "metal" IMO.


Hahaha, that looks awesome! I would maybe be able to pull that off somewhere, but nah, just looking to replace my 120mm XR5 when I became aware a few manufactures made thick 120mm rads. Seems quite a specialist rad (size wise), as rarely anyone will normally be buying it. Not really enough to do anything on its own, so 240/360 will be most common, so probably relegated to supplementing a full loop if it can be squeezed in somewhere.

I _think_ the Bykski will have the benefit of being slightly less restrictive than the XR5. It'll be on push/pull, so fine for the thick boys.


----------



## Luggage

Audioboxer said:


> Hahaha, that looks awesome! I would maybe be able to pull that off somewhere, but nah, just looking to replace my 120mm XR5 when I became aware a few manufactures made thick 120mm rads. Seems quite a specialist rad (size wise), as rarely anyone will normally be buying it. Not really enough to do anything on its own, so 240/360 will be most common, so probably relegated to supplementing a full loop if it can be squeezed in somewhere.
> 
> I _think_ the Bykski will have the benefit of being slightly less restrictive than the XR5. It'll be on push/pull, so fine for the thick boys.


My 140x60 from before 









Now it’s gathering dust till the next project


----------



## Audioboxer

Luggage said:


> My 140x60 from before
> 
> View attachment 2554122
> 
> Now it’s gathering dust till the next project


LOL, that is amazing. I've got mine inside with 1 fan, just the second fan external.


----------



## ManniX-ITA

I have released a first Alpha of BenchMaestro, enjoy 









BenchMaestro - CPU & GPU benchmarking and Tools Utility


Here's my very own benching and tools utility, hope you enjoy! Will be a constant Work in Progress of course :p https://github.com/mann1x/BenchMaestro Since it's made by someone that runs lots of benchmarks, there are some neat features: ConfigTag: name your configuration, will be part of the...




www.overclock.net







Taraquin said:


> I don't think tighter timings makes vsoc req higher, never experienced that myself.


I did experienced it, depends on the IMC quality.
My old 5950X needed at least 1.15V to be stable with B-die very tight timings under y-cruncher and AIDA.
Using the XMP not a problem.


----------



## MrHoof

@ManniX-ITA CPPC order is not read correctly on my asus board, dunno if already known. 


Spoiler: cppc


----------



## ManniX-ITA

MrHoof said:


> CPPC order is not read correctly on my asus board, dunno if already known.


That means you have some issue with the System Event Log.
I read the ACPI CPPC event log messages from there.
Maybe you disabled the Eventlog?


----------



## MrHoof

No nothing disabled. HWinfo reads them correctly dunno what source it uses.


----------



## ManniX-ITA

MrHoof said:


> No nothing disabled.


Then try clearing the System Log, must be messed up. (and reboot)

Can you send me in PM the tracelog-date.txt file in the bench dir?


----------



## MrHoof

Send in Pm


----------



## Melan

Anyone had an issue with ProcODT wildly changing values (while on auto) when switching between GDM on and off?
I had 36.9 ohm set manually with 1T command rate, then I switched to GDM on + auto ProcODT which decided to set 60 ohm. After shutdown and restart ProcODT autoset to 36.9 again with GDM.

Also with agesa 1.2.0.5 not only 1T was stable at 3600 but 3733 is stable with GDM \o/
3800 is still not booting


----------



## Anhphe93

I don't know why my latency is so high. I can't run 15-15-15-15 flat. Anyone have any ideas for me?


----------



## Bloax

Memory latency is increased for the same reason that L3 latency is increased;








the fabric is unstable

you're gonna have to bruteforce the best performing combination of SOC, IOD and CCD voltage: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
one step at a time 🤡


----------



## PJVol

Bloax said:


> Memory latency is increased for the same reason that L3 latency is increased


Did I get it right that as of today all Win11 related issues with L3 / memory latency have been solved?


----------



## Bloax

oh god why would you put yourself through running win11

I know pain is fun and all, but Winblows winblowing itself on repeat is hardly good masochism, helplessly watching as your system drools itself to death.. Yuck!


----------



## PJVol

@Bloax not me (if the above was meant for me), but @Anhphe93 seem to run win11 (my dad was like super strict and forbade me to approach any bdsm communities)


----------



## Blackfyre

Bloax said:


> oh god why would you put yourself through running win11
> 
> I know pain is fun and all, but Winblows winblowing itself on repeat is hardly good masochism, helplessly watching as your system drools itself to death.. Yuck!


What makes you think Windows 11 is that bad? Or bad at all? Have you tried it yourself?

I've been using it for months, since last year in fact, and haven't had issues with it. Especially since the L3 cache problem was resolved with a chipset driver update last year.

I find it better than Windows 10 in almost every way now. The only thing I was really missing was the drag and drop onto taskbar open programs, which has been resolved in the Dev and Beta builds on insider.


----------



## PJVol

Anhphe93 said:


> I don't know why my latency is so high.


I'd first try to update AIDA. That one from screenshot is too old.
I've heard AIDA devs greatly improved bencmark code in a recent builds, i.e. made something like


C++:


IF (version == "more-up-to-date" AND windows == 11)
{
    MemLatency -= 3; // ns
    L3latency -= 0.5; // ns
}


----------



## ManniX-ITA

PJVol said:


> I've heard AIDA devs greatly improved bencmark code in a recent builds, i.e. made something like


Makes sense. 
I've always had the impression that nanoseconds are an oneiric expression of cathartic tomatoes.


----------



## Anhphe93

PJVol said:


> @Bloax not me (if the above was meant for me), but @Anhphe93 seem to run win11 (my dad was like super strict and forbade me to approach any bdsm communities)


You're right. I am using win11  win 11 damn. But game for better picture with "auto hdr"


----------



## 97pedro

Hello all,

This is what I got out of a 3200mhz cl14 flare x kit (4 dimms).

What do you think?

Also, any idea why Aida64 memory latency test makes my pc reboot sometimes?


----------



## The_King

Any suggestion on what I can lower. Just dropped tCWL 12 and RDWR 8


----------



## izzymariano

Has anyone oc the f4-3600c14q-64gtzn quad rank pair with 5900x and dark hero mobo?
I have these but wanted to see a good tuning or oc . Much appreciated .


----------



## tcclaviger

Where I ended up for daily setup. Had run PT10 without clearing HWinfo, max values reflect PT10.

Seems reasonably good for daily. With 1 CCD instead of 2 active latency drops to ~51.5ns.


----------



## Taraquin

97pedro said:


> Hello all,
> 
> This is what I got out of a 3200mhz cl14 flare x kit (4 dimms).
> 
> What do you think?
> 
> Also, any idea why Aida64 memory latency test makes my pc reboot sometimes?
> 
> View attachment 2554369


Usually too low iod voltage. Try a bit higher.


----------



## Taraquin

The_King said:


> Any suggestion on what I can lower. Just dropped tCWL 12 and RDWR 8
> View attachment 2554380


Lower rfc by 8 and 8 till it won't boot. You should try a bit higher vdimm. At 1.45v you should be able to do 240, 248 or 256.


----------



## badger2k

izzymariano said:


> Has anyone oc the f4-3600c14q-64gtzn quad rank pair with 5900x and dark hero mobo?
> I have these but wanted to see a good tuning or oc . Much appreciated .


I got this result with a set of two. Same ones as the quad kit. Ignore 2t CR, my Motherboard is weird. 
tRFC should go lower btw. Somewhere between 130-140ns at 1.5V.


----------



## Blackfyre

I am now using *1.48v* instead of 1.52v by lowering ProcODT to *28.2 Ω* and changing CAD BUS values to* 20, 20, 20, 20* instead of 24, 20, 24, 24

It has resulted in better stability for my overclock. 32Gb --> 4 x 8 Micron-E die (_Default 3600Mhz CL16_).

Could not disable Rtt Nom, my system wouldn't boot with it disabled.


----------



## PJVol

Hi! Can anyone confirm or give an example of a bench demonstrating the negative impact the disabled global C-states generation (i.e. CC6) has on Vermeer performance in light workloads?
Preferably (or even mandatory) with a bios based on 1.2.0.3c or later agesa.
Thanks!


----------



## Taraquin

Blackfyre said:


> I am now using *1.48v* instead of 1.52v by lowering ProcODT to *28.2 Ω* and changing CAD BUS values to* 20, 20, 20, 20* instead of 24, 20, 24, 24
> 
> It has resulted in better stability for my overclock. 32Gb --> 4 x 8 Micron-E die (_Default 3600Mhz CL16_).
> 
> Could not disable Rtt Nom, my system wouldn't boot with it disabled.
> 
> View attachment 2554436


Impressive, unusal that 20 20 20 20 works at 1t gdm off. You have good phyl aswell (unless it's 28 on some sticks?). Probably very little you can tweak left. Good result!


----------



## Blackfyre

Taraquin said:


> Impressive, unusal that 20 20 20 20 works at 1t gdm off. You have good phyl aswell (unless it's 28 on some sticks?). Probably very little you can tweak left. Good result!


Yeah 26 PHY on both A's and 28 PHY on both B's. I tried everything to get it to run 26 on the B sticks, but nope. 

I'm happy with the results anyway. I could probably squeeze a bit more, but will leave it for some other time.


----------



## gameinn

One thing I've wondered. As you lower other timings does it mean that timings you previously know are stable can become unstable? For example say I have verified tRRDS fully stable at 4 but if I change another timing, is there a possiblity that tRRDS is just not stable anymore or generally is all timing independent of each other and only requires the specific voltage?


----------



## Blackfyre

gameinn said:


> One thing I've wondered. As you lower other timings does it mean that timings you previously know are stable can become unstable? For example say I have verified tRRDS fully stable at 4 but if I change another timing, is there a possiblity that tRRDS is just not stable anymore or generally is all timing independent of each other and only requires the specific voltage?


Yeah, I've always wondered this too. I would assume they are all interlinked, so the instability could be coming from something you previously assumed was stable, but could become unstable once you changed another variable. Making it very difficult to tell which variable is actually causing the instability at any given time.


----------



## 97pedro

Taraquin said:


> Usually too low iod voltage. Try a bit higher.


Since I'm using AGESA V2 PI 1.2.0.6b, both iod and ccd voltages can't go higher than 1.000v.

Is this an issue? Apart from crashing in Aida, is there any drawback?


----------



## Taraquin

97pedro said:


> Since I'm using AGESA V2 PI 1.2.0.6b, both iod and ccd voltages can't go higher than 1.000v.
> 
> Is this an issue? Apart from crashing in Aida, is there any drawback?


Could give reduced performance, especiallu if using dual CCD and\or dual rank ram.


----------



## 97pedro

Taraquin said:


> Could give reduced performance, especiallu if using dual CCD and\or dual rank ram.


Ok it seems like I could change vddg voltages, I just now have to do it in the advanced tab under amd overclocking settings.

I set up a 1.0v ccd and a 1.05v iod.
Also, my cldo vddp voltage was through the roof at 1.1v, I locked it to 0.900v.

Is this a correct setting? Doesn't seem to be crashing now.


----------



## Taraquin

97pedro said:


> Ok it seems like I could change vddg voltages, I just now have to do it in the advanced tab under amd overclocking settings.
> 
> I set up a 1.0v ccd and a 1.05v iod.
> Also, my cldo vddp voltage was through the roof at 1.1v, I locked it to 0.900v.
> 
> Is this a correct setting? Doesn't seem to be crashing now.


That sounds good


----------



## gameinn

Blackfyre said:


> Yeah, I've always wondered this too. I would assume they are all interlinked, so the instability could be coming from something you previously assumed was stable, but could become unstable once you changed another variable. Making it very difficult to tell which variable is actually causing the instability at any given time.


I was thinking the same but most guides on the subject of ram oc say stuff like 1: put a timing in then test it's stable 2: do another timing and test that stable

If timings were correlated then this approach wouldn't make much sense


----------



## The_King

Taraquin said:


> Lower rfc by 8 and 8 till it won't boot. You should try a bit higher vdimm. At 1.45v you should be able to do 240, 248 or 256.


At 1.4V I was able to lower RFC to 242 increasing to 1.45V was able to lower to 229.
Which RFC do you recommend between the two? Should I round the RFC up to 248 and 232 so they are divisible by 8?


----------



## VPII

ArchStanton said:


> @VPII I run a very similar kit with these settings.
> 
> View attachment 2553745
> 
> 
> View attachment 2553746
> 
> 
> I plagiarized these settings from another poster here on OCN. They are not truly "tuned" to my system, but I have thoroughly tested them, and they run without error. I'm on my phone, so I won't be able to go into detail.


Hi my friend, so I managed to copy your timings except for some which I had to guess, however I found that for CL14 at 3800 I needed to up the vdimm to 1.49 in the bios. Dimm temps are fine, nothing to worry about but at leats it is working. MY latency is nowhere near yours but it is better for me regardless. Thanks for your input. I am still playing around to see what is possible.


----------



## KedarWolf

VPII said:


> Hi my friend, so I managed to copy your timings except for some which I had to guess, however I found that for CL14 at 3800 I needed to up the vdimm to 1.49 in the bios. Dimm temps are fine, nothing to worry about but at leats it is working. MY latency is nowhere near yours but it is better for me regardless. Thanks for your input. I am still playing around to see what is possible.
> View attachment 2554513


This is what I get GDM Disabled. Ram voltage 1.5v, VTTs .730v. It passes TM5 usmus 1000% 8 Cycles 7+ hours overnight and usmus stock settings.

It might help that I have a decent CO curve though too. 

I'm waiting on my CL14 3600 Royal Elite RAM. The first kit I binned wouldn't do Cl14 3800 anything I tried, I sent it back for a new kit.


----------



## Bloax

tCL 14, tCWL 12, tRCD 16, tRP 19, vSOC 1.2 IOD 1.14 CCD 1.08 at 1900 FCLK
nani what the **** that's a very odd-ball set of settings 💪🤡 
(is that 5950x really so tragic as to require +100 mV on every rail compared to the 5800x I have?)


gameinn said:


> I was thinking the same but most guides on the subject of ram oc say stuff like 1: put a timing in then test it's stable 2: do another timing and test that stable
> 
> If timings were correlated then this approach wouldn't make much sense


The general level of knowledge on the subject is low enough that Things That Don't Make Much Sense pass by unnoticed. :- )


----------



## KedarWolf

Bloax said:


> tCL 14, tCWL 12, tRCD 16, tRP 19, vSOC 1.2 IOD 1.14 CCD 1.08 at 1900 FCLK
> nani what the **** that's a very odd-ball set of settings 💪🤡
> (is that 5950x really so tragic as to require +100 mV on every rail compared to the 5800x I have?)
> 
> The general level of knowledge on the subject is low enough that Things That Don't Make Much Sense pass by unnoticed. :- )


Yes, my IMC needs those voltages to be stable, but the results speak for themselves, and everything is within safe limits.

I have one of the more knowledgable peeps in this thread suggest .6v between VSOC, CCD and IOD, why I run it.

tCWL 12 gives me better Write and Copy and better latency as well.

I cheat a bit on the tRP, tRAS and tRC, but it actually improves my AIDA.

And I find 19/21 instead of say 13/27 gives me more stability and better benchmarks.

It was suggested by @Veii to try something similar last year and I've run it ever since.


----------



## KedarWolf

This is 13/27.


----------



## Taraquin

The_King said:


> At 1.4V I was able to lower RFC to 242 increasing to 1.45V was able to lower to 229.
> Which RFC do you recommend between the two? Should I round the RFC up to 248 and 232 so they are divisible by 8?
> View attachment 2554510
> View attachment 2554509


I would do 1.45v+232  RC also scales with voltage so you can try going a bit lower on that aswell, just keep rc=ras+rp. 25+13=38, 24+13=37 etc. Usually ras can't go below 21 or 22 så 34/35 rc is lowest.


----------



## Taraquin

Bloax said:


> tCL 14, tCWL 12, tRCD 16, tRP 19, vSOC 1.2 IOD 1.14 CCD 1.08 at 1900 FCLK
> nani what the **** that's a very odd-ball set of settings 💪🤡
> (is that 5950x really so tragic as to require +100 mV on every rail compared to the 5800x I have?)
> 
> The general level of knowledge on the subject is low enough that Things That Don't Make Much Sense pass by unnoticed. :- )


It varies greatly from cpu to cpu, but in general 1 ccds requires less ccd and vddp it seems, sometimes lower soc and iod aswell. 

I can run my 5600X at 840mv ccd and vddp on 2000fclk, a guy I know needs 950ccd and 1000vddp to avoid WHEA19s at 1900fclk on his 5800X.


----------



## Taraquin

Blackfyre said:


> Yeah 26 PHY on both A's and 28 PHY on both B's. I tried everything to get it to run 26 on the B sticks, but nope.
> 
> I'm happy with the results anyway. I could probably squeeze a bit more, but will leave it for some other time.


If you plan on squeezing a bit more, rp can often go lower, maybe 11 or 12, remember ras+rp=rc. Rc may go a bit lower aswell, maybe 50-52. Rfc may do 552, 544, 536 or 528. I have 4 rev E sticks, 2 of them do 536 at 3800, 2 need 552.


----------



## 97pedro

Well guys even with 1.050v iod and 1.000v ccd with 1.15v soc I still get random reboots in aida64 memory latency and cache test.
Any tips?


----------



## SneakySloth

97pedro said:


> Well guys even with 1.050v iod and 1.000v ccd with 1.15v soc I still get random reboots in aida64 memory latency and cache test.
> Any tips?


Does that happen if you remove the ram overclock and test with stock settings?


----------



## Kha

Blackfyre said:


> What makes you think Windows 11 is that bad? Or bad at all? Have you tried it yourself?


There can be no W11 with "never combine buttons" missing, period. Not for me anyway.


----------



## ArchStanton

VPII said:


> I needed to up the vdimm to 1.49 in the bios. Dimm temps are fine, nothing to worry about but at leats it is working. MY latency is nowhere near yours but it is better for me regardless.


Seems very reasonable to me (but I am still just beginning to tune RAM). Latency is highly influenced by both all the things Windows is up to in the background and how high the overclock can be pushed (while remaining stable) on your CPU (I do have a number of Windows features uninstalled, my network cable unplugged, and manually killed a few unneeded processes in Task Manager, I do all this both to improve scores in AIDA, but more so to try and limit variance, since CPU boost is temperature dependent, you will see better AIDA scores when "cold") . So, I think I'm correct in saying "always compare your results to your previous" not to others here on the forum. They may have a much better sample to play with.


----------



## 67091

tcclaviger said:


> Where I ended up for daily setup. Had run PT10 without clearing HWinfo, max values reflect PT10.
> 
> Seems reasonably good for daily. With 1 CCD instead of 2 active latency drops to ~51.5ns.
> View attachment 2554381


Where is everybody getting the absolute config for TM5? Don't worry I found it.


----------



## The_King

Taraquin said:


> I would do 1.45v+232  RC also scales with voltage so you can try going a bit lower on that aswell, just keep rc=ras+rp. 25+13=38, 24+13=37 etc. Usually ras can't go below 21 or 22 så 34/35 rc is lowest.


I am not sure if I should change RRDL 6 and TWR 12 or just leave it the way it is?


----------



## Taraquin

The_King said:


> I am not sure if I should change RRDL 6 and TWR 12 or just leave it the way it is?
> 
> View attachment 2554626


I would change them, but might not matter at all


----------



## Alastair

I could use some guidance if anyone is willing to assist.

I have posted before. But kind of gave up and just ran my memory at its XMP settings. I decided to give memory OCíng another bash.

To summarize my hardware.
Ryzen 3800X
Aorus X570 Pro Wifi
32GB 4x8GB Avexir Core 2 3600 18-20-20-44 memory. Samsung C-die's

I spent some time with them. Managed to boot them at 3800 18-21-21-21-44 2 T with an 1900fclk. It is unstable as heck. And would like some guidance from here on how to stabilize them as once I have primaries I have no idea where to go with the secondaries and tertiaries and also the various cadbus, drive strength and procodt settings.

Where I stand so far. Asides from primaries almost everything else is auto.

















To add. Vsoc is 1.1V. Adding any more doesnt seem to help.
DRAM is at 1.35 according to my DMM

edit 2: Dram calculator is little use to me as it has no c-die guidance. And OEM guidance only goes as far as 3533.


----------



## Bloax

Alastair said:


> 32GB 4x8GB Avexir Core 2 3600 18-20-20-44 memory. Samsung C-die's


Here's someone's cute C-Die config, maybe it will help - though bear in mind it is 2x8 instead of 4x8


----------



## Alastair

Bloax said:


> Here's someone's cute C-Die config, maybe it will help - though bear in mind it is 2x8 instead of 4x8
> View attachment 2554724


I don't want to necessarily start changing values willy nilly to try copy what someone else is doing. What I really want is to gain understanding as I go along. As an example I have no idea what the cadbus does short on a high level Google explanation. So I want to learn what I am doing without just doing it. 

So I see some areas where his differs to mine. So would I start messing around with secondaries and tertiaries first or mess with drive strengths and cadbus setting.


----------



## Imprezzion

So, basically I have a choice now. Stay on 1.2.0.3c with good memory OC and very stable PBO2 CO OC for the CPU and suffer the horrible fTPM stuttering (I run Windows 11 beta channel) or update to the new 1.2.0.6b that just got released for my board and later on 1.2.0.7 to fix fTPM stuttering but have to redo my entire RAM OC, probably not get the same results, and lose a massive chunk of voltage for PBO2... 

12900K is interesting but power draw is way too high and even with DDR4 the boards cost a absolute fortune for a midrange board.

Hell, I might even try to find a cheap used Z590 high-end board and a 11900K...


----------



## Blackfyre

Imprezzion said:


> So, basically I have a choice now. Stay on 1.2.0.3c with good memory OC and very stable PBO2 CO OC for the CPU and suffer the horrible fTPM stuttering (I run Windows 11 beta channel) or update to the new 1.2.0.6b that just got released for my board and later on 1.2.0.7 to fix fTPM stuttering but have to redo my entire RAM OC, probably not get the same results, and lose a massive chunk of voltage for PBO2...


I have never lost RAM stability with upgrading BIOS, if anything stability is usually better for RAM. I always run latest, even Beta BIOS versions on my X570 Hero

But yes, you lose a bit in terms of CPU performance compared to 1.2.0.3c

Nothing major really, CPU runs cooler too with the lower voltages. And who knows, maybe they fix some of the voltage & CPU performance issues with 1.2.0.7 coming out next month.

You can always go back to your old settings.

PS: You can backup all BIOS settings on a USB, update BIOS, load BIOS settings from USB. (Make sure you save 2 copies with F2 I think, and CTRL + F2).

If you do go back to 1.2.0.3c you can load your BIOS settings from the USB too. Save yourself time.


----------



## 97pedro

Any way I can improve the latency on this kit?

Flare X 3200mhz cl14


----------



## TimeDrapery




----------



## 97pedro

TimeDrapery said:


> View attachment 2554802
> 
> View attachment 2554804
> 
> View attachment 2554806


That latency drop was only from reduning TRAS and TRC?


----------



## TimeDrapery

Spoiler






97pedro said:


> That latency drop was only from reduning TRAS and TRC?






That change in latency resulted from that reduction in the primary timings as well as regular old deviation between testing iterations... These two timings (tRAS and tRC) do carry with them a goodly impact relative to what you'll see after adjusting some of the other (primary/secondary/tertiary) timings though

The first timing set (15-15-15-35-50) is commonly seen in XMP profiles (granted, my secondary/tertiary timings are "very tight"...) whereas the second timing set is similar but with the "additional latency" removed from the primary timings whilst keeping the memory running at the same VDIMM (1.480V "_set_" within BIOS/UEFI)

The idea of posting the screenshots is to illustrate what people "leave on the table" (performance-wise) when either setting and forgetting XMP (especially with well binned DIMM kits) or when haphazardly reducing timings (or copy/pasta someone else's timing set because they're running a "similar" kit)

There's too much variance on one DIMM alone (between ICs) to rely on what others have done with their kits to guide your OC...


----------



## 97pedro

Hello all,

Is this voltage related?


----------



## Blackfyre

97pedro said:


> Hello all,
> 
> Is this voltage related?
> View attachment 2554874


In my opinion, stay away from 1933 FCLK and 1966 FCLK, very rare for someone to run stable 1:1:1 on that FCLK. 

I can run 2000 loose timings, and 1800 very tight timings. And 1800 tight timing is better in 95% of cases. 1800 FCLK, being 3800Mhz RAM at 1:1:1 (MCLK, FCLK, UCLK).


----------



## Blackfyre

Taraquin said:


> Impressive, unusal that 20 20 20 20 works at 1t gdm off. You have good phyl aswell (unless it's 28 on some sticks?). Probably very little you can tweak left. Good result!


*Managed to squeeze more out and lower voltage slightly to 1.495v 
Also run a long test overnight (*_43 cycles of 1usmus v3_*) to confirm stability (*_5+ hours_*).

tRFC* down from 560 to *552* (_Tested 544, and crashed within 10 to 15 cycles_).
*tRAS* down from 38 to *30 *(_Tested 34 for 10+ cycles, then tested 30 for 43 cycles_).

Maybe I can still lower tRAS more, but there's no need I believe as I am running it perfectly with the formula *tCL + tRCDRD = tRAS (*14 + 18 = 30*).*

I'm sure there are other sub-timings I can now tweak slightly more, but won't see realistic gains. As I am close to peak with these 4 dimms.










*Currently testing with tRCDRD at 17 and tRAS at 31 (*14+17=31). *Have not stress tested this yet: tRCDRD @ 16 crashes as soon as Windows boots.*


----------



## Baio73

That's one thing I didn't expect to happen... hope someone may explain in a reasonable way.
This is the final setting I reached after a couple of weeks of deep testing with TM5 and Karhu RAM Test... obviously it was 100% rock solid:



Last week I installed my new VGA (6900 XT) and had many issues at boot... the pc didn't recognize the keyboard and mouse and could not enter the BIOS. Went through a couple of reflashes and finally understood that with the new VGA my pc does not power up the USB ports as before, some ports get power on boot, others don't (I ended up swapping keyboard and mouse cables around, so now it works, disabling fast boot didn't help).

Long story short, the above OC does not work anymore... I've started over testing (first errors in TM5 are n.11 and 12) but can someone explain me what happened??
Am I supposed to begin first with voltages again?

Baio


----------



## Taraquin

Blackfyre said:


> *Managed to squeeze more out and lower voltage slightly to 1.495v
> Also run a long test overnight (*_43 cycles of 1usmus v3_*) to confirm stability (*_5+ hours_*).
> 
> tRFC* down from 560 to *552* (_Tested 544, and crashed within 10 to 15 cycles_).
> *tRAS* down from 38 to *30 *(_Tested 34 for 10+ cycles, then tested 30 for 43 cycles_).
> 
> Maybe I can still lower tRAS more, but there's no need I believe as I am running it perfectly with the formula *tCL + tRCDRD = tRAS (*14 + 18 = 30*).*
> 
> I'm sure there are other sub-timings I can now tweak slightly more, but won't see realistic gains. As I am close to peak with these 4 dimms.
> 
> View attachment 2554886
> 
> 
> *Currently testing with tRCDRD at 17 and tRAS at 31 (*14+17=31). *Have not stress tested this yet: tRCDRD @ 16 crashes as soon as Windows boots.*
> 
> View attachment 2554893


I would stick with RAS+RP=RC, I have not seen better perg just lowering RAS as it needs to wait for RP to get to RC anyways. I noticed on my kit that on 3500 I need to raise rrds to 5 and faw to 20 for rcd 18 to work. Anta777 suggest keeping RCDRD and RP equal on all kits, this makes both RCDRD+CL=RAS and RAS+RP=RC add up, but I lose perf using that high RP. On Hynix RP sucks so it works better, but on Micron and low end Samsung like C/D lower RP can help but screws up the formulae. 

Stock
3000cl15-16-16

For every 200MHz I must raise RCDRD by 1, 3800 is no go at 19, 3733 works with 19. If you get slight trouble with RCDRD 17 at 3800 try RRDS/L 5/7 and FAW 20. RCDRD matters a bit more. If you get RCDRD 17 stable at 3800 you are in bad bin B-die territory, impressive! Too bad rev E sucks at RFC and RC :/

One of my kits do 536 at 3800, other needs 560.

RC can impact perf quite much, see if you get that lower, maybe 50-52 can go, 58 was lowest for my kit at 3800.


----------



## Koekieezz

Hello, first posting here. I had hands on my friend's 5600G, and i tried to quick OC it, i think it's not that much good? Ram kit is Vcolor Prism Pro RGB 3600 CL18, Using Hynix DJR-VKC according thaiphoon burner report.








Also could i ask? His motherboard is an *Asrock B450M Steel Legend* using bios *4.20*, set manually llc for both cpu and soc at lvl 3 (tbh i dont know what is the best value). All of this is prooven stable as i did it with furmark dynamic camera (yes, using a 3060), so pretty much making the case more hotter to find a good stability, i could only do 4133 C18 stable as this is a quick oc since my friend's picking this pc up today. The main problem is, if the PC got no electricity (or electricity got cut off), when i try to boot up, it boots up like memory fail oc etc etc.

If i restart and shutdown many times, the pc would boot up fine, as long the electricity is not cut off. I wonder if this is the CMOS battery is almost dead, and made the bios corrupt, or is there something else in the mobo? Please let me know


----------



## Taraquin

Blackfyre said:


> In my opinion, stay away from 1933 FCLK and 1966 FCLK, very rare for someone to run stable 1:1:1 on that FCLK.
> 
> I can run 2000 loose timings, and 1800 very tight timings. And 1800 tight timing is better in 95% of cases. 1800 FCLK, being 3800Mhz RAM at 1:1:1 (MCLK, FCLK, UCLK).


If he has no WHEA 19 and tune VDD18 he may get better perf, but I bet his RDWR is a bit too low, 9 is easier to get working. Very few 2 CCDs on 4 DIMM mobos can do above 1933fclk and gain perf so you are probably right.


----------



## Taraquin

Baio73 said:


> That's one thing I didn't expect to happen... hope someone may explain in a reasonable way.
> This is the final setting I reached after a couple of weeks of deep testing with TM5 and Karhu RAM Test... obviously it was 100% rock solid:
> 
> 
> 
> Last week I installed my new VGA (6900 XT) and had many issues at boot... the pc didn't recognize the keyboard and mouse and could not enter the BIOS. Went through a couple of reflashes and finally understood that with the new VGA my pc does not power up the USB ports as before, some ports get power on boot, others don't (I ended up swapping keyboard and mouse cables around, so now it works, disabling fast boot didn't help).
> 
> Long story short, the above OC does not work anymore... I've started over testing (first errors in TM5 are n.11 and 12) but can someone explain me what happened??
> Am I supposed to begin first with voltages again?
> 
> Baio


What is your ram voltage? It reads as 1.25v. I would change some timings, try scls at 4, rdwr 9, wrrd 3, rfc 256 or 272.


----------



## kratosatlante

97pedro said:


> Hello all,
> 
> Is this voltage related?
> View attachment 2554874


I have similar timings now, first get 8 error, only up vdim from 1.50v to 1.53 and get stable, see your vdim vdrop, i set 1.53v in bios but hwinfo said dram voltaje (vrm) 1.53 and dram voltaje is 1.493 max 1.503v , try first up 0.1v by step, and then this config
pll 1.85v









this is with other cpu 5600x not same vddp, vddg io cd and vsoc
pll v 1.87 set (get 1.897)


----------



## Taraquin

Koekieezz said:


> Hello, first posting here. I had hands on my friend's 5600G, and i tried to quick OC it, i think it's not that much good? Ram kit is Vcolor Prism Pro RGB 3600 CL18, Using Hynix DJR-VKC according thaiphoon burner report.
> View attachment 2554897
> 
> Also could i ask? His motherboard is an *Asrock B450M Steel Legend* using bios *4.20*, set manually llc for both cpu and soc at lvl 3 (tbh i dont know what is the best value). All of this is prooven stable as i did it with furmark dynamic camera (yes, using a 3060), so pretty much making the case more hotter to find a good stability, i could only do 4133 C18 stable as this is a quick oc since my friend's picking this pc up today. The main problem is, if the PC got no electricity (or electricity got cut off), when i try to boot up, it boots up like memory fail oc etc etc.
> 
> If i restart and shutdown many times, the pc would boot up fine, as long the electricity is not cut off. I wonder if this is the CMOS battery is almost dead, and made the bios corrupt, or is there something else in the mobo? Please let me know


Could be cold boot problems or training issues. I would consider changing some timings to see if it helps:
Scls to 4, rdwr to 10. What voltage is ram running at? If 1.35v xmp try 1.45v.


----------



## Bloax

> There's too much variance on one DIMM alone (between ICs) to rely on what others have done with their kits to guide your OC...


There's clear evidence of Valid Settings(tm) varying from PCB to PCB - for example the people using high-end dual-rank b-die kits running WTRL 8 above 3600 MT/s.
But I haven't seen evidence that the same PCB, with the same kind of memory ICs, varies in more than silicon lottery of Voltage Requirement and Maximum Primary Timing/RFC Tightness.
Which is good, as that gives some sort of consistency to this "throw **** at the wall until it sticks" procedure.🤡👌



Alastair said:


> I don't want to necessarily start changing values willy nilly to try copy what someone else is doing. What I really want is to gain understanding as I go along. As an example I have no idea what the cadbus does short on a high level Google explanation. So I want to learn what I am doing without just doing it.
> 
> So I see some areas where his differs to mine. So would I start messing around with secondaries and tertiaries first or mess with drive strengths and cadbus setting.


CADBus affects the signal power of various signal operations.. And what the requirements for those are - _we have no clue_, so random **** gets thrown at the wall until it works.
ProcODT and RTT are the counterpoint of the signal drive-strength, affecting the termination of signals instead.. And how those two interact, how they affect the signal - those are things which require fancy lab equipment to see, and Our Gracious Corporate Overlords think the customer unworthy of being shown such things. 🤡

Ergo, these things affect the signal generation, and signal termination.. But how this applies to your setup, is complete guesswork! 💪🤡

The one thing about C-Die that seems to be suggested from this single instance of someone getting it to run decently, is that it wants a very low procODT - as B-Die sticks typically want an increased CPU 1.8v (DRAM Input Voltage, around 1.86-1.93v) to properly run a low procODT, whereas this screenshot was at 1.8v.


----------



## Alastair

Bloax said:


> There's clear evidence of Valid Settings(tm) varying from PCB to PCB - for example the people using high-end dual-rank b-die kits running WTRL 8 above 3600 MT/s.
> But I haven't seen evidence that the same PCB, with the same kind of memory ICs, varies in more than silicon lottery of Voltage Requirement and Maximum Primary Timing/RFC Tightness.
> Which is good, as that gives some sort of consistency to this "throw **** at the wall until it sticks" procedure.🤡👌
> 
> 
> CADBus affects the signal power of various signal operations.. And what the requirements for those are - _we have no clue_, so random **** gets thrown at the wall until it works.
> ProcODT and RTT are the counterpoint of the signal drive-strength, affecting the termination of signals instead.. And how those two interact, how they affect the signal - those are things which require fancy lab equipment to see, and Our Gracious Corporate Overlords think the customer unworthy of being shown such things. 🤡
> 
> Ergo, these things affect the signal generation, and signal termination.. But how this applies to your setup, is complete guesswork! 💪🤡
> 
> The one thing about C-Die that seems to be suggested from this single instance of someone getting it to run decently, is that it wants a very low procODT - as B-Die sticks typically want an increased CPU 1.8v (DRAM Input Voltage, around 1.86-1.93v) to properly run a low procODT, whereas this screenshot was at 1.8v.


By low procODT do you mean low lower or higher resistance values since its measured in ohms?


----------



## Alastair

At this point I am throwing random sh... I mean stuff at the wall I've increased ODT to 60ohm and clkdrvstr to 40ohm


----------



## 97pedro

Taraquin said:


> If he has no WHEA 19 and tune VDD18 he may get better perf, but I bet his RDWR is a bit too low, 9 is easier to get working. Very few 2 CCDs on 4 DIMM mobos can do above 1933fclk and gain perf so you are probably right.


Hello there!!
I get no WHEA erros but only because my crosshair VII Hero board throws out 2.1v PLL in auto setting, 2.0v won't work without WHEA erros. I guess that the board can handle the 2.1v PLL since it sets it automatically..
Should I set RDWR to 9?
Sorry for the probabily easy to answer question, but what is VDD18?
The errors I had after 40 minutes of TM5 were Vdimm related?

EDIT: Ok I'm an idiot, VDD18 it's the same as 1.8v PLL. But still, any tips to get 1933mhz working without errors?


----------



## Bloax

Alastair said:


> By low procODT do you mean low lower or higher resistance values since its measured in ohms?


I do mean a low numerical representation of the impedance, so "low" would be 28.2-32 ohms 🤡


----------



## deadfelllow

Blackfyre said:


> *Managed to squeeze more out and lower voltage slightly to 1.495v
> Also run a long test overnight (*_43 cycles of 1usmus v3_*) to confirm stability (*_5+ hours_*).
> 
> tRFC* down from 560 to *552* (_Tested 544, and crashed within 10 to 15 cycles_).
> *tRAS* down from 38 to *30 *(_Tested 34 for 10+ cycles, then tested 30 for 43 cycles_).
> 
> Maybe I can still lower tRAS more, but there's no need I believe as I am running it perfectly with the formula *tCL + tRCDRD = tRAS (*14 + 18 = 30*).*
> 
> I'm sure there are other sub-timings I can now tweak slightly more, but won't see realistic gains. As I am close to peak with these 4 dimms.
> 
> View attachment 2554886
> 
> 
> *Currently testing with tRCDRD at 17 and tRAS at 31 (*14+17=31). *Have not stress tested this yet: tRCDRD @ 16 crashes as soon as Windows boots.*
> 
> View attachment 2554893


I have the same ram.(C9BLM i suppose). On Micron Rev-E you can adjust trcdwr 8 trp 12 and tras 21 and works like a magic. Can you try that?


----------



## deadfelllow

Image below was stable 7/24


----------



## Alastair

Bloax said:


> I do mean a low numerical representation of the impedance, so "low" would be 28.2-32 ohms 🤡


I'll give lower numbers a shot.


----------



## Imprezzion

If I disable my fTPM in BIOS and my Windows 11 stops receiving updates. Is it possible to just turn on fTPM periodically to update Windows 11 and then just turn it off after that until AGESA 1.2.0.7 drops with the fTPM fixes? Or would that absolutely break Windows... The fTPM stuttering every half an hour or so drives me bloody insane in world of tanks / division 2.


----------



## Koekieezz

Taraquin said:


> Could be cold boot problems or training issues. I would consider changing some timings to see if it helps:
> Scls to 4, rdwr to 10. What voltage is ram running at? If 1.35v xmp try 1.45v.


ram was running at 1.4v, soc at 1.16~ ish (asrock does asrock thing) and at LLC level 3 for both VDDCR SOC and Core Voltage. The thing is this thing does happen the first time i finished the build. Power drained totally = this kind of looping like oc fail symptomps, even at stock speed (normal and xmp speed) it does this thing. Power not drained (pc off/shutted down, with fast boot disabled on power plan) and everything is fine.


----------



## Taraquin

97pedro said:


> Hello there!!
> I get no WHEA erros but only because my crosshair VII Hero board throws out 2.1v PLL in auto setting, 2.0v won't work without WHEA erros. I guess that the board can handle the 2.1v PLL since it sets it automatically..
> Should I set RDWR to 9?
> Sorry for the probabily easy to answer question, but what is VDD18?
> The errors I had after 40 minutes of TM5 were Vdimm related?
> 
> EDIT: Ok I'm an idiot, VDD18 it's the same as 1.8v PLL. But still, any tips to get 1933mhz working without errors?


2.1 on VDD18 sound very high, what do you need for 3800/1900? Try changing the timings I suggested, might help.


----------



## 97pedro

Taraquin said:


> 2.1 on VDD18 sound very high, what do you need for 3800/1900? Try changing the timings I suggested, might help.


For 3800mhz 1.8v is enough for not having any WHEA erros, though I think the AIDA64 restarting my PC during the cache and memory test might have to do with the VDD18.
Most likely at 1.9v on the VDD18 I would be enough for everything at 3800mhz.
2.0v on the VDD18 gives me WHEA errors at 3866mhz 1933mhz fclk, only at 2.1v do they go away.

My latency only drops from 53.9ns at 3800/1900 to 53.2ns at 3866/1933, so probabily won't be benefitial to run 1933mhz fclk anyways.

What do you think?


----------



## Taraquin

97pedro said:


> For 3800mhz 1.8v is enough for not having any WHEA erros, though I think the AIDA64 restarting my PC during the cache and memory test might have to do with the VDD18.
> Most likely at 1.9v on the VDD18 I would be enough for everything at 3800mhz.
> 2.0v on the VDD18 gives me WHEA errors at 3866mhz 1933mhz fclk, only at 2.1v do they go away.
> 
> My latency only drops from 53.9ns at 3800/1900 to 53.2ns at 3866/1933, so probabily won't be benefitial to run 1933mhz fclk anyways.
> 
> What do you think?


I would go 3800, high VDD18 increases heat and steals from your powerbudget.


----------



## TimeDrapery

Spoiler






Blackfyre said:


> *Managed to squeeze more out and lower voltage slightly to 1.495v
> Also run a long test overnight (*_43 cycles of 1usmus v3_*) to confirm stability (*_5+ hours_*).
> 
> tRFC* down from 560 to *552* (_Tested 544, and crashed within 10 to 15 cycles_).
> *tRAS* down from 38 to *30 *(_Tested 34 for 10+ cycles, then tested 30 for 43 cycles_).
> 
> Maybe I can still lower tRAS more, but there's no need I believe as I am running it perfectly with the formula *tCL + tRCDRD = tRAS (*14 + 18 = 30*).*
> 
> I'm sure there are other sub-timings I can now tweak slightly more, but won't see realistic gains. As I am close to peak with these 4 dimms.
> 
> View attachment 2554886
> 
> 
> *Currently testing with tRCDRD at 17 and tRAS at 31 (*14+17=31). *Have not stress tested this yet: tRCDRD @ 16 crashes as soon as Windows boots.*
> 
> View attachment 2554893






@Blackfyre 

"14 + 18 = 30" ... 😂😂😂😂😂😂😂😂😂😂

Yes... Everything is perfect


----------



## ArchStanton

@TimeDrapery if it works it works 🤣


----------



## TimeDrapery

ArchStanton said:


> @TimeDrapery if it works it works 🤣


Yessir, that's the truth forreal 😂😂😂😂😂


----------



## TimeDrapery

Spoiler






Bloax said:


> There's clear evidence of Valid Settings(tm) varying from PCB to PCB - for example the people using high-end dual-rank b-die kits running WTRL 8 above 3600 MT/s.
> But I haven't seen evidence that the same PCB, with the same kind of memory ICs, varies in more than silicon lottery of Voltage Requirement and Maximum Primary Timing/RFC Tightness.
> Which is good, as that gives some sort of consistency to this "throw **** at the wall until it sticks" procedure.🤡👌






@Bloax 

"There's clear evidence of Valid Settings(tm) varying from PCB to PCB - for example the people using high-end dual-rank b-die kits running WTRL 8 above 3600 MT/s"

My kits (which run the tWTRS timing at "8") were cobbled together from the "best" (for my purposes) DIMMs out of quite a few 3200MT/s (that's a "low" bin) G.Skill kits that I binned over a period of some weeks...

There's variance on the same PCB... You have, in fact, seen evidence of this when you produce errors at different points in testing without having changed settings and, yes, this is the "silicon lottery" which is exactly what I was referring to...

Most people don't realize this extends to the lengths it does as they don't often do things like run a single DIMM in an attempt to "bin" their own "kits"

100% there are valid settings that span a range of DIMMs (with regards to IC / PCB)... Also 100% your DIMMs differ from each other in ways you won't see until you explore OC limits further by configuring different timings/voltages

This doesn't mean, whatsoever, that there's no order to the madness... It means each and every person's madness is unique to them 😂😂😂😂😂

Basically, from what I've read, you and I are saying the same thing


----------



## TimeDrapery

Alastair said:


> By low procODT do you mean low lower or higher resistance values since its measured in ohms?


28.2Ω


----------



## 97pedro

Since I can't stabilize 1933mhz fclk.

What should I try to lower here?









Can WR, Wtrl and Wtrs go lower?


----------



## TimeDrapery

97pedro said:


> Since I can't stabilize 1933mhz fclk.
> 
> What should I try to lower here?
> View attachment 2555014
> 
> 
> Can WR, Wtrl and Wtrs go lower?


You could try to drop SCLs to "2", WTRS/L _could_ run at less than "4/10" although I'd likely accept where they're at and increase RDDL to "5" instead...

You'll hate to hear it but your primary timings are ate up like a soup sandwich... Try running flat 15s, tightening secondary / tertiary timings, and then (once stability is no longer disproven rapidly via testing [can't "prove" stability... Only instability]) revisit the primary timings and attempt tightening them further

Overclocking this way is going to give you a lot less of a headache than just trying to work random timings down

The fact they're referred to as memory "timings" does indicate a relationship between the operations taking place during usage of the PC... Just because you and I don't _understand_ the correlations _*doesn't*_ mean they don't exist... Not understanding the correlations _*does*_ mean that operating systematically when overclocking memory is incredibly important


----------



## 97pedro

TimeDrapery said:


> You could try to drop SCLs to "2", WTRS/L _could_ run at less than "4/10" although I'd likely accept where they're at and increase RDDL to "5" instead...
> 
> You'll hate to hear it but your primary timings are ate up like a soup sandwich... Try running flat 15s, tightening secondary / tertiary timings, and then (once stability is no longer disproven rapidly via testing [can't "prove" stability... Only instability]) revisit the primary timings and attempt tightening them further
> 
> Overclocking this way is going to give you a lot less of a headache than just trying to work random timings down
> 
> The fact they're referred to as memory "timings" does indicate a relationship between the operations taking place during usage of the PC... Just because you and I don't _understand_ the correlations _*doesn't*_ mean they don't exist... Not understanding the correlations _*does*_ mean that operating systematically when overclocking memory is incredibly important


Thanks!
Flat 15s is impossible to be 100% stable in tm5.

My problem is RCDRD, anything lower than 17 isn't 100% stable.
You have any opinion on what I should set for the primaries?
Also WTRS/L maybe drop to 8/3?


----------



## Alastair

Bloax said:


> I do mean a low numerical representation of the impedance, so "low" would be 28.2-32 ohms 🤡


So lower procODT ended up worse for me. But I did find some success!

I have managed to get 3800Mhz stable on 3x runs of 1usmus Dram calculator memtest on easy mode.

YES, yes I know 120 seconds of stress testing is not a benchmark for stability. But it is significantly better than what I was managing. I was getting errors INSTANTLY. I will also continue to use Easy mode for my tuning as I need something that I can run quick tests on so I don't waste entire HOURS between changes of settings.

So what have I done to get this far?

I have been messing around with various combinations of ProcODT, Drive strengths and RTT settings.

I have discovered that my particular CPU/DRAM combination seems to be preferring higher ODT settings.
ProcODT is at 48
RttNom at RZQ/7
RttWr at RZQ/3
RttPark at RZQ/4
ClkDrvStr at 120
AddrCmdDrvStr at 40
CsOdtDrvStr at 40
CkeDrvStr at 40

I have seen performance improvements so far. Aida reports 53GB/s / 30.5GB/s / 51.5GB/s @ 68ns.
1usmus Dram Easy settings went from 143 seconds at 3600 down to 140seconds at very unstable 3800 down to 135 seconds at this semi-stable 3800.

My progress thus far.


----------



## Blackfyre

TimeDrapery said:


> @Blackfyre
> 
> "14 + 18 = 30" ... 😂😂😂😂😂😂😂😂😂😂
> 
> Yes... Everything is perfect


Oh shiiii....


----------



## TimeDrapery

Spoiler






97pedro said:


> Thanks!
> Flat 15s is impossible to be 100% stable in tm5.
> 
> My problem is RCDRD, anything lower than 17 isn't 100% stable.
> You have any opinion on what I should set for the primaries?
> Also WTRS/L maybe drop to 8/3?






You're welcome! When doing an OC like yours I prefer to get my primary timings lined out first, tighten stuff in the secondaries/tertiaries, and then revisit the primaries

So, in your case, I'd give a flat set a shot (whatever runs without errors, perhaps 16-16-16-36-52...?) with everything else on "Auto", find the lowest VDIMM I could run the primaries at without producing errors, then proceed to tightening secondaries/tertiaries (for example, in your case you could certainly try running 4-4 / 3-8 although I'd go as loose as 5-7 / 5-14 [at 3800 MT/s] if you're finding the DIMMs uncooperative) before returning to the primaries and seeing what can come down further from my baseline using voltage / differing resistances

Truly though... If you're running 4×8GB DIMMs you'll likely benefit from "binning" the sticks by finding tightest primaries and least voltage for each DIMM by running em individually

Doing this will allow you to find the weak sticks and stick em in the stronger slots whilst the stronger DIMMs kick it in the weak slots which should give you a better shot at attaining your OC goals


----------



## TimeDrapery

Spoiler






Blackfyre said:


> Oh shiiii....






@Blackfyre 

😂😂😂😂😂😂😂😂😂, this made my day... Thanks new homie!!!


----------



## Blackfyre

TimeDrapery said:


> Truly though... If you're running 4×8GB DIMMs you'll likely benefit from "binning" the sticks by finding tightest primaries and least voltage for each DIMM by running em individually
> 
> Doing this will allow you to find the weak sticks and stick em in the stronger slots whilst the stronger DIMMs kick it in the weak slots which should give you a better shot at attaining your OC goals


I've never thought about it this way. But damn that will take a long time to do 😔☹


----------



## Blameless

Regarding DIMM PCB quality...this can be very hard to separate from motherboard quality, without other points of reference. My current best board (which, since my ASUS Crosshair VIII Impact anheroed itself, is an ASrock B550 Phantom Gaming ITX/ax) can quite reliably do tWTR_L one cycle tighter and tRDWR two full cycles tighter than my $80 MSI B550M Pro VDH Wifi...with all other hardware and settings being identical (or as close to identical as possible).



Blackfyre said:


> I've never thought about it this way. But damn that will take a long time to do 😔☹


Four sticks is pretty easy, especially with bootable tests.

I like to use Memtest86 for this, because even though it's not a great stress test overall, it's more than good enough to find out if a stick is better or worse than another once you know where the edge of stability for one is.


----------



## eighty20

Guys, which BGS should i use for 2x SR, in my bios it has 3 mode: cpu, alt and apu. I'm using 5700G on B550-i strix, latest bios. I found that switch to BGS ALT increase tPHYRDL to 28.


http://imgur.com/a/Mo1GHLJ

 I have these tested stable.


----------



## VPII

So At first when trying the 1.2.0.6c Agesa update my memory would not work, well I figured out that the memory cannot run 1T without Geardown enabled so I tried it again and now it seems okay. I would prefer no GD, but my memory won't work. Funny as the 4 x 8GB G-Skill Flare X 3200 CL14 I had worked without an issue.


----------



## Taraquin

97pedro said:


> Thanks!
> Flat 15s is impossible to be 100% stable in tm5.
> 
> My problem is RCDRD, anything lower than 17 isn't 100% stable.
> You have any opinion on what I should set for the primaries?
> Also WTRS/L maybe drop to 8/3?


Does 15 16 15 work? Your RDWR may interfere with low RCDRD. Try 9 or 10 RDWR, see if you can run RCDRD 16 or 15 then?


----------



## Taraquin

VPII said:


> So At first when trying the 1.2.0.6c Agesa update my memory would not work, well I figured out that the memory cannot run 1T without Geardown enabled so I tried it again and now it seems okay. I would prefer no GD, but my memory won't work. Funny as the 4 x 8GB G-Skill Flare X 3200 CL14 I had worked without an issue.
> View attachment 2555100


Set RTP to 6, RAS to 28 and RC to 42, should improve things. Your ProcODT is very high, try 40. If you try 24 20 24 24 you may be able to do 2t instead of gdm.


----------



## Melan

VPII said:


> So At first when trying the 1.2.0.6c Agesa update my memory would not work, well I figured out that the memory cannot run 1T without Geardown enabled so I tried it again and now it seems okay. I would prefer no GD, but my memory won't work. Funny as the 4 x 8GB G-Skill Flare X 3200 CL14 I had worked without an issue.
> View attachment 2555100


Did you manually set ProcODT to 60 or was it auto? Because on auto mobo seems to set 60 every time you make a change to command rate, but after full shutdown and restart it sets 36.9 again.


----------



## Blackfyre

These are pretty much the limits for my 4 dimms. Unless I do what one person suggested earlier, which is to take them out and individually check them 1 by 1 from highest quality to lowest, and then place the two strongest dimms in the weaker B slots and the two weaker dimms in the stronger A slots on the board and I might be able to push for 26 PHY for all 4 dimms that way. Instead of having 26 PHY on both A and 28 PHY on both B.

Aida results below (_probably my lowest ever_) on latest version of Windows 11 Beta/Dev, which came out yesterday. And *latest chipset drivers* which came out few days ago on AMD forums:

*4.03.03.624 WHQL [03/03/2022]*





[DRIVERS] AMD Chipset/RAID (3xx/4xx/5xx/6xx/TRX40)


Hi everyone, - AMD Chipset Drivers : Package : 4.11.15.342 WHQL Download : Link - AMD RAID Drivers (Drivers Only) : Drivers - NVMe - 6xx/TRX40 : 9.3.2.158 WHQL



rog.asus.com


----------



## Alastair

VPII said:


> So At first when trying the 1.2.0.6c Agesa update my memory would not work, well I figured out that the memory cannot run 1T without Geardown enabled so I tried it again and now it seems okay. I would prefer no GD, but my memory won't work. Funny as the 4 x 8GB G-Skill Flare X 3200 CL14 I had worked without an issue.
> View attachment 2555100


GDM enabled with 1T is 2T. So you are probably better off trying to get tighter secondaries and tertiaries with GDM off since GDM won't be rounding all your timing parameters up.


----------



## gameinn

@Audioboxer I got the 3600 14-14-14-34 G. Skill 32G RAM

I did 9 cycles of tm5 to make sure it was stable after changing tRC to 48 and TRRDS to 4 as per the extended XMP profile. Should I now lower voltage to see what it's stable at? I'm thinking something like 1.42v or even 1.40v?


----------



## VPII

Taraquin said:


> Set RTP to 6, RAS to 28 and RC to 42, should improve things. Your ProcODT is very high, try 40. If you try 24 20 24 24 you may be able to do 2t instead of gdm.


Hi not really sure what you mean with RTP, maybe TRP?? Ras I am sure you mean TRAS and RC you mean TRC but not really sure.


----------



## VPII

Melan said:


> Did you manually set ProcODT to 60 or was it auto? Because on auto mobo seems to set 60 every time you make a change to command rate, but after full shutdown and restart it sets 36.9 again.


Yes it is manually set based on Ryzen Dram Calculator.


----------



## Melan

VPII said:


> Hi not really sure what you mean with RTP, maybe TRP?? Ras I am sure you mean TRAS and RC you mean TRC but not really sure.


tRTP
On your previous screenshot you have it at 8. It's below tCWL.



VPII said:


> Yes it is manually set based on Ryzen Dram Calculator.


Honestly, I've had much better luck just ignoring resistance settings from dram calc and just let the board figure it out. It did a good job so far.


----------



## KedarWolf

X570 AORUS MASTER (rev. 1.0) Support | Motherboard - GIGABYTE Global 

New chipset drivers.


----------



## Taraquin

VPII said:


> Hi not really sure what you mean with RTP, maybe TRP?? Ras I am sure you mean TRAS and RC you mean TRC but not really sure.


TRPT, TRAS and TRC. I just ditch the T since it applies to all timings. No I don't mean TRP, there is a timings called TRTP


----------



## domdtxdissar

Confirmed test done at 720p

__ https://twitter.com/i/web/status/1512151405615849477_edit_
12900KS - 200 fps average
5800X3D - 231 fps average









__ https://twitter.com/i/web/status/1512210556278624262Maybe i need to get one after all


----------



## Taraquin

VPII said:


> Yes it is manually set based on Ryzen Dram Calculator.


Dram calc works okay for Ryzen 3000 and Micron rev E, but it sucks for Ryzen 5000 (too high ProcODT, wrong resistances etc), it always suckd for B-die and suggested too low voltages for gdm off.


----------



## Taraquin

domdtxdissar said:


> Confirmed test done at 720p
> 
> __ https://twitter.com/i/web/status/1512151405615849477_edit_
> 12900KS - 200 fps average
> 5800X3D - 231 fps average
> View attachment 2555221
> 
> 
> __ https://twitter.com/i/web/status/1512210556278624262Maybe i need to get one after all


One major problem for us tweakers is that the large L3 cache compensates for ram tuning. My guesstimate is that around 10% is what to expect going from 3200cl16 to 3800cl14 on 5800X3D (maybe a bit more in some games). We saw the same goung from Zen 2 to 3 where you typically could gain up to 25% by tuning ram on Zen 2 while on Zen 3 around 20% seems more like ot. I think I saw the same on Alder lake aswell where ram tuning gives 12600K more than 12900K.

I really hope negative CO and maybe pbo is available on 5800X3D, allcore oc is not important.

Here showed in Star craft 2 with 3100 and 3300X. Only difference between them is double L3 cache on 3300X.


















The difference shrinks from +24% with 2666 ram to +13% with 3800 ram.


----------



## Imprezzion

Taraquin said:


> One major problem for us tweakers is that the large L3 cache compensates for ram tuning. My guesstimate is that around 10% is what to expect going from 3200cl16 to 3800cl14 on 5800X3D (maybe a bit more in some games). We saw the same goung from Zen 2 to 3 where you typically could gain up to 25% by tuning ram on Zen 2 while on Zen 3 around 20% seems more like ot. I think I saw the same on Alder lake aswell where ram tuning gives 12600K more than 12900K.
> 
> I really hope negative CO and maybe pbo is available on 5800X3D, allcore oc is not important.
> 
> Here showed in Star craft 2 with 3100 and 3300X. Only difference between them is double L3 cache on 3300X.
> 
> View attachment 2555223
> 
> View attachment 2555222
> 
> 
> The difference shrinks from +24% with 2666 ram to +13% with 3800 ram.


I'm quite interested as well in this chip as all I do is game on this rig so if it does perform better then a 5900X I will obviously upgrade.

I wonder if PBO / CO will be available as well and IF it is what the voltage limits will be with AGESA 1.2.0.7. It would be a real shame if we can't OC it especially since I run custom water and have the headroom for it.

I also wonder how much of a negative impact this L3 has on FCLK. There's always a chance that it will not do 1800+ whatsoever which would hamper it pretty badly.


----------



## Taraquin

Question for those of you who can't get above 3733 WHEA19 free, have you tried increasing VDD18? I've seen several people being able to get higher fclk by raising VDD18. For me I need higher VDD18 (+80mv) to get good scaling above 1900fclk. Seems this is a contributing factor to both perf and WHEA19 at high fclk.


----------



## Baio73

Taraquin said:


> Question for those of you who can't get above 3733 WHEA19 free, have you tried increasing VDD18? I've seen several people being able to get higher fclk by raising VDD18. For me I need higher VDD18 (+80mv) to get good scaling above 1900fclk. Seems this is a contributing factor to both perf and WHEA19 at high fclk.


I tried VDD up to 2.1v but got no luck with 2000 FLCK. Auto setting (1.8) is good for 1900 without WHEAs.
Someone said that that VDD is very dangerous and can not only raise T very much, but also bring bad readings from BIOS.

Baio


----------



## Audioboxer

gameinn said:


> @Audioboxer I got the 3600 14-14-14-34 G. Skill 32G RAM
> 
> I did 9 cycles of tm5 to make sure it was stable after changing tRC to 48 and TRRDS to 4 as per the extended XMP profile. Should I now lower voltage to see what it's stable at? I'm thinking something like 1.42v or even 1.40v?


What's your final goal in terms of frequency? Staying at 3600 or attempting 3800? Flat 14 at 3800 passed at 1.44v for me, I'd assume flat 14 at 3600 probably won't go much lower than 1.4v. You could try 1.38v.



domdtxdissar said:


> Confirmed test done at 720p
> 
> __ https://twitter.com/i/web/status/1512151405615849477_edit_
> 12900KS - 200 fps average
> 5800X3D - 231 fps average
> View attachment 2555221
> 
> 
> __ https://twitter.com/i/web/status/1512210556278624262Maybe i need to get one after all


Still feels like beta testing and I'd like to see chip thermals, but promising for the new generation Ryzen's.

I wonder if really fast system memory lowers this gap, as in, are these peak favourable testing conditions for AMD? 3200 RAM is not very impressive and goodness knows what the timings are.


----------



## Imprezzion

Audioboxer said:


> What's your final goal in terms of frequency? Staying at 3600 or attempting 3800? Flat 14 at 3800 passed at 1.44v for me, I'd assume flat 14 at 3600 probably won't go much lower than 1.4v. You could try 1.38v.
> 
> 
> 
> Still feels like beta testing and I'd like to see chip thermals, but promising for the new generation Ryzen's.
> 
> I wonder if really fast system memory lowers this gap, as in, are these peak favourable testing conditions for AMD? 3200 RAM is not very impressive and goodness knows what the timings are.


Probably 16-18-18 2T default XMP. That's what most reviewers test with anyway. Then again, running like, 6400C32 manual OC DDR5 on 12th gen or even 3866C14 Gear 1 DDR4 probably helps 12th gen easily as much.


----------



## Audioboxer

Doing some testing on AGESA 1.2.0.6c with +100 boost instead of +50. In the past I've felt +50 gave me better performance.

Anyway, I'm assuming a small difference between requested and effective isn't clock stretching, but just a core showing it's not quite capable of reaching a full +100 (5150mhz)?

Is clock stretching when there is a much larger difference? I just use BoostTester to run through each core individually.


----------



## kim nk

The most difficult CL13 TRP 12 TWR 10 TRTP 5 TRFC 240 DRAMVOLTAGE 1.56V TPHYRDL ALL 26 at 64GB and passed 10 cycles. The 3800 can be booted, but it is impossible to proceed. Two memory kits were used: CL14 4000 Royal Elite 16X2, CL14 3600 Royal Elite 16X2, and both two-sided rams are CL14 4000 14-14-14-14-28-42 REAL1T-enabled kits.




















trfc 224 dramvoltage 1.62v
Due to this surge in voltage requirements, trfc 240


I worked with my acquaintance on this test. Did you pass the stability test of 64GB from 3800 to CL13 to 14 TPHYRDL ALL 26?










In this situation, trrds 4-6 non-bootable tfaw 16-32 non-bootable The task of tightening the timing itself is impossible. Even if I tried to find the minimum boot value one by one, booting was possible only when trfc was tightened


----------



## Blackfyre

kim nk said:


> The most difficult CL13 TRP 12 TWR 10 TRTP 5 TRFC 240 DRAMVOLTAGE 1.56V TPHYRDL ALL 26 at 64GB and passed 10 cycles. The 3800 can be booted, but it is impossible to proceed. Two memory kits were used: CL14 4000 Royal Elite 16X2, CL14 3600 Royal Elite 16X2, and both two-sided rams are CL14 4000 14-14-14-14-28-42 REAL1T-enabled kits.
> 
> 
> 
> View attachment 2555239
> 
> 
> View attachment 2555240
> 
> 
> I worked with my acquaintance on this test. Did you pass the stability test of 64GB from 3800 to CL13 to 14 TPHYRDL ALL 26?
> 
> View attachment 2555241
> 
> 
> In this situation, trrds 4-6 non-bootable tfaw 16-32 non-bootable The task of tightening the timing itself is impossible. Even if I tried to find the minimum boot value one by one, booting was possible only when trfc was tightened


WOW great results.


----------



## gameinn

Audioboxer said:


> What's your final goal in terms of frequency?


3600 tbh. I know I can probably push more but all I want is my 5950x to routinely report less than like 59.5ns in aida64.


----------



## Luggage

gameinn said:


> 3600 tbh. I know I can probably push more but all I want is my 5950x to routinely report less than like 59.5ns in aida64.


Ive got the ripjaw version 3600 14-14-14 1.45V. gvka.
Should be same bin but not 100% sure.

Rcdrd is the weak link in my kit so I can’t bother trying tighter. But at 1.53V this is decent performance and rock stable.



http://imgur.com/zQgf7mI


----------



## ArchStanton

Luggage said:


> Ive got the ripjaw version 3600 14-14-14 1.45V. gvka


Same here (only using 32GB of 64GB kit).

















vDIMM for me set @1.48v, TM5x25 1usmus_v3 and 24hrs OCCT "stable"

I have no doubt the system is capable of better, but these are my "daily driver" settings while I continue to work my way through this thread and others (starting from "0" on learning to tune RAM)



gameinn said:


> all I want is my 5950x to routinely report less than like 59.5ns in aida64


Apologies if you have stated it previously and I have failed to notice or forgotten, the 5950X in question has been squeezed for all its worth through PBO2/CO or is more "stock"?


----------



## gameinn

ArchStanton said:


> Apologies if you have stated it previously and I have failed to notice or forgotten, the 5950X in question has been squeezed for all its worth through PBO2/CO or is more "stock"?


Pure stock besides 1800 fclk due to XMP.


----------



## ArchStanton

gameinn said:


> Pure stock besides 1800 fclk due to XMP.


I'm counting on others here to jump in and correct me if I'm wrong, but it will be a rare "bin" of 5950X that is sub 60ns without some OC'ing of the processor itself, I think. I would suggest you fire up HWiNFO64 concurrently with AIDA64 and watch the effective core clocks while AIDA64 does its thing. Being a newb, I was pretty surprised to see some of what is actually taking place. If I'm all wrong about my opening statement, I look forward to being lifted out of my ignorance by someone more knowledgeable .


----------



## KedarWolf

My second G.Skill Royal Elite CL14 3600 kit is a great bin. The first one couldn't pass the 3800 timings my CL16 kit could run.

This with RAM at 1.49v in BIOS and VTTs at .730v.

A preliminary test of usmus3 at 1000%, one cycle. But my past experience has shown me if it passes that, it'll pass anything I throw at it.




















ArchStanton said:


> Same here (only using 32GB of 64GB kit).
> View attachment 2555301
> 
> View attachment 2555302
> 
> 
> vDIMM for me set @1.48v, TM5x25 1usmus_v3 and 24hrs OCCT "stable"
> 
> I have no doubt the system is capable of better, but these are my "daily driver" settings while I continue to work my way through this thread and others (starting from "0" on learning to tune RAM)
> 
> 
> Apologies if you have stated it previously and I have failed to notice or forgotten, the 5950X in question has been squeezed for all its worth through PBO2/CO or is more "stock"?


Pretty happy with this, over 59k write, over 57k copy.


----------



## Blackfyre

I got inspired by the CL13 from earlier and decided to push some more. Couldn't get CL13 but I did reduce:

tRCDWR from 14 to 13
tRP from 14 to 13
tRAS from 30 to 29
tRC from 54 to 53
tWR from 14 to 12
tRTP from 7 to 6

tRFC2 down to lowest possible 60
tRFC4 down to lowest possible 60

I got 1 error in cycle 10 out of 31 cycles I let the test run.









*So I just upped:*

vDIMM from 1.50 to 1.515
VDDG CCD from 0.96 to 0.98
CLDO VDDP from 1.01 to 1.03
VDDG IOD from 1.01 to 1.03

^ Will test the above with a 50 cycles run tomorrow overnight.


----------



## shilka

Just wanted to ask if a RAM stick is bad if it has 1500 something errors in memtest86+ after about an hour?
Never had bad RAM in my life so i have no clue but all the bugs errors and system instability stopped after i took it out


----------



## 97pedro

KedarWolf said:


> My second G.Skill Royal Elite CL14 3600 kit is a great bin. The first one couldn't pass the 3800 timings my CL16 kit could run.
> 
> This with RAM at 1.49v in BIOS and VTTs at .730v.
> 
> A preliminary test of usmus3 at 1000%, one cycle. But my past experience has shown me if it passes that, it'll pass anything I throw at it.
> 
> View attachment 2555224
> 
> 
> View attachment 2555225
> 
> 
> 
> Pretty happy with this, over 59k write, over 57k copy.
> 
> View attachment 2555319


Nice! Why isn't tRP lower?


----------



## KedarWolf

97pedro said:


> Nice! Why isn't tRP lower?


I get better benchmarks running them 19-21 to match tRC at 40 rather than say 13-27. Easier to get stable too. 

@Veii mentioned trying something like that a long time ago and I've run it ever since. A bit earlier in the thread is AIDA64 at 19-21 then the post after at 13-27 and 19-21 benched a decent bit better.


----------



## 97pedro

KedarWolf said:


> I get better benchmarks running them 19-21 to match tRC at 40 rather than say 13-27. Easier to get stable too.
> 
> @Veii mentioned trying something like that a long time ago and I've run it ever since. A bit earlier in the thread is AIDA64 at 19-21 then the post after at 13-27 and 19-21 benched a decent bit better.


Figured that, currently I'm running 14-28 to get 42 tRC. Will try 18-24 to see how it goes, sadly I need the 42 tRC to get 252 tRFC, my kit won't do 240


----------



## KedarWolf

97pedro said:


> Figured that, currently I'm running 14-28 to get 42 tRC. Will try 18-24 to see how it goes, sadly I need the 42 tRC to get 252 tRFC, my kit won't do 240


It might only go as low as 19 so try 19-23 or it helps to cheat a bit and go 19-21, even though it breaks a timing rule, I get a bit better AIDA64 and latency when on my old kit I ran 19-21 and 42 tRC.


----------



## KedarWolf

KedarWolf said:


> It might only go as low as 19 so try 19-23 or it helps to cheat a bit and go 19-21, even though it breaks a timing rule, I get a bit better AIDA64 and latency when on my old kit I ran 19-21 and 42 tRC.


Actually, here's what I ran with 252 tRFC.


----------



## gameinn

@Audioboxer Ok that was pretty scary. I was seeing what the lowest possible voltage would be to be stable with. I didn't want to corrupt the OS so I was using memtest86 USB method.

I got down to 1.36v or so and was running memtets86 just expecting you know some errors to pop up after 5 minutes. No errors so I just said "meh let me try 1.35v and let that run for a full pass before I try tm5". I press esc on the keyboard and press restart (this worked previously at 1.38v etc). All of a sudden I got a message

WARNING ! ! ! BIOS recovery mode has been detected,

Please put file "C8DH.cap" into HDD or removable USB media device, and then reset the computer. You can also insert ASUS support CD to your CD-ROM and reset your computer, if you have done these, Please wait a moment and don't shutdown system!!!

System will be automatically rebooted.

Did what it said and..... nothing happened. I ended up just clearign cmos (the button was yellow on the back of the baord) and everything seemed fine after that. I flashed BIOS to be sure after doing "Load optimized defaults" but it was suspiciously quick. Like... 10 seconds quick. I guess it was the same BIOS version but still. Think lowering ram voltage bricked my BIOS.

I think that puts an end to my RAM OC journey. Like I just expected some errors to pop up in memtest86 not corrupt my BIOS beyond repair. Oh well.


----------



## KedarWolf

97pedro said:


> Nice! Why isn't tRP lower?


I've been tweaking. Some improvement with the below but it breaks known timing rules.


----------



## Phlereous

This fails TM5 anta777 extreme. Gives an error and PC crashes when test 7 is done. I am pretty sure it's tRFC. Is there a way to make it work or I just have to loosen it?


----------



## KedarWolf




----------



## Blameless

Phlereous said:


> View attachment 2555407
> 
> 
> This fails TM5 anta777 extreme. Gives an error and PC crashes when test 7 is done. I am pretty sure it's tRFC. Is there a way to make it work or I just have to loosen it?


~146ns should be doable with all but the worst binned B-die on most boards.

I would dial in your RTTs and drive strengths first. Perhaps try GDM disabled 2T, which seems easier to stabilize on some kits than GDM enabled. Also, not everything can do tRRDL 4.

You may need some more SoC, vDDG, and/or vDIMM.


----------



## Luggage

Phlereous said:


> View attachment 2555407
> 
> 
> This fails TM5 anta777 extreme. Gives an error and PC crashes when test 7 is done. I am pretty sure it's tRFC. Is there a way to make it work or I just have to loosen it?


tRFC runs on vdimm, hardly cares about anything else except being lowered in 8-s or 16-s depending on sr or dr.
Anta had a post about it a few months ago. edit: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## Taraquin

ArchStanton said:


> Same here (only using 32GB of 64GB kit).
> View attachment 2555301
> 
> View attachment 2555302
> 
> 
> vDIMM for me set @1.48v, TM5x25 1usmus_v3 and 24hrs OCCT "stable"
> 
> I have no doubt the system is capable of better, but these are my "daily driver" settings while I continue to work my way through this thread and others (starting from "0" on learning to tune RAM)
> 
> 
> Apologies if you have stated it previously and I have failed to notice or forgotten, the 5950X in question has been squeezed for all its worth through PBO2/CO or is more "stock"?


Easy improvements: ras 32 (ras+rp=rc), rtp 6 (half wr), wrwrscl 4, rfc might do 272 or 256 if your a lucky. Less important: wtrl 10 or maybe 8.

Next is 2t gdm off, after that 1t, but requires some work.


----------



## Phlereous

Luggage said:


> tRFC runs on vdimm, hardly cares about anything else except being lowered in 8-s or 16-s depending on sr or dr.
> Anta had a post about it a few months ago. edit: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread












This worked. I changed some other stuff but I guess it was the 1.5 VDIMM that did it. 
These threads are gold mines but how do you go through hundred of pages... Thanks a lot

What do I try to improve next? My CPU won't do 1900 FCLK and I get WHEAs on 1933, which I don't know if I can fix. So I can only look into timings.


----------



## Taraquin

Phlereous said:


> View attachment 2555427
> 
> 
> This worked. I changed some other stuff but I guess it was the 1.5 VDIMM that did it.
> These threads are gold mines but how do you go through hundred of pages... Thanks a lot
> 
> What do I try to improve next? My CPU won't do 1900 FCLK and I get WHEAs on 1933, which I don't know if I can fix. So I can only look into timings.


I would try 2t, gdm off and 15 15 15 30 45, change cwl to 14, rtp to 6, wrrd 3. If that works try 1t gdm off, but you must probably change drvstr, 40 20 24 24, 40 20 30 24 (like you have), 60 20 30 24 or 60 20 40 24 may work.


----------



## Viron

Here is 2 of the settings i run more or less on regular basis.
I could never quite figure out the tcrDRD, but think it might be cpu related? 
Not much differense in timings between 3800 (no wheas) and 2033 (lots of wheas). 
Using mostly 2033 to push for higher bench. Ram is on water monark cooling, with 12w/mK pads and 1,685V. (if Gskill can do 1,6V in any cabinett, i can do 1,685 on water) 
I have to say, if you have a custom loop and B die, get it watercooled, it is worth it. I been clocking harder on the 5900X lately, so not been working on the timings for a while.


----------



## Br3ach

Hey guys, there used to be a nice Google Sheet for calculating timings, incl. tRFC (not the mint tRFC calc, that one I have). Does anyone have the link? Ta


----------



## ArchStanton

@Taraquin Thanks, I'll be sure to try out your suggestions when I next find myself with some free time.


----------



## Alastair

So this is my progress on tightening up on my Avexir Core 2 3600s. Samsung C-die's

This kit of C-Die seems to come run pretty hard right out of the box. Bouncing off the red line so to speak. At stock XMP I can run Aida memory bench for half an hour as initial confirmation of basic stability. Even 3666 errors instantly. I am unsure if there is anyway I can get this memory to cooperate over 3600. 

I must admit I am a little disappointed with the gains I have made. I have seen very little improvement in AIDA 64 latency and bandwidth. My Geek3 memory scores went from 5500/6710 up to 5900/6900. (Which to be honest is very similar to the performance I saw at unstable 3800 18-21-21-42. So I guess there is some light on the horizon.

I could not BUDGE on TFAW. 38 is what I get at xmp. And if I set TFAW at 36 it was unstable. So no room to move on TFAW. I tried reducing at TRRDL X 4 increments as well. All unstable.

I see some people use CKE of 1. What benefit is there to modifying CKE? Can anyone guide here.

Here is a screenshot of my progress so far. Any inputs?

EDIT: Maybe my progress is being hampered by running 4 dimms?


----------



## Blackfyre

I don't know how or why, but I decided after I finished tightening 3800 Mhz and 1800 FCLK to just test 1833 FCLK and 3867 Mhz (_which was never successful in the past and always gave me WHEA errors_) and I managed to run 8 cycles of *1usmus v3* and used the PC for another few hours now without WHEA errors. Will push for 50 cycles over night to test long-term stability, but it certainly seems doable all of a sudden:


----------



## 97pedro

Blackfyre said:


> I don't know how or why, but I decided after I finished tightening 3800 Mhz and 1800 FCLK to just test 1833 FCLK and 3867 Mhz (_which was never successful in the past and always gave me WHEA errors_) and I managed to run 8 cycles of *1usmus v3* and used the PC for another few hours now without WHEA errors. Will push for 50 cycles over night to test long-term stability, but it certainly seems doable all of a sudden:
> View attachment 2555503


Been there, even without whea errors, at least for me, the level of stress in regards of voltages is not worth it for what 3866/1933 gives me, for me to have 100% stable 3866 I need to up trfc and Trcdrd, so at the end I prefer my low voltage better timings 3800mhz.
Get 53.8ns at 3800mhz and 53.2ns at 3866, the level os stress on everything is just not worth it


----------



## 97pedro

Blackfyre said:


> I don't know how or why, but I decided after I finished tightening 3800 Mhz and 1800 FCLK to just test 1833 FCLK and 3867 Mhz (_which was never successful in the past and always gave me WHEA errors_) and I managed to run 8 cycles of *1usmus v3* and used the PC for another few hours now without WHEA errors. Will push for 50 cycles over night to test long-term stability, but it certainly seems doable all of a sudden:
> View attachment 2555503


Also you seem to be braking timing rules at both tRAS+tRP for tRC and also tRFC doesn't match with your tRC.


----------



## Alastair

Here are my improvements thus far with my tuned configuration that I have gotten to so far



Spoiler: Tuned settings






Alastair said:


> So this is my progress on tightening up on my Avexir Core 2 3600s. Samsung C-die's
> 
> This kit of C-Die seems to come run pretty hard right out of the box. Bouncing off the red line so to speak. At stock XMP I can run Aida memory bench for half an hour as initial confirmation of basic stability. Even 3666 errors instantly. I am unsure if there is anyway I can get this memory to cooperate over 3600.
> 
> I must admit I am a little disappointed with the gains I have made. I have seen very little improvement in AIDA 64 latency and bandwidth. My Geek3 memory scores went from 5500/6710 up to 5900/6900. (Which to be honest is very similar to the performance I saw at unstable 3800 18-21-21-42. So I guess there is some light on the horizon.
> 
> I could not BUDGE on TFAW. 38 is what I get at xmp. And if I set TFAW at 36 it was unstable. So no room to move on TFAW. I tried reducing at TRRDL X 4 increments as well. All unstable.
> 
> I see some people use CKE of 1. What benefit is there to modifying CKE? Can anyone guide here.
> 
> Here is a screenshot of my progress so far. Any inputs?
> 
> EDIT: Maybe my progress is being hampered by running 4 dimms?
> View attachment 2555500






Here are my various improvements.



Spoiler: Aida.



Sock XMP










Tuned timings














Spoiler: Dram Membench Easy












142seconds is stock xmp
135seconds is unstable untuned 3800 18-21-21-42
128seconds is 3600 18-20-20-19-39 tuned subtimings.





Spoiler: Geek3



Stock 3600 xmp









Geek 3 3600 18-20-20-19-39 tuned.


----------



## Blackfyre

97pedro said:


> Been there, even without whea errors, at least for me, the level of stress in regards of voltages is not worth it for what 3866/1933 gives me, for me to have 100% stable 3866 I need to up trfc and Trcdrd, so at the end I prefer my low voltage better timings 3800mhz.
> Get 53.8ns at 3800mhz and 53.2ns at 3866, the level os stress on everything is just not worth it


That's the thing, those are all my tightest timings I could push with 3800Mhz. Only thing I changed was voltage from 1.495v to 1.51v which is nothing really. But previously I've got WHEA errors even with 1.55v trying 1933 FCLK, not sure now if it's the latest chipset drivers or the lowest resistance I am using on CAD BUS values or ProcODT. 

All my other voltages I would say are fairly average, I am not really pushing anything out of the ordinary to achieve these results.

Impossible for me to lower tRC beyond 54, even 52 gives me errors after 20 cycles at 3800Mhz. And there's no sense in increasing tRAS+tRP to make them match tRC. I achieve better latency and benchmark results with them being lower.


----------



## Blameless

Testing lower VDDP and VDDG voltages. Discovered I can hold a consistent 26/26 tPHYRDL with significantly less voltage than it took for my Hynix CJR, probably because of the much tighter primaries.

I'm also giving SLCs of 2 another shot. I couldn't pin down any performance benefit from 2 vs. 4 earlier, but looking at it again I think 2s may be training more consistently. Memtest86 test #7 is also finishing about a second earlier with 2 as opposed to 4, with some consistency.



gameinn said:


> @Audioboxer Ok that was pretty scary. I was seeing what the lowest possible voltage would be to be stable with. I didn't want to corrupt the OS so I was using memtest86 USB method.
> 
> I got down to 1.36v or so and was running memtets86 just expecting you know some errors to pop up after 5 minutes. No errors so I just said "meh let me try 1.35v and let that run for a full pass before I try tm5". I press esc on the keyboard and press restart (this worked previously at 1.38v etc). All of a sudden I got a message
> 
> WARNING ! ! ! BIOS recovery mode has been detected,
> 
> Please put file "C8DH.cap" into HDD or removable USB media device, and then reset the computer. You can also insert ASUS support CD to your CD-ROM and reset your computer, if you have done these, Please wait a moment and don't shutdown system!!!
> 
> System will be automatically rebooted.
> 
> Did what it said and..... nothing happened. I ended up just clearign cmos (the button was yellow on the back of the baord) and everything seemed fine after that. I flashed BIOS to be sure after doing "Load optimized defaults" but it was suspiciously quick. Like... 10 seconds quick. I guess it was the same BIOS version but still. Think lowering ram voltage bricked my BIOS.
> 
> I think that puts an end to my RAM OC journey. Like I just expected some errors to pop up in memtest86 not corrupt my BIOS beyond repair. Oh well.


I permanently bricked my Crosshair VIII Impact this way. RMAed it twice to have ASUS flash the board, then gave up when it did it again.

Anecdotally, ASUS in particular seems prone to this sort of thing. I've had memory OCs corrupt firmware NVRAM plenty of times, but never beyond the point of no return...except on a handful of my ASUS boards. At this point, I'm hesitant to buy another ASUS motherboard unless it has a dual BIOS with a physical jumper or switch, or at least a removable ROM chip.

Anyway, I was running into some FCLK and CO weirdness with my ASRock B550 Phantom Gaming ITX, probably from all the testing I've been doing, but was able to refresh it by q-flashing back to an old BIOS, then using flashrom to erase the firmware and then flash the last AGESA 1.2.0.3c firmware onto it, clean.



shilka said:


> Just wanted to ask if a RAM stick is bad if it has 1500 something errors in memtest86+ after about an hour?
> Never had bad RAM in my life so i have no clue but all the bugs errors and system instability stopped after i took it out


If this is stock (or even XMP on a platform that fully supports it) and you've ruled out board or CPU being the issue, a single error is a bad stick.



KedarWolf said:


> I get better benchmarks running them 19-21 to match tRC at 40 rather than say 13-27. Easier to get stable too.


I made an attempt at looser tRP + tighter tRAS to get the same tRC, but performance was always worse than the other way around.


----------



## shilka

Blameless said:


> If this is stock (or even XMP on a platform that fully supports it) and you've ruled out board or CPU being the issue, a single error is a bad stick.


I have two sticks number 1 was tested in B1 slot and gave 3 erros after 3,½ hours
Number two stick was tested in the same B1 and it came close to 1500 errors after only an hour

Nothing has been changed its an Asus X570 Strix-E motherboard with no OC on anything and XMP has been turned on
The system has been unstable for a while but i got a lot worse last week so i tested the RAM and found the results above

I have tested the good stick twice in B1 and it gave 3 errors which i have no idea if that is good or bad
I have not touched the CPU BIOS or or RAM in any way the only change i have done this year was taking the old RTX 2070 Super out to replace it with a Radeon RX 6800

Unless a bad RAM slot can damage RAM it seems to be the one stick that has gotten worse and worse
I have ordered a new RAM kit that should show up on tuesday


----------



## Blameless

shilka said:


> I have two sticks number 1 was tested in B1 slot and gave 3 erros after 3,½ hours
> Number two stick was tested in the same B1 and it came close to 1500 errors after only an hour
> 
> Nothing has been changed its an Asus X570 Strix-E motherboard with no OC on anything and XMP has been turned on
> The system has been unstable for a while but i got a lot worse last week so i tested the RAM and found the results above
> 
> I have tested the good stick twice in B1 and it gave 3 errors which i have no idea if that is good or bad


What happens if you test them in another slot?

Technically, XMP is an overclock, and if this is a fast kit, it could be pushing settings that the CPU/board cannot handle. One stick is clearly better than the the other, but that doesn't automatically imply the memory is incapable of rated clocks and timings at rated voltage, unless everything else is up to snuff.

What specific memory kit and CPU is this?


----------



## shilka

Blameless said:


> What happens if you test them in another slot?
> 
> Technically, XMP is an overclock, and if this is a fast kit, it could be pushing settings that the CPU/board cannot handle. One stick is clearly better than the the other, but that doesn't automatically imply the memory is incapable of rated clocks and timings at rated voltage, unless everything else is up to snuff.
> 
> What specific memory kit and CPU is this?


Its a 32 GB kit of 2x 16 GB G Skill TridentZ Neo 3600 MHz CL 16 sticks and i have not tried the good stick in the slot that might be bad because i am pretty sure the system wont boot if there is not a stick in slot B1

The kit i have ordered is a 16 GB G Skill TridentZ AMD Edition 3600 MHz CL 18 kit because it was the only 3600 MHz kit the shop had in stock and i have a kit that match in my second PC so i plan on putting the new AMD Edition kit in that PC once the Neo comes back from RMA

The plan was to take the good Neo stick out and put both the new AMD Edition sticks in and run memtest86+
If i get no errors it was just a bad stick if i get errors its a bad RAM slot

The kit has worked fine from the day i bought it and i have changed nothing or done nothing with it out than taking it out and putting it back in a few weeks ago because the RGB stopped working in all my software

Taking it out and putting it back might have damaged it but i have never heard of that before
Edit: i have taken a flashlight and looked at slot B2 and i can see nothing wrong with it there is no damage in the slot that i can see

The CPU is a 3700x


----------



## VPII

Melan said:


> tRTP
> On your previous screenshot you have it at 8. It's below tCWL.
> 
> 
> Honestly, I've had much better luck just ignoring resistance settings from dram calc and just let the board figure it out. It did a good job so far.


Hi there, thank you. Please explain to me, does TRTP and TCWL need to be similar, or the same? I will set the resistance values to Auto in the bios to see what it shows, and for the moment leave TRTP on Auto to see where it sets it.


----------



## Blameless

shilka said:


> Its a 32 GB kit of 2x 16 GB G Skill TridentZ Neo 3600 MHz CL 16 sticks and i have not tried the good stick in the slot that might be bad because i am pretty sure the system wont boot if there is not a stick in slot B1
> 
> The kit i have ordered is a 16 GB G Skill TridentZ AMD Edition 3600 MHz CL 18 kit because it was the only 3600 MHz kit the shop had in stock and i have a kit that match in my second PC so i plan on putting the new AMD Edition kit in that PC once the Neo comes back from RMA
> 
> The plan was to take the good Neo stick out and put both the new AMD Edition sticks in and run memtest86+
> If i get no errors it was just a bad stick if i get errors its a bad RAM slot
> 
> The kit has worked fine from the day i bought it and i have changed nothing or done nothing with it out than taking it out and putting it back in a few weeks ago because the RGB stopped working
> 
> Taking it out and putting it back might have damaged it but i have never heard of that before
> Edit: i have taken a flashlight and looked at slot B2 and i can see nothing wrong with it there is no damage in the slot that i can see


Most quad slot AM4 boards will boot with a stick in either channel, as long as it's the slot further from the CPU for that channel.

The RGB dying could hint at a power issue, or could have damaged the stick, or another component, as a side effect of the failure.

Anyway, almost any Zen 2/3 CPU/board combo should handle 3600 CL16. Try manually setting XMP timings to see if either stick works that way without errors.


----------



## shilka

Blameless said:


> Most quad slot AM4 boards will boot with a stick in either channel, as long as it's the slot further from the CPU for that channel.
> 
> The RGB dying could hint at a power issue, or could have damaged the stick, or another component, as a side effect of the failure.
> 
> Anyway, almost any Zen 2/3 CPU/board combo should handle 3600 CL16. Try manually setting XMP timings to see if either stick works that way without errors.


Stick one is fine its been tested twice in slot B1
Stick two is FUBAR its been tested in the same slot B1 and it gave 1400 something errors

If one stick is good its either slot B2 that has gone bad or its stick two
I dont plan on doing anything untill i get new RAM to test with

As for the RGB not working i should have explained it better it worked like it always had it just stopped being addressable in software and refuse to change from rainbow vomit
Like i said if there are no errors with new RAM it was the old RAM do i still get erros its B2 RAM slot

I hope it was the old RAM as a motherboard RMA is a total PITA


----------



## VPII

Melan said:


> tRTP
> On your previous screenshot you have it at 8. It's below tCWL.
> 
> 
> Honestly, I've had much better luck just ignoring resistance settings from dram calc and just let the board figure it out. It did a good job so far.


Okay my friend, this was with all resistances set to Auto in bios as well as tRTP, now I see same as TCWL. Thank you.


----------



## Phlereous

First one gets similar or slightly lower read scores. Why is that when all primaries are tightened and GDM off? All else is equal, could that be the problem?
I don't understand this.


----------



## Bloax

Have you tried throwing a lot of Pi at it with a fixed CPU frequency? 🥧🤡🥧
personally then I'm also a big fan of tRFC being a multiple of tRC, alongside tRFC2 & tRFC4 being (tRFC / 1.346) & (tRFC / 2.1875) respectively
(i.e. tRFC 270-201-123, on the left 15-15-15-30-45 side)


----------



## Phlereous

Bloax said:


> Have you tried throwing a lot of Pi at it with a fixed CPU frequency? 🥧🤡🥧
> personally then I'm also a big fan of tRFC being a multiple of tRC, alongside tRFC2 & tRFC4 being (tRFC / 1.346) & (tRFC / 2.1875) respectively
> (i.e. tRFC 270-201-123, on the left 15-15-15-30-45 side)
> View attachment 2555522


I haven't, I just quickly checked reads. I have ~0 experience and very limited knowledge/understanding on OC so just looking for an explanation.
Why aren't reads affected much and would there be a noticeable difference in Pi?

Also I read anta recommending tRFC being a multiple of 16. Why do you prefer the other way and what are pros/cons?


----------



## Bloax

I'm presuming you're talking about AIDA64 numbers?

It's a very poor benchmark of anything but extremely rough performance - proper memory-heavy tasks like y-cruncher Pi calculations are much more _sensitive_ to improvements in RRD/WTR/tFAW settings, lower tWR/RTP, command-rate ..

Not all things are equally sensitive, and it can also be that what you actually end up doing with your memory, doesn't care about some of those things (e.g. Overwatch, the game I play, doesn't really care about command rate). 



> Also I read anta recommending tRFC being a multiple of 16. Why do you prefer the other way and what are pros/cons?


If I had to throw blind guesses, then tRFC being multiples of 16 works for trying to keep it a non-multiple of (tCL + tRCD + tRP)
i.e. "good" tRFC values = (tCL + tRCD + tRP) * X +/- (16 * Y)

edit: now with a link


----------



## Melan

VPII said:


> Hi there, thank you. Please explain to me, does TRTP and TCWL need to be similar, or the same? I will set the resistance values to Auto in the bios to see what it shows, and for the moment leave TRTP on Auto to see where it sets it.


What I meant was tRTP is below tCWL on zentimings, as in positioned below. Not set it the same as tCWL. With tWR at 12, tRTP really should be 6.
Set what @Taraquin proposed in this post, but leave resistances on auto for now.


----------



## KedarWolf

Ask me how I did this.


----------



## ArchStanton

Taraquin said:


> Easy improvements: ras 32 (ras+rp=rc), rtp 6 (half wr), wrwrscl 4, rfc might do 272 or 256 if your a lucky. Less important: wtrl 10 or maybe 8.
> 
> Next is 2t gdm off, after that 1t, but requires some work.


Round 1 of stability testing completed. So far so good. I'll try RFC 256 next.


----------



## KedarWolf

ArchStanton said:


> Round 1 of stability testing completed. So far so good. I'll try RFC 256 next.
> 
> View attachment 2555585


Here's what I have on a similar kit. I know it breaks some timing rules but I got this on y-cruncher which is pretty good and very memory sensitive.

Also, it gets excellent AIDA64 results.


----------



## VPII

Taraquin said:


> Set RTP to 6, RAS to 28 and RC to 42, should improve things. Your ProcODT is very high, try 40. If you try 24 20 24 24 you may be able to do 2t instead of gdm.


@Melan @Taraquin it appears that your suggestion worked. Thank you so very much.


----------



## KedarWolf

VPII said:


> @Melan @Taraquin it appears that your suggestion worked. Thank you so very much.
> View attachment 2555596


You want to right-click on the 1usmus_v3.cfg file, choose properties, uncheck Read-Only, open it in Notepad++, change it from 3 cycles to 25 cycles, save it, go back to Properties and make it Read-Only again.

3 cycles are far too short to test for stability. Better to use 25 cycles.


----------



## KedarWolf




----------



## VPII

KedarWolf said:


> You want to right-click on the 1usmus_v3.cfg file, choose properties, uncheck Read-Only, open it in Notepad++, change it from 3 cycles to 25 cycles, save it, go back to Properties and make it Read-Only again.
> 
> 3 cycles are far too short to test for stability. Better to use 25 cycles.


Hi @KedarWolf thank you I'll do so when back from work later today, but will set it up now.


----------



## VPII

KedarWolf said:


> You want to right-click on the 1usmus_v3.cfg file, choose properties, uncheck Read-Only, open it in Notepad++, change it from 3 cycles to 25 cycles, save it, go back to Properties and make it Read-Only again.
> 
> 3 cycles are far too short to test for stability. Better to use 25 cycles.


Okay I have changed it will test this afternoon when back from work. Thank you


----------



## KedarWolf

Well under 97 seconds now. Had to change my timings as it froze in TM5 tRP at 13.


----------



## Baio73

KedarWolf said:


> You want to right-click on the 1usmus_v3.cfg file, choose properties, uncheck Read-Only, open it in Notepad++, change it from 3 cycles to 25 cycles, save it, go back to Properties and make it Read-Only again.
> 
> 3 cycles are far too short to test for stability. Better to use 25 cycles.


That's a great suggestion!
The worst thing about TM5 is it needs to be lauched over and over to complete the 25 passes...
My c.fg fiel hadn't the read-only attribute, I set it after the modify, but as soon as I lauche TM5 it gives me this error:



Baio


----------



## KedarWolf

Baio73 said:


> That's a great suggestion!
> The worst thing about TM5 is it needs to be lauched over and over to complete the 25 passes...
> My c.fg fiel hadn't the read-only attribute, I set it after the modify, but as soon as I lauche TM5 it gives me this error:
> 
> 
> 
> Baio


Here's mine. Right-click, rename, remove the .txt. Don't forget to make it read-only.


----------



## Taraquin

KedarWolf said:


> Well under 97 seconds now. Had to change my timings as it froze in TM5 tRP at 13.
> 
> View attachment 2555613
> 
> 
> View attachment 2555612


Good time, same I get running 4000cl16  RP is not my friend on my kit either. Suggestion: RDWR 9 or 8 (should be better and low CWL makes low RDWR harder to run), up CWL to 14, RAS22 (RP+RAS=RC), RTP 5.


----------



## Taraquin

Phlereous said:


> View attachment 2555520
> View attachment 2555521
> 
> 
> First one gets similar or slightly lower read scores. Why is that when all primaries are tightened and GDM off? All else is equal, could that be the problem?
> I don't understand this.


2 thing, you run higher RDWR and PHYL may be 26/28 on the tighter setup. That is probably it. If able try RDWR 9 or 8 and 8f PHYL runs at 26/28 try 2t, may improve performance.


----------



## Taraquin

Bloax said:


> I'm presuming you're talking about AIDA64 numbers?
> 
> It's a very poor benchmark of anything but extremely rough performance - proper memory-heavy tasks like y-cruncher Pi calculations are much more _sensitive_ to improvements in RRD/WTR/tFAW settings, lower tWR/RTP, command-rate ..
> 
> Not all things are equally sensitive, and it can also be that what you actually end up doing with your memory, doesn't care about some of those things (e.g. Overwatch, the game I play, doesn't really care about command rate).
> 
> 
> If I had to throw blind guesses, then tRFC being multiples of 16 works for trying to keep it a non-multiple of (tCL + tRCD + tRP)
> i.e. "good" tRFC values = (tCL + tRCD + tRP) * X +/- (16 * Y)
> 
> edit: now with a link


If I remember anta777 corrects RFC runs in cycles of 8 ticks on 8gb modules, 16 ticks on 16gb modules etc. Using 'wrong' values is not bad, but unless you get to the next lower tick cycle performance will be the same, example on 2x16gb 272 or 256 is different cycles, 257 would yield same perf as 272 since on same cycle, but 257 is harder to run than 272. RC multiplier has a tendency to match this. For instance RC of 48 matches 240 and 288, 44x6=264, 40x6=240 etc.


----------



## KedarWolf

Taraquin said:


> Good time, same I get running 4000cl16  RP is not my friend on my kit either. Suggestion: RDWR 9 or 8 (should be better and low CWL makes low RDWR harder to run), up CWL to 14, RAS22 (RP+RAS=RC), RTP 5.


tRDWR needs to be 10 for tCWL 12. tCWL 12 gets better write and copy than 14. I'll try tRTP 5 though.

I had to go back to 19/21/40 as 14/21/36 caused errors on TM5. Also need to do 4-4/6-6 I think. I saw someone running 4-2/6-2 but no go on my dual rank, they were single rank.


----------



## Taraquin

KedarWolf said:


> tRDWR needs to be 10 for tCWL 12. tCWL 12 gets better write and copy than 14. I'll try tRTP 5 though.
> 
> I had to go back to 19/21/40 as 14/21/36 caused errors on TM5. Also need to do 4-4/6-6 I think. I saw someone running 4-2/6-2 but no go on my dual rank, they were single rank.


Dtxdomdissar compared lower CWL vs RDWR a while back and concluded low RDWR was most important. Is RDWR 8/9 14 CWL performing worse?


----------



## KedarWolf

Taraquin said:


> Dtxdomdissar compared lower CWL vs RDWR a while back and concluded low RDWR was most important. Is RDWR 8/9 14 CWL performing worse?


Yes, it is, let me show you, bbiab.


----------



## domdtxdissar

My tCWL vs tRDWR testing:











domdtxdissar said:


> So i got intrigued by the tCWL10 and decided to test some different memory settings to see what really performed best in different memory benchmarks, little did i know how much time this would really take 😅
> 
> These are the settings i decided to have a showdown between:
> View attachment 2536836
> 
> 
> 
> A few words before we get into the data
> 
> All benchmarks were run with a static OC @ a lowish 4600/4500mhz, so everyone with a 5950x should be able to compare numbers if they want
> After each benchmark computer was restarted, and after each restart the computer was left idling for 1min so windows could start all processes in peace
> Benchmarks was performed on a newly installed GHOSTSPECTRE SUPERLIGHT Win10 OS. (around 94 processes running after 1 min idling)
> Difficulty for the Menero Miner XMR-stak-rx was "480045" for all runs
> I have screenshots for every benchmark if requested
> 
> 
> 
> Spoiler: Benchmarks
> 
> 
> 
> start
> 
> *Benchmate wPrime 1.5.0.5*
> 
> Baseline:
> 
> Run1 = 34.700 sec
> Run2 = 34.622 sec
> Run3 = 34.761 sec
> Average = 34.694 sec
> 
> Baseline -SCL2:
> 
> Run1 = 34.672 sec
> Run2 = 34.677 sec
> Run3 = 34.702 sec
> Average = 34.683 sec
> 
> -2tCWL +2tRDWR:
> 
> Run1 = 34.773 sec
> Run2 = 34.698 sec
> Run3 = 34.767 sec
> Average = 34.732 sec
> 
> -2tCWL +2tRDWR -2SCL:
> 
> Run1 = 34.763 sec
> Run2 = 34.819 sec
> Run3 = 34.686 sec
> Average = 34.756 sec
> 
> Correct tRAS:
> 
> Run1 = 34.709 sec
> Run2 = 34.773 sec
> Run3 = 34.693 sec
> Average = 34.725 sec
> 
> Flat tCL14 :
> 
> Run1 = 34.799 sec
> Run2 = 34.834 sec
> Run3 = 34.713 sec
> Average = 34.782 sec
> 
> *Corona 1.3 Benchmark:*
> 
> Baseline:
> 
> Run1 = 11.812.500 Reys/sec
> Run2 = 11.822.300 Reys/sec
> Run3 = 11.853.700 Reys/sec
> Average = 11.829.500 Reys/sec
> 
> Baseline -SCL2:
> 
> Run1 = 11.748.000 Reys/sec
> Run2 = 11.749.700 Reys/sec
> Run3 = 11.836.600 Reys/sec
> Average = 11.778.100 Reys/sec
> 
> -2tCWL +2tRDWR:
> 
> Run1 = 11.735.800 Reys/sec
> Run2 = 11.772.700 Reys/sec
> Run3 = 11.767.900 Reys/sec
> Average = 11.758.800 Reys/sec
> 
> -2tCWL +2tRDWR -2SCL:
> 
> Run1 = 11.783.300 Reys/sec
> Run2 = 11.778.700 Reys/sec
> Run3 = 11.786.400 Reys/sec
> Average = 11.782.800 Reys/sec
> 
> Correct tRAS:
> 
> Run1 = 11.804.200 Reys/sec
> Run2 = 11.813.100 Reys/sec
> Run3 = 11.818.200 Reys/sec
> Average = 11.811.833 Reys/sec
> 
> Flat tCL14:
> 
> Run1 = 11.786.700 Reys/sec
> Run2 = 11.793.000 Reys/sec
> Run3 = 11.792.200 Reys/sec
> Average = 11.790.633 Reys/sec
> 
> *Linpack Xtreme 1.1.5*
> 
> Baseline:
> 
> Run1 = 673.6121 GFlops
> Run2 = 672.5934 GFlops
> Run3 = 672.7430 GFlops
> Average = 672.9828 GFlops
> 
> Baseline -SCL2:
> 
> Run1 = 671.7620 GFlops
> Run2 = 671.3653 GFlops
> Run3 = 670.6409 GFlops
> Average = 671.2561 GFlops
> 
> -2tCWL +2tRDWR:
> 
> Run1 = 672.5900 GFlops
> Run2 = 672.1730 GFlops
> Run3 = 672.1913 GFlops
> Average = 672.3181 GFlops
> 
> -2tCWL +2tRDWR -2SCL:
> 
> Run1 = 670.3983 GFlops
> Run2 = 669.1971 GFlops
> Run3 = 669.5059 GFlops
> Average = 669.7004 GFlops
> 
> Correct tRAS:
> 
> Run1 = 671.6125 GFlops
> Run2 = 671.0436 GFlops
> Run3 = 670.6122 GFlops
> Average = 671.6122 GFlops
> 
> Flat tCL14:
> 
> Run1 = 668.8344 GFlops
> Run2 = 668.2137 GFlops
> Run3 = 668.1432 GFlops
> Average = 668.3971 GFlops
> 
> *IntelBurnTest v2.54: Very high stresslevel*
> 
> Baseline:
> 
> Run1 = 234.9265 GFlops
> Run2 = 235.5467 GFlops
> Run3 = 235.8574 GFlops
> Average = 235.4435 GFlops
> 
> Baseline -SCL2:
> 
> Run1 = 235.5185 GFlops
> Run2 = 235.6311 GFlops
> Run3 = 234.5461 GFlops
> Average = 235.2319 GFlops
> 
> -2tCWL +2tRDWR:
> 
> Run1 = 234.5213 GFlops
> Run2 = 234.4156 GFlops
> Run3 = 234.4483 GFlops
> Average = 234.4617 GFlops
> 
> -2tCWL +2tRDWR -2SCL:
> 
> Run1 = 234.0640 GFlops
> Run2 = 234.2016 GFlops
> Run3 = 235.6987 GFlops
> Average = 234.6547 GFlops
> 
> Correct tRAS:
> 
> Run1 = 234.9590 GFlops
> Run2 = 234.8467 GFlops
> Run3 = 237.0151 GFlops <-- outliner
> Average = 235.6069 GFlops
> 
> Flat tCL14:
> 
> Run1 = 233.8859 GFlops
> Run2 = 234.8498 GFlops
> Run3 = 235.7551 GFlops
> Average = 234.8302 GFlops
> 
> *Menero Miner XMR-stak-rx *
> 
> Baseline:
> 
> Average after 15min = 19709.4 H/s
> Highest = 19728.5 H/s
> 
> Baseline -SCL2:
> 
> Average after 15min = 19625.1 H/s
> Highest = 19641.9 H/s
> 
> -2tCWL +2tRDWR:
> 
> Average after 15min = 19605.5 H/s
> Highest = 19621.7 H/s
> 
> -2tCWL +2tRDWR -2SCL:
> 
> Average after 15min = 19655.7 H/s
> Highest = 19677.9 H/s
> 
> Correct tRAS:
> 
> Average after 15min = 19571.3 H/s
> Highest = 19585.1 H/s
> 
> Flat tCL14:
> 
> Average after 15min = 19509.0 H/s
> Highest = 19521.3 H/s
> 
> 
> 
> 
> 
> 
> 
> End comments:
> 
> Like previously found, my "baseline" seems to be the fastest profile overall, for my system atleast.
> SCL2 almost always seems to lower the performance on my 2x16GB dualrank setup. (in aida64 you see higher write but lower read)
> tCWL10 didn't seem to make up from the performance loss from being forced to run tRDWR11 instead of 9. (or the bios is actually not running tCWL10 like it says it is)
> "Flat tCL14" seems to be the slowest profile.
> The Menero Miner seemingly really likes low tRAS+tRC, even when its below the "calculated minimum".
> As with pretty much all "memory benchmarks", CPU clockspeed is king... Don't spend your power budget on SOC if that mean lower cpu boosting.


----------



## kim nk

This is a long time ago, we looked at the minimum by increasing the TRDWR timing and lowering the TCWL value to find out the minimum TCWL value. Don't worry about TPHYRDL. It's pretty old data.



































By SR, the minimum TCWL value is 9. There is no difference in performance between TCWL 9 and TRDWR 12 and TCWL 14 TRDWR 7. It's the same.


----------



## ArchStanton

Baio73 said:


> I set it after the modify, but as soon as I lauche TM5 it gives me this error:


Just my $0.02. I have seen that type of error before. I was not able to completely eliminate it without a full wipe and reinstall of Windows. The error began appearing intermittently for me after booting and running some tests at fclk 2000.


----------



## Alastair

This seems to be the end of the road for my Sammy C-dies. 

I managed with a lot of tinkering to get 1CR stable. Its the biggest improvement I have seen from anything out of this machine. 

































I don't see any further way that I can improve on this


----------



## Bloax

RRD short, 6, RRD long, 4 - are you sure that's right? 🤡 👌









[Official] Intel Z690 / Z790 DDR4 Daily Memory Overclock


So for ddr4000 I need to go from 1.32 to 1.56?!? That’s A LOT for just 100mhz gain? With these procODT/RTT settings on my sticks, +/- 100 MCLK costs 0.06v, and +/- 1 tRCDRD costs 0.09v (while keeping all primary timings equal) So if yours scale similarly, then it's 1.32v to 1.56v if you want...




www.overclock.net




hey look my viper 4000 16-16-16 sticks finally arrived


----------



## Alastair

Bloax said:


> RRD short, 6, RRD long, 4 - are you sure that's right? 🤡 👌
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] Intel Z690 / Z790 DDR4 Daily Memory Overclock
> 
> 
> So for ddr4000 I need to go from 1.32 to 1.56?!? That’s A LOT for just 100mhz gain? With these procODT/RTT settings on my sticks, +/- 100 MCLK costs 0.06v, and +/- 1 tRCDRD costs 0.09v (while keeping all primary timings equal) So if yours scale similarly, then it's 1.32v to 1.56v if you want...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> hey look my viper 4000 16-16-16 sticks finally arrived


Short did not want to go lower but long did.


----------



## Viron

Alastair said:


> I don't see any further way that I can improve on this


Get some cheap B-die


----------



## Alastair

Viron said:


> Get some cheap B-die


I am seriously considering selling this kit and looking for some OEM B-dies. Or good OEM kits in general. As there isnt any spare $ in the bank. But I have an OC itch that needs scratchin.


----------



## CrankyTucan

Got the new config for TM5. used to pass anta777 all day. Now, with absolute config i get two errors after the test. Anyone know what there's errors are?
One Error on test three:
[Test3]
Enable=1
Time (%)=20
Function=MirrorMove128
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=2
Test Block Size (Mb)=0

And

One Error on Test 5:
[Test5]
Enable=1
Time (%)=20
Function=MirrorMove128
DLL Name=bin\MT0.dll
Pattern Mode=0
Pattern Param0=0x0
Pattern Param1=0x0
Parameter=1
Test Block Size (Mb)=0

I know the thread on OC.com says " Error 3 & 4 by checking the MT.cfg - are MirrorMove errors. That set shows tRFC 2 issues and this tRFC "auto predicted" ? is wrong. tRFC is so far always even as tRFC stepping are 32,16,8,4,2 ,"
and
"Error 5 then 6 is a timings missmatch between dimms (data mirror move) "



My voltages: VSOC: 1.125 DIMM: 1.53 CCD: 1.025 IOD: 1.050 VDDP: .950


----------



## Bloax

Personally then I would shoot it with tRAS = tCL + rRCDRD (29), tRC = tRAS + tRP (44), and


> Personally then I'm also a big fan of tRFC being a multiple of tRC, alongside tRFC2 & tRFC4 being (tRFC / 1.346) & (tRFC / 2.1875) respectively


tRFC 264-196-121

Based on what the folks above are talking about, you may also want tCWL 14 and RDWR 8 for simplicity's sake


----------



## Viron

CrankyTucan said:


> Snipp


Try your SCL timings at 3 and then see. 
What is your VDIMM at? I would try 1.45-1,55V atleast and then see. Use a fan over it if it gets hot.


----------



## Veii

Taraquin said:


> If I remember anta777 corrects RFC runs in cycles of 8 ticks on 8gb modules, 16 ticks on 16gb modules etc. Using 'wrong' values is not bad, but unless you get to the next lower tick cycle performance will be the same, example on 2x16gb 272 or 256 is different cycles, 257 would yield same perf as 272 since on same cycle, but 257 is harder to run than 272. RC multiplier has a tendency to match this. For instance RC of 48 matches 240 and 288, 44x6=264, 40x6=240 etc.


I see it repeated multiple times, and while anta is correct looking at it from the bigger picture ~ the theory
The practice doesn't match on AMD Memory Controller capabilities

Like touched on this here,








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Try 16, 8, 18, 16, ras 42, rc 60, rfc 600, cwl 16, see if that makes errors go away? If it works try rdwr 10, 9 or 8. Still have way too many error instantly + 1 bluescreen from 1.55 to 1.6V. I don't dare to go further.




www.overclock.net




It can not be a thing ~ as there is no support neither by the IMC, nor by Samsung IC and not either by dimms without a thermal sensor

tRFC pausing, or tRFC shifting is not a feature we can use.
It might be designed by JEDEC and dimm MSR (option) ~ the chip, "might" support it , shifting to it in real time
But purely our own IMC is not capable to do this ~ and b-dies are not capable to do tRFC pausing either
Potentially Micron OEM Dimms can do it ~ but i am to this date not sure they really can use this feature of DDR4

A shift of 16 or 32, i've been there
Old mini module was exploring this, but JEDEC is not always something that is followed anywhere
Soo i moved away from it, it's not a thing.
It matches in theory, but in practice it's simply not a thing 

ICs by side are not refreshed in order, as interleaving and refresh stacking exists
Soo virtual nCK value of 8 ICs or 16 ICs can not work out, it's too dynamic and MSR defines refresh method for tRC dynamically up to preset state (CAS bef RAS refresh most commonly used)

Anta's rule can only work out, for his method of preset building and only on systems which support tRFC shifting


> On AMD once tRAS, tRC is missed, it will repeat, loop and wait for it to pass (time-break is not possible here)
> On tRFC it's worse ~ if it's missed, operation will be halted, and whole tRFC repeat ~ till operation succeeded.
> On idle operation where ICs have to still be refreshed (volatile memory) ~ a ghost read is triggered that forces recharge.


Hence all this,
Pushing tRFC down, needs consistent access latency testing and not only bandwidth testing
(BW should show a change but doesn't always have to show up in tests like pi-calculation)
A missed tRFC is about a distance of 0.3-0.5ns (increase)

A low tRAS will show faster burst access on the first test after X recharge
~ when cells are already in a charged state
But as low tRAS misses tRP before it to (p)recharge the row it tries to access & move data for the whole row read not to erase it
It will not be a consistent faster thing.
Soo even if RAS strobe time ~ check time, is bursty and short - it still will have to sometimes wait for cells to be in a ready usable state
And then "tight tRAS" does not matter.

The same for tRC and the same for tRFC
A high tRFC does cut into "maximum potentially usable" ~ bandwidth
^ hence memory has to wait for tRFC to elapse which is a continuous trigger that happens every time inside predefined tight tREFI window (on AMD)
A low tRFC will increase "the chance of operation" , so called "potential higher bandwidth by more free-usable time" in defined tREFI window
With another rephrased sentence "the potential non bottlenecked usable bandwidth free-operation time"

But "low tRFC" will not do anything, even when it increases "ceiling of potential usable bandwidth"
When memory timings 1st, don't have fluid transitions ~ and 2nd, are simply too high, to even being able to reach near that bandwidth ceiling
Only when timings are very tight, independent of MCLK ~ only then tRFC drop, will show any latency decrease and bandwidth increase

Dual Rank and higher density dimms are more affected by this "has to recharge volatile memory" thing called tRFC
~ hence there the issue of "high tRFC" becomes more apparent
But there is a limit where you move around and that ETA was the only goal of tRFC mini
~ predict correct recharge & predict discharge, since the foundation couple of years ago.








Please click on the link, and try to read my mess of lecture 
It goes more direct into it ~ this post here is more of a reminder and repeat
I know what anta is using, and been there - but it does not work out, not here at least.

Soo i move in another scale. Which is called " Row Cycle Time "
Instead of on a chip-by-chip scale 
@Bloax is a good observer for rare changes. He is quite skilled in that without having to read technical papers
So was my initial foundation build upon.
Just now i know, that ICs are not refreshed consistently and tRFC is used differently
Most of the times it being low doesn't matter ~ but it being "just on time" does matter for the bigger picture
==============================================================
@Audioboxer , bios i gave you was an attempt to fix the disabled OC "bugs" that came with newer AGESA
It had more changes than this, and it expected you to redo CO's as voltage requests will be much higher
But as you confirmed that the bug is not solved , the attempt from me was a failure 
Read your message and reports ~ simply busy atm. Only lurking on this thread


----------



## CrankyTucan

Ill give it a try. VDIMM is 1.53.


----------



## CrankyTucan

Ill give this a try thanks!


----------



## Taraquin

Veii said:


> I see it repeated multiple times, and while anta is correct looking at it from the bigger picture ~ the theory
> The practice doesn't match on AMD Memory Controller capabilities
> 
> Like touched on this here,
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Try 16, 8, 18, 16, ras 42, rc 60, rfc 600, cwl 16, see if that makes errors go away? If it works try rdwr 10, 9 or 8. Still have way too many error instantly + 1 bluescreen from 1.55 to 1.6V. I don't dare to go further.
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> It can not be a thing ~ as there is no support neither by the IMC, nor by Samsung IC and not either by dimms without a thermal sensor
> 
> tRFC pausing, or tRFC shifting is not a feature we can use.
> It might be designed by JEDEC and dimm MSR (option) ~ the chip, "might" support it , shifting to it in real time
> But purely our own IMC is not capable to do this ~ and b-dies are not capable to do tRFC pausing either
> Potentially Micron OEM Dimms can do it ~ but i am to this date not sure they really can use this feature of DDR4
> 
> A shift of 16 or 32, i've been there
> Old mini module was exploring this, but JEDEC is not always something that is followed anywhere
> Soo i moved away from it, it's not a thing.
> It matches in theory, but in practice it's simply not a thing
> 
> ICs by side are not refreshed in order, as interleaving and refresh stacking exists
> Soo virtual nCK value of 8 ICs or 16 ICs can not work out, it's too dynamic and MSR defines refresh method for tRC dynamically up to preset state (CAS bef RAS refresh most commonly used)
> 
> Anta's rule can only work out, for his method of preset building and only on systems which support tRFC shifting
> 
> Hence all this,
> Pushing tRFC down, needs consistent access latency testing and not only bandwidth testing
> (BW should show a change but doesn't always have to show up in tests like pi-calculation)
> A missed tRFC is about a distance of 0.3-0.5ns (increase)
> 
> A low tRAS will show faster burst access on the first test after X recharge
> ~ when cells are already in a charged state
> But as low tRAS misses tRP before it to (p)recharge the row it tries to access & move data for the whole row read not to erase it
> It will not be a consistent faster thing.
> Soo even if RAS strobe time ~ check time, is bursty and short - it still will have to sometimes wait for cells to be in a ready usable state
> And then "tight tRAS" does not matter.
> 
> The same for tRC and the same for tRFC
> A high tRFC does cut into "maximum potentially usable" ~ bandwidth
> ^ hence memory has to wait for tRFC to elapse which is a continuous trigger that happens every time inside predefined tight tREFI window (on AMD)
> A low tRFC will increase "the chance of operation" , so called "potential higher bandwidth by more free-usable time" in defined tREFI window
> With another rephrased sentence "the potential non bottlenecked usable bandwidth free-operation time"
> 
> But "low tRFC" will not do anything, even when it increases "ceiling of potential usable bandwidth"
> When memory timings 1st, don't have fluid transitions ~ and 2nd, are simply too high, to even being able to reach near that bandwidth ceiling
> Only when timings are very tight, independent of MCLK ~ only then tRFC drop, will show any latency decrease and bandwidth increase
> 
> Dual Rank and higher density dimms are more affected by this "has to recharge volatile memory" thing called tRFC
> ~ hence there the issue of "high tRFC" becomes more apparent
> But there is a limit where you move around and that ETA was the only goal of tRFC mini
> ~ predict correct recharge & predict discharge, since the foundation couple of years ago.
> 
> 
> 
> 
> 
> 
> 
> 
> Please click on the link, and try to read my mess of lecture
> It goes more direct into it ~ this post here is more of a reminder and repeat
> I know what anta is using, and been there - but it does not work out, not here at least.
> 
> Soo i move in another scale. Which is called " Row Cycle Time "
> Instead of on a chip-by-chip scale
> @Bloax is a good observer for rare changes. He is quite skilled in that without having to read technical papers
> So was my initial foundation build upon.
> Just now i know, that ICs are not refreshed consistently and tRFC is used differently
> Most of the times it being low doesn't matter ~ but it being "just on time" does matter for the bigger picture
> ==============================================================
> @Audioboxer , bios i gave you was an attempt to fix the disabled OC "bugs" that came with newer AGESA
> It had more changes than this, and it expected you to redo CO's as voltage requests will be much higher
> But as you confirmed that the bug is not solved , the attempt from me was a failure
> Read your message and reports ~ simply busy atm. Only lurking on this thread


My english is not so good, but wrap up, it can matter on Intel and possibly Micron dies? Except for that lowest value that improves performance is best? No way to calculate on AMD? I though RFC was related to REFI which is based on timing/recharges on Intel where it can be changed.

As for RC I get about 1 sec lower at dram calc test using RAS 29 RC 45 vs the logical 32/48 (16 16 16 32 48).


----------



## Veii

Taraquin said:


> My english is not so good, but wrap up, it can matter on Intel and possibly Micron dies? Except for that lowest value that improves performance is best? No way to calculate on AMD? I though RFC was related to REFI which is based on timing/recharges on Intel where it can be changed.
> 
> As for RC I get about 1 sec lower at dram calc test using RAS 29 RC 45 vs the logical 32/48 (16 16 16 32 48).


It should function on Intel, has to else anta wouldn't mention it at all ~ tRFC shifting
tRFC pausing "could" exist on micron, which would explain why it can not be lower than 300ns (near that) but i am not sure it really is able to
^ tRFC pausing exists on LPDDR and GDDR

On AMD Firmware, in any documents i could read ~ it does not exist. It's not a thing we can use
But as for tRFC by itself, it wouldn't matter at first till your timings are not the bottleneck anymore
Then it matters and shows effects - before that being 10ns off here doesn't show a big effect or non at all.
Any operation halts while tRFC is active, which anta is correct that there is no direct connetion
But so am i correct, that IC amount (8,16) also are not a direct connection and that thing doesn't work out in fractions of 8,16,32.
It can not be order based. I mean it "could" but it won't ~ up to order of preset and order of recharge.
It's random which rank is recharged first and which IC. Only tREFI recharges everything
Soo while it is correct to move it in these fractions by 8 or 16 tCK ~ it is not for tRFC by itself. It's just the distance
It will not dictate how low or high tRFC can be and what type of refresh algorithm is automatically decided to be used by DIMM-PCB (MSR)

Soo the rule (increase/decrease tRFC by factor of 8 for SR or 16 for DR) matters only for tREFI
You can equally rotate this wording and say "increase tREFI by 16 for SR or 32 for DR"
But tREFI is fixed on our side ~ and tMAC.tMAW (RC_Page) is something to explore with anta's rule

Meaning,
Deciding what tRFC has to be within 2 or 3 tCK is not calculable by any rule that can not simulate memory transition delays
Soo can not say "this whole thing for read, write, recharge" takes 80ns - tRFC has to be every 160ns or so
it can not work that way

What can be used, is X predicted tRFC +/- 8,16,32 // if we go to follow his rule
But even that is problematic, as you can not say tREFI = 9* tRFC, done
You can not adjust tREFI on AMD , soo this 8,16,32 IC dependent rule can not work out
And tRFC does not shift but is repeated ~ soo also one more point why this rule can not work out


> What can be used, is X predicted tRFC +/- 8,16,32 // if we go to follow his rule











I've tried that, but moved away from it
It's dynamic ~ it can not work that way. 
It maybe can work with JEDEC specific timings, just increased or decreased ~ but it can not work with any other custom user timings that will simply not add up to this.

To have a realistic prediction, it needs to also factor vdimm-to-amperage math
Then you can create for ICs and for PCBs "min/max" tRFCns distances for X amperage
Only then , yes then it can be correct
But till then ~ anything is a prediction, and i just took a different anchor which before was CAS
Only that CAS and RAS should be seen the same way , tRCD is unique both RAS and CAS scale by voltage
tRC is the only thing that is consistent, if you keep the math up (tRC = tRP+tRAS)


----------



## Veii

Taraquin said:


> As for RC I get about 1 sec lower at dram calc test using RAS 29 RC 45 vs the logical 32/48 (16 16 16 32 48).


tRAS and tCAS are 2 unique things without really any dependencies
Column Strobe (top column find time)
&
Row Strobe (row column find time inside selected memory bank)

Both have identical priority, just that columns have higher hit rate & are faster
Rows can indeed be missed ~ up to what type of indexing the DIMM-PCB chip does
(average time takes longer)
Such indexing, can be influenced by RC_PAGE , but tRC_PAGE (tMAW.tMAC) was only once mentioned by couple engineers here, yet no real supportive tool was given
Everyone i talk with has the mentality to stay closed , to appear "more important" in his higher position
Or simply learned something by bruteforce, and isn't capable to teach it in more simple methods

Anywho,
tRAS can be lower ~ up to how much charge is left in the row of the same bank. Soo if whole row needs to be recharged or not
But if tRAS is too low, everything is halted again, tRP delay inserted
(well own delay inserted to copy away valuable data and recharge) ~ then this delay extended to tRP value
And only then tRAS comes up and does it's job

Soo if cells find a state randomly where they don't have excessive voltage left
Low tRAS will be ignored fully, tRP inserted and then tRAS repeated
That's autocorrection, which you only notice if you increase tRAS & tRC higher or lower together

If tRC by itself does not match tRP+tRAS
You can exploit it, but that's for another day ~ what usually happens is the same
It's missed, it was too low , just unlike tRAS which is not triggering at first (but tRP + tRAS, not only tRAS)
Here tRC elapses, senses an issue (lack of charge) and repeats

Yet if tRC is too long, it will mask other low timings and other powering issues
Soo it has to be tRP+tRAS to be done with this ROW
Memory should not allow to have a whole row with half charge - else data would be defective inside it
But tRowCycle-Time is something "new". You can "keep it in mind" on Intel or DDR3 systems, but it's something that is now controllable
~ it's a virtual value and so a virtual anchor to me

You "could" decrease RowCycle time,(at tRAS level without tRP) but you surely will face an event where you come back to X ROW to read something & find out, the cell has corrupted data or not enough charge is left (heat leakage) soo tRP needs to happen again
That's a waste of time and soo too low tRAS is corrected upwards at the very end

We likely have to rethink later how to design timings around, but i'm not done looking into








Different type of refresh stacking methods
just keep in mind, that CAS and RAS have equal weight & are independent of the IC (to most extend)
They depend on voltage and the PCB ~ only tRCD is important and a binning thing. tCAS is irrelevant most of the time, just looks good


----------



## Bloax

Veii said:


> Yet if tRC is too long, it will mask other low timings and other powering issues











mic drop


----------



## Veii

Bloax said:


> View attachment 2555757
> 
> mic drop


XMP ? ^^'

Surprisingly on DR, XMP is not that bad








Well , not bad in the sense that timings make sense
Powering is questionable and stability is questionable
But in general , was "decent"


Spoiler: Offtopic



APU should arrive in 2 days, then i can explore the gigabyte ITX bios
And focus more work into these diva's
Nothing beyond 3600 works on my chip
Would need to change procODT and cLDO_VDDP around, but that will ruin everything (FCLK)
Better to play on an APU 

Waiting for X3D release too zZZ 
(work on couple of projects at the same time)
Whole build is stopped, but i might need some time, as CPU & Case has to arrive, before i plan a custom loop around it
(case needs to come first, GPU is there and waiting)


----------



## SaarN

Having weird issues with my 5900x (B2 stepping).
It would boot up with 2000 fclk, but there will be lots of micro stutters while browsing through the BIOS, and then it would restart itself.
I mean, I get it that it's not stable at 2000 fclk, but what's up with it restarting itself like that, shouldn't it just hang \ crash?
Tried adjusting the voltages to the point where things went smoother. I should mention that I don't let it load it Windows right away, but run MemTest86 run from a usb stick, until I'm sure it's stable.
But, once I loaded the memory test, the reported reads and writes were half of what's expected, so I knew something was off, but I was wondering if it would let me complete the test, wondering if I could solve the instability with better voltage settings.
But nope, PC restarted itself half way through the test without any warning.. temps were obviously fine.
If I'm not mistaken my SOC voltage is 1.15v, CCD is 0.95v, IOD is 1.07v and vddp is .91v.
I guess I shouldn't bother with 2000fclk, even if it kind-of posts, right?
Makes me wonder if it's actually unstable or if I'm being told by AMD that they don't appreciate me jumping over spec like that, because my chip is rock solid at 1900 fclk, but would throw tantrum even when I tried settling for something less exotic, like 1933..
Bummer..


----------



## KedarWolf

Taraquin said:


> Dtxdomdissar compared lower CWL vs RDWR a while back and concluded low RDWR was most important. Is RDWR 8/9 14 CWL performing worse?


Sorry for the delay.

tCWL at 14 is better but only because I can run other timings lower TM5 stable. I can run those timings on tCWL12 but get random reboots, freezes in TM5 etc.

Got my lowest ever y-cruncher with my optimized Core Curve.

Have only gotten quite a bit lower with a CCX static overclock.


----------



## Veii

KedarWolf said:


> Sorry for the delay.
> 
> tCWL at 14 is better but only because I can run other timings lower TM5 stable. I can run those timings on tCWL12 but get random reboots, freezes in TM5 etc.
> 
> Got my lowest ever y-cruncher with my optimized Core Curve.
> 
> Have only gotten quite a bit lower with a CCX static overclock.
> 
> View attachment 2555766
> 
> 
> View attachment 2555767


Please doublecheck with tRAS at 22 and tWRRD 4
If unstable leave tWRRD but i think it needs a change ~ too low tRAS will be ignored
Good score
Easiest test, tRAS1 up ~ if you notice no difference then keep it that way
But it potentially can be a big difference IF there was an issue beforehand ~ else there should be no perf increase


----------



## 97pedro

Just to share my settings as of today.

Best I could get out of a 3200mhz cl14 Flare X kit (2 of them).

Any thoughts?


----------



## Veii

97pedro said:


> Any thoughts?


tWTR_L to 8
or tRRD_L to 5

pick one
EDIT:
or tRRD_L 6 & tWTR_L 6
together , but that likely is too low

Is that micron Rev.B ?
Hynix ?


----------



## ArchStanton

Veii said:


> pick one


Why does this conjure up visions from the end of "Indian Jones and the Last Crusade" for me.


----------



## Taraquin

Veii said:


> tWTR_L to 8
> or tRRD_L to 5
> 
> pick one
> EDIT:
> or tRRD_L 6 & tWTR_L 6
> together , but that likely is too low
> 
> Is that micron Rev.B ?
> Hynix ?


Must be B-die with 252 rfc


----------



## Taraquin

SaarN said:


> Having weird issues with my 5900x (B2 stepping).
> It would boot up with 2000 fclk, but there will be lots of micro stutters while browsing through the BIOS, and then it would restart itself.
> I mean, I get it that it's not stable at 2000 fclk, but what's up with it restarting itself like that, shouldn't it just hang \ crash?
> Tried adjusting the voltages to the point where things went smoother. I should mention that I don't let it load it Windows right away, but run MemTest86 run from a usb stick, until I'm sure it's stable.
> But, once I loaded the memory test, the reported reads and writes were half of what's expected, so I knew something was off, but I was wondering if it would let me complete the test, wondering if I could solve the instability with better voltage settings.
> But nope, PC restarted itself half way through the test without any warning.. temps were obviously fine.
> If I'm not mistaken my SOC voltage is 1.15v, CCD is 0.95v, IOD is 1.07v and vddp is .91v.
> I guess I shouldn't bother with 2000fclk, even if it kind-of posts, right?
> Makes me wonder if it's actually unstable or if I'm being told by AMD that they don't appreciate me jumping over spec like that, because my chip is rock solid at 1900 fclk, but would throw tantrum even when I tried settling for something less exotic, like 1933..
> Bummer..


Restarting itself can be unstable infinity fabric, check if event viewer show bus/interconnect error in log at time of restart. Generally very few dual ccd cpus on 4 dimm motherboards can run above 3800/1900 without problems. You could try 1.15 soc, 1.1 iod, 1.0 ccd, 0.95 vddp and 1.9-2.0 vdd18, probably not worth it, but if you still get reboots and lots of WHEA19 don't bother, make 3800/1900 run tight


----------



## Taraquin

Veii said:


> It should function on Intel, has to else anta wouldn't mention it at all ~ tRFC shifting
> tRFC pausing "could" exist on micron, which would explain why it can not be lower than 300ns (near that) but i am not sure it really is able to
> ^ tRFC pausing exists on LPDDR and GDDR
> 
> On AMD Firmware, in any documents i could read ~ it does not exist. It's not a thing we can use
> But as for tRFC by itself, it wouldn't matter at first till your timings are not the bottleneck anymore
> Then it matters and shows effects - before that being 10ns off here doesn't show a big effect or non at all.
> Any operation halts while tRFC is active, which anta is correct that there is no direct connetion
> But so am i correct, that IC amount (8,16) also are not a direct connection and that thing doesn't work out in fractions of 8,16,32.
> It can not be order based. I mean it "could" but it won't ~ up to order of preset and order of recharge.
> It's random which rank is recharged first and which IC. Only tREFI recharges everything
> Soo while it is correct to move it in these fractions by 8 or 16 tCK ~ it is not for tRFC by itself. It's just the distance
> It will not dictate how low or high tRFC can be and what type of refresh algorithm is automatically decided to be used by DIMM-PCB (MSR)
> 
> Soo the rule (increase/decrease tRFC by factor of 8 for SR or 16 for DR) matters only for tREFI
> You can equally rotate this wording and say "increase tREFI by 16 for SR or 32 for DR"
> But tREFI is fixed on our side ~ and tMAC.tMAW (RC_Page) is something to explore with anta's rule
> 
> Meaning,
> Deciding what tRFC has to be within 2 or 3 tCK is not calculable by any rule that can not simulate memory transition delays
> Soo can not say "this whole thing for read, write, recharge" takes 80ns - tRFC has to be every 160ns or so
> it can not work that way
> 
> What can be used, is X predicted tRFC +/- 8,16,32 // if we go to follow his rule
> But even that is problematic, as you can not say tREFI = 9* tRFC, done
> You can not adjust tREFI on AMD , soo this 8,16,32 IC dependent rule can not work out
> And tRFC does not shift but is repeated ~ soo also one more point why this rule can not work out
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I've tried that, but moved away from it
> It's dynamic ~ it can not work that way.
> It maybe can work with JEDEC specific timings, just increased or decreased ~ but it can not work with any other custom user timings that will simply not add up to this.
> 
> To have a realistic prediction, it needs to also factor vdimm-to-amperage math
> Then you can create for ICs and for PCBs "min/max" tRFCns distances for X amperage
> Only then , yes then it can be correct
> But till then ~ anything is a prediction, and i just took a different anchor which before was CAS
> Only that CAS and RAS should be seen the same way , tRCD is unique both RAS and CAS scale by voltage
> tRC is the only thing that is consistent, if you keep the math up (tRC = tRP+tRAS)


I don't understand all you write, but lowest stable rfc that does not cause performance regresdion is best then? 

As for scaling, only B-die to my knowledge scales positive with rfc/voltage. I have never been able to lower rfc on Hynix/Micron or Samsung C/D/E if I up voltage.


----------



## KedarWolf

New AIDA64 available.


----------



## Bloax

97pedro said:


> Just to share my settings as of today.
> 
> Best I could get out of a 3200mhz cl14 Flare X kit (2 of them).
> 
> Any thoughts?
> View attachment 2555778


veii don't be silly 🤡, DJR doesn't run 132 ns tRFC

Thoughts? Alright








[Official] Intel Z690 / Z790 DDR4 Daily Memory Overclock


So for ddr4000 I need to go from 1.32 to 1.56?!? That’s A LOT for just 100mhz gain? With these procODT/RTT settings on my sticks, +/- 100 MCLK costs 0.06v, and +/- 1 tRCDRD costs 0.09v (while keeping all primary timings equal) So if yours scale similarly, then it's 1.32v to 1.56v if you want...




www.overclock.net




I would be _very_ surprised if there's such a massive tRCD/RP variance in this kit (+3 at the same voltage is basically Top Bin vs. Bottom Bin in b-die land), unless caused by improper powering.

For CADBus, others seem to have some success running 40-24-24-24 ? Maybe 60-24-30-24 or 60-24-24-24 since this is 4x8 ??

Beyond that, I wouldn't be surprised if those sticks are also among the ones who want Nom/6 (40) and Park/5 (48) or /6 (40)
CPU 1.8v seems to be well-hidden in the ASUS BIOS, but it's either 1.8v PLL (unlikely) or ""1.8v Standby Voltage"" - cranking that up to 1.85-1.93v, if it is CPU 1.8v, should make procODT 30-28.2 work ?


Combining all these powering/signalling things might fix this weirdly high RCD requirement.


----------



## 97pedro

Veii said:


> tWTR_L to 8
> or tRRD_L to 5
> 
> pick one
> EDIT:
> or tRRD_L 6 & tWTR_L 6
> together , but that likely is too low
> 
> Is that micron Rev.B ?
> Hynix ?


Why one or the other, can't I use tWTR_L 8 and tRRD_L 5 at the same time?

It's b die😋


----------



## Viron

SaarN said:


> snapp


Yea, this is AMD speaking to you dirctly  
Well, not much to do. Is your Trfc very thight? If you really want to try, you have to test more with the voltages. Try changing proc ODT etc too. 
.


----------



## domdtxdissar

Maybe i will buy a 5800x3d to play around with after all...

*AMD Ryzen 7 5800X3D Zen3 CPU has finally been tested in games*

Too bad they only tested with 3200MT/s..
Should have used dd4 @ 3800 for x3d and ddr5 @ 6800 for AL

*Bonus: The Witcher 3 – Intel Core i9-12900K DDR4-3600 CL14 data*
To check if there was any scalability with this title in particular, we installed *4 DIMMs of DDR4-3600 CL14* kits in our system. _There was definitely an improvement over 3200C14_ so next step is benchmark *12900K DDR5-6200 C40*.


----------



## KedarWolf




----------



## Audioboxer

Veii said:


> I see it repeated multiple times, and while anta is correct looking at it from the bigger picture ~ the theory
> The practice doesn't match on AMD Memory Controller capabilities
> 
> Like touched on this here,
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Try 16, 8, 18, 16, ras 42, rc 60, rfc 600, cwl 16, see if that makes errors go away? If it works try rdwr 10, 9 or 8. Still have way too many error instantly + 1 bluescreen from 1.55 to 1.6V. I don't dare to go further.
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> It can not be a thing ~ as there is no support neither by the IMC, nor by Samsung IC and not either by dimms without a thermal sensor
> 
> tRFC pausing, or tRFC shifting is not a feature we can use.
> It might be designed by JEDEC and dimm MSR (option) ~ the chip, "might" support it , shifting to it in real time
> But purely our own IMC is not capable to do this ~ and b-dies are not capable to do tRFC pausing either
> Potentially Micron OEM Dimms can do it ~ but i am to this date not sure they really can use this feature of DDR4
> 
> A shift of 16 or 32, i've been there
> Old mini module was exploring this, but JEDEC is not always something that is followed anywhere
> Soo i moved away from it, it's not a thing.
> It matches in theory, but in practice it's simply not a thing
> 
> ICs by side are not refreshed in order, as interleaving and refresh stacking exists
> Soo virtual nCK value of 8 ICs or 16 ICs can not work out, it's too dynamic and MSR defines refresh method for tRC dynamically up to preset state (CAS bef RAS refresh most commonly used)
> 
> Anta's rule can only work out, for his method of preset building and only on systems which support tRFC shifting
> 
> Hence all this,
> Pushing tRFC down, needs consistent access latency testing and not only bandwidth testing
> (BW should show a change but doesn't always have to show up in tests like pi-calculation)
> A missed tRFC is about a distance of 0.3-0.5ns (increase)
> 
> A low tRAS will show faster burst access on the first test after X recharge
> ~ when cells are already in a charged state
> But as low tRAS misses tRP before it to (p)recharge the row it tries to access & move data for the whole row read not to erase it
> It will not be a consistent faster thing.
> Soo even if RAS strobe time ~ check time, is bursty and short - it still will have to sometimes wait for cells to be in a ready usable state
> And then "tight tRAS" does not matter.
> 
> The same for tRC and the same for tRFC
> A high tRFC does cut into "maximum potentially usable" ~ bandwidth
> ^ hence memory has to wait for tRFC to elapse which is a continuous trigger that happens every time inside predefined tight tREFI window (on AMD)
> A low tRFC will increase "the chance of operation" , so called "potential higher bandwidth by more free-usable time" in defined tREFI window
> With another rephrased sentence "the potential non bottlenecked usable bandwidth free-operation time"
> 
> But "low tRFC" will not do anything, even when it increases "ceiling of potential usable bandwidth"
> When memory timings 1st, don't have fluid transitions ~ and 2nd, are simply too high, to even being able to reach near that bandwidth ceiling
> Only when timings are very tight, independent of MCLK ~ only then tRFC drop, will show any latency decrease and bandwidth increase
> 
> Dual Rank and higher density dimms are more affected by this "has to recharge volatile memory" thing called tRFC
> ~ hence there the issue of "high tRFC" becomes more apparent
> But there is a limit where you move around and that ETA was the only goal of tRFC mini
> ~ predict correct recharge & predict discharge, since the foundation couple of years ago.
> 
> 
> 
> 
> 
> 
> 
> 
> Please click on the link, and try to read my mess of lecture
> It goes more direct into it ~ this post here is more of a reminder and repeat
> I know what anta is using, and been there - but it does not work out, not here at least.
> 
> Soo i move in another scale. Which is called " Row Cycle Time "
> Instead of on a chip-by-chip scale
> @Bloax is a good observer for rare changes. He is quite skilled in that without having to read technical papers
> So was my initial foundation build upon.
> Just now i know, that ICs are not refreshed consistently and tRFC is used differently
> Most of the times it being low doesn't matter ~ but it being "just on time" does matter for the bigger picture
> ==============================================================
> @Audioboxer , bios i gave you was an attempt to fix the disabled OC "bugs" that came with newer AGESA
> It had more changes than this, and it expected you to redo CO's as voltage requests will be much higher
> But as you confirmed that the bug is not solved , the attempt from me was a failure
> Read your message and reports ~ simply busy atm. Only lurking on this thread


I still don't understand what this means for tRFC.... lol

To put it simply, if I run 209 instead of 208 because 209 = 110ns exactly, this isn't a detriment to performance? What if I run 205 or 206 because it's OK at 1.63v?


----------



## Bloax

The Big tl;dr of it is that not only does tRFC have this nasty habit of being questionably stable at random intermediate values, but also has questionable performance benefits (or regressions) depending on what you run tRAS/tRC as.


And yes, I'm not surprised that the 5800X3D can be incredible in some tasks.
Now, if it becomes less of a pain in the ass to make the processors not choke on their own drool on AM5, that'll be great! 🤡

Because while taking an extra 60-120 minutes of watching paint dry is fine for the Home Enthusiast, an extra 60-120 minutes of manual labour just for the CPU while you attempt to mass-produce systems with overclocked memory (which is its own can of worms) - that starts to add up real fast! 🔥🤡🔥


----------



## 97pedro

97pedro said:


> Just to share my settings as of today.
> 
> Best I could get out of a 3200mhz cl14 Flare X kit (2 of them).
> 
> Any thoughts?
> View attachment 2555778


You guys know what I can do to try to stabilize tRCDRD at 16, instead of 17?

Edit: I know @Bloax just trying to see what else I can get out of this


----------



## KedarWolf

Oh, did I mention I'm running these timings at 1.5v for memory in BIOS, VTTs at .730v?

I definitely won the silicon lottery on this second same kit.


----------



## Audioboxer

KedarWolf said:


> Oh, did I mention I'm running these timings at 1.5v for memory in BIOS, VTTs at .730v?
> 
> I definitely won the silicon lottery on this second same kit.
> 
> View attachment 2555835


If you loosen tRFC a bit 1.5v is likely still high for these bins. I managed flat 14 at 1.44v.

Try going for 1.48v or something.


----------



## KedarWolf

Deleted


----------



## KedarWolf

Audioboxer said:


> If you loosen tRFC a bit 1.5v is likely still high for these bins. I managed flat 14 at 1.44v.
> 
> Try going for 1.48v or something.


Someone here runs 1.6v for CL13 and 1.5 totally safe for this b-die.

Most are running around 1.54v for the same timings.

But yeah, not much difference between 240 and 252 but either way I needed 1.5v, I already tried both. 

Edit: Let me try 252 at 1.48.


----------



## KedarWolf

KedarWolf said:


> Someone here runs 1.6v for CL13 and 1.5 totally safe for this b-die.
> 
> Most are running around 1.54v for the same timings.
> 
> But yeah, not much difference between 240 and 252 but either way I needed 1.5v, I already tried both.
> 
> Edit: Let me try 252 at 1.48.


In TM5 100's of errors within the first minute.

But I've always known my IMC needs higher voltages than most do to be stable. Hence the high VSOC etc.


----------



## ArchStanton

KedarWolf said:


> Oh, did I mention I'm running these timings at 1.5v for memory in BIOS, VTTs at .730v?


While I read the "new" posts made to this thread as they come in, I'm also reading the "historical" ones as time allows (about page 415 currently). I like the "look" of Kedar's settings here. Stops at 1900fclk to avoid all the "wackiness" and latency penalties (assuming looser timings) of higher fclk. I have read repeatedly in the bowels of this thread that higher vSOC does eat into the CPU power budget, but I have no conception of how much. Does it matter for those of us with manual PBO limits? Does the extra "heat" from higher vSOC possibly shave a boost bin or two off peak ST boost frequencies? I wish I had a better understating of what a vSOC above 1.1v costs us, if anything 🤷‍♂️.


----------



## KedarWolf

ArchStanton said:


> While I read the "new" posts made to this thread as they come in, I'm also reading the "historical" ones as time allows (about page 415 currently). I like the "look" of Kedar's settings here. Stops at 1900fclk to avoid all the "wackiness" and latency penalties (assuming looser timings) of higher fclk. I have read repeatedly in the bowels of this thread that higher vSOC does eat into the CPU power budget, but I have no conception of how much. Does it matter for those of us with manual PBO limits? Does the extra "heat" from higher vSOC possibly shave a boost bin or two off peak ST boost frequencies? I wish I had a better understating of what a vSOC above 1.1v costs us, if anything 🤷‍♂️.


In CPU-Z single thread I get around 685 which is decent, multithreaded I get over 13500, which is nice. But yeah, my IMC needs that to get those timings TM5 stable, I've tried lower, no go.


----------



## Audioboxer

KedarWolf said:


> In TM5 100's of errors within the first minute.
> 
> But I've always known my IMC needs higher voltages than most do to be stable. Hence the high VSOC etc.


It could be secondaries?










This was done like 7 months ago so way back when I was a newbie to memory, but it gives an idea.

Unless you are struggling thermally, it really doesn't matter. Just wanted to give you a heads up lower might be possible.


----------



## Audioboxer

AMD Ryzen 7 5800X3D Review - The Magic of 3D V-Cache


The AMD Ryzen 7 5800X3D is the company's new flagship gaming processor. It introduces 3D V-Cache, a dedicated piece of silicon with additional L3 capacity. In our review, we're testing how much the larger cache can help intensive gaming workloads and applications and compare it to the Intel Core...




www.techpowerup.com





Out of the box this looks decent, but the fact you can't overclock it means with how close the 5950x is in most gaming benchmarks if not equal, a 5950x on PBO should have little issue surpassing or catching.

"No one" is playing games at 720p, and performance normalisation kicks in at 1440p and really hits at 4K.

Basically, a chip for the mass market who don't want to deal with OCing. A decent buy for some but I'd advise folks like us not to "waste" your money.


----------



## Blameless

Audioboxer said:


> AMD Ryzen 7 5800X3D Review - The Magic of 3D V-Cache
> 
> 
> The AMD Ryzen 7 5800X3D is the company's new flagship gaming processor. It introduces 3D V-Cache, a dedicated piece of silicon with additional L3 capacity. In our review, we're testing how much the larger cache can help intensive gaming workloads and applications and compare it to the Intel Core...
> 
> 
> 
> 
> www.techpowerup.com
> 
> 
> 
> 
> 
> Out of the box this looks decent, but the fact you can't overclock it means with how close the 5950x is in most gaming benchmarks if not equal, a 5950x on PBO should have little issue surpassing or catching.
> 
> "No one" is playing games at 720p, and performance normalisation kicks in at 1440p and really hits at 4K.
> 
> Basically, a chip for the mass market who don't want to deal with OCing. A decent buy for some but I'd advise folks like us not to "waste" your money.


I still want to see how the part behaves on firmware that pre-dates official support for it.

Anyway, both TPU and xanxogaming are showing very significant performance improvements in Borderlands 3, which is the only UE4 game I've seen tested, so far. This itself has pretty much sold me on the part as half of the games I play are UE4 and many of them are CPU limited at 1440p/4k ultra on my 5800X + 6800XT setup.


----------



## domdtxdissar

Audioboxer said:


> AMD Ryzen 7 5800X3D Review - The Magic of 3D V-Cache
> 
> 
> The AMD Ryzen 7 5800X3D is the company's new flagship gaming processor. It introduces 3D V-Cache, a dedicated piece of silicon with additional L3 capacity. In our review, we're testing how much the larger cache can help intensive gaming workloads and applications and compare it to the Intel Core...
> 
> 
> 
> 
> www.techpowerup.com
> 
> 
> 
> 
> 
> Out of the box this looks decent, but the fact you can't overclock it means with how close the 5950x is in most gaming benchmarks if not equal, a 5950x on PBO should have little issue surpassing or catching.
> 
> "No one" is playing games at 720p, and performance normalisation kicks in at 1440p and really hits at 4K.
> 
> Basically, a chip for the mass market who don't want to deal with OCing. A decent buy for some but I'd advise folks like us not to "waste" your money.


It is worth noting that TPU ran 5800X3D with 2x 16GB DDR4- *3600MT/s 16-20-20-34 GDM* memory and Alder Lake CPUs with 2x 16GB DDR5-6000 (36-36-36-76 2T / Gear 2.

I would say this is very bad timings for 3600MT/s speeds nowadays.. 3800 16-16-16-32 would have been a much more "even" benchmark against AL on ddr5 6000 CL36
For a comparison, with my current rig i run *3800MT/s 13-14-12-22 *real T1

Oh well.. 2 more days to official benchmarks


----------



## MrHoof

For a sec I thought u got it running with setup timings with the real 1T.
But is it really, to few people to compare I guess on my SR setup I could test it and it was no noticeable diffrence with setup or without.
But on my DR kit I could never test it, belive it or not I cant even boot with setup timings (instant bluescreen) but 1T works flawless without.


----------



## KedarWolf

This works, and the biggest test is I don't get a random reboot when running Cinebench R20 or R23 as a real-time priority.

I've never had 1000% one cycle pass then default 1usmus_v3 25 cycles fail. And it takes less than an hour to run for a solid quick test.

And I gain 100 points in R23, so yes, high VSOC and VDDGs DO cut into the power budget.


----------



## KedarWolf

MrHoof said:


> For a sec I thought u got it running with setup timings with the real 1T.
> But is it really, to few people to compare I guess on my SR setup I could test it and it was no noticeable diffrence with setup or without.
> But on my DR kit I could never test it, belive it or not I cant even boot with setup timings (instant bluescreen) but 1T works flawless without.


I tried AddrCmdSetup at 0 instead of 56, instant BSOD booting into Windows.

But normally true 1T refers to 1T with GDM off.


----------



## KedarWolf

Got this today though.


----------



## attitus3

I've been trying to tighten tRCDRD from 19 to 17 and I'd tried everything I can think of, I've tried procODT from 28.2 to 48, RTTs of 6/3/3, 6/3/4, 7/3/1, and voltages from 1.46 to 1.5. My sticks are g.skill b-die 3200 15-15-15-36-50. I'd appreciate any advice.


----------



## TMavica

attitus3 said:


> I've been trying to tighten tRCDRD from 19 to 17 and I'd tried everything I can think of, I've tried procODT from 28.2 to 48, RTTs of 6/3/3, 6/3/4, 7/3/1, and voltages from 1.46 to 1.5. My sticks are g.skill b-die 3200 15-15-15-36-50. I'd appreciate any advice.


ProcODT too high, maybe you can try 34.3 7/3/3, Clk, Addrcmd, csodt, cke to 40/20/24/24, trfc 272, SCL both 4, trtp should be 5
i guess you can stay 15-15-15-30, TRC 45 with 3800, vdimm 1.45


----------



## Blameless

domdtxdissar said:


> 3800 16-16-16-32 would have been a much more "even" benchmark against AL on ddr5 6000 CL36


TPU's sample can't do 1900 FCLK.


----------



## domdtxdissar

Blameless said:


> TPU's sample can't do 1900 FCLK.


Yeah i saw they wrote that.. They must have been super unlucky to get a single CCD cpu which cant do atleast 3800 MT/s 1:1, like pretty much 99.99% of all 5600x's and 5800x's will do 3800 and above. (or incompetence judging from their ddr4 memory timings)

And it seems like hardwareunboxed have no problems running their sample at 4000 MT/s 1:1 judging from their poll. (think this will be the norm)


----------



## Audioboxer

attitus3 said:


> I've been trying to tighten tRCDRD from 19 to 17 and I'd tried everything I can think of, I've tried procODT from 28.2 to 48, RTTs of 6/3/3, 6/3/4, 7/3/1, and voltages from 1.46 to 1.5. My sticks are g.skill b-die 3200 15-15-15-36-50. I'd appreciate any advice.


Generally speaking tRCDRD either works or it doesn't. You can test this by running all secondary timings on AUTO and just playing with primaries.

If errors spit out like mad running under tRCDRD 19 then it's just the memory can't handle it. Try for 18 I guess?

The 3200C14 kits are normally quite _easy_ to get to 3800 16-16-16-16 around 1.45v. Not too familiar with your kit.


----------



## Mach3.2

@Audioboxer Regarding your 3080 FTW3 400W hard cap problems, it's just evga lol.. It has been this way since the 3080 launched. It's really just luck of the draw, some can max out the 450W, the unlucky ones like you get hard capped at 400W. No real apparent difference between the cards that can or cannot do 450W either.


----------



## Audioboxer

Mach3.2 said:


> @Audioboxer Regarding your 3080 FTW3 400W hard cap problems, it's just evga lol.. It has been this way since the 3080 launched. It's really just luck of the draw, some can max out the 450W, the unlucky ones like you get hard capped at 400W. No real apparent difference between the cards that can or cannot do 450W either.


Sucks when you have good cooling lol. EVGA are scrambling about trying to answer my support ticket, after asking for my BIOS version it was "we'll away talk to technical support to see if there are any new firmwares". That was 2 days ago. I expect I won't hear back lol.


----------



## Mach3.2

Audioboxer said:


> Sucks when you have good cooling lol. EVGA are scrambling about trying to answer my support ticket, after asking for my BIOS version it was "we'll away talk to technical support to see if there are any new firmwares". That was 2 days ago. I expect I won't hear back lol.


I'm sure you'll hear back from them but I suspect you're SOL either way. Even those with 3090s who were allowed to RMA their cards received no guarantees that the swap will fix the problem. I believe some got back cards that still have unbalanced power draw on the PCIe power connectors.


----------



## Audioboxer

Mach3.2 said:


> I'm sure you'll hear back from them but I suspect you're SOL either way. Even those with 3090s who were allowed to RMA their cards received no guarantees that the swap will fix the problem. I believe some got back cards that still have unbalanced power draw on the PCIe power connectors.


Yeah I'm not RMAing, I don't want to risk a refurb unit. I'm happy with this card, just the power limit hard wall at 400w sucks.


----------



## Tebore

I'm back again. I tested my memory up to 4400 MCLK. with 20,22,22,44 just to get it out of the way. Is 1900FCLK the hard limit for most Zen2? Is it a chip or a board limit at this point? 
No matter what I do I can't boot even 1 Mhz above 1900. I even went as far as 1.2 SoC and 1.05 IoD and 1v for VDDP and CCD. 
I am able to do 1:1:1 3800/1900 BCLK 100 (99.8).
I attached my daily timings setup. Right now I run it at 101 BCLK to get a higher CPU PBO boost.
VDDG IoD is 1v to eliminate Audio pops.


----------



## Bloax

The FCLK 1900 wall is a software limitation, as is evident by some super early (but not necessarily The First with Zen3 Support) Zen3 BIOSes accidentally enabling it on Zen3 processors too.


----------



## Tebore

Bloax said:


> The FCLK 1900 wall is a software limitation, as is evident by some super early (but not necessarily The First with Zen3 Support) Zen3 BIOSes accidentally enabling it on Zen3 processors too.


Thanks. That's what I thought. I guess it's part of the AGESA that's preventing it. 
That's unfortunately since getting to 1900IF was relatively easy I figured there might be more headroom in the chip push the memory since at my current settings I can get another a little more out of the RAM before I have to loosen the RCDRD more.


----------



## Blackfyre

I was reading that some stabilise and can achieve better timings by playing around with *Mem VTT*.

*Where is that setting in the Asus BIOS?* And do you peeps change it around here? What impact does it have on timings?

I have CLDO VDDP, VDDG CCD, and VDDG IOD all set to *0.975* in the BIOS.
VSOC is at 1.1250v in the BIOS.

My ZenTimings does not read VDIMM or VTT MEM.

My VDIMM is 1.495v

VTT MEM I am assuming is on auto and have no idea where to find it.

*EDIT:* I found it in the *Tweaker's Paradise* section, called VTTDDR Voltage. 

Mine is set to auto, which by the description is half of VDIMM, so it should be 0.7475

Any advantage or disadvantage to raising or decreasing it?


----------



## KedarWolf

Blackfyre said:


> I was reading that some stabilise and can achieve better timings by playing around with *Mem VTT*.
> 
> *Where is that setting in the Asus BIOS?* And do you peeps change it around here? What impact does it have on timings?
> 
> I have CLDO VDDP, VDDG CCD, and VDDG IOD all set to *0.975* in the BIOS.
> VSOC is at 1.1250v in the BIOS.
> 
> My ZenTimings does not read VDIMM or VTT MEM.
> 
> My VDIMM is 1.495v
> 
> VTT MEM I am assuming is on auto and have no idea where to find it.
> 
> *EDIT:* I found it in the *Tweaker's Paradise* section, called VTTDDR Voltage.
> 
> Mine is set to auto, which by the description is half of VDIMM, so it should be 0.7475
> 
> Any advantage or disadvantage to raising or decreasing it?
> View attachment 2555960


Sometimes having too high VTTs can cause instability. I run memory at 1.5v but keep VTTs at .730v. 

I think it was @Veii that said VTT too high causes instability and they keep it at around .730v too but I could be wrong.


----------



## Audioboxer

Bloax said:


> The FCLK 1900 wall is a software limitation, as is evident by some super early (but not necessarily The First with Zen3 Support) Zen3 BIOSes accidentally enabling it on Zen3 processors too.


Wouldn't it be correct to say it's a software limitation created because the hardware can't reliably run above 1900 FCLK? All the USB drop outs and/or pretty high voltages needed to even try and force the IF?

Due to how secretive AMD are we end up with folks like Veii trying to explain why IF has such issues at 2000, and even then I still don't understand it because Veii seems to imply AMD COULD fix it.

Only the G chips seem to reliably get to something like 2000.


----------



## VPII

Okay @Taraquin here is my new run with TM5 25 cycles and it seems to work. Thank you.


----------



## Blackfyre

Blackfyre said:


> I was reading that some stabilise and can achieve better timings by playing around with *Mem VTT*.
> 
> *Where is that setting in the Asus BIOS?* And do you peeps change it around here? What impact does it have on timings?
> 
> I have CLDO VDDP, VDDG CCD, and VDDG IOD all set to *0.975* in the BIOS.
> VSOC is at 1.1250v in the BIOS.
> 
> My ZenTimings does not read VDIMM or VTT MEM.
> 
> My VDIMM is 1.495v
> 
> VTT MEM I am assuming is on auto and have no idea where to find it.
> 
> *EDIT:* I found it in the *Tweaker's Paradise* section, called VTTDDR Voltage.
> 
> Mine is set to auto, which by the description is half of VDIMM, so it should be 0.7475
> 
> Any advantage or disadvantage to raising or decreasing it?
> View attachment 2555960


Okay so to confirm, the information I found so far:

*Tweaker's Paradise* section:

VTTDDR Voltage: Should be half of vDIMM? And should be set manually?
VDDP Voltage: Should be equal to SOC Voltage? And should be set manually?

Any advantages to decreasing or increasing?

I was thinking of making them both half of the default values (so decreasing them).

So VTT = Half of XMP value 1.35 / 2 = 0.675 (_instead of 1.5 / 2 = 0.75_)
And VDDP = ~1.08v which I believe is the default SOC Voltage with no overclock or anything done. (_instead of 1.125v, which is current SOC Voltage_).


----------



## MrHoof

Audioboxer said:


> Wouldn't it be correct to say it's a software limitation created because the hardware can't reliably run above 1900 FCLK? All the USB drop outs and/or pretty high voltages needed to even try and force the IF?
> 
> Due to how secretive AMD are we end up with folks like Veii trying to explain why IF has such issues at 2000, and even then I still don't understand it because Veii seems to imply AMD COULD fix it.
> 
> Only the G chips seem to reliably get to something like 2000.


That has a other reason the G chips dont have a seperate I/O die.
5600g


----------



## KedarWolf

Blackfyre said:


> Okay so to confirm, the information I found so far:
> 
> *Tweaker's Paradise* section:
> 
> VTTDDR Voltage: Should be half of vDIMM? And should be set manually?
> VDDP Voltage: Should be equal to SOC Voltage? And should be set manually?
> 
> Any advantages to decreasing or increasing?
> 
> I was thinking of making them both half of the default values (so decreasing them).
> 
> So VTT = Half of XMP value 1.35 / 2 = 0.675 (_instead of 1.5 / 2 = 0.75_)
> And VDDP = ~1.08v which I believe is the default SOC Voltage with no overclock or anything done. (_instead of 1.125v, which is current SOC Voltage_).


VDDP is normally run at .900v. VTTs I run at .730v for RAM at 1.5v. As I said, VTT too high can cause instability.

Edit: VTTDDR at .730v too.


----------



## Bloax

VDDP is relevant for scaling memory frequency - but since we hit a FCLK-shaped brick wall on DDR4 with 1:1, and 1:2 is only relevant on DDR5 - it's fairly irrelevant on Vermeer.

There is usually little to gain from running it much higher than the lowest it can run a given memory frequency at.. Which tends to be really low.
I think some mentions of higher values being relevant for PHYRDL hitting 26, but that's also a "only on certain boards" feature, as some are hardstuck 28.. Nor do I know the impact of this 28 vs 26 :- )

either way it is most definitely not close to vSOC


----------



## oobymach

I got my hynix kit stable at cl17 woot.


----------



## Bloax

oobymach said:


> I got my hynix kit stable at cl17 woot.


Stable, cycle 6 after 2:25 hours?
Looks to me like it crashed a long time ago, as each cycle takes roughly 7-9 minutes (depending on memory performance) @ 32 GB capacity :- )


----------



## oobymach

Bloax said:


> Stable, cycle 6 after 2:25 hours?
> Looks to me like it crashed a long time ago, as each cycle takes roughly 7-9 minutes (depending on memory performance) @ 32 GB capacity :- )


I may have monkied with the settings so is probably not original 1usmus profile, but no errors after over 2 hours looks stable to me 

Have lowered a couple other timings as per suggestion on other forum, testing with anta extreme profile atm.


----------



## 97pedro

Welp, managed to lower tRC, tRAS and tRP accordingly.









Any advantages on messing with the VTT voltage?


----------



## MrHoof

Bloax said:


> VDDP is relevant for scaling memory frequency - but since we hit a FCLK-shaped brick wall on DDR4 with 1:1, and 1:2 is only relevant on DDR5 - it's fairly irrelevant on Vermeer.
> 
> There is usually little to gain from running it much higher than the lowest it can run a given memory frequency at.. Which tends to be really low.
> I think some mentions of higher values being relevant for PHYRDL hitting 26, but that's also a "only on certain boards" feature, as some are hardstuck 28.. Nor do I know the impact of this 28 vs 26 :- )


Yes thats basicly me  its rather not hitting higher values but not going to low.
at 3800mhz
SR need 0.7v for 26/26
DR need 0.9v for 26/26
asus rog x570i itx 2dimm.

0.875 DR









edit: now running 7/2/6 RTT btw, worth a try too.


----------



## SaarN

Viron said:


> Yea, this is AMD speaking to you dirctly
> Well, not much to do. Is your Trfc very thight? If you really want to try, you have to test more with the voltages. Try changing proc ODT etc too.
> .


Heh, I'm half joking.
It's possible that my rock solid 1900fclk cpu can't tolerate those extra 33\66MHz, but it feels like something "helps" to make it behave so strangely until it hard crashes. 33MHz is all it took to take it from 100% to 0%.
Lemme get my tinfoil hat..
No WHEA errors \ usb disconnects \ cracking audio \ stuttering and I've tested it for more than a couple of days non-stop, so I shouldn't complain.
And then I open the OCing excel spreadsheet, stare at some of those majestic scores and sulk. The ones that don't make any sense are my favorite - people that seemd to randomly enter 2000fclk, with 90% of their settings set to auto, and got a rock solid machine with over 60k reads and write. Those are the real nice ones.


----------



## Veii

@SaarN Your tinfoil hat shines well, but it's not the users that fake it
It's first batch dual CCD (disabled 1st CCD only 2nd works) 5600X & 5800X users ~ who have rare samples. AMD messed it up on FW level & can only fix it on hardware level (local)
They will not supply any patch that exposes a backdoor and gives low level write permissions ~ soo they will never patch it or fix it for anybody
(maybe Q1 2023, after people moved to AM5)
AMD had the option to fix the mess at B2 revision level (extend, there is not much of a mess bellow 1933 strap) ~ even when anything up to 2067 was set in stone and preconfigured (but went lazy)

They could fix it, but chose not to
Story long, and deep with drama starting since December 2020
You likely don't want to move in that field, as you should like your gear and not search for flaws in anybody (vendor) or anything (unlucky sample) 
It's fine, much better than Pinnacle Ridge was ~ just a collection of unfortunate events (matisse is the same tho, AgesaBootLoader [ABL] FCLK lock ~ early on)
Poor vendors tho, with all the security restrictions and control-practices


Mach3.2 said:


> @Audioboxer Regarding your 3080 FTW3 400W hard cap problems, it's just evga lol.. It has been this way since the 3080 launched. It's really just luck of the draw, some can max out the 450W, the unlucky ones like you get hard capped at 400W. No real apparent difference between the cards that can or cannot do 450W either.
> 
> 
> Audioboxer said:
> 
> 
> 
> Sucks when you have good cooling lol. EVGA are scrambling about trying to answer my support ticket, after asking for my BIOS version it was "we'll away talk to technical support to see if there are any new firmwares". That was 2 days ago. I expect I won't hear back lol.
> 
> 
> Mach3.2 said:
> 
> 
> 
> I'm sure you'll hear back from them but I suspect you're SOL either way. Even those with 3090s who were allowed to RMA their cards received no guarantees that the swap will fix the problem. I believe some got back cards that still have unbalanced power draw on the PCIe power connectors.
> 
> 
> 
> 
> 
> Click to expand...
Click to expand...










[Official] NVIDIA RTX 3090 Owner's Club


Absolutely if your mem temp is good. Yes, max 70 degrees (4K gaming)




www.overclock.net




~ might want to check this and ongoing posts/pages

You know i was gone for some decent time ~ 3 weeks, a month maybe
Still not in the position to say " i'm 100% back " ~ many ongoing projects (these two are not my only ones)
But if you have an SPI flasher and/or want to head over to discord, i can make a bios for you

The cap is SRC limit per 8pin
It's a little chip that independent of shunts, controls how much current is allowed to be pulled by each 8pin
Default that is 150W per 8pin (450) and 68-87W PCIe power ~ 550 peaks






















^ my work(s)
That plus usually 226W chip powerlimit instead of 680W chip powerlimit, and 90W VRAM OC powerlimit
Anything user attempted higher ~ results in lowered voltage or hardcrash by cap , if not crash by voltage


97pedro said:


> Why one or the other, can't I use tWTR_L 8 and tRRD_L 5 at the same time?
> 
> It's b die😋


Maybe if you read some of my old posts, and want to follow my logic
Memory timings "lower" is never always "better"
It's all a balance thing between timings, which endresult is compared in access time BUT also bandwidth

if there is a cut in bandwidth compared to your old preset, then you should not bother
(so i like aida64 on non bloaty stable systems, as the very first test i always run ~ to see if wasting 20-25cycles TM5 makes any sense whatsoever)
But aida will never show "performance" . What it will show is if both parts improve and if cache starts to autocorrect and destabilize

Memory by itself, does many actions at the same time
It is linear on some little parts, but does many things at the same time
It triggers latency times (up-times) to the selected latency fields & if you miss it, soo doesn't fall on "rising clock"
aka, If you miss the open door time, you can not enter the castle and have to sleep over night till it opens again for a short period of time

Memory by itself always will try to perform and saturate the whole bandwidth that is available
Problem, even when you have full bandwidth always max full bandwidth ~ you "lose" bandwidth by bottlenecks
Bottlenecks are non fluid transitions and repeat timing delays, and bottlenecks are the time where memory does absolutely nothing and stops every process for tRFC and tREFI to elapse

Some timings are repeatable, tRAS is postponable (tRP is inserted to row precharge , if chargeloss is detected) and tRAS only then is used to it's full delay (row access strobe/check, after row is charged)
tRC tho is looped and looped every time. Soo any delay there that is inaccurate and bad transition of tRP+tRAS ~ meaning if it's missed then it's missed and memory will wait for tRC to repeat fully.
No timebreak possible

tRFC, if it's missed at the very end, which you have to time by how much charge you give memory and how hot they are (soo how fast they lose charge)
If that is missed, everything stops ~ that's a hard choke not like above timings // reason i designed my module to be always working by prediction, not show the minimum values
Soo tiny bit too low tRFC will be repeaten fully and you waste a lot of potential usable bandwidth, or you as always do waste something by it being too high 

tRRD and tWTR
They are transition timings, they are helping timings
Memory splits in reads and writes. DDR4 can do writes at the same time or mid reads, if it senses it's possible
But reads are heavy and reads destroy data + fully discharge. Soo every read needs to backup "not read out" data to somewhere else ~ copy it
Now if "transition timings" are too tight, while high delay slow action primaries work ~ tight delay burst primaries (all of them) will not work. As transitions will happen much quicker than remain timings can follow
"An overlap issue"

The same goes to tRDWR ,read to write delay
and tWRRD , write to read delay
^ this and above scale by capacity and chip amount ~ but rules here are in unison. They are equal for any IC vendor (mostly) it's all up to PCB design and chip amount

tCWL, tWR, tRTP are complicated
CWL is more of a virtual timing like tRC is a virtual but controllable timing
It's more there to trigger "ghost" CAS [tCL] (collumn lookup, soo database collumn lookup) before RAS (row lookup) can read data
most of it is row lookup, as collumns are equal many but easier to find "your registers, letter A to Z name sorted".
Yet there are many people who are named with E for example. Soo many that you need more drawers only with E register to cover all people's name with E [more banks and more chips]  something like this

tCWL is more inserted into writes and to delay the distance of it, like tAL (added latency) on LPDDR and GDDR (same volatile memory, different layout, but same thing)
tWR is another of these "inserted virtual" timings, but a write recovery
tRTP is also an inserted timing/virtual timing that is there to match and utilize a feature called prefetching, that came with DDR3

Sadly on all timings, i'm not good to explain technical terms ~ when i've been working without it for too long
Soo can not give it technical logic, just own logic
He explains it much better but in technical terms ~ yet not simple terms








Most important from all that technical terms is:
"That memory does many inserted and delayed timings at the same time"
And you always have to check your changes if there is positive outcome in both parts

Access latency will always be better, unless you dropped it that low, that it starts to choke, loop and repeat
That's the "range of how low you can go before some other timing becomes the bottleneck"
But that's what people i see only focus on - drop it as low as possible , as low as it's stable. But that's not the point at all. . . 
Drop it as low as long as both "maximum usable bandwidth" and "lowest possible latency within several runs" ~ bandwidth increases & latency decreases

You can afford if you want to waste time ~ to focus on latency only and sacrifice bandwidth
I do that here and there. To shift priorities helping set run lower tRCD than possible @Bloax surely hates me for that, but understands 🤗 same for XOC community that "doesn't" understand my high tRRD & tWTR 

But every change anywhere you do inside the chain of timed things, have to keep in mind ~ that it will ! always will, influence timings before , at the same time, or after ~ it
Every time.
Soo you have to think in pairs at absolute minimum


Code:


tWR & tRTP
tRC & tRP
tCWL & tRDWR
tRAS & tRTP
VDIMM & tRP
VDIMM & ClkDrvStr
ClkDrvStr & procODT
VDD18 & procODT
cLDO_VDDP & ClkDrvStr
SOC & procODT

and so on. . . 
All of them are a balance thing, change one drop the other, increase one ~ decrease the other

There is no guide, as i'm still amateur~
But if you read a lot of our community posts here
You will slowly find the information needed ~ and learn more new things
That's the goal of this thread, help assist and teach.
Not showcase people. Showcasing with records is fun, but mostly done to show new methods of balancing. We are not an XOC thread, no d*ckshowcase here 
Although tiny bit when your daily setup improves, haha


----------



## Baio73

Veii said:


> @SaarN Your tinfoil hat shines well, but it's not the users that fake it
> It's first batch dual CCD (disabled 1st CCD only 2nd works) 5600X & 5800X users ~ who have rare samples. AMD messed it up on FW level & can only fix it on hardware level (local)
> They will not supply any patch that exposes a backdoor and gives low level write permissions ~ soo they will never patch it or fix it for anybody.
> AMD had the option to fix the mess at B2 revision level (extend, there is not much of a mess bellow 1933 strap) ~ even when anything up to 2067 was set in stone and preconfigured (but went lazy)
> 
> They could fix it, but chose not to
> Story long, and deep with drama starting since December 2020
> You likely don't want to move in that field, as you should like your gear and not search for flaws in anybody (vendor) or anything (unlucky sample)
> It's fine, much better than Pinnacle Ridge was ~ just a collection of unfortunate events (matisse is the same tho, AgesaBootLoader [ABL] FCLK lock ~ early on)
> Poor vendors tho, with all the security restrictions and control-practices
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] NVIDIA RTX 3090 Owner's Club
> 
> 
> Absolutely if your mem temp is good. Yes, max 70 degrees (4K gaming)
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> ~ might want to check this and ongoing posts/pages
> 
> You know i was gone for some decent time ~ 3 weeks, a month maybe
> Still not in the position to say " i'm 100% back " ~ many ongoing projects (these two are not my only ones)
> But if you have an SPI flasher and/or want to head over to discord, i can make a bios for you
> 
> The cap is SRC limit per 8pin
> It's a little chip that independent of shunts, controls how much current is allowed to be pulled by each 8pin
> Default that is 150W per 8pin (450) and 68-87W PCIe power ~ 550 peaks
> View attachment 2556053
> View attachment 2556054
> View attachment 2556055
> 
> ^ my work(s)
> That plus usually 226W chip powerlimit instead of 680W chip powerlimit, and 90W VRAM OC powerlimit
> Anything user attempted higher ~ results in lowered voltage or hardcrash by cap , if not crash by voltage
> 
> Maybe if you read some of my old posts, and want to follow my logic
> Memory timings "lower" is never always "better"
> It's all a balance thing between timings, which endresult is compared in access time BUT also bandwidth
> 
> if there is a cut in bandwidth compared to your old preset, then you should not bother
> (so i like aida64 on non bloaty stable systems, as the very first test i always run ~ to see if wasting 20-25cycles TM5 makes any sense whatsoever)
> But aida will never show "performance" . What it will show is if both parts improve and if cache starts to autocorrect and destabilize
> 
> Memory by itself, does many actions at the same time
> It is linear on some little parts, but does many things at the same time
> It triggers latency times (up-times) to the selected latency fields & if you miss it, soo doesn't fall on "rising clock"
> aka, If you miss the open door time, you can not enter the castle and have to sleep over night till it opens again for a short period of time
> 
> Memory by itself always will try to perform and saturate the whole bandwidth that is available
> Problem, even when you have full bandwidth always max full bandwidth ~ you "lose" bandwidth by bottlenecks
> Bottlenecks are non fluid transitions and repeat timing delays, and bottlenecks are the time where memory does absolutely nothing and stops every process for tRFC and tREFI to elapse
> 
> Some timings are repeatable, tRAS is postponable (tRP is inserted to row precharge , if chargeloss is detected) and tRAS only then is used to it's full delay (row access strobe/check, after row is charged)
> tRC tho is looped and looped every time. Soo any delay there that is inaccurate and bad transition of tRP+tRAS ~ meaning if it's missed then it's missed and memory will way for tRC to repeat fully.
> No timebreak possible
> 
> tRFC, if it's missed at the very end, which you have to time by how much charge you give memory and how hot they are (soo how fast they lose charge)
> If that is missed, everything stops ~ that's a hard choke not like above timings // reason i designed my module to be always working by prediction, not show the minimum values
> Soo tiny bit too low tRFC will be repeaten fully and you waste a lot of potential usable bandwidth, or you as always do waste something by it being too high
> 
> tRRD and tWTR
> They are transition timings, they are helping timings
> Memory splits in reads and writes. DDR4 can do writes at the same time or mid reads, if it senses it's possible
> But reads are heavy and reads destroy data + fully discharge. Soo every read needs to backup "not read out" data to somewhere else ~ copy it
> Now if "transition timings" are too tight, while high delay slow action primaries work ~ tight delay burst primaries (all of them) will not work. As transitions will happen much quicker than remain timings can follow
> "An overlap issue"
> 
> The same goes to tRDWR ,read to write delay
> and tWRRD , write to read delay
> ^ this and above scale by capacity and chip amount ~ but rules here are in unison. They are equal for any IC vendor (mostly) it's all up to PCB design and chip amount
> 
> tCWL, tWR, tRTP are complicated
> CWL is more of a virtual timing like tRC is a virtual but controllable timing
> It's more there to trigger "ghost" CAS [tCL] (collumn lookup, soo database collumn lookup) before RAS (row lookup) can read data
> most of it is row lookup, as collumns are equal many but easier to find "your registers, letter A to Z name sorted".
> Yet there are many people who are named with E for example. Soo many that you need more drawers only with E register to cover all people's name with E [more banks and more chips]  something like this
> 
> tCWL is more inserted into writes and to delay the distance of it, like tAL (added latency) on LPDDR and GDDR (same volatile memory, different layout, but same thing)
> tWR is another of these "inserted virtual" timings, but a write recovery
> tRTP is also an inserted timing/virtual timing that is there to match and utilize a feature called prefetching, that came with DDR3
> 
> Sadly on all timings, i'm not good to explain technical terms ~ when i've been working without it for too long
> Soo can not give it technical logic, just own logic
> He explains it much better but in technical terms ~ yet not simple terms
> 
> 
> 
> 
> 
> 
> 
> 
> Most important from all that technical terms is:
> "That memory does many inserted and delayed timings at the same time"
> And you always have to check your changes if there is positive outcome in both parts
> 
> Access latency will always be better, unless you dropped it that low, that it starts to choke, loop and repeat
> That's the "range of how low you can go before some other timing becomes the bottleneck"
> But that's what people i see only focus on - drop it as low as possible , as low as it's stable. But that's not the point at all. . .
> Drop it as low as long as both "maximum usable bandwidth" and "lowest possible latency within several runs" ~ bandwidth increases & latency decreases
> 
> You can afford if you want to waste time ~ to focus on latency only and sacrifice bandwidth
> I do that here and there. To shift priorities helping set run lower tRCD than possible @Bloax surely hates me for that, but understands 🤗 same for XOC community that "doesn't" understand my high tRRD & tWTR
> 
> But every change anywhere you do inside the chain of timed things, have to keep in mind ~ that it will ! always will, influence timings before , at the same time, or after ~ it
> Every time.
> Soo you have to think in pairs at absolute minimum
> 
> 
> Code:
> 
> 
> tWR & tRTP
> tRC & tRP
> tCWL & tRDWR
> tRAS & tRTP
> VDIMM & tRP
> VDIMM & ClkDrvStr
> ClkDrvStr & procODT
> VDD18 & procODT
> cLDO_VDDP & ClkDrvStr
> SOC & procODT
> 
> and so on. . .
> All of them are a balance thing, change one drop the other, increase one ~ decrease the other
> 
> There is no guide, as i'm still amateur~
> But if you read a lot of our community posts here
> You will slowly find the information needed ~ and learn more new things
> That's the goal of this thread, help assist and teach.
> Not showcase people. Showcasing with records is fun, but mostly done to show new methods of balancing. We are not an XOC thread, no d*ckshowcase here
> Although tiny bit when your daily setup improves, haha


I appreciate every single word of your posts, but I disagree in the last part... you SHOULD write a guide down! You and other users here who can contribute, obviously.
RAM OC and tweaking is way too complicated for the most part of us, even if we can be elected as an "enlightened minority" over the mass of pc users (well, it's 6 o'clock in the morning and I'm here testing my CO curve.. have to go to work by 2 hours, so I guess I'm not so "enlightened")... too complicated even if one has enough time to spent on it, but may not have the skills to understand (and there is me).
Thanks anyway you'll decide! 

Baio


----------



## SaarN

Heh, I'm very impressed by the CPU, night and day difference in comparison to my previous R3600.
I was amazed at how effortlessly it would post using all of the profiles I had to put aside once my R3600 had given up / forced me to invest too much in never ending stability tweaks because the memory controller is took weak to compensate for sub optimal settings. Tried going from 3800cl15 to 3800cl14 right after installing it and not only it posted - but it was nearly stable, dayum, not to mention the 59.5k reads at 3800cl15, 3.5k higher than what I previously got and 55ns layency thanks to the 5.05GHz boost.
The only thing I don't really like about my sample is the huge performance gap between my 2 ccds.
One ccd being insanely stable with all 6 cores being capable of hitting 5.05GHz, and there's the other ccd, the lazy one that is 15c cooler because it's running like 500MHz slower. That also made me question my ability to properly mount a cooler and had me take the pc apart just to realize it wasn't the cooling after all.. but a ****ty ccd.
Crossing my fingers that it's bios related, AMD's known weak point of being too innovative for their programmers to be able to catch up with proper software support. 
It's probably a ****ty ccd, but maybe there's hope.


----------



## Veii

SaarN said:


> One ccd being insanely stable with all 6 cores being capable of hitting 5.05GHz, and there's the other ccd, the lazy one that is 15c cooler because it's running like 500MHz slower. That also made me question my ability to properly mount a cooler and had me take the pc apart just to realize it wasn't the cooling after all.. but a ****ty ccd.
> Crossing my fingers that it's bios related, AMD's known weak point of being too innovative for their programmers to be able to catch up with proper software support.
> It's probably a ****ty ccd, but maybe there's hope.


One CCD likely needs very low CO (big negative CO) the 2nd CCD
but if you go too low, it will interfere with first CCD

Throttling nearly always happens by FIT inside deciding, substrate is weak, and needs a lot of voltage
Its good at keeping up stability at any cost, and autocorrection is fantastic on vermeer too ~ maybe a bit too good (in-chip ECC)

Curve optimizer is a very bothersome topic with zero help from AMDs side. WIthout even an ability to track when FIT decides it's voltage limited ~ shame shame AMD, could do better
CoreCycler - tool for testing Curve Optimizer settings and so on 
You nearly always lose boost as cores demand too much , far beyond throttle range
Soo if substrate programmed peak voltage is 1.45v then it will throttle on any request after 1.4v


----------



## Audioboxer

Veii said:


> @SaarN Your tinfoil hat shines well, but it's not the users that fake it
> It's first batch dual CCD (disabled 1st CCD only 2nd works) 5600X & 5800X users ~ who have rare samples. AMD messed it up on FW level & can only fix it on hardware level (local)
> They will not supply any patch that exposes a backdoor and gives low level write permissions ~ soo they will never patch it or fix it for anybody.
> AMD had the option to fix the mess at B2 revision level (extend, there is not much of a mess bellow 1933 strap) ~ even when anything up to 2067 was set in stone and preconfigured (but went lazy)
> 
> They could fix it, but chose not to
> Story long, and deep with drama starting since December 2020
> You likely don't want to move in that field, as you should like your gear and not search for flaws in anybody (vendor) or anything (unlucky sample)
> It's fine, much better than Pinnacle Ridge was ~ just a collection of unfortunate events (matisse is the same tho, AgesaBootLoader [ABL] FCLK lock ~ early on)
> Poor vendors tho, with all the security restrictions and control-practices
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] NVIDIA RTX 3090 Owner's Club
> 
> 
> Absolutely if your mem temp is good. Yes, max 70 degrees (4K gaming)
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> ~ might want to check this and ongoing posts/pages
> 
> You know i was gone for some decent time ~ 3 weeks, a month maybe
> Still not in the position to say " i'm 100% back " ~ many ongoing projects (these two are not my only ones)
> But if you have an SPI flasher and/or want to head over to discord, i can make a bios for you
> 
> The cap is SRC limit per 8pin
> It's a little chip that independent of shunts, controls how much current is allowed to be pulled by each 8pin
> Default that is 150W per 8pin (450) and 68-87W PCIe power ~ 550 peaks
> View attachment 2556053
> View attachment 2556054
> View attachment 2556055
> 
> ^ my work(s)
> That plus usually 226W chip powerlimit instead of 680W chip powerlimit, and 90W VRAM OC powerlimit
> Anything user attempted higher ~ results in lowered voltage or hardcrash by cap , if not crash by voltage
> 
> Maybe if you read some of my old posts, and want to follow my logic
> Memory timings "lower" is never always "better"
> It's all a balance thing between timings, which endresult is compared in access time BUT also bandwidth
> 
> if there is a cut in bandwidth compared to your old preset, then you should not bother
> (so i like aida64 on non bloaty stable systems, as the very first test i always run ~ to see if wasting 20-25cycles TM5 makes any sense whatsoever)
> But aida will never show "performance" . What it will show is if both parts improve and if cache starts to autocorrect and destabilize
> 
> Memory by itself, does many actions at the same time
> It is linear on some little parts, but does many things at the same time
> It triggers latency times (up-times) to the selected latency fields & if you miss it, soo doesn't fall on "rising clock"
> aka, If you miss the open door time, you can not enter the castle and have to sleep over night till it opens again for a short period of time
> 
> Memory by itself always will try to perform and saturate the whole bandwidth that is available
> Problem, even when you have full bandwidth always max full bandwidth ~ you "lose" bandwidth by bottlenecks
> Bottlenecks are non fluid transitions and repeat timing delays, and bottlenecks are the time where memory does absolutely nothing and stops every process for tRFC and tREFI to elapse
> 
> Some timings are repeatable, tRAS is postponable (tRP is inserted to row precharge , if chargeloss is detected) and tRAS only then is used to it's full delay (row access strobe/check, after row is charged)
> tRC tho is looped and looped every time. Soo any delay there that is inaccurate and bad transition of tRP+tRAS ~ meaning if it's missed then it's missed and memory will way for tRC to repeat fully.
> No timebreak possible
> 
> tRFC, if it's missed at the very end, which you have to time by how much charge you give memory and how hot they are (soo how fast they lose charge)
> If that is missed, everything stops ~ that's a hard choke not like above timings // reason i designed my module to be always working by prediction, not show the minimum values
> Soo tiny bit too low tRFC will be repeaten fully and you waste a lot of potential usable bandwidth, or you as always do waste something by it being too high
> 
> tRRD and tWTR
> They are transition timings, they are helping timings
> Memory splits in reads and writes. DDR4 can do writes at the same time or mid reads, if it senses it's possible
> But reads are heavy and reads destroy data + fully discharge. Soo every read needs to backup "not read out" data to somewhere else ~ copy it
> Now if "transition timings" are too tight, while high delay slow action primaries work ~ tight delay burst primaries (all of them) will not work. As transitions will happen much quicker than remain timings can follow
> "An overlap issue"
> 
> The same goes to tRDWR ,read to write delay
> and tWRRD , write to read delay
> ^ this and above scale by capacity and chip amount ~ but rules here are in unison. They are equal for any IC vendor (mostly) it's all up to PCB design and chip amount
> 
> tCWL, tWR, tRTP are complicated
> CWL is more of a virtual timing like tRC is a virtual but controllable timing
> It's more there to trigger "ghost" CAS [tCL] (collumn lookup, soo database collumn lookup) before RAS (row lookup) can read data
> most of it is row lookup, as collumns are equal many but easier to find "your registers, letter A to Z name sorted".
> Yet there are many people who are named with E for example. Soo many that you need more drawers only with E register to cover all people's name with E [more banks and more chips]  something like this
> 
> tCWL is more inserted into writes and to delay the distance of it, like tAL (added latency) on LPDDR and GDDR (same volatile memory, different layout, but same thing)
> tWR is another of these "inserted virtual" timings, but a write recovery
> tRTP is also an inserted timing/virtual timing that is there to match and utilize a feature called prefetching, that came with DDR3
> 
> Sadly on all timings, i'm not good to explain technical terms ~ when i've been working without it for too long
> Soo can not give it technical logic, just own logic
> He explains it much better but in technical terms ~ yet not simple terms
> 
> 
> 
> 
> 
> 
> 
> 
> Most important from all that technical terms is:
> "That memory does many inserted and delayed timings at the same time"
> And you always have to check your changes if there is positive outcome in both parts
> 
> Access latency will always be better, unless you dropped it that low, that it starts to choke, loop and repeat
> That's the "range of how low you can go before some other timing becomes the bottleneck"
> But that's what people i see only focus on - drop it as low as possible , as low as it's stable. But that's not the point at all. . .
> Drop it as low as long as both "maximum usable bandwidth" and "lowest possible latency within several runs" ~ bandwidth increases & latency decreases
> 
> You can afford if you want to waste time ~ to focus on latency only and sacrifice bandwidth
> I do that here and there. To shift priorities helping set run lower tRCD than possible @Bloax surely hates me for that, but understands 🤗 same for XOC community that "doesn't" understand my high tRRD & tWTR
> 
> But every change anywhere you do inside the chain of timed things, have to keep in mind ~ that it will ! always will, influence timings before , at the same time, or after ~ it
> Every time.
> Soo you have to think in pairs at absolute minimum
> 
> 
> Code:
> 
> 
> tWR & tRTP
> tRC & tRP
> tCWL & tRDWR
> tRAS & tRTP
> VDIMM & tRP
> VDIMM & ClkDrvStr
> ClkDrvStr & procODT
> VDD18 & procODT
> cLDO_VDDP & ClkDrvStr
> SOC & procODT
> 
> and so on. . .
> All of them are a balance thing, change one drop the other, increase one ~ decrease the other
> 
> There is no guide, as i'm still amateur~
> But if you read a lot of our community posts here
> You will slowly find the information needed ~ and learn more new things
> That's the goal of this thread, help assist and teach.
> Not showcase people. Showcasing with records is fun, but mostly done to show new methods of balancing. We are not an XOC thread, no d*ckshowcase here
> Although tiny bit when your daily setup improves, haha


Thanks Veii, will keep an eye on progress in that 3090 topic. It's a 3080 I have and I likely would be waiting on nvflash working if it ever will, but great to see you helping out! Goes to show BIOS firmware is part of the issue!


----------



## Taraquin

Baio73 said:


> I appreciate every single word of your posts, but I disagree in the last part... you SHOULD write a guide down! You and other users here who can contribute, obviously.
> RAM OC and tweaking is way too complicated for the most part of us, even if we can be elected as an "enlightened minority" over the mass of pc users (well, it's 6 o'clock in the morning and I'm here testing my CO curve.. have to go to work by 2 hours, so I guess I'm not so "enlightened")... too complicated even if one has enough time to spent on it, but may not have the skills to understand (and there is me).
> Thanks anyway you'll decide!
> 
> Baio


Anta777 made a guide on timings, although a bit cryptic, some of his advice seems more Intel specific like RFC (maybe applies to Micron mem on AMD).


----------



## Bloax

SaarN said:


> One ccd being insanely stable with all 6 cores being capable of hitting 5.05GHz, and there's the other ccd, the lazy one that is 15c cooler because it's running like 500MHz slower. That also made me question my ability to properly mount a cooler and had me take the pc apart just to realize it wasn't the cooling after all.. but a ****ty ccd.
> Crossing my fingers that it's bios related, AMD's known weak point of being too innovative for their programmers to be able to catch up with proper software support.
> It's probably a ****ty ccd, but maybe there's hope.


Actually, you'd be surprised - but it has been caught in the wild by delidders that _the solder between the IHS and the CCD_ can have air bubbles or otherwise be suboptimal.
Which causes the exact symptoms of having "****ty" cores.


----------



## Tebore

Taraquin said:


> Anta777 made a guide on timings, although a bit cryptic, some of his advice seems more Intel specific like RFC (maybe applies to Micron mem on AMD).


Where is this guide? 
Also I wish there was an updated AMD Memory tweaking guide. Most of the stuff is for Zen 1 and only starts to touch on Zen 2 but lacks the technical deep dive especially settings exposed in later AGESAs.


----------



## Taraquin

Tebore said:


> Where is this guide?
> Also I wish there was an updated AMD Memory tweaking guide. Most of the stuff is for Zen 1 and only starts to touch on Zen 2 but lacks the technical deep dive especially settings exposed in later AGESAs.











Took a screenshot. No guide on voltages, ProcODT, DrvStr etc though, that is much more complex.


----------



## KedarWolf

Taraquin said:


> View attachment 2556156
> 
> Took a screenshot. No guide on voltages, ProcODT, DrvStr etc though, that is much more complex.


I break some timings rules with my RAM, but the latency, read and write I get is quite good. Basically the tCL tRP tRAS tRFC rules.

So with those, I'm not sure if following them is something set in concrete to get the best results.

Edit: I also run 4-2/6-2 instead of 4-4/6-6 and it helps some.


----------



## MrHoof

KedarWolf said:


> I break some timings rules with my RAM, but the latency, read and write I get is quite good. Basically the tCL tRP tRAS tRFC rules.
> 
> So with those, I'm not sure if following them is something set in concrete to get the best results.
> 
> Edit: I also run 4-2/6-2 instead of 4-4/6-6 and it helps some.


tWRWRDD and tRDRDDD are only used with 4 dimms as far as i understand.
tWRWRSD and tRDRDSD are only used on Dual Rank as far as i understand.
Thats why u can just throw them at 1 with 2xSR.


----------



## Melan

Taraquin said:


> Took a screenshot. No guide on voltages, ProcODT, DrvStr etc though, that is much more complex.


Here's the link. There is also more info on next pages too.


----------



## SaarN

Bloax said:


> Actually, you'd be surprised - but it has been caught in the wild by delidders that _the solder between the IHS and the CCD_ can have air bubbles or otherwise be suboptimal.
> Which causes the exact symptoms of having "****ty" cores.


What the heck...
Do people actually delid these cpus? what about the pins, do they do it while they're upside down? Not really a fan of this type of socket, I'd much rather have the pins on the board inside a sturdy case instead of taking my chances with them on hand, so that's a hard pass on the thought of delidding, eh.
Anyway, instead of complaining, here's my new chip.
I ran Aida64 while testing with CC in the background and keeping an eye on the temps and load with HWINFO64, while also doing light work related stuff (pdfs and mail).
So impressed to be able to ran these tests without having to use the laptop until they're done. So much power that I don't even feel like there's anything running in the background, it's surreal how smooth this thing runs.


----------



## Frosted racquet

Quick question, I'm pretty much finished testing CPU OC stability and will now tweak the RAM timings. Will changing the VDDP/VDDG and VDIMM affect CPU stability? I don't plan on touching vSOC.
I have quickly OCed the RAM from 3200 to 3600 with flat 18 timings and 1.4 VDIMM, passed several test with HCI Memtest, TestMem etc, and then proceeded to OC and stress test the CPU (which is near completion).
Now it's time to tweak the RAM timings without touching the frequency any further.

I'm hobing I don't have to test with CoreCycler again...


----------



## Bloax

SaarN said:


> What the heck...
> Do people actually delid these cpus? what about the pins, do they do it while they're upside down?


The process, if memory (haHAA) serves, is to cut most of the glue first - then bake them upside down in the oven while something holds the chip elevated over the surface by the diagonal edges of the PCB.

This will weaken whatever scraps of glue remain, and liquify the indium - at which point the IHS should plop down onto the baking tray from its own weight.

And yes, people actually direct-die'd these CPUs.
Unfortunately there's not much to gain from doing so besides the fantastic temperatures.. Due to in-chip power limits. 🤡👌

Though delidding can help with this CPU->TIM->IHS manufacturing defect, it is hard to guarantee this being "the problem".
The only way to "hint" towards it that I can think of is seeing whether single-core workloads in the bad CCD heat up the surrounding cores more than in the good CCD.


----------



## SaarN

Bloax said:


> The process, if memory (haHAA) serves, is to cut most of the glue first - then bake them upside down in the oven while something holds the chip elevated over the surface by the diagonal edges of the PCB.
> 
> This will weaken whatever scraps of glue remain, and liquify the indium - at which point the IHS should plop down onto the baking tray from its own weight.
> 
> And yes, people actually direct-die'd these CPUs.
> Unfortunately there's not much to gain from doing so besides the fantastic temperatures.. Due to in-chip power limits. 🤡👌
> 
> Though delidding can help with this CPU->TIM->IHS manufacturing defect, it is hard to guarantee this being "the problem".
> The only way to "hint" towards it that I can think of is seeing whether single-core workloads in the bad CCD heat up the surrounding cores more than in the good CCD.


I mean, if I had water cooling I would have paid someone to do this process for me, it should be worth it in the case of direct die, both for performance and reliability. It won't surprised me if my stronger CCD has an extra 100-150MHz to spare if I had the option to take it close to room temp.
Sadly, I got a SFF case that had zero airflow and I had to spend $200 on extras from Noctua just to get slightly better than average cooling performance, meh.
Now when I'm thinking about Ryzen 7000 being right around the corner, this thought would have made sense 2 years ago, because I'm pretty sure it will have no issues boosting to 5GHz all core considering the jump between Zen 2 and 3, and considering how close they got with Zen 3 to to that milestone, and to think of the performance increase when combined with DDR5.
DDR5 is what made me upgrade my current PC instead of building a new one, and it will be the reason for my next upgrade, just waiting for proper kits to come out.
Wondering if these companies are actually working on new kits, or it's a show and they're just timing gradual releases of the stuff they've been working on since JEDEC published the proposed specs at like 2017. The longer they milk consumers with 4800MHz kits, the longer I'm staying with this pc lol


----------



## tcclaviger

domdtxdissar said:


> Maybe i will buy a 5800x3d to play around with after all...
> 
> *AMD Ryzen 7 5800X3D Zen3 CPU has finally been tested in games*
> 
> Too bad they only tested with 3200MT/s..
> Should have used dd4 @ 3800 for x3d and ddr5 @ 6800 for AL
> 
> *Bonus: The Witcher 3 – Intel Core i9-12900K DDR4-3600 CL14 data*
> To check if there was any scalability with this title in particular, we installed *4 DIMMs of DDR4-3600 CL14* kits in our system. _There was definitely an improvement over 3200C14_ so next step is benchmark *12900K DDR5-6200 C40*.
> View attachment 2555809


Bought one to fill the "I've achieved all my 5950x, 3900x, 2080ti and 3080ti goals" boredom. Totally impractical yes, 100%. Fun to play with new hardware, also yes.

Mine arrives tomorrow by 4pm. Will get some baseline with fast memory tests done and posted before Sunday, will shoot for 4000C14 or 3800C13 if FCLK doesn't want to cooperate.

Skatterbencher mentioned his does 2133/4266, with WHEAs, but... that's a lot of room to find a stable point over 1900.

C8E doesn't arrive for a bit so the OCd 5800x3d + fast memory results will be a while.



SaarN said:


> I mean, if I had water cooling I would have paid someone to do this process for me, it should be worth it in the case of direct die, both for performance and reliability. It won't surprised me if my stronger CCD has an extra 100-150MHz to spare if I had the option to take it close to room temp.
> Sadly, I got a SFF case that had zero airflow and I had to spend $200 on extras from Noctua just to get slightly better than average cooling performance, meh.
> Now when I'm thinking about Ryzen 7000 being right around the corner, this thought would have made sense 2 years ago, because I'm pretty sure it will have no issues boosting to 5GHz all core considering the jump between Zen 2 and 3, and considering how close they got with Zen 3 to to that milestone, and to think of the performance increase when combined with DDR5.
> DDR5 is what made me upgrade my current PC instead of building a new one, and it will be the reason for my next upgrade, just waiting for proper kits to come out.
> Wondering if these companies are actually working on new kits, or it's a show and they're just timing gradual releases of the stuff they've been working on since JEDEC published the proposed specs at like 2017. The longer they milk consumers with 4800MHz kits, the longer I'm staying with this pc lol


There is definitely more headroom when kept cold, which is why I use a chiller. It's not just PB2 pushing higher up the volt/freq table, the chip becomes more stable below about 40c die temp when loaded for 1t boosting and I can push clock/voltage pairs that become unstable under normal ambient loop temps.

I often forget to precool the loop, which results in a blue screen the first time the chip boosts a 1t load with warm water (80f-ish), as soon as water hits 60f it behaves as desired.

Benchmark score settings will bootloop into windows repair screen over 40f water temp, but are rock stable at 35f water temp. It's a fine line. At near freezing, it boosts to, and holds, 5250mhz effective clock, the max my current board will allow.

As an example. GB5 1thread at BM settings, 1870. Daily settings, ~1830. Ambient loop temps ~1770. All with a change of only MHZ override increasing the headroom to use the temp advantage, but the same CO values.


----------



## Veii

tcclaviger said:


> Bought one to fill the "I've achieved all my 5950x, 3900x, 2080ti and 3080ti goals" boredom. Totally impractical yes, 100%. Fun to play with new hardware, also yes.
> 
> Mine arrives tomorrow by 4pm. Will get some baseline with fast memory tests done and posted before Sunday, will shoot for 4000C14 or 3800C13 if FCLK doesn't want to cooperate.


Still looking for one , it's early

ZenX3D , has the same WHEA issues as normal samples. AMD did not learn bother with it








^ it's not my chip, thing is 1.3v capped

But to bring a bit positive news
I promised unlock (to some extend, don't have fab tools), and well method 3 out of 4 worked on my chip so will on all Vermeer
Can override anything even non bios listed within windows - this includes AMD CBS menu, Overclocking Menu, PBS menu
Can do memOC from windows, without rebooting into the bios too















Only unfortunate part is for anything beyond +200 fMAX to function, i need to change bios "allowed limits" (value can not exceed predefined maximum limit)
And tool is kinda under NDA still ~ to some extend, soo publication is complicated




 love his intro 
I also still have old microcode's if it's related to them [Übersicht] - Ultimative AM4 UEFI/BIOS/AGESA Übersicht
We still don't know what they erased back then,if USB patch was only integrated into PSP-FW or it was something else big

Anywho, fun times await~
Only issue, substrate/interposer is very dense. Cores heat up a lot
Cache is cold, but the stack of interposter (cores) is an issue, soo heat transfer can not happen well.
@Bloax maybe on-die cooling, might have to come back , and silicon sanding


----------



## Audioboxer

Crap like this makes me think I should have ripped Windows defender out of my Windows installation lol...

When Corsair is beating you, you know you are bloated.


----------



## KedarWolf

Audioboxer said:


> View attachment 2556307
> 
> 
> Crap like this makes me think I should have ripped Windows defender out of my Windows installation lol...
> 
> When Corsair is beating you, you know you are bloated.


What program is that that is showing your start-up processes etc.?


----------



## Bloax

SaarN said:


> Wondering if these companies are actually working on new kits, or it's a show and they're just timing gradual releases of the stuff they've been working on since JEDEC published the proposed specs at like 2017. The longer they milk consumers with 4800MHz kits, the longer I'm staying with this pc lol


All I can tell you is that teasers of DDR5-12800 running have been circulating several months prior to the release of ADL, and *nothing* available comes even close to running that, even on LN2. 🤡

Of course - those were likely experimental EUV-manufactured DDR5 ICs, prior to the machinery to them being mass-manufacturable arrived.
But that doesn't necessarily mean that it's "just around the corner" either! 💪🤡🥧

Once EUV DDR5 chips arrive and bring with them +50% up to DDR5-9600, and the price for a kit with them isn't the price of a high-end CPU, then it'll be a good time to jump onto DDR5.



> But to bring a bit positive news
> I promised unlock (to some extend, don't have fab tools), and well method 3 out of 4 worked on my chip so will on all Vermeer
> Can override anything even non bios listed within windows - this includes AMD CBS menu, Overclocking Menu, PBS menu
> Can do memOC from windows, without rebooting into the bios too


Now to see such things _standard_ on AM5 instead of SUBER SEEKRIT 🤡 🤡 🤡 🤡 🤡


----------



## Audioboxer

KedarWolf said:


> What program is that that is showing your start-up processes etc.?


Glary Utilities. Not really a fan of any of these kind of apps, but this one is alright!


----------



## KedarWolf

New Window 10 Bench ISO Link, much improved with new instructions.






Win10BenchISO.zip







drive.google.com


----------



## 97pedro

KedarWolf said:


> New Window 10 Bench ISO Link, much improved with new instructions.
> 
> 
> 
> 
> 
> 
> Win10BenchISO.zip
> 
> 
> 
> 
> 
> 
> 
> drive.google.com


Sorry for the noob question, is this OS made specifically for benchmarking?


----------



## KedarWolf

97pedro said:


> Sorry for the noob question, is this OS made specifically for benchmarking?


Yes, it has no printing, no audio, absolute minimum services to run windows after running the cmd's, completely stripped of anything unnecessary for benching, but the internet connection works for downloading drivers etc. you need to install..


----------



## Blackfyre

KedarWolf said:


> Yes, it has no printing, no audio, absolute minimum services to run windows after running the cmd's, completely stripped of anything unnecessary for benching, but the internet connection works for downloading drivers etc. you need to install..


What is the point, as it becomes an unrealistic benchmarking environment. The benchmarks achieved on it cannot be compared with anyone else using a non-stripped down OS.

You can also just run *MSCONFIG* and then switch to Diagnostic Startup for more consistent results.


----------



## gameinn

One thing I have always wondered. What's up with the L3 Cache latency in Aida64? From what I have seen a standard L3 latency at an 1800 FCLK is ~10.5 ns

I would think that the higher you push FCLK (e.g. 1900) that the L3 latency should also marginally decrease to say 10.2 ns or so. Maybe even sub 10? Every screenshot I see here of 1900 FCLK has L3 latency worse than 1800, sometimes even as high as 12ns: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

Now I get that the logic might be wrong and that FCLK speed has no bearing on how fast the L3 cache is but why is 1900 almost always showing slower results than 1800?


----------



## SaarN

gameinn said:


> One thing I have always wondered. What's up with the L3 Cache latency in Aida64? From what I have seen a standard L3 latency at an 1800 FCLK is ~10.5 ns
> 
> I would think that the higher you push FCLK (e.g. 1900) that the L3 latency should also marginally decrease to say 10.2 ns or so. Maybe even sub 10? Every screenshot I see here of 1900 FCLK has L3 latency worse than 1800, sometimes even as high as 12ns: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> Now I get that the logic might be wrong and that FCLK speed has no bearing on how fast the L3 cache is but why is 1900 almost always showing slower results than 1800?


Aida's reading aren't that consistent, I usually get 10.3-2, but seeing 10.5 is also common, and if something popped in the background mid way? 11ns..
Too easy to temper with these results for me to go down that rabbit hole. 1ns is a pretty significant delta for l3 latency on one hand, but that test is quite sensitive so I don't rely too much on the results. 11.x+ is a concern. 10.3, 10.5, are indistinguishable to me


----------



## Veii

gameinn said:


> One thing I have always wondered. What's up with the L3 Cache latency in Aida64? From what I have seen a standard L3 latency at an 1800 FCLK is ~10.5 ns


L3 Cache speed on AMD is equal to the Core Frequency
Example here








And here:









It's not Aida's fault for the environment it is in
10.4ns relate to a boost of 4.85 Ghz
10.6ns to 4.75Ghz
10.9ns to 4.65Ghz
(which is funny, as it shows that below 4.7ish Ghz fabric was bottlenecked by frequency ~ higher frequency was not the bottleneck but interconnect speed and/or access latency)
5.05Ghz are then 10ns or 9.9 ~ although mostly seen 9.8ns (which is again odd, as it should be 10ns)

Windows 11 messes with Zen, to this date still
Thread Scheduler is different and it enforces odd powerstates that do not belong to Ryzen
In general is Ryzen fast, even better with Win11, but Aida still shows an active issue on & with, it


gameinn said:


> Now I get that the logic might be wrong and that FCLK speed has no bearing on how fast the L3 cache is but why is 1900 almost always showing slower results than 1800?


Powerbudget cut by SOC


Bloax said:


> ll I can tell you is that teasers of DDR5-12800 running have been circulating several months prior to the release of ADL, and *nothing* available comes even close to running that, even on LN2. 🤡
> 
> Of course - those were likely experimental EUV-manufactured DDR5 ICs, prior to the machinery to them being mass-manufacturable arrived.
> But that doesn't necessarily mean that it's "just around the corner" either! 💪🤡🥧
> 
> Once EUV DDR5 chips arrive and bring with them +50% up to DDR5-9600, and the price for a kit with them isn't the price of a high-end CPU, then it'll be a good time to jump onto DDR5.
> 
> Now to see such things _standard_ on AM5 instead of SUBER SEEKRIT 🤡 🤡 🤡 🤡 🤡


I always make the very simple math
DDR5 6000C30-30-30 == DDR4 3000C15-15-15
Usually it's exact and correct for the visual side of things
But you don't factor in in-dimm dual channel for that








While most of the things are identical and doubled
The real benefits are just "tight" integration and greater control on signal integrity

Math is different (doubles) but in the core theory not that much different to DDR4 or DDR3-to-4 transition
Burst length is 16 instead of 8
(soo as 1tCK = 2 BL, it's 8tCK usable vs 4tCK for transferring data) ~ but that should still end up equal as it's IN-DIMM Dual channel for both sides and not between dimms








tRCD is the main factor of delay, not tRAS
Soo RAS and CAS (are kinda forced) to be utilized correctly as Row Strobe and Column Strobe
Hitrate of Row Strobe is increased, and delay of tRCD (copy away data before destructive row read access) is minimized and directly torwards ICs focused)
This change with remain old architecture change from DDR3 to DDR4 as "added bankgroups" ~ to help slow IO and chain commands together (split in groups and send back on the 8th command == matching IO)
(DDR4 has a BL of 8, which only 4 clock commands can be send to ~ on the rising edge, or 2tCK if read and write is split into burst chops [4] )

All on all, they are not much different
But till i see 7200C32-32-32 kits ~ it will be 2023 
It takes time and neither many people nor many Vendors are aware of OC'd kits. Most if not all are just JEDEC batches


Bloax said:


> Now to see such things _standard_ on AM5 instead of SUBER SEEKRIT 🤡 🤡 🤡 🤡 🤡


I kinda get the reason why they do it.
Sample holds 90° on stock 120W operation , and is much harder to cool
Lifting substrate on the cores is like an insulator at this point, and maybe delidding + lapping will be needed
(cores hold 90° , L3 cache around 50° ~ cache doesn't get hot, that's misconception)


Spoiler: ~~~Rant Start~~~



Soo hence L3 runs equal to core freq - limiting interconnect frequency when they increased internal freq of things, is not that bad as an simple-minded business focused, idea.
"Protect customers from themself"
But it is indeed a bit embarrassing hard-fuse limiting 1.3v, when you have designed a power system that is very advanced on maintaining a power target
Then also know and are well aware in your position on the mobile market with low TDP units

Now all that, and sharing weakness of doubting your firmware engineer team that they can not hold their power target
Thinking the whole tech industry is stupid and doesn't know how to handle their CPUs, yet refusing to provide a guidance what target temps have to be and/or implementing a throttling system
(believing in your own work)
It's absolutely bothersome by AMD and shows that they internally don't even trust each other on their own design. A showcase of weakness.

Now ignoring,
that they hold zero trust to us, seeing how their samples work and restricting even VID undervolting (when their own sample throttles effective clock by 200-300mhz on stock)

It's like a stubborn child, who will take away the toy from their family, instead of letting (seems like) a mass of intelligent people, explore and play with their toy
AMD themselves confirmed it's an experimental unit and they want to "learn" from it - yet being stubborn and refusing accepting information.
"We have no experience with it" ~ so you all shall not get any either. . . .type of mentality.
And that really is embarrassing and disrespectful to us and their own firmware-engineering team. 

EDIT:
I just hope the Radeon Team doesn't equally do such "less inteligent" idea of increasing SocCLK on 6x50XT rebrand-launches (with newer samsung memory)
And then wonder "uh ow, our sample runs hot, i wonder why" ~ "it's fast tho, soo let us be stubborn again and restrict overclocking on our GPUs too"
I really hope, this fewer-dream decided last minute, will not happen again on any of their other ~ usually very well designed, hardware-products.
They can keep their fear to themselves. Enthusiasts work & OC scene's work is to push and support ! the industry. Not being seen as the useless people who are the reasons their drivers or hardware having a bad reputation
^ which are actual quotes by this Vendor (AMD) ~ @Bloax
"Apparently the OC scene is in fault for unstable GPU drivers and their bad reputation"  haha🙈

EDIT2:
I want to remind some Navi users what happens if you increase SOCCLK from 1000MHz to 1300MHz. (default is 1200)
It's an increase of near 12-15° for barely performance increase
Now imagine what happens when you increase SOCCLK from 500 to 1000MHz on the CPUs....
Of course new samples are/will be faster, but this is not the right way to do it. Creating a nuclear reactor just to beat the KS sample by IPC
^ that's one of many ways to increase IPC

Has the team imagined what these core heat increase changes even do to the IMC and signal integrity
They should be more than aware, and have history to rely back on why Threadripper never got Octa-channel or consumer 3950X never on quad channel
The team has to be far more than aware how fabric interleaving ~80% nearly-doubles powerdraw , for double the bandwidth // behaves when randomly pushing internal clocks that high without precautions

Maaybe, they indeed had another more conductive material in mind, and everything failed
Soo they had to use this isolating substrate , and last minute saw cores continuously move in the 80-90° range
But then , why would you launch such thing and not just delay it "once" at least.
Launching AM4 sample at the same time as AM5 sample isn't that bad either ~ as upgrade cost + DDR5 is too much for some.
Sad sad , but i think it might really be such an event ~ and why they did such questionable decision.
Fact still stays that they indeed are stubborn, not even slightly any doubt about it. Selfish rather refusing us to play with their toy, yet AMD expecting to learn "anything" from it
~~~~~~Rant Over~~~~~~~


🙈


----------



## Audioboxer

After seeing how DDR4 progressed, there is no doubt I'm holding onto this 5950x and DDR4 kit until at least the beginning of 2024.

This new gen is exciting, but it seems like it needs a bit of time to bake in the oven.


----------



## PJVol

gameinn said:


> FCLK speed has no bearing on how fast the L3 cache is


Of course it hasn't since L3 is logically (and physically) is part of the CCD. Any latency regression observed results from EDC-based throttling function. Try to vary EDC limit from default to the maximum available while running AIDA "cache tests" and see how it affects the L3 latency. EDC metric is common for the whole ССD - not just for cores/L1/L2/SC - including L3 (not shown in HWInfo).

With regard to running fclk over 1900, throttling is either due to stress on a CCD part of the data fabric or intentionally throttled by the firmware.


----------



## TimeDrapery

Anybody gonna throw the latest Ryzen Master release on their system and see how it runs through CO? Adjustments in real-time...? "'Auto' Curve Optimizer"...?

"*Introducing both Auto-Curve optimizer and Manual Curve optimizer for AMD Ryzen™ 5000 processors and AMD Ryzen™ PRO 5000WX processors*"


----------



## Blackfyre

TimeDrapery said:


> Anybody gonna throw the latest Ryzen Master release on their system and see how it runs through CO? Adjustments in real-time...? "'Auto' Curve Optimizer"...?
> 
> "*Introducing both Auto-Curve optimizer and Manual Curve optimizer for AMD Ryzen™ 5000 processors and AMD Ryzen™ PRO 5000WX processors*"


Interesting, no I have not tested it at all. I spent a long time fine tuning, so I doubt I will benefit from it.

But I will backup my BIOS settings and try it tomorrow I guess.

*Question: Can I just run it with my overclock already done? Or do I need to reset BIOS to default and then let it run?*

Because I am already on strong negative offsets.


----------



## ArchStanton

@KedarWolf I finally had time to test your suggested settings. So far so good. I plan to run OCCT overnight now that TM5 has finished. Assuming that passes, I will see if I can reduce vSOC (1.2v set) or vDIMM (1.5v set) without a loss of stability. Incidentally, would you clarify:


KedarWolf said:


> VDDP is normally run at .900v.* VTTs I run at .730v* for RAM at 1.5v. As I said, VTT too high can cause instability.
> 
> Edit: *VTTDDR at .730v too*.


"too" implies in addition to some other VTT "value" in the BIOS. I believe you are predominantly an MSI man. I'm over here in "ASUSland" with Blackfyre.


----------



## KedarWolf

ArchStanton said:


> @KedarWolf I finally had time to test your suggested settings. So far so good. I plan to run OCCT overnight now that TM5 has finished. Assuming that passes, I will see if I can reduce vSOC (1.2v set) or vDIMM (1.5v set) without a loss of stability. Incidentally, would you clarify:
> 
> "too" implies in addition to some other VTT "value" in the BIOS. I believe you are predominantly an MSI man. I'm over here in "ASUSland" with Blackfyre.
> View attachment 2556714


I reduced VSOC etc.


----------



## ArchStanton

@KedarWolf thank you for the follow up. Rerunning TM5 at reduced vSOC/vDDG. Will check vDIMM separately later.

If I might ask again though, what other "VTT" in addition to "VTTDDR" do you tend to manually set at 730mv?


----------



## KedarWolf

ArchStanton said:


> @KedarWolf thank you for the follow up. Rerunning TM5 at reduced vSOC/vDDG. Will check vDIMM separately later.
> 
> If I might ask again though, what other "VTT" in addition to "VTTDDR" do you tend to manually set at 730mv?


EVERY BIOS setting that affects memory.




Spoiler: Open Spoiler To See Memory Related BIOS Screenshots






















*SOC Loadline Calibration here and Switching Frequency. Some people need to do 800 though or their PC won't boot.*



















Spread Spectrum, SWM Mode, Performance Regulator, VRM C-State Control.


----------



## ArchStanton

@KedarWolf Thank you .


----------



## Audioboxer

TimeDrapery said:


> Anybody gonna throw the latest Ryzen Master release on their system and see how it runs through CO? Adjustments in real-time...? "'Auto' Curve Optimizer"...?
> 
> "*Introducing both Auto-Curve optimizer and Manual Curve optimizer for AMD Ryzen™ 5000 processors and AMD Ryzen™ PRO 5000WX processors*"


I'm more shocked AMD actually updated Ryzen Master.

Feedback so far is the auto curve is pretty terrible, load up Corecycler afterwards and see cores quickly fail. Still, I'll have a look at it.


----------



## ArchStanton

Audioboxer said:


> Feedback so far is the auto curve is pretty terrible


The screenshot I saw (somewhere here on OCN) had the "auto curve" failing every core almost immediately when being tested against 720-720.

Edit: Here we are OFFICIAL 5900X and 5950X two chiplet Zen 3 CPUs...


----------



## PJVol

TimeDrapery said:


> Anybody gonna throw the latest Ryzen Master release on their system and see how it runs through CO?


I did it on my 5600X system. Tuning CO by RM took ~ 1hr.
I found the testing methodology itself interesting.
During the test I occasionally checked out for CO values it was sorting through.
So first it went through each core, alternating ST and MT load, in which "counts" for all cores except currently tested were zeroed.
This was the longest part during which the PC was rebooted 5 or 6 times.


Spoiler: Testing the last core














Close to the end, it went through all cores once more, this time with a short periods of ST workload, and here it is:








On clicking "CO profile" it will ask you to choose an "offset" value, that will be added to each count and applied after restart. I chose two values: 13, that is almost reproduce my 24/7 curve (with one important exception) and 8, i.e. first curve down 5 counts.

PS: There's a couple of things worth mentioning:
1. Despite all testing were done with a +200 boost, on reboot it was reset to 0.
2. It still not clear, what user should base on when choosing that "offset". It seems a bit odd, as this "offset" is what is supposed to be calculated by the same procedure based on PBO settings (boost, limits, scalar) or whatever.
3. At least one positive thing I've learned is that the bad Core 5 (C6 in RM) of my 5600X got even worse over time (meaning just degraded), though I guessed it is, tbf, simply looking at the its Fmax regression in a same conditions compared to other cores and to it's Fmax when I bought it. As a result it needs CO set 3 counts higher than the second worst C3.


----------



## KedarWolf

ArchStanton said:


> @KedarWolf Thank you .


Let's see your AIDA64?

I'm curious to see what your ASUS board does.

Here's my MSI X570S Unify-X Max with the unlocked BIOS. 🐺


----------



## Blackfyre

KedarWolf said:


> EVERY BIOS setting that affects memory.
> 
> 
> 
> 
> Spoiler: Open Spoiler To See Memory Related BIOS Screenshots
> 
> 
> 
> 
> View attachment 2556720
> 
> 
> View attachment 2556721
> 
> 
> *SOC Loadline Calibration here and Switching Frequency. Some people need to do 800 though or their PC won't boot.*
> 
> View attachment 2556722
> 
> 
> View attachment 2556723
> 
> 
> Spread Spectrum, SWM Mode, Performance Regulator, VRM C-State Control.
> 
> View attachment 2556724
> 
> 
> View attachment 2556725
> 
> 
> View attachment 2556726
> 
> 
> View attachment 2556727
> 
> 
> View attachment 2556728
> 
> 
> View attachment 2556729
> 
> 
> View attachment 2556730
> 
> 
> View attachment 2556732
> 
> 
> View attachment 2556733
> 
> 
> View attachment 2556734


Curious question. What are the benefits from changing these settings?

I just changed them from AUTO to what you have in those screenshots on my ASUS X570 HERO.

No difference in performance from what I have tested.


----------



## KedarWolf

Blackfyre said:


> Curious question. What are the benefits from changing these settings?
> 
> I just changed them from AUTO to what you have in those screenshots on my ASUS X570 HERO.
> 
> No difference in performance from what I have tested.


Did you run benches like AIDA64, y-cruncher and DRAM Calculator?

And does your BIOS have access to all those settings and the PBS and CBS menus?

And not all those settings will affect performance. Some are for stability so you can run lower timings etc. which in turn WILL help performance.


----------



## Blackfyre

KedarWolf said:


> Did you run benches like AIDA64, y-cruncher and DRAM Calculator?
> 
> And does your BIOS have access to all those settings and the PBS and CBS menus?
> 
> And not all those settings will affect performance. Some are for stability so you can run lower timings etc. which in turn WILL help performance.


Yep, all settings were available. I copied the same ones you have.

AIDA 64 is not really reliable. Since Latency can be 54 one test, 56 the next, 58 after and back to 55 after that.

But I am testing lower secondary timings now. Will run 50 cycles of 1usmus TM5 overnight to test stability.


----------



## KedarWolf

Blackfyre said:


> Yep, all settings were available. I copied the same ones you have.
> 
> AIDA 64 is not really reliable. Since Latency can be 54 one test, 56 the next, 58 after and back to 55 after that.
> 
> But I am testing lower secondary timings now. Will run 50 cycles of 1usmus TM5 overnight to test stability.


After AIDA64 runs, you can click on each individual box that runs, which will update, and get a base of if your latency etc. is lower. I find it more consistent to run each one, I'll get only a .1 or .2 difference in latency only if I click on the top latency box for example.


----------



## KedarWolf

Deleted


----------



## KedarWolf

KedarWolf said:


> EVERY BIOS setting that affects memory.
> 
> 
> 
> 
> Spoiler: Open Spoiler To See Memory Related BIOS Screenshots
> 
> 
> 
> 
> View attachment 2556720
> 
> 
> View attachment 2556721
> 
> 
> *SOC Loadline Calibration here and Switching Frequency. Some people need to do 800 though or their PC won't boot.*
> 
> View attachment 2556722
> 
> 
> View attachment 2556723
> 
> 
> Spread Spectrum, SWM Mode, Performance Regulator, VRM C-State Control.
> 
> View attachment 2556724
> 
> 
> View attachment 2556725
> 
> 
> View attachment 2556726
> 
> 
> View attachment 2556727
> 
> 
> View attachment 2556728
> 
> 
> View attachment 2556729
> 
> 
> View attachment 2556730
> 
> 
> View attachment 2556732
> 
> 
> View attachment 2556733
> 
> 
> View attachment 2556734


Those settings gets me the below TM5 stable, with well binned RAM.


----------



## Taraquin

KedarWolf said:


> Those settings gets me the below TM5 stable, with well binned RAM.
> 
> View attachment 2556827


Rtp 5(rtp x 2 = wr), except for that looks awesome. Phyl 28/28?


----------



## KedarWolf

Taraquin said:


> Rtp 5(rtp x 2 = wr), except for that looks awesome. Phyl 28/28?


I'm pretty sure last time I checked RTP 5 gave me errors but checking again.

Yeah, TRP 5 gives me an error early in TM5.


----------



## ArchStanton

KedarWolf said:


> Let's see your AIDA64?


Been a full day in the yard, will try to get you some additional detail after supper.


----------



## matthew87

Quick one, how's Ryzen 5000 series these days with 4000mhz RAM and running IF at 2000mhz out of box? 

Still pot luck to get IF running 1:1 at 2000mhz?


----------



## KedarWolf

ArchStanton said:


> Been a full day in the yard, will try to get you some additional detail after supper.
> View attachment 2556869


Can I see a Zen Timings screenshot? You're getting excellent results.


----------



## ArchStanton

@KedarWolf Here is a little more detail. Not quite as cold in my "laboratory" as I would like, and Aida suffers just a little with elevated temperatures. Thank you for the suggested settings. I haven't been able to finish stability testing of 2nd config, but I should be good by tomorrow morning.


----------



## KedarWolf

ArchStanton said:


> @KedarWolf Here is a little more detail. Not quite as cold in my "laboratory" as I would like, and Aida suffers just a little with elevated temperatures. Thank you for the suggested settings. I haven't been able to finish stability testing of 2nd config, but I should be good by tomorrow morning.
> View attachment 2556872


Try this.


----------



## ArchStanton

@KedarWolf


----------



## KedarWolf

ArchStanton said:


> @KedarWolf
> View attachment 2556880


Try this.


----------



## KedarWolf

ArchStanton said:


> @KedarWolf
> View attachment 2556880


Try this with 1.56v RAM, .780v VTTs.

Then run OCCT and see if you get WHEA errors before TM5.


----------



## Anhphe93

I can't get FCLK 2000. No matter what kind of voltage change I can't get out of WHEA. It just wasn't there in 1967.


----------



## ArchStanton

KedarWolf said:


> Try this.


From Post # 18,597


----------



## ArchStanton

KedarWolf said:


> Try this with 1.56v RAM, .780v VTTs.


Forgive me, but I'm going to chicken out. I have corrupted my OS twice by booting at fclk 2000, and I'm just not feelin' that spicy at the moment 🤣. Though I have bookmarked post # 18,598, and I will rise to the challenge at some point. Thank you again for all your assistance. I hope it wasn't too much like a "chore" for you.


----------



## KedarWolf

ArchStanton said:


> Forgive me, but I'm going to chicken out. I have corrupted my OS twice by booting at fclk 2000, and I'm just not feelin' that spicy at the moment 🤣. Though I have bookmarked post # 18,598, and I will rise to the challenge at some point. Thank you again for all your assistance. I hope it wasn't too much like a "chore" for you.


Pro Tip: Get Macrium Reflect Free and make a Boot USB with it. The USB needs to be formatted MBR FAT32. Rufus will do it for you.

Boot from the USB. You can boot from it UEFI. Backup your entire Windows drive to a secondary M.2 or SSD drive. Have a Windows image you can restore.

It takes me less than two minutes to fully restore my Windows, boot partitions and all, after a BSOD or O/S freeze. I have the Macrium image on my second Gen 4 M.2 drive.

Edit: My restore image is less than 70GB though. If you have a ton of games installed, it'll take longer than two minutes to restore. 

I think my All Games image takes about ten minutes, but much better than a reinstall of Windows.


----------



## ArchStanton

KedarWolf said:


> Pro Tip


Added to the "to do" list. Again, thank you.


----------



## KedarWolf

ArchStanton said:


> Added to the "to do" list. Again, thank you.


I added a few things to the post, you might want to read it again.


----------



## Taraquin

matthew87 said:


> Quick one, how's Ryzen 5000 series these days with 4000mhz RAM and running IF at 2000mhz out of box?
> 
> Still pot luck to get IF running 1:1 at 2000mhz?


1 ccd cpu + 2 dimm motherboard seems most likely. All I know who can do it WHEA19 free including myself has this combo.


----------



## Frosted racquet

Taraquin said:


> 1 ccd cpu + 2 dimm motherboard seems most likely. All I know who can do it WHEA19 free including myself has this combo.


And then there's me that can't even do 1900 with that combo


----------



## Audioboxer

ArchStanton said:


> Been a full day in the yard, will try to get you some additional detail after supper.
> View attachment 2556869


Change your SCLs to 4 instead of 2 and you should get that read up a few hundred points. Latency likely won't change or it'll be 0.1.










598xx is the highest I've been able to achieve at 3800.

While some people might benefit from SCLs at 2 more often than not at 3800 recommending people use 4 results in slightly better performance. Especially on DR.


----------



## Taraquin

KedarWolf said:


> I'm pretty sure last time I checked RTP 5 gave me errors but checking again.
> 
> Yeah, TRP 5 gives me an error early in TM5.


Try WR 12, see if it performs better, may do since your timings are better synced.


----------



## Taraquin

Frosted racquet said:


> And then there's me that can't even do 1900 with that combo


Won't boot? Or WHEA19? Some seems to need high VDDP and/or VDD18 for it to work.


----------



## Frosted racquet

WHEA19. Admittedly I haven't tweaked VDDP VDD18. Do those voltages affect core stability? I have pretty much finished core stability testing with IF at 1800, would hate to have to redo everything if I went for 3800/1900...


----------



## Taraquin

Frosted racquet said:


> WHEA19. Admittedly I haven't tweaked VDDP VDD18. Do those voltages affect core stability? I have pretty much finished core stability testing with IF at 1800, would hate to have to redo everything if I went for 3800/1900...


Try higher VDDP and/or VDD18, it might make WHEA19 go away. Save your current bios, if you are satisfied with what you have, keep it


----------



## domdtxdissar

KedarWolf said:


> Pro Tip: Get Macrium Reflect Free and make a Boot USB with it. The USB needs to be formatted MBR FAT32. Rufus will do it for you.
> 
> Boot from the USB. You can boot from it UEFI. Backup your entire Windows drive to a secondary M.2 or SSD drive. Have a Windows image you can restore.
> 
> It takes me less than two minutes to fully restore my Windows, boot partitions and all, after a BSOD or O/S freeze. I have the Macrium image on my second Gen 4 M.2 drive.
> 
> Edit: My restore image is less than 70GB though. If you have a ton of games installed, it'll take longer than two minutes to restore.
> 
> I think my All Games image takes about ten minutes, but much better than a reinstall of Windows.


I have ordered a usb SSD drive which i will try your and other bench OS on in the future 

In the meantime, these are the numbers i'm getting with my everyday fully updated *windows11 22000.613* Spectre install
(temps alittle on the warmside)


----------



## MehlstaubtheCat

Taraquin said:


> Save your current bios, if you are satisfied with what you have, keep it


On MSI board often the bios save is "bugged", it will help if he do some screenshots too, just for safety


----------



## Frosted racquet

Taraquin said:


> Try higher VDDP and/or VDD18, it might make WHEA19 go away. Save your current bios, if you are satisfied with what you have, keep it


Thanks, will try. Any suggestions for VDDP and/or VDD18 voltage ranges at 1900 IF? The only thing I kinda remember from previous discussions is that both voltages have sweetspots ie. higher doesn't mean better/more stable.


MehlstaubtheCat said:


> On MSI board often the bios save is "bugged", it will help if he do some screenshots too, just for safety


Always do, even if it worked properly I'd still take screenshots.


----------



## Taraquin

Frosted racquet said:


> Thanks, will try. Any suggestions for VDDP and/or VDD18 voltage ranges at 1900 IF? The only thing I kinda remember from previous discussions is that both voltages have sweetspots ie. higher doesn't mean better/more stable.
> 
> Always do, even if it worked properly I'd still take screenshots.


Vddp range 900-1000. Vdd18 range: 1800-1950. May need over this, but you can try this first. Soc should be 1.1-1.15v, iod 1.00-1.105v.


----------



## Blackfyre

KedarWolf said:


> After AIDA64 runs, you can click on each individual box that runs, which will update, and get a base of if your latency etc. is lower


*You're telling me, I have been using this program for over a decade without knowing this shortcut...*


----------



## 97pedro

@Blackfyre Don't worry, been using it since Everest and also just discovered that some weeks ago lel.

Any recomendations of what timing I should increase when my dimms are really temperature limited?


----------



## Arihante

Hi, guys. I have a question
I'd really appreciate it if you could give me an answer 

It works well up to 3800 cl16
but WHEA-19 log appears about once a day.
So I'm staying at 3733 cl16. 
3733 cl15 was impossible to stabilize 
and probably reached its limit.
(Bad b-die?)

Anyway, 3733 cl16 is very stable
(1.35v, tm5 anta777 2000% 50 cycles passed)

But I have a question about the AIDA64 benchmark
L3 cache score changes quite a bit every time.
Memory latency is also high at first, but gradually decreases.
And then it becomes somewhat stable
(L3 cache continues to change from 6xx ~ 5xx, latency 10.9-11.8)

Of course, all background processes are turned off
ppt 165 tdc 120 edc 175 and call core-30
and cpu side is perfectly stable

In this case, is the voltage or any value across the corners causing the variation?
Or is everyone going through this?

Thank you.


----------



## PJVol

Arihante said:


> L3 cache score changes quite a bit every time.
> Memory latency is also high at first, but gradually decreases.


It takes up to 5 min for the background processes and services to settle down (on my not bloated much W10 with the defender and all other security s**t permanently shut down)
Better wait ~10min until testing anything mem/L3 sensitive in aida.


----------



## Veii

Arihante said:


> In this case, is the voltage or any value across the corners causing the variation?
> Or is everyone going through this?


Like PJVol mentioned,
First score you always trow away
System needs some load, before settling down to it's idle states

Later the test is accurate, but
If you repeat two one-after-another, thermal issues become the factor
Every Aida field, tests 1,2,3,4,5,6 and allcores ~ in order from bottom up
It will go through all of them and with dual CCDs do such twice

Soo heat is a problem and will define how high/low the result is
Especially for L3 cache, and L3 latency.
If it frequency throttles mid test, L3 freq will be lower and latency higher (not "only" bloat related)


----------



## mtrai

Alrighty I am finally coming now that I have read this thread from start to finished. Most probably do not remember me but anyhow, had some health issues and kind of fell out of overclocking and gaming for the last couple of years. I have yes I know 2 different kits here both are b-die. These timing have passed every test I could throw out them over the last month. 

My question is am I overlooking any timing? Anything else left? I can boot into windows at 2000/4000 not stable and of course tons of whea. I have not recently tried to boot again at 3800 nor am I sure it is really worth it based on my Memory read/write/copy speeds. 

My temps are fine on the ram so that is a non issue.

View attachment 2557045


----------



## matthew87

Taraquin said:


> 1 ccd cpu + 2 dimm motherboard seems most likely. All I know who can do it WHEA19 free including myself has this combo.


Thanks, appreciate the response. 

I'm looking at upgrading the RAM for my Ryzen 5800x, currently got 4 x 8GB single rank Samsung B die 3200mhz C14. 

What's your thoughts on say buying 4 sticks of 4000mhz C16 and running them at 3800mhz/3900mhz with tighter timings if my CPU can't do 2000mhz IF stable?

I'm actually not sure what's going to place more stress on the IMC of the CPU, 4 sticks of single rank or two sticks of dual rank?


----------



## Anhphe93

domdtxdissar said:


> I have ordered a usb SSD drive which i will try your and other bench OS on in the future
> 
> In the meantime, these are the numbers i'm getting with my everyday fully updated *windows11 22000.613* Spectre install
> (temps alittle on the warmside)
> View attachment 2556942


Where can I find the PBO2 tuner program?


----------



## Veii

@PJVol & @XPEHOPE3 help 
I've requested from Irusanov, too


----------



## PJVol

@Veii
Hmm, you're finally got hold of Cezanne sample? )


----------



## Taraquin

matthew87 said:


> Thanks, appreciate the response.
> 
> I'm looking at upgrading the RAM for my Ryzen 5800x, currently got 4 x 8GB single rank Samsung B die 3200mhz C14.
> 
> What's your thoughts on say buying 4 sticks of 4000mhz C16 and running them at 3800mhz/3900mhz with tighter timings if my CPU can't do 2000mhz IF stable?
> 
> I'm actually not sure what's going to place more stress on the IMC of the CPU, 4 sticks of single rank or two sticks of dual rank?


4 sticks is generally worse, 3800/1900 will most likely work fine, maybe 3733 or 3666 os max if unlucky, I have not heard of any doing 4 sticks above 1900 WHEA19 free.


----------



## Veii

PJVol said:


> @Veii
> Hmm, you're finally got hold of Cezanne sample? )


For a mini Capture/Encode Box ~ 30 days mine
But i max CO out @ only +100 FMAX, reaches 1.4v SVI2 / 1.45 Fab Limit
















Pretty balanced overall 
CBS is fully open, i'm happy~


----------



## PJVol

Veii said:


> Pretty balanced overall


Yep, +200 hardly can handle y-cruncher n32 or even Pi-bencmark, especially if EDC is went through the roof.
Mine is from -18 to -22 at 350A EDC.

Btw, if anyone interested, RSMU analogs for set/get core psm margins are 0x0A and 0x7C (kudos to RM dev. team)
And of course, PBO2 Tuner developer will be happy to finally provide support for the Cezanne (Soon...I hope) - although it's little too late but still funny anyway


----------



## SirPerfluous

still working on this one.
4x8sr

tm5 running tonight
be back tomorrow with more


----------



## Taraquin

Made a small Zen 3 ram overclocking guide than if it works out good can guide beginners to before asking basic questions here, please contribute Veii, Mannix ITA and others with more knownledge than me  A guide to ram overclocking on Zen 3


----------



## Taraquin

SirPerfluous said:


> still working on this one.
> 4x8sr
> 
> tm5 running tonight
> be back tomorrow with more
> 
> 
> View attachment 2557063
> 
> 
> View attachment 2557064


Is this WHEA19-free in event viewer?


----------



## domdtxdissar

__ https://twitter.com/i/web/status/1515253676893478913


----------



## elbramso

KedarWolf said:


> New Window 10 Bench ISO Link, much improved with new instructions.
> 
> 
> 
> 
> 
> 
> Win10BenchISO.zip
> 
> 
> 
> 
> 
> 
> 
> drive.google.com


Windows 11 Bench ISO when?? 🤣


----------



## Audioboxer

They told me watercooling my memory was pointless.... jokes on them, I'm going to watercool my NVMe drive as well 

That's my 60mm chonk rad to go in the rear of the case as well.

Time for... another drain  Thank goodness I just use distilled water.


----------



## The_King

My new Daily settings. Finally gave RCDWR 8 a go.


----------



## Blackfyre

The_King said:


> My new Daily settings. Finally gave RCDWR 8 a go.
> View attachment 2557143


For it to be daily, IMO you need to run at least 30 cycles. I often get errors after 18 cycles and sometimes after 25 cycles when tightening secondary timings below what I previously thought was stable.

Copy and paste 1usmus_v3, edit the copy with notepad, and change the 3 cycles to 40 cycles. Save and exit, rename the file 40 cycles. Run TM5 as admin, click load config & exit, then choose the 40 cycle one you made. Then run TM5 as admin again to start testing with 40 cycles as the default.


----------



## The_King

Blackfyre said:


> For it to be daily, IMO you need to run at least 30 cycles. I often get errors after 18 cycles and sometimes after 25 cycles when tightening secondary timings below what I previously thought was stable.
> 
> Copy and paste 1usmus_v3, edit the copy with notepad, and change the 3 cycles to 40 cycles. Save and exit, rename the file 40 cycles. Run TM5 as admin, click load config & exit, then choose the 40 cycle one you made. Then run TM5 as admin again to start testing with 40 cycles as the default.


More often than not errors on longer runs are due to heat @ 1.5V+. @ 1.45V thats not likely I will run the anta777 extreme test later on to test I only use 1usmus for quick tests.


----------



## FriendlySeacow

Hi everyone, I've been messing with DRAM overclocking (through TRFC) and wondered if anyone had any hints before I turn to the SCL's, tRTP, etc.

My 5800x has the terrible 1900 FCLK hole that won't boot; it does boot up to 2100 but with WHEAs in OCCT. I've tried PLL up to 1.85 and VDDP up to 1.15 and it seems to make the instability worse, so I think I've given up on any FCLK past 1866 unless ASUS releases another AGESA update or there's some magic fix I don't know about.

VDIMM is 1.5V and I don't know what my Mem VTT is. My DIMMs get to 46-48C at the end of 3 Anta777 cycles. Thanks for your help!


----------



## andremoreira6215

FriendlySeacow said:


> Hi everyone, I've been messing with DRAM overclocking (through TRFC) and wondered if anyone had any hints before I turn to the SCL's, tRTP, etc.
> 
> My 5800x has the terrible 1900 FCLK hole that won't boot; it does boot up to 2100 but with WHEAs in OCCT. I've tried PLL up to 1.85 and VDDP up to 1.15 and it seems to make the instability worse, so I think I've given up on any FCLK past 1866 unless ASUS releases another AGESA update or there's some magic fix I don't know about.
> 
> VDIMM is 1.5V and I don't know what my Mem VTT is. My DIMMs get to 46-48C at the end of 3 Anta777 cycles. Thanks for your help!
> View attachment 2557172


Do you try with GDM enable?


----------



## FriendlySeacow

andremoreira6215 said:


> Do you try with GDM enable?


Yes GDM enabled makes no difference for WHEA at 1933 as far as I can tell.


----------



## SirPerfluous

Taraquin said:


> Is this WHEA19-free in event viewer?


yes


----------



## SirPerfluous

Gonna work on RFC, CWL and WRRD/RDWR for now

tm5 last night gave me this:


----------



## heptilion

KedarWolf said:


> Try this.
> 
> View attachment 2556883


hi, What vdim voltage did you use to make 1T command rate?


----------



## Taraquin

SirPerfluous said:


> yes


That is very impressive! This is the first time I have heard of 1933+ fclk running 4 sticks and no WHEA19  Good I\O-die, good motherboard or combo


----------



## Taraquin

SirPerfluous said:


> Gonna work on RFC, CWL and WRRD/RDWR for now
> 
> tm5 last night gave me this:


Suggestion, try 2T gdm off, easier to spot errors and often a bit faster than gdm. As for timings: RDRDSCL\WRWRSCL are more stable and about as fast on 4. RP can increase volt reqs quite a bit, I would consider trying 15-15-15 and 2t and see if that works  Try WR 12, RTP 6, they should be in a 2:1 relation. RFC should be able to run at 304, probably lower aswell, try lowering by 8 and 8.


----------



## ArchStanton

Audioboxer said:


> Change your SCLs to 4 instead of 2 and you should get that read up a few hundred points. Latency likely won't change or it'll be 0.1.


Just a follow up after implementing your suggestion. Making this change did increase "Read" by a few hundred points. However, it also decreased "Write" by an equal or greater amount. Short of citing performance on a specific "load", is there any "rule of thumb" reason to prioritize "Read" over "Write" or vice versa? Genuinely just curious .



KedarWolf said:


> Pro Tip: Get Macrium Reflect Free and make a Boot USB with it.


Mission accomplished . I was initially dismayed by the additional services/background processes that Macrium initiated, but I was pleased to discover that once the "boot thumb drive" and "recovery image" were created (on a fresh partition of a secondary drive), that I no longer needed Macrium installed. Thank you for making me aware of a very handy option. Perhaps I shall soon find myself in possession of sufficient testicular fortitude to return to the land of "Elevated fclk's".


----------



## KedarWolf

heptilion said:


> hi, What vdim voltage did you use to make 1T command rate?


I use 1.5v in BIOS, VTTs at .730v. But I've seen people having to use up to 1.54v.


----------



## MrHoof

KedarWolf said:


> I use 1.5v in BIOS, VTTs at .730v. But I've seen people having to use up to 1.54v.


1.55v here but my kit is 3600 14-15-15 so not the best.


----------



## The_King

Blackfyre said:


> *You're telling me, I have been using this program for over a decade without knowing this shortcut...*
> View attachment 2556948


Have you not seen people post Latency only timings like this before? You can actually run each box on its own.


----------



## Veii

SirPerfluous said:


> yes


Could you go on Zentimings options-debug, and please share the output 
Might still be a dual CCD unit


ArchStanton said:


> Just a follow up after implementing your suggestion. Making this change did increase "Read" by a few hundred points. However, it also decreased "Write" by an equal or greater amount. Short of citing performance on a specific "load", is there any "rule of thumb" reason to prioritize "Read" over "Write" or vice versa? Genuinely just curious .


Usually on 1CCD units caps at the bandwidth they can run, soo only shows package throttling
2 CCD have full bandwidth usable, but still can be an indicator of potential CPU based throttling ~ but also memory 
* on 1 CCD , little memory bandwidth changes don't show up, as they move in values much higher than I/O limits bandwidth
Read = Read (primaries)
Write = tertiraries
Copy = full loop & everything = efficiency of timings or generally higher utilizable average bandwidth
Memory always run in full bandwidth, just gets throttled by user timings and other refresh changes = loses bandwidth, also by I/O that cause it to lose maximum bandwidth


----------



## SaarN

Hey guys, I'm thinking about taking the heatsink off my Ripjaws kit, because they don't seem to be doing anything but block the airflow.
Got any aftermarket heatsinks to recommend by a chance? I don't want to leave them uncovered


----------



## Bloax

SaarN said:


> Hey guys, I'm thinking about taking the heatsink off my Ripjaws kit, because they don't seem to be doing anything but block the airflow.
> Got any aftermarket heatsinks to recommend by a chance? I don't want to leave them uncovered







for heatsinks idk, you can check if https://bartxstore.com/shop/custom-ram-copper-heatsinks-for-ddr5-ddr4/ becomes available at some point




> want me to see what the viper 4000 16-16-16 sticks do on AM4?
> 
> ...
> it POSTed with my dual-rank settings still running LUL
> seems to do 3800 1T GDM Off @ Nom/6 Wr/3 Park/6 & CAD 40-20-30-20 piss easy
> ...
> 
> rtt 6/3/6 works up to 4600 16-16-16 but it's not being very cooperative as far as Getting Stable goes
> probably a great kit for a ryzen 5500 (iGPU-less Cezanne)
> 
> ...
> ....
> 
> does 3800 14-14-14-28-42 ~1.50v 1T gdm off @ procodt 28.2 (1.8v ~1.9v) nom/6 wr/3 park/6 CAD 40-20-30-20 without problems @ RRD 4/4 WTR 4/8 and RDWR WRRD 9/2
> not sure about tWR 12 RTP 6 as it threw a single whole error #10 which could either be 1.8v +/- 0.01, 5/10 RTP/tWR, or one of the 20's on CADBus
> ..
> the memory controller wasn't too thrilled at the prospect of attempting 4200 14-14-14 1T LULZ


either way, it's a better viper 4400
with less "weirdness"

good kit

edit: based on me trying to run it on LGA1700, then error #10 was most likely related to not running tWR 10/RTP 5 and too high CPU 1.8v (down to 1.88v @ procODT 24 [lowest] instead of 1.91v)


----------



## SaarN

Bloax said:


> for heatsinks idk, you can check if https://bartxstore.com/shop/custom-ram-copper-heatsinks-for-ddr5-ddr4/ becomes available at some point
> 
> 
> 
> either way, it's a better viper 4400
> with less "weirdness"
> 
> good kit


He has a set for b die in stock. But is it worth it? The design doesn't look too "air cooling friendly". Not much surface area


----------



## Audioboxer

LOL, I somehow managed to kill my MP600 Pro trying to watercool it. Flat out dead.

Thankfully under warranty so straight to Corsair to do the whole "I just turned the PC on and it wasn't listed in the BIOS".

Probably the hardest thing in a PC to kill 🤣 Can you even short an NVMe? Nothing to do with water damage and I can't see any physical signs of a break or pressure crack. Taking the stock cooler off is simple.

That serves me right for trying to watercool an SSD. So, time to watercool the replacement!

Here was me worried about my EK 3080 FTW3 block given the comments online about it killing EVGA cards and I manage to break an SSD instead 🥳


----------



## ReyReverse

Asus mid range MOBO b550f, CLDO VDDP its so weird. it could go CLDO VDDP 1.0v CLDO CCD 9.5v CLDO IOD 1.05v if I leave it auto

I don't like this MOBO.
any idea to do better?
View attachment 2557417


----------



## Blameless

Audioboxer said:


> Probably the hardest thing in a PC to kill 🤣 Can you even short an NVMe?


M.2 PCBs tend to be thin and flexible, doesn't take a ton of warping to break the BGA connections on the NAND or controller either. It is also possible to short the power delivery components.


----------



## Melan

Veii said:


> If tPHYRDL or tPHYWRL missmatches between set dimms.
> A difference on tPHYRDL indicates that cLDO_VDDP from PHY was not enough (too low) to reach the furthest mem-slot and so does indicate throttling
> (a combination of too low cLDO_VDDP or too high procODT, or bad RTTs ~ but a clear sign that memory training just barely passed yet was autocorrected because of user error)
> 
> A ease of use fashion addition, as many people barely to never notice the 2nd slot B1 running lower IOL than the first A1 slot.
> Nobody checks & me neither at the start, as we didn't know - this being actually a thing.


This could've actually fixed some of my issues I had on boot with memory fastboot enabled. I had mismatched PHYRDL/WRL on my 4 DIMMs (RDL of 28 on A1/A2 vs 26 on B1/B2). Although nothing from the advice above fixed it, except switching from GDM to 2T which was very unstable until I set slightly different timings deviating from what anta777 has written before though.


----------



## TimeDrapery

Hmmmmm... I'm revisiting 4×8GB memory overclocking yet again and I'm puzzled

TM5 (with both @1usmus 1usmus_v3 and @anta777 Extreme1 configs) completes testing without errors, there's no overheating issues that present, and I've explored (what feels like) _many_ configurations of RTTs and Data Bus impedances/resistances as well as PHY/SoC voltages/VDIMM... Yet I'm not reaching anything beyond ~4500-5000% coverage in Karhu while OCCT Pro (set to stop on error) only makes it through roughly one minute of testing before finding errors (the longest this test ran for was approximately two minutes)

What am I missing here? Here's a buncha screens to help illustrate my setup


----------



## Bloax

🤡tCKE 9 ? 🤡


----------



## TimeDrapery

Bloax said:


> 🤡tCKE 9 ? 🤡


I'll give that a go right meow... What's odd (to me) is that setting a negative offset of 100mV on CPU VDDP has made it so that OCCT Pro now tests for _at least_ (test is still running as I'm drafting this post) three minutes longer than the screens I posted... 😂😂😂😂😂

*So confusing

UPDATE:* OCCT Pro has now been testing for 00:08:00 without finding any errors 😂😂😬😂😂


----------



## TimeDrapery

*Update:* **** you, OCCT Pro... You and your Memory stability test... 😂😂😂😂😂

Also, ***...? First iteration, 00:10:25... Second iteration (same settings, no restart), 00:01:32...?!?


















How frustrating... I've no idea what the discrepancy in test duration even hints towards...


----------



## Bloax

Running a wrong tCKE means the signal is intermittently not offset correctly, which means you will get random-ass errors at random-ass times.


----------



## TimeDrapery

Bloax said:


> Running a wrong tCKE means the signal is intermittently not offset correctly, which means you will get random-ass errors at random-ass times.


Although I'm still unconvinced this timing does anything whatsoever once PowerDown Mode is disabled I'm definitely convinced the logic behind what you're saying is valid... OCCT Pro disagrees unfortunately


















Sooooo... Think, think, think... The mobo sets "*6*" at 2133MT/s and "*8*" at 3200MT/s... Assuming those are somewhat near what's supposed to be set there I'll now try setting... "*11*" at 3800MT/s! I'll try this because...

"*6* × 2000 ÷ (1066.5 × 2) = *5.626*" and "*5.626* × (1900 × 2) ÷ 2000 = *11*"

Although...

"*8* × 2000 ÷ (1600 × 2) = *5*" and "*5* × (1900 × 2) ÷ 2000 = *10*"

so I dunno if it'll scale up with frequency like other timing parameters can... Doesn't look linear (which would make sense to me considering it's "purpose") from quickly checking Auto rules by changing frequencies... 😂😂😂😂😂


----------



## Bloax

tCKE actually has a rather bizarre +2 per (hard) 100 MCLK requirement on b-die sticks, 9 at 1900, 7 at 1800, 11 at 2000 - even so far as still requiring 11 at 2084 MCLK.

If tCKE 9 is still erroring, then it's likely overvoltage, or you not setting RDRD/WRWR _dd to -1 or -2 of _sd on 4x8

could also be RDWR/WRRD +/- whatever, annoying two settings


----------



## TimeDrapery

Bloax said:


> tCKE actually has a rather bizarre +2 per (hard) 100 MCLK requirement on b-die sticks, 9 at 1900, 7 at 1800, 11 at 2000 - even so far as still requiring 11 at 2084 MCLK.
> 
> If tCKE 9 is still erroring, then it's likely overvoltage, or you not setting RDRD/WRWR _dd to -1 or -2 of _sd on 4x8


I'm thinking it could very well be the "turnaround" timings...

Ack... Here's what I see when (again, _quickly_) checking Auto rules...

2133MT/s -> "_*6*_"
3200MT/s -> "*8*"
3600MT/s -> "_*0*_" (PDM disabled) / "*0*" (PDM enabled)
3800MT/s -> "*1*" (PDM disabled) / "1" (PDM enabled)


----------



## Blackfyre

Bloax said:


> 🤡tCKE 9 ? 🤡


I've always had my tCKE set to 1 on four dimms, is that an issue?


----------



## ReyReverse

need help, I don't know how to push further.
I use A2,B2.


----------



## Nighthog

ReyReverse said:


> need help, I don't know how to push further.
> I use A2,B2.
> View attachment 2557520


Unless you want to push more frequency I don't see you have much options than a few extra steps like below:

Maybe try lower the sub-timings such as tRRDL to 4 and tWTRS & tWTRL lower and check stability? Would not do much but if it works that's all there is left to do.


----------



## ReyReverse

Nighthog said:


> Unless you want to push more frequency I don't see you have much options than a few extra steps like below:
> 
> Maybe try lower the sub-timings such as tRRDL to 4 and tWTRS & tWTRL lower and check stability? Would not do much but if it works that's all there is left to do.


Ive been tried. can't pass TM5 1usmus
and not even 1T
I feel frustrated, I ve been working on it about a month.
maybe my MOBO sucks


----------



## 67091

Removed


----------



## Nighthog

ReyReverse said:


> Ive been tried. can't pass TM5 1usmus
> and not even 1T
> I feel frustrated, I ve been working on it about a month.
> maybe my MOBO sucks


I don't know what you are complaining about, you have already about the best performance you can get for the given speed & FCLK 1:1.
You could try CL13 if you are adventerious but I don't think it's likely it will work given the kind of voltages that are needed for the memory to be possible with a adequate cooling solution.


----------



## andremoreira6215

My best result full stable on tm5 usmus 25x. Any tips to improve your


----------



## andremoreira6215




----------



## ReyReverse

Nighthog said:


> I don't know what you are complaining about, you have already about the best performance you can get for the given speed & FCLK 1:1.
> You could try CL13 if you are adventerious but I don't think it's likely it will work given the kind of voltages that are needed for the memory to be possible with a adequate cooling solution.


I want more frequency, but I have no idea how to do further and make it stable.
is it Mobo problem?


----------



## Nighthog

ReyReverse said:


> I want more frequency, but I have no idea how to do further and make it stable.
> is it Mobo problem?


You are already @ 1933 FCLK.

Might be the issue. Can't run 1:1 higher. To be stable with 1:1 @ 1933FCLK is as good as it gets. Unless you want WHEA or other issues with more you could push higher but such FCLK range is night impossible without issues. 99.99% of users are already at their issue free limit with 1900FCLK.
Need to try 2:1 Ratios? Though you won't get better performance in 2:1 Ratios though than sticking with what you already have.

I want frequency as everyone else but I have to use 2:1 ratios to get 5000Mts speeds to be possible. And in the end they aren't better than sticking to 1:1 ratios maxed out in the 3800/1900 speed.
4000/2000 usually doesn't work without WHEA issues if your CPU sample even does boot.


----------



## TimeDrapery

Yet still makes it less than one minute in OCCT Pro 😂😂😂😂😂


----------



## ocisdead

TimeDrapery said:


> View attachment 2557548
> 
> 
> Yet still makes it less than one minute in OCCT Pro 😂😂😂😂😂


Did you set those tRDRDSD/DD + tWRWRSD/DD values? With the same 4x8 setup my board sets those to 4-5-1-6-7 while yours is set to 5-4-1-7-6. Is my motherboard setting them wrong on auto?


----------



## Tebore

So I discovered something interesting with my setup. If I go in to the BIOS for any reason to make any change even unrelated to RAM, the System seems to retrain the DDR4 differently and I end up with +1-1.5ns more latency (69+). When I shutdown (full off) and turn it back on I'm back to the 67.5ns I'm 100% stable (36h of Y-Cruncher set for mem testing). 
Should I be hunting for stability problems? Or could this just be a quirk in AGESA 1.2.0.5 or the Gigabyte's bug ridden BIOS? 
It's running 18.66*101.8(102) BCLK
VDDP 925mv
VDDG CCD 950mv
VDDG IOD 1v


----------



## TimeDrapery

Grrrrr... Still less than one minute in OCCT Pro...

Definitely not unstable within Karhu RAM Test though! 😂😂😂😂😂


----------



## TimeDrapery

ocisdead said:


> Did you set those tRDRDSD/DD + tWRWRSD/DD values? With the same 4x8 setup my board sets those to 4-5-1-6-7 while yours is set to 5-4-1-7-6. Is my motherboard setting them wrong on auto?


Your motherboard is prolly setting a lot of things "wrong" on Auto 😂😂😂😂😂

Mine sets them the other way around when configured to Auto


----------



## deadfelllow

Guys,









Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com





how do i submit my memorysettings to zenspreadsheet?


----------



## ReyReverse

Tebore said:


> So I discovered something interesting with my setup. If I go in to the BIOS for any reason to make any change even unrelated to RAM, the System seems to retrain the DDR4 differently and I end up with +1-1.5ns more latency (69+). When I shutdown (full off) and turn it back on I'm back to the 67.5ns I'm 100% stable (36h of Y-Cruncher set for mem testing).
> Should I be hunting for stability problems? Or could this just be a quirk in AGESA 1.2.0.5 or the Gigabyte's bug ridden BIOS?
> It's running 18.66*101.8(102) BCLK
> VDDP 925mv
> VDDG CCD 950mv
> VDDG IOD 1v
> View attachment 2557597


3733MHz is a sweetspot you probably stable here but latency is vary , cLDO IOD always love voltage, maybe you can add some. and Aida64 check again. if 67ns that mean 100% stable


----------



## L0nerism

I've finally taken a step back and realized chasing every small timing change is a waste of my time outside of the couple major timings. I've settled on 2T since that's the only way it will train tPHYRDL at 26 on both channels at 3800. Latency ends up being about the same as my 1T config, minus some bandwidth. I have this going with 1.35v. A massive improvement over needing 1.45v before for not much gain. Pretty much just an XMP+ tune now getting me 90% of the way there. Tested to 1k% in HCI.


----------



## Audioboxer

TimeDrapery said:


> Grrrrr... Still less than one minute in OCCT Pro...
> 
> Definitely not unstable within Karhu RAM Test though! 😂😂😂😂😂
> 
> View attachment 2557621


You have to remember different tests can use slightly different testing methodology. 

IIRC OCCT is harder on the CPU whilst testing memory. You might have an unstable CPU overclock. You've really gotta make sure your CPU is 100% stable before doing memory OCing.

TM5 and Karhu are quite light on the CPU, though TM5 can sometimes catch unstable CPUs by means of timeouts showing a core failing. But there is also a debate here that TM5 timeouts can also be a Windows 11 scheduler issue. Most of the time I've found it to either be an unstable CPU or tRFC is unstable.

Hit your CPU with some Corecycler with the config.ini at prime95 720-720.

In other news Corsair accepted my RMA so at some point next week I should have my PC up and running again. Still can't believe I killed an SSD lmao.


----------



## LazyGamer

Audioboxer said:


> You've really gotta make sure your CPU is 100% stable before doing memory OCing.


Isn't the reverse also true? Found this out the hard way when first working on Alder Lake with DDR5... instability made zero sense. Plan on doing similar as I learn about Ryzen overclocking and RAM tuning.


----------



## TimeDrapery

Audioboxer said:


> You have to remember different tests can use slightly different testing methodology.
> 
> IIRC OCCT is harder on the CPU whilst testing memory. You might have an unstable CPU overclock. You've really gotta make sure your CPU is 100% stable before doing memory OCing.
> 
> TM5 and Karhu are quite light on the CPU, though TM5 can sometimes catch unstable CPUs by means of timeouts showing a core failing. But there is also a debate here that TM5 timeouts can also be a Windows 11 scheduler issue. Most of the time I've found it to either be an unstable CPU or tRFC is unstable.
> 
> Hit your CPU with some Corecycler with the config.ini at prime95 720-720.
> 
> In other news Corsair accepted my RMA so at some point next week I should have my PC up and running again. Still can't believe I killed an SSD lmao.


Yeah, my cores are 720k FFT stable... Just as a last ditch resort, seeing as I've obviously modified the system overall from the last CO tuning, I'll disable PBO n see what happens next

Good points n good look @Audioboxer


----------



## Bloax

Generally then the modus-operandi for Make System Go Fast is underclock your CPU while overclocking RAM (no point wasting power on memory tests), then overclock CPU afterwards.

The reason for this is because the faster your RAM goes, the hotter the CPU gets in very heavy loads that use memory - and tuning for stability in IN-CACHE CPU TORTURE TESTS is a little silly.


----------



## Audioboxer

TimeDrapery said:


> Yeah, my cores are 720k FFT stable... Just as a last ditch resort, seeing as I've obviously modified the system overall from the last CO tuning, I'll disable PBO n see what happens next
> 
> Good points n good look @Audioboxer


It's probably stable then but a quick test would be to go back to default with the CPU, PBO disabled, and test in OCCT. If it still dies in minutes it must be something with ram timings.

Sums up why using multiple testing apps is a good idea.


----------



## TimeDrapery

Audioboxer said:


> It's probably stable then but a quick test would be to go back to default with the CPU, PBO disabled, and test in OCCT. If it still dies in minutes it must be something with ram timings.
> 
> Sums up why using multiple testing apps is a good idea.


Certainly did sum it up

Unfortunately I've still got less than a minute of test time before errors are found even though it'll run for sooooo long in Karhu and TM5 produces no errors

That's with no PBO as well... Phooey


----------



## MrHoof

The only unusual thing i see is VDDP 0.85 did you try with 0.9 already? And maybe RTT at 7/3/3 instead.


----------



## TimeDrapery

MrHoof said:


> The only unusual thing i see is VDDP 0.85 did you try with 0.9 already? And maybe RTT at 7/3/3 instead.


Yeah, I've run through VDDP from 800mV to 950mV and _many, many_ different configurations of RTTs

Soon I'll likely step the freq down a few straps n see if that helps any

Very confusing though 😂😂😂😂😂


----------



## Bloax

TimeDrapery said:


> Unfortunately I've still got less than a minute of test time before errors are found even though it'll run for sooooo long in Karhu and TM5 produces no errors


neither Karhu nor TM5 stresses the fabric, so if it fails in OCCT or Y-Cruncher FFT - then your SOC/IOD/CCD voltage combo is bad


----------



## TimeDrapery

Bloax said:


> neither Karhu nor TM5 stresses the fabric, so if it fails in OCCT or Y-Cruncher FFT - then your SOC/IOD/CCD voltage combo is bad


Thanks!

Roger that, what would you recommend insofar as how to go about testing for SoC stability via voltage changes?

I mean, following adjustments I'm seeing differences in testing duration of approximately 30 seconds at most so it's been difficult for me to plot a course


----------



## TimeDrapery

I'm seeing the greatest increase in test duration when adjusting DDR VTT by offsetting it negatively (so, rather than 7.25 [0 offset], something like 6.75 [-0.050 offset]) in BIOS/UEFI... Whatcha think?

tCKE set to "*Auto*" produces "*16*" at 4000MT/s


----------



## KedarWolf

TimeDrapery said:


> Certainly did sum it up
> 
> Unfortunately I've still got less than a minute of test time before errors are found even though it'll run for sooooo long in Karhu and TM5 produces no errors
> 
> That's with no PBO as well... Phooey
> 
> View attachment 2557672
> 
> View attachment 2557671
> 
> View attachment 2557670


I've had issues where if I don't manually disable the Curve settings in both the main CPU menu and AMD Overclocking before disabling PBO, the Curve was still active.

Maybe check that to be sure.

Also, I got TM5 errors if I never ran y-cruncher first on my curve, only ran SFT and FFT, found one core I had to lower my Curve by one notch.

Fixed after that passing TM5, OCCT SSE and AVX2 memory test as well with my Curve.


----------



## SirPerfluous

Veii said:


> Could you go on Zentimings options-debug, and please share the output
> Might still be a dual CCD unit


Only 1









It is B2 stepping though. 2207PGT


----------



## SirPerfluous

passed Anta ABSOLUT also. (1650%)

I think this might be where I leave primaries; rcdrd&rp seem stuck there, regardless of voltage.
Using a fan, Dimm temp max of 41c @1.53v
Both of these kits require this voltage to do trfc ~126ns in 2x8

Gonna move on to subs now and we'll see where latency ends up.


----------



## KedarWolf

I had problems in TM5 with ambient warmer temperatures.

The fix was to run SCLs at 3, not 2, can even do tCWL 12 with that.

And I get zero drop in AIDA64, even latency is the same. 

Oh, need to test lowering my VSOC etc. again though.


----------



## Farih

I been running with these settings for a few weeks::









Testmem5 and memtest stable.
Temperature never above 40c.
1.54Vdimm.
4x8GB SR.

I do have an odd problem though.
Sometimes while gaming my monitors turn off and my GPU gets disabled in device manager.
Have to reboot, enable GPU and reboot again to restore it.
Doesnt happen often but its really annoying when it does.

Wattman gives a message that it failed to restore itself.
Kinda logical since the GPU gets disabled in device manager.

I think its because of RAM since it doesnt seem to happen when i set it to 3733mhz.

Any idea what this could be?

Edit:
Upped CPU PLL voltage from 1.8V to 1.85V to see if that helps.


----------



## Veii

TimeDrapery said:


> so I dunno if it'll scale up with frequency like other timing parameters can











SETUP timings are flawed, and questionable
tCKE is done
There are several options, but show instant errors

Both scale with MCLK
If skipped, great
If not, that's the range

RTT_WR affects SETUP Timings & so also tCKE
all 3 dont work together
~ RTT + SETUP
~ SETUP + tCKE
~ tCKE + RTT
one of these


----------



## deadfelllow

Hello,

Any recommendations appreciated. Thank you. Its Stable 7/24 without whea fixer


----------



## Prophet4NO1

I recently doubled my RAM. Needed more for so VM's I run on my system. It was running stable at 2000/4000 with 2000 fclk. Obviously that is not going to happen with 4 DIMMS. This is where I am so far. Could not boot above 3666 and this is the lowest timing I have been able to get so far. Looking for some advice to try and squeeze more out of the memory. Memory OC is not a strong suit for me. Just never really felt much need to push it in the past before Ryzen. I looked at dram calculator and it says my RAM is Samsung when I import the file from Typhoonburner. But Typhoonburner says it is Hynix RAM. So, just been manually been messing with things instead. So, thoughts, advice, tips, what ever you got. 

Thanks.










(edit to fix a fat finger typo and clarify previous speed)


----------



## Taraquin

deadfelllow said:


> Hello,
> 
> Any recommendations appreciated. Thank you. Its Stable 7/24 without whea fixer


Looks really good, if you get positive scaling above 1900fclk then keep it. Only adjustments would be lower wtr. Try wtrs 3 and wtrl 10 or lower.


----------



## Taraquin

Prophet4NO1 said:


> I recently doubled my RAM. Needed more for so VM's I run on my system. It was running stable at 2000 with 1000 fclk. Obviously that is not going to happen with 4 DIMMS. This is where I am so far. Could not boot above 3666 and this is the lowest timing I have been able to get so far. Looking for some advice to try and squeeze more out of the memory. Memory OC is not a strong suit for me. Just never really felt much need to push it in the past before Ryzen. I looked at dram calculator and it says my RAM is Samsung when I import the file from Typhoonburner. But Typhoonburner says it is Hynix RAM. So, just been manually been messing with things instead. So, thoughts, advice, tips, what ever you got.
> 
> Thanks.
> 
> View attachment 2557834


Hynix AJR? 

Use 1.4v


Cl 16 
Rcd 20
Rp 20
Ras 36
Rc 56
Rrds 6
Rrdl 8
Faw 24
Wtrs 4
Wtrl 12
Rfc 560
Wr 16
Rdrdscl 4
Wtwrscl 4
Cwl 16
Rtp 8
Rdwr 10
Wrrd 3

Rest on auto. If AJR I have tuned one kit in a 2x16 config, only timings you may run faster is rrds 5, rrdl 7, faw 20, rfc 544 or 528, rest seemed stuck on the kit I tuned.


----------



## deadfelllow

Taraquin said:


> Looks really good, if you get positive scaling above 1900fclk then keep it. Only adjustments would be lower wtr. Try wtrs 3 and wtrl 10 or lower.


Above 2033+ FCLK it makes audio glitch. I might try to lower Soc voltage maybe? Also going to try lower wr and wtrs


----------



## TimeDrapery

Here I am testing the old DF/SoC stability using y-cruncher with all 9 tests enabled and configured to run each of the tests for 300 seconds (5 minutes)...


















So far, so good... Even with rather low voltages configured for SoC/VDDG/P


----------



## Bloax

With CPU VDD18 at 1.85-1.93v and Park /3 or whatever, you might even be able to run RRDL 4 and WTRL 8 🤡 


deadfelllow said:


> Also going to try lower wr and wtrs
> 
> View attachment 2557837


and here I am also curious if cranking CPU 1P8 (the same thing as CPU VDD18) up, and smashing procODT down to 28.2 lets you run WTRL 8

if 28.2 doesn't work with RTT 7/0/6, then try it with 6/3/5 and tCKE 11 🔍


----------



## Prophet4NO1

Taraquin said:


> Hynix AJR?
> 
> Use 1.4v
> 
> 
> Cl 16
> Rcd 20
> Rp 20
> Ras 36
> Rc 56
> Rrds 6
> Rrdl 8
> Faw 24
> Wtrs 4
> Wtrl 12
> Rfc 560
> Wr 16
> Rdrdscl 4
> Wtwrscl 4
> Cwl 16
> Rtp 8
> Rdwr 10
> Wrrd 3
> 
> Rest on auto. If AJR I have tuned one kit in a 2x16 config, only timings you may run faster is rrds 5, rrdl 7, faw 20, rfc 544 or 528, rest seemed stuck on the kit I tuned.



I am not sure what chip is on them. I tried to look up a data sheet for the part number and did not really find anything to verify. Best I can get by looking up the die that Thypoonburner spit out (H5ANAG8N[M/A]JR-VKC) is that is a newish die from Hynix. Possibly CMR. But that is not supported in DRAM Calculator. This is one of the pages I found in my digging. RGB PRO Black 64GB 3600MHz 2x32GB

The timings you have listed may be too aggressive for this RAM. I tried playing with some of the secondary timings. Iike RFC, since it is so high. I can boot to around 700, but it causes some instability in games. Seems fine in other tests though. So, back to the default for now. I have not tried pushing the SOC voltage yet. I feel I need to get more research in on these dies before I go much deeper into this.


----------



## TimeDrapery

y-cruncher passed with no issue but OCCT Pro still won't run for longer than a minute without finding errors 😂😂😂😂😂


----------



## The_King

B-Die on First Gen Ryzen is a real pain in the butt to work with. I could not get anything above 3466MT/s to Pass TM5.
Until I tried odd primary's  Im almost convinced getting 3600 to Pass is a matter of matching the correct Primary and sub timings.


----------



## Frosted racquet

TimeDrapery said:


> y-cruncher passed with no issue but OCCT Pro still won't run for longer than a minute without finding errors 😂😂😂😂😂


Have you tested how OCCT behaves with stock CPU and XMP only? Or just 2133MHz profile?


----------



## Taraquin

Prophet4NO1 said:


> I am not sure what chip is on them. I tried to look up a data sheet for the part number and did not really find anything to verify. Best I can get by looking up the die that Thypoonburner spit out (H5ANAG8N[M/A]JR-VKC) is that is a newish die from Hynix. Possibly CMR. But that is not supported in DRAM Calculator. This is one of the pages I found in my digging. RGB PRO Black 64GB 3600MHz 2x32GB
> 
> The timings you have listed may be too aggressive for this RAM. I tried playing with some of the secondary timings. Iike RFC, since it is so high. I can boot to around 700, but it causes some instability in games. Seems fine in other tests though. So, back to the default for now. I have not tried pushing the SOC voltage yet. I feel I need to get more research in on these dies before I go much deeper into this.


Read from this line: 'M/A]JR-'. They are either AJR or MJR then, I think MJR since they can't do sub 600 rfc. MJR is a terrible die, but try all the timings I suggested except set RFC to 704, 688, 672, 656, 640 or 624, lowest that works. Other suggestions should work even if they are MJR.


----------



## Audioboxer

Hmm, whilst waiting on my replacement NVMe drive I was doing some reading these storage drives actually operate best with a bit of heat in them? Anyone know if there is truth to that? I think my operating temps with a heatsink were like 35~40 degrees. Coming around to just scrapping the "fun" of watercooling the NVMe and chalking it up to a failed learning experience.

I know there is no performance gain, but part of me thought the drive could last 1% longer being well cooled and it's just fun adding things to the loop. Now I'm beginning to think unlike watercooling B-die which has some actual benefits, it could even be slightly detrimental to watercool an NVMe???

Or we talking like really low temps hurting them?


----------



## sealxohd

I got myself a 5800X3D with good FCLK. Right now im WHEA free at 2066 with nice an linear scaling.

FCLK might go even higher with more volts but right now Im at 1.225 get VSOC and I dont feel like degrading that chip, even if 1.25 V should be fine.

The cache makes FH4 fly 

Im working on 1T right now. But this IMC behaves somewhat different compared to the one of my 5900X. I need to fiddle with everything some more.


----------



## Frosted racquet

Audioboxer said:


> Hmm, whilst waiting on my replacement NVMe drive I was doing some reading these storage drives actually operate best with a bit of heat in them? Anyone know if there is truth to that?


SSD controllers can throttle if too hot, NAND chips operate better when they're a higher temperature (40-50C) and cooling them can cause data loss in extreme situations.


----------



## Audioboxer

sealxohd said:


> I got myself a 5800X3D with good FCLK. Right now im WHEA free at 2066 with nice an linear scaling.
> 
> FCLK might go even higher with more volts but right now Im at 1.225 get VSOC and I dont feel like degrading that chip, even if 1.25 V should be fine.
> 
> The cache makes FH4 fly
> 
> Im working on 1T right now. But this IMC behaves somewhat different compared to the one of my 5900X. I need to fiddle with everything some more.


Hmm, bit surprised at the latency there. Run it in diagnostic mode/safe mode just to see if it's background jank. At 4133 I'd expect lower than 54ns. Poor latency can sometimes be a sign of performance regression due to higher FCLK.

Even at 2T, with tCL15 at 4133 I'd expect you to be lower.


----------



## sealxohd

Audioboxer said:


> Hmm, bit surprised at the latency there. Run it in diagnostic mode/safe mode just to see if it's background jank. At 4133 I'd expect lower than 54ns. Poor latency can sometimes be a sign of performance regression due to higher FCLK.
> 
> Even at 2T, with tCL15 at 4133 I'd expect you to be lower.


This is in safe mode.

Thats what I was first thinking as well and I was completly clueless what to do since everything else scaled normally. But the L3 latency just increased a bit and thus the total latency of the mem sub system as well. L3 Latency is around 3 ns more. Common behavior it seems. I know a few people with 5800X3D and they all have a higher latency compared to their normal Zen3 chips.


----------



## Bloax

Cache latency scales with cache size - the fact that it has increased a little, not a lot, despite being tripled in size is magical.

If you're curious as to why, then it simply takes more time to "traverse" a larger amount of cache cells in search of "the data" - as well as retrieving this signal having to travel a longer path.
Tripling capacity by scaling its 2D size would cripple latency, but apparently it's not that bad if you introduce a new way (a NEW DIMENSION wAoW!11!) for the signal to go.

You can see a practical example of this by looking at L3 cache latency numbers for the different iterations of Skylake, Skylake+, Skylake++, Skylake+++ - which featured the exact same microarchitecture (i.e. same implementation of the cache structure) but with different cache sizes.
though finding them at more-or-less-the-same-frequency can be tricky


----------



## Audioboxer

Bloax said:


> Cache latency scales with cache size - the fact that it has increased a little, not a lot, despite being tripled in size is magical.


Good to learn!

Gives me hope the next line of AMD chips aren't going to be stinkers when it comes to something like FCLK.


----------



## Taraquin

sealxohd said:


> I got myself a 5800X3D with good FCLK. Right now im WHEA free at 2066 with nice an linear scaling.
> 
> FCLK might go even higher with more volts but right now Im at 1.225 get VSOC and I dont feel like degrading that chip, even if 1.25 V should be fine.
> 
> The cache makes FH4 fly
> 
> Im working on 1T right now. But this IMC behaves somewhat different compared to the one of my 5900X. I need to fiddle with everything some more.


Nice! 1t above 4000 may be difgicult sometimes.


----------



## TimeDrapery




----------



## Nighthog

@sealxohd 
Not anything in particular you had to do to not get WHEA errors at such FCLK with your 5800X3D?
Did it just work or did you have to do something specific to have it run that well?


----------



## sealxohd

Nighthog said:


> @sealxohd
> Not anything in particular you had to do to not get WHEA errors at such FCLK with your 5800X3D?
> Did it just work or did you have to do something specific to have it run that well?


I just got lucky. I know about 3 more X3Ds and they are all stuck at 1900 what so ever in terms of WHEAs. (Much like my other Zen3 chips)

I can trigger WHEAs when my VDDG voltages are to low. Besides tuning these, I didnt do anything special.


----------



## Frosted racquet

How does temperature affect stability on Samsung b-die? Is it related to a specific timing, lets say if you're >50C you need to increase tRFC?
I see recommendations in this thread that 40-45C is optimal for b-die, but some say up to 60C is OK depending on timing/frequency and voltage.

Is there anything obviously wrong with my current setup? Anything I could change without affecting stability? tRFC 2/3 are unknown for me, I just copied the settings from another user... tCKE 0 ok? I'm not looking for the tightest timings.
3800Mbits/s is a no go for my IF as it only does 1800 without WHEA 19 errors (tried to tweak it for a couple of hours, managed to decrease WHEA 19 but not eliminate)

Thanks in advance.


----------



## hazium233

TimeDrapery said:


> View attachment 2557951
> 
> View attachment 2557950


I think OCCT is more sensitive for tWR than the others. You already tried 16 though iirc, and can't imagine you would necessarily need higher.

What was the highest speed / loosest timings that passed OCCT so far?

May even need to consider checking the four dimms one at a time and see if it is just one weak one causing the error.


----------



## TimeDrapery

hazium233 said:


> I think OCCT is more sensitive for tWR than the others. You already tried 16 though iirc, and can't imagine you would necessarily need higher.
> 
> What was the highest speed / loosest timings that passed OCCT so far?
> 
> May even need to consider checking the four dimms one at a time and see if it is just one weak one causing the error.


Good point! I'm going to start working my way up in clock speeds from 3200MHz and see what freqs that I start finding errors in OCCT Pro if I can't determine what parameter is causing errors to arise when setting Auto for most all these parameters and seeing how that impacts testing duration

*Update:* 16-16-16-32 with all other timings set to "Auto" runs for 00:00:49 as opposed to the 00:00:10 when timing parameters are configured as shown in the screenshot below


----------



## Prophet4NO1

Taraquin said:


> Read from this line: 'M/A]JR-'. They are either AJR or MJR then, I think MJR since they can't do sub 600 rfc. MJR is a terrible die, but try all the timings I suggested except set RFC to 704, 688, 672, 656, 640 or 624, lowest that works. Other suggestions should work even if they are MJR.



Progress has been made. It booted up with the suggested timing and benches a bit better. Latency is not great, but I am not sure how much better I can really get that. Going to try the lower RFC timings and go from there. If I leave the sub timings for RFC on auto, will they scale with the first one? I have really done very little in the past outside of primary timings, so this is pretty new ground for me. 

Old timings









New timings.


----------



## Prophet4NO1

I manually turned down RFC2 & 4 a bit. Not much change. Not sure how aggressive you can really go with these and what effect they will have.


----------



## Taraquin

Prophet4NO1 said:


> Progress has been made. It booted up with the suggested timing and benches a bit better. Latency is not great, but I am not sure how much better I can really get that. Going to try the lower RFC timings and go from there. If I leave the sub timings for RFC on auto, will they scale with the first one? I have really done very little in the past outside of primary timings, so this is pretty new ground for me.
> 
> Old timings
> View attachment 2557997
> 
> 
> New timings.
> View attachment 2557996


Try working your way down by 16 and 16 on RFC, RDDS 5, RRDL 7 and FAW 20 may work, change all 3 at same time, You can try RCDRD 19, may work, also RP 19, may work, if you get both of them down try RAS 34, RC 53.


----------



## Taraquin

Prophet4NO1 said:


> I manually turned down RFC2 & 4 a bit. Not much change. Not sure how aggressive you can really go with these and what effect they will have.
> 
> View attachment 2558001


Your latency is quite high considering what speed you run. try to set SOC to 1.15v and lower VDDP to 0.95v.


----------



## Veii

Prophet4NO1 said:


> I manually turned down RFC2 & 4 a bit. Not much change. Not sure how aggressive you can really go with these and what effect they will have.
> 
> View attachment 2558001


Drop GDM, go to 2T and then check how low tRFC can go
Touch it only at the very end, not now
If it's missed it will be repeated, but you will waste delay and bandwidth at the same time
In the worst scenario, it will error because of it
^ just rarely notice that it was the issue, soo don't touch it in the beginning or trust tRFC mini to give you some predictions

29332MB/s is your target for write // you have 29306MB/s
Anything bellow that value is an indication of throttle (FCLK throttle , voltages/stability)
Drop that 1.1v cLDO_VDDP down to bellow 950mV
Bellow 925mV even as that is only for MCLK and the IMC

The IMC has no connection to your dimms you put on it, yet voltage you push on it has a negative powering/noise effect on your dimms
cLDO_VDDP bellongs to IMC for MCLK, not FCLK
procODT belongs to FCLK & cores stability, not MCLK or DIMM
Lower that value, probably even down to 860mV for this low MCLK. 900mV like everyone else on 1900MHz MCLK, should be fine.
Your procODT looks about right.

You might want to consider for CAD_BUS 60-20-30-20 as an attempt on this capacity
Maybe even 120-20-20-24 with 6-3-3/6-3-2 RTT or 6-2-3 (NOM, WR, PARK // RZQ=240ohm, soo /6 = 40ohm)
You'll notice what works out
Also if unstable, might want to give tRDWR a bump of +1 or +2 even ~ then check if 16-19-19-38-57 can work out
tRDWR delay later "once proofen stable !" , can be lowered. Will eat bandwidth but not that important for now

Important is tho, that you get GDM away,else you waste time thinking memory is stable ~ while in reality powering was an issue


----------



## Prophet4NO1

Ok, Thanks everyone. I am going to take the info and keep tweaking. Starting with GDM off on 2T and going from there. Along with the voltage adjustments above.

(UPDATE)

I made the edits above. Already a small improvement in bandwidth and response in Aida is down to a consistent 71ns. Before it would move around every test by 2-3ns every run. Now it is around a 0.2 variance. So, instability has been ironed out some. Going back in to tweak things a bit more.

And write speeds jumped to 29395MB/s. So, that is on target now.


----------



## Prophet4NO1

Taraquin said:


> Try working your way down by 16 and 16 on RFC, RDDS 5, RRDL 7 and FAW 20 may work, change all 3 at same time, You can try RCDRD 19, may work, also RP 19, may work, if you get both of them down try RAS 34, RC 53.


On the RFC, are you saying to drop in inraments of 16 on each of the RFC entries? Just trying to make sure I understand you correctly before I just start to monkey around. I may try some of the lower RFC numbers you gave before and then look at inching it down from there. Since recent tweaks have given some gains in stability and performance.


----------



## KedarWolf

I had to raise RAM voltage to 1.54v to get it TM5 stable at a much higher ambient temp in my place. VTTs are still at .730v.

Oh, and SCLs at 3 instead of 2. I lose no bandwidth and the same latency. And easier to get stable. 

But it passed TM5 1000% 8 cycles in less than 7 hours overnight.

I heard a longer cycle time is better than say TM5 default at 50 cycles.


----------



## Taraquin

Prophet4NO1 said:


> On the RFC, are you saying to drop in inraments of 16 on each of the RFC entries? Just trying to make sure I understand you correctly before I just start to monkey around. I may try some of the lower RFC numbers you gave before and then look at inching it down from there. Since recent tweaks have given some gains in stability and performance.


Find lowest stable that boost performance. Don't bother with 2/4, just lower primary RFC, the others are inactive if I remember correct. I would advice to run aida in safety mode, you have probably a lot of backgroundapps, L3 cache has poor result, safety mode drops loafing background apps. Drop by 16 and 16 is a guidance, you can try RFC mini as suggested by Veii.


----------



## Frosted racquet

Frosted racquet said:


> How does temperature affect stability on Samsung b-die? Is it related to a specific timing, lets say if you're >50C you need to increase tRFC?
> I see recommendations in this thread that 40-45C is optimal for b-die, but some say up to 60C is OK depending on timing/frequency and voltage.
> 
> Is there anything obviously wrong with my current setup? Anything I could change without affecting stability? tRFC 2/3 are unknown for me, I just copied the settings from another user... tCKE 0 ok? I'm not looking for the tightest timings.
> 3800Mbits/s is a no go for my IF as it only does 1800 without WHEA 19 errors (tried to tweak it for a couple of hours, managed to decrease WHEA 19 but not eliminate)
> 
> Thanks in advance.
> 
> View attachment 2557961
> View attachment 2557962
> View attachment 2557963
> View attachment 2557964


Here are AIDA64 results, both in normal and in safe mode


----------



## fqqf

hey guys, my timings is normal? i have patriot blackout 4133(xmp) b-die, but i can`t set voltage over 1.47(because my cooling is bad) so, i want ask about tRFC, tRDWR, tWRRD, tWR, tRTP, tFAW and other first and secondary timings. thx u guys for help


----------



## PJVol

fqqf said:


> i want ask about tRFC, tRDWR, tWRRD, tWR, tRTP, tFAW


tWRRD 1, tFAW doesn't matter (in my experience), Vsoc 1.000V, VDDP 0.9V, VDDG - both 0.95, procODT try 32Ohm
Gdm can be turned off.


----------



## pfinch

do you have any suggestions for improvements?
GDM on causes tPHYDRL 26/28. I've tried everything with voltages.
So I'll leave it at 2T for now and try to tune it.
DIMM @1.5v


----------



## 99belle99

This is mine at XMP. It's pretty bad and only just realised it has GDM enabled at XMP.


----------



## Karagra

Hey guys just picked up a 5800x3d and some OLOy 3600mhz CL14 1.45v ram, everything is completely default was wondering where I should go from here with this ram..


----------



## Prophet4NO1

Taraquin said:


> Find lowest stable that boost performance. Don't bother with 2/4, just lower primary RFC, the others are inactive if I remember correct. I would advice to run aida in safety mode, you have probably a lot of backgroundapps, L3 cache has poor result, safety mode drops loafing background apps. Drop by 16 and 16 is a guidance, you can try RFC mini as suggested by Veii.



Yeah, there are a few things running in background. Lowest I see on L3 is about 11ns typically. But it varies a fair bit run to run in normal boot. I will revisit this on the weekend, most likely. Not much free time for this during the week. I think I will find a happy spot soon and then try to back off the DIMM voltage. Try to bring temps down if I can. With four sticks they get pretty warm. Around 45-48c when gaming to testing. Not terrible, but if I can get temps down that would be good.


----------



## Veii

Prophet4NO1 said:


> With four sticks they get pretty warm. Around 45-48c when gaming to testing. Not terrible, but if I can get temps down that would be good.


Drop RTT PARK to a weaker value (higher divider) and temps will drop
But actually test your settings. I haven't seen any confirmation of stability so far
Neither HCI/Karhu 10 000% nor TM5 25 loops (20+ minimum)

Same for the CPU
Neither y-cruncher components test, nor OCCT Extreme


----------



## TimeDrapery

Veii said:


> Drop RTT PARK to a weaker value (higher divider) and temps will drop
> But actually test your settings. I haven't seen any confirmation of stability so far
> Neither HCI/Karhu 10 000% nor TM5 25 loops (20+ minimum)
> 
> Same for the CPU
> Neither y-cruncher components test, nor OCCT Extreme


What do you think about my case? I've got multiple runs over 10000% in Karhu, 750% in MemTest, TM5 (1usmus_v3 and Extreme1), but AVX2 OCCT Memory test won't run for more than a minute at any frequency greater than 3200MT/s


----------



## Bloax

Could just be that the OCCT installation is ****ed, just like I've managed to make TM5 not work on a burner OS.


----------



## Veii

TimeDrapery said:


> What do you think about my case? I've got multiple runs over 10000% in Karhu, 750% in MemTest, TM5 (1usmus_v3 and Extreme1), but AVX2 OCCT Memory test won't run for more than a minute at any frequency greater than 3200MT/s


A memory test wouldn't "care" , bother between what type of instruction set you test it with
It is a difference between "how" you test it, but this difference between linpack and 1usmus's vision of how things should test ~ we already have

Soo for an AVX2 test to error, it sounds more of a voltage bleed issue
Loadline, or noise issue outside of memory or it's timings


----------



## TimeDrapery

Bloax said:


> Could just be that the OCCT installation is ****ed, just like I've managed to make TM5 not work on a burner OS.


That's a good idea, FFS it's prolly the application that's crashed most often 😂😂😂😂😂

@Veii 

I'm wondering if it's not a noise issue, I tested thoroughly with y-cruncher the other day without issue so if a new copy of OCCT doesn't remedy this then I'll just pull two of the DIMMs until the next time I'm craving headaches 😂😂😂😂😂


----------



## domdtxdissar

Starting karhu ram test before i go to work, lets see what results i'm getting when i get home 
5800x3d @ 4066MT/s -> a few whea errors here and there but no negative scaling
(win11)


----------



## Audioboxer

Is the 5800X3D more like the G chips when it comes to how it handles FCLK, or is it more like a single CCD Ryzen processor? 

In other news whilst waiting for delivery of my replacement MP600 Pro, I found a really old 128GB NVMe drive I had lying about. Goodness knows how many years old it is now. Funnily enough you really notice a speed decrease. As much as these current NVMe 4.0 drives might be at speeds no one is going to really notice unless they're moving massive files, these older NVMe drives do show their limitations!

For anyone that has a Lian Li O11 XL, I really recommend this Lian-Li Dynamic XL | Front Grill (Lines) Clear | ColdZero Got delivered the other day. I'm just waiting on my 140mm fans arriving and I'll get some pics. I've known about replacement front panels for a year or so, but most prior to now were just all metallic, making the front look like the top of the case. This new clear plexiglass model gives you the best of both worlds. A front exhaust/intake for fans, and it's clear.

Going to be using mine as exhaust. So all 4 of my rads are set to intake, front of case, exhaust. That way it won't be a total hotbox with 4 rads running intake and the air inside trying to find ways to squeeze out ports.


----------



## Taraquin

Audioboxer said:


> Is the 5800X3D more like the G chips when it comes to how it handles FCLK, or is it more like a single CCD Ryzen processor?
> 
> In other news whilst waiting for delivery of my replacement MP600 Pro, I found a really old 128GB NVMe drive I had lying about. Goodness knows how many years old it is now. Funnily enough you really notice a speed decrease. As much as these current NVMe 4.0 drives might be at speeds no one is going to really notice unless they're moving massive files, these older NVMe drives do show their limitations!
> 
> For anyone that has a Lian Li O11 XL, I really recommend this Lian-Li Dynamic XL | Front Grill (Lines) Clear | ColdZero Got delivered the other day. I'm just waiting on my 140mm fans arriving and I'll get some pics. I've known about replacement front panels for a year or so, but most prior to now were just all metallic, making the front look like the top of the case. This new clear plexiglass model gives you the best of both worlds. A front exhaust/intake for fans, and it's clear.
> 
> Going to be using mine as exhaust. So all 4 of my rads are set to intake, front of case, exhaust. That way it won't be a total hotbox with 4 rads running intake and the air inside trying to find ways to squeeze out ports.


From the looks of it more like single CCD. Still most get WHEA19 above 1900fclk. There may be an option of running desynced fclk and ramspeed of 4500+ that may benefit 5800X3D as the large L3 cache seems to make ram timings\latency matter very little, but it still scales with increased bandwith, so if my suspision is correct you may get a performance boost in many games by running desynced at 4500+ vs 3800\1900.


----------



## Frosted racquet

Veii said:


> Drop RTT PARK to a weaker value (higher divider) and temps will drop


Would you recommend I modify RTT PARK as well, as I'm seeing temps rise up to 60C in RAM tests (around 45C in games) but no apparent errors in stability tests.
Here are my stability test and AIDA64 bench








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread







www.overclock.net












[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread







www.overclock.net


----------



## ArchStanton

Audioboxer said:


> I really recommend this


My eyes! It burns! Anything but clear acrylic. It's like Lian Li and Singularity Computers had a love child that crawled out of the ditch that was meant to serve as its grave.

Okay, I love the idea, and I certainly support function over form, but I think I'd prefer a laser cut metal one. As the former owner of a Thermaltake Armor+ (don't ask), I am haunted by visions of an acrylic side panel.


----------



## domdtxdissar

domdtxdissar said:


> Starting karhu ram test before i go to work, lets see what results i'm getting when i get home
> 5800x3d @ 4066MT/s -> a few whea errors here and there but no negative scaling
> (win11)
> View attachment 2558205


9 hours later, still no errors other than whea 
Karhu @ 18k %


----------



## Blackfyre

Veii said:


> Drop RTT PARK to a weaker value (higher divider) and temps will drop


I assume this is the lowest resistance possible on all values below: Used the highest divider for each one.

Was already stable before, but if lowering them results in better temps, why not. *Only thing I actually lowered was RttPark to RZQ/7 instead of RZQ/1, *everything else was already at weakest value (resistance).

VDIMM = 1.495v

*Question, where would I check RAM temperatures? *HWiNFO64 doesn't show RAM temps for my 4 x 8Gb Micron E-die








*PS: The above was stable, with OCCT CPU Stress 1 hour running in the middle of TM5 1usmus cycles:







*


----------



## Audioboxer

ArchStanton said:


> My eyes! It burns! Anything but clear acrylic. It's like Lian Li and Singularity Computers had a love child that crawled out of the ditch that was meant to serve as its grave.
> 
> Okay, I love the idea, and I certainly support function over form, but I think I'd prefer a laser cut metal one. As the former owner of a Thermaltake Armor+ (don't ask), I am haunted by visions of an acrylic side panel.
> View attachment 2558223


To be fair it looks really smart in person, even more so if you've got some RGB fans for the front. I just spent £18 on like 3 140mm Arctic fans for now lol. Can't beat the price of these bad boys. I just need an exhaust at the front. Maybe down the line I'll nab some 140mm RGB fans.

The problem with other face replacements for the Lian Li, at least in my opinion, is making the case look a bit....I dunno, oppressive? The default Lian Li with the glass just feels open and airy!










The mini looks quite smart, but its top piece is that hole design and it flows well. Quite like an NZXT case. I just don't really like the top XL lines design, on the front (with the plexiglass its transparent lines, at least).

Though the Mayan design looks not bad (they have this for XL)



















At the end of the day, I just wanted front fans! And something somewhat keeping the see-through look of a glass panel!

In other news, I bought a Samsung 970 EVO Plus to stick Windows on. No more nonsense with 1 NVMe going down and the whole system is out of action lol. Though, I will not be attempting to watercool anything again.... lol.

Sadly the one downside to the B550 boards is not having more than 1 PCIe 4.0 full speed for a second NVMe without dropping the GPU down to 4.0 x8. For Windows though a NVMe 3.0 will be more than fast enough. Will use the MP600 Pro just for games.


----------



## ReyReverse

domdtxdissar said:


> 9 hours later, still no errors other than whea
> Karhu @ 18k %
> View attachment 2558247


Hi, I want to know WHEA detected doesn't mean unstable?
windows won't randomly bsod ? I have so many tried before. once I see WHEA coming more than 15 I will stop the test immediately to avoid it go bsod


----------



## deadfelllow

Blackfyre said:


> I assume this is the lowest resistance possible on all values below: Used the highest divider for each one.
> 
> Was already stable before, but if lowering them results in better temps, why not. *Only thing I actually lowered was RttPark to RZQ/7 instead of RZQ/1, *everything else was already at weakest value (resistance).
> 
> VDIMM = 1.495v
> 
> *Question, where would I check RAM temperatures? *HWiNFO64 doesn't show RAM temps for my 4 x 8Gb Micron E-die
> View attachment 2558266
> 
> *PS: The above was stable, with OCCT CPU Stress 1 hour running in the middle of TM5 1usmus cycles:
> View attachment 2558267
> *


Hey,

I had the same ram kit 4x8 ballistix instead of 2x16 (c9blm). You can easily lower trcdwr to 8, trp to 12, and tras to 21.. or 8 13 26


----------



## Prophet4NO1

Veii said:


> Drop RTT PARK to a weaker value (higher divider) and temps will drop
> But actually test your settings. I haven't seen any confirmation of stability so far
> Neither HCI/Karhu 10 000% nor TM5 25 loops (20+ minimum)
> 
> Same for the CPU
> Neither y-cruncher components test, nor OCCT Extreme



I have not run any long tests yet. I wont dig in hard till this weekend. Most of my stability testing was just running Aida stress test for 20-30 min so far. I need more free time to do longer testing. Or at least some time where I wont be too busy to check in on it when testing. So, this weekend.


----------



## Blackfyre

deadfelllow said:


> Hey,
> 
> I had the same ram kit 4x8 ballistix instead of 2x16 (c9blm). You can easily lower trcdwr to 8, trp to 12, and tras to 21.. or 8 13 26
> 
> 
> View attachment 2558334


Why do I not have DIMM Temperature readings in my HWiNFO64?
What voltage were you running to achieve these numbers?

You also have tRFC at 538 when I know for me I lose stability below 552, whea errors at 544, and pretty much not possible to run below that from memory.

Pretty sure I could also not boot with RttNom disabled or RttWr Off when I tested those before.

*EDIT: I just realised you're not running 3800Mhz 1900 FCLK for those timings.*


----------



## deadfelllow

Blackfyre said:


> Why do I not have DIMM Temperature readings in my HWiNFO64?
> What voltage were you running to achieve these numbers?
> 
> You also have tRFC at 538 when I know for me I lose stability below 552, whea errors at 544, and pretty much not possible to run below that from memory.
> 
> Pretty sure I could also not boot with RttNom disabled or RttWr Off when I tested those before.
> 
> *EDIT: I just realised you're not running 3800Mhz 1900 FCLK for those timings.*


I guess vDIMM was around 1.5 ish volts. It was really hard to boot 3800mhz with 4 sticks on a ****ty mobo. Thats why its 3733.

I have no idea about temperature reading on hwinfo.


----------



## andremoreira6215

Hey people today something weird happen d with testmem5. While I'm using it with 1usmus cfg, the ram at cycle 19 becomes complete available but the timer doesn't stop, and config its to do 25 cycles. Someone know the issue?


----------



## Frosted racquet

andremoreira6215 said:


> Hey people today something weird happen d with testmem5. While I'm using it with 1usmus cfg, the ram at cycle 19 becomes complete available but the timer doesn't stop, and config its to do 25 cycles. Someone know the issue?


I'm certain it's because of a bug in the program/config. I've seen it happened on several systems that are not overclocked, so the only logical conclusion is that it's a bug. However, several people here swear it is a system instability, but good luck figuring what's the "problem" with your system.
In my experience, Absolut and Universal2 configs don't exhibit that problem as frequently as 1usmus does.


----------



## Blackfyre

Anyone know what this information (highlighted) on the right is? Is it general information or guidelines to change the values?

Via AIDA64 Extreme RAM Information section:









*Current timings:*


----------



## Mach3.2

Blackfyre said:


> *Question, where would I check RAM temperatures? *HWiNFO64 doesn't show RAM temps for my 4 x 8Gb Micron E-die


As far as I know the non-RGB Ballistix DIMMs do not have temperature sensors, only Ballistix Max and the RGB versions of the normal Ballistix DIMMs have temp sensors

Only way to get a temp read out is with a thermoprobe or IR camera.


----------



## hazium233

Blackfyre said:


> Anyone know what this information (highlighted) on the right is? Is it general information or guidelines to change the values?
> 
> Via AIDA64 Extreme RAM Information section:
> View attachment 2558420
> 
> 
> *Current timings:*
> View attachment 2558421


Ras to Ras same bank group = RRDL
Ras to Ras different bank group = RRDS

Read to Read different rank = RDRDSD ("same dimm"), or RDRDDD ("different dimm")
Read to Read same bank group = RDRDSCL
Read to Read different bank group = RDRDSC

Write to Read = tWRRD (write command to read command spacing)
Write to Read same bank group = WTRL (write burst to read command spacing)
Write to Read different bank group = WTRS

Write to Write follows same as Read to Read but with the WRWR__ timings.

*One thing though is that the RDRD_ and WRWR_ are offset by a few different things, per document posted way back in this thread.

The _SCL and __SC timings -3 from actual Cas to Cas delay (eg 4 corresponds to CCDL 7)

_SD and _DD are more convoluted


----------



## ReyReverse

andremoreira6215 said:


> Hey people today something weird happen d with testmem5. While I'm using it with 1usmus cfg, the ram at cycle 19 becomes complete available but the timer doesn't stop, and config its to do 25 cycles. Someone know the issue?


probably sleep mode problem, just turn it off from power plan


----------



## Worldwin

Back to working on this profile and have these errors. Have tried changing ProcODT from 28-34.3 and Rttnom from 6->>7 with mixed results. All have some errors.
Any suggestions.


----------



## UnchiuNarcis

Try these settings if you have a G skill Trident Z Royal. Happy to help, fully stable!


----------



## pfinch

hazium233 said:


> Ras to Ras same bank group = RRDL
> Ras to Ras different bank group = RRDS
> 
> Read to Read different rank = RDRDSD ("same dimm"), or RDRDDD ("different dimm")
> Read to Read same bank group = RDRDSCL
> Read to Read different bank group = RDRDSC
> 
> Write to Read = tWRRD (write command to read command spacing)
> Write to Read same bank group = WTRL (write burst to read command spacing)
> Write to Read different bank group = WTRS
> 
> Write to Write follows same as Read to Read but with the WRWR__ timings.
> 
> *One thing though is that the RDRD_ and WRWR_ are offset by a few different things, per document posted way back in this thread.
> 
> The _SCL and __SC timings -3 from actual Cas to Cas delay (eg 4 corresponds to CCDL 7)
> 
> _SD and _DD are more convoluted


So...he got an issue? I don't get it.


----------



## Taraquin

Worldwin said:


> View attachment 2558469
> 
> Back to working on this profile and have these errors. Have tried changing ProcODT from 28-34.3 and Rttnom from 6->>7 with mixed results. All have some errors.
> Any suggestions.


Try 0.02V higher volt on ram, I bet that will fix it unless it overheats  You have a lot of headroom on rfc and rc btw.
RC 45
RRDL 6
RFC 272
RTP 5


----------



## Worldwin

Taraquin said:


> Try 0.02V higher volt on ram, I bet that will fix it unless it overheats  You have a lot of headroom on rfc and rc btw.
> RC 45
> RRDL 6
> RFC 272
> RTP 5


Unfortunately I don't. I have actually tried those values before and they failed miserably. When I had [email protected] 170ns it failed.. I also want to keep the voltage at 1.45 since summer is coming. Next time I grab TridentZ variant as I think they bin Ripjaws worse based on the overclocks I've gotten event though they have the same XMP timings.


----------



## Blackfyre

pfinch said:


> So...he got an issue? I don't get it.


Yeah I loved the detailed response. But I still did not understand whether that is just information (general), or AIDA 64 giving advice as to values I might need to change? 

I assume it's just general information. As if it was issues, someone would have noticed & said so.


----------



## Taraquin

Worldwin said:


> Unfortunately I don't. I have actually tried those values before and they failed miserably. When I had [email protected] 170ns it failed.. I also want to keep the voltage at 1.45 since summer is coming. Next time I grab TridentZ variant as I think they bin Ripjaws worse based on the overclocks I've gotten event though they have the same XMP timings.


Pulling of flat 15 is not easy on many B-die kits at 3800 1.45v. If you won't raise voltage I would rather aim for 15 16 15, 15 16 16 or 16 16 16. The other adjustments I said should be easier with higher prims and they impact performance more than flat 15, but if you stick with 1.45v or lower try 288 rfc.


----------



## Worldwin

Taraquin said:


> Pulling of flat 15 is not easy on many B-die kits at 3800 1.45v. If you won't raise voltage I would rather aim for 15 16 15, 15 16 16 or 16 16 16. The other adjustments I said should be easier with higher prims and they impact performance more than flat 15, but if you stick with 1.45v or lower try 288 rfc.


Half the problems coming cause I want CR1 instead of CR2. I'm pretty sure my TRFC won't go lower.


----------



## slice313

I spent sometime trying to squeeze this kit. Someone with experience tweaking *Micron Rev. J* (Patriot mem barcode: *19JJB*)?










For now this is what I achieved but I am not sure if "better" is possible. Any hints?

Thank you


----------



## Taraquin

Worldwin said:


> Half the problems coming cause I want CR1 instead of CR2. I'm pretty sure my TRFC won't go lower.


I have never heard of B-die not being able to go below 340 at 1.45v, that is 180ns. Ref for good to bad binned B-die at 1.45v is 130-160ns. My avg binned 4400cl19 do 143ns. Either you are very unlucky or there is potential unexplored.


----------



## Taraquin

slice313 said:


> I spent sometime trying to squeeze this kit. Someone with experience tweaking *Micron Rev. J* (Patriot mem barcode: *19JJB*)?
> 
> View attachment 2558634
> 
> 
> For now this is what I achieved but I am not sure if "better" is possible. Any hints?
> 
> Thank you











Micron Rev.E 8/16Gbit vs Rev.J & Hynix DJR 8Gbit


Want to make a short little write up on the experience I've gained from comparing these different Memory IC's I've attained and used in the same system. Ryzen 3800X (& 4650G) Gigabyte X570 Aorus Xtreme I've just recently attained 2x kits of Kingston HyperX Fury 2x8GB 3600Mhz CL17...




www.overclock.net





Try 3800 or 3733 is my first advice. If you plan to use only 3600 try rcdrd 19, rp 19, ras 35, rc 54, rrds 4, rrdl 6, faw 16, rfc 528, wtrs 4, wtrl 8, wr 16, rtp 8, rdwr 10, wrrd 1, scl's 4.


----------



## Veii

Worldwin said:


> View attachment 2558469
> 
> Back to working on this profile and have these errors. Have tried changing ProcODT from 28-34.3 and Rttnom from 6->>7 with mixed results. All have some errors.
> Any suggestions.











15+30 = ?
Increase tWR to 16 , and CsOdtDrvStr to 30
likely even 40-20-40-20 CAD_BUS
else 40-20-30-24
another one is 60-20-40-20



Worldwin said:


> I also want to keep the voltage at 1.45 since summer is coming


VDIMM means nothing, does not relate to heat.
Amperage does, which is controlled by ClkDrvStr , high procODT and strong RTT_NOM
6-2-3 should work, or 6-2-4
6-3-3 and 7-3-3 are common, but your preset is not fluent
Soo you likely dont know if 2T is actually stable, or all was autocorrection


Worldwin said:


> Luck. I had a two 3200 C14 kits that could hit 140ns NP.


Neither does tRFC relate to "performance" or binning
it's just voltage and "left charge" (how low you can go)

Often "higher" is better, as long as it's not skipped and repeat
You won't see that it's repeaten except for higher ns delay. But you won't be able to tell it's tight, when timings are odd
Soo 180ns or 150ns doesn't matter with loosy timings


----------



## Worldwin

Taraquin said:


> I have never heard of B-die not being able to go below 340 at 1.45v, that is 180ns. Ref for good to bad binned B-die at 1.45v is 130-160ns. My avg binned 4400cl19 do 143ns. Either you are very unlucky or there is potential unexplored.


Luck. I had a two 3200 C14 kits that could hit 140ns NP. That was at 1.35V too. This kit is lousy.


----------



## Worldwin

Veii said:


> 15+30 = ?
> Increase tWR to 16 , and CsOdtDrvStr to 30
> likely even 40-20-40-20 CAD_BUS
> else 40-20-30-24
> another one is 60-20-40-20
> 
> 
> VDIMM means nothing, does not relate to heat.
> Amperage does, which is controlled by ClkDrvStr , high procODT and strong RTT_NOM
> 6-2-3 should work, or 6-2-4
> 6-3-3 and 7-3-3 are common, but your preset is not fluent
> Soo you likely dont know if 2T is actually stable, or all was autocorrection


The thing related to summer is about power consumption. My room is small so even 5W adds up.I go so far that I run my GPU at 0.806V which is about 150W down from 240W.
Regarding TRC I have it set to 48 because I remember 45 not working. I can try again. Also I'll try the DrvStr you wrote.


----------



## Taraquin

Worldwin said:


> The thing related to summer is about power consumption. My room is small so even 5W adds up.I go so far that I run my GPU at 0.806V which is about 150W down from 240W.
> Regarding TRC I have it set to 48 because I remember 45 not working. I can try again. Also I'll try the DrvStr you wrote.


Point is that if you plan to keep 48 rc you should do ras 33 since ras+rp=rc. It doesn't add up now  Maybe 46 or 47 works? Just keep the ratio right. As for RFC is scales linear with voltage on B-die. Apply the tips Veii gave you, try and up volt a bit and flat 15 may work and lower RFC WILL work


----------



## Veii

Worldwin said:


> The thing related to summer is about power consumption. My room is small so even 5W adds up.I go so far that I run my GPU at 0.806V which is about 150W down from 240W.
> Regarding TRC I have it set to 48 because I remember 45 not working. I can try again. Also I'll try the DrvStr you wrote.


You can increase tRAS to 34, 36, 38 if it doesn't work
but tRC always has to be tRP + tRAS 

Problem with RTTs is, that you can't know if it's powering or timings related ~ your issue at first
Yet good powering is required for 1T
Soo a chicken and egg problem 

Good advice at first is tWR to be double of tRTP , for a baseline


----------



## Frosted racquet

Veii said:


> VDIMM means nothing, does not relate to heat.
> Amperage does, which is controlled by ClkDrvStr , high procODT and strong RTT_NOM
> 6-2-3 should work, or 6-2-4
> 6-3-3 and 7-3-3 are common, but your preset is not fluent


I've tested these two configs comparing default RTTs and suggested ones, and the difference between them is 1-2°C. The default one is around 55°C in OCCT Memtest and the modified 7-3-3 is around 53°C.















Is there even a point to try and decrease temps, as I'm not getting any errors in tests with DIMMs getting as hot as 60°C?


----------



## Jan87xx

🤔


----------



## Karagra

So this is where I am at atm... no errors ran TestMem5 for 2 hours. Any suggestions?
1.45v on the Dram


----------



## slice313

Taraquin said:


> Micron Rev.E 8/16Gbit vs Rev.J & Hynix DJR 8Gbit
> 
> 
> Want to make a short little write up on the experience I've gained from comparing these different Memory IC's I've attained and used in the same system. Ryzen 3800X (& 4650G) Gigabyte X570 Aorus Xtreme I've just recently attained 2x kits of Kingston HyperX Fury 2x8GB 3600Mhz CL17...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> Try 3800 or 3733 is my first advice. If you plan to use only 3600 try rcdrd 19, rp 19, ras 35, rc 54, rrds 4, rrdl 6, faw 16, rfc 528, wtrs 4, wtrl 8, wr 16, rtp 8, rdwr 10, wrrd 1, scl's 4.


I tried but 3800 Mhz is hard to tune with this kit, even using baseline timings gets me no boot. Auto works but timings are an horror. With your timings I could not boot, maybe my 16 GBs DIMMs cannot play with that values.

I continued improving my timings with 3600mhz, since some thing were not optimal...










I got a small improvement.


----------



## DukeRaoul2010

Guys i'm here with my G-Skill and 5800x. Can anyone suggest a way down with my voltages (not vdimm - the others) and any other settings theat might help me get quicker. How is my ProcODT etc down the right looking? This is still a mystery to me!! I've tried tRRDS and tRRDL on 4 but I get errors)

regarding Vdimm my unify overvolts by .02 to 1.5 so i don't really want to go higher...


----------



## Jan87xx

DukeRaoul2010 said:


> Guys i'm here with my G-Skill and 5800x. Can anyone suggest a way down with my voltages (not vdimm - the others) and any other settings theat might help me get quicker. How is my ProcODT etc down the right looking? This is still a mystery to me!! I've tried tRRDS and tRRDL on 4 but I get errors)
> 
> regarding Vdimm my unify overvolts by .02 to 1.5 so i don't really want to go higher...


Try...
SoC 1.125 V
VDDP 0.900 V
CCD 0.950 V
IOD 1.050 V

RTT'S 6/3/3 or 7/3/3


----------



## pfinch

25 cycles tm5 1usmus config stable. any tips for improvement?
is there a guideline to get a stable 1t gdm off AddrCmdSetup 0 instead of 56 system? (2x16GB Bdies, DR)


----------



## Jan87xx

pfinch said:


> View attachment 2558742
> 
> 
> 25 cycles tm5 1usmus config stable. any tips for improvement?
> is there a guideline to get a stable 1t gdm off AddrCmdSetup 0 instead of 56 system? (2x16GB Bdies, DR)


VDIMM?


----------



## pfinch

Jan87xx said:


> VDIMM?


i'm at 1.5vdimm .. so the key is to increase vdimm to get "real" 1t?


----------



## KedarWolf

Real 1T usually refers to GDM off. Having 56 doesn't make it not real 1T.


----------



## Taraquin

pfinch said:


> View attachment 2558742
> 
> 
> 25 cycles tm5 1usmus config stable. any tips for improvement?
> is there a guideline to get a stable 1t gdm off AddrCmdSetup 0 instead of 56 system? (2x16GB Bdies, DR)


Do you need setup times? 
RAS 28
RC 42
RFC 256 (maybe lower can work) 
RTP 7 (half WR)


----------



## pfinch

Taraquin said:


> Do you need setup times?
> RAS 28
> RC 42
> RFC 256 (maybe lower can work)
> RTP 7 (half WR)


Thanks!
DrvStr, Setup, Proc and RTT settings looking good so far?


----------



## Taraquin

pfinch said:


> Thanks!
> DrvStr, Setup, Proc and RTT settings looking good so far?


Try 24 20 24 24, 30 20 24 24, 40 20 24 24 or 40 20 30 24 for DrvStr. Your IOD volt may be too low, I would consider raising it slightly, check latency in aida, if it improves with higher IOD.


----------



## DukeRaoul2010

Jan87xx said:


> Try...
> SoC 1.125 V
> VDDP 0.900 V
> CCD 0.950 V
> IOD 1.050 V
> 
> RTT'S 6/3/3 or 7/3/3


Thanks for these. Will the RTTs give me more stability or are they just something to tune for speed in and of themselves? In my BIOS (X570 Unify) I can't see values that match 6/3/3 only values in Ohms? Would a value roughly 6x my ProcODT be correct, and 3x for the others?

Are the VDDP and CCD values the ones that should have the 0.05 difference?

Thanks again for the help

Duke


----------



## Jan87xx

DukeRaoul2010 said:


> Thanks for these. Will the RTTs give me more stability or are they just something to tune for speed in and of themselves? In my BIOS (X570 Unify) I can't see values that match 6/3/3 only values in Ohms? Would a value roughly 6x my ProcODT be correct, and 3x for the others?
> 
> Yes it can improve stability.
> 
> 
> 
> 
> 
> 
> 
> 
> Are the VDDP and CCD values the ones that should have the 0.05 difference?
> 
> Ur VDDP is too high, the rest is a good to start with.
> 
> Thanks again for the help
> 
> Duke


----------



## pfinch

Taraquin said:


> Try 24 20 24 24, 30 20 24 24, 40 20 24 24 or 40 20 30 24 for DrvStr. Your IOD volt may be too low, I would consider raising it slightly, check latency in aida, if it improves with higher IOD.


Thank you! So the RTTs and procODT are good? (just auto settings on Asus Ch8)


----------



## Taraquin

pfinch said:


> Thank you! So the RTTs and procODT are good? (just auto settings on Asus Ch8)


They probably work fine like that, see if you encounter errors or not.


----------



## Audioboxer

Replacement drive arrived... THERE WILL BE NO WATERCOOLING  Though the watercooler in me hates seeing a temp of 40 degrees!

Read seems a bit dodgy in the samsung app, drive is supposed to be 7000MB/s max, but write is where it should be, Corsair state 6850MB/s.


----------



## Bloax

Just like AIDA likes to read into cache, so too this test may be reading into the drive DRAM cache.


----------



## kaiyrzhans

Hello everyone.  i'm super noob on RAM overclocking, but really want to tweak it to use at least 90% potential. Will appreciate any help, thank you.


----------



## Blackfyre

Audioboxer said:


> View attachment 2558841
> 
> 
> Replacement drive arrived... THERE WILL BE NO WATERCOOLING  Though the watercooler in me hates seeing a temp of 40 degrees!
> 
> Read seems a bit dodgy in the samsung app, drive is supposed to be 7000MB/s max, but write is where it should be, Corsair state 6850MB/s.


This program always breaks my Seagate External drive. Happened for the past like 6 years with 3 different operating systems. So, I never end up using it.

Install it, Seagate External drive stops working unless I unplug and plug it in manually after every boot.

Uninstall, all is good.

Never found a solution to it and gave up lol


----------



## Frosted racquet

I think I'm done with tightening timings. tCL 13 doesn't boot, GDM off @1T doesn't boot, tRDWR <9 doesn't boot. tCKE is 0 by motherboard auto setting, don't know if it's good.

Next up is trying to figure out sweet spot voltages for 3800/1900 IF, since it is throwing WHEA 19 errors.

If you have any suggestions for improving the timings feel free to suggest what to try next. Really unfortunate that the CPU controller isn't appreciative of 1900MHz by default.








EDIT:
Ok, tried 3800 again, but no combination of VSOC/VDDP/VDDG/VDD18 seems to eliminate WHEA19 errors. Are those voltages the only thing affecting IF stability?
Here's the combos I tried:


Spoiler: What I tried



VSOC 1.1v
VDDP 0.9v
VDDG CCD 1v
VDDG IOD 1.05v
-FAIL

VSOC 1.125v
VDDP 0.9v
VDDG CCD 1v
VDDG IOD 1v
-FAIL

VSOC 1.125v
VDDP 0.9v
VDDG CCD 0.950v
VDDG IOD 1v
-FAIL

VSOC 1.125v
VDDP 0.9v
VDDG CCD 1v
VDDG IOD 1.05v
-FAIL

VSOC 1.1v
VDDP 0.95v
VDDG CCD 1v
VDDG IOD 1v
-FAIL

VSOC 1.125v
VDDP 0.95v
VDDG CCD 1v
VDDG IOD 1v
-FAIL

VSOC 1.125v
VDDP 0.95v
VDDG CCD 1v
VDDG IOD 1.05v
-FAIL

VSOC 1.125v
VDDP 1v
VDDG CCD 1v
VDDG IOD 1.05v
-FAIL

VSOC 1.1v
VDDP 0.9v
VDDG CCD 1v
VDDG IOD 1v
VDD18 1.85v
-FAIL

VSOC 1.125v
VDDP 0.9v
VDDG CCD 1v
VDDG IOD 1v
VDD18 1.85v
-FAIL

VSOC 1.125v
VDDP 0.9v
VDDG CCD 1v
VDDG IOD 1v
VDD18 1.9v
-FAIL


Any advice please?


----------



## sealxohd

Since my FCLK is somewhat decent, Im aiming for 2066 1T gdm off. I got 2T completly satble. 1T GDM off with FCLK at 1900 and mclk at 2066 runs fine, with the same timings in 1:1 mode I get BSODs after 4% of Karhu. Has anyone an idea?

Same behaviour for 7/3/3. 40/20/24/24 is the best set of CADs.


----------



## Nighthog

Anyone know the cause of this error?

I've been getting it consistently now for 5100+ speeds for a long time.
I got it with my 3800X and still getting this error with the 5800X3D on the X570S Unify-X MAX motherboard when pushing my Memory kits a little harder than usual.

It takes 30min to ~1 hour depending on memory settings but can't avoid it for some reason. Can't figure out the issue with it. 
One thread or several can end up with it. Always the same error message but different cores.


----------



## Audioboxer

Blackfyre said:


> This program always breaks my Seagate External drive. Happened for the past like 6 years with 3 different operating systems. So, I never end up using it.
> 
> Install it, Seagate External drive stops working unless I unplug and plug it in manually after every boot.
> 
> Uninstall, all is good.
> 
> Never found a solution to it and gave up lol


Just installed it to see if this 970 Evo Plus I bought needed a FW update, but it was up to date. Kept it installed as it seems quite decent. Compared to the Corsair SSD Toolbox, it's amazing. That piece of Corsair software is soo bad. If you thought iCUE was dodgy, SSD Toolbox is an embarrassment.

I would normally use HWINFO for drive monitoring, but my problem is my external drive doesn't go to sleep when HWINFO is monitoring it :/ I just use my external for backup, so it's annoying having it running 24/7. So I had to turn HWINFO drive monitoring off.

Tbf, this app seems to keep my external running as well, so its closed after use, no running in taskbar.


----------



## majsterz

how to make tphyrdl timing even on both sticks? currently is 26/28


EDIT: i fixed it by swapping memory in slots or changing trfc 2/4 to auto


----------



## Milamber

I have just purchased a 32Gb kit to install in my X570S Aorus Master, I was wondering if I need to tweak them or just leave them at stock?

I got the 3600Mhz: CL14-15-15-35 

They are these: XTREEM ARGB WHITE DDR4 DESKTOP MEMORY│TEAMGROUP (teamgroupinc.com)


----------



## ArchStanton

@Nighthog for me it wound up being a corrupted operating system. Wipe and reinstall is the only thing I found that fixed it.


----------



## Blackfyre

Milamber said:


> I have just purchased a 32Gb kit to install in my X570S Aorus Master, I was wondering if I need to tweak them or just leave them at stock?
> 
> I got the 3600Mhz: CL14-15-15-35
> 
> They are these: XTREEM ARGB WHITE DDR4 DESKTOP MEMORY│TEAMGROUP (teamgroupinc.com)


No one here is going to tell you not to tweak  lol

That's a great kit that will probably overclock really well if it's already CL14 at 3600Mhz with those timings too.

Which CPU do you have?

First thing to try is to push FCLK to 1900 and RAM to 3800 Mhz, that should boot with CL14 too. Then you start changing all the secondary timings and tweaking them from auto to lowest values before crashing.

You need a lot of free time and patience. And also, something I learnt recently when the system does not boot after putting timings too tight. Make sure you shut down first by holding the power button, before you press the BIOS Reset key at the back of the motherboard. Don't reset BIOS without shutting down.


----------



## Nighthog

Not sure what was causing my TM5 crashes earlier but just trying some "safe" and "stable" might have fixed it as well.

Finally got CL17 to pass TM5 @ 5100Mts. Took almost a week to go from CL18 --> CL17 stability. Might been trying too low values for tRP for the whole time.

tRCDWR will be next to be tied down if this is really working now.

MEM VTT = 0.650V for this, (zentiming reads MEM_VREF)


----------



## TimeDrapery




----------



## Frosted racquet

@TimeDrapery so what was the cause for OCCT errors? I see you're running 2x8 instead of 4x8 now. Bad RAM?


----------



## mvdev0

Hey all,

it's my first post here, I'm glad a channel like this exists.


After reading, and hopefully right understand, I implement settings to my RAM configuration.

I'm reading mainly









MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper


C# WPF to automate HCI MemTest. Contribute to integralfx/MemTestHelper development by creating an account on GitHub.




github.com




and

__
https://www.reddit.com/r/overclocking/comments/ahs5a2

Today I reset the previous settings because I can't get the system stable anymore,
using TM5 with [email protected] config.

So I start again with D.O.C.P. profile, hardcode that values, and measure them with AIDA64 v6.70.6.

Than I tighten only the primary timings from 16-16-16-16-36-85 to 14-14-14-14-28-42, and raise
VDIMM 1.35V to 1.45V.. all this is TM5 stable at 3600MT/s and 1800MHz FCLK.

Now up to my question:

After comparing both, I realize that the CL14 settings are not worth mentioning faster.

read 54.802 -> 54.833
write 53.352 -> 53.699
copy 50.388 -> 50.759

I'm doing all the time 3 measurements and round them.

Is this what we can expect going from CL16 to CL14?

And why is tRAS and tRC from D.O.C.P. profile -36-85, and not -32-48, as explained in both
and more documents?

I think there is something I really missunderstood.. :/

Here are the outputs from "ZenTimings".. they are both identical, only the primarys and tCWL
are different.



















If this is really the truth, I consider running CL16 with a much lower VDIMM and have
a focus to the secondaries and tertiaries, especially tRFC.

Thanks for reading this and stay healthy so far.


----------



## Taraquin

Nighthog said:


> Not sure what was causing my TM5 crashes earlier but just trying some "safe" and "stable" might have fixed it as well.
> 
> Finally got CL17 to pass TM5 @ 5100Mts. Took almost a week to go from CL18 --> CL17 stability. Might been trying too low values for tRP for the whole time.
> 
> tRCDWR will be next to be tied down if this is really working now.
> 
> MEM VTT = 0.650V for this, (zentiming reads MEM_VREF)


Impressive! Do you see performance scaling vs 3800/1900? That VDDP looks borderline safe...


----------



## TimeDrapery

Frosted racquet said:


> @TimeDrapery so what was the cause for OCCT errors? I see you're running 2x8 instead of 4x8 now. Bad RAM?


No clue, I think the system just hates it for whatever reasons (noise? Bad signal integrity with four DIMMs?)

I didn't reinstall OCCT or change anything... I reflashed to F14c and completely cleared CMOS/NVRAM just in case that was the issue ("old" settings) but I never got it to survive more than a minute or two under OCCT

2×8GB is more than sufficient for me and it's tightening up pretty well

The whole reason I revisited the mem OC was to reduce voltages and, unfortunately, I see there's no gains in performance/stability for CO with the lesser voltages 😂😂😂😂😂


----------



## Frosted racquet

@mvdev0 RAM frequency affects read/write/copy bandwidth, timings have little influence over that.

XMP defined timings are pretty bad, but bad in a performance sense, as most of the time they will not produce memory errors in combination with bad memory controllers on CPUs and bad motherboard design. Compatibility is more important for XMP than tight timings.


----------



## Nighthog

Taraquin said:


> Impressive! Do you see performance scaling vs 3800/1900? That VDDP looks borderline safe...


VDDP needs to be 1.160-1.200V for 5100Mts looking at both my 3800X & 5800X3D where the X3D wants more than what my 3800X wanted to post 5100+ reliably. 

1.200V VDDP was needed to even Post/train 5200Mts for my 3800X while I haven't managed to get that to work yet with the 5800X3D sadly. Needing about the same to do 5100Mts only.

Sadly scaling wise it's not good. 4000/2000 1:1 will outperform this if your sample is good enough to do it without WHEA.
This is basically 3800/1900 parity for performance 
Though I hope there are some benefits for the extra frequency. But you really want even more frequency to get the benefits to start show. But then you hit the limits of what frequency these CPU's can do.

Really hard to get these to post/train 5200Mts with the kits of memory I've had and tried.


----------



## mvdev0

@*Frosted racquet *Hey, thank you for your respond.

That is what I had suspected, thank you for confiming this.

If I decide using CL16, is 16-16-16-16-32-48 right calculated, or is this setting to strange?


----------



## Frosted racquet

Yes, it's correctly calculated, in your case tRC = tRP + tRAS II 48 = 16 + 32

Regarding further tweaking, I would disable GDM/Gear Down Mode and set 2T Command Rate, it is easier to test stability with it disabled. Try and see if 3800 works with those 16-16-16 timings, and make sure FCLK is set to 1900. Check if you're getting WHEA errors in Event Viewer/HWiNFO


----------



## mvdev0

Frosted racquet said:


> Check if you're getting WHEA errors in Event Viewer/HWiNFO


Ohh, thank you, never did.. I will do from now.

I do a TM5 ([email protected], only 250%) run with 16-16-16-16-32-48, without of errors, until TM5, like it did
with the posted CL14 settings, opens multiple window with










This appears not at the beginning but ~60 minutes after, short before the third cycle.

I checked WHEA error in HWiNFO, there is none.

What I notice too while running TM5, the desktop icons partially got a black background (until I move the mouse over them)
and window borders are damaged.

Is this all because the RAM settings are to tight?

I never found an answer about this.. would be so helpful.  _aaargs_

This are the timings I'm running now










.. and this is the RAM, btw










After this, I try 3800/1900.. would be really nice this will go stable.


----------



## Frosted racquet

Regarding TM5 error, is your Windows installation older or freshly installed? Are you running an overclock on the CPU?


----------



## mvdev0

Frosted racquet said:


> Regarding TM5 error, is your Windows installation older or freshly installed? Are you running an overclock on the CPU?


The installation is about two years old, but with all updates.. of course.

And sorry, I forget to write.. there is no OC on CPU, but GPU is 0.1V undervolted.

EDIT: Not anymore, AMD driver resets itself to default settings.


----------



## Frosted racquet

There's a user on the previous page with a similar TM5 error [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
and another user said the windows installation being corrupted is what caused it for him [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
Maybe try with another config instead of Extreme1, 1usmus and Universal2 are OK too just to check.


----------



## mvdev0

Thanks you so much, you are so fast in responding to my questions.. sorry, that is I'm afraid of.. some others posting
the same and I dont read the whole article.

Now where I'm lower than 1.45V VDIMM, i try Universal2 config.


----------



## mvdev0

ArchStanton said:


> @Nighthog for me it wound up being a corrupted operating system. Wipe and reinstall is the only thing I found that fixed it.


A 'sfc /scannow' can't solve this?


----------



## mvdev0

I do a run with '[email protected]' config on TM5, but with the same "TM5 crash! Thread Error Handler".. it appears on two threads, no error within TM5,
but stops working minutes later (no workload at taskmanager) while time elapse in TM5.

Now, after repeating, TM5 outputs the same error directly after starting.

mmh..


----------



## TimeDrapery

Tightened subs, dropped VDDG/VDDP


----------



## TimeDrapery

Y-cruncher failed during its fourth iteration so I increased CLDO VDDP to 850mV from 800mV


----------



## Prophet4NO1

Had to bump voltage a tad on the DIMMs but got 1 hour of Aida stress test to finish. Before the bump, 20-40 min was all it would manage. Two sticks peaked at 52c. Other two got up to 47-48c. They sat at those temps for most of the test. Took about 10 min to get to those temps.


----------



## Milamber

Blackfyre said:


> That's a great kit that will probably overclock really well if it's already CL14 at 3600Mhz with those timings too.
> 
> Which CPU do you have?


Thanks, my CPU is a 5950X and I have an X570s Aorus Master, I cool the CPU with a Arctic Liquid Freezer II 360.


----------



## 67091

Hey guys 
I keep getting ERROR 1 with TM5 (absolut) after 2 hours, it's really Fing me off.
What does that error mean?
Kind Regards


----------



## TimeDrapery

Much gooder, I think I'll play with the latest Hydra release now


----------



## Theo164

angushades said:


> View attachment 2559018
> 
> 
> Hey guys
> I keep getting ERROR 1 with TM5 (absolut) after 2 hours, it's really Fing me off.
> What does that error mean?
> Kind Regards


Check CAD_BUS ohm values, maybe 20Ω is low...


----------



## 67091

Theo164 said:


> Check CAD_BUS ohm values, maybe 20Ω is low...


I’ve done all 24 and it’s the same results.


----------



## domdtxdissar

KedarWolf said:


> New Window 10 Bench ISO Link, much improved with new instructions.
> 
> 
> 
> 
> 
> 
> Win10BenchISO.zip
> 
> 
> 
> 
> 
> 
> 
> drive.google.com


Testing your new windows build and have a few questions 

How do i permanent disable windows update ?


> Double-click the RunAsTi.reg file and install it to the registry.
> 
> Right-click and run the BenchOSServicesDisable.cmd as Trusted Installer and next the Set-ProcessMitigation.cmd as Trusted installer.


Should i run those everytime i start to OS, or is it a one time thing ?


----------



## mvdev0

Hey,

the system now is running TM5 ([email protected], 250%) without "Thread Error Handler" crash.
Most tests in the past won't, but the D.O.C.P. settings. I need to run TM5 1000%, but 250% without
is nice for now.

I setup a fixed VSOC of 1.05V, VDDG CCD/IOD both to 1.0V, VDDP 0.950V and CPU/SOC LLC Level3.

It's all what DRAM Calculator suggest, but there are many documents pointing to a higher voltage for VSOC.

HWiNFO measures 1.044 VSOC, it looks like SOC LLC affecting that fixed voltage, at LLC 2 it's about 1.0375V.










EDIT : With TM5 ([email protected], 500%) i got a crash after ~50 minutes, during the change to cycle 2.


----------



## Akex

People a question about tRFC for you.
Can I calculate the tRFC number on the fact that I want to have 300ns, for 300ns at 4733 I need:

tRFC1 = 710
tRFC2 = 527
tRFC4 = 325

or do I have to respect the rule tRC * X


----------



## Veii

Akex said:


> People a question about tRFC for you.
> Can I calculate the tRFC number on the fact that I want to have 300ns, for 300ns at 4733 I need:
> 
> tRFC1 = 710
> tRFC2 = 527
> tRFC4 = 325
> 
> or do I have to respect the rule tRC * X
> 
> 
> View attachment 2559064


You don't "need" 300ns
Memory does not follow real world clock
It follows cycle based integers
Pick whatever runs for you ~ thing i provided only helps assisting the prediction
It's low priority soo pick something you feel good about
If too low, pick the next higher bigger value

Reports about micron or hynix not doing "300" ns , is equal user observation
As prediction you get on the sheet that can work
They move somewhere between 270-350ns for JEDEC.
You can never know without trying, but "300,310,320,330" fixed nice round values ~ are humans interpretation
It's not following reality, as memory does again "not move on the same worldclock" and never is a perfect non decimal value (they are 12-14 decimal digits)


domdtxdissar said:


> How do i permanent disable windows update ?


Maybe helpful so we play on the same ground (i'm not using the iso)


https://github.com/madbomb122/BlackViperScript/archive/refs/heads/master.zip


extract, remove .txt extension, put changes to "all services" then on custom settings (browse) load
Disabled is:
~ FAX / Printer
~ Microsoft store stuff & XBOX services
~ WinUpdate
~ Touch keyboard & Plug 'n Play
and couple more things
Wifi works, microphone/cam works
~i daily this~

Things you don't need, can be modified in the Service List
and if something doesn't work ~ you can change everything back to all services ~ default config (resets everything)

Else (ontop) check WPD


----------



## Prophet4NO1

Based on my info above, how much more do you guys think these sticks can give? DIMM voltage is 1.42v to get the Aida test done. I will likely test some other sthings as well, but usually Aida for 1 hr has left me having zero issues in every day life. So, feeling pretty good so far.


----------



## TimeDrapery




----------



## PJVol

@TimeDrapery
tRCDWR 8 and loosened EDC limit may improve Copy (200-300) and latency(~0.5ns)


----------



## sealxohd

I will settle with this as daily. Maybe I will try lower tRFC. IDK why GDM is such a pain this time. In 2:1 GDM off is stable.


----------



## TimeDrapery

PJVol said:


> @TimeDrapery
> tRCDWR 8 and loosened EDC limit may improve Copy (200-300) and latency(~0.5ns)


Good look! I'll give em a try here momentarily! Thanks!


----------



## andremoreira6215

mvdev0 said:


> I do a run with '[email protected]' config on TM5, but with the same "TM5 crash! Thread Error Handler".. it appears on two threads, no error within TM5,
> but stops working minutes later (no workload at taskmanager) while time elapse in TM5.
> 
> Now, after repeating, TM5 outputs the same error directly after starting.
> 
> mmh..


Try with 1usmus config, errors was desmistified in a excel from vei


----------



## hazium233

Blackfyre said:


> Yeah I loved the detailed response. But I still did not understand whether that is just information (general), or AIDA 64 giving advice as to values I might need to change?
> 
> I assume it's just general information. As if it was issues, someone would have noticed & said so.


Sorry for taking so long. AIDA is just trying to tell you the current set values. It isn't a recommendation. It is using generic terminology instead of the Ryzen timings.


----------



## ArchStanton

mvdev0 said:


> A 'sfc /scannow' can't solve this?


I did not in my particular case.


----------



## xProlific

Been testing for 3 days and I cannot get Karhu to finish error free. The image below is from a test with DOCP enabled. I am noticing I fail around 1500% usually. 

So far I have tried reseating the RAM and playing with timing and voltages but If DOCP is failing then I doubt this is going to get me anywhere. I have also tried walking the RAM up to the rated speed and noticed that I couldn't get a post a from 3200-3266. Last thing I tried was running the kit overnight at stock with no DOCP enabled but that was error free. 

I was previously using the kit with a 5900X @3666, was never able to get the kit to run at 3800 or 3733 without WHEA errors but on the 5800X3D I am not seeing WHEA errors. That said although the 5900X was initially stable at 3666 I was beginning to see memory error weirdness a week prior to swapping that processor out. 

I am about to submit an RMA unless anyone has any suggestions. It sucks for such an expensive kit to go to the landfill but at this point that is looking like the only option.


----------



## Frosted racquet

xProlific said:


> I am about to submit an RMA unless anyone has any suggestions.


Try sticking a fan over the RAM for cooling. Have you monitored RAM temps at all?


----------



## LazyGamer

Frosted racquet said:


> Try sticking a fan over the RAM for cooling. Have you monitored RAM temps at all?


For ASUS boards that don't report VDIMM or memory temperature... is there an 'accepted' way to measure this?

I have some probes coming to stick on the DIMMs and already have fans on them - just never really used thermal probes before.


----------



## Frosted racquet

LazyGamer said:


> For ASUS boards that don't report VDIMM or memory temperature...


ASUS boards have no sensor in HWiNFO for RAM temps? That's really unfortunate, I thought that the motherboard has nothing to do with the sensor on the RAM itself...


----------



## MrHoof

LazyGamer said:


> For ASUS boards that don't report VDIMM or memory temperature... is there an 'accepted' way to measure this?
> 
> I have some probes coming to stick on the DIMMs and already have fans on them - just never really used thermal probes before.


VDIMM is missing on some boards like my x570i but temperature depends on the DIMMs normaly if they have a temps sensor it will will be reported in HWInfo


----------



## LazyGamer

Frosted racquet said:


> ASUS boards have no sensor in HWiNFO for RAM temps? That's really unfortunate, I thought that the motherboard has nothing to do with the sensor on the RAM itself...


That or the memory itself lacks the reporting ability. I have quite a few DDR4 kits that don't have temp sensors themselves, so I could certainly be wrong on the temp sensing part. I'll admit to being new to AMD, some of the differences with Intel setups take getting used to.

[not that there aren't Intel boards that aren't awkward - have a Biostar Z590 board used for benchmarking other components that doesn't even report VCore in a way that HWINFO64 can read, have to use CPU-Z...]


----------



## xProlific

Frosted racquet said:


> Try sticking a fan over the RAM for cooling. Have you monitored RAM temps at all?


As been said I don't have a way to measure the RAM temp. I have an AIO on my cpu pulling most of the hot air out of my case through a triple rad at the top with an additional three noctua fans brining in fresh air at the front of the case. Air coming out the rear does not feel much hotter than room temp so I don't think there is much of a cooling issue.


----------



## andremoreira6215

xProlific said:


> Been testing for 3 days and I cannot get Karhu to finish error free. The image below is from a test with DOCP enabled. I am noticing I fail around 1500% usually.
> 
> So far I have tried reseating the RAM and playing with timing and voltages but If DOCP is failing then I doubt this is going to get me anywhere. I have also tried walking the RAM up to the rated speed and noticed that I couldn't get a post a from 3200-3266. Last thing I tried was running the kit overnight at stock with no DOCP enabled but that was error free.
> 
> I was previously using the kit with a 5900X @3666, was never able to get the kit to run at 3800 or 3733 without WHEA errors but on the 5800X3D I am not seeing WHEA errors. That said although the 5900X was initially stable at 3666 I was beginning to see memory error weirdness a week prior to swapping that processor out.
> 
> I am about to submit an RMA unless anyone has any suggestions. It sucks for such an expensive kit to go to the landfill but at this point that is looking like the only option.
> 
> View attachment 2559180


I think the cause it's the quad kit you are using. Try with only 2 slots of ram


----------



## xProlific

andremoreira6215 said:


> I think the cause it's the quad kit you are using. Try with only 2 slots of ram


Do you think the IMC on the CPU can't handle it? I might pickup a dual rank kit 2x16 to test with, do you think that would be easier on the IMC?

Not that it is any better but at least with my 5900X WHEA errors made it clear it was the IMC with the 5800X3D I am not as sure. The hole at 3200 is weird which leads me to believe it is not the be the IMC. Also I haven't been able to boot if I raise tCL above 14.


----------



## hazium233

xProlific said:


> That said although the 5900X was initially stable at 3666 I was beginning to see memory error weirdness a week prior to swapping that processor out.


Best would be to test the dimms one at a time since you mentioned this. It could be that one is dying an early death and that is why you are seeing annoying behavior with regard to posting and intermittent errors.

I had a dimm that died an early death, and it tested at spec originally, but progressively lost voltage and frequency tolerance. It still passed at JEDEC 2666, but would not pass at even 2933 1.35 16-18-18 when I RMAd.


----------



## xProlific

hazium233 said:


> Best would be to test the dimms one at a time since you mentioned this. It could be that one is dying an early death and that is why you are seeing annoying behavior with regard to posting and intermittent errors.
> 
> I had a dimm that died an early death, and it tested at spec originally, but progressively lost voltage and frequency tolerance. It still passed at JEDEC 2666, but would not pass at even 2933 1.35 16-18-18 when I RMAd.


Alright I'll test 1 by 1 with DOCP enabled and see how that goes.


----------



## 67091

Does anyone run Cl13 on bdie at 3600?


----------



## Danny.ns

xProlific said:


> Been testing for 3 days and I cannot get Karhu to finish error free. The image below is from a test with DOCP enabled. I am noticing I fail around 1500% usually.
> 
> So far I have tried reseating the RAM and playing with timing and voltages but If DOCP is failing then I doubt this is going to get me anywhere. I have also tried walking the RAM up to the rated speed and noticed that I couldn't get a post a from 3200-3266. Last thing I tried was running the kit overnight at stock with no DOCP enabled but that was error free.
> 
> I was previously using the kit with a 5900X @3666, was never able to get the kit to run at 3800 or 3733 without WHEA errors but on the 5800X3D I am not seeing WHEA errors. That said although the 5900X was initially stable at 3666 I was beginning to see memory error weirdness a week prior to swapping that processor out.
> 
> I am about to submit an RMA unless anyone has any suggestions. It sucks for such an expensive kit to go to the landfill but at this point that is looking like the only option.
> 
> View attachment 2559180


 Did you set tRRDS, tRRDL, tFAW, tRFC,2,4 according to SPD? I know my DOCP does not set those, I have to do it manually. You can see the SPD info in your BIOS and it will list what those timings should be for your XMP profile.


----------



## Blackfyre

Just saw this on Reddit earlier, would be interesting to look into it:

*Quote directly via reddit thread:*


> x570 Aorus Master rev1 & 5900x
> 
> Anything higher than 1900IF would generate about 300 Whea 19 warnings every 2mins. CPU / MEM stable at 4000cl16.
> 
> I noticed reduced NIC bandwith & Destiny 2 "contacting server" when using 2000IF.
> 
> Switched to 2.5Gb Realtek NIC & to my suprise no whea 19 warnings.
> 
> Something wrong with that PCIe/Intel NIC firmware when using higher IF speeds.
> 
> Posting here, might help others if you have this mobo / whea 19 warnings but are 100% stable.




__
https://www.reddit.com/r/Amd/comments/ugyq37


----------



## nikobobich

After spending a week now I finally figured out the ram timings and voltages and think I understand how it works to a degree below is what I came up with so far. 3733 is most stable on my C14 Gskill 3600 ram


----------



## nikobobich

How do my timings look Im open for improvements and suggestions just got this stable over the past few nights and over 12 hours on kahur and anta777 absolute tests. Let me know guys Thank you

VDIMM's at 1.5 and they are samsung bdie's


----------



## Rexbag

Blackfyre said:


> Just saw this on Reddit earlier, would be interesting to look into it:
> 
> *Quote directly via reddit thread:*
> 
> 
> __
> https://www.reddit.com/r/Amd/comments/ugyq37


Hmm, I'm using the Aorus Master and never had any luck with >1900IF. I may have to use the 2.5GbE and see if that makes any difference. Would be pretty awesome if that actually worked. I thought I'd tried everything, but don't remember trying this.


----------



## xProlific

Danny.ns said:


> Did you set tRRDS, tRRDL, tFAW, tRFC,2,4 according to SPD? I know my DOCP does not set those, I have to do it manually. You can see the SPD info in your BIOS and it will list what those timings should be for your XMP profile.


I did and had no luck. I also tried loosing timings to 3800 CL16 (originally I was haing trouble raising tCL but I got it to work) but I still got an error at around 1800%.

I am still working on testing each stick individually, first stick passed I will test the others and will hopefully have a report by tomorrow. I have also ordered a 2x16 3800 kit that I plan on testing this weekend to see if I can run that without errors.


----------



## GraveNoX

I need some advice to get my RAM to 3600Mhz, RAM is Crucial Ballistix BL2K32G32C16U4B 2x32GB Kit (64 GB total) 3200mhz 16-18-18-36. They are dual rank Micron B-Die, august 2021.
Motherboard is asus crosshair vi hero x370 with 8503 bios. CPU is Ryzen 5800X
I used dram calculator 1.7.3 to get speeds for 3400Mhz, I choose Zen 2, A0/B0, 2 rank, 2 dimm modules, b350/x370, 100 bclk and Micron E/H-die (because the software is not updated for 16GB B-die) and it's stable with Fast preset at 3400Mhz. I get 64.4 ns in Aida64. 49.1 gb/s read, 27.2 gb/s write, 48.2 gb/s copy.
But I get no post with the settings for 3600mhz, is there any setting that prevent the system to not post?
What should I try?
And sorry I haven't followed this thread at all, I just got this kit today and I'm clueless on what to try to get 3600. I don't expect more than 3600 for dual rank.
Thank you.


----------



## mvdev0

Hey,

I have some strange problems with my ASUS ROG Strix X570-E Gaming Board.

Last days I want tighten the RAM configuration, but can't get the system stable.

Yesterday I decide going to D.O.C.P. 1800MHz profile with a 1:1 FCLK setup again.
.. but the system isn't stable anymore, the system resets like I press the button
without any messages.

Not every time, this session it's online since ~15 minutes, the boot befor it was
less than 5 minutes until sporadically reboot.

I'm using the ASUS BIOS v4202 with AGESA V2 PI 1.2.0.6b.

Now I found few informations other do have problems with this version too
and they went back to AGESA V2 PI 1.2.0.3 Patch C.

Is this problem here also known?


----------



## mvdev0

I go back to AGESA V2 PI 1.2.0.3 Patch C, there are many others having problems.

At the day im flashing the currently used BIOS I noticed the "b" in the AGESA version,
but because the BIOS itself wasn't declared as beta, I go that way..


----------



## Audioboxer

Blackfyre said:


> Just saw this on Reddit earlier, would be interesting to look into it:
> 
> *Quote directly via reddit thread:*
> 
> 
> __
> https://www.reddit.com/r/Amd/comments/ugyq37


Veii mentioned before that one of the reasons we get WHEA is because of the motherboard components like network and so on. I remember months ago turning off mobo WIFI module and even trying to disable the ethernet to see if I could stop WHEA errors lol.


----------



## 67091

Hi guys I'm sorry to be a pain in the ass but I'd really like to get this stable. Is my timing too tight or what's the problem.


----------



## sealxohd

angushades said:


> Hi guys I'm sorry to be a pain in the ass but I'd really like to get this stable. Is my timing too tight or what's the problem.
> View attachment 2559294


Did you try different CADs or different setup timings?

tRTP 6 may also be a bit to tight


----------



## Bloax

angushades said:


> Hi guys I'm sorry to be a pain in the ass but I'd really like to get this stable. Is my timing too tight or what's the problem.
> View attachment 2559294


Judging by the error #4 and all the timeout related errors, it's probably asking for tCKE 7 first


----------



## 67091

sealxohd said:


> Did you try different CADs or different setup timings?
> Yeah I did 24/20/24/24
> tRTP 6 may also be a bit to tight


Ok I'll give it a try.


----------



## 67091

Ok so this what I have stable but the Tfrc is pretty high.What I would really like is to go 15 flat and the Tfrc lower but it doesn't matter if I change cad bus to 24 or anything just comes Up with errors. What should I relax and then go to 15 flat?


----------



## TimeDrapery

This is neat

On my Mini-ITX mobo I've got tPHYRDL training to 26/28 when tRDWR and tWRRD are set to Auto with an even tCL but it trains 26/26 when I manually set 7/3 with an even tCL

No change to voltages needed but in my ATX mobo it's not possible to boot 7/3 with an even tCL

Good to know

Great performance as well


----------



## Taraquin

angushades said:


> Hi guys I'm sorry to be a pain in the ass but I'd really like to get this stable. Is my timing too tight or what's the problem.
> View attachment 2559294


Probably wrong DrvStr, try 24 20 24 24, 30 20 24 24, 40 20 24 24 or 40 20 30 24. Only the ladt one makes 1t errorfree on my setup. I don't think I've seen flat 20 work on 1t gdm off b-die dual rank.


----------



## nikobobich

TimeDrapery said:


> This is neat
> 
> On my Mini-ITX mobo I've got tPHYRDL training to 26/28 when tRDWR and tWRRD are set to Auto with an even tCL but it trains 26/26 when I manually set 7/3 with an even tCL
> 
> No change to voltages needed but in my ATX mobo it's not possible to boot 7/3 with an even tCL
> 
> Good to know
> 
> Great performance as well
> 
> View attachment 2559323
> 
> View attachment 2559322


Very nice bro thats good ram bet it runs hot though


----------



## Assarad

Hello,

i've got 2 identical 32GB 3200C15 Samsung B-Die Kit (F4-3200C15-16GTZ). I'm already using and ocing the better kit (Other kit needs 0.01 to 0.02 more Vdimm for the same/slightly worse settings).
How would I improve those settings to get more performance out of it? It's a B0 PCB. I'm fairly new to RAM OC
These are the current settings.

VDIMM: 1.44








These are the settings that were TM5 Anta777 absolute stable (not fully done?), by literally taking a value lowering it and then run karhu/tm5 anta777
VDIMM 1.45


----------



## Zeryth

Any Advice to tighten it more? rev4 4x8


----------



## TimeDrapery

nikobobich said:


> Very nice bro thats good ram bet it runs hot though


Thanks dude

42.0°C top temps are not too bad for the tiny case, my open air test bench tops out around 36-37°C


----------



## Taraquin

Zeryth said:


> View attachment 2559384
> 
> Any Advice to tighten it more? rev4 4x8


Lower RC maybe, 52-56 may work, keep difference RAS+RP=RC so raise RAS. 

RFC may do 560, 552, 544 or 536

I would consider raising CWL to 16 and lowering RDWR to 10, 9 or 8. 

WR 12 (RTP X 2).


----------



## Zeryth

Taraquin said:


> Lower RC maybe, 52-56 may work, keep difference RAS+RP=RC so raise RAS.
> 
> RFC may do 560, 552, 544 or 536
> 
> I would consider raising CWL to 16 and lowering RDWR to 10, 9 or 8.
> 
> WR 12 (RTP X 2).


RC wouldn't go lower at all. no boot.
is there really a point to raising RAS?
RFC is really bad on this specific kit
is better RDWR worth more than CWL12?
WR also wouldn't budge, it would crash after like 10 hours of karhu sometimes with lower WR


----------



## Valka814

Hey guys! I would like to stabilize my memory at 3933MHz, but first have to test if my CPU can handle 1966MHz IF.
Not sure how should I loose my timings more in order to avoid errors by them.
Aorus Elite x570, 5800X, 32GB dual rank micron E-Die (Ballistix Sport LT, 2019 march)

This is my current timings:









And this is my stable OC with my previous CPU:









I also dont mind some tips where should I look for stable 3933MHz settings later. I get around 10 errors total after 10 hours of testing MemTest Pro.


----------



## Veii

Audioboxer said:


> Veii mentioned before that one of the reasons we get WHEA is because of the motherboard components like network and so on. I remember months ago turning off mobo WIFI module and even trying to disable the ethernet to see if I could stop WHEA errors lol.


I wish the user would give more data
It likely is a sideproduct of Intel Rev.02 causing issues and dropouts. That plus Firmware design of sample be configured to report any "void" value that didn't return as error to be corrected, as "hardware fault" = WHEA

Rev.02 could be patched, but was a common intel thing
Realtek all had issues , but slowly start to get better
Biggest issue of consistent errors was on Realtek 2.5gbit NIC - but hence big supply contract for many Vendors, i couldn't put Realtek on fire.
Also Intel has patched it out, but supplied for a longer time boards on Rev.02 ~ which finally got a "manual" update

I was lucky that i killed the Firmware of my ITX NIC, but it was also Rev.02 I225-V & not Rev.03 (noticed later)
Both on my B550 Creator where Rev.03 but then some B550 Strix where Rev.02 some Rev.03
Some ASRock boards the same ~ yet Vendors where quiet , trying to put the (one of the) issue(s) under the carpet tho replaced boards and redid new revisions without mention of "why" ~ on whoever contacted them about the issue (if even known)

I again, did not want to put Vendors on fire, when they did and do a lot for us.
Although slightly selfish decision, as some Vendors broke their NDA to assist me (gladly, hopefully, not fired) ~ maybe to not have to deal with my RMA's by hey, same outcome 
Meanwhile i share stuff publically of things that should not be talked about - soo your reason of decision for this event, can be made up by each on their own
If it was selfish or not 

In general
It is in the current state fixed (this tree of an issue, but not the AMDs buggy firmware type of issue) // there are many many more byproduct issues , but AMDs Firmware is the biggest one how it treats errors
Patching Rev.02 Intel NICs is hard, patching Realtek's was slowly done via driver and bios injected modules
The issue we don't need to talk about anymore (fixed after 1203C release date) ~ although some early users where/are still mad on me about this topic // who are now banned as they couldn't behave. Frustrated Rudeness, guess i understand

For OP on Reddit, it seems coincidence
As Firmware DXE module always is loaded on Post and always will cause issues
It only will not cause issues being "soft-disabled", if GMI Link speed was part of the issue (bandwidth peak)

Also i want to "abuse" this thread here too and link to the tools here
https://www.overclock.net/threads/5800x3d-owners.1798046/post-28981807
Please don't ask me for assistance how to use it 

EDIT:
And maybe passively advertise to BZs Video and the tRFC topic & comment
~ to fix potentially another misunderstanding that's out in the wild
https://www.youtube.com/watch?v=YDkSJqCPIGU&lc=UgzP2_WSmNxB6Zx3dsF4AaABAg
Link has pinned comment ~ he surely has seen it, but it's long so who knows who'll take their time to read it
^ Topic is AIDA, tRFC & Performance measurement type


----------



## Taraquin

Zeryth said:


> RC wouldn't go lower at all. no boot.
> is there really a point to raising RAS?
> RFC is really bad on this specific kit
> is better RDWR worth more than CWL12?
> WR also wouldn't budge, it would crash after like 10 hours of karhu sometimes with lower WR


Raise RAS to 44 then, RC should always be RAS+RP. WR should be RTP x 2 so if WR can't go lower raise RTP to 7. You must set 2t/gdm ofg for it to work. WR 16, RTP 8 is also fine. Try RFC 568 or 576.

You can also try gdm off 1t, but then you must change DrvStr, 40 20 30 24 maybe works. 

RDWR seems to matter more to performance than CWL so I would try that.


----------



## Luggage

Don’t know if this tool has been posted on OCN or if it’s any use for us on desktop.


__
https://www.reddit.com/r/overclocking/comments/uhsv4r


----------



## Veii

Luggage said:


> Don’t know if this tool has been posted on OCN or if it’s any use for us on desktop.
> 
> 
> __
> https://www.reddit.com/r/overclocking/comments/uhsv4r


Haha, it uses the same HII db and NVRam method with a GUI
Pretty much one to one like you have for efi variables (no UEFI overlay)

He didn't credit AMI at all and shouldn't be able to push something close source out. Needs to be open source with credits
Its a copyright issue unless he does not use AMISCE-EFI and just exports them himself

Problem, the export and security part alone is under AMI copyright and would need their tools

Ty nevertheless
Maybe useful
I'll get it just in case they Copyright strike him

Edit:
Seems to have an old tool out on edk2
Maybe it will stay. RU Tool works similar


----------



## TimeDrapery

Luggage said:


> Don’t know if this tool has been posted on OCN or if it’s any use for us on desktop.
> 
> 
> __
> https://www.reddit.com/r/overclocking/comments/uhsv4r


Thank you for linking this tool


----------



## Veii

Luggage said:


> Don’t know if this tool has been posted on OCN or if it’s any use for us on desktop.
> 
> 
> __
> https://www.reddit.com/r/overclocking/comments/uhsv4r


Glad glad, i was wrong








Build upon








edk2-platforms/Readme.md at master · tianocore/edk2-platforms


EDK II sample platform branches and tags. Contribute to tianocore/edk2-platforms development by creating an account on GitHub.




github.com




Open source EDK II platform - with their modules, nothing AMI intern at all ~ very good.
But user has build it on current AMD's architecture ~ while not having committed to the same open source project he uses it from.
Idk about that part








Once that is done, more people can work on AMD Firmware
Once again, ty for linking 

EDIT:
It can change options that are visible in AMIBCP ~ like AMI SETUP_VAR fields on ASRock boards
And surely many fields on MSI boards
But it does not show anything in CBS, PBS, or any menu ~ which you don't show in your normal bios. Unfortunately not usable for that. But surely great for notebooks


----------



## xProlific

xProlific said:


> I am still working on testing each stick individually, first stick passed I will test the others and will hopefully have a report by tomorrow. I have also ordered a 2x16 3800 kit that I plan on testing this weekend to see if I can run that without errors.


So all 4 sticks passed, so I guess the limiting factor may be the IMC. I guess I am really that unlucky have both of my last two Ryzen 5000 CPUs unable to do 3800Mhz with 4 sticks. I think at least this chip may be able to do it with two, which was something definitely not possible on my last CPU. TBH it just might be the case that most of these CPUs are unable to do 3800MHz stable with four modules.

Anyway I need some advice as to where to go from here. I got both 3600MHz and 3666 to complete without errors but latency on both seems high. What can I can do to reduce?


----------



## Taraquin

xProlific said:


> So all 4 sticks passed, so I guess the limiting factor may be the IMC. I guess I am really that unlucky have both of my last two Ryzen 5000 CPUs unable to do 3800Mhz with 4 sticks. I think at least this chip may be able to do it with two, which was something definitely not possible on my last CPU. TBH it just might be the case that most of these CPUs are unable to do 3800MHz stable with four modules.
> 
> Anyway I need some advice as to where to go from here. I got both 3600MHz and 3666 to complete without errors but latency on both seems high. What can I can do to reduce?
> 
> View attachment 2559431


Fix infinity fabric on second template, you are unsynced. I would try to get 1t gdm off stable, then tweak timings. If you have okay binning 3666cl14 should be doable around 1.45-1.5v.


----------



## xProlific

Taraquin said:


> Fix infinity fabric on second template, you are unsynced. I would try to get 1t gdm off stable, then tweak timings. If you have okay binning 3666cl14 should be doable around 1.45-1.5v.


 Good catch I, guess I forgot to adjust the IF this morning before testing. I'll give GDM mode off a try at 3600 and go from there.


----------



## Audioboxer

Veii said:


> I wish the user would give more data
> It likely is a sideproduct of Intel Rev.02 causing issues and dropouts. That plus Firmware design of sample be configured to report any "void" value that didn't return as error to be corrected, as "hardware fault" = WHEA
> 
> Rev.02 could be patched, but was a common intel thing
> Realtek all had issues , but slowly start to get better
> Biggest issue of consistent errors was on Realtek 2.5gbit NIC - but hence big supply contract for many Vendors, i couldn't put Realtek on fire.
> Also Intel has patched it out, but supplied for a longer time boards on Rev.02 ~ which finally got a "manual" update
> 
> I was lucky that i killed the Firmware of my ITX NIC, but it was also Rev.02 I225-V & not Rev.03 (noticed later)
> Both on my B550 Creator where Rev.03 but then some B550 Strix where Rev.02 some Rev.03
> Some ASRock boards the same ~ yet Vendors where quiet , trying to put the (one of the) issue(s) under the carpet tho replaced boards and redid new revisions without mention of "why" ~ on whoever contacted them about the issue (if even known)
> 
> I again, did not want to put Vendors on fire, when they did and do a lot for us.
> Although slightly selfish decision, as some Vendors broke their NDA to assist me (gladly, hopefully, not fired) ~ maybe to not have to deal with my RMA's by hey, same outcome
> Meanwhile i share stuff publically of things that should not be talked about - soo your reason of decision for this event, can be made up by each on their own
> If it was selfish or not
> 
> In general
> It is in the current state fixed (this tree of an issue, but not the AMDs buggy firmware type of issue) // there are many many more byproduct issues , but AMDs Firmware is the biggest one how it treats errors
> Patching Rev.02 Intel NICs is hard, patching Realtek's was slowly done via driver and bios injected modules
> The issue we don't need to talk about anymore (fixed after 1203C release date) ~ although some early users where/are still mad on me about this topic // who are now banned as they couldn't behave. Frustrated Rudeness, guess i understand
> 
> For OP on Reddit, it seems coincidence
> As Firmware DXE module always is loaded on Post and always will cause issues
> It only will not cause issues being "soft-disabled", if GMI Link speed was part of the issue (bandwidth peak)
> 
> Also i want to "abuse" this thread here too and link to the tools here
> https://www.overclock.net/threads/5800x3d-owners.1798046/post-28981807
> Please don't ask me for assistance how to use it
> 
> EDIT:
> And maybe passively advertise to BZs Video and the tRFC topic & comment
> ~ to fix potentially another misunderstanding that's out in the wild
> https://www.youtube.com/watch?v=YDkSJqCPIGU&lc=UgzP2_WSmNxB6Zx3dsF4AaABAg
> Link has pinned comment ~ he surely has seen it, but it's long so who knows who'll take their time to read it
> ^ Topic is AIDA, tRFC & Performance measurement type


This B550 only has a Realtek NIC, still WHEA galore above 1900 😜


----------



## Taraquin

xProlific said:


> Good catch I, guess I forgot to adjust the IF this morning before testing. I'll give GDM mode off a try at 3600 and go from there.


You are sure 1866 or 1900 fclk don`t work? WHEA19? No boot? You could try setting all ram etc to auto (except soc of 1.15v and iod of 1.05v), just run 1866 or 1900 to see if it works, then tune ram.


----------



## Taraquin

Audioboxer said:


> This B550 only has a Realtek NIC, still WHEA galore above 1900 😜


WHEA19 seems to come from a lot of sources, the changeable ones seems to be network, SOC\IOD\VDDP or VDD18. The unchangeable ones seems to be complex mobos\4dimm is more likely, simple mobos\2dimm less likely, 1 ccds less likely, 2 ccds far more likely. Probably more reasons aswell. If AMD only could make WHEA19 a bit more spesific like: 

WHEA19 error occured:

LAN miscommunication
Interconnect CCD2 - I\O
SOC voltage


----------



## Audioboxer

Taraquin said:


> WHEA19 seems to come from a lot of sources, the changeable ones seems to be network, SOC\IOD\VDDP or VDD18. The unchangeable ones seems to be complex mobos\4dimm is more likely, simple mobos\2dimm less likely, 1 ccds less likely, 2 ccds far more likely. Probably more reasons aswell. If AMD only could make WHEA19 a bit more spesific like:
> 
> WHEA19 error occured:
> 
> LAN miscommunication
> Interconnect CCD2 - I\O
> SOC voltage


It'll be 2CCD for me.


----------



## Veii

Taraquin said:


> WHEA19 seems to come from a lot of sources, the changeable ones seems to be network, SOC\IOD\VDDP or VDD18. The unchangeable ones seems to be complex mobos\4dimm is more likely, simple mobos\2dimm less likely, 1 ccds less likely, 2 ccds far more likely. Probably more reasons aswell. If AMD only could make WHEA19 a bit more spesific like:
> 
> WHEA19 error occured:
> 
> LAN miscommunication
> Interconnect CCD2 - I\O
> SOC voltage


The problem or let's call it "bizarre event" , is that CCD00 or the 01 the first one on the left/top is causing the issue.
More clearly , the connection point towards & in I/O die for some reason, is speeding up way beyond max values and cause WHEA (all sorts of)
This is manifested in core overboost beyond FIT limiters and in fabric speed (beyond GMI peak freq limiters)
So also includes LCLK beyond "current null-point" of 593MHz ~ and reaches sometimes insane 800+ values & FCLK of 2500+

Somebody would say, this has to be known to AMD's Firmware Team already ~ but time showed, they are still clueless ?!?
Really the bizarre thing is, that once only CCD02 is active ~ overboost issues stop, fully
Also without the whole CCD being suspended, they stop once load switches CCDs

This was with old windows, new windows, old chipset updates and powerplan changes
Yet to this date it still causes issues

Something with IO/Die and Firmware, is completely messed up & anything i find is rotated and unclear















(rotate last picture ~ likely)
If AMD ever gets to fix the overboost issue and actually limits internal overdriving methods ~ then they maybe will fix WHEA fully 
In the current state, they not only have L3 issues but also not every sample out there (that is 98% of them) are capable to function "normally" without running into a runaway scenario ~ hence WHEA

IO Parts breaking, while being an old issue ~ simply was by receiving absurd frequency spikes
So also where/are to this date ~ PCIe 4.0 issues

EDIT:
Whatever the exact issue is in firmware (likely many as all of them overdrive ~ even in X3D i hit applied 6ghz spikes)
If you can get on dual CCDs only the first CCD disabled not the 2nd ~ your overboost issue might fade away


----------



## Subut

Hello again. I've been at it since I've last posted with little to no progress. Will someone tell me what this error means? Also my settings look okay but somehow don't work, any ideas? Thanks in advance and happy clocking.


----------



## Veii

Subut said:


> Hello again. I've been at it since I've last posted with little to no progress. Will someone tell me what this error means? Also my settings look okay but somehow don't work, any ideas? Thanks in advance and happy clocking.
> 
> 
> View attachment 2559531


One (CPU) thread crashed


----------



## TimeDrapery

Yuuuuup

On my ATX mobo if tRDWR and tWRRD aren't "optimal" (which, past a certain memory strap this is "impossible") then with an even tCL tPHYRDL trains to 26/28... Dropping frequencies and tightening tRDWR to 7, rather than 8, and leaving tWRRD at 3 as it trains makes it so tPHYRDL trains to 26/26 with an even tCL

Phooey 😂😂😂😂😂


----------



## Subut

Veii said:


> One (CPU) thread crashed


ooh gotcha~!

im running pbo enabled on auto, co disabled, cpu all core on auto and vcore on auto on level5 LLC (out of8). what would you recommend?

edit. cooling with nh-d15 but I haven't really checked my operating temps in a while

edit2; could the thread crash casued by the memory system?


----------



## xProlific

Taraquin said:


> You are sure 1866 or 1900 fclk don`t work? WHEA19? No boot? You could try setting all ram etc to auto (except soc of 1.15v and iod of 1.05v), just run 1866 or 1900 to see if it works, then tune ram.


Just to vent a bit, I have a 4x8 3800CL4 kit that is no longer produced. In fact no one memory supplier that I am aware of sells 32gb 3800MHz at this point in time, and I think that is due in part to the memory controllers on at least 50% of AMDs CPUs not being capable of running that speed 1:1 with the IF in dual channel mode. You can buy a 4000MHz kit but I think at that speed the expectation there is you will not be running 1:1, so the gap between 3600 and 4000 is a deliberate one.

so far I have tried...
3800CL16 - I can boot easily and get No WHEA errors but I get memory errors anywhere from 500-1500% in Kharu with loose or tight subtimings. I don't think I have tried straight auto with just those two settings but definitely simillar settings. I'll give it a try 3666 though cause I have done the least amount of testing at that speed. Thinking about it more, I feel like maybe I have spent too much effort trying to achieve stability by messing with timings and voltages, maybe I should be tinkeriing with ProcODT and RttNom/WR/Park instead.

3600CL16 - I can run GDM On 1t or GDM Off 2t, GDM Off 1t is not stable. Also just to test how low I can go, I was able to pass Kharu overnight at 1.0 Vsoc and 1.40 Vdimm.


----------



## TimeDrapery

xProlific said:


> Just to vent a bit, I have a 4x8 3800CL4 kit that is no longer produced. In fact no one memory supplier that I am aware of sells 32gb 3800MHz at this point in time, and I think that is due in part to the memory controllers on at least 50% of AMDs CPUs not being capable of running that speed 1:1 with the IF in dual channel mode. You can buy a 4000MHz kit but I think at that speed the expectation there is you will not be running 1:1, so the gap between 3600 and 4000 is a deliberate one.
> 
> so far I have tried...
> 3800CL16 - I can boot easily and get No WHEA errors but I get memory errors anywhere from 500-1500% in Kharu with loose or tight subtimings. I don't think I have tried straight auto with just those two settings but definitely simillar settings. I'll give it a try 3666 though cause I have done the least amount of testing at that speed. Thinking about it more, I feel like maybe I have spent too much effort trying to achieve stability by messing with timings and voltages, maybe I should be tinkeriing with ProcODT and RttNom/WR/Park instead.
> 
> 3600CL16 - I can run GDM On 1t or GDM Off 2t, GDM Off 1t is not stable. Also just to test how low I can go, I was able to pass Kharu overnight at 1.0 Vsoc and 1.40 Vdimm.


My problem running four DIMMs was also likely due to either IMC or mobo limitations of a physical nature (more likely this IMO)

Although I'd had no problems running Karhu or MemTest over 10000% or running TM5 without errors OCCT's Memory test would produce errors RAPIDLY and this shook the idea from my head for now 😂😂😂😂😂

Back to 16GB for me until I snag a DR kit at some point in the future


----------



## Luggage

Subut said:


> ooh gotcha~!
> 
> im running pbo enabled on auto, co disabled, cpu all core on auto and vcore on auto on level5 LLC (out of8). what would you recommend?
> 
> edit. cooling with nh-d15 but I haven't really checked my operating temps in a while
> 
> edit2; could the thread crash casued by the memory system?


Put LLC back to auto on MSI mb.


----------



## Subut

Luggage said:


> Put LLC back to auto on MSI mb.


but then I can't do individual core curve optimizer negative offset in a meaningful way won't I?


----------



## Luggage

Subut said:


> but then I can't do individual core curve optimizer negative offset in a meaningful way won't I?


Wut?!? I have no idea what you’re talking about. MSI and one of the others don’t play well with PBO is you mess with LLC. (Can’t remember if Asrock or GB, don’t think it’s ASUS, someone here knows for sure)


----------



## TimeDrapery

Subut said:


> but then I can't do individual core curve optimizer negative offset in a meaningful way won't I?


You can, many people run CPU LLC on Auto and attain good results from CO OC

If you really really want to because Skatterbencher told you to on YouTube then you can run whatever LLC you please but just remember... You're likely spending more than five minutes on your OC and therefore you can familiarize yourself more thoroughly with LLC behaviors than a dude that's getting flowed hardware and stuffed in front of a camera in order to market it to you


----------



## Luggage

TimeDrapery said:


> You can, many people run CPU LLC on Auto and attain good results from CO OC
> 
> If you really really want to because Skatterbencher told you to on YouTube then you can run whatever LLC you please but just remember... You're likely spending more than five minutes on your OC and therefore you can familiarize yourself more thoroughly with LLC behaviors than a dude that's getting flowed hardware and stuffed in front of a camera in order to market it to you


Skattenbencher really seems to like all the ASUS “special features” that doesn’t translate to the other brands.


----------



## xProlific

TimeDrapery said:


> My problem running four DIMMs was also likely due to either IMC or mobo limitations of a physical nature (more likely this IMO)
> 
> Although I'd had no problems running Karhu or MemTest over 10000% or running TM5 without errors OCCT's Memory test would produce errors RAPIDLY and this shook the idea from my head for now 😂😂😂😂😂
> 
> Back to 16GB for me until I snag a DR kit at some point in the future


Thanks for the advice I'll definitely give OCCT's memory test a whirl if it can save me time. 

Also on you point about it possibly being a motherboard limitation, I thought about this too and wasn't sure how to rule out my motherboard as a factor apart from running the CPU in a different system. I thought about testing the OC stability of each individual Ram Slot but I am not coinfident the passing of such a test would enough to rule out a motherboard limitation.

I have a pair of DR 16GB neos arriving tomorrow, so it will be interesting to see how those perform and if they can resolve the issues I am experiencing. If you or anyone else want to place a bet on how 2x16DR will change things in relation to 4x8SR please feel free to speculate. Personally I think it will make no difference as for OC stability as both setups are effectively DR and I believe it is DR that puts the additional stress on the memory controller and not the 4 modules themselves. My hope though is that at the very least 2x16 will allow for reduced latency due to daisy chain topology of the motherboard.


----------



## TimeDrapery

xProlific said:


> Thanks for the advice I'll definitely give OCCT's memory test a whirl if it can save me time.
> 
> Also on you point about it possibly being a motherboard limitation, I thought about this too and wasn't sure how to rule out my motherboard as a factor apart from running the CPU in a different system. I thought about testing the OC stability of each individual Ram Slot but I am not coinfident the passing of such a test would enough to rule out a motherboard limitation.
> 
> I have a pair of DR 16GB neos arriving tomorrow, so it will be interesting to see how those perform and if they can resolve the issues I am experiencing. If you or anyone else want to place a bet on how 2x16DR will change things in relation to 4x8SR please feel free to speculate. Personally I think it will make no difference as for OC stability as both setups are effectively DR and I believe it is DR that puts the additional stress on the memory controller and not the 4 modules themselves. My hope though is that at the very least 2x16 will allow for reduced latency due to daisy chain topology of the motherboard.


Both systems _are_ definitely effectively DR but they're _not_ at all effectively identical... More PCBs plugged in to the board = more signals traveling on more traces = decreased signal integrity compared to less PCBs plugged in to the mobo

I'm looking forward to hearing of your DR results!


----------



## Netblock

Valka814 said:


> Hey guys! I would like to stabilize my memory at 3933MHz, but first have to test if my CPU can handle 1966MHz IF.
> Not sure how should I loose my timings more in order to avoid errors by them.
> Aorus Elite x570, 5800X, 32GB dual rank micron E-Die (Ballistix Sport LT, 2019 march)
> 
> This is my current timings:
> View attachment 2559395
> 
> 
> And this is my stable OC with my previous CPU:
> View attachment 2559396
> 
> 
> I also dont mind some tips where should I look for stable 3933MHz settings later. I get around 10 errors total after 10 hours of testing MemTest Pro.


If you're having fabric/WHEA issues, lower CCD to around 0.90 volts.
Otherwise errors might be due to GDM being off. See if enabling it stops the erroring; and if it does, you could get it back off again by raising ClkDrvStr to 40-60 ohms.
ProcODT might benefit being 40 or 36.9 ohms.


----------



## Netblock

Zeryth said:


> View attachment 2559384
> 
> Any Advice to tighten it more? rev4 4x8


You could get GDM off by raising ClkDrvStr to 40-60 ohms. Though you might not due to being dual-rank.

tRFC on Rev.E is very sharp wherein there is a 4-6 point difference between daily stable and not booting at all. To this, I suggest to walk it down by 5-10 ticks until it doesn't boot, then raise it up by 5-10.

tRP, tRC and the tWTR timings might be able to be scraped a little further by a tick or two.

If you have instability issues, your tRCDRD and tRTP look concerningly tight. Crucial's bins of Rev.E needs to have tRDCRD basically that of XMP in terms of nanoseconds. tRCDWR maybe too, as simply being able to set below 8 is unusal.


----------



## Veii

Veii said:


> Still having to find that bellow 1.3v SOC, degradation on Vermeer's Interposer
> The degradation is X high boost with Y fixed core voltage
> SystemOnChip adjusts linkspeed but does not adjust FCLK dynamically


Re'quote of quote of quote & jumping channels @TimeDrapery @Blameless
Internally parts still are dynamically adjusting
(need to test if xGMI & GMI link speed fixing will stop this overboosting that causes WHEA for all of us ~ but i think it's not that)

About degradation
Tested yesterday again , and i had big issues with 2133 on something that worked
Have to say am on a new "better" PSU tho. Cleared NVRAM, reset SMU ~ no change, finally got it to boot but instantly AMD PPM bluescreened
(something has changed on a non updated win-update disabled gaming system)
Disabling that via registry ~ only causes watchdog timer , crashes
Soo redid powering a bit as 2100 FCLK was crashing on stock boost even on N32 ~ tested again old 4600 profile, also no boot . . . Soo something was fishy even after reseating dimms

Apparently,
Dimm order for 2 dimms plays a role ?!? @Bloax
It seems that BGS Alt, is prioritizing dimms differently and "the first dimm" plays a role how PHY is training them

This is the AMD Experience, after many many tries and after reseating (board refuses to post tPHYRDL 32, only 30 works)
If this mess ever boots, it crashes instantly ~ same for 2133:2133:2133








And then once it finally woke up, on the next reset and another cmos + profile load
It finally got it right & can confirm it's stable again // something that didn't want to post at all








Although UCLK that low, is actually a bottleneck ~ and "something" slows down memory bit-width
Memory loses a lot of maximum bandwidth ~ and stays on 58.2ns // about 9-10ns slower on 2:1 mode

Crosslinking (well both threads are on a mixed topic of FCLK, memory and other fun issues)
But potentially someone should test if Determinism slider Power with cTDP and Package powerlimit on 200W does "anything" to multi core scores and inter-core bandwidth, compared to "performance"
And somebody should test or try to figure out, what exactly is throttling to lose over 5000MB/s peak by going 2:1 mode. And only write is unaffected
Another somebody, should also test with SCE changes if fixing GMI and xGMI link speeds to lower freq - would do anything to WHEA 19 , once they know that LCLK and FCLK_EFF are not dynamic anymore


----------



## Blameless

Veii said:


> Crosslinking (well both threads are on a mixed topic of FCLK, memory and other fun issues)
> But potentially someone should test if Determinism slider Power with cTDP and Package powerlimit on 200W does "anything" to multi core scores and inter-core bandwidth, compared to "performance"


I'll give it a look next week a some point after my new board gets here and I can use my other AM4 CPUs.



Veii said:


> And somebody should test or try to figure out, what exactly is throttling to lose over 5000MB/s peak by going 2:1 mode. And only write is unaffected


As a guess, memory controller (running at half of memory clock instead of full memory clock) seems like the clear limiting factor here, and write would be unaffected on single CCD parts because write is already completely bottlenecked by the reduced fabric link width.


----------



## papatsonis

Hi, 

Any suggestions for improvement ? (VDDR 1.3v, IF above 1800 starts slowly slowly to WHEA)


----------



## Veii

Blameless said:


> As a guess, memory controller (running at half of memory clock instead of full memory clock) seems like the clear limiting factor here, and write would be unaffected on single CCD parts because write is already completely bottlenecked by the reduced fabric link width.


That's the question i'm asking myself
UCLK and bit-width should not go hand in hand. It would be "questionable" to depend your 32 byte channel on MCLK or even make it dynamic at all
Alone questionable, when i know that memory is utilizing full bandwidth and then subtracted from that is tRFC pause and then later user timings - that limit peak bandwidth
(it comes out designed to utilize full bandwidth)

On something that "has to hit" nearly 70 000 flat, getting 59 ish
Read loss from potential peak (67200MB/s) is 6.6%
Copy loss from potential peak is 17.4%
Delta between Read & Copy is 10.1%

4600MT/s =73 600MB/s
Read = 24.5% off (nearly perfectly 4x slower)
Copy = 26.5% slower (less than double
Delta between R & C =1.6%
^ looks like outer-bottleneck scenario (and it's not UCLK, else Write would suffer too)








Something just doesn't make sense, big times
You do lose about 10ns going 2:1, but something else (has to be) slowed down aside from UCLK - with it

I'll check internal UCLK now, as what is reported here also doesn't match
1900 FCLK X3D runs 4000 Internal-UCLK, and 1900 Memory-UCLK
Will edit~


----------



## PJVol

Veii said:


> Something just doesn't make sense, big times


Do you taking into account fclk -> uclk/mclk async penalty?


----------



## Blameless

Veii said:


> That's the question i'm asking myself
> UCLK and bit-width should not go hand in hand. It would be "questionable" to depend your 64 bit channel on MCLK or even make it dynamic at all
> Alone questionable, when i know that memory is utilizing full bandwidth and then subtracted from that is tRFC pause and then later user timings - that limit peak bandwidth
> (it comes out designed to utilize full bandwidth)
> 
> On something that "has to hit" nearly 70 000 flat, getting 59 ish
> Read loss from potential peak (67200MB/s) is 6.6%
> Copy loss from potential peak is 17.4%
> Delta between Read & Copy is 10.1%
> 
> 4600MT/s =73 600MB/s
> Read = 24.5% off (nearly perfectly 4x slower)
> Copy = 26.5% slower (less than double
> Delta between R & C =1.6%
> ^ looks like outer-bottleneck scenario (and it's not UCLK, else Write would suffer too)
> View attachment 2559610
> 
> Something just doesn't make sense, big times
> You do lose about 10ns going 2:1, but something else (has to be) slowed down aside from UCLK - with it
> 
> I'll check internal UCLK now, as what is reported here also doesn't match
> 1900 FCLK X3D runs 4000 Internal-UCLK, and 1900 Memory-UCLK
> Will edit~


I'm just going off what is known about the Vermeer topology, and my interpretation is as follows...

We have a CCD connected to an IOD by a 32 byte/cycle (67.2 GB/s @ 2100MHz) downstream link and a 16 byte/cycle upstream (33.6 GB/s) link. On the IOD, we have two unified memory controllers, one for each channel, each apparently attached to fabric with a full 32 byte/cycle symmetric link. At 2100MHz that's a full 67.2GB/s per memory controller/channel, which is probably why we can get such high utilization figures at the DRAM I/O side of things when everything is 1:1...the FCLK/UMC link was designed to supply full _theoretical peak_ bandwith at 1:2 and is massively over provisioned for 1:1. I don't know where the actual clock crossing boundary is, but it shouldn't really matter; at 1150MHz uclk we are limited to 36.8GB/s per channel, or 73.6GB/s in tandem, at 100% utilization...but no where near 100% utilization is reasonable, especially after having to deal with that clock crossing boundary on top of memory side inefficiencies. Write performance still isn't hit because it's bottlenecked all the way down at 33.6 GB/s total back at the fabric link between the CCD and IOD.

I'm not sure where that 4GHz internal UCLK is coming from, unless it's adding both UMCs or something.


----------



## Veii

PJVol said:


> Do you taking into account fclk -> uclk/mclk async penalty?


Yes, it's around 10ns penalty ~ it's not the delay and cache is unaffected


Veii said:


> I'll check internal UCLK now, as what is reported here also doesn't match
> 1900 FCLK X3D runs 4000 Internal-UCLK, and 1900 Memory-UCLK
> Will edit~


Indeed it's odd ~ clearly visible that something bottlenecks with nearly identical efficiency timings


Spoiler: CPU "Specs"




















ignore freq straps here, was toying around ~ old screenshot










There is a 200Mhz or 400MT/s difference
MEM 6300 to 6900 is 600 difference, but likely both readouts are combined values - i doubt it runs that fast
6300 / 2 = 3150
3400 * 2 = 6800
250Mhz difference, or 500Mhz distance while it should be 200/400
Somehow math doesn't add up, it misses 100Mhz somewhere ~ even after comparing 2:1 or 1:1 distance
Both are at 2100 FCLK & X3D just attached for extra


Spoiler: Timings






















I struggle to believe, improved Read to Copy efficiency over 10% compared to my old preset - and on higher clock with the same voltage.
(looks to my eyes that both Read and Copy are strongly "equally" throttled , as much as that they nearly equalize
~ there is no way i out of nowhere improved efficiency that much with nearly identical timings)

Timings where just extended, soo no voltage needed to increase (1.67-1.68v)
Also should start to explore powerdown mode behavior and see what's up with sc WW & RR timings
Shows visible that PDA needed +1 in order to train 2* higher steps (used 3* here)

EDIT:
Used
CoreFreq ~ Dev download link
GitHub - cyring/CoreFreq: CoreFreq is a CPU monitoring software designed for the 64-bits Processors. ~ Code, should also work under windows Linux env kernel


----------



## Veii

Blameless said:


> I don't know where the actual clock crossing boundary is, but it shouldn't really matter; at 1150MHz uclk we are limited to 36.8GB/s per channel, or 73.6GB/s in tandem, at 100% utilization...but no where near 100% utilization is reasonable, especially after having to deal with that clock crossing boundary on top of memory side inefficiencies. Write performance still isn't hit because it's bottlenecked all the way down at 33.6 GB/s total back at the fabric link between the CCD and IOD.


Soo if i understand you , running bellow 2000 Mhz Mem (1000 UCLK) with forced 1:1:2 mode ~ soo 32GB/s, should drop 33.6GB/s write unless upstream is split ?
It's bit problematic, as anything bellow FLCK is not running in "gear 2" mode ~ but maybe enforcable

My problem to all this is
Math doesn't add up in the usable sense
The difference is too big and even "running numbers" don't add up.
Something more than UCLK is throttled, somewhy ~ or i don't get it
I'll have to try with much higher clock (poor A0's) and then compare again, if any type of scaling pattern exists.
So far it doesn't look at all ~ and would need 5000 19-19-19, to come even close to 4200C15-15 1:1 (that is, if mem latency doesn't start to be the issue first)
5000 C19 flat, is insane  or 5400+ Rev.E/Rev.B timings ~ just to equalize the losses


----------



## Blameless

Veii said:


> So far it doesn't look at all ~ and would need 5000 19-19-19, to come even close to 4200C15-15 1:1 (that is, if mem latency doesn't start to be the issue first)
> 5000 C19 flat, is insane  or 5400+ Rev.E/Rev.B timings ~ just to equalize the losses


It's a huge hit, but it doesn't seem that out of line to me.

When Zen first showed up, I was astounded at the bandwidth utilization/efficiency figures being reported, they were higher than anything I'd seen since S754 with single channel DDR at ultra tight timings. Even stuff on the Intel side with huge uncore clocks and very well regarded memory controllers wasn't coming close. I figured it was a combination of cache or some huge buffer somewhere, but when they showed the UMC links on AMD's slides it started to make more sense. The bandwidth to and from the memory controller, and presumably the bandwidth the memory controller itself could handle, was double that of the peak bandwidth of the memory you could attach to it in 1:1 mode. Cutting that memory controller bandwidth in half, relative to the memory, seems like it should tank bandwidth efficiency...and it seems to.

That clock crossing boundary implicit in running the UCLK asynchronously should also be expected to significantly hurt performance, no matter what the UCLK ends up being. We saw this with Intel's MCH and their tRD, especially when compared against NVIDIA's nForce chipsets on the same platform, which seemed to dispense with any clock crossing at all in 1:1 mode and were thus unbeatable (you could tighten tRD on an Intel chipset, but it never went away), if memory was limited to such speeds.

On Vermeer, I don't think I've ever seen anyone gain any real performance by going to 1:2 mode, unless they had some sticks that were exceptionally poor at tightening up at 1:1 but could scale to the sort of extreme clocks you mention.

Honestly, the only reason I suspect AMD included this mode was so they could retain compatibility with silly Intel-focused XMP at absurd clocks, so the set it and forget it crowd who didn't actually give a piss about real performance could see the magic number they wanted and feel like they didn't just waste a truckload of money on some ultra-high clocked memory. It's mostly marketing.

Maybe there is something more to it, some anomaly that, if corrected, will make 1:2 more viable, but I don't see that implied anywhere. I'm not an expert on the matter though.


----------



## Subut

TimeDrapery said:


> You can, many people run CPU LLC on Auto and attain good results from CO OC
> 
> If you really really want to because Skatterbencher told you to on YouTube then you can run whatever LLC you please but just remember... You're likely spending more than five minutes on your OC and therefore you can familiarize yourself more thoroughly with LLC behaviors than a dude that's getting flowed hardware and stuffed in front of a camera in order to market it to you


dunno if scatterbencher or who, definitely someone online and probably someone from youtube 😅

edit. way back on ivybridge when I was new to overclocking, I ran level5 out of 7 on an asrock board, it was just fine. I rolled with that ever since.

edit2. admittedly there is no concise guide for these stuff. so I go by whatever I hear or read online and this scatterbencher guy seems qualified 🤷‍♀️

edit3. yeah man I've been messing around and running TM5 for months now and I just wanna get it right.


----------



## Taraquin

xProlific said:


> Just to vent a bit, I have a 4x8 3800CL4 kit that is no longer produced. In fact no one memory supplier that I am aware of sells 32gb 3800MHz at this point in time, and I think that is due in part to the memory controllers on at least 50% of AMDs CPUs not being capable of running that speed 1:1 with the IF in dual channel mode. You can buy a 4000MHz kit but I think at that speed the expectation there is you will not be running 1:1, so the gap between 3600 and 4000 is a deliberate one.
> 
> so far I have tried...
> 3800CL16 - I can boot easily and get No WHEA errors but I get memory errors anywhere from 500-1500% in Kharu with loose or tight subtimings. I don't think I have tried straight auto with just those two settings but definitely simillar settings. I'll give it a try 3666 though cause I have done the least amount of testing at that speed. Thinking about it more, I feel like maybe I have spent too much effort trying to achieve stability by messing with timings and voltages, maybe I should be tinkeriing with ProcODT and RttNom/WR/Park instead.
> 
> 3600CL16 - I can run GDM On 1t or GDM Off 2t, GDM Off 1t is not stable. Also just to test how low I can go, I was able to pass Kharu overnight at 1.0 Vsoc and 1.40 Vdimm.


What soc/iod did you try 3800 on? 4xdimms may require a lot more than 3600. You may need to raise VDD18 aswell. If you get 3666 working that is good, only a few percent perf lost vs 3800.

I did a survey on TPU, about 65% can do 3800 or higher stable, but most are running 2 dimms.


----------



## Taraquin

Veii said:


> The problem or let's call it "bizarre event" , is that CCD00 or the 01 the first one on the left/top is causing the issue.
> More clearly , the connection point towards & in I/O die for some reason, is speeding up way beyond max values and cause WHEA (all sorts of)
> This is manifested in core overboost beyond FIT limiters and in fabric speed (beyond GMI peak freq limiters)
> So also includes LCLK beyond "current null-point" of 593MHz ~ and reaches sometimes insane 800+ values & FCLK of 2500+
> 
> Somebody would say, this has to be known to AMD's Firmware Team already ~ but time showed, they are still clueless ?!?
> Really the bizarre thing is, that once only CCD02 is active ~ overboost issues stop, fully
> Also without the whole CCD being suspended, they stop once load switches CCDs
> 
> This was with old windows, new windows, old chipset updates and powerplan changes
> Yet to this date it still causes issues
> 
> Something with IO/Die and Firmware, is completely messed up & anything i find is rotated and unclear
> View attachment 2559530
> 
> 
> 
> 
> 
> 
> 
> 
> (rotate last picture ~ likely)
> If AMD ever gets to fix the overboost issue and actually limits internal overdriving methods ~ then they maybe will fix WHEA fully
> In the current state, they not only have L3 issues but also not every sample out there (that is 98% of them) are capable to function "normally" without running into a runaway scenario ~ hence WHEA
> 
> IO Parts breaking, while being an old issue ~ simply was by receiving absurd frequency spikes
> So also where/are to this date ~ PCIe 4.0 issues
> 
> EDIT:
> Whatever the exact issue is in firmware (likely many as all of them overdrive ~ even in X3D i hit applied 6ghz spikes)
> If you can get on dual CCDs only the first CCD disabled not the 2nd ~ your overboost issue might fade away


How come some don't experience this overboost? I think there are more reasons aswell. Less complexity (2 dimm, itx/matx, 1 ccd) is far more likely to be WHEA19 free. Also setting some voltage higher can eliminate WHEA19 if you don't have flooding. The network fix was onteresting to see. What is the major difference vs Zen 2 that makes WHEA19 far less likely on Zen 2?

One thing that also puzzles me is why some of us can run 4133/2066 even using PCIe 4.0 WHEA19 free, while most are stuck at 3800/1900. I haven't tried disabling PCIe 4.0 to do 4200/2100, but going from 4000 to 4066 requires going from 1.12v soc to 1.16v (for no perf loss) so not worth it power wise.


----------



## Taraquin

TimeDrapery said:


> You can, many people run CPU LLC on Auto and attain good results from CO OC
> 
> If you really really want to because Skatterbencher told you to on YouTube then you can run whatever LLC you please but just remember... You're likely spending more than five minutes on your OC and therefore you can familiarize yourself more thoroughly with LLC behaviors than a dude that's getting flowed hardware and stuffed in front of a camera in order to market it to you


Skatterbencher gives you an rasy 5 min oc, good for beginners or impatient ones. Per core curve optimizer is more rewarding but also more like 5 hours+.

I actually prefers Intels approach where you get loss of performance if UV is too low, not instability. Example: My 12400F does -15mv fine, 2W lower in CB23, 4C lower temp, -20mv gives about 1% lower perf, -25mv gives 3% lower, above -30mv it becomes almost 10%. I would prefer this using curve optimizer. Regular UV behaves the same on AMD as Intel, but since you can't use adaptive pr core on Ryzen except CO you get crash instead of perf loss.


----------



## PJVol

Veii said:


> Yes, it's around 10ns penalty ~ it's not the delay and cache is unaffected


I mean did you try to roughly estimate the degree the "async fclk" and "uclk-half-speed" each affected b/w and latency?
My extreme4 board as it turned out has no divider option for the UCLK (it definitely was there in X370 Taichi), so not much for experiments.
Unlike MSI B450 board that allowed me to set some really bizarre combinations 
The screenshots below are named as FCLK-UCLK-MCLK, may be you'll find something new there


----------



## Luggage

Subut said:


> dunno if scatterbencher or who, definitely someone online and probably someone from youtube 😅
> 
> edit. way back on ivybridge when I was new to overclocking, I ran level5 out of 7 on an asrock board, it was just fine. I rolled with that ever since.
> 
> edit2. admittedly there is no concise guide for these stuff. so I go by whatever I hear or read online and this scatterbencher guy seems qualified 🤷‍♀️
> 
> edit3. yeah man I've been messing around and running TM5 for months now and I just wanna get it right.


Intel oc/undervolt is mostly manual all core, you set voltage and adjust droop for stability vs heat.
AMD PBO is dynamic and adjusts frequency and voltage much more (like GPU) if a voltage request (vid) is not met because you set a too droopy llc you will crash.
If you set a too flat llc you will push more heat than needed and will thermal or voltage limit throttle *.
(Simplified)

* not protection throttle - performance/frequency throttle. Boost scales with lower temps.


----------



## hazium233

xProlific said:


> Thanks for the advice I'll definitely give OCCT's memory test a whirl if it can save me time.
> 
> Also on you point about it possibly being a motherboard limitation, I thought about this too and wasn't sure how to rule out my motherboard as a factor apart from running the CPU in a different system. I thought about testing the OC stability of each individual Ram Slot but I am not coinfident the passing of such a test would enough to rule out a motherboard limitation.
> 
> I have a pair of DR 16GB neos arriving tomorrow, so it will be interesting to see how those perform and if they can resolve the issues I am experiencing. If you or anyone else want to place a bet on how 2x16DR will change things in relation to 4x8SR please feel free to speculate. Personally I think it will make no difference as for OC stability as both setups are effectively DR and I believe it is DR that puts the additional stress on the memory controller and not the 4 modules themselves. My hope though is that at the very least 2x16 will allow for reduced latency due to daisy chain topology of the motherboard.


The primary slots should be much better, but besides this how well four dimms v two dimms works comes down to bios too.

On the "leaderboard" there are a few four dimm setups on the Dark Hero that were tested for more than 20 or 30 minutes. Some of them were lower bins, so they were at CL 16. The secondary slot quality affects how tight the timings go, and also cramming the four dimms together makes the two middle ones pretty warm if you don't have a fan directly over them.

I don't know if you tried loose primaries with RC also loosened for lower memory controller load, or maybe more VDDP. Since you were using Karhu, could have also maybe set Cache - Disabled to make sure errors weren't somehow coming from cache.

Since you have the 2x16 coming, I guess it may be moot now.


----------



## Bugolipo

Hello guys, it's my first time posting so i'm sorry if i miss something or if it’s too long.

I'm trying to fix an issue that i have since i built this pc and i'm hopping that someone here can help since my knowledge is pretty limited (usually just turn on XMP and undervolt CPU+GPU). 

Most of the games i play just crash to desktop (really rare but sometimes it’s a BSOD) either with a memory related error or without an error, it can take 1minute to crash or some hours (usually less than 2), but it passed every single CPU or RAM stresstest that i threw at it like OCCT medium data AVX2 extreme 1h, y-cruncher 4 cycles, TM5 1usmus_v3 20 cycles (also did some extreme anta777 3 cycles), p95 1h, HCI memtest 1000% each thread.

I’ve tried stock 2133mhz, xmp 3600mhz, xmp timings with 3200mhz, timings from calculator for 3200mhz and 3600mhz, manual timings from some guides, voltages going as low as VSOC 0.9315 VDDP 0.8 VDDG both 0.85 and it’s always the same (didn’t try lower it may actually be “fine”), the only way for me to get WHEA or any other errors is if i go above 3600 even 3666 gets a lot of WHEA-19.

At this point i don’t really care about getting the most out of it i just want it to be stable and safe for some years.

CPU and GPU are both stock and already did many clean installs with different drivers and bios versions, also tried both linux and windows.

The screenshots below is what i’m trying right now and the information from thaiphoon.


----------



## hazium233

Bugolipo said:


> Most of the games i play just crash to desktop (really rare but sometimes it’s a BSOD) either with a memory related error or without an error, it can take 1minute to crash or some hours (usually less than 2), but it passed every single CPU or RAM stresstest that i threw at it like OCCT medium data AVX2 extreme 1h, y-cruncher 4 cycles, TM5 1usmus_v3 20 cycles (also did some extreme anta777 3 cycles), p95 1h, HCI memtest 1000% each thread.
> 
> I’ve tried stock 2133mhz, xmp 3600mhz, xmp timings with 3200mhz, timings from calculator for 3200mhz and 3600mhz, manual timings from some guides, voltages going as low as VSOC 0.9315 VDDP 0.8 VDDG both 0.85 and it’s always the same (didn’t try lower it may actually be “fine”), the only way for me to get WHEA or any other errors is if i go above 3600 even 3666 gets a lot of WHEA-19.


What is the dram voltage?

Default VDDP is really 0.900. Auto may set to 1.00 or 1.050 or something like that because of XMP > 3200, which may be excessive... but 0.900 may be worth checking. Your VDDG may or may not be fine here, some people are using things like Geekbench 5 benchmark to look at effect of changing voltage for that.

Similarly, you may want to try running the benchmark mode in linpack extreme, or just using LinX and verifying that increasing SOC voltage 1.00-1.0625 or so does not increase performance (and residuals are all the same). If you get more speed with higher SOC, then it was too low.

Also with the current settings, if you run AIDA and the write bandwidth is more than a couple MB/s below 28,799 then you can also tell there is an issue (as long as OS not too bloated).

For OCCT, Large dataset might be more helpful for you.


----------



## The_King

Picked up several Crucial Ballistix Max kits recently.
Got some interesting results. Unfortunately the IMC on my 1700X does not like this 4400 CL19 REV.E kit @3600MT/s even though its also C9BLM like my other kit which does 3600 CL14 DR 24/7 stable.
I believe this kit will do 3600 with flat 15s or 16s with a better CPU.


----------



## mirzet1976

Veii said:


> On something that "has to hit" nearly 70 000 flat, getting 59 ish
> Read loss from potential peak (67200MB/s) is 6.6%
> Copy loss from potential peak is 17.4%
> Delta between Read & Copy is 10.1%
> 
> 4600MT/s =73 600MB/s
> Read = 24.5% off (nearly perfectly 4x slower)
> Copy = 26.5% slower (less than double
> Delta between R & C =1.6%
> ^ looks like outer-bottleneck scenario (and it's not UCLK, else Write would suffer too)
> View attachment 2559610
> 
> Something just doesn't make sense, big times
> You do lose about 10ns going 2:1, but something else (has to be) slowed down aside from UCLK - with it


If it can help you here's my run, for comparison.


----------



## Bugolipo

hazium233 said:


> What is the dram voltage?
> 
> Default VDDP is really 0.900. Auto may set to 1.00 or 1.050 or something like that because of XMP > 3200, which may be excessive... but 0.900 may be worth checking. Your VDDG may or may not be fine here, some people are using things like Geekbench 5 benchmark to look at effect of changing voltage for that.
> 
> Similarly, you may want to try running the benchmark mode in linpack extreme, or just using LinX and verifying that increasing SOC voltage 1.00-1.0625 or so does not increase performance (and residuals are all the same). If you get more speed with higher SOC, then it was too low.
> 
> Also with the current settings, if you run AIDA and the write bandwidth is more than a couple MB/s below 28,799 then you can also tell there is an issue (as long as OS not too bloated).
> 
> For OCCT, Large dataset might be more helpful for you.


Dram voltage is 1.35, i’m just using the XMP value since it’s 3600MHz.

As for the benchmarks so far i’ve only used aida and i’m getting exactly 28,799 (sometimes 28,798).

I tried OCCT large sometimes, it still passes.

I’ll try comparing Geekbench and linpack scores with different voltages to see if there’s a change, thanks.


----------



## Taraquin

Bugolipo said:


> Dram voltage is 1.35, i’m just using the XMP value since it’s 3600MHz.
> 
> As for the benchmarks so far i’ve only used aida and i’m getting exactly 28,799 (sometimes 28,798).
> 
> I tried OCCT large sometimes, it still passes.
> 
> I’ll try comparing Geekbench and linpack scores with different voltages to see if there’s a change, thanks.


Up dram voltage to 1.4v.


----------



## Netblock

The_King said:


> Picked up several Crucial Ballistix Max kits recently.
> Got some interesting results. Unfortunately the IMC on my 1700X does not like this 4400 CL19 REV.E kit @3600MT/s even though its also C9BLM like my other kit which does 3600 CL14 DR 24/7 stable.
> I believe this kit will do 3600 with flat 15s or 16s with a better CPU.
> View attachment 2559712
> View attachment 2559711


That tRFC on that first screenshot is scary low and looks unreal for Rev.E. I have never seen a Rev.E go below 270ns, nevermind below 210.
Are the two screenshots the same kit? If so, that tRFC either has to a misreport or a XMP-be-damned tRFC unicorn bin.

Edit: or maybe you left tRFC on auto? I do recall shenanigans where tRFC2 and/or tRFC4 looks like it gets used instead, sometimes.
Edit2: yea. I just set tRFC2 and left tRFC and tRFC4 on auto. I know for a fact that my kit does not boot below tRFC of 277ns.










Edit3: those SCLs look constrictingly tight. Loosten them up to 4/4?


----------



## Taraquin

Netblock said:


> That tRFC on that first screenshot is scary low and looks unreal for Rev.E. I have never seen a Rev.E go below 270ns, nevermind below 210.
> Are the two screenshots the same kit? If so, that tRFC either has to a misreport or a XMP-be-damned tRFC unicorn bin.
> 
> Edit: or maybe you left tRFC on auto? I do recall shenanigans where tRFC2 and/or tRFC4 looks like it gets used instead, sometimes.
> Edit2: yea. I just set tRFC2 and left tRFC and tRFC4 on auto. I know for a fact that my kit does not boot below tRFC of 277ns.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Edit3: those SCLs look constrictingly tight. Loosten them up to 4/4?


Sometimes Zentimings reads RFC wrong. I have set 600 rfc on a setup I helped a friend with and it still reported 312.


----------



## TimeDrapery

Fuuuuuck you tPHYRDL 28/28, you're a chubby ****


----------



## The_King

Netblock said:


> That tRFC on that first screenshot is scary low and looks unreal for Rev.E. I have never seen a Rev.E go below 270ns, nevermind below 210.
> Are the two screenshots the same kit? If so, that tRFC either has to a misreport or a XMP-be-damned tRFC unicorn bin.
> 
> Edit: or maybe you left tRFC on auto? I do recall shenanigans where tRFC2 and/or tRFC4 looks like it gets used instead, sometimes.
> Edit2: yea. I just set tRFC2 and left tRFC and tRFC4 on auto. I know for a fact that my kit does not boot below tRFC of 277ns.
> 
> Edit3: those SCLs look constrictingly tight. Loosten them up to 4/4?


You are correct this happens sometimes when you set tRFC to low in the BIOS it misreports it has 312.
The lowest this kit does is 280ns. My CPU and mobo prefers SCLs at 2 even with my B-Die Patriot Viper 4400 C19 it always performed better and more stable with SCL at 2 vs 3 or 4.


----------



## Subut

Luggage said:


> Intel oc/undervolt is mostly manual all core, you set voltage and adjust droop for stability vs heat.
> AMD PBO is dynamic and adjusts frequency and voltage much more (like GPU) if a voltage request (vid) is not met because you set a too droopy llc you will crash.
> If you set a too flat llc you will push more heat than needed and will thermal or voltage limit throttle *.
> (Simplified)
> 
> * not protection throttle - performance/frequency throttle. Boost scales with lower temps.


thanks mate im giving it a go with auto LLC and running bunch of tests from scratch. I was using soc LLC level2. I should set that one back to auto as well don't I?


----------



## Audioboxer

@Veii I managed to catch a WHEA at 2000 FCLK that said Corrected Machine Check. Normally they say Unknown Error. What does this one mean? IF instability?


----------



## Taraquin

Audioboxer said:


> View attachment 2559788
> 
> 
> @Veii I managed to catch a WHEA at 2000 FCLK that said Corrected Machine Check. Normally they say Unknown Error. What does this one mean? IF instability?


Bus/interconnect is IF error I'm pretty sure. If rare may be correctable by adjusting voltages up/down.


----------



## Craftyman

Does TM5 (Anta777 Absolute) Error 3 mean tRFC is too low?
Anyone got a list of what all the errors mean? Thanks


----------



## Luggage

Subut said:


> thanks mate im giving it a go with auto LLC and running bunch of tests from scratch. I was using soc LLC level2. I should set that one back to auto as well don't I?


Nah, soc really doesn’t behave the same way - you want it stable for memory but not in-necessarily high so it eats into the power budget for core boosting.


----------



## sealxohd

Taraquin said:


> Bus/interconnect is IF error I'm pretty sure. If rare may be correctable by adjusting voltages up/down.


I think he meant the error source, which is normally "unknown".


----------



## Taraquin

sealxohd said:


> I think he meant the error source, which is normally "unknown".


He ask what it meant, bus/interconnect is usually IF.


----------



## ThomasW_

Any way to improve latency? FLCK 1866MHz was the maximum without WHEA error


----------



## xProlific

Okay so I received the 2x16 CL14 kit yesterday.

The highest I was able to get stable on the 4x8 CL14 kit was 3733MHz so that what I ran the 2x16 kit at first to compare. The modules have stock timings that are essentially identical to each other so I think it is about as like for like as you can get in a comparison. The only change going from the 4x8 to the 2x16 kit in my testing was that ProcODT was changed from 40>44 and RttNom was changed from RZQ/7>Disabled, all other settings are identical.

I have also attached images of the data sheets for both kits. These pretty much being equivalent offerings from Gskill it is interesting that the JEDEC Raw Card Designer is Micron for the 2x16 kit and SK hynix for the 4x8 kit. Also the 2x16 modules have integrated memory sensors, a much appreciated upgrade missing on the 4x8 kit.

*4x8 Kit*









*2x16 Kit







*


----------



## xProlific

Also the good news, I was able to run 3800 without errors on the 2x16 kit, especially considering I was never able to finish Kharu without errors on the 4x8 kit. I also ran OCCT memory test for an hour and that passed as well. Also WHEA errors in event viewer, but I was not getting wheas running 4x8 either so no change there.

Below is with DOCP enabled and everything else set to auto except VSoc at 1.15 and IOD set to 1.05 (VDIMM is set to 1.5 by DOCP). Also I think Auto brings VDDP to high...but at least no errors. So the any suggestions where should I go from here? And are their any differences I should be aware while setting timings since I am now running dual rank modules?


----------



## hazium233

Audioboxer said:


> View attachment 2559788
> 
> 
> @Veii I managed to catch a WHEA at 2000 FCLK that said Corrected Machine Check. Normally they say Unknown Error. What does this one mean? IF instability?


Like this?









I got Error Source 1 and 3 errors with CCD above a certain voltage threshold at 3866. May be CCD destabilizing cache, but I don't know exactly what it really is.


----------



## PJVol

hazium233 said:


> I don't know exactly what it really is.


It's corrected thresholded GMI link error, i.e. CCM -> IOD.
Though, i don't get, why this stupid logger missing MciSynd, there's also should be a link number pointing to the faulty CCM (for the 2 CCD cpus).


----------



## TimeDrapery

What's up everybody...? I'll bet you peoples can't ever guess *** I did to make it below 50ns in Aida64 (10000%+ Karhu/MemTest / OCCT Pro Memory test [AVX2] stable... on this profile)

😂😂😂😂😂


----------



## xProlific

My first push at bringing down the timings, passed 2000%Kharu and 1 hour OCCT memory test. Also disabling HW prefetch 1/2 bumped up CBr23 score. It also reduced Aida memory latency by around 5ns but I took a small hit to L3 of .5ns. Anyway I am happy I figured out the issues I was experiencing hitting 3800 was due to my prior 4x8 config.


----------



## TimeDrapery

xProlific said:


> My first push at bringing down the timings, passed 2000%Kharu and 1 hour OCCT memory test. Also disabling HW prefetch 1/2 bumped up CBr23 score. It also reduced Aida memory latency by around 5ns but I took a small hit to L3 of .5ns. Anyway I am happy I figured out the issues I was experiencing hitting 3800 was due to my prior 4x8 config.
> 
> View attachment 2559871


Much gooder!

Why not do your best to disable GDM?


----------



## TimeDrapery

So what's this prefetcher bullshit all about anyways? Is it that "Auto" points to "Enabled" by default but somebody at a mobo vendor or AMD (more likely since it appears across mobo brands) crossed their wires and labeled "Disabled" as "Enabled" so that the default disables the feature...? Christ...


----------



## TimeDrapery

Jesus... Child's play now 😂😂😂😂😂 @Veii we are tied now (or will be once this set is stability tested and submitted to the sheet)










Keep in mind that I changed timing parameters and voltages for this one but my last screens in my post before this... Literally all I did was disable prefetchers in BIOS and latency dropped like a ****ing rock 😂😂😂😂😂


----------



## domdtxdissar

TimeDrapery said:


> Jesus... Child's play now 😂😂😂😂😂 @Veii we are tied now (or will be once this set is stability tested and submitted to the sheet)
> 
> View attachment 2559874
> 
> 
> Keep in mind that I changed timing parameters and voltages for this one but my last screens in my post before this... Literally all I did was disable prefetchers in BIOS and latency dropped like a ****ing rock 😂😂😂😂😂


Sad if true, like i wrote in that google doc:

Ok you guys are talking about disabling L2 prefetcher in the AMD CBS biosmenu. I was testing disabling “EnablePrefetcher” in windows which does not help on latency.. I dont have the option to play with L2 prefetcher in my bios so i cant test it for now.. *but this will invalidate all previous results on this google spreadsheet.*

And it kinda explains "u/zTERRORDACTYL" old 1900:3800 results @ 48.3ns for the 5600x.. cheaters be cheaters 😆


----------



## TimeDrapery

domdtxdissar said:


> Sad if true, like i wrote in that google doc:
> 
> Ok you guys are talking about disabling L2 prefetcher in the AMD CBS biosmenu. I was testing disabling “EnablePrefetcher” in windows which does not help on latency.. I dont have the option to play with L2 prefetcher in my bios so i cant test it for now.. *but this will invalidate all previous results on this google spreadsheet.*
> 
> And it kinda explains "u/zTERRORDACTYL" old 1900:3800 results @ 48.3ns for the 5600x.. cheaters be cheaters 😆


Oh ****ing absolutely it should invalidate them _all_ unless someone can satisfactorily explain why the behavior occurs... So I messaged Robert Hallock on Reddit 😂😂😂😂😂

Disabling L1 and L2 prefetchers shouldn't do this as far as I'm aware


----------



## xProlific

TimeDrapery said:


> So what's this prefetcher bullshit all about anyways? Is it that "Auto" points to "Enabled" by default but somebody at a mobo vendor or AMD (more likely since it appears across mobo brands) crossed their wires and labeled "Disabled" as "Enabled" so that the default disables the feature...? Christ...


I am not sure what the default value does. I just know that I had manually enabled previously as that is what Dram calculator for Ryzen suggested. I had just saw someone in the Crosshair VIII motherboard thread suggest disabling it for a boost to CBr23 score sure enough that worked and also had the secondary impact of lowering latency in Aida significantly. Latency on the same setting before was disabling was 62.9...


----------



## LazyGamer

So... stupid question.

Shouldn't disabling prefetchers have far-reaching performance effects?


----------



## TimeDrapery

LazyGamer said:


> So... stupid question.
> 
> Shouldn't disabling prefetchers have far-reaching performance effects?


One would think


----------



## Veii

TimeDrapery said:


> @Veii we are tied now


I refuse~~
















But quite honestly,i feel disgusting and dirty 
Might wait with teaching a bit, let's mock these XOC guys first 

Apparently L3 improves that way, but at the trade of 0.5ns access latency
And less consistent test-to-test run variance


----------



## The_King

Veii said:


> I refuse~~


What is the actual VSOC set in the BIOS, is that VSOC safe for 24/7 use on Zen 3 ? No whea errors?
I see you also running the Viper 4000 C19 do you think Viper 4000 CL16 would perform significantly better?


----------



## Veii

The_King said:


> What is the actual VSOC set in the BIOS, is that VSOC safe for 24/7 use on Zen 3 ? No whea errors?
> I see you also running the Viper 4000 C19 do you think Viper 4000 CL16 would perform significantly better?


















That should be the orientation point
Jumping profiles and testing 2133, hence the profile had tCKE 14 in not 13
SOC & VCORE VID to V_TEL is flat


The_King said:


> is that VSOC safe for 24/7 use on Zen 3 ?


AMD max overclocking voltage main
5800X3D Owners update
daily since around 1 1/2 years now (nov, 2020)


The_King said:


> No whea errors?











Dual CCD ~ BG 2037 SUS , is correctly patched by Lab. First batch
No WHEA's, ever ~ only sometimes #18 if i do stupid things


The_King said:


> I see you also running the Viper 4000 C19 do you think Viper 4000 CL16 would perform significantly better?


Have to ask @Bloax
A0 PCB is dangerous (sensitive) and not recommended


----------



## The_King

Veii said:


> Have to ask @Bloax
> A0 PCB is dangerous (sensitive) and not recommended


Does Thaiphoon burner read these DIMMS correctly? I have the a Patriot Viper 4400 C19 kit it read has A0 but certainly does
not perform like a A0 PCB.

Could you post your Thaiphoon screenshot for comparison. Thanks


----------



## Veii

The_King said:


> I have the a Patriot Viper 4400 C19 kit it read has A0 but certainly does
> not perform like a A0 PCB.


It's a custom A1 (well A2 rather), the 4400 ones


----------



## TimeDrapery

Veii said:


> I refuse~~
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But quite honestly,i feel disgusting and dirty
> Might wait with teaching a bit, let's mock these XOC guys first
> 
> Apparently L3 improves that way, but at the trade of 0.5ns access latency
> And less consistent test-to-test run variance


😂😂😂😂😂😂😂😂😂😂

Good show, good show... Back to the drawing board I go


----------



## sealxohd

L2 Preftecher is the oldest cheat there is


----------



## PJVol

Veii said:


> Apparently L3 improves that way, but at the trade of 0.5ns access latency


Idk... for me L3 got worse, both bandwidth and latency. Turning off L1 pf also got negative impact - better to keep it auto.


----------



## sealxohd

With my 5800X3D only the L3 latency is slightly worse. But the mem + subsystem latency is 4.6 ns better


----------



## Audioboxer

lol, flashed AGESA 1.2.0.7 beta for my Unify-X and I seem to be getting micro-stutters I wasn't getting before.


----------



## TimeDrapery

Nobody can say why prefetchers being disabled brings such reductions in how Aida64 measures memory latency...? I'm confused by it... Sort of 😂😂😂😂😂


----------



## Unifyx

Audioboxer said:


> lol, flashed AGESA 1.2.0.7 beta for my Unify-X and I seem to be getting micro-stutters I wasn't getting before.


it feels like,with every new AGESA, things are getting more worse...


----------



## PJVol

TimeDrapery said:


> how Aida64 measures memory latency...?


Indeed...


----------



## KedarWolf

PJVol said:


> Idk... for me L3 got worse, both bandwidth and latency. Turning off L1 pf also got negative impact - better to keep it auto.
> View attachment 2559919


L1 PF off lost 300 points in R23 and off or on latency in AIDA is the same. 

Also off I lost 400 points in copy in AIDA.


----------



## PJVol

Perf regression in GB5 and OCCT membench combined score.
Thoughts: AIDA is too used to an old uarches, and devs could use some new blood.

PS: btw fully agree with @domdtxdissar regarding validity of the ram OC ranking's based upon it.


----------



## Prophet4NO1

I tested on my 5800x with PF on or off. Off all my bandwidth numbers are all about the same. With in variance from run to run. But, latency on memory is down into the mid to high 60ns. Down from low to mid 70's before. At least on AIDA. Maxxmem on the other hand gets butchered across the board. I go from about 50Gbs bandwidth down to low 30's. And latancy goes up to the 80ns range. Very odd. Meanwhile most benchmarks outside of that show a little bump in performance. Cinebench and the CPU test in 3dMark all see small gains. Makes no sense to me. Everything is more consistent with PF on and all over the place with it off.


----------



## Bloax

Veii said:


> Have to ask @Bloax
> A0 PCB is dangerous (sensitive) and not recommended


The Viper 4000 16-16-16 sticks are really good, and go really fast without any problems (or hassle) as long as your board does Nom/6 Wr/3 Park/6 and procODT 28.2.
CADBus 40-20-30-20, RTP 5 + tWR 10, the rest is whatever runs. (it does RRD 4/4 or 4/6 + WTR 4/8 + tFAW 16 at 4200 no problem)


My problem is more that beyond 4200 single-rank doesn't work on my board/CPU combo, and tRCD doesn't want to go to 14 at 4166 :- )
I suspect it's a great kit for a Ryzen 5500 (iGPU-less 5600g), as it impressively POSTed 4600 16-16-16 on my spare 5800x - and would probably go further.


----------



## 97pedro

Hello guys!

Any idea on how I can improve on this?









Any idea on how to lower TRCDRD from 17 to 16? 16 gives me instant errors on testmem5 even at 1.55v


----------



## hazium233

tRCDRD is part bin luck and part signal integrity, and you have four dimms.

Right now tRCD + tRTP is controlling when precharge happens and lengthen tRC by one clock for read. I would try any of the following things just for the sake of doing it:

Test tRTP 8 or 10 with lowered tRCD
Increase tRAS and tRP together along with tRCD 16 attempt
tRFC up with lowered tRCD
Impedance changes
Just recheck 16-16-16-32-48 at ~1.40 with loosened subs and see what happens

Otherwise if they were looked at individually you might already know if one dimm has weaker scaling and voltage stability compared to others. And if you have idea of which are better than others, then can help to put stronger in the secondary slots (A1 B1) and weaker in primary (A2 B2)

Put a fan on them if you haven't already.

Ultimately 3200C14 is sort of a luck bin where some sticks can be very good, but some may not be so great. I have seen a lot of people have problems dropping to tRCD 16 at 3800 with this bin though.


----------



## Bloax

97pedro said:


> Any idea on how to lower TRCDRD from 17 to 16? 16 gives me instant errors on testmem5 even at 1.55v


just pay2win by trading out your flare-x kits for Patriot Viper 4400 sticks which actually work great in 4x8








as showcased by some gentleman whose name escapes me at the moment, but I'm sure he's still around:









They also work fantastic alongside the Viper 4000 16-16-16 sticks in a 4400-4000-4400-4000 (A0-A1-B0-B1, Bad-Good-Bad-Good slot) config on z690, but I don't know if you can make them work well on AM4 without running different RTT Park (Park/5 on A0/B0, Park/6 on A1/B1) values for the different slots.


----------



## Veii

hazium233 said:


> and lengthen tRC by one clock


tRC is not lengthened on AMD
It will either elapse in the correct time or will be repeaten at the same full ! delay
tRAS will only happen if sensing units decide that enough charge is left and data from X row has been secured before destructive read
this delay before tRP is dynamic but tRP decides the minimum time of it. ***
Sometimes tRAS doesn't need tRP+tRCD delay , if cells have enough charge

tRAS is also not lengthened and not cut, also not auto corrected ~ not directly
tRAS only happens after MSR allows it, which is only after cells have enough charge and everything is secured
If they are not, memory will inject independent-length delay and/or insert tAL calibration delay + tRP delay additional dynamic latency (tAL delay) ~ till everything passes check. Only then tRAS is done and tCAS

tRAS can be missed and has lower hitrate, hence delay is longer and usually tRP (virtual added delay before row [p]recharge)
But in general tRAS and tCAS are identical. Identical priority and identical action
Just again, tRAS is either enough or it's "stopped and waited" , then tRAS elapse (error can happen if allowed tRAS delay still is too short ~ there is no extension or stretching)

tRC same like tCWL. Virtual delay
Just well timed to utilize parallelism ~ but hence read is destructive, a (charge check) before & after ! , has to be done
It's "fine" to let it float half charged and/or stack charge // but these are exploits of auto repeat delay.
tRC will (repeating myself) auto repeat, but not timebreak and not shift.

EDIT:
** *dynamic delay before tRAS will happen and has no direct name ~ maybe just tAL (AL is also a combined name, of several actions calibrated on boot)
tRP is the title that it was given which controls some of the borders. But at the very end, DIMM control unit & vendor settings are intelligent enough (mostly)

EDIT2:
tRAS "can" be as low as possible, but by this time people should know that lower is not better
Efficient transitions are ~ which is simply a result of testing testing testing 
I still don't like to split Read and Write delay paths , and cut them down ~ but that's just me
Soo tRAS optimal is either tRCD *2 or tRCD+tRTP (absolute minimum, but doesn't guarantee good efficiency)


----------



## The Sandman

I need some advice on upgrading to a 32GB kit as I've been out of touch with new memory now available since purchasing FlareX's back in 2017
I run a C6H with a 16GB kit (snip attached below) and recently installed a 5900x.
I'm happy with current performance but hoping to run a 32GB kit at 3800 c14 and maintain something very close or hopefully better than current setup.

I prefer G-Skill but may consider others depending on what the masses tell me.
So far I'm looking at F4-3600C14D-32GTZNA G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 3600 (PC4 28800) Intel XMP 2.0 Desktop Memory Model F4-3600C14D-32GTZNA - Newegg.com
Also looked at Royal's etc and can't decide where to draw the line. The FlareX have been awesome for me but feeling I need a change to play with lol.

Again feeling behind in the times knowledge wise on the memory topic of gen3, is this the way to go (2x16 neo's) or maybe seeing C6H is T-Topography is there a noticeable performance gain going 4x8 over 2x16?

Any opinions are highly appreciated.


----------



## Veii

The Sandman said:


> Again feeling behind in the times knowledge wise on the memory topic of gen3, is this the way to go (2x16 neo's) or maybe seeing C6H is T-Topography is there a noticeable performance gain going 4x8 over 2x16?


T-Topology is better with SR
But 4 dimms increaes the chance of bad batches. RTTs will be different too
B2 (A2) DR PCB on T-Topology is suboptimal but workable
Better to go with 4x A1 or A0 PCB and work on RTTs ~ than increase strain
Unless you plan to update away from the C6H

Ax = SR
Bx = DR


----------



## ReyReverse

Hi, I posted here once. I got no problem with 2T 0 WHEA for 24/7

but I wanna go pure 1T 0-0-0 .
can any pro guide me to 1T?

currently vdimm 1.545v (air cool)
PPT TDC EDC=114-72-105
Boost Override CPU =50Mhz

I've tried set RTT to 6-3-5/6-3-6/6-3-7
ClkDrvStr to 40-20-30-20/40-20-30-24 and raise my vdimm to 1.6v/1.63v Vsoc 1.18v after vdroop

safe to boot 1T 0 WHEA. once I start TM5 tons of error comes out within a minute. HwinFo64 still 0 WHEA but I shut TM5 immediately to avoid BSOD


----------



## Audioboxer

Audioboxer said:


> lol, flashed AGESA 1.2.0.7 beta for my Unify-X and I seem to be getting micro-stutters I wasn't getting before.


False positive, I think.

It appears the constant stuttering I was getting with the CPU under load in some games I tested was possibly shader caching, whatever that is.

Haven't had time to play many games lately but some of the stuff I was testing does some Nvidia caching or something and can apparently be very stuttery to start out with.

I never had any issues with TPM stuttering on any BIOS prior to now, so I didn't really know what it was/what to look for.



The Sandman said:


> I need some advice on upgrading to a 32GB kit as I've been out of touch with new memory now available since purchasing FlareX's back in 2017
> I run a C6H with a 16GB kit (snip attached below) and recently installed a 5900x.
> I'm happy with current performance but hoping to run a 32GB kit at 3800 c14 and maintain something very close or hopefully better than current setup.
> 
> I prefer G-Skill but may consider others depending on what the masses tell me.
> So far I'm looking at F4-3600C14D-32GTZNA G.SKILL Trident Z Neo Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 3600 (PC4 28800) Intel XMP 2.0 Desktop Memory Model F4-3600C14D-32GTZNA - Newegg.com
> Also looked at Royal's etc and can't decide where to draw the line. The FlareX have been awesome for me but feeling I need a change to play with lol.
> 
> Again feeling behind in the times knowledge wise on the memory topic of gen3, is this the way to go (2x16 neo's) or maybe seeing C6H is T-Topography is there a noticeable performance gain going 4x8 over 2x16?
> 
> Any opinions are highly appreciated.
> View attachment 2560054


F4-3600C14D-32GTZNA, that is one of the best kits you can buy now, with the 4000C14 DR kits basically being extinct. 4000C16 might still exist, but a 1.4v rating isn't good for OCing. High change thermal limits are poorer than if you get a kit rated for 1.45~1.55v.

All I would say is it's still an expensive gamble. I briefly had that kit, though it was RipJaws version, and I couldn't do tRCDRD 14 at 3800. Which is quite mental given the bin. But it's likely I was just super unlucky. tRCDRD 14 should really be an _almost_ certainty at 3800 with that kit with the right voltage.

But in the world of memory, you can buy a cheaper kit, like 3200C14 or even 3600C16 or something and still end up being lucky if you goal is something like 3800C14.

If you've got the money to spend though that's likely the best DR bin still being produced for operating at 3800.

Buy any model that isn't RipJaws if you plan on aircooling/not modifying stock heatsinks. It's a crime G.SKILL sell anything with the RipJaws heatsinks. They don't even properly cover the memory chips.


----------



## domdtxdissar

domdtxdissar said:


> Sad if true, like i wrote in that google doc:
> 
> Ok you guys are talking about disabling L2 prefetcher in the AMD CBS biosmenu. I was testing disabling “EnablePrefetcher” in windows which does not help on latency.. I dont have the option to play with L2 prefetcher in my bios so i cant test it for now.. *but this will invalidate all previous results on this google spreadsheet.*
> 
> And it kinda explains "u/zTERRORDACTYL" old 1900:3800 results @ 48.3ns for the 5600x.. cheaters be cheaters 😆


*So what do you guys think "we should answer" the owner of the google doc when he asked the following: ?*


> So what am I supposed to do here? Delete this result? Is there a way to see if the prefetcher was disabled?


I think it would be best to delete all entries which obvious are done with L2 prefetcher disabled.. So far only two entries sticks out to me (together with @TimeDrapery's two newly added ones)
But then we would need to start "policing" the the document for "fake/cheat" prefetcher entries in the future..

Any other point of views/thoughts ?


----------



## The_King

domdtxdissar said:


> *So what do you guys think "we should answer" the owner of the google doc when he asked the following: ?*
> 
> I think it would be best to delete all entries which obvious are done with L2 prefetcher disabled.. So far only two entries sticks out to me (together with @TimeDrapery's two newly added ones)
> But then we would need to start "policing" the the document for "fake/cheat" prefetcher entries in the future..
> 
> Any other point of views/thoughts ?


I have notice another issue that should not be allowed.
Proof of RAM testing/stability should not be provided has a separate pic. It should all be in one single desktop screenshot.

Separate Zentiming and AIDA64 screenshot should not be allowed everything should be in one screenshot including the stability tests.


----------



## MrHoof

The_King said:


> I have notice another issue that should not be allowed.
> Proof of RAM testing/stability should not be provided has a separate pic. It should all be in one single desktop screenshot.
> 
> Separate Zentiming and AIDA64 screenshot should not be allowed everything should be in one screenshot including the stability tests.


Well depends if the proof of stability has Zentimings included aswell as the AIDA64 has zentimings in the screenshot it should be fine.


----------



## KedarWolf

Audioboxer said:


> False positive, I think.
> 
> It appears the constant stuttering I was getting with the CPU under load in some games I tested was possibly shader caching, whatever that is.
> 
> Haven't had time to play many games lately but some of the stuff I was testing does some Nvidia caching or something and can apparently be very stuttery to start out with.
> 
> I never had any issues with TPM stuttering on any BIOS prior to now, so I didn't really know what it was/what to look for.
> 
> 
> 
> F4-3600C14D-32GTZNA, that is one of the best kits you can buy now, with the 4000C14 DR kits basically being extinct. 4000C16 might still exist, but a 1.4v rating isn't good for OCing. High change thermal limits are poorer than if you get a kit rated for 1.45~1.55v.
> 
> All I would say is it's still an expensive gamble. I briefly had that kit, though it was RipJaws version, and I couldn't do tRCDRD 14 at 3800. Which is quite mental given the bin. But it's likely I was just super unlucky. tRCDRD 14 should really be an _almost_ certainty at 3800 with that kit with the right voltage.
> 
> But in the world of memory, you can buy a cheaper kit, like 3200C14 or even 3600C16 or something and still end up being lucky if you goal is something like 3800C14.
> 
> If you've got the money to spend though that's likely the best DR bin still being produced for operating at 3800.
> 
> Buy any model that isn't RipJaws if you plan on aircooling/not modifying stock heatsinks. It's a crime G.SKILL sell anything with the RipJaws heatsinks. They don't even properly cover the memory chips.


My first G.Skill CL14 3600 kit sucked, but I sent it back to Newegg for a second same kit and won the silicon lottery with the second kit.


----------



## MyUsername

Considering these sticks couldn't even post at these timings before water-cooling my memory, I might be in for a chance


----------



## mvdev0

Huhu,

I'm now sure solving my TM5 "TM5 crash! - Thread Error Handler" problem..
Takes days of testing, but it's nothing about RAM timings.

It is because I have setup the W10 OS with to low swap space.

I'm using a 32G system, and set the OS to use only 4GB vRAM.
TM5 is configured at "Testing Window Size = 1150".

Now with 16G pagefile, I never saw this crash again, and I run many test since changing that setting.
Before there was nearly no run without that crash but with no error within TM5.

That black backgrounded desktop icon while running TM5 is done too.. and I can concentrate at timings.

Prime95 points me, where some threads shuts down short after starting and notify about that possibility.

Hope that can help someone too.

cu


----------



## PJVol

domdtxdissar said:


> Is there a way to see if the prefetcher was disabled?
Click to expand...

There's a way to check it from windows.
And even more, it can be turned off and on at any time.


----------



## Prophet4NO1

Turning pre fetch off knocked a chunk off latency. Not sure why that is, but it is. Seems counter intuitive to me, but it is repeatable.


----------



## Audioboxer

KedarWolf said:


> My first G.Skill CL14 3600 kit sucked, but I sent it back to Newegg for a second same kit and won the silicon lottery with the second kit.


Strange that! Just shows you how the 'silicon lottery' is still alive and well with super expensive DDR4 bins.

But I have said numerous times in the past, this is why there has never been a 3800 14-14-14-14 bin sold to retail. It would probably be one of G.SKILLs most popular sellers, but clearly they've never been confident enough to mass produce it for retail.

Closest we got was 3800 14-15-15-15.

Then again, I guess you can basically call the 4000 14-14-14-14 bin the 3800 14-14-14-14 bin. But it went extinct super quick. On sale freely probably for like 6 months or less before stock issues and then what looks like complete discontinuation for DR.

Whether that was just a shift to DDR5, or G.SKILL just couldn't keep producing the DR bins, who knows. The only comment I ever seen on it was a CS rep saying the 4000 16-16-16-16 would be the only bin going forward.


----------



## hazium233

Must have been saving unicorn chips for 5 years to make that bin. But also the improved PCB. I think the latter was why 3800 was 14-16-16.


----------



## Netblock

ReyReverse said:


> View attachment 2560086
> 
> 
> Hi, I posted here once. I got no problem with 2T 0 WHEA for 24/7
> 
> but I wanna go pure 1T 0-0-0 .
> can any pro guide me to 1T?
> 
> currently vdimm 1.545v (air cool)
> PPT TDC EDC=114-72-105
> Boost Override CPU =50Mhz
> 
> I've tried set RTT to 6-3-5/6-3-6/6-3-7
> ClkDrvStr to 40-20-30-20/40-20-30-24 and raise my vdimm to 1.6v/1.63v Vsoc 1.18v after vdroop
> 
> safe to boot 1T 0 WHEA. once I start TM5 tons of error comes out within a minute. HwinFo64 still 0 WHEA but I shut TM5 immediately to avoid BSOD


Tried 60 or 120 ohms for ClkDrvStr?
ProcODT to 36.9 or 40 ohms?
RTTs don't provide much a benefit, if any, to single-rank so you might be fine with just Disabled-Off-5
What are you able to do if you loosten all your timings and then retighten them around 1T-off?


----------



## Veii

Netblock said:


> RTTs don't provide much a benefit, if any, to single-rank so you might be fine with just Disabled-Off-5


Except that you don't leave burn marks on your PCB
Sometimes they can be wiped away, soo it's "nothing" ~ surely 🤭

I surely don't need to run 736 on 1.65v or 637 on 1.68v
It's likely just placeholders 

Aah i wish , i really wish everything was that simple , not having to worry after 1.52v to fry my PCB
"not verifying a change = denying the existence of it"
OCIng would be much easier when resistances didn't matter and XOCer didnt need to change laws of physics , running subzero just so resistance drops and voltage can get another effect
all would be soo much easier, if memory voltage would have a core meaning and resistance + impedances around it would no nothing

Sadly it's not that way 
But you don't notice a change at the very first. Only when you increase voltage too much
Usually you don't notice powering issues either with GDM, soo no RTT or CAD_BUS issue would be noticed that way ~ can't blame this response
But it's not right ~ you oversee a broader spectrum of power balancing *😇*


----------



## Netblock

Veii said:


> Except that you don't leave burn marks on your PCB
> Sometimes they can be wiped away, soo it's "nothing" ~ surely 🤭
> 
> I surely don't need to run 736 on 1.65v or 637 on 1.68v
> It's likely just placeholders
> 
> Aah i wish , i really wish everything was that simple , not having to worry after 1.52v to fry my PCB
> "not verifying a change = denying the existence of it"
> OCIng would be much easier when resistances didn't matter and XOCer didnt need to change laws of physics , running subzero just so resistance drops and voltage can get another effect
> all would be soo much easier, if memory voltage would have a core meaning and resistance + impedances around it would no nothing
> 
> Sadly it's not that way
> But you don't notice a change at the very first. Only when you increase voltage too much
> Usually you don't notice powering issues either with GDM, soo no RTT or CAD_BUS issue would be noticed that way ~ can't blame this response
> But it's not right ~ you oversee a broader spectrum of power balancing *😇*


Burn marks? Termination impedances are on low-current data pins (DQ, DM, DQS_T/DQS_C and TDQS_T/TDQS_C), not high-current power delivery pins. They reduce signal reflection by impedance matching; like how acoustic horns work like. If your stuff is esplodin', something else is going on.

I mean a fancy dynamic ODT (RTT) 'can' help for single-rank, but it's nowhere near as impactful as it is on multi-rank. I do imagine PCB quality has a big say in its usefulness though.


----------



## Veii

Netblock said:


> I mean a fancy dynamic ODT (RTT) 'can' help for single-rank, but it's nowhere near as impactful as it is on multi-rank. I do imagine PCB quality has a big say in its usefulness though.


On Die Termination feature and generally RTTs behave different on dual rank
it's comparing apples to pears ,just because they grow up in the same soil with the same rain

If you have an A0 PCB design, which starts to fail at 1.48-1.52v, and nearly dies at that (we have had dead A0 dimms here, twice already by people following blind established values)
Mine are not much different.
It's not the IC that fails, usually both my A0 and A2 , between micron and samsung (mind you they are different too, you can't expect everyone to follow jedec designs)
A2 Rev.E start to fail at 1.72ish VDIMM, my A0 B-Dies the ICs start to fail at 1.68v
I think i've reached the IC limit but very well see when PCBs fail and when ICs fail

Dimms do die instantly, but it's nearly never the ICs that mess up, but the PCBs they are on
Sadly it's also no direct post from you, but a quote from another source.
Are you sure about what information you quote me with ?

Because it's the high voltage and exactly the termination impedance's, that depend on what amperage arrives to the dimms and how warm they get
Also it's the high input voltage + strong RTTs that leave such burn residues i can not get away. The 4400 kits and a DR 4267 set (A2 and strange A1 PCB) gotten from a friend, all turned useless
He short-benched them at very high voltages following blind research but there are no way to get stable at all (also yes i do own multiple boards and dimms, if you don't know me)
^ everything i quote is my own source, me ~ based on experience  Read couple papers, but reality is always different ~ soo i don't gift them too much importance. We overclock, we don't sit at JEDEC designs

These are by now old photo's
I hope this is all i have to lookup ~ just because you don't believe me


Spoiler: Burn Marks A2 vs A0




































This was on both A2's , SR and DR
DR i could clean away and they where "fine" although were a strange A1 that trained for over 2 minutes (ripjaws)








No burn/oxidation-marks anymore, yet were clear that they had it (cleaning is bothersome and doesn't go away by isopropanol or water)
Cleaning is possible, but all that is not necessary if you just don't follow research blindly
My A0's are perfectly fine to daily 1.65v and my A2 rev.E's in 30° room temp-summer didn't go above 40° without active cooling at 1.68v
Alone that heat differentiates that strongly on RTTs, and i've got a warning that my A0's started to fail at 1.53v (lost channels) ~ i got my lesson , also after messing up @mongoled 's A0's Being equaly resposible for community not knowing what to push and what to lower on over-sensitive weak PCBs 

Gladly we don't have to have the same experience, that's good ~ so we don't have to agree & i'm happy that you have no messed up dimms
But based on my experience and community here, RTTs need a full redo.
Sadly it depends too much on DIMM PCB and Board PCB.
Boardvendors kinda follow AMDs enforced spec, but not always ~ soo sometimes CAD & RTT impedances differ between Vendor's Trace design. So also on Dimms








They differ way to much, without having a clear indicator of the design & it's not easy to establish "new RTTs"
Also especially since NOM and PARK differ by VDIMM range used


----------



## Netblock

Veii said:


> On Die Termination feature and generally RTTs behave different on dual rank
> it's comparing apples to pears ,just because they grow up in the same soil with the same rain
> 
> If you have an A0 PCB design, which starts to fail at 1.48-1.52v, and nearly dies at that (we have had dead A0 dimms here, twice already by people following blind established values)
> Mine are not much different.
> It's not the IC that fails, usually both my A0 and A2 , between micron and samsung (mind you they are different too, you can't expect everyone to follow jedec designs)
> A2 Rev.E start to fail at 1.72ish VDIMM, my A0 B-Dies the ICs start to fail at 1.68v
> I think i've reached the IC limit but very well see when PCBs fail and when ICs fail
> 
> Dimms do die instantly, but it's nearly never the ICs that mess up, but the PCBs they are on
> Sadly it's also no direct post from you, but a quote from another source.
> Are you sure about what information you quote me with ?
> 
> Because it's the high voltage and exactly the termination impedance's, that depend on what amperage arrives to the dimms and how warm they get
> Also it's the high input voltage + strong RTTs that leave such burn residues i can not get away. The 4400 kits and a DR 4267 set (A2 and strange A1 PCB) gotten from a friend, all turned useless
> He short-benched them at very high voltages following blind research but there are no way to get stable at all (also yes i do own multiple boards and dimms, if you don't know me)
> ^ everything i quote is my own source, me ~ based on experience
> 
> These are by now old photo's
> I hope this is all i have to lookup ~ just because you don't believe me
> 
> 
> Spoiler: Burn Marks A2 vs A0
> 
> 
> 
> 
> View attachment 2560290
> 
> View attachment 2560291
> View attachment 2560292
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> This was on both A2's , SR and DR
> DR i could clean away and they where "fine" although where a strange A1 that trained for over 2 minutes (ripjaws)
> View attachment 2560293
> 
> No burn/oxidation-marks anymore, yet where clear that they had it (cleaning is bothersome and doesn't go away by propranolol or water)
> Cleaning is possible, but all that is not necessary if you just don't follow research blindly
> My A0's are perfectly fine to daily 1.65v and my A2 rev.E's in 30° room temp-summer didn't go above 40° without active cooling at 1.68v
> Alone that heat differentiates that strongly on RTTs, and i've got a warning that my A0's started to fail at 1.53v (lost channels) ~ i got my lesson , also after messing up @mongoled 's A0's Being equaly resposible for community not knowing what to push and what to lower on over-sensitive weak PCBs
> 
> Gladly we don't have to have the same experience, that's good ~ so we don't have to agree & i'm happy that you have no messed up dimms
> But based on my experience and community here, RTTs need a fully redo.
> Sadly it depends too much on DIMM PCB and Board PCB.
> Boardvendors kinda follow AMDs enforced spec, but not always ~ soo sometimes CAD & RTT impedances differ between Vendor's Trace design. So also on Dimms
> 
> 
> 
> 
> 
> 
> 
> 
> They differ way to much, without having a clear indicator of the design & it's not easy to establish "new RTTs"
> Also especially since NOM and PARK differ by VDIMM range used


I'm not sure what to look at with those photos. You have a lot of fingerprints on the contact pins.

Oh yea, the design files. Also check out all/all if your archive doesn't have other gens.

I'm also not sure what you're trying to point out. A lower RTT impedance raises DQ's voltage relative to VSSQ (Figure 190 in 79-4D; Figure 239 in Micron 16Gbit DDR4); and DQ already has a high impedance (Table 169; table 133).


----------



## Audioboxer

I managed to nab a 3080/3090 active backplate for £55 on eBay. 2nd hand but hasn't been used. Never do auctions for tech stuff folks unless you have something with a high ceiling. Buy it now or risk losing out. An open box active backplate should have got nearer £90+ as long as unused.

So, I still get to watercool something else after the failed NVMe attempt lmao










It's a sickness I tell you. Once you start watercooling your PC you end up wanting to watercool everything.

Time to redo some bends as well and get rid of right angle pieces.

Even although everyone says no point in watercooling the back of a 3080 the active backplate looks nice and my previous nickel backplate with thermal pads still got warm to the touch. So if passive cooling on the back helps a little, water will help a little more.

The addiction isn't just about performance, it's about driving those temp readings as low as possible!


----------



## Bloax

Personally, then I'm very curious what effect cooling the back-side of the GPU chip has - as the active silicon is on the bottom of the whole "chip" piece, not the protective cover top.

As for RTT talk, then I can only say while I haven't blown up any DIMMs - that misbehaving (not "good") RTT's at high voltage seemed to cause spontaneous _hard_ CPU crashes (blackscreen), which is not a good sign.
Since then I've always tried to massage RTTs as a priority, so I haven't seen any other MISHAPS in this regard. 👋🤡

oh and yes, RTT 5/3/2 (nom/wr/park) on 2x8 b-die seems a little odd








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Any idea on how to lower TRCDRD from 17 to 16? 16 gives me instant errors on testmem5 even at 1.55v :( just pay2win by trading out your flare-x kits for Patriot Viper 4400 sticks which actually work great in 4x8 as showcased by some gentleman whose name escapes me at the moment, but I'm sure...




www.overclock.net




if 6/3/6 or 6/3/7 runs fine, probably just keep it there?
VDDP seems a little high for 2x8 3866, but maybe that's just me stuck in the past of 2x16 4000 running at 0.83v :- )
rdrd/wrwr SCL 2 may just cause problems and no perceivable gain over 4 (is the "usefulness" of this timing still unknown?)

Curiously you also didn't mention trying tCKE 9, which is a rather important thing for no setup delay 1T GDM off - and may very well be _very_ explosive if not set.

I think that's all?

oh right there's also trying raising CPU (VDD) 1.8v 1P8 (Standby Voltage in aSUS speak??) to 1.85-1.93v and bottoming out procODT (28.2) to see if WTRL 8 (and RRDL 4, if it has any benefits??) runs stable - because that's a dirty hack that has worked on several b-die setups I've tried
incorrect 1.8v voltages are either "nothing" or cause occasional errors in TM5 1usmus_v3 #1, (#2 ?maybe?), #10 on settings that _were previously stable_ (i.e. increase 1.8v voltage and bottom out procODT first, decrease WTR/RRD second - otherwise they cause similar errors 🤡)


----------



## ReyReverse

Bloax said:


> Personally, then I'm very curious what effect cooling the back-side of the GPU chip has - as the active silicon is on the bottom of the whole "chip" piece, not the protective cover top.
> 
> As for RTT talk, then I can only say while I haven't blown up any DIMMs - that misbehaving (not "good") RTT's at high voltage seemed to cause spontaneous _hard_ CPU crashes (blackscreen), which is not a good sign.
> Since then I've always tried to massage RTTs as a priority, so I haven't seen any other MISHAPS in this regard. 👋🤡
> 
> oh and yes, RTT 5/3/2 (nom/wr/park) on 2x8 b-die seems a little odd
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Any idea on how to lower TRCDRD from 17 to 16? 16 gives me instant errors on testmem5 even at 1.55v :( just pay2win by trading out your flare-x kits for Patriot Viper 4400 sticks which actually work great in 4x8 as showcased by some gentleman whose name escapes me at the moment, but I'm sure...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> if 6/3/6 or 6/3/7 runs fine, probably just keep it there?
> VDDP seems a little high for 2x8 3866, but maybe that's just me stuck in the past of 2x16 4000 running at 0.83v :- )
> rdrd/wrwr SCL 2 may just cause problems and no perceivable gain over 4 (is the "usefulness" of this timing still unknown?)
> 
> Curiously you also didn't mention trying tCKE 9, which is a rather important thing for no setup delay 1T GDM off - and may very well be _very_ explosive if not set.
> 
> I think that's all?
> 
> oh right there's also trying raising CPU (VDD) 1.8v 1P8 (Standby Voltage in aSUS speak??) to 1.85-1.93v and bottoming out procODT (28.2) to see if WTRL 8 (and RRDL 4, if it has any benefits??) runs stable - because that's a dirty hack that has worked on several b-die setups I've tried
> incorrect 1.8v voltages are either "nothing" or cause occasional errors in TM5 1usmus_v3 #1, (#2 ?maybe?), #10 on settings that _were previously stable_ (i.e. increase 1.8v voltage and bottom out procODT first, decrease WTR/RRD second - otherwise they cause similar errors 🤡)


Hi there
Forgot to mention when I play 1T off will lower all my subtimings included SCL to 4 or even 5


http://imgur.com/E4KYlej

Image from veii 
I ve set my tcke to 10. This helped me to avoid windows startup bsod, I will take your advice to low my VDDP to 0.83v and drop ProcODT to 28.2 and Raise my CPU1.8V to 1.85-1.93 (Hwinfo show default 1.824v)

And RTT yea Ikr, 5/3/2 its weird. but this is the only value I can pass 100cycles 1usmus TM5 and aida64. lol
But I'm pretty sure it won't work at 1T off

And vdimm, I have no idea 1t off . Maybe 1.6v? Or I just need to remain current one?


----------



## Snipie-PT

Looking for an opinion, I'm running 4 sticks of GSkill TridentZ non-RGB, if I run active cooling with fans, it's better to remove the heatsink of the sticks and run naked DIMM's?
What should be the best approach?
Thanks guys!


----------



## Bloax

ReyReverse said:


> And vdimm, I have no idea 1t off . Maybe 1.6v? Or I just need to remain current one?


Whoah buddy, slow down - command rate has no input on voltage requirement. : )
That's almost exclusively primary timing speed (DDR4-4200 easily runs around 1.3v with slow enough primaries) which determines how much voltage you need to bonk it with.
(and higher frequency = faster primary timing for the same value)

Slower command rates are simply more lenient towards suboptimal timing alignments (tRAS or tRC cycles they call them??) - the fastest one (1T vs. 2T vs. 2.5T for GDM on) just requires you to run more proper (lower is not _always better_) RDWR/WRRD, RRD/WTR and technically RDRD/WRWR but I'm not sure about those on AM4.

which really just means "try nudging them around, one by one, maybe more than one-by-one, and see which one performs best"
y-cruncher 2.5 Billion Pi Digit times with a static CPU frequency are good for this


----------



## Audioboxer

Snipie-PT said:


> Looking for an opinion, I'm running 4 sticks of GSkill TridentZ non-RGB, if I run active cooling with fans, it's better to remove the heatsink of the sticks and run naked DIMM's?
> What should be the best approach?
> Thanks guys!


No, the heatsinks are crucial to absorbing the heat. Active cooling with a fan is about getting the heat off the heatsinks as efficiently as possible.


----------



## Bloax

The non-RGB TridentZ heatsinks are surprisingly OK, just remove the plastic insert at the top for slightly better air cooling.


----------



## Snipie-PT

Thanks @Audioboxer and @Bloax for the tips


----------



## St0RM53

Is there is anyone on here with x570 aorus master with 5900x or 5950x b0 stepping and fully stable flck over 1900mhz? I'm on F35b with a 5950x that is fully stable at 1900mhz. However, while i can boot and run 1933/1966/2000 (and possibly higher) without any system crashes i keep getting whea errors no matter what Vsoc, VDDP, VDDG IOD and CCD voltages i try.
Tell me your bios version and to try it out.


----------



## Kuroihane

Hey everyone!

Does anyone here has some knowledge on 4x8GB Hynix DJR kits on Zen 3?

I have recently acquired the kit KF436C16RBK4/32, which were one of the best bins I could find for my money. Other than that I could only find 4000Mhz+ ram which was just too expensive.
Turns out the kit is Hynix DJR, or so Taiphoon says:








But I am unable to run at stock XMP, I get Memtest errors after a few hours, not many though. I also have some weird USB issues, where the controller seems to disconnect/reconnect everything. I get no WHEA errors, which seems to be memory related at this point. Those also causes stuttering and my G603 seems to lose connection sometimes. 

All this doesn't seem to happen at stock clocks on the memory, but then the latency spikes as well as the motherboard just sets the ram to run at 2T.

Previously, I have tried upping the SOC voltage to 1.1V and VDDR to 1.36V, since those are fairly close to the stock XMP ones, to no avail, errors would still happen as well as the weird USB issues.

Is someone familiar with those kits on Ryzen and could lend some time to help?


----------



## Blameless

The_King said:


> I have notice another issue that should not be allowed.
> Proof of RAM testing/stability should not be provided has a separate pic. It should all be in one single desktop screenshot.
> 
> Separate Zentiming and AIDA64 screenshot should not be allowed everything should be in one screenshot including the stability tests.


Everything is ultimately on the honor system.

If someone wants to cheat with their stability results--disadvantaging the community, and themselves, by obscuring real data--there honestly isn't much that can be done to stop them. Most of us have no reason to lie, but if a claim is extreme enough to require special proof, it's probably extreme enough to ignore entirely; there is no prize at stake here.


----------



## Nighthog

@Kuroihane 
Start with providing a screen from Zentimings for your current settings when you boot XMP.
Might be your board just setts something wrong with AUTO settings that could be easily seen if we see what it does.


----------



## mvdev0

Sorry that question, I'm confused..

Is

tWR = tRTP*2 (SR) OR tRTP*4 (DR)

OR

tWR = tCL(+N)

right, or both false / not optimal? For next bench/stability test I setup tRTP=8 and tWR=16, so I follow tWR=tCL on a DR setup.


----------



## Audioboxer

Audioboxer said:


> I managed to nab a 3080/3090 active backplate for £55 on eBay. 2nd hand but hasn't been used. Never do auctions for tech stuff folks unless you have something with a high ceiling. Buy it now or risk losing out. An open box active backplate should have got nearer £90+ as long as unused.
> 
> So, I still get to watercool something else after the failed NVMe attempt lmao
> 
> View attachment 2560302
> 
> 
> It's a sickness I tell you. Once you start watercooling your PC you end up wanting to watercool everything.
> 
> Time to redo some bends as well and get rid of right angle pieces.
> 
> Even although everyone says no point in watercooling the back of a 3080 the active backplate looks nice and my previous nickel backplate with thermal pads still got warm to the touch. So if passive cooling on the back helps a little, water will help a little more.
> 
> The addiction isn't just about performance, it's about driving those temp readings as low as possible!


So I can confirm active backplate changes on a 3080 are minimal, but not 'nothing'. Memory junction runs cooler and core tends to be between 1~3 degrees lower depending on wattage load.

Restriction wise, marginal changes. There isn't a dense fin-stack or anything on the backplate block. But that's now me with 4 rads, 4 blocks and 1 D5 lol. People on Reddit severely underestimate the power of a single D5 pump.

Unless you are obsessed with running it down at like 40~60% or something. I find 80% a good point for me now in terms of noise and flow.

All in all I'd say the biggest benefit for watercooling outwith GPU and CPU has been on memory, especially if you have B-die. I'd prioritise getting a water block for your memory over an active backplate (unless you have memory chips to cool) and NVMe (really not needed). My memory basically tracks water temp now to a few degrees max. Which means even on a 600w power supply load and all rads intake, my memory will be at like 33/34 degrees if water temp is 30~31 degrees.


----------



## Kuroihane

Nighthog said:


> @Kuroihane
> Start with providing a screen from Zentimings for your current settings when you boot XMP.
> Might be your board just setts something wrong with AUTO settings that could be easily seen if we see what it does.











There you go, after looking hard at the timings and XMP profile, I noticed that tRC and tFAW seems a bit different, tRC is 85 and TFAW 36 in XMP. tRFC is also 631 instead of 630.

Other than that, I don't think there were more timings related to it. I was able to somewhat stabilize the 3600 XMP settings pushing 1.37V on the ram. Sadly, this motherboard does not seem to have a VDDR readout...

I ran MemtestPro overnight and it got to around 1100% without errors. I also noticed less stuttering and the USB issues didn't happen after a restart yet.

Is there any timings that might be wrong since it's needing more voltage than stock XMP? Should I change the timings above to the XMP sheet?


----------



## hazium233

mvdev0 said:


> Sorry that question, I'm confused..
> 
> Is
> 
> tWR = tRTP*2 (SR) OR tRTP*4 (DR)
> 
> OR
> 
> tWR = tCL(+N)
> 
> right, or both false / not optimal? For next bench/stability test I setup tRTP=8 and tWR=16, so I follow tWR=tCL on a DR setup.


It is tWR = 2x tRTP, which is a relationship for the setting in MR0 of the ddr for read or write with auto-precharge commands since the timings share the same address bits.

But you can set them to a different relationship if you want.



Kuroihane said:


> View attachment 2560387
> 
> 
> There you go, after looking hard at the timings and XMP profile, I noticed that tRC and tFAW seems a bit different, tRC is 85 and TFAW 36 in XMP. tRFC is also 631 instead of 630.
> 
> Other than that, I don't think there were more timings related to it. I was able to somewhat stabilize the 3600 XMP settings pushing 1.37V on the ram. Sadly, this motherboard does not seem to have a VDDR readout...
> 
> I ran MemtestPro overnight and it got to around 1100% without errors. I also noticed less stuttering and the USB issues didn't happen after a restart yet.
> 
> Is there any timings that might be wrong since it's needing more voltage than stock XMP? Should I change the timings above to the XMP sheet?


XMP for those is "3602" MT/s, so that is part of why tRFC gets calculated to 631 instead of 630.

tRC through tFAW usually just get calculated from base speed nanoseconds on AM4 rather than loaded from the XMP values.

My G.Skill 3600 kits do the same thing since they are "3602" MT/s, and tRC is 80 something instead of 52 for the CL16 or 50 for CL15.

Were these a kit of 4x8, or individual? You would probably be ok through at least 1.45V if needed if these are really DJR, if somehow CJR might be better to work at 1.4. tRCD and tRP probably won't want to move much.


----------



## Kuroihane

hazium233 said:


> XMP for those is "3602" MT/s, so that is part of why tRFC gets calculated to 631 instead of 630.
> 
> tRC through tFAW usually just get calculated from base speed nanoseconds on AM4 rather than loaded from the XMP values.
> 
> My G.Skill 3600 kits do the same thing since they are "3602" MT/s, and tRC is 80 something instead of 52 for the CL16 or 50 for CL15.
> 
> Were these a kit of 4x8, or individual? You would probably be ok through at least 1.45V if needed if these are really DJR, if somehow CJR might be better to work at 1.4. tRCD and tRP probably won't want to move much.


Thank you for looking out!

Those are a kit, 4x8. I noticed that the box they came in are like 2 boxes of 2x8, so I am not too sure if there are differences on that.

Either way, I did an attempt at clocking it higher. I really wanted it to get to at least 3800 Mhz with a decent latency, but even up to 1.45V and loosening CL to 18 I could barely boot to windows before getting a BSOD, even had a random bricked BIOS message from the motherboard come up.

Maybe it is a very low bin DJR or just too many DIMMs for this Motherboard. I used to have B-Dies XMP at 3200 CL15. I was able to get to 3800 CL16 just using the Ryzen Ramcalc with that G.Skill kit, but it was 2x8 and recently 16GB has not been enough for me, hence why I tried to upgrade.

I did keep the other primary timings fairly "standard", the last setting I tried that booted to windows, but then had a BSOD was 18-20-20-40, rest on Auto. SOC had LLC at Level 2 and 1.112V, reporting dead on 1.1V on softwares, I could about load HWInfo before the crash happened.


----------



## Nighthog

Kuroihane said:


> Thank you for looking out!
> 
> Those are a kit, 4x8. I noticed that the box they came in are like 2 boxes of 2x8, so I am not too sure if there are differences on that.
> 
> Either way, I did an attempt at clocking it higher. I really wanted it to get to at least 3800 Mhz with a decent latency, but even up to 1.45V and loosening CL to 18 I could barely boot to windows before getting a BSOD, even had a random bricked BIOS message from the motherboard come up.
> 
> Maybe it is a very low bin DJR or just too many DIMMs for this Motherboard. I used to have B-Dies XMP at 3200 CL15. I was able to get to 3800 CL16 just using the Ryzen Ramcalc with that G.Skill kit, but it was 2x8 and recently 16GB has not been enough for me, hence why I tried to upgrade.
> 
> I did keep the other primary timings fairly "standard", the last setting I tried that booted to windows, but then had a BSOD was 18-20-20-40, rest on Auto. SOC had LLC at Level 2 and 1.112V, reporting dead on 1.1V on softwares, I could about load HWInfo before the crash happened.


Try a looser tRCDRD... 21...22... or even 23 Might be low bin kits.


----------



## The_King

Bought a ton of Crucial Ballistix MAX RAM recently. Some promising results form early testing. 32GB Take a long time to test. 
Seems this is C9BLJ Micron B-Die


----------



## Kuroihane

Nighthog said:


> Try a looser tRCDRD... 21...22... or even 23 Might be low bin kits.


Thanks again for helping! 

I just tried that now, 21 didn't even get past booting, 22 and 23 got past booting and crashed into windows, just same as before, using 1.45V.

I decided to try setting things slowly to auto to see what the MB would train for, and the results were quite absurd. It does make me wonder how this runs at CL 16 3600.

At those timings, I honestly didn't bother trying to boot, but it was a slightly better situation than not even getting past the memory checks and into the Bios as it did before.

































I understand the motherboard isn't too happy training 4 dimms like that, but does the timings indicate this could be some other type of IC? I wonder which though. I tried throwing the exported Thaiphoon file into Dramcalc and it claims this is a "good overclocking memory" about the timings (don't think this makes that huge of a difference though).

At this point, is there anything else I should try for?


----------



## The Sandman

Why does this show Samsung D Die for F4-3600C14Q-32GTZNA G.SKILL Trident Z Neo Series 32GB (4 x 8GB) 288-Pin PC RAM DDR4 3600 (PC4 28800) Intel XMP 2.0 Desktop Memory Model F4-3600C14Q-32GTZNA - Newegg.com
Perhaps I'm misreading or plain not "in the know" about something?


----------



## hazium233

Kuroihane said:


> Thanks again for helping!
> 
> I just tried that now, 21 didn't even get past booting, 22 and 23 got past booting and crashed into windows, just same as before, using 1.45V.
> 
> I decided to try setting things slowly to auto to see what the MB would train for, and the results were quite absurd. It does make me wonder how this runs at CL 16 3600.
> 
> At those timings, I honestly didn't bother trying to boot, but it was a slightly better situation than not even getting past the memory checks and into the Bios as it did before.
> 
> View attachment 2560419
> View attachment 2560420
> View attachment 2560421
> View attachment 2560422
> View attachment 2560423
> 
> 
> I understand the motherboard isn't too happy training 4 dimms like that, but does the timings indicate this could be some other type of IC? I wonder which though. I tried throwing the exported Thaiphoon file into Dramcalc and it claims this is a "good overclocking memory" about the timings (don't think this makes that huge of a difference though).
> 
> At this point, is there anything else I should try for?


Maybe the default ProcODT or RTT aren't very good for four dimms in your case. You could try ProcODT up or down a step, I would think Hynix could like 40. I don't know if B550-F might like something different for RTT.

If tRCD 22t doesn't work for 3733 or 3800, it is probably not the problem. Make sure you are also using tRP 22 - 23. You can try setting WRWRDD to 9t if that isn't what the motherboard tries to train anyway. Most other stuff is pretty high.

Might also check SOC up to 1.125. I think VDDG and VDDP could be adjusted, but I don't think they are necessarily your problem.

For four dimms it probably saves some headache if you can take the time to test each one at a time and figure out what they can overclock to (and secondarily make sure one isn't weak or faulty if not tested already).

This may not matter but try the VRM settings back on Auto. I didn't have very good luck with phase control "Optimized" on my Asus X370, but also 200 for switching frequency seems like it is lower than what I would expect for default (if it is in kHz).



The Sandman said:


> Why does this show Samsung D Die for F4-3600C14Q-32GTZNA G.SKILL Trident Z Neo Series 32GB (4 x 8GB) 288-Pin PC RAM DDR4 3600 (PC4 28800) Intel XMP 2.0 Desktop Memory Model F4-3600C14Q-32GTZNA - Newegg.com
> Perhaps I'm misreading or plain not "in the know" about something?
> 
> View attachment 2560448


Because most dimms don't have the die stepping / revision programmed into the SPD. I have no idea why thaiphoon makes this particular guess though. Those are B-die.

For G.Skill, look at the code on the heatspreader label starting with 042. It will end 8810B for 8Gbit Samsung B-die.

edit for typos


----------



## Kuroihane

hazium233 said:


> Maybe the default ProcODT or RTT aren't very good for four dimms in your case. You could try ProcODT up or down a step, I would think Hynix could like 40. I don't know if B550-F might like something different for RTT.
> 
> If tRCD 22t doesn't work for 3733 or 3800, it is probably not the problem. Make sure you are also using tRP 22 - 23. You can try setting WRWRDD to 9t if that isn't what the motherboard tries to train anyway. Most other stuff is pretty high.
> 
> Might also check SOC up to 1.125. I think VDDG and VDDP could be adjusted, but I don't think they are necessarily your problem.
> 
> For four dimms it probably saves some headache if you can take the time to test each one at a time and figure out what they can overclock to (and secondarily make sure one isn't weak or faulty if not tested already).
> 
> This may not matter but try the VRM settings back on Auto. I didn't have very good luck with phase control "Optimized" on my Asus X370, but also 200 for switching frequency seems like it is lower than what I would expect for default (if it is in kHz).


I might actually try to get the single dimm testing done. I was using the XMP @ 1.37V, while I don't get any errors, WHEA or whatever, I see stutter happening in moving my mouse at certain situations. I also noticed that it affects both my Logitech G533 and G603, I heard that the audio would stutter at those times on the headphones, so I am not really sure what could be the issue.

Everything was fine just before the GPU + RAM Swap I did recently, I upgraded my GTX 980 to the 6700 XT too (I don't think the GPU could actually be part of those problems), the stutter takes place in game sometimes, where audio and input lag can be noticed, but no FPS issues, SAM is turned in.

My first hunch was the memory, as it usually affects many things system wide. HCI Memtest at 3600/1.37V didn't show a single error on over 1100% test on each thread, but those stutters are really getting to me now. I just formatted my PC, as soon as it restarted for some drivers, the G533 dongle had a USB issue and didn't get recognized (happened most of the times while the RAM is overclocked) but then I noticed the same stutters when the RAM is not, no USB/Driver issues while not OCd yet though.

The 200 khz setting for the BIOS is default, it defaults at Optimized too. I can ramp up the VRM frequencies to 350 at maximum. Which software to test the dimms? Memtest86? HCI?

TL;DR: Still getting stutter even while the ram is not OCd (but less), resetted BIOS, even formatted the PC to no avail. Issues began after upgrading the PC Ram and GPU. I have a Seasonic 750W Prime Gold PSU. Sorry for throwing so many questions... I am just a bit afraid if I'd need to go through RMA in here, it's always not a pleasant experience where I live.

Edit: I went to the BIOS again and reflashed it to make sure just now.


----------



## hazium233

Kuroihane said:


> I might actually try to get the single dimm testing done. I was using the XMP @ 1.37V, while I don't get any errors, WHEA or whatever, I see stutter happening in moving my mouse at certain situations. I also noticed that it affects both my Logitech G533 and G603, I heard that the audio would stutter at those times on the headphones, so I am not really sure what could be the issue.
> 
> Everything was fine just before the GPU + RAM Swap I did recently, I upgraded my GTX 980 to the 6700 XT too (I don't think the GPU could actually be part of those problems), the stutter takes place in game sometimes, where audio and input lag can be noticed, but no FPS issues, SAM is turned in.
> 
> My first hunch was the memory, as it usually affects many things system wide. HCI Memtest at 3600/1.37V didn't show a single error on over 1100% test on each thread, but those stutters are really getting to me now. I just formatted my PC, as soon as it restarted for some drivers, the G533 dongle had a USB issue and didn't get recognized (happened most of the times while the RAM is overclocked) but then I noticed the same stutters when the RAM is not, no USB/Driver issues while not OCd yet though.
> 
> The 200 khz setting for the BIOS is default, it defaults at Optimized too. I can ramp up the VRM frequencies to 350 at maximum. Which software to test the dimms? Memtest86? HCI?
> 
> TL;DR: Still getting stutter even while the ram is not OCd (but less), resetted BIOS, even formatted the PC to no avail. Issues began after upgrading the PC Ram and GPU. I have a Seasonic 750W Prime Gold PSU. Sorry for throwing so many questions... I am just a bit afraid if I'd need to go through RMA in here, it's always not a pleasant experience where I live.


Testmem 5, you can look in this link to a topic about it with config files. HCI is good, if it did 1000% per thread than that is pretty thorough.

Neither of those tests the fabric, if you do not have WHEA, you can still try adjusting voltages (VDDG CCD may be able to go down, IOD may be ok) and see if they help. Geekbench 5 could be used for the voltage steps. The CLDO VDDP may be ok. You can also look at "CPU 1.8 Voltage" and see if small steps up make a difference.

Can also try SAM off, or also check PCIe set to Gen 3 manually to see if that helps.

I don't know what sort of bugs Asus has in different versions of their B550-F bioses, but it is a common motherboard so someone that has one may be able to help with that.


----------



## Kuroihane

hazium233 said:


> Testmem 5, you can look in this link to a topic about it with config files. HCI is good, if it did 1000% per thread than that is pretty thorough.
> 
> Neither of those tests the fabric, if you do not have WHEA, you can still try adjusting voltages (VDDG CCD may be able to go down, IOD may be ok) and see if they help. Geekbench 5 could be used for the voltage steps. The CLDO VDDP may be ok. You can also look at "CPU 1.8 Voltage" and see if small steps up make a difference.
> 
> Can also try SAM off, or also check PCIe set to Gen 3 manually to see if that helps.
> 
> I don't know what sort of bugs Asus has in different versions of their B550-F bioses, but it is a common motherboard so someone that has one may be able to help with that.


Seriously thank you for providing so much insight and taking your time.

After the BIOS reset I did I left SAM off... But there's a catch, I noticed I am on a Beta BIOS, at this point I can't even recall if I upgraded it via the Asus APP or actually flashed it.

I will continue testing the stutter issues, since that seems to be the biggest problem now. If they go away with SAM off, that's good enough. Sadly this version isn't too popular. There's the 550-F Wifi and Wifi II, the Wifi II's only difference is launch date and the integrated Wifi (it uses mediatek instead of Intel). I complained about this motherboard not having a Memory Voltage readout to Asus, they said the issue could be that 'The memory wasn't QVL'. They didn't tell me if there was either no sensor or if there just wasn't programming/BIOS to read it.

But the Bioses are "different" for some reason.


----------



## The_King

Will need a Zen 3 CPU to unlock more from this kit. Overall not bad for a 32GB kit.


----------



## Kha

Gigabyte 1.2.0.7 bios for B550 Master, I assume the X570 gets same treatment. Flashed mine and appears ok so far.


----------



## St0RM53

X570 Aorus master rev 1.1 here, F35b (Agesa 1.2.0.3b), 5950x, crucial ballistix 2x32gb micron 16gb rev B 3600c16 kit. I've been running 1900mhz 1:1:1 getting 61.7ns latency on just auto timings and 1.35v, 1T, GDM enabled with over 10000% karhu coverage. I finally decided to tighten the timings since now there is more info on this die. Big story short basically even with loose timings Geardown mode disabled (at least at 3800mhz, didn't try lower frequency) will not boot at all, or get stuck at the post screen. I thought it only rounded timings but it seems it does more things. Why is that and what do you recommend on doing? 

here are the auto loose timings that have been running stably for ages as reference:


----------



## hazium233

Kuroihane said:


> Seriously thank you for providing so much insight and taking your time.
> 
> After the BIOS reset I did I left SAM off... But there's a catch, I noticed I am on a Beta BIOS, at this point I can't even recall if I upgraded it via the Asus APP or actually flashed it.
> 
> I will continue testing the stutter issues, since that seems to be the biggest problem now. If they go away with SAM off, that's good enough. Sadly this version isn't too popular. There's the 550-F Wifi and Wifi II, the Wifi II's only difference is launch date and the integrated Wifi (it uses mediatek instead of Intel). I complained about this motherboard not having a Memory Voltage readout to Asus, they said the issue could be that 'The memory wasn't QVL'. They didn't tell me if there was either no sensor or if there just wasn't programming/BIOS to read it.
> 
> But the Bioses are "different" for some reason.


I didn't know they made a new revision, that's interesting. What AGESA was v 0305 (first release)? Had you used that bios before?

Are you on Windows 11? Stutter could also be from TPM, I don't know if it was really fixed for everyone. I have stayed on 10.

Are you using the Mediatek wifi or Intel Lan? One or other could maybe also be an issue.



Kha said:


> Gigabyte 1.2.0.7 bios for B550 Master, I assume the X570 gets same treatment. Flashed mine and appears ok so far.


1207 still has voltage limit lowered with raised EDC?


----------



## GRABibus




----------



## Sam_Oslo

Kha said:


> Gigabyte 1.2.0.7 bios for B550 Master, I assume the X570 gets same treatment. Flashed mine and appears ok so far.


The latest BIOS of my Gigabyte B550 VISION D says 1.2.0.7 too, but I thought maybe it was a typos. So Gigabyte has released the final version of AGESA.


----------



## mongoled

Veii said:


> i got my lesson , also after messing up @mongoled 's A0's Being equaly resposible for community not knowing what to push and what to lower on over-sensitive weak PCBs


Bro

sacrifices must be made

🤣🤣

Seriously, we have come along a long way since then, in particular yourself 😃😃


----------



## mongoled

Audioboxer said:


> I managed to nab a 3080/3090 active backplate for £55 on eBay. 2nd hand but hasn't been used. Never do auctions for tech stuff folks unless you have something with a high ceiling. Buy it now or risk losing out. An open box active backplate should have got nearer £90+ as long as unused.
> 
> So, I still get to watercool something else after the failed NVMe attempt lmao
> 
> View attachment 2560302
> 
> 
> It's a sickness I tell you. Once you start watercooling your PC you end up wanting to watercool everything.
> 
> Time to redo some bends as well and get rid of right angle pieces.
> 
> Even although everyone says no point in watercooling the back of a 3080 the active backplate looks nice and my previous nickel backplate with thermal pads still got warm to the touch. So if passive cooling on the back helps a little, water will help a little more.
> 
> The addiction isn't just about performance, it's about driving those temp readings as low as possible!


It's a sickness of the mind

😍😍


----------



## mongoled

Bloax said:


> just pay2win by trading out your flare-x kits for Patriot Viper 4400 sticks which actually work great in 4x8
> View attachment 2560047
> 
> as showcased by some gentleman whose name escapes me at the moment, but I'm sure he's still around:
> View attachment 2560048
> 
> 
> They also work fantastic alongside the Viper 4000 16-16-16 sticks in a 4400-4000-4400-4000 (A0-A1-B0-B1, Bad-Good-Bad-Good slot) config on z690, but I don't know if you can make them work well on AM4 without running different RTT Park (Park/5 on A0/B0, Park/6 on A1/B1) values for the different slots.


Those must be mine 😃😃


----------



## Kuroihane

hazium233 said:


> I didn't know they made a new revision, that's interesting. What AGESA was v 0305 (first release)? Had you used that bios before?
> 
> Are you on Windows 11? Stutter could also be from TPM, I don't know if it was really fixed for everyone. I have stayed on 10.
> 
> Are you using the Mediatek wifi or Intel Lan? One or other could maybe also be an issue.


Honestly, the board came with 0305, but I can't recall the AGESA version, I would say it was 1.2.0.4 or .6.

So, after reflashing the BIOS and keeping SAM disabled, it seems like there was improvement. I left HCI running overnight as always, this time, I changed some of the LLC and Phase controls. Got to nearly 1000% apart from the last thread, that for some reason lagged behind. The phase control I changed it to Manual and set it to "Fast". I think in case of this motherboard, the Switching frequencies are doubled as I am almost sure this MB uses doublers for it's phases, so 200 khz should be 400 instead, 350 which is the max config would be 700, does that sound more accurate?

I will run some tests today while gaming and see if I get stutters. Then maybe I will try increasing the memory freq to 3800 again.








Once again, thank you so much for your insight on this!


----------



## nevartojau

What can I tighten more?

CL14 requires too much voltage to my taste for daily driver, is there anything I can improve while keeping CL16?


----------



## KedarWolf

nevartojau said:


> View attachment 2560613
> View attachment 2560610
> View attachment 2560611
> View attachment 2560612
> 
> View attachment 2560609
> 
> View attachment 2560608
> 
> 
> 
> 
> 
> What can I tighten more?
> 
> CL14 requires too much voltage to my taste for daily driver, is there anything I can improve while keeping CL16?


I dunno if you can really compare the y-cruncher, I have a 5950x.


----------



## Kuroihane

So... @hazium233 

I am just tagging you because you've been helping me so much, I'd figure you'd be interested in an update on the lagging issues.

After much, much fidgeting and me almost going nuts on this (since the lags really seemed like unstable memory issues, as the mouse cursor would lag, then "teleport" somewhere and the headset would crackle/cut sound...)

I decided to try everything. I reset the BIOS, began trying from 0, unplugged all USB things, began plugging one by one. Everything seemed to work fairly fine, until the mice was in game.

I have a G603, which is both wireless with it's adapter and bluetooth. But aparently, the receiver had some issues and that was causing all the lags, delays and even USB disconnects I was getting. The sound device is another Logitech device, a G533 Wireless...

I don't even know how such a thing can happen, but I guess the receiver fried somewhere along this past week of me attempting to stabilize/improve my RAM OC. Either that or it just decided to commit sudoku.

Removed the receiver, connected the mouse via Bluetooth... No more lags (besides the bluetooth ofc), headset and sound works fine, there's no big delays or jumping of the cursor around anymore.

I already reached out to Logitech, as they usually have an amazing CS and Warranty, I am now waiting for a final response from them, it's under analysis.

With all that said, the ram is stable. The lags were caused by a single USB dork...dongle. My dumb-self honestly never imagined a single receiver could cause so much headache...


----------



## Kha

hazium233 said:


> 1207 still has voltage limit lowered with raised EDC?


Didn't try it myself, but it's been reported on tweaktown that "setting VDDG and VDDP above 1.0V works".


----------



## Blameless

nevartojau said:


> View attachment 2560613
> View attachment 2560610
> View attachment 2560611
> View attachment 2560612
> 
> View attachment 2560609
> 
> View attachment 2560608
> 
> 
> 
> 
> 
> What can I tighten more?
> 
> CL14 requires too much voltage to my taste for daily driver, is there anything I can improve while keeping CL16?


tRC should be tRP + tRAS and can probably go down to 40; if it can't your tRP or tRAS are probably too tight. tRDWR and especially tRTP can likely be reduced; tWR should be double tRTP.

SCLs below 4 are infrequently beneficial. A few tests may see improvement, but most will be the same or slightly worse.

Have you tried disabling GDM? This might require adjustment to Rtts.


----------



## mvdev0

I'm in the process setup stable timings at 1900MHz 1:1.

There must be something I miss.. I'm at the stage I want find
the correct vDIMM and ProcODT, so I lowering vDIMM until
MemTest86 (test8) producing errors.

What I really do not understand.. if I find that value in one run,
1.42V and 36.9 Ohm with 15+ errors, I go back to 1.44V, 36.9 Ohm,
sometimes the Board restarts one or two times, or I have to
disconect power and reload the profile.. AND now I CAN go
as low as 1.42V without ANY error..

Is that because there is some training that allows now going so deep?

If I read out Zen Timings, it shows exactly the values entered in UEFI.

Thanks!


EDIT : Same with booting Windows.. last setups no POST is possible <=1.42V, now I can
and the system boots into OS


----------



## Ramad

mvdev0 said:


> I'm in the process setup stable timings at 1900MHz 1:1.
> 
> There must be something I miss.. I'm at the stage I want find
> the correct vDIMM and ProcODT, so I lowering vDIMM until
> MemTest86 (test8) producing errors.
> 
> What I really do not understand.. if I find that value in one run,
> 1.42V and 36.9 Ohm with 15+ errors, I go back to 1.44V, 36.9 Ohm,
> sometimes the Board restarts one or two times, or I have to
> disconect power and reload the profile.. AND now I CAN go
> as low as 1.42V without ANY error..
> 
> Is that because there is some training that allows now going so deep?
> 
> If I read out Zen Timings, it shows exactly the values entered in UEFI.
> 
> Thanks!
> 
> 
> EDIT : Same with booting Windows.. last setups no POST is possible <=1.42V, now I can
> and the system boots into OS


RTT values could be changing while RAM training on boot if left on AUTO, you can try locking them to RZQ/7-RZQ/3-RZQ/1 or any other combination that works for your RAM (my understanding is that you have a dual-rank B-die sticks), then find and use the lowest PROCODT value.


----------



## nevartojau

Blameless said:


> tRC should be tRP + tRAS and can probably go down to 40; if it can't your tRP or tRAS are probably too tight. tRDWR and especially tRTP can likely be reduced; tWR should be double tRTP.
> 
> SCLs below 4 are infrequently beneficial. A few tests may see improvement, but most will be the same or slightly worse.
> 
> Have you tried disabling GDM? This might require adjustment to Rtts.


Thanks for the tips!
Messed around a little bit more, had to increase voltage to 1.55V to get this working. 
Did not try the GDM off yet. I hope it won't require more voltage or I have to leave it as it is.


----------



## hazium233

Kha said:


> Didn't try it myself, but it's been reported on tweaktown that "setting VDDG and VDDP above 1.0V works".


Thanks for reporting, but I meant the one where core VID limit drops if you set EDC over specification, starting in 1205. So for me on 5600X it changed 1.45 to 1.375, IIRC. "Working as intended" probably.

MSI hasn't released 1207 for my motherboard yet, they did the X570S ones first I think.


Kuroihane said:


> With all that said, the ram is stable. The lags were caused by a single USB dork...dongle. My dumb-self honestly never imagined a single receiver could cause so much headache...


 Ha, damn peripherals.


----------



## VPII

KedarWolf said:


> I dunno if you can really compare the y-cruncher, I have a 5950x.
> 
> View attachment 2560626
> 
> 
> View attachment 2560627
> 
> 
> View attachment 2560628


Hi @KedarWolf interestingly I have the exact same memory you have but for some reason I cannot do Command Rate 1T without GDM enabled, I've tried various settings but it just won't work, I'm using the older MSI Meg X570 Ace motherboard but these two boards should be more or less the same. I'm also using the same CPU.


----------



## KedarWolf

VPII said:


> Hi @KedarWolf interestingly I have the exact same memory you have but for some reason I cannot do Command Rate 1T without GDM enabled, I've tried various settings but it just won't work, I'm using the older MSI Meg X570 Ace motherboard but these two boards should be more or less the same. I'm also using the same CPU.
> View attachment 2560682


My first kit of that RAM sucked. I sent it back to Newegg for a second exact same kit. The second one I won the silicon lottery I think.


----------



## 97pedro

Hello all,

Currently I have a 3200mhz G skill flare x kit CL14 b die, running at 3800mhz 14-17-14-22 at 1.5v.

You guys think if the F4-3600C14D-16GVKA would be a nice upgrade? Should be, but by how much?

Or the F4-3600C16D-16GTZR, its cheaper and also b die, would it also be an upgrade?


----------



## Blackfyre

97pedro said:


> Hello all,
> 
> Currently I have a 3200mhz G skill flare x kit CL14 b die, running at 3800mhz 14-17-14-22 at 1.5v.
> 
> You guys think if the F4-3600C14D-16GVKA would be a nice upgrade? Should be, but by how much?
> 
> Or the F4-3600C16D-16GTZR, its cheaper and also b die, would it also be an upgrade?


What CPU & Motherboard do you have?

If you're already pushing 3800 Mhz (1900Mhz FCLK, UCLK & MCLK) with those timings, you're likely very close to the ceiling anyway for your memory controller, etc.

IMO *not worth* upgrading at all, unless you have a CPU & Combo known for being able to push 2000+ FCLK otherwise you'd have to get super lucky with it to push to even 2000Mhz FCLK with most Ryzen chips.


----------



## 97pedro

Blackfyre said:


> What CPU & Motherboard do you have?
> 
> If you're already pushing 3800 Mhz (1900Mhz FCLK, UCLK & MCLK) with those timings, you're likely very close to the ceiling anyway for your memory controller, etc.
> 
> IMO *not worth* upgrading at all, unless you have a CPU & Combo known for being able to push 2000+ FCLK otherwise you'd have to get super lucky with it to push to even 2000Mhz FCLK with most Ryzen chips.


My kit can run the same settings I use at 3800mhz but at 3866mhz if I have a fan pointed at them.

Just don't know how I can have a permanent ram cooling solution


----------



## nevartojau

97pedro said:


> Hello all,
> 
> Currently I have a 3200mhz G skill flare x kit CL14 b die, running at 3800mhz 14-17-14-22 at 1.5v.
> 
> You guys think if the F4-3600C14D-16GVKA would be a nice upgrade? Should be, but by how much?
> 
> Or the F4-3600C16D-16GTZR, its cheaper and also b die, would it also be an upgrade?


I'm running 2 kits like that with 5900X. You see my timings in the previous comment. I have to run it at 1.55V or it's unstable. But I have 4DIMMS. 
I have 2 fan cooler on my RAM though. Under TM5 anta777 Absolut it reaches like 41 - 42 C and in a gaming session it's like 35 C.


----------



## 97pedro

nevartojau said:


> I'm running 2 kits like that with 5900X. You see my timings in the previous comment. I have to run it at 1.55V or it's unstable. But I have 4DIMMS.
> I have 2 fan cooler on my RAM though. Under TM5 anta777 Absolut it reaches like 41 - 42 C and in a gaming session it's like 35 C.


Do you mind sharing a picture of how it looks with the ram cooler?

My ram is exactly the same as yours but I can't get RCDRD lower than 17.. But also, I have worst settings than you but lower NS.


----------



## nevartojau

97pedro said:


> Do you mind sharing a picture of how it looks with the ram cooler?
> 
> My ram is exactly the same as yours but I can't get RCDRD lower than 17.. But also, I have worst settings than you but lower NS.


What latency do you get on Aida? I'm getting 54.9 - 55.0ns.
The cooler is Corsair Dominator Airflow. I only bought it for esthetics to match the rest of the build. You can 3D print a frame and slap on a 120mm fan if you have space for it and don't care too much about the looks and it will perform even better than my cooler.


----------



## St0RM53

St0RM53 said:


> X570 Aorus master rev 1.1 here, F35b (Agesa 1.2.0.3b), 5950x, crucial ballistix 2x32gb micron 16gb rev B 3600c16 kit. I've been running 1900mhz 1:1:1 getting 61.7ns latency on just auto timings and 1.35v, 1T, GDM enabled with over 10000% karhu coverage. I finally decided to tighten the timings since now there is more info on this die. Big story short basically even with loose timings Geardown mode disabled (at least at 3800mhz, didn't try lower frequency) will not boot at all, or get stuck at the post screen. I thought it only rounded timings but it seems it does more things. Why is that and what do you recommend on doing?
> 
> here are the auto loose timings that have been running stably for ages as reference:
> 
> View attachment 2560525


Can someone point me to the right direction? From what i read i should play with the setup times in order to get it to post. For extra info with xmp enabled and all timings other than 1T set to auto it will boot at 3200mhz but not at 3400mhz. Considering these IC's can clock high and other people with other mobo's can run 1T just fine my guess it's that i need to get the setting manually as GB sucks ass (it will get stuck on training and i need to shut it down - unless it needs a very long time to train - it gets stuck at one code for more than 2mins)


----------



## 99belle99

nevartojau said:


> What latency do you get on Aida? I'm getting 54.9 - 55.0ns.
> The cooler is Corsair Dominator Airflow. I only bought it for esthetics to match the rest of the build. You can 3D print a frame and slap on a 120mm fan if you have space for it and don't care too much about the looks and it will perform even better than my cooler.
> View attachment 2560712


How loud is that RAM cooler fans? I have a RAM cooler from a set or Cosair Dominators from 2009 but it is really loud at speeds that would do any cooling. If I set it to silent it just like having no cooler as the way it clips on to my current RAM it is a half an inch away from the top of the RAM sticks but it was flush to the RAM it was designed for back in 2009.


----------



## 97pedro

nevartojau said:


> What latency do you get on Aida? I'm getting 54.9 - 55.0ns.
> The cooler is Corsair Dominator Airflow. I only bought it for esthetics to match the rest of the build. You can 3D print a frame and slap on a 120mm fan if you have space for it and don't care too much about the looks and it will perform even better than my cooler.
> View attachment 2560712












I get this on 3866mhz but I need airflow on my ram to be stable.


----------



## nevartojau

99belle99 said:


> How loud is that RAM cooler fans? I have a RAM cooler from a set or Cosair Dominators from 2009 but it is really loud at speeds that would do any cooling. If I set it to silent it just like having no cooler as the way it clips on to my current RAM it is a half an inch away from the top of the RAM sticks but it was flush to the RAM it was designed for back in 2009.


Well, it has a PWM connector, so I made a custom curve for it. It only spins 100% when CPU is at 65 C and that never happens while gaming, plus I have 3x140mm NOCTUA fans as intake. It's silent on my side. GPU and CPU is water cooled.


----------



## nevartojau

97pedro said:


> View attachment 2560719
> 
> 
> I get this on 3866mhz but I need airflow on my ram to be stable.


I wish I could go that low on latency. I am not very 5950X smart, but both 5900X and 5950X have 2 CCX. 5900X is 12 core and 5950X is 16 core but it has more L2 cache, how come with worse timings you get so much lower latency. Must be the CPU.


----------



## ReyReverse

nevartojau said:


> Well, it has a PWM connector, so I made a custom curve for it. It only spins 100% when CPU is at 65 C and that never happens while gaming, plus I have 3x140mm NOCTUA fans as intake. It's silent on my side. GPU and CPU is water cooled.


5 intake 1 exhaust. Goin to change my front panel to exhaust soon. See hows the performance gain


----------



## 99belle99

nevartojau said:


> I wish I could go that low on latency. I am not very 5950X smart, but both 5900X and 5950X have 2 CCX. 5900X is 12 core and 5950X is 16 core but it has more L2 cache, how come with worse timings you get so much lower latency. Must be the CPU.


I'd say it is his sub timings. I forget which sub timings it was but there are at least one or two sub timings that lower latency if they are low. It's been a while since I messed with timings but when i was messing about I found that out about having a lower latency.


----------



## ReyReverse

luxury stuff corsair dominator Airlow II, unreasonable price. is it come with heat pipe ? why would this stuff so expensive


99belle99 said:


> I'd say it is his sub timings. I forget which sub timings it was but there are at least one or two sub timings that lower latency if they are low. It's been a while since I messed with timings but when i was messing about I found that out about having a lower latency.


please leave your ZenTimings here, begging orz


----------



## nevartojau

99belle99 said:


> I'd say it is his sub timings. I forget which sub timings it was but there are at least one or two sub timings that lower latency if they are low. It's been a while since I messed with timings but when i was messing about I found that out about having a lower latency.


I'm very interested in figuring out which ones are doing this haha




97pedro said:


> View attachment 2560719
> 
> 
> I get this on 3866mhz but I need airflow on my ram to be stable.



Can you post your ZenTimings chart?


----------



## nevartojau

ReyReverse said:


> luxury stuff corsair dominator Airlow II, unreasonable price. is it come with heat pipe ? why would this stuff so expensive
> 
> please leave your ZenTimings here, begging orz


It's absolutely unreasonable, nom heatpipes, also RGB comes with their little BS device, so it's not just 2 connectors, you have this little corsair box too.
I would say if you don't care about the looks that much, just 3D print the frame and slap on some RGB fans on it. It won't look like crap.

It was an impulse buy on my side, just wanted to match the theme.
You will get a better performance with home made cooler.


----------



## 99belle99

ReyReverse said:


> please leave your ZenTimings here, begging orz


I have gone back to XMP as I run USB versions of Linux and it was not stable when I was running 3800MHz 1900MHz IF and 15, 15, 15, 15, 29, 39 GDM disabled. I could have gone through and loosened the timings to get it stable but I didn't bother and just went back to XMP. I don't game on my computer anymore so XMP is fine for my needs.


----------



## MrHoof

99belle99 said:


> I'd say it is his sub timings. I forget which sub timings it was but there are at least one or two sub timings that lower latency if they are low. It's been a while since I messed with timings but when i was messing about I found that out about having a lower latency.





nevartojau said:


> I'm very interested in figuring out which ones are doing this haha


Pretty sure thats L2 prefetcher disabled wich drops performance but gives u nice Aida screenshot for bregging rights. That latency is to low for a dual ccx.


----------



## Luggage

97pedro said:


> Hello all,
> 
> Currently I have a 3200mhz G skill flare x kit CL14 b die, running at 3800mhz 14-17-14-22 at 1.5v.
> 
> You guys think if the F4-3600C14D-16GVKA would be a nice upgrade? Should be, but by how much?
> 
> Or the F4-3600C16D-16GTZR, its cheaper and also b die, would it also be an upgrade?


Gvka - can’t get rcdrd und 15 


http://imgur.com/zQgf7mI


----------



## VPII

KedarWolf said:


> My first kit of that RAM sucked. I sent it back to Newegg for a second exact same kit. The second one I won the silicon lottery I think.


Shot, thank you. Look this kit is not that bad as I am doing CL14 at 3800 mem speed, it is just the GDM I can't seem to drop but I'll try more settings


----------



## Kha

hazium233 said:


> Thanks for reporting, but I meant the one where core VID limit drops if you set EDC over specification, starting in 1205. So for me on 5600X it changed 1.45 to 1.375, IIRC. "Working as intended" probably.











(Gigabyte X570 AORUS Owners Thread)


F36c on X570 Xtreme (5950X) on W11: fTPM stutter is totally fixed so far, µs, DPC, ISR are perfect (




www.overclock.net


----------



## Audioboxer

So, with me going to wait until early 2024 to consider going to DDR5/AMD or Intel's new chips, I decided how can I blow more money.... So, time for an anti-RGB build











This is my current setup, but I'm going to replace all fans with Noctua NF-A12x25s. No more QLs or Arctics. Especially looking forward to replacing the 25mm Arctic P12s. They really do give off an unpleasant resonance at many RPMs. Good value for money, not good value for sensitive ears.

With Noctua finally releasing their Chromax versions, no brown lol. But, RIP wallet with how much these damn fans cost. Noctua where is the 3 pack at?! 

Will replace those front Arctic P12 Slims with NF-A12x15s as well. More RIP for the wallet.

Also, going to replace the EK Slim 360mm in the back chamber. An XR7 just fits in there. 54mm vs the 53mm of the EK+25mm fans. Back chamber will now need to run pull only, but I'm sure it'll be fine with the Noctua fans performance.

Lastly, I'll probably grab 3m of the black satin hardline from Corsair. My trusty clear hardpipe has served me well, but many tear downs and adjustments has left it a bit scratched/scuffed. The black satin hardline is really nice. Yes... bending again, but can just copy my current runs.


----------



## Kuroihane

Audioboxer said:


> View attachment 2560769


Dang, and here I am, quite happy the AK620 is giving me better thermals than my 5y old H110i. I kinda gave up on water cooling for now...

I can only imagine the amount spent to get a good water-cooling setup like that haha


----------



## AsianOni

Hi everyone, I've been trying for a few days to get a good base for a 4xSR setup at 3800MT/s C14, GDM off 1T.
Gear is 4*8GB Patriot Viper Blackout (same as Steel I think) 4000C19 with a 5900X on an MSI X570 Unify. I lost a few days tuning with GDM enabled before remembering to turn off "memory fast boot"...

I could use some help, especially regarding RTT, Driver Str and Setup. This is where I am at the moment:








Considering the number of #12 that popped it should be Vdimm or Rtt, or maybe both.

I set the Bios as such:

Vsoc 1100mV
VDDP 900mV
CCD 940mV
IOD 1060mV
VDIMM 1.51V
VDIMM is read at 1.538~1546V so I'm not sure how much more I can push with my actual settings.
Thanks!


----------



## Snipie-PT

AsianOni said:


> Hi everyone, I've been trying for a few days to get a good base for a 4xSR setup at 3800MT/s C14, GDM off 1T.
> Gear is 4*8GB Patriot Viper Blackout (same as Steel I think) 4000C19 with a 5900X on an MSI X570 Unify. I lost a few days tuning with GDM enabled before remembering to turn off "memory fast boot"...
> 
> I could use some help, especially regarding RTT, Driver Str and Setup. This is where I am at the moment:
> View attachment 2560773
> 
> Considering the number of #12 that popped it should be Vdimm or Rtt, or maybe both.
> 
> I set the Bios as such:
> 
> Vsoc 1100mV
> VDDP 900mV
> CCD 940mV
> IOD 1060mV
> VDIMM 1.51V
> VDIMM is read at 1.538~1546V so I'm not sure how much more I can push with my actual settings.
> Thanks!


Same as me, when trying to push those settings is almost impossible to get stability...
Is there any changes between AGESA 1.2.0.3c and 1.2.0.6b?? Since I've upgraded, it feels harder to OC RAM...
I've order an active cooling for my RAM to see if it helps but it seems impossible to achieve 3800 CL14 for now...


----------



## nevartojau

I just stabilized this, using 1.2.0.3c AGESA, VDIMM is 1.55V


----------



## Audioboxer

Kuroihane said:


> Dang, and here I am, quite happy the AK620 is giving me better thermals than my 5y old H110i. I kinda gave up on water cooling for now...
> 
> I can only imagine the amount spent to get a good water-cooling setup like that haha


It's not cheap but if you're willing to roll up your sleeves and be patient you can build something good on a budget.

2nd hand shouldn't be ignored as long as you can inspect and see handled properly. Lots of money to be saved on Bykski/Barrow fittings rather than using Bitspower or things like Corsair fittings that IIRC are Bitspower rebranded.

When it comes to blocks and what not there is a decent budget market. I've seen people spend like £400-500 on GPU blocks, I got my GPU sandwich of the EK Vector v1 for £140 all in. Main block was listed as bstock but clearly a return unused and backplate I got on an eBay auction.

The case is likely where you won't save unless you can pickup local used. But there are plenty of cases to work with. There's no doubt the Lian Li is popular for a reason, just works great for watercooling.

Radiators, again, check out Bykski to make some savings. Their radiators are actually very good. Especially their 60mm ones. Match the HWLabs 60mm/thick. About half the cost of like a Corsair XR7 Bykski 60 mm RC Series Radiator Review

In terms of stupid money my setup isn't close to some of the showroom like builds people post with the best of the best and like £200-300 worth of fittings, alone, lmao.


----------



## athosdewitt

Hello fellow overclockers i would like to know some advanced things about relation between some timings so far this is what i got on OEM C-die DR 32GB stock is 2666 cl19(GDM ON)20-19-19-19-43 1.2v
i'm not interested to try GDM on / 2t. just 1T 

TRRDL must be set to at least 6 on DR or 4 just works?
if i have to set TRRDL to 6 is okay to run tFAW 16?
TWTRS and TWTRL can be set to 3/8 as minimum but twtrl should be equal with TRTP for stability? and twtrs looks sus that low.. i don't have rev E.
tRFC works best with tRC x tRTP ? so 350ns would be 56 x 10 = 560. did tested 320ns and worked but tRFC 504 doesn't and i need that for 56 x 9 ( tRTP )
tWR is best to be double of TRRDL and TRTP or can be lower without diminishing results?
do i have to set some timings based on TPHY i know tCL and some other timings set those.
SCL stress IMC particularly my weak ryzen 5 2600 dislike anything above cl16 3200. so higher like 3333 3400 3466 cl18-20-20-20-40 etc throws erros with or without gdm / 2t
above question SCL works at 4 minimum for 3200 and 2 for 2933. if i tight to bottom do i have to let loose other timings for stability?
as above related with imc stress tCWL can post at 10 as minimum , tested at 14 and just worked. is better a lower tCWL or a lower tRDWR tWRRD ?
should i aim for a particular number at 3200 for tRDWR tWRRD ? 6 3 works but again read somewhere for stability is bet to be set at 9 / 3 minmum. for tCWL 14 8 / 2 works at minimum.

trdrd and twrw sd dd can post 4 and 6 but i read somewhere that is better to be at 5 and 7, correct?

tCKE is on auto should be another number?

clkDrvStr and addcmdsetup higher and helps with stability at 1t, correct? well, it is on my end at 1T 24 24 24 24 throws errors and 0 addr the same. procODT looks good tho? i set those based on ryzen calculator for b450 and dual rank.

*All of this because sometimes after cold boot or waking up from sleeping , the damn thing gives a black screen when i open browser steam etc. previously i had gtx 970 now rx 580 8gb and i know for sure isn't gpu related, nor my undervolted OCed CPU, PRIME OCCT Games stable never black screen or freeze or some **** like that.

waiting for suggestion with some ''why so?'' if possible! Aiming to tight these to the floor.*
'allegedly you're thinking to ask ''why do you think that x and x must be set or equal'' - inner and inter latency gives better results with my finding but hopefully your suggestion change that. 
*Much Obliged!*


----------



## Luggage

Kuroihane said:


> Dang, and here I am, quite happy the AK620 is giving me better thermals than my 5y old H110i. I kinda gave up on water cooling for now...
> 
> I can only imagine the amount spent to get a good water-cooling setup like that haha


Best Bang for Bucks is alphacool 1080 or 1260 external rad, arctic p fans, soft tubing with straight barbed fittings and hose clamps. Just have to find a good deal on pumpres and blocks.
One big rad is cheaper than several standard sized. Just run hose through a pcie cover.



http://imgur.com/a/1sId8QF

(Delete internal rads, ram block, QDCs and flow meter - replace the rest with cheaper components and still get amazing performance)

But yea it won’t be a show piece


----------



## KedarWolf

AMD Ryzen 9 7950X CPU: possible 24C/48T, up to huge 5.4GHz CPU clocks


AMD's next-gen Zen 4-based Ryzen 7000 series CPUs could have flagship 24-core, 48-thread monster at 5.4GHz with Ryzen 9 7950X.




www.tweaktown.com


----------



## Audioboxer

Luggage said:


> Best Bang for Bucks is alphacool 1080 or 1260 external rad, arctic p fans, soft tubing with straight barbed fittings and hose clamps. Just have to find a good deal on pumpres and blocks.
> One big rad is cheaper than several standard sized. Just run hose through a pcie cover.
> 
> 
> 
> http://imgur.com/a/1sId8QF
> 
> (Delete internal rads, ram block, QDCs and flow meter - replace the rest with cheaper components and still get amazing performance)
> 
> But yea it won’t be a show piece


The external PC rads look awesome, I never really knew they were a thing when I was getting started. At least not to the extent of where they currently are.

While I'm happy with what I have managed to cram in a PC case, MO-RAs look awesome. I seen someone do a big one like yours with 9 T30 fans lmao. Talk about performance.



KedarWolf said:


> AMD Ryzen 9 7950X CPU: possible 24C/48T, up to huge 5.4GHz CPU clocks
> 
> 
> AMD's next-gen Zen 4-based Ryzen 7000 series CPUs could have flagship 24-core, 48-thread monster at 5.4GHz with Ryzen 9 7950X.
> 
> 
> 
> 
> www.tweaktown.com


Damn, I'm really going to need to be patient. Wanting to hold out for the X variant or 2nd gen. Still think DDR5 needs another year or so in the oven.


----------



## KedarWolf

MrHoof said:


> Pretty sure thats L2 prefetcher disabled wich drops performance but gives u nice Aida screenshot for bregging rights. That latency is to low for a dual ccx.


L2 disabled increases performance in everything I tried, not just AIDA.

And if you're the person who said it decreases AIDA performance when you have apps running, I mentioned any benchmark app lowers performance with apps running, so it's not reflective of having L2 cache disabled.

Someone even posted several games running with more FPS in a thread.


----------



## mvdev0

Ramad said:


> RTT values could be changing while RAM training on boot if left on AUTO, you can try locking them to RZQ/7-RZQ/3-RZQ/1 or any other combination that works for your RAM (my understanding is that you have a dual-rank B-die sticks), then find and use the lowest PROCODT value.


Hi,

the RTTs are all static (OFF-RZQ/3-RZQ/1) .. that setup _seems right_ on this dual-rank B-die system.

Yesterday I have another strange behavior.. having the system TM5 ([email protected]) 1000%, 6 cycles stable, HCI produces 1 error within 7 minutes.
I restart the system, change one setting in UEFI (do not know what anymore) but go back to the setting I used befor, and HCI runs 400% without any error.

That all is a bit confusing 

Thanks for responding!


----------



## mvdev0

.. but, I'm now TM5 250% stable with this settings (this is nothing, I know.. but I would like to change few settings befor do 1000%, HCI, y-c and OCCT) _args_










vDIMM=1.48V (at 54.3°C with ded. air cooling), VDDG CCD 1.05V (would like to adjust them lower in the last step)

Is there something I can do to stabilize tRFC at 160ns like it was befor with 3600MT/s?

EDIT: The settings not really spectacular, but I do not want raise vDIMM too much)


----------



## nevartojau

KedarWolf said:


> L2 disabled increases performance in everything I tried, not just AIDA.
> 
> And if you're the person who said it decreases AIDA performance when you have apps running, I mentioned any benchmark app lowers performance with apps running, so it's not reflective of having L2 cache disabled.
> 
> Someone even posted several games running with more FPS in a thread.



Very interesting, what workload or games are we talking about? I have not tried that ever and I'm curious. Does it mess with your OC stability?


----------



## KedarWolf

nevartojau said:


> Very interesting, what workload or games are we talking about? I have not tried that ever and I'm curious. Does it mess with your OC stability?


Here are two examples, enabled and disabled. I do find it often takes longer to boot though, but these examples are huge differences.

65.062s










64.191s










Prefetch disabled raises my R23 from 30300 or so to 30974.










Edit: I don't recall what thread it was that had the games comparison but games like SOTTR, Metro Exodus Remastered and a few other games it was slightly better across the board.


----------



## nevartojau

KedarWolf said:


> Here are two examples, enabled and disabled. I do find it often takes longer to boot though, but these examples are huge differences.
> 
> 65.062s
> 
> View attachment 2560806
> 
> 
> 64.191s
> 
> View attachment 2560807
> 
> 
> Prefetch disabled raises my R23 from 30300 or so to 30974.
> 
> View attachment 2560808
> 
> 
> Edit: I don't recall what thread it was that had the games comparison but games like SOTTR, Metro Exodus Remastered and a few other games it was slightly better across the board.


At this point I just have to try it myself


----------



## MrHoof

KedarWolf said:


> Here are two examples, enabled and disabled. I do find it often takes longer to boot though, but these examples are huge differences.
> 
> 65.062s
> 
> View attachment 2560806
> 
> 
> 64.191s
> 
> View attachment 2560807
> 
> 
> Prefetch disabled raises my R23 from 30300 or so to 30974.
> 
> View attachment 2560808
> 
> 
> Edit: I don't recall what thread it was that had the games comparison but games like SOTTR, Metro Exodus Remastered and a few other games it was slightly better across the board.


Found the post your talking about but my results were about the same as PJVOL´s he might be right that it has sth to do with dual CCD.
*ASUS ROG X570 Crosshair VIII Overclocking & Discussion Thread*


----------



## KedarWolf

@Veii Is there any benefit to having say TM5 usmus at 100% 25 cycles and run through the cycles quickly as opposed to saying 1 cycle at 4000%.

I mean wouldn't longer tests find results more thoroughly than cycling through quick fast tests?


----------



## Veii

KedarWolf said:


> @Veii Is there any benefit to having say TM5 usmus at 100% 25 cycles and run through the cycles quickly as opposed to saying 1 cycle at 4000%.
> 
> I mean wouldn't longer tests find results more thoroughly than cycling through quick fast tests?


It's hard to answer, since i don't exactly understand how Yuri's profile works.

Anta's is mostly a discharge check
1usmus's is a stacking error check, but won't find autocorrected errors easily, as it's short

On your example:
First is looping and increasing the "just long enough" testing order ~ increasing the chance of corrected error detection
2nd option is ~ increasing the duration and difficulty of the tests ~ easier to detect discharge issues, but potentially the issue of outside cache issues, to sneak in

I can't say. Need to ask him what is better as only he seems to understand how his profile behaves
What i can say, is that anta's profiles have issues on high voltage ~ for still some bizarre and unknown reason. Consistently failing irrelevant of timings near/after 1.58-1.6+ VDIMM

i think it makes sense for you, to figure out a reasonable balance between both
But it's not easy to title something "now it's better, because of reasons" 

Too long tests cause outside issues to sneak in (HCI/Karhu) & miss autocorrected timings [autocorrection is fantastic doing it's job]
Too short tests, will only be timings tests but not voltage ~ autocorrection will easily mask issues, but higher amount increases chance of error detection

25 cycles so far are a good middleground
But maybe longer duration 20 tests, could be one too
In general 3:30-4h for 32gb was a good middleground , same as 90+ minutes for 16gb (thermal equilibrium, which is near 40-45min)
^ room equilibrium with the load, not metal equilibrium which is near 10-15min for AIOs
(one adapts the delta of roomair to cooling-surface, the other adapts the roomair consistency to new added heatmakers) ~~ soo 50min minimum, any test , any category


Spoiler: EDIT



Problem is Schrödinger's/Quantum case;
~ More than 3-4h and you increase probability too high for outer issues to cause flipped bits
~ Too short tests and autocorrection is doing it's job too well, as there is a correctable margin too this days // "worse" with DDR5 now

Add that to Dynamic ODT function (_WR) also implementing another CRC check
I can not answer this. Too many variables
But surely finding a middleground of longer loads ~ can be needed.
Hence we saw now "couple enough" issues where TM5 misses a discharge error and only appears after 45-50 loops
~ yet still can be something like a fridge, lamp or stove related  // or simply powerswitch from main feeding source (location/village, not household)





Spoiler: EDIT 2



Yuri just needs to make a _v4 , and we are fine 
But his head is too full of other things + new Zen & other engineers don't seem to understand his testing methodology
Yes, maybe a slightly harsher 20 duration preset could be good
~ just needs caution, as his (lucky) decision of tests taking just long enough,
could cause issues if they are too long now or removing bruteforce method in letting autocorrection fail after time (after 3, 14 & 19+ loops usually)





Spoiler: EDIT 3



I really wish for Anta's tests to be "usable" for us ~ he knows his work very well
But all the 4-5 attempts are kind of "a fail" for us , unless you plan to stay bellow 1.5(5) or bellow 1.6v
4-5 Engineers worked on it, Arshia included ~ but still endresult is unsatisfying & nobody knows why to this day
HCI/Karhu needs 10 000% to be called "stable" ~ but that takes 6+ hours and risks of "day/night time powerswitch" to cause the flipped bit or simply you making something to eat


I don't know


----------



## nevartojau

MrHoof said:


> Found the post your talking about but my results were about the same as PJVOL´s he might be right that it has sth to do with dual CCD.
> *ASUS ROG X570 Crosshair VIII Overclocking & Discussion Thread*


I gave it a read, it's not very clear how it will behave on my CPU, my board.

Also I didn't really figure how to turn L1, L2 HW prefetchers off. In BIOS I don't have such a thing. I'm on MSI X570 MAG Tomahawk WIFI. Agesa 1.2.0.3c

I can turn off SMT, CCX, Cores, but no prefetchers in settings. Also some NUMA nodes per socket settings.

So I can't really test it. Is there another way to turn it off?


----------



## Veii

nevartojau said:


> So I can't really test it. Is there another way to turn it off?


5800X3D Owners & 5800X3D Owners for instructions (kinda)
Dangerous tool(s), tho


----------



## KedarWolf

nevartojau said:


> I gave it a read, it's not very clear how it will behave on my CPU, my board.
> 
> Also I didn't really figure how to turn L1, L2 HW prefetchers off. In BIOS I don't have such a thing. I'm on MSI X570 MAG Tomahawk WIFI. Agesa 1.2.0.3c
> 
> I can turn off SMT, CCX, Cores, but no prefetchers in settings. Also some NUMA nodes per socket settings.
> 
> So I can't really test it. Is there another way to turn it off?


No-one mad a CBS and PBS menus unlocked 1.2.0.3c BIOS for that board. 


nevartojau said:


> I gave it a read, it's not very clear how it will behave on my CPU, my board.
> 
> Also I didn't really figure how to turn L1, L2 HW prefetchers off. In BIOS I don't have such a thing. I'm on MSI X570 MAG Tomahawk WIFI. Agesa 1.2.0.3c
> 
> I can turn off SMT, CCX, Cores, but no prefetchers in settings. Also some NUMA nodes per socket settings.
> 
> So I can't really test it. Is there another way to turn it off?


No one modded a 1.2.0.3C BIOS for that board with the CBS and PBS menus unlocked. Only 1.2.0.3b. 






MSI X570 TOMAHAWK WIFI - Google Drive







drive.google.com


----------



## Kuroihane

Audioboxer said:


> It's not cheap but if you're willing to roll up your sleeves and be patient you can build something good on a budget....


I thought about starting that, then I remember that my work takes most out of my time and I end up not properly tuning my PC haha... Also one of the reasons I was looking for stability problems here, even at XMP. I use the same PC to work, so having it BSOD out of nowhere could set me back a few hours.

I live in a country where those are not readily available. I am beginning to see EK stuff slowly trickle into the market, but people here don't really seek it, they'd much rather go with a cheap CLC than proper WC.



Luggage said:


> Best Bang for Bucks is alphacool 1080 or 1260 external rad, arctic p fans, soft tubing with straight barbed fittings and hose clamps. Just have to find a good deal on pumpres and blocks.
> One big rad is cheaper than several standard sized. Just run hose through a pcie cover.
> 
> 
> 
> http://imgur.com/a/1sId8QF
> 
> (Delete internal rads, ram block, QDCs and flow meter - replace the rest with cheaper components and still get amazing performance)
> 
> But yea it won’t be a show piece


That's a nice NeverWarm 3000™ you got there 

I am honestly happy with how the AK620 performs slightly better than the H110i, maybe the CLC just about reached its age, but I am a bit skeptic on how it hangs over the ram sticks. I only have clear view on the very last DIMM, the others are covered by the fan. Hoping that doesn't cause airflow issues to the ram.


----------



## tommyd2k

Audioboxer said:


> View attachment 2560765
> 
> 
> 
> 
> Lastly, I'll probably grab 3m of the black satin hardline from Corsair. My trusty clear hardpipe has served me well, but many tear downs and adjustments has left it a bit scratched/scuffed. The black satin hardline is really nice. Yes... bending again, but can just copy my current runs.


I looked at this pic and was gonna ask what tubing you used cuz it had a nice glassy look to me. I used Thermaltake 26 and after a dozen teardowns in the last year it's time for some new tubing.


----------



## Audioboxer

Kuroihane said:


> I thought about starting that, then I remember that my work takes most out of my time and I end up not properly tuning my PC haha... Also one of the reasons I was looking for stability problems here, even at XMP. I use the same PC to work, so having it BSOD out of nowhere could set me back a few hours.
> 
> I live in a country where those are not readily available. I am beginning to see EK stuff slowly trickle into the market, but people here don't really seek it, they'd much rather go with a cheap CLC than proper WC.
> 
> 
> 
> That's a nice NeverWarm 3000™ you got there
> 
> I am honestly happy with how the AK620 performs slightly better than the H110i, maybe the CLC just about reached its age, but I am a bit skeptic on how it hangs over the ram sticks. I only have clear view on the very last DIMM, the others are covered by the fan. Hoping that doesn't cause airflow issues to the ram.


A lot of the Bykski and Barrow stuff on the likes of AliExpress is genuinely decent if not really good (those Bykski radiators I mentioned).

I think a lot of us, especially in the West, have just associated China with the kinds of videos pumped out on YouTube for clicks "My Wish dot com components only PC!" when in reality there are quite a few companies running out of China offering decent entry to mid level watercooling hardware. Often you can get free worldwide postage as well.

Warranty might be an issue, but I've been importing Bykski and Barrow stuff and no issues so far. I mean, look at the likes of Gigabyte and them cheapening out and using aluminium in their GPU blocks and the mess that caused. Not to mention EK managing to short lots of 3080/3090 EVGA cards with poor stand offs on their waterblocks.



tommyd2k said:


> I looked at this pic and was gonna ask what tubing you used cuz it had a nice glassy look to me. I used Thermaltake 26 and after a dozen teardowns in the last year it's time for some new tubing.


It's Corsair clear hardline. With me dropping all the RGB fans in my build I'm thinking of giving this a go with the tubing






If you have less RGB frosted tubing does a better job of giving a 'wider' glow effect. If I don't like how it turns out DIY I'll either grab the black satin tubing or consider the factory frosted tubing.

The black stuff really does look quite nice in all the 'anti-RGB' builds I've seen it in.


----------



## ReyReverse

KedarWolf said:


> Here are two examples, enabled and disabled. I do find it often takes longer to boot though, but these examples are huge differences.
> 
> 65.062s
> 
> View attachment 2560806
> 
> 
> 64.191s
> 
> View attachment 2560807
> 
> 
> Prefetch disabled raises my R23 from 30300 or so to 30974.
> 
> View attachment 2560808
> 
> 
> Edit: I don't recall what thread it was that had the games comparison but games like SOTTR, Metro Exodus Remastered and a few other games it was slightly better across the board.


Hi, may I know your 5950x curve settings? Mine first 3 core 24,24,24. The rest of them all 30. 
And my r23 only 29400 point (3600xmp yet overclock. I still busy for digging how to 1T off for my bin.).


----------



## MrDucky

Hi all,

I'm relatively new to overclocking memory and trying to optimize for a low latency since i use the PC for gaming and noticed that lower latency means a more stable frame rate in Warzone.
Been using this settings for some time now, used to be OCCT + memtest stable for 8 hours, just updated the bios so retested OCCT for 2 hours and memtest below for 1 hour.

Any tips for further optimization? I feel like a lot of you people here have far more knowledge about which timing does what then i have


----------



## Blameless

KedarWolf said:


> Here are two examples, enabled and disabled. I do find it often takes longer to boot though, but these examples are huge differences.
> 
> 65.062s
> 
> View attachment 2560806
> 
> 
> 64.191s
> 
> View attachment 2560807
> 
> 
> Prefetch disabled raises my R23 from 30300 or so to 30974.
> 
> View attachment 2560808
> 
> 
> Edit: I don't recall what thread it was that had the games comparison but games like SOTTR, Metro Exodus Remastered and a few other games it was slightly better across the board.


Highly random workloads (y-cruncher, encryption/hashing, archival, etc) are where one would expect disabling the prefetcher to help. Cinebench is a bit more surprising and I wouldn't expect most games to benefit.

Might be worth another look though.

_Edit:_ Did a quick test with the two games (at non-GPU limited settings) I have installed that have built-in benchmarks, _Cyberpunk 2077_ and _Deus Ex: Mankind Divided_. Cyberpunk was within margin of error, but Deus Ex favored the L2 prefetcher being enabled by 3-5%.

I also tested some Monero mining with XMRig and to my surprise it was also slightly worse with the prefetcher off, though also within possible run to run variance.

This was on my 5800X3D.


----------



## AsianOni

Snipie-PT said:


> Same as me, when trying to push those settings is almost impossible to get stability...
> Is there any changes between AGESA 1.2.0.3c and 1.2.0.6b?? Since I've upgraded, it feels harder to OC RAM...
> I've order an active cooling for my RAM to see if it helps but it seems impossible to achieve 3800 CL14 for now...


I decided to be less greedy and am now at 3800C16 2T. Although stable, this isn't fully optimized.








I've put 30 instead of 40 for ClkDrvStr without seeing but it's still stable. 
Putting 1T with those settings I'm immediately met with lots of #6.

Doing tCL14 might be a bit too difficult at 1T so I might try at 2T.


----------



## KedarWolf

ReyReverse said:


> Hi, may I know your 5950x curve settings? Mine first 3 core 24,24,24. The rest of them all 30.
> And my r23 only 29400 point (3600xmp yet overclock. I still busy for digging how to 1T off for my bin.).





ReyReverse said:


> Hi, may I know your 5950x curve settings? Mine first 3 core 24,24,24. The rest of them all 30.
> And my r23 only 29400 point (3600xmp yet overclock. I still busy for digging how to 1T off for my bin.).


Click on the link and scroll. This is Curve Cycler 720-720 FFTs SSE stable. Oh, my PBO settings are now 270-168-220. I'm at work and can't take screenshots from my personal PC, old post.



http://imgur.com/a/ZkrrKj5


----------



## nevartojau

KedarWolf said:


> No-one mad a CBS and PBS menus unlocked 1.2.0.3c BIOS for that board.
> 
> 
> No one modded a 1.2.0.3C BIOS for that board with the CBS and PBS menus unlocked. Only 1.2.0.3b.
> 
> 
> 
> 
> 
> 
> MSI X570 TOMAHAWK WIFI - Google Drive
> 
> 
> 
> 
> 
> 
> 
> drive.google.com


Still, thanks for the link! Something yo play with when I have free time.


----------



## 97pedro

Hello all!

What would be preferred?

14-15-14-28 tRC 42 trfc 252

Or

14-15-15-35 tRC 50 tRFC 250

Can I use a tras of 28 with TCL 14 and Trcdrd 15?


Thanks


----------



## tommyd2k

97pedro said:


> Hello all!
> 
> What would be preferred?
> 
> 14-15-14-28 tRC 42 trfc 252
> 
> Or
> 
> 14-15-15-35 tRC 50 tRFC 250
> 
> Can I use a tras of 28 with TCL 14 and Trcdrd 15?
> 
> 
> Thanks


The first one. You can run RAS as low as it'll go. It isn't gonna hurt anything if it's not TCL+TRCD. TRP+TRAS=tRC is one to follow for sure. RAS u can even try 21-22. 
To calculate tRFC, i'll try to do my best to explain.

Say you want 130ns then you take 0.13x memclck or 13*DDR multiplier/2
so for 130ns at 3800 do 13x19 or 0.13*3800/2 = 247
for 140ns at 3600 do 14x18 or 0.14*3600/2 = 252 <----your number

tRFC2 is tRFC*0.768 so 252*0.768=193
tRFC4 is tRFC*0.46 so 252*0.46=115


----------



## 97pedro

tommyd2k said:


> The first one. You can run RAS as low as it'll go. It isn't gonna hurt anything if it's not TCL+TRCD. TRP+TRAS=TCL is one to follow for sure. RAS u can even try 21-22.
> To calculate tRFC, i'll try to do my best to explain.
> 
> Say you want 130ns then you take 0.13x memclck or 13*DDR multiplier/2
> so for 130ns at 3800 do 13x19 or 0.13*3800/2 = 247
> for 140ns at 3600 do 14x18 or 0.14*3600/2 = 252 <----your number
> 
> tRFC2 is tRFC*0.768 so 252*0.768=193
> tRFC4 is tRFC*0.46 so 252*0.46=115


You meant trp+tras=tRC didn't you?


----------



## Audioboxer

Oooft, Noctua fans are... unsurprisingly, much better than P12s on acoustics. Legitmately silent up to 1000RPM. Between 1000 and 1300 a gradual scale, likely up to 1200RPM will be almost inaudible for many. Over 1300 a bit noisier, but to be expected pushing that amount of air. It's air travel noise though, not resonance or motor whine.

While I don't doubt some of the performance metrics for the Arctics in reviews, it definitely shows what buying a more expensive fan can do for noise levels.... and your wallet  Standing looking at the boxes of 14 Noctua fans makes you question your life choices.

The rubber mounting gaskets are pretty nice as well for that perfect radiator seal. I'm testing 1 Noctua fan on the rear 120mm 60mm thick radiator, and it legit seems OK (you can feel the air flow being reasonably strong through the rad). So no more push/pull with a fan on the rear outside of the case I think. 1 less cable to work with.

Now to drain the whole loop again and fit all the fans. One thing my rear of the case is thanking me for is getting rid of all the RGB cables.


----------



## ReyReverse

Finally I made it 3866mhz 0-0-01T off, yet tighten up. But I need to know how to fix that an error before I go to the next step. any idea?


----------



## GRABibus

TimeDrapery said:


> Disabling L1 and L2 prefetchers shouldn't do this as far as I'm aware


It will help.
It will also increase CPU performances (SC and MC) in most of applications / games.


----------



## Blackfyre

GRABibus said:


> It will help.
> It will also increase CPU performances (SC and MC) in most of applications / games.


Are there actual tests done to show the differences between the two in games? Enabled vs disabled. Googling doesn't provide with any reliable tests that I can see so far and everyone just says different from reading comments.


----------



## ReyReverse

KedarWolf said:


> Click on the link and scroll. This is Curve Cycler 720-720 FFTs SSE stable. Oh, my PBO settings are now 270-168-220. I'm at work and can't take screenshots from my personal PC, old post.
> 
> 
> 
> http://imgur.com/a/ZkrrKj5


Oh!! 
Best core 18, 2nd 25?


----------



## 97pedro

GRABibus said:


> It will help.
> It will also increase CPU performances (SC and MC) in most of applications / games.


Wrong, I tested 5 different games on my 5950X.
Shadow of Tomb Raider is better with L1and L2 prefetchers OFF
AC Valhalla better
Cyberpunk better low FPS, average the same
Watch dogs Legion 0 difference.



Blackfyre said:


> Are there actual tests done to show the differences between the two in games? Enabled vs disabled. Googling doesn't provide with any reliable tests that I can see so far and everyone just says different from reading comments.


I did all of them with my 5950x and RTX 3080 undervolted to 0.950v 1965mhz +1000mhz memory.

Didn't find any game that suffered any impact from disabling this, it's always equal or better with L1 and L2 prefecthers off.

I also run with CPPC and CPPC preffered cores OFF.

All core overclock of 4.7ghz.

I testes also, high settings and 1080p LOW, even in situtations of cpu bottleneck, it was never worse with L1 and L2 off, again, equal or better.


----------



## GRABibus

97pedro said:


> Wrong, I tested 5 different games on my 5950X.
> Shadow of Tomb Raider is better with L1and L2 prefetchers OFF
> AC Valhalla better
> Cyberpunk better low FPS, average the same
> Watch dogs Legion 0 difference.
> 
> 
> I did all of them with my 5950x and RTX 3080 undervolted to 0.950v 1965mhz +1000mhz memory.
> 
> Didn't find any game that suffered any impact from disabling this, it's always equal or better with L1 and L2 prefecthers off.
> 
> I also run with CPPC and CPPC preffered cores OFF.
> 
> All core overclock of 4.7ghz.
> 
> I testes also, high settings and 1080p LOW, even in situtations of cpu bottleneck, it was never worse with L1 and L2 off, again, equal or better.


So it is not completely wrong…as you observe some gains in some games.

How did you measure ? Your effective Clocks ?


----------



## Anhphe93

I don't know why my latency is so high. Someone please help me!


----------



## PJVol

GRABibus said:


> Your effective Clocks ?


He said all core OC 4700mhz ))


----------



## GRABibus

PJVol said:


> He said all core OC 4700mhz ))


Not challenging then 😊.
I was talking about PBO + CO


----------



## 97pedro

I know it's off topic for this thread, but I see no sense in having a 5950x running CO, because 1 core reaches 5ghz or something, playing anything that's a bit demanding, you won't be gaming at more than 4.9ghz.

There is absolutely no difference in the 5950x gaming performance, going from 4.7ghz to 4.9ghz, I rather have it locked to 4.7ghz all core.

Heck, a 5950x has amazing gaming performance even at 4.2ghz all core, games rely heavily on memory and cache performance, not on core clock.

I can bet that my 4.7ghz 5950x at around 1.25v load AVX is getting better gaming performance than anyone running with CO.

Locking everything all core allows you to disable CPPC and CPPC preffered cores, since all of them are running the same clock speed anyways. And, in this case, disabling L1 and L2 prefetchers gives some advantage.

I tried CO, PBO, anything I saw online, if anything I noticed worst 1% lows and worse overall gaming performance, even if I was gaming at 4.9-5ghz, it was worse than all core 4.7ghz.

Just my 2 cents


----------



## The_King

Got my first ZEN3 CPU today. First attempt at FCLK 2000 1:1:1


----------



## PJVol

You might find these AIDA tests useful (made some time ago with the same board/CPU):


----------



## The_King

PJVol said:


> You might find these AIDA tests useful (made some time ago with the same board/CPU):


Thanks alot for the info what RAM are you running. Mines are Micron REV B so not sure if i get the same results but i just passed 4000 CL16 with tighter timings.
Will try 16-17-17-17-34 next never tried to check anything above 2000 FCLK will try 2100 at some point.


----------



## PJVol

97pedro said:


> I rather have it locked to 4.7ghz all core.


I could agree, Auto/PB mode might not give you any advantages in gaming over Manual OC, I just have my doubts 4700mhz OC is affordable for the 5950X.


The_King said:


> Mines are Micron REV B so not sure if i get the same results but i just passed 4000 CL16 with tighter timing


They were Galax HOF 3600CL17 b-die modules. But AFAIK yours are basically differ in tRCD (+ tRAS ) and tRFC delays. Micron-E are okay.

PS: If you got no WHEA's at 2000 fclk (just like me) - i'd definitely fix this as base and move on to the timings and the CPU.


----------



## nevartojau

PJVol said:


> I could agree, Auto/PB mode might not give you any advantages in gaming over Manual OC, I just have my doubts 4700mhz OC is affordable for the 5950X.


What would be a good all-core OC for 5900X. I already have a PBO CO profile with memory tweaked to 3800 CL14. Would like to make an OC profile with all-core OC too. Do you have any insights on such? What frequencies / core voltage should I be aiming for?


----------



## PJVol

@nevartojau 
I have insights, but it'd better to ask people in the owner's thread:








OFFICIAL 5900X and 5950X two chiplet Zen 3 CPUs...


Since there is no such thread and plenty of people are interested how those new 2 chiplet Zen 3 processors are overclocking I'm starting a one. Post up your screens of OC's, cooler that you have used to do that, temperature under stability tests and a batch number if you know(it is placed on...




www.overclock.net


----------



## ReyReverse

97pedro said:


> I know it's off topic for this thread, but I see no sense in having a 5950x running CO, because 1 core reaches 5ghz or something, playing anything that's a bit demanding, you won't be gaming at more than 4.9ghz.
> 
> There is absolutely no difference in the 5950x gaming performance, going from 4.7ghz to 4.9ghz, I rather have it locked to 4.7ghz all core.
> 
> Heck, a 5950x has amazing gaming performance even at 4.2ghz all core, games rely heavily on memory and cache performance, not on core clock.
> 
> I can bet that my 4.7ghz 5950x at around 1.25v load AVX is getting better gaming performance than anyone running with CO.
> 
> Locking everything all core allows you to disable CPPC and CPPC preffered cores, since all of them are running the same clock speed anyways. And, in this case, disabling L1 and L2 prefetchers gives some advantage.
> 
> I tried CO, PBO, anything I saw online, if anything I noticed worst 1% lows and worse overall gaming performance, even if I was gaming at 4.9-5ghz, it was worse than all core 4.7ghz.
> 
> Just my 2 cents


That not right. Not everyone have a Crosshair extreme . It's very easy to achieve 4.7Ghz. but without that 18powerphase and optimem III , your memory speed can't go 3866MHz and above. 0 WHEA I mean. It's all about power package. (Silicon lottery=Crosshair Mobo= Pay money to win performance)

That's why there's a forum here ddr4 24/7 teach you overclock your memory speed .
But I really hope pro overclocker here to give some good advise, so newbie don't need to hit the brickwall so hard.


So PBO2 CO settings and memory overclock is related.

But can't deny high CPU frequency(all core) is better than high speed memory. And crosshair board can have it both .


----------



## 99belle99

Anhphe93 said:


> I don't know why my latency is so high. Someone please help me!
> View attachment 2560998
> 
> View attachment 2560997


Because your IF clock and RAM speed are really low. You want at least 3600MHz with 1800IF and higher to get lower latency.


----------



## The_King

Managed to get GDM disabled with 1T stable









Passed y-cruncher 2.5B as well CPU is stock no CO. In this test GDM was enabled.


----------



## Prophet4NO1

I have not done any more tweaking to the RAM or anything since I posted after the stress testing a week or two ago, but I have been doing some "house keeping" in windows. Got it down to 88 processes after a reboot. It was around 120-140 before. I cleaned up some things I forgot was even running that I do not need and cleared out some un used services in windows. And a few other odds and ends. All of that knocked a couple more ns off my latency. Not bad for some housekeeping.


----------



## Anhphe93

99belle99 said:


> Because your IF clock and RAM speed are really low. You want at least 3600MHz with 1800IF and higher to get lower latency.


i saw 1 result from other people giving 63ns latency on 5700g 3200c14


----------



## 97pedro

Hello all.

Getting really frustrated at this.

I've tried everything but I simply get random F9 errors while saving bios or cold booting.

I've tried many ProcODT settings, various vsoc and iod and ccd voltages but nothing.

Sometimes it will boot at 3800/1900 and 3866/1933, but it is not something that is guarranteed to work all the time.

Can anyone give me any insight of what it might be?

When it boots it's completly error free at 3800/1900.


----------



## tommyd2k

97pedro said:


> You meant trp+tras=tRC didn't you?





tommyd2k said:


> The first one. You can run RAS as low as it'll go. It isn't gonna hurt anything if it's not TCL+TRCD. TRP+TRAS=TCL is one to follow for sure. RAS u can even try 21-22.
> To calculate tRFC, i'll try to do my best to explain.
> 
> Say you want 130ns then you take 0.13x memclck or 13*DDR multiplier/2
> so for 130ns at 3800 do 13x19 or 0.13*3800/2 = 247
> for 140ns at 3600 do 14x18 or 0.14*3600/2 = 252 <----your number
> 
> tRFC2 is tRFC*0.768 so 252*0.768=193
> tRFC4 is tRFC*0.46 so 252*0.46=115


Sorry, TRP+TRAS=TRC is correct
Point is that rule is one you should always follow. I guess this is how to put it scientifically tRP+tRAS<tRC


----------



## tommyd2k

97pedro said:


> I know it's off topic for this thread, but I see no sense in having a 5950x running CO, because 1 core reaches 5ghz or something, playing anything that's a bit demanding, you won't be gaming at more than 4.9ghz.
> 
> There is absolutely no difference in the 5950x gaming performance, going from 4.7ghz to 4.9ghz, I rather have it locked to 4.7ghz all core.
> 
> Heck, a 5950x has amazing gaming performance even at 4.2ghz all core, games rely heavily on memory and cache performance, not on core clock.
> 
> I can bet that my 4.7ghz 5950x at around 1.25v load AVX is getting better gaming performance than anyone running with CO.
> 
> Locking everything all core allows you to disable CPPC and CPPC preffered cores, since all of them are running the same clock speed anyways. And, in this case, disabling L1 and L2 prefetchers gives some advantage.
> 
> I tried CO, PBO, anything I saw online, if anything I noticed worst 1% lows and worse overall gaming performance, even if I was gaming at 4.9-5ghz, it was worse than all core 4.7ghz.
> 
> Just my 2 cents


This argument was done to death over a year ago. And def off topic.


----------



## Requiem4u

ThomasW_ said:


> View attachment 2559813
> 
> 
> Any way to improve latency? FLCK 1866MHz was the maximum without WHEA error


Did you try raise FSB up to 101MHz?


----------



## 97pedro

Any one has any idea of what I can do to get rid of these random boot issues?
When it boots it's completely stable


----------



## Akex

97pedro said:


> Any one has any idea of what I can do to get rid of these random boot issues?
> When it boots it's completely stable


My bdie 4x8 SR, i need 1.65v


----------



## Ramad

97pedro said:


> Any one has any idea of what I can do to get rid of these random boot issues?
> When it boots it's completely stable


A few ideas:

CLDO VDDP is low. 900mV is low for 4x8GB set it to 1000mV. If set to AUTO, the motherboard should set it to 1100mV which is the correct value, 1000mV should work fine (depending on the memory controller quality).
Many of the memory controller timings are too low. tRDWR, tRDRD and tWRWR should be 10, 5-5 and 7-7.
tWR and tRTP should be 16 and 8 respectively.
tRRD timings should be 4 and 6 respectively.
There is no benefit from running tRCDWR at 8, it will run at 15 = tRCDRD.
tRAS should be 30
tRC should be 45
tRFC is too low. 
ProcODT could be low, try raising it one notch. This depends greatly on RTT, finding the correct RTT values will let you chose lower ProcODT values that will contribute to your system stability.
RTT could be wrong, you could try Disabled - OFF - RZQ/5 or Disabled - RZQ/2 - RZQ/5

Please remember: Too low timings does not mean your RAM will run faster, they are good for a show off, nothing more.


----------



## Comalive

Hi guys, question for AMD ComboAm4v2PI 1.2.0.6c (Gaming Edge Wifi): is the 1900fclk hole fixed by now and where there improvements to fclk stability in general? 2000fclk was almost stable for me on 1.2.0.3b so I wonder if it might work now.


----------



## ReyReverse

Ramad said:


> Too low timings does not mean your RAM will run faster, they are good for a show off, nothing more.


I can't agree more.


----------



## VPII

Comalive said:


> Hi guys, question for AMD ComboAm4v2PI 1.2.0.6c (Gaming Edge Wifi): is the 1900fclk hole fixed by now and where there improvements to fclk stability in general? 2000fclk was almost stable for me on 1.2.0.3b so I wonder if it might work now.


In all honesty, with my MSI Meg X750 Ace there is no way I can run 2000mhz fclk it will not post. I've ran 1933 and 1966 but not stable when running memory tests. And I am using the 1.2.0.6C Agesa bios.


----------



## Audioboxer

More pics here Imgur: The magic of the Internet

All the Noctuas now! With my pump at 2200RPM and fans at 600RPM for idle/desktop use this is the quietest my PC has ever been. Hard to tell it's even on. Full load fans go to 1000~1100RPM and pump goes to 4300RPM (around 85%) and it's quieter than the Arctic/QL120 combo at the same RPM, let alone the 1200~1300 I used to run it at for the same water temp/performance as I have now with less.

So yeah, things to invest in IMO, fans better than Arctics (even if they have good performance), and I'll still massively rep a RAM waterblock if anyone is using b-die. Not having to use 100% RPM on fans, or being restricted with tRFC due to 45+ degree temps is just great. It's funny how little difference voltage makes now to RAM temps, they pretty much just follow water temp no matter what. Even above 1.6v+. Just a shame B-die craps out at like 1.65v full capacity.

Apart from changing the tubing later in the summer, I was eyeing up something thicker than an XR7 at the bottom, but for now I need to stop lol. The XR7 in the side chamber literally must fit perfect. I honestly think 1mm more and the side panel might have had issues closing.

Lian-Li Dynamic XL | Front Grill (Mayan) Clear | ColdZero Mayan front panel is now available in clear, might ask Ricardo (owner, nice guy) if he can price me on just the front part of the design at some point.


----------



## athosdewitt

athosdewitt said:


> Hello fellow overclockers i would like to know some advanced things about relation between some timings so far this is what i got on OEM C-die DR 32GB stock is 2666 cl19(GDM ON)20-19-19-19-43 1.2v
> i'm not interested to try GDM on / 2t. just 1T
> 
> TRRDL must be set to at least 6 on DR or 4 just works?
> if i have to set TRRDL to 6 is okay to run tFAW 16?
> TWTRS and TWTRL can be set to 3/8 as minimum but twtrl should be equal with TRTP for stability? and twtrs looks sus that low.. i don't have rev E.
> tRFC works best with tRC x tRTP ? so 350ns would be 56 x 10 = 560. did tested 320ns and worked but tRFC 504 doesn't and i need that for 56 x 9 ( tRTP )
> tWR is best to be double of TRRDL and TRTP or can be lower without diminishing results?
> do i have to set some timings based on TPHY i know tCL and some other timings set those.
> SCL stress IMC particularly my weak ryzen 5 2600 dislike anything above cl16 3200. so higher like 3333 3400 3466 cl18-20-20-20-40 etc throws erros with or without gdm / 2t
> above question SCL works at 4 minimum for 3200 and 2 for 2933. if i tight to bottom do i have to let loose other timings for stability?
> as above related with imc stress tCWL can post at 10 as minimum , tested at 14 and just worked. is better a lower tCWL or a lower tRDWR tWRRD ?
> should i aim for a particular number at 3200 for tRDWR tWRRD ? 6 3 works but again read somewhere for stability is bet to be set at 9 / 3 minmum. for tCWL 14 8 / 2 works at minimum.
> 
> trdrd and twrw sd dd can post 4 and 6 but i read somewhere that is better to be at 5 and 7, correct?
> 
> tCKE is on auto should be another number?
> 
> clkDrvStr and addcmdsetup higher and helps with stability at 1t, correct? well, it is on my end at 1T 24 24 24 24 throws errors and 0 addr the same. procODT looks good tho? i set those based on ryzen calculator for b450 and dual rank.
> 
> *All of this because sometimes after cold boot or waking up from sleeping , the damn thing gives a black screen when i open browser steam etc. previously i had gtx 970 now rx 580 8gb and i know for sure isn't gpu related, nor my undervolted OCed CPU, PRIME OCCT Games stable never black screen or freeze or some **** like that.
> 
> waiting for suggestion with some ''why so?'' if possible! Aiming to tight these to the floor.*
> 'allegedly you're thinking to ask ''why do you think that x and x must be set or equal'' - inner and inter latency gives better results with my finding but hopefully your suggestion change that.
> *Much Obliged!*


UP
someone? Thanks.


----------



## Tobiman

Audioboxer said:


> View attachment 2561390
> 
> 
> More pics here Imgur: The magic of the Internet
> 
> All the Noctuas now! With my pump at 2200RPM and fans at 600RPM for idle/desktop use this is the quietest my PC has ever been. Hard to tell it's even on. Full load fans go to 1000~1100RPM and pump goes to 4300RPM (around 85%) and it's quieter than the Arctic/QL120 combo at the same RPM, let alone the 1200~1300 I used to run it at for the same water temp/performance as I have now with less.
> 
> So yeah, things to invest in IMO, fans better than Arctics (even if they have good performance), and I'll still massively rep a RAM waterblock if anyone is using b-die. Not having to use 100% RPM on fans, or being restricted with tRFC due to 45+ degree temps is just great. It's funny how little difference voltage makes now to RAM temps, they pretty much just follow water temp no matter what. Even above 1.6v+. Just a shame B-die craps out at like 1.65v full capacity.
> 
> Apart from changing the tubing later in the summer, I was eyeing up something thicker than an XR7 at the bottom, but for now I need to stop lol. The XR7 in the side chamber literally must fit perfect. I honestly think 1mm more and the side panel might have had issues closing.
> 
> Lian-Li Dynamic XL | Front Grill (Mayan) Clear | ColdZero Mayan front panel is now available in clear, might ask Ricardo (owner, nice guy) if he can price me on just the front part of the design at some point.


Your fan orientation is giving me a mind ****.


----------



## Audioboxer

Tobiman said:


> Your fan orientation is giving me a mind ****.


All intake, front exhaust. Get the coldest air going over all rads!

But due to where the pwm connector is for these fans sadly that has some rear logos in the orientation they are lol. If they're facing front on then it looks the same all orientations 😂

Noctua logos are metal as well so it's not a sticker that can be changed or removed.


----------



## Tobiman

Audioboxer said:


> All intake, front exhaust. Get the coldest air going over all rads!


Ah, I see. What are your water temps like? What GPU/CPU are you running?


----------



## Alexandru Lascu

Hi,
2x8gb corsair 3600cl18 micron rev-e kit ~45celcius









Thoughts on the Error 2 on [email protected]? Cheers!


----------



## Tobiman

Alexandru Lascu said:


> Hi,
> 2x8gb corsair 3600cl18 micron rev-e kit ~45celcius
> View attachment 2561404
> 
> 
> Thoughts on the Error 2 on [email protected]? Cheers!


Your VSOC looks stockish. Might want to up that a bit.


----------



## Audioboxer

Tobiman said:


> Ah, I see. What are your water temps like? What GPU/CPU are you running?


Right now ambient 27.8 degrees, water temp 31.24 degrees, GPU temp 40 degrees, CPU 66 degrees on a 360w GPU load. Fans at 1100RPM.

3080 and a 5950x.

Probably should add GPU is 2025mhz at 0.987v. Memory at +1500.


----------



## Alexandru Lascu

Tobiman said:


> Your VSOC looks stockish. Might want to up that a bit.


1.05?


----------



## Tobiman

Alexandru Lascu said:


> 1.05?


That's a good place to start.


----------



## hazium233

Comalive said:


> Hi guys, question for AMD ComboAm4v2PI 1.2.0.6c (Gaming Edge Wifi): is the 1900fclk hole fixed by now and where there improvements to fclk stability in general? 2000fclk was almost stable for me on 1.2.0.3b so I wonder if it might work now.


I didn't try 1.9 (1206c). I thought about it out of curiosity given that 1.8 (1205) resulted in what I believe was higher than set DRAM voltage. At the least it was higher than what previous bios versions (1.6 or 1.7) supplied based on my testing. MSI support couldn't give an answer about whether that was an intended change or a bug, just that they would forward my results to the technical team.

But I don't really want to flash more times than I have to. I had been waiting for 1207 bios, but who knows when they will release it.


----------



## tommyd2k

Audioboxer said:


> View attachment 2561390
> 
> 
> More pics here Imgur: The magic of the Internet
> 
> All the Noctuas now! With my pump at 2200RPM and fans at 600RPM for idle/desktop use this is the quietest my PC has ever been. Hard to tell it's even on. Full load fans go to 1000~1100RPM and pump goes to 4300RPM (around 85%) and it's quieter than the Arctic/QL120 combo at the same RPM, let alone the 1200~1300 I used to run it at for the same water temp/performance as I have now with less.
> 
> So yeah, things to invest in IMO, fans better than Arctics (even if they have good performance), and I'll still massively rep a RAM waterblock if anyone is using b-die. Not having to use 100% RPM on fans, or being restricted with tRFC due to 45+ degree temps is just great. It's funny how little difference voltage makes now to RAM temps, they pretty much just follow water temp no matter what. Even above 1.6v+. Just a shame B-die craps out at like 1.65v full capacity.
> 
> Apart from changing the tubing later in the summer, I was eyeing up something thicker than an XR7 at the bottom, but for now I need to stop lol. The XR7 in the side chamber literally must fit perfect. I honestly think 1mm more and the side panel might have had issues closing.
> 
> Lian-Li Dynamic XL | Front Grill (Mayan) Clear | ColdZero Mayan front panel is now available in clear, might ask Ricardo (owner, nice guy) if he can price me on just the front part of the design at some point.


I didn't know that was an 011D-XL. You got a thing for fans huh? I have that same inline temp+flow meter. With my DDC pump it says 3.5L/min, what does your setup run at full speed? 
That grill is a pretty good idea. I have seen distros made for the front b4 but never a grill, plus it's a 360 rad mount. Now 011's have everything like modular, they can be used with the motherboard upside down and facing the right side. It's really an ideal design for most anything. 

I use the Barrowch Ram Cooler with a temp display. It keeps my 2 sticks a constant 31deg. The lcd and led's died on mine, (It was my fault). Anyone buying one, be careful connecting the power, they have zero forgiveness if you accidentally reverse polarity. And a dead LCD screen sucks.


----------



## Audioboxer

tommyd2k said:


> I didn't know that was an 011D-XL. You got a thing for fans huh? I have that same inline temp+flow meter. With my DDC pump it says 3.5L/min, what does your setup run at full speed?
> That grill is a pretty good idea. I have seen distros made for the front b4 but never a grill, plus it's a 360 rad mount. Now 011's have everything like modular, they can be used with the motherboard upside down and facing the right side. It's really an ideal design for most anything.
> 
> I use the Barrowch Ram Cooler with a temp display. It keeps my 2 sticks a constant 31deg. The lcd and led's died on mine, (It was my fault). Anyone buying one, be careful connecting the power, they have zero forgiveness if you accidentally reverse polarity. And a dead LCD screen sucks.












Max I see at 100% under a heavy load is 5.31L/min. Still got some air to bleed, but not much. I run on a pump curve though that runs at 2100RPM on idle and goes up to around 4400RPM on load. I think this is like 85% or something. Reads at 4.xxL/min at 4400RPM. Really don't know how accurate these things are though. Usually not very, but the Barrow is definitely better built than the Bykski. The impeller is better as well. 

More fans usually means you can handle more heat at a quieter level. I'm tempted to run front intake to see how it is, but would need to switch rear to exhaust so hot air inside can escape somehow. But in most of my basic testing so far bringing external ambient air over rads is just best. Hence front exhaust.


----------



## Luggage

Audioboxer said:


> View attachment 2561508
> 
> 
> Max I see at 100% under a heavy load is 5.31L/min. Still got some air to bleed, but not much. I run on a pump curve though that runs at 2100RPM on idle and goes up to around 4400RPM on load. I think this is like 85% or something. Reads at 4.xxL/min at 4400RPM. Really don't know how accurate these things are though. Usually not very, but the Barrow is definitely better built than the Bykski. The impeller is better as well.
> 
> More fans usually means you can handle more heat at a quieter level. I'm tempted to run front intake to see how it is, but would need to switch rear to exhaust so hot air inside can escape somehow. But in most of my basic testing so far bringing external ambient air over rads is just best. Hence front exhaust.


And @tommyd2k I wouldn’t trust any flow meter very much except for aqua computer flow for comparative readings.

I had the bysksi earlier and it reported 50% more max flow over the high flow next.









Aqua Computer high flow NEXT Review - Much more than just an accurate flow meter. Only it can’t speak yet. | Page 3 | igor'sLAB


With the Aqua Computer high flow NEXT, the Swiss Army Knife for custom loops with lots of functions and accuracy has been available since this year for just under 70 Euros. Does anyone remember the…




www.igorslab.de





For diagnosing your own system they work though ie you can view your max min and % flow at different settings and also I you see a trend of dropping flow rate indicating blocks gunking up..

My rather large loop* with dual dcc pumps tops out at 185-200L/h depending on water temp…
Though I’m want to try and modify my techn block for better flow since I suspect it’s unnecessarily obstructive.


----------



## tommyd2k

Audioboxer said:


> View attachment 2561508
> 
> 
> Max I see at 100% under a heavy load is 5.31L/min. Still got some air to bleed, but not much. I run on a pump curve though that runs at 2100RPM on idle and goes up to around 4400RPM on load. I think this is like 85% or something. Reads at 4.xxL/min at 4400RPM. Really don't know how accurate these things are though. Usually not very, but the Barrow is definitely better built than the Bykski. The impeller is better as well.
> 
> More fans usually means you can handle more heat at a quieter level. I'm tempted to run front intake to see how it is, but would need to switch rear to exhaust so hot air inside can escape somehow. But in most of my basic testing so far bringing external ambient air over rads is just best. Hence front exhaust.


I thought it was the Byski one. Barrow, Byski, Barrowch they make a lot of similar stuff, sometimes Byski's design is a little better and vice versa. The Barrow distro plate has a radiator between the GPU and CPU the Byski sends the coolant straight from the GPU to the CPU then through both radiators. 

I have the 6 fans pushing air out the top and bottom and no intake fans. I had an LL120 for the back but it was facing the wrong way. I considered using a QL120 instead or even using 3 QL's to pull air in on one of the rads. The water stays 32c as is so I left it.


----------



## Audioboxer

tommyd2k said:


> I thought it was the Byski one. Barrow, Byski, Barrowch they make a lot of similar stuff, sometimes Byski's design is a little better and vice versa. The Barrow distro plate has a radiator between the GPU and CPU the Byski sends the coolant straight from the GPU to the CPU then through both radiators.
> 
> I have the 6 fans pushing air out the top and bottom and no intake fans. I had an LL120 for the back but it was facing the wrong way. I considered using a QL120 instead or even using 3 QL's to pull air in on one of the rads. The water stays 32c as is so I left it.


Yeah for everything else sometimes Bykski are better, they've got some really good radiators for example.

Flow meters though the Bykski isn't great. It's cheap, but the impeller is noisy and who knows with accuracy.

Barrow seem to have like 5 revisions of their flow meter lol. Not sure if it's just cosmetic or not for the most part but that v5 I have is like 2x the price of the Bykski. Outside of cosmetics the biggest improvement over the Bykski is PWM fan header powered and the impeller is quiet.

I own the Bykski but had to replace it when I accidentally pulled one of the power cables out of the bottom. Tried soldering it back but it got messy as contact points are tiny.

QL fans are the worst Corsair have for radiators. All their other RGB fans are marginally better.


----------



## The_King

Veii said:


> That should be the orientation point
> Jumping profiles and testing 2133, hence the profile had tCKE 14 in not 13
> SOC & VCORE VID to V_TEL is flat
> 
> AMD max overclocking voltage main
> 5800X3D Owners update
> daily since around 1 1/2 years now (nov, 2020)
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Dual CCD ~ BG 2037 SUS , is correctly patched by Lab. First batch
> No WHEA's, ever ~ only sometimes #18 if i do stupid things
> 
> Have to ask @Bloax
> A0 PCB is dangerous (sensitive) and not recommended


Are all 5600X not the same? Here is mines.


----------



## Audioboxer

Slightly offtopic question, but how is it some people get pictures of their BIOS settings? Is it a print-screen function in some manufacturers BIOS or something?

B550 Unify-X has new BIOS for 1.2.0.7 listed https://download.msi.com/bos_exe/mb/7D13vA63.zip 7D13vA63(Beta version). Last beta on Google Drive was A62, so going to update.


----------



## The_King

Audioboxer said:


> Slightly offtopic question, but how is it some people get pictures of their BIOS settings? Is it a print-screen function in some manufacturers BIOS or something?
> 
> B550 Unify-X has new BIOS for 1.2.0.7 listed https://download.msi.com/bos_exe/mb/7D13vA63.zip 7D13vA63(Beta version). Last beta on Google Drive was A62, so going to update.


On my MSi board you can press F12 in the BIOS to take screenshots.


----------



## Audioboxer

The_King said:


> On my MSi board you can press F12 in the BIOS to take screenshots.


Yeah, that works. Silly me not knowing this before now lol.










Time to test if I can get anything more out of Core 5 on the new AGESA. Older AGESA I could do -5, then around the time of all the big changes with 1.2.0.4 and curves being messed with, I had to drop it to -1.

It's my best core, but it's the odd one out being stuck as low as it is


----------



## ReyReverse

CCXCCDCount: 2
1T off 0-0-0 is so difficult man
Finally done. 3733MHz CL 14 , all core 4.825GHz single core max 5.025GHz (ambient 16c, CPU max temp 79c)
Passed TM5 1usmus 30cycles. ( not gonna go for 100 cycles waste of time.) 









CCXCCDCount: 2
3866MHz 1T off 0-0-0, win latency but lose core performance. 
passed TM5 1usmus (100 cycles, didn't screenshot I was so tired) , all core only can run 4GHz, single core 5.05Ghz 


conclusion: for those people who wants to do video editing (large rendering file)should go for scenario 1, 1080p 1440p gamer probably can go for the 2. 
4K gamer should still stick with scenario 1


Finally I can stop tweaking my bin and CPU, its game time~~~~~~


----------



## The_King

@ReyReverse
AddrCmdSetup = 56 would have made GDM OFF 1T easier why did you go for 0-0-0. Just curious.
Also what voltage did you run to pass 100 cycles. 

Here mines definitely not TM5 stable  I got some stable runs @ 4000 CL16


----------



## Audioboxer

The_King said:


> @ReyReverse
> AddrCmdSetup = 56 would have made GDM OFF 1T easier why did you go for 0-0-0. Just curious.
> Also what voltage did you run to pass 100 cycles.
> 
> Here mines definitely not TM5 stable  I got some stable runs @ 4000 CL16
> 
> View attachment 2561644


Setup timing usually isn't needed for SR!


----------



## LtMatt

Veii said:


> That's not how asking / demanding , for help works 😇
> 
> you could have tried the RTT suggestions people post for dual rank/4 dimms, but you didn't
> could try 2T over GDM, to spend your time getting your powering issues stable, didn't
> could just browse through my old posts or overall this forum here, probably also didn't
> Meanwhile i have to write the same thing over and over again
> If you rush for a build, that's acceptable ~ but all the research is out there for free
> Don't push that blame on me  ~ anywho
> 
> *>* 4400C19-19 Vipers are on a custom A2 PCB
> *>* Daisy Chain splits the signal in 25/75%
> *>* A2 PCBs need more current (ampere) to start functioning, soo as the loss on the slave set is higher, you should start to voltage bin them ~ and put the ones which work with less voltage, on the slave set
> *>* You forgot to post a ZenTimings screenshot here, but i guess you run SD, DDs as 1-4-4-1-6-6 right ?
> *>* ClkDrvStr needs to be higher if you want to use lower procODT. Lower procODT is required for high FCLK. 4x8/2x16GB need around 36.9ohm procODT, at worst 40. Lower it
> *>* For GDM Off you'd need CAD_BUS somewhere near 40-20-30-20 or 60-20-40-20. 3rd value fixes memory training on Vermeer (slightly). Another option is: 40-20-20-20, tCKE 9, Setup Time 3-3-15 (3800, or tCKE 11 4-4-16 @ 4000+)
> *>* While 3800C14 requires 1.48-1.56v, 4000C14 requires 1.62-1.67vDIMM.
> *>* + 200MT/s = +1 tCL, +1 tRCD for the same latency, same strain @ same required voltage ~ just with higher throughput
> *>* CPU VDDP needs to be 900 or 880Mhz for 2000+ to work.880mV for 2100+. cLDO_VDDP ≠ CPU VDDP
> *> *use tRFC mini, always fill tRFC1/2/4, and set tWR as clean divider of tRFC and tRTP half of it
> *> *follow tWR rule and tRC = tRAS+tRP for now , till you understand how to lower them by yourself (Baseline rules)
> 
> I think that's all you need to know.
> You probably want to fix:
> 
> Memory Clear ~ Disable
> Memory Interleaving ~ 256kb
> Memory Address Hash ~ enabled
> TSME ~ disabled
> HW Prefetcher ~ both enabled
> PHY Memory controller (DF -> DDR4 common options) PMU Pattern bits , manual ~ A (a/10 - it's in HEX) and both training options DFE, PME/PMU? ~ enabled
> CPPC & CPPC Preferred cores, enabled (NBIO - SMU/XFR)
> ^ Inside AMD CBS
> 
> Keep MCLK =/= UCLK 1:1 , enabled in AMD OVERCLOCKING, Infinity fabric section ~ else you go into 1:1:2 mode
> 
> tRRD_L can be anything over tRRD_S.
> But you might want to have tWTR_L = tRRD_L *2 for consistency
> Sadly tWTR_L only goes up till 14
> 
> The cleanest way is +2, but you can lower it to +1 with tWTR_L 10 for example
> Equalizing it, usually causes more problems - even tho it looks low.
> You use SCL 2-2 , old rulesets for tWRRD where 4x X = tRCD_WR or lower than it
> But X * SCL works too.
> tWRRD delay will be needed once you lower tRDWR below (tRCD /2) +2.
> It also will be needed if you go for tCWL ≠ tCL. This one is a Libra. You lower one by two, you have to increase the other by two. (Or by 1 if you trow in tWRRD delay)
> The board doesn't touch tRRD and tWTR delays. But the memory does autocorrect tFAW if it's too high.
> As for "too low" it did on Matisse/Renoir, but doesn't anymore on Vermeer/Cezanne
> 
> @Bruizer
> DRAM Calculator is outdated at this point. Only the timings are very useful
> Check here for voltage examples
> AMD max overclocking voltage (whole thread probably)
> And focus on running 2T GDM Off with your timings (15-15-15)
> RTT you can try 7/3/1 instead of 0/3/1, or 6/3/3
> Also SD,DD 1-4-4-1-6-6 is for 2x dual rank / 4 dimms
> (If you want to run my tCKE shenanigans, you need to match RTT & Setup Time. tCKE & CAD_BUS Setup Time, changes by MCLK)


Big oof. Just discovered this post, thanks lots of helpful stuff here.

Does it all still apply for the 5800X3D?

EDIT- Just found the TRFC sheet too, lovely.


----------



## The_King

Audioboxer said:


> Setup timing usually isn't needed for SR!


It helped me to stabilize GDM OFF 1T with my SR setup. Without it immediate crash in windows. Definitely helps on SR

Here was a quick 3 cycles test @ 1.45V.


----------



## ReyReverse

The_King said:


> @ReyReverse
> AddrCmdSetup = 56 would have made GDM OFF 1T easier why did you go for 0-0-0. Just curious.
> Also what voltage did you run to pass 100 cycles.
> 
> Here mines definitely not TM5 stable  I got some stable runs @ 4000 CL16
> 
> View attachment 2561644


I want pure 1T , 0 latency.


The_King said:


> @ReyReverse
> AddrCmdSetup = 56 would have made GDM OFF 1T easier why did you go for 0-0-0. Just curious.
> Also what voltage did you run to pass 100 cycles.
> 
> Here mines definitely not TM5 stable  I got some stable runs @ 4000 CL16
> 
> View attachment 2561644


1T off 0-0-0 got no input lag. 
Meant when you open program it will prompt immediately within a 0.1sec or 0.2sec .
Thats what I want. Ive enough with audio glitch , audio lag ( probably gdm on cause this)

1T off 0-0-0 is very sensitive for everything. 
1 timing wrong or voltage then u can't pass tm5 anta extreme /1usmus . ( I prefer 1usmus, more accurate )


----------



## ReyReverse

The_King said:


> @ReyReverse
> AddrCmdSetup = 56 would have made GDM OFF 1T easier why did you go for 0-0-0. Just curious.
> Also what voltage did you run to pass 100 cycles.
> 
> Here mines definitely not TM5 stable  I got some stable runs @ 4000 CL16
> 
> View attachment 2561644


Hey just a tips here, you can't round up tRC, but tRAS


----------



## The_King

ReyReverse said:


> Hey just a tips here, you can't round up tRC, but tRAS


I blame Ryzen DRAM calculator for that.


----------



## ReyReverse

The_King said:


> I blame Ryzen DRAM calculator for that.
> 
> View attachment 2561647


No way..... This is for Zen1,2
Zen 3 You should use RyZen Google calculator. ( Use it if you stick with GDM on , gdm off 2T or gdm off 1T 56-0-0.


----------



## The_King

ReyReverse said:


> No way..... This is for Zen1,2
> Zen 3 You should use RyZen Google calculator. ( Use it if you stick with GDM on , gdm off 2T or gdm off 1T 56-0-0.


Yes, I was just using those settings has a starting point. I am aware it does not support ZEN3 and is outdated.

I am trying at the moment to get 3800 CL15 GDM off 1T stable for 25 cycles with TM5 - 1usmus. 3800 CL16 @ 1.45V is not a problem.
Busy testing another config at the moment without AddrCmd setup 56. Since i was not aware of the latency issues that causes.


----------



## LtMatt

The_King said:


> It helped me to stabilize GDM OFF 1T with my SR setup. Without it immediate crash in windows. Definitely helps on SR
> 
> Here was a quick 3 cycles test @ 1.45V.
> View attachment 2561645


Which is better? 3800Mhz CL15 GD off, or 3800Mhz CL14 GD off T2?


----------



## ReyReverse

The_King said:


> Yes, I was just using those settings has a starting point. I am aware it does not support ZEN3 and is outdated.
> 
> I am trying at the moment to get 3800 CL15 GDM off 1T stable for 25 cycles with TM5 - 1usmus. 3800 CL16 @ 1.45V is not a problem.
> Busy testing another config at the moment without AddrCmd setup 56. Since i was not aware of the latency issues that causes.


OK good luck 
Pure 1T can't refer to Ryzen Google calculator. have to tweak it by yourself.


----------



## The_King

LtMatt said:


> Which is better? 3800Mhz CL15 GD off, or 3800Mhz CL14 GD off T2?


3800 CL14 with flat 14s 14-14-14 would be better than CL15 whether is 1T or 2T. IMO
GDM OFF 1T is hardly noticeable for me performance wise compared to 2T


----------



## The_King

ReyReverse said:


> OK good luck
> Pure 1T can't refer to Ryzen Google calculator. have to tweak it by yourself.


Only had My ZEN 3 CPU for around 3 days now. So still early days to get the right settings.
This thread is helping with that.


----------



## Audioboxer

Even just bumping my BCLK from 100 to 100.25 is enough to produce WHEA errors. Talk about a strict wall at 1900 on IF lol.


----------



## LtMatt

I've been struggling to get 3866Mhz CL14 T2 stable for a while now. Found this chart from @Veii and have since dialled it in at 10 pass 1usmus stable within a couple of hours. Now almost stable at 3933Mhz, what kind of voodoo magic is this.


----------



## ReyReverse

LtMatt said:


> Which is better? 3800Mhz CL15 GD off, or 3800Mhz CL14 GD off T2?


Low vdimm and provide same latency and bandwidth is better.


----------



## ReyReverse

Audioboxer said:


> Even just bumping my BCLK from 100 to 100.25 is enough to produce WHEA errors. Talk about a strict wall at 1900 on IF lol.


Maybe ROG Crosshair can solve it, Optimem III enhancements to the existing daisy chain topology to maximise signal integrity


----------



## The_King

ReyReverse said:


> Low vdimm and provide same latency and bandwidth is better.


CPU is stock so no PBO or CO. RAM latency at 2T 1.45V seems to be very good 53.6ns. Could be possible to get this into the 52s by tweaking a few things.









@ReyReverse
After some custom tweaks by me and the help of PBO got in the 52s. Does this mean my programs will open faster now?


----------



## The_King

Audioboxer said:


> Even just bumping my BCLK from 100 to 100.25 is enough to produce WHEA errors. Talk about a strict wall at 1900 on IF lol.


NO WHEA errors at 1933. Up your VSOC to 1.175V to 1.2V or higher if you feel comfortable with that. 1.2V is the Max I would run for daily.


----------



## Audioboxer

The_King said:


> NO WHEA errors at 1933. Up your VSOC to 1.175V to 1.2V or higher if you feel comfortable with that. 1.2V is the Max I would run for daily.
> View attachment 2561734


It's the 5950x, 2 chiplet processors stand next to no chance of WHEA free above 1900.


----------



## ReyReverse

The_King said:


> NO WHEA errors at 1933. Up your VSOC to 1.175V to 1.2V or higher if you feel comfortable with that. 1.2V is the Max I would run for daily.
> View attachment 2561734


Don't use random soc. 
You losing core package power
You go UEFI set Vsoc to offset negative maybe 0.05v then boot into Windows check ZenTimings VSOC minimum value.

Then go Bios manually key in that minimum amount after vdroop


----------



## Mach3.2

Audioboxer said:


> It's the 5950x, 2 chiplet processors stand next to no chance of WHEA free above 1900.


Not forgetting some silicons just suck. Such is luck. 🤣



For perspective I know 1866MHz IF is pretty decent and 33MHz of IF doesn't bring that much to the table in the grand scheme of things. _I just enjoy bitching leave me alone_.


----------



## umea

not completely on topic but im sort of out of the loop, haven't been paying attention to oc/hardware stuff for a while. is the 5800x3d able to hit higher FCLKs than most of the 5000 series (save for 2ccd 5600x)? it looks that way based off of the sheet, so not sure. TBH i've been pretty bored of my 5900x and these dogshit 4266cl17 bdie sticks and would love to **** around with another cpu

also not sure the performance difference between the 5800x3d vs 5900x for CPU bound games like CS/OW/Val, i see varying results from different places from 0 gain to huge gain. has anyone here done their own testing in this regard?


----------



## VPII

Okay, look I know I did not run TM5 for 25 cycles but my time was limted so I set it at 10 cycles, but will test 25 cycles later. I'm not 1005 impressed as my latency seem a little high but I am happy as it was doen running memory at 3866 instead of 3800 and it seems stable. What I found interesting is setting the VSOC, VDDG and VLDO voltages actually has an impact on the latencies . But here's my results, without changing those voltages in thge bios my latency would be a little over 60.


----------



## ReyReverse

VPII said:


> Okay, look I know I did not run TM5 for 25 cycles but my time was limted so I set it at 10 cycles, but will test 25 cycles later. I'm not 1005 impressed as my latency seem a little high but I am happy as it was doen running memory at 3866 instead of 3800 and it seems stable. What I found interesting is setting the VSOC, VDDG and VLDO voltages actually has an impact on the latencies . But here's my results, without changing those voltages in thge bios my latency would be a little over 60.
> View attachment 2561824


Nice nice~im waiting people like you figure out how to overclock his 5950x chip at 3866 and WHEA free. My 5950x been passed over 100 tm5 1usmus. But to me 3866 is my limit, I don't want to lose more core performance just for the ram speed. I've done some Tight CO last night, it push my all core to 4.125GHz
Single core 4.9GHZ
Maybe you have golden chip , golden MOBO and golden ram all core can hit more than me 4,150GHz 4.2G??


----------



## VPII

ReyReverse said:


> Nice nice~im waiting people like you figure out how to overclock his 5950x chip at 3866 and WHEA free. My 5950x been passed over 100 tm5 1usmus. But to me 3866 is my limit, I don't want to lose more core performance just for the ram speed. I've done some Tight CO last night, it push my all core to 4.125GHz
> Single core 4.9GHZ
> Maybe you have golden chip and golden MOBO, all and golden ram ,all core can hit more than me 4,150GHz 4.2G??


Thanks in all honesty, I only overclocked the cpu as it is the only way Aida pass without restarting PC. For when I run PBO with CO -25 all core and vcore undervolt it just restarts the moment it starts running the copy for memory bandwidth. If I just enable PBO instead of advance it would work but cpu performance is less.


----------



## ReyReverse

VPII said:


> Thanks in all honesty, I only overclocked the cpu as it is the only way Aida pass without restarting PC. For when I run PBO with CO -25 all core and vcore undervolt it just restarts the moment it starts running the copy for memory bandwidth. If I just enable PBO instead of advance it would work but cpu performance is less.


Go OCCT stress test then you will know what's your CPU all core frequency.


----------



## AsianOni

After more tweaking trying to get 3800CL14, this is the "best" I can get:








#2 would indicate timeout somewhere or not enough voltage somewhere. 60/20/20/20 gave me Cad_BUS related errors so I think 40/20/20/20 is fine ?
#3 I'm not too sure what's triggering it. It popped around cycle 17 so maybe tRFC too low ? Should I increase tWTR_ even more ?
How safe would it be to push more Vdimm with those resistances ?
Thanks in advance for the tips.


----------



## ReyReverse

maybe 40/20/30/20 .
It's calculate from Ryzen Google calculator right? I think only twr need increase to 16.


----------



## The_King

VPII said:


> Okay, look I know I did not run TM5 for 25 cycles but my time was limted so I set it at 10 cycles, but will test 25 cycles later. I'm not 1005 impressed as my latency seem a little high but I am happy as it was doen running memory at 3866 instead of 3800 and it seems stable. What I found interesting is setting the VSOC, VDDG and VLDO voltages actually has an impact on the latencies . But here's my results, without changing those voltages in thge bios my latency would be a little over 60.
> View attachment 2561824





VPII said:


> Thanks in all honesty, I only overclocked the cpu as it is the only way Aida pass without restarting PC. For when I run PBO with CO -25 all core and vcore under-volt it just restarts the moment it starts running the copy for memory bandwidth. If I just enable PBO instead of advance it would work but cpu performance is less.


You may/should get better latency and performance with GDM off 2T. Than GDM on 1T.
You can check for WHEA errors using HWINFO64 the reading is at the bottom of the sensor page. You can see a screenshot in my previous post.

Can't really go into the CO and set -25 all core and expect it to be stable. Performance is high because you pushing too high OC which is not stable.
I'm still learning how to perfect the CO myself lol But try from -5 and work your way up. Run y-cruncher 2.5B for stability testing before running TM5.

Update with PBO + CO


----------



## AsianOni

ReyReverse said:


> maybe 40/20/30/20 .
> It's calculate from Ryzen Google calculator right? I think only twr need increase to 16.


As a base yes, then it's trial & error after reading hundreds of pages of this thread. 
tCL14 seems too far for now. I'll settle to flat 15 and might try again when I add a dedicated fan.


----------



## VPII

The_King said:


> You may/should get better latency and performance with GDM off 2T. Than GDM on 1T.
> You can check for WHEA errors using HWINFO64 the reading is at the bottom of the sensor page. You can see a screenshot in my previous post.
> 
> Can't really go into the CO and set -25 all core and expect it to be stable. Performance is high because you pushing too high OC which is not stable.
> I'm still learning how to perfect the CO myself lol But try from -5 and work your way up. Run y-cruncher 2.5B for stability testing before running TM5.
> 
> Update with PBO + CO
> View attachment 2561884
> 
> 
> View attachment 2561842


Thanks I changed CO to -22 all core and it passed OCCT, funny thing is right after running OCCT I ran Aida64 again and it passed where as before when running PBO it will not pass.


----------



## ReyReverse

VPII said:


> Thanks I changed CO to -22 all core and it passed OCCT, funny thing is right after running OCCT I ran Aida64 again and it passed where as before when running PBO it will not pass.


you can't select multiple core and stress test. you have to do it one by one , give single core more power stress
it took me about couple hours do finish that. you have to do it again.


----------



## Arlina

Hi,

Using 4 DIMM ram degrades performance, why? I tried with 2 different bios(1260c and 1207 beta) and both are the same. I try default bios, only xmp and 3800mhz tweak;

2 DIMM Scores;






















4 DIMM Scores;





















%100 same settings.


----------



## Owterspace

Just messing around last night.. probably completely unstable.. but still pretty neat. It wont post with anything faster, so I didn't test it.


----------



## ReyReverse

Owterspace said:


> Just messing around last night.. probably completely unstable.. but still pretty neat. It wont post with anything faster, so I didn't test it.
> 
> View attachment 2562040


don't waste time on 4000MHz
550 XE Optimem II can't stable at 4k ramspeed
or you can sacrifice your core power for ramspeed. but trust me, its not worth .
you don't want your CPU all core run at 3.5Ghz.


----------



## Owterspace

ReyReverse said:


> 550 XE Optimem II can't stable at 4k ramspeed


Yes it can, with 2 sticks. With my -F and 5600X I am WHEA free at 2K 1:1 2 sticks. I can bench it at 2100 1:1. I havent had my 5600X on my XE yet. I was just messing around anyways. Nothing over 1900 fclk is stable with my 5900X.

Edit:


----------



## ReyReverse

Owterspace said:


> Yes it can, with 2 sticks. With my -F and 5600X I am WHEA free at 2K 1:1 2 sticks. I can bench it at 2100 1:1. I havent had my 5600X on my XE yet. I was just messing around anyways. Nothing over 1900 fclk is stable with my 5900X.
> 
> Edit:
> 
> View attachment 2562069


show proof. 


Owterspace said:


> Yes it can, with 2 sticks. With my -F and 5600X I am WHEA free at 2K 1:1 2 sticks. I can bench it at 2100 1:1. I havent had my 5600X on my XE yet. I was just messing around anyways. Nothing over 1900 fclk is stable with my 5900X.
> 
> Edit:
> 
> View attachment 2562069


can't compare like this

its about *signal integrity*

now I talking about high-end CPU.
5900x (12cores) have more core than 5600x (6 cores) 
less core less stress = clean signal

your 5900x probably can't do it at 4k ramspeed unless you have Crosshair Optimem III 
optimem III enhancements to the existing daisy chain topology to *MAXIMIZE signal integrity*

and like I said, unless you want to sacrifice your core power for ramspeed. 
think about it , its 5900x high end CPU not worth all core run at 3.5GHz. 

but single core you might still hit 4.5~5G, but its ridiculous, you loss overall performance.


----------



## toljan2884

1.45


----------



## toljan2884




----------



## toljan2884

View attachment 2562074
View attachment 2562074
View attachment 2562075


----------



## ReyReverse

toljan2884 said:


> View attachment 2562074
> View attachment 2562074
> View attachment 2562075


very nice, you probably can drop tRFC abit. 288 should be fine. can slightly improve your bandwidth maybe you have to add 1 step of vdimm if it unstable


----------



## The_King

ReyReverse said:


> very nice, you probably can drop tRFC abit. 288 should be fine. can slightly improve your bandwidth maybe you have to add 1 step of vdimm if it unstable


Its easy to run AIDA64 with a very unstable RAM OC. I can post ridiculously low timings with AIDA64 4000 14-15-15-30-45.
Would be great if people state whether the OC is stable and what voltage was used so that other users can test as well
Not at all stable but great numbers in AIDA64


----------



## Owterspace

ReyReverse said:


> show proof.


----------



## Owterspace

The_King said:


> Would be great if people state whether the OC is stable and what voltage was used so that other users can test as well


I did say it was unstable..

I probably have a shot or two of some crazy numbers, but they aren't stable either.


----------



## The_King

Owterspace said:


> I did say it was unstable..
> 
> I probably have a shot or two of some crazy numbers, but they aren't stable either.


I know lol
My post was not directed at your post and you did clearly say it was not stable. 
I know you from TPU Forums under a different name but same profile pic.


----------



## Owterspace

The_King said:


> I know lol
> My post was not directed at your post and you did clearly say it was not stable.
> I know you from TPU Forums under a different name but same profile pic.


Its all good my man 

I used to be freeagent here too.. but I changed my password one night while I was pretty hammed, and the email I used here was an isp account that I don't have anymore.. whoops


----------



## domdtxdissar

The_King said:


> Its easy to run AIDA64 with a very unstable RAM OC. I can post ridiculously low timings with AIDA64 4000 14-15-15-30-45.
> Would be great if people state whether the OC is stable and what voltage was used so that other users can test as well
> Not at all stable but great numbers in AIDA64
> View attachment 2562077


Kinda depends what you mean with "stable"..
its very easy to complete all stability benchmarks without error above 1900:3800 speeds, but for my dual CCD 5950x, the performance scaling in heavy workloads is not there.
(Putting up big numbers in aida is childsplay)

Example below, 5950x @ 2000:4000

1 hour OCCT large dataset -> completed
2 hours y-cruncher torture test with all enabled -> completed
100% runmemtestpro -> completed
1 hour karhu ram test -> completed
















But when we try to check the performance scaling in heavy benchmarks it looks like this: (done at lowish static OC @ 4600/4500mhz)

1833:3666 = 651.5784 average GFlops








1866:3733 = 655.2794 average GFlops (+3.701 GFlops)








1900:3800 = 657.5407 average GFlops (+2.261 GFlops)








1933:3866 = 357.5543 average GFlops








1966:3933 = 437.6164 average GFlops








2000:4000 = 204.0170 average GFlops








As we can see, there is only scaling in light "benchmarks" such as Aida64 above 1900 flck (for my system), but as soon as i hit it with a real heavy workload, the performance is out the window..

My current maxbench in Linpack Xtreme is 730 gflops (done at async 1900:4466)


----------



## The_King

domdtxdissar said:


> Kinda depends what you mean with "stable"..


Stable meaning it can pass TM5 or HCI under the stability testing section in the first post of this thread. Losing Gflops is another matter has I run 3800/1900 daily myself.

Also easy to pass 4000 C15 when your RAM is rated 4000 C14. 



domdtxdissar said:


> (Putting up big numbers in aida is childsplay)


This was exactly my point in my post that you replied to. 
I have no WHEA errors at FCLK 2000 but dont run that daily has 3800 C15 give me better overall performance.


----------



## domdtxdissar

The_King said:


> Also easy to pass 4000 C15 when your RAM is rated 4000 C14.


Thats was mostly because i wanted to keep the ~same timings for all the runs all the way up to 4466MT/s 

Here are some other timings used when i played around with the 5800x3d
(no real performance scaling above 1900, but didn't get major negative scaling until i passed 4066)








1900:
Linpack extended 8gb = 349.4 average gflops
Y-cruncher 2.5b = 95.231s


1966:
Linpack extended 8gb = 347.5 average gflops
Y-cruncher 2.5b = 94.966s


2000:
Linpack extended 8gb = 349.1 average gflops
Y-cruncher 2.5b = 94.377s


2033:
Linpack extended 8gb = 349.9 average gflops
Y-cruncher 2.5b = 93.764s


2066: (t2)
Linpack extended 8gb = 349.2 average gflops
Y-cruncher 2.5b = 96.755s


2100: (t2)
Linpack extended 8gb = 342.7 average gflops
Y-cruncher 2.5b = 101.177s



The_King said:


> This was exactly my point in my post that you replied to.
> I have no WHEA errors at FCLK 2000 but dont run that daily has 3800 C15 give me better overall performance.


Fully agree, Aida numbers dont mean much these days, better to compare "real memory performance" in performance-benchmarks such dram calc, SotTR, Linpack xtreme, y-cruncher and/or the xmr-stak-rx miner etc.
(other important thing when doing these comparisons is to keep a static CPU OC so PBO dont affect the results)

Must also say its much easier to "stabilize" performance above 1900 flck with single CCD than with dual CCD cpus..


----------



## Owterspace

Man, those 600s in Linpack are nice. I am happy when I see 520 lol.


----------



## Luggage

Owterspace said:


> Man, those 600s in Linpack are nice. I am happy when I see 520 lol.
> 
> View attachment 2562115
> 
> 
> View attachment 2562115


Just add more cold.


----------



## Owterspace

Luggage said:


> Just add more cold.


I can’t, winter is over


----------



## ReyReverse

domdtxdissar said:


> Kinda depends what you mean with "stable"..
> its very easy to complete all stability benchmarks without error above 1900:3800 speeds, but for my dual CCD 5950x, the performance scaling in heavy workloads is not there.
> (Putting up big numbers in aida is childsplay)
> 
> Example below, 5950x @ 2000:4000
> 
> 1 hour OCCT large dataset -> completed
> 2 hours y-cruncher torture test with all enabled -> completed
> 100% runmemtestpro -> completed
> 1 hour karhu ram test -> completed
> View attachment 2562101
> 
> View attachment 2562094
> 
> But when we try to check the performance scaling in heavy benchmarks it looks like this: (done at lowish static OC @ 4600/4500mhz)
> 
> 1833:3666 = 651.5784 average GFlops
> View attachment 2562095
> 
> 
> 1866:3733 = 655.2794 average GFlops (+3.701 GFlops)
> View attachment 2562096
> 
> 
> 1900:3800 = 657.5407 average GFlops (+2.261 GFlops)
> View attachment 2562097
> 
> 
> 1933:3866 = 357.5543 average GFlops
> View attachment 2562098
> 
> 
> 1966:3933 = 437.6164 average GFlops
> View attachment 2562099
> 
> 
> 2000:4000 = 204.0170 average GFlops
> View attachment 2562100
> 
> 
> As we can see, there is only scaling in light "benchmarks" such as Aida64 above 1900 flck (for my system), but as soon as i hit it with a real heavy workload, the performance is out the window..
> 
> My current maxbench in Linpack Xtreme is 730 gflops (done at async 1900:4466)
> View attachment 2562103


Very nice man. This what we want to see. 24/7 stable ko


----------



## domdtxdissar

ReyReverse said:


> Very nice man. This what we want to see. 24/7 stable ko


So far non of what i have posted above is my actual 24/7 memory settings for the 5950x, but i can re-share some of the screens from "project memory air-cooling edition overkill" again 

























Extra cooling allows me to daily 1.6vdimm without any problems.. Maximum memory temp is ~35 degrees with my current setup.

And this is my everyday 1900:3800 24/7 profile for the 5950x --> *Stabil in everything and no performance regressions in anything @ 1900:3800*
(1.6 vdimm allows me to run tWTRS = 2, tWRRD/tRDWR @ 2/8 and tRFC = 216 (sub 120ns))















25 cycles TestMem 5 1usmus cfg
1 hour OCCT CPU large dataset
2 hours y-cruncher all tests
I made a mistake with the saving of screenshot, but i also had 4 hours of karhu ram test completed in same screen

Before i had the extra cooling i was running these settings @ 1.57 vdimm







200%RunmemtestPro = ~*1.5 hour*
25 cycles TestMEM5 1usmus cfg =* ~2.5 hours*
Y-cruncher, all tests = *6 hours*
20000% karhu ram test = ~*10.5 hours*


----------



## PJVol

domdtxdissar said:


> but as soon as i hit it with a real heavy workload, the performance is out the window


Imho, scaling deficits are mostly seen in workloads that quickly saturate memory bandwidth, i.e. where the effect of RAM frequency vs. throughput in that particular benchmark is clearly noticeable. For example, Geekbench 5, Linpack, AIDA Photoworxx.


----------



## Pierce

hey guys,

Can I get this Ram to DDR4 4600? Bought it the other day and it is at 3800
Amazon.com: TEAMGROUP T-Force Xtreem ARGB 5066MHz CL20 16GB (2x8GB) PC4-40600 Dual Channel DDR4 DRAM Desktop Gaming Memory Ram (Blue) for Z590 - TF10D416G5066HC20BDC01 : Clothing, Shoes & Jewelry

My current setup:
Ryzen 3600 at 4.2
Auros B550 Elite Motherboard
DDR4 3800. IF 1900, 18-19-19-19-38 1.4V

I tried a couple of different timings and couldn't get it to boot. Not sure if I need to increase VDD_SOC, VDDP, VDDG, etc.)

Thanks


----------



## ReyReverse

domdtxdissar said:


> So far non of what i have posted above is my actual 24/7 memory settings for the 5950x, but i can re-share some of the screens from "project memory air-cooling edition overkill" again
> View attachment 2562150
> View attachment 2562151
> View attachment 2562152
> View attachment 2562153
> 
> Extra cooling allows me to daily 1.6vdimm without any problems.. Maximum memory temp is ~35 degrees with my current setup.
> 
> And this is my everyday 1900:3800 24/7 profile for the 5950x --> *Stabil in everything and no performance regressions in anything @ 1900:3800*
> (1.6 vdimm allows me to run tWTRS = 2, tWRRD/tRDWR @ 2/8 and tRFC = 216 (sub 120ns))
> View attachment 2562154
> 
> View attachment 2562155
> 
> 25 cycles TestMem 5 1usmus cfg
> 1 hour OCCT CPU large dataset
> 2 hours y-cruncher all tests
> I made a mistake with the saving of screenshot, but i also had 4 hours of karhu ram test completed in same screen
> 
> Before i had the extra cooling i was running these settings @ 1.57 vdimm
> View attachment 2562157
> 
> 200%RunmemtestPro = ~*1.5 hour*
> 25 cycles TestMEM5 1usmus cfg =* ~2.5 hours*
> Y-cruncher, all tests = *6 hours*
> 20000% karhu ram test = ~*10.5 hours*


Same like you Noctua 60mm x2 here , but I use original gskill heatsink. Maybe I will consider buy some raw bin DIY , your one is real OC good job man! I can see your all core run at stock frequency, I hope people understand ram oc should without losing any core performance.


----------



## Gegu

Hi guys,
do any of you have a description of error codes for anta77 absolut?
I get error 7 during test and I don't know what it means.


----------



## Audioboxer

Gegu said:


> Hi guys,
> do any of you have a description of error codes for anta77 absolut?
> I get error 7 during test and I don't know what it means.


Just switch to 1usmus v3 and run 25 cycles and see what error it gives. Easier to diagnose.

If it passes a 25, run a 50. Occasionally a powerdown issue can pop up during a 50 cycle.


----------



## Luggage

So just for curiosity I tried 3800cl16T2 on my old 3800X system, that I've always ran at 3600cl16GDM before, since I had to update a bunch of bios versions.
Low effort, throw a few settings like vdimm, tfaw and trfc on it and the rest is "MSI try-it" and auto.

... and it almost worked, almost 3h yc and 1 error on cycle 10 or 11 on 1usmus.


http://imgur.com/a/j4kRMww


So what did I fub?
Really don't have energy to do a proper tune but If this can be made stable with a few changes I'll be happy


----------



## speed_88

Done, any tips to improve or just sit and enjoy.
vDIMM 1.4v


----------



## ReyReverse

speed_88 said:


> Done, any tips to improve or just sit and enjoy.
> vDIMM 1.4v
> 
> 
> View attachment 2562223
> 
> 
> View attachment 2562222
> 
> 
> View attachment 2562220
> View attachment 2562221


no advice can give. low vdimm = win


----------



## PJVol

speed_88 said:


> Done, any tips to improve or just sit and enjoy.


I saw a couple of stable fclk 2000 presets with an asus b550 strix boards and a 5600X.
Can you post the AIDA Photoworxx test result, since your Memory Write is a bit of concern? (has proved to be a good indicator of bus throttling)
Here are mine for the reference:


----------



## ReyReverse

PJVol said:


> I saw a couple of stable fclk 2000 presets with an asus b550 strix boards and a 5600X.
> Can you post the AIDA Photoworxx test result, since your Memory Write is a bit of concern? (has proved to be a good indicator of bus throttling)
> Here are mine for the reference:
> View attachment 2562235


Less core = less package power.
Probably less than 100w
90w enough to push all core perform at 100% already. 

Maybe you can try lower your 
ppt to 85
tdc maybe 70
Edc 85

Then raise your memory frequency step by step til it unstable.


----------



## Gegu

Audioboxer said:


> Just switch to 1usmus v3 and run 25 cycles and see what error it gives. Easier to diagnose.
> 
> If it passes a 25, run a 50. Occasionally a powerdown issue can pop up during a 50 cycle.



I enabled TM5 1usmus v3 25 cycles, but TM5 stopped working after 7th cycle, would not resume. Is this some kind of bug or ram instability?

BTW - I'm working on AGESA 1.2.0.3, maybe should I switch to 1.2.0.7 for better stability?

These are my current timings:


----------



## andremoreira6215

Gegu said:


> I enabled TM5 1usmus v3 25 cycles, but TM5 stopped working after 7th cycle, would not resume. Is this some kind of bug or ram instability?
> 
> BTW - I'm working on AGESA 1.2.0.3, maybe should I switch to 1.2.0.7 for better stability?
> 
> These are my current timings:
> 
> View attachment 2562244


Stay at 1.2.0.3c. Try to add more Vddp and see if it not stops. Mine happens the same with low Vddp.


----------



## speed_88

PJVol said:


> I saw a couple of stable fclk 2000 presets with an asus b550 strix boards and a 5600X.
> Can you post the AIDA Photoworxx test result, since your Memory Write is a bit of concern? (has proved to be a good indicator of bus throttling)
> Here are mine for the reference:
> View attachment 2562235


----------



## Audioboxer

Gegu said:


> I enabled TM5 1usmus v3 25 cycles, but TM5 stopped working after 7th cycle, would not resume. Is this some kind of bug or ram instability?
> 
> BTW - I'm working on AGESA 1.2.0.3, maybe should I switch to 1.2.0.7 for better stability?
> 
> These are my current timings:
> 
> View attachment 2562244


A timeout? That's either RAM or CPU instability. First thing to try to rule it out is turn off PBO and turn off your curve. Run TM5 again and see if it still times out.

If it does, it's memory. Things to try on that front

Drop CCD/IOD. Sometimes IOD being close to VSOC can cause issues. You should be OK at the figures you are at, but I'd maybe try 1.0v on CCD and 1.025v on IOD. I run lower than that myself, but it's often mobo/CPU dependent what your IF needs voltage wise.

ProcODT might be better at 36.9 or below.

Run tCWL/tRDWR on auto, should train at 14/9 or 14/8, both of which will perform better than 12/10 anyway with tCL at 14.

Bump up tRFC a bit.

Try running CkeDrvStr 30. My memory likes this over 24. CmdDrvStr is also something often liked at 24










40/24/24/30, VSOC AUTO, VDDP 0.9, CCD 0.975 and IOD 1.0 were my magic numbers. But I do have a 2 DIMM B550 and a stupid bin of memory.

But I myself have also experienced lots of challenges with TM5 timeouts. Once it was my CPU curve being slightly unstable and a core crashing during TM5. All the other times it seemed to be either minor voltage issues, powerdown issues and small changes needed with resistances.

Good news for you is it will probably be a minor instability easily fixable without a performance hit, bad news is it could be a number of things so you have to patiently track it down.

For what it is worth make sure you are on the latest AMD Chipset drivers. 4.03.03.431 I believe. Months back Windows 11 with some of the earlier chipset drivers was also a bit funky with CPU overboosting issues that seemed to randomly trip TM5.


----------



## PJVol

@speed_88
That's fine. Good point to settle. Or you may try to push a bit further just for fun )
Mine needed 1.50 - 1.55V Vdimm for that, may be you'll have more luck.


----------



## Gegu

Audioboxer said:


> A timeout? That's either RAM or CPU instability. First thing to try to rule it out is turn off PBO and turn off your curve. Run TM5 again and see if it still times out.
> 
> If it does, it's memory. Things to try on that front
> 
> Drop CCD/IOD. Sometimes IOD being close to VSOC can cause issues. You should be OK at the figures you are at, but I'd maybe try 1.0v on CCD and 1.025v on IOD. I run lower than that myself, but it's often mobo/CPU dependent what your IF needs voltage wise.
> 
> ProcODT might be better at 36.9 or below.
> 
> Run tCWL/tRDWR on auto, should train at 14/9 or 14/8, both of which will perform better than 12/10 anyway with tCL at 14.
> 
> Bump up tRFC a bit.
> 
> Try running CkeDrvStr 30. My memory likes this over 24. CmdDrvStr is also something often liked at 24
> 
> View attachment 2562248
> 
> 
> 40/24/24/30, VSOC AUTO, VDDP 0.9, CCD 0.975 and IOD 1.0 were my magic numbers. But I do have a 2 DIMM B550 and a stupid bin of memory.
> 
> But I myself have also experienced lots of challenges with TM5 timeouts. Once it was my CPU curve being slightly unstable and a core crashing during TM5. All the other times it seemed to be either minor voltage issues, powerdown issues and small changes needed with resistances.
> 
> Good news for you is it will probably be a minor instability easily fixable without a performance hit, bad news is it could be a number of things so you have to patiently track it down.
> 
> For what it is worth make sure you are on the latest AMD Chipset drivers. 4.03.03.431 I believe. Months back Windows 11 with some of the earlier chipset drivers was also a bit funky with CPU overboosting issues that seemed to randomly trip TM5.


Thanks for reply.

Well, I was running TM5 with PBO turned off, so I doubt it's CPU-related.

First I will change VDDP / CCD / IOD and will run TM5.
If it doesn't work, I'll try your other suggestions.

About tRFC - I think it's ok, I have a cooler on my ram so the tRFC temperature sensitivity shouldn't be a problem.

And about the stupid bin - we have this same bin, just another series. Mine is Tridentz Neo


----------



## PJVol

ReyReverse said:


> Maybe you can try lower your
> ppt to 85
> tdc maybe 70
> Edc 85


I'm ok with it, but thanks anyway.


----------



## Audioboxer

Gegu said:


> Thanks for reply.
> 
> Well, I was running TM5 with PBO turned off, so I doubt it's CPU-related.
> 
> First I will change VDDP / CCD / IOD and will run TM5.
> If it doesn't work, I'll try your other suggestions.
> 
> About tRFC - I think it's ok, I have a cooler on my ram so the tRFC temperature sensitivity shouldn't be a problem.
> 
> And about the stupid bin - we have this same bin, just another series. Mine is Tridentz Neo


Ah yeah, so it is, I read it as 4000C16 for some reason!

My guess is it's probably the resistances, try 40/24/24/30 or 40/24/24/24 with ProcODT at 36.9 or 34.3 next.


----------



## Veii

Luggage said:


> So what did I fub?


How much is 16+28


----------



## Luggage

Veii said:


> How much is 16+28


Doh!


----------



## heptilion

So I have been running 3800 these timings with 6-3-3 Tcke 9 3-3-15 40-20-20-20 for over a year now and decided try without setup timings. if i dont run 3-3-15 i should run somthing like 40-20-30-20 for stability but ended up testing 40-20-20-20 and passed 4 runs of y-cruncher and 30 cycles of test mem. I have managed to drop my vsoc and iod down by quite a bit as well. 

decided to test with a lower procodt since i am running a low soc and also with 40-20-30-20 also passed y-cruncher and warzone so far. currently running testmem to check stability.

Same vdim voltage 1.48 in all 3 tests. 

Latency is same 54.5/6ns

My question is, is it necessary to run 40-20-30-20 if using TCKE 9? does having higher CSOdtDrvStr affect anything else other than help stability? Is it okay to run with such a low soc if so far there are no issues? I am not seeing any audio issues so far with the low iod voltage as well. 

Running a low soc should ultimately help cores boost more?


----------



## Gegu

Audioboxer said:


> Ah yeah, so it is, I read it as 4000C16 for some reason!
> 
> My guess is it's probably the resistances, try 40/24/24/30 or 40/24/24/24 with ProcODT at 36.9 or 34.3 next.


Well, you were probably right 

I've made another TM5 run on 40/24/24/24 on 1usmus v3 and now it passes 25 cycles with zero errors, and no timeout


----------



## heptilion

heptilion said:


> So I have been running 3800 these timings with 6-3-3 Tcke 9 3-3-15 40-20-20-20 for over a year now and decided try without setup timings. if i dont run 3-3-15 i should run somthing like 40-20-30-20 for stability but ended up testing 40-20-20-20 and passed 4 runs of y-cruncher and 30 cycles of test mem. I have managed to drop my vsoc and iod down by quite a bit as well.
> 
> decided to test with a lower procodt since i am running a low soc and also with 40-20-30-20 also passed y-cruncher and warzone so far. currently running testmem to check stability.
> 
> Same vdim voltage 1.48 in all 3 tests.
> 
> Latency is same 54.5/6ns
> 
> My question is, is it necessary to run 40-20-30-20 if using TCKE 9? does having higher CSOdtDrvStr affect anything else other than help stability? Is it okay to run with such a low soc if so far there are no issues? I am not seeing any audio issues so far with the low iod voltage as well.
> 
> Running a low soc should ultimately help cores boost more?
> 
> 
> View attachment 2562273
> View attachment 2562271
> View attachment 2562274


All 3 pass stress tests and gaming scenarios. So which one is the best to use and more reliable? All give same aida latency as well :/


----------



## Luggage

heptilion said:


> All 3 pass stress tests and gaming scenarios. So which one is the best to use and more reliable? All give same aida latency as well :/


Check speed with lin-x and y-c benchmark, fps in games. 3d mark TS.


----------



## ReyReverse

Gegu said:


> Well, you were probably right
> 
> I've made another TM5 run on 40/24/24/24 on 1usmus v3 and now it passes 25 cycles with zero errors, and no timeout
> 
> View attachment 2562296
> View attachment 2562297


golden chip!!! 3800 cl 14 vdimm only 1.2480v!!!! oh god
so nice


----------



## Luggage

Veii said:


> How much is 16+28


Fixed.
That cleared 1usmus, but ran hot for anta...

Lower vdimm, bump trfc, back to gdm.
Cleared short anta


http://imgur.com/a/sxHGbfw


Back to 1usmus 25.


----------



## domdtxdissar

domdtxdissar said:


> I will try the new bios for the Unify x max when i get home from work
> 
> Yesterday i also did some benchmate memory benchmarks.. If i ever get to overclock my cpu higher than 100.375mhz baseclock then your submissions are in danger @tcclaviger
> 
> SuperPi - 1M with BenchMate - 7sec 686ms - Ryzen 7 5800X3D @ 4567.2MHz
> SuperPi - 32M with BenchMate - 6min 4sec 610ms - Ryzen 7 5800X3D @ 4567.2MHz
> 
> PYPrime - 2b with BenchMate - 8sec 397ms
> 
> y-cruncher - Pi-25m - 0sec 501ms - Ryzen 7 5800X3D @ 4461.1MHz
> y-cruncher - Pi-1b - 32sec 75ms - Ryzen 7 5800X3D @ 4461.1MHz
> y-cruncher - Pi-2.5b - 1min 32sec 459ms - Ryzen 7 5800X3D @ 4450MHz
> 
> wPrime - 32m with BenchMate - 2sec 340ms - Ryzen 7 5800X3D @ 4461.4MHz
> wPrime - 1024m with BenchMate - 1min 4sec 98ms - Ryzen 7 5800X3D @ 4466.8MHz
> 
> 7-Zip - 105612 MIPS - Ryzen 7 5800X3D @ 4467MHz
> 
> PiFast with BenchMate - 17sec 400ms - Ryzen 7 5800X3D @ 4567MHz
> 
> Full 32gigs used in all benchmarks -> no maxmem used.


*Little comparison between 5800x3d @ 4550/4450mhz with ~4066MT/s memory and 5950x @ ~5200/5050mhz with ~4000MT/s memory*

SuperPi - 1M with BenchMate - 6sec 696ms - Ryzen 9 5950X @ 5213.3MHz
SuperPi - 32M with BenchMate - 5min 32sec 276ms - Ryzen 9 5950X @ 5213.4MHz

PYPrime - 2b with BenchMate - 9sec 779ms

y-cruncher - Pi-1b - 20sec 433ms - Ryzen 9 5950X @ 4775.2MHz
y-cruncher - Pi-2.5b - 58sec 362ms - Ryzen 9 5950X @ 4750.2MHz

wPrime - 32m with BenchMate - 1sec 486ms - Ryzen 9 5950X @ 5059.6MHz
wPrime - 1024m with BenchMate - 29sec 504ms - Ryzen 9 5950X @ 5034.5MHz

7-Zip - 205233 MIPS - Ryzen 9 5950X @ 4950.1MHz

PiFast with BenchMate - 15sec 170ms - Ryzen 9 5950X @ 5234.9MHz

No way around it, in these memory benchmarks cpu clockspeed is still king in everything except in PYprime
(dual CCD with twice the cores and much higher write bandwidth also helps )

Did also some Geekbenches but results seem to be all the place, not really sure why 

Geekbench3 - Single Core - 7390 points, Multi Core - 86068 points (ST and especially MT seems to be too low)








Geekbench4 - Single Core - 8104 points, Multi Core - 62264 points (Normal ST, MT score way to low)








Geekbench5 - Single Core - 1859 points, Multi Core - 17831 points (good ST, MT score way to low)








Think i have to do some more runs to figure out what going on here.. Could be down to whea throttling above 1900:3800 in the MT tests.


----------



## Luggage

Luggage said:


> Fixed.
> That cleared 1usmus, but ran hot for anta...
> 
> Lower vdimm, bump trfc, back to gdm.
> Cleared short anta
> 
> 
> http://imgur.com/a/sxHGbfw
> 
> 
> Back to 1usmus 25.





http://imgur.com/a/OdQriYR

1 error just as it ends - now what was this crap again?


----------



## heptilion

Luggage said:


> Check speed with lin-x and y-c benchmark, fps in games. 3d mark TS.


Did run bench tests and they are all within tolerable deviation. So difficult to say if one is better than the other.


----------



## Gegu

ReyReverse said:


> golden chip!!! 3800 cl 14 vdimm only 1.2480v!!!! oh god
> so nice


Ahaha, sadly - no, but it would be great 

It's just a ZenTimings bug that shows incorrect values for VDIMM voltage. 
My RAM is already running 1.5V


----------



## Leoshleo

Hi all. I just recently finished overclocking my 4x8gb SR Hynix DJR kit with the following settings.










Note: Vsoc is under load is actually 1.0875v and not 1.5500v being reported by zentimings. Also, VDIMM reported under hwinfo is actually 1.400v and not the 1.370v reported by zen timings. I think gigabyte boards overshoot VDIMM. ProcODT and drive strengths are on Auto.
CPU: 3700x Mobo: Gigabyte B550 Aorus Pro AX Agesa: 1.2.0.3B

My issue is when I run prime95 large ffts + folding with these settings I get thread errors, however zero WHEA errors. As a further test I left memory freq/fclk the same and removed all ram timings and ran prime95 large ffts and got zero thread errors. I do not get audio issues in game or youtube under either scenario.

Based on my understanding of this it seems the IMC can't keep up with the ram timings posted above. Would this be the case? Lastly, how do I solve this issue?

Thanks everyone.


----------



## umea

hey yall long time no see 

had to take apart my build to move to an open bench (which was a failure.. lol), but since its open and the radiator is out of the case i can now toss a fan on my ram and mess with it










stable, but not sure where to go from here, some notes:

tRP 13, tRCDRD 14, tWTRS 2, tWCL 12 do not work (have tried all of them individually, either don't post or instant blue screen
tRFC cannot go any lower without spitting out errors (even with staying at 38 degrees)


I know that my powering is probably very suboptimal, but it's worked in 2T GDM off, so I've left it as is. 

Any suggestions? Figured I'd ask here. Going to be asking a lot of questions anyways since I'll need help getting 1T-56 running stable.


----------



## Veii

Luggage said:


> http://imgur.com/a/OdQriYR
> 
> 1 error just as it ends - now what was this crap again?











Drop this 1.1v cLDO_VDDP to near 900-950 mV levels
even 1v would be better although likely not needed

You power dimms with this and procODT right now
Shouldn't
CAD_BUS 30-20-24-24 with much lower cLDO_VDDP
DIMMs should do easily 40-20-24-24 or on new AGESA 40-20-30-24
3rd value you'll figure out by time, if you have posting issues

Running 1.1+ cLDO_VDDP, also results in the same on Vermeer
Needed ClkDrvStr drop, RTT drop, vdimm drop & VDD18 weakening - to prevent crashing with it
There is zero need to run it that high. MCLK is just 1900 not 2400+ (edited, 2400+ requires it near 1075 levels, never 1900MCLK)
To FCLK it has no connection and to dimms, but to dimms it snowball-bothers ~ to FCLK only higher noise bothers


----------



## ioannis91

Hello guys. I've updated to latest AGESA 1.2.0.7 and the configuration that used to work in 1.2.0.5 does not work anymore. That's the timings.








On 1.2.0.5 I used to do 24/24/24/24 DvrStr, but on 1.2.0.7 it gave me error number 8. I tried 40/24/24/24 and it gave me error 10. Any ideas?


----------



## Luggage

Veii said:


> Drop this 1.1v cLDO_VDDP to near 900-950 mV levels
> even 1v would be better although likely not needed
> 
> You power dimms with this and procODT right now
> Shouldn't
> CAD_BUS 30-20-24-24 with much lower cLDO_VDDP
> DIMMs should do easily 40-20-24-24 or on new AGESA 40-20-30-24
> 3rd value you'll figure out by time, if you have posting issues
> 
> Running 1.1+ cLDO_VDDP, also results in the same on Vermeer
> Needed ClkDrvStr drop, RTT drop, vdimm drop & VDD18 weakening - to prevent crashing with it
> There is zero need to run it that high. MCLK is just 1900 not 2400+ (edited, 2400+ requires it near 1075 levels, never 1900MCLK)
> To FCLK it has no connection and to dimms, but to dimms it snowball-bothers ~ to FCLK only higher noise bothers


Thanks, it’s all auto now… I’ll look into it when I get back home on Thursday.
It’s on the “edge of stability”, cleared occt 1h, anta extreme 3cycle and another 25 cycles of 1usmus - just that 1st run errored out on last cycle


----------



## VPII

Look I've tried various settings but I cannot seem to drop my latency in Aida. ANy advice would be greatly appreciated. It hovers between 59.6 and 57.4


----------



## domdtxdissar

domdtxdissar said:


> *Little comparison between 5800x3d @ 4550/4450mhz with ~4066MT/s memory and 5950x @ ~5200/5050mhz with ~4000MT/s memory*
> 
> SuperPi - 1M with BenchMate - 6sec 696ms - Ryzen 9 5950X @ 5213.3MHz
> SuperPi - 32M with BenchMate - 5min 32sec 276ms - Ryzen 9 5950X @ 5213.4MHz
> 
> PYPrime - 2b with BenchMate - 9sec 779ms
> 
> y-cruncher - Pi-1b - 20sec 433ms - Ryzen 9 5950X @ 4775.2MHz
> y-cruncher - Pi-2.5b - 58sec 362ms - Ryzen 9 5950X @ 4750.2MHz
> 
> wPrime - 32m with BenchMate - 1sec 486ms - Ryzen 9 5950X @ 5059.6MHz
> wPrime - 1024m with BenchMate - 29sec 504ms - Ryzen 9 5950X @ 5034.5MHz
> 
> 7-Zip - 205233 MIPS - Ryzen 9 5950X @ 4950.1MHz
> 
> PiFast with BenchMate - 15sec 170ms - Ryzen 9 5950X @ 5234.9MHz
> 
> No way around it, in these memory benchmarks cpu clockspeed is still king in everything except in PYprime
> (dual CCD with twice the cores and much higher write bandwidth also helps )
> 
> Did also some Geekbenches but results seem to be all the place, not really sure why
> 
> Geekbench3 - Single Core - 7390 points, Multi Core - 86068 points (ST and especially MT seems to be too low)
> View attachment 2562325
> 
> 
> Geekbench4 - Single Core - 8104 points, Multi Core - 62264 points (Normal ST, MT score way to low)
> View attachment 2562326
> 
> 
> Geekbench5 - Single Core - 1859 points, Multi Core - 17831 points (good ST, MT score way to low)
> View attachment 2562327
> 
> 
> Think i have to do some more runs to figure out what going on here.. Could be down to whea throttling above 1900:3800 in the MT tests.


As expected, were running too high infinity fabric clock, resulting in whea-errors and throttling in the MT workloads..
When running my normal everyday 1900:3800 memoryspeed the scores are back to normal 

Geekbench 3: ST = 7651points and MT = 95277points (+9209points)















Geekbench 4: ST = 8062points and MT = 75117points (+12853points)








Geekbench 5: ST = 1859points and MT = 20477points (+2646points)


----------



## Audioboxer

I basically hope the term "WHEA" doesn't exist with AM5 lol.


----------



## ReyReverse

Just updated my bios to agesa1207. (Was 1206b)
I messed it up, no more 1T off can pass OCCT even at 3733MHz speed.

So headache now
Any agesa 1207 here?


----------



## Snipie-PT

ReyReverse said:


> Just updated my bios to agesa1207. (Was 1206b)
> I messed it up, no more 1T off can pass OCCT even at 3733MHz speed.
> 
> So headache now
> Any agesa 1207 here?


B550 Taichi with AGESA 1.2.0.7, moving forward from 1.2.0.3c for my 5900X is always loss of performance and memory stability hell!
I don't know why AMD or third party vendors are silently downgrading things, using Tool1007 I could figure out somethings:

EDC above 140A is broken (will change the below to worst)
VID Limit only 1.425v (AGESA 1.2.0.3c is 1.50v as it is since launch!)
"FIT PRE" and "LATCHUP" on "Voltage Limiters" tab, also change to 1.425v (again AGESA 1.2.0.3c is 1.50v!)

Don't know if @Veii is aware of this, but for me this is almost as planned obsolescence from AMD, and if true I will not buy again.
For system stability (to a certain degree, do not compare to server side of stability) this is also pure chaos when you just need to update a BIOS to fix issues, it should be as simple as loading your previous settings and work as usual, not the opposite...


----------



## KedarWolf

5950x $548 USD.









AMD Ryzen 9 5950X 16-core, 32-Thread Unlocked Desktop Processor : Electronics


Buy AMD Ryzen 9 5950X 16-core, 32-Thread Unlocked Desktop Processor: CPU Processors - Amazon.com ✓ FREE DELIVERY possible on eligible purchases



www.amazon.com


----------



## Luggage

Snipie-PT said:


> B550 Taichi with AGESA 1.2.0.7, moving forward from 1.2.0.3c for my 5900X is always loss of performance and memory stability hell!
> I don't know why AMD or third party vendors are silently downgrading things, using Tool1007 I could figure out somethings:
> 
> EDC above 140A is broken (will change the below to worst)
> VID Limit only 1.425v (AGESA 1.2.0.3c is 1.50v as it is since launch!)
> "FIT PRE" and "LATCHUP" on "Voltage Limiters" tab, also change to 1.425v (again AGESA 1.2.0.3c is 1.50v!)
> 
> Don't know if @Veii is aware of this, but for me this is almost as planned obsolescence from AMD, and if true I will not buy again.
> For system stability (to a certain degree, do not compare to server side of stability) this is also pure chaos when you just need to update a BIOS to fix issues, it should be as simple as loading your previous settings and work as usual, not the opposite...


“We” are all aware since 1204…



http://imgur.com/a/d5cReXo


Anyone in position to say if it’s intentional or not stays silent…


----------



## ReyReverse

no idea how to 1T off again, but 2T my tFAW can do 12, this is extremely fast cycle. if I run TM5 1usmus probably 2mins~2.5mins per cycle


----------



## MrHoof

tFAW lowest can only be 4xtRRDS so 16 if its set lower it should be auto corrected and should not show a messureable difference.

edit:


ParameterFunctiontRRD_SWhen issuing consecutive ACTIVATE commands to banks of different bank groups, the ACTIVATE commands have to be separated by tRRD_S (row-to-row delay--short)tRRD_LIf the banks belong to the same bank group, their ACTIVATEs have to be separated by tRRD_L (row-to-row delay--long)tFAW_Four Activate Window_ or sometimes also called _Fifth Activate Window_ is a timing restriction. tFAW specifies a window within which only four activate commands can be issued. So, you can issue ACTIVATE commands back-to-back with tRRD_S between them, but once you have completed 4 activates you cannot issue another one until the tFAW window expires.


----------



## ReyReverse

MrHoof said:


> tFAW lowest can only be 4xtRRDS so 16 if its set lower it should be auto corrected and should not show a messureable difference.
> 
> edit:
> 
> 
> ParameterFunctiontRRD_SWhen issuing consecutive ACTIVATE commands to banks of different bank groups, the ACTIVATE commands have to be separated by tRRD_S (row-to-row delay--short)tRRD_LIf the banks belong to the same bank group, their ACTIVATEs have to be separated by tRRD_L (row-to-row delay--long)tFAW_Four Activate Window_ or sometimes also called _Fifth Activate Window_ is a timing restriction. tFAW specifies a window within which only four activate commands can be issued. So, you can issue ACTIVATE commands back-to-back with tRRD_S between them, but once you have completed 4 activates you cannot issue another one until the tFAW window expires.


oic.......I usually do trdx4=tFaw . Im kinda like soul lost , I accidentally keyed tFaw 12,
Agesa 1207 update really messed me up today


----------



## dk_mic

Luggage said:


> “We” are all aware since 1204…
> 
> 
> 
> http://imgur.com/a/d5cReXo
> 
> 
> Anyone in position to say if it’s intentional or not stays silent…


well there is this ¯\_(ツ)_/¯

__
https://www.reddit.com/r/overclocking/comments/tktuy7/_/i1tjjbg


----------



## KedarWolf

domdtxdissar said:


> As expected, were running too high infinity fabric clock, resulting in whea-errors and throttling in the MT workloads..
> When running my normal everyday 1900:3800 memoryspeed the scores are back to normal
> 
> Geekbench 3: ST = 7651points and MT = 95277points (+9209points)
> View attachment 2562473
> View attachment 2562468
> 
> 
> Geekbench 4: ST = 8062points and MT = 75117points (+12853points)
> View attachment 2562469
> 
> 
> Geekbench 5: ST = 1859points and MT = 20477points (+2646points)
> View attachment 2562470


What are your PBO settings on your 5950x. I get like 1665/19859 GB5 with a really good CO Curve and Cl14 3800 RAM.


----------



## domdtxdissar

KedarWolf said:


> What are your PBO settings on your 5950x.


Really high, got MT scaling all the way up to 350ppt, 240tdc and 260edc in GB3, so i used that for all these GB benchmarks 



> Testing:
> 350/100/120 = 7689 and 82734
> 350/120/140 = 7700 and 87627
> 350/140/160 = 7699 and 88898
> 350/160/180 = 7687 and 91259
> 350/180/200 = 7674 and 92678
> 350/200/220 = 7687 and 93472
> 350/220/240 = 7671 and 94247
> 350/240/260 = 7659 and 94733
> 350/260/280 = 7656 and 93930 + 7633 and 94384


With lower PBO settings i could get better ST score, at the expense of MT score..

These are maxed MT runs with static OC's @ ~4950/4800mhz



















Will maybe do some maxed ST runs next


----------



## Veii

MrHoof said:


> tFAW lowest can only be 4xtRRDS so 16 if its set lower it should be auto corrected and should not show a messureable difference.
> 
> edit:
> 
> 
> ParameterFunctiontRRD_SWhen issuing consecutive ACTIVATE commands to banks of different bank groups, the ACTIVATE commands have to be separated by tRRD_S (row-to-row delay--short)tRRD_LIf the banks belong to the same bank group, their ACTIVATEs have to be separated by tRRD_L (row-to-row delay--long)tFAW_Four Activate Window_ or sometimes also called _Fifth Activate Window_ is a timing restriction. tFAW specifies a window within which only four activate commands can be issued. So, you can issue ACTIVATE commands back-to-back with tRRD_S between them, but once you have completed 4 activates you cannot issue another one until the tFAW window expires.


Half

Do not expect Global JEDEC to behave the same as IMC's capabilities & ontop AMD's viewpoint and implementation
tRRD_ behaves different on DR and up to BGS mode
tFAW can be higher and lower
Behavior is different between Intel and AMD
There is no linear behavior of tFAW. More than one action happen at the same time ~ soo there can't be an "only 4x is allowed" rule/thing


Snipie-PT said:


> Don't know if @Veii is aware of this, but for me this is almost as planned obsolescence from AMD, and if true I will not buy again.


Aware of both
Not planed obsolesce but irresponsible foreshadowing
Bad communication between Fabrication Engineering and Software Engineers
Add ontop marketing and media missjudging SVI2 capabilities ~ aand it's a mess
There is no right answer, too many "it depends". Too many "if substrate is at detected Q rating X , FIT will behave Y"
"Constant voltage as pre intel 12th gen" ~ to what people are used, can not be compared. Switching freq and hold freq is much much faster ~ bellow 2 digit ms timewindow
Sadly the same goes for the Frequency part. Too much focus on a fixed value and barely any focus on the effective clock value. Then if focus on the effective clock value ~ no focus on the FIT part.

Samples simply are throttled strongly by AMD.
They can run higher than 5Ghz , which current Hydra tries to proof ~ but everyone fights against FIT.
The sample will randomly just crash and shut down ~ without it being an instability issue, but simply AMD Software Engineers predefined Limits

EDIT:
once you've upgraded,
You should redo CO, as V/F curve changed along the different CO values (how much VID cut by CO)


Audioboxer said:


> I basically hope the term "WHEA" doesn't exist with AM5 lol.


Can't give you a good promise
But i hope, they accidentally fixed the overboosting issues ~ soo the rest resolves by itself


----------



## Luggage

KedarWolf said:


> What are your PBO settings on your 5950x. I get like 1665/19859 GB5 with a really good CO Curve and Cl14 3800 RAM.


If you put .gb5 (4,3) at the end of the url you see your top sc boost during the bench.
With cold water I get:





Micro-Star International Co., Ltd. MS-7C35 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7C35 with an AMD Ryzen 7 5800X processor.



browser.geekbench.com




Now it’s warmer so I drop down a bit.





Micro-Star International Co., Ltd. MS-7C35 - Geekbench Browser


Benchmark results for a Micro-Star International Co., Ltd. MS-7C35 with an AMD Ryzen 7 5800X processor.



browser.geekbench.com


----------



## PJVol

Snipie-PT said:


> I don't know why AMD or third party vendors are silently downgrading things


How do you imagine limiting max VID should work separately for the X and X3D chips since they both have the same FW blobs, both being Vermeer (family 19h model 21h) ?


----------



## Snipie-PT

PJVol said:


> How do you imagine limiting max VID should work separately for the X and X3D chips since they both have the same FW blobs, both being Vermeer (family 19h model 21h) ?


In the extreme of laziness, maybe separated BIOS releases for both I guess?
Better solution, code a verification routine to check a different unique camp, that identifies what model is what?
Damn, if the main GUI of the UEFI is able to tell me what model of CPU I'm running after POST, why the hell a firmware that is developed by the manufacturer cannot identify it and adapt?
I bet each one have a unique SKU or SN, that can be matched within a range with unique common identifier, and load the correct values for each.

Just some ideas, but...


----------



## PJVol

Veii said:


> There is no linear behavior of tFAW. More than one action happen at the same time ~ soo there can't be an "only 4x is allowed" rule/thing


Seems like this. Never seen tFAW has any meaninful impact (in a 6-24 range) on memory performance with the 5600X. At least not in AIDA.



Snipie-PT said:


> In the extreme of laziness


Or man-ours spent on accounting for every X3D specific, especially since it was clearly stated that 1204+ agesa is for the X3D owners.
I personally don't really understand what's the point to update 1203b/c fw for 2D Vermeer's.


----------



## Snipie-PT

PJVol said:


> Or man-ours spent on accounting for every X3D specific, especially since it was clearly stated that 1204+ agesa is for the X3D owners.
> I personally don't really understand what's the point to update 1203b/c fw for 2D Vermeer's.


How about fTPM stuttering fix? Just one from the top of my head...
But in my opinion if things are updated is usually for better not for worst, the very least acceptable scenario the same performance levels.
I use a dedicated TPM-SPI module, so I can stay in 1.2.0.3c for a while, but this sh**show should be address, if someone updates to Windows 11 and uses fTPM from the CPU, only have two options:

High performance with stutters. (AGESA 1.2.0.3c)
Lower performance without stutters. (AGESA 1.2.0.7)
Not acceptable as a customer, my view and opinion ofc, respect others also.


----------



## Audioboxer

Snipie-PT said:


> How about fTPM stuttering fix? Just one from the top of my head...
> But in my opinion if things are updated is usually for better not for worst, the very least acceptable scenario the same performance levels.
> I use a dedicated TPM-SPI module, so I can stay in 1.2.0.3c for a while, but this sh**show should be address, if someone updates to Windows 11 and uses fTPM from the CPU, only have two options:
> 
> High performance with stutters. (AGESA 1.2.0.3c)
> Lower performance without stutters. (AGESA 1.2.0.7)
> Not acceptable as a customer, my view and opinion ofc, respect others also.


It was always likely the way things get "fixed" in AGESA this late on in the hardware cycle was just by nerfing performance. Things unstable? Just make it less powerful/lower voltages/reduce boost clocks and so on.

Not done any benching on 1.2.0.7 myself, I just sort of gave up a while back with benching, reduced my PBO to 140 EDC and called it a day. I mean, it removes the fun found in forums like this with discussing OCs, benching and so on, but hey, no more raging at AGESA/WHEA/IF/AMD, just coasting till I decide what to do next when I move to current gen.


----------



## VPII

ReyReverse said:


> you can't select multiple core and stress test. you have to do it one by one , give single core more power stress
> it took me about couple hours do finish that. you have to do it again.


Sorry but I tend to prefer doing it the simple way. I mean my system passed OCCT at -25 all core but Aida64 would restart my computer while doing the memory bandwidth cache test, but with -22 it passes without an issue.


----------



## heptilion

anyone know whats happening with the ryzen google calculator? Its locked out for me now and request permission. anyone able to share a working copy?


----------



## KedarWolf

@Veii Could the new version TM5A.exe get false errors if L2 prefetcher is disabled?

I ask because I get a few errors running it when the prefetcher is disabled, however, after hours of gaming, there are zero game crashes or BSODs.

Sometimes only one usmus error 3.


----------



## ReyReverse

VPII said:


> Sorry but I tend to prefer doing it the simple way. I mean my system passed OCCT at -25 all core but Aida64 would restart my computer while doing the memory bandwidth cache test, but with -22 it passes without an issue.


Hi forgot to tell
CCD 0 =OCCT stress test result +5 = best value number 
(example= OCCT core 4# passed -25, +5 , core 4# best number= -20 
CCD 1= don't need to change anything. just key in OCCT result


----------



## ReyReverse

ReyReverse said:


> Hi forgot to tell
> CCD 0 =OCCT stress test result -5 = best value number
> CCD 1= don't need to change anything. just key in OCCT result


----------



## ReyReverse

heptilion said:


> anyone know whats happening with the ryzen google calculator? Its locked out for me now and request permission. anyone able to share a working copy?


yea, bosses set restriction, no more Ryzen Gooogle Calculator. 
luckily I got copied.


----------



## ReyReverse

is this true? MSI MEG x570 ACE support faster memory?


----------



## Luggage

ReyReverse said:


> View attachment 2562695
> 
> is this true? MSI MEG x570 ACE support faster memory?


Who says? This looks sort of like *serbenchmark - if so, you can assume they are talking out of their *sses.

Supported - just look at qvl at vendor sites.
And that’s just xmp - how good they work for real oc of memory is another thing.


----------



## MrDucky

Is there a solution to the _Thread Error Handler_ ?

I run TM5 on stock memory speeds and it crashes with that error. happens on both 1usmus and anta777 configs, also tried lowering testing window size.


----------



## TimeDrapery

97pedro said:


> Hello guys!
> 
> Any idea on how I can improve on this?
> View attachment 2560036
> 
> 
> Any idea on how to lower TRCDRD from 17 to 16? 16 gives me instant errors on testmem5 even at 1.55v


A lot more voltage(s?) will do you good... Think about your XMP profile and consider how the voltage called for by that profile might scale with what you're trying to accomplish

I'm doing yet another go at 4×8GB SR myself, I'll post progress pics as I move through the process... Perhaps they'll help you out


----------



## tommyd2k

heptilion said:


> anyone know whats happening with the ryzen google calculator? Its locked out for me now and request permission. anyone able to share a working copy?


I'll upload a copy and send you a link


----------



## nevartojau

tommyd2k said:


> I'll upload a copy and send you a link


Mind you dropping it for me too?


----------



## tommyd2k

tommyd2k said:


> Here is a copy
> Ryzen Memory Calculator


----------



## tommyd2k

I need another latency test. AIDA64 is giving me crazy results, which isn't uncommon really. But now the latency test keeps giving me 58ns and it's normally 54-55ns. I can't think of any changes I've made so it could be the test. 

Also, I went through the timings on another system I have and It gets unstable if I set the tFAW any lower than 32.







I can't figure out why. It's a different motherboard (Aorus Master). They were in my main system with water cooled spreaders up until a couple months ago and tFAW was stable at 16. I'm gonna check the spreaders and make sure I put them back on good. It's a long shot but maybe??
It's a Tforce Xtreem 4500cl18 kit. I've been using them for a couple years and never had to use a tFAW over 16. I like the Ripjaw 4000CL15's a lot, the Tforce are pretty similar to them, both use higher binned B-die.


----------



## Gegu

Does anyone of you guys have an error list for 1usmus v3 preset for TM5?


----------



## ReyReverse

tommyd2k said:


> I need another latency test. AIDA64 is giving me crazy results, which isn't uncommon really. But now the latency test keeps giving me 58ns and it's normally 54-55ns. I can't think of any changes I've made so it could be the test.
> 
> Also, I went through the timings on another system I have and It gets unstable if I set the tFAW any lower than 32.
> View attachment 2562751
> 
> I can't figure out why. It's a different motherboard (Aorus Master). They were in my main system with water cooled spreaders up until a couple months ago and tFAW was stable at 16. I'm gonna check the spreaders and make sure I put them back on good. It's a long shot but maybe??
> It's a Tforce Xtreem 4500cl18 kit. I've been using them for a couple years and never had to use a tFAW over 16. I like the Ripjaw 4000CL15's a lot, the Tforce are pretty similar to them, both use higher binned B-die.


you don't need to loose your tFAW to 32 if you running GDM enabled. it must be related voltage or primary timings and trfc
you pull it back tFAW to 16. and play with voltage, and maybe vsoc can increase a little bit.


----------



## tommyd2k

I used the test in the memory calculator and confirmed that my main system has lost about 3.5ns of latency for some reason. Not the system with the tFAW question BTW. It's never over 55ns unless I have stuff running. It's 58.5 now and I cannot pinpoint why yet. Check out the timings compared to the other one, pretty close except for GDM off, tFAW and tRCD's. .







edit: I had AI tune installed so I could make VRM changes on the fly. It causes the added latency even if it isn't running. AI tune has always been garbage, I should've known.


----------



## tommyd2k

I don't remember people having trouble running tFAW 16 or tRRDs X4


----------



## ReyReverse

tommyd2k said:


> I don't remember people having trouble running tFAW 16 or tRRDs X4


I believe many pure 1T off user can't do tfaw 16, at least to me yes. 
but I curious, whats make you change your mobo to aorus master. I thought dark hero is better?


----------



## tommyd2k

ReyReverse said:


> you don't need to loose your tFAW to 32 if you running GDM enabled. it must be related voltage or primary timings and trfc
> you pull it back tFAW to 16. and play with voltage, and maybe vsoc can increase a little bit.


I'll turn up the voltage a little more I guess. I set the timings 1 at a time in the Gigabyte bios order. When I got to tRRDs 4 I did try to set tFAW to 16, but when it didn't work I moved on and tigtened everything else. Once it was all tuned I went back to try again and tried 16,20,24,28. It's always 4xtRRDs from what I've always seen. 
If anyone wants to recommend any RTT sets that work for aorus master 2x8GB I could prob shut off GDM.


----------



## tommyd2k

ReyReverse said:


> I believe many pure 1T off user can't do tfaw 16, at least to me yes.
> but I curious, whats make you change your mobo to aorus master. I thought dark hero is better?


Two diff machines. I have a gamer in my living room and one in office. Actually my profile pic shows both machines side by side.
I like the Asus dark hero better myself, the Aorus Master has it's advantages just like the Asus has some. It all depends on preference.


----------



## tommyd2k

If they weren't behind a waterblock I'd pull the ram outta the Dark hero and try them with the Aorus Master and see if tFAW 16 works. I could also see if the Tforce still will run at 16 in the DH. It's a pain to pull the RAM without disconnecting the water lines tho.


----------



## domdtxdissar

Gegu said:


> Does anyone of you guys have an error list for 1usmus v3 preset for TM5?



 TM5 Errors DecypheredSOURCE1usmus_V3Error TypeError DescriptionERROR #0RefreshStable 0MbVoltage cutoff choke, suspect tRRD & tWTR
Nearly always tRRD & tWTR but can also be too low tRP
or tiny bit too low tRC (if user used > -3 on tRC)

Start by adding VDIMM
6x Error 0 = BSOD

2,0,0,0,0 = not enough VDIMM
0,0,0,6,6,6 = too low SCL, bad tWRRD

0 at the start = overvoltage crash
^ also too high CkeDrvStr with too high procODT
(only too high CkeDrvStr results in #6 solo)
0 bellow 5 cycles = too much VDIMMVeii
(updated 01/01/2022)ERROR #1Variable tests 16Mb Can be voltage related, can be tRFC issues,
Tiny timeout issues (tRRD, tWTR),
can also be on the edge of stability CAD_BUS (depends if #6/#4 exist or not)VeiiERROR #2Variable tests 32MbIs a timeout issue, somewhere something ends too quickly
or you lack voltage and cells are not recharged in time,
a sync issue with other words,
which's first culprit is voltage somewhere
or resistance somewhere

^ needs updating and clearer findings - WIP

Comes together with Voltages issues for #3, #4, #5, #8, #10, #14
Meaningless on it's ownVeii
(updated 02/02/2021)ERROR #3MirrorMove 0MbWould suspect more tRDWR/tWRRD
while for bigger dataset-errors before it = tRP, tRFC
start with increasing tWTR_ , for example to 5-14

It can also be too low tRRD_L or too strong RTT_NOMVeii
(updated 23/09/2021)ERROR #4MirrorMove128 0MbPCB Crash !
Too strong RTT values
too high CAD_BUS ClkDrvStr
wrong tCKE
or too high VDIMMVeii
(updated 18/01/2021)ERROR #5MirrorMove 0MbWould suspect more tRDWR/tWRRD
while for bigger datasets tRP, tRFC

- it can error after the 2nd or 3rd pass
if something is off by some ns and just "got lost"

Can be incorrect RTL training, or on AMD too high/low cLDO_VDDP & ClkDrvStr causing tPHYRDL missmatchVeii & Bloax
(updated 08/04/2022)ERROR #6Random tests 1MbIs purely related to the IMC (Can mean voltage is too high) ,
be if procODT, CLDO_VDDP or vSOC
~ it translates to "i couldn't even start transfering data, i crashed"
4-6x error 6 result in full bluescreen
- Error 5 then 6 is a timings missmatch between dimms
(Data mirror move)

0-0-0-6-6-6 (2nd cycle) Can be too low SCL with wrong tWRRD
Single rare 6 (after time), fix RTT values or give it +1 vDIMM

6-6-6 at the very start , too high/low tCKE *
* start with this firstVeii
(updated 01/12/2021)ERROR #7MirrorMove 2MbIt will error out if if CAD_BUS or CAD_BUS SETUP Time is not optimal (lower CkeSetup)
will error out of tRFC is too low,
mostly errors out only after time
Suspect vDIMM to be +/- 1 step too high/low,
tFAW be awkward value, or tRAS needing +1

1-7-7 or 7-1-8-8 (increase CkeDrvStr)Veii
(updated 05/04/2021)ERROR #8Random tests 0Mb =Error #1

1x #8 at the end = badly timed tWTR_
Likely too low tWTR_S

Can also be too high tWTR_L , but first try higher tWTR_SVeii
(updated 23/09/2021)ERROR #9MirrorMove 4Mb Suspect tWR being too slow, voltage stability issue
If you've lowered tRP , increase vDimm a tiny bit
If you've increased tRP to longer delay,
decrease vDIMM +0.01 , one tiny stepVeiiERROR #10Random tests 8MbSuspect tWR being too slow (lower value required)
mostly affects the first 5 main timings
- noticed it can be tRCDWR to RD, can be tRP too,
but it also can be the last two tRDWR & tWRRD
which don't play well with your main tRCDWR/RD

#10 at the very start = increase RTT_NOM to something strongerVeiiERROR #11Random tests 16MbIt is most likely RAM overheating
it will error out if if CAD_BUS is not optimal or SETUP Times are wrong
will error out of tRFC is too low, mostly errors out only after time
Suspect vDIMM to be +/- 1 step too high/low,
tFAW be awkward value, or tRAS needing +1VeiiERROR #12Random tests 32Mb = ERROR #2

If right at the start,
increase procODT once, or make RTT_NOM weaker
Also make CPU 1.8V line weaker

Alternatively - weaken ClkDrvStr & increase VDIMM slightlyVeii
(updated 01/21/2021)ERROR #13Random tests 64MbIt is most likely RAM overheating
timeout while transfering big data
- full crash, nearly always related to too much voltage
~ as memory was not able to autocorrect it

Explosion of #13's,
- try to lower VDIMM or use a stronger RTT_NOM
probably both

Random #13's, still in the first loop:
increase procODTVeii & PJVol
(updated 30/03/2021)ERROR #14MirrorMove 0Mb14 / 4 / 0 - relate to badly used CAD_BUS SETUP Timing
Too low CAD_BUS AddrCmdDrvStr/CsOdtDrvStren/CkeDrvStren
or overal badly timed powerdown

They will appear together, because it's the dimms crashing on badly timed values
0,0,14,0, 9 = too much VDIMMVeii
(updated 01/01/2022)ERROR #15MirrorMove128 0MbCrashed after #15 = End of one Cycle
Timing accuracy related
Can be everything from
(tCWL≠tCL, tRFC, vDIMM, tFAW smaller than tRRD_L, too tight tRRD_)

Can also be an unstable Curve Optimizer core
- verify with y-cruncher first (1-7-0 - 4 loops = 72min)Veii
(added 01/12/2021)


----------



## ReyReverse

tommyd2k said:


> I used the test in the memory calculator and confirmed that my main system has lost about 3.5ns of latency for some reason. Not the system with the tFAW question BTW. It's never over 55ns unless I have stuff running. It's 58.5 now and I cannot pinpoint why yet. Check out the timings compared to the other one, pretty close except for GDM off, tFAW and tRCD's. .
> View attachment 2562761


I only can say your mobo and ram bin is golden chip able to let you run tfaw at 16 on 1T off. lottery silicon I guess. lol
1T off trrds *4 = tfaw 16 is amazing speed. ( if its stable TM5 1usmus and passed OCCT)



tommyd2k said:


> t's never over 55ns unless I have stuff running. It's 58.5 now and I cannot pinpoint why yet.


I know its stupid remind, maybe you can check on your windows startup program and disable it. NZXT, razer, adobe....etc


----------



## turbix

This means I need to increase my RAM voltage?


----------



## Gegu

domdtxdissar said:


> TM5 Errors DecypheredSOURCE1usmus_V3Error TypeError DescriptionERROR #0RefreshStable 0MbVoltage cutoff choke, suspect tRRD & tWTR
> Nearly always tRRD & tWTR but can also be too low tRP
> or tiny bit too low tRC (if user used > -3 on tRC)
> 
> Start by adding VDIMM
> 6x Error 0 = BSOD
> 
> 2,0,0,0,0 = not enough VDIMM
> 0,0,0,6,6,6 = too low SCL, bad tWRRD
> 
> 0 at the start = overvoltage crash
> ^ also too high CkeDrvStr with too high procODT
> (only too high CkeDrvStr results in #6 solo)
> 0 bellow 5 cycles = too much VDIMMVeii
> (updated 01/01/2022)ERROR #1Variable tests 16MbCan be voltage related, can be tRFC issues,
> Tiny timeout issues (tRRD, tWTR),
> can also be on the edge of stability CAD_BUS (depends if #6/#4 exist or not)VeiiERROR #2Variable tests 32MbIs a timeout issue, somewhere something ends too quickly
> or you lack voltage and cells are not recharged in time,
> a sync issue with other words,
> which's first culprit is voltage somewhere
> or resistance somewhere
> 
> ^ needs updating and clearer findings - WIP
> 
> Comes together with Voltages issues for #3, #4, #5, #8, #10, #14
> Meaningless on it's ownVeii
> (updated 02/02/2021)ERROR #3MirrorMove 0MbWould suspect more tRDWR/tWRRD
> while for bigger dataset-errors before it = tRP, tRFC
> start with increasing tWTR_ , for example to 5-14
> 
> It can also be too low tRRD_L or too strong RTT_NOMVeii
> (updated 23/09/2021)ERROR #4MirrorMove128 0MbPCB Crash !
> Too strong RTT values
> too high CAD_BUS ClkDrvStr
> wrong tCKE
> or too high VDIMMVeii
> (updated 18/01/2021)ERROR #5MirrorMove 0MbWould suspect more tRDWR/tWRRD
> while for bigger datasets tRP, tRFC
> 
> - it can error after the 2nd or 3rd pass
> if something is off by some ns and just "got lost"
> 
> Can be incorrect RTL training, or on AMD too high/low cLDO_VDDP & ClkDrvStr causing tPHYRDL missmatchVeii & Bloax
> (updated 08/04/2022)ERROR #6Random tests 1MbIs purely related to the IMC (Can mean voltage is too high) ,
> be if procODT, CLDO_VDDP or vSOC
> ~ it translates to "i couldn't even start transfering data, i crashed"
> 4-6x error 6 result in full bluescreen
> - Error 5 then 6 is a timings missmatch between dimms
> (Data mirror move)
> 
> 0-0-0-6-6-6 (2nd cycle) Can be too low SCL with wrong tWRRD
> Single rare 6 (after time), fix RTT values or give it +1 vDIMM
> 
> 6-6-6 at the very start , too high/low tCKE *
> * start with this firstVeii
> (updated 01/12/2021)ERROR #7MirrorMove 2MbIt will error out if if CAD_BUS or CAD_BUS SETUP Time is not optimal (lower CkeSetup)
> will error out of tRFC is too low,
> mostly errors out only after time
> Suspect vDIMM to be +/- 1 step too high/low,
> tFAW be awkward value, or tRAS needing +1
> 
> 1-7-7 or 7-1-8-8 (increase CkeDrvStr)Veii
> (updated 05/04/2021)ERROR #8Random tests 0Mb=Error #1
> 
> 1x #8 at the end = badly timed tWTR_
> Likely too low tWTR_S
> 
> Can also be too high tWTR_L , but first try higher tWTR_SVeii
> (updated 23/09/2021)ERROR #9MirrorMove 4MbSuspect tWR being too slow, voltage stability issue
> If you've lowered tRP , increase vDimm a tiny bit
> If you've increased tRP to longer delay,
> decrease vDIMM +0.01 , one tiny stepVeiiERROR #10Random tests 8MbSuspect tWR being too slow (lower value required)
> mostly affects the first 5 main timings
> - noticed it can be tRCDWR to RD, can be tRP too,
> but it also can be the last two tRDWR & tWRRD
> which don't play well with your main tRCDWR/RD
> 
> #10 at the very start = increase RTT_NOM to something strongerVeiiERROR #11Random tests 16MbIt is most likely RAM overheating
> it will error out if if CAD_BUS is not optimal or SETUP Times are wrong
> will error out of tRFC is too low, mostly errors out only after time
> Suspect vDIMM to be +/- 1 step too high/low,
> tFAW be awkward value, or tRAS needing +1VeiiERROR #12Random tests 32Mb= ERROR #2
> 
> If right at the start,
> increase procODT once, or make RTT_NOM weaker
> Also make CPU 1.8V line weaker
> 
> Alternatively - weaken ClkDrvStr & increase VDIMM slightlyVeii
> (updated 01/21/2021)ERROR #13Random tests 64MbIt is most likely RAM overheating
> timeout while transfering big data
> - full crash, nearly always related to too much voltage
> ~ as memory was not able to autocorrect it
> 
> Explosion of #13's,
> - try to lower VDIMM or use a stronger RTT_NOM
> probably both
> 
> Random #13's, still in the first loop:
> increase procODTVeii & PJVol
> (updated 30/03/2021)ERROR #14MirrorMove 0Mb14 / 4 / 0 - relate to badly used CAD_BUS SETUP Timing
> Too low CAD_BUS AddrCmdDrvStr/CsOdtDrvStren/CkeDrvStren
> or overal badly timed powerdown
> 
> They will appear together, because it's the dimms crashing on badly timed values
> 0,0,14,0, 9 = too much VDIMMVeii
> (updated 01/01/2022)ERROR #15MirrorMove128 0MbCrashed after #15 = End of one Cycle
> Timing accuracy related
> Can be everything from
> (tCWL≠tCL, tRFC, vDIMM, tFAW smaller than tRRD_L, too tight tRRD_)
> 
> Can also be an unstable Curve Optimizer core
> - verify with y-cruncher first (1-7-0 - 4 loops = 72min)Veii
> (added 01/12/2021)


Thank you so much!


----------



## Baio73

Need some explanation about TM5... I've been testing my new RAM for a couple of weeks, but it seems to me that TM5 ha really weird behaviour.

When I had a 2x8Gb kit every run with 1smus profle took 6-8 minutes, now with a 2x16Gb, after 9 hours it's still running.. I've tried downloading it again but no changes.

But, generally speaking, I start doubting it's a really reliable software, as sometimes I can run it for a couple of hours and get 1 type of error, then close it, launch it again ad get 5-6 kind of different errors in 30 minutes. It seems to me it gives really wavering results if compared to Karhu RAM Test.

Also the advantage of knowing the kind of error (then potentially on which BIOS value one needs to intervene) seems inconsistent if the next run gives errors not shown in the previous one).

If I have time this evening I'm gonna post my results, but what's your thoughts about this?

Baio


----------



## ReyReverse

Baio73 said:


> Need some explanation about TM5... I've been testing my new RAM for a couple of weeks, but it seems to me that TM5 ha really weird behaviour.
> 
> When I had a 2x8Gb kit every run with 1smus profle took 6-8 minutes, now with a 2x16Gb, after 9 hours it's still running.. I've tried downloading it again but no changes.
> 
> But, generally speaking, I start doubting it's a really reliable software, as sometimes I can run it for a couple of hours and get 1 type of error, then close it, launch it again ad get 5-6 kind of different errors in 30 minutes. It seems to me it gives really wavering results if compared to Karhu RAM Test.
> 
> Also the advantage of knowing the kind of error (then potentially on which BIOS value one needs to intervene) seems inconsistent if the next run gives errors not shown in the previous one).
> 
> If I have time this evening I'm gonna post my results, but what's your thoughts about this?
> 
> Baio


wrong setting is it?
you know when I play 2T off, 20 cycles it took me within 50mins.
and pure 1T off , I need about 2 hours to run 20 cycles TM5 1usmus.

I think you should play with your subtimings. mostly problem on trrds/dl & tFAW n trfc
or you can share your zentimings here , maybe some pro can help analyse



and also maybe your windows is collapsed, I reformat everytime for my windows, once my windows detected WHEA ID 19 or bsod . after test I will reinstall windows.


----------



## izallica

Spoiler: 3800















my ram b-die only stable at tFaw 32, extreme1+1500% pbo2 +75Mhz


----------



## Hairy MacChoir

Hello there, i like to add my findings on Whea error 19, it can also be sorted out by increasing the VDDG-CCD.

The common recommendation is keep CCD under 950mv and up the IOD. For those who are unsuccessful with IOD, please try the CCD and keep IOD at default.

and also limit your all core boost clocks via tdc. seems there are 2 issues with pushing fclk, if you are suffering usb drops out, it could mean your IF-to-iod is weak and you add voltage there. If have no usb drop outs, perhaps your IF-to-ccd is weak.

and common issue is weaker a IF needs lower core clocks to synchronize i guess. 

Here is my B2 chip that have a 1900 FCLK hole, and tons of Whea core 0 error at 1933 and above. By setting a conservative ram and then tweaking the VDDG-CCD, i seems to tame the Whea core 0 errors, which i thought its the end for my bin.


----------



## Bloax

ReyReverse said:


> I only can say your mobo and ram bin is golden chip able to let you run tfaw at 16 on 1T off. lottery silicon I guess. lol
> 1T off trrds *4 = tfaw 16 is amazing speed. ( if its stable TM5 1usmus and passed OCCT)



















(mildly doctored image, because I was too lazy to take a screenshot when I found out that WTRL 8 was OK and transferring it onto my network-connected intel machine 🤡 )

Minimizing RRD/WTR/tFAW comes mostly as a result of minimizing procODT impedance, while increasing CPU 1.8v (it's actually memory input voltage, CPU 1P8, many names)
This has been true on every single b-die stick I've tried, which is five different kits by now 🤡

Would be nice if people would donate Micron 16gbit B sticks to me, so I can see what's up with those, but I ain't a beggar.


----------



## ReyReverse

Bloax said:


> View attachment 2563039
> 
> View attachment 2563040
> 
> (mildly doctored image, because I was too lazy to take a screenshot when I found out that WTRL 8 was OK and transferring it onto my network-connected intel machine 🤡 )
> 
> Minimizing RRD/WTR/tFAW comes mostly as a result of minimizing procODT impedance, while increasing CPU 1.8v (it's actually memory input voltage, CPU 1P8, many names)
> This has been true on every single b-die stick I've tried, which is five different kits by now 🤡
> 
> Would be nice if people would donate Micron 16gbit B sticks to me, so I can see what's up with those, but I ain't a beggar.


wow, your dimm temp is so nice. well done. what's your ambient temp?

I can see your Msi b550 unify-x is amazing motherboard. you don't need high vdimm to stable your ram at 1T GDM off.
my b550f is sucks. 3866MHz 1T GDM off CL 15 trfc 139.5ns need 1.545v to stable my 1T off

maybe I can do 1.55v at CL 14 after that. I still waiting the courier send me my crosshair viii dark hero.


----------



## MrHoof

Bloax said:


> View attachment 2563039
> 
> View attachment 2563040
> 
> (mildly doctored image, because I was too lazy to take a screenshot when I found out that WTRL 8 was OK and transferring it onto my network-connected intel machine 🤡 )
> 
> Minimizing RRD/WTR/tFAW comes mostly as a result of minimizing procODT impedance, while increasing CPU 1.8v (it's actually memory input voltage, CPU 1P8, many names)
> This has been true on every single b-die stick I've tried, which is five different kits by now 🤡
> 
> Would be nice if people would donate Micron 16gbit B sticks to me, so I can see what's up with those, but I ain't a beggar.


What is the resaon for those high tRDRDSD/tWRWRSD? I know DD´s dont do anything unless you have 4 sticks in use but those SD´s are little high, should be 4/6 instead of 6/9.


----------



## Bloax

Reason? No reason, just stuck habits (no difference, it works, don't change it)




ReyReverse said:


> wow, your dimm temp is so nice. well done. what's your ambient temp?
> 
> I can see your Msi b550 unify-x is amazing motherboard. you don't need high vdimm to stable your ram at 1T GDM off.
> my b550f is sucks. 3866MHz 1T GDM off CL 15 trfc 139.5ns need 1.545v to stable my 1T off
> 
> maybe I can do 1.55v at CL 14 after that. I still waiting the courier send me my crosshair viii dark hero.



I know boards vary in quacklity, and that Gigglebyte has some extremely questionable AM4 memory performance - but it shouldn't affect voltage requirements, so much as maximum operating frequency or minimum tRCD.
(as well as what RTT Nom/Park you can run, some gigglebyte boards apparently don't like going below 120 ohm Park (/2) ???)








temps are nice because I run a silly airflow config


----------



## Gegu

Guys, for now these settings seems to be rock-stable.
What do you think, is there any room to improve performance of this kit?


----------



## tcclaviger

Gegu said:


> Guys, for now these settings seems to be rock-stable.
> What do you think, is there any room to improve performance of this kit?
> 
> 
> View attachment 2563108


Also on C8E but was unable to find a 32gb 4000C14 kit, giving your timings/voltages, or something very similar a test on my 4000C16 GVKA kit. A few are a bit tighter than I was using previously like tWR.

What do you run vdimm at? Impossible to tell with zentimings on C8E. Guessing at or just over 1.5v?

Any luck with C1 GDM off AddrCmdStr at 0? Can't seem to get it to play nicely at 0 with CR1 and GDM disabled, even down at 3600 MT/s.


----------



## KedarWolf

Gegu said:


> Guys, for now these settings seems to be rock-stable.
> What do you think, is there any room to improve performance of this kit?
> 
> 
> View attachment 2563108


SCLs at 2 will lower AIDA64 read some, but increase write and copy and helps y-cruncher benches. Try tRAS 21, I know it doesn't add up for tRC but I find it don't really matter and helps. I think tRFC2 is supposed to be 178, not 179. Also might want to try tCKE at 9 to get the others stable. I find SDs/DDs at 4-2/6-2 helps a bit.

Edit: Also try TRS and TRL at 3-8.


----------



## Gegu

tcclaviger said:


> Also on C8E but was unable to find a 32gb 4000C14 kit, giving your timings/voltages, or something very similar a test on my 4000C16 GVKA kit. A few are a bit tighter than I was using previously like tWR.
> 
> What do you run vdimm at? Impossible to tell with zentimings on C8E. Guessing at or just over 1.5v?
> 
> Any luck with C1 GDM off AddrCmdStr at 0? Can't seem to get it to play nicely at 0 with CR1 and GDM disabled, even down at 3600 MT/s.


Put the kit name from ZenTimings, then you will find it  
It's not often in stock, but sometimes it is.

My VDIMM now is XMP 1.55V, but I'll be lowering it - was using 1.55 to check tRFC 224. From my previous tests, this kit does not have a problem running 3800 at 1.5V also.
And yeah, there is some Zen Timings bug with few voltage readings.

About Addr - it must be a minimum of 24 in my case, making zero will result in unstable OC.
Not sure about ProcODT, will check also 36.9, but this 40 is also good.


----------



## Gegu

KedarWolf said:


> SCLs at 2 will lower AIDA64 read some, but increase write and copy and helps y-cruncher benches. Try tRAS 21, I know it doesn't add up for tRC but I find it don't really matter and helps. I think tRFC2 is supposed to be 178, not 179. Also might want to try tCKE at 9 to get the others stable. I find SDs/DDs at 4-2/6-2 helps a bit.
> 
> Edit: Also try TRS and TRL at 3-8.


Thanks, I will check it!


----------



## ReyReverse

Bloax said:


> I know boards vary in quacklity, and that Gigglebyte has some extremely questionable AM4 memory performance - but it shouldn't affect voltage requirements, so much as maximum operating frequency or minimum tRCD.











no........its does matter. every motherboard memory signal integrity is different.

in this case 3600MHz CL 14-15-15-35 voltage requirement only need 1.25v

I was consider to get MSI board too, I know some x570 MSI board good at ram OC, reasonable price quite attractive

that's why people say Silicon Lottery on some special case


----------



## tcclaviger

Gegu said:


> Put the kit name from ZenTimings, then you will find it
> It's not often in stock, but sometimes it is.
> 
> My VDIMM now is XMP 1.55V, but I'll be lowering it - was using 1.55 to check tRFC 224. From my previous tests, this kit does not have a problem running 3800 at 1.5V also.
> And yeah, there is some Zen Timings bug with few voltage readings.
> 
> About Addr - it must be a minimum of 24 in my case, making zero will result in unstable OC.
> Not sure about ProcODT, will check also 36.9, but this 40 is also good.


Haven't seen the dual rank 4000C14 on sale in months, from what I've seen for sale it looks like Gskill is winding down Bdie kit variety, and replacing the SKUs with an "A" at the end of new part number or just deprecating them completely.

The timings tested stable with 1.1063 SOC and 1.52vdimm. ProcODT 40 vs 36.9 makes little difference on C8E for me below 1.55vdimm, with 36.9 playing better with voltages over 1.55vdimm.

tRC seems to be where the bin difference is showing most, my kit will not tolerate sub 38 at 3800 or TRFC sub 140nswithout errors.


----------



## freestaler

im at the moment with this settings (3600 Cl16 B-Die DR 2x16GB, X370, 5800x3d, BLCK 104 -> 3740 MHZ Ram IF 1:1). If i go TWR with 1:1 to TCL i god some crash during Memtest. Did you see any Value that i have to change or should that be okay?


----------



## tommyd2k

Going for 3800cl13-13-13. Tried 1.54v and immediately had errors so went to 1.56v and looks ok. Maybe I'll go back and try 1.55v. I think 1.56v should be ok for daily use. They're water-cooled [email protected] Ripjaws. 
Should I dare try 12 next? If the voltage scales evenly then I'd need 1.6-1.62v min, but probably would need more. I don't want to push them too far.


----------



## ReyReverse

tommyd2k said:


> Going for 3800cl13-13-13. Tried 1.54v and immediately had errors so went to 1.56v and looks ok. Maybe I'll go back and try 1.55v. I think 1.56v should be ok for daily use. They're water-cooled [email protected] Ripjaws.
> Should I dare try 12 next? If the voltage scales evenly then I'd need 1.6-1.62v min, but probably would need more. I don't want to push them too far.
> 
> View attachment 2563126


@Bloax see?Pure 1T off 3800 cl 13 trfc at 130ns only need 1.55-1.56v 
Different material built different quality, different Signal integrity.


----------



## tommyd2k

freestaler said:


> im at the moment with this settings (3600 Cl16 B-Die DR 2x16GB, X370, 5800x3d, BLCK 104 -> 3740 MHZ Ram IF 1:1). If i go TWR with 1:1 to TCL i god some crash during Memtest. Did you see any Value that i have to change or should that be okay?
> 
> View attachment 2563123


I see a lot of possibilities there. Have you tried to lower everything or is that just what you know works? I think tRRDL 6-4 maybe, tWR 12-14, tCWL 12, tRTP 6-8, tRDWR-tWRRD 10-1 or 8-3 and tRFC's 234-174-107 or 252-187-115


----------



## MrHoof

Bloax said:


> Reason? No reason, just stuck habits (no difference, it works, don't change it)
> 
> 
> 
> 
> 
> I know boards vary in quacklity, and that Gigglebyte has some extremely questionable AM4 memory performance - but it shouldn't affect voltage requirements, so much as maximum operating frequency or minimum tRCD.
> (as well as what RTT Nom/Park you can run, some gigglebyte boards apparently don't like going below 120 ohm Park (/2) ???)
> View attachment 2563086
> 
> temps are nice because I run a silly airflow config


With DR sticks SD´s make a diffrence.
2x SR= SD&DD dont matter they are not used
2xDR= SD is used
4x SR/4x DR= SD&DD are used both , SD cause DR and DD cause 4 dimms


----------



## Bloax

ReyReverse said:


> @Bloax see?Pure 1T off 3800 cl 13 trfc at 130ns only need 1.55-1.56v
> Different material built different quality, different Signal integrity.


Are you seriously suggesting that Marketing Material has more value than the practical experience of everyone I've seen hopping from board to board?

The primary cause for +/- 30 mV voltage requirements between boards comes down to differences in the DRAM power implementation, where Kindly Asking for 1.58v may result in 1.55v at the DIMM on one board, and 1.60v at the DIMM on another.
Thus one board would have to ask for 1.59v to receive 1.56v, while the other would "only" require asking for 1.54v - whoah, 50 mV saved!!
Except the "real" voltage is exactly the same, so the only difference is what voltage you have to "ask" for.

The biggest difference-maker in Required Operating Voltage is the signal and powering setup (procODT + RTT + CADBus), where properly dialing in the Desired Values of your Board/DIMM combo can have a big impact (-20 to -50 mV) on what Voltage you have to ask for, to get a certain tRCD to function properly. (Possibly, at all, even!)
(beyond these determining your Maximum Operating Frequency and minimum RRD/WTR/tFAW, _as well as genuinely being somewhat board-dependent_, though most boards run the most relevant values)

Well, besides the silicon lottery (the bottom of which, is determined by what Memory Bin you buy) factor, which is the Actual Largest.
The difference between my Viper Steel 4400 19-19-19 sticks and my Viper Steel 4000 16-16-16 sticks running the same 4200 15-15-15, is 60 mV (1.62v [4.4k] vs. 1.56v [4k16])
One curious anecdote, is that this difference grows even larger on my silly z690-a Pro board* in a 4x8 config between Viper 4.4k sticks (bad-slot) + old Ripjaws 3200 14-14-14 sticks (good-slot), versus Viper 4.4k (bad) + Viper 4k16 (good) with a fully slammed procODT (presumably, 24 ohms). The Ripjaws + 4.4k one ran 3800 15-15-15 at 1.46v, whereas the 4k16 + 4.4k one runs 3800 14-14-14 at 1.45v -- each full drop in primary timings being roughly +90 mV -- so -100 mV in total, with -50 mV coming mysteriously from dropping procODT from 28.8 ohms to 24 ohms, the rest from the better DIMMs.

Different DIMM PCBs also tend to have different tRTP/tWR requirements, some have a range of acceptable values - others get very angry if you don't run their Goldilocks Value.
as an example I can use the same two viper 4.4k and 4k sticks, where the 4.4k runs RTP 5/6/7 + tWR 10/12/14, but the (faster) 4k ones only accept RTP 5 + tWR 10 otherwise they throw intermittent errors.

* (on Intel the CADBUS isn't exposed by any tool, and the desired range of values you can set for the drive strengths are non-obvious. It's likely the culprit of -50 mV at the bottomed-out procODT in this 4x8 config, but I have no firm clue. Sad!)


----------



## ReyReverse

Bloax said:


> Are you seriously suggesting that Marketing Material has more value than the practical experience of everyone I've seen hopping from board to board?
> 
> The primary cause for +/- 30 mV voltage requirements between boards comes down to differences in the DRAM power implementation, where Kindly Asking for 1.58v may result in 1.55v at the DIMM on one board, and 1.60v at the DIMM on another.
> Thus one board would have to ask for 1.59v to receive 1.56v, while the other would "only" require asking for 1.54v - whoah, 50 mV saved!!
> Except the "real" voltage is exactly the same, so the only difference is what voltage you have to "ask" for.
> 
> The biggest difference-maker in Required Operating Voltage is the signal and powering setup (procODT + RTT + CADBus), where properly dialing in the Desired Values of your Board/DIMM combo can have a big impact (-20 to -50 mV) on what Voltage you have to ask for, to get a certain tRCD to function properly. (Possibly, at all, even!)
> (beyond these determining your Maximum Operating Frequency and minimum RRD/WTR/tFAW, _as well as genuinely being somewhat board-dependent_, though most boards run the most relevant values)
> 
> Well, besides the silicon lottery (the bottom of which, is determined by what Memory Bin you buy) factor, which is the Actual Largest.
> The difference between my Viper Steel 4400 19-19-19 sticks and my Viper Steel 4000 16-16-16 sticks running the same 4200 15-15-15, is 60 mV (1.62v [4.4k] vs. 1.56v [4k16])
> One curious anecdote, is that this difference grows even larger on my silly z690-a Pro board* in a 4x8 config between Viper 4.4k sticks (bad-slot) + old Ripjaws 3200 14-14-14 sticks (good-slot), versus Viper 4.4k (bad) + Viper 4k16 (good) with a fully slammed procODT (presumably, 24 ohms). The Ripjaws + 4.4k one ran 3800 15-15-15 at 1.46v, whereas the 4k16 + 4.4k one runs 3800 14-14-14 at 1.45v -- each full drop in primary timings being roughly +90 mV -- so -100 mV in total, with -50 mV coming mysteriously from dropping procODT from 28.8 ohms to 24 ohms, the rest from the better DIMMs.
> 
> Different DIMM PCBs also tend to have different tRTP/tWR requirements, some have a range of acceptable values - others get very angry if you don't run their Goldilocks Value.
> as an example I can use the same two viper 4.4k and 4k sticks, where the 4.4k runs RTP 5/6/7 + tWR 10/12/14, but the (faster) 4k ones only accept RTP 5 + tWR 10 otherwise they throw intermittent errors.
> 
> * (on Intel the CADBUS isn't exposed by any tool, and the desired range of values you can set for the drive strengths are non-obvious. It's likely the culprit of -50 mV at the bottomed-out procODT in this 4x8 config, but I have no firm clue. Sad!)


........Didn't expect you do the whole explanation for me. Because theres so many case crosshair viii mobo stable at 4k without losing core performance. That's one of the reason I bought CDH . Another reason is 5950x on b550f it's a waste. 
But anyway thanks for the explanation. I call you expert now


----------



## Baio73

ReyReverse said:


> wrong setting is it?
> you know when I play 2T off, 20 cycles it took me within 50mins.
> and pure 1T off , I need about 2 hours to run 20 cycles TM5 1usmus.


No way here... If I choose 1usmus profile it starts and never stops (I stopped after 10 hours)



> I think you should play with your subtimings. mostly problem on trrds/dl & tFAW n trfc
> or you can share your zentimings here , maybe some pro can help analyse


I had temperature issues, I solved raising all fans to 100% (can tolerate it when testing), so now TM5 and Karhu are 100% error free:



Any tips to improve? Or something greatly wrong?




> and also maybe your windows is collapsed, I reformat everytime for my windows, once my windows detected WHEA ID 19 or bsod . after test I will reinstall windows.


Well, it may be...it's been a long time since I last installed Windows, but onestly have no time to do that now...

Baio


----------



## ReyReverse

Baio73 said:


> No way here... If I choose 1usmus profile it starts and never stops (I stopped after 10 hours)


lmao
just reformat your windows.


----------



## KedarWolf

ReyReverse said:


> wrong setting is it?
> you know when I play 2T off, 20 cycles it took me within 50mins.
> and pure 1T off , I need about 2 hours to run 20 cycles TM5 1usmus.
> 
> I think you should play with your subtimings. mostly problem on trrds/dl & tFAW n trfc
> or you can share your zentimings here , maybe some pro can help analyse
> 
> 
> 
> and also maybe your windows is collapsed, I reformat everytime for my windows, once my windows detected WHEA ID 19 or bsod . after test I will reinstall windows.


You need to use the Macrium Reflect Free, make a boot USB with the program, back up your entire Windows drive boot partitions and all to a secondary drive and restore the image after BSODs. Takes a few minutes to restore an image, better than reinstalling Windows.


----------



## ioannis91

Why is the last thread falling so far behind? Is this normal?


----------



## ManniX-ITA

Baio73 said:


> No way here... If I choose 1usmus profile it starts and never stops (I stopped after 10 hours)


Usually either is the system unstable (but you can usually notice it having sporadic issues with something else) or there's an issue with memory allocation.
I guess you checked already that it's running with admin privileges (it does say it).
Most common issue is virtual memory, especially going from 16 to 32 GB; check it's enabled, configure it pretty big with a manual static dimension (best if same min and max but costly on the swap disk).
Otherwise try this, sometimes is needed:









Enable the Lock Pages in Memory Option (Windows) - SQL Server


Learn how to turn on the Lock Pages in Memory option. See how it can boost performance by keeping data in physical memory instead of paging it to disk.



docs.microsoft.com







Hairy MacChoir said:


> Here is my B2 chip that have a 1900 FCLK hole, and tons of Whea core 0 error at 1933 and above. By setting a conservative ram and then tweaking the VDDG-CCD, i seems to tame the Whea core 0 errors, which i thought its the end for my bin.


Setting conservative memory timings kinda defeats the reason to go over 1900.
You'll never use that added bandwidth other than for a very slight latency advantage.
That's probably the main reason you don't get WHEA.
I'd say it's better to run at 1900 with tighter timings.


----------



## tcclaviger

tommyd2k said:


> Going for 3800cl13-13-13. Tried 1.54v and immediately had errors so went to 1.56v and looks ok. Maybe I'll go back and try 1.55v. I think 1.56v should be ok for daily use. They're water-cooled [email protected] Ripjaws.
> Should I dare try 12 next? If the voltage scales evenly then I'd need 1.6-1.62v min, but probably would need more. I don't want to push them too far.
> 
> View attachment 2563126


There are 1.6v docp profiles from Gskill. 1.56 is perfectly safe for water-cooled bdie.


----------



## koala7

need help to make this stable
ran tm5 with 1usmus profile 100x got 2 errors
error 3 and 14


----------



## Bloax

koala7 said:


> error 3 and 14
> View attachment 2563219


#3 is likely a red herring from tWR 10 instead of 16 (RTP * 2)
Not running tRAS 29 (tCL + tRCDRD) & tRC 43 (29 + tRP) may also be hiding some things.
Expected tRFC for tRC 43 is 258-192-118, by the way (tRFC: tRC * 6, tRFC/1.346, tRFC/2.1875)
(the * 6 multiplier can be increased for better heat tolerance)

#14 is probably from CsOdtDrvStr wanting to be 24, 30, or 40 [usually lower on Zen2 than Zen3]

I would also not be surprised if you'd need tCKE 9 (7 at 1800 MCLK, +2 every multiple of 100), as this much isn't even different between Zen3 vs. Alder Lake
👋🤡

lowering VDDP and procODT to 30 or 28.2 may be beneficial in some way, may do nothing, may not work


----------



## Saiger0

I just got my 5800X3D (PGS batch) so I want to give it as much voltage headroom as possible while running a decent ram speed. I think 3600cl16 CR2 is a good middleground for now.

What do oyu guys think is the lowest VSOC I can go? I was about to try this next but Ißm not sure about the stepping:
vsoc: 0.975
vddp: 0.85
vddg (both). 0.9


----------



## Taraquin

Saiger0 said:


> I just got my 5800X3D (PGS batch) so I want to give it as much voltage headroom as possible while running a decent ram speed. I think 3600cl16 CR2 is a good middleground for now.
> 
> What do oyu guys think is the lowest VSOC I can go? I was about to try this next but Ißm not sure about the stepping:
> vsoc: 0.975
> vddp: 0.85
> vddg (both). 0.9
> 
> View attachment 2563223


On my setup 2000fclk needs 1.12v SOC, 1.04v IOD and 1900fclk needs 1.07v SOC and 0.99v IOD for max performance, VDDP and CCD works fine at 800-850mv. I would try lowering soc until you get worse latency in aida or instability. Also check if higher SOC can improve performance. You should be sub 60ns even at 3600 with the relative good timings you have.


----------



## ioannis91

How do you optimize SOC and VDDG, VDDP Voltages?


----------



## LtMatt

Taraquin said:


> On my setup 2000fclk needs 1.12v SOC, 1.04v IOD and 1900fclk needs 1.07v SOC and 0.99v IOD for max performance, VDDP and CCD works fine at 800-850mv. I would try lowering soc until you get worse latency in aida or instability. Also check if higher SOC can improve performance. You should be sub 60ns even at 3600 with the relative good timings you have.


Is there a specific error or instability symptom you get in TM5 or your system when the SOC is too low out of interest?


----------



## Hairy MacChoir

ManniX-ITA said:


> Setting conservative memory timings kinda defeats the reason to go over 1900.
> You'll never use that added bandwidth other than for a very slight latency advantage.
> That's probably the main reason you don't get WHEA.
> I'd say it's better to run at 1900 with tighter timings.


Sadly 1900 is a no-post for this bin.
Thats why i pushed for 1933, it is still a bit more bandwidth than 1900 or 1866 in general timings.


----------



## Baio73

ReyReverse said:


> lmao
> just reformat your windows.


Why laugh?
Obviously it’s not the Windows reinstallation time, but all the hours I need to install and configure all the software I use.
And I highly doubt it’s a Windows problem, it seems TM5 runs standalone and does not install anything on SSD or registry.

Baio


----------



## Baio73

ManniX-ITA said:


> Usually either is the system unstable (but you can usually notice it having sporadic issues with something else) or there's an issue with memory allocation.
> I guess you checked already that it's running with admin privileges (it does say it).
> Most common issue is virtual memory, especially going from 16 to 32 GB; check it's enabled, configure it pretty big with a manual static dimension (best if same min and max but costly on the swap disk).
> Otherwise try this, sometimes is needed:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Enable the Lock Pages in Memory Option (Windows) - SQL Server
> 
> 
> Learn how to turn on the Lock Pages in Memory option. See how it can boost performance by keeping data in physical memory instead of paging it to disk.
> 
> 
> 
> docs.microsoft.com


I don’t have any BSOD or locks in my system on basic use, and TM5 is running as admin.
What swap file dimensions do you suggest for a 32Gb system?
I checked and it’s active, 8Gb max dimension ATM.

Baio


----------



## Saiger0

Taraquin said:


> On my setup 2000fclk needs 1.12v SOC, 1.04v IOD and 1900fclk needs 1.07v SOC and 0.99v IOD for max performance, VDDP and CCD works fine at 800-850mv. I would try lowering soc until you get worse latency in aida or instability. Also check if higher SOC can improve performance. You should be sub 60ns even at 3600 with the relative good timings you have.


Thank you for your input. After testing between 1.0 and 1.1vsoc i cant seem to get under 60ns. Closest i get is 60.7.


----------



## ManniX-ITA

Hairy MacChoir said:


> Sadly 1900 is a no-post for this bin.
> Thats why i pushed for 1933, it is still a bit more bandwidth than 1900 or 1866 in general timings.


Ah, missed that. Then it could make sense, 66 MHz are enough to make it worthwhile even with relaxed timings.



Baio73 said:


> I don’t have any BSOD or licks on my system on basic use, and TM5 is running as admin.
> What swap file dimensions do you suggest for a 32Gb system?
> I checked and it’s active, 8Gb max dimension ATM.


IMO at least 24GB to be on the safe side.
Better to set a fixed size, Windows changing it dynamically will cause a lot of fragmentation.
It does have an impact also on a fast SSD.

8 GB should be enough but don't know...
You don't have the Riot Vanguard anti-cheat running right?
There was something else that could mess up TM5, but I can't recall...


----------



## ReyReverse

Bloax said:


> Are you seriously suggesting that Marketing Material has more value than the practical experience of everyone I've seen hopping from board to board?
> 
> The primary cause for +/- 30 mV voltage requirements between boards comes down to differences in the DRAM power implementation, where Kindly Asking for 1.58v may result in 1.55v at the DIMM on one board, and 1.60v at the DIMM on another.
> Thus one board would have to ask for 1.59v to receive 1.56v, while the other would "only" require asking for 1.54v - whoah, 50 mV saved!!
> Except the "real" voltage is exactly the same, so the only difference is what voltage you have to "ask" for.
> 
> The biggest difference-maker in Required Operating Voltage is the signal and powering setup (procODT + RTT + CADBus), where properly dialing in the Desired Values of your Board/DIMM combo can have a big impact (-20 to -50 mV) on what Voltage you have to ask for, to get a certain tRCD to function properly. (Possibly, at all, even!)
> (beyond these determining your Maximum Operating Frequency and minimum RRD/WTR/tFAW, _as well as genuinely being somewhat board-dependent_, though most boards run the most relevant values)
> 
> Well, besides the silicon lottery (the bottom of which, is determined by what Memory Bin you buy) factor, which is the Actual Largest.
> The difference between my Viper Steel 4400 19-19-19 sticks and my Viper Steel 4000 16-16-16 sticks running the same 4200 15-15-15, is 60 mV (1.62v [4.4k] vs. 1.56v [4k16])
> One curious anecdote, is that this difference grows even larger on my silly z690-a Pro board* in a 4x8 config between Viper 4.4k sticks (bad-slot) + old Ripjaws 3200 14-14-14 sticks (good-slot), versus Viper 4.4k (bad) + Viper 4k16 (good) with a fully slammed procODT (presumably, 24 ohms). The Ripjaws + 4.4k one ran 3800 15-15-15 at 1.46v, whereas the 4k16 + 4.4k one runs 3800 14-14-14 at 1.45v -- each full drop in primary timings being roughly +90 mV -- so -100 mV in total, with -50 mV coming mysteriously from dropping procODT from 28.8 ohms to 24 ohms, the rest from the better DIMMs.
> 
> Different DIMM PCBs also tend to have different tRTP/tWR requirements, some have a range of acceptable values - others get very angry if you don't run their Goldilocks Value.
> as an example I can use the same two viper 4.4k and 4k sticks, where the 4.4k runs RTP 5/6/7 + tWR 10/12/14, but the (faster) 4k ones only accept RTP 5 + tWR 10 otherwise they throw intermittent errors.
> 
> * (on Intel the CADBUS isn't exposed by any tool, and the desired range of values you can set for the drive strengths are non-obvious. It's likely the culprit of -50 mV at the bottomed-out procODT in this 4x8 config, but I have no firm clue. Sad!)


this is very useful information, should put it on Ryzen Google Calculator main page.


----------



## Taraquin

Saiger0 said:


> Thank you for your input. After testing between 1.0 and 1.1vsoc i cant seem to get under 60ns. Closest i get is 60.7.


Find the lowest voltage that dies not increase latency  


LtMatt said:


> Is there a specific error or instability symptom you get in TM5 or your system when the SOC is too low out of interest?


Haven't noticed in TM5, just get worse latency/performance.


----------



## LtMatt

VDIMM 1.560v

















Tomorrow I start dialling back voltages, VDIMM and SOC and then IOD.

VDDP needed a bump to 0.955 otherwise one of my DIMMS shows 28 tPHYRDL.


----------



## ReyReverse

@Bloax I considering to get some raw samsung bin to play OC, PC4-25600 3200MHz 1.2V CL 22
I want to know 2Rx8 (2 sticks =32 GB) and 1Rx16 (if I go 2 sticks=32GB will it work?) if it worked, which is better to play OC? SR or DR? of course I will apply thermal pad and put copper heatsink on


----------



## Taraquin

ReyReverse said:


> View attachment 2563297
> 
> 
> @Bloax I considering to get some raw samsung bin to play OC, PC4-25600 3200MHz 1.2V CL 22
> I want to know 2Rx8 (2 sticks =32 GB) and 1Rx16 (if I go 2 sticks=32GB will it work?) if it worked, which is better to play OC? SR or DR? of course I will apply thermal pad and put copper heatsink on


Do you know if this is B-die? It could be some other Samsung like C-die, D-die or E-die which all are crap compared to B-die.


----------



## ReyReverse

Taraquin said:


> Do you know if this is B-die? It could be some other Samsung like C-die, D-die or E-die which all are crap compared to B-die.


I just confirmed with the supplier , only PC4-21300 2666MHz CL 19 1.2v & 19200 is 2400MHz CL 17 1.2v ramspeed
is B die. the rest is A/C/D/E/R

but 2666MHz is extinct, only left 64GB for server use. so 2400MHz CL 17 1.2v USD $ 320 for 2x16GB


----------



## ioannis91

What's the deal exactly with DvrStr? I've read in forums and even BZ says on some of his videos that 24s are the default. I left them on auto and my motherboard defaults to 20s (with 3200c14 XMP though it sets 24s). Is there any particular benefit in using all 24s? As it stands now it passes all stress tests with 20s..


----------



## Bloax

ReyReverse said:


> View attachment 2563297
> 
> 
> @Bloax I considering to get some raw samsung bin to play OC, PC4-25600 3200MHz 1.2V CL 22
> I want to know 2Rx8 (2 sticks =32 GB) and 1Rx16 (if I go 2 sticks=32GB will it work?) if it worked, which is better to play OC? SR or DR? of course I will apply thermal pad and put copper heatsink on


If you want to play Silicon Roulette, then I wouldn't recommend going past 1 Rank x 8 Gb, as you don't get a fancy PCB, and the performance ceiling of a stick will depend on the weakest chip on the DIMM.

It's bad enough when there are 8 chips and a single bad one drags the entire DIMM down - but a complete lottery when it is one out of sixteen for 2 Ranks x 8 Gb.

personally then I prefer gambling on people raising their life quality than memeory but I won't stop you


----------



## ManniX-ITA

ReyReverse said:


> but 2666MHz is extinct, only left 64GB for server use. so 2400MHz CL 17 1.2v USD $ 320 for 2x16GB


Looks expensive...
Why not trying with the very cheap HP B-die kits?









HP V10 RGB DDR4 RAM 16GB (8GBx2) Gaming RAM 3200MHz PC4-25600 CL14 Computer Memoria Stick for Desktop PC - 48U41AA#ABC - Newegg.com


Buy HP V10 RGB DDR4 RAM 16GB (8GBx2) Gaming RAM 3200MHz PC4-25600 CL14 Computer Memoria Stick for Desktop PC - 48U41AA#ABC with fast shipping and top-rated customer service. Once you know, you Newegg!




www.newegg.com


----------



## CrustyJuggler

I followed the OC guide put together by @Taraquin and was able to get my Micron E-Die 2x8GB BallistiX PC3600 sticks up to 3800. They are rock stable for over a month now.

A guide to ram overclocking on Zen 3


----------



## Taraquin

CrustyJuggler said:


> I followed the OC guide put together by @Taraquin and was able to get my Micron E-Die 2x8GB BallistiX PC3600 sticks up to 3800. They are rock stable for over a month now.
> 
> A guide to ram overclocking on Zen 3
> 
> View attachment 2563317


Good result, better than the rev Es I have on my Alder lake. They need RCDRD 20 and RC 58 on 3800, but perform identical to yours on other timings


----------



## CrustyJuggler

Taraquin said:


> Good result, better than the rev Es I have on my Alder lake. They need RCDRD 20 and RC 58 on 3800, but perform identical to yours on other timings


I got lucky with this RAM. I didn't buy it to OC at all. That itch came later. 🤘🤘


----------



## Taraquin

CrustyJuggler said:


> I got lucky with this RAM. I didn't buy it to OC at all. That itch came later. 🤘🤘


Mine is 3000cl15 16 16, so 3800cl15-20-12 ain't that bad


----------



## TimeDrapery

Alright... Stupid ****ing 4×8GB setup is pissing me off so badly

I've gotten it 20000% Karhu, TM5, OCCT Memory test stable at 3200MT/s with 1T command rate and GDM disabled and I'll move from that baseline to see what the issue is running higher memory speeds that makes this so difficult...


----------



## Taraquin

TimeDrapery said:


> Alright... Stupid ****ing 4×8GB setup is pissing me off so badly
> 
> I've gotten it 20000% Karhu, TM5, OCCT Memory test stable at 3200MT/s with 1T command rate and GDM disabled and I'll move from that baseline to see what the issue is running higher memory speeds that makes this so difficult...


At what speed do you run into problems?


----------



## The_King

Taraquin said:


> Mine is 3000cl15 16 16, so 3800cl15-20-12 ain't that bad


WIth REV.E what IC is used matters. The kit that @CrustyJuggler has should be C9BLM if its the same has mines.
A 3000 CL15 Kit will not have the same IC and should not perform the same even though both are REV.E

I believe the Crucial 3600 CL16 White kits with the C9BLM were made in limited quantities. So if you can get one then you are lucky,
has those IC are the same ones found in the Crucial Ballistix MAX 4400 8GB kits.

Here what I got with mine on a 1700X, easy to get GMD off 1T stabile with these kits.


----------



## Taraquin

The_King said:


> WIth REV.E what IC is used matters. The kit that @CrustyJuggler has should be C9BLM if its the same has mines.
> A 3000 CL15 Kit will not have the same IC and should not perform the same even though both are REV.E
> 
> I believe the Crucial 3600 CL16 White kits with the C9BLM were made in limited quantities. So if you can get one then you are lucky,
> has those IC are the same ones found in the Crucial Ballistix MAX 4400 8GB kits.
> 
> Here what I got with mine on a 1700X, easy to get GMD off 1T stabile with these kits.
> 
> View attachment 2563376


Yeah, and there can be quite big variance among kits. One kit I had did 522 RFC at 3733, while another neeeds 552, both 3000cl15. 3600cl16 is a much better bin also


----------



## Audioboxer

Apart from costs, this is why I'll be waiting a bit longer to get involved in this generation.


----------



## CrustyJuggler

The_King said:


> WIth REV.E what IC is used matters. The kit that @CrustyJuggler has should be C9BLM if its the same has mines.
> A 3000 CL15 Kit will not have the same IC and should not perform the same even though both are REV.E
> 
> I believe the Crucial 3600 CL16 White kits with the C9BLM were made in limited quantities. So if you can get one then you are lucky,
> has those IC are the same ones found in the Crucial Ballistix MAX 4400 8GB kits.
> 
> Here what I got with mine on a 1700X, easy to get GMD off 1T stabile with these kits.
> 
> View attachment 2563376


I do indeed have the white C9BLM kits.


----------



## ReyReverse

ManniX-ITA said:


> Looks expensive...
> Why not trying with the very cheap HP B-die kits?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> HP V10 RGB DDR4 RAM 16GB (8GBx2) Gaming RAM 3200MHz PC4-25600 CL14 Computer Memoria Stick for Desktop PC - 48U41AA#ABC - Newegg.com
> 
> 
> Buy HP V10 RGB DDR4 RAM 16GB (8GBx2) Gaming RAM 3200MHz PC4-25600 CL14 Computer Memoria Stick for Desktop PC - 48U41AA#ABC with fast shipping and top-rated customer service. Once you know, you Newegg!
> 
> 
> 
> 
> www.newegg.com


I don't know if that is real samsung b-die 
I need part no. to check


----------



## ManniX-ITA

ReyReverse said:


> I don't know if that is real samsung b-die
> I need part no. to check


It's in the item description 









[Übersicht] - Die ultimative HARDWARELUXX Samsung 8Gb B-Die Liste - alle Hersteller (24.10.22)


Die ultimative HARDWARELUXX Samsung 8Gbit B-Die Liste Inhaltsverzeichnis / Table of Contents » 8GB Module & 2x8GB/4x8GB/8x8GB Kits (SS, SR) » 16GB Module & 2x16GB/4x16GB/8x16GB Kits (DS, DR) » 32GB Module & 2x32GB Kits (DC DIMM) » SO-DIMM 8GB/16GB Varianten (SR/DR) » Häufig gestellte Fragen...




www.hardwareluxx.de


----------



## ReyReverse

ManniX-ITA said:


> It's in the item description
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Übersicht] - Die ultimative HARDWARELUXX Samsung 8Gb B-Die Liste - alle Hersteller (24.10.22)
> 
> 
> Die ultimative HARDWARELUXX Samsung 8Gbit B-Die Liste Inhaltsverzeichnis / Table of Contents » 8GB Module & 2x8GB/4x8GB/8x8GB Kits (SS, SR) » 16GB Module & 2x16GB/4x16GB/8x16GB Kits (DS, DR) » 32GB Module & 2x32GB Kits (DC DIMM) » SO-DIMM 8GB/16GB Varianten (SR/DR) » Häufig gestellte Fragen...
> 
> 
> 
> 
> www.hardwareluxx.de


Its 2133, meant that is PC4-17900 CL 15 1.2v
same like my present one. I looking atleast PC4-19200 or PC4-21300


----------



## ManniX-ITA

ReyReverse said:


> Its 2133, meant that is PC4-17900 CL 15 1.2v
> same like my present one. I looking atleast PC4-19200 or PC4-21300


You have to check the XMP profile, they are either 3200 or 3600... or am I missing something?


----------



## ReyReverse

ManniX-ITA said:


> You have to check the XMP profile, they are either 3200 or 3600... or am I missing something?


you don't get me. 
bro, its okay
anyway that Hardwareluxx website is good.


----------



## CrustyJuggler

ReyReverse said:


> I don't know if that is real samsung b-die
> I need part no. to check


According to b-die finder, the V10 are B-Die


----------



## TimeDrapery

Taraquin said:


> At what speed do you run into problems?


I've run into issues with attaining stability at (and past) 3733MT/s in the past...

I was able to hit 25K% in Karhu RAM Test and a good, no errors, run in TM5 (anta777 "Extreme1") with GDM enabled and loose-ish timing parameters


















If I can smash tighter-ish timing parameters then perhaps I'll be able to bump it up and see if the limitation is the 3800MT/s memory speed or something else that I'm ****ing up...


----------



## TimeDrapery

Here's my most recent iteration of testing using Karhu RAM Test... Still running time now


----------



## rissie

ManniX-ITA said:


> You have to check the XMP profile, they are either 3200 or 3600... or am I missing something?


Think he's talking about speed grade... not sure why bother with that. It's not really a good indication of final binning.


----------



## ManniX-ITA

rissie said:


> Think he's talking about speed grade... not sure why bother with that. It's not really a good indication of final binning.


It's all B-die indeed, what matters is the price and PCB quality 
Can't really associate HP to this kind of products in my mind but the price seems more than fair.
Good enough to order a bunch of kits to attempt binning.


----------



## ReyReverse

The reason why:-

2133 CAS 15 OC ramspeed around 3800MHz can drop to CL 14 , able to do at CL 13 if run at sweetspot (3733 MHz CL 13 trfc around 140ns) need at least 1.6vdimm " to boot" into Windows. If you want to stable at CL 13 , probably need 1.65v and above. Or you can loose trfc to 350ns - 450ns remain at 1.6v . 
(This is my daily run at 3866MHz CL15, pure 1T disabled.)

B die 2400 CL17 , yet test, I don't know
But I believe able to do 4k ramspeed at CL 15 or 16 with some reasonable vdimm.

So b die 2666 CL 19, CAS probably can do 16,17,18
I believe this design for 4000-4266MHz dimm .


Or maybe it's just my Mobo sucks. (B550-f, 5950x)

I will run the test on C8DH again soon

(Above all the test run on Agesa version 1203c 1T GDM disable 0-0-0)


----------



## Taraquin

TimeDrapery said:


> I've run into issues with attaining stability at (and past) 3733MT/s in the past...
> 
> I was able to hit 25K% in Karhu RAM Test and a good, no errors, run in TM5 (anta777 "Extreme1") with GDM enabled and loose-ish timing parameters
> 
> View attachment 2563441
> 
> View attachment 2563440
> 
> 
> If I can smash tighter-ish timing parameters then perhaps I'll be able to bump it up and see if the limitation is the 3800MT/s memory speed or something else that I'm ****ing up...


Gdm on makes diagnostics a bit harder.


----------



## The_King

ManniX-ITA said:


> It's all B-die indeed, what matters is the price and PCB quality
> Can't really associate HP to this kind of products in my mind but the price seems more than fair.
> Good enough to order a bunch of kits to attempt binning.


Those Hp Kits are not cheap @ $119 if you want to get cheap B-Die that performs great with low latency then buy these.

$99 sometimes $89 with $10 rebate is available








Patriot Viper Steel DDR4 16GB (2 x 8GB) 4000MHz CL 16-16-16-36 UDIMM Low-Latency Gaming Memory Kits - PVS416G400C6K at Amazon.com


Buy Patriot Viper Steel DDR4 16GB (2 x 8GB) 4000MHz CL 16-16-16-36 UDIMM Low-Latency Gaming Memory Kits - PVS416G400C6K: Memory - Amazon.com ✓ FREE DELIVERY possible on eligible purchases



www.amazon.com


----------



## ManniX-ITA

The_King said:


> Those Hp Kits are not cheap @ $119 if you want to get cheap B-Die that performs great with low latency then buy these.


Yeah you are right these are much better.
But also not available 
There's a big shortage of cheap DDR4 B-die and those HP seems to be widely available (although with a price premium to pay).
I didn't look so hard but still much better than over 300$ for a 2x16GB kit


----------



## The_King

ManniX-ITA said:


> Yeah you are right these are much better.
> But also not available
> There's a big shortage of cheap DDR4 B-die and those HP seems to be widely available (although with a price premium to pay).
> I didn't look so hard but still much better than over 300$ for a 2x16GB kit


If you cant get the 4000 CL16 then look for the Patriot Viper Steel 4400 C19s. They are usually much easier to find and around $100.

I have the same kit and 3800 CL14 is not a problem


----------



## ManniX-ITA

The_King said:


> If you cant get the 4000 CL16 then look for the Patriot Viper Steel 4400 C19s. They are usually much easier to find and around $100


Almost bought one a while ago to toy with it, there was an offer on Amazon Italy.
But I don't have time right now and I've spent already too much on DDR4...
Next top money will go for some good DDR5 kit...


----------



## The_King

ManniX-ITA said:


> Almost bought one a while ago to toy with it, there was an offer on Amazon Italy.
> But I don't have time right now and I've spent already too much on DDR4...
> Next top money will go for some good DDR5 kit...


I just bought a ton of Crucial Ballistix MAX DDR4 kits. I should also take that advice and stop spending on DDR4 kits.


----------



## ReyReverse

Yea, samsung b die 2133 price is very cheap.it allow you to play cl 14,15 at 3800MHz

Like what I said above. B die 2400 & 2666 (default ram speed) is extinct. You can't find em on market place. I know there's some " used " kit on the market. But I won't buy it.


----------



## The_King

ReyReverse said:


> Yea, samsung b die 2133 price is very cheap.it allow you to play cl 14,15 at 3800MHz
> 
> Like what I said above. B die 2400 & 2666 (default ram speed) is extinct. You can't find em on market place. I know there's some " used " kit on the market. But I won't buy it.





https://assets.website-files.com/5cdb2ee0b102f96c3906500f/6169bb10fc9a02754f687af8_PVS416G360C4K_Sku%20Sheet_100621.pdf



SPECIFICATIONS:
• Capacity: 16GB (2 x 8GB)
• Base Frequency: PC4-21300 (2666MHz)
• Base Timings: 19-19-19-43
• Tested Frequency Profile 1: PC4-28800 (3600MHz)
• Tested Timings: 14-16-16-36
• Tested Voltage for Profile 1: 1.45V
• Format: NON-ECC Unbuffered DIMM

Can be bought here @ $97 (17 in stock)








Patriot Viper Steel DDR4 16GB (2 x 8GB) 3600MHz CL 14-16-16-36 UDIMM Low-Latency Gaming Memory Kits - PVS416G360C4K at Amazon.com


Buy Patriot Viper Steel DDR4 16GB (2 x 8GB) 3600MHz CL 14-16-16-36 UDIMM Low-Latency Gaming Memory Kits - PVS416G360C4K: Memory - Amazon.com ✓ FREE DELIVERY possible on eligible purchases



www.amazon.com





This might also be B-Die

Memory Type DDR4
Memory Size 32GB (2 x 16GB)
Tested Latency 14-16-16-31
Tested Voltage 1.2V
Tested Speed 2400









Corsair Vengeance LPX 32GB (2x16GB) DDR4 DRAM 2400MHz (PC4-19200) C14 Memory Kit - Black (CMK32GX4M2A2400C14) at Amazon.com


Buy Corsair Vengeance LPX 32GB (2x16GB) DDR4 DRAM 2400MHz (PC4-19200) C14 Memory Kit - Black (CMK32GX4M2A2400C14): Memory - Amazon.com ✓ FREE DELIVERY possible on eligible purchases



www.amazon.com


----------



## TimeDrapery

Well, VDIMM bumped to 1.510V proved too high and 1.490V appears to be the ticket for these tickers... although I do suppose we'll have to wait another 16000% and see!


----------



## TimeDrapery

Taraquin said:


> Gdm on makes diagnostics a bit harder.


I suppose so... I've been working these DIMMs for some time now, so I guess I'm looking to see if there's any way around the system instability that I find so prevalent at or above 3800MT/s... even if that means not running 3800MT/s in order to run 32GB of RAM with some semblance of stability present...

I'm also always open to the possibility that my 5800X's memory controller simply isn't up to the task of running 4x8GB DIMMs as I'd like it to or that my mobo's simply wack with regards to memory OC as so many seem to be these days what with the topology-of-choice and all...

Here we are at over 10000% with Karhu RAM Test... I'll let it keep on keeping on for a while longer... it's finals week


----------



## ReyReverse

I believe some brand or marketing state their product are PC4-28800,
the passed few days I've done all the research on Samsung Official website.
there's no such thing in Samsung call PC4-28800 and
and there's no single PC4-25600 bins is Samsung B-die

I sincerely thanks for the help, but don't send Amazon / Newegg link to me already
in general, information from the seller is inaccurate description. 

my purpose is spend a little money get a real b-die 2666 bins to play OC
but Samsung speed bins between 2133 & 2666 the price is almost double.

thats why look expensive for this, but you have no idea this is 2666 bins
and one last thing to understand, not all the 2666 bins is b-die.


----------



## ManniX-ITA

ReyReverse said:


> my purpose is spend a little money get a real b-die 2666 bins to play OC
> but Samsung speed bins between 2133 & 2666 the price is almost double.
> 
> thats why look expensive for this, but you have no idea this is 2666 bins
> and one last thing to understand, not all the 2666 bins is b-die.


Sorry I may be ignorant here 
I don't get it, why are you looking for the 2666 bins?
Have they been reported by someone as better with OC?
My 4000C14 kit is 2133 and also the even more expensive Royal kit I bought and sent back was 2133.

In my understanding Samsung validation is focused on reliability which doesn't mean it's for sure a better OC.
The DIMM manufacturers are validating them, usually, at least for 3200C16 which is much more stressful.
The price premium you pay to Samsung is for their time testing it at 2400 and 2666 as well.
Which it doesn't really matter...

The only P/N that maybe it's worth look for is the BIPB which is validated with industrial temperature limits.


----------



## TimeDrapery

Aha, much gooder Mr. Memory... Much gooder


----------



## TimeDrapery

Dropped tRFC, tRTP, and tWR... Upped VDIMM from 1.490V to 1.510V to compensate for the reduced timing parameters and correct for the error during the running of Karhu RAM Test that I encountered during the first iteration of stability testing...

🎼Here we go again🎼


----------



## The_King

TimeDrapery said:


> Dropped tRFC, tRTP, and tWR... Upped VDIMM from 1.490V to 1.510V to compensate for the reduced timing parameters and correct for the error during the running of Karhu RAM Test that I encountered during the first iteration of stability testing...
> 
> 🎼Here we go again🎼


Have you tried 3800 with GDM off 2T?


----------



## ioannis91

I have implemented active cooling over the ram now so I can go up to 1.5v without overheating. What do you guys think I should try improving? Going flat 15s maybe?


----------



## The_King

ioannis91 said:


> View attachment 2563569
> 
> I have implemented active cooling over the ram now so I can go up to 1.5v without overheating. What do you guys think I should try improving? Going flat 15s maybe?


Does this pass TM5 1usmus or anta777 without errors?

Getting GMD OFF 1T with those *DrvStr 20's it not something you commonly see. Usually it takes *DrvStr like these 60 20 30 20 or 40 20 24 20 etc to pass TM5.


----------



## ioannis91

The_King said:


> Does this pass TM5 1usmus or anta777 without errros?
> 
> Getting GMD OFF 1T with those *DrvStr 20's it not something you commonly see. Usually it takes *DrvStr like these 60 20 30 20 or 40 20 24 20 etc to pass TM5.


Yeah it does. HCI 500% too + 30 cycles of linpack.


----------



## Bloax

ioannis91 said:


> View attachment 2563569
> 
> I have implemented active cooling over the ram now so I can go up to 1.5v without overheating. What do you guys think I should try improving? Going flat 15s maybe?


It wouldn't start crashing hard if you set tRAS/tRC to 32/48, unless you set tCKE to 9, by any chance?


----------



## ioannis91

Bloax said:


> It wouldn't start crashing hard if you set tRAS/tRC to 32/48, unless you set tCKE to 9, by any chance?











This is the best I have managed so far. It passes the first cycle of usmus and on cycle 2 it returns error 6. Anything else I tried resulted in error in the first cycle. I will try your suggestions, thanks a lot!


----------



## TimeDrapery

Reduced VDIMM another 0.010V from 1.490V to 1.480V... still running Karhu RAM Test









I'll run TM5 one more again before moving ahead to bigger and better things...


----------



## TimeDrapery

Nope!

Forget it!

Even with Karhu RAM Test running until it's arrived at 25k% and TM5 running 1usmus_v3 and anta777's Extreme1 configurations with no errors I still fail OCCT's Memory test within a minute or less...

That's _regardless_ of:

command rate (1T, 1T with setup timing(s), GDM enabled, 2T... all of em')
timing parameters being configured loose as I can stand (17-17-17-40)
or as tight as I can get into Windows (14-13-13-32)
impedances / resistances
voltages (SOC, VDDG, VDDP, and VDIMM)
I ****ing hate 4x8GB overclocking... I'm not gonna do it anymore


----------



## SneakySloth

TimeDrapery said:


> Nope!
> 
> Forget it!
> 
> Even with Karhu RAM Test running until it's arrived at 25k% and TM5 running 1usmus_v3 and anta777's Extreme1 configurations with no errors I still fail OCCT's Memory test within a minute or less...
> 
> That's _regardless_ of:
> 
> command rate (1T, 1T with setup timing(s), GDM enabled, 2T... all of em')
> timing parameters being configured loose as I can stand (17-17-17-40)
> or as tight as I can get into Windows (14-13-13-32)
> impedances / resistances
> voltages (SOC, VDDG, VDDP, and VDIMM)
> I ****ing hate 4x8GB overclocking... I'm not gonna do it anymore


Could it be an issue with OCCT and your system? I have personally reported some issues with OCCT in the past to the developer which were corrected fairly quickly by them.

Have you tried using the Universal2 profile with TM5? I've always found that to work fairly well in finding errors. There is also MemTest Pro 7. I find that to work really well in finding errors despite it being extremely slow to run.


----------



## The_King

TimeDrapery said:


> Nope!
> 
> Forget it!
> 
> Even with Karhu RAM Test running until it's arrived at 25k% and TM5 running 1usmus_v3 and anta777's Extreme1 configurations with no errors I still fail OCCT's Memory test within a minute or less...
> 
> That's _regardless_ of:
> 
> command rate (1T, 1T with setup timing(s), GDM enabled, 2T... all of em')
> timing parameters being configured loose as I can stand (17-17-17-40)
> or as tight as I can get into Windows (14-13-13-32)
> impedances / resistances
> voltages (SOC, VDDG, VDDP, and VDIMM)
> I ****ing hate 4x8GB overclocking... I'm not gonna do it anymore


B-die is more sensitive to temps some may disagree but I know this for a fact since you increase from 1.43ish to 1.48V-1.51V you may get error free with active cooling on the RAM. Since you have 4 sticks close together running increased voltages.

The recommend DrvStr should be 40 20 30 20 or if you lower ProcODT 60 20 30 20/24 maybe something like this for 4x8GB. I had an issue with my B-die that went away running TWR 12 and RTP 8. it breaks some rule but it worked for me. Although I did not run it for hours it may be a good starting point.


----------



## ReyReverse

The_King said:


> B-die is more sensitive to temps some may disagree but I know this for a fact since you increase from 1.43ish to 1.48V-1.51V you may get error free with active cooling on the RAM. Since you have 4 sticks close together running increased voltages.
> 
> The recommend DrvStr should be 40 20 30 20 or if you lower ProcODT 60 20 30 20/24 maybe something like this for 4x8GB. I had an issue with my B-die that went away running TWR 12 and RTP 8. it breaks some rule but it worked for me. Although I did not run it for hours it may be a good starting point.
> 
> View attachment 2563637


Hi there, can you send thphn report here?


----------



## The_King

ReyReverse said:


> Hi there, can you send thphn report here?


Thaiphoon lists it has A0 PCB but apparently 4400 C19s are all A2.
I cant send a detail report, I'm running my 4700S at the moment with builtin GDDR6.
So I cant install the RAM on this board.


----------



## KedarWolf

I believe the top binned DDR4 b-die are the K4A8G085W[B/D]-BCPB like the below.

Like the G-Skill CL14 4000, CL14 3600 etc.

Those are getting Cl14 3800 on 5950x's etc. as long as you don't have the 3800 hole.

I had to send my first set of CL14 3600 Royal Elite back for a second set to get a good bin though.


----------



## The_King

KedarWolf said:


> I believe the top binned DDR4 b-die are the K4A8G085W[B/D]-BCPB like the below.
> 
> Like the G-Skill CL14 4000, CL14 3600 etc.
> 
> Those are getting Cl14 3800 on 5950x's etc. as long as you don't have the 3800 hole.
> 
> I had to send my first set of CL14 3600 Royal Elite back for a second set to get a good bin though.


What voltages are you using for RCDRD 14?


----------



## KedarWolf

The_King said:


> What voltages are you using for RCDRD 14?


I ran 1.5v memory on that TM5, .730v VTTs.


----------



## ReyReverse

KedarWolf said:


> I believe the top binned DDR4 b-die are the K4A8G085W[B/D]-BCPB like the below.
> 
> Like the G-Skill CL14 4000, CL14 3600 etc.
> 
> Those are getting Cl14 3800 on 5950x's etc. as long as you don't have the 3800 hole.
> 
> I had to send my first set of CL14 3600 Royal Elite back for a second set to get a good bin though.
> 
> View attachment 2563642
> 
> 
> View attachment 2563643
> 
> 
> View attachment 2563644


I can't run 3800 on my 5950x, but it worked on Zen 2 3700x 
it's sad. 
I believe all 5950x manufacture period on "21xxSUS" have this issue.


----------



## The_King

So Aaanyway!  

This video should be helpful for some.


Spoiler: DDR4 Voltage Regulation



*



*


----------



## ReyReverse

TimeDrapery said:


> Nope!
> 
> Forget it!
> 
> Even with Karhu RAM Test running until it's arrived at 25k% and TM5 running 1usmus_v3 and anta777's Extreme1 configurations with no errors I still fail OCCT's Memory test within a minute or less...
> 
> That's _regardless_ of:
> 
> command rate (1T, 1T with setup timing(s), GDM enabled, 2T... all of em')
> timing parameters being configured loose as I can stand (17-17-17-40)
> or as tight as I can get into Windows (14-13-13-32)
> impedances / resistances
> voltages (SOC, VDDG, VDDP, and VDIMM)
> I ****ing hate 4x8GB overclocking... I'm not gonna do it anymore


In your case 
4x8gb is another story
Loose your primary timings to 14 or 15 flat
You probably can save 50mv here
According Samsung official website
32gb trfc value at 750 , I guess you can start from here


----------



## TimeDrapery

ReyReverse said:


> In your case
> 4x8gb is another story
> Loose your primary timings to 14 or 15 flat
> You probably can save 50mv here
> According Samsung official website
> 32gb trfc value at 750 , I guess you can start from here


"Auto" sets tRFC to 350ns regardless of capacity installed and I _really really really_ don't think adding another 100ns on top will enhance stability specifically in OCCT's Memory test configured to utilize AVX2 instructions and 16 thread

Like I talked on earlier, I've loosed the primaries so far as 18-17-17-40... No 🎲


----------



## rissie

TimeDrapery said:


> "Auto" sets tRFC to 350ns regardless of capacity installed and I _really really really_ don't think adding another 100ns on top will enhance stability specifically in OCCT's Memory test configured to utilize AVX2 instructions and 16 thread
> 
> Like I talked on earlier, I've loosed the primaries so far as 18-17-17-40... No 🎲


I admire your resilience. If it was me I'd have ignored OCCT's test (HAHA!). I just stick with 25runs of TM5 1USMUS and call it a day. I don't run anything that pushes stability further really.


----------



## ReyReverse

TimeDrapery said:


> I _really really really_ don't think adding another 100ns on top will enhance stability specifically in OCCT's Memory test configured to utilize AVX2 instructions and 16 thread


never try never know


----------



## TimeDrapery

The_King said:


> B-die is more sensitive to temps some may disagree but I know this for a fact since you increase from 1.43ish to 1.48V-1.51V you may get error free with active cooling on the RAM. Since you have 4 sticks close together running increased voltages.
> 
> The recommend DrvStr should be 40 20 30 20 or if you lower ProcODT 60 20 30 20/24 maybe something like this for 4x8GB. I had an issue with my B-die that went away running TWR 12 and RTP 8. it breaks some rule but it worked for me. Although I did not run it for hours it may be a good starting point.
> 
> View attachment 2563637


I believe you... This mobo seems to hate having all four DIMM slots populated and I don't blame it considering the topology it's working with

I'll run through impedances and resistances again


----------



## Bloax

If DIMMs have a PCB that isn't compatible with low current operation (the "25%" in the 25%/75% split in daisy-chain topology) then they will always suck weiner in those slots.

My Ripjaws 3200 14-14-14 sticks wall around 3600 in the bad-slots, whereas these Viper 4400 sticks (which work great in the "bad" slots) would be doing 4200 15-15-15 just fine if the memory controller could handle it.

On LGA1700 you have the option of running mixed-DIMMs as long as they can run the same RTT Nom/Wr and RTP/tWR, by assigning different RTT Park terminations to the different DIMMs. On AM4, where you can't have slots A0B0 run a different RTT Park than A1B1, it's no fun trying to run 4x8 with anything but DIMMs that work well in "bad" slots.


----------



## ilezg

Hi! My setup is: 5950x, EVGA x570 Dark and F4-4400-C17D-32GTRG (thaiphoon screenshot attached). However it's literally impossible to run my memory at 3800cl14. Tried different timings and so on, however I can not make it stable, throws errors now and then in 1usmus_v3 test. I also haven't managed to run it 4000 cl14-15-15 (screenshot attached), also can not make it stable, throws erros (namely #2, #10, #13). Tried fixing the stability using 1usmus_v3 error list, however fixing one issue immediately throws the other one. 

As of now I am only able to run my memory stable at 3800 cl14-15-15 and 4066 flat 16 (decided to swith to 3800 though, screenshot attached). So I wonder if it's just bad memory bins or I'm doing anything wrong? Any help would be appreciated!


----------



## KedarWolf

ilezg said:


> Hi! My setup is: 5950x, EVGA x570 Dark and F4-4400-C17D-32GTRG (thaiphoon screenshot attached). However it's literally impossible to run my memory at 3800cl14. Tried different timings and so on, however I can not make it stable, throws errors now and then in 1usmus_v3 test. I also haven't managed to run it 4000 cl14-15-15 (screenshot attached), also can not make it stable, throws erros (namely #2, #10, #13). Tried fixing the stability using 1usmus_v3 error list, however fixing one issue immediately throws the other one.
> 
> As of now I am only able to run my memory stable at 3800 cl14-15-15 and 4066 flat 16 (decided to swith to 3800 though, screenshot attached). So I wonder if it's just bad memory bins or I'm doing anything wrong? Any help would be appreciated!


Try VSOC up to 1.2v, VDDP .900v, VDDGs at 1.1v and 1.15v respectively. Try VTTs at .730v or if that doesn't work, half of your RAM voltage Try the voltage that is 1.8v at stock, I forget what is called, at 1.9v. Try RAM voltages starting at 1.49v or 1.5v, up to 1.54v, 1.54v if you use a RAM fan. Ideally, you want RAM temps below 40C while stress testing, 50C absolute max. Need RAM fans for that. 

Search my username KedarWolf in a custom search with 'RAM fans' and find the post of the Aliexpress RAM fan I bought, then replaced the stock fans with 10000 RPM ones, but you need to run them at 3000 RPM to be silent or if background noise isn't an issue, up to 7000 RPM is fine.

I'm at work right now. Search is your friend.


----------



## Bloax

KedarWolf said:


> Try VSOC up to 1.2v, VDDP .900v, VDDGs at 1.1v and 1.5v respectively.


1.5v on either IOD or CCD heheheheh boom boom 🤡

edit: ok all good

apropos searching:









Memory Cooling


Hey ALL, what would be an easy way to put a fan to cool two GSkill trident Z NEO sticks? They are the f4-3600c16-32gtzn. After front mounting my new 360 AIO they got hot (up to 49C) after a gaming session.




www.overclock.net






https://www.overclock.net/threads/post-your-last-purchase.287513/page-2275#post-28769722


----------



## KedarWolf

Bloax said:


> 1.5v on either IOD or CCD heheheheh boom boom 🤡
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Memory Cooling
> 
> 
> Hey ALL, what would be an easy way to put a fan to cool two GSkill trident Z NEO sticks? They are the f4-3600c16-32gtzn. After front mounting my new 360 AIO they got hot (up to 49C) after a gaming session.
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> 
> https://www.overclock.net/threads/post-your-last-purchase.287513/page-2275#post-28769722


Fixed it, meant 1.15v.


----------



## The_King

KedarWolf said:


> I believe the top binned DDR4 b-die are the K4A8G085W[B/D]-BCPB like the below.
> 
> Like the G-Skill CL14 4000, CL14 3600 etc.
> 
> Those are getting Cl14 3800 on 5950x's etc. as long as you don't have the 3800 hole.
> 
> I had to send my first set of CL14 3600 Royal Elite back for a second set to get a good bin though.
> 
> View attachment 2563642


This should also be a good bin. 2400R


----------



## ReyReverse

The_King said:


> This should also be a good bin. 2400R
> View attachment 2563789


I thought you disagree it?
This definitely a good bin


----------



## The_King

ReyReverse said:


> I thought you disagree it?
> This definitely a good bin


Not sure why you would think that? I also read hardwareluxx.de


----------



## Gegu

After changing my faulty motherboard to the second CH8Extreme sample I repeated the TM5 test and found some errors - needed to change tRTP and TRW to 6/12 - now I can pass 25 cycles of 1usmus v3 repeatedly (see attachments). Time to test the RS/RL 3/8 and tRFC 224.


----------



## The_King

Gegu said:


> After changing my faulty motherboard to the second CH8Extreme sample I repeated the TM5 test and found some errors - needed to change tRTP and TRW to 6/12 - now I can pass 25 cycles of 1usmus v3 repeatedly (see attachments). Time to test the RS/RL 3/8 and tRFC 224.


You have to run TM5 has admin in order for it to work correctly. Your tests were both done in compatability mode.


----------



## Xipe

i have The TeamGroup T-Force Xtreem ARGB 32gbs cl14.

















This is my results, with 10 cycles of tm5.
cldo vddp is 1.05
vddg ccd is 1.075
vddg iod is 1.075
Vdim is 1.504
Isnt stable.... Bsod ... What i can change?


----------



## Gegu

The_King said:


> You have to run TM5 has admin in order for it to work correctly. Your tests were both done in compatability mode.


Yah ur right - I did another test, this time as admin - same result


----------



## The_King

Gegu said:


> Yah ur right - I did another test, this time as admin - same result


Some Kits can do TWR 10 RTP 5 with GMD Disabled.

tRAS 24 - tRCD 14 is 10.


----------



## Gegu

The_King said:


> Some Kits can do TWR 10 RTP 5 with GMD Disabled.
> 
> tRAS 24 - tRCD 14 is 10.


With TWR 10 TRTP 5 I have sometimes single test 9 error of 1usmus preset


----------



## The_King

Gegu said:


> With TWR 10 TRTP 5 I have sometimes single test 9 error of 1usmus preset


Is your VDIMM 1.2480? if so thats probably too low.


----------



## Gegu

The_King said:


> Is your VDIMM 1.2480? if so thats probably too low.


No, It's Zen Timings issue. My VDIMM is 1.51V


----------



## Gegu

Good news - my kit is capable of running RS/RL 3/8 and SCL's at 2 also - I know it's screen without admin run, will make another one.


----------



## koala7

ran tm5 with 1usmus profile 80x got 1 error
error #0
what can i do to improve it? please help


----------



## The_King

koala7 said:


> ran tm5 with 1usmus profile 80x got 1 error
> error #0
> what can i do to improve it? please help


GDM Disable 1T without AddrCmd 56 is very good. Did you run 80 cycles? If so I would not be bothered personally.

error #0 is usually tRRD and tWTR it can also be that your tRFC or SCL too low.

First I would increase TRFC to 256 and test again before changing anything else. Second SCL to 3s if that first change does not work.

Edit:
Maybe you might want to change SCL to 3/4s first before changing the tRFC.


----------



## Veii

koala7 said:


> ran tm5 with 1usmus profile 80x got 1 error
> error #0
> what can i do to improve it? please help
> View attachment 2563876


Stability check to fix error








If error has resolved








Keep tRP matching tRCD_RD. Alternative Match (tRCD_RD+tRCD_WR) / 2 ~ to preserve left enough charge between read and write
Keep tRAS as tRP + tRCD_RD, alternatively go for stacked-shorted/write-split approach (tRCD_RD+tRTP) ~ but requires discharge finetuning. 2nd picture might not work out instantly and/or will lose bandwidth if discharge happens faster than timings (halt-autocorrection)

Compare performance Aida64 & Benchmate y-cruncher 2.5b








Wait 2min between test, if on Air. 5-10min if on AIO or Water
Accuracy till 0.Xxx sec is important (single digit decimal)
If fluctuation is higher, full seconds focus on your core stability and give more time for heat to normalize between tests..

If tight preset does not function, but first does
Copy over Powering section
Pick the preset which is faster, not which looks tighter

If A0 PCB







Same thing, but weakened RTT_PARK

A0 vs A1/2/3








IC height to Pads ~ visible from bottom and sides

A1~A2








SMD module over bump ~ check both sides, sticker usually indicates "main" side
Non DR-A Modules , place where thermal pad is , single side = main side

A2~A3
Center trace difference. A3 has more and more straight/direct top-level-visible traces

G.Skill A1 10 layer ~ is readable out via Thaiphoon Burner, but is custom A1
ViperTW A2 layout, is custom A1 ~ readout sometimes as A0 sometimes A2
GALAX/ICE/Blade, is often pure A1 or pure A2. Can be fully different but rarely in-house design
G.Skill/Teamgroup/Corsair A2 RGB, is custom A2

A is an indication for SR
B is an indication for dual Rank
Layouts sometimes are type C or type D on design, but for community it's A or B


----------



## koala7

The_King said:


> Did you run 80 cycles?


i did
set 100 cycles on the profile
thank you ill try it


----------



## mongoled

After a long hiatus, can someone give me the low down on agesa 1.2.0.7 is it a hit or miss on x570 ?


----------



## Blackfyre

mongoled said:


> After a long hiatus, can someone give me the low down on agesa 1.2.0.7 is it a hit or miss on x570 ?


Better overall system stability with latest chipset drivers + AGESA 1.2.0.7
Slightly lower benchmark performance because stock voltages do not go as high as they used to with earlier iterations.
Performance in real world programs or games is identical, if not better actually, with newer AGESA due to stability and less hiccups.

RAM Overclocking identical too all previous version, I've never had an AGESA update ruin my tight RAM OC.


----------



## byDenoso

My new stable OC


----------



## Audioboxer

I know this is the AMD topic, but do any of you know if any of the DDR4 690 boards are any good for OCing? No 2 DIMMs, so just wondering.


----------



## Luggage

Audioboxer said:


> I know this is the AMD topic, but do any of you know if any of the DDR4 690 boards are any good for OCing? No 2 DIMMs, so just wondering.


It's only 184 pages, you might still catch up ;P 









[Official] Intel Z690 / Z790 DDR4 Daily Memory Overclock


Welcome to the Daily Memory Overclock thread for DDR4 memory on the Z690 and Z790 Chipset (LGA1700). Z690 Tools ASRock Timing Configurator (4.0.13) ASUS MemTweakIt (20210910) MSI Dragon Ball (1.0.0.08) MSI Dragon Power (1.0.0.6)




www.overclock.net


----------



## Bloax

Audioboxer said:


> I know this is the AMD topic, but do any of you know if any of the DDR4 690 boards are any good for OCing? No 2 DIMMs, so just wondering.


There haven't really been any standouts, to my not particularly vigilant eye.
Everyone's mostly just bonking up against IMC limits, rather than board limits.

The aSUS TUF had an early advantage in 2x16 b-die, but things have basically equalized over time.








the pro-a is cheap and runs procODT 24 (I presume, a value of [15] is 360 divided by 15), which is quirky and lets you do dumb things like running tCCD 3 that didn't like being stable otherwise.
whether that's relevant for anything but 2x8 or 4x8 is anyone's guess, as dual-rank sticks tend to demand higher procODTs


----------



## Audioboxer

Bloax said:


> There haven't really been any standouts, to my not particularly vigilant eye.
> Everyone's mostly just bonking up against IMC limits, rather than board limits.
> 
> The aSUS TUF had an early advantage in 2x16 b-die, but things have basically equalized over time.
> View attachment 2564026
> 
> the pro-a is cheap and runs procODT 24 (I presume, a value of [15] is 360 divided by 15), which is quirky and lets you do dumb things like running tCCD 3 that didn't like being stable otherwise.
> whether that's relevant for anything but 2x8 or 4x8 is anyone's guess, as dual-rank sticks tend to demand higher procODTs


Yeah, memory was my main focus which is why I asked in here, didn't know a topic like this existed already for Intel. None of the DDR4 boards are 2 DIMMs.

Was contemplating buying a 12900k and a DDR4 board and seeing if I can have some fun with my DR kit above 3800. Those adventures are DOA on this 5950x and from what I can see the 5800X3D often has a 1900 wall as well. Some people are getting beyond without WHEA but it's a risk. That's the only other AM4 chip I'd consider having some fun with, anything else is too much of a downgrade from a 5950x.

Heck, the fact I don't have a 1900 hole is a win as well given that's apparently still a thing on those 3D chips.

*edit* - Looks like the Asus ROG Strix Z690-A Gaming WIFI D4 is one of the only boards with a clear CMOS button at the back, I love having that. Will look at how it performs with memory.


----------



## heptilion

Veii said:


> Ah ok, you have one CCD
> My bad, there was no signature and i can't remember everyone's system - sorry
> 
> Hydra values are complicated,
> CO values change by -2 , every +25mhz fMAX youset
> 1 CO value = 6.25 Hydra value, and while Hydra provides value ~ older "early" public hydra does not try to redo frequency testing if "predicted CO for testing" was wrong
> Soo either it gives perfect results, or it misses them and makes the sample look worse
> 
> Soo suggested CO values are not always optimal, and side-product of this is, that "best cores" are also not always optimal
> Yuri and I, have a different viewpoint but try to work with each others experience ~ soo it improves
> I personally, would trust more CPPC , although it has been shown that they are wrong in what is "a good" and "a bad" core
> I would use CPPCs distance between cores, hence the average of CPPC by CCD is always equal on a by-SKU base
> Soo 5600X will have the same average CPPC rating, 5800X will all have the same average and target binning, and so on
> 
> It's also important to keep in mind that Hydra results will differ ! , between 0 fMAX, between Auto board-partner-cheatery +100 fMax , and between +200fMax
> So also will the result of the "quality based on allcore efficiency" differ by the used scalar changing option
> And also FIT will interfere in how high Hydra can boost cores up ~ because this "sometimes annoying thing" ~ is not disabled neither in PB2 nor in OC_MODE , and also not in XOC mode (not fully)
> 
> Potentially the best way to make a hydra debug run ~ is with X1 scalar or X6 scalar (enforced)
> With fully open limits as for example 400W-400A-400A. With fully open cTDP and package throttle wattage targets & with currently running memOC + LN2 toggles
> LN2 toggles will lift couple of peak-voltage restrictions, but board-power limiters have to be set between vendors on different places (sometimes CBS sometimes AMD OVERCLOCKING)
> 
> Opening Board limits will not only increase heat, but also change how COs are, as FIT will fully overvolt cores (well to the values they usually "should" be)
> Only then it makes sense to start limiting CO's with magnitutes, like everything -1 , everything -2 and so on
> But you have to fix the distance delta issues, because that (cores holding freq strap bigger than 25mhz distance) is what will put other cores down
> Soo while you will see that cores VID is lower ~ sometimes it is an indicator of "too much negative voltage drop" . . . aka balance between cores inside same CCD is important, and average VID balance between CCD00 & CCD01 is important too
> View attachment 2548088
> 
> 
> please start with *
> C0 [150] ~ 0
> C1 [143] ~ -4
> C2 [135] ~ -8
> C3 [146] ~ -2
> C4 [139 ?] ~ -6
> C5 [150] ~ 0
> C6 [131] ~ -10
> C7 [127] ~ -12
> ^ your delta in AMD defined quality rating
> * then go -1 on everything together, till on 0MHz FMax you find all cores reaching the same held frequency in either TM5 or boost tester , something SSE load based
> 
> [/CODE]Should help you in your CO figuring out path


@Veii

So i am trying to follow this steps and have come this far. 

Current = My stable settings that i know works. But each core speed is all over the place and i want to try to equalise all of my cores if possible. I have run the numbers and this is what i came up with. 

My core 3 is only table at -5 so if im to follow your steps i should keep that at -5 and increase the rest by -1 each? as in then it will be -1,-3,-10,-5,-1 etc..? wouldnt that cause my core 3 to have a further gap?


----------



## Veii

heptilion said:


> @Veii
> 
> So i am trying to follow this steps and have come this far.


Wow that post is old 

Gladly things keep improving by time, but i have to correct some things:
~ Delta of minimum and maximum allcore strap inside same CCD = 100MHz before it cuts fastest core strap down to match minimum strap
(stretching exists, just "what is" stretching).
~ 25MHz is the delta it can run within the same strap, before having to shift to a lower strap ~ average all-core frequency delta
~ Distance between CCD's is still in a non publishable state. Sadly. Maybe some of the people on Hydra's Information section can publish this information. Maybe Yuri answers you this exact question if he can, by time.
~ CPPC rating is half-fixed. It's order is dynamic hence CO margin (PSM margin ~ ty @PJVol) differs on-boot. CPPC average distance to cores is per SKU fixed (min-max binning delta) but this method used, is to average cores VID and nullify wave-delta (curve up/down delta) ~ soo flatten it out. Flatten Curve assists dLDO_Injector and prevents "random" strap changing issues by wrongly prioritized current shifting

What kept staying correct:
~ Hydra CO and conversion CO values from fMAX extend (+25mhz = -2 Bios CO)
~ FIT's peak voltage behavior and "random" shutdowns that are not stability based (request beyond V_MAX value)
~ First stage power-limiters (PPT, TDC, EDC) influencing VID requests & messing with CO
~ Scalar messing with CO
~ Current CO is 6.25mV, it was ~2mV before when access bellow -30 CO was granted.
~ SVI2 strap shift is 6.25mV. VID falling bellow 25mV distance, is autocorrected but can cause a stability issue. SVI 3 is much better now. // This counts for GPUs & CPUs

CCD CO "delta" inside same CCD can be seen as an own thing.
The best advice i can give, is to watch when CPU_Latch voltage wiggles, and to remove all first stage limiters.
It will wiggle by reaching procHot and wiggle by recognizing subtle VID request spikes.
It is also problematic because powerplans are sub-optimal (wake up cores) and non MUTEX tools are far to slow to track. Human eyes too tbh. Skilled person can notice 5-6ms changes, but FIT is sometimes faster ~ up to system load.
^ any system load will influence and mess with COs

You have to split your CO's in 3 categories:
~ Max single core boost-droop values for SSE/AVX/AVX2 // only when CPPC is functional and no load wakes up "other cores" that will mess with dLDO-Regulator
~ Max allcore for SSE/AVX/AVX2, while staying bellow powerlimits and bellow thermal limits
~ Per CCD focused state ~ optimally even with one CCD short time turned off // it slightly will influence signal integrity but at worst should be 1-2 CO off, max (figuring CCD delta out at the end)

Soo work steps:
*>* Use Boosttester for SSE loads and or OCCT ~ to correctly assign load to core but not thread // lower CO value to stay bellow max-VID throttle requests
^ do it for the whole CCD, ignore the 2nd CCD or keep it for about +/- 15-16 CO apart (average CCD to other CCD, CO) ~ your current CCD 1 = -15.615 CO, CCD2 is -19.5 // delta is ~ -3 CO
I can't give exact CCD to CCD delta values, i haven't found them out myself ~ to share. But math looks about like this


Spoiler: CO mid-post brainstorming



Delta allowed in the current state is 200MHz . That is 16 CO (8 x 25Mhz [-2CO each]) for 0-200MHz fMAX. -2 CO delta (25Mhz) is +/- 8mV distance between straps
(SVI2 is 6.25mV = 12.5mV shift possible) ~ i think it makes sense to give wiggle room of +/- 12.5mV aka 2 steps up & 2 steps down // 1 CO = 4mV ; 3 CO steps, -1 , 0 and +1 )
== for an dual CCD allcore load, max delta allowed between each "could" be +/- 8 CO // +/- 32mV
(+/- 50mV on own thought, as early +/- 50 CO = +/- 2mV = 100mV 
/// SVI2 spec would be +/- 1.5625mV = 78.125mV for 50 CO...
/// buut that also makes no sense and CO should be +/- 64 CO ala 1.5625mV each... or with other words 16 x SVI2 shifts = +/- 8 up and down. 
Wonder what direction FW-Design team picked. +/- 64 CO fine granular (16 non granular) or +/- 50 CO, trusting on SVI2 value balancing)

Realistically i think, current 2 CO's are not 8mV but 6.25mV. (1 CO = 3.125mV on granular/correction mode)
That makes much more logical sense within SVI2 spec. It also makes it correct to be from 3-5mV publicly stated.
I will ask around ~ and if i can share it, you'll get an update. Anywho should give an later update and write-up to this. Haven't had a need to think deeper about per-CCD delta 


*>* 2nd, after having it done per core in one CCD, use y-cruncher [BKT test], isolate each CCD on non AVX2 test and do the same ~ all up and all down till you have a reboot
Then shift to 2nd CCD, same thing. Once you have no more reboots ~ test both and shift all +/- 2 CO
*>* (step 3, optional) ; run the whole sample through OCCT Extreme (AVX !) and fix loadline droop & potentially shift -/+2 CO everything
*> *step 4, run whole y-cruncher test-suite and test both CCD's. AVX2 has a fixed droop ontop of AVX based LLC droop ~ soo reboots will happen.
If nothing improves with 4 CO shifts (after point 1 do not touch any single core) ~ when start to balance failing CCD up 2 steps or down 2 steps.
If that does not fix it - keep track of WHEA #18 ACPI ID (starts with 0-15 & 16-31), and maybe fall back to step #1 again , just with AVX2 focused (that is OCCT and y-cruncher N32, N64, VST)

At this point you should have it correct 
========================================================================
Also mid-brainstorming and thinking deeper about it ~ i think i'll stick to this, as it makes much more sense:
Old CO pre AGESA 1.1.8.X:
4 CO = 6.25mV, 2 CO on granular = 3.125mV , 1 CO on fine granual = 1.5625mV
Limit was - 64 / + 64 CO (200mV range) // user allowed -/+ 50 CO (156.25mV range)
^ potential unclearness, i got it now tho
~ brainstoming was blinded by already 3rd time CO behavior change 🤦‍♂️ AMD fixed old CO granularity


Code:


Current CO after AGESA 1.2.0.0:
2 CO = 12.5mV = 25MHz
1 CO = 6.25mV = 1 SVI2 shift
// granularity is handled by dLDO now

+25 Hydra Value = -25mV == -4 Bios CO = 4x SVI2 shifts
-30 BIOS CO = -187.5mV == +187.5 Hydra Value // a mess

Future BIOS OC after 1.2.0.7+
-40 BIOS CO = -250mV = +250 Hydra Value
// but it seems ~ while code exists, it doesn't apply yet

All you have to know 
About remain unclearness, i'll see what i can do. But still recommend ~ to go and ask Hydra Information supporters or Dev's about it


----------



## koala7

@Veii 
i tried the settings and the 2nd preset is faster
also copied all the powering section
my kit wont run y cruncher on tRAS 21
vddg ccd set in bios is 975 (is this good?)
but still getting 1 error in tm5 100 cycles


----------



## Veii

koala7 said:


> @Veii
> i tried the settings and the 2nd preset is faster
> also copied all the powering section
> my kit wont run y cruncher on tRAS 21
> vddg ccd set in bios is 975 (is this good?)
> but still getting 1 error in tm5 100 cycles
> View attachment 2564215


Hmm, zero translates to a voltage-leakage issue by time

Only things you haven't really changed are SOC and VDDG IOD
VDIMM & tRFC should've failed much ealier with a non consistent error
I fear that's CPU side or outside of PC side

You fully changed powering and procODT
Yet it consistently fails with the same issue.
That's clearly not dimm related and usually not voltage related. Sounds like a heat discharge issue

Could actually be board VRM heating and loadline being worse
Increase SOC to 1125mV , or 25mV over what you currently run.
Matisse had "negative" scaling after 1150mV SOC - soo you still have a bit of headroom
And Matisse run 28.2ohm for SR ~ you could drop to 30ohm, buut 32 is fine.
Try with slightly higher SOC 

Later invest a bit of time without touching tRFC
In comparing tRAS
You will see a huge drop when tRAS is "too low" ~ because lower is not always better








====================================================
I've settled for this now , from usual 55ns
Micron does not follow typical refresh method ~ but more to it once i get sub 50ns
Currently i feel they will replace my Vipers  just CAS 14, tCWL 10 is a bit finicky with tPHY 28
















Also Rev.E does not help FCLK ~ as it's not the IMC that's the issue. It's the substrate
They might be helpful for Monolithic ones tho ~ but do nothing, even "harm" your usual preset
2100 & 2133 are much harder to get stable than with "taxing b-die"


----------



## heptilion

Veii said:


> Wow that post is old
> 
> Gladly things keep improving by time, but i have to correct some things:
> ~ Delta of minimum and maximum allcore strap inside same CCD = 100MHz before it cuts fastest core strap down to match minimum strap
> (stretching exists, just "what is" stretching).
> ~ 25MHz is the delta it can run within the same strap, before having to shift to a lower strap ~ average all-core frequency delta
> ~ Distance between CCD's is still in a non publishable state. Sadly. Maybe some of the people on Hydra's Information section can publish this information. Maybe Yuri answers you this exact question if he can, by time.
> ~ CPPC rating is half-fixed. It's order is dynamic hence CO margin (PSM margin ~ ty @PJVol) differs on-boot. CPPC average distance to cores is per SKU fixed (min-max binning delta) but this method used, is to average cores VID and nullify wave-delta (curve up/down delta) ~ soo flatten it out. Flatten Curve assists dLDO_Injector and prevents "random" strap changing issues by wrongly prioritized current shifting
> 
> What kept staying correct:
> ~ Hydra CO and conversion CO values from fMAX extend (+25mhz = -2 Bios CO)
> ~ FIT's peak voltage behavior and "random" shutdowns that are not stability based (request beyond V_MAX value)
> ~ First stage power-limiters (PPT, TDC, EDC) influencing VID requests & messing with CO
> ~ Scalar messing with CO
> ~ Current CO is 6.25mV, it was ~2mV before when access bellow -30 CO was granted.
> ~ SVI2 strap shift is 6.25mV. VID falling bellow 25mV distance, is autocorrected but can cause a stability issue. SVI 3 is much better now. // This counts for GPUs & CPUs
> 
> CCD CO "delta" inside same CCD can be seen as an own thing.
> The best advice i can give, is to watch when CPU_Latch voltage wiggles, and to remove all first stage limiters.
> It will wiggle by reaching procHot and wiggle by recognizing subtle VID request spikes.
> It is also problematic because powerplans are sub-optimal (wake up cores) and non MUTEX tools are far to slow to track. Human eyes too tbh. Skilled person can notice 5-6ms changes, but FIT is sometimes faster ~ up to system load.
> ^ any system load will influence and mess with COs
> 
> You have to split your CO's in 3 categories:
> ~ Max single core boost-droop values for SSE/AVX/AVX2 // only when CPPC is functional and no load wakes up "other cores" that will mess with dLDO-Regulator
> ~ Max allcore for SSE/AVX/AVX2, while staying bellow powerlimits and bellow thermal limits
> ~ Per CCD focused state ~ optimally even with one CCD short time turned off // it slightly will influence signal integrity but at worst should be 1-2 CO off, max (figuring CCD delta out at the end)
> 
> Soo work steps:
> *>* Use Boosttester for SSE loads and or OCCT ~ to correctly assign load to core but not thread // lower CO value to stay bellow max-VID throttle requests
> ^ do it for the whole CCD, ignore the 2nd CCD or keep it for about +/- 15-16 CO apart (average CCD to other CCD, CO) ~ your current CCD 1 = -15.615 CO, CCD2 is -19.5 // delta is ~ -3 CO
> I can't give exact CCD to CCD delta values, i haven't found them out myself ~ to share. But math looks about like this
> 
> 
> Spoiler: CO mid-post brainstorming
> 
> 
> 
> Delta allowed in the current state is 200MHz . That is 16 CO (8 x 25Mhz [-2CO each]) for 0-200MHz fMAX. -2 CO delta (25Mhz) is +/- 8mV distance between straps
> (SVI2 is 6.25mV = 12.5mV shift possible) ~ i think it makes sense to give wiggle room of +/- 12.5mV aka 2 steps up & 2 steps down // 1 CO = 4mV ; 3 CO steps, -1 , 0 and +1 )
> == for an dual CCD allcore load, max delta allowed between each "could" be +/- 8 CO // +/- 32mV
> (+/- 50mV on own thought, as early +/- 50 CO = +/- 2mV = 100mV
> /// SVI2 spec would be +/- 1.5625mV = 78.125mV for 50 CO...
> /// buut that also makes no sense and CO should be +/- 64 CO ala 1.5625mV each... or with other words 16 x SVI2 shifts = +/- 8 up and down.
> Wonder what direction FW-Design team picked. +/- 64 CO fine granular (16 non granular) or +/- 50 CO, trusting on SVI2 value balancing)
> 
> Realistically i think, current 2 CO's are not 8mV but 6.25mV. (1 CO = 3.125mV on granular/correction mode)
> That makes much more logical sense within SVI2 spec. It also makes it correct to be from 3-5mV publicly stated.
> I will ask around ~ and if i can share it, you'll get an update. Anywho should give an later update and write-up to this. Haven't had a need to think deeper about per-CCD delta
> 
> 
> *>* 2nd, after having it done per core in one CCD, use y-cruncher [BKT test], isolate each CCD on non AVX2 test and do the same ~ all up and all down till you have a reboot
> Then shift to 2nd CCD, same thing. Once you have no more reboots ~ test both and shift all +/- 2 CO
> *>* (step 3, optional) ; run the whole sample through OCCT Extreme (AVX !) and fix loadline droop & potentially shift -/+2 CO everything
> *> *step 4, run whole y-cruncher test-suite and test both CCD's. AVX2 has a fixed droop ontop of AVX based LLC droop ~ soo reboots will happen.
> If nothing improves with 4 CO shifts (after point 1 do not touch any single core) ~ when start to balance failing CCD up 2 steps or down 2 steps.
> If that does not fix it - keep track of WHEA #18 ACPI ID (starts with 0-15 & 16-31), and maybe fall back to step #1 again , just with AVX2 focused (that is OCCT and y-cruncher N32, N64, VST)
> 
> At this point you should have it correct
> ========================================================================
> Also mid-brainstorming and thinking deeper about it ~ i think i'll stick to this, as it makes much more sense:
> Old CO pre AGESA 1.1.8.X:
> 4 CO = 6.25mV, 2 CO on granular = 3.125mV , 1 CO on fine granual = 1.5625mV
> Limit was - 64 / + 64 CO (200mV range) // user allowed -/+ 50 CO (156.25mV range)
> ^ potential unclearness, i got it now tho
> ~ brainstoming was blinded by already 3rd time CO behavior change 🤦‍♂️ AMD fixed old CO granularity
> 
> 
> Code:
> 
> 
> Current CO after AGESA 1.2.0.0:
> 2 CO = 12.5mV = 25MHz
> 1 CO = 6.25mV = 1 SVI2 shift
> // granularity is handled by dLDO now
> 
> +25 Hydra Value = -25mV == -4 Bios CO = 4x SVI2 shifts
> -30 BIOS CO = -187.5mV == +187.5 Hydra Value // a mess
> 
> Future BIOS OC after 1.2.0.7+
> -40 BIOS CO = -250mV = +250 Hydra Value
> // but it seems ~ while code exists, it doesn't apply yet
> 
> All you have to know
> About remain unclearness, i'll see what i can do. But still recommend ~ to go and ask Hydra Information supporters or Dev's about it


Ok so let me get my head around this.

1. Should I be using default PPT,TDC,EDC or use something like 220,140,140(limiting 140 so VID wont be stuck at 1.4?) or just uncap everything? 

2. What is my max-vid throttle? How do I find this out?

3. My core 3 is only stable at -5 under OCCT avx2 large variable physical and virtual core cycle 10 min run each so if I follow your steps and start from scratch are you saying I will be able to run my core 3 at a higher value than -5? But since avx2 vdroop is fixed it shouldn't change right? therefore wouldn't my single thread/all core boost will still be limited by that for CCD1? And since my CCD2 is even lower that is going to be my all core boost.


----------



## The_King

Veii said:


> View attachment 2564222


Are those sticks CB MAX 4000 CL18s, what voltage are you using for 4200 CL15?

Is lower RFC not stable? Lowering that could get you into the high 40ns.

With my Patriot Vipers 4400s @ 4000 CL 14-15-15 I got to 50.8ns in AIDA64. Could not get is stable but never tried over 1.55V. It was just for fun.
Im sure you could get those stable


----------



## Veii

heptilion said:


> 1. Should I be using default PPT,TDC,EDC or use something like 220,140,140(limiting 140 so VID wont be stuck at 1.4?) or just uncap everything?


Any limiters will limit how much VID is requested on X load
AGESA 1207 is different and annoying to some extend - but if you have to keep in mind, that hitting limiters will lower VID == will modify or mess up CO range


heptilion said:


> 2. What is my max-vid throttle? How do I find this out?











CPU SET voltage is the SKU range
Latchup_voltage, or V_MAX is the fused sample ~ FIT range
Throttle voltage, is hidden - but it's 1.4v for me
usually 50mV lower than V_MAX

You will notice which one it is, soo i am not sure if AGESA 1205+ will limit this to 1.4 and keep 1.4v limit ~ matching throttle voltage with V_MAX
Oor it still leaves that overshoot heatroom and a 1.45v cap means, that 1.35 will be the peak it allows

Depends, but i'm still questioning if i should upgrade
especially since i've messed up my sensors and can't run HWInfo anymore (freezes on Ring-0 access, as sensorics are dead)
Messed up with AMISCE & no CMOS reset fixes it , tho don't want to lose my profiles ~ whoops


----------



## Veii

The_King said:


> Are those sticks CB MAX 4000 CL18s, what voltage are you using for 4200 CL15?
> 
> Is lower RFC not stable? Lowering that could get you into the high 40ns


4000 18-19-19 , yes
1.6-1.64
I mean voltage means nothing, amperage is lower // but they are A2 8-layer








1.68 is for CL14 and tRCD 19, but performance is worse
Micron kits use a different refresh method - high tRFC doesn't bother and low tRAS is missed, works is stable but is missed. // loss of 2ns for "nothing"
I'll write more to it once i've gotten CAS 14 stable
I really like them and they are fast ~ but only now that i know how to work with them
Tertiaries are still high coming from my 4800 preset
Just shared to show that tRAS plays a role and it's not the "normal" refresh method as how Samsung/Jedec PCBs behave


Veii said:


> Micron kits use a different refresh method - high tRFC doesn't bother


Lower tRFC pushes me to higher tPHY and or misses refresh stacking
I'm still working on it & if suspicion is true ~ i'll redo tRFC mini a bit.
I bet people usually don't know different refresh methods ~ when it usually is an LPDDR/GDDR only thing


----------



## The_King

Veii said:


> 4000 18-19-19 , yes
> 1.6-1.64
> I mean voltage means nothing
> 
> 1.68 is for CL14 and tRCD 19, but performance is worse
> Micron kits use a different refresh method - high tRFC doesn't bother and low tRAS is missed, works is stable but is missed.
> I'll write more to it once i've gotten CAS 14 stable
> I really like them and they are fast ~ but only now that i know how to work with them
> Tertiaries are still high coming from my 4800 preset
> Just shared to show that tRAS plays a role and it's not the "normal" refresh method as how Samsung/Jedec PCBs behave
> 
> Lower tRFC pushes me to higher tPHY and or misses refresh stacking
> I'm still working on it & if suspicion is true ~ i'll redo tRFC mini a bit.
> I bet people usually don't know how different refresh methods ~ when it usually is an LPDDR/GDDR only thing


Looking forward to an update. I have bought a ton of CB Max Kits has they are going really really cheap here since, Crucial stopped there Ballistix series production and the prices of these kits are cheaper than the 3000 CL15 and 3600 CL16s in my country at least.

@Veii Any input on getting something like this stable on the Vipers will be greatly appreciated!


----------



## Veii

The_King said:


> With my Patriot Vipers 4400s @ 4000 CL 14-15-15 I got to 50.8ns in AIDA64. Could not get is stable but never tried over 1.55V. It was just for fun.


4000 A0 vipers run 14-14-14 at 1.65-1.66
Just RTT & CAD_BUS are fine ~ soo voltage becomes irrelevant at this point  They don't even need active cooling, tho on TM5 i like to lean a fan next to them, slightly. I have no cases, only an open test-bench & it's 26° roomtemp (summer)

VDIMM is only a question, because it will cause DIMM-PCB's to crash
on A0 already at 1.48v - 1.52v, higher was even "dangerous" and could kill them
A1 - A2 seem to also become unstable at ~1.53v

Real IC limits were on my B-dies at 1.68v and on the MAX on 1.72v
I can't weaken powering further, soo i'd say 1.72v is my wall so far with them
For the A0's 1.67-1.68, i jump between 1.64-1.68 , up to experiment ~ if it needs it or not
For more voltage i need maxmem, but i won't use that thing ~ not an XOC guy. Foundation is amateur, not good enough for XOC & a too expensive hobby


The_King said:


> Looking forward to an update. I have bought a ton of CB Max Kits has they are going really really cheap here since,


For Micron kits, try to either keep it tRAS = tRCD+tRCD+6 (failsafe)
or more correct








Just CAS-bef-RAS refresh while used on DDR5 and LPDDR
here it's different ~ slightly
It uses an alternate one and depends on tCWL and tCL state (RAS itself)
Also refresh depends on tRFC ~ too low tRFC and it breaks
It works usually -1 of tCAS*3 to -2
But that is too vague for a rule ~ it depends on more things, and easiest is to test it
Higher tRAS doesn't bother ~ too low and MSR (chip on PCB) notices it and switches away from this refresh method.
It certainly can not run tRCD+tRTP - as it isn't programmed to refresh that way , like usually b-die can. It behaves fully different
tRP+tRAS is "minimum" , buut that switches away from 3xCAS-bef-RAS

For 3xCAS-bef-RAS , this topic needs deeper research








For this, i need more time. Started to learn about it ~ but while it was planned for DDR4 ~ it is only integrated in LPDDR4 and GDDR5 onwards
Soo hence b-die does simply not behave that way, it was low priority spending further time on this research

I can not confirm it also does tRFC pausing ~ as enabled feature
But this latency drop is a different selected refresh method , that for certain.

Oh right, Rev.E's do not fail till 1h into the loop
You have to test them longer 
1:30-2h seems fine

A new ~ ES 8gb one is in plan
Buut i like these ones. They scale very well with CAS ~ although not an usual behavior of b-dies










Veii said:


> For Micron kits, try to either keep it tRAS = tRCD+tRCD+6 (failsafe)
> or more correct
> 
> 
> 
> 
> 
> 
> 
> 
> Just CAS-bef-RAS refresh is used on DDR5 and LPDDR


It can be CAS+tRTP+tRCD_RD, or CAS+tCWL+tRTP
buut, the real name is 3xCAS-bef-RAS , as actual refresh method which "can" be decided into (by MSR) in realtime ~ up to timings // if supported by controller

Either i somehow utilize burst refresh, by accident or it is indeed this
I need more testing but example should've shown big latency differences, and about 5000-6000MB/s change (by shifting something 1tCK up or down)
We'll see 
I'm confident it's capable to use this refresh method ~ but i need to get my hands on whitepapers and check how micron PCB designs function.


----------



## Veii

The_King said:


> @Veii Any input on getting something like this stable on the Vipers will be greatly appreciated!



















If unstable, some other timing is unstable ~ tRRD, tWTR or something else
tRAS = tRP+tRCD on b-die
Or tRCD+tRTP , as absolute minimum value
you can try something stupid like this








But low timings are not always better 
tCKE 11, is for 4000 MT/s


----------



## The_King

Veii said:


> View attachment 2564244


That was when I got the kit new and did not know jack about OCing B-Die RAM. Hence the high VDDP/CCD/IOD 



Veii said:


> View attachment 2564239


I have 6 kits that have C9BLM ICs 4x(2X8GB) and 2x(2X16GB). Very easy to get GMD OFF 1T stable on these Kits without changing *DrvStr
The one below is Also C9BLM but its the only one that is Micron Rev B. The others are all Rev. E


----------



## PJVol

@Veii 
Hi! What's up with your google calculator?


----------



## Veii

PJVol said:


> @Veii
> Hi! What's up with your google calculator?


Mini is fine
Personal DRAM one was never published // No time, Navi21 takes my full time ~ later X3D , system is still fully offline
The google community one belonged to a korean "user" here - i miss him , haven't seen him


The_King said:


> The one below is Also C9BLM but its the only one that is Micron Rev B. The others are all Rev. E


Is it what you daily ?








Try~
need to get 26-26 in there
it will switch to 28-28 on overcurrent ~ protection
or to 26-28 on missmatch
26-26 then neeeds shifting of powering and stronger powering to get running


----------



## heptilion

Veii said:


> Any limiters will limit how much VID is requested on X load
> AGESA 1207 is different and annoying to some extend - but if you have to keep in mind, that hitting limiters will lower VID == will modify or mess up CO range
> 
> 
> 
> 
> 
> 
> 
> 
> 
> CPU SET voltage is the SKU range
> Latchup_voltage, or V_MAX is the fused sample ~ FIT range
> Throttle voltage, is hidden - but it's 1.4v for me
> usually 50mV lower than V_MAX
> 
> You will notice which one it is, soo i am not sure if AGESA 1205+ will limit this to 1.4 and keep 1.4v limit ~ matching throttle voltage with V_MAX
> Oor it still leaves that overshoot heatroom and a 1.45v cap means, that 1.35 will be the peak it allows
> 
> Depends, but i'm still questioning if i should upgrade
> especially since i've messed up my sensors and can't run HWInfo anymore (freezes on Ring-0 access, as sensorics are dead)
> Messed up with AMISCE & no CMOS reset fixes it , tho don't want to lose my profiles ~ whoops


This is what mine shows.










Ok so i have got this now on each CCD with boost tester. fmax at 0.









Can you confirm if my logic is correct? Since each core shares voltage between each other, does this mean if i go negative -8 on Core 0 on CCD1 which i know it is stable at and keep fmax at 0, this means it will run at 5050 using less voltage which allows other cores to have more voltage therfore i can use that to reduce CO and increase boost on CCD2?

Can that be used to increase my all core AVX2 boost? or is AVX is fixed? as in i know before i can only do -10 co for core 9 on avx2 occt large extreme variable. Can this be increased now to say -12 or somehting instead of -10?


----------



## The_King

Veii said:


> Mini is fine
> Personal DRAM one was never published // No time, Navi21 takes my full time ~ later X3D , system is still fully offline
> The google community one belonged to a korean "user" here - i miss him , haven't seen him
> 
> Is it what you daily ?
> 
> 
> 
> 
> 
> 
> 
> 
> Try~
> need to get 26-26 in there
> it will switch to 28-28 on overcurrent ~ protection
> or to 26-28 on missmatch
> 26-26 then neeeds shifting of powering and stronger powering to get running


The daily was 3800 CL14 with that kit. Similar to below, I did not screenshot the last tune I did with GDM disable 1T.









My current daily is a 4700S with GDDR6. If only I could tune this.









On another note seems my 5600X is also dual CCD like yours.


----------



## Frosted racquet

If it's a dual CCD shouldn't the memory write speed double as well?


----------



## The_King

Frosted racquet said:


> If it's a dual CCD shouldn't the memory write speed double as well?


Its has dual CCD/CCX but one is disable. Most likely a 5900X with one core disbaled. So performance similar to single CCD 5600x.

The only possible advantage is that the silicon is good. This CPU has no problem boosting over 5GHz with most of the cores. It can boost higher but im running an aircooler so did not push voltage. This OC was done for CPU-Z were i just broke 701ST. AMD Ryzen 5 5600X @ 4698.9 MHz - CPU-Z VALIDATOR


----------



## ioannis91

I just noticed that on XMP settings tPHYRDL are 26 and 24, shouldn't they both be the same? Doesn't matter so much as I only switched to XMP for some baseline metrics but still it's weird. Maybe a wrong reporting of zentimings?


----------



## DokGrej

Hello, for two weeks I have been wondering what else to improve with my RAM setting, namely Patriot Memory Viper STEEL PVS416G413C9K 4133 MHz CL19. The memories used are Samsung B-Die.
Currently I set up 3600MHz CL14 with the following tamings:














d


----------



## Valka814

Can you guys tell me, what settings should I try to improve the memory overclock?
Ballistic Sport LT 3200MHz CL16 kit
For 3800MHz, SoC voltage in bios set to 1.062V, for 3866MHz its needs 1.192V to be WHEA error free.
Thank you very much!


----------



## Blackfyre

Valka814 said:


> Can you guys tell me, what settings should I try to improve the memory overclock?
> Ballistic Sport LT 3200MHz CL16 kit
> For 3800MHz, SoC voltage in bios set to 1.062V, for 3866MHz its needs 1.192V to be WHEA error free.
> Thank you very much!
> View attachment 2564371


I think that's very good already for 3200Mhz stock.

I have Crucial Ballistix Gaming, 4x8GB (32Gb) DDR4 3600MT/s CL16, running at the below timings overclocked, but I need 1.520 vDIMM to achieve these timings. Most of your secondary timings are very close to mine even though yours is originally 3200Mhz.


----------



## Bloax

edit: I hope you're not actually running 1.1v VDDP for ddr4-3800 hehehe


Valka814 said:


> Can you guys tell me, what settings should I try to improve the memory overclock?
> Ballistic Sport LT 3200MHz CL16 kit
> For 3800MHz, SoC voltage in bios set to 1.062V, for 3866MHz its needs 1.192V to be WHEA error free.
> Thank you very much!
> View attachment 2564371


Veii was toying around with tRAS = 3x tCL, tRC = tRAS + tRP for Micron/Crucial DIMMs just the other page:
(how the tCL vs. tCWL balance affects it is still Unclear(tm), but it does )








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


I know this is the AMD topic, but do any of you know if any of the DDR4 690 boards are any good for OCing? No 2 DIMMs, so just wondering.




www.overclock.net





I don't know if tCKE 9 is relevant, and whether RTT & CADBus friends are going to translate from single-rank to dual-rank sticks.
Never tried these sticks!


----------



## Blackfyre

Bloax said:


> edit: I hope you're not actually running 1.1v VDDP for ddr4-3800 hehehe


I have CLDO VDDP @ 1.1v
CCD 0.95v
IOD 1.05v
vDIMM @ 1.52v

MEM VTT was 0.73 I believe, but I changed it to Auto. Not sure what my motherboard is setting it to on AUTO, but I haven't faced issues.


----------



## Valka814

Bloax said:


> edit: I hope you're not actually running 1.1v VDDP for ddr4-3800 hehehe
> 
> Veii was toying around with tRAS = 3x tCL, tRC = tRAS + tRP for Micron/Crucial DIMMs just the other page:
> (how the tCL vs. tCWL balance affects it is still Unclear(tm), but it does )
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> I know this is the AMD topic, but do any of you know if any of the DDR4 690 boards are any good for OCing? No 2 DIMMs, so just wondering.
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> I don't know if tCKE 9 is relevant, and whether RTT & CADBus friends are going to translate from single-rank to dual-rank sticks.
> Never tried these sticks!


Did a few Aida latency benchmark and the results were the same.


----------



## PJVol

Veii said:


> AGESA 1207 is different and annoying to some extend


I don't know did you try it with your 5600X, but I'd rather say it's utterly freaking out ))
Right after flashing 6/13/2022 update, I entered my usual PBO and RAM settings and got 4-5 reboots in a 10-15 min.
Running default limits didn't remove x3d VID limit, average clocks reported as 3900-ish (~10000 CBR23), regardless of what Fmax is.
Next reboot was the final straw, when I rolled back to 2.10 without delay.

The  worst and shortest experience with asrock beta-bios since the good old X370 taichi ))


----------



## ReyReverse

Valka814 said:


> Can you guys tell me, what settings should I try to improve the memory overclock?
> Ballistic Sport LT 3200MHz CL16 kit
> For 3800MHz, SoC voltage in bios set to 1.062V, for 3866MHz its needs 1.192V to be WHEA error free.
> Thank you very much!
> View attachment 2564371


micron E -83E
since you already run 1T disabled
your CWL - Primary Choice is tcwl 12 (2tCK is 14) 
if you set your tcwl to 12 you probably need to reamend tRDWR maybe 9,10 or 11
save and reboot go for the next

step 2 here
twtr_S=3
twrt_L=9
maybe need to add a bit voltage if the system is unstable 
save and test.


----------



## Valka814

ReyReverse said:


> micron E -83E
> since you already run 1T disabled
> your CWL - Primary Choice is tcwl 12 (2tCK is 14)
> if you set your tcwl to 12 you probably need to reamend tRDWR maybe 9,10 or 11
> save and reboot go for the next
> 
> step 2 here
> twtr_S=3
> twrt_L=9
> maybe need to add a bit voltage if the system is unstable
> save and test.


I feel dumb. 

What thats mean for me? "micron E -83E"
I know my ram is Micron E-die, but thats all.

Thats totally unclear: "your CWL - Primary Choice is tcwl 12 (2tCK is 14)"
tCWL is a sub timing, the only clear thing in this one.

I understand the rest.
Also, what Dram voltage I can go for max? The stick dont have extra cooling, just the case fans blowing air into the case. (5x 140mm in and 1 out, FD Meshifiy S2)

Thank you!


----------



## Yviena

Can i bypass PBO bug with PBOtuner on 1.2.0.7?


----------



## KedarWolf

Yviena said:


> Can i bypass PBO bug with PBOtuner on 1.2.0.7?


Yes, you can.


----------



## Valka814

Whats is the reason for Micron E-die, that some go for primaries like 16-19-10-16, instead of 16-19-19-19? More headroom for better subs and subs give more performance?
Thank you!


----------



## ReyReverse

Valka814 said:


> Thats totally unclear: "your CWL - Primary Choice is tcwl 12 (2tCK is 14)"
> tCWL is a sub timing, the only clear thing in this one.


Yes, it's tcwl is subtimings , I mean your best choice is twcl 12, next is 14

And you don't need to touch your dram voltage
unless if it unstable.
voltage over 1.5v or above only need to add additional active cooling
So below 1.5v it's safe


----------



## ReyReverse

Valka814 said:


> What thats mean for me? "micron E -83E"
> I know my ram is Micron E-die, but thats all.


83E is your speedbin no. (2400R cl 16)
Usually this bin can do CL 15, maybe you can try


----------



## ReyReverse

Valka814 said:


> Whats is the reason for Micron E-die, that some go for primaries like 16-19-10-16, instead of 16-19-19-19? More headroom for better subs and subs give more performance?
> Thank you!


I don't know what's the point trcdwr below tCL ", most of the performance gain is in the tertiary timings, not in the main ones. So I suggest you save voltage for push the subtimings use.


----------



## Veii

tRCDWR and voltage have zero connection on DDR4
tCWL is a virtual timing like tRC, inserted for efficiency

Faster write cycle compared to remain timings, is debatable
For some it's faster in results, for some it makes no sense
For me it makes no sense to split read and write operation
It's harder to time good efficiency. It's not hard to get stable hence write can happen instantly
Yet would not deny that lowering delay there can be beneficial for people who split them

tRCD is likely the only timing on DDR4 that has a key influence
RtW , WtoRead, delayed Reads (tRRD), delayed writes (tWTR),
all are management timings there to time simultaneous operation ~ and utilize full given bandwidth "better"

Bandwidth itself comes from efficiency of operation
Tertiaries can finetune, but not surpass main bottleneck of primaries
~you can increase main operation only as much till main operation itself becomes the bottleneck~
"A fat dog can not run faster with better shoes, if his legs are either too heavy or muscles too weak"

EDIT:
"But a heavy dog can utilize pauses longer to recover // oor run stop run stop ~ on too fast operation" *🤭*
What actually increases strain, are wasteful burst operations that start and end too early without a reason of happening
Voltage only supports primaries cell recharge time. Delay required for primaries are relative to SNR.
Voltage itself is relative and irrelevant as Amperage is what matters for dimms.
Amperage only matters in the realm of signal integrity and thermals influence discharge.

It's no silicon to fail on voltage ~ but the PCB will faster show weakness and nearby-trace EMI , on higher voltage
As electricity transfers magnetically & not on a straight line
Voltage also is not defining heat. Amperage is. A 1.65v preset can be colder than a 1.48v preset. It's relative and so is also SNR
Soo hence VDIMM is irrelevant ~ "saving on voltage" becomes irrelevant ~ but saving on strain makes sense.
Hence going for a bursty approach instead a balanced one is counterproductive and contradicts the actual reason of "saving voltage"


----------



## umea

anyone have experience with TUF GAMING X570 PLUS in 4x8 bdie config? friend is looking to upgrade ram + cpu, not sure if i should suggest him a 2x16 or 4x8 kit. 4x8 would be the viper 4000cl16 bin probably. 

i looked through the forums/this thread but didn't find much about it.


----------



## ReyReverse

of course tCL is still the priority thats why its primary timings
I mean "once hit the bottleneck" should save voltage to play with sub tertiary

trfc need bunch of voltage to push. from 130ns to 118 need addition 0.07v
if your vdimm already at 1.65v you got no more headroom to push tRFC

Im not gonna to put 1.72v on my ram for 24/7😅


----------



## Audioboxer

Veii said:


> tRCDWR and voltage have zero connection on DDR4
> tCWL is a virtual timing like tRC, inserted for efficiency
> 
> Faster write cycle compared to remain timings, is debatable
> For some it's faster in results, for some it makes no sense
> For me it makes no sense to split read and write operation
> It's harder to time good efficiency. It's not hard to get stable hence write can happen instantly
> Yet would not deny that lowering delay there can be beneficial for people who split them
> 
> tRCD is likely the only timing on DDR4 that has a key influence
> RtW , WtoRead, delayed Reads (tRRD), delayed writes (tWTR),
> all are management timings there to time simultaneous operation ~ and utilize full given bandwidth "better"
> 
> Bandwidth itself comes from efficiency of operation
> Tertiaries can finetune, but not surpass main bottleneck of primaries
> ~you can increase main operation only as much till main operation itself becomes the bottleneck~
> "A fat dog can not run faster with better shoes, if his legs are either too heavy or muscles too weak"
> 
> EDIT:
> "But a heavy dog can utilize pauses longer to recover // oor run stop run stop ~ on too fast operation" *🤭*
> What actually increases strain, are wasteful burst operations that start and end too early without a reason of happening
> Voltage only supports primaries cell recharge time. Delay required for primaries are relative to SNR.
> Voltage itself is relative and irrelevant as Amperage is what matters for dimms.
> Amperage only matters in the realm of signal integrity and thermals influence discharge.
> 
> It's no silicon to fail on voltage ~ but the PCB will faster show weakness and nearby-trace EMI , on higher voltage
> As electricity transfers magnetically & not on a straight line
> Voltage also is not defining heat. Amperage is. A 1.65v preset can be colder than a 1.48v preset. It's relative and so is also SNR
> Soo hence VDIMM is irrelevant ~ "saving on voltage" becomes irrelevant ~ but saving on strain makes sense.
> Hence going for a bursty approach instead a balanced one is counterproductive and contradicts the actual reason of "saving voltage"


My tRCDRD is a fat dog for not doing 13 at 3800 😂

Did you ever get any more dual rank kits to mess about with Veii?


----------



## DokGrej

DokGrej said:


> Hello, for two weeks I have been wondering what else to improve with my RAM setting, namely Patriot Memory Viper STEEL PVS416G413C9K 4133 MHz CL19. The memories used are Samsung B-Die.
> Currently I set up 3600MHz CL14 with the following tamings:
> View attachment 2564367
> View attachment 2564536
> d


Anyone have any suggestions on what can be changed? Currently set to 3600MHz CL14 with 1.5V


----------



## The_King

DokGrej said:


> Anyone have any suggestions on what can be changed? Currently set to 3600MHz CL14 with 1.5V


Not sure why your SCLs are 4 and 5. Both should be 4s.

TRFC/2/4 try 210/156/96

You can try to get GMD disabled 1T stable if you want better performance or give 3800 CL14/15 a go.


----------



## Veii

Audioboxer said:


> Did you ever get any more dual rank kits to mess about with Veii?


Yes'n
There is a white TF13D432G3600HC14CDC01 waiting for the X3D to be started. Which waits for a custom bios, and that waits for his watercooling parts to arrive
I'd say "soon" - but it can take 8-10 more weeks. And i have to end up Navi 21 reserch which is not even close to done
I don't use them right now ~ they are waiting for a system.
Tried them a bit, but my Aro-14 cooler is too big on the ITX system. They slightly bent the ram slots ~ soo i don't use them right now.
The Max also slightly bent them, but barely ~ the viper heatsinks are thin enough

Answer is ~ soon, but not yet


----------



## Veii

ReyReverse said:


> of course tCL is still the priority thats why its primary timings


tCAS and tRAS are equal in priority
in DDR4 Collumn Strobe finds faster it's collumn, while Row Strobe is missing some and needs time // often misses a row and looks again
Both together have high priority but highest has tRCD and tRP'
tRP scales by VDIMM, tRCD scales by signal integrity and cleanness

tRP is technically a written out "injected delay" slowed timing - to compensate for variable AL (added latency) before tRAS+RCD can happen
tRCD is copying data over from other columns in the same row (8x8 matrix field) to a non destroyed field- where tRAS then is sending an activate command to open up cells for read
Before read, sense io is checking wherever current of the cells in the row is high enough and likely it isn't soo AL is used to halt and recharge them to a full charge state
This AL is dynamic, soo user injects slow down delay as (p)recharge delay (tRP)
Only once tRP happened, tRAS command happens ~ usually it's not in this order, but everything happens at the very same time . Commands start, match rising clock do their work and perfectly end before the next command queue's

tRAS starts together with tRP ~ hence it's longer
But tRP has to happen close to always from reads to reads
Soo if let's say tRAS is lower, it will quit faster. If it quits too fast mid-tRP or generally mid auto-inserted delay . . . it gets halted
Everything gets halted soo dataloss is prevented. Only after basic upkeep functionality has maintained, tRAS happens.

The read of it, destroys everything in the row it accesses - but the information it wants, it already gets // nearby cells are discharged and empty
Things will copy back after time ~ but after RAS happened, tRP happens again to recharge things back in usable state and tRC ends ~ row cycle time. To another row
More commands happen at the same time but basically things recharge and copy back.

Now technically speaking, DDR4 allows a write to X row at any time it is free ~ well at any rising clock in this case
Soo writes can happen at the same time, and tRC by itself (cycle delay) is another "at the same time" running virtual command ~ that ends up exactly ending after tRP + tRAS
Hence if this command is too short ~ it gets repeated by it's full value
But unlike tRC ~ if tRAS ends too early, yet cells are recharged ... everything halts. Like on an tRFC recharge
If tRC ends to early, nothing happens writes can pass but reads are slowed. tRC get's repeated for data to maintain before next big read command
If tRC is too long on the other hand ~ things will wait for tRC to elapse and nothing can happen
(mostly, here i miss more information, but a fraction of things only are allowed at the same time to happen, the rest is halted)

Soo going back to remain approach
If you keep following what early XOCers build as "it's just that way" ~ the "lower is better" mentality. You will drown in rabbit holes full of autocorrection.
You won't notice an issue at all.
The same goes by following GDM. It is fast to some extend, but it hides soo much ~ and hinders the possibility of odd timings. Plus is still slower than pure 1T or 2T on odd lower timings.

A non bursty approach, is better ~ but sadly even buildzoid illustrates this from a different perspective
Every timing lower will improve something. But the efficiency is what matters.
Tertiary are important ~ but 2ndaries and tertiaries are usually too tight set & people don't notice why their tRCD can not go lower
You increase strain too much that way, instead of improving primaries which every command belongs to 

Higher tertiaries that allow tRCD to drop, are still a win
Low CAS on the other hand is not a win ~ not on b-die, it's just faster collumn find ~ but that is pretty much irrelevant, as tRCD and tRAS are slow
tRCD is pretty much the bottleneck of DDR4 // well and tRFC without tRFC pausing functionality
On DDR5 things get back symmetrical again ~ but i see XOC guys still market with tCAS ~ although CAS and RAS are now mirrors and all depends on tRCD (as it usually does)

EDIT:
Yet at the very end ~ tRCD will only drop, if your signal integrity is good and everything around it is good
This will not happen "by voltage" and will not happen if anything around it is already as tight as possible or constantly autocorrected
It will not happen without a lot of work on powering ~ which is where "voltage is irrelevant" comes from
it really is irrelevant, as it doesn't even indicate heat
Soo things like GDM ~ unless they improve signal integrity that much where tRCD can drop further ~ it's not useful 

EDIT2:
But usually like i did
Don't listen to theory too much ~ do your own research. Find your own exploits
Maybe you figure something out that is not typical JEDEC behavior.
Not every PCB Designer holds to JEDEC & every engineer improves something on their exclusive PCB design
Keep researching for exploits. I'm not going to be "thaat" person who trows around the holy book of jedec. 
Better to know less theory, soo you can be more creative~


ReyReverse said:


> Im not gonna to put 1.72v on my ram for 24/7😅


I do / did
Rev.E A2 PCB can hold it up - IC's can hold it up.
No crash = fine ~ degradation doesn't exist in memory ~ only heat instability

Samsung b-dies usually fail near 1.68-1.7v
Rev.E likes voltage, Hynix too ~ they don't have such an architectural issue.
But before all that, after 1.48v ~ dimm PCBs start to give up, then once again at 1.58v and so on
That is what people struggle with & "kill DIMMs"
~ ICs are perfectly fine near 1.7v, till you have to use maxmem ~ as you start to lose some ICs , they drop out on higher voltage but "can not die" 

1.66v b-die & 1.69v Rev.E without an active fan
Works well enough in an open testbench
Voltage is not heat and voltage is irrelevant ~ but you'll notice sooner or later
But will also be able to differenciate maxmem XOC guys with over 1.7v vs normal daily users. They can run lower timings, as there is simply "less to run"


----------



## Veii

Audioboxer said:


> My tRCDRD is a fat dog for not doing 13 at 3800 😂


Mine too, It's mood keeps changing ~ it's very picky how much voltage it wants to eat. Eats too much and it gets drowsy & barely wants to stand up. Only sleeps 








This was the best it could run but 3800 didn't want to
Although i found that longer CAS, allowed lower tRCDRD to "boot"








Buut it wasn't stable. Something was too low
Maybe tRP was too low. At least better "a boot" vs "no boot"








This slow "basic" preset, still serves it well
CAS 14 seems to be a nogo, although 4000 likes 14-flat and 4267 likes 15-flat
Didn't get any higher than 4267 yet. Other is 4600 17-flat. But that dog really is lying flat and lazy 😋
Would need 5000 19-flat, to be interesting on 2:1 , or 5400 Rev.E to offset penalty


----------



## Bloax

umea said:


> anyone have experience with TUF GAMING X570 PLUS in 4x8 bdie config? friend is looking to upgrade ram + cpu, not sure if i should suggest him a 2x16 or 4x8 kit. 4x8 would be the viper 4000cl16 bin probably.


I haven't done thorough testing, but the 4000 16-16-16 sticks don't seem to behave very well in the daisy-bad slots - if you want to run 4x8, I'd recommend two sets of viper 4400 19-19-19 sticks instead.

If this was an LGA1700 build I'd recommend 4400 sticks in the bad slots and the 4000c16 sticks in the good slots, as they run very well together so long as you set Park/6 (40 ohm) on slots A1B1 and Park/5 (48) on A0B0 (the "daisy-bad" slots)


----------



## Audioboxer

Veii said:


> Mine too, It's mood keeps changing ~ it's very picky how much voltage it wants to eat. Eats too much and it gets drowsy & barely wants to stand up. Only sleeps
> View attachment 2564591
> 
> This was the best it could run but 3800 didn't want to
> Although i found that longer CAS, allowed lower tRCDRD to "boot"
> View attachment 2564592
> 
> Buut it wasn't stable. Something was too low
> Maybe tRP was too low. At least better "a boot" vs "no boot"
> View attachment 2564594
> 
> This slow "basic" preset, still serves it well
> CAS 14 seems to be a nogo, although 4000 likes 14-flat and 4267 likes 15-flat
> Didn't get any higher than 4267 yet. Other is 4600 17-flat. But that dog really is lying flat and lazy 😋
> Would need 5000 19-flat, to be interesting on 2:1 , or 5400 Rev.E to offset penalty


3766 is the best I can do with tRCDRD 13. I used BCLK overclocking to see where things start to fail and it's in 377x, so it's not even that close to 3800.


----------



## DukeRaoul2010

Veii said:


> tCAS and tRAS are equal in priority
> in DDR4 Collumn Strobe finds faster it's collumn, while Row Strobe is missing some and needs time // often misses a row and looks again
> Both together have high priority but highest has tRCD and tRP'
> tRP scales by VDIMM, tRCD scales by signal integrity and cleanness
> 
> tRP is technically a written out "injected delay" slowed timing - to compensate for variable AL (added latency) before tRAS+RCD can happen
> tRCD is copying data over from other columns in the same row (8x8 matrix field) to a non destroyed field- where tRAS then is sending an activate command to open up cells for read
> Before read, sense io is checking wherever current of the cells in the row is high enough and likely it isn't soo AL is used to halt and recharge them to a full charge state
> This AL is dynamic, soo user injects slow down delay as (p)recharge delay (tRP)
> Only once tRP happened, tRAS command happens ~ usually it's not in this order, but everything happens at the very same time . Commands start, match rising clock do their work and perfectly end before the next command queue's
> 
> tRAS starts together with tRP ~ hence it's longer
> But tRP has to happen close to always from reads to reads
> Soo if let's say tRAS is lower, it will quit faster. If it quits too fast mid-tRP or generally mid auto-inserted delay . . . it gets halted
> Everything gets halted soo dataloss is prevented. Only after basic upkeep functionality has maintained, tRAS happens.
> 
> The read of it, destroys everything in the row it accesses - but the information it wants, it already gets // nearby cells are discharged and empty
> Things will copy back after time ~ but after RAS happened, tRP happens again to recharge things back in usable state and tRC ends ~ row cycle time. To another row
> More commands happen at the same time but basically things recharge and copy back.
> 
> Now technically speaking, DDR4 allows a write to X row at any time it is free ~ well at any rising clock in this case
> Soo writes can happen at the same time, and tRC by itself (cycle delay) is another "at the same time" running virtual command ~ that ends up exactly ending after tRP + tRAS
> Hence if this command is too short ~ it gets repeated by it's full value
> But unlike tRC ~ if tRAS ends too early, yet cells are recharged ... everything halts. Like on an tRFC recharge
> If tRC ends to early, nothing happens writes can pass but reads are slowed. tRC get's repeated for data to maintain before next big read command
> If tRC is too long on the other hand ~ things will wait for tRC to elapse and nothing can happen
> (mostly, here i miss more information, but a fraction of things only are allowed at the same time to happen, the rest is halted)
> 
> Soo going back to remain approach
> If you keep following what early XOCers build as "it's just that way" ~ the "lower is better" mentality. You will drown in rabbit holes full of autocorrection.
> You won't notice an issue at all.
> The same goes by following GDM. It is fast to some extend, but it hides soo much ~ and hinders the possibility of odd timings. Plus is still slower than pure 1T or 2T on odd lower timings.
> 
> A non bursty approach, is better ~ but sadly even buildzoid illustrates this from a different perspective
> Every timing lower will improve something. But the efficiency is what matters.
> Tertiary are important ~ but 2ndaries and tertiaries are usually too tight set & people don't notice why their tRCD can not go lower
> You increase strain too much that way, instead of improving primaries which every command belongs to
> 
> Higher tertiaries that allow tRCD to drop, are still a win
> Low CAS on the other hand is not a win ~ not on b-die, it's just faster collumn find ~ but that is pretty much irrelevant, as tRCD and tRAS are slow
> tRCD is pretty much the bottleneck of DDR4 // well and tRFC without tRFC pausing functionality
> On DDR5 things get back symmetrical again ~ but i see XOC guys still market with tCAS ~ although CAS and RAS are now mirrors and all depends on tRCD (as it usually does)
> 
> EDIT:
> Yet at the very end ~ tRCD will only drop, if your signal integrity is good and everything around it is good
> This will not happen "by voltage" and will not happen if anything around it is already as tight as possible or constantly autocorrected
> It will not happen without a lot of work on powering ~ which is where "voltage is irrelevant" comes from
> it really is irrelevant, as it doesn't even indicate heat
> Soo things like GDM ~ unless they improve signal integrity that much where tRCD can drop further ~ it's not useful
> 
> EDIT2:
> But usually like i did
> Don't listen to theory too much ~ do your own research. Find your own exploits
> Maybe you figure something out that is not typical JEDEC behavior.
> Not every PCB Designer holds to JEDEC & every engineer improves something on their exclusive PCB design
> Keep researching for exploits. I'm not going to be "thaat" person who trows around the holy book of jedec.
> Better to know less theory, soo you can be more creative~
> 
> I do / did
> Rev.E A2 PCB can hold it up - IC's can hold it up.
> No crash = fine ~ degradation doesn't exist in memory ~ only heat instability
> 
> Samsung b-dies usually fail near 1.68-1.7v
> Rev.E likes voltage, Hynix too ~ they don't have such an architectural issue.
> But before all that, after 1.48v ~ dimm PCBs start to give up, then once again at 1.58v and so on
> That is what people struggle with & "kill DIMMs"
> ~ ICs are perfectly fine near 1.7v, till you have to use maxmem ~ as you start to lose some ICs , they drop out on higher voltage but "can not die"
> 
> 1.66v b-die & 1.69v Rev.E without an active fan
> Works well enough in an open testbench
> Voltage is not heat and voltage is irrelevant ~ but you'll notice sooner or later
> But will also be able to differenciate maxmem XOC guys with over 1.7v vs normal daily users. They can run lower timings, as there is simply "less to run"


Veii - without wanting everything on a plate it would be great to be able to get a post with your methodology - i'd love to try to push my DDR4 further...

Here's where i am now Vdimm is 1.5v


----------



## PJVol

@Veii @Blameless
Have you guys already tried RM CLI binary in action (courtesy of ASRock - I certainly do like them  ) from a mb utility package?
I tested the one from .466 build and all works fine. I even managed to launch rm service (successfully) on the MSI B450 platform (installation failed of course, but nothing prevents the service to run standalone on any modern platform, e.g. just replace that from the rm installation, as long as both are signed)
Good practice for inquisitive (and a bit lazy) newbies, as everything you need is already out there, isn't it? )



Spoiler: Full API list



(some getters moved to GetPMTableData)


Bash:


-----------------------------------------------------------
| Func |    Supported                  |   Number of  |
| Index|    Functions                  |   arguments  |
-----------------------------------------------------------
    1     GetBaseFamily                        0
    2     GetExtendedFamily                    0
    3     GetFamily                            0
    4     GetBaseModel                         0
    5     GetExtendedModel                     0
    6     GetStepping                          0
    7     GetModel                             0
    8     GetPackage                           0
    9     GetRevision                          0
   10     GetInstructionSets                   0
   11     GetCurrentFrequency                  0
   12     GetEffectiveFrequency                0
   13     GetL1DataCache                       0
   14     GetL1InstructionCache                0
   15     GetL2Cache                           0
   16     GetL3Cache                           0
   17     GetCurrentFID                        1
   18     GetCurrentDID                        1
   19     GetCurrentVIDIndex                   1
   20     GetCurrentPState                     0
   21     GetCorePark                          0
   22     GetPstateMaxVal                      0
   23     GetCurPstateLimit                    0
   24     GetFrequencybyFID                    2
   25     GetFrequencybyDID                    2
   26     GetName                              0
   27     GetDescription                       0
   28     GetVendor                            0
   29     GetRole                              0
   30     GetClassName                         0
   31     GetType                              0
   32     GetIndex                             0
   33     GetCurrentVoltage                    1
   34     GetVoltagebyVID                      1
   35     GetVIDbyVoltage                      1
   36     GetMemVDDIO                          0
   37     GetCurrentMemClock                   0
   38     GetMemCtrlTcl                        0
   39     GetMemCtrlTrcdrd                     0
   40     GetMemCtrlTrcdwr                     0
   41     GetMemCtrlTras                       0
   42     GetMemCtrlTrp                        0
   43     GetMemVTT                            0
   44     GetVDDCR_SOC                         0
   45     GetCurrentTemperature                0
   46     GetCoreCount                         0
   47     GetCurrentHwFID                      0
   48     GetCurrentHwDID                      0
   49     GetCurrentHwVID                      0
   50     GetAllInfo                           0
   51     GetFIDbyFrequency                    2
   52     GetMinMaxStepBuffer                  1
   53     GetMemCtrlTrc                        0
   54     GetMemCtrlProcODT                    0
   55     GetMemCtrlTcwl                       0
   56     IsOverClockable                      0
   57     IsSMTEnabled                         0
   58     IsTSCPatchApplied                    0
   59     GetCPUOCBiosLimits                   0
   60     GetFIDDIDStockValues                 0
   61     IsSMTToggleAvailable                 0
   62     IsDisableProcHOTAvailable            0
   63     GetMemoryInterleaveMode              0
   64     GetBIOSInfo                          0
   65     GetPerformanceOfCore                 1
   66     GetFusedMOCStatus                    0
   67     GetFusedEDCLimit                     0
   68     GetFusedTDCLimit                     0
   69     GetFusedcHTCLimit                    0
   70     GetFusedPPTLimit                     0
   71     GetBoardPassedLimits                 0
   72     GetCurrentOCMode                     0
   73     GetPowerMonitorDetails               0
   74     GetCurrentGfxClock                   0
   75     GetMaxGfxClock                       0
   76     GetMinGfxClock                       0
   77     IsGfxOverclockingSupported           0
   78     GetFastestCoreofSocket               0
   79     GetPBOScalarStatus                   0
   80     IsPBOSupported                       0
   81     GetMemCtrlTrfc                       0
   82     GetMemCtrlTrfc2                      0
   83     GetMemCtrlTrfc4                      0
   84     GetMemCtrlTfaw                       0
   85     GetMemCtrlTrrdS                      0
   86     GetMemCtrlTrrdL                      0
   87     GetMemCtrlTwr                        0
   88     GetMemCtrlTwtrS                      0
   89     GetMemCtrlTwtrL                      0
   90     GetMemCtrlTCke                       0
   91     GetMemCtrlTrtp                       0
   92     GetMemCtrlTrdrdSc                    0
   93     GetMemCtrlTrdrdScL                   0
   94     GetMemCtrlTrdrdSd                    0
   95     GetMemCtrlTrcpage                    0
   96     GetMemCtrlTrdrdDd                    0
   97     GetMemCtrlTwrwrSc                    0
   98     GetMemCtrlTwrwrScL                   0
   99     GetMemCtrlTwrwrSd                    0
  100     GetMemCtrlTwrwrDd                    0
  101     GetMemCtrlTrdwr                      0
  102     GetMemCtrlTwrrd                      0
  103     GetDRAMControllerConfig              0
  104     GetMemCtrlRttNom                     0
  105     GetMemCtrlRttWR                      0
  106     GetMemCtrlRttPark                    0
  107     GetMemCtrlCkeSetup                   0
  108     GetMemCtrlCadBusClkDrvStren          0
  109     GetMemCtrlCadBusAddrCmdDrvStren      0
  110     GetMemCtrlCadBusCsOdtCmdDrvStren     0
  111     GetMemCtrlCadBusCkeDrvStren          0
  112     GetMemCtrlAddrCmdSetup               0
  113     GetMemCtrlCsOdtSetup                 0
  114     GetMaxCClk                           0
  115     GetMemInfo                           0
  116     GetEcoModeStatus                     0
  117     GetMemVPP                            0
  118     GetPMTableData                       0
  119     GetNPSMode                           0
  120     GetGamingMode                        0
  121     GetCPPCPerformanceRankings           0
  122     GetAPUOCBiosLimits                   0
  123     GetChipsetName                       0
  124     GetCurveOptimizerStatus              0
  125     DisablePROCHOT                       0
  126     EnableDisableSMT                     1
  127     SetMemVDDIO                          1
  128     SetCurrentDID                        2
  129     SetCurrentFID                        2
  130     SetCurrentVIDIndex                   2
  131     SetCorePark                          1
  132     SetCurrentVoltage                    2
  133     SetMemVTT                            1
  134     SetCurrentMemClock                   1
  135     SetVDDCR_SOC                         1
  136     SetCurrentPState                     1
  137     SetMemCtrlTcl                        1
  138     SetMemCtrlTrcdrd                     1
  139     SetMemCtrlTrcdwr                     1
  140     SetMemCtrlTras                       1
  141     SetMemCtrlTrp                        1
  142     SetMemCtrlTrc                        1
  143     SetMemCtrlProcODT                    1
  144     SetMemCtrlTcwl                       1
  145     SetOverclockCPUVoltage               1
  146     SetMemoryInterleaveMode              1
  147     SetOverclockFreqAllCores             1
  148     SetOverclockFreqPerCore              4
  149     SetcHTCLimit                         1
  150     SetGfxClock                          2
  151     SetSOCVoltage                        1
  152     SetPPTLimit                          1
  153     SetEDClimit                          1
  154     SetTDCLimit                          1
  155     EnableDisablePBOScalar               1
  156     SetEDCVDDLimit                       1
  157     SetEDCSOCLimit                       1
  158     SetTDCVDDLimit                       1
  159     SetTDCSOCLimit                       1
  160     SetMemCtrlTrfc                       1
  161     SetMemCtrlTrfc2                      1
  162     SetMemCtrlTrfc4                      1
  163     SetMemCtrlTfaw                       1
  164     SetMemCtrlTrrdS                      1
  165     SetMemCtrlTrrdL                      1
  166     SetMemCtrlTwr                        1
  167     SetMemCtrlTwtrS                      1
  168     SetMemCtrlTwtrL                      1
  169     SetMemCtrlTCke                       1
  170     SetMemCtrlTrtp                       1
  171     SetMemCtrlTrdrdSc                    1
  172     SetMemCtrlTrdrdScL                   1
  173     SetMemCtrlTrdrdSd                    1
  174     SetMemCtrlTrcpage                    1
  175     SetMemCtrlTrdrdDd                    1
  176     SetMemCtrlTwrwrSc                    1
  177     SetMemCtrlTwrwrScL                   1
  178     SetMemCtrlTwrwrSd                    1
  179     SetMemCtrlTwrwrDd                    1
  180     SetMemCtrlTrdwr                      1
  181     SetMemCtrlTwrrd                      1
  182     SetDRAMControllerConfig              2
  183     SetMemCtrlRttNom                     1
  184     SetMemCtrlRttWR                      1
  185     SetMemCtrlRttPark                    1
  186     SetMemCtrlCkeSetup                   1
  187     SetMemCtrlCadBusClkDrvStren          1
  188     SetMemCtrlCadBusAddrCmdDrvStren      1
  189     SetMemCtrlCadBusCsOdtCmdDrvStren     1
  190     SetMemCtrlCadBusCkeDrvStren          1
  191     SetMemCtrlAddrCmdSetup               1
  192     SetMemCtrlCsOdtSetup                 1
  193     SetAutoOverClockCPU_BIOS             1
  194     SetAutoOverClockGPU_BIOS             1
  195     SetCLDO_VDDP                         1
  196     DisableOverclocking                  0
  197     SetCLDO_VDDG                         1
  198     SetFabricClock                       1
  199     SetEcoMode                           1
  200     SetMemVPP                            1
  201     SetEDCLimit_BIOS                     1
  202     SetTDCLimit_BIOS                     1
  203     SetPPTLimit_BIOS                     1
  204     EnableDisablePBOScalar_BIOS          1
  205     SetNPSMode                           1
  206     SetGamingMode                        1
  207     SetEDCSOCLimit_BIOS                  1
  208     SetTDCSOCLimit_BIOS                  1
  209     SetCLDO_VDDG_IOD                     1
  210     SetCurveOptimizerForAllCores         1
  211     SetCurveOptimizerForEachCore         3
  212     SetCurveOptimizerBIOS                3


----------



## Blameless

PJVol said:


> @Veii @Blameless
> Have you guys already tried RM CLI binary in action (courtesy of ASRock - I certainly do like them  ) from a mb utility package?
> I tested the one from .466 build and all works fine. I even managed to launch rm service (successfully) on the MSI B450 platform (installation failed of course, but nothing prevents the service to run standalone on any modern platform, e.g. just replace that from the rm installation, as long as both are signed)
> Good practice for inquisitive (and a bit lazy) newbies, as everything you need is already out there, isn't it? )
> 
> 
> 
> Spoiler: Full API list
> 
> 
> 
> (some getters moved to GetPMTableData)
> 
> 
> Bash:
> 
> 
> -----------------------------------------------------------
> | Func |    Supported                  |   Number of  |
> | Index|    Functions                  |   arguments  |
> -----------------------------------------------------------
> 1     GetBaseFamily                        0
> 2     GetExtendedFamily                    0
> 3     GetFamily                            0
> 4     GetBaseModel                         0
> 5     GetExtendedModel                     0
> 6     GetStepping                          0
> 7     GetModel                             0
> 8     GetPackage                           0
> 9     GetRevision                          0
> 10     GetInstructionSets                   0
> 11     GetCurrentFrequency                  0
> 12     GetEffectiveFrequency                0
> 13     GetL1DataCache                       0
> 14     GetL1InstructionCache                0
> 15     GetL2Cache                           0
> 16     GetL3Cache                           0
> 17     GetCurrentFID                        1
> 18     GetCurrentDID                        1
> 19     GetCurrentVIDIndex                   1
> 20     GetCurrentPState                     0
> 21     GetCorePark                          0
> 22     GetPstateMaxVal                      0
> 23     GetCurPstateLimit                    0
> 24     GetFrequencybyFID                    2
> 25     GetFrequencybyDID                    2
> 26     GetName                              0
> 27     GetDescription                       0
> 28     GetVendor                            0
> 29     GetRole                              0
> 30     GetClassName                         0
> 31     GetType                              0
> 32     GetIndex                             0
> 33     GetCurrentVoltage                    1
> 34     GetVoltagebyVID                      1
> 35     GetVIDbyVoltage                      1
> 36     GetMemVDDIO                          0
> 37     GetCurrentMemClock                   0
> 38     GetMemCtrlTcl                        0
> 39     GetMemCtrlTrcdrd                     0
> 40     GetMemCtrlTrcdwr                     0
> 41     GetMemCtrlTras                       0
> 42     GetMemCtrlTrp                        0
> 43     GetMemVTT                            0
> 44     GetVDDCR_SOC                         0
> 45     GetCurrentTemperature                0
> 46     GetCoreCount                         0
> 47     GetCurrentHwFID                      0
> 48     GetCurrentHwDID                      0
> 49     GetCurrentHwVID                      0
> 50     GetAllInfo                           0
> 51     GetFIDbyFrequency                    2
> 52     GetMinMaxStepBuffer                  1
> 53     GetMemCtrlTrc                        0
> 54     GetMemCtrlProcODT                    0
> 55     GetMemCtrlTcwl                       0
> 56     IsOverClockable                      0
> 57     IsSMTEnabled                         0
> 58     IsTSCPatchApplied                    0
> 59     GetCPUOCBiosLimits                   0
> 60     GetFIDDIDStockValues                 0
> 61     IsSMTToggleAvailable                 0
> 62     IsDisableProcHOTAvailable            0
> 63     GetMemoryInterleaveMode              0
> 64     GetBIOSInfo                          0
> 65     GetPerformanceOfCore                 1
> 66     GetFusedMOCStatus                    0
> 67     GetFusedEDCLimit                     0
> 68     GetFusedTDCLimit                     0
> 69     GetFusedcHTCLimit                    0
> 70     GetFusedPPTLimit                     0
> 71     GetBoardPassedLimits                 0
> 72     GetCurrentOCMode                     0
> 73     GetPowerMonitorDetails               0
> 74     GetCurrentGfxClock                   0
> 75     GetMaxGfxClock                       0
> 76     GetMinGfxClock                       0
> 77     IsGfxOverclockingSupported           0
> 78     GetFastestCoreofSocket               0
> 79     GetPBOScalarStatus                   0
> 80     IsPBOSupported                       0
> 81     GetMemCtrlTrfc                       0
> 82     GetMemCtrlTrfc2                      0
> 83     GetMemCtrlTrfc4                      0
> 84     GetMemCtrlTfaw                       0
> 85     GetMemCtrlTrrdS                      0
> 86     GetMemCtrlTrrdL                      0
> 87     GetMemCtrlTwr                        0
> 88     GetMemCtrlTwtrS                      0
> 89     GetMemCtrlTwtrL                      0
> 90     GetMemCtrlTCke                       0
> 91     GetMemCtrlTrtp                       0
> 92     GetMemCtrlTrdrdSc                    0
> 93     GetMemCtrlTrdrdScL                   0
> 94     GetMemCtrlTrdrdSd                    0
> 95     GetMemCtrlTrcpage                    0
> 96     GetMemCtrlTrdrdDd                    0
> 97     GetMemCtrlTwrwrSc                    0
> 98     GetMemCtrlTwrwrScL                   0
> 99     GetMemCtrlTwrwrSd                    0
> 100     GetMemCtrlTwrwrDd                    0
> 101     GetMemCtrlTrdwr                      0
> 102     GetMemCtrlTwrrd                      0
> 103     GetDRAMControllerConfig              0
> 104     GetMemCtrlRttNom                     0
> 105     GetMemCtrlRttWR                      0
> 106     GetMemCtrlRttPark                    0
> 107     GetMemCtrlCkeSetup                   0
> 108     GetMemCtrlCadBusClkDrvStren          0
> 109     GetMemCtrlCadBusAddrCmdDrvStren      0
> 110     GetMemCtrlCadBusCsOdtCmdDrvStren     0
> 111     GetMemCtrlCadBusCkeDrvStren          0
> 112     GetMemCtrlAddrCmdSetup               0
> 113     GetMemCtrlCsOdtSetup                 0
> 114     GetMaxCClk                           0
> 115     GetMemInfo                           0
> 116     GetEcoModeStatus                     0
> 117     GetMemVPP                            0
> 118     GetPMTableData                       0
> 119     GetNPSMode                           0
> 120     GetGamingMode                        0
> 121     GetCPPCPerformanceRankings           0
> 122     GetAPUOCBiosLimits                   0
> 123     GetChipsetName                       0
> 124     GetCurveOptimizerStatus              0
> 125     DisablePROCHOT                       0
> 126     EnableDisableSMT                     1
> 127     SetMemVDDIO                          1
> 128     SetCurrentDID                        2
> 129     SetCurrentFID                        2
> 130     SetCurrentVIDIndex                   2
> 131     SetCorePark                          1
> 132     SetCurrentVoltage                    2
> 133     SetMemVTT                            1
> 134     SetCurrentMemClock                   1
> 135     SetVDDCR_SOC                         1
> 136     SetCurrentPState                     1
> 137     SetMemCtrlTcl                        1
> 138     SetMemCtrlTrcdrd                     1
> 139     SetMemCtrlTrcdwr                     1
> 140     SetMemCtrlTras                       1
> 141     SetMemCtrlTrp                        1
> 142     SetMemCtrlTrc                        1
> 143     SetMemCtrlProcODT                    1
> 144     SetMemCtrlTcwl                       1
> 145     SetOverclockCPUVoltage               1
> 146     SetMemoryInterleaveMode              1
> 147     SetOverclockFreqAllCores             1
> 148     SetOverclockFreqPerCore              4
> 149     SetcHTCLimit                         1
> 150     SetGfxClock                          2
> 151     SetSOCVoltage                        1
> 152     SetPPTLimit                          1
> 153     SetEDClimit                          1
> 154     SetTDCLimit                          1
> 155     EnableDisablePBOScalar               1
> 156     SetEDCVDDLimit                       1
> 157     SetEDCSOCLimit                       1
> 158     SetTDCVDDLimit                       1
> 159     SetTDCSOCLimit                       1
> 160     SetMemCtrlTrfc                       1
> 161     SetMemCtrlTrfc2                      1
> 162     SetMemCtrlTrfc4                      1
> 163     SetMemCtrlTfaw                       1
> 164     SetMemCtrlTrrdS                      1
> 165     SetMemCtrlTrrdL                      1
> 166     SetMemCtrlTwr                        1
> 167     SetMemCtrlTwtrS                      1
> 168     SetMemCtrlTwtrL                      1
> 169     SetMemCtrlTCke                       1
> 170     SetMemCtrlTrtp                       1
> 171     SetMemCtrlTrdrdSc                    1
> 172     SetMemCtrlTrdrdScL                   1
> 173     SetMemCtrlTrdrdSd                    1
> 174     SetMemCtrlTrcpage                    1
> 175     SetMemCtrlTrdrdDd                    1
> 176     SetMemCtrlTwrwrSc                    1
> 177     SetMemCtrlTwrwrScL                   1
> 178     SetMemCtrlTwrwrSd                    1
> 179     SetMemCtrlTwrwrDd                    1
> 180     SetMemCtrlTrdwr                      1
> 181     SetMemCtrlTwrrd                      1
> 182     SetDRAMControllerConfig              2
> 183     SetMemCtrlRttNom                     1
> 184     SetMemCtrlRttWR                      1
> 185     SetMemCtrlRttPark                    1
> 186     SetMemCtrlCkeSetup                   1
> 187     SetMemCtrlCadBusClkDrvStren          1
> 188     SetMemCtrlCadBusAddrCmdDrvStren      1
> 189     SetMemCtrlCadBusCsOdtCmdDrvStren     1
> 190     SetMemCtrlCadBusCkeDrvStren          1
> 191     SetMemCtrlAddrCmdSetup               1
> 192     SetMemCtrlCsOdtSetup                 1
> 193     SetAutoOverClockCPU_BIOS             1
> 194     SetAutoOverClockGPU_BIOS             1
> 195     SetCLDO_VDDP                         1
> 196     DisableOverclocking                  0
> 197     SetCLDO_VDDG                         1
> 198     SetFabricClock                       1
> 199     SetEcoMode                           1
> 200     SetMemVPP                            1
> 201     SetEDCLimit_BIOS                     1
> 202     SetTDCLimit_BIOS                     1
> 203     SetPPTLimit_BIOS                     1
> 204     EnableDisablePBOScalar_BIOS          1
> 205     SetNPSMode                           1
> 206     SetGamingMode                        1
> 207     SetEDCSOCLimit_BIOS                  1
> 208     SetTDCSOCLimit_BIOS                  1
> 209     SetCLDO_VDDG_IOD                     1
> 210     SetCurveOptimizerForAllCores         1
> 211     SetCurveOptimizerForEachCore         3
> 212     SetCurveOptimizerBIOS                3


Haven't tried it yet myself, but it looks promising.

Will check it out when I get a chance.


----------



## KedarWolf

DukeRaoul2010 said:


> Veii - without wanting everything on a plate it would be great to be able to get a post with your methodology - i'd love to try to push my DDR4 further...
> 
> Here's where i am now Vdimm is 1.5v


tCWL 14 tRDWR 8 tWRRD 3 a bit better for me in AIDA and y-cruncher than tCWL 12 tRDWR 10 tWRRD 1.

Plus my RAM is stable at tRFC 240, need 252 for tCWL 12.


----------



## Veii

DukeRaoul2010 said:


> would be great to be able to get a post with your methodology


I don't understand

GDM does bother


----------



## Valka814

Simple question. Dual rank memory have higher latency in Aida than single rank?
Thanks!


----------



## mnathani98

Hey folks! Need some advice on how to lower tRAS and tRC. VDIMM is at 1.55v (with a 120mm fan on top of the GPU) and stable. Tried tRCD + tRTP for tRAS but wasn't stable. Should i lower it a tick at a time and see where it settles? Also couldn't get 1T GDM Off stable so any suggestions on that would be really helpful as well.


----------



## The_King

mnathani98 said:


> Hey folks! Need some advice on how to lower tRAS and tRC. VDIMM is at 1.55v (with a 120mm fan on top of the GPU) and stable. Tried tRCD + tRTP for tRAS but wasn't stable. Should i lower it a tick at a time and see where it settles? Also couldn't get 1T GDM Off stable so any suggestions on that would be really helpful as well.
> 
> 
> View attachment 2564707


For 1T you can use AddrCmd 56
Or change *DrvStr to 40/20/30/24 or 40/20/30/20


----------



## mnathani98

The_King said:


> For 1T you can use AddrCmd 56
> Or change *DrvStr to 40/20/30/24 or 40/20/30/20


I did try those drive strengths at some point if i recall correctly but didn't try AddrCmd 56. Will give it a shot and see how it turns out. Also i can do higher FCLK under 1.2v (1933 and 1966) but for some reason when i enable PBO and run OCCT AVX2 stress test i get WHEAs which i don't get at stock. Is that normal behaviour or should i bump something up? (Higher FCLK require VDDP at 1v and VDDG at 1.05 and had set SOC to 1.1875v)


----------



## The_King

mnathani98 said:


> I did try those drive strengths at some point if i recall correctly but didn't try AddrCmd 56. Will give it a shot and see how it turns out. Also i can do higher FCLK under 1.2v (1933 and 1966) but for some reason when i enable PBO and run OCCT AVX2 stress test i get WHEAs which i don't get at stock. Is that normal behaviour or should i bump something up? (Higher FCLK require VDDP at 1v and VDDG at 1.05 and had set SOC to 1.1875v)


Go through this thread @Bloax gives some good info on the Vipers.








Any difference between Patriot Viper Steel 4000 and 4400...


Has the title says is there any other difference between : Patriot Viper Steel Series DDR4 16GB (2 x 8GB) 4400MHz Performance Memory Kit (PVS416G440C9K) https://www.amazon.in/gp/product/B07KXLFDL6/ref=ox_sc_saved_title_10?smid=A14CZOWI0VEHLG&psc=1 Patriot Memory Viper Steel DDR4 16GB (2 x...




www.overclock.net


----------



## Fturkut

Hello,

I have DJR chipset. I want to use my 4000 mhz cl 18 ram as 3800 CL 16, but I can't get the right settings because I have no knowledge. Motherboard Asus B550-MA WIFI
Processor R5 5600x


----------



## Taraquin

Fturkut said:


> Hello,
> 
> I have DJR chipset. I want to use my 4000 mhz cl 18 ram as 3800 CL 16, but I can't get the right settings because I have no knowledge. Motherboard Asus B550-MA WIFI
> Processor R5 5600x
> 
> View attachment 2564715


You are running unsynced, make mclk=fclk=uclk. I would try 3800\1900 instead, you probably get a lot of WHEA19 at 4000 and you probably need to adjust VDD18 voltage etc to avoid performance loss.
For 3800 and synced:
Try 1.5V
Soc 1.15v
Iod 1.05v
ccd 1.0v
vddp 0.9v

CL 16
RCDs 19
RP 19
RAS 32
RC 51
RRDS 4
RRDL 6
FAW 16
WTRS 4
WTRL 12 (8 may work, try if 12 works)
RFC 520 (as low as 460 may work, try 10 and 10 lower and see how far you get)
RDRDSCL 4
WRWRSCL 4
CWL 16
RDWR 8 or 9
WRRD 1


----------



## ReyReverse

mnathani98 said:


> Hey folks! Need some advice on how to lower tRAS and tRC. VDIMM is at 1.55v (with a 120mm fan on top of the GPU) and stable. Tried tRCD + tRTP for tRAS but wasn't stable. Should i lower it a tick at a time and see where it settles? Also couldn't get 1T GDM Off stable so any suggestions on that would be really helpful as well.
> 
> 
> View attachment 2564707


not sure whats your Agesa version
If 1T 
RTT 
ProcODT 36.9ohm allow you - disable/ off /RZQ 5 (default)
if you go 28.2ohm , benefit is allow cldo vddp run below 900 
but you probably need to retune your RTT
I don't know whats your comfortable value RTT park and rtt nom
but RTT Wr should be always RZQ/3

then next
you can try ClkDrvStr 
40/20/30/20 or
40/20/30/24
if still unstable
last try 60/20/30/20 or 60/20/30/24 

tips
there's not compulsory to go 1T 
if you feel 2T its stable
just stay at 2T if you don't mind that few hundred Read/Writes bandwidth and the latency 0.1~0.2ns different.

if you really wants to go 1T you probably need to retune many thing.
Primary timings go flat is an idea
then sub
try trrds/trrdl/tfaw/x4 x8 x16 mode
trfc /twtrs /twtrl 
trfc is abit messy, it related to trc trtp
vdimm straight put 1.62v
then reduce step by step till it unstable.

and another tip for 2T
if 2T
ProcODT 28.2 ohm
try ClkDrvStr 
30/20/30/20 or 30/20/30/24



and another tip for 1T disable 56-0-0
your CsOdtDrvStr probably don't need 30
I think 20/24 should be fine. or maybe Im wrong?
good luck


----------



## mnathani98

ReyReverse said:


> not sure whats your Agesa version
> If 1T
> RTT
> ProcODT 36.9ohm allow you - disable/ off /RZQ 5 (default)
> if you go 28.2ohm , benefit is allow cldo vddp run below 900
> but you probably need to retune your RTT
> I don't know whats your comfortable value RTT park and rtt nom
> but RTT Wr should be always RZQ/3
> 
> then next
> you can try ClkDrvStr
> 40/20/30/20 or
> 40/20/30/24
> if still unstable
> last try 60/20/30/20 or 60/20/30/24
> 
> tips
> there's not compulsory to go 1T
> if you feel 2T its stable
> just stay at 2T if you don't mind that few hundred Read/Writes bandwidth and the latency 0.1~0.2ns different.
> 
> if you really wants to go 1T you probably need to retune many thing.
> Primary timings go flat is an idea
> then sub
> try trrds/trrdl/tfaw/x4 x8 x16 mode
> trfc /twtrs /twtrl
> trfc is abit messy, it related to trc trtp
> vdimm straight put 1.62v
> then reduce step by step till it unstable.
> 
> and another tip for 2T
> if 2T
> ProcODT 28.2 ohm
> try ClkDrvStr
> 30/20/30/20 or 30/20/30/24
> 
> 
> 
> and another tip for 1T disable 56-0-0
> your CsOdtDrvStr probably don't need 30
> I think 20/24 should be fine. or maybe Im wrong?
> good luck


Thanks for the suggestion that is really helpful, AGESA is 1.2.0.3c, the Zentimings ss i posted with 2T is stable but if the difference is 0.1-0.2ns i would have to reconsider the 1T goal. I am mostly focused on latency and currently with the setup i posted i am doing around 52.7ns. Other question I had was why I was getting WHEAs at higher FCLK (1933 and 1966) when PBO is turned on. With PBO off i have 3933cl16 2T stable (52.4ns AIDA latency). I did raise voltages but that didn't help fix em the only way i can have 3933cl16 stable is with CPU at stock. And lastly if everything fails and im stuck at 3800 2T GDM off how can I lower tRAS and tRC? I tried tRAS 21 and that was unstable so can i lower tRAS and tRC both by 1 tick and see where it settles? Thanks again


----------



## Fturkut

Taraquin said:


> You are running unsynced, make mclk=fclk=uclk. I would try 3800\1900 instead, you probably get a lot of WHEA19 at 4000 and you probably need to adjust VDD18 voltage etc to avoid performance loss.
> For 3800 and synced:
> Try 1.5V
> Soc 1.15v
> Iod 1.05v
> ccd 1.0v
> vddp 0.9v
> 
> CL 16
> RCDs 19
> RP 19
> RAS 32
> RC 51
> RRDS 4
> RRDL 6
> FAW 16
> WTRS 4
> WTRL 12 (8 may work, try if 12 works)
> RFC 520 (as low as 460 may work, try 10 and 10 lower and see how far you get)
> RDRDSCL 4
> WRWRSCL 4
> CWL 16
> RDWR 8 or 9
> WRRD 1


I couldn't get a screen with these settings. I had to reset the BIOS.


----------



## Bloax

mnathani98 said:


> Hey folks! Need some advice on how to lower tRAS and tRC. VDIMM is at 1.55v (with a 120mm fan on top of the GPU) and stable. Tried tRCD + tRTP for tRAS but wasn't stable. Should i lower it a tick at a time and see where it settles? Also couldn't get 1T GDM Off stable so any suggestions on that would be really helpful as well.
> 
> 
> View attachment 2564707


here's Veii's latest little viper4000c19 adventures for handy-dandy reference (as _I don't_ have those sticks):








some notes:

GDM Off 1T with the sticks runs with either RTT 6/3/6 + CADBus 60-20-40-20, or seemingly RTT 7/3/6 + 40-20-30-24 at high (1.63v+) voltages, alongside the frequency-appropriate tCKE*
tFAW is high and tCKE a little odd (+1) either for stability, or to nudge the data signals to time out/stall less with tRAS = RCD+RTP / tRC = RAS+RP (i.e. moar performance with "worse" timings)
These sticks might want CPU 1.8v (lucky you, you have an asscock motherboard that labels it exactly this) to be 1.9-1.96v to run procODT 30, which is important


* starting at 1800 MCLK, tCKE is 7, plus 2 for each multiple of 100 MCLK (i.e. 9 at 1900, 11 at 2000, and *still 11* at 2083 MCLK)
bear in mind that procODT, RTT and CADBus all play together to make it work, with the tCKE there to stabilize it

good luck brutha


----------



## Taraquin

Fturkut said:


> I couldn't get a screen with these settings. I had to reset the BIOS.


Okay, try the same but set:
RCD 20
RP 20
RAS 40
RC 60
RFC 560
RDWR 10

Keep the rest the same, if stable save profile and work your way down on the timings above until you see what fails.


----------



## mnathani98

Bloax said:


> here's Veii's latest little viper4000c19 adventures for handy-dandy reference (as _I don't_ have those sticks):
> View attachment 2564717
> 
> some notes:
> 
> GDM Off 1T with the sticks runs with either RTT 6/3/6 + CADBus 60-20-40-20, or seemingly RTT 7/3/6 + 40-20-30-24 at high (1.63v+) voltages, alongside the frequency-appropriate tCKE*
> tFAW is high and tCKE a little odd (+1) either for stability, or to nudge the data signals to time out/stall less with tRAS = RCD+RTP / tRC = RAS+RP (i.e. moar performance with "worse" timings)
> These sticks might want CPU 1.8v (lucky you, you have an asscock motherboard that labels it exactly this) to be 1.9-1.96v to run procODT 30, which is important
> 
> 
> * starting at 1800 MCLK, tCKE is 7, plus 2 for each multiple of 100 MCLK (i.e. 9 at 1900, 11 at 2000, and *still 11* at 2083 MCLK)
> bear in mind that procODT, RTT and CADBus all play together to make it work, with the tCKE there to stabilize it
> 
> good luck brutha


Damn that looks unreal, it might be the lowest latency ive ever seen on a Ryzen. Yeah while that seems sorta impossible for me to achieve even tho i have the same bin, i'll try the things you have said above and get back. My "reasonable" goal is to daily something sub 52ns while still having PBO. Some benchmarks of where things are currently:


----------



## Valka814

Looks like I'm slowly at a better setup with the knowledge of you guys, thank you!
Also, Veii's TM5 error guidance helped a lot!


----------



## ReyReverse

Valka814 said:


> Looks like I'm slowly at a better setup with the knowledge of you guys, thank you!
> Also, Veii's TM5 error guidance helped a lot!
> View attachment 2564728


congratz..... you made it!!!!!


----------



## KedarWolf

HCI MemTest, old classic.


----------



## ReyReverse

mnathani98 said:


> And lastly if everything fails and im stuck at 3800 2T GDM off how can I lower tRAS and tRC? I tried tRAS 21 and that was unstable so can i lower tRAS and tRC both by 1 tick and see where it settles? Thanks again


probably problem at your tRCDRD ,tRTP and tWR
try trcdRD 14, twr 14 , trtp 7.



mnathani98 said:


> Other question I had was why I was getting WHEAs at higher FCLK (1933 and 1966) when PBO is turned on. With PBO off i have 3933cl16 2T stable (52.4ns AIDA latency). I did raise voltages but that didn't help fix em the only way i can have 3933cl16 stable is with CPU at stock.


3866 3933 WHEA issues
add dimm voltage won't fix WHEA, you have to play with your vddp ccd & IOD. 
Hwinfo64 tick auto start reboot then check is there any WHEA . if no then run OCCT 1 hour SSE memtest, see can make how many cycles. (good overclock can makes 270 cycles above) 
if it passed then next play is CPU1.8v , idea start at 1.85v~1.86v
OCCT again "CPU" stress test


----------



## ReyReverse

KedarWolf said:


> HCI MemTest, old classic.
> 
> View attachment 2564731


I remembered it, my first day overclock HCI Memtest everything is so simple and easy


----------



## ReyReverse

@*mnathani98*

my previous comment
maybe you can see here.
this one is Agesa 1207, just ignore my tFAW 12. but this is the only value can let me in 26mins makes 140 cycles. extremely fast








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Hi all. I just recently finished overclocking my 4x8gb SR Hynix DJR kit with the following settings. Note: Vsoc is under load is actually 1.0875v and not 1.5500v being reported by zentimings. Also, VDIMM reported under hwinfo is actually 1.400v and not the 1.370v reported by zen timings. I...




www.overclock.net





and this one is Agesa 1203c








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Hi, 2x8gb corsair 3600cl18 micron rev-e kit ~45celcius Thoughts on the Error 2 on [email protected]? Cheers! Your VSOC looks stockish. Might want to up that a bit.




www.overclock.net


----------



## KedarWolf

ReyReverse said:


> I remembered it, my first day overclock HCI Memtest everything is so simple and easy


I have scripts for the paid version of HCI 7.0, it opens HCI, the number of instances depending on what CPU you use, the memory amounts either 16GB or 32GB. 
It'll space them evenly and cleanly, and it'll assign each HCI instance to its own logical core, like instance 1 on logical core 1, instance 2 on logical core 2 etc., the very best way to run HCI.


----------



## mnathani98

Bloax said:


> here's Veii's latest little viper4000c19 adventures for handy-dandy reference (as _I don't_ have those sticks):
> View attachment 2564717


Unfriggin believable! I just copied Veii's RTTs and Drive Strengths and now im 1T Stable! Reads saw a huge boost! Latency is just 0.1ns lower but wow. Thanks again for your help!


----------



## lordpantsington

umea said:


> anyone have experience with TUF GAMING X570 PLUS in 4x8 bdie config? friend is looking to upgrade ram + cpu, not sure if i should suggest him a 2x16 or 4x8 kit. 4x8 would be the viper 4000cl16 bin probably.
> 
> i looked through the forums/this thread but didn't find much about it.


Which cpu?
I run 5900x with TUF Gaming X570 Plus, with 4x8, 4400cl19 Viper Steels @ 3800 cl 16 2T, and would suggest 2x16 (DR). Trying to go faster or drop to cl14 has been rough. It'll post @ like 1.53v-1.575, but throw errors with TM5. I'm not comfy running that daily.


----------



## Fturkut

Taraquin said:


> Okay, try the same but set:
> RCD 20
> RP 20
> RAS 40
> RC 60
> RFC 560
> RDWR 10
> 
> Keep the rest the same, if stable save profile and work your way down on the timings above until you see what fails.


Thank you No error with this values. Which one should i drop?


----------



## Taraquin

Fturkut said:


> Thank you No error with this values. Which one should i drop?


Wr 16, rtp 8 first. Next try rfc, drop by 10 and 10 until it fails, if no boot raise by 20 and run stability test (should do 480-520), next rcdrd 19, then rp 19, then drop ras (rc must be ras+rp), rdwr 9 or 8 and lastly wtrl 10 or 8.


----------



## mnathani98

@Bloax Hey! another interesting finding, I tried tRCD 14 and it errored out after 30 mins on Anta Absolut at Test 2 or 3 on the 2nd cycle iirc. This was not the case before. Whenever i tried tRCD 14 it used to be a error fest. Do you happen to know what the test 2 or 3 error could mean on anta absolut? DRAM voltage is at 1.55v.


----------



## Baio73

Fturkut said:


> Thank you No error with this values. Which one should i drop?


I wonder how you managed to get TM5 to make 25 cycles in about 1 hour... that's mine:



The only parameter I modified was:



But 10 hours and I stopped it manually.
Of course if I execute TM5 with originale 1usmus profile, it works perfectly.
I suspect TM5 is not 100% reliable...

Baio


----------



## mnathani98

Baio73 said:


> I wonder how you managed to get TM5 to make 25 cycles in about 1 hour... that's mine:
> 
> 
> 
> The only parameter I modified was:
> 
> 
> 
> But 10 hours and I stopped it manually.
> Of course if I execute TM5 with originale 1usmus profile, it works perfectly.
> I suspect TM5 is not 100% reliable...
> 
> Baio


Try again. 1usmus v3 takes just around an hour for 25 cycles. Sometimes TM5 cucks out so try again but if it happens again then it's something wrong on your side.


----------



## Baio73

mnathani98 said:


> Try again. 1usmus v3 takes just around an hour for 25 cycles. Sometimes TM5 cucks out so try again but if it happens again then it's something wrong on your side.


Thanks for your replay, but is the mod I made in the 1smus_v3.cfg file correct to make it perform 25 cycles in row without having to stay at the pc and relaunching it every time?

Baio


----------



## The_King

Baio73 said:


> I wonder how you managed to get TM5 to make 25 cycles in about 1 hour... that's mine:
> But 10 hours and I stopped it manually.
> Of course if I execute TM5 with originale 1usmus profile, it works perfectly.
> I suspect TM5 is not 100% reliable...
> 
> Baio


Testing 32GB takes much longer than testing 16GB. There is no fixed time for cycles to complete.

Other factors like timing CAS, RRDS and tFAW etc can make test times vary from minutes to hours.


----------



## Baio73

The_King said:


> Testing 32GB takes much longer than testing 16GB. There is no fixed time for cycles to complete.
> 
> Other factors like timing CAS, RRDS and tFAW etc can make test times vary from minutes to hours.


Thanks to you too… can you confirm the mod I made to the .cfg file is correct?
It seems so strange to me… I can agree 32Gb take a longer time, but 1 hour and 25 cycles against 10h and just 8 cycles seems really weird… did anyone complete 25 cycles with 32Gb? How long did it take?

Baio


----------



## MrHoof

Ye there seems to be something wrong with your config. Should take around 3h, added my config as txt in the attachments.


Spoiler: 5800x 32GB 1usmusv3


----------



## DukeRaoul2010

Veii said:


> I don't understand
> 
> GDM does bother


I just meant you seem to do things a little differently, and i would be great to know the method you use when you overclock ie the order in which you do things and your goals etc


----------



## ReyReverse

Baio73 said:


> I wonder how you managed to get TM5 to make 25 cycles in about 1 hour... that's mine:
> 
> 
> 
> The only parameter I modified was:
> 
> 
> 
> But 10 hours and I stopped it manually.
> Of course if I execute TM5 with originale 1usmus profile, it works perfectly.
> I suspect TM5 is not 100% reliable...
> 
> Baio











Your tm5 is not running
No color blue , yellow or red.


----------



## Baio73

ReyReverse said:


> View attachment 2564815
> 
> Your tm5 is not running
> No color blue , yellow or red.


Oh, that’s the point I was thinking about.
So, does it mean TM5 crashed? Isn’t it suppose to give an error instead of running in a perpetual loop without doing nothing?

Baio


----------



## Audioboxer

Baio73 said:


> Oh, that’s the point I was thinking about.
> So, does it mean TM5 crashed? Isn’t it suppose to give an error instead of running in a perpetual loop without doing nothing?
> 
> Baio


TM5 crashed, either memory or CPU is unstable. (or both lol)


----------



## ReyReverse

Baio73 said:


> Oh, that’s the point I was thinking about.
> So, does it mean TM5 crashed? Isn’t it suppose to give an error instead of running in a perpetual loop without doing nothing?
> 
> Baio


Sometimes windows crash will cause permanent damage (even CMD SFC /scannow won't fix it) to your windows program or files( include your tm5 ). You need to reinstall your Windows


----------



## Baio73

Audioboxer said:


> TM5 crashed, either memory or CPU is unstable. (or both lol)


It happened again, and again on 8th cycle:



CPU is @stock, so it may be the RAM... what value do you suggest to lower first?



Baio


----------



## Baio73

ReyReverse said:


> Sometimes windows crash will cause permanent damage (even CMD SFC /scannow won't fix it) to your windows program or files( include your tm5 ). You need to reinstall your Windows


That's something I can hardly believe to... TM5 is freshly downloaded (and I had the same issue with the previously downloaded version), my Windows is 100% stable, bot in normal use and benchmarking (Karhu RAM Test, OCCT, 3DMark), only TM5 has this really strange behaviour.

Baio


----------



## Veii

ReyReverse said:


> Your tm5 is not running
> No color blue , yellow or red.


TM5 pauses on Cycle 15 and free's up RAM
then fills out ram @Baio73

A freeze can happen either if one thread crashes mid rendering (which will keep it on an infinite loop)
or if page file fills and something else cleans it (bugs out TM5)

If Page file systemwide is disabled, then it will the storage as cache
Windows StorageSense tho does clean temporary files

This bug can also happen, if you open your browser and/or discord - mid a cycle
Not always will it be able to prioritize enough load and it can bug out mid-cycle , well or at the end
Most common tho is core instability ~ if it hangs on the end of #15 and keep's up the timer
There will be no indication , but #15 is still a running test ~ even without colors

EDIT:
Usually it doesn't need more than 2-5min for #15


DukeRaoul2010 said:


> I just meant you seem to do things a little differently, and i would be great to know the method you use when you overclock ie the order in which you do things and your goals etc


I will think about it
There has to be something written out , but i'll keep it in mind 
Currently quite busy with Navi


PJVol said:


> @Veii @Blameless
> Have you guys already tried RM CLI binary in action (courtesy of ASRock - I certainly do like them  ) from a mb utility package?


Not yet. i try to stay very far away of AMD's recent updates.
AGESA 1207 & PCH updated caused another trouble with flashing Navi's
It looks interesting - maybe i'll check it out once X3D has finished
I really don't trust their libraries anymore ~ as recent months couple more enforced patches and changes came, where you have to play detective. Bothersome times

Thank you tho
It looks quite good
Does it auto refresh ?


----------



## Audioboxer

Baio73 said:


> It happened again, and again on 8th cycle:
> 
> 
> 
> CPU is @stock, so it may be the RAM... what value do you suggest to lower first?
> 
> 
> 
> Baio


What kind of memory is that? Running 1T with GDM disabled on a 2x16GB kit is not something I can do with my B-die. Not at 3800 anyway.

As it seems to be rated 3600C14, I'm guessing it's B-die.

So, I'd probably be wanting to look at going to 2T/GDM disabled first and working on your timings to make sure they are stable.


----------



## KedarWolf

Baio73 said:


> Thanks to you too… can you confirm the mod I made to the .cfg file is correct?
> It seems so strange to me… I can agree 32Gb take a longer time, but 1 hour and 25 cycles against 10h and just 8 cycles seems really weird… did anyone complete 25 cycles with 32Gb? How long did it take?
> 
> Baio


25 cycles on a 5950x with 32GB of RAM takes me about 2 hours and 40 minutes.


----------



## Rinko

mnathani98 said:


> Unfriggin believable! I just copied Veii's RTTs and Drive Strengths and now im 1T Stable! Reads saw a huge boost! Latency is just 0.1ns lower but wow. Thanks again for your help!


Nice to hear it worked out for you, it's encouraging! I also just got a pair of the Viper 400019s and I've been trying to get them to work @ 3800 15 1t myself but so far no luck. I seem to be stuck getting error #6s now even after 1.62v. Did you end up changing anything else besides the strengths?
I noticed my kit came in a A2 pcb though, unlike some of the previous reports about the 400019s which were A0.


----------



## Veii

Rinko said:


> Nice to hear it worked out for you, it's encouraging! I also just got a pair of the Viper 400019s and I've been trying to get them to work @ 3800 15 1t myself but so far no luck. I seem to be stuck getting error #6s now even after 1.62v. Did you end up changing anything else besides the strengths?
> I noticed my kit came in a A2 pcb though, unlike some of the previous reports about the 400019s which were A0.


Can you give a tiny bit more information ?
Does Thaiphoon burner report them that way ?
ViperTW usually runs custom PCB designs ~ can you differentiate them from A3 ?

What's your timing preset ~ #6 mostly is IMC related , but can be too low primaries too
3800 15-15 would need around 1.52ish. Somewhere 1.46-1.52, near that.
3800 14-14 is around 1.48-1.56v, but could need 1.6v

Does TM5 report you any #4's ?
CAD_BUS you can try 40-20-40-20 for A2 , and or RTT 6-3-6 on them. 
// Alternatively 6-3-7 with 60-20-30-24 (but keep VDD18/VTT bellow 1.96 and procODT at or bellow 32ohm for this)
I wonder if they downbinned a 4400 19-19 kit, then it would be "A2" but rather a custom A1 design

Please give a bit more information:
~ Zentimings screenshot
~ TM5 reports, more than one error
~ maybe a centered trace picture of the PCB
Maybe something near that:








Like this person did, but tiny bit further away // from the sides where the ICs are
Generally in good light-condition, slightly angled soo traces shine 

EDIT:
Welcome to OCN !


----------



## mnathani98

Rinko said:


> Nice to hear it worked out for you, it's encouraging! I also just got a pair of the Viper 400019s and I've been trying to get them to work @ 3800 15 1t myself but so far no luck. I seem to be stuck getting error #6s now even after 1.62v. Did you end up changing anything else besides the strengths?
> I noticed my kit came in a A2 pcb though, unlike some of the previous reports about the 400019s which were A0.


I have the same kit as well doing 3800 c14 @ 1.54v trcd 15. try tcke 9 along with Veii's suggestion of RTTs (6/3/6 and 40-20-30-24 is what i run on mine). I got a test 6 error last night when i was messing with some stuff and tcke 9 fixed it.


----------



## KedarWolf

I was messing my memory addressing. These settings are best both in AIDA64 and y-cruncher.

You need an MSI CBS unlocked BIOS though to access these settings.


----------



## Bloax

mnathani98 said:


> I have the same kit as well doing 3800 c14 @ 1.54v trcd 15. try tcke 9 along with Veii's suggestion of RTTs (6/3/6 and 40-20-30-24 is what i run on mine). I got a test 6 error last night when i was messing with some stuff and tcke 9 fixed it.


I should note that there is such a thing as "Too Much Voltage", and it is in fact no different from "Too Little" voltage except that "Too Little" tends to crash harder than "Too Much" until it becomes "WAY TOO MUCH".

For figuring out what voltage you need for 3800 14-14-14, I'd first take a look at what the minimum voltage for 3800 15-15-15 is, then what the minimum voltage (likely about -0.09v from 15-15-15) for 3800 16-16-16 is.

3800 14-14-14 should be roughly the same step up from 15-15-15, as 15-15-15 is higher than 16-16-16 (in my experience, this step is usually around 0.09v, but it should be pure lottery)

EDIT:
And this is one way to figure out the "limit" of your sticks, as when this pattern breaks while you're using the "good/optimal" RTT/CADBus setup for them at those voltages (Nom impedance decreases/divisor increases as voltage becomes very high??), they've simply been MaXxED out.

An example of this is my Ripjaws 3200 14-14-14 sticks refusing to do MCLK / tRCD > 127, whereas these Viper 4000 16-16-16 sticks are fine even with MCLK / tRCD = 147 (3800 13-13-13)


----------



## Rinko

Veii said:


> Can you give a tiny bit more information ?
> Does Thaiphoon burner report them that way ?
> ViperTW usually runs custom PCB designs ~ can you differentiate them from A3 ?
> 
> What's your timing preset ~ #6 mostly is IMC related , but can be too low primaries too
> 3800 15-15 would need around 1.52ish. Somewhere 1.46-1.52, near that.
> 3800 14-14 is around 1.48-1.56v, but could need 1.6v
> 
> Does TM5 report you any #4's ?
> CAD_BUS you can try 40-20-40-20 for A2 , and or RTT 6-3-6 on them.
> // Alternatively 6-3-7 with 60-20-30-24 (but keep VDD18/VTT bellow 1.96 and procODT at or bellow 32ohm for this)
> I wonder if they downbinned a 4400 19-19 kit, then it would be "A2" but rather a custom A1 design
> 
> Please give a bit more information:
> ~ Zentimings screenshot
> ~ TM5 reports, more than one error
> ~ maybe a centered trace picture of the PCB
> Maybe something near that:
> 
> 
> 
> 
> 
> 
> 
> 
> Like this person did, but tiny bit further away // from the sides where the ICs are
> Generally in good light-condition, slightly angled soo traces shine
> 
> EDIT:
> Welcome to OCN !


Thank you!
Typhoon reports them as A0 but I saw the thread about these memories here and decided to check out of curiosity, I didn't remove the heatsink but from what I could see it looks like the A2 layout with the extra capacitors on top (A3?):






































I tried your suggestions and this has been the best result so far:









This board seems to overvolt vdimm by 20mv, and vdd18 by 40mv. Total get was vdimm 1.55v, soc 1.115v, vdd18 1.840v (auto). Any less vdimm throws me errors with those RDWR/WRRD.
Before that I was using these timings:









And this is what I was testing when I got the error #6s and crashed:









I got this system just a few days ago so not a lot of testing done yet. One of the first things I tried that I'd like to revisit is trying to get 2000 fclk error free. The system posted fine with 2000 fclk auto on all voltages on auto + the 4000 xmp profile. After changing them from auto (cdd/iod were 1.1v and soc was 1v) and testing the system a bit this was the lowest amount of WHEA 19s I managed to get while running y-cruncher:









Higher vdd18 and soc seemed to increase the number of errors. I didn't get any usb or sound problems or any WHEA other than 19s and the system seemed stable enough during some gaming. Do you think I could manage to get rid of errors by properly tuning proc/cad/rtt?


----------



## Bloax

Rinko said:


> [2000 fclk]
> Do you think I could manage to get rid of errors by properly tuning proc/cad/rtt?


procODT/CADBus/RTT stay consistent across the entire frequency range, at least for the "best-working" set of them (which reveals itself by trying to run ""easy"" settings at high [1900-2100ish]* MCLK)
* lower for dual-rank sticks, higher for single-rank ones, usually by 2000 it's pretty obvious


Based on your Viper 4000C19 "seeming" to have a different PCB, and also running procODT 28.2 with CPU 1.8v at significantly less than what they "used" to require - it may very well be that your kit is actually using the revised PCB that is also employed in the 4000C16 kit, just with worse binned memory chips.


To dial in an FCLK, calculating 2.5 billion pi's of y-cruncher with _stable memory_ and a static CPU frequency seemed to be the easiest method?
Still featuring everyone's favorite, going up and down by 0.01v on three different voltage rails (SOC/IOD/CCD) until you find the one with the lowest time.



Code:


@echo off
cd /d %~dp0
y-cruncher skip-warnings priority:3 bench 2.5b

handy .bat file to place in the same folder as y-cruncher.exe, as well as a shortcut to it on your desktop








may also want to do this, just to shorten bootup times (and make benchmark times even more consistent)

the benchmark produces files called "Pi - [date].txt" and the part you're looking to compare is this one:


Code:


Total Computation Time:    90.148 seconds
Start-to-End Wall Time:    92.563 seconds

CPU Utilization:           1831.16 %  +  0.45 % kernel overhead
Multi-core Efficiency:     91.56 %  +  0.02 % kernel overhead


----------



## TwilightRavens

Anyone got any tips for stabilizing 4 x 16GB of b-die at 3800MHz on X570 with a 5950X? Best I can really do with all 4 sticks is 3600MHz, fclk will do 2000 but can’t get memory to sync to that.


----------



## KedarWolf

I had problems stabilizing my memory with hotter ambient temps. 

I saw @Veii using 6/3/6, that won't boot for me, but 6/3/5 will and I got this today.

Memory at 1.51v in BIOS, RTTs at .755v.

I like the low VSOC and VDDGs. I had to have 1.22v VSOC in BIOS, 1.2063 in ZenTimings, had droop, and VDDGs at 1.1v and 1.15v.


----------



## TwilightRavens

Okay so I am utterly confused now, any time I set SoC to 1.2v the PC fails POST once, then POST's fully the next.

Retried 3800MHz, not even a POST.
3733MHz I was able to boot into windows, but no matter what voltage I adjusted memtest would error within 5%
SoC up to 1.2
VDDG up to 1.1
and both VDDP IOD and CCD to 1.125

Unless I'm just at the mercy of a Daisy Chain memory topology?

-edit XMP isn't even 100% as I've just found out.


----------



## The_King

TwilightRavens said:


> Okay so I am utterly confused now, any time I set SoC to 1.2v the PC fails POST once, then POST's fully the next.
> 
> Retried 3800MHz, not even a POST.
> 3733MHz I was able to boot into windows, but no matter what voltage I adjusted memtest would error within 5%
> SoC up to 1.2
> VDDG up to 1.1
> and both VDDP IOD and CCD to 1.125
> 
> Unless I'm just at the mercy of a Daisy Chain memory topology?
> 
> -edit XMP isn't even 100% as I've just found out.


Nothing wrong with your RAM. Your board only supports DDR4 3600 2X16GB B-die at XMP not 4X16GB unless, you run Micron E-die on Hynix J.

You could get all 4 to run if you custom set Vdimm voltages and VSOC. But I have never worked with 4X16GB sticks so can't help much.
I would recommend you run 2X16GB unless you really need 64GB for work etc.









ASRock X570 Taichi


Supports AMD AM4 Socket Ryzen™ 2000, 3000, 4000 G-Series, 5000 and 5000 G-Series Desktop Processors; Intel Wi-Fi 6 802.11ax (2.4Gbps) + BT 5.2; Supports DDR4 4666+ (OC); 3 PCIe 4.0 x16, 2 PCIe 4.0 x1; NVIDIA NVLink™, Quad SLI™, AMD 3-Way CrossFireX™; 7.1 CH HD Audio (Realtek ALC1220 Audio...




www.asrock.com


----------



## Andi64

I've been reading but it's hard to catch up with 977 pages. So, sorry for the basic question. I'm running 2x16GB GSkill TridentZ Neo 3600MT/s 16-16-16 with Samsung B Die.

I had a 5800X that worked fine with 1900 FCLK, and DDR4-3800 16-16-16 1.35v
Pretty basic stuff.

I now have a 5900X, that won't even POST at 1900 FCLK (I have 3 in fact, none of them POST at 1900 FCLK, they do at 1933 but I have WHEA errors).

So, I set 1866Mhz FCLK and DDR4-3733. Is there any "easy" config for B-Die to start from?


----------



## Bloax

Andi64 said:


> I've been reading but it's hard to catch up with 977 pages. So, sorry for the basic question. I'm running 2x16GB GSkill TridentZ Neo 3600MT/s 16-16-16 with Samsung B Die.
> 
> I had a 5800X that worked fine with 1900 FCLK, and DDR4-3800 16-16-16 1.35v
> Pretty basic stuff.
> 
> I now have a 5900X, that won't even POST at 1900 FCLK (I have 3 in fact, none of them POST at 1900 FCLK, they do at 1933 but I have WHEA errors).
> 
> So, I set 1866Mhz FCLK and DDR4-3733. Is there any "easy" config for B-Die to start from?


2-CCD processors (5900/5950x) tend to have "FCLK" holes much more than 1-CCD (5600-5800x) processors, and we have our live demonstration of this here. 

For dialing in FCLK, it remains a spreadsheet job of comparing y-cruncher times as described not far above: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

3866 may not be beneficial over 3733 simply because the voltage required for it to run stable might trigger more weird internal power-throttling, thus wiping out the performance benefits.

describing the "easy" config for b-die somehow escapes me, though what is commonly the case for dual-rank b-die is Nom/6 (40 ohm) Wr/3 (80 ohm) and Park/3 (80) being a good "starting place" for RTT terminations, and CADBus being 40-20-30-20, procODT around 36.9-34 until you raise CPU 1.8v / 1P8 / VDD18 / whatever-its-name to make 30 run fine


----------



## TwilightRavens

The_King said:


> Nothing wrong with your RAM. Your board only supports DDR4 3600 2X16GB B-die at XMP not 4X16GB unless, you run Micron E-die on Hynix J.
> 
> You could get all 4 to run if you custom set Vdimm voltages and VSOC. But I have never worked with 4X16GB sticks so can't help much.
> I would recommend you run 2X16GB unless you really need 64GB for work etc.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ASRock X570 Taichi
> 
> 
> Supports AMD AM4 Socket Ryzen™ 2000, 3000, 4000 G-Series, 5000 and 5000 G-Series Desktop Processors; Intel Wi-Fi 6 802.11ax (2.4Gbps) + BT 5.2; Supports DDR4 4666+ (OC); 3 PCIe 4.0 x16, 2 PCIe 4.0 x1; NVIDIA NVLink™, Quad SLI™, AMD 3-Way CrossFireX™; 7.1 CH HD Audio (Realtek ALC1220 Audio...
> 
> 
> 
> 
> www.asrock.com


I do tend to use that RAM occasionally for VM’s and file compression, so it would be nice to have it at the fastest i can run it.

But if I have to run 32GB i may just do that.


----------



## KedarWolf

Rinko said:


> Thank you!
> Typhoon reports them as A0 but I saw the thread about these memories here and decided to check out of curiosity, I didn't remove the heatsink but from what I could see it looks like the A2 layout with the extra capacitors on top (A3?):
> View attachment 2564954
> View attachment 2564955
> View attachment 2564956
> 
> View attachment 2564957
> View attachment 2564958
> 
> 
> I tried your suggestions and this has been the best result so far:
> View attachment 2564962
> 
> 
> This board seems to overvolt vdimm by 20mv, and vdd18 by 40mv. Total get was vdimm 1.55v, soc 1.115v, vdd18 1.840v (auto). Any less vdimm throws me errors with those RDWR/WRRD.
> Before that I was using these timings:
> View attachment 2564964
> 
> 
> And this is what I was testing when I got the error #6s and crashed:
> View attachment 2564967
> 
> 
> I got this system just a few days ago so not a lot of testing done yet. One of the first things I tried that I'd like to revisit is trying to get 2000 fclk error free. The system posted fine with 2000 fclk auto on all voltages on auto + the 4000 xmp profile. After changing them from auto (cdd/iod were 1.1v and soc was 1v) and testing the system a bit this was the lowest amount of WHEA 19s I managed to get while running y-cruncher:
> View attachment 2564965
> 
> 
> Higher vdd18 and soc seemed to increase the number of errors. I didn't get any usb or sound problems or any WHEA other than 19s and the system seemed stable enough during some gaming. Do you think I could manage to get rid of errors by properly tuning proc/cad/rtt?


I looked at this picture and until I looked at it very closely, I thought you bent the heatsink and ram.


----------



## Blackfyre

*Is it true y-cruncher gives a better indication of RAM stability? *Compared to TM5 for example running *50 cycles* of 1usmus_v3?

If so, can someone direct me to a guide (_or let me know_) on how to best test system stability with y-cruncher? There seems to be a lot of options and I am not sure which to choose at each step to get the longest stress test for system and ram stability.


----------



## dansi

Blackfyre said:


> *Is it true y-cruncher gives a better indication of RAM stability? *Compared to TM5 for example running *50 cycles* of 1usmus_v3?
> 
> If so, can someone direct me to a guide (_or let me know_) on how to best test system stability with y-cruncher? There seems to be a lot of options and I am not sure which to choose at each step to get the longest stress test for system and ram stability.


Call me lazy, but i wont fret over over testing synthetics. I have passed a few of them overnight, only to bsod from WHEA after 15 mins in a game. 
After plenty of trial and errors, I loosen the ram timings and no more in game bsod.


----------



## Bloax

dansi said:


> Call me lazy, but i wont fret over over testing synthetics. I have passed a few of them overnight, only to bsod from WHEA after 15 mins in a game.
> After plenty of trial and errors, I loosen the ram timings and no more in game bsod.


That sounds like a classic case of "GPU exhaust cooks the RAM and things go to hell" to me, good sir!




Blackfyre said:


> *Is it true y-cruncher gives a better indication of RAM stability? *Compared to TM5 for example running *50 cycles* of 1usmus_v3?
> 
> If so, can someone direct me to a guide (_or let me know_) on how to best test system stability with y-cruncher? There seems to be a lot of options and I am not sure which to choose at each step to get the longest stress test for system and ram stability.


yes y-cruncher crushes the system much harder than TM5 1usmus_v3, which is much more informative in regards to _how_ something failed than Making It Fail.





the video description says things in more explicit detail, but HNT is the quick "is this stable??" two-minute test, TM5 is the "why isn't it stable" test, FFT->HNT->VST->Loop is the "haha memory go boom boom" test (preferrably not run through a .bat file so that you're guaranteed to see how long it survived)


then benchmarking billions of Pi with a static CPU frequency is a way to dial in secondary/tertiary timings into a synergistic combination at 1T command-rate

just a word of warning, Billions of Pi, HNT and VST are all very very hot CPU loads, and memory tests don't require super high CPU frequencies, so don't try "normal" CPU/Voltages like 4.7 Ghz at 1.3v :- ))))
rather you'd be looking at things like 4.3 Ghz at 1.1v


----------



## KedarWolf

7/3/5 on my board seems to be golden. 7/3/6 won't boot.


----------



## The_King

View attachment 2565116


----------



## ocisdead

Hey cool nice "gold certificate", why don't I see that in my OCCT? Oh its a paid feature, let me just buy the software then, its probably like $10 or something and removing the one hour test limit would be great.

It's a monthly subscription service for stability testing...

Why?


----------



## KedarWolf

ocisdead said:


> Hey cool nice "gold certificate", why don't I see that in my OCCT? Oh its a paid feature, let me just buy the software then, its probably like $10 or something and removing the one hour test limit would be great.
> 
> It's a monthly subscription service for stability testing...
> 
> Why?


You can buy it for a year for less as well, but it's a bit expensive.


----------



## SneakySloth

ocisdead said:


> Hey cool nice "gold certificate", why don't I see that in my OCCT? Oh its a paid feature, let me just buy the software then, its probably like $10 or something and removing the one hour test limit would be great.
> 
> It's a monthly subscription service for stability testing...
> 
> Why?


Because OCCT is the main source of income of its developer who is constantly pushing out updates almost every week. A single 10$ fee is not sustainable to live off of.


----------



## Baio73

Veii said:


> TM5 pauses on Cycle 15 and free's up RAM
> then fills out ram @Baio73
> 
> A freeze can happen either if one thread crashes mid rendering (which will keep it on an infinite loop)
> or if page file fills and something else cleans it (bugs out TM5)
> 
> If Page file systemwide is disabled, then it will the storage as cache
> Windows StorageSense tho does clean temporary files
> 
> This bug can also happen, if you open your browser and/or discord - mid a cycle
> Not always will it be able to prioritize enough load and it can bug out mid-cycle , well or at the end
> Most common tho is core instability ~ if it hangs on the end of #15 and keep's up the timer
> There will be no indication , but #15 is still a running test ~ even without colors
> 
> EDIT:
> Usually it doesn't need more than 2-5min for #15


Thanks for youre replay, my page file is manually set to 8Gb fixed, TM5 had the same problem when it was set to automatic.
I tried setting the RAM to DOCP (no OC), but it stopped as usual at the 8Th cycle, so I can say it's not a matter of unstable OC (it passes 6000% under Karhu):



I can see from RAM temperatures,TM5 is open but it's not stressing the RAM in anyway... simply stuck.

What values of page file would you recommend?

Baio


----------



## Baio73

Audioboxer said:


> What kind of memory is that? Running 1T with GDM disabled on a 2x16GB kit is not something I can do with my B-die. Not at 3800 anyway.
> 
> As it seems to be rated 3600C14, I'm guessing it's B-die.
> 
> So, I'd probably be wanting to look at going to 2T/GDM disabled first and working on your timings to make sure they are stable.


It's a Samsung B-Die kit from Corsair.
But I tried setting the RAM to DOCP (3600MHz) and TM5 stopped at the very same point (8th cycle).
I think the OC it's stable, as it can pass any test @3800 with only CAS14 and GDM off (obviously overvolt).

Baio


----------



## Baio73

KedarWolf said:


> 25 cycles on a 5950x with 32GB of RAM takes me about 2 hours and 40 minutes.


Thanks, I took note of it!

Baio


----------



## Gregix

Hi guys.
Just testing atm, it is hard as hell as my CPU/MB combo says f u every time something goes wrong and I have to start from CMOS clear and load OC file from USB. My knees will gave up at some point...
My question is, as I am noob at OC RAM on AMD platform, where to look at with lowering latency? ATM I have 57.2ns.
Have to say with some crap 3933 c16 16 16 16 32 had 57ish too, with slightly bumped reads etc, while only 1.48V on RAM.

Ok it is not stable, Ollie ok, but extreme anta 1 error after 5 mins.


----------



## KedarWolf




----------



## Valka814

Made some improvements, not sure more is possible.


----------



## The_King

Valka814 said:


> Made some improvements, not sure more is possible.


With Micron E-die I could always run low SCLs 2s try lowering to 4s first and if no errors then try 2s. Your AIDA64 memory performance should increase.


----------



## Valka814

The_King said:


> With Micron E-die I could always run low SCLs 2s try lowering to 4s first and if no errors then try 2s. Your AIDA64 memory performance should increase.


3-3 is no go, but so far 4-4 looks good, stable and a slightly better latency in Aida. Thank you very much!


----------



## The_King

Valka814 said:


> 3-3 is no go, but so far 4-4 looks good, stable and a slightly better latency in Aida. Thank you very much!
> 
> View attachment 2565388


Not sure if i missed something but why is your CDWR 20 and CDRD 18? Both should be the same or WR should be lower.
In fact CDWR can go much lower than CDRD.


----------



## Valka814

The_King said:


> Not sure if i missed something but why is your CDWR 20 and CDRD 18? Both should be the same or WR should be lower.
> In fact CDWR can go much lower than CDRD.


The idea was to save some headroom for other timings, but thats all, no specific reason. I have very limited knowledge about the link between certain timings.
What are you sugesting? Thank you!


----------



## The_King

Valka814 said:


> The idea was to save some headroom for other timings, but thats all, no specific reason. I have very limited knowledge about the link between certain timings.
> What are you sugesting? Thank you!


Change CDWR from 20 to 18 then redo AIDA64 test and see if there is any change.


----------



## Asutz

switched x470 board and upgraded, bought b550 f gaming, looks more solid it seems, better sound with onboard bluetooth usage but noticed something strange.

vsoc auto or a fixed voltage it jumps between two values, is this "normal" behavior?
manuel 1.093 jumps between 1.0875 and the 1.093v setting in the bios.
what is causing this? thanks in advance


----------



## The_King

@Bloax I want to run this kit with my Viper 4400 C19. Will they play nice? Which Kit should be put in the good slots?


----------



## Bloax

The_King said:


> @Bloax I want to run this kit with my Viper 4400 C19. Will they play nice? Which Kit should be put in the good slots?
> 
> View attachment 2565424
> View attachment 2565425


If you set CPU 1P8 to 1.9v and can run ProcODT 28.2 with RTT 6/3/5 then they might play just fine together (viper4400C19 have an RTP/tWR range of 5-7 / 10-14)


The viper sticks are likely the ones who want to be in the bad slots, but _trying and seeing_ is free


----------



## Blameless

PJVol said:


> I tested the one from .466 build and all works fine.





Veii said:


> Not yet. i try to stay very far away of AMD's recent updates.
> AGESA 1207 & PCH updated caused another trouble with flashing Navi's
> It looks interesting - maybe i'll check it out once X3D has finished
> I really don't trust their libraries anymore ~ as recent months couple more enforced patches and changes came, where you have to play detective. Bothersome times
> 
> Thank you tho
> It looks quite good
> Does it auto refresh ?


I'm not able to get it to work at all with my 5800X3D.



Bloax said:


> That sounds like a classic case of "GPU exhaust cooks the RAM and things go to hell" to me, good sir!


This is why I test memory in hot ambients and/or reduced case fan speed, with a heavy GPU load.



Bloax said:


> y-cruncher crushes the system much harder than TM5 1usmus_v3, which is much more informative in regards to _how_ something failed than Making It Fail.


In memory temperature limited scenarios, I generally find y-cruncher to be an inferior test to TM5 1usmus_v3, sometimes even loops of Memtest86 test #7. However, the higher CPU load does force my CPU fan to higher speeds if I want to keep core clocks from throttling back heavily, which may influence memory temp too much.



Valka814 said:


> Made some improvements, not sure more is possible.


Does tRCDWR really need to be so high?

tRTP can probably be tightened at least a bit.


----------



## Taraquin

Valka814 said:


> The idea was to save some headroom for other timings, but thats all, no specific reason. I have very limited knowledge about the link between certain timings.
> What are you sugesting? Thank you!


RCDWR does little for itself or other timings, keep it same as RCDRD is my advice. 

Other timingsuggestions from a fellow rev E tuner:
RAS 36
RC 54 (may work, try RAS 37 and RC 55 or both one higher if unstable)
RRDS 4 (FAW=RRDS x 4 so your FAW is now 24)
WTRL 8
RFC 576, 560 or 544 depending on how good your bin is.
WR 14 (should be equal to or 1 below CL, can go lower aswell)
RTP 7 (RTP x 2 = WR)
CWL 14 (I would consider doing that since low CWL makes it harder to run the more important timing RDWR low)
RDRDSCL 4
WRWRSCL 4 (both these are usually more stable in even numbers and 4 is doable on almost all ram-dies)
RDWR 10 or 9
WRRD 3

Further tuning after you have tried the above:
Rev E has some strength and is usually superior to even B-die at some timings:
RP: Can often run this at 11 or 12, remember to raise RAS if doing that so that RAS+RP=RC
WTRS\WTRL: Can often run these absurdly low at like 3\6
WR\RTP: 10\5 often works

Weaknesses:
RCDRD: Needs 17-20 at 3800, you have a good bin
RC: Tends to need 52-60 at 3800. Usually one value spews errors, go one below that and you can`t boot. My rev E does 55 at 3700, 54 spews errors, 53 won`t boot.
RFC: Needs 544-608 at 3800

They tolerate a low of voltage (1.6v plus is usually okay) and don`t mind high temps (60C+ once tuned). Except for the bad RCDRD, RC and RFC I actually prefer working with rev E over B-die since B-die has the temp-issue once tuned.


----------



## Taraquin

The_King said:


> @Bloax I want to run this kit with my Viper 4400 C19. Will they play nice? Which Kit should be put in the good slots?
> 
> View attachment 2565424
> View attachment 2565425


I have run my Viper 4400c19 at 4000cl16 for over a year now. They can run very low ProcODT fine (28), but you must probably raise VDD18 for them to scale positive above 3800. I need 1.88v, lower or higher gets me worse performance. At ProcODT 32 I needed 1.84v. At 4066 I bet you need 1.84-1.88 with your current ProcODT. If you run CWL at 16 you can probably do 8 on RDWR, that is more beneficial. My kit hates low CWL even if I raise RDWR by 1 or 2. WRRD can do 1, WTRS\WTRL probably 3 and 9\10. You have a slightly better bin than me, I need 1.46V at 4000 with about the same timings as you except my RFC is at 280. 288 or 296 will probably work fine for you.

Do you get WHEA19 btw?


----------



## mnathani98

Just out of curiosity, what do yall consider the max safe daily voltages for SOC, CPU 1.8, VDDP, VDDG and B-Die (with and without fan)?


----------



## The_King

Bloax said:


> If you set CPU 1P8 to 1.9v and can run ProcODT 28.2 with RTT 6/3/5 then they might play just fine together (viper4400C19 have an RTP/tWR range of 5-7 / 10-14)
> 
> 
> The viper sticks are likely the ones who want to be in the bad slots, but _trying and seeing_ is free


Off to a good start I guess. Testing 32GB in TM5 is like watching paint dry!
Any input to improved timings welcome from all. @Taraquin @Veii


----------



## The_King

Taraquin said:


> I have run my Viper 4400c19 at 4000cl16 for over a year now. They can run very low ProcODT fine (28), but you must probably raise VDD18 for them to scale positive above 3800. I need 1.88v, lower or higher gets me worse performance. At ProcODT 32 I needed 1.84v. At 4066 I bet you need 1.84-1.88 with your current ProcODT. If you run CWL at 16 you can probably do 8 on RDWR, that is more beneficial. My kit hates low CWL even if I raise RDWR by 1 or 2. WRRD can do 1, WTRS\WTRL probably 3 and 9\10. You have a slightly better bin than me, I need 1.46V at 4000 with about the same timings as you except my RFC is at 280. 288 or 296 will probably work fine for you.
> 
> Do you get WHEA19 btw?


With this 5600 non X I am WHEA free till FCLK 1933.

I will be tuning for 3800/1900 for now. Daily use.

Although I do get WHEA errors at FCLK 2000/2033 nothing crashes everything runs fine and benches fine even Y-cruncher


----------



## Taraquin

The_King said:


> WIth this 5600 non X I am WHEA free till FCLK 1933.
> 
> I will be tuning for 3800/1900 for now. Daily use.
> 
> Although I get WHEA errors at FCLK 2000/2033 nothing crashes everything runs fine and benches fine even Y-cruncher


If you only get a few they can probably be tweaked away by running SOC, IOD or VDDP lower or higher


----------



## Blackfyre

Taraquin said:


> If you only get a few they can probably be tweaked away by running SOC, IOD or VDDP lower or higher


I was testing what was already stable for 1+ month of usage (_games, desktop use, photoshop, lightroom, etc_). And was also stable with with 1usmus when I tested over a month ago.

But a few days ago, when I tested, I got *1 error*

I tweaked SOC, IOD, VDDP, 1.8PLL, etc, still got that 1 error, usually between 23 cycles and 30 cycles, and nothing after all the way to 50 cycles.

Anyway, I gave up on it and decided to roll back secondary timings to what they were before. But when I have time, I will try to tweak again and find out which secondary timing is causing the issue:


----------



## Blameless

Reevaluating settings for this Team T-Create dual-rank Samsung B-die kit at high temps on my 5800X3D:








Up to pass 45 at just over four hours as of this post.

IR thermometer reads current intake temp at the front of my case at ~35C. Coldest drive listed is an idle mechanical drive thermally coupled to the case and a very good indicator of the coldest any air flow hitting the memory could be, though it's probably higher due to the exhaust from the GPU. SSD and VRM temps indicate board is pretty uniformly 50C+. I don't have a temp sensor on the DIMMs and didn't open it up to point my thermometer at them, but from previous experience and a little napkin math, the ICs are likely ~65C tCASE.

vDIMM is 1.49v, which is about the minimum and maximum I can get away with while being completely stable at these settings at this temperature. Compared to the settings I was previously using (/3 or 80Ohm), an RttPark of RZQ/4 (60Ohm) seems to have allowed me to use slightly more voltage before reaching temperature limits. Increased tCKE and adjusting CkeDrv was required stabilize the lower termination resistance, but that has no real downsides. RttPark RZQ/5+ is a no POST at this voltage and any voltage I can get it to POST at is way past the ability of RttPark to mitigate, thermally speaking.

Other relevant voltages are set to: 1.025 vSOC (LLC 2), 0.85v CLDO VDDP and CPU VDDP, 0.91v CLDO VDDG CCD, 0.96v CLDO VDDG IOD, and 1.73v CPU 1.8v.

At this point, I can't find any combination of stable settings that is all-round faster. tCL or tRCD of 14 require enormous voltage and/or such loose tRTP and tRDWR that they either immediately overheat or are slower. AddrCmdSetup of 0 is similar. It will POST and reliably train, but without a ton more voltage and heat, or uselessly lax settings elsewhere, throws tens of thousands of errors in Memtest86. It would probab would probably destroy my Windows install if I booted into it. tRDWR of 7 is a no POST. Any combination of tighter tRP and tRAS that results in a tRC of less than 40 needs more voltage than I can justify. Down to tRC of 38 would be workable at this voltage with better airflow, but not at worst case temps. I tried tRP 14 and tRAS 26, but that was slightly slower than 13/27, while 12/28 needs more voltage and isn't really much faster. SCLs work down to 2, but help almost nothing and read benches suffer below 4.

AIDA64 latency (fresh reboot, not in safe mode, all prefetchers enabled) is pretty consistently ~52.1ns on my 5800X at these settings and 56.7ns on my 5800X3D.

I might try upping CPU 1.8v again to see if that allows me to reduce RttPark or ProcODT further.

_Edit:_









Closed the miner and fired up FurMark to dump an extra 150w into the case for the last seven passes or so. Board temp increased about 6-7C, so memory should be pushing ~70C. Will close FurMark after a few more passes and open up the room to see what a rapid reduction in memory temp does.



Blackfyre said:


> But a few days ago, when I tested, I got *1 error*
> 
> I tweaked SOC, IOD, VDDP, 1.8PLL, etc, still got that 1 error, usually between 23 cycles and 30 cycles, and nothing after all the way to 50 cycles.
> 
> Anyway, I gave up on it and decided to roll back secondary timings to what they were before. But when I have time, I will try to tweak again and find out which secondary timing is causing the issue:
> 
> View attachment 2565481


At first glance, tRAS is one low for that tRC, tRFC might be causing some issues (it should at least be even, and tRFC 2/4 should either be corrected or just set the same as tRFC). An RttPark of /7 may be too agressive, especially with tCKE on auto/1. Your CLDO VDDP voltage is also very high. You may also just need a touch more vDIMM.


----------



## Taraquin

Blackfyre said:


> I was testing what was already stable for 1+ month of usage (_games, desktop use, photoshop, lightroom, etc_). And was also stable with with 1usmus when I tested over a month ago.
> 
> But a few days ago, when I tested, I got *1 error*
> 
> I tweaked SOC, IOD, VDDP, 1.8PLL, etc, still got that 1 error, usually between 23 cycles and 30 cycles, and nothing after all the way to 50 cycles.
> 
> Anyway, I gave up on it and decided to roll back secondary timings to what they were before. But when I have time, I will try to tweak again and find out which secondary timing is causing the issue:
> 
> View attachment 2565481


My bet is RDWR or RFC. 10 and 560 may fix it.


----------



## Blackfyre

Taraquin said:


> My bet is RDWR or RFC. 10 and 560 may fix it.


Could be Trcdwr = 10, as I know 11 is safe.

But tRFC = 551 and tRDWR = 8 are safe from what I know already in the *green column* tested for 50 cycles.

I think it's* Twr* and *Trtp *(red in the last column)*, *I am changing them back to 14 and 7 and testing overnight. Instead of 12 & 6

Is there a benefit to doing 14 & 6? instead of 14 & 7. From what I remember you said Twr = Trtp x 2 back when I first started overclocking these kits.


----------



## Taraquin

Blackfyre said:


> Could be Trcdwr = 10, as I know 11 is safe.
> 
> But tRFC = 551 and tRDWR = 8 are safe from what I know already in the *green column* tested for 50 cycles.
> 
> I think it's* Twr* and *Trtp *(red in the last column)*, *I am changing them back to 14 and 7 and testing overnight. Instead of 12 & 6
> 
> Is there a benefit to doing 14 & 6? instead of 14 & 7. From what I remember you said Twr = Trtp x 2 back when I first started overclocking these kits.
> 
> View attachment 2565491


Ok, go for 14/7, 14/6 doesn't add up.


----------



## Melan

Received my 5600 today.








FCLK hole at 1900 and max at 2000 which rains down error 19.
Going 4000/2000 needs a lot of effort and likely not happening with 4 DIMMs.
3866 with 16-19-19 bluescreens almost immediately, 16-20-20 throws errors 0 and 1, so does 17-20-20.
1T and GDM don't have PHYRDL mismatch (like on 3600) but doesn't boot sometimes.

Edit: TM5 started throwing a lot of error 2 with universal cfg + roasting with furmark. 
Appears to have been fixed with tRFC 512

Yet another edit: Timings are stable but I keep getting occasional bus/interconnect error when running linpack. Reducing vsoc to 1.05 made it appear less but it still happens.
For now old 3733 setup works better :\


----------



## XPEHOPE3

Maybe it's common knowledge but I just came across what FIT stands for (Failures In Time) and wanted to share:


Spoiler: screenshot


----------



## TwilightRavens

It took forever but i got all 4 x 16GB 3600MHz b-die at least 300% memtest stable, for those who are also trying it I had to set procODT to 48-53.3, SoC to 1.15 VDDP to 1.050v and DRAM voltage to 1.452v.


----------



## Blackfyre

Taraquin said:


> Ok, go for 14/7, 14/6 doesn't add up.


Tested 14/6 last night, still got 1 error. Today I will test 14/7 and hopefully that removes the error. Even managed to get tRAS down to 26.

If that doesn't fix it, then I believe tRCDWR has to be increased from 10 to 11 as per previous successful runs.


----------



## Blameless

Blackfyre said:


> Tested 14/6 last night, still got 1 error. Today I will test 14/7 and hopefully that removes the error. Even managed to get tRAS down to 26.
> 
> If that doesn't fix it, then I believe tRCDWR has to be increased from 10 to 11 as per previous successful runs.
> View attachment 2565545


There is no reason for tRC to not be tRAS + tRP. If you can't reduce yours to 40, it means your tRAS is too low.


----------



## The_King

Taraquin said:


> I have run my Viper 4400c19 at 4000cl16 for over a year now. They can run very low ProcODT fine (28), but you must probably raise VDD18 for them to scale positive above 3800. I need 1.88v, lower or higher gets me worse performance. At ProcODT 32 I needed 1.84v. At 4066 I bet you need 1.84-1.88 with your current ProcODT. If you run CWL at 16 you can probably do 8 on RDWR, that is more beneficial. My kit hates low CWL even if I raise RDWR by 1 or 2. WRRD can do 1, WTRS\WTRL probably 3 and 9\10. You have a slightly better bin than me, I need 1.46V at 4000 with about the same timings as you except my RFC is at 280. 288 or 296 will probably work fine for you.
> 
> Do you get WHEA19 btw?


I have never adjusted VDD18 ever. Not sure where that option is on B450? 🤦‍♂️🤦‍♂️ I was told several times by @Bloax to change that but never found that option in the BIOS. 
If Auto works i leave it.  CPU +1.8V always shows 1.840 on HWINFO.

CDWR 8 caused Y-cruncher to fail so its back at 16. (These are Patriot Viper 4400 C19 mixed with G.Skill 4266 C19)

Decided to go with this for daily because it required less voltage than 3800 CL15 and getting good performance overall.


----------



## PJVol

XPEHOPE3 said:


> Maybe it's common knowledge


Not sure to which extent it's common, but I thought you've learned it in a discussion with truly yours:



> FIT is not actually throttle, rather SMU on every iteration check FIT current value, which is a function of voltage and temperature (silicon failure rate), measured by PSM's and by the thermal network respectively. Calculated aggregate FIT value then is held a notch below the target reliability value that depends on process node characteristics as well


Making sense of AMD and The Stilt's information...



Taraquin said:


> At 4066 I bet you need 1.84-1.88 with your current ProcODT


He has almost the same board as the one I've ran my 5600x and was surprised that unlike with an asrock b550 board, 2x8g ddr 4000 could run without any scaling issues, whea-free and without touching cpu 1.8 voltage (msi bios could have labeled it as 1P8).


----------



## Blackfyre

Blameless said:


> There is no reason for tRC to not be tRAS + tRP. If you can't reduce yours to 40, it means your tRAS is too low.


tRC is stable at 53, lower than that and it's not 100% anymore.

I've heard there is no reason to not have tRAS + tRP = tRC, but decreasing tRAS improves read speed and copy speeds in both AIDA & OCCT.

So tRAS (*39*) + tRP (*14*) = tRC (*53*) which you say should not make a difference, performs worse than tRAS (*28*) + tRP (*14*) = tRC (*53*).


----------



## Taraquin

Blackfyre said:


> Tested 14/6 last night, still got 1 error. Today I will test 14/7 and hopefully that removes the error. Even managed to get tRAS down to 26.
> 
> If that doesn't fix it, then I believe tRCDWR has to be increased from 10 to 11 as per previous successful runs.
> View attachment 2565545


Keep RAS+RP=RC so unless you can lower RC keep RAS at 39. RCDRW matters little for performance, may aswell keep it equal to RCDRD.


----------



## Taraquin

PJVol said:


> Not sure to which extent it's common, but I thought you've learned it in a discussion with truly yours:
> 
> 
> Making sense of AMD and The Stilt's information...
> 
> 
> He has almost the same board as the one I've ran my 5600x and was surprised that unlike with an asrock b550 board, 2x8g ddr 4000 could run without any scaling issues, whea-free and without touching cpu 1.8 voltage (msi bios could have labeled it as 1P8).


That's interesting. Wonder if it's the board or IO-die that makes the difference? Was this also Viper 4400?


----------



## Taraquin

The_King said:


> I have never adjusted VDD18 ever. Not sure where that option is on B450? 🤦‍♂️🤦‍♂️ I was told several times by @Bloax to change that but never found that option in the BIOS.
> If Auto works i leave it.  CPU +1.8V always shows 1.840 on HWINFO.
> 
> CDWR 8 caused Y-cruncher to fail so its back at 16. (These are Patriot Viper 4400 C19 mixed with G.Skill 4266 C19)
> 
> Decided to go with this for daily because it required less voltage than 3800 CL15 and getting good performance overall.
> View attachment 2565550
> View attachment 2565551


On my setup using ProcODT I get lower perf in Y-cruncher using 1.8v vdd18 running 4000 that is. Scaling above 3800 is better using 1.88v, but seems there is a lot of variance between setups.


----------



## PJVol

Taraquin said:


> Wonder if it's the board or IO-die that makes the difference?


I meant it is the same cpu (5600x) that spamming the wheas on my asrock board and throttles everything as hell unless being calmed with a vdd18 ~ 2.05-2.10V.
It's not an easy task to track real whea 19 source. I found that whea report only mentioned PIE controller as the source, but that's obvious, since it's purpose to raise interrupts when something is wrong with fabric IPs.
The real source of error should be available through not existing MCA SYND info.

Regarding the reason for such differences, my thoughts are primarily around the VRM design. Something in the whole AM4 system turned out to be very sensitive to its specifics. This I think the main culprit for the annoying stability issues out of nowhere as reported by many users.


----------



## Taraquin

PJVol said:


> I meant it is the same cpu (5600x) that spamming the wheas on my asrock board and throttles everything as hell unless being calmed with a vdd18 ~ 2.05-2.10V.
> It's not an easy task to track real whea 19 source. I found that whea report only mentioned PIE controller as the source, but that's obvious, since it's purpose to raise interrupts when something is wrong with fabric IPs.
> The real source of error should be available through not existing MCA SYND info.
> 
> Regarding the reason for such differences, my thoughts are primarily around the VRM design. Something in the whole AM4 system turned out to be very sensitive to its specifics. This I think the main culprit for the annoying stability issues out of nowhere as reported by many users.


I haven't tested my 5600X on other boards, but I have no WHEA19 even at 4133 (haven't booted 4200 or above since I must disable PCIE 4.0 then according to Veii). The 2 last setups I helped build/tune:
5600X
B550 Tomahawk
Massive WHEA19 above 3800

5600X
B450 Aorus elite
Massive WHEA19 above 3666

Both on agesa 1.2.0.3b/c

My board layout is much simpler, I suspect that is one reason why I don't get WHEA19s.


----------



## The_King

PJVol said:


> I meant it is the same cpu (5600x) that spamming the wheas on my asrock board and throttles everything as hell unless being calmed with a vdd18 ~ 2.05-2.10V.
> It's not an easy task to track real whea 19 source. I found that whea report only mentioned PIE controller as the source, but that's obvious, since it's purpose to raise interrupts when something is wrong with fabric IPs.
> The real source of error should be available through not existing MCA SYND info.
> 
> Regarding the reason for such differences, my thoughts are primarily around the VRM design. Something in the whole AM4 system turned out to be very sensitive to its specifics. This I think the main culprit for the annoying stability issues out of nowhere as reported by many users.


Is it safe to run VDD18 that high for daily?

@Taraquin what motherboard are you running that has no were errors with your 5600X, a 2 DIMM slot board?

So for WHEA 19 the board is just has important to be error free.


----------



## Taraquin

The_King said:


> Is it safe to run VDD18 that high for daily?
> 
> @Taraquin what motherboard and you running that has no were errors with your 5600X, a 2 DIMM slot board?
> 
> So for WHEA 19 the board is just has important to be error free.


Gigabyte B550m S2H. A cheap budget board that I bought due to having 2 dimm slots and a basic vrm heatsink. I decided on it after seing that the predecessor B450 S2H was able to run Zen+ based CPUs up to 3800 without problems, that made me think that ram OC would be good due to a simple 2 dimm design. Turns out it was a good deal as I get better performance vs the 2 other setups I helped with which has much more expensive boards. I have less ports etc though, but enough for my needs.


----------



## PJVol

The_King said:


> Is it safe to run VDD18 that high for daily?


I don't think it safe. 24/7 setup is running mem/fabric @1900Mhz and vdd18 auto (1.824V)



Taraquin said:


> I haven't tested my 5600X on other boards, but I have no WHEA19 even at 4133


Below is a couple screens I found on my home PC made when testing 5600x/b450m mortar.
Besides the usual AIDA and DRAM calc membench, the most revealing are two Sandra tests (with intensive use of vector math and FFT) on both machine. Take note of the differences between 1900 and 2000+ in GEMM multiply tests on either platform.


----------



## XPEHOPE3

PJVol said:


> I thought you've learned it in a discussion with truly yours


That discussion didn't explain the abbreviation as well as exact meaning. But it was pretty close


----------



## PJVol

XPEHOPE3 said:


> That discussion didn't explain the abbreviation as well as exact meaning


You just didn't ask


----------



## The_King

PJVol said:


> I don't think it safe. 24/7 setup is running mem/fabric @1900Mhz and vdd18 auto (1.824V)
> 
> 
> Below is a couple screens I found on my home PC made when testing 5600x/b450m mortar.
> Besides the usual AIDA and DRAM calc membench, the most revealing are two Sandra tests (with intensive use of vector math and FFT) on both machine. Take note of the differences between 1900 and 2000+ in GEMM multiply tests on either platform.


This is why I went with 3800/1900 for daily, It does bench higher its probably the sweet spot for ZEN 3.

In 7-Zip Bench the difference can been seen but this was 4000 CL16 vs 3800 CL16


----------



## Melan

PJVol said:


> I don't think it safe. 24/7 setup is running mem/fabric @1900Mhz and vdd18 auto (1.824V)


Do you know by any chance if HWinfo reports vdd18 voltage on MSI boards? Only thing I found similar (that actually shows something around 1.8v) was VTT which reports 1.85v on auto.


----------



## Taraquin

PJVol said:


> I don't think it safe. 24/7 setup is running mem/fabric @1900Mhz and vdd18 auto (1.824V)
> 
> 
> Below is a couple screens I found on my home PC made when testing 5600x/b450m mortar.
> Besides the usual AIDA and DRAM calc membench, the most revealing are two Sandra tests (with intensive use of vector math and FFT) on both machine. Take note of the differences between 1900 and 2000+ in GEMM multiply tests on either platform.


Quite a bit of throttling on higher fclk in Sandra it seems. After adjusting VDD18 to 1.88v I get equal score in Y-cruncher, but SOTTR fps is about 2% higher with 4000cl16 vs 3800cl15, aida and calc test 2-3% faster.


----------



## The_King

Melan said:


> Do you know by any chance if HWinfo reports vdd18 voltage on MSI boards? Only thing I found similar (that actually shows something around 1.8v) was VTT which reports 1.85v on auto.


IT should be the CPU +1.8V


----------



## PJVol

Taraquin said:


> After adjusting VDD18 to 1.88v I get equal score in Y-cruncher


Have you got any regression in a 7zip benchmark at 2000?


----------



## Valka814

Have no progress yet with the suggestions, but...is it good if I can use a lower procODT? So far 32 Ohm looks stable.


----------



## Taraquin

PJVol said:


> Have you got any regression in a 7zip benchmark at 2000?


I haven't tried that one, but all benches I tried after adjusting VDD18 got identical or up to 3% better scores vs 3800cl15.


----------



## Melan

The_King said:


> IT should be the CPU +1.8V


I played around with CPU 1P8 voltage in bios and turns out that VTT was actually 1P8 :\
Going to rename it in hwinfo so it doesn't confuse me anymore.
Weird that it shows 50mv more than w/e value I have set.


----------



## Bloax

Yeah, actually finding CPU 1.8v 1P8 Standby Voltage whats-its-name is usually a case of just _looking_ for voltages that either are around 1.8v or mention being 1.8v by default.
It's "CPU AUX voltage" on my z690 MSI board

It would make sense that it would be ""VTT"" based on the fact that VTT (something something termination voltage) is by default, half of DRAM voltage. (vDIMM)
3.6 vDIMM is a little unusual to see here in DDR4 land 🤡


----------



## Sir Beregond

I'm not really familiar with RAM overclocking, where does one start?


----------



## Blameless

Blackfyre said:


> So tRAS (*39*) + tRP (*14*) = tRC (*53*) which you say should not make a difference, performs worse than tRAS (*28*) + tRP (*14*) = tRC (*53*).


I didn't say it wouldn't make any difference, but unless you are gaining significant performance by having tRAS so low, it's one of the first places I'd look for low-hanging fruit to improve stability and/or be able to tighten up more meaningful timings.



Sir Beregond said:


> I'm not really familiar with RAM overclocking, where does one start?


Probably with identifying the specific ICs in your memory so you have a ballpark idea of what should be possible with them.


----------



## Sir Beregond

Blameless said:


> Probably with identifying the specific ICs in your memory so you have a ballpark idea of what should be possible with them.


This was just a kit I saw at Micro Center.


----------



## Bloax

I'm sorry about your Hynix DJR curse, I just posted a primarily samsung b-die guide lol
oh well someone might find it useful


Sir Beregond said:


> I'm not really familiar with RAM overclocking, where does one start?


First, most important step: Know your tools and what they are useful for (Safemode abuse, TM5, y-cruncher)




(more info also in video description LoL)

Next up:

- Start real slow ..
-> if using Samsung 8 gbit B sticks - run tCL/tRCD/tRP at 18-18-18, tRAS 36 (tRCD + tCL), tRC 54 (tRAS + tRP), tRFC 432-321-197
(order: tRFC-tRFC2-tRFC4)
(tRFC = tRC * 8, tRFC2 = tRFC/1.346, tRFC4 = tRFC/2.1875, avoid uneven tRFC1 values they tend to be explosive on AM4)
tCWL should be the same as tCL, unless tCL is uneven in which case you need to run tCWL at an even value with +1 to RDWR (when setting it manually)

At those settings, you probably won't need more than 1.4v DRAM voltage even at silly frequencies for Vermeer (DDR4 4000-4200)
Probably start at DDR4-3600

To go easy, but not XMP-easy, run tRRDS at 6, its brother tRRDL at 7, and tFAW at 24 (4x RRDS, though you can also use 4x WTRS)
Running tWTRS 6 and tWTRL 14 may or may not be necessary, it's a little overkill as WTR 4/12 (s/L) tends to ""work"".

Shamefully, keep RDWR and WRRD on auto :--DD
rdrd/wrwr tertiaries can also be kept on auto

RDRD_SCL and WRWR_SCL pretty much universally want to be 4

tRTP and tWR are connected, and usually tWR wants to be 2x of RTP (i.e. RTP 7 + tWR 14, RTP 8 + tWR 16 ..)
Sometimes sticks will want a specific kind of combination, and not necessarily one that follows this Rule of Thumb (e.g. RTP 8 + tWR 12 is one I've seen)"
Sometimes sticks will have a range of valid combinations (e.g. 5/10, 6/12, 7/14 are all ok, higher are not), sometimes they will have one (5/10), possibly two very far apart (5/10 + 12/24) but I haven't personally seen it.

This will likely be the first timing combo you will have to figure out to stop random errors, in TM5 they usually produce errors #2, #10 and #12 or some similar minor-timeout-error, it's been a while.
So don't be surprised if it errors when you initially throw, for example, tRTP 8 + tWR 16 at it - try RTP 7 + tWR 14 next, then RTP 6 + 12, then 5 + 10, then 6 + 14, then 6 + 16, then 7 + 16, 5 + 12, 5 + 14 .. until those minor timeout errors stop.

Usually, then RTT Nom/6 (40 ohm), Wr/3 (80 ohm), Park/3 (80 ohm) is a good "starting point" for Samsung B sticks, and procODT 36.9 tends to not be offensive without raising CPU 1.8v-whats-its-name

On Vermeer, 1800 FCLK should run "acceptably" with something like 1.05vSOC, 1.0v IOD, 0.9v CCD (? kinda high ?), and VDDP can be left at a not-too-high 0.9v too

- Start figuring out what RTT/procODT your sticks actually want
-> This is done by first having them stable at a lower frequency, then increasing the DRAM frequency - without raising FLCK - until it doesn't want to go further. Memory voltage shouldn't be a problem at such loose primary timings.
Then you keep on trying to boot the higher frequency further, while testing one set of termination combos at a time.
(order: Nom/Wr/Park) e.g. 6/3/3 fails, try 6/3/4, 6/3/5, 6/3/6, then 7/3/3, 7/3/4, 7/3/5, 7/3/6, then 6/2/3, 6/2/4, 6/2/5, 6/2/6, then 7/2/3, 7/2/4, 7/2/5, 7/2/6 .. 5/3/3 ...
Beware of Wr/1, it can be a little dangerous at higher voltages, and Park/1 and /2 combined with Wr/2 or Wr/1 are to be tried at your own sticks' peril 

If that fails, try going up or down a step in procODT and going through them again, then the opposite step of up/down in procODT, then two steps...

Usually though, you'll find one that works at 3800-4000+ sooner rather than later, and that one is usually Good Enough. Run that one at DDR4-3600 again.

- Proceed to disable Gear Down Mode, set Command Rate to 1T (if it wasn't), set tCKE to 7
(tCKE requirements go up by +2 every multiple of roughly 100 MCLK, so it's 9 at 1900 MCLK but also 1966 or even 1983, and 11 at 2000-2090 ..)
(MCLK is half of DDR4-[speed], so 1983 MCLK is DDR4-3966 -- don't worry too much about these BCLK-powered intermediate values, I just post them for overall clarity)

Doing this will now force you to find a set of working CADBus impedances to be stable :--DDD
note: some recent dual-rank kits "don't want to work at 1T at all", and require the "AddrCmdSetup" CAD Setup timing set to 56 to function at this command rate.
if yours only POSTs at 2T, this may be why



veii said:


> ....You should see 4 dimms as dual rank behavior - nearly identical to dual rank, with little exceptions....
> 
> -->
> CAD_BUS presets that work well are
> 60-20-40-20
> 60-20-20-24
> 40-20-40-20
> 40-20-30-24
> 24-20-24-24
> 
> 3rd value bellow 30 causes training issues for Vermeer, but has to be used when procODT is high
> 24-20-24-24 or 24-20-20-24 only works with wastefully high procODT
> But neither procODT nor cLDO_VDDP have to be pushed for FCLK and not for memory timings stability or training stability
> ^ doing so degrades signal integrity too much. Using CAD_BUS is the right way


Usually it'll be somewhere around 40-20-30-20, plus or minus a step on any of the values. Annoying step, full of memory testing DD DDD

Once you find one that behaves itself, you are ready to..


- Measure +MCLK voltage scaling requirements
-> Quite simply, find the minimal stable voltage for the current configuration - then see how much this Minimum Goldilocks Voltage changes when you try a lower, or higher, frequency.
Usually this ends up being in the 0.06 to 0.08v range

This is somewhat affected by RTT/CADBus, so that's why you do those first!

- Measure -Primaries voltage scaling requirements
-> The same thing as above, but now instead of seeing the change for frequency, we now look at how the Voltage Requirement(tm) changes when changing all the primary timings (this is a Sammy B exclusive in DDR4)
e.g. 3800 18-18-18 to 3800 17-17-17, then to 3800 16-16-16 - how much more voltage did those steps require?
You can then guess that 3800 15-15-15 will require just as much more voltage, same for 3800 14-14-14 -- until you start hitting the limits of your sticks, which either require much more voltage to overcome, or stop ever being stable.


I should note, that due to the "handy relationships" mentioned at the start --


> -> if using Samsung 8 gbit B sticks - run tCL/tRCD/tRP at 18-18-18
> tRAS 36 (tRCD + tCL)
> tRC 54 (tRAS + tRP)
> tRFC 432-321-197 (tRFC = tRC * 8, tRFC2 = tRFC/1.346, tRFC4 = tRFC/2.1875)
> (avoid uneven tRFC1 values they tend to be explosive on AM4)


then every time we go up and down, we'll have to change *all of those values*.

So 17-17-17 primaries mean tRAS 34, and tRC 51, alongside tRFC 408-303-187 -- and so on for 16-16-16
Don't forget to set tCWL to tCL (or tCL-1 for uneven values of tCL), hehe, I've sometimes done so 🤡

don't worry about the high tRFC it's just there in case a RAMFAN isn't utilized and we accidentally trip up somebody new with temperature errors )
it can be pushed down to tRC * 7 or tRC * 6 if the sticks aren't sensitive or if cooling is good enough


- Figure out what voltages your memory controller wants at the highest frequency that doesn't insta-pop
..this is more of an intel point I had written down you are free to skip it or..
You are free to discover what FCLK your CPU tops out at, and what the lowest VDDP is required to run the corresponding memory frequency.

- Get your Actual Performance settings to something less ridiculously suboptimal
Simply put, see how low RRD and WTR want to go without being unstable.
Usually this will be RRDS 4, RRDL 6 and WTRS 4 / WTRL 12 on dual-rank sticks, though some may run WTRL 8, and CPU1.8v-VDD18-whatsitsname tricks alongside decreasing procODT may allow even those that didn't want to do WTRL 8 to do so.

Don't forget to set tFAW to 4x of RRDS when you do this, otherwise you won't see GAINZ 
You could do this earlier, but it's good not to disrupt the Maximum Frequency + Blind RTT/ProcODT search where running these too low might force a lower maximum frequency, and thus possibly missing the Just Right RTT combo. (e.g. 6/3/6 was the only one to POST 4600 16-16-16 on my Viper 4000 16-16-16 sticks)

After this, try and see how low RDWR/WRRD go, usually dual-rank sticks don't want to do WRRD below 3 (some do!) and RDWR could be anything between 8 (unlikely) to 14 (unlucky)

- Confirm stability
lol
- Measure performance, note down settings
it's good to have references of your Progress

-- nondescript GOING HARDER process --


Proceed to push memory system to your voltage comfort limits
Measure performance along the way (must be stable to work LOL), keep noting down setting progression
Check if cranking CPU 1.8v (DRAM input voltage, CPU 1P8, CPU AUX ..) voltage lets you slam procODT lower
Check if this lets you run better Actual Performance (wtr/rrd/ccd) settings
Measure performance to see what wacky combos work best
Confirm stability
???




ok i let this brain vomit out thanks i am donezo


----------



## Blackfyre

Taraquin said:


> Keep RAS+RP=RC so unless you can lower RC keep RAS at 39. RCDRW matters little for performance, may aswell keep it equal to RCDRD.


Yes, I will change it next, but I managed to lower it all the way to 21 without issues. 

This one is crazy though, I finally thought I figured it out, I had tRDRDSD set to 3 before, and tWRWRSD set to 3 as well. I changed them to match their counter, so it became 4 & 4 and 6 & 6, and I had ZERO errors overnight. I woke up and saw the PC at 49 cycles with 0 errors. I went to take the screenshot to say I figured out the issue and now it's resolved, and just before I took the picture, I got 1 error 😂 *which makes me think even 50 cycles is not enough because an error could pop up after that too?* I had always assumed if I pass 50 cycles then that should be enough for anything.










Blameless said:


> I didn't say it wouldn't make any difference, but unless you are gaining significant performance by having tRAS so low, it's one of the first places I'd look for low-hanging fruit to improve stability and/or be able to tighten up more meaningful timings.


Thank you too for the input, I will change tRAS, as per @Taraquin recommendation and see if that prevents the error, maybe tomorrow I will run 60 cycles just to be sure.


----------



## Sir Beregond

Bloax said:


> I'm sorry about your Hynix DJR curse, I just posted a primarily samsung b-die guide lol


Yeah I didn't really know at the time. I might buy something else.


----------



## Bloax

Blackfyre said:


> I had always assumed if I pass 50 cycles then that should be enough for anything.


With 32 GB of RAM getting an error after 50 cycles (6 hours of constant measure-time) you're mostly just catching random powerline surges - presumably you're not on a beefy Uninterruptible Power Supply? - or the kind of cosmic-ray errors ECC is meant to prevent.

Well that or the World Famous tRAS/tRC Repeats (all rights reserved) finally don't cover-up everything, but that's unlikely to result in a #0, a super short drop in input voltage not caught by your measurement interval however probably could cause just such an error. 🤡 🥧


----------



## Blackfyre

Bloax said:


> With 32 GB of RAM getting an error after 50 cycles (6 hours of constant measure-time) you're mostly just catching random powerline surges - presumably you're not on a beefy Uninterruptible Power Supply? - or the kind of cosmic-ray errors ECC is meant to prevent.
> 
> Well that or the World Famous tRAS/tRC Repeats (all rights reserved) finally don't cover-up everything, but that's unlikely to result in a #0, a super short drop in input voltage not caught by your measurement interval however probably could cause just such an error. 🤡 🥧


I think I figured it out. I use a 4K TV as a monitor. And when I turn it on, the driver cycles (_I hear the di-ding Windows sound for when a new device is plugged in_), and that's what causes the error after turning the display on after a long period.

To confirm, I TM5 again. Turned the TV on when it was 2 cycles in, and I got that 1 error. Then I ran TM5 again, and left the TV turned on and it has reached 11 cycles so far with no error.

Interesting.

*PS:* My power supply has lasted through 3 system upgrades, it's the only thing still standing strong alongside my NH-D15.

*EVGA SuperNOVA 1000 G2, 80+ GOLD*


----------



## The Sandman

ioannis91 said:


> Hello guys. I've updated to latest AGESA 1.2.0.7 and the configuration that used to work in 1.2.0.5 does not work anymore. That's the timings.
> On 1.2.0.5 I used to do 24/24/24/24 DvrStr, but on 1.2.0.7 it gave me error number 8. I tried 40/24/24/24 and it gave me error 10. Any ideas?


Try 24-20-24-24 if you haven't already.


----------



## Blameless

Sir Beregond said:


> Yeah I didn't really know at the time. I might buy something else.


Still a lot of room to tune that DJR stuff.

Most of Bloax's guide will still apply, you just won't be able to tighten the primaries, tRTP, or tRFC anywhere near as much, and you'll probably want weaker drive strengths (higher output impedance/Rtt values).



Bloax said:


> With 32 GB of RAM getting an error after 50 cycles (6 hours of constant measure-time) you're mostly just catching random powerline surges - presumably you're not on a beefy Uninterruptible Power Supply? - or the kind of cosmic-ray errors ECC is meant to prevent.


Radiation errors on 32GiB of memory is more of a once every 6-12 month sort of thing, unless you live on top of a mountain or have some sort of radon problem. AC issues could certainly cause problems, but if the power supply and board are quality, even very dirty power is well within one's ability to stabilize.

One error every six, or even twenty-four, hour is usually a very correctable stability problem, rather than an inevitable single-event fluke.



Blackfyre said:


> I think I figured it out. I use a 4K TV as a monitor. And when I turn it on, the driver cycles (_I hear the di-ding Windows sound for when a new device is plugged in_), and that's what causes the error after turning the display on after a long period.
> 
> To confirm, I TM5 again. Turned the TV on when it was 2 cycles in, and I got that 1 error. Then I ran TM5 again, and left the TV turned on and it has reached 11 cycles so far with no error.
> 
> Interesting.
> 
> *PS:* My power supply has lasted through 3 system upgrades, it's the only thing still standing strong alongside my NH-D15.
> 
> *EVGA SuperNOVA 1000 G2, 80+ GOLD*


Might want to consider a new PSU and/or a better surge suppressor, perhaps a line conditioner. In the mean time, see if you can move the TV to a different circuit.


----------



## KedarWolf

My highest latency is 59.4.



Code:


SiSoftware Sandra

Benchmark Results
Aggregate Inter-Thread Bandwidth : 177.82GB/s
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Benchmark Results
Average Inter-Thread Latency : 39.2ns (9.5ns - 59.4ns)
Inter-Thread (same Core) Latency : 9.7ns
Inter-Core (same Module) Latency : 20.6ns
Inter-Module (same Package) Latency : 57.4ns
Results Interpretation : Lower Scores mean Better Performance.
Decimal Numeral System (base 10) : 1s = 1000ms, 1ms = 1000µs, 1µs = 1000ns, etc.

Performance per Thread
Aggregate Inter-Thread Bandwidth : 5.56GB/s
No. Threads : 32
Results Interpretation : Higher Scores mean Better Performance.
Binary Numeral System (base 2) : 1GB(/s) = 1024MB(/s), 1MB(/s) = 1024kB(/s), 1kB(/s) = 1024 bytes(/s), etc.

Performance vs. Power
Processor(s) Power : 105.00W
Aggregate Inter-Thread Bandwidth : 1734.14MB/s/W
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 3.73ns/W
Results Interpretation : Lower Scores mean Better Performance.

Capacity vs. Power
Total Cache Size : 707.05kB/W
Results Interpretation : Higher Scores mean Better Performance.

Performance vs. Speed
Aggregate Inter-Thread Bandwidth : 37.35MB/s/MHz
Results Interpretation : Higher Scores mean Better Performance.
Average Inter-Thread Latency : 0.08ns/MHz
Results Interpretation : Lower Scores mean Better Performance.

Detailed Results
Processor Affinity : U0-U1 U2-U3 U4-U5 U6-U7 U8-U9 U10-U11 U12-U13 U14-U15 U16-U17 U18-U19 U20-U21 U22-U23 U24-U25 U26-U27 U28-U29 U30-U31
U0-M0C0T0 <> U2-M0C1T0 Data Latency : 18.1ns
U0-M0C0T0 <> U4-M0C2T0 Data Latency : 19.9ns
U0-M0C0T0 <> U6-M0C3T0 Data Latency : 19.0ns
U0-M0C0T0 <> U8-M0C4T0 Data Latency : 20.5ns
U0-M0C0T0 <> U10-M0C5T0 Data Latency : 19.3ns
U0-M0C0T0 <> U12-M0C6T0 Data Latency : 21.2ns
U0-M0C0T0 <> U14-M0C7T0 Data Latency : 20.2ns
U0-M0C0T0 <> U16-M1C0T0 Data Latency : 55.5ns
U0-M0C0T0 <> U18-M1C1T0 Data Latency : 55.9ns
U0-M0C0T0 <> U20-M1C2T0 Data Latency : 56.2ns
U0-M0C0T0 <> U22-M1C3T0 Data Latency : 56.7ns
U0-M0C0T0 <> U24-M1C4T0 Data Latency : 57.4ns
U0-M0C0T0 <> U26-M1C5T0 Data Latency : 56.5ns
U0-M0C0T0 <> U28-M1C6T0 Data Latency : 57.1ns
U0-M0C0T0 <> U30-M1C7T0 Data Latency : 57.2ns
U0-M0C0T0 <> U1-M0C0T1 Data Latency : 9.6ns
U0-M0C0T0 <> U3-M0C1T1 Data Latency : 18.4ns
U0-M0C0T0 <> U5-M0C2T1 Data Latency : 20.0ns
U0-M0C0T0 <> U7-M0C3T1 Data Latency : 19.0ns
U0-M0C0T0 <> U9-M0C4T1 Data Latency : 20.5ns
U0-M0C0T0 <> U11-M0C5T1 Data Latency : 19.3ns
U0-M0C0T0 <> U13-M0C6T1 Data Latency : 21.2ns
U0-M0C0T0 <> U15-M0C7T1 Data Latency : 20.1ns
U0-M0C0T0 <> U17-M1C0T1 Data Latency : 55.7ns
U0-M0C0T0 <> U19-M1C1T1 Data Latency : 55.5ns
U0-M0C0T0 <> U21-M1C2T1 Data Latency : 56.4ns
U0-M0C0T0 <> U23-M1C3T1 Data Latency : 56.4ns
U0-M0C0T0 <> U25-M1C4T1 Data Latency : 57.4ns
U0-M0C0T0 <> U27-M1C5T1 Data Latency : 56.4ns
U0-M0C0T0 <> U29-M1C6T1 Data Latency : 57.2ns
U0-M0C0T0 <> U31-M1C7T1 Data Latency : 57.4ns
U2-M0C1T0 <> U4-M0C2T0 Data Latency : 18.8ns
U2-M0C1T0 <> U6-M0C3T0 Data Latency : 19.0ns
U2-M0C1T0 <> U8-M0C4T0 Data Latency : 19.5ns
U2-M0C1T0 <> U10-M0C5T0 Data Latency : 19.3ns
U2-M0C1T0 <> U12-M0C6T0 Data Latency : 20.1ns
U2-M0C1T0 <> U14-M0C7T0 Data Latency : 20.1ns
U2-M0C1T0 <> U16-M1C0T0 Data Latency : 55.5ns
U2-M0C1T0 <> U18-M1C1T0 Data Latency : 55.3ns
U2-M0C1T0 <> U20-M1C2T0 Data Latency : 56.4ns
U2-M0C1T0 <> U22-M1C3T0 Data Latency : 56.0ns
U2-M0C1T0 <> U24-M1C4T0 Data Latency : 57.2ns
U2-M0C1T0 <> U26-M1C5T0 Data Latency : 56.2ns
U2-M0C1T0 <> U28-M1C6T0 Data Latency : 57.3ns
U2-M0C1T0 <> U30-M1C7T0 Data Latency : 57.0ns
U2-M0C1T0 <> U1-M0C0T1 Data Latency : 18.2ns
U2-M0C1T0 <> U3-M0C1T1 Data Latency : 9.7ns
U2-M0C1T0 <> U5-M0C2T1 Data Latency : 18.9ns
U2-M0C1T0 <> U7-M0C3T1 Data Latency : 19.1ns
U2-M0C1T0 <> U9-M0C4T1 Data Latency : 19.5ns
U2-M0C1T0 <> U11-M0C5T1 Data Latency : 19.3ns
U2-M0C1T0 <> U13-M0C6T1 Data Latency : 20.1ns
U2-M0C1T0 <> U15-M0C7T1 Data Latency : 20.2ns
U2-M0C1T0 <> U17-M1C0T1 Data Latency : 55.5ns
U2-M0C1T0 <> U19-M1C1T1 Data Latency : 55.3ns
U2-M0C1T0 <> U21-M1C2T1 Data Latency : 56.3ns
U2-M0C1T0 <> U23-M1C3T1 Data Latency : 56.1ns
U2-M0C1T0 <> U25-M1C4T1 Data Latency : 57.3ns
U2-M0C1T0 <> U27-M1C5T1 Data Latency : 56.1ns
U2-M0C1T0 <> U29-M1C6T1 Data Latency : 57.2ns
U2-M0C1T0 <> U31-M1C7T1 Data Latency : 56.9ns
U4-M0C2T0 <> U6-M0C3T0 Data Latency : 19.4ns
U4-M0C2T0 <> U8-M0C4T0 Data Latency : 21.3ns
U4-M0C2T0 <> U10-M0C5T0 Data Latency : 20.3ns
U4-M0C2T0 <> U12-M0C6T0 Data Latency : 21.9ns
U4-M0C2T0 <> U14-M0C7T0 Data Latency : 20.9ns
U4-M0C2T0 <> U16-M1C0T0 Data Latency : 56.0ns
U4-M0C2T0 <> U18-M1C1T0 Data Latency : 56.1ns
U4-M0C2T0 <> U20-M1C2T0 Data Latency : 56.8ns
U4-M0C2T0 <> U22-M1C3T0 Data Latency : 56.9ns
U4-M0C2T0 <> U24-M1C4T0 Data Latency : 57.9ns
U4-M0C2T0 <> U26-M1C5T0 Data Latency : 57.2ns
U4-M0C2T0 <> U28-M1C6T0 Data Latency : 58.0ns
U4-M0C2T0 <> U30-M1C7T0 Data Latency : 57.9ns
U4-M0C2T0 <> U1-M0C0T1 Data Latency : 20.0ns
U4-M0C2T0 <> U3-M0C1T1 Data Latency : 19.1ns
U4-M0C2T0 <> U5-M0C2T1 Data Latency : 9.7ns
U4-M0C2T0 <> U7-M0C3T1 Data Latency : 19.4ns
U4-M0C2T0 <> U9-M0C4T1 Data Latency : 21.3ns
U4-M0C2T0 <> U11-M0C5T1 Data Latency : 20.3ns
U4-M0C2T0 <> U13-M0C6T1 Data Latency : 21.9ns
U4-M0C2T0 <> U15-M0C7T1 Data Latency : 20.9ns
U4-M0C2T0 <> U17-M1C0T1 Data Latency : 56.0ns
U4-M0C2T0 <> U19-M1C1T1 Data Latency : 56.4ns
U4-M0C2T0 <> U21-M1C2T1 Data Latency : 56.8ns
U4-M0C2T0 <> U23-M1C3T1 Data Latency : 56.8ns
U4-M0C2T0 <> U25-M1C4T1 Data Latency : 57.8ns
U4-M0C2T0 <> U27-M1C5T1 Data Latency : 57.2ns
U4-M0C2T0 <> U29-M1C6T1 Data Latency : 57.7ns
U4-M0C2T0 <> U31-M1C7T1 Data Latency : 57.8ns
U6-M0C3T0 <> U8-M0C4T0 Data Latency : 20.4ns
U6-M0C3T0 <> U10-M0C5T0 Data Latency : 20.2ns
U6-M0C3T0 <> U12-M0C6T0 Data Latency : 20.9ns
U6-M0C3T0 <> U14-M0C7T0 Data Latency : 21.0ns
U6-M0C3T0 <> U16-M1C0T0 Data Latency : 56.1ns
U6-M0C3T0 <> U18-M1C1T0 Data Latency : 56.1ns
U6-M0C3T0 <> U20-M1C2T0 Data Latency : 56.7ns
U6-M0C3T0 <> U22-M1C3T0 Data Latency : 56.6ns
U6-M0C3T0 <> U24-M1C4T0 Data Latency : 57.7ns
U6-M0C3T0 <> U26-M1C5T0 Data Latency : 56.8ns
U6-M0C3T0 <> U28-M1C6T0 Data Latency : 58.3ns
U6-M0C3T0 <> U30-M1C7T0 Data Latency : 57.7ns
U6-M0C3T0 <> U1-M0C0T1 Data Latency : 18.9ns
U6-M0C3T0 <> U3-M0C1T1 Data Latency : 19.3ns
U6-M0C3T0 <> U5-M0C2T1 Data Latency : 19.4ns
U6-M0C3T0 <> U7-M0C3T1 Data Latency : 9.8ns
U6-M0C3T0 <> U9-M0C4T1 Data Latency : 20.4ns
U6-M0C3T0 <> U11-M0C5T1 Data Latency : 20.2ns
U6-M0C3T0 <> U13-M0C6T1 Data Latency : 20.9ns
U6-M0C3T0 <> U15-M0C7T1 Data Latency : 21.0ns
U6-M0C3T0 <> U17-M1C0T1 Data Latency : 56.3ns
U6-M0C3T0 <> U19-M1C1T1 Data Latency : 56.3ns
U6-M0C3T0 <> U21-M1C2T1 Data Latency : 56.9ns
U6-M0C3T0 <> U23-M1C3T1 Data Latency : 56.6ns
U6-M0C3T0 <> U25-M1C4T1 Data Latency : 58.0ns
U6-M0C3T0 <> U27-M1C5T1 Data Latency : 56.7ns
U6-M0C3T0 <> U29-M1C6T1 Data Latency : 58.0ns
U6-M0C3T0 <> U31-M1C7T1 Data Latency : 57.6ns
U8-M0C4T0 <> U10-M0C5T0 Data Latency : 20.7ns
U8-M0C4T0 <> U12-M0C6T0 Data Latency : 22.3ns
U8-M0C4T0 <> U14-M0C7T0 Data Latency : 21.3ns
U8-M0C4T0 <> U16-M1C0T0 Data Latency : 56.6ns
U8-M0C4T0 <> U18-M1C1T0 Data Latency : 56.7ns
U8-M0C4T0 <> U20-M1C2T0 Data Latency : 57.4ns
U8-M0C4T0 <> U22-M1C3T0 Data Latency : 57.3ns
U8-M0C4T0 <> U24-M1C4T0 Data Latency : 58.4ns
U8-M0C4T0 <> U26-M1C5T0 Data Latency : 57.7ns
U8-M0C4T0 <> U28-M1C6T0 Data Latency : 58.2ns
U8-M0C4T0 <> U30-M1C7T0 Data Latency : 58.4ns
U8-M0C4T0 <> U1-M0C0T1 Data Latency : 20.5ns
U8-M0C4T0 <> U3-M0C1T1 Data Latency : 19.7ns
U8-M0C4T0 <> U5-M0C2T1 Data Latency : 21.3ns
U8-M0C4T0 <> U7-M0C3T1 Data Latency : 20.4ns
U8-M0C4T0 <> U9-M0C4T1 Data Latency : 9.6ns
U8-M0C4T0 <> U11-M0C5T1 Data Latency : 20.8ns
U8-M0C4T0 <> U13-M0C6T1 Data Latency : 22.3ns
U8-M0C4T0 <> U15-M0C7T1 Data Latency : 21.3ns
U8-M0C4T0 <> U17-M1C0T1 Data Latency : 56.5ns
U8-M0C4T0 <> U19-M1C1T1 Data Latency : 57.0ns
U8-M0C4T0 <> U21-M1C2T1 Data Latency : 57.5ns
U8-M0C4T0 <> U23-M1C3T1 Data Latency : 57.6ns
U8-M0C4T0 <> U25-M1C4T1 Data Latency : 58.6ns
U8-M0C4T0 <> U27-M1C5T1 Data Latency : 57.8ns
U8-M0C4T0 <> U29-M1C6T1 Data Latency : 58.4ns
U8-M0C4T0 <> U31-M1C7T1 Data Latency : 58.4ns
U10-M0C5T0 <> U12-M0C6T0 Data Latency : 21.2ns
U10-M0C5T0 <> U14-M0C7T0 Data Latency : 21.3ns
U10-M0C5T0 <> U16-M1C0T0 Data Latency : 56.6ns
U10-M0C5T0 <> U18-M1C1T0 Data Latency : 56.5ns
U10-M0C5T0 <> U20-M1C2T0 Data Latency : 57.4ns
U10-M0C5T0 <> U22-M1C3T0 Data Latency : 57.0ns
U10-M0C5T0 <> U24-M1C4T0 Data Latency : 58.7ns
U10-M0C5T0 <> U26-M1C5T0 Data Latency : 57.4ns
U10-M0C5T0 <> U28-M1C6T0 Data Latency : 58.4ns
U10-M0C5T0 <> U30-M1C7T0 Data Latency : 58.1ns
U10-M0C5T0 <> U1-M0C0T1 Data Latency : 19.4ns
U10-M0C5T0 <> U3-M0C1T1 Data Latency : 19.6ns
U10-M0C5T0 <> U5-M0C2T1 Data Latency : 20.2ns
U10-M0C5T0 <> U7-M0C3T1 Data Latency : 20.3ns
U10-M0C5T0 <> U9-M0C4T1 Data Latency : 21.0ns
U10-M0C5T0 <> U11-M0C5T1 Data Latency : 9.5ns
U10-M0C5T0 <> U13-M0C6T1 Data Latency : 21.3ns
U10-M0C5T0 <> U15-M0C7T1 Data Latency : 21.3ns
U10-M0C5T0 <> U17-M1C0T1 Data Latency : 56.7ns
U10-M0C5T0 <> U19-M1C1T1 Data Latency : 56.5ns
U10-M0C5T0 <> U21-M1C2T1 Data Latency : 57.4ns
U10-M0C5T0 <> U23-M1C3T1 Data Latency : 57.2ns
U10-M0C5T0 <> U25-M1C4T1 Data Latency : 58.8ns
U10-M0C5T0 <> U27-M1C5T1 Data Latency : 57.5ns
U10-M0C5T0 <> U29-M1C6T1 Data Latency : 58.1ns
U10-M0C5T0 <> U31-M1C7T1 Data Latency : 58.1ns
U12-M0C6T0 <> U14-M0C7T0 Data Latency : 21.5ns
U12-M0C6T0 <> U16-M1C0T0 Data Latency : 57.2ns
U12-M0C6T0 <> U18-M1C1T0 Data Latency : 57.3ns
U12-M0C6T0 <> U20-M1C2T0 Data Latency : 58.2ns
U12-M0C6T0 <> U22-M1C3T0 Data Latency : 58.1ns
U12-M0C6T0 <> U24-M1C4T0 Data Latency : 59.1ns
U12-M0C6T0 <> U26-M1C5T0 Data Latency : 58.3ns
U12-M0C6T0 <> U28-M1C6T0 Data Latency : 58.9ns
U12-M0C6T0 <> U30-M1C7T0 Data Latency : 59.0ns
U12-M0C6T0 <> U1-M0C0T1 Data Latency : 21.2ns
U12-M0C6T0 <> U3-M0C1T1 Data Latency : 20.5ns
U12-M0C6T0 <> U5-M0C2T1 Data Latency : 21.9ns
U12-M0C6T0 <> U7-M0C3T1 Data Latency : 21.0ns
U12-M0C6T0 <> U9-M0C4T1 Data Latency : 22.2ns
U12-M0C6T0 <> U11-M0C5T1 Data Latency : 21.3ns
U12-M0C6T0 <> U13-M0C6T1 Data Latency : 9.6ns
U12-M0C6T0 <> U15-M0C7T1 Data Latency : 21.7ns
U12-M0C6T0 <> U17-M1C0T1 Data Latency : 57.1ns
U12-M0C6T0 <> U19-M1C1T1 Data Latency : 57.6ns
U12-M0C6T0 <> U21-M1C2T1 Data Latency : 58.0ns
U12-M0C6T0 <> U23-M1C3T1 Data Latency : 58.4ns
U12-M0C6T0 <> U25-M1C4T1 Data Latency : 59.2ns
U12-M0C6T0 <> U27-M1C5T1 Data Latency : 58.1ns
U12-M0C6T0 <> U29-M1C6T1 Data Latency : 58.8ns
U12-M0C6T0 <> U31-M1C7T1 Data Latency : 59.0ns
U14-M0C7T0 <> U16-M1C0T0 Data Latency : 57.2ns
U14-M0C7T0 <> U18-M1C1T0 Data Latency : 57.1ns
U14-M0C7T0 <> U20-M1C2T0 Data Latency : 57.9ns
U14-M0C7T0 <> U22-M1C3T0 Data Latency : 58.0ns
U14-M0C7T0 <> U24-M1C4T0 Data Latency : 59.2ns
U14-M0C7T0 <> U26-M1C5T0 Data Latency : 58.0ns
U14-M0C7T0 <> U28-M1C6T0 Data Latency : 59.2ns
U14-M0C7T0 <> U30-M1C7T0 Data Latency : 58.9ns
U14-M0C7T0 <> U1-M0C0T1 Data Latency : 20.1ns
U14-M0C7T0 <> U3-M0C1T1 Data Latency : 20.3ns
U14-M0C7T0 <> U5-M0C2T1 Data Latency : 20.9ns
U14-M0C7T0 <> U7-M0C3T1 Data Latency : 21.1ns
U14-M0C7T0 <> U9-M0C4T1 Data Latency : 21.3ns
U14-M0C7T0 <> U11-M0C5T1 Data Latency : 21.3ns
U14-M0C7T0 <> U13-M0C6T1 Data Latency : 21.6ns
U14-M0C7T0 <> U15-M0C7T1 Data Latency : 9.6ns
U14-M0C7T0 <> U17-M1C0T1 Data Latency : 57.4ns
U14-M0C7T0 <> U19-M1C1T1 Data Latency : 57.1ns
U14-M0C7T0 <> U21-M1C2T1 Data Latency : 57.9ns
U14-M0C7T0 <> U23-M1C3T1 Data Latency : 57.9ns
U14-M0C7T0 <> U25-M1C4T1 Data Latency : 59.0ns
U14-M0C7T0 <> U27-M1C5T1 Data Latency : 58.1ns
U14-M0C7T0 <> U29-M1C6T1 Data Latency : 59.1ns
U14-M0C7T0 <> U31-M1C7T1 Data Latency : 58.7ns
U16-M1C0T0 <> U18-M1C1T0 Data Latency : 18.6ns
U16-M1C0T0 <> U20-M1C2T0 Data Latency : 20.1ns
U16-M1C0T0 <> U22-M1C3T0 Data Latency : 19.1ns
U16-M1C0T0 <> U24-M1C4T0 Data Latency : 21.4ns
U16-M1C0T0 <> U26-M1C5T0 Data Latency : 19.5ns
U16-M1C0T0 <> U28-M1C6T0 Data Latency : 21.4ns
U16-M1C0T0 <> U30-M1C7T0 Data Latency : 20.5ns
U16-M1C0T0 <> U1-M0C0T1 Data Latency : 55.4ns
U16-M1C0T0 <> U3-M0C1T1 Data Latency : 56.1ns
U16-M1C0T0 <> U5-M0C2T1 Data Latency : 56.2ns
U16-M1C0T0 <> U7-M0C3T1 Data Latency : 55.6ns
U16-M1C0T0 <> U9-M0C4T1 Data Latency : 56.9ns
U16-M1C0T0 <> U11-M0C5T1 Data Latency : 56.5ns
U16-M1C0T0 <> U13-M0C6T1 Data Latency : 57.2ns
U16-M1C0T0 <> U15-M0C7T1 Data Latency : 57.0ns
U16-M1C0T0 <> U17-M1C0T1 Data Latency : 9.7ns
U16-M1C0T0 <> U19-M1C1T1 Data Latency : 18.6ns
U16-M1C0T0 <> U21-M1C2T1 Data Latency : 19.9ns
U16-M1C0T0 <> U23-M1C3T1 Data Latency : 19.1ns
U16-M1C0T0 <> U25-M1C4T1 Data Latency : 21.2ns
U16-M1C0T0 <> U27-M1C5T1 Data Latency : 19.5ns
U16-M1C0T0 <> U29-M1C6T1 Data Latency : 21.4ns
U16-M1C0T0 <> U31-M1C7T1 Data Latency : 20.5ns
U18-M1C1T0 <> U20-M1C2T0 Data Latency : 19.1ns
U18-M1C1T0 <> U22-M1C3T0 Data Latency : 19.3ns
U18-M1C1T0 <> U24-M1C4T0 Data Latency : 20.1ns
U18-M1C1T0 <> U26-M1C5T0 Data Latency : 19.9ns
U18-M1C1T0 <> U28-M1C6T0 Data Latency : 20.7ns
U18-M1C1T0 <> U30-M1C7T0 Data Latency : 20.8ns
U18-M1C1T0 <> U1-M0C0T1 Data Latency : 55.9ns
U18-M1C1T0 <> U3-M0C1T1 Data Latency : 56.5ns
U18-M1C1T0 <> U5-M0C2T1 Data Latency : 56.6ns
U18-M1C1T0 <> U7-M0C3T1 Data Latency : 56.0ns
U18-M1C1T0 <> U9-M0C4T1 Data Latency : 57.1ns
U18-M1C1T0 <> U11-M0C5T1 Data Latency : 56.6ns
U18-M1C1T0 <> U13-M0C6T1 Data Latency : 57.8ns
U18-M1C1T0 <> U15-M0C7T1 Data Latency : 57.3ns
U18-M1C1T0 <> U17-M1C0T1 Data Latency : 18.7ns
U18-M1C1T0 <> U19-M1C1T1 Data Latency : 9.9ns
U18-M1C1T0 <> U21-M1C2T1 Data Latency : 19.1ns
U18-M1C1T0 <> U23-M1C3T1 Data Latency : 19.3ns
U18-M1C1T0 <> U25-M1C4T1 Data Latency : 20.1ns
U18-M1C1T0 <> U27-M1C5T1 Data Latency : 19.9ns
U18-M1C1T0 <> U29-M1C6T1 Data Latency : 20.7ns
U18-M1C1T0 <> U31-M1C7T1 Data Latency : 20.8ns
U20-M1C2T0 <> U22-M1C3T0 Data Latency : 19.9ns
U20-M1C2T0 <> U24-M1C4T0 Data Latency : 21.8ns
U20-M1C2T0 <> U26-M1C5T0 Data Latency : 20.4ns
U20-M1C2T0 <> U28-M1C6T0 Data Latency : 22.1ns
U20-M1C2T0 <> U30-M1C7T0 Data Latency : 21.1ns
U20-M1C2T0 <> U1-M0C0T1 Data Latency : 56.6ns
U20-M1C2T0 <> U3-M0C1T1 Data Latency : 57.0ns
U20-M1C2T0 <> U5-M0C2T1 Data Latency : 56.8ns
U20-M1C2T0 <> U7-M0C3T1 Data Latency : 56.6ns
U20-M1C2T0 <> U9-M0C4T1 Data Latency : 57.4ns
U20-M1C2T0 <> U11-M0C5T1 Data Latency : 57.2ns
U20-M1C2T0 <> U13-M0C6T1 Data Latency : 58.2ns
U20-M1C2T0 <> U15-M0C7T1 Data Latency : 57.8ns
U20-M1C2T0 <> U17-M1C0T1 Data Latency : 20.1ns
U20-M1C2T0 <> U19-M1C1T1 Data Latency : 19.1ns
U20-M1C2T0 <> U21-M1C2T1 Data Latency : 9.8ns
U20-M1C2T0 <> U23-M1C3T1 Data Latency : 19.7ns
U20-M1C2T0 <> U25-M1C4T1 Data Latency : 21.8ns
U20-M1C2T0 <> U27-M1C5T1 Data Latency : 20.4ns
U20-M1C2T0 <> U29-M1C6T1 Data Latency : 22.1ns
U20-M1C2T0 <> U31-M1C7T1 Data Latency : 21.1ns
U22-M1C3T0 <> U24-M1C4T0 Data Latency : 20.8ns
U22-M1C3T0 <> U26-M1C5T0 Data Latency : 20.5ns
U22-M1C3T0 <> U28-M1C6T0 Data Latency : 21.2ns
U22-M1C3T0 <> U30-M1C7T0 Data Latency : 21.3ns
U22-M1C3T0 <> U1-M0C0T1 Data Latency : 56.5ns
U22-M1C3T0 <> U3-M0C1T1 Data Latency : 56.9ns
U22-M1C3T0 <> U5-M0C2T1 Data Latency : 57.0ns
U22-M1C3T0 <> U7-M0C3T1 Data Latency : 56.7ns
U22-M1C3T0 <> U9-M0C4T1 Data Latency : 57.7ns
U22-M1C3T0 <> U11-M0C5T1 Data Latency : 57.4ns
U22-M1C3T0 <> U13-M0C6T1 Data Latency : 58.3ns
U22-M1C3T0 <> U15-M0C7T1 Data Latency : 57.8ns
U22-M1C3T0 <> U17-M1C0T1 Data Latency : 19.2ns
U22-M1C3T0 <> U19-M1C1T1 Data Latency : 19.2ns
U22-M1C3T0 <> U21-M1C2T1 Data Latency : 20.0ns
U22-M1C3T0 <> U23-M1C3T1 Data Latency : 9.9ns
U22-M1C3T0 <> U25-M1C4T1 Data Latency : 20.8ns
U22-M1C3T0 <> U27-M1C5T1 Data Latency : 20.5ns
U22-M1C3T0 <> U29-M1C6T1 Data Latency : 21.2ns
U22-M1C3T0 <> U31-M1C7T1 Data Latency : 21.3ns
U24-M1C4T0 <> U26-M1C5T0 Data Latency : 21.4ns
U24-M1C4T0 <> U28-M1C6T0 Data Latency : 23.0ns
U24-M1C4T0 <> U30-M1C7T0 Data Latency : 22.1ns
U24-M1C4T0 <> U1-M0C0T1 Data Latency : 57.7ns
U24-M1C4T0 <> U3-M0C1T1 Data Latency : 58.2ns
U24-M1C4T0 <> U5-M0C2T1 Data Latency : 58.4ns
U24-M1C4T0 <> U7-M0C3T1 Data Latency : 57.8ns
U24-M1C4T0 <> U9-M0C4T1 Data Latency : 58.8ns
U24-M1C4T0 <> U11-M0C5T1 Data Latency : 58.6ns
U24-M1C4T0 <> U13-M0C6T1 Data Latency : 59.4ns
U24-M1C4T0 <> U15-M0C7T1 Data Latency : 59.4ns
U24-M1C4T0 <> U17-M1C0T1 Data Latency : 21.2ns
U24-M1C4T0 <> U19-M1C1T1 Data Latency : 20.1ns
U24-M1C4T0 <> U21-M1C2T1 Data Latency : 21.8ns
U24-M1C4T0 <> U23-M1C3T1 Data Latency : 20.8ns
U24-M1C4T0 <> U25-M1C4T1 Data Latency : 10.0ns
U24-M1C4T0 <> U27-M1C5T1 Data Latency : 21.5ns
U24-M1C4T0 <> U29-M1C6T1 Data Latency : 23.0ns
U24-M1C4T0 <> U31-M1C7T1 Data Latency : 22.1ns
U26-M1C5T0 <> U28-M1C6T0 Data Latency : 21.5ns
U26-M1C5T0 <> U30-M1C7T0 Data Latency : 21.9ns
U26-M1C5T0 <> U1-M0C0T1 Data Latency : 56.6ns
U26-M1C5T0 <> U3-M0C1T1 Data Latency : 56.9ns
U26-M1C5T0 <> U5-M0C2T1 Data Latency : 57.1ns
U26-M1C5T0 <> U7-M0C3T1 Data Latency : 56.7ns
U26-M1C5T0 <> U9-M0C4T1 Data Latency : 57.8ns
U26-M1C5T0 <> U11-M0C5T1 Data Latency : 57.4ns
U26-M1C5T0 <> U13-M0C6T1 Data Latency : 58.4ns
U26-M1C5T0 <> U15-M0C7T1 Data Latency : 58.1ns
U26-M1C5T0 <> U17-M1C0T1 Data Latency : 19.6ns
U26-M1C5T0 <> U19-M1C1T1 Data Latency : 19.9ns
U26-M1C5T0 <> U21-M1C2T1 Data Latency : 20.5ns
U26-M1C5T0 <> U23-M1C3T1 Data Latency : 20.5ns
U26-M1C5T0 <> U25-M1C4T1 Data Latency : 21.6ns
U26-M1C5T0 <> U27-M1C5T1 Data Latency : 9.8ns
U26-M1C5T0 <> U29-M1C6T1 Data Latency : 21.6ns
U26-M1C5T0 <> U31-M1C7T1 Data Latency : 21.8ns
U28-M1C6T0 <> U30-M1C7T0 Data Latency : 22.0ns
U28-M1C6T0 <> U1-M0C0T1 Data Latency : 57.0ns
U28-M1C6T0 <> U3-M0C1T1 Data Latency : 58.0ns
U28-M1C6T0 <> U5-M0C2T1 Data Latency : 57.9ns
U28-M1C6T0 <> U7-M0C3T1 Data Latency : 57.8ns
U28-M1C6T0 <> U9-M0C4T1 Data Latency : 58.5ns
U28-M1C6T0 <> U11-M0C5T1 Data Latency : 58.0ns
U28-M1C6T0 <> U13-M0C6T1 Data Latency : 59.0ns
U28-M1C6T0 <> U15-M0C7T1 Data Latency : 59.0ns
U28-M1C6T0 <> U17-M1C0T1 Data Latency : 21.5ns
U28-M1C6T0 <> U19-M1C1T1 Data Latency : 20.8ns
U28-M1C6T0 <> U21-M1C2T1 Data Latency : 22.1ns
U28-M1C6T0 <> U23-M1C3T1 Data Latency : 21.3ns
U28-M1C6T0 <> U25-M1C4T1 Data Latency : 23.0ns
U28-M1C6T0 <> U27-M1C5T1 Data Latency : 21.6ns
U28-M1C6T0 <> U29-M1C6T1 Data Latency : 9.6ns
U28-M1C6T0 <> U31-M1C7T1 Data Latency : 22.1ns
U30-M1C7T0 <> U1-M0C0T1 Data Latency : 57.3ns
U30-M1C7T0 <> U3-M0C1T1 Data Latency : 57.9ns
U30-M1C7T0 <> U5-M0C2T1 Data Latency : 57.9ns
U30-M1C7T0 <> U7-M0C3T1 Data Latency : 57.6ns
U30-M1C7T0 <> U9-M0C4T1 Data Latency : 58.7ns
U30-M1C7T0 <> U11-M0C5T1 Data Latency : 58.2ns
U30-M1C7T0 <> U13-M0C6T1 Data Latency : 59.2ns
U30-M1C7T0 <> U15-M0C7T1 Data Latency : 58.9ns
U30-M1C7T0 <> U17-M1C0T1 Data Latency : 20.5ns
U30-M1C7T0 <> U19-M1C1T1 Data Latency : 20.6ns
U30-M1C7T0 <> U21-M1C2T1 Data Latency : 21.0ns
U30-M1C7T0 <> U23-M1C3T1 Data Latency : 21.3ns
U30-M1C7T0 <> U25-M1C4T1 Data Latency : 22.0ns
U30-M1C7T0 <> U27-M1C5T1 Data Latency : 21.9ns
U30-M1C7T0 <> U29-M1C6T1 Data Latency : 22.0ns
U30-M1C7T0 <> U31-M1C7T1 Data Latency : 9.8ns
U1-M0C0T1 <> U3-M0C1T1 Data Latency : 18.3ns
U1-M0C0T1 <> U5-M0C2T1 Data Latency : 19.9ns
U1-M0C0T1 <> U7-M0C3T1 Data Latency : 19.0ns
U1-M0C0T1 <> U9-M0C4T1 Data Latency : 20.5ns
U1-M0C0T1 <> U11-M0C5T1 Data Latency : 19.3ns
U1-M0C0T1 <> U13-M0C6T1 Data Latency : 21.2ns
U1-M0C0T1 <> U15-M0C7T1 Data Latency : 20.1ns
U1-M0C0T1 <> U17-M1C0T1 Data Latency : 55.8ns
U1-M0C0T1 <> U19-M1C1T1 Data Latency : 55.6ns
U1-M0C0T1 <> U21-M1C2T1 Data Latency : 56.2ns
U1-M0C0T1 <> U23-M1C3T1 Data Latency : 56.2ns
U1-M0C0T1 <> U25-M1C4T1 Data Latency : 57.4ns
U1-M0C0T1 <> U27-M1C5T1 Data Latency : 56.4ns
U1-M0C0T1 <> U29-M1C6T1 Data Latency : 57.1ns
U1-M0C0T1 <> U31-M1C7T1 Data Latency : 57.2ns
U3-M0C1T1 <> U5-M0C2T1 Data Latency : 19.1ns
U3-M0C1T1 <> U7-M0C3T1 Data Latency : 19.3ns
U3-M0C1T1 <> U9-M0C4T1 Data Latency : 19.7ns
U3-M0C1T1 <> U11-M0C5T1 Data Latency : 19.6ns
U3-M0C1T1 <> U13-M0C6T1 Data Latency : 20.4ns
U3-M0C1T1 <> U15-M0C7T1 Data Latency : 20.4ns
U3-M0C1T1 <> U17-M1C0T1 Data Latency : 56.6ns
U3-M0C1T1 <> U19-M1C1T1 Data Latency : 56.2ns
U3-M0C1T1 <> U21-M1C2T1 Data Latency : 57.2ns
U3-M0C1T1 <> U23-M1C3T1 Data Latency : 56.7ns
U3-M0C1T1 <> U25-M1C4T1 Data Latency : 58.1ns
U3-M0C1T1 <> U27-M1C5T1 Data Latency : 57.0ns
U3-M0C1T1 <> U29-M1C6T1 Data Latency : 58.0ns
U3-M0C1T1 <> U31-M1C7T1 Data Latency : 57.7ns
U5-M0C2T1 <> U7-M0C3T1 Data Latency : 19.5ns
U5-M0C2T1 <> U9-M0C4T1 Data Latency : 21.3ns
U5-M0C2T1 <> U11-M0C5T1 Data Latency : 20.3ns
U5-M0C2T1 <> U13-M0C6T1 Data Latency : 21.9ns
U5-M0C2T1 <> U15-M0C7T1 Data Latency : 20.9ns
U5-M0C2T1 <> U17-M1C0T1 Data Latency : 56.0ns
U5-M0C2T1 <> U19-M1C1T1 Data Latency : 56.2ns
U5-M0C2T1 <> U21-M1C2T1 Data Latency : 56.8ns
U5-M0C2T1 <> U23-M1C3T1 Data Latency : 57.0ns
U5-M0C2T1 <> U25-M1C4T1 Data Latency : 58.1ns
U5-M0C2T1 <> U27-M1C5T1 Data Latency : 57.1ns
U5-M0C2T1 <> U29-M1C6T1 Data Latency : 58.2ns
U5-M0C2T1 <> U31-M1C7T1 Data Latency : 57.8ns
U7-M0C3T1 <> U9-M0C4T1 Data Latency : 20.4ns
U7-M0C3T1 <> U11-M0C5T1 Data Latency : 20.3ns
U7-M0C3T1 <> U13-M0C6T1 Data Latency : 20.9ns
U7-M0C3T1 <> U15-M0C7T1 Data Latency : 21.0ns
U7-M0C3T1 <> U17-M1C0T1 Data Latency : 56.1ns
U7-M0C3T1 <> U19-M1C1T1 Data Latency : 56.1ns
U7-M0C3T1 <> U21-M1C2T1 Data Latency : 56.7ns
U7-M0C3T1 <> U23-M1C3T1 Data Latency : 56.6ns
U7-M0C3T1 <> U25-M1C4T1 Data Latency : 57.9ns
U7-M0C3T1 <> U27-M1C5T1 Data Latency : 56.9ns
U7-M0C3T1 <> U29-M1C6T1 Data Latency : 58.3ns
U7-M0C3T1 <> U31-M1C7T1 Data Latency : 57.6ns
U9-M0C4T1 <> U11-M0C5T1 Data Latency : 20.7ns
U9-M0C4T1 <> U13-M0C6T1 Data Latency : 22.3ns
U9-M0C4T1 <> U15-M0C7T1 Data Latency : 21.3ns
U9-M0C4T1 <> U17-M1C0T1 Data Latency : 56.7ns
U9-M0C4T1 <> U19-M1C1T1 Data Latency : 56.6ns
U9-M0C4T1 <> U21-M1C2T1 Data Latency : 57.3ns
U9-M0C4T1 <> U23-M1C3T1 Data Latency : 57.5ns
U9-M0C4T1 <> U25-M1C4T1 Data Latency : 58.6ns
U9-M0C4T1 <> U27-M1C5T1 Data Latency : 57.6ns
U9-M0C4T1 <> U29-M1C6T1 Data Latency : 58.3ns
U9-M0C4T1 <> U31-M1C7T1 Data Latency : 58.6ns
U11-M0C5T1 <> U13-M0C6T1 Data Latency : 21.2ns
U11-M0C5T1 <> U15-M0C7T1 Data Latency : 21.3ns
U11-M0C5T1 <> U17-M1C0T1 Data Latency : 56.7ns
U11-M0C5T1 <> U19-M1C1T1 Data Latency : 56.5ns
U11-M0C5T1 <> U21-M1C2T1 Data Latency : 57.4ns
U11-M0C5T1 <> U23-M1C3T1 Data Latency : 57.0ns
U11-M0C5T1 <> U25-M1C4T1 Data Latency : 58.7ns
U11-M0C5T1 <> U27-M1C5T1 Data Latency : 57.5ns
U11-M0C5T1 <> U29-M1C6T1 Data Latency : 58.2ns
U11-M0C5T1 <> U31-M1C7T1 Data Latency : 58.4ns
U13-M0C6T1 <> U15-M0C7T1 Data Latency : 21.6ns
U13-M0C6T1 <> U17-M1C0T1 Data Latency : 57.2ns
U13-M0C6T1 <> U19-M1C1T1 Data Latency : 57.4ns
U13-M0C6T1 <> U21-M1C2T1 Data Latency : 58.0ns
U13-M0C6T1 <> U23-M1C3T1 Data Latency : 58.2ns
U13-M0C6T1 <> U25-M1C4T1 Data Latency : 59.1ns
U13-M0C6T1 <> U27-M1C5T1 Data Latency : 58.5ns
U13-M0C6T1 <> U29-M1C6T1 Data Latency : 58.9ns
U13-M0C6T1 <> U31-M1C7T1 Data Latency : 58.8ns
U15-M0C7T1 <> U17-M1C0T1 Data Latency : 57.4ns
U15-M0C7T1 <> U19-M1C1T1 Data Latency : 57.3ns
U15-M0C7T1 <> U21-M1C2T1 Data Latency : 58.0ns
U15-M0C7T1 <> U23-M1C3T1 Data Latency : 58.2ns
U15-M0C7T1 <> U25-M1C4T1 Data Latency : 59.2ns
U15-M0C7T1 <> U27-M1C5T1 Data Latency : 58.0ns
U15-M0C7T1 <> U29-M1C6T1 Data Latency : 59.2ns
U15-M0C7T1 <> U31-M1C7T1 Data Latency : 58.9ns
U17-M1C0T1 <> U19-M1C1T1 Data Latency : 18.6ns
U17-M1C0T1 <> U21-M1C2T1 Data Latency : 19.9ns
U17-M1C0T1 <> U23-M1C3T1 Data Latency : 19.2ns
U17-M1C0T1 <> U25-M1C4T1 Data Latency : 21.3ns
U17-M1C0T1 <> U27-M1C5T1 Data Latency : 19.5ns
U17-M1C0T1 <> U29-M1C6T1 Data Latency : 21.4ns
U17-M1C0T1 <> U31-M1C7T1 Data Latency : 20.5ns
U19-M1C1T1 <> U21-M1C2T1 Data Latency : 19.1ns
U19-M1C1T1 <> U23-M1C3T1 Data Latency : 19.2ns
U19-M1C1T1 <> U25-M1C4T1 Data Latency : 20.1ns
U19-M1C1T1 <> U27-M1C5T1 Data Latency : 19.9ns
U19-M1C1T1 <> U29-M1C6T1 Data Latency : 20.7ns
U19-M1C1T1 <> U31-M1C7T1 Data Latency : 20.8ns
U21-M1C2T1 <> U23-M1C3T1 Data Latency : 19.7ns
U21-M1C2T1 <> U25-M1C4T1 Data Latency : 21.8ns
U21-M1C2T1 <> U27-M1C5T1 Data Latency : 20.4ns
U21-M1C2T1 <> U29-M1C6T1 Data Latency : 22.1ns
U21-M1C2T1 <> U31-M1C7T1 Data Latency : 21.0ns
U23-M1C3T1 <> U25-M1C4T1 Data Latency : 20.8ns
U23-M1C3T1 <> U27-M1C5T1 Data Latency : 20.5ns
U23-M1C3T1 <> U29-M1C6T1 Data Latency : 21.3ns
U23-M1C3T1 <> U31-M1C7T1 Data Latency : 21.3ns
U25-M1C4T1 <> U27-M1C5T1 Data Latency : 21.5ns
U25-M1C4T1 <> U29-M1C6T1 Data Latency : 23.0ns
U25-M1C4T1 <> U31-M1C7T1 Data Latency : 22.1ns
U27-M1C5T1 <> U29-M1C6T1 Data Latency : 21.6ns
U27-M1C5T1 <> U31-M1C7T1 Data Latency : 21.8ns
U29-M1C6T1 <> U31-M1C7T1 Data Latency : 22.0ns
1x 64bytes Blocks Bandwidth : 20.11GB/s
4x 64bytes Blocks Bandwidth : 29.54GB/s
4x 256bytes Blocks Bandwidth : 99.69GB/s
4x 1kB Blocks Bandwidth : 326.15GB/s
4x 4kB Blocks Bandwidth : 522.69GB/s
16x 4kB Blocks Bandwidth : 703GB/s
4x 64kB Blocks Bandwidth : 990.13GB/s
16x 64kB Blocks Bandwidth : 659.14GB/s
8x 256kB Blocks Bandwidth : 599.9GB/s
4x 1MB Blocks Bandwidth : 589GB/s
16x 1MB Blocks Bandwidth : 32.38GB/s
8x 4MB Blocks Bandwidth : 18.86GB/s

Benchmark Status
Result ID : AMD Ryzen 9 5950X 16-Core Processor (2M 16C 32T 4.88GHz, 1.9GHz IMC, 16x 512kB L2, 2x 32MB L3)
Microcode : A20F10-1016
Computer : MSI MS-7D51 (MSI MEG X570S UNIFY-X MAX (MS-7D51))
Platform Compliance : x64
No. Threads : 32
System Timer : 10MHz
Page Size : 2MB

Processor
Model : AMD Ryzen 9 5950X 16-Core Processor
URL : https://www.amd.com
Revision/Stepping : 21 / 0
Latest Version : 21 / 2
Microcode : A20F10-1016
Latest Version : A20F12-120A
Front-Side Bus Speed : 100MHz
Rated Power (TDP) : 105.00W

Processor Module
Modules per Processor : 2 Unit(s)
Cores per Processor : 8 Unit(s)
Threads per Core : 2 Unit(s)
Speed : 4.88GHz
Supported Speed(s) : 2.2GHz - 3.4GHz - 4.88GHz
L1D (1st Level) Data Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L1I (1st Level) Code Cache : 16x 32kB, 8-Way, Exclusive, 64bytes Line Size, 2 Thread(s)
L2 (2nd Level) Unified/Data Cache : 16x 512kB, 8-Way, Fully Inclusive, 64bytes Line Size, 2 Thread(s)
L3 (3rd Level) Unified/Data Cache : 2x 32MB, 16-Way, Exclusive, 64bytes Line Size, 16 Thread(s)
Rated Voltage (DV) : 1.45V
Min/Max/Turbo Voltage : 0.90V - 1.45V - 1.45V

Memory Controller
Model : AMD F19 (Ryzen3/TR3 Matisse) Host Bridge
Speed : 1.9GHz
Min/Max/Turbo Speed : 950MHz - 1.9GHz

Performance Enhancing Tips
Tip 232 : Newer CPU stepping exists. Newer steppings contain fixes and may have better overclocking potential.
Tip 229 : CPU microcode update available. Check for an updated System BIOS with updated microcode.
Notice 241 : Dynamic OverClocking/Turbo enabled. Performance may vary when engaged.
Tip 3 : Double-click tip or press Enter while a tip is selected for more information about the tip.


----------



## KedarWolf

Blameless said:


> Still a lot of room to tune that DJR stuff.
> 
> Most of Bloax's guide will still apply, you just won't be able to tighten the primaries, tRTP, or tRFC anywhere near as much, and you'll probably want weaker drive strengths (higher output impedance/Rtt values).
> 
> 
> 
> Radiation errors on 32GiB of memory is more of a once every 6-12 month sort of thing, unless you live on top of a mountain or have some sort of radon problem. AC issues could certainly cause problems, but if the power supply and board are quality, even very dirty power is well within one's ability to stabilize.
> 
> One error every six, or even twenty-four, hour is usually a very correctable stability problem, rather than an inevitable single-event fluke.
> 
> 
> 
> Might want to consider a new PSU and/or a better surge suppressor, perhaps a line conditioner. In the mean time, see if you can move the TV to a different circuit.


I have a Furman power conditioner. I think it only has one conditioned outlet, but my PC is plugged into it directly. It's the only thing I care about being power conditioned.

I bought it a long time ago on eBay for $150 or something.

Edit: I think all the plugs have filtration. It's only $150 CAD on Amazon.









Furman M-8x2 8 Outlet Power Conditioner


8-outlet Rackmountable Power Conditioner with Wall Wart Spacing on Rear Outlets - 15 Amps




www.sweetwater.com


----------



## mnathani98

Lowering any timing now causes errors (I can drop tRAS down to 24 and it passes 25 cycle of 1usmus v3 but errors out on anta absolut) so this is where im settling. Can do up to 3933mhz 1:1 but without PBO, with PBO it throws WHEA 19s. Super happy tho, with a 3060 Ti + 5600x i am doing 170-180fps average in warzone caldera (200+ inside buildings and jungle areas. This is the best gaming experience ive ever had. Thank you everyone who helped me with 1T GDM off and RTTs and drive strengths, i would've never figured it on my own.


----------



## The_King

mnathani98 said:


> Lowering any timing now causes errors (I can drop tRAS down to 24 and it passes 25 cycle of 1usmus v3 but errors out on anta absolut) so this is where im settling. Can do up to 3933mhz 1:1 but without PBO, with PBO it throws WHEA 19s. Super happy tho, with a 3060 Ti + 5600x i am doing 170-180fps average in warzone caldera (200+ inside buildings and jungle areas. This is the best gaming experience ive ever had. Thank you everyone who helped me with 1T GDM off and RTTs and drive strengths, i would've never figured it on my own.


You can get rid of the WHEA 19 by increasing VSOC offset.
My 5600X needed between 1.175V to 1.18V on VSOC to be WHEA free at FCLK 1966.


----------



## mnathani98

The_King said:


> You can get rid of the WHEA 19 by increasing VSOC offset.
> My 5600X need between 1.175V to 1.18V on VSOC


tried up to 1.2v, no good. Tried VDDP upto 1v and VDDGs up to 1.1v. Also WHEAs don't manifest when i run TM5 on 3933 with PBO but if i run OCCT AVX2 Variable Extreme it starts throwing them.


----------



## Blameless

KedarWolf said:


> I have a Furman power conditioner. I think it only has one conditioned outlet, but my PC is plugged into it directly. It's the only thing I care about being power conditioned.
> 
> I bought it a long time ago on eBay for $150 or something.
> 
> Edit: I think all the plugs have filtration. It's only $150 CAD on Amazon.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Furman M-8x2 8 Outlet Power Conditioner
> 
> 
> 8-outlet Rackmountable Power Conditioner with Wall Wart Spacing on Rear Outlets - 15 Amps
> 
> 
> 
> 
> www.sweetwater.com


I looked up the Furman Merit line and they seem to be just an inductor, a couple of x-capacitors, and a single MOV...basically modest EMI filtering paired with weak surge protection.









Might help noise a little, but won't do much of anything in the case of significant AC voltage drop. At 150 bucks it's also getting into getting into Tripp Lite LC-1200 territory.

Older, but still largely representative, example of what's in one of those:





Spec wise, it's about 50dB more EMI filtering, ~8 times the surge rating, and will automatically adjust any input voltage from 89-147v to ~120v output.

However, even something like that won't significantly clean up a dirty sine wave. For that you'd need an isolation transformer (which good line-interactive UPSes also tend to have), or a double-conversion UPS.


----------



## Taraquin

mnathani98 said:


> Lowering any timing now causes errors (I can drop tRAS down to 24 and it passes 25 cycle of 1usmus v3 but errors out on anta absolut) so this is where im settling. Can do up to 3933mhz 1:1 but without PBO, with PBO it throws WHEA 19s. Super happy tho, with a 3060 Ti + 5600x i am doing 170-180fps average in warzone caldera (200+ inside buildings and jungle areas. This is the best gaming experience ive ever had. Thank you everyone who helped me with 1T GDM off and RTTs and drive strengths, i would've never figured it on my own.


Looks mostly very good. A few thing I would change. Set WR to 12 (easier to run than what you do now and better timeout wise) or RTP to 5(a bit harder to run so 12/6 may be best). WR=RTPx2 so doesn't add up now. Another thing I would consider is running CWL at 14 and try to drop RDWR to 10 or maybe 9. TDWR is more important for performance than CWL, but low CWL makes low RDWR impossible and the other way around.


----------



## Taraquin

mnathani98 said:


> tried up to 1.2v, no good. Tried VDDP upto 1v and VDDGs up to 1.1v. Also WHEAs don't manifest when i run TM5 on 3933 with PBO but if i run OCCT AVX2 Variable Extreme it starts throwing them.


Try changing VDDG CCD (try both higher and lower), that may fix it. I would consider running pbo+0 and just setting negative CO, this can boost multicore perf by up to 6% if you can do -30 allcore.


----------



## Taraquin

Sir Beregond said:


> This was just a kit I saw at Micro Center.
> 
> View attachment 2565634
> 
> 
> View attachment 2565635
> 
> View attachment 2565636


You got a indepth guide, but I can make an easy one, set ram voltage to 1.45v, I would try 3733/1866 or 3800/1900 if I were you:
Keep 4 first timings as is. I hope this is rally DJR and not a good bin CJR, CJR is much more of a pain to work with. 
RAS 35
RC 54
RRDS 4
RRDL 6
FAW 16
WTRS 4
WTRL 8
RFC 512, 496, 480, 464 or 448 (start highest and try lower and lower)
WR 16
RDRDSCL 4
WRWRSCL 4
CWL 16
RTP 8
RDWR 10
WRRD 3

This should be safe settings for almost all DJR kits. If you stick with 3600 you may be able to go lower on RCDRD/RW, RP, RAS and RC. DJR is generally the second best kit after B-die, it usually beats Micron rev E/B due to better RFC. Getting B-die instead would tops give you 3-5% when CPU bound in some games so little to gain for a high price.


----------



## The_King

Slight improvement from yesterday.
Dropped RRDL 4 WTRL 8 was getting single error on each run.

Dropped RttNom from 7 to 6 and its gone now.


----------



## mnathani98

Taraquin said:


> Looks mostly very good. A few thing I would change. Set WR to 12 (easier to run than what you do now and better timeout wise) or RTP to 5(a bit harder to run so 12/6 may be best). WR=RTPx2 so doesn't add up now. Another thing I would consider is running CWL at 14 and try to drop RDWR to 10 or maybe 9. TDWR is more important for performance than CWL, but low CWL makes low RDWR impossible and the other way around.


Will try WR 12 but pretty sure RTP can't do 5. I did try CWL 12 or 14 with RDWR 10 and the performance was the same (marginally worse no biggie).


----------



## mnathani98

Taraquin said:


> Try changing VDDG CCD (try both higher and lower), that may fix it. I would consider running pbo+0 and just setting negative CO, this can boost multicore perf by up to 6% if you can do -30 allcore.


Interesting, will try that. I did try +0 but it had WHEAs too, i'll try CO with that and see how it goes. Although my current PBO setup is pretty good so idk if i want to sacrifice that. 4.775-4.85Ghz in game.


----------



## Taraquin

mnathani98 said:


> Interesting, will try that. I did try +0 but it had WHEAs too, i'll try CO with that and see how it goes. Although my current PBO setup is pretty good so idk if i want to sacrifice that. 4.775-4.85Ghz in game.


Not sure I understand you but you say you have a current pbo setup? How do you do that without enabling pbo?  If you can't do +0 and CO I would consider doing a undervolt offset instead. It will lower temps a bit and improve multicore score due to thermal headroom


----------



## Taraquin

The_King said:


> Slight improvement from yesterday.
> Dropped RRDL 4 WTRL 8 was getting single error on each run.
> 
> Dropped RttNom from 7 to 6 and its gone now.
> 
> View attachment 2565665


Try getting GDM off stable next?  DrvStr 30 20 24 24, 40 20 24 24 or 40 20 30 24 often works.


----------



## mnathani98

Taraquin said:


> Not sure I understand you but you say you have a current pbo setup? How do you do that without enabling pbo?  If you can't do +0 and CO I would consider doing a undervolt offset instead. It will lower temps a bit and improve multicore score due to thermal headroom


PBO is fine with 3800mhz, above it (3866,3933) i have WHEAs when i enable PBO. If i leave it at stock there are no WHEAs at 3933. The thing with traditional undervolt is that it causes clock stretching so i don't want to do that. My current PBO setup at 3800mhz is +200mhz + TDP EDC PPT at 130 + Scalar 10x + CO Negative ranging from -17 to -30 (-30 is only on one core) + Positive Voltage offset of 50mv. I definitely didn't steal this from some comment on reddit. No clock stretching, high scores, high clocks, low idle voltage (SV12 CPU reports 0.974v lowest). These settings have been thoroughly tested with 12+ hours on Core Cycler and with OCCT AVX2 Extreme Variable.


----------



## Sir Beregond

Taraquin said:


> You got a indepth guide, but I can make an easy one, set ram voltage to 1.45v, I would try 3733/1866 or 3800/1900 if I were you:
> Keep 4 first timings as is. I hope this is rally DJR and not a good bin CJR, CJR is much more of a pain to work with.
> RAS 35
> RC 54
> RRDS 4
> RRDL 6
> FAW 16
> WTRS 4
> WTRL 8
> RFC 512, 496, 480, 464 or 448 (start highest and try lower and lower)
> WR 16
> RDRDSCL 4
> WRWRSCL 4
> CWL 16
> RTP 8
> RDWR 10
> WRRD 3
> 
> This should be safe settings for almost all DJR kits. If you stick with 3600 you may be able to go lower on RCDRD/RW, RP, RAS and RC. DJR is generally the second best kit after B-die, it usually beats Micron rev E/B due to better RFC. Getting B-die instead would tops give you 3-5% when CPU bound in some games so little to gain for a high price.


I'll give this a shot and let you know how it goes, thank you!


----------



## KedarWolf

Blameless said:


> I looked up the Furman Merit line and they seem to be just an inductor, a couple of x-capacitors, and a single MOV...basically modest EMI filtering paired with weak surge protection.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Might help noise a little, but won't do much of anything in the case of significant AC voltage drop. At 150 bucks it's also getting into getting into Tripp Lite LC-1200 territory.
> 
> Older, but still largely representative, example of what's in one of those:
> 
> 
> 
> 
> 
> Spec wise, it's about 50dB more EMI filtering, ~8 times the surge rating, and will automatically adjust any input voltage from 89-147v to ~120v output.
> 
> However, even something like that won't significantly clean up a dirty sine wave. For that you'd need an isolation transformer (which good line-interactive UPSes also tend to have), or a double-conversion UPS.


Is this the better version of that?









Tripp Lite LC1800 Line Conditioner | eBay


Find many great new & used options and get the best deals for Tripp Lite LC1800 Line Conditioner at the best online prices at eBay! Free shipping for many products!



www.ebay.ca


----------



## KedarWolf

Cyberpower CP1000 1000VA UPS Battery Backup Pure Sine Wave w/ 10 Outlets - UPS (Battery Backups) - Memory Express Inc.







www.memoryexpress.com





*CyberpowerCP1000 1000VA UPS Battery Backup Pure Sine Wave w/ 10 Outlets*


This is Pure Sine Wave, cheap too. Any good?


----------



## The_King

Taraquin said:


> Try getting GDM off stable next?  DrvStr 30 20 24 24, 40 20 24 24 or 40 20 30 24 often works.


GDM off 1T was not happening, with high ambients here and no RAM cooling I went back GDM.

Managed to improve subs further WTRS 3 TWR 10. Can't set RTP to 5 because GDM is on. CL14 almost passed so 14-16-16 @ 1.53ish maybe possible.
Problem is I can no longer get RttNom to boot at 6 anymore.


----------



## Blameless

KedarWolf said:


> Is this the better version of that?


It's the new version, specs and actual performance should be almost identical, if both were new.

I have an LC1800 in my basement to account for the rather sketchy power in this old construction...there isn't a real noise/waveform issue, just frequent brownouts that will shut off most PSUs without AC voltage regulation.



KedarWolf said:


> Cyberpower CP1000 1000VA UPS Battery Backup Pure Sine Wave w/ 10 Outlets - UPS (Battery Backups) - Memory Express Inc.
> 
> 
> 
> 
> 
> 
> 
> www.memoryexpress.com
> 
> 
> 
> 
> 
> *CyberpowerCP1000 1000VA UPS Battery Backup Pure Sine Wave w/ 10 Outlets*
> 
> 
> This is Pure Sine Wave, cheap too. Any good?


About as good as you're likely to find for the price. It's a line-interactive PSU with single-boost AVR that kicks in below 102V and decent enough surge protection.

However, surge protection is still sacrificial MOVs and it's only 600w total output, with a recommendation that only 480w be connected to the battery. Even if that tower in your sig was the only thing connected to it, it would be a bit too small.


----------



## KedarWolf

Blameless said:


> It's the new version, specs and actual performance should be almost identical, if both were new.
> 
> I have an LC1800 in my basement to account for the rather sketchy power in this old construction...there isn't a real noise/waveform issue, just frequent brownouts that will shut off most PSUs without AC voltage regulation.
> 
> 
> 
> About as good as you're likely to find for the price. It's a line-interactive PSU with single-boost AVR that kicks in below 102V and decent enough surge protection.
> 
> However, surge protection is still sacrificial MOVs and it's only 600w total output, with a recommendation that only 480w be connected to the battery. Even if that tower in your sig was the only thing connected to it, it would be a bit too small.


I'm thinking of this one. Pure Sine Wave, 1000W.

CyberPower PFC Sinewave CP1500PFCLCD - Capacity: 1500VA / 1000W - 1500VA/1000WTower 1.98Minute Full Load - 10 x NEMA 5-15R - Battery/Surge-protected





__





CP1500PFCLCD CyberPower PFC Sinewave CP1500PFCLCD - Capacity: 1500VA / 1000W - 1500VA/1000WTower 1.98Minute Full Load - 10 x NEMA 5-15R - Battery/Surge-protected - Cendirect Canada


Canada CP1500PFCLCD CyberPower PFC Sinewave CP1500PFCLCD - Capacity: 1500VA / 1000W - 1500VA/1000WTower 1.98Minute Full Load - 10 x NEMA 5-15R - Battery/Surge-protected



www.cendirect.com





Edit: It's an adaptive sine wave marketed as a pure sign wave but there's an oscilloscope reading from it and the sine wave is quite good.


----------



## Blameless

KedarWolf said:


> I'm thinking of this one. Pure Sine Wave, 1000W.
> 
> CyberPower PFC Sinewave CP1500PFCLCD - Capacity: 1500VA / 1000W - 1500VA/1000WTower 1.98Minute Full Load - 10 x NEMA 5-15R - Battery/Surge-protected
> 
> 
> 
> 
> 
> __
> 
> 
> 
> 
> 
> CP1500PFCLCD CyberPower PFC Sinewave CP1500PFCLCD - Capacity: 1500VA / 1000W - 1500VA/1000WTower 1.98Minute Full Load - 10 x NEMA 5-15R - Battery/Surge-protected - Cendirect Canada
> 
> 
> Canada CP1500PFCLCD CyberPower PFC Sinewave CP1500PFCLCD - Capacity: 1500VA / 1000W - 1500VA/1000WTower 1.98Minute Full Load - 10 x NEMA 5-15R - Battery/Surge-protected
> 
> 
> 
> www.cendirect.com
> 
> 
> 
> 
> 
> Edit: It's an adaptive sine wave marketed as a pure sign wave but there's an oscilloscope reading from it and the sine wave is quite good.


Should suffice.


----------



## KedarWolf

Blameless said:


> Should suffice.


Yeah, I bought that one.


----------



## The_King

KedarWolf said:


> I'm thinking of this one. Pure Sine Wave, 1000W.
> 
> CyberPower PFC Sinewave CP1500PFCLCD - Capacity: 1500VA / 1000W - 1500VA/1000WTower 1.98Minute Full Load - 10 x NEMA 5-15R - Battery/Surge-protected
> 
> 
> 
> 
> 
> __
> 
> 
> 
> 
> 
> CP1500PFCLCD CyberPower PFC Sinewave CP1500PFCLCD - Capacity: 1500VA / 1000W - 1500VA/1000WTower 1.98Minute Full Load - 10 x NEMA 5-15R - Battery/Surge-protected - Cendirect Canada
> 
> 
> Canada CP1500PFCLCD CyberPower PFC Sinewave CP1500PFCLCD - Capacity: 1500VA / 1000W - 1500VA/1000WTower 1.98Minute Full Load - 10 x NEMA 5-15R - Battery/Surge-protected
> 
> 
> 
> www.cendirect.com
> 
> 
> 
> 
> 
> Edit: It's an adaptive sine wave marketed as a pure sign wave but there's an oscilloscope reading from it and the sine wave is quite good.


When I was looking for a sinewave UPS years ago I saw reviews of the APC 1000/1500VA and the CyberPower 1000/1500VA. The CP one was rated / reviewd has being the better option.

Sadly was not availble in my country so bought the APC which was very good. One thing that was awseome it shows realtime load in Watts. Backup on Desktop when new was 30mins, AVG 20mins after a few years.

Now I run this setup with over +10 hours of backup, it is a "Pure sinewave" inverter. (according to website specs) (87 USD)








Luminous Zolt 1100 Sine Wave Inverter for Home, Office & Shops (Blue) : Amazon.in: Home & Kitchen


Luminous Zolt 1100 Sine Wave Inverter for Home, Office & Shops (Blue) : Amazon.in: Home & Kitchen



www.amazon.in





Its attached to a 200AH battery (215 USD)


Amazon.in



Full load gaming I get betwen 6-8 hours when the power is out depending on the game load. My CPU and GPU is UV and UC as well for max efficiency..

At the present moment the power is out it showing 9:59 which means more than +10 hours of backup left. Only problem it does not show realtime power consumption but its the best UPS system with built in voltage stabilizer and rated 94% for efficiency..


----------



## burkettchandler

Hey guys... Umm I'm trying to install TestMem5, and I can't find the install anywhere. All I'm getting is a .rar file but I can't find the .exe file. That MEGA site only gives you the .rar file.


----------



## Valka814

Cant stabilize tWR 14 + tRTP 7 or tCWL 14 + tRDWR 9. Tried it very hard with no luck.
I need a whole night test for this I think then I can go further with your suggestions. I already very happy what I reached with your help guys, I can only become happier if I can further tweak it.


----------



## The_King

Valka814 said:


> Cant stabilize tWR 14 + tRTP 7 or tCWL 14 + tRDWR 9. Tried it very hard with no luck.
> I need a whole night test for this I think then I can go further with your suggestions. I already very happy what I reached with your help guys, I can only become happier if I can further tweak it.
> View attachment 2565754


Can your TRFC go lower?

WIth my all my E-die RAM 270-280ns is possible.
Try 551 then 532 instead of 592. decrease by 1 untill it no longer boots then add +1 to the last failed boot or +2 to be a safe.
Although TRFC is not so import on E-die has it is on B-die. According to @Veii


----------



## Valka814

The_King said:


> Can your TRFC go lower?
> 
> WIth my all my E-die RAM 270-280ns is possible.
> Try 551 then 532 instead of 592. decrease by 1 untill it no longer boots then add +1 to the last failed boot or +2 to be a safe.
> Although TRFC is not so import on E-die has it is on B-die. According to @Veii
> 
> View attachment 2565755


Not tested much tRFC yet, but windows failed to boot with 560. I'll get there to test it, thank you for the info!


----------



## Taraquin

Valka814 said:


> Cant stabilize tWR 14 + tRTP 7 or tCWL 14 + tRDWR 9. Tried it very hard with no luck.
> I need a whole night test for this I think then I can go further with your suggestions. I already very happy what I reached with your help guys, I can only become happier if I can further tweak it.
> View attachment 2565754


14 CWL + RDWR 10 may work? But maybe what you have now is the best you get. For RFC I would try 576. Rest looks very good!


The_King said:


> Can your TRFC go lower?
> 
> WIth my all my E-die RAM 270-280ns is possible.
> Try 551 then 532 instead of 592. decrease by 1 untill it no longer boots then add +1 to the last failed boot or +2 to be a safe.
> Although TRFC is not so import on E-die has it is on B-die. According to @Veii
> 
> View attachment 2565755


According to Veii Micron ram possibly benefits from the 8 RFC for 8gb modules, 16 RFC for 16gb modules like Intel do. one of my rev E kits can do 280ns, the other one needs 290ns.


----------



## Pegasuss

Hey guys,

Just wondering if there is any improvements I can make? Can't post at 1900 FLCK and anything above that I get WHEAs even with 1.2v VSoC, 1.1v IOD/CCD and 1.05 Vddp.

Maybe SCL 2-3? Not sure, I am aware of the read benefit with 4 but I am also seeing people with 2 on DR. Maybe 228 tRFC? vDIMM is at 1.49v.


----------



## Audioboxer

Pegasuss said:


> Hey guys,
> 
> Just wondering if there is any improvements I can make? Can't post at 1900 FLCK and anything above that I get WHEAs even with 1.2v VSoC, 1.1v IOD/CCD and 1.05 Vddp.
> 
> Maybe SCL 2-3? Not sure, I am aware of the read benefit with 4 but I am also seeing people with 2 on DR. Maybe 228 tRFC? vDIMM is at 1.5v.
> View attachment 2565789


You could try some BCLK overclocking to pump the mem/IF frequencies. Tends to work better on B550 motherboards than X570 though.


----------



## The_King

burkettchandler said:


> Hey guys... Umm I'm trying to install TestMem5, and I can't find the install anywhere. All I'm getting is a .rar file but I can't find the .exe file. That MEGA site only gives you the .rar file.


Did you download from this link?








28.3 KB file on MEGA







mega.nz




Above link is from this thread








Memory Testing with TestMem5 TM5 with custom configs


Hello everybody I am just making a very light tutorial with a collection of custom config files and a DOWNLOAD LINK for TM5 v0.12 anta777 absolut config *Official* Intel DDR4 24/7 Memory Stability Thread None of the work is mine but it seems like a pretty good and fast testing app




www.overclock.net





@Taraquin
I am surprised this even passed. 
3 cycles is good enough for me!


----------



## KedarWolf

TM5(TestMem5) v0.12 Advanced 4.1/5/5.1 TM5 Advanced, the newer version.

You need WinRar or 7-Zip to unzip the files and then you'll have the .exe.


----------



## domdtxdissar

KedarWolf said:


> TM5(TestMem5) v0.12 Advanced 4.1/5/5.1 TM5 Advanced, the newer version.
> 
> You need WinRar or 7-Zip to unzip the files and then you'll have the .exe.


So what's new with this advanced version, other than the translation to korean?










Old regular version:


----------



## The_King

The_King said:


> @Taraquin
> I am surprised this even passed.
> 3 cycles is good enough for me!
> View attachment 2565815


Improved on this by lowering CCD 1V and VDIMM to 1.5V. Also took VSOC off Auto. Offset +0.0250 its much more stable than Auto.
This should be good enough for daily now.











Spoiler: Y-cruncher 2.5B
















@Bloax

How many iteration does this test take to complete? 120? Loved your YT vid on "Memeory OC Basics 101". I subbed, do more vids
Does this mean my RAM OC not $hite


----------



## Bloax

The_King said:


> Improved on this by lowering CCD 1V and VDIMM to 1.5V. Also took VSOC off Auto. Offset +0.0250 its much more stable than Auto.
> This should be good enough for daily now.
> View attachment 2565840
> 
> 
> 
> 
> Spoiler: Y-cruncher 2.5B
> 
> 
> 
> 
> View attachment 2565841
> 
> 
> 
> 
> 
> @Bloax
> 
> How many iteration does this test take to complete? 120? Loved your YT vid on "Memeory OC Basics 101". I subbed, do more vids
> Does this mean my RAM OC not $hite
> View attachment 2565870


y-cruncher HNT is good as a "sniff-test" to see if your recent changes (e.g. trying WTRL 8 instead of 12, looking for "What Voltage is Too Low??") made the memory unstable, as it will crash very quickly.
(thanks to whoever pointed that out somewhere on these forums, potentially not even in this thread)

Running FFT, HNT and VST for 30-120 minutes is usually enough to "not feel bad" about your memory stability - as they are very demanding.

I will try to ramble some more.
hehe RAMble ..


----------



## Taraquin

The_King said:


> Did you download from this link?
> 
> 
> 
> 
> 
> 
> 
> 
> 28.3 KB file on MEGA
> 
> 
> 
> 
> 
> 
> 
> mega.nz
> 
> 
> 
> 
> Above link is from this thread
> 
> 
> 
> 
> 
> 
> 
> 
> Memory Testing with TestMem5 TM5 with custom configs
> 
> 
> Hello everybody I am just making a very light tutorial with a collection of custom config files and a DOWNLOAD LINK for TM5 v0.12 anta777 absolut config *Official* Intel DDR4 24/7 Memory Stability Thread None of the work is mine but it seems like a pretty good and fast testing app
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> @Taraquin
> I am surprised this even passed.
> 3 cycles is good enough for me!
> View attachment 2565815


You can probably run RFC lower, 260-280 may work, WR should be 12


----------



## The_King

Taraquin said:


> You can probably run RFC lower, 260-280 may work, WR should be 12


That is actually another weird thing with B-die. Certain higher frequency and low CL refuse to boot, but if you set tWR 10, it just boots. 🤷‍♂️ 
I noticed the same thing when I was running my 1700X and the Patriot Viper kit

I was running RFC 266 but increased it to 285 for testing. Its set to 266 currently.


----------



## Baio73

domdtxdissar said:


> So what's new with this advanced version, other than the translation to korean?
> 
> View attachment 2565825
> 
> 
> Old regular version:
> View attachment 2565826


Nothing for me... I have the same issue with both versions...

Baio


----------



## Blackfyre

*Are these voltages safe for 24/7?* The board gets good airflow. I read that increasing CLDO VDDP and VDDG CCD and VDDG IOD can help with stability and with USB issues, from the X570 HERO motherboard thread.


----------



## heptilion

Can someone please provide me with some advice on how to get out of errors 2,10,13,8 please.

Things i have tried.

Trdwr/twrrd =10/3 , 8/4, 9/4, 8,4
lowered trfc timings, trtp to 8, tcwl 16,
rtts = 5/3/3, 6/3/3, 7/3/3.
dimm range 1.52 - 1.62.


----------



## Veii

Taraquin said:


> According to Veii Micron ram possibly benefits from the 8 RFC for 8gb modules, 16 RFC for 16gb modules like Intel do.


I can not agree
This were anta's words
Been there and this multiple of 32 makes not fully sense (before mini module was published)
It does within exceptions focusing on a 14-14 preset
But is not from my perspective always the case

Also less relevant for micron dimms and lpddr or gddr


Blackfyre said:


> *Are these voltages safe for 24/7?* The board gets good airflow. I read that increasing CLDO VDDP


A memory controller, has zero connection to the GMI & DPM links going towards PCH
Which is what manages I/O stability

Also FCLK and cLDO_VDDP have no connection
Voltages are high, but beyond 950mV, and bellow 2300 MCLK
Just a waste and lower signal integrity
Else they are safe


----------



## Bloax

Blackfyre said:


> I read that increasing CLDO VDDP and VDDG CCD and VDDG IOD can help with stability and with USB issues, from the X570 HERO motherboard thread.
> View attachment 2565908


bro the USB issues are tied to FCLK dropouts, which are caused by running a set of SOC/IOD/CCD voltages that isn't the "Goldilocks Voltage"
(not toO loW, not Too HiGH, J U S T right)
too high voltages cause more dropouts : - DDD

if your memory is stable you can figure this out by trying an unreasonable amount of variations and seeing which one gives you the best y-cruncher 2.5 billion time, using a static CPU frequency (like 4.4 Ghz @ 1.125v) because boosting doesn't behave 100% consistently (and we desperately want consistency)

a little tip is trying to find the "best performing" set of "relations", steps of e.g. 25mV or 50mV, to offset IOD and CCD from SOC
as an example then my 5800x liked SOC, -50 mV IOD, -250 mV CCD*

this lets you save on testing time by trying less values simply by shifting SOC around and increasing/lowering IOD and CCD by the same amount
*except -240 mV CCD performed even better, so nudge them around once you find the seemingly best performing base SOC voltage, just to be sure








(this is "msconfig.exe" in c:/Windows/system32/)

easy trick for shortening bootup times and having less background tasks to make results unpredictable


https://dl.dropbox.com/s/b9klss9c3fbz09o/ycruncher.7z


if dear passerby reader doesn't have y-cruncher, then here it is with a convenient 2.5 billion .bat file to make a shortcut to on your desktop


good luck


----------



## Taraquin

Veii said:


> I can not agree
> This were anta's words
> Been there and this multiple of 32 makes not fully sense (before mini module was published)
> It does within exceptions focusing on a 14-14 preset
> But is not from my perspective always the case
> 
> Also less relevant for micron dimms and lpddr or gddr
> 
> A memory controller, has zero connection to the GMI & DPM links going towards PCH
> Which is what manages I/O stability
> 
> Also FCLK and cLDO_VDDP have no connection
> Voltages are high, but beyond 950mV, and bellow 2300 MCLK
> Just a waste and lower signal integrity
> Else they are safe


Okay, I thought I remebered you saying that this may apply to Micron dimms, but maybe I remembered wrong.


----------



## Bloax

heptilion said:


> Can someone please provide me with some advice on how to get out of errors 2,10,13,8 please.
> 
> Things i have tried.
> 
> Trdwr/twrrd =10/3 , 8/4, 9/4, 8,4
> lowered trfc timings, trtp to 8, tcwl 16,
> rtts = 5/3/3, 6/3/3, 7/3/3.
> dimm range 1.52 - 1.62.
> 
> View attachment 2565914


tWR doesn't always like being 2x RTP on some sticks, just a couple of days ago I was helping someone on an LGA1151 system whose sticks wanted RTP 6 and tWR 10 - could be that yours want that too.


----------



## Gregix

Hi.
I managed to rid off WHEA, yet have some TM5 errors. 11 or 13 once, or had 12 too and 6. Not too much, like 3errors in one of tests and different TM5 configs give different errors. Tried extreeme, Ollie and absolute.
Any idea what to improve? Or just go back to 3800Mhz?


----------



## SneakySloth

Got a system freeze on my linux install and I've been testing my overclocks again to confirm stability. Surprisingly TM5 gave me errors after 6 hours twice now. Would errors that late into a test potentially be heat related or timings? I was using the Universal profile and not 1usmus.


----------



## Melan

SneakySloth said:


> Got a system freeze on my linux install and I've been testing my overclocks again to confirm stability. Surprisingly TM5 gave me errors after 6 hours twice now. Would errors that late into a test potentially be heat related or timings? I was using the Universal profile and not 1usmus.


Probably heat? I usually run universal profile with furmark to roast the memory (and gpu). It starts spewing errors pretty quick if it gets too hot.


----------



## The_King

Im busy testing how high I can boot my 8GBX4 mixed GSkill and Patriot Viper without WHEA errors.
First test with mostly AUTO for VSOC CCD IOD which i will drop later. Its left high to eliminate boot issues

First question, Im not too happy with the temps going that high, is it possible to damage B-die form temps like these?
Second question since there is no errors at these high temps 55/57 does it mean these sticks have good temp tolerants?

I have read the betweem 40-45 is preffered but under 50 is OK in most cases.


----------



## Blameless

Pretty much any consumer DRAM IC is rated to work at 85C at JEDEC spec, or 95C with more frequent refreshed. Of couse, this is with low clocks, slack timings, and much lower voltage than we typically run on what's presented in this thread.

That said, I'm not concerned in the least about the longevity of most Samsung B-die at ~1.5v even at the ~70C peaks I can see. Reliability/longevity at higher voltages is a much more open question. Past a certain level voltage's effect on longevity is exponential, while every 10C increase in temperature can be (very roughly) estimated to cut IC life in half.


----------



## The_King

Blameless said:


> Pretty much any consumer DRAM IC is rated to work at 85C at JEDEC spec, or 95C with more frequent refreshed. Of couse, this is with low clocks, slack timings, and much lower voltage than we typically run on what's presented in this thread.
> 
> That said, I'm not concerned in the least about the longevity of most Samsung B-die at ~1.5v even at the ~70C peaks I can see. Reliability/longevity at higher voltages is a much more open question. Past a certain level voltage's effect on longevity is exponential, while every 10C increase in temperature can be (very roughly) estimated to cut IC life in half.


Thanks for the reply.

This brings me to my next question. 85C is where RFC2/4 works else they do basically nothing.

Should you even set RFC2/4 if your temps are not going anywhere near 85C? I usually dont has seen in my screenshots.

and why on earth will RFC2/4 be lower than main RFC when temps are high? Will that not lead to increased temps? 🤷‍♂️


----------



## Blameless

The_King said:


> This brings me to my next question. 85C is where RFC2/4 works else they do bascially nothing.
> 
> Should you even set RFC2/4 if your temps are not going anywhere near 85C? I usually dont has seen in my screenshots.
> 
> and why on earth will RFC2/4 be lower than main RFC when temps are high? Will that not lead to increased temps? 🤷‍♂️


It's not tRFC that changes at 85C, it's tREFI, which we can't adjust on AMD. A 85C the full refresh duration (tRFC) is kept, it's just done twice as often (half the tREFI). Increasing refresh frequency does increase power and heat, but it's part of the spec because higher temperature implies a higher self-discharge rate for capacitors (including DRAM cells) and not cutting tREFI could lead to the charge falling below the minimum required.

tRFC 2/4 are for FGR (fine granularity refresh) which are shorter, more frequent, refreshes that can reduce the latency of some operations. There is considerable doubt as to whether it's enabled on this platform, but I've seen enough weirdness with them set too low that I usually try to use values that make sense.


----------



## Taraquin

Gregix said:


> Hi.
> I managed to rid off WHEA, yet have some TM5 errors. 11 or 13 once, or had 12 too and 6. Not too much, like 3errors in one of tests and different TM5 configs give different errors. Tried extreeme, Ollie and absolute.
> Any idea what to improve? Or just go back to 3800Mhz?
> View attachment 2565979


Try RRDL 6 and/or RCDRD 16, it may remove the errors.


----------



## Gregix

Thx.
Now I have only #11 tm5 error, which point to cad bus...


----------



## Taraquin

Gregix said:


> Thx.
> Now I have only #11 tm5 error, which point to cad bus...


CAD bus is tricker as it is connected to DrvStr and ProcODT. Suggestion, try 40 20 30 20 and test higher\lower ProcODT (32-43), it may fix the issues.

I would suggest trying RC at 45 and RTP at 6 with your current settings btw


----------



## Taraquin

The_King said:


> Im busy testing how high I can boot my 8GBX4 mixed GSkill and Patriot Viper without WHEA errors.
> First test with mostly AUTO for VSOC CCD IOD which i will drop later. Its left high to eliminate boot issues
> 
> First question, Im not too happy with the temps going that high, is it possible to damage B-die form temps like these?
> Second question since there is no errors at these high temps 55/57 does it mean these sticks have good temp tolerants?
> 
> I have read the betweem 40-45 is preffered but under 50 is OK in most cases.
> View attachment 2566007


B-die can handle 80C fine, BUT it will become temp sensitive if highly tuned\overclocked. Especially RFC is temp-sensitive. You may need to get temps lower in order to tighen RFC. Best way for that is to lower voltage and\or increase airflow. Do you really need 1.51v dimm for cl16 to be stable? Your current RFC should be fine with below 1.45V, but depends on other timings.


----------



## The_King

Taraquin said:


> B-die can handle 80C fine, BUT it will become temp sensitive if highly tuned\overclocked. Especially RFC is temp-sensitive. You may need to get temps lower in order to tighen RFC. Best way for that is to lower voltage and\or increase airflow. Do you really need 1.51v dimm for cl16 to be stable? Your current RFC should be fine with below 1.45V, but depends on other timings.


At the moment the entire setup is out of the case so there is Zero or no airflow at all.hence poor thermals on the RAM.
My phanteks PH-TC14PE is not helping the situation by covering all 4 DIMMS. 🤦‍♂️
The RAM temps are much better in the case with three front fans directing the airflow.
Looking for a better case at the moment looking at the Lan Li Lancool II mesh or the Lan Li 215 X.

I usually prefer to tune around 1.44V-1.45V with 2 sticks, with 4 sticks it seems the higher VDIMM is needed to boot.


----------



## GrumpyCalabi314

Hi guys! Some advice on what can be improved (Micron Rev. E, 5600X, B550M Mortar on AGESA 1.2.0.7)? I'm 30 cicles of TM5 w/ anta absolut (~11 hours) and 110K Karhu (~30 hours) stable.


----------



## Taraquin

GrumpyCalabi314 said:


> Hi guys! Some advice on what can be improved (Micron Rev. E, 5600X, B550M Mortar on AGESA 1.2.0.7)? I'm 30 cicles of TM5 w/ anta absolut (~11 hours) and 110K Karhu (~30 hours) stable.
> View attachment 2566027


Try lowering RAS and RC by 1 and 1. Good rev E can do RC 52 at 3800. WR 16, RTP 8. RFC may do 530-540. Rest of timings looks very good. You may do CL15, but need 1.45v+ and that can be negative for RCDRD and RFC.


----------



## SneakySloth

I increased my VSOC from 1.1125 to 1.1250 and put a fan more directly on top of the Ram. This time, instead of an error at 5-6 hours, got a single error at around ~13 hours using Tm5 + Universal 2 profile.

I changed from 1T -> 2T and set AddrCmdSetup from 56 -> 0. Does anyone have any idea if there is anything else that looks off here?


----------



## Veii

Blameless said:


> Increasing refresh frequency does increase power and heat, but it's part of the spec because higher temperature implies a higher self-discharge rate for capacitors (including DRAM cells) and not cutting tREFI could lead to the charge falling below the minimum required.
> 
> tRFC 2/4 are for FGR (fine granularity refresh) which are shorter, more frequent, refreshes that can reduce the latency of some operations. There is considerable doubt as to whether it's enabled on this platform, but I've seen enough weirdness with them set too low that I usually try to use values that make sense.


Agree 

tRFC2/4 is a bothersome topic, and unclear
In theory to what i can dig up ~ AMD's IMC does not function the same way and does not follow the same specs nor functionality as in intel's counterpart
Which also means it handles JEDEC different and gets up with own specifications

Problem is tRFC depend on tSTAG state
tSTAG state depends on tMAW.tMAC or so called RC_PAGE
That RC_PAGE depends on memory controller (MSR) and Urg/SubUrg refresh autodecided

Now going back
RC_PAGE at unlimited MAC or at limited MAC (auto decided)
Will influence tSTAG and will influence refresh type chosen (by following or ignoring tRC)

Another problem
For tRFC 2 or 4 to function, dimms need to be thermal aware
They can not be without having a sensor integrated into them

Yet the board appears to do some predictions
I see RC_PAGE being used following JEDEC (non set custom frequency) and so also till a specific range ~ mostly 3600MT/s, being auto adjusted (tRFC2/4 being correct)
Yet ~ it does not do it always & on higher frequencies falls back to very low values, yet is not 0-0 (like on CKE @ low freq)

From my personal perspective they are used
They are also used to create tRFC 1 (it's the opposite way)
But sometimes they can not be used on dimms without a thermal sensor

I can fully agree on the weirdness that happens with them, and i do feel AMD does some prediction shenanigans, to cover up dimms without thermal sensors
Because if they wouldn't - they will not be loaded, yet used for XMP and other profile generation.

An "it's not actively used, but it is used for other timings" ~ kind of topic 
EDIT:
Arshia tried to explain with me, how "my" tRC+1, and tFAW 6 (half clock = impossible) exploit could work
And we came to the conclusion that AMD's IMC vendor, does not follow JEDEC. Not fully at least
^ in connection to UrgRefresh-Mode


----------



## Bloax

Funny observation: Doubling the minimum stable RTP/tWR seems to have worked on two (technically, three) different sets of memeory.
Doing so raises the temperature resistance of the memory - originally did it for someone who was using dual-rank bdie sticks in an ITX hot-box case, 60+ C on just the chips during use  - with a minimal performance hit --
on my wacky z690 4x8 config (featuring sticks that "Demand" RTP 5/10) RTP 10/20 _actually performs better_ than 5/10 and is also stable unlike 6/12 7/14 or 8/16

Might not be a good idea on single-rank setups, where doubling the duration of the background tWR/RTP processes may actually impact how many groups are available to access - but on dual-rank .. I should test my "thoroughly CURSED" dual-rank kit that throws temperature errors at 35 C again...


----------



## The_King

Bloax said:


> Funny observation: Doubling the minimum stable RTP/tWR seems to have worked on two (technically, three) different sets of memeory.
> Doing so raises the temperature resistance of the memory - originally did it for someone who was using dual-rank bdie sticks in an ITX hot-box case, 60+ C on just the chips during use  - with a minimal performance hit --
> on my wacky z690 4x8 config (featuring sticks that "Demand" RTP 5/10) RTP 10/20 _actually performs better_ than 5/10 and is also stable unlike 6/12 7/14 or 8/16
> 
> Might not be a good idea on single-rank setups, where doubling the duration of the background tWR/RTP processes may actually impact how many groups are available to access - but on dual-rank .. I should test my "thoroughly CURSED" dual-rank kit that throws temperature errors at 35 C again...


Y-cruncher with TWR/RTP 10/6 yeah i know it should be 10/5.

Total Computation Time: 176.733 seconds
Start-to-End Wall Time: 179.718 seconds

Y-cruncher TWR/RTP 20/10

Total Computation Time: 169.204 seconds
Start-to-End Wall Time: 172.313 seconds

NB: ECO mode was on with both runs (45W)










WIll have to recheck this test again tomorrow and test 12/6. Anyone else can confirm the same?


----------



## Bloax

I would still recommend static (manual) CPU multiplier + voltage, to keep results 100% consistent, but a 4% improovment is really funny

rtp 10 / 20 might even make AddrCmdSetup unnecessary on viper 4400's but I'm still checking










With a recommendation like that, I'm starting to wonder where I should start looking for POTENTIAL VICTIMS of making system go vroom-vroom - as I have a heavy trauma victim facing eviction to be a charity for, hehe.

And I sure love having chitty-chats while making memory systems explode into working well! 🦑


----------



## MrHoof

Bloax said:


> I would still recommend static (manual) CPU multiplier + voltage, to keep results 100% consistent, but a 4% improovment is really funny
> 
> rtp 10 / 20 might even make AddrCmdSetup unnecessary on viper 4400's but I'm still checking
> 
> 
> View attachment 2566050
> 
> With a recommendation like that, I'm starting to wonder where I should start looking for POTENTIAL VICTIMS of making system go vroom-vroom - as I have a heavy trauma victim facing eviction to be a charity for, hehe.
> 
> And I sure love having chitty-chats while making memory systems explode into working well! 🦑


I dont think there is any timing that can change AddrCmdSetup, it works without or it does not is what I observed and 99% of the time boards that work without are ASUS.
Like for my example I can run 1T without AddrCmdSetup but 56 will be bluescreen on boot. Also I dont think it hinders performance either when comparing benchmarks from people with true 1T and people with AddrCmdSetup 56.


----------



## Bloax

It's more me presenting a hypothesis out loud, because suddenly all these values can be set to 0 without the memory exploding.









edit: yep it's stable


----------



## Gregix

So there it is. Instead WHEA while running TM5/prime95 small ftt/blend/whatever and running those test without errors I now have constant #2 error in TM5 (in 14sec to 1 min, depends on ProcODT value) and crashing workers in prime, but no WHEA.
I think I'll give up. Will go down to 3800c14, try to tune it and be it. 
And this RAM is weak, 8 layers, at 3933 tRFC below 300 starting giving problems(from TM5 even don't starting) to no boot at all(tried 274 and had to CMOS clear).
Maybe I should go back to patriots? 4400c19...but have only 2 of them (16gb only)so....


----------



## Blameless

Bloax said:


> on my wacky z690 4x8 config (featuring sticks that "Demand" RTP 5/10) RTP 10/20 _actually performs better_ than 5/10 and is also stable unlike 6/12 7/14 or 8/16


It's marginally faster on my 5800X3D with 2x16GiB dual-rank Samsung B-die as well.

5/10:









10/20:









AIDA64 and my quick Memtest86 test #7 single loop time were well within margin of error, but the benefit to WinRAR (which is ultra sensitive to everything cache/memory related) is slightly beyond run-to-run and train-to-train variance.


----------



## domdtxdissar

Hmm i'm finding the opposite to you guys at static 4.5ghz in y-cruncher.

tWR = 5
tRTP = 10










tWR = 10
tRTP = 20









Sticking to my tried and tested memory profile 

_edit_
Have custom cooling on the memory, 30 degrees with 1.6vdimm atm, can affect results if this "tweak" was manly to help with temperature limited sticks


----------



## Veii

I'll join the testing @Bloax but with Rev.E for now
It seems as always to be an alignment issue
Very happy to see that at this thread here doesn't go for "lowest is the best"
Proud haha, but rather happy

No pattern for it so far, but i could bet tCWL will show a change with it
@domdtxdissar can you test a bit more broad 7-14 , 8-16

or rather for me as i dont have anything DR that can do tCL 13, tCWL 12
tRTP 8, tWR 12 ?

Can't run anything benchmate still, even with the 1200AF temporary setup
(messed up ITX on 1207 update [always update both boot and mainblock] messed up also soldering, waiting for wson pogo now)
Have to see how i can get Pi 2.5b results

Had fun ~ but main setup is rip for next two weeks


----------



## Bloax

I tried it out in the context of a super-high-temperature scenario requiring it for extra stability, but then decided to see if 2x RTP/tWR would run on my system, out of "is this a repeatable pattern" curiosity and it did.. Better than before, even!


domdtxdissar said:


> Hmm i'm finding the opposite to you guys at static 4.5ghz in y-cruncher.
> 
> tWR = 5
> tRTP = 10
> View attachment 2566067
> 
> 
> 
> tWR = 10
> tRTP = 20
> View attachment 2566068
> 
> 
> Sticking to my tried and tested memory profile
> 
> _edit_
> Have custom cooling on the memory, 30 degrees with 1.6vdimm atm, can affect results if this "tweak" was manly to help with temperature limited sticks


Bear in mind that both of the ones who saw the most improvement, were running tRAS = tCL + tRCD - the one with very mild improvements, very close to RAS = tCL + RTP, whereas you are 1 below tCL + RTP


----------



## domdtxdissar

Veii said:


> I'll join the testing @Bloax but with Rev.E for now
> It seems as always to be an alignment issue
> Very happy to see that at this thread here doesn't go for "lowest is the best"
> Proud haha, but rather happy
> 
> No pattern for it so far, but i could bet tCWL will show a change with it
> @domdtxdissar can you test a bit more broad 7-14 , 8-16
> 
> or rather for me as i dont have anything DR that can do tCL 13, tCWL 12
> tRTP 8, tWR 12 ?
> 
> Can't run anything benchmate still, even with the 1200AF temporary setup
> (messed up ITX on 1207 update [always update both boot and mainblock] messed up also soldering, waiting for wson pogo now)
> Have to see how i can get Pi 2.5b results
> 
> Had fun ~ but main setup is rip for next two weeks


Have to be tomorrow as i have some other testing to do first..
Btw 7zip v22 also seem to be a pretty good cpu/memory benchmark 
(easy to find reduced performance from whea's if not everything is tuned/balanced 100% correct)


----------



## RaXelliX

Any suggestions? These still gave a few errors in test #15 after two cycles using TM5 with Absolut config:









AIDA64 latency ~60ns. 4x8GB Viper Steel 4400 C19 B-Die.
I've heard that first gen X570 is weird when it comes to memory OC. Especially Gigabyte.


----------



## Taraquin

Gregix said:


> View attachment 2566063
> 
> So there it is. Instead WHEA while running TM5/prime95 small ftt/blend/whatever and running those test without errors I now have constant #2 error in TM5 (in 14sec to 1 min, depends on ProcODT value) and crashing workers in prime, but no WHEA.
> I think I'll give up. Will go down to 3800c14, try to tune it and be it.
> And this RAM is weak, 8 layers, at 3933 tRFC below 300 starting giving problems(from TM5 even don't starting) to no boot at all(tried 274 and had to CMOS clear).
> Maybe I should go back to patriots? 4400c19...but have only 2 of them (16gb only)so....


It can sometimes be WTRL. Above 3800 I need 9 on WTRL, 8 gives me errors.


----------



## Taraquin

Blameless said:


> It's marginally faster on my 5800X3D with 2x16GiB dual-rank Samsung B-die as well.
> 
> 5/10:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 10/20:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> AIDA64 and my quick Memtest86 test #7 single loop time were well within margin of error, but the benefit to WinRAR (which is ultra sensitive to everything cache/memory related) is slightly beyond run-to-run and train-to-train variance.


Could it be related to SOC/IOD in your case? 10/5 is much harder on IMC than 20/10, ypu run absurdly low SOC/IOD for 3800. Could it be that you get throttling due to too tight timings combined with too low voltage at 10/5? I need 1.06v SOC and 0.98v IOD at 3800 to avoid throttling.


----------



## Taraquin

The_King said:


> Y-cruncher with TWR/RTP 10/6 yeah i know it should be 10/5.
> 
> Total Computation Time: 176.733 seconds
> Start-to-End Wall Time: 179.718 seconds
> 
> Y-cruncher TWR/RTP 20/10
> 
> Total Computation Time: 169.204 seconds
> Start-to-End Wall Time: 172.313 seconds
> 
> NB: ECO mode was on with both runs (45W)
> 
> View attachment 2566048
> 
> 
> WIll have to recheck this test again tomorrow and test 12/6. Anyone else can confirm the same?


I wonder if you can test what I suggested for Blameless? Run SOC/IOD at slightly higher voltage when running 10/5 as 10/5 is harder on IMC making throttling due to low voltage more likely. 

It can also be that for some reason your system prefers those timings. I get a bit better perf with 10/5 than 16/8 which I should use according to anta777. 

Some timings like SCLs can often perform worse at lower vs higher so that it can happend with WR/RTP or some other timings seems likely.


----------



## Taraquin

Even though anta777 is somewhat disputed and I found that breaking his 'rules' sometimes yields better perf (like going lowrr on RAS/RC) it seems most of them applies quite well. Some interesting relations seem to occur than can greatly impact performance:


CL/Command rate and PHYL 26/28. Some get different PHYL using CL15, some get different using 1t vs 2t.
CWL/RDWR: Lower one makes the other go up, RDWR seems most beneficial, but perhaps not always.
SCLs often performs better at 4 than 2 or 3 which in theory dhould be best.
WR/RTP should be in a 2:1 relation, but sometimes performs better if unsynced (lack of voltage may be a reason for this, not sure yet).

Veii, Bloax and others probably have knowledge of more interesting relations between timings


----------



## The_King

Taraquin said:


> I wonder if you can test what I suggested for Blameless? Run SOC/IOD at slightly higher voltage when running 10/5 as 10/5 is harder on IMC making throttling due to low voltage more likely.
> 
> It can also be that for some reason your system prefers those timings. I get a bit better perf with 10/5 than 16/8 which I should use according to anta777.
> 
> Some timings like SCLs can often perform worse at lower vs higher so that it can happend with WR/RTP or some other timings seems likely.


With TWR 20 RTP 10. I can do things like WR 8 and managed to drop VDIMM from 1.48V to 1.46V.
Also now I can be one of the cool kids and run low RP. 😎 

RC should be 42 🤦‍♂️

@Bloax Seems there is something to the theory of better heat tolerants with TWR/RTP 20/10


----------



## Taraquin

The_King said:


> With TWR 20 RTP 10. I can do things like WR 8 and managed to drop VDIMM from 1.48V to 1.46V.
> Also now I can be one of the cool kids and run low RP. 😎
> 
> RC should be 42 🤦‍♂️
> 
> @Bloax Seems there is something to the theory of better heat tolerants with TWR/RTP 20/10
> View attachment 2566105


Some timings are very sensitive to voltage on B-die, the 3 primeries, RRDS/FAW/WR/RTP, RC and RFC also scales/is sensitive to voltage. RAS, SCLs, WTRs etc don't seem to care much for voltage. On other ram kits like rev E, Hynix AFR etc the generally cared little about voltage except for CL/CWL, rest of timings is more in relation to frequency.

How do the 'correct' WR/RTP of 16/8 perform vs 20/10?


----------



## The_King

Taraquin said:


> Some timings are very sensitive to voltage on B-die, the 3 primeries, RRDS/FAW/WR/RTP, RC and RFC also scales/is sensitive to voltage. RAS, SCLs, WTRs etc don't seem to care much for voltage. On other ram kits like rev E, Hynix AFR etc the generally cared little about voltage except for CL/CWL, rest of timings is more in relation to frequency.
> 
> How do the 'correct' WR/RTP of 16/8 perform vs 20/10?





Taraquin said:


> Some timings are very sensitive to voltage on B-die, the 3 primeries, RRDS/FAW/WR/RTP, RC and RFC also scales/is sensitive to voltage. RAS, SCLs, WTRs etc don't seem to care much for voltage. On other ram kits like rev E, Hynix AFR etc the generally cared little about voltage except for CL/CWL, rest of timings is more in relation to frequency.
> 
> How do the 'correct' WR/RTP of 16/8 perform vs 20/10?


This is very interesting indeed 16/8 fails Y-runcher I ran the test over 10 times. It fails everytime









Improved timings today with TWR 20/10 and WR 8 164 seconds. was 169 seconds before with just TWR 20/10 only changed (ECO Mode 45W)


----------



## ioannis91

The CWL/RDWR is interesting. I've always used CWL 14 and my mobo trains RDWR 10 and I just leave it at that cause it's stable. With CWL 16 it trains RDWR 8. So the lower RDWR might be faster? And how to check? With Aida or something more stressful like y-cruncher?


----------



## GrumpyCalabi314

Taraquin said:


> Try lowering RAS and RC by 1 and 1. Good rev E can do RC 52 at 3800. WR 16, RTP 8. RFC may do 530-540. Rest of timings looks very good. You may do CL15, but need 1.45v+ and that can be negative for RCDRD and RFC.





Taraquin said:


> Try lowering RAS and RC by 1 and 1. Good rev E can do RC 52 at 3800. WR 16, RTP 8. RFC may do 530-540. Rest of timings looks very good. You may do CL15, but need 1.45v+ and that can be negative for RCDRD and RFC.


Thanks for your time man, appreciated! I tried tRFC at 532 (280ns) and it passes 30 cycles (~11hours) of TM5 w/ absolut. 530 simply refuses to boot, so i think i'm on the edge of stability. Will do further stability testing but i've got some questions about tRFC. How much tRFC is temperature dependent and how much can cause ''silent'' corruption like i read for tREFI when on the edge of stability? How hard is it to test (e.g. i read that tWR is know for ''randomly error'' after a long period of time)? If 530 doesn't even boot, would you feel safe to stay daily with 532, if proper tested? I've also read that it should be a multiple of tRC, that should be divisible by 8 or 16... Should i follow those rules?


----------



## Taraquin

ioannis91 said:


> The CWL/RDWR is interesting. I've always used CWL 14 and my mobo trains RDWR 10 and I just leave it at that cause it's stable. With CWL 16 it trains RDWR 8. So the lower RDWR might be faster? And how to check? With Aida or something more stressful like y-cruncher?


Dxtdomdissar tested and got slightly better in Y-crucher if I remember correct. It may not always be beneficial, but sometimes.


----------



## Taraquin

GrumpyCalabi314 said:


> Thanks for your time man, appreciated! I tried tRFC at 532 (280ns) and it passes 30 cycles (~11hours) of TM5 w/ absolut. 530 simply refuses to boot, so i think i'm on the edge of stability. Will do further stability testing but i've got some questions about tRFC. How much tRFC is temperature dependent and how much can cause ''silent'' corruption like i read for tREFI when on the edge of stability? How hard is it to test (e.g. i read that tWR is know for ''randomly error'' after a long period of time)? If 530 doesn't even boot, would you feel safe to stay daily with 532, if proper tested? I've also read that it should be a multiple of tRC, that should be divisible by 8 or 16... Should i follow those rules?


On my rev E at 3733 I can't boot 520, 522 works totally stable, no issues. On rev E temp does very little to RFC, on Samsung B-die, mem can become unstable if RFC is liw and temps high, this may cayse corruption of files. I haven't gotten this with rev E. 

If you get random BSOD/Reboots try running RFC at 535 or something.


----------



## ioannis91

Taraquin said:


> Dxtdomdissar tested and got slightly better in Y-crucher if I remember correct. It may not always be beneficial, but sometimes.


Slightly worse here, but barely


----------



## The_King

The_King said:


> This is very interesting indeed 16/8 fails Y-runcher I ran the test over 10 times. It fails everytime
> View attachment 2566106
> 
> 
> Improved timings today with TWR 20/10 and WR 8 164 seconds. was 169 seconds before with just TWR 20/10 only changed (ECO Mode 45W)
> View attachment 2566107


Here is almost the full beans PB0 +200Mhz no CO. Just to show its also stable with PBO on and +200Mhz (updated) 126.040


----------



## domdtxdissar

ioannis91 said:


> The CWL/RDWR is interesting. I've always used CWL 14 and my mobo trains RDWR 10 and I just leave it at that cause it's stable. With CWL 16 it trains RDWR 8. So the lower RDWR might be faster? And how to check? With Aida or something more stressful like y-cruncher?


I did some tests on different memory settings, among them CWL/RDWR.
Results can be found here


----------



## The_King

The_King said:


> This is very interesting indeed 16/8 fails Y-runcher I ran the test over 10 times. It fails everytime
> View attachment 2566106
> 
> 
> Improved timings today with TWR 20/10 and WR 8 164 seconds. was 169 seconds before with just TWR 20/10 only changed (ECO Mode 45W)
> View attachment 2566107


So here are the final results with all 3 tests PBO +200



Spoiler: TWR 20 RTP 10



126.040 seconds














Spoiler: TWR 12 RTP 6



125.397 seconds














Spoiler: TWR 10 RTP 6



126.250 seconds











Fastest time TWR 12 RTP 6.

TWR 16 RTP 8 - does not complete Y-cruncher test.


----------



## Bloax

I'm just pleased to see sticks that "force" RTP 5/10 to also randomly run better with a more temperature-resistant RTP 10/20, as the 5/10 fragility was really annoying, hehe


Taraquin said:


> Some timings are very sensitive to voltage on B-die, the 3 primeries, RRDS/FAW/WR/RTP, RC and RFC also scales/is sensitive to voltage. RAS, SCLs, WTRs etc don't seem to care much for voltage.
> 
> How do the 'correct' WR/RTP of 16/8 perform vs 20/10?


In my experience, then RRD/FAW/WTR are completely down to DRAM input voltage (cpu 1.8v / 1p8 / vdd18 / cpu 1.8v standby voltage?? / cpu aux voltage ...) and low procODT than about voltage.








as at the same DRAM voltage, the difference between procODT 34.3 + 1.80v vs. procODT 30 + 1.85v - was the difference between being stuck at RRD/WTR 6/12 and being able to run RRD 4/6 + WTR 4/8 (on sticks that never did WTRL 8 above DDR4-3600 in the past!)

RTP is completely independent of voltage, and in fact - there is no "correct" value, it comes down to the requirements of the RAM PCB. (important for mixing kits in 4-DIMM configs)
It's in fact the reason I have a quote like


> tRTP and tWR are connected, and usually tWR wants to be 2x of RTP ...
> .. blah blah sometimes not 2x sometimes tWR is lower, sometimes only one value works, sometimes a range of values are ok ..
> 
> *This will likely be the first timing combo you will have to figure out to stop random errors*, in TM5 they usually produce errors #2, #10 and #12 or some similar minor-timeout-error, it's been a while.
> So don't be surprised if it errors when you initially throw, for example, tRTP 8 + tWR 16 at it - try RTP 7 + tWR 14 next, then RTP 6 + 12, then 5 + 10, then 6 + 14, then 6 + 16, then 7 + 16, 5 + 12, 5 + 14 .. until those minor timeout errors stop.


right here: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread (i should really format this better and repost it)

Because while "super safe timings" are a thing for basically any primary/secondary timing, and auto RDWR/WRRD/Tertiaries tend to Just Work, RTP and tWR vary from memory PCB to memory PCB.

So if you find them first, you are suddenly free to find the rest of your optimal memory timings, without them getting in the way.
If memeory serves (hah hah) then they are also a pair of the "background process" timings which occur all the time, independently of the tRAS/tRC row access/gathering being triggered, which is why their impact on performance is usually non-existent. This is also why I was surprised to see _going notably slower_ suddenly _going faster!_
I would also just like to remind that this is about the "lowest RTP / tWR combo your DIMMs like", times 2 - not RTP 10 tWR 20 in particular.
Just RTP 5/10 was what my Viper 4000 16-16-16 sticks _demanded_ to run stable, except they also ran 2x that.. Better! Wacky!

I much prefer the Sweet Simplicity of keeping tCL-tRCD-tRP-tRAS-tRC-tRFC all tied together, and they do in fact scale with voltage on b-die - usually at a consistent +/- vDIMM interval - up to the lottery limit of either your memory controller, or the particular DIMM itself.
Saves a lot of hassle, this simplification, it does


----------



## Blameless

Taraquin said:


> Could it be related to SOC/IOD in your case? 10/5 is much harder on IMC than 20/10, ypu run absurdly low SOC/IOD for 3800. Could it be that you get throttling due to too tight timings combined with too low voltage at 10/5? I need 1.06v SOC and 0.98v IOD at 3800 to avoid throttling.


I'm confident this setup isn't throttling at 10/5 with these voltages.


----------



## Blameless

Taraquin said:


> Could it be related to SOC/IOD in your case? 10/5 is much harder on IMC than 20/10, ypu run absurdly low SOC/IOD for 3800. Could it be that you get throttling due to too tight timings combined with too low voltage at 10/5? I need 1.06v SOC and 0.98v IOD at 3800 to avoid throttling.


I'm confident this setup isn't throttling at 10/5 with these voltages.



Bloax said:


> I'm just pleased to see sticks that "force" RTP 5/10 to also randomly run better with a more temperature-resistant RTP 10/20, as the 5/10 fragility was really annoying, hehe


WinRAR is about the only test I could see a small advantage in; everything else is pretty much margin of error. My sticks are also long term stable to at least 70C with tRTP 5/tWR 10 at 3800, but I'm hopeful that being able to loosen those timings without hurting performance will let me tighten up something elsewhere.


----------



## Blameless

Did some more iterations of AIDA64 and 7-zip with a fair number of reboots to average out training variance.

10/5 is about 100MiB/s faster read and copy in AIDA64 and maybe ~0.3GIOPS faster in 7-zip. However, 20/10 is consistently 0.1ns faster in AIDA64 latency and, again, slightly above margin of error in WinRAR. Have yet to bench any meaningful difference elsewhere, but 20/10 seems slightly faster than anything between 10/5 and 20/10 (though all of them seem stable) and is so close to 10/5 that if it proves more stable in any other combination they will probably be my go to combination.

One oddity I did notice with 20/10 was that I immediately lost some performance when I reduced tRAS and tRC by two ( to 25 and 38), which doesn't happen at 10/5 (it's just not completely stable in long test runs). The higher tRTP may still mandate a higher useful tRAS floor.


----------



## Taraquin

Bloax said:


> I'm just pleased to see sticks that "force" RTP 5/10 to also randomly run better with a more temperature-resistant RTP 10/20, as the 5/10 fragility was really annoying, hehe
> 
> In my experience, then RRD/FAW/WTR are completely down to DRAM input voltage (cpu 1.8v / 1p8 / vdd18 / cpu 1.8v standby voltage?? / cpu aux voltage ...) and low procODT than about voltage.
> View attachment 2566122
> 
> as at the same DRAM voltage, the difference between procODT 34.3 + 1.80v vs. procODT 30 + 1.85v - was the difference between being stuck at RRD/WTR 6/12 and being able to run RRD 4/6 + WTR 4/8 (on sticks that never did WTRL 8 above DDR4-3600 in the past!)
> 
> RTP is completely independent of voltage, and in fact - there is no "correct" value, it comes down to the requirements of the RAM PCB. (important for mixing kits in 4-DIMM configs)
> It's in fact the reason I have a quote like
> 
> right here: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread (i should really format this better and repost it)
> 
> Because while "super safe timings" are a thing for basically any primary/secondary timing, and auto RDWR/WRRD/Tertiaries tend to Just Work, RTP and tWR vary from memory PCB to memory PCB.
> 
> So if you find them first, you are suddenly free to find the rest of your optimal memory timings, without them getting in the way.
> If memeory serves (hah hah) then they are also a pair of the "background process" timings which occur all the time, independently of the tRAS/tRC row access/gathering being triggered, which is why their impact on performance is usually non-existent. This is also why I was surprised to see _going notably slower_ suddenly _going faster!_
> I would also just like to remind that this is about the "lowest RTP / tWR combo your DIMMs like", times 2 - not RTP 10 tWR 20 in particular.
> Just RTP 5/10 was what my Viper 4000 16-16-16 sticks _demanded_ to run stable, except they also ran 2x that.. Better! Wacky!
> 
> I much prefer the Sweet Simplicity of keeping tCL-tRCD-tRP-tRAS-tRC-tRFC all tied together, and they do in fact scale with voltage on b-die - usually at a consistent +/- vDIMM interval - up to the lottery limit of either your memory controller, or the particular DIMM itself.
> Saves a lot of hassle, this simplification, it does


On my rev E I found a relation between RRD/FAW and RCDRD. At 3500 I could run RCDRD at 18 if RRD/FAW was 5/20 or higher. If I ran RRD/FAW at 4/16 I needed to up RCDRD to 19. No matter what volt I input this changed. On B-die I have not found such a relation yet.


----------



## Taraquin

So I tried WR/RTP 20/10 on my current 3800cl15 1t setting. It did lower voltage requirements by 0.02v from 1.47v, but ida became 0.4ns slower, lost 500Kb read/copy. I tried stabilizing cl14, but even at 1.54v it got 15 errors pr minute in TM5, 14-15-14 worked better, but still 4 errors a minute. For some who are on the edge of stability with current voltage using 2xSR 20/10 the small perf loss may be worth it. For those using DR or 4xSR the 20/10 it can definatly be worth it if perf improves a bit and voltage reqs sinks.


----------



## slayer1991

I was able to get these before finding Taraquin's signature post. I wonder how much more I can push these 3200c14 Bdies on a 3600x and C6H board?

PBO set at +200, high limits, tRFC2 and tRFC4 on Auto, the rest of the things manually adjusted.
Passed all y-cruncher stress test, and TestMem5 with cfgs: 1usmus_v3 and [email protected]
Temp never over 45*C on the DIMMs and 81.5*C max on CCD1 Tdie, no WHEA errors, no BSODs (had one before switching to manual voltages on VDDP and VDDG, and raising ProcODT).

I'm wondering if I should go forwards reading this forum, or backwards even if most new info is Zen 3 relevant?
Will go through Taraquin's guide next.

EDIT:
2nd Screenshot I have tightened down some timings, and have now gotten 4 errors over 20 cycles of usmus tests 10 and 13. Maybe I should just re-enable GDM? Or pump up some of the voltages?


----------



## Blackfyre

Found the most stable timings first (_running 60 cycles of 1usmus_) then decreased all the voltages:

*VSOC* was 1.150v to 1.110v
*CLDO VDDP* 1.080v to 0.94v
*VDDG CCD* 1.020v to 0.94v
*VDDG IOD* 1.050v to 0.98v
*1.8V PPL* from 1.92v to 1.79v


----------



## Taraquin

Blackfyre said:


> Found the most stable timings first (_running 60 cycles of 1usmus_) then decreased all the voltages:
> 
> *VSOC* was 1.150v to 1.110v
> *CLDO VDDP* 1.080v to 0.94v
> *VDDG CCD* 1.020v to 0.94v
> *VDDG IOD* 1.050v to 0.98v
> *1.8V PPL* from 1.92v to 1.79v
> View attachment 2566198


Very good result


----------



## Bloax

slayer1991 said:


> EDIT:
> 2nd Screenshot I have tightened down some timings, and have now gotten 4 errors over 20 cycles of usmus tests 10 and 13. Maybe I should just re-enable GDM? Or pump up some of the voltages?


Looks more like a case of lower RTP/tWR and vDIMM, lower RTP/tWR and procODT impedance, or just lower tWR and vDIMM, or maybe even lower tWR, vDIMM and procODT!

tRFC 288-214-132 might also be a hair more stable in things like y-cruncher?


----------



## Veii

Blackfyre said:


> Found the most stable timings first (_running 60 cycles of 1usmus_) then decreased all the voltages:
> 
> *VSOC* was 1.150v to 1.110v
> *CLDO VDDP* 1.080v to 0.94v
> *VDDG CCD* 1.020v to 0.94v
> *VDDG IOD* 1.050v to 0.98v
> *1.8V PPL* from 1.92v to 1.79v
> View attachment 2566198


Surely great signal integrity ~ congrats
Can you doublecheck , tRAS 42 , tRC 56
with your 40,54 

-2 works but potentially could be slightly too low
It looks very good


----------



## Taraquin

Blackfyre said:


> Found the most stable timings first (_running 60 cycles of 1usmus_) then decreased all the voltages:
> 
> *VSOC* was 1.150v to 1.110v
> *CLDO VDDP* 1.080v to 0.94v
> *VDDG CCD* 1.020v to 0.94v
> *VDDG IOD* 1.050v to 0.98v
> *1.8V PPL* from 1.92v to 1.79v
> View attachment 2566198


Fun fact: Your CPU performance is now significantly better in many scenarios than twice as expensive B-dies (like 3600cl14 2x16 DR) running xmp or sloppy tuning


----------



## Blackfyre

Taraquin said:


> Fun fact: Your CPU performance is now significantly better in many scenarios than twice as expensive B-dies (like 3600cl14 2x16 DR) running xmp or sloppy tuning


Thank you, what's interesting is today I got 2 grams of Thermal Grizzly *Kryonaut Extreme* and noticed my NH-D15 screws weren't at the correct pressure level. Not a problem in *temperatures* because the thermal spread when cleaning the older paste of *Kryonaut* (_non-extreme_) was already perfect. But the increased correct pressure seems to have made a difference in my lowest curve optimizer offsets I can now achieve. I am testing much lower offsets and they are working now. Not sure if pressure can affect that? So maybe RAM overclocking can improve too with the correct pressure on the CPU, but I will test it later. I need to focus first on making sure the CPU is 100% stable.

What's the best method or methods to test CPU stability (_Curve Optimizer stability_) that you guys use?


----------



## Taraquin

Blackfyre said:


> Thank you, what's interesting is today I got 2 grams of Thermal Grizzly *Kryonaut Extreme* and noticed my NH-D15 screws weren't at the correct pressure level. Not a problem in *temperatures* because the thermal spread when cleaning the older paste of *Kryonaut* (_non-extreme_) was already perfect. But the increased correct pressure seems to have made a difference in my lowest curve optimizer offsets I can now achieve. I am testing much lower offsets and they are working now. Not sure if pressure can affect that? So maybe RAM overclocking can improve too with the correct pressure on the CPU, but I will test it later. I need to focus first on making sure the CPU is 100% stable.
> 
> What's the best method or methods to test CPU stability (_Curve Optimizer stability_) that you guys use?


Little chance of making ram run more stable with better cooling on CPU. You have very good timings for rev E already. 

I prefer Core cycler for testing CO stability.


----------



## Valka814

Installed Win 11 today and its a blue screen fest. Its looks as a memory issue so far.
Is this possible? I mean to have stable settings for Win 10, but very unstable for Win 11.


----------



## Bix

Bloax said:


> Funny observation: Doubling the minimum stable RTP/tWR seems to have worked on two (technically, three) different sets of memeory.
> Doing so raises the temperature resistance of the memory - originally did it for someone who was using dual-rank bdie sticks in an ITX hot-box case, 60+ C on just the chips during use  - with a minimal performance hit --
> on my wacky z690 4x8 config (featuring sticks that "Demand" RTP 5/10) RTP 10/20 _actually performs better_ than 5/10 and is also stable unlike 6/12 7/14 or 8/16
> 
> Might not be a good idea on single-rank setups, where doubling the duration of the background tWR/RTP processes may actually impact how many groups are available to access - but on dual-rank .. I should test my "thoroughly CURSED" dual-rank kit that throws temperature errors at 35 C again...


Interesting! Didn't help for my 4x viper 4400 setup sadly - average across three runs of y-cruncher 2.5b went up from 72.235 at 5/10 to 72.630 at 10/20 (with a 4.4 static CPU OC).










Any suggestions as to what else I could improve here? Was able to lower ProcODT to 28.2 by raising PLL(or whatever it's called) to 1.86 thanks to your advice which has really helped with the secondary timings 

RAM is stuck behind a NH-D15 so I'm thermally quite limited and MSI funkiness means that CL14 flat out refuses to train at tPHYRDL 26 so it didn't seem worth the extra voltage needed to lower the primaries any further.


----------



## Bloax

EDIT: oh right, and RRDL 6 might perform better than RRDL 4 - funnily enough


Bix said:


> Interesting! Didn't help for my 4x viper 4400 setup sadly - average across three runs of y-cruncher 2.5b went up from 72.235 at 5/10 to 72.630 at 10/20 (with a 4.4 static CPU OC).
> 
> View attachment 2566212
> 
> 
> Any suggestions as to what else I could improve here? Was able to lower ProcODT to 28.2 by raising PLL(or whatever it's called) to 1.86 thanks to your advice which has really helped with the secondary timings
> 
> RAM is stuck behind a NH-D15 so I'm thermally quite limited and MSI funkiness means that CL14 flat out refuses to train at tPHYRDL 26 so it didn't seem worth the extra voltage needed to lower the primaries any further.


Well, voltage is only so much a concern as it causes thermal issues - which doubling RTP/tWR happens to help with, if the sticks aren't already indestructible, hehe 🤡
as for PHYRDL 26 --








Are the b550 Unify boards truly borked in this regard compared to the x570 Unify boards, or is this a VDDP-too-low + CADBus (CsOdtDrvStr, in particular) issue?
As it's 0.86vddp & 30 Ohm on this screenshot, vs. 0.8vddp & 24 Ohm in yours. (CsOdtDrv below 30 supposedly causes training issues at low procODT impedances??)

Seems like you may or may not have RDWR and WRRD headroom based on that screenie. Whether it performs better, well ....


I'm also curious if RCDWR = RCDRD on its lonesome - without any of these other suggested changes - has any impact on RTP 10/20 performance.  

Oh right, and I'm also _really_ curious if there's a CADBus combo that works with AddrCmdSetup 0 while running RTP 10/20 - as _that's essentially the case on this z690 board_.


----------



## Bix

Bloax said:


> Well, voltage is only so much a concern as it causes thermal issues - which doubling RTP/tWR happens to help with, if the sticks aren't already indestructible, hehe 🤡
> as for PHYRDL 26 --
> View attachment 2566213
> 
> Are the b550 Unify boards truly borked in this regard compared to the x570 Unify boards, or is this a VDDP-too-low + CADBus (CsOdtDrvStr, in particular) issue?
> As it's 0.86vddp & 30 Ohm on this screenshot, vs. 0.8vddp & 24 Ohm in yours. (CsOdtDrv below 30 supposedly causes training issues at low procODT impedances??)
> 
> Seems like you may or may not have RDWR and WRRD headroom based on that screenie. Whether it performs better, well ....
> 
> 
> I'm also curious if RCDWR = RCDRD on its lonesome - without any of these other suggested changes - has any impact on RTP 10/20 performance.
> 
> Oh right, and I'm also _really_ curious if there's a CADBus combo that works with AddrCmdSetup 0 while running RTP 10/20 - as _that's essentially the case on this z690 board_.


For some reason known only to MSI the b550 unify only seems to train PHYRDL to 26 at odd CLs...










Same profile as before only with flat 16 primaries
@Audioboxer has some experience with this too I think.

Just checked RCDWR = RCDRD with RTP/WR 10/20 and was slower (73.086).

I've been leaving RDWR and WRRD on auto but just realised it's training RDWR differently on each channel (10 on A / 9 on B) ((and 11 on A / 10 on B when I changed to flat 16s)). I'm assuming this is bad. Will try bringing them down a bit.

Haven't touched the CADBus at all as it's seemed happy on auto so far. I did try AddrCmdSetup 0 with RTP/WR 10/20 and was quite impressed with how long I lasted in windows compared to previous attempts! I managed some fairly erratic AIDA latency tests but TM5 made everything go boom in about a second. Any ideas what I could try?


----------



## Bloax

Bix said:


> I did try AddrCmdSetup 0 with RTP/WR 10/20 and was quite impressed with how long I lasted in windows compared to previous attempts! I managed some fairly erratic AIDA latency tests but TM5 made everything go boom in about a second. Any ideas what I could try?


Well, in all likelyhood you're going to be at ClkDrvStr 40 as an embarassing amount of b-die DIMMs like that value.


CsOdtDrvStr is also likely to either be 30 or 40

So that leaves trying AddrCmdDrvStr 24, 30 and 40 alongside CkeDrvStr 20, 24, 30 and 40, at both CsOdtDrvStr 30 as well as 40.
That's.. 18 combinations? Not too horrendous, seeing that all but one or two of them should be very explosive.









so don't forget the safemode 🤭


----------



## Blameless

Trying to get tRC as low as possible in high temp scenarios:









1.48 vDIMM and 1.73v CPU 1.8. Room is 35C, ICs are peaking around 70C.

Anything below tRC 39 hits a temperature wall at about 60C and starts spewing errors in every single TM5 test, but 39 is very solid. Best combination to get there on this kit with tRTP 5/tWR 10 is with low tRAS and flat tRP. tRTP 10/tWR 20 mandates a higher tRAS or I get some performance and stability weirdness, but it does allow me to use a bit lower on tRP. Still, since I don't see any real temperature limits at tRC 39 and the lower tRTP makes that tRC more usable, I'll probably stay at 5.

Finished TM5 a bit ago, running y-cruncher again now.

Edit: Ten passes of y-cruncher, so far...


----------



## Bix

Bloax said:


> Well, in all likelyhood you're going to be at ClkDrvStr 40 as an embarassing amount of b-die DIMMs like that value.
> 
> 
> CsOdtDrvStr is also likely to either be 30 or 40
> 
> So that leaves trying AddrCmdDrvStr 24, 30 and 40 alongside CkeDrvStr 20, 24, 30 and 40, at both CsOdtDrvStr 30 as well as 40.
> That's.. 18 combinations? Not too horrendous, seeing that all but one or two of them should be very explosive.
> 
> View attachment 2566217
> 
> so don't forget the safemode 🤭


That's really useful, thanks - 18 combinations is a lot less painful than I was expecting😀


----------



## Taraquin

Bix said:


> Interesting! Didn't help for my 4x viper 4400 setup sadly - average across three runs of y-cruncher 2.5b went up from 72.235 at 5/10 to 72.630 at 10/20 (with a 4.4 static CPU OC).
> 
> View attachment 2566212
> 
> 
> Any suggestions as to what else I could improve here? Was able to lower ProcODT to 28.2 by raising PLL(or whatever it's called) to 1.86 thanks to your advice which has really helped with the secondary timings
> 
> RAM is stuck behind a NH-D15 so I'm thermally quite limited and MSI funkiness means that CL14 flat out refuses to train at tPHYRDL 26 so it didn't seem worth the extra voltage needed to lower the primaries any further.


My ram is also stuck behind a D15  You could try a bit higher voltage (1.49v seems to be the thermal limit on my setup) and RCDRD 14, RP 14, slightly lower RFC (250-260), maybe 9 or 8 RDWR, 3 or 1 on WRRD. Also lowering RAS and subsequently RC may be a bit faster.


----------



## Bix

Taraquin said:


> My ram is also stuck behind a D15  You could try a bit higher voltage (1.49v seems to be the thermal limit on my setup) and RCDRD 14, RP 14, slightly lower RFC (250-260), maybe 9 or 8 RDWR, 3 or 1 on WRRD. Also lowering RAS and subsequently RC may be a bit faster.


Thanks for the suggestions - will try once I'm finished playing CADBus minesweeper!

It might be possible to funnel air from a single small top intake fan down between the DIMMs for a bit more temperature headroom. There's not much space though so would probably mean trial and a lot of error with a 3d printer to get it just right! I've previously been topping out around the 1.49v mark too.


----------



## Audioboxer

Bix said:


> For some reason known only to MSI the b550 unify only seems to train PHYRDL to 26 at odd CLs...
> 
> View attachment 2566215
> 
> 
> Same profile as before only with flat 16 primaries
> @Audioboxer has some experience with this too I think.
> 
> Just checked RCDWR = RCDRD with RTP/WR 10/20 and was slower (73.086).
> 
> I've been leaving RDWR and WRRD on auto but just realised it's training RDWR differently on each channel (10 on A / 9 on B) ((and 11 on A / 10 on B when I changed to flat 16s)). I'm assuming this is bad. Will try bringing them down a bit.
> 
> Haven't touched the CADBus at all as it's seemed happy on auto so far. I did try AddrCmdSetup 0 with RTP/WR 10/20 and was quite impressed with how long I lasted in windows compared to previous attempts! I managed some fairly erratic AIDA latency tests but TM5 made everything go boom in about a second. Any ideas what I could try?


Yes, there is something stupid going on with B550 MSI boards and tPHYRDL.

If you run an even tCL at 3800 it's going to train 26/28 (28/28 possibly with some messing around) unless you run at 2T. 3800 tCL14 will do 26/26 at 2T.

In order to train 26/26 at 1T need an uneven tCL (13/15).

Absolutely nothing changes this behaviour other than running stupid powering settings which may cause things like 26/30 or 28/30 or so on. IIRC I've seen 32 once as well.


----------



## Bix

Bloax said:


> So that leaves trying AddrCmdDrvStr 24, 30 and 40 alongside CkeDrvStr 20, 24, 30 and 40, at both CsOdtDrvStr 30 as well as 40.
> That's.. 18 combinations? Not too horrendous, seeing that all but one or two of them should be very explosive.


Progress so far... 

AddrCmdDrvStr 40 is a definite no I think (either doesn't post at all or bluescreens while loading windows).

All of the other combinations with AddrCmdDrvStr 24 or 30 will get me into windows and allow multiple AIDA latency tests (all with similar results) but I'm finding it impossible to differentiate between them since TM5 crashes within 0-10 seconds after spewing a ton of 0s, 6s and/or 12s with all of them. Any suggestions gratefully received!


----------



## Blackfyre

I still do not fully understand *ProcODT* and *drive strengths* (_ClkDrvStr, AddrCmdDrvStr, CsOdtDrvStr and CkeDrvStr_). And *RTT values* (_RttWr, RttPark, and RttNom_).

*From my understanding* they are impedance related. Which means the lowest you can go on each one, the lower the voltage that is required to run smoothly. And therefore, the lowest heat produced, correct? Since there is less resistance = less voltage = less heat.

This is why when I realised this, I set them all to the lowest possible impedance.








Then you read from a lot of people and guides that all these values greatly impact over-clocking. But I do not understand how or why increasing impedance can assist and in what way. I've always achieved my best results on the lowest impedance (_which I know not many people can always run_).


----------



## MrHoof

Blackfyre said:


> I still do not fully understand *ProcODT* and *drive strengths* (_ClkDrvStr, AddrCmdDrvStr, CsOdtDrvStr and CkeDrvStr_). And *RTT values* (_RttWr, RttPark, and RttNom_).
> 
> *From my understanding* they are impedance related. Which means the lowest you can go on each one, the lower the voltage that is required to run smoothly. And therefore, the lowest heat produced, correct? Since there is less resistance = less voltage = less heat.
> 
> This is why when I realised this, I set them all to the lowest possible impedance.
> View attachment 2566279
> 
> Then you read from a lot of people and guides that all these values greatly impact over-clocking. But I do not understand how or why increasing impedance can assist and in what way. I've always achieved my best results on the lowest impedance (_which I know not many people can always run_).


 (_which I know not many people can always run_). 
Only VIII hero and dark hero owners with 4 sticks SR or 2 DR, atleast I did not see screenshots of other boards yet. On 2 SR my asus x570-i could run them also at all 20 but not with DR sticks. I need for those 40/20/24/30 on my 5800x and 40/20/30/30 on my 5800x3d.


----------



## Audioboxer

Blackfyre said:


> I still do not fully understand *ProcODT* and *drive strengths* (_ClkDrvStr, AddrCmdDrvStr, CsOdtDrvStr and CkeDrvStr_). And *RTT values* (_RttWr, RttPark, and RttNom_).
> 
> *From my understanding* they are impedance related. Which means the lowest you can go on each one, the lower the voltage that is required to run smoothly. And therefore, the lowest heat produced, correct? Since there is less resistance = less voltage = less heat.
> 
> This is why when I realised this, I set them all to the lowest possible impedance.
> View attachment 2566279
> 
> Then you read from a lot of people and guides that all these values greatly impact over-clocking. But I do not understand how or why increasing impedance can assist and in what way. I've always achieved my best results on the lowest impedance (_which I know not many people can always run_).


I guess you could technically view it as "just run as low as you can go", but inherently thinking a resistance _has_ to be low to be good/perform better would be the wrong way to think about from what I've learned.

They also aid in helping power the DIMMs, so that, I believe, is related to signal integrity. For example, good luck running ClkDrvStr at 20 if you're trying to push 3800/1T with DR. Nearly everyone ends up running 40, I've seen 30 OK a few times.

The Rtts are sometimes what cause NO POST when they are simply set at something that does not work with your combination of frequency and timings. Other times, they'll post but can either fail TM5 or cause other issues.










That's my daily. I can run RttPark at 5, boots fine and I let it do an hour of TM5 and it was fine, but, reason I stopped TM5 is because tPHYRDL trains at 26/30 instead of 26/26. So, 4 is as weak as I could go and not impact performance. But 5 boots, IIRC 6 might as well, but 7 definitely doesn't.

That is, 7 doesn't boot when RttWr is at 3. I need to make RttWr stronger (1) to boot RttPark 7. You see, they often influence each other. The real end game of memory tuning, the timings are ez-mode compared to the resistances lol. More so if you're pushing really high frequency on DDR4, or if you're looking at DR with 1T.


----------



## Bloax

Audioboxer said:


> The Rtts are sometimes what cause NO POST when they are simply set at something that does not work with your combination of frequency and timings. Other times, they'll post but can either fail TM5 or cause other issues.
> 
> That is, 7 doesn't boot when RttWr is at 3. I need to make RttWr stronger (1) to boot RttPark 7. You see, they often influence each other. The real end game of memory tuning, the timings are ez-mode compared to the resistances lol. More so if you're pushing really high frequency on DDR4, or if you're looking at DR with 1T.


RTT "viability" is most noticeable in terms of frequency - only the "best-performing" combos can run ~4000 MT/s single-rank, and ~3800-4000 dual-rank, even at very easy primary timings.
To further sort them out, you can go even higher on the frequency, and test the survivors for who comes out Last Man Standing.

And yes, there is inter-play between things like what Park impedance can be run depending on Nom and Wr impedance, and I would just like to remind not to run high Wr impedances (/2, /1) with high Park impedances (/2, /1) unless you want to fry your DIMMs. 
Wr/2 can be more tolerant of high temperature, but also more likely to cause issues at high voltage.
Even more true of Wr/1, though this one can start causing more temperature problems of its own.








don't be this guy, hehehe, that's called Living Dangerously : ))))
at least the sticks survived and led a peaceful life since

so peaceful that I'm actually selling that processor and memory kit with a convenient motherboard to contain them, at ruinous prices, because I'm tired of seeing them Do Nothing


----------



## Blackfyre

Audioboxer said:


> For example, good luck running ClkDrvStr at 20 if you're trying to push 3800/1T with DR. Nearly everyone ends up running 40, I've seen 30 OK a few times.


I am doing that, but you're saying the only reason I can run this with a 5800X and 4 sticks, is because they are single rank instead of dual rank?

But aren't 4 sticks of single-rank the best in terms of performance and hardest to stabilise? And isn't 4 x SR the same as 2 x DR?


----------



## Bloax

Different PCBs can/want to run different kind of terminations :--DD
Ballistix PCBs are famous(?) for their ability to do very silly things (such as running Park Disabled) without immediate issues.


Bix said:


> Progress so far...
> 
> AddrCmdDrvStr 40 is a definite no I think (either doesn't post at all or bluescreens while loading windows).
> 
> All of the other combinations with AddrCmdDrvStr 24 or 30 will get me into windows and allow multiple AIDA latency tests (all with similar results) but I'm finding it impossible to differentiate between them since TM5 crashes within 0-10 seconds after spewing a ton of 0s, 6s and/or 12s with all of them. Any suggestions gratefully received!


Well, if no delays don't want to work - you can always try the "old" delay strategy of CAD Setup 3-3-15 (+/- 1-1-3 at the same rate as tCKE goes up/down by 2), which are mild delays compared to 56-0-0.

****loads of 0's and 6's can also just mean the voltage requirements went down, and now they're being very angry, but unlikely.


----------



## Audioboxer

Blackfyre said:


> I am doing that, but you're saying the only reason I can run this with a 5800X and 4 sticks, is because they are single rank instead of dual rank?
> 
> But aren't 4 sticks of single-rank the best in terms of performance and hardest to stabilise? And isn't 4 x SR the same as 2 x DR?
> View attachment 2566288


My knowledge of anything other than b-die is very poor, as it is with SR. I have done all my learning with b-die and DR.

Though, along the way I've learned some things about how SR is different. But yes, doing 1T both without setup timing and with ClkDrvStr is basically SR only. Especially at 3800.

You're doing well with 4 sticks, that's usually harder than 2xSR.



> And isn't 4 x SR the same as 2 x DR?


No lol. Other than possibly being the same memory capacity. As in, 4x8 or 2x16 = 32GB.


----------



## Blameless

Blackfyre said:


> And isn't 4 x SR the same as 2 x DR?


In terms of performance at the same clock and timings, yes. However, it's still quite different in what's required to stabilize it. It's the same number of channels and ranks, but the physical topology is very different.


----------



## The_King

Blameless said:


> In terms of performance at the same clock and timings, yes. However, it's still quite different in what's required to stabilize it. It's the same number of channels and ranks, but the physical topology is very different.


This is correct. At the same frequency and timings 4XSR should be very close or almost identical to 2XDR in terms of performance.
You get the benefit of DR on both setups with ZEN 3.

The only advantage of 2XDR DIMMs is that a much higher OC maybe possible with 2 Dimms than what you may get with 4 DIMMS.
With 2XDR you could get 4000MT/s to run stable and 4XSR you could be limited to 3800 for example.

Although REV.E is much easier on the IMC compared to Samsung B-die. I will need to check what my REV. E kits can do 4XSR. My Samsung B-die Kit only goes to 3867 MT/s 4XSR.

If we talking about ZEN 3 benefiting from DR rank setup then 4XSR does the job.


----------



## Audioboxer

Highest I got with my DR was 4600










It was super hairy though, often didn't want to post.










4533 I got consistently posting, but outside of having some fun with it, running out of sync just wasn't worth it other than seeing sexy benchmarks for read/copy/write.

The latency penalty is just too much.

I reckon you need to get to 4600+ in order to run out of sync and see latency the SAME as 3800/1900. And as latency is still king in-game, it's the best thing to focus on, on AMD.

I might try visiting my adventures above again now that we're a few AGESA versions on, but AGESA for quite a while hasn't really done anything for memory. Just AMD fixing stupid bugs and... making new bugs.

But yeah, resistances, tCKE and more becomes all sorts of "fun" when you start trying to push high frequencies on DR. If you so much as sneeze you can go from posting to not posting. So, the saddest thing to end this gen is more-so AMD never got 4000/2000 working. DDR4 at 4000 and even above, became incredibly easy to run. AMD just couldn't do it with AM4 on the high performance chips.


----------



## Bloax

If they actually wanted to make a desktop videogaming dominator chip, they would employ Cezanne (which regularly does >2200 FCLK) with stacked cache - not Vermeer.
But Vermeer-3D simply utilizes the same core chiplets ("CCD"s) as go into Milan-X, so that's what you get.

You'll pay out the nose for the privilege too, hahaha


----------



## Audioboxer

Bloax said:


> If they actually wanted to make a desktop videogaming dominator chip, they would employ Cezanne (which regularly does >2200 FCLK) with stacked cache - not Vermeer.
> But Vermeer-3D simply utilizes the same core chiplets ("CCD"s) as go into Milan-X, so that's what you get.
> 
> You'll pay out the nose for the privilege too, hahaha


If we look at some of Veii's findings it's also possible if AMD cared enough, they could have sorted out or at least looked at some of the WHEA spam above 1900. AGESA still seems all sorts of janky, like it's duct taped together.

The USB issues, in general, plagued AMD forever and even to this day I'm still not convinced AMD ever fully fixed them.


----------



## Bloax

The only remaining thing to do, is pray that AM5 will be less of a stapled-together mess than AM4 coming fresh off Bullsnoozer & Piledriver was.

That DESKTOP USERS are the red-headed stepchildren of AMD despite being the ones who kept them relevant, well, whatever.
sucky sucky quarter report go up up

desktop users? who are they


----------



## Bix

Bloax said:


> Well, in all likelyhood you're going to be at ClkDrvStr 40 as an embarassing amount of b-die


ClkDrvStr 120 seems to be the only one that allows TM5 to run for me without setup timings. No bluescreens or crashes yet. The best I've managed so far is 16 errors in the first cycle so still miles away from stable but at least I've got my foot in the door🙂

I'm assuming that needing ClkDrvStr that high means something's not right with my powering elsewhere...


----------



## Blameless

In general, I use the highest output impedance (which is a weaker drive strength, not stronger) and lowest termination resistance that is stable, as this usually results in the coolest running memory, other things being equal...and my daily systems tend to run warm.


----------



## Bloax

Bix said:


> ClkDrvStr 120 seems to be the only one that allows TM5 to run for me without setup timings. No bluescreens or crashes yet. The best I've managed so far is 16 errors in the first cycle so still miles away from stable but at least I've got my foot in the door🙂
> 
> I'm assuming that needing ClkDrvStr that high means something's not right with my powering elsewhere...


Hoho, that's cool!

Might be suggesting that it wants Wr/2 and ClkDrvStr 60 or someshit, but that's certainly better than insta-crashing!


----------



## va8888

Hey guys, I just got some Asgard 3600Mhz CL 18 RAM that have chips manufactured by ChangXin.

Its 3600Mhz XMP profile goes by 18-22-22-42 1.35V, but it's quite sluggish.

Right now I'm going 16-19-18-36 1.37V and everything else in auto. Here's AIDA's benchmark:







Seems to be stable.

I'm wondering how far I can push it, but since it's a lesser now chip manufacturer, I'd love to see what you've guys been able to do with these.

Taiphoon: Module Manufacturer: Asgard Module Part Number: VMA47UG-MEC1U22T3 Module Ser - Pastebin.com

Previously I was using Corsair Vengeance CL 16 2400Mhz @ CL 14-20-14-34 3200 Mhz, and my benchmark results were just a tad bit slower than these 3600Mhz @ CL 16.
On that note, though, I'm a bit confused by the fact that DRAM Calc's benchmark for this older RAM say they're faster than these new units I got. Here's a screenshot of two benchmarks: 

Asgard 3600Mhz basic OC:









Corsair [email protected] with detailed OC:









AIDA64 however says my current OC on Asgard is faster in almost everything, except some L Caches. I don't know which benchmark to trust on this one.


----------



## Baio73

For users who helpded me with my problem of TM5 executing forever (@KedarWolf - @Audioboxer - @Veii - @The_King - @mnathani98): @ReyReverse was right and my Windows11 installation was ****ed up.
Finally found sometime to make a fresh installation and TM5 ended its 25 cycles:



Can someone please advice me on how to further tweak my RAM?
Voltage is 1.53v from BIOS, my goal is to keep CAS14 GDM OFF @3800... some less temperature would be welcomed!
Thanks anyway!

Baio


----------



## Ramad

Audioboxer said:


> The USB issues, in general, plagued AMD forever and even to this day I'm still not convinced AMD ever fully fixed them.


The USB disconnecting issues can be solved by raising chipset/south bridge voltage from 1.00V to 1.1V. AMD lowered this voltage because the chipset runs hot. I know that some motherboard has this voltage described as "Chipset 1.1V" but has it set to 1.00V by default. 

Other than that, an unstable overclock can give the user all sorts of issues which includes USB issues.


----------



## Bloax

You say "overclock", but there are plenty of boards which run 1.1v SOC/IOD/CCD/VDDP by default even on what is an "officially supported" DDR4-3200 config.

Doing so causes lots of unnecessary fabric hiccups, if not downright dropouts.


----------



## Blackfyre

Ramad said:


> The USB disconnecting issues can be solved by raising chipset/south bridge voltage from 1.00V to 1.1V. AMD lowered this voltage because the chipset runs hot. I know that some motherboard has this voltage described as "Chipset 1.1V" but has it set to 1.00V by default.
> 
> Other than that, an unstable overclock can give the user all sorts of issues which includes USB issues.


I could kiss you right now lol

The chipset fan has been driving me insane. I have a silent build, and at least when I am just watching YouTube or working, I don't want to hear the PC at all.

I just dropped *SB v1.0* down to *0.7v* instead of increasing it and it dropped my chipset temperature from 59°C to 49°C on my X570 HERO (Wi-Fi).

Not having any USB issues either, yet. So, fingers crossed it works.

In the BIOS it says minimum 0.7v, is it safe to drop it below that? To *0.5v* for example, to test.
*EDIT:* Can't set *SB v1.0* lower than *0.7v*


----------



## The_King

Baio73 said:


> For users who helpded me with my problem of TM5 executing forever (@KedarWolf - @Audioboxer - @Veii - @The_King - @mnathani98): @ReyReverse was right and my Windows11 installation was ****ed up.
> Finally found sometime to make a fresh installation and TM5 ended its 25 cycles:
> 
> 
> 
> Can someone please advice me on how to further tweak my RAM?
> Voltage is 1.53v from BIOS, my goal is to keep CAS14 GDM OFF @3800... some less temperature would be welcomed!
> Thanks anyway!
> 
> Baio


GMD off 1T stable is great without using Cmd 56.

I dont run very long tests like you or others on here but 3800-14-15-15-15-30-45 with the same voltage may work.
You may need to change your tRFC. You can use Veii tRFC mini to adjust that.

You can try TWR 20 RTP 10 that may or may not improve temps or heat tolerants. Only way to find out is to test it. 
For better performance TWR 10 RTP 5 should be faster. Also try 12/6 or 12/8









tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com





Edit: Useful commands to prevent / fix Data corruption. Run it from time to time from command prompt with ADMIN rights.
SFC /scannow

DISM /Online /Cleanup-Image /CheckHealth
DISM /Online /Cleanup-Image /ScanHealth
DISM /Online /Cleanup-Image /RestoreHealth


----------



## Blackfyre

Blackfyre said:


> Found the most stable timings first (_running 60 cycles of 1usmus_) then decreased all the voltages:
> 
> *VSOC* was 1.150v to 1.110v
> *CLDO VDDP* 1.080v to 0.94v
> *VDDG CCD* 1.020v to 0.94v
> *VDDG IOD* 1.050v to 0.98v
> *1.8V PPL* from 1.92v to 1.79v
> View attachment 2566198


*Decreased voltages even further:*

*VSOC* was 1.150v to 1.110v to 1.093v
*CLDO VDDP* 1.080v to 0.94v to 0.90v
*VDDG CCD* 1.020v to 0.94v to 0.90v
*VDDG IOD* 1.050v to 0.98v to 0.94v
*1.8V PPL* from 1.92v to 1.79v to 1.78v


Blackfyre said:


> I could kiss you right now lol
> 
> The chipset fan has been driving me insane. I have a silent build, and at least when I am just watching YouTube or working, I don't want to hear the PC at all.
> 
> I just dropped *SB v1.0* down to *0.7v* instead of increasing it and it dropped my chipset temperature from 59°C to 49°C on my X570 HERO (Wi-Fi).
> 
> Not having any USB issues either, yet. So, fingers crossed it works.
> 
> In the BIOS it says minimum 0.7v, is it safe to drop it below that? To *0.5v* for example, to test.
> *EDIT:* Can't set *SB v1.0* lower than *0.7v*


Decreased main voltages above and *SB v1.0* down to *0.7v* --> Ran TM5 *1usmus_v3* set to 60 cycles:

*1 WHEA *error that was not picked up by TM5, but picked up by HWiNFO --> I suspect it's *VDDG IOD* down to *0.94v*


----------



## Melan

How do I know if ProcODT is too low? If I set auto then mobo slams 60 ohm (for 2T CMD, for GDM and 1T it sets 36.9). I've been using 36.9 because it kinda worked (?) as in didn't give any errors. But now I've set 28.2 ohm and did the usual round of furmark roasting + tm5 universal1 and then some 1usmus_v3 and it still didn't error. I've been mostly following hardwareluxx ryzen ram oc thread op with this.

Edit: 5 iterations of y-cruncher (FFT, N64, HNT, VST, C17) also had no issues and 0 on bean whea counter.


----------



## Blackfyre

Melan said:


> How do I know if ProcODT is too low? If I set auto then mobo slams 60 ohm (for 2T CMD, for GDM and 1T it sets 36.9). I've been using 36.9 because it kinda worked (?) as in didn't give any errors. But now I've set 28.2 ohm and did the usual round of furmark roasting + tm5 universal1 and then some 1usmus_v3 and it still didn't error. I've been mostly following hardwareluxx ryzen ram oc thread op with this.
> 
> Edit: 5 iterations of y-cruncher (FFT, N64, HNT, VST, C17) also had no issues and 0 on bean whea counter.


Personally, I don't think there's too low, I run all resistance factors on the lowest resistance *possible*. If you can, keep it on lowest as that produces the least heat from my understanding, so it's better.

I'd wait for someone more experienced to comment on it, but I run all of these on lowest possible values. Works great for me.


----------



## Taraquin

va8888 said:


> Hey guys, I just got some Asgard 3600Mhz CL 18 RAM that have chips manufactured by ChangXin.
> 
> Its 3600Mhz XMP profile goes by 18-22-22-42 1.35V, but it's quite sluggish.
> 
> Right now I'm going 16-19-18-36 1.37V and everything else in auto. Here's AIDA's benchmark:
> View attachment 2566386​
> Seems to be stable.
> 
> I'm wondering how far I can push it, but since it's a lesser now chip manufacturer, I'd love to see what you've guys been able to do with these.
> 
> Taiphoon: Module Manufacturer: Asgard Module Part Number: VMA47UG-MEC1U22T3 Module Ser - Pastebin.com
> 
> Previously I was using Corsair Vengeance CL 16 2400Mhz @ CL 14-20-14-34 3200 Mhz, and my benchmark results were just a tad bit slower than these 3600Mhz @ CL 16.
> On that note, though, I'm a bit confused by the fact that DRAM Calc's benchmark for this older RAM say they're faster than these new units I got. Here's a screenshot of two benchmarks:
> 
> Asgard 3600Mhz basic OC:
> View attachment 2566387
> 
> 
> Corsair [email protected] with detailed OC:
> View attachment 2566388
> 
> 
> AIDA64 however says my current OC on Asgard is faster in almost everything, except some L Caches. I don't know which benchmark to trust on this one.


Secondaries are very lax on the Asgard. Some benches are sensitive to slow RRD/FAW, WR etc. Try tightening up the 3600 kit. RRDS/L/FAW 6/8/16 and WR/RTP 16/8 should be doable. Try setting RAS to 40 and RC to 58, RFC may fo 600 or lower.


----------



## Taraquin

Audioboxer said:


> Highest I got with my DR was 4600
> 
> View attachment 2566343
> 
> 
> It was super hairy though, often didn't want to post.
> 
> View attachment 2566344
> 
> 
> 4533 I got consistently posting, but outside of having some fun with it, running out of sync just wasn't worth it other than seeing sexy benchmarks for read/copy/write.
> 
> The latency penalty is just too much.
> 
> I reckon you need to get to 4600+ in order to run out of sync and see latency the SAME as 3800/1900. And as latency is still king in-game, it's the best thing to focus on, on AMD.
> 
> I might try visiting my adventures above again now that we're a few AGESA versions on, but AGESA for quite a while hasn't really done anything for memory. Just AMD fixing stupid bugs and... making new bugs.
> 
> But yeah, resistances, tCKE and more becomes all sorts of "fun" when you start trying to push high frequencies on DR. If you so much as sneeze you can go from posting to not posting. So, the saddest thing to end this gen is more-so AMD never got 4000/2000 working. DDR4 at 4000 and even above, became incredibly easy to run. AMD just couldn't do it with AM4 on the high performance chips.


The more basic your setup is (single CCD, basic MB layout), usually the better ram OC you get, complete opposite if Intel (except 2 dimms rock on both). Most of the setups running 4000/2000+ without issues has single CCDs, run on ITX or mATX 2 dimms. Still running 2000+ fclk problemfree doesn't equate good scaling. 3800cl15 and 4000cl16 tuned gives med equal perf in Y-cruncher and Linpack, but 4000 is 2% faster in SOTTR, Dram calc test and some other benches. Up till 3800 I get good scaling in Y-cruncher and Linpack aswell. However I must raise SOC by 50mv, IOD by 60mv and VDD18 by 80mv to achieve 2000 fclk, this which raises temps and eats from the powerbudget som unless I raise PPT, Cinebench and other renderingtasks loses 1-2% performance.


----------



## Taraquin

Blackfyre said:


> *Decreased voltages even further:*
> 
> *VSOC* was 1.150v to 1.110v to 1.093v
> *CLDO VDDP* 1.080v to 0.94v to 0.90v
> *VDDG CCD* 1.020v to 0.94v to 0.90v
> *VDDG IOD* 1.050v to 0.98v to 0.94v
> *1.8V PPL* from 1.92v to 1.79v to 1.78v
> 
> Decreased main voltages above and *SB v1.0* down to *0.7v* --> Ran TM5 *1usmus_v3* set to 60 cycles:
> 
> *1 WHEA *error that was not picked up by TM5, but picked up by HWiNFO --> I suspect it's *VDDG IOD* down to *0.94v*
> View attachment 2566454
> 
> View attachment 2566455


You can probably lower CCD and VDDP even more. I run mine at 820mv atm, works fine. Below 800mv I get no post, but performance is the same on 820mv as 1000mv on both, but the latter uses a bit more power.


----------



## ccxmonster

Hı people, i am currently using these timings for my ram kit;









my ram kit is stable under these settings but im still wondering if im using the correct tCKE & Setup Timings
i saw these settings on web for 3800MHz and applied them, is there more compliant timing of these things for 3733MHz speed ? or these are all good and should i not change ?

thanks.


----------



## va8888

Taraquin said:


> Secondaries are very lax on the Asgard. Some benches are sensitive to slow RRD/FAW, WR etc. Try tightening up the 3600 kit. RRDS/L/FAW 6/8/16 and WR/RTP 16/8 should be doable. Try setting RAS to 40 and RC to 58, RFC may fo 600 or lower.


Hey there, will do. I'll fiddle with the secondaries to see what happens.

I tried some stuff with this RAM, but it's not very easy to work with:

*Speed*: 3666 Mhz, 3733Mhz and 3800Mhz give errors on the tests at 16-20-18-36, so relaxing more than this wouldn't be worth it I think. 3666Mhz also desyncs with UCLK, increasing latency.
*tCL*: Tried 15-20-18-36 with GDM off, but errors pop up. I guess I'm stuck with tCL 16 for the best scenario.
*tRCDR: *At 3600Mhz, I can't seem to boot/post/pass tests with less than tRCDR 19.
*tRFC*: below 600 and got some Windows freezes, though benchmarks and HWMonitor didn't detect errors or WHEAs. These freezes are probably related to tighter tRFC right?

So, I noticed that the manufacturer also goes by the name of CXMT (ChangXin Memory Technologies). Also, I've read on some reddit wiki that CXMT tends to be close to Hynix CJR behaviour. What do you guys think? If that's the case, what else should I try on these RAM sticks?

For now I guess I'll focus on secondary timings, but I'd love to get more juice out of these.

Right now I'm running this which seem to be stable @ 1.38V:


----------



## Taraquin

va8888 said:


> Hey there, will do. I'll fiddle with the secondaries to see what happens.
> 
> I tried some stuff with this RAM, but it's not very easy to work with:
> 
> *Speed*: 3666 Mhz, 3733Mhz and 3800Mhz give errors on the tests at 16-20-18-36, so relaxing more than this wouldn't be worth it I think. 3666Mhz also desyncs with UCLK, increasing latency.
> *tCL*: Tried 15-20-18-36 with GDM off, but errors pop up. I guess I'm stuck with tCL 16 for the best scenario.
> *tRCDR: *At 3600Mhz, I can't seem to boot/post/pass tests with less than tRCDR 19.
> *tRFC*: below 600 and got some Windows freezes, though benchmarks and HWMonitor didn't detect errors or WHEAs. These freezes are probably related to tighter tRFC right?
> 
> So, I noticed that the manufacturer also goes by the name of CXMT (ChangXin Memory Technologies). Also, I've read on some reddit wiki that CXMT tends to be close to Hynix CJR behaviour. What do you guys think? If that's the case, what else should I try on these RAM sticks?
> 
> For now I guess I'll focus on secondary timings, but I'd love to get more juice out of these.
> 
> Right now I'm running this which seem to be stable @ 1.38V:
> 
> View attachment 2566473
> View attachment 2566474


Try 
RRDS 6
RRDL 8
FAW 24
WR 16
RTP 8
WTRS 4
WTRL 12
RFC 600
RDRDSCL 4
WRWRSCL 4
Keep rest as is

See how that goes.


----------



## Bloax

ccxmonster said:


> Hı people, i am currently using these timings for my ram kit;
> View attachment 2566468
> 
> 
> my ram kit is stable under these settings but im still wondering if im using the correct tCKE & Setup Timings
> i saw these settings on web for 3800MHz and applied them, is there more compliant timing of these things for 3733MHz speed ? or these are all good and should i not change ?
> 
> thanks.


1867 is not a clean 100 MCLK above 1800 - so the tCKE requirement actually stays 7 at that frequency, and I haven't heard of Micron chips/sticks requiring CAD Setup Timings(tm)

What you seek lies somewhere in between this:








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Some timings are very sensitive to voltage on B-die, the 3 primeries, RRDS/FAW/WR/RTP, RC and RFC also scales/is sensitive to voltage. RAS, SCLs, WTRs etc don't seem to care much for voltage. On other ram kits like rev E, Hynix AFR etc the generally cared little about voltage except for CL/CWL...




www.overclock.net




and this:








MSI B450 RAM Upgrade advice needed


Hi Specs: MSI b450 Tomahawk MAX AMD Ryzen 5900x I am looking to upgrade my 16GB Crucial Ballistix Sport LT 3000Mhz single rank RAM to 32GB. I've tuned/overclocked this RAM to 3600Mhz and has been running great for around 2 years. This RAM is discontinued so I would need to search ebay if I...




www.overclock.net





As these are most likely Micron 16 gbit B Single-rank sticks, not Micron 8 gbit E dual-rank ones.
They still have the same "unusual" tRAS behaviour as the 8 gbit E chips used in the second thread (tRAS = 3x tCL), but I don't know if they take the same procODT/RTT/CADBus as the 8 gbit E sticks.


----------



## Blackfyre

Taraquin said:


> You can probably lower CCD and VDDP even more. I run mine at 820mv atm, works fine. Below 800mv I get no post, but performance is the same on 820mv as 1000mv on both, but the latter uses a bit more power.


*MAIN EDIT:* The values here did not work and returned errors with 1usmus within 3 cycles out of 60.

*Decreased a few more voltages even further*, I'll run 60 cycles of 1usmus later. But for general use so far, it's stable with no WHEA errors.

*AIDA64 latencies* are with a default boot with usual boot/start-up services & items. Not stripped down or safe mode.

*Edit:* Had to increase CLDO VDDP Voltage back to 0.86 instead of 0.82, as it resulted in PHY being 28/28/28/28 instead of *26/26*/28/28


----------



## slayer1991

Bloax said:


> Looks more like a case of lower RTP/tWR and vDIMM, lower RTP/tWR and procODT impedance, or just lower tWR and vDIMM, or maybe even lower tWR, vDIMM and procODT!
> 
> tRFC 288-214-132 might also be a hair more stable in things like y-cruncher?


Thanks for the reply! I am now getting some C00?05h crashes in TestMem5 around cycle 18/20 1usmus.
No WHEA errors, max dimm temp 46.5*C.

Why are you suggesting to lower vDIMM? Wouldn't that make errors worse?

vDIMM was the same at 1.4388v will try to bring it down next.
ProcODT down from 36.9 to 34.3

RTP/WR down from 8/16 to 7/14
tRFC raised a bit as suggested.
VSOC up from 1.09375 to 1.1v
VDDG IOD up from 0.9474v to 0.9976
tCKE from 1 to 8, wasn't sure if it affected anything to have it that low

CLDO VDDP still at 0.9474v
VDDG CCD still at IOD-0.05v, thus 0.9474v


----------



## ioannis91

I was running 3800 16-16-16-32-48 tRFC 272 GD OFF 1T and the other timings the usual b-die as tight as possible 1.44v, 1v IOD and CDD, 1.1 SoC and 0.9 VDDP, TM5 and hci stable. Going strong for days and at some point when I exited a game the whole system locked up and I forced shutdown with power off button. Everything else was at defaults, no CPU/GPU oc, no curve optimizer, nothing. So it must be the memory. But how can I find it? Maybe some of the voltages? I never understood how you check for IOD and CCD stability.


----------



## slayer1991

The_King said:


> GDM off 1T was not happening, with high ambients here and no RAM cooling I went back GDM.
> 
> Managed to improve subs further WTRS 3 TWR 10. Can't set RTP to 5 because GDM is on. CL14 almost passed so 14-16-16 @ 1.53ish maybe possible.
> Problem is I can no longer get RttNom to boot at 6 anymore.
> 
> View attachment 2565712


Wouldn't RttNom at 7 be better? Lower resistance and thus lower power/heat


----------



## Bloax

ioannis91 said:


> I never understood how you check for IOD and CCD stability.


One old method is letting y-cruncher FFT run for 1-3 hours.








for actually "finding" the right values:








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Are these voltages safe for 24/7? The board gets good airflow. I read that increasing CLDO VDDP and VDDG CCD and VDDG IOD can help with stability and with USB issues, from the X570 HERO motherboard thread.




www.overclock.net







slayer1991 said:


> I am now getting some C00?05h crashes in TestMem5 around cycle 18/20 1usmus.
> 
> Why are you suggesting to lower vDIMM? Wouldn't that make errors worse?
> VDDG IOD up from 0.9474v to 0.9976
> tCKE from 1 to 8, wasn't sure if it affected anything to have it that low


tCKE should be 9 at 1900 MCLK, not 8 :- DD

The crashes could be anything from IOD voltage too low (see above) as I've only had <1.00vIOD run on my 5800x with all CPU features (virtualization, SMT, everything) disabled, the wrong tCKE, or just plain old CADBus (30 on CsOdtDrvStr is a super common sight on b-die sticks, so is a ClkDrvStr above 24)

As for why I suggest lowering vDIMM - then one of the people I recently helped dial in their memory for on an LGA1151 system, was using a random old Ripjaws 3200 14-14-14 kit (much like my first one!)
Who ended up running 3800 16-16-16 ... at 1.355v - because at RTT 6/3/6 it took +0.18v for 3200->3800 MT/s, and gave up -0.18v for 14-14-14 -> 16-16-16 primary timings.
Ending up pretty much at the XMP voltage of 3200 14-14-14 (1.35v) for much better performance. 🦑


----------



## slayer1991

Bloax said:


> One old method is letting y-cruncher FFT run for 1-3 hours.
> View attachment 2566521
> 
> for actually "finding" the right values:
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Are these voltages safe for 24/7? The board gets good airflow. I read that increasing CLDO VDDP and VDDG CCD and VDDG IOD can help with stability and with USB issues, from the X570 HERO motherboard thread.
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> 
> tCKE should be 9 at 1900 MCLK, not 8 :- DD
> 
> The crashes could be anything from IOD voltage too low (see above) as I've only had <1.00vIOD run on my 5800x with all CPU features (virtualization, SMT, everything) disabled, the wrong tCKE, or just plain old CADBus (30 on CsOdtDrvStr is a super common sight on b-die sticks, so is a ClkDrvStr above 24)
> 
> As for why I suggest lowering vDIMM - then one of the people I recently helped dial in their memory for on an LGA1151 system, was using a random old Ripjaws 3200 14-14-14 kit (much like my first one!)
> Who ended up running 3800 16-16-16 ... at 1.355v - because at RTT 6/3/6 it took +0.18v for 3200->3800 MT/s, and gave up -0.18v for 14-14-14 -> 16-16-16 primary timings.
> Ending up pretty much at the XMP voltage of 3200 14-14-14 (1.35v) for much better performance. 🦑


vDIMM: gotcha, increasing MCLK and loosening timings cancel each other's vDIMM requirements.
tCKE: maybe I haven't run into an issue yet, but I have booted and tested successfully with tCKE at 1 and 7, with 3800c16 settings. I will bump it up to 9.

I was able to run TestMem5 1usmus for 20 cycles, and 2 cycles of y-cruncher stress test with no errors now by bumping up some voltages.
ProcODT and Rtt set at 34 and 7/3/5, CADBus still at 24-20-24-24.

I may try bringing down the main timings to 15 or 14 now, while keeping these voltages and resistances(procODT, Rtt, CADBus) stable, as thermals do not seem too bad.

Edit:
Lowering even the first primary to 15 fails to boot, despite increasing ohms across the board.
Lowering VDIMM from 1.435v (1.46 actual) to 1.375v boots, but there's errors found as soon as TestMem5 starts. Maybe I was optimistic, and there may be room to lower voltages.

Edit2: weird/small issue..
Trying to reboot windows (warm boot) gets stuck and screen never comes back on.
A reset will then cause BIOS to revert to safe values, but if I load profile save&reset it posts/boots up no problem.

I tried a shutdown, waited 30sec, and it started no problem, so luke warm boot is okay?
Any clues which settings I should look at first?


----------



## Bloax

slayer1991 said:


> I may try bringing down the main timings to 15 or 14 now, while keeping these voltages and resistances(procODT, Rtt, CADBus) stable, as thermals do not seem too bad.


If you'll pardon the bad formatting (it can take me a long time to "start doing things", including fixing things), then as I outline in the process here: [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

The important thing to get down first is your RTP/tWR, then the procODT/RTT, then the CADBus - as figuring out these things lets you then find a stable RRD/WTR/RDWR/WRRD setup, and then you can super easily go up and down in primary timings or frequency.


or to keep it real short: don't try to go down in primary timings before you get everything stable and well-performing, they're not very important 
even Cap Boy agrees: 




making sure to have A Stable Config is the most important first step


----------



## BoredErica

This is what I got. Going any lower anywhere fails to pass tm5 all day. This was a 3600 c15 2x8GB kit. I've used this setup for almost a year and haven't got any issues like crashing, so there's that at least.


----------



## The_King

BoredErica said:


> View attachment 2566538
> 
> This is what I got. Going any lower anywhere fails to pass tm5 all day. This was a 3600 c15 2x8GB kit. I've used this setup for over 5 months and haven't got any issues like crashing, so there's that at least.


Looks like Samsung B-die because of the low tRFC. (150ns)

tRC should be 42 (13+29) I made the same mistake a few post back.
Im sure you could get 3800/1900 to run with your current setup.


----------



## Nico67

I have been playing around with tuning my ram timings, but for the life of me I can't ever get it to boot at GDM off 1T. Well it does do it at 2133, but not sure that really counts 

It very stable at these settings at 1.415vdimm set, 0.70625vttddr and 1.83pll, but I would like to get 1T so the tPHYRDL is in sync.





  








15-8-16-14 28.2.png




__
Nico67


__
6 mo ago








I have tried way loose timings, setup 56, higher clkdrvstr, all sorts of RTL's. Mainly get F9's, but setup 56 does allow it to start training, but fails every time at random codes.


----------



## slayer1991

Thanks for the pointers! Following different guides by different people messed up my mind.

I have restarted with loose 4000c18 at 1.35 VDIMM, to find all those impedances:
Rtt 6/3/3 works for ProcODT 32-34, it does not post with 30 or 37
Similarly, 7/3/7 works with ProcODT of 30-32.

At 4066MHz, I needed to go up to 37 ProcODT and it booted with 6/3/3 Rtt, but 4133mhz didn't post.

So from what trends I see, higher impedances allow higher frequencies. But for my Ryzen 5 3600x, there isn't much gaming benefit to disconnect from the 1:1 IF ratio, so 3800c16 ram speed is a good target.

Moreover, lower impedances allows to push timings like tRFC lower, correct? So in keeping all voltages as I found in my previous best, I will change:
ProcODT from 34 to 30
Rtt from 7/3/5 to 7/3/7

Which POSTed successfully!
Now CADBus at 24-20-24-24 had some warm boot issues, and pushing CsOdtDrvStr to 30 didn't work, so my next test will be 40-20-40-20

EDIT:
TestMem5 came with 2 errors over 50 cycles of 1usmus_v3 on tests 8 and 10. Back to the edit board..


----------



## Bloax

slayer1991 said:


> EDIT:
> TestMem5 came with 2 errors over 50 cycles of 1usmus_v3 on tests 8 and 10. Back to the edit board..


Ah ****, forgot you were on Zen2 and not Zen3 - CsOdtDrv is usually(?) good at 24 there as opposed to 30 on Zen3

However, 8 and 10 could easily be a request to raise the mystery, elusive "CPU 1.8v" voltage that nobody can agree on a name for* (possibly 1.8v Standby Voltage on your board?) up from 1.8v and slowly towards 1.9v while running procODT 28 instead of 30.
As that would be the only thing that could impact longterm WTRL stability.

* the only consistent giveaway is that its default value is specified as 1.8v, or it's a voltage that is running around 1.8v but not called that (an example was "VTT", which is usually half of vDIMM, not 1.8v)


----------



## slayer1991

Bloax said:


> Ah ****, forgot you were on Zen2 and not Zen3 - CsOdtDrv is usually(?) good at 24 there as opposed to 30 on Zen3
> 
> However, 8 and 10 could easily be a request to raise the mystery, elusive "CPU 1.8v" voltage that nobody can agree on a name for* (possibly 1.8v Standby Voltage on your board?) up from 1.8v and slowly towards 1.9v while running procODT 28 instead of 30.
> As that would be the only thing that could impact longterm WTRL stability.
> 
> * the only consistent giveaway is that its default value is specified as 1.8v, or it's a voltage that is running around 1.8v but not called that (an example was "VTT", which is usually half of vDIMM, not 1.8v)


My procODT cannot go lower than 30ohm on the c6h mobo, and there's no apparent differences between 30-32ohm. Will lower it to 30.
I can bump the CPU 1.8v a bit higher to 1.85v and see what it affects
Will drop the cad bus back down to 24-20-24-24
Warm reboot still getting stuck, will try to enable CSM legacy to make sure it's not the GPU acting up/dieing

Also changed:
RTP/WR to 6/12
WTRS/WTRL worked at 4/8, trying 3/10 next
SoC LLC to Level 2
Found this post by Veii with a similar CPU/RAM, where he suggests tighter WTRS, RRDL and RTP



Veii said:


> Stability check to fix error
> View attachment 2563893
> 
> If error has resolved
> View attachment 2563895
> 
> Keep tRP matching tRCD_RD. Alternative Match (tRCD_RD+tRCD_WR) / 2 ~ to preserve left enough charge between read and write
> Keep tRAS as tRP + tRCD_RD, alternatively go for stacked-shorted/write-split approach (tRCD_RD+tRTP) ~ but requires discharge finetuning. 2nd picture might not work out instantly and/or will lose bandwidth if discharge happens faster than timings (halt-autocorrection)


EDIT:
CSM didn't work, warm reboot still getting stuck
procODT 30 Rtt 6/3/5 and 40-20-40-24 errored out, didn't catch it. Note that these settings couldn't post at 4000Mhz
procODT 32 Rtt 6/3/5 and 24-20-24-24 got an error 0 before cycle 15 of 1usmus
Not sure which of the 2 changed RTP/WR or WTRS/WTRL pairs are causing the error, though they may be temperature related as I am hitting 46-47*C max.

I will revert to last night's settings and change Rtt to 7/3/5 and use 40-20-30-24


RRDSRRDLWTRSWTRLRTPWRLast night almost worked4648714Morning45310612Latest45310612


----------



## Bloax

Error #0 can very easily be RRDL/WTR awkwardness - which is why the usual values you see around are RRD 4/4 and 4/6, and WTR 4/12 or 4/8
WTR 3 is a risky play, especially as it may not even offer performance benefits :-- DDD
The thing which makes it "run" in the first place may even be WRRD 3->4 


If you're worried about temperature, there's always throwing the silly "find lowest RTP/tWR combo that is stable, run double of it" trick at it; [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
performance impact of that, thus far inconclusive, seems to depend on how well you're chasing the tRC window.
(and does funny things like "RDWR 12 runs faster than 11, but not stable" on my LGA1700 config)


----------



## slayer1991

This got me error 3 around cycle 8 running at 48*C. Any clues?
WRRD and SCL already at 4, RRD 4/6

WTR 4/12 is next I guess

Edit: 4/12 failed to train entirely! 4/8 booted up and currently testing. I think my low impedances may be affecting stability too much.
May have to run procODT 32 with 6/3/5 and 40-20-30-24 instead of 30 with 7/3/5 and 24-20-24-24

Edit2: cycle 7 got error 10. Lowering RTP/WR to 5/10


----------



## Bloax

slayer1991 said:


> This got me error 3 around cycle 8 running at 48*C. Any clues?
> WRRD and SCL already at 4, RRD 4/6


RDWR and WRRD are really annoying, because they tend to error when they're not the right values - whether that be too low _or too high_.


----------



## slayer1991

Bloax said:


> RDWR and WRRD are really annoying, because they tend to error when they're not the right values - whether that be too low _or too high_.


Will try to lower those from 8/4 to 8/1 once this RTP/WR 5/10 eventually fails and goes back up to 7/14 😂

Edit:
RTP/WR at 5/10 actually got me all the way to cycle 28! But again error 10. I could try the doubling of those two trick, and time to bring WRRD down from 4 to 1 or so?


----------



## Bloax

At this point it's definitely WRRD 3, 2, or 1

Doubling RTP/tWR is mostly a concern if you have a GPU that cooks everything including the RAM, though there's always looking at 2.5 Billions of Pi times with a static CPU frequency to see if it somehow makes things faster instead of slower. (Which opens up another can of worms ..)


----------



## Melan

Returned home to TM5 with absolut cfg finishing up testing this plain weirdness. Apparently it's stable.
Doesn't make much (or any) difference from what I was running before (rcd 19, ras 35, rc 55, wr 16, rtp 8) except maybe in PYPrime where I had 12.230s computation time compared to this with 11.970s.
Edit: Ran linpack xtreme and apparently this weirdness gains me 5-7 GFlops. I should probably keep it


----------



## Blackfyre

Achieved my lowest latency ever with my current setup (_bloated boot, not even in safe-mode or stripped down_), a drop of ~4ns thanks to @GRABibus suggesting disabling HW Prefetcher L1 and L2 cache

ZenTimings highlighted values were also lowered, but had little impact on latency from their already low values before. tRCDWR & tRAS lowered to outside the formula. They were 18 and 40, I'll probably return them to 18 and 40.

58 cycles run out of 60 to confirm stability.


----------



## Blackfyre

*Safe mode results from above (upscaled image):*


----------



## Veii

Melan said:


> Returned home to TM5 with absolut cfg finishing up testing this plain weirdness. Apparently it's stable.
> 
> 
> Melan said:
> 
> 
> 
> Ran linpack xtreme and apparently this weirdness gains me 5-7 GFlops. I should probably keep it
Click to expand...

If you want to be really "weird" well experimental friendly try:


Code:


15   //    5
10   //    5
20   //    14
20   //    5
25   //    10 (better 9, but up to PCB)
45   //    2
5    //    1
5    //    4
20   //    4
4    //    1
10   //    5
20   //    5

If Hynix DJR ~ 220-230ns
450 (240ns)
334
206

I think tho you will have overlapping issues by lack of charge.
Could be "just fine" as tRP is too long, but usually that tRC 45 needed tBURST-Chop ontop =49
Eh, good luck ~ i guess

My own recommendation would be running:


Code:


15  //   3
18  //   3
18  //  14
18  //   6
36  //   9  if Hynix, 10 if Micron // potentially 8 if Hynix and not on A0 PCB
54  //   6  or 3, if 6 overlaps
6   //   1
6   //   4
20  //   2
3   //   1
12  //   6
12  //   2
540 //   8   (near 280ns if worst Hynix)
401
247

RTT_NOM /7
RTT_WR /3
RTT_PARK /4

CAD_BUS
40-20-30-24

VDIMM 1.42-1.44v

Later down to CAS 14 ~ and then tRDWR 8 if this PCB can do it
I would not split Reads and Writes , but do everything to get tRCD lower


Blackfyre said:


> ~4ns thanks to @GRABibus suggesting disabling HW Prefetcher L1 and L2 cache


It's cheating by trading in Branch Prediction perf, for potential lower access latency
Trading in CPU compute perf for a screenshot
You need to only disable L2 prefetcher ~ for this trickery to work. I get ~45ns with it, but it's a tradeoff. Hence you OC mem for IPC, it's kind of not the point loosing IPC

@Rinko any progress on your side ?
Sorry i did not respond, but Bloax took over gladly
Screenshots you gave are a bit short. You'd like to run 1usmus_V3 at least for 20 cycles, optimally 25+
And at any capacity over 1h, soo thermal equilibrium leverages out.
We're testing discharge of capacitors, and so thermals would be preferred to be steady~


----------



## Melan

Veii said:


> If you want to be really "weird" well experimental friendly try:


Thanks. I'll try that later today. This is CJR with A2 pcb and from what I've found so far the ~262ns RFC is an absolute must because anything lower than 488 (~262ns at 3733) starts throwing errors during furmark roast and stupid hot weather isn't helping much either.
As for voltages, I've tried running 1.38 and higher but this kit utterly despises anything above 1.35 and starts error cascading on 1.38 while 1.4+ just rapid fires 20 errors/sec right into a blue screen.


----------



## KedarWolf

Not want to run 1.2v VSOC in the top, except for benching, even though it passes TM5, I run the below 24/7.


----------



## Melan

@Veii Tried the "experimental weirdness" and the system is very upset with RTP of 5... so I tried 10 and it posted. But any attempt to edit tertiary timings upsets it again so I tried the next set.
Your recommendation of 15-18-18-36 doesn't really work with this kit. Tertiary timings stop the system from posting, but everything else while posts, RCD 18 corrupts the memory. 16-19-19-36 was minimum what was required to successfully get into windows, and as I previously mentioned, this kit went nuts from v1.4+.
16-19-20 at 1.35v seems to be only thing that's working... so I went back to my old config.


----------



## Audioboxer

KedarWolf said:


> Not want to run 1.2v VSOC in the top, except for benching, even though it passes TM5, I run the below 24/7.
> 
> View attachment 2566609
> 
> 
> View attachment 2566610


I'm guessing if you run tCL13 you'll get tPHYRDL 26/26 at 1T? Dunno what it is with these MSI boards lol...

tCL13 should boot for you, will just require you to pump VDIMM until it does.


----------



## Bloax

Audioboxer said:


> tCL13 should boot for you, will just require you to pump VDIMM until it does.


edit: groggy writing snafu, voltage requirements blblblbl
The voltage required for +/- tCL in my experience is usually more or less +/- 100 MCLK, which is a lower voltage (0.06-0.08) than +/- tRCD (0.09-0.11)

by the way it's ****ing over guys my memory is unstablel 😔😔😔😔😔


----------



## Audioboxer

Bloax said:


> +/- tCL in my experience is usually more or less +/- 100 MCLK, which is a lower voltage (0.06-0.08) than +/- tRCD (0.09-0.11)
> 
> by the way it's ****ing over guys my memory is unstablel 😔😔😔😔😔
> View attachment 2566646


tCL impacts your MCLK?

Usually it's just a matter of bruteforcing tCL with VDIMM in my testing. I can even run 12 at 3800, issue is it requires 1.65v+ and I've never been able to keep b-die stable at such high voltages.


----------



## slayer1991

Bloax said:


> At this point it's definitely WRRD 3, 2, or 1
> 
> Doubling RTP/tWR is mostly a concern if you have a GPU that cooks everything including the RAM, though there's always looking at 2.5 Billions of Pi times with a static CPU frequency to see if it somehow makes things faster instead of slower. (Which opens up another can of worms ..)


Tried WRRD at 1 and it failed with errors 10 and 13 after some of those C0000005h crashes.
Thought maybe it was vDIMM, so I dropped it from 1.4388-1.46v (swings) down 25mV to 1.417-1.4388v and I ran into errors 3 and 5.

So now I bumped up WRRD to 3, should I have tried 2 instead so it's an even number? Lettuce see, results pending...

Edit: came back with errors 3 and 5, and with WRRD at 2 I got error 3. Not sure which way to go next.


----------



## N2Gaming

Hey y'all,

It was suggested I post this question in this thead.

I have the MSI MEG X570 Unify board running a 3800x and 2x16Gb of dual rank Ram kit linked below


What could I expect if I added another 2x16gb kit of these to the already existing 2x16gb kit of these? Would it put too much strain on the cpu or cause issues. Presently running the 3800x but planning to upgrade to the 5800x.

I don't overclock manually as PBO and XMP settings are quite sufficient imo.

That's another question, is any one still having problems with the 5800x or had problems in the past that they were able to resolve?









G.SKILL Ripjaws V Series 32GB DDR4 3600 RAM Memory - Newegg.com


Buy G.SKILL Ripjaws V Series 32GB (2 x 16GB) 288-Pin PC RAM DDR4 3600 (PC4 28800) Desktop Memory Model F4-3600C16D-32GVKC with fast shipping and top-rated customer service. Once you know, you Newegg!




www.newegg.com


----------



## Bloax

N2Gaming said:


> I have the MSI MEG X570 Unify board running a 3800x and 2x16Gb of dual rank Ram kit linked below
> 
> 
> What could I expect if I added another 2x16gb kit of these to the already existing 2x16gb kit of these? Would it put too much strain on the cpu or cause issues.


If the DIMM PCB isn't friendly to being run in the bad slots of a daisy-chain topology (which is in most modern 2-slots-per-memory-channel boards), then you'll likely be stuck at either DDR4-3200 or less.
There's good chance that they wouldn't be good, and so I'd recommend something like this instead if you want to run 4x16 GB:








Crucial Ballistix 32 GB (2 x 16 GB) DDR4-3200 CL16 Memory (BL2K16G32C16U4B) - PCPartPicker


Crucial Ballistix 32 GB (2 x 16 GB) DDR4-3200 CL16 Memory (BL2K16G32C16U4B)




pcpartpicker.com





as those troll PCBs at least work properly in such a configuration

I also have to hold myself from rambling incoherently about how XMP and PBO is not OK on AM4 because fabric dropouts make life wonderful and stuttery, bad memory timings do so too


----------



## N2Gaming

Being stuck at rated speeds does does not bother me the slightest. Having freezing/lock up issues or strain on the CPU's IMC does! Im trying to digest and understand what all you just said. Baby steps lol.

Are you saying that even though the mobo has 4 ram slots for dual channel that the dual rank plays a role in how the dual channel works when all 4 slots are populated?

Edit: Oh after reading it for a second time I realize that you also mentioned XMP and PBO not playing well together. I must be lucky with my system for now with just 2 slots populated and xmp enabled with PBO.

So 4x same sticks populated that I currently have runninh in XMP and PBO won't mesh well together?


----------



## Bloax

What I said is that the Sticks you have are unlikely (I could be wrong!) to Work Well in a 4x config due to their internal construction, and that Other Sticks (with a different internal construction) have a proven track record of doing that well.

It's not a memory controller problem - people have run 4x16 3866 16-16-16 with "ok" timings - it's a "the RAM stick just doesn't want to work in this slot" problem.
practical example:
My old ripjaws 3200 14-14-14 sticks refuse to go faster than DDR4-3400 in "bad" slots.
My Viper 4400 19-19-19 sticks, which I describe as "working very well" in "bad" slots, have gone to DDR4-4200 and would probably go even faster, despite being in the very same "bad" memory slot.

Same processor, same board, different PCBs, completely different behaviour.


as for XMP;

If you run ZenTimings you may see some really stupid things (top-right corner);








a fabric/memory clock desync for no reason, entirely too much voltage
-->








lower FCLK values (up to around 1700ish?) aren't very sensitive to running three voltages ("vddg" SOC, IOD, CCD) within +/- 0.01v of The Perfect Value(tm) to perform "good"

Too much voltage results in "fabric problems", which can be seen as latency spikes in something like LatencyMon or USB dropouts/mouse skipping/audio pops.












It is really quite annoying, how much setup AM4 requires to "run properly".


With PBO on a 5800x, you're likely going to be running power limits much lower than the stock values, such as PPT 96 and TDC 48 - then apply a heavy negative curve offset.
Otherwise the CPU runs pointlessly hot, and runs too high a voltage for too little frequency.







here's a little example of my old 5800x in a light workload (not PBO but whatever), while under normal circumstances it might be doing 4650 Mhz @ 1.35v instead of.. 4900 at 1.25v lol


----------



## Veii

Melan said:


> Your recommendation of 15-18-18-36 doesn't really work with this kit. Tertiary timings stop the system from posting, but everything else while posts, RCD 18 corrupts the memory.


tRCD 18 will have to run higher voltage, there is no way around that



Melan said:


> But any attempt to edit tertiary timings upsets it again so I tried the next set.


You tested things step by step once tRTP didn't work or ?

Because timings are connected
If you modify one thing, you have to modify the last and the next one
Else they wont work

If tRTP is low, very likely can be
Then you could double both tRTP and tWR
And if it still doesn't work , i have to redo the whole set

can't just let you keep a half working one
Timings will overlap or end too short = useless preset 

Maaybe we can get tRTP 5 to work still, but else i don't think it makes sense to run "lowest possible" and you should track where you have a bottleneck on the preset
Timings at best loop and then you lose 0.5-1 tCK , soo at 3733.333333~4 tha's about half a ns (0.5357inf)
It could be off by 1-2 tCK too , which is trackable but not really feelable in perf , unless stuff is halted or completely unstable


Melan said:


> and as I previously mentioned, this kit went nuts from v1.4+.


Soo there is at first a powering problem beside your timings
Alone that you require higher tRP for (p)recharge, before and post tRCD makes it a bit questionable // higher tRP over tRCD, should be equal usually or lower

A2 needs higher current to function, and you offset stability with just long (p)recharge pauses in between everything
Soo those pauses could also hide and give the ability to lower timings near it ~ tertiary without them really being able to run that low (fake stability)

I would start to go up with the timings, and figure out what is actually looped in the hidden, without you noticing. What timing was ending too early and holds the whole chain
As at best they loop and stability is kept up ~ but preferably they crash , so you know which one it is

Let's start by figuring out why you only need 24ohm ClkDrvStr and why you crash above 1.4v
Add in RTT_WR to balance current and signal integrity
Then push RTT_PARK weaker and add ClkDrvStr a bit

See after which point whatever you run atm , can still keep up stability above 1.4v
As you will have to run higher voltage for lower Primaries ~ no way around that
but higher voltage will never mean higher temperature ~ soo work on powering first before we continue riding a tired donkey 
Hynix do love voltage till 1.62
But they have a little deadspot near 1.48-1.56 , like negative scaling where nothing works out for some reason


----------



## Baio73

The_King said:


> GMD off 1T stable is great without using Cmd 56.
> 
> I dont run very long tests like you or others on here but 3800-14-15-15-15-30-45 with the same voltage may work.
> You may need to change your tRFC. You can use Veii tRFC mini to adjust that.


Thanks for your replay.
I tried 14-15-15-30-45 and it's ok after 5 hours of Anta, now I'm gonna test with 1sums profile and 25 cycles as usual.
I'm not so skilled about timings, but using tRFC mini with 3800 tCL 14 and tRC 45 gives me tRFC=450, that is far more high then the value I'm using ATM (256)... Am I missing some step?





> You can try TWR 20 RTP 10 that may or may not improve temps or heat tolerants. Only way to find out is to test it.


Tried but no boot and a CPU error code in ASUS display...



> For better performance TWR 10 RTP 5 should be faster. Also try 12/6 or 12/8


Next try!



> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> Edit: Useful commands to prevent / fix Data corruption. Run it from time to time from command prompt with ADMIN rights.
> SFC /scannow
> 
> DISM /Online /Cleanup-Image /CheckHealth
> DISM /Online /Cleanup-Image /ScanHealth
> DISM /Online /Cleanup-Image /RestoreHealth


Noted! ;-)

Baio


----------



## Melan

Veii said:


> You tested things step by step once tRTP didn't work or ?


Yes. At first I hammered them all in (which didn't work), then I went and done them in sets which revealed issue with RTP. Attempting to change tertiary timings pretty much always ended up in a failure.



Veii said:


> Alone that you require higher tRP for (p)recharge, before and post tRCD makes it a bit questionable // higher tRP over tRCD, should be equal usually or lower





Veii said:


> See after which point whatever you run atm , can still keep up stability above 1.4v


Running 1.4v with what I have right now isn't much of a problem (I didn't test it for hours with furmark though), but the moment RP goes down from 20 to 19, increasing voltage only increases the amount of errors I get within 30 seconds. Errors are 0 and 4, but I'm running universal-2 profile, so I'm not sure how well that relates to the absolut profile error guide on google docs calc. I have tried everything on auto and leaving only 16-19-19 and it still does the same. I tried playing around with RTT and ClkDrvStr which changed pretty much nothing. On hardwareluxx is does say that CJR might need 1 RP over RCD, which seems to be the case with my kit anyway.

I'll try 1usmus_v3 profile later. Maybe that'll show something which I can look up in the calc.
Edit: A bunch of 6s with 0s sprinkled here and there. Since I ran in safe mode it didn't bluescreen (it did outside of safe mode though)


----------



## The_King

Baio73 said:


> Thanks for your replay.
> I tried 14-15-15-30-45 and it's ok after 5 hours of Anta, now I'm gonna test with 1sums profile and 25 cycles as usual.
> I'm not so skilled about timings, but using tRFC mini with 3800 tCL 14 and tRC 45 gives me tRFC=450, that is far more high then the value I'm using ATM (256)... Am I missing some step?
> 
> 
> 
> 
> 
> Tried but no boot and a CPU error code in ASUS display...
> 
> 
> 
> Next try!
> 
> 
> 
> Noted! ;-)
> 
> Baio


For tRFC/2/4 I think there are 3 options you can use.

450/334/206 - 236ns
315/234/144 - 165ns
270/201/123 - 142ns <-- This is the one to try.

If you are using a lower tRFC and have no issues then probably leave it at 256.

@Veii should be able to advise better than me, he made that spreadsheet.


----------



## Bix

Bloax said:


> Might be suggesting that it wants Wr/2 and ClkDrvStr 60 or someshit, but that's certainly better than insta-crashing!


I've made some progress with AddrCmdSetup 0 but the best I've seen so far is still 8 errors in 3 cycles so still a long way to go. I'm still doubtful that this setup will work without any kind of setup timings but it's fun trying Here's where I'm currently at:










I've tried various RTT combinations including RttWr/2 alongside _A LOT_ of CADBus combinations to try and make ClkDrvStr 60 work but 120 seems to be the only option that doesn't get me 200+ errors in the first cycle.
Does anything look obviously off or any suggestions what to try next? I've been over a lot of what @Veii has written about powering again but still finding it really difficult to balance things!


----------



## slayer1991

Sad update for me as well. Recap

WRRD at 4 -> error 10
WRRD at 1 -> errors 10 and 13
vDIMM down by 25mV to 1.417-1.4388 (fluctuates) -> errors 3 and 5
WRRD at 3 -> errors 3 and 5
WRRD at 2 -> only error 3!
WRRD at 1 and procODT 30 Rtt 6/3/5 with CAD_BUS at 40-20-24-24 -> error 14 and 5
WRRD at 2 and Rtt 7/3/5 with CAD 40-20-30-24 -> errors 10, 14, and 5
WRRD at 3 and procODT 32 Rtt 6/3/5 and CAD 24-20-24-24 -> error 5
34ohm got error 14 on cycle 5.
Edit: back to 30ohm and WTRL to 10 -> error 14 on cycle 11

It seems like the higher the frequency, the higher procODT and Rtt dividers are needed to POST (4GHz: [email protected]/3/4 and [email protected]/3/3 and [email protected]/3/3)
I did raise the 1.8v PLL to 1.85 hoping that it would allow a low procODT.

I feel a little lost, not sure what to try next, since min procODT is 30ohm.


----------



## KedarWolf

Bix said:


> I've made some progress with AddrCmdSetup 0 but the best I've seen so far is still 8 errors in 3 cycles so still a long way to go. I'm still doubtful that this setup will work without any kind of setup timings but it's fun trying Here's where I'm currently at:
> 
> View attachment 2566696
> 
> 
> I've tried various RTT combinations including RttWr/2 alongside _A LOT_ of CADBus combinations to try and make ClkDrvStr 60 work but 120 seems to be the only option that doesn't get me 200+ errors in the first cycle.
> Does anything look obviously off or any suggestions what to try next? I've been over a lot of what @Veii has written about powering again but still finding it really difficult to balance things!


This is my 24/7 daily settings.










I COULD run this TM5 stable, but the high VSOC etc.


----------



## Bix

KedarWolf said:


> This is my 24/7 daily settings.
> 
> View attachment 2566699
> 
> 
> I COULD run this TM5 stable, but the high VSOC etc.
> 
> View attachment 2566700


Nice! Does your daily actually perform better given the added power budget for boosting? Here's my current profile running happily with AddrCmdSetup 56. There's definitely still some room for improvement (VDIMM can probably go higher) but I decided to try and see if I could do @Bloax trick of using WR/RTP 20/10 to allow the setup time to be removed. Finding it pretty tough!


----------



## MrHoof

From my understanding and looking at bench results from 1T with setup timings and without I think there is close to 0 performance diferrence.
AddrCmdSetup just seems to "move" the dataeye so it fits but not really impacting performance.
Posted this video in the past once already Ensuring DDR4 Electrical Performance at Intended Data-Rate - YouTube (rather boring)










edit: my daily config vdimm 1.55v


----------



## Bix

MrHoof said:


> From my understanding and looking at bench results from 1T with setup timings and without I think there is close to 0 performance diferrence.
> AddrCmdSetup just seems to "move" the dataeye so it fits but not really impacting performance.


That's interesting - a lot of that video explanation goes way over my head but I think I understand the concept. I always just assumed that the Setup timings introduced an additional delay and in Memoryland delays are bad.


----------



## MrHoof

Bix said:


> That's interesting - a lot of that video explanation goes way over my head but I think I understand the concept. I always just assumed that the Setup timings introduced an additional delay and in Memoryland delays are bad.


Well my case would support my speculation, if I add 56 AddrCmdSetup it wont even get into windows, I´ll get a bluescreen at boot.


----------



## Bix

MrHoof said:


> Well my case would support my speculation, if I add 56 AddrCmdSetup it wont even get into widows, I´ll get a bluescreen at boot.


But therefore strange that I can stabilise 1t relatively easily at 56 AddrCmdSetup and get stable enough to even run TM5 at 0 AddrCmdSetup...


----------



## MrHoof

Bix said:


> But therefore strange that I can stabilise 1t relatively easily at 56 AddrCmdSetup and get stable enough to even run TM5 at 0 AddrCmdSetup...


I guess do benchmarks to compare if it its even worth it trying to stabilize it.


----------



## Bix

MrHoof said:


> I guess do benchmarks to compare if it its even worth it trying to stabilize it.


I think I'm stable enough to run some of the shorter y-cruncher benchmarks now and AIDA's working fine so that's definitely worth checking. Will have a look tomorrow


----------



## slayer1991

slayer1991 said:


> Sad update for me as well. Recap
> 
> WRRD at 4 -> error 10
> WRRD at 1 -> errors 10 and 13
> vDIMM down by 25mV to 1.417-1.4388 (fluctuates) -> errors 3 and 5
> WRRD at 3 -> errors 3 and 5
> WRRD at 2 -> only error 3!
> WRRD at 1 and procODT 30 Rtt 6/3/5 with CAD_BUS at 40-20-24-24 -> error 14 and 5
> WRRD at 2 and Rtt 7/3/5 with CAD 40-20-30-24 -> errors 10, 14, and 5
> WRRD at 3 and procODT 32 Rtt 6/3/5 and CAD 24-20-24-24 -> error 5
> 34ohm got error 14 on cycle 5.
> Edit: back to 30ohm and WTRL to 10 -> error 14 on cycle 11
> 
> It seems like the higher the frequency, the higher procODT and Rtt dividers are needed to POST (4GHz: [email protected]/3/4 and [email protected]/3/3 and [email protected]/3/3)
> I did raise the 1.8v PLL to 1.85 hoping that it would allow a low procODT.
> 
> I feel a little lost, not sure what to try next, since min procODT is 30ohm.


Finally something that passes 25 cycles in TM5!!
procODT at 34ohm with Rtt 6/3/5 and 40-20-24-24 sounds like the sticks just wanted a cleaned/dampened signal by using SOME higher impedances (not all)
These settings are also not that far from stuff that didn't work, so I must have been just at the edge of it.

Should I try to tighten more timings, or to drop down any voltages?

Timings to retry dropping lower: WRRD, primaries + tRFC
Drop voltages while keeping them spaced around IOD = 50mV + CCD ; and VDDP = 50mV + cLDO VDDP
The 1.8V PLL may also be able to drop from 1.85v, since I had to raise procODT anyways

Thanks everyone for inputs and for posting, I'm churning around 2 year old posts to see what else I can find.


----------



## Bloax

Bix said:


> I decided to try and see if I could do @Bloax trick of using WR/RTP 20/10 to allow the setup time to be removed. Finding it pretty tough!


Hehe, sorry for sending you down a silly rabbithole - I was simply _very_ curious if this is some quirky LGA1700 thing, or if this is a thing on AM4 too.

hope you enjoyed your stay in minesweeper land 🤡💦



slayer1991 said:


> Should I try to tighten more timings, or to drop down any voltages?


You can try and shoot y-cruncher 2.5 billion to see if WRRD 3->2->1 perform any different (could be worse!)

Otherwise, not really - now you just increase voltage by however much it takes to do -1 tRCD (usually 0.09-0.11v) while dropping tCL/tRCD/tRP/tRAS/tRC/tRFC all at once, hehe.
oh right, and tCWL too, let's not forget that one (in steps of 2, as uneven values don't work, with +1 RDWR on uneven tCL's)


----------



## KedarWolf

slayer1991 said:


> Finally something that passes 25 cycles in TM5!!
> procODT at 34ohm with Rtt 6/3/5 and 40-20-24-24 sounds like the sticks just wanted a cleaned/dampened signal by using SOME higher impedances (not all)
> These settings are also not that far from stuff that didn't work, so I must have been just at the edge of it.
> 
> Should I try to tighten more timings, or to drop down any voltages?
> 
> Timings to retry dropping lower: WRRD, primaries + tRFC
> Drop voltages while keeping them spaced around IOD = 50mV + CCD ; and VDDP = 50mV + cLDO VDDP
> The 1.8V PLL may also be able to drop from 1.85v, since I had to raise procODT anyways
> 
> Thanks everyone for inputs and for posting, I'm churning around 2 year old posts to see what else I can find.


I'm 13 cycles in Iike the below Zen Timings but with 1T, SCLs at 4, tRP and tRAS at 14-26, tRC at 40, DSD and DDD at 4-4, RSD and RDD at 6-6, VSOC at 1.1V, VDDGs at 1v and 1.05v, VTTs at .755v, memory at 1.51v., setup at 56, ProcODT AT 36, 40-20-24-24.

It looks like it's going to pass 25 cycles and it'll be my 24/7 safe settings.

It shaves a full second off my 2T settings in y-cruncher.










I'll post a Zen Timings after it finishes, want to see how long it takes to complete with no background apps running.

I'm on my phone now.


----------



## dansi

RonLazer said:


> Dark Hero! Although its called "Promontory Presence" for some reason, I can never fathom why BIOS programmers refuse to give anything a useful name.
> 
> @Veii I don't think your theory about WHEAs being caused by the Realtek chip holds water (open to evidence to prove otherwise though!). I was just looking at the WHEA 19 Events and I noticed the Memory Hierarchy Level is "3", which according to the Windows hierarchy map is the L3 cache. WHEA 18s (caused by undervolting, usually curve-optimiser being too low) usually report level 0 which is the CPU registers, and sometimes level 1 (instruction cache), which is exactly what you'd expect if the error was occurring in the CPU cores. An L3 cache error implies it was caught by the GMI bus ECC mechanism before passing through the CPU cores or the L1/L2 cache. Now this could well be faulty data from a malfunctioning chip, but the CBS settings indicate that the MCA uses error thresholding and the default is set to 10, although I'm not sure how often it triggers, but you can increase it up to 4094 I think. A high memory intensity workload would be flooding the L3 cache with data, and if some of it was getting corrupted in the transfer (due to unstable link speeds) then that would exceed the MCA error threshold and trigger a PIE event which is reported to the OS. The AMD documentation points suggests this is the error:
> 
> View attachment 2511661
> 
> 
> So yeh, this might be a case of Occams Razer. The simplest explanation is the infinity fabric is clocked too high and data sent along the bus is getting corrupted. It's likely happening in normal operation, but rarely enough to stay below the MCA error threshold so it doesn't get reported.
> 
> I maintain that the root of the problem is due to the link-equalisation mechanism, where AMD/Hypertransport developed a protocol for synchronising the IF-PHY bridge interface up to 1900MHz (which appears to have been its maximum design spec), slapped together something functional but imperfect for 1900-2000MHz range in time for Zen3, but ultimately couldn't even get it to reliably synchronize until AGESA 1.1.8, decided it wasn't worth sinking extra effort into trying to push the link-equalisation past 2000MHz and so any higher frequencies re-use the protocol for 2000MHz. Maybe some chips have a remarkably stable interconnect and can function outside the specified range, but there's no hope of finding the hidden settings that will unlock performance outside this range. Maybe they will update the AGESA at some point to improve the IF-PHY training algorithm, but I wouldn't hold my breath.


bumping this to say author is on to something.

WHEA 19 corrected unknown error with level 3 hierarchy, is very likely your cores L3 having problems synchronizing with higher fclk. i believe there's a balance where a high fclk need to run L3 slower

you either lower you boost clocks overide to lower L3 or you go back a step in fclk ratio

i wish there's a setting in bios to separately cap L3 clocks. as present L3 clocks run on same domains as core clocks


----------



## slayer1991

Bloax said:


> You can try and shoot y-cruncher 2.5 billion to see if WRRD 3->2->1 perform any different (could be worse!)
> 
> Otherwise, not really - now you just increase voltage by however much it takes to do -1 tRCD (usually 0.09-0.11v) while dropping tCL/tRCD/tRP/tRAS/tRC/tRFC all at once, hehe.
> oh right, and tCWL too, let's not forget that one (in steps of 2, as uneven values don't work, with +1 RDWR on uneven tCL's)


100 cycles and I woke up to a sea of errors 5, 3, 14. Will try to drop primary timings once finally stable.



KedarWolf said:


> I'm 13 cycles in Iike the below Zen Timings but with 1T, SCLs at 4, tRP and tRAS at 14-26, tRC at 40, DSD and DDD at 4-4, RSD and RDD at 6-6, VSOC at 1.1V, VDDGs at 1v and 1.05v, VTTs at .755v, memory at 1.51v., setup at 56, ProcODT AT 36, 40-20-24-24.


Not bad!


----------



## ReyReverse

Bix said:


> ClkDrvStr 120 seems to be the only one that allows TM5 to run for me without setup timings. No bluescreens or crashes yet. The best I've managed so far is 16 errors in the first cycle so still miles away from stable but at least I've got my foot in the door🙂
> 
> I'm assuming that needing ClkDrvStr that high means something's not right with my powering elsewhere...


120ohm......Don't do it daily, You will have very serious power delivering issue. Your PC will black screen restart randomly.
Safe value is 40
If run 2T gdm disabled best choice is 30

60 is bad......120 very bad........
Try to keep it as low as possible.


----------



## ReyReverse

KedarWolf said:


> Not want to run 1.2v VSOC in the top, except for benching, even though it passes TM5, I run the below 24/7.
> 
> View attachment 2566609
> 
> 
> View attachment 2566610


so envy~~~~you have a very good golden 5950x CPU chip this made you allow to run CsOdtDrvStr at 24 ohm. 
is this UEFI bios Agesa 1207?


----------



## Veii

Baio73 said:


> that is far more high then the value I'm using ATM (256)... Am I missing some step?


----------



## Bix

ReyReverse said:


> 120ohm......Don't do it daily, You will have very serious power delivering issue. Your PC will black screen restart randomly.
> Safe value is 40
> If run 2T gdm disabled best choice is 30
> 
> 60 is bad......120 very bad........
> Try to keep it as low as possible.


Yeah this definitely isn't going to be my daily, just playing around seeing if I can get rid of my setup time but it's definitely looking like a no-go! I'm pretty sure that 60ohms is OK though, so long as it's balanced with vDIMM and RTTs.



MrHoof said:


> I guess do benchmarks to compare if it its even worth it trying to stabilize it.


Results from AIDA are pretty close, although latency is consistently 0.2ns faster on average without the setup time. y-cruncher 2.5 billion scored slightly lower without the setup time, although I only managed to get an error-free run twice so could potentially score better if it were more stable.
Ultimately I don't think it's possible to stabilise it anyway but interesting to see that it's _potentially _more performative.



Bloax said:


> Hehe, sorry for sending you down a silly rabbithole - I was simply _very_ curious if this is some quirky LGA1700 thing, or if this is a thing on AM4 too.


No problem, was fun trying! Happy to be a guinea pig🐹



Taraquin said:


> My ram is also stuck behind a D15 You could try a bit higher voltage (1.49v seems to be the thermal limit on my setup) and RCDRD 14, RP 14, slightly lower RFC (250-260), maybe 9 or 8 RDWR, 3 or 1 on WRRD. Also lowering RAS and subsequently RC may be a bit faster.


(Edited) Mine can do RP 14 at 1.49v (1.48v set but MSI). Will try RCDRD next👍


----------



## slayer1991

Bloax said:


> Looks more like a case of lower RTP/tWR and vDIMM, lower RTP/tWR and procODT impedance, or just lower tWR and vDIMM, or maybe even lower tWR, vDIMM and procODT!
> 
> tRFC 288-214-132 might also be a hair more stable in things like y-cruncher?


Aand so I slammed WR, vDIMM and procODT from 16, 1.435, 37 down...



slayer1991 said:


> Sad update for me as well. Recap
> 
> WRRD at 4 -> error 10
> WRRD at 1 -> errors 10 and 13
> vDIMM down by 25mV to 1.417-1.4388 (fluctuates) -> errors 3 and 5
> WRRD at 3 -> errors 3 and 5
> WRRD at 2 -> only error 3!
> WRRD at 1 and procODT 30 Rtt 6/3/5 with CAD_BUS at 40-20-24-24 -> error 14 and 5
> WRRD at 2 and Rtt 7/3/5 with CAD 40-20-30-24 -> errors 10, 14, and 5
> WRRD at 3 and procODT 32 Rtt 6/3/5 and CAD 24-20-24-24 -> error 5
> 34ohm got error 14 on cycle 5.
> Edit: back to 30ohm and WTRL to 10 -> error 14 on cycle 11
> 
> It seems like the higher the frequency, the higher procODT and Rtt dividers are needed to POST (4GHz: [email protected]/3/4 and [email protected]/3/3 and [email protected]/3/3)
> I did raise the 1.8v PLL to 1.85 hoping that it would allow a low procODT.
> 
> I feel a little lost, not sure what to try next, since min procODT is 30ohm.





Bloax said:


> Hehe, sorry for sending you down a silly rabbithole - I was simply _very_ curious if this is some quirky LGA1700 thing, or if this is a thing on AM4 too.
> 
> hope you enjoyed your stay in minesweeper land 🤡💦
> 
> 
> You can try and shoot y-cruncher 2.5 billion to see if WRRD 3->2->1 perform any different (could be worse!)
> 
> Otherwise, not really - now you just increase voltage by however much it takes to do -1 tRCD (usually 0.09-0.11v) while dropping tCL/tRCD/tRP/tRAS/tRC/tRFC all at once, hehe.
> oh right, and tCWL too, let's not forget that one (in steps of 2, as uneven values don't work, with +1 RDWR on uneven tCL's)


Quite a ghost hunt and 9 days later, a whole lotta impedance sweep, the 10,13 errors were traded for 3,5,14.
The error table is a little hard to read sometimes when it says increase RttNom to something stronger.. from RZQ/6 does that mean /5 or /7?

I am now back to procODT 30 with Rtt 7/3/5 and 24-20-24-24 at 1.42 vDIMM, and finally got something different, error 9 at cycle 20!!
At least that's descriptive, so +10mV on the VDIMM next, brings me to 1.43, just 5mV lower than the starting playground.

Maybe it was the 2nd part of @Bloax advice and "lower RTP/tWR and procODT impedance" that was the magic dust.

Edit: attached is a 38 cycle stable run!
Would lower SCL to 2 or 3 improve performance a lot?
Are SC/SD/DD timings relevant?
Why can RCDWR be ran offset from the other timings? I have found some weirdly matched 14-10-15-12-26-38 primaries in some posts.

Edit2: cannot even POST or get to Windows with higher than 1.49 vDIMM with 3800c15, and there I got a flurry of errors 6 and 12.

Thanks!


----------



## SneakySloth

Bix said:


> Nice! Does your daily actually perform better given the added power budget for boosting? Here's my current profile running happily with AddrCmdSetup 56. There's definitely still some room for improvement (VDIMM can probably go higher) but I decided to try and see if I could do @Bloax trick of using WR/RTP 20/10 to allow the setup time to be removed. Finding it pretty tough!
> 
> View attachment 2566703


If you're able to, test this out with the Universal2 profile in Tm5 as well. 1usmusv3 was fine for me as well for this ram and pretty much the same timings @ 1.47v but I had to bump up the voltage a little to be stable in the Universal profile. The profile's cycles will need to be increased to run it for the same amount of time.


----------



## Baio73

Veii said:


>


Thanks, didn't notice that...
I used the Pre-Release tRCF Mini and got this:



That is always higher than 256 I've tested so far... AFAIK tighter timings should be better but... will my RAM work better with tRFC 256 or 288?

Baio


----------



## Baio73

So it happened again...

First run with Anta after OS reinstallation was ok, 1sumus made TM5 stuck again in endless loop:



I've tried this workaround as suggested by @The_King but got no luck:



> Edit: Useful commands to prevent / fix Data corruption. Run it from time to time from command prompt with ADMIN rights.
> SFC /scannow
> 
> DISM /Online /Cleanup-Image /CheckHealth
> DISM /Online /Cleanup-Image /ScanHealth
> DISM /Online /Cleanup-Image /RestoreHealth


I think I'm done with TM5, this software is a real mess...

Baio


----------



## The_King

Baio73 said:


> So it happened again...
> 
> First run with Anta after OS reinstallation was ok, 1sumus made TM5 stuck again in endless loop:
> 
> 
> 
> I've tried this workaround as suggested by @The_King but got no luck:
> 
> 
> 
> I think I'm done with TM5, this software is a real mess...
> 
> Baio


*If you think TM5 install has been corrupted. Delete the enitre TM5 folder and extract a new copy.*

GMD Disabled 1T with *DrvStr all @24 Ohms could also be an issue. I cant even both into windows with that and GDM disabled 1T.

Try 40 20 24 24 or 40 20 30 24. there are a few other combos.40 20 30 20.

Try leaving tCKE on Auto if its set manually to 1.

Lastly run all tRFC/2/4 with the all values set at 280 or 266.


----------



## ReyReverse

Baio73 said:


> So it happened again...
> 
> First run with Anta after OS reinstallation was ok, 1sumus made TM5 stuck again in endless loop:
> 
> 
> 
> I've tried this workaround as suggested by @The_King but got no luck:
> 
> 
> 
> I think I'm done with TM5, this software is a real mess...
> 
> Baio


Let me know your BIOS Agesa version


----------



## Valka814

Cant solve it by myself, so I ask the gurus for tips (again) .
If I change tFAW 16->24 and tRCDWR 20->18, a rare error #4 will come up.


----------



## ReyReverse

Valka814 said:


> Cant solve it by myself, so I ask the gurus for tips (again) .
> If I change tFAW 16->24 and tRCDWR 20->18, a rare error #4 will come up.
> View attachment 2566782


something wrong at your sub timings thats why got error
try set your sub timings to x8 mode.

tRRDS 4
tRRDL 6
tFAW 26


----------



## KedarWolf

Deleted.


----------



## KedarWolf

ReyReverse said:


> so envy~~~~you have a very good golden 5950x CPU chip this made you allow to run CsOdtDrvStr at 24 ohm.
> is this UEFI bios Agesa 1207?


AGESA 1.2.0.3C, that BIOS performs best in every benchmark I've tested.

VDIMM 1.51v, VTTs .770v

FFS, I had tRCDWR at 15. It'll pass at 14, I reloaded a BIOS profile, thought it was 14. Need to test again.


----------



## Bloax

Valka814 said:


> Cant solve it by myself, so I ask the gurus for tips (again) .
> If I change tFAW 16->24 and tRCDWR 20->18, a rare error #4 will come up.
> View attachment 2566782


#4 is an error caused either by things that make the DIMM unhappy (e.g. Park/1 instead of /2 or higher), or very wacky timings (suspects: WTR 3, WTRL 9, CWL 12, RRDS not being lower than RRDL)

The time per cycle is also noticeably higher (+10% over 440 seconds, seemingly almost 8 minutes per cycle?) than I would expect well-performing DDR4-3800 to require, so it's not performing very well.

Does tCL 16, tCWL 16, RCDWR 18, and RDWR 9 really not work, especially if you add WTRS 4 / WTRL 12 on top?
Because if it does, RRDS 4 would probably also work, at which point it would no longer look strange and unusual, likely also with a significant reduction in test cycle time.


----------



## ReyReverse

KedarWolf said:


> AGESA 1.2.0.3C, that BIOS performs best in every benchmark I've tested.
> 
> VDIMM 1.51v, VTTs .770v
> 
> FFS, I had tRCDWR at 15. It'll pass at 14, I reloaded a BIOS profile, thought it was 14. Need to test again.
> 
> View attachment 2566794


I prefer your last post addrcmdsetup 0 is good


----------



## Mappi75

Only a information for Zenith II Extreme Alpha users with bios 1603 :

i updated to this bios version and i got stabilty problems with my G.Skill 256GB 3600 CL16 Kit in TM5.

I could solve the problem:

VSOC: 1,05v (1,00625v looks working too)
VDDG IOD: 1,000v 

The main problem was VDDG IOD which i always leave on AUTO.

In windows was shown near 1,100v > i had to set it manually in bios to 1,000v and now the system runs perfect stable!

tested with:

tm5: 9+ hours
Adia64 Stresstest: 4+ hours
Karhu RAM test: 12+ hours 

Maybe someone could help this info


----------



## Audioboxer

Baio73 said:


> So it happened again...
> 
> First run with Anta after OS reinstallation was ok, 1sumus made TM5 stuck again in endless loop:
> 
> 
> 
> I've tried this workaround as suggested by @The_King but got no luck:
> 
> 
> 
> I think I'm done with TM5, this software is a real mess...
> 
> Baio


Your memory or CPU is not stable, it's not TM5. A new Windows installation passing once was likely just luck. You timed out on cycle 23 above, if you're only doing 25 cycles that shows you how close this time things were to it finishing and you thinking "this is stable!".

The app is not "smart enough", or sinister enough, to know it was due to finish in 2 more cycles so best fail here for a laugh  It errors when it errors if something is unstable.

Timeouts if its memory can often be powerdown issues or something minor, and they can be sporadic. Not enough voltage, incorrect resistances, memory temps if they hit a certain point, etc.

It's why a 50 cycle TM5 isn't a waste of time if you know your memory is right on the edge/being pushed to an extreme OC. I've had an error on cycle 46 before. It's what helped me see I needed CkeDrvStr 30, whereas 24 is usually the most common. It took that long (46 cycles) for a resistance issue to rear its head. It then took multiple more 50 runs for me to be satisfied I had dealt with it.... Welcome to memory OCing, it doesn't respect time!

For running 1T/GDM disabled, I do not trust much at all from your ProcODT down. As in, it could be any one of these resistances. You're on DR right, not 4x8GB? (just asking even though screen says DR). I wouldn't have RttNom disabled on DR at 3800 for a start.


----------



## Frosted racquet

Audioboxer said:


> Your memory or CPU is not stable, it's not TM5.


I don't know why people keep defending TM5 as if it's the holy grail of memory testing. I've had it hang on a completely stock, freshly installed system, not even running XMP. So far reproduced on a laptop and a desktop.
Suggesting people change various parameters and retest because of such a hang is simply a waste of time you could spent enjoying your stable OC


----------



## rissie

Finally decided to put these 3200 C16 b-die under water. These were the same sticks that let me to discover the AddrCmdSetup 56 setting that I'm glad many have found beneficial to run 1T. Rather rare PCB since it's the dominator platinum sticks with a rather high PCB. I needed to use notebook ram copper sheets to cover the memory modules else the water jackets won't come into contact with them. It seems to be working. Max temperature in an aircon room is 38C under TM5 load with these settings: 3800 CL13 @ 1.64V.



http://imgur.com/a/06NgYdu


----------



## Audioboxer

Frosted racquet said:


> I don't know why people keep defending TM5 as if it's the holy grail of memory testing. I've had it hang on a completely stock, freshly installed system, not even running XMP. So far reproduced on a laptop and a desktop.
> Suggesting people change various parameters and retest because of such a hang is simply a waste of time you could spent enjoying your stable OC


Just offering advice, Baio73 can run what they have and never run a test again. If that's the plan not like I can stop them lol. Run something like Karhu overnight and I bet they get an error, maybe even quicker than anything.

It goes without saying their situation is not your situation and given some of their settings on DR, I know enough to say with _some_ confidence their right hand side in ZenTimings with 1T/GDM disabled is likely to cause some issues.

And for what it's worth, I don't think TM5 is some holy grail or something, it's just one of the toughest free memory tests that can be run and it has a big community around it so a lot of help with what errors mean. If you're happy to spend money I'd probably recommend Karhu instead, although, like I just mentioned, diagnosing errors is a bit harder. But Karhu tends to be faster finding errors.


----------



## Bloax

finding errors quickly is meaningless unless you're going from Totally Stable into I Wanna Go Faster territory, as "what's wrong" is much more valueable information than "something is wrong"
blindly playing whack-a-mole is how you spend weeks trying every knob without progressing
only when you already know what's wrong (the thing you tried to go faster with) are speedy tests useful

All the times I've had TM5 crash hard have been due to things like uneven timings (tWR, WTRS, tRC is technically not a timing), or unstable CPU behaviour. (it's boosting real hard in that screenshot, for no gain)

If anything then you should count your blessings that 1T GDM off runs that stable with no procODT, RTT, CADBus or tCKE adjustments.
With almost any other memory kit, you'd be bluescreening within a minute with settings like that!

Instead _the only thing that happens_ is that TM5 hangs after a random amount of cycles, not the whole system going boom-boom.


----------



## va8888

Taraquin said:


> Try
> RRDS 6
> RRDL 8
> FAW 24
> WR 16
> RTP 8
> WTRS 4
> WTRL 12
> RFC 600
> RDRDSCL 4
> WRWRSCL 4
> Keep rest as is
> 
> See how that goes.


Hey there, thanks for the reply. I tested it and it looks stable. Benchmarks got a little better too. No micro-freezes and stutters so far either. No WHEA errors.

















I should mention that this boots after a very little plus voltage offset on the mobo (Gigabyte). I wonder If I can get to 3800 Mhz CL16 with a bigger offset and maybe 1.4V. ZenTiming says the VDIMM is 1.37V, as I set on the mobo, but HWMonitor says DRAM Volt at around 1.380V - 1.404V.


----------



## KedarWolf

For my 'safe' settings I can either do the below at 1T or tRCRD at 14 and 2T.

The 1T 15 performs better though in benchmarks so I stick with that.

Edit: The 1T 15 shaves 15 seconds off each cycle of TM5 over the 2T 14.


----------



## Ramad

Frosted racquet said:


> I don't know why people keep defending TM5 as if it's the holy grail of memory testing. I've had it hang on a completely stock, freshly installed system, not even running XMP. So far reproduced on a laptop and a desktop.
> Suggesting people change various parameters and retest because of such a hang is simply a waste of time you could spent enjoying your stable OC


TM5 is not a good program for testing.
Someone someday wanted to use a testing program that was not used here at OCN, so he looked up for a program that could show that his RAM is stable in 15 min. because testing RAM using any of Memtest Pro, Prime95, Y-cruncher, Linpack Xtreme, OCCT takes to long for his taste. 🤣 So he used TM5 and made a profile for it, and I remember that I wrote to him at that time that 15 min. is not enough time to test and not enough time for the RAM to reach the highest temperature at the desired RAM frequency, but he did not care, because he wanted his RAM to appear to be stable in 15 min. This is what happened. 

Members see a program that did not know about whith a profile that promises to make sure that the RAM is stable by running it for 15 min. so they rush for using it, and this is how TM5 is came to be at OCN. Now they try to run it for 20 cycles to make sure that their RAM is stable, which is around 2 hours, and I will never understand why testing with TM5 for 2 hours is better in any way than testing for 2 hours using Y-cruncher or Prime95.

My advice, and the way that I test, is to test the RAM outside the OS using Memtest86 by PassMark, they provide a version 4 at their site, which is old, and version 9 which is the latest. The free version 9 of Memtest86 has limited functionality. The best of the 2 worlds is version 7, which is free and is included in some Linux distros such as MX Linux. 4 cycles of tests 0 to 9 (don't need test 10 and 13) should be enough to tell if the RAM is stable. Don't worry, it will toast the RAM.  This is the RAM part.

The IMC/CPU part can be tested in Windows or Linux using Prime95, Y-cruncher...etc. Running any of these programs for 2 hours should be enough to determine if the system is stable. If errors appear at this stage, then it's most likely the IMC timings, IMC voltages or the CPU. To rule the CPU out, try running it using PBO and adding a little more voltage like 0.0125V.

If your system passes these tests, which will take around 3 hours then it's pretty stable.


----------



## KedarWolf

Ramad said:


> TM5 is not a good program for testing.
> Someone someday wanted to use a testing program that was not used here at OCN, so he looked up for a program that could show that his RAM is stable in 15 min. because testing RAM using any of Memtest Pro, Prime95, Y-cruncher, Linpack Xtreme, OCCT takes to long for his taste. 🤣 So he used TM5 and made a profile for it, and I remember that I wrote to him at that time that 15 min. is not enough time to test and not enough time for the RAM to reach the highest temperature at the desired RAM frequency, but he did not care, because he wanted his RAM to appear to be stable in 15 min. This is what happened.
> 
> Members see a program that did not know about whith a profile that promises to make sure that the RAM is stable by running it for 15 min. so they rush for using it, and this is how TM5 is came to be at OCN. Now they try to run it for 20 cycles to make sure that their RAM is stable, which is around 2 hours, and I will never understand why testing with TM5 for 2 hours is better in any way than testing for 2 hours using Y-cruncher or Prime95.
> 
> My advice, and the way that I test, is to test the RAM outside the OS using Memtest86 by PassMark, they provide a version 4 at their site, which is old, and version 9 which is the latest. The free version 9 of Memtest86 has limited functionality. The best of the 2 worlds is version 7, which is free and is included in some Linux distros such as MX Linux. 4 cycles of tests 0 to 9 (don't need test 10 and 13) should be enough to tell if the RAM is stable. Don't worry, it will toast the RAM.  This is the RAM part.
> 
> The IMC/CPU part can be tested in Windows or Linux using Prime95, Y-cruncher...etc. Running any of these programs for 2 hours should be enough to determine if the system is stable. If errors appear at this stage, then it's most likely the IMC timings, IMC voltages or the CPU. To rule the CPU out, try running it using PBO and adding a little more voltage like 0.0125V.
> 
> If your system passes these tests, which will take around 3 hours then it's pretty stable.


TM5 is the best test for finding if your RAM is the the least bit unstable. It'll find errors others won't

But I test with HCI MemTest Pro as well and even RAMTest and OCCT Gold or Platinum RAM tests, just to be thorough.

I find those are all easier to pass though then TM5.


----------



## KedarWolf

Completed in user 2 hours and 31 minutes.

I'm not sure why, but TM5 is faster on a traditional platter drive than a 7000+ read, 6000+ write Gen 4 M.2 drive.

Also, MemBench in DRAM Calculator is faster. I'm going to check y-cruncher too.


----------



## The_King

KedarWolf said:


> Completed in user 2 hours and 31 minutes.
> 
> I'm not sure why, but TM5 is faster on a traditional platter drive than a 7000+ read, 6000+ write Gen 4 M.2 drive.
> 
> Also, MemBench in DRAM Calculator is faster. I'm going to check y-cruncher too.
> 
> View attachment 2566865


With GDM disable 1T if you running TWR 10 then RTP should be 5 if its 6 you maybe loosing performance.

A few pages back i did a test with Y-cruncher with TWR/RTP 10/6 12/6 12/8.

12/6 turned out to be faster than 10/6.

Just something you can look at and test yourself.


----------



## KedarWolf

The_King said:


> With GDM disable 1T if you running TWR 10 then RTP should be 5 if its 6 you maybe loosing performance.
> 
> A few pages back i did a test with Y-cruncher with TWR/RTP 10/6 12/6 12/8.
> 
> 12/6 turned out to be faster than 10/6.
> 
> Just something you can look at and test yourself.


I was really hoping 12-6 it 10-5 would help. I loaded 12-6, rebooted, ran y-cruncher twice in a row, then once again a few minutes later after everything in Windows loaded, got the worse results. 

Tried 10-5, the same way, better than 12-6, but when I did the same thing with 10-6, got the best results, by over .200s.

I set the settings in the BIOS and redid all these steps three times.

Let me try AIDA64.

AIDA64 is inconclusive but seems 10-6 gets the best read/write and copy.


----------



## tommyd2k

I had to up my ram to 32GB from 16. So I had some 16GB T-force sticks I bought a while back because I thought they were B-die they turned out to be Micron so they just collected dust.
I managed 3800Mhz with em and I have been lowering the timings little by little. So far this is where im at. Anybody have any Micron advice? I know tRFC can't go much lower (did they make em 666 on purpose btw?) I think tWTRL-tWR can go down a bit. tRDRDSCL+tWRWRSCL possibly 4? tCWL 16, tRTP 6. tRDWR+tWRRD I dunno where those will land and the rest 1-4-4 1-5-5 maybe? I don't want to throw voltage at em and end up killing em. I upped the voltage to 1.360 to get 3800. The primaries will not go any lower, I was a little surprised latency was 60ns.









So my 16GB kit does 14-14-14 at 3800 1t GDM off and all subtimings basically as low as possible with a b-die kit. I also have another system with a pretty good B-die kit in it so I threw the 4 together in that system but I haven't tweaked it much yet. I know both kits are capable of 14-14-14 GDM off in my Dark hero build but not in my Aorus Master build. The only problem is I have a water block on my ram so I need another 2 blades to do it. Should I give it a try? One kit is 4000CL15 Ripjaws the other is 4500CL18 Tforce Xtreems. They should pair well together, I know I ran both kits with identical timings. I don't know if it's worth the effort though. I could just leave em in the other system and not bother.


----------



## The_King

tommyd2k said:


> I had to up my ram to 32GB from 16. So I had some 16GB T-force sticks I bought a while back because I thought they were B-die they turned out to be Micron so they just collected dust.
> I managed 3800Mhz with em and I have been lowering the timings little by little. So far this is where im at. Anybody have any Micron advice? I know tRFC can't go much lower (did they make em 666 on purpose btw?) I think tWTRL-tWR can go down a bit. tRDRDSCL+tWRWRSCL possibly 4? tCWL 16, tRTP 6. tRDWR+tWRRD I dunno where those will land and the rest 1-4-4 1-5-5 maybe? I don't want to throw voltage at em and end up killing em. I upped the voltage to 1.360 to get 3800. The primaries will not go any lower, I was a little surprised latency was 60ns.
> View attachment 2566882
> 
> 
> So my 16GB kit does 14-14-14 at 3800 1t GDM off and all subtimings basically as low as possible with a b-die kit. I also have another system with a pretty good B-die kit in it so I threw the 4 together in that system but I haven't tweaked it much yet. I know both kits are capable of 14-14-14 GDM off in my Dark hero build but not in my Aorus Master build. The only problem is I have a water block on my ram so I need another 2 blades to do it. Should I give it a try? One kit is 4000CL15 Ripjaws the other is 4500CL18 Tforce Xtreems. They should pair well together, I know I ran both kits with identical timings. I don't know if it's worth the effort though. I could just leave em in the other system and not bother.


With Micron ICs you get different speed grades as well has Rev. E and Rev. B which do not behave the same.

If you can use Thaiphooner burner and it correctly reads the IC then you can get some idea of what OC can be possible.

Some Micron ICs have no trouble doing 3800 RCD 17 others cant go below 3800 RCD 20/21/22.

These are Micron 16GB Rev. B (C9BLJ) Subtimings were not tuned left on Auto my Last OC with this KIT was not saved.


----------



## Baio73

The_King said:


> *If you think TM5 install has been corrupted. Delete the enitre TM5 folder and extract a new copy.*


Already tried, same result... only thing I changed, I editet the 1sumus config file to make it run 25 cycles...



> GMD Disabled 1T with *DrvStr all @24 Ohms could also be an issue. I cant even both into windows with that and GDM disabled 1T.
> 
> Try 40 20 24 24 or 40 20 30 24. there are a few other combos.40 20 30 20.


Tried all of them...40-20-24-24 and 40-20-30-24 TM5 still stuck, 40-20-30-20 trows errors (non at home ATM, can't remeber what errors).



> Try leaving tCKE on Auto if its set manually to 1.


I used to have it on Auto which resulted in 1, tried to set it to 1 but TM5 started to throw errors.



> Lastly run all tRFC/2/4 with the all values set at 280 or 266.


Next try, hope I'll make it this evening.

Baio


----------



## Baio73

ReyReverse said:


> Let me know your BIOS Agesa version


Thanks for your replay.
BIOS version is 801, so it should be AGESA v1.2.0.7.

Baio


----------



## Baio73

Audioboxer said:


> Your memory or CPU is not stable, it's not TM5. A new Windows installation passing once was likely just luck. You timed out on cycle 23 above, if you're only doing 25 cycles that shows you how close this time things were to it finishing and you thinking "this is stable!".
> 
> The app is not "smart enough", or sinister enough, to know it was due to finish in 2 more cycles so best fail here for a laugh  It errors when it errors if something is unstable.
> 
> Timeouts if its memory can often be powerdown issues or something minor, and they can be sporadic. Not enough voltage, incorrect resistances, memory temps if they hit a certain point, etc.
> 
> It's why a 50 cycle TM5 isn't a waste of time if you know your memory is right on the edge/being pushed to an extreme OC. I've had an error on cycle 46 before. It's what helped me see I needed CkeDrvStr 30, whereas 24 is usually the most common. It took that long (46 cycles) for a resistance issue to rear its head. It then took multiple more 50 runs for me to be satisfied I had dealt with it.... Welcome to memory OCing, it doesn't respect time!
> 
> For running 1T/GDM disabled, I do not trust much at all from your ProcODT down. As in, it could be any one of these resistances. You're on DR right, not 4x8GB? (just asking even though screen says DR). I wouldn't have RttNom disabled on DR at 3800 for a start.


Thanks for your replay,
What sound strange to me is this... if I set RAM (2x16 DR kit) @3800 CAS 14 GDM off leaving every other BIOS setting-RAM related to Auto (obviously apart from VDIMM), I'm 100% stable (TM5 25 cycles, Kharu RAM Test, normal Windows operations), the TM5 endlessly stuck problem pops out when lowering other timings. If you say I must pass 50 cycles of 1sumus I'm gonna try.
What setting do you advice me to try for ProcODT, resistances and RttNom?
I've made a couple of tries whit the valus @The_King suggested me, but no got no luck.

Baio


----------



## Baio73

Frosted racquet said:


> I don't know why people keep defending TM5 as if it's the holy grail of memory testing. I've had it hang on a completely stock, freshly installed system, not even running XMP. So far reproduced on a laptop and a desktop.
> Suggesting people change various parameters and retest because of such a hang is simply a waste of time you could spent enjoying your stable OC


Well, didn't mean to wake up a holy war on TM5... what sounds strange to me is that a testing software should not be supposed to hang without giving an error. I mean, BSOD, reboot of wathever a programmes wants, but it really SHOULD say "hey, I'm done".

I agree with you that passing 10000% of Karhu RAM Test and not having any BSOD or OS hangs in normal use should be enough to stop testing and start using a pc, but ATM I'm curious to find out the culprit of this strange behaviour.... maybe it's simething usefull for al the comunity.

Baio


----------



## Baio73

Bloax said:


> finding errors quickly is meaningless unless you're going from Totally Stable into I Wanna Go Faster territory, as "what's wrong" is much more valueable information than "something is wrong"
> blindly playing whack-a-mole is how you spend weeks trying every knob without progressing
> only when you already know what's wrong (the thing you tried to go faster with) are speedy tests useful
> 
> All the times I've had TM5 crash hard have been due to things like uneven timings (tWR, WTRS, tRC is technically not a timing), or unstable CPU behaviour. (it's boosting real hard in that screenshot, for no gain)
> 
> If anything then you should count your blessings that 1T GDM off runs that stable with no procODT, RTT, CADBus or tCKE adjustments.
> With almost any other memory kit, you'd be bluescreening within a minute with settings like that!
> 
> Instead _the only thing that happens_ is that TM5 hangs after a random amount of cycles, not the whole system going boom-boom.


Don't know if you was referring to me with this post... if so, I'd be happy to try any BIOS values combination you'll suggest me.

Baio


----------



## ReyReverse

Baio73 said:


> Thanks for your replay.
> BIOS version is 801, so it should be AGESA v1.2.0.7.
> 
> Baio


Agesa 1207 use 40-20-30-24 (alt 60-20-30-24)
And set ProcODT 34 or 36.9ohm
RTT you need take time to try one by one, 7-3-7 is idea 
Current
Bios set
Cldo Vddp try 902
CCD try 902 or 952
IOD try 1052
Then 1.8 PLL idea start from 1.85v (alt 1.9v or 1.93v up to 2.0v)

Remember Choose windows power plan - High performance

Good luck


----------



## Audioboxer

Baio73 said:


> Thanks for your replay,
> What sound strange to me is this... if I set RAM (2x16 DR kit) @3800 CAS 14 GDM off leaving every other BIOS setting-RAM related to Auto (obviously apart from VDIMM), I'm 100% stable (TM5 25 cycles, Kharu RAM Test, normal Windows operations), the TM5 endlessly stuck problem pops out when lowering other timings. If you say I must pass 50 cycles of 1sumus I'm gonna try.
> What setting do you advice me to try for ProcODT, resistances and RttNom?
> I've made a couple of tries whit the valus @The_King suggested me, but no got no luck.
> 
> Baio


It's likely one of the secondary timings then and/or the combination of how tight you're trying to run some of those settings and the resistances.

At this point the only way to handle this properly is testing secondary timings one after the other. There really are no shortcuts with memory OCing unless you want to waste a lot time.










This is what I run on DR. 7/3/3 on Rtts tends to be a decent starting point. Your ProcODT can likely come down to around 36.9 to start with. I'd run DrvStrs something like 40/20/24/24 or 40/24/24/24 to play around with. Most of us cannot run 1T GMD disabled on DR without using the setup time 56.

But the thing is with memory it's all on you to find out what works. For example, my best advice is to begin on 2T and do your primaries and secondaries first. 2T usually cares less about the resistances, it's often 1T that brings them into play. If you're trying to do 1T and all your secondary timings at the same time, it's a total YOLO. If you don't error, great, you've effectively gambled on a shortcut. If you do have an error you basically have no idea what is causing it because you're working back the way now, rather than starting from a clean slate and going step by step.


----------



## FxMotion

Ran TM5 with the absolut config overnight, and ran into an error. Error on test 6. Apparently a standalone error 6 is related to the IMC and can mean "too much voltage." 

I have voltage manually set to 1.5 along with manually setting VDDP, CCD, and IOD (as well as SOC). Values in screenshot. When I setup this overclock, I followed a recommended 40mV stepping. 

Only timings have been manually changed, I have not manually changed ProcODT, any of the RTTs or the DrvStr values. 

I am running a 4x8 kit from Corsair: CMW16GX4M2Z4000C16 and I am fairly certain this is B-Die, as it's listed in the B-Die Finder site, how accurate that finder site is I have no idea. 

Any thoughts on this? Do I need to start playing around with ProcODT and the RTTs?


----------



## KedarWolf

FxMotion said:


> Ran TM5 with the absolut config overnight, and ran into an error. Error on test 6. Apparently a standalone error 6 is related to the IMC and can mean "too much voltage."
> 
> I have voltage manually set to 1.5 along with manually setting VDDP, CCD, and IOD (as well as SOC). Values in screenshot. When I setup this overclock, I followed a recommended 40mV stepping.
> 
> Only timings have been manually changed, I have not manually changed ProcODT, any of the RTTs or the DrvStr values.
> 
> I am running a 4x8 kit from Corsair: CMW16GX4M2Z4000C16 and I am fairly certain this is B-Die, as it's listed in the B-Die Finder site, how accurate that finder site is I have no idea.
> 
> Any thoughts on this? Do I need to start playing around with ProcODT and the RTTs?
> 
> View attachment 2566919


With Absolute you can't go by the error check sheets I think. I think it's an ANTA and the error numbers are not the same as 1usmus_v3.


----------



## FxMotion

KedarWolf said:


> With Absolute you can't go by the error check sheets I think. I think it's an ANTA and the error numbers are not the same as 1usmus_v3.


Ah, this makes sense. Do you know if there's a list of errors and meanings for ANTA floating around out there?


----------



## FxMotion

FxMotion said:


> Ah, this makes sense. Do you know if there's a list of errors and meanings for ANTA floating around out there?


Actually, I think I found it: Ryzen Google Calculator! - Google Sheets

Supposedly, Error 6 is: "Interface ("digital" timings): tBL,tCL,tRTP,CCDS,CCDL,CWL,WPRE,RPRE"


----------



## tommyd2k

The_King said:


> With Micron ICs you get different speed grades as well has Rev. E and Rev. B which do not behave the same.
> 
> If you can use Thaiphooner burner and it correctly reads the IC then you can get some idea of what OC can be possible.
> 
> Some Micron ICs have no trouble doing 3800 RCD 17 others cant go below 3800 RCD 20/21/22.
> 
> These are Micron 16GB Rev. B (C9BLJ) Subtimings were not tuned left on Auto my Last OC with this KIT was not saved.
> View attachment 2566884


So here is the report from Thaipoon. The 083E means E-die correct? Looking at this spreadsheet I see Micron E has more potential than I thought. I see you were using 1.45v, I didn't want to turn up the voltage without asking what a safe limit is on these. It looks like they have some potential room for more tuning on the primaries. I see you had a pretty high tRFC, was that the default setting? And what was the default Voltage on that kit? Is there any timings that I should watch for negative scaling with voltage? I'm looking forward to seeing how it goes now.


----------



## tommyd2k

I confirmed that these will not take tRCD's lower than 22, at least not at 1.4v. At 1.4v, tCL 16 posts, but I got 2 errors at the end of a 1usmus tm5 test. I will visit that one again once I confirm a safe limit for these sticks.. Also, in your zentimings screenshot does it say 16GB SR as in single rank? I didn't know they made single rank 16GB sticks, did they just start recently?


----------



## The_King

tommyd2k said:


> I confirmed that these will not take tRCD's lower than 22, at least not at 1.4v. At 1.4v, tCL 16 posts, but I got 2 errors at the end of a 1usmus tm5 test. I will visit that one again once I confirm a safe limit for these sticks.. Also, in your zentimings screenshot does it say 16GB SR as in single rank? I didn't know they made single rank 16GB sticks, did they just start recently?


The Crucial Ballistix Max 4400 16GBX2 should all be SR. AFAIK

Your kit seems to be Rev. E. Although Thaiphoon burner seems unsure (??)

CL16 with two errors should not be to hard to get working.
Its important to note the exact error so that you can troubleshoot what value to change.

WIth Micron RCD does not scale with Voltage like how it does with Samsung B-die.









tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com


----------



## ludovicoleone

I did this tightening to my rams. 2X16 DDR4 3600 GTZNC. Tested it, no problems at all. But does anyone have any idea or suggest going far more?


----------



## KedarWolf

ludovicoleone said:


> I did this tightening to my rams. 2X16 DDR4 3600 GTZNC. Tested it, no problems at all. But does anyone have any idea or suggest going far more?
> View attachment 2566946


They are not -b-die so tight timings are not going to happen. 2x16 16-16-16-36 3600 are b-die but yours are 16-19-19-39 and Hynix I think.


----------



## The_King

KedarWolf said:


> They are not -b-die so tight timings are not going to happen. 2x16 16-16-16-36 3600 are b-die but yours are 16-19-19-39 and Hynix I think.


It is not B-die you can tell that because the model number ends GTZNC = if there is a C at the end on G.Skill RAM it is almost never B-die.
Guaranteed B-die with G.SKill will have 8810B on sticker. You can identify your IC using the chart below.









3800 CL16-19-19-19 may work with the right voltage and also give some decent performance you may need VDIMM 1.45V-1.48V.


----------



## tommyd2k

The_King said:


> The Crucial Ballistix Max 4400 16GBX2 should all be SR. AFAIK
> 
> Your kit seems to be Rev. E. Although Thaiphoon burner seems unsure (??)
> 
> CL16 with two errors should not be to hard to get working.
> Its important to note the exact error so that you can troubleshoot what value to change.
> 
> WIth Micron RCD does not scale with Voltage like how it does with Samsung B-die.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com


What I keep running into with these is they don't produce an error early, they happen after like 30 40 minutes. It's making testing take forever to do it right. I had to start over because I gotta run an hour of the 1usmus test between adjustments. They were ok going from 3600 to 3800 without any extra voltage. So isn't it odd that I can't lower tCL or tRCD at all? I tried with an extra 100mv and gave up for the night when TM5 gave me an error 0 in cycle 7 almost 50 min in. I think I am gonna order the extra blades for the DDR block and run my 4x8GB B-die in this system and put these ones in my living room computer. That makes the most sense really... Besides, I don't have the factory spreaders for one of the kits anyways.


----------



## Luggage

Ramad said:


> TM5 is not a good program for testing.
> Someone someday wanted to use a testing program that was not used here at OCN, so he looked up for a program that could show that his RAM is stable in 15 min. because testing RAM using any of Memtest Pro, Prime95, Y-cruncher, Linpack Xtreme, OCCT takes to long for his taste. 🤣 So he used TM5 and made a profile for it, and I remember that I wrote to him at that time that 15 min. is not enough time to test and not enough time for the RAM to reach the highest temperature at the desired RAM frequency, but he did not care, because he wanted his RAM to appear to be stable in 15 min. This is what happened.
> 
> Members see a program that did not know about whith a profile that promises to make sure that the RAM is stable by running it for 15 min. so they rush for using it, and this is how TM5 is came to be at OCN. Now they try to run it for 20 cycles to make sure that their RAM is stable, which is around 2 hours, and I will never understand why testing with TM5 for 2 hours is better in any way than testing for 2 hours using Y-cruncher or Prime95.
> 
> My advice, and the way that I test, is to test the RAM outside the OS using Memtest86 by PassMark, they provide a version 4 at their site, which is old, and version 9 which is the latest. The free version 9 of Memtest86 has limited functionality. The best of the 2 worlds is version 7, which is free and is included in some Linux distros such as MX Linux. 4 cycles of tests 0 to 9 (don't need test 10 and 13) should be enough to tell if the RAM is stable. Don't worry, it will toast the RAM.  This is the RAM part.
> 
> The IMC/CPU part can be tested in Windows or Linux using Prime95, Y-cruncher...etc. Running any of these programs for 2 hours should be enough to determine if the system is stable. If errors appear at this stage, then it's most likely the IMC timings, IMC voltages or the CPU. To rule the CPU out, try running it using PBO and adding a little more voltage like 0.0125V.
> 
> If your system passes these tests, which will take around 3 hours then it's pretty stable.


The one thing TM5 has going for it is the work @Veii (and others?) put in to the error sheet for 1usmus profile giving you at least a hint about what settings are unstable.

Thinking you can be stable with 15min testing, yea no that’s a pipe dream.


----------



## The_King

tommyd2k said:


> What I keep running into with these is they don't produce an error early, they happen after like 30 40 minutes. It's making testing take forever to do it right. I had to start over because I gotta run an hour of the 1usmus test between adjustments. They were ok going from 3600 to 3800 without any extra voltage. So isn't it odd that I can't lower tCL or tRCD at all? I tried with an extra 100mv and gave up for the night when TM5 gave me an error 0 in cycle 7 almost 50 min in. I think I am gonna order the extra blades for the DDR block and run my 4x8GB B-die in this system and put these ones in my living room computer. That makes the most sense really... Besides, I don't have the factory spreaders for one of the kits anyways.


No heat spreader could mean the RAM overheating.

Try TWR 20 RTP 10. 
It could possibly increase heat tolreance with not much impact on performance.

What voltage are you running for the 3600/3800?


----------



## ludovicoleone

KedarWolf said:


> They are not -b-die so tight timings are not going to happen. 2x16 16-16-16-36 3600 are b-die but yours are 16-19-19-39 and Hynix I think.


Yes you are right sir. It has Hynix DJR.


----------



## Baio73

Baio73 said:


> The_King said:
> 
> 
> 
> Lastly run all tRFC/2/4 with the all values set at 280 or 266.
> 
> 
> 
> Next try, hope I'll make it this evening.
> 
> Baio
Click to expand...

Tried, but TM5 got stuck @ cycle 20.

Bao


----------



## ioannis91

What is your opinion on Karhu Test? I remember on one occasion it threw an error pretty quickly (around the half hour mark) while 20 cycles TM5 and 400% memtest were stable.


----------



## SneakySloth

ioannis91 said:


> What is your opinion on Karhu Test? I remember on one occasion it threw an error pretty quickly (around the half hour mark) while 20 cycles TM5 and 400% memtest were stable.


Karhu is okay but I think TM5 with different profiles/Y-cruncher/Memtest Pro/ OCCT Memory and Large FFT are better.


----------



## Baio73

ioannis91 said:


> What is your opinion on Karhu Test? I remember on one occasion it threw an error pretty quickly (around the half hour mark) while 20 cycles TM5 and 400% memtest were stable.


Don't know if you read my last posts on TM5 getting stuck in endless loop... never happened with Karhu to me.
I must say that probably TM5 is a more "flexible" software, as it gives you an error number through which you have an idea of what BIOS value is the culprit of test failing, when Karhu just stops telling you "1 error found".
And probably TM5 stresses RAM way too much then Karhu... in my rig TM5 keeps getting stuck and Karhu runs 10000% without errors, but I keep wondering if the the worst case scenario TM5 represents is a possible scenario in a normal-use pc.
Hope it may help!

Baio


----------



## M$<3OpenSource

Hello guys, I read all kinds of guides and experimented several times, but I can't seem to get latency much lower... Everything is pretty tightened up with exception to tRDWR and tWRRD tertiaries. I have gotten tWRRD to 1 but in testing going any lower on them doesn't help. Lower tRDWR doesn't post (I get the magic formula tCL - tCWL + tRDWR = 8, lower is a nono).
tRC is lowest possible currently - 52 immediately BSODs.
tRCD to 19 BSOD.
I can get tRFC to 240ns but I have relaxed it a bit to help me with testing the others, so I don't redline it in the heat and get random temperature errors throwing me off.
I have gotten to a bit lower than 70ns with slower C-die RAM, so I am puzzled how ppl get like 5ns lower than my latency with a similar or more relaxed OC.

Does anyone have any suggestions I can make?
Build is 2x16GB Hynix DJR, MSI B550 Tomahawk and R5 3500X.

EDIT: Got SCLs to 2, only L3 latency got 0.3ns faster.


----------



## koala7

nvm


----------



## slayer1991

koala7 said:


> anyone here ever experience having lower oc after bios reset to stock?
> my cpu before runs at 1900 fclk but after reset it can boot at 1867 max
> is this degradation happening? is there bios setting that can affect this?
> my bios at 1900 fclk was agesa 1207
> even after downgrading to agesa 1203b still cant boot at 1900 fclk
> what can i do to get back at 1900? pls help


How long have you been running at what voltages?
Degradation is possible, I ran into it even on the old FX-8350 with a static OC and ram timings.

One thing to check is all the manual voltages that need to be set, which resetting bios would put them all on auto.
That is vSOC, v1.8whatever-its-called, VDDP, cLDO VDDP, VDDG CCD/IOD, and the LLC settings (maybe a Level 2 or mid range for your mobo) as they would all affect Infinity Fabric OC.


----------



## slayer1991

I see a lot of B-die timing WR/RTP set to 12/8 for zen2 on the community spreadsheet, it seems to allow them to drop CWL to 14 and gain a whole bunch of latency from there on.

Is the WR=2xRTP not an important rule to follow?
My B-die is not the best bin, as an early adopter in 2017. It's on A1 PCBs (according to Taiphoon), but can pass even 100 cycles of TM5 with those timings set at 10/5.

Another thing I noticed is the higher procODT and Rtt settings, around 34ohm 0/0/5.
From what I understand so far, those should help with stability.

On the other hand, decreasing them to something like 30ohm 7/3/5 would allow tighter timings but may not end up being stable.
Impedance matching would reduce signal reflections, and should reduce heat production, correct?


----------



## domdtxdissar

slayer1991 said:


> Is the WR=2xRTP not an important rule to follow?
> My B-die is not the best bin, as an early adopter in 2017. It's on A1 PCBs (according to Taiphoon), but can pass even 100 cycles of TM5 with those timings set at 10/5.


You can visually inspect your to memory to determine what PCB type you have.


----------



## deedeeDMT

If there any real difference between 1.52v and 1.5 volts in ram cooling requirements? Current 4x8 set only does 3800 cl14 at 1.52v since 1.5v gives low Dram voltage errors. I ran both voltages stress tested under a fan. Is there any way to lower the Dram voltage any further at 3800 cl14 or is it like a hardwall kind of thing?


----------



## Dams07

Hi all,

I have a 3600c14 32GB kit (bdie) and i have severals questions :

1. I see for better stability, I can set tRAS = tRCD*2 + tCCD_L. But what is it tCCD_L, I don't see this timing in ZenTimings ?

2. In this table what is the best tcke range for DR with MCLK 1867 ? It is the alternative value : 7 ?









Thank you very much !


----------



## Bloax

EDIT: lol apparently that's what rdrd wrwr SC and SCL are about (CCD, CCDL) thanks
no i don't fix myself being wrong in public who do you think i am

tCCD_L is not a timing available to be set on AM4, but you can presume that it's 8 as that's usually what it is unless you're running low (less than DDR4-3200) frequencies with JEDEC standard timings.








here it is on a msi z690-a pro ddr4

In my experience then tCKE wants to go up by +2 strictly every multiple of 100, even so far as throwing occasional errors at 9/1900 MCLK if your BCLK droops to 99.8 - as that causes 1900 MCLK to drop to 1896, and you solve this by setting BCLK to 100.1 or something where it won't droop below 1900 MCLK.


I should also note that "for better stability" is code word for "if nothing else works", as usually tRAS = tCL+tRCD is more than stable enough.


----------



## M$<3OpenSource

deedeeDMT said:


> If there any real difference between 1.52v and 1.5 volts in ram cooling requirements? Current 4x8 set only does 3800 cl14 at 1.52v since 1.5v gives low Dram voltage errors. I ran both voltages stress tested under a fan. Is there any way to lower the Dram voltage any further at 3800 cl14 or is it like a hardwall kind of thing?


It all depends on your build. If you can run at 1.52V but can't at 1.5V, then that's the voltage it needs. Voltage requirements also depend on things like your secondary timings and your ProcODT/RTT/CAD settings. You may be able to run lower if you relax subtimings and/or use lower termination settings. If those don't work then you definitely need the voltage.


----------



## hazium233

slayer1991 said:


> My B-die is not the best bin, as an early adopter in 2017. It's on A1 PCBs (according to Taiphoon)


You probably figured it out based on dom's post, but otherwise G.Skill single rank from 2017 would be A0 for non-RGB, or A2 if RGB. I don't believe they started putting more of the non-RGB kits on A2 until midway through 2019, or early 2020. From your part number, would imagine you have A0.

They went through multiple revisions of PCBs, the 2017 Flare X set I had was on an A0 without revision markings. The 2018 and 2019 3600C15 sticks I had on A0 were marked "SD."

I don't believe G.Skill ever actually used an A1 for any of the single rank B-die, despite thaiphoon often reporting that.



Dams07 said:


> 1. I see for better stability, I can set tRAS = tRCD*2 + tCCD_L. But what is it tCCD_L, I don't see this timing in ZenTimings ?


tRDRDSCL and tWRWRSCL are the AMD stand ins for tCCD_L, although for some reason they are offset by 3t (just like tRDRDSC and tWRWRSC which stand in for CCD_S). So auto xSCL 5t = CCD_L 8t.

I think the CCD_L reported in thaiphoon was being used in the formula, which is just coming from base SPD.

You can probably push tRAS much lower than what you get from that. Probably simplest to set tRAS = tRC - tRP initially.

There are differing opinions on how tRAS works (or doesn't) on AM4 though. Best idea is just test and see what works for you.


----------



## slayer1991

hazium233 said:


> You probably figured it out based on dom's post, but otherwise G.Skill single rank from 2017 would be A0 for non-RGB, or A2 if RGB. I don't believe they started putting more of the non-RGB kits on A2 until midway through 2019, or early 2020. From your part number, would imagine you have A0.
> 
> They went through multiple revisions of PCBs, the 2017 Flare X set I had was on an A0 without revision markings. The 2018 and 2019 3600C15 sticks I had on A0 were marked "SD."
> 
> I don't believe G.Skill ever actually used an A1 for any of the single rank B-die, despite thaiphoon often reporting that.


Thanks for the intel! It's a little hard accessing my rig hidden under an ikea drawer cabinet.

Lots of messing around, even angled down the 1st fan on the NH-D15 cooler to blow on the RAM, got some -5*C difference.
Error #10 was triggered by both too high or too low VDIMM, 1.43v worked just fine.

But in the end I landed on these timings, which passed 25 cycles with no errors!
I will try to bring down the SCLs, and some other Rtt combinations. I wonder if a 3600x can hit 2000MHz on the Infinity Fabric


----------



## Frosted racquet

Okay, who used their microwave oven while I was testing?
Joking aside, started retesting my RAM settings from May, since it's +8°C hotter now and I'm getting random errors.

First, there was a single error 6 after 20+ cycles, changed the Rtt's from default to 7/3/3 and DrvStr to 24-20-24-24 from flat 20's.
Next, getting a single error 0 and 2 after 20+ cycles, changed tRTP and tWR from 5/10 to 6/12 and passed 100 cycles. (attached)
Rebooted, and retested the same settings and now a single error 0 at around 20 cycles. RAM temps are ~61°C max.
Suggestions?


----------



## Dams07

Bloax said:


> tCCD_L is not a timing available to be set on AM4, but you can presume that it's 8 as that's usually what it is unless you're running low (less than DDR4-3200) frequencies with JEDEC standard timings.
> View attachment 2567208
> 
> here it is on a msi z690-a pro ddr4
> 
> In my experience then tCKE wants to go up by +2 strictly every multiple of 100, even so far as throwing occasional errors at 9/1900 MCLK if your BCLK droops to 99.8 - as that causes 1900 MCLK to drop to 1896, and you solve this by setting BCLK to 100.1 or something where it won't droop below 1900 MCLK.
> 
> 
> I should also note that "for better stability" is code word for "if nothing else works", as usually tRAS = tCL+tRCD is more than stable enough.


Thank you for your reply.

In fact I am running 3733mhz / 1867 MCLK because more than that I have some WHEA 19 with my 5950x and my gigabyte x570s aorus elite AX...

So with this table above, I am wondering if the optimal value is on the left for SR and on the right for DR (because there is a "~DR" on the top right) ?










What is the best : tCKE 8 or 7 at 3733mhz for DR kit ?

Thank you !


----------



## Bloax

As with all things Memeory, it's a matter of trying it out on your setup and seeing which works out.
In my experience, it would be 7 -- as it starts at 7 @ 1800 MCLK (the "mhz" value is twice the value of MCLK), still stays 7 at 1600 MCLK, but requires 9 at 1900, 11 at 2000, 13 at 2100 ..

When trying in-between values like 12 at 2070 MCLK, I got nothing but errors related to a wrong tCKE (minor timeouts like #1, #2, #5 #10, #12, if you let it run long enough it'd eventually print a #4 for "wrong tCKE")

Yet, evidently, this is just my experience - and working examples of in-between tCKE values were seen to print them there.
tCKE is also oddly -1 of the "expected" value on LGA1151, just as some timings like rdrd_sg and wrwr_sg


----------



## PJVol

@Veii
Hey, what's up man? I'm getting close in a TSE Leaderboard
(from ahead )


----------



## Prophet4NO1

Does anyone else us rainmeter for real time monitoring? I have a few things displayed and I noticed that if I turn off rainmeter that I drop about 10ns on my memory latency on aida64. Leaving HWinfo running, that my rainmeter skin uses for data collection, has no impact. But as soon as I fire up rainmeter again it goes from 56-57ns up to about 65-67ns. Bandwidth seems about the same across the board. Any thoughts or is there maybe something funky with my skins causing this? Does not seem to effect real world performance at all. Just curious since it is a measurable effect when benching. It also explains why my latency has been such a pain to get down to similar spec ram others have posted here.


----------



## The_King

Prophet4NO1 said:


> Does anyone else us rainmeter for real time monitoring? I have a few things displayed and I noticed that if I turn off rainmeter that I drop about 10ns on my memory latency on aida64. Leaving HWinfo running, that my rainmeter skin uses for data collection, has no impact. But as soon as I fire up rainmeter again it goes from 56-57ns up to about 65-67ns. Bandwidth seems about the same across the board. Any thoughts or is there maybe something funky with my skins causing this? Does not seem to effect real world performance at all. Just curious since it is a measurable effect when benching. It also explains why my latency has been such a pain to get down to similar spec ram others have posted here.


Anything that uses CPU cycles will affect latency even having an active internet connection.


----------



## Prophet4NO1

The_King said:


> Anything that uses CPU cycles will affect latency even having an active internet connection.



I get that. Not my first day here. It just seems odd that rainmeter on it's own has a pretty large impact on latency. I do not get much faster in testing in safe mode with no network connection compared to just shutting rainmeter off. I have slimmed down windows to 75-80 processes running after boot. So, not a ton going on. Not a lot more I can strip out, really. It just seems odd that rainmeter is so impactful.


----------



## shnyaps

Is 1.57V good for Hunix MJR with water cooling?


----------



## KedarWolf

shnyaps said:


> Is 1.57V good for Hunix MJR with water cooling?
> View attachment 2567372


Please lower that VSOC to 1.2v or lower. You're going to destroy your IMC.


----------



## ldclopes

Hi guys!

I'm looking for some advice...

First, specs:
Ryzen 7 5800X3D. ASUS TUF B550M Plus Wifi.
2xTF10D416G3600HC14CDC01 (4x8GB Team Group Xtreem ARGB, XMP is 3600MHz CL14-15-15-35 1.45V). DeepCool AK620. Corsair CX550.

I'm having some trouble running at XMP settings, let alone overclock it. I can boot with 3600MHz but it isn't stable. I was able to change some settings from stock XMP and ran it for more time before gettings errors, but it still fails after less than a hour of testing.

I tried that:








2T with GDM disabled gave me even worse results. 1.1v SOC also did not helped.

Those are the XMP settings with everything on auto, also not stable.









Some people in other forum argued that it may not be possible to run 3600MHz with 4 memory sticks. So I lowered it to 3466MHz and it was "stable" (~2 hours on TM5 and ~4 hours on OCCT) , on those settings:










But can't it really go to 3600MHz (or higher)?Are 4 SR sticks so limiting?

I'm not exactly new to it, but the last time I overclocked RAM was on Phenom II systems, so I'm a bit outdated haha.
Suggestions?


----------



## shnyaps

KedarWolf said:


> Please lower that VSOC to 1.2v or lower. You're going to destroy your IMC.


It is zen timings bug. My vsoc is 1.13


----------



## Bloax

ldclopes said:


> Some people in other forum argued that it may not be possible to run 3600MHz with 4 memory sticks.


Some people tend to be rather clueless, as given the right DIMM choice and configuration, it should be possible to run 4x8 until your memeory controller bends over backwards.








I like to bring up mongoled's little 4x viper 4400 setup in AM4 land, it's pretty nice.

On my own LGA1700 setup, I've had 4x8 4200 15-15-15 POST - but due to either a memory controller weakness, or poor memory interface pin contact (will have to test with a good LGA1700 contact frame), it refuses to behave stable above DDR4-3840ish. Does do 4x8 3828 13-13-13 with some coercion though!
The same stick setup also just POSTed 4x8 3828 12-12-12, but once again this same problem of "inexplicable, unchangeable instability" came up. 

For 4x8 to behave properly, procODT/RTT/CADBus tomfoolery becomes unavoidable, and I think I may have written something about how to methodically wrangle it out here








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


I thought you've learned it in a discussion with truly yours That discussion didn't explain the abbreviation as well as exact meaning. But it was pretty close :)




www.overclock.net




but my memeory is fuzzy right meow. Might be useful to catch up to speed on the recent DDR4 OC meta?

If someone has a better description of what the hell those things do than my vague connect-the-dots mental tangleweb here, I'd be thankful; MSI B450 RAM Upgrade advice needed


----------



## shnyaps

ldclopes said:


> Hi guys!
> 
> I'm looking for some advice...
> 
> First, specs:
> Ryzen 7 5800X3D. ASUS TUF B550M Plus Wifi.
> 2xTF10D416G3600HC14CDC01 (4x8GB Team Group Xtreem ARGB, XMP is 3600MHz CL14-15-15-35 1.45V). DeepCool AK620. Corsair CX550.
> 
> I'm having some trouble running at XMP settings, let alone overclock it. I can boot with 3600MHz but it isn't stable. I was able to change some settings from stock XMP and ran it for more time before gettings errors, but it still fails after less than a hour of testing.
> 
> I tried that:
> View attachment 2567374
> 
> 2T with GDM disabled gave me even worse results. 1.1v SOC also did not helped.
> 
> Those are the XMP settings with everything on auto, also not stable.
> View attachment 2567375
> 
> 
> Some people in other forum argued that it may not be possible to run 3600MHz with 4 memory sticks. So I lowered it to 3466MHz and it was "stable" (~2 hours on TM5 and ~4 hours on OCCT) , on those settings:
> 
> View attachment 2567376
> 
> 
> But can't it really go to 3600MHz (or higher)?Are 4 SR sticks so limiting?
> 
> I'm not exactly new to it, but the last time I overclocked RAM was on Phenom II systems, so I'm a bit outdated haha.
> Suggestions?


I have 4x32gb with fclk 1900Mhz, mem is 3800Mhz


----------



## ldclopes

Bloax said:


> Some people tend to be rather clueless, as given the right DIMM choice and configuration, it should be possible to run 4x8 until your memeory controller bends over backwards.
> View attachment 2567388
> 
> I like to bring up mongoled's little 4x viper 4400 setup in AM4 land, it's pretty nice.
> 
> On my own LGA1700 setup, I've had 4x8 4200 15-15-15 POST - but due to either a memory controller weakness, or poor memory interface pin contact (will have to test with a good LGA1700 contact frame), it refuses to behave stable above DDR4-3840ish. Does do 4x8 3828 13-13-13 with some coercion though!
> The same stick setup also just POSTed 4x8 3828 12-12-12, but once again this same problem of "inexplicable, unchangeable instability" came up.
> 
> For 4x8 to behave properly, procODT/RTT/CADBus tomfoolery becomes unavoidable, and I think I may have written something about how to methodically wrangle it out here
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> I thought you've learned it in a discussion with truly yours That discussion didn't explain the abbreviation as well as exact meaning. But it was pretty close :)
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> but my memeory is fuzzy right meow. Might be useful to catch up to speed on the recent DDR4 OC meta?
> 
> If someone has a better description of what the hell those things do than my vague connect-the-dots mental tangleweb here, I'd be thankful; MSI B450 RAM Upgrade advice needed


Hi. Thank you for the detailed answer, it is very helpfull 
Yeah, it all sounded very strange to me, 4 sticks should be a little harder but not impossible.
I guess I haven't tried hard enough then. I'll play a bit with the procODT/RTT/CADBus as you described in that other post of yours.


----------



## Blackfyre

ldclopes said:


> Hi. Thank you for the detailed answer, it is very helpfull
> Yeah, it all sounded very strange to me, 4 sticks should be a little harder but not impossible.
> I guess I haven't tried hard enough then. I'll play a bit with the procODT/RTT/CADBus as you described in that other post of yours.


First, to answer your previous question. The people who had issues achieving 3600Mhz or higher weren't on Zen 3 or X570 boards I believe.

Second, I don't even need to play with procODT/RTT/CADBus to achieve 3800Mhz on my 4 x 8Gb Micron e-die sticks; depends on motherboard, memory controller, and luck. In fact, I set them all the lowest resistance values, as you can see my ZenTimings. *Setting them to the lowest resistance produces the least amount of heat*. If you can run them at these values below (in the yellow box), then do that. Some motherboards & memory controllers can't do that though and need higher resistance:


----------



## zerophase

Trying to tighten timings some more on a 3990x running B-die. (F4-4000C15Q-32GTRG) I'm on the 1900 flck. (took a bit to get this booting) I was not getting into the post tests with VDIMM at 1.45, and raising it to 1.5 fails on various tests, (different test each time.) but gets further. Current timings are 16-20-20-20. Trying to hit at least 14 CAS. Any tips for tightening from here? Should I try loosening secondaries and tertiaries?

SOC: 1.125
CCD: 1
IOD: 1
VDDP: 0.992
ProcODT: 43.6
RttNom: RZQ/7
RttWr: Dynamic ODT Off
RttPark: RZQ/5
CadBusClkDrvStren: 24
CadBusAddrCmdDrvStren: 20
CadBusCsOdtDrvStren: 24
CadBusCkeOdtDrvStren: 24


----------



## slayer1991

I found my Bdie to not like a lower tCWL than tCL, and tWR = 2x tRTP all the way down to 12/6.
Also, there was a sweetspot for VDIMM, where too much or too little would cause errors in TM5.

Might be able to drop cLDO VDDP to 0.9v, and VDDG CCD to 0.95
Try flat 16 for all primaries first, tRAS 32 and tRC 48, tRFC=tRTP*tRC at 288/214/132, tRDWR=tRCD/2 at 8 and tWRRD=1.


----------



## shnyaps

Do your CD mem channels have lower vdimm?


----------



## zerophase

slayer1991 said:


> I found my Bdie to not like a lower tCWL than tCL, and tWR = 2x tRTP all the way down to 12/6.
> Also, there was a sweetspot for VDIMM, where too much or too little would cause errors in TM5.
> 
> Might be able to drop cLDO VDDP to 0.9v, and VDDG CCD to 0.95
> Try flat 16 for all primaries first, tRAS 32 and tRC 48, tRFC=tRTP*tRC at 288/214/132, tRDWR=tRCD/2 at 8 and tWRRD=1.


I can boot fine with those current settings. It's once I pull tCL down to 14 that issues arise. Dropping VDDP and CCD caused one of my ram fans to not spin.



shnyaps said:


> Do your CD mem channels have lower vdimm?


Actually CD is running a little bit lower than the input voltage.


----------



## ldclopes

Blackfyre said:


> First, to answer your previous question. The people who had issues achieving 3600Mhz or higher weren't on Zen 3 or X570 boards I believe.
> 
> Second, I don't even need to play with procODT/RTT/CADBus to achieve 3800Mhz on my 4 x 8Gb Micron e-die sticks; depends on motherboard, memory controller, and luck. In fact, I set them all the lowest resistance values, as you can see my ZenTimings. *Setting them to the lowest resistance produces the least amount of heat*. If you can run them at these values below (in the yellow box), then do that. Some motherboards & memory controllers can't do that though and need higher resistance:
> View attachment 2567423


A big THANK YOU.
Those settings actually worked for me. My secondary timmings are a bit more relaxed (will try to tighten it later) and I used 1.5v on vDimm. It is stable. Again, I'm very gratefull.

Out of curiosity, I see you are actually running @ 3800MHz, the only thing you changed are the voltages?


----------



## byDenoso

Valka814 said:


> Cant solve it by myself, so I ask the gurus for tips (again) .
> If I change tFAW 16->24 and tRCDWR 20->18, a rare error #4 will come up.
> View attachment 2566782



Try:
RDCWR 18
RAS: 36
RDDS/L/FAW - 6/8/24
WTRS/L - 4/12
RTTs 7/3/3
Clk Drv Str 40ohm


----------



## zerophase

Ok, raising tRFC to 304 causes me to get to the ROG screen, and freeze on detecting the HDD every time. I'm using the DIMM.2 slot. 

One thing I've noticed is inputing 1.5v for VDIMM actually reports ~1.44v in the bios. Do I need to raise input voltage? Play with load line calibration?


----------



## Blackfyre

ldclopes said:


> A big THANK YOU.
> Those settings actually worked for me. My secondary timmings are a bit more relaxed (will try to tighten it later) and I used 1.5v on vDimm. It is stable. Again, I'm very gratefull.
> 
> Out of curiosity, I see you are actually running @ 3800MHz, the only thing you changed are the voltages?


Create a profile and save your current working setting with 3600Mhz so you don't lose them in case you need to reset the BIOS. 

Then test 3800Mhz, change Trfc to 551 instead of 544 or whatever I had it set to in my settings.


----------



## zerophase

I actually played WoW with an AMD engineer. Sadly, the guild was purged of members with the wrong politics. If anyone plays WoW Classic you could probably get in and mine some additional overclocking data.


----------



## Bloax

Bix said:


> I decided to try and see if I could do @Bloax trick of using WR/RTP 20/10 to allow the setup time to be removed. Finding it pretty tough!


It turned out to be a red herring in the end, as it was practically running the same ClkDrvStr 120 as you found - except with a tiny read delay that shouldn't have been there -- removing that, made it intermittently unstable just as you found. 🤡

whoops








the RTP/tWR tomfoolery wasn't a red herring though hehehehe
minus tRP minus tRC lower tRFC weee :---DDDD


----------



## Valka814

No succes still.


----------



## fingon82

Trying to stabilise this kit of Vipers 4400mt bdie A0...1.5v. Still working on secondaries
What could this error be, not a number of test beside it?


----------



## The_King

fingon82 said:


> Trying to stabilise this kit of Vipers 4400mt bdie A0...1.5v. Still working on secondaries
> What could this error be, not a number of test beside it?
> 
> View attachment 2567759


You will be far better off tightening sub timmings than primaries. Your overall performance will suffer with high sub timings.

I noticed running higher tFAW will let you get away with running 3800 and RCD 14 but that cost is too high if tFAW is 40 and RRDS is 8.

If you still want to make those primary work, I would try to bring tFAW down to at least 24 with RRDS 6.

Else try something like this. You would need lower VDIMM for 2 stick maybe 1.48V-1.5V. Your VDDP is also high you can try +/-0.9V


----------



## fingon82

Shouldnt tRTP be half of TWR (for your 2nd suggestion)? 
I still hadnt come to secondaries from trc to trfc. I only tried twr 12 with trtp 6,and it gives me errors

Arent primaries much more important than tfaw?

Thanks for advices,i apreciate it, long time since i fiddled with memory subtimings

Edit

Just tried your settings, 5 errors in 2nd minute, on test 1


----------



## The_King

fingon82 said:


> Shouldnt tRTP be half of TWR (for your 2nd suggestion)?
> I still hadnt come to secondaries from trc to trfc. I only tried twr 12 with trtp 6,and it gives me errors
> 
> Arent primaries much more important than tfaw?
> 
> Thanks for advices,i apreciate it, long time since i fiddled with memory subtimings
> 
> Edit
> 
> Just tried your settings, 5 errors in 2nd minute, on test 1


Yes, ideally TWR should be RTP X2 but sometimes 12/8 works when 12/6 does not.

Copy pasted setting rarely work for me as well. Not sure if its because I am still on B450.

Going too low with Primary can cause tons of headaces later on when you do the subs timings.
best to have some benchmark to see if you are actually getting faster or making things worse.
Running Y-cruncher maybe useful to check performance gains.

Also this video should explain why low CL is not always better.


----------



## Bloax

fingon82 said:


> Trying to stabilise this kit of Vipers 4400mt bdie A0...1.5v. Still working on secondaries
> What could this error be, not a number of test beside it?
> 
> View attachment 2567759


The usual go-to for error reading is TM5 with 1usmus_v3, as the rest are less "known":


https://dl.dropbox.com/s/qnf2cckk5iqu4uo/testmem5_with_sheet2.zip


For stability-stability testing, I prefer y-cruncher:










However, I should note that Viper 4400 sticks are fairly known entities by now:
procODT 28.2,
CPU 1.8v* set to around 1.86-1.92v (recently added a comment to Error #1 about finding this),
RTT Nom/6 (40 ohm) + Wr/3 (80 ohm) + Park/5 (48 ohm, or /4 [60 ohm]),
CADBus 40-20-30-20,
AddrCmdSetup 56 for GDM Off 1T

* (VDD18, CPU 1P8, whatever voltage has a default value of 1.8v is usually "it" unless it's some mystery unrelated 1.8v PLL voltage)

RTP 5-7, tWR 10-14 --
RRD runs 4-4 or 4-6 (usually RRDL 6 performs better at 1T)
WTRL is stuck at 12 unless you run low procODT + >1.8v CPU 1.8v

also runs with RTP 10 + tWR 20, if you wanna do this:


Bloax said:


> View attachment 2567717
> 
> the RTP/tWR tomfoolery wasn't a red herring though hehehehe
> minus tRP minus tRC lower tRFC weee :---DDDD


i.e. if you want to try to run tCL 14 tRCD 14 tRP 12 (maybe less?) tRAS 28 tRC 40 tRFC 240-178-110, maybe even lower tRP/tRC/tRFC!

have fun


----------



## 97pedro

Anything else I can improve on this?


----------



## byDenoso

@Veii i've finally fixed my set


----------



## Ramad

*Here* are my results of testing 32GB 4xSR Micron Rev. E using Ryzen 5600 on 2 motherboards, the old Asus Crosshair 6 Hero (X370 chipset) and the newer Gigabyte Aorus Pro rev. 1.2 (X570 chipset). The same settings and voltages are applied for both motherboards. The CPU is overclocked to 4.45GHz. I'm providing these settings/stability tests for users that have the same or similar hardware configuration, that it may help getting usable and stable and overclocked system.

As mentioned earlier, the same settings are used on both motherboards. They are as follows:

*Voltages:*
CPU @4.45GHz (Ryzen 5600 (non X)): 1.275V
SOC: 1.1V
1.8 PLL: 1.96V
CLDO_VDDP, VDDG CCD and VDDG IOD: All at 1000mV
RAM: 1.38V

*RAM settings:*
Speed: 3800MT/s
PROCODT: The lowest on both motherboards, C6H: 30 Ohm GB AP: 28.2 Ohm
Data bus: Nominal: Disabled, Write: RZQ/3 (80 Ohm), Park: RZQ/5 (48 Ohm)
CAD Strength: All at 20 Ohm
CAD timings: All at 0
Memory interleaving page size: 1 KB (under AMD CBS/DF settings)
BGS: Enabled
BGS Alternative: Disabled
GDM: Enabled

*RAM timings: *
See spoilers below.
*Note:* The memory controller is allowing tWRRD (write to read latency), tRDRDSD (read to read latency on the same DIMM) and tWRWRSD (write to write latency on the same DIMM) to be set to a latency of 1CK on both motherboards.

*Software used:*
HWiNFO64, Prime95 and ZenTimings

*Worth mentioning:*
If you have 1 set of 2 RAM sticks (i.e 2x8GB) or and have bought another set of 2 RAM sticks for at total of 4 stciks of 2 matching pairs, install a matching pair in slots A1 and A2 and the other matching pair in slots B1 and B2.
Don't install the RAM sticks as if you are installing 2x8GB as a matcing pair in A2+B2 and the other matching pair in A1+B1. The reason is that, the CPU has 2 memory controllers (1 memory controller pr. channel), means a memory controller for channel A (slots A1 and A2) and the second controller is for channel B (slot B1 and B2), and every memory controller expects a matching RAM set pr. channel.

It's different if you only have 1 set of 2x8GB or 2x16GB RAM, then you need to use them in A2+B2 to activate dual channel of 128bit in total, and you would not have any problems because the slots A1 and B1 are empty so every memory controller has 1 stick of RAM to deal with, means no worry of matching pairs.



Spoiler: C6H Prime95 test (2 hours):

























Spoiler: Gigabyte Aorus Pro Prime95 test (2 hours):


----------



## fingon82

Bloax said:


> Wr/3 (80 ohm) + Park/5 (48 ohm, or /4





Bloax said:


> thanks
> no i don't fix myself being wro





Bloax said:


> The usual go-to for error reading is TM5 with 1usmus_v3, as the rest are less "known":
> 
> 
> https://dl.dropbox.com/s/qnf2cckk5iqu4uo/testmem5_with_sheet2.zip
> 
> 
> For stability-stability testing, I prefer y-cruncher:
> View attachment 2567764
> 
> 
> 
> However, I should note that Viper 4400 sticks are fairly known entities by now:
> procODT 28.2,
> CPU 1.8v* set to around 1.86-1.92v (recently added a comment to Error #1 about finding this),
> RTT Nom/6 (40 ohm) + Wr/3 (80 ohm) + Park/5 (48 ohm, or /4 [60 ohm]),
> CADBus 40-20-30-20,
> AddrCmdSetup 56 for GDM Off 1T
> 
> * (VDD18, CPU 1P8, whatever voltage has a default value of 1.8v is usually "it" unless it's some mystery unrelated 1.8v PLL voltage)
> 
> RTP 5-7, tWR 10-14 --
> RRD runs 4-4 or 4-6 (usually RRDL 6 performs better at 1T)
> WTRL is stuck at 12 unless you run low procODT + >1.8v CPU 1.8v
> 
> also runs with RTP 10 + tWR 20, if you wanna do this:
> 
> i.e. if you want to try to run tCL 14 tRCD 14 tRP 12 (maybe less?) tRAS 28 tRC 40 tRFC 240-178-110, maybe even lower tRP/tRC/tRFC!
> 
> have fun


Well, i tried it but i dont know is it achievable:









3 errors-6,11,12. Also, my pc sometimes wont post after restart (low procODT?)

Soc - 1.15v
VDRAM - 1.52v
VDDG CCD - 1.05v
VDDG IOD - 1.05v
CLDO VDDP - 1v
CPU 1.8v - 1.89v
VTT DDR - 0.76v

Thanks for AddrCmdSetup 56 for GDM Off 1T, it pissed me off 
Question, why my Zen Timings doesnt show all voltages ?

Any suggestion how to handle those 3 errors and POST problems is greatly apreciated. I will fiddle with voltages a bit more in the meantime


----------



## Bloax

97pedro said:


> View attachment 2567765
> 
> 
> Anything else I can improve on this?


You could always try Park/2 or /3 to not fry your DIMM contacts as much, could try and find your best performing SOC/IOD/CCD voltage combo.
I'm surprised it runs without tCKE 9, might be due to not running tRAS as tCL+tRCD hehexd?




fingon82 said:


> Well, i tried it but i dont know is it achievable:
> 
> View attachment 2567830
> 
> 
> 3 errors-6,11,12. Also, my pc sometimes wont post after restart (low procODT?)
> 
> Soc - 1.15v
> VDRAM - 1.52v
> VDDG CCD - 1.05v
> VDDG IOD - 1.05v
> CLDO VDDP - 1v
> CPU 1.8v - 1.89v
> VTT DDR - 0.76v
> 
> Thanks for AddrCmdSetup 56 for GDM Off 1T, it pissed me off
> Question, why my Zen Timings doesnt show all voltages ?
> 
> Any suggestion how to handle those 3 errors and POST problems is greatly apreciated. I will fiddle with voltages a bit more in the meantime


not POSTing might be related to high SOC/IOD/CCD, though it could also be too high VDDP


Error #6 is probably due to an uneven tRFC (285 vs. 284/286), though you could keep it a multiple of tRC and use 252-187-115 for tRC 42.
#12 probably related

#11 may or may not go away at 1.51/1.53vDIMM, or just not exist once tRFC is fixed


----------



## TimeDrapery




----------



## zerophase

Almost have 1T stable. Errors in TM5 have gone down switching ProcODT to 36.9. CadBus is 24-20-20-24. The B-die is getting up to 45.5c on the hottest stick. Would pulling temps down a tad more help? Would upgrading my fans to Noctua NF-S12A help pull temps down enough to get this stable? Anyone know if an Enthoo Elite has enough resistance at the front to need static pressure fans?

Other than playing around with CadBus would raising PLL help?


----------



## wholeassery

This is my dual rank 2x16GB CJR kit running on the 5800X3D. Somehow I haven't had any issues booting at CL16 @ 4000 (2000 FCLK). Haven't touched the timings yet, I'm trying to find the max frequency first.

I start getting errors in TestMem5 (anta777 config) around the 30 minute mark. There's also a visible performance regression – my AIDA64 scores are similar to what I was getting at 3733.

Do you guys think it's possible to stabilize this CJR kit at 4000 CL16 (or at least 3933)? 

I've played around with voltages, procODT, drive strengths, and primary timings, but best I could do was minimize the performance regression – it still throws sporadic errors in TM5.


----------



## ccxmonster

hi people what *setup timings* should i use for my dual rank 2x16GB memory kit ?
they are samsung D-Die kit.
i want to use them on 1867 MCLK/3733MHz speed with gdm disabled 1T

im already researched and will try tCKE 8 value but im very undecided about setup timings. can someone give me a good settings ? 

thanks in advance.


----------



## Bix

Bloax said:


> It turned out to be a red herring in the end, as it was practically running the same ClkDrvStr 120 as you found - except with a tiny read delay that shouldn't have been there -- removing that, made it intermittently unstable just as you found. 🤡
> 
> whoops
> 
> View attachment 2567717
> 
> the RTP/tWR tomfoolery wasn't a red herring though hehehehe
> minus tRP minus tRC lower tRFC weee :---DDDD


Nice result! Will have another go at tweaking when I'm home next week. Do RP, RC and RFC all need to come down together rather than testing one at a time?


----------



## Bloax

Bix said:


> Nice result! Will have another go at tweaking when I'm home next week. Do RP, RC and RFC all need to come down together rather than testing one at a time?


Well, tRC is tRAS + tRP, and I prefer the tRFC = tRC * x (usually 6) method of setting it.

So by lowering tRP, I also lower tRC and tRFC at the same time.
and yes it is indeed, a very nice result:







3828 14-14-12 single-rank






4100 16-16-14 dual-rank
note how the bandwidth numbers on the single-rank setup _are higher_ at every utilization step, besides 100%
no wonder it doesn't wanna go faster, it's already punching far above its weight


----------



## ocisdead

Ramad said:


> *Here* are my results of testing 32GB 4xSR Micron Rev. E using Ryzen 5600 on 2 motherboards, the old Asus Crosshair 6 Hero (X370 chipset) and the newer Gigabyte Aorus Pro rev. 1.2 (X570 chipset). The same settings and voltages are applied for both motherboards. The CPU is overclocked to 4.45GHz. I'm providing these settings/stability tests for users that have the same or similar hardware configuration, that it may help getting usable and stable and overclocked system.
> 
> As mentioned earlier, the same settings are used on both motherboards. They are as follows:
> 
> *Voltages:*
> CPU @4.45GHz (Ryzen 5600 (non X)): 1.275V
> SOC: 1.1V
> 1.8 PLL: 1.96V
> CLDO_VDDP, VDDG CCD and VDDG IOD: All at 1000mV
> RAM: 1.38V
> 
> *RAM settings:*
> Speed: 3800MT/s
> PROCODT: The lowest on both motherboards, C6H: 30 Ohm GB AP: 28.2 Ohm
> Data bus: Nominal: Disabled, Write: RZQ/3 (80 Ohm), Park: RZQ/5 (48 Ohm)
> CAD Strength: All at 20 Ohm
> CAD timings: All at 0
> Memory interleaving page size: 1 KB (under AMD CBS/DF settings)
> BGS: Enabled
> BGS Alternative: Disabled
> GDM: Enabled


RttNom disabled with four sticks? I can't find another soul on the internet running this configuration. Auto should be 7. What led you to this?


----------



## Luggage

zerophase said:


> Almost have 1T stable. Errors in TM5 have gone down switching ProcODT to 36.9. CadBus is 24-20-20-24. The B-die is getting up to 45.5c on the hottest stick. Would pulling temps down a tad more help? Would upgrading my fans to Noctua NF-S12A help pull temps down enough to get this stable? Anyone know if an Enthoo Elite has enough resistance at the front to need static pressure fans?
> 
> Other than playing around with CadBus would raising PLL help?


If you have any fan over just jerry rig it towards the ram with case panel off and see if it helps.


http://imgur.com/a/pThNKHr


----------



## Ramad

ocisdead said:


> RttNom disabled with four sticks? I can't find another soul on the internet running this configuration. Auto should be 7. What led you to this?


Nothing special, it depends on the motherboard - RAM - IMC combination. I usually test many RTT combinations to find the most stable settings. The settings Disabled - RZQ/3 - RZQ/5 and Disabled - RZQ/2 - RZQ/5 was the most stable for my system and I settled for the first combination here.

Here is what I ran with first Ryzen and 2 X370 motherboards:
Ryzen 1600 + C6H + Samsung E-die needed: Disabled - RZQ/3 - RZQ/1 or RZQ/3 - RZQ/3 - RZQ/1
Ryzen 1600 + GB K7 +Samsung E-die needed: RZQ/5 - OFF- Disabled

X570:
Ryzen 2700X + MSI Tomahawk + 2X8GB Micron Rev. E: Here

I find it always best to disable Nominal RTT for best stability on motherboards, RAM and CPUs that I have tested.


----------



## deedeeDMT

I know there's latency penalty when you run desynced but but I just want to know is there a proper way to desync it or do you just let your motherboard do it?


----------



## AmINoob

First time posting here. Can i get some help?. My settings are stable both in 2t and gdm on but i can't get if any further. 3800 doesn't even post, i tried changing primaries to 15-15-15 with 2t or 14-14-14 with gdm on, i tried rising voltage to 1,45-1,5V with no luck. What do i need to loosen up in order to get trcd down? Also is my vsoc right with other voltages? I not sure if it needs to be 50mV above vddg avg or 50mv above vddg iod. Is there a way to make my ram faster without redoing everything from scratch?








From the time that i did this tesmtem run i lowered my trfc/trfc2/trfc4 by 1 and changed rttpark to /3 but i didn't saved screenshot of it running stable.


----------



## fingon82

3800 C14 on 4 sticks is 1.5v+ vdimm, not 1.45v-1.5v
I would say that you probably used too low voltages
Here`s mine latest report @Bloax










Still working on it
vdimm 1.52v, 1.51v gives 100 errors in 5 minutes, 1.53v gives overheating error sometimes, barely there
VSOC 1.12v
vddp 0.92v
vddg ccd 0.98v
vddg iod 1.02v

tRFC = tRC * 6 gives me errors, must be x7
twtrs is 6, 0 chance of 4, 5 is maybe possible...can twtrl be 6?
tcke 8 any chance of 1?
tfaw 14 or 16?
Why doesnt my zem timings show all the voltages?
Thanks guys for you help, i learned alot during last week


----------



## AmINoob

fingon82 said:


> 3800 C14 on 4 sticks is 1.5v+ vdimm, not 1.45v-1.5v
> I would say that you probably used too low voltages



I wasn't to specific i guess. I cannot boot 3800+ no matter what settings i use. I wanna get 3733 15-15-15 2t or 3733 14-14-14 gdm/2t stable


----------



## Taraquin

Blackfyre said:


> First, to answer your previous question. The people who had issues achieving 3600Mhz or higher weren't on Zen 3 or X570 boards I believe.
> 
> Second, I don't even need to play with procODT/RTT/CADBus to achieve 3800Mhz on my 4 x 8Gb Micron e-die sticks; depends on motherboard, memory controller, and luck. In fact, I set them all the lowest resistance values, as you can see my ZenTimings. *Setting them to the lowest resistance produces the least amount of heat*. If you can run them at these values below (in the yellow box), then do that. Some motherboards & memory controllers can't do that though and need higher resistance:
> View attachment 2567423


Does lower DrvStr also lower heat? What Rtts produces least heat?


----------



## Bloax

Minimizing heat inside the memory chip, simply means the heat is going elsewhere (DIMM contacts, PCB traces/wires, capacitors??) as we're still drawing roughly the same amount of wattage to run the sticks.

RTT Park/1 (240 ohms) for example, is great for memory chip temperature, but awful if you want your DIMM contacts to not get burnt over time running >1.45vDIMM.

With the memory chips being the usual things that get cooled, unless you take the heatsinks (heat traps) off, you usually want those to be the ones which bear the most heat. As those will be the things getting actively cooled by a fan.


I love sleep deprivation drunkness sometimes, somebody mentioned aquariums and I immediately jumped back to Mineral Oil builds.. Except, why engulf the entire system in it?
Why not..








build a little aquarium in epoxy (with the help of a skeleton material for the vertical walls, cardboard, styrofoam.. ??) to encase the immediate surroundings of the RAM, then fill it up with mineral oil?
if you use paint thinner to free the RAM sticks from their RAM-Seller crimes against heatsinks, the naked DIMMs are surprisingly short - so it wouldn't even require a lot of oil (roughly 1.2 L?)
plus you get 101% coverage, even the DIMM contacts get cooled LOL





cursed sticks are mildly less cursed now that I can keep them at 34.5 C running 4100 15-15-13 @ 1.53v, however my 12700k's memory interface is clearly suffering from early-onset dementia thanks to CPU bending, unlucky....

will be fun to EVENTUALLY(tm) test this RAM Aquarium Concept on my old, heatsink-less x570 Asrock ITX board that I had to replace with a b550 Unify-X just to sell my CPU in a non-embarassing package.
but that's gonna require me getting a ryzen 5500 for no other purpose than this, good thing I am made of money and not not-having-money asdsfghjdfsga





fingon82 said:


> 3800 C14 on 4 sticks is 1.5v+ vdimm, not 1.45v-1.5v
> I would say that you probably used too low voltages
> Here`s mine latest report @Bloax
> 
> View attachment 2567912
> 
> 
> tRFC = tRC * 6 gives me errors, must be x7
> twtrs is 6, 0 chance of 4, 5 is maybe possible...can twtrl be 6?
> tcke 8 any chance of 1?
> tfaw 14 or 16?
> Why doesnt my zem timings show all the voltages?
> Thanks guys for you help, i learned alot during last week


tCKE is a "minimum" timing used to offset the memory signal, i.e. offset the peaks (Left / Right) by (Decreasing / Increasing, respectively) the minimum width of this important yet meaningless-for-performance command.




example of memory signals in action
the peaks/valleys need to be in the correct position for when the data is scheduled to be picked up by the memory controller
tolerance for error is usually higher at slower (2T, 2.5T for GDM) command-rates.

You seem to be suffering from temperature-related problems, so if you want your sticks to be cooled better you should stick a fan on them
and if you do stick a fan on them, then:








here's how you remove the Viper Steel heatsink (heat trap, really - the pcb/capacitors want to be cool too), they're super nice in this regard.


If WTR_short doesn't want to be 4 (or 5) - maybe try WRRD 2 or 3? RDWR 9 and WRRD 2/3 ?? Odd that it wouldn't work, it's pretty easy on 2x8.
tFAW 16 would probably work with tCKE 9, because an increased tFAW can also be used to delay the memory signal.

I've even had tFAW 18 perform better than tFAW 16 for this reason, though it wasn't stable, hehe.
Usually if that's the case, you need to make something else (e.g. RDWR / WRRD / [rdrd / wrwr]_SCL) slower - as Lower is not Always Better.


----------



## Frosted racquet

Can anyone shed some light why I'm getting the infamous TM5 timeout/crash with no errors. Happens with both stock CPU settings and XMP.
Here's my current settings, can pass 100 cycles of 1usmus and Extreme preset, but frequently experience the timeout issue.


----------



## Audioboxer

Frosted racquet said:


> Can anyone shed some light why I'm getting the infamous TM5 timeout/crash with no errors. Happens with both stock CPU settings and XMP.
> Here's my current settings, can pass 100 cycles of 1usmus and Extreme preset, but frequently experience the timeout issue.


Timeouts are almost always minor instability issues, either a CPU core is crashing which doesn't trigger a memory error, just breaks the cycle or in my experience it's voltage or resistance on the memory.

Easiest way to test CPU is just turn PBO/curve optimiser off. With memory what fixed my power down issue was CkeDrvStr 30. As you're on DR as well I'd try that. Or a quick +0.01v to VDIMM might help.

In other news Hydra seems to be maturing a bit now. Giving it a spin again. Surprised to see it's quick stability testing actually reduced one of my cores from -16 to -13. I've been running this curve for like a year now with no issues and back when I did it all the usual corecycler/y-cruncher testing!


----------



## Frosted racquet

Audioboxer said:


> Timeouts are almost always minor instability issues, either a CPU core is crashing which doesn't trigger a memory error, just breaks the cycle or in my experience it's voltage or resistance on the memory.
> 
> Easiest way to test CPU is just turn PBO/curve optimiser off. With memory what fixed my power down issue was CkeDrvStr 30. As you're on DR as well I'd try that. Or a quick +0.01v to VDIMM might help.


Will try CkeDrvStr 30. Already tried stock CPU and XMP and it happens there as well.


----------



## Audioboxer

Frosted racquet said:


> Will try CkeDrvStr 30. Already tried stock CPU and XMP and it happens there as well.


XMP on the memory, as in no changes at all and running at default voltage?

With GDM enabled and XMP there should be no need to tweak or change resistances. 

Dumb question on this forum but I assume your BIOS is up to date? I know the Ryzen platform has had all sorts of stability changes for memory over the years.

I'd try some other memory benchmarks to see if they have an issue. Not sure what all the best free ones are outside of TM5.

Final question is on memory temps, at XMP this shouldn't be an issue at all, but what sort of temps do you see? B-die above 42 degrees can get sensitive but that's usually with OCed memory. At XMP people will regularly be in the 50s and above in a hot case.


----------



## Frosted racquet

Audioboxer said:


> XMP on the memory, as in no changes at all and running at default voltage?


Correct, XMP and default voltages, along with disabled PBO.


Audioboxer said:


> Dumb question on this forum but I assume your BIOS is up to date?


Running 1203b AGESA, avoided the chaos of 1205+ in terms of CPU voltage changes.


Audioboxer said:


> Final question is on memory temps, at XMP this shouldn't be an issue at all, but what sort of temps do you see? B-die above 42 degrees can get sensitive but that's usually with OCed memory. At XMP people will regularly be in the 50s and above in a hot case.


IIRC at XMP the temps were around 40°C, with OC settings posted above the temps go to ~60°C, but I haven't seen the temp related instabilities in TM5 and other memory tests as other people described.

I'll update with the adjusted DrvStr if it makes a difference.


----------



## Taraquin

So 3800cl15 was waaay easier stabilizing at 1t gdm off than 4000cl16.








Passed 20 rounds of TM5 with 1 error 2 at round 20 :/ I honestly don`t care, gamingstable anyways. most likely DrvStr of 20-20-20-20 is the culpit since I know 40 20 30 24 gets no errors. I just wanted to test the usually terrible 20 20 20 20 config.

I tried getting 14 15 15 and 14 14 14 stable, but errors pile up even at 1.57v ( I tried with at fan directed at ram). No idea how to fix it, ram is probably just too poorly binned.


----------



## Audioboxer

Frosted racquet said:


> Correct, XMP and default voltages, along with disabled PBO.
> 
> Running 1203b AGESA, avoided the chaos of 1205+ in terms of CPU voltage changes.
> 
> IIRC at XMP the temps were around 40°C, with OC settings posted above the temps go to ~60°C, but I haven't seen the temp related instabilities in TM5 and other memory tests as other people described.
> 
> I'll update with the adjusted DrvStr if it makes a difference.


My only other suggestions then are

a) Update the BIOS, especially if you run Windows 11
b) Make sure you're on these AMD chipset drivers https://www.amd.com/en/support/kb/release-notes/rn-ryzen-chipset-4-06-10-651
c) If still failing on the above, create a bootable Windows USB and/or a secondary clean installation and try it. Alternatively, run TM5 in safe mode/diagnostic mode from current installation

When Windows 11 first came out there was a tremendous amount of AMD jank (especially with chipset drivers), one issue being weird overboosting issues that were leading to instability. This _could_ cause random core crashes.

Just keep in mind from AGESA 1.2.0.6 curve optimiser values often changed a bit for nearly everyone. So if you're looking to slot back in your old curve values, you might need to quickly check them again in the likes of corecycler.


----------



## 0xid0

Hi guys, I need some help, I'll ask some questions, if anyone knows how to tell.

Setup:

5800x PBO=142/95/140 CO=20/20/20/20/16/12/8/20
G.Skill Trident Z F4-3200C14D-16GTZ 1.45
Asus Rog X570-F Bios 4021 Agesa 1203C
Asus Rog 3070Ti
XPG 2TB 8200 Pro
Corsair TX-750M

I have an overclock in memory to 3800 as in the image and fully working, tested on memtest 64, tm5 extreme anta, prime 95 approved, but randomly I have errors and in the event viewer it says "Kernel Whea ID Event 20" and HWInfo accuses it as cpu bus/interconnect errors, these errors are random, I'm playing sometimes they appear and sometimes they don't, sometimes the unused computer appears and sometimes for days they don't appear.

If I go down to 3733 I have no errors, they are eliminated, at 3800, rising voltages Vsoc 1.2, iod 1.1, ccd 1.1, vddp 1, pll 1.81, I have these errors, it could be more tension in the ram memory, even in the ram tests it is OK? Would some timing have to relax more? or chip limit or hole?

There's not much difference in performance from 3733 to 3800, but I wanted to round it down to 3800. I'm thinking it might be some small detail that is going unnoticed. Sorry for my english, thank you very much.


----------



## hazium233

0xid0 said:


> Hi guys, I need some help, I'll ask some questions, if anyone knows how to tell.
> 
> Setup:
> 
> 5800x PBO=142/95/140 CO=20/20/20/20/16/12/8/20
> G.Skill Trident Z F4-3200C14D-16GTZ 1.45
> Asus Rog X570-F Bios 4021 Agesa 1203C
> Asus Rog 3070Ti
> XPG 2TB 8200 Pro
> Corsair TX-750M
> 
> I have an overclock in memory to 3800 as in the image and fully working, tested on memtest 64, tm5 extreme anta, prime 95 approved, but randomly I have errors and in the event viewer it says "Kernel Whea ID Event 20" and HWInfo accuses it as cpu bus/interconnect errors, these errors are random, I'm playing sometimes they appear and sometimes they don't, sometimes the unused computer appears and sometimes for days they don't appear.
> 
> If I go down to 3733 I have no errors, they are eliminated, at 3800, rising voltages Vsoc 1.2, iod 1.1, ccd 1.1, vddp 1, pll 1.81, I have these errors, it could be more tension in the ram memory, even in the ram tests it is OK? Would some timing have to relax more? or chip limit or hole?
> 
> There's not much difference in performance from 3733 to 3800, but I wanted to round it down to 3800. I'm thinking it might be some small detail that is going unnoticed. Sorry for my english, thank you very much.
> 
> View attachment 2568070
> View attachment 2568071


The event ID 20 is actually an "information" event that is telling you some type of error has been logged related to WHEA.

Corrected Bus / Interconnect Errors will also show up as warning type event ID 19. The easiest way to find them is click / highlight the top "Event Viewer (Local)" section in the left navigation pane, then expand the "Warning" area in the middle pane. I mention this in case you see people just talk about WHEA 19.

Anyway to answer your question, sometimes adjusting the voltages up or down can reduce them. Rarely they will eliminate them. For the most part if you don't want to see them you will just have to reduce FCLK. Some will suppress or hide them. If they end up being 100% corrected, this doesn't matter. But it is possible if you see corrected errors that eventually you will get an uncorrected one.

For me they start showing up under load at FCLK 1933, where they are slow but consistent.

The real world difference between 3800 and even 3600 is pretty small, at least if the timings are tuned.


----------



## 0xid0

hazium233 said:


> The event ID 20 is actually an "information" event that is telling you some type of error has been logged related to WHEA.
> 
> Corrected Bus / Interconnect Errors will also show up as warning type event ID 19. The easiest way to find them is click / highlight the top "Event Viewer (Local)" section in the left navigation pane, then expand the "Warning" area in the middle pane. I mention this in case you see people just talk about WHEA 19.
> 
> Anyway to answer your question, sometimes adjusting the voltages up or down can reduce them. Rarely they will eliminate them. For the most part if you don't want to see them you will just have to reduce FCLK. Some will suppress or hide them. If they end up being 100% corrected, this doesn't matter. But it is possible if you see corrected errors that eventually you will get an uncorrected one.
> 
> For me they start showing up under load at FCLK 1933, where they are slow but consistent.
> 
> The real world difference between 3800 and even 3600 is pretty small, at least if the timings are tuned.


I have a custom Whea Logger error display (image), any error it adds to the page, no whea and I haven't received a Whea in a while.

This Kernel Whea Event ID 20, would be a fix, but I saw that it would be a "Silent Whea" that over time corrupts the system.

I used on 3733/1866 the same configuration for a while and without any errors, Whea or Whea ID 20, but going up to 3800/1900 I have randomly ID 20, but ram tests are stable (image). I really wanted to correct, to keep a rounded number lol.

Any more suggestions to fix?


----------



## Bloax

[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Are these voltages safe for 24/7? The board gets good airflow. I read that increasing CLDO VDDP and VDDG CCD and VDDG IOD can help with stability and with USB issues, from the X570 HERO motherboard thread.




www.overclock.net





High FCLKs don't want high voltage, they want _*The* Voltage_









IOD 1.06v? Unstable. IOD 1.04v? Unstable. IOD 1.05v? Stable!
CCD 0.87v? Unstable. CCD 0.84v? Unstable. CCD 0.83v? Unstable. CCD 0.85v? Stable. CCD 0.86v? Stabl_*er*_!

very fun AM4 minigame 10/10 would recommend playing 🤒
can't wait for the AM5 expansion pack


----------



## KedarWolf

MSI Overclocker Demoes AMD Ryzen 7000 CPU Running DDR5-6400 CL32 Memory


One of MSI’s overclockers, Toppc, has recently started to tease what the Ryzen 7000 DDR5 memory is capable of. A screenshot has been taken from the CPU-Z tool which shows that 64 GB of the DDR5 memory is clocked at a speed of 3202.7 MHz with a CAS latency of 32 clocks.




thinkcomputers.org


----------



## domdtxdissar

^^
Maybe we need us a AMD Ryzen *DDR5 *24/7 Memory Stability Thread pretty soon ? 
Have some of new cooling hardware ready for the AM5 platform 







Currently i'm eying these gskill memory sticks: DDR5-6600 CL34-40-40-105 1.40V
But also think there will be some better "AMD EXPO" memorysticks around release time of Zen4, so i haven't bought memory yet.
(I'm waiting to see what AMD EXPO have to offer before i order memory)


----------



## Blackfyre

0xid0 said:


> I have a custom Whea Logger error display (image), any error it adds to the page, no whea and I haven't received a Whea in a while.
> 
> This Kernel Whea Event ID 20, would be a fix, but I saw that it would be a "Silent Whea" that over time corrupts the system.
> 
> I used on 3733/1866 the same configuration for a while and without any errors, Whea or Whea ID 20, but going up to 3800/1900 I have randomly ID 20, but ram tests are stable (image). I really wanted to correct, to keep a rounded number lol.
> 
> Any more suggestions to fix?
> 
> View attachment 2568083
> View attachment 2568085


*How did you create that custom WHEA Logger?* I would love to know. Thank you.


----------



## Audioboxer

Bloax said:


> can't wait for the AM5 expansion pack


The last thing I would trust on a new AMD launch platform is the memory controller 

Waiting to see what people find, but my wallet is going to be happier waiting for a generational revision or two.

Also, interesting how you don't have any issues with IOD and VSOC being that close. I found I needed a bigger gap between the two when running VSOC on auto. Otherwise occasional TM5 timeouts.

Have you tried the Geekbench benchmarks? It was someone in this topic that pointed me to them for figuring out CCD. As in, there were values I seemed stable at but when doing performance benchmarks I was suffering a bit with performance (really low CCD would run but GB benchmarks showed lower performance).

I ended up CCD 0.975v and IOD 1.0v on my B550.


----------



## shnyaps

domdtxdissar said:


> ^^
> Maybe we need us a AMD Ryzen *DDR5 *24/7 Memory Stability Thread pretty soon ?
> Have some of new cooling hardware ready for the AM5 platform
> View attachment 2568109
> 
> Currently i'm eying these gskill memory sticks: DDR5-6600 CL34-40-40-105 1.40V
> But also think there will be some better "AMD EXPO" memorysticks around release time of Zen4, so i haven't bought memory yet.
> (I'm waiting to see what AMD EXPO have to offer before i order memory)


I like your copper ram cover. What is it? share link please. Could you measure distance between top holes?


----------



## domdtxdissar

shnyaps said:


> I like your copper ram cover. What is it? share link please


Here you go:








Custom RAM copper heatsinks for DDR5 / DDR4 - Bartxstore


Custom made copper RAM heatsinks for memory extreme overclocking using dry ice or LN2. Designed for DDR4 and DDR5 memory




bartxstore.com


----------



## shnyaps

domdtxdissar said:


> Here you go:
> 
> 
> 
> 
> 
> 
> 
> 
> Custom RAM copper heatsinks for DDR5 / DDR4 - Bartxstore
> 
> 
> Custom made copper RAM heatsinks for memory extreme overclocking using dry ice or LN2. Designed for DDR4 and DDR5 memory
> 
> 
> 
> 
> bartxstore.com


Please measure distance between holes


----------



## Audioboxer

Inspired by @Bloax and with nothing else to do now, thought I'd play around with VDDP










Just testing with Karhu with cache/FPU enabled. Not had it as low as 0.84v in any prior testing, I believe like 0.86v or 0.87v is lowest I've gone before.










In testing now is 0.8v lol. Doubt there is any real benefit to this, but it's interesting nonetheless to see it that low not erroring out as of yet. Even if it doesn't error benchmarking would need to be done to see if performance is dropping.

No powering issues with DIMMs at 0.8v either, still training 26/26.


----------



## Taraquin

Audioboxer said:


> Inspired by @Bloax and with nothing else to do now, thought I'd play around with VDDP
> 
> View attachment 2568147
> 
> 
> Just testing with Karhu with cache/FPU enabled. Not had it as low as 0.84v in any prior testing, I believe like 0.86v or 0.87v is lowest I've gone before.
> 
> View attachment 2568148
> 
> 
> In testing now is 0.8v lol. Doubt there is any real benefit to this, but it's interesting nonetheless to see it that low not erroring out as of yet. Even if it doesn't error benchmarking would need to be done to see if performance is dropping.
> 
> No powering issues with DIMMs at 0.8v either, still training 26/26.


Lowest stable 100% performing voltage is always benefit as it makes IO-die use less power and hence give more power headroom if using PPT and slightly lower thermals  I feel bad inside when I see several MBs using 1.2v soc, 1.1v iod/ccd/vddp at 3800 :/ Talk about waste of power, possibly instability etc. Try CCD next  At both 3800 and 4000 I ran CCD and VDDP at 0.82v


----------



## Audioboxer

Taraquin said:


> Lowest stable 100% performing voltage is always benefit as it makes IO-die use less power and hence give more power headroom if using PPT and slightly lower thermals  I feel bad inside when I see several MBs using 1.2v soc, 1.1v iod/ccd/vddp at 3800 :/ Talk about waste of power, possibly instability etc. Try CCD next  At both 3800 and 4000 I ran CCD and VDDP at 0.82v


Yup, sounds good, in principle. 0.8v ran for an hour fine, so I'm now trying to go a bit quicker to find where I error out fast. Then I'll nudge voltage back up for longer testing










0.75v didn't post, so I bumped it to 0.77v and will now let it go at least an hour. I'll see where I end up with VDDP!

My issue with CCD being low is what I mentioned a few posts above. I've ran it at 0.87v before, early on, but I got advised to run Geekbench 5 benchmarks and watch for lower scores. I did seem to find CPU performance was getting worse with a lower CCD, even if the system appeared stable. Performance scaling stops at some point though, so it's not just a case of leave CCD high.

I believe that was showing the CPU while running stable, in theory, was getting starved of voltage it wanted to perform better.

That being said I haven't done any bench testing with VDDP, so I have no idea if it can scale performance wise as well. My understanding is just that VDDP is more to do with memory, whereas CCD is about the CPU.


----------



## Taraquin

I may have been able to stabilize 3800cl14 at last  With a fan directed at ram that is. Seems RDWR and WRRD at auto did the trick. I also employed the 20\10 WR\RTP and slower RRD\FAW trick. RCDRD 14 seems impossible though. Even at 1.57v I get loads of error 2, 6, 10 and 12.


----------



## Audioboxer

Taraquin said:


> I may have been able to stabilize 3800cl14 at last  With a fan directed at ram that is. Seems RDWR and WRRD at auto did the trick. I also employed the 20\10 WR\RTP and slower RRD\FAW trick. RCDRD 14 seems impossible though. Even at 1.57v I get loads of error 2, 6, 10 and 12.
> 
> View attachment 2568152


Good old B-die, it is NOT a _fan_ of heat. I laugh when folks on Reddit burst a blood vessel screaming at me watercooling memory is 100% pointless. It's like, 95% pointless for many, maybe, but if you're pushing B-die OCing it's like the best form of active cooling. Especially when pushing tRFC stupidly low.










I mean, it's the summer at the moment, so my water temps are a bit higher following ambient, and as you can see above at 1.58v I'm at 34 degrees max. Now, this is without the GPU in action, so adding another few degrees to the water temps will bring memory to 35~36, but that's still great. Hence, it allows me to run a really low tRFC.

Never having to worry about memory temps is a big bonus when OCing!

And here's me at an hour with 0.77v. Just seems funny to drop from 0.9v to this low and it might be stable. Will do an overnight now. As I said 0.75v doesn't post, so probably on the line here.

I'll ping @Veii for a refresher from his infinite wisdom on VDDP, Veii, what say you to VDDP when it gets as low as 0.8v and below?


----------



## domdtxdissar

shnyaps said:


> Please measure distance between holes


I measure them to be 110mm apart although it dont seems like that on my own pictures 😆













Here are also a video:


----------



## Audioboxer

At 0.77v I finally found an issue, tPHYRDL intermittently booting at 28/26. 0.78v was enough to 100% boot 26/26 every time. So I thought for fun lets drop CCD to 0.78v as well. Karhu 1 hour quick test down, and running y-cruncher now.

I fully expect performance loss at this voltage, but it's still pretty damn interesting to see voltages you daily much higher run a lot lower and seemingly have a chance to pass stability testing.

Up next, drop IOD as well, any% speedrun to starving my CPU of voltage. Why? Just for fun!


----------



## Taraquin

Audioboxer said:


> View attachment 2568165
> 
> 
> At 0.77v I finally found an issue, tPHYRDL intermittently booting at 28/26. 0.78v was enough to 100% boot 26/26 every time. So I thought for fun lets drop CCD to 0.78v as well. Karhu 1 hour quick test down, and running y-cruncher now.
> 
> I fully expect performance loss at this voltage, but it's still pretty damn interesting to see voltages you daily much higher run a lot lower and seemingly have a chance to pass stability testing.
> 
> Up next, drop IOD as well, any% speedrun to starving my CPU of voltage. Why? Just for fun!


Check aida latency when dropping IOD or SOC. When latency suddenly spikes by 2-3 you have the threshold where you need 0.01v higher


----------



## Nd4spdvn

Here is my latest play on a C15 set. Could not stabilize C14 ever (since last year when I was with a 5900x, now with X3D no difference in this respect)... Will try next the tWR/tRTP trick and see where that goes. Considering also to change the Aorus Pro V2 B550 mobo to a B550 Unify-X and a pair of DR B-die. Will that even make sense??
Speaking of DR B-Die is this a good candidate to pick F4-4000C16D-32GTZNA? Thanks for any input here, much appreciated!


----------



## Audioboxer

Taraquin said:


> Check aida latency when dropping IOD or SOC. When latency suddenly spikes by 2-3 you have the threshold where you need 0.01v higher


Yup, finding that out myself now. I first played around with dropping IOD, which is more obvious with stability than needing to run hours of testing lol

0.825v - Somehow booted, but audio was playing in slow motion LOL
0.85~0.875v - WHEA spam doing nothing
0.88~0.905v - WHEA when doing heavy stability testing
0.915v - No WHEA during 45 mins of y-cruncher, needs more testing

Then I seen your post and had a quick play around. It seems VDDP has no influence on AIDA latency (not ruling out running it really low could hurt in other benchmarks). As you pointed out CCD seems to be the main culprit.

At 0.78v on CCD, I was getting 55.2~55.8ns on latency.










Bumping it back up to 0.85v and I'm around 54ns. 53.9ns is the best I've ever recorded, so basically 54~54.1ns is just MoE stuff. Not to mention that 53.9ns is from months ago under a different AGESA, AIDA version, chipset drivers and even my PBO was slightly different back then.

So after some preliminary testing tonight it seems my voltages probably can come down, it's just balancing stability and making sure there is no performance loss. 0.78v is clearly just too low for CCD (performance penalties), even if it passed hours of stability testing.


----------



## Valka814

Looks like I found my issue on the way of a stability. Some settings dont change or work once I load a profile in bios. Example, Smart Acces Memory does not work after loading a profile, but everything says the opposite (GPU-Z, Radeon driver).
At the moment with my stable, tested settings, BSOD will happen in the next 2-3 hours if TM5 is running.
I have no clue what settings are effected, what "tested" setting I can trust, so I have to start from scratch. Gigabyte issue? Bios issue? Dont know, but its very annoying.


----------



## zerophase

Luggage said:


> If you have any fan over just jerry rig it towards the ram with case panel off and see if it helps.
> 
> 
> http://imgur.com/a/pThNKHr


I have a fan on them, but the case panel on. Think opening the panel might help?


----------



## Luggage

zerophase said:


> I have a fan on them, but the case panel on. Think opening the panel might help?


It’s a very easy thing to test?


----------



## Taraquin

Taraquin said:


> I may have been able to stabilize 3800cl14 at last  With a fan directed at ram that is. Seems RDWR and WRRD at auto did the trick. I also employed the 20\10 WR\RTP and slower RRD\FAW trick. RCDRD 14 seems impossible though. Even at 1.57v I get loads of error 2, 6, 10 and 12.
> 
> View attachment 2568152


It turned out that 1 lower CL and RP just compensated for slower WR/RTP, RRD/FAW and WTR. Performance was identical to flat 15. I tried lowering RRD/FAW and WR/RTP slightly, but had to increase voltage to 1.56v, and even then got some errors after a few rounds of TM5. Guess I have to stick with flat 15 at 1.47v and call it a day. Cool to know that cl14 could work, but will need better cooling for better performance.


----------



## Audioboxer

Went a little more conservative for the first longer test, rather than YOLO lowest voltage possible! In my experience with Karhu, if you can hit about 12000%+ with CPU cache enabled, you're all good.

So, interesting to see that it may well not be necessary to leave VDDP at a standard 0.9v, let alone the VDDGs anywhere near as high as mobo defaults. It wouldn't surprise me if the errors some people get with TM5/other apps when claiming they're on XMP is down to motherboard stupid auto defaults. XMP only really being the main timings and DRAM voltage, the motherboard manufacturers handling what their boards do with AUTO.

Some of the values for AUTO on VDDP/VDDGs are just insanity. 1.15v on CCD AND IOD, I mean, wut?

VSOC on AUTO seems fine, but I guess it could be interesting to have a poke around with it on manual and see if it can be run at like 1.05v or something. AUTO seems to jump around a bit between 1.06x~1.07x. VTT is another interesting one, on AUTO it's just half of VDIMM. But I have seen people manually set it lower.

So the fun and games begins with lowering voltages!


----------



## Frosted racquet

Audioboxer said:


> My only other suggestions then are
> 
> a) Update the BIOS, especially if you run Windows 11
> b) Make sure you're on these AMD chipset drivers https://www.amd.com/en/support/kb/release-notes/rn-ryzen-chipset-4-06-10-651
> c) If still failing on the above, create a bootable Windows USB and/or a secondary clean installation and try it. Alternatively, run TM5 in safe mode/diagnostic mode from current installation
> 
> When Windows 11 first came out there was a tremendous amount of AMD jank (especially with chipset drivers), one issue being weird overboosting issues that were leading to instability. This _could_ cause random core crashes.
> 
> Just keep in mind from AGESA 1.2.0.6 curve optimiser values often changed a bit for nearly everyone. So if you're looking to slot back in your old curve values, you might need to quickly check them again in the likes of corecycler.


Started testing in Safe Mode, got 1 or 2 error #4 1usmus in ~70 cycles. While testing in normal mode I would never get an error, just a random timeout.
Will experiment with Rtts and DrvStr values, I'm guessing I'm all good on 1.5v that VDIMM isn't the issue.

Will avoid updating chipset drivers and AGESA, not really willing to retest CO values.

Thanks again for the suggestions, Safe Mode was a really simple and obvious one, didn't really think about it.


----------



## MrDucky

Hmm trying to get my ram OC stable, first got some errors in TM5 1usmus_v3 so loosened some timings a bit. now i was stable for 1hr and then got a bluescreen *irql_not_less_or_equal *but no errors in TM5 up until that point?

Any idea's where to look now? Below are my settings.


----------



## hazium233

0xid0 said:


> I have a custom Whea Logger error display (image), any error it adds to the page, no whea and I haven't received a Whea in a while.
> 
> This Kernel Whea Event ID 20, would be a fix, but I saw that it would be a "Silent Whea" that over time corrupts the system.
> 
> I used on 3733/1866 the same configuration for a while and without any errors, Whea or Whea ID 20, but going up to 3800/1900 I have randomly ID 20, but ram tests are stable (image). I really wanted to correct, to keep a rounded number lol.
> 
> Any more suggestions to fix?
> 
> View attachment 2568083
> View attachment 2568085


If there is not a combination of SOC, VDDP, VDDG CCD, and VDDG IOD that eliminates them at 1900MHz, there really isn't anything else that will get rid of them. "PLL" or "1P8" voltage tweak may help, or may not.

Different hardware has different limits. You can try also many miscellaneous settings like Power Supply Idle Control, DF Cstate, or SOC P state, VRM settings, but none of those did much of anything for me.

If 3733 is perfectly stable, then really I would suggest just running that speed and enjoying the system without worrying.

...

It probably doesn't matter, but I don't know why you only see the WHEA 20 information event and not the "Warning" level event it corresponds to. But they don't log in the same place, the information events are in Application and Service Logs > Microsoft > Windows > Kernel-WHEA. The only WHEA I have left in my log right now is from a Sata device, where the easy way for me to find it is just the Overview and Summary page. That one is Error type (ID 1), the bus / Interconnect should be Warning type.

In the Errors sub log, it logs ID 20 whenever there is an error. Sometimes if you take the data field and covert from hex to text it may show the type of error or device that logged it. But on my system, whenever I have an event ID 20 there, I could see the corresponding Warning level event in the section I mentioned previously.


----------



## Audioboxer

Audioboxer said:


> View attachment 2568230
> 
> 
> Went a little more conservative for the first longer test, rather than YOLO lowest voltage possible! In my experience with Karhu, if you can hit about 12000%+ with CPU cache enabled, you're all good.
> 
> So, interesting to see that it may well not be necessary to leave VDDP at a standard 0.9v, let alone the VDDGs anywhere near as high as mobo defaults. It wouldn't surprise me if the errors some people get with TM5/other apps when claiming they're on XMP is down to motherboard stupid auto defaults. XMP only really being the main timings and DRAM voltage, the motherboard manufacturers handling what their boards do with AUTO.
> 
> Some of the values for AUTO on VDDP/VDDGs are just insanity. 1.15v on CCD AND IOD, I mean, wut?
> 
> VSOC on AUTO seems fine, but I guess it could be interesting to have a poke around with it on manual and see if it can be run at like 1.05v or something. AUTO seems to jump around a bit between 1.06x~1.07x. VTT is another interesting one, on AUTO it's just half of VDIMM. But I have seen people manually set it lower.
> 
> So the fun and games begins with lowering voltages!


Hmm, this tussle between lowest stable voltage and performance scaling is certainly interesting. Last night with the lower voltages, AIDA seemed like it wouldn't go below 54.1ns. A result that seemed fine, given my previous best is










53.9ns.










But I just tried my older voltages, minus dropping CCD from 0.975v to 0.9v. First time I've ever recorded 53.8ns. I can never usually be bothered running AIDA like 5 times, but I do remember months back when I got the 53.9ns I ran it like 20 times just to see if it would go any lower. It didn't.

Not as if 0.01ns means much, but hey, 53.8ns is now my lowest (outwith turning off a CCD to fake a 1 CCD 5950x).

Need to play around a lot more. It's possible it's just CCD behind any marginal increases. Then again, I'm running default PBO values on AGESA 1.2.0.7 (142/90/140) with a +100mhz boost. Just gave up on MT scores after the EDC jank BIOS cap by AMD.


----------



## MrDucky

Audioboxer said:


> Hmm, this tussle between lowest stable voltage and performance scaling is certainly interesting. Last night with the lower voltages, AIDA seemed like it wouldn't go below 54.1ns. A result that seemed fine, given my previous best is
> 
> View attachment 2568234
> 
> 
> 53.9ns.
> 
> View attachment 2568235
> 
> 
> But I just tried my older voltages, minus dropping CCD from 0.975v to 0.9v. First time I've ever recorded 53.8ns. I can never usually be bothered running AIDA like 5 times, but I do remember months back when I got the 53.9ns I ran it like 20 times just to see if it would go any lower. It didn't.
> 
> Not as if 0.01ns means much, but hey, 53.8ns is now my lowest (outwith turning off a CCD to fake a 1 CCD 5950x).
> 
> Need to play around a lot more. It's possible it's just CCD behind any marginal increases. Then again, I'm running default PBO values on AGESA 1.2.0.7 (142/90/140) with a +100mhz boost. Just gave up on MT scores after the EDC jank BIOS cap by AMD.


Isn't that just within a margin of error? since windows can be doing some stuff on the background. Maybe do some more testing on the lower voltages ?


----------



## MrDucky

MrDucky said:


> Hmm trying to get my ram OC stable, first got some errors in TM5 1usmus_v3 so loosened some timings a bit. now i was stable for 1hr and then got a bluescreen *irql_not_less_or_equal *but no errors in TM5 up until that point?
> 
> Any idea's where to look now? Below are my settings.
> 
> View attachment 2568232


Did another run and now it just finished the 7th cycle without errors but doesn't continue testing? I really have no idea where to look now.


----------



## Taraquin

Audioboxer said:


> View attachment 2568230
> 
> 
> Went a little more conservative for the first longer test, rather than YOLO lowest voltage possible! In my experience with Karhu, if you can hit about 12000%+ with CPU cache enabled, you're all good.
> 
> So, interesting to see that it may well not be necessary to leave VDDP at a standard 0.9v, let alone the VDDGs anywhere near as high as mobo defaults. It wouldn't surprise me if the errors some people get with TM5/other apps when claiming they're on XMP is down to motherboard stupid auto defaults. XMP only really being the main timings and DRAM voltage, the motherboard manufacturers handling what their boards do with AUTO.
> 
> Some of the values for AUTO on VDDP/VDDGs are just insanity. 1.15v on CCD AND IOD, I mean, wut?
> 
> VSOC on AUTO seems fine, but I guess it could be interesting to have a poke around with it on manual and see if it can be run at like 1.05v or something. AUTO seems to jump around a bit between 1.06x~1.07x. VTT is another interesting one, on AUTO it's just half of VDIMM. But I have seen people manually set it lower.
> 
> So the fun and games begins with lowering voltages!


Yeah, it seems most think: Error=too low voltage, in my experience it can be too high voltage stock, plus for temps etc, running lowest voltage is gold


----------



## Audioboxer

MrDucky said:


> Isn't that just within a margin of error? since windows can be doing some stuff on the background. Maybe do some more testing on the lower voltages ?


Could be, but I run in diagnostic mode which turns off all services it can, then it's just a case of closing everything in the task bar. So the test setup is, in theory, identical.

But yeah, unless I'm dropping down something like 0.03.ns+ it's not really worth noting. That being said, last night with VDDG voltages lower, especially CCD, resulted in me not even getting into 53.xns. So it's clear CCD helps with CPU performance scaling which in turns impacts latency.


----------



## Taraquin

Tip for temp and performance, find lowest VDD18 voltage at 76W PPT:
Stock 1.8v
Clockspeed 4575 avg
CB23 11725
Temp 74.2C
Fan rpm 1170

1.76v
Clockspeed 4600 avg
CB23 11774
Temp 72.6C
Fan rpm 1140

1.72v
Clockspeed 4600 avg
CB23 11843
Temp 72.2C
Fan rpm 1120

1.68v
Clockspeed 4625 avg
CB23 11872
Temp 72.4C
Fan rpm 1140

1.64v
Clockspeed 4625
CB23 11835
Temp 72.3C
Fan rpm 1140


----------



## Taraquin

At 1.6v VDD18 I got no further gains, but seems stable. Finding lowest VDD18 is a good way to shave off a couple of degrees and raise performance if PPT limited by 1-2%.

As for VDDP and CCD they are now at 790mv. 780mv gave me some instant reboots. 790mv seems fine, CB and aida performs the same, been stable for an hour now. Seems IO-die uses 1-2W less during load now vs both running at 820mv.

Audioboxer: If I remember correctly dual CCD CPUs tend to need higher CCD voltage than single CCD-CPUs. Somewhat logical


----------



## MrDucky

Upped some voltage and went for another round. Test failed when it was over 1 hour. Not really an idea where to go from here :/



Audioboxer said:


> Could be, but I run in diagnostic mode which turns off all services it can, then it's just a case of closing everything in the task bar. So the test setup is, in theory, identical.
> 
> But yeah, unless I'm dropping down something like 0.03.ns+ it's not really worth noting. That being said, last night with VDDG voltages lower, especially CCD, resulted in me not even getting into 53.xns. So it's clear CCD helps with CPU performance scaling which in turns impacts latency.


What do you mean with diagnostics mode?
Interesting to see that it might still be stable but just has a performance loss.


Taraquin said:


> Tip for temp and performance, find lowest VDD18 voltage at 76W PPT:
> Stock 1.8v
> Clockspeed 4575 avg
> CB23 11725
> Temp 74.2C
> Fan rpm 1170
> 
> 1.76v
> Clockspeed 4600 avg
> CB23 11774
> Temp 72.6C
> Fan rpm 1140
> 
> 1.72v
> Clockspeed 4600 avg
> CB23 11843
> Temp 72.2C
> Fan rpm 1120
> 
> 1.68v
> Clockspeed 4625 avg
> CB23 11872
> Temp 72.4C
> Fan rpm 1140
> 
> 1.64v
> Clockspeed 4625
> CB23 11835
> Temp 72.3C
> Fan rpm 1140


50 Mhz free clock speed! did your ram oc stability change?


----------



## Taraquin

MrDucky said:


> View attachment 2568266
> 
> View attachment 2568267
> 
> 
> Upped some voltage and went for another round. Test failed when it was over 1 hour. Not really an idea where to go from here :/


CJR or DJR? Try setting RDWR and WRRD to auto, may fix it.


----------



## MrDucky

CJR if i remember correctly. Will check RDWR and WRRD on auto. hopefully they don't increase too much.


----------



## Taraquin

MrDucky said:


> CJR if i remember correctly. Will check RDWR and WRRD on auto. hopefully they don't increase too much.


They usually end up at RDWR=RCDRD/2 and WRRD 4 or 6 below.


----------



## 0xid0

hazium233 said:


> If there is not a combination of SOC, VDDP, VDDG CCD, and VDDG IOD that eliminates them at 1900MHz, there really isn't anything else that will get rid of them. "PLL" or "1P8" voltage tweak may help, or may not.
> 
> Different hardware has different limits. You can try also many miscellaneous settings like Power Supply Idle Control, DF Cstate, or SOC P state, VRM settings, but none of those did much of anything for me.
> 
> If 3733 is perfectly stable, then really I would suggest just running that speed and enjoying the system without worrying.
> 
> ...
> 
> It probably doesn't matter, but I don't know why you only see the WHEA 20 information event and not the "Warning" level event it corresponds to. But they don't log in the same place, the information events are in Application and Service Logs > Microsoft > Windows > Kernel-WHEA. The only WHEA I have left in my log right now is from a Sata device, where the easy way for me to find it is just the Overview and Summary page. That one is Error type (ID 1), the bus / Interconnect should be Warning type.
> 
> In the Errors sub log, it logs ID 20 whenever there is an error. Sometimes if you take the data field and covert from hex to text it may show the type of error or device that logged it. But on my system, whenever I have an event ID 20 there, I could see the corresponding Warning level event in the section I mentioned previously.


Thanks for the answer. It really got better to see the errors in the event viewer going this way. (Image)

Now I would really appreciate the opinion of anyone who can answer my case, I managed to fix the ID 20 errors.

I had a few tricks up my sleeve to test before giving up, when I identified these errors through HWInfo, first thing I tested was raising all voltages Vsoc 1.15, CCD 1.1, IOD 1.1, VDDP 1.0, even going up didn't fix the problem , then I tried raising the PLL voltage 1.8 -> 1.85, it didn't fix it, on the previous page a user reported that he managed to get the voltages right, not too high, not too low, but at the right point, I started with IOD at 0.950 testing this in YCruncher ID20 errors happened a lot as in the image, I was adding more voltage 0.960, 0.970 until at 0.980 it took longer for these ID 20 errors to happen, so as tests above 1.00 I understood that it couldn't be the voltage the problem. I reviewed this topic and found something interesting and that's what stopped with Kernel Whea ID 20 errors for now, which was to change the TCKE from 1 to 9, I didn't have these errors anymore, the log is clean and for several test sequences in YCrncher it didn't I had more errors (Image). Not being able to understand well the concept of TCKE in Zen 3.

@Bloax user report.



Bloax said:


> tCKE actually has a rather bizarre +2 per (hard) 100 MCLK requirement on b-die sticks, 9 at 1900, 7 at 1800, 11 at 2000 - even so far as still requiring 11 at 2084 MCLK.
> 
> If tCKE 9 is still erroring, then it's likely overvoltage, or you not setting RDRD/WRWR _dd to -1 or -2 of _sd on 4x8
> 
> could also be RDWR/WRRD +/- whatever, annoying two settings


Changing TCKE from 1 to 9, for now I had no more problems, if you can tell me something about it? Even if you can suggest some improvement, I would be very grateful.


----------



## Audioboxer

MrDucky said:


> View attachment 2568266
> 
> View attachment 2568267
> 
> 
> Upped some voltage and went for another round. Test failed when it was over 1 hour. Not really an idea where to go from here :/
> 
> 
> What do you mean with diagnostics mode?
> Interesting to see that it might still be stable but just has a performance loss.
> 
> 
> 50 Mhz free clock speed! did your ram oc stability change?












It's basically just safe mode but you will auto boot into it on a restart until you go back to normal startup.

And yeah, totally possible to have something running stable but with performance degradation. Just down to the way core frequency boosting works.


----------



## MrDucky

Taraquin said:


> They usually end up at RDWR=RCDRD/2 and WRRD 4 or 6 below.


Set them on auto now but then it will become 8 and 5... so thats lower then i have. maybe i should try 8 and 6 then or 10 and 6 ?


----------



## hazium233

0xid0 said:


> Thanks for the answer. It really got better to see the errors in the event viewer going this way. (Image)
> 
> Now I would really appreciate the opinion of anyone who can answer my case, I managed to fix the ID 20 errors.
> 
> I had a few tricks up my sleeve to test before giving up, when I identified these errors through HWInfo, first thing I tested was raising all voltages Vsoc 1.15, CCD 1.1, IOD 1.1, VDDP 1.0, even going up didn't fix the problem , then I tried raising the PLL voltage 1.8 -> 1.85, it didn't fix it, on the previous page a user reported that he managed to get the voltages right, not too high, not too low, but at the right point, I started with IOD at 0.950 testing this in YCruncher ID20 errors happened a lot as in the image, I was adding more voltage 0.960, 0.970 until at 0.980 it took longer for these ID 20 errors to happen, so as tests above 1.00 I understood that it couldn't be the voltage the problem. I reviewed this topic and found something interesting and that's what stopped with Kernel Whea ID 20 errors for now, which was to change the TCKE from 1 to 9, I didn't have these errors anymore, the log is clean and for several test sequences in YCrncher it didn't I had more errors (Image). Not being able to understand well the concept of TCKE in Zen 3.
> 
> @Bloax user report.
> 
> 
> 
> Changing TCKE from 1 to 9, for now I had no more problems, if you can tell me something about it? Even if you can suggest some improvement, I would be very grateful.
> 
> View attachment 2568272
> View attachment 2568274
> View attachment 2568273


I don't get WHEA at 3800 using tCKE 1t so I don't know if that is another thing that depends on hardware combination or maybe bios / AGESA version.


----------



## 0xid0

hazium233 said:


> Eu não recebo WHEA em 3800 usando tCKE 1t, então não sei é outra coisa que depende disso de hardware ou talvez da versão bios / AGESA.
> [/CITAR]


Yes, I changed tCKE 1 -> 9, my Kernel WHEA ID 20 stopped, HWINFO didn't register anymore, as far as the Event Viewer, I tested it on YCruncher as in the photos in the previous post for 2 hours and I didn't have it anymore, remembering that are Kernel WHEA ID 20, not WHEA, HWINFO accuses them as "cpu bus/interconnect errors" and these are Kernel WHEA ID 20, so I'll test more, but for now I haven't had more.

Searching I found that it is related to Power Down, but that in Zen3 it has something more related, but I can't understand it well due to the translation.

If it's stable from now on, I'm almost satisfied, I confess that I'm more willing to extract a little more.


----------



## Taraquin

MrDucky said:


> Set them on auto now but then it will become 8 and 5... so thats lower then i have. maybe i should try 8 and 6 then or 10 and 6 ?


See if auto works  May be better.


----------



## 0xid0

Blackfyre said:


> *How did you create that custom WHEA Logger?* I would love to know. Thank you.


Hello friend, answering your question, sorry for the delay in answering.

I created a custom log of WHEA, Kernel WHEA (which was my terror and I was direct monitoring) and video failures for Nvidia (to overclock the video card).

Right click on Event Viewer > Create custom view > check box "by source" > under event sources search for Whea Logger > ok and rename as you wish.


----------



## KedarWolf

I've got some weird antivirus stuff going on, but not in the way you'd think. I installed Bitdefender Internet Security. First time I ran TM5A, it shaved 8 seconds off each cycle. I uninstalled Bitdefender, times were normal again. I reinstalled Bitdefender and ran TM5A from my traditional platter hard drive, it shaved a full 11 seconds off each cycle.

And it's really weird TM5A cycles finish faster on a traditional platter drive than a Gen 4 M.2 that does over 7400 MB/sec read, 6600 write.


----------



## Luggage

KedarWolf said:


> I've got some weird antivirus stuff going on, but not in the way you'd think. I installed Bitdefender Internet Security. First time I ran TM5A, it shaved 8 seconds off each cycle. I uninstalled Bitdefender, times were normal again. I reinstalled Bitdefender and ran TM5A from my traditional platter hard drive, it shaved a full 11 seconds off each cycle.
> 
> And it's really weird TM5A cycles finish faster on a traditional platter drive than a Gen 4 M.2 that does over 7400 MB/sec read, 6600 write.


Old usb memory stick next?


----------



## KedarWolf

Luggage said:


> Old usb memory stick next?


I found out why TM5 finishes faster with Bitdefender installed. The more services that are using memory, the less memory TM5 needs to test, so it finishes faster.

The platter drive I dunno though but it's a few seconds faster running it off one.


----------



## MrDucky

Got my setup stable today by upping the TFAW a bit more compared to previous. Now from here i'm going to put some other timings back down and try again


----------



## Taraquin

MrDucky said:


> View attachment 2568309
> 
> 
> 
> Got my setup stable today by upping the TFAW a bit more compared to previous. Now from here i'm going to put some other timings back down and try again


RRDSx4=FAW. I would try WR 16, RTP 8, RRDS 7, RRDL 9, FAW 28, if that works try RRDS 6, RRDL 8, FAW 24. Also try a bit more volt on ram. 1.45-1.45v probably works.


----------



## Audioboxer

After watching this video from Buildzoid (really recommend it)






It makes me wonder about this










Pic from last year when I was messing with maxmem, but something that still haunts me seeing 1.69v not only enough for tRCDRD 13, but tCL12! 1.65v is about where I crap out at full capacity.

But I think I can rule out me being capable of doing what Buildzoid did lol. Still would be interesting to know if externally powering the DDR4 allows B-die to run at a higher voltage at full capacity.


----------



## shnyaps

Audioboxer said:


> After watching this video from Buildzoid (really recommend it)
> 
> 
> 
> 
> 
> 
> It makes me wonder about this
> 
> View attachment 2568313
> 
> 
> Pic from last year when I was messing with maxmem, but something that still haunts me seeing 1.69v not only enough for tRCDRD 13, but tCL12! 1.65v is about where I crap out at full capacity.
> 
> But I think I can rule out me being capable of doing what Buildzoid did lol. Still would be interesting to know if externally powering the DDR4 allows B-die to run at a higher voltage at full capacity.


VDIMM 1.69V?
Is it just for testing?


----------



## Avacado

shnyaps said:


> VDIMM 1.69V?
> Is it just for testing?


Meh, Have gone to 1.8v with active air cooling for benches. No problems.


----------



## Audioboxer

shnyaps said:


> VDIMM 1.69V?
> Is it just for testing?


When you watercool your RAM voltage tends to mean very little in terms of heat. I've been as high as 1.95v with maxmem in use lol.

The challenge with B-die is that it doesn't handle high voltage well at full capacity. Around 1.65v is the highest most will be able to handle.

There are retail kits sold rated for 1.6v. Good cooling helps, but it's a bit of a myth that going over like 1.5v is dangerous (quite a lot of bad info about that online with DDR4).


----------



## shnyaps

Audioboxer said:


> When you watercool your RAM voltage tends to mean very little in terms of heat. I've been as high as 1.95v with maxmem in use lol.
> 
> The challenge with B-die is that it doesn't handle high voltage well at full capacity. Around 1.65v is the highest most will be able to handle.
> 
> There are retail kits sold rated for 1.6v. Good cooling helps, but it's a bit of a myth that going over like 1.5v is dangerous (quite a lot of bad info about that online with DDR4).


I thought for Ryzen UMC 1.6V+ is dangerous


----------



## Audioboxer

shnyaps said:


> I thought for Ryzen UMC 1.6V+ is dangerous


Nope, not that simple. Remember retail kits have to have headroom as well. No manufacturer is pushing out an XMP kit that is right on the edge of stability. So 1.6v rated kits will be consumer tested a bit above that.

If your temps are fine, you aren't running stupid resistances and memory stability testing apps are passing, you're fine.

Only thing I'd caution is if you're beginning to use something like maxmem you're into territory where you're running outside spec. As in, stable at full memory capacity is within spec.

It's very hard to kill memory as long as you aren't doing something really stupid. Usually that would involve resistances. Resistance combined with voltage _can_ be an issue.


----------



## Audioboxer

Doing some lower VDDP testing with TM5. Interestingly, that's it working with CkeDrvStr back down at 24. Looks like we need to step up to the 50 cycles again! Previously I believed going to 30 fixed a powering issue.


----------



## Audioboxer

Anyone know what this is? Sounds like the kind of cheat feature manufacturers add to their motherboard to fake synthetic scores


----------



## shnyaps

Audioboxer said:


> View attachment 2568332
> 
> 
> Anyone know what this is? Sounds like the kind of cheat feature manufacturers add to their motherboard to fake synthetic scores


When I tried this "feature" I got huge amount of errors


----------



## hazium233

Audioboxer said:


> View attachment 2568332
> 
> 
> Anyone know what this is? Sounds like the kind of cheat feature manufacturers add to their motherboard to fake synthetic scores


I tried it on my board, they didn't seem to do much of anything. I was hoping they could improve tPHYRDL but didn't seem to make a difference. Latency wasn't improved, at least in AIDA. I didn't run exhaustive benchmarks.

Also my motherboard is lower down the product stack, so maybe it does something on Unify series.


----------



## Bloax

0xid0 said:


> Yes, I changed tCKE 1 -> 9, my Kernel WHEA ID 20 stopped, HWINFO didn't register anymore, as far as the Event Viewer, I tested it on YCruncher as in the photos in the previous post for 2 hours and I didn't have it anymore, remembering that are Kernel WHEA ID 20, not WHEA, HWINFO accuses them as "cpu bus/interconnect errors" and these are Kernel WHEA ID 20, so I'll test more, but for now I haven't had more.
> 
> Searching I found that it is related to Power Down, but that in Zen3 it has something more related, but I can't understand it well due to the translation.
> 
> If it's stable from now on, I'm almost satisfied, I confess that I'm more willing to extract a little more.


CKE is a signal that is always used (it's called "ClocK Enable", hehe) and by setting its "minimum" width, we can offset the memory signal peak/valley by a desireable amount.
Slightly more visual example of what exactly is being nudged halfway down this post [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


MrDucky said:


> View attachment 2568309
> 
> 
> 
> Got my setup stable today by upping the TFAW a bit more compared to previous. Now from here i'm going to put some other timings back down and try again


And speaking of that post, this seems to be an example of somebody sacrificing performance (high RRD, odd WTRL, high tFAW) to make a lack of tCKE signal-nudging run stable.
seems to be, because I'm not psychic to tell if "just run tCKE 9 loool" is going to magically make RRD 4/6 tFAW 16 run on its own without procODT/RTT adjustments


----------



## Veii

shnyaps said:


> I thought for Ryzen UMC 1.6V+ is dangerous


running 1.67 daily since kind of a year
Including 1.27 SOC

SR dimms fail near 1.68-1.72v (PCB crash not death)
but voltage means barely anything


----------



## PJVol

shnyaps said:


> Ryzen UMC 1.6V+


UMC has nothing to do with DRAM voltage aka Vdimm, derived from its own VRM.


----------



## MrDucky

Taraquin said:


> RRDSx4=FAW. I would try WR 16, RTP 8, RRDS 7, RRDL 9, FAW 28, if that works try RRDS 6, RRDL 8, FAW 24. Also try a bit more volt on ram. 1.45-1.45v probably works.


I thought CJR would become instable above 1.4v.


----------



## Taraquin

MrDucky said:


> I thought CJR would become instable above 1.4v.


It may, some kits handle 1.45v well, others hate above 1.45v. Just try


----------



## Obtendo

4X CJR stable at 1.43v. 3800 is WHEA-free while 3866 give better results but spit a WHEA 19 every now and then. Been attempting to get rid of the occational WHEA 19 at 3866 without success. Both CPU and RAM tests fine without issues at 3866. Feel free to be critical of timings. tRDRDSD and DD seems to have bandwith regression at 4 allthough I read 4 is the way to go for dualrank..?


----------



## MrDucky

Bloax said:


> CKE is a signal that is always used (it's called "ClocK Enable", hehe) and by setting its "minimum" width, we can offset the memory signal peak/valley by a desireable amount.
> Slightly more visual example of what exactly is being nudged halfway down this post [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> And speaking of that post, this seems to be an example of somebody sacrificing performance (high RRD, odd WTRL, high tFAW) to make a lack of tCKE signal-nudging run stable.
> seems to be, because I'm not psychic to tell if "just run tCKE 9 loool" is going to magically make RRD 4/6 tFAW 16 run on its own without procODT/RTT adjustments


So if i up my tCKE to 9 and maybe change my procODT/RTT i would theoretically be able to run lower RRD and tFAW? I'm still very new to DDR4 overclocking and used the guide here: MemTestHelper/DDR4 OC Guide.md at oc-guide · integralfx/MemTestHelper

This mentioned nothing about tCKE so i would love to know more how to get that to the sweetspot 




Obtendo said:


> 4X CJR stable at 1.43v. 3800 is WHEA-free while 3866 give better results but spit a WHEA 19 every now and then. Been attempting to get rid of the occational WHEA 19 at 3866 without success. Both CPU and RAM tests fine without issues at 3866. Feel free to be critical of timings. tRDRDSD and DD seems to have bandwith regression at 4 allthough I read 4 is the way to go for dualrank..?
> 
> View attachment 2568398


What are your settings / timings on your 3800 stable setup? I also can't help but notice that your latency is low but the bandwith is also low? mine do 58xxx read.


----------



## Obtendo

MrDucky said:


> What are your settings / timings on your 3800 stable setup? I also can't help but notice that your latency is low but the bandwith is also low? mine do 58xxx read.


You get 58xx on a 5800X? I suppose something is more messed up than expected in my timings then.. At 3933 I get a decent bump in throughput, but latency is pretty much the same as 3866 as I have to loosen up secondaries. Stable at 3933 as well, but logs a lot of WHEA 19's. I for some reason seem to need more VSOC than most. At 3866 I get latency regression below 1.17v and get unstable below 1.13v.

Settings at 3800 are pretty identical to 3866:


----------



## MrDucky

Obtendo said:


> You get 58xx on a 5800X? I suppose something is more messed up than expected in my timings then..


Didn't notice it was a 5800x nevermind haha!


----------



## KedarWolf

MSI confirms Ryzen 7000 CPUs and X670 motherboards are set to launch on September 15th - VideoCardz.com


MSI X670 motherboards to launch mid-September Yesterday MSI revealed the design of its new X670 motherboards, today the company confirms when they launch. MSI confirms X670/Ryzen 7000 launch date, Source: MSI MSI has now confirmed exactly when the Ryzen 7000 and X670 motherboards launch and...




videocardz.com


----------



## domdtxdissar

Found my new AM5 motherboard 

*X670E Version of Asus Apex Motherboard PCB Diagram Leaked*
*








Finally a APEX AMD motherboard  *


----------



## Luggage

domdtxdissar said:


> Found my new AM5 motherboard
> 
> *X670E Version of Asus Apex Motherboard PCB Diagram Leaked*
> *
> View attachment 2568489
> 
> Finally a APEX AMD motherboard *


Just check cap orientation before you power it on


----------



## Taraquin

domdtxdissar said:


> Found my new AM5 motherboard
> 
> *X670E Version of Asus Apex Motherboard PCB Diagram Leaked*
> *
> View attachment 2568489
> 
> Finally a APEX AMD motherboard *


1DPC 😍 This will be a ram oc beast! After my experienced with Zen 2 and 3 I will try to find a cheap B650m 1DPC board if I go for 7000-series.


----------



## Bloax

Unfortunately then the reign of really cheap AM4 boards might be at an end, with Zen4 having proper clockspeed scaling unlike Zen3 (and especially Zen2 and older)

As that means motherboard VRM actually has an impact on what sort of performance you can hope to achieve, whereas on AM4 you pretty much stop seeing gains in videogames around 100W - which even the piddliest of motherboards can handle with good airflow.


practical examples include there being no good LGA1700 DDR4 2-DIMM boards that aren't suspicious Gigglebyte ITX boards, or have VRM setups that would struggle to keep even a 6+4 core well-fed (can hit 150-180 W if you're not careful)
_ahhhhhhhhhhhhhhhhhhh_

I do hope there will be good 2-DIMM boards that don't cost a fortune though, future DDR5 will be fun to put in a mineral oil aquarium.


----------



## Taraquin

Bloax said:


> Unfortunately then the reign of really cheap AM4 boards might be at an end, with Zen4 having proper clockspeed scaling unlike Zen3 (and especially Zen2 and older)
> 
> As that means motherboard VRM actually has an impact on what sort of performance you can hope to achieve, whereas on AM4 you pretty much stop seeing gains in videogames around 100W - which even the piddliest of motherboards can handle with good airflow.
> 
> 
> practical examples include there being no good LGA1700 DDR4 2-DIMM boards that aren't suspicious Gigglebyte ITX boards, or have VRM setups that would struggle to keep even a 6+4 core well-fed (can hit 150-180 W if you're not careful)
> _ahhhhhhhhhhhhhhhhhhh_
> 
> I do hope there will be good 2-DIMM boards that don't cost a fortune though, future DDR5 will be fun to put in a mineral oil aquarium.


All brands had several budget oriented ITX and mATX with 2 dimm only for B450/B550 so there should be choices for B650 aswell


----------



## KedarWolf

domdtxdissar said:


> Found my new AM5 motherboard
> 
> *X670E Version of Asus Apex Motherboard PCB Diagram Leaked*
> *
> View attachment 2568489
> 
> Finally a APEX AMD motherboard *


I started a thread for this board here. 









X670E Asus Apex Overclocking & Discussion Thread


First AMD Apex motherboard. 26-phase VRM https://www.tomshardware.com/news/pcb-diagram-asus-rog-apex-amd-board?_ga=2.221458264.1127200355.1654387128-2139277714.1642526100 "We could see this new Apex board featuring support well into the 7000MT/s range, if not 8000MT/s."...




www.overclock.net


----------



## zerophase

Luggage said:


> It’s a very easy thing to test?


ram got hotter doing that.


----------



## Dziarson

shnyaps said:


> VDIMM 1.69V?
> Is it just for testing?


B-die can hold much higher V then rest of the world.


----------



## blodflekk

I think I have found my best result with these timings. Stable 50 cycles 1usmus v3.vDIMM is 1.56.
Not sure about resistances and drive strengths. All on auto, except ProcODT which auto sets to 43.6 (heaps of errors) , increasing to 48 got me stable. Also set rttwr to 2 manually. Kit is teamgroup 3600 C14 @ 1.45v


----------



## Dziarson

Kingston FURY Renegade RGB 2x16 GB 6000 MHz CL 32. Test pamięci DDR5 o niskich opóźnieniach


Test pamięci DDR5 Kingston FURY Renegade RGB, z podświetleniem LED RGB oraz o niskich timingach CL 32. Sprawdź, co ma do zaoferowania.




ithardware.pl




Not bad mem .


----------



## Bloax

If you put a gun to my head and told me I had to move to AM5, I'd rather take up the challenge of making a ****ty (but cheap) DDR5 kit run "alright" on a 7600x or whatever, than buy any expensive DDR5 kit at the moment.

Why? Because first-generation DDR5 is still first-generation DDR5, however you try to slice it. A dressed-up pig, a polished turd, call it what you will.
I will be *very* disappointed if pretty affordable DDR5 kits don't make an embarassment of the current "high-end" within 12-18 months.

And within 12-18 months you'll even get your 3D-cache Zen4's that might actually be worth spending on, hehe.


----------



## Dziarson

@Bloax I payd 100$ more for my DDR4


----------



## Taraquin

Dziarson said:


> B-die can hold much higher V then rest of the world.
> 
> View attachment 2568548


Hynix DJR and Micron rev E seems to accept 1.7v+ aswell, not sure if they would tolerate 2v though


----------



## Dziarson

@Taraquin I think its more Temp problem not V B-die have no problem work whit high temp.


----------



## MrDucky

Bloax said:


> CKE is a signal that is always used (it's called "ClocK Enable", hehe) and by setting its "minimum" width, we can offset the memory signal peak/valley by a desireable amount.
> Slightly more visual example of what exactly is being nudged halfway down this post [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> And speaking of that post, this seems to be an example of somebody sacrificing performance (high RRD, odd WTRL, high tFAW) to make a lack of tCKE signal-nudging run stable.
> seems to be, because I'm not psychic to tell if "just run tCKE 9 loool" is going to magically make RRD 4/6 tFAW 16 run on its own without procODT/RTT adjustments


I tried using tCKE 9,RRD 4/6 tFAW 16 and i don't get errors in TM5 but after 10-15 minutes i get a bluescreen with kmode exception not handled. going to try some other values between 1-9 just to experiment but i don't really know what im doing at this point...


----------



## Taraquin

MrDucky said:


> I tried using tCKE 9,RRD 4/6 tFAW 16 and i don't get errors in TM5 but after 10-15 minutes i get a bluescreen with kmode exception not handled. going to try some other values between 1-9 just to experiment but i don't really know what im doing at this point...


Try RRD 5/7 FAW 20, see if it helps.


----------



## Taraquin

Dziarson said:


> @Taraquin I think its more Temp problem not V B-die have no problem work whit high temp.


Unless tuned, try running B-die tight at 60C+  Spews errors. Running xmp with slack RC/RFC is no issue at 70-80C. DJR and rev E handles tight timings + heat far better.


----------



## Taraquin

Not totally mem related, but damn, PBO+200 really makes core temp raise. Tried running Cyberpunk licked at 60fps highest, dlss 1080p:
-30 CO: 38-39W, 53-55C, 1.16-1.2v
-27x1, -30x5 +200 pbo: 43-44W, 60-62C, 1.28-1.34v D15 fan rpm 50-100 higher aswell

7C for 5W, that is some concentrated heat.


----------



## MrDucky

Taraquin said:


> Try RRD 5/7 FAW 20, see if it helps.


Trying 4/6/16 and 4 on tCKE now with 48Ohm procodt. 4 was the value on which erroring out took the longest so now checking if i can stabalize it with a other procODT value.

If that doesn't work im going to try 4/8/16 and otherwise 6/8/16


----------



## Audioboxer

> At the same time, the CPU's power consumption also saw a dramatic increase from 253W to 345W which is something that we mentioned exclusively a few days ago. That's a 36% increase in power for a 14% performance gain so definitely not the best performance efficiency gain here but those who don't care about their power bills would definitely end up using the "Unlimited Power" profile for the best performance.











Intel Core i9-13900K Raptor Lake CPU With 5.8 GHz Boost Clock, 350W "Unlimited Power Setting" Up To 67% Faster Than AMD Ryzen 9 5950X In Cinebench


Intel's Core i9-13900K Raptor Lake CPU offers a 5.8 GHz boost clock at 350W using Unlimited Power profile and beats the 5950X by 67%.




wccftech.com





I know moaning about power draw on an OCing forum is kind of funny, but it's also kind of funny manufacturers of CPUs/GPUs have just decided, screw it, our improvements going forward are just going to be throwing power at everything lol.

So we're going to have a 600w+ 4xxx GPU as standard, and a CPU with a single BIOS switch that enables 345w mode. RIP power supply makers and their worry about OCP/transients. RIP electricity bills at a time where costs are through the roof.

At least cold countries will literally have home heaters in the winter 

AMD really did just give us a generation of the magic sauce with the performance of the 5xxx range in comparison to its power draw.


----------



## The_King

Got some Patriot Viper 4000 C19s to play with. Really need to stop buying DDR4 RAM 

First impression of this kit is that it's really good and stable, I loaded a 4067 CL16 profile and gamed with it for hours no issues.

I see no reason to avoid this kit over the 4400 C19s which I also have. Still busy testing it. I wonder if this will do 3800 with RCD 14. 

Let's find out!


----------



## shnyaps

Dziarson said:


> B-die can hold much higher V then rest of the world.
> 
> View attachment 2568548


My post wasn't about RAM) it was about Ryzen Memory Controller and VDIMM


----------



## Dziarson

@shnyaps a te 2.0V to bylo myślisz o czym? wlasnie o VDIMM.


----------



## Taraquin

The_King said:


> Got some Patriot Viper 4000 C19s to play with. Really need to stop buying DDR4 RAM
> 
> First impression of this kit is that it's really good and stable, I loaded a 4067 CL16 profile and gamed with it for hours no issues.
> 
> I see no reason to avoid this kit over the 4400 C19s which I also have. Still busy testing it. I wonder if this will do 3800 with RCD 14.
> 
> Let's find out!
> View attachment 2568569


That is impressive. Those 4000c19 has better binning than my 4400c19 :/


----------



## Taraquin

MrDucky said:


> Trying 4/6/16 and 4 on tCKE now with 48Ohm procodt. 4 was the value on which erroring out took the longest so now checking if i can stabalize it with a other procODT value.
> 
> If that doesn't work im going to try 4/8/16 and otherwise 6/8/16


6/8/16 is no point since FAW=RRDSx4. Better to go 6/8/24 then or my faster alternative 5/7/20.


----------



## Bloax

Audioboxer said:


> Intel Core i9-13900K Raptor Lake CPU With 5.8 GHz Boost Clock, 350W "Unlimited Power Setting" Up To 67% Faster Than AMD Ryzen 9 5950X In Cinebench
> 
> 
> Intel's Core i9-13900K Raptor Lake CPU offers a 5.8 GHz boost clock at 350W using Unlimited Power profile and beats the 5950X by 67%.
> 
> 
> 
> 
> wccftech.com
> 
> 
> 
> 
> 
> I know moaning about power draw on an OCing forum is kind of funny, but it's also kind of funny manufacturers of CPUs/GPUs have just decided, screw it, our improvements going forward are just going to be throwing power at everything lol.
> 
> So we're going to have a 600w+ 4xxx GPU as standard, and a CPU with a single BIOS switch that enables 345w mode. RIP power supply makers and their worry about OCP/transients. RIP electricity bills at a time where costs are through the roof.
> 
> At least cold countries will literally have home heaters in the winter
> 
> AMD really did just give us a generation of the magic sauce with the performance of the 5xxx range in comparison to its power draw.


I don't subscribe to the "****ty stock overvolt/clock" reality chip vendors are pushing down our throats. (the 5800x is a stunning example of The Very Same Thing on AM4)
(I shall remind that the optimal ez-mode play with a 5800x, is run PBO with LOWER power limits and a mildly negative curve offset)







(HT off, 1.16v CPU)
tops out at 110 W full crank, 140 W in y-cruncher tasks so hard they crash at a cache/ring frequency above ~4050 mhz with e-cores enabled







otherwise draws 50-90 W (mostly heavy loading screens do the latter) in videogames
performs more than fine

It's a silly meme that modern chips are somehow inefficient furnaces.. Well, except for Rocket Lake, which genuinely is/was. :- )

These chips will probably run great with HT turned off, likely around 4.9-5.1 giggleherts at 1.10-1.20v, and the internal i7-9700 handling everything that isn't the foreground.
The latest and greatest in input latency sacrificing for the sake of superior throughput nshitia GPU GPU tech will likewise run fantastic, so long as you do what _they used to do_ - run it at a reasonable place in the Voltage/Frequency curve.


LowerThanStockClock.net, oh how we fall from grace...
but hey at least we clock our memory to the moon 🤭


----------



## MrDucky

Taraquin said:


> 6/8/16 is no point since FAW=RRDSx4. Better to go 6/8/24 then or my faster alternative 5/7/20.



For some reason TRRDL wont get stable below 8 so settled for 4/8/16. now on to lowering TWRTL and TWR and TCWL back down


----------



## Audioboxer

Bloax said:


> I don't subscribe to the "****ty stock overvolt/clock" reality chip vendors are pushing down our throats. (the 5800x is a stunning example of The Very Same Thing on AM4)
> (I shall remind that the optimal ez-mode play with a 5800x, is run PBO with LOWER power limits and a mildly negative curve offset)
> View attachment 2568576
> (HT off, 1.16v CPU)
> tops out at 110 W full crank, 140 W in y-cruncher tasks so hard they crash at a cache/ring frequency above ~4050 mhz with e-cores enabled
> View attachment 2568577
> 
> otherwise draws 50-90 W (mostly heavy loading screens do the latter) in videogames
> performs more than fine
> 
> It's a silly meme that modern chips are somehow inefficient furnaces.. Well, except for Rocket Lake, which genuinely is/was. :- )
> 
> These chips will probably run great with HT turned off, likely around 4.9-5.1 giggleherts at 1.10-1.20v, and the internal i7-9700 handling everything that isn't the foreground.
> The latest and greatest in input latency sacrificing for the sake of superior throughput nshitia GPU GPU tech will likewise run fantastic, so long as you do what _they used to do_ - run it at a reasonable place in the Voltage/Frequency curve.
> 
> 
> LowerThanStockClock.net, oh how we fall from grace...
> but hey at least we clock our memory to the moon 🤭


Well, put it this way, Intel going down this route has me thinking I would indeed be happier to stay with AMD. I know power draw is going up for the new chips, but efficiency still seems important to AMD.

Only thing I'm worried about is the memory controller and how bad BIOS bugs are with a new AMD launch. Still pretty sure I'll hold off and wait till DDR5 gets more mature and the first gen revision of the chips.


----------



## Luggage

Bloax said:


> I don't subscribe to the "****ty stock overvolt/clock" reality chip vendors are pushing down our throats. (the 5800x is a stunning example of The Very Same Thing on AM4)
> (I shall remind that the optimal ez-mode play with a 5800x, is run PBO with LOWER power limits and a mildly negative curve offset)
> View attachment 2568576
> (HT off, 1.16v CPU)
> tops out at 110 W full crank, 140 W in y-cruncher tasks so hard they crash at a cache/ring frequency above ~4050 mhz with e-cores enabled
> View attachment 2568577
> 
> otherwise draws 50-90 W (mostly heavy loading screens do the latter) in videogames
> performs more than fine
> 
> It's a silly meme that modern chips are somehow inefficient furnaces.. Well, except for Rocket Lake, which genuinely is/was. :- )
> 
> These chips will probably run great with HT turned off, likely around 4.9-5.1 giggleherts at 1.10-1.20v, and the internal i7-9700 handling everything that isn't the foreground.
> The latest and greatest in input latency sacrificing for the sake of superior throughput nshitia GPU GPU tech will likewise run fantastic, so long as you do what _they used to do_ - run it at a reasonable place in the Voltage/Frequency curve.
> 
> 
> LowerThanStockClock.net, oh how we fall from grace...
> but hey at least we clock our memory to the moon 🤭


Ez-mode 5800x is a chiller


http://imgur.com/mmdm5f6

(Or in my case - winter)


----------



## Veii

Audioboxer said:


> Only thing I'm worried about is the memory controller and how bad BIOS bugs are with a new AMD launch. Still pretty sure I'll hold off and wait till DDR5 gets more mature and the first gen revision of the chips.


Locked PMIC on most of the boards within exceptions
PHC IO dropouts from bellow 1.0.0.3 ~ fixed bef launch

Mostly fine in the current state
Bit of mem problems and boot issues
but ~7200 can work on 2 DPC boards


----------



## Taraquin

Veii said:


> Locked PMIC on most of the boards within exceptions
> PHC IO dropouts from bellow 1.0.0.3 ~ fixed bef launch
> 
> Mostly fine in the current state
> Bit of mem problems and boot issues
> but ~7200 can work on 2 DPC boards


How much of an advantage is 1DPC boards? Seems there is about 400MHz of advantage on ADL of 1DPC vs 2DPC. I bet this is gear 2 so actual IF is 1750MHz? With 1900MHz, 7600MHz should be doable, depends on how high Hynix M-die can go. Samsung 'B' maxes out around 6400 and Micron at 5600.

With the upcoming 3D chips ram speed will luckily matter less so buying a cheap 4800 2x16 Micron kit and OC to 5400-5600 may give close to the speed of a 7000 kit in most games due to 3D cache


----------



## Bloax

I couldn't tell you how much of an impact it's going to have, as I don't really see mentions of RTT/ProcODT and funny voltage hacks in DDR5 discussions.
(Drive strengths are voodoo blackbox stuff [no description, no range of acceptable values] on Intel, unfortunately)

But with 16 Gbit DDR5 being the 4 Gbit of DDR4, as well as 32 GB already being "a lot of memory" -
sooner rather than later, you will see 32 Gbit dual-rank DIMMs - that's 64 GB per stick.
That matches a 4x32 GB setup on DDR4, and goes much faster. I don't see the need for kneecapping your memeory performance for capacity you don't need.

edit:










Luggage said:


> Ez-mode 5800x is a chiller
> 
> 
> http://imgur.com/mmdm5f6
> 
> (Or in my case - winter)


DDR4-2133 JEDEC power draw numbers is cheating, full of micro-stalling. 🤭
Mine are with a 3828 14-14-12 2x8 setup that provides 2% below theoretical maximum bandwidth as well as crazy latency/utilization scaling (i.e. very good latency under <=80% load) 🍷


----------



## Veii

Taraquin said:


> How much of an advantage is 1DPC boards?


Foreign land 


Taraquin said:


> With the upcoming 3D chips ram speed will luckily matter less


Don't speak or know anything about RaphaelX3D. It's a mystery
In theory yes, in practice 4800 is really slow.
Current 3D till 3733 had near 10 % perf increase, and then till 4000 near 5%
Potentially lower

Bloax mentioned once, it's picking between beans and carrots
(hard to translate ~ potentially "as thick as thieves" is such a phrase)
Most of them are the same & from community reports feel ok at 1.65v VDD

Till people start digging with RTTs , and understanding symmetry better ~ they will hardwall
You pick gen 1 DDR5, you get gen1 speeds, till somebody cracks the code
7400 is not fast at all, but it's "currently the best, stable"
6400 is realistic on 2 DPC , 4 dimms
7200 is benchable

1DPC is still a foreign land
Hopefully more Vendors than ASUS would announce boards and B650E ending up not as a fairy tale.
Currently it's unclear about how open the platform will be
As pre-release it's quite bothersome but dealable with

I know it's marketing and riding the selling train
But i wish we wouldn't have to start with X670E
It can be much more useful after 8-10 months, not after 1-2 months
After bugs are ironed out & both PCH work better together


----------



## Taraquin

Veii said:


> Foreign land
> 
> Don't speak or know anything about RaphaelX3D. It's a mystery
> In theory yes, in practice 4800 is really slow.
> Current 3D till 3733 had near 10 % perf increase, and then till 4000 near 5%
> Potentially lower
> 
> Bloax mentioned once, it's picking between beans and carrots
> (hard to translate ~ potentially "as thick as thieves" is such a phrase)
> Most of them are the same & from community reports feel ok at 1.65v VDD
> 
> Till people start digging with RTTs , and understanding symmetry better ~ they will hardwall
> You pick gen 1 DDR5, you get gen1 speeds, till somebody cracks the code
> 7400 is not fast at all, but it's "currently the best, stable"
> 6400 is realistic on 2 DPC , 4 dimms
> 7200 is benchable
> 
> 1DPC is still a foreign land
> Hopefully more Vendors than ASUS would announce boards and B650E ending up not as a fairy tale.
> Currently it's unclear about how open the platform will be
> As pre-release it's quite bothersome but dealable with
> 
> I know it's marketing and riding the selling train
> But i wish we wouldn't have to start with X670E
> It can be much more useful after 8-10 months, not after 1-2 months
> After bugs are ironed out & both PCH work better together


On avg the improvements are generally below 10%. Going from 3600 xmp to 3733cl14 tuned i2hard only got 3% avg fps improvement when CPU bound on 3D. The 5800X vanilla got above 10% on same tuning. Some games like SOTTR don't scale with faster ram at all on 3D, while some scale good like certain racing-games.


----------



## Taraquin

DDR5-6000 Memory To Be The Sweet Spot For AMD Ryzen 7000 "Zen 4" CPUs, Will Offer 1:1 Infinity Fabric Ratio With EXPO


DDR5-6000 is looking to be the sweet spot for AMD Ryzen 7000 "Zen 4" AM5 Desktop CPUs, offering a 1:1 Infinity Fabric ratio with EXPO support.




wccftech.com





6000 1:1 sweetspot?  Means most will do 5800-6000, while a lucky few can do 6200+ (1DPC may be required?)


----------



## Bloax

Taraquin said:


> On avg the improvements are generally below 10%. Going from 3600 xmp to 3733cl14 tuned i2hard only got 3% avg fps improvement when CPU bound on 3D. The 5800X vanilla got above 10% on same tuning. Some games like SOTTR don't scale with faster ram at all on 3D, while some scale good like certain racing-games.











6.6% Average FPS improvement, 60% minimum FPS improvement, lies, damn lies, statistics.


----------



## Luggage

Bloax said:


> I couldn't tell you how much of an impact it's going to have, as I don't really see mentions of RTT/ProcODT and funny voltage hacks in DDR5 discussions.
> (Drive strengths are voodoo blackbox stuff [no description, no range of acceptable values] on Intel, unfortunately)
> 
> But with 16 Gbit DDR5 being the 4 Gbit of DDR4, as well as 32 GB already being "a lot of memory" -
> sooner rather than later, you will see 32 Gbit dual-rank DIMMs - that's 64 GB per stick.
> That matches a 4x32 GB setup on DDR4, and goes much faster. I don't see the need for kneecapping your memeory performance for capacity you don't need.
> 
> edit:
> View attachment 2568648
> 
> 
> 
> DDR4-2133 JEDEC power draw numbers is cheating, full of micro-stalling. 🤭
> Mine are with a 3828 14-14-12 2x8 setup that provides 2% below theoretical maximum bandwidth as well as crazy latency/utilization scaling (i.e. very good latency under <=80% load) 🍷


Never tried with only Ram oc and the rest default - only with full tune the same session.


http://imgur.com/sqTCsYG


(and running all benches in one series is kinda sub-optimal  )


----------



## Taraquin

Bloax said:


> View attachment 2568651
> 
> 6.6% Average FPS improvement, 60% minimum FPS improvement, lies, damn lies, statistics.


As I said, on avg, there are a few games that may greatly benefit, but the 3D cache in general makes ram speed\timings matter a lot less  For instance SOTTR. Avg only improved by 2%\6% min vs 13% avg and lows on 5800X. In Cyberpunk avg improved by 9%\lows 12% on 3D vs 16%\16% on 5800X so in a few games there may be a large difference, but in most it will be less than 5% due to the enormous cache.
Мог быть лучшим?! — Тест Ryzen 7 5800X3D vs i9-12900K vs R9 5900X и R7 5800X - YouTube


----------



## Blameless

Bloax said:


> View attachment 2568651
> 
> 6.6% Average FPS improvement, 60% minimum FPS improvement, lies, damn lies, statistics.


That 0.1% low is probably the most relevant figure as that's something that will really be common enough to impact perception throughout a session. Absolute minimum only happens once a run and even if it's not a fluke, likely represents a very transient dip that is easily ignored. But yeah, average isn't worth much in a gaming, or any, scenario where it's the lower end of performance that matters more.


----------



## Veii

There is not much more to comment on those posts
But let me remind you guys that 1500 UCLK is not fast. 1600 UCLK alright , but that's also not "fast"
We will play with different numbers and higher sizes. We will need to get used to bigger numbers and a different balance when design has shifted
But neither 6600 nor 7000 MT/s is perpendicular in size, than what early 2667MT/s was vs 4800-5000s current non used Frequencies.

The moment i see communities daily 8000MT/s, is when i can say "this is fast, it took a lot of effort and is advanced technology" // while it has to be a thing that is reached at least this year
Please don't cap off the glas and limit how high a trapped frog can jump
You only limit its and next generations potential.

All i can comment 
I'm just kind of proud, that the last 2 years here, this forum has focused on understanding that a lower value is not better.
It will be a useful skillset for working with DDR5


----------



## The_King

Taraquin said:


> That is impressive. Those 4000c19 has better binning than my 4400c19 :/


Looks like this may be a better bin than my 4400 C19s as well. Probably my best binned B-die kit at the moment even better than my G.Skill









Managed to break 50ns but needs more voltage to be stable at 4067 does not pass TM5. Maybe around 1.54V-1.55V to be stable or maybe lowering ProcODT?


----------



## Baio73

*TALKING ABOUT tRFC*

So, I lost all my RAM OC settings due to BIOS reflash and saved profiles that didn't work, so I'm in the process again...
Here is what I reached so far:



I can lower tRAS and tRC to 33//48 before getting error (5+ hours of Karhu), but when it comes to lower tRFC only Auto seems to work, also tried the Mini calculator.
So the question is... is tRFC somehow related to other values? Couldn't find anything around the net...
And using the tRFC Mini, should I also set tRFC 2 and 4? I thought one could leave them on Auto...


Baio


----------



## The_King

Took 1.55V to pass


----------



## Taraquin

The_King said:


> Looks like this may be a better bin than my 4400 C19s as well. Probably my best binned B-die kit at the moment even better than my G.Skill
> View attachment 2568709
> 
> 
> Managed to break 50ns but needs more voltage to be stable at 4067 does not pass TM5. Maybe around 1.54V-1.55V to be stable or maybe lowering ProcODT?
> View attachment 2568710
> View attachment 2568711


Yeah, if cooling is good enough. 4000c19 should be a very low bin so you got lucky


----------



## The_King

Taraquin said:


> Yeah, if cooling is good enough. 4000c19 should be a very low bin so you got lucky


Looks like Voltage tolerants is also good it seems fine with 1.55V with no active airflow . Around 33 degrees C here today which is good has its usually 43C! 😅


----------



## Taraquin

The_King said:


> Took 1.55V to pass
> View attachment 2568712
> View attachment 2568713


Very good. You are lucky getting no WHEA19 with 4dimm mobo  I would check linpack if performance scales above 3800. I needed to raise VDD18 voltage to get equal performance in linpack at 4000 vs 3800. Gaming, aida etc was 2-3% better with 4000. Was it Blackout or Steel you bought?


----------



## The_King

Taraquin said:


> Very good. You are lucky getting no WHEA19 with 4dimm mobo  I would check linpack if performance scales above 3800. I needed to raise VDD18 voltage to get equal performance in linpack at 4000 vs 3800. Gaming, aida etc was 2-3% better with 4000. Was it Blackout or Steel you bought?


I asked this question before also checked on the Msi forums. I can't find the option to adjust VDD18 (CPU 1.8V?) on my B450M Mobo. I looked through all the OC settings even advanced. Unless there is a hidden option in the BIOS or its under something else.

Just passed 3800 with flat 14s so Im really happy about that. My others kits struggle with this.









It's Viper Steel


----------



## Taraquin

The_King said:


> I asked this question before also checked on the Msi forums. I can't find the option to adjust VDD18 (CPU 1.8V?) on my B450M Mobo. I looked through all the OC settings even advanced. Unless there is a hidden option in the BIOS or its under something else.
> 
> Just passed 3800 with flat 14s so Im really happy about that. My others kits struggle with this.
> View attachment 2568718
> 
> 
> It's Viper Steel


My 4400c19 can pass 3800 14-15-14 at 1.52v with a fan blowing, but I have to use 6/8/16 RRDS/FAW and 20/10 WR/RTP so vs 3800 15-15-15, 4/6/16 and 10/5 performance is identical. At 1.55v overheat issues start since the fan is not very powerful. I may buy a 4000c19 kit to test, if I get as lucky as you it should be a good investment.

Not all MBs has VDD18 control. Check linpack at 3800 and 4067, see if you get scaling. If negative I would stick yo 3800, if neutral or positive I would go for 4000 or 4067. I get 1-2% negative unless I raise VDD18 by 80mv. Unfortunately VDD18 affects CPU temp, I get 3-4C higher temps using 1.88v vs 1.6v which runs fine at 3800.


----------



## The_King

Taraquin said:


> My 4400c19 can pass 3800 14-15-14 at 1.52v with a fan blowing, but I have to use 6/8/16 RRDS/FAW and 20/10 WR/RTP so vs 3800 15-15-15, 4/6/16 and 10/5 performance is identical. At 1.55v overheat issues start since the fan is not very powerful. I may buy a 4000c19 kit to test, if I get as lucky as you it should be a good investment.
> 
> Not all MBs has VDD18 control. Check linpack at 3800 and 4067, see if you get scaling. If negative I would stick yo 3800, if neutral or positive I would go for 4000 or 4067. I get 1-2% negative unless I raise VDD18 by 80mv. Unfortunately VDD18 affects CPU temp, I get 3-4C higher temps using 1.88v vs 1.6v which runs fine at 3800.


This kit and my 4400 can do 3800 CL15 with 1.44V-1.45V so going almost 0.1v higher to get 3800 CL/RCD 14 is not worth the performance increase which doesnt seem to be alot or noticable for me as well when comparing 3800 CL14 to 3800 CL15 from my current test data with AIDA, Y-cruncger and 7-Zzp. FPS in games seems about the same as well.

I will probably still run 3800 CL15 or maybe 4000 CL16 for daily and only use above 1.5V for bechmarking tests only. 

Linpack will be a good test to run but will spend some time with that over the weekend.

Now the fun part begins. Going to try to run this with my 4400 for DR performance increase which is much more noticable than lowering CL or RCD


----------



## KedarWolf

The_King said:


> I asked this question before also checked on the Msi forums. I can't find the option to adjust VDD18 (CPU 1.8V?) on my B450M Mobo. I looked through all the OC settings even advanced. Unless there is a hidden option in the BIOS or its under something else.
> 
> Just passed 3800 with flat 14s so Im really happy about that. My others kits struggle with this.
> View attachment 2568718
> 
> 
> It's Viper Steel


You want to edit the .cfg file to 25 cycles, 3 not near enough to be considered stable.


----------



## The_King

KedarWolf said:


> You want to edit the .cfg file to 25 cycles, 3 not near enough to be considered stable.


Passing 25 cycles does not guarantee 100% stability. I have seen people pass 25 cycles TM5 but fail to run Y-cruncher or OCCT in some cases. 

Since I am not planing to run over 1.5V for daily I probably wont bother running 25 cycles at the moment or until my motherboard is placed into a case with some air flow. 
At the moment it's basically sitting on the mobo box.


----------



## Taraquin

The_King said:


> I asked this question before also checked on the Msi forums. I can't find the option to adjust VDD18 (CPU 1.8V?) on my B450M Mobo. I looked through all the OC settings even advanced. Unless there is a hidden option in the BIOS or its under something else.
> 
> Just passed 3800 with flat 14s so Im really happy about that. My others kits struggle with this.
> View attachment 2568718
> 
> 
> It's Viper Steel


Remember that RFC impacts gaming most. At 1.55v I bet 240 can be doable. RDWR may do 7 or 8 btw, works on my setup.


----------



## heptilion

Audioboxer said:


> I guess you could technically view it as "just run as low as you can go", but inherently thinking a resistance _has_ to be low to be good/perform better would be the wrong way to think about from what I've learned.
> 
> They also aid in helping power the DIMMs, so that, I believe, is related to signal integrity. For example, good luck running ClkDrvStr at 20 if you're trying to push 3800/1T with DR. Nearly everyone ends up running 40, I've seen 30 OK a few times.
> 
> The Rtts are sometimes what cause NO POST when they are simply set at something that does not work with your combination of frequency and timings. Other times, they'll post but can either fail TM5 or cause other issues.
> 
> View attachment 2566282
> 
> 
> That's my daily. I can run RttPark at 5, boots fine and I let it do an hour of TM5 and it was fine, but, reason I stopped TM5 is because tPHYRDL trains at 26/30 instead of 26/26. So, 4 is as weak as I could go and not impact performance. But 5 boots, IIRC 6 might as well, but 7 definitely doesn't.
> 
> That is, 7 doesn't boot when RttWr is at 3. I need to make RttWr stronger (1) to boot RttPark 7. You see, they often influence each other. The real end game of memory tuning, the timings are ez-mode compared to the resistances lol. More so if you're pushing really high frequency on DDR4, or if you're looking at DR with 1T.


are you able to share the rest of your bios settings as well please. what did you adjust to get procodt to 28.2?


----------



## The_King

Taraquin said:


> Remember that RFC impacts gaming most. At 1.55v I bet 240 can be doable. RDWR may do 7 or 8 btw, works on my setup.


I can do RDWR 8 only if I change ProcODT to 28.2 its actually 9 at the moment. I have Proc on Auto.

Both my 4000/4400 kits can do RFC 248 at 1.5V 130ns. I got the 4400 kit to 124ns with higher voltage.
at 1.45V RFC 256 and 266 (140ns) does not cause any issue. 266 is very stable at 3800 on both kits with 1.44V-1.45V.


----------



## Audioboxer

heptilion said:


> are you able to share the rest of your bios settings as well please. what did you adjust to get procodt to 28.2?


My BIOS is quite basic tbh, everything on AUTO apart from rebar turned on for GPU, then the memory settings you see and voltage settings and finally my CPU is set to PBO Advanced, 162/100/140 for PBO settings, my curve, a +100mhz boost, telemetry set to 150A with a 45ma offset and that's about it.

ProcODT came quite late for me (I used to run 34.3), Veii helped me to understand resistances a bit more and make sure if using a lower ProcODT there are no issues with tPHYRDL training. I'm going to guess it's not really BIOS settings that help me, but a B550 Unify X (2 DIMM motherboard) and just the B-Die bin being one of the best.

IIRC from what Veii taught me it's likely that due to the 2 DIMM board there is better quality signal integrity, which means a better chance at "cleaner" powering.


----------



## MrHoof

Taraquin said:


> Remember that RFC impacts gaming most. At 1.55v I bet 240 can be doable. RDWR may do 7 or 8 btw, works on my setup.


tRDWR 7 works only for a few that depends mostly on the motherboard not the RAM atleast all 3 kits(b-die) that I tried 2x 8GB and 1x 16GB could all run 7.


----------



## Taraquin

MrHoof said:


> tRDWR 7 works only for a few that depends mostly on the motherboard not the RAM atleast all 3 kits(b-die) that I tried 2x 8GB and 1x 16GB could all run 7.
> View attachment 2568783


When CL is at 14 my MB trains RDWR 7 and WRRD 3 on auto.


----------



## MrHoof

Taraquin said:


> When CL is at 14 my MB trains RDWR 7 and WRRD 3 on auto.


7/1 works for my 8GB kits but anything below 7/3 or even 8/2 does not work for the 16GB one, it needs atleast tWRRD 3.


----------



## Veii

RCD_RD/2 = RDWR ~ SR
RCD_RD/2 +2 = tRDWR ~ DR
Micron -1
Hynix -2
up to DIMM PCB


----------



## KedarWolf

Memory Platinum stability certificate - 8/10/2022 10:41:21 PM 00:00:00 - Info


















Memory stability certificate ( Platinum ) started at 2022-08-10 06:39:57
00:00:00 - Info - Memory - Started (Duration : 05:00:00)
05:00:01 - Info - Memory - Stopped
05:00:01 - Info - Memory - Started (Duration : 05:00:00)
10:00:01 - Info - Memory - Stopped
10:00:01 - Info - CPU - Started (Duration : 02:00:00)
12:00:01 - Info - CPU - Stopped
12:00:01 - Info - CPU - Benchmark started
12:00:12 - Info - CPU - 1 threads, SSE : 88.73
12:00:12 - Info - CPU - Benchmark started
12:00:23 - Info - CPU - 32 threads, SSE : 1 305.24
12:00:23 - Info - CPU - Benchmark started
12:00:34 - Info - CPU - 1 threads, AVX : 169.15
12:00:34 - Info - CPU - Benchmark started
12:00:45 - Info - CPU - 32 threads, AVX : 2 399.54
12:00:45 - Info - Memory - Benchmark started
12:00:56 - Info - Memory - Read : 1 406.11
12:00:56 - Info - Memory - Benchmark started
12:01:07 - Info - Memory - Write : 1 166.69
12:01:07 - Info - Memory - Benchmark started
12:01:18 - Info - Memory - Combined : 1 270.33
12:01:19 - Info - Test schedule completed


----------



## The_King

Veii said:


> RCD_RD/2 = RDWR ~ SR
> RCD_RD/2 +2 = tRDWR ~ DR
> Micron -1
> Hynix -2
> up to DIMM PCB


Thanks for that info.
Is there a full list/post with all the timing rules like this for B-die and Micron etc? trfc mini has some but I don't recall seeing the RDWR rule there.
How is your Micron ram testing going any updates?



Taraquin said:


> Remember that RFC impacts gaming most. At 1.55v I bet 240 can be doable. RDWR may do 7 or 8 btw, works on my setup.


Looks like RDWR 7 is working great. Thanks for that tip 

RFC 240 does boot but it may need more than 1.55V, I don't want to go over this at the moment without any airflow on the ram.

I am confident at this point this will do TCL 13 at +1.6V

Got no errors with 5 cycles with 14-14-14-28-42 with RDWR 7 but 1 error with these settings.
Will try procODT at 28.2 also PHYRDL is 28. According to @Veii its not good for it to be 28.
Any further advice or tips are welcome. Thanks guys.


----------



## Taraquin

Veii said:


> RCD_RD/2 = RDWR ~ SR
> RCD_RD/2 +2 = tRDWR ~ DR
> Micron -1
> Hynix -2
> up to DIMM PCB


On my MB on auto RCDRD 14 trains RDWR 7/WRRD 3, RCDRD 15/16 trains 8/2.


----------



## Taraquin

MrHoof said:


> 7/1 works for my 8GB kits but anything below 7/3 or even 8/2 does not work for the 16GB one, it needs atleast tWRRD 3.


Dual rank supposedly likes 3 and sometimes higher WRRD if I remember correctly?


----------



## MrHoof

Taraquin said:


> Dual rank supposedly likes 3 and sometimes higher WRRD if I remember correctly?


Fun fact i think this exactly the reason why I cant hit 58000MB/s read on my DR kit.


Spoiler: SR

















Spoiler: DR


----------



## KedarWolf

Got my fastest SMT-enabled DRAM Calculator MemBench and y-cruncher today.

Got my memory and CPU OCCT Platinum Stability Test stable. Passes y-cruncher and TM5 as well.


----------



## domdtxdissar

Still no ddr5 thread so i will just post it here:

*G.Skill Readies DDR5-6000 CL30 16 GB Trident Z5 Memory Modules With EXPO Support For AMD Ryzen 7000 CPUs* 



> The specific memory kit from G.Skill is the "F5-6000J3038F16G" and judging from its name, it is a single-stick memory module that operates at DDR5-6000 transfer rates and has timings rated at CL30-38-38-96. For comparison, the lowest latency kit you can get with XMP support for the Intel CPU platform is the "F5-6000J3040F16G" which is rated at the same DDR5-6000 speeds but slightly higher timings of CL-30-40-40-96. Both memory modules are expected to be rated at 1.35-1.45V.





> Just a few days ago, we reported that DDR5-6000 will be the sweet spot for AMD Ryzen 7000 CPUs based on the Zen 4 core architecture using the EXPO technology. The DDR5-6000 memory kits that are optimized with EXPO support will offer the best performance with the lowest latency in a 1:1 FCLK (3 GHz). However, for those who want to benefit from higher bandwidth, there will be faster DDR5 DIMM offerings and we have seen speeds of up to DDR5-6400 which we have been told is a very entry-level push-up from where the overclocking speeds are actually going to end up.


----------



## domdtxdissar

Dont think this video have been posted here, i found it interesting atleast





If you want more after watching the first part:


----------



## KedarWolf

Deleted, sold out.


----------



## Sanju.ro

Hey, guys, been a long time lurker on this thread. I've used what I gathered from your efforts and comments to come up with these timings on my ram. Can you give me 
an opinion? As you can see I'm not shooting for max IF or voltages, but good all around performance and most importantly stable. Thanks!


----------



## domdtxdissar

Sanju.ro said:


> Hey, guys, been a long time lurker on this thread. I've used what I gathered from your efforts and comments to come up with these timings on my ram. Can you give me
> an opinion? As you can see I'm not shooting for max IF or voltages, but good all around performance and most importantly stable. Thanks!
> View attachment 2569127


Seems like a decent timing set for very easy to run everyday settings with bdie, but there is performance to be gained by:
tRRDS = 4
tRRDL = 4
tFAW = 16


----------



## Sanju.ro

domdtxdissar said:


> Seems like a decent timing set for very easy to run everyday settings with bdie, but there is performance to be gained by:
> tRRDS = 4
> tRRDL = 4
> tFAW = 16


Thank you for taking the time to look at the settings and for the video! Never knew that Aida can be so unreliable. Will give your recommendations a shot and see how it goes.


----------



## mnathani98

Hey, what do you guys consider the max voltage to daily for B-Die with active cooling? I was going through here and i read Veii using 1.67v for about a year. This got me interested so i tried 3800 CL13. At 1.59v I got to login screen with a BSOD, bumped to 1.62v and ran Anta Absolut which errored after 2 mins. Bumped up to 1.65v which made it error after 4 mins. From my current 3800 CL14 i get 52ns consistently and with CL13 i did 2 runs and it did 52 on first and 51.6 on second. Any suggestions to make CL13 stable? Current setup attached below.


----------



## The_King

mnathani98 said:


> Hey, what do you guys consider the max voltage to daily for B-Die with active cooling? I was going through here and i read Veii using 1.67v for about a year. This got me interested so i tried 3800 CL13. At 1.59v I got to login screen with a BSOD, bumped to 1.62v and ran Anta Absolut which errored after 2 mins. Bumped up to 1.65v which made it error after 4 mins. From my current 3800 CL14 i get 52ns consistently and with CL13 i did 2 runs and it did 52 on first and 51.6 on second. Any suggestions to make CL13 stable? Current setup attached below.


If you after lower latency in AIDA64 then you should look at increasing MT frequency than going higher voltage and lower tCL.


Spoiler: 4067 CL15


----------



## mnathani98

The_King said:


> If you after lower latency in AIDA64 then you should look at increasing MT frequency than going higher voltage and lower tCL.
> 
> 
> Spoiler: 4067 CL15
> 
> 
> 
> 
> View attachment 2569305


I can do higher FCLK but only at stock cpu settings and i don't want to give up my PBO setup hence im going for CL13. And while i understand it is pretty unreasonable to pump about 1.65v for 0.5ns of improvement i just wanna do it for the kick of it. Will try loosening tRFC to 288 just to see if it was that. My original question was is it "fine" to daily something like 1.65v?


----------



## Bloax

mnathani98 said:


> Any suggestions to make CL13 stable? Current setup attached below.


Find the lowest voltage at which +1 on all the primary timings runs, subtract it from the voltage your current config runs at.
Add that much voltage when trying to make tCL -1 run, probably one or two steps lower will be where it behaves itself.

If it refuses to run stable, regardless of +/- 0.03 vDIMM from the calculated voltage (including all the in-between values, in the smallest steps possible on your board) - congratulations, you've run into either a DIMM or Memory Controller limit.
If raising tFAW by a multiple of RRD_s or WTR_L (i.e. throwing **** at the wall, tFAW 24, 32 ...) cures this instability at one of those voltages, then it was a memory controller limit. (worse performance = runs stable)
If it does not, then it is a DIMM limit - it's simply never going to run that setting long-term stable, only good for benchmarks.


----------



## Audioboxer

AMD Ryzen 7000 and Socket AM5 alleged BIOS issues pushed availability date back


According to a new report, AMD is allegedly facing firmware issues with its upcoming Socket AM5 and Ryzen 7000 series CPUs, which are set to launch at the end of this month on August 29.




www.neowin.net





AMD BIOS issues again, say it isn't so 😂


----------



## Taraquin

Audioboxer said:


> AMD Ryzen 7000 and Socket AM5 alleged BIOS issues pushed availability date back
> 
> 
> According to a new report, AMD is allegedly facing firmware issues with its upcoming Socket AM5 and Ryzen 7000 series CPUs, which are set to launch at the end of this month on August 29.
> 
> 
> 
> 
> www.neowin.net
> 
> 
> 
> 
> 
> AMD BIOS issues again, say it isn't so 😂


Not surprised. Agesa is good in some ways, but the Intel approach where MB-makers do much more of the bios themselves can be a viable approach, but you must spend much more money for good OC support etc, while a basic B450 from Biostar can give the same RAM-tuning possibilities as a X570 Unify due to agesa.


----------



## Unifyx

and the question is...

which Agesa is the most stable for RAM overclocking?
which for CPU overclocking?
and wich for both?

My experience with 1.1.0.0C, 1.2.0.1, 1.2.0.2 and 1.2.0.3b
all of them did the same RAM oc, stable with my settings. ( I didn't try to extremely overclock the RAM )








1.1.0.0C had the best performance with the same RAM settings with CPU at stock settings.

I am on a MSI unify-x with a 5900x.

would be great to read your experience 😊


----------



## SpeedyIV

I am trying to figure out why I keep getting WHEA 19 corrected hardware errors. They are always for Processor APID ID:0. They occur every time I try to overclock my RAM.

System: Asus Dark Hero, 5950X, 2 x G.Skill F4-3200C14D-32GTZR 16GB CL14-14-34 B-Die, Asus TUF 3080 GPU
BIOS 4201, AGESA ComboV2PI 1207, Win10 Pro 21H2 19044.0889
Bios (other than RAM settings) is at defaults - no PBO, no CO, PPT, TDC, EDC all on Auto.

I verified B-Die with Thaiphoon Burner and have used the Ryzen DRAM calculator as a starting point. I was able to do 3600MHz @14-14-14-28 2T (GDM disabled) and run Kahru, TestMem, and MemTest Pro for hours with no errors, but I get these WHEA 19 errors popping up. Some days none, some days a few, and some days every ~30-min.

I slowed things down to 3200MHz, tried just XMP with everything else on Auto, raised VDIMM in steps up to 1.45V, raised VSOC in steps up to 1.1V, tried GDM on, loosened 2nd's and 3rd's. The only time the WHEA-19 errors stop for good is when I set the RAM back to stock 2133MHz @15-15-15-36. What I haven't done is adjust ProcODT, Rtt's, ClkDrvStr, AddrCmdDrvStr, CsOdrtDrvStr, or CkeDrvStr. I am still learning about these settings. I have been entering the settings in Extreme Tweaker but know that they also appear under the AMD Overclocking section. I have read many conflicting posts about which area of the Bios to use. I have not tried doing it in the AMD section.

I was beginning to think that the WHEA-19 errors were not caused by RAM overclock - maybe a problem with the CPU, or a driver or OS bug. Since the WHEA's stop when I take the RAM back to defaults, I am back to thinking it's my overclock.

Here are Zen Timings screenshots for 3600, 3200, and DOCP from left to right. What am I doing wrong? Any advice is appreciated.


----------



## kairi_zeroblade

Audioboxer said:


> AMD Ryzen 7000 and Socket AM5 alleged BIOS issues pushed availability date back
> 
> 
> According to a new report, AMD is allegedly facing firmware issues with its upcoming Socket AM5 and Ryzen 7000 series CPUs, which are set to launch at the end of this month on August 29.
> 
> 
> 
> 
> www.neowin.net
> 
> 
> 
> 
> 
> AMD BIOS issues again, say it isn't so 😂


nothing new, actually..

When I hopped in the AM4 territory from my previous Intel platform this was the horrendous part of owning it..(the former platform I had was very easy to manage in that regard)


----------



## ReyReverse

SpeedyIV said:


> I am trying to figure out why I keep getting WHEA 19 corrected hardware errors. They are always for Processor APID ID:0. They occur every time I try to overclock my RAM.
> 
> System: Asus Dark Hero, 5950X, 2 x G.Skill F4-3200C14D-32GTZR 16GB CL14-14-34 B-Die, Asus TUF 3080 GPU
> BIOS 4201, AGESA ComboV2PI 1207, Win10 Pro 21H2 19044.0889
> Bios (other than RAM settings) is at defaults - no PBO, no CO, PPT, TDC, EDC all on Auto.
> 
> I verified B-Die with Thaiphoon Burner and have used the Ryzen DRAM calculator as a starting point. I was able to do 3600MHz @14-14-14-28 2T (GDM disabled) and run Kahru, TestMem, and MemTest Pro for hours with no errors, but I get these WHEA 19 errors popping up. Some days none, some days a few, and some days every ~30-min.
> 
> I slowed things down to 3200MHz, tried just XMP with everything else on Auto, raised VDIMM in steps up to 1.45V, raised VSOC in steps up to 1.1V, tried GDM on, loosened 2nd's and 3rd's. The only time the WHEA-19 errors stop for good is when I set the RAM back to stock 2133MHz @15-15-15-36. What I haven't done is adjust ProcODT, Rtt's, ClkDrvStr, AddrCmdDrvStr, CsOdrtDrvStr, or CkeDrvStr. I am still learning about these settings. I have been entering the settings in Extreme Tweaker but know that they also appear under the AMD Overclocking section. I have read many conflicting posts about which area of the Bios to use. I have not tried doing it in the AMD section.
> 
> I was beginning to think that the WHEA-19 errors were not caused by RAM overclock - maybe a problem with the CPU, or a driver or OS bug. Since the WHEA's stop when I take the RAM back to defaults, I am back to thinking it's my overclock.
> 
> Here are Zen Timings screenshots for 3600, 3200, and DOCP from left to right. What am I doing wrong? Any advice is appreciated.
> View attachment 2569635
> View attachment 2569636
> View attachment 2569637


Download and silicone v/f 
Go bios - >load default settings 
DO NOT ON XMP/docp, let everything default
then open program silicone v/f check your CPU score


----------



## ManniX-ITA

SpeedyIV said:


> Here are Zen Timings screenshots for 3600, 3200, and DOCP from left to right. What am I doing wrong? Any advice is appreciated.


Probably means something is off with the Infinity Fabric. It shouldn't happen at 3200 MHz.

The difference with 2133 MHz mode is that the IF will clock down dynamically.
You should see in HWInfo that it goes up & down in frequency.

If you have a chance to RMA the CPU, I would do it.
But you need to tell AMD that you get WHEA 19 at 2133 MHz.
Just enabling XMP is considered overclock hence not covered by warranty.

If you want to try to fix it there aren't many options.

First you probably need an out of ordinary voltage setup; try with 1.2V SOC and 1100mV VDDG IOD.
Then look in the AMD menus for "Uncore OC" or similar and try forcing it enable.
Also look in AMD CBS menu for DF C State, not sure it's available on the Dark Hero, and try it both with force it Enable or Disable.

What could help is forcing a stronger LLC for VSOC.

Remember to keep a delta of at least 60mV between VDDG CCD/IOD and VSOC.

In the Zentimings 3600 MHz you have 1.1 VSOC (down to 1.08V with LLC) and 1050mV IOD.
You should have VSOC in Zentimings read at least 1.1V to be safe.


----------



## SpeedyIV

ManniX-ITA said:


> Probably means something is off with the Infinity Fabric. It shouldn't happen at 3200 MHz.
> 
> The difference with 2133 MHz mode is that the IF will clock down dynamically.
> You should see in HWInfo that it goes up & down in frequency.
> 
> If you have a chance to RMA the CPU, I would do it.
> But you need to tell AMD that you get WHEA 19 at 2133 MHz.
> Just enabling XMP is considered overclock hence not covered by warranty.
> 
> If you want to try to fix it there aren't many options.
> 
> First you probably need an out of ordinary voltage setup; try with 1.2V SOC and 1100mV VDDG IOD.
> Then look in the AMD menus for "Uncore OC" or similar and try forcing it enable.
> Also look in AMD CBS menu for DF C State, not sure it's available on the Dark Hero, and try it both with force it Enable or Disable.
> 
> What could help is forcing a stronger LLC for VSOC.
> 
> Remember to keep a delta of at least 60mV between VDDG CCD/IOD and VSOC.
> 
> In the Zentimings 3600 MHz you have 1.1 VSOC (down to 1.08V with LLC) and 1050mV IOD.
> You should have VSOC in Zentimings read at least 1.1V to be safe.


Thanks for your input. I bought the CPU in Feb of 2021 so I don't think I can return it after 18 months. I will look into it. I have been fighting with this on and off for a long time. I have a huge spreadsheet of various timings I have tried.

I will try increasing VSOC to 1.2V, which seems awfully high but worth a try. I will also try adjusting VSOC LLC to keep it from drooping too much. I will check for Uncore OC and DF C-State. Someone else suggested increasing VCore to core 01 a little since the WHEA-19 is always for APIC ID:0. These WHEA errors occur during idle/low CPU load so maybe that core just needs a little more juice. I could also try 1 DIMM at a time (maybe a bad DIMM?) or swap in another 3200CL14 kit that I have in another machine. I really hope it's not the CPU!


----------



## SpeedyIV

ReyReverse said:


> Download and silicone v/f
> Go bios - >load default settings
> DO NOT ON XMP/docp, let everything default
> then open program silicone v/f check your CPU score


Thanks for your response. I am not familiar with "silicone v/f" and a Google search did not return anything that looked like a CPU benchmark program. Can you post a link?

I have run Cinebench R23 and my scores are reasonable for an untweaked 5950X (~1600 single, ~24,000 multi). Scores are higher with PBO enabled (multi ~3200). I have not dialed in a CO curve because I want to get the RAM OC stable first. As I mentioned, it will pass hours of Kahru, TestMem, and MemTest Pro but I still get these WHEA 19 errors, always APID ID:0.


----------



## ManniX-ITA

SpeedyIV said:


> Thanks for your input. I bought the CPU in Feb of 2021 so I don't think I can return it after 18 months. I will look into it. I have been fighting with this on and off for a long time. I have a huge spreadsheet of various timings I have tried.
> 
> I will try increasing VSOC to 1.2V, which seems awfully high but worth a try. I will also try adjusting VSOC LLC to keep it from drooping too much. I will check for Uncore OC and DF C-State. Someone else suggested increasing VCore to core 01 a little since the WHEA-19 is always for APIC ID:0. These WHEA errors occur during idle/low CPU load so maybe that core just needs a little more juice. I could also try 1 DIMM at a time (maybe a bad DIMM?) or swap in another 3200CL14 kit that I have in another machine. I really hope it's not the CPU!


WHEA-19 with APIC ID: 0 could be also messages not coming from a CPU core, there's a little chance.
You can't increase vCore on a single core.
What you can do is enable PBO and CO and set a positive offset for Core 0.
I had to do so for my 5950X which was not stable on the best core without it, had to set a positive count of +2.
What you can try is a small vCore positive offset.
Start with the lowest step and go up.
But going over 250mV usually is degrading performances.


----------



## umea

SpeedyIV said:


> Thanks for your input. I bought the CPU in Feb of 2021 so I don't think I can return it after 18 months. I will look into it. I have been fighting with this on and off for a long time. I have a huge spreadsheet of various timings I have tried.
> 
> I will try increasing VSOC to 1.2V, which seems awfully high but worth a try. I will also try adjusting VSOC LLC to keep it from drooping too much. I will check for Uncore OC and DF C-State. Someone else suggested increasing VCore to core 01 a little since the WHEA-19 is always for APIC ID:0. These WHEA errors occur during idle/low CPU load so maybe that core just needs a little more juice. I could also try 1 DIMM at a time (maybe a bad DIMM?) or swap in another 3200CL14 kit that I have in another machine. I really hope it's not the CPU!


Might be worth a shot to take a look at this https://www.amd.com/en/support/kb/warranty-information/pib


----------



## ReyReverse

SpeedyIV said:


> Thanks for your response. I am not familiar with "silicone v/f" and a Google search did not return anything that looked like a CPU benchmark program. Can you post a link?
> 
> I have run Cinebench R23 and my scores are reasonable for an untweaked 5950X (~1600 single, ~24,000 multi). Scores are higher with PBO enabled (multi ~3200). I have not dialed in a CO curve because I want to get the RAM OC stable first. As I mentioned, it will pass hours of Kahru, TestMem, and MemTest Pro but I still get these WHEA 19 errors, always APID ID:0.








AMD Ryzen Silicon Tester (AMD V/F) | CyberMania







www.cybermania.ws





Download from here ,don't worry It's safe.
Remember, must run the program in default mode, no cpu and ram overclock 
Then tell me your score


----------



## SpeedyIV

ReyReverse said:


> AMD Ryzen Silicon Tester (AMD V/F) | CyberMania
> 
> 
> 
> 
> 
> 
> 
> www.cybermania.ws
> 
> 
> 
> 
> 
> Download from here ,don't worry It's safe.
> Remember, must run the program in default mode, no cpu and ram overclock
> Then tell me your score


I got an immediate warning screen in Chrome. I bypassed the warning and tried to download the file. Chrome blocked it. I was kind of leery about installing this. Is it normal to get this warning and the download blocked? I have had this happen occasionally with downloads from mega.nz.

Possibly using poor judgment, I downloaded the file using another browser and extracted it. There are a number of .exe. files. I am not sure how to run the test you are asking for. I tried running Tool.exe, then DB Query - > AMD V/F - > Get Sil Quality. Is this what you are after? If yes, the number it came back with was -8.30549. No RAM OC, no PBO/CO. All overclocking-related things in the Bios on Auto.

I clicked around and tried some of the other functions in this utility. It looks like it can do some pretty interesting things but I would need some documentation to figure out what some of them do.


----------



## SpeedyIV

ManniX-ITA said:


> WHEA-19 with APIC ID: 0 could be also messages not coming from a CPU core, there's a little chance.
> You can't increase vCore on a single core.
> What you can do is enable PBO and CO and set a positive offset for Core 0.
> I had to do so for my 5950X which was not stable on the best core without it, had to set a positive count of +2.
> What you can try is a small vCore positive offset.
> Start with the lowest step and go up.
> But going over 250mV usually is degrading performances.


Thanks for your response. Yes I meant to send core 1 a little more voltage using CO. Ryzen Master says my Core 1 is my best core on CCX1 and it's the core that the WHEA-19 error points to (APIC ID-0). Is it odd that the "best core" would also be the core that needs more VCore? I definitely will go up slowly. I am going to push VSOC up a little too and adjust the VSOC LLC to reduce droop (another suggestion). 

Any opinion on whether I should enable PBO and set the CO offset from Extreme Tweaker or from the AMD OC section of my bios (Asus Dark Hero)? Pretty much all of the OC settings are available in both areas and I have read many conflicting opinions about which area of the Bios works best. Thanks!


----------



## ReyReverse

SpeedyIV said:


> I got an immediate warning screen in Chrome. I bypassed the warning and tried to download the file. Chrome blocked it. I appreciate your (and everyone's) help but I am leery of installing this. Is it normal to get this warning and the download blocked? I have had this happen occasionally with downloads from mega.nz.
> View attachment 2569708
> View attachment 2569709


It's safe.


----------



## SpeedyIV

ReyReverse said:


> It's safe.


Thanks. I edited my post again after I ran the program. I think I did the Get Sil Quality procedure correctly but I ran it a few times and got widely different results. What does this mean?


----------



## ReyReverse

SpeedyIV said:


> Thanks. I edited my post again after I ran the program. I think I did the Get Sil Quality procedure correctly but I ran it a few times and got widely different results. What does this mean?
> 
> View attachment 2569721
> View attachment 2569722
> View attachment 2569723


hi do you have go bios set everything default?

if yes, that mean your cpu silicon quality is 119.365
its good enough to hit 3600 -3733 above. 
it must be somewhere wrong that made you APIC :0
that problem probably not from your CPU


----------



## ManniX-ITA

ReyReverse said:


> if yes, that mean your cpu silicon quality is 119.365
> its good enough to hit 3600 -3733 above.
> it must be somewhere wrong that made you APIC :0
> that problem probably not from your CPU


The sil quality is a calculated metric from CPPC tags and I guess also FIT data.
It's not going to tell you if you have a problem or not.
This data is serialized in the CPU at the end of the production line after some testing.
Unfortunately sometimes this testing it's not very reliable and some CPUs get serialized with wrong information, either too optimistic or too less.
It's not a reliable information to guess the IF max frequency the CPU can support.



SpeedyIV said:


> Is it odd that the "best core" would also be the core that needs more VCore?


Yes it doesn't happen normally and it usually means something is wrong.
My best core ends up being the 2nd best instead of the 1st due to the +2 count.
Which is a pity since we can't control the scheduler priorities; the actual best one can't be used fully in ST.



SpeedyIV said:


> Any opinion on whether I should enable PBO and set the CO offset from Extreme Tweaker or from the AMD OC section of my bios (Asus Dark Hero)?


Sorry I don't know the board that much.
Try first from the Extreme Tweaker.
Check if the settings are properly applied via software.


----------



## ReyReverse

ManniX-ITA said:


> The sil quality is a calculated metric from CPPC tags and I guess also FIT data.
> It's not going to tell you if you have a problem or not.
> This data is serialized in the CPU at the end of the production line after some testing.
> Unfortunately sometimes this testing it's not very reliable and some CPUs get serialized with wrong information, either too optimistic or too less.
> It's not a reliable information to guess the IF max frequency the CPU can support.


max frequency of the CPU is not the point, Get Sil quality is.
bios-> load default ,no cpu overclock no ram overclock (not even XMP on), then only use Amd V/F check sil quality. 
123-125 is S grade quality best of the best. if compare with year 2021 that patch Sil quality score most of em is below 120 

so you can see lot of people complaint about their memory not boot at 3800MHz 
AMD 5000 ryzen 7 or ryzen 9 and do RMA wants to claim back the new one.


----------



## ReyReverse

SpeedyIV said:


> Thanks. I edited my post again after I ran the program. I think I did the Get Sil Quality procedure correctly but I ran it a few times and got widely different results. What does this mean?
> 
> View attachment 2569721
> View attachment 2569722
> View attachment 2569723


I just realize your Sil quality score is -10.2274, I never have this issue.
are you sure your bios load default mode already?


----------



## domdtxdissar

The calculated silicon quality from that program dont really tell you anything..

I tested 4 different 5950x's here, all got a ~116-117 rating at stock settings (no pbo co) even though one of the cpu were clearly better than the rest.
(my first cpu is "first batch" produced week 46 in 2020)


> Asus tool = "116 silicon quality" and "4381mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4525mhz --> 4.05 rating = *Golden CCD*
> CCD #1 = 4325mhz --> 3.87 rating = *Bronze CCD*





> Asus tool = "117.5 silicon quality" and "4394mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4575mhz --> 4.11 rating = *Platinum CCD*
> CCD #1 = 4475mhz --> 4.02 rating = *Golden CCD*





> Asus tool = "116.5 silicon quality" and "4386mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4575mhz --> 4.09 rating = *Golden CCD*
> CCD #1 = 4475mhz --> 4 rating = *Golden CCD*





> Asus tool = "116 silicon quality" and "4382mhz max heavy load"
> 
> Hydra: CCD quality
> CCD #1 = 4625mhz --> 4.14 rating = *Platinum CCD*
> CCD #1 = 4500mhz --> 4.03 rating = *Golden CCD*


More information with full cpu steppings etc in link above..
My mainpoint is that those AMD V/F "silicon quality" numbers are useless and dont mean anything, Hydra is much better to use if you want to check your cpu quality..

This is my "endgame" hydra diagnostic stats with everything tweaked and better cooling with liquid metal etc using the best cpu from above


SpeedyIV said:


> If yes, the number it came back with was -8.30549. No RAM OC, no PBO/CO. All overclocking-related things in the Bios on Auto.


Probably because you had Hwninfo open while running it if i were to guess..
When running this program you need to close all other programs that reads temps/clocks, otherwise it can error out with "cpu mutex busy" and give you a error number like that.


----------



## Unifyx

is there anything else I can change or tighten up to get more performance?










tRFC is not going any lower.
The only difference between the sticks is the tPHYRDL 28/26 and I don't know what that means.
I want to try to get 1T GDM off, but dont know where to start and if I have to loosen some timings to get it to work.

The actual settings are working 24/7 and are passing all stresstests. The memory temperature is getting up to 55°C on both sticks and don't error.
VDIMM is 1.45 in the BIOS.

The biggest problem that I have is, that I don't know what all this Voltage settings in the BIOS are for and which ones help for RAM overclocking and which for CPU / infinity fabric overclocking.


----------



## SpeedyIV

ReyReverse said:


> hi do you have go bios set everything default?
> 
> if yes, that mean your cpu silicon quality is 119.365
> its good enough to hit 3600 -3733 above.
> it must be somewhere wrong that made you APIC :0
> that problem probably not from your CPU


Ok thank you. Is that considered a reasonable score for Silicone Quality?

Yes everything OC related in the Bios is set to defaults. There are a few things in the Bios I set including:

Ignore CPU fan speed (I am not using the mobo for fan control)
Disable download of Armoury Crate (an Asus utility that I do not use)
Set Q-Code LEDs to display CPU temp after boot (because why not?)
Enable discrete TPM (I have a TPM module)
Set PCIE slot 1 to Gen4 (Asus TUF 3080)
Set M2.1 Link mode to Gen 4 (Samsung 980 Pro)
I don't think any of these settings will affect or cause the WHEA-19 errors which never occur unless my RAM is overclocked.


----------



## SpeedyIV

domdtxdissar said:


> The calculated silicon quality from that program dont really tell you anything..
> 
> Probably because you had Hwninfo open while running it if i were to guess..
> When running this program you need to close all other programs that reads temps/clocks, otherwise it can error out with "cpu mutex busy" and give you a error number like that.


I do use HWINFO and SIV (not gigabyte SIV) but I shut them both down before running the silicone quality test. Aquasuite was running but all sensor polling is disabled in the program. Also the silicone quality test did not error out. It returned negative numbers between -8 and -10 except for one run that returned 119.365. You mentioned an Asus Silicone Quality tool. Is this a different utility that I should try?

I tried Hydra once. It ran diagnostics for hours then crashed and lost all the data. I still subscribe to Yuri's Patreon and may try it again with v1.2C Pro but it seems that all of his latest changes have to do with adding AMD GPU support (my GPU is an RTX 3080). Maybe I will try v1.2C pro and see if it does better.


----------



## Valka814

Can you guys tell me in what order should do the memory overclock? What I mean by that:
1. 2T
2. Primaries
3. Secondaries
4. Territaries
5. RTT
6. Cad Bus


----------



## Blackfyre

Valka814 said:


> Can you guys tell me in what order should do the memory overclock? What I mean by that:
> 1. 2T
> 2. Primaries
> 3. Secondaries
> 4. Territaries
> 5. RTT
> 6. Cad Bus


1. No CPU Overclock and No PBO2 changes; to test RAM overclock stability, especially if tuning all aspects, we want the CPU at stock first.

2. I personally run XMP or AOCP first, make sure everything works with the official RAM profile.

3. Everything you listed, in that order. I combine 3 & 4 into one step and 5 & 6 into one step.

Important things that are not listed, are:

1. All the voltages & VRM controls that can be changed to fine-tune the RAM overclock, those are adjusted with all the steps and changed depending on what's needed.

2. The Advanced Overclock Tweaks, such as the changes under AMD CBS


----------



## Melan

Valka814 said:


> Can you guys tell me in what order should do the memory overclock? What I mean by that:
> 1. 2T
> 2. Primaries
> 3. Secondaries
> 4. Territaries
> 5. RTT
> 6. Cad Bus











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


how much voltage you run is completely dependent on what IC you have. most of the people here are running b-die which can run much higher voltages safely, i believe veii's daily is 1.6v and hasn't had any problems. most of us run 1.5v or higher fine as well Definitely, I'm not arguing against...




www.overclock.net


----------



## xpulse

Hi, Overclockers,
I am asking for help with overclocking RAM in my system.

System:
MB Asus PRIME x570-Pro, latest BIOS
RAM: 4 sticks G.Skill F4-3600C16-16GTZN: 16-16-16-36-1T; Total 64 GB
CPU: Ryzen 5800x

Have a problem running these sticks (4) together on nominal 3600Hz in the system. 
All together starting only on 3533. When I tested dims separated all 4 DIMMs running (by 2) on 3733 easily without changing DOCP settings.
The problem is: on this speed, the new RAM set is the same speed as my previous 64 GB 2933Mhz, with the same latency but a little faster.

Need some help with letting a set of 4 DIMMs run on 3600 or if possible higher speed.



















Thank you all for any suggestions.


----------



## ManniX-ITA

xpulse said:


> Have a problem running these sticks (4) together on nominal 3600Hz in the system.
> All together starting only on 3533. When I tested dims separated all 4 DIMMs running (by 2) on 3733 easily without changing DOCP settings.


I'd first try swapping the order.
Shuffle the sticks in the slots, could be that's just it.

Otherwise try setting manual these parameters:










Then test with a bit lower or higher ProcODT.


----------



## vitor.furlann

Hello guys, I would appreciate your help, it's my first time at OC, just built the following machine:

AMD Ryzen 7 5700G
Asrock B450m Steel Legend
Corsair Vengeance LPX 16GB 3600mhz (1x16, i'm using it in single channel)

Enabled the XMP on Bios, but I don't think it's stable cause it's resulting in a black screen when I restart the machine

Also, on DRAM Voltage, the XMP profile has set it to 1.35, but it's written in red, is that right?


----------



## The_King

vitor.furlann said:


> Hello guys, I would appreciate your help, it's my first time at OC, just built the following machine:
> 
> AMD Ryzen 7 5700G
> Asrock B450m Steel Legend
> Corsair Vengeance LPX 16GB 3600mhz (1x16, i'm using it in single channel)
> 
> Enabled the XMP on Bios, but I don't think it's stable cause it's resulting in a black screen when I restart the machine
> 
> Also, on DRAM Voltage, the XMP profile has set it to 1.35, but it's written in red, is that right?


XMP can run on a single DIMM. Just make sure it's installed in the correct slot which should be A2 for a single DIMM.


----------



## ManniX-ITA

vitor.furlann said:


> Also, on DRAM Voltage, the XMP profile has set it to 1.35, but it's written in red, is that right?


The DIMM voltage is right.

I have just built my home server/NAS with a 5600G.
If you have stability issues raise VDDCR_SOC to 1.27V and set a strong LLC.
It is still a safe voltage. I've read that who's overclocking it's keeping it at 1.35V.
I can confirm the default 1.1V is not stable for me even with Windows.


----------



## shnyaps

xpulse said:


> Hi, Overclockers,
> I am asking for help with overclocking RAM in my system.
> 
> System:
> MB Asus PRIME x570-Pro, latest BIOS
> RAM: 4 sticks G.Skill F4-3600C16-16GTZN: 16-16-16-36-1T; Total 64 GB
> CPU: Ryzen 5800x
> 
> Have a problem running these sticks (4) together on nominal 3600Hz in the system.
> All together starting only on 3533. When I tested dims separated all 4 DIMMs running (by 2) on 3733 easily without changing DOCP settings.
> The problem is: on this speed, the new RAM set is the same speed as my previous 64 GB 2933Mhz, with the same latency but a little faster.
> 
> Need some help with letting a set of 4 DIMMs run on 3600 or if possible higher speed.
> 
> View attachment 2569788
> 
> View attachment 2569789
> 
> 
> 
> Thank you all for any suggestions.


I had similar problem. 4 dual rank sticks are too hard for ryzen. I have 4x32GB 4000 gskill VDIMM 1.4V, to start them on xmp speed I should increase volatge.
At the moment they are working at 3800 MHz (1900 MHZ), voltage is 1.57V.

P.S. When I tried 2 sticks only everything was fine with default VDIMM

So try 2 sticks, after this you could increase voltage step by step if you want)


----------



## PJVol

SpeedyIV said:


> and it's the core that the WHEA-19 error points to (APIC ID-0)


WHEA errors, if their source is MCA, aren't interpreted this way. First you should find out which bank is associated with error 19.
Usually it's 27 that points to the PIE controller as the source. Some errors are thread related (core banks - load/store, L2, etc.), some not (Non-core - L3, NBIO, UMC, etc.) The latter usually raised in thread 0 unrelated to the core itself.
PIE controller is part of Data and Control Fabric, so raised corrected error exception usually mean it's unstable.


----------



## ManniX-ITA

Does anyone has good profiles to share for APU and Viper Steel 4400?

I have this 5600G that seems to run stable with 1:1 2166/4333 MHz, have to test again 2200/4400 MHz.
Anything above 4000 MHz is appreciated.


----------



## byDenoso

For 2x8 SR configurations, whats the optimal powering voltages and resistances?
I'm using 28,2ohm on ProcODT, Cad Bus 40-30-30-24 and RTTs 6/3/5
I also noticed than the SD's and DD's has no effect on 2x8SR setup.


----------



## Valka814

SoC, Ram voltage, tCL, tRCDWR, tRCDRD, tRP, tRAS set, the rest is auto. TM5 hangs sooner or later.


----------



## Frosted racquet

Valka814 said:


> SoC, Ram voltage, tCL, tRCDWR, tRCDRD, tRP, tRAS set, the rest is auto. TM5 hangs sooner or later.
> View attachment 2569931


Try running TM5 in Safe Mode, it can help with troubleshooting if it's a software or hardware issue.


----------



## SpeedyIV

PJVol said:


> WHEA errors, if their source is MCA, aren't interpreted this way. First you should find out which bank is associated with error 19.
> Usually it's 27 that points to the PIE controller as the source. Some errors are thread related (core banks - load/store, L2, etc.), some not (Non-core - L3, NBIO, UMC, etc.) The latter usually raised in thread 0 unrelated to the core itself.
> PIE controller is part of Data and Control Fabric, so raised corrected error exception usually mean it's unstable.


This is very interesting, and a bit over my head. I looked in the Event Viewer and MCABank is 27 so the PIE controller? I will admit that I do not know what that is or what it does. I Googled "AMD Ryzen PIE Controller" and got back nothing. Can you enlighten me? Here is a snip of a typical WHEA-19. They are always identical except for the characters in the RawData line. How do I tell if the error is thread related or not? Most importantly, what can I do about it?










Current options I am aware of are:

1 - Leave the RAM at stock 2133MHz. There are no WHEA-19 errors when the RAM is running default settings. I don't like this option.
2 - Live with the WHEA -19 errors. I don't like this option either.
3 - Try raising VSOC. I've had it up to 1.1v but Zen Timings reports 1.081v so there is some droop, so try 1.2v and maybe LLC4. ManniX-ITA suggested VSOC of 1.27v with high LLC.
4 - Try raising VDDG IOD Zen Timings reports VDDG IOD is ~1.047v. Try increasing to 1.1v
5 - Try raising VCore a little or adding a +2 CO offset to Core 1.
6 - Try Hydra 1.2C Pro and hope it makes it through the diagnostic.
7 - Try 1 DIMM at a time or a different set of DIMMs.

Other suggestions are welcomed.

I will the above and see if I hit on the solution. If I can more explicitly identify the exact cause of the WHEA-19 error, it may indicate the exact solution, if there is one. Thanks for your insights.


----------



## xpulse

shnyaps said:


> I had similar problem. 4 dual rank sticks are too hard for ryzen. I have 4x32GB 4000 gskill VDIMM 1.4V, to start them on xmp speed I should increase volatge.
> At the moment they are working at 3800 MHz (1900 MHZ), voltage is 1.57V.
> 
> P.S. When I tried 2 sticks only everything was fine with default VDIMM
> 
> So try 2 sticks, after this you could increase voltage step by step if you want)


Thank you for the suggestion, what is your SOC voltage.?


----------



## ManniX-ITA

SpeedyIV said:


> How do I tell if the error is thread related or not?


You can try reading the AMD Processor Programming Reference (PPR) but it's very technical.
Decoding the data in the WHEA message it's not trivial and at the end doesn't tell much.



SpeedyIV said:


> Try raising VSOC. I've had it up to 1.1v but Zen Timings reports 1.081v so there is some droop, so try 1.2v and maybe LLC4. ManniX-ITA suggested VSOC of 1.27v with high LLC


That was a suggestion for the APU 5700G.
Don't go that high with you VSOC, it's counter productive.
You should try max 1.18V VSOC and 1100mV IOD.
Sometimes is needs also fine-tuning of CCD, try 950-1050mV.


----------



## shnyaps

xpulse said:


> Thank you for the suggestion, what is your SOC voltage.?


My VSOC is 1.125


----------



## Baio73

Valka814 said:


> SoC, Ram voltage, tCL, tRCDWR, tRCDRD, tRP, tRAS set, the rest is auto. TM5 hangs sooner or later.
> View attachment 2569931


When you say "hangs" you mean it keeps running endlessly without really testing the RAM?
If so, I'm duelling with this issue since months... no solution for me ATM. :-(

Baio


----------



## ManniX-ITA

Baio73 said:


> When you say "hangs" you mean it keeps running endlessly without really testing the RAM?
> If so, I'm duelling with this issue since months... no solution for me ATM. :-(


So many reasons it could happen...
First you need to close everything else and not use the PC.
Not even for something light.
TM5 will try to lock all the available RAM but if something else takes it, it will hang.
Without a paging file set it's very likely to die at some point for this reason.
Double check it's activated.

You also need to be sure it's running with Admin privileges; that's easy you get a message otherwise.
Then it may be needed to enable lock memory pages privilege for the user running TM5.
There are many tutorials online:








Windows 10 Home Not Supported · Issue #264 · fireice-uk/xmr-stak-cpu


After getting the common "SeLockMemoryPrivilege failed" error, I follow the "Common Issues" section that leads me to this page: https://docs.microsoft.com/en-us/sql/database-eng...




github.com





Otherwise it's probably one timing or a combination of them which is wrong.
The usual suspect is tRFC/voltage; either raise tRFC or voltage.
Make a run with a very high tRFC to exclude it.


----------



## Frosted racquet

Baio73 said:


> When you say "hangs" you mean it keeps running endlessly without really testing the RAM?
> If so, I'm duelling with this issue since months... no solution for me ATM. :-(
> 
> Baio


Running the test in Safe Mode fixed the issue for me, never hanged once, so I'm guessing it's a software issue in my case.


----------



## Blackfyre

Frosted racquet said:


> Running the test in Safe Mode fixed the issue for me, never hanged once, so I'm guessing it's a software issue in my case.


Or more likely your CPU PBO2 settings are not stable, since in safe mode, CPU runs at stock. 

If RAM stress testing works fine in safe mode, but not under normal use, then it's most likely a CPU stability issue causing other errors.

For testing purposes, restore your CPU overclock to default and test TM5 without safe-mode too.


----------



## Frosted racquet

The timeouts happen with stock CPU settings as well

And as for the PBO2 settings being stable or not, here's a rundown of stability testing for my OC (open the test log spoiler): CoreCycler - tool for testing Curve Optimizer settings

Edit: so, either the default/stock AMD boost algorithm is broken (no PBO2 frequency offset), or TM5 is sensitive to background processes.


----------



## dk_mic

Blackfyre said:


> Or more likely your CPU PBO2 settings are not stable, since in safe mode, CPU runs at stock.
> 
> If RAM stress testing works fine in safe mode, but not under normal use, then it's most likely a CPU stability issue causing other errors.
> 
> For testing purposes, restore your CPU overclock to default and test TM5 without safe-mode too.


why and how would safe mode remove a bios overclock?


----------



## Blackfyre

dk_mic said:


> why and how would safe mode remove a bios overclock?


Majority of people that OC on Zen 3 do not run a locked clocked, but a fluctuating one that utilises single core performance over multi-core performance. My 5800X boosts to 3.8Ghz in safe mode for example, but boosts to 5Ghz on normal boot with my PBO2 settings. Sometimes WHEA errors and issues pop up in stress tests due to CPU instability rather than RAM instability. That's why I am telling them to eliminate that first as an issue but resetting any CPU overclock and booting normally and seeing if TM5 crashes or reports errors like it does for them.


----------



## Frosted racquet

Here's a test with stock CPU and normal mode, hanged/timed out as well. In this case, I was using my PC, Chrome/Twitch were open, but the hang/timeout happens when I test overnight as well.

I have locked the CPU ratio to 37 now, and will test in normal mode, just to rule out that AMDs stock boost algorithm is bugged somehow. But, as I've said, I suspect a software issue.

Edit: thanks for mentioning that Safe Mode removes the PBO2 OC, didn't know that.


----------



## dk_mic

I think the OS disables some kind of boost in safe mode, or the frequency readout is not working correctly. It's not setting your CPU to stock operation at least. I am still getting higher benchmarks scores with PBO2 in safe mode than with stock settings in safge mode. However, base frequency reported is 3400 Mhz. Can't start HWInfo on my installation in safe mode.


----------



## Wil8115

can't seem to get infinity clock stable above 1900/1-1-1. my ram is Sam B die, I checked with thaiphoon/Zen.
I even bought faster ram and an under clocking it. tried setting some Dram calc settings and its very unstable..
I finally got it to run but stability issues trying to get 2k/1-1-1 IF..
my build is a 5950x, x570 aorus elite wifi, 32gb Gskill 2x16


----------



## Frosted racquet

Frosted racquet said:


> Here's a test with stock CPU and normal mode, hanged/timed out as well. In this case, I was using my PC, Chrome/Twitch were open, but the hang/timeout happens when I test overnight as well.
> 
> I have locked the CPU ratio to 37 now, and will test in normal mode, just to rule out that AMDs stock boost algorithm is bugged somehow. But, as I've said, I suspect a software issue.
> 
> Edit: thanks for mentioning that Safe Mode removes the PBO2 OC, didn't know that.
> View attachment 2570025


And here it is with locked 3700MHz base clock PBO2 disabled, in normal mode. So it's definitely software related on my side, running it in Safe Mode never hangs.


----------



## 99belle99

Wil8115 said:


> can't seem to get infinity clock stable above 1900/1-1-1. my ram is Sam B die, I checked with thaiphoon/Zen.
> I even bought faster ram and an under clocking it. tried setting some Dram calc settings and its very unstable..
> I finally got it to run but stability issues trying to get 2k/1-1-1 IF..
> my build is a 5950x, x570 aorus elite wifi, 32gb Gskill 2x16


Not all CPU's can do 2000 IF. I can do 1900MHz IF too but be glad you can reach that some very unlucky people cannot even do 1900MHz.


----------



## Veii

SpeedyIV said:


> I got an immediate warning screen in Chrome. I bypassed the warning and tried to download the file. Chrome blocked it. I was kind of leery about installing this. Is it normal to get this warning and the download blocked? I have had this happen occasionally with downloads from mega.nz.
> 
> Possibly using poor judgment, I downloaded the file using another browser and extracted it. There are a number of .exe. files. I am not sure how to run the test you are asking for. I tried running Tool.exe, then DB Query - > AMD V/F - > Get Sil Quality. Is this what you are after? If yes, the number it came back with was -8.30549. No RAM OC, no PBO/CO. All overclocking-related things in the Bios on Auto.
> 
> I clicked around and tried some of the other functions in this utility. It looks like it can do some pretty interesting things but I would need some documentation to figure out what some of them do.


This is ASUS Tool1007.exe, an XOC tool i early forwarded here taken from HWBot





Tool1007.zip







drive.google.com




The creator of it should be elmor & shamino. I can not speak on elmor's behalve how much he did and from where Shamino and remain ASUS XOC Team have taken on.
The original file was lastly modified on 6th of October, 2020 & it's hash is:


Code:


SHA256: 9421322c6bdb75f959444868ead54d9c3c4d3cb4898815a9ec868c7cf54d3037

You can doublecheck such via terminal or with 7zip's CRC calculation function

I can not vouch for that it indeed is safe whoever reuploaded it wherever
It has been made for X470 and Z490.
This release in specific has no HardwareID checks and works on all boards, but be aware that all VRM functions or general control utilities belong to ASUS's PWM controller.
Within exceptions it works on some ASUS B550 & X570 boards, but i won't vouch for it either

The usable functions for us are the (SMN) Mailbox presets for HSPM (top field) & per core Freq set (it got buggy by being old, and will force 1.55v VID requests)
And the couple options on MP1. It can be useful in case you don't know them, but all of our current tools replaced its functionality
~ PBO2 Tuner by PJVol , replaced CO and Powerlimit access
~ ZenPTMonitor by XPEHOPE3 , replaced AMD Monitor for SMU MUTEX sensorics-tracking access
~ SMUDebug/RyzenSTD by 1rusanovBG/1nfraredBG (creator of Zentimings) , for pushing through SMU commands within their location presets or setting per-core frequencies

And like @domdtxdissar mentioned, Sil-Quality tool is barely of a use. It's target was Matisse where FIT didn't bother
Currently "a bad" score will happen if FIT throttles, which is by thermals or powerlimit ~ independent of substrate quality
Soo Tool107 itself has gotten worthless except for ASUS VRM access.

Doublecheck hash and if you are an ASUS owner, grab the0907 or newer version from it's original HWBot location.
Many people try to reupload stuff, yet always stay slightly pessimistic when you don't know it's original location


----------



## Baio73

ReyReverse said:


> Download from here ,don't worry It's safe.
> Remember, must run the program in default mode, no cpu and ram overclock
> Then tell me your score




Don't know if it may help you...

Baio


----------



## KedarWolf

Did a clean install of Windows 11 22621.457 and got the below first try.

Windows 11 22000.832 struggles with this.

Going to try lower VSOC etc. now.


----------



## Beyond246

shnyaps said:


> I had similar problem. 4 dual rank sticks are too hard for ryzen. I have 4x32GB 4000 gskill VDIMM 1.4V, to start them on xmp speed I should increase volatge.
> At the moment they are working at 3800 MHz (1900 MHZ), voltage is 1.57V.
> 
> P.S. When I tried 2 sticks only everything was fine with default VDIMM
> 
> So try 2 sticks, after this you could increase voltage step by step if you want)


What motherboard were you trying to use with the 4x32 kit?


----------



## The Sandman

After several months of following here I've managed to get this far,
please note this is on an C6H x370 and Dram Voltage is set to 1.46 in BIOS. Software reads incorrect due to voltage read back granularity in Super IO Chip
HWinfo is re-calibrated to match Pro Points on mobo with DMM














Runs very stable without any issues (YCruncher, RamTest, TM5, CoreCycler, P95, OCCT).
I'm now bored and looking for more but I can't get tRCDRD down to 14 regardless of what I know to try.
I'm hoping someone here can point me down the path.

I have tried with ProcODT as low 34.3, 32.0 and 30.0 without much change
Should I change this on current setup shown? I'm fairly clueless in this area along with RTTs.

Also tried RTTs 7/off/5 and Disabled/off/5 and 40/20/20/20 and 40/20/24/24
increased DramV as high as 1.51v but none of these in combination hold up more that 12 minutes or so on TM5.

What am I missing?
Any help is always highly appreciated and very willing to learn!


----------



## Baio73

ManniX-ITA said:


> So many reasons it could happen...
> First you need to close everything else and not use the PC.
> Not even for something light.
> TM5 will try to lock all the available RAM but if something else takes it, it will hang.
> Without a paging file set it's very likely to die at some point for this reason.
> Double check it's activated.
> 
> You also need to be sure it's running with Admin privileges; that's easy you get a message otherwise.
> Then it may be needed to enable lock memory pages privilege for the user running TM5.
> There are many tutorials online:
> 
> 
> 
> 
> 
> 
> 
> 
> Windows 10 Home Not Supported · Issue #264 · fireice-uk/xmr-stak-cpu
> 
> 
> After getting the common "SeLockMemoryPrivilege failed" error, I follow the "Common Issues" section that leads me to this page: https://docs.microsoft.com/en-us/sql/database-eng...
> 
> 
> 
> 
> github.com
> 
> 
> 
> 
> 
> Otherwise it's probably one timing or a combination of them which is wrong.
> The usual suspect is tRFC/voltage; either raise tRFC or voltage.
> Make a run with a very high tRFC to exclude it.


I owe you an answer... TM5 in Windows' Safe Mode completes all 25 cycles, so it's definetely a software related issue.

But my pc is ok, I have no bad/malfunctionig software running, so IMOH it's a problem of TM5 the authore should investigate.
Now I'm gonna do some other test, I suspect Lian Li L-Connect 3 is the culprit...

Baio


----------



## ManniX-ITA

Baio73 said:


> But my pc is ok, I have no bad/malfunctionig software running, so IMOH it's a problem of TM5 the authore should investigate.


Unfortunately I think it's not actively developed anymore.
What makes it so good for testing ram makes it also very susceptible to conflicts with other software, they don't strictly need to malfunction.


----------



## ManniX-ITA

The Sandman said:


> I'm now bored and looking for more but I can't get tRCDRD down to 14 regardless of what I know to try.


If you are bored try to make a 2T profile or a 1T with AddrCmdSetup 55/56 

Try with ClkDrvStr to 60 Ohm to get tRCDRD 14.
This worked for me.

Using GDM On is rounding to even most timings (it's special on AMD); right now your tRCDRD is at 16 instead of 15.
Probably also tRAS/tRC is being autocorrected somewhere else and also other timings.
Test if you see a difference setting them higher; check AIDA but don't trust it blindly, run y-cruncher 2.5b benchmark to know if it really makes a difference.

Give a try to RTT 0/3/6, seems really good for 2xSR, suggested to me by @glnn_23


----------



## The_King

ManniX-ITA said:


> If you are bored try to make a 2T profile or a 1T with AddrCmdSetup 55/56
> 
> Try with ClkDrvStr to 60 Ohm to get tRCDRD 14.
> This worked for me.
> 
> Using GDM On is rounding to even most timings (it's special on AMD); right now your tRCDRD is at 16 instead of 15.
> Probably also tRAS/tRC is being autocorrected somewhere else and also other timings.
> Test if you see a difference setting them higher; check AIDA but don't trust it blindly, run y-cruncher 2.5b benchmark to know if it really makes a difference.
> 
> Give a try to RTT 0/3/6, seems really good for 2xSR, suggested to me by @glnn_23
> 
> View attachment 2570408


One of the first Zentimings I have seen with BGS enabled instead of BGS Alt. Was this needed to boot/post or for stability?

What VDIMM did you use? I can go up to 4066 with my B450 and 5600. 
higher than this wont boot but I have not really pushed VSOC, I know APUs can run much higher VSOC because of the IGPU so 1.3V is probably safe.
I have seen some on here run 1.25V VSOC with ZEN 3 Vermeer but I would not run that 24/7 maybe for just benchmarking.


----------



## ManniX-ITA

The_King said:


> One of the first Zentimings I have seen with BGS enabled instead of BGS Alt. Was this needed to boot/post or for stability?


LoL I had no idea, didn't notice it 
Didn't set it and I don't remember seeing the option on this board.
It's an ASRock... weird BIOS.



The_King said:


> What VDIMM did you use? I can go up to 4066 with my B450 and 5600.


It's a NAS, so must be silent without additional cooling for DIMMs.
VDIMM is set at 1.52V.



The_King said:


> higher than this wont boot but I have not really pushed VSOC, I know APUs can run much higher VSOC because of the IGPU so 1.3V is probably safe.


Yes, from what I heard it's safe up to 1.35V.
But I'm more confident with a bit below, 1.325V.
At 2100 MHz fabric speed 1.3V failed after 4 hours of stressing I/O.

I'm setting up monitoring 












The_King said:


> I have seen some on here run 1.25V VSOC with ZEN 3 Vermeer but I would not run that 24/7 maybe for just benchmarking.


It's indeed a bit high even for the direst overclockers eheh
I kept mine with the 5950X at 1.22V for IF 2000 MHz.
Above that it's starting to kill performances.
From that I've seen the single CCD gets hit with power budget limitations earlier.
So it's probably better to keep it a 1.2V or below.


----------



## ManniX-ITA

The_King said:


> I have seen some on here run 1.25V VSOC with ZEN 3 Vermeer but I would not run that 24/7 maybe for just benchmarking.


I just noticed you have VSOC at 1.1V like VDDG.
Surprising it works.
I'd set it to 1.16V at the very least.
It's for sure autocorrected and it's never a good thing.
Usually the result is random crashes and reboots out of the blue.


----------



## The_King

ManniX-ITA said:


> I just noticed you have VSOC at 1.1V like VDDG.
> Surprising it works.
> I'd set it to 1.16V at the very least.
> It's for sure autocorrected and it's never a good thing.
> Usually the result is random crashes and reboots out of the blue.


VDDG was on Auto just an old screenshot. I have 4 sticks in at the moment and can only boot 3800. 
I usually set VDDG to something like this even lower, even with 4 stick VSOC is the same and its stable @ 3800


----------



## MyUsername

KedarWolf said:


> Did a clean install of Windows 11 22621.457 and got the below first try.
> 
> Windows 11 22000.832 struggles with this.
> 
> Going to try lower VSOC etc. now.
> 
> View attachment 2570216


My cpu out right says no to 1900/3800, in fact both my 5950 say no I get whea on my second, but I'm TM5 stable at these timings









By the way, I have used 1.0GO but AMD raid is severely broken. In Windows setup I get black screen when loading drivers or switching to this modded bios after Windows install on factory bios corrupts the raid and I get the same performance out of bios 1.0.


----------



## Veii

The_King said:


> I have seen some on here run 1.25V VSOC with ZEN 3 Vermeer but I would not run that 24/7 maybe for just benchmarking.


Hello i'm someone @ 1.288vSOC
Someone runs this for 2 years now without sign of degradation ~ on air
Only degradation for me was when pushing 1.76vCore for single core XOC attempts
Soo some cores need now a slightly higher negative CO ~ but bearable with AMDs +200MHz only, limit

EDIT:
First batch even, not bettered up substrate B2


----------



## ManniX-ITA

Veii said:


> Hello i'm someone @ 1.288vSOC


More than degradation I was worried about the performances hit.
Doesn't suck too much out of the power budget at that voltage?
With my old 5950X above 1.225V was slowly eating y-cruncher and cpuminer scores.
At 1.25V it was a massive hit.
How it goes with the 5600X?



The_King said:


> VDDG was on Auto just an old screenshot. I have 4 sticks in at the moment and can only boot 3800.
> I usually set VDDG to something like this even lower, even with 4 stick VSOC is the same and its stable @ 3800


Oh right, I should have thought about it  
I use Geekbench5 scores + CB23 et al to calibrate VDDG CCD and IOD.
Very often too high, even by a 10mV, it's a noticeable performance hit.


----------



## SpeedyIV

SpeedyIV said:


> I am trying to figure out why I keep getting WHEA 19 corrected hardware errors. They are always for Processor APID ID:0. They occur every time I try to overclock my RAM.
> 
> System: Asus Dark Hero, 5950X, 2 x G.Skill F4-3200C14D-32GTZR 16GB CL14-14-34 B-Die, Asus TUF 3080 GPU
> BIOS 4201, AGESA ComboV2PI 1207, Win10 Pro 21H2 19044.0889
> Bios (other than RAM settings) is at defaults - no PBO, no CO, PPT, TDC, EDC all on Auto.
> 
> I verified B-Die with Thaiphoon Burner and have used the Ryzen DRAM calculator as a starting point. I was able to do 3600MHz @14-14-14-28 2T (GDM disabled) and run Kahru, TestMem, and MemTest Pro for hours with no errors, but I get these WHEA 19 errors popping up. Some days none, some days a few, and some days every ~30-min.
> 
> I slowed things down to 3200MHz, tried just XMP with everything else on Auto, raised VDIMM in steps up to 1.45V, raised VSOC in steps up to 1.1V, tried GDM on, loosened 2nd's and 3rd's. The only time the WHEA-19 errors stop for good is when I set the RAM back to stock 2133MHz @15-15-15-36. What I haven't done is adjust ProcODT, Rtt's, ClkDrvStr, AddrCmdDrvStr, CsOdrtDrvStr, or CkeDrvStr. I am still learning about these settings. I have been entering the settings in Extreme Tweaker but know that they also appear under the AMD Overclocking section. I have read many conflicting posts about which area of the Bios to use. I have not tried doing it in the AMD section.
> 
> I was beginning to think that the WHEA-19 errors were not caused by RAM overclock - maybe a problem with the CPU, or a driver or OS bug. Since the WHEA's stop when I take the RAM back to defaults, I am back to thinking it's my overclock.
> 
> Here are Zen Timings screenshots for 3600, 3200, and DOCP from left to right. What am I doing wrong? Any advice is appreciated.
> View attachment 2569635
> View attachment 2569636
> View attachment 2569637


Quoting my own post for context. For those who made suggestions to help me track down these annoying WHEA-19 errors, I raised VSOC to 1.150V with LLC 4 and have not had a single WHEA error since. I had this RAM at 3600CL14 but went back to 3200 because I kept getting WHEA-19 errors. Since increasing VSOC to 1.150V and setting VSOC LLC to 4, Zen Timings now reports VSOC at 1.150V, so the droop I had is gone, and so are the WHEAs. I am going to try going back to 3600. Thanks for the suggestions!


----------



## SpeedyIV

Veii said:


> This is ASUS Tool1007.exe, an XOC tool i early forwarded here taken from HWBot
> 
> 
> 
> 
> 
> Tool1007.zip
> 
> 
> 
> 
> 
> 
> 
> drive.google.com
> 
> 
> 
> 
> The creator of it should be elmor & shamino. I can not speak on elmor's behalve how much he did and from where Shamino and remain ASUS XOC Team have taken on.
> The original file was lastly modified on 6th of October, 2020 & it's hash is:
> 
> 
> Code:
> 
> 
> SHA256: 9421322c6bdb75f959444868ead54d9c3c4d3cb4898815a9ec868c7cf54d3037
> 
> You can doublecheck such via terminal or with 7zip's CRC calculation function
> 
> I can not vouch for that it indeed is safe whoever reuploaded it wherever
> It has been made for X470 and Z490.
> This release in specific has no HardwareID checks and works on all boards, but be aware that all VRM functions or general control utilities belong to ASUS's PWM controller.
> Within exceptions it works on some ASUS B550 & X570 boards, but i won't vouch for it either
> 
> The usable functions for us are the (SMN) Mailbox presets for HSPM (top field) & per core Freq set (it got buggy by being old, and will force 1.55v VID requests)
> And the couple options on MP1. It can be useful in case you don't know them, but all of our current tools replaced its functionality
> ~ PBO2 Tuner by PJVol , replaced CO and Powerlimit access
> ~ ZenPTMonitor by XPEHOPE3 , replaced AMD Monitor for SMU MUTEX sensorics-tracking access
> ~ SMUDebug/RyzenSTD by 1rusanovBG/1nfraredBG (creator of Zentimings) , for pushing through SMU commands within their location presets or setting per-core frequencies
> 
> And like @domdtxdissar mentioned, Sil-Quality tool is barely of a use. It's target was Matisse where FIT didn't bother
> Currently "a bad" score will happen if FIT throttles, which is by thermals or powerlimit ~ independent of substrate quality
> Soo Tool107 itself has gotten worthless except for ASUS VRM access.
> 
> Doublecheck hash and if you are an ASUS owner, grab the0907 or newer version from it's original HWBot location.
> Many people try to reupload stuff, yet always stay slightly pessimistic when you don't know it's original location


Thank you! As I mentioned above, increasing VSOC to 1.150V and VSOC LLC to 4 seems to have stopped my WHEA-19 errors. I will check out this tool for sure.


----------



## The_King

Veii said:


> Hello i'm someone @ 1.288vSOC
> Someone runs this for 2 years now without sign of degradation ~ on air
> Only degradation for me was when pushing 1.76vCore for single core XOC attempts
> Soo some cores need now a slightly higher negative CO ~ but bearable with AMDs +200MHz only, limit
> 
> EDIT:
> First batch even, not bettered up substrate B2


Are you running this high VSOC on your dual CCD 5600X? Is that not a factor to take into consideration even though 1 CCD is disable?
Some people do get errors above 1.2V VSOC so I dont see the benefit of going to 1.288V for everyone or most users.

My 5600X REV B2 is also dual CCD I dont get errors above 1.2V but the highest I went was 1.225V.

Are your running 1.288V daily? I would like to see what setup would require such a high VSOC if you dont mind. Thanks
Is it this one?


http://imgur.com/HJRXkop


----------



## Audioboxer

__ https://twitter.com/i/web/status/1565585672689242112
I'm guessing this is without proper PBO tuning (and it's air cooling). These bad boys seem to run hot as well AMD Ryzen 7000 CPUs Reportedly Run Hot, Ryzen 9 7950X Hits Up To 95C Thermal Threshold at 230W, Ryzen 5 7600X Up To 90C at 120W So I wouldn't be surprised if air cooling just won't cut it for pushing CB23 numbers.

Bigger question I want answered that no one seems to be discussing/leaking about yet is what is the memory controller like. The 3D cache variants are rumoured to be announced early next year, so there's no way I'm changing over to AM5 at launch anyway.


----------



## domdtxdissar

Audioboxer said:


> View attachment 2570788
> 
> 
> 
> __ https://twitter.com/i/web/status/1565585672689242112
> I'm guessing this is without proper PBO tuning (and it's air cooling). These bad boys seem to run hot as well AMD Ryzen 7000 CPUs Reportedly Run Hot, Ryzen 9 7950X Hits Up To 95C Thermal Threshold at 230W, Ryzen 5 7600X Up To 90C at 120W So I wouldn't be surprised if air cooling just won't cut it for pushing CB23 numbers.
> 
> Bigger question I want answered that no one seems to be discussing/leaking about yet is what is the memory controller like. The 3D cache variants are rumoured to be announced early next year, so there's no way I'm changing over to AM5 at launch anyway.


Take a look in the Zen4 thread

Long story short:


----------



## Luggage

Audioboxer said:


> View attachment 2570788
> 
> 
> 
> __ https://twitter.com/i/web/status/1565585672689242112
> I'm guessing this is without proper PBO tuning (and it's air cooling). These bad boys seem to run hot as well AMD Ryzen 7000 CPUs Reportedly Run Hot, Ryzen 9 7950X Hits Up To 95C Thermal Threshold at 230W, Ryzen 5 7600X Up To 90C at 120W So I wouldn't be surprised if air cooling just won't cut it for pushing CB23 numbers.
> 
> Bigger question I want answered that no one seems to be discussing/leaking about yet is what is the memory controller like. The 3D cache variants are rumoured to be announced early next year, so there's no way I'm changing over to AM5 at launch anyway.




__ https://twitter.com/i/web/status/1565640634886549504


----------



## Audioboxer

Luggage said:


> __ https://twitter.com/i/web/status/1565640634886549504


Thought as much, on paper it should be smoking the 5950x.


----------



## Baio73

So... after understanding that TM5 got stuck due to a software issue, I finally get to make 25 runs with 1usumus profile without errors.

This is what I reached with 1.52v (ca't go higher due to temperature related errors popping):



Any advice to improve?
Thanks!

Baio


----------



## The_King

Baio73 said:


> So... after understanding that TM5 got stuck due to a software issue, I finally get to make 25 runs with 1usumus profile without errors.
> 
> This is what I reached with 1.52v (ca't go higher due to temperature related errors popping):
> 
> 
> 
> Any advice to improve?
> Thanks!
> 
> Baio


Not sure if this was the same RAM you have been running before. It looks like its rated 3600 CL14 so definitely a Samsung B-die Kit can do low RFC too.
Most of your timmings are off RP tRAS RC TWR RTP RDWR WRRD

I would suggest 14-15-15-15-30-45.TWR12 RTP 6 and change CWL to 14. leave RDWR and WRRD on Auto
or something like this 14-16-16-16-32-48 TWR12 RTP 6 and change CWL to 14

If you have to run RDWR 18 and WRRD 7 in order to get GDM disabled 1 T stable I would say its not worth it. Rather go with GDM enable 1 T with lower RDWR and WRRD values.

This is 8GBX4 your timmings should be something like this


----------



## heptilion

The_King said:


> When I was looking for a sinewave UPS years ago I saw reviews of the APC 1000/1500VA and the CyberPower 1000/1500VA. The CP one was rated / reviewd has being the better option.
> 
> Sadly was not availble in my country so bought the APC which was very good. One thing that was awseome it shows realtime load in Watts. Backup on Desktop when new was 30mins, AVG 20mins after a few years.
> 
> Now I run this setup with over +10 hours of backup, it is a "Pure sinewave" inverter. (according to website specs) (87 USD)
> 
> 
> 
> 
> 
> 
> 
> 
> Luminous Zolt 1100 Sine Wave Inverter for Home, Office & Shops (Blue) : Amazon.in: Home & Kitchen
> 
> 
> Luminous Zolt 1100 Sine Wave Inverter for Home, Office & Shops (Blue) : Amazon.in: Home & Kitchen
> 
> 
> 
> www.amazon.in
> 
> 
> 
> 
> 
> Its attached to a 200AH battery (215 USD)
> 
> 
> Amazon.in
> 
> 
> 
> Full load gaming I get betwen 6-8 hours when the power is out depending on the game load. My CPU and GPU is UV and UC as well for max efficiency..
> 
> At the present moment the power is out it showing 9:59 which means more than +10 hours of backup left. Only problem it does not show realtime power consumption but its the best UPS system with built in voltage stabilizer and rated 94% for efficiency..
> View attachment 2565740


I am also looking for a UPS.

Will something like this be overkill? It has only 363 surge suppression though.

Will be plugging in cpu(1000w psu), 2 240hz monitors, 1 modem, 1 router, speakers.






OLS2000ERT2UA - Smart App UPS Systems | CyberPower


CyberPower OLS2000ERT2UA is a high-performance UPS featuring online double-conversion topology, which provides seamless Pure Sine Wave power for mission-critical devices such as NAS and servers, DVRs/surveillance systems, transportation and infrastructure, and emergency systems. It’s typically...




www.cyberpower.com


----------



## ItsCash

Any thoughts on the Agesa 1.2.0.7 AMI BIOS 7C35vAE 2022-08-18 Msi has seem to have done it again, anyone stable at 4000/cl16 with IF 2000? or should I stay with 1.2.0.3c? and be happy with 3800/cl14 IF 1900 1.5v?


----------



## The_King

heptilion said:


> I am also looking for a UPS.
> 
> Will something like this be overkill? It has only 363 surge suppression though.
> 
> Will be plugging in cpu(1000w psu), 2 240hz monitors, 1 modem, 1 router, speakers.
> 
> 
> 
> 
> 
> 
> OLS2000ERT2UA - Smart App UPS Systems | CyberPower
> 
> 
> CyberPower OLS2000ERT2UA is a high-performance UPS featuring online double-conversion topology, which provides seamless Pure Sine Wave power for mission-critical devices such as NAS and servers, DVRs/surveillance systems, transportation and infrastructure, and emergency systems. It’s typically...
> 
> 
> 
> 
> www.cyberpower.com


What CPU and GPU are you going to run? How many fans, HDDs, watercoling?

From the specs it is a 4 battery system (12VX4) 48V that may be a concern when it time to replacement those batteries.



ItsCash said:


> Any thoughts on the Agesa 1.2.0.7 AMI BIOS 7C35vAE 2022-08-18 Msi has seem to have done it again, anyone stable at 4000/cl16 with IF 2000? or should I stay with 1.2.0.3c? and be happy with 3800/cl14 IF 1900 1.5v?


I am on 1.2.0.7 no issue compared to 1.2.0.3C got 4066 CL15 stable.


----------



## heptilion

The_King said:


> What CPU and GPU are you going to run? How many fans, HDDs, watercoling?
> 
> From the specs it is a 4 battery system (12VX4) 48V that may be a concern when it time to replacement those batteries.


I am on a 3090, 5950x, 360aio, HAF700evo case. 2×200mm+ 5×120mm. 2HDD, 2nvme.

Will be going for a 4090 when that's out.

What did you mean by it will be difficult to replace the battery?


----------



## The_King

heptilion said:


> I am on a 3090, 5950x, 360aio, HAF700evo case. 2×200mm+ 5×120mm. 2HDD, 2nvme.
> 
> Will be going for a 4090 when that's out.
> 
> What did you mean by it will be difficult to replace the battery?


I did not mean difficult I meant in terms of cost. If those batteries are cheap to replace and the UPS is within your budget I say go for it even
if it is overkill now.

There was news about high transient spikes over 1600W with new GPUs so I think 1800W UPS may not be a bad idea.









NVIDIA GeForce RTX 4090 Ti Specs Allegedly Revealed And It's An 800W Beast GPU


Are you ready for the next generation of GPU performance? Is your main line's power breaker ready?




hothardware.com






> with the possibility for transient spikes over 1.6 kW, it's possible that this GPU alone could trip a circuit breaker in most American homes.


----------



## ManniX-ITA

heptilion said:


> I am on a 3090, 5950x, 360aio, HAF700evo case. 2×200mm+ 5×120mm. 2HDD, 2nvme.
> 
> Will be going for a 4090 when that's out.


I'd only buy it if you have the option to send it back if it doesn't work.

I had a country house where I was going for the weekends some years ago.
The power delivery was terrible so I had many APC UPS (Pro Smart Online managed via Ethernet, good stuff more or less).

I can tell you that with less power consumption from you current configuration a 1600VA couldn't hold when switching to battery.
I had to buy a 2200VA. Otherwise it would shut off immediately if I was gaming something.

Despite the yadda yadda specs, take the (max power consumption while gaming * 1.2) * 2 = that's the UPS max wattage you need.
Probably with the 4090 it's going to be much worse.


----------



## Bloax

ManniX-ITA said:


> Probably with the 4090 it's going to be much worse.


Only if you accept the ****ty factory overclock running the chip at a silly voltage/frequency curve, rather than finding the extremely good spots somewhere in the -10% performance region.

It's open factory OC season for Nshitia, ****tel and Ayy(nother) M(assive) D(isappointment) this year.


----------



## Baio73

The_King said:


> Not sure if this was the same RAM you have been running before. It looks like its rated 3600 CL14 so definitely a Samsung B-die Kit can do low RFC too.
> Most of your timmings are off RP tRAS RC TWR RTP RDWR WRRD


Thanks for your replay.
RAM is the same, definetely B-Die.
What do you mean with "most of your timings are off" ?
Do you think I can run a lower tRFC?



> I would suggest 14-15-15-15-30-45.TWR12 RTP 6 and change CWL to 14. leave RDWR and WRRD on Auto


Tried but had a plenty of errors:



tRDWR and tWRRD are already on Auto



> or something like this 14-16-16-16-32-48 TWR12 RTP 6 and change CWL to 14


Next try!



> If you have to run RDWR 18 and WRRD 7 in order to get GDM disabled 1 T stable I would say its not worth it. Rather go with GDM enable 1 T with lower RDWR and WRRD values.


Not tried yet, those 2 values pop up leaving the setting to Auto, gonna try to lower them to check?



> This is 8GBX4 your timmings should be something like this
> View attachment 2570892


I'm gonna try this also...

Baio


----------



## The_King

Baio73 said:


> Thanks for your replay.
> RAM is the same, definetely B-Die.
> What do you mean with "most of your timings are off" ?
> Do you think I can run a lower tRFC?
> Baio


Copy/pasted settings for B-die is a hit or miss sometimes. My ProODT and WRRD and other settings are for 4 X SR sticks according to my board.

You are running 2 X DR sticks which may not like my setup..
So you would have to see what settings work on your board and make some adjustments.
I also have addcmdrsetup 56 which helps with me with stability on my setup.

@Bloax @Taraquin can probably help you out if they are free.

Try to post Zentimings along with the any TM5 errors that can be helpful.


----------



## Taraquin

Baio73 said:


> So... after understanding that TM5 got stuck due to a software issue, I finally get to make 25 runs with 1usumus profile without errors.
> 
> This is what I reached with 1.52v (ca't go higher due to temperature related errors popping):
> 
> 
> 
> Any advice to improve?
> Thanks!
> 
> Baio


Suggestions:
Turn off gear down mode, set 2t. 1.5v vdimm.

Try
15 15 15
RAS 30
RC 45
WR 14
CWL 14
RTP 7
RDWR auto
WRRD auto

CL 14 usually needs 1.55v+ unless bin is good.


----------



## Baio73

Taraquin said:


> Suggestions:
> Turn off gear down mode, set 2t. 1.5v vdimm.
> 
> Try
> 15 15 15
> RAS 30
> RC 45
> WR 14
> CWL 14
> RTP 7
> RDWR auto
> WRRD auto
> 
> CL 14 usually needs 1.55v+ unless bin is good.


Thanks for your suggestions, but my goal is to keep CAS14 1T with GDM OFF.
RAM for sure is a good bin, as I'm stable this way (v1.52):



Just asking if there is some timing to adjust... I know that probably CAS14 2T would score a better performance in bechmarks, but I suppose the difference is so close it really does not interest me.

Baio


----------



## Baio73

The_King said:


> Copy/pasted settings for B-die is a hit or miss sometimes. My ProODT and WRRD and other settings are for 4 X SR sticks according to my board.
> 
> You are running 2 X DR sticks which may not like my setup..
> So you would have to see what settings work on your board and make some adjustments.
> I also have addcmdrsetup 56 which helps with me with stability on my setup.
> 
> @Bloax @Taraquin can probably help you out if they are free.
> 
> Try to post Zentimings along with the any TM5 errors that can be helpful.


Understood.
Posting ZenTimings along with TM5 errors needs some copy/paste work, ZT does not open in Windows Safe Mode.

Baio


----------



## ManniX-ITA

Baio73 said:


> Just asking if there is some timing to adjust... I know that probably CAS14 2T would score a better performance in bechmarks, but I suppose the difference is so close it really does not interest me.


Post an AIDA64 benchmark screenshot. Best would be also a Sandra Processor Multi Core Efficiency result.
I doubt the performances are even close to a good 2T profile.
The tRC so high and the tRDWR/tWRRD are probably choking it a lot, that's why you can run 1T with GDM Off.


----------



## Taraquin

Baio73 said:


> Thanks for your suggestions, but my goal is to keep CAS14 1T with GDM OFF.
> RAM for sure is a good bin, as I'm stable this way (v1.52):
> 
> 
> 
> Just asking if there is some timing to adjust... I know that probably CAS14 2T would score a better performance in bechmarks, but I suppose the difference is so close it really does not interest me.
> 
> Baio


RCDRD generally has more impact on performance than CL, running 15-15 may be easier than 14-16. Just a suggestion


----------



## byDenoso

My new stable settings


----------



## Hun61ter

Hello dear overclockers.
I recently purchased a Ryzen 5600 and decided to overclock the RAM. I got samsung b-die chips.
I tried to accurately and correctly disperse it according to the formulas. Here's what happened to me:


Spoiler: screen














Please tell me if I did everything right?
Perhaps some timings should be raised or lowered according to the formulas?
I will be very grateful for your answers.


----------



## Taraquin

Hun61ter said:


> Hello dear overclockers.
> I recently purchased a Ryzen 5600 and decided to overclock the RAM. I got samsung b-die chips.
> I tried to accurately and correctly disperse it according to the formulas. Here's what happened to me:
> 
> 
> Spoiler: screen
> 
> 
> 
> 
> View attachment 2571384
> 
> 
> 
> Please tell me if I did everything right?
> Perhaps some timings should be raised or lowered according to the formulas?
> I will be very grateful for your answers.


Looks very good. RRDL may do 4, SCL's may perform better at 2 or 4, but 3 may be best. Are you sure you need setup times? Single rank sticks often don't need that. Are you running allcore oc of 4.6 or +150 pbo?


----------



## Baio73

Hun61ter said:


> Hello dear overclockers.
> I recently purchased a Ryzen 5600 and decided to overclock the RAM. I got samsung b-die chips.
> I tried to accurately and correctly disperse it according to the formulas. Here's what happened to me:
> 
> 
> Spoiler: screen
> 
> 
> 
> 
> View attachment 2571384
> 
> 
> 
> Please tell me if I did everything right?
> Perhaps some timings should be raised or lowered according to the formulas?
> I will be very grateful for your answers.


Looks really great to me... what voltage are you keeping?

Baio


----------



## ReyReverse

Audioboxer said:


> View attachment 2570788
> 
> 
> 
> __ https://twitter.com/i/web/status/1565585672689242112
> I'm guessing this is without proper PBO tuning (and it's air cooling). These bad boys seem to run hot as well AMD Ryzen 7000 CPUs Reportedly Run Hot, Ryzen 9 7950X Hits Up To 95C Thermal Threshold at 230W, Ryzen 5 7600X Up To 90C at 120W So I wouldn't be surprised if air cooling just won't cut it for pushing CB23 numbers.
> 
> Bigger question I want answered that no one seems to be discussing/leaking about yet is what is the memory controller like. The 3D cache variants are rumoured to be announced early next year, so there's no way I'm changing over to AM5 at launch anyway.


 Im waiting 7950x too. need a group name Ryzen DDR5 24/7 soon.


----------



## ManniX-ITA

Hun61ter said:


> Please tell me if I did everything right?
> Perhaps some timings should be raised or lowered according to the formulas?
> I will be very grateful for your answers.


Would also check SCL 5, higher doesn't mean necessarily slower.

As suggested by @Taraquin would check if feasible without Setup times and anyway use 0 on CsOdt, Cke.

If you have trouble with pure 1T try ClkDrvStr at 60 ohm and in case check RTT 0/3/6.


----------



## umea

Baio73 said:


> Thanks for your suggestions, but my goal is to keep CAS14 1T with GDM OFF.
> RAM for sure is a good bin, as I'm stable this way (v1.52):
> 
> 
> 
> Just asking if there is some timing to adjust... I know that probably CAS14 2T would score a better performance in bechmarks, but I suppose the difference is so close it really does not interest me.
> 
> Baio


your insistence to keep 1T GDM off with CL14 3800 is literally holding back your performance by a lot lol. what's the point in asking for advice and then not following it?

the reason people are suggesting to run 2T is because 2T makes it far easier to stabilize and figure out what's actually wrong with your overclock versus wondering if it has to do with 1T gdm off.. in fact, dropping to 2T and running 15-15-15-30-45 would yield much better performance than what you're running right now.. what is your reasoning for insisting on 1T gdm off when you haven't even finished stabilizing an actual good overclock?

you are heavily misunderstanding what impacts performance. running tCL14 and 1T gdm off with WR/RD 16 tRP 19 tRAS36 and tRC56 + your other loose timings versus running 2T 15-15-15-30-45 with tighter subtimings is worse.

"I know that probably CAS14 2T would score a better performance in bechmarks, but I suppose the difference is so close it really does not interest me" no, what they're saying is that a good 2T profile (not yours if you were to just drop to 2T) would yield better performance, both latency and throughput wise. in the first place the fact you think interpreted that as 2T is somehow better just shows that you need to do more reading

here's an example of an actual 2T profile which is what people are talking about


Spoiler: my profile















please try to be actually receptive to advice if you are asking for it


----------



## domdtxdissar

And now we wait 24 hours 😇


























Getting hardware ready for my AM5 7950x build..
Barts custom copper ddr5 heatsinks are going on those


----------



## byDenoso

For 2x8SR, what's the best RTTs, ProcODT and Cad Bus? and how to test it?
I have a A2 Hynix DJR


----------



## domdtxdissar

domdtxdissar said:


> And now we wait 24 hours 😇
> View attachment 2571454
> View attachment 2571455
> View attachment 2571456
> 
> View attachment 2571457
> 
> Getting hardware ready for my AM5 7950x build..
> Barts custom copper ddr5 heatsinks are going on those


lol, went to check on memory sticks after only as few hours to see if there was any progress and the heatsinks came right off 








IC information included for those that are interested in that


----------



## Baio73

umea said:


> your insistence to keep 1T GDM off with CL14 3800 is literally holding back your performance by a lot lol. what's the point in asking for advice and then not following it?


I perfectly understand your ponit of view, but I don't see anything bad in trying to make the best OC with some settings, then try other settings and finally compare the results.
You say 2T it's better. I trust you, but why can't I try?
OC should be fan of trying and experiment, I don't see anything bad in this...



> the reason people are suggesting to run 2T is because 2T makes it far easier to stabilize and figure out what's actually wrong with your overclock versus wondering if it has to do with 1T gdm off.. in fact, dropping to 2T and running 15-15-15-30-45 would yield much better performance than what you're running right now.. what is your reasoning for insisting on 1T gdm off when you haven't even finished stabilizing an actual good overclock?


My PC si perfectly stable, passed 25 cycles of TM5, I was just asking it there was something to improve with CAS14 GDM OFF.
If I can't go lower in any valuse, I'll pass to test 2T GDM OFF.



> you are heavily misunderstanding what impacts performance. running tCL14 and 1T gdm off with WR/RD 16 tRP 19 tRAS36 and tRC56 + your other loose timings versus running 2T 15-15-15-30-45 with tighter subtimings is worse.
> 
> "I know that probably CAS14 2T would score a better performance in bechmarks, but I suppose the difference is so close it really does not interest me" no, what they're saying is that a good 2T profile (not yours if you were to just drop to 2T) would yield better performance, both latency and throughput wise. in the first place the fact you think interpreted that as 2T is somehow better just shows that you need to do more reading


As I said, I trust you and anyone else in this forum, but why can't I try and compare at the end?
If I had enough time (and competence), "to do more reading" I wouldn't be here asking for some advice...



> here's an example of an actual 2T profile which is what people are talking about
> 
> 
> Spoiler: my profile
> 
> 
> 
> 
> View attachment 2571440


Thanks, I will try your settings ASAP.



> please try to be actually receptive to advice if you are asking for it


Even if the answer was to a different question?

Baio


----------



## KingEngineRevUp

Anyone here correlate temperature to memory errors or crashing? 

For B-Die, I have noticed a common pattern of 52-55C being a no go zone with memory crashing and causing errors. With a memory fan, keeping my memory at 40-45C, I see no issues or errors even with overnight stress testing. But remove that fan and it'll throw an error in 45-60 minutes.


----------



## Frosted racquet

For me, going from 55°C to ~60°C resulted in having to increase tRC from 36 to 42.


----------



## umeng2002

I'm finding the same thing with my 4 x 8 GB B-die sticks. I put a fan on it, and I'm stable.

Notably, HCI memtest is exposing the errors where Karhu or TestMem5 miss.

At 1.45v, my sticks won't do tRC 44 with long term stability even with a fan. But with a fan, I might push the voltage...


----------



## domdtxdissar

domdtxdissar said:


> And now we wait 24 hours 😇
> View attachment 2571454
> View attachment 2571455
> View attachment 2571456
> 
> View attachment 2571457
> 
> Getting hardware ready for my AM5 7950x build..
> Barts custom copper ddr5 heatsinks are going on those


Part 2 competed 









Have gathered all the pictures from the install here:


http://imgur.com/a/Qjh3cgV


----------



## domdtxdissar

Above will pretty much be a copy for how my DDR4 sticks ended up looking in the end :


























And as a last goodbye to the AM4 socket, this is a rehash of the timings ive been running on this plattform:

*5950x asynced 1900FCLK:4800MT/s CL17 (Single rank)*










*5950x asynced 1900FCLK:4466MT/s CL15*










*5950x synced 2000FCLK:4000MT/s CL15 *










*5950x synced 1900FCLK:3800MT/s CL13 (my daily 24/7 settings)*


















*5800x3d synced 2100FCLK:4200MT/s CL14*


----------



## The_King

KingEngineRevUp said:


> Anyone here correlate temperature to memory errors or crashing?
> 
> For B-Die, I have noticed a common pattern of 52-55C being a no go zone with memory crashing and causing errors. With a memory fan, keeping my memory at 40-45C, I see no issues or errors even with overnight stress testing. But remove that fan and it'll throw an error in 45-60 minutes.


My sticks seem to be fine going above 55. This is with 0 Airflow with no case.


----------



## 97pedro

What's your guy's opinion on the Asus Rog Strix B550 F gaming motherboard for 4 dimms b die at 3800mhz? Is it a solid board?


----------



## Hiv359

Hello everyone, is there any way to achieve tphyrdl 26\26 a2\b2 on my e die micron sticks with 1T? Will appreciate some help and tips! VDIMM 1.375v.


----------



## Blackfyre

Hiv359 said:


> Hello everyone, is there any way to achieve tphyrdl 26\26 a2\b2 on my e die micron sticks with 1T? Will appreciate some help and tips! VDIMM 1.375v.
> View attachment 2571798


Depends, but in my case, same exact RAM as yours, however instead of 2 sticks, I have (4 x 8Gb = 32Gb total). I could never achieve it. *26 a1 / 26 a2 / 28 b1 / 28 b2* is what I always get.

Anyway, you can tighten a bit more if you push voltage to around 1.510v, here are my best results in the *orange column (note all the changes at the bottom in blue too)*:


----------



## 97pedro

Anyone has a brief explanation of what tphyrdl does and should it be considered for optimal performance?


----------



## Blackfyre

97pedro said:


> Anyone has a brief explanation of what tphyrdl does and should it be considered for optimal performance?


26 26 vs 28 28 is usually around *1ms difference* in AIDA Latency test, and 26 28 combo is usually *0.5ms difference* compared to 26 26.

Not a big deal, you will achieve much better results focusing on tightening all the secondary timings to the best possible values.


----------



## 97pedro

Blackfyre said:


> 26 26 vs 28 28 is usually around *1ms difference* in AIDA Latency test, and 26 28 combo is usually *0.5ms difference* compared to 26 26.
> 
> Not a big deal, you will achieve much better results focusing on tightening all the secondary timings to the best possible values.


But is there a way to try and force lower values?
My zentimings shows tphyrdl at 26, how do I check is it is 26 26 or 26 28?


----------



## 97pedro

Alright it was a matter of selecting different slots on the bottom of zentimings lol.

I'm running 26 26. Is there a way to run 24?


----------



## Blackfyre

97pedro said:


> But is there a way to try and force lower values?
> My zentimings shows tphyrdl at 26, how do I check is it is 26 26 or 26 28?


At the bottom of your ZenTimings, you see where it says your RAM Model Name? That is a drop-down menu. Click and select different ones to check the timings for each stick.

With B-Die you should be able to easily do 26 26



97pedro said:


> I'm running 26 26. Is there a way to run 24?


I don't think so. But I am unsure, wait for someone else more knowledgeable to reply, like @Taraquin 

I believe 26 is the optimal value.


----------



## 97pedro

It would be nice to see an improvement somewhere..


----------



## Taraquin

Blackfyre said:


> At the bottom of your ZenTimings, you see where it says your RAM Model Name? That is a drop-down menu. Click and select different ones to check the timings for each stick.
> 
> With B-Die you should be able to easily do 26 26
> 
> 
> 
> I don't think so. But I am unsure, wait for someone else more knowledgeable to reply, like @Taraquin
> 
> I believe 26 is the optimal value.


Not sure how to get below 26. Maybe Veii knows?Most important is to avoid different values like 26 28 or higher like 28 28. This seems to vary with MBs, using true 1t it seems cl14 is more prone to get the 26 28 mess.


----------



## StrongForce

Hey guys.. I'm back, it's been a while ! 

I have recently upgraded to a 5600x with a B550 Tuf gaming plus mobo, never really got arround getting my 4266 Mhz Ripjaws RGB kit to run at good speeds stable, let alone the max speed.. so after looking more into it, now with this new CPU I feel like it's time I give memory overclocking a fair shot.. I was somewhat stable at 3733 C14 so I have a good kit, ran into hardware issues and possibly windows corrupted, so now I'm gonna be much more careful.. actually doing the testing on another windows install.. 

I'm quite new at RAM overclocking.. currently I'm running 3600 with some weird timings 16-15-16-37 and tRC 85 (that was auto I think it's a bit high) and I meant to put 15 as CL, the first.. anyways will do more tweaking but I just wanted to know, which are the best softwares to test stability "fast" this setting seem decent for now ran 10+ hours prime 95 big fft (memory testing) aswell as the techpowerup memtest64 at the same time, same thing 9 or 10 hours no issues

Also my 3d mark timespy score is really good with these settings, a bit better than with default ram speed which I guess it's not hard to do..but I was nearly at 10700 with stock 2080 trio.

Oh yea and I have Aida64, been running that full test 1h10 without issues. is Aida good to detect errors fast ? man RAM OC is such a time consuming thing to do.. 

and one last thing here is my memory cache performance from Aida with these settings : 










The latency seems high though.. I haven't really took the time to compare with other similar settings.

Any tip to try to find decent timing and subtimings without too much trial and error ? is the DRAM calculator any good ? some people recommend it some people say it's trash.. same for the stability software testing some say this or that software isn't good.. it's confusing

In the short term I guess I just want to keep these settings until I can test more aggressive timings, might try 3600 c14 since I was running 3733 c14 without much issues (and really good performances..) 

Of course I got the ram 1:1 speed thingy set properly aswell.


----------



## KedarWolf

Run from Linux Mint persistent USB.

Use Rufus to make a persistent GPT USB with maybe a 5GB persistent partition on a 16GB or 32GB USB.

Boot from USB, from Terminal run:



Code:


sudo apt update

Then:



Code:


sudo apt upgrade

Next:



Code:


 sudo apt install stressapptest

Finally for 32GMB of RAM.



Code:


stressapptest -W -M 28511 -s 7200 --pause_delay 7300

It takes precisely two hours to run.


----------



## The_King

StrongForce said:


> Hey guys.. I'm back, it's been a while !
> 
> I have recently upgraded to a 5600x with a B550 Tuf gaming plus mobo, never really got arround getting my 4266 Mhz Ripjaws RGB kit to run at good speeds stable, let alone the max speed.. so after looking more into it, now with this new CPU I feel like it's time I give memory overclocking a fair shot.. I was somewhat stable at 3733 C14 so I have a good kit, ran into hardware issues and possibly windows corrupted, so now I'm gonna be much more careful.. actually doing the testing on another windows install..
> 
> I'm quite new at RAM overclocking.. currently I'm running 3600 with some weird timings 16-15-16-37 and tRC 85 (that was auto I think it's a bit high) and I meant to put 15 as CL, the first.. anyways will do more tweaking but I just wanted to know, which are the best softwares to test stability "fast" this setting seem decent for now ran 10+ hours prime 95 big fft (memory testing) aswell as the techpowerup memtest64 at the same time, same thing 9 or 10 hours no issues
> 
> Also my 3d mark timespy score is really good with these settings, a bit better than with default ram speed which I guess it's not hard to do..but I was nearly at 10700 with stock 2080 trio.
> 
> Oh yea and I have Aida64, been running that full test 1h10 without issues. is Aida good to detect errors fast ? man RAM OC is such a time consuming thing to do..
> 
> and one last thing here is my memory cache performance from Aida with these settings :
> 
> View attachment 2571915
> 
> 
> The latency seems high though.. I haven't really took the time to compare with other similar settings.
> 
> Any tip to try to find decent timing and subtimings without too much trial and error ? is the DRAM calculator any good ? some people recommend it some people say it's trash.. same for the stability software testing some say this or that software isn't good.. it's confusing
> 
> In the short term I guess I just want to keep these settings until I can test more aggressive timings, might try 3600 c14 since I was running 3733 c14 without much issues (and really good performances..)
> 
> Of course I got the ram 1:1 speed thingy set properly aswell.


You should post a copy of your RAM timings use *Zentimings**, *if your voltage does not display then state what voltage you are using in your post.

Many think lowering primary timings only will get them best performance but its actually the subtimings that can make the biggest performance difference.

From your AIDA64 screenshot it looks like your subtimings are mostly or all on AUTO.


----------



## Anhphe93

I can't work stably with 1T GDM OFF. There are a lot of bugs in TM5(1usmus v3) and bugs in memtestpro. My configuration is stable on 1T GDM ON. What should i do next? Give me some advice.
VDIMM: 1.488


----------



## Melan

God damn those are high RDWR and WRRD.


----------



## Unifyx

KedarWolf said:


> Run from Linux Mint persistent USB.
> 
> Use Rufus to make a persistent GPT USB with maybe a 5GB persistent partition on a 16GB or 32GB USB.
> 
> Boot from USB, from Terminal run:
> 
> 
> 
> Code:
> 
> 
> sudo apt update
> 
> Then:
> 
> 
> 
> Code:
> 
> 
> sudo apt upgrade
> 
> Next:
> 
> 
> 
> Code:
> 
> 
> sudo apt install stressapptest
> 
> Finally for 32GMB of RAM.
> 
> 
> 
> Code:
> 
> 
> stressapptest -W -M 28511 -s 7200 --pause_delay 7300
> 
> It takes precisely two hours to run.
> 
> 
> View attachment 2571926
> 
> 
> View attachment 2571927


with how much VDIMM are you running this timings???

I'm running this timings at the moment with 1.45 VDIMM


----------



## KedarWolf

Unifyx said:


> with how much VDIMM are you running this timings???
> 
> I'm running this timings at the moment with 1.45 VDIMM
> 
> View attachment 2572011


I read that wrong at first, thought you meant how much RAM I had. :/

1.54V VDIMM .770v VTTs.

2x16GB CL14 3600 G.Skill Royal Elite


----------



## KedarWolf

Unifyx said:


> with how much VDIMM are you running this timings???
> 
> I'm running this timings at the moment with 1.45 VDIMM
> 
> View attachment 2572011


Can you post a Thaiphoon Burner screenshot, please?


----------



## Unifyx

KedarWolf said:


> Can you post a Thaiphoon Burner screenshot, please?


----------



## byDenoso

New stable cfg


----------



## The_King

Unifyx said:


> with how much VDIMM are you running this timings???
> 
> I'm running this timings at the moment with 1.45 VDIMM
> 
> View attachment 2572011


This is very similar to what I tested yesterday was surprised 3800 with RCD 15 just needed 1.45V. Will test out RCD 14 today.


----------



## Unifyx

@KedarWolf 

looks like, we have the same bin, because my RAM can do 3600 14-14-14-34 @1.4 VDIMM


----------



## Errende

I've never touched RAM settings before, so I thought I'd try following this guide for a start.
CPU is a 5900X. Motherboard is an Asrock B550 Steel Legend. Memory is G.Skill F4-3600C16D-32GVKC. 2x16 dual rank, should be Hynix CJR. In A2/B2 slots. No temp sensor.
I have SoC LLC set to 2, which is the step below flat (1). That's the suggestion I've seen for Asrock boards, anyway.

Following the "Finding a Baseline" section, I could boot into Windows up to at least 4000 MCLK with matched FCLK but anything past 3666 would build WHEA errors at the desktop. At 3666, Prime95 Large FFTs+OCCT VRAM wasn't giving errors.
With "Trying Higher Frequencies" settings, I was still getting WHEA errors on the desktop at 3800, but 3733 was fine until I ran Prime95 Large FFTs+OCCT VRAM, which got a WHEA error after a minute. I'm not sure I'm comfortable pushing VDIMM voltage over 1.45V.

I don't know if it matters, but this board has some weird VDIMM settings. 1.4V turns to 1.398V. 1.45V turns to 1.446V.

I haven't touched ProcODT, Rtt, or drive strengths as I have no knowledge on how those interact. They weren't changing at all on auto. Could changing those help?
Or should I just go with working on my timings at 3600? What voltages should I be looking at if I went that route?

Attached are ZenTimings with XMP values reported by taiphoon entered manually and everything else auto. And a pretty average AIDA result with those settings.


----------



## Taraquin

Errende said:


> I've never touched RAM settings before, so I thought I'd try following this guide for a start.
> CPU is a 5900X. Motherboard is an Asrock B550 Steel Legend. Memory is G.Skill F4-3600C16D-32GVKC. 2x16 dual rank, should be Hynix CJR. In A2/B2 slots. No temp sensor.
> I have SoC LLC set to 2, which is the step below flat (1). That's the suggestion I've seen for Asrock boards, anyway.
> 
> Following the "Finding a Baseline" section, I could boot into Windows up to at least 4000 MCLK with matched FCLK but anything past 3666 would build WHEA errors at the desktop. At 3666, Prime95 Large FFTs+OCCT VRAM wasn't giving errors.
> With "Trying Higher Frequencies" settings, I was still getting WHEA errors on the desktop at 3800, but 3733 was fine until I ran Prime95 Large FFTs+OCCT VRAM, which got a WHEA error after a minute. I'm not sure I'm comfortable pushing VDIMM voltage over 1.45V.
> 
> I don't know if it matters, but this board has some weird VDIMM settings. 1.4V turns to 1.398V. 1.45V turns to 1.446V.
> 
> I haven't touched ProcODT, Rtt, or drive strengths as I have no knowledge on how those interact. They weren't changing at all on auto. Could changing those help?
> Or should I just go with working on my timings at 3600? What voltages should I be looking at if I went that route?
> 
> Attached are ZenTimings with XMP values reported by taiphoon entered manually and everything else auto. And a pretty average AIDA result with those settings.
> View attachment 2572194
> View attachment 2572195


At 3666 try 1.4v dimm and:
16 19 19
RAS 37
RC 56
RRDS 4
RRDL 6
FAW 16
WTRS 4
WTRL 12
RFC 520, 500 or 480 may work
WR 16
RDRDSCL 4
WRWRSCL 4
RTP 8
CWL 16
RDWR 10 or 9
WRRD 3

Voltages should be fine, but try VDDP 0.9, CCD can probably do 0.9 aswell

DrvStr tends to work better at 24 20 24 24

Keep rest on auto


----------



## Melan

Errende said:


> I don't know if it matters, but this board has some weird VDIMM settings. 1.4V turns to 1.398V. 1.45V turns to 1.446V.


It's not that weird.
Tbh my kit of cjr wasn't responsive to voltage beyond 1.35v. I have 4x8gb sticks with almost the same timings Taraquin pointed out in the post above.
See what your CPU1.8v (or 1P8, or whatever it's called on asrock), might be worth fiddling a bit with it. I recall someone saying reducing/increasing it a bit helped stabilizing higher FCLK.

Edit: New BZ video might also help a bit. 



It's DJR but it's not that far off from CJR outside RFC afaik. Just don't set 1.6v


----------



## KedarWolf

EVGA X570 Dark










https://www.evga.com/products/product.aspx?pn=121-VR-A579-KR

Some people are getting 4000 MHz WHEA free even on a 5950x with this board where they could only do 3733 with the 3800 hole or only 3800 WHEA free.

Others it fixes the 3800 WHEA hole problem itself.

Right now, $399 USD on their website. $379 if you go there from pcpartpicker.com, it applies an affiliate code. Or Google an affiliate code.

Free shipping right now too, even to Canada.

And yes, I know the 7000 series coming out, but I'm damn sure scalpers will buy them all and I have no chance of getting a 7950x at retail.

Plus I'm waiting for better two DIMM motherboard options.


----------



## AliNT77

hey guys! any tips on getting fclk stable on cezanne ? running 1.35v vsoc and its not enough for even 2166 ... passes memtest 300% and tm5 for 3 cycles , but crashes in games after a minute or two. if i run 2133fclk 2200mclk it's stable so the problem is definitely fclk... unfortunately i only have a cheap ASUS b450m-a board and a wraith stealth cooler... ram is T-force Xtreem 4133c18 SR bdie. apu is 5600g , GPU: 2300 ,CPU: PBO -50mhz and percore UV and it is 100% stable.

i really don't wanna feed it more voltage than i already am so my question is : are there any other ways to get IF stable ?

another incredibly unusual thing is that my memory spits errors at 1.55+ (it gives error the moment i run memtest so i don't think it's overheating since i have a fan on it and the ambient temp is under 20 ). it also refuses to POST at anything above 1.65v. i thought bdie was supposed to be able to POST at 2.2v ! could this be related to the crappy MB?

thx


----------



## umeng2002

Here we go... instead of standing a fan on the GPU.


----------



## 99belle99

Would that little fan do anything. It only covers a small section of the RAM.


----------



## Errende

Taraquin said:


> At 3666 try 1.4v dimm and:
> 16 19 19
> RAS 37
> RC 56
> RRDS 4
> RRDL 6
> FAW 16
> WTRS 4
> WTRL 12
> RFC 520, 500 or 480 may work
> WR 16
> RDRDSCL 4
> WRWRSCL 4
> RTP 8
> CWL 16
> RDWR 10 or 9
> WRRD 3
> 
> Voltages should be fine, but try VDDP 0.9, CCD can probably do 0.9 aswell
> 
> DrvStr tends to work better at 24 20 24 24
> 
> Keep rest on auto


Right, I'll give those a shot with proper testing. I think I'll just stick to 3600 though?



Melan said:


> Tbh my kit of cjr wasn't responsive to voltage beyond 1.35v. I have 4x8gb sticks with almost the same timings Taraquin pointed out in the post above.
> See what your CPU1.8v (or 1P8, or whatever it's called on asrock), might be worth fiddling a bit with it. I recall someone saying reducing/increasing it a bit helped stabilizing higher FCLK.


With auto which says 1.800V, BIOS reads CPU VDD 1.8v as 1.808V. hwinfo reads a slightly fluctuating 1.808V/1.824V.


----------



## XenonQ

Hey everyone, been having some stability issues, so long story short, I replaced my mobo and ram like <6 months ago, 3 months ago the pc reboot while playing Path of Exile, mobo did 3 beeps and saw that it loaded the default setting in the bios, turned xmp on again and it refused to boot, after a few tries it did boot with xmp, it did reboot again playing PoE and Last Epoch (both game use a lot of ram) so I took the rams out, cleaned them, swapped their position and I dont remember it rebooted again, until a few days ago where it rebooted again.

Ran memtest86 for 5 hours: no errors

Ran extreme1 @anta, 5 cycles: no errors

Then today ran anta777 absolut config 3 cycles: 2 errors









Screenshot


Captured with Lightshot




prnt.sc





Ryzen 3 2200G
Asrock b450m pro4 (latest bios)
VENGEANCE® LPX 16GB (2 x 8GB) CMK16GX4M2B3200C16
Nvidia 1070

You guys think one of the stick is damaged or there is something I can try, Im going to test the ram individually and see what shows up.


----------



## Melan

Managed to get 1T working with addrcmdsetup 56 without PHYRDL mismatch on channels. Now just to test if it's actually stable.








Edit: stable but no difference whatsoever compared to 2T.


----------



## umeng2002

99belle99 said:


> Would that little fan do anything. It only covers a small section of the RAM.


It should drive air in between the sticks. The only place for it to exit is along the rest of the sticks not covered by the fan. I'll run a stress test tonight though. Those small Noctua fans really put out a lot of air.


----------



## Taraquin

Errende said:


> Right, I'll give those a shot with proper testing. I think I'll just stick to 3600 though?
> 
> 
> With auto which says 1.800V, BIOS reads CPU VDD 1.8v as 1.808V. hwinfo reads a slightly fluctuating 1.808V/1.824V.


Try them at 3666.


----------



## Unifyx

Melan said:


> Managed to get 1T working with addrcmdsetup 56 without PHYRDL mismatch on channels. Now just to test if it's actually stable.
> View attachment 2572336
> 
> Edit: stable but no difference whatsoever compared to 2T.


that's exactly what I see with my RAM settings.
with 1T GDM off and Addrcmdsetup 56 I have a tPHYRDL 28 on A1 and 26 on B1 but both 26 with 2T. 

I don't know, what this tPHYRDL is for but the performance was the same 1T 56 vs 2T


----------



## Wil8115

finally getting something worth posting. )







Gskill 3600C14 @ 3800, IF 1900/1/1, 1.5V 14-14-14-34
running stability tests while I'm at work.
5950X B0, X570 Aorus Elite.


----------



## XenonQ

So yesterday I spent most of the night testing the ram, first 3 cycles on each with ABSOLUT(01102021) anta777 profile, then 5 cycle, both test came out clean, both test were done with the stock xmp 2.0 profile at 3200mhz. Then I did another test with both rams together in dual channel setup with the stock xmp setting: Screenshot, yea thats a lot of errors, then today I did 3 cycles on each ram, clean again, tested both rams again but lowered the frequency from 3200 to 3000 and it finished with no errors, I will run a 5 cycle test tonight at 3000mhz to further confirm the stability. 

Also saw a post on reddit today about someone having issue running his corsairs ram at 3200mhz, did a google search and found bunch of threads and reddit post of people having this issue. So I guess the xmp setting from the mobo isnt good enough for these rams and you have to manually tweak it.

/r/overclocking/comments/xf8uc0/cannot_set_memory_to_3200mhz_without_computer/


----------



## Robby37

xpulse said:


> Hi, Overclockers,
> I am asking for help with overclocking RAM in my system.
> 
> System:
> MB Asus PRIME x570-Pro, latest BIOS
> RAM: 4 sticks G.Skill F4-3600C16-16GTZN: 16-16-16-36-1T; Total 64 GB
> CPU: Ryzen 5800x
> 
> Have a problem running these sticks (4) together on nominal 3600Hz in the system.
> All together starting only on 3533. When I tested dims separated all 4 DIMMs running (by 2) on 3733 easily without changing DOCP settings.
> The problem is: on this speed, the new RAM set is the same speed as my previous 64 GB 2933Mhz, with the same latency but a little faster.
> 
> Need some help with letting a set of 4 DIMMs run on 3600 or if possible higher speed.
> 
> View attachment 2569788
> 
> View attachment 2569789
> 
> 
> 
> Thank you all for any suggestions.


I run 64gb gskill 3200 c14 at 3733 14 14 14 28 42 . You have few things I see and I'm def not the most experienced . I'll post my current 3733 settings this weekend


----------



## Errende

Taraquin said:


> Try them at 3666.


Apologies for the essay, but I'm really trying to learn how this stuff works.



Spoiler: Spoiler to keep the thread tidy



I figured since just past 3666 seems to be impossible, sticking with 3600 would be the safe bet, but 3666 does seem okay at a glance.
I applied those settings in batches at 3600/1800 with 1.350V VDIMM, 1.100V SOC, 0.900V VDDG & CCD, 1.050V IOD to check for performance drops.
Linpack, Geekbench 5 and AIDA either improved with the big changes or at least stayed neutral on the smaller ones. As expected, I guess.

Bumped up to 3666/1833 with 1.398V VDIMM (thanks weird BIOS walls) with the other voltages the same.
Linpack only really saw an improvement to averages. Geekbench 5 multicore seemed to go up about 100 points on average. AIDA got +1k on read/write/copy but more importantly a reliable -1ns on top of 3600's -1ns from tightened timings. Can go as low as 58.8ns on a standard Windows boot.
I set AddrCmdDrvStr to 20 for both speeds but I tried 24 here and it didn't notice any difference in results. Set it back to 20 anyway.
Ran TM5 with anta777's absolut config when I went to sleep and it didn't hit any errors. Didn't load my GPU for extra case heat though.
I've been reading up some more on various aspects while waiting for things to complete. One thing I noticed was with 0.900V VDDP at 3666, tPHYRDL was desynced. 28 on A2, 26 on B2.
Raising VDDP to 0.950V fixed both to 26. Not sure how important that is. CCD left at 0.900V didn't matter. 0.900V VDDP at 3600 stays synchronized at 26.

Geekbench 5 multi might be slightly faster with CCD at 0.950V? It seems to average slightly higher than when I lower CCD to 0.900V or raise it to 1.000V.
Dropping IOD to 1.000V seemed to bring the average back down, but then also dropping SOC to 1.050V brought it up again? This voltage juggling is giving me a headache honestly.
So 1.050 SOC, 0.950V VDDP CCD, 1.000V IOD, maybe? Linpack average seemed to drop slightly again, but maybe that was just bad luck. I did let the system idle a bit beforehand though.

Trying VDIMM 1.350V with those voltages, I got better averages again with Linpack. Geekbench 5 seems to reliably get at least 14960 multi. AIDA read/write/copy is the same, and memory latency too, 59ns to 58.8ns.
Obviously I need to stress test it some more. But that leads me to a concern I had.
My daily OS is actually Fedora, and I'm not sure if/how Linux logs corrected/uncorrected memory errors. Or if it even can? I have rasdaemon which keeps track of CPU errors, but I'm not sure if it keeps track of anything for non-ECC memory.
So even if I'm able to pass stress tests in Windows, I'd be concerned about possible corrected/uncorrected errors on Fedora during real world use.
This Windows 10 install I'm using is just the required drivers and programs for testing.

I tried that voltage combination to get over 3666 again, thinking maybe less could be more.
1.050 SOC, 0.950V VDDP CCD, 1.000V IOD at 3800/1900 with 1.398 VDIMM seemed to work but after a few minutes an error popped up in hwmonitor, followed by a burst of them. (90+ at once) Same deal at 3733/1866.
Bumping VDIMM to 1.446V, I had to run prime95 large+OCCT VRAM to get an error to happen. But it still did. Followed by another of those bursts. AIDA latency was up to 63ns?
I feel like even if I did nail down a way to get 3733, I wouldn't trust it.

The WHEA errors when trying to go over 3666/1833 in my Microsoft-Windows-Kernel-WHEA/Errors filter are 20s, but the ones in Administrative Events are 19s with "Bus/Interconnect Error."
I also noticed a couple WHEA 19s associated with each startup at working settings. Turning off Fast Startup stopped those. Can't get it to happen again after turning it back on though.

Finally, I think I have a decent grasp on most of the timings, but I just don't get tRAS. Some people say you add some timings together, Buildzoid says it doesn't matter at all on Ryzen as long as tRC is set correctly... But then how do you calculate tRC if tRC=tRP+tRAS?

Relevant results if they'll help.


----------



## Melan

Errende said:


> Some people say you add some timings together, Buildzoid says it doesn't matter at all on Ryzen as long as tRC is set correctly... But then how do you calculate tRC if tRC=tRP+tRAS?


RCDRD + RTP + RP + BURST is what I used. BURST is 4. Calculate the rest yourself.


----------



## JustTyko

Hello everyone, that's my results of hours of testing:









No whea errors, 100cycles of TM5 with 1usmus_v3 pass, tCL 15, beacuse of tPHYRDL 26 (tCL 14=tHYRDL 26/28). I tried to change ProcODT on tCL 14, to achive 26/26, but sadly it didn't help. Anything to change?


----------



## Nighthog

Gotten 2066FCLK working if you overlook the WHEA reported errors as they seem to have no impact on stability/performance when you start fiddling with the FCLK in length on 5800X3D.
The amount of errors seems to stay in the ballpark the same regardless of FCLK on my sample so just went for how far I could push it.
The main cause of issues was USB dropouts & audio stutter, USB issue was solved by increasing voltages like VDD18 and VDDG_IOD while Audio stutter mainly also needed more VDDG_CCD than I was trying to do for most part with decent enough of *SoC voltage* around *~1.300V* for all around good results.
*VDD18* was a surprise on being needed so much as I did end up using, *2.120V* for the USB & audio stutter I encountered @ 2066FCLK.


----------



## The_King

JustTyko said:


> Hello everyone, that's my results of hours of testing:
> 
> View attachment 2572480
> 
> No whea errors, 100cycles of TM5 with 1usmus_v3 pass, tCL 15, beacuse of tPHYRDL 26 (tCL 14=tHYRDL 26/28). I tried to change ProcODT on tCL 14, to achive 26/26, but sadly it didn't help. Anything to change?


Try RDWR 9 or 8.

Was playing around with my Micron B-die Kit today also could not get off tPHYRDL 28 without changing tCL to 15.
@Veii Tried running CLX3 = TRAS but does not seem to do anything for performance or latency in AIDA64.































Managed to get 4133 to run 1:1:1.


----------



## Bix

I didn't think all 4 of my sticks could run RCDRD 14 but I finally managed to get flat 14s to work. PHYRDL trains to 28 on both channels (as it always seems to on MSI boards with an even CL at 1T).

@Taraquin this might be interesting to you (or anyone else like me who's thermally limited) - RttWr /2 allows for RttPark Disabled which in turn allows a lot more VDIMM without overheating errors starting to creep in. No thermal sensors on the Vipers (and I can't be bothered to reattach the thermocouple that's fallen off) but I was previously limited to around 1.49V when using 6/3/5 RTTs. I'm not sure exactly how much headroom I've got left but so far I've tested as high as 1.56V set / 1.57V get without getting any errors relating to overheating.

Thanks to @Veii and others we already know that RttPark is one of the main heat producers so maybe this isn't anything particularly newsworthy but I didn't know just how much of a difference it could make!


----------



## Robby37

I used to run diff timings and i was playing trying to get 3800 cl14 stable and i had to reset and dont have a recent backup but this runs good i still have some things off like i was able to run trrd 4/6 tfaw 16and now its 5/7 20 so i need to figure out what the right drv strength and maybetry setup times again i can't recall cause was over a yr ago that i did it all. Maybe this can help some 64gb b die guys and also maybe @Veii or @Taraquin have some insight on what i need to do . I would pay for a session to and then share my results if either want to do a quick consult @ $100 for the hr


----------



## XenonQ

Did some extra digging today and found out my ram are version 4.32 so C-die according to the wiki. Got 2 recommendations, lower the tRC from 72 to 55, and another from someone who was able to run them at 3600mhz with these settings (18 19 19 19 39 62. 1.35v)

Also found this thread in reddit, Im going to try some of these settings later and report back tomorrow.


----------



## MrHoof

XenonQ said:


> Did some extra digging today and found out my ram are version 4.32 so C-die according to the wiki. Got 2 recommendations, lower the tRC from 72 to 55, and another from someone who was able to run them at 3600mhz with these settings (18 19 19 19 39 62. 1.35v)
> 
> Also found this thread in reddit, Im going to try some of these settings later and report back tomorrow.


Stay around 1.35v aswell if u try to finetune further, C-die does not scale well with voltage and could also dmg the chips if going to high.


----------



## The_King

I didn't think my system was capable of running FCLK 2100...


----------



## Robby37

The_King said:


> I didn't think my system was capable of running FCLK 2100...
> View attachment 2572571


Why do you switch from 4 to 1 for twrrd ?


----------



## The_King

Robby37 said:


> Why do you switch from 4 to 1 for twrrd ?


I was running RDWR 9 with WRRD 4 because it was suggested to me by Veii in a previous post.
I most likely forget to change WRRD back to 4 when I cleared the BIOS.

My sticks are Micron B-die not Samsung B-die like what you are running in your setup.


----------



## Robby37

NEW!!! DRAM Calculator for Ryzen™ 1.7.3 (overclocking...


It is definitely a Ryzen 3600X on an ASUS TUF X570 motherboard. I am using Ryzen Master to see the values for tRFC2/4. I'm not aware of any other tool that shows these values. I set the tRFC2/4 values back to Auto and rebooted. The BIOS reads 486/192/132 and Ryzen Master is still reporting...




www.overclock.net




I found this but i am not sure what scl would be best but was curious why you ran 1 with 4 dimms ?


----------



## Robby37

The_King said:


> I was running RDWR 9 with WRRD 4 because it was suggested to me by Veii in a previous post.
> I most likely forget to change WRRD back to 4 when I cleared the BIOS.
> 
> My sticks are Micron B-die not Samsung B-die like what you are running in your setup.


Thanks ok makes more sense now. As you change your primary and scl though you should be changing your rdwr and then your wrrd as well


----------



## Taraquin

Bix said:


> View attachment 2572531
> 
> 
> I didn't think all 4 of my sticks could run RCDRD 14 but I finally managed to get flat 14s to work. PHYRDL trains to 28 on both channels (as it always seems to on MSI boards with an even CL at 1T).
> 
> @Taraquin this might be interesting to you (or anyone else like me who's thermally limited) - RttWr /2 allows for RttPark Disabled which in turn allows a lot more VDIMM without overheating errors starting to creep in. No thermal sensors on the Vipers (and I can't be bothered to reattach the thermocouple that's fallen off) but I was previously limited to around 1.49V when using 6/3/5 RTTs. I'm not sure exactly how much headroom I've got left but so far I've tested as high as 1.56V set / 1.57V get without getting any errors relating to overheating.
> 
> Thanks to @Veii and others we already know that RttPark is one of the main heat producers so maybe this isn't anything particularly newsworthy but I didn't know just how much of a difference it could make!


Will this work running 2x8 like I do?


----------



## Taraquin

Robby37 said:


> View attachment 2572537
> I used to run diff timings and i was playing trying to get 3800 cl14 stable and i had to reset and dont have a recent backup but this runs good i still have some things off like i was able to run trrd 4/6 tfaw 16and now its 5/7 20 so i need to figure out what the right drv strength and maybetry setup times again i can't recall cause was over a yr ago that i did it all. Maybe this can help some 64gb b die guys and also maybe @Veii or @Taraquin have some insight on what i need to do . I would pay for a session to and then share my results if either want to do a quick consult @ $100 for the hr


Sometimes running RCDRD 1 higher allows for lower RRDS/FAW, but unsure if worth it performancewise.


----------



## Taraquin

Bix said:


> View attachment 2572531
> 
> 
> I didn't think all 4 of my sticks could run RCDRD 14 but I finally managed to get flat 14s to work. PHYRDL trains to 28 on both channels (as it always seems to on MSI boards with an even CL at 1T).
> 
> @Taraquin this might be interesting to you (or anyone else like me who's thermally limited) - RttWr /2 allows for RttPark Disabled which in turn allows a lot more VDIMM without overheating errors starting to creep in. No thermal sensors on the Vipers (and I can't be bothered to reattach the thermocouple that's fallen off) but I was previously limited to around 1.49V when using 6/3/5 RTTs. I'm not sure exactly how much headroom I've got left but so far I've tested as high as 1.56V set / 1.57V get without getting any errors relating to overheating.
> 
> Thanks to @Veii and others we already know that RttPark is one of the main heat producers so maybe this isn't anything particularly newsworthy but I didn't know just how much of a difference it could make!


Unable to boot woth RttPark disabled, any tips?


----------



## Nighthog

The_King said:


> I didn't think my system was capable of running FCLK 2100...
> View attachment 2572571


Looking at your voltages you seem to have sensible room to run it overall and even try for more. No issues with USB or AUDIO stutter for your running this? I really needed to push my voltages high to avoid such things even with only 2066FCLK.


----------



## The_King

Nighthog said:


> Looking at your voltages you seem to have sensible room to run it overall and even try for more. No issues with USB or AUDIO stutter for your running this? I really needed to push my voltages high to avoid such things even with only 2066FCLK.


I have had no issues with USB at all.

The Audio stutter was very noticeable at FCLK 2067 increasing IOD to 1.08V completed solved any issues with the Audio even at 2100 FCLK no Audio stutter problems.


----------



## Nighthog

The_King said:


> I have had no issues witrh USB at all.
> 
> The Audio stutter was very noticeable at FCLK 2067 increasing IOD to 1.08V completed solved any issues with the Audio even at 2100 FCLK no Audio stutter problems.


Seems you have a much stronger IOD/memory controller in your ship than usual. Could do quite well with that chip I think.

EDIT: I could boot 2100FCLK but the Audio noise was horrible and using as little VDDG_IOD as you around 1.100 was slowing the system to a crawl making Audio stutter crackling even worse.


----------



## Blackfyre

Why does enabling virtualization in the BIOS and Hypervisor in Windows cause these latency issues and incorrect reading and drop CPU FSB?

I don't recall this ever happening when I had virtualization enabled on my Intel setup.

My memory latency is ~51.5ms with virtualization disabled in the BIOS.


----------



## The_King

Nighthog said:


> Seems you have a much stronger IOD/memory controller in your ship than usual. Could do quite well with that chip I think.
> 
> EDIT: I could boot 2100FCLK but the Audio noise was horrible and using as little VDDG_IOD as you around 1.100 was slowing the system to a crawl making Audio stutter crackling even worse.


Try increasing VSOC to around 1.2V also try setting IOD between 1.05V-1.09V when I used 1.1V my system was also slow.

CCD and VDDP values are also important, I had to fine tune each setting along with VSOC to get stability.


----------



## Melan

Blackfyre said:


> Why does enabling virtualization in the BIOS and Hypervisor in Windows cause these latency issues and incorrect reading and drop CPU FSB?
> 
> I don't recall this ever happening when I had virtualization enabled on my Intel setup.


Because this enables virtualization-based security in windows. Normally having "Memory integrity" disabled in device security is enough to not get the error message.


----------



## Robby37

Taraquin said:


> Sometimes running RCDRD 1 higher allows for lower RRDS/FAW, but unsure if worth it performancewise.


----------



## Robby37

Any advice for 64gb b die as far as setup timings or tcke ? i have ran 56 and 3 3 15 with tcke 9 and also ran just 6 tcke and used to run 1 never really figured out what was best


----------



## dimkatsv

Any advices on what i am still able to work on?
2x16 2R kit of Hynix DJR (sadly B-die isn't very affordable where i live). Motherboard is also quite cheap, as well, but working with what we have, right...










Additional info for context.
tCLworks strange. System won't even post at 17-18. Hard reset is only choise. Somehow my mobo don't like tCL tuning...
tRCD_RD won't go lower
tRP won't go lower
tRC=56 will error me out fast.
tWTRS=2 technically possible, but not daily stable
tWTRL=7 - won't post
tRFC... i guess can be tightened just a bit, but 230ns hadn't worked out for me
tRTP=6 will error me out in testing.
tRDWR=7 - will error me out even without testing (just randomly)
tWRRD=3 won't post
tRDRDSD/DD -1 won't post
tWRWRSD/DD -1 won't post
tCWL=14 won't post
-----------------------------------------
from tRDRDSCL and tWRWRSCL i don't remember outcome, likely -1 = won't post

Stabilzing 1933 FCLK probably is possible (and i tried 1.2.0.3C AGESA with up to 1.15 or 1.2 VDDG - nope, this one won't stabilize FCLK higher), but with at least PLL_18 being at least 1.88-1.92... But i am not sure if i would be able to run memory stable. Anything above - WHEA
Probably possible to run 101 BCLK, as it posts and even somehow works... But need extensive testing, also limits highest possible CPU frequency from 4850 to 4825 (multiplier stuff)
With VDDP =900 (Auto) i get tPHYRDL desync 28/26 (it is fine with 950, maybe i can try lower values)
ProcODT is on Auto, but it works from 28.2 (lowest), up to 60... No extensive stability testing, though.
RttNom=Auto, RttWr=Auto, RttPark=Disabled (manually, read that it helps making memory run colder, but if there are catches, would gladly take any info)
All CadBuses are on Auto... Setting ClkDrvStr to 40-60 helps with booting 1T GDM off... But it fails miserably in y-cruncher (and not much benefits in AIDA as well)
CMD setup delays even though set to 0 also finicky. With 56 they boot, with 28 no post, for example

Anyways. Would gladly take info on benefits and negatives of setting ProcODT/RttNom/RttWr/RttPark/DrvStr values higher and lower for every important one).


----------



## The_King

Nighthog said:


> Seems you have a much stronger IOD/memory controller in your ship than usual. Could do quite well with that chip I think.
> 
> EDIT: I could boot 2100FCLK but the Audio noise was horrible and using as little VDDG_IOD as you around 1.100 was slowing the system to a crawl making Audio stutter crackling even worse.


I managed to boot 4733 unsynced having some stability issues with 4800MT.


----------



## Errende

I finally tried some tests with memory clock and fabric clock on their own.
Memory at 3800 with fclk at 1800 didn't have any errors with p95 large+occt vram after a quick 5 minute run.
Memory at 3600 with fclk at 1900 got a WHEA before I could even get both programs started. Same with fclk at 1867.
Am I correct to assume this points to my IMC being a low bin?


----------



## The_King

Errende said:


> I finally tried some tests with memory clock and fabric clock on their own.
> Memory at 3800 with fclk at 1800 didn't have any errors with p95 large+occt vram after a quick 5 minute run.
> Memory at 3600 with fclk at 1900 got a WHEA before I could even get both programs started. Same with fclk at 1867.
> Am I correct to assume this points to my IMC being a low bin?


FCLK should be in Sync 1:1:1 You should not be running 3600 with FCLK 1900.

3600 goes with FCLK 1800 (3600/2)

3800 goes with FCLK 1900 (3800/2).

You can possibly get rid of WHEA errors with FCLK 1900 by adjusting VSOC VDDP CCD or IOD.
You have to fine tune these values according to your system setup.
Also make sure UCLK=MCLK is selected.

If you are running an AMD system post your Zentimings.


----------



## Errende

The_King said:


> FCLK should be in Sync 1:1:1 You should not be running 3600 with FCLK 1900.


Yeah I know, but I was trying to narrow down what my wall seems to be.
No amount of adjusting voltages stops my WHEAs at the desktop as soon as I go over 2666/1833.
I attempted some procodt and drvstr spreads too but didn't get anywhere.


----------



## Dziarson

The_King said:


> I managed to boot 4733 unsynced having some stability issues with 4800MT.
> View attachment 2572692
> View attachment 2572693
> View attachment 2572695


Try AIDA for latency .


----------



## Bix

Taraquin said:


> Unable to boot woth RttPark disabled, any tips?


I'm definitely no expert with any of this but changing to RttWr /2 from /3 seems to require a lot of re-balancing as it has a far bigger impact than changing RttNom and RttPark. Other than that I also increased drive strengths from 24-20-24-24 to 30-20-30-24. 1.8 also raised to 1.83V (1.86V get) if that makes a difference - I needed that to drop ProcODT to 28.

For some reason my combo is generally able to at least POST any combination of RTTs, even if totally unstable. 

I'm sure @Veii and @Bloax can shed more light on this than I can!


----------



## Robby37

Bix said:


> I'm definitely no expert with any of this but changing to RttWr /2 from /3 seems to require a lot of re-balancing as it has a far bigger impact than changing RttNom and RttPark. Other than that I also increased drive strengths from 24-20-24-24 to 30-20-30-24. 1.8 also raised to 1.83V (1.86V get) if that makes a difference - I needed that to drop ProcODT to 28.
> 
> For some reason my combo is generally able to at least POST any combination of RTTs, even if totally unstable.
> 
> I'm sure @Veii and @Bloax can shed more light on this than I can!


What was the benefit of rttwr 2? I have managed Park disable so far but get alot of tm5 errors "cad bus ,timing or drv strength related so I am working on it .


----------



## Bix

Robby37 said:


> What was the benefit of rttwr 2? I have managed Park disable so far but get alot of tm5 errors "cad bus ,timing or drv strength related so I am working on it .


The technical reasoning is very much beyond me but as I understand it, powering the DIMMS using Wr produces far less heat than Park (see below from Veii)



Veii said:


> I will have to look today.
> But the "sleek" part rather goes to the low footprint heatsink
> Watercooling them, might even make them warmer
> 
> I haven't compared it from the technical side of things if it matches my gotten out results
> But _WR is triggering dynamic On-DieTermination. Adjustable by shifting "phase" left and right
> 
> The positive part of it:
> 
> it does shift misaligned reflections, which means the signal is more unlikely to reflect back and so lowers ripple and noise | research micron technology
> it is capable to make up and set own borders, floor and top ~ if one of both is only provided. This helps point 1 even more
> generally it's work is to figure minimum required ceiling and adjust it dynamically
> Part of of this is very beneficial working together with MCLK timed powerdown
> 
> The reason why /2 is better, to my testing
> Is because generally its stronger, but it doesnt mean more heat
> I am not confident if it only changes +/- range (increases control range) or purely the strengthness similar to RTT_PARK
> I only check results later with technical documents, to prevent influencing a neutral viewpoint and have so no expectation's of the outcome
> 
> So far it showed me that heat was lower, and yet helps power dimms better than lower PARK (well they are similar, just WR is more controlling than X floor (park) or Y ceiling (nom) ~ WR maintenances both)
> 
> WR /2 generally is hard to get running single rank
> It took me down to /7 PARK, before i could disable it (which moves in the >1.66v range)
> Only afterwards WR was even taken as /2
> 
> But each WR has their own range of NOM and PARK ceiling
> /6 PARK on /3 WR is different Ampere outcome than /5 PARK /2 WR (first being higher and so worse)
> 
> I am not sure how to explain it fully. Still miss more data for its floor range. (After which voltage and when it starts to work
> But generally getting it to run is better. When you "can" get it to run


----------



## Nd4spdvn

I was also able to boot with rttwr /2 and park /disabled and do this, it was even stable in TM5 1usmus for 5 cycles until I had to stop it. This attempt is more aggressive on tRAS, tRC and tRP (used to run them 27, 15 and 42 before the Rtt changes).


----------



## The_King

Not sure why performance numbers are slightly down compared to 4133MT









@Veii Running RCD + RCD + 6 did improve latency slightly.


----------



## Nd4spdvn

Nd4spdvn said:


> I was also able to boot with rttwr /2 and park /disabled and do this, it was even stable in TM5 1usmus for 5 cycles until I had to stop it.


Quoting myself, as in normal PC usage I had all sort of nasties, so the above was obviously not stable. I also tried again a C14 tRCDRD 14 setup, had lots of errors like in the past, probably even more, can't remember exactly as it's been awhile since I tried to stabilize a flat 14. I am back to my c15 daily set and will focus on lowering tRC instead.


----------



## Catmart10

Hi I'm from this thread

__
https://www.reddit.com/r/overclocking/comments/xe55cj
What kind of nonsense? I left only the main timings and voltages of memory and soc. Why were there even more errors than before, when there was 1 or not at all?


----------



## Taraquin

The_King said:


> Not sure why performance numbers are slightly down compared to 4133MT
> View attachment 2572741
> 
> 
> @Veii Running RCD + RCD + 6 did improve latency slightly.
> View attachment 2572742
> View attachment 2572743


You may need more SOC,IOD or VDD18, maybe all.


----------



## dimkatsv

Catmart10 said:


> Hi I'm from this thread
> 
> __
> https://www.reddit.com/r/overclocking/comments/xe55cj
> What kind of nonsense? I left only the main timings and voltages of memory and soc. Why were there even more errors than before, when there was 1 or not at all?
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2572759
> View attachment 2572760


Oh my, what i had just saw. Is it stock XMP?> If yes, then check for WHEAS. Not to say it is 2x8GB 1R stick setup. Something is clearly just wrong there, and probably it isn't temp related

Too optimistic main timings. Especially tRCDRD and tRP
tRCDWR usually can go as low as 8
With your grand tRC timins, tRAS=21 shouldn't cause issues
tRC is too much, though, imo... i would've expected about 64 at max, i suppose (but i do have H8D chips, while you have M8E)
tRRDS and tRRDL are higher than optimun (usually 4/4 4/6 4/8 or 6/12 in worst cases).
tFAW is complete trash tier XMP (it should be 4x tRRD_S timing, because it is how it works... Four Access Window)
tWTRS/L can go lower (usually it is 4/12 3/12 4/8 or 3/8)
tRFC can go lower, to around 260ns for M8E iirc.
tRTP can be 12, 10, 8 or 6. 10 or 8 would be kind of safe bet. 
tWRRD feels too low. For my DJR kit i can only run tRDWR=8 and tWRRD=4 for example.
Maybe touching ProcODT can help you with stability. Also something is wonky with you Rtt resistances setup.


----------



## Bix

Catmart10 said:


> Hi I'm from this thread
> 
> __
> https://www.reddit.com/r/overclocking/comments/xe55cj
> What kind of nonsense? I left only the main timings and voltages of memory and soc. Why were there even more errors than before, when there was 1 or not at all?
> View attachment 2572759
> View attachment 2572760


Before doing anything with your timings you need to check that the fabric is stable at FCLK 2000, otherwise you won't have a clue where the errors are coming from. Set your memory frequency and timings to XMP (ie. out of sync with FCLK) and make sure you can pass 4 iterations of y-cruncher (press 7 to run all stress tests) and an hour of OCCT. If it's really unstable you'll hard crash, less unstable you'll get errors. 

DRAM Calculator was for Zen 2 so although the timing suggestions can be useful, the RTTs and CAD_BUS values won't work. If you're planning to keep GDM enabled then you're probably best just leaving it all on Auto.


----------



## Robby37

TimeDrapery said:


> It seems pretty "real" to me!!!
> View attachment 2490179


I get 54 to 56 ns with 2t timings at 3733 is what others are meaning . Its not beneficial is the point.


----------



## dimkatsv

Looks like i managed to break laws of physics with that RAM latency. 
Yeah, GDM OFF 1T seems off reach for me yet


----------



## The_King

Taraquin said:


> You may need more SOC,IOD or VDD18, maybe all.


Thanks for that I did increase it after reading your comment I went even higher and that did improve performance. VSOC 1.23V IOD 1.15V. 
I can't adjust VDD18 on this board. There is no option in the BIOS to do that. How high can one go on IOD voltages?


----------



## Dziarson

@dimkatsv "special operation" on ram and same results .


@The_King Try VTT 0,83 it is working good on 16GB, and you can try go lower TRFC


----------



## The_King

> @The_King Try VTT 0,83 it is working good on 16GB, and you can try go lower TRFC


The dimms I have are Crucial Ballistix MAX 4400 CL19 16GB Single Rank. (C9BLJ - Micron B-die)

They don't have the same properties has a 16GB Dual Rank Samsung B-die dimm which is in your PC.
Trfc can can go down to 280ns but I leave some headroom because it can cause boot issues at 280ns.

Lowering TRFC on Micron does not seem to have the same effect has lowering TRFC on Samsung B-die.
I have several Samsung B-die kits and that benefits greatly from lowering TRFC.

Your VDIMM is high 1.76V that is why your MEM VTT is 0.88V its VDIMM / 2. (half)


----------



## Dziarson

@The_King
I do always set the voltage by myself, but as the Buildzoid once said, VTT 0.83 is the best for most of the memory, and I cannot disagree with that, I had a few kits of 16GB and always worked.
Try set VTT you canot broke nothing.








My samsung B-die like high V and dont have high Temps .


----------



## The_King

Dziarson said:


> @The_King
> 
> Try set VTT you canot broke nothing.


I know who BZ is and have watched a few of his videos and would be very suprised if he made such a dangerous statement like that.
You can absolutely corrupt your entire Windows installation by setting the incorrect VTT. I am talking from experience.

You could cause permanent damage to your system setting incorrect VDIMM and VTT. So if BZ did say that tell him I said he should retire from giving people advice.


----------



## Dziarson

Well, now I have to wonder after what you wrote, Whether, If i understood what he was saying correctly. Although it never happened to me that I smashed win a bad VTT


----------



## The_King

Dziarson said:


> Well, now I have to wonder after what you wrote, Whether, If i understood what he was saying correctly. Although it never happened to me that I smashed win a bad VTT


Your RAM handles high VDIMM very well thats why you can run 1.76V VDIMM and 0.88VTT or 0.83VTT on another setup or with different DIMMS those settings can cause damage to the DIMMS or OS corruption.


----------



## Taraquin

Bix said:


> I'm definitely no expert with any of this but changing to RttWr /2 from /3 seems to require a lot of re-balancing as it has a far bigger impact than changing RttNom and RttPark. Other than that I also increased drive strengths from 24-20-24-24 to 30-20-30-24. 1.8 also raised to 1.83V (1.86V get) if that makes a difference - I needed that to drop ProcODT to 28.
> 
> For some reason my combo is generally able to at least POST any combination of RTTs, even if totally unstable.
> 
> I'm sure @Veii and @Bloax can shed more light on this than I can!


Remember I have 2x8gb SR. My default is disabled/disable/5.


----------



## Bix

Taraquin said:


> Remember I have 2x8gb SR. My default is disabled/disable/5.


Ah, I see. IIRC you need either Nom or Park (or both).
Have you tried 7/disabled/disabled or 6/disabled/disabled?


----------



## Taraquin

Bix said:


> Ah, I see. IIRC you need either Nom or Park (or both).
> Have you tried 7/disabled/disabled or 6/disabled/disabled?


No, but will try that. Do you know if different Park valurs will affect heat buildup if I'm not successful disabling it? Are 7 or 3 the least heat-producing?


----------



## Bix

Taraquin said:


> No, but will try that. Do you know if different Park valurs will affect heat buildup if I'm not successful disabling it? Are 7 or 3 the least heat-producing?


/7 (highest divider) is the weakest and least heat producing.


----------



## Taraquin

Bix said:


> /7 (highest divider) is the weakest and least heat producing.


I tried a bit yesterday and seemed errors came more using 3 than 7 so that makes sense!


----------



## dimkatsv

Bix said:


> /7 (highest divider) is the weakest and least heat producing.


And what about Disabled set? Does it completely remove resistance or set it to 240 ohms?


----------



## Bix

dimkatsv said:


> And what about Disabled set? Does it completely remove resistance or set it to 240 ohms?


Yes, disabled removes it. 
/1 is 240 ohms.


----------



## Taraquin

Bix said:


> Ah, I see. IIRC you need either Nom or Park (or both).
> Have you tried 7/disabled/disabled or 6/disabled/disabled?


Tried those combos, no boot, dis\dis\7 worked quite good however, I can pass a full cycle before some errors occur in TM5 at 1.54v 14 flat, half way in second round errors begin to pile.


----------



## byDenoso

JustTyko said:


> Hello everyone, that's my results of hours of testing:
> 
> View attachment 2572480
> 
> No whea errors, 100cycles of TM5 with 1usmus_v3 pass, tCL 15, beacuse of tPHYRDL 26 (tCL 14=tHYRDL 26/28). I tried to change ProcODT on tCL 14, to achive 26/26, but sadly it didn't help. Anything to change?


SD's and DD's: 1-5-5 / 1-7-7
Try to lower that RDWR
And try to get rid of these setup timings (Increase ClkDrvStr to at least 40ohm)


----------



## The_King

Nevermind dropping RCDWR to 10 caused Y-cruncher times to increase by 15 seconds.


----------



## MrHoof

byDenoso said:


> SD's and DD's: 1-5-5 / 1-7-7
> Try to lower that RDWR
> And try to get rid of these setup timings (Increase ClkDrvStr to at least 40ohm)


SD´s DD´s don´t do anything on 2xSR he could even set them to 1 would not make difference.

DD´s are only used with 4 dimms either 4x16 or 4x8
SD´s are only used on Dual Rank either 2x16 or 4x8


----------



## Robby37

Taraquin said:


> Sometimes running RCDRD 1 higher allows for lower RRDS/FAW, but unsure if worth it performancewise.





Taraquin said:


> Sometimes running RCDRD 1 higher allows for lower RRDS/FAW, but unsure if worth it performancewise.


I started from scratch and lowered back to 3600 and am going to start creeping back up . Anyway I want to try and achieve 3800 as I feel like even if I have to loosen some primaries it will be faster and I may even be able to go higher as I can post fclock over 2000. What changes would you suggest to go along with rcdrd 15 from these ? I want to start increasing clock but don't know if I should go to 15 flat for primaries or if just rcdrd 15 is enough and then I see some drop rcdrw to like 8 but don't know if that is a no go with 4 dr sticks . If it is possible then I am not sure what else to change to pull it off. tRTP and tRDWR seem to be the ones that get me stuck at boot where I have to remove a sti k to even allow me to get back into bios without doing a cmos reset . So that is why I am wanting to try your advise for adding 1 rcdrd


----------



## dimkatsv

The_King said:


> Nevermind dropping RCDWR to 10 caused Y-cruncher times to increase by 15 seconds.


Somehow got 118.5 once, and since then cannot do less than 119.5... But tbh i was focused more on precision of my overclock, rather than higher boosts.
It took me some time to understand that my CPU was AVX-2 stable with all core CO -30, while to get it SSE stable (with CO -30 ALL it errored out almost instantly) it required me tuning down negative CO up to -22/-16/-14/-24/-22/-30 and 2-3 days of testing. Funniest part. Boost clock were basically no different between AVX and SSE. And now my 2925 mHz GPU OC is stable in games while it wasn't before (it was only with 2875-2890)
My RAM OC on other side hit walls really freaking fast. Like one value - work fine, another - won't even post
Importance of all around testing!!!


----------



## Robby37

I am gettign their again much cleaner so far i am at real nice drv strength and proc odt so hopefully will turn out better . What sucks is 32 gb will run almost anything i throw at it . I almost want to just run 32 gb but i do alot of cad and video editing.


----------



## Robby37

Bix said:


> Yes, disabled removes it.
> /1 is 240 ohms.


So for rtt nom 7 is the weakest ? I was running 7 3 1 and now am 7 2 0 so I made a jump from strongest to weakest ? I read few pages back someone saying that 1 will pull more heat out of the dimms but is hard on the traces . That made no sense to me unless its letting voltage bypass the dimms or something ?


----------



## dimkatsv

Robby37 said:


> So for rtt nom 7 is the weakest ? I was running 7 3 1 and now am 7 2 0 so I made a jump from strongest to weakest ? I read few pages back someone saying that 1 will pull more heat out of the dimms but is hard on the traces . That made no sense to me unless its letting voltage bypass the dimms or something ?


Well, i am running Disabled/3/Disabled. (2x 2R H8DJR)
If i enable RttPark, system will boot only up to RZQ/5, /6 and /7 won't even boot, so i also wanna know how it works.


----------



## Robby37

dimkatsv said:


> Well, i am running Disabled/3/Disabled. (2x 2R H8DJR)
> If i enable RttPark, system will boot only up to RZQ/5, /6 and /7 won't even boot, so i also wanna know how it works.


what drive strength you run ? If what I am understanding now is true it means we have been looking at things wrong. A large dimm load would need less resistance since it would have its own but everything I understood is that I should need like 60-20-30-20 meanwhile I am working my way less and less and never ran better







ignore the tm5 I was slicing something so I used ram and itstopped working on the 5th cycle but I am running a 40 cycle test now so will see what happens if stable I will drop proc odt again which I am floored that 4 dr dimms are ok with this . I used to need 1.51v now I am down to 1.475. So this new approach is working better in every way maybe ill get up to 3800 cl14 flat this time instead of 3733 max .
\


----------



## The_King

Seems to be a wall at 51.5ns. Got a little brave with the voltages but not pratical for daily or overall performance has Y-cruncher numbers are down by 5 secs compared to 3800 FCLK 1900.
Thanks to @Taraquin once again for the help. 
















Also booted 4800MT 2:1


----------



## Taraquin

The_King said:


> Seems to be a wall at 51.5ns. Got a little brave with the voltages but not pratical for daily or overall performance has Y-cruncher numbers are down by 5 secs compared to 3800 FCLK 1900.
> Thanks to @Taraquin once again for the help.
> View attachment 2572924
> View attachment 2572925
> 
> 
> Also booted 4800MT 2:1
> View attachment 2572929


I ran 4000cl16 for a year, but ended up returning to 3800cl15. Why?
For 4000 I needed 1.11v SOC, 1.04V IOD, 1.88V VDD18. Unless I used those excact voltages I got performanceregression in Y-cruncher, linpack etc. SOTTR and other games that loves bandwith had about 2% higher fps when cpu bound so 4000 was clearly faster.
For 3800 I needed 1.06V SOC, 0.98V IOD, 1.6V VDD18. The last part affects temp on CPU during load quite a bit (over 5C) and made noise from my D15 go from good to annying when loading games etc so I settled for slightly worse gamingperformance in a few games for lower noise/temps.
I also turned of +200 pbo, but use -30 CO allcore. I lowered EDC and TDC to 48/72. In games pbo gave me about 2-3% higher fps, but temp rose by 8C on avg and noise increased.
I can no run cinebench, get 11800 points, temp around 66-68C, 74W max consumption, noise below 35dB at CB23 so very satisfied 

Summary: From what I have seen, general positive or atleast neutral performance scaling needs higher VDD18 in most cases past 1900fclk. If you have WHEA19 issues above 1900fclk like most do, the shear amount of error-reporting may also lower performance.


----------



## The_King

Taraquin said:


> I ran 4000cl16 for a year, but ended up returning to 3800cl15. Why?
> For 4000 I needed 1.11v SOC, 1.04V IOD, 1.88V VDD18. Unless I used those excact voltages I got performanceregression in Y-cruncher, linpack etc. SOTTR and other games that loves bandwith had about 2% higher fps when cpu bound so 4000 was clearly faster.
> For 3800 I needed 1.106V SOC, 0.98V IOD, 1.6V VDD18. The last part affects temp on CPU during load quite a bit (over 5C) and made noise from my D15 go from good to annying when loading games etc so I settled for slightly worse gamingperformance in a few games for lower noise/temps.
> I also turned of +200 pbo, but use -30 CO allcore. I lowered EDC and TDC to 48/72. In games pbo gave me about 2-3% higher fps, but temp rose by 8C on avg and noise increased.
> I can no run cinebench, get 11800 points, temp around 66-68C, 74W max consumption, noise below 35dB at CB23 so very satisfied
> 
> Summary: From what I have seen, general positive or atleast neutral performance scaling needs higher VDD18 in most cases past 1900fclk. If you have WHEA19 issues above 1900fclk like most do, the shear amount of error-reporting may also lower performance.


I notice that above 4066 VDDP, IOD and SOC becomes very sensitive. I also notice with to too high CCD I was losing latency in AIDA64. Sadly I can't adjust VDD18 on my B450M Mortar MAX

This is my 5600 non X with the Same RAM but 3800 FCLK 1900 when I ran R23 with 4200 FCLK 2100 score was 11400. Didn't even bother screenshotting that! 


Spoiler: R23 11824














I managed to break 12K in R23 but that was with my Patriot Viper Dual rank setup.( 4 X SR)


Spoiler: R23 12008















Edit
@Taraquin I just beat my Patriot Viper setup now using this RAM. Micron FTW 
(Looks like this Micron RAM is easier on the IMC with my Patriot Viper Samsung B-die I could only do -23 all core with this Micron B-die I can do -27 all core.)


Spoiler: R23 12108


----------



## dimkatsv

Robby37 said:


> what drive strength you run ? If what I am understanding now is true it means we have been looking at things wrong. A large dimm load would need less resistance since it would have its own but everything I understood is that I should need like 60-20-30-20 meanwhile I am working my way less and less and never ran better


I sent it before, but here you go (increasing VDIMM from 1.45 to 1.46 helped to fix that one single TM5 anta ABSOLUT error 0 after test 7 error)


----------



## Robby37

The_King said:


> Seems to be a wall at 51.5ns. Got a little brave with the voltages but not pratical for daily or overall performance has Y-cruncher numbers are down by 5 secs compared to 3800 FCLK 1900.
> Thanks to @Taraquin once again for the help.
> View attachment 2572924
> View attachment 2572925
> 
> 
> Also booted 4800MT 2:1
> View attachment 2572929


From the formulas I found you should run scls of 4 since half your tcrd is 10 if rounded up and you want to be below when scl x twrrd but as large as you can . When you violate that rule like scl 5 you regress or error and when you are smaller than te window you leave some performance on the table AFAIK. worth a shot tho . With the 4200 obv not the 4800


----------



## xpulse

Hi All,
Can you please help me with timing setup for my config. 4x16 = 64GB. Timing seems to be pretty bad. 


















Thanks


----------



## dimkatsv

xpulse said:


> Hi All,
> Can you please help me with timing setup for my config. 4x16 = 64GB. Timing seems to be pretty bad.
> 
> View attachment 2573023
> 
> 
> Thanks


4067 4x 1R 16 GB... Micron, i suppose? Oh, wait, it might be Samsung looking at these primaries.
Well... tRCDWR should go to 8. With high tRC, tRAS doesn't affect stuff, so you can tune it down up to 21... Find lowest point of tRC stability. If it Micron, it will be high up, if Samsung B-die, it can go quite a lot lower.
Major performance hit from tRRDS/tRRDL/tFAW
tFAW should ALWAYS be 4x tRRDS... So, set it to 28 first, if stable then try (tRRDS/tRRDL/tFAW) 6/10/24, 6/8/24, 4/8/16, 4/6/16, 4/4/16 in that order up to last which was fine. (4/4/16 is lowest possible)
then tWTRS/tWTRL...Try 4/12, then 3/12, then 3/8, then if you able you may attempt to go for 2/8 2/7, but success there is quite unlikely one.
tWR... i don't remeber rules, but iirc it should either be 16 ot 12... going to 8 should be teoretically possible, lower is dangerous to set.
tRTP must be set before tRFC, as it is basically counts as multiplier. Go as low as you can (usually it is set to 8)
tRFC... With Micron you can attempt to do 250-280 ns, maybe lower is possible. With Samsung B-die, 120-140 ns are likely to be at. You only need to set tRFC, as tRFC2 and tRFC could be remained at auto.
Calculation of tRFC for you is Time(ns)*Memory frequency/(2*1000) so for you it is 280*4067/2000=569.38), then increase it up to closest number divisible by tRTP you set. So in this case for tRTP=8 it will be like that: 569.38=71.1725 ===> 72*8=576.
tRDRD_SCL/tWRWR_SCL = go as low as you can
tRDWR/tWRRD = go as low as you can.
tRDRDSD and tWRWRSD don't apply for your setup, as you have 4x1R sticks.
tRDRDDD and tWRWRDD = go as low as you can
tCKE = go as low as you can (can be straight set to 1)

Then you can play with resistances a bit. RttPark is most useful to set to "lower" value (as it is measured in RZQ/X, where RZQ is 240 Ohm resistor).


----------



## xpulse

dimkatsv said:


> 4067 4x 1R 16 GB... Micron, i suppose? Oh, wait, it might be Samsung looking at these primaries.
> Well... tRCDWR should go to 8. With high tRC, tRAS doesn't affect stuff, so you can tune it down up to 21... Find lowest point of tRC stability. If it Micron, it will be high up, if Samsung B-die, it can go quite a lot lower.
> Major performance hit from tRRDS/tRRDL/tFAW
> tFAW should ALWAYS be 4x tRRDS... So, set it to 28 first, if stable then try (tRRDS/tRRDL/tFAW) 6/10/24, 6/8/24, 4/8/16, 4/6/16, 4/4/16 in that order up to last which was fine. (4/4/16 is lowest possible)
> then tWTRS/tWTRL...Try 4/12, then 3/12, then 3/8, then if you able you may attempt to go for 2/8 2/7, but success there is quite unlikely one.
> tWR... i don't remeber rules, but iirc it should either be 16 ot 12... going to 8 should be teoretically possible, lower is dangerous to set.
> tRTP must be set before tRFC, as it is basically counts as multiplier. Go as low as you can (usually it is set to 8)
> tRFC... With Micron you can attempt to do 250-280 ns, maybe lower is possible. With Samsung B-die, 120-140 ns are likely to be at. You only need to set tRFC, as tRFC2 and tRFC could be remained at auto.
> Calculation of tRFC for you is Time(ns)*Memory frequency/(2*1000) so for you it is 280*4067/2000=569.38), then increase it up to closest number divisible by tRTP you set. So in this case for tRTP=8 it will be like that: 569.38=71.1725 ===> 72*8=576.
> tRDRD_SCL/tWRWR_SCL = go as low as you can
> tRDWR/tWRRD = go as low as you can.
> tRDRDSD and tWRWRSD don't apply for your setup, as you have 4x1R sticks.
> tRDRDDD and tWRWRDD = go as low as you can
> tCKE = go as low as you can (can be straight set to 1)
> 
> Then you can play with resistances a bit. RttPark is most useful to set to "lower" value (as it is measured in RZQ/X, where RZQ is 240 Ohm resistor).


Thank you for this guidance. This memory Micron, not b-die Samsung.


----------



## Robby37

found something 


Veii said:


> When it comes to minimum required voltage for 3800C14-14-14, it depends on:
> 
> The PCB quality (layers = fixed amount of leakage & heat = variable amount of leakage)
> A general rule of understanding how tRP 14 behaves by frequency
> And the RTT's.
> 
> RTT_NOM should be increased if you increase voltage (lower divider, stronger value)
> RTT_WR is dynamic ODT and a whole layer ontop of the current ODT & powerdown signal path (dynamic)
> RTT_PARK depends on the PCB quality and will increase heat if you increase it. Requirements depend on the IMC's FW and preconfigured RZQ values (more to it later)
> 
> 3800 MT/s can need between 1.5-1.6v , usually it's 1.5v and above
> But 1.5 flat is only at 731 (DR) or 005 (SR) ~ where after 1.51-1.52 you start to see instability , till you use 705 then 1.54v is your instability range
> Higher voltage either doesn't work because of heat or start to give you fully dropped channels at 1.54-1.55. If this happens, 1..56+ would kill the PCB.
> It depends
> 
> Take a look at this current set
> View attachment 2489274
> 
> RTT_PARK got lowered to /7, RTT_NOM got increased to /5 . Initially 6/3/6 where running @ 1.66v
> Now it's 1.65v, as NOM seems to just cover the voltage requirements of the one step "lower" PARK
> 
> Also take a look at:
> 
> 
> Spoiler: this old GDM comparison
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> It needed 1.6v to finally reach stable 14-14-14
> Not because the set would require it (i mean also), but because RTT_PARK was weaker
> (706 instead of 005 ~ didn't want to run 1.55+ on my A0's at 005 or even 705. I like this memory ~ but VDIMM requirements increased with weaker PARK)
> Soo more VDIMM was needed ~ but it absolutely doesn't mean, that it causes more heat. Voltage on it's own doesn't translate to heat.
> It's the Amperage that arrives ~ depending on resistance and impedances throughout the chain.
> Except that timings love more voltage, soo it can be beneficial to take this route instead of the easier 005 / 731 route
> ============================================================
> But there is a caveat, that bothers me the last 3 days (comparing my current set above)
> IMC FW changed, and some scaling changed. 200% sure on that a this point
> Compare these two results:
> 
> 
> 
> 
> 
> 
> 
> 
> Why does one fail but one passes at "perfect" tFAW math ?
> Because it's not how it works anymore. AMD changed something with AGESA 1.2.0.1 and 1.2.0.2
> RZQ behaviour is different ~again~ !
> And generally tFAW behaviour is different
> 
> 
> Spoiler: My initial set which was rock stable
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> At this point, isn't stable at all. Not even remotely
> VDDG needed a remake with voltages, and RTT's where messed up
> This tFAW obscureness above, was randomly found ~ after beating my head against a wall of #2's for the last days
> AMD changed something !
> 
> Is 2* tFAW recommendable ?
> Unsure, it's performance is still here-and-there funky
> But 4* tFAW at least on my set doesn't work at all. Some new implemented BURST read option , breaks stability fully
> It likely is this option that @KedarWolf saw:
> 
> 
> Spoiler
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 900-1020-1100 + tad higher SOC
> is currently the new norm for me
> Y-Cruncher was rebooting on "too low" SOC & crashing on "too high IOD" (was 1120mV before)
> 
> Hope this helps someone who struggles with stability on 1.2.0.1+ AGESA
> RZQ is higher, it doesn't behave like 240ohm. Maybe DQS is finally at 480ohm instead of 240 , like "hidden" half a year ago in their bios changes
> Anywho:
> - lower IOD, and weaker RTT's are required for 1.2.0.1 / 1.2.0.2 to sustain stability
> 
> KedarWolf's set was an experiment
> Testing of tRP. The opposite on "instead of lowering it to gain room in order to lower tRC"
> Increasing it, as it's one of the timings like tRC, which has to elapse and is not breakable
> tRAS was tried to be pushed at the lowest possible value
> I think it was
> tRCDavg + tCL + (tBL - (tCL-1)) - 1
> 14+14+ (-6) = 22 (8-13-1)
> tBL used as 8 here instead of 4
> 
> The formula above tho was found by 1usmus 😇
> Overall many little experiments happen along Matisse lifespan, when we where 1900 FCLK locked and bored
> 
> 
> Spoiler: This is what i can find from the old data:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Many many little shenanigans and snippets ~ where most of the things are deprecated and have changed. But just so you know behind the scenes
> Want to remind everyone who judges on tRFC mini - that it took a loong time to build, it's not that random
> 
> I can barely remember, but i think the goal for KedarWolf's set was to either use minimum tRAS or match tRC, just in order to match some abstract tRCD_WR ruleset
> Soo tRP was one of the values which can scale down, but also can scale up to lower voltage requirements - as more time to (p)recharge will exist.
> A voltage leakage experiment, with from todays perspective, looks a bit off on tRC. Just what works well, works well
> 
> Please write or correct it next time with linebreaks, that's about all


----------



## The_King

Robby37 said:


> From the formulas I found you should run scls of 4 since half your tcrd is 10 if rounded up and you want to be below when scl x twrrd but as large as you can . When you violate that rule like scl 5 you regress or error and when you are smaller than te window you leave some performance on the table AFAIK. worth a shot tho . With the 4200 obv not the 4800


I only tested SCL 4 in Aida but when I test Y-cruncher it was 2.
WIll redo a test with SCLs at 4.


----------



## Asutz

Hello,

Need a little help, mostly stable but when benching with WoW often the game crashes, error #132 which is mostly a memory instability.
Vdimm around 1.53v, another weird thing on the asus b550f gaming, vsoc switching between 1.087v and 1.093 and every Bios setting for a fixed vsoc dont help. 4x8gb config

edit:
looks like higher trtp helped @14 now but what other changes do the trick to tighten it to like 6 /8 ?


----------



## ManniX-ITA

Asutz said:


> Vdimm around 1.53v, another weird thing on the asus b550f gaming, vsoc switching between 1.087v and 1.093 and every Bios setting for a fixed vsoc dont help.


You need to find a way to set VSOC at least 1.12V.
Otherwise you can try setting VDDG IOD at 1020mV.


----------



## xpulse

xpulse said:


> Thank you for this guidance. This memory Micron, not b-die Samsung.


1st night of overclocking 4x16Gn Crucial on Micron.
tRFC so high... can't move any lower. but from original 3600 to 4067 not so bad


----------



## misashima92

Just installed new Trident Z Neo's today([email protected])and checked my latency and it was sitting at around 70ns.
Before i used an older cl16 kit with worse timings and it was at around 65-69ns if i remember correctly.
Both just used their XMP profiles, now i'm just wondering why i get higher latency on a kit that should technically lower the latency?

I've managed to bring the latency down to 67, which is still quite high with these settings:


https://cdn.discordapp.com/attachments/1022526530489958492/1022526697964310628/IMG_0338.jpg


I used DRAM Calc, not sure if i should try a different program.

I've used the rec./alt settings.

Since i'm fairly new to this and since this was my first time even doing this manually, could i do anything else to lower the latency, or is it simply because i'm using an older cpu(3900x)?

I'd really appreciate some insight here


----------



## Frosted racquet

Most of it is due to older Zen 2 CPU and the rest is due to background processes probably. Try testing in Safe Mode and compare current settings.

Later, try WTRL 8, WR 10 and lower tRFC a bit (maybe 260). Both SCL's could go to 2.

RRDS/L and tFAW are lower than it's generally recommended, people usually run 4-4-16 for RRDS-L-tFAW and not 3-7-12

Above settings shouldn't affect latency too much, so temper your expectations.


----------



## misashima92

Frosted racquet said:


> Most of it is due to older Zen 2 CPU and the rest is due to background processes probably. Try testing in Safe Mode and compare current settings.
> 
> Later, try WTRL 8, WR 10 and lower tRFC a bit (maybe 260). Both SCL's could go to 2.
> 
> RRDS/L and tFAW are lower than it's generally recommended, people usually run 4-4-16 for RRDS-L-tFAW and not 3-7-12
> 
> Above settings shouldn't affect latency too much, so temper your expectations.


are my settings otherwise safe?
i was just reading that dram calc can put out some crazy values that might not be safe to use, so i just wanna make sure.
could you do me a favor and put the values next to the ones i need to change so i can do that later on when i'm back on my pc, would greatly appreciate that


----------



## Frosted racquet

The only "mistake" I see in the settings is the relation between tRP+tRAS=tRC

In your current settings tRP+tRAS=39 while tRC is set to 42, so the CPU memory controller will ignore the lower tRAS setting and "autocorrect it" to the higher tRC 42 (i.e tRAS becomes 29)

That, and the mentioned 4-4-16 for RRDS-L-tFAW that is suspect.

Nothing I see can result in data loss or damage.

Post a Zentimings screenshot, I'm not sure which CAD_BUS or RTT settings are active from that screenshot.


----------



## misashima92

Frosted racquet said:


> The only "mistake" I see in the settings is the relation between tRP+tRAS=tRC
> 
> In your current settings tRP+tRAS=39 while tRC is set to 42, so the CPU memory controller will ignore the lower tRAS setting and "autocorrect it" to the higher tRC 42 (i.e tRAS becomes 29)
> 
> That, and the mentioned 4-4-16 for RRDS-L-tFAW that is suspect.
> 
> Nothing I see can result in data loss or damage.
> 
> Post a Zentimings screenshot, I'm not sure which CAD_BUS or RTT settings are active from that screenshot.


I've edited my post with the screenshot, the active RTT is the middle one, second for CAD_BUS, also the middle one for voltages

So yeah, if you could put the new values next to the "old"/wrong values via paint or whatever, that would probl. be easier for me to understand, and i would hop straight into bios and change said values


----------



## Frosted racquet

Here you go. 1T command rate (Cmd2t in zentimings) with GDM off is very difficult to stabilize. Test with GDM off and 2T command rate first, and only if you're ambitious try GDM off and 1T after.


----------



## misashima92

Frosted racquet said:


> Here you go. 1T command rate (Cmd2t in zentimings) with GDM off is very difficult to stabilize. Test with GDM off and 2T command rate first, and only if you're ambitious try GDM off and 1T after.
> 
> View attachment 2573072


yeah i was actually wondering if i should leave GDM enabled, since a G.skill Rep told me it's on by default with said timings.
I'll give this a shot, really appreciate it!

Edit: I've made all the changes now, just wondering if i should change anything voltage wise? 
it's currently running at 1.45 and vsoc, i left at auto.


----------



## Frosted racquet

It's possible you'll be stable at 1.45v but my guess is you'll need to increase it. Test with TestMem5 1usmusv3 profile for 25 cycles minimum, in Safe Mode


----------



## misashima92

Frosted racquet said:


> It's possible you'll be stable at 1.45v but my guess is you'll need to increase it. Test with TestMem5 1usmusv3 profile for 25 cycles minimum, in Safe Mode


i've instantly started with errors, in cycle 1, more than a 100 errors.


----------



## dimkatsv

Frosted racquet said:


> Here you go. 1T command rate (Cmd2t in zentimings) with GDM off is very difficult to stabilize. Test with GDM off and 2T command rate first, and only if you're ambitious try GDM off and 1T after.
> 
> View attachment 2573072


tRDRD_SCL/tWRWR_SCL not always must be at minimum value. For me setting it from 3 to 2 actually reduces performance


----------



## Frosted racquet

misashima92 said:


> i've instantly started with errors, in cycle 1, more than a 100 errors.


1T command rate or 2T GDM off? I've used 1.5V to stabilize similar settings, although I have a different B-die kit.
Take a look at this sheet for error info tRFC mini



dimkatsv said:


> For me setting it from 3 to 2 actually reduces performance


Which test shows performance regression?


----------



## dimkatsv

Frosted racquet said:


> Which test shows performance regression?



Well, tbh it was AIDA bandwith test... Around -300-400 MB/S or so... I mean, i could've been bamboozled by it, so.
UPD: Tested different values with about 5 tests on each in safe mode
SCLs at 2 = most consistent result. Latency is 56.0 consistently
SCLs at 3 = lowest average latency (0.1ns lower... For 2 it is consistent 56.0, for 3 it is often 55.9)
SCLs at 4 = First test went up to 55.5 Gb/s read speed, small latency hit
SCLs at 5 (auto) = First test went up to 55.7** (was typo of 57.5, sorry) GB/s, 0.2-0.3 ns latency hit
Problem with bandwith test, is that it was consistent, but in wrong way. First test gave highest results, then they went down up to some threshold, either 55.1 read / 54.1 copy, or to 54.8 read and 53.8 copy with SCL at 2 or 3...


----------



## Frosted racquet

Thanks for testing it. I checked my results in Safe Mode as well, and there doesn't seem to be a noticeable difference but there is a small pattern.

Latency seems to be most consistent with SCL 2 and 4, but as you've noted SCL 3 achieved best latency in a single run despite more deviation.

SCL 4 is best for Read performance by looking at averages, although comparing the best results from each there's 150MB/s difference between SCL 2 and 4.

SCL 3 has the best Copy performance by looking at averages, but ~100MB/s difference between SCL 2 and 3.


Spoiler



SCL 2, 3 consecutive runs (1,2,3 from left to right)





















SCL 3




















SCL 4




















Averages








Zentimings


----------



## misashima92

Frosted racquet said:


> 1T command rate or 2T GDM off? I've used 1.5V to stabilize similar settings, although I have a different B-die kit.
> Take a look at this sheet for error info tRFC mini
> 
> 
> Which test shows performance regression?


i've used 2T with GDM off(I've just put everything back to auto and only enabled the xmp, so you can see the "base" values used in the xmp profile. (i would still try to avoid using these since it gave me super latency 70 and above for some weird reason)

also this was in the log:
======== TestMem5 Log File =========
Customize: Default @serj
Start testing at 18:55, 608Mb x24
Error in test #4 through 19 sec.


========= TestMem5 Log File =========
Customize: Default @1usmus_v3
Start testing at 18:55, 624Mb x24
Error in test #6 through 13 sec.
Error in test #2 through 36 sec.
Error in test #10 through 53 sec.
Error in test #5 through 1m 3s.
Error in test #1 through 1m 4s.

i only ran it for a minute or so because it was already at 100 errors.

this is the sheet with only the xmp profile, the only thing i've disabled is power down mode, everything else is on auto.


----------



## Frosted racquet

misashima92 said:


> i've used 2T with GDM off(I've just put everything back to auto and only enabled the xmp, so you can see the "base" values used in the xmp profile. (i would still try to avoid using these since it gave me super latency 70 and above for some weird reason)


Can you repeat the test with only XMP enabled?


----------



## byDenoso

Frosted racquet said:


> Here you go. 1T command rate (Cmd2t in zentimings) with GDM off is very difficult to stabilize. Test with GDM off and 2T command rate first, and only if you're ambitious try GDM off and 1T after.
> 
> View attachment 2573072


Increase ClkDrvStr to at least 40ohm and try GDM Off.


----------



## Robby37

xpulse said:


> 1st night of overclocking 4x16Gn Crucial on Micron.
> tRFC so high... can't move any lower. but from original 3600 to 4067 not so bad
> 
> View attachment 2573069
> 
> View attachment 2573070


Try iod 1.06 cldo .9 and ccd at .95. You are really high and they don't like being the same.


----------



## Robby37

Asutz said:


> Hello,
> 
> Need a little help, mostly stable but when benching with WoW often the game crashes, error #132 which is mostly a memory instability.
> Vdimm around 1.53v, another weird thing on the asus b550f gaming, vsoc switching between 1.087v and 1.093 and every Bios setting for a fixed vsoc dont help. 4x8gb config
> 
> edit:
> looks like higher trtp helped @14 now but what other changes do the trick to tighten it to like 6 /8 ?
> 
> View attachment 2573059


Your twr is very high. Ghave you tried lower?


----------



## Robby37

misashima92 said:


> Just installed new Trident Z Neo's today([email protected])and checked my latency and it was sitting at around 70ns.
> Before i used an older cl16 kit with worse timings and it was at around 65-69ns if i remember correctly.
> Both just used their XMP profiles, now i'm just wondering why i get higher latency on a kit that should technically lower the latency?
> 
> I've managed to bring the latency down to 67, which is still quite high with these settings:
> 
> 
> https://cdn.discordapp.com/attachments/1022526530489958492/1022526697964310628/IMG_0338.jpg
> 
> 
> I used DRAM Calc, not sure if i should try a different program.
> 
> I've used the rec./alt settings.
> 
> Since i'm fairly new to this and since this was my first time even doing this manually, could i do anything else to lower the latency, or is it simply because i'm using an older cpu(3900x)?
> 
> I'd really appreciate some insight here


With scls 3 or 4 twrrd should be 3 with your primaries. You can try reducing trdwr to 7 but try just 3 first or alternatively you can make scls 5 with 1. Trfc can be 252 if my math serves and 2 and 3 188 and 115 .also tfaw should be 16 . See if those changes get you into mid 50s for latency. I get 55 at 3666 with 64gb so looser primaries with 56xxx mbs so you should be able do better than that. I think your losing performance cause of timing mismatches


----------



## Frosted racquet

Robby37 said:


> With scls 3 or 4 twrrd should be 3 with your primaries.


What's the formula for that?


Robby37 said:


> See if those changes get you into mid 50s for latency. I get 55 at 3666 with 64gb so looser primaries with 56xxx mbs so you should be able do better than that. I think your losing performance cause of timing mismatches


Are you on Zen 2 as well?


----------



## xpulse

Hi,
Could you please help me lower memory latency with the new CPU?
5950x and Crucial BL16G36C16U4B.M8FB1 4x16 Single Rank = 64GB. 3600Hz Default timings 16-18-18-18-36.

Changed speed to 3933, with some minor changes to timings but latency is ~71ns.


----------



## kubast2_2

Still working on my mems running Dual Channel 4 sticks(single rank).









tRDRDSCL/tWRWRSC 1 was the default auto setting.
tREFI isn't available in my bios nor RyzenMasters.
Anything above 3200mhz(SoC set to auto, 1.1V for 3.2ghz) instantly crashes the memtest with timings equal to XMP in ns and with +1/+2 clocks over XMP(L at ns).
Iirc I got to 1800mhz FCLK at 3000mhz XMP(1.05V) with 1.15V SoC.

Stress-testing mainly with 7-zip(finds issues much faster than memtest86+)+audio playback;
Tried tWTRL 8, but I had to revert to 12[audio glitched out, system freezed for awhile];








my 24/7 was the 16/17/17/38/74/Rest: Auto; ns parity with XMP


----------



## dimkatsv

kubast2_2 said:


> tRDRDSCL/tWRWRSC 1 was the default auto setting.


And it booted wiith manual 1 as well? If yes then i am impressed.
Because auto is 1 after BIOS reset... technically. But after first boot auto magically changes this 1 to something different. For me it was 5.


----------



## kubast2_2

dimkatsv said:


> And it booted wiith manual 1 as well? If yes then i am impressed.
> Because auto is 1 after BIOS reset... technically. But after first boot auto magically changes this 1 to something different. For me it was 5.


I had to do a BIOS reset, because I couldn't run tRas 25;
The system would POST(gpu firmware posted(fans stop spinning once memory/gpu posts), but had no video out).
My system on BIOS reset goes through 3 restarts before posting, then it restarts while in a bootloader, and then it is ready to set XMP.
I set XMP, booted to the system, adjusted the timings+frequency back to 3200mhz;
I believe it's still set to 1, and it still auto-sets to 1.


----------



## dimkatsv

kubast2_2 said:


> I believe it's still set to 1, and it still auto-sets to 1.


Ah, you mistook tRDRD_SC / tWRWR_SC with tRDRD_SCL / tWRWR_SCL, by first timing you wrote, i thought you meant SCLs, but they were SC
One letter, but HUGE difference
tRDRD/tWRWR~
~_SC = Same side - different bank. Used for fast consecutive read/write to speed up process (As well as tRRD_S/L with tFAW, but these are limiters basically) = Usually set to 1 even by auto
~_SCL = Same side - same bank. Needs to be limited because repetitive access to same bank have own issues (mostly risk of data corruption) = Usually set on raw first boot to 1, but this is fakeout and after first training it goes up... Usually up to 5/5. Can go to as low as 2/2, but 1/1? Highly unlikely
~_SD = Same DIMM. Used in configurations of multiple RANKS per DIMM per channel to interpolate ranks (side of one DIMM).
~_DD = Different DIMM. Used in configurations of multiple DIMMS per channel to interleave operation between DIMMs for higher bandwith because of consecutive access limitations.
So, SC and SCL work in every config. SD works when you use 2xDR, 4xDR and more sticks with 2 ranks each... While DD works in setups with 4xSR 4xDR and more sticks per channel configs


----------



## kubast2_2

dimkatsv said:


> Ah, you mistook tRDRD_SC / tWRWR_SC with tRDRD_SCL / tWRWR_SCL, by first timing you wrote, i thought you meant SCLs, but they were SC
> One letter, but HUGE difference
> tRDRD/tWRWR~
> ~_SC = Same side - different bank. Used for fast consecutive read/write to speed up process (As well as tRRD_S/L with tFAW, but these are limiters basically) = Usually set to 1 even by auto
> ~_SCL = Same side - same bank. Needs to be limited because repetitive access to same bank have own issues (mostly risk of data corruption) = Usually set on raw first boot to 1, but this is fakeout and after first training it goes up... Usually up to 5/5. Can go to as low as 2/2, but 1/1? Highly unlikely
> ~_SD = Same DIMM. Used in configurations of multiple DIMMS per channel to interleave operation between DIMMs for higher bandwith because of consecutive access limitations.
> ~_DD = Different DIMM. Used in configurations of multiple RANKS per DIMM per channel to interpolate ranks (side of one DIMM).
> So, SC and SCL work in every config. SD works when you use 2xDR, 4xDR and more sticks with 2 ranks each... While DD works in setups with 4xSR 4xDR and more sticks per channel configs


Thanks I read ddr4 OC guide from github. But it seems like I missunderstood _SD _DD(I misread that the _SD timing is used with Dual Rank memories) and didn't register that _SCL and _SC where both present in my bios(yet I modified both! iirc stock timings were: Read_SCL 5 Write_SCL 8).
Yeah I noticed that as well when going into bios, I mistook that timing for another one;
I had unstable tWR+tRTP set, didn't show on 7-zip loop, the timings failed after just 2 minutes in memtest86+.
Gonna play around with timings more and run memtest overnight, if the timings fail I am just going to revert changes one by one until I find out what is stable and what isn't;
Tomorrow I might mess around with decoupled Infinity Fabric clock, and it's voltage(bring it up to 1.06V/SoC-40mV), pretty sure that either a) these mems get too hot to run anything above 3200mhz, or it's the infinity fabric clock that's unstable.
Last time I did decoupled infinity fabric it was with an 1.15V SoC+(auto infinity fabric voltage) it went up to around 1.8 ghz.
And if I recall correctly my 3500x simply can't do anything above 1.6Ghz at auto/stock infinity fabric voltage.


----------



## dimkatsv

kubast2_2 said:


> _SD _DD(I misread that the _SD timing is used with Dual Rank memories)


Sorry, i also mistyped explanations text above for each other. Swapped _SD _DD, SD is for 2R DIMMs and DD is for multiple DIMMS... 
Now it is fixed


----------



## Nelfhunt

xpulse said:


> Hi,
> Could you please help me lower memory latency with the new CPU?
> 5950x and Crucial BL16G36C16U4B.M8FB1 4x16 Single Rank = 64GB. 3600Hz Default timings 16-18-18-18-36.
> 
> Changed speed to 3933, with some minor changes to timings but latency is ~71ns.
> 
> View attachment 2573164
> 
> View attachment 2573165


Mmmm 4x 16GB @1966 FCLK and cmd 1t, just a wild guess - you are not stable.


----------



## xpulse

Nelfhunt said:


> Mmmm 4x 16GB @1966 FCLK and cmd 1t, just a wild guess - you are not stable.


It is stable mem5 test passed 3 times (1usmus_v3), but I moved down to 3866 because latency is better in Aida64.


----------



## blodflekk

xpulse said:


> Hi,
> Could you please help me lower memory latency with the new CPU?
> 5950x and Crucial BL16G36C16U4B.M8FB1 4x16 Single Rank = 64GB. 3600Hz Default timings 16-18-18-18-36.
> 
> Changed speed to 3933, with some minor changes to timings but latency is ~71ns.
> 
> View attachment 2573164
> 
> View attachment 2573165


Trc is too high and trfc is even higher than jedec spec. Reduce them and latency will drop. Trc = tras+trp


----------



## Anhphe93

you are suffering a performance penalty. SCL too low is not good, your TRFC is high try lowering it as low as possible.


















xpulse said:


> Hi,
> Could you please help me lower memory latency with the new CPU?
> 5950x and Crucial BL16G36C16U4B.M8FB1 4x16 Single Rank = 64GB. 3600Hz Default timings 16-18-18-18-36.
> 
> Changed speed to 3933, with some minor changes to timings but latency is ~71ns.
> 
> View attachment 2573164
> 
> View attachment 2573165


----------



## xpulse

blodflekk said:


> Trc is too high and trfc is even higher than jedec spec. Reduce them and latency will drop. Trc = tras+trp


The lowest TRC and TRFC I can boot into windows.


----------



## aemondis

Gskill 16-16-16-36 B-die, still not refined fully, haven't touched the tertiaries or primaries (I usually do these last). Starting all my tunings from scratch on the 5900x (5950x IMC was faulty, it would randomly go offline at both load or at idle, even partway during boot or idle at the BIOS!). Never got anywhere near this far on the 5950x, so quite happy with the results currently, but wondering where to go from here? Most timings seem to offer minimal benefit, but my goal is really bringing down the latency - since it's more noticeable in general use.

WR & RTP seem at the limit, since any tighter values seem to cause errors after ~1.5hrs of testing usually (probably heat soak). RTP = 7 is unbootable, WR will go to 14 but not sure if that makes any sense if RTP = 8?
RFC is at a safe limit too since it is unbootable at 270, but at 280 it is stable even in heatwave conditions.
1T is doable, but incredibly tough to get it going (lots of BIOS resets).
This board doesn't like odd CWL either (unbootable).










Right now VDIMM is at 1.435v and the SOC/VDDP/VDDG CCD/VDDG IOD are at 1.1/0.95/0.95/1.0.
Current settings have been rock solid at 3733, with 3 days each of solid TestMem & Karhu, prime95, OCCT etc. (I like going thorough on my tests!)

I have yet to find any way to boot at 3800 though, no combination of any settings or voltages lets this CPU boot at 3800 (even async, it seems FCLK = 1900 is just impossible?), but oddly enough - I can boot at 3866 all the way up to 3966, albeit with streams of WHEA. 4000 is unbootable.

Current AIDA scores (averaged out over 5 runs, due to random background activity):
READ: 57833
WRITE: 57098
COPY: 53748
LATENCY: 58.8

Windows 11 scheduler due to work requirements & WSL (meaning those latency figures are also within a VM technically, since WSL actually makes the host OS run as a virtual machine)... not sure how much more room there is in these numbers to improve?


----------



## Nelfhunt

xpulse said:


> It is stable mem5 test passed 3 times (1usmus_v3), but I moved down to 3866 because latency is better in Aida64.


By the 3 times you mean 3 cycles? If so, it´s nothing, it´s like 15 minutes or so, it really says nothing. Edit the source to at least 20, better 25 cycles. Then you will know better about the stability.


----------



## 97pedro

This is what I get from my 5950x with SMT disabled.

What do you think?


----------



## Robby37

Frosted racquet said:


> What's the formula for that?
> 
> Are you on Zen 2 as well?


Ia on zen 3 on one rog and zen 2 other . Scl x twrrd annot exceed tcdrd .ideally you want it close . Twrdr should be half tcdrd rounded up if odd as a start for sigle rank 2

page 418 of this thread has great info cause scl is based on leftover latency from twrrd and your trcdrd . 
Their are multiple rules to abide buy and they have proven to work so far on all my setups fro hynix , and 2 b die setups


----------



## Robby37

aemondis said:


> Gskill 16-16-16-36 B-die, still not refined fully, haven't touched the tertiaries or primaries (I usually do these last). Starting all my tunings from scratch on the 5900x (5950x IMC was faulty, it would randomly go offline at both load or at idle, even partway during boot or idle at the BIOS!). Never got anywhere near this far on the 5950x, so quite happy with the results currently, but wondering where to go from here? Most timings seem to offer minimal benefit, but my goal is really bringing down the latency - since it's more noticeable in general use.
> 
> WR & RTP seem at the limit, since any tighter values seem to cause errors after ~1.5hrs of testing usually (probably heat soak). RTP = 7 is unbootable, WR will go to 14 but not sure if that makes any sense if RTP = 8?
> RFC is at a safe limit too since it is unbootable at 270, but at 280 it is stable even in heatwave conditions.
> 1T is doable, but incredibly tough to get it going (lots of BIOS resets).
> This board doesn't like odd CWL either (unbootable).
> 
> View attachment 2573237
> 
> 
> Right now VDIMM is at 1.435v and the SOC/VDDP/VDDG CCD/VDDG IOD are at 1.1/0.95/0.95/1.0.
> Current settings have been rock solid at 3733, with 3 days each of solid TestMem & Karhu, prime95, OCCT etc. (I like going thorough on my tests!)
> 
> I have yet to find any way to boot at 3800 though, no combination of any settings or voltages lets this CPU boot at 3800 (even async, it seems FCLK = 1900 is just impossible?), but oddly enough - I can boot at 3866 all the way up to 3966, albeit with streams of WHEA. 4000 is unbootable.
> 
> Current AIDA scores (averaged out over 5 runs, due to random background activity):
> READ: 57833
> WRITE: 57098
> COPY: 53748
> LATENCY: 58.8
> 
> Windows 11 scheduler due to work requirements & WSL (meaning those latency figures are also within a VM technically, since WSL actually makes the host OS run as a virtual machine)... not sure how much more room there is in these numbers to improve?


tcwl should be 16 to match tcl. and use the trfc mini calc to get good trfc values and you should have no prob iirc would be like 240 or 288 for your primaries . I'm being lazy right now so don't take that as the values for your trc and tcl and trtp
also rtrp should be lowest half your tcl so 8 it is right now 7 would need 14 timings which with twrrd of 7 you have chance of running cl14 since your running 1 negative and tech have a timings mismatch . So I would be shocked if your long term stable right now .


----------



## Frosted racquet

Robby37 said:


> Ia on zen 3 on one rog and zen 2 other . Scl x twrrd annot exceed tcdrd .ideally you want it close . Twrdr should be half tcdrd rounded up if odd as a start for sigle rank 2
> 
> page 418 of this thread has great info cause scl is based on leftover latency from twrrd and your trcdrd .
> Their are multiple rules to abide buy and they have proven to work so far on all my setups fro hynix , and 2 b die setups


Basically for my setup (attached) you'd suggest running SCL 4's and tWRRD 3? Anything else you'd change on 2x16GB DR?


----------



## Valka814

What do you guys recommend to try first?


----------



## SneakySloth

Valka814 said:


> What do you guys recommend to try first?
> View attachment 2573291


Maybe a slight increase in vdimm to 1.49?


----------



## The_King

SneakySloth said:


> Maybe a slight increase in vdimm to 1.49?


If that does not work try 
TRAS 42 and RC 60.
RCD + RCD + 6 for Micron Rev E


----------



## dimkatsv

The_King said:


> TRAS 42 and RC 60.


You do know that if you have good tRC setup, tRAS literally does nothing? Like you can set it down to 21 (lowest possible and it will be fine.
But tRC is really important on other hand


----------



## Nd4spdvn

dimkatsv said:


> You do know that if you have good tRC setup, tRAS literally does nothing? Like you can set it down to 21 (lowest possible and it will be fine.
> But tRC is really important on other hand


Indeed, and for that reason I run this:


----------



## dimkatsv

Nd4spdvn said:


> Indeed, and for that reason I run this:


Now that is cheesy)
15+21=36... Definitely not that different from tRC=37 ))). Dang, wish i had 32GB 2x16 S8B kit... But i am kind of forced to deal with H8DJR instead, because buying B-die on top will be wasting money.

In all Hynix and Micron config this have more importance...Maybe Nanya as well, but i hadn't saw these ones much. Like here for me









Also.... 1.54V? Is it fine for daily?


----------



## Nd4spdvn

dimkatsv said:


> 15+21=36... Definitely not that different from tRC=37 ))).


 I did play a bit with 36, but seemed kind of flaky to me. I deliberately went away from tRC= tRAS + tRP by choosing to let the IMC ignore tRAS and just use tRC and tRTP, but with tRTP at 5 it is all about tRC in fact. Works a treat daily at 1.54V set 1.55V get. Cold boots, soft boots, gaming loads mostly. Open bench, no fan on the dimms.


----------



## The_King

This is another Micron Kit I have Crucial Ballistix 3600 CL 16-18-18-38-58 (C9BLM) 16GB DR Micron Rev. E
Running ar 4133 CL16-19-19-44-63 1:1:1. Left CCD on Auto it will only boot with 1.2 CCD. This passes at least 5 cycles of TM5 1usmus.


----------



## HEYY0M1KEY

First post. I am working on GDM off 2T and am struggling with making Proc, Rtt, and CAD Bus changes effectively besides what I have so far. I have a spreadsheet with a lot of combinations I have tried, but I don't have a method for adjusting Proc, Rtt, or Cad Bus. Once I figure 2T out I think I am going to try working on 1T, which I can post currently but crashes on any load. I have read through hundreds of pages learning the past month or so.

Thanks to Veii for guides on the coolenjoy website. It along with the TRFC mini spreadsheet and other guides has helped a lot.











쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네


출처 Veii 님https://www.overclock.net/forum/28385690-post3279.htmlhttps://www.overclock.net/forum/28385



coolenjoy.net







My daily is the following, I just haven't retested since updating bios. This profile does have a 26/28 tPHLYRDL mismatch, which I haven't figured out.











This is my first stable run with secondaries and tertiaries on Auto. CLKDRV at 60 was the main change that allowed it to be stable along with 6/3/3 on Rtt's. Going down to 40 or lower I have not figured out.









Next I tried to see if I could set the secondaries and tertiaries tighter. The 3 errors occurred during the 3rd cycle.










Next I tried flat 14's









Lastly a spreadsheet of combinations I tried.


----------



## Tarts5

Hi guys, can you give me a few pointers or steps where should I look into next with memory overclocking? 
I have a 5600x(B2 stepping) with a B550 motherboard with Patriot Viper Steel 16GB (2 x 8GB) 4000MHz CL16 Low-Latency RAM (Samsung B-die). 
Im running them at the XMP profile for 4000mhz with 1:1:1 ratio. Done all kinds of tests with the time limit of "overnight" and everything is stable so far. If I want to tweak anything further, where should I go from here? My 1st goal would be to squeeze out more FPS from games and the 2nd goal is to take maximum from my system, while keeping it stable.
Im not expecting a big guide, just a few pointers what should I research next. Like, should I try to increase the mhz, but then what do I do about the timings? Or/And at what point should I increase voltages etc? Like, whats the order in which I should move forward.


----------



## Taraquin

The_King said:


> I notice that above 4066 VDDP, IOD and SOC becomes very sensitive. I also notice with to too high CCD I was losing latency in AIDA64. Sadly I can't adjust VDD18 on my B450M Mortar MAX
> 
> This is my 5600 non X with the Same RAM but 3800 FCLK 1900 when I ran R23 with 4200 FCLK 2100 score was 11400. Didn't even bother screenshotting that!
> 
> 
> Spoiler: R23 11824
> 
> 
> 
> 
> View attachment 2572954
> 
> 
> 
> I managed to break 12K in R23 but that was with my Patriot Viper Dual rank setup.( 4 X SR)
> 
> 
> Spoiler: R23 12008
> 
> 
> 
> 
> View attachment 2572953
> 
> 
> 
> 
> Edit
> @Taraquin I just beat my Patriot Viper setup now using this RAM. Micron FTW
> (Looks like this Micron RAM is easier on the IMC with my Patriot Viper Samsung B-die I could only do -23 all core with this Micron B-die I can do -27 all core.)
> 
> 
> Spoiler: R23 12108
> 
> 
> 
> 
> View attachment 2572982


B-die once tuned is tough for IMC die due to tight RCDRD, RC and RFC it seems. I didn't know it could affect CO, but it sort of makes sense, maybe not from IMC itself, but probably temp/consumption and powerdistribution.


----------



## Taraquin

The_King said:


> This is another Micron Kit I have Crucial Ballistix 3600 CL 16-18-18-38-58 (C9BLM) 16GB DR Micron Rev. E
> Running ar 4133 CL16-19-19-44-63 1:1:1. Left CCD on Auto it will only boot with 1.2 CCD. This passes at least 5 cycles of TM5 1usmus.
> View attachment 2573334
> View attachment 2573335


Cool that you experiment like this! Awesome getting rev E running RCDRD 19 at 4133. My kits can max run 3733 at RCDRD 19. I would not run that high CCD daily however!


----------



## Dziarson

B-die F4-3800cl14 Anta extreme 2 cycle, its look 2000MHz 1:1:1 stable


----------



## YoichiG

I really went in to black hole about CAD BUS'es always nightmare.
Tells me increase rttnom and decrease vdimm _does_ now 12-3-8 errors out.
Tells me weaken rttnom and increase vdimm _does_ now buncha 13 errors with 5 and 12
Isn't there is RZQ/0.5?
Or what I shoulda try something else...
(addrBus setup doesnt posts if its not 55 or 56, rest works on 0 too but still same CAD BUS nightmares)


----------



## Dziarson

@YoichiG try all auto i was have problem now from soc voltage to ckedrvstr i have auto and all working super


----------



## Bix

YoichiG said:


> I really went in to black hole about CAD BUS'es always nightmare.
> Tells me increase rttnom and decrease vdimm _does_ now 12-3-8 errors out.
> Tells me weaken rttnom and increase vdimm _does_ now buncha 13 errors with 5 and 12
> Isn't there is RZQ/0.5?
> Or what I shoulda try something else...
> (addrBus setup doesnt posts if its not 55 or 56, rest works on 0 too but still same CAD BUS nightmares)
> 
> View attachment 2573408
> View attachment 2573410


RTTs can be a bit confusing! The number is a divider:
/1 = 240/1 = 240 ohms (strongest)
/7 = 240/7 = 34.3 ohms (weakest)

At 1.55V Nom will most likely want to be /7 or /6.


----------



## Taraquin

Dziarson said:


> B-die F4-3800cl14 Anta extreme 2 cycle, its look 2000MHz 1:1:1 stable
> 
> View attachment 2573404


Whea19 free? Check 3800 vs 4000 in linpack, my guess is you need to tinker with VDD18 to avoid negative scaling.


----------



## Dziarson

@Taraquin we will se tomorow i need to end tuning and install New systém this one is one big disaster 🤣🤣 i think last 125 blue screens dont help him 🤭


----------



## YoichiG

Dziarson said:


> @YoichiG try all auto i was have problem now from soc voltage to ckedrvstr i have auto and all working super


I was coming from auto and setting manually now, because auto threw me a lot errors than manual ones (24,24,24,24 for auto) so i had to do manually. Soc is already high enough for daily usage 1.12v




Bix said:


> RTTs can be a bit confusing! The number is a divider:
> /1 = 240/1 = 240 ohms (strongest)
> /7 = 240/7 = 34.3 ohms (weakest)
> 
> At 1.55V Nom will most likely want to be /7 or /6.


Man thank you so much you saved my life! I never hated this much ever in my life but thank you for enlightening me!
So i made Rzq4, now both 13-12 doesnt appear anymore. bit raised TRP by 1 because my ram getting pretty hot even without heatskinks, and fan addition 47-46 degree which is doesnt makes sense... So 1.55v is my limit so far i see.
Now wonder what should i do about CAD Setups... all 0 no post. but all 56 can work too either ckodtsetup and ckesetup 0/Auto but still throwing me few errors about setups. >.>


----------



## Bix

YoichiG said:


> I was coming from auto and setting manually now, because auto threw me a lot errors than manual ones (24,24,24,24 for auto) so i had to do manually. Soc is already high enough for daily usage 1.12v
> 
> 
> 
> 
> Man thank you so much you saved my life! I never hated this much ever in my life but thank you for enlightening me!
> So i made Rzq4, now both 13-12 doesnt appear anymore. bit raised TRP by 1 because my ram getting pretty hot even without heatskinks, and fan addition 47-46 degree which is doesnt makes sense... So 1.55v is my limit so far i see.
> Now wonder what should i do about CAD Setups... all 0 no post. but all 56 can work too either ckodtsetup and ckesetup 0/Auto but still throwing me few errors about setups. >.>
> View attachment 2573428


Not sure what you've tried up until now but I'd strongly recommend finding a stable baseline at 2T GDM Off before trying for 1T. There are just so many variables with timings and resistances etc that it can be almost impossible to work out what's causing the errors otherwise. It may seem like a step backwards but I promise it will save you time in the long run.

If I were you I'd start off by setting 2T command rate then putting all RTTs, CAD_BUS and setup times on auto (you shouldn't need setup timings on Auto anyway).

Then run 25 cycles of TM5 (edit the config file) of 1usmus_v3. This will help to show whether the timings themselves are causing you issues - your secondaries look really tight - or if there's anything you need to tweak before moving to 1T and dealing with resistances. 

CWL, RDWR and WRRD are often best left on Auto at first (CWL at 12 definitely looks too low).

Sorry if you've already done all this but it's so important to start from a stable baseline!


----------



## YoichiG

Bix said:


> Not sure what you've tried up until now but I'd strongly recommend finding a stable baseline at 2T GDM Off before trying for 1T. There are just so many variables with timings and resistances etc that it can be almost impossible to work out what's causing the errors otherwise. It may seem like a step backwards but I promise it will save you time in the long run.
> 
> If I were you I'd start off by setting 2T command rate then putting all RTTs, CAD_BUS and setup times on auto (you shouldn't need setup timings on Auto anyway).
> 
> Then run 25 cycles of TM5 (edit the config file) of 1usmus_v3. This will help to show whether the timings themselves are causing you issues - your secondaries look really tight - or if there's anything you need to tweak before moving to 1T and dealing with resistances.
> 
> CWL, RDWR and WRRD are often best left on Auto at first (CWL at 12 definitely looks too low).
> 
> Sorry if you've already done all this but it's so important to start from a stable baseline!


Thank you i will try back again! by the way i was using anta extreme until now but never seen 1usmus_v3.cfg downloadabile file anywhere. cant find from google is this got deleted?


----------



## KedarWolf

YoichiG said:


> Thank you i will try back again! by the way i was using anta extreme until now but never seen 1usmus_v3.cfg downloadabile file anywhere. cant find from google is this got deleted?











Memory Testing with TestMem5 TM5 with custom configs


Hello everybody I am just making a very light tutorial with a collection of custom config files and a DOWNLOAD LINK for TM5 v0.12 anta777 absolut config *Official* Intel DDR4 24/7 Memory Stability Thread None of the work is mine but it seems like a pretty good and fast testing app




www.overclock.net


----------



## YoichiG

KedarWolf said:


> Memory Testing with TestMem5 TM5 with custom configs
> 
> 
> Hello everybody I am just making a very light tutorial with a collection of custom config files and a DOWNLOAD LINK for TM5 v0.12 anta777 absolut config *Official* Intel DDR4 24/7 Memory Stability Thread None of the work is mine but it seems like a pretty good and fast testing app
> 
> 
> 
> 
> www.overclock.net


Thank you I finally can start testing with this!



Bix said:


> Not sure what you've tried up until now but I'd strongly recommend finding a stable baseline at 2T GDM Off before trying for 1T. There are just so many variables with timings and resistances etc that it can be almost impossible to work out what's causing the errors otherwise. It may seem like a step backwards but I promise it will save you time in the long run.
> 
> If I were you I'd start off by setting 2T command rate then putting all RTTs, CAD_BUS and setup times on auto (you shouldn't need setup timings on Auto anyway).
> 
> Then run 25 cycles of TM5 (edit the config file) of 1usmus_v3. This will help to show whether the timings themselves are causing you issues - your secondaries look really tight - or if there's anything you need to tweak before moving to 1T and dealing with resistances.
> 
> CWL, RDWR and WRRD are often best left on Auto at first (CWL at 12 definitely looks too low).
> 
> Sorry if you've already done all this but it's so important to start from a stable baseline!


No errors as expected like before happened.
First 30 minutes only showed me error 1 but realized late i didnt downgraded my vDIMM which is way mucher for 1.55 so i stopped and downgraded to 1.53V now testing since 50 minutes + 30 minutes from before. There not any error appeared and will appear i think. (Degrees now 45-46 since downgraded vdimm)
Leaved CWL, RDWR and WRRD auto as well rtts and cads. This is the result but 2T really made me lot ns increasion than 1T with
I Wonder if i can find something stable with RTT n BUS... or forever 2T? :'(









Edit 1: (Still going 10th cycle 60+ min no errors)
Edit 2:
Guess will leave from here.. later can do re-continue longer with your new suggestions or recommendations guys!
Degrees were: 46-46,5 for both dimms
timing is same as like above
also did web surfs, watched videos and stuffs


----------



## Errende

Finally got back to playing around with this a bit more. I noticed I was actually still getting mismatched tPHYRDL at 3666 and couldn't figure out how resolve it for real so I decided to just stick to 3600.
I'm totally tapped out trying to get 1866+ FCLK WHEA free without going to VDD18. The RAM seems fine running up to 4000 with FCLK decoupled. p95 large failed workers after a bit since all I touched was loose primaries and 1.45V, but no WHEA.

Ran 25 cycles of 1usmus_v3 with 2 hours of GPU heat and no errors. Did 4 iterations of all y-cruncher tests as well.
Still going to run 9 cycles of anta777 absolut to be sure I guess, but does seem fine? Since it's just cookie cutter tightening at advertised speed.
Spent most of the day trying various voltage adjustments and procodt but any changes seemed like margin of error or just worse. Guess it doesn't matter much at this speed?
Setting VDIMM to 1.380V seemed to make linpack go up a couple gflops but after a restart it went back to the previous average. Gave Windows a few minutes to settle down before each set.


----------



## Dziarson

@Taraquin linpak benchmark and sress test 10 loop completed 0 WHEA forgot run TM5 ;D


----------



## Melan

Errende said:


> Finally got back to playing around with this a bit more. I noticed I was actually still getting mismatched tPHYRDL at 3666 and couldn't figure out how resolve it for real so I decided to just stick to 3600


Either change command rate to 2T, increase tCL or set addrcmdsetup to 56
Using 2T is the less problematic way.


----------



## KedarWolf

This is my Linpack Xtreme with PBO.

That CO Curve is Linpack XTreme, y-cruncher stress tests, all tests, and Core Cycler stable on my new EVGA X570S Dark.


----------



## Taraquin

Dziarson said:


> @Taraquin linpak benchmark and sress test 10 loop completed 0 WHEA forgot run TM5 ;D
> View attachment 2573495
> 
> 
> View attachment 2573496


Nice! But check linpack on 3800 vs 4000


----------



## KedarWolf

Taraquin said:


> Nice! But check linpack on 3800 vs 4000


No point running 4000 on this CPU, WHEA fest.


----------



## Taraquin

KedarWolf said:


> No point running 4000 on this CPU, WHEA fest.


Ah, then ditch it. Even I run 3800 even though I get no WHEA at 4133, the needed increase in VDD18, SOC etc is not worth it due to noise, thermals etc.


----------



## Dziarson

Yyy i have define 7 and arctic liquid freezer ii 420 there is no noise from him PBO +200Mhz max temp curve - 10 63 when i play games


----------



## The_King

The_King said:


> This is another Micron Kit I have Crucial Ballistix 3600 CL 16-18-18-38-58 (C9BLM) 16GB DR Micron Rev. E
> Running ar 4133 CL16-19-19-44-63 1:1:1. Left CCD on Auto it will only boot with 1.2 CCD. This passes at least 5 cycles of TM5 1usmus.
> View attachment 2573334
> View attachment 2573335


 Comparison With Patriot Viper 4000 C19 running 4133 CL15 1:1:1


----------



## Bix

YoichiG said:


> Thank you I finally can start testing with this!
> 
> 
> 
> No errors as expected like before happened.
> First 30 minutes only showed me error 1 but realized late i didnt downgraded my vDIMM which is way mucher for 1.55 so i stopped and downgraded to 1.53V now testing since 50 minutes + 30 minutes from before. There not any error appeared and will appear i think. (Degrees now 45-46 since downgraded vdimm)
> Leaved CWL, RDWR and WRRD auto as well rtts and cads. This is the result but 2T really made me lot ns increasion than 1T with
> I Wonder if i can find something stable with RTT n BUS... or forever 2T? :'(
> View attachment 2573462
> 
> 
> Edit 1: (Still going 10th cycle 60+ min no errors)
> Edit 2:
> Guess will leave from here.. later can do re-continue longer with your new suggestions or recommendations guys!
> Degrees were: 46-46,5 for both dimms
> timing is same as like above
> also did web surfs, watched videos and stuffs
> 
> View attachment 2573468


Looking good🙂 Did it finish all 25 cycles without errors though? Sometimes they can come late...


----------



## YoichiG

Bix said:


> Looking good🙂 Did it finish all 25 cycles without errors though? Sometimes they can come late...


Yup, since no answer came for my post i left it open for 30 cycles before i sleep and woke up still dont see any error. Sadly my sleepy head closed the program without taking screenshot i thought i did...
But yes 30 cycles finished without any errors.
degrees avg 44.1 - 44.4 (since cold night) Max was 46.7-46.9


----------



## Bix

YoichiG said:


> Yup, since no answer came for my post i left it open for 30 cycles before i sleep and woke up still dont see any error. Sadly my sleepy head closed the program without taking screenshot i thought i did...
> But yes 30 cycles finished without any errors.
> degrees avg 44.1 - 44.4 (since cold night) Max was 46.7-46.9


Great! If changing straight to 1T gives you a ton of errors straight away then the first thing I'd try is setting just AddrCmdSetup to 56 - most people here need that to run 1T with a dual rank config. Also CKE 9 can often work better at 3800.


----------



## YoichiG

Bix said:


> Great! If changing straight to 1T gives you a ton of errors straight away then the first thing I'd try is setting just AddrCmdSetup to 56 - most people here need that to run 1T with a dual rank config. Also CKE 9 can often work better at 3800.


Allright! Either i cant boot windows without setting AddrCmdSetup 55 or 56 so obviously im gonna do that. will try about tCKE 9 never touched this timing

Edit: they came back


----------



## Anhphe93

YoichiG said:


> Allright! Either i cant boot windows without setting AddrCmdSetup 55 or 56 so obviously im gonna do that. will try about tCKE 9 never touched this timing
> 
> Edit: they came back
> 
> View attachment 2573540


I guess u need play with CAD. I have successfully stabilized 1T GDM off on 3800 with 4 sticks of ram. Which previously failed with 24-24-24-24. Now looks good with 40-20-30-20


----------



## Robby37

YoichiG said:


> I was coming from auto and setting manually now, because auto threw me a lot errors than manual ones (24,24,24,24 for auto) so i had to do manually. Soc is already high enough for daily usage 1.12v
> 
> 
> 
> 
> Man thank you so much you saved my life! I never hated this much ever in my life but thank you for enlightening me!
> So i made Rzq4, now both 13-12 doesnt appear anymore. bit raised TRP by 1 because my ram getting pretty hot even without heatskinks, and fan addition 47-46 degree which is doesnt makes sense... So 1.55v is my limit so far i see.
> Now wonder what should i do about CAD Setups... all 0 no post. but all 56 can work too either ckodtsetup and ckesetup 0/Auto but still throwing me few errors about setups. >.>
> View attachment 2573428


tcwl should equal tcl and trfc needs be a multiple of trtp so try changing trtp and make sure use the trfc mini cal . Change scls to 4 also and trrdl to 6 see if that gets rid of errors . you might even get better performance from fixing the scl . Then you can try to reduce the trdwr to 11 or maybe 10 afterwards . Also with setup times why not run tcke of 9 and last is vddp 900 CCD 940 iod 1 or 1060 and vsoc 1.1 prob would be better IMO . Also did you try setup times of 3 3 15 with tcke 9 ? 55 or 56 I would think would not be good to use with 2t and at 1t it performed same or worse than 2t without delays on setup. but I honestly am learning more about them still so could be completely wrong. I do know that aqt 3800 3 3 15 with tcke 9 is correct tho and you want to run flat x 202020 with that . I can run 20202020 with 30 or 28.8 proc on 64gb of bdie so it def works . And I am running 7 3 0 rtts and ran 7 2 0 at one point as well but the 0off park helps temps alot.


----------



## YoichiG

Anhphe93 said:


> I guess u need play with CAD. I have successfully stabilized 1T GDM off on 3800 with 4 sticks of ram. Which previously failed with 24-24-24-24. Now looks good with 40-20-30-20


My rams 2 sticks instead 4 but i always play with bus'es since from first. Will try this cads again thank you!



Robby37 said:


> tcwl should equal tcl and trfc needs be a multiple of trtp so try changing trtp and make sure use the trfc mini cal . Change scls to 4 also and trrdl to 6 see if that gets rid of errors . you might even get better performance from fixing the scl . Then you can try to reduce the trdwr to 11 or maybe 10 afterwards . Also with setup times why not run tcke of 9 and last is vddp 900 CCD 940 iod 1 or 1060 and vsoc 1.1 prob would be better IMO . Also did you try setup times of 3 3 15 with tcke 9 ? 55 or 56 I would think would not be good to use with 2t and at 1t it performed same or worse than 2t without delays on setup. but I honestly am learning more about them still so could be completely wrong. I do know that aqt 3800 3 3 15 with tcke 9 is correct tho and you want to run flat x 202020 with that . I can run 20202020 with 30 or 28.8 proc on 64gb of bdie so it def works . And I am running 7 3 0 rtts and ran 7 2 0 at one point as well but the 0off park helps temps alot.


The problem is not timings or volts. as from 2T with all rtt cad auto 0 setups, same timings, same volts 30 cycle run there no any error appears i just have problem with resistances and CADs with 1T...


----------



## Bix

YoichiG said:


> Allright! Either i cant boot windows without setting AddrCmdSetup 55 or 56 so obviously im gonna do that. will try about tCKE 9 never touched this timing
> 
> Edit: they came back
> 
> View attachment 2573540


7/3/3 and 6/3/3 are good starting points for DR RTTs. 

For CAD_BUS, 24-20-24-24, 30-20-30-24 and 40-20-30-20 (like @Anhphe93 suggests) are good to try first.
I'd try changing RTTs first and run TM5 long enough to see which looks most promising and then trying that combo with different CAD_BUS options.


----------



## YoichiG

Bix said:


> 7/3/3 and 6/3/3 are good starting points for DR RTTs.
> 
> For CAD_BUS, 24-20-24-24, 30-20-30-24 and 40-20-30-20 (like @Anhphe93 suggests) are good to try first.
> I'd try changing RTTs first and run TM5 long enough to see which looks most promising and then trying that combo with different CAD_BUS options.


did 7/3/3 first with same cad bus:
first threw me error 0 at start, then error 0 after a min, error 1-1 came last before test 11,15 comes. and again error 0 when passing to next cycle.








There wasnt anything else until 15th min:
Degrees bit raised? can be my room but 46.9-47.3 degrees im getting with same vdimm.








Edit: Trying 40/20/30/20 now
Edit 2: Just realized since we changed tCKE to 9. Every change in memory resistances gives me ntfs.sys blue screen at booting windows(now 2 times with CAD changes). resetting bios, reimport current profile and setting CAD 40/20/30/20 again and save, then boots without any problem and testing right now.
Edit 3: Seems 40/20/30/20 promising. first cycle when 13th test came it gave error 13 once. Going to test until 15 min like previous same time.








Edit 4: at 2nd cycle when test 1 came it gave twice error 1 quickly, then end without anything else. at 3rd cycle it was in test 2 but gave error 1 once then error 2 twice when aboutta end test 2. lastly error 13 at 15th min








Time to try 30-20-30-24 guess?
Edit 5: Again blue screen at boot same ntfs.sys error after memory changes. I think this happen because of tCKE? since never ever happened this before.
Doesnt boot back after blue screen, mobo itself resetting bios. I reset it, reimport the profile again and testing with 30-20-30-24 at windows now.
Last edit: Honestly im really shocked... 30-20-30-24 made it really stable with 7/3/3. i might tried similar and near but not literally like that CAD's and RTT's. Like found rabbit hole.








Do you want to suggest or recommend anything else? like reducing tcke to 1 to avoid bluescreens for future?
(Still keeping run 25 min no errors)


----------



## Bix

YoichiG said:


> did 7/3/3 first with same cad bus:
> first threw me error 0 at start, then error 0 after a min, error 1-1 came last before test 11,15 comes. and again error 0 when passing to next cycle.
> View attachment 2573547
> 
> There wasnt anything else until 15th min:
> Degrees bit raised? can be my room but 46.9-47.3 degrees im getting with same vdimm.
> View attachment 2573550
> 
> Edit: Trying 40/20/30/20 now
> Edit 2: Just realized since we changed tCKE to 9. Every change in memory resistances gives me ntfs.sys blue screen at booting windows(now 2 times with CAD changes). resetting bios, reimport current profile and setting CAD 40/20/30/20 again and save, then boots without any problem and testing right now.
> Edit 3: Seems 40/20/30/20 promising. first cycle when 13th test came it gave error 13 once. Going to test until 15 min like previous same time.
> View attachment 2573552
> 
> Edit 4: at 2nd cycle when test 1 came it gave twice error 1 quickly, then end without anything else. at 3rd cycle it was in test 2 but gave error 1 once then error 2 twice when aboutta end test 2. lastly error 13 at 15th min
> View attachment 2573553
> 
> Time to try 30-20-30-24 guess?
> Edit 5: Again blue screen at boot same ntfs.sys error after memory changes. I think this happen because of tCKE? since never ever happened this before.
> Doesnt boot back after blue screen, mobo itself resetting bios. I reset it, reimport the profile again and testing with 30-20-30-24 at windows now.
> Last edit: Honestly im really shocked... 30-20-30-24 made it really stable with 7/3/3. i might tried similar and near but not literally like that CAD's and RTT's. Like found rabbit hole.
> View attachment 2573558
> 
> Do you want to suggest or recommend anything else? like reducing tcke to 1 to avoid bluescreens for future?
> (Still keeping run 25 min no errors)


Good progress! Let it run for a full 25 cycles now and collect errors before changing anything else. The longer you test the clearer it'll be what needs tweaking. ClkDrvStr might well have been too strong at 40.


----------



## Robby37

YoichiG said:


> My rams 2 sticks instead 4 but i always play with bus'es since from first. Will try this cads again thank you!
> 
> 
> The problem is not timings or volts. as from 2T with all rtt cad auto 0 setups, same timings, same volts 30 cycle run there no any error appears i just have problem with resistances and CADs with 1T...


Their are a few errors in the timings your using tho so it will manifest with 1t without a doubt . If you fix those mismatches it may help


----------



## Robby37

def want tcwl to match tcl and def want trfc to be a multipole of trtp


----------



## Anhphe93

YoichiG said:


> did 7/3/3 first with same cad bus:
> first threw me error 0 at start, then error 0 after a min, error 1-1 came last before test 11,15 comes. and again error 0 when passing to next cycle.
> View attachment 2573547
> 
> There wasnt anything else until 15th min:
> Degrees bit raised? can be my room but 46.9-47.3 degrees im getting with same vdimm.
> View attachment 2573550
> 
> Edit: Trying 40/20/30/20 now
> Edit 2: Just realized since we changed tCKE to 9. Every change in memory resistances gives me ntfs.sys blue screen at booting windows(now 2 times with CAD changes). resetting bios, reimport current profile and setting CAD 40/20/30/20 again and save, then boots without any problem and testing right now.
> Edit 3: Seems 40/20/30/20 promising. first cycle when 13th test came it gave error 13 once. Going to test until 15 min like previous same time.
> View attachment 2573552
> 
> Edit 4: at 2nd cycle when test 1 came it gave twice error 1 quickly, then end without anything else. at 3rd cycle it was in test 2 but gave error 1 once then error 2 twice when aboutta end test 2. lastly error 13 at 15th min
> View attachment 2573553
> 
> Time to try 30-20-30-24 guess?
> Edit 5: Again blue screen at boot same ntfs.sys error after memory changes. I think this happen because of tCKE? since never ever happened this before.
> Doesnt boot back after blue screen, mobo itself resetting bios. I reset it, reimport the profile again and testing with 30-20-30-24 at windows now.
> Last edit: Honestly im really shocked... 30-20-30-24 made it really stable with 7/3/3. i might tried similar and near but not literally like that CAD's and RTT's. Like found rabbit hole.
> View attachment 2573558
> 
> Do you want to suggest or recommend anything else? like reducing tcke to 1 to avoid bluescreens for future?
> (Still keeping run 25 min no errors)


Like I said earlier, you will need to find the right CAD for yourself lol 
Congratulations on finding your sweet spot!


----------



## Taraquin

The_King said:


> Comparison With Patriot Viper 4000 C19 running 4133 CL15 1:1:1
> View attachment 2573526
> View attachment 2573527


Damn those Viper-sticks are really impressive! My 4400c19 can't even do flat 14 at 3800 with some extras cooling without overheating. How do you cool them?


----------



## Valka814

I might have found the error free settings, but cant get away the TM5 stuck problem. The install in not corrupted.
The issue appears also, when only the primaries, 2T and voltages set.


----------



## Frosted racquet

Valka814 said:


> I might have found the error free settings, but cant get away the TM5 stuck problem. The install in not corrupted.
> The issue appears also, when only the primaries, 2T and voltages set.


Test in Safe Mode.


----------



## The_King

Taraquin said:


> Damn those Viper-sticks are really impressive! My 4400c19 can't even do flat 14 at 3800 with some extras cooling without overheating. How do you cool them?


There is no cooling at all on my setup it is still out of the case and the DIMM temps go over 60 without any problem. I tested this when it was paired with my G.Skill ram that had temp sensors, Vipers as you know do not have temp sensor. So not the most accurate but should be in the ballpark even abit higher than the G.Skill temps.

I decided to buy another 4000 C19 kit. Sadly this does not perform the same it can't do 3800 14-14-14. @ 1.55V
Im also having a problem to get all 4 sticks boot 3800 FCLK 1900 CL16/15 consistently. it boots when it wants to.  with the G.skill or mixed Patriot 4400 I use 43.6 ProcODT and it boots 3800 CL14/15/16 all the time no problems.

I almost got 3800 CL15 stable. but any advice is always welcome and appreciated. Not sure if i should try the Rttnom disable thingy I seen a few post back?










Not sure if my Phanteks cooler is taking some of the heat away from the RAM or making it hotter.No need for any cable management 


Spoiler: No case


----------



## Taraquin

The_King said:


> There is no cooling at all on my setup it is still out of the case and the DIMM temps go over 60 without any problem. I tested this when it was paired with my G.Skill ram that had temp sensors, Vipers as you know do not have temp sensor. So not the most accurate but should be in the ballpark even abit higher than the G.Skill temps.
> 
> I decided to buy another 4000 C19 kit. Sadly this does not perform the same it can't do 3800 14-14-14. @ 1.55V
> Im also having a problem to get it to all 4 sticks boot 3800 FCLK 1900 CL16/15 consistently. it boots when it wants to.  with the G.skill or mixed Patriot 4400 I use 43.6 ProcODT and it boots 3800 CL14/15/16 all the time no problems.
> 
> I almost got 3800 CL15 stable. but any advice is always welcome and appreciated. Not sure if i should try the Rttnom disable thingy I seen a few post back?
> 
> View attachment 2573662
> 
> 
> Not sure if my Phanteks cooler is taking some of the heat away from the RAM or making it hotter.No need for any cable management
> 
> 
> Spoiler: No case
> 
> 
> 
> 
> View attachment 2573664
> 
> View attachment 2573663


Not so good at 4xSR setups, probably DrvStr related, maybe RttPark. Blameless, Bix, Veii etc may be able to help?


----------



## Bix

The_King said:


> There is no cooling at all on my setup it is still out of the case and the DIMM temps go over 60 without any problem. I tested this when it was paired with my G.Skill ram that had temp sensors, Vipers as you know do not have temp sensor. So not the most accurate but should be in the ballpark even abit higher than the G.Skill temps.
> 
> I decided to buy another 4000 C19 kit. Sadly this does not perform the same it can't do 3800 14-14-14. @ 1.55V
> Im also having a problem to get all 4 sticks boot 3800 FCLK 1900 CL16/15 consistently. it boots when it wants to.  with the G.skill or mixed Patriot 4400 I use 43.6 ProcODT and it boots 3800 CL14/15/16 all the time no problems.
> 
> I almost got 3800 CL15 stable. but any advice is always welcome and appreciated. Not sure if i should try the Rttnom disable thingy I seen a few post back?
> 
> View attachment 2573662
> 
> 
> Not sure if my Phanteks cooler is taking some of the heat away from the RAM or making it hotter.No need for any cable management
> 
> 
> Spoiler: No case
> 
> 
> 
> 
> View attachment 2573664
> 
> View attachment 2573663


I'd try to lower ProcODT first of all since it made a big difference to me when pushing timings, especially the secondaries. Lower CLDO_VDDP and VDDGs (especially CCD) can help with this and yours look like they're on Auto ATM... Try something like .86V VDDP, .9 CCD, 1.02 IOD and 1.1 SOC (watch out for WHEA 19s though) and then see if you can bring down Proc. 

If you can't then ClkDrvStr and Park might want to be weaker.


----------



## The_King

Bix said:


> I'd try to lower ProcODT first of all since it made a big difference to me when pushing timings, especially the secondaries. Lower CLDO_VDDP and VDDGs (especially CCD) can help with this and yours look like they're on Auto ATM... Try something like .86V VDDP, .9 CCD, 1.02 IOD and 1.1 SOC (watch out for WHEA 19s though) and then see if you can bring down Proc.
> 
> If you can't then ClkDrvStr and Park might want to be weaker.


Thanks for the reply. VDDP CCD and IOD are set to 1.05V manually sometimes with 4 DIMMS lower values can cause boot issues. I had it set to the .85V 0.9V 1.0V before increasing it since I was not getting anything to boot.

The ProcODT that usually works with my B450 board for 4 X SR DIMMS is 43.6.ohms. I have tried from your previous posts to boot everything from 28.2 and higher RTTs 6/3/5. No luck with that.

I did get 43.6 to boot and pass TM5 but if I make any change in the BIOS it will not boot again. Not sure if its that dreaded 1900 FCLK hole but the CPU has no problems booting 1900 FCLK with 2 DIMMS.consistently.

So far only ProcODT 40, 43.6 and 48 Ohms have booted succesfully with 4 DIMMS. All pass 5 cycles of TM5 just a quick test to see its not throwing errors.


















Edit dropped Park to 4 seems to be working will test and see how it goes.


----------



## Bix

The_King said:


> Thanks for the reply. VDDP CCD and IOD are set to 1.05V manually sometimes with 4 DIMMS lower values can cause boot issues. I had it set to the .85V 0.9V 1.0V before increasing it since I was not getting anything to boot.
> 
> The ProcODT that usually works with my B450 board for 4 X SR DIMMS is 43.6.ohms. I have tried from your previous posts to boot everything from 28.2 and higher RTTs 6/3/5. No luck with that.
> 
> I did get 43.6 to boot and pass TM5 but if I make any change in the BIOS it will not boot again. Not sure if its that dreaded 1900 FCLK hole but the CPU has no problems booting 1900 FCLK with 2 DIMMS.consistently.
> 
> So far only ProcODT 40, 43.6 and 48 Ohms have booted succesfully with 4 DIMMS. All pass 5 cycles of TM5 just a quick test to see its not throwing errors.
> 
> View attachment 2573728
> View attachment 2573729
> View attachment 2573730


Something's wrong there - I had no issues with 4x8 Vipers on my B450 Tomahawk at 3800 so it's really weird that you're having issues even POSTing. Have you tried at 3866 or 3734? If they work then it's most probably an FCLK hole.


----------



## rjatlsj

Hello all, this is my first time writing 

I want to know how to make tphyrdl 26 in 4000 cl13. Please give me a lot of advice

vsoc ccd iod vddp pll voltages have been modified to avoid WHEA errors at 4000 clock

Thanks for reading !


----------



## The_King

Bix said:


> Something's wrong there - I had no issues with 4x8 Vipers on my B450 Tomahawk at 3800 so it's really weird that you're having issues even POSTing. Have you tried at 3866 or 3734? If they work then it's most probably an FCLK hole.


This could be the case but the same CPU has no problems with 2 Dual Rank DIMMS @ 3800 FCLK 1900, that post like clockwork. A work around I found to get this to board to boot is to make a profile and save it. Clear CMOS and then load the profile then it boots. Seems this board likes the whole song and dance before its willing to work with 4 DIIMMS.


----------



## KedarWolf




----------



## Bix

The_King said:


> This could be the case but the same CPU has no problems with 2 Dual Rank DIMMS @ 3800 FCLK 1900, that post like clockwork. A work around I found to get this to board to boot is to make a profile and save it. Clear CMOS and then load the profile then it boots. Seems this board likes the whole song and dance before its willing to work with 4 DIIMMS.
> View attachment 2573780


Not ideal! The only other things I could suggest are trying CsOdtDrvStr at 30 (can apparently cause training issues on Vermeer if lower than that but I've never had this problem) and maybe trying a different BIOS version. 
There are memory training settings in BIOS too but I haven't a clue how they work...


----------



## heptilion

KedarWolf said:


> View attachment 2573789
> View attachment 2573792
> 
> View attachment 2573791
> 
> View attachment 2573790


weren't you using 28 procodt before? did running this at 60ohm help with something?


----------



## Nighthog

Bix said:


> Not ideal! The only other things I could suggest are trying CsOdtDrvStr at 30 (can apparently cause training issues on Vermeer if lower than that but I've never had this problem) and maybe trying a different BIOS version.
> There are memory training settings in BIOS too but I haven't a clue how they work...


I've seen help with POST when adjusting CsOdtDrvStr to 30 & 40Ohm at times but it's usually quite specific if it helps or not. Often it helps to POST but has caused Memory errors on my end when I've been pushing 4xdimm to maximum board limits. So it's been kind of a wash if you need or should use it in the end. Might need other voltage adjustments to compliment it.


----------



## Robby37

The_King said:


> This could be the case but the same CPU has no problems with 2 Dual Rank DIMMS @ 3800 FCLK 1900, that post like clockwork. A work around I found to get this to board to boot is to make a profile and save it. Clear CMOS and then load the profile then it boots. Seems this board likes the whole song and dance before its willing to work with 4 DIIMMS.
> View attachment 2573780


I run 4 dr sticks and I have found that 4 sticks need low drv values and low proc odt to keep nice clean signal then you want park wither 1 or off and rtt nom 7 as that's the weakest . Also with 20 drv you use tcke and cad setup for termination so use 9 and 3 3 15 . you can use the tcke 9 without the setup timings to . Last is iod change to 1.02 and vddp 900 and CCD 940 and vsoc 1.1 or 1.06 but id rec 1.1 to start since 4 sticks is harder on the imc . Unless its a asrock board then I understand its a 75 25 percent split with signaling so put your stronger pair on the secondary slots but simply swapping sticks from one slot to to the other can make huge diff . Last is to check to rule out imc run 3600 or 3200 fclk just to stabilize the ram at 3800. Oh super important trdwr does not usually work great with trcdwr/2 so usually you want +1 or 2 for trdwr. I would start 10 and twrrd 3 or even 4 and then work down. I have been doing this and just stabilized 3733 at cl14 flat with real tight secondaries when prev i had to run cl 16 and 5 7 20 for trrd tfaw and 5 14 for twtr. The only value that stays loose for me no matter what is my trdwr since i have 4 dual rank sticks . I also am running 4.9 currently and was able run 4.75 at 3666 with same timings so i think i will work down to 4.8 hopefully . Then i will move on to 3800 and 3866 which i assume i wont get past at cl14 . I am thinking i will have to increase my trcdrd to 15 to make 3800 with nice secondaries or i may just go cl15 or 16 flat if it gets me to 3900. I know this is diff ram but it is two 32 gb kits that are 3200 cl14 so cheap b die that's pushed real hard and its not like its a good PCB either . iirc they are b1


ps I caught up and see bix beat me to it with some of what I said but I def agree and he knows what he doing so I think its worth trying lower voltages little more . At the least the cldo vddp should stay 900 as that can be hard to get error free when playing with it . Also the lower voltages are key to the lower proc odt . i can boot my 4 sticks at 28.8 with my new lower voltages . i used to also need 43.6 and needed like 1.51 v on my ram when I ran higher voltages that all started cause the dram calculator and I just was stuck in that range until I started from scratch again and worked my way from my docp timings and stayed as low as I could .


----------



## Robby37

rjatlsj said:


> View attachment 2573750
> 
> View attachment 2573751
> 
> View attachment 2573752
> 
> 
> Hello all, this is my first time writing
> 
> I want to know how to make tphyrdl 26 in 4000 cl13. Please give me a lot of advice
> 
> vsoc ccd iod vddp pll voltages have been modified to avoid WHEA errors at 4000 clock
> 
> Thanks for reading !


try reducing cldo vddp to 900 and if you can access CPU vddp make it 880 . give cad setup a shot so you would do cmd setup 4 -4 -18 and tcke 11 with like 40-20-20-20

good info here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


----------



## The_King

Robby37 said:


> I run 4 dr sticks and I have found that 4 sticks need low drv values and low proc odt to keep nice clean signal then you want park wither 1 or off and rtt nom 7 as that's the weakest . Also with 20 drv you use tcke and cad setup for termination so use 9 and 3 3 15 . you can use the tcke 9 without the setup timings to . Last is iod change to 1.02 and vddp 900 and CCD 940 and vsoc 1.1 or 1.06 but id rec 1.1 to start since 4 sticks is harder on the imc . Unless its a asrock board then I understand its a 75 25 percent split with signaling so put your stronger pair on the secondary slots but simply swapping sticks from one slot to to the other can make huge diff . Last is to check to rule out imc run 3600 or 3200 fclk just to stabilize the ram at 3800. Oh super important trdwr does not usually work great with trcdwr/2 so usually you want +1 or 2 for trdwr. I would start 10 and twrrd 3 or even 4 and then work down. I have been doing this and just stabilized 3733 at cl14 flat with real tight secondaries when prev i had to run cl 16 and 5 7 20 for trrd tfaw and 5 14 for twtr. The only value that stays loose for me no matter what is my trdwr since i have 4 dual rank sticks . I also am running 4.9 currently and was able run 4.75 at 3666 with same timings so i think i will work down to 4.8 hopefully . Then i will move on to 3800 and 3866 which i assume i wont get past at cl14 . I am thinking i will have to increase my trcdrd to 15 to make 3800 with nice secondaries or i may just go cl15 or 16 flat if it gets me to 3900. I know this is diff ram but it is two 32 gb kits that are 3200 cl14 so cheap b die that's pushed real hard and its not like its a good PCB either . iirc they are b1


I managed to get 3800 CL16 to pass 5 cycles busy testing 3800 CL15 with GMD OFF 1T at the moment. I will drop VDDP and other settings once I find a stable config. It rarely causes issues being abit high in my testing with TM5.


----------



## Robby37

The_King said:


> I managed to get 3800 CL16 to pass 5 cycles busy testing 3800 CL15 with GMD OFF 1T at the moment. I will drop VDDP and other settings once I find a stable config. It rarely causes issues being abit high in my testing with TM5.
> View attachment 2573844


Ya but I have seen ot messages training up .


----------



## rjatlsj

[인용문="rjatlsj, 게시물: 29036819, 회원: 657644"]
[첨부]2573750[/첨부]


Robby37 said:


> try reducing cldo vddp to 900 and if you can access CPU vddp make it 880 . give cad setup a shot so you would do cmd setup 4 -4 -18 and tcke 11 with like 40-20-20-20
> 
> good info here [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread



-------------------------------
give cad setup a shot so you would do cmd setup 4 -4 -18
--------------------------------
Thank you for your advice. But I don't understand this part. Can you explain it in detail?


----------



## The_King

Ok guys so here is something interesting for those who are having issues with FCLK 1900 on ZEN 3.

After changing almost everything single 🤬 voltage, RTT and DrvStr for the past 2 days I notice that with boost override if the incorrect CPU voltage or CO was used my PC would fail to boot.

I then noticed after I change CO and CPU voltage 3733MT FCLK 1867 no longer booted despite booting before the adjustments every single time.

So I loaded 3800MT FCLK 1900 and set -5 CO in the BIOS on all core and no more boot issues at FCLK 1900 for me. This may or may not help you with your FCLK issues. Just something to look at. Sweet.


----------



## Bix

The_King said:


> Ok guys so here is something interesting for those who are having issues with FCLK 1900 on ZEN 3.
> 
> After changing almost everything single 🤬 voltage, RTT and DrvStr for the past 2 days I notice that with boost override if the incorrect CPU voltage or CO was used my PC would fail to boot.
> 
> I then noticed after I change CO and CPU voltage 3733MT FCLK 1867 no longer booted despite booting before the adjustments every single time.
> 
> So I loaded 3800MT FCLK 1900 and set -5 CO in the BIOS on all core and no more boot issues at FCLK 1900 for me. This may or may not help you with your FCLK issues. Just something to look at. Sweet.
> View attachment 2573919


So just to confirm, with no CO set you had boot issues but now with -5 all-core CO it boots fine??


----------



## Robby37

Bix said:


> So just to confirm, with no CO set you had boot issues but now with -5 all-core CO it boots fine??


Think he reduced to -5 unless I'm reading wrong .


----------



## Robby37

The_King said:


> Thanks for the reply. VDDP CCD and IOD are set to 1.05V manually sometimes with 4 DIMMS lower values can cause boot issues. I had it set to the .85V 0.9V 1.0V before increasing it since I was not getting anything to boot.
> 
> The ProcODT that usually works with my B450 board for 4 X SR DIMMS is 43.6.ohms. I have tried from your previous posts to boot everything from 28.2 and higher RTTs 6/3/5. No luck with that.
> 
> I did get 43.6 to boot and pass TM5 but if I make any change in the BIOS it will not boot again. Not sure if its that dreaded 1900 FCLK hole but the CPU has no problems booting 1900 FCLK with 2 DIMMS.consistently.
> 
> So far only ProcODT 40, 43.6 and 48 Ohms have booted succesfully with 4 DIMMS. All pass 5 cycles of TM5 just a quick test to see its not throwing errors.
> 
> View attachment 2573729
> View attachment 2573730
> 
> 7 3 1 rtts usually works good with tcke 9 and 3-3-15 setup or nop setup timings can work to but for 4 dimms 7 3 1 is usually the ticket for me to be able to boot low proc odt like down to 30 or 28.8
> 
> 
> Edit dropped Park to 4 seems to be working will test and see how it goes.
> View attachment 2573731


----------



## ManniX-ITA

The_King said:


> I then noticed after I change CO *and CPU voltage* 3733MT FCLK 1867 no longer booted despite booting before the adjustments every single time.


There's also this change of CPU voltage. What would be exactly?


----------



## Robby37

rjatlsj said:


> [인용문="rjatlsj, 게시물: 29036819, 회원: 657644"]
> [첨부]2573750[/첨부]
> 
> 
> -------------------------------
> give cad setup a shot so you would do cmd setup 4 -4 -18
> --------------------------------
> Thank you for your advice. But I don't understand this part. Can you explain it in detail?


so the values on bottom right in zen timings . so you do tcke 12 and the the addcmndsetup 4 csodtsetup 4 and cke setup 18


----------



## The_King

Bix said:


> So just to confirm, with no CO set you had boot issues but now with -5 all-core CO it boots fine??


My original setup was PBO disabled in the BIOS with -0.0500V CPU voltage offset. 

I had no issues booting up to 3733/1867 with the above settings. 3800/1900 was only booting randomly.

After I reset CPU Voltage to Auto and rebooted, I started having boot issues with 3733, droping CPU voltage to -0.0500V got 3733 booting again.

Adding -5 to all cores in the BIOS is now geting 3800/1900 to boot much more easily than before the RAM sometimes trains once but usually boots much faster now.


----------



## Bix

The_King said:


> My original setup was PBO disabled in the BIOS with -0.0500V CPU voltage offset.
> 
> I had no issues booting up to 3733/1867 with the above settings. 3800/1900 was only booting randomly.
> 
> After I reset CPU Voltage to Auto and rebooted, I started having boot issues with 3733, droping CPU voltage to -0.0500V got 3733 booting again.
> 
> Adding -5 to all cores in the BIOS is now geting 3800/1900 to boot much more easily than before the RAM sometimes trains once but usually boots much faster now.


That's very strange! Any ideas @ManniX-ITA ?


----------



## ManniX-ITA

Bix said:


> That's very strange! Any ideas @ManniX-ITA ?


Have the feeling it's a specific setup issue, not the widespread issue of Zen2/3 not booting at FCLK 1900.
When the combo board/cpu doesn't boot at 1900 there's never POST and if the postcode is visible fails with 07.
Here's there's a slow/random failing boot which is solved with a sequence of configuration settings, looks to me different.


----------



## Bix

ManniX-ITA said:


> Have the feeling it's a specific setup issue, not the widespread issue of Zen2/3 not booting at FCLK 1900.
> When the combo board/cpu doesn't boot at 1900 there's never POST and if the postcode is visible fails with 07.
> Here's there's a slow/random failing boot which is solved with a sequence of configuration settings, looks to me different.


Yes, it does seem system specific - I've just never seen a POSTing/stability issue solved by lowering VID across all cores!


----------



## ManniX-ITA

Bix said:


> I've just never seen a POSTing/stability issue solved by lowering VID across all cores!


It can happen indeed, depends on board bios/agesa.
Did happen to me with my 3800X and some earlier versions of the aorus master bios.


----------



## The_King

ManniX-ITA said:


> Have the feeling it's a specific setup issue, not the widespread issue of Zen2/3 not booting at FCLK 1900.
> When the combo board/cpu doesn't boot at 1900 there's never POST and if the postcode is visible fails with 07.
> Here's there's a slow/random failing boot which is solved with a sequence of configuration settings, looks to me different.


I had less issue with mixing ram kits than running all 4 of the same dimms. That maybe a factor. 
Tomorrow I will pull one set of the Vipers out and Run my G.Skill B-die kit with this and see if I have the same issues with FCLK 1900


----------



## The_King

Bix said:


> Yes, it does seem system specific - I've just never seen a POSTing/stability issue solved by lowering VID across all cores!


Oh! Another inteteresting thing. I could not boot into windows with anything higher than +25Mhz boost override.

Setting the -0.0500V offset on the CPU allowed +100Mhz boost override to boot into windows and is completely stable.

The cause of this is one of my "good cores" is boosting 100-125Mhz higher than the rest and was causing BSOD at windows startup/login.
I had to use a +5 on that core and can boot +200Mhz override into windows completely stable. This was before I made the changes to -5 All core
so no boost override at the moment.


----------



## rjatlsj

Robby37 said:


> so the values on bottom right in zen timings . so you do tcke 12 and the the addcmndsetup 4 csodtsetup 4 and cke setup 18













vddp 0.88 ~0.9, tcke 11 ~12 still same. tphyrdl 28 

Can I know another way?


----------



## Bix

rjatlsj said:


> View attachment 2573963
> 
> 
> 
> vddp 0.88 ~0.9, tcke 11 ~12 still same. tphyrdl 28
> 
> Can I know another way?


From what I've read on this thread VDDP, tCL, tRC and tRAS can all influence the way tPHYRDL trains. If raising VDDP doesn't help then loosening tCL to 14 and/or tRC and tRAS might actually result in lower latency if tPHYRDL comes down to 26. It's worth testing at least🙂


----------



## rjatlsj

Bix said:


> From what I've read on this thread VDDP, tCL, tRC and tRAS can all influence the way tPHYRDL trains. If raising VDDP doesn't help then loosening tCL to 14 and/or tRC and tRAS might actually result in lower latency if tPHYRDL comes down to 26. It's worth testing at least🙂












Hello, in real 2T 4000 cl14, I was able to check two tphyrdl 26 










now I can check 26 after changing to Real 1t 
I'll try to refine it a little bit. Thank you for your advice


----------



## Bix

rjatlsj said:


> View attachment 2573969
> 
> 
> Hello, in real 2T 4000 cl14, I was able to check two tphyrdl 26
> 
> View attachment 2573970
> 
> 
> now I can check 26 after changing to Real 1t
> I'll try to refine it a little bit. Thank you for your advice


Nice work!

tCKE 11 _might _help with stability at 4000 too.


----------



## HEYY0M1KEY

Finally got GDM off 2T stable. No improvement in performance over GDM on, actually 3ns penalty in Aida. It's a start at least. First goal is to hit 54ns latency along with everything else in Linpack, Cinebench, and Timespy improving.

EDIT: Ryzen Master needs to be uninstalled. Latency dropped to 54.9 to 55.1. Weird that it causes that much latency. Was using it quick to verify curve was applied while testing my curve in corecycler.


----------



## rjatlsj

tCKE 11 _might _help with stability at 4000 too.
[/QUOTE]


Bix said:


> Nice work!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> I tried various things (voltages, impedance, addrcmdsetup)
> but, I couldn't catch the error.
> 
> should be satisfied with 4000 cl 14
> I'll try it whenever I have time
> 
> Thank you for your words.


----------



## aditrex

my latency is kinda weak isnt it am i doing something wrong here?


----------



## The_King

aditrex said:


> my latency is kinda weak isnt it am i doing something wrong here?
> View attachment 2574006


Aside from RTP which should be at 5.

You have several programs opened in the background that will affect latency. Discord and Voicemeter? Close all those programs and also disconnect from the internet
and run the test again.

you can also try WTRS 3 if that is stable WTRL 7.

Are your not getting 3800 FCLK 1900 to boot with your 5800X? Try ProcODT 43.6 and see if that helps or try going lower with it 36.9.


----------



## HEYY0M1KEY

aditrex said:


> my latency is kinda weak isnt it am i doing something wrong here?
> View attachment 2574006


I was wondering on my own results as well. I uninstalled Ryzen Master, which was adding 3 ns of latency. Corsair Icue was adding 1.3 or more. This is with both of the programs closed, they still have services running all the time. 

This is the drop from uninstalling Corsair Icue. Unfortunately I don't have a way to control the fans from what I have found. The github fan control only reads the Commander Core, not adjust the fans.










Very slight different timings. Wish I could find something other than Icue.


----------



## The_King

TWR 16 then RTP should be 8. Else TWR 12 RTP 6.

Also RDWR 8 shows lower latency than running at 10 in your last screenshot. 

RDWR 7 can work on some DIIMMs with CL14.


----------



## HEYY0M1KEY

The_King said:


> TWR 16 then RTP should be 8. Else TWR 12 RTP 6.
> 
> Also RDWR 8 shows lower latency than running at 10 in your last screenshot.
> 
> RDWR 7 can work on some DIIMMs with CL14.




Updated my timings so it matched my original 55 ns timings to show the drop from Corsair Icue. Processes have more of an impact than I thought.

Thank you for pointing out the incorrect relationship there. I will update that. Now if I could just replace Icue. Time to work on my GDM off profile.

@aditrex I just learned the impact of these two software programs, Icue and Ryzen Master. I would assume you have software increasing latency similar to mine. Now I have to reinstall Icue and goodbye to 53 latency.


----------



## Luggage

HEYY0M1KEY said:


> I was wondering on my own results as well. I uninstalled Ryzen Master, which was adding 3 ns of latency. Corsair Icue was adding 1.3 or more. This is with both of the programs closed, they still have services running all the time.
> 
> This is the drop from uninstalling Corsair Icue. Unfortunately I don't have a way to control the fans from what I have found. The github fan control only reads the Commander Core, not adjust the fans.
> 
> View attachment 2574020
> 
> 
> Very slight different timings. Wish I could find something other than Icue.
> 
> View attachment 2574021


What service is RM running? Can't find anything logically named...


----------



## ManniX-ITA

Luggage said:


> What service is RM running? Can't find anything logically named...


No service, there's a device driver that can be uninstalled with Sysinternals Autoruns: AMDRyzenMasterV_xx_

Everyone should inspect regularly the list of the device drivers loaded.
Even when something is uninstalled, it can leave a device driver installed.
Often it's because of sloppy coding, sometimes because Windows doesn't allow the removal (it's Windows) and others cause there's a valid reason.

Most device drivers for peripherals only get loaded if needed.
Some others they get loaded anyway and can cause all sort of troubles, slowdowns and weird crashes.

Many chinese utilities they leave dozens of device drivers installed.
Mostly not harmful by intention but harmful cause poorly coded.
They can be often exploited for this reason by a threat actor.

Remove all motherboard software unless you really, really, need it.
Scout for device drivers with board manufacturers anmes like: ASUS AsusGIO2, GIGAVYTE gdrv, gdrv2, ASROCK AsDrv102, MSI NTIOLib_OcKit, etc
This is just a quick list of those I've removed in the past, there are many many more.

Remove RGB software if you want to get back 5% of your CPU and increase boost, nothing new.
To really recover the lost performances, make sure you remove the driver.
There's mostly one OEM driver: EneIO, EneTechIO.
Some brands they rename it with their company or product line name so you have to find it yourself.

Remove device drivers for external devices or software you are not going to use again.

Be careful not to remove anything you don't know about.
Otherwise software, peripherals could not work or the system not boot up again.
Make a backup with system restore and a full system image backup before you do any change.


----------



## Robby37

The_King said:


> TWR 16 then RTP should be 8. Else TWR 12 RTP 6.
> 
> Also RDWR 8 shows lower latency than running at 10 in your last screenshot.
> 
> RDWR 7 can work on some DIIMMs with CL14.


But don't you need rtp to be factor of trfc?


HEYY0M1KEY said:


> Updated my timings so it matched my original 55 ns timings to show the drop from Corsair Icue. Processes have more of an impact than I thought.
> 
> Thank you for pointing out the incorrect relationship there. I will update that. Now if I could just replace Icue. Time to work on my GDM off profile.
> 
> @aditrex I just learned the impact of these two software programs, Icue and Ryzen Master. I would assume you have software increasing latency similar to mine. Now I have to reinstall Icue and goodbye to 53 latency.
> 
> View attachment 2574022


Just go 2t no gdm and nothing else you should do better j am getting 57xxx at 3733 so far and think I can get 58xxx latency tbh does not look bad to me . But you are click stretching your l3


----------



## Robby37

The_King said:


> TWR 16 then RTP should be 8. Else TWR 12 RTP 6.
> 
> Also RDWR 8 shows lower latency than running at 10 in your last screenshot.
> 
> RDWR 7 can work on some DIIMMs with CL14.


Also why jump twr from 16 to 12 and no 14 ? I'm wondering if I should not be running 14 twr with my cl14 timings


----------



## The_King

Robby37 said:


> Also why jump twr from 16 to 12 and no 14 ? I'm wondering if I should not be running 14 twr with my cl14 timings


With B-die and GDM off ideally you should be running TWR 10 and RTP 5

With GDM enabled TWR/RTP 10/6 or 12/6 sometimes 12/8


----------



## walczak

Got 3866mhz stable on b350 using dual ranked d-die


----------



## Anhphe93

walczak said:


> Got 3866mhz stable on b350 using dual ranked d-die
> View attachment 2574048


D-die of what?


----------



## HEYY0M1KEY

Robby37 said:


> But don't you need rtp to be factor of trfc?
> Just go 2t no gdm and nothing else you should do better j am getting 57xxx at 3733 so far and think I can get 58xxx latency tbh does not look bad to me . But you are click stretching your l3


Here is my furthest on GDM off 2T. The latency was high when I tested, which I found to be because of Ryzen Master. So that program is gone as I was only using it to check if a curve was being applied. RTP needs to be 6, that's just an error on my part. I'll try TWR 10 RTP 5 later. I'll have to research the L3 stretching and a possible cause. I am running ClkDrvStr at 60 as I haven't been able to run lower without errors,crashes,etc while running GDM off.











@Luggage 
@ManniX-ITA Appreciate the clarification on driver issues. You know a lot more than I do. I only noticed the change since it was quite the increase and I had just installed Ryzen Master to check if a curve was actually applied. Also, thank you for your YouTube video on curve optimizer. That is helping me figure out an appropriate curve.


----------



## walczak

Anhphe93 said:


> D-die of what?


Samsung ddie


----------



## Tobiman

rjatlsj said:


> View attachment 2573750
> 
> View attachment 2573751
> 
> View attachment 2573752
> 
> 
> Hello all, this is my first time writing
> 
> I want to know how to make tphyrdl 26 in 4000 cl13. Please give me a lot of advice
> 
> vsoc ccd iod vddp pll voltages have been modified to avoid WHEA errors at 4000 clock
> 
> Thanks for reading !


What heatsink do you have on that setup?


----------



## Anhphe93

walczak said:


> Samsung ddie


Wait!!!! I also use samsung d-die. How do you have such low TRFC?


----------



## rjatlsj

Tobiman said:


> What heatsink do you have on that setup?


Hello
Its xigmatek dragoon n422 heatsink


----------



## Audioboxer

Keeping an eye on the 13900k this month, considering these intel chips support DDR4, I might take a detour off AMD for a while. Still think DDR5 needs another year or so in the oven.


----------



## Tobiman

rjatlsj said:


> Hello
> Its xigmatek dragoon n422 heatsink


Thanks for the quick reply. I hope someone is able to assist you in your endeavors.


----------



## KedarWolf

My new EVGA X570 Dark gets a much better CO curve. 

Memory exactly the same though, with minor adjustments on the ProcODT and a few other tweaks. Timings exactly the same though. 

I think it's just the limits of my IMC and I had them tweaked as much as possible on my MSI board.










Shaved more than a second off my best y-cruncher.










TM5, Core Cycler 720-720 FFTs SSE, y-cruncher HNT and FFT stress tests and Linpack XTreme 1.1.5 stable.









BIOS settings in the Imgur link.



http://imgur.com/a/biaQdPB


----------



## SneakySloth

KedarWolf said:


> My new EVGA X570 Dark gets a much better CO curve.
> 
> Memory exactly the same though, with minor adjustments on the ProcODT and a few other tweaks. Timings exactly the same though.
> 
> I think it's just the limits of my IMC and I had them tweaked as much as possible on my MSI board.
> 
> View attachment 2574254
> 
> 
> Shaved more than a second off my best y-cruncher.
> 
> View attachment 2574256
> 
> 
> TM5, Core Cycler 720-720 FFTs SSE, y-cruncher HNT and FFT stress tests and Linpack XTreme 1.1.5 stable.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> BIOS settings in the Imgur link.
> 
> 
> 
> http://imgur.com/a/biaQdPB


I've found y-cruncher all core C17 to be a great test as well for stability. I had to reduce some of my -30 cores to sub -20 to stop them from erroring out. C17 , X amount of hours, All cores.


----------



## KedarWolf

SneakySloth said:


> I've found y-cruncher all core C17 to be a great test as well for stability. I had to reduce some of my -30 cores to sub -20 to stop them from erroring out. C17 , X amount of hours, All cores.


I'm running C17 now, Run Forever, no time limit.


----------



## HEYY0M1KEY

GDM off 2T best performance and stable so far. Anyone more experienced see anything wrong or possible improvements? 

Now I need to work on my PBO curve more, trying to break 16,000 in CB23. First two cycles start at 16,100 but end on the 10 minute run at 15,900ish.


----------



## HEYY0M1KEY

KedarWolf said:


> My new EVGA X570 Dark gets a much better CO curve.
> 
> Memory exactly the same though, with minor adjustments on the ProcODT and a few other tweaks. Timings exactly the same though.
> 
> I think it's just the limits of my IMC and I had them tweaked as much as possible on my MSI board.
> 
> View attachment 2574254
> 
> 
> Shaved more than a second off my best y-cruncher.
> 
> View attachment 2574256
> 
> 
> TM5, Core Cycler 720-720 FFTs SSE, y-cruncher HNT and FFT stress tests and Linpack XTreme 1.1.5 stable.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> BIOS settings in the Imgur link.
> 
> 
> 
> http://imgur.com/a/biaQdPB


That's a nice Motherboard. Would like one myself. I feel like I may need to look into bios settings as you have a lot more changed, such as C states and DF, Memory clear, Power supply idle, Perfecters, DFE/FFE training, and memory interleaving. I know many of those show on advanced DRAM Calculator. I still have those on Auto.


----------



## KedarWolf

HEYY0M1KEY said:


> That's a nice Motherboard. Would like one myself. I feel like I may need to look into bios settings as you have a lot more changed, such as C states and DF, Memory clear, Power supply idle, Perfecters, DFE/FFE training, and memory interleaving. I know many of those show on advanced DRAM Calculator. I still have those on Auto.


My y-cruncher is like a second better with the extra tweaks.


----------



## KedarWolf

SneakySloth said:


> I've found y-cruncher all core C17 to be a great test as well for stability. I had to reduce some of my -30 cores to sub -20 to stop them from erroring out. C17 , X amount of hours, All cores.


I find OCCT CPU tests, Linpack XTreme and y-cruncher will get errors in cores if my memory isn't fully stable. C17 running like 30 minutes, zero errors.


----------



## HEYY0M1KEY

KedarWolf said:


> My y-cruncher is like a second better with the extra tweaks.


Thanks! I'll look into them. Currently running Y-cruncher C17 trying to find errors on my curve. Y-Cruncher seems to be faster on finding errors than P95, unless i'm just not trying the right settings.


----------



## KedarWolf

HEYY0M1KEY said:


> Thanks! I'll look into them. Currently running Y-cruncher C17 trying to find errors on my curve. Y-Cruncher seems to be faster on finding errors than P95, unless i'm just not trying the right settings.
> View attachment 2574267


Make a file in Notepad++, memtest.cfg add the below settings.



Code:


//  y-cruncher Configuration File
//  Version: 0.7.8 Build 9507
//
//  Load this from y-cruncher or run directly:
//      y-cruncher config filename.cfg
//
//  If you're copying Windows file paths into here, be sure to replace
//  all backslashes "\" with forward slashes "/". Backslash is an
//  escape character.
//

{
    Action : "StressTest"
    StressTest : {
        AllocateLocally : "true"
        LogicalCores : [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31]
        TotalMemory : 28991029248
        SecondsPerTest : 360
        SecondsTotal : 14400
        StopOnError : "false"
        Tests : [
            "FFT"
            "HNT"
            "C17"
        ]
    }
}

Then right-click on y-cruncher.exe Send To Desktop As Shortcut.

Right-click on the shortcut, choose Properties, and add the below.

Right-click the shortcut Run As Admin.

Oh, that's for 32GB of RAM. Use an online GB to bytes converter to get the number for your RAM amount. You want it about 3GB below your max RAM.


----------



## KedarWolf

Also, Core Cycler uses Prime95 and 720-720 FFTs SSE really good at finding errors. Test all cores and let it run overnight, 6M per core.









CoreCycler - tool for testing Curve Optimizer settings


It's not good. It'll tell you you can do all core -30 and that's just not true. Yes it's pretty sloppy. But at least it gave me a hint. Went down more or less 2 to 4 counts on all cores to get it stable and one core 10-15, it was really unstable. I can't do -30 even on Windows at FCLK 1900...




www.overclock.net


----------



## KedarWolf

SneakySloth said:


> I've found y-cruncher all core C17 to be a great test as well for stability. I had to reduce some of my -30 cores to sub -20 to stop them from erroring out. C17 , X amount of hours, All cores.


I ran C17 for an hour with no errors. No time limit, run forever. I just stopped it to do other things with my PC.


----------



## museoo

Hello, I got a new PC this time. So I reached this thread to try overclocking.

The specifications of my PC are as follows

Ryzen 5600x
Cheap DDR4 Hynix CJR Die 8Gb*2
Asus TUF B450M-PRO Gaming
Radeon RX6600

So, First, set the CPU's PBO power limit to the motherboard and ran low frequency memory overclocking. So I Set VDIMM 1.43V.

The target was 3200mhz and the tCL value was reduced as much as possible to reach 15.

However, for the tRCDRD value, setting it lower than 19 resulted in a #6 error in the TM5 1usmus config.

So I fixed the tRCDRD to 19 and set the remaining values by referring to XMP memory and this thread.

As a result, I got the same result as the picture, is there anything else I can do here? What I am curious about is how to adjust the SCL and tRDWR/tWRRD values, tCKE values, and SD and DD values. Once I find the perfect timing to operate at low frequencies, i am going to try high frequencies. Who wants to help?


----------



## HEYY0M1KEY

KedarWolf said:


> Make a file in Notepad++, memtest.cfg add the below settings.
> 
> 
> 
> Code:
> 
> 
> //  y-cruncher Configuration File
> //  Version: 0.7.8 Build 9507
> //
> //  Load this from y-cruncher or run directly:
> //      y-cruncher config filename.cfg
> //
> //  If you're copying Windows file paths into here, be sure to replace
> //  all backslashes "\" with forward slashes "/". Backslash is an
> //  escape character.
> //
> 
> {
> Action : "StressTest"
> StressTest : {
> AllocateLocally : "true"
> LogicalCores : [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31]
> TotalMemory : 28991029248
> SecondsPerTest : 360
> SecondsTotal : 14400
> StopOnError : "false"
> Tests : [
> "FFT"
> "HNT"
> "C17"
> ]
> }
> }
> 
> Then right-click on y-cruncher.exe Send To Desktop As Shortcut.
> 
> Right-click on the shortcut, choose Properties, and add the below.
> 
> Right-click the shortcut Run As Admin.
> 
> Oh, that's for 32GB of RAM. Use an online GB to bytes converter to get the number for your RAM amount. You want it about 3GB below your max RAM.
> 
> View attachment 2574268


Thank you! I will give both of those a shot. Going back in forth between CO and Ram.


----------



## Valka814

Ohh no! RttNom at 7->error #3. Disabled->error #2.


----------



## byDenoso

My new result, 2x8 SR Hynix DJR
I just love the cache performance between read/write (almost equal)
Any suggestions?


----------



## Robby37

HEYY0M1KEY said:


> GDM off 2T best performance and stable so far. Anyone more experienced see anything wrong or possible improvements?
> 
> Now I need to work on my PBO curve more, trying to break 16,000 in CB23. First two cycles start at 16,100 but end on the 10 minute run at 15,900ish.
> View attachment 2574264


Bet trdwr down one even if need to raise rd 1 would get more bandwidth.


----------



## Robby37

museoo said:


> Hello, I got a new PC this time. So I reached this thread to try overclocking.
> 
> The specifications of my PC are as follows
> 
> Ryzen 5600x
> Cheap DDR4 Hynix CJR Die 8Gb*2
> Asus TUF B450M-PRO Gaming
> Radeon RX6600
> 
> So, First, set the CPU's PBO power limit to the motherboard and ran low frequency memory overclocking. So I Set VDIMM 1.43V.
> 
> The target was 3200mhz and the tCL value was reduced as much as possible to reach 15.
> 
> However, for the tRCDRD value, setting it lower than 19 resulted in a #6 error in the TM5 1usmus config.
> 
> So I fixed the tRCDRD to 19 and set the remaining values by referring to XMP memory and this thread.
> 
> As a result, I got the same result as the picture, is there anything else I can do here? What I am curious about is how to adjust the SCL and tRDWR/tWRRD values, tCKE values, and SD and DD values. Once I find the perfect timing to operate at low frequencies, i am going to try high frequencies. Who wants to help?
> 
> View attachment 2574275


Trrdl 7 and try maybe tcke 6 for 3200 mhz . Also trdwr is usually half trcd avg then 4 sticks single add 1 , dual rank and 2, 4 dr add 3 or 4 . That's starting point . Twrrd is more complicated but if running perfect half with no leftover then 1 . Or if running below half then need the leftover timing covered . Usually most need to add some for stability but it's better to reduce rw amd have higher rd . Scl x rd should not be more than trcd as well


----------



## HEYY0M1KEY

Robby37 said:


> Bet trdwr down one even if need to raise rd 1 would get more bandwidth.


Thanks. I know 12,2 is what got Tphyrdl to 7. 9,2 doesn’t post. I’ll try 9,3 tonight before I run y-cruncher. I also need to look if any bios settings would improve performance a little. Want to hit 52 or even 51 on latency with 57K read.


----------



## xpulse

Hi OverClockers,
Is anyone of you have expirience with overclocking this RAM, this is DOHC/XMP settings no tweaks at all.
CPU overclocked to 4.5Ghz.









Any ideas will be helpful...









These settings I got via calculator

Thanks!


----------



## KedarWolf

HEYY0M1KEY said:


> GDM off 2T best performance and stable so far. Anyone more experienced see anything wrong or possible improvements?
> 
> Now I need to work on my PBO curve more, trying to break 16,000 in CB23. First two cycles start at 16,100 but end on the 10 minute run at 15,900ish.
> View attachment 2574264


Go to File, enable Advanced Benchmark, and set Minimum Test Duration to Off, it'll only run once.


----------



## Robby37

xpulse said:


> Hi OverClockers,
> Is anyone of you have expirience with overclocking this RAM, this is DOHC/XMP settings no tweaks at all.
> CPU overclocked to 4.5Ghz.
> 
> View attachment 2574387
> 
> Any ideas will be helpful...
> 
> View attachment 2574430
> 
> These settings I got via calculator
> 
> Thanks!


Those settings are no good for zen 3 and have been found way off for voltages as well . If you search posts by veii their are bunch good guides in this thread on all diff ram setups . Everyone little \diff but start with one of his baselines as low voltage as p[possible and then slowly work up .


----------



## The_King

This is the lowest bin Micron Rev. E I have. (C9BJZ) Crucial 3200 CL 16-18-18-36.


















Same Kit @ 4000 CL16


----------



## ElysianCloud

To my (limited) knowledge, this is the furthest I can push these sticks. They're 4x8 b-die running at 1.51v. Not sure how I could possibly get latency any lower


----------



## Robby37

ElysianCloud said:


> To my (limited) knowledge, this is the furthest I can push these sticks. They're 4x8 b-die running at 1.51v. Not sure how I could possibly get latency any lower
> View attachment 2574520
> View attachment 2574521











쿨엔조이,쿨앤조이 coolenjoy, cooln, 쿨엔, 검은동네


출처 Veii 님https://www.overclock.net/forum/28385690-post3279.htmlhttps://www.overclock.net/forum/28385



coolenjoy.net


----------



## 97pedro

What do you guys think of the patriot blackout series?

These specifically PVB416G413C8K.

They are dirt cheap at 100€ new from Patriot's Amazon store.

Anyone has any experience with them?


----------



## The_King

97pedro said:


> What do you guys think of the patriot blackout series?
> 
> These specifically PVB416G413C8K.
> 
> They are dirt cheap at 100€ new from Patriot's Amazon store.
> 
> Anyone has any experience with them?


IT's rated 4133 18-22-22-42 Highly unlikely to be Samsung B-die! Thats a hard NO from me.


https://assets.website-files.com/5cdb2ee0b102f96c3906500f/5f4e5ef1d8ee7a75f16a18b1_PVB416G413C8K%20Sku%20Sheet_%20080320.pdf




The best Patriot ram to get IMHO is the Patriot Viper Steel *4000 CL16* usually goes for around $99 when on Sale.


----------



## 97pedro

The blackout supposably are b die that's the thing


----------



## The_King

97pedro said:


> The blackout supposably are b die that's the thing


The only guranteed B-die Blackout is this PVB416G400C9K. The other blackout series can be anything.


----------



## Bix

97pedro said:


> The blackout supposably are b die that's the thing











[Übersicht] - Die ultimative HARDWARELUXX Samsung 8Gb B-Die Liste - alle Hersteller (09.01.23)


Die ultimative HARDWARELUXX Samsung 8Gbit B-Die Liste Inhaltsverzeichnis / Table of Contents » 8GB Module & 2x8GB/4x8GB/8x8GB Kits (SS, SR) » 16GB Module & 2x16GB/4x16GB/8x16GB Kits (DS, DR) » 32GB Module & 2x32GB Kits (DC DIMM) » SO-DIMM 8GB/16GB Varianten (SR/DR) » Häufig gestellte Fragen...




www.hardwareluxx.de





Looks like a no.


----------



## 97pedro

This is mainly asthetics, I'm looking for a complete blacked out build and the blackout series blends in much better than the viper steel


----------



## Bix

97pedro said:


> This is mainly asthetics, I'm looking for a complete blacked out build and the blackout series blends in much better than the viper steel


If you want to go with the Blackouts then it looks like PVB416G400C9K (4000 19-19-19-39) are your only option.


----------



## koji

Yo guys, anyone got a 4x8 set C1 GDM OFF stable on a Crosshair board? Aiming around 1900/3800. Thing is being a right PITA... Currently running a C2 GDM OFF but I'm kinda chasing that unicorn... (5800X3D on a Crosshair Dark Hero)


----------



## Robby37

wonder if trident neo is really any better for ryzen then reg or if its just diff stored timings on the rom


----------



## Robby37

@Veii can you post or share a copy of the ruzen calculator ? I'll host on my server if helps . It's been locked for a while but I think can help alot of people .


----------



## HEYY0M1KEY

KedarWolf said:


> Go to File, enable Advanced Benchmark, and set Minimum Test Duration to Off, it'll only run once.


Thanks. Cinebench R23 at 16,022 and 1,646 for the 10 minute cycle. I posted a screenshot it in the CoreCycler thread.

Haven't figured out tRDWR/RRD yet, that's on the to do list. I managed to break into the 52 ns. 

I'm mostly curious on the clock stretching you, correction @Robby37 mentioned that. From what I have read 5,000 should be around 10.2 ns on L3 cache. I have ran Boost Tester and all cores boost to 5K. I've tried incread cTDP and Package Power, PPT,TDC, and EDC with no luck. Also have tried different power plans from @ManniX-ITA.

Any ideas on how to troubleshoot? Maybe it's bios or possibly powering related?


----------



## Silvio1

Hello fellow clockers. I'm trying to tune my 2x8 Ballistix E-Die 3600 CL16, currently, I'm stable on this setup (Ante777 extreme, error free though 3 cycles), tried RD to 17 but still was crashing (actually it was not crashing, after few mins of stress test was getting errors but I take that as crash) even with 1.5v at DRAM and higher SOC voltage. But, I'm playing competitive games at low res (mostly 1440x1080) at low settings and playing mostly fps games (bf, cod, rust and etc) and for this type of games I'm better of dropping the freq to 3600 and tighten the timings as much as I can. So GDM is off and its set on 1T at 1.48v. Does someone has any E-die setup with tight timings at 3600mhz ?


----------



## The_King

Crucial 3600 CL 16-18-18-38-58 (C9BLM) 8GB SR. Micron Rev E

4133 CL16

















3800 CL14

















3800 CL16 @ 1.45v Seems I forgot do do an AIDA64 for this one.










EDIT:
Looks like 1.51V was not needed on this kit it only needed 1.37V to boot and 1.46V to pass 4133 CL16


----------



## StrongForce

Nighthog said:


> Gotten 2066FCLK working if you overlook the WHEA reported errors as they seem to have no impact on stability/performance when you start fiddling with the FCLK in length on 5800X3D.
> The amount of errors seems to stay in the ballpark the same regardless of FCLK on my sample so just went for how far I could push it.
> The main cause of issues was USB dropouts & audio stutter, USB issue was solved by increasing voltages like VDD18 and VDDG_IOD while Audio stutter mainly also needed more VDDG_CCD than I was trying to do for most part with decent enough of *SoC voltage* around *~1.300V* for all around good results.
> *VDD18* was a surprise on being needed so much as I did end up using, *2.120V* for the USB & audio stutter I encountered @ 2066FCLK.


Just lurking in this thread.. I have been encountering weird crashes with my windows, the explorer or bar at the bottom crash, I can still use the PC for a bit, but I just force restart, ctrl alt del doesn't work, I tried running the sfc scannow command and also DISM scanhealth and no issue (2 month fresh install) the first thing I was suspecting was the memory since I have been tweaking a bit, even though I ran 2 tests one of 12h prime 95 memory setting and even 19 hours of prime 95, just to make sure I was perfectly fine.. so now I'm reading this I'm thinking, could this be eventually caused by an unstable FCLK or something ?? even though ram is stable 100% this could still somehow freeze windows when its acting unstable..

I can play games for hours without issue, always happens in windows.. anyways I know it's not the subject of the thread but just thought I'd mention it.. I also read somewhere it could be linked to using some optimized settings in the bios, I actually turned on a setting "Asus performance mode" I thought it was just a bit of a power limit, like I seen in those benchmarks that said "power limit removed" but yeah.. now I read your post I'm thinking my crashes might be linked to bad FCLK mmh maybe I'm onto something, maybe not..but just wondering if maybe some people experienced similar things, could be definitely linked to RAM OC / Optimized settings.

As for overclocking RAM think I'm gonna stick to my current settings for now, if I upgrade in the future for a "budget" option it might be for 2 more of the same sticks of ram, get that 4x 8gb dual rank juice and eventually a 5800x3d, so I would definitely spend some times tweaking the subtimings, I realized if I do it now I might have to redo it later and since it seems pretty time consuming.. and also with those issues I been having it's a bit discouraging to try to tweak even more, but yeah, if I fix my issues I might be tempted to try to OC the subtimings a bit, just to practice


----------



## Nighthog

StrongForce said:


> Just lurking in this thread.. I have been encountering weird crashes with my windows, the explorer or bar at the bottom crash, I can still use the PC for a bit, but I just force restart, ctrl alt del doesn't work, I tried running the sfc scannow command and also DISM scanhealth and no issue (2 month fresh install) the first thing I was suspecting was the memory since I have been tweaking a bit, even though I ran 2 tests one of 12h prime 95 memory setting and even 19 hours of prime 95, just to make sure I was perfectly fine.. so now I'm reading this I'm thinking, could this be eventually caused by an unstable FCLK or something ?? even though ram is stable 100% this could still somehow freeze windows when its acting unstable..
> 
> I can play games for hours without issue, always happens in windows.. anyways I know it's not the subject of the thread but just thought I'd mention it.. I also read somewhere it could be linked to using some optimized settings in the bios, I actually turned on a setting "Asus performance mode" I thought it was just a bit of a power limit, like I seen in those benchmarks that said "power limit removed" but yeah.. now I read your post I'm thinking my crashes might be linked to bad FCLK mmh maybe I'm onto something, maybe not..but just wondering if maybe some people experienced similar things, could be definitely linked to RAM OC / Optimized settings.
> 
> As for overclocking RAM think I'm gonna stick to my current settings for now, if I upgrade in the future for a "budget" option it might be for 2 more of the same sticks of ram, get that 4x 8gb dual rank juice and eventually a 5800x3d, so I would definitely spend some times tweaking the subtimings, I realized if I do it now I might have to redo it later and since it seems pretty time consuming.. and also with those issues I been having it's a bit discouraging to try to tweak even more, but yeah, if I fix my issues I might be tempted to try to OC the subtimings a bit, just to practice


Unstable FCLK can cause random issues if it's "marginal" A little voltage on the right setting might be all that is needed.
Could be the CPU cores themselves being unstable. 
We have seen quite a few CPU samples that have unstable cores stock being sold around the place.
I have a 5700G that is unstable stock unless you give it extra voltage because of a bad core. (I just haven't wanted to bother sending it back yet [RMA])
And some cores can become unstable with elevated FCLK requiring a core voltage boost to go with it unless you adjust it with [CO] Curve Optimizer.

Just using a more aggressive LLC can be enough if the cores are marginal on the edge.
My 5700G needs minimum [Medium] LLC for the bad core to be workable for general usage. Though it requires a ridiculous +10 CO setting if stress testing single core boost. That literally tanks performance to the bottom using it like that in multi-thread loads. Gimps maximum frequency by a lot. Otherwise I need to juice it with loads and loads of voltage in any OC situation to compensate.


----------



## Robby37

StrongForce said:


> Just lurking in this thread.. I have been encountering weird crashes with my windows, the explorer or bar at the bottom crash, I can still use the PC for a bit, but I just force restart, ctrl alt del doesn't work, I tried running the sfc scannow command and also DISM scanhealth and no issue (2 month fresh install) the first thing I was suspecting was the memory since I have been tweaking a bit, even though I ran 2 tests one of 12h prime 95 memory setting and even 19 hours of prime 95, just to make sure I was perfectly fine.. so now I'm reading this I'm thinking, could this be eventually caused by an unstable FCLK or something ?? even though ram is stable 100% this could still somehow freeze windows when its acting unstable..
> 
> I can play games for hours without issue, always happens in windows.. anyways I know it's not the subject of the thread but just thought I'd mention it.. I also read somewhere it could be linked to using some optimized settings in the bios, I actually turned on a setting "Asus performance mode" I thought it was just a bit of a power limit, like I seen in those benchmarks that said "power limit removed" but yeah.. now I read your post I'm thinking my crashes might be linked to bad FCLK mmh maybe I'm onto something, maybe not..but just wondering if maybe some people experienced similar things, could be definitely linked to RAM OC / Optimized settings.
> 
> As for overclocking RAM think I'm gonna stick to my current settings for now, if I upgrade in the future for a "budget" option it might be for 2 more of the same sticks of ram, get that 4x 8gb dual rank juice and eventually a 5800x3d, so I would definitely spend some times tweaking the subtimings, I realized if I do it now I might have to redo it later and since it seems pretty time consuming.. and also with those issues I been having it's a bit discouraging to try to tweak even more, but yeah, if I fix my issues I might be tempted to try to OC the subtimings a bit, just to practice


Post your zentimings . Proc can need to be upped one is another thing or vddp voltage is good for that . Also as simple as oc mode on and power down off can cause that to .


----------



## Robby37

HEYY0M1KEY said:


> Thanks. Cinebench R23 at 16,022 and 1,646 for the 10 minute cycle. I posted a screenshot it in the CoreCycler thread.
> 
> Haven't figured out tRDWR/RRD yet, that's on the to do list. I managed to break into the 52 ns.
> 
> I'm mostly curious on the clock stretching you, correction @Robby37 mentioned that. From what I have read 5,000 should be around 10.2 ns on L3 cache. I have ran Boost Tester and all cores boost to 5K. I've tried incread cTDP and Package Power, PPT,TDC, and EDC with no luck. Also have tried different power plans from @ManniX-ITA.
> 
> Any ideas on how to troubleshoot? Maybe it's bios or possibly powering related?
> 
> 
> 
> View attachment 2574625


Try safe mode just to make sure and max edc to moon just for one test . Also what is your c0 curve ?


----------



## 99belle99

This is my current daily. Is 1.46v too high, as it's 1.475v in HWinfo.


----------



## KedarWolf

I upgraded to Windows 11 22H2.

When I run TM5, every time I get to Cycle 23, without fail, I get one random error.

I'm thinking it's a Windows 11 22H2 issue with memory allocation or something. I mean I've ran it like 20 times, error on Cycle 23.









Edit: In TM5 I changed the memory allocation to 1024, just put it back the the default 128.

Second Edit: Definitely a 21H2 issue, went back to 21H1.

Pretty much the same as my Unify-X Max, except I get a quite a bit better Curve, Core Cycler, y-cruncher and Linpack XTreme stable.

And I beat my best y-cruncher benchmark by a fair amount. I posted it earlier.

Edit: FFS, I never had any settings in the CBS and PBS menu set. So I'm thinking it's something there, maybe Prefetchers disabled.


----------



## xpulse

xpulse said:


> The lowest TRC and TRFC I can boot into windows.
> 
> View attachment 2573236


Any suggestions on how possible to lower down latency?


























Thank you for any help!


----------



## Frosted racquet

@xpulse Test in Safe Mode to see if some background program is causing high latency


----------



## 99belle99

xpulse said:


> Any suggestions on how possible to lower down latency?
> 
> View attachment 2575134
> View attachment 2575135
> 
> View attachment 2575136
> 
> 
> 
> Thank you for any help!


Get rid of two sticks of RAM...


----------



## Silvio1

xpulse said:


> Any suggestions on how possible to lower down latency?
> 
> View attachment 2575134
> View attachment 2575135
> 
> View attachment 2575136
> 
> 
> 
> Thank you for any help!


Yap, try safe mode as Frosted suggested. I've got pretty much same ram (mine is E-die tho) but a bit tighter settings with 5600X and I've had ~61ns no matter what, in safe mode I always had 55.5ns. After that I said **** it and did clean install of win11, after that I'm every single run at 55.5 without safemode.


----------



## DvL Ax3l

Hi guys, I'm trying to figure why I can't stabilize those primaries:
tRCDRD 14
tRP 14
tRAS 28
tRC 42
Any tips/trick to try?

At the moment I'm using those settings @ 1.505V, rock stable testmem5 anta extreme.
I'm using CLDO_VDDP @ 1.100 because it will match both A/B channel tPHYRDL 26













Anyway this is my RAM kit, not a good binned B-Die, but I've already squize them a lot


----------



## The Sandman

DvL Ax3l said:


> Hi guys, I'm trying to figure why I can't stabilize those primaries:
> tRCDRD 14
> tRP 14
> tRAS 28
> tRC 42
> Any tips/trick to try?
> 
> At the moment I'm using those settings @ 1.505V, rock stable testmem5 anta extreme.
> I'm using CLDO_VDDP @ 1.100 because it will match both A/B channel tPHYRDL 26
> Anyway this is my RAM kit, not a good binned B-Die, but I've already squize them a lot


I can't help with lowering tRCDRD to 14 (i'm currently in the same boat) It's not easy lol.
If you can't get tRCDRD to 14 with GDM enabled you'll see better performance running tRCDRD at 16, it may also allow a little tighter tRAS and tRP. 
GDM enabled won't allow odd values and auto corrects
You can test this using YCruncher Pi Benchmark before and after (15-16)
You can also try lowering CCD to .900 and IOD to 1.020

Here's my 4 x 8GB SR B-Die @ 1.48v in Bios if it's of any help


----------



## DvL Ax3l

The Sandman said:


> I can't help with lowering tRCDRD to 14 (i'm currently in the same boat) It's not easy lol.
> If you can't get tRCDRD to 14 with GDM enabled you'll see better performance running tRCDRD at 16, it may also allow a little tighter tRAS and tRP.
> GDM enabled won't allow odd values and auto corrects
> You can test this using YCruncher Pi Benchmark before and after (15-16)
> You can also try lowering CCD to .900 and IOD to 1.020
> 
> Here's my 4 x 8GB SR B-Die @ 1.48v in Bios if it's of any help
> View attachment 2575158
> 
> 
> View attachment 2575159


I'll try it, anyway u got tPHYRDL 26 on all 4 sticks with CLDO_VDDP 0.86 ?


----------



## The Sandman

DvL Ax3l said:


> I'll try it, anyway u got tPHYRDL 26 on all 4 sticks with CLDO_VDDP 0.86 ?


Yes without issue.


----------



## Blackfyre

99belle99 said:


> This is my current daily. Is 1.46v too high, as it's 1.475v in HWinfo.
> 
> View attachment 2574936


Some of us have been running 1.5v+ for a couple of years, others probably longer and higher voltages. As long as you have air going past the memory (_doesn't need to be directly on top of it_), you can push for higher voltages, because HEAT errors will show when you are stress testing. As long as you are stress testing properly and know it's stable, then it's stable. If you set your timings in winter, test them again in summer on a really hot day and do another stress test.

Looks like you have b-die, you should be able to hit 3800Mhz with similar timings.


----------



## The_King

Crucial Ballistix MAX 4400 C19 8GB SR (C9BLM) Micron Rev E
@Taraquin 3933 CL16 RCD 17 @ 1.46V


----------



## DvL Ax3l

The Sandman said:


> I can't help with lowering tRCDRD to 14 (i'm currently in the same boat) It's not easy lol.
> If you can't get tRCDRD to 14 with GDM enabled you'll see better performance running tRCDRD at 16, it may also allow a little tighter tRAS and tRP.
> GDM enabled won't allow odd values and auto corrects
> You can test this using YCruncher Pi Benchmark before and after (15-16)
> You can also try lowering CCD to .900 and IOD to 1.020
> 
> Here's my 4 x 8GB SR B-Die @ 1.48v in Bios if it's of any help
> View attachment 2575158
> 
> 
> View attachment 2575159


So I've tried your settings and seems everything stable, thanks for your tips.
As for tRCDRD it's the culript of the instability, can't go lower 15, if I set it 14 start throwing a lot of errors during testmem5, I really don't understand why, someone else have other tips? xD
I'm stable with those settings.









The Sandman said:


> Yes without issue.


Anyway for CLDO_VPP a need at least 1.080V otherwise tPHYRDL become 26/28.


----------



## Nighthog

The_King said:


> Crucial Ballistix MAX 4400 C19 8GB SR (C9BLM) Micron Rev E
> @Taraquin 3933 CL16 RCD 17 @ 1.46V
> View attachment 2575230


Have you tried GDM: Disabled yet?
Seems you got a good pair of the Ballistix 4400 CL19 kit. Might not work @ 17 tRCD but should check. These are easy to run 1T GDM: Disabled. (they do so @ 5000Mts with appropriate timings)


----------



## The_King

Nighthog said:


> Have you tried GDM: Disabled yet?
> Seems you got a good pair of the Ballistix 4400 CL19 kit. Might not work @ 17 tRCD but should check. These are easy to run 1T GDM: Disabled. (they do so @ 5000Mts with appropriate timings)


GDM disabled 1T is very easy to get on all my Micron kits.
This profile however is very "specific" and does not seem to like GDM off at all. If I change RCDRD to 18 it does GDM off without even adding any voltages and is stable.










The key / secret to getting RCDRD -1 to work is setting the correct TRFC1/2/3 and RC
I got this profile / setting from AIDA64 SPD TAB.









Also it seems dropping your TRFC on Micron Rev .E Kits it not a good idea has lower is not better like with Samsung B-die


----------



## mus1mus

Anyone keen on helping Overclock.net Overclocking Team in the on-going HWBOT Team Cup? 

Those who have a* (especially) *Ryzen 5950X, have been registered to hwbot and can join Overclock.net Team, we need your help in running 3DMark CPU Profile Max. 

Link for the Competition Round Overclocking eSports - oc-esports.io

A valid score will help the team in terms of the rankings in the said competition. 


Thanks,


----------



## KedarWolf

mus1mus said:


> Anyone keen on helping Overclock.net Overclocking Team in the on-going HWBOT Team Cup?
> 
> Those who have a* (especially) *Ryzen 5950X, have been registered to hwbot and can join Overclock.net Team, we need your help in running 3DMark CPU Profile Max.
> 
> Link for the Competition Round Overclocking eSports - oc-esports.io
> 
> A valid score will help the team in terms of the rankings in the said competition.
> 
> 
> Thanks,


I only run in the water cooling Enthusiast category.

I took a look and can't compete with peeps hitting 6000MHz on their 5950x.


----------



## mus1mus

Ohh man, was about to PM you after looking at tyour Ryzen 7000 Thread. 

At this moment, any score will be of great help and appreciated. We lack the said SKU soooo... yeah.. 

Would really help if you can have a run at it. 

Thanks man 😇


----------



## rissie

DvL Ax3l said:


> So I've tried your settings and seems everything stable, thanks for your tips.
> As for tRCDRD it's the culript of the instability, can't go lower 15, if I set it 14 start throwing a lot of errors during testmem5, I really don't understand why, someone else have other tips? xD
> I'm stable with those settings.
> View attachment 2575235
> 
> 
> Anyway for CLDO_VPP a need at least 1.080V otherwise tPHYRDL become 26/28.


I needed 1.53V on mine to do straight 14s, 7 3 3 and 1T with GDM off on just stock air for more than a year. Right now, I'm running 1.64V at cl 13 but with a waterblock. My sticks are Corsair B die... it's badly binned at 3200 C16 so I did get quite a bit out of it.

Check your PCB version, I do remember that you need to take care on the Voltage with certain settings if you're on older PCBs when a few folks killed their sticks due to certain settings but most sticks should do fine above 1.5V even on air.


----------



## DvL Ax3l

rissie said:


> I needed 1.53V on mine to do straight 14s, 7 3 3 and 1T with GDM off on just stock air for more than a year. Right now, I'm running 1.64V at cl 13 but with a waterblock. My sticks are Corsair B die... it's badly binned at 3200 C16 so I did get quite a bit out of it.
> 
> Check your PCB version, I do remember that you need to take care on the Voltage with certain settings if you're on older PCBs when a few folks killed their sticks due to certain settings but most sticks should do fine above 1.5V even on air.


According to Thaiphoon Burner my kit it's A0, anyway I've tried to bump the voltage up to 1.55V to stabilize tRCDRD 14 and got nothing, maybe I need to try differents termination/cad_bus value?

EDIT: So appartently, I found the culript, it's 1 stick that cannot go tRCDRD 14, for boot it I need to move it to the B1 slot otherwise cannot post... I'll try RMA


----------



## Valka814

Still no success yet.


----------



## SneakySloth

Valka814 said:


> Still no success yet.


Have you tried tWR 24, tRTP 12?


----------



## Bix

Valka814 said:


> Still no success yet.
> 
> View attachment 2575392
> 
> View attachment 2575393
> 
> View attachment 2575391
> 
> View attachment 2575394
> 
> View attachment 2575390


Errors after that length of time might be due to a core being slightly unstable. Try adding a little positive vCore offset or positive CO just to see - I had to reduce the negative curve on a number of my cores when changing from flat 15s to 14s and one of my cores (the best according to CPPC) needs positive CO or offset to be stable with any config.


----------



## CyrIng

Following rule tFAW = 4 x tRRD_S , tFAW is manually lowered to 16 (from a SPD-AUTO of 44)

Benchmarks (made with 7-zip and CoreFreq for UMC timings) show improvements but I wonder why G.Skill set default SPD @ 3600 MHz with tRRD_S of 4 and tFAW of 44 ?



Code:


                              Zen UMC  [1440]                             
Controller #0                                                Dual Channel 
 Bus Rate  1800 MHz       Bus Speed 1800 MHz           DDR4 Speed 3600 MT/s
                                                                          
 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   16   16   16   16   36   52    4    9   44    5   14   26    5    5
  #1   16   16   16   16   36   52    4    9   44    5   14   26    5    5
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   16   14    8    3    1    7    6    1    5    4    0    0    0    0
  #1   16   14    9    2    1    7    6    1    5    4    0    0    0    0
      REFI RFC1 RFC2 RFC4 RCPB RPPB  BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0 14029  631  469  289   0    0   OFF  ON  R1W1   0    0   1T    ON   0
  #1 14029  631  469  289   0    0   OFF  ON  R1W1   0    0   1T    ON   0
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0    8  18    27  27    24  210 0:F:0   11   2   11   26  648   11    4
  #1    8  18    27  27    24  210 0:F:0   11   2   11   26  648   11    4
                                                                          
 DIMM Geometry for channel #0                                             
      Slot Bank Rank     Rows   Columns    Memory Size (MB)               
       #0                                                                 
       #1    16    2     65536      1024          16384   F4-3600C16-16GTZN
 DIMM Geometry for channel #1                                             
      Slot Bank Rank     Rows   Columns    Memory Size (MB)               
       #0                                                                 
       #1    16    2     65536      1024          16384   F4-3600C16-16GTZN

7-Zip [64] 17.04 : Copyright (c) 1999-2021 Igor Pavlov : 2017-08-28
p7zip Version 17.04 (locale=en_US.UTF-8,Utf16=on,HugeFiles=on,64 bits,32 CPUs x64)

x64
CPU Freq: - - - - - - - - -

RAM size:   32008 MB,  # CPU hardware threads:  32
RAM usage:   7060 MB,  # Benchmark threads:     32

                       Compressing  |                  Decompressing
Dict     Speed Usage    R/U Rating  |      Speed Usage    R/U Rating
         KiB/s     %   MIPS   MIPS  |      KiB/s     %   MIPS   MIPS

22:     115365  2979   3767 112227  |    1433689  3167   3861 122264
23:     107468  2950   3712 109498  |    1414714  3168   3864 122417
24:     104377  2973   3775 112227  |    1390226  3161   3861 122024
25:     101616  2972   3905 116022  |    1373589  3176   3849 122240
----------------------------------  | ------------------------------
Avr:            2968   3790 112494  |             3168   3859 122236
Tot:            3068   3824 117365

***

                              Zen UMC  [1440]                             
Controller #0                                                Dual Channel 
 Bus Rate  1800 MHz       Bus Speed 1800 MHz           DDR4 Speed 3601 MT/s
                                                                          
 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   16   16   16   16   36   52    4    9   16    5   14   26    5    5
  #1   16   16   16   16   36   52    4    9   16    5   14   26    5    5
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   16   14    8    3    1    7    6    1    5    4    0    0    0    0
  #1   16   14    9    2    1    7    6    1    5    4    0    0    0    0
      REFI RFC1 RFC2 RFC4 RCPB RPPB  BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0 14029  631  469  289   0    0   OFF  ON  R1W1   0    0   1T    ON   0
  #1 14029  631  469  289   0    0   OFF  ON  R1W1   0    0   1T    ON   0
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0    8  18    27  27    24  210 0:F:0   11   2   11   26  648   11    4
  #1    8  18    27  27    24  210 0:F:0   11   2   11   26  648   11    4
                                                                          
 DIMM Geometry for channel #0                                             
      Slot Bank Rank     Rows   Columns    Memory Size (MB)               
       #0                                                                 
       #1    16    2     65536      1024          16384   F4-3600C16-16GTZN
 DIMM Geometry for channel #1                                             
      Slot Bank Rank     Rows   Columns    Memory Size (MB)               
       #0                                                                 
       #1    16    2     65536      1024          16384   F4-3600C16-16GTZN

7-Zip [64] 17.04 : Copyright (c) 1999-2021 Igor Pavlov : 2017-08-28
p7zip Version 17.04 (locale=en_US.UTF-8,Utf16=on,HugeFiles=on,64 bits,32 CPUs x64)

x64
CPU Freq: - - - - - - - - -

RAM size:   32008 MB,  # CPU hardware threads:  32
RAM usage:   7060 MB,  # Benchmark threads:     32

                       Compressing  |                  Decompressing
Dict     Speed Usage    R/U Rating  |      Speed Usage    R/U Rating
         KiB/s     %   MIPS   MIPS  |      KiB/s     %   MIPS   MIPS

22:     118161  2968   3873 114947  |    1431757  3162   3861 122099
23:     109554  2914   3830 111623  |    1422090  3180   3869 123055
24:     107288  2960   3897 115356  |    1382346  3142   3862 121333
25:     104956  2970   4035 119835  |    1377919  3184   3852 122626
----------------------------------  | ------------------------------
Avr:            2953   3909 115440  |             3167   3861 122278
Tot:            3060   3885 118859


----------



## DvL Ax3l

DvL Ax3l said:


> According to Thaiphoon Burner my kit it's A0, anyway I've tried to bump the voltage up to 1.55V to stabilize tRCDRD 14 and got nothing, maybe I need to try differents termination/cad_bus value?
> 
> EDIT: So appartently, I found the culript, it's 1 stick that cannot go tRCDRD 14, for boot it I need to move it to the B1 slot otherwise cannot post... I'll try RMA


A little update about the RMA, they've send me E-Die instead of B-Die so I kept mine and got 85€ refund for the fault dimm


----------



## xpulse

xpulse said:


> Any suggestions on how possible to lower down latency?
> 
> View attachment 2575134
> View attachment 2575135
> 
> View attachment 2575136
> 
> 
> 
> Thank you for any help!


In safe mode latency is 57ns. Thank you for help.


----------



## StrongForce

Robby37 said:


> Post your zentimings . Proc can need to be upped one is another thing or vddp voltage is good for that . Also as simple as oc mode on and power down off can cause that to .


Still getting those explorer freezes I really updated everything even the BIOS just to make sure, it even says on the bios "improve stabilility" so I was hoping..












Nighthog said:


> Unstable FCLK can cause random issues if it's "marginal" A little voltage on the right setting might be all that is needed.
> Could be the CPU cores themselves being unstable.
> We have seen quite a few CPU samples that have unstable cores stock being sold around the place.
> I have a 5700G that is unstable stock unless you give it extra voltage because of a bad core. (I just haven't wanted to bother sending it back yet [RMA])
> And some cores can become unstable with elevated FCLK requiring a core voltage boost to go with it unless you adjust it with [CO] Curve Optimizer.
> 
> Just using a more aggressive LLC can be enough if the cores are marginal on the edge.
> My 5700G needs minimum [Medium] LLC for the bad core to be workable for general usage. Though it requires a ridiculous +10 CO setting if stress testing single core boost. That literally tanks performance to the bottom using it like that in multi-thread loads. Gimps maximum frequency by a lot. Otherwise I need to juice it with loads and loads of voltage in any OC situation to compensate.


I ran 2 hours of prime 95 blend test, maybe it was even 3, and no issue, temps fine, even the ram is pretty low at max 37

Also I really never get blue screens and I can play for houurs without issue, so I think my CPU is stable

Should I boost the VDDP voltage ? or the VDDG CCD/IOD aswell

I have 1.15 on the VSOC, I guess it's normal to have a little Vdrop right

and You mean CPU LLC right, not sure but I think mine is currently set at default

I also reverted all my sub timings to auto, by the way, if some of the subtimings auto settings are really bad, I wouldn't mind try to at least set something not so aggressive but just at least decent, would be nice if manufacturers found a way to get better auto timings for non XMP profile.

I'll also include a little Aida64 screenshot 










57.6ns sounds pretty legit


----------



## The_King

The_King said:


> Crucial Ballistix MAX 4400 C19 8GB SR (C9BLM) Micron Rev E
> @Taraquin 3933 CL16 RCD 17 @ 1.46V
> View attachment 2575230


Had a RGB set of Crucial Ballistix MAX 4400 C19 8GB SR decided to pair it with my other non RGB kit for Dual Rank setup. (C9BLM)

@Bix Absolutely no issues booting FCLK 1900 or even higher with this Kit. Seems the problem I had was more the 4 X Vipers 4000 C19s did not play nice together on my board.
the issue is most likely related to ProcODT which never wanted to go lower than 40 with 4 X Vipers.


----------



## mus1mus

Very nice!!!

And I'm here stuck on 3800 Memory with X570 Ace..


----------



## The_King

mus1mus said:


> Very nice!!!
> 
> And I'm here stuck on 3800 Memory with X570 Ace..


Are you still running the SK Hynix kit?
My samsung B-die Kit also wont go above 3800 with 4X8GB sticks on this board.

Micron Rev.E seems to be much easier on the IMC than other kits. Busy testing this at the moment.









Updated: Can't seem to boot higher than 4067MT FCLK 2033 with 4 DIMMS. Sub timings need more tunning









Update 2. Changing some of the subtimings droped tPHYRDL from 30 above to 28 below.


----------



## 99belle99

I was on this stable for a while:










but got the urge to move up to 3800MHz. So have the below now:










are they good numbers. Pulled them from DRAM calculator.


----------



## Unifyx

99belle99 said:


> I was on this stable for a while:
> 
> View attachment 2575829
> 
> 
> but got the urge to move up to 3800MHz. So have the below now:
> 
> View attachment 2575830
> 
> 
> are they good numbers. Pulled them from DRAM calculator.


you should be able to run my settings or get close to mine ( my second pair of G.Skill is a 3600 14-15-15-35 1.45v but it is DR instead of your SR ) and is able to run 24/7 --->


----------



## 99belle99

Unifyx said:


> you should be able to run my settings or get close to mine ( my second pair of G.Skill is a 3600 14-15-15-35 1.45v but it is DR instead of your SR ) and is able to run 24/7
> 
> View attachment 2575849


They are tighter timings than me but 2T though.


----------



## The_King

99belle99 said:


> They are tighter timings than me but 2T though.


All my B-die kits can do 3800 CL15 with GDM off 1t at around 1.45V. Not running a high end board like you so you should be able to run this without AddrCmdSetup 56.
gets around 52ns in AIDA64.


----------



## Unifyx

99belle99 said:


> They are tighter timings than me but 2T though.


you are right, but it is very hard to run DR b-die in 1T. my kit can do 1T GDM on and 2T but you should be able to run my timings with 1T GDM off because you have SR b-die.


----------



## 99belle99

The_King said:


> All my B-die kits can do 3800 CL15 with GDM off 1t at around 1.45V. Not running a high end board like you so you should be able to run this without AddrCmdSetup 56.
> gets around 52ns in AIDA64.
> View attachment 2575856
> View attachment 2575858


I could try your timings but I doubt it would be stable as I have tried 3800MHz with tighter timings than I have now a fair few months ago and never got it stable. My RAM at XMP is 3600MHz CL16. Decent RAM but not the best you can get.


----------



## 99belle99

The_King said:


> All my B-die kits can do 3800 CL15 with GDM off 1t at around 1.45V. Not running a high end board like you so you should be able to run this without AddrCmdSetup 56.
> gets around 52ns in AIDA64.
> View attachment 2575856
> View attachment 2575858


Well I tried the timings below close to yours but not fully the same and it crashed the PC after 2mins 10 or so seconds when running TM5 1usmus_v3.


----------



## Bix

The_King said:


> Absolutely no issues booting FCLK 1900 or even higher with this Kit. Seems the problem I had was more the 4 X Vipers 4000 C19s did not play nice together on my board.
> the issue is most likely related to ProcODT which never wanted to go lower than 40 with 4 X Vipers.


Nice! My Vipers really like a low ProcODT but to lower it I needed a good bump to the 1.8V line. Can boot up to 4200 with my latest (worse) 5900x but I really can't face playing the random VDDG voltages game again trying to stabilise anything above 1900 FCLK🙃


----------



## Owterspace

My 5800X3D:



















2 sticks, 4 sticks, it doesn't matter. 1933 is all I can get it to do error free . Was really hoping to nail down 2K like my 5600X, but not in the cards this time.


----------



## Esticbo

The_King said:


> Are you still running the SK Hynix kit?
> My samsung B-die Kit also wont go above 3800 with 4X8GB sticks on this board.
> 
> Micron Rev.E seems to be much easier on the IMC than other kits. Busy testing this at the moment.
> View attachment 2575746
> 
> 
> Updated: Can't seem to boot higher than 4067MT FCLK 2033 with 4 DIMMS. Sub timings need more tunning
> View attachment 2575804
> 
> 
> Update 2. Changing some of the subtimings droped tPHYRDL from 30 above to 28 below.
> View attachment 2575811


Mine crucial max rgb 2x16 4400 cl 19 @ 4000 cl 17 at 1.35V


----------



## The_King

99belle99 said:


> Well I tried the timings below close to yours but not fully the same and it crashed the PC after 2mins 10 or so seconds when running TM5 1usmus_v3.
> 
> View attachment 2575866


If your bin is not good then maybe you should try with AddrCmdsetup 56. There is no good reason not to run it when it hardly makes any noticeable difference by running it to get an OC stable. Else If you can get lower timings with 2T then you should run 2T. There is not much difference between 3800 CL15 1T and 2T or with setup 56.



Esticbo said:


> Mine crucial max rgb 2x16 4400 cl 19 @ 4000 cl 17 at 1.35V


Nice that is Micron Rev B 16GB SR. I have the same kit just no RGB got 4200 to boot and run even pass TM5.
Some of your sub timings can be tighten up abit. tFAW 16 should run with no issues at 4000. WTRS/L 2/6 should also work see if that improves
anything or makes it worse.


This Micron Rev B Kit is crazy it can even do 3200-14-14-14 @ 1.36V











Bix said:


> Nice! My Vipers really like a low ProcODT but to lower it I needed a good bump to the 1.8V line. Can boot up to 4200 with my latest (worse) 5900x but I really can't face playing the random VDDG voltages game again trying to stabilise anything above 1900 FCLK🙃


Sadly that is the one problem I am facing with my B450 board there is no way to adjust VDD18, the option is not available in the BIOS on my board.
I think that is the reason why I am losing alot of peformance with anything above FCLK 2033. Yrcuncher number are sometimes 30 seconds slower than running 1900 FCLK.


----------



## mus1mus

The_King said:


> Are you still running the SK Hynix kit?


Micron for daily coz of 64GB cap. Benching, I use the old B-DIes.

Are you checking for HW Errors at that speed?


----------



## The_King

mus1mus said:


> Micron for daily coz of 64GB cap. Benching, I use the old B-DIes.
> 
> Are you checking for HW Errors at that speed?


There is usually some WHEA 19s at and above 2000 FCLK non of which is fatal or affects performance. The system will never crash or corrupt any data.
However has stated above i cant adjust VDD18 on my board so peformance takes a serious nose dive above 2033 FCLK.


----------



## 99belle99

The_King said:


> If your bin is not good then maybe you should try with AddrCmdsetup 56. There is no good reason not to run it when it hardly makes any noticeable difference by running it to get an OC stable. Else If you can get lower timings with 2T then you should run 2T. There is not much difference between 3800 CL15 1T and 2T or with setup 56.


I tried now with the below timings. What does that AddrCmdsetup 56 do. Seems stable enough but didn't run TM5 yet.


----------



## reantum

rjatlsj said:


> View attachment 2573969
> 
> 
> Hello, in real 2T 4000 cl14, I was able to check two tphyrdl 26
> 
> View attachment 2573970
> 
> 
> now I can check 26 after changing to Real 1t
> I'll try to refine it a little bit. Thank you for your advice


DIMM voltage?


----------



## Dazza08

Hi,

Ive been reading on this thread and the RAM OC thread for a few days and have managed to get these settings stable. Was wondering whether there is any thing that the experts can see that can be improved upon.

I believe the voltages i have set are the minimum my setup needs to be error/whea free. I dont have the best binned CPU or samsung B-dies. I also cannot post 1900fclk, can post 1933+ but its whea city no matter what I try. 1.45vdimm. 54ns aida.

Thanks!


----------



## The_King

Valka814 said:


> Still no success yet.
> 
> View attachment 2575392
> 
> View attachment 2575393
> 
> View attachment 2575391
> 
> View attachment 2575394
> 
> View attachment 2575390


I would look at your RC. After testing a few Micron kits this past few days I found that RC in the mid 60s can actually give better latency and can improve performance on REV E.

Below AIDA64 screenshot with RC 65 - 56ns AVG with RC 66 - AVG 59/60ns and with RC 64 - 58/59ns. So finding the correct RC is important! being off by just one can cause performance issue. RC in the 50s were around 58-60ns. Find your best RC in AIDA64 and use that to test TM5 again.

Try to test every RC from 58 to 68 in AIDA64 and see which one gets you the lowest AVG latency. I have not seen any benefit from lowering TRFC on REV E so maybe also test with that on AUTO.


----------



## The_King

Dazza08 said:


> Hi,
> 
> Ive been reading on this thread and the RAM OC thread for a few days and have managed to get these settings stable. Was wondering whether there is any thing that the experts can see that can be improved upon.
> 
> I believe the voltages i have set are the minimum my setup needs to be error/whea free. I dont have the best binned CPU or samsung B-dies. I also cannot post 1900fclk, can post 1933+ but its whea city no matter what I try. 1.45vdimm. 54ns aida.
> 
> Thanks!
> 
> View attachment 2576055


You can try TWR 10 RTP 5.

When ProcODT is on Auto 1900 FCLK can fail on some boards. Setting it manually can solve this problem. I had good experience with 43.6 some boards like 36.9 / 40 but you need to go through all the ProcODT from 28-60. Be prepared to reset your BIOS if OC fails and save your profiles.

I would set voltage / VDIMM abit higher when testing 1.46V-1.48V and VSOC at least 1.15V if you want to try for 3800/1900 again. You can lower these voltages once you found a ProcODT that works.

For WHEA above 1900 you can try between 1.15V-1.2V or higher on the VSOC and may need to increase IOD voltage. 1.05V-1.08V maybe 1.1V in some cases if you go above 2000 FCLK.

@99belle99
It has something to do with AGESA I believe some even run *Setup 56/56/56 to get 1T stable. It works really well for me to get 1T stable and does not seem to affect latency much or at all in my experience.


----------



## Dazza08

The_King said:


> You can try TWR 10 RTP 5.
> 
> When procODT is on auto 1900 FCLK can fail on some boards. Setting it manually can solve this problem. I had good experience with 43.6 some boards like 36.9 / 40 but you need to go through all the procODT from 28-60. Be prepared to reset your BIOS if OC fails and save your profiles.
> 
> I would set voltage / VDIMM abit higher when testing 1.46V-1.48V and VSOC at least 1.15V if you want to try for 3800/1900 again. You can lower these voltages once you found a ProcODT that works.
> 
> For WHEA above 1900 you can try between 1.15V-1.2V or higher on the VSOC and may need to increase IOD voltage. 1.05V-1.08V maybe 1.1V in some cases if you go above 2000 FCLK.
> 
> @99belle99
> It has something to do with AGESA I believe some even run *Setup 56/56/56 to get 1T stable. It works really well for me to get 1T stable and does not seem to affect latency much or at all in my experience.


3733 TWR10 RTP5 causes errors.

Have tried 1.5vdimm and tried 28-60 and i cannot post 1900.

1933fclk 1.2 VSOC and 1.1 IOD seems to get rid of the WHEA but TM5 errors almost instantly.

Ive also tried tightening primaries @3733 CL15 cannot post. CL14 will post but errors with TM5.

It seems im at the limits of my kit?

Thanks!


----------



## The_King

Dazza08 said:


> 3733 TWR10 RTP5 causes errors.
> 
> Have tried 1.5vdimm and tried 28-60 and i cannot post 1900.
> 
> 1933fclk 1.2 VSOC and 1.1 IOD seems to get rid of the WHEA but TM5 errors almost instantly.
> 
> Ive also tried tightening primaries @3733 CL15 cannot post. CL14 will post but errors with TM5.
> 
> It seems im at the limits of my kit?
> 
> Thanks!


I found this screenshot of What I used to run 3933 can try these settings. Not sure if it will help but worth a shot. Note AddrCmdSetup 56

Sometimes *DrvStr can help some run 40/20/30/20 and there are few other combos that are can help mines seem mostly fine with AUTO but different boards may need different settings. 40/20/24/24 is another combo to try with *DrvStr


----------



## Dazza08

The_King said:


> I found this screenshot of What I used to run 3933 can try these settings. Not sure if it will help but worth a shot. Note AddrCmdSetup 56
> View attachment 2576084


Tm5 errors. Procdt 34-43, 1.5vdimm DrvStr @ 20s and 24s. I even upped the [email protected]

Are these voltages safe in terms of long term daily usage?
What is AddrCmdSetup for? Just asking so i have more info incase i get a lightbulb moment and tinker heavily again.

Thanks!


----------



## scruffy1

my rig :
*ryzen 5 3600 @ 4.63 (!) boost /noctua nh-d15 / msi b450m mortar max / samsung 970 evo plus 500gb nvme/ wd 2tb / 4x8gb G.Skill ripjawsV @ (almost...) 3600 c16 (b-die) / galax 2060 super / dell u2515h / Lian Li PC-A17B & corsair hx750i & noctua fans

very recently purchased a further 2x8gb of single rank g.skill F4-3600C16D-16GVK to match my existing pair, although the dates on them are a few years newer, but the sets are both consecutive matched sticks, albeit not a matched set of 4 if that makes sense

previously the 2x8 ran sweetly at 3600 16-16-16-33 1T with the vdimm at 1.32 and the whole setup was rock stable for 2 years - the cpu is clocked using ctr2.1 rc5 

adding the "new" ram required a little fiddling using the suggestions from **here** and at present i've made it to this point, with stability in testmem5 v0.12 for 1usmus_v3 for 20 cycles, and passes in a few other trials from testmem5's options - this being at 1.36vdimm in the bios










however, any attempt to get those last few precious dregs to hit the ol' 3600 fails to even get into the boot screen despite trying a few more notches of vdimm - i know 1.4v is acceptable for the b.die i am using, but really, an extra 33 hertz shouldn't require 0.04v imho

and so, without pushing voltages much more, is there something in the ram settings i should be tweaking to hit my target sweet spot ?

my long term settings have always reflected my desire for reliable stability at stock (or under) volts, at the max available speeds within those restrictions


thanks for any helpful input *


----------



## ManniX-ITA

scruffy1 said:


> however, any attempt to get those last few precious dregs to hit the ol' 3600 fails to even get into the boot screen despite trying a few more notches of vdimm - i know 1.4v is acceptable for the b.die i am using, but really, an extra 33 hertz shouldn't require 0.04v imho


There's no such thing as under-volting with RAM or stock voltage when you are not using stock timings.
You need to use the right voltage for the setup and timings.
As an example you can get higher power usage and higher thermals with lower voltage and tighter timings and different bus settings (ProcODT, RTT, DrvStr).

In your case it's not just about the 33 MHz but the fact you are now populating 4 slots instead of 2.
The signal will get weaker and could need more voltage to stay clean at that speed.



scruffy1 said:


> and so, without pushing voltages much more, is there something in the ram settings i should be tweaking to hit my target sweet spot ?


You probably need a bit more VSOC to keep the CPU memory controller stable at that speed with 4 DIMMs.
Could also be a bit more VDDP is needed, try with 950/1000 mV.


----------



## ManniX-ITA

Dazza08 said:


> Are these voltages safe in terms of long term daily usage?


After many years at 1.55-1.6V, can say yes indeed.



Dazza08 said:


> What is AddrCmdSetup for? Just asking so i have more info incase i get a lightbulb moment and tinker heavily again.


It will add latency to the address & command lines.
Means slower memory, that's why it works.
It can make feasible 1T; albeit not as fast as pure 1T, is faster than 2T or 1T with GDM.


----------



## The_King

scruffy1 said:


> my rig :
> *ryzen 5 3600 @ 4.63 (!) boost /noctua nh-d15 / msi b450m mortar max / samsung 970 evo plus 500gb nvme/ wd 2tb / 4x8gb G.Skill ripjawsV @ (almost...) 3600 c16 (b-die) / galax 2060 super / dell u2515h / Lian Li PC-A17B & corsair hx750i & noctua fans
> 
> very recently purchased a further 2x8gb of single rank g.skill F4-3600C16D-16GVK to match my existing pair, although the dates on them are a few years newer, but the sets are both consecutive matched sticks, albeit not a matched set of 4 if that makes sense
> 
> previously the 2x8 ran sweetly at 3600 16-16-16-33 1T with the vdimm at 1.32 and the whole setup was rock stable for 2 years - the cpu is clocked using ctr2.1 rc5
> 
> adding the "new" ram required a little fiddling using the suggestions from **here** and at present i've made it to this point, with stability in testmem5 v0.12 for 1usmus_v3 for 20 cycles, and passes in a few other trials from testmem5's options - this being at 1.36vdimm in the bios
> 
> View attachment 2576085
> 
> 
> however, any attempt to get those last few precious dregs to hit the ol' 3600 fails to even get into the boot screen despite trying a few more notches of vdimm - i know 1.4v is acceptable for the b.die i am using, but really, an extra 33 hertz shouldn't require 0.04v imho
> 
> and so, without pushing voltages much more, is there something in the ram settings i should be tweaking to hit my target sweet spot ?
> 
> my long term settings have always reflected my desire for reliable stability at stock (or under) volts, at the max available speeds within those restrictions
> 
> 
> thanks for any helpful input *


I noticed your MCLK/FCLK/UCLK is not matched. I had problems with my 1700X with getting Samsung B-die and 3600MT with FCLK 1800 to work this maybe an IMC issue more than anything.

With a Ryzen 3600 I dont see why you cant run 3600 CL16-16-16 with 1800 1:1:1









1.03 VSOC is asking for problems when posting try +/-1.1V. I would run 1.4V - 1.45V VDIMM on that setup (I ran 1.2V VSOC for over 2 years my 1700X still works today)

If you can run Y-cruncher 2.5B for few cycles then you know your voltages on the VSOC and VDIMM is good then you can lower them from there till its unstable.


----------



## scruffy1

ManniX-ITA said:


> There's no such thing as under-volting with RAM or stock voltage when you are not using stock timings.
> You need to use the right voltage for the setup and timings.
> As an example you can get higher power usage and higher thermals with lower voltage and tighter timings and different bus settings (ProcODT, RTT, DrvStr).
> 
> In your case it's not just about the 33 MHz but the fact you are now populating 4 slots instead of 2.
> The signal will get weaker and could need more voltage to stay clean at that speed.


i understand enough why it needs more grunt; it sits somewhat at odds with my cool'n'quiet fetish plus i know once i start to get into it i'll be looking to tighten the timings whilst recognising the performance gains will be a bee's dick (but thus was ever the quest for e-peen), and i like having max headroom to up the voltages



> You probably need a bit more VSOC to keep the CPU memory controller stable at that speed with 4 DIMMs.
> Could also be a bit more VDDP is needed, try with 950/1000 mV.


thanks for the directions; i am way noob at what these setting actually accomplish, but i can follow a recipe and cook a masterpiece with some instruction

that idea has worked fabulously for me in jailbreaking and firmware mods to android phones / tablets and radio control multimodules (openTx based) and micro drones

i love that i can fix things till i break them, and then resurrect them - track record thus far of no bricks 

appreciate your input



The_King said:


> I noticed your MCLK/FCLK/UCLK is not matched.


a legacy of the prior set running at 1800 / 3600, and reflective of being too lazy to drop the ratio to half of where i got to



> 1.03 VSOC is asking for problems when posting try +/-1.1V. I would run 1.4V - 1.45V VDIMM on that setup (I ran 1.2V VSOC for over 2 years my 1700X still works today)


i am completely new to the current process, and just beginning my ram journey
the last time i seriously played with ram settings was back in the day with bh5 on socket a, and then onwards and upwards to 939; when c2d made me switch sides, all that happened for the longest time was upping the multiplier, and it's only now after moving on from my 2600k build that i am here again, in new territory



> If you can run Y-cruncher 2.5B for few cycles then you know your voltages on the VSOC and VDIMM is good then you can lower them from there till its unstable.


shall investigate - thanks for the suggestion


----------



## scruffy1

see later...


----------



## Blameless

The_King said:


> There is usually some WHEA 19s at and above 2000 FCLK non of which is fatal or affects performance. The system will never crash or corrupt any data.


I'm having difficulty conceiving of a test that would convince me that a system which spits out huge numbers of correctable errors is never going to throw an uncorrectable one due to the same underlying cause.

None of my AM4 CPUs are stable at 2000 FLCK and the ones that spit out the most WHEA 19s (some of them about a dozen per second) tend to throw an 18 sooner or later, or run into some other blatant instability.


----------



## The_King

Blameless said:


> I'm having difficulty conceiving of a test that would convince me that a system which spits out huge numbers of correctable errors is never going to throw an uncorrectable one due to the same underlying cause.
> 
> None of my AM4 CPUs are stable at 2000 FLCK and the ones that spit out the most WHEA 19s (some of them about a dozen per second) tend to throw an 18 sooner or later, or run into some other blatant instability.


I still run 3800MT FCLK 1900 daily. Since performance does not scale on my B450 board even with no WHEA errors using my 5600X (dual CCD) at 2000 FCLK.

I can assure you I can run Y-cruncher for days and I never came across a WHEA 18 ever on any of my Three ZEN 3 CPUs when running at 2000 FCLK. Not one single crash or
bluescreen on any of the systems.

WHEA 19s do not really bother me because I wont daily higher the 3933MT with my Micron Kits or 3800MT with my Samsung B-die kits which offers the best performance on my motherboards..

If I could adjust VDD18 on my mobo then maybe I would go to 2000 FCLK or higher for daily use. (I remember reading the WHEA #18 is CPU Vcore related )


----------



## byDenoso

tRC Exploit vs tRAS exploit


----------



## mus1mus

The_King said:


> I still run 3800MT FCLK 1900 daily. Since performance does not scale on my B450 board even with no WHEA errors using my 5600X (dual CCD) at 2000 FCLK.
> 
> I can assure you I can run Y-cruncher for days and I never came across a WHEA 18 ever on any of my Three ZEN 3 CPUs when running at 2000 FCLK. Not one single crash or
> bluescreen on any of the systems.
> 
> WHEA 19s do not really bother me because I wont daily higher the 3933MT with my Micron Kits or 3800MT with my Samsung B-die kits which offers the best performance on my motherboards..
> 
> If I could adjust VDD18 on my mobo then maybe I would go to 2000 FCLK or higher for daily use. (I remember reading the WHEA #18 is CPU Vcore related )


VDD18 does nothing for me over 3800 TBH. Anyway, have you tested the system thoroughly for actual gains going over 3800? It's interesting coz I spent at least the last two weeks trying to improve my system in SuperPi for a competition and see that going from 3800 (RAM and FCLK) to 4000 (RAM and FCLK) keeping the timings the same, actually hurt my performance.


----------



## scruffy1

re my earlier results, testmem5 using 1usmus_v3 profile failed on test 2 (single error in an hour or so today, after completing it successfully last night...)














temps look bearable.. what to tweak please ?


----------



## The_King

mus1mus said:


> VDD18 does nothing for me over 3800 TBH. Anyway, have you tested the system thoroughly for actual gains going over 3800? It's interesting coz I spent at least the last two weeks trying to improve my system in SuperPi for a competition and see that going from 3800 (RAM and FCLK) to 4000 (RAM and FCLK) keeping the timings the same, actually hurt my performance.


A few others and I in this thread have had similar experience going to 2000 FCLK. @Taraquin was able to get some scaling at 2000 FCLK by adjusting VDD18 on his mobo.

I get best performance with 4X8GB B-die sticks and when there is 4 of them then I can't go past 1900 FCLK on my board.
My Micron RAM can go above 1900 FCLK with 4 sticks but can't do the low RCD and CL of the Samsung B-die. havent really tested it recently.

My best HWBOT scores are all done using Samsung B-Die kits.



scruffy1 said:


> re my earlier results, testmem5 using 1usmus_v3 profile failed on test 2 (single error in an hour or so today, after completing it successfully last night...)
> View attachment 2576225
> View attachment 2576226
> 
> 
> temps look bearable.. what to tweak please ?


The subtimings should look similar to this even though this is 3800 CL16.
You can use the same tRAS RC RRDS RRDL tFAW etc.
It can be an issue to change several settings at once and have your RAM fail to post because you entered 1 wrong value so
look out for that. These should be safe settings for most B-die kits.


----------



## mus1mus

Was talking about this crap.

4000MHz and I lose more than 4sec off that.. Which is for some, is about where they land.


----------



## The_King

mus1mus said:


> Was talking about this crap.
> 
> 4000MHz and I lose more than 4sec off that.. Which is for some, is about where they land.


You think that is bad I lose around 20-30 seconds in Y-cruncher running 4133MT  (this improves when I increase VSOC \ CCD \ and IOD)

Very good I see you disconnected from the internet and even have sound disabled can't have anything causing latency when benching. 

Let see if we can get @Taraquin to help with this. He has some experience with scaling at 2000/2033 FCLK


----------



## mus1mus

The_King said:


> You think that is bad I lose around 20-30 seconds in Y-cruncher running 4133MT  (this improves when I increase VSOC \ CCD \ and IOD)
> 
> Very good I see you disconnected from the internet and even have sound disabled can't have anything causing latency when benching.
> 
> Let see if we can get @Taraquin to help with this. He has some experience with scaling at 2000/2033 FCLK


Ohh, I really need to disable everything when benching. every millisecond counts when trying and failing to catch a 5800X3D at that bench..

But it's good to see you guys have a running 4000 MHz RAM..


----------



## Dziarson

@mus1mus you are loosing 1 min not 4 sek


----------



## ManniX-ITA

mus1mus said:


> VDD18 does nothing for me over 3800 TBH. Anyway, have you tested the system thoroughly for actual gains going over 3800? It's interesting coz I spent at least the last two weeks trying to improve my system in SuperPi for a competition and see that going from 3800 (RAM and FCLK) to 4000 (RAM and FCLK) keeping the timings the same, actually hurt my performance.


For Pi it's best static OC and unsync FCLK:MCLK to get very high MCLK


----------



## Dziarson

@ManniX-ITA for PI you need high cpu clock and low timings memory speed is not so important


----------



## ManniX-ITA

Dziarson said:


> @ManniX-ITA for PI you need high cpu clock and low timings memory speed is not so important


High bandwidth means also lower latency, what you loose with unsync is bandwidth between IMC and CPU and you don't need it.
PBO clock it's different from static OC clock.
Some stuff will go faster, other not, that's including Pi.
I can get a better Pi calculation time with 4400 MHz RAM clock, theoretically higher timings, against 3800 MHz with theoretically better timings.
About CPU clock consider PBO boosting to 5.1 GHz gets about the same Pi calculation time against static OC at 4200 MHz.
Depending on how much static OC clock you can sustain with Pi calculation it could be worth vs PBO.

Give it a try if you are interested in Pi competitions.


----------



## Dziarson

Dziarson @ HWBOT


Ranked 96 in the apprentice league




hwbot.org


----------



## mus1mus

Dziarson said:


> @mus1mus you are loosing 1 min not 4 sek
> 
> View attachment 2576251












Told you its about 4secs. 😂

You are also 100MHz higher in CPU Freq sooo..


----------



## mus1mus

ManniX-ITA said:


> High bandwidth means also lower latency, what you loose with unsync is bandwidth between IMC and CPU and you don't need it.
> PBO clock it's different from static OC clock.
> Some stuff will go faster, other not, that's including Pi.
> I can get a better Pi calculation time with 4400 MHz RAM clock, theoretically higher timings, against 3800 MHz with theoretically better timings.
> About CPU clock consider PBO boosting to 5.1 GHz gets about the same Pi calculation time against static OC at 4200 MHz.
> Depending on how much static OC clock you can sustain with Pi calculation it could be worth vs PBO.
> 
> *Give it a try if you are interested in Pi competitions.*


Sounds fun!

Yeah, it's best to lock the CPU to gauge the improvements/loses going up in RAM Speeds. 

Sadly can't go over 4K in my current memory kits.



ManniX-ITA said:


> For Pi it's best static OC and unsync FCLK:MCLK to get very high MCLK


I am yet to try unsync mode.. 



Dziarson said:


> @ManniX-ITA for PI you need high cpu clock and low timings memory speed is not so important


CPU is king true. But if you are forced to compete in a locked CPU Frequency, you willl have to try other things to be ahead.


----------



## Dziarson

I have to try do it ať cl 12


----------



## Dziarson

@mus1mus wait you have trident z 3200cl14?


----------



## mus1mus

Yuh, from like 1800X days.


----------



## ManniX-ITA

mus1mus said:


> CPU is king true. But if you are forced to compete in a locked CPU Frequency, you willl have to try other things to be ahead.


Yes, for the 5000 MHz clock competition I didn't end up being competitive of course cause I couldn't keep it at static OC.
Got a decent result limiting the PBO clock with the power plan and using unsync. But not enough


----------



## The_King

ManniX-ITA said:


> Yes, for the 5000 MHz clock competition I didn't end up being competitive of course cause I couldn't keep it at static OC.
> Got a decent result limiting the PBO clock with the power plan and using unsync. But not enough


Does Super Pi benefit from DR ram setups VS SR? or is it just single thread and low latency?


----------



## ManniX-ITA

The_King said:


> Does Super Pi benefit from DR ram setups VS SR? or is it just single thread and low latency?


This is don't know 

All the Pi benchmarks have their own peculiarities.
y-cruncher is the one that likes more static OC (I think the code is more optimized for AVX/AVX2) and unsync FCLK.


----------



## mus1mus

ManniX-ITA said:


> Yes, for the 5000 MHz clock competition I didn't end up being competitive of course cause I couldn't keep it at static OC.
> Got a decent result limiting the PBO clock with the power plan and using unsync. But not enough


I will not be able to compete with 5GHz limit unless I can find some dry ice around here.

Maybe turning off some cores will help you next time since it is a very light test.



The_King said:


> Does Super Pi benefit from DR ram setups VS SR? or is it just single thread and low latency?


I have not tried.. got no competitive DR kits.


----------



## Dazza08

ManniX-ITA said:


> After many years at 1.55-1.6V, can say yes indeed.
> 
> 
> 
> It will add latency to the address & command lines.
> Means slower memory, that's why it works.
> It can make feasible 1T; albeit not as fast as pure 1T, is faster than 2T or 1T with GDM.


VSOC VDDP CCD IOD are there "safe" limits i should stay under for daily 24/7 usage? What i seem to be reading is vsoc 1.15 limit. Is this due to degradation or the vsoc taking too much power away from cpu to boost higher?

Thanks for clearing up Addrcmdsetup.

Ill try and get 3600cl14 working once i get time.


----------



## ocisdead

If you lower timings by a decent amount but AIDA latency barely changes does this mean the CPU clock speed is now the bottleneck?

For example with a stock potato quality 3700x
3800 18-18-18-18-36-54 432tRFC = 64.7ns
3800 16-16-16-16-32-48 384tRFC = 64.4ns


----------



## ManniX-ITA

Dazza08 said:


> VSOC VDDP CCD IOD are there "safe" limits i should stay under for daily 24/7 usage? What i seem to be reading is vsoc 1.15 limit. Is this due to degradation or the vsoc taking too much power away from cpu to boost higher?


More than what is safe the matter is usually what is best.
Unless you run with LN2, you'll hit first limits which will lower your performances before they even get dangerous.

VSOC is feeding VDDG so you need it around 40-60mV higher to avoid performance loss under load.
It's indeed not degradation but eating too much form the CPU power budget.
Said that, you need to consider if the gain is higher raising VSOC or not worth.
For instance with B-die or higher at 1900 FCLK you may have to raise VSOC to keep it stable.
Clearly being able to run VSOC lower brings an advantage.

The right VSOC and VDDG depends on the sample, some likes more others less, and FCLK, MCLK, timings, PBO or static OC, PBO settings, CO.
Both IOD and CCD have a sweet spot, depending on settings (especially if PBO or static OC and FCLK), too high and it becomes unstable or starts degrading performances.
FCLK of course is one of the main factors for IOD as that's the voltage that feed Infinity Fabric, CCD is less influenced by FCLK.

I've run VSOC at 1.225V for more than year for FCLK 2000 with the 5950X B0, no issues.
Above that most samples will just drop performances like hell.
In general it's safe and can be appropriate to gain performances up to 1.18V.

IOD is not recommended above 1200mV and you only would need that for over FCLK 2000.
CCD is not recommended above 1100mV and it's extremely rare that can provide any gain or improve stability over that threshold.

VDDP is not recommended above 1100mV, ideally not above 1050mV for daily, but I've seen many running 1.1V daily.
Really depends on how is run the memory bus but generally you go very high only when doing some extreme RAM OC.


----------



## Luggage

ManniX-ITA said:


> This is don't know
> 
> All the Pi benchmarks have their own peculiarities.
> y-cruncher is the one that likes more static OC (I think the code is more optimized for AVX/AVX2) and unsync FCLK.


Superpi is st, likes low latency and core clock - look at these 2500K with DDR3 beating my 5800X just from cl11 and LN2 clocks ;P





SuperPi - 32M overclocking records @ HWBOT


Overclocking records




hwbot.org


----------



## Taraquin

mus1mus said:


> Was talking about this crap.
> 
> 4000MHz and I lose more than 4sec off that.. Which is for some, is about where they land.
> View attachment 2576237


For 4000/2000 I needed VDD18 to be 1.88v, lower or higher caused less performance.


----------



## ManniX-ITA

Luggage said:


> Superpi is st, likes low latency and core clock - look at these 2500K with DDR3 beating my 5800X just from cl11 and LN2 clocks ;P


Everything likes higher core clock, lower latency, more bandwidth 

The matter is that with PBO there's throttling at work, always; it means the computation power is not linear with clock.
Even if you can get all the cores running at 4.8 GHz it doesn't mean you always get a better score against a static OC running at a much lower clock, eg. 4.4 GHz.
PBO will throttle the AVX/AVX2 instructions to keep running the Scalar/SSE at a higher rate, which is what usually happens in a real world usage, mixed mode.
Of course with ST there's a much higher chance that PBO works better than a static OC.

Running in desync can be useful because, depending on how memory is used, can give you a better latency.
You have to consider that AIDA is just one simple method to measure and compare latency, it doesn't tell you much.
When you compare AIDA latency you can think running unsync will give you always a worse latency but it's not true.
RAM at 4200 MHz and CL15 has better latency than 3800 MHz at CL14.
4400 MHz at CL14 is almost as fast as 3800 MHz at CL12 and it's orders of magnitude easier to run.
It's not always viable but it's best to always check if unsync is worth.
dom made in the past some interesting bench runs with y-cruncher and memory with unsync.


----------



## mus1mus

Luggage said:


> Superpi is st, likes low latency and core clock - look at these 2500K with DDR3 beating my 5800X just from cl11 and LN2 clocks ;P
> 
> 
> 
> 
> 
> SuperPi - 32M overclocking records @ HWBOT
> 
> 
> Overclocking records
> 
> 
> 
> 
> hwbot.org


Well there are a lot at play if you compare based on the records and not necessarily just the platform in question being slower and whatnot compared to another older platform.

Even if you base it off IPC (which is the generally accepted benchmark for generational performance), a higher clock system will sometimes beat a higher IPC platform (unless you are talking about aheem --- FX ----ahem). 

Also consider that those records stand there due to the person's skill -- GHz alone cannot give you the best results in SuperPi.


----------



## The_King

The_King said:


> This is the lowest bin Micron Rev. E I have. (C9BJZ) Crucial 3200 CL 16-18-18-36.
> View attachment 2574515
> View attachment 2574517
> 
> 
> 
> 
> Same Kit @ 4000 CL16
> View attachment 2574528
> View attachment 2574532


I made a really silly mistake of running WTRS/L 3/6 when I tested this. This kit is capable of running 3800 RCD 19 so 4000MT should do RCD 20 with WTRS/L 4/6
Not too bad for $25 each around 2000 rupees when on sale locally.


----------



## Luggage

ManniX-ITA said:


> Everything likes higher core clock, lower latency, more bandwidth
> 
> The matter is that with PBO there's throttling at work, always; it means the computation power is not linear with clock.
> Even if you can get all the cores running at 4.8 GHz it doesn't mean you always get a better score against a static OC running at a much lower clock, eg. 4.4 GHz.
> PBO will throttle the AVX/AVX2 instructions to keep running the Scalar/SSE at a higher rate, which is what usually happens in a real world usage, mixed mode.
> Of course with ST there's a much higher chance that PBO works better than a static OC.
> 
> Running in desync can be useful because, depending on how memory is used, can give you a better latency.
> You have to consider that AIDA is just one simple method to measure and compare latency, it doesn't tell you much.
> When you compare AIDA latency you can think running unsync will give you always a worse latency but it's not true.
> RAM at 4200 MHz and CL15 has better latency than 3800 MHz at CL14.
> 4400 MHz at CL14 is almost as fast as 3800 MHz at CL12 and it's orders of magnitude easier to run.
> It's not always viable but it's best to always check if unsync is worth.
> dom made in the past some interesting bench runs with y-cruncher and memory with unsync.


Y-cruncher is super hard mt that loves bw far more than low latency.
I would probably beat my Manual OC PB with a good unsynced memory if I could bother, from looking at Doms and millosh results with 5950X.
(The difference with PBO PB is kinda small...)
Looking at superpi nobody above me with "PBO clocks" seems to be running unsynced, they mostly have tighter,faster ram _and/or_ xoc clocks.


----------



## Luggage

mus1mus said:


> Well there are a lot at play if you compare based on the records and not necessarily just the platform in question being slower and whatnot compared to another older platform.
> 
> Even if you base it off IPC (which is the generally accepted benchmark for generational performance), a higher clock system will sometimes beat a higher IPC platform (unless you are talking about aheem --- FX ----ahem).
> 
> Also consider that those records stand there due to the person's skill -- GHz alone cannot give you the best results in SuperPi.


Need to get me a bench OS


----------



## mus1mus

Do XP 😂😂

Haven't been keen on SPi myself so yeah..


----------



## 99belle99

Ran a AIDA64 bench and cannot get my latency back down. Yesterday I got 62.8, I cannot replicate it today.


----------



## mus1mus

Luggage said:


> Need to get me a bench OS


Yeah, get a better one.. I just passed you. 😈




Dziarson said:


> @mus1mus you are loosing 1 min not 4 sek
> 
> View attachment 2576251


You are 3seconds behind now at same clocks.. ✌


----------



## KedarWolf

mus1mus said:


> Yeah, get a better one.. I just passed you. 😈
> 
> 
> 
> 
> You are 3seconds behind now at same clocks.. ✌


Can you demonstrate how to ignore a posting? I'll complain if you want, to help you show me.


----------



## mus1mus

I kinda forgot how.. been a while since I trolled the forums, you know...

Hows it going man?


----------



## KedarWolf

mus1mus said:


> I kinda forgot how.. been a while since I trolled the forums, you know...
> 
> Hows it going man?


Oh, I'm doing well. I'm quite excited!

I own a 7950x now, and ordered and paid in full for an ASROCK Taichi X670E motherboard, A-Die DDR5 with an unlocked PMIC and an ASUS Strix OC RTX 4090. The MB and RAM I'll have in a week or so, and the GPU in about a month, the store had no stock but they let me preorder it.

Getting an Optimus Water Cooling water block for the Strix too.


----------



## mus1mus

KedarWolf said:


> Oh, I'm doing well. I'm quite excited!
> 
> I own a 7950x now, and ordered and paid in full for an ASROCK Taichi X670E motherboard, A-Die DDR5 with an unlocked PMIC and an ASUS Strix OC RTX 4090. The MB and RAM I'll have in a week or so, and the GPU in about a month, the store had no stock but they let me preorder it.
> 
> Getting an Optimus Water Cooling water block for the Strix too.


Sweet!!! 

Be sure to kick some with that system incoming. 😉

Will be a while til I can upgrade myself so I will have to have fun with what I have ATM. 

In other news, looks like we are winning this year's Team Cup. 

Those who have tried to submit a score, thanks a lot whether it counted or not. 
Esp @ManniX-ITA whose score got counted!!!


----------



## Luggage

mus1mus said:


> Yeah, get a better one.. I just passed you. 😈
> 
> 
> 
> 
> You are 3seconds behind now at same clocks.. ✌


Yea you should be with those timings 

if it gets cold I’ll try an old 1190 bios and see if I can out clock you ;P


----------



## mus1mus

Out clocking me is easy bro.. I live in the tropics so my ambient temps are quite high.

Since you mentioned "old bios", I myself is using an older one. The harder to stabilize one. Makes a little difference in performance.

Still getting worse scores going up from 3800 with Pi


----------



## KedarWolf

mus1mus said:


> Out clocking me is easy bro.. I live in the tropics so my ambient are quite high.
> 
> Since you mentioned "old bios", I myself is using an older one. The harder to stabilize one. Makes a little difference in performance.
> 
> Still getting worse scores going up from 3800 with Pi


Is the overclocking competition still open?

I can try a run with my 5950x. 

Edit: Just been really busy getting the financing and research for the new build is all.


----------



## mus1mus

KedarWolf said:


> Is the overclocking competition still open?
> 
> I can try a run with my 5950x.


Ohh, just ended yesterday. We kind of survived a last day barrage from the German team. Was a close contest in the end. Pre-moderation, we are up by just 12 points. Some changes in the final tally is expected due to invalid subs but we seem okay..

Country Cup is coming up next. You'll have the latest hardware by then. 😉


----------



## 99belle99

mus1mus said:


> Out clocking me is easy bro.. I live in the tropics so my ambient temps are quite high.


I live in the tropics too, except we don't get the heat but we get the rain. 🤔


----------



## Taraquin

Anyone here have the g.skill ripjaws 3600 16-16-16 2x8? I tuned a kit for a friend of mine this weekend. Ended at 3733 15 flat, 2t, 264 RFC rest of timings tight at 1.45v. 1t was trouble though, loads of BSOD, tried up to 1.49v, temp on ram below 40C. Tried different drvstr 24 20 24 24, 30 20 24 24, 40 20 24 24 and 40 20 30 24, same issues. Any tip to stabilize 1t?


----------



## mus1mus

Try 3800 16-18-16 at 1.45? C15 is weird. TRCDRD at 15 may ask for 1.55V if it even stabilizes as often Voltage will also cause it trouble. 

I have only seen a few kits that can run over 3600 and tighter than C16..


----------



## scruffy1

i've finally got my 4x8gig of F4-3600C16D-16GVK sitting testmem5 stable on rather boring 16-16-16-36 1T with 1.376v

but it's okay, because 2x8 ran the same primary timings at 1.32v for a year before adding the extra sticks, and i have other tasks to attend before i try and destabilise my daily driver some more

i know they have more to give, but currently i don't


----------



## ManniX-ITA

Luggage said:


> Y-cruncher is super hard mt that loves bw far more than low latency.
> I would probably beat my Manual OC PB with a good unsynced memory if I could bother, from looking at Doms and millosh results with 5950X.
> (The difference with PBO PB is kinda small...)
> Looking at superpi nobody above me with "PBO clocks" seems to be running unsynced, they mostly have tighter,faster ram _and/or_ xoc clocks.


Super Pi and wPrime are more depending on CPU clock than memory.
But yet even there you can get that small boost to beat the others 
Consider I couldn't find a proper CL12/CL13 profile working on my setup at 3800 MHz.
But I can run pretty easy a 4533 MHz unsync.

Unfortunately I'm lagging behind with my new build with TECs and this 5950X B2 it's just a shameful disaster of sample.
I struggled to beat my personal scores with the old 5950X B0 and 3800 or 4000 sync.

This is the #1 5950X right now for y-cruncher pi-2.5b, it's 58.011s and it's unsync 4867 MHz.
It's simple H20 cooling, 4425 MHz.
(I should try to beat him...)









Hudson13`s y-cruncher - Pi-2.5b score: 58sec 11ms with a Ryzen 9 5950X


The Ryzen 9 5950X @ 4425.4MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. Hudson13ranks #34 worldwide and #1 in the hardware class. Find out more at HWBOT.




hwbot.org





Beats the 2nd running at a much higher clock, 5150 MHz which also runs unsync but only at 4733 MHz.









millosh_r`s y-cruncher - Pi-2.5b score: 58sec 147ms with a Ryzen 9 5950X


The Ryzen 9 5950X @ 5150.1MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. millosh_rranks #36 worldwide and #2 in the hardware class. Find out more at HWBOT.




hwbot.org





It's also using sub-ambient cooling but it wasn't enough.

All the others are unsync till my #6:









ManniX`s y-cruncher - Pi-2.5b score: 59sec 945ms with a Ryzen 9 5950X


The Ryzen 9 5950X @ 4350.3MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. ManniXranks #null worldwide and #null in the hardware class. Find out more at HWBOT.




hwbot.org





Which is using a ridiculous 4350 MHz static OC.

This is my submission for y-c pi-1b, number #5:









ManniX`s y-cruncher - Pi-1b score: 21sec 57ms with a Ryzen 9 5950X


The Ryzen 9 5950X @ 4350.3MHzscores getScoreFormatted in the y-cruncher - Pi-1b benchmark. ManniXranks #86 worldwide and #5 in the hardware class. Find out more at HWBOT.




hwbot.org





All others above are unsync as well.
But of course mine is with same ridiculous clock 

This is for y-c pi-25m where I'm at #6:









ManniX`s y-cruncher - Pi-25m score: 0sec 444ms with a Ryzen 9 5950X


The Ryzen 9 5950X @ 4350.3MHzscores getScoreFormatted in the y-cruncher - Pi-25m benchmark. ManniXranks #null worldwide and #null in the hardware class. Find out more at HWBOT.




hwbot.org





Here seems only one used unsync, there's room to do better for the others.
Number #8 with 4300 MHz went unsync and was very competitive.

With wPrime 1024M I've managed to get #64 with 4450 MHz which is a very good result.

There are no other results in the first #100 with less than 4500 MHz (except a weird 3875 MHz).
Here too probably there's a little room for improvement exploiting unsync but for wPrime CPU is king.

This guy managed to get #17 with 5150 MHz and only 3600 MHz CL14 with unsync:









delly`s wPrime - 1024m score: 28sec 281ms with a Ryzen 9 5950X


The Ryzen 9 5950X @ 5150.1MHzscores getScoreFormatted in the wPrime - 1024m benchmark. dellyranks #39 worldwide and #17 in the hardware class. Find out more at HWBOT.




hwbot.org





In general most if not all of the best results are unsync, especially since they are almost all LN2.

wPrime 32M got #46 and again it's by far the best at any low clock (except again the weird 3875 MHz)









ManniX`s wPrime - 32m score: 1sec 924ms with a Ryzen 9 5950X


The Ryzen 9 5950X @ 4350.3MHzscores getScoreFormatted in the wPrime - 32m benchmark. ManniXranks #130 worldwide and #47 in the hardware class. Find out more at HWBOT.




hwbot.org





SuperPI is even less sensible to memory settings than wPrime.

Same guy as before got an excellent result #7 at 5.8 GHz with unsync at 3800 MHz and CL14.









delly`s SuperPi - 32M score: 5min 10sec 367ms with a Ryzen 9 5950X


The Ryzen 9 5950X @ 5800.1MHzscores getScoreFormatted in the SuperPi - 32M benchmark. dellyranks #null worldwide and #7 in the hardware class. Find out more at HWBOT.




hwbot.org





I couldn't improve my 32M #26 with the old 5950X B0.

But I could improve the 1M score, now I'm #24:









ManniX`s SuperPi - 1M score: 6sec 836ms with a Ryzen 9 5950X


The Ryzen 9 5950X @ 5175.1MHzscores getScoreFormatted in the SuperPi - 1M benchmark. ManniXranks #1543 worldwide and #25 in the hardware class. Find out more at HWBOT.




hwbot.org





Which is a big thing, 30ms less, considering how bad is this B2 vs my old B0.


----------



## Taraquin

mus1mus said:


> Try 3800 16-18-16 at 1.45? C15 is weird. TRCDRD at 15 may ask for 1.55V if it even stabilizes as often Voltage will also cause it trouble.
> 
> I have only seen a few kits that can run over 3600 and tighter than C16..


No, super stable at flat 15 1.45v using 2t, 1t 7s the issue.


----------



## lkozarov

mus1mus said:


> Yeah, get a better one.. I just passed you. 😈
> 
> 
> 
> 
> You are 3seconds behind now at same clocks.. ✌


Not bad for 4 DIMM MoBo. What is DRAM Voltage?

Here is mine, just checking new cheap MoBo, after C8I died:


----------



## 99belle99

lkozarov said:


> Not bad for 4 DIMM MoBo. What is DRAM Voltage?
> 
> Here is mine, just checking new cheap MoBo, after C8I died:
> 
> View attachment 2576529


Wow that's some tight timings for that speed.


----------



## mus1mus

lkozarov said:


> Not bad for 4 DIMM MoBo. What is DRAM Voltage?
> 
> Here is mine, just checking new cheap MoBo, after C8I died:
> 
> View attachment 2576529


1.75V -- failing a lot after 1.82V thus can't do 12-11-11 consistently. Low bin B-dies sticks.


That is impressive!!! Man..


----------



## scruffy1

oooeee! that ram is heller tight timings _and _1T 

i feel shamed for running c16 🥺


----------



## lkozarov

mus1mus said:


> Yeah, get a better one.. I just passed you. 😈
> 
> 
> 
> 
> You are 3seconds behind now at same clocks.. ✌





mus1mus said:


> 1.75V -- failing a lot after 1.82V thus can't do 12-11-11 consistently. Low bin B-dies sticks.
> 
> 
> That is impressive!!! Man..


I have the same issue with the same sticks, but Intel 12600KF CPU. On AMD no problem to 2V, but MoBo doesn`t have CPU PLL Voltage and can`t do more than 1933 IF. You may try with different DRAM Vtt if the board has option, it helps with mine.


----------



## mus1mus

I can try that.. Thanks..

My issue is not being able to get better times going up in IF after 3800. Even BCLK to get a little more hurts..


----------



## The_King

New RAM got delivered today busy testing. May try for a Super Pi score later today or in the week.









Very poor first attempt with some not so good Micron RAM









Almost got it under 6mins.


----------



## Nd4spdvn

lkozarov said:


> You may try with different DRAM Vtt if the board has option, it helps with mine.


Like offsetting lower by some 50mV or other values? Or did you find a different approach, higher offset etc? I am interested to learn what approach helped in your case. Currently I run a -50mV offset on DRAM VTT but my VDIMM is 1.55V at 3800C15 with my 4400 Vipers.


----------



## lkozarov

Nd4spdvn said:


> Like offsetting lower by some 50mV or other values? Or did you find a different approach, higher offset etc? I am interested to learn what approach helped in your case. Currently I run a -50mV offset on DRAM VTT but my VDIMM is 1.55V at 3800C15 with my 4400 Vipers.


Yes, You may try -50/-100 mV on AMD, but usually works with higher voltages, for benching.


----------



## KedarWolf

If your PMIC is locked, what is your max VPP.

And on AM5, what are the other voltages in the BIOS that are controlled by the PMIC?


----------



## ManniX-ITA

KedarWolf said:


> If your PMIC is locked, what is your max VPP.
> 
> And on AM5, what are the other voltages in the BIOS that are controlled by the PMIC?


I'm curious as well.
With the PMIC locked what I knew from AL was that only VDIMM was limited to 1.435V.
But most boards have the option to unlock it.


----------



## The_King

Taraquin said:


> Anyone here have the g.skill ripjaws 3600 16-16-16 2x8? I tuned a kit for a friend of mine this weekend. Ended at 3733 15 flat, 2t, 264 RFC rest of timings tight at 1.45v. 1t was trouble though, loads of BSOD, tried up to 1.49v, temp on ram below 40C. Tried different drvstr 24 20 24 24, 30 20 24 24, 40 20 24 24 and 40 20 30 24, same issues. Any tip to stabilize 1t?


Do you mind posting Zentimings for this.

I am have issues getting this G.Skill 3600 16-16-16 to pass anything at 3800 without errors.
This RAM is much more temp sensitive than my Patriot Vipers it does not like to be above 50 and seems to error around 55.
Directed a fan at the RAM now its sits at around 45 under load.

@KedarWolf I believe these are the same sticks that come in the F4-360016Q-32GTZKK KIT which you owned a few years back.
If you have any advice or tips for this ram that will be great. Thanks.


----------



## ManniX-ITA

The_King said:


> I am have issues getting this G.Skill 3600 16-16-16 to pass anything at 3800 without errors.
> This RAM is much more temp sensitive than my Patriot Vipers it does not like to be above 50 and seems to error around 55.


Wow seems way over too sensitive.
Did you clean the DIMM pins with a contacts cleaner or alcohol before putting them in?


----------



## The_King

ManniX-ITA said:


> Wow seems way over too sensitive.
> Did you clean the DIMM pins with a contacts cleaner or alcohol before putting them in?


No I did not but should have, its a second hand RAM i bought from a guy who sold it to me for cheap cheap. 😁

I will definitely give it a good cleaning now. 

I really need to stop buying DDR4 RAM. I think I have a problem.


----------



## ManniX-ITA

The_King said:


> I will definitely give it a good cleaning now.


Last time I had weird issues with a RAM kit a little while ago was because of that.
Didn't thought about it because they were brand new, not 2nd hand.
Indeed it's always a good idea a through cleaning, it just takes seconds.
Thermal paste cleaners as well works fine.


----------



## Taraquin

The_King said:


> Do you mind posting Zentimings for this.
> 
> I am have issues getting this G.Skill 3600 16-16-16 to pass anything at 3800 without errors.
> This RAM is much more temp sensitive than my Patriot Vipers it does not like to be above 50 and seems to error around 55.
> Directed a fan at the RAM now its sits at around 45 under load.
> 
> @KedarWolf I believe these are the same sticks that come in the F4-360016Q-32GTZKK KIT which you owned a few years back.
> If you have any advice or tips for this ram that will be great. Thanks.
> View attachment 2576768


No, I delivered it to my friend. It ran 100% stable at
3733
2t gdm off
1.45V
15 flat
RAS 27
RC 42
4/4/16
4/8 WTR
264 RFC
4/4 SCL
8/1 RDWR/WRRD
14 CWL

Max temp on sticks in usmus1 20 TM5 was 41 and 44C.

Voltages required for the 5600 was ridiculus. 100% stable and no perf penalty at:
SOC 1.0
IOD 0.95
CCD/VDDP 0.8
VDD18 1.72
I didn't try lower, but it may have worked. My 5600X needs 1.06v SOC and 0.98v IOD for 3800 to work with no penalty. Seems the B2 chips are good at voltages!

CB23 at 11550 running 4.45 all the time using -30CO. Max temp in CB23 69C using stock cooler (in a Lian Li lancool 215).


----------



## gameinn

I have a 5950x with 3600C14 GTZNA 32GB G. Skill on a Dark Hero motherboard. I bought them incase I wanted to try RAM OC but also have a good XMP profile.

I am not looking for an insane overclock just a modest 3600 RAM profile better than XMP that I know will be really safe for daily use.


----------



## Kelutrel

Robby37 said:


> Try safe mode just to make sure and max edc to moon just for one test . Also what is your c0 curve ?


Hi, I may have read that you were able to stabilize 64Gb B-die @3800. I got some new 4x16Gb dimms B-die that I can't seem to move above @3733 no matter what I try.
Here is my ZenTimings screenshot for [email protected] Would you be able to share, or suggest, the configuration you used to get your 64Gb dimms stable @3800 ?


----------



## KedarWolf

ManniX-ITA said:


> I'm curious as well.
> With the PMIC locked what I knew from AL was that only VDIMM was limited to 1.435V.
> But most boards have the option to unlock it.


I might have to request a modded BIOS from ASROCK for my X670E Taichi to unlock it.

I looked at the BIOS guide and saw nothing like that in there. 
Edit: I meant to ask in the DDR5 thread.


----------



## ManniX-ITA

KedarWolf said:


> I might have to request a modded BIOS from ASROCK for my X670E Taichi to unlock it.


My understanding was that only the low-end kits have the PMIC voltage locked.
While the good to decent kits have the voltages unlocked, I've read most if not all of those above 5200.


----------



## reantum

2hrs test passed. 1smus extreme.


----------



## Ethelneth

xpulse said:


> View attachment 2575134


I had them running like this during the last year:








You should get around 54-55ns latency without services running in background (iCue, etc..). A fan directly blowing on the sticks is recommended as they tend to get a bit hot.


----------



## Merciless_Rick

KedarWolf said:


> My new EVGA X570 Dark gets a much better CO curve. Memory exactly the same though, with minor adjustments on the ProcODT and a few other tweaks. Timings exactly the same though. I think it's just the limits of my IMC and I had them tweaked as much as possible on my MSI board.
> View attachment 2574254
> Shaved more than a second off my best y-cruncher.
> View attachment 2574256
> TM5, Core Cycler 720-720 FFTs SSE, y-cruncher HNT and FFT stress tests and Linpack XTreme 1.1.5 stable.
> 
> 
> 
> 
> 
> 
> 
> BIOS settings in the Imgur link.
> 
> 
> http://imgur.com/a/biaQdPB


 🤔🤔 What bios version are you running on the EVGA Dark??? I'm running 1.08 and do not have all those extra advanced settings (interleaving, stream pre-fetchers, etc... everything from image 8 and above) on my 5600x!!! Are those settings unlocked via CPU model or is that a special bios???!!!


----------



## KedarWolf

Merciless_Rick said:


> 🤔🤔 What bios version are you running on the EVGA Dark??? I'm running 1.08 and do not have all those extra advanced settings (interleaving, stream pre-fetchers, etc... everything from image 8 and above) on my 5600x!!! Are those settings unlocked via CPU model or is that a special bios???!!!


EVGA modded a BIOS for me. It's 1.08.

I'm not allowed to share it, but you can do a Support Ticket and ask for it.


----------



## The_King

ManniX-ITA said:


> Wow seems way over too sensitive.
> Did you clean the DIMM pins with a contacts cleaner or alcohol before putting them in?


I would like to think cleaning the contacts did help. What helped even more was dropping voltage down to 1.37V only then did 3800 CL16 work. Seems this kit is very sensitive to voltages the downside to that is you can't do low TRFC because that scales with voltages. If I run RFC 285 no boot!.


----------



## ManniX-ITA

The_King said:


> I would like to think cleaning the contacts did help. What helped even more was dropping voltage down to 1.37V only then did 3800 CL16 work.


So sensitive that looks suspiciously like something is broke...

Can't be a termination issue? 
Did you try RTT 7/0/5? Maybe also with DrvStr 40/20/24/24.


----------



## The_King

ManniX-ITA said:


> So sensitive that looks suspiciously like something is broke...
> 
> Can't be a termination issue?
> Did you try RTT 7/0/5? Maybe also with DrvStr 40/20/24/24.


Will test those settings out and see if that helps. 

Edit. 
@ManniX-ITA It is definitely much more stable now will give it some more voltage and see if it behaves. Thanks for pointing me in the right direction.


----------



## Audioboxer

13900k is looking good, will be going there and keeping my DDR4 for now. Going to be interesting to see how I get on with a Z690/Z790 board compared to the B550 Unify X. I guess I'm hoping my AMD timings mostly transfer over, and I've never really done Intel memory tuning before, so be interesting to see if I can finally run 4000+ daily with no IF shenanigans.

Doesn't really look like the Intel DDR4 boards get the 2 DIMM treatment, but I'm guessing that probably won't matter as much as it might have with AM4 and getting B-die super tuned on the B550.


----------



## 99belle99

Audioboxer said:


> 13900k is looking good, will be going there and keeping my DDR4 for now. Going to be interesting to see how I get on with a Z690/Z790 board compared to the B550 Unify X. I guess I'm hoping my AMD timings mostly transfer over, and I've never really done Intel memory tuning before, so be interesting to see if I can finally run 4000+ daily with no IF shenanigans.
> 
> Doesn't really look like the Intel DDR4 boards get the 2 DIMM treatment, but I'm guessing that probably won't matter as much as it might have with AM4 and getting B-die super tuned on the B550.


Why don't you go for a 7000 series. From the limited benchmarks I seen AMD seems to edge out productive workloads and wins in some games. And that will change once 7000X3D chips arrive in the not so distant future.


----------



## ManniX-ITA

Audioboxer said:


> Doesn't really look like the Intel DDR4 boards get the 2 DIMM treatment


Well there is one but it's not a great board...









ASRock Z690M-ITX/ax


Supports 13th Gen & 12th Gen Intel Core™ Processors (LGA1700); 8 Phase Dr.MOS Power Design; Supports DDR4 5000MHz (OC); 1 PCIe 5.0 x16; Graphics Output Options: HDMI, DisplayPort; Realtek ALC897 7.1 CH HD Audio Codec, Nahimic Audio; 4 SATA3, 1 Hyper M.2 (PCIe Gen4 x4), 1 Hyper M.2 (PCIe Gen4 x4...




www.asrock.com





Going for DDR5 instead the Z690 Unify-X seems to be one of the best for RAM OC.
Pity there's nothing announced by MSI about a Z790 Unify-X.

Performance wise seems the 13900K it's a small upgrade against the 12900K.
Some decent improvements with some specific workloads but mostly is very similar to the 12th Gen at the same clock.
What is not really great is the performance per watt which is really awful, double the 7950X.
Which at then end is a 10% uplift over the board.

The 7950X could be better but overall considering the power draw is a very decent 2nd place.
What is concerning is the AVX throttling issue.
Already maturity issues and considering the previous AMD's track records I'm doubtful will ever be fixed without a new stepping.
Is the only issue or more will pop up in the next weeks?


----------



## KedarWolf

Sooooo, I get my motherboard, 7950x and DDR5, go to build my new PC, and, I need a different mounting kit for my CPU waterblock.


----------



## The_King

Audioboxer said:


> 13900k is looking good, will be going there and keeping my DDR4 for now. Going to be interesting to see how I get on with a Z690/Z790 board compared to the B550 Unify X. I guess I'm hoping my AMD timings mostly transfer over, and I've never really done Intel memory tuning before, so be interesting to see if I can finally run 4000+ daily with no IF shenanigans.
> 
> Doesn't really look like the Intel DDR4 boards get the 2 DIMM treatment, but I'm guessing that probably won't matter as much as it might have with AM4 and getting B-die super tuned on the B550.


I am still hopeful that AMD releases ZEN 4 cpus on AM4. Since they not adding support for DDR4 on the AM5 platform seems like they got no choice but to release a few new SKU's for AM4.
Dr Lisa Sue said AM4 is not dead yet! Only time will tell. Im still very happy with my ZEN 3 CPUs

Rumors of a 5900X3D have been floating around.


----------



## 99belle99

The_King said:


> I am still hopeful that AMD releases ZEN 4 cpus on AM4. Since they not adding support for DDR4 on the AM5 platform seems like they got no choice but to release a few new SKU's for AM4.
> Dr Lisa Sue said AM4 is not dead yet! Only time will tell. Im still very happy with my ZEN 3 CPUs
> 
> Rumors of a 5900X3D have been floating around.


I honestly doubt they will release Zen4 CPU's for AM4.


----------



## The_King

99belle99 said:


> I honestly doubt they will release Zen4 CPU's for AM4.


I am not holding my breath. lol but we can expect to see some new CPU for the AM4 platform very soon be it 5600X/5900/5950/X3D.

Also ZEN 4 sales have been very low as well has the AM5 platform adoption. AM4 market is much bigger than the AM5 so they really have no choice but to keep AM4 alive abit longer.


----------



## ManniX-ITA

KedarWolf said:


> I need a different mounting kit for my CPU waterblock


Wow I thought the Foundation AM4 block would be compatible with AM5.


----------



## Veii

ManniX-ITA said:


> Wow I thought the Foundation AM4 block would be compatible with AM5.


For me it works
But i wonder about direct die height
Screws might need to get sanded at the end








EDIT:

__ https://twitter.com/i/web/status/1577785460335575040


----------



## 99belle99

Audioboxer said:


> 13900k is looking good, will be going there and keeping my DDR4 for now. Going to be interesting to see how I get on with a Z690/Z790 board compared to the B550 Unify X. I guess I'm hoping my AMD timings mostly transfer over, and I've never really done Intel memory tuning before, so be interesting to see if I can finally run 4000+ daily with no IF shenanigans.
> 
> Doesn't really look like the Intel DDR4 boards get the 2 DIMM treatment, but I'm guessing that probably won't matter as much as it might have with AM4 and getting B-die super tuned on the B550.


I just watched more reviews of this CPU and it thermal throttles after a few seconds even with high end AIO coolers.

Well not really gaming but if you were buying it for productive workloads that use all cores it WILL thermal throttle after a few seconds.


----------



## ManniX-ITA

99belle99 said:


> Well not really gaming but if you were buying it for productive workloads that use all cores it WILL thermal throttle after a few seconds.


This is how Intel is achieving good performances since a few generations.
And what AMD copycat for the 7000.

The 13th gen runs with 12th gen clocks at stock so it throttles earlier.

They can both deliver great performances and low power consumption if limited.
But AMD has a big advantage on power efficiency, Intel on peak performances and gaming.

It's a bit of an impasse if you want to do some decent OC without LN2.
Intel has still that 500 MHz lead but the cooling requirements are atrocious.
AMD is still struggling with throttling AVX and it's a deal breaker for high static OC and profile based OC like Hydra.
I think I'll stick with my ugly 5950X for a little while and see what happens.


----------



## KedarWolf

ManniX-ITA said:


> Wow I thought the Foundation AM4 block would be compatible with AM5.


I have the original mounting kit that first came out. You remove the backplate to use it and screw nuts on both ends. 

The new mounting kit uses posts that screw right into the backplate, I don't have that one. You can't remove the backplate on AM5.


----------



## Luggage

ManniX-ITA said:


> This is how Intel is achieving good performances since a few generations.
> And what AMD copycat for the 7000.
> 
> The 13th gen runs with 12th gen clocks at stock so it throttles earlier.
> 
> They can both deliver great performances and low power consumption if limited.
> But AMD has a big advantage on power efficiency, Intel on peak performances and gaming.
> 
> It's a bit of an impasse if you want to do some decent OC without LN2.
> Intel has still that 500 MHz lead but the cooling requirements are atrocious.
> AMD is still struggling with throttling AVX and it's a deal breaker for high static OC and profile based OC like Hydra.
> I think I'll stick with my ugly 5950X for a little while and see what happens.


Yea waiting for 7000x3d vs 13ks, 4090 vs 7900xtx(h?), B650 Unify/Gene/Tachyon vs … Intel mb…

No rush


----------



## Luggage

KedarWolf said:


> I have the original mounting kit that first came out. You remove the backplate to use it and screw nuts on both ends.
> 
> The new mounting kit uses posts that screw right into the backplate, I don't have that one. You can't remove the backplate on AM5.


No “Noctua style” support for just giving new mounting hw?


----------



## Audioboxer

99belle99 said:


> Why don't you go for a 7000 series. From the limited benchmarks I seen AMD seems to edge out productive workloads and wins in some games. And that will change once 7000X3D chips arrive in the not so distant future.


Just waiting on DDR5 to mature a bit tbh. I've got a 5950x just now, it's not like productivity is a worry.

Really just looking for something else to tinker with without going full new platform quite yet. My DDR4 bin is the best that was released with DDR4 so I've always been interested to push it further without the annoying 1900 FCLK limit.

13900k benches are pretty good for single core and gaming which is fine for me. I have no brand loyalty so a wee stint with Intel might freshen things up! Full custom loop so up for trying to tame Intel and their "just throw power usage at **** and it will run fast".

I'm sure AMD will wipe the floor with 3D cache next year but that's more waiting 😂 Motherboards will have matured by then as well I guess, AMD BIOS gives me the fear.


----------



## Fliperx

Greetings to all. I am having a problem that I have seen occur much more frequently than I would have thought. 

My setup:
CPU: *Ryzen 5950*
Mother: *PRIME B550-PLUS*
RAM: *4x16 Team Group 3600mhz CL18*
GPU: *RTX 3080*

By loading factory defaults with F5 in the BIOS, then activating the DOCP profile, the PC reboots three times and then enters safe mode. The only way to be able to use it is with DOCP inactive.

The strange solution I have found is to remove the four memory modules of 16gb each and replace them with four modules of 8gb each, same brand and model (3600mhz cl18). In this case after loading factory defaults and activating DOCP Windows boots without problems, after which I turn off the PC, remove the four 8gb modules, place the four 16gb modules and Windows starts again without problems. But as soon as I make the slightest change in the BIOS even if it is not related to RAM, such as adjusting the curve of the coolers, immediately the PC crashes again and will not boot again until I repeat this strange procedure of exchanging the four memory modules. 

Has anyone had something similar happen to them, could you help me understand this supposed solution and find a more solid solution? I can't depend on my neighbor's RAM, and I feel imprisoned by not being able to make any changes in my BIOS without the BIOS refusing to post.


----------



## The_King

XMP usually runs at 1.35V. You can try increasing the VDIMM slightly to 1.36V to 1.37V. Sometimes a small bump in VSOC can also help.

What I recommend when your PC does boot with 4X16Gb is to check with Zentimings and note down what ProcODT is and set that manually. This can help with many XMP boot issues when you have ProcODT set on Auto.


----------



## ManniX-ITA

The_King said:


> XMP usually runs at 1.35V. You can try increasing the VDIMM slightly to 1.36V to 1.37V. Sometimes a small bump in VSOC can also help.
> 
> What I recommend when your PC does boot with 4X16Gb is to check with Zentimings and note down what ProcODT is and set that manually. This can help with many XMP boot issues when you have ProcODT set on Auto.


Yes this is indeed good advice  

@Fliperx 

I would also take note of RTT and ClkDrv quadruplets values and set them manually.
If you still have issues at cold boot, try to bring up or down a notch ProcODT


----------



## Blameless

Veii said:


> __ https://twitter.com/i/web/status/1577785460335575040


There's no text on any of my CPUs; I like sandpaper too much.

Doesn't look like that one needs it though.



Fliperx said:


> Has anyone had something similar happen to them, could you help me understand this supposed solution and find a more solid solution? I can't depend on my neighbor's RAM, and I feel imprisoned by not being able to make any changes in my BIOS without the BIOS refusing to post.


The_King and ManniX-ITA have this covered.

Unfortunately, XMP is not always as plug and play as advertised and manual adjustment is mandatory for some configurations. On the plus side, once you get a little experience, you get a bit of free performance from this as well.


----------



## ManniX-ITA

Blameless said:


> Doesn't look like that one needs it though.


Well seems it's worth to go deep and remove all that copper to get better results, much more than just the text 



Spoiler


----------



## Blameless

ManniX-ITA said:


> Well seems it's worth to go deep and remove all that copper to get better results, much more than just the text
> 
> 
> 
> Spoiler


Yeah, but if one isn't keen on going that far, lapping when one's contact is solid probably isn't worth the effort either.

On a side note, AMD's insistence on backwards compatability with coolers seems to be costing them a bit this gen. A delid helps almost anything, but the thickness of the AM5 IHS is absurd, especially with the CCDs so close to the edge.


----------



## ManniX-ITA

Blameless said:


> Yeah, but if one isn't keen on going that far, lapping when one's contact is solid probably isn't worth the effort either.


Indeed, I didn't lap my 5950X for warranty.
I've read others experiences and if it's already flat there's zero improvement.
Some old 5800X were really bad and were very worth to lap.

Now that the replacement warranty is almost gone I'm thinking about checking the flatness of this 5950X B2.
It sucks so much that can't get worse.



Blameless said:


> On a side note, AMD's insistence on backwards compatability with coolers seems to be costing them a bit this gen. A delid helps almost anything, but the thickness of the AM5 IHS is absurd, especially with the CCDs so close to the edge.


I don't think was really about AM4 compatibility.
That massive thick IHS is there mostly to provide a thermal capacity buffer, it allows usage without hard throttling (HS not detected, locked at 800 MHz till poweroff) also with cheap air coolers.
Gives more time to throttling when you have decent cooling but basically equalize anything good to that artificial bottleneck.
Not a problem with LN2 or something good sub ambient but it's a tragedy for any decent to good custom WC.


----------



## KedarWolf

Luggage said:


> No “Noctua style” support for just giving new mounting hw?


Yeah, I just got an email they are sending me a new mounting kit from Chicago to Toronto buy UPS for free.

I should have it Monday hopefully. 

Plus I ordered a new Foundation waterblock as mine is a bit pitted from bad Grizzly thermal paste and scratched up a bit too. I really should lap it before i use the old one, think I'll do that.

New waterblock is delayed as Optimus had a parts shortage but should ship by next week.


----------



## fas7play

Hello, hope you are doing well. 
Does anyone feel like looking at my settings, can i improve something, mistakes made?
F4-3200C14-8GTZSW (very old sticks^^)
@1.450V









Thank you very much for the help.


----------



## ManniX-ITA

fas7play said:


> F4-3200C14-8GTZSW (very old sticks^^)


Why not FCLK 1900 in sync? It doesn't boot?

Better 3600/1800 and maybe a CL15 profile in case.


----------



## fas7play

ManniX-ITA said:


> Why not FCLK 1900 in sync? It doesn't boot?


Oh, thanks for the quick reply, my fault - issue is fixed.








what else would you adjust to achieve more speed?
thx!


----------



## KedarWolf

My new AM5 CPU mounting kit has shipped from Chicago to Toronto by UPS. I hope to get it Monday. 

I need to lap my old block though as it's a bit pitted from bad Grizzly thermal paste. It's scratched up a bit too. I get multiple grits sandpaper and a Plexiglas plate Monday as well to lap it.


----------



## ManniX-ITA

KedarWolf said:


> I get multiple grits sandpaper and a Plexiglas plate Monday as well to lap it.


I may not be a guru expert in lapping but I wonder why Plexiglass and also why, as I keep hearing, also tempered glass is trending...
AFAIK they are not suitable for lapping. Better than other solid surfaces but not that much.

What you need is a mirror, cheapest you can buy.
It's the only thing that is made accurately flat and that you can inspect yourself for flatness, if the reflection is distorted it's not flat.

Glass plates are not made flat, they can look flat but they are probably not.


----------



## ManniX-ITA

fas7play said:


> what else would you adjust to achieve more speed?












You may have to go up to 1.46 -1.48V RAM voltage.
Test with TM5 1usmus for at least 25 cycles, more than 1h.


----------



## fas7play

ManniX-ITA said:


> Test with TM5 1usmus for at least 25 cycles, more than 1h.


had not expected so much,.... wow you are great! danke!
of course i will run with TM5


----------



## Fliperx

The_King said:


> XMP usually runs at 1.35V. You can try increasing the VDIMM slightly to 1.36V to 1.37V. Sometimes a small bump in VSOC can also help.
> 
> What I recommend when your PC does boot with 4X16Gb is to check with Zentimings and note down what ProcODT is and set that manually. This can help with many XMP boot issues when you have ProcODT set on Auto.





ManniX-ITA said:


> Yes this is indeed good advice
> 
> @Fliperx
> 
> I would also take note of RTT and ClkDrv quadruplets values and set them manually.
> If you still have issues at cold boot, try to bring up or down a notch ProcODT


Thanks in advance for the answers, I attach the values shown by zentimings with *4x16gb 3600 cl18*

_To tell you the truth I still don't understand how the supposed solution I have found works, if anyone can come up with a theory I would appreciate it if you could share it.






_


----------



## ManniX-ITA

Fliperx said:


> To tell you the truth I still don't understand how the supposed solution I have found works, if anyone can come up with a theory I would appreciate it if you could share it.


My guess is that ASUS DOCP sucks.
It's a source of the worst possible issues, I can confirm.
Still better than the sister ASRock mess with XMP.










Set the VSOC to 1.125 in BIOS or you'll always end up in some weird issues with memory.
Set manual instead of Auto what is marked in yellow.


----------



## Fliperx

ManniX-ITA said:


> Set the VSOC to 1.125 in BIOS or you'll always end up in some weird issues with memory.
> Set manual instead of Auto what is marked in yellow.


Thanks again, I must admit that I am not used to manipulate those values in the BIOS, originally I only use the BIOS to adjust the cooler curves and change the boot order. I understand that these values that you indicate me are in AI tweak, is that correct?

Another doubt, I have read that with four memory modules it is recommended to enable the BGS and disable the BGS alt, is it true?


----------



## ManniX-ITA

Fliperx said:


> Another doubt, I have read that with four memory modules it is recommended to enable the BGS and disable the BGS alt, is it true?


This I don't know...
I'd suggest you test yourself, download BenchMate:






BenchMate







benchmate.org





Run Cinebench MT, y-cruncher pi-2.5b and 7zip with both settings to check if you get different results.



Fliperx said:


> Thanks again, I must admit that I am not used to manipulate those values in the BIOS, originally I only use the BIOS to adjust the cooler curves and change the boot order. I understand that these values that you indicate me are in AI tweak, is that correct?


Should be AI Tweaker tab under DRAM Timing Control menu.
Page 18 to 20 of the board manual.


----------



## fas7play

ManniX-ITA said:


> Test with TM5 1usmus for at least 25 cycles, more than 1h.


 did 1usmus / [email protected]

changed: Cmd2T -> 1T (from 2T)
tWTRS: 4 (5)
TWTRL: 10 (14)
5903 CB R20 // 15312 CB R23 5800x3D (-30 // 110 75 110)

reducing tRDRDSCL/WR.. to 3 -> errors inTM5 so i go with 4.








thank you for the quick help


----------



## KedarWolf

ManniX-ITA said:


> I may not be a guru expert in lapping but I wonder why Plexiglass and also why, as I keep hearing, also tempered glass is trending...
> AFAIK they are not suitable for lapping. Better than other solid surfaces but not that much.
> 
> What you need is a mirror, cheapest you can buy.
> It's the only thing that is made accurately flat and that you can inspect yourself for flatness, if the reflection is distorted it's not flat.
> 
> Glass plates are not made flat, they can look flat but they are probably not.


I bought a mirror glass instead. It wasn't any cheaper, but big enough to fully fit the 9x12 sandpaper.


----------



## ManniX-ITA

fas7play said:


> changed: Cmd2T -> 1T (from 2T)
> tWTRS: 4 (5)
> TWTRL: 10 (14)


Not bad, which VDIMM did you use, same as before or higher?


----------



## fas7play

ManniX-ITA said:


> Not bad, which VDIMM did you use, same as before or higher?


 thx, 1.48 - after 1 week of testing, ill try 1.45.


----------



## The_King

Finally! GDM Off Real 1T (Turns out All my B-die kits can do 1T on this board all I had to do was have a fan blowing on the RAM to keep them cool) 🤦‍♂️🤦‍♂️🤦‍♂️ 
If I use Boost overide I could probably get latency to go lower in the 51s









51.9 Technically still in the 51s


----------



## The_King

The_King said:


> Finally! GDM Off Real 1T (Turns out All my B-die kits can do 1T on this board all I had to do was have a fan blowing on the RAM to keep them cool) 🤦‍♂️🤦‍♂️🤦‍♂️
> If I use Boost overide I could probably get latency to go lower in the 51s
> View attachment 2577466
> 
> 
> 51.9 Technically still in the 51s
> View attachment 2577609
> View attachment 2577610


Got 10 cycles to pass at this point if it errors its probably because of overheating has the fan blowing air over the DIMMS is not doing the best job.


----------



## Bix

The_King said:


> Got 10 cycles to pass at this point if it errors its probably because of overheating has the fan blowing air over the DIMMS is not doing the best job.
> View attachment 2577664


If it's in a case then 25 cycles with Furmark stressing the GPU at the same time is a sure-fire way to see if temp might be an issue. With 1.46V and those RTTs and weak ClkDrvStr I'd be surprised if it was though...


----------



## The_King

Bix said:


> If it's in a case then 25 cycles with Furmark stressing the GPU at the same time is a sure-fire way to see if temp might be an issue. With 1.46V and those RTTs and weak ClkDrvStr I'd be surprised if it was though...


Interesting things to note about this config If I increase ClkDrvStr higher than 24 it errors before 3 cycles. The same if I increase CkeDrvStr to 24.
In the past I always tried to get Real 1T with ClkDrvStr 40 and this it seems is why I was partly unsuccessful also having a fan keeping the DIMMS cool when running TWR 10 RTP 5 seems to be important.

My setup is out of the case no GPU stress is going to affect temps. 
I removed the front fan from the CPU cooler and have it blowing air on the DIMMS from an angle. The CPU cooler also cover most of the DIMMS which make cooling it even harder.


Spoiler: Setup


----------



## Mikel_Ertz




----------



## Mikel_Ertz

Got this settings stable at 1usmusv3 50 cycles. How much anta777 absolut cycles should i run? i have 2 modules of 16gb


----------



## 99belle99

Mikel_Ertz said:


> Got this settings stable at 1usmusv3 50 cycles. How much anta777 absolut cycles should i run? i have 2 modules of 16gb


I'm no expert but that seems over the top testing. Yes I know some experts will say test like fu*k but personally I think 6 hours 20 mins is mental and then wanting to run another.

Well done passing that much but I suppose you aren't pushing the timings.


----------



## ManniX-ITA

Mikel_Ertz said:


> Got this settings stable at 1usmusv3 50 cycles. How much anta777 absolut cycles should i run? i have 2 modules of 16gb


3 cycles should be enough, around a couple of hours.
What's next? Testing in hot boiling oil?


----------



## Mikel_Ertz

99belle99 said:


> I'm no expert but that seems over the top testing. Yes I know some experts will say test like fu*k but personally I think 6 hours 20 mins is mental and then wanting to run another. Well done passing that much but I suppose you aren't pushing the timings.


 I need to ensure stability lol. I am running anta777 absolute for 20 cycles (more than 15h) Gyazo This are my stock timmings (the photo is from Google, but is the same ram)


----------



## Mikel_Ertz

What settings should I change to try to disable GDM?


----------



## MrHoof

The_King said:


> Interesting things to note about this config If I increase ClkDrvStr higher than 24 it errors before 3 cycles. The same if I increase CkeDrvStr to 24.
> In the past I always tried to get Real 1T with ClkDrvStr 40 and this it seems is why I was partly unsuccessful also having a fan keeping the DIMMS cool when running TWR 10 RTP 5 seems to be important.
> 
> My setup is out of the case no GPU stress is going to affect temps.
> I removed the front fan from the CPU cooler and have it blowing air on the DIMMS from an angle. The CPU cooler also cover most of the DIMMS which make cooling it even harder.
> 
> 
> Spoiler: Setup
> 
> 
> 
> 
> View attachment 2577679


for a b450 board you have gotten very lucky even doing real 1T, seems to be a good board.


----------



## SneakySloth

Mikel_Ertz said:


> Got this settings stable at 1usmusv3 50 cycles. How much anta777 absolut cycles should i run? i have 2 modules of 16gb


I'd suggest running the Universal2 profile instead of Anta. If I was testing myself, I would personally test for around the same time (~6 hours) with either the Anta or Universal profiles.


----------



## Mikel_Ertz

SneakySloth said:


> I'd suggest running the Universal2 profile instead of Anta. If I was testing myself, I would personally test for around the same time (~6 hours) with either the Anta or Universal profiles.


it seems to be stable, with the same timings and voltages used in 1usmusv3. Still need to complete 10 cycle more to finish


----------



## The_King

MrHoof said:


> for a b450 board you have gotten very lucky even doing real 1T, seems to be a good board.


Was much cooler this morning so decided to try 25 cycles. Seems good. I have 2 B450M Mortar MAX boards both can do real 1T now.
Keep those B-die's cool. ❄😎❄😎❄ <-----Two happy B-die sticks that are cool.


----------



## Mikel_Ertz

Gyazo







gyazo.com




Got my settings stable in anta777 absolut, in the photo shows 18 cycles, but i have completed 20 cycles with no error


----------



## Mikel_Ertz

can someone pass me the Universal2 profile for TM5. How much should i test this profile?


----------



## The_King

Mikel_Ertz said:


> Gyazo
> 
> 
> 
> 
> 
> 
> 
> gyazo.com
> 
> 
> 
> 
> Got my settings stable in anta777 absolut, in the photo shows 18 cycles, but i have completed 20 cycles with no error


It not hard to get those settings to Pass TM5 you basically not even tickling those Micron RAM sticks with those settings.
You should be doing 3800 CL14 with around 1.45V. Depending on what speed grade your ICs are,. I am guessing it should be C9BLM 16GB DR.
Then you should be able to run 3933 CL16 RCD 17 with not much issues.









This post should have a link the profiles you are looking for.








Memory Testing with TestMem5 TM5 with custom configs


Hello everybody I am just making a very light tutorial with a collection of custom config files and a DOWNLOAD LINK for TM5 v0.12 anta777 absolut config *Official* Intel DDR4 24/7 Memory Stability Thread None of the work is mine but it seems like a pretty good and fast testing app




www.overclock.net


----------



## Mikel_Ertz

The_King said:


> It not hard to get those settings to Pass TM5 you basically not even tickling those Micron RAM sticks with those settings.
> You should be doing 3800 CL14 with around 1.45V. Depending on what speed grade your ICs are,. I am guessing it should be C9BLM 16GB DR.
> Then you should be able to run 3933 CL16 RCD 17 with not much issues.
> View attachment 2577924
> 
> 
> This post should have a link the profiles you are looking for.
> 
> 
> 
> 
> 
> 
> 
> 
> Memory Testing with TestMem5 TM5 with custom configs
> 
> 
> Hello everybody I am just making a very light tutorial with a collection of custom config files and a DOWNLOAD LINK for TM5 v0.12 anta777 absolut config *Official* Intel DDR4 24/7 Memory Stability Thread None of the work is mine but it seems like a pretty good and fast testing app
> 
> 
> 
> 
> www.overclock.net


Could you tell me what timmings should i change to run 3900mhz. And what voltages plz?


----------



## Mikel_Ertz

My ram: Gyazo



Amazon.es


----------



## The_King

Mikel_Ertz said:


> My ram: Gyazo
> 
> 
> 
> Amazon.es


I do have a similar kit. I did not spend too much time tuning the Crucial 3600 CL16 16GB DR. But the ICs are the same in the 8GB DIMMS I posted above.
I think I do have a post a few pages back. You should be able to use most of those timings with your kit. Just don't run WTRS/L 3/6 it can cause issues.

Let me see if I can find any screenshots on my PC.

I only found this post where I did 4133 CL16. Looks like I did not save a profile for 3800 and 3933.








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Indeed, and for that reason I run this: Now that is cheesy) 15+21=36... Definitely not that different from tRC=37 ))). Dang, wish i had 32GB 2x16 S8B kit... But i am kind of forced to deal with H8DJR instead, because buying B-die on top will be wasting money. In all Hynix and Micron config...




www.overclock.net




You should not run this at least not daily!









You can try the timings I used in the previous post for 3933 CL16. Try with 1.45V-1.47V VDIMM. Use WTRS/L 4/8

This is Thaiphoon Burner screenshot of the IC that I have in my 16GB Rev E DIMMS the same ICs are in the 16GB/8GB DIMMS.


----------



## Mikel_Ertz

The_King said:


> I do have a similar kit. I did not spend too much time tuning the Crucial 3600 CL16 16GB DR. But the ICs are the same in the 8GB DIMMS I posted above.
> I think I do have a post a few pages back. You should be able to use most of those timings with your kit. Just don't run WTRS/L 3/6 it can cause issues.
> 
> Let me see if I can find any screenshots on my PC.
> 
> I only found this post where I did 4133 CL16. Looks like I did not save a profile for 3800 and 3933.
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Indeed, and for that reason I run this: Now that is cheesy) 15+21=36... Definitely not that different from tRC=37 ))). Dang, wish i had 32GB 2x16 S8B kit... But i am kind of forced to deal with H8DJR instead, because buying B-die on top will be wasting money. In all Hynix and Micron config...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> You should not run this at least not daily!
> View attachment 2577935
> 
> 
> You can try the timings I used in the previous post for 3933 CL16. Try with 1.45V-1.47V VDIMM. Use WTRS/L 4/8
> 
> This is Thaiphoon Burner screenshot of the IC that I have in my 16GB Rev E DIMMS the same ICs are in the 16GB/8GB DIMMS.
> View attachment 2577938


"Just don't run WTRS/L 3/6 it can cause issues".
This, Do you mean with my actual settings or with the new ones?


----------



## The_King

Mikel_Ertz said:


> "Just don't run WTRS/L 3/6 it can cause issues".
> This, Do you mean with my actual settings or with the new ones?


At 3800 it should be fine. I found that running WTRS/L 3/6 above 3800 caused errors for me with more than 5 cycles so I ran 4/8 instead.
I guess you will only know if you test it out. Your kit maybe will run fine with it at 3


----------



## StrongForce

Hello,

I have been tweaking a bit and found some settings that I find performs really well (only tested 3dmark timespy though)

I ran a Mem5 test with the default profile 1usmusv3, I put 20 Cycles and it ran fine, took 30mn +- no error.. I was reading on reddit someone recommending OCCT memory test, I tried it and within 20 second, WHEA errors, what's the deal with that, I have been hearing aboout it.. should I just use Mem5 ? and I guess I should put 500% instead of 100% if I want a longer test, will try that.

Oh and I have Aida 64 could try that stress test.. not sure if it's good or what, I read people say it is.

RAM is Gskill 4266 cl19










EDIT : I have just tested and Mem5 finds errors after 20mn after this run, interesting that OCCT finds the error faster !

Any tip on which voltages I should try to bump ?


----------



## ManniX-ITA

StrongForce said:


> EDIT : I have just tested and Mem5 finds errors after 20mn after this run, interesting that OCCT finds the error faster !


WHEA errors are from the CPU, not the memory.
TM5 is a pure memory test, OCCT is RAM/CPU.
You have VDDG IOD too close to VSOC; it's probably 1.1V.
Either set IOD to 1000-1020 mV (you probably don't need it at 1050 with a 5600 and FCLK 1867) or if you need it higher set VSOC to 1.125V-1.15V.


----------



## MrHoof

The_King said:


> Was much cooler this morning so decided to try 25 cycles. Seems good. I have 2 B450M Mortar MAX boards both can do real 1T now.
> Keep those B-die's cool. ❄😎❄😎❄ <-----Two happy B-die sticks that are cool.
> View attachment 2577872


Can only agree ❄😎❄😎❄
My setup also Asus.








and old 5800x


----------



## Veii

The_King said:


> Was much cooler this morning so decided to try 25 cycles. Seems good. I have 2 B450M Mortar MAX boards both can do real 1T now.


Please try:










MrHoof said:


> My setup also Asus.


Sorry, please try









Both as comparison with Benchmate y-cruncher 2.5b & aida64
(trow away the first result, without ethernet cable)


----------



## MrHoof

Veii said:


> Please try:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sorry, please try
> View attachment 2578004
> 
> 
> Both as comparison with Benchmate y-cruncher 2.5b & aida64
> (trow away the first result, without ethernet cable)


Can already tell u tWRRD 2 wont work.
But why tWRWRSD TWRWRDD 8? As much as i undertstand they are not used with 2dimms.
Tcke i can take to 8 but i never could tell any difference between 1 and anything else.
Also will do on the 5800x3d , I edited my post, tWTRS 3 was doable on my 5800x but not on my 3d it errors into 2-3 cycles.


----------



## Veii

MrHoof said:


> As much as i undertstand they are not used with 2dimms.


writes to writes are
DD is for different dimm, but right side and RRD, WTR go hand in hand
tRAS, tRC with tRTP go hand in hand

SCL for Writes to Writes can drop strongly (only if utilized different RAS method)
Writes on AMD are instant , well 1 tCK
i try to drop it to 1 atm

I need to know what type of tCCD is loaded for both _S and _L
~ on DR, on SR i'll just use burst-chops of 4
But it only reads it on XMP, which is bothersome
Maybe SCL needs to be higher and RD to RD need to be over 8

We'll see, please report back any errors you got
I am not sure if i have to increase RCD_WR over BurstChop 8

EDIT:
Works well here, drop of 0.5ns


Spoiler






















Was testing things, ignore 2000 FCLK only ^^*
I'll have to try how Real BankGroupSwap between dimms, works // as that changes _L behavior, same for RTT_WR changes it on DR
tWTR 3 runs too , but 2 not yet
Preset before was tRRD 7, tFAW 28, tWTRS 5
Adjustment on SD, DD, SCL ~ helps 

I start to think there is an issue with recommended 1-5-5-1-7-7 ~ they make barely sense


Veii said:


> DD is for different dimm,


BGS Alt focuses and prioritizes first dimm only
But BGS normal does not, it uses both
tWTR_S 3 works but loses potential bandwidth, soo even if faster - something cuts into it (unusable to me)


----------



## The_King

@Veii Have you done any more testing with your Micron Rev E/B kits? Was waiting for updates. 🙂 

Will run those changes/settings you gave tomorrow. Thanks

I also have a 4000 C19 kit capable of doing 3800 CL14-14-14. Want to try that with real 1T tomorrow as well.
Was only 3 cycles though on my 5600 but its the only one of my B-die Kits that does RCD 14 @ 3800MT without complaining.


----------



## umea

o/ long time no see

i figured i might as well ask here since this is probably the place with the most ppl with enthusiast level boards that also care about RAM OC.

anyone have opinions on B550 Unify vs B550 Unify-X vs X570S Unify-X Max?

decided to stick to this platform for a while and going to be selling off a bunch of pc parts (including motherboards i will never use). wanna move to ATX mobo (more room, more m.2 slots) but was curious about what yall think about each. not entirely sure if i'll grab these but wanted to have a reference point.

for reference im in canada, so this is what the pricing looks like:








also the EVGA x570 dark is a potential option. 

Or... to save money, if there's any other good ATX boards with 2 dimms rather than 4.

thanks


----------



## MrHoof

Veii said:


> writes to writes are
> DD is for different dimm, but right side and RRD, WTR go hand in hand
> tRAS, tRC with tRTP go hand in hand
> 
> SCL for Writes to Writes can drop strongly (only if utilized different RAS method)
> Writes on AMD are instant , well 1 tCK
> i try to drop it to 1 atm
> 
> I need to know what type of tCCD is loaded for both _S and _L
> ~ on DR, on SR i'll just use burst-chops of 4
> But it only reads it on XMP, which is bothersome
> Maybe SCL needs to be higher and RD to RD need to be over 8
> 
> We'll see, please report back any errors you got
> I am not sure if i have to increase RCD_WR over BurstChop 8
> 
> EDIT:
> Works well here, drop of 0.5ns
> 
> 
> Spoiler
> 
> 
> 
> 
> View attachment 2578005
> 
> View attachment 2578007
> 
> 
> 
> Was testing things, ignore 2000 FCLK only ^^*
> I'll have to try how Real BankGroupSwap between dimms, works // as that changes _L behavior, same for RTT_WR changes it on DR
> tWTR 3 runs too , but 2 not yet
> Preset before was tRRD 7, tFAW 28, tWTRS 5
> Adjustment on SD, DD, SCL ~ helps
> 
> I start to think there is an issue with recommended 1-5-5-1-7-7 ~ they make barely sense
> 
> BGS Alt focuses and prioritizes first dimm only
> But BGS normal does not, it uses both
> tWTR_S 3 works but loses potential bandwidth, soo even if faster - something cuts into it (unusable to me)


Baseline stable stettings.









20tRAS/34tRC 100 errors in 5 sec , (data corruption possible sfc found no issues tho)
21tRAS/35tRC 0/2/10 errors in 2 mins
22tRAS/36tRC 1 cycle stable
also 3/10 tWRTS/L seem to work better then 3/8.


----------



## Veii

The_King said:


> @Veii Have you done any more testing with your Micron Rev E/B kits? Was waiting for updates. 🙂


They sit here.
Not wanting to complain, but how things are right now ~ i'll pull a Jayz2Cents as a "plans for 1 year a customer build". December is soon 😅
There are couple things away from RamOC that borrow my time, but this build . . . i'm more than busy 😅

Sadly no, i'm sorry.
Docs barely got love either, it's just too much.
Watercooling for personal build goes hand in hand with clients build. Both are close, but so far both are on air.
I can't really test many things. Only got curious a bit with JEDEC last 1-2 days.

I don't know either if i'll jump to Zen4.
I'll play with it for a month, but unless i figure out something people don't have (push MCLK boundries again)
Then it makes not much sense to rival people who have the resources already 
Cooling and powerbil become big topics. Personally should rather focus to change location, vs deal with those absurd living standards here in europe.

Right now, no ~ sorry



The_King said:


> I also have a 4000 C19 kit capable of doing 3800 CL14-14-14. Want to try that with real 1T tomorrow as well.


Those Vipers can do 4000 14-14-14 near that 1.6-1.65v range for daily. 
4000 15-15 is a bit childs play (sorry that's rude) , but it's very close to 3800 14-14.

Glad you found a good kit , hopefully better than mine 🙏
I try to snipe right now the 6000 Samsung Vipers on DDR5.
But only RGB versions remain, very unfortunate.
Can't believe whole industry struggles with Samsung kits. Seen only one person that got them over 7600.
But most of the time is into RTX/NAVI right now and this AM5 build.


umea said:


> o/ long time no see


o/


umea said:


> anyone have opinions on B550 Unify vs B550 Unify-X vs X570S Unify-X Max?
> 
> decided to stick to this platform for a while and going to be selling off a bunch of pc parts (including motherboards i will never use). wanna move to ATX mobo (more room, more m.2 slots) but was curious about what yall think about each. not entirely sure if i'll grab these but wanted to have a reference point.
> 
> for reference im in canada, so this is what the pricing looks like:
> 
> 
> also the EVGA x570 dark is a potential option.


X570S is a great board, with a great pricetag.
So is the EVGA DARK.
If there are sub 130CAD difference, maybe pick EVGA.

B550 Unify-X is a gamble.
Too many boards die by flashing (EEPROM issue) or by CPU(VDD)-1P8 voltage, the one input voltage we push to 2.06-2.1v
On MSI boards, it's directly connected to the EEPROM ~ which is an 1.8v part. It can handle 1.93v spikes but repetitive and long term ~ it kills them. // 1.86 has to be just fine enough
This goes for X570's too
And X570S , but here rather the Flashback MCU dies faster

In general i should not blame MSI - nobody should've exceeded this 1.9v
Yet unfortunately it's close to VDD MISC on AM5. Similar properties and issues
Unify's ROM dies by voltages over ~1.9 volt on this rail.
ASUS Gigabyte and ASRock boards probably don't have this, but now is an ASRock PCH issue going on from 3xx onwards. Since the 5000series upgrade given.

If you want to gamble, B550 is great
just flash rom by hand from now on
Or X570S is great, but then it's premium. So are other boards.
But also again, community has unlocked bioses ~ just then EVGA Team makes good boards with good bioses. *🤭*


umea said:


> Or... to save money, if there's any other good ATX boards with 2 dimms rather than 4.


Ah, can't say 
ITX boards do you well with AM4
But considering FCLK and memory OC ~ that 2 DPC ProArt board, works equally well for my tight timings, high FCLK + low procODT too
I don't think it matters too much , sub 4400MT/s. Boards follow AMD's enforced design. This is not comparable to intel.


----------



## Veii

MrHoof said:


> 22tRAS/36tRC 1 cycle stable


Push tRTP to 8, tWR to 16 then 
tRAS here is tRCD + tRTP , as split read and writes
Writes should happen instant, but you have headroom

But try before that push, to increase VDIMM a bit
And get away that lower tRCD_WR

EDIT:
@MrHoof 
I ment this


----------



## umea

Veii said:


> o/
> 
> X570S is a great board, with a great pricetag.
> So is the EVGA DARK.
> If there are sub 130CAD difference, maybe pick EVGA.
> 
> B550 Unify-X is a gamble.
> Too many boards die by flashing (EEPROM issue) or by CPU(VDD)-1P8 voltage, the one input voltage we push to 2.06-2.1v
> On MSI boards, it's directly connected to the EEPROM ~ which is an 1.8v part. It can handle 1.93v spikes but repetitive and long term ~ it kills them. // 1.86 has to be just fine enough
> This goes for X570's too
> And X570S , but here rather the Flashback MCU dies faster
> 
> In general i should not blame MSI - nobody should've exceeded this 1.9v
> Yet unfortunately it's close to VDD MISC on AM5. Similar properties and issues
> Unify's ROM dies by voltages over ~1.9 volt on this rail.
> ASUS Gigabyte and ASRock boards probably don't have this, but now is an ASRock PCH issue going on from 3xx onwards. Since the 5000series upgrade given.
> 
> If you want to gamble, B550 is great
> just flash rom by hand from now on
> Or X570S is great, but then it's premium. So are other boards.
> But also again, community has unlocked bioses ~ just then EVGA Team makes good boards with good bioses. *🤭*
> Ah, can't say
> ITX boards do you well with AM4
> But considering FCLK and memory OC ~ that 2 DPC ProArt board, works equally well for my tight timings, high FCLK + low procODT too
> I don't think it matters too much , sub 4400MT/s. Boards follow AMD's enforced design. This is not comparable to intel.


thank you as always for your in depth reply. i was considering the x570 dark, but was hesitant as there don't seem to be many people using it (thus not entirely sure how well it performs with ram stuff, despite it in theory performing well).

buying in the US and then importing it is also an option, as i live near the border. decided to put together a price list of canada vs US.
CAD always first, but the country the price is from is on the left 









i guess i should probably stick to my b550 phantom itx so long as it fits my use case  the creator board looks interesting though. if i ever feel like it's limiting me i'll go from there 

i will bookmark your reply and keep it in mind for the future 

for now, i should probably try to bin a 5800x3d that doesn't have a hole at 1900fclk, or one that can handle higher fclk better, but i think the latter is a fools errand


----------



## Veii

umea said:


> the creator board looks interesting though. if i ever feel like it's limiting me i'll go from there


I can't recommend it 
I mean it runs, but it's not special special

Thunderbolt-Audio doesn't work on B550 for what i need it, and thunderbolt by bios design is capped/not working on 1xx/2xx series
(no PBS options for first ROM section)
Even if PCH should supply the lanes.

The dark looks good, 400 bucks are a lot of money.
It's near the entry price of AM5, so you might as well 😅

The X3D should run great on anything B450/x470
(be aware gigabyte boards had core overvoltage issues on 3/4/TR4 series) ~ just sensorics issues, only 2 were fine

I don't know what to recommend. Boards are pretty much the same
VRM/Mosfet differences exist for clean current supply , but in reality all meet up AMDs enforced targets.
As long as you enforce voltages and settings - AGESA behaves.

The dark is the only board with intentionally different design.
Going with it, will surely not follow common voltage and impedance settings.
But i mean, so doesnt also the ITX to most of the parts.

I can't 
I like everyone of the AIB's equal.
Some boards have little issues, but irrelevant as 90+ % resolves by firmware updates.
I like ASRock boards right now, before too - but they are booring. Stable but booring // no Aqua's or OC-Formula's 
MSI has many options and a nice OC colleague who works for them , before with ASRock
Gigabyte has people that push them and Buildzoid gives good content with them. They also learn
Biostar would be interesting to try, but they have their eastern region as support.
ASUS is always a hit and miss, and when it works it works. You have to be selective and never trust auto values.

For me, i couldn't care less ^^'
1DPC over 2 DPC, and design over pricetag.
In AGESA all are the same on AM4.
The board won't limit you, that's all i can say. The Firmware will, but that is equally good or equally bad on all of the boards 

I like EVGA too,
it's refreshing to have somebody that doesn't blindly follow the shepherds pants
(oh that sounds maybe too rude, but i know AIB & ODMs have a hard time. not just NVIDIA who causes trouble)

EDIT:
I should note that my ASUS board overvolts memory by around 45-50mV from input
It's no wonder why sensorics are missing. The ASRock was a bit more tame -10~12mV
Buut also wouldn't wonder of users reporting "i can run less vdimm on ASUS"
Of course you can , haha

It's no issue, but considerable when you compare results with other users


----------



## MrFart

I was able to make this 4x8GB setup stable (and running at the correct stock speeds) thanks to @Blameless and I'm looking for additional advice on how I can improve it/optimize it a little bit more if possible.
I can tolerate 1.38 or maybe 1.4v max for the DRAM if I stand to gain significant latency cuts and/or some more bandwidth. If not, I guess I'll just leave it like this.

Thanks
(4x8GB Crucial Ballistix 3600 CL16 Micron E-die C9BLM (CT40A1G8SA-045M:E))


----------



## Veii

MrFart said:


> Crucial Ballistix 3600 CL16 Micron E-die


tRTP 12, tWR 24
tRAS 48 , tRC 66

tWTR_S 4 / tRRD_S 4 ~ tFAW 16
SCL 4-4

tRDWR 9
tWRWR SD/DD 8
If that fails, same settings but tRAS 48 (oh , yea 48 will not fail haha)
Good luck !


----------



## MrFart

Veii said:


> tRTP 12, tWR 24
> tRAS 48 , tRC 66
> 
> tWTR_S 4 / tRRD_S 4 ~ tFAW 16
> SCL 4-4
> 
> tRDWR 9
> tWRWR SD/DD 8
> If that fails, same settings but tRAS 48 (oh , yea 48 will not fail haha)
> Good luck !


Thanks, this would be at 1.4v right?


----------



## Veii

MrFart said:


> Thanks, this would be at 1.4v right?


You can try
Just get tRC = tRP+tRAS
and RAS further up, that's too low for micron behavior


----------



## MrFart

Veii said:


> You can try
> Just get tRC = tRP+tRAS
> and RAS further up, that's too low for micron behavior



















Well, looks like it's either the same within margin of error (not being in safe mode) or slightly worse, and that's at 1.4v.


----------



## Veii

MrFart said:


> View attachment 2578059
> View attachment 2578060
> 
> 
> Well, looks like it's either the same within margin of error (not being in safe mode) or slightly worse, and that's at 1.4v.


Is this the first run ?
You should always count the 2nd one only
Safe mode is not reporting accurate results

Run TM5, might be unstable 
tCKE would be 6 here
Also check tPHYRDL when you change both dimms, if one peaks to 28


----------



## Fliperx

ManniX-ITA said:


> My guess is that ASUS DOCP sucks.
> It's a source of the worst possible issues, I can confirm.
> Still better than the sister ASRock mess with XMP.
> 
> View attachment 2577386
> 
> 
> Set the VSOC to 1.125 in BIOS or you'll always end up in some weird issues with memory.
> Set manual instead of Auto what is marked in yellow.


Thanks, I finally managed to start windows at 3600MHz. Now a new problem has arisen and that is that it takes a long time to reboot or shut down. Sometimes I see that the ram leds turn off for a while and then turn back on and then the pc restarts or shuts down. Any recommendations?


----------



## The_King

Veii said:


> Please try:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Both as comparison with Benchmate y-cruncher 2.5b & aida64
> (trow away the first result, without ethernet cable)


I could not do RC 36 got 37 to boot but was unstable think it maybe because of the low VDIMM.
Aida performance took a hit for me. I lost 1K read and around 10K copy latency is also around 1ns higher. WRRD 1 cause weird stability issues this also maybe be an issue related to my lower VDIMM.

Sorry missed this. Still seems to be a big drop in Aida Copy performance.


> tRAS here is tRCD + tRTP , as split read and writes


----------



## Blameless

MrFart said:


> View attachment 2578060
> 
> 
> Well, looks like it's either the same within margin of error (not being in safe mode) or slightly worse, and that's at 1.4v.


I'm less experienced with Micron based memory, but...

Probably don't need 1.4v yet. I'd probably test at 1.36-1.38 and bump it as needed as you tighten things down. RttWr probably doesn't need to be 120 (RZQ/2), try 80 (RZQ/3). Might keep the memory slightly cooler.

tRAS should be 42 there (tRAS = tRC - tRP), to start off with. 8Gb Micron dies should handle it fine at only 3600.

tWRWRSD and tWRWRDD 6/6 or 7/7 should be faster than 8/8, if stable.

I would try to reduce tRRD_L and tWTR_L. The former should handle 6 and the latter 12.

If tRDWR of 8 was stable, I'd use that. You may also be able to reduce tRTP.

Beyond that, it will mostly be down to trying to reduce tRFC (see if 560 works) or increase memory clock further (FCLK permitting).



The_King said:


> I could not do RC 36 got 37-38 to boot but was unstable think it maybe because of the low VDIMM. With 1.46V RC 39 was the only option that booted into windows without issues.


My B-die isn't stable with tRC below 38 until past 1.5 vDIMM.


----------



## The_King

Blameless said:


> My B-die isn't stable with tRC below 38 until past 1.5 vDIMM.


 Will give it 1.5V and see if that helps.


----------



## Veii

The_King said:


> Sorry missed this. Still seems to be a big drop in Aida Copy performance.


You overshoot potential maximum on write - target is 30399
Are you on Hydra , else something is wrong with your Aida

Target is to split it, which focuses on tRTP
Minimum RTP would be 6 on DDR4 and 12 on DDR5
It depends on CCDS/L factors.

On SR , tBurst-Chop should be usable as 4, which would also be the bare minimum tRRD_S value and bare minimum RDRD SD value. 
Same for bare minimum SCL (technically, but i question)
_Longs can be higher but _Shorts have to follow tCCDS/L 

also _L's follow for minimum value the same CCDS limit, which is the burstchop limit
Bellow can be set, but bellow this should be autocorrection.

My issue, dual rank is 8 it's not 4
I don't think tRRD bellow 8 on dual rank has to make any sense, although i know we run it.
This drop is instability , it only happens if writes are delayed. 








Also 9 ?
Are you sure you dont run hydra which messed up zentimings readout ?


----------



## The_King

I used Hydra before its not running on my system at the present moment. New windows install I did not even download it yet.
Increasing VDIMM to 1.5V I was able to do RC 36. I will download new version of AIDA and see if there is any difference.
Will install Benchmate today as well.



> Also 9 ?
> Are you sure you dont run hydra which messed up zentimings readout ?


did you not ask me to run that at 9? I maybe read the screenshot incorrectly tCKE 9?
Not running Dual rank setup. just 8GBx2. I can run DR setup has I do have 4 X Patriot 4000 C19s DIIMMS

Knew something was wrong! I read the screenshot incorrectly 🤦‍♂️ 









In my defense you did post this.


----------



## Veii

The_King said:


> In my defense you did post this.


Oh my, i'm sorry
I notice the issue, but not the mistake. Sleepy times
Yes yes absolutely mean tCKE  My bad.
The whole blob of text shifted upwards (i use shareX for onscreen editing, lazy editing)

But hey, soo for something "Different Dimm" that is "not used on single rank"
The bandwidth cut (which is very close to WRWR SCL 14-15) ~ is honestly speaking, denying such claims 
* or it's just the huge SC delay

I still doubt it's the main contributor of the issue, and it rather forced a chain on changes.
A delay of 3 clock can not do such strong cut in write bandwidth. (Write access delay)
But the mistake found something, thank you~
I'll look closer now.


----------



## blodflekk

on DR at 3800, should tCKE be 9 or 8 ?


----------



## Veii

blodflekk said:


> on DR at 3800, should tCKE be 9 or 8 ?











-1
On skylake and earlier, always -1


----------



## The_King

@Veii CPU Auto PBO Auto. Everything Else AUTO beside DIMMs


----------



## The_King

@Veii those changes brought my Super Pi time down by almost 5 seconds with CPU on AUTO and -CO. Which is not bad at all. 👏


----------



## Veii

The_King said:


> @Veii those changes brought my Super Pi time down by almost 5 seconds with CPU on AUTO and -CO. Which is not bad at all. 👏
> View attachment 2578159


too small change

WRWR's at 8
then try CAS 14,
If it boots RDWR down one

i think tWTR_S 3 is not doing you well , or tRRD_L is too low
Something looks slightly odd


----------



## blodflekk

Veii said:


> -1
> On skylake and earlier, always -1


I have been looking through this on trfc mini, but didn't understand it. So you say 9 for SR, 8 for DR ?


----------



## bonet69

MrHoof said:


> Baseline stable stettings.
> 
> 
> 20tRAS/34tRC 100 errors in 5 sec , (data corruption possible sfc found no issues tho)
> 21tRAS/35tRC 0/2/10 errors in 2 mins
> 22tRAS/36tRC 1 cycle stable
> also 3/10 tWRTS/L seem to work better then 3/8.


Hii, if u manage to get this ram working with GDM off on asus board send me pm because i think i have tried everything wihtout success... Turn on GDM and the errors will be gone, but as said keep trying and maybe u find how to make it work, since i couldnt....

My settings for your ram 1.45v gdm on fully tested:

Currently with this new 5800x3d i cant go past 3733 without wheas, but before i was running 4000 cl14 with a previus 5800x cpu, never could make it work this DR rams with GDM off... this timings of the screen should be stable also with 3800mhz at 1.47v+- if its not u may need to up trcdrd to 15 it depends on ram binning...

Regards


----------



## blodflekk

Is there any room for improvement here? Things I've tried so far and couldn't stabilize: tRCDRD 14, tWTRS 3, tWTRL 7, tWR 10, tRFC, tRTP 5, tWRRD 3. vDIMM currently 1.54. No temp sensor on DIMMs, no active cooling, only case airflow 011 dynamic XL


----------



## StrongForce

ManniX-ITA said:


> WHEA errors are from the CPU, not the memory.
> TM5 is a pure memory test, OCCT is RAM/CPU.
> You have VDDG IOD too close to VSOC; it's probably 1.1V.
> Either set IOD to 1000-1020 mV (you probably don't need it at 1050 with a 5600 and FCLK 1867) or if you need it higher set VSOC to 1.125V-1.15V.



Thanks I'll try, I have my SOC set on auto as I read somewhere it works fine most of the time (I guess unless you start pushing really hard clocks/timings/FCLK) I think on auto it's at 1.1, but there is vdrop.. so yea could be that ! will set it at 1.125v and see how it runs, if it doesn't help, I'll reduce a bit the IOD aswell.

The WHEA error was with memory test in occt, strange that you say it's related to CPU ! 

Just to make sure there is nothing wrong, I set ram at default speeds and ran it again, no error 1h.


----------



## MrFart

Blameless said:


> I'm less experienced with Micron based memory, but...
> 
> Probably don't need 1.4v yet. I'd probably test at 1.36-1.38 and bump it as needed as you tighten things down. RttWr probably doesn't need to be 120 (RZQ/2), try 80 (RZQ/3). Might keep the memory slightly cooler.
> 
> tRAS should be 42 there (tRAS = tRC - tRP), to start off with. 8Gb Micron dies should handle it fine at only 3600.
> 
> tWRWRSD and tWRWRDD 6/6 or 7/7 should be faster than 8/8, if stable.
> 
> I would try to reduce tRRD_L and tWTR_L. The former should handle 6 and the latter 12.
> 
> If tRDWR of 8 was stable, I'd use that. You may also be able to reduce tRTP.
> 
> Beyond that, it will mostly be down to trying to reduce tRFC (see if 560 works) or increase memory clock further (FCLK permitting).



















VDIMM at 1.38 which makes VTT 0.69 nice 
This seems to be noticeably better, thanks again. I tested the latency alone (under Benchmark) and got 59.8ns right after that cache and memory benchmark run so that too seems to remain the same but with higher bandwidth. I mixed and matched some of your suggestions and Veii's (kept tWRWR SD/DD at 6 didn't use 8)








Though I have no clue if this is stable, I just booted into windows, time for testing again.
(also from our previous discussion, I reduced VDDP even further)


----------



## Blameless

MrFart said:


> View attachment 2578190


Several of these timings are inexplicably looser than your last set.

tRC should be 60 (always tRP+tRAS unless you have a very specific reason to do otherwise), tRRD_S 4, tFAW 16, and tRTP 12.


----------



## MrFart

Blameless said:


> Several of these timings are inexplicably looser than your last set.
> 
> tRC should be 60 (always tRP+tRAS unless you have a very specific reason to do otherwise), tRRD_S 4, tFAW 16, and tRTP 12.


You're right my bad, you saw the first screenshots which now I edited my comment and changed them. I reset the timings to the last stable ones and only used your suggestions but then forgot that I ignored Veii's timings so I changed them again and updated the comment accordingly. tRC should be correct now if you refresh.


----------



## The_King

Veii said:


> too small change
> 
> WRWR's at 8
> then try CAS 14,
> If it boots RDWR down one
> 
> i think tWTR_S 3 is not doing you well , or tRRD_L is too low
> Something looks slightly odd


Something is indeed odd my temps are shooting up to 90C immediately under all core load. Not sure why it was fine a few weeks ago.
Will change thermal paste an retest. Usually it hits around 80C under all core load and creeps upwards not suppose to hit 90 off the bat!.

Won't affect Super Pi but Y-cruncher for sure.

Tested different combos of tWRS/L 3/8 vs 3/10 vs 4/8 vs 4/10 and 4/8 looks to be the best performance combo. is there another one I should try?


----------



## Priller

I think my ram will go further but 1900 IF and above have alot of issues on my board. It's also not fully tuned as Ive been playing around will alot of different bios versions.


----------



## Blameless

blodflekk said:


> Is there any room for improvement here? Things I've tried so far and couldn't stabilize: tRCDRD 14, tWTRS 3, tWTRL 7, tWR 10, tRFC, tRTP 5, tWRRD 3. vDIMM currently 1.54. No temp sensor on DIMMs, no active cooling, only case airflow 011 dynamic XL
> 
> View attachment 2578173


You could try fake 1T (1T + ~56 AddCmdSetup) which does tend to perform slightly better than T2.

tRC (and tRAS by extension) might go slightly tighter and tRFC probably has room to be tightened further, depending on temps and voltage.

SCLs at 2 often don't perform any better than 4, and in the case of tRDRDSCL, often performs worse.


----------



## KedarWolf

https://www.tomshardware.com/news/memtest86-plus-is-back-after-9-years


----------



## 99belle99

KedarWolf said:


> https://www.tomshardware.com/news/memtest86-plus-is-back-after-9-years


I seen that earlier but never thought of posting it here. I wonder how it compares to testmem5 lusmusv3?


----------



## Blameless

KedarWolf said:


> https://www.tomshardware.com/news/memtest86-plus-is-back-after-9-years


I can't seem to get it to use more than one thread on my 5800X3D + ASRock setup, which makes it pretty useless. Haven't tried other systems yet.


----------



## 99belle99

Blameless said:


> I can't seem to get it to use more than one thread on my 5800X3D + ASRock setup, which makes it pretty useless. Haven't tried other systems yet.


But isn't it a memory tester not a CPU tester? So all it needs to use is one core to run.


----------



## MrHoof

Veii said:


> Push tRTP to 8, tWR to 16 then
> tRAS here is tRCD + tRTP , as split read and writes
> Writes should happen instant, but you have headroom
> 
> But try before that push, to increase VDIMM a bit
> And get away that lower tRCD_WR
> 
> EDIT:
> @MrHoof
> I ment this


Oh I wasnt clear enough I guess only got around to test up to 1 cycle, didnt had much time yesterday, today I had atleast 30mins and passed 5 cycles.
Real testing gonna happen on the weekend. But I keep those changes in mind.



bonet69 said:


> Hii, if u manage to get this ram working with GDM off on asus board send me pm because i think i have tried everything wihtout success... Turn on GDM and the errors will be gone, but as said keep trying and maybe u find how to make it work, since i couldnt....
> 
> My settings for your ram 1.45v gdm on fully tested:
> 
> Currently with this new 5800x3d i cant go past 3733 without wheas, but before i was running 4000 cl14 with a previus 5800x cpu, never could make it work this DR rams with GDM off... this timings of the screen should be stable also with 3800mhz at 1.47v+- if its not u may need to up trcdrd to 15 it depends on ram binning...
> 
> Regards


Its mostly about correct ProcODT/RTT/DrvStr settings *IF* its archiveable. Good starting point is ProcODT 32ohm, RTT 7/3/3, DrvStr 40/20/24/30 for DualRank ClkDrvStr 40 is almost a must on most boards.
Aswell I woluld suggest SCLs of 4 instead of 2 until your done testing everything and than compare if u gain any performance setting them to 2.
Also since its not reported by Zentimings my Timings are at 1.55v so if your at 1.45v atm seems pretty good.
edit: Mine is a 14-15-15 xmp bin yours probably 14-14-14?


----------



## ManniX-ITA

StrongForce said:


> The WHEA error was with memory test in occt, strange that you say it's related to CPU !


Memory test in OCCT is actually a test that is stressing the CPU to test the memory.
TM5 is purely doing memory operations, the CPU load is very light.
If you compare the clocks while running both, the CPU clocks with TM5 should be at least 200 MHz higher on average.



Fliperx said:


> Thanks, I finally managed to start windows at 3600MHz. Now a new problem has arisen and that is that it takes a long time to reboot or shut down. Sometimes I see that the ram leds turn off for a while and then turn back on and then the pc restarts or shuts down. Any recommendations?


Means the termination it's not quite right and memory training struggles at boot.
Post a Zentimings screenshot.


----------



## Blameless

99belle99 said:


> But isn't it a memory tester not a CPU tester? So all it needs to use is one core to run.


A single thread can't put enough load on the memory to effectively test it.


----------



## ManniX-ITA

I've updated my custom power plans for Win10 and created a new one for Win11.
In my signature.


----------



## Veii

ManniX-ITA said:


> I've updated my custom power plans for Win10 and created a new one for Win11.
> In my signature.


Barely a negative difference on Win11
Maybe slightly slower on dpclatency , mouse feels sliightly slower
But powersaving comes well. Likely a bigger difference once C6 works.
Well usable , thank you 


Spoiler: MLC ~ no difference, very subtle














Attached is personal service config for a gaming/daily system;
~ Image Acquisition has to be enabled for capture cards to work
~ Wlan AutoConfig has to be enabled for Wifi-Cards to work
~ ASUS Com Service if existent, is disabled
~ AMD External events for freesync, works - even without Driver GUI
~ PrintSpooler for printing, is disabled
~ Defender is put silent & MS Account Sing-in is put quiet
~ XBOX services are disabled, but can be put back on Manual for MS-Store games

Nothing else should cause trouble or be of importance.
Chained together services are put on Manual or Trigger-Manual to chainload.
Will reset to disabled on any reboot, until X Target Programm is launched again

Instructions:


----------



## Veii

Veii said:


> Attached is personal service config for a gaming/daily system;


Not too shabby, post it
// please test how big the difference is for you guys (it's hard to restore something once it's gone)
* initially dropped down FCLK by pushing high LCLK for PCIe 4.0 tests








Before:








But i have a slight issue:
I see indeed zero change between
15-15-15-15-30-45, WRWR SCL 4, tRRD 7, tWTR_L 12,
and this current. Even if current has to be better on potential usable bandwidth

Nothing on superpi, same exact time. Pretty much perfect same time, maybe 0.1sec test-by-test variance
Feels like either core freq is too low past 2000 1:1
or something else with cache access time is slower
Potential max is ~200MB/s higher by following more JEDEC or rather an own idea of it.
But realistic max did not wiggle at all. It wasn't usable on single-core focused tests.
Y-cruncher will make sense, but not here where it thermal throttles.


----------



## Toma

This is my 2x16GB (E-die) stable setup and I'm looking for additional advice on how I can improve it.









Thanks


----------



## MrFart

I'm trying to get this puppy to run at 4000 MCKL and 2000 FCKL. Someone (The King on TPU) told me to just push it to 3800/1900 from the stock 3600 it should be stable and it kinda is (obviously not fully tested but it passed TM5 1usmus default).

I set the clocks to 4000/2000 and I can boot into windows fine and run AIDA64 cache and mem. Tried TechPowerUp's MemTest64 just now and got an error already in the first loop. Any suggestions? (obviously with the stock timings from 3600 and now 3800 it's not gonna be stable that's asking too much, but I'm not sure what to change)


----------



## The_King

MrFart said:


> Someone told me to just push it to 3800/1900 from the stock 3600 it should be stable and it kinda is (obviously not fully tested but it passed TM5 1usmus default).


That someone was me. 🙂
For 4000MT you have to increase RCDRD to 19. That kit won't do RCDRD 18 @ 4000MT 











(I was able to get 3933 CL16 RCD 17 to pass using another kit with the same C9BLM IC's but not sure why I had issues with RCDRD 18 @ 4000MT)


----------



## The_King

Toma said:


> This is my 2x16GB (E-die) stable setup and I'm looking for additional advice on how I can improve it.
> View attachment 2578393
> 
> 
> Thanks


Are those C9BJZ ICs? Then you can probably go to 3933 CL 15/16 RCDRD 19. 3800 CL14 should be doable with 1.45V as well


----------



## MrFart

The_King said:


> That someone was me. 🙂
> For 4000MT you have to increase RCDRD to 19. That kit won't do RCDRD 18 @ 4000MT
> 
> 
> View attachment 2578430
> 
> 
> (I was able to get 3933 CL16 RCD 17 to pass using another kit with the same C9BLM IC's but not sure why I had issues with RCDRD 18 @ 4000MT)
> View attachment 2578451


Hey there! I didn't realize you were here as well. (pls don't judge my username, it was a long long time ago and I can't change it 😅)

I'm conflicted, idk if I should aim for 3800 CL14 or 4000 CL whatever for that 2000 FCKL. In other words, what's better, 2000 FCKL or lower latency with 3800?
The current 3800/1900 CL16 setup was stable last night on memtest86 4 passes.


----------



## Veii

For 2000 14-14 you'll need around 1.64ish volt
Near that 1.63-1.66 sweetspot
2000 C15 is not too hard to make - near 1.56-1.62 should work out
Its close to 3800 C14 flat. 4200 C15-15 is quite hard ^^*

For 16-18 you should test, thats "low" ish
Eh 4000 C16 is not too bad
But your both memtests mean zero @MrFart @The_King

1usmus_v3 above 20 cycles, usually 25
anta's extreme above 6 cycles
HCI / Karhu above 10 000%
GSAT on linux is not too bad either, but i think 1usmus_v3 finds more inconsistencies

Pick one or two
Memory has capacitors, ICs are similar ~ not silicon. Those discharge by heat
Thermal equlibrium on AIOs starts at 15min - on air coolers its the room
The room equalizes by around the 60min mark. No memtest bellow 55+ minutes is worth anything, except to test for catastrophic failure.
20+ cycles on 1usmus_v3 are needed to test even a bit of tRFC dropout change. Memory autocorrects, you need to increase delay to have it show any flukes by time.
Recommended again ~ 25+ cycles. For 32gb that will take ~3h , for 16gb ~1:30

* FCLK bump shows rather, than memory OC


----------



## The_King

I was testing if any of my other kits can do Real 1T like the Vipers 4133.
So put the Viper 4000 C19 in but obviously the same settings wont work because that will be too easy. 
The 4133 C19 was fine with ClkDrvStr 24 this need 60 to pass even 3 cycles. Will run a full 25 cycles test soon.











Veii said:


> But your both memtests mean zero @MrFart @The_King


Fully agree 25 cycles should be minimum to say that is "24/7stable" that is the name of this thread after all. However Micron RAM is not like Samsung B-die you can do 100 cycles with completely stupid values and it wont error in some cases with TM5.

My short tests are mainly to show What CL and RCDRD is possible to stabilize with the Micron Rev B/E DIMMS and not a 24/7 stable setup but can be used has a starting point for many who don't even know where to start.

I also did 4200 CL15 with some Micron Rev B 16GB SR. Only 5 cycles though to 37 minutes so not complete trash. 
10 cycles would have taken it over an hour but I really regret not buying another set of these has it would have made a sweet 64GB Dual Rank setup!











MrFart said:


> Hey there! I didn't realize you were here as well. (pls don't judge my username, it was a long long time ago and I can't change it 😅)
> 
> I'm conflicted, idk if I should aim for 3800 CL14 or 4000 CL whatever for that 2000 FCKL. In other words, what's better, 2000 FCKL or lower latency with 3800?
> The current 3800/1900 CL16 setup was stable last night on memtest86 4 passes.


I would try to get 3800 CL14/15 for most people 2000 FCLK is more trouble than anything and you also have to worry about WHEA 19 errors which most ZEN 3 cpus get at 2000 FCLK. (Actually according to Veii it maybe the motherboard that's the problem with WHEA 19s and 2000 FCLk not the ZEN 3 CPUs)

So Stick for 3800 FCLK 1900. That is my advice.even 3800 CL16 will give you great performance with your dual rank setup.

Just do has Veii said try to do at least 25 cycles with TM5.


----------



## Priller

1900 IF gives me a 07 Post code but I can get it to boot with LN2 mode enabled in the bios. Its alot more stable above 1900 IF. I seem limited to 3733 regardless of what I do.


----------



## MrFart

The_King said:


> I would try to get 3800 CL14/15 for most people 2000 FCLK is more trouble than anything and you also have to worry about WHEA 19 errors which most ZEN 3 cpus get at 2000 FCLK.
> 
> So Stick for 3800 FCLK 1900. That is my advice.even 3800 CL16 will give you great peformance


If it's more trouble than it's worth, I don't want it to be honest. I'll stick with 3800/1900 and try to tighten the timings a bit more, thanks again.


----------



## The_King

Priller said:


> 1900 IF gives me a 07 Post code but I can get it to boot with LN2 mode enabled in the bios. Its alot more stable above 1900 IF. I seem limited to 3733 regardless of what I do.


Sounds like that FCLK 1900 hole that some people experience. You could still tune 3733 CL14/15/16 and get good performance and there is the option of tuning 3866/1933 as well if you cant do 1900 IF


----------



## Priller

The_King said:


> Sounds like that FCLK 1900 hole that some people experience. You could still tune 3733 CL14/15/16 and get good performance and there is the option of tuning 3866/1933 as well if you cant do 1900 IF


The 1900 IF hole was present on my 5700X and now 5900X. 3866/1933 will boot but gives out WHEA errors at a fixed rate regardless of voltage and remains that way to 4000/2000.

I think the 1900 IF hole is board/bios related and not the CPU.


----------



## The_King

Priller said:


> The 1900 IF hole was present on my 5700X and now 5900X. 3866/1933 will boot but gives out WHEA errors at a fixed rate regardless of voltage and remains that way to 4000/2000.
> 
> I think the 1900 IF hole is board/bios related and not the CPU.


Which voltages did you adjust @3866/1933. The two important ones to help with WHEA 19s are VSOC and IOD. You may need slightly over 1.2V on VSOC and between 1.05V-1.1V on the IOD.


----------



## Priller

The_King said:


> Which voltages did you adjust @3866/1933. The two important ones to help with WHEA 19s are VSOC and IOD. You may need slightly over 1.2V on VSOC and between 1.05V-1.1V on the IOD.


Ive been going through different bios revisions and have a doc with all my observations. 

3866/1933 WHEA Errors Regardless Of Voltage. PBO Off, 1.2V SOC, 1.15V CLDO VDDP, 1.1V VDDG CCD & IOD, 1.55V DIMM, 0.950 VDDP, 1.918V PLL


----------



## mus1mus

WHEA errors are related to running UCLK, MCLK, FCLK 1:1:1 ratio over 3800MHz.


On another note,

Anyone fancy a locked CPU Clock SuperPi challenge? 
Not a competition, I am basically interested in getting a new set of sticks and seeing Micron chips hitting B-Die timings and clock makes me consider my choices..


----------



## The_King

mus1mus said:


> WHEA errors are related to running UCLK, MCLK, FCLK 1:1:1 ratio over 3800MHz.
> 
> 
> On another note,
> 
> Anyone fancy a locked CPU Clock SuperPi challenge?
> Not a competition, I am basically interested in getting a new set of sticks and seeing Micron chips hitting B-Die timings and clock makes me consider my choices..


Have you ever seen Micron B-die running 3200 CL14-14-14 @1.36V ?


Spoiler: Micron Rev B 16GB SR


----------



## mus1mus

But 3200C14 is meh.. you know that..


----------



## The_King

mus1mus said:


> But 3200C14 is meh.. you know that..


4200 CL15 2100 FCLK 1:1:1? look a few post above same RAM.


----------



## MrFart

I tried replacing "Auto" tCL and tRCDRD with their normal XMP values (not reducing anything, so 16 and 18 but just not Auto) and that made me unable to POST, uhm ***?


----------



## mus1mus

That one is impressive. I am still not convinced with over 3800 tho on Ryzen 5000 tho.. still slower in my testing. Got mine to about 4266 unsynched and still looking slower. It could just be setup thus me looking at other peoples' result keenly..


----------



## The_King

MrFart said:


> I tried replacing "Auto" tCL and tRCDRD with their normal XMP values (not reducing anything, so 16 and 18 but just not Auto) and that made me unable to POST, uhm ***?


Not sure what that is. Looks like it maybe a BIOS issue. Are you running the latest version?



mus1mus said:


> That one is impressive. I am still not convinced with over 3800 tho on Ryzen 5000 tho.. still slower in my testing. Got mine to about 4266 unsynched and still looking slower. It could just be setup thus me looking at other peoples' result keenly..


Samsung B-die is probably still the best option if you going for HWBOT records. RCDRD does not scale with voltages on Micron only CL.


----------



## StrongForce

Been trying hard to tweak my ram, ended up dialing back to 3600 C16.. which honestly is a bit disapointing ( was expecting more from my kit) but I couldn't get 3733 c15 stable at all, even c16.. so I seen one post that suggested to someone to just dial back the speed and keep the same timings .. 

Of course I know there are limiting factors like the IMC, CPU and I also read that the higher tier Ryzen CPU do get you better RAM OC (is this even true ?) usually, so if I upgrade in the future (along with 2 more ram sticks to get dual rank) I'll spend some time to get something more satisfying 😄 in the meantime, here are my results : 










Test still not completed but I put it at 25 cycle and 500% to make it last as long as possible, guess that would be 10 hours ish to complete it, for now I'll consider it stable, is that safe to say after 8 hours ? 

Still havent ran benchmarks but I'm pretty confidents the performances aren't too far off what I had with 3733 c15


----------



## The_King

@StrongForce The test is taking much longer than it should because you are not running it with Admin rights.
You need to to run TM5 has Administrator. right click the icon and select run as administrator


----------



## MrFart

The_King said:


> Note sure what that is. Looks like it maybe a BIOS issue. Are you running the latest version?


I am. 7C56vAB for this board, AGESA 1.2.0.7.


----------



## Toma

The_King said:


> Are those C9BJZ ICs? Then you can probably go to 3933 CL 15/16 RCDRD 19. 3800 CL14 should be doable with 1.45V as well
> View attachment 2578432


Yes, these are C9BJZ, but everything over 1900 gives me WHEA 19 errors 😞


----------



## The_King

Got my second Patriot Viper 4000 C19 kit to do 1T as well.
@Veii WTRS/L 4/8 is much more stable than 3/8.  Any idea why this kit needed ClkDrvStr 60 vs 24 on the other one?


----------



## Veii

Spoiler: EDIT: L2 prefetcher somehow turned off. I did not notice.... 



Time to disrupt those so called "leaderboards" again, with new efficiency crown 👑🎶
// 1.62 ASUS VDIMM ~ 1.65? reality , 1.975 VDD1P8 (do not use on MSI !!), 1.235ish SOC




























40.9GB/s = 4066.66inf MT/s
TM5 passed , but i'm working on a big screenshot again - soo ETA is 4h if nothing CO related crashes 

New Memtest86 is not too bad, but only past 2nd test it becomes heavy.
1 loop & pass = 17min,
3 loops = 1:30h
and so on
probably does a small and a big one, as charge holdtime-test #9, changes
I'd agree with 3-4 loops on this, but good overnighter.

SuperPi remains to have absolutely zero scaling ~ 150ms deviance
One core seems to be not enough utilizing memory fully. Booring

EDIT:
Aand it's submittable 🤭










Yeaa, i hate this
Of course it looked too good to be true
It even benched better.
I'm sorry to let you down ~ i'll wipe the submission now.
It's cheating, i can't accept this.

2067 FCLK atm is unstable, like every stepup - with tight RRD/WTR_Shorts
If 2100 gives me 0.2ns drop, i'd be happy. But no , it's fake i'm sorry. I wish i would have noticed before but it auto changed...


----------



## RackarN

Passed with 1mus profile, now lets try extreme1. Still some testing needed to see what timings i can lower. First time overclocking RAM, there is so much still to learn lol. Still feels like timings is all over the place


----------



## The_King

Veii said:


> Spoiler: EDIT: L2 prefetcher somehow turned off. I did not notice....
> 
> 
> 
> Time to disrupt those so called "leaderboards" again, with new efficiency crown 👑🎶
> // 1.62 ASUS VDIMM ~ 1.65? reality , 1.975 VDD1P8 (do not use on MSI !!), 1.235ish SOC
> View attachment 2578593
> 
> 
> View attachment 2578594
> View attachment 2578598
> View attachment 2578597
> 
> 40.9GB/s = 4066.66inf MT/s
> TM5 passed , but i'm working on a big screenshot again - soo ETA is 4h if nothing CO related crashes
> 
> New Memtest86 is not too bad, but only past 2nd test it becomes heavy.
> 1 loop & pass = 17min,
> 3 loops = 1:30h
> and so on
> probably does a small and a big one, as charge holdtime-test #9, changes
> I'd agree with 3-4 loops on this, but good overnighter.
> 
> SuperPi remains to have absolutely zero scaling ~ 150ms deviance
> One core seems to be not enough utilizing memory fully. Booring
> 
> EDIT:
> Aand it's submittable 🤭
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Yeaa, i hate this
> Of course it looked too good to be true
> It even benched better.
> I'm sorry to let you down ~ i'll wipe the submission now.
> It's cheating, i can't accept this.
> 
> 2067 FCLK atm is unstable, like every stepup - with tight RRD/WTR_Shorts
> If 2100 gives me 0.2ns drop, i'd be happy. But no , it's fake i'm sorry. I wish i would have noticed before but it auto changed...


Why not try with Addr 56 ? You can get pretty close to Real 1T latency maybe within 0.2ns with better timings. Im not running any latency enhancements stock windows install.
I probably need more voltage to stabilize this but cant adjust VDD18 on this B450.


----------



## The_King

RackarN said:


> View attachment 2578725
> 
> 
> Passed with 1mus profile, now lets try extreme1. Still some testing needed to see what timings i can lower. First time overclocking RAM, there is so much still to learn lol. Still feels like timings is all over the place


Crucial Ballistix MAX 4400 C19s? That Kit can do higher FCLK with the same RCD 17 1966 FCLK.

Not sure why you cant run tFAW 16 with RRDS 4 but SCLs can go 4s. RDWR 8 or 9?
Higher RC can actually improve performance and latency in AIDA64.

I will retest all my Micron RAM and run at least 25 cycles once I get some time to do so.


----------



## RackarN

The_King said:


> Crucial Ballistix MAX 4400 C19s? That Kit can do higher FCLK with the same RCD 17 1966 FCLK.
> 
> Not sure why you cant run tFAW 16 with RRDS 4 but SCLs can go 4s. RDWR 8 or 9?
> Higher RC can actually improve performance and latency in AIDA64.
> 
> I will retest all my Micron RAM and run at least 25 cycles once I get some time to do so.


Yeah Crucial Ballistix MAX 4400 C19, i can boot 2066 but WHEA above 1933 it seems. was trying to force 2000 but it was a no-go.
Had some memory error after an hour testing so i dialed back the changes i did (rookie mistake of changing too much) but it seems like SCL didnt want to go 4 4, im gonna see if i can find the culprint soon =) Thanks!


EDIT: so i changed RRDS 4 and tFAW 16, SCL's 4 to begin with but it gave me WHEA after 3 minutes of testing.

changed RRDS to 6 again and tFAW 24, so far so good. SCL might be fine at 4 atleast (only 5 min testing thus far..)


----------



## MrFart

Do I need more testing or can I safely assume this is 99.9% stable? (no GPU load during those 6 hours, how bad can ambient heat really be for a 3800 config?)


----------



## The_King

This should be good for spot 22 provided I pass 25 cycles TM5?
No WHEA errors also no boost override applied here.











MrFart said:


> View attachment 2578745
> 
> 
> Do I need more testing or can I safely assume this is 99.9% stable? (no GPU load during those 6 hours, how bad can ambient heat really be for a 3800 config?)


Looks good to me. Veii may complain about tPHYRDL being at 28 instead of 26.

Try CL15 and see if that changes that to 26 and if its stable. Nice work  
3800 CL15 may need slight increase in VDIMM voltage.


----------



## MrFart

The_King said:


> Looks good to me. Veii may complain about tPHYRDL being at 28 instead of 26.
> 
> Try CL15 and see if that changes that to 26 and if its stable. Nice work
> 3800 CL15 may need slight increase in VDIMM voltage.


Thanks, I uh, kinda have a problem with my current BIOS I can't change tCL or tRCDRD to anything other than Auto (even if I simply put the default values of 16 and 18) without losing the ability to POST (already posted about it here).
Veii did complain about tPHYRDL but I didn't find it in the BIOS so I don't know how I'm supposed to change it.


----------



## RackarN

The_King said:


> This should be good for spot 22 provided I pass 25 cycles TM5?
> No WHEA errors also no boost override applied here.



Crazy high Read and low Latencey! good job!


----------



## The_King

MrFart said:


> Thanks, I uh, kinda have a problem with my current BIOS I can't change tCL or tRCDRD to anything other than Auto (even if I simply put the default values of 16 and 18) without losing the ability to POST (already posted about it here).
> Veii did complain about but I didn't find it in the BIOS so I don't know how I'm supposed to change it.


The only way I got tPHYRDL to go down to 26 was to change CL to15 with my Micron RAM.

Have you changed GDM option in the BIOS from AUTO to 1T?


----------



## MrFart

The_King said:


> The only way I got tPHYRDL to go down to 26 was to change CL to15 with my Micron RAM.
> 
> Have you changed GDM option in the BIOS from AUTO to 1T?
> View attachment 2578757


Yup, stock would be 2T with 4 sticks but I changed it back to 1T.


----------



## Blameless

MrFart said:


> no GPU load during those 6 hours, how bad can ambient heat really be for a 3800 config?


In my case, it's the difference between memory at 40C and memory at 70C, but this is a SFF box.

You may or may not need to go to the same extremes I would, but I highly recommend testing at your personal worst case temps, or you may be in for an unpleasant surprise at some point.


----------



## The_King

Blameless said:


> In my case, it's the difference between memory at 40C and memory at 70C, but this is a SFF box.
> 
> You may or may not need to go to the same extremes I would, but I highly recommend testing at your personal worst case temps, or you may be in for an unpleasant surprise at some point.


Micron E-die is nowhere as sensitive to temps VS Samsung B-die. Unless the OP is running a hairdryer inside his case, I think he would be fine. But wont hurt to test it.
His voltages are way to low to cause overheating issues. 1.39V


----------



## MrFart

Blameless said:


> In my case, it's the difference between memory at 40C and memory at 70C, but this is a SFF box.
> 
> You may or may not need to go to the same extremes I would, but I highly recommend testing at your personal worst case temps, or you may be in for an unpleasant surprise at some point.


I have a stupid number of fans (7 lol, 5x140 and 2x120, 4 intake and 3 exhaust, midtower case) and one of them blows directly over RAM into the cpu cooler. It will surely get warmer with the gpu spitting out heat but I doubt it's gonna be at 70c.


----------



## Blameless

The_King said:


> Micron E-die is nowhere as sensitive to temps VS Samsung B-die. Unless the OP is running a hairdryer inside his case, I think he would be fine. But wont hurt to test it.
> His voltages are way to low to cause overheating issues. 1.39V


Not a very through test of that Micron stuff, but yes, I am aware that it's generally less sensitive to temps than Samsung.



MrFart said:


> I have a stupid number of fans (7 lol, 5x140 and 2x120, 4 intake and 3 exhaust, midtower case) and one of them blows directly over RAM into the cpu cooler. It will surely get warmer with the gpu spitting out heat but I doubt it's gonna be at 70c.


Specific temp is less important than it being representative of the worst temps you'll see, plus whatever headroom you find reasonable, if you want to be as confident in long term stability as possible.


----------



## Tirade75

Probably a shot in the dark but I think these are voltage related errors (I'm like 3 days old with mem overclocking). Errors all occurred in the same loop around 1.5 hours in. Thoughts on where I should start raising voltages? VDIMM is 1.45v


----------



## Nucky

I have been struggling to get this any tighter and I'm sure I have several settings way off (I'm just not sure how to fix it). I'm currently running 4x8 f4-3600c15 @3733c16 1.45v. Trying to squeeze as much performance out of this 5900x as possible to hold off upgrading until 7xxx3d. Any pointers or help would be greatly appreciated as I feel like I'm just going in circles on my own.


----------



## Blameless

Tirade75 said:


> Probably a shot in the dark but I think these are voltage related errors (I'm like 3 days old with mem overclocking). Errors all occurred in the same loop around 1.5 hours in. Thoughts on where I should start raising voltages? VDIMM is 1.45v
> 
> View attachment 2578776
> View attachment 2578777


Dual-rank memory is generally going to be receptive to Rtt tuning. Try 6/3/3 to start with. Drive strength may also be worth experimenting with.

As far as voltage, there is a chance you need more vSoC and VDDG IOD at 1900 FCLK, even on an X3D. Beyond that, it's going to be vDIMM.



Nucky said:


> View attachment 2578788
> 
> I have been struggling to get this any tighter and I'm sure I have several settings way off (I'm just not sure how to fix it). I'm currently running 4x8 f4-3600c15 @3733c16 1.45v. Trying to squeeze as much performance out of this 5900x as possible to hold off upgrading until 7xxx3d. Any pointers or help would be greatly appreciated as I feel like I'm just going in circles on my own.


Can you check Thaiphoon and see what ICs those are? Some F4-3600C15-8GTZ is Samsung B-die, but some is not.


----------



## The_King

@Blameless TRFC is showing 159ns one of the easy way to tell if its B-die or not. 

@Nucky
Link to Thaiphoon burner


Thaiphoon Burner - Official Support Website


----------



## Nucky

The_King said:


> @Blameless TRFC is showing 159ns one of the easy way to tell if its B-die or not.
> 
> @Nucky
> Link to Thaiphoon burner
> 
> 
> Thaiphoon Burner - Official Support Website





Blameless said:


> Dual-rank memory is generally going to be receptive to Rtt tuning. Try 6/3/3 to start with. Drive strength may also be worth experimenting with.
> 
> As far as voltage, there is a chance you need more vSoC and VDDG IOD at 1900 FCLK, even on an X3D. Beyond that, it's going to be vDIMM.
> 
> 
> 
> Can you check Thaiphoon and see what ICs those are? Some F4-3600C15-8GTZ is Samsung B-die, but some is not.



They are b die


----------



## Blameless

Nucky said:


> They are b die


You'll probably want a bit more vSoC as it's too low for the VDDG IOD you are using. CLDO CDDP is also about 200mV higher than it should have to be.

Timing wise, you should be able to go tighter on tRC (and tRAS), tRRD_S and L (try 4/6), tFAW (16), and tRDWR (12), at the very least.


----------



## Nucky

Blameless said:


> You'll probably want a bit more vSoC as it's too low for the VDDG IOD you are using. CLDO CDDP is also about 200mV higher than it should have to be.
> 
> Timing wise, you should be able to go tighter on tRC (and tRAS), tRRD_S and L (try 4/6), tFAW (16), and tRDWR (12), at the very least.


I’ve updated those sub timings and got some improvement. Any recommendations to try for the other settings? Soc, cldo, trc, and tras ? Also I really appreciate the help.


----------



## Tirade75

Blameless said:


> Dual-rank memory is generally going to be receptive to Rtt tuning. Try 6/3/3 to start with. Drive strength may also be worth experimenting with.
> 
> As far as voltage, there is a chance you need more vSoC and VDDG IOD at 1900 FCLK, even on an X3D. Beyond that, it's going to be vDIMM.


Ahh nice, something new to learn about! OK, I'll start with RttNom-6 / RttWr-3 / RttPark-3 as Id rather leaving raising voltage as a last resort since my goal was maximize lower voltages rather than chase the speed demon. Thanks a ton for the help and I'll update after a few runs.


----------



## Blameless

Nucky said:


> Soc, cldo


Hard to tell with droop, but 1.125v SoC should be sufficient.

CLDO VDDP (and CPU VDDP, if you have one) should both be around 0.85v to 0.9v with your memory configuration.



Nucky said:


> trc, and tras ?


Try 32 tRAS and 48 tRC. tRC should always equal tRP + tRAS, unless you have a very specific reason for them not to.


----------



## Nucky

Blameless said:


> Hard to tell with droop, but 1.125v SoC should be sufficient.
> 
> CLDO VDDP (and CPU VDDP, if you have one) should both be around 0.85v to 0.9v with your memory configuration.
> 
> 
> 
> Try 32 tRAS and 48 tRC. tRC should always equal tRP + tRAS, unless you have a very specific reason for them not to.


Upped SOC, dropped vddp, and ccd/iod are the same. Perf is a little better. latency is still about the same. I would really like to get as close to 60ns or below as I can. Don't know if that is possible without gdm disabled and I haven't had any luck whatsoever turning that off even at 3600. 

Thanks again for your time. It's helped me quite a bit today. Memory tuning has always been a struggle for me.


----------



## Blameless

Nucky said:


> View attachment 2578874
> 
> 
> Upped SOC, dropped vddp, and ccd/iod are the same. Perf is a little better. latency is still about the same. I would really like to get as close to 60ns or below as I can. Don't know if that is possible without gdm disabled and I haven't had any luck whatsoever turning that off even at 3600.
> 
> Thanks again for your time. It's helped me quite a bit today. Memory tuning has always been a struggle for me.


What vDIMM are you using?

Some additional advice:

tWR should be tRTP * 2
try making tWRWRSD/DD both 7 and tRDRDSD/DD both 5
Rtts 7/3/3, or 7/3/2 if the former isn't stable
DrvStr at 40/24/30/24, or 30/24/24/24
tCKE 8 or 9
tWTR_L 12
tRFC/2/4 at 288/216/136

If you want to try GDM off again, make sure you set 2T command rate. SCLs at 5, tRTP at 9 and tWRRD at 4 might help. If that works you can try tightening them back up, starting with tRTP.


----------



## Frosted racquet

@Nucky If current timings are stable in TestMem, try lowering tRDWR to 10 or 9, tWTRL 8, tWR 12 and tRTP 6, tRDRDDD 4, tWRWRDD 6.
If tRDWR isn't going any lower, try increasing tCWL to 16

Was slower than Blameless when writing


----------



## Veii

Tirade75 said:


> Probably a shot in the dark but I think these are voltage related errors (I'm like 3 days old with mem overclocking). Errors all occurred in the same loop around 1.5 hours in. Thoughts on where I should start raising voltages? VDIMM is 1.45v


#10's are tRRD_S, tRRD_L, tWTR_L and RTT_NOM errors
#13 are overtemp crash issues ~ connected to "too high voltage"

#10 increase slowly tRRD_L to 5 then to 6 tiill it fades away
drop VDIMM about 20mV and #13's should go away ~ if not, you have to redesign your powering (CAD_BUS , RTT)
If VTT_MEM exists, lowering it by 50mV works too to tame higher voltage. Or increasing VPP_MEM from 2.5 to 2.55-2.6








EDIT:
Unless your set was fine, GDM off will introduce very likely new errors
It only means GDM hides them & you always had problematic powering.
GDM off exposes it, else there has to be zero VDIMM adding difference between 2T & GDM ~ if set was correct to begin with


The_King said:


> Got my second Patriot Viper 4000 C19 kit to do 1T as well.
> @Veii WTRS/L 4/8 is much more stable than 3/8.  Any idea why this kit needed ClkDrvStr 60 vs 24 on the other one?


Why do you drop AddrCmdDrv, CsDdtDrv, CkeDrv to 20 ?
40-20-20-20
60-20-20-20
are presets for usage fine-usage of SETUP timings (3-3-15, 4-4-18 +++)
* to delay them clean, and not introduce noise with DrvStrengths

Run it but moved away from SETUP-Timings, as it's not a clean math and ontop adds delay to the result
Likely helps, but RTT & CAD_BUS fixing helps more first
Later slowdown of IMC to DIMM


The_King said:


> Why not try with Addr 56 ? You can get pretty close to Real 1T latency maybe within 0.2ns with better timings


Nearly equal to half command rate slowdown. Barely any issue to GDM delay, without GDM toggles sideeffects of hiding instability
SR doesn't need 1T support, it can run it 
I see the idea, but then can you trust your timings itself ~ if you 50% slow it down in post ?

Potentially good idea is CAS +1 , tRCD_RD -1
but exploring

Seems indeed that you can go tWRWR SCL -1 = WRWR_SC +1
Works out, but SCL on 1 doesn't yet


Priller said:


> 1900 IF gives me a 07 Post code


Lower ProcODT, while increasing ClkDrvStr to compensate (if it refuses to post)
Also more SOC ~ IOD is 1050 here - SOC can't be 1075
Try 1150 to have your LLC droop it

Cautious with LN2 toggle


----------



## Nucky

Blameless said:


> What vDIMM are you using?
> 
> Some additional advice:
> 
> tWR should be tRTP * 2
> try making tWRWRSD/DD both 7 and tRDRDSD/DD both 5
> Rtts 7/3/3, or 7/3/2 if the former isn't stable
> DrvStr at 40/24/30/24, or 30/24/24/24
> tCKE 8 or 9
> tWTR_L 12
> tRFC/2/4 at 288/216/136
> 
> If you want to try GDM off again, make sure you set 2T command rate. SCLs at 5, tRTP at 9 and tWRRD at 4 might help. If that works you can try tightening them back up, starting with tRTP.





Frosted racquet said:


> @Nucky If current timings are stable in TestMem, try lowering tRDWR to 10 or 9, tWTRL 8, tWR 12 and tRTP 6, tRDRDDD 4, tWRWRDD 6.
> If tRDWR isn't going any lower, try increasing tCWL to 16
> 
> Was slower than Blameless when writing


Followed a mix of both of your suggestions. Dropped 1ns and can see some gains. Anything glaring that I missed from either of you?


----------



## Frosted racquet

For latency, test in Safe Mode to eliminate background applications interfering. You should be in the ~55ns range


----------



## Veii

Frosted racquet said:


> For latency, test in Safe Mode to eliminate background applications interfering. You should be in the ~55ns range


Safemode prevents CPPC and C6 states
Result will be worse without proper idling

If you feel like benching unrealistic scenario's
Get a bench OS. That at least doesn't cut down the Ryzen in functionality and is somewhat comparable.


----------



## Frosted racquet

Safe Mode vs Normal Mode. I'd say it's very similar and falls well within run variance for AIDA64, but I have no background apps running in Normal Mode to begin with.

We shouldn't be using AIDA64 if the goal is to test realistic scenarios


----------



## Veii

Run to run variance should be under 0.3ns
Except the first run, which needs load before it settles down

Anything over this deviance is auto correcting or another issue.
Actually more like 0.2ns


----------



## Frosted racquet

Veii said:


> Run to run variance should be under 0.3ns


Yes, I miss wrote. It's run to run variance except for latency, which is lower because of safe mode. Having 65+ns latency (instead of ~56/57 ns in normal mode) with similar/better timings than mine simply means his windows installation is bloated with sh!t programs running in the background, which should NOT fall under the "normal everyday non-bench OS install" category.
Normal, non-bench OSes should not have Corsair iQue or other sh!t ruining latency


----------



## 99belle99

I read about lower latency in safe mode on here so I checked it last week and it was a tiny bit worse in safe mode which kinda shocked me.


----------



## Nucky

@Frosted racquet I just did a run in safe mode. I can't believe the difference. I have never ran aida in safe mode before and have always hit a wall in the mid-low 60s.


----------



## Frosted racquet

@Nucky Next suggestion would be to disable/uninstall any unnecessary background programs which affect your RAM performance. There should only be 1-2ns difference between normal mode and safe mode


----------



## 99belle99

Nucky said:


> @Frosted racquet I just did a run in safe mode. I can't believe the difference. I have never ran aida in safe mode before and have always hit a wall in the mid-low 60s.
> 
> View attachment 2578930
> View attachment 2578931


How have you such a variance? I just ran it now after seeing your post in case I done it wrong last time but no I get 63.3 in Windows 11 and 63.4 in safe mode.


----------



## Nucky

I'm not sure. I don't really have that much running. I can disable everything in the background and run a test in normal mode.


----------



## Veii

I have to say,
Sometimes i really struggle with you guys *🤭*

Real PB Operation:
~ idle 60 processes








Around 100MB/s delta on Read
1ish MB/s delta on peak Write, up to thermals
100-200MB/s delta on "Copy and Write"
Sub 0.2ns deviance

Safe Mode:
~ idle 45 processes, no GPU acceleration either








The results are all over the place
The write bandwidth is not hitting it's advertised targets
Boosting curve is not doing it's job
L$ access is all over the place
Latency is all over the place

Even with the difference of 10 processes less or for some users 50 processes less (don't go around the problem, maintain your OS please)
There was not even one scenario, where it showed nearly similar results.
Probably the worst, even if we accept the 0.6-1ns delta increase ~ is the constant change of results;
It pretty much defeats the sole purpose of what this buggy tool can be used for. That is to show autocorrection and in-loop timings repeat (background,on dimm)
================================================
@domdtxdissar can you try to replicate my Intel MLC results maybe with similar timings or personal ~ on current (1206+ AGESA)
Actually do you have any Zen3 system still ?


Spoiler: Results





























The results on those with L1 enabled, L2 disabled ~ since new AGESA are quite worse (sorry i mean the one with both L1,L2 enabled are worse)
The L3$ accesstime gets worse, but inter-core and anything that corresponds to Cache-Memory stream, is faster. Oh also those 3:1/2:1/1:1 ones vary by thermals, but no issue for. 

MCL is attached on post








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


I've updated my custom power plans for Win10 and created a new one for Win11. In my signature.




www.overclock.net




Potentially earlier post to check the delta for you, but you don't have to run this 
MLC and game perf is tho interesting. It performs too good for me. Could be a 1CCD thing , who knows


----------



## Veii

Nucky said:


> I can disable everything in the background and run a test in normal mode.


[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread Give this a try
Maybe, if you want.
Potentially have to edit it up to your need


----------



## sxeneize

Hi. I'm getting 1 error on Test 4, running 12 hours of TM5 1usmus_v3.
Already passed 12 hours of TM5 extreme1, absolut and HCI memtest.









Micron rev. E

Any suggestions?
Thanks.


----------



## Veii

sxeneize said:


> Micron rev. E
> 
> Any suggestions?
> Thanks.











12 hours , one PCB crash, or flipped bit
Are you sure we aren't talking about outer sources here finally ?
Like using the stove, making dinner, washing cloths, cleaning the room with the vacuum

Well error is this one 
Honestly ~ i don't know 
Drop AddrCmdDrvStr, you don't need that at 24 on B550 series
Ah also increase SOC at least once , it's too close to IOD. Can equally be "too much discharge by time" ~ it needs a bit more distance to IOD.
Well that on the general consent. #4 is an overcurrent DIMM-PCB crash. 
~ What about we try to lower cLDO_VDDP to 925mV. VDDG CCD to 975mV and drop VDIMM by 5-10mV ? (one step)


----------



## The_King

@Veii can you please do an update on all settings to change in the BIOS to minimize / stop WHEA 19s above 2000 FCLK.

I seen an older post where you talk about DPC settings etc. So far I only have 1966 FCLK completely WHEA free having some problems at 2000/2033 FCLK.

I read the rules for submitting AIDA64 apparently you only need a 20 minute stable run which I can do with most of my REV. E at very high FCLK. I only need to get rid of the WHEA 19s.

Thanks


----------



## Veii

The_King said:


> @Veii can you please do an update on all settings to change in the BIOS to minimize / stop WHEA 19s above 2000 FCLK.


There is no cheat sheet.
It's interconnects crashing, or rather stop reporting condition that causes whea.
It's a firmware issue and slightly mitigatable with some voltage settings.
It's the alarm clock that rings on even the slightest issue, even if it isn't a priority issue. Soo everything will trigger it. Even bad USB or Ethernet.
Well , bad IO from chipset to IO/Die will trigger it. A harsh or unstable GPU, will trigger that. The report is a side-issue of Firmware not functioning correctly
Main issue of report is Firmware Instability

A non issue sample, doesn't ever report WHEA 19.
There are algorithms inside to handle instability and slow GMI & LCLK link speed down.
Ones to work correctly with board chipset and that then manages correctly IO attached to it.
(X out of 10 sensors active for WHEA)

It is a hardware problem, but it's the low level firmware of this hardware that's the issue
Doesn't mean my average sample is golden ~ it's very average and slightly degraded by XOC now (running 1.76+ volts for a short time)
But my sample the way it shipped from BG SUS fab, was fixed. It was inspected and locked with newer updates of firmware. Something they should've done to B2 samples too.
They did not. The only fix and identical behavior to my sample, is now every (hopefully) Zen 4 chip.
Buuut this Zen 4 chip now again has board design issues and hardcaps memory. Fabric just slightly improved moving between 2133-2200
(peak is 2200 with same autocorrection, but it's still something)

Sorry, all i can say
~ Try pushing IOD voltage higher ~ sub 1.2v is your limit, likely cap 1.15 at worst
~ Try disabling LCLK dynamicness.
~ Force DPM LCLK in AMD CBS, NBIO, SMU Common options to my 2-1-1-2-2-1-1-2 preset, or even 1-1-1-1-1-1-1-1
~ Disable PCie 4.0 "handling" which amd implemented in AMD OVERCLOCKING section ~ which honestly is broken and copied badly, but what do i know 
~ Drop Chipset to 3.0 if possible, and increase it's voltage by 50mV . . . on both SKUs they dropped votlage to prevent the fan from running but actually caused issues on some boards.

Whea report is in firmware, soo get it as stable as possible and prevent LCLK dynamicness. Anything dynamic that has to do with the chipset/io-die(s) and the linkspeed itself. Put GMIs to lowest speed
There is my advice to look out for.
Disable serial ports, disable ethernet , see what on your board causes the issues.
Put it to the bare minimum configuration , like you would need for LN2.
Everything off unless you need it. No memory encryption, no virtualization, no spread spectrum , no thunderbolt....
At the end you might find for your board what triggers those void-issues, and then see why your sample is unstable "from IO-Die outwards"

X670(E) is now with similar children illnesses ~ but that's as always , my viewpoint 
I guess i got lucky, with a sample that reports clean "works or doesnt work". No first-adopter firmware bugs


----------



## domdtxdissar

Veii said:


> @domdtxdissar can you try to replicate my Intel MLC results maybe with similar timings or personal ~ on current (1206+ AGESA)
> Actually do you have any Zen3 system still ?
> 
> 
> Spoiler: Results
> 
> 
> 
> 
> View attachment 2578943
> View attachment 2578941
> 
> View attachment 2578942
> 
> 
> 
> The results on those with L1 enabled, L2 disabled ~ since new AGESA are quite worse (sorry i mean the one with both L1,L2 enabled are worse)
> The L3$ accesstime gets worse, but inter-core and anything that corresponds to Cache-Memory stream, is faster. Oh also those 3:1/2:1/1:1 ones vary by thermals, but no issue for.
> 
> MCL is attached on post
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> I've updated my custom power plans for Win10 and created a new one for Win11. In my signature.
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> Potentially earlier post to check the delta for you, but you don't have to run this
> MLC and game perf is tho interesting. It performs too good for me. Could be a 1CCD thing , who knows


My brother inherited that system, but i can check my screenshot folder when i get home, know i have some MLC numbers there, atleast with old layout..
RIP 5950x, you served my well 


http://imgur.com/a/PsfVNgy


----------



## sxeneize

Veii said:


> Drop AddrCmdDrvStr, you don't need that at 24 on B550 series
> Ah also increase SOC at least once , it's too close to IOD. Can equally be "too much discharge by time" ~ it needs a bit more distance to IOD.
> Well that on the general consent. #4 is an overcurrent DIMM-PCB crash.
> ~ What about we try to lower cLDO_VDDP to 925mV. VDDG CCD to 975mV and drop VDIMM by 5-10mV ? (one step)


Ok. I'll try that, thanks 
Btw i was just reading previous page, about GDM hiding powering issues. If i set GDM Off 2T i can barely get to the BIOS and there are like artifacts all over the place. What does this mean?


----------



## The_King

@Veii will this submission be fine for the AIDA64 sheet? Forgot to show no WHEA (Updated)


----------



## Veii

The_King said:


> @ veii will this submission be fine for the AIDA64 sheet?


Sorry i forgot to say
"those old submission rules are a joke" ~ he knows it and fixed it on Zen4 sheet

Bare bare minimum for any mem-stresstest over 1h,
Now requires 25 loops TM5 1usmus_v3 or 10 000% Karhu/HCI
Also running the L2 disable cheat, should be prevented. Like forbidden, till proofen it's faster in everything now. It's a daily scoreboard, not an XOC scoreboard some wish it to be
HWInfo needs to be open to show no WHEA's with it's timer at least to as long as the memory test has been running

That's kinda all
my screenshots take 6+ hours 
But at least try to hold to +1h memory test ~ as my personal wish and now new stricter rulesets.
Some of those submissions out there are kind of painting a wrong perspective


----------



## Veii

Veii said:


> Whea report is in firmware, soo get it as stable as possible and prevent LCLK dynamicness.


@The_King
On ZenPTMonitor








This value will update every boot.
On affected or unstable units it will skyrocket to 10 000+ samples.
Alone going to 49+ shows something is not fine.
Usually it sits bellow 36, up to uptime (on 2100 set)
I'm just down atm as i've been troubleshooting LCLK link NAVI instability


----------



## The_King

Veii said:


> Sorry i forgot to say
> "those old submission rules are a joke" ~ he knows it and fixed it on Zen4 sheet
> 
> Bare bare minimum for any mem-stresstest over 1h,
> Now requires 25 loops TM5 1usmus_v3 or 10 000% Karhu/HCI
> Also running the L2 disable cheat, should be prevented. Like forbidden, till proofen it's faster in everything now. It's a daily scoreboard, not an XOC scoreboard some wish it to be
> HWInfo needs to be open to show no WHEA's with it's timer at least to as long as the memory test has been running
> 
> That's kinda all
> my screenshots take 6+ hours
> But at least try to hold to +1h memory test ~ as my personal wish and now new stricter rulesets.
> Some of those submissions out there are kind of painting a wrong perspective


I don't see any L2 prefetch option on my B450 so not sure what that is.
I ran 25 cycles yesterday ran to some issues at the end. RAM overheating?


----------



## The_King

Veii said:


> @The_King
> On ZenPTMonitor
> 
> 
> 
> 
> 
> 
> 
> 
> This value will update every boot.
> On affected or unstable units it will skyrocket to 10 000+ samples.
> Alone going to 49+ shows something is not fine.
> Usually it sits bellow 36, up to uptime (on 2100 set)
> I'm just down atm as i've been troubleshooting LCLK link NAVI instability


Its Fixed on 38. No idea what this means. Should it be below 36?









After reboot its now at 33


----------



## ManniX-ITA

Nucky said:


> I'm not sure. I don't really have that much running. I can disable everything in the background and run a test in normal mode.


I feel like it's important to teach about using regularly Autoruns to clean up the system 

_*CLEAN UP YOUR SYSTEM WITH AUTORUNS*_

First thing to know is that Autoruns is a Microsoft tool, so safe to use.
But you need to be careful cause doing something wrong can cause issues to applications, which will not work, or the system, which will not boot anymore.
Don't improvise, if you have even the smallest doubt ask first.

*The concept is very easy, everything has a checkmark box in front.
Disable or enable it and reboot. That's all!*










Remove that (1) checkmark and reboot, done.

Now for the practical usage; launch it with Admin Privileges or go File -> Run As Administrator.

In the options you can enable "Check VirusTotal.com"; it's handy but don't get scared if something is reported positive by a few engines, often is just BS.
If it's like 30-40 hits, give it a check...










Now go to Options and enable Hide Microsoft Entries.

The important sections are:

Drivers
Services
Scheduled Tasks
Logon
Potentially there are other interesting tabs to check but you need knowledge and we'll keep it easy.

The entries can be marked red, which means no digital signature.
It's not a big alarm but if it's something that was supposed to be signed then something is wrong.
Almost all free software, like mine, doesn't have a signature.

Yellow mark means "File not Found"; usually safe to remove but better not to touch it.
If you unmark the something like the HWiNFO driver which is loaded from a temp folder, it could not work anymore.

_The nastier and most relevant is the Driver section._

More or less when you uninstall something they moderately care to remove Services, Logon and Scheduled Task entries.
Even if the uninstall doesn't remove them, they likely will stop working.

The drivers instead are very often forgotten, thanks also to Microsoft not making things easy at all.
If the driver is a kernel or device driver it often can't be removed but should be marked for deletion at next reboot.
Sometimes it doesn't work...

Most Tech companies, like board and HW vendors (including AMD), they just don't care about developing decent software and they mostly don't care uninstalling drivers (even when they know it's causing issues).

The drivers which are probably causing issues with performances (up to 5-10% loss in both CPU and GPU, 10ns RAM latency) are usually those:

AMDRyzenMasterDriverV*; seems latest versions are less dangerous and gets uninstalled, anyway better to remove RM unless you have gun pointed at your head
AsrDrv*; ASRock drivers, anything ASRock should be removed
Asusgio2; anything ASUS should be removed, the worst. If you have ROG peripherals you may need to keep the ROG drivers. Armoury-Crate software is a virus-like, will cause BSOD and all sort of issues, stay away.
EneIo, EneTechIo; this is the RGB software driver, one of the worst costing 5% performances alone. There are many flavors, all I have seen (ASUS, G.Skill, MSI, etc) are these drivers renamed. If a driver filename ends with "Io64.sys" be suspicious Don't use RGB software if you want full performances or use OpenRGB.
gdrv/gdrv2: GigaByte software, 2nd worse after ASUS, remove everything. Known to cause BSODs.
NTIOLib_MSISimple_OC, NTIOLib_OCKit; MSI Command Center, not the worst but hitting performances. Remove all MSI software, you can do the same without usually. Nice to change options without rebooting but then once done disable the driver.
NPF*; Network Packet Filter drivers; used by many network management utilities (eg PowerLine adapters, etc). Check if you need them, disable if not necessary. Re-enable when you need them.
There are drivers which you will find in numerous versions, like CPU-z and HWInfo; in general there's no need to disable them.
They are loaded when the application starts and doesn't create problems.
If you have a specific issue you can disable the old versions but consider that if was loaded by an application that it's not able to use the new driver, it will stop working.

Don't disable drivers that you don't know the origin or use.

The are some drivers which are safe to keep enabled like SSGDIO for Taiphoon, CPU-z, HWINFO, GPU-z, inpoutx64, WinRing (if installed by trustable apps, like mines or Hydra).

Disabling AMD or any other HW drivers used for boot can cause your system to stop booting. Be careful.

_The Services section is pretty easy._

You have a lot of information about each service and it's easier to spot something wrong.
The most suspicious ones are usually anti-cheat from games.
Very often if supported it's better to set the startup to Manual instead of Automatic to allow the related apps still working.

_The Scheduled Tasks section is a bit more tricky._

Don't disable anything unless you know the consequences.
In general is safe to disable tasks from software that you uninstalled.
You can always re-enable them.

The biggest problem is that maybe you disable something and it was all looking good.
But then after a while you start finding out issues but you forgot that you disabled that task in the past.

_The Logon section could be a bit intimidating._

Here too don't disable anything you don't know about.

Some stuff is repeated in more than one section, it's normal.
Disable mainly things you have uninstalled and which are marked yellow.
Faster boot times.

You can do it easy with task manager and startup items.

*HOW TO DO MAINTENANCE AND KEEP THE SYSTEM FAST*

Now whatever you have a good system and all is fine or you just fixed it disabling all the nasty stuff, that's what you need to do to keep it fast.

File -> Save, create an .arn file.

Now that you have your current configuration you can use File -> Compare.

Every now and then or when you see something seems off or slow, make a Compare with your latest saved Arn file.

If you see something new it can be the source of your issues. Ask around about it.


----------



## Blameless

Nucky said:


> I just did a run in safe mode. I can't believe the difference.


As others have pointed out, this is a clear sign that something is wrong.



Frosted racquet said:


> Yes, I miss wrote. It's run to run variance except for latency, which is lower because of safe mode.


I get the same latency figures in safe mode.

Main difference is that I occasionally get impossible write performance (30418, for example, on a single CCD part at 1900FCLK), probably because safemode has trouble polling timers or something.


----------



## Melan

ManniX-ITA said:


> The are some drivers which are safe to keep enabled like SSGDIO


The ssgdio driver is no longer allowed to run after recent Win 10/11 update if you have memory integrity enabled. It's flagged as a vulnerability.
Just an fyi.


----------



## The_King

@Veii Over 1 hour no sign of any WHEA's but guess who decided to show up in the last few cycles #3. Meh!
TRFC related?

I don't set the *DrvStr to 20s the board Autos to that and usually passes over 20 cycles with that. If adjust any of those 3 DrvStr I get errors within 3-5 cycles.
I shouted at it a few times but I won't behave. I don't know what else I can do, it does not listen to me.


----------



## mnathani98

The_King said:


> @Veii Over 1 hour no sign of any WHEA's but guess who decided to show up in the last few cycles #3. Meh!
> TRFC related?
> 
> Also I don't set *DrvStr 20s the board Autos to that and usually passes over 20 cycles with that. If adjust any of those 3 DrvStr I get errors within 3-5 cycles.
> I shouted at it a few times but I won't behave. I don't know what else I can do, it does not listen to me.
> View attachment 2579016


Try running OCCT Large Variable Extreme also i've been trying the same thing as you, 3933 flat 15s but i got 1 error at Test #2 on 18th cycle at 1.59v. Please excuse the low quality quality picture it wasn't taken by me.


----------



## The_King

@mnathani98 Are you running the same motherboard that I have ? I can't see that part is cut off.


----------



## mnathani98

The_King said:


> @mnathani98 Are you running the same motherboard that I have ? I can't see that part is cut off.


I have a Asrock B450 Steel Legend


----------



## Veii

The_King said:


> I ran 25 cycles yesterday ran to some issues at the end. RAM overheating?


Some are overvoltage issues
others are tRRD_/tWTR_ too low, issues


The_King said:


> Its Fixed on 38. No idea what this means. Should it be below 36?


it will change on load, or not change
they are tracked without the program running

It was a notice to watch out if it logs anything
it should not increase


The_King said:


> @Veii Over 1 hour no sign of any WHEA's but guess who decided to show up in the last few cycles #3. Meh!











Can be too low tRDWR too , but yours is fine
Likely one of the _L's


----------



## Frosted racquet

Blameless said:


> I get the same latency figures in safe mode.


I could've probably gotten the same latency if i reran the test a few times (AIDA being AIDA), but that just means we have OS clean from background junk, unlike Nucky, which is why I suggested Safe Mode as a quick way to figure out if some background junk is affecting the latency. I understand Veii's post stating about the weird results Safe Mode can yield, but it's still useful to compare to Normal mode.


----------



## Veii

Frosted racquet said:


> but it's still useful to compare to Normal mode.


That is , if what it reports actually would be accurate
Sadly it has a far to high delta and defeats any purpose of even using the software that way

Reports are meaningless in this state of operation;
From an accuracy standpoint
From an throttle finding standpoint (functionality) , when CPU operates with 1/4th of featureset or without at all
From an learning standpoint (usability)

It makes more sense to just run a small OS on another partition
if user can not get their system maintained.
That at least will have some sort of usable output values.
Or even if it was slower but not variable. Yet it is on 3 points useless (no accuracy, no functionality, no usability/value).
I see no reason to bother, except to check how bad something is, but even that paints a wrong perspective of secureness ~ shown by the bad results i gave.

Just install a 2nd OS on a little drive and you should be mostly fine, i guess ~ the laziest method i can get up with


----------



## ManniX-ITA

Melan said:


> The ssgdio driver is no longer allowed to run after recent Win 10/11 update if you have memory integrity enabled. It's flagged as a vulnerability.
> Just an fyi.


Thanks for the info.
Honestly this whole memory integrity feature it's just impossible to use unless you are in a controlled enterprise environment 

Almost all the Logitech drivers are blocked, Broadcom Bluetooth, USB drivers, etc etc
I don't even remember them all but I can't enable it on my Windows install cause there are two pages of drivers which are black-listed.
It's an unusable security feature for consumers. The black-list is non-sense and dumb and some drivers which are potentially dangerous for real are not considered as such.


----------



## ManniX-ITA

Veii said:


> It makes more sense to just run an small OS on another partition


Indeed cheapest and quickest solution.

My recommendation is always a WinToGo installation on a USB device.
Possibly a USB SSD.
Fast Pendrives works but not the best.

Advantages are that the WinToGo install it's meant to run on a removable device.
Meaning that sudden reboots, crashes, failed boots with memory corruption or CPU messed up will hardly make a difference.
I have only once messed up a WinToGo installation over the years.
A normal installation could require restore in less than 24h of testing...

Plus all internal drives are set Offline with WinToGo.
It will not mess with your system or data.
If you need to access them you can always set them online and then offline again with disk management.

This allows you also to do some BCLK testing with very few chances to hurt your drives (but it's not completely safe).

Old and small M.2 drives works really well, best enclosure is the Sabrent EC-SNVE.

Even better is a Samsung USB drive, they are often on sale.
I have a T7 drive that can do 1 GB/s and it's as fast as an internal M.2 drive for booting.


----------



## Frosted racquet

@Veii @ManniX-ITA
I'm curious about using TestMem5 in Safe Mode to test stability. I've had trouble before where TM5 would hang in normal mode even with stock settings/CPU frequency locked manually to 3.7GHz








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Hello guys, I would appreciate your help, it's my first time at OC, just built the following machine: AMD Ryzen 7 5700G Asrock B450m Steel Legend Corsair Vengeance LPX 16GB 3600mhz (1x16, i'm using it in single channel) Enabled the XMP on Bios, but I don't think it's stable cause it's...




www.overclock.net












[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Hello guys, I would appreciate your help, it's my first time at OC, just built the following machine: AMD Ryzen 7 5700G Asrock B450m Steel Legend Corsair Vengeance LPX 16GB 3600mhz (1x16, i'm using it in single channel) Enabled the XMP on Bios, but I don't think it's stable cause it's...




www.overclock.net












[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


I think the OS disables some kind of boost in safe mode, or the frequency readout is not working correctly. It's not setting your CPU to stock operation at least. I am still getting higher benchmarks scores with PBO2 in safe mode than with stock settings in safge mode. However, base frequency...




www.overclock.net





Would running TM5 from Sergei Strelec USB for ex. be OK?


----------



## ManniX-ITA

Frosted racquet said:


> I'm curious about using TestMem5 in Safe Mode to test stability.


Not in safe mode, I wouldn't do it unless it's absolutely necessary.
From what I've seen TM5 it's a tad slower and hence not the same kind of stress.



Frosted racquet said:


> Would running TM5 from Sergei Strelec USB for ex. be OK?


Yes but a cleaner image would be better.

TM5 works by allocating all the free memory.
If you run it without anything open and then with something heavy on memory open you'll see a lower memory allocated for testing.

It's recommended to avoid running anything in parallel, even HWInfo would be better not.
I had a couple of times testing going dead at the end of the cycle because of HWInfo.
Run it only if you want to validate for the Zen Leaderboard or check the memory temperature.

TM5 it's very efficient but not resilient.
Whatever you do which is using, even low usage, the CPU can kill the cycle.

But most dangerous is memory allocation.
If you open an application during testing it's probably going to kill TM5.
TM5 allocates the memory at the beginning and you must keep it free.
If something else is requesting memory allocation to Windows, it will make TM5 fail or die.

So never let any application ask memory to Windows.
That's why HWInfo is one of the few apps that you can often run with TM5; small and efficient memory footprint, no leaks over time.

One trick to test with TM5 while using the PC (only browsing and it's still risky) is to first open some quite heavy applications.
Then start TM5 and then close all the applications.
Testing will be done on less memory, not the best, but then you can open something small and likely TM5 will survive.


----------



## Nucky

@Veii @Frosted racquet @Blameless I'm looking into cleaning up my windows 11 install today. I can drop 5ns just from closing the programs I always have in the background (discord,hwinfo,etc). I have always been wary of the debloat tools due to some of their tradeoffs but now I see how necessary they can be for what I was attempting to do.


----------



## ManniX-ITA

Nucky said:


> @Veii @Frosted racquet @Blameless I'm looking into cleaning up my windows 11 install today. I can drop 5ns just from closing the programs I always have in the background (discord,hwinfo,etc). I have always been wary of the debloat tools due to some of their tradeoffs but now I see how necessary they can be for what I was attempting to do.


I'm using this one and it looks pretty decent:









GitHub - builtbybel/ThisIsWin11: The real PowerToys for Windows 11


The real PowerToys for Windows 11. Contribute to builtbybel/ThisIsWin11 development by creating an account on GitHub.




github.com





Nothing hard-core.


----------



## Tirade75

Veii said:


> #10's are tRRD_S, tRRD_L, tWTR_L and RTT_NOM errors
> #13 are overtemp crash issues ~ connected to "too high voltage"
> 
> #10 increase slowly tRRD_L to 5 then to 6 tiill it fades away
> drop VDIMM about 20mV and #13's should go away ~ if not, you have to redesign your powering (CAD_BUS , RTT)
> If VTT_MEM exists, lowering it by 50mV works too to tame higher voltage. Or increasing VPP_MEM from 2.5 to 2.55-2.6
> 
> 
> 
> 
> 
> 
> 
> 
> EDIT:
> Unless your set was fine, GDM off will introduce very likely new errors
> It only means GDM hides them & you always had problematic powering.
> GDM off exposes it, else there has to be zero VDIMM adding difference between 2T & GDM ~ if set was correct to begin with


@Veii Well damn, I dropped VDIMM 20mV and woke up this morning to this:

========= TestMem5 Log File =========
Customize: Default @1usmus_v3
Start testing at 17:22, 1.7Gb x16
Testing completed in 2:45.09, no errors.

That was a 25 run test. Here are the max temps

















Going to start the next round of stressing but that might have been the trick!!


----------



## StrongForce

Guys I need help..

Ran linpack extreme all night, no issue, aswell as another run of memtest5, no issues, I still have no problem with gaming (played overwatch and apex yesterday for hours) and have very good performance, YET.. I get even more freezes on windows than with my less stable setting when I was running 3733 c15 and higher voltages, which leads me to believe the problem indeed lies somewhere in my voltages/OC, my SOC is not even high .. 1.1v

I don't know what to do anymore, I'll be using another windows install see if this happens aswell, honestly starting to regret going AMD, maybe just bad luck with my motherboard or something, I don't know, feels strange, something is up.

Like earlier I was using edge for 1h+ no issue, I try to open discord, boom freeze. (it starts with the explorer freezing at the bottom, can still do stuff, at this point I just hard reset though interesting to notice that my mouse still work and like if I'm on edge I can still move arround tabs, though I think it will eventually freeze aswell).

Or like if I have edge open, then I try to open firefox, boom freeze instantly, soo weird.. I mean even though it sounds like it's just my windows being broken somehow, the fact that it happens alot more now than my previous settings really bugs me, now I'm almost convinced it's this OC thingy, also, it all started happening as I started messing with RAM OC..

Perhaps I need to make a dedicated thread but I thought maybe some of you RAM OC enthusiasts might have some ideas as to what's going on


----------



## ManniX-ITA

StrongForce said:


> Or like if I have edge open, then I try to open firefox, boom freeze instantly, soo weird.. I mean even though it sounds like it's just my windows being broken somehow, the fact that it happens alot more now than my previous settings really bugs me, now I'm almost convinced it's this OC thingy, also, it all started happening as I started messing with RAM OC..


Why don't you just run it for a while with the XMP profile at 3600 MHz and check if it's working.

I guess they are B-die, correct?


----------



## Iarwa1N

Hi guys, I just found a stable base, tested with 1usmus_v3 for an hour, can you point me to a direction where I can start more tweaking;


----------



## StrongForce

ManniX-ITA said:


> Why don't you just run it for a while with the XMP profile at 3600 MHz and check if it's working.
> 
> I guess they are B-die, correct?


Wait..you can run XMP at lower speeds than the max speed ?? I didn't know that.. I'll try thanks, I thought the XMP was only for the 4266mhz, yes it's B-die.


----------



## ManniX-ITA

StrongForce said:


> Wait..you can run XMP at lower speeds than the max speed ??


Sure you can, no problem just set a specific frequency other than Auto.

The profile itself it's not really good but should work via GDM.
What is the VDIMM?


----------



## The_King

@Veii I was running RTT 0/0/5 @ 1.55V😅









Running RttNom 7 now so should I run RttWr 3 or is 7/0/6 Ok for daily @ 1.55V?


----------



## MrHoof

Veii said:


> Please try:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Sorry, please try
> View attachment 2578004
> 
> 
> Both as comparison with Benchmate y-cruncher 2.5b & aida64
> (trow away the first result, without ethernet cable)


Did find time to run full 25 cycles seems fine still at 1.55v max temp 49.8°C.









Not optimized anything about my windows install besides not having any programms in autostart.









Edit: Maybe u can explain it to me but I always running fine with tCKE 1 but u keep suggesting 8 for DR. Does it make sense to run 8 if 1 is stable?
Is it not Clock enable and just applying on first command and delaying it by 8?


----------



## StrongForce

ManniX-ITA said:


> Sure you can, no problem just set a specific frequency other than Auto.
> 
> The profile itself it's not really good but should work via GDM.
> What is the VDIMM?


1.45v could it be too high now that I'm at 3600? I can try that, but it's weird how it would not show up in instability with softwares though, again, just ran apex fine for 1 hour, I alt tab, open edge, freeze.. 

I'm curious to try lower speeds XMP though will definitely do that


----------



## ManniX-ITA

StrongForce said:


> 1.45v could it be too high now that I'm at 3600? I can try that, but it's weird how it would not show up in instability with softwares though, again, just ran apex fine for 1 hour, I alt tab, open edge, freeze..


No, should be about right.
Indeed doesn't really look like a memory settings issue.

The only possible issue with the timings and the voltage is the tRFC.
It's too low from what I remember for that voltage.
It can cause really weird issues when it's borderline unstable and sometimes pass undetected by memory testing.
I would try with 312/232/143.


----------



## Blameless

ManniX-ITA said:


> I don't think was really about AM4 compatibility.
> That massive thick IHS is there mostly to provide a thermal capacity buffer, it allows usage without hard throttling (HS not detected, locked at 800 MHz till poweroff) also with cheap air coolers.
> Gives more time to throttling when you have decent cooling but basically equalize anything good to that artificial bottleneck.
> Not a problem with LN2 or something good sub ambient but it's a tragedy for any decent to good custom WC.


On a related note: 




Anyway, I'd think the cooler base or cold plate itself would be enough thermal mass to prevent issues. People are running delidded without problems on normal water (and probably air).


----------



## ManniX-ITA

Blameless said:


> Anyway, I'd think the cooler base or cold plate itself would be enough thermal mass to prevent issues. People are running delidded without problems on normal water (and probably air).


I have the feeling (can't say anything for sure cause I don't have direct experience) that the thick HS is a massive over-reaction.
Looks like wearing a space suite for a stroll around the block cause there's pollution in the air...

The whole de-lidding topic makes me more interested in AM5.
But I will still wait (hopefully, trying to resist) till it's confirmed they can fix AVX over 5.5 GHz.


----------



## gvansly1

Hey everyone,
Avid follower of this thread. I have questions regarding tPHYRDL, and excuse me if they have already been answered here.
1: What exactly is it?
2: Why does it change between dimms after changing BIOS settings?
3: Does it matter? Either stability or performance wise?

And one question regarding WHEA19 error. If I'm only getting one after a restart and none in between use and restart this seems to be ok with me, thoughts

Thanks in advance


----------



## gvansly1

Apologizes, Going from 3600 to 3800 tPHYRDL changes from 26/26 to 26/28
DDR4 passed 20 cycles of 1usmus


----------



## StrongForce

StrongForce said:


> 1.45v could it be too high now that I'm at 3600? I can try that, but it's weird how it would not show up in instability with softwares though, again, just ran apex fine for 1 hour, I alt tab, open edge, freeze..
> 
> I'm curious to try lower speeds XMP though will definitely do that


Mmh, thank you! I'll keep that in mind, so, as an interesting turn of event, I been using another windows install on a brand new SSD that got RMA'ed not long ago, no problem at all whatsoever, so I guess it would be just pure coincidence that windows decided to crap itself even more after changing settings, I was really starting to get confused by this whole thing, but as you say, it seems like it can indeed happen, I'll be using this windows more to see if I ever get a freeze.

I'm starting to suspect my m.2 ssd to be the culprit, I would doubt the FCLK or memory OC affects this in any way.. could it ?

Or perhaps just my windows is corrupted out of bad luck.. either way, if this install indeed doesn't cause any issues then I can remove the memory OC out of the equation for sure.

Appreciate the feedback though, you guys rock, I miss that forum !  once I'm sure this thing is sorted I will try a little PBO OC for my 5600x, nothing too crazy, already tried all core OC and holy the heat output ahha, pretty intense even for a noctua D14


----------



## heptilion

Veii said:


> @The_King
> On ZenPTMonitor
> 
> 
> 
> 
> 
> 
> 
> 
> This value will update every boot.
> On affected or unstable units it will skyrocket to 10 000+ samples.
> Alone going to 49+ shows something is not fine.
> Usually it sits bellow 36, up to uptime (on 2100 set)
> I'm just down atm as i've been troubleshooting LCLK link NAVI instability


showing 48 on mine. hmmm


----------



## Blameless

Veii said:


> @The_King
> On ZenPTMonitor
> 
> 
> 
> 
> 
> 
> 
> 
> This value will update every boot.
> On affected or unstable units it will skyrocket to 10 000+ samples.
> Alone going to 49+ shows something is not fine.
> Usually it sits bellow 36, up to uptime (on 2100 set)
> I'm just down atm as i've been troubleshooting LCLK link NAVI instability


What does the MP5_BUSY value actually represent?

I see between 35 and 42 on a fresh boot, reaching up to 49-50 after ~12 hours of stress testing.



StrongForce said:


> Like earlier I was using edge for 1h+ no issue, I try to open discord, boom freeze. (it starts with the explorer freezing at the bottom, can still do stuff, at this point I just hard reset though interesting to notice that my mouse still work and like if I'm on edge I can still move arround tabs, though I think it will eventually freeze aswell).


Anything suspicious in event viewer? Any WHEA errors? Any GPU OC (unstable GPU can corrupt system memory contents, especially if ReBAR is enabled)?



StrongForce said:


> I'm starting to suspect my m.2 ssd to be the culprit, I would doubt the FCLK or memory OC affects this in any way.. could it ?


FCLK can affect anything that passes through fabric and memory instability anything that passes through memory...this is pretty much everything.

Of course, an unstable SSD can also cause issues of it's own.


----------



## The_King

The_King said:


> @Veii I was running RTT 0/0/5 @ 1.55V😅
> View attachment 2579084
> 
> 
> Running RttNom 7 now so should I run RttWr 3 or is 7/0/6 Ok for daily @ 1.55V?


Another day another error. Fun!  
Tried WTRS/L 4/10 it was not happy went back to 3/8 and higher on the TRFC to help with temps. Managed to drop
to 1.54V. I think it maybe upset with me because I shouted at it yesterday.


----------



## ManniX-ITA

The_King said:


> Tried WTRS/L 4/10 it was not happy went back to 3/8 and higher on the TRFC to help with temps. Managed to drop
> to 1.54V. I think it maybe upset with me because I shouted at it yesterday


I guess saying kind and lovely words would be even worse, you could end up on a forced sanitary treatment 

I'm not really a fan of the tRAS/tRC shortening.
Not a matter of principle but on my DIMMs never had any positive effect.
But from my understanding works with the logic of tRAS = tRCDWR+tRP instead of tRCDRD+tRP.
Shouldn't you be using tRCDWR at 8?

Also is the combo tRTP/tWR at 8/10 a good one here?
tWR at 10 is very short.
I had more often loss of perf going down there than up.
Sporadic error 12 could also be something wrong there as far as I remember.


----------



## The_King

ManniX-ITA said:


> I guess saying kind and lovely words would be even worse, you could end up on a forced sanitary treatment


I apologized for calling it a dumb outdated B450 Chipset. I think it it was happy after that. 😅



ManniX-ITA said:


> I'm not really a fan of the tRAS/tRC shortening.
> Not a matter of principle but on my DIMMs never had any positive effect.
> But from my understanding works with the logic of tRAS = tRCDWR+tRP instead of tRCDRD+tRP.
> Shouldn't you be using tRCDWR at 8?


If voltage is high enough sometime it will boot with RDWR 8 but causes random failed post issues.

I will do another run without TRAS/RC shortening. Upped the VDIMM back to 1.55V will run another test tonight.
My Super Pi time did not seem to increase much with higher 3933MT vs 3800Mt. Will test y-cruncher today.

Not sure if I am losing performance somewhere.


----------



## ManniX-ITA

The_King said:


> My Super Pi time did not seem to increase much with higher 3933MT vs 3800Mt. Will test y-cruncher today.


Yes you need to compare with y-cruncher.
The only other working verification tool is running the XMRSTAK-RK monero miner.
Not in benchmark mode, real mining; you can quickly setup an account just for benching mining 
If you get same/lower time in y-c and higher throughput in XMR then the FCLK is fine.


----------



## The_King

ManniX-ITA said:


> Yes you need to compare with y-cruncher.
> The only other working verification tool is running the XMRSTAK-RK monero miner.
> Not in benchmark mode, real mining; you can quickly setup an account just for benching mining
> If you get same/lower time in y-c and higher throughput in XMR then the FCLK is fine.


With No CO applied about 1 second faster than 3800MT CL15 also no CO.
















With not optimal -CO applied.


----------



## Mikel_Ertz

Tested again this settings to ensure stability. Gyazo 50 cycles of 1usmusv3 and no error. But tested 20 cycles of anta absolut and got 1 

Gyazo Any idea how to fix it? I am running micron rev e


----------



## mus1mus

Waiting Game....
WIP as always...


----------



## Blameless

Decided to increase tRC from 38 back to 39 on my Team B-die kit. Just that change adds at least 5C to the maximum temp the memory is stable at.

Using the LCLK bug to allow the CPU to work at temps high enough (with all fans in this not so well ventilated SFF box at ~500rpm) to really push the limits on the memory:









Memory doesn't have a temp sensor, but quick peek with the IR thermometer says the heatspreaders are hitting ~70C (probably 75C+ on die).

I did get a single error in pass 10 after I took this screen shot...almost certainly temp related, but I'm still playing with things.

Also, the IOD on these newer 5800X3D batches seem really good. 1900 FCLK with barely over one volt while getting the IOD itself to over 70C and pushing almost 18A though it.

_Edit:_ Same thing, but with my normal fan speeds and some GPU load:









About 20C of headroom before I start to hit errors.


----------



## Nd4spdvn

Blameless said:


> Using the LCLK bug to allow the CPU to work at temps high


What is this LCLK bug and how does one exploits it in the manner you did? Is this playing with the DPM LCLK, if so what values? Thanks!


----------



## Blameless

Nd4spdvn said:


> What is this LCLK bug and how does one exploits it in the manner you did? Is this playing with the DPM LCLK, if so what values? Thanks!


If you disable LCLK DPM it knocks out the PPT limit entirely and increases temperature the CPU can reach before starting to throttle by 5-10C.

Clearly this can result in very high temps, and I wouldn't recommend using it without significant negative COs active. I'm using -30 all-core CO which results in well under 1.2v peak and generally under 1.1v by the time the CPU exceeds normal throttle limits.


----------



## Nd4spdvn

Thanks, I wanted to try that but the thing is that my Giga B550 Aorus Pro V2 only offers me on NBIO LCLK DPM just Auto and Manual options, I cannot disable it explicitly. In manual I have for socket0 4 DPM states to setup and again 4 for socket1 with the settings Auto, 1 and 2. So I can do 2-1-1-2 2-1-1-2 or 1-1-1-1 1-1-1-1 like Veii suggests in some of his posts, but not sure what I can accomplish with these.


----------



## Blameless

Nd4spdvn said:


> Thanks, I wanted to try that but the thing is that my Giga B550 Aorus Pro V2 only offers me on NBIO LCLK DPM just Auto and Manual options, I cannot disable it explicitly. In manual I have for socket0 4 DPM states to setup and again 4 for socket1 with the settings Auto, 1 and 2. So I can do 2-1-1-2 2-1-1-2 or 1-1-1-1 1-1-1-1 like Veii suggests in some of his posts, but not sure what I can accomplish with these.


That's in an entirely different section.

My MSI and ASRock boards show it under AMD Overclocking. I do have a Gigabyte board as well, but the firmware isn't new enough to have the option, so I'm not sure where they put it, but knowing Gigabyte, it's probably in at least three different places.


----------



## sxeneize

Veii said:


> Drop AddrCmdDrvStr, you don't need that at 24 on B550 series
> Ah also increase SOC at least once , it's too close to IOD. Can equally be "too much discharge by time" ~ it needs a bit more distance to IOD.
> Well that on the general consent. #4 is an overcurrent DIMM-PCB crash.
> ~ What about we try to lower cLDO_VDDP to 925mV. VDDG CCD to 975mV and drop VDIMM by 5-10mV ? (one step)


Ok, it's fixed now. I don't know if it makes much sense but I had to raise VDIMM to 1.51v. When i dropped VDIMM to 1.49v i got more errors.
I ended up running only test 4, so i could find errors quickly. 
2 hours of test 4 at 1.49v got 5 errors. 
8 hours of test 4 at 1.51v got 0 errors.

Now i wanted to try GDM off 2T, but doesn't even POST.


----------



## byDenoso




----------



## mnathani98

Need a bit of help here


----------



## The_King

mnathani98 said:


> Need a bit of help here
> View attachment 2579392


Your timings are very loose/slow that same test with same ram takes me +/-1:25mins 3933 CL15 for 25 cycles. 
I would try to tighten up timings looks like you are mainly running XMP subs timings.


----------



## Veii

mnathani98 said:


> Need a bit of help here
> View attachment 2579392


tCKE 11 
tWR 24, tRTP 12

VDIMM down or RTT_NOM up 
#0 = lack of vdimm or bad powering
7-3-6 you can try


----------



## Farih

I changed my board and CPU but have kept the RAM i had.

With my old board and CPU i got my RAM clocked 24/7 like this:

1.54Vdim









Trying to get my RAM to work like this again seems very hard, almost feels like i am doing something wrong...

This is what i got so far:

1.47Vdim










With slightly looser timings i can make it work at 1866/3733mhz but has same latency and needs a higher voltage then slightly tighter at 1833/3666mhz.

Nothing i do can make it run at 1900/3800mhz 
Even when i bring tRCDWR to 14 (let alone 8) my PC wont boot anymore, no matter the voltage.

Is my new board and CPU combo really so much worse then my previous or am i doing something wrong?


----------



## HEYY0M1KEY

Does TM5 report threads starting at 0 and ending at 15? I was testing my 3800 2T profile with my PBO curve and was getting a crash around 1 hour on "Core 15". 

Previous curve I have tested quite a bit with Corecycler and Y-Cruncher with my GDM on profile. Lowered the curve and now it didn't crash, this time at least.


----------



## The_King

Farih said:


> I changed my board and CPU but have kept the RAM i had.
> 
> With my old board and CPU i got my RAM clocked 24/7 like this:
> 
> 1.54Vdim
> View attachment 2579542
> 
> 
> Trying to get my RAM to work like this again seems very hard, almost feels like i am doing something wrong...
> 
> This is what i got so far:
> 
> 1.47Vdim
> View attachment 2579543
> 
> 
> 
> With slightly looser timings i can make it work at 1866/3733mhz but has same latency and needs a higher voltage then slightly tighter at 1833/3666mhz.
> 
> Nothing i do can make it run at 1900/3800mhz
> Even when i bring tRCDWR to 14 (let alone 8) my PC wont boot anymore, no matter the voltage.
> 
> Is my new board and CPU combo really so much worse then my previous or am i doing something wrong?


Most likely ProcODT is the problem set that manually to 40 or 43.6 when running 1900 FCLK. I found it works well with 4 X Samsung DIMMS well on my board it does.

Some people do have issues getting 1900 FCLK with the 5800X3D others go over it without any problems.
There is also a 5800X3D thread on here you may get some info on there as well.


----------



## Imprezzion

Blameless said:


> Decided to increase tRC from 38 back to 39 on my Team B-die kit. Just that change adds at least 5C to the maximum temp the memory is stable at.
> 
> Using the LCLK bug to allow the CPU to work at temps high enough (with all fans in this not so well ventilated SFF box at ~500rpm) to really push the limits on the memory:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Memory doesn't have a temp sensor, but quick peek with the IR thermometer says the heatspreaders are hitting ~70C (probably 75C+ on die).
> 
> I did get a single error in pass 10 after I took this screen shot...almost certainly temp related, but I'm still playing with things.
> 
> Also, the IOD on these newer 5800X3D batches seem really good. 1900 FCLK with barely over one volt while getting the IOD itself to over 70C and pushing almost 18A though it.
> 
> _Edit:_ Same thing, but with my normal fan speeds and some GPU load:
> 
> 
> 
> 
> 
> 
> 
> 
> 
> About 20C of headroom before I start to hit errors.


I have mostly copied your settings just to test some stuff. I am having a real hard time keeping the DIMM's cool enough to actually run the normal profile I have so I wanted to make a high temp resistance profile. Only thing I'm running into right now is the fact I cannot for the life of me run 1T with GDM Off. I am using a cheap board, ASUS B550-A, with 4 DIMM slots.. but still..

I usually run 3866 14-15-15-28-252-2T at 1.58v but yeah that errors above 47c which they quite easily get in the new case.

EDIT: well that's new to me.. it got SO unstable with me testing something it corrupted the BIOS and asks me to enter a recovery USB.. lucky me I came prepared and have said USB with the .cap file on it..


----------



## Farih

The_King said:


> Most likely ProcODT is the problem set that manually to 40 or 43.6 when running 1900 FCLK. I found it works well with 4 X Samsung DIMMS well on my board it does.
> 
> Some people do have issues getting 1900 FCLK with the 5800X3D others go over it without any problems.
> There is also a 5800X3D thread on here you may get some info on there as well.


Tryed ProcODT at 40, ill try 43.6 to.
Thing is my old settings don't even work at 3600mhz anymore, not even with excessive voltages 
I know the RAM can do it (has done 3800mhz CL14 24/7 for months before) and seen people talk about the 5800X3D having a good IMC in general.... Does the board have much impact?
My previous board was a x570 TUF, board i have now is a B550-F Strix.

Did skimp through the 5800X3D owner's thread but didn't find much RAM related, was more about curve, undervolting and that it seems to have a strong IMC in general.


----------



## Imprezzion

Let's see how temperature resistent this new test profile is. 1.51v vDIMM, the vSOC/VDDG/VDDP is quite high but it needs it to not give WHEA's at 2000 FCLK/MCLK. It's not out of the realm of reason tho. I would not be surprised if the DIMM's hit 60c with this much voltage and zero airflow. But as long as it's stable.. Good thing is, it also has tPHYRDL 26/26 so matching and on 26 not 28. I like it.

I haven't touched any of the RTT's or DrvStr's yet. Just wanna see what it does on Auto first.


----------



## The_King

Farih said:


> Tryed ProcODT at 40, ill try 43.6 to.
> Thing is my old settings don't even work at 3600mhz anymore, not even with excessive voltages
> I know the RAM can do it (has done 3800mhz CL14 24/7 for months before) and seen people talk about the 5800X3D having a good IMC in general.... Does the board have much impact?
> My previous board was a x570 TUF, board i have now is a B550-F Strix.
> 
> Did skimp through the 5800X3D owner's thread but didn't find much RAM related, was more about curve, undervolting and that it seems to have a strong IMC in general.


Have you tried FCLK 1933/1966 ? 3866/3933 ?


----------



## Imprezzion

Didn't quite get to 60C on the DIMM's but it seems to hold up just fine so far. Also no WHEA's at all at 2000 1:1 so far. -30 CO all core as well. 
I'll let it run over dinner for like another hour or so and call it there. It has already reached temp equilibrium so. Might tweak some more timings here and there like tRDWR which is still just on Auto or drop the voltages a bit and re-test but I think this'll have to be it for the daily profile. At least until my dedicated RAM cooler shows up.


----------



## 99belle99

I have a weird one. I sold my 6900 XT about two weeks ago and went back to my r9 230 to tie me over till new Amd cards come out. Well the next day after changing over the screen went blank but I could still move my mouse around the screen so I shut it down. Worked great for over a week until I changed to a Nvidia GT 710(DX12 card) so I could run CPU only test in Timespy. Well I was on a USB version of linux watching a video and the same happened I put it down to bad drivers in Linux working with Nvidia. So I switched back to my AMD R9 230. And today I left the room to do a few things and came back and it done the same blank screen but I can still move the mouse around and had to force shut down the PC by the power button.

Anyone any ideas what is going on? I also have all Windows power save features turned off so when I leave computer for a while it stays on and also screen stays on forever also.

I'm not sure why I'm posting here as I do not know if it is memory related. And as I said it worked fine for a while till I changed to a Nvidia card. Also I left my PC a few times today while it was still running so it wasn't some bug that comes when PC isn't used.


----------



## The_King

99belle99 said:


> I have a weird one. I sold my 6900 XT about two weeks ago and went back to my r9 230 to tie me over till new Amd cards come out. Well the next day after changing over the screen went blank but I could still move my mouse around the screen so I shut it down. Worked great for over a week until I changed to a Nvidia GT 710(DX12 card) so I could run CPU only test in Timespy. Well I was on a USB version of linux watching a video and the same happened I put it down to bad drivers in Linux working with Nvidia. So I switched back to my AMD R9 230. And today I left the room to do a few things and came back and it done the same blank screen but I can still move the mouse around and had to force shut down the PC by the power button.
> 
> Anyone any ideas what is going on? I also have all Windows power save features turned off so when I leave computer for a while it stays on and also screen stays on forever also.
> 
> I'm not sure why I'm posting here as I do not know if it is memory related. And as I said it worked fine for a while till I changed to a Nvidia card. Also I left my PC a few times today while it was still running so it wasn't some bug that comes when PC isn't used.


What screen/monitor do you have Freesync / Gsync? Does it have any power saving modes? Try resetting it to default using the Menu option on your screen if you have that feature.

It's best to use DDU to remove all GPU drivers before installing a new card. Also did you leave the AMD drivers on the system when you installed the Nvidia GPU?








Display Driver Uninstaller Download version 18.0.5.9


Here you can Download Display Driver Uninstaller, this Display Driver Uninstaller is a driver removal utility that can help you completely uninstall AMD/NVIDIA graphics card drivers and packages from your system, with...




www.guru3d.com


----------



## 99belle99

The_King said:


> What screen/monitor do you have Freesync / Gsync? Does it have any power saving modes? Try resetting it to default using the Menu option on your screen if you have that feature.
> 
> It's best to use DDU to remove all GPU drivers before installing a new card. Also did you leave the AMD drivers on the system when you installed the Nvidia GPU?
> 
> 
> 
> 
> 
> 
> 
> 
> Display Driver Uninstaller Download version 18.0.5.9
> 
> 
> Here you can Download Display Driver Uninstaller, this Display Driver Uninstaller is a driver removal utility that can help you completely uninstall AMD/NVIDIA graphics card drivers and packages from your system, with...
> 
> 
> 
> 
> www.guru3d.com


No power saving features on monitor or Freesync or Gsync. Yes I always use DDU in safe mode when clearing a old driver.


----------



## RackarN

Imprezzion said:


> Didn't quite get to 60C on the DIMM's but it seems to hold up just fine so far. Also no WHEA's at all at 2000 1:1 so far. -30 CO all core as well.
> I'll let it run over dinner for like another hour or so and call it there. It has already reached temp equilibrium so. Might tweak some more timings here and there like tRDWR which is still just on Auto or drop the voltages a bit and re-test but I think this'll have to be it for the daily profile. At least until my dedicated RAM cooler shows up.
> 
> View attachment 2579560


Congrats! Damn good cpu. Mine gives up at 1933IF


----------



## Fliperx

Greetings to all. I was doing a couple of tests to my configuration and I would like to get your opinion.
On the one hand, we have LinkpackXtreme which I am not sure if I configured all its parameters correctly. On the other hand, we have Maxxmem, which shows me 39.5GB and I don't know if this is correct (I hope so). 
What do you think about these results, something to improve?


----------



## Imprezzion

Ok so 4000C16 1:1 runs kinda fine but it still is unhappy somewhere. It seems to run fine for an hour and then randomly just reboots when under load or has a WHEA 19 interconnect error followed by a freeze.. With a bit of tweaking I can probably get it to do it stable, maybe with a little less - CO or a bit more vSOC / CPU 1.8 it might do it but honestly, it isn't worth it on the 5800X3D. Memory does almost nothing for performance and I'd rather have a nice low power low voltage simple OC.

I'm back at 3800C15 now which it seems to run much easier without WHEA or freezes so far and it also handles the heat fine on the RAM. It might do with a bit less vSOC still or a tweak here and there to ProcODT/RTT/DrvStr but this seems pretty solid to me.


----------



## MrHoof

Imprezzion said:


> Ok so 4000C16 1:1 runs kinda fine but it still is unhappy somewhere. It seems to run fine for an hour and then randomly just reboots when under load or has a WHEA 19 interconnect error followed by a freeze.. With a bit of tweaking I can probably get it to do it stable, maybe with a little less - CO or a bit more vSOC / CPU 1.8 it might do it but honestly, it isn't worth it on the 5800X3D. Memory does almost nothing for performance and I'd rather have a nice low power low voltage simple OC.
> 
> I'm back at 3800C15 now which it seems to run much easier without WHEA or freezes so far and it also handles the heat fine on the RAM. It might do with a bit less vSOC still or a tweak here and there to ProcODT/RTT/DrvStr but this seems pretty solid to me.
> 
> View attachment 2579604


For 1900mhz fclk around 1v is often enough on the 3d´s.


----------



## Imprezzion

MrHoof said:


> For 1900mhz fclk around 1v is often enough on the 3d´s.


You guys and your ITX / 2 DIMM boards all rockin' 1T GDM Off.. jealous. I'll drop the vSOC a little more and get to ProcODT / RTT tuning later tomorrow. It just finished the 25 cycles with no errors even at these dimm temps. I have 2 Dominator Airflow coolers on the way, managed to find a great deal on 2 BNIB ones for like 75 bucks so I just had to grab those. I used to have a 120mm fan zip tied above the RAM but in this new case and with the way my tubing runs now I can't put it there anymore and it's ugly. This build is finally something that actually looks nice and isn't jank. I'll actually push the RAM once they come in. I know these DIMM's will do 3866 14-15-15-28-256-1T at 1.58v but they don't handle heat at those speeds.


----------



## Asterion

Ryzen 7 3700X | ASUS TUF Gaming X570-Plus (Wi-Fi) | 16GB Corsair Vengeance 3800MHz (16-15-15-30 46 (1T) | EVGA GTX 1070 SC | WD_BLACK SN770 500GB M.2 | Corsair RM650w | Windows 10 Pro 64-bit


----------



## StrongForce

Blameless said:


> What does the MP5_BUSY value actually represent?
> 
> I see between 35 and 42 on a fresh boot, reaching up to 49-50 after ~12 hours of stress testing.
> 
> 
> 
> Anything suspicious in event viewer? Any WHEA errors? Any GPU OC (unstable GPU can corrupt system memory contents, especially if ReBAR is enabled)?
> 
> 
> 
> FCLK can affect anything that passes through fabric and memory instability anything that passes through memory...this is pretty much everything.
> 
> Of course, an unstable SSD can also cause issues of it's own.


Nope GPU running stock, nothing in event viewer (a WMI warning appear after it hangs sometimes..IntelMeProv or something.. I don't have intel, *** ? lol might be something else..), how do I test for WHEA errors, with OCCT or is there something else? which setting, I had 1 when I tried the memory stress test but memory was unstable, someone said that it's caused by CPU not memory, so I ran ram stock just to make sure and it passed without error.

Last night I ran testmem5, I thought it might be a good idea to run the software from techpowerup testmem86+ at the same time, when I woke up in the middle of the night, my screen was black, and it was all buggy when I moved arround windows leaving ghosting, it was reaaaaly weird, I suspect my CPU was super overheating and throttling because I remember testing this software before and it heated the CPU quite a bit.

Some kind of memory leak with the softwares maybe also.. not sure, either way, I then ran prime95 memory test for 3hr without issues.

I know running 2 memory stress test was overkill, but I thought even if they don't have enough free memory, eventually testmem will finish and then the other 1 will take over, but it was a bad idea, not sure what went wrong exactly there..

Oh and my settings are exactly the same that passed testmem5 with 15 tests 25 cycles and 500% with the top profile except I put TRFC on auto, as someone suggested it could cause issues, it shows 312 in the bios, however in zentimings it's different..

Someone suggested to try 312 and some other, I tried 312 manually what was strange is that both my windows decided to scandisk when I did that before booting, it was scary.. it's why I put it on auto.

here is the screenshot of zentimings with current settings, will run again testmem5 see how it goes, oh and I played hours and hours today without issues with these settings aswell, haven't ran 3d mark but performance seem solid but it's strange that here tRFC shows 350ns then tRFC 630 ?!










also I plan to try to test to reduce the VSOC until it's not stable anymore see how it goes at some point.

but yeah so far I'm thinking this thing somehow messed with the SSD, if the SSD was bad, surely I would have issues during gaming.. unless the sectors my games are installed on are fine mmh

man I love hardware and computers but sometimes it's such a headache to troubleshoot..

PS: wow my bad, I just realized those 3 numbers for tRFC someone gave me are for tRFC 1, 2 and 4.. I only put the 1, which might be why the bios got confused and got those scandisks, will try those inputs as recommended and run tests, oops..


----------



## The_King

I dropped from 1966 FCLK to 1933 FCLK don't need to run VSOC @1.25V with VDIMM 1.55V or IOD @+1.15V anymore. Took a 1ns drop in latency but I can live with that.


----------



## Imprezzion

The_King said:


> I dropped from 1966 FCLK to 1933 FCLK don't need to run VSOC @1.25V with VDIMM 1.55V or IOD @+1.15V anymore. Took a 1ns drop in latency but I can live with that.
> 
> View attachment 2579695


Wow, 4 DIMM B450 board running 1T GDM Off without AddrCmdSetup 56 even? How did you manage that lol. It looks sweet. I might try your timing setup on mine as well if I can get the poor B550-A to do 1T GDM Off. I doubt my DIMM's can do it at that low of a vDIMM tho especially with them getting well over 50c.


----------



## The_King

Imprezzion said:


> Wow, 4 DIMM B450 board running 1T GDM Off without AddrCmdSetup 56 even? How did you manage that lol. It looks sweet. I might try your timing setup on mine as well if I can get the poor B550-A to do 1T GDM Off. I doubt my DIMM's can do it at that low of a vDIMM tho especially with them getting well over 50c.


The trick on my B450 was to get the correct ClkDrvStr for the specific DIMM with the same board and 4133 C19 (Another kit) I had to use ClkDrvStr 24 the 4000 C19 needs 60.
So it seems to me that Different DIMMs may need different ClkDrvStr to get GDM off 1T stable. At least this seems to be the case with My mobo.


----------



## Taraquin

Veii: Any tip on how to run Rtt_park disabled on 2xSR 4400c19 Vipers?


----------



## Blameless

StrongForce said:


> how do I test for WHEA errors, with OCCT or is there something else?


OCCT (large, extreme, variable, auto), y-cruncher (HNT), and XMRig are all pretty good at finding FCLK releated WHEA errors, especially if you run a GPU load at the same time.



StrongForce said:


> it's strange that here tRFC shows 350ns then tRFC 630 ?!


This is not strange.

350 _nanoseconds_ at 1800MHz *is* 630 _cycles_. 1.8 * 350 = 630.

A nanosecond is only one cycle at 1GHz (2000MT/s).


----------



## Imprezzion

Usually b-die will run around 130ns tRFC pretty easily. Under 130 is possible but requires a lot of vDIMM and low temps. I run 272 now which is around 143ns at 3800 but that's just because of temperatures. They will do 256 @ 134ns just fine as long as they are under 48-49c.

What kind of ProcODT and RTT / DrvStr's should I try for 1T on 3800/3866C15 on a B550-A and a 5800X3D with 2x16 DR B-Die? I will try the settings from a few posts above this but I'm not sure what exactly the settings actually do. I know pretty much everything with Intel RAM OC and it's ODT, RTL, skews and such but I know almost nothing of AMD specific settings and would like to learn what does what and what has what impact. I know AddrCmdSetup helps with 1T for example but I don't know why or what values to put in.


----------



## RackarN

tried turning off GDM and go 2T but holy **** that fine tuning was giving me nightmares.. dont think i can do better than this exept tRFC a bit lower.


----------



## MrFart

This baby will not, and I mean WILL NOT budge from Auto. It's only tCL, I was able to change tRCDRD just fine.
Anyone else with an MSI board knows *** is happening here?

















Anyways I tried tRCDRD at 17 and I can boot fine (latency in AIDA is now 0.8-1.2ns lower). I'm feeling kinda lazy, since the same config with tRDCRD at 18 survived 50 cycles of TM5 1usmus, can I skip testing for tRDCRD 17 or is that a bad idea?
Was not stable 🙁


----------



## Imprezzion

MrFart said:


> View attachment 2579808
> 
> 
> This baby will not, and I mean WILL NOT budge from Auto. It's only tCL, I was able to change tRCDRD just fine.
> Anyone else with an MSI board knows *** is happening here?
> 
> View attachment 2579809
> View attachment 2579810
> 
> 
> Anyways I tried tRCDRD at 17 and I can boot fine (latency in AIDA is now 0.8-1.2ns lower). I'm feeling kinda lazy, since the same config with tRDCRD at 18 survived 50 cycles of TM5 1usmus, can I skip testing for tRDCRD 17 or is that a bad idea?


Never skip testing a change. It might seem fine but what if you change a whole bunch of other stuff and get errors and think it was that stuff but it was tRDCRD the whole time and all the other stuff was stable. Been there done that.

I did get my setup to boot 1T GDM Off 3800 15-16-16 at least and got it sort of stable but it requires 60 ClkDrvStr and that gives PCB crashes (error 4's and error 0's) after like 30-40 minutes of TM5. I am running 51-52c there so maybe cooling will fix it or more vDIMM (only 1.51v) but at least it's a start.


----------



## HEYY0M1KEY

I am trying to test my GDM off 2T and my Curve. Each tested separately. TM5 runs with no errors up to 1 hour then the PC restarts. I'm assuming this is a PCB crash? No WHEA errors are reported. I've only ever had the operational whea 42 and 5 on PC startup. Is there a method I should try to figure it out? Something in Event logger possibly? I'm thinking more runs with Corecycler.


----------



## MrFart

Imprezzion said:


> Never skip testing a change. It might seem fine but what if you change a whole bunch of other stuff and get errors and think it was that stuff but it was tRDCRD the whole time and all the other stuff was stable. Been there done that.
> 
> I did get my setup to boot 1T GDM Off 3800 15-16-16 at least and got it sort of stable but it requires 60 ClkDrvStr and that gives PCB crashes (error 4's and error 0's) after like 30-40 minutes of TM5. I am running 51-52c there so maybe cooling will fix it or more vDIMM (only 1.51v) but at least it's a start.


It was unstable already even using chrome, webpages crashing and all that so yeah, that was a stupid and very quick experiment 
I guess I'll wait for a new BIOS version and try messing with tCL again, until then I'm happy with these timings and voltage. Thanks again to Blameless, Veii and The King.


----------



## mus1mus

I am having a terrible time stabilizing these sticks in a weird way. 

Stable for 4 hours prior to these settings and after a reboot trigger, "MEM OC FAILED" at POST. Only change made is *ProcODT.*

Can anyone explain why ProcODT at 32Ohms with 2 sticks now needing a higher setting with 4sticks??


----------



## Mikel_Ertz

Plz help me, i am always having error 4 in 1usmusv3. How can i fix it


----------



## RackarN

Mikel_Ertz said:


> Plz help me, i am always having error 4 in 1usmusv3. How can i fix it


----------



## Mikel_Ertz

RackarN said:


> View attachment 2579984


Yes, but what values should i change? i don't know what number use


----------



## Frosted racquet

Try with 6-3-3 RTTs instead of 7-3-3, and if that doesn't help try modifying *DrvStr to 40-20-30-24 for example depending on the RAM configuration- is it 2x16 Dual Rank or 4x8GB?


----------



## Mikel_Ertz

Frosted racquet said:


> Try with 6-3-3 RTTs instead of 7-3-3, and if that doesn't help try modifying *DrvStr to 40-20-30-24 for example depending on the RAM configuration- is it 2x16 Dual Rank or 4x8GB?


2x16 dual rank, i Will give a try. Ty


----------



## Frosted racquet

I had similar experience with the same 2x16GB config with TridentZ 3200 kit, only 1 random error in 12h testing (I don't remember which unfortunately). I don't know if our kits share the same PCB design but what helped me was the 40-20-30-24 configuration. Once I found a config which doesn't throw a random single error I didn't experiment further from the 40-20-30-24, so similar configs might work as well.


----------



## Mikel_Ertz

Frosted racquet said:


> I had similar experience with the same 2x16GB config with TridentZ 3200 kit, only 1 random error in 12h testing (I don't remember which unfortunately). I don't know if our kits share the same PCB design but what helped me was the 40-20-30-24 configuration. Once I found a config which doesn't throw a random single error I didn't experiment further from the 40-20-30-24, so similar configs might work as well.


Tyyy i will give a try


----------



## Mikel_Ertz

Frosted racquet said:


> I had similar experience with the same 2x16GB config with TridentZ 3200 kit, only 1 random error in 12h testing (I don't remember which unfortunately). I don't know if our kits share the same PCB design but what helped me was the 40-20-30-24 configuration. Once I found a config which doesn't throw a random single error I didn't experiment further from the 40-20-30-24, so similar configs might work as well.


Got 1 error


----------



## Frosted racquet

Sorry, someone else might have Hynix Micron E specific recommendation, don't have experience with Crucial Ballistix


----------



## Mikel_Ertz

Frosted racquet said:


> Sorry, someone else might have Hynix specific recommendation, don't have experience with Crucial Ballistix


Np, now i am trying 6-3-3 Rtts


----------



## The_King

Frosted racquet said:


> Sorry, someone else might have Hynix specific recommendation, don't have experience with Crucial Ballistix


RAM IC should be Micron E.Die not Hynix

@Mikel_Ertz
Not sure why you changed your DDs to 1s? Rather leave those on Auto. The only time I seen people use 1s is with 2 Single rank DIMMs. It may work in your case but I believe you maybe loosing performance somewhere by having them at 1.

Most of the time for me Auto works and I rarely see errors with my Micron RAM but I have never run 147 cycles! 

Micron E-die are very different from Samsung B-die @ 3800 in my testing RttNom was almost never enabled on Auto. I probably was using too high VDIMM here for these settings but these dimms rarely complain about voltages in my testing.
ProcODT was left on Auto so I did not set it to 48.


----------



## Mikel_Ertz

I Will change the DDs. How do i now if i am loosing performance? AIDA 64 RAM bench?


----------



## The_King

Mikel_Ertz said:


> I Will change the DDs. How do i now if i am loosing performance? AIDA 64 RAM bench?


Y-cruncher 2.5B is probably a better test to tell that compared to AIDA64.


----------



## RackarN

Mikel_Ertz said:


> I Will change the DDs. How do i now if i am loosing performance? AIDA 64 RAM bench?













this is how i run mine. 1.5v (or 1.55)


----------



## Mikel_Ertz

@The_King Testing 200 cycles... Let's see.


----------



## RackarN

i got tRRDS 4, tRRDL 4 and tFAW 16 to run with this setup.. shaved 20 minutes of 25 cycles.


----------



## Ramad

Frosted racquet said:


> Sorry, someone else might have Hynix Micron E specific recommendation, don't have experience with Crucial Ballistix


Look at my sig. below. I have tested 4 x 8GB of those using prime95 on 2 motherboards. They don't need high voltages and you can try Command Rate of 2T with GDM disabled. I think 2T gives better performance, but it's somthing you can experiment with to find the best settings for your system.


----------



## RackarN

Mikel_Ertz said:


> @The_King Testing 200 cycles... Let's see.


you could also be getting error 4 while using the PC at the same time  just found out, so i ran tests over night and its all fine.


----------



## mongoled

Long time no post here



Has anyone noticed any degradation with their fclk/mclk over time ?

I am unsure to what is the cause, maybe its because I flashed to newer bioses in the past and have returned to agesa based on agesa 1.1.9.0 (A.85 BIOS).

Basically, I need alot of "1.8v PLL" voltage to be stable at 3800/1900. My previous testing showed me that for the settings in my sig I required 1.87v (HWInfo64) for the Y-Cruncher VST test to pass consistently, now I have tested up to 2v and VST cannot pass consistently, it will fail after 10 consecutive runs or so, if I use 1.87v it will fail after one or two passes.

Also the CPU could have degraded? I use PBO, never done an extended (i.e. running for several weeks) all core overclock with high voltages.

The next step is probably for me to try a different BIOS before flashing back to 1.1.9.0.

Any thoughts much appreciated


----------



## Iarwa1N

Iarwa1N said:


> Hi guys, I just found a stable base, tested with 1usmus_v3 for an hour, can you point me to a direction where I can start more tweaking;
> 
> View attachment 2579076


I could use some help to improve this timings 🙏🏻


----------



## Mikel_Ertz

RackarN said:


> you could also be getting error 4 while using the PC at the same time  just found out, so i ran tests over night and its all fine.


 I was not using the PC. I leave the PC on while testing with the screen off.


----------



## Mikel_Ertz

RackarN said:


> you could also be getting error 4 while using the PC at the same time  just found out, so i ran tests over night and its all fine.


I was not using the PC. Just left the PC on while testing with the screen off


----------



## Veii

Mikel_Ertz said:


> Plz help me











Those are absolute minimum values.

@mongoled Running constantly near or over 1.9v VDD1P8 on MSI Unifies, will kill the board slowly but guaranteed ⚠
That 1.8 line is connected straight to the EEPROM, which is an 1.8v Chip. Design idea, unclear. Same till X570S - probably more MSI boards.
This and potential mislabeling issue of sometimes using 1.8v , sometimes 2.6-3.2v EEPROM ~ while data is 3.3v // similar issue to 5v rail on CH431 on 3.3v operation ... is why Unify's slowly die
*W25Q256J & W25Q256JW* mislabeling
Batch issue shouldn't be a known one, well should be but not public
1.8v rail design tho is a concerning one.

I would not suggest running it over 1.86v, worst 1.9. Bios caps at 1.95v for a reason
The chance of the chip "forgetting" stuff or simply frying, is too high (with couple of examples examined ~ couple here means over 4)

EDIT:
I'm sorry that it's figured out that late.
But i have to warn ⚠
This is a real thing and schematics show it clear
There might be more MSI boards affected by this design idea, but B550/X570/X570S Unify's are for sure
Also MSI prevents the giveout of MCU (flashback chip) firmware , when user replaces EEPROM by itself ~ just to notice that MCU also was DOA.
User is talented engineer and capable of EEPROM swap, but thanks to lack of right-for-repair ~ user has to always use a WSON Pogo for flashing


----------



## Mikel_Ertz

Veii said:


> Those are absolute minimum values.
> 
> @mongoled Running constantly near or over 1.9v VDD1P8 on MSI Unifies, will kill the board slowly but guaranteed
> That 1.8 line is connected straight to the EEPROM, which is an 1.8v. Design idea, unclear. Same till X570S - probably more MSI boards.
> This and potential mislabeling issue of sometimes using 1.8v , sometimes 2.6-3.2v EEPROM ~ while data is 3.3v // similar issue to 5v rail on CH431 on 3.3v operation ... is why Unify's slowly die
> Batch issue shouldn't be a known one, well should be but not public
> 1.8v rail design tho is a concerning one.
> 
> I would not suggest running it over 1.86v, worst 1.9.
> The chance of the chip "forgetting" stuff or simply frying, is too high
> 
> EDIT:
> I'm sorry that it's figured out that late.
> But i have to warn.
> This is a real thing and schematics show it clear


So, i need to put TRAS at 25 and tRC at 41?


----------



## RackarN

Mikel_Ertz said:


> So, i need to put TRAS at 25 and tRC at 41?


Of u have micron chip, that I suspect u have, i dont think u can run TRC that low. The recommended lowest values are what he suggested. So TRAS 25 would be correct


----------



## Imprezzion

Veii said:


> Those are absolute minimum values.
> 
> @mongoled Running constantly near or over 1.9v VDD1P8 on MSI Unifies, will kill the board slowly but guaranteed ⚠
> That 1.8 line is connected straight to the EEPROM, which is an 1.8v Chip. Design idea, unclear. Same till X570S - probably more MSI boards.
> This and potential mislabeling issue of sometimes using 1.8v , sometimes 2.6-3.2v EEPROM ~ while data is 3.3v // similar issue to 5v rail on CH431 on 3.3v operation ... is why Unify's slowly die
> *W25Q256J & W25Q256JW* mislabeling
> Batch issue shouldn't be a known one, well should be but not public
> 1.8v rail design tho is a concerning one.
> 
> I would not suggest running it over 1.86v, worst 1.9. Bios caps at 1.95v for a reason
> The chance of the chip "forgetting" stuff or simply frying, is too high
> 
> EDIT:
> I'm sorry that it's figured out that late.
> But i have to warn ⚠
> This is a real thing and schematics show it clear
> There might be more MSI boards affected by this design idea, but B550/X570/X570S Unify's are for sure
> Also MSI prevents the giveout of MCU (flashback chip) firmware , when user replaces EEPROM by itself ~ just to notice that MCU also was DOA.
> User is talented engineer and capable of EEPROM swap, but thanks to lack of right-for-repair ~ user has to always use a WSON Pogo for flashing


I hope ASUS isn't affected by this lol. My B550-A requires 1.840v on this line to run 1967 FCLK properly without WHEA or random idle freezes.

I run this now:









It needs a lot of VDDG's and vSOC to be able to run this much FCLK without WHEA's. At for example 1.08 CCD and 0.980 IOD and 1.09v vSOC it will WHEA a lot in heavy memory loads. This fixes it but it's.. high. Are these values anything to worry about combined with -30 CO on the CPU, 1.540v vDIMM and 1.840v CPU 1.8v? 

I will be dropping the primary timings back down to 14-15-15-28-42-240-2T again as soon as my Dominator Airflow coolers show up and the DIMM's won't run at 53c load anymore lol.


----------



## Veii

Iarwa1N said:


> I could use some help to improve this timings 🙏🏻


15 tRCD + tRTP 8 = 23, not 22
13 tRP + 23 tRAS then is correct, but not 22

tRAS will be postponed, that's correct
tRC will not be postponed on AMD, it will be timebroken on Intel tho. Here it will be halted and repeat in it's entire full length

tRAS has more than the rule that BZ explains
tRAS doesn't need to issue pre-charge command if sensing units detect cells with enough charge.
This is an exception, and why there are exploits. The same goes to tRC which doesn't need tRP to trigger, if you stack charges .

This is advanced and autocorrecting technique - not tracked unless enforced, and not enforceable unless DIMM chip (MSR) decides to enforce this mode by itself.
On this topic, Intel and AMD differ in "what refresh technique" will i use with tRC - hence "tRC optimal" is different up to platform and DIMM PCB capability ~ as also CHIP IMC capability


----------



## Veii

Imprezzion said:


> I hope ASUS isn't affected by this lol.


If you have a 1.95v cap, be aware - else unlikely. I don't think.
Could ask, but that warning is putting boardpartners on fire.
Prefer to keep a good relationship with all boardpartners and collegues. They struggle enough with AMD
The design is fine for normal operation, but be aware that this is a silenced issue on MSI & their "right to repair denial-policy" bothers me here 

ASUS and ASRock are helpful, Gigabyte improves too ~ MSI hopefully but some things need a bit more pushing.
Especially when it comes to things "dying by mysterious ways" yet ignoring the issue for 2 years & just happily doing RMAs vs a new revision and admitting of "messing up"
Which speaking of pushing . . . where is MSI AM5 1DPC lineup, guys  I know PCH issues but , come on


----------



## Veii

Imprezzion said:


> At for example 1.08 CCD and 0.980 IOD and 1.09v vSOC


You can't run SOC without some buffer to remain cLDO rails (VDDP and VDDG . . . ~42mV on 1CCD, ~60-75mV for dual CCDs)
Same as you can't run [AM5] VDD MISC now, without some buffer but SOC got decoupled 

High cLDO_VDDG CCD is a thing.
But it's mostly because of high procODT to begin with.
Pushes all other voltages up too , except memory. High procODT ruins memory signal-integrity and easily "overpowers" them 

EDIT:
Can you spot your issue:








What is 16 + 30 
It might be only stable, because you waste 44 tCK in the air~
If it was at least value 50, then you would've wasted 5tCK only


----------



## mongoled

Veii said:


> @mongoled Running constantly near or over 1.9v VDD1P8 on MSI Unifies, will kill the board slowly but guaranteed ⚠
> That 1.8 line is connected straight to the EEPROM, which is an 1.8v Chip. Design idea, unclear. Same till X570S - probably more MSI boards.
> This and potential mislabeling issue of sometimes using 1.8v , sometimes 2.6-3.2v EEPROM ~ while data is 3.3v // similar issue to 5v rail on CH431 on 3.3v operation ... is why Unify's slowly die
> *W25Q256J & W25Q256JW* mislabeling
> Batch issue shouldn't be a known one, well should be but not public
> 1.8v rail design tho is a concerning one.
> 
> I would not suggest running it over 1.86v, worst 1.9. Bios caps at 1.95v for a reason
> The chance of the chip "forgetting" stuff or simply frying, is too high (with couple of examples examined ~ couple here means over 4)
> 
> EDIT:
> I'm sorry that it's figured out that late.
> But i have to warn ⚠
> This is a real thing and schematics show it clear
> There might be more MSI boards affected by this design idea, but B550/X570/X570S Unify's are for sure
> Also MSI prevents the giveout of MCU (flashback chip) firmware , when user replaces EEPROM by itself ~ just to notice that MCU also was DOA.
> User is talented engineer and capable of EEPROM swap, but thanks to lack of right-for-repair ~ user has to always use a WSON Pogo for flashing


Good to see you still posting here



Was not aware of this issue with the Unify motherboards, had been running "1.8v PLL" at 1.85 set in BIOS for the last 18 months.

Also don't have a kit to read/write to the eeprom directly so have decided to flash the latest bios and "start from scratch" to see where it takes me.

3800/1900 with default settings had no issue passing VST test for 10 loop cycle. So I've just tightened a couple of settings from default and inputed the voltages and memory resistance/termination settings I used on 1.1.9.0 and am re-running the VST test....


----------



## Veii

mongoled said:


> Good to see you still posting here


Busy with a lot of things, and AM5 now (not personal system)
But not gone from OCN ~ just , absent a bit 
Welcome back mongoled 👋


----------



## RackarN

I think I've finally hit a wall.. 1.55v
tRCDRD won't move
tRP won't move
tRAS won't move
tRC won't move
tWR + tRTP won't move
tWTR_ won't move
I think it's only SCL that i have left to try at 2 🤦🏼‍♂️
(Balistix MAX 4400mhz cl19)


----------



## The_King

RackarN said:


> I think I've finally hit a wall.. 1.55v
> tRCDRD won't move
> tRP won't move
> tRAS won't move
> tRC won't move
> tWR + tRTP won't move
> tWTR_ won't move
> I think it's only SCL that i have left to try at 2 🤦🏼‍♂️
> (Balistix MAX 4400mhz cl19)
> 
> 
> View attachment 2580168


With both Micron E/B Die RCDRD does not scale with voltages (VDIMM). I was able to run 4133 CL16 with the same kit with just 1.46V and pass at least 5 cycles. So you probably using way too much voltage here.

I could run 3800 CL14 with just 1.45V without any problems. Also only needed 1.46V for this and it was stable. tPHYRDL is 28 dropping CL15 with GDM off changes that to 26.


----------



## Nighthog

Veii said:


> Those are absolute minimum values.
> 
> @mongoled Running constantly near or over 1.9v VDD1P8 on MSI Unifies, will kill the board slowly but guaranteed ⚠
> That 1.8 line is connected straight to the EEPROM, which is an 1.8v Chip. Design idea, unclear. Same till X570S - probably more MSI boards.
> This and potential mislabeling issue of sometimes using 1.8v , sometimes 2.6-3.2v EEPROM ~ while data is 3.3v // similar issue to 5v rail on CH431 on 3.3v operation ... is why Unify's slowly die
> *W25Q256J & W25Q256JW* mislabeling
> Batch issue shouldn't be a known one, well should be but not public
> 1.8v rail design tho is a concerning one.
> 
> I would not suggest running it over 1.86v, worst 1.9. Bios caps at 1.95v for a reason
> The chance of the chip "forgetting" stuff or simply frying, is too high (with couple of examples examined ~ couple here means over 4)
> 
> EDIT:
> I'm sorry that it's figured out that late.
> But i have to warn ⚠
> This is a real thing and schematics show it clear
> There might be more MSI boards affected by this design idea, but B550/X570/X570S Unify's are for sure
> Also MSI prevents the giveout of MCU (flashback chip) firmware , when user replaces EEPROM by itself ~ just to notice that MCU also was DOA.
> User is talented engineer and capable of EEPROM swap, but thanks to lack of right-for-repair ~ user has to always use a WSON Pogo for flashing


Is the VDD1.8 voltage issue verified and confirmed for real to be a issue on the MSI boards?

Really bad design decision then. I need to push above 2.000V on occasion for 2000+ FCLK on the Gigabyte Aorus Xtreme. I was wanting that same voltage range available on the MSI but it's not advised to even use 1.900V without potential failure of the board?
The Xtreme board only starts to complain with the PWM & fan controller misbehaving @ 2.100v+.

VDD18 has even more effect when using BCLK to adjust FCLK. (needs more to alleviate issues)


----------



## RackarN

The_King said:


> With both Micron E/B Die RCDRD does not scale with voltages (VDIMM). I was able to run 4133 CL16 with the same kit with just 1.46V and pass at least 5 cycles. So you probably using way too much voltage here.
> 
> I could run 3800 CL14 with just 1.45V without any problems. Also only needed 1.46V for this and it was stable. tPHYRDL is 28 dropping CL15 with GDM off changes that to 26.
> View attachment 2580170


Thanks for input! im gonna try it after 20 cycles are done for testing SCL 2


----------



## The_King

I did a small test which always gives me the same results. In AIDA64 with AddrCmdSetup 56 VS Real 1T. This has always been the case from my previous testing as well with my Setup.

So not sure why AddrCmdSetup 56 has a bad rep. It can save you a lot of headache and many hours of TM5 cycles also saves a lot on electricity. 

Real 1T after several runs the lowest I could get in AIDA64 52.5ns and L3 @ 10.7ns









AddrCmdSetup 56 AIDA64 52.2ns same L3 @ 10.7ns Basically no difference nothing that most people would notice?


----------



## Nighthog

RackarN said:


> Thanks for input! im gonna try it after 20 cycles are done for testing SCL 2


Micron rev.E usually scales tCL with voltage & speed.
As you increase the speed you need more voltage to maintain the same tCL stable. or you can increase voltage to push tCL as low as possible that the dimms can handle & drive safely.
If you can drive your kit @ 1.700V+ you can run some really low tCL on Micron. And the increased voltage usually might allow you to tun tSCL @ 2 as bonus.

Depends on the kit of memory if they tolerate 1.700V or such without issues. Running real low MEM VTT can allow you to push high voltage on some kits.
My kingston rev.E were easy to tolerate 1.700V while my Micron Ballistix kits need to push real low VTT in the 0.650-0.750V range maximum to drive 1.700V without issues. (not all motherboards allow you to do so)


----------



## Veii

RackarN said:


> I think I've finally hit a wall.. 1.55v


Your 1.1v VDDP is a preset for 2400 (4800MT/s) or higher
X3D is on better B2 substrate, which is low power
Drop that down to 900mV if not 860mV ~ same for IOD and CCD can run lower, but those are ok


Nighthog said:


> Is the VDD1.8 voltage issue verified and confirmed for real to be a issue on the MSI boards?


100% guaranteed an issue traced by schematics
It's multi layer, and they don't deserve bashing - but a bit yes because of anti right-to-repair behavior 
They are well aware of their issue(s) and again happily RMA - but it is not ok to prevent capable engineers repairing their gear, when such costs business downtime.
And it's sad to hurt board's designer reputation with their good work (except this thing)
Also it's not ok to have a different RMA policy between regions. . . (personal/friends experience, not youtuber complain which actually fits the same experience)

CPU 1.8v rail is used to power EEPROM
1.8v EEPROM can sustain spikes to 1.93v , or longer at 1.9v - but i don't want to recommend ever running past 1.86v on it

2nd issue with 3.3v data rail & different EEPROM (typo) is a batch issue, it's not a global issue.
This 1.8 rail design tho is a global design 
Again they don't deserve bashing, because it works to specs - but it's just . . . a bit problematic designed.
All doesn't matter if they would be open to users replacing their parts... but in 2022 such is still rare
Also no idea how MCU fried of engineer friend - but that's what he got by buying "new" 
Dead EEPROM's he replaced, other friend has 3rd dead unify by repetitive updating (and likely own OC issue via APU)

Else i think i like the board a lot, and their employed OCer ~ i miss them on AM5 too
But just users should be aware ~ do NOT exceed 1.9v on this rail on MSI boards. You play Russian Roulette with your board
Extra warning, because i know i recommended it for other boards and early research


Nighthog said:


> I need to push above 2.000V on occasion for 2000+ FCLK on the Gigabyte Aorus Xtreme


EDIT:
Also you can't
Limit allowed is 1.95v

But honestly,
1.86v was perfectly fine for me till 2067 FCLK
2100 just needed 1.93, but AMD has changed a lot again on AGESA 1206 onwards.
People get less WHEA now and can run higher FCLK
Maybe it's better now


----------



## RackarN

Nighthog said:


> Micron rev.E usually scales tCL with voltage & speed.
> As you increase the speed you need more voltage to maintain the same tCL stable. or you can increase voltage to push tCL as low as possible that the dimms can handle & drive safely.
> If you can drive your kit @ 1.700V+ you can run some really low tCL on Micron. And the increased voltage usually might allow you to tun tSCL @ 2 as bonus.
> 
> Depends on the kit of memory if they tolerate 1.700V or such without issues. Running real low MEM VTT can allow you to push high voltage on some kits.
> My kingston rev.E were easy to tolerate 1.700V while my Micron Ballistix kits need to push real low VTT in the 0.650-0.750V range maximum to drive 1.700V without issues. (not all motherboards allow you to do so)


Tried to go down a bit in voltage but it seems like 1.5 is lowest, lowering tRCDRD was still giving me BSOD.
Set lose timings @1.45 was still giving me BSOD so I'm just gonna leave that bastard for now (17 seemed fine here aswell)

1.7 seems like things would start to get hot 🥵 haha! But it seems like memory ia only hitting 44 thus far, incoming air in the PC is 28 ATM. (All radiators in, 1, 140mm out) but it has room to push air out from vents and the PSU so I don't see that as an issue. Might need a fan on the ram tho if I'm going that high on voltage.


----------



## Nighthog

RackarN said:


> Tried to go down a bit in voltage but it seems like 1.5 is lowest, lowering tRCDRD was still giving me BSOD.
> Set lose timings @1.45 was still giving me BSOD so I'm just gonna leave that bastard for now (17 seemed fine here aswell)
> 
> 1.7 seems like things would start to get hot 🥵 haha! But it seems like memory ia only hitting 44 thus far, incoming air in the PC is 28 ATM. (All radiators in, 1, 140mm out) but it has room to push air out from vents and the PSU so I don't see that as an issue. Might need a fan on the ram tho if I'm going that high on voltage.


Yeah you need extra cooling at such voltages. But depending on kit you might have ~1.600V limit unless you do the VTT trick. They just start to throw errors from the voltage alone unless you push VTT low enough.


----------



## Imprezzion

Veii said:


> You can't run SOC without some buffer to remain cLDO rails (VDDP and VDDG . . . ~42mV on 1CCD, ~60-75mV for dual CCDs)
> Same as you can't run [AM5] VDD MISC now, without some buffer but SOC got decoupled
> 
> High cLDO_VDDG CCD is a thing.
> But it's mostly because of high procODT to begin with.
> Pushes all other voltages up too , except memory. High procODT ruins memory signal-integrity and easily "overpowers" them
> 
> EDIT:
> Can you spot your issue:
> 
> 
> 
> 
> 
> 
> 
> 
> What is 16 + 30
> It might be only stable, because you waste 44 tCK in the air~
> If it was at least value 50, then you would've wasted 5tCK only


Ah yeah. I tested with 15-15-15 first which errors due to too high DIMM temps and forgot to raise tRC accordingly after switching to 16 RCD and RP. My bad.. 

I guess I have something to do later tonight. Could you maybe give me some values for ProcODT, DrvStr's and RTT's I can try? It's been a while since I used AMD.. I traded my 5900X quite quickly with all the AGESA TPM stuttering issues back with 1.2.0.3 for a 11900K and only just got this kit back in..


----------



## RackarN

Nighthog said:


> Yeah you need extra cooling at such voltages. But depending on kit you might have ~1.600V limit unless you do the VTT trick. They just start to throw errors from the voltage alone unless you push VTT low enough.


VTT seems to be forced at halv dram v -_- so that was 0.85. was a bust anyhow.. but since i have GDM i tried CL12 lol.. gonna have to go down that rabbithole again


----------



## Nighthog

Veii said:


> Your 1.1v VDDP is a preset for 2400 (4800MT/s) or higher
> X3D is on better B2 substrate, which is low power
> Drop that down to 900mV if not 860mV ~ same for IOD and CCD can run lower, but those are ok
> 
> 100% guaranteed an issue traced by schematics
> It's multi layer, and they don't deserve bashing - but a bit yes because of anti right-to-repair behavior
> They are well aware of their issue(s) and again happily RMA - but it is not ok to prevent capable engineers repairing their gear, when such costs business downtime.
> And it's sad to hurt board's designer reputation with their good work (except this thing)
> Also it's not ok to have a different RMA policy between regions. . . (personal/friends experience, not youtuber complain which actually fits the same experience)
> 
> CPU 1.8v rail is used to power EEPROM
> 1.8v EEPROM can sustain spikes to 1.93v , or longer at 1.9v - but i don't want to recommend ever running past 1.86v on it
> 
> 2nd issue with 3.3v data rail & different EEPROM (typo) is a batch issue, it's not a global issue.
> This 1.8 rail design tho is a global design
> Again they don't deserve bashing, because it works to specs - but it's just . . . a bit problematic designed.
> All doesn't matter if they would be open to users replacing their parts... but in 2022 such is still rare
> Also no idea how MCU fried of engineer friend - but that's what he got by buying "new"
> Dead EEPROM's he replaced, other friend has 3rd dead unify by repetitive updating (and likely own OC issue via APU)
> 
> Else i think i like the board a lot, and their employed OCer ~ i miss them on AM5 too
> But just users should be aware ~ do NOT exceed 1.9v on this rail on MSI boards. You play Russian Roulette with your board
> Extra warning, because i know i recommended it for other boards and early research
> 
> EDIT:
> Also you can't
> Limit allowed is 1.95v
> 
> But honestly,
> 1.86v was perfectly fine for me till 2067 FCLK
> 2100 just needed 1.93, but AMD has changed a lot again on AGESA 1206 onwards.
> People get less WHEA now and can run higher FCLK


*Aorus Xtreme*, it has real high allowance on the voltage you can push there. (no limit?)

The VDD18 voltage solves issues with my Audio crackle & USB connection problems to a extent added with correct voltages for SoC & VDDG.
Maybe onboard audio has no issues but my USB DAC throws crackle out if it's not tuned correctly, and my keyboard shows input issues if they aren't right.
BCLK just adds noise on top requiring extra tuning.
I'm doing 102.5BCLK for 2050FCLK at the moment with 4100Mts memory. Wanted some extra CPU boost. So doing what is needed for it to work.
Without BCLK I needed less VDD18 overall. But BCLK pushed the requirement higher.

EDIT: Besides my 5800X3D isn't the best with regard to FCLK/MCLK etc overall, my old 3800X had a better memory controller.


----------



## RackarN

Nighthog said:


> *Aorus Xtreme*, it has real high allowance on the voltage you can push there. (no limit?)
> 
> The VDD18 voltage solves issues with my Audio crackle & USB connection problems to a extent added with correct voltages for SoC & VDDG.
> Maybe onboard audio has no issues but my USB DAC throws crackle out if it's not tuned correctly, and my keyboard shows input issues if they aren't right.
> BCLK just adds noise on top requiring extra tuning.
> I'm doing 102.5BCLK for 2050FCLK at the moment with 4100Mts memory. Wanted some extra CPU boost. So doing what is needed for it to work.
> Without BCLK I needed less VDD18 overall. But BCLK pushed the requirement higher.
> 
> EDIT: Besides my 5800X3D isn't the best with regard to FCLK/MCLK etc overall, my old 3800X had a better memory controller.


hmm. i run 102 bclk but i have no crackle sound from mic or headphones. White noise from the IEM's tho but i think i had it before aswell.
i have a Komplete Audio 1 sound card (USB, XLR mic). i just got lucky i assume.
2050FCLK is pretty good for the X3D, top 1% probably, mine wont let me do more than 1933 -_- not sure how to get rid of WHEA's yet. I guess its another rabbithole i have to visit sometime. 

I also just realized that this overclocking thing, we all probably have been doing for some time now, is a hobby lol.. never seen it this way.... i mean, why chasing RAM timings for days if it wasn't.. i guess im a bit slow lol


----------



## Nighthog

RackarN said:


> hmm. i run 102 bclk but i have no crackle sound from mic or headphones. White noise from the IEM's tho but i think i had it before aswell.
> i have a Komplete Audio 1 sound card (USB, XLR mic). i just got lucky i assume.
> 2050FCLK is pretty good for the X3D, top 1% probably, mine wont let me do more than 1933 -_- not sure how to get rid of WHEA's yet. I guess its another rabbithole i have to visit sometime.
> 
> I also just realized that this overclocking thing, we all probably have been doing for some time now, is a hobby lol.. never seen it this way.... i mean, why chasing RAM timings for days if it wasn't.. i guess im a bit slow lol


Mine doesn't do better than 1900FCLK without WHEA, it's just the whea is not an actual issue overall for performance if you get the voltages right. (way to high)
My 5800X3D is not a good sample with regard to this. Just barely does 1900FCLK if I want it WHEA free. 

I just like to brute force things when they don't want to give me what I wanted from it.
My older 3800X was better actually from the IOD overall. They just had other limits.


----------



## blodflekk

Iarwa1N said:


> I could use some help to improve this timings 🙏🏻


You don't need setup timings to run 2T, so you can remove addrcmdsetup 56. You could also try running tWR 12 and tRTP 6


----------



## Mikel_Ertz

I finally got it to be stable! I will put tRAS at 25 as recommended. What timings can I reduce more? And what values could I try?


----------



## Frosted racquet

Wow, and here I though I was crazy for doing 100 cycles of 1usmus


----------



## RackarN

SCL 3 (both) if it passes 2
tRP - as low as it can go (that's how I did atleast)
tWRRD - can it hit 1?


----------



## Mikel_Ertz

RackarN said:


> SCL 3 (both) if it passes 2
> tRP - as low as it can go (that's how I did atleast)
> tWRRD - can it hit 1?


ty, i will try. Need to complete 13 cycles to reach 200


----------



## The_King

Mikel_Ertz said:


> I finally got it to be stable! I will put tRAS at 25 as recommended. What timings can I reduce more? And what values could I try?
> View attachment 2580189


You can try for GDM disable 1T. May need a slight bump in VDIMM or may not. I usually just disable with most of my E-die and have not had any issues most of the time.


----------



## RackarN

Passed 20 cycles, Aida test and y-crunchers Pi. Might look at the FCLK thing for now.. decent timings for 24/7, but still room for improvement


----------



## ReyReverse

people should aware 1.8 PLL
I was pump my 1.8 PLL to 2.33v stable my 5950x on FCLK 2000 to fix WHEA problem at high PBO settings
250-160-205 full load without any issues for the first and second month

after that some degradation came.......one of my core become bad core no matter how I tweak it, positive +30 or all core positive offset 0.05 the problem is still there, it can't be fix.

so sad, now I have to upgrade my pc to intel 13 gen 🤣😂


----------



## The_King

ReyReverse said:


> people should aware 1.8 PLL
> I was pump my 1.8 PLL to 2.33v stable my 5950x on FCLK 2000 to fix WHEA problem at high PBO settings
> 250-160-205 full load without any issues for the first and second month
> 
> after that some degradation came.......one of my core become bad core no matter how I tweak it, positive +30 or all core positive offset 0.05 the problem is still there, it can't be fix.
> 
> so sad, now I have to upgrade my pc to intel 13 gen 🤣😂


I guess it maybe a good thing that I can't adjust that setting on my board, because I would certainly try to get high FCLK stable if I could.


----------



## sxeneize

Mikel_Ertz said:


> ty, i will try. Need to complete 13 cycles to reach 200


Did you check for WHEA?
I have the same kit. Let me know if you can run GDM off. Mine doesn't POST when i set 2T.


----------



## Mikel_Ertz

sxeneize said:


> Did you check for WHEA?
> I have the same kit. Let me know if you can run GDM off. Mine doesn't POST when i set 2T.


I do not check for whea, running stock CPU. I will let you know if i can boot with GDM OFF


----------



## sxeneize

Mikel_Ertz said:


> I do not check for whea, running stock CPU. I will let you know if i can boot with GDM OFF


I got WHEA's at 1900 FCLK. I had to raise VSOC.
It's a 5900x anyway.


----------



## Mikel_Ertz

sxeneize said:


> I got WHEA's at 1900 FCLK. I had to raise VSOC.
> It's a 5900x anyway.


My VSOC is 1.1 i think


----------



## Rexbag

Mikel_Ertz said:


> I do not check for whea, running stock CPU. I will let you know if i can boot with GDM OFF


If you don’t check for WHEA then what’s the value of this profile?

Tons of us, myself included, can boot and run benchmarks and such with FCLK higher than 1900MHz. I haven’t seen anyone with a dual-CCD Zen 3 that can do it truly WHEA-free, though, and that makes it pretty worthless. Benchmark scores can be all over the place due to WHEA, indicating eratic performance degradation. That’s why we all end up running 3800MT/s, assuming we even can. There’s no value going higher than that if WHEAs tank performance.


----------



## Mikel_Ertz

Rexbag said:


> If you don’t check for WHEA then what’s the value of this profile?
> 
> Tons of us, myself included, can boot and run benchmarks and such with FCLK higher than 1900MHz. I haven’t seen anyone with a dual-CCD Zen 3 that can do it truly WHEA-free, though, and that makes it pretty worthless. Benchmark scores can be all over the place due to WHEA, indicating eratic performance degradation. That’s why we all end up running 3800MT/s, assuming we even can. There’s no value going higher than that if WHEAs tank performance.


I am running a 5800X. Not dual CCD. When i get home, i Will check for WHEA in the event logger


----------



## Veii

Rexbag said:


> That’s why we all end up running 3800MT/s, assuming we even can.


I'm sorry you're not long on OCN , for a near 1050 page thread 
Things changed a lot around since 1206 AGESA , 1207 onwards ~ in Vermeer's lifespan


----------



## MrFart

Mikel_Ertz said:


> I finally got it to be stable! I will put tRAS at 25 as recommended. What timings can I reduce more? And what values could I try?
> View attachment 2580189


Could you post an AIDA64 benchmark screenshot? cuz those timings look good, I wonder how much better they are than what I'm currently running.


----------



## Mikel_Ertz

MrFart said:


> Could you post an AIDA64 benchmark screenshot? cuz those timings look good, I wonder how much better they are than what I'm currently running.


Gyazo 









Gyazo







gyazo.com













Gyazo







gyazo.com













Gyazo







gyazo.com


----------



## Mikel_Ertz

The_King said:


> You can try for GDM disable 1T. May need a slight bump in VDIMM or may not. I usually just disable with most of my E-die and have not had any issues most of the time.


Not working. When the PC boot, got a error screen


----------



## Mikel_Ertz

Rexbag said:


> If you don’t check for WHEA then what’s the value of this profile?
> 
> Tons of us, myself included, can boot and run benchmarks and such with FCLK higher than 1900MHz. I haven’t seen anyone with a dual-CCD Zen 3 that can do it truly WHEA-free, though, and that makes it pretty worthless. Benchmark scores can be all over the place due to WHEA, indicating eratic performance degradation. That’s why we all end up running 3800MT/s, assuming we even can. There’s no value going higher than that if WHEAs tank performance.


i have checked, and not WHEAS


----------



## MrFart

Mikel_Ertz said:


> Gyazo
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Gyazo
> 
> 
> 
> 
> 
> 
> 
> gyazo.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Gyazo
> 
> 
> 
> 
> 
> 
> 
> gyazo.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Gyazo
> 
> 
> 
> 
> 
> 
> 
> gyazo.com


63.9ns with those timings? are you sure you don't have some heavy background processes messing up your results?


----------



## Mikel_Ertz

Yes, msi afterburner, logitech g hub, immerse, discord, steam, nvdia where running. I am on W11 stock cpu settings. Also, i have GDM ON and Dram latency echance in the bios with "msi setting"


MrFart said:


> 63.9ns with those timings? are you sure you don't have some heavy background processes messing up your results?
> View attachment 2580251
> View attachment 2580252


----------



## MrFart

Mikel_Ertz said:


> Yes, msi afterburner, logitech g hub, immerse, discord, steam, nvdia where running. I am on W11 stock cpu settings. Also, i have GDM ON and Dram latency echance in the bios with "msi setting"


DRAM latency enhance made me unable to POST the other day lol. I also have an MSI board.
64ns seems like a lot for timings like yours on 3800. Try restarting and not launching any of those programs and redo the latency thing again.


----------



## Mikel_Ertz

MrFart said:


> DRAM latency enhance made me unable to POST the other day lol. I also have an MSI board.
> 64ns seems like a lot for timings like yours on 3800. Try restarting and not launching any of those programs and redo the latency thing again.


Programs closed


----------



## Luggage

Veii said:


> Your 1.1v VDDP is a preset for 2400 (4800MT/s) or higher
> X3D is on better B2 substrate, which is low power
> Drop that down to 900mV if not 860mV ~ same for IOD and CCD can run lower, but those are ok
> 
> 100% guaranteed an issue traced by schematics
> It's multi layer, and they don't deserve bashing - but a bit yes because of anti right-to-repair behavior
> They are well aware of their issue(s) and again happily RMA - but it is not ok to prevent capable engineers repairing their gear, when such costs business downtime.
> And it's sad to hurt board's designer reputation with their good work (except this thing)
> Also it's not ok to have a different RMA policy between regions. . . (personal/friends experience, not youtuber complain which actually fits the same experience)
> 
> CPU 1.8v rail is used to power EEPROM
> 1.8v EEPROM can sustain spikes to 1.93v , or longer at 1.9v - but i don't want to recommend ever running past 1.86v on it
> 
> 2nd issue with 3.3v data rail & different EEPROM (typo) is a batch issue, it's not a global issue.
> This 1.8 rail design tho is a global design
> Again they don't deserve bashing, because it works to specs - but it's just . . . a bit problematic designed.
> All doesn't matter if they would be open to users replacing their parts... but in 2022 such is still rare
> Also no idea how MCU fried of engineer friend - but that's what he got by buying "new"
> Dead EEPROM's he replaced, other friend has 3rd dead unify by repetitive updating (and likely own OC issue via APU)
> 
> Else i think i like the board a lot, and their employed OCer ~ i miss them on AM5 too
> But just users should be aware ~ do NOT exceed 1.9v on this rail on MSI boards. You play Russian Roulette with your board
> Extra warning, because i know i recommended it for other boards and early research
> 
> EDIT:
> Also you can't
> Limit allowed is 1.95v
> 
> But honestly,
> 1.86v was perfectly fine for me till 2067 FCLK
> 2100 just needed 1.93, but AMD has changed a lot again on AGESA 1206 onwards.
> People get less WHEA now and can run higher FCLK
> Maybe it's better now


Never touched 1.8 - runs auto at ~1.85 on x570 unify on all bios I can remember. (If it this one…)


----------



## MrFart

Mikel_Ertz said:


> Programs closed
> View attachment 2580261


Looks a lot better.
This is what I get in safe mode right now:









Safe mode results don't mean much obviously because they're not representative of real world use cases but it's fun to see the latency go down like that


----------



## Mikel_Ertz

MrFart said:


> Looks a lot better.
> This is what I get in safe mode right now:
> View attachment 2580266
> 
> 
> Safe mode results don't mean much obviously because they're not representative of real world use cases but it's fun to see the latency go down like that


Gyazo i want to decrease the voltages, what should i try?


----------



## gvansly1

gvansly1 said:


> Hey everyone,
> Avid follower of this thread. I have questions regarding tPHYRDL, and excuse me if they have already been answered here.
> 1: What exactly is it?
> 2: Why does it change between dimms after changing BIOS settings?
> 3: Does it matter? Either stability or performance wise?
> 
> And one question regarding WHEA19 error. If I'm only getting one after a restart and none in between use and restart this seems to be ok with me, thoughts
> 
> Thanks in advance


Anybody?


----------



## byDenoso

@Veii i need a little help here...


----------



## Iarwa1N

Veii said:


> 15 tRCD + tRTP 8 = 23, not 22
> 13 tRP + 23 tRAS then is correct, but not 22
> 
> tRAS will be postponed, that's correct
> tRC will not be postponed on AMD, it will be timebroken on Intel tho. Here it will be halted and repeat in it's entire full length
> 
> tRAS has more than the rule that BZ explains
> tRAS doesn't need to issue pre-charge command if sensing units detect cells with enough charge.
> This is an exception, and why there are exploits. The same goes to tRC which doesn't need tRP to trigger, if you stack charges .
> 
> This is advanced and autocorrecting technique - not tracked unless enforced, and not enforceable unless DIMM chip (MSR) decides to enforce this mode by itself.
> On this topic, Intel and AMD differ in "what refresh technique" will i use with tRC - hence "tRC optimal" is different up to platform and DIMM PCB capability ~ as also CHIP IMC capability





blodflekk said:


> You don't need setup timings to run 2T, so you can remove addrcmdsetup 56. You could also try running tWR 12 and tRTP 6


Thanks a lot. I changed;

tRTP to 6 (was 7)
tWR to 12 (was 14)
tRAS to 21 (was 22) ==> tRCD 15 + tRTP 6
AddrCmdSetup to 0 (was 56, I was using 1T 3600hz before, forgot to change this after 2T)

But I couldn't change tRC to 34 (tRP 13 + tRAS 21), I got lots of errors on test 6, then I tried 35 and this time I got errors on test 0. My vDIMM is 1.56V. Should I try changing the voltage?
With this changes my latency drop to 56.6 from 57.7. Previous results here.


----------



## Nighthog

ReyReverse said:


> people should aware 1.8 PLL
> I was pump my 1.8 PLL to 2.33v stable my 5950x on FCLK 2000 to fix WHEA problem at high PBO settings
> 250-160-205 full load without any issues for the first and second month
> 
> after that some degradation came.......one of my core become bad core no matter how I tweak it, positive +30 or all core positive offset 0.05 the problem is still there, it can't be fix.
> 
> so sad, now I have to upgrade my pc to intel 13 gen 🤣😂


Did you try to go lower on FCLK again to check stability? Or go back to stock?
What kind of cooling were you using?

Would be nice to know some more details about the circumstances it happened in.


----------



## StevieRay2

edit: answered


----------



## RackarN

I don't know if I'm looking for a headache just for fun or not but.

I'm trying to get 1t without GDM to run at 2040 on my memory now.. I'm just lost how to configure procODT and RTT and all resistance values are completely unknown to me. 2x 8gb micron.










Was able to boot but it was a slideshow instead with this.. (it's ok if u laugh at my ignorance)


----------



## The_King

From the 4 X Patriot Viper Steel 4000 C19 kits I have this the weakest when it comes to RCDRD.
Small compromise on RCDRD with AddrCmdSetup 56 which dropped voltages from 1.55V to 1.5V!!!


----------



## RackarN

The_King said:


> From the 4 X Patriot Viper Steel 4000 C19 kits I have this the weakest when it comes to RCDRD.
> Small compromise on RCDRD with AddrCmdSetup 56 which dropped voltages from 1.55V to 1.5V!!!


 You think that's weak? Hold my beer!










Stable for now, if i drop it to 18 i get error 6, 0, 12


----------



## The_King

RackarN said:


> You think that's weak? Hold my beer!
> 
> View attachment 2580495
> 
> 
> Stable for now, if i drop it to 18 i get error 6, 0, 12


Can't remember if you tried 3933 CL15/16 with RCDRD 17? I think you would see better performance overall with that than going to 4000 RCD 19.
I posted a profile I was running a few pages back that was stable but never ran 25 cycles on it. I'm sure it would pass though.

My Patriot Viper Steel RAM has Samsung B-die IC's so it can do much lower RCDRD than what the Micron E-Die RAM can do. Those Micron Kits still perform really well and you can get low CL has that scales with voltages on those kits. 4000 CL14 is doable with that kit but I would go for the lower RCDRD 17 @ 3933


----------



## RackarN

Yeah I might have to find a middle ground, i think it won't do 17 over 1933 🤦🏼‍♂️

Gonna start with 3943, if it works for 5 rounds I'll try up one more step and test 25 rounds.
I'm pretty sure CL would do 15 if i could get GDM off


----------



## The_King

RackarN said:


> Yeah I might have to find a middle ground, i think it won't do 17 over 1933 🤦🏼‍♂️
> 
> Gonna start with 3943, if it works for 5 rounds I'll try up one more step and test 25 rounds.
> I'm pretty sure CL would do 15 if i could get GDM off


Please try with this profile and voltages. I got it to run with 4 DIMMS so I think with 2 you should need even less voltage try with 1.45V-1.47V








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


I've updated my custom power plans for Win10 and created a new one for Win11. In my signature.




www.overclock.net





If you get any errors early in the test change WTRS/L to 4/8 if that does not help the try 5/10. This is the main setting that I found that causes issues with Micron RAM and TM5


----------



## RackarN

i think i tried it before, but as u say WTRS/L might have been the one before. i ran 4/8 without errors so if it gives errors now, thats where i'll start. ty

@The_King had to make some adjustments to procODT, rtt and drvStr but it seems mostly fine. Had some timings lower that i kept









Gonna see if I can get SCL down to 2 like before with this speed since it's not that much higher


----------



## The_King

The_King said:


> From the 4 X Patriot Viper Steel 4000 C19 kits I have this the weakest when it comes to RCDRD.
> Small compromise on RCDRD with AddrCmdSetup 56 which dropped voltages from 1.55V to 1.5V!!!
> View attachment 2580486


0.2ns faster by dropping ClkDrvStr from 60 to 20 which it seems was not needed. That's a huge difference in time for a Formula One car (F1).


----------



## sxeneize

Can't POST when i set GDM off 2T.
Any ideas?


----------



## The_King

sxeneize said:


> Can't POST when i set GDM off 2T.
> Any ideas?
> 
> View attachment 2580604


Not sure why you want 2T just turn GMD off and run 1T.

Voltage between 1.4V to 1.45V can help. (VDIMM)

If it still does not boot then you have to increase RCDRD to 18 and it should work then.


----------



## The_King

double post.


----------



## sxeneize

The_King said:


> Not sure why you want 2T just turn GMD off and run 1T.
> 
> Voltage between 1.4V to 1.45V can help. (VDIMM)
> 
> If it still does not boot then you have to increase RCDRD to 18 and it should work then.


It doesn't work. GDM off 1T or 2T.
I tried loose timings (16-20-20-40), xmp timings, everything at auto and 1.5v. Nothing works.


----------



## HEYY0M1KEY

HEYY0M1KEY said:


> Does TM5 report threads starting at 0 and ending at 15? I was testing my 3800 2T profile with my PBO curve and was getting a crash around 1 hour on "Core 15".
> 
> Previous curve I have tested quite a bit with Corecycler and Y-Cruncher with my GDM on profile. Lowered the curve and now it didn't crash, this time at least.
> View attachment 2579544


Still getting PC reboots at 1 hour point. Testing again to see if RCDRD 14 vs 15 is the cause or possibly TCWL at 12, which seems the case. VDIMM 1.55. Dimms never go above 43 degrees so it shouldn't be temps. Haven't had luck with adjusting voltages. I cannot get any Drv strength combos other than 60,20,20,20 to post with GDM off.

I would appreciate any advice.


----------



## Imprezzion

If I wanna run / test with 1T GDM On. Do I still need AddrCmdSetup for that to work in general or can I just leave it 0? And does GDM only affect uneven primary or CAS or also secondary timings like tRTP? Which would be 5 with tWR 10 thus uneven?

I also found out ClkDrvStr 60 is too much for the PCB's. It starts to get a LOT of PCB crash related errors in TM5.. shame. I know the Trident-Z Neo 3600C16 PCB is only 8 layer and not as good as higher bins but I expected better.


----------



## The_King

sxeneize said:


> It doesn't work. GDM off 1T or 2T.
> I tried loose timmings (16-20-20-40), xmp timmings, everything at auto and 1.5v. Nothing works.


With Micron RAM you get different speed grades. Older IC's don't perform the same has newer revised ones. 

If your RAM stock XMP is 3600 16-20-20-20 then its likely that your RAM is not even stable @ 3800 with RCD 17.
You would need something like 3800 16-21-21-21 or maybe 3800 16-22-22-22.

I would also try without WTRS/L 2/6 and run 4/8 or 5/10.


----------



## sxeneize

The_King said:


> With Micron RAM you get different speed grades. Older IC's don't perform the same has newer revised ones.
> 
> If your RAM stock XMP is 3600 16-20-20-20 then its likely that your RAM is not even stable @ 3800 with RCD 17.
> You would need something like 3800 16-21-21-21 or maybe 3800 16-22-22-22.
> 
> I would also try without WTRS/L 2/6 and run 4/8 or 5/10.


XMP profile is 16-18-18-38. I tried even looser timings to see if i can POST with CR 2T or 1T.
I tried with everything at auto, WTRS/L included. 3600 also.

From what i was reading 2T is supposed to work without changing anything. It's very strange.


----------



## HEYY0M1KEY

Imprezzion said:


> If I wanna run / test with 1T GDM On. Do I still need AddrCmdSetup for that to work in general or can I just leave it 0? And does GDM only affect uneven primary or CAS or also secondary timings like tRTP? Which would be 5 with tWR 10 thus uneven?
> 
> I also found out ClkDrvStr 60 is too much for the PCB's. It starts to get a LOT of PCB crash related errors in TM5.. shame. I know the Trident-Z Neo 3600C16 PCB is only 8 layer and not as good as higher bins but I expected better.


From what I’ve seen and read you should not need setup timings with GDM on. It will round all primary timings up, so 15 will turn to 16. I don’t see any other timings rounded on my GDM on profile. I attached mine for reference, TRTP I set to 6 here because I forgot to change it to 5.


----------



## The_King

sxeneize said:


> XMP profile is 16-18-18-38. I tried even looser timmings to see if i can POST with CR 2T or 1T.
> I tried with everything at auto, WTRS/L included. 3600 also.
> 
> From what i was reading 2T is supposed to work without changing anything. It's very strange.


Only other thing can suggest then is to give the VSOC some extra juice 1.15V - 1.2V. which should be generally safe.


----------



## StevieRay2

With soc 1.1, vddp .95, vddgs 1.05 I can't boot into windows at 1900 fclk but I can at 1933 and 2000 but getting 15 kernel whea 20 errors in 1 minute, anyway to get rid of them?
or I'm just not able to go to 1933, and maybe stick with 1800 then and tighten timings?

Also I'm following the DRAM Calc program with the fast setting, so far I have this, any settings I should change or lower?
Also on the DRAM Calc I see some settings under CAD_Bus_Block, not sure if those are important if they are in my bios I see CAD bus timing config and stuff like addrcmdsetup and csoodstsetup and also Cad bus drive strength config then clkdrvstern addrcmddrvstern, not sure which to choose or change if any?


----------



## blodflekk

The_King said:


> With Micron RAM you get different speed grades. Older IC's don't perform the same has newer revised ones.
> 
> If your RAM stock XMP is 3600 16-20-20-20 then its likely that your RAM is not even stable @ 3800 with RCD 17.
> You would need something like 3800 16-21-21-21 or maybe 3800 16-22-22-22.
> 
> I would also try without WTRS/L 2/6 and run 4/8 or 5/10.


Yup, I second this, those secondary's are very tight. I'd also loosen the SD and DD's to 1-4-4-1-6-6 since you're on DR. Could also loosen tWRRD to 4


----------



## sxeneize

blodflekk said:


> Yup, I second this, those secondary's are very tight. I'd also loosen the SD and DD's to 1-4-4-1-6-6 since you're on DR. Could also loosen tWRRD to 4


I think DD's are only for different DIMMs on the same channel. So 4 sticks. I have 2x16gb.
Anyway the thing is, it doesn't POST if a set GDM off 2T or 1T, no matter how loose i set every timing.


----------



## blodflekk

sxeneize said:


> I think DD's are only for different DIMMs on the same channel. So 4 sticks. I have 2x16gb.
> Anyway the thing is, it doesn't POST if a set GDM off 2T or 1T, no matter how loose i set every timming.


How high have you tried to raise vDIMM ?


----------



## sxeneize

blodflekk said:


> How high have you tried to raise vDIMM ?


I tried 1.55v, 3600 and every timing at auto. CR 2T.


----------



## The_King

sxeneize said:


> I tried 1.55v, 3600 and every timing at auto. CR 2T.


Just thought of one more thing. If your ProcODT is setup on Auto try setting it manually and try a few different ones some higher some lower.
Else I think it maybe be a board or BIOS issue. Try to see if you run 3200 with GDM off 1T or 2T.



StevieRay2 said:


> With soc 1.1, vddp .95, vddgs 1.05 I can't boot into windows at 1900 fclk but I can at 1933 and 2000 but getting 15 kernel whea 20 errors in 1 minute, anyway to get rid of them?
> or I'm just not able to go to 1933, and maybe stick with 1800 then and tighten timings?
> 
> Also I'm following the DRAM Calc program with the fast setting, so far I have this, any settings I should change or lower?
> Also on the DRAM Calc I see some settings under CAD_Bus_Block, not sure if those are important if they are in my bios I see CAD bus timing config and stuff like addrcmdsetup and csoodstsetup and also Cad bus drive strength config then clkdrvstern addrcmddrvstern, not sure which to choose or change if any?


You have to increase your VSOC and IOD until the WHEA errors stop, This will differ from board to board and there is no set value that will work for everyone.
I need at least 1.2VSOC and 1.15V IOD to be WHEA free at 3933MT FCLK 1967. At 2000 FCLK you may need more or less depending on your board..


----------



## pakultra100

Hi all, I have been learning from this thread for the past few weeks. Thanks to many useful tips posted by forum members, after weeks of hard work and testing, I have been able to find some nice stable settings. I am happy to share my settings here so that they might become useful references to inspire more fellow overclockers. 




















Thank you all


----------



## blodflekk

pakultra100 said:


> Hi all, I have been learning from this thread for the past few weeks. Thanks to many useful tips posted by forum members, after weeks of hard work and testing, I have been able to find some nice stable settings. I am happy to share my settings here so that they might become useful references to inspire more fellow overclockers.
> 
> View attachment 2580756
> 
> 
> 
> View attachment 2580757
> 
> 
> Thank you all


Nice work! If I said one thing it would be that tFAW should be tRRDS*4 so should be 32. But also tRRDs, tRRDL should be able to go much lower 4 6 or 5 7


----------



## Imprezzion

Could 1usmus error 2-10-12 after ~2h of testing be temperature related? Got up to 54.4c there. I was testing GDM On 1T with pretty tight subtimings and 3800 14-16-16-28-256-1T @ 1.59v vDIMM. It went fine for an hour and a half so I went to bed and checked again this morning and saw it had those 3 errors at like 2h10m in. My coolers still haven't showed up yet so..


----------



## pakultra100

blodflekk said:


> Nice work! If I said one thing it would be that tFAW should be tRRDS*4 so should be 32. But also tRRDs, tRRDL should be able to go much lower 4 6 or 5 7


Thank you blodflekk for your advice. I have exhausted all possibilities of tighter timings. Setting anything tighter will lead to errors. Adding more voltages does not help. It seems that either my motherboard or my memory controller is already at the limit of what they are able to do. Wish I had bought a Unify X motherboard. A lesson learnt the hard way.


----------



## mongoled

Veii said:


> Busy with a lot of things, and AM5 now (not personal system)
> But not gone from OCN ~ just , absent a bit
> Welcome back mongoled 👋


No changes there  (being busy, hahahaa)

Hope you have been able to improve the employment/monies situation and thanks for the welcome message





Nighthog said:


> Is the VDD1.8 voltage issue verified and confirmed for real to be a issue on the MSI boards?
> 
> Really bad design decision then. I need to push above 2.000V on occasion for 2000+ FCLK on the Gigabyte Aorus Xtreme. I was wanting that same voltage range available on the MSI but it's not advised to even use 1.900V without potential failure of the board?
> The Xtreme board only starts to complain with the PWM & fan controller misbehaving @ 2.100v+.
> 
> VDD18 has even more effect when using BCLK to adjust FCLK. (needs more to alleviate issues)


Yup, many of us found that when pushing high FCLK and to not loose performance that this voltage was the key.



The_King said:


> I did a small test which always gives me the same results. In AIDA64 with AddrCmdSetup 56 VS Real 1T. This has always been the case from my previous testing as well with my Setup.
> 
> So not sure why AddrCmdSetup 56 has a bad rep. It can save you a lot of headache and many hours of TM5 cycles also saves a lot on electricity.
> 
> Real 1T after several runs the lowest I could get in AIDA64 52.5ns and L3 @ 10.7ns
> View attachment 2580173
> 
> 
> AddrCmdSetup 56 AIDA64 52.2ns same L3 @ 10.7ns Basically no difference nothing that most people would notice?
> View attachment 2580174


Nice to see others doing there own testing, though this angle has been convered a few times in this mega thread and the OPs conclusion is correct





Veii said:


> CPU 1.8v rail is used to power EEPROM
> 1.8v EEPROM can sustain spikes to 1.93v , or longer at 1.9v - but i don't want to recommend ever running past 1.86v on it
> 
> 2nd issue with 3.3v data rail & different EEPROM (typo) is a batch issue, it's not a global issue.
> This 1.8 rail design tho is a global design


I am missing some knowledge here.

The convo on "PLL 1.8v" was triggered by me seeing some instability with my 24/7 settings that had been thoroughly tested in the past and proven "stable". I dont see how this issue with the EEPROM being fed from from CPU 1.8v rail is going to effect stability. My understanding is that the EEPROM chips are dying by being fed higher voltages than 1.8v when we push this rail higher when going to +2000 mhz FCLK.

Can you tell us what the functions of the two EEPROM chips are ? I assumed one is for the UEFI, the other ??



Nighthog said:


> Yeah you need extra cooling at such voltages. But depending on kit you might have ~1.600V limit unless you do the VTT trick. They just start to throw errors from the voltage alone unless you push VTT low enough.


Ah ha, some information that was not about around a year ago, please tell, what is this VTT trick ??

On a different note, I see some things never change, peeps asking Veii for unconditional help

😅

@Veii hopefully you found a means for peeps to voluntarily push some monies to you for your fantastic support ..


----------



## Nighthog

mongoled said:


> No changes there  (being busy, hahahaa)
> 
> Hope you have been able to improve the employment/monies situation and thanks for the welcome message
> 
> 
> 
> 
> Yup, many of us found that when pushing high FCLK and to not loose performance that this voltage was the key.
> 
> 
> Nice to see others doing there own testing, though this angle has been convered a few times in this mega thread and the OPs conclusion is correct
> 
> 
> 
> 
> I am missing some knowledge here.
> 
> The convo on "PLL 1.8v" was triggered by me seeing some instability with my 24/7 settings that had been thoroughly tested in the past and proven "stable". I dont see how this issue with the EEPROM being fed from from CPU 1.8v rail is going to effect stability. My understanding is that the EEPROM chips are dying by being fed higher voltages than 1.8v when we push this rail higher when going to +2000 mhz FCLK.
> 
> Can you tell us what the functions of the two EEPROM chips are ? I assumed one is for the UEFI, the other ??
> 
> 
> 
> Ah ha, some information that was not about around a year ago, please tell, what is this VTT trick ??
> 
> On a different note, I see some things never change, peeps asking Veii for unconditional help
> 
> 😅
> 
> @Veii hopefully you found a means for peeps to voluntarily push some monies to you for your fantastic support ..


The VTT trick is, MEM VTT. That half voltage of DRAM.
I found out my Ballistic Micron Rev.E kits are sensitive to it. (not my worse Kingston kits though)
Keep and lock the voltage to 0.600-0.750V range and you can push much more voltage on these kits without issue if you do this on the MSI X570S UNIFY-X.
Allowing you to push your timings a lot better. If you don't do this on the Ballistix you are limited to around 1.600V maximum or you get pcb/memory crashes&errors.
This only works on my MSI motherboard. The Gigabyte board has a offset setting which doesn't actually allow me to put this voltage this low and has different behaviour overall with this that doesn't work out. But does wonders on the MSI board.
The MSI Unify-X even has per channel setting for this so you can tune each stick individually. But never tested it out like that.
Just saw that if I set it to 0.600-0.700 I suddenly no longer had issues with the Ballistix kits when using high voltage.

EDIT: Could be MEM VFREF... I recall there being some issues with mislabelling with the voltage from BIOS Versus Windows applications.


----------



## Mikel_Ertz

Passed anta777 absoult, but got 1 WHEA while the 22h test. Is this a real whea? since in the text put that the hardaware error is corrected


----------



## mongoled

Nighthog said:


> The VTT trick is, MEM VTT. That half voltage of DRAM.
> I found out my Ballistic Micron Rev.E kits are sensitive to it. (not my worse Kingston kits though)
> Keep and lock the voltage to 0.600-0.750V range and you can push much more voltage on these kits without issue if you do this on the MSI X570S UNIFY-X.
> Allowing you to push your timings a lot better. If you don't do this on the Ballistix you are limited to around 1.600V maximum or you get pcb/memory crashes&errors.
> This only works on my MSI motherboard. The Gigabyte board has a offset setting which doesn't actually allow me to put this voltage this low and has different behaviour overall with this that doesn't work out. But does wonders on the MSI board.
> The MSI Unify-X even has per channel setting for this so you can tune each stick individually. But never tested it out like that.
> Just saw that if I set it to 0.600-0.700 I suddenly no longer had issues with the Ballistix kits when using high voltage.
> 
> EDIT: Could be MEM VFREF... I recall there being some issues with mislabelling with the voltage from BIOS Versus Windows applications.


Ah OK, as I played with these settings extensively on my B-die kits and came to the conclusion that it did not help with anything. Good to see that it helped different ICs


----------



## Veii

mongoled said:


> Hope you have been able to improve the employment/monies situation and thanks for the welcome message


ahh...no 
Still have my big build i'm working on - but after that, no 
There is no place for uneducated researcher like me, except staying freelancer
Also not interested in Europe's location hence no active focus on "paper certification" for things i already know. They are not useful to me outside of europe

Zen 4 is tempting, supposedly it fixes Thunderbolt Audio too ~ which i'll verify but i dont trust it
Matisse didn't have the problem with UniversalAudio, Vermeer was faster and completely unstable.
Now on Raphael AMD supposedly works on it ?? If it runs, i guess i have to sell my system , but we'll see.
I'd like to move away from text content if possible.


mongoled said:


> I dont see how this issue with the EEPROM being fed from from CPU 1.8v rail is going to effect stability. My understanding is that the EEPROM chips are dying by being fed higher voltages than 1.8v when we push this rail higher when going to +2000 mhz FCLK.
> 
> Can you tell us what the functions of the two EEPROM chips are ? I assumed one is for the UEFI, the other ??


Friends board was dead, hence we concluded some research.
Based on schematics, the unifies are fed directly - and very likely that's the key issue of them dying.
There are two issues of one that is simply internal error, misslabling rom chips and using 3.3v datarail for them. Death-chance of each flash increases exponentially.

But the main issue is connected to CPU 1P8. It was just on topic to warn ~ as that issue is not told.
it wouldn't even be as bad if MSI would be more...repair friendly, as they keep accepting the RMA's. But not even with NDA they wanted to share it.
Soo best i can do , is warn people to not run it higher than 1.86v.
There's some loss by the distance, soo between 1.83-1.86 should be perfectly fine. It should survive 1.9 too, but i dont know "how many years"

X570S unify has just a bios switch on it, hence two EEPROM's
But both received constant current from 1P8 plane. It's not "one or the other"


----------



## mongoled

Veii said:


> ahh...no
> Still have my big build i'm working on - but after that, no
> There is no place for uneducated researcher like me.
> Also not interested in Europe's location hence no active focus on "paper certification" for things i already know. They are not useful to me outside of europe


Oh that is a shame, education can be garnered, finding someone who works hard and diligently while not having in the forefront what they will be paid is a very rare occurrence, was hoping that some manufacturer would have discovered the "gem" that you are and offered you some employment. I am sure one day such a thing will occur for you





Veii said:


> Zen 4 is tempting, supposedly it fixes Thunderbolt Audio too ~ which i'll verify
> Matisse didn't have the problem with UniversalAudio, Vermeer was faster and completely unstable.
> Now on Raphael AMD supposedly works on it ?? If it runs, i guess i have to sell my system , but we'll see.
> I'd like to move away from text content if possible.
> 
> Friends board was dead, hence we concluded some research.
> Based on schematics, the unifies are fed directly - and very likely that's the key issue of them dying.
> There are two issues of one that is simply internal error, misslabling rom chips and using 3.3v datarail for them. Death-chance of each flash increases exponentially.
> But the main issue is connected to CPU 1P8. It was just on topic to warn ~ as that issue is not told.
> it wouldn't even be as bad if MSI would be more...repair friendly, as they keep accepting the RMA's. But not even with NDA they wanted to share it.
> Soo best i can do , is warn people to not run it higher than 1.86v.
> There's some loss by the distance, soo between 1.83-1.86 should be perfectly fine. It should survive 1.9 too, but i dont know "how many years"
> 
> X570S unify has just a bios switch on it, hence two EEPROM's
> But both received constant current from 1P8 plane. It's not "one or the other"


Interesting regards the EEPROM chips, still not clear why some use 3.3v rail and others CPU 1P8, but nevermind, its not going to help me get my prior settings stable.

Talking of which, I think ive pinpointed the "issue", still testing, but it seems that when running either/or low trfc i.e. lower than 240 when running 3800 mhz and/or tCL 13 when running 3800 mhz is effected by either ClkDrvStrength or CsOdtDrvStrength.

Previously "stable" settings I was using
ClkDrvStrength: 40 ohms
CsOdtDrvStrength: 30 ohms

After setting these to
ClkDrvStrength: 24 ohms
CsOdtDrvStrength: 24 ohms

I got two runs of Y-Cruncher VST test to pass, the first run was for over 40 cycles without failing, i then rebooted and ran VST test again and stopped it on 20 cycles.

Ive now set these settings to,

ClkDrvStrength: 40 ohms
CsOdtDrvStrength: 24 ohms

to see if I can narrow down which one is responsible for the instability (currently on the 10th cycle)

For a full picture see attached ZenTimings screen grab

Next step will be to set tRFC: 224, tRFC2:166 and tRFC4:102


----------



## RackarN

Found another rabbit hole to visit.. probably leads to disappointment, but I'm curious to see if there is a difference in gaming with the x3d.


----------



## Mikel_Ertz

Mikel_Ertz said:


> Passed anta777 absoult, but got 1 WHEA while the 22h test. Is this a real whea? since in the text put that the hardaware error is corrected


How much SOC and IOD should i put to fix the WHEA


----------



## mongoled

Whats with all the "GDM enabled" results im seeing in this thread ?



Has something changed since I was last tweaking?

Why be "blind folded" by using GDM set to enabled ??


----------



## Blameless

Veii said:


> But the main issue is connected to CPU 1P8. It was just on topic to warn ~ as that issue is not told.
> it wouldn't even be as bad if MSI would be more...repair friendly, as they keep accepting the RMA's. But not even with NDA they wanted to share it.
> Soo best i can do , is warn people to not run it higher than 1.86v.
> There's some loss by the distance, soo between 1.83-1.86 should be perfectly fine. It should survive 1.9 too, but i dont know "how many years"


Any other boards known to do this, or is it an MSI specific issue?

Are there any side effects for the EEPROM from running the 1.8v too low? Both of my 5800X3Ds are fine down to sub 1.7v as far as I can tell, but I can certainly use higher if there is a chance it will cause firmware issues.



mongoled said:


> Has something changed since I was last tweaking?
> 
> Why be "blind folded" by using GDM set to enabled ??


With Samsung stuff GMD is usually a bad idea, but all of my Hynix memory clocks so much higher or tightens up so much better with GDM enabled that disabling it is almost invariably slower.


----------



## Veii

Blameless said:


> Are there any side effects for the EEPROM from running the 1.8v too low? Both of my 5800X3Ds are fine down to sub 1.7v as far as I can tell, but I can certainly use higher if there is a chance it will cause firmware issues.


From the logical side, it should "just not boot" at all.
Nothing i know - or can guaranteed speak off. Just know schematics of one series , well 3 boards.

I asked to investigate AM5 Tomahawk , if they stopped with this idea
But it's all i know, sorry 
If there is more "public" data to share, GN would know~
I really don't want to put them on fire, but this is ... cost saving on the wrong place.
It's ok for 99% of the users too, we overclockers just need to be cautious

Only Unifies so far - can be common MSI practice but i don't know.
They had couple complications in the engineers side to what i can note. Nobody just "mistakes a 3.3v chip with a 1.8v one" ~ although realistically possible by one letter missing.
Probably the same mistake or costsaving that was done to the CH431, same issue (5v data rail on 3.3v VCC ~ 2ndary issue // here 3.3v data rail, but that was a one off)
That tho is more of a guess why such mistake happens in the production chain

The 1P8 plane issue remains a mainstream one, and there was no new revision of the board to be seen.
It appears an accepted tradeoff (PCB space or engineers cost) hence it kept being used on the X570S too ~ not only B550 and X570
EEPROM itself should hold 1.92v spikes - and the Bios limit is set to 1.95. There is some distance loss after all.
But i would personally not recommend anything over 1.86v max. 1.86v was also perfectly fine for my ASRock ITX ~ soo that should be a good OC tradeoff 
I dont know how long it can survive with constant strain at 1.9v.


----------



## mongoled

Blameless said:


> With Samsung stuff GMD is usually a bad idea, but all of my Hynix memory clocks so much higher or tightens up so much better with GDM enabled that disabling it is almost invariably slower.


OK, knew there must be some reason, shame we dont have a tool to show all memory timings so a comparison can at least be made to show what the effect GDM is having on these "hidden" variables, ive only ever clocked b-die on this platform so was not aware of the "perculiarities" of Hynix memory.



Re my VST "issue", seems like CsOdtDrvStrength from 30 to 24 ohms is now allowing VST test to loop without failure, I let it run for 30+ cycles and no failure. Have now dialled back in the tRFC settings mentioned above and am hammering the VST test again.

Hopefully dont get any failures then will proceed to some TM5 runs and then full Y-Cruncher suite to make sure its all stable


----------



## The_King

The_King said:


> Got my second Patriot Viper 4000 C19 kit to do 1T as well.
> @Veii WTRS/L 4/8 is much more stable than 3/8.  Any idea why this kit needed ClkDrvStr 60 vs 24 on the other one?


After having a look the the RAM chip layout on my Patriot Viper kits I may have a theory why the 4000 C19 need ClkDrvStr 60 vs the 4133 C19 24.
Using a flashlight I was able to clearly see the RAM chips and it turns out the 4133 C19 is A0 layout the chips are evenly spaced out on the DIMM.

With both the 4000/4400 C19s kits the layout is A2. 4 chips closely together on either end of the PCB. Just a theory for now but was interesting so I thought I would share.


----------



## sxeneize

The_King said:


> Just thought of one more thing. If your ProcODT is setup on Auto try setting it manually and try a few different ones some higher some lower.
> Else I think it maybe be a board or BIOS issue. Try to see if you run 3200 with GDM off 1T or 2T.


I tried different ProcODT, nothing. But, it works at 3200 2T..


----------



## Veii

The_King said:


> After having a look the the RAM chip layout on my Patriot Viper kits I may have a theory why the 4000 C19 need ClkDrvStr 60 vs the 4133 C19 24.
> Using a flashlight I was able to clearly see the RAM chips and it turns out the 4133 C19 is A0 layout the chips are evenly spaced out on the DIMM.
> 
> With both the 4000/4400 C19s kits the layout is A2. 4 chips closely together on either end of the PCB. Just a theory for now but was interesting so I thought I would share.


New Vipers 4000 & 4400 are A2s
Old vipers 4000 and 4133 were A0 - but 4133 sometimes were Hynix-CJR not B-Dies
4000 was always A2, but new revisions have a newer more funniky PCB

@Bloax has first hand experience


----------



## mongoled

This passed 25+ cycles Y-Cruncher VST test, so the culprit was CsOdtDrvStrength, lowering it to 24 from 30 without changing any other setting allow this test to pass when looped consecutively











So for general rule of thumb, considering that VST is an AVX float computational load, CsOdtDrvStrength when pushing high mem frequency in combination with low tCL (13) and/or low tRFC (240 and below) is very sensitive to this test.


That I had passed many hours of stress testing with CsOdtDrvStrength set to 30 shows that even the most subtle change when pushing to the edges of stability can make a big difference


----------



## Veii

@mongoled can you tripple check presets
40-20-30-24
40-20-40-20
and
60-20-30-24

I wonder if lack of CkeDrvStr is causing you issues
Because if we speak about "high timings" , my 4200 15-15 set is equal to 13-13 3800, very close to it
so is also the 4600 17-17 one
// absolutely not trying to lower the worth of your top ! 4 dimms result

You run quite some VDIMM - lovely 
Soo you might also want to check if RTT_PARK /5 out of nowhere resolves those CAD_BUS issues

EDIT:
CsOdtDrv was only needed to be pushed beyond 24 ~ because of buggy memory training
Matisse was always on 24 too, but it didn't work here
Maybe who knows benefit is low proc - i wonder


----------



## The_King

sxeneize said:


> I tried different ProcODT, nothing. But, it works at 3200 2T..


Would you mind posting a screenshot of the Thaiphooner burner read out for your DIMMS.
I have a 3600 CL16-18-18-38-58 Kit with these ICs. I want to see what ICs are on your DIMMS.
The screenshot should look like this.


----------



## mongoled

Veii said:


> @mongoled can you tripple check presets
> 40-20-30-24
> 40-20-40-20
> and
> 60-20-30-24
> 
> I wonder if lack of CkeDrvStr is causing you issues
> Because if we speak about "high timings" , my 4200 15-15 set is equal to 13-13 3800, very close to it
> so is also the 4600 17-17 one
> 
> You run quite some VDIMM - lovely
> Soo you might also want to check if RTT_PARK /5 out of nowhere resolves those CAD_BUS issues
> 
> EDIT:
> CsOdtDrv was only needed to be pushed beyond 24 ~ because of buggy memory training
> Matisse was always on 24 too, but it didn't work here
> Maybe who knows benefit is low proc - i wonder


Currently running a TM5, those should be quick and easy to test as when using 40-20-30-20 it would error out within 10 cycles sometimes not even making it to two cycles.

I may re-visit high FCLK on this new agesa, I have previewed in the past "stable" 4133-2067-16-16-16-16-32-48-288-2T benchmarks, but did not use these as 24/7 settings due to the issue with cold/warm reboots, whea warnings and having the need to run high CPU PLL voltage to combat loss in performance when running Linpack Xtreme...

Re high vdimm for those reading this, ive been running this voltage for probably something close to a year now (Viper A2s), no issues so far apart from the VST issue, though my dimms are watercooled which for sure is assisting with the high voltages along with low ProcODT and RTT settings.



4133-2067-16-16-16-16-32-48-288-2T (agesa 1.2.0.3c)


----------



## Imprezzion

RackarN said:


> Found another rabbit hole to visit.. probably leads to disappointment, but I'm curious to see if there is a difference in gaming with the x3d.
> View attachment 2580785


Keep us posted, would like to know!
My B-Die will handle 4600 17-19-19 or 4800 18-20-20 just fine as tested before on a 10900K. So yeah. Curious!


----------



## ApT01

sxeneize said:


> Can't POST when i set GDM off 2T.
> Any ideas?


Try tRDWR=9, t=tWRRD=3


----------



## sxeneize

The_King said:


> Would you mind posting a screenshot of the Thaiphooner burner read out for your DIMMS.
> I have a 3600 CL16-18-18-38-58 Kit with these ICs. I want to see what ICs are on your DIMMS.
> The screenshot should look like this.


----------



## RackarN

Imprezzion said:


> Keep us posted, would like to know!
> My B-Die will handle 4600 17-19-19 or 4800 18-20-20 just fine as tested before on a 10900K. So yeah. Curious!


So this is 25 rounds stable..









This profile vs the 1900mhz 1.1.1 profile performs the same in Forza Horizon 5 and Modern warfare 2. Was 1-2 fps better 1% low so I'd say margin of error. (Tested 1080p)
Edit: just tested cyberpunk margin of error

Aida being Aida
1k lower read speed
1k higher write
4k higher copy
8ns more

25 rounds 1usmus
1h22m (old)
1h20m

Y-crunchers Pi multi test
104,762 (old)
102,813

Was mostly curious about games to see if the x3d scales better with faster ram .but it's rough testing everything xD in time maybe..


----------



## 99belle99

Anyone know why Taiphoon burner gives me a error at launch. The kernel mode driver is blocked. It used to work. All I can think of is I opened it with out opening with administrator privilege's. Would that cause it?


----------



## Bloax

99belle99 said:


> Anyone know why Taiphoon burner gives me a error at launch. The kernel mode driver is blocked. It used to work. All I can think of is I opened it with out opening with administrator privilege's. Would that cause it?


the most common source of kernel-mode driver blockage these days is the funny Valorant anti-cheet that doesn't actually prevent people from cheating, but gives them a nice excuse as to why they're Just Better.




Veii said:


> New Vipers 4000 & 4400 are A2s
> Old vipers 4000 and 4133 were A0 - but 4133 sometimes were Hynix-CJR not B-Dies
> 4000 was always A2, but new revisions have a newer more funniky PCB
> 
> @Bloax has first hand experience


4400C19 were always A2*

4000C16 are a better bin of the 4400C19 seemingly with some small under-the-PCB changes that make them not have a weird relationship with tCKE as the 4400's do:









The _new_ 4000C19 are now a bin-reject of the A2 4000C16 sticks, as opposed to the old 4000C19 which are A0, yes.


----------



## 99belle99

Bloax said:


> the most common source of kernel-mode driver blockage these days is the funny Valorant anti-cheet that doesn't actually prevent people from cheating, but gives them a nice excuse as to why they're Just Better.


Where would that come from? When you mention that I just remembered I installed EA and a few games like Battlefield 4. Would any of those have installed Valorant?


----------



## Imprezzion

Well, it seems to like this 1T GDM Enabled profile at least. 14-14-14 is impossible with these temps. Also, my DIMM's absolutely hate running tRCD, tRP = tCL. Always has to be minimum tCL +1 even on my old Intel setups. vDIMM = 1.5300v. Rest is visible in the screenshot 
The DIMM's are very early production date G.Skill Trident-Z Neo 3600C16D-32GTZN's that I have had for almost 3 years now since they released back in '19 and I got them for Christmas for my 9900K back then.


----------



## sxeneize

99belle99 said:


> Anyone know why Taiphoon burner gives me a error at launch. The kernel mode driver is blocked. It used to work. All I can think of is I opened it with out opening with administrator privilege's. Would that cause it?


Which version of windows you have? I was getting same error on win 11 22621.755.


----------



## 99belle99

sxeneize said:


> Which version of windows you have? I was getting same error on win 11 22621.755.


I'm on the same.


----------



## sxeneize

99belle99 said:


> I'm on the same.


I think that's the problem. I tried on my laptop just before that update and it was working, 15 minutes later it wasn't.
I ended up using windows to go on a pendrive, previous version (.iso from ms website).


----------



## StevieRay2

Question for the knowledgeable, how important are these settings in DRAMCalc for performance/latency or can I keep them on Auto if my current oc/timings is stable?

And do you see any timings on my Hynix CJR/DJR I can improve on?


----------



## Imprezzion

StevieRay2 said:


> Question for the knowledgeable, how important are these settings in DRAMCalc for performance/latency or can I keep them on Auto if my current oc/timings is stable?
> 
> And do you see any timings on my Hynix CJR/DJR I can improve on?


Your tRC could go lower and maybe SCL's on 4 not 5? Not much else I can find. Do you need 20 RCD and 21 tRP? It sounds high for 3733 even for Hynix.


----------



## StevieRay2

Imprezzion said:


> Your tRC could go lower and maybe SCL's on 4 not 5? Not much else I can find. Do you need 20 RCD and 21 tRP? It sounds high for 3733 even for Hynix.


I don't have much experience with RAM OC, these timings are just taken from DRAMCalc that's probably not so great but it's a start for me just no idea where to go from here tightening up stuff a bit .


----------



## Imprezzion

StevieRay2 said:


> I don't have much experience with RAM OC, these timings are just taken from DRAMCalc that's probably not so great but it's a start for me just no idea where to go from here tightening up stuff a bit .


Try 19 on both tRCD and tRP (or maybe even 18) and tRC on 55 (or 54 if 18) and both SCL on 4.


----------



## StevieRay2

Imprezzion said:


> Try 19 on both tRCD and tRP (or maybe even 18) and tRC on 55 (or 54 if 18) and both SCL on 4.


Thanks I'll try that out, what do you suggest is a good way to test it? Right now I've been doing 1000% HCI memtest, 3 cycles of TM5(absolut) might be overkill testing timings?

Edit: seems trcd/trp 18 trc 54 gave me a bsod before logging in, 19 19 55 scl 4 4 seemed to give me odd behaviour Windows issues like web browsers freezing and not loading pages etc maybe 1.37v is too low or something else?
Am I able to test these setting independently or do they somehow go hand in hand? Like can I try the 19 if that tests good then try 19 19 then trc 55 etc one at a time?


----------



## The_King

Bloax said:


> The _new_ 4000C19 are now a bin-reject of the A2 4000C16 sticks, as opposed to the old 4000C19 which are A0, yes.


From the 4 X 4000 C19s I have only 1 show the import date has 01/22 (Jan 2022) the rest are from 2021. Its the only one that does 3800 14-14-14.
Speed grade for the Patriot 4000 CL16 is 2666V all the other Patriot Vipers are rated 2133p-downbin.

So is it possible that Thaiphoon burner is reading the speed grade of the new 4000 C19s incorrectly? Or is the speed grade dropped to 2133p-downbin because its a bin-reject?


----------



## RackarN

This is probably known to people but i just might help 1 person.
So during my testing of higher FCLK i noticed score was dropping, but i had no errors.. redid some tests and it would be lower, even if FCLK was higher. So to me it rings a bell that something doesn't get enough power.

Went to bios and set IOD voltage up by 0.02 and there was a big difference already!


----------



## The_King

RackarN said:


> This is probably known to people but i just might help 1 person.
> So during my testing of higher FCLK i noticed score was dropping, but i had no errors.. redid some tests and it would be lower, even if FCLK was higher. So to me it rings a bell that something doesn't get enough power.
> 
> Went to bios and set IOD voltage up by 0.02 and there was a big difference already!


Yes this is already well known in this thread. At 3933MT I am WHEA free with just 1.1V IOD but Multi Thread performance is terrible.
Increasing IOD to 1.15V then it performs way better.

You reach a point were if you go over 2000 FCLK no amount of IOD helps and then you may need to adjust VDD18 to prevent performance drops. But that can be dangerous on some boards.


----------



## The_King

@Veii Error #2 Rttpark 6 vs 7.
Still not conclusive has these one of single errors can appear randomly but hey it worked I guess.


----------



## rjatlsj

reantum said:


> DIMM voltage?


Srry for late
4000 cl14 trcdrd15 is 1.55v trfc 252
4000 cl14 trcdrd14 is 1.56v trfc 240
All real 2t


----------



## Mikel_Ertz

Plz help, tested again my ram, stable but got 1 WHEA. What voltages should i use plz help me


----------



## RackarN

Mikel_Ertz said:


> Plz help, tested again my ram, stable but got 1 WHEA. What voltages should i use plz help me


could it be fclk related?


----------



## Mikel_Ertz

RackarN said:


> could it be fclk related?


It's yes. That's why i need voltages recomendations

I am running stock cpu (fclk 1900mhz) and stock gpu


----------



## RackarN

Mikel_Ertz said:


> It's yes. That's why i need voltages recomendations
> 
> I am running stock cpu (fclk 1900mhz) and stock gpu


The CCD could need a bump. try 1.05, you could try giving SOC a bump 1.15 after or do both right away. Nothing is certain when it comes to WHEAs.
I feel like its kinda random with WHEA, sometimes it needs a bump in voltage, some times lowered. In your case it might be a small bump. Sometimes there is nothing more to do really.


----------



## Mikel_Ertz

RackarN said:


> The CCD could need a bump. try 1.05, you could try giving SOC a bump 1.15 after or do both right away. Nothing is certain when it comes to WHEAs.
> I feel like its kinda random with WHEA, sometimes it needs a bump in voltage, some times lowered. In your case it might be a small bump. Sometimes there is nothing more to do really.


Thanks, I'll try it. Most likely, it's about to get stable. I only have 1 WHEA in 22-23h of tests


----------



## RackarN

Mikel_Ertz said:


> Thanks, I'll try it. Most likely, it's about to get stable. I only have 1 WHEA in 22-23h of tests


Yeah, it could also be (most likley) a false positive.


----------



## StevieRay2

A few quick questions for anyone that knows:
1. ProcOCT I had it at 36 but see most people using 60, so I tried 60, any pros or cons against either if I tried both and both pass stress tests?
2. I see a lot of people disabling RttNom, RttWr too any cons against it off if I don't see a difference?
3. RttPark I see peoples saying RZQ/5 etc, mine says 1 but in the Bios I only see ohm like 30 50 whatever, which is 5? and does that matter?
Thanks


----------



## Veii

The_King said:


> @Veii Error #2 Rttpark 6 vs 7.
> Still not conclusive has these one of single errors can appear randomly but hey it worked I guess.
> View attachment 2580988
> View attachment 2580989


Fully correct
Drop RTT_PARK , resolves #2 
It's not only that, as it is a "powering issue"
but it is one of them, thank you for confirming as 3rd
This is enough to write it down as a rule


----------



## RackarN

StevieRay2 said:


> A few quick questions for anyone that knows:
> 1. ProcOCT I had it at 36 but see most people using 60, so I tried 60, any pros or cons against either if I tried both and both pass stress tests?
> 2. I see a lot of people disabling RttNom, RttWr too any cons against it off if I don't see a difference?
> 3. RttPark I see peoples saying RZQ/5 etc, mine says 1 but in the Bios I only see ohm like 30 50 whatever, which is 5? and does that matter?
> Thanks


For me i had to use RTTs trying to tweak some timings, never wrote it down tho. I use lower Proc in lower speeds it seems, usually if the PC won't boot and i get a post error i can try adding proc, that's the only one I know how i handle from the top of my head.

All the above: to high will give errors , too low will give errors. The tighter the timings, the closer you have to be to the correct RTT, procODT value in my testing.

Using 1usmus TM5 profile then looking at the error code "cheat sheet" can help figuring out if the errors is asking for more volt/less resistens.


----------



## StevieRay2

RackarN said:


> For me i had to use RTTs trying to tweak some timings, never wrote it down tho. I use lower Proc in lower speeds it seems, usually if the PC won't boot and i get a post error i can try adding proc, that's the only one I know how i handle from the top of my head.
> 
> All the above: to high will give errors , too low will give errors. The tighter the timings, the closer you have to be to the correct RTT, procODT value in my testing.
> 
> Using 1usmus TM5 profile then looking at the error code "cheat sheet" can help figuring out if the errors is asking for more volt/less resistens.


Thanks, so those 3 settings are pretty much for stability and would be obvious if too high or low? WHEA errors, crashes, failing stress tests etc? Just looking at a bunch of the Google Doc of peoples RAM OC and see a lot of people just turning off the second 2 settings so I guess if you're stable you don't need it and it won't affect anything while off?


----------



## RackarN

Failing tests mostly, those errors can probably produce wheas aswell


----------



## StevieRay2

Thanks, question regarding TestMem5, 
using it with the Absolut file, with everything closed it seems to be using a lot of my c drive, so it's using my virtual memory? I can't seem to find an option for it to use less, I have 32G not sure where to find or set it to only use my actual RAM


----------



## Imprezzion

I don't understand.. i keep getting random driver and game crashes when running 3933 / 1966 1:1. It passed full 50 overnight cycles of TM5 1usmus, it passed Cinebench R23 looped, it had no WHEA's kr memory errors yet I can't play even half an hour of games before either the game crashes or the nVidia drivers do. On 3800/1900 it's completely fine.. 

What can this be.. am I lacking a voltage somewhere or? I'm running 1.21375 vSOC, 1.120 CCD 1.070 IOD, 0.940 CLDO VDDP.


----------



## RackarN

Just for ease of mind you could keep the FCLK high and clock the memory down just to see if it's FCLK issue rather than Memory, to rule one out of the equation


----------



## StevieRay2

Since testing out my new RAM timings stress tests all pass and gaming seems fine but sometimes web browsers just fail to load pages then finally do after 1-2 minutes, I've never seen this happen before testing RAM, is that some sort of voltage issue or? Never seen anything like that before. No WHEA errors either.


----------



## RackarN

Got GDM OFF and T1, needed 63 AddrCmdSetup tho.. CL down to 19... still have some autos i need to see if i can tighten.


----------



## StevieRay2

I'm at 1.20 VSOC and 1.15 IOD testing 1933 and 1967 FCLK alone(everything is stable in my pic I only raised FCLK to test it) but still getting WHEA errors, is it a lost cause for me trying to get WHEA free at these high FCLKs or is there some other setting I can raise too?


----------



## Imprezzion

StevieRay2 said:


> I'm at 1.20 VSOC and 1.15 IOD testing 1933 and 1967 FCLK alone(everything is stable in my pic I only raised FCLK to test it) but still getting WHEA errors, is it a lost cause for me trying to get WHEA free at these high FCLKs or is there some other setting I can raise too?
> View attachment 2581107


1.150 CCD, 1.25 vSOC. How many WHEA and how fast do they show up?


----------



## StevieRay2

Imprezzion said:


> 1.150 CCD, 1.25 vSOC. How many WHEA and how fast do they show up?


Pretty quick when I'm doing something like played a game for 5 minutes and there's 50-70 errors, I'll try and raise CCD too and see and also more vSOC
Edit: With those settings I still get a 5 WHEA errors every second in TestMem5

What are the max safe values of vSOC CCD IOD VDDP anyway?


----------



## Imprezzion

StevieRay2 said:


> Pretty quick when I'm doing something like played a game for 5 minutes and there's 50-70 errors, I'll try and raise CCD too and see and also more vSOC
> Edit: With those settings I still get a 5 WHEA errors every second in TestMem5
> 
> What are the max safe values of vSOC CCD IOD VDDP anyway?


Don't bother. No fixing that level of WHEA. That's why I asked. If it was 2-5 in like 10 minutes it might be doable but that is too much. Drop the FCLK. Max safe is unknown to me, I have always stuck to max 1.25 SA 1.15 CCD IOD. Anything above that, while maybe considered safe, loses the entire point of being power efficient. Just run 3800 memory 1900 FCLK.


----------



## StevieRay2

Imprezzion said:


> Don't bother. No fixing that level of WHEA. That's why I asked. If it was 2-5 in like 10 minutes it might be doable but that is too much. Drop the FCLK. Max safe is unknown to me, I have always stuck to max 1.25 SA 1.15 CCD IOD. Anything above that, while maybe considered safe, loses the entire point of being power efficient. Just run 3800 memory 1900 FCLK.


Yeah tried a series of different SOC CCD IOD and all WHEA errors, I'll stick with 1867(1900 is a hole for me, can't boot no matter what) and maybe tighten more settings than I have currently if possible


----------



## blodflekk

Imprezzion said:


> I don't understand.. i keep getting random driver and game crashes when running 3933 / 1966 1:1. It passed full 50 overnight cycles of TM5 1usmus, it passed Cinebench R23 looped, it had no WHEA's kr memory errors yet I can't play even half an hour of games before either the game crashes or the nVidia drivers do. On 3800/1900 it's completely fine..
> 
> What can this be.. am I lacking a voltage somewhere or? I'm running 1.21375 vSOC, 1.120 CCD 1.070 IOD, 0.940 CLDO VDDP.


I've had these issues too, easy to pass tm5 for 50+ cycles but crashes in games. I stopped using tm5 and went back to using HCI memtest and sure enough there were errors. 1000% HCI memtest has been then only thing that has guaranteed no crashes related to memory


----------



## The_King

In some of my posts you guys will see HWINFO64 open on the side to watch for Windows Hardware Errors (WHEA) Its a good idea to keep that open during the entire TM5 test.

This being said I have pointed out many pages back that passing TM5 25/50/100/200 cycles does not mean your entire system is stable. So after running TM5 you should probably run 1 hour of OCCT extreme variable to check for WHEA errors when the CPU is put under heavier MT and other loads which is something TM5 does not do.

I suspect in most of the cases IOD voltage is low for some others it can be VSOC need to be slightly higher. I recommend you first try with 1.15V IOD and see if its stable if you are running over 3933 with 1.2 VSOC.

Sometimes high VSOC can be the cause of errors with certain configs.

Lastly if you still having issues and can't resolve the stability issues refer to this post where I dropped from 3933/1966 to 3867/1933 and could do so with significantly less voltages and not much performance drop compared to 3933.









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


What screen/monitor do you have Freesync / Gsync? Does it have any power saving modes? Try resetting it to default using the Menu option on your screen if you have that feature. It's best to use DDU to remove all GPU drivers before installing a new card. Also did you leave the AMD drivers on...




www.overclock.net


----------



## RackarN

@The_King so the timings i posted above with T1 ran 25 rounds stable, no issues. Today i was gonna try tightening some timings but it gave errors. I rebooted to bios to load old profile but now it won't even boot 🤦🏼‍♂️ tried procODT, rtt's, GDM on T2 but it won't 🤷🏼‍♂️ any ideas?


----------



## The_King

RackarN said:


> @The_King so the timings i posted above with T1 ran 25 rounds stable, no issues. Today i was gonna try tightening some timings but it gave errors. I rebooted to bios to load old profile but now it won't even boot 🤦🏼‍♂️ tried rtt's GDM on T2 but it won't 🤷🏼‍♂️ any ideas?


I see this happen sometimes when ProcODT is not set in the BIOS but left on AUTO. Try setting most values than leaving it on AUTO which can cause failed post or training issues.

You can also try to restore defaults in BIOS then reboot and then load the saved profile and try again.


----------



## RackarN

Just set everything as the screenshot but no post 🤦🏼‍♂️
Gonna try default and then load it again. Trcpage I'm nog sure of tho, think it was 0 before








Edit: got in, 7.3.3 RTT, change to drvStr and then 63 on all 3 setups.. last ones i feel like I need to check after if it's needed.

Edit; nope, error spams

Edit: cl20 seems fine (nope)


----------



## Nighthog

RackarN said:


> Just set everything as the screenshot but no post 🤦🏼‍♂️
> Gonna try default and then load it again. Trcpage I'm nog sure of tho, think it was 0 before
> View attachment 2581199
> 
> Edit: got in, 7.3.3 RTT, change to drvStr and then 63 on all 3 setups.. last ones i feel like I need to check after if it's needed.
> 
> Edit; nope, error spams
> 
> Edit: cl20 seems fine (nope)


you have your setup timings kinda suspect. use 0 0 0.


----------



## RackarN

Nighthog said:


> you have your setup timings kinda suspect. use 0 0 0.


Won't boot :/ so odd, nothing is on auto, exact same setup as last evening when I passed 25 rounds 1usmus


----------



## Nighthog

Imprezzion said:


> I don't understand.. i keep getting random driver and game crashes when running 3933 / 1966 1:1. It passed full 50 overnight cycles of TM5 1usmus, it passed Cinebench R23 looped, it had no WHEA's kr memory errors yet I can't play even half an hour of games before either the game crashes or the nVidia drivers do. On 3800/1900 it's completely fine..
> 
> What can this be.. am I lacking a voltage somewhere or? I'm running 1.21375 vSOC, 1.120 CCD 1.070 IOD, 0.940 CLDO VDDP.


Might just be starving overall on the voltages.
I find Y-cruncher and Prime95 usually solves issues to show lack of voltage or show instabilities so your system doesn't crash in games.
You could try CPU VDDP voltage. I often saw I needed a ~100mv boost when going above 2000FLCK.
Could be you need a CO tuning if some core becomes unstable at the frequency you try to run.
Sometimes some cores just fail with too high a FCLK without extra tuning.


----------



## Nighthog

RackarN said:


> Won't boot :/ so odd, nothing is on auto, exact same setup as last evening when I passed 25 rounds 1usmus


Something didn't train right or your system was hot and warm with the working settings but they fail cold.

When you reach higher memory frequency you encounter these erratic behaviours more often. You need to find the culprit setting that is failing and try to work around it usually.
Either a voltage is wrong etc or a setting just needs several retries to train correctly for boot. (I could try 10-20times to train 5200Mts for it to boot then have it work stable before I found settings that are more reliable to boot)

There is so much to test you just have to go back to find what worked previously or go back one frequency step as it might be needing to boot first @ 4600Mts or something before it can train 4800+
As you find the settings your motherboard,cpu & memory like more and more you can keep pushing it further and further. You learn the quirks of behaviours and how to work around the issues by for example training at a lower frequency before you train the higher speed. As it can fail to train the higher speed on first try.


----------



## The_King

RackarN said:


> Won't boot :/ so odd, nothing is on auto, exact same setup as last evening when I passed 25 rounds 1usmus


Have you tried with the bclk overclock disabled? It looks like you overclocked your BCLK abit that can also cause lots of random stability issues.


----------



## RackarN

Yeah same. I loaded same profile again, pulled memory down 2 steps and it boots without issues. Testing stability now, random 12 error thus far.

Guess it was close to stable but not quite there.

Edit: after the error i just booted to bios and put 0 0 0 for the setups, no errors, round 3.

Thx for the help guys!


----------



## Imprezzion

I am still having a lot of trouble getting it to either run 1T GDM Off or anything other then Auto for ProcODT, RTT and DrvStr's.. just the basic manual stuff like 36.9 ODT 7-3-3/6-3-3 and 40-24-30-20 just doesn't even attempt to POST and if it does it's incredibly unstable at any frequency.. my 5900X was much easier then this 5800X3D is. That was just set 28.2 ODT, 6-3-3 RTT, 40-20-24-20 drv, 56 AddrCmdSetup and it just works. This takes much more tweaking. 

Can anyone maybe give me a basic setup for ProcODT, RTT, DrvStr's and VDDG/P/vSOC voltages for 3800/1900 14-15-15-30-45-256-1T or 2T GDM Off? I tried many different combinations out of your guy's screenshots and some worked sort of at least to get to Windows but not stable.. 

On everything Auto it's perfectly stable btw so the RAM and FCLK can do it just fine I just want to optimize the ODT/RTT and such.


----------



## RackarN

I was just lucky. Once i was stable i swapped GDM off, when stable i tried T1.

My DrvStr seems to want to be at 24, all of them.
Setups seems to want to be at 0 0 0
Odt 30 at 3800
Odt 43.6 at 4759.










Seems fine so far, early to say tho..

Edit: needed to bump ClkDrvStr to 30 since i got an error.


----------



## Imprezzion

So far this is the best I can at least boot. It gives an error #2 after 15 minutes and I have no clue how to fix it..


----------



## RackarN

Imprezzion said:


> So far this is the best I can at least boot. It gives an error #2 after 15 minutes and I have no clue how to fix it..
> 
> View attachment 2581232


Try ClkDrvStr to 30, it was error 2 for me aswell.

Edit: mine might have been error 1...

I think u should try rttPark /3 if the other one didn't do anything.










This is how i run it now. Stable again i suppose.. kinda hot after all the tests so they might need a fan..


----------



## StevieRay2

Little help this is what I have so far stable in HCI TM5 Y-Cruncher, anyone have suggestions what next I should try and lower or change if something looks odd? specifically settings that could lower my latency and/or gaming performance.
Hynix CJR RAM








Tried trcdrd and trp at 19 and it was a no go


----------



## RackarN

tRRD_ both 4 would give you a nice boost
tRTP half of twr


----------



## StevieRay2

RackarN said:


> tRRD_ both 4 would give you a nice boost
> tRTP half of twr


Thanks I'll try those, you mean my rtp I should try half of twr which is 10 so try trtp 5? I'll try that too
Edit: tried the TRRD's at 4, BSOD on login, not possible to run that or do I need to up something?


----------



## Imprezzion

Why do we all put tRCDWR on 8 btw. What is the goal of doing that. It's not a timing Intel uses right? And if I put it on DOCP it just matches the other primary timings at 16. What is the actual performance be edit of running 8 and is it something all RAM can do or?

I'm testing 3933 14-14-16-16-34-272-1T GDM On now and it requires at least 1.60v vDIMM to run tCL 14 but it works so far. Even at well over 53c so far. The rest of the timings are kept quite conservative just to make sure it isn't erroring out because some secondary is too tight for the frequency.


----------



## KingEngineRevUp

I'm moving from a 5900X to a 5800X3D. Is there anything I need to expect about my memory which I'm currently running 4 sticks at 3800 MHz CL16 GDM on?

How are Controllers for the 5800X3D? Does the cache cause it to be harder to OC? Etc.


----------



## Imprezzion

KingEngineRevUp said:


> I'm moving from a 5900X to a 5800X3D. Is there anything I need to expect about my memory which I'm currently running 4 sticks at 3800 MHz CL16 GDM on?
> 
> How are Controllers for the 5800X3D? Does the cache cause it to be harder to OC? Etc.


The cache doesn't make it harder to OC for FCLK or memory. I am giving myself a hard time by using a cheap-o B550 board with the signal integrity of a 1950's telephone wire during a category 4 hurricane and not testing enough. If anything a 5800X3D is better for FCLK/MCLK then a non B2 stepping 5900X.

EDIT: Just to test my CPU OC and to use as a backup super safe stable baseline BIOS profile for when I wanna just.. game on it for a bit I made this. 
It's just Auto CPU + DOCP 3600C16, 1.40v vDIMM, 0.950v CCD/IOD and I tweaked all secondary / tertiary timings to be pretty well optimized but not too tight. 
It defaults to 1T GDM On on Auto DOCP so yeah. Fine with me.


----------



## KingEngineRevUp

Imprezzion said:


> The cache doesn't make it harder to OC for FCLK or memory. I am giving myself a hard time by using a cheap-o B550 board with the signal integrity of a 1950's telephone wire during a category 4 hurricane and not testing enough. If anything a 5800X3D is better for FCLK/MCLK then a non B2 stepping 5900X.
> 
> EDIT: Just to test my CPU OC and to use as a backup super safe stable baseline BIOS profile for when I wanna just.. game on it for a bit I made this.
> It's just Auto CPU + DOCP 3600C16, 1.40v vDIMM, 0.950v CCD/IOD and I tweaked all secondary / tertiary timings to be pretty well optimized but not too tight.
> It defaults to 1T GDM On on Auto DOCP so yeah. Fine with me.
> View attachment 2581300


Do you think I can just reuse my settings for my 5900X?


----------



## NoLongerNeeded

Nvm


----------



## sxeneize

ApT01 said:


> Try tRDWR=9, t=tWRRD=3


That worked, thanks!
I tought setting at auto was loose enough but it wasn't. Auto was 9 and 2. 
It needs 9 and 3 to post. If i set 8 and 3 or 9 and 2 doesn't work.


----------



## StevieRay2

What OCCT config is the best to test RAM? I use Y-cruncher and all the tests in it but might as well throw in an OCCT test for an hour and two


----------



## SneakySloth

StevieRay2 said:


> What OCCT config is the best to test RAM? I use Y-cruncher and all the tests in it but might as well throw in an OCCT test for an hour and two


The free version of OCCT only allows an hour long test for each run. I've found the AVX2 test to find errors fairly quickly.


----------



## StevieRay2

SneakySloth said:


> The free version of OCCT only allows an hour long test for each run. I've found the AVX2 test to find errors fairly quickly.


First time using OCCT, so just Memory, select the amount of RAM, AVX2 and Threads Auto and that's it?


----------



## SneakySloth

Yes. Memory test with 95% coverage, AVX2 and auto threads.


----------



## byDenoso

I Need some help here.
What should i do next??


----------



## mongoled

mongoled said:


> So for general rule of thumb, considering that VST is an AVX float computational load, CsOdtDrvStrength when pushing high mem frequency in combination with low tCL (13) and/or low tRFC (240 and below) is very sensitive to this test.
> 
> 
> That I had passed many hours of stress testing with CsOdtDrvStrength set to 30 shows that even the most subtle change when pushing to the edges of stability can make a big difference


Guys, sorry for the misinformation.

Its looking like another one of those issue caused by something unrelated.

Latest testing is showing that the issue may be caused by the "*Power Supply Idle Control"* setting.

I had this setting on "AUTO" it shouldnt be on "AUTO" as I remebered in the past that all my configs were set to "Typical" after having seen issues with it.

Somehow, these settings were not being applied with the import of config (on prior agesa), on this new agesa (1.2.0.7) I had forgotten that I need to set this value.

Since setting this value to "Typical" I have not had a failure of VST test in over 3 different tests, first test was over 30 cycles, second test was over 144 cycles (yes, fell asleep while testing) and third test is currently at 24 cycles.

Im still not definately sure this is the reason for my previous stable settings failing, but its looking more and more likely.

Hopefully with have this cleared up by the end of today


----------



## mongoled

byDenoso said:


> View attachment 2581386
> 
> 
> I Need some help here.
> What should i do next??


If you dont specifically state what help you need, for example, what are your aims while overclocking your RAM, then you are not helping people who may want to help you as they dont know what you want help for !


----------



## mongoled

Just did a quick test comparing agesa 1.2.0.3c and 1.2.0.7 with regards to whea/performance/cold-warm boot/audio glitches when running 4133/2067 and nothing much has changed.

Still whea warnings, still slight performance loss (due to increased VSOC voltage) in LinpackXtreme, still occasionally not posting from warm/cold boot/reboot.

Shame, was hoping to see something changing for the positive ...


----------



## Nighthog

mongoled said:


> Just did a quick test comparing agesa 1.2.0.3c and 1.2.0.7 with regards to whea/performance/cold-warm boot/audio glitches when running 4133/2067 and nothing much has changed.
> 
> Still whea warnings, still slight performance loss (due to increased VSOC voltage) in LinpackXtreme, still occasionally not posting from warm/cold boot/reboot.
> 
> Shame, was hoping to see something changing for the positive ...


We should never hope for anything else other than new bugs not be introduced.


----------



## Veii

mongoled said:


> Im still not definately sure this is the reason for my previous stable settings failing, but its looking more and more likely.
> 
> Hopefully with have this cleared up by the end of today


Good to see CAD_BUS presets still going strong 


mongoled said:


> still occasionally not posting from warm/cold boot/reboot.


But that's CsOdtDrvStr 's part. More of it, fixes it. 30+ for my testing was always needed, unless SETUP timings were used


----------



## byDenoso

mongoled said:


> If you dont specifically state what help you need, for example, what are your aims while overclocking your RAM, then you are not helping people who may want to help you as they dont know what you want help for !


I need help with powering my sticks, and PBO right after it.
Since the timings appears to be "ok".
I Have a A2Hynix DJR 2x8SR Dimms.


----------



## byDenoso

Veii said:


> Good to see CAD_BUS presets still going strong
> 
> But that's CsOdtDrvStr 's part. More of it, fixes it. 30+ for my testing was always needed, unless SETUP timings were used


CKE does anything on Matisse?
I have some questions 
There's any reason to use setup timings on 2x8 SR? (Hynix DJR Sticks)
For Matisse, low procODT is good? or only to Vermeer?
Is optimal to use RTT WR/2 on sub 1,5v?
higher (30ohm+) CkeDrvStr and OdtDrvStr impedances are good for Matisse?


----------



## Veii

byDenoso said:


> For Matisse, low procODT is good? or only to Vermeer?


It was good since Summit Ridge 
It plus higher voltages~


byDenoso said:


> There's any reason to use setup timings on 2x8 SR?


Barely, potentially you can follow







But very few can run 1933+ on Matisse.
They will help with strain and clock align, in tradeoff for 0.2ish ns more latency on every operation (delay from IO Die outwards)
If setup timings are used, CAD_BUS (AddrCmd, CsOdt, Cke ~ DriveStrengths) have to be 20, lowest possible to not ruin SNR or modify strength of it.


byDenoso said:


> higher (30ohm+) CkeDrvStr and OdtDrvStr impedances are good for Matisse?


Matisse run:
24-20-20-24 quite well (Thanks 1usmus)

You can try, likely effectiveness hasn't changed.
ClkDrvStr for, well "clock signal" ~ usage to get GDM away and lower procODT (which should not be used for Dimm powering ~ still stay by this)
And lower procODT helps generally to run more SOC range and lower cLDO_VDDP.

Requirements for "lowest procODT" are lower voltages across the point. But low procODT in general helps stabilizing high voltages.
High procODT , helps run low voltages ~ but at the tradeoff of bad SNR and so FCLK/MCLK limit


byDenoso said:


> Is optimal to use RTT WR/2 on sub 1,5v?


RTT_WR depends on PARK and NOM. It can generate only one of them if one of them is disabled.
It increases strength of them as sideeffect and has main priority over them
Also RTT_WR usage enables on-dimm CRC (DDR4 included), but most "sideeffects" WR can do, needs dimms to be thermal aware. So goes also for tRFC2/4 usage.
tRFC2 could function but wont function on dimms that are not thermal aware. It simply can not.
What it can still do, is being used as accurate conversion to remain timings. tRFC1 comes from tRFC 2 not the opposite. And because of bioses rounding irregularly on hidden timings, it's good to always supply it for accuracy sake.

120 ohm WR vs 80 ohm WR is quite some difference in VDIMM requirements
You'll notice it sooner or later.
If no thermal sensor exists, the other downside is ~ it will cap maximum runnable Freq of the DIMM (DIMM-PCB dependent)
Can't say whats better if thermal sensor is lacking.
I would touch it only, when you come to the scenario of having to run PARK /7 or even disabled. Scenario where VDIMM push does harm, PARK is pretty much gone and you still need more umpf 
Else WR 80 PARK 48 , can turn to WR 120 PARK 34 ~ around there (1-2 steps lower PARK to tame stronger WR)


----------



## byDenoso

First of all, thank you for sharing your knowledge.   



Veii said:


> It was good since Summit Ridge
> It plus higher voltages~


My Matisse can run 28ohm procODT, but it increase the VDIMM requeriments by 0.2v and i'll also have to increase ClkDrvStrto 40+ohm to power the dimms correctly.




Veii said:


> arely, potentially you can follow
> 
> But very few can run 1933+ on Matisse.
> They will help with strain and clock align, in tradeoff for 0.2ish ns more latency on every operation (delay from IO Die outwards)
> If setup timings are used, CAD_BUS (AddrCmd, CsOdt, Cke ~ DriveStrengths) have to be 20, lowest possible to not ruin SNR or modify strength of it.


My FCLK Limit is 1866mhz
So its viable to run (for my 3733mhz setup) 40/20/20/20 with 3-2-14 setup timings and Cke 8? or 7?
How Cke works in Matisse?




Veii said:


> Matisse run:
> 24-20-20-24 quite well (Thanks 1usmus)
> 
> You can try, likely effectiveness hasn't changed.
> ClkDrvStr for, well "clock signal" ~ usage to get GDM away and lower procODT (which should not be used for Dimm powering ~ still stay by this)
> And lower procODT helps generally to run more SOC range and lower cLDO_VDDP.
> 
> Requirements for "lowest procODT" are lower voltages across the point. But low procODT in general helps stabilizing high voltages.
> High procODT , helps run low voltages ~ but at the tradeoff of bad SNR and so FCLK/MCLK limit


I've also noticed than a higher (1020mv+) cLDO_VDDP increases my scores both in AIDA64 and SiSandraMCE.
It has something related to powering? or is my MCLK instead?

Also, changing the "Numa Nodes per Socket" option ins BIOS from Auto to NPS2 (or NPS1) improves my AINDA64 L3 Cache Bandwidth.
EDIT: NPS1 and NPS4 does anything. 




Veii said:


> RTT_WR depends on PARK and NOM. It can generate only one of them if one of them is disabled.
> It increases strength of them as sideeffect and has main priority over them
> Also RTT_WR usage enables on-dimm CRC (DDR4 included), but most "sideeffects" WR can do, needs dimms to be thermal aware. So goes also for tRFC2/4 usage.
> tRFC2 could function but wont function on dimms that are not thermal aware. It simply can not.
> What it can still do, is being used as accurate conversion to remain timings. tRFC1 comes from tRFC 2 not the opposite. And because of bioses rounding irregularly on hidden timings, it's good to always supply it for accuracy sake.
> 
> 120 ohm WR vs 80 ohm WR is quite some difference in VDIMM requirements
> You'll notice it sooner or later.
> If no thermal sensor exists, the other downside is ~ it will cap maximum runnable Freq of the DIMM (DIMM-PCB dependent)
> Can't say whats better if thermal sensor is lacking.
> I would touch it only, when you come to the scenario of having to run PARK /7 or even disabled. Scenario where VDIMM push does harm, PARK is pretty much gone and you still need more umpf
> Else WR 80 PARK 48 , can turn to WR 120 PARK 34 ~ around there (1-2 steps lower PARK to tame stronger WR)


So a good RTTs for 1,48v~1,5v range is 7/3/6, 7/0/6, 7/0/7, 6/3/7 or 6/0/7?
Considering than high VDIMM = Lower Divider for RTTs


----------



## Telavus

Which AGESA version is coinsidered the most stable/least BS atm?
I have ASUS' Pro WS X570-ACE, and after upgrading the firmware I've had so much random instability and crashes..... (I am running PBO and memory overclock)


----------



## Veii

byDenoso said:


> My Matisse can run 28ohm procODT, but it increase the VDIMM requeriments by 0.2v and i'll also have to increase ClkDrvStr to 40+ohm to power the dimms correctly.


That's a fine tradeoff
Because ClkDrvStr's work is it to power the dimms, never procODT nor VDDPs
procODT influences too much, it's not a good idea


byDenoso said:


> So its viable to run (for my 3733mhz setup) 40/20/20/20 with 3-2-14 setup timings and Cke 8? or 7?
> How Cke works in Matisse?


tCKE 8 here and on ADL
7 on DR or pre-Skylake

It's 2.5 hmm, round up, slower wont bother
3-2-14 is ok or 3-3-14
You'll notice missmatch if at first you fail with #6's or #0's
Maybe #12's too but unsure here


byDenoso said:


> I've also noticed than a higher (1020mv+) cLDO_VDDP increases my scores both in AIDA64 and SiSandraMCE.
> It has something related to powering? or is my MCLK instead?


Which board ?
hmm
IMC and cores are far away.
VDDP and L$ has no direct voltage connection but SOC does

Both show intercore latency improvements.
That is UCLK stability. There actually SOC and procODT influence
Probably need bit more SOC, not VDDP. VDDP is reserved for MCLK and only MCLK ~ with sideeffects on clocksignal-to-dimm


byDenoso said:


> Also, changing the "Numa Nodes per Socket" option ins BIOS from Auto to NPS2 (or NPS1) improves my AINDA64 L3 Cache Bandwidth.
> EDIT: NPS1 and NPS4 does anything.


Unlikely a thing of Numa, as that was reserved for TR4 and non prosumer
But likely a thing of Memory Interleaving Size (run 256, but test if 512 outperforms)
And memory interleaving to channel ~ if still changeable (both in CBS)


byDenoso said:


> So a good RTTs for 1,48v~1,5v range is 7/3/6, 7/0/6, 7/0/7, 6/3/7 or 6/0/7?


1.42+ is 7/3/6 or 7/3/5
~1.5 is 6/3/5
near 1.54 is 6/3/6

7/0/6 is not good
0/0/5 is near 1.28-1.4v

7/0/7 maaybe can work on 1.2v JEDEC stuff ~ unlikely, PARK is too low

6/3/7 is 1.56-1.62ish
6/3/0 is then 1.64-1.71v
There we cap on SR and B-Die

Probably with 1.65+
you can run 5/3/0 too but i haven't tested if it has any positive change
Ceiling [NOM] shrinks (more ohm) by VDIMM, but for that we have ClkDrvStr - no need on RTTs

EDIT:
1.42 should be fine with 6/2/7 or even 5/2/0
But 120ohm WR on SR is questionable. Maybe on old A2 dimms and/or T-Topology


----------



## byDenoso

Veii said:


> Which board ?
> hmm
> IMC and cores are far away.
> VDDP and L$ has no direct voltage connection but SOC does
> 
> Both show intercore latency improvements.
> That is UCLK stability. There actually SOC and procODT influence
> Probably need bit more SOC, not VDDP. VDDP is reserved for MCLK and only MCLK ~ with sideeffects on clocksignal-to-dimm


My board is a B450 Aorus-M, i'm using the latest bios (with AGESA 1.2.0.7)

I've thought the same, but wasn't low SOC (Same results only changing VSOC from 1.1v~1.175v).
I recommend you test it with a stable profile and see if your benches improve in some degree with cLDO_VDDP higher tham 1060mv.
I'm at work now but i can show you the results, its almost ~400mb read and 300mb copy (write doesnt changed at all).

Another question, is tWRRD bigger than 1 really necessary on SR or is just if i split RCD?


----------



## byDenoso

Veii said:


> Unlikely a thing of Numa, as that was reserved for TR4 and non prosumer
> But likely a thing of Memory Interleaving Size (run 256, but test if 512 outperforms)
> And memory interleaving to channel ~ if still changeable (both in CBS)


I'm using 512kb since 2019, it outperforms 256kb in write and loses in read, but SCL's 2/2 can compensate it.
Its another strange behavior, seems like it does have an effect on Matisse.


----------



## Veii

byDenoso said:


> Another question, is tWRRD bigger than 1 really necessary on SR or is just if i split RCD?


You got it 
Mostly for sync and stability, else not needed
On DR needed
Also can be used to lower tRDWR -1


byDenoso said:


> I recommend you test it with a stable profile and see if your benches improve in some degree with cLDO_VDDP higher tham 1060mv.


Currently on AM5 bench, working on a good foundation. 
Then later giving it for delid and switching back to my daily, or back to the ITX ~ unsure yet. 
Downtime will be 2-3 weeks for AM5, but currently it's holding good.


----------



## SneakySloth

Telavus said:


> Which AGESA version is coinsidered the most stable/least BS atm?
> I have ASUS' Pro WS X570-ACE, and after upgrading the firmware I've had so much random instability and crashes..... (I am running PBO and memory overclock)


I've found 1.2.0.7 to be the most stable (Tomahawk x570, 5900x). I had various issues on 1.2.0.3 and almost no issues with the latest AGESA (other than the EDC being bugged but that seems to be an intentional decision by AMD).


----------



## byDenoso

Veii said:


> You got it
> Mostly for sync and stability, else not needed
> On DR needed
> Also can be used to lower tRDWR -1


In my case, considering the SCL's 2/2 with RCDRD 20 and RCDWR 16, would be RDWR 8 and WRRD5?
Or it only works with SCL's 4/4?




Veii said:


> Currently on AM5 bench, working on a good foundation.
> Then later giving it for delid and switching back to my daily, or back to the ITX ~ unsure yet.
> Downtime will be 2-3 weeks for AM5, but currently it's holding good.



Nice!
I'll follow the thread to see the crucial changes, especially on tertiary timings.


----------



## Imprezzion

@Veii can you maybe tell me what I'm doing wrong here? I read your previous few posts but I can only POST / boot to windows on 28.2 ProcODT if I really hammer on the RTT's and ClkDrvStr. I have to run 5-1-2 RTT with 40-24-30-24 to even have a hope of being able to POST and boot to Windows at 1.60v vDIMM. And it's far from stable... Almost instantly error #6 in 1usmus.

I'm using 2x16 DR B-Die btw. It's a low/mid range 4 DIMM B550 board, that probably isn't helping..


----------



## Bix

Imprezzion said:


> @Veii can you maybe tell me what I'm doing wrong here? I read your previous few posts but I can only POST / boot to windows on 28.2 ProcODT if I really hammer on the RTT's and ClkDrvStr. I have to run 5-1-2 RTT with 40-24-30-24 to even have a hope of being able to POST and boot to Windows at 1.60v vDIMM. And it's far from stable... Almost instantly error #6 in 1usmus.
> 
> I'm using 2x16 DR B-Die btw. It's a low/mid range 4 DIMM B550 board, that probably isn't helping..
> 
> View attachment 2581488


I'm sure Veii will be able to offer you better advice than I can but in the meantime be careful with your RTTs at that kind of VDIMM - Wr and Park that strong can fry your contacts if you're not careful!


----------



## Imprezzion

Bix said:


> I'm sure Veii will be able to offer you better advice than I can but in the meantime be careful with your RTTs at that kind of VDIMM - Wr and Park that strong can fry your contacts if you're not careful!


Thanks, i won't run this then. Honestly, being an ex Intel fanboy and long time overclocker I know everything about Intel RTL IO, ODT, Skews, that sorta stuff but I know next to nothing about AMD specific things like RTT's.. I would like some basic knowledge of what does what and Veii's posts help me a LOT but it's still all a bit too "straight into the deep end" for me haha.

That's why I try to stick to copying stuff from you guys from succesfull TM5 runs but.. no real luck yet for 3933 so far. The IMC handles it, no WHEA whatsoever (i do run quite high vSOC and VDDG tho) but it handles it fine. I just can't get the RAM to work.. I mean, it ran on my 11900K 3933 14-15-15-28-256-2T @ 1.59v 10h TM5 stable but I can't even get anywhere near that on this setup..

EDIT:

So, this is 3933 / 1966 1:1 on all Auto DOCP 3600C16 timings and full Auto RTT, ODT, DrvStr's..
1.450v vDIMM, the rest is visible in the ZenTimings window. It needs a lot of VDDG and vSOC to not WHEA but it's clear as it is now. Not sure why CLDO VDDP Auto's at such a high value but it works.. i mean.. it runs 3933 quite easily but now I just have to figure out how to tighten the timings up a LOT without error loads of #6 #12 and #13...


----------



## Bix

Imprezzion said:


> Thanks, i won't run this then. Honestly, being an ex Intel fanboy and long time overclocker I know everything about Intel RTL IO, ODT, Skews, that sorta stuff but I know next to nothing about AMD specific things like RTT's.. I would like some basic knowledge of what does what and Veii's posts help me a LOT but it's still all a bit too "straight into the deep end" for me haha.
> 
> That's why I try to stick to copying stuff from you guys from succesfull TM5 runs but.. no real luck yet for 3933 so far. The IMC handles it, no WHEA whatsoever (i do run quite high vSOC and VDDG tho) but it handles it fine. I just can't get the RAM to work.. I mean, it ran on my 11900K 3933 14-15-15-28-256-2T @ 1.59v 10h TM5 stable but I can't even get anywhere near that on this setup..
> 
> EDIT:
> 
> So, this is 3933 / 1966 1:1 on all Auto DOCP 3600C16 timings and full Auto RTT, ODT, DrvStr's..
> 1.450v vDIMM, the rest is visible in the ZenTimings window. It needs a lot of VDDG and vSOC to not WHEA but it's clear as it is now. Not sure why CLDO VDDP Auto's at such a high value but it works.. i mean.. it runs 3933 quite easily but now I just have to figure out how to tighten the timings up a LOT without error loads of #6 #12 and #13...
> 
> View attachment 2581507


For what it's worth I gave up on trying to stabilize above 3800 on my B2 5900x since the performance wasn't really scaling anyway. After really tightening my timings I'm now performing better at 3800 than I was at 4000 on my old B0 and I didn't need to go anywhere near as high as you do with SOC so you're eating into your boosting budget a lot more. 

It's tempting to push FCLK but if it takes that much voltage to get rid of WHEA 19s then you might just be best off tightening everything up at 3800 - at the very least you'll be able to see if your performance scales above that. If it scales in spite of the WHEAs and is stable at lower voltages then you can always use @ManniX-ITA 's suppressor...


----------



## MrHoof

Imprezzion said:


> Thanks, i won't run this then. Honestly, being an ex Intel fanboy and long time overclocker I know everything about Intel RTL IO, ODT, Skews, that sorta stuff but I know next to nothing about AMD specific things like RTT's.. I would like some basic knowledge of what does what and Veii's posts help me a LOT but it's still all a bit too "straight into the deep end" for me haha.
> 
> That's why I try to stick to copying stuff from you guys from succesfull TM5 runs but.. no real luck yet for 3933 so far. The IMC handles it, no WHEA whatsoever (i do run quite high vSOC and VDDG tho) but it handles it fine. I just can't get the RAM to work.. I mean, it ran on my 11900K 3933 14-15-15-28-256-2T @ 1.59v 10h TM5 stable but I can't even get anywhere near that on this setup..
> 
> EDIT:
> 
> So, this is 3933 / 1966 1:1 on all Auto DOCP 3600C16 timings and full Auto RTT, ODT, DrvStr's..
> 1.450v vDIMM, the rest is visible in the ZenTimings window. It needs a lot of VDDG and vSOC to not WHEA but it's clear as it is now. Not sure why CLDO VDDP Auto's at such a high value but it works.. i mean.. it runs 3933 quite easily but now I just have to figure out how to tighten the timings up a LOT without error loads of #6 #12 and #13...
> 
> View attachment 2581507


6 is like the worst error you can get on TM 1usmus. It can mean anything its that just data is not transmitting correctly to the IMC.
Its a error u see alot if u try to go stabilize 1T when something is not right, but it shows mostly early in cycles if its late its mostly a lack of Vdimm.
edit: did u try 15-15-15 with like 1.55?


----------



## Imprezzion

MrHoof said:


> 6 is like the worst error you can get on TM 1usmus. It can mean anything its that just data is not transmitting correctly to the IMC.
> Its a error u see alot if u try to go stabilize 1T when something is not right, but it shows mostly early in cycles if its late its mostly a lack of Vdimm.
> edit: did u try 15-15-15 with like 1.55?


Yeah I gave up on 1T GDM Off. 1T GDM On is default for DOCP profile and that runs fine but even DOCP 3600C16 won't do 1T GDM Off. It boots fine with AddrCmdSetup 56 for example but just spits errors 6 and 12 after like 5-8 minutes of TM5 regardless of what I change in vDIMM, RTT or DrvStr's..

I'm running a bit of Division 2 now on the above 3933C16 setup just to see if the random crashes are still there or not.

I did get my Dominator Airflow coolers in at least and that took 12c off the DIMM temps from 53 to 41 so that should give me some more headroom.

I will first try to drop the voltages for VDDG vSOC and VDDP one by one to see where the WHEA's start to show up and if it's worth running this high FCLK/UCLK or not.


----------



## MrHoof

I would just settle with 3800, the 5800x3d does not benefit enough to be worth the hassle. Mine does it as low as 1.025v SOC and 0.975 vddg, the performance gain to push higher is just not there to justify the higher powerdraw imo, especially in times were power is as expensive as ever atleast here.
edit: AMD SOC and infinity fabric is the main reason why idle powerdraw is higher than Intel, the integrated memory controller saves power in idle.
I like my PC efficient and fast


----------



## Imprezzion

MrHoof said:


> I would just settle with 3800, the 5800x3d does not benefit enough to be worth the hassle. Mine does it as low as 1.025v SOC and 0.975 vddg, the performance gain to push higher is just not there to justify the higher powerdraw imo, especially in times were power is as expensive as ever atleast here.
> edit: AMD SOC and infinity fabric is the main reason why idle powerdraw is higher than Intel, the integrated memory controller saves power in idle.
> I like my PC efficient and fast


Same, and that's why I chose the 5800X3D and not a 12900K/13900K + Z690/Z790 DDR4. Load and game power draw is so insanely high on those.. My 11900K @ 5.1 drew like 185w in Division 2. This chip gets way more FPS at like 60w... Ok, it idles at ~24w in stead of ~18w of the 11900K but that is hardly a difference...

Btw, what is the best test to run to force WHEA to appear.. I dropped the voltages quite a lot and it still shows zero errors in TM5, y-cruncher test 17, AVX X265 encoding, games.. everything works..

Sorry about the phone pic, i didn't wanna alt tab out of the game I'm idling as a test now. I might just keep this profile and tweak some secondary timings like tRFC, tWR, tTDWR and tRRD + tFAW and just leave it here. It seems perfectly happy to run 4450 @ -23 all core CO in most tests except the hardest AVX0 stuff. That drops to 4300-4325 but it also does that on -30 with lower voltages so... No loss there..

(Note the 3080 running at a perfect undervolt staying right at the power limit without throttling, it took me days to find a perfect curve UV for that with memory at +1200, yes the mem temps are atrocious, I have Bykski full cover block stock pads but plan to put on Gelid Extreme's next weekend)


----------



## byDenoso

@Veii now tested with correct settings (cLDO_VDDP is higher because i get better scores)


EDIT:









AIDA bench


----------



## Imprezzion

Passed overnight at below settings. vDIMM = 1.450v. No WHEA's either at this vSOC and VDDG / VDDP. Best part, tPHYRDL is actually 28/28 and not mismatched.


----------



## The_King

Imprezzion said:


> Passed overnight at below settings. vDIMM = 1.450v. No WHEA's either at this vSOC and VDDG / VDDP. Best part, tPHYRDL is actually 28/28 and not mismatched.
> 
> View attachment 2581560


Sometimes changing sub times can changes PHY from 28 to 26. RDWR can and should be at 8 when TCL is 16.

WRRD for dual rank can be 3/4 ? Maybe 2 not sure if 1 may cause post issues.

Please also run CPUZ MT stress for about 5 minutes and see that you not losing any performance under load.
Passing TM5 without errors shows the memory is fine but the increase in FCLK/MCLK/UCLK can cause performance issues if IOD is not correct.


----------



## Imprezzion

The_King said:


> Sometimes changing sub times can changes PHY from 28 to 26. RDWR can and should be at 8 when TCL is 16.
> 
> WRRD for dual rank can be 3/4 ? Maybe 2 not sure if 1 may cause post issues.
> 
> Please also run CPUZ MT stress for about 5 minutes and see that you not losing any performance under load.
> Passing TM5 without errors shows the memory is fine but the increase in FCLK/MCLK/UCLK can cause performance issues if IOD is not correct.
> View attachment 2581562


Wanna know the weird thing that made it actually not WHEA or error in TM5? Running DOCP in stead of Manual for OC. All I did was load DOCP 3600C16, set frequency to 3933 / 1966 and vDIMM to 1.450, tweak some secondaries, set manual vSOC, VDDG and VDDP and run it. The ProcODT, RTT's, ClkDrvStr, and 1T GDM On is all set by DOCP / Auto and now it works...

WRRD and RDWR are still on Auto / DOCP so I'll tweak those tonight and maybe I'll even try to switch to 14-16-16 with lower tRAS.. 

I did run Cinebench R23 looped for 60 minutes and saw no real performance regression but I'll also run CPU-Z. My scores are kinda meh but that's purely because I use a very old Windows install that has seen 4 motherboards and 2 Intel and 2 AMD CPU's and has loads of bloat. Just about hit 15000 in R23 and 6440 in CPU-Z. I do also use CPPC and Preferred Cores on.


----------



## byDenoso

Imprezzion said:


> @Veii can you maybe tell me what I'm doing wrong here? I read your previous few posts but I can only POST / boot to windows on 28.2 ProcODT if I really hammer on the RTT's and ClkDrvStr. I have to run 5-1-2 RTT with 40-24-30-24 to even have a hope of being able to POST and boot to Windows at 1.60v vDIMM. And it's far from stable... Almost instantly error #6 in 1usmus.


Error #6 used to be 20mv VDIMM missing...try to increase ClkDrvStr to 60ohm or give it +20mv more VDIMM...
You can also try RTT's 6/2/3 to see if it works.


----------



## Iarwa1N

I tried tRC 34 (tRP 13 + tRAS 21), but I got lots of errors on test 6, then I tried 35 and this time I got errors on test 0. My vDIMM is 1.56V. Whatelse can I try to improve this timings?


----------



## Imprezzion

Iarwa1N said:


> I tried tRC 34 (tRP 13 + tRAS 21), but I got lots of errors on test 6, then I tried 35 and this time I got errors on test 0. My vDIMM is 1.56V. Whatelse can I try to improve this timings?
> 
> View attachment 2581720


1T CMD maybe? Not much else. Maybe tRFC 1 tick down at 240?


----------



## Nighthog

Finally!
Had trouble with TM5 getting to pass with the BCLK @ 102.5.
Surprisingly it was CkeDrvStr needing 24Ohm to make it pass.
Was trying so many things this past week and more trying to get to pass a 25cycle run but always failed at some stage with everything I was trying.
I tried higher & lower voltages, looser timings and playing around with the DrvStr & setup timings but this combo finally worked out.

No issues with Audio or game stutter either.(which was priorty one to fix) Only note to make is the system will freeze on a cold boot but a restart is all that is needed.
BCLK seems to cause issues with the PCIe connection to GPU that fails @ cold but works afterwards with a restart/reboot.


----------



## mongoled

Veii said:


> Good to see CAD_BUS presets still going strong
> 
> But that's CsOdtDrvStr 's part. More of it, fixes it. 30+ for my testing was always needed, unless SETUP timings were used


Yeah CAD_BUS presets are still going strong 

Have been stress testing the PC with the three most suitable tools (core-cycler, Y-Cruncher & TM5) for testing CO along with the CL13, uber low tRFC settings I am pushing.

And the conclusion is that the failing of the VST test was because of not setting "*Power Supply Idle Control"* manually to "Typical".

No more random VST crashes and my 24/7 settings that have been tested stable on agesa 1.1.9.0, 1.2.0.3c and now 1.2.0.7 are perfectly ok without having to change anything apart from re-tweak CO.

It looks like when pushing low tRFC (under 240), with low tCL (under 14) some transient issue occurs with power delivery which setting "*Power Supply Idle Control"* to "Typical" alleviates the issue.

Regards CsOdtDrvStr on my 4133/2066 profile, no point me spending anymore time on that profile as I am not going to be using it for a 24/7 settings, not because it is not a "stable" profile, as it is, just the fact that it eats into the power budget when having to run vSOC at 1.225v for there not be any audio glitching and to sustain the "correct" performance in apps that hammer all cores of the CPU.

I dont see the day ever returning when AMD will give us full control over the CPUs, having this 5600x is just so frustrating as I know there is more in it, however, with the EDC design "flaw" on the last few agesa's, along with the lower available CPU vid means the 5600x is bottle necked not by the silicon but by the implemented restrictions.

Though the 4133/2066 profile is excellent for running memory intensive benchmarks


----------



## mongoled

Imprezzion said:


> Wanna know the weird thing that made it actually not WHEA or error in TM5? Running DOCP in stead of Manual for OC. All I did was load DOCP 3600C16, set frequency to 3933 / 1966 and vDIMM to 1.450, tweak some secondaries, set manual vSOC, VDDG and VDDP and run it. The ProcODT, RTT's, ClkDrvStr, and 1T GDM On is all set by DOCP / Auto and now it works...
> 
> WRRD and RDWR are still on Auto / DOCP so I'll tweak those tonight and maybe I'll even try to switch to 14-16-16 with lower tRAS..
> 
> I did run Cinebench R23 looped for 60 minutes and saw no real performance regression but I'll also run CPU-Z. My scores are kinda meh but that's purely because I use a very old Windows install that has seen 4 motherboards and 2 Intel and 2 AMD CPU's and has loads of bloat. Just about hit 15000 in R23 and 6440 in CPU-Z. I do also use CPPC and Preferred Cores on.


I can see you are wanting to delve deep into overclocking those rams on the Ryzen platform.

Seeing you are using b-die ICs, why do you have GDM set to "enabled" ?

This is not helping you diagnose your settings as it is masking underlying issues that we have no control of i.e. hidden memory timings that we have no access to read or write.

I get it that it helps some peeps get easier "stable" settings, but its not helpful when you are tweaking individual timings and want to see the imapct of the changes you are making seeing that GDM enabled is autocorrecting everything ...


----------



## Farih

Is something very different between 3700x IMC and 5800X3D IMC?
or
Is there a notable difference between B550 and X570 chipsets regarding memory overclocking?

On my 3700x i was able to get my ram to this:
1.54V









But on the 5800X3D i just can't seem to get it to 3800mhz cl14
This is what i got so far:
1.505V









Thought Zen3 IMC's are better/stronger then Zen2 so am i seeing these difficulties because of the board?
Should i switch back to my old X570? (dont really want to)


----------



## Imprezzion

mongoled said:


> I can see you are wanting to delve deep into overclocking those rams on the Ryzen platform.
> 
> Seeing you are using b-die ICs, why do you have GDM set to "enabled" ?
> 
> This is not helping you diagnose your settings as it is masking underlying issues that we have no control of i.e. hidden memory timings that we have no access to read or write.
> 
> I get it that it helps some peeps get easier "stable" settings, but its not helpful when you are tweaking individual timings and want to see the imapct of the changes you are making seeing that GDM enabled is autocorrecting everything ...


I had many many issues with manually setting everything, sort of to blame on the cheap board, sort of to blame on the DIMM temperatures. I just did a quick test that kinda got out of hand with a 5h run to check simply what RAM and FCLK frequency I could pull off without timings causing problems so I just loaded DOCP/XMP 3600C16 profile and set freq to 3933. The 1T GDM On is set by the DOCP profile / Auto timings and proved to be rock solid and performance in general is great. AIDA results are great, game performance is great. I prefer to just use 1T or even 2T GDM Off but if reality proves my board doesn't wanna run that stable but it does do 1T GDM On fine, why not. Even if I just give up on RAM OC and just run DOCP daily it'll still run 1T GDM On.


----------



## The_King

Farih said:


> Is something very different between 3700x IMC and 5800X3D IMC?
> or
> Is there a notable difference between B550 and X570 chipsets regarding memory overclocking?
> 
> On my 3700x i was able to get my ram to this:
> 1.54V
> View attachment 2581778
> 
> 
> But on the 5800X3D i just can't seem to get it to 3800mhz cl14
> This is what i got so far:
> 1.505V
> View attachment 2581779
> 
> 
> Thought Zen3 IMC's are better/stronger then Zen2 so am i seeing these difficulties because of the board?
> Should i switch back to my old X570? (dont really want to)


I have seen some struggle to get FCLK 1900 to work with the 5800X3D and other ZEN 3 CPUs. You are running 4 DIMMS so that can complicate things. Try ProcODT 40 and 43.6.

If that does not work try going one step above 3867MT and 1933 FCLK

If you drop DIMMS from 4 to 2 and can boot FCLK 1900 then you know there is probably no 1900 FCLK hole and the problem maybe with the mobo..


----------



## Farih

The_King said:


> I have seen some struggle to get FCLK 1900 to work with the 5800X3D and other ZEN 3 CPUs. You are running 4 DIMMS so that can complicate things. Try ProcODT 40 and 43.6.
> 
> If that does not work try going one step above 3867MT and 1933 FCLK
> 
> If you drop DIMMS from 4 to 2 and can boot FCLK 1900 then you know there is probably no 1900 FCLK hole and the problem maybe with the mobo..


Tryed different ProcODT's to no avail.

Trying 2 DIMMS seems like a good suggestion thanks.

Wish me luck!


----------



## byDenoso

Iarwa1N said:


> I tried tRC 34 (tRP 13 + tRAS 21), but I got lots of errors on test 6, then I tried 35 and this time I got errors on test 0. My vDIMM is 1.56V. Whatelse can I try to improve this timings?



Well,here is the list of what you can try:
Give it +20mv VDIMM
Increase ClkDrvStr to 30ohm
Lower ProcODT to 32ohm
increase the tWTR to 4/12 and tRDD to 4/6
TWR 14 and tRTP 7
SCL's to 4 (If you're using 4 DIMMS, SCL 4/4 mostly outperforms SCLs 2/2)

When you fix it, you can try 1T:
ClkDrvStr to 40ohm+
Setup Timings (according with your frequency)
It should work


----------



## byDenoso

Farih said:


> Is there a notable difference between B550 and X570 chipsets regarding memory overclocking?


Maybe a higher cLDO_VDDP is powering more your DIMMS making it work better


----------



## RackarN

Nighthog said:


> Finally!
> Had trouble with TM5 getting to pass with the BCLK @ 102.5.
> Surprisingly it was CkeDrvStr needing 24Ohm to make it pass.
> Was trying so many things this past week and more trying to get to pass a 25cycle run but always failed at some stage with everything I was trying.
> I tried higher & lower voltages, looser timings and playing around with the DrvStr & setup timings but this combo finally worked out.
> 
> No issues with Audio or game stutter either.(which was priorty one to fix) Only note to make is the system will freeze on a cold boot but a restart is all that is needed.
> BCLK seems to cause issues with the PCIe connection to GPU that fails @ cold but works afterwards with a restart/reboot.


1.38 SOC?


----------



## Akex

Hello, back on OCN and on my 5700G, I decided to push the frequency further, I had stopped at 4733C16 in a stable way, then in the meantime I changed the box, I said to myself why not try again to do better.

Currently I am therefore testing 4866C16, only tCL/tRCD/tRP/tRAS/tRC are configured manually as a base, the rest in auto.

vSOC this high is for the iGPU at 2550Mhz so don't worry it's normal.
ProcODT and RTT are all manually configured as cLDO_VDDP.

I miss something, I manage to do 15000% on Kharu at 1.665v which corresponds to 6H+. On the other hand, for some reason that still escapes me, the PC will immediately reboot as if I had a bad curve, which is not the case, the CPU is stock, but the idea is the behavior I have. I did a quick tour on TM5 with the 1usmus profile to see the errors that are triggered, I have 0,0,0,0,15 when there is an error. I restart TM5 and for more than 4 hours I have no errors, until the PC reboots.

For the moment, I started to work again with cLDO_VDDP, at the beginning I started with 1.050, I went to 1.1 and 1.115v to end up currently at 1.15, bench in court.

Based on your experiences, where should I go to target my random reboot problem?

Edit: 
ProcODT 40 gives the same behavior.
ProcODT 43.6 does not boot


----------



## The_King

Akex said:


> Hello, back on OCN and on my 5700G, I decided to push the frequency further, I had stopped at 4733C16 in a stable way, then in the meantime I changed the box, I said to myself why not try again to do better.
> 
> Currently I am therefore testing 4866C16, only tCL/tRCD/tRP/tRAS/tRC are configured manually as a base, the rest in auto.
> 
> vSOC this high is for the iGPU at 2550Mhz so don't worry it's normal.
> ProcODT and RTT are all manually configured as cLDO_VDDP.
> 
> I miss something, I manage to do 15000% on Kharu at 1.665v which corresponds to 6H+. On the other hand, for some reason that still escapes me, the PC will immediately reboot as if I had a bad curve, which is not the case, the CPU is stock, but the idea is the behavior I have. I did a quick tour on TM5 with the 1usmus profile to see the errors that are triggered, I have 0,0,0,0,15 when there is an error. I restart TM5 and for more than 4 hours I have no errors, until the PC reboots.
> 
> For the moment, I started to work again with cLDO_VDDP, at the beginning I started with 1.050, I went to 1.1 and 1.115v to end up currently at 1.15, bench in court.
> 
> Based on your experiences, where should I go to target my random reboot problem?
> 
> Edit:
> ProcODT 40 gives the same behavior.
> ProcODT 43.6 does not boot
> 
> View attachment 2581839


Random reboots for me was usually VSOC and rarely but sometimes when VDIMM was a bit low needing +0.1.

The problem can also be IOD and that IF can't handle 2433 what is your IOD voltages? If its not set correctly you would be losing tons of performance in MT tests.
At 3933/4000 which is very low I need at lease 1.15V IOD on 5800X so not sure what would be needed for your 5700G.

Unstable IF will also cause reboots so you may need to go down if adjusting IOD and other voltages fails.
But these are just my views which may be wrong has I don't have a 5700G but want one now. 



> VDDG IOD: 1.05V (baseline), 1.0-1.075V (daily), 1.10-1.2V (extreme overclocking)
> 
> 
> This powers the PHY that sends signals from the IOD back to the CCDs along the infinity-fabric link. Because it is a signalling voltage there is no benefit to running higher values, you want to find the “sweet-spot” which maximise performance and minimise WHEA-19 events.
> Optimal voltage seems to scale roughly linearly with FCLK frequency, low values will dramatically decrease Aida64 read bandwidth and latency. Going too high can cause instability in FCLK stress tests, so don’t go far over 1.05V generally.


Source





Infinity Fabric Overclocking on Zen2/3







docs.google.com





Please post AIDA64 numbers when you can would love to see what you get with that config.


----------



## mongoled

Imprezzion said:


> I had many many issues with manually setting everything, sort of to blame on the cheap board, sort of to blame on the DIMM temperatures. I just did a quick test that kinda got out of hand with a 5h run to check simply what RAM and FCLK frequency I could pull off without timings causing problems so I just loaded DOCP/XMP 3600C16 profile and set freq to 3933. The 1T GDM On is set by the DOCP profile / Auto timings and proved to be rock solid and performance in general is great. AIDA results are great, game performance is great. I prefer to just use 1T or even 2T GDM Off but if reality proves my board doesn't wanna run that stable but it does do 1T GDM On fine, why not. Even if I just give up on RAM OC and just run DOCP daily it'll still run 1T GDM On.


I was not aware that you have tried to manually set the timings and were having trouble with that, I am guessing you had guidance from this forum while you were doing that ? As sometimes it can be one setting that is holding everything back.

I mentioned GDM disabled simply because you then have the most control over your timings rather than everything being auto corrected, there is not a right or wrong way to this.



@Veii
Real quickly I tested CsOdtDrvStr for my 4133/2067 profile, I went up to 60 ohms before I saw a difference, it did not help cold boot issues, but seem to have helped with warm booting, however, raising this value from 30 ohms to 60 ohms made memory completely unstable, I first tried Y-Cruncher, instant crash. Then tried core cycler, again, as it load large FFTs first, instant crash.


----------



## Imprezzion

mongoled said:


> I was not aware that you have tried to manually set the timings and were having trouble with that, I am guessing you had guidance from this forum while you were doing that ? As sometimes it can be one setting that is holding everything back.
> 
> I mentioned GDM disabled simply because you then have the most control over your timings rather than everything being auto corrected, there is not a right or wrong way to this.
> 
> 
> 
> @Veii
> Real quickly I tested CsOdtDrvStr for my 4133/2067 profile, I went up to 60 ohms before I saw a difference, it did not help cold boot issues, but seem to have helped with warm booting, however, raising this value from 30 ohms to 60 ohms made memory completely unstable, I first tried Y-Cruncher, instant crash. Then tried core cycler, again, as it load large FFTs first, instant crash.


I did attempt again yesterday to get GDM Off 1T to work and while I can get it to boot to Windows at 3933 it will not stabilize at all. Didn't change any other timings from the stable profile. Just GDM Off, 1T CMD, AddrCmdSetup has to be 56 or 60, any other value doesn't boot (BSOD while loading Windows or no POST), played around with many combinations of RTT's, ClkDrvStr, ProcODT, much higher vDIMM, it basically always results in error #0 or 12 in TM5 within minutes of starting a test. It will run 2T fine but performance is worse. I should've gone for a better board. The B550-A is a fine enough board for just daily usage (and it had to be white to match the color scheme of my build) but I should've gotten a NZXT N7 B550 or a ASUS Prime X570 Pro honestly. 

The only thing I am going to try later this week now that I have active cooling on my DIMM's again is go back to 14-16-16 and tighten up the tRAS and tRC a bit now that I can run ~1.60v vDIMM again without the DIMM's going over 50c. Maybe even tweak tWR, tRRD_L and tWRRD down a bit as well if the DIMM's wanna behave.


----------



## mongoled

Imprezzion said:


> I did attempt again yesterday to get GDM Off 1T to work and while I can get it to boot to Windows at 3933 it will not stabilize at all. Didn't change any other timings from the stable profile. Just GDM Off, 1T CMD, AddrCmdSetup has to be 56 or 60, any other value doesn't boot (BSOD while loading Windows or no POST), played around with many combinations of RTT's, ClkDrvStr, ProcODT, much higher vDIMM, it basically always results in error #0 or 12 in TM5 within minutes of starting a test. It will run 2T fine but performance is worse. I should've gone for a better board. The B550-A is a fine enough board for just daily usage (and it had to be white to match the color scheme of my build) but I should've gotten a NZXT N7 B550 or a ASUS Prime X570 Pro honestly.
> 
> The only thing I am going to try later this week now that I have active cooling on my DIMM's again is go back to 14-16-16 and tighten up the tRAS and tRC a bit now that I can run ~1.60v vDIMM again without the DIMM's going over 50c. Maybe even tweak tWR, tRRD_L and tWRRD down a bit as well if the DIMM's wanna behave.


What about at 3800/1900 ? Is that also very unstable ?

Ive been through all the trails and tribulations with FCLK, in the end I doubled down on 3800/1900 with the tightest settings.

There are very few people who can run GDM disabled, 1T with no setup timings, the few people who can are running 2 x 16GB, 2 x 8GB on ITX boards with the rare occurance on a non ITX board. I can also run GDM disabled, 1T with no setup timings when only using two dimms on my x570 Unify.

Below are my current 24/7 settings


----------



## Nighthog

RackarN said:


> 1.38 SOC?


Yeah it's not the best sample with the IOD/Memory controller. Needs a lot of voltage to clear performance loss or [Audio issues]<-- (The main issue).
I could probably go back and retest it at lower voltages but at this voltage is just started working and always had issues above 2000FCLK with less for most part when trying to get it to work.
I've even tried running higher at times.
*I don't recommend other try these voltages.*
It eats into your PPT limit to have this much power into the SoC. Reduces multi-thread scores as it's getting throttled because of power constraints. (you can't increase PPT on these X3D chips)

I would prefer to stay below 1.300V SoC but had no luck without issues creeping up. So it's at it just works crammed into it for now as I verify that there is no other trouble when I got TM5 to work stable with the BCLK adjustment. I could go back and retest to see where the actual Audio issue start to come around. These voltages just worked to fix all issues so I just kept using them for the past week. Otherwise I just kept changing voltage after voltage trying to fix the Audio to be trouble free. It's so annoying to hear crackle, pop's or noise when you try to game or listen to music & video etc.

EDIT: Just to check I went back to more reasonable 1.300V SoC and didn't encounter the major issue I had been trying to avoid for a long time so will take my time to retest for a while.


----------



## Akex

The_King said:


> Random reboots for me was usually VSOC and rarely but sometimes when VDIMM was a bit low needing +0.1.
> 
> The problem can also be IOD and that IF can't handle 2433 what is your IOD voltages? If its not set correctly you would be losing tons of performance in MT tests.
> At 3933/4000 which is very low I need at lease 1.15V IOD on 5800X so not sure what would be needed for your 5700G.
> 
> Unstable IF will also cause reboots so you may need to go down if adjusting IOD and other voltages fails.
> But these are just my views which may be wrong has I don't have a 5700G but want one now.
> 
> 
> 
> Source
> 
> 
> 
> 
> 
> Infinity Fabric Overclocking on Zen2/3
> 
> 
> 
> 
> 
> 
> 
> docs.google.com
> 
> 
> 
> 
> 
> Please post AIDA64 numbers when you can would love to see what you get with that config.


No vDDG available for Cezane in bios.

I don't think it's IOD because if I apply the 4866Mhz test profile during a cold boot, then the moment I get to windows I reboot immediately, no matter how many times I will restart the pc.
On the other hand, if I go through the stable 4733Mhz profile, and then go up to 4800 & 4866, then I can use the PC for several hours before a random reboot. So I think it's something related to the RAM module, a broken memory formation may be, or at least one or more timings that cause this phenomenon, I don't know.
I've upgraded to a more aggressive vDIMM, but nothing works.

I'll post you an AIDA when I have advanced on my current profile, for the moment it sucks, it lacks too much timing to settle in the current state to have real stats.


----------



## Iarwa1N

byDenoso said:


> Well,here is the list of what you can try:
> Give it +20mv VDIMM
> Increase ClkDrvStr to 30ohm
> Lower ProcODT to 32ohm
> increase the tWTR to 4/12 and tRDD to 4/6
> TWR 14 and tRTP 7
> SCL's to 4 (If you're using 4 DIMMS, SCL 4/4 mostly outperforms SCLs 2/2)
> 
> When you fix it, you can try 1T:
> ClkDrvStr to 40ohm+
> Setup Timings (according with your frequency)
> It should work


Thanks for the help.

+20mv vDimm: done, now it is 1.6v,
Increase ClkDrvStr to 30ohm: didn't work, but 40ohm worked
Lower ProcODT to 32ohm, done,
increase the tWTR to 4/12 and tRDD to 4/6: I didn't change these yet, still the same as previous
TWR 14 and tRTP 7: done, with tRTP to 7, increased tRAS to 22 (was 21), with tRAS 22 tRC is 35 now (was 36)
SCL's to 4: done, using 2 DIMM 2x16 gb dual rank b-die


----------



## RackarN

Nighthog said:


> Yeah it's not the best sample with the IOD/Memory controller. Needs a lot of voltage to clear performance loss or [Audio issues]<-- (The main issue).
> I could probably go back and retest it at lower voltages but at this voltage is just started working and always had issues above 2000FCLK with less for most part when trying to get it to work.
> I've even tried running higher at times.
> *I don't recommend other try these voltages.*
> It eats into your PPT limit to have this much power into the SoC. Reduces multi-thread scores as it's getting throttled because of power constraints. (you can't increase PPT on these X3D chips)
> 
> I would prefer to stay below 1.300V SoC but had no luck without issues creeping up. So it's at it just works crammed into it for now as I verify that there is no other trouble when I got TM5 to work stable with the BCLK adjustment. I could go back and retest to see where the actual Audio issue start to come around. These voltages just worked to fix all issues so I just kept using them for the past week. Otherwise I just kept changing voltage after voltage trying to fix the Audio to be trouble free. It's so annoying to hear crackle, pop's or noise when you try to game or listen to music & video etc.
> 
> EDIT: Just to check I went back to more reasonable 1.300V SoC and didn't encounter the major issue I had been trying to avoid for a long time so will take my time to retest for a while.


Scary voltage for sure, i only run 102 bclk







have some timings i need to tighten but im just lazy right now.. the 4800mhz rabbit hole was all fun and games, it was faster than my 1933 setup but had 5ns more latency. This is faster in every scenario.


----------



## Imprezzion

mongoled said:


> What about at 3800/1900 ? Is that also very unstable ?
> 
> Ive been through all the trails and tribulations with FCLK, in the end I doubled down on 3800/1900 with the tightest settings.
> 
> There are very few people who can run GDM disabled, 1T with no setup timings, the few people who can are running 2 x 16GB, 2 x 8GB on ITX boards with the rare occurance on a non ITX board. I can also run GDM disabled, 1T with no setup timings when only using two dimms on my x570 Unify.
> 
> Below are my current 24/7 settings
> View attachment 2581941


Not 1T GDM Off but I needed a baseline for 3800 first for primary timings and FCLK stability. Got WHEA's if I lower vSOC / IOD any more then this. CCD and VDDP might be able to go lower but haven't tried yet. This is a LOT lower then 1966 that's for sure. vDIMM is set to 1.565v as this is what I had to run on 11900K for tCL 14 with this low of a tRFC on 3800 but maybe it can also be lowered slightly? I also forgot to set tRCDWR lower to like 8 but k. You don't have that either . I might throw SCL's to 2 since I run 2 DIMM's maybe? DIMM's are hotter then i'd like as it's only 17c ambient here now. In the summer this would be far too hot to remain stable without raising fan speeds on my Dominator Airflows or running no sidepanel i'm guessing.

Now that I have a stable baseline for 3800/1900 I can tweak further from here and see if I can get 1T GDM Off to work with this.










EDIT:

Well, you were right. On 3800 1T GDM Off works fine so far with just AddrCmdSetup 56 and a bit more ClkDrvStr even on this not-so-great board! I'll let the test run overnight but it seems very very promising. No more errors within 3 minutes. Only thing I noticed is that tPHYRDL went from 26/28 to 28/28 with 1T GDM Off. Probably not a problem..?


----------



## Priller

3800/1900 looks so easy for some. My board seems to have the 1900IF hole and voltage doesnt do anything.

LN2 mode will get it to boot but its very unstable and above that is WHEA city.

Anyone able to post their VDDP voltage for 58X/59X ? I haven't found a bios that will let me control it on my CH7.


----------



## kairi_zeroblade

Priller said:


> My board seems to have the 1900IF hole and voltage doesnt do anything.


IF hole isn't in the motherboard..its in the processor


----------



## Priller

kairi_zeroblade said:


> IF hole isn't in the motherboard..its in the processor


Same symptoms with 2 different processors including a B2 5900X. I wish I had a B550 or X570 board to try my CPU in to know for sure.


----------



## kairi_zeroblade

Priller said:


> Same symptoms with 2 different processors including a B2 5900X. I wish I had a B550 or X570 board to try my CPU in to know for sure.


my 5800X B0 has the 1900 IF hole, I am using a B550F strix motherboard, when I upgraded to a 5900X B0 the IF hole was gone. even when I changed to a Dark Hero nothing even happened with the 5800X, still a hole in 1900 IF..


----------



## Akex

Handling error while wanting to set vSOC with the offset to keep the pstate on the iGPU, results CPU dead. It must also be said that during the Team CUP 2022 it suffered... I get another one on Saturday, I hope it will be at least as good, 2550Mhz stable in Air for the IGPU it's rare... Anyway be careful with your settings, I am experienced and yet a moment of inattention cost me my 5700G.


----------



## Priller

kairi_zeroblade said:


> my 5800X B0 has the 1900 IF hole, I am using a B550F strix motherboard, when I upgraded to a 5900X B0 the IF hole was gone. even when I changed to a Dark Hero nothing even happened with the 5800X, still a hole in 1900 IF..


That's what I thought but I've read some posts that said bios updates fixed it or changing boards did and I've changed everything but the board at this point.


----------



## Imprezzion

Priller said:


> That's what I thought but I've read some posts that said bios updates fixed it or changing boards did and I've changed everything but the board at this point.


My B2 5900X had a 1900 hole as well but 1933 ran perfectly fine. 1.25 vSOC, 1.1 CCD, 1.05 IOD, 0.950 VDDP. I had it on a B550-XE which I still regret selling.. 

3800C14 1T GDM Off ran 5h as well but it had 3 errors. A 1, 12 and 8. All 3 according to the Google docs sheet are basically related to "something ending too quickly" so I assume 240 tRFC is too tight at 1T. I'll drop to 256 and call it a day there.


----------



## ElysianCloud

So at 3800 / 1900 I got one whea error in over an hour of playing Cyberpunk. This is with 1.15 VSOC and 0.925 on the VDDGs / VDDP. Nothing else is making it throw a whea error. 

Do one of you think more SOC voltage or more of one of the other voltages is gonna be the key?


----------



## The_King

ElysianCloud said:


> So at 3800 / 1900 I got one whea error in over an hour of playing Cyberpunk. This is with 1.15 VSOC and 0.925 on the VDDGs / VDDP. Nothing else is making it throw a whea error.
> 
> Do one of you think more SOC voltage or more of one of the other voltages is gonna be the key?


The two main voltages are VSOC and specifically IOD in regards to WHEA. 
If you have only 1 WHEA after 1 hour then you probalbly only need a small bump in 1 of those to be stable.
I would think it would be IOD rather the VSOC in your case.


----------



## mongoled

Imprezzion said:


> Not 1T GDM Off but I needed a baseline for 3800 first for primary timings and FCLK stability. Got WHEA's if I lower vSOC / IOD any more then this. CCD and VDDP might be able to go lower but haven't tried yet. This is a LOT lower then 1966 that's for sure. vDIMM is set to 1.565v as this is what I had to run on 11900K for tCL 14 with this low of a tRFC on 3800 but maybe it can also be lowered slightly? I also forgot to set tRCDWR lower to like 8 but k. You don't have that either . I might throw SCL's to 2 since I run 2 DIMM's maybe? DIMM's are hotter then i'd like as it's only 17c ambient here now. In the summer this would be far too hot to remain stable without raising fan speeds on my Dominator Airflows or running no sidepanel i'm guessing.
> 
> Now that I have a stable baseline for 3800/1900 I can tweak further from here and see if I can get 1T GDM Off to work with this.
> 
> View attachment 2582119
> 
> 
> EDIT:
> 
> Well, you were right. On 3800 1T GDM Off works fine so far with just AddrCmdSetup 56 and a bit more ClkDrvStr even on this not-so-great board! I'll let the test run overnight but it seems very very promising. No more errors within 3 minutes. Only thing I noticed is that tPHYRDL went from 26/28 to 28/28 with 1T GDM Off. Probably not a problem..?
> 
> View attachment 2582127


Search for posts from Audioboxer and domdtxdissar regards timings for your DR B-die, there are some subtle changes compared to my SR Vipers that you need to apply, I dont know these from the top of my head hence my pointing you towards their results.

Good to see you have made some headway, myself personally, I test each stick independently to see if they clock similarly, in this way I know before pairing them what they can do, helps later troubleshooting knowing this information


----------



## Priller

Imprezzion said:


> My B2 5900X had a 1900 hole as well but 1933 ran perfectly fine. 1.25 vSOC, 1.1 CCD, 1.05 IOD, 0.950 VDDP. I had it on a B550-XE which I still regret selling..
> 
> 3800C14 1T GDM Off ran 5h as well but it had 3 errors. A 1, 12 and 8. All 3 according to the Google docs sheet are basically related to "something ending too quickly" so I assume 240 tRFC is too tight at 1T. I'll drop to 256 and call it a day there.


I couldn't remember if I tried vsoc that high so a quick test and no joy.


----------



## byDenoso

Iarwa1N said:


> Increase ClkDrvStr to 30ohm: didn't work, but 40ohm worked


When i say increase, isfrom 40ohm to 60ohm
It will improve the powering in your DIMMS.


----------



## KedarWolf

Deleted c wing thread.


----------



## Anhphe93

ElysianCloud said:


> So at 3800 / 1900 I got one whea error in over an hour of playing Cyberpunk. This is with 1.15 VSOC and 0.925 on the VDDGs / VDDP. Nothing else is making it throw a whea error.
> 
> Do one of you think more SOC voltage or more of one of the other voltages is gonna be the key?


Sometimes the problem can also be caused by the motherboard. Same cpu and ram i need to 1.125v vsoc without WHEA error on B550F-Gaming. but i only need 1,040v vsoc on B550 NZXT. So weird. The current configuration I have been using for over a month after changing to a new motherboard.


----------



## 97pedro

Hello everyone,

So I had my 5950x running on a Crosshair VII Hero but I needed another pc, so I got a Dark Hero for the 5950x and the Vii Hero got a brand new 5800X.

Problem is, I can't for the life of me boot at 1900mhz fclk, 1866 will work, 1933 will work, but 1900 won't.

1933 has WHEA errors so it's a no go..

I think this is called the 1900Mhz hole from what I read online. The Vii hero I have has run 3700x at 1900Mhz, it had a 5800x at launch with 1900mhz and the 5950x until recently also used 1900Mhz.

Brand new 5800x with the exact same Bios and exact same Ram can't boot 1900Mhz.

Is there any workaround here?

Thanks!


----------



## Imprezzion

97pedro said:


> Hello everyone,
> 
> So I had my 5950x running on a Crosshair VII Hero but I needed another pc, so I got a Dark Hero for the 5950x and the Vii Hero got a brand new 5800X.
> 
> Problem is, I can't for the life of me boot at 1900mhz fclk, 1866 will work, 1933 will work, but 1900 won't.
> 
> 1933 has WHEA errors so it's a no go..
> 
> I think this is called the 1900Mhz hole from what I read online. The Vii hero I have has run 3700x at 1900Mhz, it had a 5800x at launch with 1900mhz and the 5950x until recently also used 1900Mhz.
> 
> Brand new 5800x with the exact same Bios and exact same Ram can't boot 1900Mhz.
> 
> Is there any workaround here?
> 
> Thanks!


Not really. The hole depends on the CPU not the board in most cases. 1933 might work with enough VDDG IOD (~1.15v) and vSOC (~1.25v) but no guarantees it will fix all the WHEA errors.


----------



## RackarN

guess this is the sweetspot for my daily settings, could probably tweak a bit more but it's rock solid so i rather not since it wont give any more performance in games  
TRFC could probably go lower
tWTR_ can probably be tweaked to 4/8 but i get 1 random error
tRDWR & tWRRD can probably go down somewhat.

im pleased that i was able to get GDM off + 1T working


----------



## Imprezzion

Weird.. how what why help haha. 

3800 14-16-14-28-256-1T GDM Off.
57k read 30.8k write 55.5k copy 60.2 latency.

3933 16-16-16-36-272-1T GDM On.
58.8k read 31k write 57.6k copy 59.2 latency.

How in the name of... can my 1T 3800 profile perform SO bad. It also has loads of stuttering and FPS drops in games where as the 3933 profile is incredibly smooth.


----------



## Jeffrey Kistler

3900x with 3800cl14 still fine after a year at 1.52v with a fan on top of gpu


----------



## RackarN

Imprezzion said:


> Weird.. how what why help haha.
> 
> 3800 14-16-14-28-256-1T GDM Off.
> 57k read 30.8k write 55.5k copy 60.2 latency.
> 
> 3933 16-16-16-36-272-1T GDM On.
> 58.8k read 31k write 57.6k copy 59.2 latency.
> 
> How in the name of... can my 1T 3800 profile perform SO bad. It also has loads of stuttering and FPS drops in games where as the 3933 profile is incredibly smooth.


how's the IOD CCD voltages look? i got a pretty big boost setting it to 1.16 @ 2040 FCLK

Edit: also SOC voltage. I got Asus TurboV in windows so I'm playing around with it to see how much/little soc voltage i can get away with.

At 1.14 i only got 49000 read. At 1.2 i have 57461 and 8ns lower latency. So voltage sweetspot is a good thing to find. I'm still uncertain about IOD voltage but it seems to be around 40mv from soc


----------



## Mikel_Ertz

Need some help here. I am trying this timmings for mi micron E-DIE 3600 CL16 KIT 16x2 (32gb) and i am getting error 6 in 1usmusv3. 

Is purely related to the IMC (Can mean voltage is too high) ,
be if procODT, CLDO_VDDP or vSOC
~ it translates to "i couldn't even start transfering data, i crashed"
4-6x error 6 result in full bluescreen
- Error 5 then 6 is a timings missmatch between dimms
(Data mirror move)

0-0-0-6-6-6 (2nd cycle) Can be too low SCL with wrong tWRRD
*Single rare 6 (after time), fix RTT values or give it +1 vDIMM* This one!

6-6-6 at the very start , too high/low tCKE *
* start with this first

I think that the cause is that, since I only get 1 error in 15h what RTT should i try?


----------



## ttnuagmada

any tips on getting FCLK stable over 1900? Have a 5800x3D, can boot as high as FCLK 2000 but anything over 1866 throws WHEA. (1900 won't boot at all). tried 1.25v soc with no luck


----------



## Imprezzion

ttnuagmada said:


> any tips on getting FCLK stable over 1900? Have a 5800x3D, can boot as high as FCLK 2000 but anything over 1866 throws WHEA. (1900 won't boot at all). tried 1.25v soc with no luck


More IOD. Way more IOD. I don't know what you had it on but 1.15v should fix it. Lol.


----------



## ttnuagmada

Imprezzion said:


> More IOD. Way more IOD. I don't know what you had it on but 1.15v should fix it. Lol.


Are there any rules for setting it (within a certain mv of CCD or SOC etc) also, whats a safe max?


----------



## StevieRay2

ttnuagmada said:


> any tips on getting FCLK stable over 1900? Have a 5800x3D, can boot as high as FCLK 2000 but anything over 1866 throws WHEA. (1900 won't boot at all). tried 1.25v soc with no luck


Had the same issue on the same CPU, I gave up and stuck with 3733, nothing fixed it for me


----------



## 99belle99

I must be lucky with my 3700X to be hitting 1900MHz. I would be a bit annoyed if I got a 5800X3D and it couldn't hit that frequency like you guys.


----------



## Mr.Sunshine

Why are memory latencies so high with people's setups? I was under the impression lower was better.


----------



## StevieRay2

Mr.Sunshine said:


> Why are memory latencies so high with people's setups? I was under the impression lower was better.


From what I've seen it looks like Intel has lower latency compared to AMD, seen people with b-die in the 44ns


----------



## ttnuagmada

Mr.Sunshine said:


> Why are memory latencies so high with people's setups? I was under the impression lower was better.


Of course lower is better, it's just that low for a Ryzen is a lot higher than low for an Intel. I have a 5800x3D rig and a 10700K rig, and when tuned to the max, the Intel rig is in the high 30ns range while the AMD is in the high 50's, both using the exact same B-die kits.


----------



## Mr.Sunshine

ttnuagmada said:


> Of course lower is better, it's just that low for a Ryzen is a lot higher than low for an Intel. I have a 5800x3D rig and a 10700K rig, and when tuned to the max, the Intel rig is in the high 30ns range while the AMD is in the high 50's, both using the exact same B-die kits.


I realize the Intel systems have a lot lower latency but I would think Zen systems could get low 50s with some of the speed and timings I'm seeing. I'm sitting at 52.5ns @3866mhz with 14-15-14-28-42 with a 5800X/x470/32GB(8x4) setup. Some of these systems are running 4000mhz


----------



## The_King

Mikel_Ertz said:


> Need some help here. I am trying this timmings for mi micron E-DIE 3600 CL16 KIT 16x2 (32gb) and i am getting error 6 in 1usmusv3.
> 
> Is purely related to the IMC (Can mean voltage is too high) ,
> be if procODT, CLDO_VDDP or vSOC
> ~ it translates to "i couldn't even start transfering data, i crashed"
> 4-6x error 6 result in full bluescreen
> - Error 5 then 6 is a timings missmatch between dimms
> (Data mirror move)
> 
> 0-0-0-6-6-6 (2nd cycle) Can be too low SCL with wrong tWRRD
> *Single rare 6 (after time), fix RTT values or give it +1 vDIMM* This one!
> 
> 6-6-6 at the very start , too high/low tCKE *
> * start with this first
> 
> I think that the cause is that, since I only get 1 error in 15h what RTT should i try?
> 
> View attachment 2582625


Are those Auto settings for ProcODT and Rtt? Same RAM but ProcODT and RTT is not close at all.
In Most cases but not all RttNom is usually disabled on most of My Rev >E kits. You may just need a small increase in VDIMM to be stable though.









Don't run the settings below you may damage your RAM or CPU.


----------



## Taraquin

Bix said:


> For what it's worth I gave up on trying to stabilize above 3800 on my B2 5900x since the performance wasn't really scaling anyway. After really tightening my timings I'm now performing better at 3800 than I was at 4000 on my old B0 and I didn't need to go anywhere near as high as you do with SOC so you're eating into your boosting budget a lot more.
> 
> It's tempting to push FCLK but if it takes that much voltage to get rid of WHEA 19s then you might just be best off tightening everything up at 3800 - at the very least you'll be able to see if your performance scales above that. If it scales in spite of the WHEAs and is stable at lower voltages then you can always use @ManniX-ITA 's suppressor...


From my and a few others testing you must raise VDD18 voltage to get good scaling above 1900fclk. This increases temp and steals from the powerbudget. I chose to sacrifice 1-2% performance and running 3800cl15 vs 4000cl16 since I could lower SOC from 1.11 to 1.06v, IOD from 1.03v to 0.98v and VDD18 from 1.88v to 1.6v. The last one is over 5C temp during load. 

My CB23 now runs very silent maxing out at 69C and 11850p vs 76C and 11750p and quite a bit more noise with 4000cl16. I lost 6fps in SOTTR, 2sec in dram calc test and 1.5ns in aida, but wirth it in my opinion.


----------



## RackarN

Mr.Sunshine said:


> I realize the Intel systems have a lot lower latency but I would think Zen systems could get low 50s with some of the speed and timings I'm seeing. I'm sitting at 52.5ns @3866mhz with 14-15-14-28-42 with a 5800X/x470/32GB(8x4) setup. Some of these systems are running 4000mhz


Those that have B-die have better latency om AMD, by far.
Also we that run 5800X3D have higher latency (5-6ns more) because of the 3d cache. So for me with Micron + 5800X3D is kinda meh in terms of latency


----------



## Taraquin

Mr.Sunshine said:


> I realize the Intel systems have a lot lower latency but I would think Zen systems could get low 50s with some of the speed and timings I'm seeing. I'm sitting at 52.5ns @3866mhz with 14-15-14-28-42 with a 5800X/x470/32GB(8x4) setup. Some of these systems are running 4000mhz


At 4000cl16 1t gdm iff using +200 pbo I get 51.5ns in aida. Aida scales very well with ram speed even if you get throttling due to ram speed.


----------



## The_King

RackarN said:


> Those that have B-die have better latency om AMD, by far.
> Also we that run 5800X3D have higher latency (5-6ns more) because of the 3d cache. So for me with Micron + 5800X3D is kinda meh in terms of latency


There are two factors that can bring latency down in AIDA64. 1 is increase MT frequency and the second is increasing CPU frequency.
Even though 5800X3D have higher latency due to limited CPU clock frequency the 3D V-cache makes the latency hit irrelevant when gaming on that CPU.


----------



## RackarN

The_King said:


> There are two factors that can bring latency down in AIDA64. 1 is increase MT frequency and the second is increasing CPU frequency.
> Even though 5800X3D have higher latency due to limited CPU clock frequency the 3D V-cache makes the latency hit irrelevant when gaming on that CPU.


yeah it makes up for it while gaming no doubt  It might just be, as you say, the lower clock speeds that affects the latency the most and not the 3d v-cache. I tried 104 BCLK but after 2 hrs of testing last evening i realized that anything above 102.375 will give me lower scores in CB and AIDA. (still running 102 since that is bootable, anything above i had to set through Asus TurboV core)


----------



## Imprezzion

With 3933 16-16-16-36-52-272-1T GDM On I'm sitting around 59.2-59.4ns latency and performance is amazing in gaming. I have never had my PC feel this smooth in gaming in terms of frame consistency and overall smoothness. 

I would've liked if the CPU idled a little lower in terms of power consumption but that's not possible afaik. It runs around 25-28w idle. And that is with forced power saving profile and -30 CO. The 11900K could do around 13-17w on power saving profile with ring down bin enabled @ 800Mhz core and ring and 0.762v where as the AMD tends to idle more like 2200-3500Mhz around 0.98-1.006v.


----------



## Audioboxer

Taraquin said:


> From my and a few others testing you must raise VDD18 voltage to get good scaling above 1900fclk. This increases temp and steals from the powerbudget. I chose to sacrifice 1-2% performance and running 3800cl15 vs 4000cl16 since I could lower SOC from 1.11 to 1.06v, IOD from 1.03v to 0.98v and VDD18 from 1.88v to 1.6v. The last one is over 5C temp during load.
> 
> My CB23 now runs very silent maxing out at 69C and 11850p vs 76C and 11750p and quite a bit more noise with 4000cl16. I lost 6fps in SOTTR, 2sec in dram calc test and 1.5ns in aida, but wirth it in my opinion.


For me it's always been a case of is it worth it for daily or just for benchmarks?










My timings have been locked in for ages now, but more importantly it's how "low" in terms of voltage this can run versus all my attempts to go above 1900 FCLK. Most of which resulted in throwing disproportionate amounts of voltage at the CPU/motherboard eating into the power budget and still I found it near impossible to stabilise a 5950x above 1900 for anything other than running some benchmarks.

Pretty disappointed with the current AMD releases, so just sitting waiting right now for a while longer. Was tempted to go 13900k and have one last dance with this DDR4, but have held off even doing that. Though I might still go for it, such a shame how much DDR4 was held back by the 5900x/5950x. My out of sync adventures with this memory kit showed ridiculous promise even up to 4533mhz.


----------



## RackarN

Audioboxer said:


> For me it's always been a case of is it worth it for daily or just for benchmarks?
> 
> View attachment 2582812
> 
> 
> My timings have been locked in for ages now, but more importantly it's how "low" in terms of voltage this can run versus all my attempts to go above 1900 FCLK. Most of which resulted in throwing disproportionate amounts of voltage at the CPU/motherboard eating into the power budget and still I found it near impossible to stabilise a 5950x above 1900 for anything other than running some benchmarks.
> 
> Pretty disappointed with the current AMD releases, so just sitting waiting right now for a while longer. Was tempted to go 13900k and have one last dance with this DDR4, but have held off even doing that. Though I might still go for it, such a shame how much DDR4 was held back by the 5900x/5950x. My out of sync adventures with this memory kit showed ridiculous promise even up to 4533mhz.


Yeah I went up to 4759 mhz before i hit the wall. It was faster than my 1933 setup but when I got the 2040/4080mhz to run synced this was faster in every way. Was fun testing tho and I found the sweetspot for GDM OFF + 1T along the way. Lots learned on that rabbit hole! Now it's more work ahead tuning all voltages down on mem, IOD, CCD etc to make it more power efficient. 1.22 soc is needed tho, but everything is water-cooled so heat is a non-issue with 3 radiators.


----------



## Taraquin

Audioboxer said:


> For me it's always been a case of is it worth it for daily or just for benchmarks?
> 
> View attachment 2582812
> 
> 
> My timings have been locked in for ages now, but more importantly it's how "low" in terms of voltage this can run versus all my attempts to go above 1900 FCLK. Most of which resulted in throwing disproportionate amounts of voltage at the CPU/motherboard eating into the power budget and still I found it near impossible to stabilise a 5950x above 1900 for anything other than running some benchmarks.
> 
> Pretty disappointed with the current AMD releases, so just sitting waiting right now for a while longer. Was tempted to go 13900k and have one last dance with this DDR4, but have held off even doing that. Though I might still go for it, such a shame how much DDR4 was held back by the 5900x/5950x. My out of sync adventures with this memory kit showed ridiculous promise even up to 4533mhz.


If 2000fclk only needed a minor bump to voltages it could be worth it, but the VDD18-part is the major issue. It greatly affects temp and increases consumption slightly aswell.


----------



## Audioboxer

RackarN said:


> Yeah I went up to 4759 mhz before i hit the wall. It was faster than my 1933 setup but when I got the 2040/4080mhz to run synced this was faster in every way. Was fun testing tho and I found the sweetspot for GDM OFF + 1T along the way. Lots learned on that rabbit hole! Now it's more work ahead tuning all voltages down on mem, IOD, CCD etc to make it more power efficient. 1.22 soc is needed tho, but everything is water-cooled so heat is a non-issue with 3 radiators.


That VSOC really eats into the power budget so while it might help with synthetic benchmarks/multi-loads in the right environment, it's about how much does it restrict single core thread workloads if you care about things like gaming.

Basically, trying to thread the eye of a needle and make sure your overall performance is better for whatever tasks you actually run.

Out of sync is fun for benching/pushing the RAM, but the performance hit is just terrible in terms of latency. Latency still remains king for most actual PC uses.


----------



## ElysianCloud

B


Mr.Sunshine said:


> I realize the Intel systems have a lot lower latency but I would think Zen systems could get low 50s with some of the speed and timings I'm seeing. I'm sitting at 52.5ns @3866mhz with 14-15-14-28-42 with a 5800X/x470/32GB(8x4) setup. Some of these systems are running 4000mhz


Because you're running the Aida test in safe mode or with all apps force closed. Most people are booting their normal system and then running Aida.


----------



## ttnuagmada

Mr.Sunshine said:


> I realize the Intel systems have a lot lower latency but I would think Zen systems could get low 50s with some of the speed and timings I'm seeing. I'm sitting at 52.5ns @3866mhz with 14-15-14-28-42 with a 5800X/x470/32GB(8x4) setup. Some of these systems are running 4000mhz


Yeah, now that you mention it, I'm at 58-59ns with 3733 16-16-16-32. I'd figure some of these would be lower as well.


----------



## Mr.Sunshine

ElysianCloud said:


> B
> 
> Because you're running the Aida test in safe mode or with all apps force closed. Most people are booting their normal system and then running Aida.


Those numbers I posted are on normal boot. I'll post some screenshots when I get home later today. I was unaware of the latency hit on the X3D chips. I haven't really messed with tuning my system for probably well over a year so it sounds like I missed a lot of information people have posted since then. I just decided to start tinkering again and pushing things as much as I could. Trying to hold off on upgrading to Zen4 until all the bugs have settled out and prices come down.


----------



## RackarN

Audioboxer said:


> That VSOC really eats into the power budget so while it might help with synthetic benchmarks/multi-loads in the right environment, it's about how much does it restrict single core thread workloads if you care about things like gaming.
> 
> Basically, trying to thread the eye of a needle and make sure your overall performance is better for whatever tasks you actually run.
> 
> Out of sync is fun for benching/pushing the RAM, but the performance hit is just terrible in terms of latency. Latency still remains king for most actual PC uses.


True, it does but since the CPU is ok at 1.1v it perform better in games aswell. Never reached limitations thus far, i tested a few games just to make sure the 1% lows never was affected


----------



## The_King

So I have heard some people post in this thread I change my motherboard and my old settings are no longer working.

This got me thinking about things like mobo RAM topology and other things like the good (strong) slot vs bad (weaker) slot.

So one of my 4000 C19 kits absolutely refused to do above 3667/1833 GMD disabled 1T without AddrCmdSetup 56. I tried all and every setting I could. I was about to give up!









Solution to this after almost 2 weeks of testing was very simple. (ignore the 1 random error this thing use to spew errors out before)
Can you guess what I did?












Spoiler: Answer



Swap the Dimms around!


----------



## Mr.Sunshine

Here are my 24/7 core cycle/ memtest stable benches.


----------



## Nd4spdvn

ttnuagmada said:


> any tips on getting FCLK stable over 1900? Have a 5800x3D, can boot as high as FCLK 2000 but anything over 1866 throws WHEA. (1900 won't boot at all). tried 1.25v soc with no luck


If you haven't already, you may try bumping the CLDO_VDDP for that 1900 IF hole, they say it can help. Alternatively, you can also try keeping the 1867 IF and RAM speed and raise the BUS clock from 100 to 102 which will give you 1904 IF and 4540MHz on the 5800X3D. I do the latter for a lil bit better proc performance as I have no issue booting at 1900 IF on my Giga board.


----------



## RackarN

The_King said:


> Spoiler: Answer
> 
> 
> 
> Swap the Dimms around!


HAHAHA thats odd! i had this in mind last evening.. made sure not to swap order of my RAM when i slapped on a waterblock on my sticks xD


100 rounds 1usmus 36,8 degrees max on the sticks (51 before without fan, 47 with fan)  Bought the DDR blocks years ago but never used it


----------



## Imprezzion

RackarN said:


> HAHAHA thats odd! i had this in mind last evening.. made sure not to swap order of my RAM when i slapped on a waterblock on my sticks xD
> 
> 
> 100 rounds 1usmus 36,8 degrees max on the sticks (51 before without fan, 47 with fan)  Bought the DDR blocks years ago but never used it



I thought about doing water on my sticks as well but my flow rate is low enough as it is.. any more blocks would basically mean I'd have to go dual pump as well. And that block + fittings + second pump + other dual pump res would be way too expensive to warrant the temperature decrease for me..

I am going to try out 2T GDM Off tonight at 3933 and see if the DIMM's will run straight 15's. I have my doubts but we'll see. 1T is impossible at 3933 unfortunately on my board / RAM. 3800 is max for 1T.


----------



## RackarN

Imprezzion said:


> I thought about doing water on my sticks as well but my flow rate is low enough as it is.. any more blocks would basically mean I'd have to go dual pump as well. And that block + fittings + second pump + other dual pump res would be way too expensive to warrant the temperature decrease for me..
> 
> I am going to try out 2T GDM Off tonight at 3933 and see if the DIMM's will run straight 15's. I have my doubts but we'll see. 1T is impossible at 3933 unfortunately on my board / RAM. 3800 is max for 1T.


Yeah, i have a 2nd pump aswell that i bought 2nd hand. so 3 rads, 2 pumps, 3 blocks (thinking of the chipset aswell since i have a block) Would never work on 1 pump 

1T for me was hard, all DrvStr and RTT's had to have the correct values.. just got lucky when i tried high mem clocks.


----------



## Imprezzion

RackarN said:


> Yeah, i have a 2nd pump aswell that i bought 2nd hand. so 3 rads, 2 pumps, 3 blocks (thinking of the chipset aswell since i have a block) Would never work on 1 pump
> 
> 1T for me was hard, all DrvStr and RTT's had to have the correct values.. just got lucky when i tried high mem clocks.


I now run a EK Velocity D-RGB CPU block, a Bykski full cover GPU block, a Nemesis GTX420 front mounted with the tubing on top and a Nemesis GTX240 in the bottom. The pump is a single D5 PWM (Sleeved version) with an EK X-Res Revo 140. It holds up on max PWM but only just. It doesn't have the best flow because it has to push the water all the way up to the top of the rad but it's sufficient. 

I had a hard time getting 1T GDM Off to run at all but with the correct RTT and ClkDrvStr it runs fine up to 3800 and while it does boot higher it won't stabilize. Throws error #6 and #0 almost instantly regardless of RTT or DrvStr's at 3867 or 3933. I think I'm just at the max of my cheap-o B550 board. 1T GDM On works fine at 3933 but won't allow me to run tCL 15 and tCL 14 is too tight for my bad B-Die bin at 3933.


----------



## RackarN

@Imprezzion Hmm.. went to bios and turned GDM on i a attempt to ease your mind. I was supposed to say that it probably don't make that much of an impact running GDM on + T1 vs OFF but i was corrected pretty fast .


















The safe mode one tho  my win is pretty bloated it seems


----------



## Imprezzion

RackarN said:


> @Imprezzion Hmm.. went to bios and turned GDM on i a attempt to ease your mind. I was supposed to say that it probably don't make that much of an impact running GDM on + T1 vs OFF but i was corrected pretty fast .
> View attachment 2583023
> View attachment 2583024
> View attachment 2583025
> The safe mode one tho  my win is pretty bloated it seems


GDM 1T is pretty much just GDM Off 2T speed wise. It makes very little difference for me. Around 59.4 on 3933C16 GDM 1T and 59.6 2T so margin of AIDA error. But, it passed 5h with 1T GDM On so at least I know it's stable so I keep that profile saved in the BIOS as a fallback. I know 3933 16-16-16-36-52-272 is quite conservative on DR B-Die but it's the best that would stabilize that day and I wanted to actually use my PC and not just stress test all week. 

The thing is, I have had these DIMM's since late '19 on my 9900K and later 10900K and 11900KF and I know what they should be able to do but still they refuse to run the timings I ran on Intel on either the 5900X + B550-XE or the 5800X3D + B550-A. AMD is quite different so it seems. I used to run 4266 15-17-17-35-280-2T on the 9900K/10900K @ 1.59v so with proper scaling in mind that should mean 3933 14-16-16 should easily run even at 1.55v but it doesn't. At all. tCL 14 barely even boots to windows without BSOD's at any vDIMM...


----------



## vegetagaru

hello all 
some time ago i came here to get better timings on my ram it worked out stable but wanted to make them a bit tigh but couldn't achieve anything (or they dont boot or just crash xD)
my kit is: F4-4400c17D-32GVK and the actual timmings are:








latency @ aida is around 60.9/61

i wanted to place them at cl14, could you guys point me a profile or help me on this one ? i saw some at 14-15-14-28 but ended up with more latency probably because of the other timings


----------



## Imprezzion

vegetagaru said:


> hello all
> some time ago i came here to get better timings on my ram it worked out stable but wanted to make them a bit tigh but couldn't achieve anything (or they dont boot or just crash xD)
> my kit is: F4-4400c17D-32GVK and the actual timmings are:
> View attachment 2583036
> 
> latency @ aida is around 60.9/61
> 
> i wanted to place them at cl14, could you guys point me a profile or help me on this one ? i saw some at 14-15-14-28 but ended up with more latency probably because of the other timings


Keep all the secondary and tertiary timings as you have, set tWR to 10 tRTP 5, tRFC 256, tCWL 14, primary 14-15-14-28, 42 tRC, should be fine on that high of a bin at what, 1.55v ish?


----------



## vegetagaru

Imprezzion said:


> Keep all the secondary and tertiary timings as you have, set tWR to 10 tRTP 5, tRFC 256, tCWL 14, primary 14-15-14-28, 42 tRC, should be fine on that high of a bin at what, 1.55v ish?


ty for reply i will try it later and give feedback, atm i have set at 1.5 should i increase it so for 1.55 ?


----------



## vegetagaru

Imprezzion said:


> Keep all the secondary and tertiary timings as you have, set tWR to 10 tRTP 5, tRFC 256, tCWL 14, primary 14-15-14-28, 42 tRC, should be fine on that high of a bin at what, 1.55v ish?


i still didnt increased the voltage, so here are my results:










still need to test stability x)


----------



## The_King

vegetagaru said:


> i still didnt increased the voltage, so here are my results:
> 
> View attachment 2583228
> 
> 
> still need to test stability x)


Since you dropped CL and tCWL to 14 RDWR can probably got to 8 maybe even 7.
You mostly likely may need to increase voltages to be stable but that will depend on how good your B-die bin is.


----------



## Imprezzion

The_King said:


> Since you dropped CL and tCWL to 14 RDWR can probably got to 8 maybe even 7.
> You mostly likely may need to increase voltages to be stable but that will depend on how good your B-die bin is.


I didn't advise this at first because on my mediocre bin I can't go below 9 at 1.56v or below 10 at any lower voltage so. Just for the sake of stability testing i'd leave it pretty high first. But yes, for maximum performance you should drop this as well @vegetagaru

I fixed my stuttering issues at 3800 14-15-14-28-42-256-1T GDM Off. You guys were right. It was too low CCD/IOD. I raised them from 0.940 CCD 0.960 IOD to 0.960 CCD 0.980 IOD and the stuttering and inconsistent CPU bench scores are gone now. I was ever so slightly too low lol. vSOC for 1900 is still 1.100 (1.081 load) and 0.880 CLDO VDDP. No WHEA's. The board still isn't very happy with 1T GDM Off and needs AddrCmdSetup 56 and precisely tuned RTT and ClkDrvStr to run 1T at all and it will not work above 3800 but this is fine for now. Better then 3933 16-16-16 2T at least latency wise.


----------



## ReyReverse

vegetagaru said:


> i still didnt increased the voltage, so here are my results:
> 
> View attachment 2583228
> 
> 
> still need to test stability x)


2T ClkDrvStr probably can do 30ohm. 
round up tRAS to 36 tRC 50
trfc go 250 186 114
see the latency got do better?


----------



## vegetagaru

ReyReverse said:


> 2T ClkDrvStr probably can do 30ohm.
> round up tRAS to 36 tRC 50
> trfc go 250 186 114
> see the latency got do better?


thank you all for the reply's i will be a bit busy this days but once the weekend comes i will test that stuff around and post some feedback


----------



## vegetagaru

ReyReverse said:


> 2T ClkDrvStr probably can do 30ohm.
> round up tRAS to 36 tRC 50
> trfc go 250 186 114
> see the latency got do better?


managed to get free time 
so with those timings it went up 










*___*


@Imprezzion @The_King so i droped the RDWR to 8 and raised to 1.52 (couldnt get it with 7 even at 1.55 so i gave up xD )

need to test stability


----------



## MrHoof

vegetagaru said:


> managed to get free time
> so with those timings it went up
> 
> View attachment 2583288
> 
> 
> *___*
> 
> 
> @Imprezzion @The_King so i droped the RDWR to 8 and raised to 1.52 (couldnt get it with 7 even at 1.55 so i gave up xD )
> 
> need to test stability


also lower tWRRD to 3 should work with tRDWR 8
Edit: had a total brainfart while posting this now its fine 😵
edit2:
tRDWR 7 can work but for most limit is 8 and i cant tell u why.


----------



## ReyReverse

vegetagaru said:


> managed to get free time
> so with those timings it went up
> 
> View attachment 2583288
> 
> 
> *___*
> 
> 
> @Imprezzion @The_King so i droped the RDWR to 8 and raised to 1.52 (couldnt get it with 7 even at 1.55 so i gave up xD )
> 
> need to test stability


Then you remain your previous timings . But Clkdrvstr keep 30ohm


----------



## Priller

Replacement 5900X IMC is much better and boots 3800/1900 no problem. Only 1 error on test 11 during a quick test.
Same settings as I was using before and the impossible is now no sweat.


----------



## 97pedro

Well This is the best I can do with 3733mhz.

Any one has settings I can try for 3866mhz? My 5800X has the 1900Mhz fclk hole, so that's a no go.


----------



## The_King

97pedro said:


> Well This is the best I can do with 3733mhz.
> 
> Any one has settings I can try for 3866mhz? My 5800X has the 1900Mhz fclk hole, so that's a no go.
> 
> View attachment 2583360


Does your board also fail to boot with 2 DIMM sticks at FCLK 1900?
Some boards have trouble going above 1900 FCLK with 4 DIMMS.
I cant do FCLK 1933 on both my boards with Sumsung B-die with 4XDIMMS but can go up to 4133 with Micron Rev E/B.

Are you running 4.9Ghz all core load 24/7 stable or just for benching ? If its stable please run R23 @ 4.9Ghz and post the results.


----------



## 97pedro

The_King said:


> Does your board also fail to boot with 2 DIMM sticks at FCLK 1900?
> Some boards have trouble going above 1900 FCLK with 4 DIMMS.
> I cant do FCLK 1933 on both my boards with Sumsung B-die with 4XDIMMS but can go up to 4133 with Micron Rev E/B.
> 
> Are you running 4.9Ghz all core load 24/7 stable or just for benching ? If its stable please run R23 @ 4.9Ghz and post the results.


It's not the boards fault, the board had been running a 5950x for 1 year at 1900mhz fclk with the same 4 dimms. I just swapped the 5950x to a dark hero and the 7 hero got a 5800x.

I'm running 4.9 all core 24/7 but I don't use SMT, since I don't do any work with any of my PCs and the purpose is only gaming, it's better for me to turn off smt.


----------



## ElysianCloud

So I noticed a strange behavior, I can play and stress test my system and it will be stable all day at 3800/1900, but if my PC goes to sleep and I wake it, it'll throw hundred of whea errors in a minutes.

What causes this?


----------



## dimkatsv

Small, but not simple question.
I have 5600X, B550M Aorus Elite mobo, and 2x 2R16 H8D RAM 3600 16-20-20 rated sticks...
And i have an issue.
I can run 3800 frequency with 16-20-20. I can run it even with -1 each timing (except tRCDRD, this one is stubborn af). Technically at least. They can become unstable without more tweaking.
Now to the problem. I cannot loosen up primaries except tRAS or tRC. If i even dare to set them even to +1 or +2 from default XMP - system won't boot. More than that i will be forced to hard shutoff system and reset CMOS.
I can get decently tight timings to be stable even at 3800 with 1.5V (actual 1.512 it seems). anything below will throw errors in test 0 on test 6 or errors on test 7 in Anta ABSOLUT config.


Spoiler














Running 3600 XMP or even with tigher setup with 1.35 (actual is 1.38) is fine though. While even if i am able to boot 3800 16-20-20 with 1.4V+ set, it only becomes that stable at 1.5.
I thought i can just loosen up one of the tricky timings just tiny bit to reduce required boltage... But as i already said... SYSTEM JUST DOESN'T BOOT! And i have no idea why it won't accept loosened timings!
So either answer will be fine.
Is 1.5V (1.512) daily on H8D fine?
Or... Anyone have ideas why i am unable to boot if i loosen up timings?


----------



## Imprezzion

I am genuinely questioning my Windows install now lol.
I am getting these AIDA results repeatable on a full normal boot. They really, really do not look good to me comparing to some of you guys.. Especially RAM..










Running -30 CO on the CPU and RAM at this (1.56v vDIMM):


----------



## Priller

@Imprezzion As an experiment. Try taking CO to -15 and rerunning? And will it run with Addrcmdsetup at 0?


----------



## dimkatsv

Imprezzion said:


> Running -30 CO on the CPU


How sure are you this is stable for you?
Try to run CoreCycler for SSE HeavyShort preset. I also thought i can run all core -30. Until it suddenly became -22/-15/-15/-22/-22/-30


----------



## The_King

Most 5800X3Ds can do -30 on all cores because they don't run high clock frequencies like 5800X for example.
In most cases I have seen almost all 5800X3D can run very stable with -30 all core but its always best to test CO for stability.

You can check your scores in R23 with different CO settings and if your losing points at -30 vs -25 vs -15 all core then you need to adjust that.
Then you have to check if that -30 all core is stable in Y-cruncher 2.5B.

Most of the time its a 3rd party app running in windows that causes the latency issues. RGB software CPUZ even HWINFO can add latency to your AIDA64 results.
I get 1-2ns lower by just disconnecting my wifi from the internet in AIDA64.


----------



## Imprezzion

Priller said:


> @Imprezzion As an experiment. Try taking CO to -15 and rerunning? And will it run with Addrcmdsetup at 0?


It will not do 1T GDM Off with AddrCmdSetup 0. 1T GDM On or 2T Off is fine. But latency goes to 60.8ns ish. On my other profile, 3933 16-16-16-36-52-272-1T GDM On latency is also low 59's but a bit more bandwidth but I need loads more vSOC and CCD IOD to run 1967 FCLK without WHEA's so not worth it. 

The CPU ran 14h of corecycler stable and scores in both CPU-Z and CB R23 are fine with -30. I dropped all the way to -23 on all cores, the highest I can go without losing 4450 all core boost, and the scores were identical in all benches (151xx in R23 and 6440 in CPU-Z). At -15 I lose clockspeed and it drops to 4375 ish and scores 148xx in R23 and 6380 in CPU-Z so it seems fine. 

I am grabbing a new boot M.2 with black friday sales, probably a WD SN850X 2TB, and going for a full fresh install of W11 22H2 as this is a super old Insider Build install that has been upgraded to 22H2 and ran on 4 different boards and CPU's including 2 Intel's without a reinstall and that does seem to cause issues with AMD CPU's plus it's bloated as can be with lots of random software (and startallback). I might do a safe mode test after work today to see how much of a difference that makes. 

Will also probably pick up a NZXT N7 B550 from Amazon as it just dropped to 169.99 and I know how you guys feel about the NZXT boards but a mate wants to upgrade his aging 8600K rig so I wanna sell him my B550-A and pick up a 5800X3D for him as well. The N7 at least has a USB-C header, dual 2.5g lan, WiFi, all stuff my board misses. Even tho it's just a AsRock Steel Legend with a sticker and a bunch of plastic.


----------



## The_King

A practical example of how I got WHEA 19s to stop.

VSOC Auto and VDDGs Auto @ 3933 FCLK 1967 = WHEA city! 









VSOC 1.2375V and IOD 1.15V = No more WHEA


----------



## 99belle99

Imprezzion said:


> I am genuinely questioning my Windows install now lol.
> I am getting these AIDA results repeatable on a full normal boot. They really, really do not look good to me comparing to some of you guys.. Especially RAM..
> 
> View attachment 2583474
> 
> 
> Running -30 CO on the CPU and RAM at this (1.56v vDIMM):
> View attachment 2583475


Have you compared to other 5800X3D's? As someone mentioned the X3D have more latency than a 5800X.


----------



## Priller

The_King said:


> A practical example of how I got WHEA 19s to stop.
> 
> VSOC Auto and VDDGs Auto @ 3933 FCLK 1967 = WHEA city!


Is SOC and IOD safe at that range? I thought 1.2 VSOC, but i dont remember hearing a limit for CCD voltage.


----------



## The_King

Priller said:


> Is SOC and IOD safe at that range? I thought 1.2 VSOC, but i dont remember hearing a limit for CCD voltage.


AMD recommend 1.2V max for VSOC when Ryzen was first released if i recall correctly.
Many on here have been running 1.2-1.25V daily with ZEN 3 and say they have had no problems.

I ran up to 1.25V without any issues but I still run 3800MT and 1900 FCLK for daily with VSOC Auto (1.1V), So overclocking has its risk.
I think if you have decent cooling it should not be a problem. I would not go over 1.25V VSOC myself for a daily setup..

You can find more detailed info here.





Infinity Fabric Overclocking on Zen2/3







docs.google.com


----------



## Imprezzion

Well, the NZXT N7 B550 is ordered. Let's see if Amazon actually had them in stock and I get it next week. Then I'll be quite curious to see how it compares to the ASUS B550-A for memory OC. And to a lesser extend if the CPU will still run -30 fine. Mind you, I bought that specific board purely for looks and the 2.5G LAN, Wifi 6 and USB-C header support. Not for the performance. 

Also picked up a 980 Pro 1TB on early black friday sale. The B550-A and my old 970 Evo 500GB will go to a friend's brother with another new 5800X3D. He just has cringe RAM tho. 4x4 3000C15 lol. It'll have to do for now.


----------



## Priller

The_King said:


> AMD recommend 1.2V max for VSOC when Ryzen was first released if i recall correctly.
> Many on here have been running 1.2-1.25V daily with ZEN 3 and say they have had no problems.
> 
> I ran up to 1.25V without any issues but I still run 3800MT and 1900 FCLK for daily with VSOC Auto (1.1V), So overclocking has its risk.
> I think if you have decent cooling it should not be a problem. I would not go over 1.25V VSOC myself for a daily setup..
> 
> You can find more detailed info here.
> 
> 
> 
> 
> 
> Infinity Fabric Overclocking on Zen2/3
> 
> 
> 
> 
> 
> 
> 
> docs.google.com


That doc is handy to have. I had accidently stumbled across some of the reduced voltages because I couldn't get 3866/1933 stable. So I went the other way to see how low I could go with voltages to get a better idea of which voltage did what. Unsurprising, most default voltages are just way too high.


----------



## Bloax

Priller said:


> Unsurprising, most default voltages are just way too high.


Most common "default" voltage is 1.1v on all rails










for reference then 1600 FCLK has a decent voltage tolerance, and will probably perform very well at 1.0vSOC, 0.9vIOD and 0.8vCCD - while VDDP at ddr4-3200 requires laughably low voltages

1.1v is very high on IOD/CCD even for >1900 FCLK, usually not seen until you get to >2000 - and even DDR4-5000 doesn't require 1.1 VDDP 🤡 🤡 🤡


----------



## Nighthog

Bloax said:


> Most common "default" voltage is 1.1v on all rails
> View attachment 2583779
> 
> 
> 
> for reference then 1600 FCLK has a decent voltage tolerance, and will probably perform very well at 1.0vSOC, 0.9vIOD and 0.8vCCD - while VDDP at ddr4-3200 requires laughably low voltages
> 
> 1.1v is very high on IOD/CCD even for >1900 FCLK, usually not seen until you get to >2000 - and even DDR4-5000 doesn't require 1.1 VDDP 🤡 🤡 🤡


VDDP requirements go up really a lot when you hit 5200+ as you hit the limits of the memory controllers in the IOD.
Depending on the chip not even 1.200V++ might work to boot. 

my old 3800X needed minimum 1.200V VDDP to boot 5200Mts. My 5800X3D can't do it at all whatever the voltages I tried.


----------



## Akex

Do you have a B550 & Zen3 compatible version of MemTweakIt? At least to see the timings not visible with Zentiming, not necessarily to apply parameters on the fly. The latest version posted by @Veii no longer works.


----------



## Veii

Akex said:


> Do you have a B550 & Zen3 compatible version of MemTweakIt? At least to see the timings not visible with Zentiming, not necessarily to apply parameters on the fly. The latest version posted by @Veii no longer works.


----------



## Akex

Thanks veii, this is the version I'm already using, this is what I get.
For all to quickly explain, I am stabilizing a small 4933Mhz async to be sure that the RAM does not pose any problem, according to the training of the memory, I do not spend more than 30 cycles TM5 or 9000% Kharu, whereas there Next, I just validated 10H of Kharu at more than 22000% and 80 Cycle TM5
, so I wanted to see what can cause this phenomenon.








Edit:
When I have errors, it's error 14 or 0 that pops up once every 20 cycles more or less.
I mounted tRDWR to 11 instead of 10 and there I was able to validate the 10h Kharu and 80 Cycle 1usmus_v3.


----------



## Veii

Akex said:


> Thanks veii, this is the version I'm already using, this is what I get.


Try this:
~maybe too new~
APU support was an issue

Please post log file of it


----------



## Akex

Veii said:


> Try this:
> ~maybe too new~
> APU support was an issue
> 
> Please post log file of it


Always the same









Thanks for your time and help
I'm afraid I have to do without

Edit: To your knowledge, is there another solution so that I can see the entire RAM configuration so that I am compared between two cold reboots?


----------



## Valka814

Something went wrong. Without Curve Optimiser:









With Curve Optimiser:










A did test a lot CO values, with variable load and different load types like SSE, AVX, AVX2, single core, all core.
VDD18 was lowered in the 2nd stability test, but with auto value, GTA V still crashing, so not the main source or source at all of the problem.


----------



## deedeeDMT

Bit of a small question, but if I have a stable 3800 cl14 (fan) and a 3800 cl16 (fanless) 4x8 b-die config is there anything else I can do asides from trying to push for higher FLCKs if I start WHEA 19-erroring past 1900? I tried it before but that was when I was OCing to 3800mhz and I wanted to play it safe.


----------



## Nighthog

Veii said:


>


This software works with other vendors?

Surprised it shows me everything on my Aorus Xtreme.
EDIT: You can't change anythigng though, just view your settings.


----------



## The_King

Nighthog said:


> This software works with other vendors?
> 
> Surprised it shows me everything on my Aorus Xtreme.
> EDIT: You can't change anythigng though, just view your settings.


Works on my MSi board too. Settings I have never seen before.  but can't change anything!


----------



## Artylol

I'm noob, it is my first system and I just downloaded (lol) ram OC from internet. My setup is B550 Aorus pro AC, Ryzen 5 5600 (non x) stepping B2, RAM Patriot Viper Steel 4000 CL16. Dont pay attention to IF clock, it is intentionally uncoupled because IF2000 gives WHEA's. I have 3 issues:

1) tWTRL=8 causes anta777 errors.
2) Cant boot CL14 even at 1.5V VDIMM. tRCD and tRP reduces effortlesly
3) tRTP cannot be set to 5. If I set it to 5, it shows 6 in ZenTimings.

Please advice what I'm doing wrong and if possible how to further improve timings for performance. Current setup passes 20-30 minutes of anta777. Also note I have 5 bucks cooler which idles CPU at 60 degC, while waiting for Noctue D15 from aliexpress.









Edit: Sharing IF2000 results with proper voltages


----------



## ManniX-ITA

https://www.amd.com/en/support/chipsets/amd-socket-am4/x570



New chipset drivers 4.11.15.342.

"Bug fixes": https://www.amd.com/en/support/kb/release-notes/rn-ryzen-chipset-4-11-15-342

Some BSODs fixed on both Win10 and Win11


----------



## The_King

ManniX-ITA said:


> https://www.amd.com/en/support/chipsets/amd-socket-am4/x570
> 
> 
> 
> New chipset drivers 4.11.15.342.
> 
> "Bug fixes": https://www.amd.com/en/support/kb/release-notes/rn-ryzen-chipset-4-11-15-342
> 
> Some BSODs fixed on both Win10 and Win11


Some weird behavior I have notice when installing the AMD chipset drivers.
Always check your Install log after the install is completed.

On several occasions I found that some components do not upgrade on the first install but actually fail.

Only when you run the installer for a second time after reboot do the failed components install correctly. On the first install AMD Processor Management Support and AMD PCI device Drivers failed to install.

This is the install log after running the installer again after a reboot.


----------



## 99belle99

The_King said:


> Some weird behavior I have notice when installing the AMD chipset drivers.
> Always check your Install log after the install is completed.
> 
> On several occasions I found that some components do not upgrade on the first install but actually fail.
> 
> Only when you run the installer for a second time after reboot do the failed components install correctly. On the first install AMD Processor Management Support and AMD PCI device Drivers failed to install.
> 
> This is the install log after running the installer again after a reboot.
> View attachment 2584599


Mine installed correctly first time. I never usually check but decided to after you mentioned it and they all had success.


----------



## The_King

What are you guys with 5800X getting in Y-cruncher with AIR or water cooled setups? This is with my Micron DR Ram I'm sure Samsung B-die will shave this time off abit maybe 1 to 2 seconds?

Winter is coming so time to go for some PB scores on HWBOT. Any advice is welcome from all.


----------



## ManniX-ITA

The_King said:


> What are you guys with 5800X getting in Y-cruncher with AIR or water cooled setups? This is with my Micron RAM DR Ram I'm sure Samsung B-die will shave this time off abit maybe 1 to 2 seconds?
> Winter is coming so time to go for some PB on HWBOT. ANy advice is welcome form all.











Gunzi`s y-cruncher - Pi-2.5b score: 1min 32sec 159ms with a Ryzen 7 5800X


The Ryzen 7 5800X @ 4650.3MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. Gunziranks #71 worldwide and #7 in the hardware class. Find out more at HWBOT.




hwbot.org





If you want to score on y-cruncher could be easier with Micron.
Check the #1 ranking 5800X, it's using 5500 MHz static OC at memory clock 3800 MHz CL14.

While the #2 is just 4825 MHz CPU but with un-sync memory clock 4700 MHz CL16.








Antifreeze`s y-cruncher - Pi-2.5b score: 1min 29sec 546ms with a Ryzen 7 5800X


The Ryzen 7 5800X @ 4836.4MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. Antifreezeranks #64 worldwide and #2 in the hardware class. Find out more at HWBOT.




hwbot.org





The #3 is 200ms slower with 4925 MHz and memory clock 3800 MHz CL13.








mickulty`s y-cruncher - Pi-2.5b score: 1min 29sec 776ms with a Ryzen 7 5800X


The Ryzen 7 5800X @ 4925.1MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. mickultyranks #65 worldwide and #3 in the hardware class. Find out more at HWBOT.




hwbot.org





If you can get the clock above 5 GHz and un-sync memory at 4500+ then the #2 spot is yours.


----------



## Akex

Guys, I stupidly doubted the tRFC. I have the @anta777 formula but also what Veii explained here. In general I stick to the tRFC calculator of @Veii gDoc, but today for some reason that escapes me, I questioned myself, especially with the Anta777 formula. Concretely, my RAM doesn't seem to be able to be stable below 300ns around there anyway. To have the most optimal tRFC possible, do I have to do:

Anta777 = (((300ns*4933/2)+8-1)/8)x8+8 = 754.95

Or else tRC x 10 = 680 but is difficult to stabilize, in this case tRC x11 = 748 which will give me more than 300ns

But still, to have 300ns all round, it seems to me that it is tRFC 740.

So I have 3 possibilities available to me, but which one is the right one to use?


----------



## Imprezzion

Akex said:


> Guys, I stupidly doubted the tRFC. I have the @anta777 formula but also what Veii explained here. In general I stick to the tRFC calculator of @Veii gDoc, but today for some reason that escapes me, I questioned myself, especially with the Anta777 formula. Concretely, my RAM doesn't seem to be able to be stable below 300ns around there anyway. To have the most optimal tRFC possible, do I have to do:
> 
> Anta777 = (((300ns*4933/2)+8-1)/8)x8+8 = 754.95
> 
> Or else tRC x 10 = 680 but is difficult to stabilize, in this case tRC x11 = 748 which will give me more than 300ns
> 
> But still, to have 300ns all round, it seems to me that it is tRFC 740.
> 
> So I have 3 possibilities available to me, but which one is the right one to use?
> 
> View attachment 2584722


The "right" one should be 350ns as that is JEDEC spec. The other "right" one when overclocking is quite simply the lowest you can run. Nothing more complicated. I use 2x16 DR B-Die so I can run around 125-130ns (at 3800 I run either 240 or 256 tRFC).


----------



## The_King

ManniX-ITA said:


> If you can get the clock above 5 GHz and un-sync memory at 4500+ then the #2 spot is yours.


I seem to lose tons of time in Y-cruncher and Super Pi at and above 2000 FCLK, I can reach very high MT with my kits even 4800MT 2:1.

Problem is related to the VDD18 / CPU 1P8 no option to adjust that on my B450.

Contacted Reous told me I could try enabling myself with AMIBCP but have to cut the BIOS in half,
I have a 32MB (2x16MB) bios and have to cut it in the middle. The second part is for Ryzen 3000/4000/5000. First one for Ryzen 1000/2000
very clueless on that part is there any guide on here I can use to do this?

I have searched only found old guides related to X370 boards nothing about 32MB BIOS stuff.
I am familiar with AMIBCP and got this far on my own limited know how.


Spoiler: AMI BIOS


----------



## The_King

Imprezzion said:


> The "right" one should be 350ns as that is JEDEC spec. The other "right" one when overclocking is quite simply the lowest you can run. Nothing more complicated. I use 2x16 DR B-Die so I can run around 125-130ns (at 3800 I run either 240 or 256 tRFC).


Micron RAM can't do low TRFC like Samsung kits do with his kit around 300ns is safe and 280/290 ns is the lowest most kits will do without failing to post. Mines is running +/- 295ns in my above post.


----------



## Imprezzion

The_King said:


> Micron RAM can't do low TRFC like Samsung kits do with his kit around 300ns is safe and 280/290 ns is the lowest most kits will do without failing to post. Mines is running +/- 295ns in my above post.


How much of a net performance loss does that Micron tRFC actually have compared to Samsung?

I have another build in the works for a friend but we are re-using his old RAM for now which is 4x4GB Corsair Vengeance 3000C15 stuff from the Intel 8600K era. No idea what kinda chips they are but I am quite curious what I can push out of those. We'll be running a NZXT N7 B550 board and a 5800X3D.

Edit: it's 2 of these kits.


https://www.corsair.com/eu/en/Categories/Products/Memory/VENGEANCE-LPX/p/CMK8GX4M2B3000C15


----------



## The_King

Imprezzion said:


> How much of a net performance loss does that Micron tRFC actually have compared to Samsung?
> 
> I have another build in the works for a friend but we are re-using his old RAM for now which is 4x4GB Corsair Vengeance 3000C15 stuff from the Intel 8600K era. No idea what kinda chips they are but I am quite curious what I can push out of those. We'll be running a NZXT N7 B550 board and a 5800X3D.
> 
> Edit: it's 2 of these kits.
> 
> 
> https://www.corsair.com/eu/en/Categories/Products/Memory/VENGEANCE-LPX/p/CMK8GX4M2B3000C15


TRFC on Micron RAM does not impact performance in an big or significant way like on Samsung. You probably should not be running it too low with Micron. I have hardly seen much performance increase if any from lowering TRFC on my Micron kits. But big difference in my Samsung kits by lowering it.

Samsung B-die should always win since it can do the lower CL and RCDRD and TRFC with higher voltages. With Micron only CL scales with Voltage but not RCDRD


----------



## Akex

It's true that Microns don't have voltage scaling like BDIEs, and not just on tRFC as well.
But where I doubted about tRFC to be more precise, is can I define tRFC according to wanting 300ns or do I really have to follow a particular rule like Anta's or tRC*X.
In fact, I can do 295ns stable, that's what I have on the 4733C16 preset, but being at the extreme limit of my kit, I prefer to be secure and release the load on it a bit.


----------



## The_King

Akex said:


> It's true that Microns don't have voltage scaling like BDIEs, and not just on tRFC as well.
> But where I doubted about tRFC to be more precise, is can I define tRFC according to wanting 300ns or do I really have to follow a particular rule like Anta's or tRC*X.
> In fact, I can do 295ns stable, that's what I have on the 4733C16 preset, but being at the extreme limit of my kit, I prefer to be secure and release the load on it a bit.


Use the custom / manual TRFC option its on one of the spreadsheet tabs. The recommended 275ns I seen would most likely cause your system to hang at boot / post.









tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com


----------



## Akex

The_King said:


> Use the custom / manual TRFC option its on one of the spreadsheet tabs. The recommended 275ns I seen would most likely cause your system to hang at boot / post.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> tRFC mini
> 
> 
> TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...
> 
> 
> 
> 
> docs.google.com


Ok so I'm going to focus tRFC 740 and adjust tRFC2/4 to suit.


----------



## ManniX-ITA

The_King said:


> I seem to lose tons of time in Y-cruncher and Super Pi at and above 2000 FCLK, I can reach very high MT with my kits even 4800MT 2:1.
> 
> Problem is related to the VDD18 / CPU 1P8 no option to adjust that on my B450.
> 
> Contacted Reous told me I could try enabling myself with AMIBCP but have to cut the BIOS in half,
> I have a 32MB (2x16MB) bios and have to cut it in the middle. The second part is for Ryzen 3000/4000/5000. First one for Ryzen 1000/2000
> very clueless on that part is there any guide on here I can use to do this?


Oh right I forgot your issue with VDD18... not an expert with AMIBCP.
Did some mods in the past but I'm clueless about this 16/32 MB stuff.

Maybe @Veii knows better or has a link to a guide?



Imprezzion said:


> The other "right" one when overclocking is quite simply the lowest you can run. Nothing more complicated.


I don't agree; if you want to get the best latency you need the right tRFC and also tRFC2/4.

I'm not the best one to explain 
But in short tRFC is the wait window before a new command can be issued after a memory refresh command.
If tRFC expires a little too early or late it will delay the next set of commands causing at least a loss of latency.
For some reasons while AMD doesn't technically use tRFC2/4 if you don't set them properly you'll get as well another latency penalty.

Of course you need a good profile with all the timings working in sync and with GDM Off.

Then you should be able to see the difference in synthetic benchmarks.
I recall there was one pi where it was more evident on repeatability of score but I forgot. y-cruncher maybe? 

First canary bird something is wrong with tRFC is AIDA64 memory latency.
If there's too much variance between runs (on a very clean system) then tRFC needs fixing.


----------



## mongoled

Akex said:


> Handling error while wanting to set vSOC with the offset to keep the pstate on the iGPU, results CPU dead. It must also be said that during the Team CUP 2022 it suffered... I get another one on Saturday, I hope it will be at least as good, 2550Mhz stable in Air for the IGPU it's rare... Anyway be careful with your settings, I am experienced and yet a moment of inattention cost me my 5700G.


Sorry for your loss, came across your post via search function filtered using "recent posts" first and search terms "5700g"

Did you have any experiences using 5600x, 5800x ? 

I am contemplating changing my 5600X to a 5700G so I have something new to play with, but am wondering how much single thread CPU performance I would loose by doing this. The specs for both CPUs show 4.6Ghz as max boost speed, but I am unsure, are the 5700G also EDC restricted to max 90A on latest BIOS like the 5600x are ??


----------



## Imprezzion

ManniX-ITA said:


> Oh right I forgot your issue with VDD18... not an expert with AMIBCP.
> Did some mods in the past but I'm clueless about this 16/32 MB stuff.
> 
> Maybe @Veii knows better or has a link to a guide?
> 
> 
> 
> I don't agree; if you want to get the best latency you need the right tRFC and also tRFC2/4.
> 
> I'm not the best one to explain
> But in short tRFC is the wait window before a new command can be issued after a memory refresh command.
> If tRFC expires a little too early or late it will delay the next set of commands causing at least a loss of latency.
> For some reasons while AMD doesn't technically use tRFC2/4 if you don't set them properly you'll get as well another latency penalty.
> 
> Of course you need a good profile with all the timings working in sync and with GDM Off.
> 
> Then you should be able to see the difference in synthetic benchmarks.
> I recall there was one pi where it was more evident on repeatability of score but I forgot. y-cruncher maybe?
> 
> First canary bird something is wrong with tRFC is AIDA64 memory latency.
> If there's too much variance between runs (on a very clean system) then tRFC needs fixing.


Yeah sorry I over simplified it a bit. The lowest you can run which is still a correct value. 277 isn't but 272 is for example on DR B-Die. Afaik it's multiples of 16 on DR sticks. That's what I've been told at least hehe.


----------



## mongoled

@Nighthog
Interested to hear your opinion.

Can you add your thoughts regarding going from a 5600x to a 5700g.

What do you think regards overcoming the differences in CPU performance by the higher memory bandwidth that can be achieved with the 5700G, as you can see from my sig I am already running 3800/1900 CL13, tRFC 224. So these mem modules should scale beautifully a 5700g


----------



## Akex

mongoled said:


> Sorry for your loss, came across your post via search function filtered using "recent posts" first and search terms "5700g"
> 
> Did you have any experiences using 5600x, 5800x ?
> 
> I am contemplating changing my 5600X to a 5700G so I have something new to play with, but am wondering how much single thread CPU performance I would loose by doing this. The specs for both CPUs show 4.6Ghz as max boost speed, but I am unsure, are the 5700G also EDC restricted to max 90A on latest BIOS like the 5600x are ??


Don't worry, it's a blessing in disguise. And then I managed to release a better 5700G than the first one overall.

To answer your question, I have a 5800X on the main PC, coupled with a large watercustom, what I can tell you is that the 5700G does not have to be ashamed of the 5800X, after that it must be taken into account that the 5700G is akin to a Golden Sample and the 5800X more like an average bin. That said in-game, the L3 cache difference means the 5800X will still be better. Another thing, with the override the 5700G will not go higher than 4850mhz where the 5800X will be able to do 5050mhz maximum, but a good correct you will seek 4900mhz on it to have a decent curve.

Then the 5700G is on a Strix-F, and I don't have that 90A limit, I can override it with the PBO2. More concretely, the 5700G is in a 011 Air Mini case with 6x Arctic P14 ARGB and 6x Arctic P12 ARBG, the cooler is a noctua NHD15, and with an idle temperature of 32 when I trigger the benches, I have the following result:

CBR23 = 4700Mhz +/- @77°C / 114Watt
CBR20 = 4725Mhz +/- @76°C / 114Watt
CBR15 = 4715Mhz +/- @ 76°C / 114Watt
CPUZ = 4750Mhz +/- @ 67°C / 100Watt

This with the iGPU enabled and EDC=130 / TDC=90 / PPT=250

I could give you the scores obtained, but they are really not representative insofar as my OS is really rotten with useless software which runs in the background, not optimized at all, and which has known different CMs including a B450, that is to say I can do a statement on my bench OS that I use for HWBOT which is much cleaner and much closer to reality.

Roughly speaking, the 5700G and it's the only reading I've done on the HWBOT OS, CPUZ gives me more than 7000 points in multi and 675 in mono.

Don't forget that I sorted 6x 5700G, only two received have this potential, the other 4 are decent average CPUs.

The tests were done with RAM @4733 C16 - 22-22-22-44-68 tRFC680, currently I finished a 4933C16 preset and I noticed a significant gain again.

Don't be fooled, memory bandwidth will never catch up to the 5800X's L3 cache, even at 4933C16, the 5800X @3800C14 does better


----------



## Nighthog

mongoled said:


> @Nighthog
> Interested to hear your opinion.
> 
> Can you add your thoughts regarding going from a 5600x to a 5700g.
> 
> What do you think regards overcoming the differences in CPU performance by the higher memory bandwidth that can be achieved with the 5700G, as you can see from my sig I am already running 3800/1900 CL13, tRFC 224. So these mem modules should scale beautifully a 5700g


It's all about the cache in the CPU & what frequency you can hit.

The G processors don't clock as well as the regular 5000 series. Quality is overall lower. So you lose out even with the high memory clocks with the G series.
Though they are more fun to play with in general. 
Sadly my sample is a dud with regard to core stability. (not stable at stock without LLC medium at minimum) So I never could get any good OC on it.

I'm thinking on making a RMA soon for another sample. 
I think the G series can handle higher voltages better than the regular series but the silicon quality is worse so you don't get better frequencies for CPU clocks anyway. 
I really would have needed a decent sample to begin with. I realized way to late my sample was crap in actuality.


----------



## mongoled

Akex said:


> Don't worry, it's a blessing in disguise. And then I managed to release a better 5700G than the first one overall.
> 
> To answer your question, I have a 5800X on the main PC, coupled with a large watercustom, what I can tell you is that the 5700G does not have to be ashamed of the 5800X, after that it must be taken into account that the 5700G is akin to a Golden Sample and the 5800X more like an average bin. That said in-game, the L3 cache difference means the 5800X will still be better. Another thing, with the override the 5700G will not go higher than 4850mhz where the 5800X will be able to do 5050mhz maximum, but a good correct you will seek 4900mhz on it to have a decent curve.
> 
> Then the 5700G is on a Strix-F, and I don't have that 90A limit, I can override it with the PBO2. More concretely, the 5700G is in a 011 Air Mini case with 6x Arctic P14 ARGB and 6x Arctic P12 ARBG, the cooler is a noctua NHD15, and with an idle temperature of 32 when I trigger the benches, I have the following result:
> 
> CBR23 = 4700Mhz +/- @77°C / 114Watt
> CBR20 = 4725Mhz +/- @76°C / 114Watt
> CBR15 = 4715Mhz +/- @ 76°C / 114Watt
> CPUZ = 4750Mhz +/- @ 67°C / 100Watt
> 
> This with the iGPU enabled and EDC=130 / TDC=90 / PPT=250
> 
> I could give you the scores obtained, but they are really not representative insofar as my OS is really rotten with useless software which runs in the background, not optimized at all, and which has known different CMs including a B450, that is to say I can do a statement on my bench OS that I use for HWBOT which is much cleaner and much closer to reality.
> 
> Roughly speaking, the 5700G and it's the only reading I've done on the HWBOT OS, CPUZ gives me more than 7000 points in multi and 675 in mono.
> 
> Don't forget that I sorted 6x 5700G, only two received have this potential, the other 4 are decent average CPUs.
> 
> The tests were done with RAM @4733 C16 - 22-22-22-44-68 tRFC680, currently I finished a 4933C16 preset and I noticed a significant gain again.
> 
> Don't be fooled, memory bandwidth will never catch up to the 5800X's L3 cache, even at 4933C16, the 5800X @3800C14 does better





Nighthog said:


> It's all about the cache in the CPU & what frequency you can hit.
> 
> The G processors don't clock as well as the regular 5000 series. Quality is overall lower. So you lose out even with the high memory clocks with the G series.
> Though they are more fun to play with in general.
> Sadly my sample is a dud with regard to core stability. (not stable at stock without LLC medium at minimum) So I never could get any good OC on it.
> 
> I'm thinking on making a RMA soon for another sample.
> I think the G series can handle higher voltages better than the regular series but the silicon quality is worse so you don't get better frequencies for CPU clocks anyway.
> I really would have needed a decent sample to begin with. I realized way to late my sample was crap in actuality.


Thanks for both your responses,

I see you both share the same opinions regarding CPU silicon quality. Are these CPUs bought recently or from older batches ?

My general understanding is that I would need to get a good silicon quality CPU to be able to come close to what my 5600x can do, seeing that my 5600x is restricted to 4850 mhz on the latest agesa, if the 5700g would need to do more than 4850 mhz to have any chance of parity in single thread IPs, is there any headroom in a good silicon quality 5700g using BCLK ?

I have the 5700g in my Amazon.de cart, its currently priced at 173.94€ (excl. VAT), so tempted to pull the trigger as I have stuff to order from there


----------



## Nighthog

mongoled said:


> Thanks for both your responses,
> 
> I see you both share the same opinions regarding CPU silicon quality. Are these CPUs bought recently or from older batches ?
> 
> My general understanding is that I would need to get a good silicon quality CPU to be able to come close to what my 5600x can do, seeing that my 5600x is restricted to 4850 mhz on the latest agesa, if the 5700g would need to do more than 4850 mhz to have any chance of parity in single thread IPs, is there any headroom in a good silicon quality 5700g using BCLK ?
> 
> I have the 5700g in my Amazon.de cart, its currently priced at 173.94€ (excl. VAT), so tempted to pull the trigger as I have stuff to order from there


They are cheap now but I bought mine near the launch date for the regular price.
Mine is already 1year and 3 months old. (just made a RMA request)

If you want to play around I see not problem with getting one. That is if you can afford to spend money on playthings.


----------



## mongoled

Nighthog said:


> They are cheap now but I bought mine near the launch date for the regular price.
> Mine is already 1year and 3 months old. (just made a RMA request)
> 
> If you want to play around I see not problem with getting one. That is if you can afford to spend money on playthings.


As things being as they are with the economy (self-employed) dont really have the money to spend on playthings, but as I saw that the 5600x is being sold on ebay.co.uk (completed listings) for around 170€ used, would probably end up costing me 20-30€ as I would buy the 5700g at 176€ as I dont have to pay the VAT.

Will look around to see if there is any info on the net with newer versions of 5700g having better silicon, thanks for your insight


----------



## ManniX-ITA

Nighthog said:


> The G processors don't clock as well as the regular 5000 series. Quality is overall lower. So you lose out even with the high memory clocks with the G series.
> Though they are more fun to play with in general.


Completely agree. Lot of fun but I honestly wouldn't replace an X with the same cores.
Maybe it could be an option to replace a 5600X but for sure with some sacrifices.

My 5600G as well, bought less than 6 months ago, is not a good silicon.
These are monolithic CPUs so there's not much recycling as with the X versions.

Didn't really tried hard but it's not stable at 4650 MHz, had to clock down to 4625 MHz.
MCLK also is underwhelming, couldn't get it stable at 4600+.

I'm using it in my NAS/Server so at the end I've configured it for low power mode, scaled down to 1900/3800.
At 2100/4200 was quite acceptable but almost 10W more in Standby.
For higher FCLK you need to disable the dynamic FCLK and this costs another 10-15W in Standby.

Also it's running Linux so it's unstable even with stock settings.
OC is extremely limited with Linux and very difficult.
Had to spend weeks in tweaking to get it solid under stress.
But at the end it was worth it as the G power consumption and performances are trashing any Intel counterpart at the same price.


----------



## mongoled

My next search terms are "5700g ihs removal" 

Looks easier to delid than the 5600g seeing that the SMDs are more central than the 5600x meaning cutting the silicon glue will be loads easier than the 5600x


----------



## Veii

@mongoled wouldn't you want to come over to AM5 on black Friday ?
On memory you can go as cheap as possible atm.
This CPU gen (internal freq and interleaving design) prevents high MCLK
Soo any OEM kit you pick will be fine for you
Dual 16 GB Samsung's for around 155-160$, dual Hynix-A OEM for about 220, and often there is a hynix-m + CPU kit bundle 

300 for a CPU+men bundle or ~550 for everything, should be findable
Boards are a bit too much still, but thing might be fun to play with as gaming cpu
MemOC training only, the apu remains.
Boards are still a bit too much & DDR5 is halfway booring on AM5


----------



## Nighthog

mongoled said:


> My next search terms are "5700g ihs removal"
> 
> Looks easier to delid than the 5600g seeing that the SMDs are more central than the 5600x meaning cutting the silicon glue will be loads easier than the 5600x


If you want a cheap G processor without the iGPU buy a Ryzen 5 5500.


----------



## mongoled

Veii said:


> @mongoled wouldn't you want to come over to AM5 on black Friday ?
> On memory you can go as cheap as possible atm.
> This CPU gen (internal freq and interleaving design) prevents high MCLK
> Soo any OEM kit you pick will be fine for you
> Dual 16 GB Samsung's for around 155-160$, dual Hynix-A OEM for about 220, and often there is a hynix-m + CPU kit bundle
> 
> 300 for a CPU+men bundle or ~550 for everything, should be findable
> Boards are a bit too much still, but thing might be fun to play with as gaming cpu
> MemOC training only, the apu remains.
> Boards are still a bit too much & DDR5 is halfway booring on AM5


LOL, of course I would like to come over to AM5

 all new platform, so many new things to learn,

The same could be said for moving over to Raptor Lake (ive always bought AMD for my personal custom rigs).

But as previously explained, now is not a good time for me, yes I could sell off my AM4 rig and re-invest with some monies on top, but you sort of hit the nail on the head with regards to AM5, DDR5 is going to keep scaling in frequency and AM5 will be stuck on "low" frequencies when compared to what Raptor will do.

Intel now being the "underdog" are catering their CPUs to be more overclock friendly, I want this to return to AMD , but Raptor is a "dead end" platform.

Getting a 5700g should be enough to calm me from spending monies on things I dont need, not that I need the 5700g, just I can have fun playing with it, can delid it very easily and can see what my Viper steels can do with regards to 1:1 overclock


----------



## mongoled

Nighthog said:


> If you want a cheap G processor without the iGPU buy a Ryzen 5 5500.


I think you misunderstood me, why would I go to a 5500 when I already have a 5600x ??

Im considering the 5700g as its something new to play with that can let me take my Vipers to the max frequency 1:1, I can delid it easily, so more fun to play/hobby with at a low cost


----------



## Akex

@mongoled
If you're gaming at 1440p or + then the 5600X vs 5700G might be worth it for fun without losing performance. A classic 5600X vs a 5700G with a good sample, you are roughly 5-10 fps apart according to my tests. If you ask me my opinion, I would tell you that if you are lucky enough to nab a sample like mine, then you can sell your 5600X without having a performance hole in the game, as long as you know what you are doing. that, you have fun with the 5700G.

That said, you can abuse like me with Amazon, order 2x 5700G to start, and sort it out little by little. For my part my first deceased 5700G dated the release of the CPU, and it was right on top. iGPU 2500MHZ @1.3650v . MCLK/FCLK/UCLK 4733Mhz with possibility of making 4933, although at the time I had not succeeded in stabilizing the kit, partly because of the kit itself. PBO2 really not bad at all, to tell you, here is over two weeks what I was able to do for TeamCUP 2022, of course it's hwbot not h24, but in the idea my current sample is recent June 2022 if I have a good memory, and the old as I said, sample right out.

With more time devoted, I could certainly have done better on certain benchmarks, but time was running out.


----------



## Veii

mongoled said:


> DDR5 is going to keep scaling in frequency and AM5 will be stuck on "low" frequencies when compared to what Raptor will do.











It's only Zen4 being entry level and having firmware/design trouble with DDR5
Too fast internally - but would lose IPC elsehow
Currently not really slower than Raptor unless you run 6800 to 7000+ mem


mongoled said:


> But as previously explained, now is not a good time for me, yes I could sell off my AM4 rig and re-invest with some monies on top


You hope for better B650E's ?
Or Z890 ?

Except the lack of new 12HVPWR PSU's
And 5600MT/s Jedec kits
There isn't really anything that is missing on "current/new" gen
Only the prices are a bit debatable


----------



## The_King

Veii said:


> View attachment 2584794
> 
> It's only Zen4 being entry level and having firmware/design trouble with DDR5
> Too fast internally - but would lose IPC elsehow
> Currently not really slower unless you run 6800 to 7000+ mem
> 
> You hope for better B650E's ?
> Or Z890 ?
> 
> Except the lack of new 12HVPWR PSU's
> And 5600MT/s Jedec kits
> There isn't really anything that is missing on "current/new" gen
> Only the prices are a bit debatable


Which is higher at the moment the Euro or Dollar? Are these good deals?








AMD Ryzen 5 7600X - 6-Core 4.7 GHz - Socket AM5 - 105W Desktop Processor (100-100000593WOF) - Newegg.com


Buy AMD Ryzen 5 7600X - 6-Core 4.7 GHz - Socket AM5 - 105W Desktop Processor (100-100000593WOF) with fast shipping and top-rated customer service. Once you know, you Newegg!




www.newegg.com













AMD Ryzen 9 7950X - 16-Core 4.5 GHz - Socket AM5 - 170W Desktop Processor (100-100000514WOF) - Newegg.com


Buy AMD Ryzen 9 7950X - 16-Core 4.5 GHz - Socket AM5 - 170W Desktop Processor (100-100000514WOF) with fast shipping and top-rated customer service. Once you know, you Newegg!




www.newegg.com





Further discounted if you use the promo codes


----------



## Akex

The_King said:


> Which is higher at the moment the Euro or Dollar? Are these good deals?
> 
> 
> 
> 
> 
> 
> 
> 
> AMD Ryzen 5 7600X - 6-Core 4.7 GHz - Socket AM5 - 105W Desktop Processor (100-100000593WOF) - Newegg.com
> 
> 
> Buy AMD Ryzen 5 7600X - 6-Core 4.7 GHz - Socket AM5 - 105W Desktop Processor (100-100000593WOF) with fast shipping and top-rated customer service. Once you know, you Newegg!
> 
> 
> 
> 
> www.newegg.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> AMD Ryzen 9 7950X - 16-Core 4.5 GHz - Socket AM5 - 170W Desktop Processor (100-100000514WOF) - Newegg.com
> 
> 
> Buy AMD Ryzen 9 7950X - 16-Core 4.5 GHz - Socket AM5 - 170W Desktop Processor (100-100000514WOF) with fast shipping and top-rated customer service. Once you know, you Newegg!
> 
> 
> 
> 
> www.newegg.com


Dollar


----------



## ManniX-ITA

The_King said:


> Further discounted if you use the promo codes


Really good deals if you don't have to pay for duties or taxes.
But I've seen even better in the past weeks from the USA with memory and board combos from Newegg.


----------



## Veii

The_King said:


> Which is higher at the moment the Euro or Dollar? Are these good deals?
> 
> 
> 
> 
> 
> 
> 
> 
> AMD Ryzen 5 7600X - 6-Core 4.7 GHz - Socket AM5 - 105W Desktop Processor (100-100000593WOF) - Newegg.com
> 
> 
> Buy AMD Ryzen 5 7600X - 6-Core 4.7 GHz - Socket AM5 - 105W Desktop Processor (100-100000593WOF) with fast shipping and top-rated customer service. Once you know, you Newegg!
> 
> 
> 
> 
> www.newegg.com
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> AMD Ryzen 9 7950X - 16-Core 4.5 GHz - Socket AM5 - 170W Desktop Processor (100-100000514WOF) - Newegg.com
> 
> 
> Buy AMD Ryzen 9 7950X - 16-Core 4.5 GHz - Socket AM5 - 170W Desktop Processor (100-100000514WOF) with fast shipping and top-rated customer service. Once you know, you Newegg!
> 
> 
> 
> 
> www.newegg.com
> 
> 
> 
> 
> Further discounted if you use the promo codes
> 
> 
> ManniX-ITA said:
> 
> 
> 
> Really good deals if you don't have to pay for duties or taxes.
> But I've seen even better in the past weeks from the USA with memory and board combos from Newegg.
Click to expand...

Considering most of our options have ~20% VAT on them ontop
And that microcenter surely has memory combo's (including newegg)
where entry level hynix-m is universally decent and enough to stay at 6200 without breaking precision boost or ring/cache

It's not a bad option at all. // ~10 bucks too much
My clients sample is again ~130mV overvolted between CCDs and pushes 1.42 vs 1.26 on SSE workloads

I am actually happy with the perf it got after fixing boost issues
But the bios bugs are annoying, just at least "less dangerous" anymore
There are still bugs that will charr the gold contacts of your dimms by nuking voltage high
And IF instability is visible directly as mouse lag & usb or ethernet dropouts
(no logging of WHEA 18 or 19 at all)
// 5/10 sensorics active delivered. 8/10 sensorics active after PSP-FW update and chipset drivers

Buut all children-illnesses aside, i like the perf of it
You can use the APU for hardware encoding as 2ndary capture source & ontop it boosts interleaving bandwidth between L$ and IF itself.
But if you want to wait - it makes sense to see if X3D will have wide-IF implemented or just move with no locks.

But then also, i have no hopes for X3D to "not" have the same ring/cache trouble that Zen4 has
Zen 5 for sure will be fun with the change - but can't confidentially say anything more for X3D.
Hopefully bridge charr problem on v-cache will be resolved and maaybe hopefully utilize wideIF

EDIT:
For consumer this gen is great atm
Can run with the cheapest memory and be realistically maxed out on stock with bit of CO
For OCer - Zen 5 will be interesting but that's far later
Soo for hobbiest - cheapest Zen4 then cheapest X3D (with cheapest B650 board) ~ as a learning toy while AMD works on the firmware a bit more
// dual PCH do not mitigate LCLK trouble on high IF (dropouts) nor improve SNR. Spare yourself from it unless you need the IO

Or hope for soon Z890 appearance - which i haven't heard anything about.
Its really booring at the moment - and only exploring OEMs DDR5 design keeps it being interesting.
Sample doesn't really scale high - it's either 6000 MCLK and 5.8-5.9 or 6200 MCLK and barely 5.8


----------



## PJVol

mongoled said:


> I am contemplating changing my 5600X to a 5700G so I have something new to play with, but am wondering how much single thread CPU performance I would loose by doing this.


Yeah, maybe there's someone who owns both.


----------



## The_King

The_King said:


> What are you guys with 5800X getting in Y-cruncher with AIR or water cooled setups? This is with my Micron DR Ram I'm sure Samsung B-die will shave this time off abit maybe 1 to 2 seconds?
> 
> Winter is coming so time to go for some PB scores on HWBOT. Any advice is welcome from all.
> View attachment 2584716


@ManniX-ITA I dropped my all core down to 4375 and beat the above score with 4600 all core.


----------



## ManniX-ITA

The_King said:


> I dropped my all core down to 4375 and beat the above score


Uhm very weird 
It should matter that big gap in the CPU clock, there's a bottleneck somewhere.

Forgot something: did you try to go down with FCLK when trying to go very high with unsync?
I've found out a few weeks ago that this trashy 5950X sample RAM clock with unsync was limited by FCLK.
Going to down from FCLK 1900 to 1800/1700 allowed me about 200 MHz more.
y-c doesn't really care if you go down with FCLK.


----------



## The_King

ManniX-ITA said:


> Uhm very weird
> It should matter that big gap in the CPU clock, there's a bottleneck somewhere.
> 
> Forgot something: did you try to go down with FCLK when trying to go very high with unsync?
> I've found out a few weeks ago that this trashy 5950X sample RAM clock with unsync was limited by FCLK.
> Going to down from FCLK 1900 to 1800/1700 allowed me about 200 MHz more.
> y-c doesn't really care if you go down with FCLK.


Will give it try and see if there is any improvement. Thanks


----------



## MrHoof

The_King said:


> @ManniX-ITA I dropped my all core down to 4375 and beat the above score with 4600 all core.
> View attachment 2584812
> View attachment 2584814


Here some samsung scores from my daily setups 5800x and now 3d.


----------



## Luggage

ManniX-ITA said:


> Gunzi`s y-cruncher - Pi-2.5b score: 1min 32sec 159ms with a Ryzen 7 5800X
> 
> 
> The Ryzen 7 5800X @ 4650.3MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. Gunziranks #71 worldwide and #7 in the hardware class. Find out more at HWBOT.
> 
> 
> 
> 
> hwbot.org
> 
> 
> 
> 
> 
> If you want to score on y-cruncher could be easier with Micron.
> Check the #1 ranking 5800X, it's using 5500 MHz static OC at memory clock 3800 MHz CL14.
> 
> While the #2 is just 4825 MHz CPU but with un-sync memory clock 4700 MHz CL16.
> 
> 
> 
> 
> 
> 
> 
> 
> Antifreeze`s y-cruncher - Pi-2.5b score: 1min 29sec 546ms with a Ryzen 7 5800X
> 
> 
> The Ryzen 7 5800X @ 4836.4MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. Antifreezeranks #64 worldwide and #2 in the hardware class. Find out more at HWBOT.
> 
> 
> 
> 
> hwbot.org
> 
> 
> 
> 
> 
> The #3 is 200ms slower with 4925 MHz and memory clock 3800 MHz CL13.
> 
> 
> 
> 
> 
> 
> 
> 
> mickulty`s y-cruncher - Pi-2.5b score: 1min 29sec 776ms with a Ryzen 7 5800X
> 
> 
> The Ryzen 7 5800X @ 4925.1MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. mickultyranks #65 worldwide and #3 in the hardware class. Find out more at HWBOT.
> 
> 
> 
> 
> hwbot.org
> 
> 
> 
> 
> 
> If you can get the clock above 5 GHz and un-sync memory at 4500+ then the #2 spot is yours.


And #4 is me 
… and I’m slightly suspicious that I degraded my core 0 with that run  

Have test again if it gets that cold again this winter ❄

But yea I’ll have to get a decent async ram OC going to play with the top 3…


----------



## The_King

Luggage said:


> And #4 is me
> … and I’m slightly suspicious that I degraded my core 0 with that run
> 
> Have test again if it gets that cold again this winter ❄
> 
> But yea I’ll have to get a decent async ram OC going to play with the top 3…


Sent you a pm never got a reply. 

@ManniX-ITA Looks like my RAM may be the bottleneck dropped to 1900 FCLK and CL 14 almost identical scores with my 2 previous results. Will change to my Samsung kit and test again tomorrow.


----------



## Luggage

The_King said:


> Sent you a pm never got a reply.
> 
> @ManniX-ITA Looks like my RAM may be the bottleneck dropped to 1900 FCLK and CL 14 almost identical scores with my 2 previous results. Will change to my Samsung kit and test again tomorrow.
> View attachment 2584854


Ran diagnostics but forgot to zero all my settings, been away from computer since… :/


----------



## dimkatsv

MrHoof said:


> Here some samsung scores from my daily setups 5800x and now 3d.


Wish i could run my H8D 2R sticks on 1T GDM off. . . Tiny bit envy, i guess. 
Well, technically i can RUN them, but oh boy it will be rollercoaster of instabilities (Y-Cruncher crashes really fast)


----------



## MrHoof

dimkatsv said:


> Wish i could run my H8D 2R sticks on 1T GDM off. . . Tiny bit envy, i guess.
> Well, technically i can RUN them, but oh boy it will be rollercoaster of instabilities (Y-Cruncher crashes really fast)


I was always running 1t on this board with 2xSR and 2xDR and 2 different CPU´s, SR was alot easier to stabilze but for my DR kit even the dimm order did make a difference on a 2 dimm board.
When i first got the 32gb kit I always ran into radom errors until I swapped them.
Edit: very old screenshot with a very bad 3600-17-18-18-38 kit.


----------



## toljan2884

Что не так
МОДУЛЬ DIMM 1.42


----------



## ApT01

Been lurking on this thread for a while now. This is what I managed to get mine to:








Micron Rev.E C9BJZ 3000C15 DR kit @ 3800 16-20/8-18-21-60 1T GDM Off
Vdimm:1.4v
Vsoc:1.13v
Cldo_vddp:0.95v
Vddg_ccd/iod:0.9v/1.05v
Cpu 1.8v:1.85v

Everything is very stable and I don't get any WHEAs but I can't seem to tighten it any more despite going through a myriad of settings. Is this it, have I reached the limits of my hardware? Does anyone see anything glaringly wrong in my settings? Any help would be appreciated.


----------



## The_King

ApT01 said:


> Been lurking on this thread for a while now. This is what I managed to get mine to:
> View attachment 2584899
> 
> Micron Rev.E C9BJZ 3000C15 DR kit @ 3800 16-20/8-18-21-60 1T GDM Off
> Vdimm:1.4v
> Vsoc:1.13v
> Cldo_vddp:0.95v
> Vddg_ccd/iod:0.9v/1.05v
> Cpu 1.8v:1.85v
> 
> Everything is very stable and I don't get any WHEAs but I can't seem to tighten it any more despite going through a myriad of settings. Is this it, have I reached the limits of my hardware? Does anyone see anything glaringly wrong in my settings? Any help would be appreciated.


Running CL16 and tCWL 14 can be the cause of some stability problems when lowering RCDRD, this also why RDWR is at 11. Becareful with WRRD 1 with DR it can cause system to hang when RDWR is at 8/9 you may need WRRD at 2 or 3. So first try to change tCWL from 14 to 16.

Not sure if there is a difference between SR and DR C9BJZ but I'm sure RCDRD can go lower to 19 and be stable.
You can also do me a favor and save me some time by running 50 cycles on this.  Can change tWTRL/S to 4/8 adjust tWR 16 and RTP 8 if you need to should be more stable


----------



## Bloax

Veii said:


> But the bios bugs are annoying, just at least "less dangerous" anymore
> There are still bugs that will charr the gold contacts of your dimms by nuking voltage high
> And IF instability is visible directly as mouse lag & usb or ethernet dropouts
> (no logging of WHEA 18 or 19 at all)
> // 5/10 sensorics active delivered. 8/10 sensorics active after PSP-FW update and chipset drivers
> 
> Buut all children-illnesses aside, i like the perf of it
> You can use the APU for hardware encoding as 2ndary capture source & ontop it boosts interleaving bandwidth between L$ and IF itself.
> But if you want to wait - it makes sense to see if X3D will have wide-IF implemented or just move with no locks.
> 
> But then also, i have no hopes for X3D to "not" have the same ring/cache trouble that Zen4 has
> Zen 5 for sure will be fun with the change - but can't confidentially say anything more for X3D.
> Hopefully bridge charr problem on v-cache will be resolved and maaybe hopefully utilize wideIF
> 
> EDIT:
> For consumer this gen is great atm
> Can run with the cheapest memory and be realistically maxed out on stock with bit of CO
> For OCer - Zen 5 will be interesting but that's far later
> Soo for hobbiest - cheapest Zen4 then cheapest X3D (with cheapest B650 board) ~ as a learning toy while AMD works on the firmware a bit more
> // dual PCH do not mitigate LCLK trouble on high IF (dropouts) nor improve SNR. Spare yourself from it unless you need the IO
> 
> Or hope for soon Z890 appearance - which i haven't heard anything about.
> Its really booring at the moment - and only exploring OEMs DDR5 design keeps it being interesting.
> Sample doesn't really scale high - it's either 6000 MCLK and 5.8-5.9 or 6200 MCLK and barely 5.8


Basically what I'm reading is that a latency-crunched 13600k (ITX DDR4, or DDR5 if you play extremely badly coded games) is gonna be more than adequate, have none of the Classic Zen Chiplet OC xXpERienCE, and also not be all that expensive.

deadend platform oh no no no what will i do with a CPU that actually feeds a 240 Hz monitor (hey look OLED is cooming!) with barely-if-any drops below 240 FPS
bros you've gotta buy the AM5 gotta buy the big FPS printer!! throughput good!!! nvidia told me so, so it must be true.....


----------



## Veii

Bloax said:


> Basically what I'm reading is that a latency-crunched 13600k (ITX DDR4, or DDR5 if you play extremely badly coded games) is gonna be more than adequate, have none of the Classic Zen Chiplet OC xXpERienCE, and also not be all that expensive.


There is no way it wont be faster 
But on stock and for non memOC people - AM5 (Zen4) is quite fast, including scientific render.

I don't know how to judge the reason for entry, on it
This "it's a dead platform part [LGA1700]" but that also applies to X3D, which is not too bad for a 2nd cheap gaming system
(if game-broadcaster for example)
The same applies to Zen4, but sadly there we depend on PBO override (OC_Mode Hydra) to make non dual CCDs a great option. // come with too low freq limits
With the only exception, that the next CPU you put in - will be great for memOC
(X3D might not be that one, up to AMD for W-IF, but unlikely)

For memOC Zen5 will be great, but on stock 13th gen/Zen4 are equal. The only change is indeed the Boardprice.
Maybe if i was in Broadcasters shoe's and start from scratch ~ I'd buy two times AMD
One cheap low end board, one highend
Reuse the "low end" later as encoding system
(which is were AM5 shines a bit more once CO tuned)
And then wait for an arch update, to have fun with memOC.

Currently Raphael feels more like Vermeer-X (V-Cache)
Fast, strongly interleaved, warm but efficient, barely OC headroom.
Soo for consumer or prosumer, a great thing tbh. But it's boring for memOC and has firmware bugs.
Intel is bit booring for coreOC, but memory is fun . . just bandwidth efficiency is sub-optimal.
Hard to judge ~ both need to improve a bit more

EDIT:
As memOCer, i would love to be on 13th gen.
But the buying option (cost) as non-upgrade path is just not viable. It's more an option for Z690 people
On AMD you have to focus on efficiency right now, as there is nothing else you can do except try to improve SNR and fight with bioses
Overvolting won't bring you much, till AMD redo's Internal Freq a bit
// they run it too much on the limit at the moment, to take the IPC crown
// ...cache/ring simply crashes, a bit over spec
~ buut community will be annoyed again by harsh drop in perf-per-clock

EDIT2:
Considering IMC and limits.
I would still prefer them to slow down Raphael a bit internally.
Boosting system is great too, but it simply runs on the limits (not the CCDs and neither the IMC)
IMC should be capable, and 2:1 mode headroom should also be still open till minimum 7000MT/s
But all that doesn't help you when L$/Ring crashes on core freq.
I doubt anybody would like to run Raphael at 4.7GHz only to maintain 6400/6600+ stability
2:1 / 1:1 don't really matter at the moment. Its no memOC limit ~ it's an arch stability issue


----------



## The_King

@Veii Any tips to improve this? 
What the best settings in the BIOS when running this benchmark and any setting on the RAM that can give significant boost in performance?
My tRP tRAS and RC could do with some fine tuning.


----------



## Luggage

The_King said:


> @Veii Any tips to improve this?
> What the best settings in the BIOS when running this benchmark and any setting on the RAM that can give significant boost in performance?
> My tRP tRAS and RC could do with some fine tuning.
> View attachment 2584981


Run async and push for as high bw as possible.


----------



## The_King

Luggage said:


> Run async and push for as high bw as possible.


Got VDD18 issues with this B450 board that is why its @ 3933 CL15 not 4000 CL15.
Lose +/-8 seconds going over 2000 MCLK or FCLK even 2:1. Have tried


----------



## Veii

The_King said:


> @Veii Any tips to improve this?
> What the best settings in the BIOS when running this benchmark and any setting on the RAM that can give significant boost in performance?
> My tRP tRAS and RC could do with some fine tuning.
> View attachment 2584981


What is your Aida64 result ?








Hitting this ?
31465MB/s at bare minimum
~ if not you're throttling somewhere by FCLK
// i'd accept 31 464 at least . . . as it can be your OS too. But over 31465 is your target !

Y-cruncher itself is very multicore focused
FCLK less, but for 1CCD might still be

How did you get to RAS 38 ?
tRCD 18 + tRCDW 18 = 36
tCAS 15 *3 = 45
tRCD 18 + tRTP 8 = 26 tRASmin
38 doesn't match up with any possible option

Neither is tRC 58
tRP 18 + tRAS (36?) = 54 + tBurstchop 8 = 62
tRP 18 + tRASmin 26 = 44
How did you get to 58 

Fix those first
tRAS 36, tRC 54
Give at the same time tRDWR +1 (tRCD/2 = 9 + 2 for DR = 11 , -1 by slowing writes = 10 ... not 9) 
tRDWR is also DIMM PCB design focused, but at least run 10
======================
Oh actually that is DR Rev.E
I see now
Well then tRAS 45, tRC 63
Maybe this downscaled can work out for you
// up to VDIMM, because it will be [email protected] 1.65v








Take a look here
https://www.overclock.net/threads/o...memory-stability-thread.1628751/post-28946224








5000 runs too, but i lost the screenshot
not on my notebook
Uses alt (normal) method.
Better is this one for Micron's // RAS is 3xCAS








For DR , you genuinely need to worry about higher tRDWR.
And Double tWR. Double RTP you have to test, if it does show benefits
Nothing else really

Give me an Aida64 screenshot and we can work on it


----------



## The_King

@Veii Was waiting for you to do the update on Micron Timing. lol

3600 CL16-18-18-38-58 is XMP timings i just used that. I know I should not. 
Here is AIDA64 numbers. I locked the CPU in the BIOS to 4450 higher than this I hit the thermal limit on my Air cooler in Y-cruncher times get worse.
















My AIDA64 with 4200 same board but different CPU. Still lose performance in Y-cruncher here as well.


----------



## Veii

The_King said:


> @Veii Was waiting for you to do the update on Micron Timing. lol
> 
> 3600 CL16-18-18-38-58 is XMP timings i just used that. I know I should not.
> Here is AIDA64 numbers. I locked the CPU int he BIOS to 4450 higher than this I hit the thermal limit on my Air cooler in Ycruncher and times get worse.
> View attachment 2584987


Now we have a baseline and you can test stuff for me 
Your L3 access time is horrible tho. Win 11 ?
Ah might be fine for an allcore. 4.85 = 10.9, 4.75 should be 11.1...yes nvm, it's fine 
Write is correct too 
But your cLDO_VDDP is a bit high. That's for 2:1 mode, eh whatever

Soo first compare tRAS 45, tRC 63


The_King said:


> @Veii Was waiting for you to do the update on Micron Timing. lol


I should 
Especially now that Anta pushes me with JEDEC. SCL's will need a closer inspection
Minimum RDRD SCL should be 4 if i'm not mistaken. CCDL should not scale by DR and depend on tBURST
Burstlength should not be 16 ooor ?
CCDLWR doesn't seem to be a thing on AMD when pushing instant writes through. WRWR SCL should be able to stay at 4 too


The_King said:


> My AIDA64 with 4200 same board but different CPU. Still lose performance in Y-cruncher here as well.


4200 should be 33599 MB/s write 
Quite strong throttle~


----------



## The_King

@Veii I am on Windows 10.
I can bring my L3 Latency down to 10.7ns when using -CO and CPU set to Auto. Should I change CPU clocks to AUTO or leave it locked @ 4450 all core?


----------



## Veii

The_King said:


> @Veii I am on Windows 10.
> I can bring my L3 Latency down to 10.7ns when using -CO and CPU set to Auto. Should I change CPU clocks to AUTO or leave it locked @ 4450 all core?
> View attachment 2585002
> View attachment 2585001











Mmm better
But not fully happy
Please increase tWTR_S to 4 , and drop tWRRD to 1
Also increase tRDWR to 10 & tRCDWR to 18


The_King said:


> I can bring my L3 Latency down to 10.7ns when using -CO and CPU set to Auto. Should I change CPU clocks to AUTO or leave it locked @ 4450 all core?


Less variables for now


----------



## The_King

Veii said:


> View attachment 2585003
> 
> Mmm better
> But not fully happy
> Please increase tWTR_S to 4 , and drop tWRRD to 1
> Also increase tRDWR to 10 & tRCDWR to 18
> 
> Less variables for now


System failed to post had to reset CMOS twice. tried RDWR 10 and 11 with WRRD 1. Have some issue running it at WRRD 1 unless I chuck too much voltage it may work 1.55V
Got WRRD 2 to post.


----------



## Veii

The_King said:


> System failed to post had to reset CMOS twice. tried RDWR 10 and 11 with WRRD 1. Have some issue running it at WRDD 1 unless I chuck too much voltage it may work 1.55V
> Got WRRD 2 to post.


I see, i'm sorry
Copy ala write part of it are not fine
Reads are now. tRDWR 9 was too low

Now drop all SD & DD's to 1


----------



## The_King

Veii said:


> I see, i'm sorry
> Copy ala writes are not fine
> Reads are now. tRDWR 9 was too low
> 
> Now drop all SD & DD's to 1


No issues. I appreciate your time and help. Sorry took so long on my side. 

Will running SD and DD 1s be OK on DR DIMMS?


----------



## Veii

The_King said:


> No issues. I appreciate your time and help. Sorry took so long on my side.
> 
> Will running SD and DD 1s be OK on DR DIMMS?


You're actually right, keep forgetting you're running DR's
tRDRD SD to 4 // if it refuses to boot, try 8
tWRWR SD 2 // if it refuses to boot, try 4
the rest of SC, SD, DD's to 1's🙇‍♂️

it should not bother as you already waste delay and writes are instant, but we can try step by step


----------



## Bloax

Veii said:


> ...
> For memOC Zen5 will be great, but on stock 13th gen/Zen4 are equal. The only change is indeed the Boardprice.
> Maybe if i was in Broadcasters shoe's and start from scratch ~ I'd buy two times AMD
> One cheap low end board, one highend
> Reuse the "low end" later as encoding system
> (which is were AM5 shines a bit more once CO tuned)
> And then wait for an arch update, to have fun with memOC
> ...


I'm mostly talking from the perspective of Serious Vidyagaming -

In throughput tasks, Zen4 is a more appealing choice even if RAM OC doesn't go much further beyond simple "make DDR5 timings not stupid" tweaks for now.

Most people don't engage throughput-heavy tasks though, so Flawless 240 Hz Gaming(tm) in titles where frames matter - and "Good Enough" where frames don't matter - with *much less microstutter whack-a-mole* just sounds like a much more "sound of mind", not-a-tech-masochist choice to me.

240+ Hz monitors are a scam right meow anyway, lol. :_ )
no less because you're not gonna have a system that can reliably deliver that many frames (unstable frametimes = The Devil) until Raphael-X3D, let alone the fact that LCD Trash panels do not have the pixel response times for it


----------



## The_King

Veii said:


> You're actually right, keep forgetting you're running DR's
> tRDRD SD to 4 // if it refuses to boot, try 8
> tWRWR SD 2 // if it refuses to boot, try 4
> the rest of SC, SD, DD's to 1's🙇‍♂️
> 
> it should not bother as you already waste delay and writes are instant, but we can try step by step


RAM didn't like these changes. After some time testing what boots
WRWR SD wont boot below 6 can do some more testing later almost 3 am here so will do any more changes you have later today.
Thanks once again for your time.


----------



## Veii

The_King said:


> Thanks once again for your time.


Rest well !
Maybe run a 25 cycle stability test in the meantime


----------



## The_King

Veii said:


> Rest well !
> Maybe run a 25 cycle stability test in the meantime


Did a quick run this morning colder temps so that helps, lost some time but the runs in Y-cruncher seem much more stable now. Will run TM5 today 









Edit:
So I forgot to hit the apply button when I did the above run but doing so got me 95.086s.
The same CO that got me the better times yesterday is now throwing a hissy fit. 
CO tuning really is weird and frustrating sometimes by increasing -CO you get better stability other times its the opposite way around.
But I Locked the cores to 4450 so that one core does not think its Superman when it gets voltage and tries to boost to 5Ghz and crashes windows. (Core 2) 
(I am using CO with locked Cores to also reduce the temps as well and it does help in this regard)

Edit 2:
Some improvements i was able to do today DDs to 1

Global C-state on (all my previous runs it was on)

















Global C-state off (Latency is worse here)


----------



## dimkatsv

Finally. Somehow i managed to actually increase one single primary timing by (maybe can do it only by, but only if it even posts. And it may not. Easily may not. Tbh i am not even sure i can easily restore these settings after BIOS reset)
I knew my 3800 could boot at even 1.35V, just unstable. But to stabilize it i needed whole 1.5V (1.52 basically). . .
So after i managed to reduce single primary i could run this stable with 1.4V easily. Huge difference, imo.



















To just attempt to run 1T GDM OFF i MUST!!! use 60 ohms ClkDrvStr, and i am not sure if i am ready to do this
And i know, performance could've been much better with tighter tRCD and 1T. But, oh well... I will try tRCDRD at 21

UPD: Seems like tRCDRD=21 worked fine. Test for stability is actually kind of fast for me. Because TM5 will throw me error in 18 minutes if it is unstable (this is only for my hardware. It just either works well, or don't, barely anything in between).

UPD 2: I also forgot that i had TSME enabled (auto, but it affects latency). And yeah, W11, L3 cache latency is really inconsistent. can go from 10.8 to 11.8 or around that


----------



## Giacomo Coppi

Hello everyone, thaks a lot for this thread it's really full of nice info and useful 
My sistem specs are :
5600x
b550 asus strix f with 1.2.0.3 c bios that should be the last without EDC bug
16gb x 2 of g skill 3200mhz cas14 xmp 1.35v

I tryed many ram overclock in those years and actually i am using this one below , it's a decent profile if you ask me but now i'd like to have more bandwidth and i would like to go up to 4000mhz .










I've seen that i can run 2000 IF without any problem but i am not able to boot 4000mhz on ram , any suggestion ?


----------



## The_King

Veii said:


> Rest well !
> Maybe run a 25 cycle stability test in the meantime


Well testing 32GB sucks! tWR 12 didn't even make it pass the first cycle.
Longest test I ran using TM5.









I understand now why you said throw the first results in AIDA64 out. On second run write was 31465 MB/s. Not much more left to tighten here unless I go CL 14?


----------



## dimkatsv

The_King said:


> Well testing 32GB sucks! tWR 12 didn't even make it pass the first cycle.
> Longest test I ran using TM5.


Well, test duration is directly proportionate to RAM capacity and reverse proportionate to RAM speed. 
Also... Try Anta absolute)). 25 cycles will take you about 18 hours to pass)


----------



## Veii

The_King said:


> Edit 2:
> Some improvements i was able to do today DDs to 1











In the realm of acceptance, but still not perfect
Copy misses bandwidth, should be 56K+
We lost ~500MB/s Copy (write portion of it) with the change in Refresh method.

WRWR SD, is not possible to run as 4 ?
Maybe with tradeoff to tWRRD as 4 ?

If that is a boot issue, keep it how it is and try to scale
tRRD_L +1 , tWRRD SD - 1
or tRRD_L to 6 & tWTR_L 12
^ check if that lets you lower WRRD_SDs

31520 is just an overboost issue.
Might try to find CBS, NBIO DF-CStates or it's in CPU common options/SMU
Global C-States need to be on.

Also please always press the "run" bottom, don't bench only a row and dont cherry pick values.
Yet wait like 5-7 sec after the first bench.
On first init, sample needs some load, before it settles down with C-States. Only the 2nd run onwards can be valid

EDIT:
Your tRTP & WR is free
and your WRite section is free

RRD_S/WTR_S is fixed, SCL is fixed.
tRAS is fixed
You have to balance it out with:
WRRD, WRRD SD, WTR_L & RRD_L, WR, RTP 
// some delay is too long, or rather one is too short

...actually, please verify that tPHY is still 26 on both dimms


----------



## dimkatsv

Giacomo Coppi said:


> I've seen that i can run 2000 IF without any problem but i am not able to boot 4000mhz on ram , any suggestion


Those anticheats aren't helping , as we are not seeing your voltage for 3800.
But usually answer is to "loosen timings and increase voltage", just to see if 4000 is possible, then finding tight timings, lowering voltage a bit if possible and tightening rest of timings.

GZ with CPU that can run 2000 IF. . . My 5600X won't go over 1933 despite everything i tried. Even at 1.2.0.3 (with unlimited VDDG)
Also EDC bug rarely can hurt you unless you run PBO frequency override without curve optimizer. Depends on base frequency as well, i guess.
And there is a way to overcome it. VID Limit is being set as capped at boot. So if you change EDC limit from system, VID limit won't be overwritten.
Like... Here is an example.


http://imgur.com/a/dEF2HLb

And tool i use to set EDC limit is PBO Tuner (and task scheduler with arguments to program to set it every time at login)


----------



## dimkatsv

Veii said:


> WRWR SD, is not possible to run as 4 ?
> Maybe with tradeoff to tWRRD as 4 ?


tRDRD_SD = 4
tWRWR_SD = 6
are normal for DR stick. It rarely goes lower than that. Usually system just won't POST

Also. . .



The_King said:


> Some improvements i was able to do today DDs to 1


Why won't you. DD timings just don't work on 2x2R stick configs. This timing only applies if you have several sticks per channel, not several ranks.
Also if your tRC is stable, you can just drop down tRAS straight to 21. It also doesn't work on Ryzen configs.
And tRCDWR can go straight down to 8, because you don't care about data integrity in cells straight before writing to them. tRCDRD on other side is REALLY important.


----------



## Veii

dimkatsv said:


> Usually system just won't POST


What's the reason for "usually" ?

Usually people depend on different RefreshCycle (mode) prediction
I go by efficiency, not by lowest possible.
Lowest possible is too blind approach


----------



## The_King

Veii said:


> View attachment 2585185
> 
> In the realm of acceptance, but still not perfect
> Copy misses bandwidth, should be 56K+
> We lost ~500MB/s Copy (write portion of it) with the change in Refresh method.
> 
> WRWR SD, is not possible to run as 4 ?
> Maybe with tradeoff to tWRRD as 4 ?
> 
> If that is a boot issue, keep it how it is and try to scale
> tRRD_L +1 , tWRRD SD - 1
> or tRRD_L to 6 & tWTR_L 12
> ^ check if that lets you lower WRRD_SDs
> 
> 31520 is just an overboost issue.
> Might try to find CBS, NBIO DF-CStates or it's in CPU common options/SMU
> Global C-States need to be on.
> 
> Also please always press the "run" bottom, don't bench only a row and dont cherry pick values.
> Yet wait like 5-7 sec after the first bench.
> On first init, sample needs some load, before it settles down with C-States. Only the 2nd run onwards can be valid
> 
> EDIT:
> Your tRTP & WR is free
> and your WRite section is free
> 
> RRD_S/WTR_S is fixed, SCL is fixed.
> tRAS is fixed
> You have to balance it out with:
> WRRD, WRRD SD, WTR_L & RRD_L, WR, RTP
> // some delay is too long, or rather one is too short
> 
> ...actually, please verify that tPHY is still 26 on both dimms


Can confirm it wont go below 6 tried even 5 no boot.

94.6 is not far of the 94.4 best run I did with unstable RAM timings.











> If that is a boot issue, keep it how it is and try to scale
> tRRD_L +1 , tWRRD SD - 1
> or tRRD_L to 6 & tWTR_L 12
> ^ check if that lets you lower WRRD_SDs


Will try this.


----------



## Veii

The_King said:


> Can confirm it wont go below 6 tried even 5 no boot.


Ok soo "not yet"
Still halfdone work tho~

Writes are delayed somewhere ~ they are possible to be instant (1tCK) on AM4
You drop potential bandwidth a lot with RDRD SCL 8 ?
Some value definitely is too low atm, and a single one too high preventing rest to go lower
* you can't force tCCD behavior, neither tXP behavior, soo you got to change timings slowly till it switches itself down

Don't worry about anything from Benchmate
It will improve at any point. It only "might not" if you trade.
But if you improve across the whole board, there is no reason anything else won't
That's what i use Aida for, only efficiency tracking.
If your change does nothing, it might still bench better, but you cause another rabbit hole of a value potentially too being low.
Sooner or later this value (offbalance) will be the issue of stability on higher clock.


----------



## Veii

The_King said:


> Will try this.


Please also try if WRWR SCL 2 will post 
(its far to low, but out of curiosity)
As said


Veii said:


> You have to balance it out with:
> WRRD, WRRD SD, WTR_L & RRD_L, WR, RTP


~ one timing of those is too high
~ and one or two are too low, eating 500MB/s of copy


----------



## dimkatsv

Veii said:


> What's the reason for "usually" ?


It will either POST or not POST. Nothing in between. Complete lottery.
Especially as his aren't S8B. Mine also won't go below 6


----------



## Veii

dimkatsv said:


> It will either POST or not POST. Nothing in between. Complete lottery.


The outcome doesn't explain the reason for it
It's not all random and lottery


----------



## The_King

TWR 14 RTP 7 increased RRDL 6 and WTRL 10. This was the second run.


----------



## Veii

The_King said:


> TWR 14 RTP 7 increased RRDL 6 and WTRL 10. This was the second run.
> View attachment 2585195


loss of 150-200mb in read (expected by slower RRD_L)
and slight improvement on write, but still 350MB/s away of target
// not good outcome , and likely still wont allow WR SD to go lower 

Try tRRD_L 5
maybe tWR was ! too low


----------



## The_King

Veii said:


> loss of 150-200mb in read (expected by slower RRD_L)
> and slight improvement on write, but still 350MB/s away of target
> // not good outcome , and likely still wont allow WR SD to go lower
> 
> Try tRRD_L 5
> maybe tWR was ! too low


I will work on this abit and try a few different values and try to get it to 56K copy and not bring read down.. 
SCL at 2 or 3 don't make it into windows BSOD.


----------



## dimkatsv

Veii said:


> The outcome doesn't explain the reason for it


Ok. What these timings correspond to?
Delay between two consecutive reads or writes that are happening on same or different dimm, but different banks.
Soo... shouldn't too short of timing cause too much stress on controller so it is unable to actually switch in time?
SCL = same bank
SC = same rank / different bank
SD = same dimm / different rank
DD = different dimm

SCL = 4 actually allows for highest potential bandwith iirc. Because RRD_S/_L all have limitation with tFAW, which is usually 16. After that to not degrade performance controller switches access to different bank instead. SCL = 3 or 2 gives you more consistent latency instead.


----------



## ocisdead

@Veii 

I wanted to push 1.5v through my 2x8 kit but I have read through most of your posts regarding RTT values and you mention how 0/0/5 can be dangrous for a0 PCB sticks. I have tried some of your recommended RTT values such as 7/0/6, 7/3/6, 6/3/5 at 1.5v and while some can boot into windows and run y-cruncher/tm5 without errors they will not retain stability after a restart. The same timings with lower voltage and the default 0/0/5 are 100% stable even through multiple boots and restarts.

Maybe the problem is because the motherboard is x370 crosshair T-topology? Do you have any other RTT suggestions specific to my setup that can be safe with higher voltage or should I just keep vdimm around 1.425 and stick with the stable 0/0/5?


----------



## Veii

dimkatsv said:


> Soo... shouldn't too short of timing cause too much stress on controller so it is unable to actually switch in time?


In practical theory, you are fully right
I'm sorry, I shouldn't be rude either.
Can't blame anybody for keep reading "halfway wrong" stuff,
but certainly can blame people for being halldomes and not trying to research themselves~

Anywho,
Its more because everyone , and from personal viewpoint i mean over 95% if not 98% of people come here and write guides they read about something like this:








^ not my drawing

By reading JEDEC papers and expecting that only their half-visible-timings, which ontop are "different and shorted" by AMD
With completely different IMC Firmware ~ by a different Vendor
Will match up with the same behavior and working properties on typical Intel systems, because global Jedec says so

It was visible by you mentioning 
"always drop tRAS to the lowest possible [21] and let high RC do it's job"
There are many problems here, but there is not only one correct way
~ soo i don't want to judge what has been also done to me often. Often people just make mistakes


Spoiler: tRAS



*tRAS*,
lowest is irrelevant first of all 
not only does it dynamically adjust up to what sensing IO detects Row's chargestatus is
// tRFC doesn't charge them fully , and read operation doesn't discharge them fully
In the normal theory, there is no other option except for you to wait out on tRTP to finish in its full extend before RAS can be started.
If RAS wants to start too early, it will be paused and put in wait-for-action state.

Memory is dumb, mostly
And while it can check amount of charge left and predict recharge properties by thermals (IF sensor is existent)
// check that everything is recharged post REFI and skip one single RTP delay
it mostly close to always can not, soo actually can not predict the average timing it will need & it does not supply tMAW.tMAC (RC_Page)
This means,
it has nothing to look up for average discharge delay nor cell lookup database and pretty much can not do anything except insert tAL delay to compensate and multiple attempts "try" to run tRAS when its time comes
// this causes huge efficiency loss and also random additive delay ontop ~ for no reason except user being lazy and depending on autocorrect

But this also means, everything is halted. Like for time mid tRFC , time mid-tRAS is halted.
This feature, works on AMD ✅
It is supported by IMC Vendor and is supported by close to all DDR4 dimms ~ the tRAS halting.
The tRAS extension although, might be not but i am 92% confident it does support it on Samsung PCBs.


=================
Next problem,


Spoiler: tRC



*tRC*
In Jedec and on Intel Firmware used , people dont see tRC
They don't see which of those 5 modes can potentially be switched to by MSR








And they just expect that StandardRC & ExtendedRC are common operations.
Soo now actually 99.X% of Intel people , all drop tRAS as lowest possible and don't care.
Same event still is happening, but at least a little fraction knows JEDEC and tries to follow it. Most don't and run timings far bellow BurstChop and far bellow realistic ones.
Those timings run , expire, and just loop in the same exact length

Now this is here the same on AMD, this last issue.
tRC is NOT stretchable on AMD and NOT postponable. ❌
This featureset does not work on IMC FW, and i can confidently tell you that.
It can not be time-broken and if too low , it does halt, and just re-loop.
Like other similar timings that are far bellow realm of possibility.
It does loop in its fullest extend ~ if sensing IO detects tRP is needed for it.
In this case, such a delay is around 20-30ns long but it's masked by efficiency.
// Memory is dumb but controller is not , it can switch to a more efficient refresh method.
Realistically the drop is 2-3ns by "too low tRC"


=================


Spoiler: Micron's



Micron's now,
are unique.

They do support 3x CAS bef RAS refresh mode and likely both Samsung & Micron PCBs do support more.
// Samsung do not support that to current research
There is still a math with "Optimal row buffer locality", to utilize half charged cells ~ but i don't know where or how it supports it... Amateur still
The very least i don't follow "its this because it has to be" rules and do my own research.


Soo confidentially can tell you that RAS too low and RC too low, are big issues 

You likely understand a bit, but please don't trust everything you read.
Intel systems are different & now AM5 DDR5 is different.
Just because JEDEC defines a realm of possibilities,
it does not mean they are usable and equally followed by DIMM PCB designers'.
Nor does it mean when DIMM PCB supports it, that IMC FW will also know about it and can execute.


----------



## Veii

ocisdead said:


> Maybe the problem is because the motherboard is x370 crosshair T-topology? Do you have any other RTT suggestions specific to my setup that can be safe with higher voltage or should I just keep vdimm around 1.425 and stick with the stable 0/0/5?


T-Topology is weaker per slot
There should be no issue on 1.52
Dual Rank on T-Topology is a trouble, but my X370 Taichi is half-dead still
(Socket corrosion & AMD PCH patch trouble)
// soo don't count me on that and test yourself please

Generally you will notice near-dead scenario. Once channels start to drop out and memory appears crashing.
Dimms mostly PCB, dies first but before that you see one channel missing or gold contacts be charred & oxidized.

You will notice what is fine, trust me.
Mixing A0 with A2's can be a trouble on stock RTTs and running above 1.53-1.54 will be a trouble unless adjusting RTTs
But you definitely will notice that something is wrong. And then visually expecting traces on sunlight (not room light)
Will show you charred traces















Can't find the other examples atm, but on normal sunlight it's quite noticeable.
Its oxidation tho and can be cleaned, but shows that it's too much for them & needs redesign
No signs of charring on 1.65/1.68v daily on my A0 Vipers & Rev.E's that cap at 1.72ish

But charred AM5 vipers twice, and got charred A2 4400 (DDR4) Vipers already
Soo i guess you'll notice when it's too much ~ on Daisy chain around 1.54v on A0's "stock RTT" is too much for example. After 1.51 they become super unstable. Same dimms like their 1.66 now


----------



## Veii

The_King said:


> I will work on this abit and try a few different values and try to get it to 56K copy and not bring read down..


We traded it by changing refresh method








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


https://hwbot.org/submission/4927258_gunzi_y_cruncher___pi_2.5b_ryzen_7_5800x_1min_32sec_159ms If you want to score on y-cruncher could be easier with Micron. Check the #1 ranking 5800X, it's using 5500 MHz static OC at memory clock 3800 MHz CL14. While the #2 is just 4825 MHz CPU but with...




www.overclock.net




56000 Write target
And by upping tWTR_S to 4
















But it's already close, just needs little fixing on Writes
Anything you'll want to try for today ?
I might try to get a Rev.E system going, to have a bit of fun with it
But we can't compare that either.
DR is a bit different
I don't know either if i can get CAS 14 to run and beat that 
















^ this s*** on writes, i kept them too balanced, not read focused & was more amateur back then
Oh i do have work for you @The_King
Get your Rev.E's to be 1.62v stable with slightly different RTTs~
Still at RTT_WR 80








Probably 32ohm, with RTT_PARK /5 or /6 on 1.6+ volt
Potentially also CAD 60-20-30-24 or 60-20-40-24
Not entirely sure on DR, but PARK should be near that /5 range for DR. /4++
// then you can maybe lower primaries a bit (afterwards) but powering has main prio


----------



## The_King

Veii said:


> We traded it by changing refresh method
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> https://hwbot.org/submission/4927258_gunzi_y_cruncher___pi_2.5b_ryzen_7_5800x_1min_32sec_159ms If you want to score on y-cruncher could be easier with Micron. Check the #1 ranking 5800X, it's using 5500 MHz static OC at memory clock 3800 MHz CL14. While the #2 is just 4825 MHz CPU but with...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 56000 Write target
> And by upping tWTR_S to 4
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But it's already close, just needs little fixing on Writes
> Anything you'll want to try for today ?
> I might try to get a Rev.E system going, to have a bit of fun with it
> But we can't compare that either.
> DR is a bit different
> I don't know either if i can get CAS 14 to run and beat that
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ^ this s*** on writes, i kept them too balanced, not read focused & was more amateur back then
> Oh i do have work for you @The_King
> Get your Rev.E's to be 1.62v stable with slightly different RTTs~
> Still at RTT_WR 80
> View attachment 2585233
> 
> Probably 32ohm, with RTT_PARK /5 or /6 on 1.6+ volt
> Potentially also CAD 60-20-30-24 or 60-20-40-24
> Not entirely sure on DR, but PARK should be near that /5 range for DR. /4++
> // then you can maybe lower primaries a bit (afterwards) but powering has main prio


Will take a break tonight but will try get higher MCLK stable tomorrow and give those settings a try.

Trying to source a good AIO my current CPU Air-cooler (PH-TC14PE CPU) is holding back alot of potential that this 5800X has. Hopefully I get a good Cyber Monday deal.
If you have any recommendation please let me know. Not in the states no importing duty customs is too high main option for me is Amazon.in.



Amazon.in : aio liquid cooler



Sweet!


----------



## dimkatsv

Veii said:


> It was visible by you mentioning
> "always drop tRAS to the lowest possible [21] and let high RC do it's job"
> There are many problems here, but there is not only one correct way



Ah, sure, i am not forcing anyone of course. It is just on AMD tRC have much higher importance than tRAS, as AMD can ignore tRAS when it is too low and only follow tRC.
Intel cannot do that, so you must be really careful with tRAS instead for them (and they don't have tRC).
if tRC is too low it will often just BSOD fast, at least that's how it is for me. 58 works, 56 will not boot into Windows (or will just freeze my system in matter of minutes). No matter what tRAS i use (Well, unless i go with tRAS that is higher than tRC, i guess)

You can do research for higher performance, maybe there is balancing that exist where higher tRAS will be more effective on particular situation it is used in, as this way you can possibly get tRC to bit lower value. That part is true. But gosh that amount of balancing and stability tests. At some point gains are too insignificant for work spent for most people.

Also my source is quite good for this. I trust him a lot as he proven very knowledgeable.









It is just... for his tRC that tRAS of his looked bit high. Well, granted it is Micron.


----------



## Veii

The_King said:


> If you have any recommendation please let me know. Not in the states no importing duty customs is too high main option for me is Amazon.in.
> 
> Amazon.in : aio liquid cooler
> Sweet!


Coolermaster did an Advanced RMA for their AIOs (close to all are affected)
Deepcool usually are fine, all are asetek after all but track liquid temp. At first they perform quite good
Arctic liquid freezer 2 also had the same problems of unclean distilled water and corrosion , but still remained the best performing on Alu AIO (many Asetek designs had the same "by time" flaws)
NZXT generally perform well but it's a boutique product with boutique pricetag
Bequiet AIOs (new RGB series) perform well too, but mostly because of the fans

I would recommend the Alphacool Aurora Pro series
But that holds a pricetag on full copper components ~ no difference to own custom loop, maybe slightly cheaper and expandable

If i remember correctly, bitspower and bykski have cheap Custom Loop Kits.
Currently price to perf ratio on EK kits is also not too bad, although that is a boutique product too.

Early Alphacool LT series was a great cheap aio, on Matisse days
But now LiquidFreezer 2 replaced it and is cheap.
You can't go wrong with those 3, but keep the temps on eye. Very likely all 3 will need once an RMA after 6-8 months.
Soo might as well save up and get a softtube watercool kit. Blocks generally cost ~45-60$, tubes around 20$, rads 60-80, 3 fans 30-40$
There are for sure kits for 200-250$.
Alphacool Aurora Pro is for near 180-220$ up to region but technically also a custom loop kit ~ as AIO


Veii said:


> Very likely all 3 will need once an RMA after 6-8 months.


Close to all Asetek AIOs are fixed now, but you don't know how long the product you'll receive has been sitting on a shelf.
Deepcool is just cheap, soo you can't go wrong. But Artic Freezer 2 performs better.
Any Aluminum AIO you'll pick might over 60% likely, fail once in 6-8 months. You never know how old the batch was, as the change was just recently


----------



## Mr.Sunshine

Here my daily driver setting.


----------



## The_King

Veii said:


> We traded it by changing refresh method
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> https://hwbot.org/submission/4927258_gunzi_y_cruncher___pi_2.5b_ryzen_7_5800x_1min_32sec_159ms If you want to score on y-cruncher could be easier with Micron. Check the #1 ranking 5800X, it's using 5500 MHz static OC at memory clock 3800 MHz CL14. While the #2 is just 4825 MHz CPU but with...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 56000 Write target
> And by upping tWTR_S to 4
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> But it's already close, just needs little fixing on Writes
> Anything you'll want to try for today ?
> I might try to get a Rev.E system going, to have a bit of fun with it
> But we can't compare that either.
> DR is a bit different
> I don't know either if i can get CAS 14 to run and beat that
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> ^ this s*** on writes, i kept them too balanced, not read focused & was more amateur back then
> Oh i do have work for you @The_King
> Get your Rev.E's to be 1.62v stable with slightly different RTTs~
> Still at RTT_WR 80
> View attachment 2585233
> 
> Probably 32ohm, with RTT_PARK /5 or /6 on 1.6+ volt
> Potentially also CAD 60-20-30-24 or 60-20-40-24
> Not entirely sure on DR, but PARK should be near that /5 range for DR. /4++
> // then you can maybe lower primaries a bit (afterwards) but powering has main prio


Could not get ProcODT 28.2 to boot. this ram does not seem to like it or the CPU.

With DR DIMMS seems 4200 is not possible. ( I can get 4200MT 1:1 with My Micron REV. B 16GB Single Rank DIMMS)
4133MT DR with 1:1 is not bad for a B450 board I think?

I seem to be hitting a 55ns wall when it comes to latency. All combos that I have tried don't want to go lower that 55ns. <----Maybe a Dual rank RAM Dimm limitation?
With CPU frequency not locked to 4450 L3 cache is not thrash anymore. 
Apparently my math is bad again 20+48=68 and 19+38=57.


----------



## ReyReverse

The_King said:


> Could not get ProcODT 28.2 to boot. this ram does not seem to like it or the CPU.
> 
> With DR DIMMS seems 4200 is not possible. ( I can get 4200MT 1:1 with My Micron REV. B 16GB Single Rank DIMMS)
> 4133MT DR with 1:1 is not bad for a B450 board I think?
> 
> I seem to be hitting a 55ns wall when it comes to latency. All combos that I have tried don't want to go lower that 55ns. <----Maybe a Dual rank RAM Dimm limitation?
> With CPU frequency not locked to 4450 L3 cache is not thrash anymore.
> Apparently my math is bad again 20+48=68 and 19+38=57.
> 
> View attachment 2585341
> View attachment 2585343
> 
> View attachment 2585342


I remember last time the latency you post is around 51~52ns something. Why 55ns now? try smash pll to 2.5v, see can your CPU all core full load at 4.8ghz with this fclk. Damn.... I miss Ram OC so much


----------



## The_King

ReyReverse said:


> I remember last time the latency you post is around 51~52ns something. Why 55ns now? try smash pll to 2.5v, see can your CPU all core full load at 4.8ghz with this fclk. Damn.... I miss Ram OC so much


That must have been with my 8GB SR dimms or my Micron 16GB single rank dimm.

No option to adjust VDD18 / PLL would be great if I could.
Going above 2000 FCLK 1:1 is an issue for me has performance takes a hit in all other benchmarks.

Whats stopping you from OCing RAM? Its lots of fun most of the time. 

Found the post (Was my Micron 16GB SR DIMMS) @Veii Was able to run WRRD 1 and WRWR SD 4 here since these are SR DIMMS ?








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


You may need more SOC,IOD or VDD18, maybe all. Thanks for that I did increase it after reading your comment I went even higher and that did improve performance. VSOC 1.23V IOD 1.15V. (y) I can't adjust VDD18 on this board. There is no option in the BIOS to do that. How high can one go on IOD...




www.overclock.net


----------



## Artylol

Artylol said:


> I'm noob, it is my first system and I just downloaded (lol) ram OC from internet. My setup is B550 Aorus pro AC, Ryzen 5 5600 (non x) stepping B2, RAM Patriot Viper Steel 4000 CL16. Dont pay attention to IF clock, it is intentionally uncoupled because IF2000 gives WHEA's. I have 3 issues:
> 
> 1) tWTRL=8 causes anta777 errors.
> 2) Cant boot CL14 even at 1.5V VDIMM. tRCD and tRP reduces effortlesly
> 3) tRTP cannot be set to 5. If I set it to 5, it s hows 6 in ZenTimings.
> 
> Please advice what I'm doing wrong and if possible how to further improve timings for performance. Current setup passes 20-30 minutes of anta777. Also note I have 5 bucks cooler which idles CPU at 60 degC, while waiting for Noctue D15 from aliexpress.
> View attachment 2584484
> 
> 
> Edit: Sharing IF2000 results with proper voltages
> View attachment 2584489


@Veii
Can I ask you to take a look for improvement?


----------



## Veii

Artylol said:


> Edit: Sharing IF2000 results with proper voltages
> 
> 
> Artylol said:
> 
> 
> 
> @Veii
> Can I ask you to take a look for improvement?
Click to expand...

Write here and somebody will see. Here and there happens that it's missed
Outside of WHEA
You throttle. Write has to be 31999 for 2000 FCLK instead of 31991








Proof me stability (1usmus_v3 config 25 loops), and Aida64 before and after
If unstable, increase tRRD_S , tWTR_S, SCL's to 5 ; (tFAW to 4* tRRD_S)

You don't need to run such high cLDO_VDDP
These are not dual rank, and you dont run 2400+ MLCK
Drop it to 900mV. Maaybe 950 if you really need it ~ but i doubt
Drop VDDG CCD to 980mV and IOD to 1040+
SOC mostly needs between 1175-1225 ~ it can need more with lower procODT

If drop on cLDO_VDDP creates memory stability issues
Change CAD_BUS settings slightly around . 40-20-30-24 or 40-20-40-20


----------



## Luggage

The_King said:


> That must have been with my 8GB SR dimms or my Micron 16GB single rank dimm.
> 
> No option to adjust VDD18 / PLL would be great if I could.
> Going above 2000 FCLK 1:1 is an issue for me has performance takes a hit in all other benchmarks.
> 
> Whats stopping you from OCing RAM? Its lots of fun most of the time.
> 
> Found the post (Was my Micron 16GB SR DIMMS) @Veii Was able to run WRRD 1 and WRWR SD 4 here since these are SR DIMMS ?
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> You may need more SOC,IOD or VDD18, maybe all. Thanks for that I did increase it after reading your comment I went even higher and that did improve performance. VSOC 1.23V IOD 1.15V. (y) I can't adjust VDD18 on this board. There is no option in the BIOS to do that. How high can one go on IOD...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> View attachment 2585362


Not DR limitation but perhaps “not B-die limitation”?


----------



## Giacomo Coppi

dimkatsv said:


> Those anticheats aren't helping , as we are not seeing your voltage for 3800.
> But usually answer is to "loosen timings and increase voltage", just to see if 4000 is possible, then finding tight timings, lowering voltage a bit if possible and tightening rest of timings.
> 
> GZ with CPU that can run 2000 IF. . . My 5600X won't go over 1933 despite everything i tried. Even at 1.2.0.3 (with unlimited VDDG)
> Also EDC bug rarely can hurt you unless you run PBO frequency override without curve optimizer. Depends on base frequency as well, i guess.
> And there is a way to overcome it. VID Limit is being set as capped at boot. So if you change EDC limit from system, VID limit won't be overwritten.
> Like... Here is an example.
> 
> 
> http://imgur.com/a/dEF2HLb
> 
> And tool i use to set EDC limit is PBO Tuner (and task scheduler with arguments to program to set it every time at login)


Thanks a lot for your useful reply, i wasn't aware about that i could set edc limit from system and in this way i could update my bios to last version .
my 5600x looks like a good bin, when i did ctr2.1 test it was rated as a platinum ( i did all the bios setting properly not to cheat that prograsm result ) but probably in my hands it's not able to shine like it should, i hope to success with your help guys 
Actually i reverted the cpu stock and i started to overclock ram again to get better results, i will overclock cpu with pbo2 +200mhz and CO after ram tuning will be finished .


After your suggestion i loosened timings and i tryed to go over 3800mhz 1:1 with IF and i reached 3993mhz cas 16 that unfortunately scored 1 error in memtest5 that shouldn't be a problem to solve.


















My ram voltage is set to 1.50v, win 10 installation is ok but i run many programs in background like corsair icue, samsung magician ...

i tryed many times to reach 4000mhz with 2000if but i still cannot boot it and i don't know what to change , i tryed various proc odt settings , clkdv strenght , the only setting i have to try is to lower mem vtt voltage below 0.75 .


----------



## dimkatsv

Giacomo Coppi said:


> Actually i reverted the cpu stock and i started to overclock ram again to get better results, i will overclock cpu with pbo2 +200mhz and CO after ram tuning will be finished .


Well... CPU overclock can directly affect RAM OC stability. So that is a bit of problem to solve in the future. 
Because you may hit thermal instability much more easily with S8B chips i would've wanted to eliminate such possibility in the first place (frankly, my H8DJR are just feel hot on touch when i load them with TM5 at 1.5V, and this is uncomfortable to know). You can touch sticks about 10-15 minutes into TM5 test to check how hot they are.
If you want to reduce voltage but keep most of efficiency, i would first suggest to try loosen primaries tiny bit and find golden spot. With lowering voltage a bit of course.
And for holden spot search, as i did it. 
. . . Well, except part that GDM on basically serves as mask, when almost every timing becomes only even. Even tWTRL for example (with GDM on i could use tWTRL=7, but without it, big no-no)

Disable GDM, but set 2T instead (it should also decrease latency a bit), try +2 for every primary, and check lowest voltage it can boot (it will hardly be below 1.35)... Quick check stability with Y-cruncher. Wouldn't lie to you, high chance it will be unstable enough so y-cruncher will throw a quick exception, but it won't hurt to check. 
Then i suggest you to set voltage to about +0.05 higher than value you found (As i could boot 3800 at 1.35V but it was unstable i just set voltage to 1.4 to begin work). Then reduce primaries one by one, point by point to test. 
For tCAS you mostly only need to check 1) if it boots, 2) if Y-Cruncher throws an exception. This search is fast, as tCAS usually easy enough to get failure from.
tRCDRD is tricky one. If i don't have enough voltage to support it it will throw quite consistent errors 0 and 1 during test 1 in Anta ABSOLUT. (1.4V is not enough for 20 on my sticks at 3800, only 1.5 seemingly stabilize it, and 0.1V is HUGE difference for -1 to one single primary). Closer you are to stability, later error can appear, but for me it happens at around 1.5-5 minutes of test.
For tRCDWR you can either leave it as equal to tRCDRD or set to 8. Whatever you want, performance difference will only be in really, REALLY specific tasks focused on this timing. But it also won't cause any instability (at least for 99% of people that try it).
tRAS... Either lower to 21 and check tRC first. Or set tRC to lowest possible and find tRAS instead. They are mutually exclusive. With too low value system won't boot... +2 to lowest possible should be stable. +1 requires additional testing. 
tRC... look for tRAS. Technically you may gain tiny bit of performance if you synchronize them both, but that is not confirmed. 
tRRDS tRRDL seems to be fine to try 4/4 for you. This is lowest you can possibly get
tWTRS tWTRL are bit too loose, imo. You can try 3/12, then 3/9 then 3/8 (etc tWTRL will at some point get stuck, i, for example cannot set tWTRL below 8)
Try tWR = 12
Try using 40 Ohm ProcODT. 
Try disabling RttPark (it usually won't give you much benefit, but potentially sticks will run bit cooler?). There were reports from people who say that setting RttPark to highest divider (RZQ/5 6 or 7) had lower temperature. Sadly i don't have temperature sensor on my RAM, so . . . Unable to test it myself. Disabling RttPark should completely remove resistance.


----------



## The_King

Luggage said:


> Not DR limitation but perhaps “not B-die limitation”?


I did hit 51.7ns with another Micron Kit so that is has good has Any Samsung B-die kit.
However that was also Micron Rev. B not E. 

Has you increase RANKS you suppose to get higher latency is generally what I have seen with most kits.
The main thing you can do on Samsung B-die is lower TRFC which does improves latency which does not have the same effect on Micron RAM.


----------



## 67091

Hi guys , is this impossible?


----------



## The_King

angushades said:


> View attachment 2585598
> 
> Hi guys , is this impossible?


First things I would change is increase SCLs to 4 only after you get stability you can try to drop them later.
Change tCWL to 14 (12 is probably giving you issues)


----------



## dimkatsv

The_King said:


> I did hit 51.7ns with another Micron Kit


To be fair... These are some nutty Micron sticks you got there. And insance CPU sample. 
4200 to 2100 in 1:1 mode. And tRC is only 63 for 4200... I already have 58 for 3800 on H8D, so that 63 for 4200 is really low for anything that is not S8B
They also are SR sticks, which helps a bit. 
You also run GDM=OFF and 1T at same time for 4200, which is even more insane. But i guess it is much easier for SR sticks? For me just to boot 1T GDM=OFF i need to increase ClkDrvStr to whopping 60 Ohms. And stability still isn't there. 2T gives latency penalty, GDM boosts bandwith a bit, but deals second hit to latency, by it's nature. 

Also latency can depend a on motherboard, some of them can give you less latency and easier time with RAM overclocking (to be honest, my mobo is cheap-er one, and despite being decent, isn't good for overclocking)

Here is some stats. But probably many of you are already accustomed with this page.








Zen RAM OC Leaderboards


Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...




docs.google.com


----------



## dimkatsv

angushades said:


> Hi guys , is this impossible?


try tRTP 6 / 8 / 10
Personally 1.55V is too much for daily. Check if RAM overheats, B-dies are really sensitive for heat as they have lower tRFC value ---> Easier time with data corruption higher temperature goes. 
try tCWL = tCL for beginning. 
try tWR = 12

I don't think you need to use AddrCmdSetup=56
Try ProcODT = 40 Ohms
Are you sure you must run VSOC = 1.2 (upper limit), and VDDG = 1.05V ?

Try increase all primaries to 16 and check? 
For dire end you can try to stabilize 2T command rate, i guess? Then try to work from stable point?


----------



## Luggage

The_King said:


> I did hit 51.7ns with another Micron Kit so that is has good has Any Samsung B-die kit.
> However that was also Micron Rev. B not E.
> 
> Has you increase RANKS you suppose to get higher latency is generally what I have seen with most kits.
> The main thing you can do on Samsung B-die is lower TRFC which does improves latency which does not have the same effect on Micron RAM.





http://imgur.com/zQgf7mI


----------



## Imprezzion

I might have to end up dropping my 3800C14 GDM Off 1T 240 tRFC @ 1.540v setup down a lot.. I got a cheap 3090 and slapped a waterblock on it but not a active BP. Just passive. That puts so much heat into the case right under the DIMMs so temps even with active cooling still hit 48-49c ish while gaming. And that's with 18c ambients.. I don't wanna know what 28c does in the summer lol. Hello almost 60c DIMM's. There's no way the B-Dies will ever run that stable at those temps.

It remained stable for now at 48-49c but the last time I tested it with TM5 without the active cooling running to simulate high temps they started spitting errors at ~52c so.. yeah..

Can you guys recommend a general timing setup for like, 3800 or 3933Mhz that is loose enough to have some temperature headroom for stability? I did test it once without the active cooling at 3933 16-16-16-36-52-288-2T GDM Off @ 1.450v and that seemed to hold up pretty well even at 56c so maybe I can get away with 3800 15-15-15?

I mean, I could just run DOCP 3600C16 in the summer, It's not like the 5800X3D really needs the super tight RAM but still, it's OCN, we don't run "stock" here lol.


----------



## The_King

Luggage said:


> http://imgur.com/zQgf7mI


You do realize that your 5050mhz is lowering your latency now remove 2 sticks and run the exact same settings and post the result.
With two SR dimms at just 4900Mhz i got 52ns. You should be in the 51s (the lowest I got with 2 SR DIMMS is 50.8ns)











dimkatsv said:


> To be fair... These are some nutty Micron sticks you got there. And insance CPU sample.
> 4200 to 2100 in 1:1 mode. And tRC is only 63 for 4200... I already have 58 for 3800 on H8D, so that 63 for 4200 is really low for anything that is not S8B
> They also are SR sticks, which helps a bit.
> You also run GDM=OFF and 1T at same time for 4200, which is even more insane. But i guess it is much easier for SR sticks? For me just to boot 1T GDM=OFF i need to increase ClkDrvStr to whopping 60 Ohms. And stability still isn't there. 2T gives latency penalty, GDM boosts bandwith a bit, but deals second hit to latency, by it's nature.
> 
> Also latency can depend a on motherboard, some of them can give you less latency and easier time with RAM overclocking (to be honest, my mobo is cheap-er one, and despite being decent, isn't good for overclocking)
> 
> Here is some stats. But probably many of you are already accustomed with this page.
> 
> 
> 
> 
> 
> 
> 
> 
> Zen RAM OC Leaderboards
> 
> 
> Zen 4 Sheet is sorted and verified submissions LOCKED each Thursday. Please provide proof of stability via Y-Cruncher AND a memory stability test, otherwise your submission will be removed. Refer to the FAQ for more info. MEMORY,PROCESSOR Username,Memory Latency,L3 Latency,DIMMs,Die Type,Rank,Me...
> 
> 
> 
> 
> docs.google.com


I am somewhere on that leader board.  Twice!

I have 3 ZEN 3 CPUS 5600 / 5600X / 5800X all 3 can boot well over 2000 FCLK. Nothing special about any any of them apart from my 5600X which is Dual CCD with 1 CCD disabled.

Most of the performance comes from the mobo IMHO both my B450M Mortar Max seem to have excellent memory OC capabilities.
Getting GDM of 1T is much easier with Micron than it is with Samsung B-die.

I can get GDM disabled 1T on both boards with several different sets of Samsung B-die Kits so its not golden sample board or DIMMS.

Any praises should go to the motherboard more than the CPU or RAM.


----------



## Luggage

The_King said:


> You do realize that your 5050mhz is lowering your latency now remove 2 sticks and run the exact same settings and post the result.
> With two dimms at just 4900Mhz i got 52ns. You should be in the 51s (the lowest I got with 2 DIMMS is 50.8ns)
> View attachment 2585645


It’s 2 sticks 
But I can cap the boost and see how much it does.


----------



## The_King

Luggage said:


> It’s 2 sticks
> But I can cap the boost and see how much it does.


You can see the lowest latency times on the ZEN RAM OC leader boards are all 2X8GB SR setups.
There is one DR setup that comes close but I will still stick with the statement that has you increase RANKS keeping everything else the same Latency will increase.


----------



## MrHoof

The_King said:


> You can see the lowest latency times on the ZEN RAM OC leader boards are all 2X8GB SR setups.
> There is one DR setup that comes close but I will still stick with the statement that has you increase RANKS keeping everything else the same Latency will increase.
> View attachment 2585650


There is no latency penatly from ranks as far as I can tell if Timings and CPU are about the same, my SR kit cant do CL14 it needs 1.55v for CL15.
SR/DR















Anything lower then 51.5-51ns uses 4000mhz+ or L1 HW prefetcher disabled wich can save 2-3ns(from my testing worse real world performance others reported otherwise).
edit: Still confused why SR was doing better Read, if anyone has a awnser to it I would appreciate it


----------



## dimkatsv

The_King said:


> There is one DR setup that comes close but I will still stick with the statement that has you increase RANKS keeping everything else the same Latency will increase.


It depends on RAM PCB, motherboard and blessing from above on lucky chips. Usually 2R setup will slightly increase latency.
But it is slightly, again. On other hand, 2xSR setup is MUCH easier to get to the higher clock speed. And higher clock speeds = less latency.
System config can dictate latencies as well. Like with my CPU sample and MOBO i unlikely will ever hit low latencies.


----------



## Kurt Krampmeier

angushades said:


> View attachment 2585598
> 
> Hi guys , is this impossible?


hello!
you may try the following:









i found out that TCL, TRCDRD and the *SCLs were holding it back.
both ran at 3600 with 14(16) and 2 for the SCL. but not past 3733 - VDIMM is 1.55
i have not tried GDM off past 3800MT.


----------



## The_King

MrHoof said:


> There is no latency penatly from ranks as far as I can tell if Timings and CPU are about the same, my SR kit cant do CL14 it needs 1.55v for CL15.
> SR/DR
> 
> *Anything lower then 51.5-51ns uses 4000mhz+ or L1 HW prefetcher *disabled wich can save 2-3ns(from my testing worse real world performance others reported otherwise).
> edit: Still confused why SR was doing better Read, if anyone has a awnser to it I would appreciate it


I can't agree with that my B450 has no such prefetch disabled option AFAIK, number 28 on the leaders board with 3933 CL15 and that was not even my best bin kit with AddrCmdSetup 56 too. If I used boostoveride here +4900Mhz i would get into the high 50s.


----------



## MrHoof

The_King said:


> I can't agree with that my B450 has no such prefetch disabled option AFAIK, number 28 on the leaders board with 3933 CL15 and that was not even my best bin kit with AddrCmdSetup 56 too. If I used boostoveride here +4900Mhz i would get into the high 50s.
> 
> View attachment 2585675


Well what i mean was 3800mhz+ I guess what the avg CPU/Board can do, but most people that can pass it run above 4000.
edit: It was L2 preftcher not L1 my bad but both should exist.
This is what it can look like with it disabled vs enabled.


----------



## The_King

So to answer this question I decided to do a practical test with two sets of Crucial Ballistix 3600 CL16-18-18-38 one SR Kit and one DR kit both running XMP no other changes.
So for me this confirms that with *Micron RAM *increasing the RANKS will increase latency.

@MrHoof If you take a look at my L1/2/3 Latency you can see there is no such "cheating" going on here. Has I stated earlier there is no option to enable or disable
any prefetch anything on this board.

3600 CL16-18-18-38 DR 2X16GB









3800 CL16-18-18-38 SR 2X8GB









(Updated)
Further data that shows lower Latency with SR DIMMS with Micron RAM, with a similar setup with DR I get around 54.3ns









4133MT CL15 result = 3ns faster than DR kit.


----------



## Artylol

Veii said:


> Write here and somebody will see. Here and there happens that it's missed
> Outside of WHEA
> You throttle. Write has to be 31999 for 2000 FCLK instead of 31991
> View attachment 2585494
> 
> Proof me stability (1usmus_v3 config 25 loops), and Aida64 before and after
> If unstable, increase tRRD_S , tWTR_S, SCL's to 5 ; (tFAW to 4* tRRD_S)
> 
> You don't need to run such high cLDO_VDDP
> These are not dual rank, and you dont run 2400+ MLCK
> Drop it to 900mV. Maaybe 950 if you really need it ~ but i doubt
> Drop VDDG CCD to 980mV and IOD to 1040+
> SOC mostly needs between 1175-1225 ~ it can need more with lower procODT
> 
> If drop on cLDO_VDDP creates memory stability issues
> Change CAD_BUS settings slightly around . 40-20-30-24 or 40-20-40-20


Did your settings on Anta777_absolut 3 sets










And then my settings with 25 cycles of 1usmus_v3. Writes were in the range 31997-31998, but once actually reached 32001. Y-cruncher doing much worse at y-cruncher at 0.884 (not shown)











EDIT1:
I have increased VDDG CCD and write now are stable at 31999 even at my settings. In addition, I have rebooted my pc and now scoring 0.784 at y-cruncher. Seems like my pc dont like to idle for whole day.

EDIT2:
tPHYRDL is the same between both DIMMS


----------



## The_King

@Veii I have tPHYRDL mismatch 28/26. Any suggestion to help with this? Even when RDWR 10/11 it still the same


----------



## Taraquin

The_King said:


> @Veii I have tPHYRDL mismatch 28/26. Any suggestion to help with this? Even when RDWR 10 it still the same
> View attachment 2585798
> 
> View attachment 2585801
> View attachment 2585802


2t can sometimes fix it, but worsens performance nore than uneven PHYRDL :/


----------



## The_King

Taraquin said:


> 2t can sometimes fix it, but worsens performance nore than uneven PHYRDL :/


2T blasphemy! J/K 

Mismatch does not mean it wont pass TM5.

Its just that I am more conscious about it since @Veii said is means something is over powered or something to that effect cant reacall his exact words at the moment.

Running TM5 now if it passes 25 cycles I wont think too much of it.

@Taraquin Tried 2T now both DIMMS are 28/28 not sure if that is better or worse at least its the same. Memory Latency does take a hit @ 2T
Read and copy seems to be gone down as well.
















I don't like 2T going back to 1T


----------



## dimkatsv

The_King said:


> I have tPHYRDL mismatch 28/26. Any suggestion to help with this?


Try to play with ProcODT and ClkDrvStr parameters.


----------



## DOer_R

Hey guys! Can you help me with these issues? I get these errors now all the time and i dont know what causes them. I m quite sure i didn get them before. I m running latest windows and only program i use beside is hwinfo64. I also disabled CO but i still get these errors


----------



## MrHoof

The_King said:


> So to answer this question I decided to do a practical test with two sets of Crucial Ballistix 3600 CL16-18-18-38 one SR Kit and one DR kit both running XMP no other changes.
> So for me this confirms that with *Micron RAM *increasing the RANKS will increase latency.
> 
> @MrHoof If you take a look at my L1/2/3 Latency you can see there is no such "cheating" going on here. Has I stated earlier there is no option to enable or disable
> any prefetch anything on this board.
> 
> 3600 CL16-18-18-38 DR 2X16GB
> View attachment 2585788
> 
> 
> 3800 CL16-18-18-38 SR 2X8GB
> View attachment 2585789
> 
> 
> (Updated)
> Further data that shows lower Latency with SR DIMMS with Micron RAM, with a similar setup with DR I get around 54.3ns
> View attachment 2585793
> 
> 
> 4133MT CL15 result = 3ns faster than DR kit.
> View attachment 2585797


Sry If i sounded like you were cheating that was not my intention, I just wanted to point out that its possible.


----------



## Veii

DOer_R said:


> Hey guys! Can you help me with these issues? I get these errors now all the time and i dont know what causes them. I m quite sure i didn get them before. I m running latest windows and only program i use beside is hwinfo64. I also disabled CO but i still get these errors
> View attachment 2585831


Core crashing issues
Or cache/fabric hardcrashing CCDs


----------



## DooM3

does anyone know these rams, have you tried them


----------



## DOer_R

Veii said:


> Core crashing issues
> Or cache/fabric hardcrashing CCDs


Well i just started TM5 and i got error in like 5 seconds for core 27 eventhough i have SMT disabled. Sometimes i get like errors for 10 cores. 
There is no way that 10 cores are crashing because i tested quite alot with OCCT and system should be stable. Maybe i should test with another program.
Also i never got these errors before i updated to latest version of windows


----------



## Veii

DOer_R said:


> Well i just started TM5 and i got error in like 5 seconds for core 27 eventhough i have SMT disabled. Sometimes i get like errors for 10 cores.
> There is no way that 10 cores are crashing because i tested quite alot with OCCT and system should be stable. Maybe i should test with another program.
> Also i never got these errors before i updated to latest version of windows
> View attachment 2585869
> View attachment 2585866


I don't know what to tell you.
Fact is ~ core or cache+ring, crashes

Also 1.06v cLDO_VDDP (IMC voltage)
is for 2400Mhz MCLK (2:1), not for for 1800
1900MHz MCLK will need around 900mV , max 950mV cLDO_VDDP
For 1800MHz maybe even 820-840mV should work. Overvolted for +200mV

Also on Vermeer SOC-GET should be at bare minimum 43mV over highest VDDG voltage
On Dual CCDs this can be 62 to 68mV.
1060mV VDDG IOD + ~68mV = 1128mV SVI2.0
Now taken loadline, your 1137.5mV SOC can drop lower than 1128 and everything crashes by overvoltage yet undersuply.

I would just lower VDDGs , both sub 1v for this low MCLK & FCLK.
Or overvolt a bit more and run SOC 1175mV_SET. Soo you optimally stay always above 1150mV_GET


The_King said:


> Mismatch does not mean it wont pass TM5.
> 
> Its just that I am more conscious about it since @Veii said is means something is over powered or something to that effect cant reacall his exact words at the moment.
> 
> Running TM5 now if it passes 25 cycles I wont think too much of it.


You can ignore it, or go down in 200MT/s steps starting from 1800
And check when you hold 26-26.
It's the board adapting IOL/RTL , delay between traces.
A missmatch often is a board issue, but 1T will run 26's
The reason that it switches to 28-28's means something is either overvolted or underpowered.
VDDG, VDDP, CAD_BUS, RTTs & ProcODT are the factors for it.
// or you can force a change with CAS 14, tCWL 14 ~ yet 28 is not ok, 26-26 should be it

Soo jump down in MT/s and see where it changes up, to have an easier time rebalancing your preset.
For GDM shenanigans the user can not do much, but 2T or 1T both have to stay at 26
28 only is for much higher MCLK ~ up to 30, where post that it refuses to post on some boards
// Unresolved Firmware issue since 2 years & lack of access to the user, to fix it themselves


----------



## 67091

Anyhow, I think I'm stable on these timings.
I'm going to run TM5 again today and hope it doesn't time out. If it passes, I'll reduce voltage and then go for tighter timings.
I have ordered a EK monarch block which will be coming in the mail around Jan so I would like to squeeze a bit more performance out of the kit before the block arrives.

Just like to say once again, Thanks


----------



## Aby67

Hello

*Anyone here with an* ASUS ROG STRIX X670E-I GAMING WIFI AM5 MINI-ITX , can kindly tell me if the PCIe slot has bifurcation, so I can by using a PCIe riser cable slitter x16 to dual x8, drop a couple of GPu's?!
Maybe post a BIOS screenshot for this function?!
Thx


----------



## Akex

Behavior which I did not expect, here I need 1.67v to be stable in the first screenshot, and after reworking DrvStr, I need 1.64v on the second screen. It was the saved vDIMM because I'm stuck with a too high tFAW on 48, below 48 it's not stable no matter vDIMM. In short.


----------



## dimkatsv

Akex said:


> I'm stuck with a too high fFAW on 48


Aaand... how is performance? 
Speed is high, but FAW delay is atrocious, so i am intersted


----------



## Akex

dimkatsv said:


> Aaand... how is performance?
> Speed is high, but FAW delay is atrocious, so i am intersted












I'm currently working on reducing tRRD_ and tFAW.


----------



## Veii

Akex said:


> Behavior which I did not expect, here I need 1.67v to be stable in the first screenshot, and after reworking DrvStr, I need 1.64v on the second screen. It was the saved vDIMM because I'm stuck with a too high tFAW on 48, below 48 it's not stable no matter vDIMM. In short.
> 
> View attachment 2585968
> View attachment 2585969


Give this a try








tRAS 48 is what you're looking for


----------



## Akex

Veii said:


> Give this a try
> 
> 
> 
> 
> 
> 
> 
> 
> tRAS 48 is what you're looking for


Thank you, I finished the current test for validated 1.62v and I test your suggestions, I will bring you an answer at the end of the afternoon if all goes well  Why should I look for tRAS 48? Isn't it good tRCD x2?

I appreciate all your help, I would really like to have this stable preset with honorable performance for such a frequency, it's really a big challenge.

That said, I receive C9BLM revE in a few days, the IC is technically better than my current C9BKV. I hope to be able to do a little better or the same with perhaps fewer vDIMMs, we'll see when the time comes.


----------



## Taraquin

DooM3 said:


> does anyone know these rams, have you tried them
> 
> View attachment 2585859
> View attachment 2585860


Mediocre binned Hynix DJR. You run unsynced and get big latency penalty. IOD and VDDP is way too high. First I would run them at 3800 and fclk/uclk 1900 if that boots. Then try lowering timings. DJR usually handles at 3800:
1.45v
CL 16
RCD 20/20
RP 20
RAS 36
RC 56
RRDS/L 4/6
FAW 16
WTRS/L 4/10
WR 16
RFC 520 (450 may work, try lowering it by 10 and 10)
RDRDSCL/WRWRSCL 4
CWL 16
RTP 8
RDWR 9
WRRD 1

If 1900 fclk is unstable, run fclk/uclk 1867. 

Try SOC, IOD, CCD, VDDP auto first, if that works, try lower values like these:
SOC 1.1V
IOD 1.05V
CCD 0.95V
VDDP 0.9V


----------



## Artylol

Artylol said:


> Did your settings on Anta777_absolut 3 sets
> 
> View attachment 2585795
> 
> 
> And then my settings with 25 cycles of 1usmus_v3. Writes were in the range 31997-31998, but once actually reached 32001. Y-cruncher doing much worse at y-cruncher at 0.884 (not shown)
> 
> View attachment 2585796
> 
> 
> 
> EDIT1:
> I have increased VDDG CCD and write now are stable at 31999 even at my settings. In addition, I have rebooted my pc and now scoring 0.784 at y-cruncher. Seems like my pc dont like to idle for whole day.
> 
> EDIT2:
> tPHYRDL is the same between both DIMMS


@Veii

Seems stable at 1usmus 25 cycle test. Is there anything else to improve? 
My tPHYRDL is 28\28, but for some reason I can not boot every time, bios gets stuck at GPU debug light.


----------



## Akex

Veii said:


> Give this a try
> 
> 
> 
> 
> 
> 
> 
> 
> tRAS 48 is what you're looking for


Not possible tWTRL 24, I automatically switch to 14, this is the maximum in the bios.


----------



## Imprezzion

What would you guys recommend I run on a 5800X3D for daily gaming usage? I have 2 stable profiles for my RAM (2x16gb DR B-Dies). Both 1:1 FCLK MCLK UCLK without WHEA. 

1. 3800 14-16-14-28-42-256-1T GDM Off 1.56v with 0.86 VDDP, 0.96 CCD 0.98 IOD 1.068 vSOC GET.

2. 3933 16-16-16-36-52-272-1T GDM On 1.45v with 0.98 VDDP 1.07 CCD 1.12 IOD 1.240 vSOC GET. 

Profile 1 is nice and tight and fast but not the best frequency wise and it suffers from DIMM temperature issues. Even with active cooling they run 46-48c in gaming with the 3090's backplate pushing a lot of heat into them at 1.56v vDIMM. The board also does not like 1T GDM Off and sometimes has issues cold booting also hanging on VGA or DRAM LED and needs a reset to boot properly. 

Profile 2 is slower latency wise and uses GDM 1T since this setup cannot run 1T without GDM but it has significantly higher bandwidth and stays way cooler on the DIMMs due to only needing 1.45v and can handle way higher temps without becoming unstable but it needs a lot more vSOC and VDDG to stay WHEA clear at 1967. 

I have to do a BIOS update so I have to re do all the profiles anyway so I kinda wanna just pick one and run that. I'm thinking the 3933 profile would probably be better in the long run. Maybe I can try 2T GDM Off to run 15 tCL (and/or tRTP, tRCD) but in my testing 1T GDM On with tCL 16 was faster and required way less vDIMM.


----------



## Khicken

The_King said:


> IT's rated 4133 18-22-22-42 Highly unlikely to be Samsung B-die! Thats a hard NO from me.
> 
> 
> https://assets.website-files.com/5cdb2ee0b102f96c3906500f/5f4e5ef1d8ee7a75f16a18b1_PVB416G413C8K%20Sku%20Sheet_%20080320.pdf
> 
> 
> 
> 
> The best Patriot ram to get IMHO is the Patriot Viper Steel *4000 CL16* usually goes for around $99 when on Sale.


So does that mean the PVS416G400C6K is better than the PVS416G400C9K kit? If so what's the differences and why is it better, im a newbie and im not sure which kit i should get.


----------



## The_King

Khicken said:


> So does that mean the PVS416G400C6K is better than the PVS416G400C9K kit? If so what's the differences and why is it better, im a newbie and im not sure which kit i should get.


The PVS416G400C6K is 4000 CL-16-16-16-36 it is a better bin with a speed grade rating of 2666V


https://assets.website-files.com/5cdb2ee0b102f96c3906500f/6169bb2252fba3bdfda10c2b_PVS416G400C6K_Sku%20Sheet_100621.pdf



The PVS416G400C9K is 4000 CL19-19-19-39 is probably the next best kit to get if the above kit is not available.
Speed grade on these are 2133p-downbin so is not better than the above kit.


https://assets.website-files.com/5cdb2ee0b102f96c3906500f/5dd6b33a8bbffce4aac8c12f_PVS416G400C9K%20Sku%20Sheet_Copyable_062819.pdf



On Amazon.com I found the better kit is usually cheaper.
I would personally get the 4000 CL16-16-16-36 kit over the other one even if it cost slightly more at the present moment.





Imprezzion said:


> What would you guys recommend I run on a 5800X3D for daily gaming usage? I have 2 stable profiles for my RAM (2x16gb DR B-Dies). Both 1:1 FCLK MCLK UCLK without WHEA.
> 
> 1. 3800 14-16-14-28-42-256-1T GDM Off 1.56v with 0.86 VDDP, 0.96 CCD 0.98 IOD 1.068 vSOC GET.
> 
> 2. 3933 16-16-16-36-52-272-1T GDM On 1.45v with 0.98 VDDP 1.07 CCD 1.12 IOD 1.240 vSOC GET.
> 
> Profile 1 is nice and tight and fast but not the best frequency wise and it suffers from DIMM temperature issues. Even with active cooling they run 46-48c in gaming with the 3090's backplate pushing a lot of heat into them at 1.56v vDIMM. The board also does not like 1T GDM Off and sometimes has issues cold booting also hanging on VGA or DRAM LED and needs a reset to boot properly.
> 
> Profile 2 is slower latency wise and uses GDM 1T since this setup cannot run 1T without GDM but it has significantly higher bandwidth and stays way cooler on the DIMMs due to only needing 1.45v and can handle way higher temps without becoming unstable but it needs a lot more vSOC and VDDG to stay WHEA clear at 1967.
> 
> I have to do a BIOS update so I have to re do all the profiles anyway so I kinda wanna just pick one and run that. I'm thinking the 3933 profile would probably be better in the long run. Maybe I can try 2T GDM Off to run 15 tCL (and/or tRTP, tRCD) but in my testing 1T GDM On with tCL 16 was faster and required way less vDIMM.


I would use profile 2 but try to get 3933 CL15 stable. +/-1.5V or less
5800X3D does not need low latency from RAM to perform like other ZEN 3 CPUs.


----------



## Veii

Akex said:


> Not possible tWTRL 24, I automatically switch to 14, this is the maximum in the bios.


aww, right right
then 12 too , instead of 24


----------



## Giacomo Coppi

I've been able to stabilize the error i got in the previous post .
Ram voltage is still 1.500v 
I can boot with ram at 3933mhz and infinity fabric at 2000mhz but i still cannot boot ram at 4000mhz  
Any help to make me boot this ram at 4000 is really welcome , thx all


----------



## The_King

Giacomo Coppi said:


> I've been able to stabilize the error i got in the previous post .
> Ram voltage is still 1.500v
> I can boot with ram at 3933mhz and infinity fabric at 2000mhz but i still cannot boot ram at 4000mhz
> Any help to make me boot this ram at 4000 is really welcome , thx all
> 
> View attachment 2586017


Have you tried with higher VSOC 1.15V - 1.2V ?


----------



## Giacomo Coppi

The_King said:


> Have you tried with higher VSOC 1.15V - 1.2V ?


no i haven't , i actually have 2000IF at 1,09v and i thought it was unnecessary to raise its voltage , i will give it a try thanks


----------



## DOer_R

Veii said:


> I don't know what to tell you.
> Fact is ~ core or cache+ring, crashes
> 
> Also 1.06v cLDO_VDDP (IMC voltage)
> is for 2400Mhz MCLK (2:1), not for for 1800
> 1900MHz MCLK will need around 900mV , max 950mV cLDO_VDDP
> For 1800MHz maybe even 820-840mV should work. Overvolted for +200mV
> 
> Also on Vermeer SOC-GET should be at bare minimum 43mV over highest VDDG voltage
> On Dual CCDs this can be 62 to 68mV.
> 1060mV VDDG IOD + ~68mV = 1128mV SVI2.0
> Now taken loadline, your 1137.5mV SOC can drop lower than 1128 and everything crashes by overvoltage yet undersuply.
> 
> I would just lower VDDGs , both sub 1v for this low MCLK & FCLK.
> Or overvolt a bit more and run SOC 1175mV_SET. Soo you optimally stay always above 1150mV_GET


I finally found what was wrong. For some reason my virtual memory was disabled.As soon as i set paging file size to system managed i dont get any thread errors anymore.I also passed 2x 50cycles of usmus.cfg and i also lowered those voltages so i hope it s ok now. 
Although to be honest my IMC sucks.. It s near impossible to get anything working stable above 3600mt with 4 dimms


----------



## The_King

MrHoof said:


> Here some samsung scores from my daily setups 5800x and now 3d.
> View attachment 2584825


Made it into the 93s with one of my Samsung B-die Kits. Does this benchmark benefit from Dual rank setups?

















Gambit`s y-cruncher - Pi-2.5b score: 1min 33sec 936ms with a Ryzen 7 5800X


The Ryzen 7 5800X @ 4450MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. Gambitranks #null worldwide and #null in the hardware class. Find out more at HWBOT.




hwbot.org


----------



## Mozart23

Hello guys.
I want to thank all of you for this thread. I've been following it almost from the start, but was not here for the last couple of months.
I want to ask if anybody has any clue to why my memory latency went "uphill" in the last 2 months or so.
Here are 2 screenshots. The left is from the start of October. On the right is the test I did today.
You can see my memory latency is 2.5ns higher. During those 2 months I just installed Windows updates and newest chipset drivers from AMD, nothing more. I have pretty clean system overall. During those tests only apps running in bg worth mentioning are MSI Afterburner and iCUE. They are certainly not the reason for this hike (they were running during both of those tests). I'm kinda lost. I was happy with around 56ns latency, but 58ns feels a bit too much.
I tried to update Aida64 to the newest version, which you can see on the right (the result was the same on the older version)















My system is
Win 11 22H2
RTX 2080 Ti
Ryzen 5950x
RAM GSkill Trident Z Neo 32GB (1.36V)
timings:








I suspect Windows updates are the cause, but is it even possible, that it could raise the latency so much?
I will really appreciate your help.


----------



## ManniX-ITA

Mozart23 said:


> I suspect Windows updates are the cause, but is it even possible, that it could raise the latency so much?


Very unlikely the Windows Updates. 

iCUE is usually the culprit.
Maybe that earlier version was somehow not causing issues or got an ever worse than usual update.
I've removed it from my niece's system and replaced it with Argus Monitor.
Try disabling it.

If it's not iCUE, could be that you installed maybe some RGB software control? Like for the DIMMs or else?
That's a common cause for 1-2ns latency increase.


----------



## 99belle99

I see numberworld.org has that ycruncher app. Is that site safe to download from?


----------



## ManniX-ITA

99belle99 said:


> I see numberworld.org has that ycruncher app. Is that site safe to download from?


Yes it's the official site


----------



## Mozart23

ManniX-ITA said:


> Very unlikely the Windows Updates.
> 
> iCUE is usually the culprit.
> Maybe that earlier version was somehow not causing issues or got an ever worse than usual update.
> I've removed it from my niece's system and replaced it with Argus Monitor.
> Try disabling it.
> 
> If it's not iCUE, could be that you installed maybe some RGB software control? Like for the DIMMs or else?
> That's a common cause for 1-2ns latency increase.


Thank you very much for the reply.
iCUE should not be the cause, because it was the same version in both tests.
But I maybe found the culprit, but still the results are not as good as it was.
The thing is in October I used edited powerplan. For todays test I was on Balanced powerplan. I really fogot about that. After I switched back to that edited powerplan, it is around 57ns. Which is better than before, but still not around that 56ns mark.


----------



## ManniX-ITA

Mozart23 said:


> The thing is in October I used edited powerplan. For todays test I was on Balanced powerplan. I really fogot about that. After I switched back to that edited powerplan, it is around 57ns. Which is better than before, but still not around that 56ns mark.


Ah, forgot about the power plan 
You can give a try with the Ultimate power plan in my signature.


----------



## DooM3

Taraquin said:


> Mediocre binned Hynix DJR. You run unsynced and get big latency penalty. IOD and VDDP is way too high. First I would run them at 3800 and fclk/uclk 1900 if that boots. Then try lowering timings. DJR usually handles at 3800:
> 1.45v
> CL 16
> RCD 20/20
> RP 20
> RAS 36
> RC 56
> RRDS/L 4/6
> FAW 16
> WTRS/L 4/10
> WR 16
> RFC 520 (450 may work, try lowering it by 10 and 10)
> RDRDSCL/WRWRSCL 4
> CWL 16
> RTP 8
> RDWR 9
> WRRD 1
> 
> If 1900 fclk is unstable, run fclk/uclk 1867.
> 
> Try SOC, IOD, CCD, VDDP auto first, if that works, try lower values like these:
> SOC 1.1V
> IOD 1.05V
> CCD 0.95V
> VDDP 0.9V





This thread is dedicated to showing the various memory configurations of users with DDR4 on AMD Ryzen platforms.
There is no strict criteria here, all things AM4 memory overclocking welcome. However, to enter the stability chart certain criteria is to be met as this is generally speaking dedicated to showing what is obtainable on both platforms at an operational level.


----------



## Akex

The_King said:


> Made it into the 93s with one of my Samsung B-die Kits. Does this benchmark benefit from Dual rank setups?
> View attachment 2586024
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Gambit`s y-cruncher - Pi-2.5b score: 1min 33sec 936ms with a Ryzen 7 5800X
> 
> 
> The Ryzen 7 5800X @ 4450MHzscores getScoreFormatted in the y-cruncher - Pi-2.5b benchmark. Gambitranks #null worldwide and #null in the hardware class. Find out more at HWBOT.
> 
> 
> 
> 
> hwbot.org


Hum, i have 4x8 Akex`s y-cruncher - Pi-2.5b score: 1min 33sec 450ms with a Ryzen 7 5800X


----------



## The_King

Akex said:


> Hum, i have 4x8 Akex`s y-cruncher - Pi-2.5b score: 1min 33sec 450ms with a Ryzen 7 5800X


Would you mind if I ask you to rerun that with 4450 all core instead of 4650?
I want see how that will compare with mines running the same locked CPU frequency but with SR RAM setup.

That should give us some indication if y-cruncher benefits from DR or not. 
It does indeed benefit from higher CPU clocks and I can't run that high 4650 all core with my CPU Air cooler. (Thermal issues)


----------



## 99belle99

Akex said:


> Hum, i have 4x8 Akex`s y-cruncher - Pi-2.5b score: 1min 33sec 450ms with a Ryzen 7 5800X


I'm new to ycruncher but I beat you score with a 3700X in Pi2.5b.


----------



## The_King

99belle99 said:


> I'm new to ycruncher but I beat you score with a 3700X in Pi2.5b.


You should try to do your benchmarks with Benchmate. Also consider joining HWBOT. Its lots of fun IMHO.





BenchMate







benchmate.org


----------



## Akex

The_King said:


> Would you mind if I ask you to rerun that with 4450 all core instead of 4650?
> I want see how that will compare with mines running the same locked CPU frequency but with SR RAM setup.
> 
> That should give us some indication if y-cruncher benefits from DR or not.
> It does indeed benefit from higher CPU clocks and I can't run that high 4650 all core with my CPU Air cooler. (Thermal issues)


I'll do it for you this weekend if it suits you, so I'll take the opportunity to pass in front of the gentleman with his 3700X



99belle99 said:


> I'm new to ycruncher but I beat you score with a 3700X in Pi2.5b.


Boff, it's not windy bench on the 5800X, just to score a minimum for the TeamCUP 2022. Don't worry, if I want to explode your score in a few minutes, you will never be able to compete with my preset 4933C16 😇


----------



## MrHoof

The_King said:


> Would you mind if I ask you to rerun that with 4450 all core instead of 4650?
> I want see how that will compare with mines running the same locked CPU frequency but with SR RAM setup.
> 
> That should give us some indication if y-cruncher benefits from DR or not.
> It does indeed benefit from higher CPU clocks and I can't run that high 4650 all core with my CPU Air cooler. (Thermal issues)


Thats probably it my runs were done with custom CO -14 lowest negative offset on the best, -12 2nd best and -18 on core 8, rest at -30 or -28.
No boostclock override, never been able to hit over 4.85 on air anyway and it would result in lower overall clocks just going +25.
Effektive clocks on those runs were 4700mhz all core. You can see the diffrence on my 5800x3d score its about 1 second slower running at 4450mhz same timings beside twtrl 10 instead of 8.


----------



## ReyReverse

Mozart23 said:


> Hello guys.
> I want to thank all of you for this thread. I've been following it almost from the start, but was not here for the last couple of months.
> I want to ask if anybody has any clue to why my memory latency went "uphill" in the last 2 months or so.
> Here are 2 screenshots. The left is from the start of October. On the right is the test I did today.
> You can see my memory latency is 2.5ns higher. During those 2 months I just installed Windows updates and newest chipset drivers from AMD, nothing more. I have pretty clean system overall. During those tests only apps running in bg worth mentioning are MSI Afterburner and iCUE. They are certainly not the reason for this hike (they were running during both of those tests). I'm kinda lost. I was happy with around 56ns latency, but 58ns feels a bit too much.
> I tried to update Aida64 to the newest version, which you can see on the right (the result was the same on the older version)
> View attachment 2586030
> View attachment 2586031
> 
> My system is
> Win 11 22H2
> RTX 2080 Ti
> Ryzen 5950x
> RAM GSkill Trident Z Neo 32GB (1.36V)
> timings:
> View attachment 2586032
> 
> I suspect Windows updates are the cause, but is it even possible, that it could raise the latency so much?
> I will really appreciate your help.


My 5950x recently I reinstalled windows to 22H2 with 3733 my latency stable at 55.4ns , and my Kits love trtp5 twr10 trc 250 (134ns) 1.5v
Maybe you can try this settings.


----------



## Luggage

99belle99 said:


> I'm new to ycruncher but I beat you score with a 3700X in Pi2.5b.


You did what?







y-cruncher - Pi-2.5b overclocking records @ HWBOT


Overclocking records




hwbot.org










y-cruncher - Pi-2.5b overclocking records @ HWBOT


Overclocking records




hwbot.org


----------



## Mozart23

ReyReverse said:


> My 5950x recently I reinstalled windows to 22H2 with 3733 my latency stable at 55.4ns , and my Kits love trtp5 twr10 trc 250 (134ns) 1.5v
> Maybe you can try this settings.


Thank you for the tip, I will try that in the future. 
Anyway I actually practically solved my issue thanks to the *ManniX-ITA*.


----------



## ManniX-ITA

Thanks to @Mozart23 for reporting his issue!

*TL;DR

Windows 11 power management is bugged.*
Don't use any power plan except the Ultimate or you'll get higher and spotty latency and lower boost clock!
I have updated my plans with a Performance and LowPower versions based on the Ultimate.

They seems to work great, highly recommended the LowPower; same benchmark results and latency/clocks as Ultimate but lower power consumption.

I've managed finally to get 5125 MHz boost clock and 54.7ns in AIDA.
Before I was limited to 5075 MHz and 55.1ns.

Sure it's Win11 so AIDA it's still spotty and inconsistent but it's a whole different level.
Results are pretty consistent and are almost never going over 55.1ns.
All the other plans are causing the latency to fluctuate massively with some bad results up to 61-66ns and an average of 56-57ns.
Average of boost clock is also improved by 50-75 MHz.

Benchmark scores and system responsiveness are excellent.

You can download them from my signature.
Let me know if you have issues.


----------



## 99belle99

Luggage said:


> You did what?
> 
> 
> 
> 
> 
> 
> 
> y-cruncher - Pi-2.5b overclocking records @ HWBOT
> 
> 
> Overclocking records
> 
> 
> 
> 
> hwbot.org
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> y-cruncher - Pi-2.5b overclocking records @ HWBOT
> 
> 
> Overclocking records
> 
> 
> 
> 
> hwbot.org


I'm just going by what the time says. I must have done something wrong so as I said I'm new to this benchmark. I done the 2.5b test.

I have a notepad score but do not know how to make it display without just posting a Notepad image that I could have easily changed.

Anyone who knows that app want to chime in and show me how to display a score properly without running it again.


----------



## ManniX-ITA

99belle99 said:


> Anyone who knows that app want to chime in and show me how to display a score properly without running it again.








BenchMate







benchmate.org





Register on HWBot, join the OCN team optionally, run the benchmarks with Benchmate and submit.
You need to usually open CPU-z before taking the screenshot with Benchmate (CPU, Mainboard, Memory).
I usually also open Zentimings.


----------



## 99belle99

ManniX-ITA said:


> BenchMate
> 
> 
> 
> 
> 
> 
> 
> benchmate.org
> 
> 
> 
> 
> 
> Register on HWBot, join the OCN team optionally, run the benchmarks with Benchmate and submit.
> You need to usually open CPU-z before taking the screenshot with Benchmate (CPU, Mainboard, Memory).
> I usually also open Zentimings.


I seen benchmate earlier but didn't want to use as I have the stand alone Y-cruncher. I'm not really interested in putting my scores up on hwbot so I will just leave it.


----------



## ManniX-ITA

99belle99 said:


> I seen benchmate earlier but didn't want to use as I have the stand alone Y-cruncher. I'm not really interested in putting my scores up on hwbot so I will just leave it.


That's a pity 
Every score is useful for the team 

Even if you don't want to upload the scores to HWBot it's super useful to run the benchmarks, save the scores and the screenshots in a few clicks and with the proper setup.
Much better than doing it manually and it's not invasive or installing unwanted software.


----------



## Akex

99belle99 said:


> I seen benchmate earlier but didn't want to use as I have the stand alone Y-cruncher. I'm not really interested in putting my scores up on hwbot so I will just leave it.


Motivate yourself, I don't want to fight with a ghost, hwbot is good, time-consuming at times but good. I can encourage you to come and register and take up the challenges.


----------



## dimkatsv

Mozart23 said:


> I was happy with around 56ns latency, but 58ns feels a bit too much.


Check if you got tSME enabled in BIOS? It gives latency a hit.


----------



## 99belle99

Akex said:


> Motivate yourself, I don't want to fight with a ghost, hwbot is good, time-consuming at times but good. I can encourage you to come and register and take up the challenges.


I didn't beat your score. I got the below score which I thought was the score but I uploaded it to hwbot and it was much slower there for some reason. As I said I'm new to this so didn't know that happens.


----------



## 99belle99

I'm a dumbass I thought it was 1 minute 15 seconds but it's actual seconds. It's still an ok score as it's a stock 3700X.


----------



## 99belle99

You can see me in this link. y-cruncher - Pi-2.5b overclocking records @ HWBOT


----------



## 99belle99

That y-cruncher sure does hammer the CPU as I tried an all core overclocking run many times and it either caused an error or it crashed and had to keep dialling it back. I can run Timespy with a much higher all core overclock than this benchmark.


----------



## Mr.Sunshine

I've started to tweak timings and I'm getting an error after about 22-23hrs of testing. Any ideas on what to change?


----------



## The_King

99belle99 said:


> That y-cruncher sure does hammer the CPU as I tried an all core overclocking run many times and it either caused an error or it crashed and had to keep dialling it back. I can run Timespy with a much higher all core overclock than this benchmark.


Yes it sure is. People run R23 with CPU OC and think hey my CPU is great running -30 all core "stable"... until they run Y-cruncher which brings their CPU to its knees.
It is also much harder on IMC compared to R23. If you have an unstable memory OC you would usually find out much faster in Y-cruncher than running TM5 for hours,

I see you made it to number 4, so yes not bad at all compared to other 3700X scores 

Y-rcruncher uses AVX2 instructions which is much harder to run at higher clocks. Almost all CPUs will run this instruction at lower clocks speeds.


----------



## Mozart23

dimkatsv said:


> Check if you got tSME enabled in BIOS? It gives latency a hit.


Will do. Thank you for the tip.


----------



## The_King

Mr.Sunshine said:


> I've started to tweak timings and I'm getting an error after about 22-23hrs of testing. Any ideas on what to change?
> View attachment 2586132


Many here will run TM5 with 1usmus_V3 preset so that one can troubleshoot using the error codes.








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com





Try to upgrade to latest version of Zentimings as well. I would start with running both your SCL at 4 instead of 2.


----------



## Mikel_Ertz

Got this settings stable. The problem was tRCDWR to low. I have tryed tRTP 6 and tWR 12 with 1.45 and got errors. Also tryed tRP 14 and tRCDWR 14 with 1.42 and got error. Any advice to get working that tRP and tRCDWR? Also tryed 3800mhz, but getting WHEA 19 errors, any advice to get that 3800 working?


----------



## The_King

Ran OCCT AVX2 Large Extreme Variable for 1 hour. This stresses the CPU quiet hard. 1.416V Vcore and VRM peaked at 76C. (Highest I ever seen my VRM go, its usually around 60C with other tests)












Mikel_Ertz said:


> Also tryed 3800mhz, but getting WHEA 19 errors, any advice to get that 3800 working?


This post may help. This is how I got WHEA free with my setup.








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Most 5800X3Ds can do -30 on all cores because they don't run high clock frequencies like 5800X for example. In most cases I have seen almost all 5800X3D can run very stable with -30 all core but its always best to test CO for stability. You can check your scores in R23 with different CO...




www.overclock.net


----------



## dimkatsv

The_King said:


> hey my CPU is great running -30 all core "stable"... until they run Y-cruncher which brings their CPU to its knees.


Until i run CoreCycler on SSE Prime95. . . Y-cruncher runs fine for me even with CO-30 all core. Technically it can crash few hours later, but it is fine for benches. CoreCycler Prime would crash in less then 5 minutes instead. 
I have stranger sample, i guess... As AVX for me is more stable then SSE instructions


----------



## The_King

dimkatsv said:


> Until i run CoreCycler on SSE Prime95. . . Y-cruncher runs fine for me even with CO-30 all core. Technically it can crash few hours later, but it is fine for benches. CoreCycler Prime would crash in less then 5 minutes instead.
> I have stranger sample, i guess... As AVX for me is more stable then SSE instructions


I think the OCCT test I ran above uses P95. It has SSE, AVX and AVX2 instructions tests.


----------



## dimkatsv

The_King said:


> I think the OCCT test I ran above using P95. Not sure though its shows AVX2 not SSE..


Child's play and not load from my experience... It is just that you have suspiciously high voltage for such test. But yes, it is basically analog for Prime95. I mean impressive for this DRAM data rate, though. But i had seen more dangerous numbers. Y-cruncher can take my CPU to 85+ degrees as well as PPT to 125W (if i remove limit even more) approximately. Temporarily though. And highest power consumption load doesn't always equal to highest temps btw.










--------------------------------------------------

And here is how hard Y-cruncher hits





















The_King said:


> I think the OCCT test I ran above uses P95. It has SSE, AVX and AVX2 instructions tests.


Prime 95 runs AVX2 by default. You can also use AVX512, AVX and SSE instructions instead

P.S. Heaviest modes in Y-Cruncher are BBP, N64, HNT, VST, C17...
BKT, and SFT are only for frequency stability test.
FFT is good for rough memory stability test.
N32 is more sensitive to memory though.
Currently there is some bug with Y-Cruncher and Ryzen 7000 though. AVX2 tests are hard to pass there.


----------



## The_King

dimkatsv said:


> Prime 95 runs AVX2 by default. You can also use AVX512, AVX and SSE instructions instead


No AVX512 support on ZEN 3 CPUs. If you have a CPU that supports that instruction set, then that is also a good test to run.

I am running an 8 core CPU you running a 6 core so Voltages can differ between the two.


----------



## dimkatsv

The_King said:


> No AVX512 support on ZEN 3 CPUs


Yes. but Zen 4 exists)
And CoreCycler included test configs with AVX512 support for Zen4 specifically.


----------



## The_King

dimkatsv said:


> Yes. but Zen 4 exists)
> And CoreCycler included test configs with AVX512 support for Zen4 specifically.


Currently the 7600X is priced lower than what I paid for my 5800X a few months ago, but still have to factor in Mobo and DDR5 costs. 
I'm still quiet happy with 5800X performance so wont be looking to upgrade for at least another year maybe more.


----------



## dimkatsv

The_King said:


> I am running an 8 core CPU you running a 6 core so Voltages can differ between the two.


Voltage is proportionate to frequency though. And i have mine with +200 limit, which enchanced curve. 
To get to the PPT limit with given voltage, CPU uses EDC and TDC. (Usually EDC).
There is NO WAY CPU should use 1.4+ volts on multicore load. Especially for AVX load.


----------



## The_King

dimkatsv said:


> Voltage is proportionate to frequency though. And i have mine with +200 limit, which enchanced curve.
> To get to the PPT limit with given voltage, CPU uses EDC and TDC. (Usually EDC).
> There is NO WAY CPU should use 1.4+ volts on multicore load. Especially for AVX load.


Not sure about the voltages being too high it is AVX2 instruction set, running a second test now with FCLK 1933.
System seems stable with these voltages also my Air-cooler is keeping under 90C. I'm not using any LLC everything and PBO is set to Auto in the BIOS aside from the RAM OC.
I am mainly testing for WHEA and core failures.


----------



## dimkatsv

Also... Now that's Prime95 i know...85 degrees easily. Seems like with last update they made it even heavier on temps.










Also wow... I tried to set fix multiple drive swap and it didn't work out it seems. . . I couldn't run all threads Large FFT (Holy ****, 40 GB of memory isn't enough for this thing). Will troubleshoot it



The_King said:


> I am mainly testing for WHEA and core failures.


You should look for core failures on per-core basis, as frequencies will be higher.


----------



## gvansly1

Mozart23 said:


> Hello guys.
> I want to thank all of you for this thread. I've been following it almost from the start, but was not here for the last couple of months.
> I want to ask if anybody has any clue to why my memory latency went "uphill" in the last 2 months or so.
> Here are 2 screenshots. The left is from the start of October. On the right is the test I did today.
> You can see my memory latency is 2.5ns higher. During those 2 months I just installed Windows updates and newest chipset drivers from AMD, nothing more. I have pretty clean system overall. During those tests only apps running in bg worth mentioning are MSI Afterburner and iCUE. They are certainly not the reason for this hike (they were running during both of those tests). I'm kinda lost. I was happy with around 56ns latency, but 58ns feels a bit too much.
> I tried to update Aida64 to the newest version, which you can see on the right (the result was the same on the older version)
> View attachment 2586030
> View attachment 2586031
> 
> My system is
> Win 11 22H2
> RTX 2080 Ti
> Ryzen 5950x
> RAM GSkill Trident Z Neo 32GB (1.36V)
> timings:
> View attachment 2586032
> 
> I suspect Windows updates are the cause, but is it even possible, that it could raise the latency so much?
> I will really appreciate your help.


@Mozart23 I have the same kit, same cpu, and with similar timings I am also stable but get WHEA 19 errors when restarting or waking up from sleep mode, but none during stress testing. Are you WHEA free?


----------



## Mozart23

gvansly1 said:


> @Mozart23 I have the same kit, same cpu, and with similar timings I am also stable but get WHEA 19 errors when restarting or waking up from sleep mode, but none during stress testing. Are you WHEA free?


Yes. WHEA free for over a year. Maybe some bios setting is causing it for you?


----------



## ManniX-ITA

I have updated the Ultimate power plans to V2, there was a mistake on V1 causing low FPS in gaming.
Please update with the new versions!


----------



## Imprezzion

ManniX-ITA said:


> I have updated the Ultimate power plans to V2, there was a mistake on V1 causing low FPS in gaming.
> Please update with the new versions!


Is it (still) normal for a 5800X3D to have around 23-27w idle power consumption? I really wish it could be lower but neither windows stock profiles nor yours really go any lower. 

I'm fresh installing W11 22H2 on a new M.2 sometime this week and keeping the old bloated Insider Build updated to 22H2 install on the other M.2 so I can swap between them and compare some benchmarks and power consumption numbers both with and without your profiles.


----------



## ManniX-ITA

Imprezzion said:


> Is it (still) normal for a 5800X3D to have around 23-27w idle power consumption?


I think so unfortunately.
To go lower you would need to set FCLK at 1600 MHz or lower and hope the board is enabling the FCLK dynamic clock.
That is a major power saving feature but it's blocked by AMD cause it's unstable going higher.

Very soon I will have a new CPUDoc version with a new power plan.
With PSA you should get quite a bit lower idle power consumption.

But if you want to check for real buy an AC meter; the CPU package power very often doesn't reflect the actual power consumption for the system.
Especially with CPUDoc where some power savings settings are not CPU related and decrease the system consumption in idle but can't be seen monitoring the CPU.



Imprezzion said:


> I'm fresh installing W11 22H2 on a new M.2 sometime this week and keeping the old bloated Insider Build updated to 22H2 install on the other M.2 so I can swap between them and compare some benchmarks and power consumption numbers both with and without your profiles.


Windows 11 is a mess in my opinion but about power consumption in idle is quite a champion against Windows 10.
Absolutely excellent.

Unfortunately it does have also an excellent set of tricks to run "ghost" load without user knowledge which I find absolutely irritating and deceptive.

I didn't completely debloat my Win11 install, to keep it more similar to a normal install, and it does run continuously "something" on the best cores.
There's no reference of it anywhere but it's causing a constant load that triggers 500-1500 MHz of effective clock on them.
Measuring the max boost clocks with BoostTester it's almost impossible... it's like a bloated install.
And I still have, as the very first early release, a massive clock stretching on my 5950X while I have none in Windows 10.

But the worst is that despite attempting to disable background Apps they still go in background and despite trying to stop Defender or anything else to run in idle it still does it...
Which means that usually running BoostTester I have to keep moving the mouse every 5-10 seconds to stop it running something, it's extremely annoying.
And it's very often clearly a Defender background scan because my AC power consumption is flooring 200W pretty stable until I move the mouse again.

Worse than worst, Task Manager is hiding the load... You can catch it with HWInfo but Task Manger will hide it.
There's no option like in Windows 10 to show the load from system processes and I couldn't find a way to enable it.
It has been quite a pain to test it, I'll have to spend some more time to debloat more deeply.


----------



## The_King

ManniX-ITA said:


> I have updated the Ultimate power plans to V2, there was a mistake on V1 causing low FPS in gaming.
> Please update with the new versions!


Does this apply to both W11 and W10 as well?


----------



## ManniX-ITA

The_King said:


> Does this apply to both W11 and W10 as well?


Ah sorry I didn't specify, it's only relevant to Win11 (because I copied the heterogeneous settings from Win10).
I think it's related to the brand new KB patch from yesterday improving gaming.
I did not see this behavior before on Win11.


----------



## dimkatsv

dimkatsv said:


> I couldn't run all threads Large FFT (Holy ****, 40 GB of memory isn't enough for this thing). Will troubleshoot it


I was wrong. . . Issue wasn't that it was not enough memory.
Issue was that it was enough size of page file on drive C:\\
For some f**ing reason, i am completely unable to move my page file from drive C, to ANY other drive. Even if Windows creates it on reboot, it instantly forgets there is any page file in existence except one on C drive... F**K MICROSOFT AGAIN, ***

UPD: Found reason. And again F**CK MICROSOFT!
Issue was that my drives were named A:\\ and B:\\... And Windows these specific 2 letters differently just because of some legacy bullsh** with floppy drives.
Affixed another letter to drives and everything works now.


----------



## Imprezzion

dimkatsv said:


> I was wrong. . . Issue wasn't that it was not enough memory.
> Issue was that it was enough size of page file on drive C:\\
> For some f*_ing reason, i am completely unable to move my page file from drive C, to ANY other drive. Even if Windows creates it on reboot, it instantly forgets there is any page file in existence except one on C drive... F*K MICROSOFT AGAIN, *_
> 
> UPD: Found reason. And again F**CK MICROSOFT!
> Issue was that my drives were named A:\\ and B:\\... And Windows these specific 2 letters differently just because of some legacy bullsh** with floppy drives.
> Affixed another letter to drives and everything works now.


Still legacy floppy drive letter stuff in current windows? Wow.. Well, good to know. Then I'll just use D and E again on my fresh install even tho I also prefer to just start at A for the game storage m.2 drive, B for the raid-0 sata SSD storage and C for windows..


----------



## MrHoof

Didnt know people actuly care what letter the drive had. There is a reason why windows does not automaticly uses A: B: and you found it .


----------



## dimkatsv

MrHoof said:


> Didnt know people actuly care what letter the drive had. There is a reason why windows does not automaticly uses A: B: and you found it .


Windows can use whatever it wants. I don't have 25 drives to test if it will ever use A and B, and try to know why afterwards?\
So i first encountered why it doesn't, and then found out why. 
Why there is no popup telling you "Hey, letters A and B are reserved for legacy drive support including floppy disks, system may work incorrectly if you assign these letters to modern drives"


----------



## mnathani98

Need a bit of help with this, sorry for bad image. VDIMM at 1.55v and CPU at stock settings, IOD was set to 1.15v in bios and vsoc at 1.2375v


----------



## Netblock

The_King said:


> @Veii I have tPHYRDL mismatch 28/26. Any suggestion to help with this? Even when RDWR 10/11 it still the same
> View attachment 2585798
> 
> View attachment 2585801
> View attachment 2585802


28/26 in my experience tends to be instability related (which makes sense because MaxRdLatency is trained with a write-read access).
Try to get GDM off using the AddrCmd method over the ClkDrvStr. I suggest to do 20-30-24-24 and 59-0-0 and go from there.
(As a reminder, the Setups are encoded; they are also sacrificial. 63->32 helps tSetup by hurting tHold; and 1->31 helps tHold by hurting tSetup. Most systems I've seen like a AddrCmdSetup tSetup bias; though tHold systems can exist and they might like hi-impedance ClkDrvStr.)


Also RTT_Nominal does not do anything for you as you're single-rank. Nom only gets used when the ODT pin gets asserted high, which only happens on the first rank of the non-accessed DIMM (it could technically happen on the idle ranks on the same DIMM, but I have not seen any documentation or papers that suggest it). (also there is a very tiny power/temperature benefit with RTT_Nom set to disabled.)

That said, you might have some luck playing with Write and Park on single-rank, regarding potential instability between idle and writes. Try disabled-3-1?


----------



## The_King

mnathani98 said:


> Need a bit of help with this, sorry for bad image. VDIMM at 1.55v and CPU at stock settings, IOD was set to 1.15v in bios and vsoc at 1.2375v
> View attachment 2586398


I would change WTRS to 4. 

for RCDRD 16 VDIMM seems on the high side 1.5V or lower may work better.


----------



## ManniX-ITA

dimkatsv said:


> Why there is no popup telling you "Hey, letters A and B are reserved for legacy drive support including floppy disks, system may work incorrectly if you assign these letters to modern drives"


I wish they would at least test their fantastic patches on modern CPUs, like the Ryzen 5000 

Not sure if it's my system falling apart or not.
But the latest KB5020044 for Windows 11 was a real disaster, at least for me.
I'm so glad I'm still on Windows 10.

All the benchmarks I did run yesterday evening where slower than those I did run in the morning.
I've re-run the benchmarks for the day before, when the patch was installed half-way.
They are all much lower; CPU-z -5/10pts in ST, -80/100pts in MT, GB5 -30pts in ST, -200pts in MT
The Ultimate power plan is always much better than the others but all the AIDA64 good results are gone forever and ever.

The only bright side is that they messed up so much this time that the heterogeneous policy behavior changed.
Now with the Ryzen 5000 the policy 0 works much better than the default 4. Before this patch it was the same.
And you can use the better settings for the scheduling, Preferred Performant/Preferred Efficient, without issues in gaming.

Not only that, the gaming performances with policy 0 are much greater. 
+17 fps in FPS average in SotTR is quite something.
And in general works much better.
With the policy 0 still AIDA can't get back to the good results as before.
But it's the first time I see it being so stable and consistent in runs.

With just the KB installed, gaming is just as before and almost everything is slower. Very nice patch...

I've uploaded the V3 plans, highly recommended to update.


----------



## 67091

Hi guys
Is the any reason not to run TM5 in safe mode , apart from not been able to use HWINFO?


----------



## The_King

angushades said:


> Hi guys
> Is the any reason not to run TM5 in safe mode , apart from not been able to use HWINFO?











[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


In my case, it's the difference between memory at 40C and memory at 70C, but this is a SFF box. You may or may not need to go to the same extremes I would, but I highly recommend testing at your personal worst case temps, or you may be in for an unpleasant surprise at some point. Micron E-die...




www.overclock.net













[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Run to run variance should be under 0.3ns Except the first run, which needs load before it settles down Anything over this deviance is auto correcting or another issue. Actually more like 0.2ns




www.overclock.net





Personally I don't do any testing in safe mode and I would also not recommend it.


----------



## 67091

The_King said:


> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> In my case, it's the difference between memory at 40C and memory at 70C, but this is a SFF box. You may or may not need to go to the same extremes I would, but I highly recommend testing at your personal worst case temps, or you may be in for an unpleasant surprise at some point. Micron E-die...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Run to run variance should be under 0.3ns Except the first run, which needs load before it settles down Anything over this deviance is auto correcting or another issue. Actually more like 0.2ns
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> Personally I don't do any testing in safe mode and I would also not recommend it.


ok but I’m not benching. The reason why I ask is because sometimes TM5 will just stop testing and that would be around like cycle 15 out 20 on Asolute. It’s like 10hours in and it does that. I even tested this app on my z370 with a 9700k ,bdie memory that is on the QVL list and it did the samething and….at other times it passes the whole 20 cycles.
Don’t get my wrong I own both memtest86 and kahur but only this software I believe it’s the hardest on memory but damn it’s buggy as hell.


----------



## ManniX-ITA

angushades said:


> ok but I’m not benching. The reason why I ask is because sometimes TM5 will just stop testing and that would be around like cycle 15 out 20 on Asolute. It’s like 10hours in and it does that. I even tested this app on my z370 with a 9700k ,bdie memory that is on the QVL list and it did the samething and….at other times it passes the whole 20 cycles.


It's not about benching.
TM5 ran in safe mode will not be able to stress the memory as much as in normal mode.
There's a slight difference which could be enough to pass in safe but fail in normal usage.

If it's dying after so much time it's usually because something else running in background is slowly churning the memory allocated by TM5.
Can be also a driver or a service, it's not always easy to troubleshoot.
Easier way to fix it is to open something that allocates a relatively big chunk of physical memory; eg a Chrome browser with lots of tabs.
Then start TM5 and close what you opened.
You'll see a slightly lower memory allocation per thread from TM5.
When this something else will eat over time memory it'll find some free without killing TM5.


----------



## Luggage

dimkatsv said:


> Child's play and not load from my experience... It is just that you have suspiciously high voltage for such test. But yes, it is basically analog for Prime95. I mean impressive for this DRAM data rate, though. But i had seen more dangerous numbers. Y-cruncher can take my CPU to 85+ degrees as well as PPT to 125W (if i remove limit even more) approximately. Temporarily though. And highest power consumption load doesn't always equal to highest temps btw.
> 
> View attachment 2586172
> 
> 
> --------------------------------------------------
> 
> And here is how hard Y-cruncher hits
> View attachment 2586173
> 
> 
> View attachment 2586174
> 
> 
> 
> 
> Prime 95 runs AVX2 by default. You can also use AVX512, AVX and SSE instructions instead
> 
> P.S. Heaviest modes in Y-Cruncher are BBP, N64, HNT, VST, C17...
> BKT, and SFT are only for frequency stability test.
> FFT is good for rough memory stability test.
> N32 is more sensitive to memory though.
> Currently there is some bug with Y-Cruncher and Ryzen 7000 though. AVX2 tests are hard to pass there.


I don't think his voltage is not _that_ off ?


http://imgur.com/a/TUtASyX


Last ss is same occt test, rest is cold night testing from two weeks back...


----------



## ApT01

The_King said:


> Running CL16 and tCWL 14 can be the cause of some stability problems when lowering RCDRD, this also why RDWR is at 11. Becareful with WRRD 1 with DR it can cause system to hang when RDWR is at 8/9 you may need WRRD at 2 or 3. So first try to change tCWL from 14 to 16.
> 
> Not sure if there is a difference between SR and DR C9BJZ but I'm sure RCDRD can go lower to 19 and be stable.
> You can also do me a favor and save me some time by running 50 cycles on this.  Can change tWTRL/S to 4/8 adjust tWR 16 and RTP 8 if you need to should be more stable


I followed your advice with setting tCWL=16 and I was able to tighten timings some more. I tried tRCDRD at 19 but I get dozens of error 6 instantly. This is where I'm at now:








If I try to tighten them anymore I get multiple error 4s with occasional 5,3 and 14. Though it only errors after a couple of cycles. Any ideas?


----------



## Mr.Sunshine

How do you make TM5 run longer? It only runs about 20 min or 3-4 cycles and says no errors


----------



## The_King

Mr.Sunshine said:


> How do you make TM5 run longer? It only runs about 20 min or 3-4 cycles and says no errors


Edit the cfg file in the bin folder.











ApT01 said:


> I followed your advice with setting tCWL=16 and I was able to tighten timings some more. I tried tRCDRD at 19 but I get dozens of error 6 instantly. This is where I'm at now:
> 
> If I try to tighten them anymore I get multiple error 4s with occasional 5,3 and 14. Though it only errors after a couple of cycles. Any ideas?


What voltage are your running on this. Seems good overall.

For Micron RAM TRAS should be CLX3 so 16X3= 48 and
RC = Rp+TRAS 18 + 48 = 66

Not much more you can tighten unless you go CL15 and tCWL will change to 14 then. That may change tPHYRDL from 28 to 26.


----------



## ManniX-ITA

The_King said:


> Edit the cfg file in the bin folder.


And delete the Cfg.Link file or the changes will not be applied


----------



## dimkatsv

Netblock said:


> Try to get GDM off using the AddrCmd method over the ClkDrvStr. I suggest to do 20-30-24-24 and 59-0-0 and go from there.


Good if it works for some people. For me i cannot boot anything below 40-D-D-D, And i only have remnant chance for stability with 60-D-D-D.
Even with AddrCMD as 64+



ManniX-ITA said:


> But the latest KB5020044 for Windows 11 was a real disaster, at least for me.
> I'm so glad I'm still on Windows 10.


Well, except part that Task Manager got it's theme broken loose and it wasn't fixed before sending update as optional for non-insider users. . . 
I actually like Win 11 interface MUCH more. Well, with start menu tweak, to make it look like Win 10 one, but with style of Win 11 (following system theme). And right-click menu fix as well. But that's about everything.
I am not that numbers driven, even though i understand that you can get higher benches on Win 10. Unless there is some DEEPLY tweaked Win 11 for benchmarking, idk.


----------



## ManniX-ITA

dimkatsv said:


> I actually like Win 11 interface MUCH more. Well, with start menu tweak, to make it look like Win 10 one, but with style of Win 11 (following system theme). And right-click menu fix as well. But that's about everything.
> I am not that numbers driven, even though i understand that you can get higher benches on Win 10. Unless there is some DEEPLY tweaked Win 11 for benchmarking, idk.


I like the interface as well, with the tweak of the menu.
I also like the much better multi monitor support.
This background hidden load stuff it's a big no-go for me.

Benchmarking on Win11 also it's a no-go.
It's just much slower than Win10. Absolutely worthless as a benchOS.
In gaming seems to be slightly better.
But the real deal it's the massive inconsistency.
It's very often slower... slower after a reboot, slower when you re-open an application.
Slower for no reason. Then it's back to normal, and again, and again...
Still a long way before it becomes consistent like Win10.
Was the same between Win7 and Win10 in the early days.


----------



## ManniX-ITA

Oh boy.
After 3 years and 2 generations of Ryzen CPUs, I have finally fixed the dreaded USB voltage drop-outs.
Not sure how many whole days I've spent tweaking and fine-tuning BIOS settings and voltages to fix it.
I don't want to think about it.
And it was there in front of my eyes the whole time...
Just one switch. Enabling USB Selective Suspend in the power plan it's all that was needed.
Of course you must have already the correct SOC and VDDG IOD voltages set.

Thanks AMD for not taking care of it for years and driving me mad, really appreciated.
Not that Intel with the P/E-Cores mess made life better for his customers.
They both just disregarded the crucial point of providing a power plan that _at least works._
Seems they are in a tight competition to piss off who pays them big money. Must be funny but I don't see how


----------



## dimkatsv

ManniX-ITA said:


> I have finally fixed the dreaded USB voltage drop-outs.





ManniX-ITA said:


> And it was there in front of my eyes the whole time...
> Just one switch. Enabling USB Selective Suspend in the power plan it's all that was needed.


Strange, i have no such issue. Are you sure it is AMD issue, and not mobo manufacturer UEFI related problem?


----------



## ManniX-ITA

dimkatsv said:


> Strange, i have no such issue. Are you sure it is AMD issue, and not mobo manufacturer UEFI related problem?


Not everyone has it.

It's the most common issue with Ryzen 3000/5000.
My 5950X B0 had it at FCLK 1900 and not at FCLK 2000.
This crap 5950X B2 has been very problematic.
Depends also on how many USB devices and Hubs are connected.
It can be fixed with an adequate VSOC and VDDG IOD.
But not always and often not completely.

So far, so good.
I can finally play WWZ smoothly...
I can also connect and use 2 USB SSD at the same time without Windows dropping devices.

Coming from many Intel generations, I've been used to avoid it like the black death.
But on AMD seems to help instead.


----------



## 99belle99

I have a 3700X since near launch with my X570 Aorus Ultra board and I never had USB issues luckily.


----------



## Artylol

Gents, I'm proud to announce my investigation on IF OC:

My Ryzen 5 5600 (non-x) B2 stepping is able to boot stock up to 2066 MHz IF, but with WHEA's and USB/audio stuttering above 2000 MHz. Stock stable at 1900 MHz, easily stabilized 1933 with low voltages. I'm testing WHEA's with TM5 1usmus_v3, logging with HWINFO. Many people tell that every CPU behaves differently to IF OC, so your results may vary. Here are my findings:


I started from baseline VSOC=1.1V, VDDP=0.9V, VDDG_CCD=0.9V, VDDG_IOD 1.025, VDD18=1.8V. Varied voltages one by one measuring error rate of WHEA's. 
My CPU will spit exactly 100 errors (in 1 x100 batch at a time) exactly 2 minutes on 2000MHz. Like a clock. In my opinion it is indicator of high instability. Playing with voltages, especially VSOC can reduce amount of errors. But more fascinating, is that CPU can start spit out same 100 errors every 2 minutes, but in ~5-15 batches. If your stabilize more, it will be 100 errors every 2 minutes in ~1-3 batches. That's what you want to achieve as your first step - find required VSOC for stable operation with WHEA's
Increase VDD18 (also called PLL voltage or something) from stock 1.8 higher in 0.04 steps. This has massive effect on amount of WHEA's, almost completely eliminating it. I was able to bring down to 1 error per hour.
Play with other voltages if results is unsatisfactory. In my case here are interesting findings:
Increasing VSOC on stable IF 1933MHz from 1.1V to 1.15V caused WHEA's
100 errors per 2 minutes mean you don't have enough VSOC
Scaling from most voltages is negligible, so most should be left at baseline above. Pushing 2000MHz and beyond may require to increase them all.
Most crucial for WHEA free operation is combination of VSOC and VDD18

Finally, I stabilized 1966 and 2000. Will tweak a bit more and share results if any. I would be happy to hear feedback


----------



## dimkatsv

Artylol said:


> My CPU will spit exactly 100 errors (in 1 x100 batch at a time) exactly 2 minutes on 2000MHz. Like a clock. In my opinion it is indicator of high instability


Believe me... It is not that bad)
Bad is when you get 100 errors in less than seconds of RAM stress test). It is fascinating, how good data correction works for some samples like mine. Because everything runs OK, no USB fallout had been noticed, etc. But i am not comfy with having WHEA's at all.



Artylol said:


> Increase VDD18 (also called PLL voltage or something) from stock 1.8 higher in 0.04 steps. This has massive effect on amount of WHEA's, almost completely eliminating it. I was able to bring down to 1 error per hour.


Yeah, VDDG and VDD18 both have major effect on FCLK stability. VSOC is also important up to certain point. Then it starts hindering stability. Other frequencies less. Only if it is really on border.
For example i run FCLK=1900, VSOC=1.03V, VDDP = 900-950mV, VDDG=1000mV, VDD18=Default.
I can technically run FCLK=1933 without issues. But after 1966-2000 i won't be able to stabilize it even with VSOC=1.2 and VDDG=1100. Maybe it will become bit better with VDD18=1.9V+ But i won't test this for safety reasons.


----------



## Imprezzion

I can run error free at 1966 at 1.15 vSOC SET, 0.900 VDDP, 1.05 IOD 1.00 CCD, stock 1.80v VDD. I'm assuming that's quite a good result and considered totally safe?

I just flashed the new PBO BIOS on my B550-A and a new 980 Pro 1TB I got on black friday so I'll also do a full fresh Windows install but I have to re do the memory OC obviously. Just asking above question sort of so I can only remake this profile. 

I have another one for 1900 at 1.10 vSOC SET, 0.880 VDDP, 0.960 IOD and 0.940 CCD also error free just in case but I prefer the higher memory frequency and bandwidth.


----------



## Mr.Sunshine

So I changed TM5 to run longer. But now system is randomly resetting during testing. After about 40min. No WHEA errors. Just come back to check on it and its restarted the system. Any ideas?


----------



## dimkatsv

Mr.Sunshine said:


> So I changed TM5 to run longer. But now system is randomly resetting during testing. After about 40min. No WHEA errors. Just come back to check on it and its restarted the system. Any ideas?


Check if there were bluescreens? 
Check CPU stability?


----------



## Mr.Sunshine

Running core cycler now to check if anything has changed but system hasn't had any issue in past. I've never used TM5 to check memory just Memtest that has run for 23 hrs before I get 1 error. Was going to use TM5 to see if I can pin point that error.

Just checked in event viewer:

Log Name: System
Source: TPM
Date: 12/2/2022 7:42:20 PM
Event ID: 15
Description:
The device driver for the Trusted Platform Module (TPM) encountered a non-recoverable error in the TPM hardware, which prevents TPM services (such as data encryption) from being used. For further help, please contact the computer manufacturer.

Log Name: System
Source: Microsoft-Windows-WER-SystemErrorReporting
Date: 12/2/2022 7:42:27 PM
Event ID: 1001
Task Category: None
Level: Error
Keywords: Classic
User: N/A
Computer: 
Description:
The computer has rebooted from a bugcheck. The bugcheck was: 0x0000001a (0x0000000000000411, 0xffffbd00ff1f4ff8, 0x000000019ad7d880, 0xff06bd00ff1f4ff8). A dump was saved in: C:\WINDOWS\Minidump\120222-8265-01.dmp. Report Id: bf098e40-2c36-4bcf-b0cb-4b5789fa7020.

Log Name: Application
Source: Microsoft-Windows-CertificateServicesClient-CertEnroll
Date: 12/2/2022 7:42:31 PM
Event ID: 86
Task Category: None
Level: Error
Keywords: Classic
User: SYSTEM
Computer: 
Description:
SCEP Certificate enrollment initialization for WORKGROUP\DESKTOP-C870P3A$ via https://AMD-KeyId-578c545f796951421221a4a578acdb5f682f89c8.microsoftaik.azure.net/templates/Aik/scep failed:

GetCACaps
GetCACaps: Not Found
{"Message":"The authority \"amd-keyid-578c545f796951421221a4a578acdb5f682f89c8.microsoftaik.azure.net\" does not exist."}
HTTP/1.1 404 Not Found
Date: Sat, 03 Dec 2022 00:42:31 GMT
Content-Length: 121
Content-Type: application/json; charset=utf-8
X-Content-Type-Options: nosniff
Strict-Transport-Security: max-age=31536000;includeSubDomains
x-ms-request-id: fe06380e-0431-4634-ab47-37b1e77c7aa4

Method: GET(203ms)
Stage: GetCACaps
Not found (404). 0x80190194 (-2145844844 HTTP_E_STATUS_NOT_FOUND)


Both restart are same errors. Only does this when running TM5


----------



## ManniX-ITA

Artylol said:


> I would be happy to hear feedback


The amount of WHEA is not really relevant (other than being annoying).
What matters is if it's slower or faster than FCLK 1900.
Test with y-cruncher benchmark pi 2.5b, compare the time.
Then download and configure the xmr-stak-rx monero miner.
Compare the hash rate running it, not the benchmark mode.


----------



## GhOsT662

Any advice on how I can stabilize 4x8gb with gear down mode disabled on an asus x470f motherboard which from the research I've done has a topological layout,
memory voltage is 1.5.


----------



## ManniX-ITA

GhOsT662 said:


> Qualche consiglio su come posso stabilizzare 4x8gb con la modalità gear down disabilitata su una scheda madre asus x470f che dalla ricerca che ho fatto ha un layout topologico,
> la tensione della memoria è 1,5.


Post in English only here please 

Why not tRAS/tRC 28/42?
Would be easier with 2T GDM Off.


----------



## GhOsT662

ManniX-ITA said:


> Post in English only here please
> 
> Why not tRAS/tRC 28/42?
> Would be easier with 2T GDM Off.




laziness, I was testing the times until late in the evening and I started with these settings to start the tm5 extreme anta stress test. As for the command rate 2t from what I've read shouldn't it be slower in terms of writing and reading than 1t gear down mode on?


P.S.
I hope this time he managed to publish in English


----------



## ManniX-ITA

GhOsT662 said:


> As for the command rate 2t from what I've read shouldn't it be slower in terms of writing and reading than 1t gear down mode on?


Yes it's slower but not by that much. While it's 10x times easier to achieve.
You need a lot of VDIMM for CL14 1T, probably even more for 4 x DIMMs.
1.5V could be not enough. I have a set of Viper SR and they need 1.56V minimum.

There's also the option to try 1T GDM Off with AddrCmdSetup to 55/56.
Slightly slower but requires less VDIMM and is lot easier as well.



GhOsT662 said:


> I hope this time he managed to publish in English


Yes, it's in English


----------



## GhOsT662

ManniX-ITA said:


> Yes it's slower but not by that much. While it's 10x times easier to achieve.
> You need a lot of VDIMM for CL14 1T, probably even more for 4 x DIMMs.
> 1.5V could be not enough. I have a set of Viper SR and they need 1.56V minimum.
> 
> There's also the option to try 1T GDM Off with AddrCmdSetup to 55/56.
> Slightly slower but requires less VDIMM and is lot easier as well.
> 
> 
> 
> Yes, it's in English




Interesting i will try with 1T GDM Off with AddrCmdSetup at 55/56. Also is there any chance i can get command rate 1t with gdm off at 3733 cl15 at 1.55 temps shouldn't be a problem as i have alseye ram cooler kit in a corsair 7000d case.


----------



## Imprezzion

Mr.Sunshine said:


> Running core cycler now to check if anything has changed but system hasn't had any issue in past. I've never used TM5 to check memory just Memtest that has run for 23 hrs before I get 1 error. Was going to use TM5 to see if I can pin point that error.
> 
> Just checked in event viewer:
> 
> Log Name: System
> Source: TPM
> Date: 12/2/2022 7:42:20 PM
> Event ID: 15
> Description:
> The device driver for the Trusted Platform Module (TPM) encountered a non-recoverable error in the TPM hardware, which prevents TPM services (such as data encryption) from being used. For further help, please contact the computer manufacturer.
> 
> Log Name: System
> Source: Microsoft-Windows-WER-SystemErrorReporting
> Date: 12/2/2022 7:42:27 PM
> Event ID: 1001
> Task Category: None
> Level: Error
> Keywords: Classic
> User: N/A
> Computer:
> Description:
> The computer has rebooted from a bugcheck. The bugcheck was: 0x0000001a (0x0000000000000411, 0xffffbd00ff1f4ff8, 0x000000019ad7d880, 0xff06bd00ff1f4ff8). A dump was saved in: C:\WINDOWS\Minidump\120222-8265-01.dmp. Report Id: bf098e40-2c36-4bcf-b0cb-4b5789fa7020.
> 
> Log Name: Application
> Source: Microsoft-Windows-CertificateServicesClient-CertEnroll
> Date: 12/2/2022 7:42:31 PM
> Event ID: 86
> Task Category: None
> Level: Error
> Keywords: Classic
> User: SYSTEM
> Computer:
> Description:
> SCEP Certificate enrollment initialization for WORKGROUP\DESKTOP-C870P3A$ via https://AMD-KeyId-578c545f796951421221a4a578acdb5f682f89c8.microsoftaik.azure.net/templates/Aik/scep failed:
> 
> GetCACaps
> GetCACaps: Not Found
> {"Message":"The authority \"amd-keyid-578c545f796951421221a4a578acdb5f682f89c8.microsoftaik.azure.net\" does not exist."}
> HTTP/1.1 404 Not Found
> Date: Sat, 03 Dec 2022 00:42:31 GMT
> Content-Length: 121
> Content-Type: application/json; charset=utf-8
> X-Content-Type-Options: nosniff
> Strict-Transport-Security: max-age=31536000;includeSubDomains
> x-ms-request-id: fe06380e-0431-4634-ab47-37b1e77c7aa4
> 
> Method: GET(203ms)
> Stage: GetCACaps
> Not found (404). 0x80190194 (-2145844844 HTTP_E_STATUS_NOT_FOUND)
> 
> 
> Both restart are same errors. Only does this when running TM5


A TPM crash.. ok weird. Try in device Manager to wipe all TPM drivers, boot to bios, wipe TPM data there as well, boot back to windows and let windows update install the driver again. Might fix it. If you run windows 10 or 11 but dont care about TPM security features just disable it.


----------



## ManniX-ITA

Imprezzion said:


> A TPM crash.. ok weird. Try in device Manager to wipe all TPM drivers, boot to bios, wipe TPM data there as well, boot back to windows and let windows update install the driver again. Might fix it. If you run windows 10 or 11 but dont care about TPM security features just disable it.


@Mr.Sunshine 

The BSOD is about memory corruption.
Yes the TPM crashed but that's likely because the system memory was corrupted.
I'd say you have to fix the memory profile settings.


----------



## Netblock

dimkatsv said:


> Good if it works for some people. For me i cannot boot anything below 40-D-D-D, And i only have remnant chance for stability with 60-D-D-D.
> Even with AddrCMD as 64+


You might misunderstand the Setups actually do. 56 is a 'stronger' value than 59 or 63; and 63 is as weak a value as 1.

They are about the setup and hold windows in regard to clock edges. In a way, a setup violation means the signal is too late; and a hold violation means the signal is too eager for the next cycle.

For the actual value in the firmware menus, the Setups are an encoded thing: Check out the AddrCmdSetup description on page 103 of this BKDG, alongside the graph on page 246 of this other BKDG doc. (note: command/address for DDR4 is SDR). "UI" is one half of a clock cycle.

By default, the data change starts on the clock fall and held until the clock fall. For what AMD is doing, Setup values 1-31 increasingly helps with hold violations by delaying changing the signal, which introduces a risk for a setup violation. Moving to 32 shifts the start of the change to the beginning of the clock cycle, wildly helping setup violations by introducing a catastrophic hold violation; and then values 33-63 increasingly helps with aiding that catastrophic hold violation.

In other words, values from 1 to 31 increasingly helps hold violations, and values from 63 to 32 increasingly helps setup violations. A Setup value of 48 would take 1/4 clock of the hold and give it to the setup; conversely, a Setup value of 16 would take 1/4 clock of the setup and give it to the hold.

So what the Setups for AMD are useful for is to pull in or postpone within the clock cycle when to change the associated pins so that the voltage is stable for the clock's rising edge.

Furthermore, AMD defines 2T command rate as "One additional MEMCLK of setup time is provided on all DRAM address and control signals (not including CS, CKE, and ODT)". This can imply that if 2T brings major stability, playing with AddrCmdSetup might help.




GhOsT662 said:


> Any advice on how I can stabilize 4x8gb with gear down mode disabled on an asus x470f motherboard which from the research I've done has a topological layout,
> memory voltage is 1.5.


I suggest to read above too.

I'm running a tri-rank 2x8+2x16 Rev.E a hair over 3800 with GDM off:


http://imgur.com/a/i1AODlq

My images there are slightly out of date. I now have ClkDrvStr to 20 ohms and ProcODT to 34.3 ohms; I also have tWTRS to 2.

I'm in a casual process of trying to get tRDRD DD down from 5 to 4; playing with the command-address bus (specifically CsODT) allowed me to get tRDRD SD to 4, but different-dimm is notably harder.


----------



## Merciless_Rick

could i get some feedback here? I know that there is a sheet explaining what the various errors mean, sometimes the explanation is still a bit broad when trying to track down the root cause. not getting any crashes, and hwinfo doesnt even register these errors...system seems to be running great, but clearly there are more than a few issues with my timings
anything jump out as being seriously wrong just based on my screen shots? DIMM temps reached 50c during testing but typically stay under 45c during long gaming sessions. Voltage is set at 1.48v but my EVGA Dark X570 always overvolts, based on hwinfo and bios monitoring my sticks are getting 1.517v


----------



## dimkatsv

Merciless_Rick said:


> View attachment 2586700


Oh my... You might as well try to collect them all at once. 
Having 15/16 errored out tests feels wrong, but in other way.


----------



## 99belle99

You are getting all those errors even with setup 56, strange.

For my post to be more helpful you will have to dial back the timings and find a stable point and then work on tightening them up till it errors again. It will take alot of time but you will get there. And an easier way is use DRAM calculator to guide you first. That's what I done and I'm no expert.

You should also watch it while it's running the test and if it errors out which it will do most likely near the start unless you have good timings just close the TM5 app. No point in running it for so long and get as many errors as you did.


----------



## Artylol

ManniX-ITA said:


> The amount of WHEA is not really relevant (other than being annoying).
> What matters is if it's slower or faster than FCLK 1900.
> Test with y-cruncher benchmark pi 2.5b, compare the time.
> Then download and configure the xmr-stak-rx monero miner.
> Compare the hash rate running it, not the benchmark mode.


I actually do lose performance but it seems like due to TDP and EDC constraints. Raising them allows to push scores on 2000 highers than 1900. I now understand that I don't necessarily test IF OC in the same condition for different IF Clock because higher IOD power consumption eats up CCD budget. In order to make proper test, I guess I need to lock CPU speed at something reasonable like 4GHz and test different setups. 

2000 results were quite a bit worse than 1900, but now 2000 makes new records.


----------



## Imprezzion

See anything grossly wrong here guys or? Outside of it being tPHYRDL 26/28 which I don't seem to be able to correct no matter what I change. 1,450v vDIMM btw. Running TM5 1usmus as we speak.


----------



## Merciless_Rick

Imprezzion said:


> See anything grossly wrong here guys or? Outside of it being tPHYRDL 26/28 which I don't seem to be able to correct no matter what I change. 1,450v vDIMM btw. Running TM5 1usmus as we speak.
> 
> View attachment 2586736


I bet if you lowered procOdt I bet you could get it back to tphyrdl 26
May also need to mess with iod and soc voltage
2T seems to get 28 tphyrdl more often than 1T
Good timings, and impressive latency considering your CPU


----------



## Netblock

Imprezzion said:


> Outside of it being tPHYRDL 26/28 which I don't seem to be able to correct no matter what I change.


iirc, 26/26 with 2T would prefer an even tCL.

It's likely that you can get 1T-off 26/26.


tRDWR and tWRRD loose; try 9/1? if tWRRD can't be 1, you should be able to get it to 1 if you further lower tCWL from tCL (for their definitions, tRDWR has +(tCL-tCWL) and tWRRD has -(tCL-tCWL)).

tRCDWR can be 8. tRP might be able to come down a tick or two.





Merciless_Rick said:


> could i get some feedback here? I know that there is a sheet explaining what the various errors mean, sometimes the explanation is still a bit broad when trying to track down the root cause. not getting any crashes, and hwinfo doesnt even register these errors...system seems to be running great, but clearly there are more than a few issues with my timings
> anything jump out as being seriously wrong just based on my screen shots? DIMM temps reached 50c during testing but typically stay under 45c during long gaming sessions. Voltage is set at 1.48v but my EVGA Dark X570 always overvolts, based on hwinfo and bios monitoring my sticks are getting 1.517v
> View attachment 2586700
> 
> View attachment 2586699


Do you achieve stability with GDM on or 2T? If so, AddrCmdSetup with a tSetup bias tends to hate ClkDrvStr; I suggest to drop clock to 20 ohms and raise addrcmd to like 30 ohms. I also suggest messing with CsODT as you are indeed rank selecting.

RTT_Nominal shouldn't do anything for you as you have 1 DIMM per channel; disable it for a (probably immeasurable) benefit in temperature/power.


----------



## ManniX-ITA

Artylol said:


> I actually do lose performance but it seems like due to TDP and EDC constraints.


It just needs more for higher FCLK.
What matters is the total power budget and that's something you can't control.
You can raise voltages to let it pump more but there's a breakeven point.
After that, the performances will start to drop.



Artylol said:


> In order to make proper test, I guess I need to lock CPU speed at something reasonable like 4GHz and test different setups.


Don't. Static OC needs different voltages and settings than PBO.
Always compare PBO vs PBO or Static vs Static.



Artylol said:


> 2000 results were quite a bit worse than 1900, but now 2000 makes new records.


That's promising but if you really want to know test as I told you.
Another good test is Linpack Xtreme; but the result can be thermally limited.
If you top the thermal limit, you don't know for sure if it's the FCLK lowering the score or the thermal throttling.


----------



## Luggage

ManniX-ITA said:


> It just needs more for higher FCLK.
> What matters is the total power budget and that's something you can't control.
> You can raise voltages to let it pump more but there's a breakeven point.
> After that, the performances will start to drop.
> 
> 
> 
> Don't. Static OC needs different voltages and settings than PBO.
> Always compare PBO vs PBO or Static vs Static.
> 
> 
> 
> That's promising but if you really want to know test as I told you.
> Another good test is Linpack Xtreme; but the result can be thermally limited.
> If you top the thermal limit, you don't know for sure if it's the FCLK lowering the score or the thermal throttling.


With pbo you are always thermally limited though. (I say, re-testing limits with 5C water because I rebuilt my loop from last winter)


----------



## ManniX-ITA

Luggage said:


> With pbo you are always thermally limited though. (I say, re-testing limits with 5C water because I rebuilt my loop from last winter)


The problem is specific to Linpack Xtreme.
If you are thermal limited, y-cruncher and xmr-stak-rk will give you consistent results.
You can easily spot if the lower scores are due to the FCLK.
If you raise the FCLK, even thermal limited, you'll get better results.
Not with Linpack Xtreme; you'll hit earlier the thermal limit, you'll get inconsistent results and raising the FCLK will likely lower even more the scores.


----------



## dimkatsv

ManniX-ITA said:


> If you are thermal limited, y-cruncher and xmr-stak-rk will give you consistent results.


Idk what limits are you, guys, using for PBO that you are so easily themally limited everywhere. Unless you mean soft limit at about 82-85 degrees (and that's only in heaviest stress tests).
For example i can hit only soft thermal limit with 5600X at about 115W power consumption (and that's really a lot of energy for 5600X... Far beyond efficiency point, ngl). Ofc, lower temps - higher frequency = welcome inconsistencies
And at temperature heavy load even if i will set power limit to 120, my CPU just won't take it. So it won't heat.
Well, unless i force OC it with constant voltage and try to run AVX on 4750+ mHz frequency. Then it will instantly throttle.


----------



## Luggage

dimkatsv said:


> Idk what limits are you, guys, using for PBO that you are so easily themally limited everywhere. Unless you mean soft limit at about 82-85 degrees (and that's only in heaviest stress tests).
> For example i can hit only soft thermal limit with 5600X at about 115W power consumption (and that's really a lot of energy for 5600X... Far beyond efficiency point, ngl). Ofc, lower temps - higher frequency = welcome inconsistencies
> And at temperature heavy load even if i will set power limit to 120, my CPU just won't take it. So it won't heat.
> Well, unless i force OC it with constant voltage and try to run AVX on 4750+ mHz frequency. Then it will instantly throttle.


For example r23 (or was it cpuz?) starts clocking down from 61-62C on my 5800X.
I’ll see if I can turn off/minimize my pumps and get a graph…


----------



## ManniX-ITA

dimkatsv said:


> Idk what limits are you, guys, using for PBO that you are so easily themally limited everywhere. Unless you mean soft limit at about 82-85 degrees (and that's only in heaviest stress tests).
> For example i can hit only soft thermal limit with 5600X at about 115W power consumption (and that's really a lot of energy for 5600X... Far beyond efficiency point, ngl). Ofc, lower temps - higher frequency = welcome inconsistencies
> And at temperature heavy load even if i will set power limit to 120, my CPU just won't take it. So it won't heat.
> Well, unless i force OC it with constant voltage and try to run AVX on 4750+ mHz frequency. Then it will instantly throttle.


It was not a comment specific to the 5600X; of course depends on your cooling.
There's a lot of people running a 5600X without a very good air cooler, it doesn't really need a royal cooling solution to keep it below 90°C.
But if you are running PBO very tuned, high scalar, with a small positive offset, you can get there.
It's more about going up to the limit to see if the FCLK can keep up or not.
Running at FCLK 2000 generates more heat, about 2-3°C per CCD/CCX, plus the heat from the higher VSOC which is usually around 1.2V.

Did you try Linpack Xtreme?
If you top 85°C with everything else, likely it will top 90°C with the heavy test and 5 cycles.

Setting a power limit of course avoids thermal throttling, easy win 
In theory PPT throttling is better than HTC throttling, but there's a catch.
The CPU doesn't generate the same heat regardless what is the workload.
Limiting PPT will risk to leave a lot of performances on the table.
The best solution is to have proper cooling, enough to set PPT above the max and never reach HTC limit.

Also consider that with HWInfo and in general via all software means, you are not seeing the real max peaks.
I have an MSI Unify-X and I can see the board CPU temperature on the debug leds.
There are peaks during y-cruncher pi2.5b that you can't see in HWInfo even with 250ms pooling rate.
So you may think you never reach 95°C but in reality the CPU does, they are just too quick for software pooling or to trigger thermal throttling.


----------



## Luggage

Soo I can't turn off my pumps - thanks to the octo >_<

Edit: So I gave up on that after a new cold weather pbo baseline vs stock baseline



http://imgur.com/a/Zw7smvd


----------



## Imprezzion

Netblock said:


> iirc, 26/26 with 2T would prefer an even tCL.
> 
> It's likely that you can get 1T-off 26/26.
> 
> 
> tRDWR and tWRRD loose; try 9/1? if tWRRD can't be 1, you should be able to get it to 1 if you further lower tCWL from tCL (for their definitions, tRDWR has +(tCL-tCWL) and tWRRD has -(tCL-tCWL)).
> 
> tRCDWR can be 8. tRP might be able to come down a tick or two.
> 
> 
> 
> 
> 
> Do you achieve stability with GDM on or 2T? If so, AddrCmdSetup with a tSetup bias tends to hate ClkDrvStr; I suggest to drop clock to 20 ohms and raise addrcmd to like 30 ohms. I also suggest messing with CsODT as you are indeed rank selecting.
> 
> RTT_Nominal shouldn't do anything for you as you have 1 DIMM per channel; disable it for a (probably immeasurable) benefit in temperature/power.


tWRRD can't boot under 6 for me no matter what I do. Even 10/4 will not POST while 9/6 works fine.

I can get stable at 3800 c14 1T GDM Off with AddrCmdSetup 56 and 40 ClkDrvStr. Never been able to do 3933 1T GDM Off stable at all.

This wasn't stable btw, nowhere near enough vDIMM for CL15 on 3933. It barely passed 40 minutes before spitting several different error numbers. 7, 12, 0, 1.. I know above timings are fine at 1.45v with just 16-16-16 but I am trying to tighten that a bit..

EDIT: With 1.55v vDIMM scores are great, write is fine, latency is great, just has 1 error in TM5 1usmus I have to fix. It threw a single error #13 after 1h25m unfortunately. Not overheating, DIMM's at 42.1/41.9c active cooled so not temp related. Could I maybe just need 1-2 ticks more vDIMM or a small adjustment to drvstr's?


----------



## dimkatsv

ManniX-ITA said:


> But if you are running PBO very tuned, high scalar, with a small positive offset, you can get there.


PBO very tuned doesn't match with high scalar (ok this one is at least depends from sample to sample) and no way it matches with positive offset.
Your CPU will heat more and downclock even faster, because V/F curve is so high, it will limit your max frequency by itself.
Frequency overdrive shifts curves up, btw. You must have negative CO setup just to compensate it. Otherwise efficiency goes to trashbin.



ManniX-ITA said:


> Did you try Linpack Xtreme?
> If you top 85°C with everything else, likely it will top 90°C with the heavy test and 5 cycles.


Linpack Xtreme is basically Prime95 Small FFT with intervals added. In terms of power consumption and heat generation it is at least. And i run this one for HOURS at some point
Really? I don't have water cooler for it to heat up during tests. More than that, my temps are usually at their highest at very beginning of test, and then drop down by degree or, sometimes even 2.
I can also tell you that even with 120W limit highest i got is 85 degrees at beginning of first run, when consumption was at 115W max. Temps afterwards were lower down to 83-84 degrees even though CPU could take up to 120W
Same with y-cruncher. It can take 120W as well, but only on loads that are spread on calculating blocks more so it generates less hit than some 110-115W load.
I also don't see peaks higher than 85.8 (well almost 86) even with HWINFO 50ms resolution

----------------------
Quicker fan response time is generally a good thing though (so as setting it to 100% before benchmark). 5600X cooling is extremely resonsive to every freaking factor. Ambient temp, how polished are contact points, thermal paste.
I can improve my cooling solution more, but don't wanna waste more time and involve more risks coming with that.

Btw i still prefer to use 110W limit instead of 120. Unless i am doing some hardcore benchmark stuff. Because max temps just go down to about 79-81 degrees from 83-85. And you know. these 4 degrees are often diminish gains too much for it to be viable for efficiency. It is like, 0.4% gain at best.


----------



## Luggage

ManniX-ITA said:


> It was not a comment specific to the 5600X; of course depends on your cooling.
> There's a lot of people running a 5600X without a very good air cooler, it doesn't really need a royal cooling solution to keep it below 90°C.
> But if you are running PBO very tuned, high scalar, with a small positive offset, you can get there.
> It's more about going up to the limit to see if the FCLK can keep up or not.
> Running at FCLK 2000 generates more heat, about 2-3°C per CCD/CCX, plus the heat from the higher VSOC which is usually around 1.2V.
> 
> Did you try Linpack Xtreme?
> If you top 85°C with everything else, likely it will top 90°C with the heavy test and 5 cycles.
> 
> Setting a power limit of course avoids thermal throttling, easy win
> In theory PPT throttling is better than HTC throttling, but there's a catch.
> The CPU doesn't generate the same heat regardless what is the workload.
> Limiting PPT will risk to leave a lot of performances on the table.
> The best solution is to have proper cooling, enough to set PPT above the max and never reach HTC limit.
> 
> Also consider that with HWInfo and in general via all software means, you are not seeing the real max peaks.
> I have an MSI Unify-X and I can see the board CPU temperature on the debug leds.
> There are peaks during y-cruncher pi2.5b that you can't see in HWInfo even with 250ms pooling rate.
> So you may think you never reach 95°C but in reality the CPU does, they are just too quick for software pooling or to trigger thermal throttling.


Gah! You put me down the rabbits hole again - trying to tune PBO for LinX >_<



http://imgur.com/a/PXe2jiE


fMax limit appears to behave very similar to the other PBO-limits, best results is to keep it "lagom" "a bit" higher than what you can reach but not too much higher, but also not to close to what you reach...


----------



## Worgened

Hi guys İ did some tweak on rams but i have a problem. First stick of ram a2 tphyrdl is 26 and second is tphyrdl 28. Can you help me how can i do them same as tphyrdl 26. I have researched but not sure where to start. Thanks for your answer.


----------



## ManniX-ITA

dimkatsv said:


> PBO very tuned doesn't match with high scalar (ok this one is at least depends from sample to sample) and no way it matches with positive offset.
> Your CPU will heat more and downclock even faster, because V/F curve is so high, it will limit your max frequency by itself.


Depends on the sample 
This terrible 5950X needs a positive offset and works better with scalar 8x.
The effect of the scalar is now almost nothing in single/low thread, gets significative with high/full threading.
If you can keep it reasonably cool, it improves a little the scores (100-300 GB5 MT points).



dimkatsv said:


> More than that, my temps are usually at their highest at very beginning of test, and then drop down by degree or, sometimes even 2.


Among the stress tests it's usually the worst in heat generation, even more than P95 Small FFT for me.
Probably is the fan curve as you said. Did you test with fixed 100% CPU fan?

For curiosity, which air cooler do you have?



dimkatsv said:


> Btw i still prefer to use 110W limit instead of 120. Unless i am doing some hardcore benchmark stuff. Because max temps just go down to about 79-81 degrees from 83-85. And you know. these 4 degrees are often diminish gains too much for it to be viable for efficiency. It is like, 0.4% gain at best.


Yes indeed it's an option. If you don't need that last small performance delta, it's the most expensive in term of power and thermals. 
The 5000s are still unbeatable for efficiency, taking in account all factors.


----------



## dimkatsv

ManniX-ITA said:


> Probably is the fan curve as you said. Did you test with fixed 100% CPU fan?
> 
> For curiosity, which air cooler do you have?


Actually no, but my fans are set up with manual curve that maxes out at 80 degrees. With response time of 3 seconds (so it wouldn't ramp up on completely random load.)
I use ID-COOLING 226-XT (black). Tbh, there are more efficient coolers, this one was kind of cheap for me to buy for it's performance level. But removing heat from IHS is more important for Zen 3, rather than overall block heat capacity. Also higher temp difference between ambient, cooling pipes and contact plate you can make - easier cooling will become

I have my cooler base grinded down manually on 1500 grit whetstone, so it nests on CCD place better. I mean... I hadn't grinded down IHS, and f*ck dealing with copper dust in water while grinding it. It is conductive, and i don't want ANY of it close to CPU pins.
I also didn't polish my cooler base. There is not much reason to do this, unless you polish both sides. So results can be better for sure. But it must be done profesionally with good precision.
I could've used liquid metal, but my experience with it is almost none, it can destroy my whole PC and i don't have enough money to just buy another one.

P.S. I know scalar works, but not for my sample. Even base FIT limit for my CPU is so small, and despite that i never actually hit it.
Like... First one with Scalar = x10, second one with Scalar = x1


Spoiler























To be fair. My efficiency was better before. And should not be thermal paste or other stuff.. Dust maybe... Or time. Who knows
I had around 4530 mHz in Prime95 small FFT.
Now i only have about 4475

UPD: Found the culprit. Fixed. Now lower temps and higher frequencies (mostly second part). With 115W now i do get my 4520-4560 mHz, and not 4475. With 110W, i get 4500 mHz approx (usually 4995-4507 or so)

Small attention to details check. Try to find CCD


Spoiler























Welcome to the world of viscosity/temperature dependency and high power push through small chip.
Should i lower my PPT limit to prolong thermal paste application? I am too lazy to do this every few months.


----------



## Mr.Sunshine

So ran TM5 for 8 hour test and came back with 3 errors. two on 15 and one 4. Any ideas on what to change?


----------



## Veii

@dimkatsv @ManniX-ITA as for 5600X specific 
ProcHot is 65° (hidden recently, as value zero)
Only 5800X upwards , procHot is 95° 

Soo thermal "hard" cap is 65° , irrelevant of what THM is set at
Shutdown temp seems to be identical across all samples, but i remember times where it was 95° (shutdown limit) on dual CCDs.


----------



## dimkatsv

Veii said:


> Soo thermal "hard" cap is 65° , irrelevant of what THM is set at


If it was HARD cap, CPU should've throttled into oblivion just to fit under this value.But no, 81-85 degrees are easy to do.
And ProcHot can be seen through monitoring tool. Yes, it is set 65, but not gonna lie, i didn't know that 5800-5950X had different value. Temps are still go way beyond 65 degrees.
Now if it would've been 7600X with cap at 65 degrees, then CPU should've never got beyond that point.

More than that, i can actually enforce 65 degrees cap with HTC. It doesn't look as nice because HWINFO begins to report it as RED VALUE (and not usual white),
But at CB23 with 65 degrees cap my CPU uses 81.2W and have 65.3 Tdie temp. And clocks about 4430 mHz instead of 4600.
Prime95 small uses 80.5 - 81W as well, and clocks down to about 3970-3990 mHz from 4530. Would've been higher with maxed fan speed, but i am too lazy and left it at low value
Granted frequencies before downclock are from 115W power limit

Funniest part, is that despite HWINFO showing 65 degrees in red zone, it doesn't set checkmark for neither HTC or PROCHOT limitations.









Hmm... Now i am thinking. Should i just go with HTC limit and remove power limit instead? CPU can take 120+W in some tasks, but it doesn't heat as much in them.

And if i use 80 degrees HTC, i get 4470-4490 mHz at Prime95 Small. Well, because 117W give me about 83 degrees temps instead for this 50 mHz boost (which will downclock after some time to about 4500-4525 on 114W PPT because of temps)


----------



## Artylol

Is there a specific reason why below is stable








and if change timings to 3800 15-15-15-15-30-45 it does not boot? absolute timing for 3600x14 is 7.77ns,while 3800x15 is 7.9ns. It should be booting by laws of physics


----------



## dimkatsv

Artylol said:


> and if change timings to 3800 15-15-15-15-30-45 it does not boot?


Try booting with increasing them one by one
Start with tRC, then tRCDRD, then tRP, then tCL

I have similar issues. I just cannot randomly loose up my timings, system isn't booting. But one by one seemingly worked for me?


----------



## Netblock

Imprezzion said:


> tWRRD can't boot under 6 for me no matter what I do. Even 10/4 will not POST while 9/6 works fine.
> 
> I can get stable at 3800 c14 1T GDM Off with AddrCmdSetup 56 and 40 ClkDrvStr. Never been able to do 3933 1T GDM Off stable at all.
> 
> This wasn't stable btw, nowhere near enough vDIMM for CL15 on 3933. It barely passed 40 minutes before spitting several different error numbers. 7, 12, 0, 1.. I know above timings are fine at 1.45v with just 16-16-16 but I am trying to tighten that a bit..
> 
> EDIT: With 1.55v vDIMM scores are great, write is fine, latency is great, just has 1 error in TM5 1usmus I have to fix. It threw a single error #13 after 1h25m unfortunately. Not overheating, DIMM's at 42.1/41.9c active cooled so not temp related. Could I maybe just need 1-2 ticks more vDIMM or a small adjustment to drvstr's?
> 
> View attachment 2586776


Yea, you're gonna need to sit down and play with the cad bus; both the drive strengths and the setup shifts. Because you have more than one rank, play with CsODT as well (chipselect and ODT pins).

I've been playing around a little more recently and my system might be better with DrvStr 20-30-40-60 ; and setup 59-52-54. (I'm still unsure if touching the ClocK-Enable is does anything at all)

As a reminder, AddrCmdSetup of a tSetup bias (63->32) hates a high impedance ClkDrvStr; a high impedance ClkDrvStr hurts stability.

Raise tRDRD SD to 6; if this helps, messing with procODT might help.


----------



## Veii

dimkatsv said:


> If it was HARD cap, CPU should've throttled into oblivion just to fit under this value.


You are








Shutdown temp is higher, but after 65° you lose Freq_Straps. Rather F-Max lowers & maximum accepted V-Max (by FIT) lowers
Value is at the moment visible zero, but it still is in place
Grab ZenPTMonitor and check why you lose CCLK

It's only 5600X that was capped, and later it out of nowhere disappeared, yet still is enforced
5800X and every other SKU procHot cap at 95


----------



## dimkatsv

Veii said:


> You are
> 
> Shutdown temp is higher, but after 65° you lose Freq_Straps. Rather F-Max lowers & maximum accepted V-Max (by FIT) lowers


I literally showed you how hard throttle looks like and you are saying that ProcHot is a hard throttler. Yes it can affect frequency, but it isn't throttler in common sense.
If it was hard throttler, i would've been constantly hitting 65 degrees as i showed in screenshot applied at same post by setting HTC to 65 degrees.
In addition, as if CPU won't get it's frequency throttled while using MULTICORE SMT AVX2 load. AVX2 by itself causes multicore frequency throttle. For some people it even causes SINGLE core frequency throttle.
Fact that it allows me to grab 117W despite having arbitrary 65 degrees limit and STILL gain frequency with more wattage should show that ProcHOT doesn't works as you may have expected it to work.

I would agree that ProcHOT is soft throttler though.


----------



## Merciless_Rick

Netblock said:


> Yea, you're gonna need to sit down and play with the cad bus; both the drive strengths and the setup shifts. Because you have more than one rank, play with CsODT as well (chipselect and ODT pins).
> 
> I've been playing around a little more recently and my system might be better with DrvStr 20-30-40-60 ; and setup 59-52-54. (I'm still unsure if touching the ClocK-Enable is does anything at all)
> 
> As a reminder, AddrCmdSetup of a tSetup bias (63->32) hates a high impedance ClkDrvStr; a high impedance ClkDrvStr hurts stability.
> 
> Raise tRDRD SD to 6; if this helps, messing with procODT might help.


from what ive heard, if you are running 2T you dont need setup times...or they at least dont do anything for you and may even slow you down; and from what you suggest, if you are not using setup, then higher clkdrvstr should be fine
do setup times even do that much if you have tcke at 0 or 1???
for me, 30-60 ohm clkdrvstr has helped my latencies and perhaps even my dimm temps
what is clock enable???
also if running 2 dual rank, doesnt the system treat that as 2 dimm per channel?
but i'm curious to test your drvstr on my system...you are running dual rank?


----------



## Imprezzion

Netblock said:


> Yea, you're gonna need to sit down and play with the cad bus; both the drive strengths and the setup shifts. Because you have more than one rank, play with CsODT as well (chipselect and ODT pins).
> 
> I've been playing around a little more recently and my system might be better with DrvStr 20-30-40-60 ; and setup 59-52-54. (I'm still unsure if touching the ClocK-Enable is does anything at all)
> 
> As a reminder, AddrCmdSetup of a tSetup bias (63->32) hates a high impedance ClkDrvStr; a high impedance ClkDrvStr hurts stability.
> 
> Raise tRDRD SD to 6; if this helps, messing with procODT might help.


I have never used the setup timings on 2T before. Never had to lol. Only on 1T GDM Off I need 56 AddrCmdSetup to run on 3800C14. 

My CPU / IMC seems to absolutely hate low ProcODT. Even stable OC's like my 3933C16 profile cannot run under 43.6ohm at all even with many different ClkDrvStr combinations. My 5900X ran fine on 28.2 with minimal tweaking to the DrvStr's but this one really doesn't like it. On the other hand, 3933C16 1T GDM On on only 1.45v vDIMM and pretty low VDDP/VDDG and vSOC is rock solid with no WHEA's and has good power efficiency and DIMM temps so I might just stay there and tweak some secondary / tertiary timings and stick with that.


----------



## Taraquin

Artylol said:


> Is there a specific reason why below is stable
> View attachment 2586910
> 
> and if change timings to 3800 15-15-15-15-30-45 it does not boot? absolute timing for 3600x14 is 7.77ns,while 3800x15 is 7.9ns. It should be booting by laws of physics


Did you change any secondaries? RC 39 may be too low. I need 42 for very similar timings to work at 3800 and 1.47v dimm. Could be that 1t on 3800 needs other values or 3800\1900 has fclk hole. Do 1900fclk boot with all timings on auto? If it boots the change to 2t first to see if that works. If that works you may need to change Rtt-values, ProcODT and\or DrvStr.


----------



## dimkatsv

Imprezzion said:


> My CPU / IMC seems to absolutely hate low ProcODT. Even stable OC's like my 3933C16 profile cannot run under 43.6ohm at all even with many different ClkDrvStr combinations.


Oh, wow... I didn't expeced it to be that bad. Mine is very tolerant to ProcODT. But ClkDrvStr definitely have an effect on GDM=OFF 1T, as i only able to boot it with 60+ ohms


----------



## Worgened

Any help or opinion with this issue? guys thanks 


Worgened said:


> View attachment 2586838
> 
> 
> Hi guys İ did some tweak on rams but i have a problem. First stick of ram a2 tphyrdl is 26 and second is tphyrdl 28. Can you help me how can i do them same as tphyrdl 26. I have researched but not sure where to start. Thanks for your answer.


----------



## ManniX-ITA

Worgened said:


> Any help or opinion with this issue? guys thanks


Sorry I don't remember much about it.
Except the even tCL, I think the matter was trying with a bit higher VDDP, like 950mV, and different ProcODT.


----------



## Worgened

ManniX-ITA said:


> Sorry I don't remember much about it.
> Except the even tCL, I think the matter was trying with a bit higher VDDP, like 950mV, and different ProcODT.


Ty for answer i tried increa vddp voltage did not work also some different procODT but it is still same one dim 26 the other one 28.


----------



## The_King

Worgened said:


> View attachment 2586838
> 
> 
> Hi guys İ did some tweak on rams but i have a problem. First stick of ram a2 tphyrdl is 26 and second is tphyrdl 28. Can you help me how can i do them same as tphyrdl 26. I have researched but not sure where to start. Thanks for your answer.


Try these timings if they are the same like my Micron Rev.B it should work. Mines are C9BLJ IC's

Changing CL to 15 should change them to 26/26


----------



## Worgened

The_King said:


> Try these timings if they are the same like my Micron Rev.B it should work. Mines are C9BLJ IC's
> 
> Changing CL to 15 should change them to 26/26
> View attachment 2586931


Just to be sure. i should change all timing on that you shared pic or just tcl value to 15  and should i change voltage values too?


----------



## The_King

Worgened said:


> Just to be sure. i should change all timing on that you shared pic or just tcl value to 15  and should i change voltage values too?


It should but note I have GDM enabled CL16 for CL15 GDM has to be disabled like your setup. 
Not sure how my settings will behave with GDM disabled has I never test that. You may need more VDIMM than me.

First change CL to 15 on your current setup and see if it goes 26/26.


----------



## Worgened

The_King said:


> It should but note I have GDM enabled CL16 for CL15 GDM has to be disabled like your setup.
> Not sure how my settings will behave with GDM disabled has I never test that. You may need more VDIMM than me.
> 
> First change CL to 15 on your current setup and see if it goes 26/26.


Thank you so much. I cannot do it right now for some reason but i will reply you for result when i do it


----------



## The_King

Worgened said:


> Thank you so much. I cannot do it right now for some reason but i will reply you for result when i do it


If you have set RDWR manually to 8 that may cause CL15 to fail to post. Leave that at 9 or 10. Sometimes WRRD can be the issue.

CL 15 AND RDWR 8 dont play nice together in most cases.


----------



## Worgened

The_King said:


> If you have set RDWR manually to 8 that may cause CL15 to fail to post. Leave that at 9 or 10. Sometimes WRRD can be the issue.


Okey ty i think it was manuel. I will try it with 10 soon ty so much for your help


----------



## Netblock

Merciless_Rick said:


> from what ive heard, if you are running 2T you dont need setup times...or they at least dont do anything for you and may even slow you down; and from what you suggest, if you are not using setup, then higher clkdrvstr should be fine


The setup shifts still affect at 2T. It's just that 2T is absolutely massive compared to the setups; each tick of a Setup is worth 1/64'th of a clock cycle. Check out the BKDGs linked here.

An AddrCmdSetup with a tSetup bias (benefit the tSetup by hurting tHold) doesn't like a high drive strength on the clock pins. I have no idea why. But that's okay because a proper AddrCmd setup and strength very likely should be able to do 1T-off (when clkdrvstr is lowered).

AMD defines 2T command rate as "One additional MEMCLK of setup time is provided on all DRAM address and control signals (not including CS, CKE, and ODT)". If 2T helps, then messing with AddrCmdSetup will probably help get 1T; probably with a tSetup bias.



Merciless_Rick said:


> do setup times even do that much if you have tcke at 0 or 1???
> 
> what is clock enable???


tCKE is irrelevant if you don't use PowerDown or sleep the computer.
CKE is about the clock enable pin. It's registered high during normal operation, and gets registered low to make the DRAM enter a low-power mode. (powerdown and auto self refresh)




Merciless_Rick said:


> for me, 30-60 ohm clkdrvstr has helped my latencies and perhaps even my dimm temps


To make sure we're not talking past each other, all drive strengths and setups by themselves don't affect performance; what they do is affect signal stability on the respectful command-address bus pins. You then can use that increased signal stability to run a more performant config.




Merciless_Rick said:


> also if running 2 dual rank, doesnt the system treat that as 2 dimm per channel?


(Assuming AM4)
2 total DIMMs, where each DIMM is dual-rank? No; that's 1 DPC, 2 RPC. (ranks per channel).
4 total DIMMs where each DIMM is dual-rank? Yes; that's 2 DPC, 4 RPC.



Merciless_Rick said:


> but i'm curious to test your drvstr on my system...you are running dual rank?


I am running a tri-rank setup with Micron 8Gbit Rev.E. Four DIMMs, two dual-rank and two single-rank; with the order of SR-DR-SR-DR on a 3142-order daisychain topology (order does matter).


----------



## Veii

dimkatsv said:


> I literally showed you how hard throttle looks like and you are saying that ProcHot is a hard throttler. Yes it can affect frequency, but it isn't throttler in common sense.
> If it was hard throttler, i would've been constantly hitting 65 degrees as i showed in screenshot applied at same post by setting HTC to 65 degrees.
> 
> 
> dimkatsv said:
> 
> 
> 
> I would agree that ProcHOT is soft throttler though.
Click to expand...

There must be a misunderstanding
I'm sorry, not too familiar with English terminology

My thought is, it is a throttler
Which irrelevant of Workload (SSE/AVX/AVX2) and irrelevant of current VID cap - will have higher priority and limit back "potential possible FMAX" , like a throttler would do
It will happen at any point, and there is zero you can do ~ as it's a fused limit. THM is not reached & hwinfo will not report this.

I don't know how to call it else except "a hardcap", yet not an emergency toggle (full shutdown)
It's not very "soft" as the user can do zero about it.

Oh i should also state that we don't have workload frequency offsets on Zen. // we do have voltage & LLC offsets
Only now with Zen4 we got an allcore limit (per Core C-State FMAX)
And FIT can determine by CAC (EDC throttler) the loadtype, half-way predict
But to this date, AMD doesn't use multiplier throttles but determines load & limits by other factors.
Mostly limited by a powerbudget, or cores lack voltage (then take too much and get voltage capped), or a thermal limit

ProcHot is for every other SKU a Hardcap past THM's range for Precision Boost
Here it is the same "hardcap" but before even THM can reach it's advertised 95°.
Reason to implement, quite unknown. Still lacking that logical part, except "preserve stability".

EDIT:


Veii said:


> But to this date, AMD doesn't use multiplier throttles but determines load & limits by other factors.


Soo given that, if user does undervolt their sample enough - no voltage offset for X workload will throttle frequency
The only part that is left is thermal throttle ~ but on 5600X THM is not the main "soft throttler"
// but what should be past that, the procHot throttle ~ comes 30°c earlier

Thinking more about it
Maybe it was inserted by an early tCtl to tDie delta ?
But i can confidently say, that there is nothing you can do against it and it is a thing. A hardcap
If it wasn't for that thermal limit, i would hold my 4.85 on every workload


----------



## Taraquin

Damn, finally got 3800cl14 stable! I picked up a cheap pair of used 2x8 Flare X 3200cl14 and as long as they are kept below 41C I get no errors in TM5 








My Patriot Viper 4400cl19 was unable to get 14 flat stable even at 1.55v dimm (overheat then), no way they could do 14 flat at 1.51v.


----------



## Worgened

The_King said:


> If you have set RDWR manually to 8 that may cause CL15 to fail to post. Leave that at 9 or 10. Sometimes WRRD can be the issue.
> 
> CL 15 AND RDWR 8 dont play nice together in most cases.


Hi mate finally two sticks same a 26 but i needed to put 1.45 vdim voltage can you tell me what is safe voltage for daily gaming usage for micron b Die kits?


----------



## The_King

Worgened said:


> Hi mate finally two sticks same a 26 but i needed to put 1.45 vdim voltage can you tell me what is safe voltage for daily gaming usage for micron b Die kits?


I ran upto 1.5V without issues. 1.45V should be just fine daily. I run most of my RAM around 1.45V daily Micron and Samsung. Both are safe in my opinion.


----------



## Worgened

The_King said:


> I ran upto 1.5V without issues. 1.45V should be just fine daily. I run most of my RAM around 1.45V daily Micron and Samsung. Both are safe in my opinion.


Ty for your answer. I will try to reduce but if i can not. as you said it is safe 1.45v. Then dont need to worry about it


----------



## The_King

Taraquin said:


> Damn, finally got 3800cl14 stable! I picked up a cheap pair of used 2x8 Flare X 3200cl14 and as long as they are kept below 41C I get no errors in TM5
> View attachment 2586973
> 
> My Patriot Viper 4400cl19 was unable to get 14 flat stable even at 1.55v dimm (overheat then), no way they could do 14 flat at 1.51v.


Nice, don't feel bad my 4400 C19s can't do 3800 flat 14s either. lol
Have your tried RDWR 7 or WRRD 1?

Only issue is that 2 DIMM motherbord and 8GBX2 you loose out on DR gaming performance on ZEN 3.
Tried hard myself to source a decent 16GBx2 Samsung B-die kit. Very hard to come by here and still expensive.

In fact DDR5 32GB kits are now selling cheaper the Samsung B-die DDR4 32GB kits. Just crazy!

13K for DDR5 Kit





Kingston KF552C40BBK2-32 Desktop Ram FURY Beast Series 32GB (16GBx2) DDR5 5200MHz


Kingston KF552C40BBK2-32 Desktop Ram FURY Beast Series 32GB (16GBx2) DDR5 5200MHz | CL-40, 1.25V | 288-pin DIMM uses gold contact fingers | Dual Module Ram...




mdcomputers.in





23K for DDR4 Kit 








TeamGroup T-Force Xtreem ARGB 3200Mhz CL14 32GB DDR4 Ram


Buy TeamGroup T-Force Xtreem ARGB 3200Mhz CL14 32GB(2x16GB) DDR4 Ram (TF10D432G3200HC14BDC01) online at a very low price in India | PC4-25600U | Intel XMP 2.0




www.pcstudio.in







Worgened said:


> Ty for your answer. I will try to reduce but if i can not. as you said it is safe 1.45v. Then dont need to worry about it


Did you run TM5 to test stability?
Your kit may work with 1.4V. Just need to test it for stability.


----------



## Worgened

The_King said:


> Nice, don't feel bad my 4400 C19s can't do 3800 flat 14s either. lol
> Have your tried RDWR 7 or WRRD 1?
> 
> 
> Did you run TM5 to test stability?
> Your kit may work with 1.4V. Just need to test it for stability.


Yea i will test with 1.4 if it work it would be awesome ty for help again


----------



## Worgened

The_King said:


> Nice, don't feel bad my 4400 C19s can't do 3800 flat 14s either. lol
> Have your tried RDWR 7 or WRRD 1?
> 
> Only issue is that 2 DIMM motherbord and 8GBX2 you loose out on DR gaming performance on ZEN 3.
> Tried hard myself to source a decent 16GBx2 Samsung B-die kit. Very hard to come by here and still expensive.
> 
> In fact DDR5 32GB kits are now selling cheaper the Samsung B-die DDR4 32GB kits. Just crazy!
> 
> 13K for DDR5 Kit
> 
> 
> 
> 
> 
> Kingston KF552C40BBK2-32 Desktop Ram FURY Beast Series 32GB (16GBx2) DDR5 5200MHz
> 
> 
> Kingston KF552C40BBK2-32 Desktop Ram FURY Beast Series 32GB (16GBx2) DDR5 5200MHz | CL-40, 1.25V | 288-pin DIMM uses gold contact fingers | Dual Module Ram...
> 
> 
> 
> 
> mdcomputers.in
> 
> 
> 
> 
> 
> 23K for DDR4 Kit
> 
> 
> 
> 
> 
> 
> 
> 
> TeamGroup T-Force Xtreem ARGB 3200Mhz CL14 32GB DDR4 Ram
> 
> 
> Buy TeamGroup T-Force Xtreem ARGB 3200Mhz CL14 32GB(2x16GB) DDR4 Ram (TF10D432G3200HC14BDC01) online at a very low price in India | PC4-25600U | Intel XMP 2.0
> 
> 
> 
> 
> www.pcstudio.in
> 
> 
> 
> 
> 
> 
> Did you run TM5 to test stability?
> Your kit may work with 1.4V. Just need to test it for stability.


It dıd not even post with 1.4v mate only black screen on monitor. İf you say 1.45 daily gaming is safe for b die micron.
I dont wanna try anymore i wil use it with 1.45v Ty for all your help Trcdwr was 8 before now it is 18 now. If i do it as 8 pc does not post what do you think it is ok?


----------



## Taraquin

The_King said:


> Nice, don't feel bad my 4400 C19s can't do 3800 flat 14s either. lol
> Have your tried RDWR 7 or WRRD 1?
> 
> Only issue is that 2 DIMM motherbord and 8GBX2 you loose out on DR gaming performance on ZEN 3.
> Tried hard myself to source a decent 16GBx2 Samsung B-die kit. Very hard to come by here and still expensive.
> 
> In fact DDR5 32GB kits are now selling cheaper the Samsung B-die DDR4 32GB kits. Just crazy!
> 
> 13K for DDR5 Kit
> 
> 
> 
> 
> 
> Kingston KF552C40BBK2-32 Desktop Ram FURY Beast Series 32GB (16GBx2) DDR5 5200MHz
> 
> 
> Kingston KF552C40BBK2-32 Desktop Ram FURY Beast Series 32GB (16GBx2) DDR5 5200MHz | CL-40, 1.25V | 288-pin DIMM uses gold contact fingers | Dual Module Ram...
> 
> 
> 
> 
> mdcomputers.in
> 
> 
> 
> 
> 
> 23K for DDR4 Kit
> 
> 
> 
> 
> 
> 
> 
> 
> TeamGroup T-Force Xtreem ARGB 3200Mhz CL14 32GB DDR4 Ram
> 
> 
> Buy TeamGroup T-Force Xtreem ARGB 3200Mhz CL14 32GB(2x16GB) DDR4 Ram (TF10D432G3200HC14BDC01) online at a very low price in India | PC4-25600U | Intel XMP 2.0
> 
> 
> 
> 
> www.pcstudio.in
> 
> 
> 
> 
> 
> 
> Did you run TM5 to test stability?
> Your kit may work with 1.4V. Just need to test it for stability.


Will try RDWR 7/WRRD 1 next, just had to test my previous setup with flat 14. Will also try lower RFC.


----------



## The_King

Worgened said:


> It dıd not even post with 1.4v mate only black screen on monitor. İf you say 1.45 daily gaming is safe for b die micron.
> I dont wanna try anymore i wil use it with 1.45v Ty for all your help Trcdwr was 8 before now it is 18 now. If i do it as 8 pc does not post what do you think it is ok?
> View attachment 2586978


18 is probably safer to run. 

If you run AIDA64, test to see if you get better latency with TRAS 45 and RC 63.
If you find your get lower memory latency with that then use that if not what you have should be stable.

I did not test this for stability but got the lowest latency with higher TRAS and RC. So should not be hard to test or take much time.


----------



## Worgened

The_King said:


> Nice, don't feel bad my 4400 C19s can't do 3800 flat 14s either. lol





The_King said:


> 18 is probably safer to run.
> 
> If you run AIDA64, test to see if you get better latency with TRAS 45 and RC 63.
> If you find your get lower memory latency with that then use that if not what you have should be stable.
> 
> I did not test this for stability but got the lowest latency with higher TRAS and RC. So should not be hard to test or take much time.
> View attachment 2586980


Got bsod without error only says bugcheck what voltage should increase any advice please


----------



## The_King

Worgened said:


> Got bsod without error only says bugcheck what voltage should increase any advice please


Change TWR 16 RTP to 8. Voltages seem fine for the most part. Also maybe a good idea to change both SCLs to 4

This can happen if you don't test at least 25 cycles TM5 1usmus_V3 or anta777 for stability.

If you still get BSOD you may need to adjust *DrvStr which maybe be needed when GDM is disabled.
If the above does not stop the BSOD.

Try ClkDrvStr 40 and change addrCmdStr to 20 like i have in this pic below. Also run TM5 to avoid BSOD and other issues like data corruption.


----------



## dimkatsv

Veii said:


> If it wasn't for that thermal limit, i would hold my 4.85 on every workload


Well, i can enforce constant frequency as well. And if thermal conductivity was good enough, my frequencies would've been higher as well
I guess if ProcHot is 95, then boost behaviour will become more... aggressive? But i'm not sure on this one
With forcing constant frequency i can get over 95 degrees temps though. But as voltage for this is bit unacceptable for me, as well as heat output... No thanks
I think that if ProcHot worked like "target boost temp" behaviour caused by it would've be similar to how Ryzen 7000 behave. Either 95(65) degrees or PPT limit, depending on what will come first. 

It is just strange to have soft throttler at same level as hard throttler. 
Also. Just for my knowlege. you remove power limit completely on 5800X and higher, and run Prime95 small FFT, you will get 95 degrees easily?
Because my will stop at about 117W


----------



## The_King

dimkatsv said:


> Also. Just for my knowlege. you remove power limit completely on 5800X and higher, and run Prime95 small FFT, you will get 95 degrees easily?
> Because my will stop at about 117W


With y-cruncher I ran my 5800X up to 170W today. Times were not my best actually very bad, my best time is 93.6 but CPU took it like a champ peak 91C.
I am running a dual tower aircooler not sure what you are running for your cooling solution.









Oh i hit 97C peak here @ 173W.


----------



## dimkatsv

The_King said:


> I am running a dual tower aircooler not sure what you are running for your cooling solution.


ID-Cooling 226-XT as i mentioned before.I made it such tight fit on top of CCD, that it seems that i suffer from local pump-out effect. Which is not very good btw. I may need to look up for better interface.
Interstingly, that with 170/117W power consumption (1.45 multiplier) and with difference of 2 cores (8/6=1.33) you spend more watts to get to a bit lower frequency than i can get. It is close though. But efficiency seems to be less. Probably because of heat. So i won't accept point that with 30 degrees higher ProcHot CPU will get to higher frequency. Seems like it's not quite true
But point is. If you set your PPT to 190W will it just hard throttle because of HTC? Or it will attempt to take whole 190W despite going into overheating? You can check if you increase HTC a bit for one test.
Because ProcHot shouldn't engage at all as default HTC also equal to 95 degrees. And when you hit HTC it would be hard throttle anyways.

Seems like for me, soft throttler starts to engage more noticable after about 83-85 degrees. Otherwise pushing 125+W through 5600X would've been possible even for AVX2 loads. At cost of heat ofc.
But before this value. Better heat removal - higher frequency, despite there also being a way to push more watts

P.S. My best result was about 118.7 or 118.9. And this was just 20-th place. . . Well, on other hand understandable. My RAM isn't that great and it isn't even B-die
Here... Old screenshot. Old setup was indeed better to run these benchmarks. But i got good GPU result on W11 instead)
Also seems like i had even more frequency for less wattage


----------



## The_King

I did those runs just today for HWBOT CUP in R20 and just did the other tests for fun, won't be pushing my 5800X past 160W in the future unless I upgrade to an AIO.
In R23 my best was this with much less power 152W. Y-cruncher uses crazy high EDC when using -CO


----------



## Worgened

The_King said:


> 18 is probably safer to run.
> 
> If you run AIDA64, test to see if you get better latency with TRAS 45 and RC 63.
> If you find your get lower memory latency with that then use that if not what you have should be stable.
> 
> I did not test this for stability but got the lowest latency with higher TRAS and RC. So should not be hard to test or take much time.
> View attachment 2586980


It ıs not stable anyway i tried i just gave up. I use my first setting. Is there any other way than tcl 15 to make two stick 26 26 or if i dont get error on tm5mem test using 26 28 is ok what do you think. Also with first setting i got 55.3 ns on aida test in safe mode


----------



## 99belle99

Taraquin said:


> Damn, finally got 3800cl14 stable! I picked up a cheap pair of used 2x8 Flare X 3200cl14 and as long as they are kept below 41C I get no errors in TM5
> View attachment 2586973
> 
> My Patriot Viper 4400cl19 was unable to get 14 flat stable even at 1.55v dimm (overheat then), no way they could do 14 flat at 1.51v.


That is some highly binned B-Die. It must have been an early 3200MHz bin before they started binning b-die for higher frequency's as I have 3600MHz Cl16 b-die and tried your setting and it wouldn't even boot. But I kinda knew that as my 3600Mhz cl16 hasn't the best sub timings. My XMP tFAW has a lower bin than other 3600 cl16 kits.

This is the best I can do and I need steup 56.


----------



## Taraquin

99belle99 said:


> That is some highly binned B-Die. It must have been an early 3200MHz bin before they started binning b-die for higher frequency's as I have 3600MHz Cl16 b-die and tried your setting and it wouldn't even boot. But I kinda knew that as my 3600Mhz cl16 hasn't the best sub timings. My XMP tFAW has a lower bin than other 3600 cl16 kits.
> 
> This is the best I can do and I need steup 56.
> 
> View attachment 2587029


They are a june 2021 batch. Guess I just got licky, they perform quite a bit better than my Patriot 4400cl19.


----------



## Taraquin

Taraquin said:


> Will try RDWR 7/WRRD 1 next, just had to test my previous setup with flat 14. Will also try lower RFC.


RDWR 7/WRRD1 worked fine and is errorfree as long as temp on ram stays below 41C. In gaming highest I have achieved is 36C.


----------



## mikalcarbine

I picked up some crap bin B die from ebay for cheap and I'm trying to tune it at 3733. I don't think tCL 14 is going to work so I'm trying to get to flat 16 before attempting GDM off with flat 15 timings. tRCDRD has been giving me problems the whole time. I was running at 1.55v but I've backed down to 1.4v with no changes in stability at CL16. Memory is actively cooled via the dual fans on my NH-C14S and peaks around 42C. I haven't tightened up all of my sub timings yet but I figured this was a good start to attempt to lower my primary timings.










These timings are stable with tRCDRD at 17, once I bumped it down to 16 I start getting errors. Sometimes in test 6 as well. Any recommendations?


----------



## Imprezzion

mikalcarbine said:


> I picked up some crap bin B die from ebay for cheap and I'm trying to tune it at 3733. I don't think tCL 14 is going to work so I'm trying to get to flat 16 before attempting GDM off with flat 15 timings. tRCDRD has been giving me problems the whole time. I was running at 1.55v but I've backed down to 1.4v with no changes in stability at CL16. Memory is actively cooled via the dual fans on my NH-C14S and peaks around 42C. I haven't tightened up all of my sub timings yet but I figured this was a good start to attempt to lower my primary timings.
> 
> View attachment 2587040
> 
> 
> These timings are stable with tRCDRD at 17, once I bumped it down to 16 I start getting errors. Sometimes in test 6 as well. Any recommendations?


More voltage comes to mind. 1.4 might be on the low side for such a bad bin. Besides, tRAS is probably too low as well. I'd suggest 2T GDM Off, 16-16-16-36(tras)-52(tRC) and just to be safe set tRDWR to 9 and tWRRD to 5. Try 1.40 first on those timings and if it doesn't work go up to 1.45.


----------



## mikalcarbine

Imprezzion said:


> More voltage comes to mind. 1.4 might be on the low side for such a bad bin. Besides, tRAS is probably too low as well. I'd suggest 2T GDM Off, 16-16-16-36(tras)-52(tRC) and just to be safe set tRDWR to 9 and tWRRD to 5. Try 1.40 first on those timings and if it doesn't work go up to 1.45.


Thanks for the suggestions. Those timings at 1.4v threw 1 error in test 2, 6 and 10. At 1.45v I only received a single error in test 6 which is a good improvement. I'll try 1.47 to see if it helps at all.

The error guide says test 6 relates purely to IMC - procODT, VDDP or VSOC. What would you suggest tackling next? Is there an accepted process to figuring out what the best procODT values are? Mine are currently on auto.











Edit: 1.47v resulted in

2 errors test 13
1 error test 8
1 error test 11

Memory temps at 42C


----------



## Imprezzion

mikalcarbine said:


> Thanks for the suggestions. Those timings at 1.4v threw 1 error in test 2, 6 and 10. At 1.45v I only received a single error in test 6 which is a good improvement. I'll try 1.47 to see if it helps at all.
> 
> The error guide says test 6 relates purely to IMC - procODT, VDDP or VSOC. What would you suggest tackling next? Is there an accepted process to figuring out what the best procODT values are? Mine are currently on auto.
> 
> View attachment 2587044
> 
> 
> 
> Edit: 1.47v resulted in
> 
> 2 errors test 13
> 1 error test 8
> 1 error test 11
> 
> Memory temps at 42C


It's responding quite weirdly to voltage so far. Makes me think vDIMM isn't the problem nor solution here. ProcODT and RTT's and such is not my strong suit lol. I just run Auto as it simply works. 43.6 is my Auto ODT, same RTT's. 

Maybe try boosting the ClkDrvStr's slightly to all 24's on 1.45v? And raise tRFC a bit while you're at it. 320 would do. Is it b-die 100% or is it C-die maybe?


----------



## Luggage

Veii said:


> If it wasn't for that thermal limit, i would hold my 4.85 on every workload


You don’t get voltage capped?








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


It just needs more for higher FCLK. What matters is the total power budget and that's something you can't control. You can raise voltages to let it pump more but there's a breakeven point. After that, the performances will start to drop. Don't. Static OC needs different voltages and settings...




www.overclock.net


----------



## dimkatsv

Luggage said:


> You don’t get voltage capped?
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> It just needs more for higher FCLK. What matters is the total power budget and that's something you can't control. You can raise voltages to let it pump more but there's a breakeven point. After that, the performances will start to drop. Don't. Static OC needs different voltages and settings...
> 
> 
> 
> 
> www.overclock.net


Well, if there is no throttler to engage, current VID limit will not drop down, no matter situation.
That means that he will just overheat CPU instead.
Actually throttlers usually limit max requested VID instead of working on frequency. Then frequency adapts to current temp and available voltage.


----------



## Luggage

dimkatsv said:


> Well, if there is no throttler to engage, current VID limit will not drop down, no matter situation.
> That means that he will just overheat CPU instead.
> Actually throttlers usually limit max requested VID instead of working on frequency. Then frequency adapts to current temp and available voltage.


I’m sub 65C in all the tests (and 5800X…), with high or low PBO limits so that’s not the throttle.
Best result is not hitting edc fuse limit either.
Still can’t keep 4850…

So fit/cac? Should test again with tool/monitor instead of HWinfo64 probably… but now is warmer so have to wait for next cold nights


----------



## gvansly1

@Veii 
@Audioboxer 
@Taraquin 
@ManniX-ITA 

Need help from the experts.

5950x
Gigabyte X570S
BIOS F1

*All BIOS Settings = Default except DDR4 timings and voltages*

DDR4 3600C16 G.Skill 16GTZN BDie @ 3800

TestMem Extreme 1 @anta777 - 12 cycles, no errors or WHEA errors

TestMem Default @ 1usmus_V3 - 25 cycles, no errors or WHEA errors

Y-Cruncher N32, N64, HNT, VST, C17 42 iterations, ~ 7 hours, no errors, no WHEA errors

CPU stability: Y-Cruncher - All tests - 20 iterations no errors or WHEA errors

So, the question is: Why am I getting a random WHEA 19 error after a "Restart", waking up from sleep mode or after a cold boot?

It's not repeatable, sometimes it never happens, when it does it's usually occurring within 2 minutes of "up-time" and once I clear the error, I never get another one.

I have disabled all start up apps, HWiNFO64, and uninstalled GEFORCE Experience as possible suspects, but no luck. Should I even be worried about it? My OCD says yes, but what do you all suspect is causing this?

Huge thanks in advance for any insight and appreciate any suggestions/ideas.


----------



## dimkatsv

Luggage said:


> So fit/cac? Should test again with tool/monitor instead of HWinfo64 probably… but now is warmer so have to wait for next cold nights


You know... There is direct monitoring app for AMD CPU's. There you see everything that your CPU is limited by


----------



## Luggage

dimkatsv said:


> You know... There is direct monitoring app for AMD CPU's. There you see everything that your CPU is limited by


I meant Zenptmonitor…

Edit: found an old ss from last winter


http://imgur.com/iIa80pT


----------



## dimkatsv

Luggage said:


> I meant Zenptmonitor…
> 
> Edit: found an old ss from last winter
> 
> 
> http://imgur.com/iIa80pT


Well... Yes, basically. I have more generalized one with more data overall, but it works not as targeted and can misname or mismatch some values. Especially ones that linked to core-to-core variance.
It also refreshes less frequently and not very friendly to other monitoring tools (it begins to skip or corrupt readings if there is something else that gets them in queue).

That's what i have









And that's ZenPT values









Both under Prime95 Small FFT load with 110/76/125/4850/95/1 limits
As you can see. ProcHot doesn't even engage (in my tool, seems like prochot and voltage freq limiters are swapped btw. Good to know)
But i am actually limited by PPT, TDC and CCLK instead. Despite having limits higher than that.

Also i surprised that people have high FIT readings. Mine are usually in range of 0.7 -1.5. Maybe that's why PBO Scalar doesn't do anything for me . . .
Also. Really wanna mention. In ZenPT i don't even see ProcHot with value 65. Maybe anther mislable and it was related to default CPU PPT? Then it would make sense. 5600X is 65W CPU

P.S. Ah, about FIT, i see... Under low load when transient (?) hits (like i alt-tab), when i am on 4650, i will get low readings. But if i set 4850, i will get spikes up to 25.
Still well under FIT limit, but that's something. Yeah, confirmed, single thread load cause much higher FIT rate. But if i return to 4650, all is low and juicy again
Actually interesting question. Is it even worth doing PBO overdrive? Because there is not so many types of loads that can actually benefit from it, isn't it?


----------



## Netblock

gvansly1 said:


> So, the question is: Why am I getting a random WHEA 19 error after a "Restart", waking up from sleep mode or after a cold boot?


I solved this once, but l don't remember what I did. I was chasing this on my Matisse last night, and I might have solve it. It's probably either the CCD voltage (I raised it), or is related to PCIe stuff in the CBS menus (I enabled everything; PCIe AER, SRIS, ACS, ARI enable, ARI enumeration, LCLK DPM to 600MHz only).


----------



## Artylol

Is there a review/test to describe DIMM temperature vs speed/timings? My patriots don't have a temperature sensor unfortunately. I can easily boot 4000flat16 very stable, while 3666flat14 and higher get temperature errors (presumably)


----------



## dimkatsv

Artylol said:


> Is there a review/test to describe DIMM temperature vs speed/timings? My patriots don't have a temperature sensor unfortunately. I can easily boot 4000flat16 very stable, while 3666flat14 and higher get temperature errors (presumably)


It's impossible
Different DIMMS have different chip manufacturers, different chip types, different chip quality, different heat spreaders and different thermal pad quality
Then in addition different configs they can be used it, with bunch of frequencies, voltages, timings. And sometimes temps would be different just because system cannot take from DIMM everything
(like i cannot pass 55 GB/s speed on read, even though with B-die or different config it would've been possible to hit 57)
Then there are also individual timing differences.
And then there is also different airflow, case and ambient temps for every person

RAM heats when it transfers data. Basically it is directly proportional to data amount transferred and voltage DIMM works on. In no way 3666 should heat more than 4000, unless 4000 have lower voltage and terrible timings.


----------



## Netblock

dimkatsv said:


> In no way 3666 should heat more than 4000, unless 4000 have lower voltage and terrible timings


Semiconductors are interesting and there's far more it than just the frequency that affects its impedance against ohm's law. It is entirely possible for a 4000MT/s DDR4 to consume less power than even a 2133 MT/s at the same voltages and timings for a duration in nanoseconds.

For example, temperature affects leakage; tREFI being temperature-dependant by definition is about compensating for semiconductor current leakage.


----------



## dimkatsv

Netblock said:


> For example, temperature affects leakage; tREFI being temperature-dependant by definition is about compensating for semiconductor current leakage.


I guess. But still most heat comes from chip architecture and data transfer speed... If there are momentary times when it consumes low power, it doesn't mean that stick consumes less power overall. 
Like, you can transfer 3 Gb/s on 4000 CL 16 stick, and 23 Gb/s on 3200 CL 16 stick. And in this case 3200 stick will heat more, because it transfer and amplify more data than 4000 one.
So... I just assumed max load for both.
Btw that's why GDDR6X sometimes heats more than GDDR6 despite requiring less power for data transfer. It just transmits more data.


----------



## The_King

Worgened said:


> It ıs not stable anyway i tried i just gave up. I use my first setting. Is there any other way than tcl 15 to make two stick 26 26 or if i dont get error on tm5mem test using 26 28 is ok what do you think. Also with first setting i got 55.3 ns on aida test in safe mode


Please do me a favor and run Thaiphoon burner and post a screenshot of what ICs you have.


Thaiphoon Burner - Official Support Website











It is possible the Speed grade of your DIMMS are different from mines.

If you run 25 cycles with TM5 and pass then you should be fine even if its 26/28. If you running CL16 maybe a good idea just to keep GDM enabled for better stability.

If your DIMM is a lower speed grade / bin then you would need 3800 CL16-19-19-19 to be stable or 3800 CL15-19-19-19. Older binns may even need 3800 CL16-20-20-20.

You can also try changing to 2T that may make it 26/26 or 28/28.


----------



## ManniX-ITA

gvansly1 said:


> So, the question is: Why am I getting a random WHEA 19 error after a "Restart", waking up from sleep mode or after a cold boot?
> 
> It's not repeatable, sometimes it never happens, when it does it's usually occurring within 2 minutes of "up-time" and once I clear the error, I never get another one.
> 
> I have disabled all start up apps, HWiNFO64, and uninstalled GEFORCE Experience as possible suspects, but no luck. Should I even be worried about it? My OCD says yes, but what do you all suspect is causing this?
> 
> Huge thanks in advance for any insight and appreciate any suggestions/ideas.


As said it could be you need fine-tuning of the CCD voltage.
But being only one and so regular and only after a warm or cold restart it's more likely one core, not necessarily the one in the WHEA, that is unstable.
If you are at a stock settings, can be one of your cores needs a positive CO offset.
Usually it happens more frequently after a wake up form sleep that after a cold or warm boot, worst scenario for the CPU.


----------



## The_King

dimkatsv said:


> ID-Cooling 226-XT as i mentioned before.I made it such tight fit on top of CCD, that it seems that i suffer from local pump-out effect. Which is not very good btw. I may need to look up for better interface.
> Interstingly, that with 170/117W power consumption (1.45 multiplier) and with difference of 2 cores (8/6=1.33) you spend more watts to get to a bit lower frequency than i can get. It is close though. But efficiency seems to be less. Probably because of heat. So i won't accept point that with 30 degrees higher ProcHot CPU will get to higher frequency. Seems like it's not quite true
> But point is. If you set your PPT to 190W will it just hard throttle because of HTC? Or it will attempt to take whole 190W despite going into overheating? You can check if you increase HTC a bit for one test.
> Because ProcHot shouldn't engage at all as default HTC also equal to 95 degrees. And when you hit HTC it would be hard throttle anyways.
> 
> Seems like for me, soft throttler starts to engage more noticable after about 83-85 degrees. Otherwise pushing 125+W through 5600X would've been possible even for AVX2 loads. At cost of heat ofc.
> But before this value. Better heat removal - higher frequency, despite there also being a way to push more watts
> 
> P.S. My best result was about 118.7 or 118.9. And this was just 20-th place. . . Well, on other hand understandable. My RAM isn't that great and it isn't even B-die
> Here... Old screenshot. Old setup was indeed better to run these benchmarks. But i got good GPU result on W11 instead)
> Also seems like i had even more frequency for less wattage


Hard to compare two different CPU like this. Depending on PBO settings you can put out lots of power and obtain bad results or performance.
If I limit PPT on 5800X to 65W and run R23 I score over 13K you not going to get close to that score with a 5600X limited to 65W.

So this means a 5800X with its power limited to 65W can and obtain better performance and efficiency at much lower temps vs a 5600X.


----------



## Taraquin

One thing that puzzles me is that my aida latency is 53.9-54.0ns now at flat 14, RFC 256 and RDWR 7/WRRD 1. I got 53.7-53.9ns using flat 15, RFC 264 and RDWR 8/WRRD 2. Ryzen dram calc still gets 99sec to finish. Any idea why performance slightly regresses from tighter timings?


----------



## Taraquin

gvansly1 said:


> @Veii
> @Audioboxer
> @Taraquin
> @ManniX-ITA
> 
> Need help from the experts.
> 
> 5950x
> Gigabyte X570S
> BIOS F1
> 
> *All BIOS Settings = Default except DDR4 timings and voltages*
> 
> DDR4 3600C16 G.Skill 16GTZN BDie @ 3800
> 
> TestMem Extreme 1 @anta777 - 12 cycles, no errors or WHEA errors
> 
> TestMem Default @ 1usmus_V3 - 25 cycles, no errors or WHEA errors
> 
> Y-Cruncher N32, N64, HNT, VST, C17 42 iterations, ~ 7 hours, no errors, no WHEA errors
> 
> CPU stability: Y-Cruncher - All tests - 20 iterations no errors or WHEA errors
> 
> So, the question is: Why am I getting a random WHEA 19 error after a "Restart", waking up from sleep mode or after a cold boot?
> 
> It's not repeatable, sometimes it never happens, when it does it's usually occurring within 2 minutes of "up-time" and once I clear the error, I never get another one.
> 
> I have disabled all start up apps, HWiNFO64, and uninstalled GEFORCE Experience as possible suspects, but no luck. Should I even be worried about it? My OCD says yes, but what do you all suspect is causing this?
> 
> Huge thanks in advance for any insight and appreciate any suggestions/ideas.
> 
> 
> View attachment 2587060


I wouldn't bother with rare WHEA19 aslong as they don't clog the system, cause instability etc


----------



## Veii

dimkatsv said:


> With forcing constant frequency


Forcing ?



dimkatsv said:


> But point is. If you set your PPT to 190W will it just hard throttle because of HTC? Or it will attempt to take whole 190W despite going into overheating?


It is limited on EDC, by AGESA
But hardcapped by thermals first

It will take the 120-130, till 90A EDC limit is hit
But if it hits procHot limit before ~ it will throtttle frequency before it can hit any power limit
On older AGESA there was no powerdraw limit and it was more simply a voltage draw limit.
Yes it will draw as much as it likes till hits VMAX or procHot-max


dimkatsv said:


> You can check if you increase HTC a bit for one test.
> Because ProcHot shouldn't engage at all as default HTC also equal to 95 degrees. And when you hit HTC it would be hard throttle anyways.


HTC or likely THM, is defaulting at 95° for PBO , well also in general
Here also fixed frequency shares the same limit of 95° but bypasss procHot of 65°

For you, it will draw first till it hits voltage VMAX and equally EDC limit
Then with lowered enough VID , it will draw till it hits thermal limits of 95°.
Or more likely again, track SVI2 supply limits of (up to AGESA ~1.4 to 1.425v) // in latest AGESA 1.3725v ... well really SKU dependent

In all cases VMAX goes in hand with EDC limit, were only TDC & PPT can be open.
Extending EDC limit higher than AGESA's confirmed, changes VMAX range and lowers it (intentionally forced)

But for 5600X, everything looks a bit different because procHot is far to low set.
I can see thermal instability on near 70° vs 5800X onwards.
But we still share the same substrate, soo "it's just a sideeffect"
People hit 65° in games , mostly - unless running a little 120mm AIO.
Just sadly also "people" don't understand CO much, soo most i've seen just hit VMAX and don't get it.
// probably because throttle VMAX is ~50mV lower than FIT written VMAX ~~ with a 1.45v VID request range, it hardthrottles at 1.4v onwards. That is before it even reaches EDC Load-caps


dimkatsv said:


> It is just strange to have soft throttler at same level as hard throttler.
> Also. Just for my knowlege. you remove power limit completely on 5800X and higher, and run Prime95 small FFT, you will get 95 degrees easily?
> Because my will stop at about 117W


It is hard for me to say, because there are two voltage limiters ~ and not really spoofable by telemetry changes.
Mostly only the first is indicated and secondary tracking is too slow ~ while chip does Frequency & VID Gate. 
You will have Voltage spikes, that can not be tracked by normal SMU method. Well actually always it's the case of "tracked wrong" not "behaved odd".
It very likely throttles by Voltage supply first, before it hits Substrate strain wall (EDC) , before then it hits powerlimit (for everything that's not a 5600X)


----------



## dimkatsv

The_King said:


> If I limit PPT on 5800X to 65W and run R23 I score over 13K you not going to get close to that score with a 5600X limited to 65W.
> 
> So this means a 5800X with its power limited to 65W can and obtain better performance and efficiency at much lower temps vs a 5600X.


Sure. With more cores, it is easier to get higher performance with lower power consumption (well, up till some point of course). 
5600X is 6 cores vs 8 cores on 5800X. I will get penalized just by raw thread amount. Even if my frequency will be higher
CB won't take more than 100W or so anyways. So i cannot just pump out infinite amount of wattage there too. Even if i wanted too. It even doesn't run that hot. As well as doesn't achieve too high of a frequencies. But still...
Like i can use 2 presets. One is 4650 (default) with CO -30 ALL. [Maybe i can up it to 4700, but definitely not 4725+]. Or 4850 with CO = -18 -15 -15 -24 -18 -30. 
But in multicore load they are actually kinda same. Because if it is multicore load, it is rarely light enough to get me to more than 4650 mHz (actually CPU-Z could get 4725 once, but that's all basically... Ah, and y-cruncher FFT stress is light on CPU AF). 
And funniest (and saddest) part, is that my top cores are 1 and 2. . . While 0 and 5 are my slowest (5 is the slowest, then close up 0). And Windows f*cking LOVES to push EVERYTHING on core 0.
Which cannot usually go above 4775 (effective). Except for fractions of seconds on REALLY light loads. 
So i am as in between hammer and anwil. Is 4850 preset even worth time i spent (and i spent PLENTY of time) for daily? Surely i do have both preset as .bat files and can switch them in few seconds. But point still "is it worth"?
Funniest part. Is that i know that PBO setup can affect memory stability. But it mostly should work in one side. So as i have it all stable with heavy PBO setup, it shouldn't break if i set weak setup... Right? ... Right?


----------



## Veii

Luggage said:


> You don’t get voltage capped?
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> It just needs more for higher FCLK. What matters is the total power budget and that's something you can't control. You can raise voltages to let it pump more but there's a breakeven point. After that, the performances will start to drop. Don't. Static OC needs different voltages and settings...
> 
> 
> 
> 
> www.overclock.net


Still do, but it's barely managable.
On allcore load, no ~ CO range is just enough 


dimkatsv said:


> Actually throttlers usually limit max requested VID instead of working on frequency. Then frequency adapts to current temp and available voltage.


Correct
But if throttlers are far away, CPU will first hit procHot - as THM is also far away 


Luggage said:


> I’m sub 65C in all the tests (and 5800X…), with high or low PBO limits so that’s not the throttle.
> Best result is not hitting edc fuse limit either.
> Still can’t keep 4850…
> 
> So fit/cac? Should test again with tool/monitor instead of HWinfo64 probably… but now is warmer so have to wait for next cold nights


There must be still a voltage cap reason, as it can not be anything else
Unless you extended EDC limits higher than stock on AGESA past 1.2.0.3X
There then you also capped max-VID requests lower and so also max supply voltage limit lower.
==========================================================
This is what could've been , if AMD would allow us a slightly bit more range
Instead of capping VID requests, and not trusting on their own VMAX limiters, which are still hit and everything works up to spec
// maybe fear of PBO VID Req scaling to inf, but still misstrusting their Firmware engineers team having the power and voltage caps in place








@Eder , can you inv me to your Discord. I have some DXE signing and replacement questions.
Understand how to extend FMAX now, but can not pass on-boot signature check.

@PJVol here you can see ITX-Extreme4 Zombify.)
Gigabyte and Biostar bioses were less stable. This here even has fullrange L3 speedup, it's actually usable as daily.
Now if i could have newer UEFITool, or alternative methods of swapping DXE ~ it will be possible for other boards.








Only Fan headers and Board temp-sensors are missplaced, yet functional
12v,3v sensorics don't work too & lack of Switching freq access. // i should be able to fix this, if i learn to not break signature
Buut VDD1P8 exists and I just depend on Dr.Mos to auto-adjust. LLC also still works


----------



## The_King

Taraquin said:


> One thing that puzzles me is that my aida latency is 53.9-54.0ns now at flat 14, RFC 256 and RDWR 7/WRRD 1. I got 53.7-53.9ns using flat 15, RFC 264 and RDWR 8/WRRD 2. Ryzen dram calc still gets 99sec to finish. Any idea why performance slightly regresses from tighter timings?


I would try adjusting VDDG CCD and IOD slightly up or down and see if there is any change in Latency.
Sometimes too low values even on CLDO VDDP can affect performance.



dimkatsv said:


> Sure. With more cores, it is easier to get higher performance with lower power consumption (well, up till some point of course).
> 5600X is 6 cores vs 8 cores on 5800X. I will get penalized just by raw thread amount. Even if my frequency will be higher
> CB won't take more than 100W or so anyways. So i cannot just pump out infinite amount of wattage there too. Even if i wanted too. It even doesn't run that hot. As well as doesn't achieve too high of a frequencies. But still...
> Like i can use 2 presets. One is 4650 (default) with CO -30 ALL. [Maybe i can up it to 4700, but definitely not 4725+]. Or 4850 with CO = -18 -15 -15 -24 -18 -30.
> But in multicore load they are actually kinda same. Because if it is multicore load, it is rarely light enough to get me to more than 4650 mHz (actually CPU-Z could get 4725 once, but that's all basically... Ah, and y-cruncher FFT stress is light on CPU AF).
> And funniest (and saddest) part, is that my top cores are 1 and 2. . . While 0 and 5 are my slowest (5 is the slowest, then close up 0). And Windows f*cking LOVES to push EVERYTHING on core 0.
> Which cannot usually go above 4775 (effective). Except for fractions of seconds on REALLY light loads.
> So i am as in between hammer and anwil. Is 4850 preset even worth time i spent (and i spent PLENTY of time) for daily? Surely i do have both preset as .bat files and can switch them in few seconds. But point still "is it worth"?
> Funniest part. Is that i know that PBO setup can affect memory stability. But it mostly should work in one side. So as i have it all stable with heavy PBO setup, it shouldn't break if i set weak setup... Right? ... Right?


I have a dual CCD 5600X that was cut down from a 5950X. VRM-B2
















This boost to 5025Mhz without much issue. So also bin can vary if you have something like this then your 5600X bin should be better than others.


----------



## dimkatsv

Veii said:


> Forcing ?


Sure. Noone had forbidden users from applying fixed overclock. With fixed frequency and voltage.
That's what ... how it was CTR? Tool before Hydra came out? Anyways, that's how that tool regulated profiles.



Veii said:


> It is limited on EDC, by AGESA
> But hardcapped by thermals first


EDC limit can be lifted. Mine is 125, even though default is 90. on higher end CPU it can probably go even higher?
So i talked about theoretical situation with PPT/EDC/TDC limits set beyond reach and HTC set to about 100 degrees. ProcHot won't stop CPU from reaching 100 degrees.
But VID Limit yeah, that's one tricky bit...



Veii said:


> Unless you extended EDC limits higher than stock on AGESA past 1.2.0.3X


You do know you can avoid so called EDC bug. (Yes it works even for me from 1.45 to 1.375, even if it isn't noticable in practice. Unless i actually look into reporter)
Just set EDC from booted system, not in BIOS. Then EDC bug won't apply. Baseline VID limit can be only set up during boot sequence.


Veii said:


> Extending EDC limit higher than AGESA's confirmed, changes VMAX range and lowers it (intentionally forced)


As i said additional limitation can be avoided. BUT! There is another thing. Actual VID limit can change depending on load. Depending on PPT, EDC, TEMP and FIT settings. Probably there is something else, like V/F curve limits. And it changes REALLY fast.
Actually there is intersting stuff. Seems like FIT limit isn't constant, and randomly jumps down by A LOT (like 1617 nominal and up to 480 in lowest point, but usually around 650). And everything actually measures from lower FIT value, and not higher. It isn't as big of a factor when FIT limit is more than x1 though
Like here.









So i either get limited by voltage on this thread, or by FIT. Increasing scalar will allow higher voltage (0.025 higher, yeah). But overall gain will be still almost nothing.

Again, additional stuff. In low load state EDC constantly cycles as if it is sinusoid curve. When EDC becomes high, FIT comes down. At least this is tendency i noticed.
Lowering EDC can increase lower limit of FIT to be bit higher. Theoreticaly. In practice it will just be more consistently higher.
Decreasing max frequency will DRASTICALLY decrease current FIT status. Going from 650 at 4800 to 0.5 at 4650.
Granted it is mostly applied to single core loads. Well, technically these are only ones that actually get benefit from clock overdrive anyways. Multicore tasks will not have as much current FIT, but they are limited by other regulators


----------



## Veii

@dimkatsv You can actually use a scalar higher than x10 , and increase FIT limit more // shamino tool should have it
But i think too, its too adaptive. Its indeed funny that yours is low - rather that ours is so high.
Some fab CPUs are just odd. 

The best indication (for me) that a limiter is hit, is the lowering of Latchup, well VMAX
If no limiter is hit, VMAX stays at its highest point and if you still lower frequency cap ~ then it's mostly a thermal limiter

ProcHot is zero'd i notice, but it was there.
Its not readable yet still applies.
Would be funny if they changed 5800X down too now, but i dont think - as i've seen this CPU even draw 180W+ before
It was able to bypass its power limits and continue upscaling till it hit thermal limit. Maybe they mitigated it now 

It need was a "gaming" CPU and the only one that booted as high as thermals allow.
Now non does it, and only Zen4 behaves that way. Although that was on launch, now Zen4 is also frequency capped after all reviews were out.
At least only allcore load capped, but doesn't boost till it hits 95°. This "feature" was a launch bios one))


----------



## The_King

@Veii which Shamino tool? Please send link if you can. Thanks.
I have an issue getting over 5000Mhz stable boost on my 5800X in fact higher than 4975 seems unstable.

Will increasing FIT scalar over 10 help here?


----------



## Taraquin

The_King said:


> I would try adjusting VDDG CCD and IOD slightly up or down and see if there is any change in Latency.
> Sometimes too low values even on CLDO VDDP can affect performance.
> 
> 
> I have a dual CCD 5600X that was cut down from a 5950X. VRM-B2
> View attachment 2587100
> View attachment 2587103
> 
> 
> This boost to 5025Mhz without much issue. So also bin can vary if you have something like this then your 5600X bin should be better than others.
> View attachment 2587101


Yeah, may be that, will try later


----------



## dimkatsv

Veii said:


> @dimkatsv You can actually use a scalar higher than x10 , and increase FIT limit more // shamino tool should have it


Nah, it will force it down to 10. But i can set it to 0 instead. And FIT limit will actually become 0. Which, i assume, means it will be completely removed? 



Veii said:


> But i think too, its too adaptive. Its indeed funny that yours is low - rather that ours is so high.
> Some fab CPUs are just odd.


I guess. Hard to tell with certainty. 
Yeah, my CPU have own oddities. It is pretty good undervolter. But far from being that good of an overclocker sample.
It also, for some reason, just won't crash my PC. EVER. I can get errors in precision tests, like Prime95 per core (Actually on SSE specifically, AVX runs better for me). or Y-Cruncher. But i hadn't got actual crash. Even with 4850 CO -30 ALL (even though curves are missing by about 12-15 points, which is about 0.06-0.09V)
With shifting curves errors will become more rare and bit erratic. Up to point if i don't find them in 10-15 minutes of focused test, they won't appear in at least hour or several... If not forever. And testing becomes nightmare. (i have really narrow window of FFT values to test, which consistently cause crash from imprecise CO value)
My Core 5 have absolutely overboard limit. So it always runs at -30 and STILL often slows down all other cores to it's own state. Because of voltage limit.
My Core 2 is basically one that is hottest and less responsive to undervolt. So sometimes, when i am lazy, i just run test on core 2, and if it passes, then i know that everything else will pass at same value


----------



## dimkatsv

The_King said:


> @Veii which Shamino tool? Please send link if you can. Thanks.


Download CoreCycler. There is PBO2Tool in Debug folder of program.



The_King said:


> I have an issue getting over 5000Mhz stable boost on my 5800X in fact higher than 4975 seems unstable.
> 
> Will increasing FIT scalar over 10 help here?


I am not sure if i should be little envy, that 5800X can get to 5000 mHz. Or not because i know that i will hit voltage limit FAR before i will actually be able to force my CPU to run any core at this frequency.
FIT scalar can only help, if there is absolutely no other sources of throttle except FIT. Which happens quite rarely. Usually in something like CPU-Z bench, which is light on load, but intensive on EDC and FIT with high enough frequency.
Ah yeah, you also must have voltage headroom before hitting base VID limit (if it doesn't throttle)


----------



## Veii

The_King said:


> @Veii which Shamino tool? Please send link if you can. Thanks.
> I have an issue getting over 5000Mhz stable boost on my 5800X in fact higher than 4975 seems unstable.
> 
> Will increasing FIT scalar over 10 help here?


FIT scalar before could be up to 99 (hex changes)
but i didn't see scalar doing anything other than adding voltage and holding voltage longer
Soo over x6 i rarely ever used it, independent if AMD advertises "recommended x10"

On 12/16 cores supposedly it makes a difference on allcore loads, but i'm not sure

Shamino, Asus Tool
The one Dimkatsv, uses
ASUS Board Exclusive


----------



## The_King

dimkatsv said:


> Download CoreCycler. There is PBO2Tool in Debug folder of program.


I have that already it is what I used in my R23 screenshots it cant go over FIT Scalar 10.











dimkatsv said:


> I am not sure if i should be little envy, that 5800X can get to 5000 mHz. Or not because i know that i will hit voltage limit FAR before i will actually be able to force my CPU to run any core at this frequency.
> FIT scalar can only help, if there is absolutely no other sources of throttle except FIT. Which happens quite rarely. Usually in something like CPU-Z bench, which is light on load, but intensive on EDC and FIT with high enough frequency.
> Ah yeah, you also must have voltage headroom before hitting base VID limit (if it doesn't throttle)


I have seen many 5800X go over 5000 even 5050Mhz with PBO overide +200Mhz.

I have a specific issue with core 2 which is also the best core according to CPCC rating it crashes when it boost over 5000Mhz


----------



## dimkatsv

The_King said:


> I have seen many quiet a few 5800X go over 5000 even 5050 with PBO overide +200Mhz


Well... They are binned after all. Good for them
That's why 5600X have 4650 default, so no way to go over 4850 anyways). Not that it would help anyways.

Ngl, kinda want 5800X3D. But feel like it isn't worth to spend money for it at this point
I know it is good, especially at games that i often play. But money. . . It is quite a lot more expensive in my country. (about 800 USD? Yeah, our top-tier tech prices are through the roof currently)

I also must figure out what to do with CCD pumping out thermal paste from between IHS and cooler cold plate. It leaves cool trace, but hinders frequency by decent amount. And it happens fast after me reapplying paste again.


----------



## The_King

dimkatsv said:


> Well... They are binned after all. Good for them
> That's why 5600X have 4650 default, so no way to go over 4850 anyways). Not that it would help anyways.
> 
> Ngl, kinda want 5800X3D. But feel like it isn't worth to spend money for it at this point
> I know it is good, especially at games that i often play. But money. . .
> 
> I also must figure out what to do with CCD pumping out thermal paste from between IHS and cooler cold plate. It leaves cool trace, but hinders frequency by decent amount. And it happens fast after me reapplying paste again.


You can get over 4850Mhz with your 5600X using Hydra hybrid OC.


----------



## Luggage

Veii said:


> Still do, but it's barely managable.
> On allcore load, no ~ CO range is just enough
> 
> Correct
> But if throttlers are far away, CPU will first hit procHot - as THM is also far away
> 
> There must be still a voltage cap reason, as it can not be anything else
> Unless you extended EDC limits higher than stock on AGESA past 1.2.0.3X
> There then you also capped max-VID requests lower and so also max supply voltage limit lower.
> ==========================================================
> This is what could've been , if AMD would allow us a slightly bit more range
> Instead of capping VID requests, and not trusting on their own VMAX limiters, which are still hit and everything works up to spec
> // maybe fear of PBO VID Req scaling to inf, but still misstrusting their Firmware engineers team having the power and voltage caps in place
> View attachment 2587095
> 
> @Eder , can you inv me to your Discord. I have some DXE signing and replacement questions.
> Understand how to extend FMAX now, but can not pass on-boot signature check.
> 
> @PJVol here you can see ITX-Extreme4 Zombify.)
> Gigabyte and Biostar bioses were less stable. This here even has fullrange L3 speedup, it's actually usable as daily.
> Now if i could have newer UEFITool, or alternative methods of swapping DXE ~ it will be possible for other boards.
> 
> 
> 
> 
> 
> 
> 
> 
> Only Fan headers and Board temp-sensors are missplaced, yet functional
> 12v,3v sensorics don't work too & lack of Switching freq access. // i should be able to fix this, if i learn to not break signature
> Buut VDD1P8 exists and I just depend on Dr.Mos to auto-adjust. LLC also still works


No, I have no reason to go later than 1203c.

With 1190 I can find “true” max boost of cores? (With 1200 all hit 5050 if cold enough ~15C water…)


http://imgur.com/GM18HmZ

But performance is so so, not spending much time on it.


----------



## dimkatsv

The_King said:


> You can get over 4850Mhz with your 5600X using Hydra hybrid OC.


Yeah, yeah. Manual OC is a thing. Hydra just allows it to not break your stuff when you try run something heavy enough.
But i still won't be able to make it work. Not enough voltage to run 5000. I won't force my CPU to take more than 1.45


----------



## Veii

Luggage said:


> No, I have no reason to go later than 1203c.
> 
> With 1190 I can find “true” max boost of cores? (With 1200 all hit 5050 if cold enough ~15C water…)
> 
> 
> http://imgur.com/GM18HmZ
> 
> But performance is so so, not spending much time on it.


Can you export me your +500 FMAX bios too , for learning purposes

SMU 56.39 seems to be 1.1.8.X AGESA
56.40 = 1.1.9.X // but has higher cache throughput
but 56.43 is still pre 1.2.0.0 ? hmm

Have you ever tried flashrom on your board , on this bios ?
Generally are you free for 30min ?


----------



## Luggage

Veii said:


> Can you export me your +500 FMAX bios too , for learning purposes
> 
> SMU 56.39 seems to be 1.1.8.X AGESA
> 56.40 = 1.1.9.X // but has higher cache throughput
> but 56.43 is still pre 1.2.0.0 ? hmm
> 
> Have you ever tried flashrom on your board , on this bios ?
> Generally are you free for 30min ?


Not generally 
I’ll link you bios tonight.


----------



## Audioboxer

gvansly1 said:


> @Veii
> @Audioboxer
> @Taraquin
> @ManniX-ITA
> 
> Need help from the experts.
> 
> 5950x
> Gigabyte X570S
> BIOS F1
> 
> *All BIOS Settings = Default except DDR4 timings and voltages*
> 
> DDR4 3600C16 G.Skill 16GTZN BDie @ 3800
> 
> TestMem Extreme 1 @anta777 - 12 cycles, no errors or WHEA errors
> 
> TestMem Default @ 1usmus_V3 - 25 cycles, no errors or WHEA errors
> 
> Y-Cruncher N32, N64, HNT, VST, C17 42 iterations, ~ 7 hours, no errors, no WHEA errors
> 
> CPU stability: Y-Cruncher - All tests - 20 iterations no errors or WHEA errors
> 
> So, the question is: Why am I getting a random WHEA 19 error after a "Restart", waking up from sleep mode or after a cold boot?
> 
> It's not repeatable, sometimes it never happens, when it does it's usually occurring within 2 minutes of "up-time" and once I clear the error, I never get another one.
> 
> I have disabled all start up apps, HWiNFO64, and uninstalled GEFORCE Experience as possible suspects, but no luck. Should I even be worried about it? My OCD says yes, but what do you all suspect is causing this?
> 
> Huge thanks in advance for any insight and appreciate any suggestions/ideas.
> 
> 
> View attachment 2587060


Tagging me as an expert 

Leave your IOD at 1.0v or even 1.05v and see what happens. I run mine at 1.0v, that's even with my VSOC stable on auto and my VDDP at 0.8v.

WHEA as far as I'm aware is usually about the CPU/Infinity Fabric, not to do with memory timings.


----------



## Worgened

The_King said:


> Please do me a favor and run Thaiphoon burner and post a screenshot of what ICs you have.
> 
> 
> Thaiphoon Burner - Official Support Website
> 
> 
> View attachment 2587081
> 
> 
> It is possible the Speed grade of your DIMMS are different from mines.
> 
> If you run 25 cycles with TM5 and pass then you should be fine even if its 26/28. If you running CL16 maybe a good idea just to keep GDM enabled for better stability.
> 
> If your DIMM is a lower speed grade / bin then you would need 3800 CL16-19-19-19 to be stable or 3800 CL15-19-19-19. Older binns may even need 3800 CL16-20-20-20.
> 
> You can also try changing to 2T that may make it 26/26 or 28/28.


Ty for help mate here they are


----------



## The_King

Worgened said:


> Ty for help mate here they are
> View attachment 2587127
> View attachment 2587128


They are slightly lower than the Kit I have but these are some very good bin Micron Rev .B

Not sure why now you having problems with the settings i gave earlier. C9BLH should perform really well.
Over 5000 DDR4 and can do 3933/4000 CL16-17-17-17 this video has proof with 3 cycles of anta777 at around 54 seconds.






Your issues maybe coming from GDM being disabled. Don't run with GDM disabled and keep it at CL16


----------



## Worgened

The_King said:


> They are slightly lower than the Kit I have but these are some very good bin Micron Rev .B
> 
> Not sure why now you having problems with the settings i gave earlier. C9BLH should perform really well.
> Over 5000 DDR4 and can do 3933/4000 CL16-17-17-17 this video has proof with 3 cycles of anta777 at around 54 seconds.


Ty for answer mate as i said before i will use first setting that i shared with you. You said 26 / 28 wont be problem. Since i dont get any error so i will use it 26/28


----------



## marceloavf

Something that I can improve here?
Still not able to get 1T stable, using 1.4v on mem voltage.


----------



## dimkatsv

marceloavf said:


> Something that I can improve here?
> Still not able to get 1T stable, using 1.4v on mem voltage.
> 
> View attachment 2587187


Try ClkDrvStr at 40-60, if you really wanna try to do this.


----------



## gvansly1

Netblock said:


> I solved this once, but l don't remember what I did. I was chasing this on my Matisse last night, and I might have solve it. It's probably either the CCD voltage (I raised it), or is related to PCIe stuff in the CBS menus (I enabled everything; PCIe AER, SRIS, ACS, ARI enable, ARI enumeration, LCLK DPM to 600MHz only).


Thanks for the insight, but neither solution corrected the problem.



ManniX-ITA said:


> As said it could be you need fine-tuning of the CCD voltage.
> But being only one and so regular and only after a warm or cold restart it's more likely one core, not necessarily the one in the WHEA, that is unstable.
> If you are at a stock settings, can be one of your cores needs a positive CO offset.
> Usually it happens more frequently after a wake up form sleep that after a cold or warm boot, worst scenario for the CPU.


Thanks Manni, I'm at stock / default settings, except DDR4 timings and voltages, so no curve to offset. I tested CCD at 50mv increments but the issues still exists.
One thing is for sure, waking after sleep mode triggers the WHEA 19, after it's cleared nary another in sight!




Audioboxer said:


> Tagging me as an expert
> 
> Leave your IOD at 1.0v or even 1.05v and see what happens. I run mine at 1.0v, that's even with my VSOC stable on auto and my VDDP at 0.8v.
> 
> WHEA as far as I'm aware is usually about the CPU/Infinity Fabric, not to do with memory timings.


AudioB, I tagged you cause you had these sticks at one time. 1.0 and 1.05v sadly did not help, appreciate the suggestion.




Taraquin said:


> I wouldn't bother with rare WHEA19 as long as they don't clog the system, cause instability etc


Thanks Taraquin, Think I'll take this advice, since there are NO WHEAs during stability testing as stated in my original post. The trigger seems to be linked to the wake up after sleep mode, so I'll just deal with it.....

Sadly, did not get any input from Veii,  I know he's busy so no worries, thanks to all for insight and suggestions.


----------



## Taraquin

Taraquin said:


> Yeah, may be that, will try later


Okay, I tried again, seems something has changed after last win10 update. I get 53.9-54ns at 3800cl14 and 54.5ns at 3800cl15. I tried safemode at then I get 52.7ns 3800cl14 and 53.2ns 3800cl15. Seems about right then. I tried higher SOC, IOD, CCD, VDDP, VDD18, no improvement.


----------



## marceloavf

dimkatsv said:


> Try ClkDrvStr at 40-60, if you really wanna try to do this.


It POST but gave me many errors on test straight away


----------



## ManniX-ITA

gvansly1 said:


> Thanks Manni, I'm at stock / default settings, except DDR4 timings and voltages, so no curve to offset. I tested CCD at 50mv increments but the issues still exists.
> One thing is for sure, waking after sleep mode triggers the WHEA 19, after it's cleared nary another in sight!


You have to go to the PBO settings and enable it.
Use Standard limits and enable CO for all counts, test with +15 all cores and if it happens again +30.
If it doesn't happen, you have like me at least one bad core that needs a positive offset.
Either below or above +15; usually it's between 0 and +10.


----------



## Taraquin

gvansly1 said:


> Thanks for the insight, but neither solution corrected the problem.
> 
> 
> 
> Thanks Manni, I'm at stock / default settings, except DDR4 timings and voltages, so no curve to offset. I tested CCD at 50mv increments but the issues still exists.
> One thing is for sure, waking after sleep mode triggers the WHEA 19, after it's cleared nary another in sight!
> 
> 
> 
> 
> AudioB, I tagged you cause you had these sticks at one time. 1.0 and 1.05v sadly did not help, appreciate the suggestion.
> 
> 
> 
> 
> Thanks Taraquin, Think I'll take this advice, since there are NO WHEAs during stability testing as stated in my original post. The trigger seems to be linked to the wake up after sleep mode, so I'll just deal with it.....
> 
> Sadly, did not get any input from Veii,  I know he's busy so no worries, thanks to all for insight and suggestions.


Thanks for calling me expert by the way, I don't feel like that. Veii, Manni etc knows far more than me


----------



## Veii

gvansly1 said:


> Sadly, did not get any input from Veii,  I know he's busy so no worries


Sorry
Random WHEA 19 is hard to track, as it can be anything IO related
~ can be lack of chipset voltage
~ buggy powerplan that doesn't solve that issue (grab CPUDoc , let it autorun and test if running that powerplan actually resolves your random WHEA)
~ lack of VDDG CCD
~ lack of SOC

But yes, sorry
Don't really have much time and sit at old AGESA atm ~ till i figure out how to not break signature on bios mods (DXE replacement)
Can take days with no user help ~ soo no Rev.E memOC test either till that is resolved. And no further AM5 testing, till that is resolved 


Taraquin said:


> Thanks for calling me expert by the way, I don't feel like that. Veii, Manni etc knows far more than me


You're humble~
Also not even close (i'm still amateur)


----------



## 67091

I’ve come to conclusion that Testmen 5 is garbage , it’s complete random. I have two machines one with AMD another with INTEL, both passed Absolut 10 cycle at 3000 percent , which took like 10 to 12 hours on the intel 16gb and 15 or so on the AMD 32gb. Now, because I couldn’t believe it passed I wanted to do it again to double check if it was stable and Nope , both machines won’t pass. I’ve tweaked voltage ever so slightly back and forth and it continually fails. I truly believe most people run 3 cycles and call it stable. Is there anyone here that has run multiple runs of this software and consistently get passes over the standard 3 cycles with this software.


----------



## MrHoof

angushades said:


> I’ve come to conclusion that Testmen 5 is garbage , it’s complete random. I have two machines one with AMD another with INTEL, both passed Absolut 10 cycle at 3000 percent , which took like 10 to 12 hours on the intel 16gb and 15 or so on the AMD 32gb. Now, because I couldn’t believe it passed I wanted to do it again to double check if it was stable and Nope , both machines won’t pass. I’ve tweaked voltage ever so slightly back and forth and it continually fails. I truly believe most people run 3 cycles and call it stable. Is there anyone here that has run multiple runs of this software and consistently get passes over the standard 3 cycles with this software.


Depends on the config you use, Anta extreme takes alot longer per cycle compared to 1usmus.v3. Anta would need 3 cycles to run around 2h to 2h30 while 1usmusv3 would need 25 cycles.


----------



## PJVol

Veii said:


> here you can see ITX-Extreme4 Zombify.)


You did managed to make it ignore +200 limit?


dimkatsv said:


> But i can set it to 0 instead. And FIT limit will actually become 0. Which, i assume, means it will be completely removed?


It means your VID limit is now 1.35V, instead of 1.45V in the pre-1204(7) agesa firmware.


dimkatsv said:


> Actually throttlers usually limit max requested VID instead of working on frequency. Then frequency adapts to current temp and available voltage.


It's not that simple.


dimkatsv said:


> Also. Really wanna mention. In ZenPT i don't even see ProcHot with value 65. Maybe anther mislable and it was related to default CPU PPT?


I'd not rely on both of these monitoring tools, since the 1st (asus') is based on too outdated smu metrics table version, and the 2nd (ZenPT) has a number of labels mismatched and need to be corrected/updated, e.g. throttlers clock (infrastructure limits). What Veii thinks is prochot F-limiter is actually not.
First out of 8 limiter-clocks reported by SMU - Global Core Clock (not PPT) - it's calculated by proportional-intergral-derivative programmable controller (PID) being part of the DVFS/AVFS. It's also referred to by HWInfo64 as "Frequency limit - Global" in a sensor panel.


dimkatsv said:


> P.S. Ah, about FIT, i see... Under low load when transient (?) hits (like i alt-tab), when i am on 4650, i will get low readings. But if i set 4850, i will get spikes up to 25.


That makes sense 'cause FIT is just a function of temperature and voltage, and is used by the reliability tracker.


----------



## 67091

MrHoof said:


> Depends on the config you use, Anta extreme takes alot longer per cycle compared to 1usmus.v3. Anta would need 3 cycles to run around 2h to 2h30 while 1usmusv3 would need 25 cycles.


Yea I don’t have any problem with the time needed to do a thorough test , my problem is tests are failing just between reboots were no bios settings have changed. Both machines have 120mm fans facing the memory. The max ram temperature from both machine are 42c .


----------



## ManniX-ITA

angushades said:


> I’ve come to conclusion that Testmen 5 is garbage , it’s complete random. I have two machines one with AMD another with INTEL, both passed Absolut 10 cycle at 3000 percent , which took like 10 to 12 hours on the intel 16gb and 15 or so on the AMD 32gb. Now, because I couldn’t believe it passed I wanted to do it again to double check if it was stable and Nope , both machines won’t pass. I’ve tweaked voltage ever so slightly back and forth and it continually fails. I truly believe most people run 3 cycles and call it stable. Is there anyone here that has run multiple runs of this software and consistently get passes over the standard 3 cycles with this software.


TM5 is 100% reliable, not random at all. We wouldn't be using it since years otherwise 
If you can pass with one config, doesn't mean you can pass with another; the tests are different.
Use the 1usmus, run it for at least 25 cycles/32GB or 12/16GB and come back with the errors.
We often run it for 50/100 cycles or more.
Use the anta777 config to double check, at least 3 cycles.
I don't think I've ever run the Absolut config, I'm not sure that is reliable.

If you keep having random problems, it's a software issue.
Maybe you use the PC while testing or you are installing on both something that is causing a memory leak over time.
Open something that allocates a lot of RAM, run TM5 and once is started close what you opened before.


----------



## dimkatsv

ManniX-ITA said:


> I don't think I've ever run the Absolut config, I'm not sure that is reliable.


Tbh, it feels MUCH more reliable than Usmus one. No BS when random error pops out 4 hours into the test.



PJVol said:


> It means your VID limit is now 1.35V, instead of 1.45V in the pre-1204(7) agesa firmware.


Yes, kind of. I am not sure if it is 1.35 or 1.375 (just don't remember and don't want to reboot to test). EDC "bug" (and i am not quite sure if it actually is bug) in last few days causes it to be 1.375. And why i am not sure that it is bug? Seems like it was made intentionally as after 1.375V frequency scaling becomes inconsistent and inefficient, but cost of FIT for such upgrade is about 5-10x more. CPU still can get to 4850 at split seconds, but it won't try to engage into high FIT value territory. These 0.075V cause FIT readings to increase by up to 10-20x times. And in addition makes testing of voltage stability so inconsistent if you don't limit CPU by your weakest core frequency.
Funniest part. If i have EDC "bug" triggered, and THEN set scalar to 0, then i am getting latchup voltage restricted to 1.275V (set voltage is still 1.375). With resulting drop in frequency. Now that one is definitely severe undercut. I mean... i still get 4645 single thread and 4600 (instead of 4675-4725) multicore in CPU-Z. But my CPU sample, as i said before, decent undervolter, not a good overclocker.



PJVol said:


> It's not that simple.


Definitely it isn't. But in most cases it is simpler to work with voltage isn't it? I mean, of course several types of behaviour happen simultaneusly and limit usually measures by lowest one. And depending on situation voltage won't necessary be lowest one. But as simple enthusiast my knowledge is limited by my observations and data i can collect. So precision of my conclusions may suffer.



PJVol said:


> I'd not rely on both of these monitoring tools, since the 1st (asus') is based on too outdated smu metrics table version, and the 2nd (ZenPT) has a number of labels mismatched and need to be corrected/updated, e.g. throttlers clock (infrastructure limits). What Veii thinks is prochot F-limiter is actually not.
> First out of 8 limiter-clocks reported by SMU - Global Core Clock (not PPT) - it's calculated by proportional-intergral-derivative programmable controller (PID) being part of the DVFS/AVFS. It's also referred to by HWInfo64 as "Frequency limit - Global" in a sensor panel.


Thanks for letting me know, i was bit losing my head, because PPT limit engaged too frequently.
What about FIT_voltage lines and CCLK_limit. They engage at same time and to same values.

Also... I just noticed (maybe because i wasn't focused on load types before?) that FIT values change not depending on EDC (well EDC change is side effect actually), but because of changing engaged core amount
Depending on amount of load (thread count doesn't matter only raw core count)
[Amount of cores] / [FIT_Limit value]. Of course based on my 5600X sample
6 / 192
5 / 233
4 / 297
3 / 408
2 / 651
1 / 1618
That's why for some people on multicore load higher FIT helped achieve higher sustained frequencies, while on single core it wasn't doing anything. Because on multicore FIT limit is lowest and they hit ceiling. Maybe it is also like that as 5800X and above are rated for higher sustained frequencies, so they ask for bit more of a voltage?

P.S. I decided to live with "bug" enabled. 30-40 mHz on core 0 don't cost 0.075V and 5-10X more FIT requirements.
P.P.S. CPU-Z is strange, Unlike Y-Cruncher it actually decrease multicore frequency if you increase EDC. With EDC=90 i achieve 4700+. With EDC=120 it only goes to 4650+. With EDC 100-110 it is around 4675-4680


----------



## Frosted racquet

ManniX-ITA said:


> Open something that allocates a lot of RAM, run TM5 and once is started close what you opened before.


Wouldn't TM5 just use the freed up RAM when it starts another test cycle?


----------



## dimkatsv

Frosted racquet said:


> Wouldn't TM5 just use the freed up RAM when it starts another test cycle?


Nope. TM5 uses fixed page size. It is automatically calculated at beginning of session and then never changes.


----------



## Frosted racquet

dimkatsv said:


> Nope. TM5 uses fixed page size. It is automatically calculated at beginning of session and then never changes.


Just tested here and it doesn't seem to work that way. Started HCI memtest, low priority threads, allocated about 3.5GB RAM, started TM5 1usmus profile, exited HCI. On 1st cycle RAM usage was around 26-27GB, second cycle 30+GB from 32GB total.


----------



## dimkatsv

Frosted racquet said:


> On 1st cycle RAM usage was around 26-27GB, second cycle 30+GB from 32GB total.


Strange. It actually should write you dedicated RAM per thread. I don't remember it changing after test beginning. But i know that RAM testers LOVE to use page file. Maybe it just used free space in RAM instead of page file?


----------



## Frosted racquet

I'll post more detailed screenshots/info tomorrow


----------



## 67091

Sorry let me clarify, I never changed the config file , it was a simple reinstall . In this order ( Window 11 - Updates -Sophia script - Drivers - TM5 (passed) Tested it overnight - Rebooted - Overwatch 2 - TM5 Failed Error 15 Overnight test) 
And in regards to why people use might use it more is because it’s free by the way I don’t recall memory tuning being a big thing when DDR 1/2/3 was mainstream. Only overclocking speeds not so much tinkering with timings.
Im asking has any tried running two TM5 stress test using Apsolute two consecutive times after a reboot.


----------



## PJVol

dimkatsv said:


> EDC "bug" (and i am not quite sure if it actually is bug) in last few days causes it to be 1.375


Not sure I understand what EDC bug you're about


dimkatsv said:


> What about FIT_voltage lines and CCLK_limit. They engage at same time and to same values.


I doubt the clock labeled "FIT_voltage changes", but "FIT_PRE_voltage" might, which should be the CCA frequency from the EDC throttler (assuming the original PM table clocks' order kept intact). Anyway, it'd be better to see actual runtime screenshot, though the clocks order seem to be different.
CCLK limit is the same as Global Freq.


dimkatsv said:


> Because on multicore FIT limit is lowest and they hit ceiling. Maybe it is also like that as 5800X and above are rated for higher sustained frequencies, so they ask for bit more of a voltage?


See the end of my previous post.


----------



## ManniX-ITA

@Frosted racquet 
@dimkatsv 

RAM allocation is dynamic, it can change also during a cycle.
Which is very bad for the testing process.
The trick of opening something before starting TM5, more than how TM5 will work is about how Windows will handle page locks requests from TM5.

I think this confusion on how memory testing is working on Windows is the reason of the perceived randomness of TM5 and other similar software.
If you want to test with a certain 99% coverage of your RAM, you need to boot directly into Memtest86.
RAM allocate to Memtest86 and other reserved blocks, can't be tested. But on today's PC with 16/32GB it's really a few hundreds of MBs.

When you test on Windows, the coverage is much lower.
You are never going to test RAM blocks occupied by the Kernel or other reserved memory from Windows or allocated by drivers.
In general you are never going to test whatever is never given by Windows as a page lock.

One of the reasons for testing with so many cycles, or up to 20000% for Kharu, is indeed this, increasing the chances of more coverage.

TM5 is very sophisticated but also quite brutal.
Veii explained once how some tests are depending from the previous test operations; I understood some of it 
TM5 is not "smart" enough to detect if a page lock allocation changed from the previous test and restart the cycle.
I guess there are good reasons for this, starting from less complexity.
In any case, even with some more "smart" tricks, you should always use a clean system and never touch it while is testing.
That complexity would probably be not worth the effort, if even feasible.
Sometimes Windows is doing stuff without telling the application and just silently shift the allocated pages somewhere else.
I've read this is often unavoidable.
So you would probably end up with this kind of "protection" in restarting cycles more than completing them or getting errors with the wrong impression it wasn't for sure a Windows issue.
You always need to account Windows messing up testing, if you test on Windows.

And you always need to keep into account that you are never testing all RAM on Windows.
That's why it's ok to test the with anta Extreme or Absolut which have one very long cycle and very long tests.
To get the same coverage % you reach with the 1usmus config in one day you probably need to run them for weeks.

@angushades 

Don't be surprised if you get seemingly random errors.
Run the 1usmus config as told, even for more cycles.
You will get much better coverage and chances are better to spot an issue.
From what you described, it could also be a training issue.
If you reboot and you get errors you may have a simple termination issue which is causing instability after boot if the memory fails training. Or not.

If you have too many of these issues you have also other options:









Enable the Lock Pages in Memory Option (Windows) - SQL Server


Learn how to turn on the Lock Pages in Memory option. See how it can boost performance by keeping data in physical memory instead of paging it to disk.



learn.microsoft.com





Enable the "*Lock pages in memory* policy" for the user you are running TM5 with. It can help, not very often to be honest but I always do it.

Change the memory testing options in the MT.cfg:

Testing Window Size (Mb)=880
Lock Memory Granularity (Mb)=16
*Reserved Memory for Windows (Mb)=128*

I never change the window size or the granularity but adding a bit more to the reserved memory will reduce the window size and it does help in extreme cases.
But than you need more cycles to test with the same coverage.
And always remember that there's a part of memory you will never test in Windows.

I was always testing with Memtest86 for this reason but TM5 is so much better and faster at detecting issues that I fell it's not worthwhile.
If Windows is booting or not is usually enough to tell if there's a very bad instability in the memory you can't test.


----------



## 67091

@ManniX-ITA . Thanks for the reply, I’ll give what you suggested ago.


----------



## ManniX-ITA

angushades said:


> @ManniX-ITA . Thanks for the reply, I’ll give what you suggested ago.


Good luck!
I know the frustration and I thought often as well that TM5 wasn't reliable.
But at the end it was and there was always something else wrong.
Years of testing by some many people here proven it's one of the best tool to rely on.
Anyway, I always put something else in the mix when I feel something is wrong. It doesn't hurt.


----------



## dimkatsv

PJVol said:


> See the end of my previous post.


Yeah, i understand that part. I just wonder if 5800X works at 4850 at same voltage as 5600X on 4650.
And if yes, than what FIT readings does it get at same state.


----------



## Luggage

dimkatsv said:


> Yeah, i understand that part. I just wonder if 5800X works at 4850 at same voltage as 5600X on 4650.
> And if yes, than what FIT readings does it get at same state.


5800X clear cmos, 1 cycle of y-cruncher in the hwinfo64 log. (No fit of course and unrealistic temps for most people but I had this ss from last weekend up already) 


http://imgur.com/cUxC0iu


----------



## dimkatsv

Luggage said:


> 5800X clear cmos, 1 cycle of y-cruncher in the hwinfo64 log. (No fit of course and unrealistic temps for most people but I had this ss from last weekend up already)
> 
> 
> http://imgur.com/cUxC0iu


Yeah, seems like it just takes less voltage. I cannot even achieve 4850 at all cores easily without maxed out negative CO.
Ngl, even with -30 CO at least 2 of my cores won't be able to get to 4850.


----------



## alkaliv02

So I've been working on these timings for about 1.5 months because this is my first attempt at overclocking RAM. I wanted to get some feedback because I've only been able to compare my timings to the Zen leaderboards. Do my timings and related benchmarks look good for my F4-3600C16D-32GVKC Hynix CJR kit? I aimed for 1900/3800 because I run a B550i SFFPC so I just want to improve latency and reduce voltage/heat where I can.

And bonus question: I want to reduce my VSoC (1.0V?), VDDP and VDDG. Is there a good resource on how those voltages are related so I know how to incrementally lower them? White pages is fine if that is all that is available I am just unsure where to go for that. Thanks!


----------



## Luggage

Veii said:


> Can you export me your +500 FMAX bios too , for learning purposes
> 
> SMU 56.39 seems to be 1.1.8.X AGESA
> 56.40 = 1.1.9.X // but has higher cache throughput
> but 56.43 is still pre 1.2.0.0 ? hmm
> 
> Have you ever tried flashrom on your board , on this bios ?
> Generally are you free for 30min ?


Sorry it took time - MSI still has it online... https://download.msi.com/bos_exe/mb/7C35vA85.zip


----------



## Luggage

dimkatsv said:


> Tbh, it feels MUCH more reliable than Usmus one. No BS when random error pops out 4 hours into the test.
> 
> 
> Yes, kind of. I am not sure if it is 1.35 or 1.375 (just don't remember and don't want to reboot to test). EDC "bug" (and i am not quite sure if it actually is bug) in last few days causes it to be 1.375. And why i am not sure that it is bug? Seems like it was made intentionally as after 1.375V frequency scaling becomes inconsistent and inefficient, but cost of FIT for such upgrade is about 5-10x more. CPU still can get to 4850 at split seconds, but it won't try to engage into high FIT value territory. These 0.075V cause FIT readings to increase by up to 10-20x times. And in addition makes testing of voltage stability so inconsistent if you don't limit CPU by your weakest core frequency.
> Funniest part. If i have EDC "bug" triggered, and THEN set scalar to 0, then i am getting latchup voltage restricted to 1.275V (set voltage is still 1.375). With resulting drop in frequency. Now that one is definitely severe undercut. I mean... i still get 4645 single thread and 4600 (instead of 4675-4725) multicore in CPU-Z. But my CPU sample, as i said before, decent undervolter, not a good overclocker.
> 
> 
> Definitely it isn't. But in most cases it is simpler to work with voltage isn't it? I mean, of course several types of behaviour happen simultaneusly and limit usually measures by lowest one. And depending on situation voltage won't necessary be lowest one. But as simple enthusiast my knowledge is limited by my observations and data i can collect. So precision of my conclusions may suffer.
> 
> 
> Thanks for letting me know, i was bit losing my head, because PPT limit engaged too frequently.
> What about FIT_voltage lines and CCLK_limit. They engage at same time and to same values.
> 
> Also... I just noticed (maybe because i wasn't focused on load types before?) that FIT values change not depending on EDC (well EDC change is side effect actually), but because of changing engaged core amount
> Depending on amount of load (thread count doesn't matter only raw core count)
> [Amount of cores] / [FIT_Limit value]. Of course based on my 5600X sample
> 6 / 192
> 5 / 233
> 4 / 297
> 3 / 408
> 2 / 651
> 1 / 1618
> That's why for some people on multicore load higher FIT helped achieve higher sustained frequencies, while on single core it wasn't doing anything. Because on multicore FIT limit is lowest and they hit ceiling. Maybe it is also like that as 5800X and above are rated for higher sustained frequencies, so they ask for bit more of a voltage?
> 
> P.S. I decided to live with "bug" enabled. 30-40 mHz on core 0 don't cost 0.075V and 5-10X more FIT requirements.
> P.P.S. CPU-Z is strange, Unlike Y-Cruncher it actually decrease multicore frequency if you increase EDC. With EDC=90 i achieve 4700+. With EDC=120 it only goes to 4650+. With EDC 100-110 it is around 4675-4680


Yes CPU-Z likes really strangled EDC (and PPT and TDC) values that will tank most other MC workloads. It's like it want's SC tuning even for MC... 


http://imgur.com/a/5QD8amF


----------



## Luggage

PJVol said:


> Not sure I understand what EDC bug you're about
> 
> I doubt the clock labeled "FIT_voltage changes", but "FIT_PRE_voltage" might, which should be the CCA frequency from the EDC throttler (assuming the original PM table clocks' order kept intact). Anyway, it'd be better to see actual runtime screenshot, though the clocks order seem to be different.
> CCLK limit is the same as Global Freq.
> 
> See the end of my previous post.


Runtime SS like?


http://imgur.com/a/boLMzxU


----------



## 67091

A night of running 1Usmus these are the errors I got on TM5. I've looked on the excel sheet it says i need to increase RDWR/WRRD. Does that seem right, guys?


----------



## dimkatsv

angushades said:


> I've looked on the excel sheet it says i need to increase RDWR/WRRD. Does that seem right, guys?


I... am not sure. 2 errors in 8.5 hour test is too rare for timings with such strong effect as RDWR/WRRD.
I mean... you can try tinkering with them, but there may be something else, imo.

Also damn these ultrawide screens. Screenshots from such monitors are TERRIBLE to watch on for details, as they, well, don't fit on normal screen.


----------



## Giacomo Coppi

Hi everyone, after some failed tests i am here again to share with you what i've tryed and to figure out what i am doing wrong with your help if it's possible . 

My actual ram kit is this one from g skill 16gb x 2 f4-3200c14-16gtzr 3200mhz cas 14-14-14-34-48 at 1.35v xmp mounted on a 
b550 asus strix F with daisy chain topology and a 5600x rated platinum on ctr 2.1
down here there is a picture of my actual ram setting at 1.5000v 

















In those days i tryed many times to reach 4000mhz on ram with the timings you can see up here but trfc loosen at 500 .
i tryed : 
PLL voltage from 1.80000v to 1.85000v and 1.90000v 
Ram voltage up to 1.5500v with ram vttddr 0.7750v 
different IF setup like 2000mhz 1966mhz 800mhz 999mhz 
should i try to loosen all the timings just o see if it boot at 4000mhz ?
are 20-26-26-40-80 ok to try ? 
Thanks to you all


----------



## 67091

dimkatsv said:


> I... am not sure. 2 errors in 8.5 hour test is too rare for timings with such strong effect as RDWR/WRRD.
> I mean... you can try tinkering with them, but there may be something else, imo.
> 
> Also damn these ultrawide screens. Screenshots from such monitors are TERRIBLE to watch on for details, as they, well, don't fit on normal screen.


Sorry , I’ll put everything on one screen next time.


----------



## dimkatsv

angushades said:


> Sorry , I’ll put everything on one screen next time.


Don't worry too much, you have a lot of info for one screen, so no problem.
Just annoying to zoom in on such screenshots, nothing too critical.


----------



## PJVol

Luggage said:


> Runtime SS like?


Yep, looks like throttler clocks are not in order. Though you can check it yourself, just make another linpack run with the default EDC setting and see which one is most restrictive.
ProcHOT and HTFmax are static limits. When activated, Fmax severely dropped by 250Mhz or more until temps get back to normal or hysteresis threshold is passed in case of occasional thermal spike. AFAIK HTFmax temp is 90° and ProcHOT is activated by VR_HOT pin low, and CPU goes into the HTC (high temperature control mode with a low performance P-state until cooled), so neither of two should be engaged if cooled properly.


----------



## jonnyzeraa

hey guys, someone can give me tips for make this stable? one friend of mine have the same memories ( 3600 cl 14-15-15-28 1.45v xmp ) b-die, but 8x4 and he can make this stable without errors, but here with the 16x2 i got bluescreens when try a mem test, really appreciated if someone can helps / do suggestions about this timings. thx

















first screen is mine, second is from my friend


----------



## dimkatsv

jonnyzeraa said:


> but here with the 16x2 i got bluescreens when try a mem test


Try to loosen up timings and test.
Try to play with ProcODT and ClkDrvStr...
Or set up 2T and forget. 2x 2R can be nasty to stabilize with 1T. Mine also cause BSOD if i put them under load with GDM=OFF 1T. But you may have chance as at least you can boot them without much setup


----------



## Luggage

PJVol said:


> Yep, looks like throttler clocks are not in order. Though you can check it yourself, just make another linpack run with the default EDC setting and see which one is most restrictive.
> ProcHOT and HTFmax are static limits. When activated, Fmax severely dropped by 250Mhz or more until temps get back to normal or hysteresis threshold is passed in case of occasional thermal spike. AFAIK HTFmax temp is 90° and ProcHOT is activated by VR_HOT pin low, and CPU goes into the HTC (high temperature control mode with a low performance P-state until cooled), so neither of two should be engaged if cooled properly.


Ok something is funky >_>
Stock 140A doesn't show so much but "eco" 90A drops effective clock like a stone, but raises "freq" and runs hotter?!? Still the limit doesn't show up...



http://imgur.com/a/zai2PK5


@Veii @dimkatsv


----------



## dimkatsv

Luggage said:


> Ok something is funky >_>
> Stock 140A doesn't show so much but "eco" 90A drops effective clock like a stone, but raises "freq" and runs hotter?!? Still the limit doesn't show up...
> 
> 
> 
> http://imgur.com/a/zai2PK5
> 
> 
> @Veii @dimkatsv


Dang... Multicore 4.8 in Linpack AND! only 200-400 FIT reading. If i do only core 0 4800 (which can only be seen in single thread) my FIT will ramp up to 600 or so... Definitely huge difference between 5600X and 5800X for this matter. (Dang it also runs so cold. . . AIO benefits, i suppose)
And difference is quite simple. Looks like CPU forced to ramp up voltage to get same amount of power. With voltage increase comes temps and frequency.
Question is why effective frequency dropped so much.
I also see that with 90A multicore FIT ramped up to 1000. Likely because of voltage.
Maybe too much power through cores? And it stretches clocks instead? I always measure effective clock, not nominal, but i hadn't met as severe of a case of stretching. My most noticable case was about 50 mHz.


----------



## ManniX-ITA

angushades said:


> A night of running 1Usmus these are the errors I got on TM5. I've looked on the excel sheet it says i need to increase RDWR/WRRD. Does that seem right, guys?


I would try higher tRTP/tWR like 7/14 or 8/16.



Giacomo Coppi said:


> should i try to loosen all the timings just o see if it boot at 4000mhz ?


Did you try with tRDWR/tWRRD in Auto?
Also could help tRRDL to 6 and tWTRS to 5.


----------



## The_King

Giacomo Coppi said:


> Hi everyone, after some failed tests i am here again to share with you what i've tryed and to figure out what i am doing wrong with your help if it's possible .
> 
> My actual ram kit is this one from g skill 16gb x 2 f4-3200c14-16gtzr 3200mhz cas 14-14-14-34-48 at 1.35v xmp mounted on a
> b550 asus strix F with daisy chain topology and a 5600x rated platinum on ctr 2.1
> down here there is a picture of my actual ram setting at 1.5000v
> View attachment 2587592
> 
> View attachment 2587593
> 
> 
> In those days i tryed many times to reach 4000mhz on ram with the timings you can see up here but trfc loosen at 500 .
> i tryed :
> PLL voltage from 1.80000v to 1.85000v and 1.90000v
> Ram voltage up to 1.5500v with ram vttddr 0.7750v
> different IF setup like 2000mhz 1966mhz 800mhz 999mhz
> should i try to loosen all the timings just o see if it boot at 4000mhz ?
> are 20-26-26-40-80 ok to try ?
> Thanks to you all


Have you tried increasing VSOC to 1.15V-1.2V?
Also do not leave ProcODT on AUTO set that in the BIOS else the board may try with a different ProcODT and fail when you increase to 4000MT.
Also try with higher and lower ProcODT.

Sometimes B-die does not like very loose timings and have noticed several times if timings are too loose it fails to post.
You can try with 4000 CL16-17-17-17

Also keep an eye out of WHEA 19 he has an habbit of showing up around FCLK 1933/2000.


----------



## Luggage

dimkatsv said:


> Dang... Multicore 4.8 in Linpack AND! only 200-400 FIT reading. If i do only core 0 4800 (which can only be seen in single thread) my FIT will ramp up to 600 or so... Definitely huge difference between 5600X and 5800X for this matter. (Dang it also runs so cold. . . AIO benefits, i suppose)
> And difference is quite simple. Looks like CPU forced to ramp up voltage to get same amount of power. With voltage increase comes temps and frequency.
> Question is why effective frequency dropped so much.
> I also see that with 90A multicore FIT ramped up to 1000. Likely because of voltage.
> Maybe too much power through cores? And it stretches clocks instead? I always measure effective clock, not nominal, but i hadn't met as severe of a case of stretching. My most noticable case was about 50 mHz.


External rad on my balcony and 5c water temp - that’s why I said my temps are unreasonable in an earlier post. But it “removes” thermal throttle so we can look at PBO limits and voltage…


----------



## Luggage

Luggage said:


> It’s 2 sticks
> But I can cap the boost and see how much it does.


Late reply @The_King boost capped 4850 vs 5050 makes 0.3-0.4ns on mem and L3


http://imgur.com/a/HsO28le


----------



## The_King

Luggage said:


> Late reply @The_King boost capped 4850 vs 5050 makes 0.3-0.4ns on mem and L3
> 
> 
> http://imgur.com/a/HsO28le


I was correct when I said your 5050Mhz boost was lowering your latency in AIDA64. 

@ManniX-ITA was very kind enough to help me out with my boost issues on my 5800X. I seem to have a problem with Dynamic VIDs on my board, my MT performance is great but
my ST is highly unstable. Seem mainly a board or BIOS issue. Needs some further investigating or another board. Apparently this maybe a good bin 5800X held back by my B450 board.
















Some R23 runs in ECO mode 65W and 95W.


----------



## ttnuagmada

Anybody see any low-hanging fruit?

can probably do this at 1.45 or 1.46 VDIMM, I just haven't dialed it in yet. I can do CL14 if I up the VDIMM some, but I noticed it gets me absolutely nothing in latency/bandwidth? Is that normal? This is a 4x8 B-Die setup (stock is 3200CL14)


----------



## jonnyzeraa

dimkatsv said:


> Try to loosen up timings and test.
> Try to play with ProcODT and ClkDrvStr...
> Or set up 2T and forget. 2x 2R can be nasty to stabilize with 1T. Mine also cause BSOD if i put them under load with GDM=OFF 1T. But you may have chance as at least you can boot them without much setup


which one of this options u recommend me start first? try stay with this times and maybe increase procODT and ClkDrvStr? i’m a super novice in this world so .. i’m confused now


----------



## The_King

Huge thanks to @ManniX-ITA you are a legend!
Not my best bin RAM but my CPU hitting 5050+ now thanks to this Ryzen Maestro!😉


----------



## Nd4spdvn

ttnuagmada said:


> Anybody see any low-hanging fruit?
> 
> can probably do this at 1.45 or 1.46 VDIMM, I just haven't dialed it in yet. I can do CL14 if I up the VDIMM some, but I noticed it gets me absolutely nothing in latency/bandwidth? Is that normal? This is a 4x8 B-Die setup (stock is 3200CL14)
> 
> View attachment 2587711


I think it's worth it to pursue further improvements. The fact that you don't get to see latency/bw improvements could be due to a multitude of reasons, be it not ideal voltages in the system (not VDIMM) or some (loose) timings may "hide" them due to how the memory training is accomplished as we only get to see what is usually shown but there are other timings set by mobo too etc. For instance GDM is known to do that, I would suggest stabilizing a set with GDM disabled at 2T or 1T with AddrCmdSetup at 56 if straight 1T bluescreens fast. On your above set I would suggest GDM disabled and 2T, SCLs at 4, tWRRD at 2 (or 3 if no boot, this improves latecy by about 0.4ns alone!), tRDRDSD 1 and tWRWRSD 1 (as you have 4 SR dimms), maybe tWTRS at 3, and with the normal tRAS and tRC approach you have there you can put tWR 10 and tRTP 5. ProcODT 40 (Giga is kinda built around that), maybe some Rtt tweaks too like 6/3/6. And 15-15-15-30-45 once GDM disabled of course.
Or maybe you can straight try this, I have VDIMM at 1.51V set and about 1.512-1.524V get, also a Giga board albeit with B550 chipset, and admittedly I binned my sticks first against each other and then with other 4 so I got now 4 sticks very close each other in terms of voltage requirements (though that changes drastically in a 4 dimm daisy chain mobo with the less preferred slots). See where the above gets you. 

Edit: don't mind my 102 bus and 1904.34 clocks, just do straight (if you wish) 1900 M/F/U at 100 (first at least)


----------



## ttnuagmada

Nd4spdvn said:


> I think it's worth it to pursue further improvements. The fact that you don't get to see latency/bw improvements could be due to a multitude of reasons, be it not ideal voltages in the system (not VDIMM) or some (loose) timings may "hide" them due to how the memory training is accomplished as we only get to see what is usually shown but there are other timings set by mobo too etc. For instance GDM is known to do that, I would suggest stabilizing a set with GDM disabled at 2T or 1T with AddrCmdSetup at 56 if straight 1T bluescreens fast. On your above set I would suggest GDM disabled and 2T, SCLs at 4, tWRRD at 2 (or 3 if no boot, this improves latecy by about 0.4ns alone!), tRDRDSD 1 and tWRWRSD 1 (as you have 4 SR dimms), maybe tWTRS at 3, and with the normal tRAS and tRC approach you have there you can put tWR 10 and tRTP 5. ProcODT 40 (Giga is kinda built around that), maybe some Rtt tweaks too like 6/3/6. And 15-15-15-30-45 once GDM disabled of course.
> Or maybe you can straight try this, I have VDIMM at 1.51V set and about 1.512-1.524V get, also a Giga board albeit with B550 chipset, and admittedly I binned my sticks first against each other and then with other 4 so I got now 4 sticks very close each other in terms of voltage requirements (though that changes drastically in a 4 dimm daisy chain mobo with the less preferred slots). See where the above gets you.
> 
> View attachment 2587792


Hey thanks for the response.

What kind of latency do you get with those settings?


----------



## Nd4spdvn

ttnuagmada said:


> Hey thanks for the response.
> 
> What kind of latency do you get with those settings?


I get about 56.9-57.1ns in AIDA and 64.2ns in IMLC. Win11 22H2 bloated perhaps as it is a Win10 upgrade and had a 5900X before. Could not be bothered to re-install tbh.

Edit: I used to have 57.2ns in Win11 21H2 with a flat15 set, something must have changed with the latest 22H2 as it jumped to 57.8-58ns at some point about a month ago., could never been able to identify a reason so I concluded it was the OS... But then I binned the dimms and dropped tRCDRD to 14 and tWRRD from 3 to 2 and shaved 0.8-1ns which brought me to the above mentioned 56.9-57.1ns.


----------



## 99belle99

ttnuagmada said:


> Anybody see any low-hanging fruit?
> 
> can probably do this at 1.45 or 1.46 VDIMM, I just haven't dialed it in yet. I can do CL14 if I up the VDIMM some, but I noticed it gets me absolutely nothing in latency/bandwidth? Is that normal? This is a 4x8 B-Die setup (stock is 3200CL14)
> 
> View attachment 2587711


I know we have different CPU's and I'm not sure how much of a difference that makes but my RAM is much the same as yours except 3600 rather than 3200. I'm also only using two sticks rather than your four. You can try my settings below. Try it first without AddrCmdSetup 56 if that fails then use that setting.


----------



## 67091

Well, I think its stable for now, I'm going to run it one more night but in the meantime what could I do to reduce tRTP and tWR ? Should i run some other timings on auto to the lower it?


----------



## ManniX-ITA

angushades said:


> Well, I think its stable for now, I'm going to run it one more night but in the meantime what could I do to reduce tRTP and tWR ? Should i run some other timings on auto to the lower it?


Definitely not Auto.

What is probably limiting is tRCDWR at 15, set it to 8.
You can try to look for a better tRDWR/tWRRD combo (save your profile you may need to do clear CMOS).
Try with a 0,1-0,2V bump VDIMM with ProcODT 36,9 Ohm.

Also set a proper tRFC2/tRFC4 226/139:








tRFC mini


TM5 Error Description ,TM5 Errors Decyphered,SOURCE 1usmus_V3,Error Type,Error Description ERROR #0,RefreshStable 0Mb,Voltage cutoff choke, suspect tRRD & tWTR Nearly always tRRD & tWTR but can also be too low tRP or tiny bit too low tRC (if user used > -3 on tRC) Start by adding VDIMM 6x Err...




docs.google.com


----------



## The_King

angushades said:


> View attachment 2588082
> 
> 
> Well, I think its stable for now, I'm going to run it one more night but in the meantime what could I do to reduce tRTP and tWR ? Should i run some other timings on auto to the lower it?


Is that a standard 1usmus_v3? with 5 cycles over 7 hours? that does not look right to me even for 32GB. 25 cycles should stake around 3 hours.


----------



## dimkatsv

The_King said:


> Is that a standard 1usmus_v3? with 5 cycles over 7 hours? that does not look right to me even for 32GB. 25 cycles should stake around 3 hours.


He may have modded test length in %.


----------



## ManniX-ITA

dimkatsv said:


> He may have modded test length in %.


Yes. And really a lot.
Which is reducing, as well, memory coverage.


----------



## dimkatsv

ManniX-ITA said:


> Which is reducing, as well, memory coverage.


On what basis? He still does same job. Just multiple times more over in single run. 
Memory coverage is direct result of test length. How long it will take to run Kahru for different coverage %? And how long one small test of TM5 takes?


----------



## ManniX-ITA

dimkatsv said:


> On what basis? He still does same job. Just multiple times more over in single run.
> Memory coverage is direct result of test length. How long it will take to run Kahru for different coverage %? And how long one small test of TM5 takes?


You haven't read my previous post... and you were tagged.









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Yeah, may be that, will try later :) Okay, I tried again, seems something has changed after last win10 update. I get 53.9-54ns at 3800cl14 and 54.5ns at 3800cl15. I tried safemode at then I get 52.7ns 3800cl14 and 53.2ns 3800cl15. Seems about right then. I tried higher SOC, IOD, CCD, VDDP...




www.overclock.net





It does the same job every cycle but each test is run for much longer.
Read my post above and should be clear why this reduces the memory coverage.

There is a FAQ section with the expected memory coverage on Karhu website.

How much memory coverage can be achieved running a specific config with TM5 is only known to the developers.


----------



## johnnymnt

deleted


----------



## 67091

So, these are the error it made last night, I'm thinking to low VDIMM or Soc voltage.


----------



## ManniX-ITA

angushades said:


> So, these are the error it made last night, I'm thinking to low VDIMM or Soc voltage.


Yes, probably needs a little bump of VDIMM.


----------



## 67091

ManniX-ITA said:


> Yes, probably needs a little bump of VDIMM.











Could alittle too much Vdimm cause this?


----------



## dimkatsv

angushades said:


> Could alittle too much Vdimm cause this?


Technically speaking, yes. Heat instability is a thing. And S8B for example is quite sensitive to heat from what i know


----------



## ManniX-ITA

angushades said:


> Could alittle too much Vdimm cause this?


Yes indeed.
But could also be that the issue is the termination; I don't see Error 6.
Sometimes 0/4 without 6 means voltage is about right but not with that termination.
Try with a slightly lower ProcODT maybe.
Or a different RTT.


----------



## Taraquin

Some findings about my avg binned 4400cl19 vs good binned 3200cl14:
3200cl14: 
3700 14 14 14 RFC 248 at 1.46v
3800 14 14 14 RFC 256 at 1.51v

4400cl19:
3700 14 14 14 RFC 256 at 1.48v
3800 14 14 14 RFC 256 at 1.53v but must run RRDS 5/FAW 20 and WR/RTP 20/10 to avoid errors. 1.55v may work, but get probably overheat and errors very quickly.
3800 14 15 14 and tight timings seem to work at 1.54v

Interesting that they are quite similar at 3700, but at 3800 the 4400cl19 falls off a cliff.


----------



## Taraquin

ttnuagmada said:


> Anybody see any low-hanging fruit?
> 
> can probably do this at 1.45 or 1.46 VDIMM, I just haven't dialed it in yet. I can do CL14 if I up the VDIMM some, but I noticed it gets me absolutely nothing in latency/bandwidth? Is that normal? This is a 4x8 B-Die setup (stock is 3200CL14)
> 
> View attachment 2587711


GDM on masks all sort of issues. Like others said, try to get gdm iff, 2t stable or 1t if lucky. With 2t you can probably run 15 15 15 30 45 at 1.5v stable.


----------



## The_King

Taraquin said:


> Some findings about my avg binned 4400cl19 vs good binned 3200cl14:
> 3200cl14:
> 3700 14 14 14 RFC 248 at 1.46v
> 3800 14 14 14 RFC 256 at 1.51v
> 
> 4400cl19:
> 3700 14 14 14 RFC 256 at 1.48v
> 3800 14 14 14 RFC 256 at 1.53v but must run RRDS 5/FAW 20 and WR/RTP 20/10 to avoid errors. 1.55v may work, but get probably overheat and errors very quickly.
> 3800 14 15 14 and tight timings seem to work at 1.54v
> 
> Interesting that they are quite similar at 3700, but at 3800 the 4400cl19 falls off a cliff.


What are ProcODT and RTTs same on both DIMMS at those settings? GDM settings? best to post Zentimings. 

Will give those settings a try with my 4400 CL19s.


----------



## Taraquin

The_King said:


> What are ProcODT and RTTs same on both DIMMS at those settings? GDM settings? best to post Zentimings.
> 
> Will give those settings a try with my 4400 CL19s.


On 3700 they ran on Intel.

ProcODT 28
Rtts disable disable 7
1t gdm off
No setup times
DrvStr 40 20 30 20 on both

You may have a bit better bin on your 4400 and can pull off flat 14 at 3800


----------



## blodflekk

Can one of you please remind me which setting in the ASUS bios makes it ignore PPT ? I have fmax enhancer off already, but something is stopping me from setting PPT. I know its been talked about in here but I can't remember what it was.


----------



## ttnuagmada

Taraquin said:


> GDM on masks all sort of issues. Like others said, try to get gdm iff, 2t stable or 1t if lucky. With 2t you can probably run 15 15 15 30 45 at 1.5v stable.


Is no GDM with CR2 better than GDM with CR1? I guess I was under the impression that GDM CR1 was sort of like "CR1.5"


----------



## ttnuagmada

Quick question:

Is there any sort of balance between SOC and VDIMM? I was able to get pretty low with my SOC even at fclk 1900 (1.025) with this 5800X3D but seem to need about 1.49v on the ram to do 3800CL16. the 5800X I had before this 5800X3D only needed 1.45v to do the same timings at 3733, but I was running a 1.1v on the soc. Seems odd that I would need that much of a jump on the ram just to go from 3733 to 3800.


----------



## Taraquin

ttnuagmada said:


> Is no GDM with CR2 better than GDM with CR1? I guess I was under the impression that GDM CR1 was sort of like "CR1.5"


Speedwise they are quite similar, but GDM forces CL, CWL, WR, RTP to run even numbers, making CL 17, 15 etc impossible, hence less flexibility, but 2t gdm off is a bit harder to run than gdm on 1t.


----------



## Nd4spdvn

ttnuagmada said:


> Is there any sort of balance between SOC and VDIMM? I was able to get pretty low with my SOC even at fclk 1900 (1.025) with this 5800X3D but seem to need about 1.49v on the ram to do 3800CL16. the 5800X I had before this 5800X3D only needed 1.45v to do the same timings at 3733, but I was running a 1.1v on the soc. Seems odd that I would need that much of a jump on the ram just to go from 3733 to 3800.


Probably there is some sort of balance. Difficult to explain on my part but what I noticed while also using a 5900X before the 5800X3D is that for higher IFs (3733+) higher vSOC is often needed, and not just to be stable but also to provide the expected performance - useful range 1.1-1.25V depending on M/U/F clocks. I observed this with the various "pi" benches under Benchmate where if the voltage was suboptimal they were either showing slight regressions or jumpy results. And observed the same about other voltages too like the CLDO_VDDP and CPU_VDDP which I tend change together - at or over 1900 IF I noticed a slight bump in both VDDPs helps with results consistency, in my case about 20mV on both at 1900 IF, higher might require more. Also, these 2 need to be set and the system cycled on/off for them to actually be in effect. Same, with CPU 1.8V PLL rail, it needs set and the system powered off and only then you can bump up the IF higher for the expected behaviour. There is also the whole rabbit hole of clean signal and proper powering especially on DIMMs with the rule stating that higher voltages tend to ruin the signal cleanness, so balancing act there is.


----------



## Jeager

Didnt play with me hardware since 5 years, I guess it look fine for my old motherboard/ram 
RAM at 1.4v, other voltage are coming from first XMP load (maybe I should lower them ?)
Lowering RRDS/RRDL/FAW seem to give me WHEA errors on y-cruncher (timing after tFAW are in auto)

edit: look like I still have errors in game now ****, can it be related to pbo (pbo -20 auto clock +200)


----------



## Taraquin

Jeager said:


> Didnt play with me hardware since 5 years, I guess it look fine for my old motherboard/ram
> RAM at 1.4v, other voltage are coming from first XMP load (maybe I should lower them ?)
> Lowering RRDS/RRDL/FAW seem to give me WHEA errors on y-cruncher (timing after tFAW are in auto)
> 
> edit: look like I still have errors in game now ****, can it be related to pbo (pbo -20 auto clock +200)


Tune ram first, do pbo+co after


----------



## Imprezzion

I was playing with some RAM OCing and ran into a weird latency issue.. Daily I run 3933 16-16-16-36-52-272-1T GDM On with decently tight subtimings but nothing crazy. It runs in the low 59ns range consistent in AIDA. I set up 3800 14-15-14-28-42-256-1T GDM Off and tested that, high 60's.. So, I set up something completely different, 3600 13-14-14-21-35-240-1T GDM Off with super tight subtimings and tested again. 63ns... 3733 straight 15's, 63ns..

Can anyone explain why a way tighter setup with native 1T gives so much worse latency compared to super loose 3933C16 1T GDM? I don't get it..


----------



## 67091

OMG so close.More VDIMM?


----------



## dimkatsv

Taraquin said:


> Tune ram first, do pbo+co after


As PBO can affect RAM stability i will disagree. 
Tune PBO first, then RAM, or he risks turning stable RAM OC into unstable one


----------



## The_King

Jeager said:


> Didnt play with me hardware since 5 years, I guess it look fine for my old motherboard/ram
> RAM at 1.4v, other voltage are coming from first XMP load (maybe I should lower them ?)
> Lowering RRDS/RRDL/FAW seem to give me WHEA errors on y-cruncher (timing after tFAW are in auto)
> 
> edit: look like I still have errors in game now ****, can it be related to pbo (pbo -20 auto clock +200)


Ram should be Samsung B-die but shows model number is Unknown in ZenTimings.
Please post Thaiphoon burner screenshot or CPU-Z SPD tab.


----------



## Taraquin

dimkatsv said:


> As PBO can affect RAM stability i will disagree.
> Tune PBO first, then RAM, or he risks turning stable RAM OC into unstable one


Pbo + co doesn't help performance that much and he dunno if it is stable. Hence I would turn it off, tune ram first, then CO. Since it can make ram oc unstable, do it after to remove one source of error


----------



## dimkatsv

Taraquin said:


> Pbo + co doesn't help performance that much and he dunno if it is stable. Hence I would turn it off, tune ram first, then CO. Since it can make ram oc unstable, do it after to remove one source of error


Well not that we disagree overall, i just expected it to be other way. 
Set RAM to default - stabilize PBO, then tune RAM


----------



## Taraquin

dimkatsv said:


> Well not that we disagree overall, i just expected it to be other way.
> Set RAM to default - stabilize PBO, then tune RAM


Nah, since ram tuning can destabilize a pbo+co that is stable at xmp you just introduce one more possible problem. If you just use pbo, fine, but I would wait with CO to after ram since, well, ram tuning can make ot unstable. No need to first find stable CO, then tune ram, then have to find stable CO again. I have tuned many Zen 3 systems and I always start with ram, then co+pbo, then fine tune voltages like SOC, IOD, VDDP in the end


----------



## Taraquin

Kinda weird that when temp reaches 41.5C or higher the errors start piling up.


----------



## Artylol

Taraquin said:


> View attachment 2588455
> 
> Kinda weird that when temp reaches 41.5C or higher the errors start piling up.


Increase VDIMM


----------



## Imprezzion

Taraquin said:


> View attachment 2588455
> 
> Kinda weird that when temp reaches 41.5C or higher the errors start piling up.


It's at a lower temp then usual but I'm with @Artylol on this one. More vDIMM means more temperature tolerance but also higher temperatures. It's a fine balance but at only 41.5 I would just increase to 1.53v and try again.

Sidenote. I see everyone running tRDWR and tRRD at like, 7/1 while I can't even POST at any speed, even just XMP 3600C16 at anything below 9/5. It's odd as on Intel I could run 7/2 just fine with these DIMMs.


----------



## Taraquin

Artylol said:


> Increase VDIMM


I can try a bit more vdimm, but the errors are temp-related so I guess it`s about finding a sweetspot


----------



## SneakySloth

Taraquin said:


> View attachment 2588455
> 
> Kinda weird that when temp reaches 41.5C or higher the errors start piling up.


I've had something similar happen with a tight TWR/TRTP. Increasing both a little fixed this for me.


----------



## Imprezzion

This seems to run fine at 1.50v. Had 1 error 12 at like 4h into the test when I ran 5h 25 cycle 1usmus while I was at work but that should be fixed with 1 tick more vdimm and maybe a bit higher tRFC as I kinda question the stability of 130ns at 47c with just 1.50v. I did game all evening without issues tho so it is close enough to stable that i'm convinced I can make it work.

Performs very well too. Higher Copy and a lot lower latency compared to 3933 16-16-16-36-52-272-1T GDM On even with 2T GDM Off due to 15 tCL. My vSOC/VDDG/VDDP is nice and low for 1967 and no WHEA's at all but I still can't drop tRDWR or tWRRD any lower.


----------



## Netblock

Imprezzion said:


> On even with 2T GDM Off due to 15 tCL


I haven't been following what you're trying to do, but it's extremely likely that you can get 1T-off if you mess with the cad bus. You might also need to raise VDDP.



Imprezzion said:


> still can't drop tRDWR or tWRRD any lower.


By AMD's definition, tRDWR has +LD, and tWRRD has -LD, where LD=tCL-tCWL. If you're able to lower tCWL, you can lower tWRRD.


----------



## 67091

Well I’m a-little stumped as I changed what I thought the errors are from and yeah it’s still not passing a complete run.


----------



## Artylol

angushades said:


> View attachment 2588570
> Well I’m a-little stumped as I changed what I thought the errors are from and yeah it’s still not passing a complete run.


Try to set
1) tFAW to 24, tWTRL 10, and maybe tWTRS to 5
2) tWR 14, tRTP 7
Test in-between. If does not work try to fall back to flat 16 or even 18 and play from there


----------



## Artylol

Imprezzion said:


> View attachment 2588550
> 
> 
> This seems to run fine at 1.50v. Had 1 error 12 at like 4h into the test when I ran 5h 25 cycle 1usmus while I was at work but that should be fixed with 1 tick more vdimm and maybe a bit higher tRFC as I kinda question the stability of 130ns at 47c with just 1.50v. I did game all evening without issues tho so it is close enough to stable that i'm convinced I can make it work.
> 
> Performs very well too. Higher Copy and a lot lower latency compared to 3933 16-16-16-36-52-272-1T GDM On even with 2T GDM Off due to 15 tCL. My vSOC/VDDG/VDDP is nice and low for 1967 and no WHEA's at all but I still can't drop tRDWR or tWRRD any lower.


You are most likely VDIMM limited due to raising temperature. tRCD is the culprit. VSOC might help, but not likely


----------



## The_King

Taraquin said:


> I can try a bit more vdimm, but the errors are temp-related so I guess it`s about finding a sweetspot


I know you have a 2 DIMM board and these errors are heat related but. I think everyone should always do the swapped dimm test.
Switch postion of your DIMMS and see if there is any improvement. Basically check If you require the same voltage or lower etc after the swap.

Can definitely make a difference on 4 DIMM boards, I can confirm with several kits that I have tested. Won't hurt to try with yours


----------



## Artylol

Taraquin said:


> I can try a bit more vdimm, but the errors are temp-related so I guess it`s about finding a sweetspot


Your voltage is quite low, I can't push tRCD 14 even at 1.54V. I don't have temperature sensor on DIMM, but I'm pushing to 50s


----------



## diggiddi

I have 64gb of Teamgroup 3200 
TeamGroup T-FORCE VULCAN Z 64GB (2 x 32GB) DDR4-3200 PC4-25600 CL16 Dual Channel Desktop Memory Kit TLZGD464G3200H - Gray - Micro Center 
and find myself running out of RAM, will adding additional 16 GB hamper my system? 5900x 








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Get it now! Designed for complete protection and enhanced heat dissipation, the heat spreader is formed by punch press process with a 0.8mm thick, one-piece alloy aluminum to reinforce the body structure.




www.microcenter.com


----------



## Imprezzion

Netblock said:


> I haven't been following what you're trying to do, but it's extremely likely that you can get 1T-off if you mess with the cad bus. You might also need to raise VDDP.
> 
> 
> 
> By AMD's definition, tRDWR has +LD, and tWRRD has -LD, where LD=tCL-tCWL. If you're able to lower tCWL, you can lower tWRRD.


What I tried to do is basically make my 3933 daily profile have less latency and better copy performance. I used to run a nice and conservative 3933 16-16-16-36-52-272-1T GDM ON profile at 1.450v with tweaked but not very tight subtimings. It's basically 3600C16 DOCP with 3933. I know my DIMM's can handle much tighter (on Intel at least) but temperatures become a problem. 

1T GDM Off works up to 3800 with AddrCmdSetup 56 and ClkDrvStr 40-24-24-20 but I have never been able to stabilize it above 3800 regardless of bus or str settings. Always throws error 6 and 12 within minutes.

I'll try and see if it'll pass without errors overnight or while I'm at work with 15-16-15 and a little less voltage to get the temps down a bit.


----------



## GhOsT662

angushades said:


> View attachment 2588570
> Well I’m a-little stumped as I changed what I thought the errors are from and yeah it’s still not passing a complete run.




Are your tphyrdl all at 26?


----------



## Taraquin

SneakySloth said:


> I've had something similar happen with a tight TWR/TRTP. Increasing both a little fixed this for me.


Raising WR\RTP to 14\7 from 10\5 helped a bit. First error occured at 42.6C now, with tighter WR\RTP it always occured at 41-41.5C. Second error came at 44C, usually at 43C or above the start piling up so 1-2C better heat tolerance from looser WR\RTP is most welcome


----------



## The_King

Taraquin said:


> Raising WR\RTP to 14\7 from 10\5 helped a bit. First error occured at 42.6C now, with tighter WR\RTP it always occured at 41-41.5C. Second error came at 44C, usually at 43C or above the start piling up so 1-2C better heat tolerance from looser WR\RTP is most welcome
> View attachment 2588612


I was going to suggest other settings to try as well. WR/RTP does not always have to be half. 10/8 even 12/8 can work.

If you run RTP at 8 then you can try TRAS 22 RC 36. May get instant errors though but that formula works well on my current 3867MT and 3933MT setup with RCD 15/16, these pass 25 cycles TM5.

Maybe try with WTRS at 4. (Also try doing a run with a higher TRFC has that can also help with temps issues)


----------



## 67091

GhOsT662 said:


> Are your tphyrdl all at 26?


Yes


----------



## Taraquin

Artylol said:


> Your voltage is quite low, I can't push tRCD 14 even at 1.54V. I don't have temperature sensor on DIMM, but I'm pushing to 50s


That also helped, 47C before error occured now so 4.5C better vs previous changes. Thanks mate. Testing RAS 27, RC 41, RFC 248 now, maybe more headroom with a bit more voltage  As for voltages Gigabyte has variable voltage so now at 1.53V it varies between 1.536 and 1.56V, same at 1.51V, varied between 1.508V and 1.528V, wish they had kept it more stable like Asus does.


----------



## Taraquin

A bit tighter, but still stable


----------



## GhOsT662

angushades said:


> Yes




Nice, when I start with gear down mode off and command rate 1t with addrcmdsetup at 56 I have the tphyrdl at 26 on some slots and 28 on other slots, while with gear down mode on and command rate 1t or tphyrdl at 26 on all the slots this with a 4×8gb patriot 4000 cl16 1.45 configuration brought to 3733 cl14 1.5 on an asus x470f, I also tried to bring the soc slightly above 1.1 and the vddp cldo to 0.910 but I can't get the tphyrdl to start the same on all slots.


----------



## Artylol

I experience errors at 1.51VDIMM, 1.53V gives error 12 at the very start, 1.54 is error free. What I can try to tweak to reduce voltage?


----------



## Nd4spdvn

Artylol said:


> What I can try to tweak to reduce voltage?


One approach before changing any timings would be to bin the sticks between themselves to know their capabilities but learn also mobo's. On my Giga B550 Aorus Pro V2 I found the B2 slot to be the strongest i.e. it allowed the lowest voltage on any of my dimms. Or simply switch the dimms around and see if you get away with less voltage and/or better stability.


----------



## Taraquin

Artylol said:


> View attachment 2588622
> 
> I experience errors at 1.51VDIMM, 1.53V gives error 12 at the very start, 1.54 is error free. What I can try to tweak to reduce voltage?


Not sure if it`s possible, RttPark 7 and 32 or 28 ProcODT may make a difference, but probably not. Is it not possible to run RCDRD 15?


----------



## The_King

Artylol said:


> View attachment 2588622
> 
> I experience errors at 1.51VDIMM, 1.53V gives error 12 at the very start, 1.54 is error free. What I can try to tweak to reduce voltage?


Those should be some really great bin Samsung B-die DIMMS. SCLs should never be at 2 when you have not fully tuned primary and sub timings yet.

I am surprised you having difficulty with such loose RCDRD timings. That Kit is rated 4000 CL16-16-16.

You should be doing 3800 CL14-14-14 with that VDIMM.

How did you get to that number for RC? Your *DrvStr also look off for GDM disabled 1T. That could be causing you a lot of issues.


----------



## Artylol

Quite a response guys, I will give more background:

I run NH-D15 in Lancool 2 mesh case. It make DIMM closer to D15 very hot and other quite cold (based on touching them)
I effortlessly run 1T stock, I effortlessly run 1T with random ProcODT and RTT downloaded from this forum and literally every combination I tried. I just tried 1T once first booted into XMP4000 and don't experienced issues
I run 4000CL16 flat with tight timings effortlessly @ 1.45 VDIMM
I run 3600CL14 flat with tight timings effortlessly @ 1.45 VDIMM
I run 3666CL14 flat with tight timings barely @ 1.50 VDIMM
In order to reach 3800CL14 I need to raise voltage considerably, but tRCD=14 seems unachievable.
tRCD seems to be the culprit, but I think I run too high voltages, so I thought maybe there is recommendation for terminations to reduce voltages. I also cant find information which terminations can reduce temperature.



Taraquin said:


> Not sure if it`s possible, RttPark 7 and 32 or 28 ProcODT may make a difference, but probably not. Is it not possible to run RCDRD 15?


procODT 28 gives PHYRDL 28\26. Did not tried yet RCD15, but 3600flat15 does not boot, while 3600flat14 boots effortlessly



The_King said:


> Those should be some really great bin Samsung B-die DIMMS. SCLs should never be at 2 when you have not fully tuned primary and sub timings yet.
> 
> I am surprised you having difficulty with such loose RCDRD timings. That Kit is rated 4000 CL16-16-16.
> 
> You should be doing 3800 CL14-14-14 with that VDIMM.
> 
> How did you get to that number for RC? Your *DrvStr also look off for GDM disabled 1T. That could be causing you a lot of issues.


Will try to reduce SCL's. But 4000RCD16=8ns, while 3800RCD14=7.37ns, So I'm not suprised I need more voltage than stock 1.45
What drvstr you recommend and what it can change?


----------



## The_King

Artylol said:


> Quite a response guys, I will give more background:
> 
> I run NH-D15 in Lancool 2 mesh case. It make DIMM closer to D15 very hot and other quite cold (based on touching them)
> I effortlessly run 1T stock, I effortlessly run 1T with random ProcODT and RTT downloaded from this forum and literally every combination I tried. I just tried 1T once first booted into XMP4000 and don't experienced issues
> I run 4000CL16 flat with tight timings effortlessly @ 1.45 VDIMM
> I run 3600CL14 flat with tight timings effortlessly @ 1.45 VDIMM
> I run 3666CL14 flat with tight timings barely @ 1.50 VDIMM
> In order to reach 3800CL14 I need to raise voltage considerably, but tRCD=14 seems unachievable.
> tRCD seems to be the culprit, but I think I run too high voltages, so I thought maybe there is recommendation for terminations to reduce voltages. I also cant find information which terminations can reduce temperature.
> 
> 
> procODT 28 gives PHYRDL 28\26. Did not tried yet RCD15, but 3600flat15 does not boot, while 3600flat14 boots effortlessly
> 
> 
> Will try to reduce SCL's. But 4000RCD16=8ns, while 3800RCD14=7.37ns, So I'm not suprised I need more voltage than stock 1.45
> What drvstr you recommend and what it can change?


It can vary between DIMM and Mobo.

Best to start with the traditional 40 20 24 24 and see if it helps or not.
Usually GDM Disabled 1T requires some increase in ClkDrvStr it can be anywhere between 30-60 range. Have to test what works for your board and Dimms.

Both SCLs to 4.

If you want you can also try 3800 CL15-15-15-30-45 with 1.45V and see if that works with above changes. I can run this on all my Patriot Viper Kits.

Then drop to CL14 and lastly test with RCDRD 14. Try to keep RC = TRP+TRAS until its stable.

@Bloax also gave some great info on these DIMMS here that maybe useful.








Any difference between Patriot Viper Steel 4000 and 4400...


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www.overclock.net


----------



## Nd4spdvn

The_King said:


> Then drop to CL14 and lastly test with RCDRD 14.


I would do it the other way around. Drop to RCDRD14 as that is the major performance impact, stabilize that and only then move to CL14 if spare room remains (voltage/heat). It worked for me on my 4400 Vipers at 1.51V with no cooling in an open bench. Moving to CL14 at the end revealed a too much voltage increase to worth it as it could start inducing all sort of heat related errors. So, 15-14-14-14-24-38 is something to pursuit as an alternative.


----------



## Taraquin

The_King said:


> I was going to suggest other settings to try as well. WR/RTP does not always have to be half. 10/8 even 12/8 can work.
> 
> If you run RTP at 8 then you can try TRAS 22 RC 36. May get instant errors though but that formula works well on my current 3867MT and 3933MT setup with RCD 15/16, these pass 25 cycles TM5.
> 
> Maybe try with WTRS at 4. (Also try doing a run with a higher TRFC has that can also help with temps issues)
> View attachment 2588613


Trying RAS 24, RC 38 now. 47-48C before errors occur is good enough for me, I never reach those temps during gaming


----------



## Netblock

Imprezzion said:


> 1T GDM Off works up to 3800 with AddrCmdSetup 56 and ClkDrvStr 40-24-24-20 but I have never been able to stabilize it above 3800 regardless of bus or str settings. Always throws error 6 and 12 within minutes.


ClkDrvStr--raising the drive impedance to the CK_s and CK_t pins might be a poor way to get GDM off. Furthermore, An addrCmdSetup of a tSetup bias often does not like a ClkDrvStr with a high impedance.

Mess with CsODT (which affects the chipselect and ODT pins) will help because you're multi-rank. (Academically stated, you won't get anything out of the ODT pin because you can't use RTT_Nom, as you don't have more than one DIMM per channel.)

You shouldn't get anything much (if anything at all) from messing with CKE as you're not sleeping the computer or PowerDown.

You might also need to loosen some timing a little as GDM being on can mask some instability or bring instability in odd places; I suggest to kick everything loose by a couple ticks retighten around GDM off. For example, I lost 2 ticks of tRC (57->59) between GDM on and GDM off.

Raise the VDDP too. Also VDDP needs a cold boot to apply (turn off the computer and leave the computer off for 5 seconds).


If I'm saying something new to you, check out my link; I am very certain you can get GDM off as I got GDM off on a much more difficult setup than yours. (Touching just AddrCmdSetup and ClkDrvStr was no where near good enough for my hardware).

You might spend a lot of time attacking it, as it took me something closer to 100 hours learning about what stuff does and getting GDM off. Though that said, I don't suggest attacking it for performance by itself cause the amount of performance-per-effort is the closest to 0 you'll ever see; there needs to be a strong subjective draw to it.


----------



## craghorn

Hi guys!
Can you help me stabilize it?)
Only 2 errors left in absolut testing
Ryzen 5800x
Micron aes e-die dual rank 2x16gb (balliistrix lt red)
mobo gigabyte b550 pro ac


----------



## PJVol

Luggage said:


> Ok something is funky >_>
> Stock 140A doesn't show so much but "eco" 90A drops effective clock like a stone, but raises "freq" and runs hotter?!? Still the limit doesn't show up...


Can you make the same tests, e.g. 2-3 runs resp. of LinpackX "2>5>1>Y>Y>N" is enough, but using the build below for monitoring (a button in the "Limits" tab) ?


----------



## Netblock

craghorn said:


> Hi guys!
> Can you help me stabilize it?)
> Only 2 errors left in absolut testing
> Ryzen 5800x
> Micron aes e-die dual rank 2x16gb (balliistrix lt red)
> mobo gigabyte b550 pro ac
> View attachment 2588659


(forenote, I'd look for a different stress test or different TM5 config that will error faster, cause waiting over 2 hours for the error is not going to be fun. OCCT, y-cruncher, P95, TM5 Extreme, TM5 PCBDestroyer?)

Raise tRCDRD to 21; and tRC to 60. Everything else looks pretty innocent. If it helps, I suggest lowering tRC back down first.

Raise SOC; you might need a tad higher; I'd be surprised if you need more than 1.15 volts SOC.


If raising those doesn't address, I'd attack ProcODT and CAD BUS. 500 series boards tend to like 40 ohms and lower for ProcODT; though there are exceptions to this heuristic. If ProcODT isn't helping, I suggest DrvStr 20-30-30-24 and 56-56-0 Setup. If DrvStr/Setup helps, the values I suggested are very cookie-cutter, so it's likely you'll be able to find something far better.


----------



## craghorn

Netblock said:


> (forenote, I'd look for a different stress test or different TM5 config that will error faster, cause waiting over 2 hours for the error is not going to be fun. OCCT, y-cruncher, P95, TM5 Extreme, TM5 PCBDestroyer?)
> 
> Raise tRCDRD to 21; and tRC to 60. Everything else looks pretty innocent. If it helps, I suggest lowering tRC back down first.
> 
> Raise SOC; you might need a tad higher; I'd be surprised if you need more than 1.15 volts SOC.
> 
> 
> If raising those doesn't address, I'd attack ProcODT and CAD BUS. 500 series boards tend to like 40 ohms and lower for ProcODT; though there are exceptions to this heuristic. If ProcODT isn't helping, I suggest DrvStr 20-30-30-24 and 56-56-0 Setup. If DrvStr/Setup helps, the values I suggested are very cookie-cutter, so it's likely you'll be able to find something far better.


Thank you, ive run different items, prime + vram tests ooct, tm5 1usmus and anta777 extreme configs, all passes good with thoose settings.
But this test throw errors(
I will try your suggestion ^^


----------



## Imprezzion

Netblock said:


> ClkDrvStr--raising the drive impedance to the CK_s and CK_t pins might be a poor way to get GDM off. Furthermore, An addrCmdSetup of a tSetup bias often does not like a ClkDrvStr with a high impedance.
> 
> Mess with CsODT (which affects the chipselect and ODT pins) will help because you're multi-rank. (Academically stated, you won't get anything out of the ODT pin because you can't use RTT_Nom, as you don't have more than one DIMM per channel.)
> 
> You shouldn't get anything much (if anything at all) from messing with CKE as you're not sleeping the computer or PowerDown.
> 
> You might also need to loosen some timing a little as GDM being on can mask some instability or bring instability in odd places; I suggest to kick everything loose by a couple ticks retighten around GDM off. For example, I lost 2 ticks of tRC (57->59) between GDM on and GDM off.
> 
> Raise the VDDP too. Also VDDP needs a cold boot to apply (turn off the computer and leave the computer off for 5 seconds).
> 
> 
> If I'm saying something new to you, check out my link; I am very certain you can get GDM off as I got GDM off on a much more difficult setup than yours. (Touching just AddrCmdSetup and ClkDrvStr was no where near good enough for my hardware).
> 
> You might spend a lot of time attacking it, as it took me something closer to 100 hours learning about what stuff does and getting GDM off. Though that said, I don't suggest attacking it for performance by itself cause the amount of performance-per-effort is the closest to 0 you'll ever see; there needs to be a strong subjective draw to it.


Well, this is quite literally the first time I have ever made it into Windows on 1T GDM Off on 3933 after spending several hours of trying different combinations of ProcODT, Setup's, DrvStr's and RTT's. Now lets see how stable it is. At least it let me type this message lol. I'd give TM5 1usmus about 40 seconds.. lol.

I cannot go any lower then 40 ClkDrvStr. Anything lower won't even POST. Maybe i'll actually need even way higher then this like 60 for it to actually run stable. We'll see.


----------



## Luggage

PJVol said:


> Can you make the same tests, e.g. 2-3 runs resp. of LinpackX "2>5>1>Y>Y>N" is enough, but using the build below for monitoring (a button in the "Limits" tab) ?


Very nice monitor 
Well I got caught up in it when I noticed PPT and TDC start limiting clocks earlier, before hitting the limit than I thought... but they are secondary anyway.

Still the behavior is the same - with an EDC limit effective clocks and performance takes a dive while "clocks" go up and for some reason temps go up as well.



http://imgur.com/a/hoVrN0V


Edit: can you @ in an edit?
@ManniX-ITA @Veii 
New toys  what’s up with the clock stretching and especially the higher temps at low EDC?


----------



## Netblock

Imprezzion said:


> different combinations of ProcODT, Setup's, DrvStr's and RTT's


As a note, for the setups 63->32 increasingly helps tSetup by hurting tHold; and 1->31 increasingly helps tHold by hurting tSetup. A value of 50 is more potent than 56. I have more detail here (relink).

It is worth walking the the AMD Setups in both directions and see how far you go. For example, here's some notes of an 1DPC A320 board with dual-rank DIMMs I was playing with earlier:



Code:


AddrCmdSetup-CsODTSetup-CkeSetup
50-45-50? boot
45-45-50? boot
40-40-50? no boot
43-45-50? boot
41-45-50? no boot
48-42-50? boot
48-40-50? boot
48-38-50? boot
48-36-50? boot
48-34-50? boot; firmware crash

I think settled for 48-42-50.


----------



## Blameless

Netblock said:


> Furthermore, An addrCmdSetup of a tSetup bias often does not like a ClkDrvStr with a high impedance.


A higher impedance on the output drive strength is a weaker drive strength and in my experience matches up well with a delayed setup time (where setup, rather than hold violations are the issue). I run 60 ohms on ClkDrvStr because it's what's proven to handle high DIMM temp best on my current dual-rank B-die kit.



Netblock said:


> (forenote, I'd look for a different stress test or different TM5 config that will error faster, cause waiting over 2 hours for the error is not going to be fun. OCCT, y-cruncher, P95, TM5 Extreme, TM5 PCBDestroyer?)


When dialing in my possibly final timings, TM5 custom 1usmus or anta where the only tests I could get to throw any errors and the mean time between errors was more than ten hours.


----------



## Netblock

Blameless said:


> A higher impedance on the output drive strength is a weaker drive strength and in my experience matches up well with a delayed setup time (where setup, rather than hold violations are the issue). I run 60 ohms on ClkDrvStr because it's what's proven to handle high DIMM temp best on my current dual-rank B-die kit.


Are you saying that a hi-impedance ClkDrvStr works well with a AddrCmdSetup that favors tHold (1->31)? I hypothesised this, but I also haven't seen many systems that asks for a tHold bias for AddrCmdSetup.

Very few people actually play with this stuff.




Blameless said:


> When dialing in my possibly final timings, TM5 custom 1usmus or anta where the only tests I could get to throw any errors and the mean time between errors was more than ten hours.


P95 Large, and TM5 PCBDestroyer seem to get angry the most when I messed with the command-address bus stuff. Y-cruncher "FFT" test also sometimes did something quick.


----------



## Imprezzion

Yeah well it did about 5 seconds of TM5 1usmus before spitting out numerous error 6's and a few 12's. While I can boot 1T GDM Off now it's horrifically unstable. I'll keep on tweaking stuff after work tho. I'm determined to get it to work now haha.


----------



## The_King

Imprezzion said:


> Yeah well it did about 5 seconds of TM5 1usmus before spitting out numerous error 6's and a few 12's. While I can boot 1T GDM Off now it's horrifically unstable. I'll keep on tweaking stuff after work tho. I'm determined to get it to work now haha.


When was the last time you swapped your DIMMs around? 









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Those that have B-die have better latency om AMD, by far. Also we that run 5800X3D have higher latency (5-6ns more) because of the 3d cache. So for me with Micron + 5800X3D is kinda meh in terms of latency There are two factors that can bring latency down in AIDA64. 1 is increase MT frequency...




www.overclock.net





Pro-tip thanks to @ManniX-ITA use a Q-tip cotton bud to clean the contact pins on the DIMMS can sometimes make a big difference as well.


----------



## Imprezzion

The_King said:


> When was the last time you swapped your DIMMs around?
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Those that have B-die have better latency om AMD, by far. Also we that run 5800X3D have higher latency (5-6ns more) because of the 3d cache. So for me with Micron + 5800X3D is kinda meh in terms of latency There are two factors that can bring latency down in AIDA64. 1 is increase MT frequency...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> Pro-tip thanks to @ManniX-ITA use a Q-tip cotton bud to clean the contact pins on the DIMMS can sometimes make a big difference as well.


Well, since I put this motherboard in lol. They are very hard to get at due to tubing and the Dominator cooler on them. I don't really have room to remove the cooler without pulling at least the GPU out and making room with the tubing.


----------



## Blameless

Netblock said:


> Are you saying that a hi-impedance ClkDrvStr works well with a AddrCmdSetup that favors tHold (1->31)? I hypothesised this, but I also haven't seen many systems that asks for a tHold bias for AddrCmdSetup.


None of the memory I've tried seems to favor tHold. Increasing the margin for tSetup (the oft recommended 56 and close to it) does seem to let me use a higher ClkDrv impedance, which in turn seems to either reduce temperature or allow a higher temperature tolerance. Not sure if this is due to the lower drive strength itself, the slower rise of the setup enabling the lower drive strength to work, the total delay to the clock signal itself, or none of the above. Just an observation for my specfic scenario (dual-rank Team T-Create B-die in a toasty SFF setup).



Netblock said:


> Very few people actually play with this stuff.


Not surprising, there isn't a lot of clear information on it's implications and the setting is often inscrutable if all one has is trial and error to go by. A small adjustment is often the difference between as stable as can be and needing to clear the bios setting to get the board to POST.



Netblock said:


> P95 Large, and TM5 PCBDestroyer seem to get angry the most when I messed with the command-address bus stuff. Y-cruncher "FFT" test also sometimes did something quick.


Temperature has been my main limiting factor, rather than intrinsic timing instabilities.


----------



## Artylol

The_King said:


> It can vary between DIMM and Mobo.
> 
> Best to start with the traditional 40 20 24 24 and see if it helps or not.
> Usually GDM Disabled 1T requires some increase in ClkDrvStr it can be anywhere between 30-60 range. Have to test what works for your board and Dimms.
> 
> Both SCLs to 4.
> 
> If you want you can also try 3800 CL15-15-15-30-45 with 1.45V and see if that works with above changes. I can run this on all my Patriot Viper Kits.
> 
> Then drop to CL14 and lastly test with RCDRD 14. Try to keep RC = TRP+TRAS until its stable.
> 
> @Bloax also gave some great info on these DIMMS here that maybe useful.
> 
> 
> 
> 
> 
> 
> 
> 
> Any difference between Patriot Viper Steel 4000 and 4400...
> 
> 
> Has the title says is there any other difference between : Patriot Viper Steel Series DDR4 16GB (2 x 8GB) 4400MHz Performance Memory Kit (PVS416G440C9K) https://www.amazon.in/gp/product/B07KXLFDL6/ref=ox_sc_saved_title_10?smid=A14CZOWI0VEHLG&psc=1 Patriot Memory Viper Steel DDR4 16GB (2 x...
> 
> 
> 
> 
> www.overclock.net





The_King said:


> It can vary between DIMM and Mobo.
> 
> Best to start with the traditional 40 20 24 24 and see if it helps or not.
> Usually GDM Disabled 1T requires some increase in ClkDrvStr it can be anywhere between 30-60 range. Have to test what works for your board and Dimms.
> 
> Both SCLs to 4.
> 
> If you want you can also try 3800 CL15-15-15-30-45 with 1.45V and see if that works with above changes. I can run this on all my Patriot Viper Kits.
> 
> Then drop to CL14 and lastly test with RCDRD 14. Try to keep RC = TRP+TRAS until its stable.
> 
> @Bloax also gave some great info on these DIMMS here that maybe useful.
> 
> 
> 
> 
> 
> 
> 
> 
> Any difference between Patriot Viper Steel 4000 and 4400...
> 
> 
> Has the title says is there any other difference between : Patriot Viper Steel Series DDR4 16GB (2 x 8GB) 4400MHz Performance Memory Kit (PVS416G440C9K) https://www.amazon.in/gp/product/B07KXLFDL6/ref=ox_sc_saved_title_10?smid=A14CZOWI0VEHLG&psc=1 Patriot Memory Viper Steel DDR4 16GB (2 x...
> 
> 
> 
> 
> www.overclock.net


ъ
thanks it works. It does not boot 1.54V auto ClkDrvStr, easily boots 1.45V at settings below


----------



## Taraquin

Artylol said:


> ъ
> thanks it works. It does not boot 1.54V auto ClkDrvStr, easily boots 1.45V at settings below
> View attachment 2588793


Stable now? Try tightening RRD/FAW and RFC now 

My avg binned Viper 4400 can do at 1.48v:
3800 
15 15 15
27
42
4/4/16
WTR 3/8
WR 10
RFC 264
SCL 4/4
CWL 14
RTP 5
RDWR 8
WRRD 1
CKE 11

20 20 20 20 1t gdm off works, my 3200 FlareX needs 40 20 30 20 at flat 14 at 1.51v.
ProcODT 28, disable/disable/RttPark 7

It seems your ram is closer to my FlareX kit which is picky on DrvStr, but needs less voltage than Vipers.


----------



## Artylol

Taraquin said:


> Stable now? Try tightening RRD/FAW and RFC now
> 
> My avg binned Viper 4400 can do at 1.48v:
> 3800
> 15 15 15
> 27
> 42
> 4/4/16
> WTR 3/8
> WR 10
> RFC 264
> SCL 4/4
> CWL 14
> RTP 5
> RDWR 8
> WRRD 1
> CKE 11
> 
> 20 20 20 20 1t gdm off works, my 3200 FlareX needs 40 20 30 20 at flat 14 at 1.51v.
> ProcODT 28, disable/disable/RttPark 7
> 
> It seems your ram is closer to my FlareX kit which is picky on DrvStr, but needs less voltage than Vipers.


Not sure about pickiness, my ram just does not care about settings of procODT and DrvStr at 7.8-8ns, it just swallows everything. But below that we see that it wants some stabilization.

I think I will achieve 14flat first, then tighten timings. As far as I know, it tightens all tertiaries without effort. I'm currently testing 3800 14-14-15-30-45 so cl and rcd are 14


----------



## Imprezzion

I'm still running into weird latency issues. 3933 16-16-16-36-52-272-2T GDM Off (1.450v) has 59.5-59.8ns which is normal for that speed. Dropping to 15-15-15-30-45-256-2T (1.52v) has 58.7-59.1ns which is also expected and scales properly.

3800 14-15-14-28-42-256-1T GDM Off (1.56v) has like 63.7-64.1ns. Makes no sense. It should be way faster. On the older 1.2.0.7 BIOS without the PBO settings I had that exact 3800 profile, I have screenshots of all the timings and voltages saved, as daily and it did like 57.2-57.5ns.

I even tested with a "suicide" run stable enough to run benches @ 1.68v 3733 13-14-13-21-40-240-1T GDM Off with stuff like tWR 10, tCWL 12, tWTR 7/3, tWRRD and tRDWR 7/2 and such and it still ran high 62's. Write speed is completely out of whack as well. On 3933 it's 314xx which is what it should be, on 3800 it's 292xx which is way too low and on 3733 it's 281xx which is also too low. Again on the older BIOS 3800 also did 31xxx fine. Something is not right with this BIOS...


----------



## Artylol

Imprezzion said:


> I'm still running into weird latency issues. 3933 16-16-16-36-52-272-2T GDM Off (1.450v) has 59.5-59.8ns which is normal for that speed. Dropping to 15-15-15-30-45-256-2T (1.52v) has 58.7-59.1ns which is also expected and scales properly.
> 
> 3800 14-15-14-28-42-256-1T GDM Off (1.56v) has like 63.7-64.1ns. Makes no sense. It should be way faster. On the older 1.2.0.7 BIOS without the PBO settings I had that exact 3800 profile, I have screenshots of all the timings and voltages saved, as daily and it did like 57.2-57.5ns.
> 
> I even tested with a "suicide" run stable enough to run benches @ 1.68v 3733 13-14-13-21-40-240-1T GDM Off with stuff like tWR 10, tCWL 12, tWTR 7/3, tWRRD and tRDWR 7/2 and such and it still ran high 62's. Write speed is completely out of whack as well. On 3933 it's 314xx which is what it should be, on 3800 it's 292xx which is way too low and on 3733 it's 281xx which is also too low. Again on the older BIOS 3800 also did 31xxx fine. Something is not right with this BIOS...


You sure you are 1:1:1 synced? Check in zentimings, because writes suggest you are not


----------



## Imprezzion

Artylol said:


> You sure you are 1:1:1 synced? Check in zentimings, because writes suggest you are not


I only checked FCLK and that was 1:1 but maybe UCLK or MCLK was out of sync. You might be right.. I'm at work now but I'll double-check tonight. I got the profiles saved in the BIOS so I can swap between them easy enough.


----------



## Netblock

Blameless said:


> Temperature has been my main limiting factor, rather than intrinsic timing instabilities.


DrvStr/Setup helping suggests that temperature-based noise on the buses are non-trivial. That the traces are gaining a significant impedance, and/or the terminations' impedances are drifting away from what they're calibrated to, for the worse.

I wonder if this is what is actually meant when people day 'tRCDRD is hard on the memory controller'.


----------



## Luggage

Netblock said:


> DrvStr/Setup helping suggests that temperature-based noise on the buses are non-trivial. That the traces are gaining a significant impedance, and/or the terminations' impedances are drifting away from what they're calibrated to, for the worse.
> 
> I wonder if this is what is actually meant when people day 'tRCDRD is hard on the memory controller'.


I remember mentions about tRCDRD being more limited by the RAM PCB than anything else but I can't remember who said it... Veii perhaps?


----------



## Mr.Sunshine

How many cycles of TM5 do you consider stable? I've been testing and I can get to 15hrs(120cycles) before a random 15 error. could that be heat related?


----------



## Mr.Sunshine

.


----------



## SneakySloth

Mr.Sunshine said:


> How many cycles of TM5 do you consider stable? I've been testing and I can get to 15hrs(120cycles) before a random 15 error. could that be heat related?


I had something similar happen when I was testing for extended periods of time. In my case I had to slightly loosen some of the timings and adjust RTT/Proc a little.


----------



## ManniX-ITA

Mr.Sunshine said:


> How many cycles of TM5 do you consider stable? I've been testing and I can get to 15hrs(120cycles) before a random 15 error. could that be heat related?


Can be literally anything, can be heat related.
Most common in my experience tightening B-die is tRFC borderline unstable.


----------



## Mr.Sunshine

ManniX-ITA said:


> Can be literally anything, can be heat related.
> Most common in my experience tightening B-die is tRFC borderline unstable.


That is one of the timings I changed. Testing again now.
Was 240-178-110 Failed at 15hr 26min
Now 246-183-113 at 16hr 23min stable so far.


----------



## Imprezzion

Mr.Sunshine said:


> That is one of the timings I changed. Testing again now.
> Was 240-178-110 Failed at 15hr 26min
> Now 246-183-113 at 16hr 23min stable so far.


I consider 5h to be stable enough for daily gaming usage. 

@Artylol you were right. It didn't do the UCLK properly on Auto so write is now in the 31xxx again for 3800 but latency is still terrible. High 60's low 61's on 3800 14-15-14-28-42-256-1T GDM Off. Still way worse then even 3933 16-16-16-36-52-272-2T. It's weird but I don't wanna roll back the BIOS tbh. 

I guess I'll stick to trying to get 3933 15-15-15-30-45-256-2T GDM Off to run stable. I'm almost there. 1.520v vDIMM survived a 5h run but I had the secondary and tertiary timings quite loose. Going to retest with tighter tWR, tRTP, tWTR, tWRRD and tRDWR again. If that passes I might try 15-15-15-25-40.


----------



## Artylol

Imprezzion said:


> I consider 5h to be stable enough for daily gaming usage.
> 
> @Artylol you were right. It didn't do the UCLK properly on Auto so write is now in the 31xxx again for 3800 but latency is still terrible. High 60's low 61's on 3800 14-15-14-28-42-256-1T GDM Off. Still way worse then even 3933 16-16-16-36-52-272-2T. It's weird but I don't wanna roll back the BIOS tbh.
> 
> I guess I'll stick to trying to get 3933 15-15-15-30-45-256-2T GDM Off to run stable. I'm almost there. 1.520v vDIMM survived a 5h run but I had the secondary and tertiary timings quite loose. Going to retest with tighter tWR, tRTP, tWTR, tWRRD and tRDWR again. If that passes I might try 15-15-15-25-40.


So you are gaining latency on lower timings, right? Maybe you IMC is bottlenecking? Don't you have WHEA errors?
I would try to 
1) find what timings raise latency
2) try feeding IMC with more voltage, or maybe less voltage


----------



## Frosted racquet

PJVol said:


> Can you make the same tests, e.g. 2-3 runs resp. of LinpackX "2>5>1>Y>Y>N" is enough, but using the build below for monitoring (a button in the "Limits" tab) ?


Hi, is this build of PBO2 stable for use on a 5800X3D, with startup commandline enabled? Thanks


----------



## PJVol

Frosted racquet said:


> Hi, is this build of PBO2 stable for use on a 5800X3D, with startup commandline enabled? Thanks


Not sure, what stable implies here, but I just added montoring feature for testing (single CCD cpus so far). Should work as cli as prev builds.


----------



## Imprezzion

About 3.5h into the test I had a error #11, #12, #11 pop up and then it stayed good again till 5.5h into it when I stopped it. Both indicate either voltage or resistance. Temp was steady around 45.5-46c. Should I just raise vDIMM 1 more tick from 1.520 to 1.530? Or slightly drop tRFC maybe? I'm at 256 on 3933 which is pretty much 130ns so maybe I should go to 264/272?


----------



## Artylol

Imprezzion said:


> About 3.5h into the test I had a error #11, #12, #11 pop up and then it stayed good again till 5.5h into it when I stopped it. Both indicate either voltage or resistance. Temp was steady around 45.5-46c. Should I just raise vDIMM 1 more tick from 1.520 to 1.530? Or slightly drop tRFC maybe? I'm at 256 on 3933 which is pretty much 130ns so maybe I should go to 264/272?


I experience same thing. It is temperature related in my opinion and can be countered with +1tick of voltage in most cases.


----------



## Artylol

Ok, so I encountered new issue.

PHYRDL 26/26 on 4000flat16, 3600flat14, 3666flat14, 3733flat14
PHYRDL 28/26 on 3800CL14 (specifically CL 14 pushes PHYRDL, RCD14 works ok)










edit:
interesting observation that someone might useful:

Unstable RAM gives error on start of Y-cruncher. No need to run hour long tests, 1 second and you can go reboot and adjust.
ClkDrvStr 40 in my case gives a lot more stability and less variation in Y-cruncher 25m results.
edit2:
Fixed issue above by raising VSOC, VDDP and both VDDG


----------



## Mikel_Ertz

Hello, need some help plz. Finaly got this settings stable in 1usmusv3 (200 cycles) anta777 extreme 30 cycles and anta777 absolut 30 cycles.

The next thing that I want to try is 3800mhz but i am getting WHEA 19 error. Any way to fix it?

Also, i will test again the stability with this settings but with 1.42


----------



## Jeager

Sorry I wasnt here in the last couple of day, here my export from taiphoon :
-------------------------------------------------------------
MEMORY MODULE
Manufacturer : Galaxy Microsystems
Series : Not determined
Part Number : Undefined
Serial Number : Undefined
JEDEC DIMM Label : 8GB 1Rx8 PC4-2133P-UA0-10
Architecture : DDR4 SDRAM UDIMM
Speed Grade : DDR4-2133P
Capacity  : 8 GB (8 components)
Organization : 1024M x64 (1 rank)
Register Manufacturer : N/A
Register Model : N/A
Manufacturing Date : Undefined
Manufacturing Location : Unknown: 00h
Revision / Raw Card : 0000h / A0 (8 layers)
-------------------------------------------------------------
DRAM COMPONENTS
Manufacturer : Samsung
Part Number : K4A8G085WB-BCPB
Package : Standard Monolithic 78-ball FBGA
Die Density / Count : 8 Gb B-die (Boltzmann / 20 nm) / 1 die
Composition : 1024Mb x8 (64Mb x8 x 16 banks)
Input Clock Frequency : 1067 MHz (0.938 ns)
Minimum Timing Delays : 15-15-15-36-51
Read Latencies Supported : 16T, 15T, 14T
Supply Voltage : 1.20 V
XMP Certified : 1800 MHz / 17-18-18-38-62 / 1.35 V
XMP Extreme : Not programmed
SPD Revision : 1.0 / January 2014
XMP Revision : 2.0 / December 2013









No errors in games and no PBO this time but with vSOC at 1.1v (instead of 1.0875) and tRAS/RC higher with +2 on both


----------



## PJVol

Jeager said:


> here my export from taiphoon


They look identically to mine.


----------



## Jeager

Whats settings are you using without errors ?


----------



## PJVol

24/7 or for the records?


----------



## Jeager

24/7 so i have a good base for my HOF


----------



## PJVol

Jeager said:


> 24/7 so i have a good base for my HOF


----------



## Jeager

A bit better than me but you are with GDM Off and 1.44 vDIMM 
Just got 3 errors after playing for an hour and with my higher voltage I'm not sure If I'll be able to stick at 3800


----------



## PJVol

Jeager said:


> Just got 3 errors after playing for an hour and with my higher voltage I'm not sure If I'll be able to stick at 3800


Not sure i understand, what your goal is.
Anyway, what exactly were the errors you got and what were the CPU settings when the errors occured?
Have you done the thorough RAM testing, i.e. TM5 with a 1usmus or anta preset?


----------



## mirzet1976

I bought myself a memory Viper 4000mhz CL16-16-16-36-52 and left TM5 to test, HWiNFO turned on and when I came back I first noticed a high temperature of 90C and then the rest. Bios settings for PPT-100, EDC-105.


----------



## PJVol

mirzet1976 said:


> and then the rest


This could be the cpu got fed up with those stupid tm5 cycles and decided to pace up a bit.


----------



## Jeager

PJVol said:


> Not sure i understand, what your goal is.
> Anyway, what exactly were the errors you got and what were the CPU settings when the errors occured?
> Have you done the thorough RAM testing, i.e. TM5 with a 1usmus or anta preset?


I'm just trying to have a stable/no WHEA error at 3800 
I'm using y-cruncher not TM5, usualy its have no error except after gaming session


----------



## Imprezzion

What voltage / resistance / whatever in general can fix WHEA in TM5 but not in y-cruncher? It's weird as y-cruncher set to benchmark and then multi thread and then setting 8 is a much much higher load and it doesn't WHEA there but it does in TM5.

I'm testing at 4000 straight 16's 2000 FCLK/UCLK btw. I did have WHEA in y-cruncher at first at 1.15v vSOC 1.10 CCD 1.12 IOD 0.900 VDDP but I raised it to 1.20 vSOC and 0.920 VDDP and they went away but now they are still there in TM5. It is only 2 so far but still.

EDIT: The RAM is perfectly fine with this, 26/26 tPHYRDL as well, but the FCLK isn't yet.. 25 WHEA in 1h testing lol.










EDIT2:

Fixed it. Little more vSOC and 20mv more on the VDDP did it. No more WHEA's in either y-cruncher or TM5. And on -30 the CPU still happily sits at max boost.


----------



## Mr.Sunshine

Imprezzion said:


> What voltage / resistance / whatever in general can fix WHEA in TM5 but not in y-cruncher? It's weird as y-cruncher set to benchmark and then multi thread and then setting 8 is a much much higher load and it doesn't WHEA there but it does in TM5.
> 
> I'm testing at 4000 straight 16's 2000 FCLK/UCLK btw. I did have WHEA in y-cruncher at first at 1.15v vSOC 1.10 CCD 1.12 IOD 0.900 VDDP but I raised it to 1.20 vSOC and 0.920 VDDP and they went away but now they are still there in TM5. It is only 2 so far but still.
> 
> EDIT: The RAM is perfectly fine with this, 26/26 tPHYRDL as well, but the FCLK isn't yet.. 25 WHEA in 1h testing lol.
> 
> View attachment 2589025
> 
> 
> EDIT2:
> 
> Fixed it. Little more vSOC and 20mv more on the VDDP did it. No more WHEA's in either y-cruncher or TM5. And on -30 the CPU still happily sits at max boost.
> 
> View attachment 2589029
> 
> 
> View attachment 2589031


Nice!! Good job. Ive been trying to get past 3800 with good timings stable but to no luck. No mattrer the setting I cant get GDM disable with 1T either.(only 3600) I'm sure it has to do with a few things. Older CPU, x470 T-Topology, 4 dimms filled.


----------



## Mr.Sunshine

This is TM5 24/hr run stable. Any ideas on improving?


----------



## GhOsT662

Mr.Sunshine said:


> View attachment 2589049
> 
> This is TM5 24/hr run stable. Any ideas on improving?




I too have the same motherboard as yours and 2 patriot viper steel kits only that I have the 4000 cl16 1.45 version to try disabling gear dowm mode and have the commad rate 1t try running a procodt between 30 and 40 ohms and rttnom rzq7, rttwr rzq3, and rttpark rzq6 or rzq5 and clkdrvstr at 60ohm, addrcmddrvstr at 20ohm, csodtdrvstr at 30ohm and ckedrvstr at 24ohm you can also try adding to addrcmdsetup 56 to try and boot com 1t gear dowm mode off. Also before doing all this I suggest you downgrade the bios to version 5861 chs it would be agesa 1.2.0.3 patch c as it has better support for overclocking both the cpu as it does not block the edc and the ram the agesa later have a block on the edc due to the 5800x3d


----------



## GhOsT662

Mr.Sunshine said:


> View attachment 2589049
> 
> This is TM5 24/hr run stable. Any ideas on improving?



also try with both scl at 4 and try to start gear dowm mode off and 1t with 3800 cl16 16 16 40 at 1.45 and the rest of the times in automatic and see if it starts and is stable then after start working on the times


----------



## Teussi

What have changed, i did clean win10 install, new bios and new amd chipset drivers, copied my ram settings (same dram vol., iod, vddp etc) and same values and now getting errors on tm5 test. Before "uppgrade" did 50 round tm5 anta error free, now giving 4 errors in 45 min. So, i should now start "again" increasing voltages etc.


----------



## PJVol

Jeager said:


> I'm just trying to have a stable/no WHEA error at 3800


Whea errors (19) usually mean unstable fabric, so they're not about RAM timings. As for the latter, you may try 3800CL16 - negligible loss to CL15 and 1.386V Vdimm


----------



## 99belle99

How did I get such a high write speed? I checked a few scores I had saved from a while back and was getting in and around 30399 but I think I had different timings then.


----------



## N3KKi

Just curious as to how I would set the SOC voltage on my B450 Aorus Pro as it doesn't seem to allow decimals for any of the voltages under AMD Overclocking. Also if I go into the Voltages tab there are only 3 options there and all are offsets not absolutes.

Thanks for any and all help!


----------



## Mr.Sunshine

GhOsT662 said:


> I too have the same motherboard as yours and 2 patriot viper steel kits only that I have the 4000 cl16 1.45 version to try disabling gear dowm mode and have the commad rate 1t try running a procodt between 30 and 40 ohms and rttnom rzq7, rttwr rzq3, and rttpark rzq6 or rzq5 and clkdrvstr at 60ohm, addrcmddrvstr at 20ohm, csodtdrvstr at 30ohm and ckedrvstr at 24ohm you can also try adding to addrcmdsetup 56 to try and boot com 1t gear dowm mode off. Also before doing all this I suggest you downgrade the bios to version 5861 chs it would be agesa 1.2.0.3 patch c as it has better support for overclocking both the cpu as it does not block the edc and the ram the agesa later have a block on the edc due to the 5800x3d


Thanks for the info. Ive never heard about newer BIOS blocking OCing. Would that effect non x3D CPUs? I didnt seem to have any issues. I know awhile back they blocked the EDC bug.


----------



## Imprezzion

Aight so. I fixed the WHEA's completely on 2000 fclk. It turned out I didn't need more vSOC but rather more VDDP. And by quite a lot. 1967 runs fine at 0.900 but for 2000 I had to go all the way to 1.000 to keep them away. This setup really comes into it's own with 4000 straight 16's and tight subtimings with 2000 FCLK UCLK MCLK 1:1. I'm actually getting into the 57's now for latency with the X3D which is really good.
I'm at 1.20v vSOC 1.120 CCD 1.140 IOD 1.000 VDDP at 32ohm ProcODT.


----------



## GhOsT662

Mr.Sunshine said:


> Thanks for the info. Ive never heard about newer BIOS blocking OCing. Would that effect non x3D CPUs? I didnt seem to have any issues. I know awhile back they blocked the EDC bug.



the agesa following 1.2.0.3 blocks the edc at 140 so you can't go beyond the 1.4/1.425v with the pbo so basically the single cores are a bit castrated this is said to be due to the fact that the 5800x3ds are sensitive at the upper voltage of 1.35v due to how the cache is set up I also read that they have problems with frequencies over 3800 even if on ryzens going over 3800 stable without whea is a fortune of the silicon lottery even if the cpu with a single ccd for example the 5600x or the 5800x have a few more chances of being able to exceed the 3800


----------



## Artylol

GhOsT662 said:


> the agesa following 1.2.0.3 blocks the edc at 140 so you can't go beyond the 1.4/1.425v with the pbo so basically the single cores are a bit castrated this is said to be due to the fact that the 5800x3ds are sensitive at the upper voltage of 1.35v due to how the cache is set up I also read that they have problems with frequencies over 3800 even if on ryzens going over 3800 stable without whea is a fortune of the silicon lottery even if the cpu with a single ccd for example the 5600x or the 5800x have a few more chances of being able to exceed the 3800


I have 5600(non x) on 1207 AGESA, with CO -30 I run cinebench at [email protected] all core (maximum PBO frequency on this chip). Will I benefit from downgrading to 1203?

Without CO -30, EDC maxes out at 125A, and no setting allows to pass that. Will I be able to set higher EDC on 1203?

By the way, in more intensive tasks than CB, like Y-cruncher, clocks are way lower even though I don't reach Any limit of PBO.


----------



## The_King

Before DIMM swap. Had to use ACS-56.









After DIMM swap. Only 3 cycles but now no ACS-56 real 1T









Having random error issues with 3933 CL15.  @Veii Anyway to get this stable without loosing latency on even making it go into the high 50s?


----------



## GhOsT662

Artylol said:


> I have 5600(non x) on 1207 AGESA, with CO -30 I run cinebench at [email protected] all core (maximum PBO frequency on this chip). Will I benefit from downgrading to 1203?
> 
> Without CO -30, EDC maxes out at 125A, and no setting allows to pass that. Will I be able to set higher EDC on 1203?
> 
> By the way, in more intensive tasks than CB, like Y-cruncher, clocks are way lower even though I don't reach Any limit of PBO.


You could do a quick and dirty test by downloading pbo tuner from github to see if it gets any benefit playing with ppt tdc and edc as you set the values from windows and not from bios and this allows you to bypass the pbo bug.

This instead is the link where I had read the news of the agesa who had introduced this behavior on the pbo.


__
https://www.reddit.com/r/Amd/comments/vecyn6


----------



## The_King

GhOsT662 said:


> You could do a quick and dirty test by downloading pbo tuner from github to see if it gets any benefit playing with ppt tdc and edc as you set the values from windows and not from bios and this allows you to bypass the pbo bug.
> 
> This instead is the link where I had read the news of the agesa who had introduced this behavior on the pbo.
> 
> 
> __
> https://www.reddit.com/r/Amd/comments/vecyn6


I am running 1.2.0.7 and Lowering EDC increases my R23 score.


----------



## GhOsT662

The_King said:


> I am running 1.2.0.7 and Lowering EDC increases my R23 score.
> View attachment 2589233
> 
> View attachment 2589234
> 
> View attachment 2589235



Well yes actually there is also to consider that each chip of the 5000 family has a sweet spoot of the ppt tdc and edc values which varies from processor to processor


----------



## Luggage

GhOsT662 said:


> Well yes actually there is also to consider that each chip of the 5000 family has a sweet spoot of the ppt tdc and edc values which varies from processor to processor


And workload to workload. R23 wants modest tdc and edc but a bit raised ppt. Heavy stuff like p95, linx, yc can use much higher limits if you can cool it. Cpu-z on the other hand wants really low limits to boost high…

Most games I would consider to be reasonably light workloads.


----------



## LicSqualo

(double post)


----------



## LicSqualo

Finally, reached a stable configuration with GDM OFF and 1T at 3800/1900 with 5800X3D (arrived 10 day ago and switched from my "old" 1700) on C6H/x370 with a pair of sammy b-die 3600c16.
Thanks to all you guys in the thread for the suggestions, the last one (with the RTT solution) was THE KING (really thanks!) with the RTT section on the last images.
View attachment 2589251


This is the proof (thanks also to TRFc Mini -and Veii- to make suggestion for the stability)











Any advice?


----------



## Jeager

PJVol said:


> Whea errors (19) usually mean unstable fabric, so they're not about RAM timings. As for the latter, you may try 3800CL16 - negligible loss to CL15 and 1.386V Vdimm


Ok ! The last couple of days I only had one error per day (I stop/restart computer every day) at 1900 (even with vSOC at 1.0v). This seems strange, can it be related to voltage drop ? Originaly no LLC option on my motherboard but since v7 bios option is available but doesnt seem to work ?
Another thing, I cannot change my vDDG CCD/IOD voltage (they stay at 0.99 what ever I put here )


----------



## The_King

LicSqualo said:


> Finally, reached a stable configuration with GDM OFF and 1T at 3800/1900 with 5800X3D (arrived 10 day ago and switched from my "old" 1700) on C6H/x370 with a pair of sammy b-die 3600c16.
> Thanks to all you guys in the thread for the suggestions, the last one (with the RTT solution) was THE KING (really thanks!) with the RTT section on the last images.
> View attachment 2589251
> 
> 
> This is the proof (thanks also to TRFc Mini -and Veii- to make suggestion for the stability)
> 
> View attachment 2589252
> 
> 
> 
> Any advice?


You can try dropping WTRL 10 even 8 and also try with RDWR 9.

Probably best to test each change 1 at a time so you know if it stable.



Jeager said:


> Ok ! The last couple of days I only had one error per day (I stop/restart computer every day) at 1900 (even with vSOC at 1.0v). This seems strange, can it be related to voltage drop ? Originaly no LLC option on my motherboard but since v7 bios option is available but doesnt seem to work ?
> Another thing, I cannot change my vDDG CCD/IOD voltage (they stay at 0.99 what ever I put here )


VSOC at 3800 FCLK 1900 should not be at 1.0V minimum should be around 1.05V-1.08V.
Very low VSOC is probably the main cause of your WHEA errors.

@Taraquin
RttPark disabled this seems somewhat stable. 1 error in last cycle.









Very snappy 51.5ns (no boost override)


----------



## Artylol

GhOsT662 said:


> You could do a quick and dirty test by downloading pbo tuner from github to see if it gets any benefit playing with ppt tdc and edc as you set the values from windows and not from bios and this allows you to bypass the pbo bug.
> 
> This instead is the link where I had read the news of the agesa who had introduced this behavior on the pbo.
> 
> 
> __
> https://www.reddit.com/r/Amd/comments/vecyn6


I tried tuner ofc. Performance scales with EDC up to 125. Cinebench runs at maybe 70 or 80, with all cores boosting to absolute maximum frequency available. I run CB on air with 70DegC, so I m wondering if downgrading can increase performance. In memory intensive benchmarks speed does not go above 4500MHz, being bottlenecked by EDC


----------



## GhOsT662

Artylol said:


> I tried tuner ofc. Performance scales with EDC up to 125. Cinebench runs at maybe 70 or 80, with all cores boosting to absolute maximum frequency available. I run CB on air with 70DegC, so I m wondering if downgrading can increase performance. In memory intensive benchmarks speed does not go above 4500MHz, being bottlenecked by EDC



Do you mean the bios downgrade to previous agesa versions?


----------



## PJVol

Jeager said:


> Ok ! The last couple of days I only had one error per day (I stop/restart computer every day) at 1900 (even with vSOC at 1.0v). This seems strange, can it be related to voltage drop ? Originaly no LLC option on my motherboard but since v7 bios option is available but doesnt seem to work ?
> Another thing, I cannot change my vDDG CCD/IOD voltage (they stay at 0.99 what ever I put here )


Well... it seems you've got the Fatality x370 gaming X?
Stuck VDDG voltages - bug in some bridge to 1207 bioses, and occasional WHEAs were typical for early x370 Vermeer support.
I'd flash it with this BIOS 7.03 Beta based on 1203 agesa and SMU 56.52 - which is the most stable for my B550, so definitely worth a try.
Don't forget to specify your full PC config.


----------



## Jeager

PJVol said:


> Well... it seems you've got the Fatality x370 gaming X?
> Stuck VDDG voltages - bug in some bridge to 1207 bioses, and occasional WHEAs were typical for early x370 Vermeer support.
> I'd flash it with this BIOS 7.03 Beta based on 1203 agesa and SMU 56.52 - which is the most stable for my B550, so definitely worth a try.
> Don't forget to specify your full PC config.


Yes Gaming X, stuck vDDG is a know thing ? Are you sure I can downgrade ?
P7.30 : *** User will not able to flash previous BIOS once upgrading to this BIOS version.

With default settings and vSOC at 1.1375 it seems to works for now, no errors today (render + game)
I will lower main timings tomorrow and see if we are still OK (damn those default timing are utterly bad )












The_King said:


> VSOC at 3800 FCLK 1900 should not be at 1.0V minimum should be around 1.05V-1.08V.
> Very low VSOC is probably the main cause of your WHEA errors.


My bad, default was 1.08


----------



## Artylol

GhOsT662 said:


> Do you mean the bios downgrade to previous agesa versions?


Yes, is downgrading to AGESA 1203 helpful for performance on 65W chip?


----------



## The_King

@Veii Can't be too much RttPark in this case. 

Is something like this safe to run daily with 1.54V and RttPark disabled? Was lazy should have set the correct tRFC before I ran 25 cycles. Any suggestions before I do another run? Error popped somewhere between cycle 14 and 16.


----------



## GhOsT662

Artylol said:


> Yes, is downgrading to AGESA 1203 helpful for performance on 65W chip?



in theory it should give you better results with the pbo adjustments as there are no bugs that limit the edc up to agesa 1.2.0.3 and the 65 watt chips can eventually be adjusted like the 105 watt chips


----------



## PJVol

Jeager said:


> Yes Gaming X, stuck vDDG is a know thing ?


yep


Jeager said:


> Are you sure I can downgrade ?


Never heard of anyone got issues with the downgrade on asrock boards.
However, it make sense to reset BIOS to default and to disable fTPM before flashing.


----------



## Taraquin

The_King said:


> You can try dropping WTRL 10 even 8 and also try with RDWR 9.
> 
> Probably best to test each change 1 at a time so you know if it stable.
> 
> 
> VSOC at 3800 FCLK 1900 should not be at 1.0V minimum should be around 1.05V-1.08V.
> Very low VSOC is probably the main cause of your WHEA errors.
> 
> @Taraquin
> RttPark disabled this seems somewhat stable. 1 error in last cycle.
> View attachment 2589271
> 
> 
> Very snappy 51.5ns (no boost override)
> View attachment 2589288


Nice! Seemed it was the Vipers that was crap, my FlareX handles 3800 flat 14 at 1.53v without issues up to 46C at RC 38, RC 40 can do 47.5C error free so RC is also quite temp sensitive.

Nice latency! Safe mode or tuned windows 10? I get 53ns with +200 pbo and 54ns wIth no pbo running some tighter timings than you. RC 38, RFC 248, but WR/RTP 14/7.

Tested 4000 flat 15 for fun and the FlareX handles well. Raised RC 40, RFC 264, WTR 4/10, RDWR 8. 

Tested linpack 8gb:
3800cl14 272.6GF VDD18 1.6V
4000c15 266.2GF VDD18 1.6V
4000C15 268.5GF VDD18 1.72V

Will fine tune and see if I match/surpass my 4000 score with my Vipers.


----------



## The_King

Taraquin said:


> Nice! Seemed it was the Vipers that was crap, my FlareX handles 3800 flat 14 at 1.53v without issues up to 46C at RC 38, RC 40 can do 47.5C error free so RC is also quite temp sensitive.
> 
> Nice latency! Safe mode or tuned windows 10? I get 53ns with +200 pbo and 54ns wIth no pbo running some tighter timings than you. RC 38, RFC 248, but WR/RTP 14/7.


I don't test in safe mode. Stock vanilla bloated windows 10.

Only had CO set to -30 for first 3 cores to get 4850 boost clock to to hold. PBO is AUTO the latency will go lower if i do +200Mhz with CL13 managed to get 51ns.
Need more voltage to be stable maybe 1.63V dont want to run that high at the moment.


----------



## Taraquin

The_King said:


> I don't test in safe mode. Stock vanilla bloated windows 10.
> 
> Only had CO set to -30 for first 3 cores to get 4850 boost clock to to hold. PBO is AUTO the latency will go lower if i do +200Mhz with CL13 managed to get 51ns.
> Need more voltage to be stable maybe 1.63V dont want to run that high at the moment.
> View attachment 2589371
> View attachment 2589372


Hmm, seems something is slowing down my windows, have to check. I used to get 52.5-53 earlier with 3800cl15 and 51.5-52 with 4000cl16.


----------



## The_King

Taraquin said:


> Hmm, seems something is slowing down my windows, have to check. I used to get 52.5-53 earlier with 3800cl15 and 51.5-52 with 4000cl16.


I checked 3800 CL15 got about the same 52.3ns









Are you running 21H2 or 22H2?

Mines is this


----------



## Taraquin

The_King said:


> Are you running 21H2 or 22H2?
> 
> Mines is this
> View attachment 2589373


Think it's 22H2, can check after work. Is it slower?


----------



## Artylol

I tried testing for RTT's and CAD Bus by trying to post high speed. I was able to post [email protected] VSOC, 1.0 VDDP with 7/off/7 and 20-20-20-20.

Now when I test normal settings I get error #4 which suggests "PCB crash". What I did wrong and how to fix error #4?


----------



## The_King

Taraquin said:


> Think it's 22H2, can check after work. Is it slower?


Not sure seen a few articles were some people where complaining about 22H2.
The reason I asked is because 22H2 update is pending and I don't want to upgrade if its going to affect performance. lol

@Artylol
I would leave ProcODT on Auto. ProcODT at 28.2 can cause more issues than it can solve.

Most likely your *DrvStr also VDIMM could be abit low

*Edited*
Did a quick test to see what VDIMM I need for 3600 CL14-14-14 its seems like minimum is 1.45V on my setup. Below this gives me errors.


----------



## Imprezzion

The_King said:


> Not sure seen a few articles were some people where complaining about 22H2.
> The reason I asked is because 22H2 update is pending and I don't want to upgrade if its going to affect performance. lol
> 
> @Artylol
> I would leave ProcODT on Auto. ProcODT at 28.2 can cause more issues than it can solve.
> 
> Most likely your *DrvStr also VDIMM could be abit low
> 
> *Edited*
> Did a quick test to see what VDIMM I need for 3600 CL14-14-14 its seems like minimum is 1.45V on my setup. Below this gives me errors.
> View attachment 2589399
> View attachment 2589400


3600C14 bin has 1.45 XMP as well afaik so that kinda lines up. I'm at 3933 straight 15's now at 1.52v and that is pretty much the best I can get out of it. It can do 4000 on 15-16-16 just fine but I need way too much vSOC (1.275 set 1.250 get) to run without WHEA at 2000 FCLK and I don't wanna burn up my great sample 5800X3D lol.


----------



## PJVol

The_King said:


> The reason I asked is because 22H2 update is pending and I don't want to upgrade if its going to affect performance. lol


It's not, as far as I can tell.


----------



## Jeager

PJVol said:


> Well... it seems you've got the Fatality x370 gaming X?
> Stuck VDDG voltages - bug in some bridge to 1207 bioses, and occasional WHEAs were typical for early x370 Vermeer support.
> I'd flash it with this BIOS 7.03 Beta based on 1203 agesa and SMU 56.52 - which is the most stable for my B550, so definitely worth a try.
> Don't forget to specify your full PC config.


Ok so I tried to downgrade from P7.30 to P7.03 I cannot I have an "Invalid file"


----------



## PJVol

Jeager said:


> Ok so I tried to downgrade from P7.30 to P7.03 I cannot I have an "Invalid file"


You may need flashrom to do that.
But honestly, I'd advise to get rid of it and buy some decent b450/b550 board.


----------



## Jeager

I'm not going to spend anymore money on AM4, the whole point of the 5000 upgrade was the X370 compatibility  (i will get nothing more from new board anyway)

edit : no error today on gaming & rendering [email protected]/1.15 cLDO 0.95 with **** timings, will lower them and hope nothing will pop tommorow


----------



## The_King

Jeager said:


> I'm not going to spend anymore money on AM4, the whole point of the 5000 upgrade was the X370 compatibility  (i will get nothing more from new board anyway)
> 
> edit : no error today on gaming & rendering [email protected]/1.15 cLDO 0.95 with **** timings, will lower them and hope nothing will pop tommorow


PJVol maybe was talking about flashrom program you run in DOS or windows that can force flash the BIOS with the correct command line switch.

Was also considering getting a B550 or X570 but just doesn't feel right spending more on AM4 has those boards are quiet close in price to next GEN boards depending on where you live.

Something like this is very cheap I bought mines of Amazon it works very well. Allows you to flash BIOS chip directly on the board. I learned how to use it watching a few
YT few videos. +/- $10 ) They are risks involved so best do your own research before attempting it. have used this on several bricked routers it works like a charm.

Oh you also need another PC or laptop for the flash software to run off.


----------



## Owterspace

Was just playing around.. seems ok to me 

1.575v I believe.. My Black and Whites are weak, while my Royals are strong 

Mixed pairs..


----------



## 67091

Update : I have a semi stable system . I can pass 1Usmus 50 passes back to back after reboots but I can’t pass absolut. I’m going to attempt 150 passes tonight to see if it pings an error. I’m sorry if it bothers people but for me I like to be extremely stable. I’m the kinda guy who runs prime 95 24 hours. I have these ways set in stone since my AMD 462 Barton days.


----------



## The_King

angushades said:


> Update : I have a semi stable system . I can pass 1Usmus 50 passes back to back after reboots but I can’t pass absolut. I’m going to attempt 150 passes tonight to see if it pings an error. I’m sorry if it bothers people but for me I like to be extremely stable. I’m the kinda guy who runs prime 95 24 hours. I have these ways set in stone since my AMD 462 Barton days.
> View attachment 2589885


The one reason why I don't run Anta profiles is that there is no deciphered codes for troubleshooting.
At least none that I know off. If anyone knows of such a thing then please let me and others know.

TRAS = RCD+RP is 16+15 = 31 then RC 46. Not sure if that will help or not.

RttNom and RttWr don't look correct for 4X8GB dimms. If the above does not help then I would look at those has possible issues.
My guess is your issues in Absolut are from overheating dimms. What does your temp reach when you run Absolut and it starts to error?

You can also try making RTP 8 and setting TRAS 24 and RC 39. Or just try changing RTP to 8 only might help with your issues.


----------



## Artylol

I have encountered some barrier during overclock of Patriot 4000 cl 16 A2 Board:
1) [email protected] VDIMM - no errors
2) [email protected] VDIMM - no errors
3) [email protected] VDIMM - a lot of errors 2, 6, 8, 10, 11, 12, 13, all of which tell about not enough VDIMM. In addition, this step forces PHYRDL from 26/26 to 28/26, which is countered by increasing CLDO_VDDP to 920-950 mV.

It seems like I need twice as much voltage for incremental step of 3733-3800CL14. Loosening timing does not help. I suspect that it is a limit of IMC going below 7.5ns (3800cl14). Does anyone have experience or answer how to counter that? 

All settings below, changing only the speed. I know I should do primaries first, but my approach right is to find how much voltage I need for each step of frequency.


----------



## The_King

Artylol said:


> I have encountered some barrier during overclock of Patriot 4000 cl 16 A2 Board:
> 1) [email protected] VDIMM - no errors
> 2) [email protected] VDIMM - no errors
> 3) [email protected] VDIMM - a lot of errors 2, 6, 8, 10, 11, 12, 13, all of which tell about not enough VDIMM. In addition, this step forces PHYRDL from 26/26 to 28/26, which is countered by increasing CLDO_VDDP to 920-950 mV.
> 
> It seems like I need twice as much voltage for incremental step of 3733-3800CL14. Loosening timing does not help. I suspect that it is a limit of IMC going below 7.5ns (3800cl14). Does anyone have experience or answer how to counter that?
> 
> All settings below, changing only the speed. I know I should do primaries first, but my approach right is to find how much voltage I need for each step of frequency.
> View attachment 2590099


The only thing I can suggest again is trying to switch the DIMMs position.
It can make a world of difference on 4 DIMM slot board and may make things much better or much worse. lol

Only way to find out is to try it and see. If I switch positions off my DIMMs I won't be able to do 3800 CL14 and pass TM5 anymore without using ACS-56


----------



## Imprezzion

I'm fighting still with my RAM. It makes no sense. How can 4000C16 8ns calculated latency, AIDA 58.2-58.4ns be SO much faster then for example 3866C15 7.76ns calculated latency AIDA 60.4-60.7ns or 3800C15 which is still faster at 7.89ns calculated but barely even hits under 62ns. I have all the tertiary timings as tight as they can go, I adjust tRFC to stay around 138-140ns so that isn't it, all 3 profiles are ran 1:1, all 3 profiles have tCL, tRCD and tRP the same so 15-15-15 and tRAS as 35/36 with tRC being tRCD+tRAS at all times... Always set to 2T GDM OFF to prevent GDM from playing a role, yet still on anything that isn't at least 4000Mhz the latency stays horrible in any benchmark.. i see people hitting 57.xx on 5800X3D's and 3800Mhz memory but I can't even get under 61ns..


----------



## Artylol

Imprezzion said:


> I'm fighting still with my RAM. It makes no sense. How can 4000C16 8ns calculated latency, AIDA 58.2-58.4ns be SO much faster then for example 3866C15 7.76ns calculated latency AIDA 60.4-60.7ns or 3800C15 which is still faster at 7.89ns calculated but barely even hits under 62ns. I have all the tertiary timings as tight as they can go, I adjust tRFC to stay around 138-140ns so that isn't it, all 3 profiles are ran 1:1, all 3 profiles have tCL, tRCD and tRP the same so 15-15-15 and tRAS as 35/36 with tRC being tRCD+tRAS at all times... Always set to 2T GDM OFF to prevent GDM from playing a role, yet still on anything that isn't at least 4000Mhz the latency stays horrible in any benchmark.. i see people hitting 57.xx on 5800X3D's and 3800Mhz memory but I can't even get under 61ns..


Does X3D generally has higher timings than normal SKU's? Please share your zentimings.

In my case 3866cl15 is faster than 4000cl16. You might get lower latency if something is too tight, as far as I know


----------



## Nd4spdvn

Imprezzion said:


> I'm fighting still with my RAM. It makes no sense. How can 4000C16 8ns calculated latency, AIDA 58.2-58.4ns be SO much faster then for example 3866C15 7.76ns calculated latency AIDA 60.4-60.7ns or 3800C15 which is still faster at 7.89ns calculated but barely even hits under 62ns. I have all the tertiary timings as tight as they can go, I adjust tRFC to stay around 138-140ns so that isn't it, all 3 profiles are ran 1:1, all 3 profiles have tCL, tRCD and tRP the same so 15-15-15 and tRAS as 35/36 with tRC being tRCD+tRAS at all times... Always set to 2T GDM OFF to prevent GDM from playing a role, yet still on anything that isn't at least 4000Mhz the latency stays horrible in any benchmark.. i see people hitting 57.xx on 5800X3D's and 3800Mhz memory but I can't even get under 61ns..


It's not only ram timings but also IF speed which improves system latency by up to about 2ns per 100MHz IF (AIDA) at similar ram timings. I get about 57ns in AIDA at these settings & timings and 64.2ns in IMLC.


----------



## Imprezzion

Nd4spdvn said:


> It's not only ram timings but also IF speed which improves system latency by up to about 2ns per 100MHz IF (AIDA) at similar ram timings. I get about 57ns in AIDA at these settings & timings and 64.2ns in IMLC.
> 
> View attachment 2590489


Hmm. Zentiming shows your FCLK out of sync with the RAM tho. That is odd. I am at 57.6 ish with 3933 flat 15's 1967 FCLK MCLK but dropping down to for example 3800 with the exact same timings and FCLK 1900 it goes all the way up to like high 61's. That is just too much of a jump to make sense.


----------



## Artylol

@Veii
Dear Veii, I have hard time searching for all information you shared here. I believe we should create sticky first post with links to your posts. Anyway, I have red everything I can find about RTT and CADstr. It seems like adjusting RTT can help to reduce temperature of the dimms by certain amount by controlling electrical current to the dimms and at the same time can be dangerous at high voltages. I have Patriot Viper 4000flat16, A2 board (8 layers). I have couple of questions: 

Can you advice on safe limits for this A2 PCB's and clarify on how to reduce DIMM temperature and what is drawback? 
Do I understand correctly that all resistances should be as low as possible? For example if I stable at RTT_park 3 to 7 and RTT nom 1,4,6,7 which should I choose?
Do DrvStr should be as low as possible too? I can run 14 flat and 16 flat with 20-20-20-20, but for odd CL15 I need ClkDrvStr 40
Do I need to vary CadSetups depending on frequency, as I seen on some of your screenshots? Also, Do I understand correctly that DrvStr use can allow to avoid use of CADsetups?
Does tCKE do anything with disabled powerdown?


----------



## Nd4spdvn

Imprezzion said:


> Hmm. Zentiming shows your FCLK out of sync with the RAM tho. That is odd. I am at 57.6 ish with 3933 flat 15's 1967 FCLK MCLK but dropping down to for example 3800 with the exact same timings and FCLK 1900 it goes all the way up to like high 61's. That is just too much of a jump to make sense.


There is no out of sync with the RAM it's just Zentimings failing to detect properly the RAM speed which I think is in the notes of the latest version. Probably caused by the fact that I use the 56:3 strap which is memory at 1867Mhz with 102 BCLK.
But in your case, you are right the jump is higher than normal should probably be about 0.6ns.


----------



## Artylol

deleted


----------



## amdocer34

Bought a used dual rank b-die 16gb x 2 which runs by default on these xmp timings, wondering which timings i should focus on to get most improvement for gaming, mostly online multipalyer like cs go and rocketleague, but also play massive single player like GOW etc. 
\


----------



## neobpm

Here my ZenTimmings and Aida64 memory benchmark results with 32gb Crucial Ballistix Max 4000cl18 @ 3500cl15:





Could anyone help me to improve the latency? 65.5ns is a bit high for 3600cl15 RAM...


----------



## Ivan B.

Hi, after my Christmas testing. For me the best option is 3600MHz. RAM voltage is 1.45V


----------



## Taraquin

Artylol said:


> I have encountered some barrier during overclock of Patriot 4000 cl 16 A2 Board:
> 1) [email protected] VDIMM - no errors
> 2) [email protected] VDIMM - no errors
> 3) [email protected] VDIMM - a lot of errors 2, 6, 8, 10, 11, 12, 13, all of which tell about not enough VDIMM. In addition, this step forces PHYRDL from 26/26 to 28/26, which is countered by increasing CLDO_VDDP to 920-950 mV.
> 
> It seems like I need twice as much voltage for incremental step of 3733-3800CL14. Loosening timing does not help. I suspect that it is a limit of IMC going below 7.5ns (3800cl14). Does anyone have experience or answer how to counter that?
> 
> All settings below, changing only the speed. I know I should do primaries first, but my approach right is to find how much voltage I need for each step of frequency.
> View attachment 2590099


You may need RCDRD 15, you may get problems due to temp. I would try QR/RTP 12/6 or 14/7 and run slightly lower voltage to see if that helps. RRDL 6 may also help and ProcODT 30, 32 or 34 may resolve the 26/28 issue.


----------



## Netblock

The_King said:


> @Veii Can't be too much RttPark in this case.
> 
> Is something like this safe to run daily with 1.54V and RttPark disabled? Was lazy should have set the correct tRFC before I ran 25 cycles. Any suggestions before I do another run? Error popped somewhere between cycle 14 and 16.
> 
> View attachment 2589367


RTT_Nominal won't do anything for you as you are running single-rank. RTT_Nominal gets used when the ODT pin gets driven high, which only happens on the first rank on the inactive DIMM of the channel; otherwise, RTT_Park gets used instead. (Furthermore disabling Nom will give you a tiny probably immeasurable power/temp benefit as the ODT receiver gets turned off)

For single-rank, setting RTT to dis-3-1 might improve stability issues when transitioning between idle and writes.


----------



## Netblock

Artylol said:


> Anyway, I have red everything I can find about RTT and CADstr. It seems like adjusting RTT can help to reduce temperature of the dimms by certain amount by controlling electrical current to the dimms and at the same time can be dangerous at high voltages.


That is an incorrect understanding of the termination impedances and drive strengths. They are about improving signal integrity though impedance matching which reduces signal reflection. Lower impedances are not inherently better and higher impedances are not inherently better; the ideal value depends on the motherboard for the traces and generally all the metal that exists between the DRAM silicon and the memory controller PHY.





Artylol said:


> Do I need to vary CadSetups depending on frequency, as I seen on some of your screenshots? Also, Do I understand correctly that DrvStr use can allow to avoid use of CADsetups?
> Does tCKE do anything with disabled powerdown?


The setups are separate from the drive strengths, but they work in tandem for improving command-address bus stability. I have more detail on how they work like here.

tCKE does not do anything without PowerDown. It might be used in regard to sleeping the computer, but tCKE 1 is good enough in my experience.




Artylol said:


> View attachment 2590490


RTT_Nominal won't do anything for you as you're single-rank.

Also you should not get anything out of adjusting CsODT because you are running single-rank; the chipselect (rank select) and ODT (RTT_Nom) pins will not change during normal operation for you.


----------



## Artylol

@Netblock 
Do you have an idea about how VDDP can increase or reduce DIMM temperature? I don't have temperature sensors on my vipers. If I knew this previously, actually would have overpaid for other set.



Netblock said:


> That is an incorrect understanding of the termination impedances and drive strengths.


Okay, everyone is quoting "signal integrity" but I bet barely anyone understands that. I don't for that matter. Can you please comment on following statements on impedances then:

Lesser impedance means higher signal integrity because resistance creates noise. In addition to that "impedance matching" reduces noise by eliminating signal reflections
Higher impedance creates stress on PCB and/or chips, so with higher voltage you need to use lower impedance
At the same voltage, higher impedance/resistance circuit will have less current, so increasing impedance/resistance can reduce heat of the DIMM's

This is my understanding so far, mostly based on @Veii, but his texts are pain in the ass to read because they are probably google translated or something IDK.



Netblock said:


> tCKE does not do anything without PowerDown. It might be used in regard to sleeping the computer, but tCKE 1 is good enough in my experience.


I've heard that proper tCKE can reduce heat output, I guess this does not work without powerdown right? If I have powerdown disabled, does it mean that CKEDrvStr is also useless?


----------



## Netblock

Artylol said:


> Do you have an idea about how VDDP can increase or reduce DIMM temperature? I don't have temperature sensors on my vipers. If I knew this previously, actually would have overpaid for other set.


VDDP powers the DDR PHY, which is at the memory controller side. With Zen2 and newer, it gets LDO'd in the IOD from the DIMM rail. VDDP won't increase DIMM temperature.




Artylol said:


> Okay, everyone is quoting "signal integrity" but I bet barely anyone understands that


Loudhorns and our ear cartilage (auricle) are impedance matchers that improve signal integrity. I believe swimming goggles are too.



Artylol said:


> Lesser impedance means higher signal integrity because resistance creates noise. In addition to that "impedance matching" reduces noise by eliminating signal reflections
> Higher impedance creates stress on PCB and/or chips, so with higher voltage you need to use lower impedance
> At the same voltage, higher impedance/resistance circuit will have less current, so increasing impedance/resistance can reduce heat of the DIMM's


None of that is true; that's not how it works; that's not what those resistors do or are about. They don't create noise, they solve it; they don't create stress on the PCB/chips/whatever, they reduce it; they don't increase heat, they enable allow a lower transmission power.

A termination impedance that is matched to the transmission line (traces, etc) will allow a lower transmission voltage as less of the transmission power gets thrown away via reflection or destroyed by wave addition.

Regurgitating Wikipedia, some of the signal power may be reflected back to its origin rather than being carried all the way along the cable to the far end. This happens because imperfections in the cable cause impedance mismatches and non-linear changes in the cable characteristics. These abrupt changes in characteristics cause some of the transmitted signal to be reflected.

The surface of water reflecting light is an impedance mismatch, yielding a signal reflection. Optical refractive index matching is impedance matching.



Artylol said:


> I've heard that proper tCKE can reduce heat output, I guess this does not work without powerdown right? If I have powerdown disabled, does it mean that CKEDrvStr is also useless?


tCKE is how long a change of the CKE pin takes to be valid. The CKE pin doesn't change unless PowerDown or computer sleep gets used.

Check out Micron's rewording on JESD79-4 and its revisions for more detail.


----------



## PJVol

Netblock said:


> With Zen2 and newer, it gets LDO'd in the IOD from the DIMM rail.


To be precise, from the VddIO_Mem am4 rail. Dimm rail is powering dimms directly from a separate buck converter.


----------



## Nucky

I just moved from a 5900x to a 5800x3d. I could never get my 5900x faster than 3733c16 at the attached timings with this with 4x8 3600c15 b die. I would like to push the 5800x3d further but im hitting a similar wall. I think I'm stuck at 101 bclk. I don't have an external clock gen and my gen4 nvmes don't seem to want to show up at pcie3 though the board posts at 102 easily. Any thing obvious I can try to push for 3800+ ?


----------



## The_King

Netblock said:


> RTT_Nominal won't do anything for you as you are running single-rank. RTT_Nominal gets used when the ODT pin gets driven high, which only happens on the first rank on the inactive DIMM of the channel; otherwise, RTT_Park gets used instead. (Furthermore disabling Nom will give you a tiny probably immeasurable power/temp benefit as the ODT receiver gets turned off)
> 
> For single-rank, setting RTT to dis-3-1 might improve stability issues when transitioning between idle and writes.


Thanks for the reply. 

Just want to confirm we talking about RttPark at 1? RZQ/1 (240)?

I have only used or seen that high Rttpark with DR or 4XSR dimms, is that ok for 2XSR dimms?


----------



## Artylol

Netblock said:


> A termination impedance that is matched to the transmission line (traces, etc) will allow a lower transmission voltage as less of the transmission power gets thrown away via reflection or destroyed by wave addition.


OK, so is there a method of finding a way to reduce those effects or is it just a guess game? Even if it guess game, is there a way to know if stabilizing can be done by changing terminations?


----------



## Taraquin

Netblock said:


> That is an incorrect understanding of the termination impedances and drive strengths. They are about improving signal integrity though impedance matching which reduces signal reflection. Lower impedances are not inherently better and higher impedances are not inherently better; the ideal value depends on the motherboard for the traces and generally all the metal that exists between the DRAM silicon and the memory controller PHY.
> 
> 
> 
> 
> 
> The setups are separate from the drive strengths, but they work in tandem for improving command-address bus stability. I have more detail on how they work like here.
> 
> tCKE does not do anything without PowerDown. It might be used in regard to sleeping the computer, but tCKE 1 is good enough in my experience.
> 
> 
> 
> 
> RTT_Nominal won't do anything for you as you're single-rank.
> 
> Also you should not get anything out of adjusting CsODT because you are running single-rank; the chipselect (rank select) and ODT (RTT_Nom) pins will not change during normal operation for you.


On my SR B-die I noticed that temps rose faster during stress-testing when using a lower value on RTT_Park. For instance using 3 made stresstest fail a couple of mins faster than 7, so it seemed 3 increased temps a bit faster on my setup. The others were set to disable. If I remember Veii correct he said that if you could disable RTT_Park that could reduce temps further on certain setups. Did you test this The King when you found the combo that made Park disable possible?


----------



## Taraquin

The_King said:


> Thanks for the reply.
> 
> Just want to confirm we talking about RttPark at 1? RZQ/1 (240)?
> 
> I have only used or seen that high Rttpark with DR or 4XSR dimms, is that ok for 2XSR dimms?


I tried 1 on Park and that mde temps increase even faster. If I remember correct using 1 on Park combined with high voltage can possible damage certain A0 dimms?


----------



## The_King

Taraquin said:


> I tried 1 on Park and that mde temps increase even faster. If I remember correct using 1 on Park combined with high voltage can possible damage certain A0 dimms?


Yes, that is why I wanted to confirm. 

Considering I only had 1 error in 25 cycles with RttPark disabled I won't want to run something like that on a daily setup with Rttpark @ 1 seems a bit dangerous for my current config.

Don't want to destroy the best binned ram I have.


----------



## mikalcarbine

Could use some advice with tightening up my B-die timings, here is where I am so far. I've tightened up my sub timings and I'm trying to achieve flat 14-14-14-14-28. It's rock stable at 14-15-14-14-28 but tRCRD at 14 is giving me errors no matter what I've tried.










So far I've tried playing with ProcODT 30-60 ohms, IOD up to 1.085 in 0.05mV increments, VSOC up to 1.175, VDDP from 0.85-0.925 and vDimm up to 1.53v. I just started playing with RTT and CAD BUS settings but it doesn't look like it is helping tremendously. Could one of my subtimings be too tight and be holding me back or this just silicon lottery at this point?


----------



## The_King

mikalcarbine said:


> Could use some advice with tightening up my B-die timings, here is where I am so far. I've tightened up my sub timings and I'm trying to achieve flat 14-14-14-14-28. It's rock stable at 14-15-14-14-28 but tRCRD at 14 is giving me errors no matter what I've tried.
> 
> View attachment 2590848
> 
> 
> So far I've tried playing with ProcODT 30-60 ohms, IOD up to 1.085 in 0.05mV increments, VSOC up to 1.175, VDDP from 0.85-0.925 and vDimm up to 1.53v. I just started playing with RTT and CAD BUS settings but it doesn't look like it is helping tremendously. Could one of my subtimings be too tight and be holding me back or this just silicon lottery at this point?


Probably going to get into trouble for repeating this so many times in this thread but have you tried swapping your dimm positions? 

tCWL 14 is usually easier to stabilize than CL14 with tCWL 12.
Would also leave both SCLs at 4.
Have your tried with ClkDrvStr 40?

It's best you post TM5-1usmus_v3 errors codes else no one can really advise what your issues are.


----------



## Veii

Artylol said:


> This is my understanding so far, mostly based on @Veii, but his texts are pain in the ass to read because they are probably google translated or something IDK.
> 
> 
> Artylol said:
> 
> 
> 
> 
> Lesser impedance means higher signal integrity because resistance creates noise. In addition to that "impedance matching" reduces noise by eliminating signal reflections
> Higher impedance creates stress on PCB and/or chips, so with higher voltage you need to use lower impedance
> At the same voltage, higher impedance/resistance circuit will have less current, so increasing impedance/resistance can reduce heat of the DIMM's
Click to expand...

Its exactly the opposite, but not all
You can google try to translate the chinese pages, it might be easier to read than my English text
https://www.overclock.net/threads/o...ability-thread.1628751/page-544#post-28845817
Those are the 4 links in the middle, try to read it there





DDR4 设计概述以及分析仿真案例_信号


和DDR3不同的是， DDR4的ODT有四种模式：Data termination disable, RTT_NOM,RTT_WR, 和 RTT_PARK。 众所周知，DDR信号一般通过比较输入信号…




www.sohu.com












The Secrets of PC Memory: Part 3 | bit-tech.net


In the third part of our detailed investigation into memory technology, our resident expert, Ryan J. Leng, dives into memory generations and detail its revolutionary, then evolutionary technical break-throughs that lead us up to today's systems.




www.bit-tech.net












The Secrets of PC Memory: Part 3 | bit-tech.net


In the third part of our detailed investigation into memory technology, our resident expert, Ryan J. Leng, dives into memory generations and detail its revolutionary, then evolutionary technical break-throughs that lead us up to today's systems.




www.bit-tech.net












The Secrets of PC Memory: Part 3 | bit-tech.net


In the third part of our detailed investigation into memory technology, our resident expert, Ryan J. Leng, dives into memory generations and detail its revolutionary, then evolutionary technical break-throughs that lead us up to today's systems.




www.bit-tech.net




~ because explanation might be bad, even if target is similar

Target is clean pulse or wide data-eye
Which means there are, always were pairs

Thinking explanation might be more difficult than reading explanation
Up to human really. For you maybe technical data is more logical or i have it badly explained in the past.
Both can be true
Explanation was based on real world, while later crosschecked with technical

At any point,
data states one but ground-zero/unison is unclear.
You can not base expectation or tutorial of "first design" , to "tuning on done implemenation"

Values you can select in the gui-database (bios), are pretested and determined based on AMD QVL (trace design)
They do not exactly match values you would target on first-pcb-design
Soo foundation-tutorials can be easily misleading
But yes, ofcourse they go in pairs
=====================
EDIT:
half of the thinking has been done for you by boarddesign and symmetric target
Other half depends now on the DIMM PCB you get, what works and at which starting VDIMM point

Values will shift up to VDIMM and MT/s (strain)
Timings are halfway irrelevant, except for GDM which influences it

Side-issue influences are also,
CPU1P8
VDDP
ProcODT state
CAD_BUS values
SETUP timing values

And CKE is used not only on powerdown, also there is not "one" powerdown mode
// it was not that way at launch but it changed. It still ? maybe is not on Matisse, unsure
This you can easily verify, vs expecting technical to reflect real world.
Just test, there is no "preset" even if boarddesigns on AM4 nearly always behave identical.
That was the target to begin with, unlike on Intel where boardpartners have more access.

I will not give you presets or teach you technical terms.
But if written-out thinking method leads to nowhere, then i dont know how to help further.
Or "in which language"


----------



## mikalcarbine

The_King said:


> Probably going to get into trouble for repeating this so many times in this thread but have you tried swapping your dimm positions?
> 
> tCWL 14 is usually easier to stabilize than CL14 with tCWL 12.
> Would also leave both SCLs at 4.
> Have your tried with ClkDrvStr 40?
> 
> It's best you post TM5-1usmus_v3 errors codes else no one can really advise what your issues are.


Is swapping DIMMs really a thing that works??

Tried your settings, I had to changed tRDWR to 8 and tWRRD to 3 in order to boot. 










ClkDrvStr at 40 seemed to help a little. It's better at 60 but still throwing single to a few errors on test 2, 6 and 13. At 40 single errors were popping up in test 11 as well. Memory temps are around 40C.


----------



## Netblock

The_King said:


> Thanks for the reply.
> 
> Just want to confirm we talking about RttPark at 1? RZQ/1 (240)?
> 
> I have only used or seen that high Rttpark with DR or 4XSR dimms, is that ok for 2XSR dimms?


Yea RTT_Park at RZQ/1 as in 240 ohms. I've heard of a couple anecdotes that single-rank observes a minor stability benefit with dis-3-1.


The use of RTT for single-rank is not as straightforward as it is for multi-rank; it's about state transitions rather stablising the bus for another rank's access.

During normal operation, for any given rank, you got 3 states: reads, writes, and idle. Reads can't have a drive strength (termination) for the DRAM drives with R_on (= RZQ/7, I believe); writes terminate with RTT_Wr; and idle terminates to RTT_Park. RTT_Nominal is used instead of RTT_Park when the ODT pin gets driven high.

(anecdotes with a tri-rank system: RTT 1-3-7 and 1-3-6 doesn't boot; though I didn't test with the DIMMs in the unoptimal order.)

Consider the ODT section for more information; though DDR5 has a beter-written description of ODT so I suggest to read that instead. (That said, DDR5 brings new features, like splitting Nominal for writes and reads, and DQS parking, both of which don't exist for DDR4.)


----------



## Veii

The_King said:


> Just want to confirm we talking about RttPark at 1? RZQ/1 (240)?
> 
> I have only used or seen that high Rttpark with DR or 4XSR dimms, is that ok for 2XSR dimms?


Best of luck~ 
It might be needed


----------



## Netblock

Veii said:


> And CKE is used not only on powerdown, also there is not "one" powerdown mode
> // it was not that way at launch but it changed. It still ? maybe is not on Matisse, unsure
> This you can easily verify, vs expecting technical to reflect real world.
> Just test, there is no "preset" even if boarddesigns on AM4 nearly always behave identical.
> That was the target to begin with, unlike on Intel where boardpartners have more access.



What are you referring to?

At least for DDR4, the CKE pin basically never changes from high if PowerDown and Self Refresh (eg, computer sleep) aren't used. (That said, there are multiple different uses for the CKE pin during the bootup sequence and abnormal operation modes.)


----------



## Veii

Netblock said:


> What are you referring to?
> 
> At least for DDR4, the CKE pin basically never changes from high from high if PowerDown and Self Refresh (eg, computer sleep) aren't used. (That said, there are multiple different uses for the CKE pin during the bootup sequence and abnormal operation modes.)


Daily operation, not specification
What is "abnormal operation" mode ?


----------



## The_King

Veii said:


> Best of luck~
> It might be needed


If you have some free time to check this post and let me know if its safe to run 1.54V with rttpark disabled for daily. Thanks 









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Ok ! The last couple of days I only had one error per day (I stop/restart computer every day) at 1900 (even with vSOC at 1.0v). This seems strange, can it be related to voltage drop ? Originaly no LLC option on my motherboard but since v7 bios option is available but doesnt seem to work ...




www.overclock.net


----------



## Netblock

Veii said:


> Daily operation, not specification
> What is "abnormal operation" mode ?


I'm having trouble understanding your first line.

By 'abnormal operation' I mean situations where the DRAM isn't being used as a memory. Bootup sequence, connectivity test, maximum power saving (a data-destroying low-power mode). For normal operation, toggling the CKE pin implies nothing more than the PowerDown and Auto Self Refresh features.

(likewise, tCKE isn't used outside of those two aforementioned features)


----------



## Netblock

The_King said:


> If you have some free time to check this post and let me know if its safe to run 1.54V with rttpark disabled for daily. Thanks
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Ok ! The last couple of days I only had one error per day (I stop/restart computer every day) at 1900 (even with vSOC at 1.0v). This seems strange, can it be related to voltage drop ? Originaly no LLC option on my motherboard but since v7 bios option is available but doesnt seem to work ...
> 
> 
> 
> 
> www.overclock.net


There's nothing unsafe about RTT; anything goes. That said, not sure why you would want to run RTT park disabled.


----------



## Veii

The_King said:


> @Veii Can't be too much RttPark in this case.
> 
> Is something like this safe to run daily with 1.54V and RttPark disabled? Was lazy should have set the correct tRFC before I ran 25 cycles. Any suggestions before I do another run? Error popped somewhere between cycle 14 and 16.
> 
> View attachment 2589367
> 
> 
> 
> The_King said:
> 
> 
> 
> If you have some free time to check this post and let me know if its safe to run 1.54V with rttpark disabled for daily. Thanks
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Ok ! The last couple of days I only had one error per day (I stop/restart computer every day) at 1900 (even with vSOC at 1.0v). This seems strange, can it be related to voltage drop ? Originaly no LLC option on my motherboard but since v7 bios option is available but doesnt seem to work ...
> 
> 
> 
> 
> www.overclock.net
Click to expand...

Netblock can maybe explain you the difference on DynamicODT between Single Rank and Dual rank
Dual rank "becomes complicated"

Because you use RTT_WR , lack of PARK is corrected/adapted for
It's fine, but about the issue/error i'm not sure
Maybe this is alright















Added for comparison
If SD, DDs dont run - it's too tight RRD/WTR_L's
1.54v is about in the middle - if you up it to 1.57 you could run RTT_NOM /6

When that is stable, you can go down on RAS to 20, RC 34 and try to zero away SD's
Also then add WRWRSCL 2 (experimental)
// lack more testing data, could autocorrect & be worse, as CCDL/CCDLWR behavior is abstract on AMD and scales by Freq

You will see what works 
Are those old A0 vipers or A2 customs ?


----------



## Veii

Netblock said:


> I'm having trouble understanding your first line.
> 
> By 'abnormal operation' I mean situations where the DRAM isn't being used as a memory. Bootup sequence, connectivity test, maximum power saving (a data-destroying low-power mode). For normal operation, toggling the CKE pin implies nothing more than the PowerDown and Auto Self Refresh features.
> 
> (likewise, tCKE isn't used outside of those two aforementioned features)


soo this is the theory
Can you replicate the theory to real world and / or explain why memory tests fail by it ?

I haven't seen anybody who quotes specification, be able to explain this "anomaly" on Vermeer and Raphael 
Maybe you can


----------



## The_King

Veii said:


> Netblock can maybe explain you the difference on DynamicODT between Single Rank and Dual rank
> Dual rank "becomes complicated"
> 
> Because you use RTT_WR , lack of PARK is corrected/adapted for
> It's fine, but about the issue/error i'm not sure
> Maybe this is alright
> 
> 
> 
> 
> 
> 
> 
> View attachment 2590867
> 
> Added for comparison
> If SD, DDs dont run - it's too tight RRD/WTR_L's
> 1.54v is about in the middle - if you up it to 1.57 you could run RTT_NOM /6
> 
> When that is stable, you can go down on RAS to 20, RC 34 and try to zero away SD's
> Also then add WRWRSCL 2 (experimental)
> // lack more testing data, could autocorrect & be worse, as CCDL/CCDLWR behavior is abstract on AMD and scales by Freq
> 
> You will see what works
> Are those old A0 vipers or A2 customs ?


A2 custom from what I can tell from looking at the IC layout is that they evenly spaced apart. Very different from my Patriot 4133 C19 which have them bunched together.



Netblock said:


> There's nothing unsafe about RTT; anything goes. That said, not sure why you would want to run RTT park disabled.


Dimms may run cooler with Rttpark disable not sure can't confirm this unless i try it with my G.Skill kit that has temps sensors. These Patriot Vipers dont have temp senors.


----------



## shiznit

If using two dual-rank DIMMs, should I enable BGS or BGS Alt? Thx.


----------



## Veii

The_King said:


> A2 custom from what I can tell from looking at the IC layout is that they evenly spaced apart. Very different from my Patriot 4133 C19 which have them bunched together.


I haven't seen such
They only differ in height , but are still close

A0's are further upwards


----------



## The_King

Veii said:


> I haven't seen such
> They only differ in height , but are still close
> 
> A0's are further upwards


Will try to take some clear photos with my DSLR tomorrow and post it. Time to hit the hay


----------



## Netblock

Veii said:


> 1.54v is about in the middle - if you up it to 1.57 you could run RTT_NOM /6


RTT_Nominal does not get used unless there is more than one DIMM per channel; otherwise RTT_Park does the job.



Veii said:


> soo this is the theory
> Can you replicate the theory to real world and / or explain why memory tests fail by it ?
> 
> I haven't seen anybody who quotes specification, be able to explain this "anomaly" on Vermeer and Raphael
> Maybe you can


I'm not sure what you mean. Furthermore, you're the one with the theory; you're the one making the claim that it does do something outside of PowerDown and computer sleep (ACPI S3).

I am running a 48GB tri-rank config at a hair over 3800MT/s with GDM off 1T. My system presents a pretty hefty load on the command-address and data buses, as well as the scheduler compute logic. I haven't found a reason to move from tCKE 1. I am currently stress-testing Cke DrvStr/Setup at 24/0 to see if what I had them at makes or breaks anything (I had them at 120/50 for the longest time); PCBDestroyer has been running for 50 minutes (~10 cycles) without error.

What could I do to make my system express what you are talking about?




The_King said:


> Dimms may run cooler with Rttpark disable


I can sorta believe it; disabling termination is a thing often used for powersaving in PHY design. However I'm not too sure if it can exhibit a measurable difference on the temperature for how low-power memory already is. That said, there are multiple other tools in the toolbag if you're trying to lower the temperature.

Have you shucked the heatspreaders (heatspreaders are often outright worse than naked DIMMs); have you attached a heatsink or waterblock to the DRAM (attach VRAM heatsinks to the memory with a thermally conductive adhesive)?

RGB memory? disable with OpenRGB

Lower VPP? (there's also a separate stability benefit with a lowered VPP (rowhammer); though it might make tRCDRD and tRFC worse)

Is there any single timing that's preventing a lowered DIMM voltage? tCL often ends up being the sole reason a higher voltage is needed.


----------



## Veii

Netblock said:


> I'm not sure what you mean. Furthermore, you're the one with the theory; you're the one making the claim that it does do something outside of PowerDown and computer sleep (ACPI S3).


EDIT:
Redacted by being unintentionally rude


----------



## Netblock

Veii said:


> Why ?
> I dont seek to argue, seen its an issue and build around it to resolve it
> Yet you try to decline experienced issue without testing
> // soo i asked "can you even try and replicate instability on bad tCKE"
> 
> We don't have to resolve this, but if you want to argue that i am wrong
> - at least take the time to test, not only to quote "how it has to" behave
> One should get up with the reason that something is different , but you only quote me booktheory.
> 
> Anything i write belongs to tested experience, i don't read specifications unless i have to. (being stuck)
> While i wait to see tested experience on things you recommend.
> 
> Mixture of ranks doesnt become Tri Rank either.
> 
> We can make it simple, come to a common playfield with gear you actually own
> Test 2x single rank and two times dual rank on the RTTs you recommend, let's hope for a familiar PCB layout and then i can believe on data from those theories
> // show how its "correct" before judging about other people's testing. Show what to do based on data and then teach
> 
> But right now, you argue from a position of theory-crafting to a position of somebody who tested and declines it.
> Either we dont argue at all or we meet on common ground. Its that simple.
> 
> What friendly people would do, is just accept the others perspective.
> You decide.
> 
> Sadly i did and was not alone.
> Soo it remains in the room to scale it.
> Because personal experience says while what you write can be true, reality is different.
> Even with PDM it still became a variable of issue ~ which means something is overlooked, or powerdown doesnt tell the full story.
> Or its a bug, that now affects two architectures even on different chipset. Who knows 🤭
> 
> If you want to argue or teach, come to common ground (real world & similar systems)
> There is nothing to argue on who can read better book-theory.



I am having issues interpreting most of what you are saying. Can you please reword?


----------



## Veii

EDIT:
Redacted by being unintentionally rude


----------



## Netblock

Veii said:


> In short, nobody wants to argue
> I've seen it causes issues and found my way to resolve them


Ah sorry, I'm not arguing; I am asking a question. If they do affect, I would like to experience what you are experiencing. What could I do to induce CKE-related instability? What timing or voltage could I adjust that increasing tCKE or adjusting Cke Setup/DrvStr would solve?



Veii said:


> I've seen also issues on RTT changes, soo they definitely are used


Well of course changing RTT does affect stuff. I'm saying that RTT_Nominal happens when the ODT pin gets driven high, and the ODT pin does not get driven high unless there is another DIMM connected to the channel; for all other situations, RTT_Park shall be used instead.




Veii said:


> I don't know how to phrase it differently
> Want to help on 2x SR system, test on gear you own
> Want to help on 2x DR system, own that and show how it is correct // proof us wrong


I am doing something harder; 2xSR+2xDR at the exact same time (four DIMMs, in the order of SR-DR-SR-DR on a 3142-order daisy-chain topology); a tri-rank-per-channel system and have geardown mode disabled with a 1T command rate (check out my screenhots in my earlier post).

I have felt the affects of ProcODT, RTT Nominal, Write, Park; I have little playroom in what they could be (34.3; 6-3-1 seems to be the most ideal) and often outright fail to boot if they are different. The drive strengths and the tSetup/tHold shifts of address-command and chipselect-odt means everything for me being able to run 1T-off. I am having trouble proving to myself that tCKE, CkeSetup and CkeDrvStr do anything for me.


----------



## Anhphe93

Hi everybody! I want to ask about the temperature on Ram, i have Corsair Dominator Platinum 4x8 3200c16. currently is 3800c16 with 1.5vdim. temperature in tm5 is 60 degrees is it normal? Is there any way I can improve that?


----------



## toljan2884




----------



## Imprezzion

I completely messed everything up... I watched some Australian guy on YouTube talk about Windows 11 optimization and disabled a whole bunch of services and uninstalled some bloat and such but ever since my latency is insanely high. 

With just a fresh stock untweaked W11 22H2 I could get around 58.2-58.6ns at 3933C15. Now it doesn't even go under 60ns. With my 59.2-59.6ns 3800C15 profile I now have 61.6-62ns. CB R23 lost 400 points, CPU-Z lost 100 points... 

I don't know what the hell happened but I will probably have to reinstall.. I rolled all the changes back but scores remain terrible.


----------



## klipschorny

Just picked up two kits of Ballistix MAX RGB 4400 MHz 19-19-19-46 (2x8) so i can run 32gb at dual rank (its 8gb E-die so i can run four at dual rank)
I've got a 5800x3d and a X570S TOMAHAWK MAX
keeping clock at 3800 so I can run 1:1 with IF 
How low can I get my timings? Any suggestions?
Thank you in advance


----------



## The_King

klipschorny said:


> Just picked up two kits of Ballistix MAX RGB 4400 MHz 19-19-19-46 (2x8) so i can run 32gb at dual rank (its 8gb E-die so i can run four at dual rank)
> I've got a 5800x3d and a X570S TOMAHAWK MAX
> keeping clock at 3800 so I can run 1:1 with IF
> How low can I get my timings? Any suggestions?
> Thank you in advance


If they are the same 4400 C19s like my C9BLM ICs then these timings should be attainable.
You have to run 25 cycles to check stability but can use these timings has a reference.

If you are going to run GDM disable these timings may not work and you would need to loosen RCDRD to 18 or 19
Don't seem to have a 3800MT FCLK 1900 screenshot with 4X8GB. Will update if I find one.









[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Still no success yet. Errors after that length of time might be due to a core being slightly unstable. Try adding a little positive vCore offset or positive CO just to see - I had to reduce the negative curve on a number of my cores when changing from flat 15s to 14s and one of my cores...




www.overclock.net


----------



## klipschorny

The_King said:


> If they are the same 4400 C19s like my C9BLM ICs then these timings should be attainable.
> You have to run 25 cycles to check stability but can use these timings has a reference.
> 
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Still no success yet. Errors after that length of time might be due to a core being slightly unstable. Try adding a little positive vCore offset or positive CO just to see - I had to reduce the negative curve on a number of my cores when changing from flat 15s to 14s and one of my cores...
> 
> 
> 
> 
> www.overclock.net


Why is your trfc so high?


----------



## The_King

klipschorny said:


> Why is your trfc so high?


I left it high because it not so important to lower that on Micron Rev. E. It makes a bigger difference on Samsung B-die.
You should be able to run TRFC between 280-290ns depending on your dimms bin. But hardly makes a noticeable difference in performance in my opinion or testing


----------



## klipschorny

The_King said:


> I left it high because it not so important to lower that on Micron Rev. E. It makes a bigger difference on Samsung B-die.
> You should be able to run TRFC between 280-290ns depending on your dimms bin. But hardly makes a noticeable difference in performance in my opinion or testing


Okay good to know. I found a zentimings screenshot of my timings on my old 5800x and x570 tomahawk. Now that i have the 5800x3d and x570s tomahawk max should i just put in my old values on new mobo bios and call it a day?

Oh cool you can edit posts. I like this board.


----------



## The_King

klipschorny said:


> Okay good to know. I found a zentimings screenshot of my timings on my old 5800x and x570 tomahawk. Now that i have the 5800x3d and x570s tomahawk max should i just put in my old values on new mobo bios and call it a day?
> 
> Oh cool you can edit posts. I like this board.
> View attachment 2591140


Timings look ok to me, have you tested it for stability using TM5?

You can try testing AIDA64 memory latency with TRAS 48 and RC 64. This may actually improve your Latency.

If its stable with the old settings then just run that.


----------



## Veii

Netblock said:


> Well of course changing RTT does affect stuff. I'm saying that RTT_Nominal happens when the ODT pin gets driven high, and the ODT pin does not get driven high unless there is another DIMM connected to the channel; for all other situations, RTT_Park shall be used instead.


How do you see Bank Group Swap - Alternative mode, operating ?


Netblock said:


> I am doing something harder; 2xSR+2xDR at the exact same time (four DIMMs, in the order of SR-DR-SR-DR on a 3142-order daisy-chain topology); a tri-rank-per-channel system and have geardown mode disabled with a 1T command rate (check out my screenhots in my earlier post).
> 
> I have felt the affects of ProcODT, RTT Nominal, Write, Park; I have little playroom in what they could be (34.3; 6-3-1 seems to be the most ideal) and often outright fail to boot if they are different. The drive strengths and the tSetup/tHold shifts of address-command and chipselect-odt means everything for me being able to run 1T-off. I am having trouble proving to myself that tCKE, CkeSetup and CkeDrvStr do anything for


But if you test on an exotic system , you will get exotic results
Isn't this an issue when recommending values ?

Is it a watercooled system and hard to remove two dimms ? ~ to help people with 2x 16 and 2x 8gb configs
Oh i have to find it
Is this your last result ?









Netblock said:


> I am having trouble proving to myself that tCKE, CkeSetup and CkeDrvStr do anything for


You see no difference on CkeDrvStr & CkeSetup at all ? 
Let me doublecheck how my Setup behaves and edit it here

Also @Netblock , excuse me for being unintentionally rude to you.
It was not needed, had a reason but was not needed. I'm sorry.


----------



## Veii

PJVol said:


> You did managed to make it ignore +200 limit?


I was fooling around, but seems like failed on a personal compile. So did a frankenstein rebrand
Uefitool is old, and AOD is signed. Likely i also messed up and did it wrong. Rebrand worked nearly fully


PJVol said:


> I'd not rely on both of these monitoring tools, since the 1st (asus') is based on too outdated smu metrics table version, and the 2nd (ZenPT) has a number of labels mismatched and need to be corrected/updated, e.g. throttlers clock (infrastructure limits). What Veii thinks is prochot F-limiter is actually not.
> First out of 8 limiter-clocks reported by SMU - Global Core Clock (not PPT) - it's calculated by proportional-intergral-derivative programmable controller (PID) being part of the DVFS/AVFS. It's also referred to by HWInfo64 as "Frequency limit - Global" in a sensor panel.


I can only quote things we see, on tools we have.
Their names can be wrong , but its what we got and can pinpoint to common understanding name.

The connection tracked should still apply even if the title is different.
FIT analyze to what i got so far, missmatches with every other CPU, and is far lower on my side
This goes for remain inspection values and expected values.








Idle between 2.3ghz and 10ghz by readouts
Else thank you for the update. It can be useful. A bit slow on the pooling but most of it is useful for sure

There is an issue with lack of accepted values on this extreme4 bios at i think SMU 56.23?, bellow 56.30
And i think there were untracked issues at SMU 56.72/73. I'm on 56.70 now , back to old ITX ~ because while everything worked, pwm for memory didnt. I was hardstuck at 1.2v
Sadly great potential but not fully compatible convert. Might revisit it someday if time remains and bios modding knowledge increases.


----------



## PJVol

Veii said:


> I can only quote things we see, on tools we have.


Give me a bit of time to fix my monitoring, 'cause currently it's only usable for the single CCD units, and I wanna remind you that of the 2 CCDs in 5600X, the 1st is entirely downcored and the 2nd - by 2 cores (via PSP).
I'm at a loss as to why SMU still generates a PM table for both.


----------



## Veii

PJVol said:


> Give me a bit of time to fix my monitoring,


No worries
I wonder if you could








Be inspired by him, and take a look how he manages the layout for Raphael
Your tool has gotten quite a bit of tracking by a github page linking but not quoting you
Then also same tech media found RyzenSDT to be "too dangerous" haha ~ so i beg for an update on PBO2 Tuner


----------



## Giacomo Coppi

I had some time during those christmas days to play a bit with my setup and i managed to tune a bit 2 different profile i have while still trying to boot 4000mhz without success.










my scores on aida64 test seems a bit low to me , shouldn't i get 57k read and 55k copy at least ?
Ram voltage is flat 1.5v and mem vtt is 0.75v
the cpu is actually stock and no pbo2 is going on .
i tryed to follow a guide on github and i have to test twr at 10 and tcwl at 13 or 12 .
Trcdrd at14 gave me errors on 1usmus_v3
tPHYRDL is 26/28 , i can get 26/26 if i set 2t geardown disabled , 1t geardown disabled no boot and i need clrcmos to boot again in bios.

Any advice to make some further improvements will be much appreciated, good day to everyone


----------



## PJVol

Veii said:


> take a look how he manages the layout for Raphael


Yeah, in fact he shared his findings with me on this long before the Zen4 launch.
I just think I'm unlikely to upgrade until Zen5 and Rdna4 - honestly both AMD latest releases did not impress much, hence the enthusiasm for further support has gone ))
Just wanna add the "monitoring" for a long time.

Btw, if you still have your 2ccd 5600x, can you send me (or post here) ZT-debug-log with a 1.2.0.3 or later Agesa? Early ZT builds logged a truncated 380805 pm_table.

As for "not quoting", heh... it was never a thing for me .


----------



## Netblock

Veii said:


> How do you see Bank Group Swap - Alternative mode, operating ?


I would like to test it but I can't seem got get BGSalt disabled. I have access to an option that controls the regular BGS (non-alt) in the CBS/UMC menu, but it states that BGSalt takes priority.




Veii said:


> But if you test on an exotic system , you will get exotic results
> Isn't this an issue when recommending values ?
> 
> Is it a watercooled system and hard to remove two dimms ? ~ to help people with 2x 16 and 2x 8gb configs


It's not watercooled, though accessing the insides of the computer is a little inconvenient due to how I cable manage my desk.

Remove DIMMs? I'm not entirely sure what you mean. My tri-rank system is a sum of its parts so I expect the dual- and single-rank reductions to work for me without needing to change anything; that said, I haven't actually bothered to revisit 1R and 2R.

For what it is worth, here is an ancient single-rank config I used to daily.


(in attempt to explain an outline of what I'd do, it just grew into a guide, so enjoy the verbosity)
As for value recommendation, I mainly recommend guidelines and starting-points cause I acknowledge different systems will be a little different. For someone actually trying to attack GDM for a 1T-off system,

I'd first explain what each of the things actually affect:
CAD BUS:
Clk is about the actual differential clock pins
AddrCmd address and command pins
CsODT, chipselect (rank select) and ODT (RTT_Nom)
Cke is clock enable (PowerDown and computer sleep)

RTT and ProcODT are for the data bus; and RTT is DRAM-side while ProcODT is controller-side.
ProcODT is only for reads (technical: I believe the processor has a fixed 30 ohms strength for writes)
RTT_Park for rank idle
RTT_Wr for rank writes
RTT_Nom is also idle like Park but selected with ODT pin
is not used unless there is more than one DIMM per channel.

The RTT has other contexts and shortcuts, so it's worth reading the JEDEC entry for ODT if you're gonna give them a good go.

VDDP is the DDR PHY at the memory controller powering the electrical/analog block. Raise it to 1 volt; you can lower it later.
Needs a cold boot to apply. Simple power off should do.
Matters a lot for multi-rank and multi-dimm.
Zen2 and newer use the "cLDO VDDP" and Zen+ and older use "CPU VDDP"; different approaches, really. Zen2 uses a linear regulator sourcing from VDDIO_MEM_S3 (DIMM voltage); and Zen+ sources directly from the VDDP pins, which is an external rail that also powers other PHYs of the system-on-chip.

SOC powers (among other things) the memory controller logic/scheduler, and might need more voltage.



What they actually do and how they work like:
RTT, ProcODT and DrvStr are all about impedance matching for the sake of reducing signal reflection cause signal reflection harms signal integrity.
Higher isn't better and lower isn't better. What is best depends on the hardware for all the metal that exists between the DRAM chips and the memory controller.

The AMD "Setup"s are about tSetup/tHold windows when a information transfer actually gets registered at the clock edge (check out the graph in this link)
Setup values 63->32 helps tSetup, while and tHold is 1->31. They stay within the clock cycle so they are a sacrificial biasing; to give to one you must take from the other.
All DDR SDRAM's command-address bus is SDR. LPDDR and GDDR can be an exception.
By default (0), the data change starts on the clock fall and held until the clock fall.
At the perspective of the memory controller, a Setup value of 48 would take 1/4 clock of the tHold and give it to the tSetup; conversely, a Setup value of 16 would take 1/4 clock of the tSetup and give it to the tHold.
Electricity takes time to travel; at the perspective of the DRAM chips, especially the furthest one, 48 might yield a dead-center balanced tSetup/tHold.


AMD defines 2T command rate as "One additional MEMCLK of setup time is provided on all DRAM address and control signals (not including CS, CKE, and ODT)". This implies that if 2T brings major stability, a proper AddrCmdSetup might allow 1T.
(Check out these two different BKDGs for extra detail (1 UI is 1/2 of a clock cycle). The setups are also encoded hence the count-down count-up representation. Separately, "PPR" is the newer name for "BKDG".)




Recommend DrvStr 24-30-30-24 and Setup 56-56-0; and RTT 7-3-1 and ProcODT <=40 for 500-series boards and >=40 for 400-series and older. Also show what works for me.
And then recommend various approaches and tips:
It is a very good idea to have a well-done 'GDM on' config, good and stabilised, as a point of sanity.
View the stress test errors as a statistical error rate; raise and lower things based on how fast/slow the error rate is or how soon/late it errors.
Walk the Setups in each direction (tSetup:63->32 vs tHold:1->31) to see how far you'd go before you stop booting.
Find local middle and global middle and try them out. (64 = 0)
For global suppose you stop booting at 42 and 3. (64+3) - (64+3 - 42)/2 = 54,55. Local would be to ignore the distance into the other direction. (eg, skip +3)

Or slam to a side and "add" a few steps (say 6-8 steps) to the value that doesn't boot.

Take notes and save firmware overclocking profiles to a USB stick.
Some time later, revisit certain values of the various things because you might have gotten the wrong idea the first time.



Mention various casual behaviours I or others have seen messing around with this:
Some timings might need to be loosened. I lost 2 ticks on tRC (57->59) between GDM on and GDM off for my tri-rank.
tRDRD SD/DD will be affected by CsODT and RTT/ProcODT; if there is a struggle to get to 4, play with those. I was able to get tRDRD SD to 4 from 5 by playing with CsODTDrvStr.
Some people seem to have a better time lowering tWR by messing with the cad bus stuff a little bit.
The vast majority of systems I've seen prefer a tSetup bias on everything (63->32), so skipping out and neglect tHold for an honest poke might save some time.
tHold-favouring systems might like a strong (high impedance) ClkDrvStr? (I also haven't seen many tHold-favoring systems)
Some tSetup-favouring systems might like a weak (low impedance) ClkDrvStr; so like 20 ohms.





Veii said:


> Is this your last result ?
> You see no difference on CkeDrvStr & CkeSetup at all ?
> Let me doublecheck how my Setup behaves and edit it here


Here's my latest result; yea tCKE, CkeDrvStr, CkeSetup all seem to not matter for my system.

Though I can imagine a benefit for the CKE stuff for POSTing, but I'm not sure how to scientifically approach that. The vast majority of my posting issues seem to be about both VDDP and Infinity Fabric being clunky. VDDP needs a cold boot to apply (perhaps a change too?); and my FCLK gets upset at POSTing a >1900MHz fabric sometimes (currently BCLK'ing from 56/3 to 1902.8MHz).



Veii said:


> Also @Netblock , excuse me for being unintentionally rude to you.
> It was not needed, had a reason but was not needed. I'm sorry.


It's okay. I also wasn't clear and straightforward either.


edit jan6 2023: lots of guide tweaks


----------



## GhOsT662

What is a safe cldo vddp for zen 3 to be precise a ryzen 9 5900x, because i noticed that it directly affects the tphyrdl. Because I've read conflicting reports some say not to go over 0.900mV others that over 0.950 can degrade the memory controller. Even if I noticed that at 0.985mV it helps me to have both tphyrdl at 26 could someone give me an explanation thanks


----------



## Imprezzion

I give up with either this board or this 3 week old Windows install..

No matter what I do in terms of RAM frequency or timings latency remains absolutely trash. Even 3800 14-16-14-28-42-240-1T GDM Off all subtimings smashed super low STILL won't go under 61ns.. On the X3D this should run at like 57.xx but in stead I get stuck at 60.5-60.7ns.. It just will not go any lower. No matter what I do.


----------



## Frosted racquet

Trying to stabilize 3733MHz. 1.5-1.51 VDIMM results in numerous error 0, 6-3-3 or 7-3-3 RTTs don't seem to boot, tWTRS 6 doesn't fix error 8. Any suggestions?


----------



## Requiem4u

Imprezzion said:


> I give up with either this board or this 3 week old Windows install..
> 
> No matter what I do in terms of RAM frequency or timings latency remains absolutely trash. Even 3800 14-16-14-28-42-240-1T GDM Off all subtimings smashed super low STILL won't go under 61ns.. On the X3D this should run at like 57.xx but in stead I get stuck at 60.5-60.7ns.. It just will not go any lower. No matter what I do.


Tryed safe mode yet?


----------



## Imprezzion

Requiem4u said:


> Tryed safe mode yet?


I tried a completely new install lol. But. Who knows. Let me give it a shot.

EDIT: yeah ok.. so it is Windows.. the spare SSD has also W11 22H2 on it just a clean install. Still gives me a large variance in latency and still at 3866C15 around 59.6-60.3ns. Safe mode however gives a perfectly flat reproducible run to run 56.5ns. Which is what it should be +2ns ish in live Windows. 58.5 ish. And on CAS 14 57.5 ish. 

But, now I know the RAM, board and timings are fine, it's just W11 22H2 or a service or driver or background program whatever causing the higher then expected latency.


----------



## Veii

Frosted racquet said:


> Trying to stabilize 3733MHz. 1.5-1.51 VDIMM results in numerous error 0, 6-3-3 or 7-3-3 RTTs don't seem to boot, tWTRS 6 doesn't fix error 8. Any suggestions?
> View attachment 2591229











0's are voltage/powering issues, but give it a try.
Else needs some RTT focus ~ or rather CAD_BUS
Once stable, try to drop WRRD
If not possible to get it away ~ drop _Ls to 5/10 (tWR 23), 4/8 (tWR 22)

Generally DR needs tWRRD, at least 2CK to 4CK
But most should be slowable/replacable with SC,SD , DD's delay ~ which even if not always needed (for example on SR) still is inserted

#8s are dimm to dimm or bank to bank - errors
#11 is a sideproduct issue, can be everything which includes overheating too - but not a solo error


----------



## Blameless

Netblock said:


> RTT_Nominal does not get used unless there is more than one DIMM per channel; otherwise RTT_Park does the job.


If this were the case, disabling RttNom on my single DIMM per-channel setups, where rtt_park is enabled, wouldn't change anything, but doing so often renders them unable to post, unable to train, or causes stability issues. Likewise, disabling rtt_park also causes issues on essentially all of my single DPC setups, irrespective of rtt_nom. So, it seems fairly clear that all the ODT values are being used for something.

I also haven't seen any thing in any termination state table that suggests number of DIMMs per channel, in and of itself, has an impact on ODT state, nor anything that suggests termination state distinguishes between different ranks and different DIMMs. Obviously, more than one DPC is needed for most systems to have more than two-ranks per channel, which could influence ODT selection, but if anything rtt_nom seems to take precident over rtt_park when ODT is aserted, according to the DDR4 specifications I can find.

https://www.micron.com/-/media/clie...s/data-sheet/dram/ddr4/8gb_auto_ddr4_dram.pdf -- page 256-257...most DDR4 IC datasheets have equivalent info.

DDR4 is a complex interface to verify — assistance needed! - Semiwiki -- section "Signal Integrity Optimizations in DDR4".


----------



## Frosted racquet

@Veii Thanks for replying, appreciate it. Before I saw your post, I increased VDIMM from 1.52 to 1.55v and it seems stable so far. I will let it finish 50 cycles and then try to decrease VDIMM to 1.53-1.54v and retest. Temps are 2-3°C higher than with my previous 3600 1.5v profile (timings and CAD_BUS were basically the same). During the summer the temps @3600 1.5v were near 60°C when testing TM5 in and ITX case, without any errors (regular use never exceeded ~55°C). Will see if I need to decrease the voltage or add a fan, but I think even keeping 1.55v is OK?

At one point I checked the RAM contacts after running 3600 @1.5v for one year, everything seemed fine. I'll definitely recheck in 6 months if I keep 1.55v @3733

I'm guessing tWRRD is ok to keep at 1 and tCKE at 7 if this is stable?


----------



## Netblock

Blameless said:


> If this were the case, disabling RttNom on my single DIMM per-channel setups, where rtt_park is enabled, wouldn't change anything, but doing so often renders them unable to post, unable to train, or causes stability issues.


Is RTT_Write disabled? The mode-register-programmed values of RTT_Park or RTT_Nominal might be used instead. I wouldn't be surprised if AMD supplies ODT-for-writes via RTT_Nom/ODT pin if RTT_Wr is disabled; this wouldn't be unfounded as DDR4's RTT_Wr is limited in what values could be configured. That said, I haven't actually found any discussion over that. (edit: mode register)

Edit2: AMD's firmware could be clunky too. I have an A320 that refuses to post on any manual RTT.

(Also check out DDR5's termination for a better description)





Blameless said:


> I also haven't seen any thing in any termination state table that suggests number of DIMMs per channel,


RTT_Nom is disabled by default on 1 DPC configurations; this is AMD-recommended behavior.

Also, my understanding is ODT hots on the first rank of the opposite DIMM of the accessed rank. Check out this image album of 17h PPR


Here's other docs:
(Over DDR3, DDR4 brings RTT_Park, which gets used during idle; when the rank is not being read/written, and ODT pin is low)

This intel state table (admittedly for DDR3, tho intel says its the same state diagram for DDR4.) (edit3: writes like a hi-impedance termination)

This AMD BKDG decision flow (also DDR3)

Search through these two BKDG for DDR4 stuff (also here's a list of tech docs). Hella cryptic but it might say something useful.


----------



## Blameless

Netblock said:


> Is RTT_Write disabled?


No.



Netblock said:


> RTT_Nom is disabled by default on 1 DPC configurations; this is AMD-recommended behavior.


All of my dual-rank AM4 systems like all of the termination values to be set. Some of my single rank per channel setups don't seem to benefit from rtt_nom being enabled, but that's not a sure thing.

Anyway, the question isn't whether rtt_nom is enabled by default, it's whether it being manually enabled is respected and utilized.

As far as these various state tables seem to show, I'm not seeing anything that suggests rtt_nom will not be used, if it has been set, at least as far as multi-rank setups go. I'm less clear on single rank, but even then there do seem to be scenarios where ODT could be expected to be held low or high at different times, which would dictate the difference between rtt_nom and rtt_park being used.

More anecdotally, the fact I can achieve consistently different results by enabling rtt_nom, even when both write and park are also set, also suggests the manual setting is being leveraged in some scenario.


----------



## Netblock

Blameless said:


> Some of my single rank per channel setups don't seem to benefit from rtt_nom being enabled, but that's not a sure thing.
> 
> I'm less clear on single rank, but even then there do seem to be scenarios where ODT could be expected to be held low or high at different times, which would dictate the difference between rtt_nom and rtt_park being used.


Single-rank systems have three states: reads, writes and idle, right? Reads cannot terminate because it is driving; for writes you got RTT_Wr; and idle, Park. There isn't a rank and situation that RTT_Nom could address that you haven't already allocated RTT_Wr or RTT_Park for. You'd need at least a second rank to be idle for RTT_Nom to be practical.




Blameless said:


> All of my dual-rank AM4 systems like all of the termination values to be set.
> As far as these various state tables seem to show, I'm not seeing anything that suggests rtt_nom will not be used, if it has been set, at least as far as multi-rank setups go


Dual-rank via 1DPC do have the state room to use RTT_Nom, but there'd be little to no point cause the second rank impacts signal integrity on the data bus a lot less than 2RPC via 2DPC.

This state table says that the ODT pin won't get asserted high unless there is another DIMM in the channel. That said, looking at AGESA documentation, it seems to be vendor-overrideable; to this degree have we seen any AM4 board, at all, not auto to the usual dis-off-5 / dis-3-1 / 7-3-1?




Blameless said:


> More anecdotally, the fact I can achieve consistently different results by enabling rtt_nom,


What do you mean by results? If you mean performance, there are timings related to RTT engagement; if you're observing them, that's pretty neat.


Or do you mean stability anecdotes? Also how are you configuring the RTT? What happens at dis-3-1; and what happens if you try to configure ProcODT while assuming dis-3-1?

Affects of the RTT and ProcODT should be quite visible on the tRDRD and tWRWR timings, especially SD/DD; are you observing a stability benefit that allows (say) tRDRD SD 4 from 5 with RTT_Nom on a 1DPC 2RPC system?



Anecdotally, for most systems I've seen, RTT doesn't really need to be changed; stock is almost always good enough. ProcODT does need a good look for some reason, however. For what can be gained, most of it is in the command-address bus stuff.


----------



## Snipie-PT

Hey guys,

Long time no posting, wishing everyone an happy new year.
After some time, I got this pretty stable on my side, looking for some suggestions (if any) to improve the timings, or should I leave this as is and forget about it?

Edit: VDIMM is 1.56

Thank you!

BR,


----------



## Imprezzion

Snipie-PT said:


> Hey guys,
> 
> Long time no posting, wishing everyone an happy new year.
> After some time, I got this pretty stable on my side, looking for some suggestions (if any) to improve the timings, or should I leave this as is and forget about it?
> 
> Edit: VDIMM is 1.56
> 
> Thank you!
> 
> BR,
> 
> View attachment 2591500


tWTR maybe? 3-8 should work. I mean, it's super tight and very well optimized as is but that is the only thing I see that could change.


----------



## Frosted racquet

Welp, hahahah... error appeared after 70 cycles. I think I had a similar issue with 5600x 3600 1.5v profile. I played around with *DrvStr values and passed 100 cycles one time. Now I'm wondering if *DrvStr fixed the issue or was it just a fluke and if the error would appear again if I ran the test a second/third time.


----------



## Imprezzion

Frosted racquet said:


> Welp, hahahah... error appeared after 70 cycles. I think I had a similar issue with 5600x 3600 1.5v profile. I played around with *DrvStr values and passed 100 cycles one time. Now I'm wondering if *DrvStr fixed the issue or was it just a fluke and if the error would appear again if I ran the test a second/third time.


I'm sorry but this is just considered stable. A single error after 10h.. it can be literally anything.. and I have some serious doubts a completely stock (DOCP) kit and CPU wouldn't eventually give 1 error even if it's temperature related. If you want 100% guaranteed stability get a threadripper / Intel xeon WS and ECC FB DIMM's. If you want to manually OC and play with stuff, accept it won't always be 100000% stable.

So, here's what I'm testing today. Voltage is.. up there at 1.565v, temps are not great either. 44c in TM5 is not great considering the GPU is not running so no heat from there and the DIMMs are actively cooled and the cooler is at 65% PWM already.. But, unfortunately it needs this much vDIMM for 14 tCL and this low of a tRC and tRFC. That's just the price I pay for not having a 3600C14 kit but a much cheaper, much worse binned, 3600C16 kit.

It runs tPHYRDL properly 26/26, no WHEA's, 6h 30 cycles TM5 1usmus tested overnight last night, was fine.


----------



## Frosted racquet

Imprezzion said:


> I'm sorry but this is just considered stable. A single error after 10h.. it can be literally anything.. and I have some serious doubts a completely stock (DOCP) kit and CPU wouldn't eventually give 1 error even if it's temperature related. If you want 100% guaranteed stability get a threadripper / Intel xeon WS and ECC FB DIMM's. If you want to manually OC and play with stuff, accept it won't always be 100000% stable.


Yep, that's pretty much my reasoning as well. Will play around for a bit with it since I have the time, just out of curiosity.


----------



## Imprezzion

How exactly does ProcODT, RTT's and DrvStr's affect DIMM temperatures and power draw in general? I'm trying to find a setup that has the lowest possible power draw, vDIMM and temperature for 3800C15 for example.

Normally I would run 32Ohm ODT, Disabled-3-1 RTT's with all 24 DrvStr's. But, is there a way to set that up differently for lower vDIMM requirement / temps / power draw?

For example, I have this setup now to test with: (vDIMM 1.420v, yes I know tRFC should be 272, mistyped and yet this has great benchmark scores in AIDA...)


----------



## Netblock

Imprezzion said:


> How exactly does ProcODT, RTT's and DrvStr's affect DIMM temperatures and power draw in general? I'm trying to find a setup that has the lowest possible power draw, vDIMM and temperature for 3800C15 for example.
> 
> Normally I would run 32Ohm ODT, Disabled-3-1 RTT's with all 24 DrvStr's. But, is there a way to set that up differently for lower vDIMM requirement / temps / power draw?
> 
> For example, I have this setup now to test with: (vDIMM 1.420v, yes I know tRFC should be 272, mistyped and yet this has great benchmark scores in AIDA...)
> View attachment 2591551


With optimal strengths and terminations, you should be able to run a lower transmission power (DRAM voltage) as less power is getting reflected and becoming noise.

Having RTT_Nom disabled will have a minor (probably immeasurable) power reduction due to the ODT reciever being turned off.

I also suggest to attack the cad bus a bit more. There's no reason why you can't do 1T-off besides the time-effort sink.


If you're looking for lower temperatures,

Have you shucked the heatspreaders (heatspreaders are often outright worse than naked DIMMs); have you attached a heatsink or waterblock to the DRAM (attach VRAM heatsinks to the memory with a thermally conductive adhesive)?

RGB memory? disable with OpenRGB

Lower VPP? (there's also a separate stability benefit with a lowered VPP (rowhammer); though it might make tRCDRD and tRFC worse)

Is there any single timing that's preventing a lowered DIMM voltage? tCL often ends up being the sole reason a higher voltage is needed.


----------



## klipschorny

Hey everyone, just wondering if absolutnew.cfg is still the go-to TM5 config. 

Also I have two sets of this kit
Crucial Ballistix MAX RGB 16GB Kit (2 x 8GB) DDR4-4400 BLM2K8G44C19U4BL
to make a 4x8 single rank setup 

Anyone with this kit have any screenshots of optimized timings running at 3800 1900 FCLK 1:1 that they could share for a baseline? Preferably on Ryzen 5000 series. I know it's a big ask but gotta try. If someone does have a pic it could save me a few hours.

HAPPY NEW YEARS EVE!


----------



## Imprezzion

Netblock said:


> With optimal strengths and terminations, you should be able to run a lower transmission power (DRAM voltage) as less power is getting reflected and becoming noise.
> 
> Having RTT_Nom disabled will have a minor (probably immeasurable) power reduction due to the ODT reciever being turned off.
> 
> I also suggest to attack the cad bus a bit more. There's no reason why you can't do 1T-off besides the time-effort sink.
> 
> 
> If you're looking for lower temperatures,
> 
> Have you shucked the heatspreaders (heatspreaders are often outright worse than naked DIMMs); have you attached a heatsink or waterblock to the DRAM (attach VRAM heatsinks to the memory with a thermally conductive adhesive)?
> 
> RGB memory? disable with OpenRGB
> 
> Lower VPP? (there's also a separate stability benefit with a lowered VPP (hammer); though it might make tRCDRD and tRFC worse)
> 
> Is there any single timing that's preventing a lowered DIMM voltage? tCL often ends up being the sole reason a higher voltage is needed.


Mostly tCL, tRFC and the tertiaries. tWRRD/tRDRD is real picky and voltage hungry on my DIMM's. It was on Intel and it's no better on AMD.

I made a 3800 16-16-16-36-52-280 baseline profile and that passed 5 hours 1usmus fine at 1.43v at 43c. Benefit is that I can run really low vSOC, VDDG and VDDP. I took a bit of a hit in read write copy but latency is almost the same weirdly enough. Still around 59.6-59.8ns ish which is fine. Yes, I can get down into the low 57's on 3933 straight 15's but it takes such an ungodly amount of voltage across all voltages and extra heat..

My board does not allow lowering of VPP. It has a min. Of 2.500 anything under becomes Auto and a max of 2.800. 

The problem with temps is the fact I have a Nemesis GTX 420 in the front as intake that blows all the hot air from a 400w 3090 and a 5800X3D directly onto the RAM so even with active cooling it doesn't really help. They will run at minimum 44c regardless of voltage or frequency. Even on 3600C16 DOCP 1.35v they go to 44c.


----------



## mongoled

The_King said:


> I am running 1.2.0.7 and Lowering EDC increases my R23 score.
> View attachment 2589233
> 
> View attachment 2589234
> 
> View attachment 2589235


I started a new thread in the "AMD General" section, but no one is posting over there

So........ what CO are you running with that 5800x ?

Got a 5800x off a friend so currently tweaking it, 15900 is my highest score so far, though its all EDC constrained (temps dont break 72C on my custom loop when running R23), for 15900 am using 140A for EDC, do you not loose out on single core max frequencies when you lower the EDC to these values ?

For sure with high intensity stress testing tools such as Prime95, Y-Cruncher, OCCT etc, that these will run at very low frequencies when reducing EDC to such low values.


----------



## marcopx95

Hello everyone !

This is my first post, I don't know much about overclocking but I'm learning. I'm looking for help stabilizing my 4400 mHz CL19 Viper Steel to 3800 CL14.
Based on the post I have this:
VSoC = 1100mV
VDDP = 950mV
VDDG CCD = 1050mV
VDDG IOD = 1050mV
vDIMM = 1.530V
















Is there any chance? Please help


----------



## Frosted racquet

@marcopx95 First stabilize GDM off and 2T command rate. tWR can go lower, 12 for example (2*tRTP)

Are you sure it's 1.1v VSOC since Zentimings reads ~1.2v?


----------



## Imprezzion

@marcopx95 I suspect the ClkDrvStr is far too high at 60. tRC is not optimal, tWRRD/tRDRD maybe too low.. 

Try RTT Disabled, 3, 1 with ClkDrvStr 30-24-24-24, ProcODT 32 or 34.3, timings at 14-15-15-15-35-50-264-2T GDM Off with tRDWR 9 tWRRD 2 or 3, tWR 12, tRTP 6, tWRDRD both 6 and tWRWR both 4, leave the rest as is. That should run fine at about 1.52-1.53v. If that is stable, start by lowering vSOC and VDDG/VDDP as they are seriously high for only 1900 FCLK unless you have WHEA issues already.


----------



## marcopx95

Frosted racquet said:


> @marcopx95 First stabilize GDM off and 2T command rate. tWR can go lower, 12 for example (2*tRTP)
> 
> Are you sure it's 1.1v VSOC since Zentimings reads ~1.2v?


I think so. In BIOS I set 1.1V for sure. 
ZenTimings shows the same VSOC no matter how many I set. When I set over 1.2 it changes in ZenTimings.
Is it wrong?


----------



## Frosted racquet

Then ZenTimings is wrong. Maybe update it to the latest version.


----------



## PJVol

marcopx95 said:


> Is it wrong?


ZenTimings report is correct. There's two confusing fields in ASRock bios. 
The right place is under "External voltage settings and LLC"


----------



## ReyReverse

mongoled said:


> I started a new thread in the "AMD General" section, but no one is posting over there
> 
> So........ what CO are you running with that 5800x ?
> 
> Got a 5800x off a friend so currently tweaking it, 15900 is my highest score so far, though its all EDC constrained (temps dont break 72C on my custom loop when running R23), for 15900 am using 140A for EDC, do you not loose out on single core max frequencies when you lower the EDC to these values ?
> 
> For sure with high intensity stress testing tools such as Prime95, Y-Cruncher, OCCT etc, that these will run at very low frequencies when reducing EDC to such low values.


yea I couldn't agree more low EDC lose all /single performance 
that why I always tell people set your PBO as high as possible to the max. I know my Mobo can handle EDC 205 max cpu and vrm temp hit 88~90c , I will put it max without a doubt, that make my L1 cache hit 4600++mbps, lower PPT TDC EDC will decrease your overall performance. 
since you have that amazing decent cooling system temp only hit 72c you should go over 140A , just smash it to 200A hahaha


----------



## Giacomo Coppi

Giacomo Coppi said:


> I had some time during those christmas days to play a bit with my setup and i managed to tune a bit 2 different profile i have while still trying to boot 4000mhz without success.
> 
> View attachment 2591179
> 
> 
> my scores on aida64 test seems a bit low to me , shouldn't i get 57k read and 55k copy at least ?
> Ram voltage is flat 1.5v and mem vtt is 0.75v
> the cpu is actually stock and no pbo2 is going on .
> i tryed to follow a guide on github and i have to test twr at 10 and tcwl at 13 or 12 .
> Trcdrd at14 gave me errors on 1usmus_v3
> tPHYRDL is 26/28 , i can get 26/26 if i set 2t geardown disabled , 1t geardown disabled no boot and i need clrcmos to boot again in bios.
> 
> Any advice to make some further improvements will be much appreciated, good day to everyone












I actually been able to lower trfc to 265 , still no boot 1t for tphyrdl 26/26 , only works in 2T


----------



## mongoled

ReyReverse said:


> yea I couldn't agree more low EDC lose all /single performance
> that why I always tell people set your PBO as high as possible to the max. I know my Mobo can handle EDC 205 max cpu and vrm temp hit 88~90c , I will put it max without a doubt, that make my L1 cache hit 4600++mbps, lower PPT TDC EDC will decrease your overall performance.
> since you have that amazing decent cooling system temp only hit 72c you should go over 140A , just smash it to 200A hahaha


As I am using the latest agesa (1.2.0.7) anything over 140A on EDC means vCore gets capped to 1.425v instead of the 1.5v. This means that you loose the single core boost and loose multithread frequency.

I will probably stay on this BIOS in the hope they actually fix this issue on the next Agesa. I could always drop to a earlier agesa, but will see what I can get out this CPU on this agesa and decide after if I am to go to an older BIOS.


----------



## The_King

mongoled said:


> I started a new thread in the "AMD General" section, but no one is posting over there
> 
> So........ what CO are you running with that 5800x ?
> 
> Got a 5800x off a friend so currently tweaking it, 15900 is my highest score so far, though its all EDC constrained (temps dont break 72C on my custom loop when running R23), for 15900 am using 140A for EDC, do you not loose out on single core max frequencies when you lower the EDC to these values ?
> 
> For sure with high intensity stress testing tools such as Prime95, Y-Cruncher, OCCT etc, that these will run at very low frequencies when reducing EDC to such low values.


Something went wrong with PBO has a result of changing PPT/TDC/EDC. Did not find the exact cause yet.

My best R23 score so far is a 16277 running a dual tower air cooler. Wanted to break 17K lol but still around 750 points away from that,
here is the settings i used -30 on all the cores. @Luggage any tips on how to break 17K or increase my score?

All cores locked to 4675 @ 1.4V

















Gambit`s Cinebench - R23 Multi Core with BenchMate score: 16277 cb with a Ryzen 7 5800X


The Ryzen 7 5800X @ 4675.3MHzscores getScoreFormatted in the Cinebench - R23 Multi Core with BenchMate benchmark. Gambitranks #200 worldwide and #73 in the hardware class. Find out more at HWBOT.




hwbot.org


----------



## ReyReverse

mongoled said:


> As I am using the latest agesa (1.2.0.7) anything over 140A on EDC means vCore gets capped to 1.425v instead of the 1.5v. This means that you loose the single core boost and loose multithread frequency.
> 
> I will probably stay on this BIOS in the hope they actually fix this issue on the next Agesa. I could always drop to a earlier agesa, but will see what I can get out this CPU on this agesa and decide after if I am to go to an older BIOS.


oh yea 1.425v cap but 1203c also have soc current bug issue, it draw my soc current to 90A that mean my soc power all the way draw over 100watt , plus my CPU package power in total draw over 300watt, that's crazy. 
I don't know will they release new agesa on am4 or not. since they want to push AM5


----------



## PJVol

ReyReverse said:


> it draw my soc current to 90A


How to you know this?


----------



## marcopx95

Imprezzion said:


> @marcopx95 I suspect the ClkDrvStr is far too high at 60. tRC is not optimal, tWRRD/tRDRD maybe too low..
> 
> Try RTT Disabled, 3, 1 with ClkDrvStr 30-24-24-24, ProcODT 32 or 34.3, timings at 14-15-15-15-35-50-264-2T GDM Off with tRDWR 9 tWRRD 2 or 3, tWR 12, tRTP 6, tWRDRD both 6 and tWRWR both 4, leave the rest as is. That should run fine at about 1.52-1.53v. If that is stable, start by lowering vSOC and VDDG/VDDP as they are seriously high for only 1900 FCLK unless you have WHEA issues already.


It looks mutch more stable. But...










Set higher procOdt or should i try with lower vSOC etc?


----------



## The_King

marcopx95 said:


> It looks mutch more stable. But...
> View attachment 2591852
> 
> 
> 
> Set higher procOdt or should i try with lower vSOC etc?


Your RAM is showing 4400 C18? If that is correct it can't be a 4400 C19 kit.
Can you confirm what is the XMP profile on that kit with CPU-Z or Thaiphoon burner?


----------



## mongoled

Here is a screen shot of my values when I was using 2x8GB Viper Steels 4400mhz dimms.

This is one of the "loosest" timings I have saved. Use it to compare to your current settings, dont copy these settings directly as you dimms may not be able to run these settings ...


----------



## mongoled

The_King said:


> Your RAM is showing 4400 C18? If that is correct it can't be a 4400 C19 kit.
> Can you confirm what is the XMP profile on that kit with CPU-Z or Thaiphoon burner?


Good catch!

The Patriot Viper 4 Blackout DDR4-4400 are C18


----------



## marcopx95

The_King said:


> Your RAM is showing 4400 C18? If that is correct it can't be a 4400 C19 kit.
> Can you confirm what is the XMP profile on that kit with CPU-Z or Thaiphoon burner?





mongoled said:


> Good catch!
> 
> The Patriot Viper 4 Blackout DDR4-4400 are C18


I bought Viper Steel but actually my kit are 18-26-26-46 on XMP profile...
Kit look like viper steel.The packaging was fine too. 
How is this possible?


----------



## mongoled

marcopx95 said:


> I bought Viper Steel but actually my kit are 18-26-26-46 on XMP profile...
> Kit look like viper steel.The packaging was fine too.
> How is this possible?


This is your kit, correct ??



https://assets.website-files.com/5cdb2ee0b102f96c3906500f/6140d6fc7a6987508a104c33_PVS416G440C9K_Sku%20Sheet_050421.pdf



Did you buy them from ebay ?


----------



## The_King

marcopx95 said:


> I bought Viper Steel but actually my kit are 18-26-26-46 on XMP profile...
> Kit look like viper steel.The packaging was fine too.
> How is this possible?


Can you post Thaiphoon burner screen of those dimms.


Thaiphoon Burner - Official Support Website



It seems 100% the kit is Samsung B-die from the timings you are currently doing but curious to see what the specs are in Thaiphoon burner.
Here is a screenshot of my 4400 C19 in Thaiphoon burner


----------



## ReyReverse

PJVol said:


> How to you know this?


huh~ I believe there is many software can monitor voltage and temp? example the software start with Hxxxxx
lol


----------



## ReyReverse

mongoled said:


> Here is a screen shot of my values when I was using 2x8GB Viper Steels 4400mhz dimms.
> 
> This is one of the "loosest" timings I have saved. Use it to compare to your current settings, dont copy these settings directly as you dimms may not be able to run these settings ...
> 
> View attachment 2591853


beautiful, power reporting deviation under 4 hours test Max at 177.9% and minimum still got 99% so perfect.


----------



## Imprezzion

Hmm, 18-26-26 does not sound like B-Die at all. However the current tRFC you're running means it has to be either b or c die Samsung. No way hynix or micron can do ~140ns at that speed...






Ryzen Google Calculator! - Google Drive







docs.google.com





It was a error 0 so might be fixed with just 1 tick more vDIMM 1.540v or dropping tWRRD tRDRD to 10/4 for example. Error 0 usually isn't all that serious or hard to fix.


----------



## marcopx95

The_King said:


> Can you post Thaiphoon burner screen of those dimms.
> 
> 
> Thaiphoon Burner - Official Support Website
> 
> 
> 
> It seems 100% the kit is Samsung B-die from the timings you are currently doing but curious to see what the specs are in Thaiphoon burner.
> Here is a screenshot of my 4400 C19 in Thaiphoon burner
> View attachment 2591857


Interesting...


----------



## The_King

marcopx95 said:


> Interesting...
> View attachment 2591869


I did manage to find a review here.
It seems its Patriot Viper Blackout series and not the Steel series if they look like the dimms in the picture on Tomshardware.


https://www.tomshardware.com/reviews/patriot-viper-4-blackout-ddr4-4400-c18-2x8gb-review



Performance is very similar to the Steel series. The Blackout series actually runs cooler than the steel series from what I heard because the heat-sinks are better.

It also seems that All patriot Viper Blackout 4000/4133/4266/4400 are all Samsung B-die.
















*PVB416G400C9K*


----------



## marcopx95

So, my kit is a Viper Blackout but its look like Viper Steel?
The weird thing is I was definitely buying viper steel and a box and the appearance says I got what I bought.


----------



## The_King

marcopx95 said:


> So, my kit is a Viper Blackout but its look like Viper Steel?
> The weird thing is I was definitely buying viper steel and a box and the appearance says I got what I bought.


Could be a limited editon thing or someone changed the heatsinks and then sold them to you. Either way it seems to be a good bin Samsung B-die kit.
Did you buy this new from a PC Shop / online or second hand / E-bay?


----------



## marcopx95

The_King said:


> Could be a limited editon thing or someone changed the heatsinks and then sold them to you. Either way it seems to be a good bin Samsung B-die kit.
> Did you buy this new from a PC Shop / online or second hand / E-bay?


Yes, new from pc shop. That's why I was surprised.
Anyway, I have stable timings so thanks to all for help!


----------



## PJVol

ReyReverse said:


> huh~ I believe there is many software can monitor voltage and temp? example the software start with Hxxxxx
> lol


I believe also some people often post things starts with BULL****
lol


----------



## MagmaTET

Hey, do someone know why my motherboard (B550-M prime A wifi) with Ryzen 7 5800X brick himself when i try more than 3200Mhz memory ? i need to remove cmos battery to boot the pc after


----------



## Netblock

Giacomo Coppi said:


> View attachment 2591845
> 
> 
> I actually been able to lower trfc to 265 , still no boot 1t for tphyrdl 26/26 , only works in 2T


To attack GDM off 1T, I suggest checking out this little guide. A place to start is to copy what I have; set DrvStr 20-30-40-24 and setup 59-45-0.
You might need to raise SOC (maybe not); and you might need to lower ProcODT (though if you've figured out that 43.6 is best stay with that).




marcopx95 said:


> It looks mutch more stable. But...
> View attachment 2591852
> 
> 
> 
> Set higher procOdt or should i try with lower vSOC etc?



If PG velocita has a similar topology to B550 pro4, you might prefer 40 ohms ProcODT; maybe 36.9. Also you should be able to run 1T-off; try DrvStr 60-20-24-24 might be good enough, and if it isn't, playing with AddrCmdSetup will definitely help (try 59? Also check out the guide I linked above).

If AddrCmdSetup of 59 hurts stability, you might have some luck lowering ClkDrvStr, and maybe raising AddrCmdDrvStr.


----------



## Frosted racquet

Frosted racquet said:


> Welp, hahahah... error appeared after 70 cycles. I think I had a similar issue with 5600x 3600 1.5v profile. I played around with *DrvStr values and passed 100 cycles one time. Now I'm wondering if *DrvStr fixed the issue or was it just a fluke and if the error would appear again if I ran the test a second/third time.





Imprezzion said:


> I'm sorry but this is just considered stable. A single error after 10h.. it can be literally anything.. and I have some serious doubts a completely stock (DOCP) kit and CPU wouldn't eventually give 1 error even if it's temperature related. If you want 100% guaranteed stability get a threadripper / Intel xeon WS and ECC FB DIMM's. If you want to manually OC and play with stuff, accept it won't always be 100000% stable.


Managed to figure it out. tCKE was at fault, changing it from 7 to 8 eliminated the random single errors. Universal2 profile threw a single error in 10 cycles, much quicker than 1usmus profile after 70+ cycles.


----------



## Netblock

Frosted racquet said:


> Managed to figure it out. tCKE was at fault, changing it from 7 to 8 eliminated the random single errors. Universal2 profile threw a single error in 10 cycles, much quicker than 1usmus profile after 70+ cycles.
> View attachment 2591897
> View attachment 2591898
> View attachment 2591896



What happens if you set tCKE to 1?

Also you can very much obtain 1T-off if you mess with the cad bus stuff. Check out the mini-guide in an earlier comment of mine.

(GDM on I believe should be more performant than GDM off 2T)


----------



## Luggage

The_King said:


> Something went wrong with PBO has a result of changing PPT/TDC/EDC. Did not find the exact cause yet.
> 
> My best R23 score so far is a 16277 running a dual tower air cooler. Wanted to break 17K lol but still around 750 points away from that,
> here is the settings i used -30 on all the cores. @Luggage any tips on how to break 17K or increase my score?
> 
> All cores locked to 4675 @ 1.4V
> View attachment 2591847
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> Gambit`s Cinebench - R23 Multi Core with BenchMate score: 16277 cb with a Ryzen 7 5800X
> 
> 
> The Ryzen 7 5800X @ 4675.3MHzscores getScoreFormatted in the Cinebench - R23 Multi Core with BenchMate benchmark. Gambitranks #200 worldwide and #73 in the hardware class. Find out more at HWBOT.
> 
> 
> 
> 
> hwbot.org


Higher boost, lower limits, lower ambient.




http://imgur.com/a/YcebAwL


Manual all core testing last winter
Edit: you need 4.9 all core for 17k



http://imgur.com/a/YK3ZFmz


----------



## Luggage

mongoled said:


> I started a new thread in the "AMD General" section, but no one is posting over there
> 
> So........ what CO are you running with that 5800x ?
> 
> Got a 5800x off a friend so currently tweaking it, 15900 is my highest score so far, though its all EDC constrained (temps dont break 72C on my custom loop when running R23), for 15900 am using 140A for EDC, do you not loose out on single core max frequencies when you lower the EDC to these values ?
> 
> For sure with high intensity stress testing tools such as Prime95, Y-Cruncher, OCCT etc, that these will run at very low frequencies when reducing EDC to such low values.


Yo!









OFFICIAL 5900X and 5950X two chiplet Zen 3 CPUs...


Agree, was just trying to be polite. Going all the way back to the Athlon 2500+ people have been running unstable clocks that "don't crash". PBO stability testing has improved drastically now that the boost limit can be lowered in BIOS. It can be done, I did for a while cause I was lazy and...




www.overclock.net







also



http://imgur.com/a/6W2DN47


+200 curve is



http://imgur.com/keLaSoN


----------



## Imprezzion

Netblock said:


> What happens if you set tCKE to 1?
> 
> Also you can very much obtain 1T-off if you mess with the cad bus stuff. Check out the mini-guide in an earlier comment of mine.
> 
> (GDM on I believe should be more performant than GDM off 2T)


It wasn't directed at me but allow me to hook into this please. I am running tCL 15 so can't use GDM 1T however, 1T GDM Off is stable for me error wise but it performs actually worse in most tests then 2T. Any idea how this can be? This same happens on both 3800 and 3866.. I also tested with 3600 and same again, 1T performs worse then 2T in AIDA / Y-cruncher RAM only test somehow...


----------



## Netblock

Imprezzion said:


> however, 1T GDM Off is stable for me error wise but it performs actually worse in most tests then 2T. Any idea how this can be?


tPHYRDL 26/26? You might be doing 28 on one of the channels; and although extremely rare, also might be reaching 24. 

(lower is better. I'm not sure if desyced is better than universally higher; I'm not sure if 26/28 is better or worse than 28/28.)


----------



## ReyReverse

PJVol said:


> I believe also some people often post things starts with BULL****
> lol


Lol beginner xmp overclocker


----------



## mongoled

Luggage said:


> Yo!
> 
> 
> 
> 
> 
> 
> 
> 
> 
> OFFICIAL 5900X and 5950X two chiplet Zen 3 CPUs...
> 
> 
> Agree, was just trying to be polite. Going all the way back to the Athlon 2500+ people have been running unstable clocks that "don't crash". PBO stability testing has improved drastically now that the boost limit can be lowered in BIOS. It can be done, I did for a while cause I was lazy and...
> 
> 
> 
> 
> www.overclock.net
> 
> 
> 
> 
> 
> 
> 
> also
> 
> 
> 
> http://imgur.com/a/6W2DN47
> 
> 
> +200 curve is
> 
> 
> 
> http://imgur.com/keLaSoN


Cheers bud, I posted in the thread I created


----------



## Imprezzion

Netblock said:


> tPHYRDL 26/26? You might be doing 28 on one of the channels; and although extremely rare, also might be reaching 24.
> 
> (lower is better. I'm not sure if desyced is better than universally higher; I'm not sure if 26/28 is better or worse than 28/28.)


It's on 26/28 on 1T and 26/26 on 2T so that might explain. If it's the same workings as RTL/IO with Intel it has to be synced otherwise performance will be horrible. Then again, my best performing profile of 3933C15 1T GDM On is still 26/28..

Oh well. This board is just weird like that with memory. I have never gotten it to work properly ever since I got the board. This is what I daily now and the scores it gets. It's not too shabby considering the very low vSOC/VDDG/VDDP requirement for WHEA free operation. vDIMM = 1.500v. It can run 1.470v with a little looser tRFC and tWRRD but why would I. Temps are basically the same so..


----------



## GhOsT662

Any ideas on how to fix these errors on a 16gb kit

VDIMM 1.45
ProcOdt 36.9
RRttNom RZQ/7
RttWr RZQ/3
RttPark RZQ/5

ClkDrvStr 60
AddrCmdSetup 20
CsOdtDrvStren 24
CkeDrvStren 24

AddrCmdSetup 0
CsOdtSetup 0
CkeSetup 0


----------



## nada324

Hey all, what would you improve from here? 

Using @1.52v Vdimm, tried lowering TRCDRD to 15 long time ago, but nope, i got bad luck with my vipers bin


----------



## PJVol

nada324 said:


> what would you improve from here?


Improve compared to what? Numbers by themselves mean nothing.
Care to be specific about the baseline?

Purely guessing:
tRCD 15, tRAS 30, tRC 45, tWRRD 2


----------



## Netblock

Imprezzion said:


> It's on 26/28 on 1T and 26/26 on 2T so that might explain. If it's the same workings as RTL/IO with Intel it has to be synced otherwise performance will be horrible. Then again, my best performing profile of 3933C15 1T GDM On is still 26/28..
> 
> Oh well. This board is just weird like that with memory. I have never gotten it to work properly ever since I got the board. This is what I daily now and the scores it gets. It's not too shabby considering the very low vSOC/VDDG/VDDP requirement for WHEA free operation. vDIMM = 1.500v. It can run 1.470v with a little looser tRFC and tWRRD but why would I. Temps are basically the same so..
> 
> View attachment 2591948
> View attachment 2591949


Why not 1T-off with that 3933? Haven't sunk in that effort?

You can 'lower' tWRRD if you lowered tCWL from tCL. 



For how AMD defines them, tRDWR has a+LD and tWRRD has b-LD, where LD = tCL - tCWL.
a and b are personal simplifications of other things that get considered, but they tend to be often a=8, b<4

AMD's definition of tRDWR/tWRRD and every single tRDRD/tWRWR has a very similar wording to this:
tRDWR: _Specifies the minimum number of clock cycles from the last clock of virtual CAS of a first read-burst operation to the clock in which CAS is asserted for a following write-burst operation_.
This means a value of 1 means tCCD=4; a value of 2 means tCCD=5.


----------



## Imprezzion

Netblock said:


> Why not 1T-off with that 3933? Haven't sunk in that effort?
> 
> You can 'lower' tWRRD if you lowered tCWL from tCL.
> 
> 
> 
> For how AMD defines them, tRDWR has a+LD and tWRRD has b-LD, where LD = tCL - tCWL.
> a and b are personal simplifications of other things that get considered, but they tend to be often a=8, b<4
> 
> AMD's definition of tRDWR/tWRRD and every single tRDRD/tWRWR has a very similar wording to this:
> tRDWR: _Specifies the minimum number of clock cycles from the last clock of virtual CAS of a first read-burst operation to the clock in which CAS is asserted for a following write-burst operation_.
> This means a value of 1 means tCCD=4; a value of 2 means tCCD=5.


Well, there's a bit of a voltage wall at 1933 FCLK. For 1967 I have to go from 1.09 vsoc to 1.21 and VDDG from 0.98 to 1.07 to not get WHEA's. Not really worth it tbh. So I don't daily 3933. 3866 tCL 14 is perfectly doable if my DIMM's didn't get as hot as they do now. I sit around 43-44c while gaming with the GPU heat and for tCL 14 I need 1.565v vDIMM which means 47-48c and that won't ever survive the summer.


----------



## Netblock

Imprezzion said:


> Well, there's a bit of a voltage wall at 1933 FCLK. For 1967 I have to go from 1.09 vsoc to 1.21 and VDDG from 0.98 to 1.07 to not get WHEA's. Not really worth it tbh. So I don't daily 3933. 3866 tCL 14 is perfectly doable if my DIMM's didn't get as hot as they do now. I sit around 43-44c while gaming with the GPU heat and for tCL 14 I need 1.565v vDIMM which means 47-48c and that won't ever survive the summer.


Probably a PLL hole. BCLK? My Matisse will refuse to boot at 1900MHz FCLK without similarly insane voltages, so I daily a 101.9375MHz BCLK with a 56/3 multiplier into 3805/1902.8.
(I heard someone saying lowering the 1.8v/PLL rail helped them stablise their Vermeer at 2000. I have yet to play with that)

If you sometimes are able to do 26/26 on 1T-off and are having weird issues where it goes to like 28/26, command rate 1T-2T-1T with reboots back-to-back will cause it to retrain. If that doesn't solve, that suggests instability elsewhere. VDDP being dumb and not applying correctly?


(Not relevant to this convo, but last night I had a 22 minute pass of y-cruncher (FFT~C17+FFT) with PowerDown on, with tCKE 1, CkeDrvStr 120, CkeSetup 42)


----------



## Imprezzion

Netblock said:


> Probably a PLL hole. BCLK? My Matisse will refuse to boot at 1900MHz FCLK without similarly insane voltages, so I daily a 101.9375MHz BCLK with a 56/3 multiplier into 3805/1902.8.
> (I heard someone saying lowering the 1.8v/PLL rail helped them stablise their Vermeer at 2000. I have yet to play with that)
> 
> If you sometimes are able to do 26/26 on 1T-off and are having weird issues where it goes to like 28/26, command rate 1T-2T-1T with reboots back-to-back will cause it to retrain. If that doesn't solve, that suggests instability elsewhere. VDDP being dumb and not applying correctly?
> 
> 
> (Not relevant to this convo, but last night I had a 22 minute pass of y-cruncher (FFT~C17+FFT) with PowerDown on, with tCKE 1, CkeDrvStr 120, CkeSetup 42)


BCLK is good up to 102.3. I'll play around with it a bit later tonight. I'm grinding in Tiny Tina's Wonderland at the moment hehe.


----------



## Artylol

I have started project of evaluating lowest voltage required for given mode of RAM operation. I know by fact that:

XMP 4000CL16 (8ns) works at 1.45VDIMM 
OC 3600FLAT14Tight (7.78ns) works at 1.45VDIMM (maybe less)








OC 3733FLAT14Tight (7.50ns) works at 1.51VDIMM (not minimized yet)









OC 3800FLAT15Tight (7.87ns) works at 1.45VDIMM 










OC 3866FLAT15Tight (7.76ns) does not work at 1.46VDIMM. *The problem is here. *According to math, I should be able to run 7.76ns at 1.45VDIMM, but in reality it spits out errors depending on RTT's after 1-3 hours of 1usmum v3 even at 1.46VDIMM









I suspect that the fact that I can't run same timings-in-ns at higher frequency is caused by signal integrity issues. I not sure where to look from this point. @Veii do you have ideas about that? Or do I just need to bump up the voltage.


----------



## Veii

Artylol said:


> I not sure where to look from this point. @Veii do you have ideas about that? Or do I just need to bump up the voltage.


SCL 4
RRDL 5
tWR 24
procODT 30

on all of your attempts you keep SOC very close to VDDG IOD
Its hard to differentiate mem issues from CPU issues on your examples


----------



## Artylol

Veii said:


> SCL 4
> RRDL 5
> tWR 24
> procODT 30
> 
> on all of your attempts you keep SOC very close to VDDG IOD
> Its hard to differentiate mem issues from CPU issues on your examples


Uhm, so 60mv is not enough? I thought minimum is 40mv... 

Will try your suggestion on 1.45VDIMM


----------



## Veii

Artylol said:


> Uhm, so 60mv is not enough? I thought minimum is 40mv...


42, but that's GET value, on load
on dual CCDs it's near 60 ~ 75mV delta is better as it factors for droop and efficiency loss by heat

Main issue is surely 2ndary and tertiaries
#3 is mirror move error (between banks/bank groups)
#6 is voltage issue or IMC issue ~ in both cases "underpowered"

The higher you go in MT/s the higher the strain is, even at similar MT/s levels
4200 C15 = 7.142ish ns
4267 C15 (7.03)
3800 C13 (6.84) , C14 (7.3)

Yet 3800 C13 should be slightly easier to run than 4200 C15-15


Artylol said:


> Uhm, so 60mv is not enough? I thought minimum is 40mv...
> 
> Will try your suggestion on 1.45VDIMM


If nothing works, put back Park /6
I think /7 is too low under 1.6v, especially when those are on hungry A2 PCB


----------



## The_King

nada324 said:


> Hey all, what would you improve from here?
> 
> Using @1.52v Vdimm, tried lowering TRCDRD to 15 long time ago, but nope, i got bad luck with my vipers bin
> 
> View attachment 2592013


Firstly have you tried swapping your dimm slot position. 

I have yet to come across a patriot Viper kit that cant do 3800 CL15-15-15-30-45 between 1.44V to 1.46V.

My 4133 C19 Kit is also Avg compared to my other kits but this should be possible.


----------



## Artylol

@Veii









got through 50+ cycles, no errors so far with your corrections. Should I proceed further and tighten timings or reduce VDIMM to 1.45V? 



Veii said:


> Main issue is surely 2ndary and tertiaries
> #3 is mirror move error (between bank groups)
> #6 is voltage issue or IMC issue ~ in both cases "underpowered"


My experience is that pure lack of voltage results in errors 1 and 6 (and maybe 12) in my setup. So I increase VDIMM 1 step and they are gone. Well if its IMC issue, should I increase/reduce VSOC? or just changing procODT was probably enough?


Veii said:


> If nothing works, put back Park /6
> I think /7 is too low under 1.6v, especially when those are on hungry A2 PCB


Can try in further iterations, depending on further steps.


----------



## Veii

Artylol said:


> Can try in further iterations, depending on further steps.


Further target is, RTP up and RAS as = tRTP + RCD
RC logically as RP+RAS

Further further goal is, tWRRD to 1 - to have less delay between ended writes to reads
Writes can be instant on AMD , nearly zero delay instant - but the reasoning is bigger.
tWR by JEDEC's illustrated "work behavior" is:

tCAS + tRRD_ (highest) + tBurstChop (4) // translated & simplified
... (*-0 if *[CWL is -2 of CAS], *-1 if* [CWL is -1 of CAS], *-2 if *[CAS = CWL])
soo 15 + 5 + 4 = 24 , potentially 23
tCWL like tRC are virtual timings, tCWL there to trigger timed shadow refreshes.

Soo because writes are pretty much instant, a lower tCWL barely does anything for us on AMD ~ vs on intel.
The ability to lower tRCDWR down BurstLength 8 (actually should be able to 4 but...)
Is enough & tCWL is only used for efficiency.

tCWL matching tRCDWR , would be hard
And pushing RDWR delay even higher , would hurt minimum-write triggerable delay past reads.
It might not matter by AMDs FW design, but i am not sure how far you can scale tCWL - 2 = tRDWR +2 

I dont think this will run for you and it's not perfect either








Next target is to lower SC, SD, DD, WRWRSCL, tWRRD to the lowest possible
SD, DD lowering means increase in RRD_, WTR_
SC increase can mean SCL decrease.
But this post has become more speculation options, than direct help
You'll figure it out ~ always test the result not what is lowest-autocorrected stable


----------



## Taraquin

Netblock said:


> Why not 1T-off with that 3933? Haven't sunk in that effort?
> 
> You can 'lower' tWRRD if you lowered tCWL from tCL.
> 
> 
> 
> For how AMD defines them, tRDWR has a+LD and tWRRD has b-LD, where LD = tCL - tCWL.
> a and b are personal simplifications of other things that get considered, but they tend to be often a=8, b<4
> 
> AMD's definition of tRDWR/tWRRD and every single tRDRD/tWRWR has a very similar wording to this:
> tRDWR: _Specifies the minimum number of clock cycles from the last clock of virtual CAS of a first read-burst operation to the clock in which CAS is asserted for a following write-burst operation_.
> This means a value of 1 means tCCD=4; a value of 2 means tCCD=5.


When I run flat 14 at 3800 my SR kit prefers RDWR 7, WRRD 1, often trains to that on auto. At flat 15 it likes 8/1, same at flat 16. Good match fpr the CL vs CWL rule. If there is a difference of -1 on CWL then RDWR must be +1.


----------



## Artylol

I tested 100 cycles of your initial suggestion, no errors.



Veii said:


> Further target is, RTP up and RAS as = tRTP + RCD
> RC logically as RP+RAS


What do you mean by that? I should increase RTP to meet a formula? Would not it reduce performance? I will try for sure, but I don't understand reasoning



Veii said:


> Further further goal is, tWRRD to 1 - to have less delay between ended writes to reads
> Writes can be instant on AMD , nearly zero delay instant - but the reasoning is bigger.


Will do and report back



Veii said:


> tWR by JEDEC's illustrated "work behavior" is:
> 
> tCAS + tRRD_ (highest) + tBurstChop (4) // translated & simplified
> ... (*-0 if *[CWL is -2 of CAS], *-1 if* [CWL is -1 of CAS], *-2 if *[CAS = CWL])
> soo 15 + 5 + 4 = 24 , potentially 23


Again, is that really better than 10, 12 or 14 in your experience even if you can run it twice lower? 
I can reach 94.6% of theoretical DDR4 read speeds, while your setup reaches ~93.6%.



Veii said:


> tCWL like tRC are virtual timings, tCWL there to trigger timed shadow refreshes.
> 
> Soo because writes are pretty much instant, a lower tCWL barely does anything for us on AMD ~ vs on intel.
> The ability to lower tRCDWR down BurstLength 8 (actually should be able to 4 but...)
> Is enough & tCWL is only used for efficiency.
> 
> tCWL matching tRCDWR , would be hard
> And pushing RDWR delay even higher , would hurt minimum-write triggerable delay past reads.
> It might not matter by AMDs FW design, but i am not sure how far you can scale tCWL - 2 = tRDWR +2


My understanding is that tRCDWR, and tCWL do not really matter for performance. Probably moreso on single CCD that dual CCD because of IF write bottleneck.


Veii said:


> Next target is to lower SC, SD, DD, WRWRSCL, tWRRD to the lowest possible
> SD, DD lowering means increase in RRD_, WTR_
> SC increase can mean SCL decrease.
> But this post has become more speculation options, than direct help
> You'll figure it out ~ always test the result not what is lowest-autocorrected stable


My understanding that I should lower each one of them step by step, test for stability and also test for performance increase (or decrease for that matter).


----------



## PJVol

Netblock said:


> AMD's definition of tRDWR/tWRRD and every single tRDRD/tWRWR has a very similar wording to this:
> tRDWR: _Specifies the minimum number of clock cycles from the last clock of virtual CAS of a first read-burst operation to the clock in which CAS is asserted for a following write-burst operation_.
> This means a value of 1 means tCCD=4; a value of 2 means tCCD=5.


What "_virtual CAS_" suppose to mean? Aren't there only DES between RD and WR CAS?


















Acc. to specs:
tRDWR is LD + BL/2 +1+tWPRE, i.e.* LD + 6*
tWRRD is CWL + BL/2 + WTR_L(S), i.e. *CWL + WTR_S + 4*

Even AMD's own calculations hardly give you Twrrd 1 or 2 ):
(from their UMC#CH#DramTiming10 manual)
_Trdwr = phy_rdcsgap(2) + CDD_RW + LD 
Twrrd = phy_wrcsgap(4) + CDD_WR - LD + 2_
(_CDD_RW_ and _CDD_WR _are the values returned by PMU after init and training, which for example could be equal to CCD_S and CCD_L).
Could anyone clarify this? )

EDIT: found it in an old 16h BKDG for the DDR3, but it probably has the answer to my own question:
_The Critical Delay Difference (CDD) is the largest delay difference of the channel:
CDD_WR is WrDqsGrossDly (0.5 - 3.5 mclk) minus DqsRcvEnGrossDelay (0 - 15.5 mclk) and
CDD_RW is DqsRcvEnGrossDelay minus WrDqsGrossDly._

So it looks like CDD_WR could be a negative number, giving something like Twrrd 1 or 2 indeed.

-----------------------------------------
Two things worth noting from the above:
1. AMD's Twrrd is probably not JEDEC's Write to Read command spacing, which is the
_- "total number of clock cycles from a WRITE command to a READ command_".
what AMD specified looks more like tWTR (though I may be wrong here)
- _"Write-to-read turn around time (tWTR) specifies how much time must elapse from the last bit of the write data burst prior to a READ command being issued."_
To be fair both timings are not part of the SPD ROM-based config, so the values one put in an UMC registers just used to program DFI, unlike other timings passed directly to the PHY.
2. It's never a bad idea to increase tRDWR *one CK up* as it may greatly improve RAM stability, same goes for tWRRD. Xilinx engineers mentioned JEDEC trdwr spec as too tight (see the 1st diagram).





Documentation Portal







docs.xilinx.com


----------



## Artylol

@Veii 
I tried tWWRD=1 and reducing VDIMM from 1.46V to 1.45V *simultaneously*. Idea is to try if both changes introduce error, then try one by one. Or if no errors, then proceed further. I understand why its dumb, but it is much faster if it works. Here is the result:









after 20-30 minutes (probably) Error#5=Error#3 appears to be related to tWRRD, so I will try again with tWWRD=2 and VDIMM=1.45V in next 24 hours. I don't leave computer working overnight, thats why so long.


----------



## byDenoso

Veii said:


> I have them on enabled, and if your CBS allows it - enforce BGSAlt to enable
> It gives you a HEX value to further play with
> If your's is different, we maybe can align it


Hi!
What Hexi canplay with it?

When i set BGS ALT do "Enabled (3F8 Hex)" i have less bandwidith than with "Auto", i've tried with 400, 800 and 200 but with no sucess.
Can you Help me?


----------



## CoffeeCake

Has anyone actually benched FCLKs higher than 1900? Buildzoid assumes that a FCLK higher than 1900 (without the occurence of WHEAs) operates in a different mode, silently correcting errors, resulting in a lower performance than a FCLK of 1866 and so on. Looking at hwbot results seem to confirm this assumption. Is it even worth it to go higher than 1900?


----------



## Imprezzion

CoffeeCake said:


> Has anyone actually benched FCLKs higher than 1900? Buildzoid assumes that a FCLK higher than 1900 (without the occurence of WHEAs) operates in a different mode, silently correcting errors, resulting in a lower performance than a FCLK of 1866 and so on. Looking at hwbot results seem to confirm this assumption. Is it even worth it to go higher than 1900?


What kinda benches do you have in mind? My 5800X3D's CB R23 scores, game benchmark scores (SotTR, Division 2, Cyberpunk) and AIDA64 Memory / Cache scores scale very well from 1900 to 1967. I daily 1933 actually but performance is great.


----------



## CoffeeCake

Imprezzion said:


> What kinda benches do you have in mind? My 5800X3D's CB R23 scores, game benchmark scores (SotTR, Division 2, Cyberpunk) and AIDA64 Memory / Cache scores scale very well from 1900 to 1967. I daily 1933 actually but performance is great.


I'm aware that aida64 bandwith / latency improves, but it' doesn't seem to be representative for other benchmarks like linpack, pyprime, super pi, ycruncher 2.5b, 3dmark cpu.


----------



## The_King

Some interesting AIDA64 numbers. ( No Boost override )

3800 CL14 @ 1.54V

















3866 CL15 @ 1.46V
















4000 CL17 @ 1.48V


----------



## Netblock

Taraquin said:


> Good match fpr the CL vs CWL rule. If there is a difference of -1 on CWL then RDWR must be +1.


Well, I got it from AMD documentation.



PJVol said:


> What "_virtual CAS_" suppose to mean? Aren't there only DES between RD and WR CAS?


The last clock of virtual CAS is defined as BL/2-1.
AMD defines tRDRD/tWRWR SC timings to be JEDEC tCCD_S - 3.
For DDR4, JEDEC tCCD_S is always 4 no matter the speed bin. For DDR4, tCCD of 4 means 0 idle clock cycles on the data bus.
AMD's wording for tRDWR description is extremely similar to tRDRD SC.

My understanding is as follows:

That an AMD data bus timing of 1 (eg tRDRD SC = 1) can imply 0 idle clocks on the data bus. Specifically, the time between commands is 3+n clock cycles, where n is the AMD data bus timing's value.
The reason why tRDWR and tWRRD relies on tCL and tCWL is that they're about session transitions, where there is guaranteed (far) more than one data burst of the same kind (many writes or many reads; no funny mixtures).
tRDWR: delay WRITE by LD such that the write burst happens after the read burst, and delay WRITE even further such that the data bus is stable. The data bus commonly needs 6-7 clocks idle for it to be stable (6-7: when tCL=tCWL tRDWR is 7-8)
I tried tCL 17, tCWL 10, tRDWR 2. This does not boot. I have not tried yeeting tCL to like 23 or higher.

AMD is compressing SC SCL SD DD into a single form for tRDWR and tWRRD. What I don't get is that they don't seem to scale with ranks much at all. Like if on single-rank and SCL can be 2, you'd expect tRDWR to be able do to like 6+LD or something.
I have to guess AMD defines the data bus spacing this way because they probably use burst-chop; AMD does have UMC config options for BC4*. That is, instead of 3+n, it's 1+n.
*(both DDR3 and DDR4 have 8n, so still BL8, BC4. DDR2 has 4n; DDR5 has 16n.)

And what makes the virtual CAS "virtual" has to do with the prefetch architecture for how it looks like for the column address.
I also think Intel has a better way of representing the data bus spacing. This is stupid.

(edit: JEDEC tCCD; tRDWR.
edit2: point 1 wording)


----------



## PJVol

Netblock said:


> The reason why tRDWR and tWRRD relies on tCL and tCWL is that they're about session transitions, where there is guaranteed (far) more than one data burst of the same kind (many writes or many reads; no funny mixtures).


Only tRDWR relies on both tCL and tCWL, tWRRD - derived from tCWL, this is clearly follows from the 2nd graph.

Afaik, BC burst type is not used in amd's DFI. It's part of the DDR4 specs, but not mandatory, and is basically allows using short clock counters.

What seems confusing to me is that calculated tRDWR values perfectly fit standard formula. The same goes for SCLs, read-to-read and write-to-write spacing timings, except this weird tWRRD.
Also tWRRD, unlike the tRDWR, depends on whether successive Read occured in the same or different bank group, hence there's tWTR_S/L in the formula.


----------



## Artylol

The_King said:


> Some interesting AIDA64 numbers. ( No Boost override )
> 4000 CL17 @ 1.48V
> View attachment 2592147
> View attachment 2592148


You can do [email protected] probably. 4000CL16 is a XMP for Patriot Steel 4000. Maybe you can also try to leave voltage and reduce SCL to 2. Otherwise, good observation, I have similar experience with my tests, just not finalized stability on some of the shared profiles. 

In my case 3867CL15 is the best performing in y-cruncher and every other memory intensive benchmark. 3933 probably even better, but requires VDD18 bump to avoid WHEA.


----------



## Netblock

PJVol said:


> Only tRDWR relies on both tCL and tCWL, tWRRD - derived from tCWL, this is clearly follows from the 2nd graph.


Both consider both; tRDWR has +LD and tWRRD has -LD.




PJVol said:


> BC burst type is not used in amd's DFI


Well there are like 3 UMC options in the options tables about it; though there's no discussion over it in the PPR. (17h)



PJVol said:


> What seems confusing to me is that calculated tRDWR values perfectly fit standard formula. The same goes for SCLs, read-to-read and write-to-write spacing timings, except this weird tWRRD.
> Also tWRRD, unlike the tRDWR, depends on whether successive Read occured in the same or different bank group, hence there's tWTR_S/L in the formula.


What I'm looking at for the definition of tWRRD doesn't consider tWTR.

Or is the 'tWRRD' timing is about to a different chipselect (SD/DD), and thus doesn't consider tWTR? I saw in a paper that multi-rank can ignore JEDEC tWTR (fig2 and fig3).
To this degree, does tWRRD below say tCWL+BL/2+tWTR affect performance at all for single-rank?


----------



## The_King

Artylol said:


> You can do [email protected] probably. 4000CL16 is a XMP for Patriot Steel 4000. Maybe you can also try to leave voltage and reduce SCL to 2. Otherwise, good observation, I have similar experience with my tests, just not finalized stability on some of the shared profiles.
> 
> In my case 3867CL15 is the best performing in y-cruncher and every other memory intensive benchmark. 3933 probably even better, but requires VDD18 bump to avoid WHEA.


3933 CL15 is the fastest on my setup in AIDA64 and in other benchmarks without losing performance since I can't adjust VDD18 on this motherboard..

It require +1.2V VSOC and under heavy AVX2 loads increasing 1.15V IOD seems to help keep random WHEA 19s away.


----------



## mikalcarbine

I've been working on my Samsung B-die kit and I was recently able to get to 1900 FCLK without any WHEA errors. 1933 appears to be my brick wall and starts spitting them out at a decent rate. 

The timings below are stable up to 25 cycles of Anta Extreme. I'm trying to get tRCDRD stable at 14 but I'm having no luck. Even 33 MHz past their XMP values (3600 14-14-14-34 @1.45v) and I seem to have issues with tRCDRD at 14. Do any of the pros have any recommendations? @Veii @Blameless @Netblock? If I'm limited by silicon lottery is there anything else you'd recommend tightening? 










Here is their Thaiphoon readout


----------



## Netblock

mikalcarbine said:


> 1933 appears to be my brick wall and starts spitting them out at a decent rate.


In no particular order (worded generically; you already tried a couple of these probably):

Make sure it's actually about the fabric and not the memory preventing booting. Desync the memory to something low (say 3200MT/s) and mess around with FCLK.
Try 1933 or 1966. A major issue is that the PLL multipliers can be catastrophically broken, so moving to a different multiplier might alleviate (58/3 and 59/3 respectively).
Matisse often has a broken 57/3 multiplier, and Vermeer often has broken 58/3 and 59/3 mltipliers; Vermeer can have, though rarely, a broken 57/3.

Raise the 1.8V/PLL voltage. Though comprehensive anecdotes are hard to come by, so I can't say how dangerous doing this would be, so be careful with this.
Furthermore, on many older platforms the 1.8V/PLL rail is also used as the reference voltage for the thermistors (temperature sense), so temperature readouts might might be wacked; though since Zen2, AMD's been throwing LDO regulators left and right, so maybe not anymore?

PLL multipliers: if they all suck, crawl with a BCLK overclock. Keep in mind this also overclocks PCIe, USB, SATA too.
I personally crawl from 56/3 (1866) into 1902.8MHz with a 101.9375MHz BCLK on my Matisse.

Regress your board's firmware to something that has some letter revision of AGESA 1203, as newer AGESAs often don't fix. A major symptom of which is CCD/IOD getting locked to 1 volt and unable to change.
Update to a firmware with AGESA 1207 or newer, as some boards not only have the aforementioned issue fixed, but provides even further stability.
Vermeer's VDDG_CCD often experiences negative voltage scaling when approaching 1.0 volts somewhere after 0.90 volts; it is worth regressing the voltage to somewhere between 0.85 to 0.93 volts.




mikalcarbine said:


> I'm trying to get tRCDRD stable at 14 but I'm having no luck. Even 33 MHz past their XMP values (3600 14-14-14-34 @1.45v) and I seem to have issues with tRCDRD at 14.


tRCDRD 14 at 3600 means 7.8ns, which means a little below 15 at 3800, and a little above 15 at 3866.

For things to try:

your RTT looks wacky--try dis-3-1.
ProcODT might be better higher. Maybe.
What happens with GDM on? You might observe some consequential stability benefit if you aimed for 1T GDM off. Check out this guide.
here's my most recent config


----------



## Artylol

Artylol said:


> I tested 100 cycles of your initial suggestion, no errors.
> 
> 
> What do you mean by that? I should increase RTP to meet a formula? Would not it reduce performance? I will try for sure, but I don't understand reasoning
> 
> 
> Will do and report back
> 
> 
> Again, is that really better than 10, 12 or 14 in your experience even if you can run it twice lower?
> I can reach 94.6% of theoretical DDR4 read speeds, while your setup reaches ~93.6%.
> 
> 
> My understanding is that tRCDWR, and tCWL do not really matter for performance. Probably moreso on single CCD that dual CCD because of IF write bottleneck.
> 
> 
> My understanding that I should lower each one of them step by step, test for stability and also test for performance increase (or decrease for that matter).


@Veii

Here are new trials.
[email protected],46V. It works








SCL=3 does not work, it puts out error#1 after about 20 minutes very consistently (tried 2 times already). It refers to "voltage cutoff choke" I guess this is what it mean. It just not enough voltage/power to perform reads or writes head to head. If I understand correctly only way to solve this is to increase voltage.









tRRDL=4 actually works in preliminary test, will try to test for longer later.


----------



## Netblock

Artylol said:


> [email protected],46V. It works


Does performance change if you yeet tWRRD to register max (but stay below tCWL+4+tWTRS)?


----------



## Blameless

mikalcarbine said:


> I've been working on my Samsung B-die kit and I was recently able to get to 1900 FCLK without any WHEA errors. 1933 appears to be my brick wall and starts spitting them out at a decent rate.
> 
> The timings below are stable up to 25 cycles of Anta Extreme. I'm trying to get tRCDRD stable at 14 but I'm having no luck. Even 33 MHz past their XMP values (3600 14-14-14-34 @1.45v) and I seem to have issues with tRCDRD at 14. Do any of the pros have any recommendations? @Veii @Blameless @Netblock? If I'm limited by silicon lottery is there anything else you'd recommend tightening?
> 
> View attachment 2592434


Not sure there is much you can do to tighten tRCDRD without throwing more voltage at it, but you can probably squeeze a bit more performance out of the kit.

tRTP can probably be tightened a bit more and it might be possible to run T1 with an AddrCmdSetup delay (~56 often works).


----------



## klipschorny

anyone have a download for typhoon that they know is safe?

what can i improve on here? 4x8 ballistix max 4400 rgb c19-19-19-46 i'm trying for 3800mhz with the tightest timings i can manage


----------



## Artylol

Netblock said:


> Does performance change if you yeet tWRRD to register max (but stay below tCWL+4+tWTRS)?


I dont understand what means "below tCWL+4+tWTRS". I set it to 1 which is way below this formula. I get additional 50mb AIDA64 copy bandwidth and a bit faster y-cruncher.


----------



## Netblock

Artylol said:


> I dont understand what means "below tCWL+4+tWTRS". I set it to 1 which is way below this formula. I get additional 50mb AIDA64 copy bandwidth and a bit faster y-cruncher.


What happens if you set it to 15?

Write-to-read operations to the same rank needs to satisfy JEDEC's tWTR for how it works like. That is for the timeline of events,

Dispatch WRITE command
Wait tCWL
Burst the data on the data bus. for DDR4, this means 4 clock cycles.
Wait tWTR (S or L, for wherever the READ command shall be)
Dispatch READ command
This means the READ command is at least like 20 cycles or so later after the WRITE command. So what does AMD's "tWRRD" timing actually mean? I hazard a guess it means rank-to-rank write-to-read. If this is the case then there shouldn't be any performance difference below tCWL+4-3+tWTR

(-3 is derived from AMD's wonky 'last clock of virtual-CAS to CAS' definition (see a few posts earlier)).


----------



## Nd4spdvn

mikalcarbine said:


> I'm trying to get tRCDRD stable at 14 but I'm having no luck.


You may look into a different strategy like upping the CL from 14 to 15 and go with tRCDRD and tRP both 14. tRCDRD is more important than tCL which comes at the very end of all operations. That might still require a little voltage bump but less than keeping flat 14s. It worked for me like this (albeit I run 4 SR DIMMs):










Also, worth switching DIMMs around, binning is real as well as mobo's preferred slots. That may free up some voltage requirements and you may become stable at tRCDRD 14.


----------



## PJVol

The_King said:


> 3933 CL15 is the fastest on my setup in AIDA64 and in other benchmarks without losing performance since I can't adjust VDD18 on this motherboard..


These are ~ year old tests, but anyway looks similar to what my 5600X scored on that mb, might worth a try with the latest agesa ):


----------



## Netblock

klipschorny said:


> anyone have a download for typhoon that they know is safe?


softnology.biz

Though you have micron Rev.E.



klipschorny said:


> what can i improve on here? 4x8 ballistix max 4400 rgb c19-19-19-46 i'm trying for 3800mhz with the tightest timings i can manage
> View attachment 2592484



Most of those timings can come down. I also have Rev.E, here's what I can do.


----------



## The_King

PJVol said:


> These are ~ year old tests, but anyway looks similar to what my 5600X scored on that mb, might worth a try with the latest agesa ):
> View attachment 2592493


Found this going through some old screenshots. My 5600 non X 4650Mhz 50ns


----------



## PJVol

The_King said:


> My 5600 non X 4650Mhz 50ns


tRCD 15 lowers mem latency. I had it around 48.2-48.5 @15, but much higher Vdimm.


Netblock said:


> though there's no discussion over it in the PPR. (17h)


Have you got all volumes (1-3)? I miss the 2nd.


----------



## byDenoso

byDenoso said:


> Hi!
> What Hexi canplay with it?
> 
> When i set BGS ALT do "Enabled (3F8 Hex)" i have less bandwidith than with "Auto", i've tried with 400, 800 and 200 but with no sucess.
> Can you Help me?


Bump
@Veii


----------



## Artylol

Netblock said:


> What happens if you set it to 15?
> 
> Write-to-read operations to the same rank needs to satisfy JEDEC's tWTR for how it works like. That is for the timeline of events,
> 
> Dispatch WRITE command
> Wait tCWL
> Burst the data on the data bus. for DDR4, this means 4 clock cycles.
> Wait tWTR (S or L, for wherever the READ command shall be)
> Dispatch READ command
> This means the READ command is at least like 20 cycles or so later after the WRITE command. So what does AMD's "tWRRD" timing actually mean? I hazard a guess it means rank-to-rank write-to-read. If this is the case then there shouldn't be any performance difference below tCWL+4-3+tWTR
> 
> (-3 is derived from AMD's wonky 'last clock of virtual-CAS to CAS' definition (see a few posts earlier)).


If I set tWRRD from 1 to 15, I lose ~300mb read bandwidth and 150mb copy bandwidth. I think change is the same if I made it equal 2. So only tWRRD=1 makes performance change, values above 1 are equal


----------



## Kaliz

Hello fellow RAM overclockers, just joined the forums!
I am lurking in the forum for some time now and learned a lot already from various posts and screenshots.
I have recently got a Ryzen 5600 stepping B0, new from retailer. It has the1900 fclk hole and anything above 1866 gives WHEA errrors in Ycruncher/ Linpack. 

Above settings are stable in everything but I am wondering if the voltages VDDP and VDDG are too low?


----------



## Imprezzion

Kaliz said:


> View attachment 2592655
> 
> Hello fellow RAM overclockers, just joined the forums!
> I am lurking in the forum for some time now and learned a lot already from various posts and screenshots.
> I have recently got a Ryzen 5600 stepping B0, new from retailer. It has the1900 fclk hole and anything above 1866 gives WHEA errrors in Ycruncher/ Linpack.
> 
> Above settings are stable in everything but I am wondering if the voltages VDDP and VDDG are too low?


CCD is questionable but if it's stable and doesn't degrade performance it's fine. Make sure to do a few memory benches with the low voltage and with like, 1.00v or something just to check for degradation in performance.


----------



## Kaliz

Imprezzion said:


> CCD is questionable but if it's stable and doesn't degrade performance it's fine. Make sure to do a few memory benches with the low voltage and with like, 1.00v or something just to check for degradation in performance.












Just did a short stability test to verify the settings running now. This is my daily profile with PBO and CO. Thanks for the tip on testing with different voltages: CCD 840 880 900 950 1000 1100, can't see much difference in AIDA cache and memory benchmark with higher voltages overall. Tried posting with 700mV VDDP but that was just too little settled with 800. If i go higher fclk i really need those higher voltages but it isnt stable anyway only good for HWBot


----------



## Kaliz

Is this ok to run daily with 102 MHz fsb? Or am i better off setting plain 100 and 56:3 ratio? Asking this because of the higher clockspeed with PBO. 
Is it possible to set the CPU boost override to more than 200MHz? Or is that only on higher end mobo? 
I've seen people setting values like 375 and even saw +600 MHz in a Ryzen Master screenshot. I think it was a cheap B550m Asus board, and it boosted a 5600x to 5025. Is there a list of motherboards which have this extended boost function?


----------



## Frosted racquet

@Kaliz Only older bioses with AGESA 1.0.9.0 had a higher boost override. You're out of luck with a 5600 non-x.


----------



## Kaliz

Frosted racquet said:


> @Kaliz Only older bioses with AGESA 1.0.9.0 had a higher boost override. You're out of luck with a 5600 non-x.


Pretty bummed about this man! Also this chip is golden, it runs 2000 1:1 on 5GHz flawlessly in benchmarks, so it handles higher clocks. Boots 2133 1:1. Benches 5100 etc. But those damn IF whea errors and the 1900 fclk hole. Is this unlucky or maybe AMD didnt optimize its stuff?


----------



## Kaliz

I have found what i was looking for. 



 Clock Tuner for AMD Ryzen CTR (2.1 Beta 5) Download It says i have a PLATINUM sample. ve tried some tweaking and i can get it to boost to 5050 instead of 4650 so very pleased with it.


----------



## The_King

Kaliz said:


> I have found what i was looking for.
> 
> 
> 
> Clock Tuner for AMD Ryzen CTR (2.1 Beta 5) Download It says i have a PLATINUM sample. ve tried some tweaking and i can get it to boost to 5050 instead of 4650 so very pleased with it.


CTR is EOL you should use Hydra. Especially if your CPU is Revision B2.

Hydra has better compatibility with Ryzen B2 than CTR it also has way more features and tons of updates.

In some cases WHEA 19 errors can be resolved by increasing VSOC and IOD voltages.

This post may help.








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


Most 5800X3Ds can do -30 on all cores because they don't run high clock frequencies like 5800X for example. In most cases I have seen almost all 5800X3D can run very stable with -30 all core but its always best to test CO for stability. You can check your scores in R23 with different CO...




www.overclock.net


----------



## Artylol

Okay, So I started receiving WHEA-19 errors in Y-cruncher on profile stable before, which is 1933IF. No amounts of relevant voltage changes do not help, including VDD18. What changed is I nowadays run CPU overclock via PBO (CO-30 fMAX=200). I checked and rechecked multiple times, CPU clock 4200 and below WHEA-19 free, 4300 and above increasingly WHEA-19 prone. Have to add, that there is no WHEA in TM5, Linpack, Prime95. I also know that Y-cruncher uses AVX2 and FMA3. Most likely when switching to one of those instruction sets, I get WHEA-19. FYI: Y-cruncher switches between normal instruction set, AVX2 and FMA3 like 100 times per 1B run (source: use of Hydra)

Has anyone faced common issue?


----------



## The_King

Artylol said:


> Okay, So I started receiving WHEA-19 errors in Y-cruncher on profile stable before, which is 1933IF. No amounts of relevant voltage changes do not help, including VDD18. What changed is I nowadays run CPU overclock via PBO (CO-30 fMAX=200). I checked and rechecked multiple times, CPU clock 4200 and below WHEA-19 free, 4300 and above increasingly WHEA-19 prone. Have to add, that there is no WHEA in TM5, Linpack, Prime95. I also know that Y-cruncher uses AVX2 and FMA3. Most likely when switching to one of those instruction sets, I get WHEA-19. FYI: Y-cruncher switches between normal instruction set, AVX2 and FMA3 like 100 times per 1B run (source: use of Hydra)
> 
> Has anyone faced common issue?
> View attachment 2592914


If you run with CO at 0 do you still get WHEA 19s above 4300?
If not it means your -30 CO is unstable even if it does pass the other tests.

Something to try is play around with LLC modes. It can help with voltage drops under heavy work loads.
For R23 mode 3 works best on my setup and for Y-cruncher mode 2 seems more stable for me.


----------



## Artylol

The_King said:


> If you run with CO at 0 do you still get WHEA 19s above 4300?
> If not it means your -30 CO is unstable even if it does pass the other tests.
> 
> Something to try is play around with LLC modes. It can help with voltage drops under heavy work loads.
> For R23 mode 3 works best on my setup and for Y-cruncher mode 2 seems more stable for me.


Culprit is not CO. It is fully stable at -30. I tested 0, +15, -15, all behave about similarly. I'm using LLC high, but changing it might help. Moreover, I tried running 4500 manual OC with 1,19VCORE, same result.


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## Kaliz

The_King said:


> CTR is EOL you should use Hydra. Especially if your CPU is Revision B2.
> 
> Hydra has better compatibility with Ryzen B2 than CTR it also has way more features and tons of updates.
> 
> In some cases WHEA 19 errors can be resolved by increasing VSOC and IOD voltages.
> 
> This post may help.
> 
> 
> 
> 
> 
> 
> 
> 
> [Official] AMD Ryzen DDR4 24/7 Memory Stability Thread
> 
> 
> Most 5800X3Ds can do -30 on all cores because they don't run high clock frequencies like 5800X for example. In most cases I have seen almost all 5800X3D can run very stable with -30 all core but its always best to test CO for stability. You can check your scores in R23 with different CO...
> 
> 
> 
> 
> www.overclock.net


I have a stepping B0 sample, but gonna check out Hydra, thanks for the tip.

I did up the voltages and have the same results as you in TM5. Stock voltages or lower gives errors, soc to 1,22 and vddp and vddgs all raised does pass TM5, but it will still fail in Linpack or YCruncher. I am really curious if any of your settings shown above 1900 fclk are actually stable in exteme workloads? I mean passing TM5 is easy for me at 1966, but anything above 1866 will give whea errors in Linpack. YCruncher.


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## The_King

Kaliz said:


> I have a stepping B0 sample, but gonna check out Hydra, thanks for the tip.
> 
> I did up the voltages and have the same results as you in TM5. Stock voltages or lower gives errors, soc to 1,22 and vddp and vddgs all raised does pass TM5, but it will still fail in Linpack or YCruncher. I am really curious if any of your settings shown above 1900 fclk are actually stable in exteme workloads? I mean passing TM5 is easy for me at 1966, but anything above 1866 will give whea errors in Linpack. YCruncher.


I have no stability issues running Y-cruncher or Linpack even if FCLK is over 2000.

Can pass OCCT 1 hour stress test as well.








[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread


I think the OCCT test I ran above using P95. Not sure though its shows AVX2 not SSE.. Child's play and not load from my experience... It is just that you have suspiciously high voltage for such test. But yes, it is basically analog for Prime95. I mean impressive for this DRAM data rate, though...




www.overclock.net


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## ReyReverse

Kaliz said:


> I have a stepping B0 sample, but gonna check out Hydra, thanks for the tip.
> 
> I did up the voltages and have the same results as you in TM5. Stock voltages or lower gives errors, soc to 1,22 and vddp and vddgs all raised does pass TM5, but it will still fail in Linpack or YCruncher. I am really curious if any of your settings shown above 1900 fclk are actually stable in exteme workloads? I mean passing TM5 is easy for me at 1966, but anything above 1866 will give whea errors in Linpack. YCruncher.


It depend what kind processor you use, low-end processor 4,6 cores . You probably can sacrifice your all core performance , just play with single core . Set Pbo as low as you can, and tune the best pbo2 CO so your single core can boost higher a little bit. 

But like 12,16 cores this kind of high end processor all core performance is more important than ram speed. That mean you can't restrict your ppt limit too much , under heavy fullload it need more power to maintain high frequency like 4.75ghz 4.85ghz on all core performance. Your single core probably still can hit 4.95Ghz 5.05Ghz.

But there's a problem on those ryzen 9 processor, WHEA problem . You barely can do over fclk 1900 with high PBO setting. ( Of course there's always have some silicon lottery )

Or you can smash 1.8PLL to fix WHEA to maintain your high pbo settings.But that also come with the price CPU degradation, it will kill your CPU slowly ( high soc 1.25v won't kill your CPU or mobo, so far no one have this issue)

Above mentioned High PBO is mean
ppt 300-400
Tdc 250-300
Edc 200-250 <-it depends on your board limit.

Low pbo like

Edc 90-100 .............Or below
Ya, in other way low pbo help save your electric bill 😅

4-6cores processor don't need high pbo
Core power 80-100watt
Soc power 27watt (if 1.2v above)
Ppt 120
Should be enough push all core to the limit


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## Kaliz

Tried 2000 flat 16 again with raised voltages, passed TM5 1usmus but then again I tried ycruncher 2,5B and had 3 whea, have to try it with lower clockspeed on the cpu maybe?

Also installed Hydra 1.3a PRO and ran for over 5 hours Diagnosing the system. 










C01 LIMIT: 4750MHz
C02 LIMIT: 4825MHz
C03 LIMIT: 4750MHz
C04 LIMIT: 4750MHz
C05 LIMIT: 4725MHz
C06 LIMIT: 4700MHz
The process of determining the optimal frequencies is complete!

I dont like the software very much: it took too long to get a result what i already knew. Next time I will try to up the VID voltage to 1,25 because this was at just 1,05V...which was the default setting. Gotta look for a tutorial for this program because it looks promising, still you set -30 and +200 in BIOS for the same effect. I want the extra boost tho!


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## Kaliz

ReyReverse said:


> It depend what kind processor you use, low-end processor 4,6 cores . You probably can sacrifice your all core performance , just play with single core . Set Pbo as low as you can, and tune the best pbo2 CO so your single core can boost higher a little bit.
> 
> 4-6cores processor don't need high pbo
> Core power 80-100watt
> Soc power 27watt (if 1.2v above)
> Ppt 120
> Should be enough push all core to the limit


i just set PBO limits disabled and no scalar no CO only +200 and it passed ycruncher 1B on 2000 just now man ive always had on high powerlimits is this the problem all along? gonna test some more now


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## Kaliz

Now I know why all the XOC guys have to lower the fclk to max 1400... the CPU sucks the juice out of the SOC side. I am trying 4000C15 and it passes Linpack with 78W PPT (stock) but fails on 85W. The max boost is like 4000MHz.


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## ReyReverse

Kaliz said:


> i just set PBO limits disabled and no scalar no CO only +200 and it passed ycruncher 1B on 2000 just now man ive always had on high powerlimits is this the problem all along? gonna test some more now


Set PBO enable and reduce your edc increment by 5 , under heavy load stress test until you see no more WHEA


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## Kaliz

ReyReverse said:


> Set PBO enable and reduce your edc increment by 5 , under heavy load stress test until you see no more WHEA


back to 3733 all previous settings not working with OCCT extreme avx12 cpu test. still whea. ive tried AIDA cache and memory benchmark it scales up to 2066 at 2100 the bandwith plummets. YCruncher is no problem (with enough soc voltage) at 2000 and also passes TM5, but then i tried the heaviest CPU test in OCCT and all failed.


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## Artylol

Kaliz said:


> back to 3733 all previous settings not working with OCCT extreme avx12 cpu test. still whea. ive tried AIDA cache and memory benchmark it scales up to 2066 at 2100 the bandwith plummets. YCruncher is no problem (with enough soc voltage) at 2000 and also passes TM5, but then i tried the heaviest CPU test in OCCT and all failed.


I also have 5600 and above ~78W I get WHEA above 1900IF. I can imagine this be lock from AMD so we don't push lowest part to perform good


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## Kaliz

Artylol said:


> I also have 5600 and above ~78W I get WHEA above 1900IF. I can imagine this be lock from AMD so we don't push lowest part to perform good


I am investigating this now. With PPT TDS EDC at 100 90 100 i can get 1966 to run 1 hour OCCT (avx2 extreme) and YCruncher pi 2,5b without trouble. It boosts up to 4275 MHz effective under load.
Ive tried 2000 with 78W, no problem. Then 90W still ok (boost to 4050MHz) then 110, this didnt pass. I will try diffrent settings but it seems you are right....AMD locking or at least crippling their lower tier parts.


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## Kaliz

my findings so far: all with PBO +200, CO -30 
1)Stock powerlimits(78W, 65A, 90A), runs 4000 stable.
2)adjusted powerlimits (90W, 75A, 105A) up to 3933
3)motherboard powerlimits (150, 125, 150) max 3733

with lower powerlimits the maximum effective boostclock is drasticly lowered in extreme workloads like OCCT Linpack. Ycruncher seems a little bit less affected, CB23 not at all.
1) ~ 4050 MHz
2) ~ 4300 MHz
3) 4650 MHz


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## Kaliz

this is about the maximum Ive gotten so far. I wish this was daily stable, even watching a YT video gives hundreds of whea but sound is good. Anything higher fclk and sound is crackling.


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## Luggage

Kaliz said:


> my findings so far: all with PBO +200, CO -30
> 1)Stock powerlimits(78W, 65A, 90A), runs 4000 stable.
> 2)adjusted powerlimits (90W, 75A, 105A) up to 3933
> 3)motherboard powerlimits (150, 125, 150) max 3733
> 
> with lower powerlimits the maximum effective boostclock is drasticly lowered in extreme workloads like OCCT Linpack. Ycruncher seems a little bit less affected, CB23 not at all.
> 1) ~ 4050 MHz
> 2) ~ 4300 MHz
> 3) 4650 MHz


Never thought about gimping ppt to gain ram speed but I’ve heard some use it if they run hot anyway.

r23 is rather lightweight compared to linx etc… tops out at ~165W no matter what I do on my 5800x.
Linx can pull 200…

With too low limits you will get a lot of clock stretching as well








pbo limits and throttle behavior


Blad1 5800x 3d Mark CPU fmax,ppt,tdc,edc,x,max t,16 t,8 t,4 t,2 t,1 t 5050,250,200,700,10,8265,8257,6497,3815,1948,1004 5050,205,135,170,10,8281,8261,6548,3833,1988,1004 5050,164,100,135,10,8328,8302,6544,3839,1987,1006 5050,135,95,108,10,8233,8271,6531,3853,1988,1005 <a href="https://imgur.com/...




docs.google.com


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## ReyReverse

Kaliz said:


> back to 3733 all previous settings not working with OCCT extreme avx12 cpu test. still whea. ive tried AIDA cache and memory benchmark it scales up to 2066 at 2100 the bandwith plummets. YCruncher is no problem (with enough soc voltage) at 2000 and also passes TM5, but then i tried the heaviest CPU test in OCCT and all failed.


you can't use it to another settings, different EDC different PBO2. example, if I pumb my EDC to 210 on PBO2 CO most of the core can go -30, if I back to 200, maybe only left -27-28. you have to know how many power you need to draw, 4-6 core I guess only need PPT 100





Kaliz said:


> With PPT TDS EDC at 100 90 100 i can get 1966 to run 1 hour OCCT (avx2 extreme) and YCruncher pi 2,5b without trouble. It boosts up to 4275 MHz effective under load.


so seemed this is the best to you. don't worry about all core frequency, just play with your single core.






Kaliz said:


> View attachment 2593158
> View attachment 2593159
> 
> 
> this is about the maximum Ive gotten so far. I wish this was daily stable, even watching a YT video gives hundreds of whea but sound is good. Anything higher fclk and sound is crackling.


if you wish your pc restart randomly 😅


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## Kaliz

Luggage said:


> Never thought about gimping ppt to gain ram speed but I’ve heard some use it if they run hot anyway.


its the fclk which i cannot get stable above 3733 if set maximum ppt, was trying stock ppt 78W that works with 2000 1:1, allthough like you said there is clock stretching in heavy MT workloads. But all WHEA are gone so cant be happier. just discovered this, mostly running max powerlimits before



ReyReverse said:


> you can't use it to another settings, different EDC different PBO2. example, if I pumb my EDC to 210 on PBO2 CO most of the core can go -30, if I back to 200, maybe only left -27-28. you have to know how many power you need to draw, 4-6 core I guess only need PPT 100


this platinum 5600 has pretty good cores and CO -30 is no problem even at 4750, ive tried -20 for core 2 (best cores) and 4 couldnt see anything different. Its locked at 4650.
Trying to make a Hydra 1.3a profile but cant get nice performance out of it without losing the powerlimits.







you can see the rating of the cores the worst Core 5 automatically scales and gets up to 0,155V more then core 2 at 4,775MHz.

















this is stable OCCT, TM5, YCruncher etc! needs some tuning


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## Artylol

Kaliz said:


> its the fclk which i cannot get stable above 3733 if set maximum ppt, was trying stock ppt 78W that works with 2000 1:1, allthough like you said there is clock stretching in heavy MT workloads. But all WHEA are gone so cant be happier. just discovered this, mostly running max powerlimits before
> 
> 
> this platinum 5600 has pretty good cores and CO -30 is no problem even at 4750, ive tried -20 for core 2 (best cores) and 4 couldnt see anything different. Its locked at 4650.
> Trying to make a Hydra 1.3a profile but cant get nice performance out of it without losing the powerlimits.
> View attachment 2593269
> 
> you can see the rating of the cores the worst Core 5 automatically scales and gets up to 0,155V more then core 2 at 4,775MHz.
> 
> View attachment 2593271
> View attachment 2593274
> 
> 
> this is stable OCCT, TM5, YCruncher etc! needs some tuning


I have about the same CPPC, but my chip is "golden" and it boosts up to 4925 on best core and 4900 on worst. I don't use Hydra though... 
My behavior of IF OC is identical to yours, dont even know if it is coincidence of AMD is ****ing with us.











Luggage said:


> ever thought about gimping ppt to gain ram speed but I’ve heard some use it if they run hot anyway.
> 
> r23 is rather lightweight compared to linx etc… tops out at ~165W no matter what I do on my 5800x.
> Linx can pull 200…
> 
> With too low limits you will get a lot of clock stretching as well


What cooler are you using? I can only get 120W out of 6 cores, otherwise overheats on Noctua NH-D15 in a good ventilated case. D15 is about equal to average 240mm AIO


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## Kaliz

Artylol said:


> I have about the same CPPC, but my chip is "golden" and it boosts up to 4925 on best core and 4900 on worst. I don't use Hydra though...
> My behavior of IF OC is identical to yours, dont even know if it is coincidence of AMD is ****ing with us.


i dont use Hydra or CTR, dont like the programs. Its good for setting a all core OC in Windows. but cant think of any situation why you wouldnt do that in BIOS and have actual control of the voltages and loadline etc. 

If I remember correctly AMD was promoting the 4000 1:1 memory OC for 5000 series. Technically we can do it within spec. If set stock CPU clock and stock powerlimits. Maybe AMD did do something with the non X parts though, some kind of powerlimit to prevent it from boosting higher clockspeeds with 2000 fclk without whea. I would do it if i was selling them so cheap.


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## Luggage

Artylol said:


> I have about the same CPPC, but my chip is "golden" and it boosts up to 4925 on best core and 4900 on worst. I don't use Hydra though...
> My behavior of IF OC is identical to yours, dont even know if it is coincidence of AMD is ****ing with us.
> View attachment 2593298
> 
> 
> 
> What cooler are you using? I can only get 120W out of 6 cores, otherwise overheats on Noctua NH-D15 in a good ventilated case. D15 is about equal to average 240mm AIO


This was with water around 0C in a big custom loop and radiator outside.


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## Artylol

Kaliz said:


> i dont use Hydra or CTR, dont like the programs. Its good for setting a all core OC in Windows. but cant think of any situation why you wouldnt do that in BIOS and have actual control of the voltages and loadline etc.


5600 non-x has pitiful boost of 4650MHz, which it can actually do all core. Meaning there is no single core boost. Hydra can do that


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## Kaliz

Artylol said:


> 5600 non-x has pitiful boost of 4650MHz, which it can actually do all core. Meaning there is no single core boost. Hydra can do that


I did a run with 102 bclk and 4004 MHz C15 1:1 in Ryzen Master with higher powerlimits: 95W 75A 120A
result is these CO values. (1) -30 (2) -6 (3) -20 (4) -26 (5)-30 (6) -26
which i set in BIOS. now its boosting to 4750 in CB, Linpack Extreme AVX2 passes with max boost 4400 whea free! and in the CPU test its gets 4500MHz. If i set the powerlimits to 120W 90A 125A i get one whea error in linpack. if i set 108 75 120 i get 0 errors. i get max boost in and gaming with just 90W ppt so i settle on 95W. I have the fclk clock at 1966. for some reason if i set 100 bclk and 2000 fclk i get errors in linpack. This way with 102 bclk i have 100MHz more boost and 4000 is rock stable!! Awesome as of yesterday i didnt know i could get it


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## Kaliz

Artylol said:


> Hydra can do that


i havent figured out how to make a profile with good single core boost. Are you using it? and if so can you make a screenshot of the settings?


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## Artylol

Kaliz said:


> i havent figured out how to make a profile with good single core boost. Are you using it? and if so can you make a screenshot of the settings?


I simply run diagnostic with stock settings, it evaluated all cores with maximum boost of 4925MHz. No screenshot available, I don't use Hydra anymore


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## Kaliz

I just set my multiplier to 47 with the settings i just teted at 1,35v and i beat the number one score on Ycruncher 1B. this is just at 50 mhz more i run daily like ***  can you run a YCruncher pi1B with the 5600? kaliz`s y-cruncher - Pi-1b score: 40sec 96ms with a Ryzen 5 5600


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## Kaliz

Artylol said:


> I simply run diagnostic with stock settings, it evaluated all cores with maximum boost of 4925MHz. No screenshot available, I don't use Hydra anymore


how do you get the 4925 boost? ore are you using the normal 4650 now?


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## Artylol

Kaliz said:


> I just set my multiplier to 47 with the settings i just teted at 1,35v and i beat the number one score on Ycruncher 1B. this is just at 50 mhz more i run daily like ***  can you run a YCruncher pi1B with the 5600? kaliz`s y-cruncher - Pi-1b score: 40sec 96ms with a Ryzen 5 5600


I get 41.7 seconds with PBO instead of staticOC. I'm still finalizing RAM OC, prior to finalizing bench records. Anyway impressive OC. I'm on AIR so 1.25V is absolute maximum, otherwise it overheats


Kaliz said:


> how do you get the 4925 boost? ore are you using the normal 4650 now?


I'm using PBO, so only 4650


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## Kaliz

Artylol said:


> I'm using PBO, so only 4650


may i suggest: set 102 bclk in bios with powerlimits 95 70 110, then run Ryzen Master CO per core test. you will get other values as with 100 bclk. apply those values in bios and then you have 95 MHz more boost and better mem OC. At least thats is my experience. and the last tip i got from other member is higher soc and iod voltage which really helped, and not too tight CL RCD and SCL, the rest can go supertight.


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## Kaliz

i also ran TM5 1usmus preset but forgot that it closes itself when pressing OK. 0 errors.


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## ReyReverse

Kaliz said:


> I did a run with 102 bclk and 4004 MHz C15 1:1 in Ryzen Master with higher powerlimits: 95W 75A 120A
> result is these CO values. (1) -30 (2) -6 (3) -20 (4) -26 (5)-30 (6) -26
> which i set in BIOS. now its boosting to 4750 in CB, Linpack Extreme AVX2 passes with max boost 4400 whea free! and in the CPU test its gets 4500MHz. If i set the powerlimits to 120W 90A 125A i get one whea error in linpack. if i set 108 75 120 i get 0 errors. i get max boost in and gaming with just 90W ppt so i settle on 95W. I have the fclk clock at 1966. for some reason if i set 100 bclk and 2000 fclk i get errors in linpack. This way with 102 bclk i have 100MHz more boost and 4000 is rock stable!! Awesome as of yesterday i didnt know i could get it


this is what I told you, lower your ppt. 4-6 core processor don't need high PBO.


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## Kaliz

just finished OCCT cpu test extreme preset AVX2 with 95W ppt 70A TDC and 110A EDC, thanks for the tip it was this and more soc voltage that pushed me over 3933.


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## ReyReverse

Kaliz said:


> just finished OCCT cpu test extreme preset AVX2 with 95W ppt 70A TDC and 110A EDC, thanks for the tip it was this and more soc voltage that pushed me over 3933.


run the hardest test, OCCT SMALL avx2, then small sse. both run 1 hour


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## Taraquin

Kaliz said:


> i dont use Hydra or CTR, dont like the programs. Its good for setting a all core OC in Windows. but cant think of any situation why you wouldnt do that in BIOS and have actual control of the voltages and loadline etc.
> 
> If I remember correctly AMD was promoting the 4000 1:1 memory OC for 5000 series. Technically we can do it within spec. If set stock CPU clock and stock powerlimits. Maybe AMD did do something with the non X parts though, some kind of powerlimit to prevent it from boosting higher clockspeeds with 2000 fclk without whea. I would do it if i was selling them so cheap.


Frim the data I have gathered the recipe for WHEA19 free above 3800 is 1 ccd and 2 dimm motherboard. Very few are able to get no WGEA19 with 2ccds abd 4dimm MB. My guess is that the simplicity of 1ccd and only 2dimms (way less wiring) reduces the chance of WHEA19. That beibg said, it is usually not worth it to run above 3800 since scaling is poor in several scenarios. You gain some in BW loving ganes like SOTTR and aida,but the best you can hope for is no scaling in linpack, y-cruncher etc and you usuallt have to rause VDD18 voktage which greatly increases temp during load and hence reduces clockspeed.

My WHEA19 free setups using -30 CO (core 1 and 2 -27 and -29) +200 pbo 76W PPT 50A TDC 75A EDC
3800
1.06v SOC
0.98v IOD
0.8v CCD and VDDP
1.6v VDD18 (runs fin 0.2v lower than stock)
SOTTR 1080p lowest CPU 258fps 
aida 53.3
Linpack 273Gflops
Temp CB23 65C

4000
1.12v SOC
1.04v IOD
0.84v CCD and VDDP
1.84v VDD18 at ProcODT 32/1.88v at ProcODT 28
SOTTR 1080p lowest CPU 264fps 
aida 51.7
Linpack 272Gflops
CB23 72C 100points lower

4133
1.2v SOC
1.08v IOD
0.88v CCD and VDDP
1.84v VDD18 at ProcODT 32/1.88v at ProcODT 28
SOTTR 1080p lowest CPU 267fps 
aida 50.5
Linpack 271Gflops
CB23 74C 200points lower score, probably SOC/IOD eating up powerbudget


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## Kaliz

Taraquin said:


> Frim the data I have gathered the recipe for WHEA19 free above 3800 is 1 ccd and 2 dimm motherboard. Very few are able to get no WGEA19 with 2ccds abd 4dimm MB. My guess is that the simplicity of 1ccd and only 2dimms (way less wiring) reduces the chance of WHEA19. That beibg said, it is usually not worth it to run above 3800 since scaling is poor in several scenarios. You gain some in BW loving ganes like SOTTR and aida,but the best you can hope for is no scaling in linpack, y-cruncher etc and you usuallt have to rause VDD18 voktage which greatly increases temp during load and hence reduces clockspeed.
> 
> My WHEA19 free setups using -30 CO (core 1 and 2 -27 and -29) +200 pbo 76W PPT 50A TDC 75A EDC
> 3800
> 1.06v SOC
> 0.98v IOD
> 0.8v CCD and VDDP
> 1.6v VDD18 (runs fin 0.2v lower than stock)
> SOTTR 1080p lowest CPU 258fps
> aida 53.3
> Linpack 273Gflops
> Temp CB23 65C
> 
> 4000
> 1.12v SOC
> 1.04v IOD
> 0.84v CCD and VDDP
> 1.84v VDD18 at ProcODT 32/1.88v at ProcODT 28
> SOTTR 1080p lowest CPU 264fps
> aida 51.7
> Linpack 272Gflops
> CB23 72C 100points lower
> 
> 4133
> 1.2v SOC
> 1.08v IOD
> 0.88v CCD and VDDP
> 1.84v VDD18 at ProcODT 32/1.88v at ProcODT 28
> SOTTR 1080p lowest CPU 267fps
> aida 50.5
> Linpack 271Gflops
> CB23 74C 200points lower score, probably SOC/IOD eating up powerbudget


Thanks for these. How did you find those CO values? I was running -30 all core all along, but i did a Ryzen Master CO per core on 102 bclk so i got other values. which i entered in BIOS. (i do this because for some reason the IF likes 1966 more then 2000 set in BIOS and i get 95MHz more boost). Im really unsure if this is good because the numbers are off by a pretty large margin. (1) -30 (2) -6 (3) -20 (4) -26 (5)-30 (6) -26 

I did up the VDD18 to 1,88v and use 40 procODT for all setups. I have tried lowering procODT on some instable settings to 37 and found it gave some stability but never actually tried further. Not sure how these work so just set them to 40 Ohm as Buildzoid mentioned it was the go to procODT for GigaBYTE b550 boards. Also ive never tried lowering VDD18, as ive heard best is to give it a little more for higher fclk clocks. 

your SOC voltages are pretty low, im gonna try out these procODT values and voltages myself. Also why are you running this low powerlimits? I was testing 78W, 90W, 95W 100W and so on and it seems the mzimum setting before whea/degradation is around 90W. run with 70A tdc and 110A EDC.


----------

